; -------------------------------------------------------------------------------- ; @Title: G9090x On-Chip Peripherals ; @Props: Released ; @Author: JDU ; @Changelog: 2023-05-17 JDU ; @Manufacturer: SemiDrive ; @Doc: Generated (Trace32 Version S.2023.04.000158918M), based on : G9/xml files, ; G9H_Processor_Datasheet_Rev01.00.pdf, G9_Processor_TRM_Rev00.10.pdf ; @Core: Cortex-R5F, Cortex-A55 ; @Chip: G9090* ; @Copyright: (C) 1989-2023 Lauterbach GmbH, licensed for use with TRACE32(R) only ; -------------------------------------------------------------------------------- ; $Id: perg9h.per 17440 2024-02-02 15:33:08Z kwisniewski $ ; KNOWN PROBLEMS ; ETHERNET - All address blocks have same set of offsets in TRM ; DDR_PHY - No information about module in TRM ; LVDS - No information about module in TRM ; MSHC - No information about DWC_mshc_embedded_control and ; DWC_mshc_vendor registers in TRM sif (CORENAME()=="CORTEXR5F") tree "Core Registers (Cortex-R5F)" AUTOINDENT.PUSH AUTOINDENT.OFF width 0x8 ; -------------------------------------------------------------------------------- ; Identification registers ; -------------------------------------------------------------------------------- tree "ID Registers" rgroup.long c15:0x00++0x00 line.long 0x00 "MIDR,Main ID Register" hexmask.long.byte 0x0 24.--31. 0x1 " IMPL ,Implementer code" bitfld.long 0x0 20.--23. " VAR ,Variant" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 16.--19. " ARCH ,Architecture" "Pre-ARMv7,Pre-ARMv7,Pre-ARMv7,Pre-ARMv7,Pre-ARMv7,Pre-ARMv7,Pre-ARMv7,Pre-ARMv7,Pre-ARMv7,Pre-ARMv7,Pre-ARMv7,Pre-ARMv7,Pre-ARMv7,Pre-ARMv7,Pre-ARMv7,ARMv7" textline " " hexmask.long.word 0x0 4.--15. 0x1 " PART ,Primary Part Number" bitfld.long 0x0 0.--3. " REV ,Revision Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rgroup.long c15:0x100++0x00 line.long 0x00 "CTR,Cache Type Register" bitfld.long 0x00 24.--27. " CWG ,Cache Write-back Granule" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x00 20.--23. " ERG ,Exclusives Reservation Granule" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x0 16.--19. " DMINLINE ,D-Cache Minimum Line Size" "1 word,2 words,4 words,8 words,16 words,32 words,64 words,128 words,256 words,512 words,1024 words,2048 words,4096 words,8192 words,16384 words,32768 words" bitfld.long 0x0 14.--15. " L1POLICY ,L1 Instruction cache policy" "Reserved,ASID,Virtual,Physical" textline " " bitfld.long 0x0 0.--3. " IMINLINE ,I-Cache Minimum Line Size" "1 word,2 words,4 words,8 words,16 words,32 words,64 words,128 words,256 words,512 words,1024 words,2048 words,4096 words,8192 words,16384 words,32768 words" rgroup.long c15:0x400--0x400 line.long 0x0 "MPUIR,MPU type register" hexmask.long.byte 0x00 8.--15. 1. " REGNUM ,Number of regions" bitfld.long 0x00 0. " TYPE ,Type of MPU regions" "Unified,Seperated" rgroup.long c15:0x500++0x00 line.long 0x0 "MPIDR,Multiprocessor Affinity Register" bitfld.long 0x00 30.--31. " MULT_EXT ,Multiprocessing extensions" "No extensions,Reserved,Reserved,Part of a uniprocessor system" textline " " hexmask.long.byte 0x00 16.--23. 1. " AFFL2 ,Affitnity Level 2" hexmask.long.byte 0x00 8.--15. 1. " AFFL1 ,Affitnity Level 1" hexmask.long.byte 0x00 0.--7. 1. " AFFL0 ,Affitnity Level 0" textline " " rgroup.long c15:0x0410++0x00 line.long 0x00 "MMFR0,Memory Model Feature Register 0" bitfld.long 0x00 28.--31. " IT ,Instruction Type Support" "Reserved,Reserved,Reserved,Supported,?..." bitfld.long 0x00 24.--27. " FCSE ,Fast Context Switch Memory Mappings Support" "Reserved,Supported,?..." textline " " bitfld.long 0x00 20.--23. " ACR ,Auxiliary Control Register Support" "Reserved,Supported,?..." bitfld.long 0x00 16.--19. " TCM ,TCM and Associated DMA Support" "Not supported,?..." textline " " bitfld.long 0x00 12.--15. " SL ,Number of Shareability levels implemented" "1,?..." bitfld.long 0x00 8.--11. " OS ,Outermost Shareability domain support" "Supported,?..." textline " " bitfld.long 0x00 4.--7. " PMSA ,Physical Memory System Architecture (PMSA) Support" "Not supported,?..." bitfld.long 0x00 0.--3. " VMSA ,Virtual Memory System Architecture (VMSA) Support" "Reserved,Reserved,Reserved,Supported,?..." rgroup.long c15:0x0510++0x00 line.long 0x00 "MMFR1,Memory Model Feature Register 1" bitfld.long 0x00 28.--31. " BTB ,Branch Target Buffer Support" "Reserved,Reserved,Not required,?..." bitfld.long 0x00 24.--27. " L1TCO ,Test and Clean Operations on Data Cache/Harvard/Unified Architecture Support" "Not supported,?..." textline " " bitfld.long 0x00 20.--23. " L1UCMO ,L1 Cache/All Maintenance Operations/Unified Architecture Support" "Not supported,?..." bitfld.long 0x00 16.--19. " L1HCMO ,L1 Cache/All Maintenance Operations/Harvard Architecture Support" "Supported,?..." textline " " bitfld.long 0x00 12.--15. " L1UCLMOSW ,L1 Cache Line Maintenance Operations by Set and Way/Unified Architecture Support" "Not supported,?..." bitfld.long 0x00 8.--11. " L1HCLMOSW ,L1 Cache Line Maintenance Operations by Set and Way/Harvard Architecture Support" "Supported,?..." textline " " bitfld.long 0x00 4.--7. " L1UCLMOMVA ,L1 Cache Line Maintenance Operations by MVA/Unified Architecture Support" "Not supported,?..." bitfld.long 0x00 0.--3. " L1HCLMOMVA ,L1 Cache Line Maintenance Operations by MVA/Harvard Architecture" "Supported,?..." rgroup.long c15:0x0610++0x00 line.long 0x00 "MMFR2,Memory Model Feature Register 2" bitfld.long 0x00 28.--31. " HAF ,Hardware Access Flag Support" "Not supported,?..." bitfld.long 0x00 24.--27. " WFI ,Wait for Interrupt Stalling Support" "Reserved,Supported,?..." textline " " bitfld.long 0x00 20.--23. " MBF ,Memory Barrier Operations Support" "Reserved,Reserved,Supported,?..." bitfld.long 0x00 16.--19. " UTLBMO ,TLB Maintenance Operations/Unified Architecture Support" "Not supported,?..." textline " " bitfld.long 0x00 12.--15. " HTLBMO ,TLB Maintenance Operations/Harvard Architecture Support" "Reserved,Reserved,Supported,?..." bitfld.long 0x00 8.--11. " HL1CMRO ,Cache Maintenance Range Operations/Harvard Architecture Support" "Not supported,?..." textline " " bitfld.long 0x00 4.--7. " HL1BPCRO ,Background Prefetch Cache Range Operations/Harvard Architecture Support" "Not supported,?..." bitfld.long 0x00 0.--3. " HL1FPCRO ,Foreground Prefetch Cache Range Operations/Harvard Architecture Support" "Not supported,?..." rgroup.long c15:0x0710++0x00 line.long 0x00 "MMFR3,Memory Model Feature Register 3" bitfld.long 0x00 28.--31. " SS ,Supersection support" "Supported,?..." bitfld.long 0x00 20.--23. " CW ,Coherent walk" "Supported,?..." textline " " bitfld.long 0x00 12.--15. " MB ,Invalidate broadcast Support" "Reserved,Reserved,Supported,?..." textline " " bitfld.long 0x00 4.--7. " HCMOSW ,Invalidate Cache by Set and Way/Clean by Set and Way/Invalidate and Clean by Set and Way Support" "Reserved,Supported,?..." bitfld.long 0x00 0.--3. " HCMOMVA ,Invalidate Cache by MVA/Clean by MVA/Invalidate and Clean by MVA/Invalidate All Support" "Reserved,Supported,?..." rgroup.long c15:0x020++0x00 line.long 0x00 "ISAR0,Instruction Set Attributes Register 0" bitfld.long 0x00 24.--27. " DIVI ,Divide Instructions Support" "Not supported,?..." bitfld.long 0x00 20.--23. " DEBI ,Debug Instructions Support" "Reserved,Supported,?..." textline " " bitfld.long 0x00 16.--19. " CI ,Coprocessor Instructions Support" "Not supported,?..." bitfld.long 0x00 12.--15. " CBI ,Combined Compare and Branch Instructions Support" "Reserved,Supported,?..." textline " " bitfld.long 0x00 8.--11. " BI ,Bitfield Instructions Support" "Reserved,Supported,?..." bitfld.long 0x00 4.--7. " BCI ,Bit Counting Instructions Support" "Reserved,Supported,?..." textline " " bitfld.long 0x00 0.--3. " SI ,Swap Instructions Support" "Reserved,Supported,?..." rgroup.long c15:0x120++0x00 line.long 0x00 "ISAR1,Instruction Set Attributes Register 1" bitfld.long 0x00 28.--31. " JI ,Jazelle Instructions Support" "Reserved,Supported,?..." bitfld.long 0x00 24.--27. " INTI ,Instructions That Branch Between ARM and Thumb Code Support" "Reserved,Reserved,Supported,?..." textline " " bitfld.long 0x00 20.--23. " IMMI ,Immediate Instructions Support" "Reserved,Supported,?..." bitfld.long 0x00 16.--19. " ITEI ,If Then Instructions Support" "Reserved,Supported,?..." textline " " bitfld.long 0x00 12.--15. " EXTI ,Sign or Zero Extend Instructions Support" "Reserved,Reserved,Supported,?..." bitfld.long 0x00 8.--11. " E2I ,Exception 2 Instructions Support" "Reserved,Supported,?..." textline " " bitfld.long 0x00 4.--7. " E1I ,Exception 1 Instructions Support" "Reserved,Supported,?..." bitfld.long 0x00 0.--3. " ENDI ,Endianness Control Instructions Support" "Reserved,Supported,?..." rgroup.long c15:0x220++0x00 line.long 0x00 "ISAR2,Instruction Set Attributes Register 2" bitfld.long 0x00 28.--31. " RI ,Reversal Instructions Support" "Reserved,Reserved,Supported,?..." bitfld.long 0x00 24.--27. " PSRI ,PSR Instructions Support" "Reserved,Supported,?..." textline " " bitfld.long 0x00 20.--23. " UMI ,Advanced Unsigned Multiply Instructions Support" "Reserved,Reserved,Supported,?..." bitfld.long 0x00 16.--19. " SMI ,Advanced Signed Multiply Instructions Support" "Reserved,Reserved,Reserved,Supported,?..." textline " " bitfld.long 0x00 12.--15. " MI ,Multiply Instructions Support" "Reserved,Reserved,Supported,?..." bitfld.long 0x00 8.--11. " II ,Multi-Access Interruptible Instructions Support" "Supported,?..." textline " " bitfld.long 0x00 4.--7. " MHI ,Memory Hint Instructions Support" "Reserved,Reserved,Reserved,Supported,?..." bitfld.long 0x00 0.--3. " LSI ,Load and Store Instructions Support" "Reserved,Supported,?..." rgroup.long c15:0x320++0x00 line.long 0x00 "ISAR3,Instruction Set Attributes Register 3" bitfld.long 0x00 28.--31. " T2E ,Thumb-2 Extensions Support" "Reserved,Supported,?..." bitfld.long 0x00 24.--27. " NOPI ,True NOP Instructions Support" "Reserved,Supported,?..." textline " " bitfld.long 0x00 20.--23. " TCI ,Thumb Copy Instructions Support" "Reserved,Supported,?..." bitfld.long 0x00 16.--19. " TBI ,Table Branch Instructions Support" "Reserved,Reserved,Supported,?..." textline " " bitfld.long 0x00 12.--15. " SPI ,Synchronization Primitive Instructions Support" "Reserved,Reserved,Supported,?..." bitfld.long 0x00 8.--11. " SVCI ,SVC Instructions Support" "Reserved,Supported,?..." textline " " bitfld.long 0x00 4.--7. " SIMDI ,Single Instruction Multiple Data (SIMD) Instructions Support" "Reserved,Reserved,Reserved,Supported,?..." bitfld.long 0x00 0.--3. " SI ,Saturate Instructions Support" "Reserved,Supported,?..." rgroup.long c15:0x420++0x00 line.long 0x00 "ISAR4,Instruction Set Attributes Register 4" bitfld.long 0x00 28.--31. " SWP_FRAC ,SWAP_frac" "Supported,?..." bitfld.long 0x00 24.--27. " PSR_M_I ,PSR_M Instructions Support" "Not supported,?..." textline " " bitfld.long 0x00 20.--23. " EI ,Exclusive Instructions Support" "Reserved,Supported,?..." bitfld.long 0x00 16.--19. " BI ,Barrier Instructions Support" "Reserved,Supported,?..." textline " " bitfld.long 0x00 12.--15. " SMII ,SMI Instructions Support" "Reserved,Supported,?..." bitfld.long 0x00 8.--11. " WBI ,Write-Back Instructions Support" "Reserved,Supported,?..." textline " " bitfld.long 0x00 4.--7. " WSI ,With-Shift Instructions Support" "Reserved,Reserved,Reserved,Reserved,Supported,?..." bitfld.long 0x00 0.--3. " UI ,Unprivileged Instructions Support" "Reserved,Reserved,Supported,?..." rgroup.long c15:0x0520++0x00 line.long 0x00 "ISAR5,Instruction Set Attribute Registers 5 (Reserved)" rgroup.long c15:0x0620++0x00 line.long 0x00 "ISAR6,Instruction Set Attribute Registers 6 (Reserved)" rgroup.long c15:0x0720++0x00 line.long 0x00 "ISAR7,Instruction Set Attribute Registers 7 (Reserved)" rgroup.long c15:0x010++0x00 line.long 0x00 "ID_PFR0,Processor Feature Register 0" bitfld.long 0x00 12.--15. " STATE3 ,Thumb-2 Execution Environment (Thumb-2EE) Support" "Reserved,Supported,?..." bitfld.long 0x00 8.--11. " STATE2 ,Java Extension Interface Support" "Not supported,?..." bitfld.long 0x00 4.--7. " STATE1 ,Thumb Encoding Supported by the Processor Type" "Reserved,Reserved,Reserved,Supported,?..." textline " " bitfld.long 0x00 0.--3. " STATE0 ,ARM Instruction Set Support" "Reserved,Supported,?..." rgroup.long c15:0x110++0x00 line.long 0x00 "ID_PFR1,Processor Feature Register 1" bitfld.long 0x00 8.--11. " MPM ,Microcontroller Programmer's Model Support" "Supported,?..." bitfld.long 0x00 4.--7. " SE ,Security Extensions Architecture v1 Support" "Reserved,Supported,?..." bitfld.long 0x00 0.--3. " PM ,Standard ARMv4 Programmer's Model Support" "Reserved,Supported,?..." textline " " rgroup.long c15:0x210++0x00 line.long 0x00 "ID_DFR0,Debug Feature Register 0" bitfld.long 0x00 20.--23. " MDM_MM ,Microcontroller Debug Model Support" "Not supported,?..." bitfld.long 0x00 16.--19. " TDM_MM ,Trace Debug Model (Memory-Mapped) Support" "Reserved,Supported,?..." bitfld.long 0x00 12.--15. " TDM_CB ,Coprocessor-Based Trace Debug Model Support" "Not supported,?..." textline " " bitfld.long 0x00 8.--11. " CDM_MM ,Memory-Mapped Debug Model Support" "Reserved,Reserved,Reserved,Reserved,Supported,?..." bitfld.long 0x00 4.--7. " SDM_CB ,Secure Debug Model (Coprocessor) Support" "Not supported,?..." bitfld.long 0x00 0.--3. " CDM_CB ,Coprocessor Debug Model Support" "Not supported,?..." rgroup.long c15:0x310++0x00 line.long 0x00 "ID_AFR0,Auxiliary Feature Register 0" rgroup.long c15:0x02f++0x00 line.long 0x00 "BO1R,Build Options 1 Register" hexmask.long.long 0x00 12.--31. 0x1000 " TCM_HI_INIT_ADDR ,Default high address for the TCM" bitfld.long 0x00 1. " FLOAT_PRECISION ,Indicate whether double-precision floating point is implemented" "Not implemented,Implemented" textline " " bitfld.long 0x00 0. " PP_BUS_ECC ,Indicate whether bus-ECC is implemented" "Not implemented,Implemented" group.long c15:0x12f++0x00 line.long 0x00 "BO2R,Build Options 2 Register" bitfld.long 0x00 31. " NUM_CPU ,Number of CPUs" "1,2" bitfld.long 0x00 30. " LOCK_STEP ,Indicate whether the CPU has redundant logic running in lock step for checking purposes" "Not included,Included" textline " " bitfld.long 0x00 29. " NO_ICACHE ,Indicate whether the CPU contains instruction cache" "Yes,No" bitfld.long 0x00 28. " NO_DCACHE ,Indicate whether the CPU contains data cache" "Yes,No" textline " " bitfld.long 0x00 26.--27. " ATCM_ES ,Indicate whether an error scheme is implemented on the ATCM interface" "No error scheme,32 bit error detection,Reserved,64 bit error detection" bitfld.long 0x00 23.--25. " BTCM_ES ,Indicate whether an error scheme is implemented on the BTCM interface" "No error scheme,32 bit error detection,Reserved,64 bit error detection,?..." textline " " bitfld.long 0x00 23. " NO_IE ,Indicate whether the processor supports big-endian instructions" "Yes,No" bitfld.long 0x00 22. " NO_FPU ,Indicate whether the CPU contains a floating point unit" "Yes,No" textline " " bitfld.long 0x00 20.--21. " MPU_REGIONS ,Indicates the number of regions in the included CPU MPU" "No region,Reserved,12 regions,16 regions" bitfld.long 0x00 17.--19. " BREAK_POINTS ,Indicate the number of break points implemented in each CPU in the processor minus 1" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 14.--16. " WATCH_POINTS ,Indicate the number of watch points implemented in each CPU in the processor minus 1" "0,1,2,3,4,5,6,7" bitfld.long 0x00 13. " NO_A_TCM_INF ,Indicate whether the CPUs contain ATCM ports" "Yes,No" textline " " bitfld.long 0x00 12. " NO_B0_TCM_INF ,Indicate whether the CPUs contain B0TCM ports" "Yes,No" bitfld.long 0x00 11. " NO_B1_TCM_INF ,Indicate whether the CPUs contain B1TCM ports" "Yes,No" textline " " bitfld.long 0x00 10. " TCMBUSPARITY ,Indicate whether the processor contains TCM address bus parity logic" "No,Yes" bitfld.long 0x00 9. " NO_SLAVE ,Indicate whether the CPU contains an AXI slave port" "Yes,No" textline " " bitfld.long 0x00 7.--8. " ICACHE_ES ,Indicate whether an error scheme is implemented for the instruction cache" "No error scheme,8-bit parity,Reserved,64-bit ECC" bitfld.long 0x00 5.--6. " DCACHE_ES ,Indicate whether an error scheme is implemented for the data cache" "No error scheme,8-bit parity,32-bit ECC,?..." textline " " bitfld.long 0x00 4. " NO_HARD_ERROR_CACHE ,Indicate whether the processor contains cache for corrected TCM errors" "Yes,No" bitfld.long 0x00 3. " AXI_BUS_ECC ,Indicate whether the processor contains AXI bus ECC logic" "No,Yes" textline " " bitfld.long 0x00 2. " SL ,Indicate whether the processor has been built with split/lock logic" "No,Yes" bitfld.long 0x00 1. " AHB_PP ,Indicate whether the CPU contain AHB peripheral interfaces" "No,Yes" textline " " bitfld.long 0x00 0. " MICRO_SCU ,Indicate whether the processor contain an ACP interface" "No,Yes" group.long c15:0x72f++0x00 line.long 0x00 "POR,Pin Options Register" bitfld.long 0x00 4. " DBGNOCLKSTOP ,Value of the DBGNOCLKSTOP pin" "Low,High" bitfld.long 0x00 3. " INTSYNCEN ,Value of the INTSYNCEN pin" "Low,High" textline " " bitfld.long 0x00 2. " IRQADDRVSYNCEN ,Value of the IRQADDRVSYNCEN pin" "Low,High" bitfld.long 0x00 1. " SLBTCMSB ,Value of the SLBTCMSBm pin" "Low,High" textline " " bitfld.long 0x00 0. " PARITYLEVEL ,Value of the PARITYLEVEL pin" "Low,High" tree.end width 0x8 tree "System Control and Configuration" group.long c15:0x01++0x00 line.long 0x00 "SCTLR,Control Register" bitfld.long 0x0 31. " IE ,Instruction endianness" "Little,Big" bitfld.long 0x0 30. " TE ,Thumb exception enable" "ARM,Thumb" bitfld.long 0x0 29. " AFE ,Access Flag Enable" "Disable,Enable" bitfld.long 0x0 28. " TRE ,TEX remap enable" "Disable,Enable" bitfld.long 0x0 27. " NMFI ,Nonmaskable Fast Interrupt enable" "Disable,Enable" textline " " bitfld.long 0x0 25. " EE ,Exception endianess" "Little,Big" bitfld.long 0x0 24. " VE ,Vector Enable" "Disable,Vectored" bitfld.long 0x0 21. " FI ,Fast Interrupts enable" "Disable,Enable" textline " " bitfld.long 0x0 19. " DZ ,Divide by Zero exception bit" "Disable,Enable" bitfld.long 0x0 17. " BR ,MPU Background region enable" "Disable,Enable" bitfld.long 0x0 14. " RR ,Round-Robin bit" "Random,RRobin" bitfld.long 0x0 13. " V ,Base Location of Exception Registers" "0x00000000,0xFFFF0000" textline " " bitfld.long 0x0 12. " I ,Instruction Cache Enable" "Disable,Enable" bitfld.long 0x0 11. " Z ,Branch Prediction Enable" "Disable,Enable" bitfld.long 0x0 2. " C ,Enable data cache" "Disable,Enable" bitfld.long 0x0 1. " A ,Strict Alignment" "Disable,Enable" bitfld.long 0x0 0. " M ,MPU Enable" "Disable,Enable" textline " " group.long c15:0x101++0x00 line.long 0x0 "ACTLR,Auxiliary Control Register" bitfld.long 0x00 31. " DICDI ,Disable Case C dual issue control" "Enable,Disable" bitfld.long 0x00 30. " DIB2DI ,Disable Case B2 dual issue control" "Enable,Disable" bitfld.long 0x00 29. " DIB1DI ,Disable Case B1 dual issue control" "Enable,Disable" textline " " bitfld.long 0x00 28. " DIADI ,Disable Case A dual issue control" "Enable,Disable" bitfld.long 0x00 27. " B1TCMPCEN ,B1TCM parity or ECC check enable" "Disable,Enable" bitfld.long 0x00 26. " B0TCMPCEN ,B1TCM parity or ECC check enable" "Disable,Enable" textline " " bitfld.long 0x00 25. " ATCMPCEN ,B1TCM parity or ECC check enable" "Disable,Enable" bitfld.long 0x00 24. " AXISCEN ,AXI slave cache access enable" "Disable,Enable" bitfld.long 0x00 23. " AXISCUEN ,AXI slave cache User mode access enable" "Disable,Enable" textline " " bitfld.long 0x00 22. " DILSM ,Disable LIL on load/store multiples" "Enable,Disable" bitfld.long 0x00 21. " DEOLP ,Disable end of loop prediction" "Enable,Disable" bitfld.long 0x00 20. " DBHE ,Disable BH extension" "Enable,Disable" textline " " bitfld.long 0x00 19. " FRCDIS ,Fetch rate control disable" "Enable,Disable" bitfld.long 0x00 17. " RSDIS ,Return stack disable" "Enable,Disable" bitfld.long 0x00 15.--16. " BP ,Control of the branch prediction policy" "Normal,Taken,Not taken,?..." textline " " bitfld.long 0x00 14. " DBWR ,Disable write_burst on AXI master" "Enable,Disable" bitfld.long 0x00 13. " DLFO ,Disable linefill optimization in the AXI master" "Enable,Disable" bitfld.long 0x00 12. " ERPEG ,Enable random parity error generation" "Disable,Enable" textline " " bitfld.long 0x00 11. " DNCH ,Disable data forwarding for Non-cacheable accesses in the AXI master" "Enable,Disable" bitfld.long 0x00 10. " FORA ,Force outer read allocate (ORA) for outer write allocate (OWA) regions" "Not forced,Forced" bitfld.long 0x00 9. " FWT ,Force write-through (WT) for write-back (WB) regions" "Not forced,Forced" textline " " bitfld.long 0x00 8. " FDSnS ,Force D-side to not-shared when MPU is off" "Not forced,Forced" bitfld.long 0x00 7. " SMOV ,sMOV disabled" "Enabled,Disabled" bitfld.long 0x0 6. " DILS ,Disable low interrupt latency on all load/store instructions" "Enable,Disable" textline " " bitfld.long 0x00 3.--5. " CEC ,Cache error control for cache parity and ECC errors" "Generate abort,Generate abort,Generate abort,Reserved,Disabled parity checking,Not generate abort,Not generate abort,?..." textline " " bitfld.long 0x00 2. " B1TCMECEN ,B1TCM external error enable" "Disable,Enable" bitfld.long 0x00 1. " B0TCMECEN ,B0TCM external error enable" "Disable,Enable" bitfld.long 0x00 0. " ATCMECEN ,ATCM external error enable" "Disable,Enable" textline " " group.long c15:0x0f++0x00 line.long 0x00 "SACTLR,Secondary Auxiliary Control Register" bitfld.long 0x00 22. " DCHE ,Disable hard-error support in the caches" "Enable,Disable" bitfld.long 0x00 21. " DR2B ,Enable random 2-bit error genration in cache RAMs" "Disable,Enable" bitfld.long 0x00 20. " DF6DI ,F6 dual issue control" "Enable,Disable" textline " " bitfld.long 0x00 19. " DF2DI ,F2 dual issue control" "Enable,Disable" bitfld.long 0x00 18. " DDI ,F1/F3/F4 dual issue control" "Enable,Disable" bitfld.long 0x00 17. " DOODPFP ,Out-of-order Double Precision Floating-point control" "Enable,Disable" textline " " bitfld.long 0x00 16. " DOOFMACS ,Out-of-order FMACS control" "Enable,Disable" bitfld.long 0x00 13. " IXC ,Floating-point inexact exception output mask" "Mask,Propagate" bitfld.long 0x00 12. " OFC ,Floating-point overflow exception output mask" "Mask,Propagate" textline " " bitfld.long 0x00 11. " UFC ,Floating-point underflow exception output mask" "Mask,Propagate" bitfld.long 0x00 10. " IOC ,Floating-point invalid operation exception output mask" "Mask,Propagate" bitfld.long 0x00 9. " DZC ,Floating-point divide-by-zero exception output mask" "Mask,Propagate" textline " " bitfld.long 0x00 8. " IDC ,Floating-point input denormal exception output mask" "Mask,Propagate" bitfld.long 0x00 3. " BTCMECC ,Correction for internal ECC logic on BTCM ports" "Enable,Disable" bitfld.long 0x00 2. " ATCMECC ,Correction for internal ECC logic on ATCM port" "Enable,Disable" textline " " bitfld.long 0x00 1. " BTCMRMW ,Enable 64-bit stores on BTCMs" "Disable,Enable" bitfld.long 0x00 0. " ATCMRMW ,Enable 64-bit stores on ATCM" "Disable,Enable" textline " " group.long c15:0x201++0x00 line.long 0x0 "CPACR,Coprocessor Access Control Register" bitfld.long 0x0 31. " ASEDIS ,Disable Advanced SIMD Extension functionality" "No,Yes" bitfld.long 0x0 30. " D32DIS ,Disable use of D16-D31 of the VFP register file" "No,Yes" textline " " bitfld.long 0x0 26.--27. " CP13 ,Coprocesor access control" "Denied,Privileged,Reserved,Full" bitfld.long 0x0 24.--25. " CP12 ,Coprocesor access control" "Denied,Privileged,Reserved,Full" textline " " bitfld.long 0x0 22.--23. " CP11 ,Coprocesor access control" "Denied,Privileged,Reserved,Full" bitfld.long 0x0 20.--21. " CP10 ,Coprocesor access control" "Denied,Privileged,Reserved,Full" textline " " bitfld.long 0x0 18.--19. " CP9 ,Coprocesor access control" "Denied,Privileged,Reserved,Full" bitfld.long 0x0 16.--17. " CP8 ,Coprocesor access control" "Denied,Privileged,Reserved,Full" textline " " bitfld.long 0x0 14.--15. " CP7 ,Coprocesor access control" "Denied,Privileged,Reserved,Full" bitfld.long 0x0 12.--13. " CP6 ,Coprocesor access control" "Denied,Privileged,Reserved,Full" textline " " bitfld.long 0x0 10.--11. " CP5 ,Coprocesor access control" "Denied,Privileged,Reserved,Full" bitfld.long 0x0 8.--9. " CP4 ,Coprocesor access control" "Denied,Privileged,Reserved,Full" textline " " bitfld.long 0x0 6.--7. " CP3 ,Coprocesor access control" "Denied,Privileged,Reserved,Full" bitfld.long 0x0 4.--5. " CP2 ,Coprocesor access control" "Denied,Privileged,Reserved,Full" textline " " bitfld.long 0x0 2.--3. " CP1 ,Coprocesor access control" "Denied,Privileged,Reserved,Full" bitfld.long 0x0 0.--1. " CP0 ,Coprocesor access control" "Denied,Privileged,Reserved,Full" textline " " group.long c15:0x000b++0x00 line.long 0x00 "SPCR,Slave Port Control Register" bitfld.long 0x00 1. " PRIV ,Privilege access only" "User/Privilege,Privilege only" bitfld.long 0x00 0. " AXISLEN ,AXI slave port disable" "Enabled,Disabled" tree.end width 0x8 tree "MPU Control and Configuration" group.long c15:0x01++0x00 line.long 0x00 "SCTLR,Control Register" bitfld.long 0x0 31. " IE ,Instruction endianness" "Little,Big" bitfld.long 0x0 30. " TE ,Thumb exception enable" "ARM,Thumb" bitfld.long 0x0 29. " AFE ,Access Flag Enable" "Disable,Enable" bitfld.long 0x0 28. " TRE ,TEX remap enable" "Disable,Enable" bitfld.long 0x0 27. " NMFI ,Nonmaskable Fast Interrupt enable" "Disable,Enable" textline " " bitfld.long 0x0 25. " EE ,Exception endianess" "Little,Big" bitfld.long 0x0 24. " VE ,Vector Enable" "Disable,Vectored" bitfld.long 0x0 21. " FI ,Fast Interrupts enable" "Disable,Enable" textline " " bitfld.long 0x0 19. " DZ ,Divide by Zero exception bit" "Disable,Enable" bitfld.long 0x0 17. " BR ,MPU Background region enable" "Disable,Enable" bitfld.long 0x0 14. " RR ,Round-Robin bit" "Random,RRobin" bitfld.long 0x0 13. " V ,Base Location of Exception Registers" "0x00000000,0xFFFF0000" textline " " bitfld.long 0x0 12. " I ,Instruction Cache Enable" "Disable,Enable" bitfld.long 0x0 11. " Z ,Branch Prediction Enable" "Disable,Enable" bitfld.long 0x0 2. " C ,Enable data cache" "Disable,Enable" bitfld.long 0x0 1. " A ,Strict Alignment" "Disable,Enable" bitfld.long 0x0 0. " M ,MPU Enable" "Disable,Enable" textline " " group.long c15:0x05++0x00 line.long 0x00 "DFSR,Data Fault Status Register" bitfld.long 0x00 12. " EXT ,External Abort Qualifier" "DECERR,SLVERR" bitfld.long 0x00 11. " RW ,Access Caused an Abort Type" "Read,Write" textline " " bitfld.long 0x00 4.--7. " DOMAIN ,Domain Accessed When a Data Fault Occurs" "D0,D1,D2,D3,D4,D5,D6,D7,D8,D9,D10,D11,D12,D13,D14,D15" bitfld.long 0x00 0.--3. 10. " STATUS ,Generated Exception Type" "Reserved,Alignment,Debug,Access/section,Instruction,Translation/section,Access/page,Translation/page,Nontranslation/synchronous external,Domain/section,Reserved,Domain/page,L1/external,Permission/section,L2/external,Permission/page,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Asynchronous external,?..." group.long c15:0x15++0x00 line.long 0x00 "ADFSR,Auxiliary Data Fault Status Register" bitfld.long 0x00 24.--27. " CACHEWAY ,Cache way or ways in which the error occurred" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 22.--23. 20. " SIDE ,Source of the error" "Cache/AXIM,ATCM,BTCM,Reserved,Reserved,AXI,AHB,Reserved" textline " " bitfld.long 0x00 21. " REC_ERR ,Error recoverability indication" "Not recoverable,Recoverable" bitfld.long 0x00 20. " SIDE_EXT ,Source of the error" "Internal,External" textline " " hexmask.long.word 0x00 5.--13. 1. " INDEX ,Index Value for The Access Giving the Error Register" group.long c15:0x06++0x00 line.long 0x00 "DFAR,Data Fault Address Register" textline " " group.long c15:0x0105++0x00 line.long 0x00 "IFSR,Instruction Fault Status Register" bitfld.long 0x00 12. " EXT ,External Abort Qualifier" "DECERR,SLVERR" bitfld.long 0x00 0.--3. 10. " STATUS ,Generated Exception Type" "Reserved,Alignment,Debug,Access/section,Instruction,Translation/section,Access/page,Translation/page,Nontranslation/synchronous external,Domain/section,Reserved,Domain/page,L1/external,Permission/section,L2/external,Permission/page,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Asynchronous external,?..." group.long c15:0x115++0x00 line.long 0x00 "AIFSR,Auxiliary Instruction Fault Status Register" bitfld.long 0x00 24.--27. " CACHEWAY ,Cache way or ways in which the error occurred" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 22.--23. 20. " SIDE ,Source of the error" "Cache/AXIM,ATCM,BTCM,Reserved,Reserved,AXI,AHB,Reserved" textline " " bitfld.long 0x00 21. " REC_ERR ,Error recoverability indication" "Not recoverable,Recoverable" bitfld.long 0x00 20. " SIDE_EXT ,Source of the error" "Internal,External" textline " " hexmask.long.word 0x00 5.--13. 1. " INDEX ,Index Value for The Access Giving the Error Register" group.long c15:0x206++0x00 line.long 0x00 "IFAR,Instruction Fault Address Register" textline " " group.long c15:0x0016++0x00 line.long 0x00 "RBAR,Region Base Address Register" hexmask.long 0x00 5.--31. 0x20 " BA ,Base address" group.long c15:0x0216++0x00 line.long 0x00 "RSER,Region Size and Enable Register" bitfld.long 0x00 15. " SD ,Subregion 7 disable" "-,D" bitfld.long 0x00 14. " ,Subregion 6 disable" "-,D" bitfld.long 0x00 13. " ,Subregion 5 disable" "-,D" bitfld.long 0x00 12. " ,Subregion 4 disable" "-,D" bitfld.long 0x00 11. " ,Subregion 3 disable" "-,D" bitfld.long 0x00 10. " ,Subregion 2 disable" "-,D" bitfld.long 0x00 9. " ,Subregion 1 disable" "-,D" bitfld.long 0x00 8. " ,Subregion 0 disable" "-,D" bitfld.long 0x00 1.--5. " RS ,Region size" "Unpredictable,Unpredictable,Unpredictable,Unpredictable,32 bytes,64 bytes,128 bytes,256 bytes,512 bytes,1KB,2KB,4KB,8KB,16KB,32KB,64KB,128KB,256KB,512KB,1MB,2MB,4MB,8MB,16MB,32MB,64MB,128MB,256MB,512MB,1GB,2GB,4GB" bitfld.long 0x00 0. " EN ,Enable" "Disabled,Enabled" group.long c15:0x0416++0x00 line.long 0x00 "RACR,Region Access Control Register" bitfld.long 0x00 12. " XN ,Execute never" "-,NoExec" bitfld.long 0x00 2. " S ,Share" "No,Yes" bitfld.long 0x00 8.--10. " AP ,Access permission" "None,Privileged,User read-only,Full,Reserved,Privileged read,Read-only,Reserved" bitfld.long 0x00 0.--1. 3.--5. " TYPE ,Region type" "Strongly-ordered,Shareable Device,Outer and Inner write-through/no write-allocate,Outer and Inner write-back/no write-allocate,Outer and Inner Non-cacheable,00101,00110,Outer and Inner write-back/write-allocate,Non-shareable Device,01001,01010,01011,01100,01101,01110,01111,O:Non-cacheable I:Non-cacheable,O:Non-cacheable I:Write-back/write-allocate,O:Non-cacheable I:Write-through/no write-allocate,O:Non-cacheable I:Write-back/no write-allocate,O:Write-back/write-allocate I:Non-cacheable,O:Write-back/write-allocate I:Write-back/write-allocate,O:Write-back/write-allocate I:Write-through/no write-allocate,O:Write-back/write-allocate I:Write-back/no write-allocate,O:Write-through/no write-allocate I:Non-cacheable,O:Write-through/no write-allocate I:Write-back/write-allocate,O:Write-through/no write-allocate I:Write-through/no write-allocate,O:Write-through/no write-allocate I:Write-back/no write-allocate,O:Write-back/no write-allocate I:Non-cacheable,O:Write-back/no write-allocate I:Write-back/write-allocate,O:Write-back/no write-allocate I:Write-through/no write-allocate,O:Write-back/no write-allocate I:Write-back/no write-allocate" group.long c15:0x0026++0x00 line.long 0x00 "MRNR,Memory Region Number Register" bitfld.long 0x00 0.--3. " REGION ,Defines the group of registers to be accessed" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " group.long c15:0x010d++0x00 line.long 0x00 "CIDR,Context ID Register" group.long c15:0x20d++0x00 line.long 0x00 "TIDRURW,User read/write Thread and Process ID Register" group.long c15:0x30d++0x00 line.long 0x00 "TIDRURO,User read only Thread and Process ID Register" group.long c15:0x40d++0x00 line.long 0x00 "TIDRPRW,Privileged Only Thread and Process ID Register" width 0x08 tree "MPU regions" group c15:0x0016++0x00 saveout c15:0x26 %l 0x0 line.long 0x00 "RBAR0,Region Base Address Register 0" hexmask.long 0x00 5.--31. 0x20 " BA ,Base address" group c15:0x0216++0x00 saveout c15:0x26 %l 0x0 line.long 0x00 "RSER0,Region Size and Enable Register 0" bitfld.long 0x00 15. " SD ,Subregion 7 disable" "-,D" bitfld.long 0x00 14. " ,Subregion 6 disable" "-,D" bitfld.long 0x00 13. " ,Subregion 5 disable" "-,D" bitfld.long 0x00 12. " ,Subregion 4 disable" "-,D" bitfld.long 0x00 11. " ,Subregion 3 disable" "-,D" bitfld.long 0x00 10. " ,Subregion 2 disable" "-,D" bitfld.long 0x00 9. " ,Subregion 1 disable" "-,D" bitfld.long 0x00 8. " ,Subregion 0 disable" "-,D" bitfld.long 0x00 1.--5. " RS ,Region size" "Unpredictable,Unpredictable,Unpredictable,Unpredictable,32 bytes,64 bytes,128 bytes,256 bytes,512 bytes,1KB,2KB,4KB,8KB,16KB,32KB,64KB,128KB,256KB,512KB,1MB,2MB,4MB,8MB,16MB,32MB,64MB,128MB,256MB,512MB,1GB,2GB,4GB" bitfld.long 0x00 0. " EN ,Enable" "Disabled,Enabled" group c15:0x0416++0x00 saveout c15:0x26 %l 0x0 line.long 0x00 "RACR0,Region Access Control Register 0" bitfld.long 0x00 12. " XN ,Execute never" "-,NoExec" bitfld.long 0x00 2. " S ,Share" "No,Yes" bitfld.long 0x00 8.--10. " AP ,Access permission" "None,Privileged,User read-only,Full,Reserved,Privileged read,Read-only,Reserved" bitfld.long 0x00 0.--1. 3.--5. " type ,Region type" "Strongly-ordered,Shareable Device,Outer and Inner write-through/no write-allocate,Outer and Inner write-back/no write-allocate,Outer and Inner Non-cacheable,00101,00110,Outer and Inner write-back/write-allocate,Non-shareable Device,01001,01010,01011,01100,01101,01110,01111,O:Non-cacheable I:Non-cacheable,O:Non-cacheable I:Write-back/write-allocate,O:Non-cacheable I:Write-through/no write-allocate,O:Non-cacheable I:Write-back/no write-allocate,O:Write-back/write-allocate I:Non-cacheable,O:Write-back/write-allocate I:Write-back/write-allocate,O:Write-back/write-allocate I:Write-through/no write-allocate,O:Write-back/write-allocate I:Write-back/no write-allocate,O:Write-through/no write-allocate I:Non-cacheable,O:Write-through/no write-allocate I:Write-back/write-allocate,O:Write-through/no write-allocate I:Write-through/no write-allocate,O:Write-through/no write-allocate I:Write-back/no write-allocate,O:Write-back/no write-allocate I:Non-cacheable,O:Write-back/no write-allocate I:Write-back/write-allocate,O:Write-back/no write-allocate I:Write-through/no write-allocate,O:Write-back/no write-allocate I:Write-back/no write-allocate" textline " " group c15:0x0016++0x00 saveout c15:0x26 %l 0x1 line.long 0x00 "RBAR1,Region Base Address Register 1" hexmask.long 0x00 5.--31. 0x20 " BA ,Base address" group c15:0x0216++0x00 saveout c15:0x26 %l 0x1 line.long 0x00 "RSER1,Region Size and Enable Register 1" bitfld.long 0x00 15. " SD ,Subregion 7 disable" "-,D" bitfld.long 0x00 14. " ,Subregion 6 disable" "-,D" bitfld.long 0x00 13. " ,Subregion 5 disable" "-,D" bitfld.long 0x00 12. " ,Subregion 4 disable" "-,D" bitfld.long 0x00 11. " ,Subregion 3 disable" "-,D" bitfld.long 0x00 10. " ,Subregion 2 disable" "-,D" bitfld.long 0x00 9. " ,Subregion 1 disable" "-,D" bitfld.long 0x00 8. " ,Subregion 0 disable" "-,D" bitfld.long 0x00 1.--5. " RS ,Region size" "Unpredictable,Unpredictable,Unpredictable,Unpredictable,32 bytes,64 bytes,128 bytes,256 bytes,512 bytes,1KB,2KB,4KB,8KB,16KB,32KB,64KB,128KB,256KB,512KB,1MB,2MB,4MB,8MB,16MB,32MB,64MB,128MB,256MB,512MB,1GB,2GB,4GB" bitfld.long 0x00 0. " EN ,Enable" "Disabled,Enabled" group c15:0x0416++0x00 saveout c15:0x26 %l 0x1 line.long 0x00 "RACR1,Region Access Control Register 1" bitfld.long 0x00 12. " XN ,Execute never" "-,NoExec" bitfld.long 0x00 2. " S ,Share" "No,Yes" bitfld.long 0x00 8.--10. " AP ,Access permission" "None,Privileged,User read-only,Full,Reserved,Privileged read,Read-only,Reserved" bitfld.long 0x00 0.--1. 3.--5. " type ,Region type" "Strongly-ordered,Shareable Device,Outer and Inner write-through/no write-allocate,Outer and Inner write-back/no write-allocate,Outer and Inner Non-cacheable,00101,00110,Outer and Inner write-back/write-allocate,Non-shareable Device,01001,01010,01011,01100,01101,01110,01111,O:Non-cacheable I:Non-cacheable,O:Non-cacheable I:Write-back/write-allocate,O:Non-cacheable I:Write-through/no write-allocate,O:Non-cacheable I:Write-back/no write-allocate,O:Write-back/write-allocate I:Non-cacheable,O:Write-back/write-allocate I:Write-back/write-allocate,O:Write-back/write-allocate I:Write-through/no write-allocate,O:Write-back/write-allocate I:Write-back/no write-allocate,O:Write-through/no write-allocate I:Non-cacheable,O:Write-through/no write-allocate I:Write-back/write-allocate,O:Write-through/no write-allocate I:Write-through/no write-allocate,O:Write-through/no write-allocate I:Write-back/no write-allocate,O:Write-back/no write-allocate I:Non-cacheable,O:Write-back/no write-allocate I:Write-back/write-allocate,O:Write-back/no write-allocate I:Write-through/no write-allocate,O:Write-back/no write-allocate I:Write-back/no write-allocate" textline " " group c15:0x0016++0x00 saveout c15:0x26 %l 0x2 line.long 0x00 "RBAR2,Region Base Address Register 2" hexmask.long 0x00 5.--31. 0x20 " BA ,Base address" group c15:0x0216++0x00 saveout c15:0x26 %l 0x2 line.long 0x00 "RSER2,Region Size and Enable Register 2" bitfld.long 0x00 15. " SD ,Subregion 7 disable" "-,D" bitfld.long 0x00 14. " ,Subregion 6 disable" "-,D" bitfld.long 0x00 13. " ,Subregion 5 disable" "-,D" bitfld.long 0x00 12. " ,Subregion 4 disable" "-,D" bitfld.long 0x00 11. " ,Subregion 3 disable" "-,D" bitfld.long 0x00 10. " ,Subregion 2 disable" "-,D" bitfld.long 0x00 9. " ,Subregion 1 disable" "-,D" bitfld.long 0x00 8. " ,Subregion 0 disable" "-,D" bitfld.long 0x00 1.--5. " RS ,Region size" "Unpredictable,Unpredictable,Unpredictable,Unpredictable,32 bytes,64 bytes,128 bytes,256 bytes,512 bytes,1KB,2KB,4KB,8KB,16KB,32KB,64KB,128KB,256KB,512KB,1MB,2MB,4MB,8MB,16MB,32MB,64MB,128MB,256MB,512MB,1GB,2GB,4GB" bitfld.long 0x00 0. " EN ,Enable" "Disabled,Enabled" group c15:0x0416++0x00 saveout c15:0x26 %l 0x2 line.long 0x00 "RACR2,Region Access Control Register 2" bitfld.long 0x00 12. " XN ,Execute never" "-,NoExec" bitfld.long 0x00 2. " S ,Share" "No,Yes" bitfld.long 0x00 8.--10. " AP ,Access permission" "None,Privileged,User read-only,Full,Reserved,Privileged read,Read-only,Reserved" bitfld.long 0x00 0.--1. 3.--5. " type ,Region type" "Strongly-ordered,Shareable Device,Outer and Inner write-through/no write-allocate,Outer and Inner write-back/no write-allocate,Outer and Inner Non-cacheable,00101,00110,Outer and Inner write-back/write-allocate,Non-shareable Device,01001,01010,01011,01100,01101,01110,01111,O:Non-cacheable I:Non-cacheable,O:Non-cacheable I:Write-back/write-allocate,O:Non-cacheable I:Write-through/no write-allocate,O:Non-cacheable I:Write-back/no write-allocate,O:Write-back/write-allocate I:Non-cacheable,O:Write-back/write-allocate I:Write-back/write-allocate,O:Write-back/write-allocate I:Write-through/no write-allocate,O:Write-back/write-allocate I:Write-back/no write-allocate,O:Write-through/no write-allocate I:Non-cacheable,O:Write-through/no write-allocate I:Write-back/write-allocate,O:Write-through/no write-allocate I:Write-through/no write-allocate,O:Write-through/no write-allocate I:Write-back/no write-allocate,O:Write-back/no write-allocate I:Non-cacheable,O:Write-back/no write-allocate I:Write-back/write-allocate,O:Write-back/no write-allocate I:Write-through/no write-allocate,O:Write-back/no write-allocate I:Write-back/no write-allocate" textline " " group c15:0x0016++0x00 saveout c15:0x26 %l 0x3 line.long 0x00 "RBAR3,Region Base Address Register 3" hexmask.long 0x00 5.--31. 0x20 " BA ,Base address" group c15:0x0216++0x00 saveout c15:0x26 %l 0x3 line.long 0x00 "RSER3,Region Size and Enable Register 3" bitfld.long 0x00 15. " SD ,Subregion 7 disable" "-,D" bitfld.long 0x00 14. " ,Subregion 6 disable" "-,D" bitfld.long 0x00 13. " ,Subregion 5 disable" "-,D" bitfld.long 0x00 12. " ,Subregion 4 disable" "-,D" bitfld.long 0x00 11. " ,Subregion 3 disable" "-,D" bitfld.long 0x00 10. " ,Subregion 2 disable" "-,D" bitfld.long 0x00 9. " ,Subregion 1 disable" "-,D" bitfld.long 0x00 8. " ,Subregion 0 disable" "-,D" bitfld.long 0x00 1.--5. " RS ,Region size" "Unpredictable,Unpredictable,Unpredictable,Unpredictable,32 bytes,64 bytes,128 bytes,256 bytes,512 bytes,1KB,2KB,4KB,8KB,16KB,32KB,64KB,128KB,256KB,512KB,1MB,2MB,4MB,8MB,16MB,32MB,64MB,128MB,256MB,512MB,1GB,2GB,4GB" bitfld.long 0x00 0. " EN ,Enable" "Disabled,Enabled" group c15:0x0416++0x00 saveout c15:0x26 %l 0x3 line.long 0x00 "RACR3,Region Access Control Register 3" bitfld.long 0x00 12. " XN ,Execute never" "-,NoExec" bitfld.long 0x00 2. " S ,Share" "No,Yes" bitfld.long 0x00 8.--10. " AP ,Access permission" "None,Privileged,User read-only,Full,Reserved,Privileged read,Read-only,Reserved" bitfld.long 0x00 0.--1. 3.--5. " type ,Region type" "Strongly-ordered,Shareable Device,Outer and Inner write-through/no write-allocate,Outer and Inner write-back/no write-allocate,Outer and Inner Non-cacheable,00101,00110,Outer and Inner write-back/write-allocate,Non-shareable Device,01001,01010,01011,01100,01101,01110,01111,O:Non-cacheable I:Non-cacheable,O:Non-cacheable I:Write-back/write-allocate,O:Non-cacheable I:Write-through/no write-allocate,O:Non-cacheable I:Write-back/no write-allocate,O:Write-back/write-allocate I:Non-cacheable,O:Write-back/write-allocate I:Write-back/write-allocate,O:Write-back/write-allocate I:Write-through/no write-allocate,O:Write-back/write-allocate I:Write-back/no write-allocate,O:Write-through/no write-allocate I:Non-cacheable,O:Write-through/no write-allocate I:Write-back/write-allocate,O:Write-through/no write-allocate I:Write-through/no write-allocate,O:Write-through/no write-allocate I:Write-back/no write-allocate,O:Write-back/no write-allocate I:Non-cacheable,O:Write-back/no write-allocate I:Write-back/write-allocate,O:Write-back/no write-allocate I:Write-through/no write-allocate,O:Write-back/no write-allocate I:Write-back/no write-allocate" textline " " group c15:0x0016++0x00 saveout c15:0x26 %l 0x4 line.long 0x00 "RBAR4,Region Base Address Register 4" hexmask.long 0x00 5.--31. 0x20 " BA ,Base address" group c15:0x0216++0x00 saveout c15:0x26 %l 0x4 line.long 0x00 "RSER4,Region Size and Enable Register 4" bitfld.long 0x00 15. " SD ,Subregion 7 disable" "-,D" bitfld.long 0x00 14. " ,Subregion 6 disable" "-,D" bitfld.long 0x00 13. " ,Subregion 5 disable" "-,D" bitfld.long 0x00 12. " ,Subregion 4 disable" "-,D" bitfld.long 0x00 11. " ,Subregion 3 disable" "-,D" bitfld.long 0x00 10. " ,Subregion 2 disable" "-,D" bitfld.long 0x00 9. " ,Subregion 1 disable" "-,D" bitfld.long 0x00 8. " ,Subregion 0 disable" "-,D" bitfld.long 0x00 1.--5. " RS ,Region size" "Unpredictable,Unpredictable,Unpredictable,Unpredictable,32 bytes,64 bytes,128 bytes,256 bytes,512 bytes,1KB,2KB,4KB,8KB,16KB,32KB,64KB,128KB,256KB,512KB,1MB,2MB,4MB,8MB,16MB,32MB,64MB,128MB,256MB,512MB,1GB,2GB,4GB" bitfld.long 0x00 0. " EN ,Enable" "Disabled,Enabled" group c15:0x0416++0x00 saveout c15:0x26 %l 0x4 line.long 0x00 "RACR4,Region Access Control Register 4" bitfld.long 0x00 12. " XN ,Execute never" "-,NoExec" bitfld.long 0x00 2. " S ,Share" "No,Yes" bitfld.long 0x00 8.--10. " AP ,Access permission" "None,Privileged,User read-only,Full,Reserved,Privileged read,Read-only,Reserved" bitfld.long 0x00 0.--1. 3.--5. " type ,Region type" "Strongly-ordered,Shareable Device,Outer and Inner write-through/no write-allocate,Outer and Inner write-back/no write-allocate,Outer and Inner Non-cacheable,00101,00110,Outer and Inner write-back/write-allocate,Non-shareable Device,01001,01010,01011,01100,01101,01110,01111,O:Non-cacheable I:Non-cacheable,O:Non-cacheable I:Write-back/write-allocate,O:Non-cacheable I:Write-through/no write-allocate,O:Non-cacheable I:Write-back/no write-allocate,O:Write-back/write-allocate I:Non-cacheable,O:Write-back/write-allocate I:Write-back/write-allocate,O:Write-back/write-allocate I:Write-through/no write-allocate,O:Write-back/write-allocate I:Write-back/no write-allocate,O:Write-through/no write-allocate I:Non-cacheable,O:Write-through/no write-allocate I:Write-back/write-allocate,O:Write-through/no write-allocate I:Write-through/no write-allocate,O:Write-through/no write-allocate I:Write-back/no write-allocate,O:Write-back/no write-allocate I:Non-cacheable,O:Write-back/no write-allocate I:Write-back/write-allocate,O:Write-back/no write-allocate I:Write-through/no write-allocate,O:Write-back/no write-allocate I:Write-back/no write-allocate" textline " " group c15:0x0016++0x00 saveout c15:0x26 %l 0x5 line.long 0x00 "RBAR5,Region Base Address Register 5" hexmask.long 0x00 5.--31. 0x20 " BA ,Base address" group c15:0x0216++0x00 saveout c15:0x26 %l 0x5 line.long 0x00 "RSER5,Region Size and Enable Register 5" bitfld.long 0x00 15. " SD ,Subregion 7 disable" "-,D" bitfld.long 0x00 14. " ,Subregion 6 disable" "-,D" bitfld.long 0x00 13. " ,Subregion 5 disable" "-,D" bitfld.long 0x00 12. " ,Subregion 4 disable" "-,D" bitfld.long 0x00 11. " ,Subregion 3 disable" "-,D" bitfld.long 0x00 10. " ,Subregion 2 disable" "-,D" bitfld.long 0x00 9. " ,Subregion 1 disable" "-,D" bitfld.long 0x00 8. " ,Subregion 0 disable" "-,D" bitfld.long 0x00 1.--5. " RS ,Region size" "Unpredictable,Unpredictable,Unpredictable,Unpredictable,32 bytes,64 bytes,128 bytes,256 bytes,512 bytes,1KB,2KB,4KB,8KB,16KB,32KB,64KB,128KB,256KB,512KB,1MB,2MB,4MB,8MB,16MB,32MB,64MB,128MB,256MB,512MB,1GB,2GB,4GB" bitfld.long 0x00 0. " EN ,Enable" "Disabled,Enabled" group c15:0x0416++0x00 saveout c15:0x26 %l 0x5 line.long 0x00 "RACR5,Region Access Control Register 5" bitfld.long 0x00 12. " XN ,Execute never" "-,NoExec" bitfld.long 0x00 2. " S ,Share" "No,Yes" bitfld.long 0x00 8.--10. " AP ,Access permission" "None,Privileged,User read-only,Full,Reserved,Privileged read,Read-only,Reserved" bitfld.long 0x00 0.--1. 3.--5. " type ,Region type" "Strongly-ordered,Shareable Device,Outer and Inner write-through/no write-allocate,Outer and Inner write-back/no write-allocate,Outer and Inner Non-cacheable,00101,00110,Outer and Inner write-back/write-allocate,Non-shareable Device,01001,01010,01011,01100,01101,01110,01111,O:Non-cacheable I:Non-cacheable,O:Non-cacheable I:Write-back/write-allocate,O:Non-cacheable I:Write-through/no write-allocate,O:Non-cacheable I:Write-back/no write-allocate,O:Write-back/write-allocate I:Non-cacheable,O:Write-back/write-allocate I:Write-back/write-allocate,O:Write-back/write-allocate I:Write-through/no write-allocate,O:Write-back/write-allocate I:Write-back/no write-allocate,O:Write-through/no write-allocate I:Non-cacheable,O:Write-through/no write-allocate I:Write-back/write-allocate,O:Write-through/no write-allocate I:Write-through/no write-allocate,O:Write-through/no write-allocate I:Write-back/no write-allocate,O:Write-back/no write-allocate I:Non-cacheable,O:Write-back/no write-allocate I:Write-back/write-allocate,O:Write-back/no write-allocate I:Write-through/no write-allocate,O:Write-back/no write-allocate I:Write-back/no write-allocate" textline " " group c15:0x0016++0x00 saveout c15:0x26 %l 0x6 line.long 0x00 "RBAR6,Region Base Address Register 6" hexmask.long 0x00 5.--31. 0x20 " BA ,Base address" group c15:0x0216++0x00 saveout c15:0x26 %l 0x6 line.long 0x00 "RSER6,Region Size and Enable Register 6" bitfld.long 0x00 15. " SD ,Subregion 7 disable" "-,D" bitfld.long 0x00 14. " ,Subregion 6 disable" "-,D" bitfld.long 0x00 13. " ,Subregion 5 disable" "-,D" bitfld.long 0x00 12. " ,Subregion 4 disable" "-,D" bitfld.long 0x00 11. " ,Subregion 3 disable" "-,D" bitfld.long 0x00 10. " ,Subregion 2 disable" "-,D" bitfld.long 0x00 9. " ,Subregion 1 disable" "-,D" bitfld.long 0x00 8. " ,Subregion 0 disable" "-,D" bitfld.long 0x00 1.--5. " RS ,Region size" "Unpredictable,Unpredictable,Unpredictable,Unpredictable,32 bytes,64 bytes,128 bytes,256 bytes,512 bytes,1KB,2KB,4KB,8KB,16KB,32KB,64KB,128KB,256KB,512KB,1MB,2MB,4MB,8MB,16MB,32MB,64MB,128MB,256MB,512MB,1GB,2GB,4GB" bitfld.long 0x00 0. " EN ,Enable" "Disabled,Enabled" group c15:0x0416++0x00 saveout c15:0x26 %l 0x6 line.long 0x00 "RACR6,Region Access Control Register 6" bitfld.long 0x00 12. " XN ,Execute never" "-,NoExec" bitfld.long 0x00 2. " S ,Share" "No,Yes" bitfld.long 0x00 8.--10. " AP ,Access permission" "None,Privileged,User read-only,Full,Reserved,Privileged read,Read-only,Reserved" bitfld.long 0x00 0.--1. 3.--5. " type ,Region type" "Strongly-ordered,Shareable Device,Outer and Inner write-through/no write-allocate,Outer and Inner write-back/no write-allocate,Outer and Inner Non-cacheable,00101,00110,Outer and Inner write-back/write-allocate,Non-shareable Device,01001,01010,01011,01100,01101,01110,01111,O:Non-cacheable I:Non-cacheable,O:Non-cacheable I:Write-back/write-allocate,O:Non-cacheable I:Write-through/no write-allocate,O:Non-cacheable I:Write-back/no write-allocate,O:Write-back/write-allocate I:Non-cacheable,O:Write-back/write-allocate I:Write-back/write-allocate,O:Write-back/write-allocate I:Write-through/no write-allocate,O:Write-back/write-allocate I:Write-back/no write-allocate,O:Write-through/no write-allocate I:Non-cacheable,O:Write-through/no write-allocate I:Write-back/write-allocate,O:Write-through/no write-allocate I:Write-through/no write-allocate,O:Write-through/no write-allocate I:Write-back/no write-allocate,O:Write-back/no write-allocate I:Non-cacheable,O:Write-back/no write-allocate I:Write-back/write-allocate,O:Write-back/no write-allocate I:Write-through/no write-allocate,O:Write-back/no write-allocate I:Write-back/no write-allocate" textline " " group c15:0x0016++0x00 saveout c15:0x26 %l 0x7 line.long 0x00 "RBAR7,Region Base Address Register 7" hexmask.long 0x00 5.--31. 0x20 " BA ,Base address" group c15:0x0216++0x00 saveout c15:0x26 %l 0x7 line.long 0x00 "RSER7,Region Size and Enable Register 7" bitfld.long 0x00 15. " SD ,Subregion 7 disable" "-,D" bitfld.long 0x00 14. " ,Subregion 6 disable" "-,D" bitfld.long 0x00 13. " ,Subregion 5 disable" "-,D" bitfld.long 0x00 12. " ,Subregion 4 disable" "-,D" bitfld.long 0x00 11. " ,Subregion 3 disable" "-,D" bitfld.long 0x00 10. " ,Subregion 2 disable" "-,D" bitfld.long 0x00 9. " ,Subregion 1 disable" "-,D" bitfld.long 0x00 8. " ,Subregion 0 disable" "-,D" bitfld.long 0x00 1.--5. " RS ,Region size" "Unpredictable,Unpredictable,Unpredictable,Unpredictable,32 bytes,64 bytes,128 bytes,256 bytes,512 bytes,1KB,2KB,4KB,8KB,16KB,32KB,64KB,128KB,256KB,512KB,1MB,2MB,4MB,8MB,16MB,32MB,64MB,128MB,256MB,512MB,1GB,2GB,4GB" bitfld.long 0x00 0. " EN ,Enable" "Disabled,Enabled" group c15:0x0416++0x00 saveout c15:0x26 %l 0x7 line.long 0x00 "RACR7,Region Access Control Register 7" bitfld.long 0x00 12. " XN ,Execute never" "-,NoExec" bitfld.long 0x00 2. " S ,Share" "No,Yes" bitfld.long 0x00 8.--10. " AP ,Access permission" "None,Privileged,User read-only,Full,Reserved,Privileged read,Read-only,Reserved" bitfld.long 0x00 0.--1. 3.--5. " type ,Region type" "Strongly-ordered,Shareable Device,Outer and Inner write-through/no write-allocate,Outer and Inner write-back/no write-allocate,Outer and Inner Non-cacheable,00101,00110,Outer and Inner write-back/write-allocate,Non-shareable Device,01001,01010,01011,01100,01101,01110,01111,O:Non-cacheable I:Non-cacheable,O:Non-cacheable I:Write-back/write-allocate,O:Non-cacheable I:Write-through/no write-allocate,O:Non-cacheable I:Write-back/no write-allocate,O:Write-back/write-allocate I:Non-cacheable,O:Write-back/write-allocate I:Write-back/write-allocate,O:Write-back/write-allocate I:Write-through/no write-allocate,O:Write-back/write-allocate I:Write-back/no write-allocate,O:Write-through/no write-allocate I:Non-cacheable,O:Write-through/no write-allocate I:Write-back/write-allocate,O:Write-through/no write-allocate I:Write-through/no write-allocate,O:Write-through/no write-allocate I:Write-back/no write-allocate,O:Write-back/no write-allocate I:Non-cacheable,O:Write-back/no write-allocate I:Write-back/write-allocate,O:Write-back/no write-allocate I:Write-through/no write-allocate,O:Write-back/no write-allocate I:Write-back/no write-allocate" textline " " group c15:0x0016++0x00 saveout c15:0x26 %l 0x8 line.long 0x00 "RBAR8,Region Base Address Register 8" hexmask.long 0x00 5.--31. 0x20 " BA ,Base address" group c15:0x0216++0x00 saveout c15:0x26 %l 0x8 line.long 0x00 "RSER8,Region Size and Enable Register 8" bitfld.long 0x00 15. " SD ,Subregion 7 disable" "-,D" bitfld.long 0x00 14. " ,Subregion 6 disable" "-,D" bitfld.long 0x00 13. " ,Subregion 5 disable" "-,D" bitfld.long 0x00 12. " ,Subregion 4 disable" "-,D" bitfld.long 0x00 11. " ,Subregion 3 disable" "-,D" bitfld.long 0x00 10. " ,Subregion 2 disable" "-,D" bitfld.long 0x00 9. " ,Subregion 1 disable" "-,D" bitfld.long 0x00 8. " ,Subregion 0 disable" "-,D" bitfld.long 0x00 1.--5. " RS ,Region size" "Unpredictable,Unpredictable,Unpredictable,Unpredictable,32 bytes,64 bytes,128 bytes,256 bytes,512 bytes,1KB,2KB,4KB,8KB,16KB,32KB,64KB,128KB,256KB,512KB,1MB,2MB,4MB,8MB,16MB,32MB,64MB,128MB,256MB,512MB,1GB,2GB,4GB" bitfld.long 0x00 0. " EN ,Enable" "Disabled,Enabled" group c15:0x0416++0x00 saveout c15:0x26 %l 0x8 line.long 0x00 "RACR8,Region Access Control Register 8" bitfld.long 0x00 12. " XN ,Execute never" "-,NoExec" bitfld.long 0x00 2. " S ,Share" "No,Yes" bitfld.long 0x00 8.--10. " AP ,Access permission" "None,Privileged,User read-only,Full,Reserved,Privileged read,Read-only,Reserved" bitfld.long 0x00 0.--1. 3.--5. " type ,Region type" "Strongly-ordered,Shareable Device,Outer and Inner write-through/no write-allocate,Outer and Inner write-back/no write-allocate,Outer and Inner Non-cacheable,00101,00110,Outer and Inner write-back/write-allocate,Non-shareable Device,01001,01010,01011,01100,01101,01110,01111,O:Non-cacheable I:Non-cacheable,O:Non-cacheable I:Write-back/write-allocate,O:Non-cacheable I:Write-through/no write-allocate,O:Non-cacheable I:Write-back/no write-allocate,O:Write-back/write-allocate I:Non-cacheable,O:Write-back/write-allocate I:Write-back/write-allocate,O:Write-back/write-allocate I:Write-through/no write-allocate,O:Write-back/write-allocate I:Write-back/no write-allocate,O:Write-through/no write-allocate I:Non-cacheable,O:Write-through/no write-allocate I:Write-back/write-allocate,O:Write-through/no write-allocate I:Write-through/no write-allocate,O:Write-through/no write-allocate I:Write-back/no write-allocate,O:Write-back/no write-allocate I:Non-cacheable,O:Write-back/no write-allocate I:Write-back/write-allocate,O:Write-back/no write-allocate I:Write-through/no write-allocate,O:Write-back/no write-allocate I:Write-back/no write-allocate" textline " " group c15:0x0016++0x00 saveout c15:0x26 %l 0x9 line.long 0x00 "RBAR9,Region Base Address Register 9" hexmask.long 0x00 5.--31. 0x20 " BA ,Base address" group c15:0x0216++0x00 saveout c15:0x26 %l 0x9 line.long 0x00 "RSER9,Region Size and Enable Register 9" bitfld.long 0x00 15. " SD ,Subregion 7 disable" "-,D" bitfld.long 0x00 14. " ,Subregion 6 disable" "-,D" bitfld.long 0x00 13. " ,Subregion 5 disable" "-,D" bitfld.long 0x00 12. " ,Subregion 4 disable" "-,D" bitfld.long 0x00 11. " ,Subregion 3 disable" "-,D" bitfld.long 0x00 10. " ,Subregion 2 disable" "-,D" bitfld.long 0x00 9. " ,Subregion 1 disable" "-,D" bitfld.long 0x00 8. " ,Subregion 0 disable" "-,D" bitfld.long 0x00 1.--5. " RS ,Region size" "Unpredictable,Unpredictable,Unpredictable,Unpredictable,32 bytes,64 bytes,128 bytes,256 bytes,512 bytes,1KB,2KB,4KB,8KB,16KB,32KB,64KB,128KB,256KB,512KB,1MB,2MB,4MB,8MB,16MB,32MB,64MB,128MB,256MB,512MB,1GB,2GB,4GB" bitfld.long 0x00 0. " EN ,Enable" "Disabled,Enabled" group c15:0x0416++0x00 saveout c15:0x26 %l 0x9 line.long 0x00 "RACR9,Region Access Control Register 9" bitfld.long 0x00 12. " XN ,Execute never" "-,NoExec" bitfld.long 0x00 2. " S ,Share" "No,Yes" bitfld.long 0x00 8.--10. " AP ,Access permission" "None,Privileged,User read-only,Full,Reserved,Privileged read,Read-only,Reserved" bitfld.long 0x00 0.--1. 3.--5. " type ,Region type" "Strongly-ordered,Shareable Device,Outer and Inner write-through/no write-allocate,Outer and Inner write-back/no write-allocate,Outer and Inner Non-cacheable,00101,00110,Outer and Inner write-back/write-allocate,Non-shareable Device,01001,01010,01011,01100,01101,01110,01111,O:Non-cacheable I:Non-cacheable,O:Non-cacheable I:Write-back/write-allocate,O:Non-cacheable I:Write-through/no write-allocate,O:Non-cacheable I:Write-back/no write-allocate,O:Write-back/write-allocate I:Non-cacheable,O:Write-back/write-allocate I:Write-back/write-allocate,O:Write-back/write-allocate I:Write-through/no write-allocate,O:Write-back/write-allocate I:Write-back/no write-allocate,O:Write-through/no write-allocate I:Non-cacheable,O:Write-through/no write-allocate I:Write-back/write-allocate,O:Write-through/no write-allocate I:Write-through/no write-allocate,O:Write-through/no write-allocate I:Write-back/no write-allocate,O:Write-back/no write-allocate I:Non-cacheable,O:Write-back/no write-allocate I:Write-back/write-allocate,O:Write-back/no write-allocate I:Write-through/no write-allocate,O:Write-back/no write-allocate I:Write-back/no write-allocate" textline " " group c15:0x0016++0x00 saveout c15:0x26 %l 0xA line.long 0x00 "RBAR10,Region Base Address Register 10" hexmask.long 0x00 5.--31. 0x20 " BA ,Base address" group c15:0x0216++0x00 saveout c15:0x26 %l 0xA line.long 0x00 "RSER10,Region Size and Enable Register 10" bitfld.long 0x00 15. " SD ,Subregion 7 disable" "-,D" bitfld.long 0x00 14. " ,Subregion 6 disable" "-,D" bitfld.long 0x00 13. " ,Subregion 5 disable" "-,D" bitfld.long 0x00 12. " ,Subregion 4 disable" "-,D" bitfld.long 0x00 11. " ,Subregion 3 disable" "-,D" bitfld.long 0x00 10. " ,Subregion 2 disable" "-,D" bitfld.long 0x00 9. " ,Subregion 1 disable" "-,D" bitfld.long 0x00 8. " ,Subregion 0 disable" "-,D" bitfld.long 0x00 1.--5. " RS ,Region size" "Unpredictable,Unpredictable,Unpredictable,Unpredictable,32 bytes,64 bytes,128 bytes,256 bytes,512 bytes,1KB,2KB,4KB,8KB,16KB,32KB,64KB,128KB,256KB,512KB,1MB,2MB,4MB,8MB,16MB,32MB,64MB,128MB,256MB,512MB,1GB,2GB,4GB" bitfld.long 0x00 0. " EN ,Enable" "Disabled,Enabled" group c15:0x0416++0x00 saveout c15:0x26 %l 0xA line.long 0x00 "RACR10,Region Access Control Register 10" bitfld.long 0x00 12. " XN ,Execute never" "-,NoExec" bitfld.long 0x00 2. " S ,Share" "No,Yes" bitfld.long 0x00 8.--10. " AP ,Access permission" "None,Privileged,User read-only,Full,Reserved,Privileged read,Read-only,Reserved" bitfld.long 0x00 0.--1. 3.--5. " type ,Region type" "Strongly-ordered,Shareable Device,Outer and Inner write-through/no write-allocate,Outer and Inner write-back/no write-allocate,Outer and Inner Non-cacheable,00101,00110,Outer and Inner write-back/write-allocate,Non-shareable Device,01001,01010,01011,01100,01101,01110,01111,O:Non-cacheable I:Non-cacheable,O:Non-cacheable I:Write-back/write-allocate,O:Non-cacheable I:Write-through/no write-allocate,O:Non-cacheable I:Write-back/no write-allocate,O:Write-back/write-allocate I:Non-cacheable,O:Write-back/write-allocate I:Write-back/write-allocate,O:Write-back/write-allocate I:Write-through/no write-allocate,O:Write-back/write-allocate I:Write-back/no write-allocate,O:Write-through/no write-allocate I:Non-cacheable,O:Write-through/no write-allocate I:Write-back/write-allocate,O:Write-through/no write-allocate I:Write-through/no write-allocate,O:Write-through/no write-allocate I:Write-back/no write-allocate,O:Write-back/no write-allocate I:Non-cacheable,O:Write-back/no write-allocate I:Write-back/write-allocate,O:Write-back/no write-allocate I:Write-through/no write-allocate,O:Write-back/no write-allocate I:Write-back/no write-allocate" textline " " group c15:0x0016++0x00 saveout c15:0x26 %l 0xB line.long 0x00 "RBAR11,Region Base Address Register 11" hexmask.long 0x00 5.--31. 0x20 " BA ,Base address" group c15:0x0216++0x00 saveout c15:0x26 %l 0xB line.long 0x00 "RSER11,Region Size and Enable Register 11" bitfld.long 0x00 15. " SD ,Subregion 7 disable" "-,D" bitfld.long 0x00 14. " ,Subregion 6 disable" "-,D" bitfld.long 0x00 13. " ,Subregion 5 disable" "-,D" bitfld.long 0x00 12. " ,Subregion 4 disable" "-,D" bitfld.long 0x00 11. " ,Subregion 3 disable" "-,D" bitfld.long 0x00 10. " ,Subregion 2 disable" "-,D" bitfld.long 0x00 9. " ,Subregion 1 disable" "-,D" bitfld.long 0x00 8. " ,Subregion 0 disable" "-,D" bitfld.long 0x00 1.--5. " RS ,Region size" "Unpredictable,Unpredictable,Unpredictable,Unpredictable,32 bytes,64 bytes,128 bytes,256 bytes,512 bytes,1KB,2KB,4KB,8KB,16KB,32KB,64KB,128KB,256KB,512KB,1MB,2MB,4MB,8MB,16MB,32MB,64MB,128MB,256MB,512MB,1GB,2GB,4GB" bitfld.long 0x00 0. " EN ,Enable" "Disabled,Enabled" group c15:0x0416++0x00 saveout c15:0x26 %l 0xB line.long 0x00 "RACR11,Region Access Control Register 11" bitfld.long 0x00 12. " XN ,Execute never" "-,NoExec" bitfld.long 0x00 2. " S ,Share" "No,Yes" bitfld.long 0x00 8.--10. " AP ,Access permission" "None,Privileged,User read-only,Full,Reserved,Privileged read,Read-only,Reserved" bitfld.long 0x00 0.--1. 3.--5. " type ,Region type" "Strongly-ordered,Shareable Device,Outer and Inner write-through/no write-allocate,Outer and Inner write-back/no write-allocate,Outer and Inner Non-cacheable,00101,00110,Outer and Inner write-back/write-allocate,Non-shareable Device,01001,01010,01011,01100,01101,01110,01111,O:Non-cacheable I:Non-cacheable,O:Non-cacheable I:Write-back/write-allocate,O:Non-cacheable I:Write-through/no write-allocate,O:Non-cacheable I:Write-back/no write-allocate,O:Write-back/write-allocate I:Non-cacheable,O:Write-back/write-allocate I:Write-back/write-allocate,O:Write-back/write-allocate I:Write-through/no write-allocate,O:Write-back/write-allocate I:Write-back/no write-allocate,O:Write-through/no write-allocate I:Non-cacheable,O:Write-through/no write-allocate I:Write-back/write-allocate,O:Write-through/no write-allocate I:Write-through/no write-allocate,O:Write-through/no write-allocate I:Write-back/no write-allocate,O:Write-back/no write-allocate I:Non-cacheable,O:Write-back/no write-allocate I:Write-back/write-allocate,O:Write-back/no write-allocate I:Write-through/no write-allocate,O:Write-back/no write-allocate I:Write-back/no write-allocate" textline " " group c15:0x0016++0x00 saveout c15:0x26 %l 0xC line.long 0x00 "RBAR12,Region Base Address Register 12" hexmask.long 0x00 5.--31. 0x20 " BA ,Base address" group c15:0x0216++0x00 saveout c15:0x26 %l 0xC line.long 0x00 "RSER12,Region Size and Enable Register 12" bitfld.long 0x00 15. " SD ,Subregion 7 disable" "-,D" bitfld.long 0x00 14. " ,Subregion 6 disable" "-,D" bitfld.long 0x00 13. " ,Subregion 5 disable" "-,D" bitfld.long 0x00 12. " ,Subregion 4 disable" "-,D" bitfld.long 0x00 11. " ,Subregion 3 disable" "-,D" bitfld.long 0x00 10. " ,Subregion 2 disable" "-,D" bitfld.long 0x00 9. " ,Subregion 1 disable" "-,D" bitfld.long 0x00 8. " ,Subregion 0 disable" "-,D" bitfld.long 0x00 1.--5. " RS ,Region size" "Unpredictable,Unpredictable,Unpredictable,Unpredictable,32 bytes,64 bytes,128 bytes,256 bytes,512 bytes,1KB,2KB,4KB,8KB,16KB,32KB,64KB,128KB,256KB,512KB,1MB,2MB,4MB,8MB,16MB,32MB,64MB,128MB,256MB,512MB,1GB,2GB,4GB" bitfld.long 0x00 0. " EN ,Enable" "Disabled,Enabled" group c15:0x0416++0x00 saveout c15:0x26 %l 0xC line.long 0x00 "RACR12,Region Access Control Register 12" bitfld.long 0x00 12. " XN ,Execute never" "-,NoExec" bitfld.long 0x00 2. " S ,Share" "No,Yes" bitfld.long 0x00 8.--10. " AP ,Access permission" "None,Privileged,User read-only,Full,Reserved,Privileged read,Read-only,Reserved" bitfld.long 0x00 0.--1. 3.--5. " type ,Region type" "Strongly-ordered,Shareable Device,Outer and Inner write-through/no write-allocate,Outer and Inner write-back/no write-allocate,Outer and Inner Non-cacheable,00101,00110,Outer and Inner write-back/write-allocate,Non-shareable Device,01001,01010,01011,01100,01101,01110,01111,O:Non-cacheable I:Non-cacheable,O:Non-cacheable I:Write-back/write-allocate,O:Non-cacheable I:Write-through/no write-allocate,O:Non-cacheable I:Write-back/no write-allocate,O:Write-back/write-allocate I:Non-cacheable,O:Write-back/write-allocate I:Write-back/write-allocate,O:Write-back/write-allocate I:Write-through/no write-allocate,O:Write-back/write-allocate I:Write-back/no write-allocate,O:Write-through/no write-allocate I:Non-cacheable,O:Write-through/no write-allocate I:Write-back/write-allocate,O:Write-through/no write-allocate I:Write-through/no write-allocate,O:Write-through/no write-allocate I:Write-back/no write-allocate,O:Write-back/no write-allocate I:Non-cacheable,O:Write-back/no write-allocate I:Write-back/write-allocate,O:Write-back/no write-allocate I:Write-through/no write-allocate,O:Write-back/no write-allocate I:Write-back/no write-allocate" textline " " group c15:0x0016++0x00 saveout c15:0x26 %l 0xD line.long 0x00 "RBAR13,Region Base Address Register 13" hexmask.long 0x00 5.--31. 0x20 " BA ,Base address" group c15:0x0216++0x00 saveout c15:0x26 %l 0xD line.long 0x00 "RSER13,Region Size and Enable Register 13" bitfld.long 0x00 15. " SD ,Subregion 7 disable" "-,D" bitfld.long 0x00 14. " ,Subregion 6 disable" "-,D" bitfld.long 0x00 13. " ,Subregion 5 disable" "-,D" bitfld.long 0x00 12. " ,Subregion 4 disable" "-,D" bitfld.long 0x00 11. " ,Subregion 3 disable" "-,D" bitfld.long 0x00 10. " ,Subregion 2 disable" "-,D" bitfld.long 0x00 9. " ,Subregion 1 disable" "-,D" bitfld.long 0x00 8. " ,Subregion 0 disable" "-,D" bitfld.long 0x00 1.--5. " RS ,Region size" "Unpredictable,Unpredictable,Unpredictable,Unpredictable,32 bytes,64 bytes,128 bytes,256 bytes,512 bytes,1KB,2KB,4KB,8KB,16KB,32KB,64KB,128KB,256KB,512KB,1MB,2MB,4MB,8MB,16MB,32MB,64MB,128MB,256MB,512MB,1GB,2GB,4GB" bitfld.long 0x00 0. " EN ,Enable" "Disabled,Enabled" group c15:0x0416++0x00 saveout c15:0x26 %l 0xD line.long 0x00 "RACR13,Region Access Control Register 13" bitfld.long 0x00 12. " XN ,Execute never" "-,NoExec" bitfld.long 0x00 2. " S ,Share" "No,Yes" bitfld.long 0x00 8.--10. " AP ,Access permission" "None,Privileged,User read-only,Full,Reserved,Privileged read,Read-only,Reserved" bitfld.long 0x00 0.--1. 3.--5. " type ,Region type" "Strongly-ordered,Shareable Device,Outer and Inner write-through/no write-allocate,Outer and Inner write-back/no write-allocate,Outer and Inner Non-cacheable,00101,00110,Outer and Inner write-back/write-allocate,Non-shareable Device,01001,01010,01011,01100,01101,01110,01111,O:Non-cacheable I:Non-cacheable,O:Non-cacheable I:Write-back/write-allocate,O:Non-cacheable I:Write-through/no write-allocate,O:Non-cacheable I:Write-back/no write-allocate,O:Write-back/write-allocate I:Non-cacheable,O:Write-back/write-allocate I:Write-back/write-allocate,O:Write-back/write-allocate I:Write-through/no write-allocate,O:Write-back/write-allocate I:Write-back/no write-allocate,O:Write-through/no write-allocate I:Non-cacheable,O:Write-through/no write-allocate I:Write-back/write-allocate,O:Write-through/no write-allocate I:Write-through/no write-allocate,O:Write-through/no write-allocate I:Write-back/no write-allocate,O:Write-back/no write-allocate I:Non-cacheable,O:Write-back/no write-allocate I:Write-back/write-allocate,O:Write-back/no write-allocate I:Write-through/no write-allocate,O:Write-back/no write-allocate I:Write-back/no write-allocate" textline " " group c15:0x0016++0x00 saveout c15:0x26 %l 0xE line.long 0x00 "RBAR14,Region Base Address Register 14" hexmask.long 0x00 5.--31. 0x20 " BA ,Base address" group c15:0x0216++0x00 saveout c15:0x26 %l 0xE line.long 0x00 "RSER14,Region Size and Enable Register 14" bitfld.long 0x00 15. " SD ,Subregion 7 disable" "-,D" bitfld.long 0x00 14. " ,Subregion 6 disable" "-,D" bitfld.long 0x00 13. " ,Subregion 5 disable" "-,D" bitfld.long 0x00 12. " ,Subregion 4 disable" "-,D" bitfld.long 0x00 11. " ,Subregion 3 disable" "-,D" bitfld.long 0x00 10. " ,Subregion 2 disable" "-,D" bitfld.long 0x00 9. " ,Subregion 1 disable" "-,D" bitfld.long 0x00 8. " ,Subregion 0 disable" "-,D" bitfld.long 0x00 1.--5. " RS ,Region size" "Unpredictable,Unpredictable,Unpredictable,Unpredictable,32 bytes,64 bytes,128 bytes,256 bytes,512 bytes,1KB,2KB,4KB,8KB,16KB,32KB,64KB,128KB,256KB,512KB,1MB,2MB,4MB,8MB,16MB,32MB,64MB,128MB,256MB,512MB,1GB,2GB,4GB" bitfld.long 0x00 0. " EN ,Enable" "Disabled,Enabled" group c15:0x0416++0x00 saveout c15:0x26 %l 0xE line.long 0x00 "RACR14,Region Access Control Register 14" bitfld.long 0x00 12. " XN ,Execute never" "-,NoExec" bitfld.long 0x00 2. " S ,Share" "No,Yes" bitfld.long 0x00 8.--10. " AP ,Access permission" "None,Privileged,User read-only,Full,Reserved,Privileged read,Read-only,Reserved" bitfld.long 0x00 0.--1. 3.--5. " type ,Region type" "Strongly-ordered,Shareable Device,Outer and Inner write-through/no write-allocate,Outer and Inner write-back/no write-allocate,Outer and Inner Non-cacheable,00101,00110,Outer and Inner write-back/write-allocate,Non-shareable Device,01001,01010,01011,01100,01101,01110,01111,O:Non-cacheable I:Non-cacheable,O:Non-cacheable I:Write-back/write-allocate,O:Non-cacheable I:Write-through/no write-allocate,O:Non-cacheable I:Write-back/no write-allocate,O:Write-back/write-allocate I:Non-cacheable,O:Write-back/write-allocate I:Write-back/write-allocate,O:Write-back/write-allocate I:Write-through/no write-allocate,O:Write-back/write-allocate I:Write-back/no write-allocate,O:Write-through/no write-allocate I:Non-cacheable,O:Write-through/no write-allocate I:Write-back/write-allocate,O:Write-through/no write-allocate I:Write-through/no write-allocate,O:Write-through/no write-allocate I:Write-back/no write-allocate,O:Write-back/no write-allocate I:Non-cacheable,O:Write-back/no write-allocate I:Write-back/write-allocate,O:Write-back/no write-allocate I:Write-through/no write-allocate,O:Write-back/no write-allocate I:Write-back/no write-allocate" textline " " group c15:0x0016++0x00 saveout c15:0x26 %l 0xF line.long 0x00 "RBAR15,Region Base Address Register 15" hexmask.long 0x00 5.--31. 0x20 " BA ,Base address" group c15:0x0216++0x00 saveout c15:0x26 %l 0xF line.long 0x00 "RSER15,Region Size and Enable Register 15" bitfld.long 0x00 15. " SD ,Subregion 7 disable" "-,D" bitfld.long 0x00 14. " ,Subregion 6 disable" "-,D" bitfld.long 0x00 13. " ,Subregion 5 disable" "-,D" bitfld.long 0x00 12. " ,Subregion 4 disable" "-,D" bitfld.long 0x00 11. " ,Subregion 3 disable" "-,D" bitfld.long 0x00 10. " ,Subregion 2 disable" "-,D" bitfld.long 0x00 9. " ,Subregion 1 disable" "-,D" bitfld.long 0x00 8. " ,Subregion 0 disable" "-,D" bitfld.long 0x00 1.--5. " RS ,Region size" "Unpredictable,Unpredictable,Unpredictable,Unpredictable,32 bytes,64 bytes,128 bytes,256 bytes,512 bytes,1KB,2KB,4KB,8KB,16KB,32KB,64KB,128KB,256KB,512KB,1MB,2MB,4MB,8MB,16MB,32MB,64MB,128MB,256MB,512MB,1GB,2GB,4GB" bitfld.long 0x00 0. " EN ,Enable" "Disabled,Enabled" group c15:0x0416++0x00 saveout c15:0x26 %l 0xF line.long 0x00 "RACR15,Region Access Control Register 15" bitfld.long 0x00 12. " XN ,Execute never" "-,NoExec" bitfld.long 0x00 2. " S ,Share" "No,Yes" bitfld.long 0x00 8.--10. " AP ,Access permission" "None,Privileged,User read-only,Full,Reserved,Privileged read,Read-only,Reserved" bitfld.long 0x00 0.--1. 3.--5. " type ,Region type" "Strongly-ordered,Shareable Device,Outer and Inner write-through/no write-allocate,Outer and Inner write-back/no write-allocate,Outer and Inner Non-cacheable,00101,00110,Outer and Inner write-back/write-allocate,Non-shareable Device,01001,01010,01011,01100,01101,01110,01111,O:Non-cacheable I:Non-cacheable,O:Non-cacheable I:Write-back/write-allocate,O:Non-cacheable I:Write-through/no write-allocate,O:Non-cacheable I:Write-back/no write-allocate,O:Write-back/write-allocate I:Non-cacheable,O:Write-back/write-allocate I:Write-back/write-allocate,O:Write-back/write-allocate I:Write-through/no write-allocate,O:Write-back/write-allocate I:Write-back/no write-allocate,O:Write-through/no write-allocate I:Non-cacheable,O:Write-through/no write-allocate I:Write-back/write-allocate,O:Write-through/no write-allocate I:Write-through/no write-allocate,O:Write-through/no write-allocate I:Write-back/no write-allocate,O:Write-back/no write-allocate I:Non-cacheable,O:Write-back/no write-allocate I:Write-back/write-allocate,O:Write-back/no write-allocate I:Write-through/no write-allocate,O:Write-back/no write-allocate I:Write-back/no write-allocate" textline " " tree.end tree.end width 0x9 tree "TCM Control and Configuration" rgroup.long c15:0x200++0x00 line.long 0x00 "TCMTR,TCM Type Register" bitfld.long 0x00 16.--18. " BTCM ,Number of BTCMs implemented" "0,1,2,3,4,5,6,7" bitfld.long 0x00 0.--2. " ATCM ,Number of ATCMs implemented" "0,1,2,3,4,5,6,7" group.long c15:0x019++0x00 line.long 0x00 "BTCMRR,BTCM Region Register" hexmask.long 0x00 12.--31. 0x1000 " BA ,Base address (physical address)" bitfld.long 0x00 2.--6. " SIZE ,Size of instruction TCM on reads" "None,Reserved,Reserved,4KB,8KB,16KB,32KB,64KB,128KB,256KB,512KB,1MB,2MB,4MB,8MB,16M,32M,64M,128M,256M,512M,1G,2G,4G,?..." bitfld.long 0x00 0. " EN ,Enable instruction TCM" "Disabled,Enabled" group.long c15:0x119++0x00 line.long 0x00 "ATCMRR,ATCM Region Register" hexmask.long 0x00 12.--31. 0x1000 " BA ,Base address (physical address)" bitfld.long 0x00 2.--6. " SIZE ,Size of instruction TCM on reads" "None,Reserved,Reserved,4KB,8KB,16KB,32KB,64KB,128KB,256KB,512KB,1MB,2MB,4MB,8MB,16M,32M,64M,128M,256M,512M,1G,2G,4G,?..." bitfld.long 0x00 0. " EN ,Enable instruction TCM" "Disabled,Enabled" rgroup.long c15:0x29++0x00 line.long 0x00 "TCMSEL,TCM Selection Register" textline " " group.long c15:0x10f++0x00 line.long 0x00 "NAXIPIRR,Normal AXI Peripheral Interface Region Register" hexmask.long 0x00 12.--31. 0x1000 " BA ,Base address of the interface" bitfld.long 0x00 2.--6. " SIZE ,Size of the interface configured during integration" "None,Reserved,Reserved,4KB,8KB,16KB,32KB,64KB,128KB,256KB,512KB,1MB,2MB,4MB,8MB,16M,32M,64M,128M,256M,512M,1G,2G,4G,?..." bitfld.long 0x00 0. " EN ,Interface enable" "Disabled,Enabled" group.long c15:0x20f++0x00 line.long 0x00 "VAXIPIRR,Virtual AXI Peripheral Interface Region Register" hexmask.long 0x00 12.--31. 0x1000 " BA ,Base address of the interface" bitfld.long 0x00 2.--6. " SIZE ,Size of the interface configured during integration" "None,Reserved,Reserved,4KB,8KB,16KB,32KB,64KB,128KB,256KB,512KB,1MB,2MB,4MB,8MB,16M,32M,64M,128M,256M,512M,1G,2G,4G,?..." bitfld.long 0x00 0. " EN ,Interface enable" "Disabled,Enabled" group.long c15:0x30f++0x00 line.long 0x00 "AHBPIRR,AHB Peripheral Interface Region Register" hexmask.long 0x00 12.--31. 0x1000 " BA ,Base address of the interface" bitfld.long 0x00 2.--6. " SIZE ,Size of the interface configured during integration" "None,Reserved,Reserved,4KB,8KB,16KB,32KB,64KB,128KB,256KB,512KB,1MB,2MB,4MB,8MB,16M,32M,64M,128M,256M,512M,1G,2G,4G,?..." bitfld.long 0x00 0. " EN ,Interface enable" "Disabled,Enabled" tree.end width 0xC tree "Cache Control and Configuration" rgroup.long c15:0x1100++0x00 line.long 0x00 "CLIDR,Cache Level ID Register" bitfld.long 0x00 27.--29. " LOU ,Level of Unification" "0,1,2,3,4,5,6,7" bitfld.long 0x00 24.--26. " LOC ,Level of Coherency" "Level 1,Level 2,Level 3,Level 4,Level 5,Level 6,Level 7,Level 8" textline " " bitfld.long 0x00 21.--23. " CL8 ,Cache Level (CL) 8" "0,1,2,3,4,5,6,7" bitfld.long 0x00 18.--20. " CL7 ,Cache Level (CL) 7" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 15.--17. " CL6 ,Cache Level (CL) 6" "0,1,2,3,4,5,6,7" bitfld.long 0x00 12.--14. " CL5 ,Cache Level (CL) 5" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 9.--11. " CL4 ,Cache Level (CL) 4" "0,1,2,3,4,5,6,7" bitfld.long 0x00 6.--8. " CL3 ,Cache Level (CL) 3" "0,1,2,3,4,5,6,7" textline " " bitfld.long 0x00 3.--5. " CL2 ,Cache Level (CL) 2" "0,1,2,3,4,5,6,7" bitfld.long 0x00 0.--2. " CL1 ,Cache Level (CL) 1" "0,1,2,3,4,5,6,7" rgroup.long c15:0x1700++0x00 line.long 0x00 "AIDR,Auxiliary ID Register" rgroup.long c15:0x1000++0x00 line.long 0x00 "CCSIDR,Cache Size ID Register" bitfld.long 0x00 31. " WT ,Write-Through" "Not supported,Supported" bitfld.long 0x00 30. " WB ,Write-Back" "Not supported,Supported" textline " " bitfld.long 0x00 29. " RA ,Read-Allocate" "Not supported,Supported" bitfld.long 0x00 28. " WA ,Write-Allocate" "Not supported,Supported" textline " " hexmask.long.word 0x00 13.--27. 1. " NUMSETS ,Number of sets" hexmask.long.word 0x00 3.--12. 1. " ASSOCIATIVITY ,Associativity" textline " " bitfld.long 0x00 0.--2. " LINESIZE ,Number of words in each cache line" "0,1,2,3,4,5,6,7" group.long c15:0x2000++0x00 line.long 0x0 "CSSELR,Cache Size Selection Register" bitfld.long 0x00 1.--3. " LEVEL ,Cache level to select" "0,1,2,3,4,5,6,7" bitfld.long 0x00 0. " IND ,Instruction or data or unified cache to use" "Data/unified,Instruction" group.long c15:0x03f++0x00 line.long 0x00 "CFLR,Correctable Fault Location Register" bitfld.long 0x00 26.--29. " WAY ,Way of the error" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 24.--25. " SIDE ,Source of the error" "0,1,2,3" textline " " hexmask.long.word 0x00 5.--13. 1. " INDEX ,index of the location where the error occurred" bitfld.long 0x00 0.--1. " TYPE ,Type of access that caused the error" "Instruction cache,Data cache,Reserved,ACP" group.long c15:0x5f++0x00 line.long 0x00 "IADCR,Invalidate All Data Cache Register" bitfld.long 0x00 30.--31. " WAY ,Cache way to invalidate or clean" "0,1,2,3" hexmask.long.byte 0x00 5.--10. 1. " SET ,Cache set to invalidate or clean" group.long c15:0xef++0x00 line.long 0x00 "CSOR,Cache Size Override Register" bitfld.long 0x00 4.--7. " Dcache ,Validation data cache size" "4kB,8kB,Reserved,16kB,Reserved,Reserved,Reserved,32kB,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,64kB" bitfld.long 0x00 0.--3. " Icache ,Validation instruction cache size" "4kB,8kB,Reserved,16kB,Reserved,Reserved,Reserved,32kB,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,64kB" tree.end width 12. tree "System Performance Monitor" group.long c15:0xc9++0x00 line.long 0x00 "PMCR,Performance Monitor Control Register" hexmask.long.byte 0x00 24.--31. 1. " IMP ,Implementer code" hexmask.long.byte 0x00 16.--23. 1. " IDCODE ,Identification code" bitfld.long 0x00 11.--15. " N ,Number of counters implemented" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 5. " DP ,Disable PMCCNTR when prohibited" "No,Yes" textline " " bitfld.long 0x00 4. " X ,Export enable" "Disabled,Enabled" bitfld.long 0x00 3. " D ,Clock divider" "Every cycle,64th cycle" bitfld.long 0x00 2. " C ,Clock counter reset" "No action,Reset" bitfld.long 0x00 1. " P ,Event counter reset" "No action,Reset" textline " " bitfld.long 0x00 0. " E ,Enable" "Disabled,Enabled" group.long c15:0x1c9++0x00 line.long 0x00 "PMCNTENSET,Count Enable Set Register" eventfld.long 0x00 31. " C ,CCNT Enabled / Enable / Disable CCNT" "Disabled,Enabled" eventfld.long 0x00 2. " P2 ,PMN2 Enabled / Enable / Disable counter" "Disabled,Enabled" eventfld.long 0x00 1. " P1 ,PMN1 Enabled / Enable / Disable counter" "Disabled,Enabled" eventfld.long 0x00 0. " P0 ,PMN0 Enabled / Enable / Disable counter" "Disabled,Enabled" group.long c15:0x2c9++0x00 line.long 0x0 "PMCNTENCLR,Count Enable Clear Register" eventfld.long 0x00 31. " C ,CCNT Enabled / Enable / Disable CCNT" "Disabled,Enabled" eventfld.long 0x00 2. " P2 ,PMN2 Enabled / Enable / Disable counter" "Disabled,Enabled" eventfld.long 0x00 1. " P1 ,PMN1 Enabled / Enable / Disable counter" "Disabled,Enabled" eventfld.long 0x00 0. " P0 ,PMN0 Enabled / Enable / Disable counter" "Disabled,Enabled" group.long c15:0x3c9++0x00 line.long 0x0 "PMOVSR,Overflow Flag Status Register" eventfld.long 0x00 31. " C ,CCNT overflowed" "No overflow,Overflow" eventfld.long 0x00 2. " P2 ,PMN2 overflowed" "No overflow,Overflow" eventfld.long 0x00 1. " P1 ,PMN1 overflowed" "No overflow,Overflow" eventfld.long 0x00 0. " P0 ,PMN0 overflowed" "No overflow,Overflow" group.long c15:0x4c9++0x00 line.long 0x0 "PMSWINC,Software Increment Register" eventfld.long 0x00 2. " P2 ,Increment PMN2" "No action,Increment" eventfld.long 0x00 1. " P1 ,Increment PMN1" "No action,Increment" eventfld.long 0x00 0. " P0 ,Increment PMN0" "No action,Increment" group.long c15:0x01d9++0x00 line.long 0x00 "PMXEVTYPER,Event Type Selection Register" hexmask.long.byte 0x00 0.--7. 1. " SEL ,Event number selected" group.long c15:0x02d9++0x00 line.long 0x00 "PMXEVCNTR,Event Count Register" group.long c15:0x5c9++0x00 line.long 0x00 "PMSELR,Performance Counter Selection Register" bitfld.long 0x00 0.--4. " SEL ,Counter select" "0,1,2,?..." group.long c15:0xd9++0x00 line.long 0x00 "PMCCNTR,Cycle Count Register" group.long c15:0x01d9++0x00 saveout c15:0x5C9 %l 0x0 line.long 0x00 "ESR0,Event Selection Register 0" hexmask.long.byte 0x00 0.--7. 1. " SEL ,Event Selection" group.long c15:0x02d9++0x00 saveout c15:0x5C9 %l 0x0 line.long 0x00 "PMCR0,Performance Monitor Count Register 0" hexmask.long 0x00 0.--31. 1. " PMC ,Performance Monitor Count" group.long c15:0x01d9++0x00 saveout c15:0x5C9 %l 0x1 line.long 0x00 "ESR1,Event Selection Register 1" hexmask.long.byte 0x00 0.--7. 1. " SEL ,Event Selection" group.long c15:0x02d9++0x00 saveout c15:0x5C9 %l 0x1 line.long 0x00 "PMCR1,Performance Monitor Count Register 1" hexmask.long 0x00 0.--31. 1. " PMC ,Performance Monitor Count" group.long c15:0x01d9++0x00 saveout c15:0x5C9 %l 0x2 line.long 0x00 "ESR2,Event Selection Register 2" hexmask.long.byte 0x00 0.--7. 1. " SEL ,Event Selection" group.long c15:0x02d9++0x00 saveout c15:0x5C9 %l 0x2 line.long 0x00 "PMCR2,Performance Monitor Count Register 2" hexmask.long 0x00 0.--31. 1. " PMC ,Performance Monitor Count" group.long c15:0xe9++0x00 line.long 0x00 "PMUSERENR,User Enable Register" bitfld.long 0x00 0. " EN ,User mode access to performance monitor and validation registers" "Not allowed,Allowed" group.long c15:0x1e9++0x00 line.long 0x00 "PMINTENSET,Interrupt Enable Set Register" eventfld.long 0x00 31. " C ,Interrupt on CCNT Overflow Enabled / Enable / Disable Interrupt" "Disabled,Enabled" eventfld.long 0x00 2. " P2 ,Interrupt on PMN2 Overflow Enabled / Enable / Disable Interrupt" "Disabled,Enabled" eventfld.long 0x00 1. " P1 ,Interrupt on PMN1 Overflow Enabled / Enable / Disable Interrupt" "Disabled,Enabled" eventfld.long 0x00 0. " P0 ,Interrupt on PMN0 Overflow Enabled / Enable / Disable Interrupt" "Disabled,Enabled" group.long c15:0x2e9++0x00 line.long 0x00 "PMINTENCLR,Interrupt Enable Clear Register" eventfld.long 0x00 31. " C ,Interrupt on CCNT Overflow Enabled / Enable / Disable Interrupt" "Disabled,Enabled" eventfld.long 0x00 2. " P2 ,Interrupt on PMN2 Overflow Enabled / Enable / Disable Interrupt" "Disabled,Enabled" eventfld.long 0x00 1. " P1 ,Interrupt on PMN1 Overflow Enabled / Enable / Disable Interrupt" "Disabled,Enabled" eventfld.long 0x00 0. " P0 ,Interrupt on PMN0 Overflow Enabled / Enable / Disable Interrupt" "Disabled,Enabled" tree "Validation Registers" group.long c15:0x01f++0x00 line.long 0x00 "IRQESR,nVAL IRQ Enable Set Register" bitfld.long 0x00 31. " C ,CCNT overflow IRQ request" "Not requested,Requested" bitfld.long 0x00 2. " P2 ,PMXEVCNTR2 overflow IRQ request" "Not requested,Requested" bitfld.long 0x00 1. " P1 ,PMXEVCNTR1 overflow IRQ request" "Not requested,Requested" bitfld.long 0x00 0. " P0 ,PMXEVCNTR0 overflow IRQ request" "Not requested,Requested" group.long c15:0x11f++0x00 line.long 0x00 "FIQESR,nVAL FIQ Enable Set Register" bitfld.long 0x00 31. " C ,CCNT overflow FIQ request" "Not requested,Requested" bitfld.long 0x00 2. " P2 ,PMXEVCNTR2 overflow FIQ request" "Not requested,Requested" bitfld.long 0x00 1. " P1 ,PMXEVCNTR1 overflow FIQ request" "Not requested,Requested" bitfld.long 0x00 0. " P0 ,PMXEVCNTR0 overflow FIQ request" "Not requested,Requested" group.long c15:0x21f++0x00 line.long 0x00 "RESR,nVAL Reset Enable Set Register" bitfld.long 0x00 31. " C ,CCNT overflow reset request" "Not requested,Requested" bitfld.long 0x00 2. " P2 ,PMXEVCNTR2 overflow reset request" "Not requested,Requested" bitfld.long 0x00 1. " P1 ,PMXEVCNTR1 overflow reset request" "Not requested,Requested" bitfld.long 0x00 0. " P0 ,PMXEVCNTR0 overflow reset request" "Not requested,Requested" group.long c15:0x31f++0x00 line.long 0x00 "RESR,VAL Debug Request Enable Set Register" bitfld.long 0x00 31. " C ,CCNT overflow debug request" "Not requested,Requested" bitfld.long 0x00 2. " P2 ,PMXEVCNTR2 overflow debug request" "Not requested,Requested" bitfld.long 0x00 1. " P1 ,PMXEVCNTR1 overflow debug request" "Not requested,Requested" bitfld.long 0x00 0. " P0 ,PMXEVCNTR0 overflow debug request" "Not requested,Requested" group.long c15:0x41f++0x00 line.long 0x00 "IRQECR,VAL IRQ Enable Clear Register" eventfld.long 0x00 31. " C ,CCNT overflow IRQ request" "Not requested,Requested" eventfld.long 0x00 2. " P2 ,PMXEVCNTR2 overflow IRQ request" "Not requested,Requested" eventfld.long 0x00 1. " P1 ,PMXEVCNTR1 overflow IRQ request" "Not requested,Requested" eventfld.long 0x00 0. " P0 ,PMXEVCNTR0 overflow IRQ request" "Not requested,Requested" group.long c15:0x51f++0x00 line.long 0x00 "FIQECR,VAL FIQ Enable Clear Register" eventfld.long 0x00 31. " C ,CCNT overflow FIQ request" "Not requested,Requested" eventfld.long 0x00 2. " P2 ,PMXEVCNTR2 overflow FIQ request" "Not requested,Requested" eventfld.long 0x00 1. " P1 ,PMXEVCNTR1 overflow FIQ request" "Not requested,Requested" eventfld.long 0x00 0. " P0 ,PMXEVCNTR0 overflow FIQ request" "Not requested,Requested" group.long c15:0x61f++0x00 line.long 0x00 "RECR,nVAL Reset Enable Clear Register" eventfld.long 0x00 31. " C ,CCNT overflow reset request" "Not requested,Requested" eventfld.long 0x00 2. " P2 ,PMXEVCNTR2 overflow reset request" "Not requested,Requested" eventfld.long 0x00 1. " P1 ,PMXEVCNTR1 overflow reset request" "Not requested,Requested" eventfld.long 0x00 0. " P0 ,PMXEVCNTR0 overflow reset request" "Not requested,Requested" group.long c15:0x71f++0x00 line.long 0x00 "DRECR,VAL Debug Request Enable Clear Register" eventfld.long 0x00 31. " C ,CCNT overflow debug request" "Not requested,Requested" eventfld.long 0x00 2. " P2 ,PMXEVCNTR2 overflow debug request" "Not requested,Requested" eventfld.long 0x00 1. " P1 ,PMXEVCNTR1 overflow debug request" "Not requested,Requested" eventfld.long 0x00 0. " P0 ,PMXEVCNTR0 overflow debug request" "Not requested,Requested" tree.end tree.end width 11. width 18. tree "Debug Registers" tree "Processor Identifier Registers" rgroup.long c14:832.++0x00 line.long 0x00 "MIDR,Main ID Register" hexmask.long.byte 0x0 24.--31. 0x1 " IMPL ,Implementer code" hexmask.long.byte 0x0 20.--23. 0x1 " SPECREV ,Variant number" textline " " hexmask.long.byte 0x0 16.--19. 0x1 " ARCH ,Architecture" hexmask.long.word 0x0 4.--15. 0x1 " PARTNUM ,Part Number" textline " " hexmask.long.byte 0x0 0.--3. 0x1 " REV ,Layout Revision" rgroup.long c14:833.++0x00 line.long 0x00 "CACHETYPE,Cache Type Register" bitfld.long 0x00 16.--19. " DMINLINE ,Words of Smallest Line Length in L1 or L2 Data Cache Number" "Reserved,Reserved,Reserved,Reserved,16x32-bit words,?..." bitfld.long 0x00 14.--15. " L1_IPOLICY ,VIPT Instruction Cache Support" "Reserved,Reserved,Supported,?..." textline " " bitfld.long 0x00 0.--3. " IMINLINE ,Words of Smallest Line Length in L1 or L2 Instruction Cache Number" "Reserved,Reserved,Reserved,Reserved,16x32-bit words,?..." rgroup.long c14:834.++0x00 line.long 0x00 "TCMTR,TCM Type Register" group.long c14:835.++0x00 line.long 0x00 "AMIDR,Alias of MIDR" rgroup.long c14:836.++0x00 line.long 0x00 "MPUTR,MPU Type Register" rgroup.long c14:837.++0x00 line.long 0x00 "MPIDR,Multiprocessor Affinity Register" group.long c14:838.++0x00 line.long 0x00 "AMIDR0,Alias of MIDR" group.long c14:839.++0x00 line.long 0x00 "AMIDR1,Alias of MIDR" rgroup.long c14:840.++0x00 line.long 0x00 "ID_PFR0,Processor Feature Register 0" bitfld.long 0x00 12.--15. " STATE3 ,Thumb-2 Execution Environment (Thumb-2EE) Support" "Reserved,Supported,?..." bitfld.long 0x00 8.--11. " STATE2 ,Java Extension Interface Support" "Not supported,?..." textline " " bitfld.long 0x00 4.--7. " STATE1 ,Thumb Encoding Supported by the Processor Type" "Reserved,Reserved,Reserved,Supported,?..." bitfld.long 0x00 0.--3. " STATE0 ,ARM Instruction Set Support" "Reserved,Supported,?..." rgroup.long c14:841.++0x00 line.long 0x00 "ID_PFR1,Processor Feature Register 1" bitfld.long 0x00 8.--11. " MPM ,Microcontroller Programmer's Model Support" "Supported,?..." bitfld.long 0x00 4.--7. " SE ,Security Extensions Architecture v1 Support" "Reserved,Supported,?..." textline " " bitfld.long 0x00 0.--3. " PM ,Standard ARMv4 Programmer's Model Support" "Reserved,Supported,?..." rgroup.long c14:842.++0x00 line.long 0x00 "ID_DFR0,Debug Feature Register 0" bitfld.long 0x00 20.--23. " MDM_MM ,Microcontroller Debug Model Support" "Not supported,?..." bitfld.long 0x00 16.--19. " TDM_MM ,Trace Debug Model (Memory-Mapped) Support" "Reserved,Supported,?..." textline " " bitfld.long 0x00 12.--15. " TDM_CB ,Coprocessor-Based Trace Debug Model Support" "Not supported,?..." bitfld.long 0x00 8.--11. " CDM_MM ,Memory-Mapped Debug Model Support" "Reserved,Reserved,Reserved,Reserved,Supported,?..." textline " " bitfld.long 0x00 4.--7. " SDM_CB ,Secure Debug Model (Coprocessor) Support" "Not supported,?..." bitfld.long 0x00 0.--3. " CDM_CB ,Coprocessor Debug Model Support" "Not supported,?..." rgroup.long c14:843.++0x00 line.long 0x00 "ID_AFR0,Auxiliary Feature Register 0" rgroup.long c14:844.++0x00 line.long 0x00 "ID_MMFR0,Processor Feature Register 0" bitfld.long 0x00 28.--31. " IT ,Instruction Type Support" "Reserved,Reserved,Reserved,Supported,?..." bitfld.long 0x00 24.--27. " FCSE ,Fast Context Switch Memory Mappings Support" "Reserved,Supported,?..." textline " " bitfld.long 0x00 20.--23. " ACR ,Auxiliary Control Register Support" "Reserved,Supported,?..." bitfld.long 0x00 16.--19. " TCM ,TCM and Associated DMA Support" "Not supported,?..." textline " " bitfld.long 0x00 12.--15. " CC_PLEA ,Cache Coherency With PLE Agent/Shared Memory Support" "Not supported,?..." bitfld.long 0x00 8.--11. " CC_CPUA ,Cache Coherency Support With CPU Agent/Shared Memory Support" "Not supported,?..." textline " " bitfld.long 0x00 4.--7. " PMSA ,Physical Memory System Architecture (PMSA) Support" "Not supported,?..." bitfld.long 0x00 0.--3. " VMSA ,Virtual Memory System Architecture (VMSA) Support" "Reserved,Reserved,Reserved,Supported,?..." rgroup.long c14:845.++0x00 line.long 0x00 "ID_MMFR1,Processor Feature Register 1" bitfld.long 0x00 28.--31. " BTB ,Branch Target Buffer Support" "Reserved,Reserved,Not required,?..." bitfld.long 0x00 24.--27. " L1TCO ,Test and Clean Operations on Data Cache/Harvard/Unified Architecture Support" "Not supported,?..." textline " " bitfld.long 0x00 20.--23. " L1UCMO ,L1 Cache/All Maintenance Operations/Unified Architecture Support" "Not supported,?..." bitfld.long 0x00 16.--19. " L1HCMO ,L1 Cache/All Maintenance Operations/Harvard Architecture Support" "Supported,?..." textline " " bitfld.long 0x00 12.--15. " L1UCLMOSW ,L1 Cache Line Maintenance Operations by Set and Way/Unified Architecture Support" "Not supported,?..." bitfld.long 0x00 8.--11. " L1HCLMOSW ,L1 Cache Line Maintenance Operations by Set and Way/Harvard Architecture Support" "Supported,?..." textline " " bitfld.long 0x00 4.--7. " L1UCLMOMVA ,L1 Cache Line Maintenance Operations by MVA/Unified Architecture Support" "Not supported,?..." bitfld.long 0x00 0.--3. " L1HCLMOMVA ,L1 Cache Line Maintenance Operations by MVA/Harvard Architecture" "Supported,?..." rgroup.long c14:846.++0x00 line.long 0x00 "ID_MMFR2,Processor Feature Register 2" bitfld.long 0x00 28.--31. " HAF ,Hardware Access Flag Support" "Not supported,?..." bitfld.long 0x00 24.--27. " WFI ,Wait for Interrupt Stalling Support" "Reserved,Supported,?..." textline " " bitfld.long 0x00 20.--23. " MBF ,Memory Barrier Operations Support" "Reserved,Reserved,Supported,?..." bitfld.long 0x00 16.--19. " UTLBMO ,TLB Maintenance Operations/Unified Architecture Support" "Not supported,?..." textline " " bitfld.long 0x00 12.--15. " HTLBMO ,TLB Maintenance Operations/Harvard Architecture Support" "Reserved,Reserved,Supported,?..." bitfld.long 0x00 8.--11. " HL1CMRO ,Cache Maintenance Range Operations/Harvard Architecture Support" "Not supported,?..." textline " " bitfld.long 0x00 4.--7. " HL1BPCRO ,Background Prefetch Cache Range Operations/Harvard Architecture Support" "Not supported,?..." bitfld.long 0x00 0.--3. " HL1FPCRO ,Foreground Prefetch Cache Range Operations/Harvard Architecture Support" "Not supported,?..." rgroup.long c14:847.++0x00 line.long 0x00 "ID_MMFR3,Processor Feature Register 3" bitfld.long 0x00 4.--7. " HCMOSW ,Invalidate Cache by Set and Way/Clean by Set and Way/Invalidate and Clean by Set and Way Support" "Reserved,Supported,?..." bitfld.long 0x00 0.--3. " HCMOMVA ,Invalidate Cache by MVA/Clean by MVA/Invalidate and Clean by MVA/Invalidate All Support" "Reserved,Supported,?..." rgroup.long c14:848.++0x00 line.long 0x00 "ID_ISAR0,ISA Feature Register 0" bitfld.long 0x00 24.--27. " DIVI ,Divide Instructions Support" "Not supported,?..." bitfld.long 0x00 20.--23. " DEBI ,Debug Instructions Support" "Reserved,Supported,?..." textline " " bitfld.long 0x00 16.--19. " CI ,Coprocessor Instructions Support" "Not supported,?..." bitfld.long 0x00 12.--15. " CBI ,Combined Compare and Branch Instructions Support" "Reserved,Supported,?..." textline " " bitfld.long 0x00 8.--11. " BI ,Bitfield Instructions Support" "Reserved,Supported,?..." bitfld.long 0x00 4.--7. " BCI ,Bit Counting Instructions Support" "Reserved,Supported,?..." textline " " bitfld.long 0x00 0.--3. " AI ,Atomic Load and Store Instructions Support" "Reserved,Supported,?..." rgroup.long c14:849.++0x00 line.long 0x00 "ID_ISAR1,ISA Feature Register 1" bitfld.long 0x00 28.--31. " JI ,Jazelle Instructions Support" "Reserved,Supported,?..." bitfld.long 0x00 24.--27. " INTI ,Instructions That Branch Between ARM and Thumb Code Support" "Reserved,Reserved,Supported,?..." textline " " bitfld.long 0x00 20.--23. " IMMI ,Immediate Instructions Support" "Reserved,Supported,?..." bitfld.long 0x00 16.--19. " ITEI ,If Then Instructions Support" "Reserved,Supported,?..." textline " " bitfld.long 0x00 12.--15. " EXTI ,Sign or Zero Extend Instructions Support" "Reserved,Reserved,Supported,?..." bitfld.long 0x00 8.--11. " E2I ,Exception 2 Instructions Support" "Reserved,Supported,?..." textline " " bitfld.long 0x00 4.--7. " E1I ,Exception 1 Instructions Support" "Reserved,Supported,?..." bitfld.long 0x00 0.--3. " ENDI ,Endianness Control Instructions Support" "Reserved,Supported,?..." rgroup.long c14:850.++0x00 line.long 0x00 "ID_ISAR2,ISA Feature Register 2" bitfld.long 0x00 28.--31. " RI ,Reversal Instructions Support" "Reserved,Reserved,Supported,?..." bitfld.long 0x00 24.--27. " PSRI ,PSR Instructions Support" "Reserved,Supported,?..." textline " " bitfld.long 0x00 20.--23. " UMI ,Advanced Unsigned Multiply Instructions Support" "Reserved,Reserved,Supported,?..." bitfld.long 0x00 16.--19. " SMI ,Advanced Signed Multiply Instructions Support" "Reserved,Reserved,Reserved,Supported,?..." textline " " bitfld.long 0x00 12.--15. " MI ,Multiply Instructions Support" "Reserved,Reserved,Supported,?..." bitfld.long 0x00 8.--11. " II ,Multi-Access Interruptible Instructions Support" "Supported,?..." textline " " bitfld.long 0x00 4.--7. " MHI ,Memory Hint Instructions Support" "Reserved,Reserved,Reserved,Supported,?..." bitfld.long 0x00 0.--3. " LSI ,Load and Store Instructions Support" "Reserved,Supported,?..." rgroup.long c14:851.++0x00 line.long 0x00 "ID_ISAR3,ISA Feature Register 3" bitfld.long 0x00 28.--31. " T2E ,Thumb-2 Extensions Support" "Reserved,Supported,?..." bitfld.long 0x00 24.--27. " NOPI ,True NOP Instructions Support" "Reserved,Supported,?..." textline " " bitfld.long 0x00 20.--23. " TCI ,Thumb Copy Instructions Support" "Reserved,Supported,?..." bitfld.long 0x00 16.--19. " TBI ,Table Branch Instructions Support" "Reserved,Reserved,Supported,?..." textline " " bitfld.long 0x00 12.--15. " SPI ,Synchronization Primitive Instructions Support" "Reserved,Reserved,Supported,?..." bitfld.long 0x00 8.--11. " SWII ,SWI Instructions Support" "Reserved,Supported,?..." textline " " bitfld.long 0x00 4.--7. " SIMDI ,Single Instruction Multiple Data (SIMD) Instructions Support" "Reserved,Reserved,Reserved,Supported,?..." bitfld.long 0x00 0.--3. " SI ,Saturate Instructions Support" "Reserved,Supported,?..." rgroup.long c14:852.++0x00 line.long 0x00 "ID_ISAR4,ISA Feature Register 4" bitfld.long 0x00 20.--23. " EI ,Exclusive Instructions Support" "Reserved,Supported,?..." bitfld.long 0x00 16.--19. " BI ,Barrier Instructions Support" "Reserved,Supported,?..." textline " " bitfld.long 0x00 12.--15. " SMII ,SMI Instructions Support" "Reserved,Supported,?..." bitfld.long 0x00 8.--11. " WBI ,Write-Back Instructions Support" "Reserved,Supported,?..." textline " " bitfld.long 0x00 4.--7. " WSI ,With-Shift Instructions Support" "Reserved,Reserved,Reserved,Reserved,Supported,?..." bitfld.long 0x00 0.--3. " UI ,Unprivileged Instructions Support" "Reserved,Reserved,Supported,?..." rgroup.long c14:853.++0x00 line.long 0x00 "ID_ISAR5,ISA Feature Register 5" tree.end width 15. tree "Coresight Management Registers" group.long c14:960.++0x00 line.long 0x00 "DBGITCTRL,Integration Mode Control Register" bitfld.long 0x00 0. " INTMODE ,Processor integration mode" "Normal,Integration" group.long c14:1000.++0x00 line.long 0x00 "DBGCLAIMSET,Claim Tag Set Register" hexmask.long.byte 0x00 0.--7. 1. " CTS ,Claim tag set" group.long c14:1001.++0x00 line.long 0x00 "DBGCLAIMCLR,Claim Tag Clear Register" hexmask.long.byte 0x00 0.--7. 1. " CTC ,Claim tag clear" wgroup.long c14:1004.++0x00 line.long 0x00 "DBGLAR,Lock Access Register" rgroup.long c14:1005.++0x00 line.long 0x00 "DBGLSR,Lock Status Register" bitfld.long 0x00 2. " 32BA ,Indicate that a 32-bit access is required to write the key to the DBGLAR" "No,Yes" textline " " bitfld.long 0x00 1. " LB ,Lock bit" "Not locked,Locked" bitfld.long 0x00 0. " LIB ,Lock implemented bit" "Not locked,Locked" rgroup.long c14:1006.++0x00 line.long 0x00 "DBGAUTHSTATUS,Authentication Status Register" bitfld.long 0x00 7. " SNDFI ,Secure non-invasive debug features implemented" "Not implemented,Implemented" bitfld.long 0x00 6. " SNDFE ,Secure non-invasive debug features enable" "Disabled,Enabled" textline " " bitfld.long 0x00 5. " SIDFI ,Secure invasive debug features implemented" "Not implemented,Implemented" bitfld.long 0x00 4. " SIDFE ,Secure invasive debug features enabled" "Disabled,Enabled" rgroup.long c14:1011.++0x00 line.long 0x00 "DBGDEVTYPE,Device Type Register" hexmask.long.byte 0x00 4.--7. 1. " SUBTYPE ,Subtype" hexmask.long.byte 0x00 0.--3. 1. " MAIN_CLASS ,Main class" tree.end textline " " width 12. rgroup.long c14:0.++0x0 line.long 0x0 "DBGDIDR,Debug ID Register" bitfld.long 0x0 28.--31. " WRP ,Number of Watchpoint Register Pairs" "1,2,3,4,5,6,7,8,?..." bitfld.long 0x0 24.--27. " BRP ,Number of Breakpoint Register Pairs" "1,2,3,4,5,6,7,8,?..." textline " " bitfld.long 0x0 20.--23. " CTX_CMP ,Number of BRPs with Context ID Comparison Capability" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16" hexmask.long.byte 0x0 16.--19. 1. " VERSION ,Debug Architecture Version" textline " " bitfld.long 0x0 15. " DEVID ,Debug Device ID" "Low,High" bitfld.long 0x0 14. " NSUHD ,Secure User halting debug-mode" "Low,High" textline " " bitfld.long 0x0 13. " PCSR ,PC Sample register implemented" "Low,High" bitfld.long 0x0 12. " SE ,Security Extensions implemented" "Low,High" textline " " hexmask.long.byte 0x0 4.--7. 1. " VARIANT ,Implementation-defined Variant Number" hexmask.long.byte 0x0 0.--3. 1. " REVISION ,Implementation-defined Revision Number" group.long c14:34.++0x0 line.long 0x00 "DBGDSCREXT,Debug Status and Control Register" bitfld.long 0x00 30. " RXFULL ,DBGDTRRX Register full" "Empty,Full" bitfld.long 0x00 29. " TXFULL ,DBGDTRTX Register full" "Empty,Full" textline " " bitfld.long 0x00 25. " PIPEADV ,PIPEADV Processor Idle flag" "Not idle,Idle" bitfld.long 0x00 24. " INSTRCOMPL_L ,Latched instruction complete" "Not completed,Completed" textline " " bitfld.long 0x00 20.--21. " EXTDCCMODE ,External DCC access mode field" "Non-blocking,Stall,Fast,?..." bitfld.long 0x00 19. " ADADISCARD ,Asynchronous Data Aborts Discarded bit" "Normal,Abort" bitfld.long 0x00 18. " NS ,Non-secure status bit" "Secure,Non-secure" textline " " bitfld.long 0x00 17. " SPNIDDIS ,Secure Privileged Non-Invasive Debug Disable" "No,Yes" bitfld.long 0x00 16. " SPIDDIS ,Secure Privileged Invasive Debug Disable" "No,Yes" bitfld.long 0x00 15. " MDBGEN ,Monitor debug-mode enable" "Disabled,Enabled" textline " " bitfld.long 0x00 14. " HDBGEN ,Halting debug-mode" "Disabled,Enabled" bitfld.long 0x00 13. " ITREN ,Execute ARM instruction enable" "Disabled,Enabled" bitfld.long 0x00 12. " UDCCDIS ,User mode access to Communications Channel disable" "No,Yes" textline " " bitfld.long 0x00 11. " INTDIS ,Interrupt disable" "No,Yes" bitfld.long 0x00 10. " DBGACK ,Force debug acknowledge" "Normal,Forced" textline " " bitfld.long 0x00 8. " UND_L ,Sticky undefined bit" "Not occurred,Occurred" bitfld.long 0x00 7. " ADABORT ,Asynchronous data abort" "Not aborted,Aborted" bitfld.long 0x00 6. " SDABORT ,Synchronous data abort" "Not aborted,Aborted" textline " " bitfld.long 0x00 2.--5. " MOE ,Method of debug entry field" "Halt Request,Breakpoint,Reserved,BKPT Instruction,External Debug Request,Reserved,Reserved,Reserved,Reserved,Reserved,Synchronous Watchpoint,?..." bitfld.long 0x00 1. " RESTARTED ,Processor restarted" "Pending,Exited" bitfld.long 0x00 0. " HALTED ,Processor halted" "Non-debug,Debug" group.long c14:0x7++0x0 line.long 0x00 "DBGVCR,Debug Vector Catch register" bitfld.long 0x00 7. " FIQVCE_S ,FIQ vector catch in Secure state" "Disabled,Enabled" textline " " bitfld.long 0x00 6. " IRQVCE_S ,IRQ vector catch in Secure state" "Disabled,Enabled" bitfld.long 0x00 4. " DAVCE_S ,Data Abort vector catch in Secure state" "Disabled,Enabled" textline " " bitfld.long 0x00 3. " PAVCE_S ,Prefetch Abort vector catch in Secure state" "Disabled,Enabled" bitfld.long 0x00 2. " SVCVCE_S ,SVC vector catch in Secure state" "Disabled,Enabled" textline " " bitfld.long 0x00 1. " UIVCE_S ,Undefined instruction vector catch in Secure state" "Disabled,Enabled" bitfld.long 0x00 0. " RVCE ,Reset vector catch enable" "Disabled,Enabled" hgroup.long c14:32.++0x0 hide.long 0x00 "DTRRX,Target -> Host Data Transfer Register" in group.long c14:35.++0x00 line.long 0x0 "DTRTX,Host -> Target Data Transfer Register" hexmask.long 0x00 0.--31. 1. " HTD ,Host -> target data" group.long c14:10.++0x0 line.long 0x00 "DBGDSCCR,Debug State Cache Control Register" bitfld.long 0x00 2. " NWT ,Write through disable" "No,Yes" bitfld.long 0x00 1. " NIL ,L1 instruction cache line-fills disable" "No,Yes" textline " " bitfld.long 0x00 0. " NDL ,L1 data cache line-fills disable" "No,Yes" wgroup.long c14:33.++0x0 line.long 0x00 "DBGITR,Instruction Transfer Register" wgroup.long c14:36.++0x0 line.long 0x00 "DBGDRCR,Debug Run Control Register" bitfld.long 0x00 4. " CMR ,Cancel memory requests" "Not cancel,Cancel" bitfld.long 0x00 3. " CSPA ,Clear Sticky Pipeline Advance bit" "No effect,Clear" textline " " bitfld.long 0x00 2. " CSE ,Clear Sticky Exceptions bits" "No effect,Clear" bitfld.long 0x00 1. " RR ,Restart request" "No effect,Restart" textline " " bitfld.long 0x00 0. " HR ,Halt request" "No effect,Halt" textline " " rgroup.long c14:193.++0x0 line.long 0x00 "DBGOSLSR,Operating System Lock Status Register" bitfld.long 0x00 1. " LOCK_IMP_BIT ,Indicate whether the OS lock functionality is implemented" "Not implemented,Implemented" group.long c14:196.++0x0 line.long 0x00 "DBGPRCR,Device Power-down and Reset Control Register" bitfld.long 0x00 2. " HCWR ,Hold core warm reset" "Not held,Held" textline " " bitfld.long 0x00 1. " CWRR ,Reset reguest" "Not requested,Requested" bitfld.long 0x00 0. " CORENPDRQ ,Core no powerdown request" "Power-down,Emulate" rgroup.long c14:197.++0x0 line.long 0x00 "DBGPRSR,Device Power-down and Reset Status Register" bitfld.long 0x00 3. " SR ,Sticky Reset Status" "Not reset,Reset" bitfld.long 0x00 2. " R ,Reset Status" "No reset,Reset" textline " " bitfld.long 0x00 1. " SPD ,Sticky Power-down Status" "Not reset,Reset" bitfld.long 0x00 0. " PU ,Power-up Status" "Powered down,Powered up" tree.end width 7. tree "Breakpoint Registers" group.long c14:64.++0x0 line.long 0x00 "BVR0,Breakpoint Value 0 Register" hexmask.long 0x00 0.--31. 1. " BV0 ,Breakpoint Value 0" group.long c14:80.++0x0 line.long 0x00 "BCR0,Breakpoint Control 0 Register" bitfld.long 0x00 24.--28. " BAM ,Breakpoint Address Mask" "Not masked,Reserved,Reserved,0x7,0xF,0x1F,0x3F,0x7F,0xFF,0x1FF,0x3FF,0x7FF,0xFFF,0x1FFF,0x3FFF,0x7FFF,0xFFFF,0x1FFFF,0x3FFFF,0x7FFFF,0xFFFFF,0x1FFFFF,0x3FFFFF,0x7FFFFF,0xFFFFFF,0x1FFFFFF,0x3FFFFFF,0x7FFFFFF,0xFFFFFFF,0x1FFFFFFF,0x3FFFFFFF,0x7FFFFFFF" bitfld.long 0x00 20.--22. " M ,BVR Meaning" "IVA match,Linked IVA match,Unlinked ID,Linked ID,IVA mismatch,Linked IVA mismatch,?..." bitfld.long 0x00 16.--19. " LBRP ,Linked BRP Number" "BRP,BRP1,BRP2,BRP3,BRP4,BRP5,BRP6,BRP7,BRP8,BRP9,BRP10,BRP11,BRP12,BRP13,BRP14,BRP15" bitfld.long 0x00 14.--15. " SWAC ,Secure World Access Control" "Both,Nonsecure,Secure,?..." textline " " bitfld.long 0x0 8. " BAS ,Byte 3 address select" "0,1" bitfld.long 0x0 7. ",Byte 2 address select" "0,1" bitfld.long 0x0 6. ",Byte 1 address select" "0,1" bitfld.long 0x0 5. ",Byte 0 address select" "0,1" bitfld.long 0x00 1.--2. " S ,Supervisor Access Control" "User/system/supervisor,Privileged,User,Any" bitfld.long 0x00 0. " B ,Breakpoint Enable" "Disabled,Enabled" group.long c14:65.++0x0 line.long 0x00 "BVR1,Breakpoint Value 1 Register" hexmask.long 0x00 0.--31. 1. " BV1 ,Breakpoint Value 1" group.long c14:81.++0x0 line.long 0x00 "BCR1,Breakpoint Control 1 Register" bitfld.long 0x00 24.--28. " BAM ,Breakpoint Address Mask" "Not masked,Reserved,Reserved,0x7,0xF,0x1F,0x3F,0x7F,0xFF,0x1FF,0x3FF,0x7FF,0xFFF,0x1FFF,0x3FFF,0x7FFF,0xFFFF,0x1FFFF,0x3FFFF,0x7FFFF,0xFFFFF,0x1FFFFF,0x3FFFFF,0x7FFFFF,0xFFFFFF,0x1FFFFFF,0x3FFFFFF,0x7FFFFFF,0xFFFFFFF,0x1FFFFFFF,0x3FFFFFFF,0x7FFFFFFF" bitfld.long 0x00 20.--22. " M ,BVR Meaning" "IVA match,Linked IVA match,Unlinked ID,Linked ID,IVA mismatch,Linked IVA mismatch,?..." bitfld.long 0x00 16.--19. " LBRP ,Linked BRP Number" "BRP,BRP1,BRP2,BRP3,BRP4,BRP5,BRP6,BRP7,BRP8,BRP9,BRP10,BRP11,BRP12,BRP13,BRP14,BRP15" bitfld.long 0x00 14.--15. " SWAC ,Secure World Access Control" "Both,Nonsecure,Secure,?..." textline " " bitfld.long 0x0 8. " BAS ,Byte 3 address select" "0,1" bitfld.long 0x0 7. ",Byte 2 address select" "0,1" bitfld.long 0x0 6. ",Byte 1 address select" "0,1" bitfld.long 0x0 5. ",Byte 0 address select" "0,1" bitfld.long 0x00 1.--2. " S ,Supervisor Access Control" "User/system/supervisor,Privileged,User,Any" bitfld.long 0x00 0. " B ,Breakpoint Enable" "Disabled,Enabled" group.long c14:66.++0x0 line.long 0x00 "BVR2,Breakpoint Value 2 Register" hexmask.long 0x00 0.--31. 1. " BV2 ,Breakpoint Value 2" group.long c14:82.++0x0 line.long 0x00 "BCR2,Breakpoint Control 2 Register" bitfld.long 0x00 24.--28. " BAM ,Breakpoint Address Mask" "Not masked,Reserved,Reserved,0x7,0xF,0x1F,0x3F,0x7F,0xFF,0x1FF,0x3FF,0x7FF,0xFFF,0x1FFF,0x3FFF,0x7FFF,0xFFFF,0x1FFFF,0x3FFFF,0x7FFFF,0xFFFFF,0x1FFFFF,0x3FFFFF,0x7FFFFF,0xFFFFFF,0x1FFFFFF,0x3FFFFFF,0x7FFFFFF,0xFFFFFFF,0x1FFFFFFF,0x3FFFFFFF,0x7FFFFFFF" bitfld.long 0x00 20.--22. " M ,BVR Meaning" "IVA match,Linked IVA match,Unlinked ID,Linked ID,IVA mismatch,Linked IVA mismatch,?..." bitfld.long 0x00 16.--19. " LBRP ,Linked BRP Number" "BRP,BRP1,BRP2,BRP3,BRP4,BRP5,BRP6,BRP7,BRP8,BRP9,BRP10,BRP11,BRP12,BRP13,BRP14,BRP15" bitfld.long 0x00 14.--15. " SWAC ,Secure World Access Control" "Both,Nonsecure,Secure,?..." textline " " bitfld.long 0x0 8. " BAS ,Byte 3 address select" "0,1" bitfld.long 0x0 7. ",Byte 2 address select" "0,1" bitfld.long 0x0 6. ",Byte 1 address select" "0,1" bitfld.long 0x0 5. ",Byte 0 address select" "0,1" bitfld.long 0x00 1.--2. " S ,Supervisor Access Control" "User/system/supervisor,Privileged,User,Any" bitfld.long 0x00 0. " B ,Breakpoint Enable" "Disabled,Enabled" group.long c14:67.++0x0 line.long 0x00 "BVR3,Breakpoint Value 3 Register" hexmask.long 0x00 0.--31. 1. " BV3 ,Breakpoint Value 3" group.long c14:83.++0x0 line.long 0x00 "BCR3,Breakpoint Control 3 Register" bitfld.long 0x00 24.--28. " BAM ,Breakpoint Address Mask" "Not masked,Reserved,Reserved,0x7,0xF,0x1F,0x3F,0x7F,0xFF,0x1FF,0x3FF,0x7FF,0xFFF,0x1FFF,0x3FFF,0x7FFF,0xFFFF,0x1FFFF,0x3FFFF,0x7FFFF,0xFFFFF,0x1FFFFF,0x3FFFFF,0x7FFFFF,0xFFFFFF,0x1FFFFFF,0x3FFFFFF,0x7FFFFFF,0xFFFFFFF,0x1FFFFFFF,0x3FFFFFFF,0x7FFFFFFF" bitfld.long 0x00 20.--22. " M ,BVR Meaning" "IVA match,Linked IVA match,Unlinked ID,Linked ID,IVA mismatch,Linked IVA mismatch,?..." bitfld.long 0x00 16.--19. " LBRP ,Linked BRP Number" "BRP,BRP1,BRP2,BRP3,BRP4,BRP5,BRP6,BRP7,BRP8,BRP9,BRP10,BRP11,BRP12,BRP13,BRP14,BRP15" bitfld.long 0x00 14.--15. " SWAC ,Secure World Access Control" "Both,Nonsecure,Secure,?..." textline " " bitfld.long 0x0 8. " BAS ,Byte 3 address select" "0,1" bitfld.long 0x0 7. ",Byte 2 address select" "0,1" bitfld.long 0x0 6. ",Byte 1 address select" "0,1" bitfld.long 0x0 5. ",Byte 0 address select" "0,1" bitfld.long 0x00 1.--2. " S ,Supervisor Access Control" "User/system/supervisor,Privileged,User,Any" bitfld.long 0x00 0. " B ,Breakpoint Enable" "Disabled,Enabled" group.long c14:68.++0x0 line.long 0x00 "BVR4,Breakpoint Value 4 Register" hexmask.long 0x00 0.--31. 1. " BV4 ,Breakpoint Value 4" group.long c14:84.++0x0 line.long 0x00 "BCR4,Breakpoint Control 4 Register" bitfld.long 0x00 24.--28. " BAM ,Breakpoint Address Mask" "Not masked,Reserved,Reserved,0x7,0xF,0x1F,0x3F,0x7F,0xFF,0x1FF,0x3FF,0x7FF,0xFFF,0x1FFF,0x3FFF,0x7FFF,0xFFFF,0x1FFFF,0x3FFFF,0x7FFFF,0xFFFFF,0x1FFFFF,0x3FFFFF,0x7FFFFF,0xFFFFFF,0x1FFFFFF,0x3FFFFFF,0x7FFFFFF,0xFFFFFFF,0x1FFFFFFF,0x3FFFFFFF,0x7FFFFFFF" bitfld.long 0x00 20.--22. " M ,BVR Meaning" "IVA match,Linked IVA match,Unlinked ID,Linked ID,IVA mismatch,Linked IVA mismatch,?..." bitfld.long 0x00 16.--19. " LBRP ,Linked BRP Number" "BRP,BRP1,BRP2,BRP3,BRP4,BRP5,BRP6,BRP7,BRP8,BRP9,BRP10,BRP11,BRP12,BRP13,BRP14,BRP15" bitfld.long 0x00 14.--15. " SWAC ,Secure World Access Control" "Both,Nonsecure,Secure,?..." textline " " bitfld.long 0x0 8. " BAS ,Byte 3 address select" "0,1" bitfld.long 0x0 7. ",Byte 2 address select" "0,1" bitfld.long 0x0 6. ",Byte 1 address select" "0,1" bitfld.long 0x0 5. ",Byte 0 address select" "0,1" bitfld.long 0x00 1.--2. " S ,Supervisor Access Control" "User/system/supervisor,Privileged,User,Any" bitfld.long 0x00 0. " B ,Breakpoint Enable" "Disabled,Enabled" group.long c14:69.++0x0 line.long 0x00 "BVR5,Breakpoint Value 5 Register" hexmask.long 0x00 0.--31. 1. " BV5 ,Breakpoint Value 5" group.long c14:85.++0x0 line.long 0x00 "BCR5,Breakpoint Control 5 Register" bitfld.long 0x00 24.--28. " BAM ,Breakpoint Address Mask" "Not masked,Reserved,Reserved,0x7,0xF,0x1F,0x3F,0x7F,0xFF,0x1FF,0x3FF,0x7FF,0xFFF,0x1FFF,0x3FFF,0x7FFF,0xFFFF,0x1FFFF,0x3FFFF,0x7FFFF,0xFFFFF,0x1FFFFF,0x3FFFFF,0x7FFFFF,0xFFFFFF,0x1FFFFFF,0x3FFFFFF,0x7FFFFFF,0xFFFFFFF,0x1FFFFFFF,0x3FFFFFFF,0x7FFFFFFF" bitfld.long 0x00 20.--22. " M ,BVR Meaning" "IVA match,Linked IVA match,Unlinked ID,Linked ID,IVA mismatch,Linked IVA mismatch,?..." bitfld.long 0x00 16.--19. " LBRP ,Linked BRP Number" "BRP,BRP1,BRP2,BRP3,BRP4,BRP5,BRP6,BRP7,BRP8,BRP9,BRP10,BRP11,BRP12,BRP13,BRP14,BRP15" bitfld.long 0x00 14.--15. " SWAC ,Secure World Access Control" "Both,Nonsecure,Secure,?..." textline " " bitfld.long 0x0 8. " BAS ,Byte 3 address select" "0,1" bitfld.long 0x0 7. ",Byte 2 address select" "0,1" bitfld.long 0x0 6. ",Byte 1 address select" "0,1" bitfld.long 0x0 5. ",Byte 0 address select" "0,1" bitfld.long 0x00 1.--2. " S ,Supervisor Access Control" "User/system/supervisor,Privileged,User,Any" bitfld.long 0x00 0. " B ,Breakpoint Enable" "Disabled,Enabled" group.long c14:70.++0x0 line.long 0x00 "BVR6,Breakpoint Value 6 Register" hexmask.long 0x00 0.--31. 1. " BV6 ,Breakpoint Value 6" group.long c14:86.++0x0 line.long 0x00 "BCR6,Breakpoint Control 6 Register" bitfld.long 0x00 24.--28. " BAM ,Breakpoint Address Mask" "Not masked,Reserved,Reserved,0x7,0xF,0x1F,0x3F,0x7F,0xFF,0x1FF,0x3FF,0x7FF,0xFFF,0x1FFF,0x3FFF,0x7FFF,0xFFFF,0x1FFFF,0x3FFFF,0x7FFFF,0xFFFFF,0x1FFFFF,0x3FFFFF,0x7FFFFF,0xFFFFFF,0x1FFFFFF,0x3FFFFFF,0x7FFFFFF,0xFFFFFFF,0x1FFFFFFF,0x3FFFFFFF,0x7FFFFFFF" bitfld.long 0x00 20.--22. " M ,BVR Meaning" "IVA match,Linked IVA match,Unlinked ID,Linked ID,IVA mismatch,Linked IVA mismatch,?..." bitfld.long 0x00 16.--19. " LBRP ,Linked BRP Number" "BRP,BRP1,BRP2,BRP3,BRP4,BRP5,BRP6,BRP7,BRP8,BRP9,BRP10,BRP11,BRP12,BRP13,BRP14,BRP15" bitfld.long 0x00 14.--15. " SWAC ,Secure World Access Control" "Both,Nonsecure,Secure,?..." textline " " bitfld.long 0x0 8. " BAS ,Byte 3 address select" "0,1" bitfld.long 0x0 7. ",Byte 2 address select" "0,1" bitfld.long 0x0 6. ",Byte 1 address select" "0,1" bitfld.long 0x0 5. ",Byte 0 address select" "0,1" bitfld.long 0x00 1.--2. " S ,Supervisor Access Control" "User/system/supervisor,Privileged,User,Any" bitfld.long 0x00 0. " B ,Breakpoint Enable" "Disabled,Enabled" group.long c14:71.++0x0 line.long 0x00 "BVR7,Breakpoint Value 7 Register" hexmask.long 0x00 0.--31. 1. " BV7 ,Breakpoint Value 7" group.long c14:87.++0x0 line.long 0x00 "BCR7,Breakpoint Control 7 Register" bitfld.long 0x00 24.--28. " BAM ,Breakpoint Address Mask" "Not masked,Reserved,Reserved,0x7,0xF,0x1F,0x3F,0x7F,0xFF,0x1FF,0x3FF,0x7FF,0xFFF,0x1FFF,0x3FFF,0x7FFF,0xFFFF,0x1FFFF,0x3FFFF,0x7FFFF,0xFFFFF,0x1FFFFF,0x3FFFFF,0x7FFFFF,0xFFFFFF,0x1FFFFFF,0x3FFFFFF,0x7FFFFFF,0xFFFFFFF,0x1FFFFFFF,0x3FFFFFFF,0x7FFFFFFF" bitfld.long 0x00 20.--22. " M ,BVR Meaning" "IVA match,Linked IVA match,Unlinked ID,Linked ID,IVA mismatch,Linked IVA mismatch,?..." bitfld.long 0x00 16.--19. " LBRP ,Linked BRP Number" "BRP,BRP1,BRP2,BRP3,BRP4,BRP5,BRP6,BRP7,BRP8,BRP9,BRP10,BRP11,BRP12,BRP13,BRP14,BRP15" bitfld.long 0x00 14.--15. " SWAC ,Secure World Access Control" "Both,Nonsecure,Secure,?..." textline " " bitfld.long 0x0 8. " BAS ,Byte 3 address select" "0,1" bitfld.long 0x0 7. ",Byte 2 address select" "0,1" bitfld.long 0x0 6. ",Byte 1 address select" "0,1" bitfld.long 0x0 5. ",Byte 0 address select" "0,1" bitfld.long 0x00 1.--2. " S ,Supervisor Access Control" "User/system/supervisor,Privileged,User,Any" bitfld.long 0x00 0. " B ,Breakpoint Enable" "Disabled,Enabled" tree.end tree "Watchpoint Control Registers" group.long c14:96.++0x0 line.long 0x00 "WVR0,Watchpoint Value 0 Register" hexmask.long 0x00 2.--31. 0x04 " WA0 ,Watchpoint Address 0" group.long c14:112.++0x0 line.long 0x00 "WCR0,Watchpoint Control 0 Register" bitfld.long 0x0 24.--28. " WAM ,Watchpoint address mask" "Not masked,Reserved,Reserved,0x7,0xF,0x1F,0x3F,0x7F,0xFF,0x1FF,0x3FF,0x7FF,0xFFF,0x1FFF,0x3FFF,0x7FFF,0xFFFF,0x1FFFF,0x3FFFF,0x7FFFF,0xFFFFF,0x1FFFFF,0x3FFFFF,0x7FFFFF,0xFFFFFF,0x1FFFFFF,0x3FFFFFF,0x7FFFFFF,0xFFFFFFF,0x1FFFFFFF,0x3FFFFFFF,0x7FFFFFFF" bitfld.long 0x0 20. " EL ,Enable Linking" "Disabled,Enabled" textline " " bitfld.long 0x0 16.--19. " LBN ,Linked BRP number" "BRP,BRP1,BRP2,BRP3,BRP4,BRP5,BRP6,BRP7,BRP8,BRP9,BRP10,BRP11,BRP12,BRP13,BRP14,BRP15" bitfld.long 0x0 14.--15. " SWAC ,Secure world access control" "Non-secure & Secure,Non-secure,Secure,?..." textline " " bitfld.long 0x0 12. " BAS ,Byte 7 address select" "0,1" bitfld.long 0x0 11. ",Byte 6 address select" "0,1" bitfld.long 0x0 10. ",Byte 5 address select" "0,1" bitfld.long 0x0 9. ",Byte 4 address select" "0,1" bitfld.long 0x0 8. ",Byte 3 address select" "0,1" bitfld.long 0x0 7. ",Byte 2 address select" "0,1" bitfld.long 0x0 6. ",Byte 1 address select" "0,1" bitfld.long 0x0 5. ",Byte 0 address select" "0,1" textline " " bitfld.long 0x0 3.--4. " RD/WR ,Load/Store access control" "Reserved,Load,Store,Any" bitfld.long 0x0 1.--2. " PAC ,Privileged access control" "Reserved,Privileged,USR,Any" textline " " bitfld.long 0x0 0. " WE ,Watchpoint enable" "Disabled,Enabled" group.long c14:97.++0x0 line.long 0x00 "WVR1,Watchpoint Value 1 Register" hexmask.long 0x00 2.--31. 0x04 " WA0 ,Watchpoint Address 0" group.long c14:113.++0x0 line.long 0x00 "WCR1,Watchpoint Control 1 Register" bitfld.long 0x0 24.--28. " WAM ,Watchpoint address mask" "Not masked,Reserved,Reserved,0x7,0xF,0x1F,0x3F,0x7F,0xFF,0x1FF,0x3FF,0x7FF,0xFFF,0x1FFF,0x3FFF,0x7FFF,0xFFFF,0x1FFFF,0x3FFFF,0x7FFFF,0xFFFFF,0x1FFFFF,0x3FFFFF,0x7FFFFF,0xFFFFFF,0x1FFFFFF,0x3FFFFFF,0x7FFFFFF,0xFFFFFFF,0x1FFFFFFF,0x3FFFFFFF,0x7FFFFFFF" bitfld.long 0x0 20. " EL ,Enable Linking" "Disabled,Enabled" textline " " bitfld.long 0x0 16.--19. " LBN ,Linked BRP number" "BRP,BRP1,BRP2,BRP3,BRP4,BRP5,BRP6,BRP7,BRP8,BRP9,BRP10,BRP11,BRP12,BRP13,BRP14,BRP15" bitfld.long 0x0 14.--15. " SWAC ,Secure world access control" "Non-secure & Secure,Non-secure,Secure,?..." textline " " bitfld.long 0x0 12. " BAS ,Byte 7 address select" "0,1" bitfld.long 0x0 11. ",Byte 6 address select" "0,1" bitfld.long 0x0 10. ",Byte 5 address select" "0,1" bitfld.long 0x0 9. ",Byte 4 address select" "0,1" bitfld.long 0x0 8. ",Byte 3 address select" "0,1" bitfld.long 0x0 7. ",Byte 2 address select" "0,1" bitfld.long 0x0 6. ",Byte 1 address select" "0,1" bitfld.long 0x0 5. ",Byte 0 address select" "0,1" textline " " bitfld.long 0x0 3.--4. " RD/WR ,Load/Store access control" "Reserved,Load,Store,Any" bitfld.long 0x0 1.--2. " PAC ,Privileged access control" "Reserved,Privileged,USR,Any" textline " " bitfld.long 0x0 0. " WE ,Watchpoint enable" "Disabled,Enabled" group.long c14:98.++0x0 line.long 0x00 "WVR2,Watchpoint Value 2 Register" hexmask.long 0x00 2.--31. 0x04 " WA0 ,Watchpoint Address 0" group.long c14:114.++0x0 line.long 0x00 "WCR2,Watchpoint Control 2 Register" bitfld.long 0x0 24.--28. " WAM ,Watchpoint address mask" "Not masked,Reserved,Reserved,0x7,0xF,0x1F,0x3F,0x7F,0xFF,0x1FF,0x3FF,0x7FF,0xFFF,0x1FFF,0x3FFF,0x7FFF,0xFFFF,0x1FFFF,0x3FFFF,0x7FFFF,0xFFFFF,0x1FFFFF,0x3FFFFF,0x7FFFFF,0xFFFFFF,0x1FFFFFF,0x3FFFFFF,0x7FFFFFF,0xFFFFFFF,0x1FFFFFFF,0x3FFFFFFF,0x7FFFFFFF" bitfld.long 0x0 20. " EL ,Enable Linking" "Disabled,Enabled" textline " " bitfld.long 0x0 16.--19. " LBN ,Linked BRP number" "BRP,BRP1,BRP2,BRP3,BRP4,BRP5,BRP6,BRP7,BRP8,BRP9,BRP10,BRP11,BRP12,BRP13,BRP14,BRP15" bitfld.long 0x0 14.--15. " SWAC ,Secure world access control" "Non-secure & Secure,Non-secure,Secure,?..." textline " " bitfld.long 0x0 12. " BAS ,Byte 7 address select" "0,1" bitfld.long 0x0 11. ",Byte 6 address select" "0,1" bitfld.long 0x0 10. ",Byte 5 address select" "0,1" bitfld.long 0x0 9. ",Byte 4 address select" "0,1" bitfld.long 0x0 8. ",Byte 3 address select" "0,1" bitfld.long 0x0 7. ",Byte 2 address select" "0,1" bitfld.long 0x0 6. ",Byte 1 address select" "0,1" bitfld.long 0x0 5. ",Byte 0 address select" "0,1" textline " " bitfld.long 0x0 3.--4. " RD/WR ,Load/Store access control" "Reserved,Load,Store,Any" bitfld.long 0x0 1.--2. " PAC ,Privileged access control" "Reserved,Privileged,USR,Any" textline " " bitfld.long 0x0 0. " WE ,Watchpoint enable" "Disabled,Enabled" group.long c14:99.++0x0 line.long 0x00 "WVR3,Watchpoint Value 3 Register" hexmask.long 0x00 2.--31. 0x04 " WA0 ,Watchpoint Address 0" group.long c14:115.++0x0 line.long 0x00 "WCR3,Watchpoint Control 3 Register" bitfld.long 0x0 24.--28. " WAM ,Watchpoint address mask" "Not masked,Reserved,Reserved,0x7,0xF,0x1F,0x3F,0x7F,0xFF,0x1FF,0x3FF,0x7FF,0xFFF,0x1FFF,0x3FFF,0x7FFF,0xFFFF,0x1FFFF,0x3FFFF,0x7FFFF,0xFFFFF,0x1FFFFF,0x3FFFFF,0x7FFFFF,0xFFFFFF,0x1FFFFFF,0x3FFFFFF,0x7FFFFFF,0xFFFFFFF,0x1FFFFFFF,0x3FFFFFFF,0x7FFFFFFF" bitfld.long 0x0 20. " EL ,Enable Linking" "Disabled,Enabled" textline " " bitfld.long 0x0 16.--19. " LBN ,Linked BRP number" "BRP,BRP1,BRP2,BRP3,BRP4,BRP5,BRP6,BRP7,BRP8,BRP9,BRP10,BRP11,BRP12,BRP13,BRP14,BRP15" bitfld.long 0x0 14.--15. " SWAC ,Secure world access control" "Non-secure & Secure,Non-secure,Secure,?..." textline " " bitfld.long 0x0 12. " BAS ,Byte 7 address select" "0,1" bitfld.long 0x0 11. ",Byte 6 address select" "0,1" bitfld.long 0x0 10. ",Byte 5 address select" "0,1" bitfld.long 0x0 9. ",Byte 4 address select" "0,1" bitfld.long 0x0 8. ",Byte 3 address select" "0,1" bitfld.long 0x0 7. ",Byte 2 address select" "0,1" bitfld.long 0x0 6. ",Byte 1 address select" "0,1" bitfld.long 0x0 5. ",Byte 0 address select" "0,1" textline " " bitfld.long 0x0 3.--4. " RD/WR ,Load/Store access control" "Reserved,Load,Store,Any" bitfld.long 0x0 1.--2. " PAC ,Privileged access control" "Reserved,Privileged,USR,Any" textline " " bitfld.long 0x0 0. " WE ,Watchpoint enable" "Disabled,Enabled" group.long c14:100.++0x0 line.long 0x00 "WVR4,Watchpoint Value 4 Register" hexmask.long 0x00 2.--31. 0x04 " WA0 ,Watchpoint Address 0" group.long c14:116.++0x0 line.long 0x00 "WCR4,Watchpoint Control 4 Register" bitfld.long 0x0 24.--28. " WAM ,Watchpoint address mask" "Not masked,Reserved,Reserved,0x7,0xF,0x1F,0x3F,0x7F,0xFF,0x1FF,0x3FF,0x7FF,0xFFF,0x1FFF,0x3FFF,0x7FFF,0xFFFF,0x1FFFF,0x3FFFF,0x7FFFF,0xFFFFF,0x1FFFFF,0x3FFFFF,0x7FFFFF,0xFFFFFF,0x1FFFFFF,0x3FFFFFF,0x7FFFFFF,0xFFFFFFF,0x1FFFFFFF,0x3FFFFFFF,0x7FFFFFFF" bitfld.long 0x0 20. " EL ,Enable Linking" "Disabled,Enabled" textline " " bitfld.long 0x0 16.--19. " LBN ,Linked BRP number" "BRP,BRP1,BRP2,BRP3,BRP4,BRP5,BRP6,BRP7,BRP8,BRP9,BRP10,BRP11,BRP12,BRP13,BRP14,BRP15" bitfld.long 0x0 14.--15. " SWAC ,Secure world access control" "Non-secure & Secure,Non-secure,Secure,?..." textline " " bitfld.long 0x0 12. " BAS ,Byte 7 address select" "0,1" bitfld.long 0x0 11. ",Byte 6 address select" "0,1" bitfld.long 0x0 10. ",Byte 5 address select" "0,1" bitfld.long 0x0 9. ",Byte 4 address select" "0,1" bitfld.long 0x0 8. ",Byte 3 address select" "0,1" bitfld.long 0x0 7. ",Byte 2 address select" "0,1" bitfld.long 0x0 6. ",Byte 1 address select" "0,1" bitfld.long 0x0 5. ",Byte 0 address select" "0,1" textline " " bitfld.long 0x0 3.--4. " RD/WR ,Load/Store access control" "Reserved,Load,Store,Any" bitfld.long 0x0 1.--2. " PAC ,Privileged access control" "Reserved,Privileged,USR,Any" textline " " bitfld.long 0x0 0. " WE ,Watchpoint enable" "Disabled,Enabled" group.long c14:101.++0x0 line.long 0x00 "WVR5,Watchpoint Value 5 Register" hexmask.long 0x00 2.--31. 0x04 " WA0 ,Watchpoint Address 0" group.long c14:117.++0x0 line.long 0x00 "WCR5,Watchpoint Control 5 Register" bitfld.long 0x0 24.--28. " WAM ,Watchpoint address mask" "Not masked,Reserved,Reserved,0x7,0xF,0x1F,0x3F,0x7F,0xFF,0x1FF,0x3FF,0x7FF,0xFFF,0x1FFF,0x3FFF,0x7FFF,0xFFFF,0x1FFFF,0x3FFFF,0x7FFFF,0xFFFFF,0x1FFFFF,0x3FFFFF,0x7FFFFF,0xFFFFFF,0x1FFFFFF,0x3FFFFFF,0x7FFFFFF,0xFFFFFFF,0x1FFFFFFF,0x3FFFFFFF,0x7FFFFFFF" bitfld.long 0x0 20. " EL ,Enable Linking" "Disabled,Enabled" textline " " bitfld.long 0x0 16.--19. " LBN ,Linked BRP number" "BRP,BRP1,BRP2,BRP3,BRP4,BRP5,BRP6,BRP7,BRP8,BRP9,BRP10,BRP11,BRP12,BRP13,BRP14,BRP15" bitfld.long 0x0 14.--15. " SWAC ,Secure world access control" "Non-secure & Secure,Non-secure,Secure,?..." textline " " bitfld.long 0x0 12. " BAS ,Byte 7 address select" "0,1" bitfld.long 0x0 11. ",Byte 6 address select" "0,1" bitfld.long 0x0 10. ",Byte 5 address select" "0,1" bitfld.long 0x0 9. ",Byte 4 address select" "0,1" bitfld.long 0x0 8. ",Byte 3 address select" "0,1" bitfld.long 0x0 7. ",Byte 2 address select" "0,1" bitfld.long 0x0 6. ",Byte 1 address select" "0,1" bitfld.long 0x0 5. ",Byte 0 address select" "0,1" textline " " bitfld.long 0x0 3.--4. " RD/WR ,Load/Store access control" "Reserved,Load,Store,Any" bitfld.long 0x0 1.--2. " PAC ,Privileged access control" "Reserved,Privileged,USR,Any" textline " " bitfld.long 0x0 0. " WE ,Watchpoint enable" "Disabled,Enabled" group.long c14:102.++0x0 line.long 0x00 "WVR6,Watchpoint Value 6 Register" hexmask.long 0x00 2.--31. 0x04 " WA0 ,Watchpoint Address 0" group.long c14:118.++0x0 line.long 0x00 "WCR6,Watchpoint Control 6 Register" bitfld.long 0x0 24.--28. " WAM ,Watchpoint address mask" "Not masked,Reserved,Reserved,0x7,0xF,0x1F,0x3F,0x7F,0xFF,0x1FF,0x3FF,0x7FF,0xFFF,0x1FFF,0x3FFF,0x7FFF,0xFFFF,0x1FFFF,0x3FFFF,0x7FFFF,0xFFFFF,0x1FFFFF,0x3FFFFF,0x7FFFFF,0xFFFFFF,0x1FFFFFF,0x3FFFFFF,0x7FFFFFF,0xFFFFFFF,0x1FFFFFFF,0x3FFFFFFF,0x7FFFFFFF" bitfld.long 0x0 20. " EL ,Enable Linking" "Disabled,Enabled" textline " " bitfld.long 0x0 16.--19. " LBN ,Linked BRP number" "BRP,BRP1,BRP2,BRP3,BRP4,BRP5,BRP6,BRP7,BRP8,BRP9,BRP10,BRP11,BRP12,BRP13,BRP14,BRP15" bitfld.long 0x0 14.--15. " SWAC ,Secure world access control" "Non-secure & Secure,Non-secure,Secure,?..." textline " " bitfld.long 0x0 12. " BAS ,Byte 7 address select" "0,1" bitfld.long 0x0 11. ",Byte 6 address select" "0,1" bitfld.long 0x0 10. ",Byte 5 address select" "0,1" bitfld.long 0x0 9. ",Byte 4 address select" "0,1" bitfld.long 0x0 8. ",Byte 3 address select" "0,1" bitfld.long 0x0 7. ",Byte 2 address select" "0,1" bitfld.long 0x0 6. ",Byte 1 address select" "0,1" bitfld.long 0x0 5. ",Byte 0 address select" "0,1" textline " " bitfld.long 0x0 3.--4. " RD/WR ,Load/Store access control" "Reserved,Load,Store,Any" bitfld.long 0x0 1.--2. " PAC ,Privileged access control" "Reserved,Privileged,USR,Any" textline " " bitfld.long 0x0 0. " WE ,Watchpoint enable" "Disabled,Enabled" group.long c14:103.++0x0 line.long 0x00 "WVR7,Watchpoint Value 7 Register" hexmask.long 0x00 2.--31. 0x04 " WA0 ,Watchpoint Address 0" group.long c14:119.++0x0 line.long 0x00 "WCR7,Watchpoint Control 7 Register" bitfld.long 0x0 24.--28. " WAM ,Watchpoint address mask" "Not masked,Reserved,Reserved,0x7,0xF,0x1F,0x3F,0x7F,0xFF,0x1FF,0x3FF,0x7FF,0xFFF,0x1FFF,0x3FFF,0x7FFF,0xFFFF,0x1FFFF,0x3FFFF,0x7FFFF,0xFFFFF,0x1FFFFF,0x3FFFFF,0x7FFFFF,0xFFFFFF,0x1FFFFFF,0x3FFFFFF,0x7FFFFFF,0xFFFFFFF,0x1FFFFFFF,0x3FFFFFFF,0x7FFFFFFF" bitfld.long 0x0 20. " EL ,Enable Linking" "Disabled,Enabled" textline " " bitfld.long 0x0 16.--19. " LBN ,Linked BRP number" "BRP,BRP1,BRP2,BRP3,BRP4,BRP5,BRP6,BRP7,BRP8,BRP9,BRP10,BRP11,BRP12,BRP13,BRP14,BRP15" bitfld.long 0x0 14.--15. " SWAC ,Secure world access control" "Non-secure & Secure,Non-secure,Secure,?..." textline " " bitfld.long 0x0 12. " BAS ,Byte 7 address select" "0,1" bitfld.long 0x0 11. ",Byte 6 address select" "0,1" bitfld.long 0x0 10. ",Byte 5 address select" "0,1" bitfld.long 0x0 9. ",Byte 4 address select" "0,1" bitfld.long 0x0 8. ",Byte 3 address select" "0,1" bitfld.long 0x0 7. ",Byte 2 address select" "0,1" bitfld.long 0x0 6. ",Byte 1 address select" "0,1" bitfld.long 0x0 5. ",Byte 0 address select" "0,1" textline " " bitfld.long 0x0 3.--4. " RD/WR ,Load/Store access control" "Reserved,Load,Store,Any" bitfld.long 0x0 1.--2. " PAC ,Privileged access control" "Reserved,Privileged,USR,Any" textline " " bitfld.long 0x0 0. " WE ,Watchpoint enable" "Disabled,Enabled" group.long c14:6.++0x0 line.long 0x00 "WFAR ,Watchpoint Fault Address Register" hexmask.long 0x00 1.--31. 0x2 " WFAR ,Address of the watchpointed instruction" tree.end width 11. AUTOINDENT.POP tree.end elif (CORENAME()=="CORTEXA55") tree "Core Registers (Cortex-A55)" AUTOINDENT.PUSH AUTOINDENT.ON center tree tree.open "AArch64" tree "ID Registers" rgroup.quad spr:0x30000++0x00 line.quad 0x00 "MIDR_EL1,Main ID Register" hexmask.quad.byte 0x0 24.--31. 1. "IMPL,Implementer code" bitfld.quad 0x00 20.--23. "VAR,Variant" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.quad 0x00 16.--19. "ARCH, Architecture" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,CPUID scheme" newline hexmask.quad.word 0x00 4.--15. 1. "PART,Primary Part Number" bitfld.quad 0x00 0.--3. "REV,Revision Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" if (CORENAME()=="CORTEXA75") rgroup.quad spr:0x30040++0x00 line.quad 0x00 "ID_AA64PFR0_EL1,Processor Feature Register 0" bitfld.quad 0x00 60.--63. "CSV3,Speculative use of faulting data" "Cannot be used,?..." bitfld.quad 0x00 56.--59. "CSV2,Speculative use of out of context branch targets" "Cannot effect,?..." newline bitfld.quad 0x00 28.--31. "RAS,RAS extension version" "Reserved,Version 1,?..." bitfld.quad 0x00 24.--27. "GIC,GIC CPU interface" "Disabled,Enabled,?..." newline bitfld.quad 0x00 20.--23. "ASIMD,Advanced SIMD" "Reserved,Implemented,?..." bitfld.quad 0x00 16.--19. "FP,Floating-point" "Reserved,Implemented,?..." newline bitfld.quad 0x00 12.--15. "EL3_ELH,EL3 exception level handling" "Reserved,Reserved,AArch64/AArch32,?..." bitfld.quad 0x00 8.--11. "EL2_ELH,EL2 exception level handling" "Reserved,Reserved,AArch64/AArch32,?..." newline bitfld.quad 0x00 4.--7. "EL1_ELH,EL1 exception level handling" "Reserved,Reserved,AArch64/AArch32,?..." bitfld.quad 0x00 0.--3. "EL0_ELH,EL0 exception level handling" "Reserved,Reserved,AArch64/AArch32,?..." elif (CORENAME()=="CORTEXA55") rgroup.quad spr:0x30040++0x00 line.quad 0x00 "ID_AA64PFR0_EL1,Processor Feature Register 0" bitfld.quad 0x00 60.--63. "CSV3,Speculative use of faulting data" "Reserved,Forbidden,?..." bitfld.quad 0x00 56.--59. "CSV2,Speculative use of faulting data" "Reserved,Forbidden,?..." newline bitfld.quad 0x00 28.--31. "RAS,RAS extension version" "Reserved,Version 1,?..." bitfld.quad 0x00 24.--27. "GIC,GIC CPU interface" "Disabled,Enabled,?..." newline bitfld.quad 0x00 20.--23. "ASIMD,Advanced SIMD" "Reserved,Implemented,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Not implemented" bitfld.quad 0x00 16.--19. "FP,Floating-point" "Reserved,Implemented,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Not implemented" newline bitfld.quad 0x00 12.--15. "EL3_ELH,EL3 exception level handling" "Reserved,Reserved,AArch64/AArch32,?..." bitfld.quad 0x00 8.--11. "EL2_ELH,EL2 exception level handling" "Reserved,Reserved,AArch64/AArch32,?..." newline bitfld.quad 0x00 4.--7. "EL1_ELH,EL1 exception level handling" "Reserved,Reserved,AArch64/AArch32,?..." bitfld.quad 0x00 0.--3. "EL0_ELH,EL0 exception level handling" "Reserved,Reserved,AArch64/AArch32,?..." rgroup.quad spr:0x30041++0x00 line.quad 0x00 "ID_AA64PFR1_EL1,Processor Feature Register 1" bitfld.quad 0x00 4.--7. "SSBS,Speculative store bypassing safe mechanism implemented" "Reserved,Implemented,?..." endif rgroup.quad spr:0x30050++0x00 line.quad 0x00 "ID_AA64DFR0_EL1,AArch64 Debug Feature Register" bitfld.quad 0x00 28.--31. "CTX_CMPS,Number of breakpoints that are context-aware" "Reserved,2,?..." bitfld.quad 0x00 20.--23. "WRPS,Number of watchpoints" "Reserved,Reserved,Reserved,4,?..." bitfld.quad 0x00 12.--15. "BRPS,Number of breakpoints" "Reserved,Reserved,Reserved,Reserved,Reserved,6,?..." newline bitfld.quad 0x00 8.--11. "PMEV,Performance monitor extension version" "Reserved,Reserved,Reserved,Reserved,Version 3/16 bit evtCount,?..." bitfld.quad 0x00 4.--7. "TEV,Trace extension version" "Not implemented,?..." bitfld.quad 0x00 0.--3. "DAV,Debug architecture version" "Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,v8-A,?..." rgroup.quad spr:0x30060++0x00 line.quad 0x00 "ID_AA64ISAR0_EL1,Instruction Set Attribute Register 0" bitfld.quad 0x00 44.--47. "DP,Implemented UDOT and SDOT instructions" "Reserved,Implemented,?..." newline bitfld.quad 0x00 28.--31. "RDM,Rounding Double Multiply Add/Subtract instructions Support" "Reserved,Implemented,?..." bitfld.quad 0x00 20.--23. "ATOMIC,Atomic instructions in AArch64" "Reserved,Reserved,Implemented,?..." bitfld.quad 0x00 16.--19. "CRC32,Indicates whether CRC32 instructions are implemented" "Reserved,Implemented,?..." newline bitfld.quad 0x00 12.--15. "SHA2,SHA2 instructions in AArch64" "Not implemented,Implemented,?..." bitfld.quad 0x00 8.--11. "SHA1,SHA1 instructions in AArch64" "Not implemented,Implemented,?..." bitfld.quad 0x00 4.--7. "AES,AES instruction in AArch64" "Not implemented,Reserved,AESE/AESD/AESMC/AESIMC/PMULL/PMULL2,?..." if (CORENAME()=="CORTEXA75") rgroup.quad spr:0x30070++0x00 line.quad 0x00 "ID_AA64MMFR0_EL1,Memory Model Feature Register 0" bitfld.quad 0x00 28.--31. "TGRAN4,4KB granule supported" "Supported,?..." bitfld.quad 0x00 24.--27. "TGRAN64,64KB granule supported" "Supported,?..." bitfld.quad 0x00 20.--23. "TGRAN16,16KB granule supported" "Reserved,Supported,?..." newline bitfld.quad 0x00 16.--19. "BIGENDEL0,Mixed-endian support at EL0" "Not supported,?..." bitfld.quad 0x00 12.--15. "SNSMEM,Secure versus Non-secure Memory distinction" "Reserved,Supported,?..." bitfld.quad 0x00 8.--11. "BIGEND,Mixed-endian configuration support" "Reserved,Supported,?..." newline bitfld.quad 0x00 4.--7. "ASIDBITS,Number of ASID bits" "Reserved,Reserved,16 bits,?..." bitfld.quad 0x00 0.--3. "PARANGE,Physical address range supported" "Reserved,Reserved,Reserved,Reserved,44 bits/16 TB,?..." elif (CORENAME()=="CORTEXA55") rgroup.quad spr:0x30070++0x00 line.quad 0x00 "ID_AA64MMFR0_EL1,Memory Model Feature Register 0" bitfld.quad 0x00 20.--23. "TGRAN16,16KB granule supported" "Reserved,Supported,?..." bitfld.quad 0x00 16.--19. "BIGENDEL0,Mixed-endian support at EL0" "Not supported,?..." bitfld.quad 0x00 12.--15. "SNSMEM,Secure versus Non-secure Memory distinction" "Reserved,Supported,?..." newline bitfld.quad 0x00 8.--11. "BIGEND,Mixed-endian configuration support" "Reserved,Supported,?..." bitfld.quad 0x00 4.--7. "ASIDBITS,Number of ASID bits" "Reserved,Reserved,16 bits,?..." bitfld.quad 0x00 0.--3. "PARANGE,Physical address range supported" "Reserved,Reserved,40 bits/1 TB,?..." endif rgroup.quad spr:0x30041++0x00 line.quad 0x00 "ID_AA64PFR1_EL1,Processor Feature Register 1" bitfld.quad 0x00 4.--7. "SSBS,Speculative Store Bypassing Safe (SSBS) mechanism support" "Reserved,Supported,?..." rgroup.quad spr:0x30051++0x00 line.quad 0x00 "ID_AA64DFR1_EL1,Debug Feature Register 1" rgroup.quad spr:0x30061++0x00 line.quad 0x00 "ID_AA64ISAR1_EL1,Instruction Set Attribute Register 1" bitfld.quad 0x00 20.--23. "LRCPC,Indicates whether load-acquire (LDA) instructions are implemented for an Release Consistent processor consistent RCPC model" "Reserved,Implemented,?..." bitfld.quad 0x00 0.--3. "DPB,DC CVAP support in AArch64" "Reserved,Implemented,?..." rgroup.quad spr:0x30071++0x00 line.quad 0x00 "ID_AA64MMFR1_EL1,Memory Model Feature Register 1" bitfld.quad 0x00 28.--31. "XNX,EL0/EL1 execute control distinction at stage2 bit support" "Reserved,Supported,?..." bitfld.quad 0x00 20.--23. "PAN,Privileged Access Never Support" "Reserved,Reserved,Extended,?..." bitfld.quad 0x00 16.--19. "LO,Limited Order Regions Support" "Reserved,Supported,?..." newline bitfld.quad 0x00 12.--15. "HD,Hierarchical Permission Disabled Support" "Reserved,Reserved,Extended,?..." bitfld.quad 0x00 8.--11. "VH,Virtualization Host Extensions Support" "Reserved,Supported,?..." bitfld.quad 0x00 4.--7. "VMID,Number of VMID bits" "Reserved,Reserved,16 bits,?..." newline bitfld.quad 0x00 0.--3. "HAFDBS,Hardware updates of the Access and Dirty" "Reserved,Reserved,Access/Dirty supported,?..." if (CORENAME()=="CORTEXA75") rgroup.quad spr:0x30072++0x00 line.quad 0x00 "ID_AA64MMFR2_EL1,Memory Model Feature Register 2" bitfld.quad 0x00 12.--15. "IESB, Indicates whether an implicit Error Synchronization Barrier has been inserted" "Reserved,Supported,?..." bitfld.quad 0x00 8.--11. "LSM,Indicates whether LDM and STM are supported" "Not supported,?..." bitfld.quad 0x00 4.--7. "UAO,User Access Override support" "Reserved,Supported,?..." newline bitfld.quad 0x00 0.--3. "CNP,Common not Private support" "Reserved,Supported,?..." elif (CORENAME()=="CORTEXA55") rgroup.quad spr:0x30072++0x00 line.quad 0x00 "ID_AA64MMFR2_EL1,Memory Model Feature Register 2" bitfld.quad 0x00 16.--19. "VARANGE,Indicates support for a larger virtual address" "Not supported,?..." bitfld.quad 0x00 12.--15. "IESB, Indicates whether an implicit Error Synchronization Barrier has been inserted" "Reserved,Supported,?..." bitfld.quad 0x00 8.--11. "LSM,Indicates whether LDM and STM are supported" "Not supported,?..." newline bitfld.quad 0x00 4.--7. "UAO,User Access Override support" "Reserved,Supported,?..." bitfld.quad 0x00 0.--3. "CNP,Common not Private support" "Reserved,Supported,?..." endif rgroup.quad spr:0x30054++0x00 line.quad 0x00 "ID_AA64AFR0_EL1,Auxiliary Feature Register 0" rgroup.quad spr:0x30055++0x00 line.quad 0x00 "ID_AA64AFR1_EL1,Auxiliary Feature Register 1" rgroup.quad spr:0x30010++0x00 line.quad 0x00 "ID_PFR0_EL1,AArch32 Processor Feature Register 0" bitfld.quad 0x00 28.--31. "RAS,RAS extension version" "Reserved,Version 1,?..." bitfld.quad 0x00 16.--19. "CSV2,Speculative use of faulting data" "Not disclosed,?..." newline bitfld.quad 0x00 12.--15. "STATE3,Thumb Execution Environment (Thumb-EE) Support" "Not supported,?..." bitfld.quad 0x00 8.--11. "STATE2,Support for Jazelle extension" "Reserved,Trivial,?..." bitfld.quad 0x00 4.--7. "STATE1,Thumb Encoding Supported by the Processor Type" "Reserved,Reserved,Reserved,After Thumb-2,?..." newline bitfld.quad 0x00 0.--3. "STATE0,ARM Instruction Set Support" "Reserved,Supported,?..." if (CORENAME()=="CORTEXA75") rgroup.quad spr:0x30011++0x00 line.quad 0x00 "ID_PFR1_EL1,AArch32 Processor Feature Register 1" bitfld.quad 0x00 28.--31. "GIC_CPU,GIC CPU Support" "Disabled,Enabled,?..." bitfld.quad 0x00 24.--27. "VF,Virtualization fractional Support - Supported features from the ARMv7 Virtualization Extensions" "Not supported,?..." bitfld.quad 0x00 20.--23. "SF,Security fractional Support - Supported features from the ARMv7 Security Extensions" "Not supported,?..." newline bitfld.quad 0x00 16.--19. "GT,Generic Timer Support" "Reserved,Supported,?..." bitfld.quad 0x00 12.--15. "VE,Virtualization Extensions Support" "Reserved,Supported,?..." bitfld.quad 0x00 8.--11. "MPM,Microcontroller Programmer's Model Support" "Not supported,?..." newline bitfld.quad 0x00 4.--7. "SE,Security Extensions Architecture v1 Support" "Reserved,Supported,?..." bitfld.quad 0x00 0.--3. "PM,Standard ARMv4 Programmer's Model Support" "Reserved,Supported,?..." elif (CORENAME()=="CORTEXA55") rgroup.quad spr:0x30011++0x00 line.quad 0x00 "ID_PFR1_EL1,AArch32 Processor Feature Register 1" bitfld.quad 0x00 28.--31. "GIC_CPU,GIC CPU Support" "Disabled,Enabled,?..." newline bitfld.quad 0x00 16.--19. "GT,Generic Timer Support" "Reserved,Supported,?..." bitfld.quad 0x00 12.--15. "VE,Virtualization Extensions Support" "Reserved,Supported,?..." bitfld.quad 0x00 8.--11. "MPM,Microcontroller Programmer's Model Support" "Not supported,?..." newline bitfld.quad 0x00 4.--7. "SE,Security Extensions Architecture v1 Support" "Reserved,Supported,?..." bitfld.quad 0x00 0.--3. "PM,Standard ARMv4 Programmer's Model Support" "Reserved,Supported,?..." endif if (CORENAME()=="CORTEXA75") rgroup.quad spr:0x30034++0x00 line.quad 0x00 "ID_PFR2_EL1,AArch32 Processor Feature Register 2" bitfld.quad 0x00 0.--3. "CSV3,Speculative use of faulting data" "Reserved,Forbidden,?..." elif (CORENAME()=="CORTEXA55") rgroup.quad spr:0x30034++0x00 line.quad 0x00 "ID_PFR2_EL1,AArch32 Processor Feature Register 2" bitfld.quad 0x00 4.--7. "SSBS,Speculative Store Bypassing Safe (SSBS) mechanism support" "Reserved,Supported,?..." bitfld.quad 0x00 0.--3. "CSV3,Speculative use of faulting data" "Reserved,Cannot be used,?..." endif rgroup.quad spr:0x30013++0x00 line.quad 0x00 "ID_AFR0_EL1,AArch32 Auxiliary Feature Register 0" rgroup.quad spr:0x30014++0x00 line.quad 0x00 "ID_MMFR0_EL1,Memory Model Feature Register 0" bitfld.quad 0x00 28.--31. "IS,Indicates innermost shareability domain implemented" "Reserved,HW coherency,?..." bitfld.quad 0x00 24.--27. "FCSE,Fast Context Switch Memory Mappings Support" "Not supported,?..." bitfld.quad 0x00 20.--23. "AR,Auxiliary Register Support" "Reserved,Reserved,Control/Fault Status,?..." newline bitfld.quad 0x00 16.--19. "TCM,TCM and Associated DMA Support" "Not supported,?..." bitfld.quad 0x00 12.--15. "SL,Shareability levels" "Reserved,Implemented 2 levels,?..." bitfld.quad 0x00 8.--11. "OSS,Outer Shareable Support" "Reserved,HW coherency,?..." newline bitfld.quad 0x00 4.--7. "PMSA,Physical Memory System Architecture (PMSA) Support" "Not supported,?..." bitfld.quad 0x00 0.--3. "VMSA,Virtual Memory System Architecture (VMSA) Support" "Reserved,Reserved,Reserved,Reserved,Reserved,VMSAv7/PXN/L-DESC,?..." rgroup.quad spr:0x30015++0x00 line.quad 0x00 "ID_MMFR1_EL1,Memory Model Feature Register 1" bitfld.quad 0x00 28.--31. "BTB,Branch Predictor" "Reserved,Reserved,Reserved,Reserved,No flushing,?..." bitfld.quad 0x00 24.--27. "L1TCO,Test and Clean Operations on Data Cache/Harvard/Unified Architecture Support" "Not supported,?..." bitfld.quad 0x00 20.--23. "L1UCMO,L1 Cache/All Maintenance Operations/Unified Architecture Support" "Not supported,?..." newline bitfld.quad 0x00 16.--19. "L1HCMO,L1 Cache/All Maintenance Operations/Harvard Architecture Support" "Not supported,?..." bitfld.quad 0x00 12.--15. "L1UCLMOSW,L1 Cache Line Maintenance Operations by Set and Way/Unified Architecture Support" "Not supported,?..." bitfld.quad 0x00 8.--11. "L1HCLMOSW,L1 Cache Line Maintenance Operations by Set and Way/Harvard Architecture Support" "Not supported,?..." newline bitfld.quad 0x00 4.--7. "L1UCLMOMVA,L1 Cache Line Maintenance Operations by VA/Unified Architecture Support" "Not supported,?..." bitfld.quad 0x00 0.--3. "L1HCLMOMVA,L1 Cache Line Maintenance Operations by VA/Harvard Architecture" "Not supported,?..." rgroup.quad spr:0x30016++0x00 line.quad 0x00 "ID_MMFR2_EL1,Memory Model Feature Register 2" bitfld.quad 0x00 28.--31. "HAF,Hardware Access Flag Support" "Not supported,?..." bitfld.quad 0x00 24.--27. "WFI,Wait for Interrupt Stalling Support" "Reserved,Supported,?..." bitfld.quad 0x00 20.--23. "MBF,Memory Barrier Operations Support" "Reserved,Reserved,DSB/ISB/DMB,?..." newline bitfld.quad 0x00 16.--19. "UTLBMO,TLB Maintenance Operations/Unified Architecture Support" "Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,S2 operations,?..." bitfld.quad 0x00 12.--15. "HTLBMO,TLB Maintenance Operations/Harvard Architecture Support" "Not supported,?..." bitfld.quad 0x00 8.--11. "HL1CMRO,Cache Maintenance Range Operations/Harvard Architecture Support" "Not supported,?..." newline bitfld.quad 0x00 4.--7. "HL1BPCRO,Background Prefetch Cache Range Operations/Harvard Architecture Support" "Not supported,?..." bitfld.quad 0x00 0.--3. "HL1FPCRO,Foreground Prefetch Cache Range Operations/Harvard Architecture Support" "Not supported,?..." rgroup.quad spr:0x30017++0x00 line.quad 0x00 "ID_MMFR3_EL1,AArch32 Memory Model Feature Register 3" bitfld.quad 0x00 28.--31. "SS,Supersection support" "Supported,?..." bitfld.quad 0x00 24.--27. "CMEMSZ,Cache memory size" "Reserved,Reserved,1TByte,?..." bitfld.quad 0x00 20.--23. "CW,Indicates whether translation table updates require a clean to the point of unification" "Reserved,Not required,?..." newline bitfld.quad 0x00 16.--19. "PAN,Privileged Access Never Support" "Reserved,Reserved,Extended,?..." bitfld.quad 0x00 12.--15. "MB,Maintenance broadcast Support" "Reserved,Reserved,Shareability/Defined behavior,?..." bitfld.quad 0x00 8.--11. "BPM,Invalidate Branch predictor Support" "Reserved,Reserved,Invalidate All/VA,?..." newline bitfld.quad 0x00 4.--7. "CMSW,Cache maintenance by set/way" "Reserved,Supported,?..." bitfld.quad 0x00 0.--3. "CMMVA,Cache maintenance by MVA" "Reserved,Supported,?..." rgroup.quad spr:0x30026++0x00 line.quad 0x00 "ID_MMFR4_EL1,AArch32 Memory Model Feature Register 4" bitfld.quad 0x00 20.--23. "LSM,LSMAOE and NTLSMD bits support" "Not supported,?..." bitfld.quad 0x00 16.--19. "HD,Hierarchical Permission Disabled Support" "Reserved,Reserved,Extended,?..." bitfld.quad 0x00 12.--15. "CNP,Common not Private support" "Reserved,Supported,?..." newline bitfld.quad 0x00 8.--11. "XNX,EL0/EL1 execute control distinction at stage2 bit support" "Not supported,Supported,?..." bitfld.quad 0x00 4.--7. "AC2,Indicates the extension of the HACTLR register using HACTLR2" "Reserved,Supported,?..." bitfld.quad 0x00 0.--3. "SPECSEI,Describes whether the PE can generate SError interrupt exceptions" "Not possible,?..." rgroup.quad spr:0x30020++0x00 line.quad 0x00 "ID_ISAR0_EL1,AArch32 Instruction Set Attribute Register 0" bitfld.quad 0x00 24.--27. "DIVI,Divide Instructions Support" "Reserved,Reserved,T32/A32,?..." bitfld.quad 0x00 20.--23. "DEBI,Debug Instructions Support" "Reserved,Supported,?..." bitfld.quad 0x00 16.--19. "CI,Coprocessor Instructions Support" "Not supported,?..." newline bitfld.quad 0x00 12.--15. "CBI,Combined Compare and Branch Instructions Support" "Reserved,Supported,?..." bitfld.quad 0x00 8.--11. "BI,Bitfield Instructions Support" "Reserved,Supported,?..." bitfld.quad 0x00 4.--7. "BCI,Bit Counting Instructions Support" "Reserved,Supported,?..." newline bitfld.quad 0x00 0.--3. "SI,Swap Instructions Support" "Not supported,?..." rgroup.quad spr:0x30021++0x00 line.quad 0x00 "ID_ISAR1_EL1,AArch32 Instruction Set Attribute Register 1" bitfld.quad 0x00 28.--31. "JI,Jazelle Instructions Support" "Reserved,Supported,?..." bitfld.quad 0x00 24.--27. "INTI,Interwork Instructions Support" "Reserved,Reserved,Reserved,Supported,?..." bitfld.quad 0x00 20.--23. "IMMI,Immediate Instructions Support" "Reserved,Supported,?..." newline bitfld.quad 0x00 16.--19. "ITEI,If Then Instructions Support" "Reserved,Supported,?..." bitfld.quad 0x00 12.--15. "EXTI,Extend Instructions Support" "Reserved,Reserved,Full support,?..." bitfld.quad 0x00 8.--11. "EARI,Exception A and R Instructions Support" "Reserved,Supported,?..." newline bitfld.quad 0x00 4.--7. "EXIN,Exception in ARM Instructions Support" "Reserved,Supported,?..." bitfld.quad 0x00 0.--3. "ENDI,Endian Instructions Support" "Reserved,Supported,?..." rgroup.quad spr:0x30022++0x00 line.quad 0x00 "ID_ISAR2_EL1,AArch32 Instruction Set Attribute Register 2" bitfld.quad 0x00 28.--31. "RI,Reversal Instructions Support" "Reserved,Reserved,Supported,?..." bitfld.quad 0x00 24.--27. "PSRI,PSR Instructions Support" "Not supported,Supported,?..." bitfld.quad 0x00 20.--23. "UMI,Advanced Unsigned Multiply Instructions Support" "Reserved,Reserved,UMAAL,?..." newline bitfld.quad 0x00 16.--19. "SMI,Advanced Signed Multiply Instructions Support" "Reserved,Reserved,Reserved,Supported,?..." newline bitfld.quad 0x00 12.--15. "MI,Multiply Instructions Support" "Reserved,Reserved,Supported,?..." bitfld.quad 0x00 8.--11. "II,Multi-Access Interruptible Instructions Support" "Not supported,?..." newline bitfld.quad 0x00 4.--7. "MHI,Memory Hint Instructions Support" "Reserved,Reserved,Reserved,Reserved,PLD/PLI/PLDW,?..." newline bitfld.quad 0x00 0.--3. "LSI,Load and Store Instructions Support" "Reserved,Reserved,Supported,?..." rgroup.quad spr:0x30023++0x00 line.quad 0x00 "ID_ISAR3_EL1, AArch32 Instruction Set Attribute Register 3" bitfld.quad 0x00 28.--31. "TEEEI,Thumb-EE Extensions Support" "Not supported,?..." bitfld.quad 0x00 24.--27. "NOPI,True NOP Instructions Support" "Reserved,Supported,?..." bitfld.quad 0x00 20.--23. "TCI,Thumb Copy Instructions Support" "Reserved,Supported,?..." newline bitfld.quad 0x00 16.--19. "TBI,Table Branch Instructions Support" "Reserved,Supported,?..." newline bitfld.quad 0x00 12.--15. "SPI,Synchronization Primitive Instructions Support" "Reserved,Reserved,Supported,?..." newline bitfld.quad 0x00 8.--11. "SVCI,SVC Instructions Support" "Reserved,Supported,?..." bitfld.quad 0x00 4.--7. "SIMDI,Single Instruction Multiple Data (SIMD) Instructions Support" "Reserved,Reserved,Reserved,Supported,?..." bitfld.quad 0x00 0.--3. "SI,Saturate Instructions Support" "Reserved,Supported,?..." rgroup.quad spr:0x30024++0x00 line.quad 0x00 "ID_ISAR4_EL1, AArch32 Instruction Set Attribute Register 4" bitfld.quad 0x00 28.--31. "SWP_FRAC,Memory System Locking Support" "Not supported,?..." bitfld.quad 0x00 24.--27. "PSR_M_I,PSR_M Instructions Support" "Not supported,?..." bitfld.quad 0x00 20.--23. "SPRI,Synchronization Primitive instructions" "Supported,?..." newline bitfld.quad 0x00 16.--19. "BI,Barrier Instructions Support" "Reserved,Supported,?..." bitfld.quad 0x00 12.--15. "SMCI,SMC Instructions Support" "Reserved,Supported,?..." bitfld.quad 0x00 8.--11. "WBI,Write-Back Instructions Support" "Reserved,Supported,?..." newline bitfld.quad 0x00 4.--7. "WSI,With-Shift Instructions Support" "Reserved,Reserved,Reserved,Reserved,Supported,?..." bitfld.quad 0x00 0.--3. "UI,Unprivileged Instructions Support" "Reserved,Reserved,Supported,?..." rgroup.quad spr:0x30025++0x00 line.quad 0x00 "ID_ISAR5_EL1,AArch32 Instruction Set Attribute Register 5" bitfld.quad 0x00 24.--27. "RDM,Rounding Double Multiply Add/Subtract instructions Support" "Reserved,Supported,?..." bitfld.quad 0x00 16.--19. "CRC32,CRC32 Instructions Support" "Reserved,Supported,?..." bitfld.quad 0x00 12.--15. "SHA2,SHA2 Instructions Support" "Not supported,Supported,?..." newline bitfld.quad 0x00 8.--11. "SHA1,SHA1 Instructions Support" "Not supported,Supported,?..." bitfld.quad 0x00 4.--7. "AES,AES Instructions Support" "Not supported,Reserved,Supported,?..." bitfld.quad 0x00 0.--3. "SEVL, SEVL Instructions Support" "Reserved,Supported,?..." rgroup.quad spr:0x30027++0x00 line.quad 0x00 "ID_ISAR6_EL1,AArch32 Instruction Set Attribute Register 6" bitfld.quad 0x00 4.--7. "DP,UDOT and SDOT instructions support" "Reserved,Supported,?..." rgroup.quad spr:0x33001++0x00 line.quad 0x00 "CTR_EL0,Cache Type Register" bitfld.quad 0x0 24.--27. "CWG,Cache writeback granule size" "Reserved,Reserved,Reserved,Reserved,16 words,?..." bitfld.quad 0x0 20.--23. "ERG,Exclusives reservation granule size" "Reserved,Reserved,Reserved,Reserved,16 words,?..." newline bitfld.quad 0x0 16.--19. "DMINLINE,Smallest data cache line size" "Reserved,Reserved,Reserved,Reserved,16 words,?..." bitfld.quad 0x0 14.--15. "VIPT,L1 Instruction cache policy" "Reserved,Reserved,VIPT,?..." newline bitfld.quad 0x0 0.--3. "IMINLINE,I-Cache Minimum Line Size" "Reserved,Reserved,Reserved,Reserved,16 words,?..." rgroup.quad spr:0x30005++0x00 line.quad 0x00 "MPIDR_EL1,MPIDR_EL1" hexmask.quad.byte 0x00 32.--39. 1. "AFF3,Affinity level 3. Highest level affinity field" bitfld.quad 0x00 30. "U,Uniprocessor" "Multiprocessor,?..." bitfld.quad 0x00 24. "MT,Indicates whether the lowest level of affinity consists of logical processors that are implemented using a multi-threading type approach" "Reserved,Very inter" newline hexmask.quad.byte 0x00 16.--23. 1. "AFF2,Affinity level 2. Second highest level affinity field" bitfld.quad 0x00 8.--10. "AFF1,Third highest level affinity field/Identification number for each CPU in cluster" "CPUID0,CPUID1,CPUID2,CPUID3,CPUID4,CPUID5,CPUID6,CPUID7" hexmask.quad.byte 0x00 0.--7. 1. "AFF0,Affinity level 0. The level identifies individual threads within a multi-threaded core" rgroup.quad spr:0x30006++0x00 line.quad 0x00 "REVIDR_EL1,Revision ID register" rgroup.quad spr:0x33007++0x00 line.quad 0x00 "DCZID_EL0,DCZID_EL0" bitfld.quad 0x00 4. "DZP,Data Zero prohibited" "Permitted,Prohibited" bitfld.quad 0x00 0.--3. "BLOCK,Log2 of the block size in words" "Reserved,Reserved,Reserved,Reserved,16 words,?..." rgroup.quad spr:0x31007++0x00 line.quad 0x00 "AIDR_EL1,Auxiliary ID Register EL1" group.quad spr:0x34000++0x00 line.quad 0x00 "VPIDR_EL2,Virtualization Processor ID register" hexmask.quad.byte 0x0 24.--31. 1. "IMPL,Implementer code" bitfld.quad 0x00 20.--23. "VAR,Variant" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.quad 0x00 16.--19. "ARCH, Architecture" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,CPUID scheme" newline hexmask.quad.word 0x00 4.--15. 1. "PART,Primary Part Number" bitfld.quad 0x00 0.--3. "REV,Revision Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.quad spr:0x34005++0x00 line.quad 0x00 "VMPIDR_EL2,Virtualization Multiprocessor ID registers" hexmask.quad.byte 0x00 32.--39. 1. "AFF3,Affinity level 3. Highest level affinity field" bitfld.quad 0x00 30. "U,Uniprocessor" "Multiprocessor,?..." bitfld.quad 0x00 24. "MT,Indicates whether the lowest level of affinity consists of logical processors that are implemented using a multi-threading type approach" "Reserved,Very interdependent" newline hexmask.quad.byte 0x00 16.--23. 1. "AFF2,Affinity level 2. Second highest level affinity field" bitfld.quad 0x00 8.--11. "AFF1,Third highest level affinity field/Identification number for each CPU in cluster" "CPUID0,CPUID1,CPUID2,CPUID3,CPUID4,CPUID5,CPUID6,CPUID7,?..." hexmask.quad.byte 0x00 0.--7. 1. "AFF0,Affinity level 0. The level identifies individual threads within a multi-threaded core" tree.end tree "System Control and Configuration" group.quad spr:0x36111++0x00 line.quad 0x00 "SDER32_EL3,Secure Debug Enable Register" bitfld.quad 0x00 1. "SUNIDEN,Enable non-invasive debug features in Secure User mode" "Disabled,Enabled" bitfld.quad 0x00 0. "SUIDEN,Enable debug exceptions in Secure User mode" "Disabled,Enabled" if (CORENAME()=="CORTEXA75") group.quad spr:0x30100++0x00 line.quad 0x00 "SCTLR_EL1,System Control Register EL1" bitfld.quad 0x00 26. "UCI,EL0 access in AArch64 for DC CVAU/ DC CIVAC/ DC CVAC and IC IVAU instructions enable" "Disabled,Enabled" bitfld.quad 0x00 25. "EE,Exception endianness" "Little,Big" newline bitfld.quad 0x00 24. "E0E,Endianness of explicit data accesses at EL0" "Little,Big" bitfld.quad 0x00 23. "SPAN,Set PSTATE.PAN bit on taking an exception to the EL1 exception level" "Reserved,Unchanged" newline bitfld.quad 0x00 21. "IESB,Implicit Error Synchronization Barrier enable" "Disabled,Enabled" bitfld.quad 0x00 19. "WXN,Write permission implies XN (Execute Never)" "Not forced,Forced" newline bitfld.quad 0x00 18. "NTWE,WFE instruction executed at EL0" "Executed,Not executed" bitfld.quad 0x00 16. "NTWI,WFI instruction executed at EL0" "Executed,Not executed" newline bitfld.quad 0x00 15. "UCT,EL0 access in AArch64 to the CTR_EL0 enable" "Disabled,Enabled" bitfld.quad 0x00 14. "DZE,Access to DC ZVA instruction at EL0" "Prohibited,Allowed" newline bitfld.quad 0x00 12. "I,Instruction Cache enable" "Disabled,Enabled" bitfld.quad 0x00 9. "UMA,User Mask Access. Controls access to interrupt masks from EL0, when EL0 is using AArch64" "Disabled,Enabled" newline bitfld.quad 0x00 8. "SED,SETEND instruction disable" "No,Yes" bitfld.quad 0x00 7. "ITD,IT Disable" "No," newline bitfld.quad 0x00 5. "CP15BEN,CP15 Barrier Enable" "Disabled,Enabled" bitfld.quad 0x00 4. "SA0,Stack Alignment Check Enable for EL0" "Disabled,Enabled" newline bitfld.quad 0x00 3. "SA,Stack Alignment Check Enable" "Disabled,Enabled" bitfld.quad 0x00 2. "C,Data/Unified Cache enable" "Disabled,Enabled" newline bitfld.quad 0x00 1. "A,Alignment Check" "Low,High" bitfld.quad 0x00 0. "M,MMU Enable" "Disabled,Enabled" elif (CORENAME()=="CORTEXA55") group.quad spr:0x30100++0x00 line.quad 0x00 "SCTLR_EL1,System Control Register EL1" bitfld.quad 0x00 26. "UCI,EL0 access in AArch64 for DC CVAU/ DC CIVAC/ DC CVAC and IC IVAU instructions enable" "Disabled,Enabled" bitfld.quad 0x00 25. "EE,Exception endianness" "Little,Big" newline bitfld.quad 0x00 24. "E0E,Endianness of explicit data accesses at EL0" "Little,Big" bitfld.quad 0x00 23. "SPAN,Set PSTATE.PAN bit on taking an exception to the EL1 exception level" "Reserved,Unchanged" newline bitfld.quad 0x00 19. "WXN,Write permission implies XN (Execute Never)" "Not forced,Forced" bitfld.quad 0x00 18. "NTWE,WFE instruction executed at EL0" "Executed,Not executed" newline bitfld.quad 0x00 16. "NTWI,WFI instruction executed at EL0" "Executed,Not executed" bitfld.quad 0x00 15. "UCT,EL0 access in AArch64 to the CTR_EL0 enable" "Disabled,Enabled" newline bitfld.quad 0x00 14. "DZE,Access to DC ZVA instruction at EL0" "Prohibited,Allowed" bitfld.quad 0x00 12. "I,Instruction Cache enable" "Disabled,Enabled" newline bitfld.quad 0x00 9. "UMA,User Mask Access. Controls access to interrupt masks from EL0, when EL0 is using AArch64" "Disabled,Enabled" bitfld.quad 0x00 8. "SED,SETEND instruction disable" "No,Yes" newline bitfld.quad 0x00 5. "CP15BEN,CP15 Barrier Enable" "Disabled,Enabled" bitfld.quad 0x00 4. "SA0,Stack Alignment Check Enable for EL0" "Disabled,Enabled" newline bitfld.quad 0x00 3. "SA,Stack Alignment Check Enable" "Disabled,Enabled" bitfld.quad 0x00 2. "C,Data/Unified Cache enable" "Disabled,Enabled" newline bitfld.quad 0x00 1. "A,Alignment Check" "Low,High" bitfld.quad 0x00 0. "M,MMU Enable" "Disabled,Enabled" endif group.quad spr:0x35100++0x00 line.quad 0x00 "SCTLR_EL12,System Control Register EL12" bitfld.quad 0x00 26. "UCI,EL0 access in AArch64 for DC CVAU/ DC CIVAC/ DC CVAC and IC IVAU instructions enable" "Disabled,Enabled" bitfld.quad 0x00 25. "EE,Exception endianness" "Little,Big" newline bitfld.quad 0x00 24. "E0E,Endianness of explicit data accesses at EL0" "Little,Big" bitfld.quad 0x00 23. "SPAN,Set PSTATE.PAN bit on taking an exception to the EL1 exception level" "Reserved,Unchanged" newline bitfld.quad 0x00 21. "IESB,Implicit Error Synchronization Barrier enable" "Disabled,Enabled" bitfld.quad 0x00 19. "WXN,Write permission implies XN (Execute Never)" "Not forced,Forced" newline bitfld.quad 0x00 18. "NTWE,WFE instruction executed at EL0" "Executed,Not executed" bitfld.quad 0x00 16. "NTWI,WFI instruction executed at EL0" "Executed,Not executed" newline bitfld.quad 0x00 15. "UCT,EL0 access in AArch64 to the CTR_EL0 enable" "Disabled,Enabled" bitfld.quad 0x00 14. "DZE,Access to DC ZVA instruction at EL0" "Prohibited,Allowed" newline bitfld.quad 0x00 12. "I,Instruction Cache enable" "Disabled,Enabled" bitfld.quad 0x00 9. "UMA,User Mask Access. Controls access to interrupt masks from EL0, when EL0 is using AArch64" "Disabled,Enabled" newline bitfld.quad 0x00 8. "SED,SETEND instruction disable" "No,Yes" bitfld.quad 0x00 7. "ITD,IT Disable" "No," newline bitfld.quad 0x00 5. "CP15BEN,CP15 Barrier Enable" "Disabled,Enabled" bitfld.quad 0x00 4. "SA0,Stack Alignment Check Enable for EL0" "Disabled,Enabled" newline bitfld.quad 0x00 3. "SA,Stack Alignment Check Enable" "Disabled,Enabled" bitfld.quad 0x00 2. "C,Data/Unified Cache enable" "Disabled,Enabled" newline bitfld.quad 0x00 1. "A,Alignment Check" "Low,High" bitfld.quad 0x00 0. "M,MMU Enable" "Disabled,Enabled" group.quad spr:0x34100++0x00 line.quad 0x00 "SCTLR_EL2,System Control Register EL2" bitfld.quad 0x00 25. "EE,Exception endianness" "Little,Big" bitfld.quad 0x00 19. "WXN,Write permission implies XN (Execute Never)" "Not forced,Forced" newline bitfld.quad 0x00 12. "I,Instruction Cache enable" "Disabled,Enabled" bitfld.quad 0x00 3. "SA,Stack Alignment Check Enable" "Disabled,Enabled" newline bitfld.quad 0x00 2. "C,Data/Unified Cache enable" "Disabled,Enabled" bitfld.quad 0x00 1. "A,Alignment Check" "Low,High" newline bitfld.quad 0x00 0. "M,MMU Enable" "Disabled,Enabled" group.quad spr:0x36100++0x00 line.quad 0x00 "SCTLR_EL3,System Control Register EL3" bitfld.quad 0x00 25. "EE,Exception endianness" "Little,Big" bitfld.quad 0x00 21. "IESB,Implicit Error Synchronization Barrier enable" "Disabled,Enabled" newline bitfld.quad 0x00 19. "WXN,Write permission implies XN (Execute Never)" "Not forced,Forced" bitfld.quad 0x00 12. "I,Instruction Cache enable" "Disabled,Enabled" newline bitfld.quad 0x00 3. "SA,Stack Alignment Check Enable" "Disabled,Enabled" bitfld.quad 0x00 2. "C,Data/Unified Cache enable" "Disabled,Enabled" newline bitfld.quad 0x00 1. "A,Alignment Check" "Low,High" bitfld.quad 0x00 0. "M,MMU Enable" "Disabled,Enabled" if (CORENAME()=="CORTEXA55") group.quad spr:0x30F70++0x00 line.quad 0x00 "ATCR_EL1,CPU Auxiliary Control Register" bitfld.quad 0x00 13. "HWVAL160,Indicates the value of PBHA[1] on page table walks memory access targeting the base address defined by TTB1 if HWEN160 is set" "0,1" bitfld.quad 0x00 12. "HWVAL159,Indicates the value of PBHA[0] on page table walks memory access targeting the base address defined by TTB1 if HWEN159 is set" "0,1" newline bitfld.quad 0x00 9. "HWVAL060,Indicates the value of PBHA[1] on page table walks memory access targeting the base address defined by TTB0 if HWEN060 is set" "0,1" bitfld.quad 0x00 8. "HWVAL059,Indicates the value of PBHA[1] on page table walks memory access targeting the base address defined by TTB0 if HWEN059 is set" "0,1" newline bitfld.quad 0x00 5. "HWEN160,Enables PBHA[1] page table walks memory access targeting the base address defined by TTB1" "Disabled,Enabled" bitfld.quad 0x00 4. "HWEN159,Enables PBHA[0] page table walks memory access targeting the base address defined by TTB1" "Disabled,Enabled" newline bitfld.quad 0x00 1. "HWEN060,Enables PBHA[1] page table walks memory access targeting the base address defined by TTB0" "Disabled,Enabled" bitfld.quad 0x00 0. "HWEN059,Enables PBHA[0] page table walks memory access targeting the base address defined by TTB0" "Disabled,Enabled" group.quad spr:0x35F70++0x00 line.quad 0x00 "ATCR_EL12,CPU Auxiliary Control Register" bitfld.quad 0x00 13. "HWVAL160,Indicates the value of PBHA[1] on page table walks memory access targeting the base address defined by TTB1 if HWEN160 is set" "0,1" bitfld.quad 0x00 12. "HWVAL159,Indicates the value of PBHA[0] on page table walks memory access targeting the base address defined by TTB1 if HWEN159 is set" "0,1" newline bitfld.quad 0x00 9. "HWVAL060,Indicates the value of PBHA[1] on page table walks memory access targeting the base address defined by TTB0 if HWEN060 is set" "0,1" bitfld.quad 0x00 8. "HWVAL059,Indicates the value of PBHA[1] on page table walks memory access targeting the base address defined by TTB0 if HWEN059 is set" "0,1" newline bitfld.quad 0x00 5. "HWEN160,Enables PBHA[1] page table walks memory access targeting the base address defined by TTB1" "Disabled,Enabled" bitfld.quad 0x00 4. "HWEN159,Enables PBHA[0] page table walks memory access targeting the base address defined by TTB1" "Disabled,Enabled" newline bitfld.quad 0x00 1. "HWEN060,Enables PBHA[1] page table walks memory access targeting the base address defined by TTB0" "Disabled,Enabled" bitfld.quad 0x00 0. "HWEN059,Enables PBHA[0] page table walks memory access targeting the base address defined by TTB0" "Disabled,Enabled" group.quad spr:0x34F70++0x00 line.quad 0x00 "ATCR_EL2,CPU Auxiliary Control Register" bitfld.quad 0x00 13. "HWVAL160,Indicates the value of PBHA[1] on page table walks memory access targeting the base address defined by TTB1 if HWEN160 is set" "0,1" bitfld.quad 0x00 12. "HWVAL159,Indicates the value of PBHA[0] on page table walks memory access targeting the base address defined by TTB1 if HWEN159 is set" "0,1" newline bitfld.quad 0x00 9. "HWVAL060,Indicates the value of PBHA[1] on page table walks memory access targeting the base address defined by TTB0 if HWEN060 is set" "0,1" bitfld.quad 0x00 8. "HWVAL059,Indicates the value of PBHA[1] on page table walks memory access targeting the base address defined by TTB0 if HWEN059 is set" "0,1" newline bitfld.quad 0x00 5. "HWEN160,Enables PBHA[1] page table walks memory access targeting the base address defined by TTB1" "Disabled,Enabled" bitfld.quad 0x00 4. "HWEN159,Enables PBHA[0] page table walks memory access targeting the base address defined by TTB1" "Disabled,Enabled" newline bitfld.quad 0x00 1. "HWEN060,Enables PBHA[1] page table walks memory access targeting the base address defined by TTB0" "Disabled,Enabled" bitfld.quad 0x00 0. "HWEN059,Enables PBHA[0] page table walks memory access targeting the base address defined by TTB0" "Disabled,Enabled" group.quad spr:0x36F70++0x00 line.quad 0x00 "ATCR_EL3,CPU Auxiliary Control Register" bitfld.quad 0x00 9. "HWVAL060,Indicates the value of PBHA[1] on page table walks memory access targeting the base address defined by TTB0 if HWEN060 is set" "0,1" bitfld.quad 0x00 8. "HWVAL059,Indicates the value of PBHA[1] on page table walks memory access targeting the base address defined by TTB0 if HWEN059 is set" "0,1" newline bitfld.quad 0x00 1. "HWEN060,Enables PBHA[1] page table walks memory access targeting the base address defined by TTB0" "Disabled,Enabled" bitfld.quad 0x00 0. "HWEN059,Enables PBHA[0] page table walks memory access targeting the base address defined by TTB0" "Disabled,Enabled" group.quad spr:0x34F71++0x00 line.quad 0x00 "AVTCR_EL2,CPU Auxiliary Control Register" bitfld.quad 0x00 9. "HWVAL060,Indicates the value of PBHA[1] on page table walks memory access targeting the base address defined by TTB0 if HWEN060 is set" "0,1" bitfld.quad 0x00 8. "HWVAL059,Indicates the value of PBHA[1] on page table walks memory access targeting the base address defined by TTB0 if HWEN059 is set" "0,1" newline bitfld.quad 0x00 1. "HWEN060,Enables PBHA[1] page table walks memory access targeting the base address defined by TTB0" "Disabled,Enabled" bitfld.quad 0x00 0. "HWEN059,Enables PBHA[0] page table walks memory access targeting the base address defined by TTB0" "Disabled,Enabled" endif group.quad spr:0x30F10++0x00 line.quad 0x00 "CPUACTLR_EL1,CPU Auxiliary Control Register" if (CORENAME()=="CORTEXA75") group.quad spr:0x30F11++0x00 line.quad 0x00 "CPUACTLR2_EL1,CPU Auxiliary Control Register 2" group.quad spr:0x30F14++0x00 line.quad 0x00 "CPUECTLR_EL1,CPU Extended Control Register" bitfld.quad 0x00 63. "GBPP,Branch prediction structure invalidation" "0,1" bitfld.quad 0x00 22.--23. "L4_STREAM,Threshold for direct stream to L4 cache on store" "512KB,1024KB,2048KB,Disabled" newline bitfld.quad 0x00 20.--21. "L3_STREAM,Threshold for direct stream to L3 cache on store" "64KB,256KB,512KB,Disabled" bitfld.quad 0x00 18.--19. "L2_STREAM,Threshold for direct stream to L2 cache on store" "16KB,64KB,128KB,Disabled" newline bitfld.quad 0x00 10. "L3PF,Enable L3 prefetch requests sent by the stride prefetcher" "Disabled,Enabled" bitfld.quad 0x00 9. "L2PF,Enable L2 prefetch requests sent by the stride prefetcher" "Disabled,Enabled" newline bitfld.quad 0x00 8. "L1PF,Enable L1 prefetch requests sent by the stride prefetcher" "Disabled,Enabled" bitfld.quad 0x00 7. "RPF,Enable L2 region prefetch requests" "Disabled,Enabled" newline bitfld.quad 0x00 6. "MMUPF,Enable MMU prefetch requests" "Disabled,Enabled" bitfld.quad 0x00 5. "RPF_AGGRO,L2 region prefetcher aggressivity" "Less,More" newline bitfld.quad 0x00 1. "RNSD_EXCL,Enables signaling of cacheable Exclusive loads on the internal interface between the core and the DSU" "Disabled,Enabled" bitfld.quad 0x00 0. "EXTLLC,Type of last-level cache that is present in the system" "Internal,External" elif (CORENAME()=="CORTEXA55") group.quad spr:0x30F14++0x00 line.quad 0x00 "CPUECTLR_EL1,CPU Extended Control Register" bitfld.quad 0x00 38.--39. "ATOM,Force most cacheable atomic instructions to be executed far in the L3 cache or beyond and near in the L1 cache" "Near - hit/unique | Far - miss/shared,Near,Far,Near - load | Far - store" bitfld.quad 0x00 37. "L2FLUSH,L2 cache flush" "Enabled,Disabled" newline bitfld.quad 0x00 29.--30. "L3WSCTL,Write streaming no-L3-allocate threshold" "128th line,1024th line,4096th line,Disabled" bitfld.quad 0x00 27.--28. "L2WSCTL,Write streaming no-L2-allocate threshold" "16th line,128th line,512th line,Disabled" newline bitfld.quad 0x00 25.--26. "L1WSCTL,Write streaming no-L1-allocate threshold" "4th line,64th line,128th line,Disabled" bitfld.quad 0x00 13.--15. "L1PCTL,L1 Data prefetch control. Maximum number of outstanding data prefetches allowed in the L1 memory system" "Disabled,1,2,3,4,5,6,7" newline bitfld.quad 0x00 10.--12. "L3PCTL,L3 Data prefetch control. Maximum number of outstanding data prefetches allowed that can be sent to the L3 memory system" "16 lines,32 lines,Reserved,Reserved,Disabled,2 lines,4 lines,8 lines" bitfld.quad 0x00 0. "EXTLLC,Indicates that an external Last-level cache is present in the system" "L3 cache,Present" group.quad spr:0x36F81++0x00 line.quad 0x00 "CPUPCR_EL3,CPU Private Control Register" group.quad spr:0x36F83++0x00 line.quad 0x00 "CPUPMR_EL3,CPU Private Mask Register" group.quad spr:0x36F82++0x00 line.quad 0x00 "CPUPOR_EL3,CPU Private Operation Register" group.quad spr:0x36F80++0x00 line.quad 0x00 "CPUPSELR_EL3,CPU Private Selection Register" endif group.quad spr:0x30101++0x00 line.quad 0x00 "ACTLR_EL1,Auxiliary Control register 1" if (CORENAME()=="CORTEXA75") group.quad spr:0x34101++0x00 line.quad 0x00 "ACTLR_EL2,Auxiliary Control register 2" bitfld.quad 0x00 12. "CLUSTERPMUEN,Performance Management Registers write access control" "Not accessible,Accessible" bitfld.quad 0x00 11. "SMEN,Scheme Management Registers write access control" "Not accessible,Accessible" newline bitfld.quad 0x00 10. "TSIDEN,Thread Scheme ID Register enable" "Not accessible,Accessible" bitfld.quad 0x00 7. "PWREN,Power Control Registers access control" "Not accessible,Accessible" newline bitfld.quad 0x00 5. "ERXPFGEN,Error Record Registers write access control" "Not accessible,Accessible" bitfld.quad 0x00 4. "AMEN,Activity Monitor enable" "Trapped,Not trapped" newline bitfld.quad 0x00 1. "ECTLREN,Extended Control Registers write access control" "Not accessible,Accessible" bitfld.quad 0x00 0. "ACTLREN,Auxiliary Control Registers write access control" "Not accessible,Accessible" group.quad spr:0x36101++0x00 line.quad 0x00 "ACTLR_EL3,Auxiliary Control register 3" bitfld.quad 0x00 12. "CLUSTERPMUEN,Performance Management Registers write access control" "Not accessible,Accessible" bitfld.quad 0x00 11. "SMEN,Scheme Management Registers write access control" "Not accessible,Accessible" newline bitfld.quad 0x00 7. "PWREN,Power Control Registers access control" "Not accessible,Accessible" bitfld.quad 0x00 5. "ERXPFGEN,Error Record Registers write access control" "Not accessible,Accessible" newline bitfld.quad 0x00 4. "AMEN,Activity Monitor enable" "Trapped,Not trapped" bitfld.quad 0x00 1. "ECTLREN,Extended Control Registers write access control" "Not accessible,Accessible" newline bitfld.quad 0x00 0. "ACTLREN,Auxiliary Control Registers write access control" "Not accessible,Accessible" group.quad spr:0x30102++0x00 line.quad 0x00 "CPACR_EL1,Coprocessor Access Control Register 1" bitfld.quad 0x00 28. "TTA,Traps EL0 and EL1 System register accesses to all implemented trace registers to EL1" "No trap," bitfld.quad 0x00 20.--21. "FPEN,Floating Point and Advanced SIMD execution to trap to EL1 when executed from EL0 or EL1" "EL0/EL1,EL0,EL0/EL1,No trap" group.quad spr:0x35102++0x00 line.quad 0x00 "CPACR_EL12,Coprocessor Access Control Register 1" bitfld.quad 0x00 28. "TTA,Traps EL0 and EL1 System register accesses to all implemented trace registers to EL1" "No trap," bitfld.quad 0x00 20.--21. "FPEN,Floating Point and Advanced SIMD execution to trap to EL1 when executed from EL0 or EL1" "EL0/EL1,EL0,EL0/EL1,No trap" elif (CORENAME()=="CORTEXA55") group.quad spr:0x34101++0x00 line.quad 0x00 "ACTLR_EL2,Auxiliary Control register 2" bitfld.quad 0x00 12. "CLUSTERPMUEN,Performance Management Registers write access control" "Not accessible,Accessible" bitfld.quad 0x00 11. "SMEN,Scheme Management Registers write access control" "Not accessible,Accessible" newline bitfld.quad 0x00 10. "TSIDEN,Thread Scheme ID Register enable" "Not accessible,Accessible" bitfld.quad 0x00 7. "PWREN,Power Control Registers access control" "Not accessible,Accessible" newline bitfld.quad 0x00 5. "ERXPFGEN,Error Record Registers write access control" "Not accessible,Accessible" bitfld.quad 0x00 1. "ECTLREN,Extended Control Registers write access control" "Not accessible,Accessible" newline bitfld.quad 0x00 0. "ACTLREN,Auxiliary Control Registers write access control" "Not accessible,Accessible" group.quad spr:0x36101++0x00 line.quad 0x00 "ACTLR_EL3,Auxiliary Control register 3" bitfld.quad 0x00 12. "CLUSTERPMUEN,Performance Management Registers write access control" "Not accessible,Accessible" bitfld.quad 0x00 11. "SMEN,Scheme Management Registers write access control" "Not accessible,Accessible" newline bitfld.quad 0x00 10. "TSIDEN,Thread Scheme ID Register enable" "Not accessible,Accessible" bitfld.quad 0x00 7. "PWREN,Power Control Registers access control" "Not accessible,Accessible" newline bitfld.quad 0x00 5. "ERXPFGEN,Error Record Registers write access control" "Not accessible,Accessible" bitfld.quad 0x00 1. "ECTLREN,Extended Control Registers write access control" "Not accessible,Accessible" newline bitfld.quad 0x00 0. "ACTLREN,Auxiliary Control Registers write access control" "Not accessible,Accessible" group.quad spr:0x30102++0x00 line.quad 0x00 "CPACR_EL1,Coprocessor Access Control Register 1" bitfld.quad 0x00 20.--21. "FPEN,Floating Point and Advanced SIMD execution to trap to EL1 when executed from EL0 or EL1" "EL0/EL1,EL0,EL0/EL1,No trap" group.quad spr:0x35102++0x00 line.quad 0x00 "CPACR_EL12,Coprocessor Access Control Register 1" bitfld.quad 0x00 20.--21. "FPEN,Floating Point and Advanced SIMD execution to trap to EL1 when executed from EL0 or EL1" "EL0/EL1,EL0,EL0/EL1,No trap" endif group.quad spr:0x34112++0x00 line.quad 0x00 "CPTR_EL2,Coprocessor Access Control Register 2" bitfld.quad 0x00 31. "TCPAC,Trap Coprocessor Access Control" "No trap,Trap" bitfld.quad 0x00 10. "TFP,Trap Floating Point and Advanced SIMD execution" "No trap,Trap" group.quad spr:0x36112++0x00 line.quad 0x00 "CPTR_EL3,Coprocessor Access Control Register 3" bitfld.quad 0x00 31. "TCPAC,Trap Coprocessor Access Control" "No trap,Trap" bitfld.quad 0x00 10. "TFP,Trap Floating Point and Advanced SIMD execution" "No trap,Trap" group.quad spr:0x36110++0x00 line.quad 0x00 "SCR_EL3,Secure Configuration Register" bitfld.quad 0x00 15. "TERR,Trap Error record accesses" "No Trap,Trap" bitfld.quad 0x00 14. "TLOR,Trap access to the LOR Registers from Non-secure EL1 and EL2 to EL3" "No trap,Trap" newline bitfld.quad 0x00 13. "TWE,Trap WFE" "No trap,Trap" bitfld.quad 0x00 12. "TWI,Trap WFI" "No trap,Trap" newline bitfld.quad 0x00 11. "ST,Enables Secure EL1 access to the CNTPS_TVAL_EL1 CNTPS_CTL_EL1 CNTPS_CVAL_EL1[63:0] registers" "Disabled,Enabled" bitfld.quad 0x00 10. "RW,Register width control for lower exception levels" "AArch32,AArch64" newline bitfld.quad 0x00 9. "SIF,Secure Instruction Fetch" "Permitted,Not permitted" bitfld.quad 0x00 8. "HCE,Hypervisor Call enable" "Disabled,Enabled" newline bitfld.quad 0x00 7. "SMD,Secure Monitor Call disable at EL1, EL2, or EL3" "No,Yes" bitfld.quad 0x00 3. "EA,External Abort exceptions handled in Abort mode or Monitor mode" "Abort,Monitor" newline bitfld.quad 0x00 2. "FIQ,FIQ exceptions handled in Abort mode or Monitor mode" "FIQ,Monitor" bitfld.quad 0x00 1. "IRQ,IRQ exceptions handled in Abort mode or Monitor mode" "IRQ,Monitor" newline bitfld.quad 0x00 0. "NS,Secure mode " "Secure,Non-secure" group.quad spr:0x34110++0x00 line.quad 0x00 "HCR_EL2,Hypervisor Configuration Register" bitfld.quad 0x00 35. "TLOR,Trap access to the LOR Registers from Non-secure EL1 to EL2" "No trap,Trap" bitfld.quad 0x00 34. "E2H,EL2 Host" "Disabled,Enabled" newline bitfld.quad 0x00 33. "ID,Stage 2 Instruction cache disable" "No,Yes" bitfld.quad 0x00 32. "CD,Stage 2 Data cache disable" "No,Yes" newline bitfld.quad 0x00 31. "RW,Register width control for lower exception levels" "AArch32,EL1 is 64-bit" bitfld.quad 0x00 30. "TRVM,Trap Read of Virtual Memory controls" "No trap,Trap" newline bitfld.quad 0x00 28. "TDZ,Trap DC ZVA instruction" "No trap,Trap" bitfld.quad 0x00 27. "TGE,Trap General Exceptions has an enhanced role when EL2 is using AArch64" "No trap,Trap" newline bitfld.quad 0x00 26. "TVM,Trap Virtual Memory controls to EL2" "No trap,Trap" bitfld.quad 0x00 25. "TTLB,Trap TLB maintenance instructions to EL2" "No trap,Trap" newline bitfld.quad 0x00 24. "TPU,Trap Cache maintenance instructions to Point of Unification to EL2" "No trap,Trap" bitfld.quad 0x00 23. "TPC,Trap Data/Unified Cache maintenance instructions to Point of Coherency to EL2" "No trap,Trap" newline bitfld.quad 0x00 22. "TSW,Trap Data/Unified Cache maintenance instructions by Set/Way to EL2" "No trap,Trap" bitfld.quad 0x00 21. "TACR,Trap Auxiliary Control Register" "No trap,Trap" newline bitfld.quad 0x00 20. "TIDCP,Trap Implementation Dependent functionality" "No trap,Trap" bitfld.quad 0x00 19. "TSC,Trap SMC" "No trap,Trap" newline bitfld.quad 0x00 18. "TID3,Trap ID Group 3" "No trap,Trap" bitfld.quad 0x00 17. "TID2,Trap ID Group 2" "No trap,Trap" newline bitfld.quad 0x00 16. "TID1,Trap ID Group 1" "No trap,Trap" bitfld.quad 0x00 15. "TID0,Trap ID Group 0" "No trap,Trap" newline bitfld.quad 0x00 14. "TWE,Trap WFE" "No trap,Trap" bitfld.quad 0x00 13. "TWI,Trap WFI" "No trap,Trap" newline bitfld.quad 0x00 12. "DC,Default Cacheable" "Disabled,Enabled" bitfld.quad 0x00 10.--11. "BSU,Barrier Shareability upgrade. determines the minimum shareability domain that is applied to any barrier executed from EL1 or EL0" "No effect,Inner Shareable,Outer Shareable,Full System" newline bitfld.quad 0x00 9. "FB,Force broadcast" "Not forced,Forced" bitfld.quad 0x00 8. "VSE,Virtual System Error/Asynchronous Abort:" "Not pending,Pending" newline bitfld.quad 0x00 7. "VI,Virtual IRQ Interrupt" "Not pending,Pending" bitfld.quad 0x00 6. "VF,Virtual FIQ Interrupt" "Not pending,Pending" newline bitfld.quad 0x00 5. "AMO,Asynchronous abort and error interrupt routing" "Disabled,Enabled" bitfld.quad 0x00 4. "IMO,Physical IRQ Routing" "Disabled,Enabled" newline bitfld.quad 0x00 3. "FMO,Physical FIQ Routing" "Disabled,Enabled" bitfld.quad 0x00 2. "PTW,Protected Table Walk" "Disabled,Enabled" newline bitfld.quad 0x00 0. "VM,Second stage of Translation enable" "Disabled,Enabled" group.quad spr:0x30510++0x00 line.quad 0x00 "AFSR0_EL1,Auxiliary Fault Status Registers" group.quad spr:0x35510++0x00 line.quad 0x00 "AFSR0_EL12,Auxiliary Fault Status Registers" group.quad spr:0x30511++0x00 line.quad 0x00 "AFSR1_EL1,Auxiliary Fault Status Registers" group.quad spr:0x35511++0x00 line.quad 0x00 "AFSR1_EL12,Auxiliary Fault Status Registers" group.quad spr:0x34510++0x00 line.quad 0x00 "AFSR0_EL2,Auxiliary Fault Status Registers" group.quad spr:0x34511++0x00 line.quad 0x00 "AFSR1_EL2,Auxiliary Fault Status Registers" group.quad spr:0x36510++0x00 line.quad 0x00 "AFSR0_EL3,Auxiliary Fault Status Registers" group.quad spr:0x36511++0x00 line.quad 0x00 "AFSR1_EL3,Auxiliary Fault Status Registers" tree.open "Exception Syndrome Registers" if (((per.q(spr:0x30520))&0xFC000000)==(0x00000000||0x38000000||0x88000000||0x98000000)) group.quad spr:0x30520++0x00 line.quad 0x00 "ESR_EL1,Exception Syndrome Register (EL1)" bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" elif (((per.q(spr:0x30520))&0xFC000000)==0x04000000) if (((per.q(spr:0x30520))&0x1000000)==0x1000000) group.quad spr:0x30520++0x00 line.quad 0x00 "ESR_EL1,Exception Syndrome Register (EL1)" bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline bitfld.quad 0x00 24. "CV,Condition code valid" "Not valid,Valid" bitfld.quad 0x00 20.--23. "COND,Condition code for the trapped instruction" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111" newline bitfld.quad 0x00 0. "TI,Trapped instruction" "WFI,WFE" else group.quad spr:0x30520++0x00 line.quad 0x00 "ESR_EL1,Exception Syndrome Register (EL1)" bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline bitfld.quad 0x00 24. "CV,Condition code valid" "Not valid,Valid" newline bitfld.quad 0x00 0. "TI,Trapped instruction" "WFI,WFE" endif elif (((per.q(spr:0x30520))&0xFC000000)==(0x0C000000||0x14000000)) if (((per.q(spr:0x30520))&0x1000000)==0x1000000) group.quad spr:0x30520++0x00 line.quad 0x00 "ESR_EL1,Exception Syndrome Register (EL1)" bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline bitfld.quad 0x00 24. "CV,Condition code valid" "Not valid,Valid" bitfld.quad 0x00 20.--23. "COND,Condition code for the trapped instruction" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111" newline bitfld.quad 0x00 17.--19. "OPC2,Opc2 value from the issued instruction" "0,1,2,3,4,5,6,7" bitfld.quad 0x00 14.--16. "OPC1,Opc1 value from the issued instruction" "0,1,2,3,4,5,6,7" newline bitfld.quad 0x00 10.--13. "CRN,CRn value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.quad 0x00 5.--9. "RT,Rt value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.quad 0x00 1.--4. "CRM,CRm value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.quad 0x00 0. "DIRECTION,Direction of the trapped instruction" "Write,Read" else group.quad spr:0x30520++0x00 line.quad 0x00 "ESR_EL1,Exception Syndrome Register (EL1)" bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline bitfld.quad 0x00 24. "CV,Condition code valid" "Not valid,Valid" newline bitfld.quad 0x00 17.--19. "OPC2,Opc2 value from the issued instruction" "0,1,2,3,4,5,6,7" bitfld.quad 0x00 14.--16. "OPC1,Opc1 value from the issued instruction" "0,1,2,3,4,5,6,7" newline bitfld.quad 0x00 10.--13. "CRN,CRn value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.quad 0x00 5.--9. "RT,Rt value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.quad 0x00 1.--4. "CRM,CRm value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.quad 0x00 0. "DIRECTION,Direction of the trapped instruction" "Write,Read" endif elif (((per.q(spr:0x30520))&0xFC000000)==(0x10000000||0x30000000)) if (((per.q(spr:0x30520))&0x1000000)==0x1000000) group.quad spr:0x30520++0x00 line.quad 0x00 "ESR_EL1,Exception Syndrome Register (EL1)" bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline bitfld.quad 0x00 24. "CV,Condition code valid" "Not valid,Valid" bitfld.quad 0x00 20.--23. "COND,Condition code for the trapped instruction" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111" newline bitfld.quad 0x00 16.--19. "OPC1,Opc1 value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.quad 0x00 10.--14. "RT2,Rt2 value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.quad 0x00 5.--9. "RT,Rt value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.quad 0x00 1.--4. "CRM,CRm value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.quad 0x00 0. "DIRECTION,Direction of the trapped instruction" "Write,Read" else group.quad spr:0x30520++0x00 line.quad 0x00 "ESR_EL1,Exception Syndrome Register (EL1)" bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline bitfld.quad 0x00 24. "CV,Condition code valid" "Not valid,Valid" newline bitfld.quad 0x00 16.--19. "OPC1,Opc1 value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.quad 0x00 10.--14. "RT2,Rt2 value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.quad 0x00 5.--9. "RT,Rt value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.quad 0x00 1.--4. "CRM,CRm value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.quad 0x00 0. "DIRECTION,Direction of the trapped instruction" "Write,Read" endif elif (((per.q(spr:0x30520))&0xFC000000)==0x18000000) if (((per.q(spr:0x30520))&0x1000000)==0x1000000) group.quad spr:0x30520++0x00 line.quad 0x00 "ESR_EL1,Exception Syndrome Register (EL1)" bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline bitfld.quad 0x00 24. "CV,Condition code valid" "Not valid,Valid" bitfld.quad 0x00 20.--23. "COND,Condition code for the trapped instruction" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111" newline hexmask.quad.byte 0x00 12.--19. 1. "IMM8,The immediate value from the issued instruction" bitfld.quad 0x00 5.--9. "RN,Rn value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.quad 0x00 4. "OFFSET,Indicates whether the offset is added or subtracted" "Subtracted,Added" bitfld.quad 0x00 1.--3. "AM,Addressing mode" "Immediate unindexed,Immediate post-indexed,Immediate offset,Immediate pre-indexed,Literal unindexed,Reserved,Literal offset,Reserved" newline bitfld.quad 0x00 0. "DIRECTION,Direction of the trapped instruction" "Write,Read" else group.quad spr:0x30520++0x00 line.quad 0x00 "ESR_EL1,Exception Syndrome Register (EL1)" bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline bitfld.quad 0x00 24. "CV,Condition code valid" "Not valid,Valid" newline hexmask.quad.byte 0x00 12.--19. 1. "IMM8,The immediate value from the issued instruction" bitfld.quad 0x00 5.--9. "RN,Rn value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.quad 0x00 4. "OFFSET,Indicates whether the offset is added or subtracted" "Subtracted,Added" bitfld.quad 0x00 1.--3. "AM,Addressing mode" "Immediate unindexed,Immediate post-indexed,Immediate offset,Immediate pre-indexed,Literal unindexed,Reserved,Literal offset,Reserved" newline bitfld.quad 0x00 0. "DIRECTION,Direction of the trapped instruction" "Write,Read" endif elif (((per.q(spr:0x30520))&0xFC000000)==0x1C000000) if (((per.q(spr:0x30520))&0x1000000)==0x1000000) group.quad spr:0x30520++0x00 line.quad 0x00 "ESR_EL1,Exception Syndrome Register (EL1)" bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline bitfld.quad 0x00 24. "CV,Condition code valid" "Not valid,Valid" bitfld.quad 0x00 20.--23. "COND,Condition code for the trapped instruction" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111" else group.quad spr:0x30520++0x00 line.quad 0x00 "ESR_EL1,Exception Syndrome Register (EL1)" bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline bitfld.quad 0x00 24. "CV,Condition code valid" "Not valid,Valid" endif elif (((per.q(spr:0x30520))&0xFC000000)==(0x44000000||0x54000000)) group.quad spr:0x30520++0x00 line.quad 0x00 "ESR_EL1,Exception Syndrome Register (EL1)" bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline hexmask.quad.word 0x00 0.--15. 1. "IMM16,The value of the immediate field from the HVC or SVC instruction" elif (((per.q(spr:0x30520))&0xFC000000)==0x60000000) group.quad spr:0x30520++0x00 line.quad 0x00 "ESR_EL1,Exception Syndrome Register (EL1)" bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline bitfld.quad 0x00 20.--21. "OP0,Op0 value from the issued instruction" "0,1,2,3" bitfld.quad 0x00 17.--19. "OP2,Opc2 value from the issued instruction" "0,1,2,3,4,5,6,7" newline bitfld.quad 0x00 14.--16. "OP1,Opc1 value from the issued instruction" "0,1,2,3,4,5,6,7" bitfld.quad 0x00 10.--13. "CRN,CRn value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.quad 0x00 5.--9. "RT,Rt value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.quad 0x00 1.--4. "CRM,CRm value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.quad 0x00 0. "DIRECTION,Direction of the trapped instruction" "Write,Read" elif (((per.q(spr:0x30520))&0xFC000000)==(0x80000000||0x84000000)) if (((per.q(spr:0x30520))&0x3F)==(0x10)) group.quad spr:0x30520++0x00 line.quad 0x00 "ESR_EL1,Exception Syndrome Register (EL1)" bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline bitfld.quad 0x00 11.--12. "SET,Synchronous Error Type" "UER,UEO,UC,CE" newline bitfld.quad 0x00 10. "FNV,FAR not Valid" "No,Yes" bitfld.quad 0x00 9. "EA,External abort type" "Not external,External" newline bitfld.quad 0x00 7. "S1PTW,Fault on the stage 2 translation of an address accessed during a stage 1 translation table walk" "Not stage 2,Stage 2" bitfld.quad 0x00 0.--5. "IFSC,Instruction Fault Status Code" "Address size/L0/base register,Address size/L1,Address size/L2,Address size/L3,Translation/L0,Translation/L1,Translation/L2,Translation/L3,Reserved,Access flag/L1,Access flag/L2,Access flag/L3,Reserved,Permission/L1,Permission/L2,Permission/L3,Sync. external abort/not table walk,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Sync. parity/ECC/not table walk,Reserved,Reserved,Reserved,Sync. external abort/L0,Sync. external abort/L1,Sync. external abort/L2,Sync. external abort/L3,Sync. parity/ECC/L0,Sync. parity/ECC/L1,Sync. parity/ECC/L2,Sync. parity/ECC/L3,Alignment,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,TLB conflict,?..." else group.quad spr:0x30520++0x00 line.quad 0x00 "ESR_EL1,Exception Syndrome Register (EL1)" bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline newline bitfld.quad 0x00 9. "EA,External abort type" "Not external,External" newline bitfld.quad 0x00 7. "S1PTW,Fault on the stage 2 translation of an address accessed during a stage 1 translation table walk" "Not stage 2,Stage 2" bitfld.quad 0x00 0.--5. "IFSC,Instruction Fault Status Code" "Address size/L0/base register,Address size/L1,Address size/L2,Address size/L3,Translation/L0,Translation/L1,Translation/L2,Translation/L3,Reserved,Access flag/L1,Access flag/L2,Access flag/L3,Reserved,Permission/L1,Permission/L2,Permission/L3,Sync. external abort/not table walk,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Sync. parity/ECC/not table walk,Reserved,Reserved,Reserved,Sync. external abort/L0,Sync. external abort/L1,Sync. external abort/L2,Sync. external abort/L3,Sync. parity/ECC/L0,Sync. parity/ECC/L1,Sync. parity/ECC/L2,Sync. parity/ECC/L3,Alignment,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,TLB conflict,?..." endif elif (((per.q(spr:0x30520))&0xFD000000)==(0x91000000||0x95000000)) if (((per.q(spr:0x30520))&0x3F)==(0x10)) group.quad spr:0x30520++0x00 line.quad 0x00 "ESR_EL1,Exception Syndrome Register (EL1)" bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline bitfld.quad 0x00 24. "ISV,Instruction syndrome valid" "Not valid,Valid" bitfld.quad 0x00 22.--23. "SAS,Syndrome Access Size" "Byte,Halfword,Word,Doubleword" newline bitfld.quad 0x00 21. "SSE,Syndrome Sign Extend" "Not required,Required" bitfld.quad 0x00 16.--20. "SRT,Syndrome Register transfer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.quad 0x00 15. "SF,Width of the register accessed by the instruction is Sixty-Four" "32-bit,64-bit" bitfld.quad 0x00 14. "AR,Acquire/Release" "No,Yes" newline bitfld.quad 0x00 11.--12. "SET,Synchronous Error Type" "UER,UEO,UC,CE" newline bitfld.quad 0x00 10. "FNV,FAR not Valid" "No,Yes" bitfld.quad 0x00 9. "EA,External abort type" "Not external,External" newline bitfld.quad 0x00 8. "CM,Fault came from a Cache Maintenance Instruction other than DC ZVA" "No,Yes" bitfld.quad 0x00 7. "S1PTW,Fault on the stage 2 translation of an address accessed during a stage 1 translation table walk" "Not stage 2,Stage 2" newline bitfld.quad 0x00 6. "WNR,Write not Read" "Read,Write" bitfld.quad 0x00 0.--5. "DFSC,Data Fault Status Code" "Address size/L0/TTBR,Address size/L1,Address size/L2,Address size/L3,Translation/L0,Translation/L1,Translation/L2,Translation/L3,Reserved,Access flag/L1,Access flag/L2,Access flag/L3,Reserved,Permission/L1,Permission/L2,Permission/L3,Sync. external abort/not table walk,Reserved,Reserved,Reserved,Sync. external abort/L0,Sync. external abort/L1,Sync. external abort/L2,Sync. external abort/L3,Sync. parity/ECC/not table walk,Reserved,Reserved,Reserved,Sync. parity/ECC/L0,Sync. parity/ECC/L1,Sync. parity/ECC/L2,Sync. parity/ECC/L3,Reserved,Alignment,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,TLB conflict,Reserved,Reserved,Reserved,Lockdown,Unsupported Exclusive/Atomic access,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Section Domain,Page Domain,Reserved" else group.quad spr:0x30520++0x00 line.quad 0x00 "ESR_EL1,Exception Syndrome Register (EL1)" bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline bitfld.quad 0x00 24. "ISV,Instruction syndrome valid" "Not valid,Valid" bitfld.quad 0x00 22.--23. "SAS,Syndrome Access Size" "Byte,Halfword,Word,Doubleword" newline bitfld.quad 0x00 21. "SSE,Syndrome Sign Extend" "Not required,Required" bitfld.quad 0x00 16.--20. "SRT,Syndrome Register transfer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.quad 0x00 15. "SF,Width of the register accessed by the instruction is Sixty-Four" "32-bit,64-bit" bitfld.quad 0x00 14. "AR,Acquire/Release" "No,Yes" newline newline bitfld.quad 0x00 9. "EA,External abort type" "Not external,External" newline bitfld.quad 0x00 8. "CM,Fault came from a Cache Maintenance Instruction other than DC ZVA" "No,Yes" bitfld.quad 0x00 7. "S1PTW,Fault on the stage 2 translation of an address accessed during a stage 1 translation table walk" "Not stage 2,Stage 2" newline bitfld.quad 0x00 6. "WNR,Write not Read" "Read,Write" bitfld.quad 0x00 0.--5. "DFSC,Data Fault Status Code" "Address size/L0/TTBR,Address size/L1,Address size/L2,Address size/L3,Translation/L0,Translation/L1,Translation/L2,Translation/L3,Reserved,Access flag/L1,Access flag/L2,Access flag/L3,Reserved,Permission/L1,Permission/L2,Permission/L3,Sync. external abort/not table walk,Reserved,Reserved,Reserved,Sync. external abort/L0,Sync. external abort/L1,Sync. external abort/L2,Sync. external abort/L3,Sync. parity/ECC/not table walk,Reserved,Reserved,Reserved,Sync. parity/ECC/L0,Sync. parity/ECC/L1,Sync. parity/ECC/L2,Sync. parity/ECC/L3,Reserved,Alignment,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,TLB conflict,Reserved,Reserved,Reserved,Lockdown,Unsupported Exclusive/Atomic access,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Section Domain,Page Domain,Reserved" endif elif (((per.q(spr:0x30520))&0xFD000000)==(0x90000000||0x94000000)) if (((per.q(spr:0x30520))&0x3F)==(0x10)) group.quad spr:0x30520++0x00 line.quad 0x00 "ESR_EL1,Exception Syndrome Register (EL1)" bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline bitfld.quad 0x00 24. "ISV,Instruction syndrome valid" "Not valid,Valid" newline newline newline bitfld.quad 0x00 11.--12. "SET,Synchronous Error Type" "UER,UEO,UC,CE" newline bitfld.quad 0x00 10. "FNV,FAR not Valid" "No,Yes" bitfld.quad 0x00 9. "EA,External abort type" "Not external,External" newline bitfld.quad 0x00 8. "CM,Fault came from a Cache Maintenance Instruction other than DC ZVA" "No,Yes" bitfld.quad 0x00 7. "S1PTW,Fault on the stage 2 translation of an address accessed during a stage 1 translation table walk" "Not stage 2,Stage 2" newline bitfld.quad 0x00 6. "WNR,Write not Read" "Read,Write" bitfld.quad 0x00 0.--5. "DFSC,Data Fault Status Code" "Address size/L0/TTBR,Address size/L1,Address size/L2,Address size/L3,Translation/L0,Translation/L1,Translation/L2,Translation/L3,Reserved,Access flag/L1,Access flag/L2,Access flag/L3,Reserved,Permission/L1,Permission/L2,Permission/L3,Sync. external abort/not table walk,Reserved,Reserved,Reserved,Sync. external abort/L0,Sync. external abort/L1,Sync. external abort/L2,Sync. external abort/L3,Sync. parity/ECC/not table walk,Reserved,Reserved,Reserved,Sync. parity/ECC/L0,Sync. parity/ECC/L1,Sync. parity/ECC/L2,Sync. parity/ECC/L3,Reserved,Alignment,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,TLB conflict,Reserved,Reserved,Reserved,Lockdown,Unsupported Exclusive/Atomic access,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Section Domain,Page Domain,Reserved" else group.quad spr:0x30520++0x00 line.quad 0x00 "ESR_EL1,Exception Syndrome Register (EL1)" bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline bitfld.quad 0x00 24. "ISV,Instruction syndrome valid" "Not valid,Valid" newline newline newline newline bitfld.quad 0x00 9. "EA,External abort type" "Not external,External" newline bitfld.quad 0x00 8. "CM,Fault came from a Cache Maintenance Instruction other than DC ZVA" "No,Yes" bitfld.quad 0x00 7. "S1PTW,Fault on the stage 2 translation of an address accessed during a stage 1 translation table walk" "Not stage 2,Stage 2" newline bitfld.quad 0x00 6. "WNR,Write not Read" "Read,Write" bitfld.quad 0x00 0.--5. "DFSC,Data Fault Status Code" "Address size/L0/TTBR,Address size/L1,Address size/L2,Address size/L3,Translation/L0,Translation/L1,Translation/L2,Translation/L3,Reserved,Access flag/L1,Access flag/L2,Access flag/L3,Reserved,Permission/L1,Permission/L2,Permission/L3,Sync. external abort/not table walk,Reserved,Reserved,Reserved,Sync. external abort/L0,Sync. external abort/L1,Sync. external abort/L2,Sync. external abort/L3,Sync. parity/ECC/not table walk,Reserved,Reserved,Reserved,Sync. parity/ECC/L0,Sync. parity/ECC/L1,Sync. parity/ECC/L2,Sync. parity/ECC/L3,Reserved,Alignment,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,TLB conflict,Reserved,Reserved,Reserved,Lockdown,Unsupported Exclusive/Atomic access,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Section Domain,Page Domain,Reserved" endif elif (((per.q(spr:0x30520))&0xFC800000)==(0xA0800000||0xB0800000)) group.quad spr:0x30520++0x00 line.quad 0x00 "ESR_EL1,Exception Syndrome Register (EL1)" bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline bitfld.quad 0x00 23. "TFV,Trapped Fault Valid" "Not valid,Valid" bitfld.quad 0x00 8.--10. "VECITR,Number of the element that is being reported" "0,1,2,3,4,5,6,7" newline bitfld.quad 0x00 7. "IDF,Input Denormal floating-point exception trapped" "Not occurred,Occurred" bitfld.quad 0x00 4. "IXF,Inexact floating-point exception trapped" "Not occurred,Occurred" newline bitfld.quad 0x00 3. "UFF,Underflow floating-point exception trapped" "Not occurred,Occurred" bitfld.quad 0x00 2. "OFF,Overflow floating-point exception trapped" "Not occurred,Occurred" newline bitfld.quad 0x00 1. "DZF,Divide-by-zero floating-point exception trapped" "Not occurred,Occurred" bitfld.quad 0x00 0. "IOF,Invalid Operation floating-point exception trapped" "Not occurred,Occurred" elif (((per.q(spr:0x30520))&0xFC800000)==(0xA0000000||0xB0000000)) group.quad spr:0x30520++0x00 line.quad 0x00 "ESR_EL1,Exception Syndrome Register (EL1)" bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline bitfld.quad 0x00 23. "TFV,Trapped Fault Valid" "Not valid,Valid" bitfld.quad 0x00 8.--10. "VECITR,Number of the element that is being reported" "0,1,2,3,4,5,6,7" elif (((per.q(spr:0x30520))&0xFD000000)==0xBD000000) if (((per.q(spr:0x30520))&0x3F)==0x11) group.quad spr:0x30520++0x00 line.quad 0x00 "ESR_EL1,Exception Syndrome Register (EL1)" bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline bitfld.quad 0x00 24. "IDS,Implementation defined syndrome" "Not hold,Hold" bitfld.quad 0x00 13. "IESB,Implicit Error Synchronization Barrier" "Not synchronized,Synchronized" newline bitfld.quad 0x00 10.--12. "AET,Asynchronous Error Type" "UC,UEU,UEO,UER,CE,?..." bitfld.quad 0x00 9. "EA,External abort type" "No,Yes" newline bitfld.quad 0x00 0.--5. "DFSC,Data Fault Status Code" "Uncategorized,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Asynchronous,?..." else group.quad spr:0x30520++0x00 line.quad 0x00 "ESR_EL1,Exception Syndrome Register (EL1)" bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline bitfld.quad 0x00 24. "IDS,Implementation defined syndrome" "Not hold,Hold" bitfld.quad 0x00 9. "EA,External abort type" "No,Yes" newline bitfld.quad 0x00 0.--5. "DFSC,Data Fault Status Code" "Uncategorized,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Asynchronous,?..." endif elif (((per.q(spr:0x30520))&0xFD000000)==0xBC000000) group.quad spr:0x30520++0x00 line.quad 0x00 "ESR_EL1,Exception Syndrome Register (EL1)" bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline bitfld.quad 0x00 24. "IDS,Implementation defined syndrome" "Not hold,Hold" elif (((per.q(spr:0x30520))&0xFC000000)==(0xC0000000||0xC4000000)) group.quad spr:0x30520++0x00 line.quad 0x00 "ESR_EL1,Exception Syndrome Register (EL1)" bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline bitfld.quad 0x00 0.--5. "IFSC,Instruction Fault Status Code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,Debug exception,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" elif (((per.q(spr:0x30520))&0xFC000000)==(0xC8000000||0xCC000000)) group.quad spr:0x30520++0x00 line.quad 0x00 "ESR_EL1,Exception Syndrome Register (EL1)" bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline bitfld.quad 0x00 24. "ISV,EX bit valid" "Not valid,Valid" bitfld.quad 0x00 6. "EX,Exclusive operation" "No,Yes" newline bitfld.quad 0x00 0.--5. "IFSC,Instruction Fault Status Code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,Debug exception,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" elif (((per.q(spr:0x30520))&0xFC000000)==(0xD0000000||0xD4000000)) group.quad spr:0x30520++0x00 line.quad 0x00 "ESR_EL1,Exception Syndrome Register (EL1)" bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline bitfld.quad 0x00 8. "CM,Data came from a Cache Maintenance Instruction other than DC ZVA" "No,Yes" bitfld.quad 0x00 6. "WNR,Write not Read" "Read,Write" newline bitfld.quad 0x00 0.--5. "IFSC,Instruction Fault Status Code" "0,1,2,3,?..." elif (((per.q(spr:0x30520))&0xFC000000)==(0xE0000000||0xF0000000)) group.quad spr:0x30520++0x00 line.quad 0x00 "ESR_EL1,Exception Syndrome Register (EL1)" bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline hexmask.quad.word 0x00 0.--15. 1. "COMMENT,Set to the instruction comment field value" else group.quad spr:0x30520++0x00 line.quad 0x00 "ESR_EL1,Exception Syndrome Register (EL1)" bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" endif if (((per.q(spr:0x35520))&0xFC000000)==(0x00000000||0x38000000||0x88000000||0x98000000)) group.quad spr:0x35520++0x00 line.quad 0x00 "ESR_EL12,Exception Syndrome Register (EL1)" bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" elif (((per.q(spr:0x35520))&0xFC000000)==0x04000000) if (((per.q(spr:0x35520))&0x1000000)==0x1000000) group.quad spr:0x35520++0x00 line.quad 0x00 "ESR_EL12,Exception Syndrome Register (EL1)" bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline bitfld.quad 0x00 24. "CV,Condition code valid" "Not valid,Valid" bitfld.quad 0x00 20.--23. "COND,Condition code for the trapped instruction" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111" newline bitfld.quad 0x00 0. "TI,Trapped instruction" "WFI,WFE" else group.quad spr:0x35520++0x00 line.quad 0x00 "ESR_EL12,Exception Syndrome Register (EL1)" bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline bitfld.quad 0x00 24. "CV,Condition code valid" "Not valid,Valid" newline bitfld.quad 0x00 0. "TI,Trapped instruction" "WFI,WFE" endif elif (((per.q(spr:0x35520))&0xFC000000)==(0x0C000000||0x14000000)) if (((per.q(spr:0x35520))&0x1000000)==0x1000000) group.quad spr:0x35520++0x00 line.quad 0x00 "ESR_EL12,Exception Syndrome Register (EL1)" bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline bitfld.quad 0x00 24. "CV,Condition code valid" "Not valid,Valid" bitfld.quad 0x00 20.--23. "COND,Condition code for the trapped instruction" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111" newline bitfld.quad 0x00 17.--19. "OPC2,Opc2 value from the issued instruction" "0,1,2,3,4,5,6,7" bitfld.quad 0x00 14.--16. "OPC1,Opc1 value from the issued instruction" "0,1,2,3,4,5,6,7" newline bitfld.quad 0x00 10.--13. "CRN,CRn value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.quad 0x00 5.--9. "RT,Rt value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.quad 0x00 1.--4. "CRM,CRm value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.quad 0x00 0. "DIRECTION,Direction of the trapped instruction" "Write,Read" else group.quad spr:0x35520++0x00 line.quad 0x00 "ESR_EL12,Exception Syndrome Register (EL1)" bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline bitfld.quad 0x00 24. "CV,Condition code valid" "Not valid,Valid" newline bitfld.quad 0x00 17.--19. "OPC2,Opc2 value from the issued instruction" "0,1,2,3,4,5,6,7" bitfld.quad 0x00 14.--16. "OPC1,Opc1 value from the issued instruction" "0,1,2,3,4,5,6,7" newline bitfld.quad 0x00 10.--13. "CRN,CRn value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.quad 0x00 5.--9. "RT,Rt value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.quad 0x00 1.--4. "CRM,CRm value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.quad 0x00 0. "DIRECTION,Direction of the trapped instruction" "Write,Read" endif elif (((per.q(spr:0x35520))&0xFC000000)==(0x10000000||0x30000000)) if (((per.q(spr:0x35520))&0x1000000)==0x1000000) group.quad spr:0x35520++0x00 line.quad 0x00 "ESR_EL12,Exception Syndrome Register (EL1)" bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline bitfld.quad 0x00 24. "CV,Condition code valid" "Not valid,Valid" bitfld.quad 0x00 20.--23. "COND,Condition code for the trapped instruction" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111" newline bitfld.quad 0x00 16.--19. "OPC1,Opc1 value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.quad 0x00 10.--14. "RT2,Rt2 value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.quad 0x00 5.--9. "RT,Rt value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.quad 0x00 1.--4. "CRM,CRm value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.quad 0x00 0. "DIRECTION,Direction of the trapped instruction" "Write,Read" else group.quad spr:0x35520++0x00 line.quad 0x00 "ESR_EL12,Exception Syndrome Register (EL1)" bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline bitfld.quad 0x00 24. "CV,Condition code valid" "Not valid,Valid" newline bitfld.quad 0x00 16.--19. "OPC1,Opc1 value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.quad 0x00 10.--14. "RT2,Rt2 value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.quad 0x00 5.--9. "RT,Rt value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.quad 0x00 1.--4. "CRM,CRm value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.quad 0x00 0. "DIRECTION,Direction of the trapped instruction" "Write,Read" endif elif (((per.q(spr:0x35520))&0xFC000000)==0x18000000) if (((per.q(spr:0x35520))&0x1000000)==0x1000000) group.quad spr:0x35520++0x00 line.quad 0x00 "ESR_EL12,Exception Syndrome Register (EL1)" bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline bitfld.quad 0x00 24. "CV,Condition code valid" "Not valid,Valid" bitfld.quad 0x00 20.--23. "COND,Condition code for the trapped instruction" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111" newline hexmask.quad.byte 0x00 12.--19. 1. "IMM8,The immediate value from the issued instruction" bitfld.quad 0x00 5.--9. "RN,Rn value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.quad 0x00 4. "OFFSET,Indicates whether the offset is added or subtracted" "Subtracted,Added" bitfld.quad 0x00 1.--3. "AM,Addressing mode" "Immediate unindexed,Immediate post-indexed,Immediate offset,Immediate pre-indexed,Literal unindexed,Reserved,Literal offset,Reserved" newline bitfld.quad 0x00 0. "DIRECTION,Direction of the trapped instruction" "Write,Read" else group.quad spr:0x35520++0x00 line.quad 0x00 "ESR_EL12,Exception Syndrome Register (EL1)" bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline bitfld.quad 0x00 24. "CV,Condition code valid" "Not valid,Valid" newline hexmask.quad.byte 0x00 12.--19. 1. "IMM8,The immediate value from the issued instruction" bitfld.quad 0x00 5.--9. "RN,Rn value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.quad 0x00 4. "OFFSET,Indicates whether the offset is added or subtracted" "Subtracted,Added" bitfld.quad 0x00 1.--3. "AM,Addressing mode" "Immediate unindexed,Immediate post-indexed,Immediate offset,Immediate pre-indexed,Literal unindexed,Reserved,Literal offset,Reserved" newline bitfld.quad 0x00 0. "DIRECTION,Direction of the trapped instruction" "Write,Read" endif elif (((per.q(spr:0x35520))&0xFC000000)==0x1C000000) if (((per.q(spr:0x35520))&0x1000000)==0x1000000) group.quad spr:0x35520++0x00 line.quad 0x00 "ESR_EL12,Exception Syndrome Register (EL1)" bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline bitfld.quad 0x00 24. "CV,Condition code valid" "Not valid,Valid" bitfld.quad 0x00 20.--23. "COND,Condition code for the trapped instruction" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111" else group.quad spr:0x35520++0x00 line.quad 0x00 "ESR_EL12,Exception Syndrome Register (EL1)" bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline bitfld.quad 0x00 24. "CV,Condition code valid" "Not valid,Valid" endif elif (((per.q(spr:0x35520))&0xFC000000)==(0x44000000||0x54000000)) group.quad spr:0x35520++0x00 line.quad 0x00 "ESR_EL12,Exception Syndrome Register (EL1)" bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline hexmask.quad.word 0x00 0.--15. 1. "IMM16,The value of the immediate field from the HVC or SVC instruction" elif (((per.q(spr:0x35520))&0xFC000000)==0x60000000) group.quad spr:0x35520++0x00 line.quad 0x00 "ESR_EL12,Exception Syndrome Register (EL1)" bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline bitfld.quad 0x00 20.--21. "OP0,Op0 value from the issued instruction" "0,1,2,3" bitfld.quad 0x00 17.--19. "OP2,Opc2 value from the issued instruction" "0,1,2,3,4,5,6,7" newline bitfld.quad 0x00 14.--16. "OP1,Opc1 value from the issued instruction" "0,1,2,3,4,5,6,7" bitfld.quad 0x00 10.--13. "CRN,CRn value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.quad 0x00 5.--9. "RT,Rt value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.quad 0x00 1.--4. "CRM,CRm value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.quad 0x00 0. "DIRECTION,Direction of the trapped instruction" "Write,Read" elif (((per.q(spr:0x35520))&0xFC000000)==(0x80000000||0x84000000)) if (((per.q(spr:0x35520))&0x3F)==(0x10)) group.quad spr:0x35520++0x00 line.quad 0x00 "ESR_EL12,Exception Syndrome Register (EL1)" bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline bitfld.quad 0x00 11.--12. "SET,Synchronous Error Type" "UER,UEO,UC,CE" newline bitfld.quad 0x00 10. "FNV,FAR not Valid" "No,Yes" bitfld.quad 0x00 9. "EA,External abort type" "Not external,External" newline bitfld.quad 0x00 7. "S1PTW,Fault on the stage 2 translation of an address accessed during a stage 1 translation table walk" "Not stage 2,Stage 2" bitfld.quad 0x00 0.--5. "IFSC,Instruction Fault Status Code" "Address size/L0/base register,Address size/L1,Address size/L2,Address size/L3,Translation/L0,Translation/L1,Translation/L2,Translation/L3,Reserved,Access flag/L1,Access flag/L2,Access flag/L3,Reserved,Permission/L1,Permission/L2,Permission/L3,Sync. external abort/not table walk,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Sync. parity/ECC/not table walk,Reserved,Reserved,Reserved,Sync. external abort/L0,Sync. external abort/L1,Sync. external abort/L2,Sync. external abort/L3,Sync. parity/ECC/L0,Sync. parity/ECC/L1,Sync. parity/ECC/L2,Sync. parity/ECC/L3,Alignment,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,TLB conflict,?..." else group.quad spr:0x35520++0x00 line.quad 0x00 "ESR_EL12,Exception Syndrome Register (EL1)" bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline newline bitfld.quad 0x00 9. "EA,External abort type" "Not external,External" newline bitfld.quad 0x00 7. "S1PTW,Fault on the stage 2 translation of an address accessed during a stage 1 translation table walk" "Not stage 2,Stage 2" bitfld.quad 0x00 0.--5. "IFSC,Instruction Fault Status Code" "Address size/L0/base register,Address size/L1,Address size/L2,Address size/L3,Translation/L0,Translation/L1,Translation/L2,Translation/L3,Reserved,Access flag/L1,Access flag/L2,Access flag/L3,Reserved,Permission/L1,Permission/L2,Permission/L3,Sync. external abort/not table walk,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Sync. parity/ECC/not table walk,Reserved,Reserved,Reserved,Sync. external abort/L0,Sync. external abort/L1,Sync. external abort/L2,Sync. external abort/L3,Sync. parity/ECC/L0,Sync. parity/ECC/L1,Sync. parity/ECC/L2,Sync. parity/ECC/L3,Alignment,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,TLB conflict,?..." endif elif (((per.q(spr:0x35520))&0xFD000000)==(0x91000000||0x95000000)) if (((per.q(spr:0x35520))&0x3F)==(0x10)) group.quad spr:0x35520++0x00 line.quad 0x00 "ESR_EL12,Exception Syndrome Register (EL1)" bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline bitfld.quad 0x00 24. "ISV,Instruction syndrome valid" "Not valid,Valid" bitfld.quad 0x00 22.--23. "SAS,Syndrome Access Size" "Byte,Halfword,Word,Doubleword" newline bitfld.quad 0x00 21. "SSE,Syndrome Sign Extend" "Not required,Required" bitfld.quad 0x00 16.--20. "SRT,Syndrome Register transfer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.quad 0x00 15. "SF,Width of the register accessed by the instruction is Sixty-Four" "32-bit,64-bit" bitfld.quad 0x00 14. "AR,Acquire/Release" "No,Yes" newline bitfld.quad 0x00 11.--12. "SET,Synchronous Error Type" "UER,UEO,UC,CE" newline bitfld.quad 0x00 10. "FNV,FAR not Valid" "No,Yes" bitfld.quad 0x00 9. "EA,External abort type" "Not external,External" newline bitfld.quad 0x00 8. "CM,Fault came from a Cache Maintenance Instruction other than DC ZVA" "No,Yes" bitfld.quad 0x00 7. "S1PTW,Fault on the stage 2 translation of an address accessed during a stage 1 translation table walk" "Not stage 2,Stage 2" newline bitfld.quad 0x00 6. "WNR,Write not Read" "Read,Write" bitfld.quad 0x00 0.--5. "DFSC,Data Fault Status Code" "Address size/L0/TTBR,Address size/L1,Address size/L2,Address size/L3,Translation/L0,Translation/L1,Translation/L2,Translation/L3,Reserved,Access flag/L1,Access flag/L2,Access flag/L3,Reserved,Permission/L1,Permission/L2,Permission/L3,Sync. external abort/not table walk,Reserved,Reserved,Reserved,Sync. external abort/L0,Sync. external abort/L1,Sync. external abort/L2,Sync. external abort/L3,Sync. parity/ECC/not table walk,Reserved,Reserved,Reserved,Sync. parity/ECC/L0,Sync. parity/ECC/L1,Sync. parity/ECC/L2,Sync. parity/ECC/L3,Reserved,Alignment,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,TLB conflict,Reserved,Reserved,Reserved,Lockdown,Unsupported Exclusive/Atomic access,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Section Domain,Page Domain,Reserved" else group.quad spr:0x35520++0x00 line.quad 0x00 "ESR_EL12,Exception Syndrome Register (EL1)" bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline bitfld.quad 0x00 24. "ISV,Instruction syndrome valid" "Not valid,Valid" bitfld.quad 0x00 22.--23. "SAS,Syndrome Access Size" "Byte,Halfword,Word,Doubleword" newline bitfld.quad 0x00 21. "SSE,Syndrome Sign Extend" "Not required,Required" bitfld.quad 0x00 16.--20. "SRT,Syndrome Register transfer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.quad 0x00 15. "SF,Width of the register accessed by the instruction is Sixty-Four" "32-bit,64-bit" bitfld.quad 0x00 14. "AR,Acquire/Release" "No,Yes" newline newline bitfld.quad 0x00 9. "EA,External abort type" "Not external,External" newline bitfld.quad 0x00 8. "CM,Fault came from a Cache Maintenance Instruction other than DC ZVA" "No,Yes" bitfld.quad 0x00 7. "S1PTW,Fault on the stage 2 translation of an address accessed during a stage 1 translation table walk" "Not stage 2,Stage 2" newline bitfld.quad 0x00 6. "WNR,Write not Read" "Read,Write" bitfld.quad 0x00 0.--5. "DFSC,Data Fault Status Code" "Address size/L0/TTBR,Address size/L1,Address size/L2,Address size/L3,Translation/L0,Translation/L1,Translation/L2,Translation/L3,Reserved,Access flag/L1,Access flag/L2,Access flag/L3,Reserved,Permission/L1,Permission/L2,Permission/L3,Sync. external abort/not table walk,Reserved,Reserved,Reserved,Sync. external abort/L0,Sync. external abort/L1,Sync. external abort/L2,Sync. external abort/L3,Sync. parity/ECC/not table walk,Reserved,Reserved,Reserved,Sync. parity/ECC/L0,Sync. parity/ECC/L1,Sync. parity/ECC/L2,Sync. parity/ECC/L3,Reserved,Alignment,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,TLB conflict,Reserved,Reserved,Reserved,Lockdown,Unsupported Exclusive/Atomic access,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Section Domain,Page Domain,Reserved" endif elif (((per.q(spr:0x35520))&0xFD000000)==(0x90000000||0x94000000)) if (((per.q(spr:0x35520))&0x3F)==(0x10)) group.quad spr:0x35520++0x00 line.quad 0x00 "ESR_EL12,Exception Syndrome Register (EL1)" bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline bitfld.quad 0x00 24. "ISV,Instruction syndrome valid" "Not valid,Valid" newline newline newline bitfld.quad 0x00 11.--12. "SET,Synchronous Error Type" "UER,UEO,UC,CE" newline bitfld.quad 0x00 10. "FNV,FAR not Valid" "No,Yes" bitfld.quad 0x00 9. "EA,External abort type" "Not external,External" newline bitfld.quad 0x00 8. "CM,Fault came from a Cache Maintenance Instruction other than DC ZVA" "No,Yes" bitfld.quad 0x00 7. "S1PTW,Fault on the stage 2 translation of an address accessed during a stage 1 translation table walk" "Not stage 2,Stage 2" newline bitfld.quad 0x00 6. "WNR,Write not Read" "Read,Write" bitfld.quad 0x00 0.--5. "DFSC,Data Fault Status Code" "Address size/L0/TTBR,Address size/L1,Address size/L2,Address size/L3,Translation/L0,Translation/L1,Translation/L2,Translation/L3,Reserved,Access flag/L1,Access flag/L2,Access flag/L3,Reserved,Permission/L1,Permission/L2,Permission/L3,Sync. external abort/not table walk,Reserved,Reserved,Reserved,Sync. external abort/L0,Sync. external abort/L1,Sync. external abort/L2,Sync. external abort/L3,Sync. parity/ECC/not table walk,Reserved,Reserved,Reserved,Sync. parity/ECC/L0,Sync. parity/ECC/L1,Sync. parity/ECC/L2,Sync. parity/ECC/L3,Reserved,Alignment,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,TLB conflict,Reserved,Reserved,Reserved,Lockdown,Unsupported Exclusive/Atomic access,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Section Domain,Page Domain,Reserved" else group.quad spr:0x35520++0x00 line.quad 0x00 "ESR_EL12,Exception Syndrome Register (EL1)" bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline bitfld.quad 0x00 24. "ISV,Instruction syndrome valid" "Not valid,Valid" newline newline newline newline bitfld.quad 0x00 9. "EA,External abort type" "Not external,External" newline bitfld.quad 0x00 8. "CM,Fault came from a Cache Maintenance Instruction other than DC ZVA" "No,Yes" bitfld.quad 0x00 7. "S1PTW,Fault on the stage 2 translation of an address accessed during a stage 1 translation table walk" "Not stage 2,Stage 2" newline bitfld.quad 0x00 6. "WNR,Write not Read" "Read,Write" bitfld.quad 0x00 0.--5. "DFSC,Data Fault Status Code" "Address size/L0/TTBR,Address size/L1,Address size/L2,Address size/L3,Translation/L0,Translation/L1,Translation/L2,Translation/L3,Reserved,Access flag/L1,Access flag/L2,Access flag/L3,Reserved,Permission/L1,Permission/L2,Permission/L3,Sync. external abort/not table walk,Reserved,Reserved,Reserved,Sync. external abort/L0,Sync. external abort/L1,Sync. external abort/L2,Sync. external abort/L3,Sync. parity/ECC/not table walk,Reserved,Reserved,Reserved,Sync. parity/ECC/L0,Sync. parity/ECC/L1,Sync. parity/ECC/L2,Sync. parity/ECC/L3,Reserved,Alignment,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,TLB conflict,Reserved,Reserved,Reserved,Lockdown,Unsupported Exclusive/Atomic access,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Section Domain,Page Domain,Reserved" endif elif (((per.q(spr:0x35520))&0xFC800000)==(0xA0800000||0xB0800000)) group.quad spr:0x35520++0x00 line.quad 0x00 "ESR_EL12,Exception Syndrome Register (EL1)" bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline bitfld.quad 0x00 23. "TFV,Trapped Fault Valid" "Not valid,Valid" bitfld.quad 0x00 8.--10. "VECITR,Number of the element that is being reported" "0,1,2,3,4,5,6,7" newline bitfld.quad 0x00 7. "IDF,Input Denormal floating-point exception trapped" "Not occurred,Occurred" bitfld.quad 0x00 4. "IXF,Inexact floating-point exception trapped" "Not occurred,Occurred" newline bitfld.quad 0x00 3. "UFF,Underflow floating-point exception trapped" "Not occurred,Occurred" bitfld.quad 0x00 2. "OFF,Overflow floating-point exception trapped" "Not occurred,Occurred" newline bitfld.quad 0x00 1. "DZF,Divide-by-zero floating-point exception trapped" "Not occurred,Occurred" bitfld.quad 0x00 0. "IOF,Invalid Operation floating-point exception trapped" "Not occurred,Occurred" elif (((per.q(spr:0x35520))&0xFC800000)==(0xA0000000||0xB0000000)) group.quad spr:0x35520++0x00 line.quad 0x00 "ESR_EL12,Exception Syndrome Register (EL1)" bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline bitfld.quad 0x00 23. "TFV,Trapped Fault Valid" "Not valid,Valid" bitfld.quad 0x00 8.--10. "VECITR,Number of the element that is being reported" "0,1,2,3,4,5,6,7" elif (((per.q(spr:0x35520))&0xFD000000)==0xBD000000) if (((per.q(spr:0x35520))&0x3F)==0x11) group.quad spr:0x35520++0x00 line.quad 0x00 "ESR_EL12,Exception Syndrome Register (EL1)" bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline bitfld.quad 0x00 24. "IDS,Implementation defined syndrome" "Not hold,Hold" bitfld.quad 0x00 13. "IESB,Implicit Error Synchronization Barrier" "Not synchronized,Synchronized" newline bitfld.quad 0x00 10.--12. "AET,Asynchronous Error Type" "UC,UEU,UEO,UER,CE,?..." bitfld.quad 0x00 9. "EA,External abort type" "No,Yes" newline bitfld.quad 0x00 0.--5. "DFSC,Data Fault Status Code" "Uncategorized,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Asynchronous,?..." else group.quad spr:0x35520++0x00 line.quad 0x00 "ESR_EL12,Exception Syndrome Register (EL1)" bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline bitfld.quad 0x00 24. "IDS,Implementation defined syndrome" "Not hold,Hold" bitfld.quad 0x00 9. "EA,External abort type" "No,Yes" newline bitfld.quad 0x00 0.--5. "DFSC,Data Fault Status Code" "Uncategorized,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Asynchronous,?..." endif elif (((per.q(spr:0x35520))&0xFD000000)==0xBC000000) group.quad spr:0x35520++0x00 line.quad 0x00 "ESR_EL12,Exception Syndrome Register (EL1)" bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline bitfld.quad 0x00 24. "IDS,Implementation defined syndrome" "Not hold,Hold" elif (((per.q(spr:0x35520))&0xFC000000)==(0xC0000000||0xC4000000)) group.quad spr:0x35520++0x00 line.quad 0x00 "ESR_EL12,Exception Syndrome Register (EL1)" bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline bitfld.quad 0x00 0.--5. "IFSC,Instruction Fault Status Code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,Debug exception,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" elif (((per.q(spr:0x35520))&0xFC000000)==(0xC8000000||0xCC000000)) group.quad spr:0x35520++0x00 line.quad 0x00 "ESR_EL12,Exception Syndrome Register (EL1)" bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline bitfld.quad 0x00 24. "ISV,EX bit valid" "Not valid,Valid" bitfld.quad 0x00 6. "EX,Exclusive operation" "No,Yes" newline bitfld.quad 0x00 0.--5. "IFSC,Instruction Fault Status Code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,Debug exception,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" elif (((per.q(spr:0x35520))&0xFC000000)==(0xD0000000||0xD4000000)) group.quad spr:0x35520++0x00 line.quad 0x00 "ESR_EL12,Exception Syndrome Register (EL1)" bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline bitfld.quad 0x00 8. "CM,Data came from a Cache Maintenance Instruction other than DC ZVA" "No,Yes" bitfld.quad 0x00 6. "WNR,Write not Read" "Read,Write" newline bitfld.quad 0x00 0.--5. "IFSC,Instruction Fault Status Code" "0,1,2,3,?..." elif (((per.q(spr:0x35520))&0xFC000000)==(0xE0000000||0xF0000000)) group.quad spr:0x35520++0x00 line.quad 0x00 "ESR_EL12,Exception Syndrome Register (EL1)" bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline hexmask.quad.word 0x00 0.--15. 1. "COMMENT,Set to the instruction comment field value" else group.quad spr:0x35520++0x00 line.quad 0x00 "ESR_EL12,Exception Syndrome Register (EL1)" bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" endif if (((per.q(spr:0x34520))&0xFC000000)==(0x00000000||0x38000000||0x88000000||0x98000000)) group.quad spr:0x34520++0x00 line.quad 0x00 "ESR_EL2,Exception Syndrome Register (EL2)" bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,MCR/VMRS to CP10/AArch32,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,HVC in AArch32,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Vector Catch,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" elif (((per.q(spr:0x34520))&0xFC000000)==0x04000000) if (((per.q(spr:0x34520))&0x1000000)==0x1000000) group.quad spr:0x34520++0x00 line.quad 0x00 "ESR_EL2,Exception Syndrome Register (EL2)" bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,MCR/VMRS to CP10/AArch32,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,HVC in AArch32,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Vector Catch,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline bitfld.quad 0x00 24. "CV,Condition code valid" "Not valid,Valid" bitfld.quad 0x00 20.--23. "COND,Condition code for the trapped instruction" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111" newline bitfld.quad 0x00 0. "TI,Trapped instruction" "WFI,WFE" else group.quad spr:0x34520++0x00 line.quad 0x00 "ESR_EL2,Exception Syndrome Register (EL2)" bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,MCR/VMRS to CP10/AArch32,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,HVC in AArch32,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Vector Catch,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline bitfld.quad 0x00 24. "CV,Condition code valid" "Not valid,Valid" newline bitfld.quad 0x00 0. "TI,Trapped instruction" "WFI,WFE" endif elif (((per.q(spr:0x34520))&0xFC000000)==(0x0C000000||0x14000000||0x20000000)) if (((per.q(spr:0x34520))&0x1000000)==0x1000000) group.quad spr:0x34520++0x00 line.quad 0x00 "ESR_EL2,Exception Syndrome Register (EL2)" bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,MCR/VMRS to CP10/AArch32,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,HVC in AArch32,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Vector Catch,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline bitfld.quad 0x00 24. "CV,Condition code valid" "Not valid,Valid" bitfld.quad 0x00 20.--23. "COND,Condition code for the trapped instruction" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111" newline bitfld.quad 0x00 17.--19. "OPC2,Opc2 value from the issued instruction" "0,1,2,3,4,5,6,7" bitfld.quad 0x00 14.--16. "OPC1,Opc1 value from the issued instruction" "0,1,2,3,4,5,6,7" newline bitfld.quad 0x00 10.--13. "CRN,CRn value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.quad 0x00 5.--9. "RT,Rt value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.quad 0x00 1.--4. "CRM,CRm value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.quad 0x00 0. "DIRECTION,Direction of the trapped instruction" "Write,Read" else group.quad spr:0x34520++0x00 line.quad 0x00 "ESR_EL2,Exception Syndrome Register (EL2)" bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,MCR/VMRS to CP10/AArch32,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,HVC in AArch32,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Vector Catch,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline bitfld.quad 0x00 24. "CV,Condition code valid" "Not valid,Valid" newline bitfld.quad 0x00 17.--19. "OPC2,Opc2 value from the issued instruction" "0,1,2,3,4,5,6,7" bitfld.quad 0x00 14.--16. "OPC1,Opc1 value from the issued instruction" "0,1,2,3,4,5,6,7" newline bitfld.quad 0x00 10.--13. "CRN,CRn value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.quad 0x00 5.--9. "RT,Rt value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.quad 0x00 1.--4. "CRM,CRm value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.quad 0x00 0. "DIRECTION,Direction of the trapped instruction" "Write,Read" endif elif (((per.q(spr:0x34520))&0xFC000000)==(0x10000000||0x30000000)) if (((per.q(spr:0x34520))&0x1000000)==0x1000000) group.quad spr:0x34520++0x00 line.quad 0x00 "ESR_EL2,Exception Syndrome Register (EL2)" bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,MCR/VMRS to CP10/AArch32,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,HVC in AArch32,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Vector Catch,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline bitfld.quad 0x00 24. "CV,Condition code valid" "Not valid,Valid" bitfld.quad 0x00 20.--23. "COND,Condition code for the trapped instruction" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111" newline bitfld.quad 0x00 16.--19. "OPC1,Opc1 value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.quad 0x00 10.--14. "RT2,Rt2 value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.quad 0x00 5.--9. "RT,Rt value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.quad 0x00 1.--4. "CRM,CRm value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.quad 0x00 0. "DIRECTION,Direction of the trapped instruction" "Write,Read" else group.quad spr:0x34520++0x00 line.quad 0x00 "ESR_EL2,Exception Syndrome Register (EL2)" bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,MCR/VMRS to CP10/AArch32,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,HVC in AArch32,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Vector Catch,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline bitfld.quad 0x00 24. "CV,Condition code valid" "Not valid,Valid" newline bitfld.quad 0x00 16.--19. "OPC1,Opc1 value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.quad 0x00 10.--14. "RT2,Rt2 value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.quad 0x00 5.--9. "RT,Rt value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.quad 0x00 1.--4. "CRM,CRm value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.quad 0x00 0. "DIRECTION,Direction of the trapped instruction" "Write,Read" endif elif (((per.q(spr:0x34520))&0xFC000000)==0x18000000) if (((per.q(spr:0x34520))&0x1000000)==0x1000000) group.quad spr:0x34520++0x00 line.quad 0x00 "ESR_EL2,Exception Syndrome Register (EL2)" bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,MCR/VMRS to CP10/AArch32,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,HVC in AArch32,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Vector Catch,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline bitfld.quad 0x00 24. "CV,Condition code valid" "Not valid,Valid" bitfld.quad 0x00 20.--23. "COND,Condition code for the trapped instruction" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111" newline hexmask.quad.byte 0x00 12.--19. 1. "IMM8,The immediate value from the issued instruction" bitfld.quad 0x00 5.--9. "RN,Rn value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.quad 0x00 4. "OFFSET,Indicates whether the offset is added or subtracted" "Subtracted,Added" bitfld.quad 0x00 1.--3. "AM,Addressing mode" "Immediate unindexed,Immediate post-indexed,Immediate offset,Immediate pre-indexed,Literal unindexed,Reserved,Literal offset,Reserved" newline bitfld.quad 0x00 0. "DIRECTION,Direction of the trapped instruction" "Write,Read" else group.quad spr:0x34520++0x00 line.quad 0x00 "ESR_EL2,Exception Syndrome Register (EL2)" bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,MCR/VMRS to CP10/AArch32,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,HVC in AArch32,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Vector Catch,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline bitfld.quad 0x00 24. "CV,Condition code valid" "Not valid,Valid" newline hexmask.quad.byte 0x00 12.--19. 1. "IMM8,The immediate value from the issued instruction" bitfld.quad 0x00 5.--9. "RN,Rn value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.quad 0x00 4. "OFFSET,Indicates whether the offset is added or subtracted" "Subtracted,Added" bitfld.quad 0x00 1.--3. "AM,Addressing mode" "Immediate unindexed,Immediate post-indexed,Immediate offset,Immediate pre-indexed,Literal unindexed,Reserved,Literal offset,Reserved" newline bitfld.quad 0x00 0. "DIRECTION,Direction of the trapped instruction" "Write,Read" endif elif (((per.q(spr:0x34520))&0xFC000000)==0x1C000000) if (((per.q(spr:0x34520))&0x1000000)==0x1000000) group.quad spr:0x34520++0x00 line.quad 0x00 "ESR_EL2,Exception Syndrome Register (EL2)" bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,MCR/VMRS to CP10/AArch32,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,HVC in AArch32,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Vector Catch,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline bitfld.quad 0x00 24. "CV,Condition code valid" "Not valid,Valid" bitfld.quad 0x00 20.--23. "COND,Condition code for the trapped instruction" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111" else group.quad spr:0x34520++0x00 line.quad 0x00 "ESR_EL2,Exception Syndrome Register (EL2)" bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,MCR/VMRS to CP10/AArch32,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,HVC in AArch32,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Vector Catch,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline bitfld.quad 0x00 24. "CV,Condition code valid" "Not valid,Valid" endif elif (((per.q(spr:0x34520))&0xFC000000)==(0x44000000||0x48000000||0x54000000||0x58000000)) group.quad spr:0x34520++0x00 line.quad 0x00 "ESR_EL2,Exception Syndrome Register (EL2)" bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,MCR/VMRS to CP10/AArch32,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,HVC in AArch32,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Vector Catch,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline hexmask.quad.word 0x00 0.--15. 1. "IMM16,The value of the immediate field from the HVC or SVC instruction" elif (((per.q(spr:0x34520))&0xFC000000)==0x4C000000) if ((((per.q(spr:0x34520))&0x1000000)==0x1000000)&&(((per.q(spr:0x34520))&0xF0000)==0x80000)) group.quad spr:0x34520++0x00 line.quad 0x00 "ESR_EL2,Exception Syndrome Register (EL2)" bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,MCR/VMRS to CP10/AArch32,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,HVC in AArch32,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Vector Catch,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline bitfld.quad 0x00 24. "CV,Condition code valid" "Not valid,Valid" bitfld.quad 0x00 20.--23. "COND,Condition code for the trapped instruction" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111" newline bitfld.quad 0x00 19. "CCKNOWNPASS,Indicates whether the instruction might have failed its condition code check" "Unconditional,Conditional" elif (((per.q(spr:0x34520))&0xF0000)==0x80000) group.quad spr:0x34520++0x00 line.quad 0x00 "ESR_EL2,Exception Syndrome Register (EL2)" bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,MCR/VMRS to CP10/AArch32,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,HVC in AArch32,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Vector Catch,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline bitfld.quad 0x00 24. "CV,Condition code valid" "Not valid,Valid" newline bitfld.quad 0x00 19. "CCKNOWNPASS,Indicates whether the instruction might have failed its condition code check" "Unconditional,Conditional" else group.quad spr:0x34520++0x00 line.quad 0x00 "ESR_EL2,Exception Syndrome Register (EL2)" bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,MCR/VMRS to CP10/AArch32,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,HVC in AArch32,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Vector Catch,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline newline bitfld.quad 0x00 19. "CCKNOWNPASS,Indicates whether the instruction might have failed its condition code check" "Unconditional,Conditional" endif elif (((per.q(spr:0x34520))&0xFC000000)==0x5C000000) group.quad spr:0x34520++0x00 line.quad 0x00 "ESR_EL2,Exception Syndrome Register (EL2)" bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,MCR/VMRS to CP10/AArch32,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,HVC in AArch32,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Vector Catch,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline hexmask.quad.word 0x00 0.--15. 1. "IMM16,The value of the immediate field from the issued SMC instruction" elif (((per.q(spr:0x34520))&0xFC000000)==0x60000000) group.quad spr:0x34520++0x00 line.quad 0x00 "ESR_EL2,Exception Syndrome Register (EL2)" bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,MCR/VMRS to CP10/AArch32,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,HVC in AArch32,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Vector Catch,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline bitfld.quad 0x00 20.--21. "OP0,Op0 value from the issued instruction" "0,1,2,3" bitfld.quad 0x00 17.--19. "OP2,Opc2 value from the issued instruction" "0,1,2,3,4,5,6,7" newline bitfld.quad 0x00 14.--16. "OP1,Opc1 value from the issued instruction" "0,1,2,3,4,5,6,7" bitfld.quad 0x00 10.--13. "CRN,CRn value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.quad 0x00 5.--9. "RT,Rt value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.quad 0x00 1.--4. "CRM,CRm value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.quad 0x00 0. "DIRECTION,Direction of the trapped instruction" "Write,Read" elif (((per.q(spr:0x34520))&0xFC000000)==(0x80000000||0x84000000)) if (((per.q(spr:0x34520))&0x3F)==(0x10)) group.quad spr:0x34520++0x00 line.quad 0x00 "ESR_EL2,Exception Syndrome Register (EL2)" bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,MCR/VMRS to CP10/AArch32,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,HVC in AArch32,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Vector Catch,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline bitfld.quad 0x00 11.--12. "SET,Synchronous Error Type" "UER,UEO,UC,CE" newline bitfld.quad 0x00 10. "FNV,FAR not Valid" "No,Yes" bitfld.quad 0x00 9. "EA,External abort type" "Not external,External" newline bitfld.quad 0x00 7. "S1PTW,Fault on the stage 2 translation of an address accessed during a stage 1 translation table walk" "Not stage 2,Stage 2" bitfld.quad 0x00 0.--5. "IFSC,Instruction Fault Status Code" "Address size/L0/base register,Address size/L1,Address size/L2,Address size/L3,Translation/L0,Translation/L1,Translation/L2,Translation/L3,Reserved,Access flag/L1,Access flag/L2,Access flag/L3,Reserved,Permission/L1,Permission/L2,Permission/L3,Sync. external abort/not table walk,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Sync. parity/ECC/not table walk,Reserved,Reserved,Reserved,Sync. external abort/L0,Sync. external abort/L1,Sync. external abort/L2,Sync. external abort/L3,Sync. parity/ECC/L0,Sync. parity/ECC/L1,Sync. parity/ECC/L2,Sync. parity/ECC/L3,Alignment,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,TLB conflict,?..." else group.quad spr:0x34520++0x00 line.quad 0x00 "ESR_EL2,Exception Syndrome Register (EL2)" bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,MCR/VMRS to CP10/AArch32,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,HVC in AArch32,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Vector Catch,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline newline bitfld.quad 0x00 9. "EA,External abort type" "Not external,External" newline bitfld.quad 0x00 7. "S1PTW,Fault on the stage 2 translation of an address accessed during a stage 1 translation table walk" "Not stage 2,Stage 2" bitfld.quad 0x00 0.--5. "IFSC,Instruction Fault Status Code" "Address size/L0/base register,Address size/L1,Address size/L2,Address size/L3,Translation/L0,Translation/L1,Translation/L2,Translation/L3,Reserved,Access flag/L1,Access flag/L2,Access flag/L3,Reserved,Permission/L1,Permission/L2,Permission/L3,Sync. external abort/not table walk,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Sync. parity/ECC/not table walk,Reserved,Reserved,Reserved,Sync. external abort/L0,Sync. external abort/L1,Sync. external abort/L2,Sync. external abort/L3,Sync. parity/ECC/L0,Sync. parity/ECC/L1,Sync. parity/ECC/L2,Sync. parity/ECC/L3,Alignment,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,TLB conflict,?..." endif elif (((per.q(spr:0x34520))&0xFD000000)==(0x91000000||0x95000000)) if (((per.q(spr:0x34520))&0x3F)==(0x10)) group.quad spr:0x34520++0x00 line.quad 0x00 "ESR_EL2,Exception Syndrome Register (EL2)" bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,MCR/VMRS to CP10/AArch32,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,HVC in AArch32,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Vector Catch,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline bitfld.quad 0x00 24. "ISV,Instruction syndrome valid" "Not valid,Valid" bitfld.quad 0x00 22.--23. "SAS,Syndrome Access Size" "Byte,Halfword,Word,Doubleword" newline bitfld.quad 0x00 21. "SSE,Syndrome Sign Extend" "Not required,Required" bitfld.quad 0x00 16.--20. "SRT,Syndrome Register transfer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.quad 0x00 15. "SF,Width of the register accessed by the instruction is Sixty-Four" "32-bit,64-bit" bitfld.quad 0x00 14. "AR,Acquire/Release" "No,Yes" newline bitfld.quad 0x00 11.--12. "SET,Synchronous Error Type" "UER,UEO,UC,CE" newline bitfld.quad 0x00 10. "FNV,FAR not Valid" "No,Yes" bitfld.quad 0x00 9. "EA,External abort type" "Not external,External" newline bitfld.quad 0x00 8. "CM,Fault came from a Cache Maintenance Instruction other than DC ZVA" "No,Yes" bitfld.quad 0x00 7. "S1PTW,Fault on the stage 2 translation of an address accessed during a stage 1 translation table walk" "Not stage 2,Stage 2" newline bitfld.quad 0x00 6. "WNR,Write not Read" "Read,Write" bitfld.quad 0x00 0.--5. "DFSC,Data Fault Status Code" "Address size/L0/TTBR,Address size/L1,Address size/L2,Address size/L3,Translation/L0,Translation/L1,Translation/L2,Translation/L3,Reserved,Access flag/L1,Access flag/L2,Access flag/L3,Reserved,Permission/L1,Permission/L2,Permission/L3,Sync. external abort/not table walk,Reserved,Reserved,Reserved,Sync. external abort/L0,Sync. external abort/L1,Sync. external abort/L2,Sync. external abort/L3,Sync. parity/ECC/not table walk,Reserved,Reserved,Reserved,Sync. parity/ECC/L0,Sync. parity/ECC/L1,Sync. parity/ECC/L2,Sync. parity/ECC/L3,Reserved,Alignment,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,TLB conflict,Reserved,Reserved,Reserved,Lockdown,Unsupported Exclusive/Atomic access,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Section Domain,Page Domain,Reserved" else group.quad spr:0x34520++0x00 line.quad 0x00 "ESR_EL2,Exception Syndrome Register (EL2)" bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,MCR/VMRS to CP10/AArch32,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,HVC in AArch32,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Vector Catch,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline bitfld.quad 0x00 24. "ISV,Instruction syndrome valid" "Not valid,Valid" bitfld.quad 0x00 22.--23. "SAS,Syndrome Access Size" "Byte,Halfword,Word,Doubleword" newline bitfld.quad 0x00 21. "SSE,Syndrome Sign Extend" "Not required,Required" bitfld.quad 0x00 16.--20. "SRT,Syndrome Register transfer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.quad 0x00 15. "SF,Width of the register accessed by the instruction is Sixty-Four" "32-bit,64-bit" bitfld.quad 0x00 14. "AR,Acquire/Release" "No,Yes" newline newline bitfld.quad 0x00 9. "EA,External abort type" "Not external,External" newline bitfld.quad 0x00 8. "CM,Fault came from a Cache Maintenance Instruction other than DC ZVA" "No,Yes" bitfld.quad 0x00 7. "S1PTW,Fault on the stage 2 translation of an address accessed during a stage 1 translation table walk" "Not stage 2,Stage 2" newline bitfld.quad 0x00 6. "WNR,Write not Read" "Read,Write" bitfld.quad 0x00 0.--5. "DFSC,Data Fault Status Code" "Address size/L0/TTBR,Address size/L1,Address size/L2,Address size/L3,Translation/L0,Translation/L1,Translation/L2,Translation/L3,Reserved,Access flag/L1,Access flag/L2,Access flag/L3,Reserved,Permission/L1,Permission/L2,Permission/L3,Sync. external abort/not table walk,Reserved,Reserved,Reserved,Sync. external abort/L0,Sync. external abort/L1,Sync. external abort/L2,Sync. external abort/L3,Sync. parity/ECC/not table walk,Reserved,Reserved,Reserved,Sync. parity/ECC/L0,Sync. parity/ECC/L1,Sync. parity/ECC/L2,Sync. parity/ECC/L3,Reserved,Alignment,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,TLB conflict,Reserved,Reserved,Reserved,Lockdown,Unsupported Exclusive/Atomic access,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Section Domain,Page Domain,Reserved" endif elif (((per.q(spr:0x34520))&0xFD000000)==(0x90000000||0x94000000)) if (((per.q(spr:0x34520))&0x3F)==(0x10)) group.quad spr:0x34520++0x00 line.quad 0x00 "ESR_EL2,Exception Syndrome Register (EL2)" bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,MCR/VMRS to CP10/AArch32,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,HVC in AArch32,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Vector Catch,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline bitfld.quad 0x00 24. "ISV,Instruction syndrome valid" "Not valid,Valid" newline newline newline bitfld.quad 0x00 11.--12. "SET,Synchronous Error Type" "UER,UEO,UC,CE" newline bitfld.quad 0x00 10. "FNV,FAR not Valid" "No,Yes" bitfld.quad 0x00 9. "EA,External abort type" "Not external,External" newline bitfld.quad 0x00 8. "CM,Fault came from a Cache Maintenance Instruction other than DC ZVA" "No,Yes" bitfld.quad 0x00 7. "S1PTW,Fault on the stage 2 translation of an address accessed during a stage 1 translation table walk" "Not stage 2,Stage 2" newline bitfld.quad 0x00 6. "WNR,Write not Read" "Read,Write" bitfld.quad 0x00 0.--5. "DFSC,Data Fault Status Code" "Address size/L0/TTBR,Address size/L1,Address size/L2,Address size/L3,Translation/L0,Translation/L1,Translation/L2,Translation/L3,Reserved,Access flag/L1,Access flag/L2,Access flag/L3,Reserved,Permission/L1,Permission/L2,Permission/L3,Sync. external abort/not table walk,Reserved,Reserved,Reserved,Sync. external abort/L0,Sync. external abort/L1,Sync. external abort/L2,Sync. external abort/L3,Sync. parity/ECC/not table walk,Reserved,Reserved,Reserved,Sync. parity/ECC/L0,Sync. parity/ECC/L1,Sync. parity/ECC/L2,Sync. parity/ECC/L3,Reserved,Alignment,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,TLB conflict,Reserved,Reserved,Reserved,Lockdown,Unsupported Exclusive/Atomic access,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Section Domain,Page Domain,Reserved" else group.quad spr:0x34520++0x00 line.quad 0x00 "ESR_EL2,Exception Syndrome Register (EL2)" bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,MCR/VMRS to CP10/AArch32,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,HVC in AArch32,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Vector Catch,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline bitfld.quad 0x00 24. "ISV,Instruction syndrome valid" "Not valid,Valid" newline newline newline newline bitfld.quad 0x00 9. "EA,External abort type" "Not external,External" newline bitfld.quad 0x00 8. "CM,Fault came from a Cache Maintenance Instruction other than DC ZVA" "No,Yes" bitfld.quad 0x00 7. "S1PTW,Fault on the stage 2 translation of an address accessed during a stage 1 translation table walk" "Not stage 2,Stage 2" newline bitfld.quad 0x00 6. "WNR,Write not Read" "Read,Write" bitfld.quad 0x00 0.--5. "DFSC,Data Fault Status Code" "Address size/L0/TTBR,Address size/L1,Address size/L2,Address size/L3,Translation/L0,Translation/L1,Translation/L2,Translation/L3,Reserved,Access flag/L1,Access flag/L2,Access flag/L3,Reserved,Permission/L1,Permission/L2,Permission/L3,Sync. external abort/not table walk,Reserved,Reserved,Reserved,Sync. external abort/L0,Sync. external abort/L1,Sync. external abort/L2,Sync. external abort/L3,Sync. parity/ECC/not table walk,Reserved,Reserved,Reserved,Sync. parity/ECC/L0,Sync. parity/ECC/L1,Sync. parity/ECC/L2,Sync. parity/ECC/L3,Reserved,Alignment,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,TLB conflict,Reserved,Reserved,Reserved,Lockdown,Unsupported Exclusive/Atomic access,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Section Domain,Page Domain,Reserved" endif elif (((per.q(spr:0x34520))&0xFC800000)==(0xA0800000||0xB0800000)) group.quad spr:0x34520++0x00 line.quad 0x00 "ESR_EL2,Exception Syndrome Register (EL2)" bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,MCR/VMRS to CP10/AArch32,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,HVC in AArch32,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Vector Catch,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline bitfld.quad 0x00 23. "TFV,Trapped Fault Valid" "Not valid,Valid" bitfld.quad 0x00 8.--10. "VECITR,Number of the element that is being reported" "0,1,2,3,4,5,6,7" newline bitfld.quad 0x00 7. "IDF,Input Denormal floating-point exception trapped" "Not occurred,Occurred" bitfld.quad 0x00 4. "IXF,Inexact floating-point exception trapped" "Not occurred,Occurred" newline bitfld.quad 0x00 3. "UFF,Underflow floating-point exception trapped" "Not occurred,Occurred" bitfld.quad 0x00 2. "OFF,Overflow floating-point exception trapped" "Not occurred,Occurred" newline bitfld.quad 0x00 1. "DZF,Divide-by-zero floating-point exception trapped" "Not occurred,Occurred" bitfld.quad 0x00 0. "IOF,Invalid Operation floating-point exception trapped" "Not occurred,Occurred" elif (((per.q(spr:0x34520))&0xFC800000)==(0xA0000000||0xB0000000)) group.quad spr:0x34520++0x00 line.quad 0x00 "ESR_EL2,Exception Syndrome Register (EL2)" bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,MCR/VMRS to CP10/AArch32,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,HVC in AArch32,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Vector Catch,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline bitfld.quad 0x00 23. "TFV,Trapped Fault Valid" "Not valid,Valid" bitfld.quad 0x00 8.--10. "VECITR,Number of the element that is being reported" "0,1,2,3,4,5,6,7" elif (((per.q(spr:0x34520))&0xFD000000)==0xBD000000) if (((per.q(spr:0x34520))&0x3F)==0x11) group.quad spr:0x34520++0x00 line.quad 0x00 "ESR_EL2,Exception Syndrome Register (EL2)" bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline bitfld.quad 0x00 24. "IDS,Implementation defined syndrome" "Not hold,Hold" bitfld.quad 0x00 13. "IESB,Implicit Error Synchronization Barrier" "Not synchronized,Synchronized" newline bitfld.quad 0x00 10.--12. "AET,Asynchronous Error Type" "UC,UEU,UEO,UER,CE,?..." newline bitfld.quad 0x00 9. "EA,External abort type" "No,Yes" bitfld.quad 0x00 0.--5. "DFSC,Data Fault Status Code" "Uncategorized,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Asynchronous,?..." else group.quad spr:0x34520++0x00 line.quad 0x00 "ESR_EL2,Exception Syndrome Register (EL2)" bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline bitfld.quad 0x00 24. "IDS,Implementation defined syndrome" "Not hold,Hold" newline newline bitfld.quad 0x00 9. "EA,External abort type" "No,Yes" bitfld.quad 0x00 0.--5. "DFSC,Data Fault Status Code" "Uncategorized,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Asynchronous,?..." endif elif (((per.q(spr:0x34520))&0xFD000000)==0xBC000000) group.quad spr:0x34520++0x00 line.quad 0x00 "ESR_EL2,Exception Syndrome Register (EL2)" bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline bitfld.quad 0x00 24. "IDS,Implementation defined syndrome" "Not hold,Hold" elif (((per.q(spr:0x34520))&0xFC000000)==(0xC0000000||0xC4000000||0xE8000000)) group.quad spr:0x34520++0x00 line.quad 0x00 "ESR_EL2,Exception Syndrome Register (EL2)" bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,MCR/VMRS to CP10/AArch32,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,HVC in AArch32,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Vector Catch,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline bitfld.quad 0x00 0.--5. "IFSC,Instruction Fault Status Code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,Debug exception,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" elif (((per.q(spr:0x34520))&0xFC000000)==(0xC8000000||0xCC000000)) group.quad spr:0x34520++0x00 line.quad 0x00 "ESR_EL2,Exception Syndrome Register (EL2)" bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,MCR/VMRS to CP10/AArch32,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,HVC in AArch32,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Vector Catch,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline bitfld.quad 0x00 24. "ISV,EX bit valid" "Not valid,Valid" bitfld.quad 0x00 6. "EX,Exclusive operation" "No,Yes" newline bitfld.quad 0x00 0.--5. "IFSC,Instruction Fault Status Code" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,Debug exception,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" elif (((per.q(spr:0x34520))&0xFC000000)==(0xD0000000||0xD4000000)) group.quad spr:0x34520++0x00 line.quad 0x00 "ESR_EL2,Exception Syndrome Register (EL2)" bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,MCR/VMRS to CP10/AArch32,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,HVC in AArch32,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Vector Catch,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline bitfld.quad 0x00 8. "CM,Data came from a Cache Maintenance Instruction other than DC ZVA" "No,Yes" bitfld.quad 0x00 6. "WNR,Write not Read" "Read,Write" newline bitfld.quad 0x00 0.--5. "IFSC,Instruction Fault Status Code" "0,1,2,3,?..." elif (((per.q(spr:0x34520))&0xFC000000)==(0xE0000000||0xF0000000)) group.quad spr:0x34520++0x00 line.quad 0x00 "ESR_EL2,Exception Syndrome Register (EL2)" bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,MCR/VMRS to CP10/AArch32,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,HVC in AArch32,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Vector Catch,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline hexmask.quad.word 0x00 0.--15. 1. "COMMENT,Set to the instruction comment field value" else group.quad spr:0x34520++0x00 line.quad 0x00 "ESR_EL2,Exception Syndrome Register (EL2)" bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,MCR/VMRS to CP10/AArch32,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,HVC in AArch32,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Vector Catch,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" endif if (((per.q(spr:0x36520))&0xFC000000)==(0x00000000||0x38000000||0x88000000||0x98000000)) group.quad spr:0x36520++0x00 line.quad 0x00 "ESR_EL3,Exception Syndrome Register (EL3)" bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,Reserved,Reserved,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Implementation defined,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Reserved,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" elif (((per.q(spr:0x36520))&0xFC000000)==0x04000000) if (((per.q(spr:0x36520))&0x1000000)==0x1000000) group.quad spr:0x36520++0x00 line.quad 0x00 "ESR_EL3,Exception Syndrome Register (EL3)" bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,Reserved,Reserved,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Implementation defined,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Reserved,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline bitfld.quad 0x00 24. "CV,Condition code valid" "Not valid,Valid" bitfld.quad 0x00 20.--23. "COND,Condition code for the trapped instruction" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111" newline bitfld.quad 0x00 0. "TI,Trapped instruction" "WFI,WFE" else group.quad spr:0x36520++0x00 line.quad 0x00 "ESR_EL3,Exception Syndrome Register (EL3)" bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,Reserved,Reserved,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Implementation defined,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Reserved,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline bitfld.quad 0x00 24. "CV,Condition code valid" "Not valid,Valid" newline bitfld.quad 0x00 0. "TI,Trapped instruction" "WFI,WFE" endif elif (((per.q(spr:0x36520))&0xFC000000)==(0x0C000000||0x14000000)) if (((per.q(spr:0x36520))&0x1000000)==0x1000000) group.quad spr:0x36520++0x00 line.quad 0x00 "ESR_EL3,Exception Syndrome Register (EL3)" bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,Reserved,Reserved,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Implementation defined,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Reserved,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline bitfld.quad 0x00 24. "CV,Condition code valid" "Not valid,Valid" bitfld.quad 0x00 20.--23. "COND,Condition code for the trapped instruction" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111" newline bitfld.quad 0x00 17.--19. "OPC2,Opc2 value from the issued instruction" "0,1,2,3,4,5,6,7" bitfld.quad 0x00 14.--16. "OPC1,Opc1 value from the issued instruction" "0,1,2,3,4,5,6,7" newline bitfld.quad 0x00 10.--13. "CRN,CRn value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.quad 0x00 5.--9. "RT,Rt value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.quad 0x00 1.--4. "CRM,CRm value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.quad 0x00 0. "DIRECTION,Direction of the trapped instruction" "Write,Read" else group.quad spr:0x36520++0x00 line.quad 0x00 "ESR_EL3,Exception Syndrome Register (EL3)" bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,Reserved,Reserved,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Implementation defined,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Reserved,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline bitfld.quad 0x00 24. "CV,Condition code valid" "Not valid,Valid" newline bitfld.quad 0x00 17.--19. "OPC2,Opc2 value from the issued instruction" "0,1,2,3,4,5,6,7" bitfld.quad 0x00 14.--16. "OPC1,Opc1 value from the issued instruction" "0,1,2,3,4,5,6,7" newline bitfld.quad 0x00 10.--13. "CRN,CRn value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.quad 0x00 5.--9. "RT,Rt value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.quad 0x00 1.--4. "CRM,CRm value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.quad 0x00 0. "DIRECTION,Direction of the trapped instruction" "Write,Read" endif elif (((per.q(spr:0x36520))&0xFC000000)==(0x10000000||0x30000000)) if (((per.q(spr:0x36520))&0x1000000)==0x1000000) group.quad spr:0x36520++0x00 line.quad 0x00 "ESR_EL3,Exception Syndrome Register (EL3)" bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,Reserved,Reserved,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Implementation defined,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Reserved,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline bitfld.quad 0x00 24. "CV,Condition code valid" "Not valid,Valid" bitfld.quad 0x00 20.--23. "COND,Condition code for the trapped instruction" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111" newline bitfld.quad 0x00 16.--19. "OPC1,Opc1 value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.quad 0x00 10.--14. "RT2,Rt2 value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.quad 0x00 5.--9. "RT,Rt value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.quad 0x00 1.--4. "CRM,CRm value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.quad 0x00 0. "DIRECTION,Direction of the trapped instruction" "Write,Read" else group.quad spr:0x36520++0x00 line.quad 0x00 "ESR_EL3,Exception Syndrome Register (EL3)" bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,Reserved,Reserved,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Implementation defined,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Reserved,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline bitfld.quad 0x00 24. "CV,Condition code valid" "Not valid,Valid" newline bitfld.quad 0x00 16.--19. "OPC1,Opc1 value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.quad 0x00 10.--14. "RT2,Rt2 value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.quad 0x00 5.--9. "RT,Rt value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.quad 0x00 1.--4. "CRM,CRm value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.quad 0x00 0. "DIRECTION,Direction of the trapped instruction" "Write,Read" endif elif (((per.q(spr:0x36520))&0xFC000000)==0x18000000) if (((per.q(spr:0x36520))&0x1000000)==0x1000000) group.quad spr:0x36520++0x00 line.quad 0x00 "ESR_EL3,Exception Syndrome Register (EL3)" bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,Reserved,Reserved,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Implementation defined,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Reserved,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline bitfld.quad 0x00 24. "CV,Condition code valid" "Not valid,Valid" bitfld.quad 0x00 20.--23. "COND,Condition code for the trapped instruction" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111" newline hexmask.quad.byte 0x00 12.--19. 1. "IMM8,The immediate value from the issued instruction" bitfld.quad 0x00 5.--9. "RN,Rn value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.quad 0x00 4. "OFFSET,Indicates whether the offset is added or subtracted" "Subtracted,Added" bitfld.quad 0x00 1.--3. "AM,Addressing mode" "Immediate unindexed,Immediate post-indexed,Immediate offset,Immediate pre-indexed,Literal unindexed,Reserved,Literal offset,Reserved" newline bitfld.quad 0x00 0. "DIRECTION,Direction of the trapped instruction" "Write,Read" else group.quad spr:0x36520++0x00 line.quad 0x00 "ESR_EL3,Exception Syndrome Register (EL3)" bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,Reserved,Reserved,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Implementation defined,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Reserved,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline bitfld.quad 0x00 24. "CV,Condition code valid" "Not valid,Valid" newline hexmask.quad.byte 0x00 12.--19. 1. "IMM8,The immediate value from the issued instruction" bitfld.quad 0x00 5.--9. "RN,Rn value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.quad 0x00 4. "OFFSET,Indicates whether the offset is added or subtracted" "Subtracted,Added" bitfld.quad 0x00 1.--3. "AM,Addressing mode" "Immediate unindexed,Immediate post-indexed,Immediate offset,Immediate pre-indexed,Literal unindexed,Reserved,Literal offset,Reserved" newline bitfld.quad 0x00 0. "DIRECTION,Direction of the trapped instruction" "Write,Read" endif elif (((per.q(spr:0x36520))&0xFC000000)==0x1C000000) if (((per.q(spr:0x36520))&0x1000000)==0x1000000) group.quad spr:0x36520++0x00 line.quad 0x00 "ESR_EL3,Exception Syndrome Register (EL3)" bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,Reserved,Reserved,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Implementation defined,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Reserved,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline bitfld.quad 0x00 24. "CV,Condition code valid" "Not valid,Valid" bitfld.quad 0x00 20.--23. "COND,Condition code for the trapped instruction" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111" else group.quad spr:0x36520++0x00 line.quad 0x00 "ESR_EL3,Exception Syndrome Register (EL3)" bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,Reserved,Reserved,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Implementation defined,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Reserved,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline bitfld.quad 0x00 24. "CV,Condition code valid" "Not valid,Valid" endif elif (((per.q(spr:0x36520))&0xFC000000)==0x4C000000) if ((((per.q(spr:0x36520))&0x1000000)==0x1000000)&&(((per.q(spr:0x36520))&0xF0000)==0x80000)) group.quad spr:0x36520++0x00 line.quad 0x00 "ESR_EL3,Exception Syndrome Register (EL3)" bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,MCR/VMRS to CP10/AArch32,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,HVC in AArch32,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Vector Catch,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline bitfld.quad 0x00 24. "CV,Condition code valid" "Not valid,Valid" bitfld.quad 0x00 20.--23. "COND,Condition code for the trapped instruction" "0b0000,0b0001,0b0010,0b0011,0b0100,0b0101,0b0110,0b0111,0b1000,0b1001,0b1010,0b1011,0b1100,0b1101,0b1110,0b1111" newline bitfld.quad 0x00 19. "CCKNOWNPASS,Indicates whether the instruction might have failed its condition code check" "Unconditional,Conditional" elif (((per.q(spr:0x36520))&0xF0000)==0x80000) group.quad spr:0x36520++0x00 line.quad 0x00 "ESR_EL3,Exception Syndrome Register (EL3)" bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,MCR/VMRS to CP10/AArch32,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,HVC in AArch32,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Vector Catch,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline bitfld.quad 0x00 24. "CV,Condition code valid" "Not valid,Valid" newline bitfld.quad 0x00 19. "CCKNOWNPASS,Indicates whether the instruction might have failed its condition code check" "Unconditional,Conditional" else group.quad spr:0x36520++0x00 line.quad 0x00 "ESR_EL3,Exception Syndrome Register (EL3)" bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,MCR/VMRS to CP10/AArch32,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,HVC in AArch32,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Vector Catch,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline newline bitfld.quad 0x00 19. "CCKNOWNPASS,Indicates whether the instruction might have failed its condition code check" "Unconditional,Conditional" endif elif (((per.q(spr:0x36520))&0xFC000000)==(0x54000000||0x58000000)) group.quad spr:0x36520++0x00 line.quad 0x00 "ESR_EL3,Exception Syndrome Register (EL3)" bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,Reserved,Reserved,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Implementation defined,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Reserved,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline hexmask.quad.word 0x00 0.--15. 1. "IMM16,The value of the immediate field from the HVC or SVC instruction" elif (((per.q(spr:0x36520))&0xFC000000)==0x5C000000) group.quad spr:0x36520++0x00 line.quad 0x00 "ESR_EL3,Exception Syndrome Register (EL3)" bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,Reserved,Reserved,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Implementation defined,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Reserved,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline hexmask.quad.word 0x00 0.--15. 1. "IMM16,The value of the immediate field from the issued SMC instruction" elif (((per.q(spr:0x36520))&0xFC000000)==0x60000000) group.quad spr:0x36520++0x00 line.quad 0x00 "ESR_EL3,Exception Syndrome Register (EL3)" bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,Reserved,Reserved,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Implementation defined,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Reserved,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline bitfld.quad 0x00 20.--21. "OP0,Op0 value from the issued instruction" "0,1,2,3" bitfld.quad 0x00 17.--19. "OP2,Opc2 value from the issued instruction" "0,1,2,3,4,5,6,7" newline bitfld.quad 0x00 14.--16. "OP1,Opc1 value from the issued instruction" "0,1,2,3,4,5,6,7" bitfld.quad 0x00 10.--13. "CRN,CRn value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.quad 0x00 5.--9. "RT,Rt value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.quad 0x00 1.--4. "CRM,CRm value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.quad 0x00 0. "DIRECTION,Direction of the trapped instruction" "Write,Read" elif (((per.q(spr:0x36520))&0xFC000000)==0x7C000000) group.quad spr:0x36520++0x00 line.quad 0x00 "ESR_EL3,Exception Syndrome Register (EL3)" bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,Reserved,Reserved,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Implementation defined,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Reserved,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline hexmask.quad.long 0x00 0.--24. 1. "IMPL_DEF,Implementation defined" elif (((per.q(spr:0x36520))&0xFC000000)==(0x80000000||0x84000000)) if (((per.q(spr:0x36520))&0x3F)==(0x10)) group.quad spr:0x36520++0x00 line.quad 0x00 "ESR_EL3,Exception Syndrome Register (EL3)" bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,Reserved,Reserved,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Implementation defined,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Reserved,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline bitfld.quad 0x00 11.--12. "SET,Synchronous Error Type" "UER,UEO,UC,CE" newline bitfld.quad 0x00 10. "FNV,FAR not Valid" "No,Yes" bitfld.quad 0x00 9. "EA,External abort type" "Not external,External" newline bitfld.quad 0x00 7. "S1PTW,Fault on the stage 2 translation of an address accessed during a stage 1 translation table walk" "Not stage 2,Stage 2" bitfld.quad 0x00 0.--5. "IFSC,Instruction Fault Status Code" "Address size/L0/base register,Address size/L1,Address size/L2,Address size/L3,Translation/L0,Translation/L1,Translation/L2,Translation/L3,Reserved,Access flag/L1,Access flag/L2,Access flag/L3,Reserved,Permission/L1,Permission/L2,Permission/L3,Sync. external abort/not table walk,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Sync. parity/ECC/not table walk,Reserved,Reserved,Reserved,Sync. external abort/L0,Sync. external abort/L1,Sync. external abort/L2,Sync. external abort/L3,Sync. parity/ECC/L0,Sync. parity/ECC/L1,Sync. parity/ECC/L2,Sync. parity/ECC/L3,Alignment,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,TLB conflict,?..." else group.quad spr:0x36520++0x00 line.quad 0x00 "ESR_EL3,Exception Syndrome Register (EL3)" bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,Reserved,Reserved,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Implementation defined,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Reserved,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline newline bitfld.quad 0x00 9. "EA,External abort type" "Not external,External" newline bitfld.quad 0x00 7. "S1PTW,Fault on the stage 2 translation of an address accessed during a stage 1 translation table walk" "Not stage 2,Stage 2" bitfld.quad 0x00 0.--5. "IFSC,Instruction Fault Status Code" "Address size/L0/base register,Address size/L1,Address size/L2,Address size/L3,Translation/L0,Translation/L1,Translation/L2,Translation/L3,Reserved,Access flag/L1,Access flag/L2,Access flag/L3,Reserved,Permission/L1,Permission/L2,Permission/L3,Sync. external abort/not table walk,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Sync. parity/ECC/not table walk,Reserved,Reserved,Reserved,Sync. external abort/L0,Sync. external abort/L1,Sync. external abort/L2,Sync. external abort/L3,Sync. parity/ECC/L0,Sync. parity/ECC/L1,Sync. parity/ECC/L2,Sync. parity/ECC/L3,Alignment,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,TLB conflict,?..." endif elif (((per.q(spr:0x36520))&0xFD000000)==(0x91000000||0x95000000)) if (((per.q(spr:0x36520))&0x3F)==(0x10)) group.quad spr:0x36520++0x00 line.quad 0x00 "ESR_EL3,Exception Syndrome Register (EL3)" bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,Reserved,Reserved,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Implementation defined,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Reserved,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline bitfld.quad 0x00 24. "ISV,Instruction syndrome valid" "Not valid,Valid" bitfld.quad 0x00 22.--23. "SAS,Syndrome Access Size" "Byte,Halfword,Word,Doubleword" newline bitfld.quad 0x00 21. "SSE,Syndrome Sign Extend" "Not required,Required" bitfld.quad 0x00 16.--20. "SRT,Syndrome Register transfer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.quad 0x00 15. "SF,Width of the register accessed by the instruction is Sixty-Four" "32-bit,64-bit" bitfld.quad 0x00 14. "AR,Acquire/Release" "No,Yes" newline bitfld.quad 0x00 11.--12. "SET,Synchronous Error Type" "UER,UEO,UC,CE" newline bitfld.quad 0x00 10. "FNV,FAR not Valid" "No,Yes" bitfld.quad 0x00 9. "EA,External abort type" "Not external,External" newline bitfld.quad 0x00 8. "CM,Fault came from a Cache Maintenance Instruction other than DC ZVA" "No,Yes" bitfld.quad 0x00 7. "S1PTW,Fault on the stage 2 translation of an address accessed during a stage 1 translation table walk" "Not stage 2,Stage 2" newline bitfld.quad 0x00 6. "WNR,Write not Read" "Read,Write" bitfld.quad 0x00 0.--5. "DFSC,Data Fault Status Code" "Address size/L0/TTBR,Address size/L1,Address size/L2,Address size/L3,Translation/L0,Translation/L1,Translation/L2,Translation/L3,Reserved,Access flag/L1,Access flag/L2,Access flag/L3,Reserved,Permission/L1,Permission/L2,Permission/L3,Sync. external abort/not table walk,Reserved,Reserved,Reserved,Sync. external abort/L0,Sync. external abort/L1,Sync. external abort/L2,Sync. external abort/L3,Sync. parity/ECC/not table walk,Reserved,Reserved,Reserved,Sync. parity/ECC/L0,Sync. parity/ECC/L1,Sync. parity/ECC/L2,Sync. parity/ECC/L3,Reserved,Alignment,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,TLB conflict,Reserved,Reserved,Reserved,Lockdown,Unsupported Exclusive/Atomic access,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Section Domain,Page Domain,Reserved" else group.quad spr:0x36520++0x00 line.quad 0x00 "ESR_EL3,Exception Syndrome Register (EL3)" bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,Reserved,Reserved,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Implementation defined,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Reserved,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline bitfld.quad 0x00 24. "ISV,Instruction syndrome valid" "Not valid,Valid" bitfld.quad 0x00 22.--23. "SAS,Syndrome Access Size" "Byte,Halfword,Word,Doubleword" newline bitfld.quad 0x00 21. "SSE,Syndrome Sign Extend" "Not required,Required" bitfld.quad 0x00 16.--20. "SRT,Syndrome Register transfer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline bitfld.quad 0x00 15. "SF,Width of the register accessed by the instruction is Sixty-Four" "32-bit,64-bit" bitfld.quad 0x00 14. "AR,Acquire/Release" "No,Yes" newline newline bitfld.quad 0x00 9. "EA,External abort type" "Not external,External" newline bitfld.quad 0x00 8. "CM,Fault came from a Cache Maintenance Instruction other than DC ZVA" "No,Yes" bitfld.quad 0x00 7. "S1PTW,Fault on the stage 2 translation of an address accessed during a stage 1 translation table walk" "Not stage 2,Stage 2" newline bitfld.quad 0x00 6. "WNR,Write not Read" "Read,Write" bitfld.quad 0x00 0.--5. "DFSC,Data Fault Status Code" "Address size/L0/TTBR,Address size/L1,Address size/L2,Address size/L3,Translation/L0,Translation/L1,Translation/L2,Translation/L3,Reserved,Access flag/L1,Access flag/L2,Access flag/L3,Reserved,Permission/L1,Permission/L2,Permission/L3,Sync. external abort/not table walk,Reserved,Reserved,Reserved,Sync. external abort/L0,Sync. external abort/L1,Sync. external abort/L2,Sync. external abort/L3,Sync. parity/ECC/not table walk,Reserved,Reserved,Reserved,Sync. parity/ECC/L0,Sync. parity/ECC/L1,Sync. parity/ECC/L2,Sync. parity/ECC/L3,Reserved,Alignment,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,TLB conflict,Reserved,Reserved,Reserved,Lockdown,Unsupported Exclusive/Atomic access,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Section Domain,Page Domain,Reserved" endif elif (((per.q(spr:0x36520))&0xFD000000)==(0x90000000||0x94000000)) if (((per.q(spr:0x36520))&0x3F)==(0x10)) group.quad spr:0x36520++0x00 line.quad 0x00 "ESR_EL3,Exception Syndrome Register (EL3)" bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,Reserved,Reserved,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Implementation defined,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Reserved,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline bitfld.quad 0x00 24. "ISV,Instruction syndrome valid" "Not valid,Valid" newline newline newline bitfld.quad 0x00 11.--12. "SET,Synchronous Error Type" "UER,UEO,UC,CE" newline bitfld.quad 0x00 10. "FNV,FAR not Valid" "No,Yes" bitfld.quad 0x00 9. "EA,External abort type" "Not external,External" newline bitfld.quad 0x00 8. "CM,Fault came from a Cache Maintenance Instruction other than DC ZVA" "No,Yes" bitfld.quad 0x00 7. "S1PTW,Fault on the stage 2 translation of an address accessed during a stage 1 translation table walk" "Not stage 2,Stage 2" newline bitfld.quad 0x00 6. "WNR,Write not Read" "Read,Write" bitfld.quad 0x00 0.--5. "DFSC,Data Fault Status Code" "Address size/L0/TTBR,Address size/L1,Address size/L2,Address size/L3,Translation/L0,Translation/L1,Translation/L2,Translation/L3,Reserved,Access flag/L1,Access flag/L2,Access flag/L3,Reserved,Permission/L1,Permission/L2,Permission/L3,Sync. external abort/not table walk,Reserved,Reserved,Reserved,Sync. external abort/L0,Sync. external abort/L1,Sync. external abort/L2,Sync. external abort/L3,Sync. parity/ECC/not table walk,Reserved,Reserved,Reserved,Sync. parity/ECC/L0,Sync. parity/ECC/L1,Sync. parity/ECC/L2,Sync. parity/ECC/L3,Reserved,Alignment,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,TLB conflict,Reserved,Reserved,Reserved,Lockdown,Unsupported Exclusive/Atomic access,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Section Domain,Page Domain,Reserved" else group.quad spr:0x36520++0x00 line.quad 0x00 "ESR_EL3,Exception Syndrome Register (EL3)" bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,Reserved,Reserved,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Implementation defined,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Reserved,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline bitfld.quad 0x00 24. "ISV,Instruction syndrome valid" "Not valid,Valid" newline newline newline newline bitfld.quad 0x00 9. "EA,External abort type" "Not external,External" newline bitfld.quad 0x00 8. "CM,Fault came from a Cache Maintenance Instruction other than DC ZVA" "No,Yes" bitfld.quad 0x00 7. "S1PTW,Fault on the stage 2 translation of an address accessed during a stage 1 translation table walk" "Not stage 2,Stage 2" newline bitfld.quad 0x00 6. "WNR,Write not Read" "Read,Write" bitfld.quad 0x00 0.--5. "DFSC,Data Fault Status Code" "Address size/L0/TTBR,Address size/L1,Address size/L2,Address size/L3,Translation/L0,Translation/L1,Translation/L2,Translation/L3,Reserved,Access flag/L1,Access flag/L2,Access flag/L3,Reserved,Permission/L1,Permission/L2,Permission/L3,Sync. external abort/not table walk,Reserved,Reserved,Reserved,Sync. external abort/L0,Sync. external abort/L1,Sync. external abort/L2,Sync. external abort/L3,Sync. parity/ECC/not table walk,Reserved,Reserved,Reserved,Sync. parity/ECC/L0,Sync. parity/ECC/L1,Sync. parity/ECC/L2,Sync. parity/ECC/L3,Reserved,Alignment,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,TLB conflict,Reserved,Reserved,Reserved,Lockdown,Unsupported Exclusive/Atomic access,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Section Domain,Page Domain,Reserved" endif elif (((per.q(spr:0x36520))&0xFC800000)==0xB0800000) group.quad spr:0x36520++0x00 line.quad 0x00 "ESR_EL3,Exception Syndrome Register (EL3)" bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,Reserved,Reserved,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Implementation defined,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Reserved,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline bitfld.quad 0x00 23. "TFV,Trapped Fault Valid" "Not valid,Valid" bitfld.quad 0x00 8.--10. "VECITR,Number of the element that is being reported" "0,1,2,3,4,5,6,7" newline bitfld.quad 0x00 7. "IDF,Input Denormal floating-point exception trapped" "Not occurred,Occurred" bitfld.quad 0x00 4. "IXF,Inexact floating-point exception trapped" "Not occurred,Occurred" newline bitfld.quad 0x00 3. "UFF,Underflow floating-point exception trapped" "Not occurred,Occurred" bitfld.quad 0x00 2. "OFF,Overflow floating-point exception trapped" "Not occurred,Occurred" newline bitfld.quad 0x00 1. "DZF,Divide-by-zero floating-point exception trapped" "Not occurred,Occurred" bitfld.quad 0x00 0. "IOF,Invalid Operation floating-point exception trapped" "Not occurred,Occurred" elif (((per.q(spr:0x36520))&0xFC800000)==0xB0000000) group.quad spr:0x36520++0x00 line.quad 0x00 "ESR_EL3,Exception Syndrome Register (EL3)" bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,Reserved,Reserved,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Implementation defined,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Reserved,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline bitfld.quad 0x00 23. "TFV,Trapped Fault Valid" "Not valid,Valid" bitfld.quad 0x00 8.--10. "VECITR,Number of the element that is being reported" "0,1,2,3,4,5,6,7" elif (((per.q(spr:0x36520))&0xFD000000)==0xBD000000) if (((per.q(spr:0x36520))&0x3F)==0x11) group.quad spr:0x36520++0x00 line.quad 0x00 "ESR_EL3,Exception Syndrome Register (EL3)" bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline bitfld.quad 0x00 24. "IDS,Implementation defined syndrome" "Not hold,Hold" bitfld.quad 0x00 13. "IESB,Implicit Error Synchronization Barrier" "Not synchronized,Synchronized" newline bitfld.quad 0x00 10.--12. "AET,Asynchronous Error Type" "UC,UEU,UEO,UER,CE,?..." newline bitfld.quad 0x00 9. "EA,External abort type" "No,Yes" bitfld.quad 0x00 0.--5. "DFSC,Data Fault Status Code" "Uncategorized,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Asynchronous,?..." else group.quad spr:0x36520++0x00 line.quad 0x00 "ESR_EL3,Exception Syndrome Register (EL3)" bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline bitfld.quad 0x00 24. "IDS,Implementation defined syndrome" "Not hold,Hold" newline newline bitfld.quad 0x00 9. "EA,External abort type" "No,Yes" bitfld.quad 0x00 0.--5. "DFSC,Data Fault Status Code" "Uncategorized,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Asynchronous,?..." endif elif (((per.q(spr:0x36520))&0xFD000000)==0xBC000000) group.quad spr:0x36520++0x00 line.quad 0x00 "ESR_EL3,Exception Syndrome Register (EL3)" bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,SVC in AArch32,Reserved,Reserved,Reserved,SVC in AArch64,Reserved,Reserved,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Trapped Floating-point/AArch32,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Breakpoint/lower level,Breakpoint/current level,Software Step/lower level,Software Step/current level,Watchpoint debug/lower level,Watchpoint debug/current level,Reserved,Reserved,Software Breakpoint/AArch32,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline bitfld.quad 0x00 24. "IDS,Implementation defined syndrome" "Not hold,Hold" elif (((per.q(spr:0x36520))&0xFC000000)==0xF0000000) group.quad spr:0x36520++0x00 line.quad 0x00 "ESR_EL3,Exception Syndrome Register (EL3)" bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,Reserved,Reserved,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Implementation defined,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Reserved,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" bitfld.quad 0x00 25. "IL,Instruction Length for synchronous exceptions" "16-bit,32-bit" newline hexmask.quad.word 0x00 0.--15. 1. "COMMENT,Set to the instruction comment field value" else group.quad spr:0x36520++0x00 line.quad 0x00 "ESR_EL3,Exception Syndrome Register (EL3)" bitfld.quad 0x00 26.--31. "EC,Exception class" "Unknown reason,WFI/WFE instruction,Reserved,MCR/MRC to CP15/AArch32,MCRR/MRRC to CP15/AArch32,MCR/MRC to CP14/AArch32,LDC/STC to CP14/AArch32,SIMD/Floating point register,Reserved,Reserved,Reserved,Reserved,MCRR/MRRC to CP14/AArch32,Reserved,Illegal execution,Reserved,Reserved,Reserved,Reserved,SMC in AArch32,Reserved,SVC in AArch64,HVC in AArch64,SMC in AArch64,MSR/MRS/System in AArch64,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Implementation defined,Instruction abort,Instruction abort/AArch64,PC alignment fault,Reserved,Data abort,Data abort/Aarch64,SP alignment fault,Reserved,Reserved,Reserved,Reserved,Reserved,Trapped Floating-point/AArch64,Reserved,Reserved,SError interrupt,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Software Breakpoint/AArch64,Reserved,Reserved,Reserved" endif tree.end newline if (CORENAME()=="CORTEXA75") group.quad spr:0x30C11++0x00 line.quad 0x00 "DISR_EL1,Deferred Interrupt Status Register" bitfld.quad 0x00 31. "A,Asynchronous SError interrupt deferred" "No,Yes" bitfld.quad 0x00 24. "IDS,Indicates the type of format the deferred SError interrupt uses" "Architecturally-defined," newline bitfld.quad 0x00 10.--12. "AET,Asynchronous Error Type" "UC/Uncontainable,?..." bitfld.quad 0x00 0.--5. "DFSC,Fault status code" "Uncategorized,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Async. SError,?..." elif (CORENAME()=="CORTEXA55") if (((per.q(spr:0x30C11))&0x1000000)==0x00)&&(((per.q(spr:0x30C11))&0x3F)==0x11) group.quad spr:0x30C11++0x00 line.quad 0x00 "DISR_EL1,Deferred Interrupt Status Register" bitfld.quad 0x00 31. "A,Asynchronous SError interrupt deferred" "No,Yes" bitfld.quad 0x00 24. "IDS,Indicates the type of format the deferred SError interrupt uses" "Architecturally-defined," newline bitfld.quad 0x00 10.--12. "AET,Asynchronous Error Type" "Reserved,UEU/Unrecoverable,?..." bitfld.quad 0x00 0.--5. "DFSC,Fault Status Code" "Uncategorized,Reserved,Reserved,Reserved,Reserved,Reserved,Async. SError/AArch32,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Async. SError/AArch64,?..." else group.quad spr:0x30C11++0x00 line.quad 0x00 "DISR_EL1,Deferred Interrupt Status Register" bitfld.quad 0x00 31. "A,Asynchronous SError interrupt deferred" "No,Yes" bitfld.quad 0x00 24. "IDS,Indicates the type of format the deferred SError interrupt uses" "Architecturally-defined," newline bitfld.quad 0x00 0.--5. "DFSC,Fault Status Code" "Uncategorized,Reserved,Reserved,Reserved,Reserved,Reserved,Async. SError/AArch32,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Async. SError/AArch64,?..." endif endif if (CORENAME()=="CORTEXA75") group.quad spr:0x34523++0x00 line.quad 0x00 "VSESR_EL2,Virtual SError Exception Syndrome Register - EL1 using AArch32" bitfld.quad 0x00 14.--15. "AET,Asynchronous Error Type" "UC/Uncontainable,?..." bitfld.quad 0x00 12. "EXT,External Abort Type" "0,1" group.quad spr:0x34523++0x00 line.quad 0x00 "VSESR_EL2,Virtual SError Exception Syndrome Register - EL1 using AArch64" bitfld.quad 0x00 24. "IDS,Indicates the type of format the deferred SError interrupt uses" "Architecturally-defined,Implementation-defined" hexmask.quad.tbyte 0x00 0.--23. 1. "ISS,Syndrome information" if (((per.q(spr:0x34C11))&0x200)==0x00) group.quad spr:0x34C11++0x00 line.quad 0x00 "VDISR_EL2,Virtual Deferred Interrupt Status Register - EL1 using the AArch32 Short-descriptor" bitfld.quad 0x00 31. "A,Indicates when ESB defers a virtual SError interrupt" "Not deferred,Deferred" bitfld.quad 0x00 14.--15. "AET,Asynchronous Error Type" "UC/Uncontainable,?..." newline bitfld.quad 0x00 9. "LPAE,Translation table format" "Short,Long" bitfld.quad 0x00 0.--3. 10. "FS,Fault status code" ",,,,,,,,,,,,,,,,,,,,,,Asynchronous SError interrupt,?..." else group.quad spr:0x34C11++0x00 line.quad 0x00 "VDISR_EL2,Virtual Deferred Interrupt Status Register - EL1 using the AArch32 Long-descriptor" bitfld.quad 0x00 31. "A,Indicates when ESB defers a virtual SError interrupt" "Not deferred,Deferred" bitfld.quad 0x00 14.--15. "AET,Asynchronous Error Type" "UC/Uncontainable,?..." newline bitfld.quad 0x00 9. "LPAE,Translation table format" "Short,Long" bitfld.quad 0x00 0.--5. "STATUS,Fault status code" ",,,,,,,,,,,,,,,,,Asynchronous SError interrupt,?..." endif group.quad spr:0x34C11++0x00 line.quad 0x00 "VDISR_EL2,Virtual Deferred Interrupt Status Register - EL1 using the AArch64" bitfld.quad 0x00 31. "A,Indicates when ESB defers a virtual SError interrupt" "Not deferred,Deferred" bitfld.quad 0x00 24. "IDS,Indicates the type of format the deferred SError interrupt uses" "Architecturally-defined,Implementation-defined" newline hexmask.quad.tbyte 0x00 0.--23. 1. "ISS,Syndrome information" elif (CORENAME()=="CORTEXA55") group.quad spr:0x34523++0x00 line.quad 0x00 "VSESR_EL2,Virtual SError Exception Syndrome Register - EL1 using AArch32" bitfld.quad 0x00 14.--15. "AET,Asynchronous Error Type" "Reserved,UEU/Unrecoverable,?..." group.quad spr:0x34523++0x00 line.quad 0x00 "VSESR_EL2,Virtual SError Exception Syndrome Register - EL1 using AArch64" bitfld.quad 0x00 24. "IDS,Indicates the type of format the deferred SError interrupt uses" "Architecturally-defined,Implementation-defined" hexmask.quad.tbyte 0x00 0.--23. 1. "ISS,Syndrome information" if (((per.q(spr:0x34C11))&0x200)==0x00) group.quad spr:0x34C11++0x00 line.quad 0x00 "VDISR_EL2,Virtual Deferred Interrupt Status Register - EL1 using the AArch32 Short-descriptor" bitfld.quad 0x00 31. "A,Indicates when ESB defers a virtual SError interrupt" "Not deferred,Deferred" bitfld.quad 0x00 14.--15. "AET,Asynchronous Error Type" "Reserved,UEU/Unrecoverable,?..." newline bitfld.quad 0x00 9. "LPAE,Translation table format" "Short,Long" bitfld.quad 0x00 0.--3. 10. "FS,Fault status code" ",,,,,,,,,,,,,,,,,,,,,,Asynchronous SError interrupt,?..." else group.quad spr:0x34C11++0x00 line.quad 0x00 "VDISR_EL2,Virtual Deferred Interrupt Status Register - EL1 using the AArch32 Long-descriptor" bitfld.quad 0x00 31. "A,Indicates when ESB defers a virtual SError interrupt" "Not deferred,Deferred" bitfld.quad 0x00 14.--15. "AET,Asynchronous Error Type" "Reserved,UEU/Unrecoverable,?..." newline bitfld.quad 0x00 9. "LPAE,Translation table format" "Short,Long" bitfld.quad 0x00 0.--5. "STATUS,Fault status code" ",,,,,,,,,,,,,,,,,Asynchronous SError interrupt,?..." endif group.quad spr:0x34C11++0x00 line.quad 0x00 "VDISR_EL2,Virtual Deferred Interrupt Status Register - EL1 using the AArch64" bitfld.quad 0x00 31. "A,Indicates when ESB defers a virtual SError interrupt" "Not deferred,Deferred" bitfld.quad 0x00 24. "IDS,Indicates the type of format the deferred SError interrupt uses" "Architecturally-defined,Implementation-defined" newline hexmask.quad.tbyte 0x00 0.--23. 1. "ISS,Syndrome information" endif if (((per.q(c15:0x0202))&0x80000000)==0x00000000) group.quad spr:0x34501++0x00 line.quad 0x00 "IFSR32_EL2,Instruction Fault Status Register" bitfld.quad 0x00 16. "FNV,FAR not Valid" "Valid,Not valid" bitfld.quad 0x00 12. "EXT,External abort type" "0,1" newline bitfld.quad 0x00 9. "LPAE,Descriptor translation table format" "Short,Long" bitfld.quad 0x00 0.--3. 10. "FS,Fault Status" "Reserved,Reserved,Debug event,Access flag/section,Reserved,Translation/section,Access flag/page,Translation/page,Sync. external/non-translation,Domain/section,Reserved,Domain/page,Sync. external/on TTW/L1,Permission/section,Sync. external/on TTW/L2,Permission/page,TLB conflict,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Sync. parity/on memory access,Reserved,Reserved,Sync. parity/on TTW/L1,Reserved,Sync. parity/on TTW/L2,?..." else group.quad spr:0x34501++0x00 line.quad 0x00 "IFSR32_EL2,Instruction Fault Status Register" bitfld.quad 0x00 16. "FNV,FAR not Valid" "Valid,Not valid" bitfld.quad 0x00 12. "EXT,External abort type" "0,1" newline bitfld.quad 0x00 9. "LPAE,Descriptor translation table format" "Short,Long" bitfld.quad 0x00 0.--5. "STATUS,Fault Status" "Reserved,Reserved,Reserved,Reserved,Reserved,Translation/L1,Translation/L2,Translation/L3,Reserved,Access flag/L1,Access flag/L2,Access flag/L3,Reserved,Permission/L1,Permission/L2,Permission/L3,Sync. external,Reserved,Reserved,Reserved,Reserved,Sync. external/on TTW/L1,Sync. external/on TTW/L2,Sync. external/on TTW/L3,Sync. parity/on memory access,Reserved,Reserved,Reserved,Reserved,Sync. parity/on memory access/on TTW/L1,Sync. parity/on memory access/on TTW/L2,Sync. parity/on memory access/on TTW/L3,Reserved,Alignment,Debug event,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,TLB conflict,?..." endif group.quad spr:0x30600++0x00 line.quad 0x00 "FAR_EL1,Fault Address Register" group.quad spr:0x35600++0x00 line.quad 0x00 "FAR_EL12,Fault Address Register" group.quad spr:0x34600++0x00 line.quad 0x00 "FAR_EL2,Fault Address Register" group.quad spr:0x36600++0x00 line.quad 0x00 "FAR_EL3,Fault Address Register" group.quad spr:0x34604++0x00 line.quad 0x00 "HPFAR_EL2,Hypervisor IPA Fault Address Register" hexmask.quad 0x00 4.--43. 0x10 "FIPA[51:12],Bits [51:12] of the faulting intermediate physical address" group.quad spr:0x31F30++0x00 line.quad 0x00 "CBAR_EL1,Configuration Base Address Register EL1" hexmask.quad.long 0x00 18.--43. 0x4 "PERIPHBASE,Holds the physical base address of the memory-mapped GIC CPU interface registers" group.quad spr:0x30C00++0x00 line.quad 0x00 "VBAR_EL1,Vector Base Address Register" hexmask.quad 0x00 11.--63. 0x8 "VBA,Vector Base Address" group.quad spr:0x35C00++0x00 line.quad 0x00 "VBAR_EL12,Vector Base Address Register" hexmask.quad 0x00 11.--63. 0x8 "VBA,Vector Base Address" group.quad spr:0x34C00++0x00 line.quad 0x00 "VBAR_EL2,Vector Base Address Register" hexmask.quad 0x00 11.--63. 0x8 "VBA,Vector Base Address" group.quad spr:0x36C00++0x00 line.quad 0x00 "VBAR_EL3,Vector Base Address Register" hexmask.quad 0x00 11.--63. 0x8 "VBA,Vector Base Address" if (CORENAME()=="CORTEXA75") rgroup.quad spr:0x36C01++0x00 line.quad 0x00 "RVBAR_EL3,Reset Vector Base Address Register" elif (CORENAME()=="CORTEXA55") rgroup.quad spr:0x36C01++0x00 line.quad 0x00 "RVBAR_EL3,Reset Vector Base Address Register" hexmask.quad 0x00 0.--39. 0x1 "RVBA,Reset Vector Base Address" endif group.quad spr:0x30C02++0x00 line.quad 0x00 "RMR_EL1,Reset Management Register" bitfld.quad 0x00 1. "RR,Reset Request" "Not requested,Requested" bitfld.quad 0x00 0. "AA64,Determines which execution state the processor boots into after a warm reset" "AArch32,AArch64" group.quad spr:0x36C02++0x00 line.quad 0x00 "RMR_EL3,Reset Management Register" bitfld.quad 0x00 1. "RR,Reset Request" "Not requested,Requested" bitfld.quad 0x00 0. "AA64,Determines which execution state the processor boots into after a warm reset" "AArch32,AArch64" rgroup.quad spr:0x30C10++0x00 line.quad 0x00 "ISR_EL1,Interrupt Status Register" bitfld.quad 0x00 8. "A,SError interrupt pending bit" "Not pending,Pending" bitfld.quad 0x00 7. "I,IRQ pending bit" "Not pending,Pending" newline bitfld.quad 0x00 6. "F,FIQ pending bit" "Not pending,Pending" group.quad spr:0x30D01++0x00 line.quad 0x00 "CONTEXTIDR_EL1,Context ID Register" group.quad spr:0x35D01++0x00 line.quad 0x00 "CONTEXTIDR_EL12,Context ID Register" group.quad spr:0x34D01++0x00 line.quad 0x00 "CONTEXTIDR_EL2,Context ID Register" group.quad spr:0x33D02++0x00 line.quad 0x00 "TPIDR_EL0,Software Thread ID registers" group.quad spr:0x33D03++0x00 line.quad 0x00 "TPIDRRO_EL0,Software Thread ID registers" group.quad spr:0x30D04++0x00 line.quad 0x00 "TPIDR_EL1,Software Thread ID registers" group.quad spr:0x34D02++0x00 line.quad 0x00 "TPIDR_EL2,Software Thread ID registers" group.quad spr:0x36D02++0x00 line.quad 0x00 "TPIDR_EL3,Software Thread ID registers" tree "System Instructions" wgroup.quad spr:0x10710++0x00 line.quad 0x00 "IC_IALLUIS,IC_IALLUIS" wgroup.quad spr:0x10750++0x00 line.quad 0x00 "IC_IALLU,IC_IALLU" wgroup.quad spr:0x13751++0x00 line.quad 0x00 "IC_IVAU,IC_IVAU" wgroup.quad spr:0x13741++0x00 line.quad 0x00 "DC_ZVA,DC_ZVA" wgroup.quad spr:0x10761++0x00 line.quad 0x00 "DC_IVAC,DC_IVAC" wgroup.quad spr:0x10762++0x00 line.quad 0x00 "DC_ISW,DC_ISW" wgroup.quad spr:0x137A1++0x00 line.quad 0x00 "DC_CVAC,DC_CVAC" wgroup.quad spr:0x137C1++0x00 line.quad 0x00 "DC_CVAP,DC CVAP" wgroup.quad spr:0x107A2++0x00 line.quad 0x00 "DC_CSW,DC_CSW" wgroup.quad spr:0x137B1++0x00 line.quad 0x00 "DC_CVAU,DC_CVAU" wgroup.quad spr:0x137E1++0x00 line.quad 0x00 "DC_CIVAC,DC_CIVAC" wgroup.quad spr:0x107E2++0x00 line.quad 0x00 "DC_CISW,DC_CISW" wgroup.quad spr:0x10780++0x00 line.quad 0x00 "AT_S1E1R,AT_S1E1R" wgroup.quad spr:0x10781++0x00 line.quad 0x00 "AT_S1E1W,AT_S1E1W" wgroup.quad spr:0x10782++0x00 line.quad 0x00 "AT_S1E0R,AT_S1E0R" wgroup.quad spr:0x10790++0x00 line.quad 0x00 "AT_S1E1RP,AT_S1E1RP" wgroup.quad spr:0x10791++0x00 line.quad 0x00 "AT_S1E1WP,AT_S1E1WP" wgroup.quad spr:0x10783++0x00 line.quad 0x00 "AT_S1E0W,AT_S1E0W" wgroup.quad spr:0x14784++0x00 line.quad 0x00 "AT_S12E1R,AT_S12E1R" wgroup.quad spr:0x14785++0x00 line.quad 0x00 "AT_S12E1W,AT_S12E1W" wgroup.quad spr:0x14786++0x00 line.quad 0x00 "AT_S12E0R,AT_S12E0R" wgroup.quad spr:0x14787++0x00 line.quad 0x00 "AT_S12E0W,AT_S12E0W" wgroup.quad spr:0x14780++0x00 line.quad 0x00 "AT_S1E2R,AT_S1E2R" wgroup.quad spr:0x14781++0x00 line.quad 0x00 "AT_S1E2W,AT_S1E2W" wgroup.quad spr:0x16780++0x00 line.quad 0x00 "AT_S1E3R,AT_S1E3R" wgroup.quad spr:0x16781++0x00 line.quad 0x00 "AT_S1E3W,AT_S1E3W" wgroup.quad spr:0x10870++0x00 line.quad 0x00 "TLBI_VMALLE1,TLBI_VMALLE1" wgroup.quad spr:0x10871++0x00 line.quad 0x00 "TLBI_VAE1,TLBI_VAE1" wgroup.quad spr:0x10872++0x00 line.quad 0x00 "TLBI_ASIDE1,TLBI_ASIDE1" wgroup.quad spr:0x10873++0x00 line.quad 0x00 "TLBI_VAAE1,TLBI_VAAE1" wgroup.quad spr:0x10875++0x00 line.quad 0x00 "TLBI_VALE1,TLBI_VALE1" wgroup.quad spr:0x10877++0x00 line.quad 0x00 "TLBI_VAALE1,TLBI_VAALE1" wgroup.quad spr:0x10830++0x00 line.quad 0x00 "TLBI_VMALLE1IS,TLBI_VMALLE1IS" wgroup.quad spr:0x10831++0x00 line.quad 0x00 "TLBI_VAE1IS,TLBI_VAE1IS" wgroup.quad spr:0x10832++0x00 line.quad 0x00 "TLBI_ASIDE1IS,TLBI_ASIDE1IS" wgroup.quad spr:0x10833++0x00 line.quad 0x00 "TLBI_VAAE1IS,TLBI_VAAE1IS" wgroup.quad spr:0x10835++0x00 line.quad 0x00 "TLBI_VALE1IS,TLBI_VALE1IS" wgroup.quad spr:0x10837++0x00 line.quad 0x00 "TLBI_VAALE1IS,TLBI_VAALE1IS" wgroup.quad spr:0x14801++0x00 line.quad 0x00 "TLBI_IPAS2E1IS,TLBI_IPAS2E1IS" wgroup.quad spr:0x14805++0x00 line.quad 0x00 "TLBI_IPAS2LE1IS,TLBI_IPAS2LE1IS" wgroup.quad spr:0x14841++0x00 line.quad 0x00 "TLBI_IPAS2E1,TLBI_IPAS2E1" wgroup.quad spr:0x14845++0x00 line.quad 0x00 "TLBI_IPAS2LE1,TLBI_IPAS2LE1" wgroup.quad spr:0x14871++0x00 line.quad 0x00 "TLBI_VAE2,TLBI_VAE2" wgroup.quad spr:0x14875++0x00 line.quad 0x00 "TLBI_VALE2,TLBI_VALE2" wgroup.quad spr:0x14876++0x00 line.quad 0x00 "TLBI_VMALLS12E1,TLBI_VMALLS12E1" wgroup.quad spr:0x14831++0x00 line.quad 0x00 "TLBI_VAE2IS,TLBI_VAE2IS" wgroup.quad spr:0x14835++0x00 line.quad 0x00 "TLBI_VALE2IS,TLBI_VALE2IS" wgroup.quad spr:0x14836++0x00 line.quad 0x00 "TLBI_VMALLS12E1IS,TLBI_VMALLS12E1IS" wgroup.quad spr:0x16871++0x00 line.quad 0x00 "TLBI_VAE3,TLBI_VAE3" wgroup.quad spr:0x16875++0x00 line.quad 0x00 "TLBI_VALE3,TLBI_VALE3" wgroup.quad spr:0x16831++0x00 line.quad 0x00 "TLBI_VAE3IS,TLBI_VAE3IS" wgroup.quad spr:0x16835++0x00 line.quad 0x00 "TLBI_VALE3IS,TLBI_VALE3IS" wgroup.quad spr:0x14870++0x00 line.quad 0x00 "TLBI_ALLE2,TLBI_ALLE2" wgroup.quad spr:0x14830++0x00 line.quad 0x00 "TLBI_ALLE2IS,TLBI_ALLE2IS" wgroup.quad spr:0x14874++0x00 line.quad 0x00 "TLBI_ALLE1,TLBI_ALLE1" wgroup.quad spr:0x14834++0x00 line.quad 0x00 "TLBI_ALLE1IS,TLBI_ALLE1IS" wgroup.quad spr:0x16870++0x00 line.quad 0x00 "TLBI_ALLE3,TLBI_ALLE3" wgroup.quad spr:0x16830++0x00 line.quad 0x00 "TLBI_ALLE3IS,TLBI_ALLE3IS" tree.end tree.end tree "Memory Management Unit" tree.open "Hypervisor Configuration System Registers" group.quad spr:0x34113++0x00 line.quad 0x00 "HSTR_EL2,Hypervisor System Trap Register" bitfld.quad 0x00 15. "T15,Trap to Hypervisor mode Non-secure priv 15" "No trap,Trap" bitfld.quad 0x00 13. "T13,Trap to Hypervisor mode Non-secure priv 13" "No trap,Trap" bitfld.quad 0x00 12. "T12,Trap to Hypervisor mode Non-secure priv 12" "No trap,Trap" newline bitfld.quad 0x00 11. "T11,Trap to Hypervisor mode Non-secure priv 11" "No trap,Trap" bitfld.quad 0x00 10. "T10,Trap to Hypervisor mode Non-secure priv 10" "No trap,Trap" bitfld.quad 0x00 9. "T9,Trap to Hypervisor mode Non-secure priv 9" "No trap,Trap" newline bitfld.quad 0x00 8. "T8,Trap to Hypervisor mode Non-secure priv 8" "No trap,Trap" bitfld.quad 0x00 7. "T7,Trap to Hypervisor mode Non-secure priv 7" "No trap,Trap" bitfld.quad 0x00 6. "T6,Trap to Hypervisor mode Non-secure priv 6" "No trap,Trap" newline bitfld.quad 0x00 5. "T5,Trap to Hypervisor mode Non-secure priv 5" "No trap,Trap" bitfld.quad 0x00 3. "T3,Trap to Hypervisor mode Non-secure priv 3" "No trap,Trap" bitfld.quad 0x00 2. "T2,Trap to Hypervisor mode Non-secure priv 2" "No trap,Trap" newline bitfld.quad 0x00 1. "T1,Trap to Hypervisor mode Non-secure priv 1" "No trap,Trap" bitfld.quad 0x00 0. "T0,Trap to Hypervisor mode Non-secure priv 0" "No trap,Trap" group.quad spr:0x34117++0x00 line.quad 0x00 "HACR_EL2,Hypervisor Auxiliary Configuration Register" tree.end if (CORENAME()=="CORTEXA75") group.quad spr:0x30200++0x00 line.quad 0x00 "TTBR0_EL1,Translation Table Base Registers" hexmask.quad.word 0x00 48.--63. 1. "ASID,ASID for the translation table base address" hexmask.quad 0x00 1.--47. 0x2 "BADDR[47:1],Translation table base address" newline bitfld.quad 0x00 0. "CNP,Common not Private" "Not supported,Supported" group.quad spr:0x30201++0x00 line.quad 0x00 "TTBR1_EL1,Translation Table Base Registers" hexmask.quad.word 0x00 48.--63. 1. "ASID,ASID for the translation table base address" hexmask.quad 0x00 1.--47. 0x2 "BADDR[47:1],Translation table base address" newline bitfld.quad 0x00 0. "CNP,Common not Private" "Not supported,Supported" group.quad spr:0x35200++0x00 line.quad 0x00 "TTBR0_EL12,Translation Table Base Registers" hexmask.quad.word 0x00 48.--63. 1. "ASID,ASID for the translation table base address" hexmask.quad 0x00 1.--47. 0x2 "BADDR[47:1],Translation table base address" newline bitfld.quad 0x00 0. "CNP,Common not Private" "Not supported,Supported" group.quad spr:0x35201++0x00 line.quad 0x00 "TTBR1_EL12,Translation Table Base Registers" hexmask.quad.word 0x00 48.--63. 1. "ASID,ASID for the translation table base address" hexmask.quad 0x00 1.--47. 0x2 "BADDR[47:1],Translation table base address" newline bitfld.quad 0x00 0. "CNP,Common not Private" "Not supported,Supported" group.quad spr:0x34200++0x00 line.quad 0x00 "TTBR0_EL2,Translation Table Base Registers" hexmask.quad 0x00 2.--47. 0x4 "BADDR[47:2],Translation table base address" bitfld.quad 0x00 0. "CNP,Common not Private" "Not supported,Supported" group.quad spr:0x34201++0x00 line.quad 0x00 "TTBR1_EL2,Translation Table Base Registers" hexmask.quad.word 0x00 48.--63. 1. "ASID,ASID for the translation table base address" hexmask.quad 0x00 1.--47. 0x2 "BADDR[47:1],Translation table base address" newline bitfld.quad 0x00 0. "CNP,Common not Private" "Not supported,Supported" group.quad spr:0x36200++0x00 line.quad 0x00 "TTBR0_EL3,Translation Table Base Registers" hexmask.quad 0x00 1.--47. 0x2 "BADDR[47:1],Translation table base address" bitfld.quad 0x00 0. "CNP,Common not Private" "Not supported,Supported" group.quad spr:0x34210++0x00 line.quad 0x00 "VTTBR_EL2,Virtualization Translation Table Base Register" hexmask.quad.byte 0x00 48.--55. 1. "VMID,The VMID for the translation table" hexmask.quad 0x00 4.--47. 0x10 "BADDR[47:4],Translation table base address" newline bitfld.quad 0x00 0. "CNP,Common not Private" "Not supported,Supported" elif (CORENAME()=="CORTEXA55") group.quad spr:0x30200++0x00 line.quad 0x00 "TTBR0_EL1,Translation Table Base Registers" hexmask.quad.word 0x00 48.--63. 1. "ASID,ASID for the translation table base address" hexmask.quad 0x00 2.--47. 0x4 "BADDR[47:2],Translation table base address" newline bitfld.quad 0x00 0. "CNP,Common not Private" "Not supported,Supported" group.quad spr:0x30201++0x00 line.quad 0x00 "TTBR1_EL1,Translation Table Base Registers" hexmask.quad.word 0x00 48.--63. 1. "ASID,ASID for the translation table base address" hexmask.quad 0x00 2.--47. 0x4 "BADDR[47:2],Translation table base address" newline bitfld.quad 0x00 0. "CNP,Common not Private" "Not supported,Supported" group.quad spr:0x35200++0x00 line.quad 0x00 "TTBR0_EL12,Translation Table Base Registers" hexmask.quad.word 0x00 48.--63. 1. "ASID,ASID for the translation table base address" hexmask.quad 0x00 2.--47. 0x4 "BADDR[47:2],Translation table base address" newline bitfld.quad 0x00 0. "CNP,Common not Private" "Not supported,Supported" group.quad spr:0x35201++0x00 line.quad 0x00 "TTBR1_EL12,Translation Table Base Registers" hexmask.quad.word 0x00 48.--63. 1. "ASID,ASID for the translation table base address" hexmask.quad 0x00 2.--47. 0x4 "BADDR[47:2],Translation table base address" newline bitfld.quad 0x00 0. "CNP,Common not Private" "Not supported,Supported" group.quad spr:0x34200++0x00 line.quad 0x00 "TTBR0_EL2,Translation Table Base Registers" hexmask.quad.word 0x00 48.--63. 1. "ASID,ASID for the translation table base address" hexmask.quad 0x00 2.--47. 0x4 "BADDR[47:2],Translation table base address" newline bitfld.quad 0x00 0. "CNP,Common not Private" "Not supported,Supported" group.quad spr:0x34201++0x00 line.quad 0x00 "TTBR1_EL2,Translation Table Base Registers" hexmask.quad.word 0x00 48.--63. 1. "ASID,ASID for the translation table base address" hexmask.quad 0x00 2.--47. 0x4 "BADDR[47:2],Translation table base address" newline bitfld.quad 0x00 0. "CNP,Common not Private" "Not supported,Supported" group.quad spr:0x36200++0x00 line.quad 0x00 "TTBR0_EL3,Translation Table Base Registers" hexmask.quad 0x00 2.--47. 0x4 "BADDR[47:2],Translation table base address" bitfld.quad 0x00 0. "CNP,Common not Private" "Not supported,Supported" group.quad spr:0x34210++0x00 line.quad 0x00 "VTTBR_EL2,Virtualization Translation Table Base Register" hexmask.quad.word 0x00 48.--63. 1. "VMID,The VMID for the translation table" hexmask.quad 0x00 2.--47. 0x04 "BADDR[47:1],Translation table base address" newline bitfld.quad 0x00 0. "CNP,Common not Private" "Not supported," endif group.quad spr:0x30202++0x00 line.quad 0x00 "TCR_EL1,Translation Control Registers" bitfld.quad 0x00 50. "HWU162,Hardware use of bit[62] of the stage1 translation table block or level 3 entry for pages pointed to by TTBR1_EL1/EL2" "Not possible,Possible" bitfld.quad 0x00 49. "HWU161,Hardware use of bit[61] of the stage1 translation table block or level 3 entry for pages pointed to by TTBR1_EL1/EL2" "Not possible,Possible" newline bitfld.quad 0x00 48. "HWU160,Hardware use of bit[60] of the stage1 translation table block or level 3 entry for pages pointed to by TTBR1_EL1/EL2" "Not possible,Possible" bitfld.quad 0x00 47. "HWU159,Hardware use of bit[59] of the stage1 translation table block or level 3 entry for pages pointed to by TTBR1_EL1/EL2" "Not possible,Possible" newline bitfld.quad 0x00 46. "HWU062,Hardware use of bit[62] of the stage1 translation table block or level 3 entry for pages pointed to by TTBR0_EL1/EL2" "Not possible,Possible" bitfld.quad 0x00 45. "HWU061,Hardware use of bit[61] of the stage1 translation table block or level 3 entry for pages pointed to by TTBR0_EL1/EL2" "Not possible,Possible" newline bitfld.quad 0x00 44. "HWU060,Hardware use of bit[60] of the stage1 translation table block or level 3 entry for pages pointed to by TTBR0_EL1/EL2" "Not possible,Possible" bitfld.quad 0x00 43. "HWU059,Hardware use of bit[59] of the stage1 translation table block or level 3 entry for pages pointed to by TTBR0_EL1/EL2" "Not possible,Possible" newline bitfld.quad 0x00 42. "HPD1,Hierarchical Permission Disable for the TTBR1 region" "No,Yes" bitfld.quad 0x00 41. "HPD0,Hierarchical Permission Disable for the TTBR0 region" "No,Yes" newline bitfld.quad 0x00 40. "HD,Hardware Update of the Dirty Bit Enable - Stage 1" "Disabled,Enabled" bitfld.quad 0x00 39. "HA,Hardware Update of the Access Bit Enable - Stage 1" "Disabled,Enabled" newline bitfld.quad 0x00 38. "TBI1,Top Byte ignored" "Used,Ignored" bitfld.quad 0x00 37. "TBI0,Top Byte ignored" "Used,Ignored" newline bitfld.quad 0x00 36. "AS,ASID Size" "8 bit,16 bit" bitfld.quad 0x00 32.--34. "IPS,IPASize" "4GByte,64GByte,1TByte,?..." newline bitfld.quad 0x00 30.--31. "TG1,TTBR1_EL1 Granule size" "Reserved,16KByte,4KByte,64KByte" bitfld.quad 0x00 28.--29. "SH1,Shareability attributes for TTBR1 as described in LPAE" "Non-shareable,Reserved,Outer Shareable,Inner Shareable" newline bitfld.quad 0x00 26.--27. "ORGN1,Outer Cacheability attributes for TTBR1 as described in LPAE" "Outer Non-cacheable,Outer WB WA cacheable,Outer WT cacheable,Outer WB no WA cacheable" bitfld.quad 0x00 24.--25. "IRGN1,Inner Cacheability attributes for TTBR1 as described in LPAE" "Inner Non-cacheable,Inner WB WA cacheable,Inner WT cacheable,Inner WB no WA cacheable" newline bitfld.quad 0x00 23. "EPD1,Translation Table walk disable for TTBR1 as described in LPAE" "No,Yes" bitfld.quad 0x00 22. "A1,ASID definition from TTBR0 or TTBR1" "TTBR0_EL1,TTBR1_EL1" newline bitfld.quad 0x00 16.--21. "T1SZ,Size offset of the memory region for TTBR1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.quad 0x00 14.--15. "TG0,TTBR0_ELx Granule size" "4KByte,64KByte,16KByte,?..." newline bitfld.quad 0x00 12.--13. "SH0,Shareability attributes for TTBR0 as described in LPAE" "Non-shareable,Reserved,Outer Shareable,Inner Shareable" bitfld.quad 0x00 10.--11. "ORGN0,Outer Cacheability attributes for TTBR0 as described in LPAE" "Outer Non-cacheable,Outer WB WA cacheable,Outer WT cacheable,Outer WB no WA cacheable" newline bitfld.quad 0x00 8.--9. "IRGN0,Inner Cacheability attributes for TTBR0 as described in LPAE" "Inner Non-cacheable,Inner WB WA cacheable,Inner WT cacheable,Inner WB no WA cacheable" bitfld.quad 0x00 7. "EPD0,Translation Table walk disable for TTBR0 as described in LPAE" "No,Yes" newline bitfld.quad 0x00 0.--5. "T0SZ,Size offset of the memory region for TTBR0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" group.quad spr:0x35202++0x00 line.quad 0x00 "TCR_EL12,Translation Control Registers" bitfld.quad 0x00 50. "HWU162,Hardware use of bit[62] of the stage1 translation table block or level 3 entry for pages pointed to by TTBR1_EL1/EL2" "Not possible,Possible" bitfld.quad 0x00 49. "HWU161,Hardware use of bit[61] of the stage1 translation table block or level 3 entry for pages pointed to by TTBR1_EL1/EL2" "Not possible,Possible" newline bitfld.quad 0x00 48. "HWU160,Hardware use of bit[60] of the stage1 translation table block or level 3 entry for pages pointed to by TTBR1_EL1/EL2" "Not possible,Possible" bitfld.quad 0x00 47. "HWU159,Hardware use of bit[59] of the stage1 translation table block or level 3 entry for pages pointed to by TTBR1_EL1/EL2" "Not possible,Possible" newline bitfld.quad 0x00 46. "HWU062,Hardware use of bit[62] of the stage1 translation table block or level 3 entry for pages pointed to by TTBR0_EL1/EL2" "Not possible,Possible" bitfld.quad 0x00 45. "HWU061,Hardware use of bit[61] of the stage1 translation table block or level 3 entry for pages pointed to by TTBR0_EL1/EL2" "Not possible,Possible" newline bitfld.quad 0x00 44. "HWU060,Hardware use of bit[60] of the stage1 translation table block or level 3 entry for pages pointed to by TTBR0_EL1/EL2" "Not possible,Possible" bitfld.quad 0x00 43. "HWU059,Hardware use of bit[59] of the stage1 translation table block or level 3 entry for pages pointed to by TTBR0_EL1/EL2" "Not possible,Possible" newline bitfld.quad 0x00 42. "HPD1,Hierarchical Permission Disable for the TTBR1 region" "No,Yes" bitfld.quad 0x00 41. "HPD0,Hierarchical Permission Disable for the TTBR0 region" "No,Yes" newline bitfld.quad 0x00 40. "HD,Hardware Update of the Dirty Bit Enable - Stage 1" "Disabled,Enabled" bitfld.quad 0x00 39. "HA,Hardware Update of the Access Bit Enable - Stage 1" "Disabled,Enabled" newline bitfld.quad 0x00 38. "TBI1,Top Byte ignored" "Used,Ignored" bitfld.quad 0x00 37. "TBI0,Top Byte ignored" "Used,Ignored" newline bitfld.quad 0x00 36. "AS,ASID Size" "8 bit,16 bit" bitfld.quad 0x00 32.--34. "IPS,IPASize" "4GByte,64GByte,1TByte,?..." newline bitfld.quad 0x00 30.--31. "TG1,TTBR1_EL1 Granule size" "Reserved,16KByte,4KByte,64KByte" bitfld.quad 0x00 28.--29. "SH1,Shareability attributes for TTBR1 as described in LPAE" "Non-shareable,Reserved,Outer Shareable,Inner Shareable" newline bitfld.quad 0x00 26.--27. "ORGN1,Outer Cacheability attributes for TTBR1 as described in LPAE" "Outer Non-cacheable,Outer WB WA cacheable,Outer WT cacheable,Outer WB no WA cacheable" bitfld.quad 0x00 24.--25. "IRGN1,Inner Cacheability attributes for TTBR1 as described in LPAE" "Inner Non-cacheable,Inner WB WA cacheable,Inner WT cacheable,Inner WB no WA cacheable" newline bitfld.quad 0x00 23. "EPD1,Translation Table walk disable for TTBR1 as described in LPAE" "No,Yes" bitfld.quad 0x00 22. "A1,ASID definition from TTBR0 or TTBR1" "TTBR0_EL1,TTBR1_EL1" newline bitfld.quad 0x00 16.--21. "T1SZ,Size offset of the memory region for TTBR1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.quad 0x00 14.--15. "TG0,TTBR0_ELx Granule size" "4KByte,64KByte,16KByte,?..." newline bitfld.quad 0x00 12.--13. "SH0,Shareability attributes for TTBR0 as described in LPAE" "Non-shareable,Reserved,Outer Shareable,Inner Shareable" bitfld.quad 0x00 10.--11. "ORGN0,Outer Cacheability attributes for TTBR0 as described in LPAE" "Outer Non-cacheable,Outer WB WA cacheable,Outer WT cacheable,Outer WB no WA cacheable" newline bitfld.quad 0x00 8.--9. "IRGN0,Inner Cacheability attributes for TTBR0 as described in LPAE" "Inner Non-cacheable,Inner WB WA cacheable,Inner WT cacheable,Inner WB no WA cacheable" bitfld.quad 0x00 7. "EPD0,Translation Table walk disable for TTBR0 as described in LPAE" "No,Yes" newline bitfld.quad 0x00 0.--5. "T0SZ,Size offset of the memory region for TTBR0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" if (((per.q(spr:0x34110))&0x400000000)==0x000000000) group.quad spr:0x34202++0x00 line.quad 0x00 "TCR_EL2,Translation Control Registers" bitfld.quad 0x00 28. "HWU62,Hardware usage of bit[62] of the stage1 translation table block or level 3 entry" "Not possible,Possible" bitfld.quad 0x00 27. "HWU61,Hardware usage of bit[61] of the stage1 translation table block or level 3 entry" "Not possible,Possible" newline bitfld.quad 0x00 26. "HWU60,Hardware usage of bit[60] of the stage1 translation table block or level 3 entry" "Not possible,Possible" bitfld.quad 0x00 25. "HWU59,Hardware usage of bit[59] of the stage1 translation table block or level 3 entry" "Not possible,Possible" newline bitfld.quad 0x00 24. "HPD,Hierarchical Permission Disable" "No,Yes" bitfld.quad 0x00 22. "HD,Hardware Update of the Dirty Bit Enable - Stage 1" "Disabled,Enabled" newline bitfld.quad 0x00 21. "HA,Hardware Update of the Access Bit Enable - Stage 1" "Disabled,Enabled" bitfld.quad 0x00 20. "TBI,Top Byte ignored" "Used,Ignored" newline bitfld.quad 0x00 16.--18. "PS,PASize" "4GByte,64GByte,1TByte,?..." bitfld.quad 0x00 14.--15. "TG0,TTBR0_ELx Granule size" "4KByte,64KByte,16KByte,?..." newline bitfld.quad 0x00 12.--13. "SH0,Shareability attributes for TTBR_ELx as described in LPAE" "Non-shareable,Reserved,Outer shareable,Inner shareable" bitfld.quad 0x00 10.--11. "ORGN0,Outer Cacheability attributes for TTBR_ELx as described in LPAE" "Outer Non-cacheable,Outer WB WA cacheable,Outer WT cacheable,Outer WB no WA cacheable" newline bitfld.quad 0x00 8.--9. "IRGN0,Inner Cacheability attributes for TTBR_ELx as described in LPAE" "Inner Non-cacheable,Inner WB WA cacheable,Inner WT cacheable,Inner WB no WA cacheable" bitfld.quad 0x00 0.--5. "T0SZ,Size of virtual address for TTBR_ELx" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" else group.quad spr:0x34202++0x00 line.quad 0x00 "TCR_EL2,Translation Control Registers" bitfld.quad 0x00 50. "HWU162,Hardware use of bit[62] of the stage1 translation table block or level 3 entry for pages pointed to by TTBR1_EL1/EL2" "Not possible,Possible" bitfld.quad 0x00 49. "HWU161,Hardware use of bit[61] of the stage1 translation table block or level 3 entry for pages pointed to by TTBR1_EL1/EL2" "Not possible,Possible" newline bitfld.quad 0x00 48. "HWU160,Hardware use of bit[60] of the stage1 translation table block or level 3 entry for pages pointed to by TTBR1_EL1/EL2" "Not possible,Possible" bitfld.quad 0x00 47. "HWU159,Hardware use of bit[59] of the stage1 translation table block or level 3 entry for pages pointed to by TTBR1_EL1/EL2" "Not possible,Possible" newline bitfld.quad 0x00 46. "HWU062,Hardware use of bit[62] of the stage1 translation table block or level 3 entry for pages pointed to by TTBR0_EL1/EL2" "Not possible,Possible" bitfld.quad 0x00 45. "HWU061,Hardware use of bit[61] of the stage1 translation table block or level 3 entry for pages pointed to by TTBR0_EL1/EL2" "Not possible,Possible" newline bitfld.quad 0x00 44. "HWU060,Hardware use of bit[60] of the stage1 translation table block or level 3 entry for pages pointed to by TTBR0_EL1/EL2" "Not possible,Possible" bitfld.quad 0x00 43. "HWU059,Hardware use of bit[59] of the stage1 translation table block or level 3 entry for pages pointed to by TTBR0_EL1/EL2" "Not possible,Possible" newline bitfld.quad 0x00 42. "HPD1,Hierarchical Permission Disable for the TTBR1 region" "No,Yes" bitfld.quad 0x00 41. "HPD0,Hierarchical Permission Disable for the TTBR0 region" "No,Yes" newline bitfld.quad 0x00 40. "HD,Hardware Update of the Dirty Bit Enable - Stage 1" "Disabled,Enabled" bitfld.quad 0x00 39. "HA,Hardware Update of the Access Bit Enable - Stage 1" "Disabled,Enabled" newline bitfld.quad 0x00 38. "TBI1,Top Byte ignored" "Used,Ignored" bitfld.quad 0x00 37. "TBI0,Top Byte ignored" "Used,Ignored" newline bitfld.quad 0x00 36. "AS,ASID Size" "8 bit,16 bit" bitfld.quad 0x00 32.--34. "IPS,IPASize" "4GByte,64GByte,1TByte,?..." newline bitfld.quad 0x00 30.--31. "TG1,TTBR1_EL1 Granule size" "Reserved,16KByte,4KByte,64KByte" bitfld.quad 0x00 28.--29. "SH1,Shareability attributes for TTBR1 as described in LPAE" "Non-shareable,Reserved,Outer Shareable,Inner Shareable" newline bitfld.quad 0x00 26.--27. "ORGN1,Outer Cacheability attributes for TTBR1 as described in LPAE" "Outer Non-cacheable,Outer WB WA cacheable,Outer WT cacheable,Outer WB no WA cacheable" bitfld.quad 0x00 24.--25. "IRGN1,Inner Cacheability attributes for TTBR1 as described in LPAE" "Inner Non-cacheable,Inner WB WA cacheable,Inner WT cacheable,Inner WB no WA cacheable" newline bitfld.quad 0x00 23. "EPD1,Translation Table walk disable for TTBR1 as described in LPAE" "No,Yes" bitfld.quad 0x00 22. "A1,ASID definition from TTBR0 or TTBR1" "TTBR0_EL1,TTBR1_EL1" newline bitfld.quad 0x00 16.--21. "T1SZ,Size offset of the memory region for TTBR1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" bitfld.quad 0x00 14.--15. "TG0,TTBR0_ELx Granule size" "4KByte,64KByte,16KByte,?..." newline bitfld.quad 0x00 12.--13. "SH0,Shareability attributes for TTBR0 as described in LPAE" "Non-shareable,Reserved,Outer Shareable,Inner Shareable" bitfld.quad 0x00 10.--11. "ORGN0,Outer Cacheability attributes for TTBR0 as described in LPAE" "Outer Non-cacheable,Outer WB WA cacheable,Outer WT cacheable,Outer WB no WA cacheable" newline bitfld.quad 0x00 8.--9. "IRGN0,Inner Cacheability attributes for TTBR0 as described in LPAE" "Inner Non-cacheable,Inner WB WA cacheable,Inner WT cacheable,Inner WB no WA cacheable" bitfld.quad 0x00 7. "EPD0,Translation Table walk disable for TTBR0 as described in LPAE" "No,Yes" newline bitfld.quad 0x00 0.--5. "T0SZ,Size offset of the memory region for TTBR0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" endif if (CORENAME()=="CORTEXA75") group.quad spr:0x36202++0x00 line.quad 0x00 "TCR_EL3,Translation Control Registers" bitfld.quad 0x00 28. "HWU62,Hardware usage of bit[62] of the stage1 translation table block or level 3 entry" "Not possible,Possible" bitfld.quad 0x00 27. "HWU61,Hardware usage of bit[61] of the stage1 translation table block or level 3 entry" "Not possible,Possible" newline bitfld.quad 0x00 26. "HWU60,Hardware usage of bit[60] of the stage1 translation table block or level 3 entry" "Not possible,Possible" bitfld.quad 0x00 25. "HWU59,Hardware usage of bit[59] of the stage1 translation table block or level 3 entry" "Not possible,Possible" newline bitfld.quad 0x00 24. "HPD,Hierarchical Permission Disable" "No,Yes" bitfld.quad 0x00 22. "HD,Hardware Update of the Dirty Bit Enable - Stage 1" "Disabled,Enabled" newline bitfld.quad 0x00 21. "HA,Hardware Update of the Access Bit Enable - Stage 1" "Disabled,Enabled" bitfld.quad 0x00 20. "TBI,Top Byte ignored" "Used,Ignored" newline bitfld.quad 0x00 16.--18. "PS,PASize" "4GByte,64GByte,1TByte,4TByte,16TByte,256TB,4PB,?..." bitfld.quad 0x00 14.--15. "TG0,TTBR0_ELx Granule size" "4KByte,64KByte,16KByte,?..." newline bitfld.quad 0x00 12.--13. "SH0,Shareability attributes for TTBR_ELx as described in LPAE" "Non-shareable,Reserved,Outer shareable,Inner shareable" bitfld.quad 0x00 10.--11. "ORGN0,Outer Cacheability attributes for TTBR_ELx as described in LPAE" "Outer Non-cacheable,Outer WB WA cacheable,Outer WT cacheable,Outer WB no WA cacheable" newline bitfld.quad 0x00 8.--9. "IRGN0,Inner Cacheability attributes for TTBR_ELx as described in LPAE" "Inner Non-cacheable,Inner WB WA cacheable,Inner WT cacheable,Inner WB no WA cacheable" bitfld.quad 0x00 0.--5. "T0SZ,Size of virtual address for TTBR_ELx" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" elif (CORENAME()=="CORTEXA55") group.quad spr:0x36202++0x00 line.quad 0x00 "TCR_EL3,Translation Control Registers" bitfld.quad 0x00 28. "HWU62,Hardware usage of bit[62] of the stage1 translation table block or level 3 entry" "Not possible,Possible" bitfld.quad 0x00 27. "HWU61,Hardware usage of bit[61] of the stage1 translation table block or level 3 entry" "Not possible,Possible" newline bitfld.quad 0x00 26. "HWU60,Hardware usage of bit[60] of the stage1 translation table block or level 3 entry" "Not possible,Possible" bitfld.quad 0x00 25. "HWU59,Hardware usage of bit[59] of the stage1 translation table block or level 3 entry" "Not possible,Possible" newline bitfld.quad 0x00 24. "HPD,Hierarchical Permission Disable" "No,Yes" bitfld.quad 0x00 22. "HD,Hardware Update of the Dirty Bit Enable - Stage 1" "Disabled,Enabled" newline bitfld.quad 0x00 21. "HA,Hardware Update of the Access Bit Enable - Stage 1" "Disabled,Enabled" bitfld.quad 0x00 20. "TBI,Top Byte ignored" "Used,Ignored" newline bitfld.quad 0x00 16.--18. "PS,PASize" "4GByte,64GByte,1TByte,?..." bitfld.quad 0x00 14.--15. "TG0,TTBR0_ELx Granule size" "4KByte,64KByte,16KByte,?..." newline bitfld.quad 0x00 12.--13. "SH0,Shareability attributes for TTBR_ELx as described in LPAE" "Non-shareable,Reserved,Outer shareable,Inner shareable" bitfld.quad 0x00 10.--11. "ORGN0,Outer Cacheability attributes for TTBR_ELx as described in LPAE" "Outer Non-cacheable,Outer WB WA cacheable,Outer WT cacheable,Outer WB no WA cacheable" newline bitfld.quad 0x00 8.--9. "IRGN0,Inner Cacheability attributes for TTBR_ELx as described in LPAE" "Inner Non-cacheable,Inner WB WA cacheable,Inner WT cacheable,Inner WB no WA cacheable" bitfld.quad 0x00 0.--5. "T0SZ,Size of virtual address for TTBR_ELx" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" endif if (((per.q(spr:0x34212))&0xC000)==0x0) group.quad spr:0x34212++0x00 line.quad 0x00 "VTCR_EL2,Virtualization Translation Control Register" bitfld.quad 0x00 28. "HWU62,Hardware usage of bit[62] of the stage 2 translation table block or level 3 entry" "Not possible,Possible" bitfld.quad 0x00 27. "HWU61,Hardware usage of bit[61] of the stage 2 translation table block or level 3 entry" "Not possible,Possible" newline bitfld.quad 0x00 26. "HWU60,Hardware usage of bit[60] of the stage 2 translation table block or level 3 entry" "Not possible,Possible" bitfld.quad 0x00 25. "HWU59,Hardware usage of bit[59] of the stage 2 translation table block or level 3 entry" "Not possible,Possible" newline bitfld.quad 0x00 22. "HD,Hardware Update of the Dirty Bit Enable - Stage 2" "Disabled,Enabled" bitfld.quad 0x00 21. "HA,Hardware Update of the Access Bit Enable - Stage 2" "Disabled,Enabled" newline bitfld.quad 0x00 19. "VS,VMID Size" "8-bit,16-bit" bitfld.quad 0x00 16.--18. "PS,PASize" "4GByte,64GByte,1TByte,4TByte,16TByte,256TByte,?..." newline bitfld.quad 0x00 14.--15. "TG0,VTTBR0_EL2 Granule size" "4KByte,64KByte,16KByte,?..." bitfld.quad 0x00 12.--13. "SH0,Shareability attributes for VTTBR_EL2 as described in LPAE" "Non-shareable,Reserved,Outer shareable,Inner shareable" newline bitfld.quad 0x00 10.--11. "ORGN0,Outer Cacheability attributes for VTTBR_EL2 as described in LPAE" "Outer Non-cacheable,Outer WB WA cacheable,Outer WT cacheable,Outer WB no WA cacheable" bitfld.quad 0x00 8.--9. "IRGN0,Inner Cacheability attributes for VTTBR_EL2 as described in LPAE" "Inner Non-cacheable,Inner WB WA cacheable,Inner WT cacheable,Inner WB no WA cacheable" newline bitfld.quad 0x00 6.--7. "SL0,Starting level of the VTCR_EL2 addressed region" "Level 2,Level 1,Level 0,?..." bitfld.quad 0x00 0.--5. "T0SZ,Size of virtual address for VTTBR_EL2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" else group.quad spr:0x34212++0x00 line.quad 0x00 "VTCR_EL2,Virtualization Translation Control Register" bitfld.quad 0x00 28. "HWU62,Hardware usage of bit[62] of the stage 2 translation table block or level 3 entry" "Not possible,Possible" bitfld.quad 0x00 27. "HWU61,Hardware usage of bit[61] of the stage 2 translation table block or level 3 entry" "Not possible,Possible" newline bitfld.quad 0x00 26. "HWU60,Hardware usage of bit[60] of the stage 2 translation table block or level 3 entry" "Not possible,Possible" bitfld.quad 0x00 25. "HWU59,Hardware usage of bit[59] of the stage 2 translation table block or level 3 entry" "Not possible,Possible" newline bitfld.quad 0x00 22. "HD,Hardware Update of the Dirty Bit Enable - Stage 2" "Disabled,Enabled" bitfld.quad 0x00 21. "HA,Hardware Update of the Access Bit Enable - Stage 2" "Disabled,Enabled" newline bitfld.quad 0x00 19. "VS,VMID Size" "8-bit,16-bit" bitfld.quad 0x00 16.--18. "PS,PASize" "4GByte,64GByte,1TByte,4TByte,16TByte,256TByte,?..." newline bitfld.quad 0x00 14.--15. "TG0,VTTBR0_EL2 Granule size" "4KByte,64KByte,16KByte,?..." bitfld.quad 0x00 12.--13. "SH0,Shareability attributes for VTTBR_EL2 as described in LPAE" "Non-shareable,Reserved,Outer shareable,Inner shareable" newline bitfld.quad 0x00 10.--11. "ORGN0,Outer Cacheability attributes for VTTBR_EL2 as described in LPAE" "Outer Non-cacheable,Outer WB WA cacheable,Outer WT cacheable,Outer WB no WA cacheable" bitfld.quad 0x00 8.--9. "IRGN0,Inner Cacheability attributes for VTTBR_EL2 as described in LPAE" "Inner Non-cacheable,Inner WB WA cacheable,Inner WT cacheable,Inner WB no WA cacheable" newline bitfld.quad 0x00 6.--7. "SL0,Starting level of the VTCR_EL2 addressed region" "Level 3,Level 2,Level 1,?..." bitfld.quad 0x00 0.--5. "T0SZ,Size of virtual address for VTTBR_EL2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63" endif if (CORENAME()=="CORTEXA75") if (((per.q(spr:0x30740))&0xF000000000000001)==0x0000000000000000) group.quad spr:0x30740++0x00 line.quad 0x00 "PAR_EL1,Physical Address Register" bitfld.quad 0x00 60.--63. "ATTRH,Device memory or Normal memory plus Outer cacheability [Type/Cacheable/Allocate]" "Device memory,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Non-Cacheable,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient" newline bitfld.quad 0x00 56.--59. "ATTRL,Device memory or Normal memory plus Inner cacheability [Type/Cacheable/Allocate]" "Device-nGnRnE memory,---,---,---,Device-nGnRE memory,---,---,---,Device-nGRE memory,---,---,---,Device-GRE memory,---,---,---" newline hexmask.quad 0x00 12.--43. 0x10 "PA[47:12],Physical Address" bitfld.quad 0x00 9. "NS,The NS attribute for a translation table entry read from Secure state" "No,Yes" newline bitfld.quad 0x00 7.--8. "SHA,Shareable attribute" "Non-shareable,Reserved,Outer Shareable,Inner Shareable" newline bitfld.quad 0x00 0. "F,Indicates whether the conversion completed successfully" "Successful,Aborted" elif ((((per.q(spr:0x30740))&0x01)==0x00)&&(((per.q(spr:0x30740))&0xF000000000000000)==(0x1000000000000000||0x2000000000000000||0x3000000000000000||0x5000000000000000||0x6000000000000000||0x7000000000000000))) group.quad spr:0x30740++0x00 line.quad 0x00 "PAR_EL1,Physical Address Register" bitfld.quad 0x00 60.--63. "ATTRH,Device memory or Normal memory plus Outer cacheability [Type/Cacheable/Allocate]" "Device memory,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Non-Cacheable,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient" newline newline hexmask.quad 0x00 12.--43. 0x10 "PA[47:12],Physical Address" bitfld.quad 0x00 9. "NS,The NS attribute for a translation table entry read from Secure state" "No,Yes" newline bitfld.quad 0x00 7.--8. "SHA,Shareable attribute" "Non-shareable,Reserved,Outer Shareable,Inner Shareable" newline bitfld.quad 0x00 0. "F,Indicates whether the conversion completed successfully" "Successful,Aborted" elif (((per.q(spr:0x30740))&0x01)==0x00) group.quad spr:0x30740++0x00 line.quad 0x00 "PAR_EL1,Physical Address Register" bitfld.quad 0x00 60.--63. "ATTRH,Device memory or Normal memory plus Outer cacheability [Type/Cacheable/Allocate]" "Device memory,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Non-Cacheable,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient" newline bitfld.quad 0x00 56.--59. "ATTRL,Device memory or Normal memory plus Inner cacheability [Type/Cacheable/Allocate]" "---,Inner Write-Through Transient W,Inner Write-Through Transient R,Inner Write-Through Transient RW,Inner Non-cacheable,Inner Write-Back Transient R,Inner Write-Back Transient W,Inner Write-Back Transient RW,Inner Write-Through Non-transient,Inner Write-Through Non-transient W,Inner Write-Through Non-transient R,Inner Write-Through Non-transient RW,Inner Write-Back Non-transient,Inner Write-Back Non-transient W,Inner Write-Back Non-transient R,Inner Write-Back Non-transient RW" newline hexmask.quad 0x00 12.--43. 0x10 "PA[47:12],Physical Address" bitfld.quad 0x00 9. "NS,The NS attribute for a translation table entry read from Secure state" "No,Yes" newline bitfld.quad 0x00 7.--8. "SHA,Shareable attribute" "Non-shareable,Reserved,Outer Shareable,Inner Shareable" newline bitfld.quad 0x00 0. "F,Indicates whether the conversion completed successfully" "Successful,Aborted" else group.quad spr:0x30740++0x00 line.quad 0x00 "PAR_EL1,Physical Address Register" bitfld.quad 0x00 9. "S,Indicates the translation stage at which the translation aborted" "Stage 1,Stage 2" bitfld.quad 0x00 8. "PTW,Translation aborted because of a stage 2 fault during a stage 1 translation table walk" "No,Yes" newline bitfld.quad 0x00 1.--6. "FST,Fault Status Field" "Address size fault/zeroth level/TTBR,Address size fault/first level,Address size fault/second level,Address size fault/third level,Translation fault/zeroth level,Translation fault/first level,Translation fault/second level,Translation fault/third level,Reserved,Access flag fault/first level,Access flag fault/second level,Access flag fault/third level,Reserved,Permission fault/first level,Permission fault/second level,Permission fault/third level,Synchronous external abort/not TTBR,Reserved,Reserved,Reserved,Synchronous external abort/TTBR/zeroth level,Synchronous external abort/TTBR/first level,Synchronous external abort/TTBR/second level,Synchronous external abort/TTBR/third level,Synchronous parity/ECC error/not TTBR,Reserved,Reserved,Reserved,Synchronous parity/ECC error/TTBR/zeroth level,Synchronous parity/ECC error/TTBR/first level,Synchronous parity/ECC error/TTBR/second level,Synchronous parity/ECC error/TTBR/third level,Reserved,Alignment fault,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,TLB conflict abort,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Section Domain fault,Page Domain fault,Reserved" newline newline newline bitfld.quad 0x00 0. "F,Indicates whether the conversion completed successfully" "Successful,Aborted" endif elif (CORENAME()=="CORTEXA55") if (((per.q(spr:0x30740))&0xF000000000000001)==0x0000000000000000) group.quad spr:0x30740++0x00 line.quad 0x00 "PAR_EL1,Physical Address Register" bitfld.quad 0x00 60.--63. "ATTRH,Device memory or Normal memory plus Outer cacheability [Type/Cacheable/Allocate]" "Device memory,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Non-Cacheable,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient" newline bitfld.quad 0x00 56.--59. "ATTRL,Device memory or Normal memory plus Inner cacheability [Type/Cacheable/Allocate]" "Device-nGnRnE memory,---,---,---,Device-nGnRE memory,---,---,---,Device-nGRE memory,---,---,---,Device-GRE memory,---,---,---" newline hexmask.quad.long 0x00 12.--39. 0x10 "PA[39:12],Physical Address" bitfld.quad 0x00 9. "NS,The NS attribute for a translation table entry read from Secure state" "No,Yes" newline bitfld.quad 0x00 7.--8. "SHA,Shareable attribute" "Non-shareable,Reserved,Outer Shareable,Inner Shareable" newline bitfld.quad 0x00 0. "F,Indicates whether the conversion completed successfully" "Successful,Aborted" elif ((((per.q(spr:0x30740))&0x01)==0x00)&&(((per.q(spr:0x30740))&0xF000000000000000)==(0x1000000000000000||0x2000000000000000||0x3000000000000000||0x5000000000000000||0x6000000000000000||0x7000000000000000))) group.quad spr:0x30740++0x00 line.quad 0x00 "PAR_EL1,Physical Address Register" bitfld.quad 0x00 60.--63. "ATTRH,Device memory or Normal memory plus Outer cacheability [Type/Cacheable/Allocate]" "Device memory,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Non-Cacheable,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient" newline newline hexmask.quad.long 0x00 12.--39. 0x10 "PA[39:12],Physical Address" bitfld.quad 0x00 9. "NS,The NS attribute for a translation table entry read from Secure state" "No,Yes" newline bitfld.quad 0x00 7.--8. "SHA,Shareable attribute" "Non-shareable,Reserved,Outer Shareable,Inner Shareable" newline bitfld.quad 0x00 0. "F,Indicates whether the conversion completed successfully" "Successful,Aborted" elif (((per.q(spr:0x30740))&0x01)==0x00) group.quad spr:0x30740++0x00 line.quad 0x00 "PAR_EL1,Physical Address Register" bitfld.quad 0x00 60.--63. "ATTRH,Device memory or Normal memory plus Outer cacheability [Type/Cacheable/Allocate]" "Device memory,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Non-Cacheable,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient" newline bitfld.quad 0x00 56.--59. "ATTRL,Device memory or Normal memory plus Inner cacheability [Type/Cacheable/Allocate]" "---,Inner Write-Through Transient W,Inner Write-Through Transient R,Inner Write-Through Transient RW,Inner Non-cacheable,Inner Write-Back Transient R,Inner Write-Back Transient W,Inner Write-Back Transient RW,Inner Write-Through Non-transient,Inner Write-Through Non-transient W,Inner Write-Through Non-transient R,Inner Write-Through Non-transient RW,Inner Write-Back Non-transient,Inner Write-Back Non-transient W,Inner Write-Back Non-transient R,Inner Write-Back Non-transient RW" newline hexmask.quad.long 0x00 12.--39. 0x10 "PA[39:12],Physical Address" bitfld.quad 0x00 9. "NS,The NS attribute for a translation table entry read from Secure state" "No,Yes" newline bitfld.quad 0x00 7.--8. "SHA,Shareable attribute" "Non-shareable,Reserved,Outer Shareable,Inner Shareable" newline bitfld.quad 0x00 0. "F,Indicates whether the conversion completed successfully" "Successful,Aborted" else group.quad spr:0x30740++0x00 line.quad 0x00 "PAR_EL1,Physical Address Register" bitfld.quad 0x00 9. "S,Indicates the translation stage at which the translation aborted" "Stage 1,Stage 2" bitfld.quad 0x00 8. "PTW,Translation aborted because of a stage 2 fault during a stage 1 translation table walk" "No,Yes" newline bitfld.quad 0x00 1.--6. "FST,Fault Status Field" "Address size fault/zeroth level/TTBR,Address size fault/first level,Address size fault/second level,Address size fault/third level,Translation fault/zeroth level,Translation fault/first level,Translation fault/second level,Translation fault/third level,Reserved,Access flag fault/first level,Access flag fault/second level,Access flag fault/third level,Reserved,Permission fault/first level,Permission fault/second level,Permission fault/third level,Synchronous external abort/not TTBR,Reserved,Reserved,Reserved,Synchronous external abort/TTBR/zeroth level,Synchronous external abort/TTBR/first level,Synchronous external abort/TTBR/second level,Synchronous external abort/TTBR/third level,Synchronous parity/ECC error/not TTBR,Reserved,Reserved,Reserved,Synchronous parity/ECC error/TTBR/zeroth level,Synchronous parity/ECC error/TTBR/first level,Synchronous parity/ECC error/TTBR/second level,Synchronous parity/ECC error/TTBR/third level,Reserved,Alignment fault,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,TLB conflict abort,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Section Domain fault,Page Domain fault,Reserved" newline newline newline bitfld.quad 0x00 0. "F,Indicates whether the conversion completed successfully" "Successful,Aborted" endif endif newline tree.open "Memory Attribute Indirection Registers" if (CORENAME()=="CORTEXA75") group.quad spr:0x30A20++0x00 line.quad 0x00 "MAIR_EL1,Memory Attribute Indirection Register (EL1)" bitfld.quad 0x00 60.--63. "ATTR7H,Attribute 7 High" "Device memory,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Non-Cacheable,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient" bitfld.quad 0x00 56.--59. "ATTR7L,Attribute 7 Low (Device mem/Normal mem)" "Device-nGnRnE/---,---/Inner Write-through transient,---/Inner Write-through transient,---/Inner Write-through transient,Device-nGnRE/Inner Non-Cacheable,---/Inner Write-back transient,---/Inner Write-back transient,---/Inner Write-back transient,Device-nGRE memory/Inner Write-through,---/Inner Write-through non-transient,---/Inner Write-through non-transient,---/Inner Write-through non-transient,Reserved,---/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient" newline bitfld.quad 0x00 52.--55. "ATTR6H,Attribute 6 High" "Device memory,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Non-Cacheable,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient" bitfld.quad 0x00 48.--51. "ATTR6L,Attribute 6 Low (Device mem/Normal mem)" "Device-nGnRnE/---,---/Inner Write-through transient,---/Inner Write-through transient,---/Inner Write-through transient,Device-nGnRE/Inner Non-Cacheable,---/Inner Write-back transient,---/Inner Write-back transient,---/Inner Write-back transient,Device-nGRE memory/Inner Write-through,---/Inner Write-through non-transient,---/Inner Write-through non-transient,---/Inner Write-through non-transient,Reserved,---/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient" newline bitfld.quad 0x00 44.--47. "ATTR5H,Attribute 5 High" "Device memory,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Non-Cacheable,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient" bitfld.quad 0x00 40.--43. "ATTR5L,Attribute 5 Low (Device mem/Normal mem)" "Device-nGnRnE/---,---/Inner Write-through transient,---/Inner Write-through transient,---/Inner Write-through transient,Device-nGnRE/Inner Non-Cacheable,---/Inner Write-back transient,---/Inner Write-back transient,---/Inner Write-back transient,Device-nGRE memory/Inner Write-through,---/Inner Write-through non-transient,---/Inner Write-through non-transient,---/Inner Write-through non-transient,Reserved,---/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient" newline bitfld.quad 0x00 36.--39. "ATTR4H,Attribute 4 High" "Device memory,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Non-Cacheable,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient" bitfld.quad 0x00 32.--35. "ATTR4L,Attribute 4 Low (Device mem/Normal mem)" "Device-nGnRnE/---,---/Inner Write-through transient,---/Inner Write-through transient,---/Inner Write-through transient,Device-nGnRE/Inner Non-Cacheable,---/Inner Write-back transient,---/Inner Write-back transient,---/Inner Write-back transient,Device-nGRE memory/Inner Write-through,---/Inner Write-through non-transient,---/Inner Write-through non-transient,---/Inner Write-through non-transient,Reserved,---/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient" newline bitfld.quad 0x00 28.--31. "ATTR3H,Attribute 3 High" "Device memory,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Non-Cacheable,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient" bitfld.quad 0x00 24.--27. "ATTR3L,Attribute 3 Low (Device mem/Normal mem)" "Device-nGnRnE/---,---/Inner Write-through transient,---/Inner Write-through transient,---/Inner Write-through transient,Device-nGnRE/Inner Non-Cacheable,---/Inner Write-back transient,---/Inner Write-back transient,---/Inner Write-back transient,Device-nGRE memory/Inner Write-through,---/Inner Write-through non-transient,---/Inner Write-through non-transient,---/Inner Write-through non-transient,Reserved,---/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient" newline bitfld.quad 0x00 20.--23. "ATTR2H,Attribute 2 High" "Device memory,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Non-Cacheable,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient" bitfld.quad 0x00 16.--19. "ATTR2L,Attribute 2 Low (Device mem/Normal mem)" "Device-nGnRnE/---,---/Inner Write-through transient,---/Inner Write-through transient,---/Inner Write-through transient,Device-nGnRE/Inner Non-Cacheable,---/Inner Write-back transient,---/Inner Write-back transient,---/Inner Write-back transient,Device-nGRE memory/Inner Write-through,---/Inner Write-through non-transient,---/Inner Write-through non-transient,---/Inner Write-through non-transient,Reserved,---/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient" newline bitfld.quad 0x00 12.--15. "ATTR1H,Attribute 1 High" "Device memory,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Non-Cacheable,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient" bitfld.quad 0x00 8.--11. "ATTR1L,Attribute 1 Low (Device mem/Normal mem)" "Device-nGnRnE/---,---/Inner Write-through transient,---/Inner Write-through transient,---/Inner Write-through transient,Device-nGnRE/Inner Non-Cacheable,---/Inner Write-back transient,---/Inner Write-back transient,---/Inner Write-back transient,Device-nGRE memory/Inner Write-through,---/Inner Write-through non-transient,---/Inner Write-through non-transient,---/Inner Write-through non-transient,Reserved,---/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient" newline bitfld.quad 0x00 4.--7. "ATTR0H,Attribute 0 High" "Device memory,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Non-Cacheable,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient" bitfld.quad 0x00 0.--3. "ATTR0L,Attribute 0 Low (Device mem/Normal mem)" "Device-nGnRnE/---,---/Inner Write-through transient,---/Inner Write-through transient,---/Inner Write-through transient,Device-nGnRE/Inner Non-Cacheable,---/Inner Write-back transient,---/Inner Write-back transient,---/Inner Write-back transient,Device-nGRE memory/Inner Write-through,---/Inner Write-through non-transient,---/Inner Write-through non-transient,---/Inner Write-through non-transient,Reserved,---/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient" group.quad spr:0x35A20++0x00 line.quad 0x00 "MAIR_EL12,Memory Attribute Indirection Register (EL12)" bitfld.quad 0x00 60.--63. "ATTR7H,Attribute 7 High" "Device memory,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Non-Cacheable,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient" bitfld.quad 0x00 56.--59. "ATTR7L,Attribute 7 Low (Device mem/Normal mem)" "Device-nGnRnE/---,---/Inner Write-through transient,---/Inner Write-through transient,---/Inner Write-through transient,Device-nGnRE/Inner Non-Cacheable,---/Inner Write-back transient,---/Inner Write-back transient,---/Inner Write-back transient,Device-nGRE memory/Inner Write-through,---/Inner Write-through non-transient,---/Inner Write-through non-transient,---/Inner Write-through non-transient,Reserved,---/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient" newline bitfld.quad 0x00 52.--55. "ATTR6H,Attribute 6 High" "Device memory,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Non-Cacheable,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient" bitfld.quad 0x00 48.--51. "ATTR6L,Attribute 6 Low (Device mem/Normal mem)" "Device-nGnRnE/---,---/Inner Write-through transient,---/Inner Write-through transient,---/Inner Write-through transient,Device-nGnRE/Inner Non-Cacheable,---/Inner Write-back transient,---/Inner Write-back transient,---/Inner Write-back transient,Device-nGRE memory/Inner Write-through,---/Inner Write-through non-transient,---/Inner Write-through non-transient,---/Inner Write-through non-transient,Reserved,---/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient" newline bitfld.quad 0x00 44.--47. "ATTR5H,Attribute 5 High" "Device memory,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Non-Cacheable,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient" bitfld.quad 0x00 40.--43. "ATTR5L,Attribute 5 Low (Device mem/Normal mem)" "Device-nGnRnE/---,---/Inner Write-through transient,---/Inner Write-through transient,---/Inner Write-through transient,Device-nGnRE/Inner Non-Cacheable,---/Inner Write-back transient,---/Inner Write-back transient,---/Inner Write-back transient,Device-nGRE memory/Inner Write-through,---/Inner Write-through non-transient,---/Inner Write-through non-transient,---/Inner Write-through non-transient,Reserved,---/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient" newline bitfld.quad 0x00 36.--39. "ATTR4H,Attribute 4 High" "Device memory,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Non-Cacheable,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient" bitfld.quad 0x00 32.--35. "ATTR4L,Attribute 4 Low (Device mem/Normal mem)" "Device-nGnRnE/---,---/Inner Write-through transient,---/Inner Write-through transient,---/Inner Write-through transient,Device-nGnRE/Inner Non-Cacheable,---/Inner Write-back transient,---/Inner Write-back transient,---/Inner Write-back transient,Device-nGRE memory/Inner Write-through,---/Inner Write-through non-transient,---/Inner Write-through non-transient,---/Inner Write-through non-transient,Reserved,---/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient" newline bitfld.quad 0x00 28.--31. "ATTR3H,Attribute 3 High" "Device memory,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Non-Cacheable,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient" bitfld.quad 0x00 24.--27. "ATTR3L,Attribute 3 Low (Device mem/Normal mem)" "Device-nGnRnE/---,---/Inner Write-through transient,---/Inner Write-through transient,---/Inner Write-through transient,Device-nGnRE/Inner Non-Cacheable,---/Inner Write-back transient,---/Inner Write-back transient,---/Inner Write-back transient,Device-nGRE memory/Inner Write-through,---/Inner Write-through non-transient,---/Inner Write-through non-transient,---/Inner Write-through non-transient,Reserved,---/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient" newline bitfld.quad 0x00 20.--23. "ATTR2H,Attribute 2 High" "Device memory,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Non-Cacheable,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient" bitfld.quad 0x00 16.--19. "ATTR2L,Attribute 2 Low (Device mem/Normal mem)" "Device-nGnRnE/---,---/Inner Write-through transient,---/Inner Write-through transient,---/Inner Write-through transient,Device-nGnRE/Inner Non-Cacheable,---/Inner Write-back transient,---/Inner Write-back transient,---/Inner Write-back transient,Device-nGRE memory/Inner Write-through,---/Inner Write-through non-transient,---/Inner Write-through non-transient,---/Inner Write-through non-transient,Reserved,---/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient" newline bitfld.quad 0x00 12.--15. "ATTR1H,Attribute 1 High" "Device memory,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Non-Cacheable,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient" bitfld.quad 0x00 8.--11. "ATTR1L,Attribute 1 Low (Device mem/Normal mem)" "Device-nGnRnE/---,---/Inner Write-through transient,---/Inner Write-through transient,---/Inner Write-through transient,Device-nGnRE/Inner Non-Cacheable,---/Inner Write-back transient,---/Inner Write-back transient,---/Inner Write-back transient,Device-nGRE memory/Inner Write-through,---/Inner Write-through non-transient,---/Inner Write-through non-transient,---/Inner Write-through non-transient,Reserved,---/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient" newline bitfld.quad 0x00 4.--7. "ATTR0H,Attribute 0 High" "Device memory,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Non-Cacheable,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient" bitfld.quad 0x00 0.--3. "ATTR0L,Attribute 0 Low (Device mem/Normal mem)" "Device-nGnRnE/---,---/Inner Write-through transient,---/Inner Write-through transient,---/Inner Write-through transient,Device-nGnRE/Inner Non-Cacheable,---/Inner Write-back transient,---/Inner Write-back transient,---/Inner Write-back transient,Device-nGRE memory/Inner Write-through,---/Inner Write-through non-transient,---/Inner Write-through non-transient,---/Inner Write-through non-transient,Reserved,---/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient" group.quad spr:0x34A20++0x00 line.quad 0x00 "MAIR_EL2,Memory Attribute Indirection Register (EL2)" bitfld.quad 0x00 60.--63. "ATTR7H,Attribute 7 High" "Device memory,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Non-Cacheable,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient" bitfld.quad 0x00 56.--59. "ATTR7L,Attribute 7 Low (Device mem/Normal mem)" "Device-nGnRnE/---,---/Inner Write-through transient,---/Inner Write-through transient,---/Inner Write-through transient,Device-nGnRE/Inner Non-Cacheable,---/Inner Write-back transient,---/Inner Write-back transient,---/Inner Write-back transient,Device-nGRE memory/Inner Write-through,---/Inner Write-through non-transient,---/Inner Write-through non-transient,---/Inner Write-through non-transient,Reserved,---/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient" newline bitfld.quad 0x00 52.--55. "ATTR6H,Attribute 6 High" "Device memory,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Non-Cacheable,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient" bitfld.quad 0x00 48.--51. "ATTR6L,Attribute 6 Low (Device mem/Normal mem)" "Device-nGnRnE/---,---/Inner Write-through transient,---/Inner Write-through transient,---/Inner Write-through transient,Device-nGnRE/Inner Non-Cacheable,---/Inner Write-back transient,---/Inner Write-back transient,---/Inner Write-back transient,Device-nGRE memory/Inner Write-through,---/Inner Write-through non-transient,---/Inner Write-through non-transient,---/Inner Write-through non-transient,Reserved,---/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient" newline bitfld.quad 0x00 44.--47. "ATTR5H,Attribute 5 High" "Device memory,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Non-Cacheable,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient" bitfld.quad 0x00 40.--43. "ATTR5L,Attribute 5 Low (Device mem/Normal mem)" "Device-nGnRnE/---,---/Inner Write-through transient,---/Inner Write-through transient,---/Inner Write-through transient,Device-nGnRE/Inner Non-Cacheable,---/Inner Write-back transient,---/Inner Write-back transient,---/Inner Write-back transient,Device-nGRE memory/Inner Write-through,---/Inner Write-through non-transient,---/Inner Write-through non-transient,---/Inner Write-through non-transient,Reserved,---/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient" newline bitfld.quad 0x00 36.--39. "ATTR4H,Attribute 4 High" "Device memory,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Non-Cacheable,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient" bitfld.quad 0x00 32.--35. "ATTR4L,Attribute 4 Low (Device mem/Normal mem)" "Device-nGnRnE/---,---/Inner Write-through transient,---/Inner Write-through transient,---/Inner Write-through transient,Device-nGnRE/Inner Non-Cacheable,---/Inner Write-back transient,---/Inner Write-back transient,---/Inner Write-back transient,Device-nGRE memory/Inner Write-through,---/Inner Write-through non-transient,---/Inner Write-through non-transient,---/Inner Write-through non-transient,Reserved,---/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient" newline bitfld.quad 0x00 28.--31. "ATTR3H,Attribute 3 High" "Device memory,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Non-Cacheable,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient" bitfld.quad 0x00 24.--27. "ATTR3L,Attribute 3 Low (Device mem/Normal mem)" "Device-nGnRnE/---,---/Inner Write-through transient,---/Inner Write-through transient,---/Inner Write-through transient,Device-nGnRE/Inner Non-Cacheable,---/Inner Write-back transient,---/Inner Write-back transient,---/Inner Write-back transient,Device-nGRE memory/Inner Write-through,---/Inner Write-through non-transient,---/Inner Write-through non-transient,---/Inner Write-through non-transient,Reserved,---/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient" newline bitfld.quad 0x00 20.--23. "ATTR2H,Attribute 2 High" "Device memory,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Non-Cacheable,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient" bitfld.quad 0x00 16.--19. "ATTR2L,Attribute 2 Low (Device mem/Normal mem)" "Device-nGnRnE/---,---/Inner Write-through transient,---/Inner Write-through transient,---/Inner Write-through transient,Device-nGnRE/Inner Non-Cacheable,---/Inner Write-back transient,---/Inner Write-back transient,---/Inner Write-back transient,Device-nGRE memory/Inner Write-through,---/Inner Write-through non-transient,---/Inner Write-through non-transient,---/Inner Write-through non-transient,Reserved,---/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient" newline bitfld.quad 0x00 12.--15. "ATTR1H,Attribute 1 High" "Device memory,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Non-Cacheable,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient" bitfld.quad 0x00 8.--11. "ATTR1L,Attribute 1 Low (Device mem/Normal mem)" "Device-nGnRnE/---,---/Inner Write-through transient,---/Inner Write-through transient,---/Inner Write-through transient,Device-nGnRE/Inner Non-Cacheable,---/Inner Write-back transient,---/Inner Write-back transient,---/Inner Write-back transient,Device-nGRE memory/Inner Write-through,---/Inner Write-through non-transient,---/Inner Write-through non-transient,---/Inner Write-through non-transient,Reserved,---/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient" newline bitfld.quad 0x00 4.--7. "ATTR0H,Attribute 0 High" "Device memory,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Non-Cacheable,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient" bitfld.quad 0x00 0.--3. "ATTR0L,Attribute 0 Low (Device mem/Normal mem)" "Device-nGnRnE/---,---/Inner Write-through transient,---/Inner Write-through transient,---/Inner Write-through transient,Device-nGnRE/Inner Non-Cacheable,---/Inner Write-back transient,---/Inner Write-back transient,---/Inner Write-back transient,Device-nGRE memory/Inner Write-through,---/Inner Write-through non-transient,---/Inner Write-through non-transient,---/Inner Write-through non-transient,Reserved,---/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient" group.quad spr:0x36A20++0x00 line.quad 0x00 "MAIR_EL3,Memory Attribute Indirection Register (EL3)" bitfld.quad 0x00 60.--63. "ATTR7H,Attribute 7 High" "Device memory,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Non-Cacheable,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient" bitfld.quad 0x00 56.--59. "ATTR7L,Attribute 7 Low (Device mem/Normal mem)" "Device-nGnRnE/---,---/Inner Write-through transient,---/Inner Write-through transient,---/Inner Write-through transient,Device-nGnRE/Inner Non-Cacheable,---/Inner Write-back transient,---/Inner Write-back transient,---/Inner Write-back transient,Device-nGRE memory/Inner Write-through,---/Inner Write-through non-transient,---/Inner Write-through non-transient,---/Inner Write-through non-transient,Reserved,---/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient" newline bitfld.quad 0x00 52.--55. "ATTR6H,Attribute 6 High" "Device memory,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Non-Cacheable,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient" bitfld.quad 0x00 48.--51. "ATTR6L,Attribute 6 Low (Device mem/Normal mem)" "Device-nGnRnE/---,---/Inner Write-through transient,---/Inner Write-through transient,---/Inner Write-through transient,Device-nGnRE/Inner Non-Cacheable,---/Inner Write-back transient,---/Inner Write-back transient,---/Inner Write-back transient,Device-nGRE memory/Inner Write-through,---/Inner Write-through non-transient,---/Inner Write-through non-transient,---/Inner Write-through non-transient,Reserved,---/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient" newline bitfld.quad 0x00 44.--47. "ATTR5H,Attribute 5 High" "Device memory,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Non-Cacheable,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient" bitfld.quad 0x00 40.--43. "ATTR5L,Attribute 5 Low (Device mem/Normal mem)" "Device-nGnRnE/---,---/Inner Write-through transient,---/Inner Write-through transient,---/Inner Write-through transient,Device-nGnRE/Inner Non-Cacheable,---/Inner Write-back transient,---/Inner Write-back transient,---/Inner Write-back transient,Device-nGRE memory/Inner Write-through,---/Inner Write-through non-transient,---/Inner Write-through non-transient,---/Inner Write-through non-transient,Reserved,---/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient" newline bitfld.quad 0x00 36.--39. "ATTR4H,Attribute 4 High" "Device memory,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Non-Cacheable,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient" bitfld.quad 0x00 32.--35. "ATTR4L,Attribute 4 Low (Device mem/Normal mem)" "Device-nGnRnE/---,---/Inner Write-through transient,---/Inner Write-through transient,---/Inner Write-through transient,Device-nGnRE/Inner Non-Cacheable,---/Inner Write-back transient,---/Inner Write-back transient,---/Inner Write-back transient,Device-nGRE memory/Inner Write-through,---/Inner Write-through non-transient,---/Inner Write-through non-transient,---/Inner Write-through non-transient,Reserved,---/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient" newline bitfld.quad 0x00 28.--31. "ATTR3H,Attribute 3 High" "Device memory,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Non-Cacheable,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient" bitfld.quad 0x00 24.--27. "ATTR3L,Attribute 3 Low (Device mem/Normal mem)" "Device-nGnRnE/---,---/Inner Write-through transient,---/Inner Write-through transient,---/Inner Write-through transient,Device-nGnRE/Inner Non-Cacheable,---/Inner Write-back transient,---/Inner Write-back transient,---/Inner Write-back transient,Device-nGRE memory/Inner Write-through,---/Inner Write-through non-transient,---/Inner Write-through non-transient,---/Inner Write-through non-transient,Reserved,---/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient" newline bitfld.quad 0x00 20.--23. "ATTR2H,Attribute 2 High" "Device memory,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Non-Cacheable,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient" bitfld.quad 0x00 16.--19. "ATTR2L,Attribute 2 Low (Device mem/Normal mem)" "Device-nGnRnE/---,---/Inner Write-through transient,---/Inner Write-through transient,---/Inner Write-through transient,Device-nGnRE/Inner Non-Cacheable,---/Inner Write-back transient,---/Inner Write-back transient,---/Inner Write-back transient,Device-nGRE memory/Inner Write-through,---/Inner Write-through non-transient,---/Inner Write-through non-transient,---/Inner Write-through non-transient,Reserved,---/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient" newline bitfld.quad 0x00 12.--15. "ATTR1H,Attribute 1 High" "Device memory,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Non-Cacheable,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient" bitfld.quad 0x00 8.--11. "ATTR1L,Attribute 1 Low (Device mem/Normal mem)" "Device-nGnRnE/---,---/Inner Write-through transient,---/Inner Write-through transient,---/Inner Write-through transient,Device-nGnRE/Inner Non-Cacheable,---/Inner Write-back transient,---/Inner Write-back transient,---/Inner Write-back transient,Device-nGRE memory/Inner Write-through,---/Inner Write-through non-transient,---/Inner Write-through non-transient,---/Inner Write-through non-transient,Reserved,---/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient" newline bitfld.quad 0x00 4.--7. "ATTR0H,Attribute 0 High" "Device memory,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Non-Cacheable,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient" bitfld.quad 0x00 0.--3. "ATTR0L,Attribute 0 Low (Device mem/Normal mem)" "Device-nGnRnE/---,---/Inner Write-through transient,---/Inner Write-through transient,---/Inner Write-through transient,Device-nGnRE/Inner Non-Cacheable,---/Inner Write-back transient,---/Inner Write-back transient,---/Inner Write-back transient,Device-nGRE memory/Inner Write-through,---/Inner Write-through non-transient,---/Inner Write-through non-transient,---/Inner Write-through non-transient,Reserved,---/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient" elif (CORENAME()=="CORTEXA55") group.quad spr:0x30A20++0x00 line.quad 0x00 "MAIR_EL1,Memory Attribute Indirection Register (EL1)" bitfld.quad 0x00 60.--63. "ATTR7H,Attribute 7 High" "Device memory,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Non-Cacheable,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient" bitfld.quad 0x00 56.--59. "ATTR7L,Attribute 7 Low (Device mem/Normal mem)" "Device-nGnRnE/---,---/Inner Write-through transient,---/Inner Write-through transient,---/Inner Write-through transient,Device-nGnRE/Inner Non-Cacheable,---/Inner Write-back transient,---/Inner Write-back transient,---/Inner Write-back transient,Device-nGRE memory/Inner Write-through,---/Inner Write-through non-transient,---/Inner Write-through non-transient,---/Inner Write-through non-transient,Device-GRE memory/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient" newline bitfld.quad 0x00 52.--55. "ATTR6H,Attribute 6 High" "Device memory,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Non-Cacheable,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient" bitfld.quad 0x00 48.--51. "ATTR6L,Attribute 6 Low (Device mem/Normal mem)" "Device-nGnRnE/---,---/Inner Write-through transient,---/Inner Write-through transient,---/Inner Write-through transient,Device-nGnRE/Inner Non-Cacheable,---/Inner Write-back transient,---/Inner Write-back transient,---/Inner Write-back transient,Device-nGRE memory/Inner Write-through,---/Inner Write-through non-transient,---/Inner Write-through non-transient,---/Inner Write-through non-transient,Device-GRE memory/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient" newline bitfld.quad 0x00 44.--47. "ATTR5H,Attribute 5 High" "Device memory,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Non-Cacheable,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient" bitfld.quad 0x00 40.--43. "ATTR5L,Attribute 5 Low (Device mem/Normal mem)" "Device-nGnRnE/---,---/Inner Write-through transient,---/Inner Write-through transient,---/Inner Write-through transient,Device-nGnRE/Inner Non-Cacheable,---/Inner Write-back transient,---/Inner Write-back transient,---/Inner Write-back transient,Device-nGRE memory/Inner Write-through,---/Inner Write-through non-transient,---/Inner Write-through non-transient,---/Inner Write-through non-transient,Device-GRE memory/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient" newline bitfld.quad 0x00 36.--39. "ATTR4H,Attribute 4 High" "Device memory,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Non-Cacheable,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient" bitfld.quad 0x00 32.--35. "ATTR4L,Attribute 4 Low (Device mem/Normal mem)" "Device-nGnRnE/---,---/Inner Write-through transient,---/Inner Write-through transient,---/Inner Write-through transient,Device-nGnRE/Inner Non-Cacheable,---/Inner Write-back transient,---/Inner Write-back transient,---/Inner Write-back transient,Device-nGRE memory/Inner Write-through,---/Inner Write-through non-transient,---/Inner Write-through non-transient,---/Inner Write-through non-transient,Device-GRE memory/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient" newline bitfld.quad 0x00 28.--31. "ATTR3H,Attribute 3 High" "Device memory,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Non-Cacheable,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient" bitfld.quad 0x00 24.--27. "ATTR3L,Attribute 3 Low (Device mem/Normal mem)" "Device-nGnRnE/---,---/Inner Write-through transient,---/Inner Write-through transient,---/Inner Write-through transient,Device-nGnRE/Inner Non-Cacheable,---/Inner Write-back transient,---/Inner Write-back transient,---/Inner Write-back transient,Device-nGRE memory/Inner Write-through,---/Inner Write-through non-transient,---/Inner Write-through non-transient,---/Inner Write-through non-transient,Device-GRE memory/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient" newline bitfld.quad 0x00 20.--23. "ATTR2H,Attribute 2 High" "Device memory,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Non-Cacheable,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient" bitfld.quad 0x00 16.--19. "ATTR2L,Attribute 2 Low (Device mem/Normal mem)" "Device-nGnRnE/---,---/Inner Write-through transient,---/Inner Write-through transient,---/Inner Write-through transient,Device-nGnRE/Inner Non-Cacheable,---/Inner Write-back transient,---/Inner Write-back transient,---/Inner Write-back transient,Device-nGRE memory/Inner Write-through,---/Inner Write-through non-transient,---/Inner Write-through non-transient,---/Inner Write-through non-transient,Device-GRE memory/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient" newline bitfld.quad 0x00 12.--15. "ATTR1H,Attribute 1 High" "Device memory,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Non-Cacheable,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient" bitfld.quad 0x00 8.--11. "ATTR1L,Attribute 1 Low (Device mem/Normal mem)" "Device-nGnRnE/---,---/Inner Write-through transient,---/Inner Write-through transient,---/Inner Write-through transient,Device-nGnRE/Inner Non-Cacheable,---/Inner Write-back transient,---/Inner Write-back transient,---/Inner Write-back transient,Device-nGRE memory/Inner Write-through,---/Inner Write-through non-transient,---/Inner Write-through non-transient,---/Inner Write-through non-transient,Device-GRE memory/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient" newline bitfld.quad 0x00 4.--7. "ATTR0H,Attribute 0 High" "Device memory,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Non-Cacheable,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient" bitfld.quad 0x00 0.--3. "ATTR0L,Attribute 0 Low (Device mem/Normal mem)" "Device-nGnRnE/---,---/Inner Write-through transient,---/Inner Write-through transient,---/Inner Write-through transient,Device-nGnRE/Inner Non-Cacheable,---/Inner Write-back transient,---/Inner Write-back transient,---/Inner Write-back transient,Device-nGRE memory/Inner Write-through,---/Inner Write-through non-transient,---/Inner Write-through non-transient,---/Inner Write-through non-transient,Device-GRE memory/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient" group.quad spr:0x35A20++0x00 line.quad 0x00 "MAIR_EL12,Memory Attribute Indirection Register (EL12)" bitfld.quad 0x00 60.--63. "ATTR7H,Attribute 7 High" "Device memory,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Non-Cacheable,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient" bitfld.quad 0x00 56.--59. "ATTR7L,Attribute 7 Low (Device mem/Normal mem)" "Device-nGnRnE/---,---/Inner Write-through transient,---/Inner Write-through transient,---/Inner Write-through transient,Device-nGnRE/Inner Non-Cacheable,---/Inner Write-back transient,---/Inner Write-back transient,---/Inner Write-back transient,Device-nGRE memory/Inner Write-through,---/Inner Write-through non-transient,---/Inner Write-through non-transient,---/Inner Write-through non-transient,Device-GRE memory/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient" newline bitfld.quad 0x00 52.--55. "ATTR6H,Attribute 6 High" "Device memory,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Non-Cacheable,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient" bitfld.quad 0x00 48.--51. "ATTR6L,Attribute 6 Low (Device mem/Normal mem)" "Device-nGnRnE/---,---/Inner Write-through transient,---/Inner Write-through transient,---/Inner Write-through transient,Device-nGnRE/Inner Non-Cacheable,---/Inner Write-back transient,---/Inner Write-back transient,---/Inner Write-back transient,Device-nGRE memory/Inner Write-through,---/Inner Write-through non-transient,---/Inner Write-through non-transient,---/Inner Write-through non-transient,Device-GRE memory/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient" newline bitfld.quad 0x00 44.--47. "ATTR5H,Attribute 5 High" "Device memory,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Non-Cacheable,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient" bitfld.quad 0x00 40.--43. "ATTR5L,Attribute 5 Low (Device mem/Normal mem)" "Device-nGnRnE/---,---/Inner Write-through transient,---/Inner Write-through transient,---/Inner Write-through transient,Device-nGnRE/Inner Non-Cacheable,---/Inner Write-back transient,---/Inner Write-back transient,---/Inner Write-back transient,Device-nGRE memory/Inner Write-through,---/Inner Write-through non-transient,---/Inner Write-through non-transient,---/Inner Write-through non-transient,Device-GRE memory/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient" newline bitfld.quad 0x00 36.--39. "ATTR4H,Attribute 4 High" "Device memory,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Non-Cacheable,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient" bitfld.quad 0x00 32.--35. "ATTR4L,Attribute 4 Low (Device mem/Normal mem)" "Device-nGnRnE/---,---/Inner Write-through transient,---/Inner Write-through transient,---/Inner Write-through transient,Device-nGnRE/Inner Non-Cacheable,---/Inner Write-back transient,---/Inner Write-back transient,---/Inner Write-back transient,Device-nGRE memory/Inner Write-through,---/Inner Write-through non-transient,---/Inner Write-through non-transient,---/Inner Write-through non-transient,Device-GRE memory/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient" newline bitfld.quad 0x00 28.--31. "ATTR3H,Attribute 3 High" "Device memory,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Non-Cacheable,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient" bitfld.quad 0x00 24.--27. "ATTR3L,Attribute 3 Low (Device mem/Normal mem)" "Device-nGnRnE/---,---/Inner Write-through transient,---/Inner Write-through transient,---/Inner Write-through transient,Device-nGnRE/Inner Non-Cacheable,---/Inner Write-back transient,---/Inner Write-back transient,---/Inner Write-back transient,Device-nGRE memory/Inner Write-through,---/Inner Write-through non-transient,---/Inner Write-through non-transient,---/Inner Write-through non-transient,Device-GRE memory/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient" newline bitfld.quad 0x00 20.--23. "ATTR2H,Attribute 2 High" "Device memory,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Non-Cacheable,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient" bitfld.quad 0x00 16.--19. "ATTR2L,Attribute 2 Low (Device mem/Normal mem)" "Device-nGnRnE/---,---/Inner Write-through transient,---/Inner Write-through transient,---/Inner Write-through transient,Device-nGnRE/Inner Non-Cacheable,---/Inner Write-back transient,---/Inner Write-back transient,---/Inner Write-back transient,Device-nGRE memory/Inner Write-through,---/Inner Write-through non-transient,---/Inner Write-through non-transient,---/Inner Write-through non-transient,Device-GRE memory/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient" newline bitfld.quad 0x00 12.--15. "ATTR1H,Attribute 1 High" "Device memory,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Non-Cacheable,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient" bitfld.quad 0x00 8.--11. "ATTR1L,Attribute 1 Low (Device mem/Normal mem)" "Device-nGnRnE/---,---/Inner Write-through transient,---/Inner Write-through transient,---/Inner Write-through transient,Device-nGnRE/Inner Non-Cacheable,---/Inner Write-back transient,---/Inner Write-back transient,---/Inner Write-back transient,Device-nGRE memory/Inner Write-through,---/Inner Write-through non-transient,---/Inner Write-through non-transient,---/Inner Write-through non-transient,Device-GRE memory/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient" newline bitfld.quad 0x00 4.--7. "ATTR0H,Attribute 0 High" "Device memory,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Non-Cacheable,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient" bitfld.quad 0x00 0.--3. "ATTR0L,Attribute 0 Low (Device mem/Normal mem)" "Device-nGnRnE/---,---/Inner Write-through transient,---/Inner Write-through transient,---/Inner Write-through transient,Device-nGnRE/Inner Non-Cacheable,---/Inner Write-back transient,---/Inner Write-back transient,---/Inner Write-back transient,Device-nGRE memory/Inner Write-through,---/Inner Write-through non-transient,---/Inner Write-through non-transient,---/Inner Write-through non-transient,Device-GRE memory/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient" group.quad spr:0x34A20++0x00 line.quad 0x00 "MAIR_EL2,Memory Attribute Indirection Register (EL2)" bitfld.quad 0x00 60.--63. "ATTR7H,Attribute 7 High" "Device memory,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Non-Cacheable,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient" bitfld.quad 0x00 56.--59. "ATTR7L,Attribute 7 Low (Device mem/Normal mem)" "Device-nGnRnE/---,---/Inner Write-through transient,---/Inner Write-through transient,---/Inner Write-through transient,Device-nGnRE/Inner Non-Cacheable,---/Inner Write-back transient,---/Inner Write-back transient,---/Inner Write-back transient,Device-nGRE memory/Inner Write-through,---/Inner Write-through non-transient,---/Inner Write-through non-transient,---/Inner Write-through non-transient,Device-GRE memory/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient" newline bitfld.quad 0x00 52.--55. "ATTR6H,Attribute 6 High" "Device memory,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Non-Cacheable,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient" bitfld.quad 0x00 48.--51. "ATTR6L,Attribute 6 Low (Device mem/Normal mem)" "Device-nGnRnE/---,---/Inner Write-through transient,---/Inner Write-through transient,---/Inner Write-through transient,Device-nGnRE/Inner Non-Cacheable,---/Inner Write-back transient,---/Inner Write-back transient,---/Inner Write-back transient,Device-nGRE memory/Inner Write-through,---/Inner Write-through non-transient,---/Inner Write-through non-transient,---/Inner Write-through non-transient,Device-GRE memory/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient" newline bitfld.quad 0x00 44.--47. "ATTR5H,Attribute 5 High" "Device memory,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Non-Cacheable,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient" bitfld.quad 0x00 40.--43. "ATTR5L,Attribute 5 Low (Device mem/Normal mem)" "Device-nGnRnE/---,---/Inner Write-through transient,---/Inner Write-through transient,---/Inner Write-through transient,Device-nGnRE/Inner Non-Cacheable,---/Inner Write-back transient,---/Inner Write-back transient,---/Inner Write-back transient,Device-nGRE memory/Inner Write-through,---/Inner Write-through non-transient,---/Inner Write-through non-transient,---/Inner Write-through non-transient,Device-GRE memory/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient" newline bitfld.quad 0x00 36.--39. "ATTR4H,Attribute 4 High" "Device memory,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Non-Cacheable,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient" bitfld.quad 0x00 32.--35. "ATTR4L,Attribute 4 Low (Device mem/Normal mem)" "Device-nGnRnE/---,---/Inner Write-through transient,---/Inner Write-through transient,---/Inner Write-through transient,Device-nGnRE/Inner Non-Cacheable,---/Inner Write-back transient,---/Inner Write-back transient,---/Inner Write-back transient,Device-nGRE memory/Inner Write-through,---/Inner Write-through non-transient,---/Inner Write-through non-transient,---/Inner Write-through non-transient,Device-GRE memory/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient" newline bitfld.quad 0x00 28.--31. "ATTR3H,Attribute 3 High" "Device memory,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Non-Cacheable,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient" bitfld.quad 0x00 24.--27. "ATTR3L,Attribute 3 Low (Device mem/Normal mem)" "Device-nGnRnE/---,---/Inner Write-through transient,---/Inner Write-through transient,---/Inner Write-through transient,Device-nGnRE/Inner Non-Cacheable,---/Inner Write-back transient,---/Inner Write-back transient,---/Inner Write-back transient,Device-nGRE memory/Inner Write-through,---/Inner Write-through non-transient,---/Inner Write-through non-transient,---/Inner Write-through non-transient,Device-GRE memory/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient" newline bitfld.quad 0x00 20.--23. "ATTR2H,Attribute 2 High" "Device memory,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Non-Cacheable,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient" bitfld.quad 0x00 16.--19. "ATTR2L,Attribute 2 Low (Device mem/Normal mem)" "Device-nGnRnE/---,---/Inner Write-through transient,---/Inner Write-through transient,---/Inner Write-through transient,Device-nGnRE/Inner Non-Cacheable,---/Inner Write-back transient,---/Inner Write-back transient,---/Inner Write-back transient,Device-nGRE memory/Inner Write-through,---/Inner Write-through non-transient,---/Inner Write-through non-transient,---/Inner Write-through non-transient,Device-GRE memory/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient" newline bitfld.quad 0x00 12.--15. "ATTR1H,Attribute 1 High" "Device memory,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Non-Cacheable,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient" bitfld.quad 0x00 8.--11. "ATTR1L,Attribute 1 Low (Device mem/Normal mem)" "Device-nGnRnE/---,---/Inner Write-through transient,---/Inner Write-through transient,---/Inner Write-through transient,Device-nGnRE/Inner Non-Cacheable,---/Inner Write-back transient,---/Inner Write-back transient,---/Inner Write-back transient,Device-nGRE memory/Inner Write-through,---/Inner Write-through non-transient,---/Inner Write-through non-transient,---/Inner Write-through non-transient,Device-GRE memory/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient" newline bitfld.quad 0x00 4.--7. "ATTR0H,Attribute 0 High" "Device memory,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Non-Cacheable,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient" bitfld.quad 0x00 0.--3. "ATTR0L,Attribute 0 Low (Device mem/Normal mem)" "Device-nGnRnE/---,---/Inner Write-through transient,---/Inner Write-through transient,---/Inner Write-through transient,Device-nGnRE/Inner Non-Cacheable,---/Inner Write-back transient,---/Inner Write-back transient,---/Inner Write-back transient,Device-nGRE memory/Inner Write-through,---/Inner Write-through non-transient,---/Inner Write-through non-transient,---/Inner Write-through non-transient,Device-GRE memory/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient" group.quad spr:0x36A20++0x00 line.quad 0x00 "MAIR_EL3,Memory Attribute Indirection Register (EL3)" bitfld.quad 0x00 60.--63. "ATTR7H,Attribute 7 High" "Device memory,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Non-Cacheable,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient" bitfld.quad 0x00 56.--59. "ATTR7L,Attribute 7 Low (Device mem/Normal mem)" "Device-nGnRnE/---,---/Inner Write-through transient,---/Inner Write-through transient,---/Inner Write-through transient,Device-nGnRE/Inner Non-Cacheable,---/Inner Write-back transient,---/Inner Write-back transient,---/Inner Write-back transient,Device-nGRE memory/Inner Write-through,---/Inner Write-through non-transient,---/Inner Write-through non-transient,---/Inner Write-through non-transient,Device-GRE memory/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient" newline bitfld.quad 0x00 52.--55. "ATTR6H,Attribute 6 High" "Device memory,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Non-Cacheable,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient" bitfld.quad 0x00 48.--51. "ATTR6L,Attribute 6 Low (Device mem/Normal mem)" "Device-nGnRnE/---,---/Inner Write-through transient,---/Inner Write-through transient,---/Inner Write-through transient,Device-nGnRE/Inner Non-Cacheable,---/Inner Write-back transient,---/Inner Write-back transient,---/Inner Write-back transient,Device-nGRE memory/Inner Write-through,---/Inner Write-through non-transient,---/Inner Write-through non-transient,---/Inner Write-through non-transient,Device-GRE memory/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient" newline bitfld.quad 0x00 44.--47. "ATTR5H,Attribute 5 High" "Device memory,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Non-Cacheable,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient" bitfld.quad 0x00 40.--43. "ATTR5L,Attribute 5 Low (Device mem/Normal mem)" "Device-nGnRnE/---,---/Inner Write-through transient,---/Inner Write-through transient,---/Inner Write-through transient,Device-nGnRE/Inner Non-Cacheable,---/Inner Write-back transient,---/Inner Write-back transient,---/Inner Write-back transient,Device-nGRE memory/Inner Write-through,---/Inner Write-through non-transient,---/Inner Write-through non-transient,---/Inner Write-through non-transient,Device-GRE memory/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient" newline bitfld.quad 0x00 36.--39. "ATTR4H,Attribute 4 High" "Device memory,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Non-Cacheable,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient" bitfld.quad 0x00 32.--35. "ATTR4L,Attribute 4 Low (Device mem/Normal mem)" "Device-nGnRnE/---,---/Inner Write-through transient,---/Inner Write-through transient,---/Inner Write-through transient,Device-nGnRE/Inner Non-Cacheable,---/Inner Write-back transient,---/Inner Write-back transient,---/Inner Write-back transient,Device-nGRE memory/Inner Write-through,---/Inner Write-through non-transient,---/Inner Write-through non-transient,---/Inner Write-through non-transient,Device-GRE memory/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient" newline bitfld.quad 0x00 28.--31. "ATTR3H,Attribute 3 High" "Device memory,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Non-Cacheable,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient" bitfld.quad 0x00 24.--27. "ATTR3L,Attribute 3 Low (Device mem/Normal mem)" "Device-nGnRnE/---,---/Inner Write-through transient,---/Inner Write-through transient,---/Inner Write-through transient,Device-nGnRE/Inner Non-Cacheable,---/Inner Write-back transient,---/Inner Write-back transient,---/Inner Write-back transient,Device-nGRE memory/Inner Write-through,---/Inner Write-through non-transient,---/Inner Write-through non-transient,---/Inner Write-through non-transient,Device-GRE memory/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient" newline bitfld.quad 0x00 20.--23. "ATTR2H,Attribute 2 High" "Device memory,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Non-Cacheable,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient" bitfld.quad 0x00 16.--19. "ATTR2L,Attribute 2 Low (Device mem/Normal mem)" "Device-nGnRnE/---,---/Inner Write-through transient,---/Inner Write-through transient,---/Inner Write-through transient,Device-nGnRE/Inner Non-Cacheable,---/Inner Write-back transient,---/Inner Write-back transient,---/Inner Write-back transient,Device-nGRE memory/Inner Write-through,---/Inner Write-through non-transient,---/Inner Write-through non-transient,---/Inner Write-through non-transient,Device-GRE memory/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient" newline bitfld.quad 0x00 12.--15. "ATTR1H,Attribute 1 High" "Device memory,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Non-Cacheable,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient" bitfld.quad 0x00 8.--11. "ATTR1L,Attribute 1 Low (Device mem/Normal mem)" "Device-nGnRnE/---,---/Inner Write-through transient,---/Inner Write-through transient,---/Inner Write-through transient,Device-nGnRE/Inner Non-Cacheable,---/Inner Write-back transient,---/Inner Write-back transient,---/Inner Write-back transient,Device-nGRE memory/Inner Write-through,---/Inner Write-through non-transient,---/Inner Write-through non-transient,---/Inner Write-through non-transient,Device-GRE memory/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient" newline bitfld.quad 0x00 4.--7. "ATTR0H,Attribute 0 High" "Device memory,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Non-Cacheable,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient" bitfld.quad 0x00 0.--3. "ATTR0L,Attribute 0 Low (Device mem/Normal mem)" "Device-nGnRnE/---,---/Inner Write-through transient,---/Inner Write-through transient,---/Inner Write-through transient,Device-nGnRE/Inner Non-Cacheable,---/Inner Write-back transient,---/Inner Write-back transient,---/Inner Write-back transient,Device-nGRE memory/Inner Write-through,---/Inner Write-through non-transient,---/Inner Write-through non-transient,---/Inner Write-through non-transient,Device-GRE memory/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient" endif group.quad spr:0x30A30++0x00 line.quad 0x00 "AMAIR_EL1,Auxiliary Memory Attribute Indirection Register" group.quad spr:0x35A30++0x00 line.quad 0x00 "AMAIR_EL12,Auxiliary Memory Attribute Indirection Register" group.quad spr:0x34A30++0x00 line.quad 0x00 "AMAIR_EL2,Auxiliary Memory Attribute Indirection Register" group.quad spr:0x36A30++0x00 line.quad 0x00 "AMAIR_EL3,Auxiliary Memory Attribute Indirection Register" tree.end newline group.quad spr:0x34300++0x00 line.quad 0x00 "DACR32_EL2,Domain Access Control Register" bitfld.quad 0x00 30.--31. "D15,Domain 15 access permission" "No access,Client,Reserved,Manager" bitfld.quad 0x00 28.--29. "D14,Domain 14 access permission" "No access,Client,Reserved,Manager" newline bitfld.quad 0x00 26.--27. "D13,Domain 13 access permission" "No access,Client,Reserved,Manager" bitfld.quad 0x00 24.--25. "D12,Domain 12 access permission" "No access,Client,Reserved,Manager" newline bitfld.quad 0x00 22.--23. "D11,Domain 11 access permission" "No access,Client,Reserved,Manager" bitfld.quad 0x00 20.--21. "D10,Domain 10 access permission" "No access,Client,Reserved,Manager" newline bitfld.quad 0x00 18.--19. "D9,Domain 9 access permission" "No access,Client,Reserved,Manager" bitfld.quad 0x00 16.--17. "D8,Domain 8 access permission" "No access,Client,Reserved,Manager" newline bitfld.quad 0x00 14.--15. "D7,Domain 7 access permission" "No access,Client,Reserved,Manager" bitfld.quad 0x00 12.--13. "D6,Domain 6 access permission" "No access,Client,Reserved,Manager" newline bitfld.quad 0x00 10.--11. "D5,Domain 5 access permission" "No access,Client,Reserved,Manager" bitfld.quad 0x00 8.--9. "D4,Domain 4 access permission" "No access,Client,Reserved,Manager" newline bitfld.quad 0x00 6.--7. "D3,Domain 3 access permission" "No access,Client,Reserved,Manager" bitfld.quad 0x00 4.--5. "D2,Domain 2 access permission" "No access,Client,Reserved,Manager" newline bitfld.quad 0x00 2.--3. "D1,Domain 1 access permission" "No access,Client,Reserved,Manager" bitfld.quad 0x00 0.--1. "D0,Domain 0 access permission" "No access,Client,Reserved,Manager" tree.end tree "Virtualization Extensions" group.quad spr:0x34111++0x00 line.quad 0x00 "MDCR_EL2,Monitor Debug Configuration Register" bitfld.quad 0x00 17. "HPMD,Hypervisor performance monitors disable" "No,Yes" newline bitfld.quad 0x00 14. "TPMS,Trap Performance Monitor Sampling" "No trap,Trap" newline bitfld.quad 0x00 11. "TDRA,Trap valid EL1 and EL0 access to debug ROM address registers to EL2" "No trap,Trap" bitfld.quad 0x00 10. "TDOSA,Trap valid accesses to OS-related debug registers to EL2" "No trap,Trap" bitfld.quad 0x00 9. "TDA,Trap valid Non-secure accesses to Debug registers to EL2" "No trap,Trap" newline bitfld.quad 0x00 8. "TDE,Route debug exceptions from Non-secure EL1 and EL0 to EL2" "Disabled,Enabled" bitfld.quad 0x00 7. "HPME,Hypervisor Performance Monitors Enable" "Disabled,Enabled" bitfld.quad 0x00 6. "TPM,Trap Non-secure EL0 and EL1 accesses to Performance Monitors registers that are not UNALLOCATED to EL2" "No trap,Trap" newline bitfld.quad 0x00 5. "TPMCR,Trap Non-secure EL0 and EL1 accesses to PMCR_EL0 to EL2" "No trap,Trap" bitfld.quad 0x00 0.--4. "HPMN,Defines the number of Performance Monitors counters accessible from non-secure EL0/EL1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.quad spr:0x36131++0x00 line.quad 0x00 "MDCR_EL3,Monitor Debug Configuration Register" bitfld.quad 0x00 21. "EPMAD,External debugger to Performance Monitor registers access disable" "No,Yes" bitfld.quad 0x00 20. "EDAD,External debugger access to breakpoint and watchpoint registers disabled" "No,Yes" bitfld.quad 0x00 17. "SPME,Secure performance monitors enable" "Disabled,Enabled" newline bitfld.quad 0x00 16. "SDD,Secure self-hosted invasive debug disable" "No,Yes" newline bitfld.quad 0x00 14.--15. "SPD32,AArch32 secure privileged debug" "Legacy mode,Reserved,Disabled,Enabled" bitfld.quad 0x00 10. "TDOSA,Trap valid accesses to OS-related debug registers to EL3" "No trap,Trap" bitfld.quad 0x00 9. "TDA,Trap valid Non-secure accesses to Debug registers to EL3" "No trap,Trap" newline bitfld.quad 0x00 6. "TPM,Trap Non-secure EL0/EL1/EL2 accesses to Performance Monitors registers that are not UNALLOCATED or trapped to a lower exception level to EL3" "No trap,Trap" rgroup.quad spr:0x30012++0x00 line.quad 0x00 "ID_DFR0_EL1,Debug Feature Register" bitfld.quad 0x00 24.--27. "PMM,Performance Monitor Model Support" "Reserved,Reserved,Reserved,Reserved,Supported/16-bit evtCount,?..." bitfld.quad 0x00 20.--23. "MDM_MM,Memory-mapped Debug Model for M profile processors Support" "Not supported,?..." bitfld.quad 0x00 16.--19. "TM_MM,Trace Model (Memory-Mapped) Support" "Reserved,Supported,?..." newline bitfld.quad 0x00 12.--15. "CTM_CB,Coprocessor-Based Trace Debug Model Support" "Not supported,?..." bitfld.quad 0x00 4.--7. "SDM_CB,Secure Debug Model (Coprocessor) Support" "Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Support v8.2,?..." bitfld.quad 0x00 0.--3. "CDM_CB,Coprocessor Debug Model Support" "Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Support v8.2,?..." tree.end tree "Cache Control and Configuration" rgroup.quad spr:0x30F00++0x00 line.quad 0x00 "CPUCFR_EL1, CPU Configuration Register (EL1)" bitfld.quad 0x00 2. "SCU,Indicates whether the SCU is present or not" "Present,?..." bitfld.quad 0x00 0.--1. "ECC,Indicates whether ECC is present or not" "Not present,Present,?..." if (CORENAME()=="CORTEXA75") group.quad spr:0x30F27++0x00 line.quad 0x00 "CPUPWRCTLR_EL1,Power Control Register (EL1)" bitfld.quad 0x00 7.--9. "WFE_RET_CTRL,CPU WFE retention control. Specifies the number of Architectural Timer ticks required before retention entry" "Disabled,2 AT ticks,8 AT ticks,32 AT ticks,64 AT ticks,128 AT ticks,256 AT ticks,512 AT ticks" bitfld.quad 0x00 4.--6. "WFI_RET_CTRL,CPU WFI retention control. Specifies the number of Architectural Timer ticks required before retention entry" "Disabled,2 AT ticks,8 AT ticks,32 AT ticks,64 AT ticks,128 AT ticks,256 AT ticks,512 AT ticks" bitfld.quad 0x00 0. "CORE_PWRDN_EN,Indicates to the power controller if the CPU wants to power down when it enters WFI state" "Not requested,Requested" elif (CORENAME()=="CORTEXA55") group.quad spr:0x30F27++0x00 line.quad 0x00 "CPUPWRCTLR_EL1,Power Control Register (EL1)" bitfld.quad 0x00 10.--12. "SIMD_RET_CTRL,Advanced SIMD and floating-point retention control. Specifies the number of Architectural Timer ticks required before retention entry" "Disabled,2 AT ticks,8 AT ticks,32 AT ticks,64 AT ticks,128 AT ticks,256 AT ticks,512 AT ticks" bitfld.quad 0x00 7.--9. "WFE_RET_CTRL,CPU WFE retention control. Specifies the number of Architectural Timer ticks required before retention entry" "Disabled,2 AT ticks,8 AT ticks,32 AT ticks,64 AT ticks,128 AT ticks,256 AT ticks,512 AT ticks" bitfld.quad 0x00 4.--6. "WFI_RET_CTRL,CPU WFI retention control. Specifies the number of Architectural Timer ticks required before retention entry" "Disabled,2 AT ticks,8 AT ticks,32 AT ticks,64 AT ticks,128 AT ticks,256 AT ticks,512 AT ticks" newline bitfld.quad 0x00 0. "CORE_PWRDN_EN,Indicates to the power controller if the CPU wants to power down when it enters WFI state" "Not requested,Requested" endif rgroup.quad spr:0x33001++0x00 line.quad 0x00 "CTR_EL0,Cache Type Register" bitfld.quad 0x0 24.--27. "CWG,Cache writeback granule size" "Reserved,Reserved,Reserved,Reserved,16 words,?..." bitfld.quad 0x0 20.--23. "ERG,Exclusives reservation granule size" "Reserved,Reserved,Reserved,Reserved,16 words,?..." bitfld.quad 0x0 16.--19. "DMINLINE,Smallest data cache line size" "Reserved,Reserved,Reserved,Reserved,16 words,?..." newline bitfld.quad 0x0 14.--15. "VIPT,Instruction cache policy" "Reserved,Reserved,VIPT,?..." bitfld.quad 0x0 0.--3. "IMINLINE,I-Cache Minimum Line Size" "Reserved,Reserved,Reserved,Reserved,16 words,?..." if (((per.q(spr:0x32000))&0xE)==(0x02||0x04)) group.quad spr:0x32000++0x00 line.quad 0x00 "CSSELR_EL1,Cache Size Selection Register" bitfld.quad 0x00 1.--3. "LEVEL,Cache level of required cache" "Level 1,Level 2,Level 3,?..." bitfld.quad 0x00 0. "IND,Instruction/Not Data" "Data/Unified,?..." else group.quad spr:0x32000++0x00 line.quad 0x00 "CSSELR_EL1,Cache Size Selection Register" bitfld.quad 0x00 1.--3. "LEVEL,Cache level of required cache" "Level 1,Level 2,Level 3,?..." bitfld.quad 0x00 0. "IND,Instruction/Not Data" "Data/Unified,Instruction" endif rgroup.quad spr:0x31000++0x00 line.quad 0x00 "CCSIDR_EL1,Cache Size and ID register" bitfld.quad 0x00 31. "WT,Indicates whether the selected cache level supports Write-Through" "Not Supported,?..." bitfld.quad 0x00 30. "WB,Indicates whether the selected cache level supports Write-Back" "Not Supported,Supported" bitfld.quad 0x00 29. "RA,Indicates whether the selected cache level supports read-allocation" "Not Supported,Supported" newline bitfld.quad 0x00 28. "WA,Indicates whether the selected cache level supports write-allocation" "Not Supported,Supported" hexmask.quad.word 0x00 13.--27. 1. 1. "SETS,Number of Sets" hexmask.quad.word 0x00 3.--12. 1. 1. "ASSOC,Associativity" newline bitfld.quad 0x00 0.--2. "LSIZE,Line Size" "Reserved,Reserved,64 bytes,?..." if (CORENAME()=="CORTEXA75") rgroup.quad spr:0x31001++0x00 line.quad 0x00 "CLIDR_EL1,Cache Level ID register" bitfld.quad 0x00 30.--32. "ICB,Inner cache boundary" "Reserved,Reserved,L2 highest,L3 highest,?..." bitfld.quad 0x00 27.--29. "LOUU,Level of Unification Uniprocessor" "Not required,?..." bitfld.quad 0x00 24.--26. "LOC,Level of Coherency" "Reserved,Reserved,No L3 cache,L3 cache,?..." newline bitfld.quad 0x00 21.--23. "LOUIS,Level of Unification Inner Shareable" "No cache,?..." bitfld.quad 0x00 6.--8. "CTYPE3,Cache type for levels 3" "No cache,Reserved,Reserved,Reserved,Unified,?..." bitfld.quad 0x00 3.--5. "CTYPE2,Cache type for levels 2" "Reserved,Reserved,Reserved,Reserved,Unified,?..." newline bitfld.quad 0x00 0.--2. "CTYPE1,Cache type for levels 1" "Reserved,Reserved,Reserved,Separate,?..." elif (CORENAME()=="CORTEXA55") rgroup.quad spr:0x31001++0x00 line.quad 0x00 "CLIDR_EL1,Cache Level ID register" bitfld.quad 0x00 30.--32. "ICB,Inner cache boundary" "Reserved,L1 highest,L2 highest,L3 highest,?..." bitfld.quad 0x00 27.--29. "LOUU,Level of Unification Uniprocessor" "Not required,?..." bitfld.quad 0x00 24.--26. "LOC,Level of Coherency" "Reserved,No cache,L2 or L3 cache,L2 and L3 cache,?..." newline bitfld.quad 0x00 21.--23. "LOUIS,Level of Unification Inner Shareable" "Not required,?..." bitfld.quad 0x00 6.--8. "CTYPE3,Cache type for levels 3" "No cache,Reserved,Reserved,Reserved,L2 and L3 cache,?..." bitfld.quad 0x00 3.--5. "CTYPE2,Cache type for levels 2" "No cache,Reserved,Reserved,Reserved,Unified,?..." newline bitfld.quad 0x00 0.--2. "CTYPE1,Cache type for levels 1" "Reserved,Reserved,Reserved,Separate,?..." endif tree "Level 1 memory system" rgroup.quad spr:0x36F00++0x00 line.quad 0x00 "CDBGDR0_EL3,Data Register 0" rgroup.quad spr:0x36F01++0x00 line.quad 0x00 "CDBGDR1_EL3,Data Register 1" rgroup.quad spr:0x36F02++0x00 line.quad 0x00 "CDBGDR2_EL3,Data Register 2" wgroup.quad spr:0x16F20++0x00 line.quad 0x00 "CDBGDCT_EL3,Data Cache Tag Read Operation Register" wgroup.quad spr:0x16F21++0x00 line.quad 0x00 "CDBGICT_EL3,Instruction Cache Tag Read Operation Register" wgroup.quad spr:0x16F22++0x00 line.quad 0x00 "CDBGTT_EL3,TLB Tag Read Operation Register" wgroup.quad spr:0x16F40++0x00 line.quad 0x00 "CDBGDCD_EL3,Data Cache Data Read Operation Register" wgroup.quad spr:0x16F41++0x00 line.quad 0x00 "CDBGICD_EL3,Instruction Cache Data Read Operation Register" wgroup.quad spr:0x16F42++0x00 line.quad 0x00 "CDBGTD_EL3,TLB Data Read Operation Register" tree.end tree.end tree "System Performance Monitor" group.quad spr:0x339C0++0x00 line.quad 0x00 "PMCR_EL0,Performance Monitors Control Register" hexmask.quad.byte 0x00 24.--31. 1. "IMP,Implementer code" hexmask.quad.byte 0x00 16.--23. 1. "IDCODE,Identification code" bitfld.quad 0x00 11.--15. "N,Number of counters implemented" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.quad 0x00 6. "LC,Long cycle counter enable" "Disabled,Enabled" newline bitfld.quad 0x00 5. "DP,Disable CCNT when event counting prohibited" "No,Yes" bitfld.quad 0x00 4. "X,Export of events Enable" "Disabled,Enabled" bitfld.quad 0x00 3. "D,Clock Divider" "Every cycle,64th cycle" bitfld.quad 0x00 2. "C,Clock Counter Reset" "No reset,Reset" newline bitfld.quad 0x00 1. "P,Performance Counter Reset" "No reset,Reset" bitfld.quad 0x00 0. "E,All Counters Enable" "Disabled,Enabled" group.quad spr:0x339C1++0x00 line.quad 0x00 "PMCNTENSET_EL0,Count Enable Set register" bitfld.quad 0x00 31. "C,Enables the cycle counter register" "Disabled,Enabled" newline bitfld.quad 0x00 5. "P5,Event counter PMN 5 enable bit" "Disabled,Enabled" bitfld.quad 0x00 4. "P4,Event counter PMN 4 enable bit" "Disabled,Enabled" bitfld.quad 0x00 3. "P3,Event counter PMN 3 enable bit" "Disabled,Enabled" newline bitfld.quad 0x00 2. "P2,Event counter PMN 2 enable bit" "Disabled,Enabled" bitfld.quad 0x00 1. "P1,Event counter PMN 1 enable bit" "Disabled,Enabled" bitfld.quad 0x00 0. "P0,Event counter PMN 0 enable bit" "Disabled,Enabled" group.quad spr:0x339C2++0x00 line.quad 0x00 "PMCNTENCLR_EL0,Count Enable Clear register" bitfld.quad 0x00 31. "C,Disables the cycle counter register" "Disabled,Enabled" newline bitfld.quad 0x00 5. "P5,PMN5 overflow" "No overflow,Overflow" bitfld.quad 0x00 4. "P4,PMN4 overflow" "No overflow,Overflow" bitfld.quad 0x00 3. "P3,PMN3 overflow" "No overflow,Overflow" newline bitfld.quad 0x00 2. "P2,PMN2 overflow" "No overflow,Overflow" bitfld.quad 0x00 1. "P1,PMN1 overflow" "No overflow,Overflow" bitfld.quad 0x00 0. "P0,PMN0 overflow" "No overflow,Overflow" group.quad spr:0x339C3++0x00 line.quad 0x00 "PMOVSCLR_EL0,Overflow Status Flags Clear register" eventfld.quad 0x00 31. "C,PMCCNTR overflow" "No overflow,Overflow" newline eventfld.quad 0x00 5. "P5,PMN5 overflow" "No overflow,Overflow" eventfld.quad 0x00 4. "P4,PMN4 overflow" "No overflow,Overflow" eventfld.quad 0x00 3. "P3,PMN3 overflow" "No overflow,Overflow" newline eventfld.quad 0x00 2. "P2,PMN2 overflow" "No overflow,Overflow" eventfld.quad 0x00 1. "P1,PMN1 overflow" "No overflow,Overflow" eventfld.quad 0x00 0. "P0,PMN0 overflow" "No overflow,Overflow" wgroup.quad spr:0x339C4++0x00 line.quad 0x00 "PMSWINC_EL0,Software Increment register" bitfld.quad 0x00 5. "P5,PMN5 software increment" "Disabled,Enabled" bitfld.quad 0x00 4. "P4,PMN4 software increment" "Disabled,Enabled" bitfld.quad 0x00 3. "P3,PMN3 software increment" "Disabled,Enabled" newline bitfld.quad 0x00 2. "P2,PMN2 software increment" "Disabled,Enabled" bitfld.quad 0x00 1. "P1,PMN1 software increment" "Disabled,Enabled" bitfld.quad 0x00 0. "P0,PMN0 software increment" "Disabled,Enabled" group.quad spr:0x339C5++0x00 line.quad 0x00 "PMSELR_EL0,Event Counter Selection Register" bitfld.quad 0x00 0.--4. "SEL,Current event counter select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline tree.open "Common Event Identification Registers" rgroup.quad spr:0x339C6++0x00 line.quad 0x00 "PMCEID0_EL0,Common Event Identification register" bitfld.quad 0x00 31. "L1D_CACHE_ALLOCATE,Level 1 data cache allocate" "Not implemented,Implemented" bitfld.quad 0x00 30. "CHAIN,Chain" "Not implemented,Implemented" bitfld.quad 0x00 29. "BUS_CYCLES,Bus cycle" "Not implemented,Implemented" newline bitfld.quad 0x00 28. "TTBR_WRITE_RETIRED,TTBR write retired" "Not implemented,Implemented" bitfld.quad 0x00 27. "INST_SPEC,Instruction speculatively executed" "Not implemented,Implemented" bitfld.quad 0x00 26. "MEMORY_ERROR,Local memory error" "Not implemented,Implemented" newline bitfld.quad 0x00 25. "BUS_ACCESS,Bus access" "Not implemented,Implemented" bitfld.quad 0x00 24. "L2D_CACHE_WB,Level 2 data cache write-back" "Not implemented,Implemented" bitfld.quad 0x00 23. "L2D_CACHE_REFILL,Level 2 data cache refill" "Not implemented,Implemented" newline bitfld.quad 0x00 22. "L2D_CACHE,Level 2 data cache access" "Not implemented,Implemented" bitfld.quad 0x00 21. "L1D_CACHE_WB,Level 1 data cache write-back" "Not implemented,Implemented" bitfld.quad 0x00 20. "L1I_CACHE,Level 1 instruction cache access" "Not implemented,Implemented" newline bitfld.quad 0x00 19. "MEM_ACCESS,Data memory access" "Not implemented,Implemented" bitfld.quad 0x00 18. "BR_PRED,Predictable branch speculatively executed" "Not implemented,Implemented" bitfld.quad 0x00 17. "CPU_CYCLES,CPU Cycle" "Not implemented,Implemented" newline bitfld.quad 0x00 16. "BR_MIS_PRED,Mispredicted or not predicted branch speculatively executed" "Not implemented,Implemented" bitfld.quad 0x00 15. "UNALIGNED_LDST_RETIRED,UNALIGNED_LDST_RETIRED" "Not implemented,Implemented" bitfld.quad 0x00 14. "BR_RETURN_RETIRED,Instruction architecturally executed condition check pass procedure return" "Not implemented,Implemented" newline bitfld.quad 0x00 13. "BR_IMMED_RETIRED,Instruction architecturally executed immediate branch" "Not implemented,Implemented" bitfld.quad 0x00 12. "PC_WRITE_RETIRED,Instruction architecturally executed condition check pass software change of the PC" "Not implemented,Implemented" bitfld.quad 0x00 11. "CID_WRITE_RETIRED,Instruction architecturally executed condition check pass write to CONTEXTIDR" "Not implemented,Implemented" newline bitfld.quad 0x00 10. "EXC_RETURN,Instruction architecturally executed condition check pass exception return" "Not implemented,Implemented" bitfld.quad 0x00 9. "EXC_TAKEN,Exception taken" "Not implemented,Implemented" bitfld.quad 0x00 8. "INST_RETIRED,Instruction architecturally executed" "Not implemented,Implemented" newline bitfld.quad 0x00 7. "ST_RETIRED,Instruction architecturally executed condition check pass store" "Not implemented,Implemented" bitfld.quad 0x00 6. "LD_RETIRED,Instruction architecturally executed condition check pass load" "Not implemented,Implemented" bitfld.quad 0x00 5. "L1D_TLB_REFILL,Level 1 data TLB refill" "Not implemented,Implemented" newline bitfld.quad 0x00 4. "L1D_CACHE,Level 1 data cache access" "Not implemented,Implemented" bitfld.quad 0x00 3. "L1D_CACHE_REFILL,Level 1 data cache refill" "Not implemented,Implemented" bitfld.quad 0x00 2. "L1I_TLB_REFILL,Level 1 instruction TLB refill" "Not implemented,Implemented" newline bitfld.quad 0x00 1. "L1I_CACHE_REFILL,Level 1 instruction cache refill" "Not implemented,Implemented" bitfld.quad 0x00 0. "SW_INCR,Instruction architecturally executed condition check pass software increment" "Not implemented,Implemented" if (CORENAME()=="CORTEXA75") rgroup.quad spr:0x339C7++0x00 line.quad 0x00 "PMCEID1_EL0,Common Event Identification register" bitfld.quad 0x00 24. "REMOTE_ACCESS,Access to another socket in a multi-socket system" "Not implemented,Implemented" bitfld.quad 0x00 23. "LL_CACHE_MISS_RD,Last Level cache miss read" "Not implemented,Implemented" bitfld.quad 0x00 22. "LL_CACHE_RD,Last Level cache access read" "Not implemented,Implemented" newline bitfld.quad 0x00 21. "ITLB_WALK,Access to instruction TLB that caused a page table walk" "Not implemented,Implemented" bitfld.quad 0x00 20. "DTLB_WALK,Access to data TLB that caused a page table walk" "Not implemented,Implemented" bitfld.quad 0x00 16. "L2I_TLB,Attributable Level 2 instruction TLB access" "Not implemented,Implemented" newline bitfld.quad 0x00 15. "L2D_TLB,Attributable Level 2 data or unified TLB access" "Not implemented,Implemented" bitfld.quad 0x00 13. "L2D_TLB_REFILL,Attributable Level 2 data or unified TLB refill" "Not implemented,Implemented" bitfld.quad 0x00 11. "L3D_CACHE,Attributable Level 3 data or unified cache access" "Not implemented,Implemented" newline bitfld.quad 0x00 10. "L3D_CACHE_REFILL,Attributable Level 3 data or unified cache refill" "Not implemented,Implemented" bitfld.quad 0x00 9. "L3D_CACHE_ALLOCATE,Attributable Level 3 data or unified cache allocation without refill" "Not implemented,Implemented" bitfld.quad 0x00 6. "L1I_TLB,Level 1 instruction TLB access" "Not implemented,Implemented" newline bitfld.quad 0x00 5. "L1D_TLB,Level 1 data or unified TLB access" "Not implemented,Implemented" bitfld.quad 0x00 4. "STALL_BACKEND,No operation issued due to backend" "Not implemented,Implemented" bitfld.quad 0x00 3. "STALL_FRONTEND,No operation issued due to the frontend" "Not implemented,Implemented" newline bitfld.quad 0x00 1. "BR_RETIRED,Instruction architecturally executed branch" "Not implemented,Implemented" bitfld.quad 0x00 0. "L2D_CACHE_ALLOCATE,Level 2 data cache allocate" "Not implemented,Implemented" elif (CORENAME()=="CORTEXA55") rgroup.quad spr:0x339C7++0x00 line.quad 0x00 "PMCEID1_EL0,Common Event Identification register" bitfld.quad 0x00 23. "LL_CACHE_MISS_RD,Last Level cache miss read" "Not implemented,Implemented" bitfld.quad 0x00 22. "LL_CACHE_RD,Last Level cache access read" "Not implemented,Implemented" bitfld.quad 0x00 21. "ITLB_WALK,Access to instruction TLB that caused a page table walk" "Not implemented,Implemented" newline bitfld.quad 0x00 20. "DTLB_WALK,Access to data TLB that caused a page table walk" "Not implemented,Implemented" bitfld.quad 0x00 17. "REMOTE_ACCESS,Access to another socket in a multi-socket system" "Not implemented,Implemented" bitfld.quad 0x00 16. "L2I_TLB,Attributable Level 2 instruction TLB access" "Not implemented,Implemented" newline bitfld.quad 0x00 15. "L2D_TLB,Attributable Level 2 data or unified TLB access" "Not implemented,Implemented" bitfld.quad 0x00 14. "L2I_TLB_REFILL,Attributable Level 2 instruction TLB refill" "Not implemented,Implemented" bitfld.quad 0x00 13. "L2D_TLB_REFILL,Attributable Level 2 data or unified TLB refill" "Not implemented,Implemented" newline bitfld.quad 0x00 12. "L3D_CACHE_WB,Attributable Level 3 data or unified cache write-back" "Not implemented,Implemented" bitfld.quad 0x00 11. "L3D_CACHE,Attributable Level 3 data or unified cache access" "Not implemented,Implemented" bitfld.quad 0x00 10. "L3D_CACHE_REFILL,Attributable Level 3 data or unified cache refill" "Not implemented,Implemented" newline bitfld.quad 0x00 9. "L3D_CACHE_ALLOCATE,Attributable Level 3 data or unified cache allocation without refill" "Not implemented,Implemented" bitfld.quad 0x00 8. "L2I_CACHE_REFILL,Attributable Level 2 instruction cache refill" "Not implemented,Implemented" bitfld.quad 0x00 7. "L2I_CACHE,Attributable Level 2 instruction cache access" "Not implemented,Implemented" newline bitfld.quad 0x00 6. "L1I_TLB,Level 1 instruction TLB access" "Not implemented,Implemented" bitfld.quad 0x00 5. "L1D_TLB,Level 1 data or unified TLB access" "Not implemented,Implemented" bitfld.quad 0x00 4. "STALL_BACKEND,No operation issued due to backend" "Not implemented,Implemented" newline bitfld.quad 0x00 3. "STALL_FRONTEND,No operation issued due to the frontend" "Not implemented,Implemented" bitfld.quad 0x00 2. "BR_MIS_PRED_RETIRED,Instruction architecturally executed mispredicted branch" "Not implemented,Implemented" bitfld.quad 0x00 1. "BR_RETIRED,Instruction architecturally executed branch" "Not implemented,Implemented" newline bitfld.quad 0x00 0. "L2D_CACHE_ALLOCATE,Level 2 data cache allocate" "Not implemented,Implemented" endif tree.end newline group.quad spr:0x339D0++0x00 line.quad 0x00 "PMCCNTR_EL0,Performance Monitors Cycle Counter" group.quad spr:0x339D1++0x00 line.quad 0x00 "PMXEVTYPER_EL0,Performance Monitors Selected Event Type Register" group.quad spr:0x339D2++0x00 line.quad 0x00 "PMXEVCNTR_EL0,Selected Event Counter Register" group.quad spr:0x339E0++0x00 line.quad 0x00 "PMUSERENR_EL0,User Enable Register" bitfld.quad 0x00 3. "ER,Event counter read enable" "Disabled,Enabled" bitfld.quad 0x00 2. "CR,Cycle counter read enable" "Disabled,Enabled" newline bitfld.quad 0x00 1. "SW,Software Increment write enable" "Disabled,Enabled" bitfld.quad 0x00 0. "EN,EL0 access enable bit" "Disabled,Enabled" group.quad spr:0x309E1++0x00 line.quad 0x00 "PMINTENSET_EL1,Interrupt Enable Set register" bitfld.quad 0x00 31. "C,CCNT Overflow Interrupt Request Enable" "Disabled,Enabled" newline bitfld.quad 0x00 5. "P5,PMCNT5 Overflow Interrupt Enable" "Disabled,Enabled" bitfld.quad 0x00 4. "P4,PMCNT4 Overflow Interrupt Enable" "Disabled,Enabled" bitfld.quad 0x00 3. "P3,PMCNT3 Overflow Interrupt Enable" "Disabled,Enabled" newline bitfld.quad 0x00 2. "P2,PMCNT2 Overflow Interrupt Enable" "Disabled,Enabled" bitfld.quad 0x00 1. "P1,PMCNT1 Overflow Interrupt Enable" "Disabled,Enabled" bitfld.quad 0x00 0. "P0,PMCNT0 Overflow Interrupt Enable" "Disabled,Enabled" group.quad spr:0x309E2++0x00 line.quad 0x00 "PMINTENCLR_EL1,Interrupt Enable Clear register" eventfld.quad 0x00 31. "C,CCNT Overflow Interrupt Request Enable" "Disabled,Enabled" newline eventfld.quad 0x00 5. "P5,PMCNT5 Overflow Interrupt Enable" "Disabled,Enabled" eventfld.quad 0x00 4. "P4,PMCNT4 Overflow Interrupt Enable" "Disabled,Enabled" eventfld.quad 0x00 3. "P3,PMCNT3 Overflow Interrupt Enable" "Disabled,Enabled" newline eventfld.quad 0x00 2. "P2,PMCNT2 Overflow Interrupt Enable" "Disabled,Enabled" eventfld.quad 0x00 1. "P1,PMCNT1 Overflow Interrupt Enable" "Disabled,Enabled" eventfld.quad 0x00 0. "P0,PMCNT0 Overflow Interrupt Enable" "Disabled,Enabled" group.quad spr:0x339E3++0x00 line.quad 0x00 "PMOVSSET_EL0,Overflow Status Flags Set register" bitfld.quad 0x00 31. "C,PMCCNTR overflow" "No overflow,Overflow" newline bitfld.quad 0x00 5. "P5,PMN5 Overflow" "No overflow,Overflow" bitfld.quad 0x00 4. "P4,PMN4 Overflow" "No overflow,Overflow" bitfld.quad 0x00 3. "P3,PMN3 Overflow" "No overflow,Overflow" newline bitfld.quad 0x00 2. "P2,PMN2 Overflow" "No overflow,Overflow" bitfld.quad 0x00 1. "P1,PMN1 Overflow" "No overflow,Overflow" bitfld.quad 0x00 0. "P0,PMN0 Overflow" "No overflow,Overflow" group.quad spr:(0x33E80+0x0)++0x00 line.quad 0x00 "PMEVCNTR0_EL0,Event Counter Register" group.quad spr:(0x33E80+0x1)++0x00 line.quad 0x00 "PMEVCNTR1_EL0,Event Counter Register" group.quad spr:(0x33E80+0x2)++0x00 line.quad 0x00 "PMEVCNTR2_EL0,Event Counter Register" group.quad spr:(0x33E80+0x3)++0x00 line.quad 0x00 "PMEVCNTR3_EL0,Event Counter Register" group.quad spr:(0x33E80+0x4)++0x00 line.quad 0x00 "PMEVCNTR4_EL0,Event Counter Register" group.quad spr:(0x33E80+0x5)++0x00 line.quad 0x00 "PMEVCNTR5_EL0,Event Counter Register" group.quad spr:(0x33EC0+0x0)++0x00 line.quad 0x00 "PMEVTYPER0_EL0,Event Counter Register" bitfld.quad 0x00 31. "P,Count events in EL1" "Disabled,Enabled" bitfld.quad 0x00 30. "U,Count events in EL0" "Disabled,Enabled" bitfld.quad 0x00 29. "NSK,Count events in non-secure EL1" "Disabled,Enabled" newline bitfld.quad 0x00 28. "NSU,Count events in non-secure EL0" "Disabled,Enabled" bitfld.quad 0x00 27. "NSH,Count events in non-secure EL2" "Disabled,Enabled" bitfld.quad 0x00 26. "M,Count events in secure EL3" "Disabled,Enabled" newline hexmask.quad.word 0x00 0.--15. 1. "EVTCOUNT,Event number" group.quad spr:(0x33EC0+0x1)++0x00 line.quad 0x00 "PMEVTYPER1_EL0,Event Counter Register" bitfld.quad 0x00 31. "P,Count events in EL1" "Disabled,Enabled" bitfld.quad 0x00 30. "U,Count events in EL0" "Disabled,Enabled" bitfld.quad 0x00 29. "NSK,Count events in non-secure EL1" "Disabled,Enabled" newline bitfld.quad 0x00 28. "NSU,Count events in non-secure EL0" "Disabled,Enabled" bitfld.quad 0x00 27. "NSH,Count events in non-secure EL2" "Disabled,Enabled" bitfld.quad 0x00 26. "M,Count events in secure EL3" "Disabled,Enabled" newline hexmask.quad.word 0x00 0.--15. 1. "EVTCOUNT,Event number" group.quad spr:(0x33EC0+0x2)++0x00 line.quad 0x00 "PMEVTYPER2_EL0,Event Counter Register" bitfld.quad 0x00 31. "P,Count events in EL1" "Disabled,Enabled" bitfld.quad 0x00 30. "U,Count events in EL0" "Disabled,Enabled" bitfld.quad 0x00 29. "NSK,Count events in non-secure EL1" "Disabled,Enabled" newline bitfld.quad 0x00 28. "NSU,Count events in non-secure EL0" "Disabled,Enabled" bitfld.quad 0x00 27. "NSH,Count events in non-secure EL2" "Disabled,Enabled" bitfld.quad 0x00 26. "M,Count events in secure EL3" "Disabled,Enabled" newline hexmask.quad.word 0x00 0.--15. 1. "EVTCOUNT,Event number" group.quad spr:(0x33EC0+0x3)++0x00 line.quad 0x00 "PMEVTYPER3_EL0,Event Counter Register" bitfld.quad 0x00 31. "P,Count events in EL1" "Disabled,Enabled" bitfld.quad 0x00 30. "U,Count events in EL0" "Disabled,Enabled" bitfld.quad 0x00 29. "NSK,Count events in non-secure EL1" "Disabled,Enabled" newline bitfld.quad 0x00 28. "NSU,Count events in non-secure EL0" "Disabled,Enabled" bitfld.quad 0x00 27. "NSH,Count events in non-secure EL2" "Disabled,Enabled" bitfld.quad 0x00 26. "M,Count events in secure EL3" "Disabled,Enabled" newline hexmask.quad.word 0x00 0.--15. 1. "EVTCOUNT,Event number" group.quad spr:(0x33EC0+0x4)++0x00 line.quad 0x00 "PMEVTYPER4_EL0,Event Counter Register" bitfld.quad 0x00 31. "P,Count events in EL1" "Disabled,Enabled" bitfld.quad 0x00 30. "U,Count events in EL0" "Disabled,Enabled" bitfld.quad 0x00 29. "NSK,Count events in non-secure EL1" "Disabled,Enabled" newline bitfld.quad 0x00 28. "NSU,Count events in non-secure EL0" "Disabled,Enabled" bitfld.quad 0x00 27. "NSH,Count events in non-secure EL2" "Disabled,Enabled" bitfld.quad 0x00 26. "M,Count events in secure EL3" "Disabled,Enabled" newline hexmask.quad.word 0x00 0.--15. 1. "EVTCOUNT,Event number" group.quad spr:(0x33EC0+0x5)++0x00 line.quad 0x00 "PMEVTYPER5_EL0,Event Counter Register" bitfld.quad 0x00 31. "P,Count events in EL1" "Disabled,Enabled" bitfld.quad 0x00 30. "U,Count events in EL0" "Disabled,Enabled" bitfld.quad 0x00 29. "NSK,Count events in non-secure EL1" "Disabled,Enabled" newline bitfld.quad 0x00 28. "NSU,Count events in non-secure EL0" "Disabled,Enabled" bitfld.quad 0x00 27. "NSH,Count events in non-secure EL2" "Disabled,Enabled" bitfld.quad 0x00 26. "M,Count events in secure EL3" "Disabled,Enabled" newline hexmask.quad.word 0x00 0.--15. 1. "EVTCOUNT,Event number" group.quad spr:0x33EF7++0x00 line.quad 0x00 "PMCCFILTR_EL0,Event Type and Cycle Counter Filter Register" bitfld.quad 0x00 31. "P,Count events in EL1" "Disabled,Enabled" bitfld.quad 0x00 30. "U,Count events in EL0" "Disabled,Enabled" bitfld.quad 0x00 29. "NSK,Count events in non-secure EL1" "Disabled,Enabled" newline bitfld.quad 0x00 28. "NSU,Count events in non-secure EL0" "Disabled,Enabled" bitfld.quad 0x00 27. "NSH,Count events in non-secure EL2" "Disabled,Enabled" bitfld.quad 0x00 26. "M,Count events in secure EL3" "Disabled,Enabled" newline hexmask.quad.word 0x00 0.--15. 1. "EVTCOUNT,Event number" tree.end tree "System Timer Registers" group.quad spr:0x33E00++0x00 line.quad 0x00 "CNTFRQ_EL0,Counter-timer Frequency register" rgroup.quad spr:0x33E01++0x00 line.quad 0x00 "CNTPCT_EL0,Counter-timer Physical Count register" rgroup.quad spr:0x33E02++0x00 line.quad 0x00 "CNTVCT_EL0,Counter-timer Virtual Count register" group.quad spr:0x34E03++0x00 line.quad 0x00 "CNTVOFF_EL2,Counter-timer Virtual Offset register" if (((per.q(spr:0x34110))&0x408000000)==0x408000000) group.quad spr:0x30E10++0x00 line.quad 0x00 "CNTKCTL_EL1,Counter-timer Kernel Control register" bitfld.quad 0x00 4.--7. "EVNTI,Selects which bit of CNTVCT is the trigger for the event stream generated from that counter, when that stream is enabled" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.quad 0x00 3. "EVNTDIR,Controls which transition of the CNTVCT trigger bit defined by EVNTI, generates an event when the event stream is enabled" "0 to 1,1 to 0" bitfld.quad 0x00 2. "EVNTEN,Enables the generation of an event stream from the corresponding counter" "Disabled,Enabled" else group.quad spr:0x30E10++0x00 line.quad 0x00 "CNTKCTL_EL1,Counter-timer Kernel Control register" bitfld.quad 0x00 9. "EL0PTEN,Controls whether the physical timer registers are accessible from EL0 mode" "Disabled,Enabled" bitfld.quad 0x00 8. "EL0VTEN,Controls whether the virtual timer registers are accessible from EL0 mode" "Disabled,Enabled" bitfld.quad 0x00 4.--7. "EVNTI,Selects which bit of CNTVCT is the trigger for the event stream generated from that counter, when that stream is enabled" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.quad 0x00 3. "EVNTDIR,Controls which transition of the CNTVCT trigger bit defined by EVNTI, generates an event when the event stream is enabled" "0 to 1,1 to 0" newline bitfld.quad 0x00 2. "EVNTEN,Enables the generation of an event stream from the corresponding counter" "Disabled,Enabled" bitfld.quad 0x00 1. "EL0VCTEN,Controls whether the virtual counter, CNTVCT, and the frequency register CNTFRQ, are accessible from EL0 mode" "Disabled,Enabled" bitfld.quad 0x00 0. "EL0PCTEN,Controls whether the physical counter, CNTPCT, and the frequency register CNTFRQ, are accessible from EL0 mode" "Disabled,Enabled" endif if (((per.q(spr:0x34110))&0x408000000)==0x408000000) group.quad spr:0x35E10++0x00 line.quad 0x00 "CNTKCTL_EL12,Counter-timer Kernel Control register" bitfld.quad 0x00 4.--7. "EVNTI,Selects which bit of CNTVCT is the trigger for the event stream generated from that counter, when that stream is enabled" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.quad 0x00 3. "EVNTDIR,Controls which transition of the CNTVCT trigger bit defined by EVNTI, generates an event when the event stream is enabled" "0 to 1,1 to 0" bitfld.quad 0x00 2. "EVNTEN,Enables the generation of an event stream from the corresponding counter" "Disabled,Enabled" else group.quad spr:0x35E10++0x00 line.quad 0x00 "CNTKCTL_EL12,Counter-timer Kernel Control register" bitfld.quad 0x00 9. "EL0PTEN,Controls whether the physical timer registers are accessible from EL0 mode" "Disabled,Enabled" bitfld.quad 0x00 8. "EL0VTEN,Controls whether the virtual timer registers are accessible from EL0 mode" "Disabled,Enabled" bitfld.quad 0x00 4.--7. "EVNTI,Selects which bit of CNTVCT is the trigger for the event stream generated from that counter, when that stream is enabled" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.quad 0x00 3. "EVNTDIR,Controls which transition of the CNTVCT trigger bit defined by EVNTI, generates an event when the event stream is enabled" "0 to 1,1 to 0" newline bitfld.quad 0x00 2. "EVNTEN,Enables the generation of an event stream from the corresponding counter" "Disabled,Enabled" bitfld.quad 0x00 1. "EL0VCTEN,Controls whether the virtual counter, CNTVCT, and the frequency register CNTFRQ, are accessible from EL0 mode" "Disabled,Enabled" bitfld.quad 0x00 0. "EL0PCTEN,Controls whether the physical counter, CNTPCT, and the frequency register CNTFRQ, are accessible from EL0 mode" "Disabled,Enabled" endif if (((per.q(spr:0x34110))&0x400000000)==0x000000000) group.quad spr:0x34E10++0x00 line.quad 0x00 "CNTHCTL_EL2,Counter-timer Hypervisor Control register" bitfld.quad 0x00 4.--7. "EVNTI,Selects which bit of CNTPCT is the trigger for the event stream generated from the physical counter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.quad 0x00 3. "EVNTDIR,Controls which transition of the CNTVCT trigger bit defined by EVNTI, generates an event when the event stream is enabled" "0 to 1,1 to 0" bitfld.quad 0x00 2. "EVNTEN,Enables the generation of an event stream from the physical counter" "Disabled,Enabled" bitfld.quad 0x00 1. "EL1PCEN,Controls whether the physical timer registers are accessible from Non-secure EL1 and EL0 modes" "Not accessible,Accessible" newline bitfld.quad 0x00 0. "EL1PCTEN,Controls whether the physical counter, CNTPCT, is accessible from Non-secure EL1 and EL0 modes" "Not accessible,Accessible" elif (((per.q(spr:0x34110))&0x408000000)==0x400000000) group.quad spr:0x34E10++0x00 line.quad 0x00 "CNTHCTL_EL2,Counter-timer Hypervisor Control register" bitfld.quad 0x00 11. "EL1PTEN,Physical timer register accessing instructions are accessible from Non-secure EL1 and EL0" "Not accessible,Accessible" bitfld.quad 0x00 10. "EL1PCEN,Physical counter is accessible from Non-secure EL1 and EL0" "Not accessible,Accessible" newline bitfld.quad 0x00 4.--7. "EVNTI,Selects which bit of CNTPCT is the trigger for the event stream generated from the physical counter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.quad 0x00 3. "EVNTDIR,Controls which transition of the CNTVCT trigger bit defined by EVNTI, generates an event when the event stream is enabled" "0 to 1,1 to 0" bitfld.quad 0x00 2. "EVNTEN,Enables the generation of an event stream from the physical counter" "Disabled,Enabled" else group.quad spr:0x34E10++0x00 line.quad 0x00 "CNTHCTL_EL2,Counter-timer Hypervisor Control register" bitfld.quad 0x00 9. "EL0PTEN,Physical timer register accessing instructions are accessible from Non-secure EL0" "Not accessible,Accessible" bitfld.quad 0x00 8. "EL0VTEN,Virtual timer register accessing instructions are accessible from Non-secure EL0" "Not accessible,Accessible" newline bitfld.quad 0x00 4.--7. "EVNTI,Selects which bit of CNTPCT is the trigger for the event stream generated from the physical counter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.quad 0x00 3. "EVNTDIR,Controls which transition of the CNTVCT trigger bit defined by EVNTI, generates an event when the event stream is enabled" "0 to 1,1 to 0" bitfld.quad 0x00 2. "EVNTEN,Enables the generation of an event stream from the physical counter" "Disabled,Enabled" bitfld.quad 0x00 1. "EL0VCTEN,Virtual counter register accessing instructions are accessible from Non-secure EL0" "Not accessible,Accessible" newline bitfld.quad 0x00 0. "EL0PCTEN,Physical counter is accessible from Non-secure EL0 modes" "Not accessible,Accessible" endif group.quad spr:0x33E20++0x00 line.quad 0x00 "CNTP_TVAL_EL0,Counter-timer Physical Timer TimerValue register" group.quad spr:0x35E20++0x00 line.quad 0x00 "CNTP_TVAL_EL02,Counter-timer Physical Timer TimerValue register" group.quad spr:0x33E21++0x00 line.quad 0x00 "CNTP_CTL_EL0,Counter-timer Physical Timer Control register" rbitfld.quad 0x00 2. "ISTATUS,The status of the timer interrupt" "No interrupt,Interrupt" bitfld.quad 0x00 1. "IMASK,Timer interrupt mask" "Not masked,Masked" bitfld.quad 0x00 0. "ENABLE,Enables the timer" "Disabled,Enabled" group.quad spr:0x35E21++0x00 line.quad 0x00 "CNTP_CTL_EL02,Counter-timer Physical Timer Control register" rbitfld.quad 0x00 2. "ISTATUS,The status of the timer interrupt" "No interrupt,Interrupt" bitfld.quad 0x00 1. "IMASK,Timer interrupt mask" "Not masked,Masked" bitfld.quad 0x00 0. "ENABLE,Enables the timer" "Disabled,Enabled" group.quad spr:0x33E22++0x00 line.quad 0x00 "CNTP_CVAL_EL0,Counter-timer Physical Timer CompareValue register" group.quad spr:0x35E22++0x00 line.quad 0x00 "CNTP_CVAL_EL02,Counter-timer Physical Timer CompareValue register" group.quad spr:0x33E30++0x00 line.quad 0x00 "CNTV_TVAL_EL0,Counter-timer Virtual Timer TimerValue register" group.quad spr:0x35E30++0x00 line.quad 0x00 "CNTV_TVAL_EL02,Counter-timer Virtual Timer TimerValue register" group.quad spr:0x33E31++0x00 line.quad 0x00 "CNTV_CTL_EL0,Counter-timer Virtual Timer Control register" rbitfld.quad 0x00 2. "ISTATUS,The status of the timer interrupt" "No interrupt,Interrupt" bitfld.quad 0x00 1. "IMASK,Timer interrupt mask" "Not masked,Masked" bitfld.quad 0x00 0. "ENABLE,Enables the timer" "Disabled,Enabled" group.quad spr:0x35E31++0x00 line.quad 0x00 "CNTV_CTL_EL02,Counter-timer Virtual Timer Control register" rbitfld.quad 0x00 2. "ISTATUS,The status of the timer interrupt" "No interrupt,Interrupt" bitfld.quad 0x00 1. "IMASK,Timer interrupt mask" "Not masked,Masked" bitfld.quad 0x00 0. "ENABLE,Enables the timer" "Disabled,Enabled" group.quad spr:0x33E32++0x00 line.quad 0x00 "CNTV_CVAL_EL0,Counter-timer Virtual Timer CompareValue register" group.quad spr:0x35E32++0x00 line.quad 0x00 "CNTV_CVAL_EL02,Counter-timer Virtual Timer CompareValue register" group.quad spr:0x34E20++0x00 line.quad 0x00 "CNTHP_TVAL_EL2,Counter-timer Hypervisor Physical Timer TimerValue register" group.quad spr:0x34E21++0x00 line.quad 0x00 "CNTHP_CTL_EL2,Counter-timer Hypervisor Physical Timer Control register" rbitfld.quad 0x00 2. "ISTATUS,The status of the timer interrupt" "No interrupt,Interrupt" bitfld.quad 0x00 1. "IMASK,Timer interrupt mask" "Not masked,Masked" bitfld.quad 0x00 0. "ENABLE,Enables the timer" "Disabled,Enabled" group.quad spr:0x34E22++0x00 line.quad 0x00 "CNTHP_CVAL_EL2,Counter-timer Hypervisor Physical Timer CompareValue register" group.quad spr:0x34E30++0x00 line.quad 0x00 "CNTHV_TVAL_EL2,Counter-timer Hypervisor Virtual Timer Value register" group.quad spr:0x34E31++0x00 line.quad 0x00 "CNTHV_CTL_EL2,Counter-timer Hypervisor Virtual Timer Control register" rbitfld.quad 0x00 2. "ISTATUS,The status of the timer interrupt" "No interrupt,Interrupt" bitfld.quad 0x00 1. "IMASK,Timer interrupt mask" "Not masked,Masked" bitfld.quad 0x00 0. "ENABLE,Enables the timer" "Disabled,Enabled" group.quad spr:0x34E32++0x00 line.quad 0x00 "CNTHV_CVAL_EL2,Counter-timer Hypervisor Virtual Timer CompareValue register" group.quad spr:0x37E20++0x00 line.quad 0x00 "CNTPS_TVAL_EL1,Counter-timer Physical Secure Timer TimerValue register" group.quad spr:0x37E21++0x00 line.quad 0x00 "CNTPS_CTL_EL1,Counter-timer Physical Secure Timer Control register" rbitfld.quad 0x00 2. "ISTATUS,The status of the timer interrupt" "No interrupt,Interrupt" bitfld.quad 0x00 1. "IMASK,Timer interrupt mask" "Not masked,Masked" bitfld.quad 0x00 0. "ENABLE,Enables the timer" "Disabled,Enabled" group.quad spr:0x37E22++0x00 line.quad 0x00 "CNTPS_CVAL_EL1,Counter-timer Physical Secure Timer CompareValue register" tree.end tree "Generic Interrupt Controller System Registers" tree "AArch64 Physical GIC CPU Interface System Registers" tree "Active Priorities Registers" group.quad spr:0x30C84++0x00 line.quad 0x00 "ICC_AP0R0_EL1,Active Priorities 0 Register 0" bitfld.quad 0x00 31. "P31,Group 0 interrupt active with priority level 31" "No interrupt,Interrupt" bitfld.quad 0x00 30. "P30,Group 0 interrupt active with priority level 30" "No interrupt,Interrupt" bitfld.quad 0x00 29. "P29,Group 0 interrupt active with priority level 29" "No interrupt,Interrupt" bitfld.quad 0x00 28. "P28,Group 0 interrupt active with priority level 28" "No interrupt,Interrupt" bitfld.quad 0x00 27. "P27,Group 0 interrupt active with priority level 27" "No interrupt,Interrupt" newline bitfld.quad 0x00 26. "P26,Group 0 interrupt active with priority level 26" "No interrupt,Interrupt" bitfld.quad 0x00 25. "P25,Group 0 interrupt active with priority level 25" "No interrupt,Interrupt" bitfld.quad 0x00 24. "P24,Group 0 interrupt active with priority level 24" "No interrupt,Interrupt" bitfld.quad 0x00 23. "P23,Group 0 interrupt active with priority level 23" "No interrupt,Interrupt" bitfld.quad 0x00 22. "P22,Group 0 interrupt active with priority level 22" "No interrupt,Interrupt" newline bitfld.quad 0x00 21. "P21,Group 0 interrupt active with priority level 21" "No interrupt,Interrupt" bitfld.quad 0x00 20. "P20,Group 0 interrupt active with priority level 20" "No interrupt,Interrupt" bitfld.quad 0x00 19. "P19,Group 0 interrupt active with priority level 19" "No interrupt,Interrupt" bitfld.quad 0x00 18. "P18,Group 0 interrupt active with priority level 18" "No interrupt,Interrupt" bitfld.quad 0x00 17. "P17,Group 0 interrupt active with priority level 17" "No interrupt,Interrupt" newline bitfld.quad 0x00 16. "P16,Group 0 interrupt active with priority level 16" "No interrupt,Interrupt" bitfld.quad 0x00 15. "P15,Group 0 interrupt active with priority level 15" "No interrupt,Interrupt" bitfld.quad 0x00 14. "P14,Group 0 interrupt active with priority level 14" "No interrupt,Interrupt" bitfld.quad 0x00 13. "P13,Group 0 interrupt active with priority level 13" "No interrupt,Interrupt" bitfld.quad 0x00 12. "P12,Group 0 interrupt active with priority level 12" "No interrupt,Interrupt" newline bitfld.quad 0x00 11. "P11,Group 0 interrupt active with priority level 11" "No interrupt,Interrupt" bitfld.quad 0x00 10. "P10,Group 0 interrupt active with priority level 10" "No interrupt,Interrupt" bitfld.quad 0x00 9. "P9,Group 0 interrupt active with priority level 9" "No interrupt,Interrupt" bitfld.quad 0x00 8. "P8,Group 0 interrupt active with priority level 8" "No interrupt,Interrupt" bitfld.quad 0x00 7. "P7,Group 0 interrupt active with priority level 7" "No interrupt,Interrupt" newline bitfld.quad 0x00 6. "P6,Group 0 interrupt active with priority level 6" "No interrupt,Interrupt" bitfld.quad 0x00 5. "P5,Group 0 interrupt active with priority level 5" "No interrupt,Interrupt" bitfld.quad 0x00 4. "P4,Group 0 interrupt active with priority level 4" "No interrupt,Interrupt" bitfld.quad 0x00 3. "P3,Group 0 interrupt active with priority level 3" "No interrupt,Interrupt" bitfld.quad 0x00 2. "P2,Group 0 interrupt active with priority level 2" "No interrupt,Interrupt" newline bitfld.quad 0x00 1. "P1,Group 0 interrupt active with priority level 1" "No interrupt,Interrupt" bitfld.quad 0x00 0. "P0,Group 0 interrupt active with priority level 0" "No interrupt,Interrupt" group.quad spr:0x30C90++0x00 line.quad 0x00 "ICC_AP1R0_EL1,Active Priorities 1 Register 0" bitfld.quad 0x00 31. "P31,Group 1 interrupt active with priority level 31" "No interrupt,Interrupt" bitfld.quad 0x00 30. "P30,Group 1 interrupt active with priority level 30" "No interrupt,Interrupt" bitfld.quad 0x00 29. "P29,Group 1 interrupt active with priority level 29" "No interrupt,Interrupt" bitfld.quad 0x00 28. "P28,Group 1 interrupt active with priority level 28" "No interrupt,Interrupt" bitfld.quad 0x00 27. "P27,Group 1 interrupt active with priority level 27" "No interrupt,Interrupt" newline bitfld.quad 0x00 26. "P26,Group 1 interrupt active with priority level 26" "No interrupt,Interrupt" bitfld.quad 0x00 25. "P25,Group 1 interrupt active with priority level 25" "No interrupt,Interrupt" bitfld.quad 0x00 24. "P24,Group 1 interrupt active with priority level 24" "No interrupt,Interrupt" bitfld.quad 0x00 23. "P23,Group 1 interrupt active with priority level 23" "No interrupt,Interrupt" bitfld.quad 0x00 22. "P22,Group 1 interrupt active with priority level 22" "No interrupt,Interrupt" newline bitfld.quad 0x00 21. "P21,Group 1 interrupt active with priority level 21" "No interrupt,Interrupt" bitfld.quad 0x00 20. "P20,Group 1 interrupt active with priority level 20" "No interrupt,Interrupt" bitfld.quad 0x00 19. "P19,Group 1 interrupt active with priority level 19" "No interrupt,Interrupt" bitfld.quad 0x00 18. "P18,Group 1 interrupt active with priority level 18" "No interrupt,Interrupt" bitfld.quad 0x00 17. "P17,Group 1 interrupt active with priority level 17" "No interrupt,Interrupt" newline bitfld.quad 0x00 16. "P16,Group 1 interrupt active with priority level 16" "No interrupt,Interrupt" bitfld.quad 0x00 15. "P15,Group 1 interrupt active with priority level 15" "No interrupt,Interrupt" bitfld.quad 0x00 14. "P14,Group 1 interrupt active with priority level 14" "No interrupt,Interrupt" bitfld.quad 0x00 13. "P13,Group 1 interrupt active with priority level 13" "No interrupt,Interrupt" bitfld.quad 0x00 12. "P12,Group 1 interrupt active with priority level 12" "No interrupt,Interrupt" newline bitfld.quad 0x00 11. "P11,Group 1 interrupt active with priority level 11" "No interrupt,Interrupt" bitfld.quad 0x00 10. "P10,Group 1 interrupt active with priority level 10" "No interrupt,Interrupt" bitfld.quad 0x00 9. "P9,Group 1 interrupt active with priority level 9" "No interrupt,Interrupt" bitfld.quad 0x00 8. "P8,Group 1 interrupt active with priority level 8" "No interrupt,Interrupt" bitfld.quad 0x00 7. "P7,Group 1 interrupt active with priority level 7" "No interrupt,Interrupt" newline bitfld.quad 0x00 6. "P6,Group 1 interrupt active with priority level 6" "No interrupt,Interrupt" bitfld.quad 0x00 5. "P5,Group 1 interrupt active with priority level 5" "No interrupt,Interrupt" bitfld.quad 0x00 4. "P4,Group 1 interrupt active with priority level 4" "No interrupt,Interrupt" bitfld.quad 0x00 3. "P3,Group 1 interrupt active with priority level 3" "No interrupt,Interrupt" bitfld.quad 0x00 2. "P2,Group 1 interrupt active with priority level 2" "No interrupt,Interrupt" newline bitfld.quad 0x00 1. "P1,Group 1 interrupt active with priority level 1" "No interrupt,Interrupt" bitfld.quad 0x00 0. "P0,Group 1 interrupt active with priority level 0" "No interrupt,Interrupt" tree.end newline if (((per.q(spr:0x30CB6))&0x10000000000)==0x00) wgroup.quad spr:0x30CB6++0x00 line.quad 0x00 "ICC_ASGI1R_EL1,Interrupt Controller Alias Software Generated Interrupt Group 1 Register" hexmask.quad.byte 0x00 48.--55. 1. "AFF3,Affinity 3" newline bitfld.quad 0x00 44.--47. "RS,Range selector" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.quad 0x00 40. "IRM,Interrupt routing mode" "Target list,All PEs excluding self" newline hexmask.quad.byte 0x00 32.--39. 1. "AFF2,Affinity 2" bitfld.quad 0x00 24.--27. "INTID,The INTID of the SGI" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline hexmask.quad.byte 0x00 16.--23. 1. "AFF1,Affinity 1" hexmask.quad.word 0x00 0.--15. 1. "TARGETLIST,The set of PEs for which SGI interrupts will be generated" else wgroup.quad spr:0x30CB6++0x00 line.quad 0x00 "ICC_ASGI1R_EL1,Interrupt Controller Alias Software Generated Interrupt Group 1 Register" newline bitfld.quad 0x00 44.--47. "RS,Range selector" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.quad 0x00 40. "IRM,Interrupt routing mode" "Target list,All PEs excluding self" newline bitfld.quad 0x00 24.--27. "INTID,The INTID of the SGI" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline endif group.quad spr:0x30C83++0x00 line.quad 0x00 "ICC_BPR0_EL1,Binary Point Register 0" bitfld.quad 0x00 0.--2. "BINARYPOINT,Interrupt Priority Field Control And Interrupt Preemption Control" "Reserved,Reserved,[7:3]-[2:0],[7:4]-[3:0],[7:5]-[4:0],[7:6]-[5:0],[7]-[6:0],No preemption-[7:0]" group.quad spr:0x30CC3++0x00 line.quad 0x00 "ICC_BPR1_EL1,Binary Point Register 1" bitfld.quad 0x00 0.--2. "BINARYPOINT,Interrupt Priority Field Control And Interrupt Preemption Control" "Reserved,Reserved,[7:2]-[1:0],[7:3]-[2:0],[7:4]-[3:0],[7:5]-[4:0],[7:6]-[5:0],[7]-[6:0]" group.quad spr:0x30CC4++0x00 line.quad 0x00 "ICC_CTLR_EL1,Interrupt Control Registers for EL1" rbitfld.quad 0x00 19. "EXTRANGE,Extended INTID range" "Reserved,Supported" rbitfld.quad 0x00 18. "RSS,Range selector support" "0 - 15,0 - 255" newline rbitfld.quad 0x00 15. "A3V,Affinity 3 Valid" "Reserved,Valid" rbitfld.quad 0x00 14. "SEIS,SEI Support" "Not supported," bitfld.quad 0x00 11.--13. "IDBITS,Number of physical interrupt identifier bits supported" "16 bits,?..." rbitfld.quad 0x00 8.--10. "PRIBITS,Number of priority bits implemented" "Reserved,Reserved,Reserved,Reserved,5,?..." newline bitfld.quad 0x00 6. "PMHE,Priority Mask Hint Enable" "Disabled,Enabled" bitfld.quad 0x00 1. "EOIMODE,Indicates whether ICC_EOIR0 and ICC_EOIR1 provide both priority drop and interrupt deactivation functionality" "Both,Priority drop" bitfld.quad 0x00 0. "CBPR,Common Binary Point Register" "Separate,Common" group.quad spr:0x36CC4++0x00 line.quad 0x00 "ICC_CTLR_EL3,Interrupt Control Registers for EL3" rbitfld.quad 0x00 19. "EXTRANGE,Extended INTID range" "Reserved,Supported" rbitfld.quad 0x00 18. "RSS,Range selector support" "0 - 15,0 - 255" newline rbitfld.quad 0x00 17. "NDS,Disable Security not supported" "Reserved,Not supported" rbitfld.quad 0x00 15. "A3V,Affinity 3 Valid" "Reserved,Valid" rbitfld.quad 0x00 14. "SEIS,SEI Support" "Not supported," newline bitfld.quad 0x00 11.--13. "IDBITS,Number of physical interrupt identifier bits supported" "16 bits,?..." rbitfld.quad 0x00 8.--10. "PRIBITS,Number of priority bits implemented" "Reserved,Reserved,Reserved,Reserved,5,?..." bitfld.quad 0x00 6. "PMHE,Priority Mask Hint Enable" "Disabled,Enabled" newline rbitfld.quad 0x00 5. "RM,Routing Modifier" "Normal," bitfld.quad 0x00 4. "EOIMODE_EL1NS,EOI mode for interrupts handledat non-secure EL1 and EL2" "0,1" bitfld.quad 0x00 3. "EOIMODE_EL1S,EOI mode for interrupts handled at secure EL1" "0,1" newline bitfld.quad 0x00 2. "EOIMODE_EL3,EOI mode for interrupts handled at EL3" "0,1" bitfld.quad 0x00 1. "CBPR_EL1NS,Non-secure accesses to GICC_BPR allowed." "Not allowed,Allowed" bitfld.quad 0x00 0. "CBPR_EL1S,Secure EL1 accesses to ICC_BPR1 allowed" "Not allowed,Allowed" wgroup.quad spr:0x30CB1++0x00 line.quad 0x00 "ICC_DIR_EL1,Deactivate Interrupt Register" hexmask.quad.word 0x00 0.--15. 1. "INTID,The INTID of the interrupt to be deactivated" wgroup.quad spr:0x30C81++0x00 line.quad 0x00 "ICC_EOIR0_EL1,End Of Interrupt Register 0" hexmask.quad.word 0x00 0.--15. 1. "INTID,The INTID from the corresponding ICC_IAR0_EL1 access" wgroup.quad spr:0x30CC1++0x00 line.quad 0x00 "ICC_EOIR1_EL1,End Of Interrupt Register 1" hexmask.quad.word 0x00 0.--15. 1. "INTID,The INTID from the corresponding ICC_IAR1_EL1 access" rgroup.quad spr:0x30C82++0x00 line.quad 0x00 "ICC_HPPIR0_EL1,Highest Priority Pending Interrupt Register 0" hexmask.quad.word 0x00 0.--15. 1. "INTID,The INTID of the highest priority pending interrupt" rgroup.quad spr:0x30CC2++0x00 line.quad 0x00 "ICC_HPPIR1_EL1,Highest Priority Pending Interrupt Register 1" hexmask.quad.word 0x00 0.--15. 1. "INTID,The INTID of the highest priority pending interrupt" newline hgroup.quad spr:0x30C80++0x00 hide.long 0x00 "ICC_IAR0_EL1,Interrupt Acknowledge Register 0" in hgroup.quad spr:0x30CC0++0x00 hide.long 0x00 "ICC_IAR1_EL1,Interrupt Acknowledge Register 1" in newline group.quad spr:0x30CC6++0x00 line.quad 0x00 "ICC_IGRPEN0_EL1,Interrupt Group 0 Enable Register (EL1)" bitfld.quad 0x00 0. "ENABLE,Enable" "Disabled,Enabled" group.quad spr:0x30CC7++0x00 line.quad 0x00 "ICC_IGRPEN1_EL1,Interrupt Group 1 Enable Register (EL1)" bitfld.quad 0x00 0. "ENABLE,Enable" "Disabled,Enabled" group.quad spr:0x36CC7++0x00 line.quad 0x00 "ICC_IGRPEN1_EL3,Interrupt Group Enable Register 1 (EL3)" bitfld.quad 0x00 1. "ENABLEGRP1S,Enable Group 1 interrupts for the Secure state" "Disabled,Enabled" bitfld.quad 0x00 0. "ENABLEGRP1NS,Enable Group 1 interrupts for the Non-secure state" "Disabled,Enabled" group.quad spr:0x30460++0x00 line.quad 0x00 "ICC_PMR_EL1,Priority Mask Register" hexmask.quad.byte 0x00 0.--7. 1. "PRIORITY,Priority mask level for the CPU interface" rgroup.quad spr:0x30CB3++0x00 line.quad 0x00 "ICC_RPR_EL1,Running Priority Register" hexmask.quad.byte 0x00 0.--7. 1. "PRIORITY,Current running priority on the CPU interface" if (((per.q(spr:0x30CB7))&0x10000000000)==0x00) wgroup.quad spr:0x30CB7++0x00 line.quad 0x00 "ICC_SGI0R_EL1,Interrupt Controller Software Generated Interrupt Group 0 Register" hexmask.quad.byte 0x00 48.--55. 1. "AFF3,Affinity 3" newline bitfld.quad 0x00 44.--47. "RS,Range selector" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.quad 0x00 40. "IRM,Interrupt routing mode" "Target list,All PEs excluding self" newline hexmask.quad.byte 0x00 32.--39. 1. "AFF2,Affinity 2" bitfld.quad 0x00 24.--27. "INTID,The INTID of the SGI" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline hexmask.quad.byte 0x00 16.--23. 1. "AFF1,Affinity 1" hexmask.quad.word 0x00 0.--15. 1. "TARGETLIST,The set of PEs for which SGI interrupts will be generated." else wgroup.quad spr:0x30CB7++0x00 line.quad 0x00 "ICC_SGI0R_EL1,Interrupt Controller Software Generated Interrupt Group 0 Register" newline bitfld.quad 0x00 44.--47. "RS,Range selector" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.quad 0x00 40. "IRM,Interrupt routing mode" "Target list,All PEs excluding self" newline bitfld.quad 0x00 24.--27. "INTID,The INTID of the SGI" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline endif if (((per.q(spr:0x30CB5))&0x10000000000)==0x00) wgroup.quad spr:0x30CB5++0x00 line.quad 0x00 "ICC_SGI1R_EL1,Interrupt Controller Software Generated Interrupt Group 0 Register" hexmask.quad.byte 0x00 48.--55. 1. "AFF3,Affinity 3" newline bitfld.quad 0x00 44.--47. "RS,Range selector" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.quad 0x00 40. "IRM,Interrupt routing mode" "Target list,All PEs excluding self" newline hexmask.quad.byte 0x00 32.--39. 1. "AFF2,Affinity 2" bitfld.quad 0x00 24.--27. "INTID,The INTID of the SGI" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline hexmask.quad.byte 0x00 16.--23. 1. "AFF1,Affinity 1" hexmask.quad.word 0x00 0.--15. 1. "TARGETLIST,The set of PEs for which SGI interrupts will be generated" else wgroup.quad spr:0x30CB5++0x00 line.quad 0x00 "ICC_SGI1R_EL1,Interrupt Controller Software Generated Interrupt Group 0 Register" newline bitfld.quad 0x00 44.--47. "RS,Range selector" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.quad 0x00 40. "IRM,Interrupt routing mode" "Target list,All PEs excluding self" newline bitfld.quad 0x00 24.--27. "INTID,The INTID of the SGI" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline endif group.quad spr:0x30CC5++0x00 line.quad 0x00 "ICC_SRE_EL1,System Register Enable Register for EL1" bitfld.quad 0x00 2. "DIB,Disable IRQ bypass" "No,Yes" bitfld.quad 0x00 1. "DFB,Disable FIQ bypass" "No,Yes" rbitfld.quad 0x00 0. "SRE,System Register Enable" "Reserved,Enabled" group.quad spr:0x34C95++0x00 line.quad 0x00 "ICC_SRE_EL2,System Register Enable Register for EL2" rbitfld.quad 0x00 3. "ENABLE,Enable lower exception level access to ICC_SRE_EL1" "Reserved,Enabled" bitfld.quad 0x00 2. "DIB,Disable IRQ bypass" "No,Yes" bitfld.quad 0x00 1. "DFB,Disable FIQ bypass" "No,Yes" newline rbitfld.quad 0x00 0. "SRE,System Register Enable" "Reserved,Enabled" group.quad spr:0x36CC5++0x00 line.quad 0x00 "ICC_SRE_EL3,System Register Enable Register for EL3" rbitfld.quad 0x00 3. "ENABLE,Enable lower exception level access to ICC_SRE_EL1 and ICC_SRE_EL2" "Reserved,Enabled" bitfld.quad 0x00 2. "DIB,Disable IRQ bypass" "No,Yes" bitfld.quad 0x00 1. "DFB,Disable FIQ bypass" "No,Yes" newline rbitfld.quad 0x00 0. "SRE,System Register Enable" "Reserved,Enabled" tree.end tree "AArch64 Virtual GIC CPU Interface System Registers" tree.open "Interrupt Controller Active Priorities Registers" group.quad spr:0x30C84++0x00 line.quad 0x00 "ICV_AP0R0_EL1,Active Priorities Group 0 Register 0 (EL1)" bitfld.quad 0x00 31. "P31,Group 0 interrupt active with priority level 31" "No interrupt,Interrupt" bitfld.quad 0x00 30. "P30,Group 0 interrupt active with priority level 30" "No interrupt,Interrupt" bitfld.quad 0x00 29. "P29,Group 0 interrupt active with priority level 29" "No interrupt,Interrupt" bitfld.quad 0x00 28. "P28,Group 0 interrupt active with priority level 28" "No interrupt,Interrupt" bitfld.quad 0x00 27. "P27,Group 0 interrupt active with priority level 27" "No interrupt,Interrupt" newline bitfld.quad 0x00 26. "P26,Group 0 interrupt active with priority level 26" "No interrupt,Interrupt" bitfld.quad 0x00 25. "P25,Group 0 interrupt active with priority level 25" "No interrupt,Interrupt" bitfld.quad 0x00 24. "P24,Group 0 interrupt active with priority level 24" "No interrupt,Interrupt" bitfld.quad 0x00 23. "P23,Group 0 interrupt active with priority level 23" "No interrupt,Interrupt" bitfld.quad 0x00 22. "P22,Group 0 interrupt active with priority level 22" "No interrupt,Interrupt" newline bitfld.quad 0x00 21. "P21,Group 0 interrupt active with priority level 21" "No interrupt,Interrupt" bitfld.quad 0x00 20. "P20,Group 0 interrupt active with priority level 20" "No interrupt,Interrupt" bitfld.quad 0x00 19. "P19,Group 0 interrupt active with priority level 19" "No interrupt,Interrupt" bitfld.quad 0x00 18. "P18,Group 0 interrupt active with priority level 18" "No interrupt,Interrupt" bitfld.quad 0x00 17. "P17,Group 0 interrupt active with priority level 17" "No interrupt,Interrupt" newline bitfld.quad 0x00 16. "P16,Group 0 interrupt active with priority level 16" "No interrupt,Interrupt" bitfld.quad 0x00 15. "P15,Group 0 interrupt active with priority level 15" "No interrupt,Interrupt" bitfld.quad 0x00 14. "P14,Group 0 interrupt active with priority level 14" "No interrupt,Interrupt" bitfld.quad 0x00 13. "P13,Group 0 interrupt active with priority level 13" "No interrupt,Interrupt" bitfld.quad 0x00 12. "P12,Group 0 interrupt active with priority level 12" "No interrupt,Interrupt" newline bitfld.quad 0x00 11. "P11,Group 0 interrupt active with priority level 11" "No interrupt,Interrupt" bitfld.quad 0x00 10. "P10,Group 0 interrupt active with priority level 10" "No interrupt,Interrupt" bitfld.quad 0x00 9. "P9,Group 0 interrupt active with priority level 9" "No interrupt,Interrupt" bitfld.quad 0x00 8. "P8,Group 0 interrupt active with priority level 8" "No interrupt,Interrupt" bitfld.quad 0x00 7. "P7,Group 0 interrupt active with priority level 7" "No interrupt,Interrupt" newline bitfld.quad 0x00 6. "P6,Group 0 interrupt active with priority level 6" "No interrupt,Interrupt" bitfld.quad 0x00 5. "P5,Group 0 interrupt active with priority level 5" "No interrupt,Interrupt" bitfld.quad 0x00 4. "P4,Group 0 interrupt active with priority level 4" "No interrupt,Interrupt" bitfld.quad 0x00 3. "P3,Group 0 interrupt active with priority level 3" "No interrupt,Interrupt" bitfld.quad 0x00 2. "P2,Group 0 interrupt active with priority level 2" "No interrupt,Interrupt" newline bitfld.quad 0x00 1. "P1,Group 0 interrupt active with priority level 1" "No interrupt,Interrupt" bitfld.quad 0x00 0. "P0,Group 0 interrupt active with priority level 0" "No interrupt,Interrupt" group.quad spr:0x30C90++0x00 line.quad 0x00 "ICV_AP1R0_EL1,Active Priorities Group 1 Register 0 (EL1)" bitfld.quad 0x00 31. "P31,Group 1 interrupt active with priority level 31" "No interrupt,Interrupt" bitfld.quad 0x00 30. "P30,Group 1 interrupt active with priority level 30" "No interrupt,Interrupt" bitfld.quad 0x00 29. "P29,Group 1 interrupt active with priority level 29" "No interrupt,Interrupt" bitfld.quad 0x00 28. "P28,Group 1 interrupt active with priority level 28" "No interrupt,Interrupt" bitfld.quad 0x00 27. "P27,Group 1 interrupt active with priority level 27" "No interrupt,Interrupt" newline bitfld.quad 0x00 26. "P26,Group 1 interrupt active with priority level 26" "No interrupt,Interrupt" bitfld.quad 0x00 25. "P25,Group 1 interrupt active with priority level 25" "No interrupt,Interrupt" bitfld.quad 0x00 24. "P24,Group 1 interrupt active with priority level 24" "No interrupt,Interrupt" bitfld.quad 0x00 23. "P23,Group 1 interrupt active with priority level 23" "No interrupt,Interrupt" bitfld.quad 0x00 22. "P22,Group 1 interrupt active with priority level 22" "No interrupt,Interrupt" newline bitfld.quad 0x00 21. "P21,Group 1 interrupt active with priority level 21" "No interrupt,Interrupt" bitfld.quad 0x00 20. "P20,Group 1 interrupt active with priority level 20" "No interrupt,Interrupt" bitfld.quad 0x00 19. "P19,Group 1 interrupt active with priority level 19" "No interrupt,Interrupt" bitfld.quad 0x00 18. "P18,Group 1 interrupt active with priority level 18" "No interrupt,Interrupt" bitfld.quad 0x00 17. "P17,Group 1 interrupt active with priority level 17" "No interrupt,Interrupt" newline bitfld.quad 0x00 16. "P16,Group 1 interrupt active with priority level 16" "No interrupt,Interrupt" bitfld.quad 0x00 15. "P15,Group 1 interrupt active with priority level 15" "No interrupt,Interrupt" bitfld.quad 0x00 14. "P14,Group 1 interrupt active with priority level 14" "No interrupt,Interrupt" bitfld.quad 0x00 13. "P13,Group 1 interrupt active with priority level 13" "No interrupt,Interrupt" bitfld.quad 0x00 12. "P12,Group 1 interrupt active with priority level 12" "No interrupt,Interrupt" newline bitfld.quad 0x00 11. "P11,Group 1 interrupt active with priority level 11" "No interrupt,Interrupt" bitfld.quad 0x00 10. "P10,Group 1 interrupt active with priority level 10" "No interrupt,Interrupt" bitfld.quad 0x00 9. "P9,Group 1 interrupt active with priority level 9" "No interrupt,Interrupt" bitfld.quad 0x00 8. "P8,Group 1 interrupt active with priority level 8" "No interrupt,Interrupt" bitfld.quad 0x00 7. "P7,Group 1 interrupt active with priority level 7" "No interrupt,Interrupt" newline bitfld.quad 0x00 6. "P6,Group 1 interrupt active with priority level 6" "No interrupt,Interrupt" bitfld.quad 0x00 5. "P5,Group 1 interrupt active with priority level 5" "No interrupt,Interrupt" bitfld.quad 0x00 4. "P4,Group 1 interrupt active with priority level 4" "No interrupt,Interrupt" bitfld.quad 0x00 3. "P3,Group 1 interrupt active with priority level 3" "No interrupt,Interrupt" bitfld.quad 0x00 2. "P2,Group 1 interrupt active with priority level 2" "No interrupt,Interrupt" newline bitfld.quad 0x00 1. "P1,Group 1 interrupt active with priority level 1" "No interrupt,Interrupt" bitfld.quad 0x00 0. "P0,Group 1 interrupt active with priority level 0" "No interrupt,Interrupt" tree.end newline group.quad spr:0x30C83++0x00 line.quad 0x00 "ICV_BPR0_EL1,Binary Point Register 0 (EL1)" bitfld.quad 0x00 0.--2. "BINARYPOINT,Interrupt Priority Field Control And Interrupt Preemption Control" "Reserved,Reserved,[7:3]-[2:0],[7:4]-[3:0],[7:5]-[4:0],[7:6]-[5:0],[7]-[6:0],No preemption-[7:0]" group.quad spr:0x30CC3++0x00 line.quad 0x00 "ICV_BPR1_EL1,Binary Point Register 1 (EL1)" bitfld.quad 0x00 0.--2. "BINARYPOINT,Interrupt Priority Field Control And Interrupt Preemption Control" "Reserved,Reserved,[7:2]-[1:0],[7:3]-[2:0],[7:4]-[3:0],[7:5]-[4:0],[7:6]-[5:0],[7]-[6:0]" group.quad spr:0x30CC4++0x00 line.quad 0x00 "ICV_CTLR_EL1,Control Register (EL1)" rbitfld.quad 0x00 15. "A3V,Affinity 3 Valid" "Reserved,Valid" rbitfld.quad 0x00 14. "SEIS,SEI Support" "Not supported," rbitfld.quad 0x00 11.--13. "IDBITS,The number of physical interrupt identifier bits supported" "16 bits,?..." newline rbitfld.quad 0x00 8.--10. "PRIBITS,Number of priority bits implemented" "Reserved,Reserved,Reserved,Reserved,5,?..." bitfld.quad 0x00 1. "VEOIMODE,Indicates whether ICV_EOIR0 and ICV_EOIR1 provide both priority drop and interrupt deactivation functionality" "Both,Priority drop" bitfld.quad 0x00 0. "VCBPR,Common Binary Point Register" "Separate,Common" wgroup.quad spr:0x30CB1++0x00 line.quad 0x00 "ICV_DIR_EL1,Deactivate Interrupt Register" hexmask.quad.word 0x00 0.--15. 1. "INTID,The INTID of the virtual interrupt to be deactivated" wgroup.quad spr:0x30C81++0x00 line.quad 0x00 "ICV_EOIR0_EL1,End Of Interrupt Register 0" hexmask.quad.word 0x00 0.--15. 1. "INTID,The INTID from the corresponding ICV_IAR0_EL1 access" wgroup.quad spr:0x30CC1++0x00 line.quad 0x00 "ICV_EOIR1_EL1,End Of Interrupt Register 1" hexmask.quad.word 0x00 0.--15. 1. "INTID,The INTID from the corresponding ICV_IAR1_EL1 access" rgroup.quad spr:0x30C82++0x00 line.quad 0x00 "ICV_HPPIR0_EL1,Highest Priority Pending Interrupt Register 0" hexmask.quad.word 0x00 0.--15. 1. "INTID,The INTID of the highest priority pending interrupt" rgroup.quad spr:0x30CC2++0x00 line.quad 0x00 "ICV_HPPIR1_EL1,Highest Priority Pending Interrupt Register 1" hexmask.quad.word 0x00 0.--15. 1. "INTID,The INTID of the highest priority pending interrupt" rgroup.quad spr:0x30C80++0x00 line.quad 0x00 "ICV_IAR0_EL1,Interrupt Acknowledge Register 0" rgroup.quad spr:0x30CC0++0x00 line.quad 0x00 "ICV_IAR1_EL1,Interrupt Acknowledge Register 1" group.quad spr:0x30CC6++0x00 line.quad 0x00 "ICV_IGRPEN0_EL1,Interrupt Group 0 Enable register" bitfld.quad 0x00 0. "ENABLE,Enables Group 0 interrupts" "Disabled,Enabled" group.quad spr:0x30CC7++0x00 line.quad 0x00 "ICV_IGRPEN1_EL1,Interrupt Group 1 Enable register" bitfld.quad 0x00 0. "ENABLE,Enables Group 1 interrupts" "Disabled,Enabled" group.quad spr:0x30460++0x00 line.quad 0x00 "ICV_PMR_EL1,Priority Mask Register" hexmask.quad.byte 0x00 0.--7. 1. "PRIORITY,Priority mask level for the CPU interface" rgroup.quad spr:0x30CB3++0x00 line.quad 0x00 "ICV_RPR_EL1,Running Priority Register" hexmask.quad.byte 0x00 0.--7. 1. "PRIORITY,Current running priority on the CPU interface" tree.end tree "AArch64 Virtual Interface Control System Registers" tree.open "Hypervisor Active Priorities Registers" group.quad spr:0x34C80++0x00 line.quad 0x00 "ICH_AP0R0_EL2,Hypervisor Active Priorities Group 0 Register 0" bitfld.quad 0x00 31. "P31,Group 0 interrupt active with priority level 31" "No interrupt,Interrupt" bitfld.quad 0x00 30. "P30,Group 0 interrupt active with priority level 30" "No interrupt,Interrupt" bitfld.quad 0x00 29. "P29,Group 0 interrupt active with priority level 29" "No interrupt,Interrupt" bitfld.quad 0x00 28. "P28,Group 0 interrupt active with priority level 28" "No interrupt,Interrupt" bitfld.quad 0x00 27. "P27,Group 0 interrupt active with priority level 27" "No interrupt,Interrupt" newline bitfld.quad 0x00 26. "P26,Group 0 interrupt active with priority level 26" "No interrupt,Interrupt" bitfld.quad 0x00 25. "P25,Group 0 interrupt active with priority level 25" "No interrupt,Interrupt" bitfld.quad 0x00 24. "P24,Group 0 interrupt active with priority level 24" "No interrupt,Interrupt" bitfld.quad 0x00 23. "P23,Group 0 interrupt active with priority level 23" "No interrupt,Interrupt" bitfld.quad 0x00 22. "P22,Group 0 interrupt active with priority level 22" "No interrupt,Interrupt" newline bitfld.quad 0x00 21. "P21,Group 0 interrupt active with priority level 21" "No interrupt,Interrupt" bitfld.quad 0x00 20. "P20,Group 0 interrupt active with priority level 20" "No interrupt,Interrupt" bitfld.quad 0x00 19. "P19,Group 0 interrupt active with priority level 19" "No interrupt,Interrupt" bitfld.quad 0x00 18. "P18,Group 0 interrupt active with priority level 18" "No interrupt,Interrupt" bitfld.quad 0x00 17. "P17,Group 0 interrupt active with priority level 17" "No interrupt,Interrupt" newline bitfld.quad 0x00 16. "P16,Group 0 interrupt active with priority level 16" "No interrupt,Interrupt" bitfld.quad 0x00 15. "P15,Group 0 interrupt active with priority level 15" "No interrupt,Interrupt" bitfld.quad 0x00 14. "P14,Group 0 interrupt active with priority level 14" "No interrupt,Interrupt" bitfld.quad 0x00 13. "P13,Group 0 interrupt active with priority level 13" "No interrupt,Interrupt" bitfld.quad 0x00 12. "P12,Group 0 interrupt active with priority level 12" "No interrupt,Interrupt" newline bitfld.quad 0x00 11. "P11,Group 0 interrupt active with priority level 11" "No interrupt,Interrupt" bitfld.quad 0x00 10. "P10,Group 0 interrupt active with priority level 10" "No interrupt,Interrupt" bitfld.quad 0x00 9. "P9,Group 0 interrupt active with priority level 9" "No interrupt,Interrupt" bitfld.quad 0x00 8. "P8,Group 0 interrupt active with priority level 8" "No interrupt,Interrupt" bitfld.quad 0x00 7. "P7,Group 0 interrupt active with priority level 7" "No interrupt,Interrupt" newline bitfld.quad 0x00 6. "P6,Group 0 interrupt active with priority level 6" "No interrupt,Interrupt" bitfld.quad 0x00 5. "P5,Group 0 interrupt active with priority level 5" "No interrupt,Interrupt" bitfld.quad 0x00 4. "P4,Group 0 interrupt active with priority level 4" "No interrupt,Interrupt" bitfld.quad 0x00 3. "P3,Group 0 interrupt active with priority level 3" "No interrupt,Interrupt" bitfld.quad 0x00 2. "P2,Group 0 interrupt active with priority level 2" "No interrupt,Interrupt" newline bitfld.quad 0x00 1. "P1,Group 0 interrupt active with priority level 1" "No interrupt,Interrupt" bitfld.quad 0x00 0. "P0,Group 0 interrupt active with priority level 0" "No interrupt,Interrupt" group.quad spr:0x34C90++0x00 line.quad 0x00 "ICH_AP1R0_EL2,Hypervisor Active Priorities Group 1 Register 0" bitfld.quad 0x00 31. "P31,Group 1 interrupt active with priority level 31" "No interrupt,Interrupt" bitfld.quad 0x00 30. "P30,Group 1 interrupt active with priority level 30" "No interrupt,Interrupt" bitfld.quad 0x00 29. "P29,Group 1 interrupt active with priority level 29" "No interrupt,Interrupt" bitfld.quad 0x00 28. "P28,Group 1 interrupt active with priority level 28" "No interrupt,Interrupt" bitfld.quad 0x00 27. "P27,Group 1 interrupt active with priority level 27" "No interrupt,Interrupt" newline bitfld.quad 0x00 26. "P26,Group 1 interrupt active with priority level 26" "No interrupt,Interrupt" bitfld.quad 0x00 25. "P25,Group 1 interrupt active with priority level 25" "No interrupt,Interrupt" bitfld.quad 0x00 24. "P24,Group 1 interrupt active with priority level 24" "No interrupt,Interrupt" bitfld.quad 0x00 23. "P23,Group 1 interrupt active with priority level 23" "No interrupt,Interrupt" bitfld.quad 0x00 22. "P22,Group 1 interrupt active with priority level 22" "No interrupt,Interrupt" newline bitfld.quad 0x00 21. "P21,Group 1 interrupt active with priority level 21" "No interrupt,Interrupt" bitfld.quad 0x00 20. "P20,Group 1 interrupt active with priority level 20" "No interrupt,Interrupt" bitfld.quad 0x00 19. "P19,Group 1 interrupt active with priority level 19" "No interrupt,Interrupt" bitfld.quad 0x00 18. "P18,Group 1 interrupt active with priority level 18" "No interrupt,Interrupt" bitfld.quad 0x00 17. "P17,Group 1 interrupt active with priority level 17" "No interrupt,Interrupt" newline bitfld.quad 0x00 16. "P16,Group 1 interrupt active with priority level 16" "No interrupt,Interrupt" bitfld.quad 0x00 15. "P15,Group 1 interrupt active with priority level 15" "No interrupt,Interrupt" bitfld.quad 0x00 14. "P14,Group 1 interrupt active with priority level 14" "No interrupt,Interrupt" bitfld.quad 0x00 13. "P13,Group 1 interrupt active with priority level 13" "No interrupt,Interrupt" bitfld.quad 0x00 12. "P12,Group 1 interrupt active with priority level 12" "No interrupt,Interrupt" newline bitfld.quad 0x00 11. "P11,Group 1 interrupt active with priority level 11" "No interrupt,Interrupt" bitfld.quad 0x00 10. "P10,Group 1 interrupt active with priority level 10" "No interrupt,Interrupt" bitfld.quad 0x00 9. "P9,Group 1 interrupt active with priority level 9" "No interrupt,Interrupt" bitfld.quad 0x00 8. "P8,Group 1 interrupt active with priority level 8" "No interrupt,Interrupt" bitfld.quad 0x00 7. "P7,Group 1 interrupt active with priority level 7" "No interrupt,Interrupt" newline bitfld.quad 0x00 6. "P6,Group 1 interrupt active with priority level 6" "No interrupt,Interrupt" bitfld.quad 0x00 5. "P5,Group 1 interrupt active with priority level 5" "No interrupt,Interrupt" bitfld.quad 0x00 4. "P4,Group 1 interrupt active with priority level 4" "No interrupt,Interrupt" bitfld.quad 0x00 3. "P3,Group 1 interrupt active with priority level 3" "No interrupt,Interrupt" bitfld.quad 0x00 2. "P2,Group 1 interrupt active with priority level 2" "No interrupt,Interrupt" newline bitfld.quad 0x00 1. "P1,Group 1 interrupt active with priority level 1" "No interrupt,Interrupt" bitfld.quad 0x00 0. "P0,Group 1 interrupt active with priority level 0" "No interrupt,Interrupt" tree.end newline rgroup.quad spr:0x34CB3++0x00 line.quad 0x00 "ICH_EISR_EL2,End of Interrupt Status Register" bitfld.quad 0x00 3. "STATUS3,EOI maintenance interrupt status bit for List register ICH_LR3_EL2" "No interrupt,Interrupt" bitfld.quad 0x00 2. "STATUS2,EOI maintenance interrupt status bit for List register ICH_LR2_EL2" "No interrupt,Interrupt" bitfld.quad 0x00 1. "STATUS1,EOI maintenance interrupt status bit for List register ICH_LR1_EL2" "No interrupt,Interrupt" bitfld.quad 0x00 0. "STATUS0,EOI maintenance interrupt status bit for List register ICH_LR0_EL2" "No interrupt,Interrupt" rgroup.quad spr:0x34CB5++0x00 line.quad 0x00 "ICH_ELRSR_EL2,Empty List Register Status Register" bitfld.quad 0x00 3. "STATUS3,Status bit for List register ICH_LR3_EL2" "No interrupt,Interrupt" bitfld.quad 0x00 2. "STATUS2,Status bit for List register ICH_LR2_EL2" "No interrupt,Interrupt" bitfld.quad 0x00 1. "STATUS1,Status bit for List register ICH_LR1_EL2" "No interrupt,Interrupt" bitfld.quad 0x00 0. "STATUS0,Status bit for List register ICH_LR0_EL2" "No interrupt,Interrupt" group.quad spr:0x34CB0++0x00 line.quad 0x00 "ICH_HCR_EL2,Hypervisor Control Register" bitfld.quad 0x00 27.--31. "EOICOUNT,Incremented whenever a successful write to a virtual EOIR or DIR register would have resulted in a virtual interrupt deactivation" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.quad 0x00 14. "TDIR,Trap Non-secure EL1 writes to ICC_DIR_EL1 and ICV_DIR" "No trap,Trap" bitfld.quad 0x00 13. "TSEI,Trap all locally generated SEIs" "No trap," newline bitfld.quad 0x00 12. "TALL1,Trap all Non-secure EL1 accesses to ICC_* and ICV* System registers for Group 1 interrupts to EL2" "No trap,Trap" bitfld.quad 0x00 11. "TALL0,Trap all Non-secure EL1 accesses to ICC_* and ICV* System registers for Group 0 interrupts to EL2" "No trap,Trap" bitfld.quad 0x00 10. "TC,Trap all Non-secure EL1 accesses to System registers that are common to Group 0 and Group 1 to EL2" "No trap,Trap" newline bitfld.quad 0x00 7. "VGRP1DIE,VM Group 1 Disabled Interrupt Enable" "Disabled,Enabled" bitfld.quad 0x00 6. "VGRP1EIE,VM Group 1 Enabled Interrupt Enable" "Disabled,Enabled" newline bitfld.quad 0x00 5. "VGRP0DIE,VM Group 0 Disabled Interrupt Enable" "Disabled,Enabled" bitfld.quad 0x00 4. "VGRP0EIE,VM Group 0 Enabled Interrupt Enable" "Disabled,Enabled" bitfld.quad 0x00 3. "NPIE,No Pending Interrupt Enable" "Disabled,Enabled" newline bitfld.quad 0x00 2. "LRENPIE,List Register Entry Not Present Interrupt Enable" "Disabled,Enabled" bitfld.quad 0x00 1. "UIE,Underflow Interrupt Enable" "Disabled,Enabled" bitfld.quad 0x00 0. "EN,Global enable bit for the virtual CPU interface" "Disabled,Enabled" if (((per.q(spr:0x34CC0))&0x2000000000000000)==0x0) group.quad spr:0x34CC0++0x00 line.quad 0x00 "ICH_LR0_EL2,List Register 0" bitfld.quad 0x00 62.--63. "STATE,The state of the interrupt" "Inactive,Pending,Active,Pending/Active" bitfld.quad 0x00 61. "HW,Indicates whether this virtual interrupt maps directly to a hardware interrupt" "Software,Hardware" bitfld.quad 0x00 60. "GROUP,Indicates the group for this virtual interrupt" "Group 0,Group 1" hexmask.quad.byte 0x00 48.--55. 1. "PRIORITY,The priority of this interrupt" newline bitfld.quad 0x00 41. "EOI,Maintenance interrupt assertion" "Not asserted,Asserted" hexmask.quad.long 0x00 0.--31. 1. "VINTID,Virtual INTID of the interrupt" else group.quad spr:0x34CC0++0x00 line.quad 0x00 "ICH_LR0_EL2,List Register 0" bitfld.quad 0x00 62.--63. "STATE,The state of the interrupt" "Inactive,Pending,Active,Pending/Active" bitfld.quad 0x00 61. "HW,Indicates whether this virtual interrupt maps directly to a hardware interrupt" "Software,Hardware" bitfld.quad 0x00 60. "GROUP,Indicates the group for this virtual interrupt" "Group 0,Group 1" hexmask.quad.byte 0x00 48.--55. 1. "PRIORITY,The priority of this interrupt" newline hexmask.quad.word 0x00 32.--41. 1. "PINTID,Physical interrupt ID for hardware interrupts" hexmask.quad.long 0x00 0.--31. 1. "VINTID,Virtual INTID of the interrupt" endif if (((per.q(spr:0x34CC1))&0x2000000000000000)==0x0) group.quad spr:0x34CC1++0x00 line.quad 0x00 "ICH_LR1_EL2,List Register 1" bitfld.quad 0x00 62.--63. "STATE,The state of the interrupt" "Inactive,Pending,Active,Pending/Active" bitfld.quad 0x00 61. "HW,Indicates whether this virtual interrupt maps directly to a hardware interrupt" "Software,Hardware" bitfld.quad 0x00 60. "GROUP,Indicates the group for this virtual interrupt" "Group 0,Group 1" hexmask.quad.byte 0x00 48.--55. 1. "PRIORITY,The priority of this interrupt" newline bitfld.quad 0x00 41. "EOI,Maintenance interrupt assertion" "Not asserted,Asserted" hexmask.quad.long 0x00 0.--31. 1. "VINTID,Virtual INTID of the interrupt" else group.quad spr:0x34CC1++0x00 line.quad 0x00 "ICH_LR1_EL2,List Register 1" bitfld.quad 0x00 62.--63. "STATE,The state of the interrupt" "Inactive,Pending,Active,Pending/Active" bitfld.quad 0x00 61. "HW,Indicates whether this virtual interrupt maps directly to a hardware interrupt" "Software,Hardware" bitfld.quad 0x00 60. "GROUP,Indicates the group for this virtual interrupt" "Group 0,Group 1" hexmask.quad.byte 0x00 48.--55. 1. "PRIORITY,The priority of this interrupt" newline hexmask.quad.word 0x00 32.--41. 1. "PINTID,Physical interrupt ID for hardware interrupts" hexmask.quad.long 0x00 0.--31. 1. "VINTID,Virtual INTID of the interrupt" endif if (((per.q(spr:0x34CC2))&0x2000000000000000)==0x0) group.quad spr:0x34CC2++0x00 line.quad 0x00 "ICH_LR2_EL2,List Register 2" bitfld.quad 0x00 62.--63. "STATE,The state of the interrupt" "Inactive,Pending,Active,Pending/Active" bitfld.quad 0x00 61. "HW,Indicates whether this virtual interrupt maps directly to a hardware interrupt" "Software,Hardware" bitfld.quad 0x00 60. "GROUP,Indicates the group for this virtual interrupt" "Group 0,Group 1" hexmask.quad.byte 0x00 48.--55. 1. "PRIORITY,The priority of this interrupt" newline bitfld.quad 0x00 41. "EOI,Maintenance interrupt assertion" "Not asserted,Asserted" hexmask.quad.long 0x00 0.--31. 1. "VINTID,Virtual INTID of the interrupt" else group.quad spr:0x34CC2++0x00 line.quad 0x00 "ICH_LR2_EL2,List Register 2" bitfld.quad 0x00 62.--63. "STATE,The state of the interrupt" "Inactive,Pending,Active,Pending/Active" bitfld.quad 0x00 61. "HW,Indicates whether this virtual interrupt maps directly to a hardware interrupt" "Software,Hardware" bitfld.quad 0x00 60. "GROUP,Indicates the group for this virtual interrupt" "Group 0,Group 1" hexmask.quad.byte 0x00 48.--55. 1. "PRIORITY,The priority of this interrupt" newline hexmask.quad.word 0x00 32.--41. 1. "PINTID,Physical interrupt ID for hardware interrupts" hexmask.quad.long 0x00 0.--31. 1. "VINTID,Virtual INTID of the interrupt" endif if (((per.q(spr:0x34CC3))&0x2000000000000000)==0x0) group.quad spr:0x34CC3++0x00 line.quad 0x00 "ICH_LR3_EL2,List Register 3" bitfld.quad 0x00 62.--63. "STATE,The state of the interrupt" "Inactive,Pending,Active,Pending/Active" bitfld.quad 0x00 61. "HW,Indicates whether this virtual interrupt maps directly to a hardware interrupt" "Software,Hardware" bitfld.quad 0x00 60. "GROUP,Indicates the group for this virtual interrupt" "Group 0,Group 1" hexmask.quad.byte 0x00 48.--55. 1. "PRIORITY,The priority of this interrupt" newline bitfld.quad 0x00 41. "EOI,Maintenance interrupt assertion" "Not asserted,Asserted" hexmask.quad.long 0x00 0.--31. 1. "VINTID,Virtual INTID of the interrupt" else group.quad spr:0x34CC3++0x00 line.quad 0x00 "ICH_LR3_EL2,List Register 3" bitfld.quad 0x00 62.--63. "STATE,The state of the interrupt" "Inactive,Pending,Active,Pending/Active" bitfld.quad 0x00 61. "HW,Indicates whether this virtual interrupt maps directly to a hardware interrupt" "Software,Hardware" bitfld.quad 0x00 60. "GROUP,Indicates the group for this virtual interrupt" "Group 0,Group 1" hexmask.quad.byte 0x00 48.--55. 1. "PRIORITY,The priority of this interrupt" newline hexmask.quad.word 0x00 32.--41. 1. "PINTID,Physical interrupt ID for hardware interrupts" hexmask.quad.long 0x00 0.--31. 1. "VINTID,Virtual INTID of the interrupt" endif rgroup.quad spr:0x34CB2++0x00 line.quad 0x00 "ICH_MISR_EL2,Maintenance Interrupt State Register" bitfld.quad 0x00 7. "VGRP1D,vPE Group 1 Disabled maintenance interrupt assertion" "Not asserted,Asserted" bitfld.quad 0x00 6. "VGRP1E,vPE Group 1 Enabled maintenance interrupt assertion" "Not asserted,Asserted" bitfld.quad 0x00 5. "VGRP0D,vPE Group 0 Disabled maintenance interrupt assertion" "Not asserted,Asserted" bitfld.quad 0x00 4. "VGRP0E,vPE Group 0 Enabled maintenance interrupt assertion" "Not asserted,Asserted" newline bitfld.quad 0x00 3. "NP,No Pending maintenance interrupt assertion" "Not asserted,Asserted" bitfld.quad 0x00 2. "LRENP,List Register Entry Not Present maintenance interrupt assertion" "Not asserted,Asserted" bitfld.quad 0x00 1. "U,Underflow maintenance interrupt assertion" "Not asserted,Asserted" bitfld.quad 0x00 0. "EOI,End of Interrupt maintenance interrupt assertion" "Not asserted,Asserted" group.quad spr:0x34CB7++0x00 line.quad 0x00 "ICH_VMCR_EL2,Virtual Machine Control Register" hexmask.quad.byte 0x00 24.--31. 1. "VPMR,Virtual Priority Mask" bitfld.quad 0x00 21.--23. "VBPR0,Interrupt Priority Field Control And Interrupt Preemption Control" "Reserved,Reserved,[7:3]-[2:0],[7:4]-[3:0],[7:5]-[4:0],[7:6]-[5:0],[7]-[6:0],No preemption-[7:0]" bitfld.quad 0x00 18.--20. "VBPR1,Interrupt Priority Field Control And Interrupt Preemption Control" "Reserved,Reserved,[7:2]-[1:0],[7:3]-[2:0],[7:4]-[3:0],[7:5]-[4:0],[7:6]-[5:0],[7]-[6:0]" bitfld.quad 0x00 9. "VEOIM,Virtual EOI mode. Controls whether a write to an End of Interrupt register also deactivates the virtual interrupt" "Both,Priority drop" newline bitfld.quad 0x00 4. "VCBPR,Decides whether both interrupt groups are controlled by ICV_BPR0_EL1" "Separate,Both" bitfld.quad 0x00 3. "VFIQEN,Virtual FIQ enable" "Reserved,Enabled" bitfld.quad 0x00 1. "VENG1,Virtual Group 1 interrupt enable" "Disabled,Enabled" bitfld.quad 0x00 0. "VENG0,Virtual Group 0 interrupt enable" "Disabled,Enabled" rgroup.quad spr:0x34CB1++0x00 line.quad 0x00 "ICH_VTR_EL2,VGIC Type Register" bitfld.quad 0x00 29.--31. "PRIBITS,The number of virtual priority bits implemented" "Reserved,Reserved,Reserved,Reserved,5,?..." bitfld.quad 0x00 26.--28. "PREBITS,The number of virtual preemption bits implemented" "Reserved,Reserved,Reserved,Reserved,5,?..." bitfld.quad 0x00 23.--25. "IDBITS,The number of virtual interrupt identifier bits supported" "16 bits,?..." bitfld.quad 0x00 22. "SEIS,SEI Support" "Not supported," newline bitfld.quad 0x00 21. "A3V,Affinity 3 Valid" "Reserved,Valid" bitfld.quad 0x00 20. "NV4,GICv4 direct injection of virtual interrupts not supported" "Supported," bitfld.quad 0x00 19. "TDS,Separate trapping of Non-secure EL1 writes to ICV_DIR_EL1 supported" "Reserved,Supported" bitfld.quad 0x00 0.--4. "LISTREGS,The number of implemented List registers" "Reserved,Reserved,Reserved,4,?..." tree.end tree.end tree "Debug Registers" rgroup.quad spr:0x23010++0x00 line.quad 0x00 "MDCCSR_EL0,Debug Comms Channel Status Register" bitfld.quad 0x00 30. "RXFULL,DBGDTRRX Register full" "Empty,Full" bitfld.quad 0x00 29. "TXFULL,DBGDTRTX Register full" "Empty,Full" group.quad spr:0x20020++0x00 line.quad 0x00 "MDCCINT_EL1,Debug Comms Channel Interrupt Enable register" bitfld.quad 0x00 30. "RX,DCC interrupt enable controls" "Disabled,Enabled" bitfld.quad 0x00 29. "TX,DCC interrupt enable controls" "Disabled,Enabled" group.quad spr:0x23040++0x00 line.quad 0x00 "DBGDTR_EL0,Half Duplex Data Transfer Register" rgroup.quad spr:0x23050++0x00 line.quad 0x00 "DBGDTRRX_EL0,Full Duplex Receive Data Transfer Register" wgroup.quad spr:0x23050++0x00 line.quad 0x00 "DBGDTRTX_EL0,Full Duplex Transmit Data Transfer Register" group.quad spr:0x24070++0x00 line.quad 0x00 "DBGVCR32_EL2,Vector Catch Register" bitfld.quad 0x00 31. "NSF,FIQ vector catch enable in Non-secure state" "Disabled,Enabled" bitfld.quad 0x00 30. "NSI,IRQ vector catch enable in Non-secure state" "Disabled,Enabled" bitfld.quad 0x00 28. "NSD,Data Abort vector catch enable in Non-secure state" "Disabled,Enabled" bitfld.quad 0x00 27. "NSP,Prefetch Abort vector catch enable in Non-secure state" "Disabled,Enabled" newline bitfld.quad 0x00 26. "NSS,Supervisor Call (SVC) vector catch enable in Non-secure state" "Disabled,Enabled" bitfld.quad 0x00 25. "NSU,Undefined Instruction vector catch enable in Non-secure state" "Disabled,Enabled" bitfld.quad 0x00 7. "SF,FIQ vector catch enable in Secure state" "Disabled,Enabled" bitfld.quad 0x00 6. "SI,IRQ vector catch enable in Secure state" "Disabled,Enabled" newline bitfld.quad 0x00 4. "SD,Data Abort vector catch enable in Secure state" "Disabled,Enabled" bitfld.quad 0x00 3. "SP,Prefetch Abort vector catch enable in Secure state" "Disabled,Enabled" bitfld.quad 0x00 2. "SS,Supervisor Call (SVC) vector catch enable in Secure state" "Disabled,Enabled" bitfld.quad 0x00 1. "SU,Undefined Instruction vector catch enable in Secure state" "Disabled,Enabled" group.quad spr:0x20002++0x00 line.quad 0x00 "OSDTRRX_EL1,OS Lock Data Transfer Register" if (((per.q(spr:0x20114)&0x02)==0x00)) group.quad spr:0x20022++0x00 line.quad 0x00 "MDSCR_EL1,Monitor Debug System Control Register" rbitfld.quad 0x00 30. "RXFULL,Save/restore of EDSCR.RXfull" "Empty,Full" rbitfld.quad 0x00 29. "TXFULL,Save/restore of EDSCR.TXfull" "Empty,Full" rbitfld.quad 0x00 27. "RXO,Save/restore of EDSCR.RXO" "Low,High" rbitfld.quad 0x00 26. "TXU,Save/restore of EDSCR.TXU" "Low,High" newline rbitfld.quad 0x00 22.--23. "INTDIS,Save/restore of EDSCR.INTDIS" "0,1,2,3" rbitfld.quad 0x00 21. "TDA,Save/restore of EDSCR.TDA" "Low,High" bitfld.quad 0x00 15. "MDE,Monitor debug events" "Disabled,Enabled" rbitfld.quad 0x00 14. "HDE,Save/restore of EDSCR.HDE" "Low,High" newline bitfld.quad 0x00 13. "KDE,Local (kernel) debug enable" "Disabled,Enabled" bitfld.quad 0x00 12. "TDCC,Traps EL0 accesses to the DCC registers to EL1" "No trap,Trap" rbitfld.quad 0x00 6. "ERR,Save/restore of EDSCR.ERR" "Low,High" bitfld.quad 0x00 0. "SS,Software step control" "Disabled,Enabled" else group.quad spr:0x20022++0x00 line.quad 0x00 "MDSCR_EL1,Monitor Debug System Control Register" bitfld.quad 0x00 30. "RXFULL,Save/restore of EDSCR.RXfull" "Empty,Full" bitfld.quad 0x00 29. "TXFULL,Save/restore of EDSCR.TXfull" "Empty,Full" bitfld.quad 0x00 27. "RXO,Save/restore of EDSCR.RXO" "Low,High" bitfld.quad 0x00 26. "TXU,Save/restore of EDSCR.TXU" "Low,High" newline bitfld.quad 0x00 22.--23. "INTDIS,Save/restore of EDSCR.INTDIS" "0,1,2,3" bitfld.quad 0x00 21. "TDA,Save/restore of EDSCR.TDA" "Low,High" bitfld.quad 0x00 15. "MDE,Monitor debug events" "Disabled,Enabled" bitfld.quad 0x00 14. "HDE,Save/restore of EDSCR.HDE" "Low,High" newline bitfld.quad 0x00 13. "KDE,Local (kernel) debug enable" "Disabled,Enabled" bitfld.quad 0x00 12. "TDCC,Traps EL0 accesses to the DCC registers to EL1" "No trap,Trap" bitfld.quad 0x00 6. "ERR,Save/restore of EDSCR.ERR" "Low,High" bitfld.quad 0x00 0. "SS,Software step control" "Disabled,Enabled" endif group.quad spr:0x20032++0x00 line.quad 0x00 "OSDTRTX_EL1,OS Lock Data Transfer Register" group.quad spr:0x20062++0x00 line.quad 0x00 "OSECCR_EL1,OS Lock Exception Catch Control Register" bitfld.quad 0x00 7. 15. "NS[3],Coarse-grained Non-secure exception catch/return bit NSE[3] and NSR[3]" "No action/No action,Halt/Halt,Halt/Halt,Halt/No action" bitfld.quad 0x00 6. 14. "NS[2],Coarse-grained Non-secure exception catch/return bit NSE[2] and NSR[2]" "No action/No action,Halt/Halt,Halt/Halt,Halt/No action" bitfld.quad 0x00 5. 13. "NS[1],Coarse-grained Non-secure exception catch/return bit NSE[1] and NSR[1]" "No action/No action,Halt/Halt,Halt/Halt,Halt/No action" bitfld.quad 0x00 4. 12. "NS[0],Coarse-grained Non-secure exception catch/return bit NSE[0] and NSR[0]" "No action/No action,Halt/Halt,Halt/Halt,Halt/No action" newline bitfld.quad 0x00 3. 11. "S[3],Coarse-grained Secure exception catch/return bit SE[3] and SR[3]" "No action/No action,Halt/Halt,Halt/Halt,Halt/No action" bitfld.quad 0x00 2. 10. "S[2],Coarse-grained Secure exception catch/return bit SE[2] and SR[2]" "No action/No action,Halt/Halt,Halt/Halt,Halt/No action" bitfld.quad 0x00 1. 9. "S[1],Coarse-grained Secure exception catch/return bit SE[1] and SR[1]" "No action/No action,Halt/Halt,Halt/Halt,Halt/No action" bitfld.quad 0x00 0. 8. "S[0],Coarse-grained Secure exception catch/return bit SE[0] and SR[0]" "No action/No action,Halt/Halt,Halt/Halt,Halt/No action" rgroup.quad spr:0x20100++0x00 line.quad 0x00 "MDRAR_EL1,Debug ROM Address Register" wgroup.quad spr:0x20104++0x00 line.quad 0x00 "OSLAR_EL1,OS Lock Access Register" bitfld.quad 0x00 0. "OSLK,OS lock" "Unlock,Lock" rgroup.quad spr:0x20114++0x00 line.quad 0x00 "OSLSR_EL1,OS Lock Status Register" bitfld.quad 0x00 2. "NTT,Not 32-bit access" "Low,High" bitfld.quad 0x00 1. "OSLK,OS lock status" "Not locked,Locked" bitfld.quad 0x00 0. 3. "OSLM,OS lock model implemented field" "Reserved,Reserved,Implemented,?..." group.quad spr:0x20134++0x00 line.quad 0x00 "OSDLR_EL1,OS Double-lock Register" bitfld.quad 0x00 0. "DLK,OS double-lock control" "Not locked,Locked" group.quad spr:0x20144++0x00 line.quad 0x00 "DBGPRCR_EL1,Debug Power/Reset Control Register" bitfld.quad 0x00 0. "CORENPDRQ,Core no powerdown request" "Powered down,Emulated" group.quad spr:0x20786++0x00 line.quad 0x00 "DBGCLAIMSET_EL1,Claim Tag register Set" bitfld.quad 0x0 7. "CT7,Claim Tag 7 Set" "Not set,Set" bitfld.quad 0x0 6. "CT6,Claim Tag 6 Set" "Not set,Set" bitfld.quad 0x0 5. "CT5,Claim Tag 5 Set" "Not set,Set" bitfld.quad 0x0 4. "CT4,Claim Tag 4 Set" "Not set,Set" newline bitfld.quad 0x0 3. "CT3,Claim Tag 3 Set" "Not set,Set" bitfld.quad 0x0 2. "CT2,Claim Tag 2 Set" "Not set,Set" bitfld.quad 0x0 1. "CT1,Claim Tag 1 Set" "Not set,Set" bitfld.quad 0x0 0. "CT0,Claim Tag 0 Set" "Not set,Set" group.quad spr:0x20796++0x00 line.quad 0x00 "DBGCLAIMCLR_EL1,Claim Tag register Clear" bitfld.quad 0x0 7. "CT7,Claim Tag 7 Clear" "Not cleared,Cleared" bitfld.quad 0x0 6. "CT6,Claim Tag 6 Clear" "Not cleared,Cleared" bitfld.quad 0x0 5. "CT5,Claim Tag 5 Clear" "Not cleared,Cleared" bitfld.quad 0x0 4. "CT4,Claim Tag 4 Clear" "Not cleared,Cleared" newline bitfld.quad 0x0 3. "CT3,Claim Tag 3 Clear" "Not cleared,Cleared" bitfld.quad 0x0 2. "CT2,Claim Tag 2 Clear" "Not cleared,Cleared" bitfld.quad 0x0 1. "CT1,Claim Tag 1 Clear" "Not cleared,Cleared" bitfld.quad 0x0 0. "CT0,Claim Tag 0 Clear" "Not cleared,Cleared" rgroup.quad spr:0x207e6++0x00 line.quad 0x00 "DBGAUTHSTATUS_EL1,Authentication Status register" bitfld.quad 0x00 7. "SNI,Secure non-invasive debug implemented" "Not implemented,Implemented" bitfld.quad 0x00 6. "SNE,Secure non-invasive debug enabled" "Disabled,Enabled" bitfld.quad 0x00 5. "SI,Secure invasive debug implemented" "Not implemented,Implemented" bitfld.quad 0x00 4. "SE,Secure invasive debug enabled" "Disabled,Enabled" newline bitfld.quad 0x00 3. "NSNI,Non-secure non-invasive debug implemented" "Not implemented,Implemented" bitfld.quad 0x00 2. "NSNE,Non-secure non-invasive debug enabled" "Disabled,Enabled" bitfld.quad 0x00 1. "NSI,Non-secure invasive debug implemented" "Not implemented,Implemented" bitfld.quad 0x00 0. "NSE,Non-secure invasive debug enabled" "Disabled,Enabled" if (((per.q(spr:0x30400))&0x10)==0x10) group.quad spr:0x30400++0x00 line.quad 0x00 "SPSR_EL1,Saved Program Status Register" bitfld.quad 0x00 31. "N,Negative condition flag" "Not negative,Negative" bitfld.quad 0x00 30. "Z,Zero condition flag" "Not zero,Zero" bitfld.quad 0x00 29. "C,Carry condition flag" "Not carry,Carry" bitfld.quad 0x00 28. "V,Overflow condition flag" "No overflow,Overflow" newline bitfld.quad 0x00 27. "Q,Cumulative condition flag" "Not occurred,Occurred" bitfld.quad 0x00 22. "PAN,Privileged Access Never" "No,Yes" bitfld.quad 0x00 21. "SS,Software step" "0,1" bitfld.quad 0x00 20. "IL,Illegal Execution state" "0,1" newline bitfld.quad 0x00 14.--15. 25.--26. "IT[4:7],IT block state bits for the T32 IT (If-Then) instruction - base condition for the IT block" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.quad 0x00 10.--13. "IT[0:3],IT block state bits for the T32 IT (If-Then) instruction - size of the IT block" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.quad 0x00 16.--19. "GE,Greater than or Equal flags" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.quad 0x00 9. "E,Endianness state bit" "Little,Big" newline bitfld.quad 0x00 8. "A,Asynchronous data abort mask bit" "Not masked,Masked" bitfld.quad 0x00 7. "I,IRQ mask bit" "Not masked,Masked" bitfld.quad 0x00 6. "F,FIQ mask bit" "Not masked,Masked" bitfld.quad 0x00 5. "T,T32 Instruction set state" "A32,T32" newline bitfld.quad 0x00 4. "M[4],Execution state that the exception was taken from" "AArch64,AArch32" bitfld.quad 0x00 0.--3. "M[3:0],Current PE mode" "User,FIQ,IRQ,Supervisor,,,,Abort,,,Hyp,Undefined,,,,System" else group.quad spr:0x30400++0x00 line.quad 0x00 "SPSR_EL1,Saved Program Status Register" bitfld.quad 0x00 31. "N,Negative condition flag" "Not negative,Negative" bitfld.quad 0x00 30. "Z,Zero condition flag" "Not zero,Zero" bitfld.quad 0x00 29. "C,Carry condition flag" "Not carry,Carry" bitfld.quad 0x00 28. "V,Overflow condition flag" "No overflow,Overflow" newline bitfld.quad 0x00 27. "Q,Cumulative condition flag" "Not occurred,Occurred" bitfld.quad 0x00 23. "UAO,User Access Override" "Standard routines,New routines" bitfld.quad 0x00 22. "PAN,Privileged Access Never" "No,Yes" bitfld.quad 0x00 21. "SS,Software step" "0,1" newline bitfld.quad 0x00 20. "IL,Illegal Execution state" "0,1" bitfld.quad 0x00 14.--15. 25.--26. "IT[4:7],IT block state bits for the T32 IT (If-Then) instruction - base condition for the IT block" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.quad 0x00 10.--13. "IT[0:3],IT block state bits for the T32 IT (If-Then) instruction - size of the IT block" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.quad 0x00 16.--19. "GE,Greater than or Equal flags" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.quad 0x00 9. "E,Endianness state bit" "Little,Big" bitfld.quad 0x00 8. "A,Asynchronous data abort mask bit" "Not masked,Masked" bitfld.quad 0x00 7. "I,IRQ mask bit" "Not masked,Masked" bitfld.quad 0x00 6. "F,FIQ mask bit" "Not masked,Masked" newline bitfld.quad 0x00 5. "T,T32 Instruction set state" "A32,T32" bitfld.quad 0x00 4. "M[4],Execution state that the exception was taken from" "AArch64,AArch32" bitfld.quad 0x00 0.--3. "M[3:0],Current PE mode" "El0t,,,,EL1t,EL1h,?..." endif if (((per.q(spr:0x34400))&0x10)==0x10) group.quad spr:0x34400++0x00 line.quad 0x00 "SPSR_EL2,Saved Program Status Register" bitfld.quad 0x00 31. "N,Negative condition flag" "Not negative,Negative" bitfld.quad 0x00 30. "Z,Zero condition flag" "Not zero,Zero" bitfld.quad 0x00 29. "C,Carry condition flag" "Not carry,Carry" bitfld.quad 0x00 28. "V,Overflow condition flag" "No overflow,Overflow" newline bitfld.quad 0x00 27. "Q,Cumulative condition flag" "Not occurred,Occurred" bitfld.quad 0x00 22. "PAN,Privileged Access Never" "No,Yes" bitfld.quad 0x00 21. "SS,Software step" "0,1" bitfld.quad 0x00 20. "IL,Illegal Execution state" "0,1" newline bitfld.quad 0x00 14.--15. 25.--26. "IT[4:7],IT block state bits for the T32 IT (If-Then) instruction - base condition for the IT block" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.quad 0x00 10.--13. "IT[0:3],IT block state bits for the T32 IT (If-Then) instruction - size of the IT block" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.quad 0x00 16.--19. "GE,Greater than or Equal flags" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.quad 0x00 9. "E,Endianness state bit" "Little,Big" newline bitfld.quad 0x00 8. "A,Asynchronous data abort mask bit" "Not masked,Masked" bitfld.quad 0x00 7. "I,IRQ mask bit" "Not masked,Masked" bitfld.quad 0x00 6. "F,FIQ mask bit" "Not masked,Masked" bitfld.quad 0x00 5. "T,T32 Instruction set state" "A32,T32" newline bitfld.quad 0x00 4. "M[4],Execution state that the exception was taken from" "AArch64,AArch32" bitfld.quad 0x00 0.--3. "M[3:0],Current PE mode" "User,FIQ,IRQ,Supervisor,,,,Abort,,,Hyp,Undefined,,,,System" else group.quad spr:0x34400++0x00 line.quad 0x00 "SPSR_EL2,Saved Program Status Register" bitfld.quad 0x00 31. "N,Negative condition flag" "Not negative,Negative" bitfld.quad 0x00 30. "Z,Zero condition flag" "Not zero,Zero" bitfld.quad 0x00 29. "C,Carry condition flag" "Not carry,Carry" bitfld.quad 0x00 28. "V,Overflow condition flag" "No overflow,Overflow" newline bitfld.quad 0x00 27. "Q,Cumulative condition flag" "Not occurred,Occurred" bitfld.quad 0x00 23. "UAO,User Access Override" "Standard routines,New routines" bitfld.quad 0x00 22. "PAN,Privileged Access Never" "No,Yes" bitfld.quad 0x00 21. "SS,Software step" "0,1" newline bitfld.quad 0x00 20. "IL,Illegal Execution state" "0,1" bitfld.quad 0x00 14.--15. 25.--26. "IT[4:7],IT block state bits for the T32 IT (If-Then) instruction - base condition for the IT block" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.quad 0x00 10.--13. "IT[0:3],IT block state bits for the T32 IT (If-Then) instruction - size of the IT block" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.quad 0x00 16.--19. "GE,Greater than or Equal flags" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.quad 0x00 9. "E,Endianness state bit" "Little,Big" bitfld.quad 0x00 8. "A,Asynchronous data abort mask bit" "Not masked,Masked" bitfld.quad 0x00 7. "I,IRQ mask bit" "Not masked,Masked" bitfld.quad 0x00 6. "F,FIQ mask bit" "Not masked,Masked" newline bitfld.quad 0x00 5. "T,T32 Instruction set state" "A32,T32" bitfld.quad 0x00 4. "M[4],Execution state that the exception was taken from" "AArch64,AArch32" bitfld.quad 0x00 0.--3. "M[3:0],Current PE mode" "El0t,,,,EL1t,EL1h,?..." endif if (((per.q(spr:0x36400))&0x10)==0x10) group.quad spr:0x36400++0x00 line.quad 0x00 "SPSR_EL3,Saved Program Status Register" bitfld.quad 0x00 31. "N,Negative condition flag" "Not negative,Negative" bitfld.quad 0x00 30. "Z,Zero condition flag" "Not zero,Zero" bitfld.quad 0x00 29. "C,Carry condition flag" "Not carry,Carry" bitfld.quad 0x00 28. "V,Overflow condition flag" "No overflow,Overflow" newline bitfld.quad 0x00 27. "Q,Cumulative condition flag" "Not occurred,Occurred" bitfld.quad 0x00 22. "PAN,Privileged Access Never" "No,Yes" bitfld.quad 0x00 21. "SS,Software step" "0,1" bitfld.quad 0x00 20. "IL,Illegal Execution state" "0,1" newline bitfld.quad 0x00 14.--15. 25.--26. "IT[4:7],IT block state bits for the T32 IT (If-Then) instruction - base condition for the IT block" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.quad 0x00 10.--13. "IT[0:3],IT block state bits for the T32 IT (If-Then) instruction - size of the IT block" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.quad 0x00 16.--19. "GE,Greater than or Equal flags" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.quad 0x00 9. "E,Endianness state bit" "Little,Big" newline bitfld.quad 0x00 8. "A,Asynchronous data abort mask bit" "Not masked,Masked" bitfld.quad 0x00 7. "I,IRQ mask bit" "Not masked,Masked" bitfld.quad 0x00 6. "F,FIQ mask bit" "Not masked,Masked" bitfld.quad 0x00 5. "T,T32 Instruction set state" "A32,T32" newline bitfld.quad 0x00 4. "M[4],Execution state that the exception was taken from" "AArch64,AArch32" bitfld.quad 0x00 0.--3. "M[3:0],Current PE mode" "User,FIQ,IRQ,Supervisor,,,,Abort,,,Hyp,Undefined,,,,System" else group.quad spr:0x36400++0x00 line.quad 0x00 "SPSR_EL3,Saved Program Status Register" bitfld.quad 0x00 31. "N,Negative condition flag" "Not negative,Negative" bitfld.quad 0x00 30. "Z,Zero condition flag" "Not zero,Zero" bitfld.quad 0x00 29. "C,Carry condition flag" "Not carry,Carry" bitfld.quad 0x00 28. "V,Overflow condition flag" "No overflow,Overflow" newline bitfld.quad 0x00 27. "Q,Cumulative condition flag" "Not occurred,Occurred" bitfld.quad 0x00 23. "UAO,User Access Override" "Standard routines,New routines" bitfld.quad 0x00 22. "PAN,Privileged Access Never" "No,Yes" bitfld.quad 0x00 21. "SS,Software step" "0,1" newline bitfld.quad 0x00 20. "IL,Illegal Execution state" "0,1" bitfld.quad 0x00 14.--15. 25.--26. "IT[4:7],IT block state bits for the T32 IT (If-Then) instruction - base condition for the IT block" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.quad 0x00 10.--13. "IT[0:3],IT block state bits for the T32 IT (If-Then) instruction - size of the IT block" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.quad 0x00 16.--19. "GE,Greater than or Equal flags" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.quad 0x00 9. "E,Endianness state bit" "Little,Big" bitfld.quad 0x00 8. "A,Asynchronous data abort mask bit" "Not masked,Masked" bitfld.quad 0x00 7. "I,IRQ mask bit" "Not masked,Masked" bitfld.quad 0x00 6. "F,FIQ mask bit" "Not masked,Masked" newline bitfld.quad 0x00 5. "T,T32 Instruction set state" "A32,T32" bitfld.quad 0x00 4. "M[4],Execution state that the exception was taken from" "AArch64,AArch32" bitfld.quad 0x00 0.--3. "M[3:0],Current PE mode" "El0t,,,,EL1t,EL1h,?..." endif if (((per.q(spr:0x33450))&0x10)==0x10) group.quad spr:0x33450++0x00 line.quad 0x00 "DSPSR_EL0,Debug Saved Processor Status Register" bitfld.quad 0x00 31. "N,Negative condition flag" "Not negative,Negative" bitfld.quad 0x00 30. "Z,Zero condition flag" "Not zero,Zero" bitfld.quad 0x00 29. "C,Carry condition flag" "Not carry,Carry" bitfld.quad 0x00 28. "V,Overflow condition flag" "No overflow,Overflow" newline bitfld.quad 0x00 27. "Q,Cumulative condition flag" "Not occurred,Occurred" bitfld.quad 0x00 22. "PAN,Privileged Access Never" "No,Yes" bitfld.quad 0x00 21. "SS,Software step" "0,1" bitfld.quad 0x00 20. "IL,Illegal Execution state" "0,1" newline bitfld.quad 0x00 13.--15. "IT[5:7],IT block state bits for the T32 IT (If-Then) instruction - base condition for the IT block" "0,1,2,3,4,5,6,7" bitfld.quad 0x00 25.--26. 10.--12. "IT[0:4],IT block state bits for the T32 IT (If-Then) instruction - size of the IT block" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.quad 0x00 16.--19. "GE,Greater than or Equal flags" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.quad 0x00 9. "E,Endianness state bit" "Little,Big" newline bitfld.quad 0x00 8. "A,Asynchronous data abort mask bit" "Not masked,Masked" bitfld.quad 0x00 7. "I,IRQ mask bit" "Not masked,Masked" bitfld.quad 0x00 6. "F,FIQ mask bit" "Not masked,Masked" bitfld.quad 0x00 5. "T,T32 Instruction set state" "A32,T32" newline bitfld.quad 0x00 4. "M[4],Execution state that the exception was taken from" "AArch64,AArch32" bitfld.quad 0x00 0.--3. "M[3:0],Current PE mode" "User,FIQ,IRQ,Supervisor,,,Monitor,Abort,,,Hyp,Undefined,,,,System" else group.quad spr:0x33450++0x00 line.quad 0x00 "DSPSR_EL0,Debug Saved Processor Status Register" bitfld.quad 0x00 31. "N,Negative condition flag" "Not negative,Negative" bitfld.quad 0x00 30. "Z,Zero condition flag" "Not zero,Zero" bitfld.quad 0x00 29. "C,Carry condition flag" "Not carry,Carry" bitfld.quad 0x00 28. "V,Overflow condition flag" "No overflow,Overflow" newline bitfld.quad 0x00 27. "Q,Cumulative condition flag" "Not occurred,Occurred" bitfld.quad 0x00 23. "UAO,User Access Override" "Standard routines,New routines" bitfld.quad 0x00 22. "PAN,Privileged Access Never" "No,Yes" bitfld.quad 0x00 21. "SS,Software step" "0,1" newline bitfld.quad 0x00 20. "IL,Illegal Execution state" "0,1" bitfld.quad 0x00 13.--15. "IT[5:7],IT block state bits for the T32 IT (If-Then) instruction - base condition for the IT block" "0,1,2,3,4,5,6,7" bitfld.quad 0x00 25.--26. 10.--12. "IT[0:4],IT block state bits for the T32 IT (If-Then) instruction - size of the IT block" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.quad 0x00 16.--19. "GE,Greater than or Equal flags" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.quad 0x00 9. "E,Endianness state bit" "Little,Big" bitfld.quad 0x00 8. "A,Asynchronous data abort mask bit" "Not masked,Masked" bitfld.quad 0x00 7. "I,IRQ mask bit" "Not masked,Masked" bitfld.quad 0x00 6. "F,FIQ mask bit" "Not masked,Masked" newline bitfld.quad 0x00 5. "T,T32 Instruction set state" "A32,T32" bitfld.quad 0x00 4. "M[4],Execution state that the exception was taken from" "AArch64,AArch32" bitfld.quad 0x00 0.--3. "M[3:0],Current PE mode" "El0t,,,,EL1t,EL1h,,,EL2t,EL2h,,EL3t,EL3h,?..." endif tree.end tree "Activity Monitors Unit" if (CORENAME()=="CORTEXA75") group.quad spr:0x33F97++0x00 line.quad 0x00 "CPUAMCNTENCLR_EL0, Activity Monitors Count Enable Clear Register" bitfld.quad 0x00 4. "P4,AMEVCNTR4 disable bit [read/write]" "Disabled/No effect,Enabled/Disable" newline bitfld.quad 0x00 3. "P3,AMEVCNTR3 disable bit [read/write]" "Disabled/No effect,Enabled/Disable" bitfld.quad 0x00 2. "P2,AMEVCNTR2 disable bit [read/write]" "Disabled/No effect,Enabled/Disable" bitfld.quad 0x00 1. "P1,AMEVCNTR1 disable bit [read/write]" "Disabled/No effect,Enabled/Disable" bitfld.quad 0x00 0. "P0,AMEVCNTR0 disable bit [read/write]" "Disabled/No effect,Enabled/Disable" group.quad spr:0x33F96++0x00 line.quad 0x00 "CPUAMCNTENSET_EL0,Activity Monitors Count Enable Set Register" bitfld.quad 0x00 4. "P4,AMEVCNTR4 enable bit" "Disabled,Enabled" newline bitfld.quad 0x00 3. "P3,AMEVCNTR3 enable bit" "Disabled,Enabled" bitfld.quad 0x00 2. "P2,AMEVCNTR2 enable bit" "Disabled,Enabled" bitfld.quad 0x00 1. "P1,AMEVCNTR1 enable bit" "Disabled,Enabled" bitfld.quad 0x00 0. "P0,AMEVCNTR0 enable bit" "Disabled,Enabled" group.quad spr:0x33FA6++0x00 line.quad 0x00 "CPUAMCFGR_EL0, Activity Monitors Configuration Register" bitfld.quad 0x00 8.--13. "SIZE,Size of counters" "1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63,64" hexmask.quad.byte 0x00 0.--7. 1. "N,Number of activity counters implemented" group.quad spr:0x33FA7++0x00 line.quad 0x00 "CPUAMUSERENR_EL0, Activity Monitor EL0 Enable access" bitfld.quad 0x00 0. "EN,Traps EL0 accesses to the activity monitor registers to EL1" "Trapped,Not trapped" group.quad spr:0x33F90++0x00 line.quad 0x00 "CPUAMEVCNTR0_EL0,Activity Monitor Event Counter Register 0" group.quad spr:(0x33F90+0x10)++0x00 line.quad 0x00 "CPUAMEVTYPER0_EL0,Activity Monitor Event Type Register 0" hexmask.quad.word 0x00 0.--9. 1. "EVTCOUNT,EVTCOUNT" group.quad spr:0x33F91++0x00 line.quad 0x00 "CPUAMEVCNTR1_EL0,Activity Monitor Event Counter Register 1" group.quad spr:(0x33F91+0x10)++0x00 line.quad 0x00 "CPUAMEVTYPER1_EL0,Activity Monitor Event Type Register 1" hexmask.quad.word 0x00 0.--9. 1. "EVTCOUNT,EVTCOUNT" group.quad spr:0x33F92++0x00 line.quad 0x00 "CPUAMEVCNTR2_EL0,Activity Monitor Event Counter Register 2" group.quad spr:(0x33F92+0x10)++0x00 line.quad 0x00 "CPUAMEVTYPER2_EL0,Activity Monitor Event Type Register 2" hexmask.quad.word 0x00 0.--9. 1. "EVTCOUNT,EVTCOUNT" group.quad spr:0x33F93++0x00 line.quad 0x00 "CPUAMEVCNTR3_EL0,Activity Monitor Event Counter Register 3" group.quad spr:(0x33F93+0x10)++0x00 line.quad 0x00 "CPUAMEVTYPER3_EL0,Activity Monitor Event Type Register 3" hexmask.quad.word 0x00 0.--9. 1. "EVTCOUNT,EVTCOUNT" group.quad spr:0x33F94++0x00 line.quad 0x00 "CPUAMEVCNTR4_EL0,Activity Monitor Event Counter Register 4" group.quad spr:(0x33F94+0x10)++0x00 line.quad 0x00 "CPUAMEVTYPER4_EL0,Activity Monitor Event Type Register 4" hexmask.quad.word 0x00 0.--9. 1. "EVTCOUNT,EVTCOUNT" endif tree.end tree "Breakpoint Registers" tree "Breakpoint 0" if ((((per.q(spr:0x20005+0x0))&0xF00000)<=0x100000)||((((per.q(spr:0x20005+0x0))&0xF00000)>=0x400000)&&(((per.q(spr:0x20005+0x0))&0xF00000)<=0x500000))) group.quad spr:(0x20004+0x0)++0x00 line.quad 0x00 "DBGBVR0_EL1,Breakpoint Value Register" hexmask.quad 0x00 2.--48. 0x4 "VA,Bits[48:2] of the address value for comparison" elif (((((per.q(spr:0x20005+0x0))&0xF00000)>=0x200000)&&(((per.q(spr:0x20005+0x0))&0xF00000)<=0x300000))||((((per.q(spr:0x20005+0x0))&0xF00000)>=0x600000)&&(((per.q(spr:0x20005+0x0))&0xF00000)<=0x700000))||((((per.q(spr:0x20005+0x0))&0xF00000)>=0xC00000))) group.quad spr:(0x20004+0x0)++0x00 line.quad 0x00 "DBGBVR0_EL1,Breakpoint Value Register" hexmask.quad.long 0x00 0.--31. 1. "CONTEXTID,Context ID value for comparison" elif ((((per.q(spr:0x20005+0x0))&0xF00000)>=0x800000)&&(((per.q(spr:0x20005+0x0))&0xF00000)<=0x900000)) group.quad spr:(0x20004+0x0)++0x00 line.quad 0x00 "DBGBVR0_EL1,Breakpoint Value Register" hexmask.quad.byte 0x00 32.--39. 1. "VMID,VMID value for comparison" elif ((((per.q(spr:0x20005+0x0))&0xF00000)>=0xA00000)&&(((per.q(spr:0x20005+0x0))&0xF00000)<=0xB00000)) group.quad spr:(0x20004+0x0)++0x00 line.quad 0x00 "DBGBVR0_EL1,Breakpoint Value Register" hexmask.quad.byte 0x00 32.--39. 1. "VMID,VMID value for comparison" hexmask.quad.long 0x00 0.--31. 1. "CONTEXTID,Context ID value for comparison" else rgroup.quad spr:(0x20004+0x0)++0x00 line.quad 0x00 "DBGBVR0_EL1,Breakpoint Value Register" in endif group.quad spr:(0x20005+0x0)++0x00 line.quad 0x00 "DBGBCR0_EL1,Breakpoint Control Register" bitfld.quad 0x00 20.--23. "BT,Breakpoint type" "Unlinked address match,Linked address match,Unlinked Context ID match,Linked Context ID match,Unlinked address mismatch,Linked address mismatch,Unlinked CONTEXTIDR_EL1 match,Linked CONTEXTIDR_EL1 match,Unlinked VMID match,Linked VMID match,Unlinked VMID + Context ID match,Linked VMID + Context ID match,Unlinked CONTEXTIDR_EL2 match,Linked CONTEXTIDR_EL2 match,Unlinked Full Context ID match,Linked Full Context ID match" bitfld.quad 0x00 16.--19. "LBN,Linked breakpoint number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.quad 0x00 14.--15. "SSC,Security state control" "Both,Non-secure,Secure,?..." newline bitfld.quad 0x00 13. "HMC,Hypervisor mode control" "Disabled,Enabled" bitfld.quad 0x0 5.--8. "BAS,Byte address select" "Reserved,Reserved,Reserved,T32/DBGBVRn_EL1,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,T32/DBGBVRn+2_EL1,Reserved,Reserved,A64/A32/DBGBVRn_EL1" bitfld.quad 0x00 1.--2. "PMC,Privileged mode control" "User/System/Supervisor,Privileged,User only,Any mode" newline bitfld.quad 0x00 0. "E,Breakpoint enable" "Disabled,Enabled" tree.end tree "Breakpoint 1" if ((((per.q(spr:0x20005+0x10))&0xF00000)<=0x100000)||((((per.q(spr:0x20005+0x10))&0xF00000)>=0x400000)&&(((per.q(spr:0x20005+0x10))&0xF00000)<=0x500000))) group.quad spr:(0x20004+0x10)++0x00 line.quad 0x00 "DBGBVR1_EL1,Breakpoint Value Register" hexmask.quad 0x00 2.--48. 0x4 "VA,Bits[48:2] of the address value for comparison" elif (((((per.q(spr:0x20005+0x10))&0xF00000)>=0x200000)&&(((per.q(spr:0x20005+0x10))&0xF00000)<=0x300000))||((((per.q(spr:0x20005+0x10))&0xF00000)>=0x600000)&&(((per.q(spr:0x20005+0x10))&0xF00000)<=0x700000))||((((per.q(spr:0x20005+0x10))&0xF00000)>=0xC00000))) group.quad spr:(0x20004+0x10)++0x00 line.quad 0x00 "DBGBVR1_EL1,Breakpoint Value Register" hexmask.quad.long 0x00 0.--31. 1. "CONTEXTID,Context ID value for comparison" elif ((((per.q(spr:0x20005+0x10))&0xF00000)>=0x800000)&&(((per.q(spr:0x20005+0x10))&0xF00000)<=0x900000)) group.quad spr:(0x20004+0x10)++0x00 line.quad 0x00 "DBGBVR1_EL1,Breakpoint Value Register" hexmask.quad.byte 0x00 32.--39. 1. "VMID,VMID value for comparison" elif ((((per.q(spr:0x20005+0x10))&0xF00000)>=0xA00000)&&(((per.q(spr:0x20005+0x10))&0xF00000)<=0xB00000)) group.quad spr:(0x20004+0x10)++0x00 line.quad 0x00 "DBGBVR1_EL1,Breakpoint Value Register" hexmask.quad.byte 0x00 32.--39. 1. "VMID,VMID value for comparison" hexmask.quad.long 0x00 0.--31. 1. "CONTEXTID,Context ID value for comparison" else rgroup.quad spr:(0x20004+0x10)++0x00 line.quad 0x00 "DBGBVR1_EL1,Breakpoint Value Register" in endif group.quad spr:(0x20005+0x10)++0x00 line.quad 0x00 "DBGBCR1_EL1,Breakpoint Control Register" bitfld.quad 0x00 20.--23. "BT,Breakpoint type" "Unlinked address match,Linked address match,Unlinked Context ID match,Linked Context ID match,Unlinked address mismatch,Linked address mismatch,Unlinked CONTEXTIDR_EL1 match,Linked CONTEXTIDR_EL1 match,Unlinked VMID match,Linked VMID match,Unlinked VMID + Context ID match,Linked VMID + Context ID match,Unlinked CONTEXTIDR_EL2 match,Linked CONTEXTIDR_EL2 match,Unlinked Full Context ID match,Linked Full Context ID match" bitfld.quad 0x00 16.--19. "LBN,Linked breakpoint number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.quad 0x00 14.--15. "SSC,Security state control" "Both,Non-secure,Secure,?..." newline bitfld.quad 0x00 13. "HMC,Hypervisor mode control" "Disabled,Enabled" bitfld.quad 0x0 5.--8. "BAS,Byte address select" "Reserved,Reserved,Reserved,T32/DBGBVRn_EL1,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,T32/DBGBVRn+2_EL1,Reserved,Reserved,A64/A32/DBGBVRn_EL1" bitfld.quad 0x00 1.--2. "PMC,Privileged mode control" "User/System/Supervisor,Privileged,User only,Any mode" newline bitfld.quad 0x00 0. "E,Breakpoint enable" "Disabled,Enabled" tree.end tree "Breakpoint 2" if ((((per.q(spr:0x20005+0x20))&0xF00000)<=0x100000)||((((per.q(spr:0x20005+0x20))&0xF00000)>=0x400000)&&(((per.q(spr:0x20005+0x20))&0xF00000)<=0x500000))) group.quad spr:(0x20004+0x20)++0x00 line.quad 0x00 "DBGBVR2_EL1,Breakpoint Value Register" hexmask.quad 0x00 2.--48. 0x4 "VA,Bits[48:2] of the address value for comparison" elif (((((per.q(spr:0x20005+0x20))&0xF00000)>=0x200000)&&(((per.q(spr:0x20005+0x20))&0xF00000)<=0x300000))||((((per.q(spr:0x20005+0x20))&0xF00000)>=0x600000)&&(((per.q(spr:0x20005+0x20))&0xF00000)<=0x700000))||((((per.q(spr:0x20005+0x20))&0xF00000)>=0xC00000))) group.quad spr:(0x20004+0x20)++0x00 line.quad 0x00 "DBGBVR2_EL1,Breakpoint Value Register" hexmask.quad.long 0x00 0.--31. 1. "CONTEXTID,Context ID value for comparison" elif ((((per.q(spr:0x20005+0x20))&0xF00000)>=0x800000)&&(((per.q(spr:0x20005+0x20))&0xF00000)<=0x900000)) group.quad spr:(0x20004+0x20)++0x00 line.quad 0x00 "DBGBVR2_EL1,Breakpoint Value Register" hexmask.quad.byte 0x00 32.--39. 1. "VMID,VMID value for comparison" elif ((((per.q(spr:0x20005+0x20))&0xF00000)>=0xA00000)&&(((per.q(spr:0x20005+0x20))&0xF00000)<=0xB00000)) group.quad spr:(0x20004+0x20)++0x00 line.quad 0x00 "DBGBVR2_EL1,Breakpoint Value Register" hexmask.quad.byte 0x00 32.--39. 1. "VMID,VMID value for comparison" hexmask.quad.long 0x00 0.--31. 1. "CONTEXTID,Context ID value for comparison" else rgroup.quad spr:(0x20004+0x20)++0x00 line.quad 0x00 "DBGBVR2_EL1,Breakpoint Value Register" in endif group.quad spr:(0x20005+0x20)++0x00 line.quad 0x00 "DBGBCR2_EL1,Breakpoint Control Register" bitfld.quad 0x00 20.--23. "BT,Breakpoint type" "Unlinked address match,Linked address match,Unlinked Context ID match,Linked Context ID match,Unlinked address mismatch,Linked address mismatch,Unlinked CONTEXTIDR_EL1 match,Linked CONTEXTIDR_EL1 match,Unlinked VMID match,Linked VMID match,Unlinked VMID + Context ID match,Linked VMID + Context ID match,Unlinked CONTEXTIDR_EL2 match,Linked CONTEXTIDR_EL2 match,Unlinked Full Context ID match,Linked Full Context ID match" bitfld.quad 0x00 16.--19. "LBN,Linked breakpoint number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.quad 0x00 14.--15. "SSC,Security state control" "Both,Non-secure,Secure,?..." newline bitfld.quad 0x00 13. "HMC,Hypervisor mode control" "Disabled,Enabled" bitfld.quad 0x0 5.--8. "BAS,Byte address select" "Reserved,Reserved,Reserved,T32/DBGBVRn_EL1,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,T32/DBGBVRn+2_EL1,Reserved,Reserved,A64/A32/DBGBVRn_EL1" bitfld.quad 0x00 1.--2. "PMC,Privileged mode control" "User/System/Supervisor,Privileged,User only,Any mode" newline bitfld.quad 0x00 0. "E,Breakpoint enable" "Disabled,Enabled" tree.end tree "Breakpoint 3" if ((((per.q(spr:0x20005+0x30))&0xF00000)<=0x100000)||((((per.q(spr:0x20005+0x30))&0xF00000)>=0x400000)&&(((per.q(spr:0x20005+0x30))&0xF00000)<=0x500000))) group.quad spr:(0x20004+0x30)++0x00 line.quad 0x00 "DBGBVR3_EL1,Breakpoint Value Register" hexmask.quad 0x00 2.--48. 0x4 "VA,Bits[48:2] of the address value for comparison" elif (((((per.q(spr:0x20005+0x30))&0xF00000)>=0x200000)&&(((per.q(spr:0x20005+0x30))&0xF00000)<=0x300000))||((((per.q(spr:0x20005+0x30))&0xF00000)>=0x600000)&&(((per.q(spr:0x20005+0x30))&0xF00000)<=0x700000))||((((per.q(spr:0x20005+0x30))&0xF00000)>=0xC00000))) group.quad spr:(0x20004+0x30)++0x00 line.quad 0x00 "DBGBVR3_EL1,Breakpoint Value Register" hexmask.quad.long 0x00 0.--31. 1. "CONTEXTID,Context ID value for comparison" elif ((((per.q(spr:0x20005+0x30))&0xF00000)>=0x800000)&&(((per.q(spr:0x20005+0x30))&0xF00000)<=0x900000)) group.quad spr:(0x20004+0x30)++0x00 line.quad 0x00 "DBGBVR3_EL1,Breakpoint Value Register" hexmask.quad.byte 0x00 32.--39. 1. "VMID,VMID value for comparison" elif ((((per.q(spr:0x20005+0x30))&0xF00000)>=0xA00000)&&(((per.q(spr:0x20005+0x30))&0xF00000)<=0xB00000)) group.quad spr:(0x20004+0x30)++0x00 line.quad 0x00 "DBGBVR3_EL1,Breakpoint Value Register" hexmask.quad.byte 0x00 32.--39. 1. "VMID,VMID value for comparison" hexmask.quad.long 0x00 0.--31. 1. "CONTEXTID,Context ID value for comparison" else rgroup.quad spr:(0x20004+0x30)++0x00 line.quad 0x00 "DBGBVR3_EL1,Breakpoint Value Register" in endif group.quad spr:(0x20005+0x30)++0x00 line.quad 0x00 "DBGBCR3_EL1,Breakpoint Control Register" bitfld.quad 0x00 20.--23. "BT,Breakpoint type" "Unlinked address match,Linked address match,Unlinked Context ID match,Linked Context ID match,Unlinked address mismatch,Linked address mismatch,Unlinked CONTEXTIDR_EL1 match,Linked CONTEXTIDR_EL1 match,Unlinked VMID match,Linked VMID match,Unlinked VMID + Context ID match,Linked VMID + Context ID match,Unlinked CONTEXTIDR_EL2 match,Linked CONTEXTIDR_EL2 match,Unlinked Full Context ID match,Linked Full Context ID match" bitfld.quad 0x00 16.--19. "LBN,Linked breakpoint number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.quad 0x00 14.--15. "SSC,Security state control" "Both,Non-secure,Secure,?..." newline bitfld.quad 0x00 13. "HMC,Hypervisor mode control" "Disabled,Enabled" bitfld.quad 0x0 5.--8. "BAS,Byte address select" "Reserved,Reserved,Reserved,T32/DBGBVRn_EL1,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,T32/DBGBVRn+2_EL1,Reserved,Reserved,A64/A32/DBGBVRn_EL1" bitfld.quad 0x00 1.--2. "PMC,Privileged mode control" "User/System/Supervisor,Privileged,User only,Any mode" newline bitfld.quad 0x00 0. "E,Breakpoint enable" "Disabled,Enabled" tree.end tree "Breakpoint 4" if ((((per.q(spr:0x20005+0x40))&0xF00000)<=0x100000)||((((per.q(spr:0x20005+0x40))&0xF00000)>=0x400000)&&(((per.q(spr:0x20005+0x40))&0xF00000)<=0x500000))) group.quad spr:(0x20004+0x40)++0x00 line.quad 0x00 "DBGBVR4_EL1,Breakpoint Value Register" hexmask.quad 0x00 2.--48. 0x4 "VA,Bits[48:2] of the address value for comparison" elif (((((per.q(spr:0x20005+0x40))&0xF00000)>=0x200000)&&(((per.q(spr:0x20005+0x40))&0xF00000)<=0x300000))||((((per.q(spr:0x20005+0x40))&0xF00000)>=0x600000)&&(((per.q(spr:0x20005+0x40))&0xF00000)<=0x700000))||((((per.q(spr:0x20005+0x40))&0xF00000)>=0xC00000))) group.quad spr:(0x20004+0x40)++0x00 line.quad 0x00 "DBGBVR4_EL1,Breakpoint Value Register" hexmask.quad.long 0x00 0.--31. 1. "CONTEXTID,Context ID value for comparison" elif ((((per.q(spr:0x20005+0x40))&0xF00000)>=0x800000)&&(((per.q(spr:0x20005+0x40))&0xF00000)<=0x900000)) group.quad spr:(0x20004+0x40)++0x00 line.quad 0x00 "DBGBVR4_EL1,Breakpoint Value Register" hexmask.quad.byte 0x00 32.--39. 1. "VMID,VMID value for comparison" elif ((((per.q(spr:0x20005+0x40))&0xF00000)>=0xA00000)&&(((per.q(spr:0x20005+0x40))&0xF00000)<=0xB00000)) group.quad spr:(0x20004+0x40)++0x00 line.quad 0x00 "DBGBVR4_EL1,Breakpoint Value Register" hexmask.quad.byte 0x00 32.--39. 1. "VMID,VMID value for comparison" hexmask.quad.long 0x00 0.--31. 1. "CONTEXTID,Context ID value for comparison" else rgroup.quad spr:(0x20004+0x40)++0x00 line.quad 0x00 "DBGBVR4_EL1,Breakpoint Value Register" in endif group.quad spr:(0x20005+0x40)++0x00 line.quad 0x00 "DBGBCR4_EL1,Breakpoint Control Register" bitfld.quad 0x00 20.--23. "BT,Breakpoint type" "Unlinked address match,Linked address match,Unlinked Context ID match,Linked Context ID match,Unlinked address mismatch,Linked address mismatch,Unlinked CONTEXTIDR_EL1 match,Linked CONTEXTIDR_EL1 match,Unlinked VMID match,Linked VMID match,Unlinked VMID + Context ID match,Linked VMID + Context ID match,Unlinked CONTEXTIDR_EL2 match,Linked CONTEXTIDR_EL2 match,Unlinked Full Context ID match,Linked Full Context ID match" bitfld.quad 0x00 16.--19. "LBN,Linked breakpoint number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.quad 0x00 14.--15. "SSC,Security state control" "Both,Non-secure,Secure,?..." newline bitfld.quad 0x00 13. "HMC,Hypervisor mode control" "Disabled,Enabled" bitfld.quad 0x0 5.--8. "BAS,Byte address select" "Reserved,Reserved,Reserved,T32/DBGBVRn_EL1,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,T32/DBGBVRn+2_EL1,Reserved,Reserved,A64/A32/DBGBVRn_EL1" bitfld.quad 0x00 1.--2. "PMC,Privileged mode control" "User/System/Supervisor,Privileged,User only,Any mode" newline bitfld.quad 0x00 0. "E,Breakpoint enable" "Disabled,Enabled" tree.end tree "Breakpoint 5" if ((((per.q(spr:0x20005+0x50))&0xF00000)<=0x100000)||((((per.q(spr:0x20005+0x50))&0xF00000)>=0x400000)&&(((per.q(spr:0x20005+0x50))&0xF00000)<=0x500000))) group.quad spr:(0x20004+0x50)++0x00 line.quad 0x00 "DBGBVR5_EL1,Breakpoint Value Register" hexmask.quad 0x00 2.--48. 0x4 "VA,Bits[48:2] of the address value for comparison" elif (((((per.q(spr:0x20005+0x50))&0xF00000)>=0x200000)&&(((per.q(spr:0x20005+0x50))&0xF00000)<=0x300000))||((((per.q(spr:0x20005+0x50))&0xF00000)>=0x600000)&&(((per.q(spr:0x20005+0x50))&0xF00000)<=0x700000))||((((per.q(spr:0x20005+0x50))&0xF00000)>=0xC00000))) group.quad spr:(0x20004+0x50)++0x00 line.quad 0x00 "DBGBVR5_EL1,Breakpoint Value Register" hexmask.quad.long 0x00 0.--31. 1. "CONTEXTID,Context ID value for comparison" elif ((((per.q(spr:0x20005+0x50))&0xF00000)>=0x800000)&&(((per.q(spr:0x20005+0x50))&0xF00000)<=0x900000)) group.quad spr:(0x20004+0x50)++0x00 line.quad 0x00 "DBGBVR5_EL1,Breakpoint Value Register" hexmask.quad.byte 0x00 32.--39. 1. "VMID,VMID value for comparison" elif ((((per.q(spr:0x20005+0x50))&0xF00000)>=0xA00000)&&(((per.q(spr:0x20005+0x50))&0xF00000)<=0xB00000)) group.quad spr:(0x20004+0x50)++0x00 line.quad 0x00 "DBGBVR5_EL1,Breakpoint Value Register" hexmask.quad.byte 0x00 32.--39. 1. "VMID,VMID value for comparison" hexmask.quad.long 0x00 0.--31. 1. "CONTEXTID,Context ID value for comparison" else rgroup.quad spr:(0x20004+0x50)++0x00 line.quad 0x00 "DBGBVR5_EL1,Breakpoint Value Register" in endif group.quad spr:(0x20005+0x50)++0x00 line.quad 0x00 "DBGBCR5_EL1,Breakpoint Control Register" bitfld.quad 0x00 20.--23. "BT,Breakpoint type" "Unlinked address match,Linked address match,Unlinked Context ID match,Linked Context ID match,Unlinked address mismatch,Linked address mismatch,Unlinked CONTEXTIDR_EL1 match,Linked CONTEXTIDR_EL1 match,Unlinked VMID match,Linked VMID match,Unlinked VMID + Context ID match,Linked VMID + Context ID match,Unlinked CONTEXTIDR_EL2 match,Linked CONTEXTIDR_EL2 match,Unlinked Full Context ID match,Linked Full Context ID match" bitfld.quad 0x00 16.--19. "LBN,Linked breakpoint number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.quad 0x00 14.--15. "SSC,Security state control" "Both,Non-secure,Secure,?..." newline bitfld.quad 0x00 13. "HMC,Hypervisor mode control" "Disabled,Enabled" bitfld.quad 0x0 5.--8. "BAS,Byte address select" "Reserved,Reserved,Reserved,T32/DBGBVRn_EL1,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,T32/DBGBVRn+2_EL1,Reserved,Reserved,A64/A32/DBGBVRn_EL1" bitfld.quad 0x00 1.--2. "PMC,Privileged mode control" "User/System/Supervisor,Privileged,User only,Any mode" newline bitfld.quad 0x00 0. "E,Breakpoint enable" "Disabled,Enabled" tree.end tree.end tree "Watchpoint Registers" tree "Watchpoint 0" group.quad spr:(0x20006+0x0)++0x00 line.quad 0x00 "DBGWVR0_EL1,Watchpoint Value Register (AArch64)" hexmask.quad 0x00 2.--48. 0x4 "ADDRESS,Data address" group.quad spr:(0x20007+0x0)++0x00 line.quad 0x00 "DBGWCR0_EL1,Watchpoint Control Register" bitfld.quad 0x00 24.--28. "MASK,Address mask" "No mask,Reserved,Reserved,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.quad 0x00 20. "WT,Watchpoint type" "Unlinked,Linked" bitfld.quad 0x00 16.--19. "LBN,Linked breakpoint number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.quad 0x00 14.--15. "SSC,Security state control" "Both,Non-secure,Secure,?..." bitfld.quad 0x00 13. "HMC,Hypervisor mode control" "Disabled,Enabled" hexmask.quad.byte 0x00 5.--12. 1. "BAS,Byte address select" newline bitfld.quad 0x00 3.--4. "LSC,Load/store control" "Reserved,Load,Store,Both" bitfld.quad 0x00 1.--2. "PAC,Privileged mode control" "User/System/Supervisor,Privileged,User only,Any mode" bitfld.quad 0x00 0. "E,Enable" "Disabled,Enabled" tree.end tree "Watchpoint 1" group.quad spr:(0x20006+0x10)++0x00 line.quad 0x00 "DBGWVR1_EL1,Watchpoint Value Register (AArch64)" hexmask.quad 0x00 2.--48. 0x4 "ADDRESS,Data address" group.quad spr:(0x20007+0x10)++0x00 line.quad 0x00 "DBGWCR1_EL1,Watchpoint Control Register" bitfld.quad 0x00 24.--28. "MASK,Address mask" "No mask,Reserved,Reserved,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.quad 0x00 20. "WT,Watchpoint type" "Unlinked,Linked" bitfld.quad 0x00 16.--19. "LBN,Linked breakpoint number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.quad 0x00 14.--15. "SSC,Security state control" "Both,Non-secure,Secure,?..." bitfld.quad 0x00 13. "HMC,Hypervisor mode control" "Disabled,Enabled" hexmask.quad.byte 0x00 5.--12. 1. "BAS,Byte address select" newline bitfld.quad 0x00 3.--4. "LSC,Load/store control" "Reserved,Load,Store,Both" bitfld.quad 0x00 1.--2. "PAC,Privileged mode control" "User/System/Supervisor,Privileged,User only,Any mode" bitfld.quad 0x00 0. "E,Enable" "Disabled,Enabled" tree.end tree "Watchpoint 2" group.quad spr:(0x20006+0x20)++0x00 line.quad 0x00 "DBGWVR2_EL1,Watchpoint Value Register (AArch64)" hexmask.quad 0x00 2.--48. 0x4 "ADDRESS,Data address" group.quad spr:(0x20007+0x20)++0x00 line.quad 0x00 "DBGWCR2_EL1,Watchpoint Control Register" bitfld.quad 0x00 24.--28. "MASK,Address mask" "No mask,Reserved,Reserved,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.quad 0x00 20. "WT,Watchpoint type" "Unlinked,Linked" bitfld.quad 0x00 16.--19. "LBN,Linked breakpoint number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.quad 0x00 14.--15. "SSC,Security state control" "Both,Non-secure,Secure,?..." bitfld.quad 0x00 13. "HMC,Hypervisor mode control" "Disabled,Enabled" hexmask.quad.byte 0x00 5.--12. 1. "BAS,Byte address select" newline bitfld.quad 0x00 3.--4. "LSC,Load/store control" "Reserved,Load,Store,Both" bitfld.quad 0x00 1.--2. "PAC,Privileged mode control" "User/System/Supervisor,Privileged,User only,Any mode" bitfld.quad 0x00 0. "E,Enable" "Disabled,Enabled" tree.end tree "Watchpoint 3" group.quad spr:(0x20006+0x30)++0x00 line.quad 0x00 "DBGWVR3_EL1,Watchpoint Value Register (AArch64)" hexmask.quad 0x00 2.--48. 0x4 "ADDRESS,Data address" group.quad spr:(0x20007+0x30)++0x00 line.quad 0x00 "DBGWCR3_EL1,Watchpoint Control Register" bitfld.quad 0x00 24.--28. "MASK,Address mask" "No mask,Reserved,Reserved,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.quad 0x00 20. "WT,Watchpoint type" "Unlinked,Linked" bitfld.quad 0x00 16.--19. "LBN,Linked breakpoint number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.quad 0x00 14.--15. "SSC,Security state control" "Both,Non-secure,Secure,?..." bitfld.quad 0x00 13. "HMC,Hypervisor mode control" "Disabled,Enabled" hexmask.quad.byte 0x00 5.--12. 1. "BAS,Byte address select" newline bitfld.quad 0x00 3.--4. "LSC,Load/store control" "Reserved,Load,Store,Both" bitfld.quad 0x00 1.--2. "PAC,Privileged mode control" "User/System/Supervisor,Privileged,User only,Any mode" bitfld.quad 0x00 0. "E,Enable" "Disabled,Enabled" tree.end tree.end tree "LORegions Registers" group.quad spr:0x30A40++0x00 line.quad 0x00 "LORSA_EL1,LORegion Start Address" hexmask.quad.long 0x00 16.--47. 0x1 "SA,Start physical address bits[47:16]" bitfld.quad 0x00 0. "VALID,Indicates whether the LORegion Descriptor is enabled" "Not valid,Valid" group.quad spr:0x30A41++0x00 line.quad 0x00 "LOREA_EL1,LORegion End Address" hexmask.quad.long 0x00 16.--47. 0x1 "EA,End physical address bits[47:16]" group.quad spr:0x30A42++0x00 line.quad 0x00 "LORN_EL1,LORegion Number Register" bitfld.quad 0x00 0.--1. "NUM,Indicates the LORegion number" "0,1,2,3" group.quad spr:0x30A43++0x00 line.quad 0x00 "LORC_EL1,LORegion Control Register" bitfld.quad 0x00 2.--3. "DS,Descriptor Select" "0,1,2,3" bitfld.quad 0x00 0. "EN,Enable" "Disabled,Enabled" rgroup.quad spr:0x30A47++0x00 line.quad 0x00 "LORID_EL1,Limited Order Region Identification Register" hexmask.quad.byte 0x00 16.--23. 1. "LD,Number of LOR Descriptors supported by the implementation" hexmask.quad.byte 0x00 0.--7. 1. "LR,Number of LORegions supported by the implementation" tree.end tree "DynamIQ Shared Unit" tree "Cluster Control Registers" if (((per.q(spr:0x30F30))&0x2000)==0x00) rgroup.quad spr:0x30F30++0x00 line.long 0x00 "CLUSTERCFR_EL1,Cluster Configuration Register" bitfld.long 0x00 24.--27. "NPE,Number of processing elements" "1,2,?..." bitfld.long 0x00 23. "L3_DATA_RAM_DELAY,L3 data RAM write delay" "Not delayed,Delayed" newline bitfld.long 0x00 17. "CRSP3,Core 3 register slice present" "Not present,Present" bitfld.long 0x00 16. "CRSP2,Core 2 register slice present" "Not present,Present" newline bitfld.long 0x00 15. "CRSP1,Core 1 register slice present" "Not present,Present" bitfld.long 0x00 14. "CRSP0,Core 0 register slice present" "Not present,Present" bitfld.long 0x00 13. "BUS_INTERFACE_EXT,Bus interface extended" "Not extended,Extended" newline bitfld.long 0x00 12. "PPP,Peripheral port present" "Not present,Present" bitfld.long 0x00 11. "ACP,ACP interface present" "Not present,Present" bitfld.long 0x00 9.--10. "BUS_INTERFACE,Bus interface configuration" "Single 128-bit ACE,Dual 128-bit ACE,Single 128-bit CHI,Single 256-bit CHI" newline bitfld.long 0x00 8. "SCU_L3_ECC,SCU-L3 is configured with ECC" "No ECC,ECC" bitfld.long 0x00 7. "L3_DATA_RAM_RS,L3 data RAM register slice present" "Not present,Present" bitfld.long 0x00 6. "L3_DATA_RAM_RL,L3 data RAM read latency" "2 cycles,3 cycles" newline bitfld.long 0x00 5. "L3_DATA_RAM_WL,L3 data RAM write latency" "1 cycle,2 cycles" bitfld.long 0x00 4. "L3_CACHE_PRESENT,L3 cache present" "Not present,Present" bitfld.long 0x00 0.--2. "NOC,Number of cores present in the cluster" "1,2,3,4,?..." else rgroup.quad spr:0x30F30++0x00 line.long 0x00 "CLUSTERCFR_EL1,Cluster Configuration Register" bitfld.long 0x00 24.--27. "NPE,Number of processing elements" "1,2,?..." bitfld.long 0x00 23. "L3_DATA_RAM_DELAY,L3 data RAM write delay" "Not delayed,Delayed" newline bitfld.long 0x00 17. "CRSP3,Core 3 register slice present" "Not present,Present" bitfld.long 0x00 16. "CRSP2,Core 2 register slice present" "Not present,Present" newline bitfld.long 0x00 15. "CRSP1,Core 1 register slice present" "Not present,Present" bitfld.long 0x00 14. "CRSP0,Core 0 register slice present" "Not present,Present" bitfld.long 0x00 13. "BUS_INTERFACE_EXT,Bus interface extended" "Not extended,Extended" newline bitfld.long 0x00 12. "PPP,Peripheral port present" "Not present,Present" bitfld.long 0x00 11. "ACP,ACP interface present" "Not present,Present" bitfld.long 0x00 9.--10. "BUS_INTERFACE,Bus interface configuration" "Single 128-bit ACE,Dual 128-bit ACE,Single 128-bit CHI,Dual 256-bit CHI" newline bitfld.long 0x00 8. "SCU_L3_ECC,SCU-L3 is configured with ECC" "No ECC,ECC" bitfld.long 0x00 7. "L3_DATA_RAM_RS,L3 data RAM register slice present" "Not present,Present" bitfld.long 0x00 6. "L3_DATA_RAM_RL,L3 data RAM read latency" "2 cycles,3 cycles" newline bitfld.long 0x00 5. "L3_DATA_RAM_WL,L3 data RAM write latency" "1 cycle,2 cycles" bitfld.long 0x00 4. "L3_CACHE_PRESENT,L3 cache present" "Not present,Present" bitfld.long 0x00 0.--2. "NOC,Number of cores present in the cluster" "1,2,3,4,?..." endif rgroup.quad spr:0x30F31++0x00 line.long 0x00 "CLUSTERIDR_EL1,Cluster Main Revision ID" hexmask.long.byte 0x00 4.--7. 1. "VARIANT,Indicates the variant of the FCM" hexmask.long.byte 0x00 0.--3. 1. "REVISION,Indicates the minor revision number of the FCM" rgroup.quad spr:0x30F32++0x00 line.long 0x00 "CLUSTERREVIDR_EL1,Cluster ECO ID" group.quad spr:0x30F33++0x00 line.long 0x00 "CLUSTERACTLR_EL1,Cluster Auxiliary Control Register" if (((per.l(spr:0x30F30))&0x600)==(0x00||0x200)) group.quad spr:0x30F34++0x00 line.long 0x00 "CLUSTERECTLR_EL1,Cluster Extended Control Register" bitfld.long 0x00 14. "CUEC,Cache UniqueClean eviction control" "Disabled,Enabled" bitfld.long 0x00 8.--10. "PMD,Prefetch matching delay" "1,2,4,8,16,32,64,128" bitfld.long 0x00 7. "DICA,Disable interconnect cacheable atomics" "No,Yes" newline bitfld.long 0x00 4. "IDPS,Interconnect data poisoning support" "Not supported,Supported" bitfld.long 0x00 3. "CTEC,Disables send evict transactions on the ACE/CHI master" "No,Yes" bitfld.long 0x00 2. "CFUCEC,Disables WriteEvict requests on the ACE/CHI master (Powering down part/All L3 cache)" "No,Yes" newline bitfld.long 0x00 0. "DNCWL,Disable the limit on the number of non-cacheable writes that are allowed on the ACE interface" "No,Yes" else group.quad spr:0x30F34++0x00 line.long 0x00 "CLUSTERECTLR_EL1,Cluster Extended Control Register" bitfld.long 0x00 14. "CUEC,Cache UniqueClean eviction control" "Disabled,Enabled" bitfld.long 0x00 8.--10. "PMD,Prefetch matching delay" "1,2,4,8,16,32,64,128" bitfld.long 0x00 7. "DICA,Disable interconnect cacheable atomics" "No,Yes" newline bitfld.long 0x00 4. "IDPS,Interconnect data poisoning support" "Not supported,Supported" bitfld.long 0x00 3. "CTEC,Disables send evict transactions on the ACE/CHI master" "No,Yes" bitfld.long 0x00 2. "CFUCEC,Disables WriteEvict requests on the ACE/CHI master (Powering down part/All L3 cache)" "No,Yes" endif group.quad spr:0x30F35++0x00 line.long 0x00 "CLUSTERPWRCTLR_EL1,Cluster Power Control Register" bitfld.long 0x00 4.--7. "CPPR,Cache portion power request" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--2. "L3_DATA_RAM_RC,L3 data RAM retention control [Number of Architectural Timer ticks required before retention entry]" "Disabled,2 AT ticks,8 AT ticks,32 AT ticks,64 AT ticks,128 AT ticks,256 AT ticks,512 AT ticks" group.quad spr:0x30F36++0x00 line.long 0x00 "CLUSTERPWRDN_EL1,Cluster Power Down Register" bitfld.long 0x00 1. "MRR,Memory retention required" "Not required,Required" bitfld.long 0x00 0. "CPR,Cluster power required" "Not required,Required" rgroup.quad spr:0x30F37++0x00 line.long 0x00 "CLUSTERPWRSTAT_EL1,Cluster Power Status Register" bitfld.long 0x00 4.--7. "CPPS,This bits indicates which cache portions are currently powered up and available" "No ways,Ways 0-3,Reserved,Ways 0-7,Reserved,Reserved,Reserved,Ways 0-11,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Ways 0-15" bitfld.long 0x00 1. "RWPD,Enabled memory retention when all cores are powered down" "Disabled,Enabled" bitfld.long 0x00 0. "DCPD,Disabled cluster power down when all cores are powered down" "No,Yes" group.quad spr:0x30F40++0x00 line.long 0x00 "CLUSTERTHREADSID_EL1,Cluster Thread Scheme ID Register" bitfld.long 0x00 0.--2. "SCHEME_ID_THREAD,Scheme ID for current thread" "0,1,2,3,4,5,6,7" group.quad spr:0x30F41++0x00 line.long 0x00 "CLUSTERACPSID_EL1,Cluster ACP Scheme ID Register" bitfld.long 0x00 0.--2. "SCHEME_ID_ACP,Scheme ID for ACP transactions" "0,1,2,3,4,5,6,7" group.quad spr:0x30F42++0x00 line.long 0x00 "CLUSTERSTASHSID_EL1,Cluster Stash Scheme ID Register" bitfld.long 0x00 0.--2. "SCHEME_ID_SR,Scheme ID for stash requests received from the interconnect" "0,1,2,3,4,5,6,7" group.quad spr:0x30F43++0x00 line.long 0x00 "CLUSTERPARTCR_EL1,Cluster Partition Control Register" bitfld.long 0x00 31. "W3_ID7,Way group 3 is assigned as private to scheme ID 7" "Not assigned,Assigned" bitfld.long 0x00 30. "W2_ID7,Way group 2 is assigned as private to scheme ID 7" "Not assigned,Assigned" bitfld.long 0x00 29. "W1_ID7,Way group 1 is assigned as private to scheme ID 7" "Not assigned,Assigned" newline bitfld.long 0x00 28. "W0_ID7,Way group 0 is assigned as private to scheme ID 7" "Not assigned,Assigned" bitfld.long 0x00 27. "W3_ID6,Way group 3 is assigned as private to scheme ID 6" "Not assigned,Assigned" bitfld.long 0x00 26. "W2_ID6,Way group 2 is assigned as private to scheme ID 6" "Not assigned,Assigned" newline bitfld.long 0x00 25. "W1_ID6,Way group 1 is assigned as private to scheme ID 6" "Not assigned,Assigned" bitfld.long 0x00 24. "W0_ID6,Way group 0 is assigned as private to scheme ID 6" "Not assigned,Assigned" bitfld.long 0x00 23. "W3_ID5,Way group 3 is assigned as private to scheme ID 5" "Not assigned,Assigned" newline bitfld.long 0x00 22. "W2_ID5,Way group 2 is assigned as private to scheme ID 5" "Not assigned,Assigned" bitfld.long 0x00 21. "W1_ID5,Way group 1 is assigned as private to scheme ID 5" "Not assigned,Assigned" bitfld.long 0x00 20. "W0_ID5,Way group 0 is assigned as private to scheme ID 5" "Not assigned,Assigned" newline bitfld.long 0x00 19. "W3_ID4,Way group 3 is assigned as private to scheme ID 4" "Not assigned,Assigned" bitfld.long 0x00 18. "W2_ID4,Way group 2 is assigned as private to scheme ID 4" "Not assigned,Assigned" bitfld.long 0x00 17. "W1_ID4,Way group 1 is assigned as private to scheme ID 4" "Not assigned,Assigned" newline bitfld.long 0x00 16. "W0_ID4,Way group 0 is assigned as private to scheme ID 4" "Not assigned,Assigned" bitfld.long 0x00 15. "W3_ID3,Way group 3 is assigned as private to scheme ID 3" "Not assigned,Assigned" bitfld.long 0x00 14. "W2_ID3,Way group 2 is assigned as private to scheme ID 3" "Not assigned,Assigned" newline bitfld.long 0x00 13. "W1_ID3,Way group 1 is assigned as private to scheme ID 3" "Not assigned,Assigned" bitfld.long 0x00 12. "W0_ID3,Way group 0 is assigned as private to scheme ID 3" "Not assigned,Assigned" bitfld.long 0x00 11. "W3_ID2,Way group 3 is assigned as private to scheme ID 2" "Not assigned,Assigned" newline bitfld.long 0x00 10. "W2_ID2,Way group 2 is assigned as private to scheme ID 2" "Not assigned,Assigned" bitfld.long 0x00 9. "W1_ID2,Way group 1 is assigned as private to scheme ID 2" "Not assigned,Assigned" bitfld.long 0x00 8. "W0_ID2,Way group 0 is assigned as private to scheme ID 2" "Not assigned,Assigned" newline bitfld.long 0x00 7. "W3_ID1,Way group 3 is assigned as private to scheme ID 1" "Not assigned,Assigned" bitfld.long 0x00 6. "W2_ID1,Way group 2 is assigned as private to scheme ID 1" "Not assigned,Assigned" bitfld.long 0x00 5. "W1_ID1,Way group 1 is assigned as private to scheme ID 1" "Not assigned,Assigned" newline bitfld.long 0x00 4. "W0_ID1,Way group 0 is assigned as private to scheme ID 1" "Not assigned,Assigned" bitfld.long 0x00 3. "W3_ID0,Way group 3 is assigned as private to scheme ID 0" "Not assigned,Assigned" bitfld.long 0x00 2. "W2_ID0,Way group 2 is assigned as private to scheme ID 0" "Not assigned,Assigned" newline bitfld.long 0x00 1. "W1_ID0,Way group 1 is assigned as private to scheme ID 0" "Not assigned,Assigned" bitfld.long 0x00 0. "W0_ID0,Way group 0 is assigned as private to scheme ID 0" "Not assigned,Assigned" group.quad spr:0x30F44++0x00 line.long 0x00 "CLUSTERBUSQOS_EL1,Cluster Bus QoS Control Register" bitfld.long 0x00 28.--31. "CHI_BUS_QOS_SCHEME_ID7,Value driven on the CHI bus QoS field for scheme ID 7" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 24.--27. "CHI_BUS_QOS_SCHEME_ID6,Value driven on the CHI bus QoS field for scheme ID 6" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 20.--23. "CHI_BUS_QOS_SCHEME_ID5,Value driven on the CHI bus QoS field for scheme ID 5" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 16.--19. "CHI_BUS_QOS_SCHEME_ID4,Value driven on the CHI bus QoS field for scheme ID 4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 12.--15. "CHI_BUS_QOS_SCHEME_ID3,Value driven on the CHI bus QoS field for scheme ID 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. "CHI_BUS_QOS_SCHEME_ID2,Value driven on the CHI bus QoS field for scheme ID 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 4.--7. "CHI_BUS_QOS_SCHEME_ID1,Value driven on the CHI bus QoS field for scheme ID 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. "CHI_BUS_QOS_SCHEME_ID0,Value driven on the CHI bus QoS field for scheme ID 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.quad spr:0x30F45++0x00 line.long 0x00 "CLUSTERL3HIT_EL1,Cluster L3 Hit Counter Register" group.quad spr:0x30F46++0x00 line.long 0x00 "CLUSTERL3MISS_EL1,Cluster L3 Miss Counter Register" group.quad spr:0x30F47++0x00 line.long 0x00 "CLUSTERTHREADSIDOVR_EL1,Cluster Thread Scheme ID Override Register" bitfld.long 0x00 16.--18. "SCHEME_ID_MASK,A bit set in the mask causes the matching bit to be taken from this register rather than from the CLUSTERTHREADSID_EL1 register" "0,1,2,3,4,5,6,7" bitfld.long 0x00 0.--2. "SCHEME_ID_THREAD,Scheme ID for this thread if masked" "0,1,2,3,4,5,6,7" tree.end tree "Error System Registers" rgroup.quad spr:0x30530++0x00 line.long 0x00 "ERRIDR_EL1,Error ID Register" hexmask.long.word 0x00 0.--15. 1. "NUM,Number of records that can be accessed through the Error Record system registers" group.quad spr:0x30531++0x00 line.quad 0x00 "ERRSELR_EL1,Error Record Select Register" bitfld.quad 0x00 0. "SEL,Selects the record accessed through the ERX registers" "Record 0 - Core,Record 1 - DSU" if (((per.q(spr:0x30531))&0x01)==0x00) if (CORENAME()=="CORTEXA75") rgroup.quad spr:0x30540++0x00 line.quad 0x00 "ERXFR_EL1,Error Record Feature Register" bitfld.quad 0x00 10.--11. "CFI,Fault handling interrupt for corrected errors" "Reserved,Reserved,Implemented,?..." bitfld.quad 0x00 6.--7. "FI,Fault handling interrupt" "Reserved,Reserved,Implemented,?..." bitfld.quad 0x00 4.--5. "UI,Error recovery interrupt for uncorrected errors" "Reserved,Reserved,Implemented,?..." newline bitfld.quad 0x00 0.--1. "ED,Error detection and correction" "Reserved,Reserved,Implemented,?..." group.quad spr:0x30541++0x00 line.quad 0x00 "ERXCTLR_EL1,Selected Error Record Control Register" bitfld.quad 0x00 8. "CFI,Fault handling interrupt for corrected errors enable" "No interrupt,Interrupt" bitfld.quad 0x00 3. "FI,Fault handling interrupt enable" "No interrupt,Interrupt" bitfld.quad 0x00 2. "UI,Uncorrected error recovery interrupt enable" "No interrupt,Interrupt" group.quad spr:0x30542++0x00 line.long 0x00 "ERXSTATUS_EL1,Selected Error Record Status Register" bitfld.long 0x00 31. "AV,Address valid" "Not valid,Valid" bitfld.long 0x00 30. "V,Status register valid" "Not valid,Valid" bitfld.long 0x00 29. "UE,Uncorrected Error" "No error,>=1 error" newline bitfld.long 0x00 28. "ER,Error reported" "No error,Error" bitfld.long 0x00 27. "OF,Error overflow" "No error,>1 error" bitfld.long 0x00 26. "MV,Miscellaneous registers valid" "Not valid,Valid" newline bitfld.long 0x00 24.--25. "CE,Corrected errors" "No error,Reserved,>=1 error,?..." bitfld.long 0x00 23. "DE,Deferred errors" "No error,>=1 error" bitfld.long 0x00 22. "PN,Poison" "No distinction,?..." newline bitfld.long 0x00 20.--21. "UET,Uncorrected error type" "Uncontainable,?..." newline abitfld.long 0x00 0.--7. "SERR,Primary error code" "0x00=No error,0x02=ECC/internal data buffer,0x06=ECC/Cache data RAM,0x07=ECC/Cache tag/Dirty RAM,0x08=Parity/TLB data,0x09=Parity/TLB tag,0x15=Deferred not supported" group.quad spr:0x30543++0x00 line.quad 0x00 "ERXADDR_EL1,Selected Error Record Address Register" bitfld.quad 0x00 63. "NS,Non-secure attribute" "Secure,Non-secure" bitfld.quad 0x00 62. "SI,Secure incorrect" "Non secure,Secure" bitfld.quad 0x00 61. "AI,Address incomplete or incorrect" "Correct,Not correct" hexmask.quad 0x00 0.--43. 0x01 "PADDR,Physical address" group.quad spr:0x30550++0x00 line.quad 0x00 "ERXMISC0_EL1,Selected Error Record Miscellaneous Register 0" hexmask.quad.byte 0x00 32.--47. 1. "CECO,Corrected error count other" bitfld.quad 0x00 28.--31. "WAY,Indicates the way that contained the error" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.quad.word 0x00 6.--18. 1. "INDX,Indicates the index that contained the error" newline bitfld.quad 0x00 5. "TLBRAM,Indicates which TLB RAM block the error occurs" "RAM 0,RAM 1" bitfld.quad 0x00 1.--3. "LVL,Indicates the level that contained the error" "level 1,Level 2,?..." bitfld.quad 0x00 0. "IND,Indicates the type of cache that contained the error" "L1 data/Unified L2/TLB,L1 instruction" group.quad spr:0x30551++0x00 line.quad 0x00 "ERXMISC1_EL1,Selected Error Record Miscellaneous Register 1" group.quad spr:0x30F22++0x00 line.long 0x00 "ERXPFGCDN_EL1,Selected Error Pseudo Fault Generation Count Down Register" group.quad spr:0x30F21++0x00 line.quad 0x00 "ERXPFGCTL_EL1,Selected Error Pseudo Fault Generation Control Register" bitfld.quad 0x00 31. "CDNEN,Count down enable" "Disabled,Enabled" newline bitfld.quad 0x00 30. "R,Restart" "Stop,Reloaded" bitfld.quad 0x00 6. "CE,Corrected error generation enable" "Disabled,Enabled" newline bitfld.quad 0x00 5. "DE,Deferred Error generation enable" "Disabled,Enabled" bitfld.quad 0x00 1. "UC,Uncontainable error generation enable" "Disabled,Enabled" rgroup.quad spr:0x30F20++0x00 line.quad 0x00 "ERXPFGF_EL1,Selected Pseudo Fault Generation Feature Register" bitfld.quad 0x00 31. "PFG,Pseudo fault generation" "Reserved,Supported" bitfld.quad 0x00 30. "R,Error Generation Counter restart mode support" "Reserved,Supported" newline bitfld.quad 0x00 6. "CE,Corrected Error generation" "Reserved,Supported" bitfld.quad 0x00 5. "DE,Deferred error generation" "Reserved,Supported" newline bitfld.quad 0x00 4. "UEO,Latent or restartable error generation" "Not supported,?..." bitfld.quad 0x00 3. "UER,Signaled or recoverable error generation" "Not supported,?..." newline bitfld.quad 0x00 2. "UEU,Unrecoverable error generation" "Not supported,?..." bitfld.quad 0x00 1. "UC,Uncontainable error generation" "Reserved,Supported" elif (CORENAME()=="CORTEXA55") rgroup.quad spr:0x30540++0x00 line.quad 0x00 "ERXFR_EL1,Error Record Feature Register" bitfld.quad 0x00 18.--19. "CEO,Corrected Error Overwrite" "Count CE,?..." bitfld.quad 0x00 16.--17. "DUI,Error recovery interrupt for deferred errors" "Not supported,?..." bitfld.quad 0x00 15. "RP,Repeat counter" "Reserved,Implemented" newline bitfld.quad 0x00 12.--14. "CEC,Corrected Error Counter" "Reserved,Reserved,8-bit,?..." bitfld.quad 0x00 10.--11. "CFI,Fault handling interrupt for corrected errors" "Reserved,Reserved,Implemented,?..." bitfld.quad 0x00 8.--9. "UE,In-band uncorrected error reporting" "Reserved,Implemented,?..." newline bitfld.quad 0x00 6.--7. "FI,Fault handling interrupt" "Reserved,Reserved,Implemented,?..." bitfld.quad 0x00 4.--5. "UI,Error recovery interrupt for uncorrected errors" "Reserved,Reserved,Implemented,?..." bitfld.quad 0x00 2.--3. "DE,Defers errors" "Reserved,Enabled,?..." newline bitfld.quad 0x00 0.--1. "ED,Error detection and correction" "Reserved,Reserved,Implemented,?..." group.quad spr:0x30541++0x00 line.quad 0x00 "ERXCTLR_EL1,Selected Error Record Control Register" bitfld.quad 0x00 8. "CFI,Fault handling interrupt for corrected errors enable" "No interrupt,Interrupt" bitfld.quad 0x00 3. "FI,Fault handling interrupt enable" "No interrupt,Interrupt" bitfld.quad 0x00 2. "UI,Uncorrected error recovery interrupt enable" "No interrupt,Interrupt" newline bitfld.quad 0x00 0. "ED,Error detection and correction enable" "Disabled,Enabled" group.quad spr:0x30542++0x00 line.long 0x00 "ERXSTATUS_EL1,Selected Error Record Status Register" bitfld.long 0x00 31. "AV,Address valid" "Not valid,?..." bitfld.long 0x00 30. "V,Status register valid" "Not valid,Valid" bitfld.long 0x00 29. "UE,Uncorrected Error" "No error,>=1 error" newline bitfld.long 0x00 28. "ER,Error reported" "No error,Error" bitfld.long 0x00 27. "OF,Error overflow" "No error,>1 error" bitfld.long 0x00 26. "MV,Miscellaneous registers valid" "Not valid,Valid" newline bitfld.long 0x00 24.--25. "CE,Corrected errors" "No error,Reserved,>=1 error,?..." bitfld.long 0x00 23. "DE,Deferred errors" "No error,>=1 error" bitfld.long 0x00 22. "PN,Poison" "No distinction,?..." newline bitfld.long 0x00 20.--21. "UET,Uncorrected error type" "Uncontainable,?..." newline abitfld.long 0x00 8.--15. "IERR,Implementation defined error code" "0x00=No error/Other RAMs,0x01=Error/L3 snoop RAM" abitfld.long 0x00 0.--7. "SERR,Primary error code" "0x00=No error,0x02=ECC/internal data buffer,0x06=ECC/Cache data RAM,0x07=ECC/Cache tag/Dirty RAM,0x08=Parity/TLB data,0x09=Parity/TLB tag,0x15=Deferred not supported" rgroup.quad spr:0x30543++0x00 line.quad 0x00 "ERXADDR_EL1,Selected Error Record Address Register" group.quad spr:0x30550++0x00 line.quad 0x00 "ERXMISC0_EL1,Selected Error Record Miscellaneous Register 0" bitfld.quad 0x00 47. "OFO,Sticky overflow bit other" "No overflow,Overflow" hexmask.quad.byte 0x00 40.--46. 1. "CECO,Corrected error count other" bitfld.quad 0x00 39. "OFR,Sticky overflow bit repeat" "No overflow,Overflow" newline hexmask.quad.byte 0x00 32.--38. 1. "CECR,Repeat error count" bitfld.quad 0x00 28.--31. "WAY,Indicates the way that contained the error" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.quad.word 0x00 6.--18. 1. "INDX,Indicates the index that contained the error" newline bitfld.quad 0x00 1.--3. "LVL,Indicates the level that contained the error" "level 1,Level 2,?..." bitfld.quad 0x00 0. "IND,Indicates the type of cache that contained the error" "L1 data/Unified L2/TLB,L1 instruction" group.quad spr:0x30551++0x00 line.quad 0x00 "ERXMISC1_EL1,Selected Error Record Miscellaneous Register 1" group.quad spr:0x30F22++0x00 line.long 0x00 "ERXPFGCDN_EL1,Selected Error Pseudo Fault Generation Count Down Register" group.quad spr:0x30F21++0x00 line.quad 0x00 "ERXPFGCTL_EL1,Selected Error Pseudo Fault Generation Control Register" bitfld.quad 0x00 31. "CDNEN,Count down enable" "Disabled,Enabled" newline bitfld.quad 0x00 30. "R,Restart" "Stop,Reloaded" bitfld.quad 0x00 6. "CE,Corrected error generation enable" "Disabled,Enabled" newline bitfld.quad 0x00 5. "DE,Deferred Error generation enable" "Disabled,Enabled" bitfld.quad 0x00 3. "UER,Signaled or recoverable error generation enable" "Disabled,Enabled" newline bitfld.quad 0x00 1. "UC,Uncontainable error generation enable" "Disabled,Enabled" rgroup.quad spr:0x30F20++0x00 line.quad 0x00 "ERXPFGF_EL1,Selected Pseudo Fault Generation Feature Register" bitfld.quad 0x00 31. "PFG,Pseudo fault generation" "Not supported,Supported" bitfld.quad 0x00 30. "R,Error Generation Counter restart mode support" "Reserved,Supported" newline bitfld.quad 0x00 6. "CE,Corrected Error generation" "Not supported,Supported" bitfld.quad 0x00 5. "DE,Deferred error generation" "Not supported,Supported" newline bitfld.quad 0x00 4. "UEO,Latent or restartable error generation" "Not supported,?..." bitfld.quad 0x00 3. "UER,Signaled or recoverable error generation" "Not supported,Supported" newline bitfld.quad 0x00 2. "UEU,Unrecoverable error generation" "Not supported,?..." bitfld.quad 0x00 1. "UC,Uncontainable error generation" "Not supported,Supported" endif else rgroup.quad spr:0x30540++0x00 line.quad 0x00 "ERXFR_EL1,Error Record Feature Register" bitfld.quad 0x00 18.--19. "CEO,Corrected Error Overwrite" "Count CE,?..." bitfld.quad 0x00 16.--17. "DUI,Error recovery interrupt for deferred errors" "Not supported,?..." bitfld.quad 0x00 15. "RP,Repeat counter" "Reserved,Implemented" newline bitfld.quad 0x00 12.--14. "CEC,Corrected Error Counter" "Reserved,Reserved,8-bit,?..." bitfld.quad 0x00 10.--11. "CFI,Fault handling interrupt for corrected errors" "Reserved,Reserved,Implemented,?..." bitfld.quad 0x00 8.--9. "UE,In-band uncorrected error reporting" "Reserved,Implemented,?..." newline bitfld.quad 0x00 6.--7. "FI,Fault handling interrupt" "Reserved,Reserved,Implemented,?..." bitfld.quad 0x00 4.--5. "UI,Error recovery interrupt for uncorrected errors" "Reserved,Enabled,Implemented,?..." bitfld.quad 0x00 2.--3. "DE,Defers errors" "Reserved,Enabled,?..." newline bitfld.quad 0x00 0.--1. "ED,Error detection and correction" "Reserved,Enabled,Implemented,?..." group.quad spr:0x30541++0x00 line.quad 0x00 "ERXCTLR_EL1,Selected Error Record Control Register" bitfld.quad 0x00 8. "CFI,Fault handling interrupt for corrected errors enable" "No interrupt,Interrupt" bitfld.quad 0x00 3. "FI,Fault handling interrupt enable" "No interrupt,Interrupt" bitfld.quad 0x00 2. "UI,Uncorrected error recovery interrupt enable" "No interrupt,Interrupt" newline bitfld.quad 0x00 0. "ED,Error detection and correction enable" "Disabled,Enabled" group.quad spr:0x30542++0x00 line.long 0x00 "ERXSTATUS_EL1,Selected Error Record Status Register" bitfld.long 0x00 31. "AV,Address valid" "Not valid,?..." bitfld.long 0x00 30. "V,Status register valid" "Not valid,Valid" bitfld.long 0x00 29. "UE,Uncorrected Error" "No error,>=1 error" newline bitfld.long 0x00 28. "ER,Error reported" "No error,?..." bitfld.long 0x00 27. "OF,Error overflow" "No error,>1 error" bitfld.long 0x00 26. "MV,Miscellaneous registers valid" "Not valid,Valid" newline bitfld.long 0x00 24.--25. "CE,Corrected errors" "No error,Reserved,>=1 error,?..." bitfld.long 0x00 23. "DE,Deferred errors" "No error,>=1 error" bitfld.long 0x00 22. "PN,Poison" "No distinction,Earlier" newline bitfld.long 0x00 20.--21. "UET,Uncorrected error type" "Uncontainable,?..." newline bitfld.long 0x00 8.--15. "IERR,Implementation defined error code" "No error/Other RAMs,Reserved,Error/L3 snoop RAM,?..." bitfld.long 0x00 0.--7. "SERR,Primary error code" "No error,Reserved,ECC/internal data buffer,Reserved,Reserved,Reserved,ECC/Cache data RAM,ECC/Cache tag/Dirty RAM,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Bus error,?..." rgroup.quad spr:0x30543++0x00 line.quad 0x00 "ERXADDR_EL1,Selected Error Record Address Register" group.quad spr:0x30550++0x00 line.quad 0x00 "ERXMISC0_EL1,Selected Error Record Miscellaneous Register 0" bitfld.quad 0x00 47. "OFO,Sticky overflow bit other" "No overflow,Overflow" hexmask.quad.byte 0x00 40.--46. 1. "CECO,Corrected error count other" bitfld.quad 0x00 39. "OFR,Sticky overflow bit repeat" "No overflow,Overflow" newline hexmask.quad.byte 0x00 32.--38. 1. "CECR,Repeat error count" bitfld.quad 0x00 28.--31. "WAY,Indicates the way that contained the error" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.quad.word 0x00 6.--18. 1. "INDX,Indicates the index that contained the error" newline bitfld.quad 0x00 1.--3. "LVL,Indicates the level that contained the error" "Reserved,Reserved,Level 3,?..." bitfld.quad 0x00 0. "IND,Indicates the type of cache that contained the error" "L3 cache,?..." group.quad spr:0x30551++0x00 line.quad 0x00 "ERXMISC1_EL1,Selected Error Record Miscellaneous Register 1" group.quad spr:0x30F22++0x00 line.long 0x00 "ERXPFGCDN_EL1,Selected Error Pseudo Fault Generation Count Down Register" group.quad spr:0x30F21++0x00 line.quad 0x00 "ERXPFGCTL_EL1,Selected Error Pseudo Fault Generation Control Register" bitfld.quad 0x00 31. "CDNEN,Count down enable" "Disabled,Enabled" newline bitfld.quad 0x00 30. "R,Restart" "Stop,Reloaded" bitfld.quad 0x00 6. "CE,Corrected error generation" "Not generated,Generated" newline bitfld.quad 0x00 5. "DE,Deferred Error generation enable" "Not generated,Generated" bitfld.quad 0x00 1. "UC,Signaled or recoverable error generation enable" "Not supported,Controllable" rgroup.quad spr:0x30F20++0x00 line.quad 0x00 "ERXPFGF_EL1,Selected Pseudo Fault Generation Feature Register" bitfld.quad 0x00 31. "PFG,Pseudo fault generation" "Not supported,Supported" bitfld.quad 0x00 30. "R,Error Generation Counter restart mode support" "Reserved,Supported" newline bitfld.quad 0x00 6. "CE,Corrected Error generation" "Reserved,Supported" bitfld.quad 0x00 5. "DE,Deferred error generation" "Reserved,Supported" newline bitfld.quad 0x00 4. "UEO,Latent or restartable error generation" "Not supported,?..." bitfld.quad 0x00 3. "UER,Signaled or recoverable error generation" "Not supported,?..." newline bitfld.quad 0x00 2. "UEU,Unrecoverable error generation" "Not supported,?..." bitfld.quad 0x00 1. "UC,Uncontainable error generation" "Reserved,Supported" endif tree.end tree "Cluster PMU Registers" group.quad spr:0x30F50++0x00 line.long 0x00 "CLUSTERPMCR_EL1,Cluster Performance Monitors Control Register (EL1)" hexmask.long.byte 0x00 24.--31. 1. "IMP,Implementer code" hexmask.long.byte 0x00 16.--23. 1. "IDCODE,Identification code" bitfld.long 0x00 11.--15. "N,Number of counters implemented" "Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,6,?..." newline bitfld.long 0x00 2. "C,Clock Counter Reset" "No reset,Reset" bitfld.long 0x00 1. "P,Event Counter Reset" "No reset,Reset" newline bitfld.long 0x00 0. "E,All Counters Enable" "Disabled,Enabled" group.quad spr:0x30F51++0x00 line.long 0x00 "CLUSTERPMCNTENSET_EL1,Cluster Count Enable Set Register (EL1)" bitfld.long 0x00 31. "C,Enables the cycle counter register [Read/Write]" "Disabled/No effect,Enabled/Enable" newline bitfld.long 0x00 5. "P5,Event counter PMN 5 enable bit [Read/Write]" "Disabled/No effect,Enabled/Enable" bitfld.long 0x00 4. "P4,Event counter PMN 4 enable bit [Read/Write]" "Disabled/No effect,Enabled/Enable" bitfld.long 0x00 3. "P3,Event counter PMN 3 enable bit [Read/Write]" "Disabled/No effect,Enabled/Enable" newline bitfld.long 0x00 2. "P2,Event counter PMN 2 enable bit [Read/Write]" "Disabled/No effect,Enabled/Enable" bitfld.long 0x00 1. "P1,Event counter PMN 1 enable bit [Read/Write]" "Disabled/No effect,Enabled/Enable" bitfld.long 0x00 0. "P0,Event counter PMN 0 enable bit [Read/Write]" "Disabled/No effect,Enabled/Enable" group.quad spr:0x30F52++0x00 line.long 0x00 "CLUSTERPMCNTENCLR_EL1,Cluster Count Enable Clear Register (EL1)" bitfld.long 0x00 31. "C,Disables the cycle counter register [Read/Write]" "Disabled/No effect,Enabled/Disable" newline bitfld.long 0x00 5. "P5,Event counter PMN 5 disable bit [Read/Write]" "Disabled/No effect,Enabled/Disable" bitfld.long 0x00 4. "P4,Event counter PMN 4 disable bit [Read/Write]" "Disabled/No effect,Enabled/Disable" bitfld.long 0x00 3. "P3,Event counter PMN 3 disable bit [Read/Write]" "Disabled/No effect,Enabled/Disable" newline bitfld.long 0x00 2. "P2,Event counter PMN 2 disable bit [Read/Write]" "Disabled/No effect,Enabled/Disable" bitfld.long 0x00 1. "P1,Event counter PMN 1 disable bit [Read/Write]" "Disabled/No effect,Enabled/Disable" bitfld.long 0x00 0. "P0,Event counter PMN 0 disable bit [Read/Write]" "Disabled/No effect,Enabled/Disable" group.quad spr:0x30F53++0x00 line.long 0x00 "CLUSTERPMOVSSET_EL1,Cluster Overflow Flag Status Set (EL1)" bitfld.long 0x00 31. "C,PMCCNTR overflow bit [Read/Write]" "No overflow/No effect,Overflow/Set" newline bitfld.long 0x00 5. "P5,PMN5 Overflow set bit [Read/Write]" "No overflow/No effect,Overflow/Set" bitfld.long 0x00 4. "P4,PMN4 Overflow set bit [Read/Write]" "No overflow/No effect,Overflow/Set" bitfld.long 0x00 3. "P3,PMN3 Overflow set bit [Read/Write]" "No overflow/No effect,Overflow/Set" newline bitfld.long 0x00 2. "P2,PMN2 Overflow set bit [Read/Write]" "No overflow/No effect,Overflow/Set" bitfld.long 0x00 1. "P1,PMN1 Overflow set bit [Read/Write]" "No overflow/No effect,Overflow/Set" bitfld.long 0x00 0. "P0,PMN0 Overflow set bit [Read/Write]" "No overflow/No effect,Overflow/Set" group.quad spr:0x30F54++0x00 line.long 0x00 "CLUSTERPMOVSCLR_EL1,Cluster Overflow Flag Status Clear (EL1)" eventfld.long 0x00 31. "C,PMCCNTR overflow bit [Read/Write]" "No overflow/No effect,Overflow/Clear" newline eventfld.long 0x00 5. "P5,PMN5 overflow clear bit [Read/Write]" "No overflow/No effect,Overflow/Clear" eventfld.long 0x00 4. "P4,PMN4 Overflow clear bit [Read/Write]" "No overflow/No effect,Overflow/Clear" eventfld.long 0x00 3. "P3,PMN3 Overflow clear bit [Read/Write]" "No overflow/No effect,Overflow/Clear" newline eventfld.long 0x00 2. "P2,PMN2 Overflow clear bit [Read/Write]" "No overflow/No effect,Overflow/Clear" eventfld.long 0x00 1. "P1,PMN1 Overflow clear bit [Read/Write]" "No overflow/No effect,Overflow/Clear" eventfld.long 0x00 0. "P0,PMN0 Overflow clear bit [Read/Write]" "No overflow/No effect,Overflow/Clear" group.quad spr:0x30F55++0x00 line.long 0x00 "CLUSTERPMSELR_EL1,Cluster Event Counter Selection Register (EL1)" bitfld.long 0x00 0.--4. "SEL,Current event counter select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.quad spr:0x30F56++0x00 line.long 0x00 "CLUSTERPMINTENSET_EL1,Cluster Interrupt Enable Set Register (EL1)" bitfld.long 0x00 31. "C,PMCCNTR Overflow Interrupt Request Enable [Read/Write]" "Disabled/No effect,Enabled/Enable" newline bitfld.long 0x00 5. "P5,PMCNT5 Overflow Interrupt Request Enable [Read/Write]" "Disabled/No effect,Enabled/Enable" bitfld.long 0x00 4. "P4,PMCNT4 Overflow Interrupt Request Enable [Read/Write]" "Disabled/No effect,Enabled/Enable" bitfld.long 0x00 3. "P3,PMCNT3 Overflow Interrupt Request Enable [Read/Write]" "Disabled/No effect,Enabled/Enable" newline bitfld.long 0x00 2. "P2,PMCNT2 Overflow Interrupt Request Enable [Read/Write]" "Disabled/No effect,Enabled/Enable" bitfld.long 0x00 1. "P1,PMCNT1 Overflow Interrupt Request Enable [Read/Write]" "Disabled/No effect,Enabled/Enable" bitfld.long 0x00 0. "P0,PMCNT0 Overflow Interrupt Request Enable [Read/Write]" "Disabled/No effect,Enabled/Enable" group.quad spr:0x30F57++0x00 line.long 0x00 "CLUSTERPMINTENCLR_EL1,Cluster Interrupt Enable Clear Register (EL1)" eventfld.long 0x00 31. "C,PMCCNTR Overflow Interrupt Request Disable [Read/Write]" "Disabled/No effect,Enabled/Disable" newline eventfld.long 0x00 5. "P5,PMCNT5 Overflow Interrupt Disable [Read/Write]" "Disabled/No effect,Enabled/Disable" eventfld.long 0x00 4. "P4,PMCNT4 Overflow Interrupt Disable [Read/Write]" "Disabled/No effect,Enabled/Disable" eventfld.long 0x00 3. "P3,PMCNT3 Overflow Interrupt Disable [Read/Write]" "Disabled/No effect,Enabled/Disable" newline eventfld.long 0x00 2. "P2,PMCNT2 Overflow Interrupt Disable [Read/Write]" "Disabled/No effect,Enabled/Disable" eventfld.long 0x00 1. "P1,PMCNT1 Overflow Interrupt Disable [Read/Write]" "Disabled/No effect,Enabled/Disable" eventfld.long 0x00 0. "P0,PMCNT0 Overflow Interrupt Disable [Read/Write]" "Disabled/No effect,Enabled/Disable" if (((per.l(spr:0x30F55))&0x1F)<=0x05) if (((per.q(spr:0x30F61))&0x80000000)==0x00) group.quad spr:0x30F61++0x00 line.long 0x00 "CLUSTERPMXEVTYPER_EL1,Cluster Selected Event Type and Filter Register (EL1)" bitfld.long 0x00 31. "S,Count events in EL1 disable" "No,Yes" bitfld.long 0x00 29. "NS,Count events in non-secure EL2 disable" "No,Yes" newline hexmask.long.word 0x00 0.--15. 1. "EVTCOUNT,Event number" else group.quad spr:0x30F61++0x00 line.long 0x00 "CLUSTERPMXEVTYPER_EL1,Cluster Selected Event Type and Filter Register (EL1)" bitfld.long 0x00 31. "S,Count events in EL1 disable" "No,Yes" bitfld.long 0x00 29. "NS,Count events in non-secure EL2 disable" "Yes,No" newline hexmask.long.word 0x00 0.--15. 1. "EVTCOUNT,Event number" endif else rgroup.quad spr:0x30F61++0x00 line.long 0x00 "CLUSTERPMXEVTYPER_EL1,Cluster Selected Event Type and Filter Register (EL1)" endif group.quad spr:0x30F62++0x00 line.long 0x00 "CLUSTERPMXEVCNTR_EL1,Cluster Selected Event Counter Register (EL1)" tree.open "Common Event Identification Registers" rgroup.quad spr:0x30F64++0x00 line.long 0x00 "CLUSTERPMCEID0_EL1,Cluster Common Event Identification ID0 Register (EL1)" bitfld.long 0x00 30. "CHAIN,Chain" "Reserved,Implemented" bitfld.long 0x00 29. "BUS_CYCLES,Bus cycle" "Reserved,Implemented" bitfld.long 0x00 26. "MEMORY_ERROR,Local memory error" "Reserved,Implemented" newline bitfld.long 0x00 25. "BUS_ACCESS,Bus access" "Reserved,Implemented" bitfld.long 0x00 17. "CPU_CYCLES,CPU Cycle" "Reserved,Implemented" rgroup.quad spr:0x30F65++0x00 line.long 0x00 "CLUSTERPMCEID1_EL1,Cluster Common Event Identification ID1 Register (EL1)" bitfld.long 0x00 12. "L3D_CACHE_WB,Attributable Level 3 data or unified cache write-back" "Reserved,Implemented" bitfld.long 0x00 11. "L3D_CACHE,Attributable Level 3 data or unified cache access" "Reserved,Implemented" bitfld.long 0x00 10. "L3D_CACHE_REFILL,Attributable Level 3 data or unified cache refill" "Reserved,Implemented" newline bitfld.long 0x00 9. "L3D_CACHE_ALLOCATE,Attributable Level 3 data or unified cache allocation without refill" "Reserved,Implemented" tree.end newline group.quad spr:0x30F66++0x00 line.long 0x00 "CLUSTERPMCLAIMSET_EL1,Cluster Performance Monitor Claim Tag Set Register (EL1)" bitfld.long 0x00 3. "S[3],Set bit 3 [Read/Write]" "Not implemented/No effect,Implemented/Set" bitfld.long 0x00 2. "S[2],Set bit 2 [Read/Write]" "Not implemented/No effect,Implemented/Set" bitfld.long 0x00 1. "S[1],Set bit 1 [Read/Write]" "Not implemented/No effect,Implemented/Set" bitfld.long 0x00 0. "S[0],Set bit 0 [Read/Write]" "Not implemented/No effect,Implemented/Set" group.quad spr:0x30F67++0x00 line.long 0x00 "CLUSTERPMCLAIMCLR_EL1,Cluster Performance Monitor Claim Tag Clear Register (EL1)" bitfld.long 0x00 3. "C[3],Clear bit 3 [Read/Write]" "Not implemented/No effect,Implemented/Set" bitfld.long 0x00 2. "C[2],Clear bit 2 [Read/Write]" "Not implemented/No effect,Implemented/Set" bitfld.long 0x00 1. "C[1],Clear bit 1 [Read/Write]" "Not implemented/No effect,Implemented/Set" bitfld.long 0x00 0. "C[0],Clear bit 0 [Read/Write]" "Not implemented/No effect,Implemented/Set" tree.end tree.end tree.end tree.open "AArch32" tree "ID Registers" rgroup.long c15:0x0010++0x00 line.long 0x00 "ID_PFR0,Processor Feature Register 0" bitfld.long 0x00 28.--31. "RAS,RAS extension version" "Reserved,Version 1,?..." newline bitfld.long 0x00 12.--15. "STATE3,Thumb Execution Environment (Thumb-EE) Support" "Not supported,?..." bitfld.long 0x00 8.--11. "STATE2,Support for Jazelle extension" "Reserved,Trivial,?..." bitfld.long 0x00 4.--7. "STATE1,Thumb Encoding Supported by the Processor Type" "Reserved,Reserved,Reserved,After Thumb-2,?..." newline bitfld.long 0x00 0.--3. "STATE0,ARM Instruction Set Support" "Reserved,Supported,?..." rgroup.long c15:0x0110++0x00 line.long 0x00 "ID_PFR1,Processor Feature Register 1" bitfld.long 0x00 28.--31. "GIC_CPU,GIC CPU Support" "Disabled,Enabled,?..." newline bitfld.long 0x00 16.--19. "GT,Generic Timer Support" "Reserved,Supported,?..." bitfld.long 0x00 12.--15. "VE,Virtualization Extensions Support" "Reserved,Supported,?..." bitfld.long 0x00 8.--11. "MPM,Microcontroller Programmer's Model Support" "Not supported,?..." newline bitfld.long 0x00 4.--7. "SE,Security Extensions Architecture v1 Support" "Reserved,Supported,?..." bitfld.long 0x00 0.--3. "PM,Standard ARMv4 Programmer's Model Support" "Reserved,Supported,?..." rgroup.long c15:0x0310++0x00 line.long 0x00 "ID_AFR0,Auxiliary Feature Register 0" rgroup.long c15:0x0410++0x00 line.long 0x00 "ID_MMFR0,Memory Model Feature Register 0" bitfld.long 0x00 28.--31. "IS,Indicates innermost shareability domain implemented" "Reserved,HW coherency,?..." bitfld.long 0x00 24.--27. "FCSE,Fast Context Switch Memory Mappings Support" "Not supported,?..." bitfld.long 0x00 20.--23. "AR,Auxiliary Register Support" "Reserved,Reserved,Control/Fault Status,?..." newline bitfld.long 0x00 16.--19. "TCM,TCM and Associated DMA Support" "Not supported,?..." bitfld.long 0x00 12.--15. "SL,Shareability levels" "Reserved,Implemented 2 levels,?..." bitfld.long 0x00 8.--11. "OSS,Outer Shareable Support" "Reserved,HW coherency,?..." newline bitfld.long 0x00 4.--7. "PMSA,Physical Memory System Architecture (PMSA) Support" "Not supported,?..." bitfld.long 0x00 0.--3. "VMSA,Virtual Memory System Architecture (VMSA) Support" "Reserved,Reserved,Reserved,Reserved,Reserved,VMSAv7/PXN/L-DESC,?..." rgroup.long c15:0x0510++0x00 line.long 0x00 "ID_MMFR1,Memory Model Feature Register 1" bitfld.long 0x00 28.--31. "BTB,Branch Predictor" "Reserved,Reserved,Reserved,Reserved,No flushing,?..." bitfld.long 0x00 24.--27. "L1TCO,Test and Clean Operations on Data Cache/Harvard/Unified Architecture Support" "Not supported,?..." bitfld.long 0x00 20.--23. "L1UCMO,L1 Cache/All Maintenance Operations/Unified Architecture Support" "Not supported,?..." newline bitfld.long 0x00 16.--19. "L1HCMO,L1 Cache/All Maintenance Operations/Harvard Architecture Support" "Not supported,?..." newline bitfld.long 0x00 12.--15. "L1UCLMOSW,L1 Cache Line Maintenance Operations by Set and Way/Unified Architecture Support" "Not supported,?..." bitfld.long 0x00 8.--11. "L1HCLMOSW,L1 Cache Line Maintenance Operations by Set and Way/Harvard Architecture Support" "Not supported,?..." newline bitfld.long 0x00 4.--7. "L1UCLMOMVA,L1 Cache Line Maintenance Operations by VA/Unified Architecture Support" "Not supported,?..." newline bitfld.long 0x00 0.--3. "L1HCLMOMVA,L1 Cache Line Maintenance Operations by VA/Harvard Architecture" "Not supported,?..." rgroup.long c15:0x0610++0x00 line.long 0x00 "ID_MMFR2,Memory Model Feature Register 2" bitfld.long 0x00 28.--31. "HAF,Hardware Access Flag Support" "Not supported,?..." bitfld.long 0x00 24.--27. "WFI,Wait for Interrupt Stalling Support" "Reserved,Supported,?..." bitfld.long 0x00 20.--23. "MBF,Memory Barrier Operations Support" "Reserved,Reserved,DSB/ISB/DMB,?..." newline bitfld.long 0x00 16.--19. "UTLBMO,TLB Maintenance Operations/Unified Architecture Support" "Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,S2 operations,?..." newline bitfld.long 0x00 12.--15. "HTLBMO,TLB Maintenance Operations/Harvard Architecture Support" "Not supported,?..." bitfld.long 0x00 8.--11. "HL1CMRO,Cache Maintenance Range Operations/Harvard Architecture Support" "Not supported,?..." bitfld.long 0x00 4.--7. "HL1BPCRO,Background Prefetch Cache Range Operations/Harvard Architecture Support" "Not supported,?..." newline bitfld.long 0x00 0.--3. "HL1FPCRO,Foreground Prefetch Cache Range Operations/Harvard Architecture Support" "Not supported,?..." rgroup.long c15:0x0710++0x00 line.long 0x00 "ID_MMFR3,Memory Model Feature Register 3" bitfld.long 0x00 28.--31. "SS,Supersection support" "Supported,?..." bitfld.long 0x00 24.--27. "CMEMSZ,Cache memory size" "Reserved,Reserved,1TByte,?..." bitfld.long 0x00 20.--23. "CW,Coherent walk" "Reserved,Not required,?..." newline bitfld.long 0x00 16.--19. "PAN,Privileged Access Never Support" "Reserved,Reserved,Extended,?..." bitfld.long 0x00 12.--15. "MB,Maintenance broadcast Support" "Reserved,Reserved,Shareability/Defined behavior,?..." bitfld.long 0x00 8.--11. "BPM,Invalidate Branch predictor Support" "Reserved,Reserved,Invalidate All/VA,?..." newline bitfld.long 0x00 4.--7. "CMSW,Cache maintenance by set/way" "Reserved,Supported,?..." bitfld.long 0x00 0.--3. "CMMVA,Cache maintenance by MVA" "Reserved,Supported,?..." rgroup.long c15:0x0620++0x00 line.long 0x00 "ID_MMFR4,Memory Model Feature Register 4" bitfld.long 0x00 20.--23. "LSM,LSMAOE and NTLSMD bits support" "Not supported,?..." bitfld.long 0x00 16.--19. "HD,Hierarchical Permission Disables Support" "Reserved,Reserved,Extended,?..." bitfld.long 0x00 12.--15. "CNP,Common not Private support" "Reserved,Supported,?..." newline bitfld.long 0x00 8.--11. "XNX,EL0/EL1 execute control distinction at stage2 bit support" "Reserved,Supported,?..." bitfld.long 0x00 4.--7. "AC2,Indicates the extension of the HACTLR Register using HACTLR2" "Reserved,Supported,?..." bitfld.long 0x00 0.--3. "SPECSEI,Describes whether the PE can generate SError interrupt exceptions" "Not possible,?..." rgroup.long c15:0x0020++0x00 line.long 0x00 "ID_ISAR0,ID_ISAR0" bitfld.long 0x00 24.--27. "DIVI,Divide Instructions Support" "Reserved,Reserved,T32/A32,?..." bitfld.long 0x00 20.--23. "DEBI,Debug Instructions Support" "Reserved,Supported,?..." bitfld.long 0x00 16.--19. "CI,Coprocessor Instructions Support" "Not supported,?..." newline bitfld.long 0x00 12.--15. "CBI,Combined Compare and Branch Instructions Support" "Reserved,Supported,?..." bitfld.long 0x00 8.--11. "BI,Bitfield Instructions Support" "Reserved,Supported,?..." bitfld.long 0x00 4.--7. "BCI,Bit Counting Instructions Support" "Reserved,Supported,?..." newline bitfld.long 0x00 0.--3. "SI,Swap Instructions Support" "Not supported,?..." rgroup.long c15:0x0120++0x00 line.long 0x00 "ID_ISAR1,ID_ISAR1" bitfld.long 0x00 28.--31. "JI,Jazelle Instructions Support" "Reserved,Supported,?..." bitfld.long 0x00 24.--27. "INTI,Interwork Instructions Support" "Reserved,Reserved,Reserved,A32-BX like,?..." bitfld.long 0x00 20.--23. "IMMI,Immediate Instructions Support" "Reserved,Supported,?..." newline bitfld.long 0x00 16.--19. "ITEI,If Then Instructions Support" "Reserved,Supported,?..." bitfld.long 0x00 12.--15. "EXTI,Extend Instructions Support" "Reserved,Reserved,Full support,?..." bitfld.long 0x00 8.--11. "EARI,Exception A and R Instructions Support" "Reserved,Supported,?..." newline bitfld.long 0x00 4.--7. "EXIN,Exception in ARM Instructions Support" "Reserved,Supported,?..." bitfld.long 0x00 0.--3. "ENDI,Endian Instructions Support" "Reserved,Supported,?..." rgroup.long c15:0x0220++0x00 line.long 0x00 "ID_ISAR2,ID_ISAR2" bitfld.long 0x00 28.--31. "RI,Reversal Instructions Support" "Reserved,Reserved,Supported,?..." bitfld.long 0x00 24.--27. "PSRI,PSR Instructions Support" "Not supported,Supported,?..." bitfld.long 0x00 20.--23. "UMI,Advanced Unsigned Multiply Instructions Support" "Reserved,Reserved,UMAAL,?..." newline bitfld.long 0x00 16.--19. "SMI,Advanced Signed Multiply Instructions Support" "Reserved,Reserved,Reserved,Supported,?..." newline bitfld.long 0x00 12.--15. "MI,Multiply Instructions Support" "Reserved,Reserved,Supported,?..." bitfld.long 0x00 8.--11. "II,Multi-Access Interruptible Instructions Support" "Not supported,?..." newline bitfld.long 0x00 4.--7. "MHI,Memory Hint Instructions Support" "Reserved,Reserved,Reserved,Reserved,PLD/PLI/PLDW,?..." bitfld.long 0x00 0.--3. "LSI,Load and Store Instructions Support" "Reserved,Reserved,Supported,?..." rgroup.long c15:0x0320++0x00 line.long 0x00 "ID_ISAR3,ID_ISAR3" bitfld.long 0x00 28.--31. "T32EE,Thumb-EE Extensions Support" "Not supported,?..." bitfld.long 0x00 24.--27. "NOPI,True NOP Instructions Support" "Reserved,Supported,?..." bitfld.long 0x00 20.--23. "TCI,Thumb Copy Instructions Support" "Reserved,Supported,?..." newline bitfld.long 0x00 16.--19. "TBI,Table Branch Instructions Support" "Reserved,Supported,?..." bitfld.long 0x00 12.--15. "SPI,Synchronization Primitive Instructions Support" "Reserved,Reserved,Supported,?..." bitfld.long 0x00 8.--11. "SVCI,SVC Instructions Support" "Reserved,Supported,?..." newline bitfld.long 0x00 4.--7. "SIMDI,Single Instruction Multiple Data (SIMD) Instructions Support" "Reserved,Reserved,Reserved,Supported,?..." bitfld.long 0x00 0.--3. "SI,Saturate Instructions Support" "Reserved,Supported,?..." rgroup.long c15:0x0420++0x00 line.long 0x00 "ID_ISAR4,ID_ISAR4" bitfld.long 0x00 28.--31. "SWP_FRAC,Memory System Locking Support" "Not supported,?..." bitfld.long 0x00 24.--27. "PSR_M_I,PSR_M Instructions Support" "Not supported,?..." bitfld.long 0x00 20.--23. "SPRI,Synchronization Primitive instructions" "Supported,?..." newline bitfld.long 0x00 16.--19. "BI,Barrier Instructions Support" "Reserved,Supported,?..." bitfld.long 0x00 12.--15. "SMCI,SMC Instructions Support" "Reserved,Supported,?..." bitfld.long 0x00 8.--11. "WBI,Write-Back Instructions Support" "Reserved,Supported,?..." newline bitfld.long 0x00 4.--7. "WSI,With-Shift Instructions Support" "Reserved,Reserved,Reserved,Reserved,Supported,?..." bitfld.long 0x00 0.--3. "UI,Unprivileged Instructions Support" "Reserved,Reserved,Supported,?..." rgroup.long c15:0x0520++0x00 line.long 0x00 "ID_ISAR5,Instruction Set Attribute Register 5" bitfld.long 0x00 24.--27. "RDM,Rounding Double Multiply Add/Subtract instructions Support" "Reserved,Supported,?..." bitfld.long 0x00 16.--19. "CRC32,Indicates whether CRC32 instructions are implemented in AArch32 state" "Reserved,Supported,?..." bitfld.long 0x00 12.--15. "SHA2,Indicates whether SHA2 instructions are implemented in AArch32 state" "Not supported,Supported,?..." newline bitfld.long 0x00 8.--11. "SHA1,Indicates whether SHA1 instructions are implemented in AArch32 state" "Not supported,Supported,?..." bitfld.long 0x00 4.--7. "AES,Indicates whether AES instructions are implemented in AArch32 state" "Not supported,Reserved,Supported,?..." bitfld.long 0x00 0.--3. "SEVL,Indicates whether SEVL instruction is implemented in AArch32" "Reserved,Supported,?..." rgroup.long c15:0x0720++0x00 line.long 0x00 "ID_ISAR6,Instruction Set Attribute Register 6" bitfld.long 0x00 4.--7. "DP,Indicates UDOT and SDOT instructions in AArch32 state" "Reserved,Implemented,?..." rgroup.long c15:0x0210++0x00 line.long 0x00 "ID_DFR0,Debug Feature Register" bitfld.long 0x00 24.--27. "PMM,Performance Monitor Model Support" "Reserved,Reserved,Reserved,Reserved,Supported/16bit evtCount,?..." bitfld.long 0x00 20.--23. "MDM_MM,Memory-mapped Debug Model for M profile processors Support" "Not supported,?..." bitfld.long 0x00 16.--19. "TM_MM,Trace Model (Memory-Mapped) Support" "Reserved,Supported,?..." newline bitfld.long 0x00 12.--15. "CTM_CB,Coprocessor-Based Trace Debug Model Support" "Not supported,?..." bitfld.long 0x00 4.--7. "SDM_CB,Secure Debug Model (Coprocessor) Support" "Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Support v8.2,?..." newline bitfld.long 0x00 0.--3. "CDM_CB,Coprocessor Debug Model Support" "Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Support v8.2,?..." rgroup.long c15:0x0000++0x00 line.long 0x00 "MIDR,Main ID Register" hexmask.long.byte 0x0 24.--31. 1. "IMPL,Implementer code" bitfld.long 0x00 20.--23. "VAR,Variant" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 16.--19. "ARCH, Architecture" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,CPUID scheme" newline hexmask.long.word 0x00 4.--15. 1. "PART,Primary Part Number" bitfld.long 0x00 0.--3. "REV,Revision Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rgroup.long c15:0x0200++0x00 line.long 0x00 "TCMTR,TCM Type Register" rgroup.long c15:0x0300++0x00 line.long 0x00 "TLBTR,TLB Type Register" bitfld.long 0x00 0. "NU,Not Unified TLB" "Unified TLB,Separate Instruction and Data TLBs" rgroup.long c15:0x0500++0x00 line.long 0x00 "MPIDR,Multiprocessor Affinity Register" bitfld.long 0x00 30. "U,Processor is part of a multiprocessor or uniprocessor system" "Multiprocessor,?..." bitfld.long 0x00 24. "MT,Lowest level of affinity consist of logical processors" "Not implemented,Implemented" newline hexmask.long.byte 0x00 16.--23. 1. "AFF2,Affinity level 2. Identifies different clusters within the system" bitfld.long 0x00 8.--15. "AFF1,Affinity level 1. Identifies individual cores within the local FCM cluster" "CORE0,CORE1,CORE2,CORE3,CORE4,CORE5,CORE6,CORE7,?..." hexmask.long.byte 0x00 0.--7. 1. "AFF0,Affinity level 0. Identifies individual threads within a multi-threaded core" rgroup.long c15:0x0600++0x00 line.long 0x00 "REVIDR,Revision ID Register" rgroup.long c15:0x1700++0x00 line.long 0x00 "AIDR,Auxiliary ID Register" tree.end tree "System Control and Configuration" group.long c15:0x0001++0x00 line.long 0x0 "SCTLR,Control Register" bitfld.long 0x00 30. "TE,T32 exception enable" "A32,T32" bitfld.long 0x00 29. "AFE,Access Flag Enable" "Disabled,Enabled" newline bitfld.long 0x00 28. "TRE,TEX remap enable" "Disabled,Enabled" bitfld.long 0x00 25. "EE,Exception endianness" "Little,Big" newline bitfld.long 0x00 23. "SPAN,Set Privileged Access Never" "Disabled,Enabled" bitfld.long 0x00 20. "UWXN,Unprivileged write permission implies PL1 Execute Never" "Not forced,Forced" newline bitfld.long 0x00 19. "WXN,Write permission implies PL1 Execute Never" "Not forced,Forced" bitfld.long 0x00 18. "NTWE,Not trap WFE" "No,Yes" newline bitfld.long 0x00 16. "NTWI,Not trap WFI" "No,Yes" bitfld.long 0x00 13. "V,Base Location of Exception Registers" "VBAR value,0xFFFF0000" newline bitfld.long 0x00 12. "I,Instruction Cache Enable" "Disabled,Enabled" bitfld.long 0x00 8. "SED,SETEND Disable" "No,Yes" newline bitfld.long 0x00 5. "CP15BEN,C15 Barrier Enable" "Disabled,Enabled" bitfld.long 0x00 4. "LSMAOE,Load/Store Multiple Atomicity and Ordering Enable" "Reserved,Enabled" newline bitfld.long 0x00 3. "NTLSMD,No Trap Load/Store Multiple to Device-nGRE/Device-nGnRE/Device-nGnRnE memory" "Reserved,No Trap" bitfld.long 0x00 2. "C,Enable unified cache or data cache" "Disabled,Enabled" newline bitfld.long 0x00 1. "A,Strict Alignment" "Disabled,Enabled" bitfld.long 0x00 0. "M,MMU or Protection Unit" "Disabled,Enabled" rgroup.quad c15:0x100F0++0x01 line.quad 0x00 "CPUACTLR,CPU Auxiliary Control Register" if corename()=="CORTEXA75" rgroup.quad c15:0x10F11++0x01 line.quad 0x00 "CPUACTLR2,CPU Auxiliary Control Register 2" endif if corename()=="CORTEXA75" group.quad c15:0x140F0++0x01 line.quad 0x00 "CPUECTLR,CPU Extended Control Register" bitfld.quad 0x00 22.--23. "L4_STREAM,Threshold for direct stream to L4 cache on store" "512KB,1024KB,2048KB,Disabled" bitfld.quad 0x00 20.--21. "L3_STREAM,Threshold for direct stream to L3 cache on store" "64KB,256KB,512KB,Disabled" newline bitfld.quad 0x00 18.--19. "L2_STREAM,Threshold for direct stream to L2 cache on store" "16KB,64KB,128KB,Disabled" bitfld.quad 0x00 10. "L3PF,Enable L3 prefetch requests sent by the stride prefetcher" "Disabled,Enabled" newline bitfld.quad 0x00 9. "L2PF,Enable L2 prefetch requests sent by the stride prefetcher" "Disabled,Enabled" bitfld.quad 0x00 8. "L1PF,Enable L1 prefetch requests sent by the stride prefetcher" "Disabled,Enabled" newline bitfld.quad 0x00 7. "RPF,Enable L2 region prefetch requests" "Disabled,Enabled" bitfld.quad 0x00 6. "MMUPF,Enable MMU prefetch requests" "Disabled,Enabled" newline bitfld.quad 0x00 5. "RPF_AGGRO,L2 region prefetcher aggressivity" "Longer,Shorter" bitfld.quad 0x00 1. "RNSD_EXCL,Enables signaling of cacheable Exclusive loads on the internal interface between the core and the DSU" "Not use,Use" newline bitfld.quad 0x00 0. "EXTLLC,Type of last-level cache that is present in the system" "Internal,External" elif corename()=="CORTEXA55" group.quad c15:0x140F0++0x01 line.quad 0x00 "CPUECTLR,CPU Extended Control Register" bitfld.quad 0x00 38.--39. "ATOM,Force most cacheable atomic instructions to be executed far in the L3 cache or beyond and near in the L1 cache" "Near - hit/unique | Far - miss/shared,Near,Far,Near - load | Far - store" bitfld.quad 0x00 37. "L2FLUSH,L2 cache flush" "Enabled,Disabled" newline bitfld.quad 0x00 29.--30. "L3WSCTL,Write streaming no-L3-allocate threshold" "128th line,1024th line,4096th line,Disabled" bitfld.quad 0x00 27.--28. "L2WSCTL,Write streaming no-L2-allocate threshold" "16th line,128th line,512th line,Disabled" newline bitfld.quad 0x00 25.--26. "L1WSCTL,Write streaming no-L1-allocate threshold" "4th line,64th line,128th line,Disabled" bitfld.quad 0x00 13.--15. "L1PCTL,L1 Data prefetch control. Maximum number of outstanding data prefetches allowed in the L1 memory system" "Prefetch disabled,1,2,3,4,5,6,7" newline bitfld.quad 0x00 10.--12. "L3PCTL,L3 Data prefetch control. Maximum number of outstanding data prefetches allowed that can be sent to the L3 memory system" "16 lines,32 lines,Reserved,Reserved,Disabled,2 lines,4 lines,8 lines" bitfld.quad 0x00 0. "EXTLLC,Type of last-level cache that is present in the system" "Internal,External" endif rgroup.long c15:0x608F++0x00 line.long 0x00 "CPUPSELR,CPU Private Selection Register" rgroup.quad c15:0x618F++0x01 line.quad 0x00 "CPUPCR,CPU Private Control Register" rgroup.quad c15:0x638F++0x01 line.quad 0x00 "CPUPMR,CPU Private Mask Register" rgroup.quad c15:0x628F++0x01 line.quad 0x00 "CPUPOR,CPU Private Operation Register" group.long c15:0x0101++0x00 line.long 0x00 "ACTLR,Auxiliary Control Register" bitfld.long 0x00 12. "CLUSTERPMUEN,Performance Management Registers access control" "Not accessible,Accessible" bitfld.long 0x00 11. "SMEN,Scheme Management Registers access control" "Not accessible,Accessible" newline bitfld.long 0x00 10. "TSIDEN,Thread Scheme ID Register enable" "Not accessible,Accessible" bitfld.long 0x00 7. "PWREN,Power Control Registers access control" "Not accessible,Accessible" newline bitfld.long 0x00 5. "ERXPFGEN,Error Record Registers access control" "Not accessible,Accessible" bitfld.long 0x00 1. "ECTLREN, Extended Control Registers access control" "Not accessible,Accessible" newline bitfld.long 0x00 0. "ACTLREN,Auxiliary Control Registers access control" "Not accessible,Accessible" rgroup.long c15:0x0301++0x00 line.long 0x00 "ACTLR2,Auxiliary Control Register 2" group.long c15:0x0201++0x00 line.long 0x00 "CPACR,Coprocessor Access Control Register 1" bitfld.long 0x00 31. "ASEDIS,Disable Advanced SIMD Extension functionality" "No,Yes" bitfld.long 0x00 22.--23. "CP11,Coprocessor access control" "Denied,Privileged,Reserved,Full" newline bitfld.long 0x00 20.--21. "CP10,Coprocessor access control" "Denied,Privileged,Reserved,Full" group.long c15:0x0011++0x00 line.long 0x00 "SCR,Secure Configuration Register" bitfld.long 0x00 13. "TWE,Traps WFE instructions to Monitor mode" "No trap,Trap" bitfld.long 0x00 12. "TWI,Traps WFI instructions to Monitor mode" "No trap,Trap" newline bitfld.long 0x00 9. "SIF,Secure Instruction Fetch" "Permitted,Not permitted" bitfld.long 0x00 8. "HCE,Hypervisor Call instruction enable" "No,Yes" newline bitfld.long 0x00 7. "SCD,Secure Monitor Call disable" "No,Yes" bitfld.long 0x00 6. "NET,Disables early termination" "Enabled,Disabled" newline bitfld.long 0x00 5. "AW,Controls whether the Non-secure world can modify the A-bit in the CPSR" "Not allowed,Allowed" bitfld.long 0x00 4. "FW,Controls whether the Non-secure world can modify the F-bit in the CPSR" "Not allowed,Allowed" newline bitfld.long 0x00 3. "EA,External Abort exceptions handled in Abort mode or Monitor mode" "Abort,Monitor" bitfld.long 0x00 2. "FIQ,FIQ exceptions handled in Abort mode or Monitor mode" "FIQ,Monitor" newline bitfld.long 0x00 1. "IRQ,IRQ exceptions handled in Abort mode or Monitor mode" "IRQ,Monitor" bitfld.long 0x00 0. "NS,Secure mode " "Secure,Non-secure" group.long c15:0x0111++0x00 line.long 0x00 "SDER,Secure Debug Enable Register" bitfld.long 0x00 1. "SUNIDEN,Secure User Non-Invasive Debug Enable" "Disabled,Enabled" bitfld.long 0x00 0. "SUIDEN,Secure User Invasive Debug Enable" "Disabled,Enabled" group.long c15:0x0131++0x00 line.long 0x00 "SDCR,Secure Debug Control Register" bitfld.long 0x00 21. "EPMAD,External debugger access to Performance Monitors Registers disabled" "No,Yes" bitfld.long 0x00 20. "EDAD,External debugger access to breakpoint and watchpoint Registers disabled" "No,Yes" newline bitfld.long 0x00 17. "SPME,Secure performance monitors enable" "Disabled,Enabled" bitfld.long 0x00 14.--15. "SPD,AArch32 secure privileged debug" "Legacy,Reserved,Disabled,Enabled" group.long c15:0x0211++0x00 line.long 0x00 "NSACR,Non-Secure Access Control Register" bitfld.long 0x00 15. "NSASEDIS,Disable Non-secure Advanced SIMD Extension functionality" "No,Yes" bitfld.long 0x00 11. "CP11,Coprocessor 11 in the Non-secure World Access Permission" "Denied,Permitted" newline bitfld.long 0x00 10. "CP10,Coprocessor 10 in the Non-secure World Access Permission" "Denied,Permitted" group.long c15:0x000C++0x00 line.long 0x00 "VBAR,Vector Base Address Register" hexmask.long 0x00 5.--31. 0x20 "VBA,Vector Base Address" group.long c15:0x010C++0x00 line.long 0x00 "MVBAR,Monitor Vector Base Address Register" hexmask.long 0x00 5.--31. 0x20 "MVBADDR,Monitor Vector Base Address" rgroup.long c15:0x001C++0x00 line.long 0x00 "ISR,Interrupt Status Register" bitfld.long 0x00 8. "A,Asynchronous external abort pending bit" "Not pending,Pending" bitfld.long 0x00 7. "I,IRQ pending bit" "Not pending,Pending" newline bitfld.long 0x00 6. "F,FIQ pending bit" "Not pending,Pending" group.long c15:0x020C++0x00 line.long 0x00 "RMR,Reset Management Register" bitfld.long 0x00 1. "RR,Reset Request" "Not requested,Requested" bitfld.long 0x00 0. "AA64,Determines which execution state the processor boots into after a warm reset" "AArch32,AArch64" if corename()=="CORTEXA75" rgroup.long c15:0x010C++0x00 line.long 0x00 "RVBAR,Reset Vector Base Address Register" hexmask.long 0x00 2.--31. 0x4 "RA,Reset Address" endif rgroup.long c15:0x0015++0x00 line.long 0x00 "ADFSR,Auxiliary Data Fault Status Register" rgroup.long c15:0x0115++0x00 line.long 0x00 "AIFSR,Auxiliary Instruction Fault Status Register" if corename()=="CORTEXA75" if (((per.l(c15:0x0202))&0x80000000)==0x00000000) group.long c15:0x0005++0x00 line.long 0x00 "DFSR,Data Fault Status Register" bitfld.long 0x00 16. "FNV,FAR not Valid" "Valid,Not valid" bitfld.long 0x00 14.--15. "AET,Asynchronous Error Type" "Uncorrected/Unrecoverable,?..." newline bitfld.long 0x00 13. "CM,Cache maintenance fault" "No fault,Fault" bitfld.long 0x00 11. "WNR,Access Caused an Abort Type" "Read,Write" newline bitfld.long 0x00 9. "LPAE,Descriptor translation table format" "Short,Long" bitfld.long 0x00 4.--7. "DOMAIN,Domain Accessed When a Data Fault Occurs" "D0,D1,D2,D3,D4,D5,D6,D7,D8,D9,D10,D11,D12,D13,D14,D15" newline bitfld.long 0x00 0.--3. 10. "FS,Generated Exception Type" "Reserved,Alignment,Debug,Access flag/L1,Instruction,Translation/L1,Access flag/L2,Translation/L1,Sync. external,Domain/L1,Reserved,Domain/L2,Sync. external/on TTW/L1,Permission/L1,Sync. external/on TTW/L2,Permission/L2,TLB conflict,Reserved,Reserved,Reserved,Lockdown,Unsupp exclusive access,SError,Reserved,SError/ECC on memory access,Sync. parity/ECC on memory access,Reserved,Reserved,Sync. parity/ECC on TTW/L1,Reserved,Sync. parity/ECC on TTW/L2,?..." group.long c15:0x0105++0x00 line.long 0x00 "IFSR,Instruction Fault Status Register" bitfld.long 0x00 16. "FNV,FAR not Valid" "Valid,Not valid" bitfld.long 0x00 12. "EXT,External Abort Qualifier" "0,1" newline bitfld.long 0x00 9. "LPAE,Descriptor translation table format" "Short,Long" bitfld.long 0x00 0.--3. 10. "FS,Fault status bits" "Reserved,Alignment,Debug,Access flag/L1,Reserved,Translation/L1,Access flag/L2,Translation/L2,Sync. external,Domain/L1,Reserved,Domain/L2,Sync. external/on TTW/L1,Permission/L1,Sync. external/on TTW/L2,Permission/L2,TLB conflict,Reserved,Reserved,Reserved,Lockdown,Reserved,Reserved,Reserved,Reserved,Sync. parity/ECC on memory access,Reserved,Reserved,Sync. parity/ECC on TTW/L1,Reserved,Sync. parity/ECC on TTW/L2,?..." else group.long c15:0x0005++0x00 line.long 0x00 "DFSR,Data Fault Status Register" bitfld.long 0x00 16. "FNV,FAR not Valid" "Valid,Not valid" bitfld.long 0x00 14.--15. "AET,Asynchronous Error Type" "Uncorrected/Unrecoverable,?..." newline bitfld.long 0x00 13. "CM,Cache maintenance fault" "No fault,Fault" bitfld.long 0x00 11. "WNR,Access Caused an Abort Type" "Read,Write" newline bitfld.long 0x00 9. "LPAE,Descriptor translation table format" "Short,Long" bitfld.long 0x00 0.--5. "STATUS,Fault status bits" "Address size/TTBR0/TTBR1,Address size/L1,Address size/L2,Address size/L3,Reserved,Translation/L1,Translation/L2,Translation/L3,Reserved,Access flag/L1,Access flag/L2,Access flag/L3,Reserved,Permission/L1,Permission/L2,Permission/L3,Sync. external,Async. SError,Reserved,Reserved,Reserved,Sync. external/on TTW/L1,Sync. external/on TTW/L2,Sync. external/on TTW/L3,Sync. parity/ECC on memory access,Reserved,Reserved,Reserved,Reserved,Sync. parity/ECC on TTW/L1,Sync. parity error/ECC on TTW/L2,Sync. parity error/ECC on TTW/L3,Reserved,Alignment,Debug,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,TLB conflict,Reserved,Reserved,Reserved,Lockdown,Unsupp exclusive access,?..." group.long c15:0x0105++0x00 line.long 0x00 "IFSR,Instruction Fault Status Register" bitfld.long 0x00 16. "FNV,FAR not Valid" "Valid,Not valid" bitfld.long 0x00 12. "EXT,External Abort Qualifier" "0,1" newline bitfld.long 0x00 9. "LPAE,Descriptor translation table format" "Short,Long" bitfld.long 0x00 0.--5. "STATUS,Fault status bits" "Address size/TTBR0/TTBR1,Address size/L1,Address size/L2,Address size/L3,Reserved,Translation/L1,Translation/L2,Translation/L3,Reserved,Access flag/L1,Access flag/L2,Access flag/L3,Reserved,Permission/L1,Permission/L2,Permission/L3,Sync. external,Reserved,Reserved,Reserved,Reserved,Sync. external/on TTW/L1,Sync. external/on TTW/L2,Sync. external/on TTW/L3,Sync. parity/ECC on memory access,Reserved,Reserved,Reserved,Reserved,Sync. parity/ECC on TTW/L1,Sync. parity/ECC on TTW/L2,Sync. parity/ECC on TTW/L3,Reserved,Alignment,Debug,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,TLB conflict,?..." endif elif corename()=="CORTEXA55" if (((per.l(c15:0x0202))&0x80000000)==0x00000000) group.long c15:0x0005++0x00 line.long 0x00 "DFSR,Data Fault Status Register" bitfld.long 0x00 16. "FNV,FAR not Valid" "Valid,Not valid" bitfld.long 0x00 14.--15. "AET,Asynchronous Error Type" ",Uncorrected/Unrecoverable,?..." newline bitfld.long 0x00 13. "CM,Cache maintenance fault" "No fault,Fault" bitfld.long 0x00 11. "WNR,Access Caused an Abort Type" "Read,Write" newline bitfld.long 0x00 9. "LPAE,Descriptor translation table format" "Short,Long" bitfld.long 0x00 4.--7. "DOMAIN,Domain Accessed When a Data Fault Occurs" "D0,D1,D2,D3,D4,D5,D6,D7,D8,D9,D10,D11,D12,D13,D14,D15" newline bitfld.long 0x00 0.--3. 10. "FS,Fault status bits" "Reserved,Alignment,Debug,Access flag/L1,Reserved,Translation/L1,Access flag/L2,Translation/L2,Sync. external,Domain/L1,Reserved,Domain/L2,Sync. external/on TTW/L1,Permission/L1,Sync. external/on TTW/L2,Permission/L2,TLB conflict,Reserved,Reserved,Reserved,Lockdown,Reserved,Reserved,Reserved,Reserved,Sync. parity/ECC on memory access,Reserved,Reserved,Sync. parity/ECC on TTW/L1,Reserved,Sync. parity/ECC on TTW/L2,?..." group.long c15:0x0105++0x00 line.long 0x00 "IFSR,Instruction Fault Status Register" bitfld.long 0x00 16. "FNV,FAR not Valid" "Valid,Not valid" bitfld.long 0x00 12. "EXT,External Abort Qualifier" "0,1" newline bitfld.long 0x00 9. "LPAE,Descriptor translation table format" "Short,Long" bitfld.long 0x00 0.--3. 10. "FS,Fault Status" "Reserved,Reserved,Debug event,Access flag/section,Reserved,Translation/section,Access flag/page,Translation/page,Sync. external/non-translation,Domain/section,Reserved,Domain/page,Sync. external/on TTW/L1,Permission/section,Sync. external/on TTW/L2,Permission/page,TLB conflict,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Sync. parity/on memory access,Reserved,Reserved,Sync. parity/on TTW/L1,Reserved,Sync. parity/on TTW/L2,?..." else group.long c15:0x0005++0x00 line.long 0x00 "DFSR,Data Fault Status Register" bitfld.long 0x00 16. "FNV,FAR not Valid" "Valid,Not valid" bitfld.long 0x00 14.--15. "AET,Asynchronous Error Type" ",Uncorrected/Unrecoverable,?..." newline bitfld.long 0x00 13. "CM,Cache maintenance fault" "No fault,Fault" bitfld.long 0x00 11. "WNR,Access Caused an Abort Type" "Read,Write" newline bitfld.long 0x00 9. "LPAE,Descriptor translation table format" "Short,Long" bitfld.long 0x00 0.--5. "STATUS,Fault status bits" "Address size/TTBR0/TTBR1,Address size/L1,Address size/L2,Address size/L3,Reserved,Translation/L1,Translation/L2,Translation/L3,Reserved,Access flag/L1,Access flag/L2,Access flag/L3,Reserved,Permission/L1,Permission/L2,Permission/L3,Sync. external,Async. SError,Reserved,Reserved,Reserved,Sync. external/on TTW/L1,Sync. external/on TTW/L2,Sync. external/on TTW/L3,Sync. parity/ECC on memory access,Reserved,Reserved,Reserved,Reserved,Sync. parity/ECC on TTW/L1,Sync. parity error/ECC on TTW/L2,Sync. parity error/ECC on TTW/L3,Reserved,Alignment,Debug,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,TLB conflict,Reserved,Reserved,Reserved,Lockdown,Unsupp exclusive access,?..." group.long c15:0x0105++0x00 line.long 0x00 "IFSR,Instruction Fault Status Register" bitfld.long 0x00 16. "FNV,FAR not Valid" "Valid,Not valid" bitfld.long 0x00 12. "EXT,External Abort Qualifier" "0,1" newline bitfld.long 0x00 9. "LPAE,Descriptor translation table format" "Short,Long" bitfld.long 0x00 0.--5. "STATUS,Fault status bits" "Address size/TTBR0/TTBR1,Address size/L1,Address size/L2,Address size/L3,Reserved,Translation/L1,Translation/L2,Translation/L3,Reserved,Access flag/L1,Access flag/L2,Access flag/L3,Reserved,Permission/L1,Permission/L2,Permission/L3,Sync. external,Reserved,Reserved,Reserved,Reserved,Sync. external/on TTW/L1,Sync. external/on TTW/L2,Sync. external/on TTW/L3,Sync. parity/ECC on memory access,Reserved,Reserved,Reserved,Reserved,Sync. parity/ECC on TTW/L1,Sync. parity/ECC on TTW/L2,Sync. parity/ECC on TTW/L3,Reserved,Alignment,Debug,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,TLB conflict,?..." endif endif group.long c15:0x0006++0x00 line.long 0x00 "DFAR,Data Fault Address Register" group.long c15:0x0206++0x00 line.long 0x00 "IFAR,Instruction Fault Address Register" rgroup.long c15:0x000D++0x00 line.long 0x00 "FCSEIDR,FCSE PID Register" group.long c15:0x020D++0x00 line.long 0x00 "TPIDRURW,PL0 Read/Write Software Thread ID Register" group.long c15:0x030D++0x00 line.long 0x00 "TPIDRURO,PL0 Read-Only Software Thread ID Register" group.long c15:0x040D++0x00 line.long 0x00 "TPIDRPRW,PL1 Software Thread ID Register" if corename()=="CORTEXA75" if (((per.l(c15:0x0202))&0x80000000)==0x00000000) group.long c15:0x011C++0x00 line.long 0x00 "DISR,Deferred Interrupt Status Register" bitfld.long 0x00 31. "A,Asynchronous SError interrupt deferred" "No,Yes" bitfld.long 0x00 14.--15. "AET,Asynchronous Error Type" "UC/Uncontainable,?..." newline bitfld.long 0x00 9. "LPAE,Format" "Short-descriptor,Long-descriptor" bitfld.long 0x00 0.--3. 10. "FS,Fault Status Code" "Reserved,Alignment,Debug,Access/L1,Instruction,Translation/L1,Access/L2,Translation/L2,Non-translation/sync. external,Domain/L1,Reserved,Domain/L2,L1/external,Permission/L1,L2/external,Permission/L2,TLB conflict,Reserved,Reserved,Reserved,Lockdown,Unsupp exclusive access,SError interrupt,Reserved,SError interrupt parity/ECC on memory access,Sync. parity/ECC on memory access,Reserved,Reserved,Sync. parity/ECC on TTW/L1,Reserved,Sync. parity/ECC on TTW/L2,?..." else group.long c15:0x011C++0x00 line.long 0x00 "DISR,Deferred Interrupt Status Register" bitfld.long 0x00 31. "A,Asynchronous SError interrupt deferred" "No,Yes" bitfld.long 0x00 14.--15. "AET,Asynchronous Error Type" "UC/Uncontainable,?..." newline bitfld.long 0x00 9. "LPAE,Format" "Short-descriptor,Long-descriptor" bitfld.long 0x00 0.--5. "STATUS,Fault Status Code" "Address size/TTBR0/TTBR1,Address size/L1,Address size/L2,Address size/L3,Reserved,Translation/L1,Translation/L2,Translation/L3,Reserved,Access flag/L1,Access flag/L2,Access flag/L3,Reserved,Permission/L1,Permission/L2,Permission/L3,Sync. external,SError interrupt,Reserved,Reserved,Reserved,Sync. external/on TTW/L1,Sync. external/on TTW/L2,Sync. external/on TTW/L3,Sync. parity/on memory access,SError interrupt/a parity or ECC/on memory access,Reserved,Reserved,Reserved,Sync. parity/on memory access/on TTW/L1,Sync. parity/on memory access/on TTW/L2,Sync. parity/on memory access/on TTW/L3,Reserved,Alignment,Debug event,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Lockdown,Unsupp exclusive access,?..." endif elif corename()=="CORTEXA55" if (((per.l(c15:0x0202))&0x80000000)==0x00000000) group.long c15:0x011C++0x00 line.long 0x00 "DISR,Deferred Interrupt Status Register" bitfld.long 0x00 31. "A,Asynchronous SError interrupt deferred" "No,Yes" bitfld.long 0x00 14.--15. "AET,Asynchronous Error Type" "Reserved,UEU/Unrecoverable,?..." newline bitfld.long 0x00 9. "LPAE,Format" "Short-descriptor,Long-descriptor" bitfld.long 0x00 0.--3. 10. "FS,Fault Status Code" "Reserved,Alignment,Debug,Access/L1,Instruction,Translation/L1,Access/L2,Translation/L2,Non-translation/sync. external,Domain/L1,Reserved,Domain/L2,L1/external,Permission/L1,L2/external,Permission/L2,TLB conflict,Reserved,Reserved,Reserved,Lockdown,Unsupp exclusive access,SError interrupt,Reserved,SError interrupt parity/ECC on memory access,Sync. parity/ECC on memory access,Reserved,Reserved,Sync. parity/ECC on TTW/L1,Reserved,Sync. parity/ECC on TTW/L2,?..." else group.long c15:0x011C++0x00 line.long 0x00 "DISR,Deferred Interrupt Status Register" bitfld.long 0x00 31. "A,Asynchronous SError interrupt deferred" "No,Yes" bitfld.long 0x00 14.--15. "AET,Asynchronous Error Type" "Reserved,UEU/Unrecoverable,?..." newline bitfld.long 0x00 9. "LPAE,Format" "Short-descriptor,Long-descriptor" bitfld.long 0x00 0.--5. "STATUS,Fault Status Code" "Address size/TTBR0/TTBR1,Address size/L1,Address size/L2,Address size/L3,Reserved,Translation/L1,Translation fault/L2,Translation fault/L3,Reserved,Access flag fault/L1,Access flag fault/L2,Access flag fault/L3,Reserved,Permission fault/L1,Permission fault/L2,Permission fault/L3,Sync. external,SError interrupt,Reserved,Reserved,Reserved,Sync. external/on TTW/L1,Sync. external/on TTW/L2,Sync. external/on TTW/L3,Sync. parity/on memory access,SError interrupt/parity or ECC/on memory access,Reserved,Reserved,Reserved,Sync. parity/on memory access/on TTW/L1,Sync. parity/on memory access/on TTW/L2,Sync. parity/on memory access/on TTW/L3,Reserved,Alignment,Debug event,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Lockdown,Unsupp exclusive access,?..." endif endif if corename()=="CORTEXA75" if (((per.l(c15:0x0202))&0x80000000)==0x00000000) group.long c15:0x411C++0x00 line.long 0x00 "VDISR,Virtual Deferred Interrupt Status Register" bitfld.long 0x00 31. "A,Asynchronous SError interrupt deferred" "No,Yes" bitfld.long 0x00 14.--15. "AET,Asynchronous Error Type" "UC/Uncontainable,?..." newline bitfld.long 0x00 9. "LPAE,Format" "Short-descriptor,Long-descriptor" bitfld.long 0x00 0.--3. 10. "FS,Fault Status Code" "Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Async SError interrupt,?..." else group.long c15:0x411C++0x00 line.long 0x00 "VDISR,Virtual Deferred Interrupt Status Register" bitfld.long 0x00 31. "A,Asynchronous SError interrupt deferred" "No,Yes" bitfld.long 0x00 14.--15. "AET,Asynchronous Error Type" "UC/Uncontainable,?..." newline bitfld.long 0x00 9. "LPAE,Format" "Short-descriptor,Long-descriptor" bitfld.long 0x00 0.--5. "STATUS,Fault Status Code" "Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Async SError interrupt,?..." endif elif corename()=="CORTEXA55" if (((per.l(c15:0x0202))&0x80000000)==0x00000000) group.long c15:0x411C++0x00 line.long 0x00 "VDISR,Virtual Deferred Interrupt Status Register" bitfld.long 0x00 31. "A,Asynchronous SError interrupt deferred" "No,Yes" bitfld.long 0x00 14.--15. "AET,Asynchronous Error Type" "Reserved,UEU/Unrecoverable,?..." newline bitfld.long 0x00 9. "LPAE,Format" "Short-descriptor,?..." bitfld.long 0x00 0.--3. 10. "FS,Fault Status Code" "Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Async SError interrupt,?..." else group.long c15:0x411C++0x00 line.long 0x00 "VDISR,Virtual Deferred Interrupt Status Register" bitfld.long 0x00 31. "A,Asynchronous SError interrupt deferred" "No,Yes" bitfld.long 0x00 14.--15. "AET,Asynchronous Error Type" "Reserved,UEU/Unrecoverable,?..." newline bitfld.long 0x00 9. "LPAE,Format" ",Long-descriptor" bitfld.long 0x00 0.--5. "STATUS,Fault Status Code" "Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Async SError interrupt,?..." endif endif group.long c15:0x4325++0x00 line.long 0x00 "VDFSR,Virtual SError Exception Syndrome Register" bitfld.long 0x00 14.--15. "AET,Asynchronous Error Type" "Reserved,UEU/Unrecoverable,?..." tree "System Instructions" wgroup.long c15:0x0068++0x00 line.long 0x00 "DTLBIALL,DTLBIALL" wgroup.long c15:0x0268++0x00 line.long 0x00 "DTLBIASID,DTLBIASID" wgroup.long c15:0x0168++0x00 line.long 0x00 "DTLBIMVA,DTLBIMVA" wgroup.long c15:0x0058++0x00 line.long 0x00 "ITLBIALL,ITLBIALL" wgroup.long c15:0x0258++0x00 line.long 0x00 "ITLBIASID,ITLBIASID" wgroup.long c15:0x0158++0x00 line.long 0x00 "ITLBIMVA,ITLBIMVA" wgroup.long c15:0x05A7++0x00 line.long 0x00 "CP15DMB,CP15DMB" wgroup.long c15:0x04A7++0x00 line.long 0x00 "CP15DSB,CP15DSB" wgroup.long c15:0x0457++0x00 line.long 0x00 "CP15ISB,CP15ISB" wgroup.long c15:0x0657++0x00 line.long 0x00 "BPIALL,BPIALL" wgroup.long c15:0x0617++0x00 line.long 0x00 "BPIALLIS,BPIALLIS" wgroup.long c15:0x0757++0x00 line.long 0x00 "BPIMVA,BPIMVA" wgroup.long c15:0x0017++0x00 line.long 0x00 "ICIALLUIS,ICIALLUIS" wgroup.long c15:0x0057++0x00 line.long 0x00 "ICIALLU,ICIALLU" wgroup.long c15:0x0157++0x00 line.long 0x00 "ICIMVAU,ICIMVAU" wgroup.long c15:0x3147++0x00 line.long 0x00 "DCZVA,DCZVA" wgroup.long c15:0x0167++0x00 line.long 0x00 "DCIMVAC,DCIMVAC" wgroup.long c15:0x0267++0x00 line.long 0x00 "DCISW,DCISW" wgroup.long c15:0x01A7++0x00 line.long 0x00 "DCCMVAC,DCCMVAC" wgroup.long c15:0x02A7++0x00 line.long 0x00 "DCCSW,DCCSW" wgroup.long c15:0x01B7++0x00 line.long 0x00 "DCCMVAU,DCCMVAU" wgroup.long c15:0x01E7++0x00 line.long 0x00 "DCCIMVAC,DCCIMVAC" wgroup.long c15:0x02E7++0x00 line.long 0x00 "DCCISW,DCCISW" wgroup.long c15:0x0087++0x00 line.long 0x00 "ATS1CPR,ATS1CPR" wgroup.long c15:0x0097++0x00 line.long 0x00 "ATS1CPRP,ATS1CPRP" wgroup.long c15:0x0187++0x00 line.long 0x00 "ATS1CPW,ATS1CPW" wgroup.long c15:0x0197++0x00 line.long 0x00 "ATS1CPWP,ATS1CPWP" wgroup.long c15:0x0287++0x00 line.long 0x00 "ATS1CUR,ATS1CUR" wgroup.long c15:0x0387++0x00 line.long 0x00 "ATS1CUW,ATS1CUW" wgroup.long c15:0x0487++0x00 line.long 0x00 "ATS12NSOPR,ATS12NSOPR" wgroup.long c15:0x0587++0x00 line.long 0x00 "ATS12NSOPW,ATS12NSOPW" wgroup.long c15:0x0687++0x00 line.long 0x00 "ATS12NSOUR,ATS12NSOUR" wgroup.long c15:0x0787++0x00 line.long 0x00 "ATS12NSOUW,ATS12NSOUW" wgroup.long c15:0x4087++0x00 line.long 0x00 "ATS1HR,ATS1HR" wgroup.long c15:0x4187++0x00 line.long 0x00 "ATS1HW,ATS1HW" ; Commented Registers are not described in ARMv8 reference manual (DDI0407A) ; wgroup.long c15:0x6087++0x00 ; line.long 0x00 "ATS1E3R,ATS1E3R" ; wgroup.long c15:0x6187++0x00 ; line.long 0x00 "ATS1E3W,ATS1E3W" wgroup.long c15:0x0078++0x00 line.long 0x00 "TLBIALL,TLBIALL" wgroup.long c15:0x0178++0x00 line.long 0x00 "TLBIMVA,TLBIMVA" wgroup.long c15:0x4178++0x00 line.long 0x00 "TLBIMVAH,Invalidate Hypervisor unified TLB entry by MVA" wgroup.long c15:0x0278++0x00 line.long 0x00 "TLBIASID,TLBIASID" wgroup.long c15:0x0378++0x00 line.long 0x00 "TLBIMVAA,TLBIMVAA" wgroup.long c15:0x0578++0x00 line.long 0x00 "TLBIMVAL,TLBIMVAL" wgroup.long c15:0x0778++0x00 line.long 0x00 "TLBIMVAAL,TLBIMVAAL" wgroup.long c15:0x0038++0x00 line.long 0x00 "TLBIALLIS,TLBIALLIS" wgroup.long c15:0x0138++0x00 line.long 0x00 "TLBIMVAIS,TLBIMVAIS" wgroup.long c15:0x0238++0x00 line.long 0x00 "TLBIASIDIS,TLBIASIDIS" wgroup.long c15:0x0338++0x00 line.long 0x00 "TLBIMVAAIS,TLBIMVAAIS" wgroup.long c15:0x0538++0x00 line.long 0x00 "TLBIMVALIS,TLBIMVALIS" wgroup.long c15:0x0738++0x00 line.long 0x00 "TLBIMVAALI,TLBIMVAALI" wgroup.long c15:0x4108++0x00 line.long 0x00 "TLBIIPAS2IS,TLBIIPAS2IS" wgroup.long c15:0x4508++0x00 line.long 0x00 "TLBIIPAS2LIS,TLBIIPAS2LIS" wgroup.long c15:0x4148++0x00 line.long 0x00 "TLBIIPAS2,TLBIIPAS2" wgroup.long c15:0x4548++0x00 line.long 0x00 "TLBIIPAS2L,TLBIIPAS2L" wgroup.long c15:0x4178++0x00 line.long 0x00 "TLBIIPAS2L,TLBIIPAS2L" wgroup.long c15:0x4578++0x00 line.long 0x00 "TLBIMVALH,TLBIMVALH" ; wgroup.long c15:0x4678++0x00 ; line.long 0x00 "TLBIVMALLS12E1,TLBIVMALLS12E1" wgroup.long c15:0x4138++0x00 line.long 0x00 "TLBIMVAHIS,TLBIMVAHIS" wgroup.long c15:0x4538++0x00 line.long 0x00 "TLBIMVALHIS,TLBIMVALHIS" ; wgroup.long c15:0x4638++0x00 ; line.long 0x00 "TLBIVMALLS12E1IS,TLBIVMALLS12E1IS" ; wgroup.long c15:0x6178++0x00 ; line.long 0x00 "TLBIVAE3,TLBIVAE3" ; wgroup.long c15:0x6578++0x00 ; line.long 0x00 "TLBIVALE3,TLBIVALE3" ; wgroup.long c15:0x6138++0x00 ; line.long 0x00 "TLBIVAE3IS,TLBIVAE3IS" ; wgroup.long c15:0x6538++0x00 ; line.long 0x00 "TLBIVALE3IS,TLBIVALE3IS" wgroup.long c15:0x4078++0x00 line.long 0x00 "TLBIALLH,TLBIALLH" wgroup.long c15:0x4038++0x00 line.long 0x00 "TLBIALLHIS,TLBIALLHIS" wgroup.long c15:0x4478++0x00 line.long 0x00 "TLBIALLNSNH,TLBIALLNSNH" wgroup.long c15:0x4438++0x00 line.long 0x00 "TLBIALLNSNHIS,TLBIALLNSNHIS" ; wgroup.long c15:0x6078++0x00 ; line.long 0x00 "TLBIALLE3,TLBIALLE3" ; wgroup.long c15:0x6038++0x00 ; line.long 0x00 "TLBIALLE3IS,TLBIALLE3IS" tree.end tree.end tree "Memory Management Unit" group.long c15:0x0001++0x0 line.long 0x0 "SCTLR,Control Register" bitfld.long 0x00 30. "TE,T32 exception enable" "A32,T32" bitfld.long 0x00 29. "AFE,Access Flag Enable" "Disabled,Enabled" newline bitfld.long 0x00 28. "TRE,TEX remap enable" "Disabled,Enabled" bitfld.long 0x00 25. "EE,Exception endianness" "Little,Big" newline bitfld.long 0x00 23. "SPAN,Set Privileged Access Never" "Disabled,Enabled" bitfld.long 0x00 20. "UWXN,Unprivileged write permission implies PL1 Execute Never" "Not forced,Forced" newline bitfld.long 0x00 19. "WXN,Write permission implies PL1 Execute Never" "Not forced,Forced" bitfld.long 0x00 18. "NTWE,Not trap WFE" "No,Yes" newline bitfld.long 0x00 16. "NTWI,Not trap WFI" "No,Yes" bitfld.long 0x00 13. "V,Base Location of Exception Registers" "VBAR value,0xFFFF0000" newline bitfld.long 0x00 12. "I,Instruction Cache Enable" "Disabled,Enabled" bitfld.long 0x00 8. "SED,SETEND Disable" "No,Yes" newline bitfld.long 0x00 5. "CP15BEN,C15 Barrier Enable" "Disabled,Enabled" rbitfld.long 0x00 4. "LSMAOE,Load/Store Multiple Atomicity and Ordering Enable" "Reserved,Enabled" newline rbitfld.long 0x00 3. "NTLSMD,No Trap Load/Store Multiple to Device-nGRE/Device-nGnRE/Device-nGnRnE memory" "Reserved,No Trap" bitfld.long 0x00 2. "C,Enable unified cache or data cache" "Disabled,Enabled" newline bitfld.long 0x00 1. "A,Strict Alignment" "Disabled,Enabled" bitfld.long 0x00 0. "M,MMU or Protection Unit" "Disabled,Enabled" group.long c15:0x4001++0x0 line.long 0x00 "HSCTLR,Hypervisor System Control Register" bitfld.long 0x00 30. "TE,Thumb exception enable" "A32,T32" bitfld.long 0x00 25. "EE,Exception endianness" "Little,Big" newline bitfld.long 0x00 19. "WXN,Write permission implies XN" "Not forced,Forced" bitfld.long 0x00 12. "I,Instruction Cache Enable" "Disabled,Enabled" newline bitfld.long 0x00 8. "SED,SETEND Disable" "No,Yes" bitfld.long 0x00 7. "ITD,IT instruction functionality Disabled" "No,?..." newline bitfld.long 0x00 5. "CP15BEN,C15 Barrier Enable" "Disabled,Enabled" rbitfld.long 0x00 4. "LSMAOE,Load/Store Multiple Atomicity and Ordering Enable" "Reserved,Enabled" newline rbitfld.long 0x00 3. "NTLSMD,No Trap Load/Store Multiple to Device-nGRE/Device-nGnRE/Device-nGnRnE memory" "Trapped,No Trapped" bitfld.long 0x00 2. "C,Enable unified cache or data cache" "Disabled,Enabled" newline bitfld.long 0x00 1. "A,Strict Alignment" "Disabled,Enabled" bitfld.long 0x00 0. "M,Enable address translation" "Disabled,Enabled" if (((per.l(c15:0x0202))&0x80000000)==0x00000000) group.long c15:0x0002++0x00 line.long 0x00 "TTBR0,Translation Table Base Registers" hexmask.long 0x00 7.--31. 0x80 "TTB0,Translation table base address" bitfld.long 0x00 6. 0. "IRGN,Inner region bits" "Non-cacheable,Write-Back Write-Allocate Cacheable,Write-Through Cacheable,Write-Back no Write-Allocate Cacheable" newline bitfld.long 0x00 5. "NOS,Not Outer Shareable bit" "Outer,Inner" bitfld.long 0x00 3.--4. "RGN,RGN" "Non-cacheable,Write-Back Write-Allocate Cacheable,Write-Through Cacheable,Write-Back no Write-Allocate Cacheable" newline bitfld.long 0x00 1. "S,Shareable bit" "Non-shareable,Shareable" group.long c15:0x0102++0x00 line.long 0x00 "TTBR1,Translation Table Base Registers" hexmask.long 0x00 7.--31. 0x80 "TTB1,Translation table base address" bitfld.long 0x00 6. 0. "IRGN,Inner region bits" "Non-cacheable,Write-Back Write-Allocate Cacheable,Write-Through Cacheable,Write-Back no Write-Allocate Cacheable" newline bitfld.long 0x00 5. "NOS,Not Outer Shareable bit" "Outer,Inner" bitfld.long 0x00 3.--4. "RGN,RGN" "Non-cacheable,Write-Back Write-Allocate Cacheable,Write-Through Cacheable,Write-Back no Write-Allocate Cacheable" newline bitfld.long 0x00 1. "S,Shareable" "Non-shareable,Shareable" group.long c15:0x0202++0x00 line.long 0x00 "TTBCR,Translation Table Base Control Register" bitfld.long 0x00 31. "EAE,Extended Address Enable" "32-bit,40-bit" bitfld.long 0x00 5. "PD1,Translation table walk disable for translations using TTBR1" "No,Yes" newline bitfld.long 0x00 4. "PD0,Translation table walk disable for translations using TTBR0" "No,Yes" bitfld.long 0x00 0.--2. "N,Width of the base address held in TTBR0" "0,1,2,3,4,5,6,7" else group.quad c15:0x10020++0x01 line.quad 0x00 "TTBR0,Translation Table Base Registers" hexmask.quad.byte 0x00 48.--55. 1. "ASID,ASID for the translation table base address" hexmask.quad 0x00 1.--47. 1. "BADDR,Translation table base address" newline bitfld.quad 0x00 0. "CNP,Common not Private" "Not supported,Supported" group.quad c15:0x11020++0x01 line.quad 0x00 "TTBR1,Translation Table Base Registers" hexmask.quad.byte 0x00 48.--55. 1. "ASID,ASID for the translation table base address" hexmask.quad 0x00 1.--47. 1. "BADDR,Translation table base address" newline bitfld.quad 0x00 0. "CNP,Common not Private" "Not supported,Supported" group.long c15:0x0202++0x00 line.long 0x00 "TTBCR,Translation Table Base Control Register" bitfld.long 0x00 31. "EAE,Extended Address Enable" "32-bit,40-bit" bitfld.long 0x00 28.--29. "SH1,Shareability attributes for the memory associated with the translation table walks using TTBR1" "Non-Shareable,Reserved,Outer Shareable,Inner Shareable" newline bitfld.long 0x00 26.--27. "ORGN1,Outer Cacheability attributes for the memory associated with the translation table walks using TTBR1" "Non-cacheable,Write-Back Write-Allocate Cacheable,Write-Through Cacheable,Write-Back no Write-Allocate Cacheable" bitfld.long 0x00 24.--25. "IRGN1,Inner Cacheability attributes for the memory associated with the translation table walks using TTBR1" "Non-cacheable,Write-Back Write-Allocate Cacheable,Write-Through Cacheable,Write-Back no Write-Allocate Cacheable" newline bitfld.long 0x00 23. "EPD1,Translation Walk Disable for TTBR1" "No,Yes" bitfld.long 0x00 22. "A1,Selects whether TTBR0 or TTBR1 defines the ASID" "TTBR0,TTBR1" newline bitfld.long 0x00 16.--18. "T1SZ,The Size offset of the TTBR1 addressed region" "0,1,2,3,4,5,6,7" bitfld.long 0x00 12.--13. "SH0,Shareability attributes for the memory associated with the translation table walks using TTBR0/HTTBR" "Non-Shareable,Reserved,Outer Shareable,Inner Shareable" newline bitfld.long 0x00 10.--11. "ORGN0,Outer Cacheability attributes for the memory associated with the translation table walks using TTBR0/HTTBR" "Non-cacheable,Write-Back Write-Allocate Cacheable,Write-Through Cacheable,Write-Back no Write-Allocate Cacheable" bitfld.long 0x00 8.--9. "IRGN0,Inner Cacheability attributes for the memory associated with the translation table walks using TTBR0/HTTBR" "Non-cacheable,Write-Back Write-Allocate Cacheable,Write-Through Cacheable,Write-Back no Write-Allocate Cacheable" newline bitfld.long 0x00 7. "EPD0,Translation Walk Disable for TTBR0 region" "No,Yes" bitfld.long 0x00 6. "T2E,TTBCR2 Enable" "Disabled,Enabled" newline bitfld.long 0x00 0.--2. "T0SZ,The Size offset of the TTBR0/HTTBR addressed region" "0,1,2,3,4,5,6,7" endif if corename()=="CORTEXA55" group.long c15:0x0302++0x00 line.long 0x00 "TTBCR2,Translation Table Base Control Register 2" bitfld.long 0x00 18. "HWU162,Hardware usage of bit[62] of the stage1 translation table block or level 3 entry for pages pointed to by TTBR1" "Not possible,Possible" bitfld.long 0x00 17. "HWU161,Hardware usage of bit[61] of the stage1 translation table block or level 3 entry for pages pointed to by TTBR1" "Not possible,Possible" newline bitfld.long 0x00 16. "HWU160,Hardware usage of bit[60] of the stage1 translation table block or level 3 entry for pages pointed to by TTBR1" "Not possible,Possible" bitfld.long 0x00 15. "HWU159,Hardware usage of bit[59] of the stage1 translation table block or level 3 entry for pages pointed to by TTBR1" "Not possible,Possible" newline bitfld.long 0x00 14. "HWU062,Hardware usage of bit[62] of the stage1 translation table block or level 3 entry for pages pointed to by TTBR0" "Not possible,Possible" bitfld.long 0x00 13. "HWU061,Hardware usage of bit[61] of the stage1 translation table block or level 3 entry for pages pointed to by TTBR0" "Not possible,Possible" newline bitfld.long 0x00 12. "HWU060,Hardware usage of bit[60] of the stage1 translation table block or level 3 entry for pages pointed to by TTBR0" "Not possible,Possible" bitfld.long 0x00 11. "HWU059,Hardware usage of bit[59] of the stage1 translation table block or level 3 entry for pages pointed to by TTBR0" "Not possible,Possible" newline bitfld.long 0x00 10. "HPD1,Hierarchical Permission Disable for the TTBR1 region" "No,Yes" bitfld.long 0x00 9. "HPD0,Hierarchical Permission Disable for the TTBR0 region" "No,Yes" group.long c15:0x007F++0x00 line.long 0x00 "ATTBCR,Auxiliary Translation Table Base Control Register" bitfld.long 0x00 13. "HWVAL160,Indicates the value of PBHA[1] on page table walks memory access targeting the base address defined by TTB1 if HWEN160 is set" "0,1" bitfld.long 0x00 12. "HWVAL159,Indicates the value of PBHA[0] on page table walks memory access targeting the base address defined by TTB1 if HWEN159 is set" "0,1" newline bitfld.long 0x00 9. "HWVAL060,Indicates the value of PBHA[1] on page table walks memory access targeting the base address defined by TTB0 if HWEN060 is set" "0,1" bitfld.long 0x00 8. "HWVAL059,Indicates the value of PBHA[1] on page table walks memory access targeting the base address defined by TTB0 if HWEN059 is set" "0,1" newline bitfld.long 0x00 5. "HWEN160,Enables PBHA[1] page table walks memory access targeting the base address defined by TTB1" "Disabled,Enabled" bitfld.long 0x00 4. "HWEN159,Enables PBHA[0] page table walks memory access targeting the base address defined by TTB1" "Disabled,Enabled" newline bitfld.long 0x00 1. "HWEN060,Enables PBHA[1] page table walks memory access targeting the base address defined by TTB0" "Disabled,Enabled" bitfld.long 0x00 0. "HWEN059,Enables PBHA[0] page table walks memory access targeting the base address defined by TTB0" "Disabled,Enabled" endif group.quad c15:0x14020++0x01 line.quad 0x00 "HTTBR,Hypervisor Translation Table Base Register" hexmask.quad 0x00 1.--47. 0x02 "BADDR,Translation table base address" bitfld.quad 0x00 0. "CNP,Common not Private" "Not supported,Supported" group.long c15:0x4202++0x00 line.long 0x00 "HTCR,Hypervisor Translation Control Register" bitfld.long 0x00 28. "HWU062,Hardware usage of bit[62] of the stage1 translation table block or level 3 entry for pages pointed to by TTBR0" "Not possible,Possible" bitfld.long 0x00 27. "HWU061,Hardware usage of bit[61] of the stage1 translation table block or level 3 entry for pages pointed to by TTBR0" "Not possible,Possible" newline bitfld.long 0x00 26. "HWU060,Hardware usage of bit[60] of the stage1 translation table block or level 3 entry for pages pointed to by TTBR0" "Not possible,Possible" bitfld.long 0x00 25. "HWU059,Hardware usage of bit[59] of the stage1 translation table block or level 3 entry for pages pointed to by TTBR0" "Not possible,Possible" newline bitfld.long 0x00 24. "HPD,Hierarchical Permission Disables" "No,Yes" bitfld.long 0x00 12.--13. "SH0,Shareability attribute" "Non-shareable,Reserved,Outer Shareable,Inner Shareable" newline bitfld.long 0x00 10.--11. "ORGN0,Outer cacheability attribute, Normal memory" "Non-cacheable,Write-Back Write-Allocate Cacheable,Write-Through Cacheable,Write-Back no Write-Allocate Cacheable" bitfld.long 0x00 8.--9. "IRGN0,Inner cacheability attribute, Normal memory" "Non-cacheable,Write-Back Write-Allocate Cacheable,Write-Through Cacheable,Write-Back no Write-Allocate Cacheable" newline bitfld.long 0x00 0.--2. "T0SZ,The size offset of the memory region addressed by HTTBR" "0,1,2,3,4,5,6,7" group.long c15:0x0003++0x00 line.long 0x00 "DACR,Domain Access Control Register" bitfld.long 0x0 30.--31. "D15,Domain Access 15" "Denied,Client,Reserved,Manager" bitfld.long 0x0 28.--29. "D14,Domain Access 14" "Denied,Client,Reserved,Manager" newline bitfld.long 0x0 26.--27. "D13,Domain Access 13" "Denied,Client,Reserved,Manager" bitfld.long 0x0 24.--25. "D12,Domain Access 12" "Denied,Client,Reserved,Manager" newline bitfld.long 0x0 22.--23. "D11,Domain Access 11" "Denied,Client,Reserved,Manager" bitfld.long 0x0 20.--21. "D10,Domain Access 10" "Denied,Client,Reserved,Manager" newline bitfld.long 0x0 18.--19. "D9,Domain Access 9" "Denied,Client,Reserved,Manager" bitfld.long 0x0 16.--17. "D8,Domain Access 8" "Denied,Client,Reserved,Manager" newline bitfld.long 0x0 14.--15. "D7,Domain Access 7" "Denied,Client,Reserved,Manager" bitfld.long 0x0 12.--13. "D6,Domain Access 6" "Denied,Client,Reserved,Manager" newline bitfld.long 0x0 10.--11. "D5,Domain Access 5" "Denied,Client,Reserved,Manager" bitfld.long 0x0 8.--9. "D4,Domain Access 4" "Denied,Client,Reserved,Manager" newline bitfld.long 0x0 6.--7. "D3,Domain Access 3" "Denied,Client,Reserved,Manager" bitfld.long 0x0 4.--5. "D2,Domain Access 2" "Denied,Client,Reserved,Manager" newline bitfld.long 0x0 2.--3. "D1,Domain Access 1" "Denied,Client,Reserved,Manager" bitfld.long 0x0 0.--1. "D0,Domain Access 0" "Denied,Client,Reserved,Manager" if corename()=="CORTEXA75" if ((((per.l(c15:0x0202))&0x80000000)==0x00000000)&&(((per.l(c15:0x0047))&0x1)==0x0)) group.long c15:0x0047++0x00 line.long 0x00 "PAR,Physical Address Register" hexmask.long.tbyte 0x00 12.--31. 0x10 "PA,Physical Address" bitfld.long 0x00 11. "LPAE,Descriptor translation table format" "Short,Long" newline bitfld.long 0x00 10. "NOS,Not Outer Shareable attribute for the region" "Outer,?..." bitfld.long 0x00 9. "NS,Non-secure" "No,Yes" newline bitfld.long 0x00 7. "SH,Shareability attribute for the region" "No,Yes" newline bitfld.long 0x00 4.--6. "INNER,Inner memory attributes for the region" "Non-cacheable,Device-nGnRnE,Reserved,Device-nGnRE,Reserved,Write-Back/Write-Allocate,Write-Through,Write-Back/No Write-Allocate" newline bitfld.long 0x00 2.--3. "OUTER,Outer memory attributes for the region" "Non-cacheable,Write-Back/Write-Allocate,Write-Through/No Write-Allocate,Write-Back/No Write-Allocate" newline bitfld.long 0x00 1. "SS,Used to indicate if the result is a Supersection" "No,Yes" newline bitfld.long 0x00 0. "F,Indicates whether the conversion completed successfully" "Successful,Aborted" elif ((((per.l(c15:0x0202))&0x80000000)==0x00000000)&&(((per.l(c15:0x0047))&0x1)==0x1)) group.long c15:0x0047++0x00 line.long 0x00 "PAR,Physical Address Register" bitfld.long 0x00 11. "LPAE,Descriptor translation table format" "Short,?..." newline newline newline bitfld.long 0x00 6. "FS[5],Fault status bit [5] - External abort type" "Internal,External" newline newline bitfld.long 0x00 1.--5. "FS[4:0],Fault status bit [4:0] - Abort source" "Reserved,Alignment,Debug,Access flag/L1,Instruction,Translation/L1,Access flag/L2,Translation/L2,Sync. external,Domain/L1,Reserved,Domain/L2,Sync. external/on TTW/L1,Permission/L1,Sync. external/on TTW/L2,Permission/L2,TLB conflict,Reserved,Reserved,Reserved,Lockdown,Unsupp. exclusive access,SError,Reserved,Reserved,Sync. parity/ECC on memory access,Reserved,Reserved,Sync. parity/ECC on TTW/L1,Reserved,Sync. parity/ECC on TTW/L2,?..." newline bitfld.long 0x00 0. "F,Indicates whether the conversion completed successfully" "Successful,Aborted" elif ((((per.l(c15:0x0202))&0x80000000)==0x80000000)&&(((per.l(c15:0x10070))&0x1)==0x0)) group.quad c15:0x10070++0x01 line.quad 0x00 "PAR,Physical Address Register" hexmask.quad.byte 0x00 56.--63. 1. "ATTR,Memory attributes for the returned PA" hexmask.quad.long 0x00 12.--39. 0x10 "PA,Physical Address" newline bitfld.quad 0x00 11. "LPAE,Descriptor translation table format" ",Long" newline bitfld.quad 0x00 9. "NS,Non-secure" "No,Yes" bitfld.quad 0x00 7.--8. "SH,Shareability attribute" "Non-shareable,Reserved,Outer Shareable,Inner Shareable" newline newline newline newline bitfld.quad 0x00 0. "F,Indicates whether the conversion completed successfully" "Successful,Aborted" else group.quad c15:0x10070++0x01 line.quad 0x00 "PAR,Physical Address Register" newline bitfld.quad 0x00 11. "LPAE,Descriptor translation table format" ",Long" newline bitfld.quad 0x00 9. "FSTAGE,Indicates the translation stage at which the translation aborted" "Stage 1,Stage 2" bitfld.quad 0x00 8. "S2WLK,Translation aborted because of a stage 2 fault during a stage 1 translation table walk" "No,Yes" newline newline newline bitfld.quad 0x00 1.--6. "FST,Fault Status Field" "Address size/TTBR,Address size/L1,Address size/L2,Address size/L3,Reserved,Translation/L1,Translation/L2,Translation/L3,Reserved,Access flag/L1,Access flag/L2,Access flag/L3,Reserved,Permission/L1,Permission/L2,Permission/L3,Sync. external,Reserved,Reserved,Reserved,Reserved,Sync. external/on TTW/L1,Sync. external/on TTW/L2,Sync. external/on TTW/L3,Sync. parity/ECC on memory access,Sync. parity/ECC on memory access,Reserved,Reserved,Reserved,Sync. parity/ECC on TTW/L1,Sync. parity/ECC on TTW/L2,Sync. parity/ECC/on TTW/L3,Reserved,Alignment,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,TLB conflict,?..." newline bitfld.quad 0x00 0. "F,Indicates whether the conversion completed successfully" "Successful,Aborted" endif elif corename()=="CORTEXA55" if ((((per.l(c15:0x0202))&0x80000000)==0x00000000)&&(((per.l(c15:0x0047))&0x1)==0x0)) group.long c15:0x0047++0x00 line.long 0x00 "PAR,Physical Address Register" hexmask.long.tbyte 0x00 12.--31. 0x10 "PA,Physical Address" newline bitfld.long 0x00 11. "LPAE,Descriptor translation table format" "Short,?..." bitfld.long 0x00 10. "NOS,Not Outer Shareable attribute for the region" "Outer,Inner" newline bitfld.long 0x00 9. "NS,Non-secure" "No,Yes" bitfld.long 0x00 7. "SH,Shareability attribute for the region" "No,Yes" newline bitfld.long 0x00 4.--6. "INNER,Inner memory attributes for the region" "Non-cacheable,Device-nGnRnE,Reserved,Device-nGnRE,Reserved,Write-Back/Write-Allocate,Write-Through,Write-Back/No Write-Allocate" newline bitfld.long 0x00 2.--3. "OUTER,Outer memory attributes for the region" "Non-cacheable,Write-Back/Write-Allocate,Write-Through/No Write-Allocate,Write-Back/No Write-Allocate" newline bitfld.long 0x00 1. "SS,Used to indicate if the result is a Supersection" "No,Yes" newline bitfld.long 0x00 0. "F,Indicates whether the conversion completed successfully" "Successful,?..." elif ((((per.l(c15:0x0202))&0x80000000)==0x00000000)&&(((per.l(c15:0x0047))&0x1)==0x1)) group.long c15:0x0047++0x00 line.long 0x00 "PAR,Physical Address Register" newline bitfld.long 0x00 11. "LPAE,Descriptor translation table format" "Short,?..." newline bitfld.long 0x00 6. "FS[5],Fault status bit [5] - External abort type" "Internal,External" newline newline newline bitfld.long 0x00 1.--5. "FS[4:0],Fault status bit [4:0] - Abort source" "Reserved,Alignment,Debug,Access flag/L1,Instruction,Translation/L1,Access flag/L2,Translation/L2,Sync. external,Domain/L1,Reserved,Domain/L2,Sync. external/on TTW/L1,Permission/L1,Sync. external/on TTW/L2,Permission/L2,TLB conflict,Reserved,Reserved,Reserved,Lockdown,Unsupp. exclusive access,SError,Reserved,Reserved,Sync. parity/ECC on memory access,Reserved,Reserved,Sync. parity/ECC on TTW/L1,Reserved,Sync. parity/ECC on TTW/L2,?..." newline bitfld.long 0x00 0. "F,Indicates whether the conversion completed successfully" ",Aborted" elif ((((per.l(c15:0x0202))&0x80000000)==0x80000000)&&(((per.l(c15:0x10070))&0x1)==0x0)) group.quad c15:0x10070++0x01 line.quad 0x00 "PAR,Physical Address Register" hexmask.quad.byte 0x00 56.--63. 1. "ATTR,Memory attributes for the returned PA" hexmask.quad.long 0x00 12.--39. 0x10 "PA,Physical Address" newline bitfld.quad 0x00 11. "LPAE,Descriptor translation table format" ",Long" newline bitfld.quad 0x00 9. "NS,Non-secure" "No,Yes" bitfld.quad 0x00 7.--8. "SH,Shareability attribute" "Non-shareable,Reserved,Outer Shareable,Inner Shareable" newline newline newline newline bitfld.quad 0x00 0. "F,Indicates whether the conversion completed successfully" "Successful,?..." else group.quad c15:0x10070++0x01 line.quad 0x00 "PAR,Physical Address Register" newline bitfld.quad 0x00 11. "LPAE,Descriptor translation table format" ",Long" newline bitfld.quad 0x00 9. "FSTAGE,Indicates the translation stage at which the translation aborted" "Stage 1,Stage 2" bitfld.quad 0x00 8. "S2WLK,Translation aborted because of a stage 2 fault during a stage 1 translation table walk" "No,Yes" newline newline newline bitfld.quad 0x00 1.--6. "FST,Fault Status Field" "Address size/TTBR,Address size/L1,Address size/L2,Address size/L3,Reserved,Translation/L1,Translation/L2,Translation/L3,Reserved,Access flag/L1,Access flag/L2,Access flag/L3,Reserved,Permission/L1,Permission/L2,Permission/L3,Sync. external,Reserved,Reserved,Reserved,Reserved,Sync. external/on TTW/L1,Sync. external/on TTW/L2,Sync. external/on TTW/L3,Sync. parity/ECC on memory access,Sync. parity/ECC on memory access,Reserved,Reserved,Reserved,Sync. parity/ECC on TTW/L1,Sync. parity/ECC on TTW/L2,Sync. parity/ECC/on TTW/L3,Reserved,Alignment,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,TLB conflict,?..." newline bitfld.quad 0x00 0. "F,Indicates whether the conversion completed successfully" ",Aborted" endif endif tree.open "Memory Attribute Indirection Registers" rgroup.long c15:0x003A++0x00 line.long 0x00 "AMAIR0,Auxiliary Memory Attribute Indirection Register 0" rgroup.long c15:0x013A++0x00 line.long 0x00 "AMAIR1,Auxiliary Memory Attribute Indirection Register 1" if corename()=="CORTEXA75" if (((per.l(c15:0x0202))&0x80000000)==0x80000000) group.long c15:0x402A++0x00 line.long 0x00 "HMAIR0,Hypervisor Memory Attribute Indirection Register 0" bitfld.long 0x00 28.--31. "ATTR3H,Attribute 3 High" "Device memory,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Non-Cacheable,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient" bitfld.long 0x00 24.--27. "ATTR3L,Attribute 3 Low" "Device-nGnRnE/---,---/Inner Write-through transient,---/Inner Write-through transient,---/Inner Write-through transient,Device-nGnRE/Inner Non-Cacheable,---/Inner Write-back transient,---/Inner Write-back transient,---/Inner Write-back transient,Device-nGRE memory/Inner Write-through,---/Inner Write-through non-transient,---/Inner Write-through non-transient,---/Inner Write-through non-transient,Reserved,---/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient" newline bitfld.long 0x00 20.--23. "ATTR2H,Attribute 2 High" "Device memory,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Non-Cacheable,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient" bitfld.long 0x00 16.--19. "ATTR2L,Attribute 2 Low" "Device-nGnRnE/---,---/Inner Write-through transient,---/Inner Write-through transient,---/Inner Write-through transient,Device-nGnRE/Inner Non-Cacheable,---/Inner Write-back transient,---/Inner Write-back transient,---/Inner Write-back transient,Device-nGRE memory/Inner Write-through,---/Inner Write-through non-transient,---/Inner Write-through non-transient,---/Inner Write-through non-transient,Reserved,---/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient" newline bitfld.long 0x00 12.--15. "ATTR1H,Attribute 1 High" "Device memory,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Non-Cacheable,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient" bitfld.long 0x00 8.--11. "ATTR1L,Attribute 1 Low" "Device-nGnRnE/---,---/Inner Write-through transient,---/Inner Write-through transient,---/Inner Write-through transient,Device-nGnRE/Inner Non-Cacheable,---/Inner Write-back transient,---/Inner Write-back transient,---/Inner Write-back transient,Device-nGRE memory/Inner Write-through,---/Inner Write-through non-transient,---/Inner Write-through non-transient,---/Inner Write-through non-transient,Reserved,---/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient" newline bitfld.long 0x00 4.--7. "ATTR0H,Attribute 0 High" "Device memory,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Non-Cacheable,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient" bitfld.long 0x00 0.--3. "ATTR0L,Attribute 0 Low" "Device-nGnRnE/---,---/Inner Write-through transient,---/Inner Write-through transient,---/Inner Write-through transient,Device-nGnRE/Inner Non-Cacheable,---/Inner Write-back transient,---/Inner Write-back transient,---/Inner Write-back transient,Device-nGRE memory/Inner Write-through,---/Inner Write-through non-transient,---/Inner Write-through non-transient,---/Inner Write-through non-transient,Reserved,---/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient" group.long c15:0x412A++0x00 line.long 0x00 "HMAIR1,Hypervisor Memory Attribute Indirection Register 1" bitfld.long 0x00 28.--31. "ATTR7H,Attribute 7 High" "Device memory,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Non-Cacheable,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient" bitfld.long 0x00 24.--27. "ATTR7L,Attribute 7 Low" "Device-nGnRnE/---,---/Inner Write-through transient,---/Inner Write-through transient,---/Inner Write-through transient,Device-nGnRE/Inner Non-Cacheable,---/Inner Write-back transient,---/Inner Write-back transient,---/Inner Write-back transient,Device-nGRE memory/Inner Write-through,---/Inner Write-through non-transient,---/Inner Write-through non-transient,---/Inner Write-through non-transient,Reserved,---/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient" newline bitfld.long 0x00 20.--23. "ATTR6H,Attribute 6 High" "Device memory,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Non-Cacheable,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient" bitfld.long 0x00 16.--19. "ATTR6L,Attribute 6 Low" "Device-nGnRnE/---,---/Inner Write-through transient,---/Inner Write-through transient,---/Inner Write-through transient,Device-nGnRE/Inner Non-Cacheable,---/Inner Write-back transient,---/Inner Write-back transient,---/Inner Write-back transient,Device-nGRE memory/Inner Write-through,---/Inner Write-through non-transient,---/Inner Write-through non-transient,---/Inner Write-through non-transient,Reserved,---/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient" newline bitfld.long 0x00 12.--15. "ATTR5H,Attribute 5 High" "Device memory,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Non-Cacheable,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient" bitfld.long 0x00 8.--11. "ATTR5L,Attribute 5 Low" "Device-nGnRnE/---,---/Inner Write-through transient,---/Inner Write-through transient,---/Inner Write-through transient,Device-nGnRE/Inner Non-Cacheable,---/Inner Write-back transient,---/Inner Write-back transient,---/Inner Write-back transient,Device-nGRE memory/Inner Write-through,---/Inner Write-through non-transient,---/Inner Write-through non-transient,---/Inner Write-through non-transient,Reserved,---/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient" newline bitfld.long 0x00 4.--7. "ATTR4H,Attribute 4 High" "Device memory,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Non-Cacheable,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient" bitfld.long 0x00 0.--3. "ATTR4L,Attribute 4 Low" "Device-nGnRnE/---,---/Inner Write-through transient,---/Inner Write-through transient,---/Inner Write-through transient,Device-nGnRE/Inner Non-Cacheable,---/Inner Write-back transient,---/Inner Write-back transient,---/Inner Write-back transient,Device-nGRE memory/Inner Write-through,---/Inner Write-through non-transient,---/Inner Write-through non-transient,---/Inner Write-through non-transient,Reserved,---/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient" else rgroup.long c15:0x402A++0x00 line.long 0x00 "HMAIR0,Hypervisor Memory Attribute Indirection Register 0" rgroup.long c15:0x412A++0x00 line.long 0x00 "HMAIR1,Hypervisor Memory Attribute Indirection Register 1" endif elif corename()=="CORTEXA55" if (((per.l(c15:0x0202))&0x80000000)==0x80000000) group.long c15:0x402A++0x00 line.long 0x00 "HMAIR0,Hypervisor Memory Attribute Indirection Register 0" bitfld.long 0x00 28.--31. "ATTR3H,Attribute 3 High" "Device memory,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Non-Cacheable,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient" bitfld.long 0x00 24.--27. "ATTR3L,Attribute 3 Low" "Device-nGnRnE/---,---/Inner Write-through transient,---/Inner Write-through transient,---/Inner Write-through transient,Device-nGnRE/Inner Non-Cacheable,---/Inner Write-back transient,---/Inner Write-back transient,---/Inner Write-back transient,Device-nGRE memory/Inner Write-through,---/Inner Write-through non-transient,---/Inner Write-through non-transient,---/Inner Write-through non-transient,Device-GRE memory/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient" newline bitfld.long 0x00 20.--23. "ATTR2H,Attribute 2 High" "Device memory,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Non-Cacheable,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient" bitfld.long 0x00 16.--19. "ATTR2L,Attribute 2 Low" "Device-nGnRnE/---,---/Inner Write-through transient,---/Inner Write-through transient,---/Inner Write-through transient,Device-nGnRE/Inner Non-Cacheable,---/Inner Write-back transient,---/Inner Write-back transient,---/Inner Write-back transient,Device-nGRE memory/Inner Write-through,---/Inner Write-through non-transient,---/Inner Write-through non-transient,---/Inner Write-through non-transient,Device-GRE memory/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient" newline bitfld.long 0x00 12.--15. "ATTR1H,Attribute 1 High" "Device memory,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Non-Cacheable,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient" bitfld.long 0x00 8.--11. "ATTR1L,Attribute 1 Low" "Device-nGnRnE/---,---/Inner Write-through transient,---/Inner Write-through transient,---/Inner Write-through transient,Device-nGnRE/Inner Non-Cacheable,---/Inner Write-back transient,---/Inner Write-back transient,---/Inner Write-back transient,Device-nGRE memory/Inner Write-through,---/Inner Write-through non-transient,---/Inner Write-through non-transient,---/Inner Write-through non-transient,Device-GRE memory/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient" newline bitfld.long 0x00 4.--7. "ATTR0H,Attribute 0 High" "Device memory,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Non-Cacheable,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient" bitfld.long 0x00 0.--3. "ATTR0L,Attribute 0 Low" "Device-nGnRnE/---,---/Inner Write-through transient,---/Inner Write-through transient,---/Inner Write-through transient,Device-nGnRE/Inner Non-Cacheable,---/Inner Write-back transient,---/Inner Write-back transient,---/Inner Write-back transient,Device-nGRE memory/Inner Write-through,---/Inner Write-through non-transient,---/Inner Write-through non-transient,---/Inner Write-through non-transient,Device-GRE memory/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient" group.long c15:0x412A++0x00 line.long 0x00 "HMAIR1,Hypervisor Memory Attribute Indirection Register 1" bitfld.long 0x00 28.--31. "ATTR7H,Attribute 7 High" "Device memory,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Non-Cacheable,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient" bitfld.long 0x00 24.--27. "ATTR7L,Attribute 7 Low" "Device-nGnRnE/---,---/Inner Write-through transient,---/Inner Write-through transient,---/Inner Write-through transient,Device-nGnRE/Inner Non-Cacheable,---/Inner Write-back transient,---/Inner Write-back transient,---/Inner Write-back transient,Device-nGRE memory/Inner Write-through,---/Inner Write-through non-transient,---/Inner Write-through non-transient,---/Inner Write-through non-transient,Device-GRE memory/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient" newline bitfld.long 0x00 20.--23. "ATTR6H,Attribute 6 High" "Device memory,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Non-Cacheable,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient" bitfld.long 0x00 16.--19. "ATTR6L,Attribute 6 Low" "Device-nGnRnE/---,---/Inner Write-through transient,---/Inner Write-through transient,---/Inner Write-through transient,Device-nGnRE/Inner Non-Cacheable,---/Inner Write-back transient,---/Inner Write-back transient,---/Inner Write-back transient,Device-nGRE memory/Inner Write-through,---/Inner Write-through non-transient,---/Inner Write-through non-transient,---/Inner Write-through non-transient,Device-GRE memory/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient" newline bitfld.long 0x00 12.--15. "ATTR5H,Attribute 5 High" "Device memory,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Non-Cacheable,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient" bitfld.long 0x00 8.--11. "ATTR5L,Attribute 5 Low" "Device-nGnRnE/---,---/Inner Write-through transient,---/Inner Write-through transient,---/Inner Write-through transient,Device-nGnRE/Inner Non-Cacheable,---/Inner Write-back transient,---/Inner Write-back transient,---/Inner Write-back transient,Device-nGRE memory/Inner Write-through,---/Inner Write-through non-transient,---/Inner Write-through non-transient,---/Inner Write-through non-transient,Device-GRE memory/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient" newline bitfld.long 0x00 4.--7. "ATTR4H,Attribute 4 High" "Device memory,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Non-Cacheable,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient" bitfld.long 0x00 0.--3. "ATTR4L,Attribute 4 Low" "Device-nGnRnE/---,---/Inner Write-through transient,---/Inner Write-through transient,---/Inner Write-through transient,Device-nGnRE/Inner Non-Cacheable,---/Inner Write-back transient,---/Inner Write-back transient,---/Inner Write-back transient,Device-nGRE memory/Inner Write-through,---/Inner Write-through non-transient,---/Inner Write-through non-transient,---/Inner Write-through non-transient,Device-GRE memory/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient" else rgroup.long c15:0x402A++0x00 line.long 0x00 "HMAIR0,Hypervisor Memory Attribute Indirection Register 0" rgroup.long c15:0x412A++0x00 line.long 0x00 "HMAIR1,Hypervisor Memory Attribute Indirection Register 1" endif endif rgroup.long c15:0x403A++0x00 line.long 0x00 "HAMAIR0,Hypervisor Auxiliary Memory Attribute Indirection Register 0" rgroup.long c15:0x413A++0x00 line.long 0x00 "HAMAIR1,Hypervisor Auxiliary Memory Attribute Indirection Register 1" if corename()=="CORTEXA75" if (((per.l(c15:0x0202))&0x80000000)==0x80000000) group.long c15:0x002A++0x00 line.long 0x00 "MAIR0,Memory Attribute Indirection Register 0" bitfld.long 0x00 28.--31. "ATTR3H,Attribute 3 High" "Device memory,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Non-Cacheable,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient" bitfld.long 0x00 24.--27. "ATTR3L,Attribute 3 Low" "Device-nGnRnE/---,---/Inner Write-through transient,---/Inner Write-through transient,---/Inner Write-through transient,Device-nGnRE/Inner Non-Cacheable,---/Inner Write-back transient,---/Inner Write-back transient,---/Inner Write-back transient,Device-nGRE memory/Inner Write-through,---/Inner Write-through non-transient,---/Inner Write-through non-transient,---/Inner Write-through non-transient,Reserved,---/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient" newline bitfld.long 0x00 20.--23. "ATTR2H,Attribute 2 High" "Device memory,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Non-Cacheable,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient" bitfld.long 0x00 16.--19. "ATTR2L,Attribute 2 Low" "Device-nGnRnE/---,---/Inner Write-through transient,---/Inner Write-through transient,---/Inner Write-through transient,Device-nGnRE/Inner Non-Cacheable,---/Inner Write-back transient,---/Inner Write-back transient,---/Inner Write-back transient,Device-nGRE memory/Inner Write-through,---/Inner Write-through non-transient,---/Inner Write-through non-transient,---/Inner Write-through non-transient,Reserved,---/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient" newline bitfld.long 0x00 12.--15. "ATTR1H,Attribute 1 High" "Device memory,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Non-Cacheable,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient" bitfld.long 0x00 8.--11. "ATTR1L,Attribute 1 Low" "Device-nGnRnE/---,---/Inner Write-through transient,---/Inner Write-through transient,---/Inner Write-through transient,Device-nGnRE/Inner Non-Cacheable,---/Inner Write-back transient,---/Inner Write-back transient,---/Inner Write-back transient,Device-nGRE memory/Inner Write-through,---/Inner Write-through non-transient,---/Inner Write-through non-transient,---/Inner Write-through non-transient,Reserved,---/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient" newline bitfld.long 0x00 4.--7. "ATTR0H,Attribute 0 High" "Device memory,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Non-Cacheable,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient" bitfld.long 0x00 0.--3. "ATTR0L,Attribute 0 Low" "Device-nGnRnE/---,---/Inner Write-through transient,---/Inner Write-through transient,---/Inner Write-through transient,Device-nGnRE/Inner Non-Cacheable,---/Inner Write-back transient,---/Inner Write-back transient,---/Inner Write-back transient,Device-nGRE memory/Inner Write-through,---/Inner Write-through non-transient,---/Inner Write-through non-transient,---/Inner Write-through non-transient,Reserved,---/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient" group.long c15:0x012A++0x00 line.long 0x00 "MAIR1,Memory Attribute Indirection Register 1" bitfld.long 0x00 28.--31. "ATTR7H,Attribute 7 High" "Device memory,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Non-Cacheable,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient" bitfld.long 0x00 24.--27. "ATTR7L,Attribute 7 Low" "Device-nGnRnE/---,---/Inner Write-through transient,---/Inner Write-through transient,---/Inner Write-through transient,Device-nGnRE/Inner Non-Cacheable,---/Inner Write-back transient,---/Inner Write-back transient,---/Inner Write-back transient,Device-nGRE memory/Inner Write-through,---/Inner Write-through non-transient,---/Inner Write-through non-transient,---/Inner Write-through non-transient,Reserved,---/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient" newline bitfld.long 0x00 20.--23. "ATTR6H,Attribute 6 High" "Device memory,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Non-Cacheable,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient" bitfld.long 0x00 16.--19. "ATTR6L,Attribute 6 Low" "Device-nGnRnE/---,---/Inner Write-through transient,---/Inner Write-through transient,---/Inner Write-through transient,Device-nGnRE/Inner Non-Cacheable,---/Inner Write-back transient,---/Inner Write-back transient,---/Inner Write-back transient,Device-nGRE memory/Inner Write-through,---/Inner Write-through non-transient,---/Inner Write-through non-transient,---/Inner Write-through non-transient,Reserved,---/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient" newline bitfld.long 0x00 12.--15. "ATTR5H,Attribute 5 High" "Device memory,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Non-Cacheable,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient" bitfld.long 0x00 8.--11. "ATTR5L,Attribute 5 Low" "Device-nGnRnE/---,---/Inner Write-through transient,---/Inner Write-through transient,---/Inner Write-through transient,Device-nGnRE/Inner Non-Cacheable,---/Inner Write-back transient,---/Inner Write-back transient,---/Inner Write-back transient,Device-nGRE memory/Inner Write-through,---/Inner Write-through non-transient,---/Inner Write-through non-transient,---/Inner Write-through non-transient,Reserved,---/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient" newline bitfld.long 0x00 4.--7. "ATTR4H,Attribute 4 High" "Device memory,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Non-Cacheable,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient" bitfld.long 0x00 0.--3. "ATTR4L,Attribute 4 Low" "Device-nGnRnE/---,---/Inner Write-through transient,---/Inner Write-through transient,---/Inner Write-through transient,Device-nGnRE/Inner Non-Cacheable,---/Inner Write-back transient,---/Inner Write-back transient,---/Inner Write-back transient,Device-nGRE memory/Inner Write-through,---/Inner Write-through non-transient,---/Inner Write-through non-transient,---/Inner Write-through non-transient,Reserved,---/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient" group.long c15:0x010D++0x00 line.long 0x00 "CONTEXTIDR,Context ID Register" else group.long c15:0x002A++0x0 line.long 0x00 "PRRR,Primary Region Remap Register" bitfld.long 0x00 31. "NOS7,Outer Shareable property mapping for memory attributes" "Outer,Inner" bitfld.long 0x00 30. "NOS6,Outer Shareable property mapping for memory attributes" "Outer,Inner" newline bitfld.long 0x00 29. "NOS5,Outer Shareable property mapping for memory attributes" "Outer,Inner" bitfld.long 0x00 28. "NOS4,Outer Shareable property mapping for memory attributes" "Outer,Inner" newline bitfld.long 0x00 27. "NOS3,Outer Shareable property mapping for memory attributes" "Outer,Inner" bitfld.long 0x00 26. "NOS2,Outer Shareable property mapping for memory attributes" "Outer,Inner" newline bitfld.long 0x00 25. "NOS1,Outer Shareable property mapping for memory attributes" "Outer,Inner" bitfld.long 0x00 24. "NOS0,Outer Shareable property mapping for memory attributes" "Outer,Inner" newline bitfld.long 0x00 19. "NS1,Mapping of S = 1 attribute for Normal memory" "Not shareable,Shareable" bitfld.long 0x00 18. "NS0,Mapping of S = 0 attribute for Normal memory" "Not shareable,Shareable" newline bitfld.long 0x00 17. "DS1,Mapping of S = 1 attribute for Device memory" "Not shareable,Shareable" bitfld.long 0x00 16. "DS0,Mapping of S = 0 attribute for Device memory" "Not shareable,Shareable" newline bitfld.long 0x00 14.--15. "TR7,{TEX[0] C B} = b111 Remap" "Device (nGnRnE),Device (not nGnRnE),Normal,?..." bitfld.long 0x00 12.--13. "TR6,{TEX[0] C B} = b110 Remap" "Device (nGnRnE),Device (not nGnRnE),Normal,?..." newline bitfld.long 0x00 10.--11. "TR5,{TEX[0] C B} = b101 Remap" "Device (nGnRnE),Device (not nGnRnE),Normal,?..." bitfld.long 0x00 8.--9. "TR4,{TEX[0] C B} = b100 Remap" "Device (nGnRnE),Device (not nGnRnE),Normal,?..." newline bitfld.long 0x00 6.--7. "TR3,{TEX[0] C B} = b011 Remap" "Device (nGnRnE),Device (not nGnRnE),Normal,?..." bitfld.long 0x00 4.--5. "TR2,{TEX[0] C B} = b010 Remap" "Device (nGnRnE),Device (not nGnRnE),Normal,?..." newline bitfld.long 0x00 2.--3. "TR1,{TEX[0] C B} = b001 Remap" "Device (nGnRnE),Device (not nGnRnE),Normal,?..." bitfld.long 0x00 0.--1. "TR0,{TEX[0] C B} = b000 Remap" "Device (nGnRnE),Device (not nGnRnE),Normal,?..." group.long c15:0x012A++0x0 line.long 0x00 "NMRR,Normal Memory Remap Register" bitfld.long 0x00 30.--31. "OR7,Outer Attribute for {TEX[0] C B} = b111 Remap" "Non-cacheable,Write-Back Allocate,Write-Through,Write-Back no Allocate" bitfld.long 0x00 28.--29. "OR6,Outer Attribute for {TEX[0] C B} = b110 Remap" "Non-cacheable,Write-Back Allocate,Write-Through,Write-Back no Allocate" newline bitfld.long 0x00 26.--27. "OR5,Outer Attribute for {TEX[0] C B} = b101 Remap" "Non-cacheable,Write-Back Allocate,Write-Through,Write-Back no Allocate" bitfld.long 0x00 24.--25. "OR4,Outer Attribute for {TEX[0] C B} = b100 Remap" "Non-cacheable,Write-Back Allocate,Write-Through,Write-Back no Allocate" newline bitfld.long 0x00 22.--23. "OR3,Outer Attribute for {TEX[0] C B} = b011 Remap" "Non-cacheable,Write-Back Allocate,Write-Through,Write-Back no Allocate" bitfld.long 0x00 20.--21. "OR2,Outer Attribute for {TEX[0] C B} = b010 Remap" "Non-cacheable,Write-Back Allocate,Write-Through,Write-Back no Allocate" newline bitfld.long 0x00 18.--19. "OR1,Outer Attribute for {TEX[0] C B} = b001 Remap" "Non-cacheable,Write-Back Allocate,Write-Through,Write-Back no Allocate" bitfld.long 0x00 16.--17. "OR0,Outer Attribute for {TEX[0] C B} = b000 Remap" "Non-cacheable,Write-Back Allocate,Write-Through,Write-Back no Allocate" newline bitfld.long 0x00 14.--15. "IR7,Inner attribute for {TEX[0] C B} = b111 Remap" "Non-cacheable,Write-Back Allocate,Write-Through,Write-Back no Allocate" bitfld.long 0x00 12.--13. "IR6,Inner attribute for {TEX[0] C B} = b110 Remap" "Non-cacheable,Write-Back Allocate,Write-Through,Write-Back no Allocate" newline bitfld.long 0x00 10.--11. "IR5,Inner attribute for {TEX[0] C B} = b101 Remap" "Non-cacheable,Write-Back Allocate,Write-Through,Write-Back no Allocate" bitfld.long 0x00 8.--9. "IR4,Inner attribute for {TEX[0] C B} = b100 Remap" "Non-cacheable,Write-Back Allocate,Write-Through,Write-Back no Allocate" newline bitfld.long 0x00 6.--7. "IR3,Inner attribute for {TEX[0] C B} = b011 Remap" "Non-cacheable,Write-Back Allocate,Write-Through,Write-Back no Allocate" bitfld.long 0x00 4.--5. "IR2,Inner attribute for {TEX[0] C B} = b010 Remap" "Non-cacheable,Write-Back Allocate,Write-Through,Write-Back no Allocate" newline bitfld.long 0x00 2.--3. "IR1,Inner attribute for {TEX[0] C B} = b001 Remap" "Non-cacheable,Write-Back Allocate,Write-Through,Write-Back no Allocate" bitfld.long 0x00 0.--1. "IR0,Inner attribute for {TEX[0] C B} = b000 Remap" "Non-cacheable,Write-Back Allocate,Write-Through,Write-Back no Allocate" group.long c15:0x010D++0x00 line.long 0x00 "CONTEXTIDR,Context ID Register" hexmask.long.tbyte 0x00 8.--31. 1. "PROCID,Process Identifier" hexmask.long.byte 0x00 0.--7. 1. "ASID,Address Space Identifier" endif elif corename()=="CORTEXA55" if (((per.l(c15:0x0202))&0x80000000)==0x80000000) group.long c15:0x002A++0x00 line.long 0x00 "MAIR0,Memory Attribute Indirection Register 0" bitfld.long 0x00 28.--31. "ATTR3H,Attribute 3 High" "Device memory,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Non-Cacheable,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient" bitfld.long 0x00 24.--27. "ATTR3L,Attribute 3 Low" "Device-nGnRnE/---,---/Inner Write-through transient,---/Inner Write-through transient,---/Inner Write-through transient,Device-nGnRE/Inner Non-Cacheable,---/Inner Write-back transient,---/Inner Write-back transient,---/Inner Write-back transient,Device-nGRE memory/Inner Write-through,---/Inner Write-through non-transient,---/Inner Write-through non-transient,---/Inner Write-through non-transient,Device-GRE memory/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient" newline bitfld.long 0x00 20.--23. "ATTR2H,Attribute 2 High" "Device memory,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Non-Cacheable,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient" bitfld.long 0x00 16.--19. "ATTR2L,Attribute 2 Low" "Device-nGnRnE/---,---/Inner Write-through transient,---/Inner Write-through transient,---/Inner Write-through transient,Device-nGnRE/Inner Non-Cacheable,---/Inner Write-back transient,---/Inner Write-back transient,---/Inner Write-back transient,Device-nGRE memory/Inner Write-through,---/Inner Write-through non-transient,---/Inner Write-through non-transient,---/Inner Write-through non-transient,Device-GRE memory/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient" newline bitfld.long 0x00 12.--15. "ATTR1H,Attribute 1 High" "Device memory,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Non-Cacheable,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient" bitfld.long 0x00 8.--11. "ATTR1L,Attribute 1 Low" "Device-nGnRnE/---,---/Inner Write-through transient,---/Inner Write-through transient,---/Inner Write-through transient,Device-nGnRE/Inner Non-Cacheable,---/Inner Write-back transient,---/Inner Write-back transient,---/Inner Write-back transient,Device-nGRE memory/Inner Write-through,---/Inner Write-through non-transient,---/Inner Write-through non-transient,---/Inner Write-through non-transient,Device-GRE memory/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient" newline bitfld.long 0x00 4.--7. "ATTR0H,Attribute 0 High" "Device memory,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Non-Cacheable,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient" bitfld.long 0x00 0.--3. "ATTR0L,Attribute 0 Low" "Device-nGnRnE/---,---/Inner Write-through transient,---/Inner Write-through transient,---/Inner Write-through transient,Device-nGnRE/Inner Non-Cacheable,---/Inner Write-back transient,---/Inner Write-back transient,---/Inner Write-back transient,Device-nGRE memory/Inner Write-through,---/Inner Write-through non-transient,---/Inner Write-through non-transient,---/Inner Write-through non-transient,Device-GRE memory/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient" group.long c15:0x012A++0x00 line.long 0x00 "MAIR1,Memory Attribute Indirection Register 1" bitfld.long 0x00 28.--31. "ATTR7H,Attribute 7 High" "Device memory,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Non-Cacheable,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient" bitfld.long 0x00 24.--27. "ATTR7L,Attribute 7 Low" "Device-nGnRnE/---,---/Inner Write-through transient,---/Inner Write-through transient,---/Inner Write-through transient,Device-nGnRE/Inner Non-Cacheable,---/Inner Write-back transient,---/Inner Write-back transient,---/Inner Write-back transient,Device-nGRE memory/Inner Write-through,---/Inner Write-through non-transient,---/Inner Write-through non-transient,---/Inner Write-through non-transient,Device-GRE memory/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient" newline bitfld.long 0x00 20.--23. "ATTR6H,Attribute 6 High" "Device memory,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Non-Cacheable,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient" bitfld.long 0x00 16.--19. "ATTR6L,Attribute 6 Low" "Device-nGnRnE/---,---/Inner Write-through transient,---/Inner Write-through transient,---/Inner Write-through transient,Device-nGnRE/Inner Non-Cacheable,---/Inner Write-back transient,---/Inner Write-back transient,---/Inner Write-back transient,Device-nGRE memory/Inner Write-through,---/Inner Write-through non-transient,---/Inner Write-through non-transient,---/Inner Write-through non-transient,Device-GRE memory/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient" newline bitfld.long 0x00 12.--15. "ATTR5H,Attribute 5 High" "Device memory,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Non-Cacheable,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient" bitfld.long 0x00 8.--11. "ATTR5L,Attribute 5 Low" "Device-nGnRnE/---,---/Inner Write-through transient,---/Inner Write-through transient,---/Inner Write-through transient,Device-nGnRE/Inner Non-Cacheable,---/Inner Write-back transient,---/Inner Write-back transient,---/Inner Write-back transient,Device-nGRE memory/Inner Write-through,---/Inner Write-through non-transient,---/Inner Write-through non-transient,---/Inner Write-through non-transient,Device-GRE memory/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient" newline bitfld.long 0x00 4.--7. "ATTR4H,Attribute 4 High" "Device memory,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Non-Cacheable,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient" bitfld.long 0x00 0.--3. "ATTR4L,Attribute 4 Low" "Device-nGnRnE/---,---/Inner Write-through transient,---/Inner Write-through transient,---/Inner Write-through transient,Device-nGnRE/Inner Non-Cacheable,---/Inner Write-back transient,---/Inner Write-back transient,---/Inner Write-back transient,Device-nGRE memory/Inner Write-through,---/Inner Write-through non-transient,---/Inner Write-through non-transient,---/Inner Write-through non-transient,Device-GRE memory/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient" group.long c15:0x010D++0x00 line.long 0x00 "CONTEXTIDR,Context ID Register" else group.long c15:0x002A++0x0 line.long 0x00 "PRRR,Primary Region Remap Register" bitfld.long 0x00 31. "NOS7,Outer Shareable property mapping for memory attributes" "Outer,Inner" bitfld.long 0x00 30. "NOS6,Outer Shareable property mapping for memory attributes" "Outer,Inner" newline bitfld.long 0x00 29. "NOS5,Outer Shareable property mapping for memory attributes" "Outer,Inner" bitfld.long 0x00 28. "NOS4,Outer Shareable property mapping for memory attributes" "Outer,Inner" newline bitfld.long 0x00 27. "NOS3,Outer Shareable property mapping for memory attributes" "Outer,Inner" bitfld.long 0x00 26. "NOS2,Outer Shareable property mapping for memory attributes" "Outer,Inner" newline bitfld.long 0x00 25. "NOS1,Outer Shareable property mapping for memory attributes" "Outer,Inner" bitfld.long 0x00 24. "NOS0,Outer Shareable property mapping for memory attributes" "Outer,Inner" newline bitfld.long 0x00 19. "NS1,Mapping of S = 1 attribute for Normal memory" "Not shareable,Shareable" bitfld.long 0x00 18. "NS0,Mapping of S = 0 attribute for Normal memory" "Not shareable,Shareable" newline bitfld.long 0x00 17. "DS1,Mapping of S = 1 attribute for Device memory" "Not shareable,Shareable" bitfld.long 0x00 16. "DS0,Mapping of S = 0 attribute for Device memory" "Not shareable,Shareable" newline bitfld.long 0x00 14.--15. "TR7,{TEX[0] C B} = b111 Remap" "Device (nGnRnE),Device (not nGnRnE),Normal,?..." bitfld.long 0x00 12.--13. "TR6,{TEX[0] C B} = b110 Remap" "Device (nGnRnE),Device (not nGnRnE),Normal,?..." newline bitfld.long 0x00 10.--11. "TR5,{TEX[0] C B} = b101 Remap" "Device (nGnRnE),Device (not nGnRnE),Normal,?..." bitfld.long 0x00 8.--9. "TR4,{TEX[0] C B} = b100 Remap" "Device (nGnRnE),Device (not nGnRnE),Normal,?..." newline bitfld.long 0x00 6.--7. "TR3,{TEX[0] C B} = b011 Remap" "Device (nGnRnE),Device (not nGnRnE),Normal,?..." bitfld.long 0x00 4.--5. "TR2,{TEX[0] C B} = b010 Remap" "Device (nGnRnE),Device (not nGnRnE),Normal,?..." newline bitfld.long 0x00 2.--3. "TR1,{TEX[0] C B} = b001 Remap" "Device (nGnRnE),Device (not nGnRnE),Normal,?..." bitfld.long 0x00 0.--1. "TR0,{TEX[0] C B} = b000 Remap" "Device (nGnRnE),Device (not nGnRnE),Normal,?..." group.long c15:0x012A++0x0 line.long 0x00 "NMRR,Normal Memory Remap Register" bitfld.long 0x00 30.--31. "OR7,Outer Attribute for {TEX[0] C B} = b111 Remap" "Non-cacheable,Write-Back Allocate,Write-Through,Write-Back no Allocate" bitfld.long 0x00 28.--29. "OR6,Outer Attribute for {TEX[0] C B} = b110 Remap" "Non-cacheable,Write-Back Allocate,Write-Through,Write-Back no Allocate" newline bitfld.long 0x00 26.--27. "OR5,Outer Attribute for {TEX[0] C B} = b101 Remap" "Non-cacheable,Write-Back Allocate,Write-Through,Write-Back no Allocate" bitfld.long 0x00 24.--25. "OR4,Outer Attribute for {TEX[0] C B} = b100 Remap" "Non-cacheable,Write-Back Allocate,Write-Through,Write-Back no Allocate" newline bitfld.long 0x00 22.--23. "OR3,Outer Attribute for {TEX[0] C B} = b011 Remap" "Non-cacheable,Write-Back Allocate,Write-Through,Write-Back no Allocate" bitfld.long 0x00 20.--21. "OR2,Outer Attribute for {TEX[0] C B} = b010 Remap" "Non-cacheable,Write-Back Allocate,Write-Through,Write-Back no Allocate" newline bitfld.long 0x00 18.--19. "OR1,Outer Attribute for {TEX[0] C B} = b001 Remap" "Non-cacheable,Write-Back Allocate,Write-Through,Write-Back no Allocate" bitfld.long 0x00 16.--17. "OR0,Outer Attribute for {TEX[0] C B} = b000 Remap" "Non-cacheable,Write-Back Allocate,Write-Through,Write-Back no Allocate" newline bitfld.long 0x00 14.--15. "IR7,Inner attribute for {TEX[0] C B} = b111 Remap" "Non-cacheable,Write-Back Allocate,Write-Through,Write-Back no Allocate" bitfld.long 0x00 12.--13. "IR6,Inner attribute for {TEX[0] C B} = b110 Remap" "Non-cacheable,Write-Back Allocate,Write-Through,Write-Back no Allocate" newline bitfld.long 0x00 10.--11. "IR5,Inner attribute for {TEX[0] C B} = b101 Remap" "Non-cacheable,Write-Back Allocate,Write-Through,Write-Back no Allocate" bitfld.long 0x00 8.--9. "IR4,Inner attribute for {TEX[0] C B} = b100 Remap" "Non-cacheable,Write-Back Allocate,Write-Through,Write-Back no Allocate" newline bitfld.long 0x00 6.--7. "IR3,Inner attribute for {TEX[0] C B} = b011 Remap" "Non-cacheable,Write-Back Allocate,Write-Through,Write-Back no Allocate" bitfld.long 0x00 4.--5. "IR2,Inner attribute for {TEX[0] C B} = b010 Remap" "Non-cacheable,Write-Back Allocate,Write-Through,Write-Back no Allocate" newline bitfld.long 0x00 2.--3. "IR1,Inner attribute for {TEX[0] C B} = b001 Remap" "Non-cacheable,Write-Back Allocate,Write-Through,Write-Back no Allocate" bitfld.long 0x00 0.--1. "IR0,Inner attribute for {TEX[0] C B} = b000 Remap" "Non-cacheable,Write-Back Allocate,Write-Through,Write-Back no Allocate" group.long c15:0x010D++0x00 line.long 0x00 "CONTEXTIDR,Context ID Register" hexmask.long.tbyte 0x00 8.--31. 1. "PROCID,Process Identifier" hexmask.long.byte 0x00 0.--7. 1. "ASID,Address Space Identifier" endif endif tree.end tree.end tree "Virtualization Extensions" group.long c15:0x4000++0x00 line.long 0x00 "VPIDR,Virtualization Processor ID Register" hexmask.long.byte 0x0 24.--31. 0x1 "IMPL,Implementer code" bitfld.long 0x00 20.--23. "VAR,Variant" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 16.--19. "ARCH, Architecture" "0,ARMv4,ARMv4T,ARMv5,ARMv5T,ARMv5TE,ARMv5TEJ,ARMv6,8,9,10,11,12,13,14,CPUID scheme" hexmask.long.word 0x00 4.--15. 1. "PART,Primary Part Number" newline bitfld.long 0x00 0.--3. "REV,Revision Number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long c15:0x4500++0x00 line.long 0x00 "VMPIDR,Virtualization Multiprocessor ID Registers" bitfld.long 0x00 31. "M,Multiprocessing Extensions Register format" "Reserved,Supported" bitfld.long 0x00 30. "U,Processor is part of a multiprocessor or uniprocessor system" "Multiprocessor,Uniprocessor" newline bitfld.long 0x00 24. "MT,Lowest level of affinity consist of logical processors" "Not implemented,Implemented" hexmask.long.byte 0x00 16.--23. 1. "AFF2,Affinity level 2. Identifies different clusters within the system" newline bitfld.long 0x00 8.--15. "AFF1,Affinity level 1. Identifies individual cores within the local FCM cluster" "CORE0,CORE1,CORE2,CORE3,CORE4,CORE5,CORE6,CORE7,?..." hexmask.long.byte 0x00 0.--7. 1. "AFF0,Affinity level 0. Identifies individual threads within a multi-threaded core" group.long c15:0x420D++0x00 line.long 0x00 "HTPIDR,Hypervisor Software Thread ID Register" group.long c15:0x4001++0x0 line.long 0x00 "HSCTLR,Hypervisor System Control Register" bitfld.long 0x00 30. "TE,Thumb exception enable" "A32,T32" bitfld.long 0x00 25. "EE,Exception endianness" "Little,Big" newline bitfld.long 0x00 19. "WXN,Write permission implies XN" "Not forced,Forced" bitfld.long 0x00 12. "I,Instruction Cache Enable" "Disabled,Enabled" newline bitfld.long 0x00 8. "SED,SETEND Disable" "No,Yes" bitfld.long 0x00 7. "ITD,IT instruction functionality Disabled" "No,?..." newline bitfld.long 0x00 5. "CP15BEN,C15 Barrier Enable" "Disabled,Enabled" bitfld.long 0x00 4. "LSMAOE,Load/Store Multiple Atomicity and Ordering Enable" "Reserved,Enabled" newline bitfld.long 0x00 3. "NTLSMD,No Trap Load/Store Multiple to Device-nGRE/Device-nGnRE/Device-nGnRnE memory" "Reserved,No Trap" bitfld.long 0x00 2. "C,Enable unified cache or data cache" "Disabled,Enabled" newline bitfld.long 0x00 1. "A,Strict Alignment" "Disabled,Enabled" bitfld.long 0x00 0. "M,Enable address translation" "Disabled,Enabled" group.long c15:0x4101++0x00 line.long 0x00 "HACTLR,Hypervisor Auxiliary Control Register" bitfld.long 0x00 12. "CLUSTERPMUEN,Performance Management Registers write access control" "Not accessible,Accessible" bitfld.long 0x00 11. "SMEN,Scheme Management Registers write access control" "Not accessible,Accessible" newline bitfld.long 0x00 10. "TSIDEN,Thread Scheme ID Register enable" "Not accessible,Accessible" bitfld.long 0x00 7. "PWREN,Power Control Registers access control" "Not accessible,Accessible" newline bitfld.long 0x00 5. "ERXPFGEN,Error Record Registers write access control" "Not accessible,Accessible" bitfld.long 0x00 1. "ECTLREN,Extended Control Registers write access control" "Not accessible,Accessible" newline bitfld.long 0x00 0. "ACTLREN,Auxiliary Control Registers write access control" "Not accessible,Accessible" rgroup.long c15:0x4301++0x00 line.long 0x00 "HACTLR2,Hypervisor Auxiliary Control Register 2" rgroup.long c15:0x4711++0x00 line.long 0x00 "HACR,Hypervisor Auxiliary Configuration Register" group.long c15:0x4011++0x00 line.long 0x00 "HCR,Hypervisor Configuration Register" bitfld.long 0x00 30. "TRVM,Trap Read of Virtual Memory controls" "No trap,Trap" bitfld.long 0x00 27. "TGE,Trap General Exceptions from Non-secure EL0" "No trap,Trap" newline bitfld.long 0x00 26. "TVM,Trap Virtual Memory controls" "No trap,Trap" bitfld.long 0x00 25. "TTLB,Trap TLB maintenance instructions" "No trap,Trap" newline bitfld.long 0x00 24. "TPU,Trap Cache maintenance instructions to Point of Unification" "No trap,Trap" bitfld.long 0x00 23. "TPC,Trap Data/Unified Cache maintenance instructions to Point of Coherency" "No trap,Trap" newline bitfld.long 0x00 22. "TSW,Trap Data/Unified Cache maintenance instructions by Set/Way" "No trap,Trap" bitfld.long 0x00 21. "TAC,Trap Auxiliary Control Register" "No trap,Trap" newline bitfld.long 0x00 20. "TIDCP,Trap Implementation Dependent functionality" "No trap,Trap" bitfld.long 0x00 19. "TSC,Trap SMC" "No trap,Trap" newline bitfld.long 0x00 18. "TID3,Trap ID Group 3" "No trap,Trap" bitfld.long 0x00 17. "TID2,Trap ID Group 2" "No trap,Trap" newline bitfld.long 0x00 16. "TID1,Trap ID Group 1" "No trap,Trap" bitfld.long 0x00 15. "TID0,Trap ID Group 0" "No trap,Trap" newline bitfld.long 0x00 14. "TWE,Trap WFE" "No trap,Trap" bitfld.long 0x00 13. "TWI,Trap WFI" "No trap,Trap" newline bitfld.long 0x00 12. "DC,Default Cacheable" "Disabled,Enabled" bitfld.long 0x00 10.--11. "BSU,Barrier Shareability upgrade" "No effect,Inner Shareable,Outer Shareable,Full System" newline bitfld.long 0x00 9. "FB,Force broadcast" "Not forced,Forced" bitfld.long 0x00 8. "VA,Virtual Asynchronous Abort exception" "Not pending,Pending" newline bitfld.long 0x00 7. "VI,Virtual IRQ Interrupt" "Not pending,Pending" bitfld.long 0x00 6. "VF,Virtual FIQ Interrupt" "Not pending,Pending" newline bitfld.long 0x00 5. "AMO,Asynchronous Abort Mask Override" "Disabled,Enabled" bitfld.long 0x00 4. "IMO,Physical IRQ Routing" "Disabled,Enabled" newline bitfld.long 0x00 3. "FMO,Physical FIQ Routing" "Disabled,Enabled" bitfld.long 0x00 2. "PTW,Protected Table Walk" "Disabled,Enabled" newline bitfld.long 0x00 1. "SWIO,Set/Way Invalidation Override" "Disabled,Enabled" bitfld.long 0x00 0. "VM,Second stage of Translation enable" "Disabled,Enabled" group.long c15:0x4411++0x00 line.long 0x00 "HCR2,Hypervisor Configuration Register" bitfld.long 0x00 5. "TEA, Route synchronous external aborts to EL2" "Not routed,Routed" bitfld.long 0x00 4. "TERR, Trap Error record accesses" "No trap,Trap" newline bitfld.long 0x00 1. "ID,Stage 2 Instruction cache disable" "No,Yes" bitfld.long 0x00 0. "CD,Stage 2 Data cache disable" "No,Yes" group.long c15:0x3054++0x00 line.long 0x00 "DSPSR,Debug Saved Program Status Register" bitfld.long 0x00 31. "N,Negative condition flag" "Not negative,Negative" bitfld.long 0x00 30. "Z,Zero condition flag" "Not zero,Zero" newline bitfld.long 0x00 29. "C,Carry condition flag" "Not carry,Carry" bitfld.long 0x00 28. "V,Overflow condition flag" "No overflow,Overflow" newline bitfld.long 0x00 27. "Q,Cumulative condition flag" "Not occurred,Occurred" bitfld.long 0x00 22. "PAN,Privileged Access Never" "No,Yes" newline bitfld.long 0x00 21. "SS,Software step" "0,1" bitfld.long 0x00 20. "IL,Illegal Execution state" "0,1" newline bitfld.long 0x00 16.--19. "GE,Greater than or Equal flags" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 13.--15. "IT[5:7],IT block state bits for the T32 IT (If-Then) instruction - base condition for the IT block" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 25.--26. 10.--12. "IT[0:4],IT block state bits for the T32 IT (If-Then) instruction - size of the IT block" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 9. "E,Endianness state bit" "Little,Big" newline bitfld.long 0x00 8. "A,Asynchronous data abort mask bit" "Not masked,Masked" bitfld.long 0x00 7. "I,IRQ mask bit" "Not masked,Masked" newline bitfld.long 0x00 6. "F,FIQ mask bit" "Not masked,Masked" bitfld.long 0x00 5. "T,T32 Instruction set state" "A32,T32" newline bitfld.long 0x00 4. "M[4],Execution state that the exception was taken from" ",AArch32" bitfld.long 0x00 0.--3. "M[3:0],Current PE mode" "User,FIQ,IRQ,Supervisor,,,Monitor,Abort,,,Hyp,Undefined,,,,System" group.long c15:0x4111++0x00 line.long 0x00 "HDCR,Hypervisor Debug Control Register" bitfld.long 0x00 17. "HPMD,Guest Performance Monitors Disable" "Allowed,Prohibited" bitfld.long 0x00 11. "TDRA,Trap Debug ROM Access" "No trap,Trap" newline bitfld.long 0x00 10. "TDOSA,Trap Debug OS-related Register Access" "No trap,Trap" bitfld.long 0x00 9. "TDA,Trap Debug Access" "No trap,Trap" newline bitfld.long 0x00 8. "TDE,Trap Debug Exceptions" "No trap,Trap" bitfld.long 0x00 7. "HPME,Hypervisor Performance Monitors Enable" "Disabled,Enabled" newline bitfld.long 0x00 6. "TPM,Trap Performance Monitors accesses" "No trap,Trap" bitfld.long 0x00 5. "TPMCR,Trap Performance Monitor Control Register accesses" "No trap,Trap" newline bitfld.long 0x00 0.--4. "HPMN,Defines the number of Performance Monitors counters" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long c15:0x4211++0x00 line.long 0x00 "HCPTR,Hypervisor Coprocessor Trap Register" bitfld.long 0x0 31. "TCPAC,Trap Coprocessor Access Control" "No trap,Trap" bitfld.long 0x0 20. "TTA,Traps Non-secure System Register accesses to all implemented trace Registers to Hypervisor mode" "No trap,Trap" newline bitfld.long 0x0 15. "TASE,Trap Advanced SIMD extensions" "No trap,Trap" bitfld.long 0x0 11. "TCP11,Trap coprocessor 11" "No trap,Trap" newline bitfld.long 0x0 10. "TCP10,Trap coprocessor 10" "No trap,Trap" group.long c15:0x4311++0x00 line.long 0x00 "HSTR,Hypervisor System Trap Register" bitfld.long 0x00 15. "T15,Trap to Hypervisor mode Non-secure priv 15" "No trap,Trap" bitfld.long 0x00 13. "T13,Trap to Hypervisor mode Non-secure priv 13" "No trap,Trap" newline bitfld.long 0x00 12. "T12,Trap to Hypervisor mode Non-secure priv 12" "No trap,Trap" bitfld.long 0x00 11. "T11,Trap to Hypervisor mode Non-secure priv 11" "No trap,Trap" newline bitfld.long 0x00 10. "T10,Trap to Hypervisor mode Non-secure priv 10" "No trap,Trap" bitfld.long 0x00 9. "T9,Trap to Hypervisor mode Non-secure priv 9" "No trap,Trap" newline bitfld.long 0x00 8. "T8,Trap to Hypervisor mode Non-secure priv 8" "No trap,Trap" bitfld.long 0x00 7. "T7,Trap to Hypervisor mode Non-secure priv 7" "No trap,Trap" newline bitfld.long 0x00 6. "T6,Trap to Hypervisor mode Non-secure priv 6" "No trap,Trap" bitfld.long 0x00 5. "T5,Trap to Hypervisor mode Non-secure priv 5" "No trap,Trap" newline bitfld.long 0x00 3. "T3,Trap to Hypervisor mode Non-secure priv 3" "No trap,Trap" bitfld.long 0x00 2. "T2,Trap to Hypervisor mode Non-secure priv 2" "No trap,Trap" newline bitfld.long 0x00 1. "T1,Trap to Hypervisor mode Non-secure priv 1" "No trap,Trap" bitfld.long 0x00 0. "T0,Trap to Hypervisor mode Non-secure priv 0" "No trap,Trap" group.quad c15:0x14020++0x01 line.quad 0x00 "HTTBR,Hypervisor Translation Table Base Register" hexmask.quad 0x00 1.--47. 0x02 "BADDR,Translation table base address" bitfld.quad 0x00 0. "CNP,Common not Private" "Not supported,Supported" group.long c15:0x4202++0x00 line.long 0x00 "HTCR,Hypervisor Translation Control Register" bitfld.long 0x00 28. "HWU62,Hardware usage of bit[62] of the stage2 translation table block or level 3 entry" "Not possible,Possible" bitfld.long 0x00 27. "HWU61,Hardware usage of bit[61] of the stage2 translation table block or level 3 entry" "Not possible,Possible" newline bitfld.long 0x00 26. "HWU60,Hardware usage of bit[60] of the stage2 translation table block or level 3 entry" "Not possible,Possible" bitfld.long 0x00 25. "HWU59,Hardware usage of bit[59] of the stage2 translation table block or level 3 entry" "Not possible,Possible" newline bitfld.long 0x00 24. "HPD,Hierarchical Permission Disables" "No,Yes" bitfld.long 0x00 12.--13. "SH0,Shareability attribute" "Non-shareable,Reserved,Outer Shareable,Inner Shareable" newline bitfld.long 0x00 10.--11. "ORGN0,Outer cacheability attribute, Normal memory" "Non-cacheable,Write-Back Write-Allocate Cacheable,Write-Through Cacheable,Write-Back no Write-Allocate Cacheable" bitfld.long 0x00 8.--9. "IRGN0, ,Inner cacheability attribute, Normal memory" "Non-cacheable,Write-Back Write-Allocate Cacheable,Write-Through Cacheable,Write-Back no Write-Allocate Cacheable" newline bitfld.long 0x00 0.--2. "T0SZ,The size offset of the memory region addressed by HTTBR" "0,1,2,3,4,5,6,7" if corename()=="CORTEXA75" group.quad c15:0x16020++0x01 line.quad 0x00 "VTTBR,Virtualization Translation Table Base Register" hexmask.quad.word 0x00 48.--63. 1. "VMID,VMID for the translation table" hexmask.quad 0x00 4.--47. 0x10 "BADDR,Translation table base address" newline bitfld.quad 0x00 0. "CNP,Common not Private" "Not supported,Supported" elif corename()=="CORTEXA55" group.long c15:0x407F++0x00 line.long 0x00 "AHTCR,Auxiliary Hypervisor Translation Control Register" bitfld.long 0x00 9. "HWVAL60,Indicates the value of PBHA[1] page table walks memory access if HWEN60 is set" "0,1" bitfld.long 0x00 8. "HWVAL59,Indicates the value of PBHA[1] page table walks memory access if HWEN59 is set" "0,1" newline bitfld.long 0x00 1. "HWEN60,Enables PBHA[1] page table walks memory access" "Disabled,Enabled" bitfld.long 0x00 0. "HWEN59,Enables PBHA[0] page table walks memory access" "Disabled,Enabled" group.quad c15:0x16020++0x01 line.quad 0x00 "VTTBR,Virtualization Translation Table Base Register" hexmask.quad.word 0x00 48.--63. 1. "ASID,ASID for the translation table base address" hexmask.quad 0x00 2.--47. 0x04 "BADDR,Translation table base address" newline bitfld.quad 0x00 0. "CNP,Common not Private" "Not supported,?..." endif if corename()=="CORTEXA75" group.long c15:0x4212++0x00 line.long 0x00 "VTCR,Virtualization Translation Control Register" bitfld.long 0x00 28. "HWU62,Hardware usage of bit[62] of the stage2 translation table block or level 3 entry" "Not possible,Possible" bitfld.long 0x00 27. "HWU61,Hardware usage of bit[61] of the stage2 translation table block or level 3 entry" "Not possible,Possible" newline bitfld.long 0x00 26. "HWU60,Hardware usage of bit[60] of the stage2 translation table block or level 3 entry" "Not possible,Possible" bitfld.long 0x00 25. "HWU59,Hardware usage of bit[59] of the stage2 translation table block or level 3 entry" "Not possible,Possible" newline bitfld.long 0x00 12.--13. "SH0,Shareability attribute" "Non-shareable,Reserved,Outer Shareable,Inner Shareable" bitfld.long 0x00 10.--11. "ORGN0,Outer cacheability attribute, Normal memory" "Non-cacheable,Write-Back Write-Allocate Cacheable,Write-Through Cacheable,Write-Back no Write-Allocate Cacheable" newline bitfld.long 0x00 8.--9. "IRGN0,Inner cacheability attribute, Normal memory" "Non-cacheable,Write-Back Write-Allocate Cacheable,Write-Through Cacheable,Write-Back no Write-Allocate Cacheable" bitfld.long 0x00 6.--7. "SL0,Starting level for translation table walks using VTTBR" "L2,L1,?..." newline bitfld.long 0x00 4. "S,Sign extension bit" "0,1" bitfld.long 0x00 0.--3. "T0SZ,Size offset of the memory region addressed by TTBR0" "0,1,2,3,4,5,6,7,-8,-7,-6,-5,-4,-3,-2,-1" elif corename()=="CORTEXA55" group.long c15:0x4212++0x00 line.long 0x00 "VTCR,Virtualization Translation Control Register" bitfld.long 0x00 12.--13. "SH0,Shareability attribute" "Non-shareable,Reserved,Outer Shareable,Inner Shareable" bitfld.long 0x00 10.--11. "ORGN0,Outer cacheability attribute, Normal memory" "Non-cacheable,Write-Back Write-Allocate Cacheable,Write-Through Cacheable,Write-Back no Write-Allocate Cacheable" newline bitfld.long 0x00 8.--9. "IRGN0,Inner cacheability attribute, Normal memory" "Non-cacheable,Write-Back Write-Allocate Cacheable,Write-Through Cacheable,Write-Back no Write-Allocate Cacheable" bitfld.long 0x00 6.--7. "SL0,Starting level for translation table walks using VTTBR" "L2,L1,?..." newline bitfld.long 0x00 4. "S,Sign extension bit" "0,1" bitfld.long 0x00 0.--3. "T0SZ,Size offset of the memory region addressed by TTBR0" "0,1,2,3,4,5,6,7,-8,-7,-6,-5,-4,-3,-2,-1" group.long c15:0x417F++0x00 line.long 0x00 "AVTCR,Auxiliary Virtualized Translation Control Register" bitfld.long 0x00 9. "HWVAL60,Indicates the value of PBHA[1] page table walks memory access if HWEN60 is set" "0,1" bitfld.long 0x00 8. "HWVAL59,Indicates the value of PBHA[1] page table walks memory access if HWEN59 is set" "0,1" newline bitfld.long 0x00 1. "HWEN60,Enables PBHA[1] page table walks memory access" "Disabled,Enabled" bitfld.long 0x00 0. "HWEN59,Enables PBHA[0] page table walks memory access" "Disabled,Enabled" endif rgroup.long c15:0x4015++0x00 line.long 0x00 "HADFSR,Hypervisor Auxiliary Data Fault Status Syndrome Register" rgroup.long c15:0x4115++0x00 line.long 0x00 "HAIFSR,Hypervisor Auxiliary Instruction Fault Status Register" group.long c15:0x4006++0x00 line.long 0x00 "HDFAR,Hypervisor Data Fault Address Register" group.long c15:0x3154++0x00 line.long 0x00 "DLR,Debug Link Register" if (((per.l(c15:0x4025))&0xFC000000)==0x0) group.long c15:0x4025++0x00 line.long 0x00 "HSR,Hypervisor Syndrome Register" bitfld.long 0x00 26.--31. "EC,Exception class (reason)" "Unknown reason,Trapped WFI/WFE,Reserved,Trapped MCR/MRC to CP15,Trapped MCRR/MRRC to CP15,Trapped MCR/MRC to CP14,Trapped LDC/STC to CP14,Trapped Coprocessor Usage,Trapped MRC/VMRS to CP10,Reserved,Reserved,Reserved,Trapped MRRC/MCRR to CP14,Reserved,Illegal state to AArch32,Reserved,Reserved,SVC taken to Hyp,HVC executed,Trapped SMC,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Entry into Hypervisor mode Instruction Abort,Executing within Hypervisor mode Instruction Abort,PC alignment fault exception,Reserved,Entry into Hypervisor mode Data Abort,Executing within Hypervisor mode Data Abort,?..." elif (((per.l(c15:0x4025))&0xFC000000)==0x4000000) if (((per.l(c15:0x4025))&0x1000000)==0x1000000) group.long c15:0x4025++0x00 line.long 0x00 "HSR,Hypervisor Syndrome Register" bitfld.long 0x00 26.--31. "EC,Exception class (reason)" "Unknown reason,Trapped WFI/WFE,Reserved,Trapped MCR/MRC to CP15,Trapped MCRR/MRRC to CP15,Trapped MCR/MRC to CP14,Trapped LDC/STC to CP14,Trapped Coprocessor Usage,Trapped MRC/VMRS to CP10,Reserved,Reserved,Reserved,Trapped MRRC/MCRR to CP14,Reserved,Illegal state to AArch32,Reserved,Reserved,SVC taken to Hyp,HVC executed,Trapped SMC,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Entry into Hypervisor mode Instruction Abort,Executing within Hypervisor mode Instruction Abort,PC alignment fault exception,Reserved,Entry into Hypervisor mode Data Abort,Executing within Hypervisor mode Data Abort,?..." bitfld.long 0x00 25. "IL,Instruction length" "16-bit,32-bit" newline bitfld.long 0x00 24. "CV,Condition code valid" "Invalid,Valid" bitfld.long 0x00 20.--23. "COND,The condition code for the trapped instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 0. "TI,Trapped instruction" "WFI,WFE" else group.long c15:0x4025++0x00 line.long 0x00 "HSR,Hypervisor Syndrome Register" bitfld.long 0x00 26.--31. "EC,Exception class (reason)" "Unknown reason,Trapped WFI/WFE,Reserved,Trapped MCR/MRC to CP15,Trapped MCRR/MRRC to CP15,Trapped MCR/MRC to CP14,Trapped LDC/STC to CP14,Trapped Coprocessor Usage,Trapped MRC/VMRS to CP10,Reserved,Reserved,Reserved,Trapped MRRC/MCRR to CP14,Reserved,Illegal state to AArch32,Reserved,Reserved,SVC taken to Hyp,HVC executed,Trapped SMC,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Entry into Hypervisor mode Instruction Abort,Executing within Hypervisor mode Instruction Abort,PC alignment fault exception,Reserved,Entry into Hypervisor mode Data Abort,Executing within Hypervisor mode Data Abort,?..." bitfld.long 0x00 25. "IL,Instruction length" "16-bit,32-bit" newline bitfld.long 0x00 24. "CV,Condition code valid" "Invalid,Valid" bitfld.long 0x00 0. "TI,Trapped instruction" "WFI,WFE" endif elif (((per.l(c15:0x4025))&0xFC000000)==(0xC000000||0x20000000||0x14000000)) if (((per.l(c15:0x4025))&0x1000000)==0x1000000) group.long c15:0x4025++0x00 line.long 0x00 "HSR,Hypervisor Syndrome Register" bitfld.long 0x00 26.--31. "EC,Exception class (reason)" "Unknown reason,Trapped WFI/WFE,Reserved,Trapped MCR/MRC to CP15,Trapped MCRR/MRRC to CP15,Trapped MCR/MRC to CP14,Trapped LDC/STC to CP14,Trapped Coprocessor Usage,Trapped MRC/VMRS to CP10,Reserved,Reserved,Reserved,Trapped MRRC/MCRR to CP14,Reserved,Illegal state to AArch32,Reserved,Reserved,SVC taken to Hyp,HVC executed,Trapped SMC,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Entry into Hypervisor mode Instruction Abort,Executing within Hypervisor mode Instruction Abort,PC alignment fault exception,Reserved,Entry into Hypervisor mode Data Abort,Executing within Hypervisor mode Data Abort,?..." bitfld.long 0x00 25. "IL,Instruction length" "16-bit,32-bit" newline bitfld.long 0x00 24. "CV,Condition code valid" "Invalid,Valid" bitfld.long 0x00 20.--23. "COND,The condition code for the trapped instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 17.--19. "OPC2,The Opc2 value from the issued instruction" "0,1,2,3,4,5,6,7" bitfld.long 0x00 14.--16. "OPC1,The Opc1 value from the issued instruction" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 10.--13. "CRN,The CRn value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 5.--8. "RT,The Rt value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 1.--4. "CRM,The CRm value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0. "DIRECTION,Indicates the direction of the trapped instruction" "MCR,MRC/VMRS" else group.long c15:0x4025++0x00 line.long 0x00 "HSR,Hypervisor Syndrome Register" bitfld.long 0x00 26.--31. "EC,Exception class (reason)" "Unknown reason,Trapped WFI/WFE,Reserved,Trapped MCR/MRC to CP15,Trapped MCRR/MRRC to CP15,Trapped MCR/MRC to CP14,Trapped LDC/STC to CP14,Trapped Coprocessor Usage,Trapped MRC/VMRS to CP10,Reserved,Reserved,Reserved,Trapped MRRC/MCRR to CP14,Reserved,Illegal state to AArch32,Reserved,Reserved,SVC taken to Hyp,HVC executed,Trapped SMC,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Entry into Hypervisor mode Instruction Abort,Executing within Hypervisor mode Instruction Abort,PC alignment fault exception,Reserved,Entry into Hypervisor mode Data Abort,Executing within Hypervisor mode Data Abort,?..." bitfld.long 0x00 25. "IL,Instruction length" "16-bit,32-bit" newline bitfld.long 0x00 24. "CV,Condition code valid" "Invalid,Valid" bitfld.long 0x00 17.--19. "OPC2,The Opc2 value from the issued instruction" "0,1,2,3,4,5,6,7" newline bitfld.long 0x00 14.--16. "OPC1,The Opc1 value from the issued instruction" "0,1,2,3,4,5,6,7" bitfld.long 0x00 10.--13. "CRN,The CRn value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 5.--8. "RT,The Rt value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 1.--4. "CRM,The CRm value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 0. "DIRECTION,Indicates the direction of the trapped instruction" "MCR,MRC/VMRS" endif elif (((per.l(c15:0x4025))&0xFC000000)==(0x10000000||0x30000000)) if (((per.l(c15:0x4025))&0x1000000)==0x1000000) group.long c15:0x4025++0x00 line.long 0x00 "HSR,Hypervisor Syndrome Register" bitfld.long 0x00 26.--31. "EC,Exception class (reason)" "Unknown reason,Trapped WFI/WFE,Reserved,Trapped MCR/MRC to CP15,Trapped MCRR/MRRC to CP15,Trapped MCR/MRC to CP14,Trapped LDC/STC to CP14,Trapped Coprocessor Usage,Trapped MRC/VMRS to CP10,Reserved,Reserved,Reserved,Trapped MRRC/MCRR to CP14,Reserved,Illegal state to AArch32,Reserved,Reserved,SVC taken to Hyp,HVC executed,Trapped SMC,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Entry into Hypervisor mode Instruction Abort,Executing within Hypervisor mode Instruction Abort,PC alignment fault exception,Reserved,Entry into Hypervisor mode Data Abort,Executing within Hypervisor mode Data Abort,?..." bitfld.long 0x00 25. "IL,Instruction length" "16-bit,32-bit" newline bitfld.long 0x00 24. "CV,Condition code valid" "Invalid,Valid" bitfld.long 0x00 20.--23. "COND,The condition code for the trapped instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 16.--19. "OPC1,The Opc1 value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 10.--13. "RT2,The Rt2 value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 5.--8. "RT,The Rt value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 1.--4. "CRM,The CRm value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 0. "DIRECTION,Indicates the direction of the trapped instruction" "MCRR,MRRC" else group.long c15:0x4025++0x00 line.long 0x00 "HSR,Hypervisor Syndrome Register" bitfld.long 0x00 26.--31. "EC,Exception class (reason)" "Unknown reason,Trapped WFI/WFE,Reserved,Trapped MCR/MRC to CP15,Trapped MCRR/MRRC to CP15,Trapped MCR/MRC to CP14,Trapped LDC/STC to CP14,Trapped Coprocessor Usage,Trapped MRC/VMRS to CP10,Reserved,Reserved,Reserved,Trapped MRRC/MCRR to CP14,Reserved,Illegal state to AArch32,Reserved,Reserved,SVC taken to Hyp,HVC executed,Trapped SMC,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Entry into Hypervisor mode Instruction Abort,Executing within Hypervisor mode Instruction Abort,PC alignment fault exception,Reserved,Entry into Hypervisor mode Data Abort,Executing within Hypervisor mode Data Abort,?..." bitfld.long 0x00 25. "IL,Instruction length" "16-bit,32-bit" newline bitfld.long 0x00 24. "CV,Condition code valid" "Invalid,Valid" bitfld.long 0x00 16.--19. "OPC1,The Opc1 value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 10.--13. "RT2,The Rt2 value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 5.--8. "RT,The Rt value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 1.--4. "CRM,The CRm value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0. "DIRECTION,Indicates the direction of the trapped instruction" "MCRR,MRRC" endif elif (((per.l(c15:0x4025))&0xFC000000)==0x18000000) if (((per.l(c15:0x4025))&0x1000000)==0x1000000) group.long c15:0x4025++0x00 line.long 0x00 "HSR,Hypervisor Syndrome Register" bitfld.long 0x00 26.--31. "EC,Exception class (reason)" "Unknown reason,Trapped WFI/WFE,Reserved,Trapped MCR/MRC to CP15,Trapped MCRR/MRRC to CP15,Trapped MCR/MRC to CP14,Trapped LDC/STC to CP14,Trapped Coprocessor Usage,Trapped MRC/VMRS to CP10,Reserved,Reserved,Reserved,Trapped MRRC/MCRR to CP14,Reserved,Illegal state to AArch32,Reserved,Reserved,SVC taken to Hyp,HVC executed,Trapped SMC,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Entry into Hypervisor mode Instruction Abort,Executing within Hypervisor mode Instruction Abort,PC alignment fault exception,Reserved,Entry into Hypervisor mode Data Abort,Executing within Hypervisor mode Data Abort,?..." bitfld.long 0x00 25. "IL,Instruction length" "16-bit,32-bit" newline bitfld.long 0x00 24. "CV,Condition code valid" "Invalid,Valid" bitfld.long 0x00 20.--23. "COND,The condition code for the trapped instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline hexmask.long.byte 0x00 12.--19. 1. "IMM8,The immediate value from the issued instruction" bitfld.long 0x00 5.--8. "RN,The Rn value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 4. "OFFSET,Indicates whether the offset is added or subtracted" "Subtracted,Added" bitfld.long 0x00 1.--3. "AM,Addressing mode" "Imm unindexed,Imm post-indexed,Imm offset,Imm pre-indexed,Literal unindexed (A32),Reserved,Literal offset (A32),?..." newline bitfld.long 0x00 0. "DIRECTION,Indicates the direction of the trapped instruction" "STC,LDC" else group.long c15:0x4025++0x00 line.long 0x00 "HSR,Hypervisor Syndrome Register" bitfld.long 0x00 26.--31. "EC,Exception class (reason)" "Unknown reason,Trapped WFI/WFE,Reserved,Trapped MCR/MRC to CP15,Trapped MCRR/MRRC to CP15,Trapped MCR/MRC to CP14,Trapped LDC/STC to CP14,Trapped Coprocessor Usage,Trapped MRC/VMRS to CP10,Reserved,Reserved,Reserved,Trapped MRRC/MCRR to CP14,Reserved,Illegal state to AArch32,Reserved,Reserved,SVC taken to Hyp,HVC executed,Trapped SMC,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Entry into Hypervisor mode Instruction Abort,Executing within Hypervisor mode Instruction Abort,PC alignment fault exception,Reserved,Entry into Hypervisor mode Data Abort,Executing within Hypervisor mode Data Abort,?..." bitfld.long 0x00 25. "IL,Instruction length" "16-bit,32-bit" newline bitfld.long 0x00 24. "CV,Condition code valid" "Invalid,Valid" hexmask.long.byte 0x00 12.--19. 1. "IMM8,The immediate value from the issued instruction" newline bitfld.long 0x00 5.--8. "RN,The Rn value from the issued instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 4. "OFFSET,Indicates whether the offset is added or subtracted" "Subtracted,Added" newline bitfld.long 0x00 1.--3. "AM,Addressing mode" "Imm unindexed,Imm post-indexed,Imm offset,Imm pre-indexed,Literal unindexed (A32),Reserved,Literal offset (A32),?..." bitfld.long 0x00 0. "DIRECTION,Indicates the direction of the trapped instruction" "STC,LDC" endif elif (((per.l(c15:0x4025))&0xFC000000)==0x1C000000) if (((per.l(c15:0x4025))&0x1000000)==0x1000000) group.long c15:0x4025++0x00 line.long 0x00 "HSR,Hypervisor Syndrome Register" bitfld.long 0x00 26.--31. "EC,Exception class (reason)" "Unknown reason,Trapped WFI/WFE,Reserved,Trapped MCR/MRC to CP15,Trapped MCRR/MRRC to CP15,Trapped MCR/MRC to CP14,Trapped LDC/STC to CP14,Trapped Coprocessor Usage,Trapped MRC/VMRS to CP10,Reserved,Reserved,Reserved,Trapped MRRC/MCRR to CP14,Reserved,Illegal state to AArch32,Reserved,Reserved,SVC taken to Hyp,HVC executed,Trapped SMC,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Entry into Hypervisor mode Instruction Abort,Executing within Hypervisor mode Instruction Abort,PC alignment fault exception,Reserved,Entry into Hypervisor mode Data Abort,Executing within Hypervisor mode Data Abort,?..." bitfld.long 0x00 25. "IL,Instruction length" "16-bit,32-bit" newline bitfld.long 0x00 24. "CV,Condition code valid" "Invalid,Valid" bitfld.long 0x00 20.--23. "COND,The condition code for the trapped instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 5. "TA,Indicates trapped use of Advanced SIMD functionality" "Not occurred,Occurred" bitfld.long 0x00 0.--3. "COPROC,The number of the coprocessor accessed by the trapped operation" "Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,CP10,?..." else group.long c15:0x4025++0x00 line.long 0x00 "HSR,Hypervisor Syndrome Register" bitfld.long 0x00 26.--31. "EC,Exception class (reason)" "Unknown reason,Trapped WFI/WFE,Reserved,Trapped MCR/MRC to CP15,Trapped MCRR/MRRC to CP15,Trapped MCR/MRC to CP14,Trapped LDC/STC to CP14,Trapped Coprocessor Usage,Trapped MRC/VMRS to CP10,Reserved,Reserved,Reserved,Trapped MRRC/MCRR to CP14,Reserved,Illegal state to AArch32,Reserved,Reserved,SVC taken to Hyp,HVC executed,Trapped SMC,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Entry into Hypervisor mode Instruction Abort,Executing within Hypervisor mode Instruction Abort,PC alignment fault exception,Reserved,Entry into Hypervisor mode Data Abort,Executing within Hypervisor mode Data Abort,?..." bitfld.long 0x00 25. "IL,Instruction length" "16-bit,32-bit" newline bitfld.long 0x00 24. "CV,Condition code valid" "Invalid,Valid" bitfld.long 0x00 5. "TA,Indicates trapped use of Advanced SIMD functionality" "Not occurred,Occurred" newline bitfld.long 0x00 0.--3. "COPROC,The number of the coprocessor accessed by the trapped operation" "Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,CP10,?..." endif elif (((per.l(c15:0x4025))&0xFC000000)==(0x44000000||0x48000000)) group.long c15:0x4025++0x00 line.long 0x00 "HSR,Hypervisor Syndrome Register" bitfld.long 0x00 26.--31. "EC,Exception class (reason)" "Unknown reason,Trapped WFI/WFE,Reserved,Trapped MCR/MRC to CP15,Trapped MCRR/MRRC to CP15,Trapped MCR/MRC to CP14,Trapped LDC/STC to CP14,Trapped Coprocessor Usage,Trapped MRC/VMRS to CP10,Reserved,Reserved,Reserved,Trapped MRRC/MCRR to CP14,Reserved,Illegal state to AArch32,Reserved,Reserved,SVC taken to Hyp,HVC executed,Trapped SMC,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Entry into Hypervisor mode Instruction Abort,Executing within Hypervisor mode Instruction Abort,PC alignment fault exception,Reserved,Entry into Hypervisor mode Data Abort,Executing within Hypervisor mode Data Abort,?..." bitfld.long 0x00 25. "IL,Instruction length" "16-bit,32-bit" newline hexmask.long.word 0x00 0.--15. 1. "IMM16,The value of the immediate field from the HVC or SVC instruction" elif ((((per.l(c15:0x4025))&0xFC000000)==(0x80000000||0x84000000))&&(((per.l(c15:0x4025))&0x3F)==0x10)) group.long c15:0x4025++0x00 line.long 0x00 "HSR,Hypervisor Syndrome Register" bitfld.long 0x00 26.--31. "EC,Exception class (reason)" "Unknown reason,Trapped WFI/WFE,Reserved,Trapped MCR/MRC to CP15,Trapped MCRR/MRRC to CP15,Trapped MCR/MRC to CP14,Trapped LDC/STC to CP14,Trapped Coprocessor Usage,Trapped MRC/VMRS to CP10,Reserved,Reserved,Reserved,Trapped MRRC/MCRR to CP14,Reserved,Illegal state to AArch32,Reserved,Reserved,SVC taken to Hyp,HVC executed,Trapped SMC,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Entry into Hypervisor mode Instruction Abort,Executing within Hypervisor mode Instruction Abort,PC alignment fault exception,Reserved,Entry into Hypervisor mode Data Abort,Executing within Hypervisor mode Data Abort,?..." bitfld.long 0x00 10. "FNV,FAR not Valid" "HIFAR valid,HIFAR invalid" newline bitfld.long 0x00 9. "EA,External abort type" "Internal,External" bitfld.long 0x00 7. "S1PTW,Fault on the stage 2 translation of an access for a stage 1 translation table walk" "Not occurred,Occurred" newline bitfld.long 0x00 0.--5. "IFSC,Instruction Fault Status Code. SEA - Synchronous External Abort / SPE - Synchronous parity or ECC" "Address/TTBR,Address/Lvl1,Address/Lvl2,Address/Lvl3,Reserved,Translation/Lvl1,Translation/Lvl2,Translation/Lvl3,Reserved,Access flag/Lvl1,Access flag/Lvl2,Access flag/Lvl3,Reserved,Permission/Lvl1,Permission/Lvl2,Permission/Lvl3,SEA/Not ECC/Not on TTBW,Reserved,Reserved,Reserved,Reserved,SEA/Not ECC/On TTBW lvl1,SEA/Not ECC/On TTBW lvl2,SEA/Not ECC/On TTBW lvl3,SPE on mem access/Not on TTBW,Reserved,Reserved,Reserved,Reserved,SPE on mem access/On TTBW lvl1,SPE on mem access/On TTBW lvl2,SPE on mem access/On TTBW lvl3,Reserved,Reserved,Debug (only from Hypervisor mode),Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,TLB conflict abort,?..." elif ((((per.l(c15:0x4025))&0xFC000000)==(0x80000000||0x84000000))&&(((per.l(c15:0x4025))&0x3F)!=0x10)) group.long c15:0x4025++0x00 line.long 0x00 "HSR,Hypervisor Syndrome Register" bitfld.long 0x00 26.--31. "EC,Exception class (reason)" "Unknown reason,Trapped WFI/WFE,Reserved,Trapped MCR/MRC to CP15,Trapped MCRR/MRRC to CP15,Trapped MCR/MRC to CP14,Trapped LDC/STC to CP14,Trapped Coprocessor Usage,Trapped MRC/VMRS to CP10,Reserved,Reserved,Reserved,Trapped MRRC/MCRR to CP14,Reserved,Illegal state to AArch32,Reserved,Reserved,SVC taken to Hyp,HVC executed,Trapped SMC,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Entry into Hypervisor mode Instruction Abort,Executing within Hypervisor mode Instruction Abort,PC alignment fault exception,Reserved,Entry into Hypervisor mode Data Abort,Executing within Hypervisor mode Data Abort,?..." bitfld.long 0x00 9. "EA,External abort type" "Internal,External" newline bitfld.long 0x00 7. "S1PTW,Fault on the stage 2 translation of an access for a stage 1 translation table walk" "Not occurred,Occurred" bitfld.long 0x00 0.--5. "IFSC,Instruction Fault Status Code. SEA - Synchronous External Abort / SPE - Synchronous parity or ECC" "Address/TTBR,Address/Lvl1,Address/Lvl2,Address/Lvl3,Reserved,Translation/Lvl1,Translation/Lvl2,Translation/Lvl3,Reserved,Access flag/Lvl1,Access flag/Lvl2,Access flag/Lvl3,Reserved,Permission/Lvl1,Permission/Lvl2,Permission/Lvl3,SEA/Not ECC/Not on TTBW,Reserved,Reserved,Reserved,Reserved,SEA/Not ECC/On TTBW lvl1,SEA/Not ECC/On TTBW lvl2,SEA/Not ECC/On TTBW lvl3,SPE on mem access/Not on TTBW,Reserved,Reserved,Reserved,Reserved,SPE on mem access/On TTBW lvl1,SPE on mem access/On TTBW lvl2,SPE on mem access/On TTBW lvl3,Reserved,Reserved,Debug (only from Hypervisor mode),Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,TLB conflict abort,?..." elif (((per.l(c15:0x4025))&0xFC000000)==(0x88000000||0x38000000)) group.long c15:0x4025++0x00 line.long 0x00 "HSR,Hypervisor Syndrome Register" bitfld.long 0x00 26.--31. "EC,Exception class (reason)" "Unknown reason,Trapped WFI/WFE,Reserved,Trapped MCR/MRC to CP15,Trapped MCRR/MRRC to CP15,Trapped MCR/MRC to CP14,Trapped LDC/STC to CP14,Trapped Coprocessor Usage,Trapped MRC/VMRS to CP10,Reserved,Reserved,Reserved,Trapped MRRC/MCRR to CP14,Reserved,Illegal state to AArch32,Reserved,Reserved,SVC taken to Hyp,HVC executed,Trapped SMC,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Entry into Hypervisor mode Instruction Abort,Executing within Hypervisor mode Instruction Abort,PC alignment fault exception,Reserved,Entry into Hypervisor mode Data Abort,Executing within Hypervisor mode Data Abort,?..." elif (((per.l(c15:0x4025))&0xFD000000)==(0x91000000||0x95000000)) if (((per.l(c15:0x4025))&0x3F)==(0x11)) group.long c15:0x4025++0x00 line.long 0x00 "HSR,Hypervisor Syndrome Register" bitfld.long 0x00 26.--31. "EC,Exception class (reason)" "Unknown reason,Trapped WFI/WFE,Reserved,Trapped MCR/MRC to CP15,Trapped MCRR/MRRC to CP15,Trapped MCR/MRC to CP14,Trapped LDC/STC to CP14,Trapped Coprocessor Usage,Trapped MRC/VMRS to CP10,Reserved,Reserved,Reserved,Trapped MRRC/MCRR to CP14,Reserved,Illegal state to AArch32,Reserved,Reserved,SVC taken to Hyp,HVC executed,Trapped SMC,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Entry into Hypervisor mode Instruction Abort,Executing within Hypervisor mode Instruction Abort,PC alignment fault exception,Reserved,Entry into Hypervisor mode Data Abort,Executing within Hypervisor mode Data Abort,?..." bitfld.long 0x00 25. "IL,Instruction length" "16-bit,32-bit" newline bitfld.long 0x00 24. "ISV,Instruction syndrome valid" "Invalid,Valid" bitfld.long 0x00 22.--23. "SAS,Syndrome Access Size" "Byte,Halfword,Word,Doubleword" newline bitfld.long 0x00 21. "SSE,Syndrome Sign Extend" "Not required,Required" bitfld.long 0x00 16.--19. "SRT,Syndrome Register transfer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 14. "AR,Acquire/Release semantics present" "Absent,Present" bitfld.long 0x00 10.--11. "AET,Asynchronous Error Type" "UC,UEU,UEO/CE,UER" newline bitfld.long 0x00 9. "EA,External abort type" "Internal,External" bitfld.long 0x00 8. "CM,Cache maintenance" "Not generated,Generated" newline bitfld.long 0x00 7. "S1PTW,Fault on the stage 2 translation of an access for a stage 1 translation table walk" "Not occurred,Occurred" bitfld.long 0x00 6. "WNR,Write not Read as abort cause" "Read,Write" newline bitfld.long 0x00 0.--5. "DFSC,Data Fault Status Code. SEA - Synchronous External Abort / SPE - Synchronous parity or ECC" "Address/TTBR,Address/Lvl1,Address/Lvl2,Address/Lvl3,Reserved,Translation/Lvl1,Translation/Lvl2,Translation/Lvl3,Reserved,Access flag/Lvl1,Access flag/Lvl2,Access flag/Lvl3,Reserved,Permission/Lvl1,Permission/Lvl2,Permission/Lvl3,SEA/Not ECC/Not on TTBW,SError int,Reserved,Reserved,Reserved,SEA/Not ECC/On TTBW lvl1,SEA/Not ECC/On TTBW lvl2,SEA/Not ECC/On TTBW lvl3,SPE on mem access/Not on TTBW,SError int from parity/ECC err on mem access,Reserved,Reserved,Reserved,SPE on mem access/On TTBW lvl1,SPE on mem access/On TTBW lvl2,SPE on mem access/On TTBW lvl3,Reserved,Alignment fault,Debug (only from Hypervisor mode),Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,TLB conflict abort,Reserved,Reserved,Reserved,Lockdown fault,Unsupp Exclusive acc fault,?..." else group.long c15:0x4025++0x00 line.long 0x00 "HSR,Hypervisor Syndrome Register" bitfld.long 0x00 26.--31. "EC,Exception class (reason)" "Unknown reason,Trapped WFI/WFE,Reserved,Trapped MCR/MRC to CP15,Trapped MCRR/MRRC to CP15,Trapped MCR/MRC to CP14,Trapped LDC/STC to CP14,Trapped Coprocessor Usage,Trapped MRC/VMRS to CP10,Reserved,Reserved,Reserved,Trapped MRRC/MCRR to CP14,Reserved,Illegal state to AArch32,Reserved,Reserved,SVC taken to Hyp,HVC executed,Trapped SMC,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Entry into Hypervisor mode Instruction Abort,Executing within Hypervisor mode Instruction Abort,PC alignment fault exception,Reserved,Entry into Hypervisor mode Data Abort,Executing within Hypervisor mode Data Abort,?..." bitfld.long 0x00 25. "IL,Instruction length" "16-bit,32-bit" newline bitfld.long 0x00 24. "ISV,Instruction syndrome valid" "Invalid,Valid" bitfld.long 0x00 22.--23. "SAS,Syndrome Access Size" "Byte,Halfword,Word,Doubleword" newline bitfld.long 0x00 21. "SSE,Syndrome Sign Extend" "Not required,Required" bitfld.long 0x00 16.--19. "SRT,Syndrome Register transfer" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 14. "AR,Acquire/Release semantics present" "Absent,Present" bitfld.long 0x00 10. "FNV,FAR not Valid" "Valid,Invalid" newline bitfld.long 0x00 9. "EA,External abort type" "Internal,External" bitfld.long 0x00 8. "CM,Cache maintenance" "Not generated,Generated" newline bitfld.long 0x00 7. "S1PTW,Fault on the stage 2 translation of an access for a stage 1 translation table walk" "Not occurred,Occurred" bitfld.long 0x00 6. "WNR,Write not Read as abort cause" "Read,Write" newline bitfld.long 0x00 0.--5. "DFSC,Data Fault Status Code. SEA - Synchronous External Abort / SPE - Synchronous parity or ECC" "Address/TTBR,Address/Lvl1,Address/Lvl2,Address/Lvl3,Reserved,Translation/Lvl1,Translation/Lvl2,Translation/Lvl3,Reserved,Access flag/Lvl1,Access flag/Lvl2,Access flag/Lvl3,Reserved,Permission/Lvl1,Permission/Lvl2,Permission/Lvl3,SEA/Not ECC/Not on TTBW,SError int,Reserved,Reserved,Reserved,SEA/Not ECC/On TTBW lvl1,SEA/Not ECC/On TTBW lvl2,SEA/Not ECC/On TTBW lvl3,SPE on mem access/Not on TTBW,SError int from parity/ECC err on mem access,Reserved,Reserved,Reserved,SPE on mem access/On TTBW lvl1,SPE on mem access/On TTBW lvl2,SPE on mem access/On TTBW lvl3,Reserved,Alignment fault,Debug (only from Hypervisor mode),Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,TLB conflict abort,Reserved,Reserved,Reserved,Lockdown fault,Unsupp Exclusive acc fault,?..." endif elif (((per.l(c15:0x4025))&0xFD000000)==(0x90000000||0x94000000)) if (((per.l(c15:0x4025))&0x3F)==(0x11)) group.long c15:0x4025++0x00 line.long 0x00 "HSR,Hypervisor Syndrome Register" bitfld.long 0x00 26.--31. "EC,Exception class (reason)" "Unknown reason,Trapped WFI/WFE,Reserved,Trapped MCR/MRC to CP15,Trapped MCRR/MRRC to CP15,Trapped MCR/MRC to CP14,Trapped LDC/STC to CP14,Trapped Coprocessor Usage,Trapped MRC/VMRS to CP10,Reserved,Reserved,Reserved,Trapped MRRC/MCRR to CP14,Reserved,Illegal state to AArch32,Reserved,Reserved,SVC taken to Hyp,HVC executed,Trapped SMC,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Entry into Hypervisor mode Instruction Abort,Executing within Hypervisor mode Instruction Abort,PC alignment fault exception,Reserved,Entry into Hypervisor mode Data Abort,Executing within Hypervisor mode Data Abort,?..." bitfld.long 0x00 25. "IL,Instruction length" "16-bit,32-bit" newline bitfld.long 0x00 24. "ISV,Instruction syndrome valid" "Invalid,Valid" bitfld.long 0x00 10.--11. "AET,Asynchronous Error Type" "UC,UEU,UEO/CE,UER" newline bitfld.long 0x00 9. "EA,External abort type" "Internal,External" bitfld.long 0x00 8. "CM,Cache maintenance" "Not generated,Generated" newline bitfld.long 0x00 7. "S1PTW,Fault on the stage 2 translation of an access for a stage 1 translation table walk" "Not occurred,Occurred" bitfld.long 0x00 6. "WNR,Write not Read as abort cause" "Read,Write" newline bitfld.long 0x00 0.--5. "DFSC,Data Fault Status Code. SEA - Synchronous External Abort / SPE - Synchronous parity or ECC" "Address/TTBR,Address/Lvl1,Address/Lvl2,Address/Lvl3,Reserved,Translation/Lvl1,Translation/Lvl2,Translation/Lvl3,Reserved,Access flag/Lvl1,Access flag/Lvl2,Access flag/Lvl3,Reserved,Permission/Lvl1,Permission/Lvl2,Permission/Lvl3,SEA/Not ECC/Not on TTBW,SError int,Reserved,Reserved,Reserved,SEA/Not ECC/On TTBW lvl1,SEA/Not ECC/On TTBW lvl2,SEA/Not ECC/On TTBW lvl3,SPE on mem access/Not on TTBW,SError int from parity/ECC err on mem access,Reserved,Reserved,Reserved,SPE on mem access/On TTBW lvl1,SPE on mem access/On TTBW lvl2,SPE on mem access/On TTBW lvl3,Reserved,Alignment fault,Debug (only from Hypervisor mode),Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,TLB conflict abort,Reserved,Reserved,Reserved,Lockdown fault,Unsupp Exclusive acc fault,?..." else group.long c15:0x4025++0x00 line.long 0x00 "HSR,Hypervisor Syndrome Register" bitfld.long 0x00 26.--31. "EC,Exception class (reason)" "Unknown reason,Trapped WFI/WFE,Reserved,Trapped MCR/MRC to CP15,Trapped MCRR/MRRC to CP15,Trapped MCR/MRC to CP14,Trapped LDC/STC to CP14,Trapped Coprocessor Usage,Trapped MRC/VMRS to CP10,Reserved,Reserved,Reserved,Trapped MRRC/MCRR to CP14,Reserved,Illegal state to AArch32,Reserved,Reserved,SVC taken to Hyp,HVC executed,Trapped SMC,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Entry into Hypervisor mode Instruction Abort,Executing within Hypervisor mode Instruction Abort,PC alignment fault exception,Reserved,Entry into Hypervisor mode Data Abort,Executing within Hypervisor mode Data Abort,?..." bitfld.long 0x00 25. "IL,Instruction length" "16-bit,32-bit" newline bitfld.long 0x00 24. "ISV,Instruction syndrome valid" "Invalid,Valid" bitfld.long 0x00 10. "FNV,FAR not Valid" "Valid,Invalid" newline bitfld.long 0x00 9. "EA,External abort type" "Internal,External" bitfld.long 0x00 8. "CM,Cache maintenance" "Not generated,Generated" newline bitfld.long 0x00 7. "S1PTW,Fault on the stage 2 translation of an access for a stage 1 translation table walk" "Not occurred,Occurred" bitfld.long 0x00 6. "WNR,Write not Read as abort cause" "Read,Write" newline bitfld.long 0x00 0.--5. "DFSC,Data Fault Status Code. SEA - Synchronous External Abort / SPE - Synchronous parity or ECC" "Address/TTBR,Address/Lvl1,Address/Lvl2,Address/Lvl3,Reserved,Translation/Lvl1,Translation/Lvl2,Translation/Lvl3,Reserved,Access flag/Lvl1,Access flag/Lvl2,Access flag/Lvl3,Reserved,Permission/Lvl1,Permission/Lvl2,Permission/Lvl3,SEA/Not ECC/Not on TTBW,SError int,Reserved,Reserved,Reserved,SEA/Not ECC/On TTBW lvl1,SEA/Not ECC/On TTBW lvl2,SEA/Not ECC/On TTBW lvl3,SPE on mem access/Not on TTBW,SError int from parity/ECC err on mem access,Reserved,Reserved,Reserved,SPE on mem access/On TTBW lvl1,SPE on mem access/On TTBW lvl2,SPE on mem access/On TTBW lvl3,Reserved,Alignment fault,Debug (only from Hypervisor mode),Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,TLB conflict abort,Reserved,Reserved,Reserved,Lockdown fault,Unsupp Exclusive acc fault,?..." endif elif (((per.l(c15:0x4025))&0xFC080000)==(0x4C080000)) if (((per.l(c15:0x4025))&0x1000000)==(0x1000000)) group.long c15:0x4025++0x00 line.long 0x00 "HSR,Hypervisor Syndrome Register" bitfld.long 0x00 26.--31. "EC,Exception class (reason)" "Unknown reason,Trapped WFI/WFE,Reserved,Trapped MCR/MRC to CP15,Trapped MCRR/MRRC to CP15,Trapped MCR/MRC to CP14,Trapped LDC/STC to CP14,Trapped Coprocessor Usage,Trapped MRC/VMRS to CP10,Reserved,Reserved,Reserved,Trapped MRRC/MCRR to CP14,Reserved,Illegal state to AArch32,Reserved,Reserved,SVC taken to Hyp,HVC executed,Trapped SMC,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Entry into Hypervisor mode Instruction Abort,Executing within Hypervisor mode Instruction Abort,PC alignment fault exception,Reserved,Entry into Hypervisor mode Data Abort,Executing within Hypervisor mode Data Abort,?..." bitfld.long 0x00 25. "IL,Instruction length" "16-bit,32-bit" newline bitfld.long 0x00 24. "CV,Condition code valid" "Invalid,Valid" bitfld.long 0x00 20.--23. "COND,The condition code for the trapped instruction" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 19. "CCKNOWNPASS,Trapped instruction" "Unconditional,Conditional" else group.long c15:0x4025++0x00 line.long 0x00 "HSR,Hypervisor Syndrome Register" bitfld.long 0x00 26.--31. "EC,Exception class (reason)" "Unknown reason,Trapped WFI/WFE,Reserved,Trapped MCR/MRC to CP15,Trapped MCRR/MRRC to CP15,Trapped MCR/MRC to CP14,Trapped LDC/STC to CP14,Trapped Coprocessor Usage,Trapped MRC/VMRS to CP10,Reserved,Reserved,Reserved,Trapped MRRC/MCRR to CP14,Reserved,Illegal state to AArch32,Reserved,Reserved,SVC taken to Hyp,HVC executed,Trapped SMC,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Entry into Hypervisor mode Instruction Abort,Executing within Hypervisor mode Instruction Abort,PC alignment fault exception,Reserved,Entry into Hypervisor mode Data Abort,Executing within Hypervisor mode Data Abort,?..." bitfld.long 0x00 25. "IL,Instruction length" "16-bit,32-bit" newline bitfld.long 0x00 24. "CV,Condition code valid" "Invalid,Valid" bitfld.long 0x00 19. "CCKNOWNPASS,Trapped instruction" "Unconditional,Conditional" endif elif (((per.l(c15:0x4025))&0xFC080000)==(0x4C000000)) group.long c15:0x4025++0x00 line.long 0x00 "HSR,Hypervisor Syndrome Register" bitfld.long 0x00 26.--31. "EC,Exception class (reason)" "Unknown reason,Trapped WFI/WFE,Reserved,Trapped MCR/MRC to CP15,Trapped MCRR/MRRC to CP15,Trapped MCR/MRC to CP14,Trapped LDC/STC to CP14,Trapped Coprocessor Usage,Trapped MRC/VMRS to CP10,Reserved,Reserved,Reserved,Trapped MRRC/MCRR to CP14,Reserved,Illegal state to AArch32,Reserved,Reserved,SVC taken to Hyp,HVC executed,Trapped SMC,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Entry into Hypervisor mode Instruction Abort,Executing within Hypervisor mode Instruction Abort,PC alignment fault exception,Reserved,Entry into Hypervisor mode Data Abort,Executing within Hypervisor mode Data Abort,?..." bitfld.long 0x00 25. "IL,Instruction length" "16-bit,32-bit" newline bitfld.long 0x00 19. "CCKNOWNPASS,Trapped instruction" "Unconditional,Conditional" else group.long c15:0x4025++0x00 line.long 0x00 "HSR,Hypervisor Syndrome Register" bitfld.long 0x00 26.--31. "EC,Exception class (reason)" "Unknown reason,Trapped WFI/WFE,Reserved,Trapped MCR/MRC to CP15,Trapped MCRR/MRRC to CP15,Trapped MCR/MRC to CP14,Trapped LDC/STC to CP14,Trapped Coprocessor Usage,Trapped MRC/VMRS to CP10,Reserved,Reserved,Reserved,Trapped MRRC/MCRR to CP14,Reserved,Illegal state to AArch32,Reserved,Reserved,SVC taken to Hyp,HVC executed,Trapped SMC,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Entry into Hypervisor mode Instruction Abort,Executing within Hypervisor mode Instruction Abort,PC alignment fault exception,Reserved,Entry into Hypervisor mode Data Abort,Executing within Hypervisor mode Data Abort,?..." bitfld.long 0x00 25. "IL,Instruction length" "16-bit,32-bit" newline hexmask.long 0x00 0.--24. 1. "ISS,Instruction specific syndrome" endif rgroup.long c15:0x4115++0x00 line.long 0x00 "HAIFSR,Hypervisor Auxiliary Instruction Fault Status Register" group.long c15:0x4206++0x00 line.long 0x00 "HIFAR,Hypervisor Instruction Fault Address Register" group.long c15:0x4406++0x00 line.long 0x00 "HPFAR,Hypervisor IPA Fault Address Register" hexmask.long 0x00 4.--31. 0x10 "FIPA[39:12],Bits [39:12] of the faulting intermediate physical address" tree.open "Hypervisor Memory Attribute Indirection Registers" if corename()=="CORTEXA75" if (((per.l(c15:0x0202))&0x80000000)==0x80000000) group.long c15:0x402A++0x00 line.long 0x00 "HMAIR0,Hypervisor Memory Attribute Indirection Register 0" bitfld.long 0x00 28.--31. "ATTR3H,Attribute 3 High" "Device memory,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Non-Cacheable,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient" bitfld.long 0x00 24.--27. "ATTR3L,Attribute 3 Low" "Device-nGnRnE/---,---/Inner Write-through transient,---/Inner Write-through transient,---/Inner Write-through transient,Device-nGnRE/Inner Non-Cacheable,---/Inner Write-back transient,---/Inner Write-back transient,---/Inner Write-back transient,Device-nGRE memory/Inner Write-through,---/Inner Write-through non-transient,---/Inner Write-through non-transient,---/Inner Write-through non-transient,Reserved,---/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient" newline bitfld.long 0x00 20.--23. "ATTR2H,Attribute 2 High" "Device memory,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Non-Cacheable,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient" bitfld.long 0x00 16.--19. "ATTR2L,Attribute 2 Low" "Device-nGnRnE/---,---/Inner Write-through transient,---/Inner Write-through transient,---/Inner Write-through transient,Device-nGnRE/Inner Non-Cacheable,---/Inner Write-back transient,---/Inner Write-back transient,---/Inner Write-back transient,Device-nGRE memory/Inner Write-through,---/Inner Write-through non-transient,---/Inner Write-through non-transient,---/Inner Write-through non-transient,Reserved,---/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient" newline bitfld.long 0x00 12.--15. "ATTR1H,Attribute 1 High" "Device memory,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Non-Cacheable,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient" bitfld.long 0x00 8.--11. "ATTR1L,Attribute 1 Low" "Device-nGnRnE/---,---/Inner Write-through transient,---/Inner Write-through transient,---/Inner Write-through transient,Device-nGnRE/Inner Non-Cacheable,---/Inner Write-back transient,---/Inner Write-back transient,---/Inner Write-back transient,Device-nGRE memory/Inner Write-through,---/Inner Write-through non-transient,---/Inner Write-through non-transient,---/Inner Write-through non-transient,Reserved,---/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient" newline bitfld.long 0x00 4.--7. "ATTR0H,Attribute 0 High" "Device memory,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Non-Cacheable,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient" bitfld.long 0x00 0.--3. "ATTR0L,Attribute 0 Low" "Device-nGnRnE/---,---/Inner Write-through transient,---/Inner Write-through transient,---/Inner Write-through transient,Device-nGnRE/Inner Non-Cacheable,---/Inner Write-back transient,---/Inner Write-back transient,---/Inner Write-back transient,Device-nGRE memory/Inner Write-through,---/Inner Write-through non-transient,---/Inner Write-through non-transient,---/Inner Write-through non-transient,Reserved,---/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient" group.long c15:0x412A++0x00 line.long 0x00 "HMAIR1,Hypervisor Memory Attribute Indirection Register 1" bitfld.long 0x00 28.--31. "ATTR7H,Attribute 7 High" "Device memory,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Non-Cacheable,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient" bitfld.long 0x00 24.--27. "ATTR7L,Attribute 7 Low" "Device-nGnRnE/---,---/Inner Write-through transient,---/Inner Write-through transient,---/Inner Write-through transient,Device-nGnRE/Inner Non-Cacheable,---/Inner Write-back transient,---/Inner Write-back transient,---/Inner Write-back transient,Device-nGRE memory/Inner Write-through,---/Inner Write-through non-transient,---/Inner Write-through non-transient,---/Inner Write-through non-transient,Reserved,---/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient" newline bitfld.long 0x00 20.--23. "ATTR6H,Attribute 6 High" "Device memory,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Non-Cacheable,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient" bitfld.long 0x00 16.--19. "ATTR6L,Attribute 6 Low" "Device-nGnRnE/---,---/Inner Write-through transient,---/Inner Write-through transient,---/Inner Write-through transient,Device-nGnRE/Inner Non-Cacheable,---/Inner Write-back transient,---/Inner Write-back transient,---/Inner Write-back transient,Device-nGRE memory/Inner Write-through,---/Inner Write-through non-transient,---/Inner Write-through non-transient,---/Inner Write-through non-transient,Reserved,---/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient" newline bitfld.long 0x00 12.--15. "ATTR5H,Attribute 5 High" "Device memory,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Non-Cacheable,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient" bitfld.long 0x00 8.--11. "ATTR5L,Attribute 5 Low" "Device-nGnRnE/---,---/Inner Write-through transient,---/Inner Write-through transient,---/Inner Write-through transient,Device-nGnRE/Inner Non-Cacheable,---/Inner Write-back transient,---/Inner Write-back transient,---/Inner Write-back transient,Device-nGRE memory/Inner Write-through,---/Inner Write-through non-transient,---/Inner Write-through non-transient,---/Inner Write-through non-transient,Reserved,---/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient" newline bitfld.long 0x00 4.--7. "ATTR4H,Attribute 4 High" "Device memory,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Non-Cacheable,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient" bitfld.long 0x00 0.--3. "ATTR4L,Attribute 4 Low" "Device-nGnRnE/---,---/Inner Write-through transient,---/Inner Write-through transient,---/Inner Write-through transient,Device-nGnRE/Inner Non-Cacheable,---/Inner Write-back transient,---/Inner Write-back transient,---/Inner Write-back transient,Device-nGRE memory/Inner Write-through,---/Inner Write-through non-transient,---/Inner Write-through non-transient,---/Inner Write-through non-transient,Reserved,---/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient" else rgroup.long c15:0x402A++0x00 line.long 0x00 "HMAIR0,Hypervisor Memory Attribute Indirection Register 0" rgroup.long c15:0x412A++0x00 line.long 0x00 "HMAIR1,Hypervisor Memory Attribute Indirection Register 1" endif elif corename()=="CORTEXA55" if (((per.l(c15:0x0202))&0x80000000)==0x80000000) group.long c15:0x402A++0x00 line.long 0x00 "HMAIR0,Hypervisor Memory Attribute Indirection Register 0" bitfld.long 0x00 28.--31. "ATTR3H,Attribute 3 High" "Device memory,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Non-Cacheable,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient" bitfld.long 0x00 24.--27. "ATTR3L,Attribute 3 Low" "Device-nGnRnE/---,---/Inner Write-through transient,---/Inner Write-through transient,---/Inner Write-through transient,Device-nGnRE/Inner Non-Cacheable,---/Inner Write-back transient,---/Inner Write-back transient,---/Inner Write-back transient,Device-nGRE memory/Inner Write-through,---/Inner Write-through non-transient,---/Inner Write-through non-transient,---/Inner Write-through non-transient,Device-GRE memory/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient" newline bitfld.long 0x00 20.--23. "ATTR2H,Attribute 2 High" "Device memory,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Non-Cacheable,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient" bitfld.long 0x00 16.--19. "ATTR2L,Attribute 2 Low" "Device-nGnRnE/---,---/Inner Write-through transient,---/Inner Write-through transient,---/Inner Write-through transient,Device-nGnRE/Inner Non-Cacheable,---/Inner Write-back transient,---/Inner Write-back transient,---/Inner Write-back transient,Device-nGRE memory/Inner Write-through,---/Inner Write-through non-transient,---/Inner Write-through non-transient,---/Inner Write-through non-transient,Device-GRE memory/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient" newline bitfld.long 0x00 12.--15. "ATTR1H,Attribute 1 High" "Device memory,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Non-Cacheable,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient" bitfld.long 0x00 8.--11. "ATTR1L,Attribute 1 Low" "Device-nGnRnE/---,---/Inner Write-through transient,---/Inner Write-through transient,---/Inner Write-through transient,Device-nGnRE/Inner Non-Cacheable,---/Inner Write-back transient,---/Inner Write-back transient,---/Inner Write-back transient,Device-nGRE memory/Inner Write-through,---/Inner Write-through non-transient,---/Inner Write-through non-transient,---/Inner Write-through non-transient,Device-GRE memory/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient" newline bitfld.long 0x00 4.--7. "ATTR0H,Attribute 0 High" "Device memory,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Non-Cacheable,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient" bitfld.long 0x00 0.--3. "ATTR0L,Attribute 0 Low" "Device-nGnRnE/---,---/Inner Write-through transient,---/Inner Write-through transient,---/Inner Write-through transient,Device-nGnRE/Inner Non-Cacheable,---/Inner Write-back transient,---/Inner Write-back transient,---/Inner Write-back transient,Device-nGRE memory/Inner Write-through,---/Inner Write-through non-transient,---/Inner Write-through non-transient,---/Inner Write-through non-transient,Device-GRE memory/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient" group.long c15:0x412A++0x00 line.long 0x00 "HMAIR1,Hypervisor Memory Attribute Indirection Register 1" bitfld.long 0x00 28.--31. "ATTR7H,Attribute 7 High" "Device memory,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Non-Cacheable,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient" bitfld.long 0x00 24.--27. "ATTR7L,Attribute 7 Low" "Device-nGnRnE/---,---/Inner Write-through transient,---/Inner Write-through transient,---/Inner Write-through transient,Device-nGnRE/Inner Non-Cacheable,---/Inner Write-back transient,---/Inner Write-back transient,---/Inner Write-back transient,Device-nGRE memory/Inner Write-through,---/Inner Write-through non-transient,---/Inner Write-through non-transient,---/Inner Write-through non-transient,Device-GRE memory/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient" newline bitfld.long 0x00 20.--23. "ATTR6H,Attribute 6 High" "Device memory,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Non-Cacheable,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient" bitfld.long 0x00 16.--19. "ATTR6L,Attribute 6 Low" "Device-nGnRnE/---,---/Inner Write-through transient,---/Inner Write-through transient,---/Inner Write-through transient,Device-nGnRE/Inner Non-Cacheable,---/Inner Write-back transient,---/Inner Write-back transient,---/Inner Write-back transient,Device-nGRE memory/Inner Write-through,---/Inner Write-through non-transient,---/Inner Write-through non-transient,---/Inner Write-through non-transient,Device-GRE memory/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient" newline bitfld.long 0x00 12.--15. "ATTR5H,Attribute 5 High" "Device memory,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Non-Cacheable,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient" bitfld.long 0x00 8.--11. "ATTR5L,Attribute 5 Low" "Device-nGnRnE/---,---/Inner Write-through transient,---/Inner Write-through transient,---/Inner Write-through transient,Device-nGnRE/Inner Non-Cacheable,---/Inner Write-back transient,---/Inner Write-back transient,---/Inner Write-back transient,Device-nGRE memory/Inner Write-through,---/Inner Write-through non-transient,---/Inner Write-through non-transient,---/Inner Write-through non-transient,Device-GRE memory/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient" newline bitfld.long 0x00 4.--7. "ATTR4H,Attribute 4 High" "Device memory,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Write-through transient,Normal Memory/Outer Non-Cacheable,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-back transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-through non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient,Normal Memory/Outer Write-back non-transient" bitfld.long 0x00 0.--3. "ATTR4L,Attribute 4 Low" "Device-nGnRnE/---,---/Inner Write-through transient,---/Inner Write-through transient,---/Inner Write-through transient,Device-nGnRE/Inner Non-Cacheable,---/Inner Write-back transient,---/Inner Write-back transient,---/Inner Write-back transient,Device-nGRE memory/Inner Write-through,---/Inner Write-through non-transient,---/Inner Write-through non-transient,---/Inner Write-through non-transient,Device-GRE memory/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient,---/Inner Write-back non-transient" else rgroup.long c15:0x402A++0x00 line.long 0x00 "HMAIR0,Hypervisor Memory Attribute Indirection Register 0" rgroup.long c15:0x412A++0x00 line.long 0x00 "HMAIR1,Hypervisor Memory Attribute Indirection Register 1" endif endif rgroup.long c15:0x403A++0x00 line.long 0x00 "HAMAIR0,Hypervisor Auxiliary Memory Attribute Indirection Register 0" rgroup.long c15:0x413A++0x00 line.long 0x00 "HAMAIR1,Hypervisor Auxiliary Memory Attribute Indirection Register 1" tree.end newline group.long c15:0x400C++0x00 line.long 0x00 "HVBAR,Hypervisor Vector Base Address Register" hexmask.long 0x00 5.--31. 0x20 "VBA,Vector Base Address" tree.end tree "Cache Control and Configuration" rgroup.long c15:0x000F++0x00 line.long 0x00 "CPUCFR,CPU Configuration Register" bitfld.long 0x00 2. "SCU,Indicates whether the SCU is present or not" "Present,?..." bitfld.long 0x00 0.--1. "ECC,Indicates whether ECC is present or not" "Not present,Present,?..." group.long c15:0x072F++0x00 line.long 0x00 "CPUPWRCTLR,Power Control Register" bitfld.long 0x00 10.--12. "SIMD_RET_CTRL,Advanced SIMD and floating-point retention control. Specifies the number of Architectural Timer ticks required before retention entry" "Disabled,2 AT ticks,8 AT ticks,32 AT ticks,64 AT ticks,128 AT ticks,256 AT ticks,512 AT ticks" bitfld.long 0x00 7.--9. "WFE_RET_CTRL,CPU WFE retention control. Specifies the number of Architectural Timer ticks required before retention entry" "Disabled,2 AT ticks,8 AT ticks,32 AT ticks,64 AT ticks,128 AT ticks,256 AT ticks,512 AT ticks" bitfld.long 0x00 4.--6. "WFI_RET_CTRL,CPU WFI retention control. Specifies the number of Architectural Timer ticks required before retention entry" "Disabled,2 AT ticks,8 AT ticks,32 AT ticks,64 AT ticks,128 AT ticks,256 AT ticks,512 AT ticks" newline bitfld.long 0x00 0. "CORE_PWRDN_EN,Indicates to the power controller if the CPU wants to power down when it enters WFI state" "Not requested,Requested" rgroup.long c15:0x0100++0x00 line.long 0x00 "CTR,Cache Type Register" bitfld.long 0x00 24.--27. "CWG,Cache writeback granule size" "Reserved,Reserved,Reserved,Reserved,16 words,?..." bitfld.long 0x00 20.--23. "ERG,Exclusives reservation granule size" "Reserved,Reserved,Reserved,Reserved,16 words,?..." bitfld.long 0x00 16.--19. "DMINLINE,Smallest data cache line size" "Reserved,Reserved,Reserved,Reserved,16 words,?..." newline bitfld.long 0x00 14.--15. "L1IP,Instruction cache policy" "Reserved,Reserved,VIPT,?..." bitfld.long 0x00 0.--3. "IMINLINE,I-Cache Minimum Line Size" "Reserved,Reserved,Reserved,Reserved,16 words,?..." if (((per.l(c15:0x2000))&0x0E)==0x00) group.long c15:0x2000++0x00 line.long 0x00 "CSSELR,Cache Size Selection Register" bitfld.long 0x00 1.--3. "LEVEL,Cache level of required cache" "Level 1,Level 2,Level 3,?..." bitfld.long 0x00 0. "IND,Instruction/Not Data" "Data,Instruction" else group.long c15:0x2000++0x00 line.long 0x00 "CSSELR,Cache Size Selection Register" bitfld.long 0x00 1.--3. "LEVEL,Cache level of required cache" "Level 1,Level 2,Level 3,?..." bitfld.long 0x00 0. "IND,Instruction/Not Data" "Unified,?..." endif rgroup.long c15:0x1000++0x00 line.long 0x00 "CCSIDR,Cache size ID Register" bitfld.long 0x00 31. "WT,Indicates whether the selected cache level supports Write-Through" "Not Supported,?..." bitfld.long 0x00 30. "WB,Indicates whether the selected cache level supports Write-Back" "Not Supported,Supported" bitfld.long 0x00 29. "RA,Indicates whether the selected cache level supports read-allocation" "Not Supported,Supported" newline bitfld.long 0x00 28. "WA,Indicates whether the selected cache level supports write-allocation" "Not Supported,Supported" hexmask.long.word 0x00 13.--27. 1. 1. "SETS,Number of Sets" hexmask.long.word 0x00 3.--12. 1. 1. "ASSOC,Associativity" newline bitfld.long 0x00 0.--2. "LSIZE,Line Size" "Reserved,Reserved,64 bytes,?..." if corename()=="CORTEXA75" rgroup.long c15:0x1100++0x00 line.long 0x00 "CLIDR,Cache Level ID Register" bitfld.long 0x00 30.--31. "ICB,Inner cache boundary" "Reserved,Reserved,L2 highest,L3 highest" bitfld.long 0x00 27.--29. "LOUU,Level of Unification Uniprocessor" "Not required,?..." bitfld.long 0x00 24.--26. "LOC,Level of Coherency" "Reserved,Reserved,No L3 cache,L3 cache,?..." newline bitfld.long 0x00 21.--23. "LOUIS,Level of Unification Inner Shareable" "Not required,?..." bitfld.long 0x00 6.--8. "CTYPE3,Cache type for levels 3" "No cache,Reserved,Reserved,Reserved,L3 cache,?..." bitfld.long 0x00 3.--5. "CTYPE2,Cache type for levels 2" "Reserved,Reserved,Reserved,Reserved,Unified,?..." newline bitfld.long 0x00 0.--2. "CTYPE1,Cache type for levels 1" "Reserved,Reserved,Reserved,Separate I/D,?..." elif corename()=="CORTEXA55" rgroup.long c15:0x1100++0x00 line.long 0x00 "CLIDR,Cache Level ID Register" bitfld.long 0x00 30.--31. "ICB,Inner cache boundary" "Reserved,Reserved,L2 highest,L3 highest" bitfld.long 0x00 27.--29. "LOUU,Level of Unification Uniprocessor" "Not required,?..." bitfld.long 0x00 24.--26. "LOC,Level of Coherency" "Reserved,No cache,L2 or L3 cache,L2 and L3 cache,?..." newline bitfld.long 0x00 21.--23. "LOUIS,Level of Unification Inner Shareable" "Not required,?..." bitfld.long 0x00 6.--8. "CTYPE3,Cache type for levels 3" "L2 or L3 cache,Reserved,Reserved,Reserved,L2 and L3 cache,?..." bitfld.long 0x00 3.--5. "CTYPE2,Cache type for levels 2" "No cache,Reserved,Reserved,Reserved,Unified,?..." newline bitfld.long 0x00 0.--2. "CTYPE1,Cache type for levels 1" "Reserved,Reserved,Reserved,Separate I/D,?..." endif tree "Level 1 memory system" rgroup.long c15:0x600F++0x00 line.long 0x00 "CDBGDR0,Data Register 0" rgroup.long c15:0x610F++0x00 line.long 0x00 "CDBGDR1,Data Register 1" rgroup.long c15:0x620F++0x00 line.long 0x00 "CDBGDR2,Data Register 2" wgroup.long c15:0x602F++0x00 line.long 0x00 "CDBGDCT,Data Cache Tag Read Operation Register" wgroup.long c15:0x612F++0x00 line.long 0x00 "CDBGICT,Instruction Cache Tag Read Operation Register" wgroup.long c15:0x622F++0x00 line.long 0x00 "CDBGTT,TLB Tag Read Operation Register" wgroup.long c15:0x604F++0x00 line.long 0x00 "CDBGDCD,Data Cache Data Read Operation Register" wgroup.long c15:0x614F++0x00 line.long 0x00 "CDBGICD,Instruction Cache Data Read Operation Register" wgroup.long c15:0x624F++0x00 line.long 0x00 "CDBGTD,TLB Data Read Operation Register" tree.end tree.end tree "System Performance Monitor" group.long c15:0x00C9++0x00 line.long 0x00 "PMCR,Performance Monitors Control Register" hexmask.long.byte 0x00 24.--31. 1. "IMP,Implementer code" hexmask.long.byte 0x00 16.--23. 1. "IDCODE,Identification code" bitfld.long 0x00 11.--15. "N,Number of counters implemented" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 6. "LC,Long cycle counter enable" "Disabled,Enabled" newline bitfld.long 0x00 5. "DP,Disable CCNT when prohibited" "No,Yes" bitfld.long 0x00 4. "X,Export Enable" "Disabled,Enabled" bitfld.long 0x00 3. "D,Clock Divider" "Every cycle,64th cycle" bitfld.long 0x00 2. "C,Clock Counter Reset" "No reset,Reset" newline bitfld.long 0x00 1. "P,Performance Counter Reset" "No reset,Reset" bitfld.long 0x00 0. "E,All Counters Enable" "Disabled,Enabled" group.long c15:0x01C9++0x00 line.long 0x00 "PMCNTENSET,Performance Monitors Count Enable Set Register" bitfld.long 0x00 31. "C,PMCCNTR Overflow Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 5. "P5,Event counter PMN 5 enable bit" "Disabled,Enabled" bitfld.long 0x00 4. "P4,Event counter PMN 4 enable bit" "Disabled,Enabled" newline bitfld.long 0x00 3. "P3,Event counter PMN 3 enable bit" "Disabled,Enabled" bitfld.long 0x00 2. "P2,Event counter PMN 2 enable bit" "Disabled,Enabled" bitfld.long 0x00 1. "P1,Event counter PMN 1 enable bit" "Disabled,Enabled" newline bitfld.long 0x00 0. "P0,Event counter PMN 0 enable bit" "Disabled,Enabled" group.long c15:0x02C9++0x00 line.long 0x00 "PMCNTENCLR,Performance Monitors Count Enable Clear Register" bitfld.long 0x00 31. "C,PMCCNTR Overflow Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 5. "P5,Event counter PMN 5 enable bit" "Disabled,Enabled" bitfld.long 0x00 4. "P4,Event counter PMN 4 enable bit" "Disabled,Enabled" newline bitfld.long 0x00 3. "P3,Event counter PMN 3 enable bit" "Disabled,Enabled" bitfld.long 0x00 2. "P2,Event counter PMN 2 enable bit" "Disabled,Enabled" bitfld.long 0x00 1. "P1,Event counter PMN 1 enable bit" "Disabled,Enabled" newline bitfld.long 0x00 0. "P0,Event counter PMN 0 enable bit" "Disabled,Enabled" group.long c15:0x03C9++0x00 line.long 0x00 "PMOVSR,Performance Monitors Overflow Status Flags Register" eventfld.long 0x00 31. "C,PMCCNTR overflow" "No overflow,Overflow" eventfld.long 0x00 5. "P5,PMN5 overflow" "No overflow,Overflow" eventfld.long 0x00 4. "P4,PMN4 overflow" "No overflow,Overflow" newline eventfld.long 0x00 3. "P3,PMN3 overflow" "No overflow,Overflow" eventfld.long 0x00 2. "P2,PMN2 overflow" "No overflow,Overflow" eventfld.long 0x00 1. "P1,PMN1 overflow" "No overflow,Overflow" newline eventfld.long 0x00 0. "P0,PMN0 overflow" "No overflow,Overflow" wgroup.long c15:0x04C9++0x00 line.long 0x00 "PMSWINC,Performance Monitors Software Increment Register" bitfld.long 0x00 5. "P5,PMN5 software increment" "Disabled,Enabled" bitfld.long 0x00 4. "P4,PMN4 software increment" "Disabled,Enabled" bitfld.long 0x00 3. "P3,PMN3 software increment" "Disabled,Enabled" newline bitfld.long 0x00 2. "P2,PMN2 software increment" "Disabled,Enabled" bitfld.long 0x00 1. "P1,PMN1 software increment" "Disabled,Enabled" bitfld.long 0x00 0. "P0,PMN0 software increment" "Disabled,Enabled" group.long c15:0x05C9++0x00 line.long 0x00 "PMSELR,Performance Monitors Event Counter Selection Register" bitfld.long 0x00 0.--4. "SEL,Current event counter select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" tree.open "Common Event Identification Registers" rgroup.long c15:0x06C9++0x00 line.long 0x00 "PMCEID0,Performance Monitors Common Event Identification Register 0" bitfld.long 0x00 31. "L1D_CACHE_ALLOCATE,Level 1 data cache allocate" "Not implemented,Implemented" bitfld.long 0x00 30. "CHAIN,Chain" "Not implemented,Implemented" bitfld.long 0x00 29. "BUS_CYCLES,Bus cycle" "Not implemented,Implemented" newline bitfld.long 0x00 28. "TTBR_WRITE_RETIRED,TTBR write retired" "Not implemented,Implemented" bitfld.long 0x00 27. "INST_SPEC,Instruction speculatively executed" "Not implemented,Implemented" bitfld.long 0x00 26. "MEMORY_ERROR,Local memory error" "Not implemented,Implemented" newline bitfld.long 0x00 25. "BUS_ACCESS,Bus access" "Not implemented,Implemented" bitfld.long 0x00 24. "L2D_CACHE_WB,Level 2 data cache write-back" "Not implemented,Implemented" bitfld.long 0x00 23. "L2D_CACHE_REFILL,Level 2 data cache refill" "Not implemented,Implemented" newline bitfld.long 0x00 22. "L2D_CACHE,Level 2 data cache access" "Not implemented,Implemented" bitfld.long 0x00 21. "L1D_CACHE_WB,Level 1 data cache write-back" "Not implemented,Implemented" bitfld.long 0x00 20. "L1I_CACHE,Level 1 instruction cache access" "Not implemented,Implemented" newline bitfld.long 0x00 19. "MEM_ACCESS,Data memory access" "Not implemented,Implemented" bitfld.long 0x00 18. "BR_PRED,Predictable branch speculatively executed" "Not implemented,Implemented" bitfld.long 0x00 17. "CPU_CYCLES,CPU Cycle" "Not implemented,Implemented" newline bitfld.long 0x00 16. "BR_MIS_PRED,Mispredicted or not predicted branch speculatively executed" "Not implemented,Implemented" bitfld.long 0x00 15. "UNALIGNED_LDST_RETIRED,UNALIGNED_LDST_RETIRED" "Not implemented,Implemented" bitfld.long 0x00 14. "BR_RETURN_RETIRED,Instruction architecturally executed condition check pass procedure return" "Not implemented,Implemented" newline bitfld.long 0x00 13. "BR_IMMED_RETIRED,Instruction architecturally executed immediate branch" "Not implemented,Implemented" bitfld.long 0x00 12. "PC_WRITE_RETIRED,Instruction architecturally executed condition check pass software change of the PC" "Not implemented,Implemented" bitfld.long 0x00 11. "CID_WRITE_RETIRED,Instruction architecturally executed condition check pass write to CONTEXTIDR" "Not implemented,Implemented" newline bitfld.long 0x00 10. "EXC_RETURN,Instruction architecturally executed condition check pass exception return" "Not implemented,Implemented" bitfld.long 0x00 9. "EXC_TAKEN,Exception taken" "Not implemented,Implemented" bitfld.long 0x00 8. "INST_RETIRED,Instruction architecturally executed" "Not implemented,Implemented" newline bitfld.long 0x00 7. "ST_RETIRED,Instruction architecturally executed condition check pass store" "Not implemented,Implemented" bitfld.long 0x00 6. "LD_RETIRED,Instruction architecturally executed condition check pass load" "Not implemented,Implemented" bitfld.long 0x00 5. "L1D_TLB_REFILL,Level 1 data TLB refill" "Not implemented,Implemented" newline bitfld.long 0x00 4. "L1D_CACHE,Level 1 data cache access" "Not implemented,Implemented" bitfld.long 0x00 3. "L1D_CACHE_REFILL,Level 1 data cache refill" "Not implemented,Implemented" bitfld.long 0x00 2. "L1I_TLB_REFILL,Level 1 instruction TLB refill" "Not implemented,Implemented" newline bitfld.long 0x00 1. "L1I_CACHE_REFILL,Level 1 instruction cache refill" "Not implemented,Implemented" bitfld.long 0x00 0. "SW_INCR,Instruction architecturally executed condition check pass software increment" "Not implemented,Implemented" if corename()=="CORTEXA75" rgroup.long c15:0x07C9++0x00 line.long 0x00 "PMCEID1,Performance Monitors Common Event Identification Register 1" bitfld.long 0x00 24. "REMOTE_ACCESS,Access to another socket in a multi-socket system" "Not implemented,Implemented" bitfld.long 0x00 23. "LL_CACHE_MISS_RD,Last Level cache miss read" "Not implemented,Implemented" bitfld.long 0x00 22. "LL_CACHE_RD,Last Level cache access read" "Not implemented,Implemented" newline bitfld.long 0x00 21. "ITLB_WALK,Access to instruction TLB that caused a page table walk" "Not implemented,Implemented" bitfld.long 0x00 20. "DTLB_WALK,Access to data TLB that caused a page table walk" "Not implemented,Implemented" bitfld.long 0x00 16. "L2I_TLB,Attributable Level 2 instruction TLB access" "Not implemented,Implemented" newline bitfld.long 0x00 15. "L2D_TLB,Attributable Level 2 data or unified TLB access" "Not implemented,Implemented" bitfld.long 0x00 13. "L2D_TLB_REFILL,Attributable Level 2 data or unified TLB refill" "Not implemented,Implemented" bitfld.long 0x00 11. "L3D_CACHE,Attributable Level 3 data or unified cache access" "Not implemented,Implemented" newline bitfld.long 0x00 10. "L3D_CACHE_REFILL,Attributable Level 3 data or unified cache refill" "Not implemented,Implemented" bitfld.long 0x00 9. "L3D_CACHE_ALLOCATE,Attributable Level 3 data or unified cache allocation without refill" "Not implemented,Implemented" bitfld.long 0x00 6. "L1I_TLB,Level 1 instruction TLB access" "Not implemented,Implemented" newline bitfld.long 0x00 5. "L1D_TLB,Level 1 data or unified TLB access" "Not implemented,Implemented" bitfld.long 0x00 4. "STALL_BACKEND,No operation issued due to backend" "Not implemented,Implemented" bitfld.long 0x00 3. "STALL_FRONTEND,No operation issued due to the frontend" "Not implemented,Implemented" newline bitfld.long 0x00 1. "BR_RETIRED,Instruction architecturally executed branch" "Not implemented,Implemented" bitfld.long 0x00 0. "L2D_CACHE_ALLOCATE,Level 2 data cache allocate" "Not implemented,Implemented" elif corename()=="CORTEXA55" rgroup.long c15:0x07C9++0x00 line.long 0x00 "PMCEID1,Performance Monitors Common Event Identification Register 1" bitfld.long 0x00 24. "REMOTE_ACCESS,Access to another socket in a multi-socket system" "Not implemented,Implemented" bitfld.long 0x00 23. "LL_CACHE_MISS_RD,Last Level cache miss read" "Not implemented,Implemented" bitfld.long 0x00 22. "LL_CACHE_RD,Last Level cache access read" "Not implemented,Implemented" newline bitfld.long 0x00 21. "ITLB_WALK,Access to instruction TLB that caused a page table walk" "Not implemented,Implemented" bitfld.long 0x00 20. "DTLB_WALK,Access to data TLB that caused a page table walk" "Not implemented,Implemented" bitfld.long 0x00 16. "L2I_TLB,Attributable Level 2 instruction TLB access" "Not implemented,Implemented" newline bitfld.long 0x00 15. "L2D_TLB,Attributable Level 2 data or unified TLB access" "Not implemented,Implemented" bitfld.long 0x00 14. "L2I_TLB_REFILL,Attributable Level 2 instruction TLB refill" "Not implemented,Implemented" bitfld.long 0x00 13. "L2D_TLB_REFILL,Attributable Level 2 data or unified TLB refill" "Not implemented,Implemented" newline bitfld.long 0x00 12. "L3D_CACHE_WB,Attributable Level 3 data or unified cache write-back" "Not implemented,Implemented" bitfld.long 0x00 11. "L3D_CACHE,Attributable Level 3 data or unified cache access" "Not implemented,Implemented" bitfld.long 0x00 10. "L3D_CACHE_REFILL,Attributable Level 3 data or unified cache refill" "Not implemented,Implemented" newline bitfld.long 0x00 9. "L3D_CACHE_ALLOCATE,Attributable Level 3 data or unified cache allocation without refill" "Not implemented,Implemented" bitfld.long 0x00 8. "L2I_CACHE_REFILL,Attributable Level 2 instruction cache refill" "Not implemented,Implemented" bitfld.long 0x00 7. "L2I_CACHE,Attributable Level 2 instruction cache access" "Not implemented,Implemented" newline bitfld.long 0x00 6. "L1I_TLB,Level 1 instruction TLB access" "Not implemented,Implemented" bitfld.long 0x00 5. "L1D_TLB,Level 1 data or unified TLB access" "Not implemented,Implemented" bitfld.long 0x00 4. "STALL_BACKEND,No operation issued due to backend" "Not implemented,Implemented" newline bitfld.long 0x00 3. "STALL_FRONTEND,No operation issued due to the frontend" "Not implemented,Implemented" bitfld.long 0x00 2. "BR_MIS_PRED_RETIRED,Instruction architecturally executed mispredicted branch" "Not implemented,Implemented" bitfld.long 0x00 1. "BR_RETIRED,Instruction architecturally executed branch" "Not implemented,Implemented" newline bitfld.long 0x00 0. "L2D_CACHE_ALLOCATE,Level 2 data cache allocate" "Not implemented,Implemented" endif rgroup.long c15:0x04E9++0x00 line.long 0x00 "PMCEID2,Performance Monitors Common Event Identification Register 2" rgroup.long c15:0x05E9++0x00 line.long 0x00 "PMCEID3,Performance Monitors Common Event Identification Register 3" tree.end newline group.long c15:0x00D9++0x00 line.long 0x00 "PMCCNTR[31:0],Performance Monitors Cycle Counter (32bit access)" group.quad c15:0x13090++0x01 line.quad 0x00 "PMCCNTR[63:0],Performance Monitors Cycle Counter (64bit access)" if (((per.l(c15:0X05C9))&0x1F)==0x1F) group.long c15:0x01D9++0x00 line.long 0x00 "PMXEVTYPER,Performance Monitors Selected Event Type and Filter Register - PMCCFILTR" bitfld.long 0x00 31. "P,Privileged modes filtering" "Disabled,Enabled" bitfld.long 0x00 30. "U,User modes filtering" "Disabled,Enabled" bitfld.long 0x00 29. "NSK,Non-secure kernel modes filtering" "Disabled,Enabled" newline bitfld.long 0x00 28. "NSU,Non-secure user modes filtering" "Disabled,Enabled" bitfld.long 0x00 27. "NSH,Non-secure Hypervisor modes filtering" "Disabled,Enabled" elif (((per.l(c15:0X00E9))&0x1)==0x1) group.long c15:0x01D9++0x00 line.long 0x00 "PMXEVTYPER,Performance Monitors Selected Event Type and Filter Register - PMEVTYPER" bitfld.long 0x00 31. "P,Privileged modes filtering" "Disabled,Enabled" bitfld.long 0x00 30. "U,User modes filtering" "Disabled,Enabled" bitfld.long 0x00 29. "NSK,Non-secure kernel modes filtering" "Disabled,Enabled" newline bitfld.long 0x00 28. "NSU,Non-secure user modes filtering" "Disabled,Enabled" bitfld.long 0x00 27. "NSH,Non-secure Hypervisor modes filtering" "Disabled,Enabled" bitfld.long 0x00 26. "M,Secure EL3 filtering" "Disabled,Enabled" newline hexmask.long.word 0x00 0.--9. 1. "EVTCOUNT,Event number" else rgroup.long c15:0x01D9++0x00 line.long 0x00 "PMXEVTYPER,Performance Monitors Selected Event Type and Filter Register" endif group.long c15:0x02D9++0x00 line.long 0x00 "PMXEVCNTR,Performance Monitors Selected Event Counter Register" group.long c15:0x00E9++0x00 line.long 0x00 "PMUSERENR,Performance Monitors User Enable Register" bitfld.long 0x00 3. "ER,Event counter read enable" "Disabled,Enabled" bitfld.long 0x00 2. "CR,Cycle counter read enable" "Disabled,Enabled" newline bitfld.long 0x00 1. "SW,Software Increment write enable" "Disabled,Enabled" bitfld.long 0x00 0. "EN,User enable" "Disabled,Enabled" group.long c15:0x01E9++0x00 line.long 0x00 "PMINTENSET,Performance Monitors Interrupt Enable Set Register" bitfld.long 0x00 31. "C,PMCCNTR Overflow Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 5. "P5,PMCNT5 Overflow Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 4. "P4,PMCNT4 Overflow Interrupt Enable" "Disabled,Enabled" newline bitfld.long 0x00 3. "P3,PMCNT3 Overflow Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 2. "P2,PMCNT2 Overflow Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 1. "P1,PMCNT1 Overflow Interrupt Enable" "Disabled,Enabled" newline bitfld.long 0x00 0. "P0,PMCNT0 Overflow Interrupt Enable" "Disabled,Enabled" group.long c15:0x02E9++0x00 line.long 0x00 "PMINTENCLR,Performance Monitors Interrupt Enable Clear Register" bitfld.long 0x00 31. "C,PMCCNTR Overflow Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 5. "P5,PMCNT5 Overflow Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 4. "P4,PMCNT4 Overflow Interrupt Enable" "Disabled,Enabled" newline bitfld.long 0x00 3. "P3,PMCNT3 Overflow Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 2. "P2,PMCNT2 Overflow Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 1. "P1,PMCNT1 Overflow Interrupt Enable" "Disabled,Enabled" newline bitfld.long 0x00 0. "P0,PMCNT0 Overflow Interrupt Enable" "Disabled,Enabled" group.long c15:0x03E9++0x00 line.long 0x00 "PMOVSSET,Performance Monitors Overflow Flag Status Set Register" bitfld.long 0x00 31. "C,PMCCNTR overflow" "No overflow,Overflow" bitfld.long 0x00 5. "P5,PMEVCNTR5 Overflow Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 4. "P4,PMEVCNTR4 Overflow Interrupt Enable" "Disabled,Enabled" newline bitfld.long 0x00 3. "P3,PMEVCNTR3 Overflow Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 2. "P2,PMEVCNTR2 Overflow Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 1. "P1,PMEVCNTR1 Overflow Interrupt Enable" "Disabled,Enabled" newline bitfld.long 0x00 0. "P0,PMEVCNTR0 Overflow Interrupt Enable" "Disabled,Enabled" group.long c15:0x8E++0x00 line.long 0x00 "PMEVCNTR0,Performance Monitors Event Count Register 0" group.long c15:(0x8E+0x0040)++0x00 line.long 0x00 "PMEVTYPER0,Performance Monitors Event Type Register 0" group.long c15:0x18E++0x00 line.long 0x00 "PMEVCNTR1,Performance Monitors Event Count Register 1" group.long c15:(0x18E+0x0040)++0x00 line.long 0x00 "PMEVTYPER1,Performance Monitors Event Type Register 1" group.long c15:0x28E++0x00 line.long 0x00 "PMEVCNTR2,Performance Monitors Event Count Register 2" group.long c15:(0x28E+0x0040)++0x00 line.long 0x00 "PMEVTYPER2,Performance Monitors Event Type Register 2" group.long c15:0x38E++0x00 line.long 0x00 "PMEVCNTR3,Performance Monitors Event Count Register 3" group.long c15:(0x38E+0x0040)++0x00 line.long 0x00 "PMEVTYPER3,Performance Monitors Event Type Register 3" group.long c15:0x48E++0x00 line.long 0x00 "PMEVCNTR4,Performance Monitors Event Count Register 4" group.long c15:(0x48E+0x0040)++0x00 line.long 0x00 "PMEVTYPER4,Performance Monitors Event Type Register 4" group.long c15:0x58E++0x00 line.long 0x00 "PMEVCNTR5,Performance Monitors Event Count Register 5" group.long c15:(0x58E+0x0040)++0x00 line.long 0x00 "PMEVTYPER5,Performance Monitors Event Type Register 5" group.long c15:0x07FE++0x00 line.long 0x00 "PMCCFILTR,Performance Monitors Cycle Count Filter Register" bitfld.long 0x00 31. "P,EL1 modes filtering bit" "Disabled,Enabled" bitfld.long 0x00 30. "U,EL0 filtering bit" "Disabled,Enabled" bitfld.long 0x00 29. "NSK,Non-secure kernel modes filtering bit" "Disabled,Enabled" newline bitfld.long 0x00 28. "NSU,Non-secure user modes filtering bit" "Enabled,Disabled" bitfld.long 0x00 27. "NSH,Non-secure Hypervisor modes filtering bit" "Disabled,Enabled" tree.end tree "System Timer Registers" group.long c15:0x000E++0x00 line.long 0x00 "CNTFRQ,Counter Frequency Register" group.quad c15:0x100E0++0x01 line.quad 0x00 "CNTPCT,Counter Physical Count Register" rgroup.quad c15:0x110E0++0x01 line.quad 0x00 "CNTVCT,Counter Virtual Count Register" group.quad c15:0x140E0++0x01 line.quad 0x00 "CNTVOFF,Counter Virtual Offset Register" group.long c15:0x001E++0x00 line.long 0x00 "CNTKCTL,Timer PL1 Control Register" bitfld.long 0x00 9. "EL0PTEN,Controls whether the physical timer Registers are accessible from EL0 mode" "Disabled,Enabled" bitfld.long 0x00 8. "EL0VTEN,Controls whether the virtual timer Registers are accessible from EL0 mode" "Disabled,Enabled" bitfld.long 0x00 4.--7. "EVNTI,Selects which bit of CNTVCT is the trigger for the event stream generated from the virtual counter, when that stream is enabled" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "EVNTDIR,Controls which transition of the CNTVCT trigger bit" "0 to 1,1 to 0" newline bitfld.long 0x00 2. "EVNTEN,Enables the generation of an event stream from the virtual counter" "Disabled,Enabled" bitfld.long 0x00 1. "EL0VCTEN,Controls whether the virtual counter, CNTVCT, and the frequency Register CNTFRQ, are accessible from EL0 mode" "Disabled,Enabled" bitfld.long 0x00 0. "EL0PCTEN,Controls whether the physical counter, CNTPCT, and the frequency Register CNTFRQ, are accessible from EL0 mode" "Disabled,Enabled" group.long c15:0x401E++0x00 line.long 0x00 "CNTHCTL,Counter Non-secure PL2 Control Register" bitfld.long 0x00 4.--7. "EVNTI,Selects which bit of CNTPCT is the trigger for the event stream generated from the physical counter" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 3. "EVNTDIR,Controls which transition of the CNTPCT trigger bit, defined by EVNTI" "0 to 1,1 to 0" bitfld.long 0x00 2. "EVNTEN,Enables the generation of an event stream from the physical counter" "Disabled,Enabled" bitfld.long 0x00 1. "EL1PCEN,Controls whether the Non-secure copies of the physical timer Registers are accessible from Non-secure EL1 and EL0 modes" "Not accessible,Accessible" newline bitfld.long 0x00 0. "EL1PCTEN,Controls whether the physical counter, CNTPCT, is accessible from Non-secure EL1 and EL0 modes" "Not accessible,Accessible" group.long c15:0x002E++0x00 line.long 0x00 "CNTP_TVAL,Counter EL1 Physical Compare Value Register" group.long c15:0x012E++0x00 line.long 0x00 "CNTP_CTL,Counter EL1 Physical Timer Control Register" rbitfld.long 0x00 2. "ISTATUS,The status of the timer interrupt" "No interrupt,Interrupt" bitfld.long 0x00 1. "IMASK,Timer interrupt mask" "Not masked,Masked" bitfld.long 0x00 0. "ENABLE,Enables the timer" "Disabled,Enabled" group.quad c15:0x120E0++0x01 line.quad 0x00 "CNTP_CVAL,Counter EL1 Physical Compare Value Register" group.long c15:0x003E++0x00 line.long 0x00 "CNTV_TVAL,Counter EL1 Virtual Timer Value Register" group.long c15:0x013E++0x00 line.long 0x00 "CNTV_CTL,Counter EL1 Virtual Timer Control Register" rbitfld.long 0x00 2. "ISTATUS,The status of the timer interrupt" "No interrupt,Interrupt" bitfld.long 0x00 1. "IMASK,Timer interrupt mask" "Not masked,Masked" bitfld.long 0x00 0. "ENABLE,Enables the timer" "Disabled,Enabled" group.quad c15:0x130E0++0x01 line.quad 0x00 "CNTV_CVAL,Counter EL1 Virtual Compare Value Register" group.long c15:0x402E++0x00 line.long 0x00 "CNTHP_TVAL,Counter Non-secure EL2 Physical Timer Value Register" group.long c15:0x412E++0x00 line.long 0x00 "CNTHP_CTL,Counter Non-secure EL2 Physical Timer Control Register" rbitfld.long 0x00 2. "ISTATUS,The status of the timer interrupt" "No interrupt,Interrupt" bitfld.long 0x00 1. "IMASK,Timer interrupt mask" "Not masked,Masked" bitfld.long 0x00 0. "ENABLE,Enables the timer" "Disabled,Enabled" group.quad c15:0x160E0++0x01 line.quad 0x00 "CNTHP_CVAL,Counter Non-secure EL2 Physical Compare Value Register" tree.end tree "Generic Interrupt Controller System Registers" tree "AArch32 Physical GIC CPU Interface System Registers" tree.open "Interrupt Controller Active Priorities Registers" group.long c15:0x048C++0x00 line.long 0x00 "ICC_AP0R0,Active Priorities Group 0 Register 0" bitfld.long 0x00 31. "P31,Group 0 interrupt active with priority level 31" "No interrupt,Interrupt" bitfld.long 0x00 30. "P30,Group 0 interrupt active with priority level 30" "No interrupt,Interrupt" bitfld.long 0x00 29. "P29,Group 0 interrupt active with priority level 29" "No interrupt,Interrupt" newline bitfld.long 0x00 28. "P28,Group 0 interrupt active with priority level 28" "No interrupt,Interrupt" bitfld.long 0x00 27. "P27,Group 0 interrupt active with priority level 27" "No interrupt,Interrupt" bitfld.long 0x00 26. "P26,Group 0 interrupt active with priority level 26" "No interrupt,Interrupt" newline bitfld.long 0x00 25. "P25,Group 0 interrupt active with priority level 25" "No interrupt,Interrupt" bitfld.long 0x00 24. "P24,Group 0 interrupt active with priority level 24" "No interrupt,Interrupt" bitfld.long 0x00 23. "P23,Group 0 interrupt active with priority level 23" "No interrupt,Interrupt" newline bitfld.long 0x00 22. "P22,Group 0 interrupt active with priority level 22" "No interrupt,Interrupt" bitfld.long 0x00 21. "P21,Group 0 interrupt active with priority level 21" "No interrupt,Interrupt" bitfld.long 0x00 20. "P20,Group 0 interrupt active with priority level 20" "No interrupt,Interrupt" newline bitfld.long 0x00 19. "P19,Group 0 interrupt active with priority level 19" "No interrupt,Interrupt" bitfld.long 0x00 18. "P18,Group 0 interrupt active with priority level 18" "No interrupt,Interrupt" bitfld.long 0x00 17. "P17,Group 0 interrupt active with priority level 17" "No interrupt,Interrupt" newline bitfld.long 0x00 16. "P16,Group 0 interrupt active with priority level 16" "No interrupt,Interrupt" bitfld.long 0x00 15. "P15,Group 0 interrupt active with priority level 15" "No interrupt,Interrupt" bitfld.long 0x00 14. "P14,Group 0 interrupt active with priority level 14" "No interrupt,Interrupt" newline bitfld.long 0x00 13. "P13,Group 0 interrupt active with priority level 13" "No interrupt,Interrupt" bitfld.long 0x00 12. "P12,Group 0 interrupt active with priority level 12" "No interrupt,Interrupt" bitfld.long 0x00 11. "P11,Group 0 interrupt active with priority level 11" "No interrupt,Interrupt" newline bitfld.long 0x00 10. "P10,Group 0 interrupt active with priority level 10" "No interrupt,Interrupt" bitfld.long 0x00 9. "P9,Group 0 interrupt active with priority level 9" "No interrupt,Interrupt" bitfld.long 0x00 8. "P8,Group 0 interrupt active with priority level 8" "No interrupt,Interrupt" newline bitfld.long 0x00 7. "P7,Group 0 interrupt active with priority level 7" "No interrupt,Interrupt" bitfld.long 0x00 6. "P6,Group 0 interrupt active with priority level 6" "No interrupt,Interrupt" bitfld.long 0x00 5. "P5,Group 0 interrupt active with priority level 5" "No interrupt,Interrupt" newline bitfld.long 0x00 4. "P4,Group 0 interrupt active with priority level 4" "No interrupt,Interrupt" bitfld.long 0x00 3. "P3,Group 0 interrupt active with priority level 3" "No interrupt,Interrupt" bitfld.long 0x00 2. "P2,Group 0 interrupt active with priority level 2" "No interrupt,Interrupt" newline bitfld.long 0x00 1. "P1,Group 0 interrupt active with priority level 1" "No interrupt,Interrupt" bitfld.long 0x00 0. "P0,Group 0 interrupt active with priority level 0" "No interrupt,Interrupt" group.long c15:0x009C++0x00 line.long 0x00 "ICC_AP1R0,Active Priorities Group 1 Register 0" bitfld.long 0x00 31. "P31,Group 1 interrupt active with priority level 31" "No interrupt,Interrupt" bitfld.long 0x00 30. "P30,Group 1 interrupt active with priority level 30" "No interrupt,Interrupt" bitfld.long 0x00 29. "P29,Group 1 interrupt active with priority level 29" "No interrupt,Interrupt" newline bitfld.long 0x00 28. "P28,Group 1 interrupt active with priority level 28" "No interrupt,Interrupt" bitfld.long 0x00 27. "P27,Group 1 interrupt active with priority level 27" "No interrupt,Interrupt" bitfld.long 0x00 26. "P26,Group 1 interrupt active with priority level 26" "No interrupt,Interrupt" newline bitfld.long 0x00 25. "P25,Group 1 interrupt active with priority level 25" "No interrupt,Interrupt" bitfld.long 0x00 24. "P24,Group 1 interrupt active with priority level 24" "No interrupt,Interrupt" bitfld.long 0x00 23. "P23,Group 1 interrupt active with priority level 23" "No interrupt,Interrupt" newline bitfld.long 0x00 22. "P22,Group 1 interrupt active with priority level 22" "No interrupt,Interrupt" bitfld.long 0x00 21. "P21,Group 1 interrupt active with priority level 21" "No interrupt,Interrupt" bitfld.long 0x00 20. "P20,Group 1 interrupt active with priority level 20" "No interrupt,Interrupt" newline bitfld.long 0x00 19. "P19,Group 1 interrupt active with priority level 19" "No interrupt,Interrupt" bitfld.long 0x00 18. "P18,Group 1 interrupt active with priority level 18" "No interrupt,Interrupt" bitfld.long 0x00 17. "P17,Group 1 interrupt active with priority level 17" "No interrupt,Interrupt" newline bitfld.long 0x00 16. "P16,Group 1 interrupt active with priority level 16" "No interrupt,Interrupt" bitfld.long 0x00 15. "P15,Group 1 interrupt active with priority level 15" "No interrupt,Interrupt" bitfld.long 0x00 14. "P14,Group 1 interrupt active with priority level 14" "No interrupt,Interrupt" newline bitfld.long 0x00 13. "P13,Group 1 interrupt active with priority level 13" "No interrupt,Interrupt" bitfld.long 0x00 12. "P12,Group 1 interrupt active with priority level 12" "No interrupt,Interrupt" bitfld.long 0x00 11. "P11,Group 1 interrupt active with priority level 11" "No interrupt,Interrupt" newline bitfld.long 0x00 10. "P10,Group 1 interrupt active with priority level 10" "No interrupt,Interrupt" bitfld.long 0x00 9. "P9,Group 1 interrupt active with priority level 9" "No interrupt,Interrupt" bitfld.long 0x00 8. "P8,Group 1 interrupt active with priority level 8" "No interrupt,Interrupt" newline bitfld.long 0x00 7. "P7,Group 1 interrupt active with priority level 7" "No interrupt,Interrupt" bitfld.long 0x00 6. "P6,Group 1 interrupt active with priority level 6" "No interrupt,Interrupt" bitfld.long 0x00 5. "P5,Group 1 interrupt active with priority level 5" "No interrupt,Interrupt" newline bitfld.long 0x00 4. "P4,Group 1 interrupt active with priority level 4" "No interrupt,Interrupt" bitfld.long 0x00 3. "P3,Group 1 interrupt active with priority level 3" "No interrupt,Interrupt" bitfld.long 0x00 2. "P2,Group 1 interrupt active with priority level 2" "No interrupt,Interrupt" newline bitfld.long 0x00 1. "P1,Group 1 interrupt active with priority level 1" "No interrupt,Interrupt" bitfld.long 0x00 0. "P0,Group 1 interrupt active with priority level 0" "No interrupt,Interrupt" tree.end newline if (((per.l(c15:0x110C0))&0x10000000000)==0x00) wgroup.quad c15:0x110C0++0x01 line.quad 0x00 "ICC_ASGI1R,Interrupt Controller Alias Software Generated Interrupt Group 1 Register" hexmask.quad.byte 0x00 48.--55. 1. "AFF3,Affinity 3" newline bitfld.quad 0x00 44.--47. "RS,Range selector" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.quad 0x00 40. "IRM,Interrupt routing mode" "Target list,All PEs excluding self" newline hexmask.quad.byte 0x00 32.--39. 1. "AFF2,Affinity 2" bitfld.quad 0x00 24.--27. "INTID,The INTID of the SGI" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline hexmask.quad.byte 0x00 16.--23. 1. "AFF1,Affinity 1" hexmask.quad.word 0x00 0.--15. 1. "TARGETLIST,The set of PEs for which SGI interrupts will be generated" else wgroup.quad c15:0x110C0++0x01 line.quad 0x00 "ICC_ASGI1R,Interrupt Controller Alias Software Generated Interrupt Group 1 Register" newline bitfld.quad 0x00 44.--47. "RS,Range selector" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.quad 0x00 40. "IRM,Interrupt routing mode" "Target list,All PEs excluding self" newline bitfld.quad 0x00 24.--27. "INTID,The INTID of the SGI" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline endif group.long c15:0x038C++0x00 line.long 0x00 "ICC_BPR0,Binary Point Register 0" bitfld.long 0x00 0.--2. "BINARYPOINT,Interrupt Priority Field Control And Interrupt Preemption Control" "[7:1]-[0],[7:2]-[1:0],[7:3]-[2:0],[7:4]-[3:0],[7:5]-[4:0],[7:6]-[5:0],[7]-[6:0],No preemption-[7:0]" group.long c15:0x03CC++0x00 line.long 0x00 "ICC_BPR1,Binary Point Register 1" bitfld.long 0x00 0.--2. "BINARYPOINT,Interrupt Priority Field Control And Interrupt Preemption Control" ",[7:1]-[0],[7:2]-[1:0],[7:3]-[2:0],[7:4]-[3:0],[7:5]-[4:0],[7:6]-[5:0],[7]-[6:0]" group.long c15:0x04CC++0x00 line.long 0x00 "ICC_CTLR,Interrupt Control Registers for EL1" rbitfld.long 0x00 19. "EXTRANGE,Extended INTID range" "Not supported,Supported" rbitfld.long 0x00 18. "RSS,Range selector support" "0 - 15,0 - 255" newline rbitfld.long 0x00 15. "A3V,Affinity 3 Valid" "Reserved,Supported" rbitfld.long 0x00 14. "SEIS,SEI Support" "Not supported,?..." rbitfld.long 0x00 11.--13. "IDBITS,Number of physical interrupt identifier bits supported" "16 bits,?..." newline rbitfld.long 0x00 8.--10. "PRIBITS,Number of priority bits implemented" "0,1,2,3,4,5,6,7" bitfld.long 0x00 6. "PMHE,Priority Mask Hint Enable" "Disabled,Enabled" bitfld.long 0x00 1. "EOIMODE,Controls whether a write to an End of Interrupt Register also deactivates the interrupt" "Enabled,Disabled" newline bitfld.long 0x00 0. "CBPR,Common Binary Point Register. Controls whether the same Register is used for interrupt pre-emption of both Group 0 and Group 1 interrupt" "Separate Registers,Same Register" group.long c15:0x64CC++0x00 line.long 0x00 "ICC_MCTLR,Interrupt Control Registers for EL3" rbitfld.long 0x00 19. "EXTRANGE,Extended INTID range" "Not supported,Supported" rbitfld.long 0x00 18. "RSS,Range selector support" "0 - 15,0 - 255" newline rbitfld.long 0x00 17. "NDS,Disable Security not supported" "Supported,Not supported" rbitfld.long 0x00 15. "A3V,Affinity 3 Valid" "Reserved,Supported" rbitfld.long 0x00 14. "SEIS,Indicates whether the CPU interface supports generation of SEIs" "Not supported,?..." newline rbitfld.long 0x00 11.--13. "IDBITS,The number of physical interrupt identifier bits supported" "16 bits,?..." rbitfld.long 0x00 8.--10. "PRIBITS,The number of priority bits implemented minus one" "0,1,2,3,4,5,6,7" bitfld.long 0x00 6. "PMHE,Priority Mask Hint Enable" "Disabled,Enabled" newline bitfld.long 0x00 4. "EOIMODE_EL1NS,Controls whether a write to an End of Interrupt Register also deactivates the interrupt(Non-secure EL1 and EL2)" "Enabled,Disabled" bitfld.long 0x00 3. "EOIMODE_EL1S,Controls whether a write to an End of Interrupt Register also deactivates the interrupt(Secure EL1)" "Enabled,Disabled" bitfld.long 0x00 2. "EOIMODE_EL3,Controls whether a write to an End of Interrupt Register also deactivates the interrupt(EL3)" "Enabled,Disabled" newline bitfld.long 0x00 1. "CBPR_EL1NS,Controls whether the same Register is used for interrupt preemption of both Group 0 and Group 1 Non-secure interrupts at EL1" "Separate Registers,Same Register" bitfld.long 0x00 0. "CBPR_EL1S,Controls whether the same Register is used for interrupt preemption of both Group 0 and Group 1 Secure interrupts in Secure non-Monitor modes" "Separate Registers,Same Register" wgroup.long c15:0x01BC++0x00 line.long 0x00 "ICC_DIR,Deactivate Interrupt Register" hexmask.long.word 0x00 0.--15. 1. "INTID,The INTID of the interrupt to be deactivated" wgroup.long c15:0x018C++0x00 line.long 0x00 "ICC_EOIR0,End Of Interrupt Register 0" hexmask.long.word 0x00 0.--15. 1. "INTID,The INTID from the corresponding ICC_IAR0 access" wgroup.long c15:0x01CC++0x00 line.long 0x00 "ICC_EOIR1,End Of Interrupt Register 1" hexmask.long.word 0x00 0.--15. 1. "INTID,The INTID from the corresponding ICC_IAR1 access." rgroup.long c15:0x028C++0x00 line.long 0x00 "ICC_HPPIR0,Highest Priority Pending Interrupt Register 0" hexmask.long.word 0x00 0.--15. 1. "INTID,The INTID of the highest priority pending interrupt" rgroup.long c15:0x02CC++0x00 line.long 0x00 "ICC_HPPIR1,Highest Priority Pending Interrupt Register 1" hexmask.long.word 0x00 0.--15. 1. "INTID,The INTID of the highest priority pending interrupt" rgroup.long c15:0x008C++0x00 line.long 0x00 "ICC_IAR0,Interrupt Acknowledge Register 0" rgroup.long c15:0x00CC++0x00 line.long 0x00 "ICC_IAR1,Interrupt Acknowledge Register 1" group.long c15:0x06CC++0x00 line.long 0x00 "ICC_IGRPEN0,Interrupt Group Enable Register 0" bitfld.long 0x00 0. "ENABLE,Enables Group 0 interrupts" "Disabled,Enabled" group.long c15:0x07CC++0x00 line.long 0x00 "ICC_IGRPEN1,Interrupt Group Enable Register 1" bitfld.long 0x00 0. "ENABLE,Enables Group 0 interrupts" "Disabled,Enabled" group.long c15:0x0064++0x00 line.long 0x00 "ICC_PMR,Priority Mask Register" hexmask.long.byte 0x00 0.--7. 1. "PRIORITY,Priority mask level for the CPU interface" rgroup.long c15:0x03BC++0x00 line.long 0x00 "ICC_RPR,Running Priority Register" hexmask.long.byte 0x00 0.--7. 1. "PRIORITY,Current running priority on the CPU interface" if (((per.q(c15:0x120C0))&0x10000000000)==0x00) group.quad c15:0x120C0++0x01 line.quad 0x00 "ICC_SGI0R,Interrupt Controller Software Generated Interrupt Group 0 Register" hexmask.quad.byte 0x00 48.--55. 1. "AFF3,Affinity 3" newline bitfld.quad 0x00 44.--47. "RS,Range selector" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.quad 0x00 40. "IRM,Interrupt routing mode" "Target list,All PEs excluding self" hexmask.quad.byte 0x00 32.--39. 1. "AFF2,Affinity 2" newline bitfld.quad 0x00 24.--27. "INTID,The INTID of the SGI" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.quad.byte 0x00 16.--23. 1. "AFF1,Affinity 1" hexmask.quad.word 0x00 0.--15. 1. "TARGETLIST,The set of PEs for which SGI interrupts will be generated." else group.quad c15:0x120C0++0x01 line.quad 0x00 "ICC_SGI0R,Interrupt Controller Software Generated Interrupt Group 0 Register" bitfld.quad 0x00 44.--47. "RS,Range selector" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.quad 0x00 40. "IRM,Interrupt routing mode" "Target list,All PEs excluding self" bitfld.quad 0x00 24.--27. "INTID,The INTID of the SGI" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif group.long c15:0x05CC++0x00 line.long 0x00 "ICC_SRE,System Register Enable Register for EL1" bitfld.long 0x00 2. "DIB,Disable IRQ bypass" "No,Yes" bitfld.long 0x00 1. "DFB,Disable FIQ bypass" "No,Yes" rbitfld.long 0x00 0. "SRE,System Register Enable" "Reserved,Enabled" group.long c15:0x459C++0x00 line.long 0x00 "ICC_HSRE,System Register Enable Register for EL2" rbitfld.long 0x00 3. "ENABLE,Enable lower exception level access to ICC_SRE_EL1" "Reserved,Enabled" bitfld.long 0x00 2. "DIB,Disable IRQ bypass" "No,Yes" bitfld.long 0x00 1. "DFB,Disable FIQ bypass" "No,Yes" newline rbitfld.long 0x00 0. "SRE,System Register Enable" "Reserved,Enabled" group.long c15:0x65CC++0x00 line.long 0x00 "ICC_MSRE,System Register Enable Register for EL3" rbitfld.long 0x00 3. "ENABLE,Enable lower exception level access to ICC_SRE_EL1 and ICC_SRE_EL2" "Reserved,Enabled" bitfld.long 0x00 2. "DIB,Disable IRQ bypass" "No,Yes" bitfld.long 0x00 1. "DFB,Disable FIQ bypass" "No,Yes" newline rbitfld.long 0x00 0. "SRE,System Register Enable" "Reserved,Enabled" group.long c15:0x67CC++0x00 line.long 0x00 "ICC_MGRPEN1,Monitor Group1 Interrupt Group Enable" bitfld.long 0x00 1. "ENABLEGRP1S,Enables Group 1 interrupts for the Secure state" "Disabled,Enabled" bitfld.long 0x00 0. "ENABLEGRP1NS,Enables Group 1 interrupts for the Non-secure state" "Disabled,Enabled" tree.end tree "AArch32 Virtual GIC CPU Interface System Registers" tree.open "Interrupt Controller Active Priorities Registers" group.long c15:0x048C++0x00 line.long 0x00 "ICV_AP0R0,Active Priorities Group 0 Register 0" bitfld.long 0x00 31. "P31,Group 0 interrupt active with priority level 31" "No interrupt,Interrupt" bitfld.long 0x00 30. "P30,Group 0 interrupt active with priority level 30" "No interrupt,Interrupt" bitfld.long 0x00 29. "P29,Group 0 interrupt active with priority level 29" "No interrupt,Interrupt" newline bitfld.long 0x00 28. "P28,Group 0 interrupt active with priority level 28" "No interrupt,Interrupt" bitfld.long 0x00 27. "P27,Group 0 interrupt active with priority level 27" "No interrupt,Interrupt" bitfld.long 0x00 26. "P26,Group 0 interrupt active with priority level 26" "No interrupt,Interrupt" newline bitfld.long 0x00 25. "P25,Group 0 interrupt active with priority level 25" "No interrupt,Interrupt" bitfld.long 0x00 24. "P24,Group 0 interrupt active with priority level 24" "No interrupt,Interrupt" bitfld.long 0x00 23. "P23,Group 0 interrupt active with priority level 23" "No interrupt,Interrupt" newline bitfld.long 0x00 22. "P22,Group 0 interrupt active with priority level 22" "No interrupt,Interrupt" bitfld.long 0x00 21. "P21,Group 0 interrupt active with priority level 21" "No interrupt,Interrupt" bitfld.long 0x00 20. "P20,Group 0 interrupt active with priority level 20" "No interrupt,Interrupt" newline bitfld.long 0x00 19. "P19,Group 0 interrupt active with priority level 19" "No interrupt,Interrupt" bitfld.long 0x00 18. "P18,Group 0 interrupt active with priority level 18" "No interrupt,Interrupt" bitfld.long 0x00 17. "P17,Group 0 interrupt active with priority level 17" "No interrupt,Interrupt" newline bitfld.long 0x00 16. "P16,Group 0 interrupt active with priority level 16" "No interrupt,Interrupt" bitfld.long 0x00 15. "P15,Group 0 interrupt active with priority level 15" "No interrupt,Interrupt" bitfld.long 0x00 14. "P14,Group 0 interrupt active with priority level 14" "No interrupt,Interrupt" newline bitfld.long 0x00 13. "P13,Group 0 interrupt active with priority level 13" "No interrupt,Interrupt" bitfld.long 0x00 12. "P12,Group 0 interrupt active with priority level 12" "No interrupt,Interrupt" bitfld.long 0x00 11. "P11,Group 0 interrupt active with priority level 11" "No interrupt,Interrupt" newline bitfld.long 0x00 10. "P10,Group 0 interrupt active with priority level 10" "No interrupt,Interrupt" bitfld.long 0x00 9. "P9,Group 0 interrupt active with priority level 9" "No interrupt,Interrupt" bitfld.long 0x00 8. "P8,Group 0 interrupt active with priority level 8" "No interrupt,Interrupt" newline bitfld.long 0x00 7. "P7,Group 0 interrupt active with priority level 7" "No interrupt,Interrupt" bitfld.long 0x00 6. "P6,Group 0 interrupt active with priority level 6" "No interrupt,Interrupt" bitfld.long 0x00 5. "P5,Group 0 interrupt active with priority level 5" "No interrupt,Interrupt" newline bitfld.long 0x00 4. "P4,Group 0 interrupt active with priority level 4" "No interrupt,Interrupt" bitfld.long 0x00 3. "P3,Group 0 interrupt active with priority level 3" "No interrupt,Interrupt" bitfld.long 0x00 2. "P2,Group 0 interrupt active with priority level 2" "No interrupt,Interrupt" newline bitfld.long 0x00 1. "P1,Group 0 interrupt active with priority level 1" "No interrupt,Interrupt" bitfld.long 0x00 0. "P0,Group 0 interrupt active with priority level 0" "No interrupt,Interrupt" group.long c15:0x009C++0x00 line.long 0x00 "ICV_AP1R0,Active Priorities Group 1 Register 0" bitfld.long 0x00 31. "P31,Group 1 interrupt active with priority level 31" "No interrupt,Interrupt" bitfld.long 0x00 30. "P30,Group 1 interrupt active with priority level 30" "No interrupt,Interrupt" bitfld.long 0x00 29. "P29,Group 1 interrupt active with priority level 29" "No interrupt,Interrupt" newline bitfld.long 0x00 28. "P28,Group 1 interrupt active with priority level 28" "No interrupt,Interrupt" bitfld.long 0x00 27. "P27,Group 1 interrupt active with priority level 27" "No interrupt,Interrupt" bitfld.long 0x00 26. "P26,Group 1 interrupt active with priority level 26" "No interrupt,Interrupt" newline bitfld.long 0x00 25. "P25,Group 1 interrupt active with priority level 25" "No interrupt,Interrupt" bitfld.long 0x00 24. "P24,Group 1 interrupt active with priority level 24" "No interrupt,Interrupt" bitfld.long 0x00 23. "P23,Group 1 interrupt active with priority level 23" "No interrupt,Interrupt" newline bitfld.long 0x00 22. "P22,Group 1 interrupt active with priority level 22" "No interrupt,Interrupt" bitfld.long 0x00 21. "P21,Group 1 interrupt active with priority level 21" "No interrupt,Interrupt" bitfld.long 0x00 20. "P20,Group 1 interrupt active with priority level 20" "No interrupt,Interrupt" newline bitfld.long 0x00 19. "P19,Group 1 interrupt active with priority level 19" "No interrupt,Interrupt" bitfld.long 0x00 18. "P18,Group 1 interrupt active with priority level 18" "No interrupt,Interrupt" bitfld.long 0x00 17. "P17,Group 1 interrupt active with priority level 17" "No interrupt,Interrupt" newline bitfld.long 0x00 16. "P16,Group 1 interrupt active with priority level 16" "No interrupt,Interrupt" bitfld.long 0x00 15. "P15,Group 1 interrupt active with priority level 15" "No interrupt,Interrupt" bitfld.long 0x00 14. "P14,Group 1 interrupt active with priority level 14" "No interrupt,Interrupt" newline bitfld.long 0x00 13. "P13,Group 1 interrupt active with priority level 13" "No interrupt,Interrupt" bitfld.long 0x00 12. "P12,Group 1 interrupt active with priority level 12" "No interrupt,Interrupt" bitfld.long 0x00 11. "P11,Group 1 interrupt active with priority level 11" "No interrupt,Interrupt" newline bitfld.long 0x00 10. "P10,Group 1 interrupt active with priority level 10" "No interrupt,Interrupt" bitfld.long 0x00 9. "P9,Group 1 interrupt active with priority level 9" "No interrupt,Interrupt" bitfld.long 0x00 8. "P8,Group 1 interrupt active with priority level 8" "No interrupt,Interrupt" newline bitfld.long 0x00 7. "P7,Group 1 interrupt active with priority level 7" "No interrupt,Interrupt" bitfld.long 0x00 6. "P6,Group 1 interrupt active with priority level 6" "No interrupt,Interrupt" bitfld.long 0x00 5. "P5,Group 1 interrupt active with priority level 5" "No interrupt,Interrupt" newline bitfld.long 0x00 4. "P4,Group 1 interrupt active with priority level 4" "No interrupt,Interrupt" bitfld.long 0x00 3. "P3,Group 1 interrupt active with priority level 3" "No interrupt,Interrupt" bitfld.long 0x00 2. "P2,Group 1 interrupt active with priority level 2" "No interrupt,Interrupt" newline bitfld.long 0x00 1. "P1,Group 1 interrupt active with priority level 1" "No interrupt,Interrupt" bitfld.long 0x00 0. "P0,Group 1 interrupt active with priority level 0" "No interrupt,Interrupt" tree.end newline group.long c15:0x038C++0x00 line.long 0x00 "ICV_BPR0,Binary Point Register 0" bitfld.long 0x00 0.--2. "BINARYPOINT,Interrupt Priority Field Control And Interrupt Preemption Control" "[7:1]-[0],[7:2]-[1:0],[7:3]-[2:0],[7:4]-[3:0],[7:5]-[4:0],[7:6]-[5:0],[7]-[6:0],No preemption-[7:0]" group.long c15:0x03CC++0x00 line.long 0x00 "ICV_BPR1,Binary Point Register 1" bitfld.long 0x00 0.--2. "BINARYPOINT,Interrupt Priority Field Control And Interrupt Preemption Control" ",[7:1]-[0],[7:2]-[1:0],[7:3]-[2:0],[7:4]-[3:0],[7:5]-[4:0],[7:6]-[5:0],[7]-[6:0]" group.long c15:0x4CC++0x00 line.long 0x00 "ICV_CTLR,Control Register" rbitfld.long 0x00 19. "EXTRANGE,Extended INTID range" "Not supported,Supported" rbitfld.long 0x00 18. "RSS,Range selector support" "0 - 15,0 - 255" newline bitfld.long 0x00 15. "A3V,Affinity 3 Valid" "Reserved,Supported" bitfld.long 0x00 14. "SEIS,Indicates whether the CPU interface supports local generation of SEIs" "Not supported,?..." bitfld.long 0x00 11.--13. "IDBITS,The number of physical interrupt identifier bits supported" "16 bits,?..." newline bitfld.long 0x00 8.--10. "PRIBITS,The number of priority bits implemented minus one" "0,1,2,3,4,5,6,7" bitfld.long 0x00 1. "VEOIMODE,Controls whether a write to an End of Interrupt Register also deactivates the interrupt" "Disabled,Enabled" newline bitfld.long 0x00 0. "VCBPR,Controls whether the same Register is used for interrupt preemption of both virtual Group 0 and virtual Group 1 interrupts" "Separate Registers,Same Register" wgroup.long c15:0x01BC++0x00 line.long 0x00 "ICV_DIR,Deactivate Interrupt Register" hexmask.long.word 0x00 0.--15. 1. "INTID,The INTID of the interrupt to be deactivated" wgroup.long c15:0x018C++0x00 line.long 0x00 "ICV_EOIR0,End Of Interrupt Register 0" hexmask.long.word 0x00 0.--15. 1. "INTID,The INTID from the corresponding ICC_IAR0 access" wgroup.long c15:0x01CC++0x00 line.long 0x00 "ICV_EOIR1,End Of Interrupt Register 1" hexmask.long.word 0x00 0.--15. 1. "INTID,The INTID from the corresponding ICC_IAR1 access" rgroup.long c15:0x028C++0x00 line.long 0x00 "ICV_HPPIR0,Highest Priority Pending Interrupt Register 0" hexmask.long.word 0x00 0.--15. 1. "INTID,The INTID of the highest priority pending interrupt" rgroup.long c15:0x02CC++0x00 line.long 0x00 "ICV_HPPIR1,Highest Priority Pending Interrupt Register 1" hexmask.long.word 0x00 0.--15. 1. "INTID,The INTID of the highest priority pending interrupt" rgroup.long c15:0x008C++0x00 line.long 0x00 "ICV_IAR0,Interrupt Acknowledge Register 0" rgroup.long c15:0x00CC++0x00 line.long 0x00 "ICV_IAR1,Interrupt Acknowledge Register 1" group.long c15:0x06CC++0x00 line.long 0x00 "ICV_IGRPEN0,Interrupt Group 0 Enable Register" bitfld.long 0x00 0. "ENABLE,Enables Group 0 interrupts" "Disabled,Enabled" group.long c15:0x07CC++0x00 line.long 0x00 "ICV_IGRPEN1,Interrupt Group 1 Enable Register" bitfld.long 0x00 0. "ENABLE,Enables Group 1 interrupts" "Disabled,Enabled" newline group.long c15:0x064CC++0x00 line.long 0x00 "ICV_MCTLR,Monitor Control Register" rbitfld.long 0x00 19. "EXTRANGE,Extended INTID range" "Not supported,Supported" rbitfld.long 0x00 18. "RSS,Range selector support" "0 - 15,0 - 255" newline rbitfld.long 0x00 17. "NDS,Disable Security not supported" "Supported,Not supported" rbitfld.long 0x00 15. "A3V,Affinity 3 Valid" "Reserved,Supported" rbitfld.long 0x00 14. "SEIS,Indicates whether the CPU interface supports generation of SEIs" "Not supported,?..." newline rbitfld.long 0x00 11.--13. "IDBITS,The number of physical interrupt identifier bits supported" "16 bits,?..." rbitfld.long 0x00 8.--10. "PRIBITS,The number of priority bits implemented minus one" "0,1,2,3,4,5,6,7" bitfld.long 0x00 6. "PMHE,Priority Mask Hint Enable" "Disabled,Enabled" newline bitfld.long 0x00 4. "EOIMODE_EL1NS,Controls whether a write to an End of Interrupt Register also deactivates the interrupt (Non-secure EL1 and EL2)" "Priority drop/Deactivation,Priority drop" bitfld.long 0x00 3. "EOIMODE_EL1S,Controls whether a write to an End of Interrupt Register also deactivates the interrupt (Secure EL1)" "Enabled,Disabled" bitfld.long 0x00 2. "EOIMODE_EL3,Controls whether a write to an End of Interrupt Register also deactivates the interrupt (EL3)" "Enabled,Disabled" newline bitfld.long 0x00 1. "CBPR_EL1NS,Controls whether the same Register is used for interrupt preemption of both Group 0 and Group 1 Non-secure interrupts at EL1" "Separate Registers,Same Register" bitfld.long 0x00 0. "CBPR_EL1S,Controls whether the same Register is used for interrupt preemption of both Group 0 and Group 1 Secure interrupts in Secure non-Monitor modes" "Separate Registers,Same Register" group.long c15:0x67CC++0x00 line.long 0x00 "ICV_MGRPEN1,Monitor Interrupt Group 1 Enable Register" bitfld.long 0x00 1. "ENABLEGRP1S,Enables Group 1 interrupts for the Secure state" "Disabled,Enabled" bitfld.long 0x00 0. "ENABLEGRP1NS,Enables Group 1 interrupts for the Non-secure state" "Disabled,Enabled" group.long c15:0x0064++0x00 line.long 0x00 "ICV_PMR,Interrupt Priority Mask Register" hexmask.long.byte 0x00 0.--7. 1. "PRIORITY,The priority mask level for the CPU interface" rgroup.long c15:0x03BC++0x00 line.long 0x00 "ICV_RPR,Running Priority Register" hexmask.long.byte 0x00 0.--7. 1. "PRIORITY,The current running priority on the CPU interface" tree.end tree "AArch32 Virtual Interface Control System Registers" tree.open "Hypervisor Active Priorities Registers" group.long c15:0x408C++0x00 line.long 0x00 "ICH_AP0R0,Hypervisor Active Priorities Group 0 Register 0" bitfld.long 0x00 31. "P31,Group 0 interrupt active with priority level 31" "No interrupt,Interrupt" bitfld.long 0x00 30. "P30,Group 0 interrupt active with priority level 30" "No interrupt,Interrupt" bitfld.long 0x00 29. "P29,Group 0 interrupt active with priority level 29" "No interrupt,Interrupt" newline bitfld.long 0x00 28. "P28,Group 0 interrupt active with priority level 28" "No interrupt,Interrupt" bitfld.long 0x00 27. "P27,Group 0 interrupt active with priority level 27" "No interrupt,Interrupt" bitfld.long 0x00 26. "P26,Group 0 interrupt active with priority level 26" "No interrupt,Interrupt" newline bitfld.long 0x00 25. "P25,Group 0 interrupt active with priority level 25" "No interrupt,Interrupt" bitfld.long 0x00 24. "P24,Group 0 interrupt active with priority level 24" "No interrupt,Interrupt" bitfld.long 0x00 23. "P23,Group 0 interrupt active with priority level 23" "No interrupt,Interrupt" newline bitfld.long 0x00 22. "P22,Group 0 interrupt active with priority level 22" "No interrupt,Interrupt" bitfld.long 0x00 21. "P21,Group 0 interrupt active with priority level 21" "No interrupt,Interrupt" bitfld.long 0x00 20. "P20,Group 0 interrupt active with priority level 20" "No interrupt,Interrupt" newline bitfld.long 0x00 19. "P19,Group 0 interrupt active with priority level 19" "No interrupt,Interrupt" bitfld.long 0x00 18. "P18,Group 0 interrupt active with priority level 18" "No interrupt,Interrupt" bitfld.long 0x00 17. "P17,Group 0 interrupt active with priority level 17" "No interrupt,Interrupt" newline bitfld.long 0x00 16. "P16,Group 0 interrupt active with priority level 16" "No interrupt,Interrupt" bitfld.long 0x00 15. "P15,Group 0 interrupt active with priority level 15" "No interrupt,Interrupt" bitfld.long 0x00 14. "P14,Group 0 interrupt active with priority level 14" "No interrupt,Interrupt" newline bitfld.long 0x00 13. "P13,Group 0 interrupt active with priority level 13" "No interrupt,Interrupt" bitfld.long 0x00 12. "P12,Group 0 interrupt active with priority level 12" "No interrupt,Interrupt" bitfld.long 0x00 11. "P11,Group 0 interrupt active with priority level 11" "No interrupt,Interrupt" newline bitfld.long 0x00 10. "P10,Group 0 interrupt active with priority level 10" "No interrupt,Interrupt" bitfld.long 0x00 9. "P9,Group 0 interrupt active with priority level 9" "No interrupt,Interrupt" bitfld.long 0x00 8. "P8,Group 0 interrupt active with priority level 8" "No interrupt,Interrupt" newline bitfld.long 0x00 7. "P7,Group 0 interrupt active with priority level 7" "No interrupt,Interrupt" bitfld.long 0x00 6. "P6,Group 0 interrupt active with priority level 6" "No interrupt,Interrupt" bitfld.long 0x00 5. "P5,Group 0 interrupt active with priority level 5" "No interrupt,Interrupt" newline bitfld.long 0x00 4. "P4,Group 0 interrupt active with priority level 4" "No interrupt,Interrupt" bitfld.long 0x00 3. "P3,Group 0 interrupt active with priority level 3" "No interrupt,Interrupt" bitfld.long 0x00 2. "P2,Group 0 interrupt active with priority level 2" "No interrupt,Interrupt" newline bitfld.long 0x00 1. "P1,Group 0 interrupt active with priority level 1" "No interrupt,Interrupt" bitfld.long 0x00 0. "P0,Group 0 interrupt active with priority level 0" "No interrupt,Interrupt" group.long c15:0x409C++0x00 line.long 0x00 "ICH_AP1R0,Hypervisor Active Priorities Group 1 Register 0" bitfld.long 0x00 31. "P31,Group 1 interrupt active with priority level 31" "No interrupt,Interrupt" bitfld.long 0x00 30. "P30,Group 1 interrupt active with priority level 30" "No interrupt,Interrupt" bitfld.long 0x00 29. "P29,Group 1 interrupt active with priority level 29" "No interrupt,Interrupt" newline bitfld.long 0x00 28. "P28,Group 1 interrupt active with priority level 28" "No interrupt,Interrupt" bitfld.long 0x00 27. "P27,Group 1 interrupt active with priority level 27" "No interrupt,Interrupt" bitfld.long 0x00 26. "P26,Group 1 interrupt active with priority level 26" "No interrupt,Interrupt" newline bitfld.long 0x00 25. "P25,Group 1 interrupt active with priority level 25" "No interrupt,Interrupt" bitfld.long 0x00 24. "P24,Group 1 interrupt active with priority level 24" "No interrupt,Interrupt" bitfld.long 0x00 23. "P23,Group 1 interrupt active with priority level 23" "No interrupt,Interrupt" newline bitfld.long 0x00 22. "P22,Group 1 interrupt active with priority level 22" "No interrupt,Interrupt" bitfld.long 0x00 21. "P21,Group 1 interrupt active with priority level 21" "No interrupt,Interrupt" bitfld.long 0x00 20. "P20,Group 1 interrupt active with priority level 20" "No interrupt,Interrupt" newline bitfld.long 0x00 19. "P19,Group 1 interrupt active with priority level 19" "No interrupt,Interrupt" bitfld.long 0x00 18. "P18,Group 1 interrupt active with priority level 18" "No interrupt,Interrupt" bitfld.long 0x00 17. "P17,Group 1 interrupt active with priority level 17" "No interrupt,Interrupt" newline bitfld.long 0x00 16. "P16,Group 1 interrupt active with priority level 16" "No interrupt,Interrupt" bitfld.long 0x00 15. "P15,Group 1 interrupt active with priority level 15" "No interrupt,Interrupt" bitfld.long 0x00 14. "P14,Group 1 interrupt active with priority level 14" "No interrupt,Interrupt" newline bitfld.long 0x00 13. "P13,Group 1 interrupt active with priority level 13" "No interrupt,Interrupt" bitfld.long 0x00 12. "P12,Group 1 interrupt active with priority level 12" "No interrupt,Interrupt" bitfld.long 0x00 11. "P11,Group 1 interrupt active with priority level 11" "No interrupt,Interrupt" newline bitfld.long 0x00 10. "P10,Group 1 interrupt active with priority level 10" "No interrupt,Interrupt" bitfld.long 0x00 9. "P9,Group 1 interrupt active with priority level 9" "No interrupt,Interrupt" bitfld.long 0x00 8. "P8,Group 1 interrupt active with priority level 8" "No interrupt,Interrupt" newline bitfld.long 0x00 7. "P7,Group 1 interrupt active with priority level 7" "No interrupt,Interrupt" bitfld.long 0x00 6. "P6,Group 1 interrupt active with priority level 6" "No interrupt,Interrupt" bitfld.long 0x00 5. "P5,Group 1 interrupt active with priority level 5" "No interrupt,Interrupt" newline bitfld.long 0x00 4. "P4,Group 1 interrupt active with priority level 4" "No interrupt,Interrupt" bitfld.long 0x00 3. "P3,Group 1 interrupt active with priority level 3" "No interrupt,Interrupt" bitfld.long 0x00 2. "P2,Group 1 interrupt active with priority level 2" "No interrupt,Interrupt" newline bitfld.long 0x00 1. "P1,Group 1 interrupt active with priority level 1" "No interrupt,Interrupt" bitfld.long 0x00 0. "P0,Group 1 interrupt active with priority level 0" "No interrupt,Interrupt" tree.end newline rgroup.long c15:0x438C++0x00 line.long 0x00 "ICH_EISR,End of Interrupt Status Register" bitfld.long 0x00 3. "STATUS3,EOI maintenance interrupt status bit for List Register 3" "No interrupt,Interrupt" bitfld.long 0x00 2. "STATUS2,EOI maintenance interrupt status bit for List Register 2" "No interrupt,Interrupt" bitfld.long 0x00 1. "STATUS1,EOI maintenance interrupt status bit for List Register 1" "No interrupt,Interrupt" newline bitfld.long 0x00 0. "STATUS0,EOI maintenance interrupt status bit for List Register 0" "No interrupt,Interrupt" rgroup.long c15:0x458C++0x00 line.long 0x00 "ICH_ELRSR,Empty List Register Status Register" bitfld.long 0x00 3. "STATUS3,Status bit for List Register 3" "Interrupt,No interrupt" bitfld.long 0x00 2. "STATUS2,Status bit for List Register 2" "Interrupt,No interrupt" bitfld.long 0x00 1. "STATUS1,Status bit for List Register 1" "Interrupt,No interrupt" newline bitfld.long 0x00 0. "STATUS0,Status bit for List Register 0" "Interrupt,No interrupt" group.long c15:0x40BC++0x00 line.long 0x00 "ICH_HCR,Hypervisor Control Register" bitfld.long 0x00 27.--31. "EOICOUNT,This field is incremented whenever a successful write to a virtual EOIR or DIR Register would have resulted in a virtual interrupt deactivation" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 14. "TDIR,Trap Non-secure EL1 writes to ICC_DIR and ICV_DIR" "No trap,Trap" bitfld.long 0x00 13. "TSEI,Trap all locally generated SEIs" "No trap,Trap" newline bitfld.long 0x00 12. "TALL1,Trap all Non-secure EL1 accesses to ICC_* and ICV_* System Registers for Group 1 interrupts to EL2" "No trap,Trap" bitfld.long 0x00 11. "TALL0,Trap all Non-secure EL1 accesses to ICC_* and ICV_* System Registers for Group 0 interrupts to EL2" "No trap,Trap" bitfld.long 0x00 10. "TC,Trap all Non-secure EL1 accesses to System Registers that are common to Group 0 and Group 1 to EL2" "No trap,Trap" newline bitfld.long 0x00 7. "VGRP1DIE,VM Group 1 Disabled Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 6. "VGRP1EIE,VM Group 1 Enabled Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 5. "VGRP0DIE,VM Group 0 Disabled Interrupt Enable" "Disabled,Enabled" newline bitfld.long 0x00 4. "VGRP0EIE,VM Group 0 Enabled Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 3. "NPIE,No Pending Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 2. "LRENPIE,List Register Entry Not Present Interrupt Enable" "Disabled,Enabled" newline bitfld.long 0x00 1. "UIE,Underflow Interrupt Enable" "Disabled,Enabled" bitfld.long 0x00 0. "EN,Global enable bit for the virtual CPU interface" "Disabled,Enabled" group.long c15:(0x40CC+0x0)++0x00 line.long 0x00 "ICH_LR0,List Register 0" hexmask.long 0x00 0.--31. 1. "vINTID,Virtual INTID of the interrupt" group.long c15:(0x40CC+0x100)++0x00 line.long 0x00 "ICH_LR1,List Register 1" hexmask.long 0x00 0.--31. 1. "vINTID,Virtual INTID of the interrupt" group.long c15:(0x40CC+0x200)++0x00 line.long 0x00 "ICH_LR2,List Register 2" hexmask.long 0x00 0.--31. 1. "vINTID,Virtual INTID of the interrupt" group.long c15:(0x40CC+0x300)++0x00 line.long 0x00 "ICH_LR3,List Register 3" hexmask.long 0x00 0.--31. 1. "vINTID,Virtual INTID of the interrupt" group.long c15:(0x40EC+0x0)++0x00 line.long 0x00 "ICH_LRC0,List Register Extension 0" bitfld.long 0x00 30.--31. "STATE,The state of the interrupt" "Inactive,Pending,Active,Pending and active" bitfld.long 0x00 29. "HW,Indicates whether this virtual interrupt maps directly to a hardware interrupt, meaning that it corresponds to a physical interrupt." "Triggered by Software,Hardware interrupt" bitfld.long 0x00 28. "GROUP,Indicates the group for this virtual interrupt" "Group 1,Group 0" newline hexmask.long.byte 0x00 16.--23. 1. "PRIORITY,The priority of this interrupt" hexmask.long.word 0x00 0.--9. 1. "PINTID,Physical INTID for hardware interrupts" group.long c15:(0x40EC+0x100)++0x00 line.long 0x00 "ICH_LRC1,List Register Extension 1" bitfld.long 0x00 30.--31. "STATE,The state of the interrupt" "Inactive,Pending,Active,Pending and active" bitfld.long 0x00 29. "HW,Indicates whether this virtual interrupt maps directly to a hardware interrupt, meaning that it corresponds to a physical interrupt." "Triggered by Software,Hardware interrupt" bitfld.long 0x00 28. "GROUP,Indicates the group for this virtual interrupt" "Group 1,Group 0" newline hexmask.long.byte 0x00 16.--23. 1. "PRIORITY,The priority of this interrupt" hexmask.long.word 0x00 0.--9. 1. "PINTID,Physical INTID for hardware interrupts" group.long c15:(0x40EC+0x200)++0x00 line.long 0x00 "ICH_LRC2,List Register Extension 2" bitfld.long 0x00 30.--31. "STATE,The state of the interrupt" "Inactive,Pending,Active,Pending and active" bitfld.long 0x00 29. "HW,Indicates whether this virtual interrupt maps directly to a hardware interrupt, meaning that it corresponds to a physical interrupt." "Triggered by Software,Hardware interrupt" bitfld.long 0x00 28. "GROUP,Indicates the group for this virtual interrupt" "Group 1,Group 0" newline hexmask.long.byte 0x00 16.--23. 1. "PRIORITY,The priority of this interrupt" hexmask.long.word 0x00 0.--9. 1. "PINTID,Physical INTID for hardware interrupts" group.long c15:(0x40EC+0x300)++0x00 line.long 0x00 "ICH_LRC3,List Register Extension 3" bitfld.long 0x00 30.--31. "STATE,The state of the interrupt" "Inactive,Pending,Active,Pending and active" bitfld.long 0x00 29. "HW,Indicates whether this virtual interrupt maps directly to a hardware interrupt, meaning that it corresponds to a physical interrupt." "Triggered by Software,Hardware interrupt" bitfld.long 0x00 28. "GROUP,Indicates the group for this virtual interrupt" "Group 1,Group 0" newline hexmask.long.byte 0x00 16.--23. 1. "PRIORITY,The priority of this interrupt" hexmask.long.word 0x00 0.--9. 1. "PINTID,Physical INTID for hardware interrupts" rgroup.long c15:0x42BC++0x00 line.long 0x00 "ICH_MISR,Maintenance Interrupt State Register" bitfld.long 0x00 7. "VGRP1D,VPE Group 1 Disabled" "Not asserted,Asserted" bitfld.long 0x00 6. "VGRP1E,VPE Group 1 Enabled" "Not asserted,Asserted" bitfld.long 0x00 5. "VGRP0D,VPE Group 0 Disabled" "Not asserted,Asserted" newline bitfld.long 0x00 4. "VGRP0E,VPE Group 0 Enabled" "Not asserted,Asserted" bitfld.long 0x00 3. "NP,No Pending" "Not asserted,Asserted" bitfld.long 0x00 2. "LRENP,List Register Entry Not Present" "Not asserted,Asserted" newline bitfld.long 0x00 1. "U,Underflow" "Not asserted,Asserted" bitfld.long 0x00 0. "EOI,End Of Interrupt" "Not asserted,Asserted" group.long c15:0x47BC++0x00 line.long 0x00 "ICH_VMCR,Virtual Machine Control Register" hexmask.long.byte 0x00 24.--31. 1. "VPMR,The priority mask level for the virtual CPU interface" bitfld.long 0x00 21.--23. "VBPR0,Virtual Binary Point Register Group 0" "[7:1]-[0],[7:2]-[1:0],[7:3]-[2:0],[7:4]-[3:0],[7:5]-[4:0],[7:6]-[5:0],[7]-[6:0],No preemption-[7:0]" bitfld.long 0x00 18.--20. "VBPR1,Virtual Binary Point Register, Group 1" ",[7:1]-[0],[7:2]-[1:0],[7:3]-[2:0],[7:4]-[3:0],[7:5]-[4:0],[7:6]-[5:0],[7]-[6:0]" newline bitfld.long 0x00 9. "VEOIM,Controls whether a write to an End of Interrupt Register also deactivates the virtual interrupt" "Disabled,Enabled" bitfld.long 0x00 4. "VCBPR,Virtual Common Binary Point Register" "Separate Registers,Same Register" bitfld.long 0x00 3. "VFIQEN,Virtual FIQ enable" "Reserved,Virtual FIQs" newline bitfld.long 0x00 1. "VENG1,Virtual Group 1 interrupt enable" "Disabled,Enabled" bitfld.long 0x00 0. "VENG0,Virtual Group 0 interrupt enable" "Disabled,Enabled" group.long c15:0x449C++0x00 line.long 0x00 "ICH_VSEIR,Virtual System Error Interrupt Register" rgroup.long c15:0x41BC++0x00 line.long 0x00 "ICH_VTR,VGIC Type Register" bitfld.long 0x00 29.--31. "PRIBITS,The number of priority bits implemented minus one" "0,1,2,3,4,5,6,7" bitfld.long 0x00 26.--28. "PREBITS,The number of virtual preemption bits implemented, minus one" "0,1,2,3,4,5,6,7" bitfld.long 0x00 23.--25. "IDBITS,The number of physical interrupt identifier bits supported" "16 bits,?..." newline bitfld.long 0x00 22. "SEIS,Indicates whether the CPU interface supports local generation of SEIs" "Not supported,?..." bitfld.long 0x00 21. "A3V,Affinity 3 Valid" "Reserved,Supported" bitfld.long 0x00 20. "NV4,GICv4 direct injection of virtual interrupts not supported" "Supported,?..." newline bitfld.long 0x00 19. "TDS,Separate trapping of Non-secure EL1 writes to ICV_DIR_EL1 supported" "Reserved,Supported" bitfld.long 0x00 0.--4. "LISTREGS,The number of implemented List Registers minus one" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" tree.end tree.end tree "Debug Registers" tree "Coresight Management Registers" if corename()=="CORTEXA75" rgroup.long c14:0x0000++0x0 line.long 0x0 "DBGDIDR,Debug ID Register" bitfld.long 0x0 28.--31. "WRP,Number of Watchpoint Register Pairs" "Reserved,Reserved,Reserved,4,?..." bitfld.long 0x0 24.--27. "BRP,Number of Breakpoint Register Pairs" "Reserved,Reserved,Reserved,Reserved,Reserved,6,?..." bitfld.long 0x0 20.--23. "CTX_CMP,Number of BRPs with Context ID Comparison Capability" "Reserved,2,?..." newline bitfld.long 0x00 16.--19. "VERSION,Debug architecture version" "Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,v8.2,?..." bitfld.long 0x0 14. "NSUHD,Secure User halting debug-mode" "Reserved,Not supported" bitfld.long 0x0 12. "SE,Security Extensions implemented" "Reserved,Implemented" elif corename()=="CORTEXA55" rgroup.long c14:0x0000++0x0 line.long 0x0 "DBGDIDR,Debug ID Register" bitfld.long 0x0 28.--31. "WRP,Number of Watchpoint Register Pairs" "Reserved,Reserved,Reserved,4,?..." bitfld.long 0x0 24.--27. "BRP,Number of Breakpoint Register Pairs" "Reserved,Reserved,Reserved,Reserved,Reserved,6,?..." bitfld.long 0x0 20.--23. "CTX_CMP,Number of BRPs with Context ID Comparison Capability" "Reserved,2,?..." newline bitfld.long 0x00 16.--19. "VERSION,Debug architecture version" "Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,v8.2,?..." bitfld.long 0x0 14. "NSUHD,Secure User halting debug-mode" "Reserved,Not supported" bitfld.long 0x0 12. "SE,Security Extensions implemented" "Reserved,Implemented" endif rgroup.long c14:0x0060++0x0 line.long 0x00 "DBGWFAR,Watchpoint Fault Address Register" group.long c14:0x0070++0x0 line.long 0x00 "DBGVCR,Debug Vector Catch register" bitfld.long 0x00 31. "FIQVCE_NS,FIQ vector catch in Non-secure state" "Disabled,Enabled" bitfld.long 0x00 30. "IRQVCE_NS,IRG vector catch in Non-secure state" "Disabled,Enabled" bitfld.long 0x00 28. "DAVCE_NS,Data Abort vector catch in Non-secure state" "Disabled,Enabled" newline bitfld.long 0x00 27. "PAVCE_NS,Prefetch Abort vector catch in Non-secure state" "Disabled,Enabled" bitfld.long 0x00 26. "SVCVCE_NS,SVC vector catch in Non-secure state" "Disabled,Enabled" bitfld.long 0x00 25. "UIVCE_NS,Undefined instruction vector catch in Non-secure state" "Disabled,Enabled" newline bitfld.long 0x00 23. "FIQ,HVBAR: FIQ" "Disabled,Enabled" bitfld.long 0x00 22. "IRQ,HVBAR: IRQ" "Disabled,Enabled" bitfld.long 0x00 21. "HEE,HVBAR: Hyp Entry Exception" "Disabled,Enabled" newline bitfld.long 0x00 20. "DA,HVBAR: Data Abort" "Disabled,Enabled" bitfld.long 0x00 19. "PA,HVBAR: Prefetch Abort" "Disabled,Enabled" bitfld.long 0x00 18. "HVC,HVBAR: HVC" "Disabled,Enabled" newline bitfld.long 0x00 17. "UI,HVBAR: Undefined Instruction" "Disabled,Enabled" bitfld.long 0x00 15. "FIQVCE_SM,FIQ vector catch enable, in Secure state on Monitor mode vector" "Disabled,Enabled" bitfld.long 0x00 14. "IRQVCE_SM,IRQ vector catch enable in Secure state on Monitor mode vector" "Disabled,Enabled" newline bitfld.long 0x00 12. "DAVCE_SM,Data Abort vector catch enable in Secure state on Monitor mode vector" "Disabled,Enabled" bitfld.long 0x00 11. "PAVCE_SM,Prefetch Abort vector catch enable in Secure state on Monitor mode vector" "Disabled,Enabled" bitfld.long 0x00 10. "SMCVCE_S,SMC vector catch enable in Secure state" "Disabled,Enabled" newline bitfld.long 0x00 7. "FIQVCE_S,FIQ vector catch in Secure state" "Disabled,Enabled" bitfld.long 0x00 6. "IRQVCE_S,IRG vector catch in Secure state" "Disabled,Enabled" bitfld.long 0x00 4. "DAVCE_S,Data Abort vector catch in Secure state" "Disabled,Enabled" newline bitfld.long 0x00 3. "PAVCE_S,Prefetch Abort vector catch in Secure state" "Disabled,Enabled" bitfld.long 0x00 2. "SVCVCE_S,SVC vector catch in Secure state" "Disabled,Enabled" bitfld.long 0x00 1. "UIVCE_S,Undefined instruction vector catch in Secure state" "Disabled,Enabled" newline bitfld.long 0x00 0. "RVCE,Reset vector catch enable" "Disabled,Enabled" group.long c14:0x0200++0x0 line.long 0x00 "DBGDTRRXEXT,Debug Receive Register (External View)" rgroup.long c14:0x0050++0x0 line.long 0x00 "DBGDTRRXINT,Debug Receive Register (Internal View)" group.long c14:0x0020++0x00 line.long 0x00 "DBGDCCINT,Debug Comms Channel Interrupt Enable register" bitfld.long 0x00 30. "RX,DCC interrupt enable controls" "Disabled,Enabled" bitfld.long 0x00 29. "TX,DCC interrupt enable controls" "Disabled,Enabled" ; For DBGDSCRint, bits 28 - 19, 14 - 13, 11 - 6, 1 - 0 are RES0. ; DBGDSCRint is read only. rgroup.long c14:0x0010++0x0 line.long 0x00 "DBGDSCRINT,Debug Status and Control Register (Internal View)" bitfld.long 0x00 30. "RXFULL,DBGDTRRX Register full" "Empty,Full" bitfld.long 0x00 29. "TXFULL,DBGDTRTX Register full" "Empty,Full" bitfld.long 0x00 18. "NS,Non-secure status bit" "Secure,Non-secure" newline bitfld.long 0x00 17. "SPNIDDIS,Secure Privileged Non-Invasive Debug Disable" "No,Yes" bitfld.long 0x00 16. "SPIDDIS,Secure Privileged Invasive Debug Disable" "No,Yes" bitfld.long 0x00 15. "MDBGEN,Monitor debug-mode enable" "Disabled,Enabled" newline bitfld.long 0x00 12. "UDCCDIS,User mode access to Communications Channel disable" "No,Yes" bitfld.long 0x00 2.--5. "MOE,Method of debug entry field" "Reserved,Breakpoint,Reserved,Software Breakpoint (BKPT),Reserved,Vector Catch,Reserved,Reserved,Reserved,Reserved,Watchpoint,?..." ; For DBGDSCRext, bits 25 - 24, 20, 13, 11 - 7, 1 - 0 are RES0. ; DBGDSCRext is read/write only. group.long c14:0x0220++0x0 line.long 0x00 "DBGDSCREXT,Debug Status and Control Register (External View)" bitfld.long 0x00 30. "RXFULL,DBGDTRRX Register full" "Empty,Full" bitfld.long 0x00 29. "TXFULL,DBGDTRTX Register full" "Empty,Full" bitfld.long 0x00 27. "RXO,DBGDTRRX overflow" "No overflow,Overflow" newline bitfld.long 0x00 26. "TXU,DBGDTRTX underflow" "No underflow,Underflow" bitfld.long 0x00 22.--23. "INTDIS,Interrupt disable" "Don't disable interrupts,Disable interrupts targeting non-sec EL1,Disable interrupts targeting EL1 & EL2,Disable all interrupts" bitfld.long 0x00 21. "TDA,Trap debug register access" "No trap,Trap" newline bitfld.long 0x00 19. "SC2,Sample CONTEXTIDR_EL2" "VTTBR_EL2.VMID,CONTEXTIDR_EL2" bitfld.long 0x00 18. "NS,Non-secure status bit" "Secure,Non-secure" bitfld.long 0x00 17. "SPNIDDIS,Secure Privileged Non-Invasive Debug Disable" "No,Yes" newline bitfld.long 0x00 16. "SPIDDIS,Secure Privileged Invasive Debug Disable" "No,Yes" bitfld.long 0x00 15. "MDBGEN,Monitor debug-mode enable" "Disabled,Enabled" bitfld.long 0x00 14. "HDE,Halting debug-mode" "Disabled,Enabled" newline bitfld.long 0x00 12. "UDCCDIS,User mode access to Communications Channel disable" "No,Yes" bitfld.long 0x00 7. "ADABORT,Asynchronous data abort" "Not aborted,Aborted" bitfld.long 0x00 6. "ERR,Cumulative error flag" "Not error,Error" newline bitfld.long 0x00 2.--5. "MOE,Method of debug entry field" "Reserved,Breakpoint,Reserved,Software Breakpoint (BKPT),Reserved,Vector Catch,Reserved,Reserved,Reserved,Reserved,Watchpoint,?..." group.long c14:0x0230++0x0 line.long 0x00 "DBGDTRTXEXT,Debug Transmit Register (External View)" wgroup.long c14:0x0050++0x0 line.long 0x00 "DBGDTRTXINT,Debug Transmit Register (Internal View)" if (((per.l(c14:0x0411))&0x2)==0x2) group.long c14:0x0260++0x0 line.long 0x0 "DBGOSECCR,Debug OS Lock Exception Catch Control Register" else rgroup.long c14:0x0260++0x0 line.long 0x0 "DBGOSECCR,Debug OS Lock Exception Catch Control Register" endif rgroup.long c14:0x0707++0x0 line.long 0x0 "DBGDEVID2,Debug Device ID Register 2" rgroup.long c14:0x0717++0x0 line.long 0x0 "DBGDEVID1,Debug Device ID Register 1" rgroup.long c14:0x0727++0x0 line.long 0x0 "DBGDEVID,Debug Device ID Register 0" bitfld.long 0x0 28.--31. "CIDMASK,Level of support for the Context ID matching breakpoint masking capability" "Not implemented,?..." bitfld.long 0x0 24.--27. "AR,Debug External Auxiliary Control Register support status" "Not supported,?..." bitfld.long 0x0 20.--23. "DL,Support for Debug OS Double Lock Register" "Reserved,Supported,?..." newline bitfld.long 0x0 16.--19. "VE,Specifies implementation of Virtualization Extension" "Reserved,Implemented,?..." bitfld.long 0x0 12.--15. "VC,Form of the vector catch event implemented" "Implemented,?..." bitfld.long 0x0 8.--11. "BPAM,Level of support for Immediate Virtual Address matching breakpoint masking capability" "Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Not implemented" newline bitfld.long 0x0 4.--7. "WPAM,Level of support for the DVA matching watchpoint masking capability" "Reserved,Implemented,?..." tree.end newline rgroup.quad c14:0x10010++0x1 line.quad 0x0 "DBGDRAR,Debug ROM Address Register" rgroup.quad c14:0x10020++0x1 line.quad 0x0 "DBGDSAR,Debug Self Address Offset Register" wgroup.long c14:0x0401++0x00 line.long 0x00 "DBGOSLAR,Operating System Lock Access Register" rgroup.long c14:0x0411++0x00 line.long 0x00 "DBGOSLSR,Operating System Lock Status Register" bitfld.long 0x00 2. "NTT,32-Bit Access" "Not required,Required" bitfld.long 0x00 1. "OSLK,Status of the OS Lock" "Not locked,Locked" bitfld.long 0x00 0. 3. "OSLM,OS Lock Model implemented Bit" "Reserved,Reserved,Implemented,?..." group.long c14:0x0431++0x00 line.long 0x00 "DBGOSDLR,OS Double-lock Register" bitfld.long 0x00 0. "DLK,OS double-lock control" "Not locked,Locked" group.long c14:0x0441++0x00 line.long 0x00 "DBGPRCR,Device Power-Down and Reset Control Register" bitfld.long 0x00 0. "CORENPDRQ,Core No Power down Request" "Powered down,Emulated" group.long c14:0x0687++0x00 line.long 0x00 "DBGCLAIMSET,Claim Tag register Set" bitfld.long 0x0 7. "CT7,Claim Tag 7 Set" "Not set,Set" bitfld.long 0x0 6. "CT6,Claim Tag 6 Set" "Not set,Set" bitfld.long 0x0 5. "CT5,Claim Tag 5 Set" "Not set,Set" newline bitfld.long 0x0 4. "CT4,Claim Tag 4 Set" "Not set,Set" bitfld.long 0x0 3. "CT3,Claim Tag 3 Set" "Not set,Set" bitfld.long 0x0 2. "CT2,Claim Tag 2 Set" "Not set,Set" newline bitfld.long 0x0 1. "CT1,Claim Tag 1 Set" "Not set,Set" bitfld.long 0x0 0. "CT0,Claim Tag 0 Set" "Not set,Set" group.long c14:0x0697++0x00 line.long 0x00 "DBGCLAIMCLR,Claim Tag register Clear" bitfld.long 0x0 7. "CT7,Claim Tag 7 Clear" "Not cleared,Cleared" bitfld.long 0x0 6. "CT6,Claim Tag 6 Clear" "Not cleared,Cleared" bitfld.long 0x0 5. "CT5,Claim Tag 5 Clear" "Not cleared,Cleared" newline bitfld.long 0x0 4. "CT4,Claim Tag 4 Clear" "Not cleared,Cleared" bitfld.long 0x0 3. "CT3,Claim Tag 3 Clear" "Not cleared,Cleared" bitfld.long 0x0 2. "CT2,Claim Tag 2 Clear" "Not cleared,Cleared" newline bitfld.long 0x0 1. "CT1,Claim Tag 1 Clear" "Not cleared,Cleared" bitfld.long 0x0 0. "CT0,Claim Tag 0 Clear" "Not cleared,Cleared" rgroup.long c14:0x06E7++0x00 line.long 0x00 "DBGAUTHSTATUS,Authentication Status register" bitfld.long 0x00 7. "SNI,Secure non-invasive debug implemented" "Not implemented,Implemented" bitfld.long 0x00 6. "SNE,Secure non-invasive debug enabled" "Disabled,Enabled" bitfld.long 0x00 5. "SI,Secure invasive debug implemented" "Not implemented,Implemented" newline bitfld.long 0x00 4. "SE,Secure invasive debug enabled" "Disabled,Enabled" bitfld.long 0x00 3. "NSNI,Non-secure non-invasive debug implemented" "Not implemented,Implemented" bitfld.long 0x00 2. "NSNE,Non-secure non-invasive debug enabled" "Disabled,Enabled" newline bitfld.long 0x00 1. "NSI,Non-secure invasive debug implemented" "Not implemented,Implemented" bitfld.long 0x00 0. "NSE,Non-secure invasive debug enabled" "Disabled,Enabled" rgroup.long c14:0x7000++0x00 "Jazelle Registers" line.long 0x0 "JIDR,Jazelle ID Register" rgroup.long c14:0x7001++0x00 line.long 0x0 "JOSCR,Jazelle OS Control Register" rgroup.long c14:0x7002++0x00 line.long 0x0 "JMCR,Jazelle Main Configuration Register" tree.end tree "Breakpoint Registers" tree "Breakpoint 0" group.long c14:(0x0400+0x0)++0x00 line.long 0x00 "DBGBVR0,Breakpoint Value Register" group.long c14:(0x0500+0x0)++0x00 line.long 0x00 "DBGBCR0,Breakpoint Control Register" bitfld.long 0x00 20.--23. "BT,Breakpoint type" "Unlinked address match,Linked address match,Unlinked Context ID match,Linked Context ID match,Unlinked address mismatch,Linked address mismatch,Unlinked CONTEXTIDR_EL1 match,Linked CONTEXTIDR_EL1 match,Unlinked VMID match,Linked VMID match,Unlinked VMID + Context ID match,Linked VMID + Context ID match,Unlinked CONTEXTIDR_EL2 match,Linked CONTEXTIDR_EL2 match,Unlinked Full Context ID match,Linked Full Context ID match" bitfld.long 0x00 16.--19. "LBN,Linked breakpoint number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 14.--15. "SSC,Security state control" "Both,Non-secure,Secure,?..." newline bitfld.long 0x00 13. "HMC,Hyp mode control" "Disabled,Enabled" bitfld.long 0x0 5.--8. "BAS,Byte address select" "Reserved,Reserved,Reserved,T32/DBGBVRn,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,T32/DBGBVRn+2,Reserved,Reserved,A64/A32/DBGBVRn" bitfld.long 0x00 1.--2. "PMC,Privileged mode control" "User/System/Supervisor,Privileged,User only,Any mode" newline bitfld.long 0x00 0. "E,Breakpoint enable" "Disabled,Enabled" tree.end tree "Breakpoint 1" group.long c14:(0x0400+0x10)++0x00 line.long 0x00 "DBGBVR1,Breakpoint Value Register" group.long c14:(0x0500+0x10)++0x00 line.long 0x00 "DBGBCR1,Breakpoint Control Register" bitfld.long 0x00 20.--23. "BT,Breakpoint type" "Unlinked address match,Linked address match,Unlinked Context ID match,Linked Context ID match,Unlinked address mismatch,Linked address mismatch,Unlinked CONTEXTIDR_EL1 match,Linked CONTEXTIDR_EL1 match,Unlinked VMID match,Linked VMID match,Unlinked VMID + Context ID match,Linked VMID + Context ID match,Unlinked CONTEXTIDR_EL2 match,Linked CONTEXTIDR_EL2 match,Unlinked Full Context ID match,Linked Full Context ID match" bitfld.long 0x00 16.--19. "LBN,Linked breakpoint number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 14.--15. "SSC,Security state control" "Both,Non-secure,Secure,?..." newline bitfld.long 0x00 13. "HMC,Hyp mode control" "Disabled,Enabled" bitfld.long 0x0 5.--8. "BAS,Byte address select" "Reserved,Reserved,Reserved,T32/DBGBVRn,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,T32/DBGBVRn+2,Reserved,Reserved,A64/A32/DBGBVRn" bitfld.long 0x00 1.--2. "PMC,Privileged mode control" "User/System/Supervisor,Privileged,User only,Any mode" newline bitfld.long 0x00 0. "E,Breakpoint enable" "Disabled,Enabled" tree.end tree "Breakpoint 2" group.long c14:(0x0400+0x20)++0x00 line.long 0x00 "DBGBVR2,Breakpoint Value Register" group.long c14:(0x0500+0x20)++0x00 line.long 0x00 "DBGBCR2,Breakpoint Control Register" bitfld.long 0x00 20.--23. "BT,Breakpoint type" "Unlinked address match,Linked address match,Unlinked Context ID match,Linked Context ID match,Unlinked address mismatch,Linked address mismatch,Unlinked CONTEXTIDR_EL1 match,Linked CONTEXTIDR_EL1 match,Unlinked VMID match,Linked VMID match,Unlinked VMID + Context ID match,Linked VMID + Context ID match,Unlinked CONTEXTIDR_EL2 match,Linked CONTEXTIDR_EL2 match,Unlinked Full Context ID match,Linked Full Context ID match" bitfld.long 0x00 16.--19. "LBN,Linked breakpoint number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 14.--15. "SSC,Security state control" "Both,Non-secure,Secure,?..." newline bitfld.long 0x00 13. "HMC,Hyp mode control" "Disabled,Enabled" bitfld.long 0x0 5.--8. "BAS,Byte address select" "Reserved,Reserved,Reserved,T32/DBGBVRn,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,T32/DBGBVRn+2,Reserved,Reserved,A64/A32/DBGBVRn" bitfld.long 0x00 1.--2. "PMC,Privileged mode control" "User/System/Supervisor,Privileged,User only,Any mode" newline bitfld.long 0x00 0. "E,Breakpoint enable" "Disabled,Enabled" tree.end tree "Breakpoint 3" group.long c14:(0x0400+0x30)++0x00 line.long 0x00 "DBGBVR3,Breakpoint Value Register" group.long c14:(0x0500+0x30)++0x00 line.long 0x00 "DBGBCR3,Breakpoint Control Register" bitfld.long 0x00 20.--23. "BT,Breakpoint type" "Unlinked address match,Linked address match,Unlinked Context ID match,Linked Context ID match,Unlinked address mismatch,Linked address mismatch,Unlinked CONTEXTIDR_EL1 match,Linked CONTEXTIDR_EL1 match,Unlinked VMID match,Linked VMID match,Unlinked VMID + Context ID match,Linked VMID + Context ID match,Unlinked CONTEXTIDR_EL2 match,Linked CONTEXTIDR_EL2 match,Unlinked Full Context ID match,Linked Full Context ID match" bitfld.long 0x00 16.--19. "LBN,Linked breakpoint number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 14.--15. "SSC,Security state control" "Both,Non-secure,Secure,?..." newline bitfld.long 0x00 13. "HMC,Hyp mode control" "Disabled,Enabled" bitfld.long 0x0 5.--8. "BAS,Byte address select" "Reserved,Reserved,Reserved,T32/DBGBVRn,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,T32/DBGBVRn+2,Reserved,Reserved,A64/A32/DBGBVRn" bitfld.long 0x00 1.--2. "PMC,Privileged mode control" "User/System/Supervisor,Privileged,User only,Any mode" newline bitfld.long 0x00 0. "E,Breakpoint enable" "Disabled,Enabled" tree.end tree "Breakpoint 4" group.long c14:(0x0400+0x40)++0x00 line.long 0x00 "DBGBVR4,Breakpoint Value Register" group.long c14:(0x0101+0x40)++0x00 line.long 0x00 "DBGBXVR4,Breakpoint Extended Value Register" group.long c14:(0x0500+0x40)++0x00 line.long 0x00 "DBGBCR4,Breakpoint Control Register" bitfld.long 0x00 20.--23. "BT,Breakpoint type" "Unlinked address match,Linked address match,Unlinked Context ID match,Linked Context ID match,Unlinked address mismatch,Linked address mismatch,Unlinked CONTEXTIDR_EL1 match,Linked CONTEXTIDR_EL1 match,Unlinked VMID match,Linked VMID match,Unlinked VMID + Context ID match,Linked VMID + Context ID match,Unlinked CONTEXTIDR_EL2 match,Linked CONTEXTIDR_EL2 match,Unlinked Full Context ID match,Linked Full Context ID match" bitfld.long 0x00 16.--19. "LBN,Linked breakpoint number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 14.--15. "SSC,Security state control" "Both,Non-secure,Secure,?..." newline bitfld.long 0x00 13. "HMC,Hyp mode control" "Disabled,Enabled" bitfld.long 0x0 5.--8. "BAS,Byte address select" "Reserved,Reserved,Reserved,T32/DBGBVRn,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,T32/DBGBVRn+2,Reserved,Reserved,A64/A32/DBGBVRn" bitfld.long 0x00 1.--2. "PMC,Privileged mode control" "User/System/Supervisor,Privileged,User only,Any mode" newline bitfld.long 0x00 0. "E,Breakpoint enable" "Disabled,Enabled" tree.end tree "Breakpoint 5" group.long c14:(0x0400+0x50)++0x00 line.long 0x00 "DBGBVR5,Breakpoint Value Register" group.long c14:(0x0101+0x50)++0x00 line.long 0x00 "DBGBXVR5,Breakpoint Extended Value Register" group.long c14:(0x0500+0x50)++0x00 line.long 0x00 "DBGBCR5,Breakpoint Control Register" bitfld.long 0x00 20.--23. "BT,Breakpoint type" "Unlinked address match,Linked address match,Unlinked Context ID match,Linked Context ID match,Unlinked address mismatch,Linked address mismatch,Unlinked CONTEXTIDR_EL1 match,Linked CONTEXTIDR_EL1 match,Unlinked VMID match,Linked VMID match,Unlinked VMID + Context ID match,Linked VMID + Context ID match,Unlinked CONTEXTIDR_EL2 match,Linked CONTEXTIDR_EL2 match,Unlinked Full Context ID match,Linked Full Context ID match" bitfld.long 0x00 16.--19. "LBN,Linked breakpoint number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 14.--15. "SSC,Security state control" "Both,Non-secure,Secure,?..." newline bitfld.long 0x00 13. "HMC,Hyp mode control" "Disabled,Enabled" bitfld.long 0x0 5.--8. "BAS,Byte address select" "Reserved,Reserved,Reserved,T32/DBGBVRn,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,T32/DBGBVRn+2,Reserved,Reserved,A64/A32/DBGBVRn" bitfld.long 0x00 1.--2. "PMC,Privileged mode control" "User/System/Supervisor,Privileged,User only,Any mode" newline bitfld.long 0x00 0. "E,Breakpoint enable" "Disabled,Enabled" tree.end tree.end tree "Watchpoint Registers" tree "Watchpoint 0" group.long c14:(0x0600+0x0)++0x00 line.long 0x00 "DBGWVR0,Watchpoint Value Register" hexmask.long 0x00 2.--31. 0x4 "ADDRESS,Data address" group.long c14:(0x0700+0x0)++0x00 line.long 0x00 "DBGWCR0,Watchpoint Control Register" bitfld.long 0x00 24.--28. "MASK,Address mask" "No mask,Reserved,Reserved,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 20. "WT,Watchpoint type" "Unlinked,Linked" bitfld.long 0x00 16.--19. "LBN,Linked breakpoint number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 14.--15. "SSC,Security state control" "Both,Non-secure,Secure,?..." bitfld.long 0x00 13. "HMC,Hyp mode control" "Disabled,Enabled" hexmask.long.byte 0x00 5.--12. 1. "BAS,Byte address select" newline bitfld.long 0x00 3.--4. "LSC,Load/store control" "Reserved,Load,Store,Both" bitfld.long 0x00 1.--2. "PAC,Privileged mode control" "User/System/Supervisor,Privileged,User only,Any mode" bitfld.long 0x00 0. "E,Enable" "Disabled,Enabled" tree.end tree "Watchpoint 1" group.long c14:(0x0600+0x10)++0x00 line.long 0x00 "DBGWVR1,Watchpoint Value Register" hexmask.long 0x00 2.--31. 0x4 "ADDRESS,Data address" group.long c14:(0x0700+0x10)++0x00 line.long 0x00 "DBGWCR1,Watchpoint Control Register" bitfld.long 0x00 24.--28. "MASK,Address mask" "No mask,Reserved,Reserved,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 20. "WT,Watchpoint type" "Unlinked,Linked" bitfld.long 0x00 16.--19. "LBN,Linked breakpoint number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 14.--15. "SSC,Security state control" "Both,Non-secure,Secure,?..." bitfld.long 0x00 13. "HMC,Hyp mode control" "Disabled,Enabled" hexmask.long.byte 0x00 5.--12. 1. "BAS,Byte address select" newline bitfld.long 0x00 3.--4. "LSC,Load/store control" "Reserved,Load,Store,Both" bitfld.long 0x00 1.--2. "PAC,Privileged mode control" "User/System/Supervisor,Privileged,User only,Any mode" bitfld.long 0x00 0. "E,Enable" "Disabled,Enabled" tree.end tree "Watchpoint 2" group.long c14:(0x0600+0x20)++0x00 line.long 0x00 "DBGWVR2,Watchpoint Value Register" hexmask.long 0x00 2.--31. 0x4 "ADDRESS,Data address" group.long c14:(0x0700+0x20)++0x00 line.long 0x00 "DBGWCR2,Watchpoint Control Register" bitfld.long 0x00 24.--28. "MASK,Address mask" "No mask,Reserved,Reserved,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 20. "WT,Watchpoint type" "Unlinked,Linked" bitfld.long 0x00 16.--19. "LBN,Linked breakpoint number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 14.--15. "SSC,Security state control" "Both,Non-secure,Secure,?..." bitfld.long 0x00 13. "HMC,Hyp mode control" "Disabled,Enabled" hexmask.long.byte 0x00 5.--12. 1. "BAS,Byte address select" newline bitfld.long 0x00 3.--4. "LSC,Load/store control" "Reserved,Load,Store,Both" bitfld.long 0x00 1.--2. "PAC,Privileged mode control" "User/System/Supervisor,Privileged,User only,Any mode" bitfld.long 0x00 0. "E,Enable" "Disabled,Enabled" tree.end tree "Watchpoint 3" group.long c14:(0x0600+0x30)++0x00 line.long 0x00 "DBGWVR3,Watchpoint Value Register" hexmask.long 0x00 2.--31. 0x4 "ADDRESS,Data address" group.long c14:(0x0700+0x30)++0x00 line.long 0x00 "DBGWCR3,Watchpoint Control Register" bitfld.long 0x00 24.--28. "MASK,Address mask" "No mask,Reserved,Reserved,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 20. "WT,Watchpoint type" "Unlinked,Linked" bitfld.long 0x00 16.--19. "LBN,Linked breakpoint number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 14.--15. "SSC,Security state control" "Both,Non-secure,Secure,?..." bitfld.long 0x00 13. "HMC,Hyp mode control" "Disabled,Enabled" hexmask.long.byte 0x00 5.--12. 1. "BAS,Byte address select" newline bitfld.long 0x00 3.--4. "LSC,Load/store control" "Reserved,Load,Store,Both" bitfld.long 0x00 1.--2. "PAC,Privileged mode control" "User/System/Supervisor,Privileged,User only,Any mode" bitfld.long 0x00 0. "E,Enable" "Disabled,Enabled" tree.end tree.end tree "DynamIQ Shared Unit" tree "Cluster Control Registers" if (((per.l(c15:0x003F))&0x2000)==0x00) rgroup.long c15:0x003F++0x00 line.long 0x00 "CLUSTERCFR,Cluster Configuration Register" bitfld.long 0x00 24.--27. "NPE,Number of processing elements" "1,2,?..." newline bitfld.long 0x00 17. "CRSP3,Core 3 Register slice present" "Not present,Present" bitfld.long 0x00 16. "CRSP2,Core 2 Register slice present" "Not present,Present" bitfld.long 0x00 15. "CRSP1,Core 1 Register slice present" "Not present,Present" newline bitfld.long 0x00 14. "CRSP0,Core 0 Register slice present" "Not present,Present" bitfld.long 0x00 13. "BUS_INTERFACE_EXT,Bus interface extended" "Not extended,Extended" bitfld.long 0x00 12. "PPP,Peripheral port present" "Not present,Present" newline bitfld.long 0x00 11. "ACP,ACP interface present" "Not present,Present" bitfld.long 0x00 9.--10. "BUS_INTERFACE,Bus interface configuration" "Single 128-bit ACE,Dual 128-bit ACE,Single 128-bit CHI,Single 256-bit CHI" bitfld.long 0x00 8. "SCU_L3_ECC,SCU-L3 is configured with ECC" "No ECC,ECC" newline bitfld.long 0x00 7. "L3_DATA_RAM_RS,L3 data RAM Register slice present" "Not present,Present" bitfld.long 0x00 6. "L3_DATA_RAM_RL,L3 data RAM read latency" "2 cycles,3 cycles" bitfld.long 0x00 5. "L3_DATA_RAM_WL,L3 data RAM write latency" "1 cycle,2 cycles" newline bitfld.long 0x00 4. "L3_CACHE_PRESENT,L3 cache present" "Not present,Present" bitfld.long 0x00 0.--2. "NOC,Number of cores present in the cluster" "1,2,3,4,?..." else rgroup.long c15:0x003F++0x00 line.long 0x00 "CLUSTERCFR,Cluster Configuration Register" bitfld.long 0x00 24.--27. "NPE,Number of processing elements" "1,2,?..." newline bitfld.long 0x00 17. "CRSP3,Core 3 Register slice present" "Not present,Present" bitfld.long 0x00 16. "CRSP2,Core 2 Register slice present" "Not present,Present" bitfld.long 0x00 15. "CRSP1,Core 1 Register slice present" "Not present,Present" newline bitfld.long 0x00 14. "CRSP0,Core 0 Register slice present" "Not present,Present" bitfld.long 0x00 13. "BUS_INTERFACE_EXT,Bus interface extended" "Not extended,Extended" bitfld.long 0x00 12. "PPP,Peripheral port present" "Not present,Present" newline bitfld.long 0x00 11. "ACP,ACP interface present" "Not present,Present" bitfld.long 0x00 9.--10. "BUS_INTERFACE,Bus interface configuration" "Single 128-bit ACE,Dual 128-bit ACE,Single 128-bit CHI,Dual 256-bit CHI" bitfld.long 0x00 8. "SCU_L3_ECC,SCU-L3 is configured with ECC" "No ECC,ECC" newline bitfld.long 0x00 7. "L3_DATA_RAM_RS,L3 data RAM Register slice present" "Not present,Present" bitfld.long 0x00 6. "L3_DATA_RAM_RL,L3 data RAM read latency" "2 cycles,3 cycles" bitfld.long 0x00 5. "L3_DATA_RAM_WL,L3 data RAM write latency" "1 cycle,2 cycles" newline bitfld.long 0x00 4. "L3_CACHE_PRESENT,L3 cache present" "Not present,Present" bitfld.long 0x00 0.--2. "NOC,Number of cores present in the cluster" "1,2,3,4,?..." endif rgroup.long c15:0x013F++0x00 line.long 0x00 "CLUSTERIDR,Cluster Main Revision ID" hexmask.long.byte 0x00 4.--7. 1. "VARIANT,Indicates the variant of the DSU" hexmask.long.byte 0x00 0.--3. 1. "REVISION,Indicates the minor revision number of the DSU" rgroup.long c15:0x023F++0x00 line.long 0x00 "CLUSTERREVIDR,Cluster ECO ID" rgroup.long c15:0x033F++0x00 line.long 0x00 "CLUSTERACTLR,Cluster Auxiliary Control Register" if (((per.l(c15:0x003F))&0x600)==(0x00||0x200)) group.long c15:0x043F++0x00 line.long 0x00 "CLUSTERECTLR,Cluster Extended Control Register" bitfld.long 0x00 14. "CUEC,Cache UniqueClean eviction control" "Disabled,Enabled" bitfld.long 0x00 8.--10. "PMD,Prefetch matching delay" "1,2,4,8,16,32,64,128" bitfld.long 0x00 7. "DICA,Disable interconnect cacheable atomics" "No,Yes" newline bitfld.long 0x00 4. "IDPS,Interconnect data poisoning support" "Not supported,Supported" bitfld.long 0x00 3. "CTEC,Clean/evict to external control disable" "No,Yes" bitfld.long 0x00 2. "CFUCEC,Cache flush UniqueClean eviction control" "No,Yes" newline bitfld.long 0x00 0. "DNCWL,Disable non-cacheable write limit" "No,Yes" else group.long c15:0x043F++0x00 line.long 0x00 "CLUSTERECTLR,Cluster Extended Control Register" bitfld.long 0x00 14. "CUEC,Cache UniqueClean eviction control" "Disabled,Enabled" bitfld.long 0x00 8.--10. "PMD,Prefetch matching delay" "1,2,4,8,16,32,64,128" bitfld.long 0x00 7. "DICA,Disable interconnect cacheable atomics" "No,Yes" newline bitfld.long 0x00 4. "IDPS,Interconnect data poisoning support" "Not supported,Supported" bitfld.long 0x00 3. "CTEC,Clean/evict to external control disable" "No,Yes" bitfld.long 0x00 2. "CFUCEC,Cache flush UniqueClean eviction control" "No,Yes" endif group.long c15:0x053F++0x00 line.long 0x00 "CLUSTERPWRCTLR,Cluster Power Control Register" bitfld.long 0x00 4.--7. "CPPR,Cache portion power request" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--2. "FUNC_RET_CTRL,Duration of inactivity before the DSU uses CLUSTERPACTIVE" "Disabled,2 AT ticks,8 AT ticks,32 AT ticks,64 AT ticks,128 AT ticks,256 AT ticks,512 AT ticks" group.long c15:0x063F++0x00 line.long 0x00 "CLUSTERPWRDN,Cluster Power Down Register" bitfld.long 0x00 1. "MRR,Memory retention required" "Not required,Required" bitfld.long 0x00 0. "CPR,Cluster power required" "Not required,Required" rgroup.long c15:0x073F++0x00 line.long 0x00 "CLUSTERPWRSTAT,Cluster Power Status Register" bitfld.long 0x00 4.--7. "CPPS,This bits indicates which cache portions are currently powered up and available" "No ways,Ways 0-3,Reserved,Ways 0-7,Reserved,Reserved,Reserved,Ways 0-11,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Reserved,Ways 0-15" bitfld.long 0x00 1. "RWPD,Enabled memory retention when all cores are powered down" "Disabled,Enabled" bitfld.long 0x00 0. "DCPD,Disabled cluster power down when all cores are powered down" "No,Yes" group.long c15:0x004F++0x00 line.long 0x00 "CLUSTERTHREADSID,Cluster Thread Scheme ID Register" bitfld.long 0x00 0.--2. "SCHEME_ID_THREAD,Scheme ID for current thread" "0,1,2,3,4,5,6,7" group.long c15:0x014F++0x00 line.long 0x00 "CLUSTERACPSID,Cluster ACP Scheme ID Register" bitfld.long 0x00 0.--2. "SCHEME_ID_ACP,Scheme ID for ACP transactions" "0,1,2,3,4,5,6,7" group.long c15:0x024F++0x00 line.long 0x00 "CLUSTERSTASHSID,Cluster Stash Scheme ID Register" bitfld.long 0x00 0.--2. "SCHEME_ID_SR,Scheme ID for stash requests received from the interconnect" "0,1,2,3,4,5,6,7" group.long c15:0x034F++0x00 line.long 0x00 "CLUSTERPARTCR,Cluster Partition Control Register" bitfld.long 0x00 31. "W3_ID7,Way group 3 is assigned as private to scheme ID 7" "Not assigned,Assigned" bitfld.long 0x00 30. "W2_ID7,Way group 2 is assigned as private to scheme ID 7" "Not assigned,Assigned" bitfld.long 0x00 29. "W1_ID7,Way group 1 is assigned as private to scheme ID 7" "Not assigned,Assigned" newline bitfld.long 0x00 28. "W0_ID7,Way group 0 is assigned as private to scheme ID 7" "Not assigned,Assigned" bitfld.long 0x00 27. "W3_ID6,Way group 3 is assigned as private to scheme ID 6" "Not assigned,Assigned" bitfld.long 0x00 26. "W2_ID6,Way group 2 is assigned as private to scheme ID 6" "Not assigned,Assigned" newline bitfld.long 0x00 25. "W1_ID6,Way group 1 is assigned as private to scheme ID 6" "Not assigned,Assigned" bitfld.long 0x00 24. "W0_ID6,Way group 0 is assigned as private to scheme ID 6" "Not assigned,Assigned" bitfld.long 0x00 23. "W3_ID5,Way group 3 is assigned as private to scheme ID 5" "Not assigned,Assigned" newline bitfld.long 0x00 22. "W2_ID5,Way group 2 is assigned as private to scheme ID 5" "Not assigned,Assigned" bitfld.long 0x00 21. "W1_ID5,Way group 1 is assigned as private to scheme ID 5" "Not assigned,Assigned" bitfld.long 0x00 20. "W0_ID5,Way group 0 is assigned as private to scheme ID 5" "Not assigned,Assigned" newline bitfld.long 0x00 19. "W3_ID4,Way group 3 is assigned as private to scheme ID 4" "Not assigned,Assigned" bitfld.long 0x00 18. "W2_ID4,Way group 2 is assigned as private to scheme ID 4" "Not assigned,Assigned" bitfld.long 0x00 17. "W1_ID4,Way group 1 is assigned as private to scheme ID 4" "Not assigned,Assigned" newline bitfld.long 0x00 16. "W0_ID4,Way group 0 is assigned as private to scheme ID 4" "Not assigned,Assigned" bitfld.long 0x00 15. "W3_ID3,Way group 3 is assigned as private to scheme ID 3" "Not assigned,Assigned" bitfld.long 0x00 14. "W2_ID3,Way group 2 is assigned as private to scheme ID 3" "Not assigned,Assigned" newline bitfld.long 0x00 13. "W1_ID3,Way group 1 is assigned as private to scheme ID 3" "Not assigned,Assigned" bitfld.long 0x00 12. "W0_ID3,Way group 0 is assigned as private to scheme ID 3" "Not assigned,Assigned" bitfld.long 0x00 11. "W3_ID2,Way group 3 is assigned as private to scheme ID 2" "Not assigned,Assigned" newline bitfld.long 0x00 10. "W2_ID2,Way group 2 is assigned as private to scheme ID 2" "Not assigned,Assigned" bitfld.long 0x00 9. "W1_ID2,Way group 1 is assigned as private to scheme ID 2" "Not assigned,Assigned" bitfld.long 0x00 8. "W0_ID2,Way group 0 is assigned as private to scheme ID 2" "Not assigned,Assigned" newline bitfld.long 0x00 7. "W3_ID1,Way group 3 is assigned as private to scheme ID 1" "Not assigned,Assigned" bitfld.long 0x00 6. "W2_ID1,Way group 2 is assigned as private to scheme ID 1" "Not assigned,Assigned" bitfld.long 0x00 5. "W1_ID1,Way group 1 is assigned as private to scheme ID 1" "Not assigned,Assigned" newline bitfld.long 0x00 4. "W0_ID1,Way group 0 is assigned as private to scheme ID 1" "Not assigned,Assigned" bitfld.long 0x00 3. "W3_ID0,Way group 3 is assigned as private to scheme ID 0" "Not assigned,Assigned" bitfld.long 0x00 2. "W2_ID0,Way group 2 is assigned as private to scheme ID 0" "Not assigned,Assigned" newline bitfld.long 0x00 1. "W1_ID0,Way group 1 is assigned as private to scheme ID 0" "Not assigned,Assigned" bitfld.long 0x00 0. "W0_ID0,Way group 0 is assigned as private to scheme ID 0" "Not assigned,Assigned" newline group.long c15:0x044F++0x00 line.long 0x00 "CLUSTERBUSQOS,Cluster Bus QoS Control Register" bitfld.long 0x00 28.--31. "CHI_BUS_QOS_SCHEME_ID7,Value driven on the CHI bus QoS field for scheme ID 7" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 24.--27. "CHI_BUS_QOS_SCHEME_ID6,Value driven on the CHI bus QoS field for scheme ID 6" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 20.--23. "CHI_BUS_QOS_SCHEME_ID5,Value driven on the CHI bus QoS field for scheme ID 5" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 16.--19. "CHI_BUS_QOS_SCHEME_ID4,Value driven on the CHI bus QoS field for scheme ID 4" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 12.--15. "CHI_BUS_QOS_SCHEME_ID3,Value driven on the CHI bus QoS field for scheme ID 3" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 8.--11. "CHI_BUS_QOS_SCHEME_ID2,Value driven on the CHI bus QoS field for scheme ID 2" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" newline bitfld.long 0x00 4.--7. "CHI_BUS_QOS_SCHEME_ID1,Value driven on the CHI bus QoS field for scheme ID 1" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.long 0x00 0.--3. "CHI_BUS_QOS_SCHEME_ID0,Value driven on the CHI bus QoS field for scheme ID 0" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" group.long c15:0x054F++0x00 line.long 0x00 "CLUSTERL3HIT,Cluster L3 Hit Counter Register" group.long c15:0x064F++0x00 line.long 0x00 "CLUSTERL3MISS,Cluster L3 Miss Counter Register" group.long c15:0x074F++0x00 line.long 0x00 "CLUSTERTHREADSIDOVR,Cluster Thread Scheme ID Override Register" bitfld.long 0x00 16.--18. "SCHEME_ID_MASK,A bit set in the mask causes the matching bit to be taken from this Register rather than from the CLUSTERTHREADSID_EL1 Register" "0,1,2,3,4,5,6,7" bitfld.long 0x00 0.--2. "SCHEME_ID_THREAD,Scheme ID for this thread if masked" "0,1,2,3,4,5,6,7" tree.end tree "Error System Registers" rgroup.long c15:0x0035++0x00 line.long 0x00 "ERRIDR,Error Record ID Register" hexmask.long.word 0x00 0.--15. 1. "NUM,Number of records that can be accessed through the Error Record system Registers" group.long c15:0x0135++0x00 line.long 0x00 "ERRSELR,Error Record Select Register" bitfld.long 0x00 0. "SEL,Selects the record accessed through the Error Record system Registers" "Record 0 - Core,Record 1 - DSU" if (((per.l(c15:0x0135))&0x01)==0x00) if CORENAME()=="CORTEXA55" rgroup.long c15:0x0345++0x00 line.long 0x00 "ERXADDR,Selected Error Record Address Register" rgroup.long c15:0x0745++0x00 line.long 0x00 "ERXADDR2,Selected Error Record Address Register 2" group.long c15:0x0145++0x00 line.long 0x00 "ERXCTLR,Selected Error Record Control Register" bitfld.long 0x00 8. "CFI,Fault handling interrupt for corrected errors enable" "Disabled,Enabled" bitfld.long 0x00 3. "FI,Fault handling interrupt enable" "Disabled,Enabled" bitfld.long 0x00 2. "UI,Uncorrected error recovery interrupt enable" "Disabled,Enabled" newline bitfld.long 0x00 0. "ED,Enable error detection" "Disabled,Enabled" rgroup.long c15:0x0545++0x00 line.long 0x00 "ERXCTLR2,Selected Error Record Control Register 2" rgroup.long c15:0x0045++0x00 line.long 0x00 "ERXFR,Selected Error Record Feature Register" bitfld.long 0x00 18.--19. "CEO,Previous error syndrome is kept on a second corrected error" "Yes,?..." bitfld.long 0x00 16.--17. "DUI,Error recovery interrupt for deferred errors" "Not supported,?..." bitfld.long 0x00 15. "RP,Indicates whether a repeat counter is implemented" "Reserved,1st and 2nd counter implemented" newline bitfld.long 0x00 12.--14. "CEC,Defines whether the node implements a standard CE counter mechanism in ERRMISC0" "Reserved,Reserved,8bit error counter,?..." bitfld.long 0x00 10.--11. "CFI,Fault handling interrupt for corrected errors" "Reserved,Reserved,Controllable,?..." bitfld.long 0x00 8.--9. "UE,Uncorrected error reporting" "Reserved,Supported,?..." newline bitfld.long 0x00 6.--7. "FI,Fault handling interrupt" "Reserved,Reserved,Controllable,?..." bitfld.long 0x00 4.--5. "UI,Uncorrected error recovery interrupt" "Reserved,Reserved,Controllable,?..." bitfld.long 0x00 2.--3. "DE,Deferred errors" "Reserved,Reserved,Controllable,?..." newline bitfld.long 0x00 0.--1. "ED,Error detection and correction" "Reserved,Reserved,Controllable,?..." rgroup.long c15:0x0445++0x00 line.long 0x00 "ERXFR2,Selected Error Record Feature Register 2" group.long c15:0x0055++0x00 line.long 0x00 "ERXMISC0,Selected Error Miscellaneous Register 0" bitfld.long 0x00 28.--31. "WAY,Indicates the way that contained the error" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.word 0x00 6.--18. 1. "INDX,Indicates the index that contained the error" newline bitfld.long 0x00 1.--3. "L,Indicates the level that contained the error" "Level 1,Level 2,?..." bitfld.long 0x00 0. "IND,Indicates the type of cache that contained the error" "Data cache(L1)/Unified cache(L2)/TLB,Instruction cache(L1)" group.long c15:0x0155++0x00 line.long 0x00 "ERXMISC1,Selected Error Miscellaneous Register 1" bitfld.long 0x00 15. "OFO,Other Error Count Overflow" "No overflow,Overflow" hexmask.long.byte 0x00 8.--14. 1. "CECO,Other Error Count" bitfld.long 0x00 7. "OFR,Repeat Error Count Overflow" "No overflow,Overflow" newline hexmask.long.byte 0x00 0.--6. 1. "CECR,Repeat Error Count" rgroup.long c15:0x0455++0x00 line.long 0x00 "ERXMISC2,Selected Error Miscellaneous Register 2" rgroup.long c15:0x0555++0x00 line.long 0x00 "ERXMISC3,Selected Error Miscellaneous Register 3" group.long c15:0x0245++0x00 line.long 0x00 "ERXSTATUS,Selected Error Record Primary Status Register" bitfld.long 0x00 31. "AV,Address Valid" "Not valid,?..." bitfld.long 0x00 30. "V,Status Register valid" "Not valid,Valid" bitfld.long 0x00 29. "UE,Uncorrected Error" "No error,>=1 error" newline bitfld.long 0x00 28. "ER,Error Reported" "No error,Error" bitfld.long 0x00 27. "OF,Error overflow" "No error,>1 error" bitfld.long 0x00 26. "MV,Miscellaneous Registers Valid" "Not valid,Valid" newline bitfld.long 0x00 24.--25. "CE,Corrected Errors" "No error,Reserved,>=1 error,?..." bitfld.long 0x00 23. "DE,Deferred Errors" "No error,>=1 error" bitfld.long 0x00 22. "PN,Poison" "No distinction,?..." newline bitfld.long 0x00 20.--21. "UET,Uncorrected Error Type" "Uncontainable,?..." abitfld.long 0x00 8.--15. "IERR,Implementation defined error code" "0x00=No error/Error not on dirty RAM,0x01=Error on L1 dirty RAM" abitfld.long 0x00 0.--7. "SERR,Primary error code" "0x00=No error,0x02=ECC/Internal data buffer,0x06=ECC/Cache data RAM,0x07=ECC/Cache tag/Dirty RAM,0x08=Parity error/TLB data RAM,0x09=Parity error/TLB tag RAM,0x15=Deferred error from slave,?..." group.long c15:0x022F++0x00 line.long 0x00 "ERXPFGCDN,Selected Error Pseudo Fault Generation Count Down Register" group.long c15:0x012F++0x00 line.long 0x00 "ERXPFGCTL,Selected Error Pseudo Fault Generation Control Register" bitfld.long 0x00 31. "CDNEN,Count down enable" "Disabled,Enabled" bitfld.long 0x00 30. "R,Restartable bit. Controls whether Error Generation Counter restarts from the ERR0PFGCDNR value or stops after reaching 0" "Counter stops,Counter restarts" bitfld.long 0x00 6. "CE,Corrected Error generation enable" "Disabled,Enabled" newline bitfld.long 0x00 5. "DE,Deferred Error generation enable" "Disabled,Enabled" bitfld.long 0x00 3. "UER,Signaled or Recoverable Error generation enable" "Disabled,Enabled" newline bitfld.long 0x00 1. "UC,Uncontainable error generation enable" "Disabled,Enabled" rgroup.long c15:0x002F++0x00 line.long 0x00 "ERXPFGF,Selected Pseudo Fault Generation Feature Register" bitfld.long 0x00 31. "PFG,Pseudo Fault Generation" "Not supported,Supported" bitfld.long 0x00 30. "R,Restartable bit" "Not supported,Controllable" bitfld.long 0x00 6. "CE,Corrected Error generation" "Not supported,Controllable" newline bitfld.long 0x00 5. "DE,Deferred Error generation" "Not supported,Controllable" bitfld.long 0x00 4. "UEO,Latent or Restartable Error generation" "Not supported,?..." bitfld.long 0x00 3. "UER,Signaled or Recoverable Error generation" "Not supported,Controllable" newline bitfld.long 0x00 2. "UEU,Unrecoverable Error generation" "Not supported,?..." bitfld.long 0x00 1. "UC,Uncontainable Error generation" "Not supported,Controllable" elif CORENAME()=="CORTEXA75" group.long c15:0x0345++0x00 line.long 0x00 "ERXADDR,Selected Error Record Address Register" bitfld.long 0x00 31. "NS,Non-secure attribute" "Secure,Non-secure" bitfld.long 0x00 30. "SI,Secure incorrect" "Correct,Incorrect" bitfld.long 0x00 29. "AI,Address incomplete or incorrect" "Correct,Not correct" newline hexmask.long.word 0x00 0.--31. 0x01 "PADDR[43:32],Physical address bits [43:32]" group.long c15:0x0745++0x00 line.long 0x00 "ERXADDR2,Selected Error Record Address Register 2" hexmask.long 0x00 0.--31. 0x01 "PADDR[31:0],Physical address" group.long c15:0x0145++0x00 line.long 0x00 "ERXCTLR,Selected Error Record Control Register" bitfld.long 0x00 8. "CFI,Fault handling interrupt for corrected errors enable" "Disabled,Enabled" bitfld.long 0x00 3. "FI,Fault handling interrupt enable" "Disabled,Enabled" bitfld.long 0x00 2. "UI,Uncorrected error recovery interrupt enable" "Disabled,Enabled" newline bitfld.long 0x00 0. "ED,Enable error detection" "Disabled,Enabled" rgroup.long c15:0x0545++0x00 line.long 0x00 "ERXCTLR2,Selected Error Record Control Register 2" rgroup.long c15:0x0045++0x00 line.long 0x00 "ERXFR,Selected Error Record Feature Register" bitfld.long 0x00 18.--19. "CEO,Previous error syndrome is kept on a second corrected error" "Yes,?..." bitfld.long 0x00 16.--17. "DUI,Error recovery interrupt for deferred errors" "Not supported,?..." bitfld.long 0x00 15. "RP,Indicates whether a repeat counter is implemented" "Reserved,1st and 2nd counter implemented" newline bitfld.long 0x00 12.--14. "CEC,Defines whether the node implements a standard CE counter mechanism in ERRMISC0" "Reserved,Reserved,8bit error counter,?..." bitfld.long 0x00 10.--11. "CFI,Fault handling interrupt for corrected errors" "Reserved,Reserved,Controllable,?..." bitfld.long 0x00 8.--9. "UE,Uncorrected error reporting" "Reserved,Supported,?..." newline bitfld.long 0x00 6.--7. "FI,Fault handling interrupt" "Reserved,Reserved,Controllable,?..." bitfld.long 0x00 4.--5. "UI,Uncorrected error recovery interrupt" "Reserved,Reserved,Controllable,?..." newline bitfld.long 0x00 0.--1. "ED,Error detection and correction" "Reserved,Reserved,Controllable,?..." rgroup.long c15:0x0445++0x00 line.long 0x00 "ERXFR2,Selected Error Record Feature Register 2" group.long c15:0x0055++0x00 line.long 0x00 "ERXMISC0,Selected Error Miscellaneous Register 0" bitfld.long 0x00 28.--31. "WAY,Indicates the way that contained the error" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.word 0x00 6.--18. 1. "INDX,Indicates the index that contained the error" bitfld.long 0x00 5. "TLBRAM,Indicates in which TLB RAM block the error occurs" "RAM0,RAM1" newline bitfld.long 0x00 1.--3. "L,Indicates the level that contained the error" "Level 1,Level 2,?..." bitfld.long 0x00 0. "IND,Indicates the type of cache that contained the error" "Data cache(L1)/Unified cache(L2)/TLB,Instruction cache(L1)" group.long c15:0x0155++0x00 line.long 0x00 "ERXMISC1,Selected Error Miscellaneous Register 1" hexmask.long.word 0x00 0.--15. 1. "CEC,Corrected Error Count" rgroup.long c15:0x0455++0x00 line.long 0x00 "ERXMISC2,Selected Error Miscellaneous Register 2" rgroup.long c15:0x0555++0x00 line.long 0x00 "ERXMISC3,Selected Error Miscellaneous Register 3" group.long c15:0x0245++0x00 line.long 0x00 "ERXSTATUS,Selected Error Record Primary Status Register" bitfld.long 0x00 31. "AV,Address Valid" "Not valid,Valid" bitfld.long 0x00 30. "V,Status Register valid" "Not valid,Valid" bitfld.long 0x00 29. "UE,Uncorrected Error" "No error,>=1 error" newline bitfld.long 0x00 28. "ER,Error Reported" "No error,Error" bitfld.long 0x00 27. "OF,Error overflow" "No error,>1 error" bitfld.long 0x00 26. "MV,Miscellaneous Registers Valid" "Not valid,Valid" newline bitfld.long 0x00 24.--25. "CE,Corrected Errors" "No error,Reserved,>=1 error,?..." bitfld.long 0x00 23. "DE,Deferred Errors" "No error,>=1 error" bitfld.long 0x00 22. "PN,Poison" "No distinction,?..." newline bitfld.long 0x00 20.--21. "UET,Uncorrected Error Type" "Uncontainable,?..." abitfld.long 0x00 0.--7. "SERR,Primary error code" "0x00=No error,0x02=ECC/Internal data buffer,0x06=ECC/Cache data RAM,0x07=ECC/Cache tag/Dirty RAM,0x08=Parity error/TLB data RAM,0x09=Parity error/TLB tag RAM,0x15=Deferred error from slave,?..." group.long c15:0x022F++0x00 line.long 0x00 "ERXPFGCDN,Selected Error Pseudo Fault Generation Count Down Register" group.long c15:0x012F++0x00 line.long 0x00 "ERXPFGCTL,Selected Error Pseudo Fault Generation Control Register" bitfld.long 0x00 31. "CDNEN,Count down enable" "Disabled,Enabled" bitfld.long 0x00 30. "R,Restartable bit. Controls whether Error Generation Counter restarts from the ERR0PFGCDNR value or stops after reaching 0" "Counter stops,Counter restarts" bitfld.long 0x00 6. "CE,Corrected Error generation enable" "Disabled,Enabled" newline bitfld.long 0x00 5. "DE,Deferred Error generation enable" "Disabled,Enabled" bitfld.long 0x00 3. "UER,Signaled or Recoverable Error generation enable" "Disabled,Enabled" newline bitfld.long 0x00 1. "UC,Uncontainable error generation enable" "Disabled,Enabled" rgroup.long c15:0x002F++0x00 line.long 0x00 "ERXPFGF,Selected Pseudo Fault Generation Feature Register" bitfld.long 0x00 31. "PFG,Pseudo Fault Generation" "Reserved,Supported" bitfld.long 0x00 30. "R,Restartable bit" "Reserved,Controllable" bitfld.long 0x00 6. "CE,Corrected Error generation" "Reserved,Controllable" newline bitfld.long 0x00 5. "DE,Deferred Error generation" "Reserved,Controllable" bitfld.long 0x00 4. "UEO,Latent or Restartable Error generation" "Not supported,?..." bitfld.long 0x00 3. "UER,Signaled or Recoverable Error generation" "Not supported,?..." newline bitfld.long 0x00 2. "UEU,Unrecoverable Error generation" "Not supported,?..." bitfld.long 0x00 1. "UC,Uncontainable Error generation" "Reserved,Controllable" endif else rgroup.long c15:0x0345++0x00 line.long 0x00 "ERXADDR,Selected Error Record Address Register" rgroup.long c15:0x0745++0x00 line.long 0x00 "ERXADDR2,Selected Error Record Address Register 2" group.long c15:0x0145++0x00 line.long 0x00 "ERXCTLR,Selected Error Record Control Register" bitfld.long 0x00 8. "CFI,Fault handling interrupt for corrected errors enable" "Disabled,Enabled" bitfld.long 0x00 3. "FI,Fault handling interrupt enable" "Disabled,Enabled" bitfld.long 0x00 2. "UI,Uncorrected error recovery interrupt enable" "Disabled,Enabled" newline bitfld.long 0x00 0. "ED,Error reporting and logging enable" "Disabled,Enabled" rgroup.long c15:0x0545++0x00 line.long 0x00 "ERXCTLR2,Selected Error Record Control Register 2" rgroup.long c15:0x0045++0x00 line.long 0x00 "ERXFR,Selected Error Record Feature Register" bitfld.long 0x00 18.--19. "CEO,Previous error syndrome is kept on a second corrected error" "Yes,?..." bitfld.long 0x00 16.--17. "DUI,Error recovery interrupt for deferred errors" "Not supported,?..." bitfld.long 0x00 15. "RP,Indicates whether a repeat counter is implemented" "Reserved,1st and 2nd counter implemented" newline bitfld.long 0x00 12.--14. "CEC,Defines whether the node implements a standard CE counter mechanism in ERRMISC0" "Reserved,Reserved,8bit error counter,?..." bitfld.long 0x00 10.--11. "CFI,Fault handling interrupt for corrected errors" "Reserved,Reserved,Controllable,?..." bitfld.long 0x00 8.--9. "UE,Uncorrected error reporting" "Reserved,Supported,?..." newline bitfld.long 0x00 6.--7. "FI,Fault handling interrupt" "Reserved,Reserved,Controllable,?..." bitfld.long 0x00 4.--5. "UI,Uncorrected error recovery interrupt" ",Reserved,Controllable,?..." bitfld.long 0x00 2.--3. "DE,Deferred errors" "Reserved,Always enabled,?..." newline bitfld.long 0x00 0.--1. "ED,Error detection and correction" "Reserved,Reserved,Controllable,?..." rgroup.long c15:0x0445++0x00 line.long 0x00 "ERXFR2,Selected Error Record Feature Register 2" group.long c15:0x0055++0x00 line.long 0x00 "ERXMISC0,Selected Error Miscellaneous Register 0" bitfld.long 0x00 28.--31. "WAY,Indicates the way that contained the error" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.word 0x00 6.--18. 1. "INDX,Indicates the index that contained the error" newline bitfld.long 0x00 1.--3. "L,Indicates the level that contained the error" "Reserved,Reserved,Level 3,?..." bitfld.long 0x00 0. "IND,Indicates the type of cache that contained the error" "L3 cache," group.long c15:0x0155++0x00 line.long 0x00 "ERXMISC1,Selected Error Miscellaneous Register 1" bitfld.long 0x00 15. "OFO,Other Error Count Overflow" "No overflow,Overflow" hexmask.long.byte 0x00 8.--14. 1. "CECO,Other Error Count" bitfld.long 0x00 7. "OFR,Repeat Error Count Overflow" "No overflow,Overflow" newline hexmask.long.byte 0x00 0.--6. 1. "CECR,Repeat Error Count" rgroup.long c15:0x0455++0x00 line.long 0x00 "ERXMISC2,Selected Error Miscellaneous Register 2" rgroup.long c15:0x0555++0x00 line.long 0x00 "ERXMISC3,Selected Error Miscellaneous Register 3" group.long c15:0x0245++0x00 line.long 0x00 "ERXSTATUS,Selected Error Record Primary Status Register" bitfld.long 0x00 31. "AV,Address Valid" "Not valid,?..." bitfld.long 0x00 30. "V,Status Register valid" "Not valid,Valid" bitfld.long 0x00 29. "UE,Uncorrected Error" "No error,>=1 error" newline bitfld.long 0x00 28. "ER,Error Reported" "No error,?..." bitfld.long 0x00 27. "OF,Error overflow" "No error,>1 error" bitfld.long 0x00 26. "MV,Miscellaneous Registers Valid" "Not valid,Valid" newline bitfld.long 0x00 24.--25. "CE,Corrected Errors" "No error,Reserved,>=1 error,?..." bitfld.long 0x00 23. "DE,Deferred Errors" "No error,>=1 error" bitfld.long 0x00 22. "PN,Poison" "No distinction,Uncorrected error" newline bitfld.long 0x00 20.--21. "UET,Uncorrected Error Type" "Uncontainable,?..." abitfld.long 0x00 8.--15. "IERR,Implementation defined error code" "0x00=No error/Error on other RAMs,0x02=Error on a L3 snoop filter RAM" abitfld.long 0x00 0.--7. "SERR,Primary error code" "0x00=No error,0x02=ECC/Internal data buffer,0x06=ECC/Cache data RAM,0x07=ECC/Cache tag/Dirty RAM,0x12=Bus error" group.long c15:0x022F++0x00 line.long 0x00 "ERXPFGCDN,Selected Error Pseudo Fault Generation Count Down Register" group.long c15:0x012F++0x00 line.long 0x00 "ERXPFGCTL,Selected Error Pseudo Fault Generation Control Register" bitfld.long 0x00 31. "CDNEN,Count down enable" "Disabled,Enabled" bitfld.long 0x00 30. "R,Restartable bit. Controls whether Error Generation Counter restarts from the ERR0PFGCDNR value or stops after reaching 0" "Counter stops,Counter restarts" bitfld.long 0x00 6. "CE,Corrected Error generation enable" "Disabled,Enabled" newline bitfld.long 0x00 5. "DE,Deferred Error generation enable" "Disabled,Enabled" bitfld.long 0x00 1. "UC,Uncontainable error generation enable" "Disabled,Enabled" rgroup.long c15:0x002F++0x00 line.long 0x00 "ERXPFGF,Selected Pseudo Fault Generation Feature Register" bitfld.long 0x00 31. "PFG,Pseudo Fault Generation" "Not supported,Supported" bitfld.long 0x00 30. "R,Restartable bit" "Not supported,Controllable" bitfld.long 0x00 6. "CE,Corrected Error generation" "Not supported,Controllable" newline bitfld.long 0x00 5. "DE,Deferred Error generation" "Not supported,Controllable" bitfld.long 0x00 4. "UEO,Latent or Restartable Error generation" "Not supported,Controllable" bitfld.long 0x00 3. "UER,Signaled or Recoverable Error generation" "Not supported,Controllable" newline bitfld.long 0x00 2. "UEU,Unrecoverable Error generation" "Not supported,Controllable" bitfld.long 0x00 1. "UC,Uncontainable Error generation" "Not supported,Controllable" endif tree.end tree "Cluster PMU Registers" group.long c15:0x005F++0x00 line.long 0x00 "CLUSTERPMCR,Cluster Performance Monitors Control Register" hexmask.long.byte 0x00 24.--31. 1. "IMP,Implementer code" hexmask.long.byte 0x00 16.--23. 1. "IDCODE,Identification code" bitfld.long 0x00 11.--15. "N,Number of counters implemented" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" newline rbitfld.long 0x00 4. "X,Export of events Enable" "Disabled," bitfld.long 0x00 2. "C,Clock Counter Reset" "No reset,Reset" bitfld.long 0x00 1. "P,Event Counter Reset" "No reset,Reset" newline bitfld.long 0x00 0. "E,All Counters Enable" "Disabled,Enabled" newline group.long c15:0x015F++0x00 line.long 0x00 "CLUSTERPMCNTENSET,Cluster Count Enable Set Register" bitfld.long 0x00 31. "C,Enables the cycle counter Register [Read/Write]" "Disabled/No effect,Enabled/Enable" newline bitfld.long 0x00 5. "P5,Event counter PMN 5 enable bit [Read/Write]" "Disabled/No effect,Enabled/Enable" bitfld.long 0x00 4. "P4,Event counter PMN 4 enable bit [Read/Write]" "Disabled/No effect,Enabled/Enable" bitfld.long 0x00 3. "P3,Event counter PMN 3 enable bit [Read/Write]" "Disabled/No effect,Enabled/Enable" newline bitfld.long 0x00 2. "P2,Event counter PMN 2 enable bit [Read/Write]" "Disabled/No effect,Enabled/Enable" bitfld.long 0x00 1. "P1,Event counter PMN 1 enable bit [Read/Write]" "Disabled/No effect,Enabled/Enable" bitfld.long 0x00 0. "P0,Event counter PMN 0 enable bit [Read/Write]" "Disabled/No effect,Enabled/Enable" group.long c15:0x025F++0x00 line.long 0x00 "CLUSTERPMCNTENCLR,Cluster Count Enable Clear Register" bitfld.long 0x00 31. "C,Disables the cycle counter Register [Read/Write]" "Disabled/No effect,Enabled/Disable" newline bitfld.long 0x00 5. "P5,Event counter PMN 5 disable bit [Read/Write]" "Disabled/No effect,Enabled/Disable" bitfld.long 0x00 4. "P4,Event counter PMN 4 disable bit [Read/Write]" "Disabled/No effect,Enabled/Disable" bitfld.long 0x00 3. "P3,Event counter PMN 3 disable bit [Read/Write]" "Disabled/No effect,Enabled/Disable" newline bitfld.long 0x00 2. "P2,Event counter PMN 2 disable bit [Read/Write]" "Disabled/No effect,Enabled/Disable" bitfld.long 0x00 1. "P1,Event counter PMN 1 disable bit [Read/Write]" "Disabled/No effect,Enabled/Disable" bitfld.long 0x00 0. "P0,Event counter PMN 0 disable bit [Read/Write]" "Disabled/No effect,Enabled/Disable" group.long c15:0x035F++0x00 line.long 0x00 "CLUSTERPMOVSSET,Cluster Overflow Flag Status Set" bitfld.long 0x00 31. "C,PMCCNTR overflow bit [Read/Write]" "No overflow/No effect,Overflow/Set" newline bitfld.long 0x00 5. "P5,PMN5 Overflow set bit [Read/Write]" "No overflow/No effect,Overflow/Set" bitfld.long 0x00 4. "P4,PMN4 Overflow set bit [Read/Write]" "No overflow/No effect,Overflow/Set" bitfld.long 0x00 3. "P3,PMN3 Overflow set bit [Read/Write]" "No overflow/No effect,Overflow/Set" newline bitfld.long 0x00 2. "P2,PMN2 Overflow set bit [Read/Write]" "No overflow/No effect,Overflow/Set" bitfld.long 0x00 1. "P1,PMN1 Overflow set bit [Read/Write]" "No overflow/No effect,Overflow/Set" bitfld.long 0x00 0. "P0,PMN0 Overflow set bit [Read/Write]" "No overflow/No effect,Overflow/Set" group.long c15:0x045F++0x00 line.long 0x00 "CLUSTERPMOVSCLR,Cluster Overflow Flag Status Clear" eventfld.long 0x00 31. "C,PMCCNTR overflow bit [Read/Write]" "No overflow/No effect,Overflow/Clear" newline eventfld.long 0x00 5. "P5,PMN5 overflow clear bit [Read/Write]" "No overflow/No effect,Overflow/Clear" eventfld.long 0x00 4. "P4,PMN4 Overflow clear bit [Read/Write]" "No overflow/No effect,Overflow/Clear" eventfld.long 0x00 3. "P3,PMN3 Overflow clear bit [Read/Write]" "No overflow/No effect,Overflow/Clear" newline eventfld.long 0x00 2. "P2,PMN2 Overflow clear bit [Read/Write]" "No overflow/No effect,Overflow/Clear" eventfld.long 0x00 1. "P1,PMN1 Overflow clear bit [Read/Write]" "No overflow/No effect,Overflow/Clear" eventfld.long 0x00 0. "P0,PMN0 Overflow clear bit [Read/Write]" "No overflow/No effect,Overflow/Clear" group.long c15:0x055F++0x00 line.long 0x00 "CLUSTERPMSELR,Cluster Event Counter Selection Register" bitfld.long 0x00 0.--4. "SEL,Current event counter select" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" group.long c15:0x065F++0x00 line.long 0x00 "CLUSTERPMINTENSET,Cluster Interrupt Enable Set Register" bitfld.long 0x00 31. "C,PMCCNTR Overflow Interrupt Request Enable [Read/Write]" "Disabled/No effect,Enabled/Enable" newline bitfld.long 0x00 5. "P5,PMCNT5 Overflow Interrupt Request Enable [Read/Write]" "Disabled/No effect,Enabled/Enable" bitfld.long 0x00 4. "P4,PMCNT4 Overflow Interrupt Request Enable [Read/Write]" "Disabled/No effect,Enabled/Enable" bitfld.long 0x00 3. "P3,PMCNT3 Overflow Interrupt Request Enable [Read/Write]" "Disabled/No effect,Enabled/Enable" newline bitfld.long 0x00 2. "P2,PMCNT2 Overflow Interrupt Request Enable [Read/Write]" "Disabled/No effect,Enabled/Enable" bitfld.long 0x00 1. "P1,PMCNT1 Overflow Interrupt Request Enable [Read/Write]" "Disabled/No effect,Enabled/Enable" bitfld.long 0x00 0. "P0,PMCNT0 Overflow Interrupt Request Enable [Read/Write]" "Disabled/No effect,Enabled/Enable" group.long c15:0x075F++0x00 line.long 0x00 "CLUSTERPMINTENCLR,Cluster Interrupt Enable Clear Register" eventfld.long 0x00 31. "C,PMCCNTR Overflow Interrupt Request Disable [Read/Write]" "Disabled/No effect,Enabled/Disable" newline eventfld.long 0x00 5. "P5,PMCNT5 Overflow Interrupt Disable [Read/Write]" "Disabled/No effect,Enabled/Disable" eventfld.long 0x00 4. "P4,PMCNT4 Overflow Interrupt Disable [Read/Write]" "Disabled/No effect,Enabled/Disable" eventfld.long 0x00 3. "P3,PMCNT3 Overflow Interrupt Disable [Read/Write]" "Disabled/No effect,Enabled/Disable" newline eventfld.long 0x00 2. "P2,PMCNT2 Overflow Interrupt Disable [Read/Write]" "Disabled/No effect,Enabled/Disable" eventfld.long 0x00 1. "P1,PMCNT1 Overflow Interrupt Disable [Read/Write]" "Disabled/No effect,Enabled/Disable" eventfld.long 0x00 0. "P0,PMCNT0 Overflow Interrupt Disable [Read/Write]" "Disabled/No effect,Enabled/Disable" group.quad c15:0x006F++0x01 line.quad 0x00 "CLUSTERPMCCNTR,Cluster Performance Monitors Cycle Counter" if (((per.l(c15:0x016F))&0x80000000)==0x80000000) group.long c15:0x016F++0x00 line.long 0x00 "CLUSTERPMXEVTYPER,Cluster Selected Event Type and Filter Register" bitfld.long 0x00 31. "S,Secure events filtering bit. Controls counting of events that are generated by Secure transactions" "Count Secure events,Not count Secure events" bitfld.long 0x00 29. "NS,Non-secure events filtering bit. Controls counting of events that are generated by Non-secure transactions" "Not count Non-secure events,Count Non-secure events" hexmask.long.word 0x00 0.--15. 1. "EVTCOUNT,Event number" else group.long c15:0x016F++0x00 line.long 0x00 "CLUSTERPMXEVTYPER,Cluster Selected Event Type and Filter Register" bitfld.long 0x00 31. "S,Secure events filtering bit. Controls counting of events that are generated by Secure transactions" "Count Secure events,Not count Secure events" bitfld.long 0x00 29. "NS,Non-secure events filtering bit. Controls counting of events that are generated by Non-secure transactions" "Count Non-secure events,Not count Non-secure events" hexmask.long.word 0x00 0.--15. 1. "EVTCOUNT,Event number" endif group.long c15:0x026F++0x00 line.long 0x00 "CLUSTERPMXEVCNTR,Cluster Selected Event Counter Register" group.long c15:0x036F++0x00 line.long 0x00 "CLUSTERPMMDCR,Cluster Monitor Debug Configuration Register" bitfld.long 0x00 0. "SPME,Secure Performance Monitors Enable" "Disabled,Enabled" tree.open "Common Event Identification Registers" rgroup.long c15:0x046F++0x00 line.long 0x00 "CLUSTERPMCEID0,Cluster Common Event Identification ID0 Register" bitfld.long 0x00 30. "CHAIN,Chain" "Reserved,Implemented" bitfld.long 0x00 29. "BUS_CYCLES,Bus cycle" "Reserved,Implemented" bitfld.long 0x00 26. "MEMORY_ERROR,Local memory error" "Reserved,Implemented" newline bitfld.long 0x00 25. "BUS_ACCESS,Bus access" "Reserved,Implemented" bitfld.long 0x00 17. "CPU_CYCLES,CPU Cycle" "Reserved,Implemented" rgroup.long c15:0x056F++0x00 line.long 0x00 "CLUSTERPMCEID1,Cluster Common Event Identification ID1 Register" bitfld.long 0x00 12. "L3D_CACHE_WB,Attributable Level 3 data or unified cache write-back" "Reserved,Implemented" bitfld.long 0x00 11. "L3D_CACHE,Attributable Level 3 data or unified cache access" "Reserved,Implemented" bitfld.long 0x00 10. "L3D_CACHE_REFILL,Attributable Level 3 data or unified cache refill" "Reserved,Implemented" newline bitfld.long 0x00 9. "L3D_CACHE_ALLOCATE,Attributable Level 3 data or unified cache allocation without refill" "Reserved,Implemented" tree.end newline group.long c15:0x066F++0x00 line.long 0x00 "CLUSTERPMCLAIMSET,Cluster Performance Monitor Claim Tag Set Register" bitfld.long 0x00 3. "S[3],Set bit 3" "Low,High" bitfld.long 0x00 2. "S[2],Set bit 2" "Low,High" bitfld.long 0x00 1. "S[1],Set bit 1" "Low,High" newline bitfld.long 0x00 0. "S[0],Set bit 0" "Low,High" group.long c15:0x076F++0x00 line.long 0x00 "CLUSTERPMCLAIMCLR,Cluster Performance Monitor Claim Tag Clear Register" bitfld.long 0x00 3. "C[3],Clear bit 3" "Low,High" bitfld.long 0x00 2. "C[2],Clear bit 2" "Low,High" bitfld.long 0x00 1. "C[1],Clear bit 1" "Low,High" newline bitfld.long 0x00 0. "C[0],Clear bit 0" "Low,High" tree.end tree.end tree.end AUTOINDENT.OFF AUTOINDENT.POP tree "Interrupt Controller" width 17. base ad:(per.long(spr:0x31F30)&0xFFFC0000) tree "Distributor Interface" if (((per.l(ad:(per.long(spr:0x31F30)&0xFFFC0000)+0x04))&0x400)==0x400) if PER.ADDRESS.isSECUREEX(ad:(per.long(spr:0x31F30)&0xFFFC0000)) group.long 0x0000++0x03 line.long 0x00 "GICD_CTLR,Distributor Control Register (Secure access)" bitfld.long 0x00 1. " ENABLEGRP1 ,Global Interrupt Enable Group 1" "Disabled,Enabled" bitfld.long 0x00 0. " ENABLEGRP0 ,Global Interrupt Enable Group 1" "Disabled,Enabled" else group.long 0x0000++0x03 line.long 0x00 "GICD_CTLR,Distributor Control Register (Non-secure access)" bitfld.long 0x00 0. " ENABLE ,Global enable for forwarding pending interrupts from the Distributor to the CPU interfaces" "Disabled,Enabled" endif else group.long 0x0000++0x03 line.long 0x00 "GICD_CTLR,Distributor Control Register" bitfld.long 0x00 0. " ENABLE ,Global enable for forwarding pending interrupts from the Distributor to the CPU interfaces" "Disabled,Enabled" endif if (((per.l(ad:(per.long(spr:0x31F30)&0xFFFC0000)+0x04))&0x400)==0x400) rgroup.long 0x0004++0x03 line.long 0x00 "GICD_TYPER,Interrupt Controller Type Register" bitfld.long 0x00 11.--15. " LSPI ,Locable Shared Peripheral Interrupts" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31" bitfld.long 0x00 10. " SECURITYEXTN ,Indicate whether interrupt controller implements the security extensions" "Not implemented,Implemented" textline " " bitfld.long 0x00 5.--7. " CPUNUMBER ,Indicates the number of implemented CPU interfaces" "1,2,3,4,?..." bitfld.long 0x00 0.--4. " ITLN ,Indicates the number of interrupts that the interrupt controller supports" "Up to 32,Up to 64,Up to 96,Up to 128,Up to 160,Up to 192,Up to 224,Up to 256,Up to 288,Up to 320,Up to 352,Up to 384,Up to 416,Up to 448,Up to 480,Up to 512,Up to 544,Up to 576,Up to 608,Up to 640,Up to 672,Up to 704,Up to 736,Up to 768,Up to 800,Up to 832,Up to 864,Up to 896,Up to 928,Up to 960,Up to 992,Up to 1020" else rgroup.long 0x0004++0x03 line.long 0x00 "GICD_TYPER,Interrupt Controller Type Register" bitfld.long 0x00 10. " SECURITYEXTN ,Indicates whether interrupt controller implements the security extensions" "Not implemented,Implemented" textline " " bitfld.long 0x00 5.--7. " CPUNUMBER ,Indicates the number of implemented CPU interfaces" "1,2,3,4,?..." bitfld.long 0x00 0.--4. " ITLN ,Indicates the number of interrupts that the interrupt controller supports" "Up to 32,Up to 64,Up to 96,Up to 128,Up to 160,Up to 192,Up to 224,Up to 256,Up to 288,Up to 320,Up to 352,Up to 384,Up to 416,Up to 448,Up to 480,Up to 512,Up to 544,Up to 576,Up to 608,Up to 640,Up to 672,Up to 704,Up to 736,Up to 768,Up to 800,Up to 832,Up to 864,Up to 896,Up to 928,Up to 960,Up to 992,Up to 1020" endif rgroup.long 0x0008++0x03 line.long 0x00 "GICD_IIDR,Distributor Implementer Identification Register" bitfld.long 0x00 24.--31. " PRODID ,Indicates the product ID" "PL390,PL390,GIC400,GIC400,?..." bitfld.long 0x00 16.--19. " VAR ,Major revison number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" textline " " bitfld.long 0x00 12.--15. " REV ,Minor revision number" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" hexmask.long.word 0x00 0.--11. 1. " IMP ,Implementer" sif CPU.FEATURE(hypervisor)||CPU.FEATURE(secure) width 17. tree "Group/Security Registers" if PER.ADDRESS.isSECUREEX(ad:(per.long(spr:0x31F30)&0xFFFC0000)+0x0080) group.long 0x0080++0x03 line.long 0x0 "GICD_IGROUPR0,Interrupt Group Register 0 (Secure Access)" bitfld.long 0x00 31. " GSB31 ,Group Status Bit 31" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 30. " GSB30 ,Group Status Bit 30" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 29. " GSB29 ,Group Status Bit 29" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 28. " GSB28 ,Group Status Bit 28" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 27. " GSB27 ,Group Status Bit 27" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 26. " GSB26 ,Group Status Bit 26" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 25. " GSB25 ,Group Status Bit 25" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 24. " GSB24 ,Group Status Bit 24" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 23. " GSB23 ,Group Status Bit 23" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 22. " GSB22 ,Group Status Bit 22" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 21. " GSB21 ,Group Status Bit 21" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 20. " GSB20 ,Group Status Bit 20" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 19. " GSB19 ,Group Status Bit 19" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 18. " GSB18 ,Group Status Bit 18" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 17. " GSB17 ,Group Status Bit 17" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 16. " GSB16 ,Group Status Bit 16" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 15. " GSB15 ,Group Status Bit 15" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 14. " GSB14 ,Group Status Bit 14" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 13. " GSB13 ,Group Status Bit 13" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 12. " GSB12 ,Group Status Bit 12" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 11. " GSB11 ,Group Status Bit 11" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 10. " GSB10 ,Group Status Bit 10" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 9. " GSB9 ,Group Status Bit 9" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 8. " GSB8 ,Group Status Bit 8" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 7. " GSB7 ,Group Status Bit 7" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 6. " GSB6 ,Group Status Bit 6" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 5. " GSB5 ,Group Status Bit 5" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 4. " GSB4 ,Group Status Bit 4" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 3. " GSB3 ,Group Status Bit 3" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 2. " GSB2 ,Group Status Bit 2" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 1. " GSB1 ,Group Status Bit 1" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 0. " GSB0 ,Group Status Bit 0" "Group 0 (Secure),Group 1 (Non-secure)" else group.long 0x0080++0x03 line.long 0x0 "GICD_IGROUPR0,Interrupt Group Register 0 (Non-secure access)" bitfld.long 0x00 31. " GSB31 ,Group Status Bit 31" "Group 0,Group 1" bitfld.long 0x00 30. " GSB30 ,Group Status Bit 30" "Group 0,Group 1" bitfld.long 0x00 29. " GSB29 ,Group Status Bit 29" "Group 0,Group 1" textline " " bitfld.long 0x00 28. " GSB28 ,Group Status Bit 28" "Group 0,Group 1" bitfld.long 0x00 27. " GSB27 ,Group Status Bit 27" "Group 0,Group 1" bitfld.long 0x00 26. " GSB26 ,Group Status Bit 26" "Group 0,Group 1" textline " " bitfld.long 0x00 25. " GSB25 ,Group Status Bit 25" "Group 0,Group 1" bitfld.long 0x00 24. " GSB24 ,Group Status Bit 24" "Group 0,Group 1" bitfld.long 0x00 23. " GSB23 ,Group Status Bit 23" "Group 0,Group 1" textline " " bitfld.long 0x00 22. " GSB22 ,Group Status Bit 22" "Group 0,Group 1" bitfld.long 0x00 21. " GSB21 ,Group Status Bit 21" "Group 0,Group 1" bitfld.long 0x00 20. " GSB20 ,Group Status Bit 20" "Group 0,Group 1" textline " " bitfld.long 0x00 19. " GSB19 ,Group Status Bit 19" "Group 0,Group 1" bitfld.long 0x00 18. " GSB18 ,Group Status Bit 18" "Group 0,Group 1" bitfld.long 0x00 17. " GSB17 ,Group Status Bit 17" "Group 0,Group 1" textline " " bitfld.long 0x00 16. " GSB16 ,Group Status Bit 16" "Group 0,Group 1" bitfld.long 0x00 15. " GSB15 ,Group Status Bit 15" "Group 0,Group 1" bitfld.long 0x00 14. " GSB14 ,Group Status Bit 14" "Group 0,Group 1" textline " " bitfld.long 0x00 13. " GSB13 ,Group Status Bit 13" "Group 0,Group 1" bitfld.long 0x00 12. " GSB12 ,Group Status Bit 12" "Group 0,Group 1" bitfld.long 0x00 11. " GSB11 ,Group Status Bit 11" "Group 0,Group 1" textline " " bitfld.long 0x00 10. " GSB10 ,Group Status Bit 10" "Group 0,Group 1" bitfld.long 0x00 9. " GSB9 ,Group Status Bit 9" "Group 0,Group 1" bitfld.long 0x00 8. " GSB8 ,Group Status Bit 8" "Group 0,Group 1" textline " " bitfld.long 0x00 7. " GSB7 ,Group Status Bit 7" "Group 0,Group 1" bitfld.long 0x00 6. " GSB6 ,Group Status Bit 6" "Group 0,Group 1" bitfld.long 0x00 5. " GSB5 ,Group Status Bit 5" "Group 0,Group 1" textline " " bitfld.long 0x00 4. " GSB4 ,Group Status Bit 4" "Group 0,Group 1" bitfld.long 0x00 3. " GSB3 ,Group Status Bit 3" "Group 0,Group 1" bitfld.long 0x00 2. " GSB2 ,Group Status Bit 2" "Group 0,Group 1" textline " " bitfld.long 0x00 1. " GSB1 ,Group Status Bit 1" "Group 0,Group 1" bitfld.long 0x00 0. " GSB0 ,Group Status Bit 0" "Group 0,Group 1" endif if (((per.l(ad:(per.long(spr:0x31F30)&0xFFFC0000)+0x04))&0x0000001F)>=0x01)&&(PER.ADDRESS.isSECUREEX(ad:(per.long(spr:0x31F30)&0xFFFC0000)+0x0084)) group.long 0x0084++0x03 line.long 0x0 "GICD_IGROUPR1,Interrupt Group Register 1 (Secure Access)" bitfld.long 0x00 31. " GSB63 ,Group Status Bit 63" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 30. " GSB62 ,Group Status Bit 62" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 29. " GSB61 ,Group Status Bit 61" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 28. " GSB60 ,Group Status Bit 60" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 27. " GSB59 ,Group Status Bit 59" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 26. " GSB58 ,Group Status Bit 58" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 25. " GSB57 ,Group Status Bit 57" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 24. " GSB56 ,Group Status Bit 56" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 23. " GSB55 ,Group Status Bit 55" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 22. " GSB54 ,Group Status Bit 54" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 21. " GSB53 ,Group Status Bit 53" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 20. " GSB52 ,Group Status Bit 52" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 19. " GSB51 ,Group Status Bit 51" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 18. " GSB50 ,Group Status Bit 50" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 17. " GSB49 ,Group Status Bit 49" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 16. " GSB48 ,Group Status Bit 48" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 15. " GSB47 ,Group Status Bit 47" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 14. " GSB46 ,Group Status Bit 46" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 13. " GSB45 ,Group Status Bit 45" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 12. " GSB44 ,Group Status Bit 44" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 11. " GSB43 ,Group Status Bit 43" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 10. " GSB42 ,Group Status Bit 42" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 9. " GSB41 ,Group Status Bit 41" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 8. " GSB40 ,Group Status Bit 40" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 7. " GSB39 ,Group Status Bit 39" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 6. " GSB38 ,Group Status Bit 38" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 5. " GSB37 ,Group Status Bit 37" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 4. " GSB36 ,Group Status Bit 36" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 3. " GSB35 ,Group Status Bit 35" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 2. " GSB34 ,Group Status Bit 34" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 1. " GSB33 ,Group Status Bit 33" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 0. " GSB32 ,Group Status Bit 32" "Group 0 (Secure),Group 1 (Non-secure)" elif (((per.l(ad:(per.long(spr:0x31F30)&0xFFFC0000)+0x04))&0x0000001F)>=0x01) group.long 0x0084++0x03 line.long 0x0 "GICD_IGROUPR1,Interrupt Group Register 1 (Non-secure access)" bitfld.long 0x00 31. " GSB63 ,Group Status Bit 63" "Group 0,Group 1" bitfld.long 0x00 30. " GSB62 ,Group Status Bit 62" "Group 0,Group 1" bitfld.long 0x00 29. " GSB61 ,Group Status Bit 61" "Group 0,Group 1" textline " " bitfld.long 0x00 28. " GSB60 ,Group Status Bit 60" "Group 0,Group 1" bitfld.long 0x00 27. " GSB59 ,Group Status Bit 59" "Group 0,Group 1" bitfld.long 0x00 26. " GSB58 ,Group Status Bit 58" "Group 0,Group 1" textline " " bitfld.long 0x00 25. " GSB57 ,Group Status Bit 57" "Group 0,Group 1" bitfld.long 0x00 24. " GSB56 ,Group Status Bit 56" "Group 0,Group 1" bitfld.long 0x00 23. " GSB55 ,Group Status Bit 55" "Group 0,Group 1" textline " " bitfld.long 0x00 22. " GSB54 ,Group Status Bit 54" "Group 0,Group 1" bitfld.long 0x00 21. " GSB53 ,Group Status Bit 53" "Group 0,Group 1" bitfld.long 0x00 20. " GSB52 ,Group Status Bit 52" "Group 0,Group 1" textline " " bitfld.long 0x00 19. " GSB51 ,Group Status Bit 51" "Group 0,Group 1" bitfld.long 0x00 18. " GSB50 ,Group Status Bit 50" "Group 0,Group 1" bitfld.long 0x00 17. " GSB49 ,Group Status Bit 49" "Group 0,Group 1" textline " " bitfld.long 0x00 16. " GSB48 ,Group Status Bit 48" "Group 0,Group 1" bitfld.long 0x00 15. " GSB47 ,Group Status Bit 47" "Group 0,Group 1" bitfld.long 0x00 14. " GSB46 ,Group Status Bit 46" "Group 0,Group 1" textline " " bitfld.long 0x00 13. " GSB45 ,Group Status Bit 45" "Group 0,Group 1" bitfld.long 0x00 12. " GSB44 ,Group Status Bit 44" "Group 0,Group 1" bitfld.long 0x00 11. " GSB43 ,Group Status Bit 43" "Group 0,Group 1" textline " " bitfld.long 0x00 10. " GSB42 ,Group Status Bit 42" "Group 0,Group 1" bitfld.long 0x00 9. " GSB41 ,Group Status Bit 41" "Group 0,Group 1" bitfld.long 0x00 8. " GSB40 ,Group Status Bit 40" "Group 0,Group 1" textline " " bitfld.long 0x00 7. " GSB39 ,Group Status Bit 39" "Group 0,Group 1" bitfld.long 0x00 6. " GSB38 ,Group Status Bit 38" "Group 0,Group 1" bitfld.long 0x00 5. " GSB37 ,Group Status Bit 37" "Group 0,Group 1" textline " " bitfld.long 0x00 4. " GSB36 ,Group Status Bit 36" "Group 0,Group 1" bitfld.long 0x00 3. " GSB35 ,Group Status Bit 35" "Group 0,Group 1" bitfld.long 0x00 2. " GSB34 ,Group Status Bit 34" "Group 0,Group 1" textline " " bitfld.long 0x00 1. " GSB33 ,Group Status Bit 33" "Group 0,Group 1" bitfld.long 0x00 0. " GSB32 ,Group Status Bit 32" "Group 0,Group 1" else rgroup.long 0x0084++0x03 line.long 0x0 "GICD_IGROUPR1,Interrupt Group Register 1" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(ad:(per.long(spr:0x31F30)&0xFFFC0000)+0x04))&0x0000001F)>=0x02)&&(PER.ADDRESS.isSECUREEX(ad:(per.long(spr:0x31F30)&0xFFFC0000)+0x0088)) group.long 0x0088++0x03 line.long 0x0 "GICD_IGROUPR2,Interrupt Group Register 2 (Secure access)" bitfld.long 0x00 31. " GSB95 ,Group Status Bit 95" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 30. " GSB94 ,Group Status Bit 94" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 29. " GSB93 ,Group Status Bit 93" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 28. " GSB92 ,Group Status Bit 92" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 27. " GSB91 ,Group Status Bit 91" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 26. " GSB90 ,Group Status Bit 90" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 25. " GSB89 ,Group Status Bit 89" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 24. " GSB88 ,Group Status Bit 88" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 23. " GSB87 ,Group Status Bit 87" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 22. " GSB86 ,Group Status Bit 86" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 21. " GSB85 ,Group Status Bit 85" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 20. " GSB84 ,Group Status Bit 84" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 19. " GSB83 ,Group Status Bit 83" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 18. " GSB82 ,Group Status Bit 82" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 17. " GSB81 ,Group Status Bit 81" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 16. " GSB80 ,Group Status Bit 80" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 15. " GSB79 ,Group Status Bit 79" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 14. " GSB78 ,Group Status Bit 78" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 13. " GSB77 ,Group Status Bit 77" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 12. " GSB76 ,Group Status Bit 76" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 11. " GSB75 ,Group Status Bit 75" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 10. " GSB74 ,Group Status Bit 74" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 9. " GSB73 ,Group Status Bit 73" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 8. " GSB72 ,Group Status Bit 72" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 7. " GSB71 ,Group Status Bit 71" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 6. " GSB70 ,Group Status Bit 70" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 5. " GSB69 ,Group Status Bit 69" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 4. " GSB68 ,Group Status Bit 68" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 3. " GSB67 ,Group Status Bit 67" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 2. " GSB66 ,Group Status Bit 66" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 1. " GSB65 ,Group Status Bit 65" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 0. " GSB64 ,Group Status Bit 64" "Group 0 (Secure),Group 1 (Non-secure)" elif (((per.l(ad:(per.long(spr:0x31F30)&0xFFFC0000)+0x04))&0x0000001F)>=0x02) group.long 0x0088++0x03 line.long 0x0 "GICD_IGROUPR2,Interrupt Group Register 2 (Non-secure access)" bitfld.long 0x00 31. " GSB95 ,Group Status Bit 95" "Group 0,Group 1" bitfld.long 0x00 30. " GSB94 ,Group Status Bit 94" "Group 0,Group 1" bitfld.long 0x00 29. " GSB93 ,Group Status Bit 93" "Group 0,Group 1" textline " " bitfld.long 0x00 28. " GSB92 ,Group Status Bit 92" "Group 0,Group 1" bitfld.long 0x00 27. " GSB91 ,Group Status Bit 91" "Group 0,Group 1" bitfld.long 0x00 26. " GSB90 ,Group Status Bit 90" "Group 0,Group 1" textline " " bitfld.long 0x00 25. " GSB89 ,Group Status Bit 89" "Group 0,Group 1" bitfld.long 0x00 24. " GSB88 ,Group Status Bit 88" "Group 0,Group 1" bitfld.long 0x00 23. " GSB87 ,Group Status Bit 87" "Group 0,Group 1" textline " " bitfld.long 0x00 22. " GSB86 ,Group Status Bit 86" "Group 0,Group 1" bitfld.long 0x00 21. " GSB85 ,Group Status Bit 85" "Group 0,Group 1" bitfld.long 0x00 20. " GSB84 ,Group Status Bit 84" "Group 0,Group 1" textline " " bitfld.long 0x00 19. " GSB83 ,Group Status Bit 83" "Group 0,Group 1" bitfld.long 0x00 18. " GSB82 ,Group Status Bit 82" "Group 0,Group 1" bitfld.long 0x00 17. " GSB81 ,Group Status Bit 81" "Group 0,Group 1" textline " " bitfld.long 0x00 16. " GSB80 ,Group Status Bit 80" "Group 0,Group 1" bitfld.long 0x00 15. " GSB79 ,Group Status Bit 79" "Group 0,Group 1" bitfld.long 0x00 14. " GSB78 ,Group Status Bit 78" "Group 0,Group 1" textline " " bitfld.long 0x00 13. " GSB77 ,Group Status Bit 77" "Group 0,Group 1" bitfld.long 0x00 12. " GSB76 ,Group Status Bit 76" "Group 0,Group 1" bitfld.long 0x00 11. " GSB75 ,Group Status Bit 75" "Group 0,Group 1" textline " " bitfld.long 0x00 10. " GSB74 ,Group Status Bit 74" "Group 0,Group 1" bitfld.long 0x00 9. " GSB73 ,Group Status Bit 73" "Group 0,Group 1" bitfld.long 0x00 8. " GSB72 ,Group Status Bit 72" "Group 0,Group 1" textline " " bitfld.long 0x00 7. " GSB71 ,Group Status Bit 71" "Group 0,Group 1" bitfld.long 0x00 6. " GSB70 ,Group Status Bit 70" "Group 0,Group 1" bitfld.long 0x00 5. " GSB69 ,Group Status Bit 69" "Group 0,Group 1" textline " " bitfld.long 0x00 4. " GSB68 ,Group Status Bit 68" "Group 0,Group 1" bitfld.long 0x00 3. " GSB67 ,Group Status Bit 67" "Group 0,Group 1" bitfld.long 0x00 2. " GSB66 ,Group Status Bit 66" "Group 0,Group 1" textline " " bitfld.long 0x00 1. " GSB65 ,Group Status Bit 65" "Group 0,Group 1" bitfld.long 0x00 0. " GSB64 ,Group Status Bit 64" "Group 0,Group 1" else rgroup.long 0x0088++0x03 line.long 0x0 "GICD_IGROUPR2,Interrupt Group Register 2" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(ad:(per.long(spr:0x31F30)&0xFFFC0000)+0x04))&0x0000001F)>=0x03)&&(PER.ADDRESS.isSECUREEX(ad:(per.long(spr:0x31F30)&0xFFFC0000)+0x008C)) group.long 0x008C++0x03 line.long 0x0 "GICD_IGROUPR3,Interrupt Group Register 3 (Secure access)" bitfld.long 0x00 31. " GSB127 ,Group Status Bit 127" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 30. " GSB126 ,Group Status Bit 126" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 29. " GSB125 ,Group Status Bit 125" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 28. " GSB124 ,Group Status Bit 124" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 27. " GSB123 ,Group Status Bit 123" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 26. " GSB122 ,Group Status Bit 122" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 25. " GSB121 ,Group Status Bit 121" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 24. " GSB120 ,Group Status Bit 120" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 23. " GSB119 ,Group Status Bit 119" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 22. " GSB118 ,Group Status Bit 118" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 21. " GSB117 ,Group Status Bit 117" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 20. " GSB116 ,Group Status Bit 116" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 19. " GSB115 ,Group Status Bit 115" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 18. " GSB114 ,Group Status Bit 114" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 17. " GSB113 ,Group Status Bit 113" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 16. " GSB112 ,Group Status Bit 112" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 15. " GSB111 ,Group Status Bit 111" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 14. " GSB110 ,Group Status Bit 110" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 13. " GSB109 ,Group Status Bit 109" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 12. " GSB108 ,Group Status Bit 108" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 11. " GSB107 ,Group Status Bit 107" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 10. " GSB106 ,Group Status Bit 106" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 9. " GSB105 ,Group Status Bit 105" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 8. " GSB104 ,Group Status Bit 104" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 7. " GSB103 ,Group Status Bit 103" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 6. " GSB102 ,Group Status Bit 102" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 5. " GSB101 ,Group Status Bit 101" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 4. " GSB100 ,Group Status Bit 100" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 3. " GSB99 ,Group Status Bit 99" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 2. " GSB98 ,Group Status Bit 98" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 1. " GSB97 ,Group Status Bit 97" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 0. " GSB96 ,Group Status Bit 96" "Group 0 (Secure),Group 1 (Non-secure)" elif (((per.l(ad:(per.long(spr:0x31F30)&0xFFFC0000)+0x04))&0x0000001F)>=0x03) group.long 0x008C++0x03 line.long 0x0 "GICD_IGROUPR3,Interrupt Group Register 3 (Non-secure access)" bitfld.long 0x00 31. " GSB127 ,Group Status Bit 127" "Group 0,Group 1" bitfld.long 0x00 30. " GSB126 ,Group Status Bit 126" "Group 0,Group 1" bitfld.long 0x00 29. " GSB125 ,Group Status Bit 125" "Group 0,Group 1" textline " " bitfld.long 0x00 28. " GSB124 ,Group Status Bit 124" "Group 0,Group 1" bitfld.long 0x00 27. " GSB123 ,Group Status Bit 123" "Group 0,Group 1" bitfld.long 0x00 26. " GSB122 ,Group Status Bit 122" "Group 0,Group 1" textline " " bitfld.long 0x00 25. " GSB121 ,Group Status Bit 121" "Group 0,Group 1" bitfld.long 0x00 24. " GSB120 ,Group Status Bit 120" "Group 0,Group 1" bitfld.long 0x00 23. " GSB119 ,Group Status Bit 119" "Group 0,Group 1" textline " " bitfld.long 0x00 22. " GSB118 ,Group Status Bit 118" "Group 0,Group 1" bitfld.long 0x00 21. " GSB117 ,Group Status Bit 117" "Group 0,Group 1" bitfld.long 0x00 20. " GSB116 ,Group Status Bit 116" "Group 0,Group 1" textline " " bitfld.long 0x00 19. " GSB115 ,Group Status Bit 115" "Group 0,Group 1" bitfld.long 0x00 18. " GSB114 ,Group Status Bit 114" "Group 0,Group 1" bitfld.long 0x00 17. " GSB113 ,Group Status Bit 113" "Group 0,Group 1" textline " " bitfld.long 0x00 16. " GSB112 ,Group Status Bit 112" "Group 0,Group 1" bitfld.long 0x00 15. " GSB111 ,Group Status Bit 111" "Group 0,Group 1" bitfld.long 0x00 14. " GSB110 ,Group Status Bit 110" "Group 0,Group 1" textline " " bitfld.long 0x00 13. " GSB109 ,Group Status Bit 109" "Group 0,Group 1" bitfld.long 0x00 12. " GSB108 ,Group Status Bit 108" "Group 0,Group 1" bitfld.long 0x00 11. " GSB107 ,Group Status Bit 107" "Group 0,Group 1" textline " " bitfld.long 0x00 10. " GSB106 ,Group Status Bit 106" "Group 0,Group 1" bitfld.long 0x00 9. " GSB105 ,Group Status Bit 105" "Group 0,Group 1" bitfld.long 0x00 8. " GSB104 ,Group Status Bit 104" "Group 0,Group 1" textline " " bitfld.long 0x00 7. " GSB103 ,Group Status Bit 103" "Group 0,Group 1" bitfld.long 0x00 6. " GSB102 ,Group Status Bit 102" "Group 0,Group 1" bitfld.long 0x00 5. " GSB101 ,Group Status Bit 101" "Group 0,Group 1" textline " " bitfld.long 0x00 4. " GSB100 ,Group Status Bit 100" "Group 0,Group 1" bitfld.long 0x00 3. " GSB99 ,Group Status Bit 99" "Group 0,Group 1" bitfld.long 0x00 2. " GSB98 ,Group Status Bit 98" "Group 0,Group 1" textline " " bitfld.long 0x00 1. " GSB97 ,Group Status Bit 97" "Group 0,Group 1" bitfld.long 0x00 0. " GSB96 ,Group Status Bit 96" "Group 0,Group 1" else rgroup.long 0x008C++0x03 line.long 0x0 "GICD_IGROUPR3,Interrupt Group Register 3" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(ad:(per.long(spr:0x31F30)&0xFFFC0000)+0x04))&0x0000001F)>=0x04)&&(PER.ADDRESS.isSECUREEX(ad:(per.long(spr:0x31F30)&0xFFFC0000)+0x0090)) group.long 0x0090++0x03 line.long 0x0 "GICD_IGROUPR4,Interrupt Group Register 4 (Secure access)" bitfld.long 0x00 31. " GSB159 ,Group Status Bit 159" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 30. " GSB158 ,Group Status Bit 158" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 29. " GSB157 ,Group Status Bit 157" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 28. " GSB156 ,Group Status Bit 156" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 27. " GSB155 ,Group Status Bit 155" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 26. " GSB154 ,Group Status Bit 154" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 25. " GSB153 ,Group Status Bit 153" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 24. " GSB152 ,Group Status Bit 152" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 23. " GSB151 ,Group Status Bit 151" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 22. " GSB150 ,Group Status Bit 150" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 21. " GSB149 ,Group Status Bit 149" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 20. " GSB148 ,Group Status Bit 148" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 19. " GSB147 ,Group Status Bit 147" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 18. " GSB146 ,Group Status Bit 146" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 17. " GSB145 ,Group Status Bit 145" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 16. " GSB144 ,Group Status Bit 144" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 15. " GSB143 ,Group Status Bit 143" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 14. " GSB142 ,Group Status Bit 142" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 13. " GSB141 ,Group Status Bit 141" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 12. " GSB140 ,Group Status Bit 140" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 11. " GSB139 ,Group Status Bit 139" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 10. " GSB138 ,Group Status Bit 138" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 9. " GSB137 ,Group Status Bit 137" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 8. " GSB136 ,Group Status Bit 136" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 7. " GSB135 ,Group Status Bit 135" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 6. " GSB134 ,Group Status Bit 134" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 5. " GSB133 ,Group Status Bit 133" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 4. " GSB132 ,Group Status Bit 132" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 3. " GSB131 ,Group Status Bit 131" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 2. " GSB130 ,Group Status Bit 130" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 1. " GSB129 ,Group Status Bit 129" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 0. " GSB128 ,Group Status Bit 128" "Group 0 (Secure),Group 1 (Non-secure)" elif (((per.l(ad:(per.long(spr:0x31F30)&0xFFFC0000)+0x04))&0x0000001F)>=0x04) group.long 0x0090++0x03 line.long 0x0 "GICD_IGROUPR4,Interrupt Group Register 4 (Non-secure access)" bitfld.long 0x00 31. " GSB159 ,Group Status Bit 159" "Group 0,Group 1" bitfld.long 0x00 30. " GSB158 ,Group Status Bit 158" "Group 0,Group 1" bitfld.long 0x00 29. " GSB157 ,Group Status Bit 157" "Group 0,Group 1" textline " " bitfld.long 0x00 28. " GSB156 ,Group Status Bit 156" "Group 0,Group 1" bitfld.long 0x00 27. " GSB155 ,Group Status Bit 155" "Group 0,Group 1" bitfld.long 0x00 26. " GSB154 ,Group Status Bit 154" "Group 0,Group 1" textline " " bitfld.long 0x00 25. " GSB153 ,Group Status Bit 153" "Group 0,Group 1" bitfld.long 0x00 24. " GSB152 ,Group Status Bit 152" "Group 0,Group 1" bitfld.long 0x00 23. " GSB151 ,Group Status Bit 151" "Group 0,Group 1" textline " " bitfld.long 0x00 22. " GSB150 ,Group Status Bit 150" "Group 0,Group 1" bitfld.long 0x00 21. " GSB149 ,Group Status Bit 149" "Group 0,Group 1" bitfld.long 0x00 20. " GSB148 ,Group Status Bit 148" "Group 0,Group 1" textline " " bitfld.long 0x00 19. " GSB147 ,Group Status Bit 147" "Group 0,Group 1" bitfld.long 0x00 18. " GSB146 ,Group Status Bit 146" "Group 0,Group 1" bitfld.long 0x00 17. " GSB145 ,Group Status Bit 145" "Group 0,Group 1" textline " " bitfld.long 0x00 16. " GSB144 ,Group Status Bit 144" "Group 0,Group 1" bitfld.long 0x00 15. " GSB143 ,Group Status Bit 143" "Group 0,Group 1" bitfld.long 0x00 14. " GSB142 ,Group Status Bit 142" "Group 0,Group 1" textline " " bitfld.long 0x00 13. " GSB141 ,Group Status Bit 141" "Group 0,Group 1" bitfld.long 0x00 12. " GSB140 ,Group Status Bit 140" "Group 0,Group 1" bitfld.long 0x00 11. " GSB139 ,Group Status Bit 139" "Group 0,Group 1" textline " " bitfld.long 0x00 10. " GSB138 ,Group Status Bit 138" "Group 0,Group 1" bitfld.long 0x00 9. " GSB137 ,Group Status Bit 137" "Group 0,Group 1" bitfld.long 0x00 8. " GSB136 ,Group Status Bit 136" "Group 0,Group 1" textline " " bitfld.long 0x00 7. " GSB135 ,Group Status Bit 135" "Group 0,Group 1" bitfld.long 0x00 6. " GSB134 ,Group Status Bit 134" "Group 0,Group 1" bitfld.long 0x00 5. " GSB133 ,Group Status Bit 133" "Group 0,Group 1" textline " " bitfld.long 0x00 4. " GSB132 ,Group Status Bit 132" "Group 0,Group 1" bitfld.long 0x00 3. " GSB131 ,Group Status Bit 131" "Group 0,Group 1" bitfld.long 0x00 2. " GSB130 ,Group Status Bit 130" "Group 0,Group 1" textline " " bitfld.long 0x00 1. " GSB129 ,Group Status Bit 129" "Group 0,Group 1" bitfld.long 0x00 0. " GSB128 ,Group Status Bit 128" "Group 0,Group 1" else rgroup.long 0x0090++0x03 line.long 0x0 "GICD_IGROUPR4,Interrupt Group Register 4" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(ad:(per.long(spr:0x31F30)&0xFFFC0000)+0x04))&0x0000001F)>=0x05)&&(PER.ADDRESS.isSECUREEX(ad:(per.long(spr:0x31F30)&0xFFFC0000)+0x0094)) group.long 0x0094++0x03 line.long 0x0 "GICD_IGROUPR5,Interrupt Group Register 5 (Secure access)" bitfld.long 0x00 31. " GSB191 ,Group Status Bit 191" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 30. " GSB190 ,Group Status Bit 190" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 29. " GSB189 ,Group Status Bit 189" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 28. " GSB188 ,Group Status Bit 188" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 27. " GSB187 ,Group Status Bit 187" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 26. " GSB186 ,Group Status Bit 186" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 25. " GSB185 ,Group Status Bit 185" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 24. " GSB184 ,Group Status Bit 184" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 23. " GSB183 ,Group Status Bit 183" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 22. " GSB182 ,Group Status Bit 182" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 21. " GSB181 ,Group Status Bit 181" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 20. " GSB180 ,Group Status Bit 180" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 19. " GSB179 ,Group Status Bit 179" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 18. " GSB178 ,Group Status Bit 178" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 17. " GSB177 ,Group Status Bit 177" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 16. " GSB176 ,Group Status Bit 176" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 15. " GSB175 ,Group Status Bit 175" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 14. " GSB174 ,Group Status Bit 174" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 13. " GSB173 ,Group Status Bit 173" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 12. " GSB172 ,Group Status Bit 172" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 11. " GSB171 ,Group Status Bit 171" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 10. " GSB170 ,Group Status Bit 170" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 9. " GSB169 ,Group Status Bit 169" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 8. " GSB168 ,Group Status Bit 168" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 7. " GSB167 ,Group Status Bit 167" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 6. " GSB166 ,Group Status Bit 166" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 5. " GSB165 ,Group Status Bit 165" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 4. " GSB164 ,Group Status Bit 164" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 3. " GSB163 ,Group Status Bit 163" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 2. " GSB162 ,Group Status Bit 162" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 1. " GSB161 ,Group Status Bit 161" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 0. " GSB160 ,Group Status Bit 160" "Group 0 (Secure),Group 1 (Non-secure)" elif (((per.l(ad:(per.long(spr:0x31F30)&0xFFFC0000)+0x04))&0x0000001F)>=0x05) group.long 0x0094++0x03 line.long 0x0 "GICD_IGROUPR5,Interrupt Group Register 5 (Non-secure access)" bitfld.long 0x00 31. " GSB191 ,Group Status Bit 191" "Group 0,Group 1" bitfld.long 0x00 30. " GSB190 ,Group Status Bit 190" "Group 0,Group 1" bitfld.long 0x00 29. " GSB189 ,Group Status Bit 189" "Group 0,Group 1" textline " " bitfld.long 0x00 28. " GSB188 ,Group Status Bit 188" "Group 0,Group 1" bitfld.long 0x00 27. " GSB187 ,Group Status Bit 187" "Group 0,Group 1" bitfld.long 0x00 26. " GSB186 ,Group Status Bit 186" "Group 0,Group 1" textline " " bitfld.long 0x00 25. " GSB185 ,Group Status Bit 185" "Group 0,Group 1" bitfld.long 0x00 24. " GSB184 ,Group Status Bit 184" "Group 0,Group 1" bitfld.long 0x00 23. " GSB183 ,Group Status Bit 183" "Group 0,Group 1" textline " " bitfld.long 0x00 22. " GSB182 ,Group Status Bit 182" "Group 0,Group 1" bitfld.long 0x00 21. " GSB181 ,Group Status Bit 181" "Group 0,Group 1" bitfld.long 0x00 20. " GSB180 ,Group Status Bit 180" "Group 0,Group 1" textline " " bitfld.long 0x00 19. " GSB179 ,Group Status Bit 179" "Group 0,Group 1" bitfld.long 0x00 18. " GSB178 ,Group Status Bit 178" "Group 0,Group 1" bitfld.long 0x00 17. " GSB177 ,Group Status Bit 177" "Group 0,Group 1" textline " " bitfld.long 0x00 16. " GSB176 ,Group Status Bit 176" "Group 0,Group 1" bitfld.long 0x00 15. " GSB175 ,Group Status Bit 175" "Group 0,Group 1" bitfld.long 0x00 14. " GSB174 ,Group Status Bit 174" "Group 0,Group 1" textline " " bitfld.long 0x00 13. " GSB173 ,Group Status Bit 173" "Group 0,Group 1" bitfld.long 0x00 12. " GSB172 ,Group Status Bit 172" "Group 0,Group 1" bitfld.long 0x00 11. " GSB171 ,Group Status Bit 171" "Group 0,Group 1" textline " " bitfld.long 0x00 10. " GSB170 ,Group Status Bit 170" "Group 0,Group 1" bitfld.long 0x00 9. " GSB169 ,Group Status Bit 169" "Group 0,Group 1" bitfld.long 0x00 8. " GSB168 ,Group Status Bit 168" "Group 0,Group 1" textline " " bitfld.long 0x00 7. " GSB167 ,Group Status Bit 167" "Group 0,Group 1" bitfld.long 0x00 6. " GSB166 ,Group Status Bit 166" "Group 0,Group 1" bitfld.long 0x00 5. " GSB165 ,Group Status Bit 165" "Group 0,Group 1" textline " " bitfld.long 0x00 4. " GSB164 ,Group Status Bit 164" "Group 0,Group 1" bitfld.long 0x00 3. " GSB163 ,Group Status Bit 163" "Group 0,Group 1" bitfld.long 0x00 2. " GSB162 ,Group Status Bit 162" "Group 0,Group 1" textline " " bitfld.long 0x00 1. " GSB161 ,Group Status Bit 161" "Group 0,Group 1" bitfld.long 0x00 0. " GSB160 ,Group Status Bit 160" "Group 0,Group 1" else rgroup.long 0x0094++0x03 line.long 0x0 "GICD_IGROUPR5,Interrupt Group Register 5" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(ad:(per.long(spr:0x31F30)&0xFFFC0000)+0x04))&0x0000001F)>=0x06)&&(PER.ADDRESS.isSECUREEX(ad:(per.long(spr:0x31F30)&0xFFFC0000)+0x0098)) group.long 0x0098++0x03 line.long 0x0 "GICD_IGROUPR6,Interrupt Group Register 6 (Secure access)" bitfld.long 0x00 31. " GSB223 ,Group Status Bit 223" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 30. " GSB222 ,Group Status Bit 222" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 29. " GSB221 ,Group Status Bit 221" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 28. " GSB220 ,Group Status Bit 220" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 27. " GSB219 ,Group Status Bit 219" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 26. " GSB218 ,Group Status Bit 218" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 25. " GSB217 ,Group Status Bit 217" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 24. " GSB216 ,Group Status Bit 216" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 23. " GSB215 ,Group Status Bit 215" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 22. " GSB214 ,Group Status Bit 214" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 21. " GSB213 ,Group Status Bit 213" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 20. " GSB212 ,Group Status Bit 212" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 19. " GSB211 ,Group Status Bit 211" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 18. " GSB210 ,Group Status Bit 210" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 17. " GSB209 ,Group Status Bit 209" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 16. " GSB208 ,Group Status Bit 208" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 15. " GSB207 ,Group Status Bit 207" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 14. " GSB206 ,Group Status Bit 206" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 13. " GSB205 ,Group Status Bit 205" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 12. " GSB204 ,Group Status Bit 204" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 11. " GSB203 ,Group Status Bit 203" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 10. " GSB202 ,Group Status Bit 202" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 9. " GSB201 ,Group Status Bit 201" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 8. " GSB200 ,Group Status Bit 200" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 7. " GSB199 ,Group Status Bit 199" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 6. " GSB198 ,Group Status Bit 198" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 5. " GSB197 ,Group Status Bit 197" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 4. " GSB196 ,Group Status Bit 196" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 3. " GSB195 ,Group Status Bit 195" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 2. " GSB194 ,Group Status Bit 194" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 1. " GSB193 ,Group Status Bit 193" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 0. " GSB192 ,Group Status Bit 192" "Group 0 (Secure),Group 1 (Non-secure)" elif (((per.l(ad:(per.long(spr:0x31F30)&0xFFFC0000)+0x04))&0x0000001F)>=0x06) group.long 0x0098++0x03 line.long 0x0 "GICD_IGROUPR6,Interrupt Group Register 6 (Non-secure access)" bitfld.long 0x00 31. " GSB223 ,Group Status Bit 223" "Group 0,Group 1" bitfld.long 0x00 30. " GSB222 ,Group Status Bit 222" "Group 0,Group 1" bitfld.long 0x00 29. " GSB221 ,Group Status Bit 221" "Group 0,Group 1" textline " " bitfld.long 0x00 28. " GSB220 ,Group Status Bit 220" "Group 0,Group 1" bitfld.long 0x00 27. " GSB219 ,Group Status Bit 219" "Group 0,Group 1" bitfld.long 0x00 26. " GSB218 ,Group Status Bit 218" "Group 0,Group 1" textline " " bitfld.long 0x00 25. " GSB217 ,Group Status Bit 217" "Group 0,Group 1" bitfld.long 0x00 24. " GSB216 ,Group Status Bit 216" "Group 0,Group 1" bitfld.long 0x00 23. " GSB215 ,Group Status Bit 215" "Group 0,Group 1" textline " " bitfld.long 0x00 22. " GSB214 ,Group Status Bit 214" "Group 0,Group 1" bitfld.long 0x00 21. " GSB213 ,Group Status Bit 213" "Group 0,Group 1" bitfld.long 0x00 20. " GSB212 ,Group Status Bit 212" "Group 0,Group 1" textline " " bitfld.long 0x00 19. " GSB211 ,Group Status Bit 211" "Group 0,Group 1" bitfld.long 0x00 18. " GSB210 ,Group Status Bit 210" "Group 0,Group 1" bitfld.long 0x00 17. " GSB209 ,Group Status Bit 209" "Group 0,Group 1" textline " " bitfld.long 0x00 16. " GSB208 ,Group Status Bit 208" "Group 0,Group 1" bitfld.long 0x00 15. " GSB207 ,Group Status Bit 207" "Group 0,Group 1" bitfld.long 0x00 14. " GSB206 ,Group Status Bit 206" "Group 0,Group 1" textline " " bitfld.long 0x00 13. " GSB205 ,Group Status Bit 205" "Group 0,Group 1" bitfld.long 0x00 12. " GSB204 ,Group Status Bit 204" "Group 0,Group 1" bitfld.long 0x00 11. " GSB203 ,Group Status Bit 203" "Group 0,Group 1" textline " " bitfld.long 0x00 10. " GSB202 ,Group Status Bit 202" "Group 0,Group 1" bitfld.long 0x00 9. " GSB201 ,Group Status Bit 201" "Group 0,Group 1" bitfld.long 0x00 8. " GSB200 ,Group Status Bit 200" "Group 0,Group 1" textline " " bitfld.long 0x00 7. " GSB199 ,Group Status Bit 199" "Group 0,Group 1" bitfld.long 0x00 6. " GSB198 ,Group Status Bit 198" "Group 0,Group 1" bitfld.long 0x00 5. " GSB197 ,Group Status Bit 197" "Group 0,Group 1" textline " " bitfld.long 0x00 4. " GSB196 ,Group Status Bit 196" "Group 0,Group 1" bitfld.long 0x00 3. " GSB195 ,Group Status Bit 195" "Group 0,Group 1" bitfld.long 0x00 2. " GSB194 ,Group Status Bit 194" "Group 0,Group 1" textline " " bitfld.long 0x00 1. " GSB193 ,Group Status Bit 193" "Group 0,Group 1" bitfld.long 0x00 0. " GSB192 ,Group Status Bit 192" "Group 0,Group 1" else rgroup.long 0x0098++0x03 line.long 0x0 "GICD_IGROUPR6,Interrupt Group Register 6" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(ad:(per.long(spr:0x31F30)&0xFFFC0000)+0x04))&0x0000001F)>=0x07)&&(PER.ADDRESS.isSECUREEX(ad:(per.long(spr:0x31F30)&0xFFFC0000)+0x009C)) group.long 0x009C++0x03 line.long 0x0 "GICD_IGROUPR7,Interrupt Group Register 7 (Secure access)" bitfld.long 0x00 31. " GSB255 ,Group Status Bit 255" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 30. " GSB254 ,Group Status Bit 254" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 29. " GSB253 ,Group Status Bit 253" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 28. " GSB252 ,Group Status Bit 252" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 27. " GSB251 ,Group Status Bit 251" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 26. " GSB250 ,Group Status Bit 250" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 25. " GSB249 ,Group Status Bit 249" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 24. " GSB248 ,Group Status Bit 248" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 23. " GSB247 ,Group Status Bit 247" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 22. " GSB246 ,Group Status Bit 246" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 21. " GSB245 ,Group Status Bit 245" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 20. " GSB244 ,Group Status Bit 244" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 19. " GSB243 ,Group Status Bit 243" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 18. " GSB242 ,Group Status Bit 242" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 17. " GSB241 ,Group Status Bit 241" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 16. " GSB240 ,Group Status Bit 240" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 15. " GSB239 ,Group Status Bit 239" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 14. " GSB238 ,Group Status Bit 238" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 13. " GSB237 ,Group Status Bit 237" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 12. " GSB236 ,Group Status Bit 236" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 11. " GSB235 ,Group Status Bit 235" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 10. " GSB234 ,Group Status Bit 234" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 9. " GSB233 ,Group Status Bit 233" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 8. " GSB232 ,Group Status Bit 232" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 7. " GSB231 ,Group Status Bit 231" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 6. " GSB230 ,Group Status Bit 230" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 5. " GSB229 ,Group Status Bit 229" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 4. " GSB228 ,Group Status Bit 228" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 3. " GSB227 ,Group Status Bit 227" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 2. " GSB226 ,Group Status Bit 226" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 1. " GSB225 ,Group Status Bit 225" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 0. " GSB224 ,Group Status Bit 224" "Group 0 (Secure),Group 1 (Non-secure)" elif (((per.l(ad:(per.long(spr:0x31F30)&0xFFFC0000)+0x04))&0x0000001F)>=0x07) group.long 0x009C++0x03 line.long 0x0 "GICD_IGROUPR7,Interrupt Group Register 7 (Non-secure access)" bitfld.long 0x00 31. " GSB255 ,Group Status Bit 255" "Group 0,Group 1" bitfld.long 0x00 30. " GSB254 ,Group Status Bit 254" "Group 0,Group 1" bitfld.long 0x00 29. " GSB253 ,Group Status Bit 253" "Group 0,Group 1" textline " " bitfld.long 0x00 28. " GSB252 ,Group Status Bit 252" "Group 0,Group 1" bitfld.long 0x00 27. " GSB251 ,Group Status Bit 251" "Group 0,Group 1" bitfld.long 0x00 26. " GSB250 ,Group Status Bit 250" "Group 0,Group 1" textline " " bitfld.long 0x00 25. " GSB249 ,Group Status Bit 249" "Group 0,Group 1" bitfld.long 0x00 24. " GSB248 ,Group Status Bit 248" "Group 0,Group 1" bitfld.long 0x00 23. " GSB247 ,Group Status Bit 247" "Group 0,Group 1" textline " " bitfld.long 0x00 22. " GSB246 ,Group Status Bit 246" "Group 0,Group 1" bitfld.long 0x00 21. " GSB245 ,Group Status Bit 245" "Group 0,Group 1" bitfld.long 0x00 20. " GSB244 ,Group Status Bit 244" "Group 0,Group 1" textline " " bitfld.long 0x00 19. " GSB243 ,Group Status Bit 243" "Group 0,Group 1" bitfld.long 0x00 18. " GSB242 ,Group Status Bit 242" "Group 0,Group 1" bitfld.long 0x00 17. " GSB241 ,Group Status Bit 241" "Group 0,Group 1" textline " " bitfld.long 0x00 16. " GSB240 ,Group Status Bit 240" "Group 0,Group 1" bitfld.long 0x00 15. " GSB239 ,Group Status Bit 239" "Group 0,Group 1" bitfld.long 0x00 14. " GSB238 ,Group Status Bit 238" "Group 0,Group 1" textline " " bitfld.long 0x00 13. " GSB237 ,Group Status Bit 237" "Group 0,Group 1" bitfld.long 0x00 12. " GSB236 ,Group Status Bit 236" "Group 0,Group 1" bitfld.long 0x00 11. " GSB235 ,Group Status Bit 235" "Group 0,Group 1" textline " " bitfld.long 0x00 10. " GSB234 ,Group Status Bit 234" "Group 0,Group 1" bitfld.long 0x00 9. " GSB233 ,Group Status Bit 233" "Group 0,Group 1" bitfld.long 0x00 8. " GSB232 ,Group Status Bit 232" "Group 0,Group 1" textline " " bitfld.long 0x00 7. " GSB231 ,Group Status Bit 231" "Group 0,Group 1" bitfld.long 0x00 6. " GSB230 ,Group Status Bit 230" "Group 0,Group 1" bitfld.long 0x00 5. " GSB229 ,Group Status Bit 229" "Group 0,Group 1" textline " " bitfld.long 0x00 4. " GSB228 ,Group Status Bit 228" "Group 0,Group 1" bitfld.long 0x00 3. " GSB227 ,Group Status Bit 227" "Group 0,Group 1" bitfld.long 0x00 2. " GSB226 ,Group Status Bit 226" "Group 0,Group 1" textline " " bitfld.long 0x00 1. " GSB225 ,Group Status Bit 225" "Group 0,Group 1" bitfld.long 0x00 0. " GSB224 ,Group Status Bit 224" "Group 0,Group 1" else rgroup.long 0x009C++0x03 line.long 0x0 "GICD_IGROUPR7,Interrupt Group Register 7" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(ad:(per.long(spr:0x31F30)&0xFFFC0000)+0x04))&0x0000001F)>=0x08)&&(PER.ADDRESS.isSECUREEX(ad:(per.long(spr:0x31F30)&0xFFFC0000)+0x00A0)) group.long 0x00A0++0x03 line.long 0x0 "GICD_IGROUPR8,Interrupt Group Register 8 (Secure access)" bitfld.long 0x00 31. " GSB287 ,Group Status Bit 287" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 30. " GSB286 ,Group Status Bit 286" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 29. " GSB285 ,Group Status Bit 285" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 28. " GSB284 ,Group Status Bit 284" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 27. " GSB283 ,Group Status Bit 283" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 26. " GSB282 ,Group Status Bit 282" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 25. " GSB281 ,Group Status Bit 281" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 24. " GSB280 ,Group Status Bit 280" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 23. " GSB279 ,Group Status Bit 279" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 22. " GSB278 ,Group Status Bit 278" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 21. " GSB277 ,Group Status Bit 277" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 20. " GSB276 ,Group Status Bit 276" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 19. " GSB275 ,Group Status Bit 275" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 18. " GSB274 ,Group Status Bit 274" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 17. " GSB273 ,Group Status Bit 273" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 16. " GSB272 ,Group Status Bit 272" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 15. " GSB271 ,Group Status Bit 271" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 14. " GSB270 ,Group Status Bit 270" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 13. " GSB269 ,Group Status Bit 269" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 12. " GSB268 ,Group Status Bit 268" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 11. " GSB267 ,Group Status Bit 267" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 10. " GSB266 ,Group Status Bit 266" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 9. " GSB265 ,Group Status Bit 265" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 8. " GSB264 ,Group Status Bit 264" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 7. " GSB263 ,Group Status Bit 263" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 6. " GSB262 ,Group Status Bit 262" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 5. " GSB261 ,Group Status Bit 261" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 4. " GSB260 ,Group Status Bit 260" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 3. " GSB259 ,Group Status Bit 259" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 2. " GSB258 ,Group Status Bit 258" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 1. " GSB257 ,Group Status Bit 257" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 0. " GSB256 ,Group Status Bit 256" "Group 0 (Secure),Group 1 (Non-secure)" elif (((per.l(ad:(per.long(spr:0x31F30)&0xFFFC0000)+0x04))&0x0000001F)>=0x08) group.long 0x00A0++0x03 line.long 0x0 "GICD_IGROUPR8,Interrupt Group Register 8 (Non-secure access)" bitfld.long 0x00 31. " GSB287 ,Group Status Bit 287" "Group 0,Group 1" bitfld.long 0x00 30. " GSB286 ,Group Status Bit 286" "Group 0,Group 1" bitfld.long 0x00 29. " GSB285 ,Group Status Bit 285" "Group 0,Group 1" textline " " bitfld.long 0x00 28. " GSB284 ,Group Status Bit 284" "Group 0,Group 1" bitfld.long 0x00 27. " GSB283 ,Group Status Bit 283" "Group 0,Group 1" bitfld.long 0x00 26. " GSB282 ,Group Status Bit 282" "Group 0,Group 1" textline " " bitfld.long 0x00 25. " GSB281 ,Group Status Bit 281" "Group 0,Group 1" bitfld.long 0x00 24. " GSB280 ,Group Status Bit 280" "Group 0,Group 1" bitfld.long 0x00 23. " GSB279 ,Group Status Bit 279" "Group 0,Group 1" textline " " bitfld.long 0x00 22. " GSB278 ,Group Status Bit 278" "Group 0,Group 1" bitfld.long 0x00 21. " GSB277 ,Group Status Bit 277" "Group 0,Group 1" bitfld.long 0x00 20. " GSB276 ,Group Status Bit 276" "Group 0,Group 1" textline " " bitfld.long 0x00 19. " GSB275 ,Group Status Bit 275" "Group 0,Group 1" bitfld.long 0x00 18. " GSB274 ,Group Status Bit 274" "Group 0,Group 1" bitfld.long 0x00 17. " GSB273 ,Group Status Bit 273" "Group 0,Group 1" textline " " bitfld.long 0x00 16. " GSB272 ,Group Status Bit 272" "Group 0,Group 1" bitfld.long 0x00 15. " GSB271 ,Group Status Bit 271" "Group 0,Group 1" bitfld.long 0x00 14. " GSB270 ,Group Status Bit 270" "Group 0,Group 1" textline " " bitfld.long 0x00 13. " GSB269 ,Group Status Bit 269" "Group 0,Group 1" bitfld.long 0x00 12. " GSB268 ,Group Status Bit 268" "Group 0,Group 1" bitfld.long 0x00 11. " GSB267 ,Group Status Bit 267" "Group 0,Group 1" textline " " bitfld.long 0x00 10. " GSB266 ,Group Status Bit 266" "Group 0,Group 1" bitfld.long 0x00 9. " GSB265 ,Group Status Bit 265" "Group 0,Group 1" bitfld.long 0x00 8. " GSB264 ,Group Status Bit 264" "Group 0,Group 1" textline " " bitfld.long 0x00 7. " GSB263 ,Group Status Bit 263" "Group 0,Group 1" bitfld.long 0x00 6. " GSB262 ,Group Status Bit 262" "Group 0,Group 1" bitfld.long 0x00 5. " GSB261 ,Group Status Bit 261" "Group 0,Group 1" textline " " bitfld.long 0x00 4. " GSB260 ,Group Status Bit 260" "Group 0,Group 1" bitfld.long 0x00 3. " GSB259 ,Group Status Bit 259" "Group 0,Group 1" bitfld.long 0x00 2. " GSB258 ,Group Status Bit 258" "Group 0,Group 1" textline " " bitfld.long 0x00 1. " GSB257 ,Group Status Bit 257" "Group 0,Group 1" bitfld.long 0x00 0. " GSB256 ,Group Status Bit 256" "Group 0,Group 1" else rgroup.long 0x00A0++0x03 line.long 0x0 "GICD_IGROUPR8,Interrupt Group Register 8" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(ad:(per.long(spr:0x31F30)&0xFFFC0000)+0x04))&0x0000001F)>=0x09)&&(PER.ADDRESS.isSECUREEX(ad:(per.long(spr:0x31F30)&0xFFFC0000)+0x00A4)) group.long 0x00A4++0x03 line.long 0x0 "GICD_IGROUPR9,Interrupt Group Register 9 (Secure access)" bitfld.long 0x00 31. " GSB319 ,Group Status Bit 319" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 30. " GSB318 ,Group Status Bit 318" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 29. " GSB317 ,Group Status Bit 317" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 28. " GSB316 ,Group Status Bit 316" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 27. " GSB315 ,Group Status Bit 315" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 26. " GSB314 ,Group Status Bit 314" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 25. " GSB313 ,Group Status Bit 313" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 24. " GSB312 ,Group Status Bit 312" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 23. " GSB311 ,Group Status Bit 311" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 22. " GSB310 ,Group Status Bit 310" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 21. " GSB309 ,Group Status Bit 309" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 20. " GSB308 ,Group Status Bit 308" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 19. " GSB307 ,Group Status Bit 307" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 18. " GSB306 ,Group Status Bit 306" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 17. " GSB305 ,Group Status Bit 305" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 16. " GSB304 ,Group Status Bit 304" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 15. " GSB303 ,Group Status Bit 303" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 14. " GSB302 ,Group Status Bit 302" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 13. " GSB301 ,Group Status Bit 301" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 12. " GSB300 ,Group Status Bit 300" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 11. " GSB299 ,Group Status Bit 299" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 10. " GSB298 ,Group Status Bit 298" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 9. " GSB297 ,Group Status Bit 297" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 8. " GSB296 ,Group Status Bit 296" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 7. " GSB295 ,Group Status Bit 295" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 6. " GSB294 ,Group Status Bit 294" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 5. " GSB293 ,Group Status Bit 293" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 4. " GSB292 ,Group Status Bit 292" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 3. " GSB291 ,Group Status Bit 291" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 2. " GSB290 ,Group Status Bit 290" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 1. " GSB289 ,Group Status Bit 289" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 0. " GSB288 ,Group Status Bit 288" "Group 0 (Secure),Group 1 (Non-secure)" elif (((per.l(ad:(per.long(spr:0x31F30)&0xFFFC0000)+0x04))&0x0000001F)>=0x09) group.long 0x00A4++0x03 line.long 0x0 "GICD_IGROUPR9,Interrupt Group Register 9 (Non-secure access)" bitfld.long 0x00 31. " GSB319 ,Group Status Bit 319" "Group 0,Group 1" bitfld.long 0x00 30. " GSB318 ,Group Status Bit 318" "Group 0,Group 1" bitfld.long 0x00 29. " GSB317 ,Group Status Bit 317" "Group 0,Group 1" textline " " bitfld.long 0x00 28. " GSB316 ,Group Status Bit 316" "Group 0,Group 1" bitfld.long 0x00 27. " GSB315 ,Group Status Bit 315" "Group 0,Group 1" bitfld.long 0x00 26. " GSB314 ,Group Status Bit 314" "Group 0,Group 1" textline " " bitfld.long 0x00 25. " GSB313 ,Group Status Bit 313" "Group 0,Group 1" bitfld.long 0x00 24. " GSB312 ,Group Status Bit 312" "Group 0,Group 1" bitfld.long 0x00 23. " GSB311 ,Group Status Bit 311" "Group 0,Group 1" textline " " bitfld.long 0x00 22. " GSB310 ,Group Status Bit 310" "Group 0,Group 1" bitfld.long 0x00 21. " GSB309 ,Group Status Bit 309" "Group 0,Group 1" bitfld.long 0x00 20. " GSB308 ,Group Status Bit 308" "Group 0,Group 1" textline " " bitfld.long 0x00 19. " GSB307 ,Group Status Bit 307" "Group 0,Group 1" bitfld.long 0x00 18. " GSB306 ,Group Status Bit 306" "Group 0,Group 1" bitfld.long 0x00 17. " GSB305 ,Group Status Bit 305" "Group 0,Group 1" textline " " bitfld.long 0x00 16. " GSB304 ,Group Status Bit 304" "Group 0,Group 1" bitfld.long 0x00 15. " GSB303 ,Group Status Bit 303" "Group 0,Group 1" bitfld.long 0x00 14. " GSB302 ,Group Status Bit 302" "Group 0,Group 1" textline " " bitfld.long 0x00 13. " GSB301 ,Group Status Bit 301" "Group 0,Group 1" bitfld.long 0x00 12. " GSB300 ,Group Status Bit 300" "Group 0,Group 1" bitfld.long 0x00 11. " GSB299 ,Group Status Bit 299" "Group 0,Group 1" textline " " bitfld.long 0x00 10. " GSB298 ,Group Status Bit 298" "Group 0,Group 1" bitfld.long 0x00 9. " GSB297 ,Group Status Bit 297" "Group 0,Group 1" bitfld.long 0x00 8. " GSB296 ,Group Status Bit 296" "Group 0,Group 1" textline " " bitfld.long 0x00 7. " GSB295 ,Group Status Bit 295" "Group 0,Group 1" bitfld.long 0x00 6. " GSB294 ,Group Status Bit 294" "Group 0,Group 1" bitfld.long 0x00 5. " GSB293 ,Group Status Bit 293" "Group 0,Group 1" textline " " bitfld.long 0x00 4. " GSB292 ,Group Status Bit 292" "Group 0,Group 1" bitfld.long 0x00 3. " GSB291 ,Group Status Bit 291" "Group 0,Group 1" bitfld.long 0x00 2. " GSB290 ,Group Status Bit 290" "Group 0,Group 1" textline " " bitfld.long 0x00 1. " GSB289 ,Group Status Bit 289" "Group 0,Group 1" bitfld.long 0x00 0. " GSB288 ,Group Status Bit 288" "Group 0,Group 1" else rgroup.long 0x00A4++0x03 line.long 0x0 "GICD_IGROUPR9,Interrupt Group Register 9" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(ad:(per.long(spr:0x31F30)&0xFFFC0000)+0x04))&0x0000001F)>=0x0A)&&(PER.ADDRESS.isSECUREEX(ad:(per.long(spr:0x31F30)&0xFFFC0000)+0x00A8)) group.long 0x00A8++0x03 line.long 0x0 "GICD_IGROUPR10,Interrupt Group Register 10 (Secure access)" bitfld.long 0x00 31. " GSB351 ,Group Status Bit 351" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 30. " GSB350 ,Group Status Bit 350" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 29. " GSB349 ,Group Status Bit 349" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 28. " GSB348 ,Group Status Bit 348" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 27. " GSB347 ,Group Status Bit 347" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 26. " GSB346 ,Group Status Bit 346" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 25. " GSB345 ,Group Status Bit 345" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 24. " GSB344 ,Group Status Bit 344" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 23. " GSB343 ,Group Status Bit 343" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 22. " GSB342 ,Group Status Bit 342" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 21. " GSB341 ,Group Status Bit 341" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 20. " GSB340 ,Group Status Bit 340" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 19. " GSB339 ,Group Status Bit 339" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 18. " GSB338 ,Group Status Bit 338" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 17. " GSB337 ,Group Status Bit 337" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 16. " GSB336 ,Group Status Bit 336" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 15. " GSB335 ,Group Status Bit 335" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 14. " GSB334 ,Group Status Bit 334" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 13. " GSB333 ,Group Status Bit 333" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 12. " GSB332 ,Group Status Bit 332" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 11. " GSB331 ,Group Status Bit 331" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 10. " GSB330 ,Group Status Bit 330" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 9. " GSB329 ,Group Status Bit 329" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 8. " GSB328 ,Group Status Bit 328" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 7. " GSB327 ,Group Status Bit 327" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 6. " GSB326 ,Group Status Bit 326" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 5. " GSB325 ,Group Status Bit 325" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 4. " GSB324 ,Group Status Bit 324" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 3. " GSB323 ,Group Status Bit 323" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 2. " GSB322 ,Group Status Bit 322" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 1. " GSB321 ,Group Status Bit 321" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 0. " GSB320 ,Group Status Bit 320" "Group 0 (Secure),Group 1 (Non-secure)" elif (((per.l(ad:(per.long(spr:0x31F30)&0xFFFC0000)+0x04))&0x0000001F)>=0x0A) group.long 0x00A8++0x03 line.long 0x0 "GICD_IGROUPR10,Interrupt Group Register 10 (Non-secure access)" bitfld.long 0x00 31. " GSB351 ,Group Status Bit 351" "Group 0,Group 1" bitfld.long 0x00 30. " GSB350 ,Group Status Bit 350" "Group 0,Group 1" bitfld.long 0x00 29. " GSB349 ,Group Status Bit 349" "Group 0,Group 1" textline " " bitfld.long 0x00 28. " GSB348 ,Group Status Bit 348" "Group 0,Group 1" bitfld.long 0x00 27. " GSB347 ,Group Status Bit 347" "Group 0,Group 1" bitfld.long 0x00 26. " GSB346 ,Group Status Bit 346" "Group 0,Group 1" textline " " bitfld.long 0x00 25. " GSB345 ,Group Status Bit 345" "Group 0,Group 1" bitfld.long 0x00 24. " GSB344 ,Group Status Bit 344" "Group 0,Group 1" bitfld.long 0x00 23. " GSB343 ,Group Status Bit 343" "Group 0,Group 1" textline " " bitfld.long 0x00 22. " GSB342 ,Group Status Bit 342" "Group 0,Group 1" bitfld.long 0x00 21. " GSB341 ,Group Status Bit 341" "Group 0,Group 1" bitfld.long 0x00 20. " GSB340 ,Group Status Bit 340" "Group 0,Group 1" textline " " bitfld.long 0x00 19. " GSB339 ,Group Status Bit 339" "Group 0,Group 1" bitfld.long 0x00 18. " GSB338 ,Group Status Bit 338" "Group 0,Group 1" bitfld.long 0x00 17. " GSB337 ,Group Status Bit 337" "Group 0,Group 1" textline " " bitfld.long 0x00 16. " GSB336 ,Group Status Bit 336" "Group 0,Group 1" bitfld.long 0x00 15. " GSB335 ,Group Status Bit 335" "Group 0,Group 1" bitfld.long 0x00 14. " GSB334 ,Group Status Bit 334" "Group 0,Group 1" textline " " bitfld.long 0x00 13. " GSB333 ,Group Status Bit 333" "Group 0,Group 1" bitfld.long 0x00 12. " GSB332 ,Group Status Bit 332" "Group 0,Group 1" bitfld.long 0x00 11. " GSB331 ,Group Status Bit 331" "Group 0,Group 1" textline " " bitfld.long 0x00 10. " GSB330 ,Group Status Bit 330" "Group 0,Group 1" bitfld.long 0x00 9. " GSB329 ,Group Status Bit 329" "Group 0,Group 1" bitfld.long 0x00 8. " GSB328 ,Group Status Bit 328" "Group 0,Group 1" textline " " bitfld.long 0x00 7. " GSB327 ,Group Status Bit 327" "Group 0,Group 1" bitfld.long 0x00 6. " GSB326 ,Group Status Bit 326" "Group 0,Group 1" bitfld.long 0x00 5. " GSB325 ,Group Status Bit 325" "Group 0,Group 1" textline " " bitfld.long 0x00 4. " GSB324 ,Group Status Bit 324" "Group 0,Group 1" bitfld.long 0x00 3. " GSB323 ,Group Status Bit 323" "Group 0,Group 1" bitfld.long 0x00 2. " GSB322 ,Group Status Bit 322" "Group 0,Group 1" textline " " bitfld.long 0x00 1. " GSB321 ,Group Status Bit 321" "Group 0,Group 1" bitfld.long 0x00 0. " GSB320 ,Group Status Bit 320" "Group 0,Group 1" else rgroup.long 0x00A8++0x03 line.long 0x0 "GICD_IGROUPR10,Interrupt Group Register 10" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(ad:(per.long(spr:0x31F30)&0xFFFC0000)+0x04))&0x0000001F)>=0x0B)&&(PER.ADDRESS.isSECUREEX(ad:(per.long(spr:0x31F30)&0xFFFC0000)+0x00AC)) group.long 0x00AC++0x03 line.long 0x0 "GICD_IGROUPR11,Interrupt Group Register 11 (Secure access)" bitfld.long 0x00 31. " GSB383 ,Group Status Bit 383" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 30. " GSB382 ,Group Status Bit 382" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 29. " GSB381 ,Group Status Bit 381" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 28. " GSB380 ,Group Status Bit 380" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 27. " GSB379 ,Group Status Bit 379" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 26. " GSB378 ,Group Status Bit 378" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 25. " GSB377 ,Group Status Bit 377" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 24. " GSB376 ,Group Status Bit 376" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 23. " GSB375 ,Group Status Bit 375" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 22. " GSB374 ,Group Status Bit 374" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 21. " GSB373 ,Group Status Bit 373" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 20. " GSB372 ,Group Status Bit 372" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 19. " GSB371 ,Group Status Bit 371" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 18. " GSB370 ,Group Status Bit 370" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 17. " GSB369 ,Group Status Bit 369" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 16. " GSB368 ,Group Status Bit 368" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 15. " GSB367 ,Group Status Bit 367" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 14. " GSB366 ,Group Status Bit 366" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 13. " GSB365 ,Group Status Bit 365" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 12. " GSB364 ,Group Status Bit 364" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 11. " GSB363 ,Group Status Bit 363" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 10. " GSB362 ,Group Status Bit 362" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 9. " GSB361 ,Group Status Bit 361" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 8. " GSB360 ,Group Status Bit 360" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 7. " GSB359 ,Group Status Bit 359" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 6. " GSB358 ,Group Status Bit 358" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 5. " GSB357 ,Group Status Bit 357" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 4. " GSB356 ,Group Status Bit 356" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 3. " GSB355 ,Group Status Bit 355" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 2. " GSB354 ,Group Status Bit 354" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 1. " GSB353 ,Group Status Bit 353" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 0. " GSB352 ,Group Status Bit 352" "Group 0 (Secure),Group 1 (Non-secure)" elif (((per.l(ad:(per.long(spr:0x31F30)&0xFFFC0000)+0x04))&0x0000001F)>=0x0B) group.long 0x00AC++0x03 line.long 0x0 "GICD_IGROUPR11,Interrupt Group Register 11 (Non-secure access)" bitfld.long 0x00 31. " GSB383 ,Group Status Bit 383" "Group 0,Group 1" bitfld.long 0x00 30. " GSB382 ,Group Status Bit 382" "Group 0,Group 1" bitfld.long 0x00 29. " GSB381 ,Group Status Bit 381" "Group 0,Group 1" textline " " bitfld.long 0x00 28. " GSB380 ,Group Status Bit 380" "Group 0,Group 1" bitfld.long 0x00 27. " GSB379 ,Group Status Bit 379" "Group 0,Group 1" bitfld.long 0x00 26. " GSB378 ,Group Status Bit 378" "Group 0,Group 1" textline " " bitfld.long 0x00 25. " GSB377 ,Group Status Bit 377" "Group 0,Group 1" bitfld.long 0x00 24. " GSB376 ,Group Status Bit 376" "Group 0,Group 1" bitfld.long 0x00 23. " GSB375 ,Group Status Bit 375" "Group 0,Group 1" textline " " bitfld.long 0x00 22. " GSB374 ,Group Status Bit 374" "Group 0,Group 1" bitfld.long 0x00 21. " GSB373 ,Group Status Bit 373" "Group 0,Group 1" bitfld.long 0x00 20. " GSB372 ,Group Status Bit 372" "Group 0,Group 1" textline " " bitfld.long 0x00 19. " GSB371 ,Group Status Bit 371" "Group 0,Group 1" bitfld.long 0x00 18. " GSB370 ,Group Status Bit 370" "Group 0,Group 1" bitfld.long 0x00 17. " GSB369 ,Group Status Bit 369" "Group 0,Group 1" textline " " bitfld.long 0x00 16. " GSB368 ,Group Status Bit 368" "Group 0,Group 1" bitfld.long 0x00 15. " GSB367 ,Group Status Bit 367" "Group 0,Group 1" bitfld.long 0x00 14. " GSB366 ,Group Status Bit 366" "Group 0,Group 1" textline " " bitfld.long 0x00 13. " GSB365 ,Group Status Bit 365" "Group 0,Group 1" bitfld.long 0x00 12. " GSB364 ,Group Status Bit 364" "Group 0,Group 1" bitfld.long 0x00 11. " GSB363 ,Group Status Bit 363" "Group 0,Group 1" textline " " bitfld.long 0x00 10. " GSB362 ,Group Status Bit 362" "Group 0,Group 1" bitfld.long 0x00 9. " GSB361 ,Group Status Bit 361" "Group 0,Group 1" bitfld.long 0x00 8. " GSB360 ,Group Status Bit 360" "Group 0,Group 1" textline " " bitfld.long 0x00 7. " GSB359 ,Group Status Bit 359" "Group 0,Group 1" bitfld.long 0x00 6. " GSB358 ,Group Status Bit 358" "Group 0,Group 1" bitfld.long 0x00 5. " GSB357 ,Group Status Bit 357" "Group 0,Group 1" textline " " bitfld.long 0x00 4. " GSB356 ,Group Status Bit 356" "Group 0,Group 1" bitfld.long 0x00 3. " GSB355 ,Group Status Bit 355" "Group 0,Group 1" bitfld.long 0x00 2. " GSB354 ,Group Status Bit 354" "Group 0,Group 1" textline " " bitfld.long 0x00 1. " GSB353 ,Group Status Bit 353" "Group 0,Group 1" bitfld.long 0x00 0. " GSB352 ,Group Status Bit 352" "Group 0,Group 1" else rgroup.long 0x00AC++0x03 line.long 0x0 "GICD_IGROUPR11,Interrupt Group Register 11" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(ad:(per.long(spr:0x31F30)&0xFFFC0000)+0x04))&0x0000001F)>=0x0C)&&(PER.ADDRESS.isSECUREEX(ad:(per.long(spr:0x31F30)&0xFFFC0000)+0x00B0)) group.long 0x00B0++0x03 line.long 0x0 "GICD_IGROUPR12,Interrupt Group Register 12 (Secure access)" bitfld.long 0x00 31. " GSB415 ,Group Status Bit 415" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 30. " GSB414 ,Group Status Bit 414" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 29. " GSB413 ,Group Status Bit 413" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 28. " GSB412 ,Group Status Bit 412" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 27. " GSB411 ,Group Status Bit 411" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 26. " GSB410 ,Group Status Bit 410" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 25. " GSB409 ,Group Status Bit 409" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 24. " GSB408 ,Group Status Bit 408" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 23. " GSB407 ,Group Status Bit 407" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 22. " GSB406 ,Group Status Bit 406" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 21. " GSB405 ,Group Status Bit 405" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 20. " GSB404 ,Group Status Bit 404" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 19. " GSB403 ,Group Status Bit 403" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 18. " GSB402 ,Group Status Bit 402" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 17. " GSB401 ,Group Status Bit 401" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 16. " GSB400 ,Group Status Bit 400" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 15. " GSB399 ,Group Status Bit 399" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 14. " GSB398 ,Group Status Bit 398" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 13. " GSB397 ,Group Status Bit 397" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 12. " GSB396 ,Group Status Bit 396" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 11. " GSB395 ,Group Status Bit 395" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 10. " GSB394 ,Group Status Bit 394" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 9. " GSB393 ,Group Status Bit 393" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 8. " GSB392 ,Group Status Bit 392" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 7. " GSB391 ,Group Status Bit 391" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 6. " GSB390 ,Group Status Bit 390" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 5. " GSB389 ,Group Status Bit 389" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 4. " GSB388 ,Group Status Bit 388" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 3. " GSB387 ,Group Status Bit 387" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 2. " GSB386 ,Group Status Bit 386" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 1. " GSB385 ,Group Status Bit 385" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 0. " GSB384 ,Group Status Bit 384" "Group 0 (Secure),Group 1 (Non-secure)" elif (((per.l(ad:(per.long(spr:0x31F30)&0xFFFC0000)+0x04))&0x0000001F)>=0x0C) group.long 0x00B0++0x03 line.long 0x0 "GICD_IGROUPR12,Interrupt Group Register 12 (Non-secure access)" bitfld.long 0x00 31. " GSB415 ,Group Status Bit 415" "Group 0,Group 1" bitfld.long 0x00 30. " GSB414 ,Group Status Bit 414" "Group 0,Group 1" bitfld.long 0x00 29. " GSB413 ,Group Status Bit 413" "Group 0,Group 1" textline " " bitfld.long 0x00 28. " GSB412 ,Group Status Bit 412" "Group 0,Group 1" bitfld.long 0x00 27. " GSB411 ,Group Status Bit 411" "Group 0,Group 1" bitfld.long 0x00 26. " GSB410 ,Group Status Bit 410" "Group 0,Group 1" textline " " bitfld.long 0x00 25. " GSB409 ,Group Status Bit 409" "Group 0,Group 1" bitfld.long 0x00 24. " GSB408 ,Group Status Bit 408" "Group 0,Group 1" bitfld.long 0x00 23. " GSB407 ,Group Status Bit 407" "Group 0,Group 1" textline " " bitfld.long 0x00 22. " GSB406 ,Group Status Bit 406" "Group 0,Group 1" bitfld.long 0x00 21. " GSB405 ,Group Status Bit 405" "Group 0,Group 1" bitfld.long 0x00 20. " GSB404 ,Group Status Bit 404" "Group 0,Group 1" textline " " bitfld.long 0x00 19. " GSB403 ,Group Status Bit 403" "Group 0,Group 1" bitfld.long 0x00 18. " GSB402 ,Group Status Bit 402" "Group 0,Group 1" bitfld.long 0x00 17. " GSB401 ,Group Status Bit 401" "Group 0,Group 1" textline " " bitfld.long 0x00 16. " GSB400 ,Group Status Bit 400" "Group 0,Group 1" bitfld.long 0x00 15. " GSB399 ,Group Status Bit 399" "Group 0,Group 1" bitfld.long 0x00 14. " GSB398 ,Group Status Bit 398" "Group 0,Group 1" textline " " bitfld.long 0x00 13. " GSB397 ,Group Status Bit 397" "Group 0,Group 1" bitfld.long 0x00 12. " GSB396 ,Group Status Bit 396" "Group 0,Group 1" bitfld.long 0x00 11. " GSB395 ,Group Status Bit 395" "Group 0,Group 1" textline " " bitfld.long 0x00 10. " GSB394 ,Group Status Bit 394" "Group 0,Group 1" bitfld.long 0x00 9. " GSB393 ,Group Status Bit 393" "Group 0,Group 1" bitfld.long 0x00 8. " GSB392 ,Group Status Bit 392" "Group 0,Group 1" textline " " bitfld.long 0x00 7. " GSB391 ,Group Status Bit 391" "Group 0,Group 1" bitfld.long 0x00 6. " GSB390 ,Group Status Bit 390" "Group 0,Group 1" bitfld.long 0x00 5. " GSB389 ,Group Status Bit 389" "Group 0,Group 1" textline " " bitfld.long 0x00 4. " GSB388 ,Group Status Bit 388" "Group 0,Group 1" bitfld.long 0x00 3. " GSB387 ,Group Status Bit 387" "Group 0,Group 1" bitfld.long 0x00 2. " GSB386 ,Group Status Bit 386" "Group 0,Group 1" textline " " bitfld.long 0x00 1. " GSB385 ,Group Status Bit 385" "Group 0,Group 1" bitfld.long 0x00 0. " GSB384 ,Group Status Bit 384" "Group 0,Group 1" else rgroup.long 0x00B0++0x03 line.long 0x0 "GICD_IGROUPR12,Interrupt Group Register 12" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(ad:(per.long(spr:0x31F30)&0xFFFC0000)+0x04))&0x0000001F)>=0x0D)&&(PER.ADDRESS.isSECUREEX(ad:(per.long(spr:0x31F30)&0xFFFC0000)+0x00B4)) group.long 0x00B4++0x03 line.long 0x0 "GICD_IGROUPR13,Interrupt Group Register 13 (Secure access)" bitfld.long 0x00 31. " GSB447 ,Group Status Bit 447" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 30. " GSB446 ,Group Status Bit 446" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 29. " GSB445 ,Group Status Bit 445" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 28. " GSB444 ,Group Status Bit 444" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 27. " GSB443 ,Group Status Bit 443" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 26. " GSB442 ,Group Status Bit 442" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 25. " GSB441 ,Group Status Bit 441" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 24. " GSB440 ,Group Status Bit 440" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 23. " GSB439 ,Group Status Bit 439" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 22. " GSB438 ,Group Status Bit 438" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 21. " GSB437 ,Group Status Bit 437" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 20. " GSB436 ,Group Status Bit 436" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 19. " GSB435 ,Group Status Bit 435" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 18. " GSB434 ,Group Status Bit 434" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 17. " GSB433 ,Group Status Bit 433" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 16. " GSB432 ,Group Status Bit 432" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 15. " GSB431 ,Group Status Bit 431" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 14. " GSB430 ,Group Status Bit 430" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 13. " GSB429 ,Group Status Bit 429" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 12. " GSB428 ,Group Status Bit 428" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 11. " GSB427 ,Group Status Bit 427" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 10. " GSB426 ,Group Status Bit 426" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 9. " GSB425 ,Group Status Bit 425" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 8. " GSB424 ,Group Status Bit 424" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 7. " GSB423 ,Group Status Bit 423" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 6. " GSB422 ,Group Status Bit 422" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 5. " GSB421 ,Group Status Bit 421" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 4. " GSB420 ,Group Status Bit 420" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 3. " GSB419 ,Group Status Bit 419" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 2. " GSB418 ,Group Status Bit 418" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 1. " GSB417 ,Group Status Bit 417" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 0. " GSB416 ,Group Status Bit 416" "Group 0 (Secure),Group 1 (Non-secure)" elif (((per.l(ad:(per.long(spr:0x31F30)&0xFFFC0000)+0x04))&0x0000001F)>=0x0D) group.long 0x00B4++0x03 line.long 0x0 "GICD_IGROUPR13,Interrupt Group Register 13 (Non-secure access)" bitfld.long 0x00 31. " GSB447 ,Group Status Bit 447" "Group 0,Group 1" bitfld.long 0x00 30. " GSB446 ,Group Status Bit 446" "Group 0,Group 1" bitfld.long 0x00 29. " GSB445 ,Group Status Bit 445" "Group 0,Group 1" textline " " bitfld.long 0x00 28. " GSB444 ,Group Status Bit 444" "Group 0,Group 1" bitfld.long 0x00 27. " GSB443 ,Group Status Bit 443" "Group 0,Group 1" bitfld.long 0x00 26. " GSB442 ,Group Status Bit 442" "Group 0,Group 1" textline " " bitfld.long 0x00 25. " GSB441 ,Group Status Bit 441" "Group 0,Group 1" bitfld.long 0x00 24. " GSB440 ,Group Status Bit 440" "Group 0,Group 1" bitfld.long 0x00 23. " GSB439 ,Group Status Bit 439" "Group 0,Group 1" textline " " bitfld.long 0x00 22. " GSB438 ,Group Status Bit 438" "Group 0,Group 1" bitfld.long 0x00 21. " GSB437 ,Group Status Bit 437" "Group 0,Group 1" bitfld.long 0x00 20. " GSB436 ,Group Status Bit 436" "Group 0,Group 1" textline " " bitfld.long 0x00 19. " GSB435 ,Group Status Bit 435" "Group 0,Group 1" bitfld.long 0x00 18. " GSB434 ,Group Status Bit 434" "Group 0,Group 1" bitfld.long 0x00 17. " GSB433 ,Group Status Bit 433" "Group 0,Group 1" textline " " bitfld.long 0x00 16. " GSB432 ,Group Status Bit 432" "Group 0,Group 1" bitfld.long 0x00 15. " GSB431 ,Group Status Bit 431" "Group 0,Group 1" bitfld.long 0x00 14. " GSB430 ,Group Status Bit 430" "Group 0,Group 1" textline " " bitfld.long 0x00 13. " GSB429 ,Group Status Bit 429" "Group 0,Group 1" bitfld.long 0x00 12. " GSB428 ,Group Status Bit 428" "Group 0,Group 1" bitfld.long 0x00 11. " GSB427 ,Group Status Bit 427" "Group 0,Group 1" textline " " bitfld.long 0x00 10. " GSB426 ,Group Status Bit 426" "Group 0,Group 1" bitfld.long 0x00 9. " GSB425 ,Group Status Bit 425" "Group 0,Group 1" bitfld.long 0x00 8. " GSB424 ,Group Status Bit 424" "Group 0,Group 1" textline " " bitfld.long 0x00 7. " GSB423 ,Group Status Bit 423" "Group 0,Group 1" bitfld.long 0x00 6. " GSB422 ,Group Status Bit 422" "Group 0,Group 1" bitfld.long 0x00 5. " GSB421 ,Group Status Bit 421" "Group 0,Group 1" textline " " bitfld.long 0x00 4. " GSB420 ,Group Status Bit 420" "Group 0,Group 1" bitfld.long 0x00 3. " GSB419 ,Group Status Bit 419" "Group 0,Group 1" bitfld.long 0x00 2. " GSB418 ,Group Status Bit 418" "Group 0,Group 1" textline " " bitfld.long 0x00 1. " GSB417 ,Group Status Bit 417" "Group 0,Group 1" bitfld.long 0x00 0. " GSB416 ,Group Status Bit 416" "Group 0,Group 1" else rgroup.long 0x00B4++0x03 line.long 0x0 "GICD_IGROUPR13,Interrupt Group Register 13" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(ad:(per.long(spr:0x31F30)&0xFFFC0000)+0x04))&0x0000001F)>=0x0E)&&(PER.ADDRESS.isSECUREEX(ad:(per.long(spr:0x31F30)&0xFFFC0000)+0x00B8)) group.long 0x00B8++0x03 line.long 0x0 "GICD_IGROUPR14,Interrupt Group Register 14 (Secure access)" bitfld.long 0x00 31. " GSB479 ,Group Status Bit 479" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 30. " GSB478 ,Group Status Bit 478" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 29. " GSB477 ,Group Status Bit 477" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 28. " GSB476 ,Group Status Bit 476" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 27. " GSB475 ,Group Status Bit 475" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 26. " GSB474 ,Group Status Bit 474" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 25. " GSB473 ,Group Status Bit 473" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 24. " GSB472 ,Group Status Bit 472" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 23. " GSB471 ,Group Status Bit 471" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 22. " GSB470 ,Group Status Bit 470" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 21. " GSB469 ,Group Status Bit 469" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 20. " GSB468 ,Group Status Bit 468" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 19. " GSB467 ,Group Status Bit 467" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 18. " GSB466 ,Group Status Bit 466" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 17. " GSB465 ,Group Status Bit 465" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 16. " GSB464 ,Group Status Bit 464" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 15. " GSB463 ,Group Status Bit 463" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 14. " GSB462 ,Group Status Bit 462" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 13. " GSB461 ,Group Status Bit 461" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 12. " GSB460 ,Group Status Bit 460" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 11. " GSB459 ,Group Status Bit 459" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 10. " GSB458 ,Group Status Bit 458" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 9. " GSB457 ,Group Status Bit 457" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 8. " GSB456 ,Group Status Bit 456" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 7. " GSB455 ,Group Status Bit 455" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 6. " GSB454 ,Group Status Bit 454" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 5. " GSB453 ,Group Status Bit 453" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 4. " GSB452 ,Group Status Bit 452" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 3. " GSB451 ,Group Status Bit 451" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 2. " GSB450 ,Group Status Bit 450" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 1. " GSB449 ,Group Status Bit 449" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 0. " GSB448 ,Group Status Bit 448" "Group 0 (Secure),Group 1 (Non-secure)" elif (((per.l(ad:(per.long(spr:0x31F30)&0xFFFC0000)+0x04))&0x0000001F)>=0x0E) group.long 0x00B8++0x03 line.long 0x0 "GICD_IGROUPR14,Interrupt Group Register 14 (Non-secure access)" bitfld.long 0x00 31. " GSB479 ,Group Status Bit 479" "Group 0,Group 1" bitfld.long 0x00 30. " GSB478 ,Group Status Bit 478" "Group 0,Group 1" bitfld.long 0x00 29. " GSB477 ,Group Status Bit 477" "Group 0,Group 1" textline " " bitfld.long 0x00 28. " GSB476 ,Group Status Bit 476" "Group 0,Group 1" bitfld.long 0x00 27. " GSB475 ,Group Status Bit 475" "Group 0,Group 1" bitfld.long 0x00 26. " GSB474 ,Group Status Bit 474" "Group 0,Group 1" textline " " bitfld.long 0x00 25. " GSB473 ,Group Status Bit 473" "Group 0,Group 1" bitfld.long 0x00 24. " GSB472 ,Group Status Bit 472" "Group 0,Group 1" bitfld.long 0x00 23. " GSB471 ,Group Status Bit 471" "Group 0,Group 1" textline " " bitfld.long 0x00 22. " GSB470 ,Group Status Bit 470" "Group 0,Group 1" bitfld.long 0x00 21. " GSB469 ,Group Status Bit 469" "Group 0,Group 1" bitfld.long 0x00 20. " GSB468 ,Group Status Bit 468" "Group 0,Group 1" textline " " bitfld.long 0x00 19. " GSB467 ,Group Status Bit 467" "Group 0,Group 1" bitfld.long 0x00 18. " GSB466 ,Group Status Bit 466" "Group 0,Group 1" bitfld.long 0x00 17. " GSB465 ,Group Status Bit 465" "Group 0,Group 1" textline " " bitfld.long 0x00 16. " GSB464 ,Group Status Bit 464" "Group 0,Group 1" bitfld.long 0x00 15. " GSB463 ,Group Status Bit 463" "Group 0,Group 1" bitfld.long 0x00 14. " GSB462 ,Group Status Bit 462" "Group 0,Group 1" textline " " bitfld.long 0x00 13. " GSB461 ,Group Status Bit 461" "Group 0,Group 1" bitfld.long 0x00 12. " GSB460 ,Group Status Bit 460" "Group 0,Group 1" bitfld.long 0x00 11. " GSB459 ,Group Status Bit 459" "Group 0,Group 1" textline " " bitfld.long 0x00 10. " GSB458 ,Group Status Bit 458" "Group 0,Group 1" bitfld.long 0x00 9. " GSB457 ,Group Status Bit 457" "Group 0,Group 1" bitfld.long 0x00 8. " GSB456 ,Group Status Bit 456" "Group 0,Group 1" textline " " bitfld.long 0x00 7. " GSB455 ,Group Status Bit 455" "Group 0,Group 1" bitfld.long 0x00 6. " GSB454 ,Group Status Bit 454" "Group 0,Group 1" bitfld.long 0x00 5. " GSB453 ,Group Status Bit 453" "Group 0,Group 1" textline " " bitfld.long 0x00 4. " GSB452 ,Group Status Bit 452" "Group 0,Group 1" bitfld.long 0x00 3. " GSB451 ,Group Status Bit 451" "Group 0,Group 1" bitfld.long 0x00 2. " GSB450 ,Group Status Bit 450" "Group 0,Group 1" textline " " bitfld.long 0x00 1. " GSB449 ,Group Status Bit 449" "Group 0,Group 1" bitfld.long 0x00 0. " GSB448 ,Group Status Bit 448" "Group 0,Group 1" else rgroup.long 0x00B8++0x03 line.long 0x0 "GICD_IGROUPR14,Interrupt Group Register 14" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(ad:(per.long(spr:0x31F30)&0xFFFC0000)+0x04))&0x0000001F)>=0x0F)&&(PER.ADDRESS.isSECUREEX(ad:(per.long(spr:0x31F30)&0xFFFC0000)+0x00BC)) group.long 0x00BC++0x03 line.long 0x0 "GICD_IGROUPR15,Interrupt Group Register 15 (Secure access)" bitfld.long 0x00 31. " GSB511 ,Group Status Bit 511" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 30. " GSB510 ,Group Status Bit 510" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 29. " GSB509 ,Group Status Bit 509" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 28. " GSB508 ,Group Status Bit 508" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 27. " GSB507 ,Group Status Bit 507" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 26. " GSB506 ,Group Status Bit 506" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 25. " GSB505 ,Group Status Bit 505" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 24. " GSB504 ,Group Status Bit 504" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 23. " GSB503 ,Group Status Bit 503" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 22. " GSB502 ,Group Status Bit 502" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 21. " GSB501 ,Group Status Bit 501" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 20. " GSB500 ,Group Status Bit 500" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 19. " GSB499 ,Group Status Bit 499" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 18. " GSB498 ,Group Status Bit 498" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 17. " GSB497 ,Group Status Bit 497" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 16. " GSB496 ,Group Status Bit 496" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 15. " GSB495 ,Group Status Bit 495" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 14. " GSB494 ,Group Status Bit 494" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 13. " GSB493 ,Group Status Bit 493" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 12. " GSB492 ,Group Status Bit 492" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 11. " GSB491 ,Group Status Bit 491" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 10. " GSB490 ,Group Status Bit 490" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 9. " GSB489 ,Group Status Bit 489" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 8. " GSB488 ,Group Status Bit 488" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 7. " GSB487 ,Group Status Bit 487" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 6. " GSB486 ,Group Status Bit 486" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 5. " GSB485 ,Group Status Bit 485" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 4. " GSB484 ,Group Status Bit 484" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 3. " GSB483 ,Group Status Bit 483" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 2. " GSB482 ,Group Status Bit 482" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 1. " GSB481 ,Group Status Bit 481" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 0. " GSB480 ,Group Status Bit 480" "Group 0 (Secure),Group 1 (Non-secure)" elif (((per.l(ad:(per.long(spr:0x31F30)&0xFFFC0000)+0x04))&0x0000001F)>=0x0F) group.long 0x00BC++0x03 line.long 0x0 "GICD_IGROUPR15,Interrupt Group Register 15 (Non-secure access)" bitfld.long 0x00 31. " GSB511 ,Group Status Bit 511" "Group 0,Group 1" bitfld.long 0x00 30. " GSB510 ,Group Status Bit 510" "Group 0,Group 1" bitfld.long 0x00 29. " GSB509 ,Group Status Bit 509" "Group 0,Group 1" textline " " bitfld.long 0x00 28. " GSB508 ,Group Status Bit 508" "Group 0,Group 1" bitfld.long 0x00 27. " GSB507 ,Group Status Bit 507" "Group 0,Group 1" bitfld.long 0x00 26. " GSB506 ,Group Status Bit 506" "Group 0,Group 1" textline " " bitfld.long 0x00 25. " GSB505 ,Group Status Bit 505" "Group 0,Group 1" bitfld.long 0x00 24. " GSB504 ,Group Status Bit 504" "Group 0,Group 1" bitfld.long 0x00 23. " GSB503 ,Group Status Bit 503" "Group 0,Group 1" textline " " bitfld.long 0x00 22. " GSB502 ,Group Status Bit 502" "Group 0,Group 1" bitfld.long 0x00 21. " GSB501 ,Group Status Bit 501" "Group 0,Group 1" bitfld.long 0x00 20. " GSB500 ,Group Status Bit 500" "Group 0,Group 1" textline " " bitfld.long 0x00 19. " GSB499 ,Group Status Bit 499" "Group 0,Group 1" bitfld.long 0x00 18. " GSB498 ,Group Status Bit 498" "Group 0,Group 1" bitfld.long 0x00 17. " GSB497 ,Group Status Bit 497" "Group 0,Group 1" textline " " bitfld.long 0x00 16. " GSB496 ,Group Status Bit 496" "Group 0,Group 1" bitfld.long 0x00 15. " GSB495 ,Group Status Bit 495" "Group 0,Group 1" bitfld.long 0x00 14. " GSB494 ,Group Status Bit 494" "Group 0,Group 1" textline " " bitfld.long 0x00 13. " GSB493 ,Group Status Bit 493" "Group 0,Group 1" bitfld.long 0x00 12. " GSB492 ,Group Status Bit 492" "Group 0,Group 1" bitfld.long 0x00 11. " GSB491 ,Group Status Bit 491" "Group 0,Group 1" textline " " bitfld.long 0x00 10. " GSB490 ,Group Status Bit 490" "Group 0,Group 1" bitfld.long 0x00 9. " GSB489 ,Group Status Bit 489" "Group 0,Group 1" bitfld.long 0x00 8. " GSB488 ,Group Status Bit 488" "Group 0,Group 1" textline " " bitfld.long 0x00 7. " GSB487 ,Group Status Bit 487" "Group 0,Group 1" bitfld.long 0x00 6. " GSB486 ,Group Status Bit 486" "Group 0,Group 1" bitfld.long 0x00 5. " GSB485 ,Group Status Bit 485" "Group 0,Group 1" textline " " bitfld.long 0x00 4. " GSB484 ,Group Status Bit 484" "Group 0,Group 1" bitfld.long 0x00 3. " GSB483 ,Group Status Bit 483" "Group 0,Group 1" bitfld.long 0x00 2. " GSB482 ,Group Status Bit 482" "Group 0,Group 1" textline " " bitfld.long 0x00 1. " GSB481 ,Group Status Bit 481" "Group 0,Group 1" bitfld.long 0x00 0. " GSB480 ,Group Status Bit 480" "Group 0,Group 1" else rgroup.long 0x00BC++0x03 line.long 0x0 "GICD_IGROUPR15,Interrupt Group Register 15" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(ad:(per.long(spr:0x31F30)&0xFFFC0000)+0x04))&0x0000001F)>=0x10)&&(PER.ADDRESS.isSECUREEX(ad:(per.long(spr:0x31F30)&0xFFFC0000)+0x00C0)) group.long 0x00C0++0x03 line.long 0x0 "GICD_IGROUPR16,Interrupt Group Register 16 (Secure access)" bitfld.long 0x00 31. " GSB543 ,Group Status Bit 543" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 30. " GSB542 ,Group Status Bit 542" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 29. " GSB541 ,Group Status Bit 541" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 28. " GSB540 ,Group Status Bit 540" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 27. " GSB539 ,Group Status Bit 539" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 26. " GSB538 ,Group Status Bit 538" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 25. " GSB537 ,Group Status Bit 537" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 24. " GSB536 ,Group Status Bit 536" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 23. " GSB535 ,Group Status Bit 535" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 22. " GSB534 ,Group Status Bit 534" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 21. " GSB533 ,Group Status Bit 533" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 20. " GSB532 ,Group Status Bit 532" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 19. " GSB531 ,Group Status Bit 531" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 18. " GSB530 ,Group Status Bit 530" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 17. " GSB529 ,Group Status Bit 529" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 16. " GSB528 ,Group Status Bit 528" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 15. " GSB527 ,Group Status Bit 527" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 14. " GSB526 ,Group Status Bit 526" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 13. " GSB525 ,Group Status Bit 525" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 12. " GSB524 ,Group Status Bit 524" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 11. " GSB523 ,Group Status Bit 523" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 10. " GSB522 ,Group Status Bit 522" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 9. " GSB521 ,Group Status Bit 521" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 8. " GSB520 ,Group Status Bit 520" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 7. " GSB519 ,Group Status Bit 519" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 6. " GSB518 ,Group Status Bit 518" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 5. " GSB517 ,Group Status Bit 517" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 4. " GSB516 ,Group Status Bit 516" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 3. " GSB515 ,Group Status Bit 515" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 2. " GSB514 ,Group Status Bit 514" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 1. " GSB513 ,Group Status Bit 513" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 0. " GSB512 ,Group Status Bit 512" "Group 0 (Secure),Group 1 (Non-secure)" elif (((per.l(ad:(per.long(spr:0x31F30)&0xFFFC0000)+0x04))&0x0000001F)>=0x10) group.long 0x00C0++0x03 line.long 0x0 "GICD_IGROUPR16,Interrupt Group Register 16 (Non-secure access)" bitfld.long 0x00 31. " GSB543 ,Group Status Bit 543" "Group 0,Group 1" bitfld.long 0x00 30. " GSB542 ,Group Status Bit 542" "Group 0,Group 1" bitfld.long 0x00 29. " GSB541 ,Group Status Bit 541" "Group 0,Group 1" textline " " bitfld.long 0x00 28. " GSB540 ,Group Status Bit 540" "Group 0,Group 1" bitfld.long 0x00 27. " GSB539 ,Group Status Bit 539" "Group 0,Group 1" bitfld.long 0x00 26. " GSB538 ,Group Status Bit 538" "Group 0,Group 1" textline " " bitfld.long 0x00 25. " GSB537 ,Group Status Bit 537" "Group 0,Group 1" bitfld.long 0x00 24. " GSB536 ,Group Status Bit 536" "Group 0,Group 1" bitfld.long 0x00 23. " GSB535 ,Group Status Bit 535" "Group 0,Group 1" textline " " bitfld.long 0x00 22. " GSB534 ,Group Status Bit 534" "Group 0,Group 1" bitfld.long 0x00 21. " GSB533 ,Group Status Bit 533" "Group 0,Group 1" bitfld.long 0x00 20. " GSB532 ,Group Status Bit 532" "Group 0,Group 1" textline " " bitfld.long 0x00 19. " GSB531 ,Group Status Bit 531" "Group 0,Group 1" bitfld.long 0x00 18. " GSB530 ,Group Status Bit 530" "Group 0,Group 1" bitfld.long 0x00 17. " GSB529 ,Group Status Bit 529" "Group 0,Group 1" textline " " bitfld.long 0x00 16. " GSB528 ,Group Status Bit 528" "Group 0,Group 1" bitfld.long 0x00 15. " GSB527 ,Group Status Bit 527" "Group 0,Group 1" bitfld.long 0x00 14. " GSB526 ,Group Status Bit 526" "Group 0,Group 1" textline " " bitfld.long 0x00 13. " GSB525 ,Group Status Bit 525" "Group 0,Group 1" bitfld.long 0x00 12. " GSB524 ,Group Status Bit 524" "Group 0,Group 1" bitfld.long 0x00 11. " GSB523 ,Group Status Bit 523" "Group 0,Group 1" textline " " bitfld.long 0x00 10. " GSB522 ,Group Status Bit 522" "Group 0,Group 1" bitfld.long 0x00 9. " GSB521 ,Group Status Bit 521" "Group 0,Group 1" bitfld.long 0x00 8. " GSB520 ,Group Status Bit 520" "Group 0,Group 1" textline " " bitfld.long 0x00 7. " GSB519 ,Group Status Bit 519" "Group 0,Group 1" bitfld.long 0x00 6. " GSB518 ,Group Status Bit 518" "Group 0,Group 1" bitfld.long 0x00 5. " GSB517 ,Group Status Bit 517" "Group 0,Group 1" textline " " bitfld.long 0x00 4. " GSB516 ,Group Status Bit 516" "Group 0,Group 1" bitfld.long 0x00 3. " GSB515 ,Group Status Bit 515" "Group 0,Group 1" bitfld.long 0x00 2. " GSB514 ,Group Status Bit 514" "Group 0,Group 1" textline " " bitfld.long 0x00 1. " GSB513 ,Group Status Bit 513" "Group 0,Group 1" bitfld.long 0x00 0. " GSB512 ,Group Status Bit 512" "Group 0,Group 1" else rgroup.long 0x00C0++0x03 line.long 0x0 "GICD_IGROUPR16,Interrupt Group Register 16" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(ad:(per.long(spr:0x31F30)&0xFFFC0000)+0x04))&0x0000001F)>=0x11)&&(PER.ADDRESS.isSECUREEX(ad:(per.long(spr:0x31F30)&0xFFFC0000)+0x00C4)) group.long 0x00C4++0x03 line.long 0x0 "GICD_IGROUPR17,Interrupt Group Register 17 (Secure access)" bitfld.long 0x00 31. " GSB575 ,Group Status Bit 575" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 30. " GSB574 ,Group Status Bit 574" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 29. " GSB573 ,Group Status Bit 573" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 28. " GSB572 ,Group Status Bit 572" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 27. " GSB571 ,Group Status Bit 571" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 26. " GSB570 ,Group Status Bit 570" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 25. " GSB569 ,Group Status Bit 569" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 24. " GSB568 ,Group Status Bit 568" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 23. " GSB567 ,Group Status Bit 567" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 22. " GSB566 ,Group Status Bit 566" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 21. " GSB565 ,Group Status Bit 565" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 20. " GSB564 ,Group Status Bit 564" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 19. " GSB563 ,Group Status Bit 563" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 18. " GSB562 ,Group Status Bit 562" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 17. " GSB561 ,Group Status Bit 561" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 16. " GSB560 ,Group Status Bit 560" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 15. " GSB559 ,Group Status Bit 559" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 14. " GSB558 ,Group Status Bit 558" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 13. " GSB557 ,Group Status Bit 557" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 12. " GSB556 ,Group Status Bit 556" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 11. " GSB555 ,Group Status Bit 555" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 10. " GSB554 ,Group Status Bit 554" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 9. " GSB553 ,Group Status Bit 553" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 8. " GSB552 ,Group Status Bit 552" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 7. " GSB551 ,Group Status Bit 551" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 6. " GSB550 ,Group Status Bit 550" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 5. " GSB549 ,Group Status Bit 549" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 4. " GSB548 ,Group Status Bit 548" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 3. " GSB547 ,Group Status Bit 547" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 2. " GSB546 ,Group Status Bit 546" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 1. " GSB545 ,Group Status Bit 545" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 0. " GSB544 ,Group Status Bit 544" "Group 0 (Secure),Group 1 (Non-secure)" elif (((per.l(ad:(per.long(spr:0x31F30)&0xFFFC0000)+0x04))&0x0000001F)>=0x11) group.long 0x00C4++0x03 line.long 0x0 "GICD_IGROUPR17,Interrupt Group Register 17 (Non-secure access)" bitfld.long 0x00 31. " GSB575 ,Group Status Bit 575" "Group 0,Group 1" bitfld.long 0x00 30. " GSB574 ,Group Status Bit 574" "Group 0,Group 1" bitfld.long 0x00 29. " GSB573 ,Group Status Bit 573" "Group 0,Group 1" textline " " bitfld.long 0x00 28. " GSB572 ,Group Status Bit 572" "Group 0,Group 1" bitfld.long 0x00 27. " GSB571 ,Group Status Bit 571" "Group 0,Group 1" bitfld.long 0x00 26. " GSB570 ,Group Status Bit 570" "Group 0,Group 1" textline " " bitfld.long 0x00 25. " GSB569 ,Group Status Bit 569" "Group 0,Group 1" bitfld.long 0x00 24. " GSB568 ,Group Status Bit 568" "Group 0,Group 1" bitfld.long 0x00 23. " GSB567 ,Group Status Bit 567" "Group 0,Group 1" textline " " bitfld.long 0x00 22. " GSB566 ,Group Status Bit 566" "Group 0,Group 1" bitfld.long 0x00 21. " GSB565 ,Group Status Bit 565" "Group 0,Group 1" bitfld.long 0x00 20. " GSB564 ,Group Status Bit 564" "Group 0,Group 1" textline " " bitfld.long 0x00 19. " GSB563 ,Group Status Bit 563" "Group 0,Group 1" bitfld.long 0x00 18. " GSB562 ,Group Status Bit 562" "Group 0,Group 1" bitfld.long 0x00 17. " GSB561 ,Group Status Bit 561" "Group 0,Group 1" textline " " bitfld.long 0x00 16. " GSB560 ,Group Status Bit 560" "Group 0,Group 1" bitfld.long 0x00 15. " GSB559 ,Group Status Bit 559" "Group 0,Group 1" bitfld.long 0x00 14. " GSB558 ,Group Status Bit 558" "Group 0,Group 1" textline " " bitfld.long 0x00 13. " GSB557 ,Group Status Bit 557" "Group 0,Group 1" bitfld.long 0x00 12. " GSB556 ,Group Status Bit 556" "Group 0,Group 1" bitfld.long 0x00 11. " GSB555 ,Group Status Bit 555" "Group 0,Group 1" textline " " bitfld.long 0x00 10. " GSB554 ,Group Status Bit 554" "Group 0,Group 1" bitfld.long 0x00 9. " GSB553 ,Group Status Bit 553" "Group 0,Group 1" bitfld.long 0x00 8. " GSB552 ,Group Status Bit 552" "Group 0,Group 1" textline " " bitfld.long 0x00 7. " GSB551 ,Group Status Bit 551" "Group 0,Group 1" bitfld.long 0x00 6. " GSB550 ,Group Status Bit 550" "Group 0,Group 1" bitfld.long 0x00 5. " GSB549 ,Group Status Bit 549" "Group 0,Group 1" textline " " bitfld.long 0x00 4. " GSB548 ,Group Status Bit 548" "Group 0,Group 1" bitfld.long 0x00 3. " GSB547 ,Group Status Bit 547" "Group 0,Group 1" bitfld.long 0x00 2. " GSB546 ,Group Status Bit 546" "Group 0,Group 1" textline " " bitfld.long 0x00 1. " GSB545 ,Group Status Bit 545" "Group 0,Group 1" bitfld.long 0x00 0. " GSB544 ,Group Status Bit 544" "Group 0,Group 1" else rgroup.long 0x00C4++0x03 line.long 0x0 "GICD_IGROUPR17,Interrupt Group Register 17" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(ad:(per.long(spr:0x31F30)&0xFFFC0000)+0x04))&0x0000001F)>=0x12)&&(PER.ADDRESS.isSECUREEX(ad:(per.long(spr:0x31F30)&0xFFFC0000)+0x00C8)) group.long 0x00C8++0x03 line.long 0x0 "GICD_IGROUPR18,Interrupt Group Register 18 (Secure access)" bitfld.long 0x00 31. " GSB607 ,Group Status Bit 607" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 30. " GSB606 ,Group Status Bit 606" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 29. " GSB605 ,Group Status Bit 605" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 28. " GSB604 ,Group Status Bit 604" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 27. " GSB603 ,Group Status Bit 603" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 26. " GSB602 ,Group Status Bit 602" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 25. " GSB601 ,Group Status Bit 601" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 24. " GSB600 ,Group Status Bit 600" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 23. " GSB599 ,Group Status Bit 599" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 22. " GSB598 ,Group Status Bit 598" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 21. " GSB597 ,Group Status Bit 597" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 20. " GSB596 ,Group Status Bit 596" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 19. " GSB595 ,Group Status Bit 595" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 18. " GSB594 ,Group Status Bit 594" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 17. " GSB593 ,Group Status Bit 593" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 16. " GSB592 ,Group Status Bit 592" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 15. " GSB591 ,Group Status Bit 591" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 14. " GSB590 ,Group Status Bit 590" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 13. " GSB589 ,Group Status Bit 589" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 12. " GSB588 ,Group Status Bit 588" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 11. " GSB587 ,Group Status Bit 587" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 10. " GSB586 ,Group Status Bit 586" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 9. " GSB585 ,Group Status Bit 585" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 8. " GSB584 ,Group Status Bit 584" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 7. " GSB583 ,Group Status Bit 583" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 6. " GSB582 ,Group Status Bit 582" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 5. " GSB581 ,Group Status Bit 581" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 4. " GSB580 ,Group Status Bit 580" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 3. " GSB579 ,Group Status Bit 579" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 2. " GSB578 ,Group Status Bit 578" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 1. " GSB577 ,Group Status Bit 577" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 0. " GSB576 ,Group Status Bit 576" "Group 0 (Secure),Group 1 (Non-secure)" elif (((per.l(ad:(per.long(spr:0x31F30)&0xFFFC0000)+0x04))&0x0000001F)>=0x12) group.long 0x00C8++0x03 line.long 0x0 "GICD_IGROUPR18,Interrupt Group Register 18 (Non-secure access)" bitfld.long 0x00 31. " GSB607 ,Group Status Bit 607" "Group 0,Group 1" bitfld.long 0x00 30. " GSB606 ,Group Status Bit 606" "Group 0,Group 1" bitfld.long 0x00 29. " GSB605 ,Group Status Bit 605" "Group 0,Group 1" textline " " bitfld.long 0x00 28. " GSB604 ,Group Status Bit 604" "Group 0,Group 1" bitfld.long 0x00 27. " GSB603 ,Group Status Bit 603" "Group 0,Group 1" bitfld.long 0x00 26. " GSB602 ,Group Status Bit 602" "Group 0,Group 1" textline " " bitfld.long 0x00 25. " GSB601 ,Group Status Bit 601" "Group 0,Group 1" bitfld.long 0x00 24. " GSB600 ,Group Status Bit 600" "Group 0,Group 1" bitfld.long 0x00 23. " GSB599 ,Group Status Bit 599" "Group 0,Group 1" textline " " bitfld.long 0x00 22. " GSB598 ,Group Status Bit 598" "Group 0,Group 1" bitfld.long 0x00 21. " GSB597 ,Group Status Bit 597" "Group 0,Group 1" bitfld.long 0x00 20. " GSB596 ,Group Status Bit 596" "Group 0,Group 1" textline " " bitfld.long 0x00 19. " GSB595 ,Group Status Bit 595" "Group 0,Group 1" bitfld.long 0x00 18. " GSB594 ,Group Status Bit 594" "Group 0,Group 1" bitfld.long 0x00 17. " GSB593 ,Group Status Bit 593" "Group 0,Group 1" textline " " bitfld.long 0x00 16. " GSB592 ,Group Status Bit 592" "Group 0,Group 1" bitfld.long 0x00 15. " GSB591 ,Group Status Bit 591" "Group 0,Group 1" bitfld.long 0x00 14. " GSB590 ,Group Status Bit 590" "Group 0,Group 1" textline " " bitfld.long 0x00 13. " GSB589 ,Group Status Bit 589" "Group 0,Group 1" bitfld.long 0x00 12. " GSB588 ,Group Status Bit 588" "Group 0,Group 1" bitfld.long 0x00 11. " GSB587 ,Group Status Bit 587" "Group 0,Group 1" textline " " bitfld.long 0x00 10. " GSB586 ,Group Status Bit 586" "Group 0,Group 1" bitfld.long 0x00 9. " GSB585 ,Group Status Bit 585" "Group 0,Group 1" bitfld.long 0x00 8. " GSB584 ,Group Status Bit 584" "Group 0,Group 1" textline " " bitfld.long 0x00 7. " GSB583 ,Group Status Bit 583" "Group 0,Group 1" bitfld.long 0x00 6. " GSB582 ,Group Status Bit 582" "Group 0,Group 1" bitfld.long 0x00 5. " GSB581 ,Group Status Bit 581" "Group 0,Group 1" textline " " bitfld.long 0x00 4. " GSB580 ,Group Status Bit 580" "Group 0,Group 1" bitfld.long 0x00 3. " GSB579 ,Group Status Bit 579" "Group 0,Group 1" bitfld.long 0x00 2. " GSB578 ,Group Status Bit 578" "Group 0,Group 1" textline " " bitfld.long 0x00 1. " GSB577 ,Group Status Bit 577" "Group 0,Group 1" bitfld.long 0x00 0. " GSB576 ,Group Status Bit 576" "Group 0,Group 1" else rgroup.long 0x00C8++0x03 line.long 0x0 "GICD_IGROUPR18,Interrupt Group Register 18" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(ad:(per.long(spr:0x31F30)&0xFFFC0000)+0x04))&0x0000001F)>=0x13)&&(PER.ADDRESS.isSECUREEX(ad:(per.long(spr:0x31F30)&0xFFFC0000)+0x00CC)) group.long 0x00CC++0x03 line.long 0x0 "GICD_IGROUPR19,Interrupt Group Register 19 (Secure access)" bitfld.long 0x00 31. " GSB639 ,Group Status Bit 639" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 30. " GSB638 ,Group Status Bit 638" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 29. " GSB637 ,Group Status Bit 637" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 28. " GSB636 ,Group Status Bit 636" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 27. " GSB635 ,Group Status Bit 635" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 26. " GSB634 ,Group Status Bit 634" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 25. " GSB633 ,Group Status Bit 633" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 24. " GSB632 ,Group Status Bit 632" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 23. " GSB631 ,Group Status Bit 631" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 22. " GSB630 ,Group Status Bit 630" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 21. " GSB629 ,Group Status Bit 629" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 20. " GSB628 ,Group Status Bit 628" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 19. " GSB627 ,Group Status Bit 627" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 18. " GSB626 ,Group Status Bit 626" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 17. " GSB625 ,Group Status Bit 625" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 16. " GSB624 ,Group Status Bit 624" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 15. " GSB623 ,Group Status Bit 623" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 14. " GSB622 ,Group Status Bit 622" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 13. " GSB621 ,Group Status Bit 621" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 12. " GSB620 ,Group Status Bit 620" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 11. " GSB619 ,Group Status Bit 619" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 10. " GSB618 ,Group Status Bit 618" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 9. " GSB617 ,Group Status Bit 617" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 8. " GSB616 ,Group Status Bit 616" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 7. " GSB615 ,Group Status Bit 615" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 6. " GSB614 ,Group Status Bit 614" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 5. " GSB613 ,Group Status Bit 613" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 4. " GSB612 ,Group Status Bit 612" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 3. " GSB611 ,Group Status Bit 611" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 2. " GSB610 ,Group Status Bit 610" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 1. " GSB609 ,Group Status Bit 609" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 0. " GSB608 ,Group Status Bit 608" "Group 0 (Secure),Group 1 (Non-secure)" elif (((per.l(ad:(per.long(spr:0x31F30)&0xFFFC0000)+0x04))&0x0000001F)>=0x13) group.long 0x00CC++0x03 line.long 0x0 "GICD_IGROUPR19,Interrupt Group Register 19 (Non-secure access)" bitfld.long 0x00 31. " GSB639 ,Group Status Bit 639" "Group 0,Group 1" bitfld.long 0x00 30. " GSB638 ,Group Status Bit 638" "Group 0,Group 1" bitfld.long 0x00 29. " GSB637 ,Group Status Bit 637" "Group 0,Group 1" textline " " bitfld.long 0x00 28. " GSB636 ,Group Status Bit 636" "Group 0,Group 1" bitfld.long 0x00 27. " GSB635 ,Group Status Bit 635" "Group 0,Group 1" bitfld.long 0x00 26. " GSB634 ,Group Status Bit 634" "Group 0,Group 1" textline " " bitfld.long 0x00 25. " GSB633 ,Group Status Bit 633" "Group 0,Group 1" bitfld.long 0x00 24. " GSB632 ,Group Status Bit 632" "Group 0,Group 1" bitfld.long 0x00 23. " GSB631 ,Group Status Bit 631" "Group 0,Group 1" textline " " bitfld.long 0x00 22. " GSB630 ,Group Status Bit 630" "Group 0,Group 1" bitfld.long 0x00 21. " GSB629 ,Group Status Bit 629" "Group 0,Group 1" bitfld.long 0x00 20. " GSB628 ,Group Status Bit 628" "Group 0,Group 1" textline " " bitfld.long 0x00 19. " GSB627 ,Group Status Bit 627" "Group 0,Group 1" bitfld.long 0x00 18. " GSB626 ,Group Status Bit 626" "Group 0,Group 1" bitfld.long 0x00 17. " GSB625 ,Group Status Bit 625" "Group 0,Group 1" textline " " bitfld.long 0x00 16. " GSB624 ,Group Status Bit 624" "Group 0,Group 1" bitfld.long 0x00 15. " GSB623 ,Group Status Bit 623" "Group 0,Group 1" bitfld.long 0x00 14. " GSB622 ,Group Status Bit 622" "Group 0,Group 1" textline " " bitfld.long 0x00 13. " GSB621 ,Group Status Bit 621" "Group 0,Group 1" bitfld.long 0x00 12. " GSB620 ,Group Status Bit 620" "Group 0,Group 1" bitfld.long 0x00 11. " GSB619 ,Group Status Bit 619" "Group 0,Group 1" textline " " bitfld.long 0x00 10. " GSB618 ,Group Status Bit 618" "Group 0,Group 1" bitfld.long 0x00 9. " GSB617 ,Group Status Bit 617" "Group 0,Group 1" bitfld.long 0x00 8. " GSB616 ,Group Status Bit 616" "Group 0,Group 1" textline " " bitfld.long 0x00 7. " GSB615 ,Group Status Bit 615" "Group 0,Group 1" bitfld.long 0x00 6. " GSB614 ,Group Status Bit 614" "Group 0,Group 1" bitfld.long 0x00 5. " GSB613 ,Group Status Bit 613" "Group 0,Group 1" textline " " bitfld.long 0x00 4. " GSB612 ,Group Status Bit 612" "Group 0,Group 1" bitfld.long 0x00 3. " GSB611 ,Group Status Bit 611" "Group 0,Group 1" bitfld.long 0x00 2. " GSB610 ,Group Status Bit 610" "Group 0,Group 1" textline " " bitfld.long 0x00 1. " GSB609 ,Group Status Bit 609" "Group 0,Group 1" bitfld.long 0x00 0. " GSB608 ,Group Status Bit 608" "Group 0,Group 1" else rgroup.long 0x00CC++0x03 line.long 0x0 "GICD_IGROUPR19,Interrupt Group Register 19" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(ad:(per.long(spr:0x31F30)&0xFFFC0000)+0x04))&0x0000001F)>=0x14)&&(PER.ADDRESS.isSECUREEX(ad:(per.long(spr:0x31F30)&0xFFFC0000)+0x00D0)) group.long 0x00D0++0x03 line.long 0x0 "GICD_IGROUPR20,Interrupt Group Register 20 (Secure access)" bitfld.long 0x00 31. " GSB671 ,Group Status Bit 671" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 30. " GSB670 ,Group Status Bit 670" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 29. " GSB669 ,Group Status Bit 669" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 28. " GSB668 ,Group Status Bit 668" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 27. " GSB667 ,Group Status Bit 667" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 26. " GSB666 ,Group Status Bit 666" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 25. " GSB665 ,Group Status Bit 665" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 24. " GSB664 ,Group Status Bit 664" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 23. " GSB663 ,Group Status Bit 663" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 22. " GSB662 ,Group Status Bit 662" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 21. " GSB661 ,Group Status Bit 661" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 20. " GSB660 ,Group Status Bit 660" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 19. " GSB659 ,Group Status Bit 659" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 18. " GSB658 ,Group Status Bit 658" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 17. " GSB657 ,Group Status Bit 657" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 16. " GSB656 ,Group Status Bit 656" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 15. " GSB655 ,Group Status Bit 655" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 14. " GSB654 ,Group Status Bit 654" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 13. " GSB653 ,Group Status Bit 653" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 12. " GSB652 ,Group Status Bit 652" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 11. " GSB651 ,Group Status Bit 651" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 10. " GSB650 ,Group Status Bit 650" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 9. " GSB649 ,Group Status Bit 649" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 8. " GSB648 ,Group Status Bit 648" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 7. " GSB647 ,Group Status Bit 647" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 6. " GSB646 ,Group Status Bit 646" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 5. " GSB645 ,Group Status Bit 645" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 4. " GSB644 ,Group Status Bit 644" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 3. " GSB643 ,Group Status Bit 643" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 2. " GSB642 ,Group Status Bit 642" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 1. " GSB641 ,Group Status Bit 641" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 0. " GSB640 ,Group Status Bit 640" "Group 0 (Secure),Group 1 (Non-secure)" elif (((per.l(ad:(per.long(spr:0x31F30)&0xFFFC0000)+0x04))&0x0000001F)>=0x14) group.long 0x00D0++0x03 line.long 0x0 "GICD_IGROUPR20,Interrupt Group Register 20 (Non-secure access)" bitfld.long 0x00 31. " GSB671 ,Group Status Bit 671" "Group 0,Group 1" bitfld.long 0x00 30. " GSB670 ,Group Status Bit 670" "Group 0,Group 1" bitfld.long 0x00 29. " GSB669 ,Group Status Bit 669" "Group 0,Group 1" textline " " bitfld.long 0x00 28. " GSB668 ,Group Status Bit 668" "Group 0,Group 1" bitfld.long 0x00 27. " GSB667 ,Group Status Bit 667" "Group 0,Group 1" bitfld.long 0x00 26. " GSB666 ,Group Status Bit 666" "Group 0,Group 1" textline " " bitfld.long 0x00 25. " GSB665 ,Group Status Bit 665" "Group 0,Group 1" bitfld.long 0x00 24. " GSB664 ,Group Status Bit 664" "Group 0,Group 1" bitfld.long 0x00 23. " GSB663 ,Group Status Bit 663" "Group 0,Group 1" textline " " bitfld.long 0x00 22. " GSB662 ,Group Status Bit 662" "Group 0,Group 1" bitfld.long 0x00 21. " GSB661 ,Group Status Bit 661" "Group 0,Group 1" bitfld.long 0x00 20. " GSB660 ,Group Status Bit 660" "Group 0,Group 1" textline " " bitfld.long 0x00 19. " GSB659 ,Group Status Bit 659" "Group 0,Group 1" bitfld.long 0x00 18. " GSB658 ,Group Status Bit 658" "Group 0,Group 1" bitfld.long 0x00 17. " GSB657 ,Group Status Bit 657" "Group 0,Group 1" textline " " bitfld.long 0x00 16. " GSB656 ,Group Status Bit 656" "Group 0,Group 1" bitfld.long 0x00 15. " GSB655 ,Group Status Bit 655" "Group 0,Group 1" bitfld.long 0x00 14. " GSB654 ,Group Status Bit 654" "Group 0,Group 1" textline " " bitfld.long 0x00 13. " GSB653 ,Group Status Bit 653" "Group 0,Group 1" bitfld.long 0x00 12. " GSB652 ,Group Status Bit 652" "Group 0,Group 1" bitfld.long 0x00 11. " GSB651 ,Group Status Bit 651" "Group 0,Group 1" textline " " bitfld.long 0x00 10. " GSB650 ,Group Status Bit 650" "Group 0,Group 1" bitfld.long 0x00 9. " GSB649 ,Group Status Bit 649" "Group 0,Group 1" bitfld.long 0x00 8. " GSB648 ,Group Status Bit 648" "Group 0,Group 1" textline " " bitfld.long 0x00 7. " GSB647 ,Group Status Bit 647" "Group 0,Group 1" bitfld.long 0x00 6. " GSB646 ,Group Status Bit 646" "Group 0,Group 1" bitfld.long 0x00 5. " GSB645 ,Group Status Bit 645" "Group 0,Group 1" textline " " bitfld.long 0x00 4. " GSB644 ,Group Status Bit 644" "Group 0,Group 1" bitfld.long 0x00 3. " GSB643 ,Group Status Bit 643" "Group 0,Group 1" bitfld.long 0x00 2. " GSB642 ,Group Status Bit 642" "Group 0,Group 1" textline " " bitfld.long 0x00 1. " GSB641 ,Group Status Bit 641" "Group 0,Group 1" bitfld.long 0x00 0. " GSB640 ,Group Status Bit 640" "Group 0,Group 1" else rgroup.long 0x00D0++0x03 line.long 0x0 "GICD_IGROUPR20,Interrupt Group Register 20" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(ad:(per.long(spr:0x31F30)&0xFFFC0000)+0x04))&0x0000001F)>=0x15)&&(PER.ADDRESS.isSECUREEX(ad:(per.long(spr:0x31F30)&0xFFFC0000)+0x00D4)) group.long 0x00D4++0x03 line.long 0x0 "GICD_IGROUPR21,Interrupt Group Register 21 (Secure access)" bitfld.long 0x00 31. " GSB703 ,Group Status Bit 703" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 30. " GSB702 ,Group Status Bit 702" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 29. " GSB701 ,Group Status Bit 701" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 28. " GSB700 ,Group Status Bit 700" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 27. " GSB699 ,Group Status Bit 699" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 26. " GSB698 ,Group Status Bit 698" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 25. " GSB697 ,Group Status Bit 697" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 24. " GSB696 ,Group Status Bit 696" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 23. " GSB695 ,Group Status Bit 695" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 22. " GSB694 ,Group Status Bit 694" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 21. " GSB693 ,Group Status Bit 693" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 20. " GSB692 ,Group Status Bit 692" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 19. " GSB691 ,Group Status Bit 691" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 18. " GSB690 ,Group Status Bit 690" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 17. " GSB689 ,Group Status Bit 689" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 16. " GSB688 ,Group Status Bit 688" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 15. " GSB687 ,Group Status Bit 687" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 14. " GSB686 ,Group Status Bit 686" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 13. " GSB685 ,Group Status Bit 685" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 12. " GSB684 ,Group Status Bit 684" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 11. " GSB683 ,Group Status Bit 683" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 10. " GSB682 ,Group Status Bit 682" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 9. " GSB681 ,Group Status Bit 681" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 8. " GSB680 ,Group Status Bit 680" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 7. " GSB679 ,Group Status Bit 679" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 6. " GSB678 ,Group Status Bit 678" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 5. " GSB677 ,Group Status Bit 677" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 4. " GSB676 ,Group Status Bit 676" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 3. " GSB675 ,Group Status Bit 675" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 2. " GSB674 ,Group Status Bit 674" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 1. " GSB673 ,Group Status Bit 673" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 0. " GSB672 ,Group Status Bit 672" "Group 0 (Secure),Group 1 (Non-secure)" elif (((per.l(ad:(per.long(spr:0x31F30)&0xFFFC0000)+0x04))&0x0000001F)>=0x15) group.long 0x00D4++0x03 line.long 0x0 "GICD_IGROUPR21,Interrupt Group Register 21 (Non-secure access)" bitfld.long 0x00 31. " GSB703 ,Group Status Bit 703" "Group 0,Group 1" bitfld.long 0x00 30. " GSB702 ,Group Status Bit 702" "Group 0,Group 1" bitfld.long 0x00 29. " GSB701 ,Group Status Bit 701" "Group 0,Group 1" textline " " bitfld.long 0x00 28. " GSB700 ,Group Status Bit 700" "Group 0,Group 1" bitfld.long 0x00 27. " GSB699 ,Group Status Bit 699" "Group 0,Group 1" bitfld.long 0x00 26. " GSB698 ,Group Status Bit 698" "Group 0,Group 1" textline " " bitfld.long 0x00 25. " GSB697 ,Group Status Bit 697" "Group 0,Group 1" bitfld.long 0x00 24. " GSB696 ,Group Status Bit 696" "Group 0,Group 1" bitfld.long 0x00 23. " GSB695 ,Group Status Bit 695" "Group 0,Group 1" textline " " bitfld.long 0x00 22. " GSB694 ,Group Status Bit 694" "Group 0,Group 1" bitfld.long 0x00 21. " GSB693 ,Group Status Bit 693" "Group 0,Group 1" bitfld.long 0x00 20. " GSB692 ,Group Status Bit 692" "Group 0,Group 1" textline " " bitfld.long 0x00 19. " GSB691 ,Group Status Bit 691" "Group 0,Group 1" bitfld.long 0x00 18. " GSB690 ,Group Status Bit 690" "Group 0,Group 1" bitfld.long 0x00 17. " GSB689 ,Group Status Bit 689" "Group 0,Group 1" textline " " bitfld.long 0x00 16. " GSB688 ,Group Status Bit 688" "Group 0,Group 1" bitfld.long 0x00 15. " GSB687 ,Group Status Bit 687" "Group 0,Group 1" bitfld.long 0x00 14. " GSB686 ,Group Status Bit 686" "Group 0,Group 1" textline " " bitfld.long 0x00 13. " GSB685 ,Group Status Bit 685" "Group 0,Group 1" bitfld.long 0x00 12. " GSB684 ,Group Status Bit 684" "Group 0,Group 1" bitfld.long 0x00 11. " GSB683 ,Group Status Bit 683" "Group 0,Group 1" textline " " bitfld.long 0x00 10. " GSB682 ,Group Status Bit 682" "Group 0,Group 1" bitfld.long 0x00 9. " GSB681 ,Group Status Bit 681" "Group 0,Group 1" bitfld.long 0x00 8. " GSB680 ,Group Status Bit 680" "Group 0,Group 1" textline " " bitfld.long 0x00 7. " GSB679 ,Group Status Bit 679" "Group 0,Group 1" bitfld.long 0x00 6. " GSB678 ,Group Status Bit 678" "Group 0,Group 1" bitfld.long 0x00 5. " GSB677 ,Group Status Bit 677" "Group 0,Group 1" textline " " bitfld.long 0x00 4. " GSB676 ,Group Status Bit 676" "Group 0,Group 1" bitfld.long 0x00 3. " GSB675 ,Group Status Bit 675" "Group 0,Group 1" bitfld.long 0x00 2. " GSB674 ,Group Status Bit 674" "Group 0,Group 1" textline " " bitfld.long 0x00 1. " GSB673 ,Group Status Bit 673" "Group 0,Group 1" bitfld.long 0x00 0. " GSB672 ,Group Status Bit 672" "Group 0,Group 1" else rgroup.long 0x00D4++0x03 line.long 0x0 "GICD_IGROUPR21,Interrupt Group Register 21" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(ad:(per.long(spr:0x31F30)&0xFFFC0000)+0x04))&0x0000001F)>=0x16)&&(PER.ADDRESS.isSECUREEX(ad:(per.long(spr:0x31F30)&0xFFFC0000)+0x00D8)) group.long 0x00D8++0x03 line.long 0x0 "GICD_IGROUPR22,Interrupt Group Register 22 (Secure access)" bitfld.long 0x00 31. " GSB735 ,Group Status Bit 735" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 30. " GSB734 ,Group Status Bit 734" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 29. " GSB733 ,Group Status Bit 733" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 28. " GSB732 ,Group Status Bit 732" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 27. " GSB731 ,Group Status Bit 731" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 26. " GSB730 ,Group Status Bit 730" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 25. " GSB729 ,Group Status Bit 729" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 24. " GSB728 ,Group Status Bit 728" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 23. " GSB727 ,Group Status Bit 727" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 22. " GSB726 ,Group Status Bit 726" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 21. " GSB725 ,Group Status Bit 725" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 20. " GSB724 ,Group Status Bit 724" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 19. " GSB723 ,Group Status Bit 723" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 18. " GSB722 ,Group Status Bit 722" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 17. " GSB721 ,Group Status Bit 721" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 16. " GSB720 ,Group Status Bit 720" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 15. " GSB719 ,Group Status Bit 719" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 14. " GSB718 ,Group Status Bit 718" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 13. " GSB717 ,Group Status Bit 717" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 12. " GSB716 ,Group Status Bit 716" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 11. " GSB715 ,Group Status Bit 715" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 10. " GSB714 ,Group Status Bit 714" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 9. " GSB713 ,Group Status Bit 713" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 8. " GSB712 ,Group Status Bit 712" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 7. " GSB711 ,Group Status Bit 711" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 6. " GSB710 ,Group Status Bit 710" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 5. " GSB709 ,Group Status Bit 709" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 4. " GSB708 ,Group Status Bit 708" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 3. " GSB707 ,Group Status Bit 707" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 2. " GSB706 ,Group Status Bit 706" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 1. " GSB705 ,Group Status Bit 705" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 0. " GSB704 ,Group Status Bit 704" "Group 0 (Secure),Group 1 (Non-secure)" elif (((per.l(ad:(per.long(spr:0x31F30)&0xFFFC0000)+0x04))&0x0000001F)>=0x16) group.long 0x00D8++0x03 line.long 0x0 "GICD_IGROUPR22,Interrupt Group Register 22 (Non-secure access)" bitfld.long 0x00 31. " GSB735 ,Group Status Bit 735" "Group 0,Group 1" bitfld.long 0x00 30. " GSB734 ,Group Status Bit 734" "Group 0,Group 1" bitfld.long 0x00 29. " GSB733 ,Group Status Bit 733" "Group 0,Group 1" textline " " bitfld.long 0x00 28. " GSB732 ,Group Status Bit 732" "Group 0,Group 1" bitfld.long 0x00 27. " GSB731 ,Group Status Bit 731" "Group 0,Group 1" bitfld.long 0x00 26. " GSB730 ,Group Status Bit 730" "Group 0,Group 1" textline " " bitfld.long 0x00 25. " GSB729 ,Group Status Bit 729" "Group 0,Group 1" bitfld.long 0x00 24. " GSB728 ,Group Status Bit 728" "Group 0,Group 1" bitfld.long 0x00 23. " GSB727 ,Group Status Bit 727" "Group 0,Group 1" textline " " bitfld.long 0x00 22. " GSB726 ,Group Status Bit 726" "Group 0,Group 1" bitfld.long 0x00 21. " GSB725 ,Group Status Bit 725" "Group 0,Group 1" bitfld.long 0x00 20. " GSB724 ,Group Status Bit 724" "Group 0,Group 1" textline " " bitfld.long 0x00 19. " GSB723 ,Group Status Bit 723" "Group 0,Group 1" bitfld.long 0x00 18. " GSB722 ,Group Status Bit 722" "Group 0,Group 1" bitfld.long 0x00 17. " GSB721 ,Group Status Bit 721" "Group 0,Group 1" textline " " bitfld.long 0x00 16. " GSB720 ,Group Status Bit 720" "Group 0,Group 1" bitfld.long 0x00 15. " GSB719 ,Group Status Bit 719" "Group 0,Group 1" bitfld.long 0x00 14. " GSB718 ,Group Status Bit 718" "Group 0,Group 1" textline " " bitfld.long 0x00 13. " GSB717 ,Group Status Bit 717" "Group 0,Group 1" bitfld.long 0x00 12. " GSB716 ,Group Status Bit 716" "Group 0,Group 1" bitfld.long 0x00 11. " GSB715 ,Group Status Bit 715" "Group 0,Group 1" textline " " bitfld.long 0x00 10. " GSB714 ,Group Status Bit 714" "Group 0,Group 1" bitfld.long 0x00 9. " GSB713 ,Group Status Bit 713" "Group 0,Group 1" bitfld.long 0x00 8. " GSB712 ,Group Status Bit 712" "Group 0,Group 1" textline " " bitfld.long 0x00 7. " GSB711 ,Group Status Bit 711" "Group 0,Group 1" bitfld.long 0x00 6. " GSB710 ,Group Status Bit 710" "Group 0,Group 1" bitfld.long 0x00 5. " GSB709 ,Group Status Bit 709" "Group 0,Group 1" textline " " bitfld.long 0x00 4. " GSB708 ,Group Status Bit 708" "Group 0,Group 1" bitfld.long 0x00 3. " GSB707 ,Group Status Bit 707" "Group 0,Group 1" bitfld.long 0x00 2. " GSB706 ,Group Status Bit 706" "Group 0,Group 1" textline " " bitfld.long 0x00 1. " GSB705 ,Group Status Bit 705" "Group 0,Group 1" bitfld.long 0x00 0. " GSB704 ,Group Status Bit 704" "Group 0,Group 1" else rgroup.long 0x00D8++0x03 line.long 0x0 "GICD_IGROUPR22,Interrupt Group Register 22" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(ad:(per.long(spr:0x31F30)&0xFFFC0000)+0x04))&0x0000001F)>=0x17)&&(PER.ADDRESS.isSECUREEX(ad:(per.long(spr:0x31F30)&0xFFFC0000)+0x00DC)) group.long 0x00DC++0x03 line.long 0x0 "GICD_IGROUPR23,Interrupt Group Register 23 (Secure access)" bitfld.long 0x00 31. " GSB767 ,Group Status Bit 767" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 30. " GSB766 ,Group Status Bit 766" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 29. " GSB765 ,Group Status Bit 765" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 28. " GSB764 ,Group Status Bit 764" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 27. " GSB763 ,Group Status Bit 763" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 26. " GSB762 ,Group Status Bit 762" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 25. " GSB761 ,Group Status Bit 761" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 24. " GSB760 ,Group Status Bit 760" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 23. " GSB759 ,Group Status Bit 759" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 22. " GSB758 ,Group Status Bit 758" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 21. " GSB757 ,Group Status Bit 757" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 20. " GSB756 ,Group Status Bit 756" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 19. " GSB755 ,Group Status Bit 755" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 18. " GSB754 ,Group Status Bit 754" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 17. " GSB753 ,Group Status Bit 753" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 16. " GSB752 ,Group Status Bit 752" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 15. " GSB751 ,Group Status Bit 751" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 14. " GSB750 ,Group Status Bit 750" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 13. " GSB749 ,Group Status Bit 749" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 12. " GSB748 ,Group Status Bit 748" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 11. " GSB747 ,Group Status Bit 747" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 10. " GSB746 ,Group Status Bit 746" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 9. " GSB745 ,Group Status Bit 745" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 8. " GSB744 ,Group Status Bit 744" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 7. " GSB743 ,Group Status Bit 743" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 6. " GSB742 ,Group Status Bit 742" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 5. " GSB741 ,Group Status Bit 741" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 4. " GSB740 ,Group Status Bit 740" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 3. " GSB739 ,Group Status Bit 739" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 2. " GSB738 ,Group Status Bit 738" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 1. " GSB737 ,Group Status Bit 737" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 0. " GSB736 ,Group Status Bit 736" "Group 0 (Secure),Group 1 (Non-secure)" elif (((per.l(ad:(per.long(spr:0x31F30)&0xFFFC0000)+0x04))&0x0000001F)>=0x17) group.long 0x00DC++0x03 line.long 0x0 "GICD_IGROUPR23,Interrupt Group Register 23 (Non-secure access)" bitfld.long 0x00 31. " GSB767 ,Group Status Bit 767" "Group 0,Group 1" bitfld.long 0x00 30. " GSB766 ,Group Status Bit 766" "Group 0,Group 1" bitfld.long 0x00 29. " GSB765 ,Group Status Bit 765" "Group 0,Group 1" textline " " bitfld.long 0x00 28. " GSB764 ,Group Status Bit 764" "Group 0,Group 1" bitfld.long 0x00 27. " GSB763 ,Group Status Bit 763" "Group 0,Group 1" bitfld.long 0x00 26. " GSB762 ,Group Status Bit 762" "Group 0,Group 1" textline " " bitfld.long 0x00 25. " GSB761 ,Group Status Bit 761" "Group 0,Group 1" bitfld.long 0x00 24. " GSB760 ,Group Status Bit 760" "Group 0,Group 1" bitfld.long 0x00 23. " GSB759 ,Group Status Bit 759" "Group 0,Group 1" textline " " bitfld.long 0x00 22. " GSB758 ,Group Status Bit 758" "Group 0,Group 1" bitfld.long 0x00 21. " GSB757 ,Group Status Bit 757" "Group 0,Group 1" bitfld.long 0x00 20. " GSB756 ,Group Status Bit 756" "Group 0,Group 1" textline " " bitfld.long 0x00 19. " GSB755 ,Group Status Bit 755" "Group 0,Group 1" bitfld.long 0x00 18. " GSB754 ,Group Status Bit 754" "Group 0,Group 1" bitfld.long 0x00 17. " GSB753 ,Group Status Bit 753" "Group 0,Group 1" textline " " bitfld.long 0x00 16. " GSB752 ,Group Status Bit 752" "Group 0,Group 1" bitfld.long 0x00 15. " GSB751 ,Group Status Bit 751" "Group 0,Group 1" bitfld.long 0x00 14. " GSB750 ,Group Status Bit 750" "Group 0,Group 1" textline " " bitfld.long 0x00 13. " GSB749 ,Group Status Bit 749" "Group 0,Group 1" bitfld.long 0x00 12. " GSB748 ,Group Status Bit 748" "Group 0,Group 1" bitfld.long 0x00 11. " GSB747 ,Group Status Bit 747" "Group 0,Group 1" textline " " bitfld.long 0x00 10. " GSB746 ,Group Status Bit 746" "Group 0,Group 1" bitfld.long 0x00 9. " GSB745 ,Group Status Bit 745" "Group 0,Group 1" bitfld.long 0x00 8. " GSB744 ,Group Status Bit 744" "Group 0,Group 1" textline " " bitfld.long 0x00 7. " GSB743 ,Group Status Bit 743" "Group 0,Group 1" bitfld.long 0x00 6. " GSB742 ,Group Status Bit 742" "Group 0,Group 1" bitfld.long 0x00 5. " GSB741 ,Group Status Bit 741" "Group 0,Group 1" textline " " bitfld.long 0x00 4. " GSB740 ,Group Status Bit 740" "Group 0,Group 1" bitfld.long 0x00 3. " GSB739 ,Group Status Bit 739" "Group 0,Group 1" bitfld.long 0x00 2. " GSB738 ,Group Status Bit 738" "Group 0,Group 1" textline " " bitfld.long 0x00 1. " GSB737 ,Group Status Bit 737" "Group 0,Group 1" bitfld.long 0x00 0. " GSB736 ,Group Status Bit 736" "Group 0,Group 1" else rgroup.long 0x00DC++0x03 line.long 0x0 "GICD_IGROUPR23,Interrupt Group Register 23" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(ad:(per.long(spr:0x31F30)&0xFFFC0000)+0x04))&0x0000001F)>=0x18)&&(PER.ADDRESS.isSECUREEX(ad:(per.long(spr:0x31F30)&0xFFFC0000)+0x00E0)) group.long 0x00E0++0x03 line.long 0x0 "GICD_IGROUPR24,Interrupt Group Register 24 (Secure access)" bitfld.long 0x00 31. " GSB799 ,Group Status Bit 799" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 30. " GSB798 ,Group Status Bit 798" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 29. " GSB797 ,Group Status Bit 797" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 28. " GSB796 ,Group Status Bit 796" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 27. " GSB795 ,Group Status Bit 795" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 26. " GSB794 ,Group Status Bit 794" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 25. " GSB793 ,Group Status Bit 793" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 24. " GSB792 ,Group Status Bit 792" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 23. " GSB791 ,Group Status Bit 791" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 22. " GSB790 ,Group Status Bit 790" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 21. " GSB789 ,Group Status Bit 789" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 20. " GSB788 ,Group Status Bit 788" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 19. " GSB787 ,Group Status Bit 787" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 18. " GSB786 ,Group Status Bit 786" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 17. " GSB785 ,Group Status Bit 785" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 16. " GSB784 ,Group Status Bit 784" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 15. " GSB783 ,Group Status Bit 783" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 14. " GSB782 ,Group Status Bit 782" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 13. " GSB781 ,Group Status Bit 781" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 12. " GSB780 ,Group Status Bit 780" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 11. " GSB779 ,Group Status Bit 779" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 10. " GSB778 ,Group Status Bit 778" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 9. " GSB777 ,Group Status Bit 777" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 8. " GSB776 ,Group Status Bit 776" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 7. " GSB775 ,Group Status Bit 775" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 6. " GSB774 ,Group Status Bit 774" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 5. " GSB773 ,Group Status Bit 773" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 4. " GSB772 ,Group Status Bit 772" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 3. " GSB771 ,Group Status Bit 771" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 2. " GSB770 ,Group Status Bit 770" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 1. " GSB769 ,Group Status Bit 769" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 0. " GSB768 ,Group Status Bit 768" "Group 0 (Secure),Group 1 (Non-secure)" elif (((per.l(ad:(per.long(spr:0x31F30)&0xFFFC0000)+0x04))&0x0000001F)>=0x18) group.long 0x00E0++0x03 line.long 0x0 "GICD_IGROUPR24,Interrupt Group Register 24 (Non-secure access)" bitfld.long 0x00 31. " GSB799 ,Group Status Bit 799" "Group 0,Group 1" bitfld.long 0x00 30. " GSB798 ,Group Status Bit 798" "Group 0,Group 1" bitfld.long 0x00 29. " GSB797 ,Group Status Bit 797" "Group 0,Group 1" textline " " bitfld.long 0x00 28. " GSB796 ,Group Status Bit 796" "Group 0,Group 1" bitfld.long 0x00 27. " GSB795 ,Group Status Bit 795" "Group 0,Group 1" bitfld.long 0x00 26. " GSB794 ,Group Status Bit 794" "Group 0,Group 1" textline " " bitfld.long 0x00 25. " GSB793 ,Group Status Bit 793" "Group 0,Group 1" bitfld.long 0x00 24. " GSB792 ,Group Status Bit 792" "Group 0,Group 1" bitfld.long 0x00 23. " GSB791 ,Group Status Bit 791" "Group 0,Group 1" textline " " bitfld.long 0x00 22. " GSB790 ,Group Status Bit 790" "Group 0,Group 1" bitfld.long 0x00 21. " GSB789 ,Group Status Bit 789" "Group 0,Group 1" bitfld.long 0x00 20. " GSB788 ,Group Status Bit 788" "Group 0,Group 1" textline " " bitfld.long 0x00 19. " GSB787 ,Group Status Bit 787" "Group 0,Group 1" bitfld.long 0x00 18. " GSB786 ,Group Status Bit 786" "Group 0,Group 1" bitfld.long 0x00 17. " GSB785 ,Group Status Bit 785" "Group 0,Group 1" textline " " bitfld.long 0x00 16. " GSB784 ,Group Status Bit 784" "Group 0,Group 1" bitfld.long 0x00 15. " GSB783 ,Group Status Bit 783" "Group 0,Group 1" bitfld.long 0x00 14. " GSB782 ,Group Status Bit 782" "Group 0,Group 1" textline " " bitfld.long 0x00 13. " GSB781 ,Group Status Bit 781" "Group 0,Group 1" bitfld.long 0x00 12. " GSB780 ,Group Status Bit 780" "Group 0,Group 1" bitfld.long 0x00 11. " GSB779 ,Group Status Bit 779" "Group 0,Group 1" textline " " bitfld.long 0x00 10. " GSB778 ,Group Status Bit 778" "Group 0,Group 1" bitfld.long 0x00 9. " GSB777 ,Group Status Bit 777" "Group 0,Group 1" bitfld.long 0x00 8. " GSB776 ,Group Status Bit 776" "Group 0,Group 1" textline " " bitfld.long 0x00 7. " GSB775 ,Group Status Bit 775" "Group 0,Group 1" bitfld.long 0x00 6. " GSB774 ,Group Status Bit 774" "Group 0,Group 1" bitfld.long 0x00 5. " GSB773 ,Group Status Bit 773" "Group 0,Group 1" textline " " bitfld.long 0x00 4. " GSB772 ,Group Status Bit 772" "Group 0,Group 1" bitfld.long 0x00 3. " GSB771 ,Group Status Bit 771" "Group 0,Group 1" bitfld.long 0x00 2. " GSB770 ,Group Status Bit 770" "Group 0,Group 1" textline " " bitfld.long 0x00 1. " GSB769 ,Group Status Bit 769" "Group 0,Group 1" bitfld.long 0x00 0. " GSB768 ,Group Status Bit 768" "Group 0,Group 1" else rgroup.long 0x0E0++0x03 line.long 0x0 "GICD_IGROUPR24,Interrupt Group Register 24" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(ad:(per.long(spr:0x31F30)&0xFFFC0000)+0x04))&0x0000001F)>=0x19)&&(PER.ADDRESS.isSECUREEX(ad:(per.long(spr:0x31F30)&0xFFFC0000)+0x00E4)) group.long 0x00E4++0x03 line.long 0x0 "GICD_IGROUPR25,Interrupt Group Register 25 (Secure access)" bitfld.long 0x00 31. " GSB831 ,Group Status Bit 831" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 30. " GSB830 ,Group Status Bit 830" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 29. " GSB829 ,Group Status Bit 829" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 28. " GSB828 ,Group Status Bit 828" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 27. " GSB827 ,Group Status Bit 827" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 26. " GSB826 ,Group Status Bit 826" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 25. " GSB825 ,Group Status Bit 825" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 24. " GSB824 ,Group Status Bit 824" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 23. " GSB823 ,Group Status Bit 823" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 22. " GSB822 ,Group Status Bit 822" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 21. " GSB821 ,Group Status Bit 821" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 20. " GSB820 ,Group Status Bit 820" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 19. " GSB819 ,Group Status Bit 819" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 18. " GSB818 ,Group Status Bit 818" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 17. " GSB817 ,Group Status Bit 817" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 16. " GSB816 ,Group Status Bit 816" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 15. " GSB815 ,Group Status Bit 815" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 14. " GSB814 ,Group Status Bit 814" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 13. " GSB813 ,Group Status Bit 813" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 12. " GSB812 ,Group Status Bit 812" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 11. " GSB811 ,Group Status Bit 811" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 10. " GSB810 ,Group Status Bit 810" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 9. " GSB809 ,Group Status Bit 809" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 8. " GSB808 ,Group Status Bit 808" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 7. " GSB807 ,Group Status Bit 807" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 6. " GSB806 ,Group Status Bit 806" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 5. " GSB805 ,Group Status Bit 805" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 4. " GSB804 ,Group Status Bit 804" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 3. " GSB803 ,Group Status Bit 803" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 2. " GSB802 ,Group Status Bit 802" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 1. " GSB801 ,Group Status Bit 801" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 0. " GSB800 ,Group Status Bit 800" "Group 0 (Secure),Group 1 (Non-secure)" elif (((per.l(ad:(per.long(spr:0x31F30)&0xFFFC0000)+0x04))&0x0000001F)>=0x19) group.long 0x00E4++0x03 line.long 0x0 "GICD_IGROUPR25,Interrupt Group Register 25 (Non-secure access)" bitfld.long 0x00 31. " GSB831 ,Group Status Bit 831" "Group 0,Group 1" bitfld.long 0x00 30. " GSB830 ,Group Status Bit 830" "Group 0,Group 1" bitfld.long 0x00 29. " GSB829 ,Group Status Bit 829" "Group 0,Group 1" textline " " bitfld.long 0x00 28. " GSB828 ,Group Status Bit 828" "Group 0,Group 1" bitfld.long 0x00 27. " GSB827 ,Group Status Bit 827" "Group 0,Group 1" bitfld.long 0x00 26. " GSB826 ,Group Status Bit 826" "Group 0,Group 1" textline " " bitfld.long 0x00 25. " GSB825 ,Group Status Bit 825" "Group 0,Group 1" bitfld.long 0x00 24. " GSB824 ,Group Status Bit 824" "Group 0,Group 1" bitfld.long 0x00 23. " GSB823 ,Group Status Bit 823" "Group 0,Group 1" textline " " bitfld.long 0x00 22. " GSB822 ,Group Status Bit 822" "Group 0,Group 1" bitfld.long 0x00 21. " GSB821 ,Group Status Bit 821" "Group 0,Group 1" bitfld.long 0x00 20. " GSB820 ,Group Status Bit 820" "Group 0,Group 1" textline " " bitfld.long 0x00 19. " GSB819 ,Group Status Bit 819" "Group 0,Group 1" bitfld.long 0x00 18. " GSB818 ,Group Status Bit 818" "Group 0,Group 1" bitfld.long 0x00 17. " GSB817 ,Group Status Bit 817" "Group 0,Group 1" textline " " bitfld.long 0x00 16. " GSB816 ,Group Status Bit 816" "Group 0,Group 1" bitfld.long 0x00 15. " GSB815 ,Group Status Bit 815" "Group 0,Group 1" bitfld.long 0x00 14. " GSB814 ,Group Status Bit 814" "Group 0,Group 1" textline " " bitfld.long 0x00 13. " GSB813 ,Group Status Bit 813" "Group 0,Group 1" bitfld.long 0x00 12. " GSB812 ,Group Status Bit 812" "Group 0,Group 1" bitfld.long 0x00 11. " GSB811 ,Group Status Bit 811" "Group 0,Group 1" textline " " bitfld.long 0x00 10. " GSB810 ,Group Status Bit 810" "Group 0,Group 1" bitfld.long 0x00 9. " GSB809 ,Group Status Bit 809" "Group 0,Group 1" bitfld.long 0x00 8. " GSB808 ,Group Status Bit 808" "Group 0,Group 1" textline " " bitfld.long 0x00 7. " GSB807 ,Group Status Bit 807" "Group 0,Group 1" bitfld.long 0x00 6. " GSB806 ,Group Status Bit 806" "Group 0,Group 1" bitfld.long 0x00 5. " GSB805 ,Group Status Bit 805" "Group 0,Group 1" textline " " bitfld.long 0x00 4. " GSB804 ,Group Status Bit 804" "Group 0,Group 1" bitfld.long 0x00 3. " GSB803 ,Group Status Bit 803" "Group 0,Group 1" bitfld.long 0x00 2. " GSB802 ,Group Status Bit 802" "Group 0,Group 1" textline " " bitfld.long 0x00 1. " GSB801 ,Group Status Bit 801" "Group 0,Group 1" bitfld.long 0x00 0. " GSB800 ,Group Status Bit 800" "Group 0,Group 1" else rgroup.long 0x00E4++0x03 line.long 0x0 "GICD_IGROUPR25,Interrupt Group Register 25" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(ad:(per.long(spr:0x31F30)&0xFFFC0000)+0x04))&0x0000001F)>=0x1A)&&(PER.ADDRESS.isSECUREEX(ad:(per.long(spr:0x31F30)&0xFFFC0000)+0x00E8)) group.long 0x00E8++0x03 line.long 0x0 "GICD_IGROUPR26,Interrupt Group Register 26 (Secure access)" bitfld.long 0x00 31. " GSB863 ,Group Status Bit 863" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 30. " GSB862 ,Group Status Bit 862" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 29. " GSB861 ,Group Status Bit 861" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 28. " GSB860 ,Group Status Bit 860" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 27. " GSB859 ,Group Status Bit 859" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 26. " GSB858 ,Group Status Bit 858" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 25. " GSB857 ,Group Status Bit 857" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 24. " GSB856 ,Group Status Bit 856" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 23. " GSB855 ,Group Status Bit 855" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 22. " GSB854 ,Group Status Bit 854" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 21. " GSB853 ,Group Status Bit 853" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 20. " GSB852 ,Group Status Bit 852" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 19. " GSB851 ,Group Status Bit 851" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 18. " GSB850 ,Group Status Bit 850" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 17. " GSB849 ,Group Status Bit 849" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 16. " GSB848 ,Group Status Bit 848" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 15. " GSB847 ,Group Status Bit 847" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 14. " GSB846 ,Group Status Bit 846" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 13. " GSB845 ,Group Status Bit 845" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 12. " GSB844 ,Group Status Bit 844" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 11. " GSB843 ,Group Status Bit 843" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 10. " GSB842 ,Group Status Bit 842" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 9. " GSB841 ,Group Status Bit 841" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 8. " GSB840 ,Group Status Bit 840" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 7. " GSB839 ,Group Status Bit 839" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 6. " GSB838 ,Group Status Bit 838" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 5. " GSB837 ,Group Status Bit 837" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 4. " GSB836 ,Group Status Bit 836" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 3. " GSB835 ,Group Status Bit 835" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 2. " GSB834 ,Group Status Bit 834" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 1. " GSB833 ,Group Status Bit 833" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 0. " GSB832 ,Group Status Bit 832" "Group 0 (Secure),Group 1 (Non-secure)" elif (((per.l(ad:(per.long(spr:0x31F30)&0xFFFC0000)+0x04))&0x0000001F)>=0x1A) group.long 0x00E8++0x03 line.long 0x0 "GICD_IGROUPR26,Interrupt Group Register 26 (Non-secure access)" bitfld.long 0x00 31. " GSB863 ,Group Status Bit 863" "Group 0,Group 1" bitfld.long 0x00 30. " GSB862 ,Group Status Bit 862" "Group 0,Group 1" bitfld.long 0x00 29. " GSB861 ,Group Status Bit 861" "Group 0,Group 1" textline " " bitfld.long 0x00 28. " GSB860 ,Group Status Bit 860" "Group 0,Group 1" bitfld.long 0x00 27. " GSB859 ,Group Status Bit 859" "Group 0,Group 1" bitfld.long 0x00 26. " GSB858 ,Group Status Bit 858" "Group 0,Group 1" textline " " bitfld.long 0x00 25. " GSB857 ,Group Status Bit 857" "Group 0,Group 1" bitfld.long 0x00 24. " GSB856 ,Group Status Bit 856" "Group 0,Group 1" bitfld.long 0x00 23. " GSB855 ,Group Status Bit 855" "Group 0,Group 1" textline " " bitfld.long 0x00 22. " GSB854 ,Group Status Bit 854" "Group 0,Group 1" bitfld.long 0x00 21. " GSB853 ,Group Status Bit 853" "Group 0,Group 1" bitfld.long 0x00 20. " GSB852 ,Group Status Bit 852" "Group 0,Group 1" textline " " bitfld.long 0x00 19. " GSB851 ,Group Status Bit 851" "Group 0,Group 1" bitfld.long 0x00 18. " GSB850 ,Group Status Bit 850" "Group 0,Group 1" bitfld.long 0x00 17. " GSB849 ,Group Status Bit 849" "Group 0,Group 1" textline " " bitfld.long 0x00 16. " GSB848 ,Group Status Bit 848" "Group 0,Group 1" bitfld.long 0x00 15. " GSB847 ,Group Status Bit 847" "Group 0,Group 1" bitfld.long 0x00 14. " GSB846 ,Group Status Bit 846" "Group 0,Group 1" textline " " bitfld.long 0x00 13. " GSB845 ,Group Status Bit 845" "Group 0,Group 1" bitfld.long 0x00 12. " GSB844 ,Group Status Bit 844" "Group 0,Group 1" bitfld.long 0x00 11. " GSB843 ,Group Status Bit 843" "Group 0,Group 1" textline " " bitfld.long 0x00 10. " GSB842 ,Group Status Bit 842" "Group 0,Group 1" bitfld.long 0x00 9. " GSB841 ,Group Status Bit 841" "Group 0,Group 1" bitfld.long 0x00 8. " GSB840 ,Group Status Bit 840" "Group 0,Group 1" textline " " bitfld.long 0x00 7. " GSB839 ,Group Status Bit 839" "Group 0,Group 1" bitfld.long 0x00 6. " GSB838 ,Group Status Bit 838" "Group 0,Group 1" bitfld.long 0x00 5. " GSB837 ,Group Status Bit 837" "Group 0,Group 1" textline " " bitfld.long 0x00 4. " GSB836 ,Group Status Bit 836" "Group 0,Group 1" bitfld.long 0x00 3. " GSB835 ,Group Status Bit 835" "Group 0,Group 1" bitfld.long 0x00 2. " GSB834 ,Group Status Bit 834" "Group 0,Group 1" textline " " bitfld.long 0x00 1. " GSB833 ,Group Status Bit 833" "Group 0,Group 1" bitfld.long 0x00 0. " GSB832 ,Group Status Bit 832" "Group 0,Group 1" else rgroup.long 0x00E8++0x03 line.long 0x0 "GICD_IGROUPR26,Interrupt Group Register 26" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(ad:(per.long(spr:0x31F30)&0xFFFC0000)+0x04))&0x0000001F)>=0x1B)&&(PER.ADDRESS.isSECUREEX(ad:(per.long(spr:0x31F30)&0xFFFC0000)+0x00EC)) group.long 0x00EC++0x03 line.long 0x0 "GICD_IGROUPR27,Interrupt Group Register 27 (Secure access)" bitfld.long 0x00 31. " GSB895 ,Group Status Bit 895" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 30. " GSB894 ,Group Status Bit 894" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 29. " GSB893 ,Group Status Bit 893" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 28. " GSB892 ,Group Status Bit 892" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 27. " GSB891 ,Group Status Bit 891" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 26. " GSB890 ,Group Status Bit 890" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 25. " GSB889 ,Group Status Bit 889" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 24. " GSB888 ,Group Status Bit 888" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 23. " GSB887 ,Group Status Bit 887" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 22. " GSB886 ,Group Status Bit 886" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 21. " GSB885 ,Group Status Bit 885" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 20. " GSB884 ,Group Status Bit 884" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 19. " GSB883 ,Group Status Bit 883" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 18. " GSB882 ,Group Status Bit 882" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 17. " GSB881 ,Group Status Bit 881" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 16. " GSB880 ,Group Status Bit 880" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 15. " GSB879 ,Group Status Bit 879" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 14. " GSB878 ,Group Status Bit 878" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 13. " GSB877 ,Group Status Bit 877" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 12. " GSB876 ,Group Status Bit 876" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 11. " GSB875 ,Group Status Bit 875" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 10. " GSB874 ,Group Status Bit 874" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 9. " GSB873 ,Group Status Bit 873" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 8. " GSB872 ,Group Status Bit 872" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 7. " GSB871 ,Group Status Bit 871" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 6. " GSB870 ,Group Status Bit 870" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 5. " GSB869 ,Group Status Bit 869" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 4. " GSB868 ,Group Status Bit 868" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 3. " GSB867 ,Group Status Bit 867" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 2. " GSB866 ,Group Status Bit 866" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 1. " GSB865 ,Group Status Bit 865" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 0. " GSB864 ,Group Status Bit 864" "Group 0 (Secure),Group 1 (Non-secure)" elif (((per.l(ad:(per.long(spr:0x31F30)&0xFFFC0000)+0x04))&0x0000001F)>=0x1B) group.long 0x00EC++0x03 line.long 0x0 "GICD_IGROUPR27,Interrupt Group Register 27 (Non-Secure access)" bitfld.long 0x00 31. " GSB895 ,Group Status Bit 895" "Group 0,Group 1" bitfld.long 0x00 30. " GSB894 ,Group Status Bit 894" "Group 0,Group 1" bitfld.long 0x00 29. " GSB893 ,Group Status Bit 893" "Group 0,Group 1" textline " " bitfld.long 0x00 28. " GSB892 ,Group Status Bit 892" "Group 0,Group 1" bitfld.long 0x00 27. " GSB891 ,Group Status Bit 891" "Group 0,Group 1" bitfld.long 0x00 26. " GSB890 ,Group Status Bit 890" "Group 0,Group 1" textline " " bitfld.long 0x00 25. " GSB889 ,Group Status Bit 889" "Group 0,Group 1" bitfld.long 0x00 24. " GSB888 ,Group Status Bit 888" "Group 0,Group 1" bitfld.long 0x00 23. " GSB887 ,Group Status Bit 887" "Group 0,Group 1" textline " " bitfld.long 0x00 22. " GSB886 ,Group Status Bit 886" "Group 0,Group 1" bitfld.long 0x00 21. " GSB885 ,Group Status Bit 885" "Group 0,Group 1" bitfld.long 0x00 20. " GSB884 ,Group Status Bit 884" "Group 0,Group 1" textline " " bitfld.long 0x00 19. " GSB883 ,Group Status Bit 883" "Group 0,Group 1" bitfld.long 0x00 18. " GSB882 ,Group Status Bit 882" "Group 0,Group 1" bitfld.long 0x00 17. " GSB881 ,Group Status Bit 881" "Group 0,Group 1" textline " " bitfld.long 0x00 16. " GSB880 ,Group Status Bit 880" "Group 0,Group 1" bitfld.long 0x00 15. " GSB879 ,Group Status Bit 879" "Group 0,Group 1" bitfld.long 0x00 14. " GSB878 ,Group Status Bit 878" "Group 0,Group 1" textline " " bitfld.long 0x00 13. " GSB877 ,Group Status Bit 877" "Group 0,Group 1" bitfld.long 0x00 12. " GSB876 ,Group Status Bit 876" "Group 0,Group 1" bitfld.long 0x00 11. " GSB875 ,Group Status Bit 875" "Group 0,Group 1" textline " " bitfld.long 0x00 10. " GSB874 ,Group Status Bit 874" "Group 0,Group 1" bitfld.long 0x00 9. " GSB873 ,Group Status Bit 873" "Group 0,Group 1" bitfld.long 0x00 8. " GSB872 ,Group Status Bit 872" "Group 0,Group 1" textline " " bitfld.long 0x00 7. " GSB871 ,Group Status Bit 871" "Group 0,Group 1" bitfld.long 0x00 6. " GSB870 ,Group Status Bit 870" "Group 0,Group 1" bitfld.long 0x00 5. " GSB869 ,Group Status Bit 869" "Group 0,Group 1" textline " " bitfld.long 0x00 4. " GSB868 ,Group Status Bit 868" "Group 0,Group 1" bitfld.long 0x00 3. " GSB867 ,Group Status Bit 867" "Group 0,Group 1" bitfld.long 0x00 2. " GSB866 ,Group Status Bit 866" "Group 0,Group 1" textline " " bitfld.long 0x00 1. " GSB865 ,Group Status Bit 865" "Group 0,Group 1" bitfld.long 0x00 0. " GSB864 ,Group Status Bit 864" "Group 0,Group 1" else rgroup.long 0x00EC++0x03 line.long 0x0 "GICD_IGROUPR27,Interrupt Group Register 27" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(ad:(per.long(spr:0x31F30)&0xFFFC0000)+0x04))&0x0000001F)>=0x1C)&&(PER.ADDRESS.isSECUREEX(ad:(per.long(spr:0x31F30)&0xFFFC0000)+0x00F0)) group.long 0x00F0++0x03 line.long 0x0 "GICD_IGROUPR28,Interrupt Group Register 28 (Secure access)" bitfld.long 0x00 31. " GSB927 ,Group Status Bit 927" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 30. " GSB926 ,Group Status Bit 926" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 29. " GSB925 ,Group Status Bit 925" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 28. " GSB924 ,Group Status Bit 924" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 27. " GSB923 ,Group Status Bit 923" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 26. " GSB922 ,Group Status Bit 922" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 25. " GSB921 ,Group Status Bit 921" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 24. " GSB920 ,Group Status Bit 920" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 23. " GSB919 ,Group Status Bit 919" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 22. " GSB918 ,Group Status Bit 918" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 21. " GSB917 ,Group Status Bit 917" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 20. " GSB916 ,Group Status Bit 916" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 19. " GSB915 ,Group Status Bit 915" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 18. " GSB914 ,Group Status Bit 914" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 17. " GSB913 ,Group Status Bit 913" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 16. " GSB912 ,Group Status Bit 912" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 15. " GSB911 ,Group Status Bit 911" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 14. " GSB910 ,Group Status Bit 910" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 13. " GSB909 ,Group Status Bit 909" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 12. " GSB908 ,Group Status Bit 908" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 11. " GSB907 ,Group Status Bit 907" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 10. " GSB906 ,Group Status Bit 906" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 9. " GSB905 ,Group Status Bit 905" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 8. " GSB904 ,Group Status Bit 904" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 7. " GSB903 ,Group Status Bit 903" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 6. " GSB902 ,Group Status Bit 902" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 5. " GSB901 ,Group Status Bit 901" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 4. " GSB900 ,Group Status Bit 900" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 3. " GSB899 ,Group Status Bit 899" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 2. " GSB898 ,Group Status Bit 898" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 1. " GSB897 ,Group Status Bit 897" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 0. " GSB896 ,Group Status Bit 896" "Group 0 (Secure),Group 1 (Non-secure)" elif (((per.l(ad:(per.long(spr:0x31F30)&0xFFFC0000)+0x04))&0x0000001F)>=0x1C) group.long 0x00F0++0x03 line.long 0x0 "GICD_IGROUPR28,Interrupt Group Register 28 (Non-secure access)" bitfld.long 0x00 31. " GSB927 ,Group Status Bit 927" "Group 0,Group 1" bitfld.long 0x00 30. " GSB926 ,Group Status Bit 926" "Group 0,Group 1" bitfld.long 0x00 29. " GSB925 ,Group Status Bit 925" "Group 0,Group 1" textline " " bitfld.long 0x00 28. " GSB924 ,Group Status Bit 924" "Group 0,Group 1" bitfld.long 0x00 27. " GSB923 ,Group Status Bit 923" "Group 0,Group 1" bitfld.long 0x00 26. " GSB922 ,Group Status Bit 922" "Group 0,Group 1" textline " " bitfld.long 0x00 25. " GSB921 ,Group Status Bit 921" "Group 0,Group 1" bitfld.long 0x00 24. " GSB920 ,Group Status Bit 920" "Group 0,Group 1" bitfld.long 0x00 23. " GSB919 ,Group Status Bit 919" "Group 0,Group 1" textline " " bitfld.long 0x00 22. " GSB918 ,Group Status Bit 918" "Group 0,Group 1" bitfld.long 0x00 21. " GSB917 ,Group Status Bit 917" "Group 0,Group 1" bitfld.long 0x00 20. " GSB916 ,Group Status Bit 916" "Group 0,Group 1" textline " " bitfld.long 0x00 19. " GSB915 ,Group Status Bit 915" "Group 0,Group 1" bitfld.long 0x00 18. " GSB914 ,Group Status Bit 914" "Group 0,Group 1" bitfld.long 0x00 17. " GSB913 ,Group Status Bit 913" "Group 0,Group 1" textline " " bitfld.long 0x00 16. " GSB912 ,Group Status Bit 912" "Group 0,Group 1" bitfld.long 0x00 15. " GSB911 ,Group Status Bit 911" "Group 0,Group 1" bitfld.long 0x00 14. " GSB910 ,Group Status Bit 910" "Group 0,Group 1" textline " " bitfld.long 0x00 13. " GSB909 ,Group Status Bit 909" "Group 0,Group 1" bitfld.long 0x00 12. " GSB908 ,Group Status Bit 908" "Group 0,Group 1" bitfld.long 0x00 11. " GSB907 ,Group Status Bit 907" "Group 0,Group 1" textline " " bitfld.long 0x00 10. " GSB906 ,Group Status Bit 906" "Group 0,Group 1" bitfld.long 0x00 9. " GSB905 ,Group Status Bit 905" "Group 0,Group 1" bitfld.long 0x00 8. " GSB904 ,Group Status Bit 904" "Group 0,Group 1" textline " " bitfld.long 0x00 7. " GSB903 ,Group Status Bit 903" "Group 0,Group 1" bitfld.long 0x00 6. " GSB902 ,Group Status Bit 902" "Group 0,Group 1" bitfld.long 0x00 5. " GSB901 ,Group Status Bit 901" "Group 0,Group 1" textline " " bitfld.long 0x00 4. " GSB900 ,Group Status Bit 900" "Group 0,Group 1" bitfld.long 0x00 3. " GSB899 ,Group Status Bit 899" "Group 0,Group 1" bitfld.long 0x00 2. " GSB898 ,Group Status Bit 898" "Group 0,Group 1" textline " " bitfld.long 0x00 1. " GSB897 ,Group Status Bit 897" "Group 0,Group 1" bitfld.long 0x00 0. " GSB896 ,Group Status Bit 896" "Group 0,Group 1" else rgroup.long 0x0F0++0x03 line.long 0x0 "GICD_IGROUPR28,Interrupt Group Register 28" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(ad:(per.long(spr:0x31F30)&0xFFFC0000)+0x04))&0x0000001F)>=0x1D)&&(PER.ADDRESS.isSECUREEX(ad:(per.long(spr:0x31F30)&0xFFFC0000)+0x00F4)) group.long 0x00F4++0x03 line.long 0x0 "GICD_IGROUPR29,Interrupt Group Register 29 (Secure access)" bitfld.long 0x00 31. " GSB959 ,Group Status Bit 959" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 30. " GSB958 ,Group Status Bit 958" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 29. " GSB957 ,Group Status Bit 957" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 28. " GSB956 ,Group Status Bit 956" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 27. " GSB955 ,Group Status Bit 955" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 26. " GSB954 ,Group Status Bit 954" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 25. " GSB953 ,Group Status Bit 953" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 24. " GSB952 ,Group Status Bit 952" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 23. " GSB951 ,Group Status Bit 951" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 22. " GSB950 ,Group Status Bit 950" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 21. " GSB949 ,Group Status Bit 949" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 20. " GSB948 ,Group Status Bit 948" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 19. " GSB947 ,Group Status Bit 947" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 18. " GSB946 ,Group Status Bit 946" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 17. " GSB945 ,Group Status Bit 945" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 16. " GSB944 ,Group Status Bit 944" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 15. " GSB943 ,Group Status Bit 943" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 14. " GSB942 ,Group Status Bit 942" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 13. " GSB941 ,Group Status Bit 941" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 12. " GSB940 ,Group Status Bit 940" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 11. " GSB939 ,Group Status Bit 939" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 10. " GSB938 ,Group Status Bit 938" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 9. " GSB937 ,Group Status Bit 937" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 8. " GSB936 ,Group Status Bit 936" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 7. " GSB935 ,Group Status Bit 935" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 6. " GSB934 ,Group Status Bit 934" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 5. " GSB933 ,Group Status Bit 933" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 4. " GSB932 ,Group Status Bit 932" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 3. " GSB931 ,Group Status Bit 931" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 2. " GSB930 ,Group Status Bit 930" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 1. " GSB929 ,Group Status Bit 929" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 0. " GSB928 ,Group Status Bit 928" "Group 0 (Secure),Group 1 (Non-secure)" elif (((per.l(ad:(per.long(spr:0x31F30)&0xFFFC0000)+0x04))&0x0000001F)>=0x1D) group.long 0x00F4++0x03 line.long 0x0 "GICD_IGROUPR29,Interrupt Group Register 29 (Non-secure access)" bitfld.long 0x00 31. " GSB959 ,Group Status Bit 959" "Group 0,Group 1" bitfld.long 0x00 30. " GSB958 ,Group Status Bit 958" "Group 0,Group 1" bitfld.long 0x00 29. " GSB957 ,Group Status Bit 957" "Group 0,Group 1" textline " " bitfld.long 0x00 28. " GSB956 ,Group Status Bit 956" "Group 0,Group 1" bitfld.long 0x00 27. " GSB955 ,Group Status Bit 955" "Group 0,Group 1" bitfld.long 0x00 26. " GSB954 ,Group Status Bit 954" "Group 0,Group 1" textline " " bitfld.long 0x00 25. " GSB953 ,Group Status Bit 953" "Group 0,Group 1" bitfld.long 0x00 24. " GSB952 ,Group Status Bit 952" "Group 0,Group 1" bitfld.long 0x00 23. " GSB951 ,Group Status Bit 951" "Group 0,Group 1" textline " " bitfld.long 0x00 22. " GSB950 ,Group Status Bit 950" "Group 0,Group 1" bitfld.long 0x00 21. " GSB949 ,Group Status Bit 949" "Group 0,Group 1" bitfld.long 0x00 20. " GSB948 ,Group Status Bit 948" "Group 0,Group 1" textline " " bitfld.long 0x00 19. " GSB947 ,Group Status Bit 947" "Group 0,Group 1" bitfld.long 0x00 18. " GSB946 ,Group Status Bit 946" "Group 0,Group 1" bitfld.long 0x00 17. " GSB945 ,Group Status Bit 945" "Group 0,Group 1" textline " " bitfld.long 0x00 16. " GSB944 ,Group Status Bit 944" "Group 0,Group 1" bitfld.long 0x00 15. " GSB943 ,Group Status Bit 943" "Group 0,Group 1" bitfld.long 0x00 14. " GSB942 ,Group Status Bit 942" "Group 0,Group 1" textline " " bitfld.long 0x00 13. " GSB941 ,Group Status Bit 941" "Group 0,Group 1" bitfld.long 0x00 12. " GSB940 ,Group Status Bit 940" "Group 0,Group 1" bitfld.long 0x00 11. " GSB939 ,Group Status Bit 939" "Group 0,Group 1" textline " " bitfld.long 0x00 10. " GSB938 ,Group Status Bit 938" "Group 0,Group 1" bitfld.long 0x00 9. " GSB937 ,Group Status Bit 937" "Group 0,Group 1" bitfld.long 0x00 8. " GSB936 ,Group Status Bit 936" "Group 0,Group 1" textline " " bitfld.long 0x00 7. " GSB935 ,Group Status Bit 935" "Group 0,Group 1" bitfld.long 0x00 6. " GSB934 ,Group Status Bit 934" "Group 0,Group 1" bitfld.long 0x00 5. " GSB933 ,Group Status Bit 933" "Group 0,Group 1" textline " " bitfld.long 0x00 4. " GSB932 ,Group Status Bit 932" "Group 0,Group 1" bitfld.long 0x00 3. " GSB931 ,Group Status Bit 931" "Group 0,Group 1" bitfld.long 0x00 2. " GSB930 ,Group Status Bit 930" "Group 0,Group 1" textline " " bitfld.long 0x00 1. " GSB929 ,Group Status Bit 929" "Group 0,Group 1" bitfld.long 0x00 0. " GSB928 ,Group Status Bit 928" "Group 0,Group 1" else rgroup.long 0x00F4++0x03 line.long 0x0 "GICD_IGROUPR29,Interrupt Group Register 29" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(ad:(per.long(spr:0x31F30)&0xFFFC0000)+0x04))&0x0000001F)>=0x1E)&&(PER.ADDRESS.isSECUREEX(ad:(per.long(spr:0x31F30)&0xFFFC0000)+0x00F8)) group.long 0x00F8++0x03 line.long 0x0 "GICD_IGROUPR30,Interrupt Group Register 30 (Secure access)" bitfld.long 0x00 31. " GSB991 ,Group Status Bit 991" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 30. " GSB990 ,Group Status Bit 990" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 29. " GSB989 ,Group Status Bit 989" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 28. " GSB988 ,Group Status Bit 988" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 27. " GSB987 ,Group Status Bit 987" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 26. " GSB986 ,Group Status Bit 986" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 25. " GSB985 ,Group Status Bit 985" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 24. " GSB984 ,Group Status Bit 984" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 23. " GSB983 ,Group Status Bit 983" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 22. " GSB982 ,Group Status Bit 982" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 21. " GSB981 ,Group Status Bit 981" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 20. " GSB980 ,Group Status Bit 980" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 19. " GSB979 ,Group Status Bit 979" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 18. " GSB978 ,Group Status Bit 978" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 17. " GSB977 ,Group Status Bit 977" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 16. " GSB976 ,Group Status Bit 976" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 15. " GSB975 ,Group Status Bit 975" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 14. " GSB974 ,Group Status Bit 974" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 13. " GSB973 ,Group Status Bit 973" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 12. " GSB972 ,Group Status Bit 972" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 11. " GSB971 ,Group Status Bit 971" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 10. " GSB970 ,Group Status Bit 970" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 9. " GSB969 ,Group Status Bit 969" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 8. " GSB968 ,Group Status Bit 968" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 7. " GSB967 ,Group Status Bit 967" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 6. " GSB966 ,Group Status Bit 966" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 5. " GSB965 ,Group Status Bit 965" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 4. " GSB964 ,Group Status Bit 964" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 3. " GSB963 ,Group Status Bit 963" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 2. " GSB962 ,Group Status Bit 962" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 1. " GSB961 ,Group Status Bit 961" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 0. " GSB960 ,Group Status Bit 960" "Group 0 (Secure),Group 1 (Non-secure)" elif (((per.l(ad:(per.long(spr:0x31F30)&0xFFFC0000)+0x04))&0x0000001F)>=0x1E) group.long 0x00F8++0x03 line.long 0x0 "GICD_IGROUPR30,Interrupt Group Register 30 (Non-secure access)" bitfld.long 0x00 31. " GSB991 ,Group Status Bit 991" "Group 0,Group 1" bitfld.long 0x00 30. " GSB990 ,Group Status Bit 990" "Group 0,Group 1" bitfld.long 0x00 29. " GSB989 ,Group Status Bit 989" "Group 0,Group 1" textline " " bitfld.long 0x00 28. " GSB988 ,Group Status Bit 988" "Group 0,Group 1" bitfld.long 0x00 27. " GSB987 ,Group Status Bit 987" "Group 0,Group 1" bitfld.long 0x00 26. " GSB986 ,Group Status Bit 986" "Group 0,Group 1" textline " " bitfld.long 0x00 25. " GSB985 ,Group Status Bit 985" "Group 0,Group 1" bitfld.long 0x00 24. " GSB984 ,Group Status Bit 984" "Group 0,Group 1" bitfld.long 0x00 23. " GSB983 ,Group Status Bit 983" "Group 0,Group 1" textline " " bitfld.long 0x00 22. " GSB982 ,Group Status Bit 982" "Group 0,Group 1" bitfld.long 0x00 21. " GSB981 ,Group Status Bit 981" "Group 0,Group 1" bitfld.long 0x00 20. " GSB980 ,Group Status Bit 980" "Group 0,Group 1" textline " " bitfld.long 0x00 19. " GSB979 ,Group Status Bit 979" "Group 0,Group 1" bitfld.long 0x00 18. " GSB978 ,Group Status Bit 978" "Group 0,Group 1" bitfld.long 0x00 17. " GSB977 ,Group Status Bit 977" "Group 0,Group 1" textline " " bitfld.long 0x00 16. " GSB976 ,Group Status Bit 976" "Group 0,Group 1" bitfld.long 0x00 15. " GSB975 ,Group Status Bit 975" "Group 0,Group 1" bitfld.long 0x00 14. " GSB974 ,Group Status Bit 974" "Group 0,Group 1" textline " " bitfld.long 0x00 13. " GSB973 ,Group Status Bit 973" "Group 0,Group 1" bitfld.long 0x00 12. " GSB972 ,Group Status Bit 972" "Group 0,Group 1" bitfld.long 0x00 11. " GSB971 ,Group Status Bit 971" "Group 0,Group 1" textline " " bitfld.long 0x00 10. " GSB970 ,Group Status Bit 970" "Group 0,Group 1" bitfld.long 0x00 9. " GSB969 ,Group Status Bit 969" "Group 0,Group 1" bitfld.long 0x00 8. " GSB968 ,Group Status Bit 968" "Group 0,Group 1" textline " " bitfld.long 0x00 7. " GSB967 ,Group Status Bit 967" "Group 0,Group 1" bitfld.long 0x00 6. " GSB966 ,Group Status Bit 966" "Group 0,Group 1" bitfld.long 0x00 5. " GSB965 ,Group Status Bit 965" "Group 0,Group 1" textline " " bitfld.long 0x00 4. " GSB964 ,Group Status Bit 964" "Group 0,Group 1" bitfld.long 0x00 3. " GSB963 ,Group Status Bit 963" "Group 0,Group 1" bitfld.long 0x00 2. " GSB962 ,Group Status Bit 962" "Group 0,Group 1" textline " " bitfld.long 0x00 1. " GSB961 ,Group Status Bit 961" "Group 0,Group 1" bitfld.long 0x00 0. " GSB960 ,Group Status Bit 960" "Group 0,Group 1" else rgroup.long 0x00F8++0x03 line.long 0x0 "GICD_IGROUPR30,Interrupt Group Register 30" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(ad:(per.long(spr:0x31F30)&0xFFFC0000)+0x04))&0x0000001F)==0x1F)&&(PER.ADDRESS.isSECUREEX(ad:(per.long(spr:0x31F30)&0xFFFC0000)+0x00FC)) group.long 0x00FC++0x03 line.long 0x0 "GICD_IGROUPR31,Interrupt Group Register 31 (Secure access)" bitfld.long 0x00 27. " GSB1019 ,Group Status Bit 1019" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 26. " GSB1018 ,Group Status Bit 1018" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 25. " GSB1017 ,Group Status Bit 1017" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 24. " GSB1016 ,Group Status Bit 1016" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 23. " GSB1015 ,Group Status Bit 1015" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 22. " GSB1014 ,Group Status Bit 1014" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 21. " GSB1013 ,Group Status Bit 1013" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 20. " GSB1012 ,Group Status Bit 1012" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 19. " GSB1011 ,Group Status Bit 1011" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 18. " GSB1010 ,Group Status Bit 1010" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 17. " GSB1009 ,Group Status Bit 1009" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 16. " GSB1008 ,Group Status Bit 1008" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 15. " GSB1007 ,Group Status Bit 1007" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 14. " GSB1006 ,Group Status Bit 1006" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 13. " GSB1005 ,Group Status Bit 1005" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 12. " GSB1004 ,Group Status Bit 1004" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 11. " GSB1003 ,Group Status Bit 1003" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 10. " GSB1002 ,Group Status Bit 1002" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 9. " GSB1001 ,Group Status Bit 1001" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 8. " GSB1000 ,Group Status Bit 1000" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 7. " GSB999 ,Group Status Bit 999" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 6. " GSB998 ,Group Status Bit 998" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 5. " GSB997 ,Group Status Bit 997" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 4. " GSB996 ,Group Status Bit 996" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 3. " GSB995 ,Group Status Bit 995" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 2. " GSB994 ,Group Status Bit 994" "Group 0 (Secure),Group 1 (Non-secure)" textline " " bitfld.long 0x00 1. " GSB993 ,Group Status Bit 993" "Group 0 (Secure),Group 1 (Non-secure)" bitfld.long 0x00 0. " GSB992 ,Group Status Bit 992" "Group 0 (Secure),Group 1 (Non-secure)" elif (((per.l(ad:(per.long(spr:0x31F30)&0xFFFC0000)+0x04))&0x0000001F)==0x1F) group.long 0x00FC++0x03 line.long 0x0 "GICD_IGROUPR31,Interrupt Group Register 31 (Non-secure access)" bitfld.long 0x00 27. " GSB1019 ,Group Status Bit 1019" "Group 0,Group 1" bitfld.long 0x00 26. " GSB1018 ,Group Status Bit 1018" "Group 0,Group 1" textline " " bitfld.long 0x00 25. " GSB1017 ,Group Status Bit 1017" "Group 0,Group 1" bitfld.long 0x00 24. " GSB1016 ,Group Status Bit 1016" "Group 0,Group 1" bitfld.long 0x00 23. " GSB1015 ,Group Status Bit 1015" "Group 0,Group 1" textline " " bitfld.long 0x00 22. " GSB1014 ,Group Status Bit 1014" "Group 0,Group 1" bitfld.long 0x00 21. " GSB1013 ,Group Status Bit 1013" "Group 0,Group 1" bitfld.long 0x00 20. " GSB1012 ,Group Status Bit 1012" "Group 0,Group 1" textline " " bitfld.long 0x00 19. " GSB1011 ,Group Status Bit 1011" "Group 0,Group 1" bitfld.long 0x00 18. " GSB1010 ,Group Status Bit 1010" "Group 0,Group 1" bitfld.long 0x00 17. " GSB1009 ,Group Status Bit 1009" "Group 0,Group 1" textline " " bitfld.long 0x00 16. " GSB1008 ,Group Status Bit 1008" "Group 0,Group 1" bitfld.long 0x00 15. " GSB1007 ,Group Status Bit 1007" "Group 0,Group 1" bitfld.long 0x00 14. " GSB1006 ,Group Status Bit 1006" "Group 0,Group 1" textline " " bitfld.long 0x00 13. " GSB1005 ,Group Status Bit 1005" "Group 0,Group 1" bitfld.long 0x00 12. " GSB1004 ,Group Status Bit 1004" "Group 0,Group 1" bitfld.long 0x00 11. " GSB1003 ,Group Status Bit 1003" "Group 0,Group 1" textline " " bitfld.long 0x00 10. " GSB1002 ,Group Status Bit 1002" "Group 0,Group 1" bitfld.long 0x00 9. " GSB1001 ,Group Status Bit 1001" "Group 0,Group 1" bitfld.long 0x00 8. " GSB1000 ,Group Status Bit 1000" "Group 0,Group 1" textline " " bitfld.long 0x00 7. " GSB999 ,Group Status Bit 999" "Group 0,Group 1" bitfld.long 0x00 6. " GSB998 ,Group Status Bit 998" "Group 0,Group 1" bitfld.long 0x00 5. " GSB997 ,Group Status Bit 997" "Group 0,Group 1" textline " " bitfld.long 0x00 4. " GSB996 ,Group Status Bit 996" "Group 0,Group 1" bitfld.long 0x00 3. " GSB995 ,Group Status Bit 995" "Group 0,Group 1" bitfld.long 0x00 2. " GSB994 ,Group Status Bit 994" "Group 0,Group 1" textline " " bitfld.long 0x00 1. " GSB993 ,Group Status Bit 993" "Group 0,Group 1" bitfld.long 0x00 0. " GSB992 ,Group Status Bit 992" "Group 0,Group 1" else rgroup.long 0x00FC++0x03 line.long 0x0 "GICD_IGROUPR31,Interrupt Group Register 31" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif tree.end endif width 24. tree "Set/Clear Enable Registers" group.long 0x0100++0x03 line.long 0x0 "GICD_SET/CLR_ENABLER0,Interrupt Set/Clear Enable Register 0" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENB31 ,Set/Clear Enable Bit 31" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRENB30 ,Set/Clear Enable Bit 30" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRENB29 ,Set/Clear Enable Bit 29" "Disabled,Enabled" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENB28 ,Set/Clear Enable Bit 28" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRENB27 ,Set/Clear Enable Bit 27" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRENB26 ,Set/Clear Enable Bit 26" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENB25 ,Set/Clear Enable Bit 25" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRENB24 ,Set/Clear Enable Bit 24" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRENB23 ,Set/Clear Enable Bit 23" "Disabled,Enabled" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENB22 ,Set/Clear Enable Bit 22" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRENB21 ,Set/Clear Enable Bit 21" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRENB20 ,Set/Clear Enable Bit 20" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENB19 ,Set/Clear Enable Bit 19" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRENB18 ,Set/Clear Enable Bit 18" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRENB17 ,Set/Clear Enable Bit 17" "Disabled,Enabled" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENB16 ,Set/Clear Enable Bit 16" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRENB15 ,Set/Clear Enable Bit 15" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRENB14 ,Set/Clear Enable Bit 14" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENB13 ,Set/Clear Enable Bit 13" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRENB12 ,Set/Clear Enable Bit 12" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRENB11 ,Set/Clear Enable Bit 11" "Disabled,Enabled" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENB10 ,Set/Clear Enable Bit 10" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRENB9 ,Set/Clear Enable Bit 9" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRENB8 ,Set/Clear Enable Bit 8" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENB7 ,Set/Clear Enable Bit 7" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRENB6 ,Set/Clear Enable Bit 6" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRENB5 ,Set/Clear Enable Bit 5" "Disabled,Enabled" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENB4 ,Set/Clear Enable Bit 4" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRENB3 ,Set/Clear Enable Bit 3" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRENB2 ,Set/Clear Enable Bit 2" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENB1 ,Set/Clear Enable Bit 1" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRENB0 ,Set/Clear Enable Bit 0" "Disabled,Enabled" if (((per.l(ad:(per.long(spr:0x31F30)&0xFFFC0000)+0x04))&0x0000001F)>=0x01) group.long 0x0104++0x03 line.long 0x0 "GICD_SET/CLR_ENABLER1,Interrupt Set/Clear Enable Register 1" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENB63 ,Set/Clear Enable Bit 63" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRENB62 ,Set/Clear Enable Bit 62" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRENB61 ,Set/Clear Enable Bit 61" "Disabled,Enabled" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENB60 ,Set/Clear Enable Bit 60" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRENB59 ,Set/Clear Enable Bit 59" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRENB58 ,Set/Clear Enable Bit 58" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENB57 ,Set/Clear Enable Bit 57" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRENB56 ,Set/Clear Enable Bit 56" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRENB55 ,Set/Clear Enable Bit 55" "Disabled,Enabled" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENB54 ,Set/Clear Enable Bit 54" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRENB53 ,Set/Clear Enable Bit 53" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRENB52 ,Set/Clear Enable Bit 52" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENB51 ,Set/Clear Enable Bit 51" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRENB50 ,Set/Clear Enable Bit 50" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRENB49 ,Set/Clear Enable Bit 49" "Disabled,Enabled" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENB48 ,Set/Clear Enable Bit 48" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRENB47 ,Set/Clear Enable Bit 47" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRENB46 ,Set/Clear Enable Bit 46" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENB45 ,Set/Clear Enable Bit 45" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRENB44 ,Set/Clear Enable Bit 44" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRENB43 ,Set/Clear Enable Bit 43" "Disabled,Enabled" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENB42 ,Set/Clear Enable Bit 42" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRENB41 ,Set/Clear Enable Bit 41" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRENB40 ,Set/Clear Enable Bit 40" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENB39 ,Set/Clear Enable Bit 39" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRENB38 ,Set/Clear Enable Bit 38" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRENB37 ,Set/Clear Enable Bit 37" "Disabled,Enabled" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENB36 ,Set/Clear Enable Bit 36" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRENB35 ,Set/Clear Enable Bit 35" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRENB34 ,Set/Clear Enable Bit 34" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENB33 ,Set/Clear Enable Bit 33" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRENB32 ,Set/Clear Enable Bit 32" "Disabled,Enabled" else rgroup.long 0x0104++0x03 line.long 0x0 "GICD_SET/CLR_ENABLER1,Interrupt Set/Clear Enable Register 1" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(ad:(per.long(spr:0x31F30)&0xFFFC0000)+0x04))&0x0000001F)>=0x02) group.long 0x0108++0x03 line.long 0x0 "GICD_SET/CLR_ENABLER2,Interrupt Set/Clear Enable Register 2" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENB95 ,Set/Clear Enable Bit 95" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRENB94 ,Set/Clear Enable Bit 94" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRENB93 ,Set/Clear Enable Bit 93" "Disabled,Enabled" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENB92 ,Set/Clear Enable Bit 92" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRENB91 ,Set/Clear Enable Bit 91" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRENB90 ,Set/Clear Enable Bit 90" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENB89 ,Set/Clear Enable Bit 89" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRENB88 ,Set/Clear Enable Bit 88" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRENB87 ,Set/Clear Enable Bit 87" "Disabled,Enabled" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENB86 ,Set/Clear Enable Bit 86" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRENB85 ,Set/Clear Enable Bit 85" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRENB84 ,Set/Clear Enable Bit 84" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENB83 ,Set/Clear Enable Bit 83" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRENB82 ,Set/Clear Enable Bit 82" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRENB81 ,Set/Clear Enable Bit 81" "Disabled,Enabled" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENB80 ,Set/Clear Enable Bit 80" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRENB79 ,Set/Clear Enable Bit 79" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRENB78 ,Set/Clear Enable Bit 78" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENB77 ,Set/Clear Enable Bit 77" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRENB76 ,Set/Clear Enable Bit 76" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRENB75 ,Set/Clear Enable Bit 75" "Disabled,Enabled" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENB74 ,Set/Clear Enable Bit 74" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRENB73 ,Set/Clear Enable Bit 73" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRENB72 ,Set/Clear Enable Bit 72" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENB71 ,Set/Clear Enable Bit 71" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRENB70 ,Set/Clear Enable Bit 70" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRENB69 ,Set/Clear Enable Bit 69" "Disabled,Enabled" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENB68 ,Set/Clear Enable Bit 68" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRENB67 ,Set/Clear Enable Bit 67" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRENB66 ,Set/Clear Enable Bit 66" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENB65 ,Set/Clear Enable Bit 65" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRENB64 ,Set/Clear Enable Bit 64" "Disabled,Enabled" else rgroup.long 0x0108++0x03 line.long 0x0 "GICD_SET/CLR_ENABLER2,Interrupt Set/Clear Enable Register 2" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(ad:(per.long(spr:0x31F30)&0xFFFC0000)+0x04))&0x0000001F)>=0x03) group.long 0x010C++0x03 line.long 0x0 "GICD_SET/CLR_ENABLER3,Interrupt Set/Clear Enable Register 3" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENB127 ,Set/Clear Enable Bit 127" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRENB126 ,Set/Clear Enable Bit 126" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRENB125 ,Set/Clear Enable Bit 125" "Disabled,Enabled" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENB124 ,Set/Clear Enable Bit 124" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRENB123 ,Set/Clear Enable Bit 123" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRENB122 ,Set/Clear Enable Bit 122" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENB121 ,Set/Clear Enable Bit 121" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRENB120 ,Set/Clear Enable Bit 120" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRENB119 ,Set/Clear Enable Bit 119" "Disabled,Enabled" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENB118 ,Set/Clear Enable Bit 118" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRENB117 ,Set/Clear Enable Bit 117" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRENB116 ,Set/Clear Enable Bit 116" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENB115 ,Set/Clear Enable Bit 115" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRENB114 ,Set/Clear Enable Bit 114" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRENB113 ,Set/Clear Enable Bit 113" "Disabled,Enabled" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENB112 ,Set/Clear Enable Bit 112" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRENB111 ,Set/Clear Enable Bit 111" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRENB110 ,Set/Clear Enable Bit 110" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENB109 ,Set/Clear Enable Bit 109" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRENB108 ,Set/Clear Enable Bit 108" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRENB107 ,Set/Clear Enable Bit 107" "Disabled,Enabled" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENB106 ,Set/Clear Enable Bit 106" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRENB105 ,Set/Clear Enable Bit 105" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRENB104 ,Set/Clear Enable Bit 104" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENB103 ,Set/Clear Enable Bit 103" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRENB102 ,Set/Clear Enable Bit 102" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRENB101 ,Set/Clear Enable Bit 101" "Disabled,Enabled" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENB100 ,Set/Clear Enable Bit 100" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRENB99 ,Set/Clear Enable Bit 99" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRENB98 ,Set/Clear Enable Bit 98" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENB97 ,Set/Clear Enable Bit 97" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRENB96 ,Set/Clear Enable Bit 96" "Disabled,Enabled" else rgroup.long 0x010C++0x03 line.long 0x0 "GICD_SET/CLR_ENABLER3,Interrupt Set/Clear Enable Register 3" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(ad:(per.long(spr:0x31F30)&0xFFFC0000)+0x04))&0x0000001F)>=0x04) group.long 0x0110++0x03 line.long 0x0 "GICD_SET/CLR_ENABLER4,Interrupt Set/Clear Enable Register 4" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENB159 ,Set/Clear Enable Bit 159" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRENB158 ,Set/Clear Enable Bit 158" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRENB157 ,Set/Clear Enable Bit 157" "Disabled,Enabled" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENB156 ,Set/Clear Enable Bit 156" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRENB155 ,Set/Clear Enable Bit 155" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRENB154 ,Set/Clear Enable Bit 154" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENB153 ,Set/Clear Enable Bit 153" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRENB152 ,Set/Clear Enable Bit 152" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRENB151 ,Set/Clear Enable Bit 151" "Disabled,Enabled" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENB150 ,Set/Clear Enable Bit 150" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRENB149 ,Set/Clear Enable Bit 149" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRENB148 ,Set/Clear Enable Bit 148" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENB147 ,Set/Clear Enable Bit 147" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRENB146 ,Set/Clear Enable Bit 146" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRENB145 ,Set/Clear Enable Bit 145" "Disabled,Enabled" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENB144 ,Set/Clear Enable Bit 144" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRENB143 ,Set/Clear Enable Bit 143" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRENB142 ,Set/Clear Enable Bit 142" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENB141 ,Set/Clear Enable Bit 141" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRENB140 ,Set/Clear Enable Bit 140" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRENB139 ,Set/Clear Enable Bit 139" "Disabled,Enabled" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENB138 ,Set/Clear Enable Bit 138" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRENB137 ,Set/Clear Enable Bit 137" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRENB136 ,Set/Clear Enable Bit 136" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENB135 ,Set/Clear Enable Bit 135" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRENB134 ,Set/Clear Enable Bit 134" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRENB133 ,Set/Clear Enable Bit 133" "Disabled,Enabled" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENB132 ,Set/Clear Enable Bit 132" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRENB131 ,Set/Clear Enable Bit 131" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRENB130 ,Set/Clear Enable Bit 130" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENB129 ,Set/Clear Enable Bit 129" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRENB128 ,Set/Clear Enable Bit 128" "Disabled,Enabled" else rgroup.long 0x0110++0x03 line.long 0x0 "GICD_SET/CLR_ENABLER4,Interrupt Set/Clear Enable Register 4" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(ad:(per.long(spr:0x31F30)&0xFFFC0000)+0x04))&0x0000001F)>=0x05) group.long 0x0114++0x03 line.long 0x0 "GICD_SET/CLR_ENABLER5,Interrupt Set/Clear Enable Register 5" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENB191 ,Set/Clear Enable Bit 191" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRENB190 ,Set/Clear Enable Bit 190" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRENB189 ,Set/Clear Enable Bit 189" "Disabled,Enabled" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENB188 ,Set/Clear Enable Bit 188" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRENB187 ,Set/Clear Enable Bit 187" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRENB186 ,Set/Clear Enable Bit 186" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENB185 ,Set/Clear Enable Bit 185" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRENB184 ,Set/Clear Enable Bit 184" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRENB183 ,Set/Clear Enable Bit 183" "Disabled,Enabled" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENB182 ,Set/Clear Enable Bit 182" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRENB181 ,Set/Clear Enable Bit 181" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRENB180 ,Set/Clear Enable Bit 180" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENB179 ,Set/Clear Enable Bit 179" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRENB178 ,Set/Clear Enable Bit 178" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRENB177 ,Set/Clear Enable Bit 177" "Disabled,Enabled" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENB176 ,Set/Clear Enable Bit 176" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRENB175 ,Set/Clear Enable Bit 175" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRENB174 ,Set/Clear Enable Bit 174" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENB173 ,Set/Clear Enable Bit 173" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRENB172 ,Set/Clear Enable Bit 172" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRENB171 ,Set/Clear Enable Bit 171" "Disabled,Enabled" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENB170 ,Set/Clear Enable Bit 170" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRENB169 ,Set/Clear Enable Bit 169" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRENB168 ,Set/Clear Enable Bit 168" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENB167 ,Set/Clear Enable Bit 167" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRENB166 ,Set/Clear Enable Bit 166" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRENB165 ,Set/Clear Enable Bit 165" "Disabled,Enabled" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENB164 ,Set/Clear Enable Bit 164" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRENB163 ,Set/Clear Enable Bit 163" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRENB162 ,Set/Clear Enable Bit 162" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENB161 ,Set/Clear Enable Bit 161" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRENB160 ,Set/Clear Enable Bit 160" "Disabled,Enabled" else rgroup.long 0x0114++0x03 line.long 0x0 "GICD_SET/CLR_ENABLER5,Interrupt Set/Clear Enable Register 5" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(ad:(per.long(spr:0x31F30)&0xFFFC0000)+0x04))&0x0000001F)>=0x06) group.long 0x0118++0x03 line.long 0x0 "GICD_SET/CLR_ENABLER6,Interrupt Set/Clear Enable Register 6" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENB223 ,Set/Clear Enable Bit 223" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRENB222 ,Set/Clear Enable Bit 222" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRENB221 ,Set/Clear Enable Bit 221" "Disabled,Enabled" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENB220 ,Set/Clear Enable Bit 220" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRENB219 ,Set/Clear Enable Bit 219" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRENB218 ,Set/Clear Enable Bit 218" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENB217 ,Set/Clear Enable Bit 217" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRENB216 ,Set/Clear Enable Bit 216" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRENB215 ,Set/Clear Enable Bit 215" "Disabled,Enabled" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENB214 ,Set/Clear Enable Bit 214" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRENB213 ,Set/Clear Enable Bit 213" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRENB212 ,Set/Clear Enable Bit 212" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENB211 ,Set/Clear Enable Bit 211" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRENB210 ,Set/Clear Enable Bit 210" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRENB209 ,Set/Clear Enable Bit 209" "Disabled,Enabled" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENB208 ,Set/Clear Enable Bit 208" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRENB207 ,Set/Clear Enable Bit 207" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRENB206 ,Set/Clear Enable Bit 206" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENB205 ,Set/Clear Enable Bit 205" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRENB204 ,Set/Clear Enable Bit 204" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRENB203 ,Set/Clear Enable Bit 203" "Disabled,Enabled" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENB202 ,Set/Clear Enable Bit 202" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRENB201 ,Set/Clear Enable Bit 201" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRENB200 ,Set/Clear Enable Bit 200" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENB199 ,Set/Clear Enable Bit 199" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRENB198 ,Set/Clear Enable Bit 198" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRENB197 ,Set/Clear Enable Bit 197" "Disabled,Enabled" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENB196 ,Set/Clear Enable Bit 196" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRENB195 ,Set/Clear Enable Bit 195" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRENB194 ,Set/Clear Enable Bit 194" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENB193 ,Set/Clear Enable Bit 193" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRENB192 ,Set/Clear Enable Bit 192" "Disabled,Enabled" else rgroup.long 0x0118++0x03 line.long 0x0 "GICD_SET/CLR_ENABLER6,Interrupt Set/Clear Enable Register 6" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(ad:(per.long(spr:0x31F30)&0xFFFC0000)+0x04))&0x0000001F)>=0x07) group.long 0x011C++0x03 line.long 0x0 "GICD_SET/CLR_ENABLER7,Interrupt Set/Clear Enable Register 7" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENB255 ,Set/Clear Enable Bit 255" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRENB254 ,Set/Clear Enable Bit 254" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRENB253 ,Set/Clear Enable Bit 253" "Disabled,Enabled" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENB252 ,Set/Clear Enable Bit 252" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRENB251 ,Set/Clear Enable Bit 251" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRENB250 ,Set/Clear Enable Bit 250" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENB249 ,Set/Clear Enable Bit 249" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRENB248 ,Set/Clear Enable Bit 248" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRENB247 ,Set/Clear Enable Bit 247" "Disabled,Enabled" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENB246 ,Set/Clear Enable Bit 246" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRENB245 ,Set/Clear Enable Bit 245" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRENB244 ,Set/Clear Enable Bit 244" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENB243 ,Set/Clear Enable Bit 243" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRENB242 ,Set/Clear Enable Bit 242" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRENB241 ,Set/Clear Enable Bit 241" "Disabled,Enabled" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENB240 ,Set/Clear Enable Bit 240" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRENB239 ,Set/Clear Enable Bit 239" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRENB238 ,Set/Clear Enable Bit 238" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENB237 ,Set/Clear Enable Bit 237" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRENB236 ,Set/Clear Enable Bit 236" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRENB235 ,Set/Clear Enable Bit 235" "Disabled,Enabled" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENB234 ,Set/Clear Enable Bit 234" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRENB233 ,Set/Clear Enable Bit 233" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRENB232 ,Set/Clear Enable Bit 232" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENB231 ,Set/Clear Enable Bit 231" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRENB230 ,Set/Clear Enable Bit 230" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRENB229 ,Set/Clear Enable Bit 229" "Disabled,Enabled" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENB228 ,Set/Clear Enable Bit 228" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRENB227 ,Set/Clear Enable Bit 227" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRENB226 ,Set/Clear Enable Bit 226" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENB225 ,Set/Clear Enable Bit 225" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRENB224 ,Set/Clear Enable Bit 224" "Disabled,Enabled" else rgroup.long 0x011C++0x03 line.long 0x0 "GICD_SET/CLR_ENABLER7,Interrupt Set/Clear Enable Register 7" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(ad:(per.long(spr:0x31F30)&0xFFFC0000)+0x04))&0x0000001F)>=0x08) group.long 0x0120++0x03 line.long 0x0 "GICD_SET/CLR_ENABLER8,Interrupt Set/Clear Enable Register 8" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENB287 ,Set/Clear Enable Bit 287" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRENB286 ,Set/Clear Enable Bit 286" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRENB285 ,Set/Clear Enable Bit 285" "Disabled,Enabled" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENB284 ,Set/Clear Enable Bit 284" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRENB283 ,Set/Clear Enable Bit 283" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRENB282 ,Set/Clear Enable Bit 282" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENB281 ,Set/Clear Enable Bit 281" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRENB280 ,Set/Clear Enable Bit 280" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRENB279 ,Set/Clear Enable Bit 279" "Disabled,Enabled" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENB278 ,Set/Clear Enable Bit 278" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRENB277 ,Set/Clear Enable Bit 277" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRENB276 ,Set/Clear Enable Bit 276" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENB275 ,Set/Clear Enable Bit 275" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRENB274 ,Set/Clear Enable Bit 274" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRENB273 ,Set/Clear Enable Bit 273" "Disabled,Enabled" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENB272 ,Set/Clear Enable Bit 272" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRENB271 ,Set/Clear Enable Bit 271" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRENB270 ,Set/Clear Enable Bit 270" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENB269 ,Set/Clear Enable Bit 269" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRENB268 ,Set/Clear Enable Bit 268" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRENB267 ,Set/Clear Enable Bit 267" "Disabled,Enabled" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENB266 ,Set/Clear Enable Bit 266" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRENB265 ,Set/Clear Enable Bit 265" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRENB264 ,Set/Clear Enable Bit 264" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENB263 ,Set/Clear Enable Bit 263" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRENB262 ,Set/Clear Enable Bit 262" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRENB261 ,Set/Clear Enable Bit 261" "Disabled,Enabled" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENB260 ,Set/Clear Enable Bit 260" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRENB259 ,Set/Clear Enable Bit 259" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRENB258 ,Set/Clear Enable Bit 258" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENB257 ,Set/Clear Enable Bit 257" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRENB256 ,Set/Clear Enable Bit 256" "Disabled,Enabled" else rgroup.long 0x0120++0x03 line.long 0x0 "GICD_SET/CLR_ENABLER8,Interrupt Set/Clear Enable Register 8" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(ad:(per.long(spr:0x31F30)&0xFFFC0000)+0x04))&0x0000001F)>=0x09) group.long 0x0124++0x03 line.long 0x0 "GICD_SET/CLR_ENABLER9,Interrupt Set/Clear Enable Register 9" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENB319 ,Set/Clear Enable Bit 319" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRENB318 ,Set/Clear Enable Bit 318" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRENB317 ,Set/Clear Enable Bit 317" "Disabled,Enabled" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENB316 ,Set/Clear Enable Bit 316" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRENB315 ,Set/Clear Enable Bit 315" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRENB314 ,Set/Clear Enable Bit 314" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENB313 ,Set/Clear Enable Bit 313" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRENB312 ,Set/Clear Enable Bit 312" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRENB311 ,Set/Clear Enable Bit 311" "Disabled,Enabled" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENB310 ,Set/Clear Enable Bit 310" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRENB309 ,Set/Clear Enable Bit 309" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRENB308 ,Set/Clear Enable Bit 308" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENB307 ,Set/Clear Enable Bit 307" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRENB306 ,Set/Clear Enable Bit 306" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRENB305 ,Set/Clear Enable Bit 305" "Disabled,Enabled" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENB304 ,Set/Clear Enable Bit 304" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRENB303 ,Set/Clear Enable Bit 303" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRENB302 ,Set/Clear Enable Bit 302" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENB301 ,Set/Clear Enable Bit 301" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRENB300 ,Set/Clear Enable Bit 300" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRENB299 ,Set/Clear Enable Bit 299" "Disabled,Enabled" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENB298 ,Set/Clear Enable Bit 298" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRENB297 ,Set/Clear Enable Bit 297" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRENB296 ,Set/Clear Enable Bit 296" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENB295 ,Set/Clear Enable Bit 295" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRENB294 ,Set/Clear Enable Bit 294" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRENB293 ,Set/Clear Enable Bit 293" "Disabled,Enabled" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENB292 ,Set/Clear Enable Bit 292" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRENB291 ,Set/Clear Enable Bit 291" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRENB290 ,Set/Clear Enable Bit 290" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENB289 ,Set/Clear Enable Bit 289" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRENB288 ,Set/Clear Enable Bit 288" "Disabled,Enabled" else rgroup.long 0x0124++0x03 line.long 0x0 "GICD_SET/CLR_ENABLER9,Interrupt Set/Clear Enable Register 9" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(ad:(per.long(spr:0x31F30)&0xFFFC0000)+0x04))&0x0000001F)>=0x0A) group.long 0x0128++0x03 line.long 0x0 "GICD_SET/CLR_ENABLER10,Interrupt Set/Clear Enable Register 10" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENB351 ,Set/Clear Enable Bit 351" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRENB350 ,Set/Clear Enable Bit 350" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRENB349 ,Set/Clear Enable Bit 349" "Disabled,Enabled" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENB348 ,Set/Clear Enable Bit 348" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRENB347 ,Set/Clear Enable Bit 347" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRENB346 ,Set/Clear Enable Bit 346" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENB345 ,Set/Clear Enable Bit 345" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRENB344 ,Set/Clear Enable Bit 344" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRENB343 ,Set/Clear Enable Bit 343" "Disabled,Enabled" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENB342 ,Set/Clear Enable Bit 342" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRENB341 ,Set/Clear Enable Bit 341" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRENB340 ,Set/Clear Enable Bit 340" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENB339 ,Set/Clear Enable Bit 339" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRENB338 ,Set/Clear Enable Bit 338" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRENB337 ,Set/Clear Enable Bit 337" "Disabled,Enabled" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENB336 ,Set/Clear Enable Bit 336" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRENB335 ,Set/Clear Enable Bit 335" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRENB334 ,Set/Clear Enable Bit 334" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENB333 ,Set/Clear Enable Bit 333" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRENB332 ,Set/Clear Enable Bit 332" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRENB331 ,Set/Clear Enable Bit 331" "Disabled,Enabled" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENB330 ,Set/Clear Enable Bit 330" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRENB329 ,Set/Clear Enable Bit 329" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRENB328 ,Set/Clear Enable Bit 328" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENB327 ,Set/Clear Enable Bit 327" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRENB326 ,Set/Clear Enable Bit 326" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRENB325 ,Set/Clear Enable Bit 325" "Disabled,Enabled" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENB324 ,Set/Clear Enable Bit 324" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRENB323 ,Set/Clear Enable Bit 323" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRENB322 ,Set/Clear Enable Bit 322" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENB321 ,Set/Clear Enable Bit 321" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRENB320 ,Set/Clear Enable Bit 320" "Disabled,Enabled" else rgroup.long 0x0128++0x03 line.long 0x0 "GICD_SET/CLR_ENABLER10,Interrupt Set/Clear Enable Register 10" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(ad:(per.long(spr:0x31F30)&0xFFFC0000)+0x04))&0x0000001F)>=0x0B) group.long 0x012C++0x03 line.long 0x0 "GICD_SET/CLR_ENABLER11,Interrupt Set/Clear Enable Register 11" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENB383 ,Set/Clear Enable Bit 383" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRENB382 ,Set/Clear Enable Bit 382" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRENB381 ,Set/Clear Enable Bit 381" "Disabled,Enabled" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENB380 ,Set/Clear Enable Bit 380" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRENB379 ,Set/Clear Enable Bit 379" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRENB378 ,Set/Clear Enable Bit 378" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENB377 ,Set/Clear Enable Bit 377" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRENB376 ,Set/Clear Enable Bit 376" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRENB375 ,Set/Clear Enable Bit 375" "Disabled,Enabled" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENB374 ,Set/Clear Enable Bit 374" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRENB373 ,Set/Clear Enable Bit 373" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRENB372 ,Set/Clear Enable Bit 372" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENB371 ,Set/Clear Enable Bit 371" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRENB370 ,Set/Clear Enable Bit 370" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRENB369 ,Set/Clear Enable Bit 369" "Disabled,Enabled" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENB368 ,Set/Clear Enable Bit 368" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRENB367 ,Set/Clear Enable Bit 367" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRENB366 ,Set/Clear Enable Bit 366" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENB365 ,Set/Clear Enable Bit 365" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRENB364 ,Set/Clear Enable Bit 364" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRENB363 ,Set/Clear Enable Bit 363" "Disabled,Enabled" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENB362 ,Set/Clear Enable Bit 362" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRENB361 ,Set/Clear Enable Bit 361" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRENB360 ,Set/Clear Enable Bit 360" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENB359 ,Set/Clear Enable Bit 359" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRENB358 ,Set/Clear Enable Bit 358" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRENB357 ,Set/Clear Enable Bit 357" "Disabled,Enabled" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENB356 ,Set/Clear Enable Bit 356" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRENB355 ,Set/Clear Enable Bit 355" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRENB354 ,Set/Clear Enable Bit 354" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENB353 ,Set/Clear Enable Bit 353" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRENB352 ,Set/Clear Enable Bit 352" "Disabled,Enabled" else rgroup.long 0x012C++0x03 line.long 0x0 "GICD_SET/CLR_ENABLER11,Interrupt Set/Clear Enable Register 11" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(ad:(per.long(spr:0x31F30)&0xFFFC0000)+0x04))&0x0000001F)>=0x0C) group.long 0x0130++0x03 line.long 0x0 "GICD_SET/CLR_ENABLER12,Interrupt Set/Clear Enable Register 12" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENB415 ,Set/Clear Enable Bit 415" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRENB414 ,Set/Clear Enable Bit 414" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRENB413 ,Set/Clear Enable Bit 413" "Disabled,Enabled" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENB412 ,Set/Clear Enable Bit 412" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRENB411 ,Set/Clear Enable Bit 411" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRENB410 ,Set/Clear Enable Bit 410" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENB409 ,Set/Clear Enable Bit 409" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRENB408 ,Set/Clear Enable Bit 408" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRENB407 ,Set/Clear Enable Bit 407" "Disabled,Enabled" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENB406 ,Set/Clear Enable Bit 406" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRENB405 ,Set/Clear Enable Bit 405" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRENB404 ,Set/Clear Enable Bit 404" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENB403 ,Set/Clear Enable Bit 403" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRENB402 ,Set/Clear Enable Bit 402" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRENB401 ,Set/Clear Enable Bit 401" "Disabled,Enabled" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENB400 ,Set/Clear Enable Bit 400" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRENB399 ,Set/Clear Enable Bit 399" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRENB398 ,Set/Clear Enable Bit 398" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENB397 ,Set/Clear Enable Bit 397" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRENB396 ,Set/Clear Enable Bit 396" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRENB395 ,Set/Clear Enable Bit 395" "Disabled,Enabled" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENB394 ,Set/Clear Enable Bit 394" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRENB393 ,Set/Clear Enable Bit 393" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRENB392 ,Set/Clear Enable Bit 392" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENB391 ,Set/Clear Enable Bit 391" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRENB390 ,Set/Clear Enable Bit 390" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRENB389 ,Set/Clear Enable Bit 389" "Disabled,Enabled" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENB388 ,Set/Clear Enable Bit 388" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRENB387 ,Set/Clear Enable Bit 387" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRENB386 ,Set/Clear Enable Bit 386" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENB385 ,Set/Clear Enable Bit 385" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRENB384 ,Set/Clear Enable Bit 384" "Disabled,Enabled" else rgroup.long 0x0130++0x03 line.long 0x0 "GICD_SET/CLR_ENABLER12,Interrupt Set/Clear Enable Register 12" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(ad:(per.long(spr:0x31F30)&0xFFFC0000)+0x04))&0x0000001F)>=0x0D) group.long 0x0134++0x03 line.long 0x0 "GICD_SET/CLR_ENABLER13,Interrupt Set/Clear Enable Register 13" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENB447 ,Set/Clear Enable Bit 447" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRENB446 ,Set/Clear Enable Bit 446" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRENB445 ,Set/Clear Enable Bit 445" "Disabled,Enabled" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENB444 ,Set/Clear Enable Bit 444" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRENB443 ,Set/Clear Enable Bit 443" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRENB442 ,Set/Clear Enable Bit 442" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENB441 ,Set/Clear Enable Bit 441" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRENB440 ,Set/Clear Enable Bit 440" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRENB439 ,Set/Clear Enable Bit 439" "Disabled,Enabled" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENB438 ,Set/Clear Enable Bit 438" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRENB437 ,Set/Clear Enable Bit 437" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRENB436 ,Set/Clear Enable Bit 436" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENB435 ,Set/Clear Enable Bit 435" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRENB434 ,Set/Clear Enable Bit 434" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRENB433 ,Set/Clear Enable Bit 433" "Disabled,Enabled" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENB432 ,Set/Clear Enable Bit 432" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRENB431 ,Set/Clear Enable Bit 431" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRENB430 ,Set/Clear Enable Bit 430" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENB429 ,Set/Clear Enable Bit 429" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRENB428 ,Set/Clear Enable Bit 428" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRENB427 ,Set/Clear Enable Bit 427" "Disabled,Enabled" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENB426 ,Set/Clear Enable Bit 426" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRENB425 ,Set/Clear Enable Bit 425" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRENB424 ,Set/Clear Enable Bit 424" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENB423 ,Set/Clear Enable Bit 423" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRENB422 ,Set/Clear Enable Bit 422" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRENB421 ,Set/Clear Enable Bit 421" "Disabled,Enabled" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENB420 ,Set/Clear Enable Bit 420" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRENB419 ,Set/Clear Enable Bit 419" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRENB418 ,Set/Clear Enable Bit 418" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENB417 ,Set/Clear Enable Bit 417" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRENB416 ,Set/Clear Enable Bit 416" "Disabled,Enabled" else rgroup.long 0x0134++0x03 line.long 0x0 "GICD_SET/CLR_ENABLER13,Interrupt Set/Clear Enable Register 13" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(ad:(per.long(spr:0x31F30)&0xFFFC0000)+0x04))&0x0000001F)>=0x0E) group.long 0x0138++0x03 line.long 0x0 "GICD_SET/CLR_ENABLER14,Interrupt Set/Clear Enable Register 14" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENB479 ,Set/Clear Enable Bit 479" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRENB478 ,Set/Clear Enable Bit 478" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRENB477 ,Set/Clear Enable Bit 477" "Disabled,Enabled" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENB476 ,Set/Clear Enable Bit 476" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRENB475 ,Set/Clear Enable Bit 475" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRENB474 ,Set/Clear Enable Bit 474" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENB473 ,Set/Clear Enable Bit 473" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRENB472 ,Set/Clear Enable Bit 472" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRENB471 ,Set/Clear Enable Bit 471" "Disabled,Enabled" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENB470 ,Set/Clear Enable Bit 470" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRENB469 ,Set/Clear Enable Bit 469" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRENB468 ,Set/Clear Enable Bit 468" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENB467 ,Set/Clear Enable Bit 467" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRENB466 ,Set/Clear Enable Bit 466" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRENB465 ,Set/Clear Enable Bit 465" "Disabled,Enabled" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENB464 ,Set/Clear Enable Bit 464" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRENB463 ,Set/Clear Enable Bit 463" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRENB462 ,Set/Clear Enable Bit 462" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENB461 ,Set/Clear Enable Bit 461" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRENB460 ,Set/Clear Enable Bit 460" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRENB459 ,Set/Clear Enable Bit 459" "Disabled,Enabled" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENB458 ,Set/Clear Enable Bit 458" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRENB457 ,Set/Clear Enable Bit 457" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRENB456 ,Set/Clear Enable Bit 456" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENB455 ,Set/Clear Enable Bit 455" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRENB454 ,Set/Clear Enable Bit 454" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRENB453 ,Set/Clear Enable Bit 453" "Disabled,Enabled" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENB452 ,Set/Clear Enable Bit 452" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRENB451 ,Set/Clear Enable Bit 451" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRENB450 ,Set/Clear Enable Bit 450" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENB449 ,Set/Clear Enable Bit 449" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRENB448 ,Set/Clear Enable Bit 448" "Disabled,Enabled" else rgroup.long 0x0138++0x03 line.long 0x0 "GICD_SET/CLR_ENABLER14,Interrupt Set/Clear Enable Register 14" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(ad:(per.long(spr:0x31F30)&0xFFFC0000)+0x04))&0x0000001F)>=0x0F) group.long 0x013C++0x03 line.long 0x0 "GICD_SET/CLR_ENABLER15,Interrupt Set/Clear Enable Register 15" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENB511 ,Set/Clear Enable Bit 511" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRENB510 ,Set/Clear Enable Bit 510" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRENB509 ,Set/Clear Enable Bit 509" "Disabled,Enabled" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENB508 ,Set/Clear Enable Bit 508" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRENB507 ,Set/Clear Enable Bit 507" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRENB506 ,Set/Clear Enable Bit 506" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENB505 ,Set/Clear Enable Bit 505" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRENB504 ,Set/Clear Enable Bit 504" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRENB503 ,Set/Clear Enable Bit 503" "Disabled,Enabled" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENB502 ,Set/Clear Enable Bit 502" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRENB501 ,Set/Clear Enable Bit 501" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRENB500 ,Set/Clear Enable Bit 500" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENB499 ,Set/Clear Enable Bit 499" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRENB498 ,Set/Clear Enable Bit 498" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRENB497 ,Set/Clear Enable Bit 497" "Disabled,Enabled" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENB496 ,Set/Clear Enable Bit 496" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRENB495 ,Set/Clear Enable Bit 495" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRENB494 ,Set/Clear Enable Bit 494" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENB493 ,Set/Clear Enable Bit 493" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRENB492 ,Set/Clear Enable Bit 492" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRENB491 ,Set/Clear Enable Bit 491" "Disabled,Enabled" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENB490 ,Set/Clear Enable Bit 490" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRENB489 ,Set/Clear Enable Bit 489" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRENB488 ,Set/Clear Enable Bit 488" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENB487 ,Set/Clear Enable Bit 487" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRENB486 ,Set/Clear Enable Bit 486" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRENB485 ,Set/Clear Enable Bit 485" "Disabled,Enabled" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENB484 ,Set/Clear Enable Bit 484" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRENB483 ,Set/Clear Enable Bit 483" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRENB482 ,Set/Clear Enable Bit 482" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENB481 ,Set/Clear Enable Bit 481" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRENB480 ,Set/Clear Enable Bit 480" "Disabled,Enabled" else rgroup.long 0x013C++0x03 line.long 0x0 "GICD_SET/CLR_ENABLER15,Interrupt Set/Clear Enable Register 15" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(ad:(per.long(spr:0x31F30)&0xFFFC0000)+0x04))&0x0000001F)>=0x10) group.long 0x0140++0x03 line.long 0x0 "GICD_SET/CLR_ENABLER16,Interrupt Set/Clear Enable Register 16" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENB543 ,Set/Clear Enable Bit 543" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRENB542 ,Set/Clear Enable Bit 542" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRENB541 ,Set/Clear Enable Bit 541" "Disabled,Enabled" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENB540 ,Set/Clear Enable Bit 540" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRENB539 ,Set/Clear Enable Bit 539" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRENB538 ,Set/Clear Enable Bit 538" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENB537 ,Set/Clear Enable Bit 537" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRENB536 ,Set/Clear Enable Bit 536" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRENB535 ,Set/Clear Enable Bit 535" "Disabled,Enabled" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENB534 ,Set/Clear Enable Bit 534" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRENB533 ,Set/Clear Enable Bit 533" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRENB532 ,Set/Clear Enable Bit 532" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENB531 ,Set/Clear Enable Bit 531" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRENB530 ,Set/Clear Enable Bit 530" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRENB529 ,Set/Clear Enable Bit 529" "Disabled,Enabled" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENB528 ,Set/Clear Enable Bit 528" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRENB527 ,Set/Clear Enable Bit 527" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRENB526 ,Set/Clear Enable Bit 526" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENB525 ,Set/Clear Enable Bit 525" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRENB524 ,Set/Clear Enable Bit 524" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRENB523 ,Set/Clear Enable Bit 523" "Disabled,Enabled" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENB522 ,Set/Clear Enable Bit 522" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRENB521 ,Set/Clear Enable Bit 521" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRENB520 ,Set/Clear Enable Bit 520" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENB519 ,Set/Clear Enable Bit 519" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRENB518 ,Set/Clear Enable Bit 518" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRENB517 ,Set/Clear Enable Bit 517" "Disabled,Enabled" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENB516 ,Set/Clear Enable Bit 516" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRENB515 ,Set/Clear Enable Bit 515" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRENB514 ,Set/Clear Enable Bit 514" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENB513 ,Set/Clear Enable Bit 513" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRENB512 ,Set/Clear Enable Bit 512" "Disabled,Enabled" else rgroup.long 0x0140++0x03 line.long 0x0 "GICD_SET/CLR_ENABLER16,Interrupt Set/Clear Enable Register 16" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(ad:(per.long(spr:0x31F30)&0xFFFC0000)+0x04))&0x0000001F)>=0x11) group.long 0x0144++0x03 line.long 0x0 "GICD_SET/CLR_ENABLER17,Interrupt Set/Clear Enable Register 17" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENB575 ,Set/Clear Enable Bit 575" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRENB574 ,Set/Clear Enable Bit 574" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRENB573 ,Set/Clear Enable Bit 573" "Disabled,Enabled" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENB572 ,Set/Clear Enable Bit 572" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRENB571 ,Set/Clear Enable Bit 571" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRENB570 ,Set/Clear Enable Bit 570" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENB569 ,Set/Clear Enable Bit 569" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRENB568 ,Set/Clear Enable Bit 568" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRENB567 ,Set/Clear Enable Bit 567" "Disabled,Enabled" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENB566 ,Set/Clear Enable Bit 566" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRENB565 ,Set/Clear Enable Bit 565" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRENB564 ,Set/Clear Enable Bit 564" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENB563 ,Set/Clear Enable Bit 563" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRENB562 ,Set/Clear Enable Bit 562" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRENB561 ,Set/Clear Enable Bit 561" "Disabled,Enabled" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENB560 ,Set/Clear Enable Bit 560" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRENB559 ,Set/Clear Enable Bit 559" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRENB558 ,Set/Clear Enable Bit 558" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENB557 ,Set/Clear Enable Bit 557" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRENB556 ,Set/Clear Enable Bit 556" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRENB555 ,Set/Clear Enable Bit 555" "Disabled,Enabled" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENB554 ,Set/Clear Enable Bit 554" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRENB553 ,Set/Clear Enable Bit 553" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRENB552 ,Set/Clear Enable Bit 552" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENB551 ,Set/Clear Enable Bit 551" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRENB550 ,Set/Clear Enable Bit 550" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRENB549 ,Set/Clear Enable Bit 549" "Disabled,Enabled" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENB548 ,Set/Clear Enable Bit 548" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRENB547 ,Set/Clear Enable Bit 547" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRENB546 ,Set/Clear Enable Bit 546" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENB545 ,Set/Clear Enable Bit 545" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRENB544 ,Set/Clear Enable Bit 544" "Disabled,Enabled" else rgroup.long 0x0144++0x03 line.long 0x0 "GICD_SET/CLR_ENABLER17,Interrupt Set/Clear Enable Register 17" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(ad:(per.long(spr:0x31F30)&0xFFFC0000)+0x04))&0x0000001F)>=0x12) group.long 0x0148++0x03 line.long 0x0 "GICD_SET/CLR_ENABLER18,Interrupt Set/Clear Enable Register 18" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENB607 ,Set/Clear Enable Bit 607" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRENB606 ,Set/Clear Enable Bit 606" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRENB605 ,Set/Clear Enable Bit 605" "Disabled,Enabled" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENB604 ,Set/Clear Enable Bit 604" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRENB603 ,Set/Clear Enable Bit 603" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRENB602 ,Set/Clear Enable Bit 602" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENB601 ,Set/Clear Enable Bit 601" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRENB600 ,Set/Clear Enable Bit 600" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRENB599 ,Set/Clear Enable Bit 599" "Disabled,Enabled" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENB598 ,Set/Clear Enable Bit 598" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRENB597 ,Set/Clear Enable Bit 597" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRENB596 ,Set/Clear Enable Bit 596" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENB595 ,Set/Clear Enable Bit 595" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRENB594 ,Set/Clear Enable Bit 594" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRENB593 ,Set/Clear Enable Bit 593" "Disabled,Enabled" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENB592 ,Set/Clear Enable Bit 592" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRENB591 ,Set/Clear Enable Bit 591" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRENB590 ,Set/Clear Enable Bit 590" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENB589 ,Set/Clear Enable Bit 589" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRENB588 ,Set/Clear Enable Bit 588" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRENB587 ,Set/Clear Enable Bit 587" "Disabled,Enabled" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENB586 ,Set/Clear Enable Bit 586" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRENB585 ,Set/Clear Enable Bit 585" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRENB584 ,Set/Clear Enable Bit 584" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENB583 ,Set/Clear Enable Bit 583" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRENB582 ,Set/Clear Enable Bit 582" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRENB581 ,Set/Clear Enable Bit 581" "Disabled,Enabled" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENB580 ,Set/Clear Enable Bit 580" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRENB579 ,Set/Clear Enable Bit 579" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRENB578 ,Set/Clear Enable Bit 578" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENB577 ,Set/Clear Enable Bit 577" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRENB576 ,Set/Clear Enable Bit 576" "Disabled,Enabled" else rgroup.long 0x0148++0x03 line.long 0x0 "GICD_SET/CLR_ENABLER18,Interrupt Set/Clear Enable Register 18" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(ad:(per.long(spr:0x31F30)&0xFFFC0000)+0x04))&0x0000001F)>=0x13) group.long 0x014C++0x03 line.long 0x0 "GICD_SET/CLR_ENABLER19,Interrupt Set/Clear Enable Register 19" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENB639 ,Set/Clear Enable Bit 639" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRENB638 ,Set/Clear Enable Bit 638" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRENB637 ,Set/Clear Enable Bit 637" "Disabled,Enabled" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENB636 ,Set/Clear Enable Bit 636" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRENB635 ,Set/Clear Enable Bit 635" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRENB634 ,Set/Clear Enable Bit 634" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENB633 ,Set/Clear Enable Bit 633" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRENB632 ,Set/Clear Enable Bit 632" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRENB631 ,Set/Clear Enable Bit 631" "Disabled,Enabled" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENB630 ,Set/Clear Enable Bit 630" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRENB629 ,Set/Clear Enable Bit 629" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRENB628 ,Set/Clear Enable Bit 628" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENB627 ,Set/Clear Enable Bit 627" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRENB626 ,Set/Clear Enable Bit 626" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRENB625 ,Set/Clear Enable Bit 625" "Disabled,Enabled" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENB624 ,Set/Clear Enable Bit 624" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRENB623 ,Set/Clear Enable Bit 623" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRENB622 ,Set/Clear Enable Bit 622" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENB621 ,Set/Clear Enable Bit 621" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRENB620 ,Set/Clear Enable Bit 620" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRENB619 ,Set/Clear Enable Bit 619" "Disabled,Enabled" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENB618 ,Set/Clear Enable Bit 618" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRENB617 ,Set/Clear Enable Bit 617" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRENB616 ,Set/Clear Enable Bit 616" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENB615 ,Set/Clear Enable Bit 615" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRENB614 ,Set/Clear Enable Bit 614" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRENB613 ,Set/Clear Enable Bit 613" "Disabled,Enabled" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENB612 ,Set/Clear Enable Bit 612" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRENB611 ,Set/Clear Enable Bit 611" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRENB610 ,Set/Clear Enable Bit 610" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENB609 ,Set/Clear Enable Bit 609" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRENB608 ,Set/Clear Enable Bit 608" "Disabled,Enabled" else rgroup.long 0x014C++0x03 line.long 0x0 "GICD_SET/CLR_ENABLER19,Interrupt Set/Clear Enable Register 19" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(ad:(per.long(spr:0x31F30)&0xFFFC0000)+0x04))&0x0000001F)>=0x14) group.long 0x0150++0x03 line.long 0x0 "GICD_SET/CLR_ENABLER20,Interrupt Set/Clear Enable Register 20" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENB671 ,Set/Clear Enable Bit 671" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRENB670 ,Set/Clear Enable Bit 670" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRENB669 ,Set/Clear Enable Bit 669" "Disabled,Enabled" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENB668 ,Set/Clear Enable Bit 668" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRENB667 ,Set/Clear Enable Bit 667" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRENB666 ,Set/Clear Enable Bit 666" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENB665 ,Set/Clear Enable Bit 665" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRENB664 ,Set/Clear Enable Bit 664" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRENB663 ,Set/Clear Enable Bit 663" "Disabled,Enabled" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENB662 ,Set/Clear Enable Bit 662" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRENB661 ,Set/Clear Enable Bit 661" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRENB660 ,Set/Clear Enable Bit 660" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENB659 ,Set/Clear Enable Bit 659" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRENB658 ,Set/Clear Enable Bit 658" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRENB657 ,Set/Clear Enable Bit 657" "Disabled,Enabled" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENB656 ,Set/Clear Enable Bit 656" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRENB655 ,Set/Clear Enable Bit 655" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRENB654 ,Set/Clear Enable Bit 654" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENB653 ,Set/Clear Enable Bit 653" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRENB652 ,Set/Clear Enable Bit 652" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRENB651 ,Set/Clear Enable Bit 651" "Disabled,Enabled" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENB650 ,Set/Clear Enable Bit 650" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRENB649 ,Set/Clear Enable Bit 649" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRENB648 ,Set/Clear Enable Bit 648" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENB647 ,Set/Clear Enable Bit 647" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRENB646 ,Set/Clear Enable Bit 646" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRENB645 ,Set/Clear Enable Bit 645" "Disabled,Enabled" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENB644 ,Set/Clear Enable Bit 644" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRENB643 ,Set/Clear Enable Bit 643" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRENB642 ,Set/Clear Enable Bit 642" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENB641 ,Set/Clear Enable Bit 641" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRENB640 ,Set/Clear Enable Bit 640" "Disabled,Enabled" else rgroup.long 0x0150++0x03 line.long 0x0 "GICD_SET/CLR_ENABLER20,Interrupt Set/Clear Enable Register 20" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(ad:(per.long(spr:0x31F30)&0xFFFC0000)+0x04))&0x0000001F)>=0x15) group.long 0x0154++0x03 line.long 0x0 "GICD_SET/CLR_ENABLER21,Interrupt Set/Clear Enable Register 21" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENB703 ,Set/Clear Enable Bit 703" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRENB702 ,Set/Clear Enable Bit 702" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRENB701 ,Set/Clear Enable Bit 701" "Disabled,Enabled" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENB700 ,Set/Clear Enable Bit 700" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRENB699 ,Set/Clear Enable Bit 699" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRENB698 ,Set/Clear Enable Bit 698" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENB697 ,Set/Clear Enable Bit 697" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRENB696 ,Set/Clear Enable Bit 696" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRENB695 ,Set/Clear Enable Bit 695" "Disabled,Enabled" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENB694 ,Set/Clear Enable Bit 694" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRENB693 ,Set/Clear Enable Bit 693" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRENB692 ,Set/Clear Enable Bit 692" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENB691 ,Set/Clear Enable Bit 691" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRENB690 ,Set/Clear Enable Bit 690" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRENB689 ,Set/Clear Enable Bit 689" "Disabled,Enabled" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENB688 ,Set/Clear Enable Bit 688" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRENB687 ,Set/Clear Enable Bit 687" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRENB686 ,Set/Clear Enable Bit 686" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENB685 ,Set/Clear Enable Bit 685" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRENB684 ,Set/Clear Enable Bit 684" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRENB683 ,Set/Clear Enable Bit 683" "Disabled,Enabled" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENB682 ,Set/Clear Enable Bit 682" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRENB681 ,Set/Clear Enable Bit 681" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRENB680 ,Set/Clear Enable Bit 680" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENB679 ,Set/Clear Enable Bit 679" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRENB678 ,Set/Clear Enable Bit 678" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRENB677 ,Set/Clear Enable Bit 677" "Disabled,Enabled" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENB676 ,Set/Clear Enable Bit 676" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRENB675 ,Set/Clear Enable Bit 675" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRENB674 ,Set/Clear Enable Bit 674" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENB673 ,Set/Clear Enable Bit 673" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRENB672 ,Set/Clear Enable Bit 672" "Disabled,Enabled" else rgroup.long 0x0154++0x03 line.long 0x0 "GICD_SET/CLR_ENABLER21,Interrupt Set/Clear Enable Register 21" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(ad:(per.long(spr:0x31F30)&0xFFFC0000)+0x04))&0x0000001F)>=0x16) group.long 0x0158++0x03 line.long 0x0 "GICD_SET/CLR_ENABLER22,Interrupt Set/Clear Enable Register 22" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENB735 ,Set/Clear Enable Bit 735" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRENB734 ,Set/Clear Enable Bit 734" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRENB733 ,Set/Clear Enable Bit 733" "Disabled,Enabled" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENB732 ,Set/Clear Enable Bit 732" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRENB731 ,Set/Clear Enable Bit 731" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRENB730 ,Set/Clear Enable Bit 730" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENB729 ,Set/Clear Enable Bit 729" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRENB728 ,Set/Clear Enable Bit 728" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRENB727 ,Set/Clear Enable Bit 727" "Disabled,Enabled" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENB726 ,Set/Clear Enable Bit 726" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRENB725 ,Set/Clear Enable Bit 725" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRENB724 ,Set/Clear Enable Bit 724" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENB723 ,Set/Clear Enable Bit 723" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRENB722 ,Set/Clear Enable Bit 722" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRENB721 ,Set/Clear Enable Bit 721" "Disabled,Enabled" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENB720 ,Set/Clear Enable Bit 720" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRENB719 ,Set/Clear Enable Bit 719" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRENB718 ,Set/Clear Enable Bit 718" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENB717 ,Set/Clear Enable Bit 717" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRENB716 ,Set/Clear Enable Bit 716" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRENB715 ,Set/Clear Enable Bit 715" "Disabled,Enabled" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENB714 ,Set/Clear Enable Bit 714" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRENB713 ,Set/Clear Enable Bit 713" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRENB712 ,Set/Clear Enable Bit 712" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENB711 ,Set/Clear Enable Bit 711" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRENB710 ,Set/Clear Enable Bit 710" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRENB709 ,Set/Clear Enable Bit 709" "Disabled,Enabled" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENB708 ,Set/Clear Enable Bit 708" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRENB707 ,Set/Clear Enable Bit 707" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRENB706 ,Set/Clear Enable Bit 706" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENB705 ,Set/Clear Enable Bit 705" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRENB704 ,Set/Clear Enable Bit 704" "Disabled,Enabled" else rgroup.long 0x0158++0x03 line.long 0x0 "GICD_SET/CLR_ENABLER22,Interrupt Set/Clear Enable Register 22" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(ad:(per.long(spr:0x31F30)&0xFFFC0000)+0x04))&0x0000001F)>=0x17) group.long 0x015C++0x03 line.long 0x0 "GICD_SET/CLR_ENABLER23,Interrupt Set/Clear Enable Register 23" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENB767 ,Set/Clear Enable Bit 767" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRENB766 ,Set/Clear Enable Bit 766" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRENB765 ,Set/Clear Enable Bit 765" "Disabled,Enabled" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENB764 ,Set/Clear Enable Bit 764" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRENB763 ,Set/Clear Enable Bit 763" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRENB762 ,Set/Clear Enable Bit 762" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENB761 ,Set/Clear Enable Bit 761" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRENB760 ,Set/Clear Enable Bit 760" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRENB759 ,Set/Clear Enable Bit 759" "Disabled,Enabled" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENB758 ,Set/Clear Enable Bit 758" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRENB757 ,Set/Clear Enable Bit 757" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRENB756 ,Set/Clear Enable Bit 756" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENB755 ,Set/Clear Enable Bit 755" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRENB754 ,Set/Clear Enable Bit 754" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRENB753 ,Set/Clear Enable Bit 753" "Disabled,Enabled" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENB752 ,Set/Clear Enable Bit 752" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRENB751 ,Set/Clear Enable Bit 751" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRENB750 ,Set/Clear Enable Bit 750" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENB749 ,Set/Clear Enable Bit 749" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRENB748 ,Set/Clear Enable Bit 748" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRENB747 ,Set/Clear Enable Bit 747" "Disabled,Enabled" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENB746 ,Set/Clear Enable Bit 746" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRENB745 ,Set/Clear Enable Bit 745" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRENB744 ,Set/Clear Enable Bit 744" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENB743 ,Set/Clear Enable Bit 743" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRENB742 ,Set/Clear Enable Bit 742" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRENB741 ,Set/Clear Enable Bit 741" "Disabled,Enabled" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENB740 ,Set/Clear Enable Bit 740" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRENB739 ,Set/Clear Enable Bit 739" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRENB738 ,Set/Clear Enable Bit 738" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENB737 ,Set/Clear Enable Bit 737" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRENB736 ,Set/Clear Enable Bit 736" "Disabled,Enabled" else rgroup.long 0x015C++0x03 line.long 0x0 "GICD_SET/CLR_ENABLER23,Interrupt Set/Clear Enable Register 23" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(ad:(per.long(spr:0x31F30)&0xFFFC0000)+0x04))&0x0000001F)>=0x18) group.long 0x0160++0x03 line.long 0x0 "GICD_SET/CLR_ENABLER24,Interrupt Set/Clear Enable Register 24" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENB799 ,Set/Clear Enable Bit 799" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRENB798 ,Set/Clear Enable Bit 798" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRENB797 ,Set/Clear Enable Bit 797" "Disabled,Enabled" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENB796 ,Set/Clear Enable Bit 796" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRENB795 ,Set/Clear Enable Bit 795" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRENB794 ,Set/Clear Enable Bit 794" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENB793 ,Set/Clear Enable Bit 793" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRENB792 ,Set/Clear Enable Bit 792" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRENB791 ,Set/Clear Enable Bit 791" "Disabled,Enabled" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENB790 ,Set/Clear Enable Bit 790" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRENB789 ,Set/Clear Enable Bit 789" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRENB788 ,Set/Clear Enable Bit 788" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENB787 ,Set/Clear Enable Bit 787" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRENB786 ,Set/Clear Enable Bit 786" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRENB785 ,Set/Clear Enable Bit 785" "Disabled,Enabled" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENB784 ,Set/Clear Enable Bit 784" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRENB783 ,Set/Clear Enable Bit 783" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRENB782 ,Set/Clear Enable Bit 782" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENB781 ,Set/Clear Enable Bit 781" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRENB780 ,Set/Clear Enable Bit 780" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRENB779 ,Set/Clear Enable Bit 779" "Disabled,Enabled" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENB778 ,Set/Clear Enable Bit 778" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRENB777 ,Set/Clear Enable Bit 777" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRENB776 ,Set/Clear Enable Bit 776" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENB775 ,Set/Clear Enable Bit 775" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRENB774 ,Set/Clear Enable Bit 774" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRENB773 ,Set/Clear Enable Bit 773" "Disabled,Enabled" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENB772 ,Set/Clear Enable Bit 772" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRENB771 ,Set/Clear Enable Bit 771" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRENB770 ,Set/Clear Enable Bit 770" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENB769 ,Set/Clear Enable Bit 769" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRENB768 ,Set/Clear Enable Bit 768" "Disabled,Enabled" else rgroup.long 0x0160++0x03 line.long 0x0 "GICD_SET/CLR_ENABLER24,Interrupt Set/Clear Enable Register 24" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(ad:(per.long(spr:0x31F30)&0xFFFC0000)+0x04))&0x0000001F)>=0x19) group.long 0x0164++0x03 line.long 0x0 "GICD_SET/CLR_ENABLER25,Interrupt Set/Clear Enable Register 25" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENB831 ,Set/Clear Enable Bit 831" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRENB830 ,Set/Clear Enable Bit 830" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRENB829 ,Set/Clear Enable Bit 829" "Disabled,Enabled" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENB828 ,Set/Clear Enable Bit 828" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRENB827 ,Set/Clear Enable Bit 827" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRENB826 ,Set/Clear Enable Bit 826" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENB825 ,Set/Clear Enable Bit 825" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRENB824 ,Set/Clear Enable Bit 824" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRENB823 ,Set/Clear Enable Bit 823" "Disabled,Enabled" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENB822 ,Set/Clear Enable Bit 822" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRENB821 ,Set/Clear Enable Bit 821" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRENB820 ,Set/Clear Enable Bit 820" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENB819 ,Set/Clear Enable Bit 819" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRENB818 ,Set/Clear Enable Bit 818" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRENB817 ,Set/Clear Enable Bit 817" "Disabled,Enabled" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENB816 ,Set/Clear Enable Bit 816" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRENB815 ,Set/Clear Enable Bit 815" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRENB814 ,Set/Clear Enable Bit 814" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENB813 ,Set/Clear Enable Bit 813" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRENB812 ,Set/Clear Enable Bit 812" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRENB811 ,Set/Clear Enable Bit 811" "Disabled,Enabled" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENB810 ,Set/Clear Enable Bit 810" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRENB809 ,Set/Clear Enable Bit 809" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRENB808 ,Set/Clear Enable Bit 808" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENB807 ,Set/Clear Enable Bit 807" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRENB806 ,Set/Clear Enable Bit 806" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRENB805 ,Set/Clear Enable Bit 805" "Disabled,Enabled" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENB804 ,Set/Clear Enable Bit 804" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRENB803 ,Set/Clear Enable Bit 803" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRENB802 ,Set/Clear Enable Bit 802" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENB801 ,Set/Clear Enable Bit 801" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRENB800 ,Set/Clear Enable Bit 800" "Disabled,Enabled" else rgroup.long 0x0164++0x03 line.long 0x0 "GICD_SET/CLR_ENABLER25,Interrupt Set/Clear Enable Register 25" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(ad:(per.long(spr:0x31F30)&0xFFFC0000)+0x04))&0x0000001F)>=0x1A) group.long 0x0168++0x03 line.long 0x0 "GICD_SET/CLR_ENABLER26,Interrupt Set/Clear Enable Register 26" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENB863 ,Set/Clear Enable Bit 863" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRENB862 ,Set/Clear Enable Bit 862" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRENB861 ,Set/Clear Enable Bit 861" "Disabled,Enabled" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENB860 ,Set/Clear Enable Bit 860" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRENB859 ,Set/Clear Enable Bit 859" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRENB858 ,Set/Clear Enable Bit 858" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENB857 ,Set/Clear Enable Bit 857" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRENB856 ,Set/Clear Enable Bit 856" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRENB855 ,Set/Clear Enable Bit 855" "Disabled,Enabled" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENB854 ,Set/Clear Enable Bit 854" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRENB853 ,Set/Clear Enable Bit 853" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRENB852 ,Set/Clear Enable Bit 852" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENB851 ,Set/Clear Enable Bit 851" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRENB850 ,Set/Clear Enable Bit 850" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRENB849 ,Set/Clear Enable Bit 849" "Disabled,Enabled" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENB848 ,Set/Clear Enable Bit 848" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRENB847 ,Set/Clear Enable Bit 847" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRENB846 ,Set/Clear Enable Bit 846" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENB845 ,Set/Clear Enable Bit 845" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRENB844 ,Set/Clear Enable Bit 844" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRENB843 ,Set/Clear Enable Bit 843" "Disabled,Enabled" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENB842 ,Set/Clear Enable Bit 842" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRENB841 ,Set/Clear Enable Bit 841" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRENB840 ,Set/Clear Enable Bit 840" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENB839 ,Set/Clear Enable Bit 839" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRENB838 ,Set/Clear Enable Bit 838" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRENB837 ,Set/Clear Enable Bit 837" "Disabled,Enabled" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENB836 ,Set/Clear Enable Bit 836" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRENB835 ,Set/Clear Enable Bit 835" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRENB834 ,Set/Clear Enable Bit 834" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENB833 ,Set/Clear Enable Bit 833" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRENB832 ,Set/Clear Enable Bit 832" "Disabled,Enabled" else rgroup.long 0x0168++0x03 line.long 0x0 "GICD_SET/CLR_ENABLER26,Interrupt Set/Clear Enable Register 26" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(ad:(per.long(spr:0x31F30)&0xFFFC0000)+0x04))&0x0000001F)>=0x1B) group.long 0x016C++0x03 line.long 0x0 "GICD_SET/CLR_ENABLER27,Interrupt Set/Clear Enable Register 27" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENB895 ,Set/Clear Enable Bit 895" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRENB894 ,Set/Clear Enable Bit 894" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRENB893 ,Set/Clear Enable Bit 893" "Disabled,Enabled" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENB892 ,Set/Clear Enable Bit 892" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRENB891 ,Set/Clear Enable Bit 891" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRENB890 ,Set/Clear Enable Bit 890" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENB889 ,Set/Clear Enable Bit 889" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRENB888 ,Set/Clear Enable Bit 888" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRENB887 ,Set/Clear Enable Bit 887" "Disabled,Enabled" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENB886 ,Set/Clear Enable Bit 886" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRENB885 ,Set/Clear Enable Bit 885" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRENB884 ,Set/Clear Enable Bit 884" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENB883 ,Set/Clear Enable Bit 883" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRENB882 ,Set/Clear Enable Bit 882" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRENB881 ,Set/Clear Enable Bit 881" "Disabled,Enabled" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENB880 ,Set/Clear Enable Bit 880" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRENB879 ,Set/Clear Enable Bit 879" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRENB878 ,Set/Clear Enable Bit 878" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENB877 ,Set/Clear Enable Bit 877" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRENB876 ,Set/Clear Enable Bit 876" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRENB875 ,Set/Clear Enable Bit 875" "Disabled,Enabled" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENB874 ,Set/Clear Enable Bit 874" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRENB873 ,Set/Clear Enable Bit 873" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRENB872 ,Set/Clear Enable Bit 872" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENB871 ,Set/Clear Enable Bit 871" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRENB870 ,Set/Clear Enable Bit 870" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRENB869 ,Set/Clear Enable Bit 869" "Disabled,Enabled" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENB868 ,Set/Clear Enable Bit 868" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRENB867 ,Set/Clear Enable Bit 867" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRENB866 ,Set/Clear Enable Bit 866" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENB865 ,Set/Clear Enable Bit 865" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRENB864 ,Set/Clear Enable Bit 864" "Disabled,Enabled" else rgroup.long 0x016C++0x03 line.long 0x0 "GICD_SET/CLR_ENABLER27,Interrupt Set/Clear Enable Register 27" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(ad:(per.long(spr:0x31F30)&0xFFFC0000)+0x04))&0x0000001F)>=0x1C) group.long 0x0170++0x03 line.long 0x0 "GICD_SET/CLR_ENABLER28,Interrupt Set/Clear Enable Register 28" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENB927 ,Set/Clear Enable Bit 927" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRENB926 ,Set/Clear Enable Bit 926" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRENB925 ,Set/Clear Enable Bit 925" "Disabled,Enabled" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENB924 ,Set/Clear Enable Bit 924" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRENB923 ,Set/Clear Enable Bit 923" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRENB922 ,Set/Clear Enable Bit 922" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENB921 ,Set/Clear Enable Bit 921" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRENB920 ,Set/Clear Enable Bit 920" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRENB919 ,Set/Clear Enable Bit 919" "Disabled,Enabled" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENB918 ,Set/Clear Enable Bit 918" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRENB917 ,Set/Clear Enable Bit 917" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRENB916 ,Set/Clear Enable Bit 916" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENB915 ,Set/Clear Enable Bit 915" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRENB914 ,Set/Clear Enable Bit 914" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRENB913 ,Set/Clear Enable Bit 913" "Disabled,Enabled" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENB912 ,Set/Clear Enable Bit 912" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRENB911 ,Set/Clear Enable Bit 911" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRENB910 ,Set/Clear Enable Bit 910" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENB909 ,Set/Clear Enable Bit 909" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRENB908 ,Set/Clear Enable Bit 908" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRENB907 ,Set/Clear Enable Bit 907" "Disabled,Enabled" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENB906 ,Set/Clear Enable Bit 906" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRENB905 ,Set/Clear Enable Bit 905" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRENB904 ,Set/Clear Enable Bit 904" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENB903 ,Set/Clear Enable Bit 903" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRENB902 ,Set/Clear Enable Bit 902" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRENB901 ,Set/Clear Enable Bit 901" "Disabled,Enabled" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENB900 ,Set/Clear Enable Bit 900" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRENB899 ,Set/Clear Enable Bit 899" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRENB898 ,Set/Clear Enable Bit 898" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENB897 ,Set/Clear Enable Bit 897" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRENB896 ,Set/Clear Enable Bit 896" "Disabled,Enabled" else rgroup.long 0x0170++0x03 line.long 0x0 "GICD_SET/CLR_ENABLER28,Interrupt Set/Clear Enable Register 28" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(ad:(per.long(spr:0x31F30)&0xFFFC0000)+0x04))&0x0000001F)>=0x1D) group.long 0x0174++0x03 line.long 0x0 "GICD_SET/CLR_ENABLER29,Interrupt Set/Clear Enable Register 29" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENB959 ,Set/Clear Enable Bit 959" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRENB958 ,Set/Clear Enable Bit 958" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRENB957 ,Set/Clear Enable Bit 957" "Disabled,Enabled" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENB956 ,Set/Clear Enable Bit 956" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRENB955 ,Set/Clear Enable Bit 955" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRENB954 ,Set/Clear Enable Bit 954" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENB953 ,Set/Clear Enable Bit 953" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRENB952 ,Set/Clear Enable Bit 952" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRENB951 ,Set/Clear Enable Bit 951" "Disabled,Enabled" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENB950 ,Set/Clear Enable Bit 950" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRENB949 ,Set/Clear Enable Bit 949" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRENB948 ,Set/Clear Enable Bit 948" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENB947 ,Set/Clear Enable Bit 947" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRENB946 ,Set/Clear Enable Bit 946" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRENB945 ,Set/Clear Enable Bit 945" "Disabled,Enabled" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENB944 ,Set/Clear Enable Bit 944" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRENB943 ,Set/Clear Enable Bit 943" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRENB942 ,Set/Clear Enable Bit 942" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENB941 ,Set/Clear Enable Bit 941" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRENB940 ,Set/Clear Enable Bit 940" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRENB939 ,Set/Clear Enable Bit 939" "Disabled,Enabled" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENB938 ,Set/Clear Enable Bit 938" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRENB937 ,Set/Clear Enable Bit 937" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRENB936 ,Set/Clear Enable Bit 936" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENB935 ,Set/Clear Enable Bit 935" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRENB934 ,Set/Clear Enable Bit 934" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRENB933 ,Set/Clear Enable Bit 933" "Disabled,Enabled" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENB932 ,Set/Clear Enable Bit 932" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRENB931 ,Set/Clear Enable Bit 931" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRENB930 ,Set/Clear Enable Bit 930" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENB929 ,Set/Clear Enable Bit 929" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRENB928 ,Set/Clear Enable Bit 928" "Disabled,Enabled" else rgroup.long 0x0174++0x03 line.long 0x0 "GICD_SET/CLR_ENABLER29,Interrupt Set/Clear Enable Register 29" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(ad:(per.long(spr:0x31F30)&0xFFFC0000)+0x04))&0x0000001F)>=0x1E) group.long 0x0178++0x03 line.long 0x0 "GICD_SET/CLR_ENABLER30,Interrupt Set/Clear Enable Register 30" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRENB991 ,Set/Clear Enable Bit 991" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRENB990 ,Set/Clear Enable Bit 990" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRENB989 ,Set/Clear Enable Bit 989" "Disabled,Enabled" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRENB988 ,Set/Clear Enable Bit 988" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRENB987 ,Set/Clear Enable Bit 987" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRENB986 ,Set/Clear Enable Bit 986" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENB985 ,Set/Clear Enable Bit 985" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRENB984 ,Set/Clear Enable Bit 984" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRENB983 ,Set/Clear Enable Bit 983" "Disabled,Enabled" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENB982 ,Set/Clear Enable Bit 982" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRENB981 ,Set/Clear Enable Bit 981" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRENB980 ,Set/Clear Enable Bit 980" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENB979 ,Set/Clear Enable Bit 979" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRENB978 ,Set/Clear Enable Bit 978" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRENB977 ,Set/Clear Enable Bit 977" "Disabled,Enabled" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENB976 ,Set/Clear Enable Bit 976" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRENB975 ,Set/Clear Enable Bit 975" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRENB974 ,Set/Clear Enable Bit 974" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENB973 ,Set/Clear Enable Bit 973" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRENB972 ,Set/Clear Enable Bit 972" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRENB971 ,Set/Clear Enable Bit 971" "Disabled,Enabled" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENB970 ,Set/Clear Enable Bit 970" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRENB969 ,Set/Clear Enable Bit 969" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRENB968 ,Set/Clear Enable Bit 968" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENB967 ,Set/Clear Enable Bit 967" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRENB966 ,Set/Clear Enable Bit 966" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRENB965 ,Set/Clear Enable Bit 965" "Disabled,Enabled" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENB964 ,Set/Clear Enable Bit 964" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRENB963 ,Set/Clear Enable Bit 963" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRENB962 ,Set/Clear Enable Bit 962" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENB961 ,Set/Clear Enable Bit 961" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRENB960 ,Set/Clear Enable Bit 960" "Disabled,Enabled" else rgroup.long 0x0178++0x03 line.long 0x0 "GICD_SET/CLR_ENABLER30,Interrupt Set/Clear Enable Register 30" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(ad:(per.long(spr:0x31F30)&0xFFFC0000)+0x04))&0x0000001F)==0x1F) group.long 0x017C++0x03 line.long 0x0 "GICD_SET/CLR_ENABLER31,Interrupt Set/Clear Enable Register 31" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRENB1019 ,Set/Clear Enable Bit 1019" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRENB1018 ,Set/Clear Enable Bit 1018" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRENB1017 ,Set/Clear Enable Bit 1017" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRENB1016 ,Set/Clear Enable Bit 1016" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRENB1015 ,Set/Clear Enable Bit 1015" "Disabled,Enabled" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRENB1014 ,Set/Clear Enable Bit 1014" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRENB1013 ,Set/Clear Enable Bit 1013" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRENB1012 ,Set/Clear Enable Bit 1012" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRENB1011 ,Set/Clear Enable Bit 1011" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRENB1010 ,Set/Clear Enable Bit 1010" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRENB1009 ,Set/Clear Enable Bit 1009" "Disabled,Enabled" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRENB1008 ,Set/Clear Enable Bit 1008" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRENB1007 ,Set/Clear Enable Bit 1007" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRENB1006 ,Set/Clear Enable Bit 1006" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRENB1005 ,Set/Clear Enable Bit 1005" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRENB1004 ,Set/Clear Enable Bit 1004" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRENB1003 ,Set/Clear Enable Bit 1003" "Disabled,Enabled" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRENB1002 ,Set/Clear Enable Bit 1002" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRENB1001 ,Set/Clear Enable Bit 1001" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRENB1000 ,Set/Clear Enable Bit 1000" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRENB999 ,Set/Clear Enable Bit 999" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRENB998 ,Set/Clear Enable Bit 998" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRENB997 ,Set/Clear Enable Bit 997" "Disabled,Enabled" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRENB996 ,Set/Clear Enable Bit 996" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRENB995 ,Set/Clear Enable Bit 995" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRENB994 ,Set/Clear Enable Bit 994" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRENB993 ,Set/Clear Enable Bit 993" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRENB992 ,Set/Clear Enable Bit 992" "Disabled,Enabled" else rgroup.long 0x017C++0x03 line.long 0x0 "GICD_SET/CLR_ENABLER31,Interrupt Set/Clear Enable Register 31" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif tree.end width 22. tree "Set/Clear Pending Registers" group.long 0x0200++0x03 line.long 0x0 "GICD_SET/CLR_PENDR0,Interrupt Set/Clear Pending Register 0" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEND31 ,Set/Clear Pending Bit 31" "Not pending,Pending" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRPEND30 ,Set/Clear Pending Bit 30" "Not pending,Pending" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRPEND29 ,Set/Clear Pending Bit 29" "Not pending,Pending" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEND28 ,Set/Clear Pending Bit 28" "Not pending,Pending" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRPEND27 ,Set/Clear Pending Bit 27" "Not pending,Pending" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRPEND26 ,Set/Clear Pending Bit 26" "Not pending,Pending" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEND25 ,Set/Clear Pending Bit 25" "Not pending,Pending" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRPEND24 ,Set/Clear Pending Bit 24" "Not pending,Pending" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRPEND23 ,Set/Clear Pending Bit 23" "Not pending,Pending" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEND22 ,Set/Clear Pending Bit 22" "Not pending,Pending" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRPEND21 ,Set/Clear Pending Bit 21" "Not pending,Pending" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRPEND20 ,Set/Clear Pending Bit 20" "Not pending,Pending" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEND19 ,Set/Clear Pending Bit 19" "Not pending,Pending" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRPEND18 ,Set/Clear Pending Bit 18" "Not pending,Pending" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRPEND17 ,Set/Clear Pending Bit 17" "Not pending,Pending" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEND16 ,Set/Clear Pending Bit 16" "Not pending,Pending" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRPEND15 ,Set/Clear Pending Bit 15" "Not pending,Pending" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRPEND14 ,Set/Clear Pending Bit 14" "Not pending,Pending" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEND13 ,Set/Clear Pending Bit 13" "Not pending,Pending" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRPEND12 ,Set/Clear Pending Bit 12" "Not pending,Pending" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRPEND11 ,Set/Clear Pending Bit 11" "Not pending,Pending" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEND10 ,Set/Clear Pending Bit 10" "Not pending,Pending" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRPEND9 ,Set/Clear Pending Bit 9" "Not pending,Pending" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRPEND8 ,Set/Clear Pending Bit 8" "Not pending,Pending" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEND7 ,Set/Clear Pending Bit 7" "Not pending,Pending" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRPEND6 ,Set/Clear Pending Bit 6" "Not pending,Pending" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRPEND5 ,Set/Clear Pending Bit 5" "Not pending,Pending" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEND4 ,Set/Clear Pending Bit 4" "Not pending,Pending" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRPEND3 ,Set/Clear Pending Bit 3" "Not pending,Pending" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRPEND2 ,Set/Clear Pending Bit 2" "Not pending,Pending" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEND1 ,Set/Clear Pending Bit 1" "Not pending,Pending" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRPEND0 ,Set/Clear Pending Bit 0" "Not pending,Pending" if (((per.l(ad:(per.long(spr:0x31F30)&0xFFFC0000)+0x04))&0x0000001F)>=0x01) group.long 0x0204++0x03 line.long 0x0 "GICD_SET/CLR_PENDR1,Interrupt Set/Clear Pending Register 1" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEND63 ,Set/Clear Pending Bit 63" "Not pending,Pending" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRPEND62 ,Set/Clear Pending Bit 62" "Not pending,Pending" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRPEND61 ,Set/Clear Pending Bit 61" "Not pending,Pending" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEND60 ,Set/Clear Pending Bit 60" "Not pending,Pending" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRPEND59 ,Set/Clear Pending Bit 59" "Not pending,Pending" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRPEND58 ,Set/Clear Pending Bit 58" "Not pending,Pending" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEND57 ,Set/Clear Pending Bit 57" "Not pending,Pending" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRPEND56 ,Set/Clear Pending Bit 56" "Not pending,Pending" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRPEND55 ,Set/Clear Pending Bit 55" "Not pending,Pending" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEND54 ,Set/Clear Pending Bit 54" "Not pending,Pending" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRPEND53 ,Set/Clear Pending Bit 53" "Not pending,Pending" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRPEND52 ,Set/Clear Pending Bit 52" "Not pending,Pending" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEND51 ,Set/Clear Pending Bit 51" "Not pending,Pending" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRPEND50 ,Set/Clear Pending Bit 50" "Not pending,Pending" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRPEND49 ,Set/Clear Pending Bit 49" "Not pending,Pending" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEND48 ,Set/Clear Pending Bit 48" "Not pending,Pending" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRPEND47 ,Set/Clear Pending Bit 47" "Not pending,Pending" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRPEND46 ,Set/Clear Pending Bit 46" "Not pending,Pending" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEND45 ,Set/Clear Pending Bit 45" "Not pending,Pending" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRPEND44 ,Set/Clear Pending Bit 44" "Not pending,Pending" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRPEND43 ,Set/Clear Pending Bit 43" "Not pending,Pending" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEND42 ,Set/Clear Pending Bit 42" "Not pending,Pending" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRPEND41 ,Set/Clear Pending Bit 41" "Not pending,Pending" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRPEND40 ,Set/Clear Pending Bit 40" "Not pending,Pending" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEND39 ,Set/Clear Pending Bit 39" "Not pending,Pending" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRPEND38 ,Set/Clear Pending Bit 38" "Not pending,Pending" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRPEND37 ,Set/Clear Pending Bit 37" "Not pending,Pending" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEND36 ,Set/Clear Pending Bit 36" "Not pending,Pending" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRPEND35 ,Set/Clear Pending Bit 35" "Not pending,Pending" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRPEND34 ,Set/Clear Pending Bit 34" "Not pending,Pending" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEND33 ,Set/Clear Pending Bit 33" "Not pending,Pending" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRPEND32 ,Set/Clear Pending Bit 32" "Not pending,Pending" else rgroup.long 0x0204++0x03 line.long 0x0 "GICD_SET/CLR_PENDR1,Interrupt Set/Clear Pending Register 1" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(ad:(per.long(spr:0x31F30)&0xFFFC0000)+0x04))&0x0000001F)>=0x02) group.long 0x0208++0x03 line.long 0x0 "GICD_SET/CLR_PENDR2,Interrupt Set/Clear Pending Register 2" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEND95 ,Set/Clear Pending Bit 95" "Not pending,Pending" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRPEND94 ,Set/Clear Pending Bit 94" "Not pending,Pending" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRPEND93 ,Set/Clear Pending Bit 93" "Not pending,Pending" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEND92 ,Set/Clear Pending Bit 92" "Not pending,Pending" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRPEND91 ,Set/Clear Pending Bit 91" "Not pending,Pending" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRPEND90 ,Set/Clear Pending Bit 90" "Not pending,Pending" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEND89 ,Set/Clear Pending Bit 89" "Not pending,Pending" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRPEND88 ,Set/Clear Pending Bit 88" "Not pending,Pending" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRPEND87 ,Set/Clear Pending Bit 87" "Not pending,Pending" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEND86 ,Set/Clear Pending Bit 86" "Not pending,Pending" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRPEND85 ,Set/Clear Pending Bit 85" "Not pending,Pending" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRPEND84 ,Set/Clear Pending Bit 84" "Not pending,Pending" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEND83 ,Set/Clear Pending Bit 83" "Not pending,Pending" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRPEND82 ,Set/Clear Pending Bit 82" "Not pending,Pending" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRPEND81 ,Set/Clear Pending Bit 81" "Not pending,Pending" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEND80 ,Set/Clear Pending Bit 80" "Not pending,Pending" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRPEND79 ,Set/Clear Pending Bit 79" "Not pending,Pending" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRPEND78 ,Set/Clear Pending Bit 78" "Not pending,Pending" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEND77 ,Set/Clear Pending Bit 77" "Not pending,Pending" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRPEND76 ,Set/Clear Pending Bit 76" "Not pending,Pending" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRPEND75 ,Set/Clear Pending Bit 75" "Not pending,Pending" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEND74 ,Set/Clear Pending Bit 74" "Not pending,Pending" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRPEND73 ,Set/Clear Pending Bit 73" "Not pending,Pending" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRPEND72 ,Set/Clear Pending Bit 72" "Not pending,Pending" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEND71 ,Set/Clear Pending Bit 71" "Not pending,Pending" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRPEND70 ,Set/Clear Pending Bit 70" "Not pending,Pending" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRPEND69 ,Set/Clear Pending Bit 69" "Not pending,Pending" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEND68 ,Set/Clear Pending Bit 68" "Not pending,Pending" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRPEND67 ,Set/Clear Pending Bit 67" "Not pending,Pending" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRPEND66 ,Set/Clear Pending Bit 66" "Not pending,Pending" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEND65 ,Set/Clear Pending Bit 65" "Not pending,Pending" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRPEND64 ,Set/Clear Pending Bit 64" "Not pending,Pending" else rgroup.long 0x0208++0x03 line.long 0x0 "GICD_SET/CLR_PENDR2,Interrupt Set/Clear Pending Register 2" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(ad:(per.long(spr:0x31F30)&0xFFFC0000)+0x04))&0x0000001F)>=0x03) group.long 0x020C++0x03 line.long 0x0 "GICD_SET/CLR_PENDR3,Interrupt Set/Clear Pending Register 3" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEND127 ,Set/Clear Pending Bit 127" "Not pending,Pending" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRPEND126 ,Set/Clear Pending Bit 126" "Not pending,Pending" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRPEND125 ,Set/Clear Pending Bit 125" "Not pending,Pending" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEND124 ,Set/Clear Pending Bit 124" "Not pending,Pending" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRPEND123 ,Set/Clear Pending Bit 123" "Not pending,Pending" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRPEND122 ,Set/Clear Pending Bit 122" "Not pending,Pending" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEND121 ,Set/Clear Pending Bit 121" "Not pending,Pending" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRPEND120 ,Set/Clear Pending Bit 120" "Not pending,Pending" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRPEND119 ,Set/Clear Pending Bit 119" "Not pending,Pending" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEND118 ,Set/Clear Pending Bit 118" "Not pending,Pending" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRPEND117 ,Set/Clear Pending Bit 117" "Not pending,Pending" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRPEND116 ,Set/Clear Pending Bit 116" "Not pending,Pending" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEND115 ,Set/Clear Pending Bit 115" "Not pending,Pending" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRPEND114 ,Set/Clear Pending Bit 114" "Not pending,Pending" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRPEND113 ,Set/Clear Pending Bit 113" "Not pending,Pending" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEND112 ,Set/Clear Pending Bit 112" "Not pending,Pending" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRPEND111 ,Set/Clear Pending Bit 111" "Not pending,Pending" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRPEND110 ,Set/Clear Pending Bit 110" "Not pending,Pending" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEND109 ,Set/Clear Pending Bit 109" "Not pending,Pending" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRPEND108 ,Set/Clear Pending Bit 108" "Not pending,Pending" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRPEND107 ,Set/Clear Pending Bit 107" "Not pending,Pending" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEND106 ,Set/Clear Pending Bit 106" "Not pending,Pending" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRPEND105 ,Set/Clear Pending Bit 105" "Not pending,Pending" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRPEND104 ,Set/Clear Pending Bit 104" "Not pending,Pending" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEND103 ,Set/Clear Pending Bit 103" "Not pending,Pending" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRPEND102 ,Set/Clear Pending Bit 102" "Not pending,Pending" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRPEND101 ,Set/Clear Pending Bit 101" "Not pending,Pending" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEND100 ,Set/Clear Pending Bit 100" "Not pending,Pending" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRPEND99 ,Set/Clear Pending Bit 99" "Not pending,Pending" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRPEND98 ,Set/Clear Pending Bit 98" "Not pending,Pending" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEND97 ,Set/Clear Pending Bit 97" "Not pending,Pending" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRPEND96 ,Set/Clear Pending Bit 96" "Not pending,Pending" else rgroup.long 0x020C++0x03 line.long 0x0 "GICD_SET/CLR_PENDR3,Interrupt Set/Clear Pending Register 3" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(ad:(per.long(spr:0x31F30)&0xFFFC0000)+0x04))&0x0000001F)>=0x04) group.long 0x0210++0x03 line.long 0x0 "GICD_SET/CLR_PENDR4,Interrupt Set/Clear Pending Register 4" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEND159 ,Set/Clear Pending Bit 159" "Not pending,Pending" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRPEND158 ,Set/Clear Pending Bit 158" "Not pending,Pending" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRPEND157 ,Set/Clear Pending Bit 157" "Not pending,Pending" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEND156 ,Set/Clear Pending Bit 156" "Not pending,Pending" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRPEND155 ,Set/Clear Pending Bit 155" "Not pending,Pending" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRPEND154 ,Set/Clear Pending Bit 154" "Not pending,Pending" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEND153 ,Set/Clear Pending Bit 153" "Not pending,Pending" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRPEND152 ,Set/Clear Pending Bit 152" "Not pending,Pending" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRPEND151 ,Set/Clear Pending Bit 151" "Not pending,Pending" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEND150 ,Set/Clear Pending Bit 150" "Not pending,Pending" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRPEND149 ,Set/Clear Pending Bit 149" "Not pending,Pending" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRPEND148 ,Set/Clear Pending Bit 148" "Not pending,Pending" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEND147 ,Set/Clear Pending Bit 147" "Not pending,Pending" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRPEND146 ,Set/Clear Pending Bit 146" "Not pending,Pending" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRPEND145 ,Set/Clear Pending Bit 145" "Not pending,Pending" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEND144 ,Set/Clear Pending Bit 144" "Not pending,Pending" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRPEND143 ,Set/Clear Pending Bit 143" "Not pending,Pending" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRPEND142 ,Set/Clear Pending Bit 142" "Not pending,Pending" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEND141 ,Set/Clear Pending Bit 141" "Not pending,Pending" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRPEND140 ,Set/Clear Pending Bit 140" "Not pending,Pending" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRPEND139 ,Set/Clear Pending Bit 139" "Not pending,Pending" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEND138 ,Set/Clear Pending Bit 138" "Not pending,Pending" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRPEND137 ,Set/Clear Pending Bit 137" "Not pending,Pending" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRPEND136 ,Set/Clear Pending Bit 136" "Not pending,Pending" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEND135 ,Set/Clear Pending Bit 135" "Not pending,Pending" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRPEND134 ,Set/Clear Pending Bit 134" "Not pending,Pending" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRPEND133 ,Set/Clear Pending Bit 133" "Not pending,Pending" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEND132 ,Set/Clear Pending Bit 132" "Not pending,Pending" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRPEND131 ,Set/Clear Pending Bit 131" "Not pending,Pending" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRPEND130 ,Set/Clear Pending Bit 130" "Not pending,Pending" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEND129 ,Set/Clear Pending Bit 129" "Not pending,Pending" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRPEND128 ,Set/Clear Pending Bit 128" "Not pending,Pending" else rgroup.long 0x0210++0x03 line.long 0x0 "GICD_SET/CLR_PENDR4,Interrupt Set/Clear Pending Register 4" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(ad:(per.long(spr:0x31F30)&0xFFFC0000)+0x04))&0x0000001F)>=0x05) group.long 0x0214++0x03 line.long 0x0 "GICD_SET/CLR_PENDR5,Interrupt Set/Clear Pending Register 5" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEND191 ,Set/Clear Pending Bit 191" "Not pending,Pending" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRPEND190 ,Set/Clear Pending Bit 190" "Not pending,Pending" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRPEND189 ,Set/Clear Pending Bit 189" "Not pending,Pending" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEND188 ,Set/Clear Pending Bit 188" "Not pending,Pending" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRPEND187 ,Set/Clear Pending Bit 187" "Not pending,Pending" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRPEND186 ,Set/Clear Pending Bit 186" "Not pending,Pending" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEND185 ,Set/Clear Pending Bit 185" "Not pending,Pending" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRPEND184 ,Set/Clear Pending Bit 184" "Not pending,Pending" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRPEND183 ,Set/Clear Pending Bit 183" "Not pending,Pending" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEND182 ,Set/Clear Pending Bit 182" "Not pending,Pending" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRPEND181 ,Set/Clear Pending Bit 181" "Not pending,Pending" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRPEND180 ,Set/Clear Pending Bit 180" "Not pending,Pending" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEND179 ,Set/Clear Pending Bit 179" "Not pending,Pending" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRPEND178 ,Set/Clear Pending Bit 178" "Not pending,Pending" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRPEND177 ,Set/Clear Pending Bit 177" "Not pending,Pending" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEND176 ,Set/Clear Pending Bit 176" "Not pending,Pending" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRPEND175 ,Set/Clear Pending Bit 175" "Not pending,Pending" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRPEND174 ,Set/Clear Pending Bit 174" "Not pending,Pending" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEND173 ,Set/Clear Pending Bit 173" "Not pending,Pending" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRPEND172 ,Set/Clear Pending Bit 172" "Not pending,Pending" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRPEND171 ,Set/Clear Pending Bit 171" "Not pending,Pending" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEND170 ,Set/Clear Pending Bit 170" "Not pending,Pending" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRPEND169 ,Set/Clear Pending Bit 169" "Not pending,Pending" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRPEND168 ,Set/Clear Pending Bit 168" "Not pending,Pending" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEND167 ,Set/Clear Pending Bit 167" "Not pending,Pending" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRPEND166 ,Set/Clear Pending Bit 166" "Not pending,Pending" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRPEND165 ,Set/Clear Pending Bit 165" "Not pending,Pending" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEND164 ,Set/Clear Pending Bit 164" "Not pending,Pending" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRPEND163 ,Set/Clear Pending Bit 163" "Not pending,Pending" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRPEND162 ,Set/Clear Pending Bit 162" "Not pending,Pending" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEND161 ,Set/Clear Pending Bit 161" "Not pending,Pending" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRPEND160 ,Set/Clear Pending Bit 160" "Not pending,Pending" else rgroup.long 0x0214++0x03 line.long 0x0 "GICD_SET/CLR_PENDR5,Interrupt Set/Clear Pending Register 5" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(ad:(per.long(spr:0x31F30)&0xFFFC0000)+0x04))&0x0000001F)>=0x06) group.long 0x0218++0x03 line.long 0x0 "GICD_SET/CLR_PENDR6,Interrupt Set/Clear Pending Register 6" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEND223 ,Set/Clear Pending Bit 223" "Not pending,Pending" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRPEND222 ,Set/Clear Pending Bit 222" "Not pending,Pending" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRPEND221 ,Set/Clear Pending Bit 221" "Not pending,Pending" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEND220 ,Set/Clear Pending Bit 220" "Not pending,Pending" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRPEND219 ,Set/Clear Pending Bit 219" "Not pending,Pending" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRPEND218 ,Set/Clear Pending Bit 218" "Not pending,Pending" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEND217 ,Set/Clear Pending Bit 217" "Not pending,Pending" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRPEND216 ,Set/Clear Pending Bit 216" "Not pending,Pending" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRPEND215 ,Set/Clear Pending Bit 215" "Not pending,Pending" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEND214 ,Set/Clear Pending Bit 214" "Not pending,Pending" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRPEND213 ,Set/Clear Pending Bit 213" "Not pending,Pending" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRPEND212 ,Set/Clear Pending Bit 212" "Not pending,Pending" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEND211 ,Set/Clear Pending Bit 211" "Not pending,Pending" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRPEND210 ,Set/Clear Pending Bit 210" "Not pending,Pending" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRPEND209 ,Set/Clear Pending Bit 209" "Not pending,Pending" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEND208 ,Set/Clear Pending Bit 208" "Not pending,Pending" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRPEND207 ,Set/Clear Pending Bit 207" "Not pending,Pending" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRPEND206 ,Set/Clear Pending Bit 206" "Not pending,Pending" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEND205 ,Set/Clear Pending Bit 205" "Not pending,Pending" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRPEND204 ,Set/Clear Pending Bit 204" "Not pending,Pending" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRPEND203 ,Set/Clear Pending Bit 203" "Not pending,Pending" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEND202 ,Set/Clear Pending Bit 202" "Not pending,Pending" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRPEND201 ,Set/Clear Pending Bit 201" "Not pending,Pending" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRPEND200 ,Set/Clear Pending Bit 200" "Not pending,Pending" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEND199 ,Set/Clear Pending Bit 199" "Not pending,Pending" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRPEND198 ,Set/Clear Pending Bit 198" "Not pending,Pending" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRPEND197 ,Set/Clear Pending Bit 197" "Not pending,Pending" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEND196 ,Set/Clear Pending Bit 196" "Not pending,Pending" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRPEND195 ,Set/Clear Pending Bit 195" "Not pending,Pending" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRPEND194 ,Set/Clear Pending Bit 194" "Not pending,Pending" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEND193 ,Set/Clear Pending Bit 193" "Not pending,Pending" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRPEND192 ,Set/Clear Pending Bit 192" "Not pending,Pending" else rgroup.long 0x0218++0x03 line.long 0x0 "GICD_SET/CLR_PENDR6,Interrupt Set/Clear Pending Register 6" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(ad:(per.long(spr:0x31F30)&0xFFFC0000)+0x04))&0x0000001F)>=0x07) group.long 0x021C++0x03 line.long 0x0 "GICD_SET/CLR_PENDR7,Interrupt Set/Clear Pending Register 7" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEND255 ,Set/Clear Pending Bit 255" "Not pending,Pending" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRPEND254 ,Set/Clear Pending Bit 254" "Not pending,Pending" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRPEND253 ,Set/Clear Pending Bit 253" "Not pending,Pending" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEND252 ,Set/Clear Pending Bit 252" "Not pending,Pending" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRPEND251 ,Set/Clear Pending Bit 251" "Not pending,Pending" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRPEND250 ,Set/Clear Pending Bit 250" "Not pending,Pending" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEND249 ,Set/Clear Pending Bit 249" "Not pending,Pending" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRPEND248 ,Set/Clear Pending Bit 248" "Not pending,Pending" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRPEND247 ,Set/Clear Pending Bit 247" "Not pending,Pending" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEND246 ,Set/Clear Pending Bit 246" "Not pending,Pending" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRPEND245 ,Set/Clear Pending Bit 245" "Not pending,Pending" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRPEND244 ,Set/Clear Pending Bit 244" "Not pending,Pending" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEND243 ,Set/Clear Pending Bit 243" "Not pending,Pending" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRPEND242 ,Set/Clear Pending Bit 242" "Not pending,Pending" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRPEND241 ,Set/Clear Pending Bit 241" "Not pending,Pending" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEND240 ,Set/Clear Pending Bit 240" "Not pending,Pending" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRPEND239 ,Set/Clear Pending Bit 239" "Not pending,Pending" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRPEND238 ,Set/Clear Pending Bit 238" "Not pending,Pending" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEND237 ,Set/Clear Pending Bit 237" "Not pending,Pending" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRPEND236 ,Set/Clear Pending Bit 236" "Not pending,Pending" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRPEND235 ,Set/Clear Pending Bit 235" "Not pending,Pending" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEND234 ,Set/Clear Pending Bit 234" "Not pending,Pending" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRPEND233 ,Set/Clear Pending Bit 233" "Not pending,Pending" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRPEND232 ,Set/Clear Pending Bit 232" "Not pending,Pending" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEND231 ,Set/Clear Pending Bit 231" "Not pending,Pending" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRPEND230 ,Set/Clear Pending Bit 230" "Not pending,Pending" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRPEND229 ,Set/Clear Pending Bit 229" "Not pending,Pending" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEND228 ,Set/Clear Pending Bit 228" "Not pending,Pending" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRPEND227 ,Set/Clear Pending Bit 227" "Not pending,Pending" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRPEND226 ,Set/Clear Pending Bit 226" "Not pending,Pending" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEND225 ,Set/Clear Pending Bit 225" "Not pending,Pending" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRPEND224 ,Set/Clear Pending Bit 224" "Not pending,Pending" else rgroup.long 0x021C++0x03 line.long 0x0 "GICD_SET/CLR_PENDR7,Interrupt Set/Clear Pending Register 7" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(ad:(per.long(spr:0x31F30)&0xFFFC0000)+0x04))&0x0000001F)>=0x08) group.long 0x0220++0x03 line.long 0x0 "GICD_SET/CLR_PENDR8,Interrupt Set/Clear Pending Register 8" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEND287 ,Set/Clear Pending Bit 287" "Not pending,Pending" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRPEND286 ,Set/Clear Pending Bit 286" "Not pending,Pending" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRPEND285 ,Set/Clear Pending Bit 285" "Not pending,Pending" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEND284 ,Set/Clear Pending Bit 284" "Not pending,Pending" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRPEND283 ,Set/Clear Pending Bit 283" "Not pending,Pending" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRPEND282 ,Set/Clear Pending Bit 282" "Not pending,Pending" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEND281 ,Set/Clear Pending Bit 281" "Not pending,Pending" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRPEND280 ,Set/Clear Pending Bit 280" "Not pending,Pending" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRPEND279 ,Set/Clear Pending Bit 279" "Not pending,Pending" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEND278 ,Set/Clear Pending Bit 278" "Not pending,Pending" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRPEND277 ,Set/Clear Pending Bit 277" "Not pending,Pending" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRPEND276 ,Set/Clear Pending Bit 276" "Not pending,Pending" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEND275 ,Set/Clear Pending Bit 275" "Not pending,Pending" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRPEND274 ,Set/Clear Pending Bit 274" "Not pending,Pending" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRPEND273 ,Set/Clear Pending Bit 273" "Not pending,Pending" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEND272 ,Set/Clear Pending Bit 272" "Not pending,Pending" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRPEND271 ,Set/Clear Pending Bit 271" "Not pending,Pending" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRPEND270 ,Set/Clear Pending Bit 270" "Not pending,Pending" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEND269 ,Set/Clear Pending Bit 269" "Not pending,Pending" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRPEND268 ,Set/Clear Pending Bit 268" "Not pending,Pending" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRPEND267 ,Set/Clear Pending Bit 267" "Not pending,Pending" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEND266 ,Set/Clear Pending Bit 266" "Not pending,Pending" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRPEND265 ,Set/Clear Pending Bit 265" "Not pending,Pending" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRPEND264 ,Set/Clear Pending Bit 264" "Not pending,Pending" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEND263 ,Set/Clear Pending Bit 263" "Not pending,Pending" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRPEND262 ,Set/Clear Pending Bit 262" "Not pending,Pending" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRPEND261 ,Set/Clear Pending Bit 261" "Not pending,Pending" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEND260 ,Set/Clear Pending Bit 260" "Not pending,Pending" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRPEND259 ,Set/Clear Pending Bit 259" "Not pending,Pending" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRPEND258 ,Set/Clear Pending Bit 258" "Not pending,Pending" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEND257 ,Set/Clear Pending Bit 257" "Not pending,Pending" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRPEND256 ,Set/Clear Pending Bit 256" "Not pending,Pending" else rgroup.long 0x0220++0x03 line.long 0x0 "GICD_SET/CLR_PENDR8,Interrupt Set/Clear Pending Register 8" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(ad:(per.long(spr:0x31F30)&0xFFFC0000)+0x04))&0x0000001F)>=0x09) group.long 0x0224++0x03 line.long 0x0 "GICD_SET/CLR_PENDR9,Interrupt Set/Clear Pending Register 9" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEND319 ,Set/Clear Pending Bit 319" "Not pending,Pending" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRPEND318 ,Set/Clear Pending Bit 318" "Not pending,Pending" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRPEND317 ,Set/Clear Pending Bit 317" "Not pending,Pending" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEND316 ,Set/Clear Pending Bit 316" "Not pending,Pending" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRPEND315 ,Set/Clear Pending Bit 315" "Not pending,Pending" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRPEND314 ,Set/Clear Pending Bit 314" "Not pending,Pending" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEND313 ,Set/Clear Pending Bit 313" "Not pending,Pending" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRPEND312 ,Set/Clear Pending Bit 312" "Not pending,Pending" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRPEND311 ,Set/Clear Pending Bit 311" "Not pending,Pending" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEND310 ,Set/Clear Pending Bit 310" "Not pending,Pending" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRPEND309 ,Set/Clear Pending Bit 309" "Not pending,Pending" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRPEND308 ,Set/Clear Pending Bit 308" "Not pending,Pending" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEND307 ,Set/Clear Pending Bit 307" "Not pending,Pending" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRPEND306 ,Set/Clear Pending Bit 306" "Not pending,Pending" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRPEND305 ,Set/Clear Pending Bit 305" "Not pending,Pending" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEND304 ,Set/Clear Pending Bit 304" "Not pending,Pending" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRPEND303 ,Set/Clear Pending Bit 303" "Not pending,Pending" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRPEND302 ,Set/Clear Pending Bit 302" "Not pending,Pending" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEND301 ,Set/Clear Pending Bit 301" "Not pending,Pending" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRPEND300 ,Set/Clear Pending Bit 300" "Not pending,Pending" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRPEND299 ,Set/Clear Pending Bit 299" "Not pending,Pending" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEND298 ,Set/Clear Pending Bit 298" "Not pending,Pending" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRPEND297 ,Set/Clear Pending Bit 297" "Not pending,Pending" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRPEND296 ,Set/Clear Pending Bit 296" "Not pending,Pending" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEND295 ,Set/Clear Pending Bit 295" "Not pending,Pending" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRPEND294 ,Set/Clear Pending Bit 294" "Not pending,Pending" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRPEND293 ,Set/Clear Pending Bit 293" "Not pending,Pending" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEND292 ,Set/Clear Pending Bit 292" "Not pending,Pending" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRPEND291 ,Set/Clear Pending Bit 291" "Not pending,Pending" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRPEND290 ,Set/Clear Pending Bit 290" "Not pending,Pending" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEND289 ,Set/Clear Pending Bit 289" "Not pending,Pending" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRPEND288 ,Set/Clear Pending Bit 288" "Not pending,Pending" else rgroup.long 0x0224++0x03 line.long 0x0 "GICD_SET/CLR_PENDR9,Interrupt Set/Clear Pending Register 9" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(ad:(per.long(spr:0x31F30)&0xFFFC0000)+0x04))&0x0000001F)>=0x0A) group.long 0x0228++0x03 line.long 0x0 "GICD_SET/CLR_PENDR10,Interrupt Set/Clear Pending Register 10" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEND351 ,Set/Clear Pending Bit 351" "Not pending,Pending" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRPEND350 ,Set/Clear Pending Bit 350" "Not pending,Pending" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRPEND349 ,Set/Clear Pending Bit 349" "Not pending,Pending" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEND348 ,Set/Clear Pending Bit 348" "Not pending,Pending" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRPEND347 ,Set/Clear Pending Bit 347" "Not pending,Pending" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRPEND346 ,Set/Clear Pending Bit 346" "Not pending,Pending" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEND345 ,Set/Clear Pending Bit 345" "Not pending,Pending" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRPEND344 ,Set/Clear Pending Bit 344" "Not pending,Pending" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRPEND343 ,Set/Clear Pending Bit 343" "Not pending,Pending" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEND342 ,Set/Clear Pending Bit 342" "Not pending,Pending" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRPEND341 ,Set/Clear Pending Bit 341" "Not pending,Pending" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRPEND340 ,Set/Clear Pending Bit 340" "Not pending,Pending" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEND339 ,Set/Clear Pending Bit 339" "Not pending,Pending" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRPEND338 ,Set/Clear Pending Bit 338" "Not pending,Pending" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRPEND337 ,Set/Clear Pending Bit 337" "Not pending,Pending" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEND336 ,Set/Clear Pending Bit 336" "Not pending,Pending" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRPEND335 ,Set/Clear Pending Bit 335" "Not pending,Pending" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRPEND334 ,Set/Clear Pending Bit 334" "Not pending,Pending" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEND333 ,Set/Clear Pending Bit 333" "Not pending,Pending" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRPEND332 ,Set/Clear Pending Bit 332" "Not pending,Pending" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRPEND331 ,Set/Clear Pending Bit 331" "Not pending,Pending" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEND330 ,Set/Clear Pending Bit 330" "Not pending,Pending" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRPEND329 ,Set/Clear Pending Bit 329" "Not pending,Pending" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRPEND328 ,Set/Clear Pending Bit 328" "Not pending,Pending" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEND327 ,Set/Clear Pending Bit 327" "Not pending,Pending" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRPEND326 ,Set/Clear Pending Bit 326" "Not pending,Pending" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRPEND325 ,Set/Clear Pending Bit 325" "Not pending,Pending" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEND324 ,Set/Clear Pending Bit 324" "Not pending,Pending" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRPEND323 ,Set/Clear Pending Bit 323" "Not pending,Pending" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRPEND322 ,Set/Clear Pending Bit 322" "Not pending,Pending" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEND321 ,Set/Clear Pending Bit 321" "Not pending,Pending" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRPEND320 ,Set/Clear Pending Bit 320" "Not pending,Pending" else rgroup.long 0x0228++0x03 line.long 0x0 "GICD_SET/CLR_PENDR10,Interrupt Set/Clear Pending Register 10" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(ad:(per.long(spr:0x31F30)&0xFFFC0000)+0x04))&0x0000001F)>=0x0B) group.long 0x022C++0x03 line.long 0x0 "GICD_SET/CLR_PENDR11,Interrupt Set/Clear Pending Register 11" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEND383 ,Set/Clear Pending Bit 383" "Not pending,Pending" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRPEND382 ,Set/Clear Pending Bit 382" "Not pending,Pending" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRPEND381 ,Set/Clear Pending Bit 381" "Not pending,Pending" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEND380 ,Set/Clear Pending Bit 380" "Not pending,Pending" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRPEND379 ,Set/Clear Pending Bit 379" "Not pending,Pending" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRPEND378 ,Set/Clear Pending Bit 378" "Not pending,Pending" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEND377 ,Set/Clear Pending Bit 377" "Not pending,Pending" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRPEND376 ,Set/Clear Pending Bit 376" "Not pending,Pending" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRPEND375 ,Set/Clear Pending Bit 375" "Not pending,Pending" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEND374 ,Set/Clear Pending Bit 374" "Not pending,Pending" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRPEND373 ,Set/Clear Pending Bit 373" "Not pending,Pending" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRPEND372 ,Set/Clear Pending Bit 372" "Not pending,Pending" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEND371 ,Set/Clear Pending Bit 371" "Not pending,Pending" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRPEND370 ,Set/Clear Pending Bit 370" "Not pending,Pending" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRPEND369 ,Set/Clear Pending Bit 369" "Not pending,Pending" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEND368 ,Set/Clear Pending Bit 368" "Not pending,Pending" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRPEND367 ,Set/Clear Pending Bit 367" "Not pending,Pending" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRPEND366 ,Set/Clear Pending Bit 366" "Not pending,Pending" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEND365 ,Set/Clear Pending Bit 365" "Not pending,Pending" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRPEND364 ,Set/Clear Pending Bit 364" "Not pending,Pending" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRPEND363 ,Set/Clear Pending Bit 363" "Not pending,Pending" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEND362 ,Set/Clear Pending Bit 362" "Not pending,Pending" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRPEND361 ,Set/Clear Pending Bit 361" "Not pending,Pending" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRPEND360 ,Set/Clear Pending Bit 360" "Not pending,Pending" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEND359 ,Set/Clear Pending Bit 359" "Not pending,Pending" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRPEND358 ,Set/Clear Pending Bit 358" "Not pending,Pending" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRPEND357 ,Set/Clear Pending Bit 357" "Not pending,Pending" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEND356 ,Set/Clear Pending Bit 356" "Not pending,Pending" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRPEND355 ,Set/Clear Pending Bit 355" "Not pending,Pending" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRPEND354 ,Set/Clear Pending Bit 354" "Not pending,Pending" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEND353 ,Set/Clear Pending Bit 353" "Not pending,Pending" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRPEND352 ,Set/Clear Pending Bit 352" "Not pending,Pending" else rgroup.long 0x022C++0x03 line.long 0x0 "GICD_SET/CLR_PENDR11,Interrupt Set/Clear Pending Register 11" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(ad:(per.long(spr:0x31F30)&0xFFFC0000)+0x04))&0x0000001F)>=0x0C) group.long 0x0230++0x03 line.long 0x0 "GICD_SET/CLR_PENDR12,Interrupt Set/Clear Pending Register 12" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEND415 ,Set/Clear Pending Bit 415" "Not pending,Pending" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRPEND414 ,Set/Clear Pending Bit 414" "Not pending,Pending" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRPEND413 ,Set/Clear Pending Bit 413" "Not pending,Pending" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEND412 ,Set/Clear Pending Bit 412" "Not pending,Pending" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRPEND411 ,Set/Clear Pending Bit 411" "Not pending,Pending" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRPEND410 ,Set/Clear Pending Bit 410" "Not pending,Pending" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEND409 ,Set/Clear Pending Bit 409" "Not pending,Pending" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRPEND408 ,Set/Clear Pending Bit 408" "Not pending,Pending" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRPEND407 ,Set/Clear Pending Bit 407" "Not pending,Pending" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEND406 ,Set/Clear Pending Bit 406" "Not pending,Pending" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRPEND405 ,Set/Clear Pending Bit 405" "Not pending,Pending" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRPEND404 ,Set/Clear Pending Bit 404" "Not pending,Pending" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEND403 ,Set/Clear Pending Bit 403" "Not pending,Pending" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRPEND402 ,Set/Clear Pending Bit 402" "Not pending,Pending" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRPEND401 ,Set/Clear Pending Bit 401" "Not pending,Pending" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEND400 ,Set/Clear Pending Bit 400" "Not pending,Pending" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRPEND399 ,Set/Clear Pending Bit 399" "Not pending,Pending" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRPEND398 ,Set/Clear Pending Bit 398" "Not pending,Pending" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEND397 ,Set/Clear Pending Bit 397" "Not pending,Pending" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRPEND396 ,Set/Clear Pending Bit 396" "Not pending,Pending" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRPEND395 ,Set/Clear Pending Bit 395" "Not pending,Pending" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEND394 ,Set/Clear Pending Bit 394" "Not pending,Pending" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRPEND393 ,Set/Clear Pending Bit 393" "Not pending,Pending" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRPEND392 ,Set/Clear Pending Bit 392" "Not pending,Pending" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEND391 ,Set/Clear Pending Bit 391" "Not pending,Pending" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRPEND390 ,Set/Clear Pending Bit 390" "Not pending,Pending" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRPEND389 ,Set/Clear Pending Bit 389" "Not pending,Pending" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEND388 ,Set/Clear Pending Bit 388" "Not pending,Pending" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRPEND387 ,Set/Clear Pending Bit 387" "Not pending,Pending" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRPEND386 ,Set/Clear Pending Bit 386" "Not pending,Pending" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEND385 ,Set/Clear Pending Bit 385" "Not pending,Pending" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRPEND384 ,Set/Clear Pending Bit 384" "Not pending,Pending" else rgroup.long 0x0230++0x03 line.long 0x0 "GICD_SET/CLR_PENDR12,Interrupt Set/Clear Pending Register 12" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(ad:(per.long(spr:0x31F30)&0xFFFC0000)+0x04))&0x0000001F)>=0x0D) group.long 0x0234++0x03 line.long 0x0 "GICD_SET/CLR_PENDR13,Interrupt Set/Clear Pending Register 13" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEND447 ,Set/Clear Pending Bit 447" "Not pending,Pending" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRPEND446 ,Set/Clear Pending Bit 446" "Not pending,Pending" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRPEND445 ,Set/Clear Pending Bit 445" "Not pending,Pending" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEND444 ,Set/Clear Pending Bit 444" "Not pending,Pending" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRPEND443 ,Set/Clear Pending Bit 443" "Not pending,Pending" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRPEND442 ,Set/Clear Pending Bit 442" "Not pending,Pending" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEND441 ,Set/Clear Pending Bit 441" "Not pending,Pending" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRPEND440 ,Set/Clear Pending Bit 440" "Not pending,Pending" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRPEND439 ,Set/Clear Pending Bit 439" "Not pending,Pending" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEND438 ,Set/Clear Pending Bit 438" "Not pending,Pending" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRPEND437 ,Set/Clear Pending Bit 437" "Not pending,Pending" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRPEND436 ,Set/Clear Pending Bit 436" "Not pending,Pending" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEND435 ,Set/Clear Pending Bit 435" "Not pending,Pending" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRPEND434 ,Set/Clear Pending Bit 434" "Not pending,Pending" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRPEND433 ,Set/Clear Pending Bit 433" "Not pending,Pending" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEND432 ,Set/Clear Pending Bit 432" "Not pending,Pending" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRPEND431 ,Set/Clear Pending Bit 431" "Not pending,Pending" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRPEND430 ,Set/Clear Pending Bit 430" "Not pending,Pending" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEND429 ,Set/Clear Pending Bit 429" "Not pending,Pending" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRPEND428 ,Set/Clear Pending Bit 428" "Not pending,Pending" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRPEND427 ,Set/Clear Pending Bit 427" "Not pending,Pending" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEND426 ,Set/Clear Pending Bit 426" "Not pending,Pending" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRPEND425 ,Set/Clear Pending Bit 425" "Not pending,Pending" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRPEND424 ,Set/Clear Pending Bit 424" "Not pending,Pending" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEND423 ,Set/Clear Pending Bit 423" "Not pending,Pending" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRPEND422 ,Set/Clear Pending Bit 422" "Not pending,Pending" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRPEND421 ,Set/Clear Pending Bit 421" "Not pending,Pending" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEND420 ,Set/Clear Pending Bit 420" "Not pending,Pending" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRPEND419 ,Set/Clear Pending Bit 419" "Not pending,Pending" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRPEND418 ,Set/Clear Pending Bit 418" "Not pending,Pending" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEND417 ,Set/Clear Pending Bit 417" "Not pending,Pending" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRPEND416 ,Set/Clear Pending Bit 416" "Not pending,Pending" else rgroup.long 0x0234++0x03 line.long 0x0 "GICD_SET/CLR_PENDR13,Interrupt Set/Clear Pending Register 13" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(ad:(per.long(spr:0x31F30)&0xFFFC0000)+0x04))&0x0000001F)>=0x0E) group.long 0x0238++0x03 line.long 0x0 "GICD_SET/CLR_PENDR14,Interrupt Set/Clear Pending Register 14" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEND479 ,Set/Clear Pending Bit 479" "Not pending,Pending" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRPEND478 ,Set/Clear Pending Bit 478" "Not pending,Pending" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRPEND477 ,Set/Clear Pending Bit 477" "Not pending,Pending" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEND476 ,Set/Clear Pending Bit 476" "Not pending,Pending" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRPEND475 ,Set/Clear Pending Bit 475" "Not pending,Pending" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRPEND474 ,Set/Clear Pending Bit 474" "Not pending,Pending" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEND473 ,Set/Clear Pending Bit 473" "Not pending,Pending" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRPEND472 ,Set/Clear Pending Bit 472" "Not pending,Pending" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRPEND471 ,Set/Clear Pending Bit 471" "Not pending,Pending" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEND470 ,Set/Clear Pending Bit 470" "Not pending,Pending" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRPEND469 ,Set/Clear Pending Bit 469" "Not pending,Pending" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRPEND468 ,Set/Clear Pending Bit 468" "Not pending,Pending" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEND467 ,Set/Clear Pending Bit 467" "Not pending,Pending" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRPEND466 ,Set/Clear Pending Bit 466" "Not pending,Pending" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRPEND465 ,Set/Clear Pending Bit 465" "Not pending,Pending" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEND464 ,Set/Clear Pending Bit 464" "Not pending,Pending" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRPEND463 ,Set/Clear Pending Bit 463" "Not pending,Pending" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRPEND462 ,Set/Clear Pending Bit 462" "Not pending,Pending" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEND461 ,Set/Clear Pending Bit 461" "Not pending,Pending" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRPEND460 ,Set/Clear Pending Bit 460" "Not pending,Pending" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRPEND459 ,Set/Clear Pending Bit 459" "Not pending,Pending" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEND458 ,Set/Clear Pending Bit 458" "Not pending,Pending" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRPEND457 ,Set/Clear Pending Bit 457" "Not pending,Pending" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRPEND456 ,Set/Clear Pending Bit 456" "Not pending,Pending" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEND455 ,Set/Clear Pending Bit 455" "Not pending,Pending" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRPEND454 ,Set/Clear Pending Bit 454" "Not pending,Pending" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRPEND453 ,Set/Clear Pending Bit 453" "Not pending,Pending" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEND452 ,Set/Clear Pending Bit 452" "Not pending,Pending" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRPEND451 ,Set/Clear Pending Bit 451" "Not pending,Pending" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRPEND450 ,Set/Clear Pending Bit 450" "Not pending,Pending" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEND449 ,Set/Clear Pending Bit 449" "Not pending,Pending" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRPEND448 ,Set/Clear Pending Bit 448" "Not pending,Pending" else rgroup.long 0x0238++0x03 line.long 0x0 "GICD_SET/CLR_PENDR14,Interrupt Set/Clear Pending Register 14" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(ad:(per.long(spr:0x31F30)&0xFFFC0000)+0x04))&0x0000001F)>=0x0F) group.long 0x023C++0x03 line.long 0x0 "GICD_SET/CLR_PENDR15,Interrupt Set/Clear Pending Register 15" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEND511 ,Set/Clear Pending Bit 511" "Not pending,Pending" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRPEND510 ,Set/Clear Pending Bit 510" "Not pending,Pending" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRPEND509 ,Set/Clear Pending Bit 509" "Not pending,Pending" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEND508 ,Set/Clear Pending Bit 508" "Not pending,Pending" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRPEND507 ,Set/Clear Pending Bit 507" "Not pending,Pending" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRPEND506 ,Set/Clear Pending Bit 506" "Not pending,Pending" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEND505 ,Set/Clear Pending Bit 505" "Not pending,Pending" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRPEND504 ,Set/Clear Pending Bit 504" "Not pending,Pending" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRPEND503 ,Set/Clear Pending Bit 503" "Not pending,Pending" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEND502 ,Set/Clear Pending Bit 502" "Not pending,Pending" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRPEND501 ,Set/Clear Pending Bit 501" "Not pending,Pending" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRPEND500 ,Set/Clear Pending Bit 500" "Not pending,Pending" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEND499 ,Set/Clear Pending Bit 499" "Not pending,Pending" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRPEND498 ,Set/Clear Pending Bit 498" "Not pending,Pending" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRPEND497 ,Set/Clear Pending Bit 497" "Not pending,Pending" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEND496 ,Set/Clear Pending Bit 496" "Not pending,Pending" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRPEND495 ,Set/Clear Pending Bit 495" "Not pending,Pending" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRPEND494 ,Set/Clear Pending Bit 494" "Not pending,Pending" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEND493 ,Set/Clear Pending Bit 493" "Not pending,Pending" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRPEND492 ,Set/Clear Pending Bit 492" "Not pending,Pending" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRPEND491 ,Set/Clear Pending Bit 491" "Not pending,Pending" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEND490 ,Set/Clear Pending Bit 490" "Not pending,Pending" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRPEND489 ,Set/Clear Pending Bit 489" "Not pending,Pending" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRPEND488 ,Set/Clear Pending Bit 488" "Not pending,Pending" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEND487 ,Set/Clear Pending Bit 487" "Not pending,Pending" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRPEND486 ,Set/Clear Pending Bit 486" "Not pending,Pending" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRPEND485 ,Set/Clear Pending Bit 485" "Not pending,Pending" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEND484 ,Set/Clear Pending Bit 484" "Not pending,Pending" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRPEND483 ,Set/Clear Pending Bit 483" "Not pending,Pending" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRPEND482 ,Set/Clear Pending Bit 482" "Not pending,Pending" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEND481 ,Set/Clear Pending Bit 481" "Not pending,Pending" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRPEND480 ,Set/Clear Pending Bit 480" "Not pending,Pending" else rgroup.long 0x023C++0x03 line.long 0x0 "GICD_SET/CLR_PENDR15,Interrupt Set/Clear Pending Register 15" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(ad:(per.long(spr:0x31F30)&0xFFFC0000)+0x04))&0x0000001F)>=0x10) group.long 0x0240++0x03 line.long 0x0 "GICD_SET/CLR_PENDR16,Interrupt Set/Clear Pending Register 16" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEND543 ,Set/Clear Pending Bit 543" "Not pending,Pending" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRPEND542 ,Set/Clear Pending Bit 542" "Not pending,Pending" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRPEND541 ,Set/Clear Pending Bit 541" "Not pending,Pending" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEND540 ,Set/Clear Pending Bit 540" "Not pending,Pending" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRPEND539 ,Set/Clear Pending Bit 539" "Not pending,Pending" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRPEND538 ,Set/Clear Pending Bit 538" "Not pending,Pending" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEND537 ,Set/Clear Pending Bit 537" "Not pending,Pending" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRPEND536 ,Set/Clear Pending Bit 536" "Not pending,Pending" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRPEND535 ,Set/Clear Pending Bit 535" "Not pending,Pending" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEND534 ,Set/Clear Pending Bit 534" "Not pending,Pending" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRPEND533 ,Set/Clear Pending Bit 533" "Not pending,Pending" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRPEND532 ,Set/Clear Pending Bit 532" "Not pending,Pending" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEND531 ,Set/Clear Pending Bit 531" "Not pending,Pending" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRPEND530 ,Set/Clear Pending Bit 530" "Not pending,Pending" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRPEND529 ,Set/Clear Pending Bit 529" "Not pending,Pending" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEND528 ,Set/Clear Pending Bit 528" "Not pending,Pending" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRPEND527 ,Set/Clear Pending Bit 527" "Not pending,Pending" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRPEND526 ,Set/Clear Pending Bit 526" "Not pending,Pending" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEND525 ,Set/Clear Pending Bit 525" "Not pending,Pending" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRPEND524 ,Set/Clear Pending Bit 524" "Not pending,Pending" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRPEND523 ,Set/Clear Pending Bit 523" "Not pending,Pending" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEND522 ,Set/Clear Pending Bit 522" "Not pending,Pending" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRPEND521 ,Set/Clear Pending Bit 521" "Not pending,Pending" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRPEND520 ,Set/Clear Pending Bit 520" "Not pending,Pending" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEND519 ,Set/Clear Pending Bit 519" "Not pending,Pending" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRPEND518 ,Set/Clear Pending Bit 518" "Not pending,Pending" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRPEND517 ,Set/Clear Pending Bit 517" "Not pending,Pending" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEND516 ,Set/Clear Pending Bit 516" "Not pending,Pending" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRPEND515 ,Set/Clear Pending Bit 515" "Not pending,Pending" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRPEND514 ,Set/Clear Pending Bit 514" "Not pending,Pending" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEND513 ,Set/Clear Pending Bit 513" "Not pending,Pending" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRPEND512 ,Set/Clear Pending Bit 512" "Not pending,Pending" else rgroup.long 0x0240++0x03 line.long 0x0 "GICD_SET/CLR_PENDR16,Interrupt Set/Clear Pending Register 16" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(ad:(per.long(spr:0x31F30)&0xFFFC0000)+0x04))&0x0000001F)>=0x11) group.long 0x0244++0x03 line.long 0x0 "GICD_SET/CLR_PENDR17,Interrupt Set/Clear Pending Register 17" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEND575 ,Set/Clear Pending Bit 575" "Not pending,Pending" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRPEND574 ,Set/Clear Pending Bit 574" "Not pending,Pending" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRPEND573 ,Set/Clear Pending Bit 573" "Not pending,Pending" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEND572 ,Set/Clear Pending Bit 572" "Not pending,Pending" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRPEND571 ,Set/Clear Pending Bit 571" "Not pending,Pending" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRPEND570 ,Set/Clear Pending Bit 570" "Not pending,Pending" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEND569 ,Set/Clear Pending Bit 569" "Not pending,Pending" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRPEND568 ,Set/Clear Pending Bit 568" "Not pending,Pending" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRPEND567 ,Set/Clear Pending Bit 567" "Not pending,Pending" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEND566 ,Set/Clear Pending Bit 566" "Not pending,Pending" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRPEND565 ,Set/Clear Pending Bit 565" "Not pending,Pending" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRPEND564 ,Set/Clear Pending Bit 564" "Not pending,Pending" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEND563 ,Set/Clear Pending Bit 563" "Not pending,Pending" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRPEND562 ,Set/Clear Pending Bit 562" "Not pending,Pending" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRPEND561 ,Set/Clear Pending Bit 561" "Not pending,Pending" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEND560 ,Set/Clear Pending Bit 560" "Not pending,Pending" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRPEND559 ,Set/Clear Pending Bit 559" "Not pending,Pending" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRPEND558 ,Set/Clear Pending Bit 558" "Not pending,Pending" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEND557 ,Set/Clear Pending Bit 557" "Not pending,Pending" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRPEND556 ,Set/Clear Pending Bit 556" "Not pending,Pending" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRPEND555 ,Set/Clear Pending Bit 555" "Not pending,Pending" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEND554 ,Set/Clear Pending Bit 554" "Not pending,Pending" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRPEND553 ,Set/Clear Pending Bit 553" "Not pending,Pending" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRPEND552 ,Set/Clear Pending Bit 552" "Not pending,Pending" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEND551 ,Set/Clear Pending Bit 551" "Not pending,Pending" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRPEND550 ,Set/Clear Pending Bit 550" "Not pending,Pending" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRPEND549 ,Set/Clear Pending Bit 549" "Not pending,Pending" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEND548 ,Set/Clear Pending Bit 548" "Not pending,Pending" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRPEND547 ,Set/Clear Pending Bit 547" "Not pending,Pending" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRPEND546 ,Set/Clear Pending Bit 546" "Not pending,Pending" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEND545 ,Set/Clear Pending Bit 545" "Not pending,Pending" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRPEND544 ,Set/Clear Pending Bit 544" "Not pending,Pending" else rgroup.long 0x0244++0x03 line.long 0x0 "GICD_SET/CLR_PENDR17,Interrupt Set/Clear Pending Register 17" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(ad:(per.long(spr:0x31F30)&0xFFFC0000)+0x04))&0x0000001F)>=0x12) group.long 0x0248++0x03 line.long 0x0 "GICD_SET/CLR_PENDR18,Interrupt Set/Clear Pending Register 18" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEND607 ,Set/Clear Pending Bit 607" "Not pending,Pending" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRPEND606 ,Set/Clear Pending Bit 606" "Not pending,Pending" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRPEND605 ,Set/Clear Pending Bit 605" "Not pending,Pending" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEND604 ,Set/Clear Pending Bit 604" "Not pending,Pending" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRPEND603 ,Set/Clear Pending Bit 603" "Not pending,Pending" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRPEND602 ,Set/Clear Pending Bit 602" "Not pending,Pending" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEND601 ,Set/Clear Pending Bit 601" "Not pending,Pending" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRPEND600 ,Set/Clear Pending Bit 600" "Not pending,Pending" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRPEND599 ,Set/Clear Pending Bit 599" "Not pending,Pending" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEND598 ,Set/Clear Pending Bit 598" "Not pending,Pending" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRPEND597 ,Set/Clear Pending Bit 597" "Not pending,Pending" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRPEND596 ,Set/Clear Pending Bit 596" "Not pending,Pending" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEND595 ,Set/Clear Pending Bit 595" "Not pending,Pending" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRPEND594 ,Set/Clear Pending Bit 594" "Not pending,Pending" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRPEND593 ,Set/Clear Pending Bit 593" "Not pending,Pending" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEND592 ,Set/Clear Pending Bit 592" "Not pending,Pending" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRPEND591 ,Set/Clear Pending Bit 591" "Not pending,Pending" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRPEND590 ,Set/Clear Pending Bit 590" "Not pending,Pending" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEND589 ,Set/Clear Pending Bit 589" "Not pending,Pending" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRPEND588 ,Set/Clear Pending Bit 588" "Not pending,Pending" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRPEND587 ,Set/Clear Pending Bit 587" "Not pending,Pending" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEND586 ,Set/Clear Pending Bit 586" "Not pending,Pending" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRPEND585 ,Set/Clear Pending Bit 585" "Not pending,Pending" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRPEND584 ,Set/Clear Pending Bit 584" "Not pending,Pending" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEND583 ,Set/Clear Pending Bit 583" "Not pending,Pending" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRPEND582 ,Set/Clear Pending Bit 582" "Not pending,Pending" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRPEND581 ,Set/Clear Pending Bit 581" "Not pending,Pending" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEND580 ,Set/Clear Pending Bit 580" "Not pending,Pending" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRPEND579 ,Set/Clear Pending Bit 579" "Not pending,Pending" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRPEND578 ,Set/Clear Pending Bit 578" "Not pending,Pending" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEND577 ,Set/Clear Pending Bit 577" "Not pending,Pending" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRPEND576 ,Set/Clear Pending Bit 576" "Not pending,Pending" else rgroup.long 0x0248++0x03 line.long 0x0 "GICD_SET/CLR_PENDR18,Interrupt Set/Clear Pending Register 18" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(ad:(per.long(spr:0x31F30)&0xFFFC0000)+0x04))&0x0000001F)>=0x13) group.long 0x024C++0x03 line.long 0x0 "GICD_SET/CLR_PENDR19,Interrupt Set/Clear Pending Register 19" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEND639 ,Set/Clear Pending Bit 639" "Not pending,Pending" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRPEND638 ,Set/Clear Pending Bit 638" "Not pending,Pending" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRPEND637 ,Set/Clear Pending Bit 637" "Not pending,Pending" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEND636 ,Set/Clear Pending Bit 636" "Not pending,Pending" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRPEND635 ,Set/Clear Pending Bit 635" "Not pending,Pending" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRPEND634 ,Set/Clear Pending Bit 634" "Not pending,Pending" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEND633 ,Set/Clear Pending Bit 633" "Not pending,Pending" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRPEND632 ,Set/Clear Pending Bit 632" "Not pending,Pending" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRPEND631 ,Set/Clear Pending Bit 631" "Not pending,Pending" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEND630 ,Set/Clear Pending Bit 630" "Not pending,Pending" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRPEND629 ,Set/Clear Pending Bit 629" "Not pending,Pending" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRPEND628 ,Set/Clear Pending Bit 628" "Not pending,Pending" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEND627 ,Set/Clear Pending Bit 627" "Not pending,Pending" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRPEND626 ,Set/Clear Pending Bit 626" "Not pending,Pending" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRPEND625 ,Set/Clear Pending Bit 625" "Not pending,Pending" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEND624 ,Set/Clear Pending Bit 624" "Not pending,Pending" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRPEND623 ,Set/Clear Pending Bit 623" "Not pending,Pending" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRPEND622 ,Set/Clear Pending Bit 622" "Not pending,Pending" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEND621 ,Set/Clear Pending Bit 621" "Not pending,Pending" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRPEND620 ,Set/Clear Pending Bit 620" "Not pending,Pending" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRPEND619 ,Set/Clear Pending Bit 619" "Not pending,Pending" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEND618 ,Set/Clear Pending Bit 618" "Not pending,Pending" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRPEND617 ,Set/Clear Pending Bit 617" "Not pending,Pending" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRPEND616 ,Set/Clear Pending Bit 616" "Not pending,Pending" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEND615 ,Set/Clear Pending Bit 615" "Not pending,Pending" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRPEND614 ,Set/Clear Pending Bit 614" "Not pending,Pending" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRPEND613 ,Set/Clear Pending Bit 613" "Not pending,Pending" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEND612 ,Set/Clear Pending Bit 612" "Not pending,Pending" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRPEND611 ,Set/Clear Pending Bit 611" "Not pending,Pending" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRPEND610 ,Set/Clear Pending Bit 610" "Not pending,Pending" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEND609 ,Set/Clear Pending Bit 609" "Not pending,Pending" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRPEND608 ,Set/Clear Pending Bit 608" "Not pending,Pending" else rgroup.long 0x024C++0x03 line.long 0x0 "GICD_SET/CLR_PENDR19,Interrupt Set/Clear Pending Register 19" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(ad:(per.long(spr:0x31F30)&0xFFFC0000)+0x04))&0x0000001F)>=0x14) group.long 0x0250++0x03 line.long 0x0 "GICD_SET/CLR_PENDR20,Interrupt Set/Clear Pending Register 20" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEND671 ,Set/Clear Pending Bit 671" "Not pending,Pending" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRPEND670 ,Set/Clear Pending Bit 670" "Not pending,Pending" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRPEND669 ,Set/Clear Pending Bit 669" "Not pending,Pending" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEND668 ,Set/Clear Pending Bit 668" "Not pending,Pending" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRPEND667 ,Set/Clear Pending Bit 667" "Not pending,Pending" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRPEND666 ,Set/Clear Pending Bit 666" "Not pending,Pending" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEND665 ,Set/Clear Pending Bit 665" "Not pending,Pending" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRPEND664 ,Set/Clear Pending Bit 664" "Not pending,Pending" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRPEND663 ,Set/Clear Pending Bit 663" "Not pending,Pending" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEND662 ,Set/Clear Pending Bit 662" "Not pending,Pending" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRPEND661 ,Set/Clear Pending Bit 661" "Not pending,Pending" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRPEND660 ,Set/Clear Pending Bit 660" "Not pending,Pending" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEND659 ,Set/Clear Pending Bit 659" "Not pending,Pending" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRPEND658 ,Set/Clear Pending Bit 658" "Not pending,Pending" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRPEND657 ,Set/Clear Pending Bit 657" "Not pending,Pending" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEND656 ,Set/Clear Pending Bit 656" "Not pending,Pending" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRPEND655 ,Set/Clear Pending Bit 655" "Not pending,Pending" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRPEND654 ,Set/Clear Pending Bit 654" "Not pending,Pending" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEND653 ,Set/Clear Pending Bit 653" "Not pending,Pending" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRPEND652 ,Set/Clear Pending Bit 652" "Not pending,Pending" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRPEND651 ,Set/Clear Pending Bit 651" "Not pending,Pending" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEND650 ,Set/Clear Pending Bit 650" "Not pending,Pending" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRPEND649 ,Set/Clear Pending Bit 649" "Not pending,Pending" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRPEND648 ,Set/Clear Pending Bit 648" "Not pending,Pending" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEND647 ,Set/Clear Pending Bit 647" "Not pending,Pending" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRPEND646 ,Set/Clear Pending Bit 646" "Not pending,Pending" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRPEND645 ,Set/Clear Pending Bit 645" "Not pending,Pending" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEND644 ,Set/Clear Pending Bit 644" "Not pending,Pending" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRPEND643 ,Set/Clear Pending Bit 643" "Not pending,Pending" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRPEND642 ,Set/Clear Pending Bit 642" "Not pending,Pending" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEND641 ,Set/Clear Pending Bit 641" "Not pending,Pending" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRPEND640 ,Set/Clear Pending Bit 640" "Not pending,Pending" else rgroup.long 0x0250++0x03 line.long 0x0 "GICD_SET/CLR_PENDR20,Interrupt Set/Clear Pending Register 20" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(ad:(per.long(spr:0x31F30)&0xFFFC0000)+0x04))&0x0000001F)>=0x15) group.long 0x0254++0x03 line.long 0x0 "GICD_SET/CLR_PENDR21,Interrupt Set/Clear Pending Register 21" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEND703 ,Set/Clear Pending Bit 703" "Not pending,Pending" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRPEND702 ,Set/Clear Pending Bit 702" "Not pending,Pending" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRPEND701 ,Set/Clear Pending Bit 701" "Not pending,Pending" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEND700 ,Set/Clear Pending Bit 700" "Not pending,Pending" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRPEND699 ,Set/Clear Pending Bit 699" "Not pending,Pending" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRPEND698 ,Set/Clear Pending Bit 698" "Not pending,Pending" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEND697 ,Set/Clear Pending Bit 697" "Not pending,Pending" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRPEND696 ,Set/Clear Pending Bit 696" "Not pending,Pending" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRPEND695 ,Set/Clear Pending Bit 695" "Not pending,Pending" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEND694 ,Set/Clear Pending Bit 694" "Not pending,Pending" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRPEND693 ,Set/Clear Pending Bit 693" "Not pending,Pending" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRPEND692 ,Set/Clear Pending Bit 692" "Not pending,Pending" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEND691 ,Set/Clear Pending Bit 691" "Not pending,Pending" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRPEND690 ,Set/Clear Pending Bit 690" "Not pending,Pending" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRPEND689 ,Set/Clear Pending Bit 689" "Not pending,Pending" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEND688 ,Set/Clear Pending Bit 688" "Not pending,Pending" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRPEND687 ,Set/Clear Pending Bit 687" "Not pending,Pending" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRPEND686 ,Set/Clear Pending Bit 686" "Not pending,Pending" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEND685 ,Set/Clear Pending Bit 685" "Not pending,Pending" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRPEND684 ,Set/Clear Pending Bit 684" "Not pending,Pending" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRPEND683 ,Set/Clear Pending Bit 683" "Not pending,Pending" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEND682 ,Set/Clear Pending Bit 682" "Not pending,Pending" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRPEND681 ,Set/Clear Pending Bit 681" "Not pending,Pending" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRPEND680 ,Set/Clear Pending Bit 680" "Not pending,Pending" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEND679 ,Set/Clear Pending Bit 679" "Not pending,Pending" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRPEND678 ,Set/Clear Pending Bit 678" "Not pending,Pending" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRPEND677 ,Set/Clear Pending Bit 677" "Not pending,Pending" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEND676 ,Set/Clear Pending Bit 676" "Not pending,Pending" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRPEND675 ,Set/Clear Pending Bit 675" "Not pending,Pending" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRPEND674 ,Set/Clear Pending Bit 674" "Not pending,Pending" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEND673 ,Set/Clear Pending Bit 673" "Not pending,Pending" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRPEND672 ,Set/Clear Pending Bit 672" "Not pending,Pending" else rgroup.long 0x0254++0x03 line.long 0x0 "GICD_SET/CLR_PENDR21,Interrupt Set/Clear Pending Register 21" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(ad:(per.long(spr:0x31F30)&0xFFFC0000)+0x04))&0x0000001F)>=0x16) group.long 0x0258++0x03 line.long 0x0 "GICD_SET/CLR_PENDR22,Interrupt Set/Clear Pending Register 22" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEND735 ,Set/Clear Pending Bit 735" "Not pending,Pending" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRPEND734 ,Set/Clear Pending Bit 734" "Not pending,Pending" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRPEND733 ,Set/Clear Pending Bit 733" "Not pending,Pending" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEND732 ,Set/Clear Pending Bit 732" "Not pending,Pending" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRPEND731 ,Set/Clear Pending Bit 731" "Not pending,Pending" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRPEND730 ,Set/Clear Pending Bit 730" "Not pending,Pending" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEND729 ,Set/Clear Pending Bit 729" "Not pending,Pending" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRPEND728 ,Set/Clear Pending Bit 728" "Not pending,Pending" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRPEND727 ,Set/Clear Pending Bit 727" "Not pending,Pending" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEND726 ,Set/Clear Pending Bit 726" "Not pending,Pending" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRPEND725 ,Set/Clear Pending Bit 725" "Not pending,Pending" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRPEND724 ,Set/Clear Pending Bit 724" "Not pending,Pending" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEND723 ,Set/Clear Pending Bit 723" "Not pending,Pending" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRPEND722 ,Set/Clear Pending Bit 722" "Not pending,Pending" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRPEND721 ,Set/Clear Pending Bit 721" "Not pending,Pending" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEND720 ,Set/Clear Pending Bit 720" "Not pending,Pending" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRPEND719 ,Set/Clear Pending Bit 719" "Not pending,Pending" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRPEND718 ,Set/Clear Pending Bit 718" "Not pending,Pending" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEND717 ,Set/Clear Pending Bit 717" "Not pending,Pending" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRPEND716 ,Set/Clear Pending Bit 716" "Not pending,Pending" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRPEND715 ,Set/Clear Pending Bit 715" "Not pending,Pending" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEND714 ,Set/Clear Pending Bit 714" "Not pending,Pending" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRPEND713 ,Set/Clear Pending Bit 713" "Not pending,Pending" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRPEND712 ,Set/Clear Pending Bit 712" "Not pending,Pending" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEND711 ,Set/Clear Pending Bit 711" "Not pending,Pending" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRPEND710 ,Set/Clear Pending Bit 710" "Not pending,Pending" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRPEND709 ,Set/Clear Pending Bit 709" "Not pending,Pending" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEND708 ,Set/Clear Pending Bit 708" "Not pending,Pending" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRPEND707 ,Set/Clear Pending Bit 707" "Not pending,Pending" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRPEND706 ,Set/Clear Pending Bit 706" "Not pending,Pending" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEND705 ,Set/Clear Pending Bit 705" "Not pending,Pending" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRPEND704 ,Set/Clear Pending Bit 704" "Not pending,Pending" else rgroup.long 0x0258++0x03 line.long 0x0 "GICD_SET/CLR_PENDR22,Interrupt Set/Clear Pending Register 22" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(ad:(per.long(spr:0x31F30)&0xFFFC0000)+0x04))&0x0000001F)>=0x17) group.long 0x025C++0x03 line.long 0x0 "GICD_SET/CLR_PENDR23,Interrupt Set/Clear Pending Register 23" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEND767 ,Set/Clear Pending Bit 767" "Not pending,Pending" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRPEND766 ,Set/Clear Pending Bit 766" "Not pending,Pending" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRPEND765 ,Set/Clear Pending Bit 765" "Not pending,Pending" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEND764 ,Set/Clear Pending Bit 764" "Not pending,Pending" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRPEND763 ,Set/Clear Pending Bit 763" "Not pending,Pending" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRPEND762 ,Set/Clear Pending Bit 762" "Not pending,Pending" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEND761 ,Set/Clear Pending Bit 761" "Not pending,Pending" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRPEND760 ,Set/Clear Pending Bit 760" "Not pending,Pending" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRPEND759 ,Set/Clear Pending Bit 759" "Not pending,Pending" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEND758 ,Set/Clear Pending Bit 758" "Not pending,Pending" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRPEND757 ,Set/Clear Pending Bit 757" "Not pending,Pending" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRPEND756 ,Set/Clear Pending Bit 756" "Not pending,Pending" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEND755 ,Set/Clear Pending Bit 755" "Not pending,Pending" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRPEND754 ,Set/Clear Pending Bit 754" "Not pending,Pending" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRPEND753 ,Set/Clear Pending Bit 753" "Not pending,Pending" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEND752 ,Set/Clear Pending Bit 752" "Not pending,Pending" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRPEND751 ,Set/Clear Pending Bit 751" "Not pending,Pending" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRPEND750 ,Set/Clear Pending Bit 750" "Not pending,Pending" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEND749 ,Set/Clear Pending Bit 749" "Not pending,Pending" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRPEND748 ,Set/Clear Pending Bit 748" "Not pending,Pending" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRPEND747 ,Set/Clear Pending Bit 747" "Not pending,Pending" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEND746 ,Set/Clear Pending Bit 746" "Not pending,Pending" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRPEND745 ,Set/Clear Pending Bit 745" "Not pending,Pending" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRPEND744 ,Set/Clear Pending Bit 744" "Not pending,Pending" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEND743 ,Set/Clear Pending Bit 743" "Not pending,Pending" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRPEND742 ,Set/Clear Pending Bit 742" "Not pending,Pending" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRPEND741 ,Set/Clear Pending Bit 741" "Not pending,Pending" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEND740 ,Set/Clear Pending Bit 740" "Not pending,Pending" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRPEND739 ,Set/Clear Pending Bit 739" "Not pending,Pending" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRPEND738 ,Set/Clear Pending Bit 738" "Not pending,Pending" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEND737 ,Set/Clear Pending Bit 737" "Not pending,Pending" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRPEND736 ,Set/Clear Pending Bit 736" "Not pending,Pending" else rgroup.long 0x025C++0x03 line.long 0x0 "GICD_SET/CLR_PENDR23,Interrupt Set/Clear Pending Register 23" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(ad:(per.long(spr:0x31F30)&0xFFFC0000)+0x04))&0x0000001F)>=0x18) group.long 0x0260++0x03 line.long 0x0 "GICD_SET/CLR_PENDR24,Interrupt Set/Clear Pending Register 24" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEND799 ,Set/Clear Pending Bit 799" "Not pending,Pending" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRPEND798 ,Set/Clear Pending Bit 798" "Not pending,Pending" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRPEND797 ,Set/Clear Pending Bit 797" "Not pending,Pending" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEND796 ,Set/Clear Pending Bit 796" "Not pending,Pending" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRPEND795 ,Set/Clear Pending Bit 795" "Not pending,Pending" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRPEND794 ,Set/Clear Pending Bit 794" "Not pending,Pending" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEND793 ,Set/Clear Pending Bit 793" "Not pending,Pending" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRPEND792 ,Set/Clear Pending Bit 792" "Not pending,Pending" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRPEND791 ,Set/Clear Pending Bit 791" "Not pending,Pending" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEND790 ,Set/Clear Pending Bit 790" "Not pending,Pending" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRPEND789 ,Set/Clear Pending Bit 789" "Not pending,Pending" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRPEND788 ,Set/Clear Pending Bit 788" "Not pending,Pending" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEND787 ,Set/Clear Pending Bit 787" "Not pending,Pending" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRPEND786 ,Set/Clear Pending Bit 786" "Not pending,Pending" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRPEND785 ,Set/Clear Pending Bit 785" "Not pending,Pending" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEND784 ,Set/Clear Pending Bit 784" "Not pending,Pending" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRPEND783 ,Set/Clear Pending Bit 783" "Not pending,Pending" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRPEND782 ,Set/Clear Pending Bit 782" "Not pending,Pending" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEND781 ,Set/Clear Pending Bit 781" "Not pending,Pending" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRPEND780 ,Set/Clear Pending Bit 780" "Not pending,Pending" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRPEND779 ,Set/Clear Pending Bit 779" "Not pending,Pending" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEND778 ,Set/Clear Pending Bit 778" "Not pending,Pending" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRPEND777 ,Set/Clear Pending Bit 777" "Not pending,Pending" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRPEND776 ,Set/Clear Pending Bit 776" "Not pending,Pending" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEND775 ,Set/Clear Pending Bit 775" "Not pending,Pending" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRPEND774 ,Set/Clear Pending Bit 774" "Not pending,Pending" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRPEND773 ,Set/Clear Pending Bit 773" "Not pending,Pending" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEND772 ,Set/Clear Pending Bit 772" "Not pending,Pending" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRPEND771 ,Set/Clear Pending Bit 771" "Not pending,Pending" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRPEND770 ,Set/Clear Pending Bit 770" "Not pending,Pending" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEND769 ,Set/Clear Pending Bit 769" "Not pending,Pending" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRPEND768 ,Set/Clear Pending Bit 768" "Not pending,Pending" else rgroup.long 0x0260++0x03 line.long 0x0 "GICD_SET/CLR_PENDR24,Interrupt Set/Clear Pending Register 24" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(ad:(per.long(spr:0x31F30)&0xFFFC0000)+0x04))&0x0000001F)>=0x19) group.long 0x0264++0x03 line.long 0x0 "GICD_SET/CLR_PENDR25,Interrupt Set/Clear Pending Register 25" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEND831 ,Set/Clear Pending Bit 831" "Not pending,Pending" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRPEND830 ,Set/Clear Pending Bit 830" "Not pending,Pending" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRPEND829 ,Set/Clear Pending Bit 829" "Not pending,Pending" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEND828 ,Set/Clear Pending Bit 828" "Not pending,Pending" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRPEND827 ,Set/Clear Pending Bit 827" "Not pending,Pending" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRPEND826 ,Set/Clear Pending Bit 826" "Not pending,Pending" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEND825 ,Set/Clear Pending Bit 825" "Not pending,Pending" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRPEND824 ,Set/Clear Pending Bit 824" "Not pending,Pending" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRPEND823 ,Set/Clear Pending Bit 823" "Not pending,Pending" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEND822 ,Set/Clear Pending Bit 822" "Not pending,Pending" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRPEND821 ,Set/Clear Pending Bit 821" "Not pending,Pending" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRPEND820 ,Set/Clear Pending Bit 820" "Not pending,Pending" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEND819 ,Set/Clear Pending Bit 819" "Not pending,Pending" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRPEND818 ,Set/Clear Pending Bit 818" "Not pending,Pending" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRPEND817 ,Set/Clear Pending Bit 817" "Not pending,Pending" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEND816 ,Set/Clear Pending Bit 816" "Not pending,Pending" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRPEND815 ,Set/Clear Pending Bit 815" "Not pending,Pending" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRPEND814 ,Set/Clear Pending Bit 814" "Not pending,Pending" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEND813 ,Set/Clear Pending Bit 813" "Not pending,Pending" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRPEND812 ,Set/Clear Pending Bit 812" "Not pending,Pending" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRPEND811 ,Set/Clear Pending Bit 811" "Not pending,Pending" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEND810 ,Set/Clear Pending Bit 810" "Not pending,Pending" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRPEND809 ,Set/Clear Pending Bit 809" "Not pending,Pending" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRPEND808 ,Set/Clear Pending Bit 808" "Not pending,Pending" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEND807 ,Set/Clear Pending Bit 807" "Not pending,Pending" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRPEND806 ,Set/Clear Pending Bit 806" "Not pending,Pending" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRPEND805 ,Set/Clear Pending Bit 805" "Not pending,Pending" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEND804 ,Set/Clear Pending Bit 804" "Not pending,Pending" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRPEND803 ,Set/Clear Pending Bit 803" "Not pending,Pending" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRPEND802 ,Set/Clear Pending Bit 802" "Not pending,Pending" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEND801 ,Set/Clear Pending Bit 801" "Not pending,Pending" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRPEND800 ,Set/Clear Pending Bit 800" "Not pending,Pending" else rgroup.long 0x0264++0x03 line.long 0x0 "GICD_SET/CLR_PENDR25,Interrupt Set/Clear Pending Register 25" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(ad:(per.long(spr:0x31F30)&0xFFFC0000)+0x04))&0x0000001F)>=0x1A) group.long 0x0268++0x03 line.long 0x0 "GICD_SET/CLR_PENDR26,Interrupt Set/Clear Pending Register 26" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEND863 ,Set/Clear Pending Bit 863" "Not pending,Pending" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRPEND862 ,Set/Clear Pending Bit 862" "Not pending,Pending" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRPEND861 ,Set/Clear Pending Bit 861" "Not pending,Pending" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEND860 ,Set/Clear Pending Bit 860" "Not pending,Pending" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRPEND859 ,Set/Clear Pending Bit 859" "Not pending,Pending" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRPEND858 ,Set/Clear Pending Bit 858" "Not pending,Pending" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEND857 ,Set/Clear Pending Bit 857" "Not pending,Pending" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRPEND856 ,Set/Clear Pending Bit 856" "Not pending,Pending" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRPEND855 ,Set/Clear Pending Bit 855" "Not pending,Pending" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEND854 ,Set/Clear Pending Bit 854" "Not pending,Pending" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRPEND853 ,Set/Clear Pending Bit 853" "Not pending,Pending" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRPEND852 ,Set/Clear Pending Bit 852" "Not pending,Pending" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEND851 ,Set/Clear Pending Bit 851" "Not pending,Pending" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRPEND850 ,Set/Clear Pending Bit 850" "Not pending,Pending" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRPEND849 ,Set/Clear Pending Bit 849" "Not pending,Pending" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEND848 ,Set/Clear Pending Bit 848" "Not pending,Pending" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRPEND847 ,Set/Clear Pending Bit 847" "Not pending,Pending" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRPEND846 ,Set/Clear Pending Bit 846" "Not pending,Pending" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEND845 ,Set/Clear Pending Bit 845" "Not pending,Pending" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRPEND844 ,Set/Clear Pending Bit 844" "Not pending,Pending" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRPEND843 ,Set/Clear Pending Bit 843" "Not pending,Pending" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEND842 ,Set/Clear Pending Bit 842" "Not pending,Pending" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRPEND841 ,Set/Clear Pending Bit 841" "Not pending,Pending" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRPEND840 ,Set/Clear Pending Bit 840" "Not pending,Pending" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEND839 ,Set/Clear Pending Bit 839" "Not pending,Pending" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRPEND838 ,Set/Clear Pending Bit 838" "Not pending,Pending" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRPEND837 ,Set/Clear Pending Bit 837" "Not pending,Pending" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEND836 ,Set/Clear Pending Bit 836" "Not pending,Pending" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRPEND835 ,Set/Clear Pending Bit 835" "Not pending,Pending" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRPEND834 ,Set/Clear Pending Bit 834" "Not pending,Pending" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEND833 ,Set/Clear Pending Bit 833" "Not pending,Pending" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRPEND832 ,Set/Clear Pending Bit 832" "Not pending,Pending" else rgroup.long 0x0268++0x03 line.long 0x0 "GICD_SET/CLR_PENDR26,Interrupt Set/Clear Pending Register 26" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(ad:(per.long(spr:0x31F30)&0xFFFC0000)+0x04))&0x0000001F)>=0x1B) group.long 0x026C++0x03 line.long 0x0 "GICD_SET/CLR_PENDR27,Interrupt Set/Clear Pending Register 27" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEND895 ,Set/Clear Pending Bit 895" "Not pending,Pending" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRPEND894 ,Set/Clear Pending Bit 894" "Not pending,Pending" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRPEND893 ,Set/Clear Pending Bit 893" "Not pending,Pending" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEND892 ,Set/Clear Pending Bit 892" "Not pending,Pending" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRPEND891 ,Set/Clear Pending Bit 891" "Not pending,Pending" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRPEND890 ,Set/Clear Pending Bit 890" "Not pending,Pending" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEND889 ,Set/Clear Pending Bit 889" "Not pending,Pending" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRPEND888 ,Set/Clear Pending Bit 888" "Not pending,Pending" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRPEND887 ,Set/Clear Pending Bit 887" "Not pending,Pending" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEND886 ,Set/Clear Pending Bit 886" "Not pending,Pending" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRPEND885 ,Set/Clear Pending Bit 885" "Not pending,Pending" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRPEND884 ,Set/Clear Pending Bit 884" "Not pending,Pending" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEND883 ,Set/Clear Pending Bit 883" "Not pending,Pending" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRPEND882 ,Set/Clear Pending Bit 882" "Not pending,Pending" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRPEND881 ,Set/Clear Pending Bit 881" "Not pending,Pending" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEND880 ,Set/Clear Pending Bit 880" "Not pending,Pending" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRPEND879 ,Set/Clear Pending Bit 879" "Not pending,Pending" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRPEND878 ,Set/Clear Pending Bit 878" "Not pending,Pending" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEND877 ,Set/Clear Pending Bit 877" "Not pending,Pending" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRPEND876 ,Set/Clear Pending Bit 876" "Not pending,Pending" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRPEND875 ,Set/Clear Pending Bit 875" "Not pending,Pending" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEND874 ,Set/Clear Pending Bit 874" "Not pending,Pending" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRPEND873 ,Set/Clear Pending Bit 873" "Not pending,Pending" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRPEND872 ,Set/Clear Pending Bit 872" "Not pending,Pending" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEND871 ,Set/Clear Pending Bit 871" "Not pending,Pending" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRPEND870 ,Set/Clear Pending Bit 870" "Not pending,Pending" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRPEND869 ,Set/Clear Pending Bit 869" "Not pending,Pending" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEND868 ,Set/Clear Pending Bit 868" "Not pending,Pending" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRPEND867 ,Set/Clear Pending Bit 867" "Not pending,Pending" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRPEND866 ,Set/Clear Pending Bit 866" "Not pending,Pending" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEND865 ,Set/Clear Pending Bit 865" "Not pending,Pending" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRPEND864 ,Set/Clear Pending Bit 864" "Not pending,Pending" else rgroup.long 0x026C++0x03 line.long 0x0 "GICD_SET/CLR_PENDR27,Interrupt Set/Clear Pending Register 27" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(ad:(per.long(spr:0x31F30)&0xFFFC0000)+0x04))&0x0000001F)>=0x1C) group.long 0x0270++0x03 line.long 0x0 "GICD_SET/CLR_PENDR28,Interrupt Set/Clear Pending Register 28" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEND927 ,Set/Clear Pending Bit 927" "Not pending,Pending" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRPEND926 ,Set/Clear Pending Bit 926" "Not pending,Pending" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRPEND925 ,Set/Clear Pending Bit 925" "Not pending,Pending" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEND924 ,Set/Clear Pending Bit 924" "Not pending,Pending" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRPEND923 ,Set/Clear Pending Bit 923" "Not pending,Pending" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRPEND922 ,Set/Clear Pending Bit 922" "Not pending,Pending" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEND921 ,Set/Clear Pending Bit 921" "Not pending,Pending" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRPEND920 ,Set/Clear Pending Bit 920" "Not pending,Pending" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRPEND919 ,Set/Clear Pending Bit 919" "Not pending,Pending" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEND918 ,Set/Clear Pending Bit 918" "Not pending,Pending" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRPEND917 ,Set/Clear Pending Bit 917" "Not pending,Pending" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRPEND916 ,Set/Clear Pending Bit 916" "Not pending,Pending" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEND915 ,Set/Clear Pending Bit 915" "Not pending,Pending" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRPEND914 ,Set/Clear Pending Bit 914" "Not pending,Pending" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRPEND913 ,Set/Clear Pending Bit 913" "Not pending,Pending" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEND912 ,Set/Clear Pending Bit 912" "Not pending,Pending" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRPEND911 ,Set/Clear Pending Bit 911" "Not pending,Pending" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRPEND910 ,Set/Clear Pending Bit 910" "Not pending,Pending" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEND909 ,Set/Clear Pending Bit 909" "Not pending,Pending" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRPEND908 ,Set/Clear Pending Bit 908" "Not pending,Pending" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRPEND907 ,Set/Clear Pending Bit 907" "Not pending,Pending" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEND906 ,Set/Clear Pending Bit 906" "Not pending,Pending" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRPEND905 ,Set/Clear Pending Bit 905" "Not pending,Pending" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRPEND904 ,Set/Clear Pending Bit 904" "Not pending,Pending" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEND903 ,Set/Clear Pending Bit 903" "Not pending,Pending" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRPEND902 ,Set/Clear Pending Bit 902" "Not pending,Pending" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRPEND901 ,Set/Clear Pending Bit 901" "Not pending,Pending" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEND900 ,Set/Clear Pending Bit 900" "Not pending,Pending" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRPEND899 ,Set/Clear Pending Bit 899" "Not pending,Pending" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRPEND898 ,Set/Clear Pending Bit 898" "Not pending,Pending" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEND897 ,Set/Clear Pending Bit 897" "Not pending,Pending" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRPEND896 ,Set/Clear Pending Bit 896" "Not pending,Pending" else rgroup.long 0x0270++0x03 line.long 0x0 "GICD_SET/CLR_PENDR28,Interrupt Set/Clear Pending Register 28" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(ad:(per.long(spr:0x31F30)&0xFFFC0000)+0x04))&0x0000001F)>=0x1D) group.long 0x0274++0x03 line.long 0x0 "GICD_SET/CLR_PENDR29,Interrupt Set/Clear Pending Register 29" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEND959 ,Set/Clear Pending Bit 959" "Not pending,Pending" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRPEND958 ,Set/Clear Pending Bit 958" "Not pending,Pending" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRPEND957 ,Set/Clear Pending Bit 957" "Not pending,Pending" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEND956 ,Set/Clear Pending Bit 956" "Not pending,Pending" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRPEND955 ,Set/Clear Pending Bit 955" "Not pending,Pending" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRPEND954 ,Set/Clear Pending Bit 954" "Not pending,Pending" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEND953 ,Set/Clear Pending Bit 953" "Not pending,Pending" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRPEND952 ,Set/Clear Pending Bit 952" "Not pending,Pending" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRPEND951 ,Set/Clear Pending Bit 951" "Not pending,Pending" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEND950 ,Set/Clear Pending Bit 950" "Not pending,Pending" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRPEND949 ,Set/Clear Pending Bit 949" "Not pending,Pending" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRPEND948 ,Set/Clear Pending Bit 948" "Not pending,Pending" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEND947 ,Set/Clear Pending Bit 947" "Not pending,Pending" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRPEND946 ,Set/Clear Pending Bit 946" "Not pending,Pending" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRPEND945 ,Set/Clear Pending Bit 945" "Not pending,Pending" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEND944 ,Set/Clear Pending Bit 944" "Not pending,Pending" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRPEND943 ,Set/Clear Pending Bit 943" "Not pending,Pending" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRPEND942 ,Set/Clear Pending Bit 942" "Not pending,Pending" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEND941 ,Set/Clear Pending Bit 941" "Not pending,Pending" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRPEND940 ,Set/Clear Pending Bit 940" "Not pending,Pending" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRPEND939 ,Set/Clear Pending Bit 939" "Not pending,Pending" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEND938 ,Set/Clear Pending Bit 938" "Not pending,Pending" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRPEND937 ,Set/Clear Pending Bit 937" "Not pending,Pending" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRPEND936 ,Set/Clear Pending Bit 936" "Not pending,Pending" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEND935 ,Set/Clear Pending Bit 935" "Not pending,Pending" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRPEND934 ,Set/Clear Pending Bit 934" "Not pending,Pending" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRPEND933 ,Set/Clear Pending Bit 933" "Not pending,Pending" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEND932 ,Set/Clear Pending Bit 932" "Not pending,Pending" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRPEND931 ,Set/Clear Pending Bit 931" "Not pending,Pending" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRPEND930 ,Set/Clear Pending Bit 930" "Not pending,Pending" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEND929 ,Set/Clear Pending Bit 929" "Not pending,Pending" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRPEND928 ,Set/Clear Pending Bit 928" "Not pending,Pending" else rgroup.long 0x0274++0x03 line.long 0x0 "GICD_SET/CLR_PENDR29,Interrupt Set/Clear Pending Register 29" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(ad:(per.long(spr:0x31F30)&0xFFFC0000)+0x04))&0x0000001F)>=0x1E) group.long 0x0278++0x03 line.long 0x0 "GICD_SET/CLR_PENDR30,Interrupt Set/Clear Pending Register 30" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRPEND991 ,Set/Clear Pending Bit 991" "Not pending,Pending" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRPEND990 ,Set/Clear Pending Bit 990" "Not pending,Pending" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRPEND989 ,Set/Clear Pending Bit 989" "Not pending,Pending" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRPEND988 ,Set/Clear Pending Bit 988" "Not pending,Pending" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRPEND987 ,Set/Clear Pending Bit 987" "Not pending,Pending" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRPEND986 ,Set/Clear Pending Bit 986" "Not pending,Pending" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEND985 ,Set/Clear Pending Bit 985" "Not pending,Pending" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRPEND984 ,Set/Clear Pending Bit 984" "Not pending,Pending" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRPEND983 ,Set/Clear Pending Bit 983" "Not pending,Pending" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEND982 ,Set/Clear Pending Bit 982" "Not pending,Pending" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRPEND981 ,Set/Clear Pending Bit 981" "Not pending,Pending" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRPEND980 ,Set/Clear Pending Bit 980" "Not pending,Pending" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEND979 ,Set/Clear Pending Bit 979" "Not pending,Pending" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRPEND978 ,Set/Clear Pending Bit 978" "Not pending,Pending" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRPEND977 ,Set/Clear Pending Bit 977" "Not pending,Pending" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEND976 ,Set/Clear Pending Bit 976" "Not pending,Pending" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRPEND975 ,Set/Clear Pending Bit 975" "Not pending,Pending" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRPEND974 ,Set/Clear Pending Bit 974" "Not pending,Pending" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEND973 ,Set/Clear Pending Bit 973" "Not pending,Pending" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRPEND972 ,Set/Clear Pending Bit 972" "Not pending,Pending" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRPEND971 ,Set/Clear Pending Bit 971" "Not pending,Pending" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEND970 ,Set/Clear Pending Bit 970" "Not pending,Pending" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRPEND969 ,Set/Clear Pending Bit 969" "Not pending,Pending" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRPEND968 ,Set/Clear Pending Bit 968" "Not pending,Pending" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEND967 ,Set/Clear Pending Bit 967" "Not pending,Pending" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRPEND966 ,Set/Clear Pending Bit 966" "Not pending,Pending" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRPEND965 ,Set/Clear Pending Bit 965" "Not pending,Pending" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEND964 ,Set/Clear Pending Bit 964" "Not pending,Pending" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRPEND963 ,Set/Clear Pending Bit 963" "Not pending,Pending" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRPEND962 ,Set/Clear Pending Bit 962" "Not pending,Pending" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEND961 ,Set/Clear Pending Bit 961" "Not pending,Pending" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRPEND960 ,Set/Clear Pending Bit 960" "Not pending,Pending" else rgroup.long 0x0278++0x03 line.long 0x0 "GICD_SET/CLR_PENDR30,Interrupt Set/Clear Pending Register 30" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(ad:(per.long(spr:0x31F30)&0xFFFC0000)+0x04))&0x0000001F)==0x1F) group.long 0x027C++0x03 line.long 0x0 "GICD_SET/CLR_PENDR31,Interrupt Set/Clear Pending Register 31" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRPEND1019 ,Set/Clear Pending Bit 1019" "Not pending,Pending" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRPEND1018 ,Set/Clear Pending Bit 1018" "Not pending,Pending" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRPEND1017 ,Set/Clear Pending Bit 1017" "Not pending,Pending" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRPEND1016 ,Set/Clear Pending Bit 1016" "Not pending,Pending" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRPEND1015 ,Set/Clear Pending Bit 1015" "Not pending,Pending" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRPEND1014 ,Set/Clear Pending Bit 1014" "Not pending,Pending" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRPEND1013 ,Set/Clear Pending Bit 1013" "Not pending,Pending" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRPEND1012 ,Set/Clear Pending Bit 1012" "Not pending,Pending" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRPEND1011 ,Set/Clear Pending Bit 1011" "Not pending,Pending" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRPEND1010 ,Set/Clear Pending Bit 1010" "Not pending,Pending" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRPEND1009 ,Set/Clear Pending Bit 1009" "Not pending,Pending" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRPEND1008 ,Set/Clear Pending Bit 1008" "Not pending,Pending" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRPEND1007 ,Set/Clear Pending Bit 1007" "Not pending,Pending" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRPEND1006 ,Set/Clear Pending Bit 1006" "Not pending,Pending" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRPEND1005 ,Set/Clear Pending Bit 1005" "Not pending,Pending" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRPEND1004 ,Set/Clear Pending Bit 1004" "Not pending,Pending" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRPEND1003 ,Set/Clear Pending Bit 1003" "Not pending,Pending" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRPEND1002 ,Set/Clear Pending Bit 1002" "Not pending,Pending" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRPEND1001 ,Set/Clear Pending Bit 1001" "Not pending,Pending" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRPEND1000 ,Set/Clear Pending Bit 1000" "Not pending,Pending" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRPEND999 ,Set/Clear Pending Bit 999" "Not pending,Pending" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRPEND998 ,Set/Clear Pending Bit 998" "Not pending,Pending" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRPEND997 ,Set/Clear Pending Bit 997" "Not pending,Pending" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRPEND996 ,Set/Clear Pending Bit 996" "Not pending,Pending" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRPEND995 ,Set/Clear Pending Bit 995" "Not pending,Pending" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRPEND994 ,Set/Clear Pending Bit 994" "Not pending,Pending" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRPEND993 ,Set/Clear Pending Bit 993" "Not pending,Pending" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRPEND992 ,Set/Clear Pending Bit 992" "Not pending,Pending" else rgroup.long 0x027C++0x03 line.long 0x0 "GICD_SET/CLR_PENDR31,Interrupt Set/Clear Pending Register 31" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif tree.end width 24. tree "Set/Clear Active Registers" if (((per.l(ad:(per.long(spr:0x31F30)&0xFFFC0000)+0x08))&0xFF000000)==(0x0000000||0x1000000)) rgroup.long 0x0300++0x03 line.long 0x0 "GICD_ICDABR0,Active Status Register 0" bitfld.long 0x00 31. " ASB31 ,Active Status Bit 31" "Not active,Active" bitfld.long 0x00 30. " ASB30 ,Active Status Bit 30" "Not active,Active" bitfld.long 0x00 29. " ASB29 ,Active Status Bit 29" "Not active,Active" textline " " bitfld.long 0x00 28. " ASB28 ,Active Status Bit 28" "Not active,Active" bitfld.long 0x00 27. " ASB27 ,Active Status Bit 27" "Not active,Active" bitfld.long 0x00 26. " ASB26 ,Active Status Bit 26" "Not active,Active" textline " " bitfld.long 0x00 25. " ASB25 ,Active Status Bit 25" "Not active,Active" bitfld.long 0x00 24. " ASB24 ,Active Status Bit 24" "Not active,Active" bitfld.long 0x00 23. " ASB23 ,Active Status Bit 23" "Not active,Active" textline " " bitfld.long 0x00 22. " ASB22 ,Active Status Bit 22" "Not active,Active" bitfld.long 0x00 21. " ASB21 ,Active Status Bit 21" "Not active,Active" bitfld.long 0x00 20. " ASB20 ,Active Status Bit 20" "Not active,Active" textline " " bitfld.long 0x00 19. " ASB19 ,Active Status Bit 19" "Not active,Active" bitfld.long 0x00 18. " ASB18 ,Active Status Bit 18" "Not active,Active" bitfld.long 0x00 17. " ASB17 ,Active Status Bit 17" "Not active,Active" textline " " bitfld.long 0x00 16. " ASB16 ,Active Status Bit 16" "Not active,Active" bitfld.long 0x00 15. " ASB15 ,Active Status Bit 15" "Not active,Active" bitfld.long 0x00 14. " ASB14 ,Active Status Bit 14" "Not active,Active" textline " " bitfld.long 0x00 13. " ASB13 ,Active Status Bit 13" "Not active,Active" bitfld.long 0x00 12. " ASB12 ,Active Status Bit 12" "Not active,Active" bitfld.long 0x00 11. " ASB11 ,Active Status Bit 11" "Not active,Active" textline " " bitfld.long 0x00 10. " ASB10 ,Active Status Bit 10" "Not active,Active" bitfld.long 0x00 9. " ASB9 ,Active Status Bit 9" "Not active,Active" bitfld.long 0x00 8. " ASB8 ,Active Status Bit 8" "Not active,Active" textline " " bitfld.long 0x00 7. " ASB7 ,Active Status Bit 7" "Not active,Active" bitfld.long 0x00 6. " ASB6 ,Active Status Bit 6" "Not active,Active" bitfld.long 0x00 5. " ASB5 ,Active Status Bit 5" "Not active,Active" textline " " bitfld.long 0x00 4. " ASB4 ,Active Status Bit 4" "Not active,Active" bitfld.long 0x00 3. " ASB3 ,Active Status Bit 3" "Not active,Active" bitfld.long 0x00 2. " ASB2 ,Active Status Bit 2" "Not active,Active" textline " " bitfld.long 0x00 1. " ASB1 ,Active Status Bit 1" "Not active,Active" bitfld.long 0x00 0. " ASB0 ,Active Status Bit 0" "Not active,Active" if (((per.l(ad:(per.long(spr:0x31F30)&0xFFFC0000)+0x04))&0x0000001F)>=0x01) rgroup.long 0x0304++0x03 line.long 0x0 "GICD_ICDABR1,Active Status Register 1" bitfld.long 0x00 31. " ASB63 ,Active Status Bit 63" "Not active,Active" bitfld.long 0x00 30. " ASB62 ,Active Status Bit 62" "Not active,Active" bitfld.long 0x00 29. " ASB61 ,Active Status Bit 61" "Not active,Active" textline " " bitfld.long 0x00 28. " ASB60 ,Active Status Bit 60" "Not active,Active" bitfld.long 0x00 27. " ASB59 ,Active Status Bit 59" "Not active,Active" bitfld.long 0x00 26. " ASB58 ,Active Status Bit 58" "Not active,Active" textline " " bitfld.long 0x00 25. " ASB57 ,Active Status Bit 57" "Not active,Active" bitfld.long 0x00 24. " ASB56 ,Active Status Bit 56" "Not active,Active" bitfld.long 0x00 23. " ASB55 ,Active Status Bit 55" "Not active,Active" textline " " bitfld.long 0x00 22. " ASB54 ,Active Status Bit 54" "Not active,Active" bitfld.long 0x00 21. " ASB53 ,Active Status Bit 53" "Not active,Active" bitfld.long 0x00 20. " ASB52 ,Active Status Bit 52" "Not active,Active" textline " " bitfld.long 0x00 19. " ASB51 ,Active Status Bit 51" "Not active,Active" bitfld.long 0x00 18. " ASB50 ,Active Status Bit 50" "Not active,Active" bitfld.long 0x00 17. " ASB49 ,Active Status Bit 49" "Not active,Active" textline " " bitfld.long 0x00 16. " ASB48 ,Active Status Bit 48" "Not active,Active" bitfld.long 0x00 15. " ASB47 ,Active Status Bit 47" "Not active,Active" bitfld.long 0x00 14. " ASB46 ,Active Status Bit 46" "Not active,Active" textline " " bitfld.long 0x00 13. " ASB45 ,Active Status Bit 45" "Not active,Active" bitfld.long 0x00 12. " ASB44 ,Active Status Bit 44" "Not active,Active" bitfld.long 0x00 11. " ASB43 ,Active Status Bit 43" "Not active,Active" textline " " bitfld.long 0x00 10. " ASB42 ,Active Status Bit 42" "Not active,Active" bitfld.long 0x00 9. " ASB41 ,Active Status Bit 41" "Not active,Active" bitfld.long 0x00 8. " ASB40 ,Active Status Bit 40" "Not active,Active" textline " " bitfld.long 0x00 7. " ASB39 ,Active Status Bit 39" "Not active,Active" bitfld.long 0x00 6. " ASB38 ,Active Status Bit 38" "Not active,Active" bitfld.long 0x00 5. " ASB37 ,Active Status Bit 37" "Not active,Active" textline " " bitfld.long 0x00 4. " ASB36 ,Active Status Bit 36" "Not active,Active" bitfld.long 0x00 3. " ASB35 ,Active Status Bit 35" "Not active,Active" bitfld.long 0x00 2. " ASB34 ,Active Status Bit 34" "Not active,Active" textline " " bitfld.long 0x00 1. " ASB33 ,Active Status Bit 33" "Not active,Active" bitfld.long 0x00 0. " ASB32 ,Active Status Bit 32" "Not active,Active" else rgroup.long 0x0304++0x03 line.long 0x0 "GICD_ICDABR1,Active Status Register 1" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(ad:(per.long(spr:0x31F30)&0xFFFC0000)+0x04))&0x0000001F)>=0x02) rgroup.long 0x0308++0x03 line.long 0x0 "GICD_ICDABR2,Active Status Register 2" bitfld.long 0x00 31. " ASB95 ,Active Status Bit 95" "Not active,Active" bitfld.long 0x00 30. " ASB94 ,Active Status Bit 94" "Not active,Active" bitfld.long 0x00 29. " ASB93 ,Active Status Bit 93" "Not active,Active" textline " " bitfld.long 0x00 28. " ASB92 ,Active Status Bit 92" "Not active,Active" bitfld.long 0x00 27. " ASB91 ,Active Status Bit 91" "Not active,Active" bitfld.long 0x00 26. " ASB90 ,Active Status Bit 90" "Not active,Active" textline " " bitfld.long 0x00 25. " ASB89 ,Active Status Bit 89" "Not active,Active" bitfld.long 0x00 24. " ASB88 ,Active Status Bit 88" "Not active,Active" bitfld.long 0x00 23. " ASB87 ,Active Status Bit 87" "Not active,Active" textline " " bitfld.long 0x00 22. " ASB86 ,Active Status Bit 86" "Not active,Active" bitfld.long 0x00 21. " ASB85 ,Active Status Bit 85" "Not active,Active" bitfld.long 0x00 20. " ASB84 ,Active Status Bit 84" "Not active,Active" textline " " bitfld.long 0x00 19. " ASB83 ,Active Status Bit 83" "Not active,Active" bitfld.long 0x00 18. " ASB82 ,Active Status Bit 82" "Not active,Active" bitfld.long 0x00 17. " ASB81 ,Active Status Bit 81" "Not active,Active" textline " " bitfld.long 0x00 16. " ASB80 ,Active Status Bit 80" "Not active,Active" bitfld.long 0x00 15. " ASB79 ,Active Status Bit 79" "Not active,Active" bitfld.long 0x00 14. " ASB78 ,Active Status Bit 78" "Not active,Active" textline " " bitfld.long 0x00 13. " ASB77 ,Active Status Bit 77" "Not active,Active" bitfld.long 0x00 12. " ASB76 ,Active Status Bit 76" "Not active,Active" bitfld.long 0x00 11. " ASB75 ,Active Status Bit 75" "Not active,Active" textline " " bitfld.long 0x00 10. " ASB74 ,Active Status Bit 74" "Not active,Active" bitfld.long 0x00 9. " ASB73 ,Active Status Bit 73" "Not active,Active" bitfld.long 0x00 8. " ASB72 ,Active Status Bit 72" "Not active,Active" textline " " bitfld.long 0x00 7. " ASB71 ,Active Status Bit 71" "Not active,Active" bitfld.long 0x00 6. " ASB70 ,Active Status Bit 70" "Not active,Active" bitfld.long 0x00 5. " ASB69 ,Active Status Bit 69" "Not active,Active" textline " " bitfld.long 0x00 4. " ASB68 ,Active Status Bit 68" "Not active,Active" bitfld.long 0x00 3. " ASB67 ,Active Status Bit 67" "Not active,Active" bitfld.long 0x00 2. " ASB66 ,Active Status Bit 66" "Not active,Active" textline " " bitfld.long 0x00 1. " ASB65 ,Active Status Bit 65" "Not active,Active" bitfld.long 0x00 0. " ASB64 ,Active Status Bit 64" "Not active,Active" else rgroup.long 0x0308++0x03 line.long 0x0 "GICD_ICDABR2,Active Status Register 2" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(ad:(per.long(spr:0x31F30)&0xFFFC0000)+0x04))&0x0000001F)>=0x03) rgroup.long 0x030C++0x03 line.long 0x0 "GICD_ICDABR3,Active Status Register 3" bitfld.long 0x00 31. " ASB127 ,Active Status Bit 127" "Not active,Active" bitfld.long 0x00 30. " ASB126 ,Active Status Bit 126" "Not active,Active" bitfld.long 0x00 29. " ASB125 ,Active Status Bit 125" "Not active,Active" textline " " bitfld.long 0x00 28. " ASB124 ,Active Status Bit 124" "Not active,Active" bitfld.long 0x00 27. " ASB123 ,Active Status Bit 123" "Not active,Active" bitfld.long 0x00 26. " ASB122 ,Active Status Bit 122" "Not active,Active" textline " " bitfld.long 0x00 25. " ASB121 ,Active Status Bit 121" "Not active,Active" bitfld.long 0x00 24. " ASB120 ,Active Status Bit 120" "Not active,Active" bitfld.long 0x00 23. " ASB119 ,Active Status Bit 119" "Not active,Active" textline " " bitfld.long 0x00 22. " ASB118 ,Active Status Bit 118" "Not active,Active" bitfld.long 0x00 21. " ASB117 ,Active Status Bit 117" "Not active,Active" bitfld.long 0x00 20. " ASB116 ,Active Status Bit 116" "Not active,Active" textline " " bitfld.long 0x00 19. " ASB115 ,Active Status Bit 115" "Not active,Active" bitfld.long 0x00 18. " ASB114 ,Active Status Bit 114" "Not active,Active" bitfld.long 0x00 17. " ASB113 ,Active Status Bit 113" "Not active,Active" textline " " bitfld.long 0x00 16. " ASB112 ,Active Status Bit 112" "Not active,Active" bitfld.long 0x00 15. " ASB111 ,Active Status Bit 111" "Not active,Active" bitfld.long 0x00 14. " ASB110 ,Active Status Bit 110" "Not active,Active" textline " " bitfld.long 0x00 13. " ASB109 ,Active Status Bit 109" "Not active,Active" bitfld.long 0x00 12. " ASB108 ,Active Status Bit 108" "Not active,Active" bitfld.long 0x00 11. " ASB107 ,Active Status Bit 107" "Not active,Active" textline " " bitfld.long 0x00 10. " ASB106 ,Active Status Bit 106" "Not active,Active" bitfld.long 0x00 9. " ASB105 ,Active Status Bit 105" "Not active,Active" bitfld.long 0x00 8. " ASB104 ,Active Status Bit 104" "Not active,Active" textline " " bitfld.long 0x00 7. " ASB103 ,Active Status Bit 103" "Not active,Active" bitfld.long 0x00 6. " ASB102 ,Active Status Bit 102" "Not active,Active" bitfld.long 0x00 5. " ASB101 ,Active Status Bit 101" "Not active,Active" textline " " bitfld.long 0x00 4. " ASB100 ,Active Status Bit 100" "Not active,Active" bitfld.long 0x00 3. " ASB99 ,Active Status Bit 99" "Not active,Active" bitfld.long 0x00 2. " ASB98 ,Active Status Bit 98" "Not active,Active" textline " " bitfld.long 0x00 1. " ASB97 ,Active Status Bit 97" "Not active,Active" bitfld.long 0x00 0. " ASB96 ,Active Status Bit 96" "Not active,Active" else rgroup.long 0x030C++0x03 line.long 0x0 "GICD_ICDABR3,Active Status Register 3" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(ad:(per.long(spr:0x31F30)&0xFFFC0000)+0x04))&0x0000001F)>=0x04) rgroup.long 0x0310++0x03 line.long 0x0 "GICD_ICDABR4,Active Status Register 4" bitfld.long 0x00 31. " ASB159 ,Active Status Bit 159" "Not active,Active" bitfld.long 0x00 30. " ASB158 ,Active Status Bit 158" "Not active,Active" bitfld.long 0x00 29. " ASB157 ,Active Status Bit 157" "Not active,Active" textline " " bitfld.long 0x00 28. " ASB156 ,Active Status Bit 156" "Not active,Active" bitfld.long 0x00 27. " ASB155 ,Active Status Bit 155" "Not active,Active" bitfld.long 0x00 26. " ASB154 ,Active Status Bit 154" "Not active,Active" textline " " bitfld.long 0x00 25. " ASB153 ,Active Status Bit 153" "Not active,Active" bitfld.long 0x00 24. " ASB152 ,Active Status Bit 152" "Not active,Active" bitfld.long 0x00 23. " ASB151 ,Active Status Bit 151" "Not active,Active" textline " " bitfld.long 0x00 22. " ASB150 ,Active Status Bit 150" "Not active,Active" bitfld.long 0x00 21. " ASB149 ,Active Status Bit 149" "Not active,Active" bitfld.long 0x00 20. " ASB148 ,Active Status Bit 148" "Not active,Active" textline " " bitfld.long 0x00 19. " ASB147 ,Active Status Bit 147" "Not active,Active" bitfld.long 0x00 18. " ASB146 ,Active Status Bit 146" "Not active,Active" bitfld.long 0x00 17. " ASB145 ,Active Status Bit 145" "Not active,Active" textline " " bitfld.long 0x00 16. " ASB144 ,Active Status Bit 144" "Not active,Active" bitfld.long 0x00 15. " ASB143 ,Active Status Bit 143" "Not active,Active" bitfld.long 0x00 14. " ASB142 ,Active Status Bit 142" "Not active,Active" textline " " bitfld.long 0x00 13. " ASB141 ,Active Status Bit 141" "Not active,Active" bitfld.long 0x00 12. " ASB140 ,Active Status Bit 140" "Not active,Active" bitfld.long 0x00 11. " ASB139 ,Active Status Bit 139" "Not active,Active" textline " " bitfld.long 0x00 10. " ASB138 ,Active Status Bit 138" "Not active,Active" bitfld.long 0x00 9. " ASB137 ,Active Status Bit 137" "Not active,Active" bitfld.long 0x00 8. " ASB136 ,Active Status Bit 136" "Not active,Active" textline " " bitfld.long 0x00 7. " ASB135 ,Active Status Bit 135" "Not active,Active" bitfld.long 0x00 6. " ASB134 ,Active Status Bit 134" "Not active,Active" bitfld.long 0x00 5. " ASB133 ,Active Status Bit 133" "Not active,Active" textline " " bitfld.long 0x00 4. " ASB132 ,Active Status Bit 132" "Not active,Active" bitfld.long 0x00 3. " ASB131 ,Active Status Bit 131" "Not active,Active" bitfld.long 0x00 2. " ASB130 ,Active Status Bit 130" "Not active,Active" textline " " bitfld.long 0x00 1. " ASB129 ,Active Status Bit 129" "Not active,Active" bitfld.long 0x00 0. " ASB128 ,Active Status Bit 128" "Not active,Active" else rgroup.long 0x0310++0x03 line.long 0x0 "GICD_ICDABR4,Active Status Register 4" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(ad:(per.long(spr:0x31F30)&0xFFFC0000)+0x04))&0x0000001F)>=0x05) rgroup.long 0x0314++0x03 line.long 0x0 "GICD_ICDABR5,Active Status Register 5" bitfld.long 0x00 31. " ASB191 ,Active Status Bit 191" "Not active,Active" bitfld.long 0x00 30. " ASB190 ,Active Status Bit 190" "Not active,Active" bitfld.long 0x00 29. " ASB189 ,Active Status Bit 189" "Not active,Active" textline " " bitfld.long 0x00 28. " ASB188 ,Active Status Bit 188" "Not active,Active" bitfld.long 0x00 27. " ASB187 ,Active Status Bit 187" "Not active,Active" bitfld.long 0x00 26. " ASB186 ,Active Status Bit 186" "Not active,Active" textline " " bitfld.long 0x00 25. " ASB185 ,Active Status Bit 185" "Not active,Active" bitfld.long 0x00 24. " ASB184 ,Active Status Bit 184" "Not active,Active" bitfld.long 0x00 23. " ASB183 ,Active Status Bit 183" "Not active,Active" textline " " bitfld.long 0x00 22. " ASB182 ,Active Status Bit 182" "Not active,Active" bitfld.long 0x00 21. " ASB181 ,Active Status Bit 181" "Not active,Active" bitfld.long 0x00 20. " ASB180 ,Active Status Bit 180" "Not active,Active" textline " " bitfld.long 0x00 19. " ASB179 ,Active Status Bit 179" "Not active,Active" bitfld.long 0x00 18. " ASB178 ,Active Status Bit 178" "Not active,Active" bitfld.long 0x00 17. " ASB177 ,Active Status Bit 177" "Not active,Active" textline " " bitfld.long 0x00 16. " ASB176 ,Active Status Bit 176" "Not active,Active" bitfld.long 0x00 15. " ASB175 ,Active Status Bit 175" "Not active,Active" bitfld.long 0x00 14. " ASB174 ,Active Status Bit 174" "Not active,Active" textline " " bitfld.long 0x00 13. " ASB173 ,Active Status Bit 173" "Not active,Active" bitfld.long 0x00 12. " ASB172 ,Active Status Bit 172" "Not active,Active" bitfld.long 0x00 11. " ASB171 ,Active Status Bit 171" "Not active,Active" textline " " bitfld.long 0x00 10. " ASB170 ,Active Status Bit 170" "Not active,Active" bitfld.long 0x00 9. " ASB169 ,Active Status Bit 169" "Not active,Active" bitfld.long 0x00 8. " ASB168 ,Active Status Bit 168" "Not active,Active" textline " " bitfld.long 0x00 7. " ASB167 ,Active Status Bit 167" "Not active,Active" bitfld.long 0x00 6. " ASB166 ,Active Status Bit 166" "Not active,Active" bitfld.long 0x00 5. " ASB165 ,Active Status Bit 165" "Not active,Active" textline " " bitfld.long 0x00 4. " ASB164 ,Active Status Bit 164" "Not active,Active" bitfld.long 0x00 3. " ASB163 ,Active Status Bit 163" "Not active,Active" bitfld.long 0x00 2. " ASB162 ,Active Status Bit 162" "Not active,Active" textline " " bitfld.long 0x00 1. " ASB161 ,Active Status Bit 161" "Not active,Active" bitfld.long 0x00 0. " ASB160 ,Active Status Bit 160" "Not active,Active" else rgroup.long 0x0314++0x03 line.long 0x0 "GICD_ICDABR5,Active Status Register 5" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(ad:(per.long(spr:0x31F30)&0xFFFC0000)+0x04))&0x0000001F)>=0x06) rgroup.long 0x0318++0x03 line.long 0x0 "GICD_ICDABR6,Active Status Register 6" bitfld.long 0x00 31. " ASB223 ,Active Status Bit 223" "Not active,Active" bitfld.long 0x00 30. " ASB222 ,Active Status Bit 222" "Not active,Active" bitfld.long 0x00 29. " ASB221 ,Active Status Bit 221" "Not active,Active" textline " " bitfld.long 0x00 28. " ASB220 ,Active Status Bit 220" "Not active,Active" bitfld.long 0x00 27. " ASB219 ,Active Status Bit 219" "Not active,Active" bitfld.long 0x00 26. " ASB218 ,Active Status Bit 218" "Not active,Active" textline " " bitfld.long 0x00 25. " ASB217 ,Active Status Bit 217" "Not active,Active" bitfld.long 0x00 24. " ASB216 ,Active Status Bit 216" "Not active,Active" bitfld.long 0x00 23. " ASB215 ,Active Status Bit 215" "Not active,Active" textline " " bitfld.long 0x00 22. " ASB214 ,Active Status Bit 214" "Not active,Active" bitfld.long 0x00 21. " ASB213 ,Active Status Bit 213" "Not active,Active" bitfld.long 0x00 20. " ASB212 ,Active Status Bit 212" "Not active,Active" textline " " bitfld.long 0x00 19. " ASB211 ,Active Status Bit 211" "Not active,Active" bitfld.long 0x00 18. " ASB210 ,Active Status Bit 210" "Not active,Active" bitfld.long 0x00 17. " ASB209 ,Active Status Bit 209" "Not active,Active" textline " " bitfld.long 0x00 16. " ASB208 ,Active Status Bit 208" "Not active,Active" bitfld.long 0x00 15. " ASB207 ,Active Status Bit 207" "Not active,Active" bitfld.long 0x00 14. " ASB206 ,Active Status Bit 206" "Not active,Active" textline " " bitfld.long 0x00 13. " ASB205 ,Active Status Bit 205" "Not active,Active" bitfld.long 0x00 12. " ASB204 ,Active Status Bit 204" "Not active,Active" bitfld.long 0x00 11. " ASB203 ,Active Status Bit 203" "Not active,Active" textline " " bitfld.long 0x00 10. " ASB202 ,Active Status Bit 202" "Not active,Active" bitfld.long 0x00 9. " ASB201 ,Active Status Bit 201" "Not active,Active" bitfld.long 0x00 8. " ASB200 ,Active Status Bit 200" "Not active,Active" textline " " bitfld.long 0x00 7. " ASB199 ,Active Status Bit 199" "Not active,Active" bitfld.long 0x00 6. " ASB198 ,Active Status Bit 198" "Not active,Active" bitfld.long 0x00 5. " ASB197 ,Active Status Bit 197" "Not active,Active" textline " " bitfld.long 0x00 4. " ASB196 ,Active Status Bit 196" "Not active,Active" bitfld.long 0x00 3. " ASB195 ,Active Status Bit 195" "Not active,Active" bitfld.long 0x00 2. " ASB194 ,Active Status Bit 194" "Not active,Active" textline " " bitfld.long 0x00 1. " ASB193 ,Active Status Bit 193" "Not active,Active" bitfld.long 0x00 0. " ASB192 ,Active Status Bit 192" "Not active,Active" else rgroup.long 0x0318++0x03 line.long 0x0 "GICD_ICDABR6,Active Status Register 6" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(ad:(per.long(spr:0x31F30)&0xFFFC0000)+0x04))&0x0000001F)>=0x07) rgroup.long 0x031C++0x03 line.long 0x0 "GICD_ICDABR7,Active Status Register 7" bitfld.long 0x00 31. " ASB255 ,Active Status Bit 255" "Not active,Active" bitfld.long 0x00 30. " ASB254 ,Active Status Bit 254" "Not active,Active" bitfld.long 0x00 29. " ASB253 ,Active Status Bit 253" "Not active,Active" textline " " bitfld.long 0x00 28. " ASB252 ,Active Status Bit 252" "Not active,Active" bitfld.long 0x00 27. " ASB251 ,Active Status Bit 251" "Not active,Active" bitfld.long 0x00 26. " ASB250 ,Active Status Bit 250" "Not active,Active" textline " " bitfld.long 0x00 25. " ASB249 ,Active Status Bit 249" "Not active,Active" bitfld.long 0x00 24. " ASB248 ,Active Status Bit 248" "Not active,Active" bitfld.long 0x00 23. " ASB247 ,Active Status Bit 247" "Not active,Active" textline " " bitfld.long 0x00 22. " ASB246 ,Active Status Bit 246" "Not active,Active" bitfld.long 0x00 21. " ASB245 ,Active Status Bit 245" "Not active,Active" bitfld.long 0x00 20. " ASB244 ,Active Status Bit 244" "Not active,Active" textline " " bitfld.long 0x00 19. " ASB243 ,Active Status Bit 243" "Not active,Active" bitfld.long 0x00 18. " ASB242 ,Active Status Bit 242" "Not active,Active" bitfld.long 0x00 17. " ASB241 ,Active Status Bit 241" "Not active,Active" textline " " bitfld.long 0x00 16. " ASB240 ,Active Status Bit 240" "Not active,Active" bitfld.long 0x00 15. " ASB239 ,Active Status Bit 239" "Not active,Active" bitfld.long 0x00 14. " ASB238 ,Active Status Bit 238" "Not active,Active" textline " " bitfld.long 0x00 13. " ASB237 ,Active Status Bit 237" "Not active,Active" bitfld.long 0x00 12. " ASB236 ,Active Status Bit 236" "Not active,Active" bitfld.long 0x00 11. " ASB235 ,Active Status Bit 235" "Not active,Active" textline " " bitfld.long 0x00 10. " ASB234 ,Active Status Bit 234" "Not active,Active" bitfld.long 0x00 9. " ASB233 ,Active Status Bit 233" "Not active,Active" bitfld.long 0x00 8. " ASB232 ,Active Status Bit 232" "Not active,Active" textline " " bitfld.long 0x00 7. " ASB231 ,Active Status Bit 231" "Not active,Active" bitfld.long 0x00 6. " ASB230 ,Active Status Bit 230" "Not active,Active" bitfld.long 0x00 5. " ASB229 ,Active Status Bit 229" "Not active,Active" textline " " bitfld.long 0x00 4. " ASB228 ,Active Status Bit 228" "Not active,Active" bitfld.long 0x00 3. " ASB227 ,Active Status Bit 227" "Not active,Active" bitfld.long 0x00 2. " ASB226 ,Active Status Bit 226" "Not active,Active" textline " " bitfld.long 0x00 1. " ASB225 ,Active Status Bit 225" "Not active,Active" bitfld.long 0x00 0. " ASB224 ,Active Status Bit 224" "Not active,Active" else rgroup.long 0x031C++0x03 line.long 0x0 "GICD_ICDABR7,Active Status Register 7" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(ad:(per.long(spr:0x31F30)&0xFFFC0000)+0x04))&0x0000001F)>=0x08) rgroup.long 0x0320++0x03 line.long 0x0 "GICD_ICDABR8,Active Status Register 8" bitfld.long 0x00 31. " ASB287 ,Active Status Bit 287" "Not active,Active" bitfld.long 0x00 30. " ASB286 ,Active Status Bit 286" "Not active,Active" bitfld.long 0x00 29. " ASB285 ,Active Status Bit 285" "Not active,Active" textline " " bitfld.long 0x00 28. " ASB284 ,Active Status Bit 284" "Not active,Active" bitfld.long 0x00 27. " ASB283 ,Active Status Bit 283" "Not active,Active" bitfld.long 0x00 26. " ASB282 ,Active Status Bit 282" "Not active,Active" textline " " bitfld.long 0x00 25. " ASB281 ,Active Status Bit 281" "Not active,Active" bitfld.long 0x00 24. " ASB280 ,Active Status Bit 280" "Not active,Active" bitfld.long 0x00 23. " ASB279 ,Active Status Bit 279" "Not active,Active" textline " " bitfld.long 0x00 22. " ASB278 ,Active Status Bit 278" "Not active,Active" bitfld.long 0x00 21. " ASB277 ,Active Status Bit 277" "Not active,Active" bitfld.long 0x00 20. " ASB276 ,Active Status Bit 276" "Not active,Active" textline " " bitfld.long 0x00 19. " ASB275 ,Active Status Bit 275" "Not active,Active" bitfld.long 0x00 18. " ASB274 ,Active Status Bit 274" "Not active,Active" bitfld.long 0x00 17. " ASB273 ,Active Status Bit 273" "Not active,Active" textline " " bitfld.long 0x00 16. " ASB272 ,Active Status Bit 272" "Not active,Active" bitfld.long 0x00 15. " ASB271 ,Active Status Bit 271" "Not active,Active" bitfld.long 0x00 14. " ASB270 ,Active Status Bit 270" "Not active,Active" textline " " bitfld.long 0x00 13. " ASB269 ,Active Status Bit 269" "Not active,Active" bitfld.long 0x00 12. " ASB268 ,Active Status Bit 268" "Not active,Active" bitfld.long 0x00 11. " ASB267 ,Active Status Bit 267" "Not active,Active" textline " " bitfld.long 0x00 10. " ASB266 ,Active Status Bit 266" "Not active,Active" bitfld.long 0x00 9. " ASB265 ,Active Status Bit 265" "Not active,Active" bitfld.long 0x00 8. " ASB264 ,Active Status Bit 264" "Not active,Active" textline " " bitfld.long 0x00 7. " ASB263 ,Active Status Bit 263" "Not active,Active" bitfld.long 0x00 6. " ASB262 ,Active Status Bit 262" "Not active,Active" bitfld.long 0x00 5. " ASB261 ,Active Status Bit 261" "Not active,Active" textline " " bitfld.long 0x00 4. " ASB260 ,Active Status Bit 260" "Not active,Active" bitfld.long 0x00 3. " ASB259 ,Active Status Bit 259" "Not active,Active" bitfld.long 0x00 2. " ASB258 ,Active Status Bit 258" "Not active,Active" textline " " bitfld.long 0x00 1. " ASB257 ,Active Status Bit 257" "Not active,Active" bitfld.long 0x00 0. " ASB256 ,Active Status Bit 256" "Not active,Active" else rgroup.long 0x0320++0x03 line.long 0x0 "GICD_ICDABR8,Active Status Register 8" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(ad:(per.long(spr:0x31F30)&0xFFFC0000)+0x04))&0x0000001F)>=0x09) rgroup.long 0x0324++0x03 line.long 0x0 "GICD_ICDABR9,Active Status Register 9" bitfld.long 0x00 31. " ASB319 ,Active Status Bit 319" "Not active,Active" bitfld.long 0x00 30. " ASB318 ,Active Status Bit 318" "Not active,Active" bitfld.long 0x00 29. " ASB317 ,Active Status Bit 317" "Not active,Active" textline " " bitfld.long 0x00 28. " ASB316 ,Active Status Bit 316" "Not active,Active" bitfld.long 0x00 27. " ASB315 ,Active Status Bit 315" "Not active,Active" bitfld.long 0x00 26. " ASB314 ,Active Status Bit 314" "Not active,Active" textline " " bitfld.long 0x00 25. " ASB313 ,Active Status Bit 313" "Not active,Active" bitfld.long 0x00 24. " ASB312 ,Active Status Bit 312" "Not active,Active" bitfld.long 0x00 23. " ASB311 ,Active Status Bit 311" "Not active,Active" textline " " bitfld.long 0x00 22. " ASB310 ,Active Status Bit 310" "Not active,Active" bitfld.long 0x00 21. " ASB309 ,Active Status Bit 309" "Not active,Active" bitfld.long 0x00 20. " ASB308 ,Active Status Bit 308" "Not active,Active" textline " " bitfld.long 0x00 19. " ASB307 ,Active Status Bit 307" "Not active,Active" bitfld.long 0x00 18. " ASB306 ,Active Status Bit 306" "Not active,Active" bitfld.long 0x00 17. " ASB305 ,Active Status Bit 305" "Not active,Active" textline " " bitfld.long 0x00 16. " ASB304 ,Active Status Bit 304" "Not active,Active" bitfld.long 0x00 15. " ASB303 ,Active Status Bit 303" "Not active,Active" bitfld.long 0x00 14. " ASB302 ,Active Status Bit 302" "Not active,Active" textline " " bitfld.long 0x00 13. " ASB301 ,Active Status Bit 301" "Not active,Active" bitfld.long 0x00 12. " ASB300 ,Active Status Bit 300" "Not active,Active" bitfld.long 0x00 11. " ASB299 ,Active Status Bit 299" "Not active,Active" textline " " bitfld.long 0x00 10. " ASB298 ,Active Status Bit 298" "Not active,Active" bitfld.long 0x00 9. " ASB297 ,Active Status Bit 297" "Not active,Active" bitfld.long 0x00 8. " ASB296 ,Active Status Bit 296" "Not active,Active" textline " " bitfld.long 0x00 7. " ASB295 ,Active Status Bit 295" "Not active,Active" bitfld.long 0x00 6. " ASB294 ,Active Status Bit 294" "Not active,Active" bitfld.long 0x00 5. " ASB293 ,Active Status Bit 293" "Not active,Active" textline " " bitfld.long 0x00 4. " ASB292 ,Active Status Bit 292" "Not active,Active" bitfld.long 0x00 3. " ASB291 ,Active Status Bit 291" "Not active,Active" bitfld.long 0x00 2. " ASB290 ,Active Status Bit 290" "Not active,Active" textline " " bitfld.long 0x00 1. " ASB289 ,Active Status Bit 289" "Not active,Active" bitfld.long 0x00 0. " ASB288 ,Active Status Bit 288" "Not active,Active" else rgroup.long 0x0324++0x03 line.long 0x0 "GICD_ICDABR9,Active Status Register 9" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(ad:(per.long(spr:0x31F30)&0xFFFC0000)+0x04))&0x0000001F)>=0x0A) rgroup.long 0x0328++0x03 line.long 0x0 "GICD_ICDABR10,Active Status Register 10" bitfld.long 0x00 31. " ASB351 ,Active Status Bit 351" "Not active,Active" bitfld.long 0x00 30. " ASB350 ,Active Status Bit 350" "Not active,Active" bitfld.long 0x00 29. " ASB349 ,Active Status Bit 349" "Not active,Active" textline " " bitfld.long 0x00 28. " ASB348 ,Active Status Bit 348" "Not active,Active" bitfld.long 0x00 27. " ASB347 ,Active Status Bit 347" "Not active,Active" bitfld.long 0x00 26. " ASB346 ,Active Status Bit 346" "Not active,Active" textline " " bitfld.long 0x00 25. " ASB345 ,Active Status Bit 345" "Not active,Active" bitfld.long 0x00 24. " ASB344 ,Active Status Bit 344" "Not active,Active" bitfld.long 0x00 23. " ASB343 ,Active Status Bit 343" "Not active,Active" textline " " bitfld.long 0x00 22. " ASB342 ,Active Status Bit 342" "Not active,Active" bitfld.long 0x00 21. " ASB341 ,Active Status Bit 341" "Not active,Active" bitfld.long 0x00 20. " ASB340 ,Active Status Bit 340" "Not active,Active" textline " " bitfld.long 0x00 19. " ASB339 ,Active Status Bit 339" "Not active,Active" bitfld.long 0x00 18. " ASB338 ,Active Status Bit 338" "Not active,Active" bitfld.long 0x00 17. " ASB337 ,Active Status Bit 337" "Not active,Active" textline " " bitfld.long 0x00 16. " ASB336 ,Active Status Bit 336" "Not active,Active" bitfld.long 0x00 15. " ASB335 ,Active Status Bit 335" "Not active,Active" bitfld.long 0x00 14. " ASB334 ,Active Status Bit 334" "Not active,Active" textline " " bitfld.long 0x00 13. " ASB333 ,Active Status Bit 333" "Not active,Active" bitfld.long 0x00 12. " ASB332 ,Active Status Bit 332" "Not active,Active" bitfld.long 0x00 11. " ASB331 ,Active Status Bit 331" "Not active,Active" textline " " bitfld.long 0x00 10. " ASB330 ,Active Status Bit 330" "Not active,Active" bitfld.long 0x00 9. " ASB329 ,Active Status Bit 329" "Not active,Active" bitfld.long 0x00 8. " ASB328 ,Active Status Bit 328" "Not active,Active" textline " " bitfld.long 0x00 7. " ASB327 ,Active Status Bit 327" "Not active,Active" bitfld.long 0x00 6. " ASB326 ,Active Status Bit 326" "Not active,Active" bitfld.long 0x00 5. " ASB325 ,Active Status Bit 325" "Not active,Active" textline " " bitfld.long 0x00 4. " ASB324 ,Active Status Bit 324" "Not active,Active" bitfld.long 0x00 3. " ASB323 ,Active Status Bit 323" "Not active,Active" bitfld.long 0x00 2. " ASB322 ,Active Status Bit 322" "Not active,Active" textline " " bitfld.long 0x00 1. " ASB321 ,Active Status Bit 321" "Not active,Active" bitfld.long 0x00 0. " ASB320 ,Active Status Bit 320" "Not active,Active" else rgroup.long 0x0328++0x03 line.long 0x0 "GICD_ICDABR10,Active Status Register 10" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(ad:(per.long(spr:0x31F30)&0xFFFC0000)+0x04))&0x0000001F)>=0x0B) rgroup.long 0x032C++0x03 line.long 0x0 "GICD_ICDABR11,Active Status Register 11" bitfld.long 0x00 31. " ASB383 ,Active Status Bit 383" "Not active,Active" bitfld.long 0x00 30. " ASB382 ,Active Status Bit 382" "Not active,Active" bitfld.long 0x00 29. " ASB381 ,Active Status Bit 381" "Not active,Active" textline " " bitfld.long 0x00 28. " ASB380 ,Active Status Bit 380" "Not active,Active" bitfld.long 0x00 27. " ASB379 ,Active Status Bit 379" "Not active,Active" bitfld.long 0x00 26. " ASB378 ,Active Status Bit 378" "Not active,Active" textline " " bitfld.long 0x00 25. " ASB377 ,Active Status Bit 377" "Not active,Active" bitfld.long 0x00 24. " ASB376 ,Active Status Bit 376" "Not active,Active" bitfld.long 0x00 23. " ASB375 ,Active Status Bit 375" "Not active,Active" textline " " bitfld.long 0x00 22. " ASB374 ,Active Status Bit 374" "Not active,Active" bitfld.long 0x00 21. " ASB373 ,Active Status Bit 373" "Not active,Active" bitfld.long 0x00 20. " ASB372 ,Active Status Bit 372" "Not active,Active" textline " " bitfld.long 0x00 19. " ASB371 ,Active Status Bit 371" "Not active,Active" bitfld.long 0x00 18. " ASB370 ,Active Status Bit 370" "Not active,Active" bitfld.long 0x00 17. " ASB369 ,Active Status Bit 369" "Not active,Active" textline " " bitfld.long 0x00 16. " ASB368 ,Active Status Bit 368" "Not active,Active" bitfld.long 0x00 15. " ASB367 ,Active Status Bit 367" "Not active,Active" bitfld.long 0x00 14. " ASB366 ,Active Status Bit 366" "Not active,Active" textline " " bitfld.long 0x00 13. " ASB365 ,Active Status Bit 365" "Not active,Active" bitfld.long 0x00 12. " ASB364 ,Active Status Bit 364" "Not active,Active" bitfld.long 0x00 11. " ASB363 ,Active Status Bit 363" "Not active,Active" textline " " bitfld.long 0x00 10. " ASB362 ,Active Status Bit 362" "Not active,Active" bitfld.long 0x00 9. " ASB361 ,Active Status Bit 361" "Not active,Active" bitfld.long 0x00 8. " ASB360 ,Active Status Bit 360" "Not active,Active" textline " " bitfld.long 0x00 7. " ASB359 ,Active Status Bit 359" "Not active,Active" bitfld.long 0x00 6. " ASB358 ,Active Status Bit 358" "Not active,Active" bitfld.long 0x00 5. " ASB357 ,Active Status Bit 357" "Not active,Active" textline " " bitfld.long 0x00 4. " ASB356 ,Active Status Bit 356" "Not active,Active" bitfld.long 0x00 3. " ASB355 ,Active Status Bit 355" "Not active,Active" bitfld.long 0x00 2. " ASB354 ,Active Status Bit 354" "Not active,Active" textline " " bitfld.long 0x00 1. " ASB353 ,Active Status Bit 353" "Not active,Active" bitfld.long 0x00 0. " ASB352 ,Active Status Bit 352" "Not active,Active" else rgroup.long 0x032C++0x03 line.long 0x0 "GICD_ICDABR11,Active Status Register 11" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(ad:(per.long(spr:0x31F30)&0xFFFC0000)+0x04))&0x0000001F)>=0x0C) rgroup.long 0x0330++0x03 line.long 0x0 "GICD_ICDABR12,Active Status Register 12" bitfld.long 0x00 31. " ASB415 ,Active Status Bit 415" "Not active,Active" bitfld.long 0x00 30. " ASB414 ,Active Status Bit 414" "Not active,Active" bitfld.long 0x00 29. " ASB413 ,Active Status Bit 413" "Not active,Active" textline " " bitfld.long 0x00 28. " ASB412 ,Active Status Bit 412" "Not active,Active" bitfld.long 0x00 27. " ASB411 ,Active Status Bit 411" "Not active,Active" bitfld.long 0x00 26. " ASB410 ,Active Status Bit 410" "Not active,Active" textline " " bitfld.long 0x00 25. " ASB409 ,Active Status Bit 409" "Not active,Active" bitfld.long 0x00 24. " ASB408 ,Active Status Bit 408" "Not active,Active" bitfld.long 0x00 23. " ASB407 ,Active Status Bit 407" "Not active,Active" textline " " bitfld.long 0x00 22. " ASB406 ,Active Status Bit 406" "Not active,Active" bitfld.long 0x00 21. " ASB405 ,Active Status Bit 405" "Not active,Active" bitfld.long 0x00 20. " ASB404 ,Active Status Bit 404" "Not active,Active" textline " " bitfld.long 0x00 19. " ASB403 ,Active Status Bit 403" "Not active,Active" bitfld.long 0x00 18. " ASB402 ,Active Status Bit 402" "Not active,Active" bitfld.long 0x00 17. " ASB401 ,Active Status Bit 401" "Not active,Active" textline " " bitfld.long 0x00 16. " ASB400 ,Active Status Bit 400" "Not active,Active" bitfld.long 0x00 15. " ASB399 ,Active Status Bit 399" "Not active,Active" bitfld.long 0x00 14. " ASB398 ,Active Status Bit 398" "Not active,Active" textline " " bitfld.long 0x00 13. " ASB397 ,Active Status Bit 397" "Not active,Active" bitfld.long 0x00 12. " ASB396 ,Active Status Bit 396" "Not active,Active" bitfld.long 0x00 11. " ASB395 ,Active Status Bit 395" "Not active,Active" textline " " bitfld.long 0x00 10. " ASB394 ,Active Status Bit 394" "Not active,Active" bitfld.long 0x00 9. " ASB393 ,Active Status Bit 393" "Not active,Active" bitfld.long 0x00 8. " ASB392 ,Active Status Bit 392" "Not active,Active" textline " " bitfld.long 0x00 7. " ASB391 ,Active Status Bit 391" "Not active,Active" bitfld.long 0x00 6. " ASB390 ,Active Status Bit 390" "Not active,Active" bitfld.long 0x00 5. " ASB389 ,Active Status Bit 389" "Not active,Active" textline " " bitfld.long 0x00 4. " ASB388 ,Active Status Bit 388" "Not active,Active" bitfld.long 0x00 3. " ASB387 ,Active Status Bit 387" "Not active,Active" bitfld.long 0x00 2. " ASB386 ,Active Status Bit 386" "Not active,Active" textline " " bitfld.long 0x00 1. " ASB385 ,Active Status Bit 385" "Not active,Active" bitfld.long 0x00 0. " ASB384 ,Active Status Bit 384" "Not active,Active" else rgroup.long 0x0330++0x03 line.long 0x0 "GICD_ICDABR12,Active Status Register 12" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(ad:(per.long(spr:0x31F30)&0xFFFC0000)+0x04))&0x0000001F)>=0x0D) rgroup.long 0x0334++0x03 line.long 0x0 "GICD_ICDABR13,Active Status Register 13" bitfld.long 0x00 31. " ASB447 ,Active Status Bit 447" "Not active,Active" bitfld.long 0x00 30. " ASB446 ,Active Status Bit 446" "Not active,Active" bitfld.long 0x00 29. " ASB445 ,Active Status Bit 445" "Not active,Active" textline " " bitfld.long 0x00 28. " ASB444 ,Active Status Bit 444" "Not active,Active" bitfld.long 0x00 27. " ASB443 ,Active Status Bit 443" "Not active,Active" bitfld.long 0x00 26. " ASB442 ,Active Status Bit 442" "Not active,Active" textline " " bitfld.long 0x00 25. " ASB441 ,Active Status Bit 441" "Not active,Active" bitfld.long 0x00 24. " ASB440 ,Active Status Bit 440" "Not active,Active" bitfld.long 0x00 23. " ASB439 ,Active Status Bit 439" "Not active,Active" textline " " bitfld.long 0x00 22. " ASB438 ,Active Status Bit 438" "Not active,Active" bitfld.long 0x00 21. " ASB437 ,Active Status Bit 437" "Not active,Active" bitfld.long 0x00 20. " ASB436 ,Active Status Bit 436" "Not active,Active" textline " " bitfld.long 0x00 19. " ASB435 ,Active Status Bit 435" "Not active,Active" bitfld.long 0x00 18. " ASB434 ,Active Status Bit 434" "Not active,Active" bitfld.long 0x00 17. " ASB433 ,Active Status Bit 433" "Not active,Active" textline " " bitfld.long 0x00 16. " ASB432 ,Active Status Bit 432" "Not active,Active" bitfld.long 0x00 15. " ASB431 ,Active Status Bit 431" "Not active,Active" bitfld.long 0x00 14. " ASB430 ,Active Status Bit 430" "Not active,Active" textline " " bitfld.long 0x00 13. " ASB429 ,Active Status Bit 429" "Not active,Active" bitfld.long 0x00 12. " ASB428 ,Active Status Bit 428" "Not active,Active" bitfld.long 0x00 11. " ASB427 ,Active Status Bit 427" "Not active,Active" textline " " bitfld.long 0x00 10. " ASB426 ,Active Status Bit 426" "Not active,Active" bitfld.long 0x00 9. " ASB425 ,Active Status Bit 425" "Not active,Active" bitfld.long 0x00 8. " ASB424 ,Active Status Bit 424" "Not active,Active" textline " " bitfld.long 0x00 7. " ASB423 ,Active Status Bit 423" "Not active,Active" bitfld.long 0x00 6. " ASB422 ,Active Status Bit 422" "Not active,Active" bitfld.long 0x00 5. " ASB421 ,Active Status Bit 421" "Not active,Active" textline " " bitfld.long 0x00 4. " ASB420 ,Active Status Bit 420" "Not active,Active" bitfld.long 0x00 3. " ASB419 ,Active Status Bit 419" "Not active,Active" bitfld.long 0x00 2. " ASB418 ,Active Status Bit 418" "Not active,Active" textline " " bitfld.long 0x00 1. " ASB417 ,Active Status Bit 417" "Not active,Active" bitfld.long 0x00 0. " ASB416 ,Active Status Bit 416" "Not active,Active" else rgroup.long 0x0334++0x03 line.long 0x0 "GICD_ICDABR13,Active Status Register 13" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(ad:(per.long(spr:0x31F30)&0xFFFC0000)+0x04))&0x0000001F)>=0x0E) rgroup.long 0x0338++0x03 line.long 0x0 "GICD_ICDABR14,Active Status Register 14" bitfld.long 0x00 31. " ASB479 ,Active Status Bit 479" "Not active,Active" bitfld.long 0x00 30. " ASB478 ,Active Status Bit 478" "Not active,Active" bitfld.long 0x00 29. " ASB477 ,Active Status Bit 477" "Not active,Active" textline " " bitfld.long 0x00 28. " ASB476 ,Active Status Bit 476" "Not active,Active" bitfld.long 0x00 27. " ASB475 ,Active Status Bit 475" "Not active,Active" bitfld.long 0x00 26. " ASB474 ,Active Status Bit 474" "Not active,Active" textline " " bitfld.long 0x00 25. " ASB473 ,Active Status Bit 473" "Not active,Active" bitfld.long 0x00 24. " ASB472 ,Active Status Bit 472" "Not active,Active" bitfld.long 0x00 23. " ASB471 ,Active Status Bit 471" "Not active,Active" textline " " bitfld.long 0x00 22. " ASB470 ,Active Status Bit 470" "Not active,Active" bitfld.long 0x00 21. " ASB469 ,Active Status Bit 469" "Not active,Active" bitfld.long 0x00 20. " ASB468 ,Active Status Bit 468" "Not active,Active" textline " " bitfld.long 0x00 19. " ASB467 ,Active Status Bit 467" "Not active,Active" bitfld.long 0x00 18. " ASB466 ,Active Status Bit 466" "Not active,Active" bitfld.long 0x00 17. " ASB465 ,Active Status Bit 465" "Not active,Active" textline " " bitfld.long 0x00 16. " ASB464 ,Active Status Bit 464" "Not active,Active" bitfld.long 0x00 15. " ASB463 ,Active Status Bit 463" "Not active,Active" bitfld.long 0x00 14. " ASB462 ,Active Status Bit 462" "Not active,Active" textline " " bitfld.long 0x00 13. " ASB461 ,Active Status Bit 461" "Not active,Active" bitfld.long 0x00 12. " ASB460 ,Active Status Bit 460" "Not active,Active" bitfld.long 0x00 11. " ASB459 ,Active Status Bit 459" "Not active,Active" textline " " bitfld.long 0x00 10. " ASB458 ,Active Status Bit 458" "Not active,Active" bitfld.long 0x00 9. " ASB457 ,Active Status Bit 457" "Not active,Active" bitfld.long 0x00 8. " ASB456 ,Active Status Bit 456" "Not active,Active" textline " " bitfld.long 0x00 7. " ASB455 ,Active Status Bit 455" "Not active,Active" bitfld.long 0x00 6. " ASB454 ,Active Status Bit 454" "Not active,Active" bitfld.long 0x00 5. " ASB453 ,Active Status Bit 453" "Not active,Active" textline " " bitfld.long 0x00 4. " ASB452 ,Active Status Bit 452" "Not active,Active" bitfld.long 0x00 3. " ASB451 ,Active Status Bit 451" "Not active,Active" bitfld.long 0x00 2. " ASB450 ,Active Status Bit 450" "Not active,Active" textline " " bitfld.long 0x00 1. " ASB449 ,Active Status Bit 449" "Not active,Active" bitfld.long 0x00 0. " ASB448 ,Active Status Bit 448" "Not active,Active" else rgroup.long 0x0338++0x03 line.long 0x0 "GICD_ICDABR14,Active Status Register 14" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(ad:(per.long(spr:0x31F30)&0xFFFC0000)+0x04))&0x0000001F)>=0x0F) rgroup.long 0x033C++0x03 line.long 0x0 "GICD_ICDABR15,Active Status Register 15" bitfld.long 0x00 31. " ASB511 ,Active Status Bit 511" "Not active,Active" bitfld.long 0x00 30. " ASB510 ,Active Status Bit 510" "Not active,Active" bitfld.long 0x00 29. " ASB509 ,Active Status Bit 509" "Not active,Active" textline " " bitfld.long 0x00 28. " ASB508 ,Active Status Bit 508" "Not active,Active" bitfld.long 0x00 27. " ASB507 ,Active Status Bit 507" "Not active,Active" bitfld.long 0x00 26. " ASB506 ,Active Status Bit 506" "Not active,Active" textline " " bitfld.long 0x00 25. " ASB505 ,Active Status Bit 505" "Not active,Active" bitfld.long 0x00 24. " ASB504 ,Active Status Bit 504" "Not active,Active" bitfld.long 0x00 23. " ASB503 ,Active Status Bit 503" "Not active,Active" textline " " bitfld.long 0x00 22. " ASB502 ,Active Status Bit 502" "Not active,Active" bitfld.long 0x00 21. " ASB501 ,Active Status Bit 501" "Not active,Active" bitfld.long 0x00 20. " ASB500 ,Active Status Bit 500" "Not active,Active" textline " " bitfld.long 0x00 19. " ASB499 ,Active Status Bit 499" "Not active,Active" bitfld.long 0x00 18. " ASB498 ,Active Status Bit 498" "Not active,Active" bitfld.long 0x00 17. " ASB497 ,Active Status Bit 497" "Not active,Active" textline " " bitfld.long 0x00 16. " ASB496 ,Active Status Bit 496" "Not active,Active" bitfld.long 0x00 15. " ASB495 ,Active Status Bit 495" "Not active,Active" bitfld.long 0x00 14. " ASB494 ,Active Status Bit 494" "Not active,Active" textline " " bitfld.long 0x00 13. " ASB493 ,Active Status Bit 493" "Not active,Active" bitfld.long 0x00 12. " ASB492 ,Active Status Bit 492" "Not active,Active" bitfld.long 0x00 11. " ASB491 ,Active Status Bit 491" "Not active,Active" textline " " bitfld.long 0x00 10. " ASB490 ,Active Status Bit 490" "Not active,Active" bitfld.long 0x00 9. " ASB489 ,Active Status Bit 489" "Not active,Active" bitfld.long 0x00 8. " ASB488 ,Active Status Bit 488" "Not active,Active" textline " " bitfld.long 0x00 7. " ASB487 ,Active Status Bit 487" "Not active,Active" bitfld.long 0x00 6. " ASB486 ,Active Status Bit 486" "Not active,Active" bitfld.long 0x00 5. " ASB485 ,Active Status Bit 485" "Not active,Active" textline " " bitfld.long 0x00 4. " ASB484 ,Active Status Bit 484" "Not active,Active" bitfld.long 0x00 3. " ASB483 ,Active Status Bit 483" "Not active,Active" bitfld.long 0x00 2. " ASB482 ,Active Status Bit 482" "Not active,Active" textline " " bitfld.long 0x00 1. " ASB481 ,Active Status Bit 481" "Not active,Active" bitfld.long 0x00 0. " ASB480 ,Active Status Bit 480" "Not active,Active" else rgroup.long 0x033C++0x03 line.long 0x0 "GICD_ICDABR15,Active Status Register 15" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(ad:(per.long(spr:0x31F30)&0xFFFC0000)+0x04))&0x0000001F)>=0x10) rgroup.long 0x0340++0x03 line.long 0x0 "GICD_ICDABR16,Active Status Register 16" bitfld.long 0x00 31. " ASB543 ,Active Status Bit 543" "Not active,Active" bitfld.long 0x00 30. " ASB542 ,Active Status Bit 542" "Not active,Active" bitfld.long 0x00 29. " ASB541 ,Active Status Bit 541" "Not active,Active" textline " " bitfld.long 0x00 28. " ASB540 ,Active Status Bit 540" "Not active,Active" bitfld.long 0x00 27. " ASB539 ,Active Status Bit 539" "Not active,Active" bitfld.long 0x00 26. " ASB538 ,Active Status Bit 538" "Not active,Active" textline " " bitfld.long 0x00 25. " ASB537 ,Active Status Bit 537" "Not active,Active" bitfld.long 0x00 24. " ASB536 ,Active Status Bit 536" "Not active,Active" bitfld.long 0x00 23. " ASB535 ,Active Status Bit 535" "Not active,Active" textline " " bitfld.long 0x00 22. " ASB534 ,Active Status Bit 534" "Not active,Active" bitfld.long 0x00 21. " ASB533 ,Active Status Bit 533" "Not active,Active" bitfld.long 0x00 20. " ASB532 ,Active Status Bit 532" "Not active,Active" textline " " bitfld.long 0x00 19. " ASB531 ,Active Status Bit 531" "Not active,Active" bitfld.long 0x00 18. " ASB530 ,Active Status Bit 530" "Not active,Active" bitfld.long 0x00 17. " ASB529 ,Active Status Bit 529" "Not active,Active" textline " " bitfld.long 0x00 16. " ASB528 ,Active Status Bit 528" "Not active,Active" bitfld.long 0x00 15. " ASB527 ,Active Status Bit 527" "Not active,Active" bitfld.long 0x00 14. " ASB526 ,Active Status Bit 526" "Not active,Active" textline " " bitfld.long 0x00 13. " ASB525 ,Active Status Bit 525" "Not active,Active" bitfld.long 0x00 12. " ASB524 ,Active Status Bit 524" "Not active,Active" bitfld.long 0x00 11. " ASB523 ,Active Status Bit 523" "Not active,Active" textline " " bitfld.long 0x00 10. " ASB522 ,Active Status Bit 522" "Not active,Active" bitfld.long 0x00 9. " ASB521 ,Active Status Bit 521" "Not active,Active" bitfld.long 0x00 8. " ASB520 ,Active Status Bit 520" "Not active,Active" textline " " bitfld.long 0x00 7. " ASB519 ,Active Status Bit 519" "Not active,Active" bitfld.long 0x00 6. " ASB518 ,Active Status Bit 518" "Not active,Active" bitfld.long 0x00 5. " ASB517 ,Active Status Bit 517" "Not active,Active" textline " " bitfld.long 0x00 4. " ASB516 ,Active Status Bit 516" "Not active,Active" bitfld.long 0x00 3. " ASB515 ,Active Status Bit 515" "Not active,Active" bitfld.long 0x00 2. " ASB514 ,Active Status Bit 514" "Not active,Active" textline " " bitfld.long 0x00 1. " ASB513 ,Active Status Bit 513" "Not active,Active" bitfld.long 0x00 0. " ASB512 ,Active Status Bit 512" "Not active,Active" else rgroup.long 0x0340++0x03 line.long 0x0 "GICD_ICDABR16,Active Status Register 16" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(ad:(per.long(spr:0x31F30)&0xFFFC0000)+0x04))&0x0000001F)>=0x11) rgroup.long 0x0344++0x03 line.long 0x0 "GICD_ICDABR17,Active Status Register 17" bitfld.long 0x00 31. " ASB575 ,Active Status Bit 575" "Not active,Active" bitfld.long 0x00 30. " ASB574 ,Active Status Bit 574" "Not active,Active" bitfld.long 0x00 29. " ASB573 ,Active Status Bit 573" "Not active,Active" textline " " bitfld.long 0x00 28. " ASB572 ,Active Status Bit 572" "Not active,Active" bitfld.long 0x00 27. " ASB571 ,Active Status Bit 571" "Not active,Active" bitfld.long 0x00 26. " ASB570 ,Active Status Bit 570" "Not active,Active" textline " " bitfld.long 0x00 25. " ASB569 ,Active Status Bit 569" "Not active,Active" bitfld.long 0x00 24. " ASB568 ,Active Status Bit 568" "Not active,Active" bitfld.long 0x00 23. " ASB567 ,Active Status Bit 567" "Not active,Active" textline " " bitfld.long 0x00 22. " ASB566 ,Active Status Bit 566" "Not active,Active" bitfld.long 0x00 21. " ASB565 ,Active Status Bit 565" "Not active,Active" bitfld.long 0x00 20. " ASB564 ,Active Status Bit 564" "Not active,Active" textline " " bitfld.long 0x00 19. " ASB563 ,Active Status Bit 563" "Not active,Active" bitfld.long 0x00 18. " ASB562 ,Active Status Bit 562" "Not active,Active" bitfld.long 0x00 17. " ASB561 ,Active Status Bit 561" "Not active,Active" textline " " bitfld.long 0x00 16. " ASB560 ,Active Status Bit 560" "Not active,Active" bitfld.long 0x00 15. " ASB559 ,Active Status Bit 559" "Not active,Active" bitfld.long 0x00 14. " ASB558 ,Active Status Bit 558" "Not active,Active" textline " " bitfld.long 0x00 13. " ASB557 ,Active Status Bit 557" "Not active,Active" bitfld.long 0x00 12. " ASB556 ,Active Status Bit 556" "Not active,Active" bitfld.long 0x00 11. " ASB555 ,Active Status Bit 555" "Not active,Active" textline " " bitfld.long 0x00 10. " ASB554 ,Active Status Bit 554" "Not active,Active" bitfld.long 0x00 9. " ASB553 ,Active Status Bit 553" "Not active,Active" bitfld.long 0x00 8. " ASB552 ,Active Status Bit 552" "Not active,Active" textline " " bitfld.long 0x00 7. " ASB551 ,Active Status Bit 551" "Not active,Active" bitfld.long 0x00 6. " ASB550 ,Active Status Bit 550" "Not active,Active" bitfld.long 0x00 5. " ASB549 ,Active Status Bit 549" "Not active,Active" textline " " bitfld.long 0x00 4. " ASB548 ,Active Status Bit 548" "Not active,Active" bitfld.long 0x00 3. " ASB547 ,Active Status Bit 547" "Not active,Active" bitfld.long 0x00 2. " ASB546 ,Active Status Bit 546" "Not active,Active" textline " " bitfld.long 0x00 1. " ASB545 ,Active Status Bit 545" "Not active,Active" bitfld.long 0x00 0. " ASB544 ,Active Status Bit 544" "Not active,Active" else rgroup.long 0x0344++0x03 line.long 0x0 "GICD_ICDABR17,Active Status Register 17" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(ad:(per.long(spr:0x31F30)&0xFFFC0000)+0x04))&0x0000001F)>=0x12) rgroup.long 0x0348++0x03 line.long 0x0 "GICD_ICDABR18,Active Status Register 18" bitfld.long 0x00 31. " ASB607 ,Active Status Bit 607" "Not active,Active" bitfld.long 0x00 30. " ASB606 ,Active Status Bit 606" "Not active,Active" bitfld.long 0x00 29. " ASB605 ,Active Status Bit 605" "Not active,Active" textline " " bitfld.long 0x00 28. " ASB604 ,Active Status Bit 604" "Not active,Active" bitfld.long 0x00 27. " ASB603 ,Active Status Bit 603" "Not active,Active" bitfld.long 0x00 26. " ASB602 ,Active Status Bit 602" "Not active,Active" textline " " bitfld.long 0x00 25. " ASB601 ,Active Status Bit 601" "Not active,Active" bitfld.long 0x00 24. " ASB600 ,Active Status Bit 600" "Not active,Active" bitfld.long 0x00 23. " ASB599 ,Active Status Bit 599" "Not active,Active" textline " " bitfld.long 0x00 22. " ASB598 ,Active Status Bit 598" "Not active,Active" bitfld.long 0x00 21. " ASB597 ,Active Status Bit 597" "Not active,Active" bitfld.long 0x00 20. " ASB596 ,Active Status Bit 596" "Not active,Active" textline " " bitfld.long 0x00 19. " ASB595 ,Active Status Bit 595" "Not active,Active" bitfld.long 0x00 18. " ASB594 ,Active Status Bit 594" "Not active,Active" bitfld.long 0x00 17. " ASB593 ,Active Status Bit 593" "Not active,Active" textline " " bitfld.long 0x00 16. " ASB592 ,Active Status Bit 592" "Not active,Active" bitfld.long 0x00 15. " ASB591 ,Active Status Bit 591" "Not active,Active" bitfld.long 0x00 14. " ASB590 ,Active Status Bit 590" "Not active,Active" textline " " bitfld.long 0x00 13. " ASB589 ,Active Status Bit 589" "Not active,Active" bitfld.long 0x00 12. " ASB588 ,Active Status Bit 588" "Not active,Active" bitfld.long 0x00 11. " ASB587 ,Active Status Bit 587" "Not active,Active" textline " " bitfld.long 0x00 10. " ASB586 ,Active Status Bit 586" "Not active,Active" bitfld.long 0x00 9. " ASB585 ,Active Status Bit 585" "Not active,Active" bitfld.long 0x00 8. " ASB584 ,Active Status Bit 584" "Not active,Active" textline " " bitfld.long 0x00 7. " ASB583 ,Active Status Bit 583" "Not active,Active" bitfld.long 0x00 6. " ASB582 ,Active Status Bit 582" "Not active,Active" bitfld.long 0x00 5. " ASB581 ,Active Status Bit 581" "Not active,Active" textline " " bitfld.long 0x00 4. " ASB580 ,Active Status Bit 580" "Not active,Active" bitfld.long 0x00 3. " ASB579 ,Active Status Bit 579" "Not active,Active" bitfld.long 0x00 2. " ASB578 ,Active Status Bit 578" "Not active,Active" textline " " bitfld.long 0x00 1. " ASB577 ,Active Status Bit 577" "Not active,Active" bitfld.long 0x00 0. " ASB576 ,Active Status Bit 576" "Not active,Active" else rgroup.long 0x0348++0x03 line.long 0x0 "GICD_ICDABR18,Active Status Register 18" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(ad:(per.long(spr:0x31F30)&0xFFFC0000)+0x04))&0x0000001F)>=0x13) rgroup.long 0x034C++0x03 line.long 0x0 "GICD_ICDABR19,Active Status Register 19" bitfld.long 0x00 31. " ASB639 ,Active Status Bit 639" "Not active,Active" bitfld.long 0x00 30. " ASB638 ,Active Status Bit 638" "Not active,Active" bitfld.long 0x00 29. " ASB637 ,Active Status Bit 637" "Not active,Active" textline " " bitfld.long 0x00 28. " ASB636 ,Active Status Bit 636" "Not active,Active" bitfld.long 0x00 27. " ASB635 ,Active Status Bit 635" "Not active,Active" bitfld.long 0x00 26. " ASB634 ,Active Status Bit 634" "Not active,Active" textline " " bitfld.long 0x00 25. " ASB633 ,Active Status Bit 633" "Not active,Active" bitfld.long 0x00 24. " ASB632 ,Active Status Bit 632" "Not active,Active" bitfld.long 0x00 23. " ASB631 ,Active Status Bit 631" "Not active,Active" textline " " bitfld.long 0x00 22. " ASB630 ,Active Status Bit 630" "Not active,Active" bitfld.long 0x00 21. " ASB629 ,Active Status Bit 629" "Not active,Active" bitfld.long 0x00 20. " ASB628 ,Active Status Bit 628" "Not active,Active" textline " " bitfld.long 0x00 19. " ASB627 ,Active Status Bit 627" "Not active,Active" bitfld.long 0x00 18. " ASB626 ,Active Status Bit 626" "Not active,Active" bitfld.long 0x00 17. " ASB625 ,Active Status Bit 625" "Not active,Active" textline " " bitfld.long 0x00 16. " ASB624 ,Active Status Bit 624" "Not active,Active" bitfld.long 0x00 15. " ASB623 ,Active Status Bit 623" "Not active,Active" bitfld.long 0x00 14. " ASB622 ,Active Status Bit 622" "Not active,Active" textline " " bitfld.long 0x00 13. " ASB621 ,Active Status Bit 621" "Not active,Active" bitfld.long 0x00 12. " ASB620 ,Active Status Bit 620" "Not active,Active" bitfld.long 0x00 11. " ASB619 ,Active Status Bit 619" "Not active,Active" textline " " bitfld.long 0x00 10. " ASB618 ,Active Status Bit 618" "Not active,Active" bitfld.long 0x00 9. " ASB617 ,Active Status Bit 617" "Not active,Active" bitfld.long 0x00 8. " ASB616 ,Active Status Bit 616" "Not active,Active" textline " " bitfld.long 0x00 7. " ASB615 ,Active Status Bit 615" "Not active,Active" bitfld.long 0x00 6. " ASB614 ,Active Status Bit 614" "Not active,Active" bitfld.long 0x00 5. " ASB613 ,Active Status Bit 613" "Not active,Active" textline " " bitfld.long 0x00 4. " ASB612 ,Active Status Bit 612" "Not active,Active" bitfld.long 0x00 3. " ASB611 ,Active Status Bit 611" "Not active,Active" bitfld.long 0x00 2. " ASB610 ,Active Status Bit 610" "Not active,Active" textline " " bitfld.long 0x00 1. " ASB609 ,Active Status Bit 609" "Not active,Active" bitfld.long 0x00 0. " ASB608 ,Active Status Bit 608" "Not active,Active" else rgroup.long 0x034C++0x03 line.long 0x0 "GICD_ICDABR19,Active Status Register 19" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(ad:(per.long(spr:0x31F30)&0xFFFC0000)+0x04))&0x0000001F)>=0x14) rgroup.long 0x0350++0x03 line.long 0x0 "GICD_ICDABR20,Active Status Register 20" bitfld.long 0x00 31. " ASB671 ,Active Status Bit 671" "Not active,Active" bitfld.long 0x00 30. " ASB670 ,Active Status Bit 670" "Not active,Active" bitfld.long 0x00 29. " ASB669 ,Active Status Bit 669" "Not active,Active" textline " " bitfld.long 0x00 28. " ASB668 ,Active Status Bit 668" "Not active,Active" bitfld.long 0x00 27. " ASB667 ,Active Status Bit 667" "Not active,Active" bitfld.long 0x00 26. " ASB666 ,Active Status Bit 666" "Not active,Active" textline " " bitfld.long 0x00 25. " ASB665 ,Active Status Bit 665" "Not active,Active" bitfld.long 0x00 24. " ASB664 ,Active Status Bit 664" "Not active,Active" bitfld.long 0x00 23. " ASB663 ,Active Status Bit 663" "Not active,Active" textline " " bitfld.long 0x00 22. " ASB662 ,Active Status Bit 662" "Not active,Active" bitfld.long 0x00 21. " ASB661 ,Active Status Bit 661" "Not active,Active" bitfld.long 0x00 20. " ASB660 ,Active Status Bit 660" "Not active,Active" textline " " bitfld.long 0x00 19. " ASB659 ,Active Status Bit 659" "Not active,Active" bitfld.long 0x00 18. " ASB658 ,Active Status Bit 658" "Not active,Active" bitfld.long 0x00 17. " ASB657 ,Active Status Bit 657" "Not active,Active" textline " " bitfld.long 0x00 16. " ASB656 ,Active Status Bit 656" "Not active,Active" bitfld.long 0x00 15. " ASB655 ,Active Status Bit 655" "Not active,Active" bitfld.long 0x00 14. " ASB654 ,Active Status Bit 654" "Not active,Active" textline " " bitfld.long 0x00 13. " ASB653 ,Active Status Bit 653" "Not active,Active" bitfld.long 0x00 12. " ASB652 ,Active Status Bit 652" "Not active,Active" bitfld.long 0x00 11. " ASB651 ,Active Status Bit 651" "Not active,Active" textline " " bitfld.long 0x00 10. " ASB650 ,Active Status Bit 650" "Not active,Active" bitfld.long 0x00 9. " ASB649 ,Active Status Bit 649" "Not active,Active" bitfld.long 0x00 8. " ASB648 ,Active Status Bit 648" "Not active,Active" textline " " bitfld.long 0x00 7. " ASB647 ,Active Status Bit 647" "Not active,Active" bitfld.long 0x00 6. " ASB646 ,Active Status Bit 646" "Not active,Active" bitfld.long 0x00 5. " ASB645 ,Active Status Bit 645" "Not active,Active" textline " " bitfld.long 0x00 4. " ASB644 ,Active Status Bit 644" "Not active,Active" bitfld.long 0x00 3. " ASB643 ,Active Status Bit 643" "Not active,Active" bitfld.long 0x00 2. " ASB642 ,Active Status Bit 642" "Not active,Active" textline " " bitfld.long 0x00 1. " ASB641 ,Active Status Bit 641" "Not active,Active" bitfld.long 0x00 0. " ASB640 ,Active Status Bit 640" "Not active,Active" else rgroup.long 0x0350++0x03 line.long 0x0 "GICD_ICDABR20,Active Status Register 20" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(ad:(per.long(spr:0x31F30)&0xFFFC0000)+0x04))&0x0000001F)>=0x15) rgroup.long 0x0354++0x03 line.long 0x0 "GICD_ICDABR21,Active Status Register 21" bitfld.long 0x00 31. " ASB703 ,Active Status Bit 703" "Not active,Active" bitfld.long 0x00 30. " ASB702 ,Active Status Bit 702" "Not active,Active" bitfld.long 0x00 29. " ASB701 ,Active Status Bit 701" "Not active,Active" textline " " bitfld.long 0x00 28. " ASB700 ,Active Status Bit 700" "Not active,Active" bitfld.long 0x00 27. " ASB699 ,Active Status Bit 699" "Not active,Active" bitfld.long 0x00 26. " ASB698 ,Active Status Bit 698" "Not active,Active" textline " " bitfld.long 0x00 25. " ASB697 ,Active Status Bit 697" "Not active,Active" bitfld.long 0x00 24. " ASB696 ,Active Status Bit 696" "Not active,Active" bitfld.long 0x00 23. " ASB695 ,Active Status Bit 695" "Not active,Active" textline " " bitfld.long 0x00 22. " ASB694 ,Active Status Bit 694" "Not active,Active" bitfld.long 0x00 21. " ASB693 ,Active Status Bit 693" "Not active,Active" bitfld.long 0x00 20. " ASB692 ,Active Status Bit 692" "Not active,Active" textline " " bitfld.long 0x00 19. " ASB691 ,Active Status Bit 691" "Not active,Active" bitfld.long 0x00 18. " ASB690 ,Active Status Bit 690" "Not active,Active" bitfld.long 0x00 17. " ASB689 ,Active Status Bit 689" "Not active,Active" textline " " bitfld.long 0x00 16. " ASB688 ,Active Status Bit 688" "Not active,Active" bitfld.long 0x00 15. " ASB687 ,Active Status Bit 687" "Not active,Active" bitfld.long 0x00 14. " ASB686 ,Active Status Bit 686" "Not active,Active" textline " " bitfld.long 0x00 13. " ASB685 ,Active Status Bit 685" "Not active,Active" bitfld.long 0x00 12. " ASB684 ,Active Status Bit 684" "Not active,Active" bitfld.long 0x00 11. " ASB683 ,Active Status Bit 683" "Not active,Active" textline " " bitfld.long 0x00 10. " ASB682 ,Active Status Bit 682" "Not active,Active" bitfld.long 0x00 9. " ASB681 ,Active Status Bit 681" "Not active,Active" bitfld.long 0x00 8. " ASB680 ,Active Status Bit 680" "Not active,Active" textline " " bitfld.long 0x00 7. " ASB679 ,Active Status Bit 679" "Not active,Active" bitfld.long 0x00 6. " ASB678 ,Active Status Bit 678" "Not active,Active" bitfld.long 0x00 5. " ASB677 ,Active Status Bit 677" "Not active,Active" textline " " bitfld.long 0x00 4. " ASB676 ,Active Status Bit 676" "Not active,Active" bitfld.long 0x00 3. " ASB675 ,Active Status Bit 675" "Not active,Active" bitfld.long 0x00 2. " ASB674 ,Active Status Bit 674" "Not active,Active" textline " " bitfld.long 0x00 1. " ASB673 ,Active Status Bit 673" "Not active,Active" bitfld.long 0x00 0. " ASB672 ,Active Status Bit 672" "Not active,Active" else rgroup.long 0x0354++0x03 line.long 0x0 "GICD_ICDABR21,Active Status Register 21" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(ad:(per.long(spr:0x31F30)&0xFFFC0000)+0x04))&0x0000001F)>=0x16) rgroup.long 0x0358++0x03 line.long 0x0 "GICD_ICDABR22,Active Status Register 22" bitfld.long 0x00 31. " ASB735 ,Active Status Bit 735" "Not active,Active" bitfld.long 0x00 30. " ASB734 ,Active Status Bit 734" "Not active,Active" bitfld.long 0x00 29. " ASB733 ,Active Status Bit 733" "Not active,Active" textline " " bitfld.long 0x00 28. " ASB732 ,Active Status Bit 732" "Not active,Active" bitfld.long 0x00 27. " ASB731 ,Active Status Bit 731" "Not active,Active" bitfld.long 0x00 26. " ASB730 ,Active Status Bit 730" "Not active,Active" textline " " bitfld.long 0x00 25. " ASB729 ,Active Status Bit 729" "Not active,Active" bitfld.long 0x00 24. " ASB728 ,Active Status Bit 728" "Not active,Active" bitfld.long 0x00 23. " ASB727 ,Active Status Bit 727" "Not active,Active" textline " " bitfld.long 0x00 22. " ASB726 ,Active Status Bit 726" "Not active,Active" bitfld.long 0x00 21. " ASB725 ,Active Status Bit 725" "Not active,Active" bitfld.long 0x00 20. " ASB724 ,Active Status Bit 724" "Not active,Active" textline " " bitfld.long 0x00 19. " ASB723 ,Active Status Bit 723" "Not active,Active" bitfld.long 0x00 18. " ASB722 ,Active Status Bit 722" "Not active,Active" bitfld.long 0x00 17. " ASB721 ,Active Status Bit 721" "Not active,Active" textline " " bitfld.long 0x00 16. " ASB720 ,Active Status Bit 720" "Not active,Active" bitfld.long 0x00 15. " ASB719 ,Active Status Bit 719" "Not active,Active" bitfld.long 0x00 14. " ASB718 ,Active Status Bit 718" "Not active,Active" textline " " bitfld.long 0x00 13. " ASB717 ,Active Status Bit 717" "Not active,Active" bitfld.long 0x00 12. " ASB716 ,Active Status Bit 716" "Not active,Active" bitfld.long 0x00 11. " ASB715 ,Active Status Bit 715" "Not active,Active" textline " " bitfld.long 0x00 10. " ASB714 ,Active Status Bit 714" "Not active,Active" bitfld.long 0x00 9. " ASB713 ,Active Status Bit 713" "Not active,Active" bitfld.long 0x00 8. " ASB712 ,Active Status Bit 712" "Not active,Active" textline " " bitfld.long 0x00 7. " ASB711 ,Active Status Bit 711" "Not active,Active" bitfld.long 0x00 6. " ASB710 ,Active Status Bit 710" "Not active,Active" bitfld.long 0x00 5. " ASB709 ,Active Status Bit 709" "Not active,Active" textline " " bitfld.long 0x00 4. " ASB708 ,Active Status Bit 708" "Not active,Active" bitfld.long 0x00 3. " ASB707 ,Active Status Bit 707" "Not active,Active" bitfld.long 0x00 2. " ASB706 ,Active Status Bit 706" "Not active,Active" textline " " bitfld.long 0x00 1. " ASB705 ,Active Status Bit 705" "Not active,Active" bitfld.long 0x00 0. " ASB704 ,Active Status Bit 704" "Not active,Active" else rgroup.long 0x0358++0x03 line.long 0x0 "GICD_ICDABR22,Active Status Register 22" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(ad:(per.long(spr:0x31F30)&0xFFFC0000)+0x04))&0x0000001F)>=0x17) rgroup.long 0x035C++0x03 line.long 0x0 "GICD_ICDABR23,Active Status Register 23" bitfld.long 0x00 31. " ASB767 ,Active Status Bit 767" "Not active,Active" bitfld.long 0x00 30. " ASB766 ,Active Status Bit 766" "Not active,Active" bitfld.long 0x00 29. " ASB765 ,Active Status Bit 765" "Not active,Active" textline " " bitfld.long 0x00 28. " ASB764 ,Active Status Bit 764" "Not active,Active" bitfld.long 0x00 27. " ASB763 ,Active Status Bit 763" "Not active,Active" bitfld.long 0x00 26. " ASB762 ,Active Status Bit 762" "Not active,Active" textline " " bitfld.long 0x00 25. " ASB761 ,Active Status Bit 761" "Not active,Active" bitfld.long 0x00 24. " ASB760 ,Active Status Bit 760" "Not active,Active" bitfld.long 0x00 23. " ASB759 ,Active Status Bit 759" "Not active,Active" textline " " bitfld.long 0x00 22. " ASB758 ,Active Status Bit 758" "Not active,Active" bitfld.long 0x00 21. " ASB757 ,Active Status Bit 757" "Not active,Active" bitfld.long 0x00 20. " ASB756 ,Active Status Bit 756" "Not active,Active" textline " " bitfld.long 0x00 19. " ASB755 ,Active Status Bit 755" "Not active,Active" bitfld.long 0x00 18. " ASB754 ,Active Status Bit 754" "Not active,Active" bitfld.long 0x00 17. " ASB753 ,Active Status Bit 753" "Not active,Active" textline " " bitfld.long 0x00 16. " ASB752 ,Active Status Bit 752" "Not active,Active" bitfld.long 0x00 15. " ASB751 ,Active Status Bit 751" "Not active,Active" bitfld.long 0x00 14. " ASB750 ,Active Status Bit 750" "Not active,Active" textline " " bitfld.long 0x00 13. " ASB749 ,Active Status Bit 749" "Not active,Active" bitfld.long 0x00 12. " ASB748 ,Active Status Bit 748" "Not active,Active" bitfld.long 0x00 11. " ASB747 ,Active Status Bit 747" "Not active,Active" textline " " bitfld.long 0x00 10. " ASB746 ,Active Status Bit 746" "Not active,Active" bitfld.long 0x00 9. " ASB745 ,Active Status Bit 745" "Not active,Active" bitfld.long 0x00 8. " ASB744 ,Active Status Bit 744" "Not active,Active" textline " " bitfld.long 0x00 7. " ASB743 ,Active Status Bit 743" "Not active,Active" bitfld.long 0x00 6. " ASB742 ,Active Status Bit 742" "Not active,Active" bitfld.long 0x00 5. " ASB741 ,Active Status Bit 741" "Not active,Active" textline " " bitfld.long 0x00 4. " ASB740 ,Active Status Bit 740" "Not active,Active" bitfld.long 0x00 3. " ASB739 ,Active Status Bit 739" "Not active,Active" bitfld.long 0x00 2. " ASB738 ,Active Status Bit 738" "Not active,Active" textline " " bitfld.long 0x00 1. " ASB737 ,Active Status Bit 737" "Not active,Active" bitfld.long 0x00 0. " ASB736 ,Active Status Bit 736" "Not active,Active" else rgroup.long 0x035C++0x03 line.long 0x0 "GICD_ICDABR23,Active Status Register 23" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(ad:(per.long(spr:0x31F30)&0xFFFC0000)+0x04))&0x0000001F)>=0x18) rgroup.long 0x0360++0x03 line.long 0x0 "GICD_ICDABR24,Active Status Register 24" bitfld.long 0x00 31. " ASB799 ,Active Status Bit 799" "Not active,Active" bitfld.long 0x00 30. " ASB798 ,Active Status Bit 798" "Not active,Active" bitfld.long 0x00 29. " ASB797 ,Active Status Bit 797" "Not active,Active" textline " " bitfld.long 0x00 28. " ASB796 ,Active Status Bit 796" "Not active,Active" bitfld.long 0x00 27. " ASB795 ,Active Status Bit 795" "Not active,Active" bitfld.long 0x00 26. " ASB794 ,Active Status Bit 794" "Not active,Active" textline " " bitfld.long 0x00 25. " ASB793 ,Active Status Bit 793" "Not active,Active" bitfld.long 0x00 24. " ASB792 ,Active Status Bit 792" "Not active,Active" bitfld.long 0x00 23. " ASB791 ,Active Status Bit 791" "Not active,Active" textline " " bitfld.long 0x00 22. " ASB790 ,Active Status Bit 790" "Not active,Active" bitfld.long 0x00 21. " ASB789 ,Active Status Bit 789" "Not active,Active" bitfld.long 0x00 20. " ASB788 ,Active Status Bit 788" "Not active,Active" textline " " bitfld.long 0x00 19. " ASB787 ,Active Status Bit 787" "Not active,Active" bitfld.long 0x00 18. " ASB786 ,Active Status Bit 786" "Not active,Active" bitfld.long 0x00 17. " ASB785 ,Active Status Bit 785" "Not active,Active" textline " " bitfld.long 0x00 16. " ASB784 ,Active Status Bit 784" "Not active,Active" bitfld.long 0x00 15. " ASB783 ,Active Status Bit 783" "Not active,Active" bitfld.long 0x00 14. " ASB782 ,Active Status Bit 782" "Not active,Active" textline " " bitfld.long 0x00 13. " ASB781 ,Active Status Bit 781" "Not active,Active" bitfld.long 0x00 12. " ASB780 ,Active Status Bit 780" "Not active,Active" bitfld.long 0x00 11. " ASB779 ,Active Status Bit 779" "Not active,Active" textline " " bitfld.long 0x00 10. " ASB778 ,Active Status Bit 778" "Not active,Active" bitfld.long 0x00 9. " ASB777 ,Active Status Bit 777" "Not active,Active" bitfld.long 0x00 8. " ASB776 ,Active Status Bit 776" "Not active,Active" textline " " bitfld.long 0x00 7. " ASB775 ,Active Status Bit 775" "Not active,Active" bitfld.long 0x00 6. " ASB774 ,Active Status Bit 774" "Not active,Active" bitfld.long 0x00 5. " ASB773 ,Active Status Bit 773" "Not active,Active" textline " " bitfld.long 0x00 4. " ASB772 ,Active Status Bit 772" "Not active,Active" bitfld.long 0x00 3. " ASB771 ,Active Status Bit 771" "Not active,Active" bitfld.long 0x00 2. " ASB770 ,Active Status Bit 770" "Not active,Active" textline " " bitfld.long 0x00 1. " ASB769 ,Active Status Bit 769" "Not active,Active" bitfld.long 0x00 0. " ASB768 ,Active Status Bit 768" "Not active,Active" else rgroup.long 0x0360++0x03 line.long 0x0 "GICD_ICDABR24,Active Status Register 24" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(ad:(per.long(spr:0x31F30)&0xFFFC0000)+0x04))&0x0000001F)>=0x19) rgroup.long 0x0364++0x03 line.long 0x0 "GICD_ICDABR25,Active Status Register 25" bitfld.long 0x00 31. " ASB831 ,Active Status Bit 831" "Not active,Active" bitfld.long 0x00 30. " ASB830 ,Active Status Bit 830" "Not active,Active" bitfld.long 0x00 29. " ASB829 ,Active Status Bit 829" "Not active,Active" textline " " bitfld.long 0x00 28. " ASB828 ,Active Status Bit 828" "Not active,Active" bitfld.long 0x00 27. " ASB827 ,Active Status Bit 827" "Not active,Active" bitfld.long 0x00 26. " ASB826 ,Active Status Bit 826" "Not active,Active" textline " " bitfld.long 0x00 25. " ASB825 ,Active Status Bit 825" "Not active,Active" bitfld.long 0x00 24. " ASB824 ,Active Status Bit 824" "Not active,Active" bitfld.long 0x00 23. " ASB823 ,Active Status Bit 823" "Not active,Active" textline " " bitfld.long 0x00 22. " ASB822 ,Active Status Bit 822" "Not active,Active" bitfld.long 0x00 21. " ASB821 ,Active Status Bit 821" "Not active,Active" bitfld.long 0x00 20. " ASB820 ,Active Status Bit 820" "Not active,Active" textline " " bitfld.long 0x00 19. " ASB819 ,Active Status Bit 819" "Not active,Active" bitfld.long 0x00 18. " ASB818 ,Active Status Bit 818" "Not active,Active" bitfld.long 0x00 17. " ASB817 ,Active Status Bit 817" "Not active,Active" textline " " bitfld.long 0x00 16. " ASB816 ,Active Status Bit 816" "Not active,Active" bitfld.long 0x00 15. " ASB815 ,Active Status Bit 815" "Not active,Active" bitfld.long 0x00 14. " ASB814 ,Active Status Bit 814" "Not active,Active" textline " " bitfld.long 0x00 13. " ASB813 ,Active Status Bit 813" "Not active,Active" bitfld.long 0x00 12. " ASB812 ,Active Status Bit 812" "Not active,Active" bitfld.long 0x00 11. " ASB811 ,Active Status Bit 811" "Not active,Active" textline " " bitfld.long 0x00 10. " ASB810 ,Active Status Bit 810" "Not active,Active" bitfld.long 0x00 9. " ASB809 ,Active Status Bit 809" "Not active,Active" bitfld.long 0x00 8. " ASB808 ,Active Status Bit 808" "Not active,Active" textline " " bitfld.long 0x00 7. " ASB807 ,Active Status Bit 807" "Not active,Active" bitfld.long 0x00 6. " ASB806 ,Active Status Bit 806" "Not active,Active" bitfld.long 0x00 5. " ASB805 ,Active Status Bit 805" "Not active,Active" textline " " bitfld.long 0x00 4. " ASB804 ,Active Status Bit 804" "Not active,Active" bitfld.long 0x00 3. " ASB803 ,Active Status Bit 803" "Not active,Active" bitfld.long 0x00 2. " ASB802 ,Active Status Bit 802" "Not active,Active" textline " " bitfld.long 0x00 1. " ASB801 ,Active Status Bit 801" "Not active,Active" bitfld.long 0x00 0. " ASB800 ,Active Status Bit 800" "Not active,Active" else rgroup.long 0x0364++0x03 line.long 0x0 "GICD_ICDABR25,Active Status Register 25" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(ad:(per.long(spr:0x31F30)&0xFFFC0000)+0x04))&0x0000001F)>=0x1A) rgroup.long 0x0368++0x03 line.long 0x0 "GICD_ICDABR26,Active Status Register 26" bitfld.long 0x00 31. " ASB863 ,Active Status Bit 863" "Not active,Active" bitfld.long 0x00 30. " ASB862 ,Active Status Bit 862" "Not active,Active" bitfld.long 0x00 29. " ASB861 ,Active Status Bit 861" "Not active,Active" textline " " bitfld.long 0x00 28. " ASB860 ,Active Status Bit 860" "Not active,Active" bitfld.long 0x00 27. " ASB859 ,Active Status Bit 859" "Not active,Active" bitfld.long 0x00 26. " ASB858 ,Active Status Bit 858" "Not active,Active" textline " " bitfld.long 0x00 25. " ASB857 ,Active Status Bit 857" "Not active,Active" bitfld.long 0x00 24. " ASB856 ,Active Status Bit 856" "Not active,Active" bitfld.long 0x00 23. " ASB855 ,Active Status Bit 855" "Not active,Active" textline " " bitfld.long 0x00 22. " ASB854 ,Active Status Bit 854" "Not active,Active" bitfld.long 0x00 21. " ASB853 ,Active Status Bit 853" "Not active,Active" bitfld.long 0x00 20. " ASB852 ,Active Status Bit 852" "Not active,Active" textline " " bitfld.long 0x00 19. " ASB851 ,Active Status Bit 851" "Not active,Active" bitfld.long 0x00 18. " ASB850 ,Active Status Bit 850" "Not active,Active" bitfld.long 0x00 17. " ASB849 ,Active Status Bit 849" "Not active,Active" textline " " bitfld.long 0x00 16. " ASB848 ,Active Status Bit 848" "Not active,Active" bitfld.long 0x00 15. " ASB847 ,Active Status Bit 847" "Not active,Active" bitfld.long 0x00 14. " ASB846 ,Active Status Bit 846" "Not active,Active" textline " " bitfld.long 0x00 13. " ASB845 ,Active Status Bit 845" "Not active,Active" bitfld.long 0x00 12. " ASB844 ,Active Status Bit 844" "Not active,Active" bitfld.long 0x00 11. " ASB843 ,Active Status Bit 843" "Not active,Active" textline " " bitfld.long 0x00 10. " ASB842 ,Active Status Bit 842" "Not active,Active" bitfld.long 0x00 9. " ASB841 ,Active Status Bit 841" "Not active,Active" bitfld.long 0x00 8. " ASB840 ,Active Status Bit 840" "Not active,Active" textline " " bitfld.long 0x00 7. " ASB839 ,Active Status Bit 839" "Not active,Active" bitfld.long 0x00 6. " ASB838 ,Active Status Bit 838" "Not active,Active" bitfld.long 0x00 5. " ASB837 ,Active Status Bit 837" "Not active,Active" textline " " bitfld.long 0x00 4. " ASB836 ,Active Status Bit 836" "Not active,Active" bitfld.long 0x00 3. " ASB835 ,Active Status Bit 835" "Not active,Active" bitfld.long 0x00 2. " ASB834 ,Active Status Bit 834" "Not active,Active" textline " " bitfld.long 0x00 1. " ASB833 ,Active Status Bit 833" "Not active,Active" bitfld.long 0x00 0. " ASB832 ,Active Status Bit 832" "Not active,Active" else rgroup.long 0x0368++0x03 line.long 0x0 "GICD_ICDABR26,Active Status Register 26" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(ad:(per.long(spr:0x31F30)&0xFFFC0000)+0x04))&0x0000001F)>=0x1B) rgroup.long 0x036C++0x03 line.long 0x0 "GICD_ICDABR27,Active Status Register 27" bitfld.long 0x00 31. " ASB895 ,Active Status Bit 895" "Not active,Active" bitfld.long 0x00 30. " ASB894 ,Active Status Bit 894" "Not active,Active" bitfld.long 0x00 29. " ASB893 ,Active Status Bit 893" "Not active,Active" textline " " bitfld.long 0x00 28. " ASB892 ,Active Status Bit 892" "Not active,Active" bitfld.long 0x00 27. " ASB891 ,Active Status Bit 891" "Not active,Active" bitfld.long 0x00 26. " ASB890 ,Active Status Bit 890" "Not active,Active" textline " " bitfld.long 0x00 25. " ASB889 ,Active Status Bit 889" "Not active,Active" bitfld.long 0x00 24. " ASB888 ,Active Status Bit 888" "Not active,Active" bitfld.long 0x00 23. " ASB887 ,Active Status Bit 887" "Not active,Active" textline " " bitfld.long 0x00 22. " ASB886 ,Active Status Bit 886" "Not active,Active" bitfld.long 0x00 21. " ASB885 ,Active Status Bit 885" "Not active,Active" bitfld.long 0x00 20. " ASB884 ,Active Status Bit 884" "Not active,Active" textline " " bitfld.long 0x00 19. " ASB883 ,Active Status Bit 883" "Not active,Active" bitfld.long 0x00 18. " ASB882 ,Active Status Bit 882" "Not active,Active" bitfld.long 0x00 17. " ASB881 ,Active Status Bit 881" "Not active,Active" textline " " bitfld.long 0x00 16. " ASB880 ,Active Status Bit 880" "Not active,Active" bitfld.long 0x00 15. " ASB879 ,Active Status Bit 879" "Not active,Active" bitfld.long 0x00 14. " ASB878 ,Active Status Bit 878" "Not active,Active" textline " " bitfld.long 0x00 13. " ASB877 ,Active Status Bit 877" "Not active,Active" bitfld.long 0x00 12. " ASB876 ,Active Status Bit 876" "Not active,Active" bitfld.long 0x00 11. " ASB875 ,Active Status Bit 875" "Not active,Active" textline " " bitfld.long 0x00 10. " ASB874 ,Active Status Bit 874" "Not active,Active" bitfld.long 0x00 9. " ASB873 ,Active Status Bit 873" "Not active,Active" bitfld.long 0x00 8. " ASB872 ,Active Status Bit 872" "Not active,Active" textline " " bitfld.long 0x00 7. " ASB871 ,Active Status Bit 871" "Not active,Active" bitfld.long 0x00 6. " ASB870 ,Active Status Bit 870" "Not active,Active" bitfld.long 0x00 5. " ASB869 ,Active Status Bit 869" "Not active,Active" textline " " bitfld.long 0x00 4. " ASB868 ,Active Status Bit 868" "Not active,Active" bitfld.long 0x00 3. " ASB867 ,Active Status Bit 867" "Not active,Active" bitfld.long 0x00 2. " ASB866 ,Active Status Bit 866" "Not active,Active" textline " " bitfld.long 0x00 1. " ASB865 ,Active Status Bit 865" "Not active,Active" bitfld.long 0x00 0. " ASB864 ,Active Status Bit 864" "Not active,Active" else rgroup.long 0x036C++0x03 line.long 0x0 "GICD_ICDABR27,Active Status Register 27" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(ad:(per.long(spr:0x31F30)&0xFFFC0000)+0x04))&0x0000001F)>=0x1C) rgroup.long 0x0370++0x03 line.long 0x0 "GICD_ICDABR28,Active Status Register 28" bitfld.long 0x00 31. " ASB927 ,Active Status Bit 927" "Not active,Active" bitfld.long 0x00 30. " ASB926 ,Active Status Bit 926" "Not active,Active" bitfld.long 0x00 29. " ASB925 ,Active Status Bit 925" "Not active,Active" textline " " bitfld.long 0x00 28. " ASB924 ,Active Status Bit 924" "Not active,Active" bitfld.long 0x00 27. " ASB923 ,Active Status Bit 923" "Not active,Active" bitfld.long 0x00 26. " ASB922 ,Active Status Bit 922" "Not active,Active" textline " " bitfld.long 0x00 25. " ASB921 ,Active Status Bit 921" "Not active,Active" bitfld.long 0x00 24. " ASB920 ,Active Status Bit 920" "Not active,Active" bitfld.long 0x00 23. " ASB919 ,Active Status Bit 919" "Not active,Active" textline " " bitfld.long 0x00 22. " ASB918 ,Active Status Bit 918" "Not active,Active" bitfld.long 0x00 21. " ASB917 ,Active Status Bit 917" "Not active,Active" bitfld.long 0x00 20. " ASB916 ,Active Status Bit 916" "Not active,Active" textline " " bitfld.long 0x00 19. " ASB915 ,Active Status Bit 915" "Not active,Active" bitfld.long 0x00 18. " ASB914 ,Active Status Bit 914" "Not active,Active" bitfld.long 0x00 17. " ASB913 ,Active Status Bit 913" "Not active,Active" textline " " bitfld.long 0x00 16. " ASB912 ,Active Status Bit 912" "Not active,Active" bitfld.long 0x00 15. " ASB911 ,Active Status Bit 911" "Not active,Active" bitfld.long 0x00 14. " ASB910 ,Active Status Bit 910" "Not active,Active" textline " " bitfld.long 0x00 13. " ASB909 ,Active Status Bit 909" "Not active,Active" bitfld.long 0x00 12. " ASB908 ,Active Status Bit 908" "Not active,Active" bitfld.long 0x00 11. " ASB907 ,Active Status Bit 907" "Not active,Active" textline " " bitfld.long 0x00 10. " ASB906 ,Active Status Bit 906" "Not active,Active" bitfld.long 0x00 9. " ASB905 ,Active Status Bit 905" "Not active,Active" bitfld.long 0x00 8. " ASB904 ,Active Status Bit 904" "Not active,Active" textline " " bitfld.long 0x00 7. " ASB903 ,Active Status Bit 903" "Not active,Active" bitfld.long 0x00 6. " ASB902 ,Active Status Bit 902" "Not active,Active" bitfld.long 0x00 5. " ASB901 ,Active Status Bit 901" "Not active,Active" textline " " bitfld.long 0x00 4. " ASB900 ,Active Status Bit 900" "Not active,Active" bitfld.long 0x00 3. " ASB899 ,Active Status Bit 899" "Not active,Active" bitfld.long 0x00 2. " ASB898 ,Active Status Bit 898" "Not active,Active" textline " " bitfld.long 0x00 1. " ASB897 ,Active Status Bit 897" "Not active,Active" bitfld.long 0x00 0. " ASB896 ,Active Status Bit 896" "Not active,Active" else rgroup.long 0x0370++0x03 line.long 0x0 "GICD_ICDABR28,Active Status Register 28" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(ad:(per.long(spr:0x31F30)&0xFFFC0000)+0x04))&0x0000001F)>=0x1D) rgroup.long 0x0374++0x03 line.long 0x0 "GICD_ICDABR29,Active Status Register 29" bitfld.long 0x00 31. " ASB959 ,Active Status Bit 959" "Not active,Active" bitfld.long 0x00 30. " ASB958 ,Active Status Bit 958" "Not active,Active" bitfld.long 0x00 29. " ASB957 ,Active Status Bit 957" "Not active,Active" textline " " bitfld.long 0x00 28. " ASB956 ,Active Status Bit 956" "Not active,Active" bitfld.long 0x00 27. " ASB955 ,Active Status Bit 955" "Not active,Active" bitfld.long 0x00 26. " ASB954 ,Active Status Bit 954" "Not active,Active" textline " " bitfld.long 0x00 25. " ASB953 ,Active Status Bit 953" "Not active,Active" bitfld.long 0x00 24. " ASB952 ,Active Status Bit 952" "Not active,Active" bitfld.long 0x00 23. " ASB951 ,Active Status Bit 951" "Not active,Active" textline " " bitfld.long 0x00 22. " ASB950 ,Active Status Bit 950" "Not active,Active" bitfld.long 0x00 21. " ASB949 ,Active Status Bit 949" "Not active,Active" bitfld.long 0x00 20. " ASB948 ,Active Status Bit 948" "Not active,Active" textline " " bitfld.long 0x00 19. " ASB947 ,Active Status Bit 947" "Not active,Active" bitfld.long 0x00 18. " ASB946 ,Active Status Bit 946" "Not active,Active" bitfld.long 0x00 17. " ASB945 ,Active Status Bit 945" "Not active,Active" textline " " bitfld.long 0x00 16. " ASB944 ,Active Status Bit 944" "Not active,Active" bitfld.long 0x00 15. " ASB943 ,Active Status Bit 943" "Not active,Active" bitfld.long 0x00 14. " ASB942 ,Active Status Bit 942" "Not active,Active" textline " " bitfld.long 0x00 13. " ASB941 ,Active Status Bit 941" "Not active,Active" bitfld.long 0x00 12. " ASB940 ,Active Status Bit 940" "Not active,Active" bitfld.long 0x00 11. " ASB939 ,Active Status Bit 939" "Not active,Active" textline " " bitfld.long 0x00 10. " ASB938 ,Active Status Bit 938" "Not active,Active" bitfld.long 0x00 9. " ASB937 ,Active Status Bit 937" "Not active,Active" bitfld.long 0x00 8. " ASB936 ,Active Status Bit 936" "Not active,Active" textline " " bitfld.long 0x00 7. " ASB935 ,Active Status Bit 935" "Not active,Active" bitfld.long 0x00 6. " ASB934 ,Active Status Bit 934" "Not active,Active" bitfld.long 0x00 5. " ASB933 ,Active Status Bit 933" "Not active,Active" textline " " bitfld.long 0x00 4. " ASB932 ,Active Status Bit 932" "Not active,Active" bitfld.long 0x00 3. " ASB931 ,Active Status Bit 931" "Not active,Active" bitfld.long 0x00 2. " ASB930 ,Active Status Bit 930" "Not active,Active" textline " " bitfld.long 0x00 1. " ASB929 ,Active Status Bit 929" "Not active,Active" bitfld.long 0x00 0. " ASB928 ,Active Status Bit 928" "Not active,Active" else rgroup.long 0x0374++0x03 line.long 0x0 "GICD_ICDABR29,Active Status Register 29" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(ad:(per.long(spr:0x31F30)&0xFFFC0000)+0x04))&0x0000001F)>=0x1E) rgroup.long 0x0378++0x03 line.long 0x0 "GICD_ICDABR30,Active Status Register 30" bitfld.long 0x00 31. " ASB991 ,Active Status Bit 991" "Not active,Active" bitfld.long 0x00 30. " ASB990 ,Active Status Bit 990" "Not active,Active" bitfld.long 0x00 29. " ASB989 ,Active Status Bit 989" "Not active,Active" textline " " bitfld.long 0x00 28. " ASB988 ,Active Status Bit 988" "Not active,Active" bitfld.long 0x00 27. " ASB987 ,Active Status Bit 987" "Not active,Active" bitfld.long 0x00 26. " ASB986 ,Active Status Bit 986" "Not active,Active" textline " " bitfld.long 0x00 25. " ASB985 ,Active Status Bit 985" "Not active,Active" bitfld.long 0x00 24. " ASB984 ,Active Status Bit 984" "Not active,Active" bitfld.long 0x00 23. " ASB983 ,Active Status Bit 983" "Not active,Active" textline " " bitfld.long 0x00 22. " ASB982 ,Active Status Bit 982" "Not active,Active" bitfld.long 0x00 21. " ASB981 ,Active Status Bit 981" "Not active,Active" bitfld.long 0x00 20. " ASB980 ,Active Status Bit 980" "Not active,Active" textline " " bitfld.long 0x00 19. " ASB979 ,Active Status Bit 979" "Not active,Active" bitfld.long 0x00 18. " ASB978 ,Active Status Bit 978" "Not active,Active" bitfld.long 0x00 17. " ASB977 ,Active Status Bit 977" "Not active,Active" textline " " bitfld.long 0x00 16. " ASB976 ,Active Status Bit 976" "Not active,Active" bitfld.long 0x00 15. " ASB975 ,Active Status Bit 975" "Not active,Active" bitfld.long 0x00 14. " ASB974 ,Active Status Bit 974" "Not active,Active" textline " " bitfld.long 0x00 13. " ASB973 ,Active Status Bit 973" "Not active,Active" bitfld.long 0x00 12. " ASB972 ,Active Status Bit 972" "Not active,Active" bitfld.long 0x00 11. " ASB971 ,Active Status Bit 971" "Not active,Active" textline " " bitfld.long 0x00 10. " ASB970 ,Active Status Bit 970" "Not active,Active" bitfld.long 0x00 9. " ASB969 ,Active Status Bit 969" "Not active,Active" bitfld.long 0x00 8. " ASB968 ,Active Status Bit 968" "Not active,Active" textline " " bitfld.long 0x00 7. " ASB967 ,Active Status Bit 967" "Not active,Active" bitfld.long 0x00 6. " ASB966 ,Active Status Bit 966" "Not active,Active" bitfld.long 0x00 5. " ASB965 ,Active Status Bit 965" "Not active,Active" textline " " bitfld.long 0x00 4. " ASB964 ,Active Status Bit 964" "Not active,Active" bitfld.long 0x00 3. " ASB963 ,Active Status Bit 963" "Not active,Active" bitfld.long 0x00 2. " ASB962 ,Active Status Bit 962" "Not active,Active" textline " " bitfld.long 0x00 1. " ASB961 ,Active Status Bit 961" "Not active,Active" bitfld.long 0x00 0. " ASB960 ,Active Status Bit 960" "Not active,Active" else rgroup.long 0x0378++0x03 line.long 0x0 "GICD_ICDABR30,Active Status Register 30" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(ad:(per.long(spr:0x31F30)&0xFFFC0000)+0x04))&0x0000001F)==0x1F) rgroup.long 0x037C++0x03 line.long 0x0 "GICD_ICDABR31,Active Status Register 31" bitfld.long 0x00 27. " ASB1019 ,Active Status Bit 1019" "Not active,Active" bitfld.long 0x00 26. " ASB1018 ,Active Status Bit 1018" "Not active,Active" textline " " bitfld.long 0x00 25. " ASB1017 ,Active Status Bit 1017" "Not active,Active" bitfld.long 0x00 24. " ASB1016 ,Active Status Bit 1016" "Not active,Active" bitfld.long 0x00 23. " ASB1015 ,Active Status Bit 1015" "Not active,Active" textline " " bitfld.long 0x00 22. " ASB1014 ,Active Status Bit 1014" "Not active,Active" bitfld.long 0x00 21. " ASB1013 ,Active Status Bit 1013" "Not active,Active" bitfld.long 0x00 20. " ASB1012 ,Active Status Bit 1012" "Not active,Active" textline " " bitfld.long 0x00 19. " ASB1011 ,Active Status Bit 1011" "Not active,Active" bitfld.long 0x00 18. " ASB1010 ,Active Status Bit 1010" "Not active,Active" bitfld.long 0x00 17. " ASB1009 ,Active Status Bit 1009" "Not active,Active" textline " " bitfld.long 0x00 16. " ASB1008 ,Active Status Bit 1008" "Not active,Active" bitfld.long 0x00 15. " ASB1007 ,Active Status Bit 1007" "Not active,Active" bitfld.long 0x00 14. " ASB1006 ,Active Status Bit 1006" "Not active,Active" textline " " bitfld.long 0x00 13. " ASB1005 ,Active Status Bit 1005" "Not active,Active" bitfld.long 0x00 12. " ASB1004 ,Active Status Bit 1004" "Not active,Active" bitfld.long 0x00 11. " ASB1003 ,Active Status Bit 1003" "Not active,Active" textline " " bitfld.long 0x00 10. " ASB1002 ,Active Status Bit 1002" "Not active,Active" bitfld.long 0x00 9. " ASB1001 ,Active Status Bit 1001" "Not active,Active" bitfld.long 0x00 8. " ASB1000 ,Active Status Bit 1000" "Not active,Active" textline " " bitfld.long 0x00 7. " ASB999 ,Active Status Bit 999" "Not active,Active" bitfld.long 0x00 6. " ASB998 ,Active Status Bit 998" "Not active,Active" bitfld.long 0x00 5. " ASB997 ,Active Status Bit 997" "Not active,Active" textline " " bitfld.long 0x00 4. " ASB996 ,Active Status Bit 996" "Not active,Active" bitfld.long 0x00 3. " ASB995 ,Active Status Bit 995" "Not active,Active" bitfld.long 0x00 2. " ASB994 ,Active Status Bit 994" "Not active,Active" textline " " bitfld.long 0x00 1. " ASB993 ,Active Status Bit 993" "Not active,Active" bitfld.long 0x00 0. " ASB992 ,Active Status Bit 992" "Not active,Active" else rgroup.long 0x037C++0x03 line.long 0x0 "GICD_ICDABR31,Active Status Register 31" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif else group.long 0x0300++0x03 line.long 0x0 "GICD_SET/CLR_ACTIVER0,Interrupt Set/Clear Active Register 0" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRACTIVE31 ,Set/Clear Active Bit 31" "Not active,Active" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRACTIVE30 ,Set/Clear Active Bit 30" "Not active,Active" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRACTIVE29 ,Set/Clear Active Bit 29" "Not active,Active" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRACTIVE28 ,Set/Clear Active Bit 28" "Not active,Active" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRACTIVE27 ,Set/Clear Active Bit 27" "Not active,Active" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRACTIVE26 ,Set/Clear Active Bit 26" "Not active,Active" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRACTIVE25 ,Set/Clear Active Bit 25" "Not active,Active" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRACTIVE24 ,Set/Clear Active Bit 24" "Not active,Active" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRACTIVE23 ,Set/Clear Active Bit 23" "Not active,Active" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRACTIVE22 ,Set/Clear Active Bit 22" "Not active,Active" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRACTIVE21 ,Set/Clear Active Bit 21" "Not active,Active" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRACTIVE20 ,Set/Clear Active Bit 20" "Not active,Active" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRACTIVE19 ,Set/Clear Active Bit 19" "Not active,Active" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRACTIVE18 ,Set/Clear Active Bit 18" "Not active,Active" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRACTIVE17 ,Set/Clear Active Bit 17" "Not active,Active" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRACTIVE16 ,Set/Clear Active Bit 16" "Not active,Active" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRACTIVE15 ,Set/Clear Active Bit 15" "Not active,Active" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRACTIVE14 ,Set/Clear Active Bit 14" "Not active,Active" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRACTIVE13 ,Set/Clear Active Bit 13" "Not active,Active" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRACTIVE12 ,Set/Clear Active Bit 12" "Not active,Active" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRACTIVE11 ,Set/Clear Active Bit 11" "Not active,Active" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRACTIVE10 ,Set/Clear Active Bit 10" "Not active,Active" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRACTIVE9 ,Set/Clear Active Bit 9" "Not active,Active" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRACTIVE8 ,Set/Clear Active Bit 8" "Not active,Active" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRACTIVE7 ,Set/Clear Active Bit 7" "Not active,Active" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRACTIVE6 ,Set/Clear Active Bit 6" "Not active,Active" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRACTIVE5 ,Set/Clear Active Bit 5" "Not active,Active" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRACTIVE4 ,Set/Clear Active Bit 4" "Not active,Active" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRACTIVE3 ,Set/Clear Active Bit 3" "Not active,Active" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRACTIVE2 ,Set/Clear Active Bit 2" "Not active,Active" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRACTIVE1 ,Set/Clear Active Bit 1" "Not active,Active" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRACTIVE0 ,Set/Clear Active Bit 0" "Not active,Active" if (((per.l(ad:(per.long(spr:0x31F30)&0xFFFC0000)+0x04))&0x0000001F)>=0x01) group.long 0x0304++0x03 line.long 0x0 "GICD_SET/CLR_ACTIVER1,Interrupt Set/Clear Active Register 1" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRACTIVE63 ,Set/Clear Active Bit 63" "Not active,Active" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRACTIVE62 ,Set/Clear Active Bit 62" "Not active,Active" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRACTIVE61 ,Set/Clear Active Bit 61" "Not active,Active" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRACTIVE60 ,Set/Clear Active Bit 60" "Not active,Active" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRACTIVE59 ,Set/Clear Active Bit 59" "Not active,Active" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRACTIVE58 ,Set/Clear Active Bit 58" "Not active,Active" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRACTIVE57 ,Set/Clear Active Bit 57" "Not active,Active" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRACTIVE56 ,Set/Clear Active Bit 56" "Not active,Active" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRACTIVE55 ,Set/Clear Active Bit 55" "Not active,Active" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRACTIVE54 ,Set/Clear Active Bit 54" "Not active,Active" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRACTIVE53 ,Set/Clear Active Bit 53" "Not active,Active" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRACTIVE52 ,Set/Clear Active Bit 52" "Not active,Active" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRACTIVE51 ,Set/Clear Active Bit 51" "Not active,Active" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRACTIVE50 ,Set/Clear Active Bit 50" "Not active,Active" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRACTIVE49 ,Set/Clear Active Bit 49" "Not active,Active" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRACTIVE48 ,Set/Clear Active Bit 48" "Not active,Active" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRACTIVE47 ,Set/Clear Active Bit 47" "Not active,Active" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRACTIVE46 ,Set/Clear Active Bit 46" "Not active,Active" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRACTIVE45 ,Set/Clear Active Bit 45" "Not active,Active" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRACTIVE44 ,Set/Clear Active Bit 44" "Not active,Active" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRACTIVE43 ,Set/Clear Active Bit 43" "Not active,Active" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRACTIVE42 ,Set/Clear Active Bit 42" "Not active,Active" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRACTIVE41 ,Set/Clear Active Bit 41" "Not active,Active" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRACTIVE40 ,Set/Clear Active Bit 40" "Not active,Active" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRACTIVE39 ,Set/Clear Active Bit 39" "Not active,Active" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRACTIVE38 ,Set/Clear Active Bit 38" "Not active,Active" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRACTIVE37 ,Set/Clear Active Bit 37" "Not active,Active" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRACTIVE36 ,Set/Clear Active Bit 36" "Not active,Active" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRACTIVE35 ,Set/Clear Active Bit 35" "Not active,Active" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRACTIVE34 ,Set/Clear Active Bit 34" "Not active,Active" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRACTIVE33 ,Set/Clear Active Bit 33" "Not active,Active" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRACTIVE32 ,Set/Clear Active Bit 32" "Not active,Active" else rgroup.long 0x0304++0x03 line.long 0x0 "GICD_SET/CLR_ACTIVER1,Interrupt Set/Clear Active Register 1" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(ad:(per.long(spr:0x31F30)&0xFFFC0000)+0x04))&0x0000001F)>=0x02) group.long 0x0308++0x03 line.long 0x0 "GICD_SET/CLR_ACTIVER2,Interrupt Set/Clear Active Register 2" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRACTIVE95 ,Set/Clear Active Bit 95" "Not active,Active" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRACTIVE94 ,Set/Clear Active Bit 94" "Not active,Active" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRACTIVE93 ,Set/Clear Active Bit 93" "Not active,Active" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRACTIVE92 ,Set/Clear Active Bit 92" "Not active,Active" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRACTIVE91 ,Set/Clear Active Bit 91" "Not active,Active" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRACTIVE90 ,Set/Clear Active Bit 90" "Not active,Active" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRACTIVE89 ,Set/Clear Active Bit 89" "Not active,Active" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRACTIVE88 ,Set/Clear Active Bit 88" "Not active,Active" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRACTIVE87 ,Set/Clear Active Bit 87" "Not active,Active" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRACTIVE86 ,Set/Clear Active Bit 86" "Not active,Active" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRACTIVE85 ,Set/Clear Active Bit 85" "Not active,Active" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRACTIVE84 ,Set/Clear Active Bit 84" "Not active,Active" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRACTIVE83 ,Set/Clear Active Bit 83" "Not active,Active" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRACTIVE82 ,Set/Clear Active Bit 82" "Not active,Active" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRACTIVE81 ,Set/Clear Active Bit 81" "Not active,Active" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRACTIVE80 ,Set/Clear Active Bit 80" "Not active,Active" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRACTIVE79 ,Set/Clear Active Bit 79" "Not active,Active" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRACTIVE78 ,Set/Clear Active Bit 78" "Not active,Active" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRACTIVE77 ,Set/Clear Active Bit 77" "Not active,Active" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRACTIVE76 ,Set/Clear Active Bit 76" "Not active,Active" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRACTIVE75 ,Set/Clear Active Bit 75" "Not active,Active" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRACTIVE74 ,Set/Clear Active Bit 74" "Not active,Active" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRACTIVE73 ,Set/Clear Active Bit 73" "Not active,Active" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRACTIVE72 ,Set/Clear Active Bit 72" "Not active,Active" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRACTIVE71 ,Set/Clear Active Bit 71" "Not active,Active" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRACTIVE70 ,Set/Clear Active Bit 70" "Not active,Active" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRACTIVE69 ,Set/Clear Active Bit 69" "Not active,Active" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRACTIVE68 ,Set/Clear Active Bit 68" "Not active,Active" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRACTIVE67 ,Set/Clear Active Bit 67" "Not active,Active" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRACTIVE66 ,Set/Clear Active Bit 66" "Not active,Active" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRACTIVE65 ,Set/Clear Active Bit 65" "Not active,Active" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRACTIVE64 ,Set/Clear Active Bit 64" "Not active,Active" else rgroup.long 0x0308++0x03 line.long 0x0 "GICD_SET/CLR_ACTIVER2,Interrupt Set/Clear Active Register 2" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(ad:(per.long(spr:0x31F30)&0xFFFC0000)+0x04))&0x0000001F)>=0x03) group.long 0x030C++0x03 line.long 0x0 "GICD_SET/CLR_ACTIVER3,Interrupt Set/Clear Active Register 3" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRACTIVE127 ,Set/Clear Active Bit 127" "Not active,Active" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRACTIVE126 ,Set/Clear Active Bit 126" "Not active,Active" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRACTIVE125 ,Set/Clear Active Bit 125" "Not active,Active" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRACTIVE124 ,Set/Clear Active Bit 124" "Not active,Active" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRACTIVE123 ,Set/Clear Active Bit 123" "Not active,Active" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRACTIVE122 ,Set/Clear Active Bit 122" "Not active,Active" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRACTIVE121 ,Set/Clear Active Bit 121" "Not active,Active" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRACTIVE120 ,Set/Clear Active Bit 120" "Not active,Active" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRACTIVE119 ,Set/Clear Active Bit 119" "Not active,Active" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRACTIVE118 ,Set/Clear Active Bit 118" "Not active,Active" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRACTIVE117 ,Set/Clear Active Bit 117" "Not active,Active" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRACTIVE116 ,Set/Clear Active Bit 116" "Not active,Active" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRACTIVE115 ,Set/Clear Active Bit 115" "Not active,Active" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRACTIVE114 ,Set/Clear Active Bit 114" "Not active,Active" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRACTIVE113 ,Set/Clear Active Bit 113" "Not active,Active" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRACTIVE112 ,Set/Clear Active Bit 112" "Not active,Active" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRACTIVE111 ,Set/Clear Active Bit 111" "Not active,Active" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRACTIVE110 ,Set/Clear Active Bit 110" "Not active,Active" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRACTIVE109 ,Set/Clear Active Bit 109" "Not active,Active" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRACTIVE108 ,Set/Clear Active Bit 108" "Not active,Active" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRACTIVE107 ,Set/Clear Active Bit 107" "Not active,Active" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRACTIVE106 ,Set/Clear Active Bit 106" "Not active,Active" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRACTIVE105 ,Set/Clear Active Bit 105" "Not active,Active" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRACTIVE104 ,Set/Clear Active Bit 104" "Not active,Active" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRACTIVE103 ,Set/Clear Active Bit 103" "Not active,Active" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRACTIVE102 ,Set/Clear Active Bit 102" "Not active,Active" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRACTIVE101 ,Set/Clear Active Bit 101" "Not active,Active" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRACTIVE100 ,Set/Clear Active Bit 100" "Not active,Active" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRACTIVE99 ,Set/Clear Active Bit 99" "Not active,Active" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRACTIVE98 ,Set/Clear Active Bit 98" "Not active,Active" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRACTIVE97 ,Set/Clear Active Bit 97" "Not active,Active" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRACTIVE96 ,Set/Clear Active Bit 96" "Not active,Active" else rgroup.long 0x030C++0x03 line.long 0x0 "GICD_SET/CLR_ACTIVER3,Interrupt Set/Clear Active Register 3" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(ad:(per.long(spr:0x31F30)&0xFFFC0000)+0x04))&0x0000001F)>=0x04) group.long 0x0310++0x03 line.long 0x0 "GICD_SET/CLR_ACTIVER4,Interrupt Set/Clear Active Register 4" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRACTIVE159 ,Set/Clear Active Bit 159" "Not active,Active" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRACTIVE158 ,Set/Clear Active Bit 158" "Not active,Active" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRACTIVE157 ,Set/Clear Active Bit 157" "Not active,Active" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRACTIVE156 ,Set/Clear Active Bit 156" "Not active,Active" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRACTIVE155 ,Set/Clear Active Bit 155" "Not active,Active" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRACTIVE154 ,Set/Clear Active Bit 154" "Not active,Active" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRACTIVE153 ,Set/Clear Active Bit 153" "Not active,Active" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRACTIVE152 ,Set/Clear Active Bit 152" "Not active,Active" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRACTIVE151 ,Set/Clear Active Bit 151" "Not active,Active" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRACTIVE150 ,Set/Clear Active Bit 150" "Not active,Active" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRACTIVE149 ,Set/Clear Active Bit 149" "Not active,Active" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRACTIVE148 ,Set/Clear Active Bit 148" "Not active,Active" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRACTIVE147 ,Set/Clear Active Bit 147" "Not active,Active" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRACTIVE146 ,Set/Clear Active Bit 146" "Not active,Active" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRACTIVE145 ,Set/Clear Active Bit 145" "Not active,Active" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRACTIVE144 ,Set/Clear Active Bit 144" "Not active,Active" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRACTIVE143 ,Set/Clear Active Bit 143" "Not active,Active" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRACTIVE142 ,Set/Clear Active Bit 142" "Not active,Active" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRACTIVE141 ,Set/Clear Active Bit 141" "Not active,Active" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRACTIVE140 ,Set/Clear Active Bit 140" "Not active,Active" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRACTIVE139 ,Set/Clear Active Bit 139" "Not active,Active" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRACTIVE138 ,Set/Clear Active Bit 138" "Not active,Active" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRACTIVE137 ,Set/Clear Active Bit 137" "Not active,Active" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRACTIVE136 ,Set/Clear Active Bit 136" "Not active,Active" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRACTIVE135 ,Set/Clear Active Bit 135" "Not active,Active" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRACTIVE134 ,Set/Clear Active Bit 134" "Not active,Active" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRACTIVE133 ,Set/Clear Active Bit 133" "Not active,Active" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRACTIVE132 ,Set/Clear Active Bit 132" "Not active,Active" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRACTIVE131 ,Set/Clear Active Bit 131" "Not active,Active" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRACTIVE130 ,Set/Clear Active Bit 130" "Not active,Active" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRACTIVE129 ,Set/Clear Active Bit 129" "Not active,Active" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRACTIVE128 ,Set/Clear Active Bit 128" "Not active,Active" else rgroup.long 0x0310++0x03 line.long 0x0 "GICD_SET/CLR_ACTIVER4,Interrupt Set/Clear Active Register 4" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(ad:(per.long(spr:0x31F30)&0xFFFC0000)+0x04))&0x0000001F)>=0x05) group.long 0x0314++0x03 line.long 0x0 "GICD_SET/CLR_ACTIVER5,Interrupt Set/Clear Active Register 5" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRACTIVE191 ,Set/Clear Active Bit 191" "Not active,Active" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRACTIVE190 ,Set/Clear Active Bit 190" "Not active,Active" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRACTIVE189 ,Set/Clear Active Bit 189" "Not active,Active" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRACTIVE188 ,Set/Clear Active Bit 188" "Not active,Active" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRACTIVE187 ,Set/Clear Active Bit 187" "Not active,Active" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRACTIVE186 ,Set/Clear Active Bit 186" "Not active,Active" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRACTIVE185 ,Set/Clear Active Bit 185" "Not active,Active" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRACTIVE184 ,Set/Clear Active Bit 184" "Not active,Active" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRACTIVE183 ,Set/Clear Active Bit 183" "Not active,Active" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRACTIVE182 ,Set/Clear Active Bit 182" "Not active,Active" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRACTIVE181 ,Set/Clear Active Bit 181" "Not active,Active" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRACTIVE180 ,Set/Clear Active Bit 180" "Not active,Active" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRACTIVE179 ,Set/Clear Active Bit 179" "Not active,Active" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRACTIVE178 ,Set/Clear Active Bit 178" "Not active,Active" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRACTIVE177 ,Set/Clear Active Bit 177" "Not active,Active" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRACTIVE176 ,Set/Clear Active Bit 176" "Not active,Active" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRACTIVE175 ,Set/Clear Active Bit 175" "Not active,Active" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRACTIVE174 ,Set/Clear Active Bit 174" "Not active,Active" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRACTIVE173 ,Set/Clear Active Bit 173" "Not active,Active" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRACTIVE172 ,Set/Clear Active Bit 172" "Not active,Active" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRACTIVE171 ,Set/Clear Active Bit 171" "Not active,Active" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRACTIVE170 ,Set/Clear Active Bit 170" "Not active,Active" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRACTIVE169 ,Set/Clear Active Bit 169" "Not active,Active" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRACTIVE168 ,Set/Clear Active Bit 168" "Not active,Active" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRACTIVE167 ,Set/Clear Active Bit 167" "Not active,Active" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRACTIVE166 ,Set/Clear Active Bit 166" "Not active,Active" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRACTIVE165 ,Set/Clear Active Bit 165" "Not active,Active" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRACTIVE164 ,Set/Clear Active Bit 164" "Not active,Active" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRACTIVE163 ,Set/Clear Active Bit 163" "Not active,Active" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRACTIVE162 ,Set/Clear Active Bit 162" "Not active,Active" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRACTIVE161 ,Set/Clear Active Bit 161" "Not active,Active" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRACTIVE160 ,Set/Clear Active Bit 160" "Not active,Active" else rgroup.long 0x0314++0x03 line.long 0x0 "GICD_SET/CLR_ACTIVER5,Interrupt Set/Clear Active Register 5" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(ad:(per.long(spr:0x31F30)&0xFFFC0000)+0x04))&0x0000001F)>=0x06) group.long 0x0318++0x03 line.long 0x0 "GICD_SET/CLR_ACTIVER6,Interrupt Set/Clear Active Register 6" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRACTIVE223 ,Set/Clear Active Bit 223" "Not active,Active" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRACTIVE222 ,Set/Clear Active Bit 222" "Not active,Active" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRACTIVE221 ,Set/Clear Active Bit 221" "Not active,Active" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRACTIVE220 ,Set/Clear Active Bit 220" "Not active,Active" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRACTIVE219 ,Set/Clear Active Bit 219" "Not active,Active" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRACTIVE218 ,Set/Clear Active Bit 218" "Not active,Active" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRACTIVE217 ,Set/Clear Active Bit 217" "Not active,Active" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRACTIVE216 ,Set/Clear Active Bit 216" "Not active,Active" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRACTIVE215 ,Set/Clear Active Bit 215" "Not active,Active" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRACTIVE214 ,Set/Clear Active Bit 214" "Not active,Active" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRACTIVE213 ,Set/Clear Active Bit 213" "Not active,Active" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRACTIVE212 ,Set/Clear Active Bit 212" "Not active,Active" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRACTIVE211 ,Set/Clear Active Bit 211" "Not active,Active" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRACTIVE210 ,Set/Clear Active Bit 210" "Not active,Active" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRACTIVE209 ,Set/Clear Active Bit 209" "Not active,Active" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRACTIVE208 ,Set/Clear Active Bit 208" "Not active,Active" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRACTIVE207 ,Set/Clear Active Bit 207" "Not active,Active" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRACTIVE206 ,Set/Clear Active Bit 206" "Not active,Active" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRACTIVE205 ,Set/Clear Active Bit 205" "Not active,Active" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRACTIVE204 ,Set/Clear Active Bit 204" "Not active,Active" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRACTIVE203 ,Set/Clear Active Bit 203" "Not active,Active" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRACTIVE202 ,Set/Clear Active Bit 202" "Not active,Active" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRACTIVE201 ,Set/Clear Active Bit 201" "Not active,Active" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRACTIVE200 ,Set/Clear Active Bit 200" "Not active,Active" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRACTIVE199 ,Set/Clear Active Bit 199" "Not active,Active" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRACTIVE198 ,Set/Clear Active Bit 198" "Not active,Active" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRACTIVE197 ,Set/Clear Active Bit 197" "Not active,Active" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRACTIVE196 ,Set/Clear Active Bit 196" "Not active,Active" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRACTIVE195 ,Set/Clear Active Bit 195" "Not active,Active" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRACTIVE194 ,Set/Clear Active Bit 194" "Not active,Active" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRACTIVE193 ,Set/Clear Active Bit 193" "Not active,Active" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRACTIVE192 ,Set/Clear Active Bit 192" "Not active,Active" else rgroup.long 0x0318++0x03 line.long 0x0 "GICD_SET/CLR_ACTIVER6,Interrupt Set/Clear Active Register 6" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(ad:(per.long(spr:0x31F30)&0xFFFC0000)+0x04))&0x0000001F)>=0x07) group.long 0x031C++0x03 line.long 0x0 "GICD_SET/CLR_ACTIVER7,Interrupt Set/Clear Active Register 7" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRACTIVE255 ,Set/Clear Active Bit 255" "Not active,Active" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRACTIVE254 ,Set/Clear Active Bit 254" "Not active,Active" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRACTIVE253 ,Set/Clear Active Bit 253" "Not active,Active" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRACTIVE252 ,Set/Clear Active Bit 252" "Not active,Active" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRACTIVE251 ,Set/Clear Active Bit 251" "Not active,Active" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRACTIVE250 ,Set/Clear Active Bit 250" "Not active,Active" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRACTIVE249 ,Set/Clear Active Bit 249" "Not active,Active" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRACTIVE248 ,Set/Clear Active Bit 248" "Not active,Active" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRACTIVE247 ,Set/Clear Active Bit 247" "Not active,Active" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRACTIVE246 ,Set/Clear Active Bit 246" "Not active,Active" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRACTIVE245 ,Set/Clear Active Bit 245" "Not active,Active" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRACTIVE244 ,Set/Clear Active Bit 244" "Not active,Active" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRACTIVE243 ,Set/Clear Active Bit 243" "Not active,Active" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRACTIVE242 ,Set/Clear Active Bit 242" "Not active,Active" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRACTIVE241 ,Set/Clear Active Bit 241" "Not active,Active" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRACTIVE240 ,Set/Clear Active Bit 240" "Not active,Active" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRACTIVE239 ,Set/Clear Active Bit 239" "Not active,Active" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRACTIVE238 ,Set/Clear Active Bit 238" "Not active,Active" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRACTIVE237 ,Set/Clear Active Bit 237" "Not active,Active" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRACTIVE236 ,Set/Clear Active Bit 236" "Not active,Active" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRACTIVE235 ,Set/Clear Active Bit 235" "Not active,Active" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRACTIVE234 ,Set/Clear Active Bit 234" "Not active,Active" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRACTIVE233 ,Set/Clear Active Bit 233" "Not active,Active" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRACTIVE232 ,Set/Clear Active Bit 232" "Not active,Active" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRACTIVE231 ,Set/Clear Active Bit 231" "Not active,Active" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRACTIVE230 ,Set/Clear Active Bit 230" "Not active,Active" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRACTIVE229 ,Set/Clear Active Bit 229" "Not active,Active" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRACTIVE228 ,Set/Clear Active Bit 228" "Not active,Active" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRACTIVE227 ,Set/Clear Active Bit 227" "Not active,Active" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRACTIVE226 ,Set/Clear Active Bit 226" "Not active,Active" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRACTIVE225 ,Set/Clear Active Bit 225" "Not active,Active" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRACTIVE224 ,Set/Clear Active Bit 224" "Not active,Active" else rgroup.long 0x031C++0x03 line.long 0x0 "GICD_SET/CLR_ACTIVER7,Interrupt Set/Clear Active Register 7" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(ad:(per.long(spr:0x31F30)&0xFFFC0000)+0x04))&0x0000001F)>=0x08) group.long 0x0320++0x03 line.long 0x0 "GICD_SET/CLR_ACTIVER8,Interrupt Set/Clear Active Register 8" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRACTIVE287 ,Set/Clear Active Bit 287" "Not active,Active" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRACTIVE286 ,Set/Clear Active Bit 286" "Not active,Active" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRACTIVE285 ,Set/Clear Active Bit 285" "Not active,Active" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRACTIVE284 ,Set/Clear Active Bit 284" "Not active,Active" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRACTIVE283 ,Set/Clear Active Bit 283" "Not active,Active" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRACTIVE282 ,Set/Clear Active Bit 282" "Not active,Active" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRACTIVE281 ,Set/Clear Active Bit 281" "Not active,Active" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRACTIVE280 ,Set/Clear Active Bit 280" "Not active,Active" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRACTIVE279 ,Set/Clear Active Bit 279" "Not active,Active" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRACTIVE278 ,Set/Clear Active Bit 278" "Not active,Active" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRACTIVE277 ,Set/Clear Active Bit 277" "Not active,Active" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRACTIVE276 ,Set/Clear Active Bit 276" "Not active,Active" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRACTIVE275 ,Set/Clear Active Bit 275" "Not active,Active" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRACTIVE274 ,Set/Clear Active Bit 274" "Not active,Active" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRACTIVE273 ,Set/Clear Active Bit 273" "Not active,Active" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRACTIVE272 ,Set/Clear Active Bit 272" "Not active,Active" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRACTIVE271 ,Set/Clear Active Bit 271" "Not active,Active" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRACTIVE270 ,Set/Clear Active Bit 270" "Not active,Active" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRACTIVE269 ,Set/Clear Active Bit 269" "Not active,Active" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRACTIVE268 ,Set/Clear Active Bit 268" "Not active,Active" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRACTIVE267 ,Set/Clear Active Bit 267" "Not active,Active" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRACTIVE266 ,Set/Clear Active Bit 266" "Not active,Active" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRACTIVE265 ,Set/Clear Active Bit 265" "Not active,Active" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRACTIVE264 ,Set/Clear Active Bit 264" "Not active,Active" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRACTIVE263 ,Set/Clear Active Bit 263" "Not active,Active" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRACTIVE262 ,Set/Clear Active Bit 262" "Not active,Active" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRACTIVE261 ,Set/Clear Active Bit 261" "Not active,Active" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRACTIVE260 ,Set/Clear Active Bit 260" "Not active,Active" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRACTIVE259 ,Set/Clear Active Bit 259" "Not active,Active" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRACTIVE258 ,Set/Clear Active Bit 258" "Not active,Active" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRACTIVE257 ,Set/Clear Active Bit 257" "Not active,Active" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRACTIVE256 ,Set/Clear Active Bit 256" "Not active,Active" else rgroup.long 0x0320++0x03 line.long 0x0 "GICD_SET/CLR_ACTIVER8,Interrupt Set/Clear Active Register 8" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(ad:(per.long(spr:0x31F30)&0xFFFC0000)+0x04))&0x0000001F)>=0x09) group.long 0x0324++0x03 line.long 0x0 "GICD_SET/CLR_ACTIVER9,Interrupt Set/Clear Active Register 9" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRACTIVE319 ,Set/Clear Active Bit 319" "Not active,Active" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRACTIVE318 ,Set/Clear Active Bit 318" "Not active,Active" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRACTIVE317 ,Set/Clear Active Bit 317" "Not active,Active" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRACTIVE316 ,Set/Clear Active Bit 316" "Not active,Active" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRACTIVE315 ,Set/Clear Active Bit 315" "Not active,Active" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRACTIVE314 ,Set/Clear Active Bit 314" "Not active,Active" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRACTIVE313 ,Set/Clear Active Bit 313" "Not active,Active" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRACTIVE312 ,Set/Clear Active Bit 312" "Not active,Active" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRACTIVE311 ,Set/Clear Active Bit 311" "Not active,Active" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRACTIVE310 ,Set/Clear Active Bit 310" "Not active,Active" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRACTIVE309 ,Set/Clear Active Bit 309" "Not active,Active" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRACTIVE308 ,Set/Clear Active Bit 308" "Not active,Active" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRACTIVE307 ,Set/Clear Active Bit 307" "Not active,Active" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRACTIVE306 ,Set/Clear Active Bit 306" "Not active,Active" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRACTIVE305 ,Set/Clear Active Bit 305" "Not active,Active" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRACTIVE304 ,Set/Clear Active Bit 304" "Not active,Active" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRACTIVE303 ,Set/Clear Active Bit 303" "Not active,Active" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRACTIVE302 ,Set/Clear Active Bit 302" "Not active,Active" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRACTIVE301 ,Set/Clear Active Bit 301" "Not active,Active" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRACTIVE300 ,Set/Clear Active Bit 300" "Not active,Active" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRACTIVE299 ,Set/Clear Active Bit 299" "Not active,Active" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRACTIVE298 ,Set/Clear Active Bit 298" "Not active,Active" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRACTIVE297 ,Set/Clear Active Bit 297" "Not active,Active" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRACTIVE296 ,Set/Clear Active Bit 296" "Not active,Active" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRACTIVE295 ,Set/Clear Active Bit 295" "Not active,Active" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRACTIVE294 ,Set/Clear Active Bit 294" "Not active,Active" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRACTIVE293 ,Set/Clear Active Bit 293" "Not active,Active" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRACTIVE292 ,Set/Clear Active Bit 292" "Not active,Active" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRACTIVE291 ,Set/Clear Active Bit 291" "Not active,Active" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRACTIVE290 ,Set/Clear Active Bit 290" "Not active,Active" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRACTIVE289 ,Set/Clear Active Bit 289" "Not active,Active" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRACTIVE288 ,Set/Clear Active Bit 288" "Not active,Active" else rgroup.long 0x0324++0x03 line.long 0x0 "GICD_SET/CLR_ACTIVER9,Interrupt Set/Clear Active Register 9" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(ad:(per.long(spr:0x31F30)&0xFFFC0000)+0x04))&0x0000001F)>=0x0A) group.long 0x0328++0x03 line.long 0x0 "GICD_SET/CLR_ACTIVER10,Interrupt Set/Clear Active Register 10" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRACTIVE351 ,Set/Clear Active Bit 351" "Not active,Active" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRACTIVE350 ,Set/Clear Active Bit 350" "Not active,Active" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRACTIVE349 ,Set/Clear Active Bit 349" "Not active,Active" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRACTIVE348 ,Set/Clear Active Bit 348" "Not active,Active" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRACTIVE347 ,Set/Clear Active Bit 347" "Not active,Active" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRACTIVE346 ,Set/Clear Active Bit 346" "Not active,Active" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRACTIVE345 ,Set/Clear Active Bit 345" "Not active,Active" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRACTIVE344 ,Set/Clear Active Bit 344" "Not active,Active" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRACTIVE343 ,Set/Clear Active Bit 343" "Not active,Active" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRACTIVE342 ,Set/Clear Active Bit 342" "Not active,Active" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRACTIVE341 ,Set/Clear Active Bit 341" "Not active,Active" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRACTIVE340 ,Set/Clear Active Bit 340" "Not active,Active" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRACTIVE339 ,Set/Clear Active Bit 339" "Not active,Active" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRACTIVE338 ,Set/Clear Active Bit 338" "Not active,Active" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRACTIVE337 ,Set/Clear Active Bit 337" "Not active,Active" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRACTIVE336 ,Set/Clear Active Bit 336" "Not active,Active" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRACTIVE335 ,Set/Clear Active Bit 335" "Not active,Active" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRACTIVE334 ,Set/Clear Active Bit 334" "Not active,Active" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRACTIVE333 ,Set/Clear Active Bit 333" "Not active,Active" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRACTIVE332 ,Set/Clear Active Bit 332" "Not active,Active" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRACTIVE331 ,Set/Clear Active Bit 331" "Not active,Active" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRACTIVE330 ,Set/Clear Active Bit 330" "Not active,Active" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRACTIVE329 ,Set/Clear Active Bit 329" "Not active,Active" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRACTIVE328 ,Set/Clear Active Bit 328" "Not active,Active" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRACTIVE327 ,Set/Clear Active Bit 327" "Not active,Active" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRACTIVE326 ,Set/Clear Active Bit 326" "Not active,Active" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRACTIVE325 ,Set/Clear Active Bit 325" "Not active,Active" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRACTIVE324 ,Set/Clear Active Bit 324" "Not active,Active" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRACTIVE323 ,Set/Clear Active Bit 323" "Not active,Active" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRACTIVE322 ,Set/Clear Active Bit 322" "Not active,Active" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRACTIVE321 ,Set/Clear Active Bit 321" "Not active,Active" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRACTIVE320 ,Set/Clear Active Bit 320" "Not active,Active" else rgroup.long 0x0328++0x03 line.long 0x0 "GICD_SET/CLR_ACTIVER10,Interrupt Set/Clear Active Register 10" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(ad:(per.long(spr:0x31F30)&0xFFFC0000)+0x04))&0x0000001F)>=0x0B) group.long 0x032C++0x03 line.long 0x0 "GICD_SET/CLR_ACTIVER11,Interrupt Set/Clear Active Register 11" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRACTIVE383 ,Set/Clear Active Bit 383" "Not active,Active" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRACTIVE382 ,Set/Clear Active Bit 382" "Not active,Active" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRACTIVE381 ,Set/Clear Active Bit 381" "Not active,Active" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRACTIVE380 ,Set/Clear Active Bit 380" "Not active,Active" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRACTIVE379 ,Set/Clear Active Bit 379" "Not active,Active" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRACTIVE378 ,Set/Clear Active Bit 378" "Not active,Active" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRACTIVE377 ,Set/Clear Active Bit 377" "Not active,Active" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRACTIVE376 ,Set/Clear Active Bit 376" "Not active,Active" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRACTIVE375 ,Set/Clear Active Bit 375" "Not active,Active" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRACTIVE374 ,Set/Clear Active Bit 374" "Not active,Active" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRACTIVE373 ,Set/Clear Active Bit 373" "Not active,Active" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRACTIVE372 ,Set/Clear Active Bit 372" "Not active,Active" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRACTIVE371 ,Set/Clear Active Bit 371" "Not active,Active" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRACTIVE370 ,Set/Clear Active Bit 370" "Not active,Active" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRACTIVE369 ,Set/Clear Active Bit 369" "Not active,Active" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRACTIVE368 ,Set/Clear Active Bit 368" "Not active,Active" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRACTIVE367 ,Set/Clear Active Bit 367" "Not active,Active" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRACTIVE366 ,Set/Clear Active Bit 366" "Not active,Active" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRACTIVE365 ,Set/Clear Active Bit 365" "Not active,Active" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRACTIVE364 ,Set/Clear Active Bit 364" "Not active,Active" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRACTIVE363 ,Set/Clear Active Bit 363" "Not active,Active" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRACTIVE362 ,Set/Clear Active Bit 362" "Not active,Active" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRACTIVE361 ,Set/Clear Active Bit 361" "Not active,Active" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRACTIVE360 ,Set/Clear Active Bit 360" "Not active,Active" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRACTIVE359 ,Set/Clear Active Bit 359" "Not active,Active" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRACTIVE358 ,Set/Clear Active Bit 358" "Not active,Active" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRACTIVE357 ,Set/Clear Active Bit 357" "Not active,Active" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRACTIVE356 ,Set/Clear Active Bit 356" "Not active,Active" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRACTIVE355 ,Set/Clear Active Bit 355" "Not active,Active" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRACTIVE354 ,Set/Clear Active Bit 354" "Not active,Active" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRACTIVE353 ,Set/Clear Active Bit 353" "Not active,Active" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRACTIVE352 ,Set/Clear Active Bit 352" "Not active,Active" else rgroup.long 0x032C++0x03 line.long 0x0 "GICD_SET/CLR_ACTIVER11,Interrupt Set/Clear Active Register 11" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(ad:(per.long(spr:0x31F30)&0xFFFC0000)+0x04))&0x0000001F)>=0x0C) group.long 0x0330++0x03 line.long 0x0 "GICD_SET/CLR_ACTIVER12,Interrupt Set/Clear Active Register 12" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRACTIVE415 ,Set/Clear Active Bit 415" "Not active,Active" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRACTIVE414 ,Set/Clear Active Bit 414" "Not active,Active" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRACTIVE413 ,Set/Clear Active Bit 413" "Not active,Active" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRACTIVE412 ,Set/Clear Active Bit 412" "Not active,Active" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRACTIVE411 ,Set/Clear Active Bit 411" "Not active,Active" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRACTIVE410 ,Set/Clear Active Bit 410" "Not active,Active" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRACTIVE409 ,Set/Clear Active Bit 409" "Not active,Active" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRACTIVE408 ,Set/Clear Active Bit 408" "Not active,Active" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRACTIVE407 ,Set/Clear Active Bit 407" "Not active,Active" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRACTIVE406 ,Set/Clear Active Bit 406" "Not active,Active" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRACTIVE405 ,Set/Clear Active Bit 405" "Not active,Active" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRACTIVE404 ,Set/Clear Active Bit 404" "Not active,Active" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRACTIVE403 ,Set/Clear Active Bit 403" "Not active,Active" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRACTIVE402 ,Set/Clear Active Bit 402" "Not active,Active" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRACTIVE401 ,Set/Clear Active Bit 401" "Not active,Active" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRACTIVE400 ,Set/Clear Active Bit 400" "Not active,Active" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRACTIVE399 ,Set/Clear Active Bit 399" "Not active,Active" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRACTIVE398 ,Set/Clear Active Bit 398" "Not active,Active" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRACTIVE397 ,Set/Clear Active Bit 397" "Not active,Active" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRACTIVE396 ,Set/Clear Active Bit 396" "Not active,Active" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRACTIVE395 ,Set/Clear Active Bit 395" "Not active,Active" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRACTIVE394 ,Set/Clear Active Bit 394" "Not active,Active" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRACTIVE393 ,Set/Clear Active Bit 393" "Not active,Active" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRACTIVE392 ,Set/Clear Active Bit 392" "Not active,Active" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRACTIVE391 ,Set/Clear Active Bit 391" "Not active,Active" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRACTIVE390 ,Set/Clear Active Bit 390" "Not active,Active" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRACTIVE389 ,Set/Clear Active Bit 389" "Not active,Active" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRACTIVE388 ,Set/Clear Active Bit 388" "Not active,Active" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRACTIVE387 ,Set/Clear Active Bit 387" "Not active,Active" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRACTIVE386 ,Set/Clear Active Bit 386" "Not active,Active" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRACTIVE385 ,Set/Clear Active Bit 385" "Not active,Active" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRACTIVE384 ,Set/Clear Active Bit 384" "Not active,Active" else rgroup.long 0x0330++0x03 line.long 0x0 "GICD_SET/CLR_ACTIVER12,Interrupt Set/Clear Active Register 12" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(ad:(per.long(spr:0x31F30)&0xFFFC0000)+0x04))&0x0000001F)>=0x0D) group.long 0x0334++0x03 line.long 0x0 "GICD_SET/CLR_ACTIVER13,Interrupt Set/Clear Active Register 13" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRACTIVE447 ,Set/Clear Active Bit 447" "Not active,Active" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRACTIVE446 ,Set/Clear Active Bit 446" "Not active,Active" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRACTIVE445 ,Set/Clear Active Bit 445" "Not active,Active" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRACTIVE444 ,Set/Clear Active Bit 444" "Not active,Active" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRACTIVE443 ,Set/Clear Active Bit 443" "Not active,Active" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRACTIVE442 ,Set/Clear Active Bit 442" "Not active,Active" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRACTIVE441 ,Set/Clear Active Bit 441" "Not active,Active" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRACTIVE440 ,Set/Clear Active Bit 440" "Not active,Active" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRACTIVE439 ,Set/Clear Active Bit 439" "Not active,Active" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRACTIVE438 ,Set/Clear Active Bit 438" "Not active,Active" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRACTIVE437 ,Set/Clear Active Bit 437" "Not active,Active" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRACTIVE436 ,Set/Clear Active Bit 436" "Not active,Active" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRACTIVE435 ,Set/Clear Active Bit 435" "Not active,Active" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRACTIVE434 ,Set/Clear Active Bit 434" "Not active,Active" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRACTIVE433 ,Set/Clear Active Bit 433" "Not active,Active" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRACTIVE432 ,Set/Clear Active Bit 432" "Not active,Active" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRACTIVE431 ,Set/Clear Active Bit 431" "Not active,Active" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRACTIVE430 ,Set/Clear Active Bit 430" "Not active,Active" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRACTIVE429 ,Set/Clear Active Bit 429" "Not active,Active" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRACTIVE428 ,Set/Clear Active Bit 428" "Not active,Active" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRACTIVE427 ,Set/Clear Active Bit 427" "Not active,Active" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRACTIVE426 ,Set/Clear Active Bit 426" "Not active,Active" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRACTIVE425 ,Set/Clear Active Bit 425" "Not active,Active" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRACTIVE424 ,Set/Clear Active Bit 424" "Not active,Active" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRACTIVE423 ,Set/Clear Active Bit 423" "Not active,Active" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRACTIVE422 ,Set/Clear Active Bit 422" "Not active,Active" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRACTIVE421 ,Set/Clear Active Bit 421" "Not active,Active" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRACTIVE420 ,Set/Clear Active Bit 420" "Not active,Active" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRACTIVE419 ,Set/Clear Active Bit 419" "Not active,Active" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRACTIVE418 ,Set/Clear Active Bit 418" "Not active,Active" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRACTIVE417 ,Set/Clear Active Bit 417" "Not active,Active" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRACTIVE416 ,Set/Clear Active Bit 416" "Not active,Active" else rgroup.long 0x0334++0x03 line.long 0x0 "GICD_SET/CLR_ACTIVER13,Interrupt Set/Clear Active Register 13" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(ad:(per.long(spr:0x31F30)&0xFFFC0000)+0x04))&0x0000001F)>=0x0E) group.long 0x0338++0x03 line.long 0x0 "GICD_SET/CLR_ACTIVER14,Interrupt Set/Clear Active Register 14" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRACTIVE479 ,Set/Clear Active Bit 479" "Not active,Active" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRACTIVE478 ,Set/Clear Active Bit 478" "Not active,Active" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRACTIVE477 ,Set/Clear Active Bit 477" "Not active,Active" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRACTIVE476 ,Set/Clear Active Bit 476" "Not active,Active" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRACTIVE475 ,Set/Clear Active Bit 475" "Not active,Active" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRACTIVE474 ,Set/Clear Active Bit 474" "Not active,Active" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRACTIVE473 ,Set/Clear Active Bit 473" "Not active,Active" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRACTIVE472 ,Set/Clear Active Bit 472" "Not active,Active" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRACTIVE471 ,Set/Clear Active Bit 471" "Not active,Active" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRACTIVE470 ,Set/Clear Active Bit 470" "Not active,Active" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRACTIVE469 ,Set/Clear Active Bit 469" "Not active,Active" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRACTIVE468 ,Set/Clear Active Bit 468" "Not active,Active" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRACTIVE467 ,Set/Clear Active Bit 467" "Not active,Active" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRACTIVE466 ,Set/Clear Active Bit 466" "Not active,Active" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRACTIVE465 ,Set/Clear Active Bit 465" "Not active,Active" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRACTIVE464 ,Set/Clear Active Bit 464" "Not active,Active" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRACTIVE463 ,Set/Clear Active Bit 463" "Not active,Active" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRACTIVE462 ,Set/Clear Active Bit 462" "Not active,Active" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRACTIVE461 ,Set/Clear Active Bit 461" "Not active,Active" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRACTIVE460 ,Set/Clear Active Bit 460" "Not active,Active" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRACTIVE459 ,Set/Clear Active Bit 459" "Not active,Active" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRACTIVE458 ,Set/Clear Active Bit 458" "Not active,Active" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRACTIVE457 ,Set/Clear Active Bit 457" "Not active,Active" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRACTIVE456 ,Set/Clear Active Bit 456" "Not active,Active" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRACTIVE455 ,Set/Clear Active Bit 455" "Not active,Active" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRACTIVE454 ,Set/Clear Active Bit 454" "Not active,Active" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRACTIVE453 ,Set/Clear Active Bit 453" "Not active,Active" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRACTIVE452 ,Set/Clear Active Bit 452" "Not active,Active" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRACTIVE451 ,Set/Clear Active Bit 451" "Not active,Active" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRACTIVE450 ,Set/Clear Active Bit 450" "Not active,Active" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRACTIVE449 ,Set/Clear Active Bit 449" "Not active,Active" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRACTIVE448 ,Set/Clear Active Bit 448" "Not active,Active" else rgroup.long 0x0338++0x03 line.long 0x0 "GICD_SET/CLR_ACTIVER14,Interrupt Set/Clear Active Register 14" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(ad:(per.long(spr:0x31F30)&0xFFFC0000)+0x04))&0x0000001F)>=0x0F) group.long 0x033C++0x03 line.long 0x0 "GICD_SET/CLR_ACTIVER15,Interrupt Set/Clear Active Register 15" setclrfld.long 0x00 31. 0x00 31. 0x80 31. " SET/CLRACTIVE511 ,Set/Clear Active Bit 511" "Not active,Active" setclrfld.long 0x00 30. 0x00 30. 0x80 30. " SET/CLRACTIVE510 ,Set/Clear Active Bit 510" "Not active,Active" setclrfld.long 0x00 29. 0x00 29. 0x80 29. " SET/CLRACTIVE509 ,Set/Clear Active Bit 509" "Not active,Active" textline " " setclrfld.long 0x00 28. 0x00 28. 0x80 28. " SET/CLRACTIVE508 ,Set/Clear Active Bit 508" "Not active,Active" setclrfld.long 0x00 27. 0x00 27. 0x80 27. " SET/CLRACTIVE507 ,Set/Clear Active Bit 507" "Not active,Active" setclrfld.long 0x00 26. 0x00 26. 0x80 26. " SET/CLRACTIVE506 ,Set/Clear Active Bit 506" "Not active,Active" textline " " setclrfld.long 0x00 25. 0x00 25. 0x80 25. " SET/CLRACTIVE505 ,Set/Clear Active Bit 505" "Not active,Active" setclrfld.long 0x00 24. 0x00 24. 0x80 24. " SET/CLRACTIVE504 ,Set/Clear Active Bit 504" "Not active,Active" setclrfld.long 0x00 23. 0x00 23. 0x80 23. " SET/CLRACTIVE503 ,Set/Clear Active Bit 503" "Not active,Active" textline " " setclrfld.long 0x00 22. 0x00 22. 0x80 22. " SET/CLRACTIVE502 ,Set/Clear Active Bit 502" "Not active,Active" setclrfld.long 0x00 21. 0x00 21. 0x80 21. " SET/CLRACTIVE501 ,Set/Clear Active Bit 501" "Not active,Active" setclrfld.long 0x00 20. 0x00 20. 0x80 20. " SET/CLRACTIVE500 ,Set/Clear Active Bit 500" "Not active,Active" textline " " setclrfld.long 0x00 19. 0x00 19. 0x80 19. " SET/CLRACTIVE499 ,Set/Clear Active Bit 499" "Not active,Active" setclrfld.long 0x00 18. 0x00 18. 0x80 18. " SET/CLRACTIVE498 ,Set/Clear Active Bit 498" "Not active,Active" setclrfld.long 0x00 17. 0x00 17. 0x80 17. " SET/CLRACTIVE497 ,Set/Clear Active Bit 497" "Not active,Active" textline " " setclrfld.long 0x00 16. 0x00 16. 0x80 16. " SET/CLRACTIVE496 ,Set/Clear Active Bit 496" "Not active,Active" setclrfld.long 0x00 15. 0x00 15. 0x80 15. " SET/CLRACTIVE495 ,Set/Clear Active Bit 495" "Not active,Active" setclrfld.long 0x00 14. 0x00 14. 0x80 14. " SET/CLRACTIVE494 ,Set/Clear Active Bit 494" "Not active,Active" textline " " setclrfld.long 0x00 13. 0x00 13. 0x80 13. " SET/CLRACTIVE493 ,Set/Clear Active Bit 493" "Not active,Active" setclrfld.long 0x00 12. 0x00 12. 0x80 12. " SET/CLRACTIVE492 ,Set/Clear Active Bit 492" "Not active,Active" setclrfld.long 0x00 11. 0x00 11. 0x80 11. " SET/CLRACTIVE491 ,Set/Clear Active Bit 491" "Not active,Active" textline " " setclrfld.long 0x00 10. 0x00 10. 0x80 10. " SET/CLRACTIVE490 ,Set/Clear Active Bit 490" "Not active,Active" setclrfld.long 0x00 9. 0x00 9. 0x80 9. " SET/CLRACTIVE489 ,Set/Clear Active Bit 489" "Not active,Active" setclrfld.long 0x00 8. 0x00 8. 0x80 8. " SET/CLRACTIVE488 ,Set/Clear Active Bit 488" "Not active,Active" textline " " setclrfld.long 0x00 7. 0x00 7. 0x80 7. " SET/CLRACTIVE487 ,Set/Clear Active Bit 487" "Not active,Active" setclrfld.long 0x00 6. 0x00 6. 0x80 6. " SET/CLRACTIVE486 ,Set/Clear Active Bit 486" "Not active,Active" setclrfld.long 0x00 5. 0x00 5. 0x80 5. " SET/CLRACTIVE485 ,Set/Clear Active Bit 485" "Not active,Active" textline " " setclrfld.long 0x00 4. 0x00 4. 0x80 4. " SET/CLRACTIVE484 ,Set/Clear Active Bit 484" "Not active,Active" setclrfld.long 0x00 3. 0x00 3. 0x80 3. " SET/CLRACTIVE483 ,Set/Clear Active Bit 483" "Not active,Active" setclrfld.long 0x00 2. 0x00 2. 0x80 2. " SET/CLRACTIVE482 ,Set/Clear Active Bit 482" "Not active,Active" textline " " setclrfld.long 0x00 1. 0x00 1. 0x80 1. " SET/CLRACTIVE481 ,Set/Clear Active Bit 481" "Not active,Active" setclrfld.long 0x00 0. 0x00 0. 0x80 0. " SET/CLRACTIVE480 ,Set/Clear Active Bit 480" "Not active,Active" else rgroup.long 0x033C++0x03 line.long 0x0 "GICD_SET/CLR_ACTIVER15,Interrupt Set/Clear Active Register 15" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif rgroup.long 0x0340++0x03 line.long 0x0 "GICD_SET/CLR_ACTIVER16,Interrupt Set/Clear Active Register 16" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " rgroup.long 0x0344++0x03 line.long 0x0 "GICD_SET/CLR_ACTIVER17,Interrupt Set/Clear Active Register 17" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " rgroup.long 0x0348++0x03 line.long 0x0 "GICD_SET/CLR_ACTIVER18,Interrupt Set/Clear Active Register 18" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " rgroup.long 0x034C++0x03 line.long 0x0 "GICD_SET/CLR_ACTIVER19,Interrupt Set/Clear Active Register 19" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " rgroup.long 0x0350++0x03 line.long 0x0 "GICD_SET/CLR_ACTIVER20,Interrupt Set/Clear Active Register 20" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " rgroup.long 0x0354++0x03 line.long 0x0 "GICD_SET/CLR_ACTIVER21,Interrupt Set/Clear Active Register 21" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " rgroup.long 0x0358++0x03 line.long 0x0 "GICD_SET/CLR_ACTIVER22,Interrupt Set/Clear Active Register 22" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " rgroup.long 0x035C++0x03 line.long 0x0 "GICD_SET/CLR_ACTIVER23,Interrupt Set/Clear Active Register 23" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " rgroup.long 0x0360++0x03 line.long 0x0 "GICD_SET/CLR_ACTIVER24,Interrupt Set/Clear Active Register 24" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " rgroup.long 0x0364++0x03 line.long 0x0 "GICD_SET/CLR_ACTIVER25,Interrupt Set/Clear Active Register 25" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " rgroup.long 0x0368++0x03 line.long 0x0 "GICD_SET/CLR_ACTIVER26,Interrupt Set/Clear Active Register 26" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " rgroup.long 0x036C++0x03 line.long 0x0 "GICD_SET/CLR_ACTIVER27,Interrupt Set/Clear Active Register 27" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " rgroup.long 0x0370++0x03 line.long 0x0 "GICD_SET/CLR_ACTIVER28,Interrupt Set/Clear Active Register 28" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " rgroup.long 0x0374++0x03 line.long 0x0 "GICD_SET/CLR_ACTIVER29,Interrupt Set/Clear Active Register 29" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " rgroup.long 0x0378++0x03 line.long 0x0 "GICD_SET/CLR_ACTIVER30,Interrupt Set/Clear Active Register 30" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " rgroup.long 0x037C++0x03 line.long 0x0 "GICD_SET/CLR_ACTIVER31,Interrupt Set/Clear Active Register 31" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif tree.end tree "Priority Registers" group.long 0x400++0x03 line.long 0x00 "GICD_IPRIORITYR0,Interrupt Priority Register 0" hexmask.long.byte 0x00 24.--31. 1. " INTID3 ,Interrupt ID3 Priority/Priority Byte Offset 3 " hexmask.long.byte 0x00 16.--23. 1. " INTID2 ,Interrupt ID2 Priority/Priority Byte Offset 2 " hexmask.long.byte 0x00 8.--15. 1. " INTID1 ,Interrupt ID1 Priority/Priority Byte Offset 1 " hexmask.long.byte 0x00 0.--7. 1. " INTID0 ,Interrupt ID0 Priority/Priority Byte Offset 0 " group.long 0x404++0x03 line.long 0x00 "GICD_IPRIORITYR1,Interrupt Priority Register 1" hexmask.long.byte 0x00 24.--31. 1. " INTID7 ,Interrupt ID7 Priority/Priority Byte Offset 7 " hexmask.long.byte 0x00 16.--23. 1. " INTID6 ,Interrupt ID6 Priority/Priority Byte Offset 6 " hexmask.long.byte 0x00 8.--15. 1. " INTID5 ,Interrupt ID5 Priority/Priority Byte Offset 5 " hexmask.long.byte 0x00 0.--7. 1. " INTID4 ,Interrupt ID4 Priority/Priority Byte Offset 4 " group.long 0x408++0x03 line.long 0x00 "GICD_IPRIORITYR2,Interrupt Priority Register 2" hexmask.long.byte 0x00 24.--31. 1. " INTID11 ,Interrupt ID11 Priority/Priority Byte Offset 11 " hexmask.long.byte 0x00 16.--23. 1. " INTID10 ,Interrupt ID10 Priority/Priority Byte Offset 10 " hexmask.long.byte 0x00 8.--15. 1. " INTID9 ,Interrupt ID9 Priority/Priority Byte Offset 9 " hexmask.long.byte 0x00 0.--7. 1. " INTID8 ,Interrupt ID8 Priority/Priority Byte Offset 8 " group.long 0x40C++0x03 line.long 0x00 "GICD_IPRIORITYR3,Interrupt Priority Register 3" hexmask.long.byte 0x00 24.--31. 1. " INTID15 ,Interrupt ID15 Priority/Priority Byte Offset 15 " hexmask.long.byte 0x00 16.--23. 1. " INTID14 ,Interrupt ID14 Priority/Priority Byte Offset 14 " hexmask.long.byte 0x00 8.--15. 1. " INTID13 ,Interrupt ID13 Priority/Priority Byte Offset 13 " hexmask.long.byte 0x00 0.--7. 1. " INTID12 ,Interrupt ID12 Priority/Priority Byte Offset 12 " group.long 0x410++0x03 line.long 0x00 "GICD_IPRIORITYR4,Interrupt Priority Register 4" hexmask.long.byte 0x00 24.--31. 1. " INTID19 ,Interrupt ID19 Priority/Priority Byte Offset 19 " hexmask.long.byte 0x00 16.--23. 1. " INTID18 ,Interrupt ID18 Priority/Priority Byte Offset 18 " hexmask.long.byte 0x00 8.--15. 1. " INTID17 ,Interrupt ID17 Priority/Priority Byte Offset 17 " hexmask.long.byte 0x00 0.--7. 1. " INTID16 ,Interrupt ID16 Priority/Priority Byte Offset 16 " group.long 0x414++0x03 line.long 0x00 "GICD_IPRIORITYR5,Interrupt Priority Register 5" hexmask.long.byte 0x00 24.--31. 1. " INTID23 ,Interrupt ID23 Priority/Priority Byte Offset 23 " hexmask.long.byte 0x00 16.--23. 1. " INTID22 ,Interrupt ID22 Priority/Priority Byte Offset 22 " hexmask.long.byte 0x00 8.--15. 1. " INTID21 ,Interrupt ID21 Priority/Priority Byte Offset 21 " hexmask.long.byte 0x00 0.--7. 1. " INTID20 ,Interrupt ID20 Priority/Priority Byte Offset 20 " group.long 0x418++0x03 line.long 0x00 "GICD_IPRIORITYR6,Interrupt Priority Register 6" hexmask.long.byte 0x00 24.--31. 1. " INTID27 ,Interrupt ID27 Priority/Priority Byte Offset 27 " hexmask.long.byte 0x00 16.--23. 1. " INTID26 ,Interrupt ID26 Priority/Priority Byte Offset 26 " hexmask.long.byte 0x00 8.--15. 1. " INTID25 ,Interrupt ID25 Priority/Priority Byte Offset 25 " hexmask.long.byte 0x00 0.--7. 1. " INTID24 ,Interrupt ID24 Priority/Priority Byte Offset 24 " group.long 0x41C++0x03 line.long 0x00 "GICD_IPRIORITYR7,Interrupt Priority Register 7" hexmask.long.byte 0x00 24.--31. 1. " INTID31 ,Interrupt ID31 Priority/Priority Byte Offset 31 " hexmask.long.byte 0x00 16.--23. 1. " INTID30 ,Interrupt ID30 Priority/Priority Byte Offset 30 " hexmask.long.byte 0x00 8.--15. 1. " INTID29 ,Interrupt ID29 Priority/Priority Byte Offset 29 " hexmask.long.byte 0x00 0.--7. 1. " INTID28 ,Interrupt ID28 Priority/Priority Byte Offset 28 " if (((per.l(ad:(per.long(spr:0x31F30)&0xFFFC0000)+0x04))&0x0000001F)>=0x01) group.long 0x420++0x03 line.long 0x00 "GICD_IPRIORITYR8,Interrupt Priority Register 8" hexmask.long.byte 0x00 24.--31. 1. " INTID35 ,Interrupt ID35 Priority/Priority Byte Offset 35 " hexmask.long.byte 0x00 16.--23. 1. " INTID34 ,Interrupt ID34 Priority/Priority Byte Offset 34 " hexmask.long.byte 0x00 8.--15. 1. " INTID33 ,Interrupt ID33 Priority/Priority Byte Offset 33 " hexmask.long.byte 0x00 0.--7. 1. " INTID32 ,Interrupt ID32 Priority/Priority Byte Offset 32 " group.long 0x424++0x03 line.long 0x00 "GICD_IPRIORITYR9,Interrupt Priority Register 9" hexmask.long.byte 0x00 24.--31. 1. " INTID39 ,Interrupt ID39 Priority/Priority Byte Offset 39 " hexmask.long.byte 0x00 16.--23. 1. " INTID38 ,Interrupt ID38 Priority/Priority Byte Offset 38 " hexmask.long.byte 0x00 8.--15. 1. " INTID37 ,Interrupt ID37 Priority/Priority Byte Offset 37 " hexmask.long.byte 0x00 0.--7. 1. " INTID36 ,Interrupt ID36 Priority/Priority Byte Offset 36 " group.long 0x428++0x03 line.long 0x00 "GICD_IPRIORITYR10,Interrupt Priority Register 10" hexmask.long.byte 0x00 24.--31. 1. " INTID43 ,Interrupt ID43 Priority/Priority Byte Offset 43 " hexmask.long.byte 0x00 16.--23. 1. " INTID42 ,Interrupt ID42 Priority/Priority Byte Offset 42 " hexmask.long.byte 0x00 8.--15. 1. " INTID41 ,Interrupt ID41 Priority/Priority Byte Offset 41 " hexmask.long.byte 0x00 0.--7. 1. " INTID40 ,Interrupt ID40 Priority/Priority Byte Offset 40 " group.long 0x42C++0x03 line.long 0x00 "GICD_IPRIORITYR11,Interrupt Priority Register 11" hexmask.long.byte 0x00 24.--31. 1. " INTID47 ,Interrupt ID47 Priority/Priority Byte Offset 47 " hexmask.long.byte 0x00 16.--23. 1. " INTID46 ,Interrupt ID46 Priority/Priority Byte Offset 46 " hexmask.long.byte 0x00 8.--15. 1. " INTID45 ,Interrupt ID45 Priority/Priority Byte Offset 45 " hexmask.long.byte 0x00 0.--7. 1. " INTID44 ,Interrupt ID44 Priority/Priority Byte Offset 44 " group.long 0x430++0x03 line.long 0x00 "GICD_IPRIORITYR12,Interrupt Priority Register 12" hexmask.long.byte 0x00 24.--31. 1. " INTID51 ,Interrupt ID51 Priority/Priority Byte Offset 51 " hexmask.long.byte 0x00 16.--23. 1. " INTID50 ,Interrupt ID50 Priority/Priority Byte Offset 50 " hexmask.long.byte 0x00 8.--15. 1. " INTID49 ,Interrupt ID49 Priority/Priority Byte Offset 49 " hexmask.long.byte 0x00 0.--7. 1. " INTID48 ,Interrupt ID48 Priority/Priority Byte Offset 48 " group.long 0x434++0x03 line.long 0x00 "GICD_IPRIORITYR13,Interrupt Priority Register 13" hexmask.long.byte 0x00 24.--31. 1. " INTID55 ,Interrupt ID55 Priority/Priority Byte Offset 55 " hexmask.long.byte 0x00 16.--23. 1. " INTID54 ,Interrupt ID54 Priority/Priority Byte Offset 54 " hexmask.long.byte 0x00 8.--15. 1. " INTID53 ,Interrupt ID53 Priority/Priority Byte Offset 53 " hexmask.long.byte 0x00 0.--7. 1. " INTID52 ,Interrupt ID52 Priority/Priority Byte Offset 52 " group.long 0x438++0x03 line.long 0x00 "GICD_IPRIORITYR14,Interrupt Priority Register 14" hexmask.long.byte 0x00 24.--31. 1. " INTID59 ,Interrupt ID59 Priority/Priority Byte Offset 59 " hexmask.long.byte 0x00 16.--23. 1. " INTID58 ,Interrupt ID58 Priority/Priority Byte Offset 58 " hexmask.long.byte 0x00 8.--15. 1. " INTID57 ,Interrupt ID57 Priority/Priority Byte Offset 57 " hexmask.long.byte 0x00 0.--7. 1. " INTID56 ,Interrupt ID56 Priority/Priority Byte Offset 56 " group.long 0x43C++0x03 line.long 0x00 "GICD_IPRIORITYR15,Interrupt Priority Register 15" hexmask.long.byte 0x00 24.--31. 1. " INTID63 ,Interrupt ID63 Priority/Priority Byte Offset 63 " hexmask.long.byte 0x00 16.--23. 1. " INTID62 ,Interrupt ID62 Priority/Priority Byte Offset 62 " hexmask.long.byte 0x00 8.--15. 1. " INTID61 ,Interrupt ID61 Priority/Priority Byte Offset 61 " hexmask.long.byte 0x00 0.--7. 1. " INTID60 ,Interrupt ID60 Priority/Priority Byte Offset 60 " else rgroup.long 0x420++0x03 line.long 0x00 "GICD_IPRIORITYR8,Interrupt Priority Register 8" rgroup.long 0x424++0x03 line.long 0x00 "GICD_IPRIORITYR9,Interrupt Priority Register 9" rgroup.long 0x428++0x03 line.long 0x00 "GICD_IPRIORITYR10,Interrupt Priority Register 10" rgroup.long 0x42C++0x03 line.long 0x00 "GICD_IPRIORITYR11,Interrupt Priority Register 11" rgroup.long 0x430++0x03 line.long 0x00 "GICD_IPRIORITYR12,Interrupt Priority Register 12" rgroup.long 0x434++0x03 line.long 0x00 "GICD_IPRIORITYR13,Interrupt Priority Register 13" rgroup.long 0x438++0x03 line.long 0x00 "GICD_IPRIORITYR14,Interrupt Priority Register 14" rgroup.long 0x43C++0x03 line.long 0x00 "GICD_IPRIORITYR15,Interrupt Priority Register 15" endif if (((per.l(ad:(per.long(spr:0x31F30)&0xFFFC0000)+0x04))&0x0000001F)>=0x02) group.long 0x440++0x03 line.long 0x00 "GICD_IPRIORITYR16,Interrupt Priority Register 16" hexmask.long.byte 0x00 24.--31. 1. " INTID67 ,Interrupt ID67 Priority/Priority Byte Offset 67 " hexmask.long.byte 0x00 16.--23. 1. " INTID66 ,Interrupt ID66 Priority/Priority Byte Offset 66 " hexmask.long.byte 0x00 8.--15. 1. " INTID65 ,Interrupt ID65 Priority/Priority Byte Offset 65 " hexmask.long.byte 0x00 0.--7. 1. " INTID64 ,Interrupt ID64 Priority/Priority Byte Offset 64 " group.long 0x444++0x03 line.long 0x00 "GICD_IPRIORITYR17,Interrupt Priority Register 17" hexmask.long.byte 0x00 24.--31. 1. " INTID71 ,Interrupt ID71 Priority/Priority Byte Offset 71 " hexmask.long.byte 0x00 16.--23. 1. " INTID70 ,Interrupt ID70 Priority/Priority Byte Offset 70 " hexmask.long.byte 0x00 8.--15. 1. " INTID69 ,Interrupt ID69 Priority/Priority Byte Offset 69 " hexmask.long.byte 0x00 0.--7. 1. " INTID68 ,Interrupt ID68 Priority/Priority Byte Offset 68 " group.long 0x448++0x03 line.long 0x00 "GICD_IPRIORITYR18,Interrupt Priority Register 18" hexmask.long.byte 0x00 24.--31. 1. " INTID75 ,Interrupt ID75 Priority/Priority Byte Offset 75 " hexmask.long.byte 0x00 16.--23. 1. " INTID74 ,Interrupt ID74 Priority/Priority Byte Offset 74 " hexmask.long.byte 0x00 8.--15. 1. " INTID73 ,Interrupt ID73 Priority/Priority Byte Offset 73 " hexmask.long.byte 0x00 0.--7. 1. " INTID72 ,Interrupt ID72 Priority/Priority Byte Offset 72 " group.long 0x44C++0x03 line.long 0x00 "GICD_IPRIORITYR19,Interrupt Priority Register 19" hexmask.long.byte 0x00 24.--31. 1. " INTID79 ,Interrupt ID79 Priority/Priority Byte Offset 79 " hexmask.long.byte 0x00 16.--23. 1. " INTID78 ,Interrupt ID78 Priority/Priority Byte Offset 78 " hexmask.long.byte 0x00 8.--15. 1. " INTID77 ,Interrupt ID77 Priority/Priority Byte Offset 77 " hexmask.long.byte 0x00 0.--7. 1. " INTID76 ,Interrupt ID76 Priority/Priority Byte Offset 76 " group.long 0x450++0x03 line.long 0x00 "GICD_IPRIORITYR20,Interrupt Priority Register 20" hexmask.long.byte 0x00 24.--31. 1. " INTID83 ,Interrupt ID83 Priority/Priority Byte Offset 83 " hexmask.long.byte 0x00 16.--23. 1. " INTID82 ,Interrupt ID82 Priority/Priority Byte Offset 82 " hexmask.long.byte 0x00 8.--15. 1. " INTID81 ,Interrupt ID81 Priority/Priority Byte Offset 81 " hexmask.long.byte 0x00 0.--7. 1. " INTID80 ,Interrupt ID80 Priority/Priority Byte Offset 80 " group.long 0x454++0x03 line.long 0x00 "GICD_IPRIORITYR21,Interrupt Priority Register 21" hexmask.long.byte 0x00 24.--31. 1. " INTID87 ,Interrupt ID87 Priority/Priority Byte Offset 87 " hexmask.long.byte 0x00 16.--23. 1. " INTID86 ,Interrupt ID86 Priority/Priority Byte Offset 86 " hexmask.long.byte 0x00 8.--15. 1. " INTID85 ,Interrupt ID85 Priority/Priority Byte Offset 85 " hexmask.long.byte 0x00 0.--7. 1. " INTID84 ,Interrupt ID84 Priority/Priority Byte Offset 84 " group.long 0x458++0x03 line.long 0x00 "GICD_IPRIORITYR22,Interrupt Priority Register 22" hexmask.long.byte 0x00 24.--31. 1. " INTID91 ,Interrupt ID91 Priority/Priority Byte Offset 91 " hexmask.long.byte 0x00 16.--23. 1. " INTID90 ,Interrupt ID90 Priority/Priority Byte Offset 90 " hexmask.long.byte 0x00 8.--15. 1. " INTID89 ,Interrupt ID89 Priority/Priority Byte Offset 89 " hexmask.long.byte 0x00 0.--7. 1. " INTID88 ,Interrupt ID88 Priority/Priority Byte Offset 88 " group.long 0x45C++0x03 line.long 0x00 "GICD_IPRIORITYR23,Interrupt Priority Register 23" hexmask.long.byte 0x00 24.--31. 1. " INTID95 ,Interrupt ID95 Priority/Priority Byte Offset 95 " hexmask.long.byte 0x00 16.--23. 1. " INTID94 ,Interrupt ID94 Priority/Priority Byte Offset 94 " hexmask.long.byte 0x00 8.--15. 1. " INTID93 ,Interrupt ID93 Priority/Priority Byte Offset 93 " hexmask.long.byte 0x00 0.--7. 1. " INTID92 ,Interrupt ID92 Priority/Priority Byte Offset 92 " else rgroup.long 0x440++0x03 line.long 0x00 "GICD_IPRIORITYR16,Interrupt Priority Register 16" rgroup.long 0x444++0x03 line.long 0x00 "GICD_IPRIORITYR17,Interrupt Priority Register 17" rgroup.long 0x448++0x03 line.long 0x00 "GICD_IPRIORITYR18,Interrupt Priority Register 18" rgroup.long 0x44C++0x03 line.long 0x00 "GICD_IPRIORITYR19,Interrupt Priority Register 19" rgroup.long 0x450++0x03 line.long 0x00 "GICD_IPRIORITYR20,Interrupt Priority Register 20" rgroup.long 0x454++0x03 line.long 0x00 "GICD_IPRIORITYR21,Interrupt Priority Register 21" rgroup.long 0x458++0x03 line.long 0x00 "GICD_IPRIORITYR22,Interrupt Priority Register 22" rgroup.long 0x45C++0x03 line.long 0x00 "GICD_IPRIORITYR23,Interrupt Priority Register 23" endif if (((per.l(ad:(per.long(spr:0x31F30)&0xFFFC0000)+0x04))&0x0000001F)>=0x03) group.long 0x460++0x03 line.long 0x00 "GICD_IPRIORITYR24,Interrupt Priority Register 24" hexmask.long.byte 0x00 24.--31. 1. " INTID99 ,Interrupt ID99 Priority/Priority Byte Offset 99 " hexmask.long.byte 0x00 16.--23. 1. " INTID98 ,Interrupt ID98 Priority/Priority Byte Offset 98 " hexmask.long.byte 0x00 8.--15. 1. " INTID97 ,Interrupt ID97 Priority/Priority Byte Offset 97 " hexmask.long.byte 0x00 0.--7. 1. " INTID96 ,Interrupt ID96 Priority/Priority Byte Offset 96 " group.long 0x464++0x03 line.long 0x00 "GICD_IPRIORITYR25,Interrupt Priority Register 25" hexmask.long.byte 0x00 24.--31. 1. " INTID103 ,Interrupt ID103 Priority/Priority Byte Offset 103 " hexmask.long.byte 0x00 16.--23. 1. " INTID102 ,Interrupt ID102 Priority/Priority Byte Offset 102 " hexmask.long.byte 0x00 8.--15. 1. " INTID101 ,Interrupt ID101 Priority/Priority Byte Offset 101 " hexmask.long.byte 0x00 0.--7. 1. " INTID100 ,Interrupt ID100 Priority/Priority Byte Offset 100 " group.long 0x468++0x03 line.long 0x00 "GICD_IPRIORITYR26,Interrupt Priority Register 26" hexmask.long.byte 0x00 24.--31. 1. " INTID107 ,Interrupt ID107 Priority/Priority Byte Offset 107 " hexmask.long.byte 0x00 16.--23. 1. " INTID106 ,Interrupt ID106 Priority/Priority Byte Offset 106 " hexmask.long.byte 0x00 8.--15. 1. " INTID105 ,Interrupt ID105 Priority/Priority Byte Offset 105 " hexmask.long.byte 0x00 0.--7. 1. " INTID104 ,Interrupt ID104 Priority/Priority Byte Offset 104 " group.long 0x46C++0x03 line.long 0x00 "GICD_IPRIORITYR27,Interrupt Priority Register 27" hexmask.long.byte 0x00 24.--31. 1. " INTID111 ,Interrupt ID111 Priority/Priority Byte Offset 111 " hexmask.long.byte 0x00 16.--23. 1. " INTID110 ,Interrupt ID110 Priority/Priority Byte Offset 110 " hexmask.long.byte 0x00 8.--15. 1. " INTID109 ,Interrupt ID109 Priority/Priority Byte Offset 109 " hexmask.long.byte 0x00 0.--7. 1. " INTID108 ,Interrupt ID108 Priority/Priority Byte Offset 108 " group.long 0x470++0x03 line.long 0x00 "GICD_IPRIORITYR28,Interrupt Priority Register 28" hexmask.long.byte 0x00 24.--31. 1. " INTID115 ,Interrupt ID115 Priority/Priority Byte Offset 115 " hexmask.long.byte 0x00 16.--23. 1. " INTID114 ,Interrupt ID114 Priority/Priority Byte Offset 114 " hexmask.long.byte 0x00 8.--15. 1. " INTID113 ,Interrupt ID113 Priority/Priority Byte Offset 113 " hexmask.long.byte 0x00 0.--7. 1. " INTID112 ,Interrupt ID112 Priority/Priority Byte Offset 112 " group.long 0x474++0x03 line.long 0x00 "GICD_IPRIORITYR29,Interrupt Priority Register 29" hexmask.long.byte 0x00 24.--31. 1. " INTID119 ,Interrupt ID119 Priority/Priority Byte Offset 119 " hexmask.long.byte 0x00 16.--23. 1. " INTID118 ,Interrupt ID118 Priority/Priority Byte Offset 118 " hexmask.long.byte 0x00 8.--15. 1. " INTID117 ,Interrupt ID117 Priority/Priority Byte Offset 117 " hexmask.long.byte 0x00 0.--7. 1. " INTID116 ,Interrupt ID116 Priority/Priority Byte Offset 116 " group.long 0x478++0x03 line.long 0x00 "GICD_IPRIORITYR30,Interrupt Priority Register 30" hexmask.long.byte 0x00 24.--31. 1. " INTID123 ,Interrupt ID123 Priority/Priority Byte Offset 123 " hexmask.long.byte 0x00 16.--23. 1. " INTID122 ,Interrupt ID122 Priority/Priority Byte Offset 122 " hexmask.long.byte 0x00 8.--15. 1. " INTID121 ,Interrupt ID121 Priority/Priority Byte Offset 121 " hexmask.long.byte 0x00 0.--7. 1. " INTID120 ,Interrupt ID120 Priority/Priority Byte Offset 120 " group.long 0x47C++0x03 line.long 0x00 "GICD_IPRIORITYR31,Interrupt Priority Register 31" hexmask.long.byte 0x00 24.--31. 1. " INTID127 ,Interrupt ID127 Priority/Priority Byte Offset 127 " hexmask.long.byte 0x00 16.--23. 1. " INTID126 ,Interrupt ID126 Priority/Priority Byte Offset 126 " hexmask.long.byte 0x00 8.--15. 1. " INTID125 ,Interrupt ID125 Priority/Priority Byte Offset 125 " hexmask.long.byte 0x00 0.--7. 1. " INTID124 ,Interrupt ID124 Priority/Priority Byte Offset 124 " else rgroup.long 0x460++0x03 line.long 0x00 "GICD_IPRIORITYR24,Interrupt Priority Register 24" rgroup.long 0x464++0x03 line.long 0x00 "GICD_IPRIORITYR25,Interrupt Priority Register 25" rgroup.long 0x468++0x03 line.long 0x00 "GICD_IPRIORITYR26,Interrupt Priority Register 26" rgroup.long 0x46C++0x03 line.long 0x00 "GICD_IPRIORITYR27,Interrupt Priority Register 27" rgroup.long 0x470++0x03 line.long 0x00 "GICD_IPRIORITYR28,Interrupt Priority Register 28" rgroup.long 0x474++0x03 line.long 0x00 "GICD_IPRIORITYR29,Interrupt Priority Register 29" rgroup.long 0x478++0x03 line.long 0x00 "GICD_IPRIORITYR30,Interrupt Priority Register 30" rgroup.long 0x47C++0x03 line.long 0x00 "GICD_IPRIORITYR31,Interrupt Priority Register 31" endif if (((per.l(ad:(per.long(spr:0x31F30)&0xFFFC0000)+0x04))&0x0000001F)>=0x04) group.long 0x480++0x03 line.long 0x00 "GICD_IPRIORITYR32,Interrupt Priority Register 32" hexmask.long.byte 0x00 24.--31. 1. " INTID131 ,Interrupt ID131 Priority/Priority Byte Offset 131 " hexmask.long.byte 0x00 16.--23. 1. " INTID130 ,Interrupt ID130 Priority/Priority Byte Offset 130 " hexmask.long.byte 0x00 8.--15. 1. " INTID129 ,Interrupt ID129 Priority/Priority Byte Offset 129 " hexmask.long.byte 0x00 0.--7. 1. " INTID128 ,Interrupt ID128 Priority/Priority Byte Offset 128 " group.long 0x484++0x03 line.long 0x00 "GICD_IPRIORITYR33,Interrupt Priority Register 33" hexmask.long.byte 0x00 24.--31. 1. " INTID135 ,Interrupt ID135 Priority/Priority Byte Offset 135 " hexmask.long.byte 0x00 16.--23. 1. " INTID134 ,Interrupt ID134 Priority/Priority Byte Offset 134 " hexmask.long.byte 0x00 8.--15. 1. " INTID133 ,Interrupt ID133 Priority/Priority Byte Offset 133 " hexmask.long.byte 0x00 0.--7. 1. " INTID132 ,Interrupt ID132 Priority/Priority Byte Offset 132 " group.long 0x488++0x03 line.long 0x00 "GICD_IPRIORITYR34,Interrupt Priority Register 34" hexmask.long.byte 0x00 24.--31. 1. " INTID139 ,Interrupt ID139 Priority/Priority Byte Offset 139 " hexmask.long.byte 0x00 16.--23. 1. " INTID138 ,Interrupt ID138 Priority/Priority Byte Offset 138 " hexmask.long.byte 0x00 8.--15. 1. " INTID137 ,Interrupt ID137 Priority/Priority Byte Offset 137 " hexmask.long.byte 0x00 0.--7. 1. " INTID136 ,Interrupt ID136 Priority/Priority Byte Offset 136 " group.long 0x48C++0x03 line.long 0x00 "GICD_IPRIORITYR35,Interrupt Priority Register 35" hexmask.long.byte 0x00 24.--31. 1. " INTID143 ,Interrupt ID143 Priority/Priority Byte Offset 143 " hexmask.long.byte 0x00 16.--23. 1. " INTID142 ,Interrupt ID142 Priority/Priority Byte Offset 142 " hexmask.long.byte 0x00 8.--15. 1. " INTID141 ,Interrupt ID141 Priority/Priority Byte Offset 141 " hexmask.long.byte 0x00 0.--7. 1. " INTID140 ,Interrupt ID140 Priority/Priority Byte Offset 140 " group.long 0x490++0x03 line.long 0x00 "GICD_IPRIORITYR36,Interrupt Priority Register 36" hexmask.long.byte 0x00 24.--31. 1. " INTID147 ,Interrupt ID147 Priority/Priority Byte Offset 147 " hexmask.long.byte 0x00 16.--23. 1. " INTID146 ,Interrupt ID146 Priority/Priority Byte Offset 146 " hexmask.long.byte 0x00 8.--15. 1. " INTID145 ,Interrupt ID145 Priority/Priority Byte Offset 145 " hexmask.long.byte 0x00 0.--7. 1. " INTID144 ,Interrupt ID144 Priority/Priority Byte Offset 144 " group.long 0x494++0x03 line.long 0x00 "GICD_IPRIORITYR37,Interrupt Priority Register 37" hexmask.long.byte 0x00 24.--31. 1. " INTID151 ,Interrupt ID151 Priority/Priority Byte Offset 151 " hexmask.long.byte 0x00 16.--23. 1. " INTID150 ,Interrupt ID150 Priority/Priority Byte Offset 150 " hexmask.long.byte 0x00 8.--15. 1. " INTID149 ,Interrupt ID149 Priority/Priority Byte Offset 149 " hexmask.long.byte 0x00 0.--7. 1. " INTID148 ,Interrupt ID148 Priority/Priority Byte Offset 148 " group.long 0x498++0x03 line.long 0x00 "GICD_IPRIORITYR38,Interrupt Priority Register 38" hexmask.long.byte 0x00 24.--31. 1. " INTID155 ,Interrupt ID155 Priority/Priority Byte Offset 155 " hexmask.long.byte 0x00 16.--23. 1. " INTID154 ,Interrupt ID154 Priority/Priority Byte Offset 154 " hexmask.long.byte 0x00 8.--15. 1. " INTID153 ,Interrupt ID153 Priority/Priority Byte Offset 153 " hexmask.long.byte 0x00 0.--7. 1. " INTID152 ,Interrupt ID152 Priority/Priority Byte Offset 152 " group.long 0x49C++0x03 line.long 0x00 "GICD_IPRIORITYR39,Interrupt Priority Register 39" hexmask.long.byte 0x00 24.--31. 1. " INTID159 ,Interrupt ID159 Priority/Priority Byte Offset 159 " hexmask.long.byte 0x00 16.--23. 1. " INTID158 ,Interrupt ID158 Priority/Priority Byte Offset 158 " hexmask.long.byte 0x00 8.--15. 1. " INTID157 ,Interrupt ID157 Priority/Priority Byte Offset 157 " hexmask.long.byte 0x00 0.--7. 1. " INTID156 ,Interrupt ID156 Priority/Priority Byte Offset 156 " else rgroup.long 0x480++0x03 line.long 0x00 "GICD_IPRIORITYR32,Interrupt Priority Register 32" rgroup.long 0x484++0x03 line.long 0x00 "GICD_IPRIORITYR33,Interrupt Priority Register 33" rgroup.long 0x488++0x03 line.long 0x00 "GICD_IPRIORITYR34,Interrupt Priority Register 34" rgroup.long 0x48C++0x03 line.long 0x00 "GICD_IPRIORITYR35,Interrupt Priority Register 35" rgroup.long 0x490++0x03 line.long 0x00 "GICD_IPRIORITYR36,Interrupt Priority Register 36" rgroup.long 0x494++0x03 line.long 0x00 "GICD_IPRIORITYR37,Interrupt Priority Register 37" rgroup.long 0x498++0x03 line.long 0x00 "GICD_IPRIORITYR38,Interrupt Priority Register 38" rgroup.long 0x49C++0x03 line.long 0x00 "GICD_IPRIORITYR39,Interrupt Priority Register 39" endif if (((per.l(ad:(per.long(spr:0x31F30)&0xFFFC0000)+0x04))&0x0000001F)>=0x05) group.long 0x4A0++0x03 line.long 0x00 "GICD_IPRIORITYR40,Interrupt Priority Register 40" hexmask.long.byte 0x00 24.--31. 1. " INTID163 ,Interrupt ID163 Priority/Priority Byte Offset 163 " hexmask.long.byte 0x00 16.--23. 1. " INTID162 ,Interrupt ID162 Priority/Priority Byte Offset 162 " hexmask.long.byte 0x00 8.--15. 1. " INTID161 ,Interrupt ID161 Priority/Priority Byte Offset 161 " hexmask.long.byte 0x00 0.--7. 1. " INTID160 ,Interrupt ID160 Priority/Priority Byte Offset 160 " group.long 0x4A4++0x03 line.long 0x00 "GICD_IPRIORITYR41,Interrupt Priority Register 41" hexmask.long.byte 0x00 24.--31. 1. " INTID167 ,Interrupt ID167 Priority/Priority Byte Offset 167 " hexmask.long.byte 0x00 16.--23. 1. " INTID166 ,Interrupt ID166 Priority/Priority Byte Offset 166 " hexmask.long.byte 0x00 8.--15. 1. " INTID165 ,Interrupt ID165 Priority/Priority Byte Offset 165 " hexmask.long.byte 0x00 0.--7. 1. " INTID164 ,Interrupt ID164 Priority/Priority Byte Offset 164 " group.long 0x4A8++0x03 line.long 0x00 "GICD_IPRIORITYR42,Interrupt Priority Register 42" hexmask.long.byte 0x00 24.--31. 1. " INTID171 ,Interrupt ID171 Priority/Priority Byte Offset 171 " hexmask.long.byte 0x00 16.--23. 1. " INTID170 ,Interrupt ID170 Priority/Priority Byte Offset 170 " hexmask.long.byte 0x00 8.--15. 1. " INTID169 ,Interrupt ID169 Priority/Priority Byte Offset 169 " hexmask.long.byte 0x00 0.--7. 1. " INTID168 ,Interrupt ID168 Priority/Priority Byte Offset 168 " group.long 0x4AC++0x03 line.long 0x00 "GICD_IPRIORITYR43,Interrupt Priority Register 43" hexmask.long.byte 0x00 24.--31. 1. " INTID175 ,Interrupt ID175 Priority/Priority Byte Offset 175 " hexmask.long.byte 0x00 16.--23. 1. " INTID174 ,Interrupt ID174 Priority/Priority Byte Offset 174 " hexmask.long.byte 0x00 8.--15. 1. " INTID173 ,Interrupt ID173 Priority/Priority Byte Offset 173 " hexmask.long.byte 0x00 0.--7. 1. " INTID172 ,Interrupt ID172 Priority/Priority Byte Offset 172 " group.long 0x4B0++0x03 line.long 0x00 "GICD_IPRIORITYR44,Interrupt Priority Register 44" hexmask.long.byte 0x00 24.--31. 1. " INTID179 ,Interrupt ID179 Priority/Priority Byte Offset 179 " hexmask.long.byte 0x00 16.--23. 1. " INTID178 ,Interrupt ID178 Priority/Priority Byte Offset 178 " hexmask.long.byte 0x00 8.--15. 1. " INTID177 ,Interrupt ID177 Priority/Priority Byte Offset 177 " hexmask.long.byte 0x00 0.--7. 1. " INTID176 ,Interrupt ID176 Priority/Priority Byte Offset 176 " group.long 0x4B4++0x03 line.long 0x00 "GICD_IPRIORITYR45,Interrupt Priority Register 45" hexmask.long.byte 0x00 24.--31. 1. " INTID183 ,Interrupt ID183 Priority/Priority Byte Offset 183 " hexmask.long.byte 0x00 16.--23. 1. " INTID182 ,Interrupt ID182 Priority/Priority Byte Offset 182 " hexmask.long.byte 0x00 8.--15. 1. " INTID181 ,Interrupt ID181 Priority/Priority Byte Offset 181 " hexmask.long.byte 0x00 0.--7. 1. " INTID180 ,Interrupt ID180 Priority/Priority Byte Offset 180 " group.long 0x4B8++0x03 line.long 0x00 "GICD_IPRIORITYR46,Interrupt Priority Register 46" hexmask.long.byte 0x00 24.--31. 1. " INTID187 ,Interrupt ID187 Priority/Priority Byte Offset 187 " hexmask.long.byte 0x00 16.--23. 1. " INTID186 ,Interrupt ID186 Priority/Priority Byte Offset 186 " hexmask.long.byte 0x00 8.--15. 1. " INTID185 ,Interrupt ID185 Priority/Priority Byte Offset 185 " hexmask.long.byte 0x00 0.--7. 1. " INTID184 ,Interrupt ID184 Priority/Priority Byte Offset 184 " group.long 0x4BC++0x03 line.long 0x00 "GICD_IPRIORITYR47,Interrupt Priority Register 47" hexmask.long.byte 0x00 24.--31. 1. " INTID191 ,Interrupt ID191 Priority/Priority Byte Offset 191 " hexmask.long.byte 0x00 16.--23. 1. " INTID190 ,Interrupt ID190 Priority/Priority Byte Offset 190 " hexmask.long.byte 0x00 8.--15. 1. " INTID189 ,Interrupt ID189 Priority/Priority Byte Offset 189 " hexmask.long.byte 0x00 0.--7. 1. " INTID188 ,Interrupt ID188 Priority/Priority Byte Offset 188 " else rgroup.long 0x4A0++0x03 line.long 0x00 "GICD_IPRIORITYR40,Interrupt Priority Register 40" rgroup.long 0x4A4++0x03 line.long 0x00 "GICD_IPRIORITYR41,Interrupt Priority Register 41" rgroup.long 0x4A8++0x03 line.long 0x00 "GICD_IPRIORITYR42,Interrupt Priority Register 42" rgroup.long 0x4AC++0x03 line.long 0x00 "GICD_IPRIORITYR43,Interrupt Priority Register 43" rgroup.long 0x4B0++0x03 line.long 0x00 "GICD_IPRIORITYR44,Interrupt Priority Register 44" rgroup.long 0x4B4++0x03 line.long 0x00 "GICD_IPRIORITYR45,Interrupt Priority Register 45" rgroup.long 0x4B8++0x03 line.long 0x00 "GICD_IPRIORITYR46,Interrupt Priority Register 46" rgroup.long 0x4BC++0x03 line.long 0x00 "GICD_IPRIORITYR47,Interrupt Priority Register 47" endif if (((per.l(ad:(per.long(spr:0x31F30)&0xFFFC0000)+0x04))&0x0000001F)>=0x06) group.long 0x4C0++0x03 line.long 0x00 "GICD_IPRIORITYR48,Interrupt Priority Register 48" hexmask.long.byte 0x00 24.--31. 1. " INTID195 ,Interrupt ID195 Priority/Priority Byte Offset 195 " hexmask.long.byte 0x00 16.--23. 1. " INTID194 ,Interrupt ID194 Priority/Priority Byte Offset 194 " hexmask.long.byte 0x00 8.--15. 1. " INTID193 ,Interrupt ID193 Priority/Priority Byte Offset 193 " hexmask.long.byte 0x00 0.--7. 1. " INTID192 ,Interrupt ID192 Priority/Priority Byte Offset 192 " group.long 0x4C4++0x03 line.long 0x00 "GICD_IPRIORITYR49,Interrupt Priority Register 49" hexmask.long.byte 0x00 24.--31. 1. " INTID199 ,Interrupt ID199 Priority/Priority Byte Offset 199 " hexmask.long.byte 0x00 16.--23. 1. " INTID198 ,Interrupt ID198 Priority/Priority Byte Offset 198 " hexmask.long.byte 0x00 8.--15. 1. " INTID197 ,Interrupt ID197 Priority/Priority Byte Offset 197 " hexmask.long.byte 0x00 0.--7. 1. " INTID196 ,Interrupt ID196 Priority/Priority Byte Offset 196 " group.long 0x4C8++0x03 line.long 0x00 "GICD_IPRIORITYR50,Interrupt Priority Register 50" hexmask.long.byte 0x00 24.--31. 1. " INTID203 ,Interrupt ID203 Priority/Priority Byte Offset 203 " hexmask.long.byte 0x00 16.--23. 1. " INTID202 ,Interrupt ID202 Priority/Priority Byte Offset 202 " hexmask.long.byte 0x00 8.--15. 1. " INTID201 ,Interrupt ID201 Priority/Priority Byte Offset 201 " hexmask.long.byte 0x00 0.--7. 1. " INTID200 ,Interrupt ID200 Priority/Priority Byte Offset 200 " group.long 0x4CC++0x03 line.long 0x00 "GICD_IPRIORITYR51,Interrupt Priority Register 51" hexmask.long.byte 0x00 24.--31. 1. " INTID207 ,Interrupt ID207 Priority/Priority Byte Offset 207 " hexmask.long.byte 0x00 16.--23. 1. " INTID206 ,Interrupt ID206 Priority/Priority Byte Offset 206 " hexmask.long.byte 0x00 8.--15. 1. " INTID205 ,Interrupt ID205 Priority/Priority Byte Offset 205 " hexmask.long.byte 0x00 0.--7. 1. " INTID204 ,Interrupt ID204 Priority/Priority Byte Offset 204 " group.long 0x4D0++0x03 line.long 0x00 "GICD_IPRIORITYR52,Interrupt Priority Register 52" hexmask.long.byte 0x00 24.--31. 1. " INTID211 ,Interrupt ID211 Priority/Priority Byte Offset 211 " hexmask.long.byte 0x00 16.--23. 1. " INTID210 ,Interrupt ID210 Priority/Priority Byte Offset 210 " hexmask.long.byte 0x00 8.--15. 1. " INTID209 ,Interrupt ID209 Priority/Priority Byte Offset 209 " hexmask.long.byte 0x00 0.--7. 1. " INTID208 ,Interrupt ID208 Priority/Priority Byte Offset 208 " group.long 0x4D4++0x03 line.long 0x00 "GICD_IPRIORITYR53,Interrupt Priority Register 53" hexmask.long.byte 0x00 24.--31. 1. " INTID215 ,Interrupt ID215 Priority/Priority Byte Offset 215 " hexmask.long.byte 0x00 16.--23. 1. " INTID214 ,Interrupt ID214 Priority/Priority Byte Offset 214 " hexmask.long.byte 0x00 8.--15. 1. " INTID213 ,Interrupt ID213 Priority/Priority Byte Offset 213 " hexmask.long.byte 0x00 0.--7. 1. " INTID212 ,Interrupt ID212 Priority/Priority Byte Offset 212 " group.long 0x4D8++0x03 line.long 0x00 "GICD_IPRIORITYR54,Interrupt Priority Register 54" hexmask.long.byte 0x00 24.--31. 1. " INTID219 ,Interrupt ID219 Priority/Priority Byte Offset 219 " hexmask.long.byte 0x00 16.--23. 1. " INTID218 ,Interrupt ID218 Priority/Priority Byte Offset 218 " hexmask.long.byte 0x00 8.--15. 1. " INTID217 ,Interrupt ID217 Priority/Priority Byte Offset 217 " hexmask.long.byte 0x00 0.--7. 1. " INTID216 ,Interrupt ID216 Priority/Priority Byte Offset 216 " group.long 0x4DC++0x03 line.long 0x00 "GICD_IPRIORITYR55,Interrupt Priority Register 55" hexmask.long.byte 0x00 24.--31. 1. " INTID223 ,Interrupt ID223 Priority/Priority Byte Offset 223 " hexmask.long.byte 0x00 16.--23. 1. " INTID222 ,Interrupt ID222 Priority/Priority Byte Offset 222 " hexmask.long.byte 0x00 8.--15. 1. " INTID221 ,Interrupt ID221 Priority/Priority Byte Offset 221 " hexmask.long.byte 0x00 0.--7. 1. " INTID220 ,Interrupt ID220 Priority/Priority Byte Offset 220 " else rgroup.long 0x4C0++0x03 line.long 0x00 "GICD_IPRIORITYR48,Interrupt Priority Register 48" rgroup.long 0x4C4++0x03 line.long 0x00 "GICD_IPRIORITYR49,Interrupt Priority Register 49" rgroup.long 0x4C8++0x03 line.long 0x00 "GICD_IPRIORITYR50,Interrupt Priority Register 50" rgroup.long 0x4CC++0x03 line.long 0x00 "GICD_IPRIORITYR51,Interrupt Priority Register 51" rgroup.long 0x4D0++0x03 line.long 0x00 "GICD_IPRIORITYR52,Interrupt Priority Register 52" rgroup.long 0x4D4++0x03 line.long 0x00 "GICD_IPRIORITYR53,Interrupt Priority Register 53" rgroup.long 0x4D8++0x03 line.long 0x00 "GICD_IPRIORITYR54,Interrupt Priority Register 54" rgroup.long 0x4DC++0x03 line.long 0x00 "GICD_IPRIORITYR55,Interrupt Priority Register 55" endif if (((per.l(ad:(per.long(spr:0x31F30)&0xFFFC0000)+0x04))&0x0000001F)>=0x07) group.long 0x4E0++0x03 line.long 0x00 "GICD_IPRIORITYR56,Interrupt Priority Register 56" hexmask.long.byte 0x00 24.--31. 1. " INTID227 ,Interrupt ID227 Priority/Priority Byte Offset 227 " hexmask.long.byte 0x00 16.--23. 1. " INTID226 ,Interrupt ID226 Priority/Priority Byte Offset 226 " hexmask.long.byte 0x00 8.--15. 1. " INTID225 ,Interrupt ID225 Priority/Priority Byte Offset 225 " hexmask.long.byte 0x00 0.--7. 1. " INTID224 ,Interrupt ID224 Priority/Priority Byte Offset 224 " group.long 0x4E4++0x03 line.long 0x00 "GICD_IPRIORITYR57,Interrupt Priority Register 57" hexmask.long.byte 0x00 24.--31. 1. " INTID231 ,Interrupt ID231 Priority/Priority Byte Offset 231 " hexmask.long.byte 0x00 16.--23. 1. " INTID230 ,Interrupt ID230 Priority/Priority Byte Offset 230 " hexmask.long.byte 0x00 8.--15. 1. " INTID229 ,Interrupt ID229 Priority/Priority Byte Offset 229 " hexmask.long.byte 0x00 0.--7. 1. " INTID228 ,Interrupt ID228 Priority/Priority Byte Offset 228 " group.long 0x4E8++0x03 line.long 0x00 "GICD_IPRIORITYR58,Interrupt Priority Register 58" hexmask.long.byte 0x00 24.--31. 1. " INTID235 ,Interrupt ID235 Priority/Priority Byte Offset 235 " hexmask.long.byte 0x00 16.--23. 1. " INTID234 ,Interrupt ID234 Priority/Priority Byte Offset 234 " hexmask.long.byte 0x00 8.--15. 1. " INTID233 ,Interrupt ID233 Priority/Priority Byte Offset 233 " hexmask.long.byte 0x00 0.--7. 1. " INTID232 ,Interrupt ID232 Priority/Priority Byte Offset 232 " group.long 0x4EC++0x03 line.long 0x00 "GICD_IPRIORITYR59,Interrupt Priority Register 59" hexmask.long.byte 0x00 24.--31. 1. " INTID239 ,Interrupt ID239 Priority/Priority Byte Offset 239 " hexmask.long.byte 0x00 16.--23. 1. " INTID238 ,Interrupt ID238 Priority/Priority Byte Offset 238 " hexmask.long.byte 0x00 8.--15. 1. " INTID237 ,Interrupt ID237 Priority/Priority Byte Offset 237 " hexmask.long.byte 0x00 0.--7. 1. " INTID236 ,Interrupt ID236 Priority/Priority Byte Offset 236 " group.long 0x4F0++0x03 line.long 0x00 "GICD_IPRIORITYR60,Interrupt Priority Register 60" hexmask.long.byte 0x00 24.--31. 1. " INTID243 ,Interrupt ID243 Priority/Priority Byte Offset 243 " hexmask.long.byte 0x00 16.--23. 1. " INTID242 ,Interrupt ID242 Priority/Priority Byte Offset 242 " hexmask.long.byte 0x00 8.--15. 1. " INTID241 ,Interrupt ID241 Priority/Priority Byte Offset 241 " hexmask.long.byte 0x00 0.--7. 1. " INTID240 ,Interrupt ID240 Priority/Priority Byte Offset 240 " group.long 0x4F4++0x03 line.long 0x00 "GICD_IPRIORITYR61,Interrupt Priority Register 61" hexmask.long.byte 0x00 24.--31. 1. " INTID247 ,Interrupt ID247 Priority/Priority Byte Offset 247 " hexmask.long.byte 0x00 16.--23. 1. " INTID246 ,Interrupt ID246 Priority/Priority Byte Offset 246 " hexmask.long.byte 0x00 8.--15. 1. " INTID245 ,Interrupt ID245 Priority/Priority Byte Offset 245 " hexmask.long.byte 0x00 0.--7. 1. " INTID244 ,Interrupt ID244 Priority/Priority Byte Offset 244 " group.long 0x4F8++0x03 line.long 0x00 "GICD_IPRIORITYR62,Interrupt Priority Register 62" hexmask.long.byte 0x00 24.--31. 1. " INTID251 ,Interrupt ID251 Priority/Priority Byte Offset 251 " hexmask.long.byte 0x00 16.--23. 1. " INTID250 ,Interrupt ID250 Priority/Priority Byte Offset 250 " hexmask.long.byte 0x00 8.--15. 1. " INTID249 ,Interrupt ID249 Priority/Priority Byte Offset 249 " hexmask.long.byte 0x00 0.--7. 1. " INTID248 ,Interrupt ID248 Priority/Priority Byte Offset 248 " group.long 0x4FC++0x03 line.long 0x00 "GICD_IPRIORITYR63,Interrupt Priority Register 63" hexmask.long.byte 0x00 24.--31. 1. " INTID255 ,Interrupt ID255 Priority/Priority Byte Offset 255 " hexmask.long.byte 0x00 16.--23. 1. " INTID254 ,Interrupt ID254 Priority/Priority Byte Offset 254 " hexmask.long.byte 0x00 8.--15. 1. " INTID253 ,Interrupt ID253 Priority/Priority Byte Offset 253 " hexmask.long.byte 0x00 0.--7. 1. " INTID252 ,Interrupt ID252 Priority/Priority Byte Offset 252 " else rgroup.long 0x4E0++0x03 line.long 0x00 "GICD_IPRIORITYR56,Interrupt Priority Register 56" rgroup.long 0x4E4++0x03 line.long 0x00 "GICD_IPRIORITYR57,Interrupt Priority Register 57" rgroup.long 0x4E8++0x03 line.long 0x00 "GICD_IPRIORITYR58,Interrupt Priority Register 58" rgroup.long 0x4EC++0x03 line.long 0x00 "GICD_IPRIORITYR59,Interrupt Priority Register 59" rgroup.long 0x4F0++0x03 line.long 0x00 "GICD_IPRIORITYR60,Interrupt Priority Register 60" rgroup.long 0x4F4++0x03 line.long 0x00 "GICD_IPRIORITYR61,Interrupt Priority Register 61" rgroup.long 0x4F8++0x03 line.long 0x00 "GICD_IPRIORITYR62,Interrupt Priority Register 62" rgroup.long 0x4FC++0x03 line.long 0x00 "GICD_IPRIORITYR63,Interrupt Priority Register 63" endif if (((per.l(ad:(per.long(spr:0x31F30)&0xFFFC0000)+0x04))&0x0000001F)>=0x08) group.long 0x500++0x03 line.long 0x00 "GICD_IPRIORITYR64,Interrupt Priority Register 64" hexmask.long.byte 0x00 24.--31. 1. " INTID259 ,Interrupt ID259 Priority/Priority Byte Offset 259 " hexmask.long.byte 0x00 16.--23. 1. " INTID258 ,Interrupt ID258 Priority/Priority Byte Offset 258 " hexmask.long.byte 0x00 8.--15. 1. " INTID257 ,Interrupt ID257 Priority/Priority Byte Offset 257 " hexmask.long.byte 0x00 0.--7. 1. " INTID256 ,Interrupt ID256 Priority/Priority Byte Offset 256 " group.long 0x504++0x03 line.long 0x00 "GICD_IPRIORITYR65,Interrupt Priority Register 65" hexmask.long.byte 0x00 24.--31. 1. " INTID263 ,Interrupt ID263 Priority/Priority Byte Offset 263 " hexmask.long.byte 0x00 16.--23. 1. " INTID262 ,Interrupt ID262 Priority/Priority Byte Offset 262 " hexmask.long.byte 0x00 8.--15. 1. " INTID261 ,Interrupt ID261 Priority/Priority Byte Offset 261 " hexmask.long.byte 0x00 0.--7. 1. " INTID260 ,Interrupt ID260 Priority/Priority Byte Offset 260 " group.long 0x508++0x03 line.long 0x00 "GICD_IPRIORITYR66,Interrupt Priority Register 66" hexmask.long.byte 0x00 24.--31. 1. " INTID267 ,Interrupt ID267 Priority/Priority Byte Offset 267 " hexmask.long.byte 0x00 16.--23. 1. " INTID266 ,Interrupt ID266 Priority/Priority Byte Offset 266 " hexmask.long.byte 0x00 8.--15. 1. " INTID265 ,Interrupt ID265 Priority/Priority Byte Offset 265 " hexmask.long.byte 0x00 0.--7. 1. " INTID264 ,Interrupt ID264 Priority/Priority Byte Offset 264 " group.long 0x50C++0x03 line.long 0x00 "GICD_IPRIORITYR67,Interrupt Priority Register 67" hexmask.long.byte 0x00 24.--31. 1. " INTID271 ,Interrupt ID271 Priority/Priority Byte Offset 271 " hexmask.long.byte 0x00 16.--23. 1. " INTID270 ,Interrupt ID270 Priority/Priority Byte Offset 270 " hexmask.long.byte 0x00 8.--15. 1. " INTID269 ,Interrupt ID269 Priority/Priority Byte Offset 269 " hexmask.long.byte 0x00 0.--7. 1. " INTID268 ,Interrupt ID268 Priority/Priority Byte Offset 268 " group.long 0x510++0x03 line.long 0x00 "GICD_IPRIORITYR68,Interrupt Priority Register 68" hexmask.long.byte 0x00 24.--31. 1. " INTID275 ,Interrupt ID275 Priority/Priority Byte Offset 275 " hexmask.long.byte 0x00 16.--23. 1. " INTID274 ,Interrupt ID274 Priority/Priority Byte Offset 274 " hexmask.long.byte 0x00 8.--15. 1. " INTID273 ,Interrupt ID273 Priority/Priority Byte Offset 273 " hexmask.long.byte 0x00 0.--7. 1. " INTID272 ,Interrupt ID272 Priority/Priority Byte Offset 272 " group.long 0x514++0x03 line.long 0x00 "GICD_IPRIORITYR69,Interrupt Priority Register 69" hexmask.long.byte 0x00 24.--31. 1. " INTID279 ,Interrupt ID279 Priority/Priority Byte Offset 279 " hexmask.long.byte 0x00 16.--23. 1. " INTID278 ,Interrupt ID278 Priority/Priority Byte Offset 278 " hexmask.long.byte 0x00 8.--15. 1. " INTID277 ,Interrupt ID277 Priority/Priority Byte Offset 277 " hexmask.long.byte 0x00 0.--7. 1. " INTID276 ,Interrupt ID276 Priority/Priority Byte Offset 276 " group.long 0x518++0x03 line.long 0x00 "GICD_IPRIORITYR70,Interrupt Priority Register 70" hexmask.long.byte 0x00 24.--31. 1. " INTID283 ,Interrupt ID283 Priority/Priority Byte Offset 283 " hexmask.long.byte 0x00 16.--23. 1. " INTID282 ,Interrupt ID282 Priority/Priority Byte Offset 282 " hexmask.long.byte 0x00 8.--15. 1. " INTID281 ,Interrupt ID281 Priority/Priority Byte Offset 281 " hexmask.long.byte 0x00 0.--7. 1. " INTID280 ,Interrupt ID280 Priority/Priority Byte Offset 280 " group.long 0x51C++0x03 line.long 0x00 "GICD_IPRIORITYR71,Interrupt Priority Register 71" hexmask.long.byte 0x00 24.--31. 1. " INTID287 ,Interrupt ID287 Priority/Priority Byte Offset 287 " hexmask.long.byte 0x00 16.--23. 1. " INTID286 ,Interrupt ID286 Priority/Priority Byte Offset 286 " hexmask.long.byte 0x00 8.--15. 1. " INTID285 ,Interrupt ID285 Priority/Priority Byte Offset 285 " hexmask.long.byte 0x00 0.--7. 1. " INTID284 ,Interrupt ID284 Priority/Priority Byte Offset 284 " else rgroup.long 0x500++0x03 line.long 0x00 "GICD_IPRIORITYR64,Interrupt Priority Register 64" rgroup.long 0x504++0x03 line.long 0x00 "GICD_IPRIORITYR65,Interrupt Priority Register 65" rgroup.long 0x508++0x03 line.long 0x00 "GICD_IPRIORITYR66,Interrupt Priority Register 66" rgroup.long 0x50C++0x03 line.long 0x00 "GICD_IPRIORITYR67,Interrupt Priority Register 67" rgroup.long 0x510++0x03 line.long 0x00 "GICD_IPRIORITYR68,Interrupt Priority Register 68" rgroup.long 0x514++0x03 line.long 0x00 "GICD_IPRIORITYR69,Interrupt Priority Register 69" rgroup.long 0x518++0x03 line.long 0x00 "GICD_IPRIORITYR70,Interrupt Priority Register 70" rgroup.long 0x51C++0x03 line.long 0x00 "GICD_IPRIORITYR71,Interrupt Priority Register 71" endif if (((per.l(ad:(per.long(spr:0x31F30)&0xFFFC0000)+0x04))&0x0000001F)>=0x09) group.long 0x520++0x03 line.long 0x00 "GICD_IPRIORITYR72,Interrupt Priority Register 72" hexmask.long.byte 0x00 24.--31. 1. " INTID291 ,Interrupt ID291 Priority/Priority Byte Offset 291 " hexmask.long.byte 0x00 16.--23. 1. " INTID290 ,Interrupt ID290 Priority/Priority Byte Offset 290 " hexmask.long.byte 0x00 8.--15. 1. " INTID289 ,Interrupt ID289 Priority/Priority Byte Offset 289 " hexmask.long.byte 0x00 0.--7. 1. " INTID288 ,Interrupt ID288 Priority/Priority Byte Offset 288 " group.long 0x524++0x03 line.long 0x00 "GICD_IPRIORITYR73,Interrupt Priority Register 73" hexmask.long.byte 0x00 24.--31. 1. " INTID295 ,Interrupt ID295 Priority/Priority Byte Offset 295 " hexmask.long.byte 0x00 16.--23. 1. " INTID294 ,Interrupt ID294 Priority/Priority Byte Offset 294 " hexmask.long.byte 0x00 8.--15. 1. " INTID293 ,Interrupt ID293 Priority/Priority Byte Offset 293 " hexmask.long.byte 0x00 0.--7. 1. " INTID292 ,Interrupt ID292 Priority/Priority Byte Offset 292 " group.long 0x528++0x03 line.long 0x00 "GICD_IPRIORITYR74,Interrupt Priority Register 74" hexmask.long.byte 0x00 24.--31. 1. " INTID299 ,Interrupt ID299 Priority/Priority Byte Offset 299 " hexmask.long.byte 0x00 16.--23. 1. " INTID298 ,Interrupt ID298 Priority/Priority Byte Offset 298 " hexmask.long.byte 0x00 8.--15. 1. " INTID297 ,Interrupt ID297 Priority/Priority Byte Offset 297 " hexmask.long.byte 0x00 0.--7. 1. " INTID296 ,Interrupt ID296 Priority/Priority Byte Offset 296 " group.long 0x52C++0x03 line.long 0x00 "GICD_IPRIORITYR75,Interrupt Priority Register 75" hexmask.long.byte 0x00 24.--31. 1. " INTID303 ,Interrupt ID303 Priority/Priority Byte Offset 303 " hexmask.long.byte 0x00 16.--23. 1. " INTID302 ,Interrupt ID302 Priority/Priority Byte Offset 302 " hexmask.long.byte 0x00 8.--15. 1. " INTID301 ,Interrupt ID301 Priority/Priority Byte Offset 301 " hexmask.long.byte 0x00 0.--7. 1. " INTID300 ,Interrupt ID300 Priority/Priority Byte Offset 300 " group.long 0x530++0x03 line.long 0x00 "GICD_IPRIORITYR76,Interrupt Priority Register 76" hexmask.long.byte 0x00 24.--31. 1. " INTID307 ,Interrupt ID307 Priority/Priority Byte Offset 307 " hexmask.long.byte 0x00 16.--23. 1. " INTID306 ,Interrupt ID306 Priority/Priority Byte Offset 306 " hexmask.long.byte 0x00 8.--15. 1. " INTID305 ,Interrupt ID305 Priority/Priority Byte Offset 305 " hexmask.long.byte 0x00 0.--7. 1. " INTID304 ,Interrupt ID304 Priority/Priority Byte Offset 304 " group.long 0x534++0x03 line.long 0x00 "GICD_IPRIORITYR77,Interrupt Priority Register 77" hexmask.long.byte 0x00 24.--31. 1. " INTID311 ,Interrupt ID311 Priority/Priority Byte Offset 311 " hexmask.long.byte 0x00 16.--23. 1. " INTID310 ,Interrupt ID310 Priority/Priority Byte Offset 310 " hexmask.long.byte 0x00 8.--15. 1. " INTID309 ,Interrupt ID309 Priority/Priority Byte Offset 309 " hexmask.long.byte 0x00 0.--7. 1. " INTID308 ,Interrupt ID308 Priority/Priority Byte Offset 308 " group.long 0x538++0x03 line.long 0x00 "GICD_IPRIORITYR78,Interrupt Priority Register 78" hexmask.long.byte 0x00 24.--31. 1. " INTID315 ,Interrupt ID315 Priority/Priority Byte Offset 315 " hexmask.long.byte 0x00 16.--23. 1. " INTID314 ,Interrupt ID314 Priority/Priority Byte Offset 314 " hexmask.long.byte 0x00 8.--15. 1. " INTID313 ,Interrupt ID313 Priority/Priority Byte Offset 313 " hexmask.long.byte 0x00 0.--7. 1. " INTID312 ,Interrupt ID312 Priority/Priority Byte Offset 312 " group.long 0x53C++0x03 line.long 0x00 "GICD_IPRIORITYR79,Interrupt Priority Register 79" hexmask.long.byte 0x00 24.--31. 1. " INTID319 ,Interrupt ID319 Priority/Priority Byte Offset 319 " hexmask.long.byte 0x00 16.--23. 1. " INTID318 ,Interrupt ID318 Priority/Priority Byte Offset 318 " hexmask.long.byte 0x00 8.--15. 1. " INTID317 ,Interrupt ID317 Priority/Priority Byte Offset 317 " hexmask.long.byte 0x00 0.--7. 1. " INTID316 ,Interrupt ID316 Priority/Priority Byte Offset 316 " else rgroup.long 0x520++0x03 line.long 0x00 "GICD_IPRIORITYR72,Interrupt Priority Register 72" rgroup.long 0x524++0x03 line.long 0x00 "GICD_IPRIORITYR73,Interrupt Priority Register 73" rgroup.long 0x528++0x03 line.long 0x00 "GICD_IPRIORITYR74,Interrupt Priority Register 74" rgroup.long 0x52C++0x03 line.long 0x00 "GICD_IPRIORITYR75,Interrupt Priority Register 75" rgroup.long 0x530++0x03 line.long 0x00 "GICD_IPRIORITYR76,Interrupt Priority Register 76" rgroup.long 0x534++0x03 line.long 0x00 "GICD_IPRIORITYR77,Interrupt Priority Register 77" rgroup.long 0x538++0x03 line.long 0x00 "GICD_IPRIORITYR78,Interrupt Priority Register 78" rgroup.long 0x53C++0x03 line.long 0x00 "GICD_IPRIORITYR79,Interrupt Priority Register 79" endif if (((per.l(ad:(per.long(spr:0x31F30)&0xFFFC0000)+0x04))&0x0000001F)>=0x0A) group.long 0x540++0x03 line.long 0x00 "GICD_IPRIORITYR80,Interrupt Priority Register 80" hexmask.long.byte 0x00 24.--31. 1. " INTID323 ,Interrupt ID323 Priority/Priority Byte Offset 323 " hexmask.long.byte 0x00 16.--23. 1. " INTID322 ,Interrupt ID322 Priority/Priority Byte Offset 322 " hexmask.long.byte 0x00 8.--15. 1. " INTID321 ,Interrupt ID321 Priority/Priority Byte Offset 321 " hexmask.long.byte 0x00 0.--7. 1. " INTID320 ,Interrupt ID320 Priority/Priority Byte Offset 320 " group.long 0x544++0x03 line.long 0x00 "GICD_IPRIORITYR81,Interrupt Priority Register 81" hexmask.long.byte 0x00 24.--31. 1. " INTID327 ,Interrupt ID327 Priority/Priority Byte Offset 327 " hexmask.long.byte 0x00 16.--23. 1. " INTID326 ,Interrupt ID326 Priority/Priority Byte Offset 326 " hexmask.long.byte 0x00 8.--15. 1. " INTID325 ,Interrupt ID325 Priority/Priority Byte Offset 325 " hexmask.long.byte 0x00 0.--7. 1. " INTID324 ,Interrupt ID324 Priority/Priority Byte Offset 324 " group.long 0x548++0x03 line.long 0x00 "GICD_IPRIORITYR82,Interrupt Priority Register 82" hexmask.long.byte 0x00 24.--31. 1. " INTID331 ,Interrupt ID331 Priority/Priority Byte Offset 331 " hexmask.long.byte 0x00 16.--23. 1. " INTID330 ,Interrupt ID330 Priority/Priority Byte Offset 330 " hexmask.long.byte 0x00 8.--15. 1. " INTID329 ,Interrupt ID329 Priority/Priority Byte Offset 329 " hexmask.long.byte 0x00 0.--7. 1. " INTID328 ,Interrupt ID328 Priority/Priority Byte Offset 328 " group.long 0x54C++0x03 line.long 0x00 "GICD_IPRIORITYR83,Interrupt Priority Register 83" hexmask.long.byte 0x00 24.--31. 1. " INTID335 ,Interrupt ID335 Priority/Priority Byte Offset 335 " hexmask.long.byte 0x00 16.--23. 1. " INTID334 ,Interrupt ID334 Priority/Priority Byte Offset 334 " hexmask.long.byte 0x00 8.--15. 1. " INTID333 ,Interrupt ID333 Priority/Priority Byte Offset 333 " hexmask.long.byte 0x00 0.--7. 1. " INTID332 ,Interrupt ID332 Priority/Priority Byte Offset 332 " group.long 0x550++0x03 line.long 0x00 "GICD_IPRIORITYR84,Interrupt Priority Register 84" hexmask.long.byte 0x00 24.--31. 1. " INTID339 ,Interrupt ID339 Priority/Priority Byte Offset 339 " hexmask.long.byte 0x00 16.--23. 1. " INTID338 ,Interrupt ID338 Priority/Priority Byte Offset 338 " hexmask.long.byte 0x00 8.--15. 1. " INTID337 ,Interrupt ID337 Priority/Priority Byte Offset 337 " hexmask.long.byte 0x00 0.--7. 1. " INTID336 ,Interrupt ID336 Priority/Priority Byte Offset 336 " group.long 0x554++0x03 line.long 0x00 "GICD_IPRIORITYR85,Interrupt Priority Register 85" hexmask.long.byte 0x00 24.--31. 1. " INTID343 ,Interrupt ID343 Priority/Priority Byte Offset 343 " hexmask.long.byte 0x00 16.--23. 1. " INTID342 ,Interrupt ID342 Priority/Priority Byte Offset 342 " hexmask.long.byte 0x00 8.--15. 1. " INTID341 ,Interrupt ID341 Priority/Priority Byte Offset 341 " hexmask.long.byte 0x00 0.--7. 1. " INTID340 ,Interrupt ID340 Priority/Priority Byte Offset 340 " group.long 0x558++0x03 line.long 0x00 "GICD_IPRIORITYR86,Interrupt Priority Register 86" hexmask.long.byte 0x00 24.--31. 1. " INTID347 ,Interrupt ID347 Priority/Priority Byte Offset 347 " hexmask.long.byte 0x00 16.--23. 1. " INTID346 ,Interrupt ID346 Priority/Priority Byte Offset 346 " hexmask.long.byte 0x00 8.--15. 1. " INTID345 ,Interrupt ID345 Priority/Priority Byte Offset 345 " hexmask.long.byte 0x00 0.--7. 1. " INTID344 ,Interrupt ID344 Priority/Priority Byte Offset 344 " group.long 0x55C++0x03 line.long 0x00 "GICD_IPRIORITYR87,Interrupt Priority Register 87" hexmask.long.byte 0x00 24.--31. 1. " INTID351 ,Interrupt ID351 Priority/Priority Byte Offset 351 " hexmask.long.byte 0x00 16.--23. 1. " INTID350 ,Interrupt ID350 Priority/Priority Byte Offset 350 " hexmask.long.byte 0x00 8.--15. 1. " INTID349 ,Interrupt ID349 Priority/Priority Byte Offset 349 " hexmask.long.byte 0x00 0.--7. 1. " INTID348 ,Interrupt ID348 Priority/Priority Byte Offset 348 " else rgroup.long 0x540++0x03 line.long 0x00 "GICD_IPRIORITYR80,Interrupt Priority Register 80" rgroup.long 0x544++0x03 line.long 0x00 "GICD_IPRIORITYR81,Interrupt Priority Register 81" rgroup.long 0x548++0x03 line.long 0x00 "GICD_IPRIORITYR82,Interrupt Priority Register 82" rgroup.long 0x54C++0x03 line.long 0x00 "GICD_IPRIORITYR83,Interrupt Priority Register 83" rgroup.long 0x550++0x03 line.long 0x00 "GICD_IPRIORITYR84,Interrupt Priority Register 84" rgroup.long 0x554++0x03 line.long 0x00 "GICD_IPRIORITYR85,Interrupt Priority Register 85" rgroup.long 0x558++0x03 line.long 0x00 "GICD_IPRIORITYR86,Interrupt Priority Register 86" rgroup.long 0x55C++0x03 line.long 0x00 "GICD_IPRIORITYR87,Interrupt Priority Register 87" endif if (((per.l(ad:(per.long(spr:0x31F30)&0xFFFC0000)+0x04))&0x0000001F)>=0x0B) group.long 0x560++0x03 line.long 0x00 "GICD_IPRIORITYR88,Interrupt Priority Register 88" hexmask.long.byte 0x00 24.--31. 1. " INTID355 ,Interrupt ID355 Priority/Priority Byte Offset 355 " hexmask.long.byte 0x00 16.--23. 1. " INTID354 ,Interrupt ID354 Priority/Priority Byte Offset 354 " hexmask.long.byte 0x00 8.--15. 1. " INTID353 ,Interrupt ID353 Priority/Priority Byte Offset 353 " hexmask.long.byte 0x00 0.--7. 1. " INTID352 ,Interrupt ID352 Priority/Priority Byte Offset 352 " group.long 0x564++0x03 line.long 0x00 "GICD_IPRIORITYR89,Interrupt Priority Register 89" hexmask.long.byte 0x00 24.--31. 1. " INTID359 ,Interrupt ID359 Priority/Priority Byte Offset 359 " hexmask.long.byte 0x00 16.--23. 1. " INTID358 ,Interrupt ID358 Priority/Priority Byte Offset 358 " hexmask.long.byte 0x00 8.--15. 1. " INTID357 ,Interrupt ID357 Priority/Priority Byte Offset 357 " hexmask.long.byte 0x00 0.--7. 1. " INTID356 ,Interrupt ID356 Priority/Priority Byte Offset 356 " group.long 0x568++0x03 line.long 0x00 "GICD_IPRIORITYR90,Interrupt Priority Register 90" hexmask.long.byte 0x00 24.--31. 1. " INTID363 ,Interrupt ID363 Priority/Priority Byte Offset 363 " hexmask.long.byte 0x00 16.--23. 1. " INTID362 ,Interrupt ID362 Priority/Priority Byte Offset 362 " hexmask.long.byte 0x00 8.--15. 1. " INTID361 ,Interrupt ID361 Priority/Priority Byte Offset 361 " hexmask.long.byte 0x00 0.--7. 1. " INTID360 ,Interrupt ID360 Priority/Priority Byte Offset 360 " group.long 0x56C++0x03 line.long 0x00 "GICD_IPRIORITYR91,Interrupt Priority Register 91" hexmask.long.byte 0x00 24.--31. 1. " INTID367 ,Interrupt ID367 Priority/Priority Byte Offset 367 " hexmask.long.byte 0x00 16.--23. 1. " INTID366 ,Interrupt ID366 Priority/Priority Byte Offset 366 " hexmask.long.byte 0x00 8.--15. 1. " INTID365 ,Interrupt ID365 Priority/Priority Byte Offset 365 " hexmask.long.byte 0x00 0.--7. 1. " INTID364 ,Interrupt ID364 Priority/Priority Byte Offset 364 " group.long 0x570++0x03 line.long 0x00 "GICD_IPRIORITYR92,Interrupt Priority Register 92" hexmask.long.byte 0x00 24.--31. 1. " INTID371 ,Interrupt ID371 Priority/Priority Byte Offset 371 " hexmask.long.byte 0x00 16.--23. 1. " INTID370 ,Interrupt ID370 Priority/Priority Byte Offset 370 " hexmask.long.byte 0x00 8.--15. 1. " INTID369 ,Interrupt ID369 Priority/Priority Byte Offset 369 " hexmask.long.byte 0x00 0.--7. 1. " INTID368 ,Interrupt ID368 Priority/Priority Byte Offset 368 " group.long 0x574++0x03 line.long 0x00 "GICD_IPRIORITYR93,Interrupt Priority Register 93" hexmask.long.byte 0x00 24.--31. 1. " INTID375 ,Interrupt ID375 Priority/Priority Byte Offset 375 " hexmask.long.byte 0x00 16.--23. 1. " INTID374 ,Interrupt ID374 Priority/Priority Byte Offset 374 " hexmask.long.byte 0x00 8.--15. 1. " INTID373 ,Interrupt ID373 Priority/Priority Byte Offset 373 " hexmask.long.byte 0x00 0.--7. 1. " INTID372 ,Interrupt ID372 Priority/Priority Byte Offset 372 " group.long 0x578++0x03 line.long 0x00 "GICD_IPRIORITYR94,Interrupt Priority Register 94" hexmask.long.byte 0x00 24.--31. 1. " INTID379 ,Interrupt ID379 Priority/Priority Byte Offset 379 " hexmask.long.byte 0x00 16.--23. 1. " INTID378 ,Interrupt ID378 Priority/Priority Byte Offset 378 " hexmask.long.byte 0x00 8.--15. 1. " INTID377 ,Interrupt ID377 Priority/Priority Byte Offset 377 " hexmask.long.byte 0x00 0.--7. 1. " INTID376 ,Interrupt ID376 Priority/Priority Byte Offset 376 " group.long 0x57C++0x03 line.long 0x00 "GICD_IPRIORITYR95,Interrupt Priority Register 95" hexmask.long.byte 0x00 24.--31. 1. " INTID383 ,Interrupt ID383 Priority/Priority Byte Offset 383 " hexmask.long.byte 0x00 16.--23. 1. " INTID382 ,Interrupt ID382 Priority/Priority Byte Offset 382 " hexmask.long.byte 0x00 8.--15. 1. " INTID381 ,Interrupt ID381 Priority/Priority Byte Offset 381 " hexmask.long.byte 0x00 0.--7. 1. " INTID380 ,Interrupt ID380 Priority/Priority Byte Offset 380 " else rgroup.long 0x560++0x03 line.long 0x00 "GICD_IPRIORITYR88,Interrupt Priority Register 88" rgroup.long 0x564++0x03 line.long 0x00 "GICD_IPRIORITYR89,Interrupt Priority Register 89" rgroup.long 0x568++0x03 line.long 0x00 "GICD_IPRIORITYR90,Interrupt Priority Register 90" rgroup.long 0x56C++0x03 line.long 0x00 "GICD_IPRIORITYR91,Interrupt Priority Register 91" rgroup.long 0x570++0x03 line.long 0x00 "GICD_IPRIORITYR92,Interrupt Priority Register 92" rgroup.long 0x574++0x03 line.long 0x00 "GICD_IPRIORITYR93,Interrupt Priority Register 93" rgroup.long 0x578++0x03 line.long 0x00 "GICD_IPRIORITYR94,Interrupt Priority Register 94" rgroup.long 0x57C++0x03 line.long 0x00 "GICD_IPRIORITYR95,Interrupt Priority Register 95" endif if (((per.l(ad:(per.long(spr:0x31F30)&0xFFFC0000)+0x04))&0x0000001F)>=0x0C) group.long 0x580++0x03 line.long 0x00 "GICD_IPRIORITYR96,Interrupt Priority Register 96" hexmask.long.byte 0x00 24.--31. 1. " INTID387 ,Interrupt ID387 Priority/Priority Byte Offset 387 " hexmask.long.byte 0x00 16.--23. 1. " INTID386 ,Interrupt ID386 Priority/Priority Byte Offset 386 " hexmask.long.byte 0x00 8.--15. 1. " INTID385 ,Interrupt ID385 Priority/Priority Byte Offset 385 " hexmask.long.byte 0x00 0.--7. 1. " INTID384 ,Interrupt ID384 Priority/Priority Byte Offset 384 " group.long 0x584++0x03 line.long 0x00 "GICD_IPRIORITYR97,Interrupt Priority Register 97" hexmask.long.byte 0x00 24.--31. 1. " INTID391 ,Interrupt ID391 Priority/Priority Byte Offset 391 " hexmask.long.byte 0x00 16.--23. 1. " INTID390 ,Interrupt ID390 Priority/Priority Byte Offset 390 " hexmask.long.byte 0x00 8.--15. 1. " INTID389 ,Interrupt ID389 Priority/Priority Byte Offset 389 " hexmask.long.byte 0x00 0.--7. 1. " INTID388 ,Interrupt ID388 Priority/Priority Byte Offset 388 " group.long 0x588++0x03 line.long 0x00 "GICD_IPRIORITYR98,Interrupt Priority Register 98" hexmask.long.byte 0x00 24.--31. 1. " INTID395 ,Interrupt ID395 Priority/Priority Byte Offset 395 " hexmask.long.byte 0x00 16.--23. 1. " INTID394 ,Interrupt ID394 Priority/Priority Byte Offset 394 " hexmask.long.byte 0x00 8.--15. 1. " INTID393 ,Interrupt ID393 Priority/Priority Byte Offset 393 " hexmask.long.byte 0x00 0.--7. 1. " INTID392 ,Interrupt ID392 Priority/Priority Byte Offset 392 " group.long 0x58C++0x03 line.long 0x00 "GICD_IPRIORITYR99,Interrupt Priority Register 99" hexmask.long.byte 0x00 24.--31. 1. " INTID399 ,Interrupt ID399 Priority/Priority Byte Offset 399 " hexmask.long.byte 0x00 16.--23. 1. " INTID398 ,Interrupt ID398 Priority/Priority Byte Offset 398 " hexmask.long.byte 0x00 8.--15. 1. " INTID397 ,Interrupt ID397 Priority/Priority Byte Offset 397 " hexmask.long.byte 0x00 0.--7. 1. " INTID396 ,Interrupt ID396 Priority/Priority Byte Offset 396 " group.long 0x590++0x03 line.long 0x00 "GICD_IPRIORITYR100,Interrupt Priority Register 100" hexmask.long.byte 0x00 24.--31. 1. " INTID403 ,Interrupt ID403 Priority/Priority Byte Offset 403 " hexmask.long.byte 0x00 16.--23. 1. " INTID402 ,Interrupt ID402 Priority/Priority Byte Offset 402 " hexmask.long.byte 0x00 8.--15. 1. " INTID401 ,Interrupt ID401 Priority/Priority Byte Offset 401 " hexmask.long.byte 0x00 0.--7. 1. " INTID400 ,Interrupt ID400 Priority/Priority Byte Offset 400 " group.long 0x594++0x03 line.long 0x00 "GICD_IPRIORITYR101,Interrupt Priority Register 101" hexmask.long.byte 0x00 24.--31. 1. " INTID407 ,Interrupt ID407 Priority/Priority Byte Offset 407 " hexmask.long.byte 0x00 16.--23. 1. " INTID406 ,Interrupt ID406 Priority/Priority Byte Offset 406 " hexmask.long.byte 0x00 8.--15. 1. " INTID405 ,Interrupt ID405 Priority/Priority Byte Offset 405 " hexmask.long.byte 0x00 0.--7. 1. " INTID404 ,Interrupt ID404 Priority/Priority Byte Offset 404 " group.long 0x598++0x03 line.long 0x00 "GICD_IPRIORITYR102,Interrupt Priority Register 102" hexmask.long.byte 0x00 24.--31. 1. " INTID411 ,Interrupt ID411 Priority/Priority Byte Offset 411 " hexmask.long.byte 0x00 16.--23. 1. " INTID410 ,Interrupt ID410 Priority/Priority Byte Offset 410 " hexmask.long.byte 0x00 8.--15. 1. " INTID409 ,Interrupt ID409 Priority/Priority Byte Offset 409 " hexmask.long.byte 0x00 0.--7. 1. " INTID408 ,Interrupt ID408 Priority/Priority Byte Offset 408 " group.long 0x59C++0x03 line.long 0x00 "GICD_IPRIORITYR103,Interrupt Priority Register 103" hexmask.long.byte 0x00 24.--31. 1. " INTID415 ,Interrupt ID415 Priority/Priority Byte Offset 415 " hexmask.long.byte 0x00 16.--23. 1. " INTID414 ,Interrupt ID414 Priority/Priority Byte Offset 414 " hexmask.long.byte 0x00 8.--15. 1. " INTID413 ,Interrupt ID413 Priority/Priority Byte Offset 413 " hexmask.long.byte 0x00 0.--7. 1. " INTID412 ,Interrupt ID412 Priority/Priority Byte Offset 412 " else rgroup.long 0x580++0x03 line.long 0x00 "GICD_IPRIORITYR96,Interrupt Priority Register 96" rgroup.long 0x584++0x03 line.long 0x00 "GICD_IPRIORITYR97,Interrupt Priority Register 97" rgroup.long 0x588++0x03 line.long 0x00 "GICD_IPRIORITYR98,Interrupt Priority Register 98" rgroup.long 0x58C++0x03 line.long 0x00 "GICD_IPRIORITYR99,Interrupt Priority Register 99" rgroup.long 0x590++0x03 line.long 0x00 "GICD_IPRIORITYR100,Interrupt Priority Register 100" rgroup.long 0x594++0x03 line.long 0x00 "GICD_IPRIORITYR101,Interrupt Priority Register 101" rgroup.long 0x598++0x03 line.long 0x00 "GICD_IPRIORITYR102,Interrupt Priority Register 102" rgroup.long 0x59C++0x03 line.long 0x00 "GICD_IPRIORITYR103,Interrupt Priority Register 103" endif if (((per.l(ad:(per.long(spr:0x31F30)&0xFFFC0000)+0x04))&0x0000001F)>=0x0D) group.long 0x5A0++0x03 line.long 0x00 "GICD_IPRIORITYR104,Interrupt Priority Register 104" hexmask.long.byte 0x00 24.--31. 1. " INTID419 ,Interrupt ID419 Priority/Priority Byte Offset 419 " hexmask.long.byte 0x00 16.--23. 1. " INTID418 ,Interrupt ID418 Priority/Priority Byte Offset 418 " hexmask.long.byte 0x00 8.--15. 1. " INTID417 ,Interrupt ID417 Priority/Priority Byte Offset 417 " hexmask.long.byte 0x00 0.--7. 1. " INTID416 ,Interrupt ID416 Priority/Priority Byte Offset 416 " group.long 0x5A4++0x03 line.long 0x00 "GICD_IPRIORITYR105,Interrupt Priority Register 105" hexmask.long.byte 0x00 24.--31. 1. " INTID423 ,Interrupt ID423 Priority/Priority Byte Offset 423 " hexmask.long.byte 0x00 16.--23. 1. " INTID422 ,Interrupt ID422 Priority/Priority Byte Offset 422 " hexmask.long.byte 0x00 8.--15. 1. " INTID421 ,Interrupt ID421 Priority/Priority Byte Offset 421 " hexmask.long.byte 0x00 0.--7. 1. " INTID420 ,Interrupt ID420 Priority/Priority Byte Offset 420 " group.long 0x5A8++0x03 line.long 0x00 "GICD_IPRIORITYR106,Interrupt Priority Register 106" hexmask.long.byte 0x00 24.--31. 1. " INTID427 ,Interrupt ID427 Priority/Priority Byte Offset 427 " hexmask.long.byte 0x00 16.--23. 1. " INTID426 ,Interrupt ID426 Priority/Priority Byte Offset 426 " hexmask.long.byte 0x00 8.--15. 1. " INTID425 ,Interrupt ID425 Priority/Priority Byte Offset 425 " hexmask.long.byte 0x00 0.--7. 1. " INTID424 ,Interrupt ID424 Priority/Priority Byte Offset 424 " group.long 0x5AC++0x03 line.long 0x00 "GICD_IPRIORITYR107,Interrupt Priority Register 107" hexmask.long.byte 0x00 24.--31. 1. " INTID431 ,Interrupt ID431 Priority/Priority Byte Offset 431 " hexmask.long.byte 0x00 16.--23. 1. " INTID430 ,Interrupt ID430 Priority/Priority Byte Offset 430 " hexmask.long.byte 0x00 8.--15. 1. " INTID429 ,Interrupt ID429 Priority/Priority Byte Offset 429 " hexmask.long.byte 0x00 0.--7. 1. " INTID428 ,Interrupt ID428 Priority/Priority Byte Offset 428 " group.long 0x5B0++0x03 line.long 0x00 "GICD_IPRIORITYR108,Interrupt Priority Register 108" hexmask.long.byte 0x00 24.--31. 1. " INTID435 ,Interrupt ID435 Priority/Priority Byte Offset 435 " hexmask.long.byte 0x00 16.--23. 1. " INTID434 ,Interrupt ID434 Priority/Priority Byte Offset 434 " hexmask.long.byte 0x00 8.--15. 1. " INTID433 ,Interrupt ID433 Priority/Priority Byte Offset 433 " hexmask.long.byte 0x00 0.--7. 1. " INTID432 ,Interrupt ID432 Priority/Priority Byte Offset 432 " group.long 0x5B4++0x03 line.long 0x00 "GICD_IPRIORITYR109,Interrupt Priority Register 109" hexmask.long.byte 0x00 24.--31. 1. " INTID439 ,Interrupt ID439 Priority/Priority Byte Offset 439 " hexmask.long.byte 0x00 16.--23. 1. " INTID438 ,Interrupt ID438 Priority/Priority Byte Offset 438 " hexmask.long.byte 0x00 8.--15. 1. " INTID437 ,Interrupt ID437 Priority/Priority Byte Offset 437 " hexmask.long.byte 0x00 0.--7. 1. " INTID436 ,Interrupt ID436 Priority/Priority Byte Offset 436 " group.long 0x5B8++0x03 line.long 0x00 "GICD_IPRIORITYR110,Interrupt Priority Register 110" hexmask.long.byte 0x00 24.--31. 1. " INTID443 ,Interrupt ID443 Priority/Priority Byte Offset 443 " hexmask.long.byte 0x00 16.--23. 1. " INTID442 ,Interrupt ID442 Priority/Priority Byte Offset 442 " hexmask.long.byte 0x00 8.--15. 1. " INTID441 ,Interrupt ID441 Priority/Priority Byte Offset 441 " hexmask.long.byte 0x00 0.--7. 1. " INTID440 ,Interrupt ID440 Priority/Priority Byte Offset 440 " group.long 0x5BC++0x03 line.long 0x00 "GICD_IPRIORITYR111,Interrupt Priority Register 111" hexmask.long.byte 0x00 24.--31. 1. " INTID447 ,Interrupt ID447 Priority/Priority Byte Offset 447 " hexmask.long.byte 0x00 16.--23. 1. " INTID446 ,Interrupt ID446 Priority/Priority Byte Offset 446 " hexmask.long.byte 0x00 8.--15. 1. " INTID445 ,Interrupt ID445 Priority/Priority Byte Offset 445 " hexmask.long.byte 0x00 0.--7. 1. " INTID444 ,Interrupt ID444 Priority/Priority Byte Offset 444 " else rgroup.long 0x5A0++0x03 line.long 0x00 "GICD_IPRIORITYR104,Interrupt Priority Register 104" rgroup.long 0x5A4++0x03 line.long 0x00 "GICD_IPRIORITYR105,Interrupt Priority Register 105" rgroup.long 0x5A8++0x03 line.long 0x00 "GICD_IPRIORITYR106,Interrupt Priority Register 106" rgroup.long 0x5AC++0x03 line.long 0x00 "GICD_IPRIORITYR107,Interrupt Priority Register 107" rgroup.long 0x5B0++0x03 line.long 0x00 "GICD_IPRIORITYR108,Interrupt Priority Register 108" rgroup.long 0x5B4++0x03 line.long 0x00 "GICD_IPRIORITYR109,Interrupt Priority Register 109" rgroup.long 0x5B8++0x03 line.long 0x00 "GICD_IPRIORITYR110,Interrupt Priority Register 110" rgroup.long 0x5BC++0x03 line.long 0x00 "GICD_IPRIORITYR111,Interrupt Priority Register 111" endif if (((per.l(ad:(per.long(spr:0x31F30)&0xFFFC0000)+0x04))&0x0000001F)>=0x0E) group.long 0x5C0++0x03 line.long 0x00 "GICD_IPRIORITYR112,Interrupt Priority Register 112" hexmask.long.byte 0x00 24.--31. 1. " INTID451 ,Interrupt ID451 Priority/Priority Byte Offset 451 " hexmask.long.byte 0x00 16.--23. 1. " INTID450 ,Interrupt ID450 Priority/Priority Byte Offset 450 " hexmask.long.byte 0x00 8.--15. 1. " INTID449 ,Interrupt ID449 Priority/Priority Byte Offset 449 " hexmask.long.byte 0x00 0.--7. 1. " INTID448 ,Interrupt ID448 Priority/Priority Byte Offset 448 " group.long 0x5C4++0x03 line.long 0x00 "GICD_IPRIORITYR113,Interrupt Priority Register 113" hexmask.long.byte 0x00 24.--31. 1. " INTID455 ,Interrupt ID455 Priority/Priority Byte Offset 455 " hexmask.long.byte 0x00 16.--23. 1. " INTID454 ,Interrupt ID454 Priority/Priority Byte Offset 454 " hexmask.long.byte 0x00 8.--15. 1. " INTID453 ,Interrupt ID453 Priority/Priority Byte Offset 453 " hexmask.long.byte 0x00 0.--7. 1. " INTID452 ,Interrupt ID452 Priority/Priority Byte Offset 452 " group.long 0x5C8++0x03 line.long 0x00 "GICD_IPRIORITYR114,Interrupt Priority Register 114" hexmask.long.byte 0x00 24.--31. 1. " INTID459 ,Interrupt ID459 Priority/Priority Byte Offset 459 " hexmask.long.byte 0x00 16.--23. 1. " INTID458 ,Interrupt ID458 Priority/Priority Byte Offset 458 " hexmask.long.byte 0x00 8.--15. 1. " INTID457 ,Interrupt ID457 Priority/Priority Byte Offset 457 " hexmask.long.byte 0x00 0.--7. 1. " INTID456 ,Interrupt ID456 Priority/Priority Byte Offset 456 " group.long 0x5CC++0x03 line.long 0x00 "GICD_IPRIORITYR115,Interrupt Priority Register 115" hexmask.long.byte 0x00 24.--31. 1. " INTID463 ,Interrupt ID463 Priority/Priority Byte Offset 463 " hexmask.long.byte 0x00 16.--23. 1. " INTID462 ,Interrupt ID462 Priority/Priority Byte Offset 462 " hexmask.long.byte 0x00 8.--15. 1. " INTID461 ,Interrupt ID461 Priority/Priority Byte Offset 461 " hexmask.long.byte 0x00 0.--7. 1. " INTID460 ,Interrupt ID460 Priority/Priority Byte Offset 460 " group.long 0x5D0++0x03 line.long 0x00 "GICD_IPRIORITYR116,Interrupt Priority Register 116" hexmask.long.byte 0x00 24.--31. 1. " INTID467 ,Interrupt ID467 Priority/Priority Byte Offset 467 " hexmask.long.byte 0x00 16.--23. 1. " INTID466 ,Interrupt ID466 Priority/Priority Byte Offset 466 " hexmask.long.byte 0x00 8.--15. 1. " INTID465 ,Interrupt ID465 Priority/Priority Byte Offset 465 " hexmask.long.byte 0x00 0.--7. 1. " INTID464 ,Interrupt ID464 Priority/Priority Byte Offset 464 " group.long 0x5D4++0x03 line.long 0x00 "GICD_IPRIORITYR117,Interrupt Priority Register 117" hexmask.long.byte 0x00 24.--31. 1. " INTID471 ,Interrupt ID471 Priority/Priority Byte Offset 471 " hexmask.long.byte 0x00 16.--23. 1. " INTID470 ,Interrupt ID470 Priority/Priority Byte Offset 470 " hexmask.long.byte 0x00 8.--15. 1. " INTID469 ,Interrupt ID469 Priority/Priority Byte Offset 469 " hexmask.long.byte 0x00 0.--7. 1. " INTID468 ,Interrupt ID468 Priority/Priority Byte Offset 468 " group.long 0x5D8++0x03 line.long 0x00 "GICD_IPRIORITYR118,Interrupt Priority Register 118" hexmask.long.byte 0x00 24.--31. 1. " INTID475 ,Interrupt ID475 Priority/Priority Byte Offset 475 " hexmask.long.byte 0x00 16.--23. 1. " INTID474 ,Interrupt ID474 Priority/Priority Byte Offset 474 " hexmask.long.byte 0x00 8.--15. 1. " INTID473 ,Interrupt ID473 Priority/Priority Byte Offset 473 " hexmask.long.byte 0x00 0.--7. 1. " INTID472 ,Interrupt ID472 Priority/Priority Byte Offset 472 " group.long 0x5DC++0x03 line.long 0x00 "GICD_IPRIORITYR119,Interrupt Priority Register 119" hexmask.long.byte 0x00 24.--31. 1. " INTID479 ,Interrupt ID479 Priority/Priority Byte Offset 479 " hexmask.long.byte 0x00 16.--23. 1. " INTID478 ,Interrupt ID478 Priority/Priority Byte Offset 478 " hexmask.long.byte 0x00 8.--15. 1. " INTID477 ,Interrupt ID477 Priority/Priority Byte Offset 477 " hexmask.long.byte 0x00 0.--7. 1. " INTID476 ,Interrupt ID476 Priority/Priority Byte Offset 476 " else rgroup.long 0x5C0++0x03 line.long 0x00 "GICD_IPRIORITYR112,Interrupt Priority Register 112" rgroup.long 0x5C4++0x03 line.long 0x00 "GICD_IPRIORITYR113,Interrupt Priority Register 113" rgroup.long 0x5C8++0x03 line.long 0x00 "GICD_IPRIORITYR114,Interrupt Priority Register 114" rgroup.long 0x5CC++0x03 line.long 0x00 "GICD_IPRIORITYR115,Interrupt Priority Register 115" rgroup.long 0x5D0++0x03 line.long 0x00 "GICD_IPRIORITYR116,Interrupt Priority Register 116" rgroup.long 0x5D4++0x03 line.long 0x00 "GICD_IPRIORITYR117,Interrupt Priority Register 117" rgroup.long 0x5D8++0x03 line.long 0x00 "GICD_IPRIORITYR118,Interrupt Priority Register 118" rgroup.long 0x5DC++0x03 line.long 0x00 "GICD_IPRIORITYR119,Interrupt Priority Register 119" endif if (((per.l(ad:(per.long(spr:0x31F30)&0xFFFC0000)+0x04))&0x0000001F)>=0x0F) group.long 0x5E0++0x03 line.long 0x00 "GICD_IPRIORITYR120,Interrupt Priority Register 120" hexmask.long.byte 0x00 24.--31. 1. " INTID483 ,Interrupt ID483 Priority/Priority Byte Offset 483 " hexmask.long.byte 0x00 16.--23. 1. " INTID482 ,Interrupt ID482 Priority/Priority Byte Offset 482 " hexmask.long.byte 0x00 8.--15. 1. " INTID481 ,Interrupt ID481 Priority/Priority Byte Offset 481 " hexmask.long.byte 0x00 0.--7. 1. " INTID480 ,Interrupt ID480 Priority/Priority Byte Offset 480 " group.long 0x5E4++0x03 line.long 0x00 "GICD_IPRIORITYR121,Interrupt Priority Register 121" hexmask.long.byte 0x00 24.--31. 1. " INTID487 ,Interrupt ID487 Priority/Priority Byte Offset 487 " hexmask.long.byte 0x00 16.--23. 1. " INTID486 ,Interrupt ID486 Priority/Priority Byte Offset 486 " hexmask.long.byte 0x00 8.--15. 1. " INTID485 ,Interrupt ID485 Priority/Priority Byte Offset 485 " hexmask.long.byte 0x00 0.--7. 1. " INTID484 ,Interrupt ID484 Priority/Priority Byte Offset 484 " group.long 0x5E8++0x03 line.long 0x00 "GICD_IPRIORITYR122,Interrupt Priority Register 122" hexmask.long.byte 0x00 24.--31. 1. " INTID491 ,Interrupt ID491 Priority/Priority Byte Offset 491 " hexmask.long.byte 0x00 16.--23. 1. " INTID490 ,Interrupt ID490 Priority/Priority Byte Offset 490 " hexmask.long.byte 0x00 8.--15. 1. " INTID489 ,Interrupt ID489 Priority/Priority Byte Offset 489 " hexmask.long.byte 0x00 0.--7. 1. " INTID488 ,Interrupt ID488 Priority/Priority Byte Offset 488 " group.long 0x5EC++0x03 line.long 0x00 "GICD_IPRIORITYR123,Interrupt Priority Register 123" hexmask.long.byte 0x00 24.--31. 1. " INTID495 ,Interrupt ID495 Priority/Priority Byte Offset 495 " hexmask.long.byte 0x00 16.--23. 1. " INTID494 ,Interrupt ID494 Priority/Priority Byte Offset 494 " hexmask.long.byte 0x00 8.--15. 1. " INTID493 ,Interrupt ID493 Priority/Priority Byte Offset 493 " hexmask.long.byte 0x00 0.--7. 1. " INTID492 ,Interrupt ID492 Priority/Priority Byte Offset 492 " group.long 0x5F0++0x03 line.long 0x00 "GICD_IPRIORITYR124,Interrupt Priority Register 124" hexmask.long.byte 0x00 24.--31. 1. " INTID499 ,Interrupt ID499 Priority/Priority Byte Offset 499 " hexmask.long.byte 0x00 16.--23. 1. " INTID498 ,Interrupt ID498 Priority/Priority Byte Offset 498 " hexmask.long.byte 0x00 8.--15. 1. " INTID497 ,Interrupt ID497 Priority/Priority Byte Offset 497 " hexmask.long.byte 0x00 0.--7. 1. " INTID496 ,Interrupt ID496 Priority/Priority Byte Offset 496 " group.long 0x5F4++0x03 line.long 0x00 "GICD_IPRIORITYR125,Interrupt Priority Register 125" hexmask.long.byte 0x00 24.--31. 1. " INTID503 ,Interrupt ID503 Priority/Priority Byte Offset 503 " hexmask.long.byte 0x00 16.--23. 1. " INTID502 ,Interrupt ID502 Priority/Priority Byte Offset 502 " hexmask.long.byte 0x00 8.--15. 1. " INTID501 ,Interrupt ID501 Priority/Priority Byte Offset 501 " hexmask.long.byte 0x00 0.--7. 1. " INTID500 ,Interrupt ID500 Priority/Priority Byte Offset 500 " group.long 0x5F8++0x03 line.long 0x00 "GICD_IPRIORITYR126,Interrupt Priority Register 126" hexmask.long.byte 0x00 24.--31. 1. " INTID507 ,Interrupt ID507 Priority/Priority Byte Offset 507 " hexmask.long.byte 0x00 16.--23. 1. " INTID506 ,Interrupt ID506 Priority/Priority Byte Offset 506 " hexmask.long.byte 0x00 8.--15. 1. " INTID505 ,Interrupt ID505 Priority/Priority Byte Offset 505 " hexmask.long.byte 0x00 0.--7. 1. " INTID504 ,Interrupt ID504 Priority/Priority Byte Offset 504 " group.long 0x5FC++0x03 line.long 0x00 "GICD_IPRIORITYR127,Interrupt Priority Register 127" hexmask.long.byte 0x00 24.--31. 1. " INTID511 ,Interrupt ID511 Priority/Priority Byte Offset 511 " hexmask.long.byte 0x00 16.--23. 1. " INTID510 ,Interrupt ID510 Priority/Priority Byte Offset 510 " hexmask.long.byte 0x00 8.--15. 1. " INTID509 ,Interrupt ID509 Priority/Priority Byte Offset 509 " hexmask.long.byte 0x00 0.--7. 1. " INTID508 ,Interrupt ID508 Priority/Priority Byte Offset 508 " else rgroup.long 0x5E0++0x03 line.long 0x00 "GICD_IPRIORITYR120,Interrupt Priority Register 120" rgroup.long 0x5E4++0x03 line.long 0x00 "GICD_IPRIORITYR121,Interrupt Priority Register 121" rgroup.long 0x5E8++0x03 line.long 0x00 "GICD_IPRIORITYR122,Interrupt Priority Register 122" rgroup.long 0x5EC++0x03 line.long 0x00 "GICD_IPRIORITYR123,Interrupt Priority Register 123" rgroup.long 0x5F0++0x03 line.long 0x00 "GICD_IPRIORITYR124,Interrupt Priority Register 124" rgroup.long 0x5F4++0x03 line.long 0x00 "GICD_IPRIORITYR125,Interrupt Priority Register 125" rgroup.long 0x5F8++0x03 line.long 0x00 "GICD_IPRIORITYR126,Interrupt Priority Register 126" rgroup.long 0x5FC++0x03 line.long 0x00 "GICD_IPRIORITYR127,Interrupt Priority Register 127" endif if (((per.l(ad:(per.long(spr:0x31F30)&0xFFFC0000)+0x04))&0x0000001F)>=0x10) group.long 0x600++0x03 line.long 0x00 "GICD_IPRIORITYR128,Interrupt Priority Register 128" hexmask.long.byte 0x00 24.--31. 1. " INTID515 ,Interrupt ID515 Priority/Priority Byte Offset 515 " hexmask.long.byte 0x00 16.--23. 1. " INTID514 ,Interrupt ID514 Priority/Priority Byte Offset 514 " hexmask.long.byte 0x00 8.--15. 1. " INTID513 ,Interrupt ID513 Priority/Priority Byte Offset 513 " hexmask.long.byte 0x00 0.--7. 1. " INTID512 ,Interrupt ID512 Priority/Priority Byte Offset 512 " group.long 0x604++0x03 line.long 0x00 "GICD_IPRIORITYR129,Interrupt Priority Register 129" hexmask.long.byte 0x00 24.--31. 1. " INTID519 ,Interrupt ID519 Priority/Priority Byte Offset 519 " hexmask.long.byte 0x00 16.--23. 1. " INTID518 ,Interrupt ID518 Priority/Priority Byte Offset 518 " hexmask.long.byte 0x00 8.--15. 1. " INTID517 ,Interrupt ID517 Priority/Priority Byte Offset 517 " hexmask.long.byte 0x00 0.--7. 1. " INTID516 ,Interrupt ID516 Priority/Priority Byte Offset 516 " group.long 0x608++0x03 line.long 0x00 "GICD_IPRIORITYR130,Interrupt Priority Register 130" hexmask.long.byte 0x00 24.--31. 1. " INTID523 ,Interrupt ID523 Priority/Priority Byte Offset 523 " hexmask.long.byte 0x00 16.--23. 1. " INTID522 ,Interrupt ID522 Priority/Priority Byte Offset 522 " hexmask.long.byte 0x00 8.--15. 1. " INTID521 ,Interrupt ID521 Priority/Priority Byte Offset 521 " hexmask.long.byte 0x00 0.--7. 1. " INTID520 ,Interrupt ID520 Priority/Priority Byte Offset 520 " group.long 0x60C++0x03 line.long 0x00 "GICD_IPRIORITYR131,Interrupt Priority Register 131" hexmask.long.byte 0x00 24.--31. 1. " INTID527 ,Interrupt ID527 Priority/Priority Byte Offset 527 " hexmask.long.byte 0x00 16.--23. 1. " INTID526 ,Interrupt ID526 Priority/Priority Byte Offset 526 " hexmask.long.byte 0x00 8.--15. 1. " INTID525 ,Interrupt ID525 Priority/Priority Byte Offset 525 " hexmask.long.byte 0x00 0.--7. 1. " INTID524 ,Interrupt ID524 Priority/Priority Byte Offset 524 " group.long 0x610++0x03 line.long 0x00 "GICD_IPRIORITYR132,Interrupt Priority Register 132" hexmask.long.byte 0x00 24.--31. 1. " INTID531 ,Interrupt ID531 Priority/Priority Byte Offset 531 " hexmask.long.byte 0x00 16.--23. 1. " INTID530 ,Interrupt ID530 Priority/Priority Byte Offset 530 " hexmask.long.byte 0x00 8.--15. 1. " INTID529 ,Interrupt ID529 Priority/Priority Byte Offset 529 " hexmask.long.byte 0x00 0.--7. 1. " INTID528 ,Interrupt ID528 Priority/Priority Byte Offset 528 " group.long 0x614++0x03 line.long 0x00 "GICD_IPRIORITYR133,Interrupt Priority Register 133" hexmask.long.byte 0x00 24.--31. 1. " INTID535 ,Interrupt ID535 Priority/Priority Byte Offset 535 " hexmask.long.byte 0x00 16.--23. 1. " INTID534 ,Interrupt ID534 Priority/Priority Byte Offset 534 " hexmask.long.byte 0x00 8.--15. 1. " INTID533 ,Interrupt ID533 Priority/Priority Byte Offset 533 " hexmask.long.byte 0x00 0.--7. 1. " INTID532 ,Interrupt ID532 Priority/Priority Byte Offset 532 " group.long 0x618++0x03 line.long 0x00 "GICD_IPRIORITYR134,Interrupt Priority Register 134" hexmask.long.byte 0x00 24.--31. 1. " INTID539 ,Interrupt ID539 Priority/Priority Byte Offset 539 " hexmask.long.byte 0x00 16.--23. 1. " INTID538 ,Interrupt ID538 Priority/Priority Byte Offset 538 " hexmask.long.byte 0x00 8.--15. 1. " INTID537 ,Interrupt ID537 Priority/Priority Byte Offset 537 " hexmask.long.byte 0x00 0.--7. 1. " INTID536 ,Interrupt ID536 Priority/Priority Byte Offset 536 " group.long 0x61C++0x03 line.long 0x00 "GICD_IPRIORITYR135,Interrupt Priority Register 135" hexmask.long.byte 0x00 24.--31. 1. " INTID543 ,Interrupt ID543 Priority/Priority Byte Offset 543 " hexmask.long.byte 0x00 16.--23. 1. " INTID542 ,Interrupt ID542 Priority/Priority Byte Offset 542 " hexmask.long.byte 0x00 8.--15. 1. " INTID541 ,Interrupt ID541 Priority/Priority Byte Offset 541 " hexmask.long.byte 0x00 0.--7. 1. " INTID540 ,Interrupt ID540 Priority/Priority Byte Offset 540 " else rgroup.long 0x600++0x03 line.long 0x00 "GICD_IPRIORITYR128,Interrupt Priority Register 128" rgroup.long 0x604++0x03 line.long 0x00 "GICD_IPRIORITYR129,Interrupt Priority Register 129" rgroup.long 0x608++0x03 line.long 0x00 "GICD_IPRIORITYR130,Interrupt Priority Register 130" rgroup.long 0x60C++0x03 line.long 0x00 "GICD_IPRIORITYR131,Interrupt Priority Register 131" rgroup.long 0x610++0x03 line.long 0x00 "GICD_IPRIORITYR132,Interrupt Priority Register 132" rgroup.long 0x614++0x03 line.long 0x00 "GICD_IPRIORITYR133,Interrupt Priority Register 133" rgroup.long 0x618++0x03 line.long 0x00 "GICD_IPRIORITYR134,Interrupt Priority Register 134" rgroup.long 0x61C++0x03 line.long 0x00 "GICD_IPRIORITYR135,Interrupt Priority Register 135" endif if (((per.l(ad:(per.long(spr:0x31F30)&0xFFFC0000)+0x04))&0x0000001F)>=0x11) group.long 0x620++0x03 line.long 0x00 "GICD_IPRIORITYR136,Interrupt Priority Register 136" hexmask.long.byte 0x00 24.--31. 1. " INTID547 ,Interrupt ID547 Priority/Priority Byte Offset 547 " hexmask.long.byte 0x00 16.--23. 1. " INTID546 ,Interrupt ID546 Priority/Priority Byte Offset 546 " hexmask.long.byte 0x00 8.--15. 1. " INTID545 ,Interrupt ID545 Priority/Priority Byte Offset 545 " hexmask.long.byte 0x00 0.--7. 1. " INTID544 ,Interrupt ID544 Priority/Priority Byte Offset 544 " group.long 0x624++0x03 line.long 0x00 "GICD_IPRIORITYR137,Interrupt Priority Register 137" hexmask.long.byte 0x00 24.--31. 1. " INTID551 ,Interrupt ID551 Priority/Priority Byte Offset 551 " hexmask.long.byte 0x00 16.--23. 1. " INTID550 ,Interrupt ID550 Priority/Priority Byte Offset 550 " hexmask.long.byte 0x00 8.--15. 1. " INTID549 ,Interrupt ID549 Priority/Priority Byte Offset 549 " hexmask.long.byte 0x00 0.--7. 1. " INTID548 ,Interrupt ID548 Priority/Priority Byte Offset 548 " group.long 0x628++0x03 line.long 0x00 "GICD_IPRIORITYR138,Interrupt Priority Register 138" hexmask.long.byte 0x00 24.--31. 1. " INTID555 ,Interrupt ID555 Priority/Priority Byte Offset 555 " hexmask.long.byte 0x00 16.--23. 1. " INTID554 ,Interrupt ID554 Priority/Priority Byte Offset 554 " hexmask.long.byte 0x00 8.--15. 1. " INTID553 ,Interrupt ID553 Priority/Priority Byte Offset 553 " hexmask.long.byte 0x00 0.--7. 1. " INTID552 ,Interrupt ID552 Priority/Priority Byte Offset 552 " group.long 0x62C++0x03 line.long 0x00 "GICD_IPRIORITYR139,Interrupt Priority Register 139" hexmask.long.byte 0x00 24.--31. 1. " INTID559 ,Interrupt ID559 Priority/Priority Byte Offset 559 " hexmask.long.byte 0x00 16.--23. 1. " INTID558 ,Interrupt ID558 Priority/Priority Byte Offset 558 " hexmask.long.byte 0x00 8.--15. 1. " INTID557 ,Interrupt ID557 Priority/Priority Byte Offset 557 " hexmask.long.byte 0x00 0.--7. 1. " INTID556 ,Interrupt ID556 Priority/Priority Byte Offset 556 " group.long 0x630++0x03 line.long 0x00 "GICD_IPRIORITYR140,Interrupt Priority Register 140" hexmask.long.byte 0x00 24.--31. 1. " INTID563 ,Interrupt ID563 Priority/Priority Byte Offset 563 " hexmask.long.byte 0x00 16.--23. 1. " INTID562 ,Interrupt ID562 Priority/Priority Byte Offset 562 " hexmask.long.byte 0x00 8.--15. 1. " INTID561 ,Interrupt ID561 Priority/Priority Byte Offset 561 " hexmask.long.byte 0x00 0.--7. 1. " INTID560 ,Interrupt ID560 Priority/Priority Byte Offset 560 " group.long 0x634++0x03 line.long 0x00 "GICD_IPRIORITYR141,Interrupt Priority Register 141" hexmask.long.byte 0x00 24.--31. 1. " INTID567 ,Interrupt ID567 Priority/Priority Byte Offset 567 " hexmask.long.byte 0x00 16.--23. 1. " INTID566 ,Interrupt ID566 Priority/Priority Byte Offset 566 " hexmask.long.byte 0x00 8.--15. 1. " INTID565 ,Interrupt ID565 Priority/Priority Byte Offset 565 " hexmask.long.byte 0x00 0.--7. 1. " INTID564 ,Interrupt ID564 Priority/Priority Byte Offset 564 " group.long 0x638++0x03 line.long 0x00 "GICD_IPRIORITYR142,Interrupt Priority Register 142" hexmask.long.byte 0x00 24.--31. 1. " INTID571 ,Interrupt ID571 Priority/Priority Byte Offset 571 " hexmask.long.byte 0x00 16.--23. 1. " INTID570 ,Interrupt ID570 Priority/Priority Byte Offset 570 " hexmask.long.byte 0x00 8.--15. 1. " INTID569 ,Interrupt ID569 Priority/Priority Byte Offset 569 " hexmask.long.byte 0x00 0.--7. 1. " INTID568 ,Interrupt ID568 Priority/Priority Byte Offset 568 " group.long 0x63C++0x03 line.long 0x00 "GICD_IPRIORITYR143,Interrupt Priority Register 143" hexmask.long.byte 0x00 24.--31. 1. " INTID575 ,Interrupt ID575 Priority/Priority Byte Offset 575 " hexmask.long.byte 0x00 16.--23. 1. " INTID574 ,Interrupt ID574 Priority/Priority Byte Offset 574 " hexmask.long.byte 0x00 8.--15. 1. " INTID573 ,Interrupt ID573 Priority/Priority Byte Offset 573 " hexmask.long.byte 0x00 0.--7. 1. " INTID572 ,Interrupt ID572 Priority/Priority Byte Offset 572 " else rgroup.long 0x620++0x03 line.long 0x00 "GICD_IPRIORITYR136,Interrupt Priority Register 136" rgroup.long 0x624++0x03 line.long 0x00 "GICD_IPRIORITYR137,Interrupt Priority Register 137" rgroup.long 0x628++0x03 line.long 0x00 "GICD_IPRIORITYR138,Interrupt Priority Register 138" rgroup.long 0x62C++0x03 line.long 0x00 "GICD_IPRIORITYR139,Interrupt Priority Register 139" rgroup.long 0x630++0x03 line.long 0x00 "GICD_IPRIORITYR140,Interrupt Priority Register 140" rgroup.long 0x634++0x03 line.long 0x00 "GICD_IPRIORITYR141,Interrupt Priority Register 141" rgroup.long 0x638++0x03 line.long 0x00 "GICD_IPRIORITYR142,Interrupt Priority Register 142" rgroup.long 0x63C++0x03 line.long 0x00 "GICD_IPRIORITYR143,Interrupt Priority Register 143" endif if (((per.l(ad:(per.long(spr:0x31F30)&0xFFFC0000)+0x04))&0x0000001F)>=0x12) group.long 0x640++0x03 line.long 0x00 "GICD_IPRIORITYR144,Interrupt Priority Register 144" hexmask.long.byte 0x00 24.--31. 1. " INTID579 ,Interrupt ID579 Priority/Priority Byte Offset 579 " hexmask.long.byte 0x00 16.--23. 1. " INTID578 ,Interrupt ID578 Priority/Priority Byte Offset 578 " hexmask.long.byte 0x00 8.--15. 1. " INTID577 ,Interrupt ID577 Priority/Priority Byte Offset 577 " hexmask.long.byte 0x00 0.--7. 1. " INTID576 ,Interrupt ID576 Priority/Priority Byte Offset 576 " group.long 0x644++0x03 line.long 0x00 "GICD_IPRIORITYR145,Interrupt Priority Register 145" hexmask.long.byte 0x00 24.--31. 1. " INTID583 ,Interrupt ID583 Priority/Priority Byte Offset 583 " hexmask.long.byte 0x00 16.--23. 1. " INTID582 ,Interrupt ID582 Priority/Priority Byte Offset 582 " hexmask.long.byte 0x00 8.--15. 1. " INTID581 ,Interrupt ID581 Priority/Priority Byte Offset 581 " hexmask.long.byte 0x00 0.--7. 1. " INTID580 ,Interrupt ID580 Priority/Priority Byte Offset 580 " group.long 0x648++0x03 line.long 0x00 "GICD_IPRIORITYR146,Interrupt Priority Register 146" hexmask.long.byte 0x00 24.--31. 1. " INTID587 ,Interrupt ID587 Priority/Priority Byte Offset 587 " hexmask.long.byte 0x00 16.--23. 1. " INTID586 ,Interrupt ID586 Priority/Priority Byte Offset 586 " hexmask.long.byte 0x00 8.--15. 1. " INTID585 ,Interrupt ID585 Priority/Priority Byte Offset 585 " hexmask.long.byte 0x00 0.--7. 1. " INTID584 ,Interrupt ID584 Priority/Priority Byte Offset 584 " group.long 0x64C++0x03 line.long 0x00 "GICD_IPRIORITYR147,Interrupt Priority Register 147" hexmask.long.byte 0x00 24.--31. 1. " INTID591 ,Interrupt ID591 Priority/Priority Byte Offset 591 " hexmask.long.byte 0x00 16.--23. 1. " INTID590 ,Interrupt ID590 Priority/Priority Byte Offset 590 " hexmask.long.byte 0x00 8.--15. 1. " INTID589 ,Interrupt ID589 Priority/Priority Byte Offset 589 " hexmask.long.byte 0x00 0.--7. 1. " INTID588 ,Interrupt ID588 Priority/Priority Byte Offset 588 " group.long 0x650++0x03 line.long 0x00 "GICD_IPRIORITYR148,Interrupt Priority Register 148" hexmask.long.byte 0x00 24.--31. 1. " INTID595 ,Interrupt ID595 Priority/Priority Byte Offset 595 " hexmask.long.byte 0x00 16.--23. 1. " INTID594 ,Interrupt ID594 Priority/Priority Byte Offset 594 " hexmask.long.byte 0x00 8.--15. 1. " INTID593 ,Interrupt ID593 Priority/Priority Byte Offset 593 " hexmask.long.byte 0x00 0.--7. 1. " INTID592 ,Interrupt ID592 Priority/Priority Byte Offset 592 " group.long 0x654++0x03 line.long 0x00 "GICD_IPRIORITYR149,Interrupt Priority Register 149" hexmask.long.byte 0x00 24.--31. 1. " INTID599 ,Interrupt ID599 Priority/Priority Byte Offset 599 " hexmask.long.byte 0x00 16.--23. 1. " INTID598 ,Interrupt ID598 Priority/Priority Byte Offset 598 " hexmask.long.byte 0x00 8.--15. 1. " INTID597 ,Interrupt ID597 Priority/Priority Byte Offset 597 " hexmask.long.byte 0x00 0.--7. 1. " INTID596 ,Interrupt ID596 Priority/Priority Byte Offset 596 " group.long 0x658++0x03 line.long 0x00 "GICD_IPRIORITYR150,Interrupt Priority Register 150" hexmask.long.byte 0x00 24.--31. 1. " INTID603 ,Interrupt ID603 Priority/Priority Byte Offset 603 " hexmask.long.byte 0x00 16.--23. 1. " INTID602 ,Interrupt ID602 Priority/Priority Byte Offset 602 " hexmask.long.byte 0x00 8.--15. 1. " INTID601 ,Interrupt ID601 Priority/Priority Byte Offset 601 " hexmask.long.byte 0x00 0.--7. 1. " INTID600 ,Interrupt ID600 Priority/Priority Byte Offset 600 " group.long 0x65C++0x03 line.long 0x00 "GICD_IPRIORITYR151,Interrupt Priority Register 151" hexmask.long.byte 0x00 24.--31. 1. " INTID607 ,Interrupt ID607 Priority/Priority Byte Offset 607 " hexmask.long.byte 0x00 16.--23. 1. " INTID606 ,Interrupt ID606 Priority/Priority Byte Offset 606 " hexmask.long.byte 0x00 8.--15. 1. " INTID605 ,Interrupt ID605 Priority/Priority Byte Offset 605 " hexmask.long.byte 0x00 0.--7. 1. " INTID604 ,Interrupt ID604 Priority/Priority Byte Offset 604 " else rgroup.long 0x640++0x03 line.long 0x00 "GICD_IPRIORITYR144,Interrupt Priority Register 144" rgroup.long 0x644++0x03 line.long 0x00 "GICD_IPRIORITYR145,Interrupt Priority Register 145" rgroup.long 0x648++0x03 line.long 0x00 "GICD_IPRIORITYR146,Interrupt Priority Register 146" rgroup.long 0x64C++0x03 line.long 0x00 "GICD_IPRIORITYR147,Interrupt Priority Register 147" rgroup.long 0x650++0x03 line.long 0x00 "GICD_IPRIORITYR148,Interrupt Priority Register 148" rgroup.long 0x654++0x03 line.long 0x00 "GICD_IPRIORITYR149,Interrupt Priority Register 149" rgroup.long 0x658++0x03 line.long 0x00 "GICD_IPRIORITYR150,Interrupt Priority Register 150" rgroup.long 0x65C++0x03 line.long 0x00 "GICD_IPRIORITYR151,Interrupt Priority Register 151" endif if (((per.l(ad:(per.long(spr:0x31F30)&0xFFFC0000)+0x04))&0x0000001F)>=0x13) group.long 0x660++0x03 line.long 0x00 "GICD_IPRIORITYR152,Interrupt Priority Register 152" hexmask.long.byte 0x00 24.--31. 1. " INTID611 ,Interrupt ID611 Priority/Priority Byte Offset 611 " hexmask.long.byte 0x00 16.--23. 1. " INTID610 ,Interrupt ID610 Priority/Priority Byte Offset 610 " hexmask.long.byte 0x00 8.--15. 1. " INTID609 ,Interrupt ID609 Priority/Priority Byte Offset 609 " hexmask.long.byte 0x00 0.--7. 1. " INTID608 ,Interrupt ID608 Priority/Priority Byte Offset 608 " group.long 0x664++0x03 line.long 0x00 "GICD_IPRIORITYR153,Interrupt Priority Register 153" hexmask.long.byte 0x00 24.--31. 1. " INTID615 ,Interrupt ID615 Priority/Priority Byte Offset 615 " hexmask.long.byte 0x00 16.--23. 1. " INTID614 ,Interrupt ID614 Priority/Priority Byte Offset 614 " hexmask.long.byte 0x00 8.--15. 1. " INTID613 ,Interrupt ID613 Priority/Priority Byte Offset 613 " hexmask.long.byte 0x00 0.--7. 1. " INTID612 ,Interrupt ID612 Priority/Priority Byte Offset 612 " group.long 0x668++0x03 line.long 0x00 "GICD_IPRIORITYR154,Interrupt Priority Register 154" hexmask.long.byte 0x00 24.--31. 1. " INTID619 ,Interrupt ID619 Priority/Priority Byte Offset 619 " hexmask.long.byte 0x00 16.--23. 1. " INTID618 ,Interrupt ID618 Priority/Priority Byte Offset 618 " hexmask.long.byte 0x00 8.--15. 1. " INTID617 ,Interrupt ID617 Priority/Priority Byte Offset 617 " hexmask.long.byte 0x00 0.--7. 1. " INTID616 ,Interrupt ID616 Priority/Priority Byte Offset 616 " group.long 0x66C++0x03 line.long 0x00 "GICD_IPRIORITYR155,Interrupt Priority Register 155" hexmask.long.byte 0x00 24.--31. 1. " INTID623 ,Interrupt ID623 Priority/Priority Byte Offset 623 " hexmask.long.byte 0x00 16.--23. 1. " INTID622 ,Interrupt ID622 Priority/Priority Byte Offset 622 " hexmask.long.byte 0x00 8.--15. 1. " INTID621 ,Interrupt ID621 Priority/Priority Byte Offset 621 " hexmask.long.byte 0x00 0.--7. 1. " INTID620 ,Interrupt ID620 Priority/Priority Byte Offset 620 " group.long 0x670++0x03 line.long 0x00 "GICD_IPRIORITYR156,Interrupt Priority Register 156" hexmask.long.byte 0x00 24.--31. 1. " INTID627 ,Interrupt ID627 Priority/Priority Byte Offset 627 " hexmask.long.byte 0x00 16.--23. 1. " INTID626 ,Interrupt ID626 Priority/Priority Byte Offset 626 " hexmask.long.byte 0x00 8.--15. 1. " INTID625 ,Interrupt ID625 Priority/Priority Byte Offset 625 " hexmask.long.byte 0x00 0.--7. 1. " INTID624 ,Interrupt ID624 Priority/Priority Byte Offset 624 " group.long 0x674++0x03 line.long 0x00 "GICD_IPRIORITYR157,Interrupt Priority Register 157" hexmask.long.byte 0x00 24.--31. 1. " INTID631 ,Interrupt ID631 Priority/Priority Byte Offset 631 " hexmask.long.byte 0x00 16.--23. 1. " INTID630 ,Interrupt ID630 Priority/Priority Byte Offset 630 " hexmask.long.byte 0x00 8.--15. 1. " INTID629 ,Interrupt ID629 Priority/Priority Byte Offset 629 " hexmask.long.byte 0x00 0.--7. 1. " INTID628 ,Interrupt ID628 Priority/Priority Byte Offset 628 " group.long 0x678++0x03 line.long 0x00 "GICD_IPRIORITYR158,Interrupt Priority Register 158" hexmask.long.byte 0x00 24.--31. 1. " INTID635 ,Interrupt ID635 Priority/Priority Byte Offset 635 " hexmask.long.byte 0x00 16.--23. 1. " INTID634 ,Interrupt ID634 Priority/Priority Byte Offset 634 " hexmask.long.byte 0x00 8.--15. 1. " INTID633 ,Interrupt ID633 Priority/Priority Byte Offset 633 " hexmask.long.byte 0x00 0.--7. 1. " INTID632 ,Interrupt ID632 Priority/Priority Byte Offset 632 " group.long 0x67C++0x03 line.long 0x00 "GICD_IPRIORITYR159,Interrupt Priority Register 159" hexmask.long.byte 0x00 24.--31. 1. " INTID639 ,Interrupt ID639 Priority/Priority Byte Offset 639 " hexmask.long.byte 0x00 16.--23. 1. " INTID638 ,Interrupt ID638 Priority/Priority Byte Offset 638 " hexmask.long.byte 0x00 8.--15. 1. " INTID637 ,Interrupt ID637 Priority/Priority Byte Offset 637 " hexmask.long.byte 0x00 0.--7. 1. " INTID636 ,Interrupt ID636 Priority/Priority Byte Offset 636 " else rgroup.long 0x660++0x03 line.long 0x00 "GICD_IPRIORITYR152,Interrupt Priority Register 152" rgroup.long 0x664++0x03 line.long 0x00 "GICD_IPRIORITYR153,Interrupt Priority Register 153" rgroup.long 0x668++0x03 line.long 0x00 "GICD_IPRIORITYR154,Interrupt Priority Register 154" rgroup.long 0x66C++0x03 line.long 0x00 "GICD_IPRIORITYR155,Interrupt Priority Register 155" rgroup.long 0x670++0x03 line.long 0x00 "GICD_IPRIORITYR156,Interrupt Priority Register 156" rgroup.long 0x674++0x03 line.long 0x00 "GICD_IPRIORITYR157,Interrupt Priority Register 157" rgroup.long 0x678++0x03 line.long 0x00 "GICD_IPRIORITYR158,Interrupt Priority Register 158" rgroup.long 0x67C++0x03 line.long 0x00 "GICD_IPRIORITYR159,Interrupt Priority Register 159" endif if (((per.l(ad:(per.long(spr:0x31F30)&0xFFFC0000)+0x04))&0x0000001F)>=0x14) group.long 0x680++0x03 line.long 0x00 "GICD_IPRIORITYR160,Interrupt Priority Register 160" hexmask.long.byte 0x00 24.--31. 1. " INTID643 ,Interrupt ID643 Priority/Priority Byte Offset 643 " hexmask.long.byte 0x00 16.--23. 1. " INTID642 ,Interrupt ID642 Priority/Priority Byte Offset 642 " hexmask.long.byte 0x00 8.--15. 1. " INTID641 ,Interrupt ID641 Priority/Priority Byte Offset 641 " hexmask.long.byte 0x00 0.--7. 1. " INTID640 ,Interrupt ID640 Priority/Priority Byte Offset 640 " group.long 0x684++0x03 line.long 0x00 "GICD_IPRIORITYR161,Interrupt Priority Register 161" hexmask.long.byte 0x00 24.--31. 1. " INTID647 ,Interrupt ID647 Priority/Priority Byte Offset 647 " hexmask.long.byte 0x00 16.--23. 1. " INTID646 ,Interrupt ID646 Priority/Priority Byte Offset 646 " hexmask.long.byte 0x00 8.--15. 1. " INTID645 ,Interrupt ID645 Priority/Priority Byte Offset 645 " hexmask.long.byte 0x00 0.--7. 1. " INTID644 ,Interrupt ID644 Priority/Priority Byte Offset 644 " group.long 0x688++0x03 line.long 0x00 "GICD_IPRIORITYR162,Interrupt Priority Register 162" hexmask.long.byte 0x00 24.--31. 1. " INTID651 ,Interrupt ID651 Priority/Priority Byte Offset 651 " hexmask.long.byte 0x00 16.--23. 1. " INTID650 ,Interrupt ID650 Priority/Priority Byte Offset 650 " hexmask.long.byte 0x00 8.--15. 1. " INTID649 ,Interrupt ID649 Priority/Priority Byte Offset 649 " hexmask.long.byte 0x00 0.--7. 1. " INTID648 ,Interrupt ID648 Priority/Priority Byte Offset 648 " group.long 0x68C++0x03 line.long 0x00 "GICD_IPRIORITYR163,Interrupt Priority Register 163" hexmask.long.byte 0x00 24.--31. 1. " INTID655 ,Interrupt ID655 Priority/Priority Byte Offset 655 " hexmask.long.byte 0x00 16.--23. 1. " INTID654 ,Interrupt ID654 Priority/Priority Byte Offset 654 " hexmask.long.byte 0x00 8.--15. 1. " INTID653 ,Interrupt ID653 Priority/Priority Byte Offset 653 " hexmask.long.byte 0x00 0.--7. 1. " INTID652 ,Interrupt ID652 Priority/Priority Byte Offset 652 " group.long 0x690++0x03 line.long 0x00 "GICD_IPRIORITYR164,Interrupt Priority Register 164" hexmask.long.byte 0x00 24.--31. 1. " INTID659 ,Interrupt ID659 Priority/Priority Byte Offset 659 " hexmask.long.byte 0x00 16.--23. 1. " INTID658 ,Interrupt ID658 Priority/Priority Byte Offset 658 " hexmask.long.byte 0x00 8.--15. 1. " INTID657 ,Interrupt ID657 Priority/Priority Byte Offset 657 " hexmask.long.byte 0x00 0.--7. 1. " INTID656 ,Interrupt ID656 Priority/Priority Byte Offset 656 " group.long 0x694++0x03 line.long 0x00 "GICD_IPRIORITYR165,Interrupt Priority Register 165" hexmask.long.byte 0x00 24.--31. 1. " INTID663 ,Interrupt ID663 Priority/Priority Byte Offset 663 " hexmask.long.byte 0x00 16.--23. 1. " INTID662 ,Interrupt ID662 Priority/Priority Byte Offset 662 " hexmask.long.byte 0x00 8.--15. 1. " INTID661 ,Interrupt ID661 Priority/Priority Byte Offset 661 " hexmask.long.byte 0x00 0.--7. 1. " INTID660 ,Interrupt ID660 Priority/Priority Byte Offset 660 " group.long 0x698++0x03 line.long 0x00 "GICD_IPRIORITYR166,Interrupt Priority Register 166" hexmask.long.byte 0x00 24.--31. 1. " INTID667 ,Interrupt ID667 Priority/Priority Byte Offset 667 " hexmask.long.byte 0x00 16.--23. 1. " INTID666 ,Interrupt ID666 Priority/Priority Byte Offset 666 " hexmask.long.byte 0x00 8.--15. 1. " INTID665 ,Interrupt ID665 Priority/Priority Byte Offset 665 " hexmask.long.byte 0x00 0.--7. 1. " INTID664 ,Interrupt ID664 Priority/Priority Byte Offset 664 " group.long 0x69C++0x03 line.long 0x00 "GICD_IPRIORITYR167,Interrupt Priority Register 167" hexmask.long.byte 0x00 24.--31. 1. " INTID671 ,Interrupt ID671 Priority/Priority Byte Offset 671 " hexmask.long.byte 0x00 16.--23. 1. " INTID670 ,Interrupt ID670 Priority/Priority Byte Offset 670 " hexmask.long.byte 0x00 8.--15. 1. " INTID669 ,Interrupt ID669 Priority/Priority Byte Offset 669 " hexmask.long.byte 0x00 0.--7. 1. " INTID668 ,Interrupt ID668 Priority/Priority Byte Offset 668 " else rgroup.long 0x680++0x03 line.long 0x00 "GICD_IPRIORITYR160,Interrupt Priority Register 160" rgroup.long 0x684++0x03 line.long 0x00 "GICD_IPRIORITYR161,Interrupt Priority Register 161" rgroup.long 0x688++0x03 line.long 0x00 "GICD_IPRIORITYR162,Interrupt Priority Register 162" rgroup.long 0x68C++0x03 line.long 0x00 "GICD_IPRIORITYR163,Interrupt Priority Register 163" rgroup.long 0x690++0x03 line.long 0x00 "GICD_IPRIORITYR164,Interrupt Priority Register 164" rgroup.long 0x694++0x03 line.long 0x00 "GICD_IPRIORITYR165,Interrupt Priority Register 165" rgroup.long 0x698++0x03 line.long 0x00 "GICD_IPRIORITYR166,Interrupt Priority Register 166" rgroup.long 0x69C++0x03 line.long 0x00 "GICD_IPRIORITYR167,Interrupt Priority Register 167" endif if (((per.l(ad:(per.long(spr:0x31F30)&0xFFFC0000)+0x04))&0x0000001F)>=0x15) group.long 0x6A0++0x03 line.long 0x00 "GICD_IPRIORITYR168,Interrupt Priority Register 168" hexmask.long.byte 0x00 24.--31. 1. " INTID675 ,Interrupt ID675 Priority/Priority Byte Offset 675 " hexmask.long.byte 0x00 16.--23. 1. " INTID674 ,Interrupt ID674 Priority/Priority Byte Offset 674 " hexmask.long.byte 0x00 8.--15. 1. " INTID673 ,Interrupt ID673 Priority/Priority Byte Offset 673 " hexmask.long.byte 0x00 0.--7. 1. " INTID672 ,Interrupt ID672 Priority/Priority Byte Offset 672 " group.long 0x6A4++0x03 line.long 0x00 "GICD_IPRIORITYR169,Interrupt Priority Register 169" hexmask.long.byte 0x00 24.--31. 1. " INTID679 ,Interrupt ID679 Priority/Priority Byte Offset 679 " hexmask.long.byte 0x00 16.--23. 1. " INTID678 ,Interrupt ID678 Priority/Priority Byte Offset 678 " hexmask.long.byte 0x00 8.--15. 1. " INTID677 ,Interrupt ID677 Priority/Priority Byte Offset 677 " hexmask.long.byte 0x00 0.--7. 1. " INTID676 ,Interrupt ID676 Priority/Priority Byte Offset 676 " group.long 0x6A8++0x03 line.long 0x00 "GICD_IPRIORITYR170,Interrupt Priority Register 170" hexmask.long.byte 0x00 24.--31. 1. " INTID683 ,Interrupt ID683 Priority/Priority Byte Offset 683 " hexmask.long.byte 0x00 16.--23. 1. " INTID682 ,Interrupt ID682 Priority/Priority Byte Offset 682 " hexmask.long.byte 0x00 8.--15. 1. " INTID681 ,Interrupt ID681 Priority/Priority Byte Offset 681 " hexmask.long.byte 0x00 0.--7. 1. " INTID680 ,Interrupt ID680 Priority/Priority Byte Offset 680 " group.long 0x6AC++0x03 line.long 0x00 "GICD_IPRIORITYR171,Interrupt Priority Register 171" hexmask.long.byte 0x00 24.--31. 1. " INTID687 ,Interrupt ID687 Priority/Priority Byte Offset 687 " hexmask.long.byte 0x00 16.--23. 1. " INTID686 ,Interrupt ID686 Priority/Priority Byte Offset 686 " hexmask.long.byte 0x00 8.--15. 1. " INTID685 ,Interrupt ID685 Priority/Priority Byte Offset 685 " hexmask.long.byte 0x00 0.--7. 1. " INTID684 ,Interrupt ID684 Priority/Priority Byte Offset 684 " group.long 0x6B0++0x03 line.long 0x00 "GICD_IPRIORITYR172,Interrupt Priority Register 172" hexmask.long.byte 0x00 24.--31. 1. " INTID691 ,Interrupt ID691 Priority/Priority Byte Offset 691 " hexmask.long.byte 0x00 16.--23. 1. " INTID690 ,Interrupt ID690 Priority/Priority Byte Offset 690 " hexmask.long.byte 0x00 8.--15. 1. " INTID689 ,Interrupt ID689 Priority/Priority Byte Offset 689 " hexmask.long.byte 0x00 0.--7. 1. " INTID688 ,Interrupt ID688 Priority/Priority Byte Offset 688 " group.long 0x6B4++0x03 line.long 0x00 "GICD_IPRIORITYR173,Interrupt Priority Register 173" hexmask.long.byte 0x00 24.--31. 1. " INTID695 ,Interrupt ID695 Priority/Priority Byte Offset 695 " hexmask.long.byte 0x00 16.--23. 1. " INTID694 ,Interrupt ID694 Priority/Priority Byte Offset 694 " hexmask.long.byte 0x00 8.--15. 1. " INTID693 ,Interrupt ID693 Priority/Priority Byte Offset 693 " hexmask.long.byte 0x00 0.--7. 1. " INTID692 ,Interrupt ID692 Priority/Priority Byte Offset 692 " group.long 0x6B8++0x03 line.long 0x00 "GICD_IPRIORITYR174,Interrupt Priority Register 174" hexmask.long.byte 0x00 24.--31. 1. " INTID699 ,Interrupt ID699 Priority/Priority Byte Offset 699 " hexmask.long.byte 0x00 16.--23. 1. " INTID698 ,Interrupt ID698 Priority/Priority Byte Offset 698 " hexmask.long.byte 0x00 8.--15. 1. " INTID697 ,Interrupt ID697 Priority/Priority Byte Offset 697 " hexmask.long.byte 0x00 0.--7. 1. " INTID696 ,Interrupt ID696 Priority/Priority Byte Offset 696 " group.long 0x6BC++0x03 line.long 0x00 "GICD_IPRIORITYR175,Interrupt Priority Register 175" hexmask.long.byte 0x00 24.--31. 1. " INTID703 ,Interrupt ID703 Priority/Priority Byte Offset 703 " hexmask.long.byte 0x00 16.--23. 1. " INTID702 ,Interrupt ID702 Priority/Priority Byte Offset 702 " hexmask.long.byte 0x00 8.--15. 1. " INTID701 ,Interrupt ID701 Priority/Priority Byte Offset 701 " hexmask.long.byte 0x00 0.--7. 1. " INTID700 ,Interrupt ID700 Priority/Priority Byte Offset 700 " else rgroup.long 0x6A0++0x03 line.long 0x00 "GICD_IPRIORITYR168,Interrupt Priority Register 168" rgroup.long 0x6A4++0x03 line.long 0x00 "GICD_IPRIORITYR169,Interrupt Priority Register 169" rgroup.long 0x6A8++0x03 line.long 0x00 "GICD_IPRIORITYR170,Interrupt Priority Register 170" rgroup.long 0x6AC++0x03 line.long 0x00 "GICD_IPRIORITYR171,Interrupt Priority Register 171" rgroup.long 0x6B0++0x03 line.long 0x00 "GICD_IPRIORITYR172,Interrupt Priority Register 172" rgroup.long 0x6B4++0x03 line.long 0x00 "GICD_IPRIORITYR173,Interrupt Priority Register 173" rgroup.long 0x6B8++0x03 line.long 0x00 "GICD_IPRIORITYR174,Interrupt Priority Register 174" rgroup.long 0x6BC++0x03 line.long 0x00 "GICD_IPRIORITYR175,Interrupt Priority Register 175" endif if (((per.l(ad:(per.long(spr:0x31F30)&0xFFFC0000)+0x04))&0x0000001F)>=0x16) group.long 0x6C0++0x03 line.long 0x00 "GICD_IPRIORITYR176,Interrupt Priority Register 176" hexmask.long.byte 0x00 24.--31. 1. " INTID707 ,Interrupt ID707 Priority/Priority Byte Offset 707 " hexmask.long.byte 0x00 16.--23. 1. " INTID706 ,Interrupt ID706 Priority/Priority Byte Offset 706 " hexmask.long.byte 0x00 8.--15. 1. " INTID705 ,Interrupt ID705 Priority/Priority Byte Offset 705 " hexmask.long.byte 0x00 0.--7. 1. " INTID704 ,Interrupt ID704 Priority/Priority Byte Offset 704 " group.long 0x6C4++0x03 line.long 0x00 "GICD_IPRIORITYR177,Interrupt Priority Register 177" hexmask.long.byte 0x00 24.--31. 1. " INTID711 ,Interrupt ID711 Priority/Priority Byte Offset 711 " hexmask.long.byte 0x00 16.--23. 1. " INTID710 ,Interrupt ID710 Priority/Priority Byte Offset 710 " hexmask.long.byte 0x00 8.--15. 1. " INTID709 ,Interrupt ID709 Priority/Priority Byte Offset 709 " hexmask.long.byte 0x00 0.--7. 1. " INTID708 ,Interrupt ID708 Priority/Priority Byte Offset 708 " group.long 0x6C8++0x03 line.long 0x00 "GICD_IPRIORITYR178,Interrupt Priority Register 178" hexmask.long.byte 0x00 24.--31. 1. " INTID715 ,Interrupt ID715 Priority/Priority Byte Offset 715 " hexmask.long.byte 0x00 16.--23. 1. " INTID714 ,Interrupt ID714 Priority/Priority Byte Offset 714 " hexmask.long.byte 0x00 8.--15. 1. " INTID713 ,Interrupt ID713 Priority/Priority Byte Offset 713 " hexmask.long.byte 0x00 0.--7. 1. " INTID712 ,Interrupt ID712 Priority/Priority Byte Offset 712 " group.long 0x6CC++0x03 line.long 0x00 "GICD_IPRIORITYR179,Interrupt Priority Register 179" hexmask.long.byte 0x00 24.--31. 1. " INTID719 ,Interrupt ID719 Priority/Priority Byte Offset 719 " hexmask.long.byte 0x00 16.--23. 1. " INTID718 ,Interrupt ID718 Priority/Priority Byte Offset 718 " hexmask.long.byte 0x00 8.--15. 1. " INTID717 ,Interrupt ID717 Priority/Priority Byte Offset 717 " hexmask.long.byte 0x00 0.--7. 1. " INTID716 ,Interrupt ID716 Priority/Priority Byte Offset 716 " group.long 0x6D0++0x03 line.long 0x00 "GICD_IPRIORITYR180,Interrupt Priority Register 180" hexmask.long.byte 0x00 24.--31. 1. " INTID723 ,Interrupt ID723 Priority/Priority Byte Offset 723 " hexmask.long.byte 0x00 16.--23. 1. " INTID722 ,Interrupt ID722 Priority/Priority Byte Offset 722 " hexmask.long.byte 0x00 8.--15. 1. " INTID721 ,Interrupt ID721 Priority/Priority Byte Offset 721 " hexmask.long.byte 0x00 0.--7. 1. " INTID720 ,Interrupt ID720 Priority/Priority Byte Offset 720 " group.long 0x6D4++0x03 line.long 0x00 "GICD_IPRIORITYR181,Interrupt Priority Register 181" hexmask.long.byte 0x00 24.--31. 1. " INTID727 ,Interrupt ID727 Priority/Priority Byte Offset 727 " hexmask.long.byte 0x00 16.--23. 1. " INTID726 ,Interrupt ID726 Priority/Priority Byte Offset 726 " hexmask.long.byte 0x00 8.--15. 1. " INTID725 ,Interrupt ID725 Priority/Priority Byte Offset 725 " hexmask.long.byte 0x00 0.--7. 1. " INTID724 ,Interrupt ID724 Priority/Priority Byte Offset 724 " group.long 0x6D8++0x03 line.long 0x00 "GICD_IPRIORITYR182,Interrupt Priority Register 182" hexmask.long.byte 0x00 24.--31. 1. " INTID731 ,Interrupt ID731 Priority/Priority Byte Offset 731 " hexmask.long.byte 0x00 16.--23. 1. " INTID730 ,Interrupt ID730 Priority/Priority Byte Offset 730 " hexmask.long.byte 0x00 8.--15. 1. " INTID729 ,Interrupt ID729 Priority/Priority Byte Offset 729 " hexmask.long.byte 0x00 0.--7. 1. " INTID728 ,Interrupt ID728 Priority/Priority Byte Offset 728 " group.long 0x6DC++0x03 line.long 0x00 "GICD_IPRIORITYR183,Interrupt Priority Register 183" hexmask.long.byte 0x00 24.--31. 1. " INTID735 ,Interrupt ID735 Priority/Priority Byte Offset 735 " hexmask.long.byte 0x00 16.--23. 1. " INTID734 ,Interrupt ID734 Priority/Priority Byte Offset 734 " hexmask.long.byte 0x00 8.--15. 1. " INTID733 ,Interrupt ID733 Priority/Priority Byte Offset 733 " hexmask.long.byte 0x00 0.--7. 1. " INTID732 ,Interrupt ID732 Priority/Priority Byte Offset 732 " else rgroup.long 0x6C0++0x03 line.long 0x00 "GICD_IPRIORITYR176,Interrupt Priority Register 176" rgroup.long 0x6C4++0x03 line.long 0x00 "GICD_IPRIORITYR177,Interrupt Priority Register 177" rgroup.long 0x6C8++0x03 line.long 0x00 "GICD_IPRIORITYR178,Interrupt Priority Register 178" rgroup.long 0x6CC++0x03 line.long 0x00 "GICD_IPRIORITYR179,Interrupt Priority Register 179" rgroup.long 0x6D0++0x03 line.long 0x00 "GICD_IPRIORITYR180,Interrupt Priority Register 180" rgroup.long 0x6D4++0x03 line.long 0x00 "GICD_IPRIORITYR181,Interrupt Priority Register 181" rgroup.long 0x6D8++0x03 line.long 0x00 "GICD_IPRIORITYR182,Interrupt Priority Register 182" rgroup.long 0x6DC++0x03 line.long 0x00 "GICD_IPRIORITYR183,Interrupt Priority Register 183" endif if (((per.l(ad:(per.long(spr:0x31F30)&0xFFFC0000)+0x04))&0x0000001F)>=0x17) group.long 0x6E0++0x03 line.long 0x00 "GICD_IPRIORITYR184,Interrupt Priority Register 184" hexmask.long.byte 0x00 24.--31. 1. " INTID739 ,Interrupt ID739 Priority/Priority Byte Offset 739 " hexmask.long.byte 0x00 16.--23. 1. " INTID738 ,Interrupt ID738 Priority/Priority Byte Offset 738 " hexmask.long.byte 0x00 8.--15. 1. " INTID737 ,Interrupt ID737 Priority/Priority Byte Offset 737 " hexmask.long.byte 0x00 0.--7. 1. " INTID736 ,Interrupt ID736 Priority/Priority Byte Offset 736 " group.long 0x6E4++0x03 line.long 0x00 "GICD_IPRIORITYR185,Interrupt Priority Register 185" hexmask.long.byte 0x00 24.--31. 1. " INTID743 ,Interrupt ID743 Priority/Priority Byte Offset 743 " hexmask.long.byte 0x00 16.--23. 1. " INTID742 ,Interrupt ID742 Priority/Priority Byte Offset 742 " hexmask.long.byte 0x00 8.--15. 1. " INTID741 ,Interrupt ID741 Priority/Priority Byte Offset 741 " hexmask.long.byte 0x00 0.--7. 1. " INTID740 ,Interrupt ID740 Priority/Priority Byte Offset 740 " group.long 0x6E8++0x03 line.long 0x00 "GICD_IPRIORITYR186,Interrupt Priority Register 186" hexmask.long.byte 0x00 24.--31. 1. " INTID747 ,Interrupt ID747 Priority/Priority Byte Offset 747 " hexmask.long.byte 0x00 16.--23. 1. " INTID746 ,Interrupt ID746 Priority/Priority Byte Offset 746 " hexmask.long.byte 0x00 8.--15. 1. " INTID745 ,Interrupt ID745 Priority/Priority Byte Offset 745 " hexmask.long.byte 0x00 0.--7. 1. " INTID744 ,Interrupt ID744 Priority/Priority Byte Offset 744 " group.long 0x6EC++0x03 line.long 0x00 "GICD_IPRIORITYR187,Interrupt Priority Register 187" hexmask.long.byte 0x00 24.--31. 1. " INTID751 ,Interrupt ID751 Priority/Priority Byte Offset 751 " hexmask.long.byte 0x00 16.--23. 1. " INTID750 ,Interrupt ID750 Priority/Priority Byte Offset 750 " hexmask.long.byte 0x00 8.--15. 1. " INTID749 ,Interrupt ID749 Priority/Priority Byte Offset 749 " hexmask.long.byte 0x00 0.--7. 1. " INTID748 ,Interrupt ID748 Priority/Priority Byte Offset 748 " group.long 0x6F0++0x03 line.long 0x00 "GICD_IPRIORITYR188,Interrupt Priority Register 188" hexmask.long.byte 0x00 24.--31. 1. " INTID755 ,Interrupt ID755 Priority/Priority Byte Offset 755 " hexmask.long.byte 0x00 16.--23. 1. " INTID754 ,Interrupt ID754 Priority/Priority Byte Offset 754 " hexmask.long.byte 0x00 8.--15. 1. " INTID753 ,Interrupt ID753 Priority/Priority Byte Offset 753 " hexmask.long.byte 0x00 0.--7. 1. " INTID752 ,Interrupt ID752 Priority/Priority Byte Offset 752 " group.long 0x6F4++0x03 line.long 0x00 "GICD_IPRIORITYR189,Interrupt Priority Register 189" hexmask.long.byte 0x00 24.--31. 1. " INTID759 ,Interrupt ID759 Priority/Priority Byte Offset 759 " hexmask.long.byte 0x00 16.--23. 1. " INTID758 ,Interrupt ID758 Priority/Priority Byte Offset 758 " hexmask.long.byte 0x00 8.--15. 1. " INTID757 ,Interrupt ID757 Priority/Priority Byte Offset 757 " hexmask.long.byte 0x00 0.--7. 1. " INTID756 ,Interrupt ID756 Priority/Priority Byte Offset 756 " group.long 0x6F8++0x03 line.long 0x00 "GICD_IPRIORITYR190,Interrupt Priority Register 190" hexmask.long.byte 0x00 24.--31. 1. " INTID763 ,Interrupt ID763 Priority/Priority Byte Offset 763 " hexmask.long.byte 0x00 16.--23. 1. " INTID762 ,Interrupt ID762 Priority/Priority Byte Offset 762 " hexmask.long.byte 0x00 8.--15. 1. " INTID761 ,Interrupt ID761 Priority/Priority Byte Offset 761 " hexmask.long.byte 0x00 0.--7. 1. " INTID760 ,Interrupt ID760 Priority/Priority Byte Offset 760 " group.long 0x6FC++0x03 line.long 0x00 "GICD_IPRIORITYR191,Interrupt Priority Register 191" hexmask.long.byte 0x00 24.--31. 1. " INTID767 ,Interrupt ID767 Priority/Priority Byte Offset 767 " hexmask.long.byte 0x00 16.--23. 1. " INTID766 ,Interrupt ID766 Priority/Priority Byte Offset 766 " hexmask.long.byte 0x00 8.--15. 1. " INTID765 ,Interrupt ID765 Priority/Priority Byte Offset 765 " hexmask.long.byte 0x00 0.--7. 1. " INTID764 ,Interrupt ID764 Priority/Priority Byte Offset 764 " else rgroup.long 0x6E0++0x03 line.long 0x00 "GICD_IPRIORITYR184,Interrupt Priority Register 184" rgroup.long 0x6E4++0x03 line.long 0x00 "GICD_IPRIORITYR185,Interrupt Priority Register 185" rgroup.long 0x6E8++0x03 line.long 0x00 "GICD_IPRIORITYR186,Interrupt Priority Register 186" rgroup.long 0x6EC++0x03 line.long 0x00 "GICD_IPRIORITYR187,Interrupt Priority Register 187" rgroup.long 0x6F0++0x03 line.long 0x00 "GICD_IPRIORITYR188,Interrupt Priority Register 188" rgroup.long 0x6F4++0x03 line.long 0x00 "GICD_IPRIORITYR189,Interrupt Priority Register 189" rgroup.long 0x6F8++0x03 line.long 0x00 "GICD_IPRIORITYR190,Interrupt Priority Register 190" rgroup.long 0x6FC++0x03 line.long 0x00 "GICD_IPRIORITYR191,Interrupt Priority Register 191" endif if (((per.l(ad:(per.long(spr:0x31F30)&0xFFFC0000)+0x04))&0x0000001F)>=0x18) group.long 0x700++0x03 line.long 0x00 "GICD_IPRIORITYR192,Interrupt Priority Register 192" hexmask.long.byte 0x00 24.--31. 1. " INTID771 ,Interrupt ID771 Priority/Priority Byte Offset 771 " hexmask.long.byte 0x00 16.--23. 1. " INTID770 ,Interrupt ID770 Priority/Priority Byte Offset 770 " hexmask.long.byte 0x00 8.--15. 1. " INTID769 ,Interrupt ID769 Priority/Priority Byte Offset 769 " hexmask.long.byte 0x00 0.--7. 1. " INTID768 ,Interrupt ID768 Priority/Priority Byte Offset 768 " group.long 0x704++0x03 line.long 0x00 "GICD_IPRIORITYR193,Interrupt Priority Register 193" hexmask.long.byte 0x00 24.--31. 1. " INTID775 ,Interrupt ID775 Priority/Priority Byte Offset 775 " hexmask.long.byte 0x00 16.--23. 1. " INTID774 ,Interrupt ID774 Priority/Priority Byte Offset 774 " hexmask.long.byte 0x00 8.--15. 1. " INTID773 ,Interrupt ID773 Priority/Priority Byte Offset 773 " hexmask.long.byte 0x00 0.--7. 1. " INTID772 ,Interrupt ID772 Priority/Priority Byte Offset 772 " group.long 0x708++0x03 line.long 0x00 "GICD_IPRIORITYR194,Interrupt Priority Register 194" hexmask.long.byte 0x00 24.--31. 1. " INTID779 ,Interrupt ID779 Priority/Priority Byte Offset 779 " hexmask.long.byte 0x00 16.--23. 1. " INTID778 ,Interrupt ID778 Priority/Priority Byte Offset 778 " hexmask.long.byte 0x00 8.--15. 1. " INTID777 ,Interrupt ID777 Priority/Priority Byte Offset 777 " hexmask.long.byte 0x00 0.--7. 1. " INTID776 ,Interrupt ID776 Priority/Priority Byte Offset 776 " group.long 0x70C++0x03 line.long 0x00 "GICD_IPRIORITYR195,Interrupt Priority Register 195" hexmask.long.byte 0x00 24.--31. 1. " INTID783 ,Interrupt ID783 Priority/Priority Byte Offset 783 " hexmask.long.byte 0x00 16.--23. 1. " INTID782 ,Interrupt ID782 Priority/Priority Byte Offset 782 " hexmask.long.byte 0x00 8.--15. 1. " INTID781 ,Interrupt ID781 Priority/Priority Byte Offset 781 " hexmask.long.byte 0x00 0.--7. 1. " INTID780 ,Interrupt ID780 Priority/Priority Byte Offset 780 " group.long 0x710++0x03 line.long 0x00 "GICD_IPRIORITYR196,Interrupt Priority Register 196" hexmask.long.byte 0x00 24.--31. 1. " INTID787 ,Interrupt ID787 Priority/Priority Byte Offset 787 " hexmask.long.byte 0x00 16.--23. 1. " INTID786 ,Interrupt ID786 Priority/Priority Byte Offset 786 " hexmask.long.byte 0x00 8.--15. 1. " INTID785 ,Interrupt ID785 Priority/Priority Byte Offset 785 " hexmask.long.byte 0x00 0.--7. 1. " INTID784 ,Interrupt ID784 Priority/Priority Byte Offset 784 " group.long 0x714++0x03 line.long 0x00 "GICD_IPRIORITYR197,Interrupt Priority Register 197" hexmask.long.byte 0x00 24.--31. 1. " INTID791 ,Interrupt ID791 Priority/Priority Byte Offset 791 " hexmask.long.byte 0x00 16.--23. 1. " INTID790 ,Interrupt ID790 Priority/Priority Byte Offset 790 " hexmask.long.byte 0x00 8.--15. 1. " INTID789 ,Interrupt ID789 Priority/Priority Byte Offset 789 " hexmask.long.byte 0x00 0.--7. 1. " INTID788 ,Interrupt ID788 Priority/Priority Byte Offset 788 " group.long 0x718++0x03 line.long 0x00 "GICD_IPRIORITYR198,Interrupt Priority Register 198" hexmask.long.byte 0x00 24.--31. 1. " INTID795 ,Interrupt ID795 Priority/Priority Byte Offset 795 " hexmask.long.byte 0x00 16.--23. 1. " INTID794 ,Interrupt ID794 Priority/Priority Byte Offset 794 " hexmask.long.byte 0x00 8.--15. 1. " INTID793 ,Interrupt ID793 Priority/Priority Byte Offset 793 " hexmask.long.byte 0x00 0.--7. 1. " INTID792 ,Interrupt ID792 Priority/Priority Byte Offset 792 " group.long 0x71C++0x03 line.long 0x00 "GICD_IPRIORITYR199,Interrupt Priority Register 199" hexmask.long.byte 0x00 24.--31. 1. " INTID799 ,Interrupt ID799 Priority/Priority Byte Offset 799 " hexmask.long.byte 0x00 16.--23. 1. " INTID798 ,Interrupt ID798 Priority/Priority Byte Offset 798 " hexmask.long.byte 0x00 8.--15. 1. " INTID797 ,Interrupt ID797 Priority/Priority Byte Offset 797 " hexmask.long.byte 0x00 0.--7. 1. " INTID796 ,Interrupt ID796 Priority/Priority Byte Offset 796 " else rgroup.long 0x700++0x03 line.long 0x00 "GICD_IPRIORITYR192,Interrupt Priority Register 192" rgroup.long 0x704++0x03 line.long 0x00 "GICD_IPRIORITYR193,Interrupt Priority Register 193" rgroup.long 0x708++0x03 line.long 0x00 "GICD_IPRIORITYR194,Interrupt Priority Register 194" rgroup.long 0x70C++0x03 line.long 0x00 "GICD_IPRIORITYR195,Interrupt Priority Register 195" rgroup.long 0x710++0x03 line.long 0x00 "GICD_IPRIORITYR196,Interrupt Priority Register 196" rgroup.long 0x714++0x03 line.long 0x00 "GICD_IPRIORITYR197,Interrupt Priority Register 197" rgroup.long 0x718++0x03 line.long 0x00 "GICD_IPRIORITYR198,Interrupt Priority Register 198" rgroup.long 0x71C++0x03 line.long 0x00 "GICD_IPRIORITYR199,Interrupt Priority Register 199" endif if (((per.l(ad:(per.long(spr:0x31F30)&0xFFFC0000)+0x04))&0x0000001F)>=0x19) group.long 0x720++0x03 line.long 0x00 "GICD_IPRIORITYR200,Interrupt Priority Register 200" hexmask.long.byte 0x00 24.--31. 1. " INTID803 ,Interrupt ID803 Priority/Priority Byte Offset 803 " hexmask.long.byte 0x00 16.--23. 1. " INTID802 ,Interrupt ID802 Priority/Priority Byte Offset 802 " hexmask.long.byte 0x00 8.--15. 1. " INTID801 ,Interrupt ID801 Priority/Priority Byte Offset 801 " hexmask.long.byte 0x00 0.--7. 1. " INTID800 ,Interrupt ID800 Priority/Priority Byte Offset 800 " group.long 0x724++0x03 line.long 0x00 "GICD_IPRIORITYR201,Interrupt Priority Register 201" hexmask.long.byte 0x00 24.--31. 1. " INTID807 ,Interrupt ID807 Priority/Priority Byte Offset 807 " hexmask.long.byte 0x00 16.--23. 1. " INTID806 ,Interrupt ID806 Priority/Priority Byte Offset 806 " hexmask.long.byte 0x00 8.--15. 1. " INTID805 ,Interrupt ID805 Priority/Priority Byte Offset 805 " hexmask.long.byte 0x00 0.--7. 1. " INTID804 ,Interrupt ID804 Priority/Priority Byte Offset 804 " group.long 0x728++0x03 line.long 0x00 "GICD_IPRIORITYR202,Interrupt Priority Register 202" hexmask.long.byte 0x00 24.--31. 1. " INTID811 ,Interrupt ID811 Priority/Priority Byte Offset 811 " hexmask.long.byte 0x00 16.--23. 1. " INTID810 ,Interrupt ID810 Priority/Priority Byte Offset 810 " hexmask.long.byte 0x00 8.--15. 1. " INTID809 ,Interrupt ID809 Priority/Priority Byte Offset 809 " hexmask.long.byte 0x00 0.--7. 1. " INTID808 ,Interrupt ID808 Priority/Priority Byte Offset 808 " group.long 0x72C++0x03 line.long 0x00 "GICD_IPRIORITYR203,Interrupt Priority Register 203" hexmask.long.byte 0x00 24.--31. 1. " INTID815 ,Interrupt ID815 Priority/Priority Byte Offset 815 " hexmask.long.byte 0x00 16.--23. 1. " INTID814 ,Interrupt ID814 Priority/Priority Byte Offset 814 " hexmask.long.byte 0x00 8.--15. 1. " INTID813 ,Interrupt ID813 Priority/Priority Byte Offset 813 " hexmask.long.byte 0x00 0.--7. 1. " INTID812 ,Interrupt ID812 Priority/Priority Byte Offset 812 " group.long 0x730++0x03 line.long 0x00 "GICD_IPRIORITYR204,Interrupt Priority Register 204" hexmask.long.byte 0x00 24.--31. 1. " INTID819 ,Interrupt ID819 Priority/Priority Byte Offset 819 " hexmask.long.byte 0x00 16.--23. 1. " INTID818 ,Interrupt ID818 Priority/Priority Byte Offset 818 " hexmask.long.byte 0x00 8.--15. 1. " INTID817 ,Interrupt ID817 Priority/Priority Byte Offset 817 " hexmask.long.byte 0x00 0.--7. 1. " INTID816 ,Interrupt ID816 Priority/Priority Byte Offset 816 " group.long 0x734++0x03 line.long 0x00 "GICD_IPRIORITYR205,Interrupt Priority Register 205" hexmask.long.byte 0x00 24.--31. 1. " INTID823 ,Interrupt ID823 Priority/Priority Byte Offset 823 " hexmask.long.byte 0x00 16.--23. 1. " INTID822 ,Interrupt ID822 Priority/Priority Byte Offset 822 " hexmask.long.byte 0x00 8.--15. 1. " INTID821 ,Interrupt ID821 Priority/Priority Byte Offset 821 " hexmask.long.byte 0x00 0.--7. 1. " INTID820 ,Interrupt ID820 Priority/Priority Byte Offset 820 " group.long 0x738++0x03 line.long 0x00 "GICD_IPRIORITYR206,Interrupt Priority Register 206" hexmask.long.byte 0x00 24.--31. 1. " INTID827 ,Interrupt ID827 Priority/Priority Byte Offset 827 " hexmask.long.byte 0x00 16.--23. 1. " INTID826 ,Interrupt ID826 Priority/Priority Byte Offset 826 " hexmask.long.byte 0x00 8.--15. 1. " INTID825 ,Interrupt ID825 Priority/Priority Byte Offset 825 " hexmask.long.byte 0x00 0.--7. 1. " INTID824 ,Interrupt ID824 Priority/Priority Byte Offset 824 " group.long 0x73C++0x03 line.long 0x00 "GICD_IPRIORITYR207,Interrupt Priority Register 207" hexmask.long.byte 0x00 24.--31. 1. " INTID831 ,Interrupt ID831 Priority/Priority Byte Offset 831 " hexmask.long.byte 0x00 16.--23. 1. " INTID830 ,Interrupt ID830 Priority/Priority Byte Offset 830 " hexmask.long.byte 0x00 8.--15. 1. " INTID829 ,Interrupt ID829 Priority/Priority Byte Offset 829 " hexmask.long.byte 0x00 0.--7. 1. " INTID828 ,Interrupt ID828 Priority/Priority Byte Offset 828 " else rgroup.long 0x720++0x03 line.long 0x00 "GICD_IPRIORITYR200,Interrupt Priority Register 200" rgroup.long 0x724++0x03 line.long 0x00 "GICD_IPRIORITYR201,Interrupt Priority Register 201" rgroup.long 0x728++0x03 line.long 0x00 "GICD_IPRIORITYR202,Interrupt Priority Register 202" rgroup.long 0x72C++0x03 line.long 0x00 "GICD_IPRIORITYR203,Interrupt Priority Register 203" rgroup.long 0x730++0x03 line.long 0x00 "GICD_IPRIORITYR204,Interrupt Priority Register 204" rgroup.long 0x734++0x03 line.long 0x00 "GICD_IPRIORITYR205,Interrupt Priority Register 205" rgroup.long 0x738++0x03 line.long 0x00 "GICD_IPRIORITYR206,Interrupt Priority Register 206" rgroup.long 0x73C++0x03 line.long 0x00 "GICD_IPRIORITYR207,Interrupt Priority Register 207" endif if (((per.l(ad:(per.long(spr:0x31F30)&0xFFFC0000)+0x04))&0x0000001F)>=0x1A) group.long 0x740++0x03 line.long 0x00 "GICD_IPRIORITYR208,Interrupt Priority Register 208" hexmask.long.byte 0x00 24.--31. 1. " INTID835 ,Interrupt ID835 Priority/Priority Byte Offset 835 " hexmask.long.byte 0x00 16.--23. 1. " INTID834 ,Interrupt ID834 Priority/Priority Byte Offset 834 " hexmask.long.byte 0x00 8.--15. 1. " INTID833 ,Interrupt ID833 Priority/Priority Byte Offset 833 " hexmask.long.byte 0x00 0.--7. 1. " INTID832 ,Interrupt ID832 Priority/Priority Byte Offset 832 " group.long 0x744++0x03 line.long 0x00 "GICD_IPRIORITYR209,Interrupt Priority Register 209" hexmask.long.byte 0x00 24.--31. 1. " INTID839 ,Interrupt ID839 Priority/Priority Byte Offset 839 " hexmask.long.byte 0x00 16.--23. 1. " INTID838 ,Interrupt ID838 Priority/Priority Byte Offset 838 " hexmask.long.byte 0x00 8.--15. 1. " INTID837 ,Interrupt ID837 Priority/Priority Byte Offset 837 " hexmask.long.byte 0x00 0.--7. 1. " INTID836 ,Interrupt ID836 Priority/Priority Byte Offset 836 " group.long 0x748++0x03 line.long 0x00 "GICD_IPRIORITYR210,Interrupt Priority Register 210" hexmask.long.byte 0x00 24.--31. 1. " INTID843 ,Interrupt ID843 Priority/Priority Byte Offset 843 " hexmask.long.byte 0x00 16.--23. 1. " INTID842 ,Interrupt ID842 Priority/Priority Byte Offset 842 " hexmask.long.byte 0x00 8.--15. 1. " INTID841 ,Interrupt ID841 Priority/Priority Byte Offset 841 " hexmask.long.byte 0x00 0.--7. 1. " INTID840 ,Interrupt ID840 Priority/Priority Byte Offset 840 " group.long 0x74C++0x03 line.long 0x00 "GICD_IPRIORITYR211,Interrupt Priority Register 211" hexmask.long.byte 0x00 24.--31. 1. " INTID847 ,Interrupt ID847 Priority/Priority Byte Offset 847 " hexmask.long.byte 0x00 16.--23. 1. " INTID846 ,Interrupt ID846 Priority/Priority Byte Offset 846 " hexmask.long.byte 0x00 8.--15. 1. " INTID845 ,Interrupt ID845 Priority/Priority Byte Offset 845 " hexmask.long.byte 0x00 0.--7. 1. " INTID844 ,Interrupt ID844 Priority/Priority Byte Offset 844 " group.long 0x750++0x03 line.long 0x00 "GICD_IPRIORITYR212,Interrupt Priority Register 212" hexmask.long.byte 0x00 24.--31. 1. " INTID851 ,Interrupt ID851 Priority/Priority Byte Offset 851 " hexmask.long.byte 0x00 16.--23. 1. " INTID850 ,Interrupt ID850 Priority/Priority Byte Offset 850 " hexmask.long.byte 0x00 8.--15. 1. " INTID849 ,Interrupt ID849 Priority/Priority Byte Offset 849 " hexmask.long.byte 0x00 0.--7. 1. " INTID848 ,Interrupt ID848 Priority/Priority Byte Offset 848 " group.long 0x754++0x03 line.long 0x00 "GICD_IPRIORITYR213,Interrupt Priority Register 213" hexmask.long.byte 0x00 24.--31. 1. " INTID855 ,Interrupt ID855 Priority/Priority Byte Offset 855 " hexmask.long.byte 0x00 16.--23. 1. " INTID854 ,Interrupt ID854 Priority/Priority Byte Offset 854 " hexmask.long.byte 0x00 8.--15. 1. " INTID853 ,Interrupt ID853 Priority/Priority Byte Offset 853 " hexmask.long.byte 0x00 0.--7. 1. " INTID852 ,Interrupt ID852 Priority/Priority Byte Offset 852 " group.long 0x758++0x03 line.long 0x00 "GICD_IPRIORITYR214,Interrupt Priority Register 214" hexmask.long.byte 0x00 24.--31. 1. " INTID859 ,Interrupt ID859 Priority/Priority Byte Offset 859 " hexmask.long.byte 0x00 16.--23. 1. " INTID858 ,Interrupt ID858 Priority/Priority Byte Offset 858 " hexmask.long.byte 0x00 8.--15. 1. " INTID857 ,Interrupt ID857 Priority/Priority Byte Offset 857 " hexmask.long.byte 0x00 0.--7. 1. " INTID856 ,Interrupt ID856 Priority/Priority Byte Offset 856 " group.long 0x75C++0x03 line.long 0x00 "GICD_IPRIORITYR215,Interrupt Priority Register 215" hexmask.long.byte 0x00 24.--31. 1. " INTID863 ,Interrupt ID863 Priority/Priority Byte Offset 863 " hexmask.long.byte 0x00 16.--23. 1. " INTID862 ,Interrupt ID862 Priority/Priority Byte Offset 862 " hexmask.long.byte 0x00 8.--15. 1. " INTID861 ,Interrupt ID861 Priority/Priority Byte Offset 861 " hexmask.long.byte 0x00 0.--7. 1. " INTID860 ,Interrupt ID860 Priority/Priority Byte Offset 860 " else rgroup.long 0x740++0x03 line.long 0x00 "GICD_IPRIORITYR208,Interrupt Priority Register 208" rgroup.long 0x744++0x03 line.long 0x00 "GICD_IPRIORITYR209,Interrupt Priority Register 209" rgroup.long 0x748++0x03 line.long 0x00 "GICD_IPRIORITYR210,Interrupt Priority Register 210" rgroup.long 0x74C++0x03 line.long 0x00 "GICD_IPRIORITYR211,Interrupt Priority Register 211" rgroup.long 0x750++0x03 line.long 0x00 "GICD_IPRIORITYR212,Interrupt Priority Register 212" rgroup.long 0x754++0x03 line.long 0x00 "GICD_IPRIORITYR213,Interrupt Priority Register 213" rgroup.long 0x758++0x03 line.long 0x00 "GICD_IPRIORITYR214,Interrupt Priority Register 214" rgroup.long 0x75C++0x03 line.long 0x00 "GICD_IPRIORITYR215,Interrupt Priority Register 215" endif if (((per.l(ad:(per.long(spr:0x31F30)&0xFFFC0000)+0x04))&0x0000001F)>=0x1B) group.long 0x760++0x03 line.long 0x00 "GICD_IPRIORITYR216,Interrupt Priority Register 216" hexmask.long.byte 0x00 24.--31. 1. " INTID867 ,Interrupt ID867 Priority/Priority Byte Offset 867 " hexmask.long.byte 0x00 16.--23. 1. " INTID866 ,Interrupt ID866 Priority/Priority Byte Offset 866 " hexmask.long.byte 0x00 8.--15. 1. " INTID865 ,Interrupt ID865 Priority/Priority Byte Offset 865 " hexmask.long.byte 0x00 0.--7. 1. " INTID864 ,Interrupt ID864 Priority/Priority Byte Offset 864 " group.long 0x764++0x03 line.long 0x00 "GICD_IPRIORITYR217,Interrupt Priority Register 217" hexmask.long.byte 0x00 24.--31. 1. " INTID871 ,Interrupt ID871 Priority/Priority Byte Offset 871 " hexmask.long.byte 0x00 16.--23. 1. " INTID870 ,Interrupt ID870 Priority/Priority Byte Offset 870 " hexmask.long.byte 0x00 8.--15. 1. " INTID869 ,Interrupt ID869 Priority/Priority Byte Offset 869 " hexmask.long.byte 0x00 0.--7. 1. " INTID868 ,Interrupt ID868 Priority/Priority Byte Offset 868 " group.long 0x768++0x03 line.long 0x00 "GICD_IPRIORITYR218,Interrupt Priority Register 218" hexmask.long.byte 0x00 24.--31. 1. " INTID875 ,Interrupt ID875 Priority/Priority Byte Offset 875 " hexmask.long.byte 0x00 16.--23. 1. " INTID874 ,Interrupt ID874 Priority/Priority Byte Offset 874 " hexmask.long.byte 0x00 8.--15. 1. " INTID873 ,Interrupt ID873 Priority/Priority Byte Offset 873 " hexmask.long.byte 0x00 0.--7. 1. " INTID872 ,Interrupt ID872 Priority/Priority Byte Offset 872 " group.long 0x76C++0x03 line.long 0x00 "GICD_IPRIORITYR219,Interrupt Priority Register 219" hexmask.long.byte 0x00 24.--31. 1. " INTID879 ,Interrupt ID879 Priority/Priority Byte Offset 879 " hexmask.long.byte 0x00 16.--23. 1. " INTID878 ,Interrupt ID878 Priority/Priority Byte Offset 878 " hexmask.long.byte 0x00 8.--15. 1. " INTID877 ,Interrupt ID877 Priority/Priority Byte Offset 877 " hexmask.long.byte 0x00 0.--7. 1. " INTID876 ,Interrupt ID876 Priority/Priority Byte Offset 876 " group.long 0x770++0x03 line.long 0x00 "GICD_IPRIORITYR220,Interrupt Priority Register 220" hexmask.long.byte 0x00 24.--31. 1. " INTID883 ,Interrupt ID883 Priority/Priority Byte Offset 883 " hexmask.long.byte 0x00 16.--23. 1. " INTID882 ,Interrupt ID882 Priority/Priority Byte Offset 882 " hexmask.long.byte 0x00 8.--15. 1. " INTID881 ,Interrupt ID881 Priority/Priority Byte Offset 881 " hexmask.long.byte 0x00 0.--7. 1. " INTID880 ,Interrupt ID880 Priority/Priority Byte Offset 880 " group.long 0x774++0x03 line.long 0x00 "GICD_IPRIORITYR221,Interrupt Priority Register 221" hexmask.long.byte 0x00 24.--31. 1. " INTID887 ,Interrupt ID887 Priority/Priority Byte Offset 887 " hexmask.long.byte 0x00 16.--23. 1. " INTID886 ,Interrupt ID886 Priority/Priority Byte Offset 886 " hexmask.long.byte 0x00 8.--15. 1. " INTID885 ,Interrupt ID885 Priority/Priority Byte Offset 885 " hexmask.long.byte 0x00 0.--7. 1. " INTID884 ,Interrupt ID884 Priority/Priority Byte Offset 884 " group.long 0x778++0x03 line.long 0x00 "GICD_IPRIORITYR222,Interrupt Priority Register 222" hexmask.long.byte 0x00 24.--31. 1. " INTID891 ,Interrupt ID891 Priority/Priority Byte Offset 891 " hexmask.long.byte 0x00 16.--23. 1. " INTID890 ,Interrupt ID890 Priority/Priority Byte Offset 890 " hexmask.long.byte 0x00 8.--15. 1. " INTID889 ,Interrupt ID889 Priority/Priority Byte Offset 889 " hexmask.long.byte 0x00 0.--7. 1. " INTID888 ,Interrupt ID888 Priority/Priority Byte Offset 888 " group.long 0x77C++0x03 line.long 0x00 "GICD_IPRIORITYR223,Interrupt Priority Register 223" hexmask.long.byte 0x00 24.--31. 1. " INTID895 ,Interrupt ID895 Priority/Priority Byte Offset 895 " hexmask.long.byte 0x00 16.--23. 1. " INTID894 ,Interrupt ID894 Priority/Priority Byte Offset 894 " hexmask.long.byte 0x00 8.--15. 1. " INTID893 ,Interrupt ID893 Priority/Priority Byte Offset 893 " hexmask.long.byte 0x00 0.--7. 1. " INTID892 ,Interrupt ID892 Priority/Priority Byte Offset 892 " else rgroup.long 0x760++0x03 line.long 0x00 "GICD_IPRIORITYR216,Interrupt Priority Register 216" rgroup.long 0x764++0x03 line.long 0x00 "GICD_IPRIORITYR217,Interrupt Priority Register 217" rgroup.long 0x768++0x03 line.long 0x00 "GICD_IPRIORITYR218,Interrupt Priority Register 218" rgroup.long 0x76C++0x03 line.long 0x00 "GICD_IPRIORITYR219,Interrupt Priority Register 219" rgroup.long 0x770++0x03 line.long 0x00 "GICD_IPRIORITYR220,Interrupt Priority Register 220" rgroup.long 0x774++0x03 line.long 0x00 "GICD_IPRIORITYR221,Interrupt Priority Register 221" rgroup.long 0x778++0x03 line.long 0x00 "GICD_IPRIORITYR222,Interrupt Priority Register 222" rgroup.long 0x77C++0x03 line.long 0x00 "GICD_IPRIORITYR223,Interrupt Priority Register 223" endif if (((per.l(ad:(per.long(spr:0x31F30)&0xFFFC0000)+0x04))&0x0000001F)>=0x1C) group.long 0x780++0x03 line.long 0x00 "GICD_IPRIORITYR224,Interrupt Priority Register 224" hexmask.long.byte 0x00 24.--31. 1. " INTID899 ,Interrupt ID899 Priority/Priority Byte Offset 899 " hexmask.long.byte 0x00 16.--23. 1. " INTID898 ,Interrupt ID898 Priority/Priority Byte Offset 898 " hexmask.long.byte 0x00 8.--15. 1. " INTID897 ,Interrupt ID897 Priority/Priority Byte Offset 897 " hexmask.long.byte 0x00 0.--7. 1. " INTID896 ,Interrupt ID896 Priority/Priority Byte Offset 896 " group.long 0x784++0x03 line.long 0x00 "GICD_IPRIORITYR225,Interrupt Priority Register 225" hexmask.long.byte 0x00 24.--31. 1. " INTID903 ,Interrupt ID903 Priority/Priority Byte Offset 903 " hexmask.long.byte 0x00 16.--23. 1. " INTID902 ,Interrupt ID902 Priority/Priority Byte Offset 902 " hexmask.long.byte 0x00 8.--15. 1. " INTID901 ,Interrupt ID901 Priority/Priority Byte Offset 901 " hexmask.long.byte 0x00 0.--7. 1. " INTID900 ,Interrupt ID900 Priority/Priority Byte Offset 900 " group.long 0x788++0x03 line.long 0x00 "GICD_IPRIORITYR226,Interrupt Priority Register 226" hexmask.long.byte 0x00 24.--31. 1. " INTID907 ,Interrupt ID907 Priority/Priority Byte Offset 907 " hexmask.long.byte 0x00 16.--23. 1. " INTID906 ,Interrupt ID906 Priority/Priority Byte Offset 906 " hexmask.long.byte 0x00 8.--15. 1. " INTID905 ,Interrupt ID905 Priority/Priority Byte Offset 905 " hexmask.long.byte 0x00 0.--7. 1. " INTID904 ,Interrupt ID904 Priority/Priority Byte Offset 904 " group.long 0x78C++0x03 line.long 0x00 "GICD_IPRIORITYR227,Interrupt Priority Register 227" hexmask.long.byte 0x00 24.--31. 1. " INTID911 ,Interrupt ID911 Priority/Priority Byte Offset 911 " hexmask.long.byte 0x00 16.--23. 1. " INTID910 ,Interrupt ID910 Priority/Priority Byte Offset 910 " hexmask.long.byte 0x00 8.--15. 1. " INTID909 ,Interrupt ID909 Priority/Priority Byte Offset 909 " hexmask.long.byte 0x00 0.--7. 1. " INTID908 ,Interrupt ID908 Priority/Priority Byte Offset 908 " group.long 0x790++0x03 line.long 0x00 "GICD_IPRIORITYR228,Interrupt Priority Register 228" hexmask.long.byte 0x00 24.--31. 1. " INTID915 ,Interrupt ID915 Priority/Priority Byte Offset 915 " hexmask.long.byte 0x00 16.--23. 1. " INTID914 ,Interrupt ID914 Priority/Priority Byte Offset 914 " hexmask.long.byte 0x00 8.--15. 1. " INTID913 ,Interrupt ID913 Priority/Priority Byte Offset 913 " hexmask.long.byte 0x00 0.--7. 1. " INTID912 ,Interrupt ID912 Priority/Priority Byte Offset 912 " group.long 0x794++0x03 line.long 0x00 "GICD_IPRIORITYR229,Interrupt Priority Register 229" hexmask.long.byte 0x00 24.--31. 1. " INTID919 ,Interrupt ID919 Priority/Priority Byte Offset 919 " hexmask.long.byte 0x00 16.--23. 1. " INTID918 ,Interrupt ID918 Priority/Priority Byte Offset 918 " hexmask.long.byte 0x00 8.--15. 1. " INTID917 ,Interrupt ID917 Priority/Priority Byte Offset 917 " hexmask.long.byte 0x00 0.--7. 1. " INTID916 ,Interrupt ID916 Priority/Priority Byte Offset 916 " group.long 0x798++0x03 line.long 0x00 "GICD_IPRIORITYR230,Interrupt Priority Register 230" hexmask.long.byte 0x00 24.--31. 1. " INTID923 ,Interrupt ID923 Priority/Priority Byte Offset 923 " hexmask.long.byte 0x00 16.--23. 1. " INTID922 ,Interrupt ID922 Priority/Priority Byte Offset 922 " hexmask.long.byte 0x00 8.--15. 1. " INTID921 ,Interrupt ID921 Priority/Priority Byte Offset 921 " hexmask.long.byte 0x00 0.--7. 1. " INTID920 ,Interrupt ID920 Priority/Priority Byte Offset 920 " group.long 0x79C++0x03 line.long 0x00 "GICD_IPRIORITYR231,Interrupt Priority Register 231" hexmask.long.byte 0x00 24.--31. 1. " INTID927 ,Interrupt ID927 Priority/Priority Byte Offset 927 " hexmask.long.byte 0x00 16.--23. 1. " INTID926 ,Interrupt ID926 Priority/Priority Byte Offset 926 " hexmask.long.byte 0x00 8.--15. 1. " INTID925 ,Interrupt ID925 Priority/Priority Byte Offset 925 " hexmask.long.byte 0x00 0.--7. 1. " INTID924 ,Interrupt ID924 Priority/Priority Byte Offset 924 " else rgroup.long 0x780++0x03 line.long 0x00 "GICD_IPRIORITYR224,Interrupt Priority Register 224" rgroup.long 0x784++0x03 line.long 0x00 "GICD_IPRIORITYR225,Interrupt Priority Register 225" rgroup.long 0x788++0x03 line.long 0x00 "GICD_IPRIORITYR226,Interrupt Priority Register 226" rgroup.long 0x78C++0x03 line.long 0x00 "GICD_IPRIORITYR227,Interrupt Priority Register 227" rgroup.long 0x790++0x03 line.long 0x00 "GICD_IPRIORITYR228,Interrupt Priority Register 228" rgroup.long 0x794++0x03 line.long 0x00 "GICD_IPRIORITYR229,Interrupt Priority Register 229" rgroup.long 0x798++0x03 line.long 0x00 "GICD_IPRIORITYR230,Interrupt Priority Register 230" rgroup.long 0x79C++0x03 line.long 0x00 "GICD_IPRIORITYR231,Interrupt Priority Register 231" endif if (((per.l(ad:(per.long(spr:0x31F30)&0xFFFC0000)+0x04))&0x0000001F)>=0x1D) group.long 0x7A0++0x03 line.long 0x00 "GICD_IPRIORITYR232,Interrupt Priority Register 232" hexmask.long.byte 0x00 24.--31. 1. " INTID931 ,Interrupt ID931 Priority/Priority Byte Offset 931 " hexmask.long.byte 0x00 16.--23. 1. " INTID930 ,Interrupt ID930 Priority/Priority Byte Offset 930 " hexmask.long.byte 0x00 8.--15. 1. " INTID929 ,Interrupt ID929 Priority/Priority Byte Offset 929 " hexmask.long.byte 0x00 0.--7. 1. " INTID928 ,Interrupt ID928 Priority/Priority Byte Offset 928 " group.long 0x7A4++0x03 line.long 0x00 "GICD_IPRIORITYR233,Interrupt Priority Register 233" hexmask.long.byte 0x00 24.--31. 1. " INTID935 ,Interrupt ID935 Priority/Priority Byte Offset 935 " hexmask.long.byte 0x00 16.--23. 1. " INTID934 ,Interrupt ID934 Priority/Priority Byte Offset 934 " hexmask.long.byte 0x00 8.--15. 1. " INTID933 ,Interrupt ID933 Priority/Priority Byte Offset 933 " hexmask.long.byte 0x00 0.--7. 1. " INTID932 ,Interrupt ID932 Priority/Priority Byte Offset 932 " group.long 0x7A8++0x03 line.long 0x00 "GICD_IPRIORITYR234,Interrupt Priority Register 234" hexmask.long.byte 0x00 24.--31. 1. " INTID939 ,Interrupt ID939 Priority/Priority Byte Offset 939 " hexmask.long.byte 0x00 16.--23. 1. " INTID938 ,Interrupt ID938 Priority/Priority Byte Offset 938 " hexmask.long.byte 0x00 8.--15. 1. " INTID937 ,Interrupt ID937 Priority/Priority Byte Offset 937 " hexmask.long.byte 0x00 0.--7. 1. " INTID936 ,Interrupt ID936 Priority/Priority Byte Offset 936 " group.long 0x7AC++0x03 line.long 0x00 "GICD_IPRIORITYR235,Interrupt Priority Register 235" hexmask.long.byte 0x00 24.--31. 1. " INTID943 ,Interrupt ID943 Priority/Priority Byte Offset 943 " hexmask.long.byte 0x00 16.--23. 1. " INTID942 ,Interrupt ID942 Priority/Priority Byte Offset 942 " hexmask.long.byte 0x00 8.--15. 1. " INTID941 ,Interrupt ID941 Priority/Priority Byte Offset 941 " hexmask.long.byte 0x00 0.--7. 1. " INTID940 ,Interrupt ID940 Priority/Priority Byte Offset 940 " group.long 0x7B0++0x03 line.long 0x00 "GICD_IPRIORITYR236,Interrupt Priority Register 236" hexmask.long.byte 0x00 24.--31. 1. " INTID947 ,Interrupt ID947 Priority/Priority Byte Offset 947 " hexmask.long.byte 0x00 16.--23. 1. " INTID946 ,Interrupt ID946 Priority/Priority Byte Offset 946 " hexmask.long.byte 0x00 8.--15. 1. " INTID945 ,Interrupt ID945 Priority/Priority Byte Offset 945 " hexmask.long.byte 0x00 0.--7. 1. " INTID944 ,Interrupt ID944 Priority/Priority Byte Offset 944 " group.long 0x7B4++0x03 line.long 0x00 "GICD_IPRIORITYR237,Interrupt Priority Register 237" hexmask.long.byte 0x00 24.--31. 1. " INTID951 ,Interrupt ID951 Priority/Priority Byte Offset 951 " hexmask.long.byte 0x00 16.--23. 1. " INTID950 ,Interrupt ID950 Priority/Priority Byte Offset 950 " hexmask.long.byte 0x00 8.--15. 1. " INTID949 ,Interrupt ID949 Priority/Priority Byte Offset 949 " hexmask.long.byte 0x00 0.--7. 1. " INTID948 ,Interrupt ID948 Priority/Priority Byte Offset 948 " group.long 0x7B8++0x03 line.long 0x00 "GICD_IPRIORITYR238,Interrupt Priority Register 238" hexmask.long.byte 0x00 24.--31. 1. " INTID955 ,Interrupt ID955 Priority/Priority Byte Offset 955 " hexmask.long.byte 0x00 16.--23. 1. " INTID954 ,Interrupt ID954 Priority/Priority Byte Offset 954 " hexmask.long.byte 0x00 8.--15. 1. " INTID953 ,Interrupt ID953 Priority/Priority Byte Offset 953 " hexmask.long.byte 0x00 0.--7. 1. " INTID952 ,Interrupt ID952 Priority/Priority Byte Offset 952 " group.long 0x7BC++0x03 line.long 0x00 "GICD_IPRIORITYR239,Interrupt Priority Register 239" hexmask.long.byte 0x00 24.--31. 1. " INTID959 ,Interrupt ID959 Priority/Priority Byte Offset 959 " hexmask.long.byte 0x00 16.--23. 1. " INTID958 ,Interrupt ID958 Priority/Priority Byte Offset 958 " hexmask.long.byte 0x00 8.--15. 1. " INTID957 ,Interrupt ID957 Priority/Priority Byte Offset 957 " hexmask.long.byte 0x00 0.--7. 1. " INTID956 ,Interrupt ID956 Priority/Priority Byte Offset 956 " else rgroup.long 0x7A0++0x03 line.long 0x00 "GICD_IPRIORITYR232,Interrupt Priority Register 232" rgroup.long 0x7A4++0x03 line.long 0x00 "GICD_IPRIORITYR233,Interrupt Priority Register 233" rgroup.long 0x7A8++0x03 line.long 0x00 "GICD_IPRIORITYR234,Interrupt Priority Register 234" rgroup.long 0x7AC++0x03 line.long 0x00 "GICD_IPRIORITYR235,Interrupt Priority Register 235" rgroup.long 0x7B0++0x03 line.long 0x00 "GICD_IPRIORITYR236,Interrupt Priority Register 236" rgroup.long 0x7B4++0x03 line.long 0x00 "GICD_IPRIORITYR237,Interrupt Priority Register 237" rgroup.long 0x7B8++0x03 line.long 0x00 "GICD_IPRIORITYR238,Interrupt Priority Register 238" rgroup.long 0x7BC++0x03 line.long 0x00 "GICD_IPRIORITYR239,Interrupt Priority Register 239" endif if (((per.l(ad:(per.long(spr:0x31F30)&0xFFFC0000)+0x04))&0x0000001F)>=0x1E) group.long 0x7C0++0x03 line.long 0x00 "GICD_IPRIORITYR240,Interrupt Priority Register 240" hexmask.long.byte 0x00 24.--31. 1. " INTID963 ,Interrupt ID963 Priority/Priority Byte Offset 963 " hexmask.long.byte 0x00 16.--23. 1. " INTID962 ,Interrupt ID962 Priority/Priority Byte Offset 962 " hexmask.long.byte 0x00 8.--15. 1. " INTID961 ,Interrupt ID961 Priority/Priority Byte Offset 961 " hexmask.long.byte 0x00 0.--7. 1. " INTID960 ,Interrupt ID960 Priority/Priority Byte Offset 960 " group.long 0x7C4++0x03 line.long 0x00 "GICD_IPRIORITYR241,Interrupt Priority Register 241" hexmask.long.byte 0x00 24.--31. 1. " INTID967 ,Interrupt ID967 Priority/Priority Byte Offset 967 " hexmask.long.byte 0x00 16.--23. 1. " INTID966 ,Interrupt ID966 Priority/Priority Byte Offset 966 " hexmask.long.byte 0x00 8.--15. 1. " INTID965 ,Interrupt ID965 Priority/Priority Byte Offset 965 " hexmask.long.byte 0x00 0.--7. 1. " INTID964 ,Interrupt ID964 Priority/Priority Byte Offset 964 " group.long 0x7C8++0x03 line.long 0x00 "GICD_IPRIORITYR242,Interrupt Priority Register 242" hexmask.long.byte 0x00 24.--31. 1. " INTID971 ,Interrupt ID971 Priority/Priority Byte Offset 971 " hexmask.long.byte 0x00 16.--23. 1. " INTID970 ,Interrupt ID970 Priority/Priority Byte Offset 970 " hexmask.long.byte 0x00 8.--15. 1. " INTID969 ,Interrupt ID969 Priority/Priority Byte Offset 969 " hexmask.long.byte 0x00 0.--7. 1. " INTID968 ,Interrupt ID968 Priority/Priority Byte Offset 968 " group.long 0x7CC++0x03 line.long 0x00 "GICD_IPRIORITYR243,Interrupt Priority Register 243" hexmask.long.byte 0x00 24.--31. 1. " INTID975 ,Interrupt ID975 Priority/Priority Byte Offset 975 " hexmask.long.byte 0x00 16.--23. 1. " INTID974 ,Interrupt ID974 Priority/Priority Byte Offset 974 " hexmask.long.byte 0x00 8.--15. 1. " INTID973 ,Interrupt ID973 Priority/Priority Byte Offset 973 " hexmask.long.byte 0x00 0.--7. 1. " INTID972 ,Interrupt ID972 Priority/Priority Byte Offset 972 " group.long 0x7D0++0x03 line.long 0x00 "GICD_IPRIORITYR244,Interrupt Priority Register 244" hexmask.long.byte 0x00 24.--31. 1. " INTID979 ,Interrupt ID979 Priority/Priority Byte Offset 979 " hexmask.long.byte 0x00 16.--23. 1. " INTID978 ,Interrupt ID978 Priority/Priority Byte Offset 978 " hexmask.long.byte 0x00 8.--15. 1. " INTID977 ,Interrupt ID977 Priority/Priority Byte Offset 977 " hexmask.long.byte 0x00 0.--7. 1. " INTID976 ,Interrupt ID976 Priority/Priority Byte Offset 976 " group.long 0x7D4++0x03 line.long 0x00 "GICD_IPRIORITYR245,Interrupt Priority Register 245" hexmask.long.byte 0x00 24.--31. 1. " INTID983 ,Interrupt ID983 Priority/Priority Byte Offset 983 " hexmask.long.byte 0x00 16.--23. 1. " INTID982 ,Interrupt ID982 Priority/Priority Byte Offset 982 " hexmask.long.byte 0x00 8.--15. 1. " INTID981 ,Interrupt ID981 Priority/Priority Byte Offset 981 " hexmask.long.byte 0x00 0.--7. 1. " INTID980 ,Interrupt ID980 Priority/Priority Byte Offset 980 " group.long 0x7D8++0x03 line.long 0x00 "GICD_IPRIORITYR246,Interrupt Priority Register 246" hexmask.long.byte 0x00 24.--31. 1. " INTID987 ,Interrupt ID987 Priority/Priority Byte Offset 987 " hexmask.long.byte 0x00 16.--23. 1. " INTID986 ,Interrupt ID986 Priority/Priority Byte Offset 986 " hexmask.long.byte 0x00 8.--15. 1. " INTID985 ,Interrupt ID985 Priority/Priority Byte Offset 985 " hexmask.long.byte 0x00 0.--7. 1. " INTID984 ,Interrupt ID984 Priority/Priority Byte Offset 984 " group.long 0x7DC++0x03 line.long 0x00 "GICD_IPRIORITYR247,Interrupt Priority Register 247" hexmask.long.byte 0x00 24.--31. 1. " INTID991 ,Interrupt ID991 Priority/Priority Byte Offset 991 " hexmask.long.byte 0x00 16.--23. 1. " INTID990 ,Interrupt ID990 Priority/Priority Byte Offset 990 " hexmask.long.byte 0x00 8.--15. 1. " INTID989 ,Interrupt ID989 Priority/Priority Byte Offset 989 " hexmask.long.byte 0x00 0.--7. 1. " INTID988 ,Interrupt ID988 Priority/Priority Byte Offset 988 " else rgroup.long 0x7C0++0x03 line.long 0x00 "GICD_IPRIORITYR240,Interrupt Priority Register 240" rgroup.long 0x7C4++0x03 line.long 0x00 "GICD_IPRIORITYR241,Interrupt Priority Register 241" rgroup.long 0x7C8++0x03 line.long 0x00 "GICD_IPRIORITYR242,Interrupt Priority Register 242" rgroup.long 0x7CC++0x03 line.long 0x00 "GICD_IPRIORITYR243,Interrupt Priority Register 243" rgroup.long 0x7D0++0x03 line.long 0x00 "GICD_IPRIORITYR244,Interrupt Priority Register 244" rgroup.long 0x7D4++0x03 line.long 0x00 "GICD_IPRIORITYR245,Interrupt Priority Register 245" rgroup.long 0x7D8++0x03 line.long 0x00 "GICD_IPRIORITYR246,Interrupt Priority Register 246" rgroup.long 0x7DC++0x03 line.long 0x00 "GICD_IPRIORITYR247,Interrupt Priority Register 247" endif if (((per.l(ad:(per.long(spr:0x31F30)&0xFFFC0000)+0x04))&0x0000001F)>=0x1F) group.long 0x7E0++0x03 line.long 0x00 "GICD_IPRIORITYR248,Interrupt Priority Register 248" hexmask.long.byte 0x00 24.--31. 1. " INTID995 ,Interrupt ID995 Priority/Priority Byte Offset 995 " hexmask.long.byte 0x00 16.--23. 1. " INTID994 ,Interrupt ID994 Priority/Priority Byte Offset 994 " hexmask.long.byte 0x00 8.--15. 1. " INTID993 ,Interrupt ID993 Priority/Priority Byte Offset 993 " hexmask.long.byte 0x00 0.--7. 1. " INTID992 ,Interrupt ID992 Priority/Priority Byte Offset 992 " group.long 0x7E4++0x03 line.long 0x00 "GICD_IPRIORITYR249,Interrupt Priority Register 249" hexmask.long.byte 0x00 24.--31. 1. " INTID999 ,Interrupt ID999 Priority/Priority Byte Offset 999 " hexmask.long.byte 0x00 16.--23. 1. " INTID998 ,Interrupt ID998 Priority/Priority Byte Offset 998 " hexmask.long.byte 0x00 8.--15. 1. " INTID997 ,Interrupt ID997 Priority/Priority Byte Offset 997 " hexmask.long.byte 0x00 0.--7. 1. " INTID996 ,Interrupt ID996 Priority/Priority Byte Offset 996 " group.long 0x7E8++0x03 line.long 0x00 "GICD_IPRIORITYR250,Interrupt Priority Register 250" hexmask.long.byte 0x00 24.--31. 1. " INTID1003 ,Interrupt ID1003 Priority/Priority Byte Offset 1003" hexmask.long.byte 0x00 16.--23. 1. " INTID1002 ,Interrupt ID1002 Priority/Priority Byte Offset 1002" hexmask.long.byte 0x00 8.--15. 1. " INTID1001 ,Interrupt ID1001 Priority/Priority Byte Offset 1001" hexmask.long.byte 0x00 0.--7. 1. " INTID1000 ,Interrupt ID1000 Priority/Priority Byte Offset 1000" group.long 0x7EC++0x03 line.long 0x00 "GICD_IPRIORITYR251,Interrupt Priority Register 251" hexmask.long.byte 0x00 24.--31. 1. " INTID1007 ,Interrupt ID1007 Priority/Priority Byte Offset 1007" hexmask.long.byte 0x00 16.--23. 1. " INTID1006 ,Interrupt ID1006 Priority/Priority Byte Offset 1006" hexmask.long.byte 0x00 8.--15. 1. " INTID1005 ,Interrupt ID1005 Priority/Priority Byte Offset 1005" hexmask.long.byte 0x00 0.--7. 1. " INTID1004 ,Interrupt ID1004 Priority/Priority Byte Offset 1004" group.long 0x7F0++0x03 line.long 0x00 "GICD_IPRIORITYR252,Interrupt Priority Register 252" hexmask.long.byte 0x00 24.--31. 1. " INTID1011 ,Interrupt ID1011 Priority/Priority Byte Offset 1011" hexmask.long.byte 0x00 16.--23. 1. " INTID1010 ,Interrupt ID1010 Priority/Priority Byte Offset 1010" hexmask.long.byte 0x00 8.--15. 1. " INTID1009 ,Interrupt ID1009 Priority/Priority Byte Offset 1009" hexmask.long.byte 0x00 0.--7. 1. " INTID1008 ,Interrupt ID1008 Priority/Priority Byte Offset 1008" group.long 0x7F4++0x03 line.long 0x00 "GICD_IPRIORITYR253,Interrupt Priority Register 253" hexmask.long.byte 0x00 24.--31. 1. " INTID1015 ,Interrupt ID1015 Priority/Priority Byte Offset 1015" hexmask.long.byte 0x00 16.--23. 1. " INTID1014 ,Interrupt ID1014 Priority/Priority Byte Offset 1014" hexmask.long.byte 0x00 8.--15. 1. " INTID1013 ,Interrupt ID1013 Priority/Priority Byte Offset 1013" hexmask.long.byte 0x00 0.--7. 1. " INTID1012 ,Interrupt ID1012 Priority/Priority Byte Offset 1012" group.long 0x7F8++0x03 line.long 0x00 "GICD_IPRIORITYR254,Interrupt Priority Register 254" hexmask.long.byte 0x00 24.--31. 1. " INTID1019 ,Interrupt ID1019 Priority/Priority Byte Offset 1019" hexmask.long.byte 0x00 16.--23. 1. " INTID1018 ,Interrupt ID1018 Priority/Priority Byte Offset 1018" hexmask.long.byte 0x00 8.--15. 1. " INTID1017 ,Interrupt ID1017 Priority/Priority Byte Offset 1017" hexmask.long.byte 0x00 0.--7. 1. " INTID1016 ,Interrupt ID1016 Priority/Priority Byte Offset 1016" else rgroup.long 0x7E0++0x03 line.long 0x00 "GICD_IPRIORITYR248,Interrupt Priority Register 248" rgroup.long 0x7E4++0x03 line.long 0x00 "GICD_IPRIORITYR249,Interrupt Priority Register 249" rgroup.long 0x7E8++0x03 line.long 0x00 "GICD_IPRIORITYR250,Interrupt Priority Register 250" rgroup.long 0x7EC++0x03 line.long 0x00 "GICD_IPRIORITYR251,Interrupt Priority Register 251" rgroup.long 0x7F0++0x03 line.long 0x00 "GICD_IPRIORITYR252,Interrupt Priority Register 252" rgroup.long 0x7F4++0x03 line.long 0x00 "GICD_IPRIORITYR253,Interrupt Priority Register 253" rgroup.long 0x7F8++0x03 line.long 0x00 "GICD_IPRIORITYR254,Interrupt Priority Register 254" endif tree.end width 19. tree "Processor Targets Registers" if (((per.l(ad:(per.long(spr:0x31F30)&0xFFFC0000)+0x04))&0x000000E0)>0x1) rgroup.long 0x800++0x03 line.long 0x00 "GICD_ITARGETSR0,Interrupt Processor Targets Register 0" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO3 ,CPU Targets Byte Offset 3 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO2 ,CPU Targets Byte Offset 2 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO1 ,CPU Targets Byte Offset 1 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO0 ,CPU Targets Byte Offset 0 " rgroup.long 0x804++0x03 line.long 0x00 "GICD_ITARGETSR1,Interrupt Processor Targets Register 1" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO7 ,CPU Targets Byte Offset 7 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO6 ,CPU Targets Byte Offset 6 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO5 ,CPU Targets Byte Offset 5 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO4 ,CPU Targets Byte Offset 4 " rgroup.long 0x808++0x03 line.long 0x00 "GICD_ITARGETSR2,Interrupt Processor Targets Register 2" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO11 ,CPU Targets Byte Offset 11 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO10 ,CPU Targets Byte Offset 10 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO9 ,CPU Targets Byte Offset 9 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO8 ,CPU Targets Byte Offset 8 " rgroup.long 0x80C++0x03 line.long 0x00 "GICD_ITARGETSR3,Interrupt Processor Targets Register 3" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO15 ,CPU Targets Byte Offset 15 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO14 ,CPU Targets Byte Offset 14 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO13 ,CPU Targets Byte Offset 13 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO12 ,CPU Targets Byte Offset 12 " rgroup.long 0x810++0x03 line.long 0x00 "GICD_ITARGETSR4,Interrupt Processor Targets Register 4" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO19 ,CPU Targets Byte Offset 19 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO18 ,CPU Targets Byte Offset 18 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO17 ,CPU Targets Byte Offset 17 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO16 ,CPU Targets Byte Offset 16 " rgroup.long 0x814++0x03 line.long 0x00 "GICD_ITARGETSR5,Interrupt Processor Targets Register 5" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO23 ,CPU Targets Byte Offset 23 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO22 ,CPU Targets Byte Offset 22 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO21 ,CPU Targets Byte Offset 21 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO20 ,CPU Targets Byte Offset 20 " rgroup.long 0x818++0x03 line.long 0x00 "GICD_ITARGETSR6,Interrupt Processor Targets Register 6" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO27 ,CPU Targets Byte Offset 27 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO26 ,CPU Targets Byte Offset 26 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO25 ,CPU Targets Byte Offset 25 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO24 ,CPU Targets Byte Offset 24 " rgroup.long 0x81C++0x03 line.long 0x00 "GICD_ITARGETSR7,Interrupt Processor Targets Register 7" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO31 ,CPU Targets Byte Offset 31 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO30 ,CPU Targets Byte Offset 30 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO29 ,CPU Targets Byte Offset 29 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO28 ,CPU Targets Byte Offset 28 " if (((per.l(ad:(per.long(spr:0x31F30)&0xFFFC0000)+0x04))&0x0000001F)>=0x01) group.long 0x820++0x03 line.long 0x00 "GICD_ITARGETSR8,Interrupt Processor Targets Register 8" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO35 ,CPU Targets Byte Offset 35 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO34 ,CPU Targets Byte Offset 34 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO33 ,CPU Targets Byte Offset 33 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO32 ,CPU Targets Byte Offset 32 " group.long 0x824++0x03 line.long 0x00 "GICD_ITARGETSR9,Interrupt Processor Targets Register 9" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO39 ,CPU Targets Byte Offset 39 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO38 ,CPU Targets Byte Offset 38 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO37 ,CPU Targets Byte Offset 37 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO36 ,CPU Targets Byte Offset 36 " group.long 0x828++0x03 line.long 0x00 "GICD_ITARGETSR10,Interrupt Processor Targets Register 10" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO43 ,CPU Targets Byte Offset 43 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO42 ,CPU Targets Byte Offset 42 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO41 ,CPU Targets Byte Offset 41 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO40 ,CPU Targets Byte Offset 40 " group.long 0x82C++0x03 line.long 0x00 "GICD_ITARGETSR11,Interrupt Processor Targets Register 11" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO47 ,CPU Targets Byte Offset 47 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO46 ,CPU Targets Byte Offset 46 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO45 ,CPU Targets Byte Offset 45 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO44 ,CPU Targets Byte Offset 44 " group.long 0x830++0x03 line.long 0x00 "GICD_ITARGETSR12,Interrupt Processor Targets Register 12" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO51 ,CPU Targets Byte Offset 51 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO50 ,CPU Targets Byte Offset 50 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO49 ,CPU Targets Byte Offset 49 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO48 ,CPU Targets Byte Offset 48 " group.long 0x834++0x03 line.long 0x00 "GICD_ITARGETSR13,Interrupt Processor Targets Register 13" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO55 ,CPU Targets Byte Offset 55 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO54 ,CPU Targets Byte Offset 54 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO53 ,CPU Targets Byte Offset 53 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO52 ,CPU Targets Byte Offset 52 " group.long 0x838++0x03 line.long 0x00 "GICD_ITARGETSR14,Interrupt Processor Targets Register 14" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO59 ,CPU Targets Byte Offset 59 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO58 ,CPU Targets Byte Offset 58 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO57 ,CPU Targets Byte Offset 57 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO56 ,CPU Targets Byte Offset 56 " group.long 0x83C++0x03 line.long 0x00 "GICD_ITARGETSR15,Interrupt Processor Targets Register 15" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO63 ,CPU Targets Byte Offset 63 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO62 ,CPU Targets Byte Offset 62 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO61 ,CPU Targets Byte Offset 61 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO60 ,CPU Targets Byte Offset 60 " else rgroup.long 0x820++0x03 line.long 0x00 "GICD_ITARGETSR8,Interrupt Processor Targets Register 8" rgroup.long 0x824++0x03 line.long 0x00 "GICD_ITARGETSR9,Interrupt Processor Targets Register 9" rgroup.long 0x828++0x03 line.long 0x00 "GICD_ITARGETSR10,Interrupt Processor Targets Register 10" rgroup.long 0x82C++0x03 line.long 0x00 "GICD_ITARGETSR11,Interrupt Processor Targets Register 11" rgroup.long 0x830++0x03 line.long 0x00 "GICD_ITARGETSR12,Interrupt Processor Targets Register 12" rgroup.long 0x834++0x03 line.long 0x00 "GICD_ITARGETSR13,Interrupt Processor Targets Register 13" rgroup.long 0x838++0x03 line.long 0x00 "GICD_ITARGETSR14,Interrupt Processor Targets Register 14" rgroup.long 0x83C++0x03 line.long 0x00 "GICD_ITARGETSR15,Interrupt Processor Targets Register 15" endif if (((per.l(ad:(per.long(spr:0x31F30)&0xFFFC0000)+0x04))&0x0000001F)>=0x02) group.long 0x840++0x03 line.long 0x00 "GICD_ITARGETSR16,Interrupt Processor Targets Register 16" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO67 ,CPU Targets Byte Offset 67 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO66 ,CPU Targets Byte Offset 66 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO65 ,CPU Targets Byte Offset 65 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO64 ,CPU Targets Byte Offset 64 " group.long 0x844++0x03 line.long 0x00 "GICD_ITARGETSR17,Interrupt Processor Targets Register 17" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO71 ,CPU Targets Byte Offset 71 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO70 ,CPU Targets Byte Offset 70 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO69 ,CPU Targets Byte Offset 69 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO68 ,CPU Targets Byte Offset 68 " group.long 0x848++0x03 line.long 0x00 "GICD_ITARGETSR18,Interrupt Processor Targets Register 18" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO75 ,CPU Targets Byte Offset 75 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO74 ,CPU Targets Byte Offset 74 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO73 ,CPU Targets Byte Offset 73 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO72 ,CPU Targets Byte Offset 72 " group.long 0x84C++0x03 line.long 0x00 "GICD_ITARGETSR19,Interrupt Processor Targets Register 19" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO79 ,CPU Targets Byte Offset 79 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO78 ,CPU Targets Byte Offset 78 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO77 ,CPU Targets Byte Offset 77 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO76 ,CPU Targets Byte Offset 76 " group.long 0x850++0x03 line.long 0x00 "GICD_ITARGETSR20,Interrupt Processor Targets Register 20" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO83 ,CPU Targets Byte Offset 83 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO82 ,CPU Targets Byte Offset 82 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO81 ,CPU Targets Byte Offset 81 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO80 ,CPU Targets Byte Offset 80 " group.long 0x854++0x03 line.long 0x00 "GICD_ITARGETSR21,Interrupt Processor Targets Register 21" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO87 ,CPU Targets Byte Offset 87 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO86 ,CPU Targets Byte Offset 86 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO85 ,CPU Targets Byte Offset 85 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO84 ,CPU Targets Byte Offset 84 " group.long 0x858++0x03 line.long 0x00 "GICD_ITARGETSR22,Interrupt Processor Targets Register 22" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO91 ,CPU Targets Byte Offset 91 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO90 ,CPU Targets Byte Offset 90 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO89 ,CPU Targets Byte Offset 89 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO88 ,CPU Targets Byte Offset 88 " group.long 0x85C++0x03 line.long 0x00 "GICD_ITARGETSR23,Interrupt Processor Targets Register 23" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO95 ,CPU Targets Byte Offset 95 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO94 ,CPU Targets Byte Offset 94 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO93 ,CPU Targets Byte Offset 93 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO92 ,CPU Targets Byte Offset 92 " else rgroup.long 0x840++0x03 line.long 0x00 "GICD_ITARGETSR16,Interrupt Processor Targets Register 16" rgroup.long 0x844++0x03 line.long 0x00 "GICD_ITARGETSR17,Interrupt Processor Targets Register 17" rgroup.long 0x848++0x03 line.long 0x00 "GICD_ITARGETSR18,Interrupt Processor Targets Register 18" rgroup.long 0x84C++0x03 line.long 0x00 "GICD_ITARGETSR19,Interrupt Processor Targets Register 19" rgroup.long 0x850++0x03 line.long 0x00 "GICD_ITARGETSR20,Interrupt Processor Targets Register 20" rgroup.long 0x854++0x03 line.long 0x00 "GICD_ITARGETSR21,Interrupt Processor Targets Register 21" rgroup.long 0x858++0x03 line.long 0x00 "GICD_ITARGETSR22,Interrupt Processor Targets Register 22" rgroup.long 0x85C++0x03 line.long 0x00 "GICD_ITARGETSR23,Interrupt Processor Targets Register 23" endif if (((per.l(ad:(per.long(spr:0x31F30)&0xFFFC0000)+0x04))&0x0000001F)>=0x03) group.long 0x860++0x03 line.long 0x00 "GICD_ITARGETSR24,Interrupt Processor Targets Register 24" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO99 ,CPU Targets Byte Offset 99 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO98 ,CPU Targets Byte Offset 98 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO97 ,CPU Targets Byte Offset 97 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO96 ,CPU Targets Byte Offset 96 " group.long 0x864++0x03 line.long 0x00 "GICD_ITARGETSR25,Interrupt Processor Targets Register 25" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO103 ,CPU Targets Byte Offset 103 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO102 ,CPU Targets Byte Offset 102 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO101 ,CPU Targets Byte Offset 101 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO100 ,CPU Targets Byte Offset 100 " group.long 0x868++0x03 line.long 0x00 "GICD_ITARGETSR26,Interrupt Processor Targets Register 26" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO107 ,CPU Targets Byte Offset 107 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO106 ,CPU Targets Byte Offset 106 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO105 ,CPU Targets Byte Offset 105 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO104 ,CPU Targets Byte Offset 104 " group.long 0x86C++0x03 line.long 0x00 "GICD_ITARGETSR27,Interrupt Processor Targets Register 27" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO111 ,CPU Targets Byte Offset 111 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO110 ,CPU Targets Byte Offset 110 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO109 ,CPU Targets Byte Offset 109 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO108 ,CPU Targets Byte Offset 108 " group.long 0x870++0x03 line.long 0x00 "GICD_ITARGETSR28,Interrupt Processor Targets Register 28" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO115 ,CPU Targets Byte Offset 115 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO114 ,CPU Targets Byte Offset 114 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO113 ,CPU Targets Byte Offset 113 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO112 ,CPU Targets Byte Offset 112 " group.long 0x874++0x03 line.long 0x00 "GICD_ITARGETSR29,Interrupt Processor Targets Register 29" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO119 ,CPU Targets Byte Offset 119 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO118 ,CPU Targets Byte Offset 118 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO117 ,CPU Targets Byte Offset 117 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO116 ,CPU Targets Byte Offset 116 " group.long 0x878++0x03 line.long 0x00 "GICD_ITARGETSR30,Interrupt Processor Targets Register 30" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO123 ,CPU Targets Byte Offset 123 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO122 ,CPU Targets Byte Offset 122 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO121 ,CPU Targets Byte Offset 121 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO120 ,CPU Targets Byte Offset 120 " group.long 0x87C++0x03 line.long 0x00 "GICD_ITARGETSR31,Interrupt Processor Targets Register 31" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO127 ,CPU Targets Byte Offset 127 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO126 ,CPU Targets Byte Offset 126 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO125 ,CPU Targets Byte Offset 125 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO124 ,CPU Targets Byte Offset 124 " else rgroup.long 0x860++0x03 line.long 0x00 "GICD_ITARGETSR24,Interrupt Processor Targets Register 24" rgroup.long 0x864++0x03 line.long 0x00 "GICD_ITARGETSR25,Interrupt Processor Targets Register 25" rgroup.long 0x868++0x03 line.long 0x00 "GICD_ITARGETSR26,Interrupt Processor Targets Register 26" rgroup.long 0x86C++0x03 line.long 0x00 "GICD_ITARGETSR27,Interrupt Processor Targets Register 27" rgroup.long 0x870++0x03 line.long 0x00 "GICD_ITARGETSR28,Interrupt Processor Targets Register 28" rgroup.long 0x874++0x03 line.long 0x00 "GICD_ITARGETSR29,Interrupt Processor Targets Register 29" rgroup.long 0x878++0x03 line.long 0x00 "GICD_ITARGETSR30,Interrupt Processor Targets Register 30" rgroup.long 0x87C++0x03 line.long 0x00 "GICD_ITARGETSR31,Interrupt Processor Targets Register 31" endif if (((per.l(ad:(per.long(spr:0x31F30)&0xFFFC0000)+0x04))&0x0000001F)>=0x04) group.long 0x880++0x03 line.long 0x00 "GICD_ITARGETSR32,Interrupt Processor Targets Register 32" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO131 ,CPU Targets Byte Offset 131 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO130 ,CPU Targets Byte Offset 130 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO129 ,CPU Targets Byte Offset 129 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO128 ,CPU Targets Byte Offset 128 " group.long 0x884++0x03 line.long 0x00 "GICD_ITARGETSR33,Interrupt Processor Targets Register 33" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO135 ,CPU Targets Byte Offset 135 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO134 ,CPU Targets Byte Offset 134 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO133 ,CPU Targets Byte Offset 133 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO132 ,CPU Targets Byte Offset 132 " group.long 0x888++0x03 line.long 0x00 "GICD_ITARGETSR34,Interrupt Processor Targets Register 34" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO139 ,CPU Targets Byte Offset 139 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO138 ,CPU Targets Byte Offset 138 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO137 ,CPU Targets Byte Offset 137 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO136 ,CPU Targets Byte Offset 136 " group.long 0x88C++0x03 line.long 0x00 "GICD_ITARGETSR35,Interrupt Processor Targets Register 35" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO143 ,CPU Targets Byte Offset 143 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO142 ,CPU Targets Byte Offset 142 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO141 ,CPU Targets Byte Offset 141 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO140 ,CPU Targets Byte Offset 140 " group.long 0x890++0x03 line.long 0x00 "GICD_ITARGETSR36,Interrupt Processor Targets Register 36" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO147 ,CPU Targets Byte Offset 147 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO146 ,CPU Targets Byte Offset 146 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO145 ,CPU Targets Byte Offset 145 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO144 ,CPU Targets Byte Offset 144 " group.long 0x894++0x03 line.long 0x00 "GICD_ITARGETSR37,Interrupt Processor Targets Register 37" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO151 ,CPU Targets Byte Offset 151 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO150 ,CPU Targets Byte Offset 150 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO149 ,CPU Targets Byte Offset 149 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO148 ,CPU Targets Byte Offset 148 " group.long 0x898++0x03 line.long 0x00 "GICD_ITARGETSR38,Interrupt Processor Targets Register 38" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO155 ,CPU Targets Byte Offset 155 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO154 ,CPU Targets Byte Offset 154 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO153 ,CPU Targets Byte Offset 153 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO152 ,CPU Targets Byte Offset 152 " group.long 0x89C++0x03 line.long 0x00 "GICD_ITARGETSR39,Interrupt Processor Targets Register 39" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO159 ,CPU Targets Byte Offset 159 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO158 ,CPU Targets Byte Offset 158 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO157 ,CPU Targets Byte Offset 157 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO156 ,CPU Targets Byte Offset 156 " else rgroup.long 0x880++0x03 line.long 0x00 "GICD_ITARGETSR32,Interrupt Processor Targets Register 32" rgroup.long 0x884++0x03 line.long 0x00 "GICD_ITARGETSR33,Interrupt Processor Targets Register 33" rgroup.long 0x888++0x03 line.long 0x00 "GICD_ITARGETSR34,Interrupt Processor Targets Register 34" rgroup.long 0x88C++0x03 line.long 0x00 "GICD_ITARGETSR35,Interrupt Processor Targets Register 35" rgroup.long 0x890++0x03 line.long 0x00 "GICD_ITARGETSR36,Interrupt Processor Targets Register 36" rgroup.long 0x894++0x03 line.long 0x00 "GICD_ITARGETSR37,Interrupt Processor Targets Register 37" rgroup.long 0x898++0x03 line.long 0x00 "GICD_ITARGETSR38,Interrupt Processor Targets Register 38" rgroup.long 0x89C++0x03 line.long 0x00 "GICD_ITARGETSR39,Interrupt Processor Targets Register 39" endif if (((per.l(ad:(per.long(spr:0x31F30)&0xFFFC0000)+0x04))&0x0000001F)>=0x05) group.long 0x8A0++0x03 line.long 0x00 "GICD_ITARGETSR40,Interrupt Processor Targets Register 40" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO163 ,CPU Targets Byte Offset 163 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO162 ,CPU Targets Byte Offset 162 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO161 ,CPU Targets Byte Offset 161 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO160 ,CPU Targets Byte Offset 160 " group.long 0x8A4++0x03 line.long 0x00 "GICD_ITARGETSR41,Interrupt Processor Targets Register 41" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO167 ,CPU Targets Byte Offset 167 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO166 ,CPU Targets Byte Offset 166 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO165 ,CPU Targets Byte Offset 165 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO164 ,CPU Targets Byte Offset 164 " group.long 0x8A8++0x03 line.long 0x00 "GICD_ITARGETSR42,Interrupt Processor Targets Register 42" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO171 ,CPU Targets Byte Offset 171 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO170 ,CPU Targets Byte Offset 170 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO169 ,CPU Targets Byte Offset 169 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO168 ,CPU Targets Byte Offset 168 " group.long 0x8AC++0x03 line.long 0x00 "GICD_ITARGETSR43,Interrupt Processor Targets Register 43" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO175 ,CPU Targets Byte Offset 175 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO174 ,CPU Targets Byte Offset 174 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO173 ,CPU Targets Byte Offset 173 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO172 ,CPU Targets Byte Offset 172 " group.long 0x8B0++0x03 line.long 0x00 "GICD_ITARGETSR44,Interrupt Processor Targets Register 44" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO179 ,CPU Targets Byte Offset 179 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO178 ,CPU Targets Byte Offset 178 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO177 ,CPU Targets Byte Offset 177 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO176 ,CPU Targets Byte Offset 176 " group.long 0x8B4++0x03 line.long 0x00 "GICD_ITARGETSR45,Interrupt Processor Targets Register 45" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO183 ,CPU Targets Byte Offset 183 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO182 ,CPU Targets Byte Offset 182 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO181 ,CPU Targets Byte Offset 181 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO180 ,CPU Targets Byte Offset 180 " group.long 0x8B8++0x03 line.long 0x00 "GICD_ITARGETSR46,Interrupt Processor Targets Register 46" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO187 ,CPU Targets Byte Offset 187 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO186 ,CPU Targets Byte Offset 186 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO185 ,CPU Targets Byte Offset 185 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO184 ,CPU Targets Byte Offset 184 " group.long 0x8BC++0x03 line.long 0x00 "GICD_ITARGETSR47,Interrupt Processor Targets Register 47" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO191 ,CPU Targets Byte Offset 191 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO190 ,CPU Targets Byte Offset 190 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO189 ,CPU Targets Byte Offset 189 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO188 ,CPU Targets Byte Offset 188 " else rgroup.long 0x8A0++0x03 line.long 0x00 "GICD_ITARGETSR40,Interrupt Processor Targets Register 40" rgroup.long 0x8A4++0x03 line.long 0x00 "GICD_ITARGETSR41,Interrupt Processor Targets Register 41" rgroup.long 0x8A8++0x03 line.long 0x00 "GICD_ITARGETSR42,Interrupt Processor Targets Register 42" rgroup.long 0x8AC++0x03 line.long 0x00 "GICD_ITARGETSR43,Interrupt Processor Targets Register 43" rgroup.long 0x8B0++0x03 line.long 0x00 "GICD_ITARGETSR44,Interrupt Processor Targets Register 44" rgroup.long 0x8B4++0x03 line.long 0x00 "GICD_ITARGETSR45,Interrupt Processor Targets Register 45" rgroup.long 0x8B8++0x03 line.long 0x00 "GICD_ITARGETSR46,Interrupt Processor Targets Register 46" rgroup.long 0x8BC++0x03 line.long 0x00 "GICD_ITARGETSR47,Interrupt Processor Targets Register 47" endif if (((per.l(ad:(per.long(spr:0x31F30)&0xFFFC0000)+0x04))&0x0000001F)>=0x06) group.long 0x8C0++0x03 line.long 0x00 "GICD_ITARGETSR48,Interrupt Processor Targets Register 48" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO195 ,CPU Targets Byte Offset 195 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO194 ,CPU Targets Byte Offset 194 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO193 ,CPU Targets Byte Offset 193 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO192 ,CPU Targets Byte Offset 192 " group.long 0x8C4++0x03 line.long 0x00 "GICD_ITARGETSR49,Interrupt Processor Targets Register 49" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO199 ,CPU Targets Byte Offset 199 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO198 ,CPU Targets Byte Offset 198 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO197 ,CPU Targets Byte Offset 197 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO196 ,CPU Targets Byte Offset 196 " group.long 0x8C8++0x03 line.long 0x00 "GICD_ITARGETSR50,Interrupt Processor Targets Register 50" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO203 ,CPU Targets Byte Offset 203 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO202 ,CPU Targets Byte Offset 202 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO201 ,CPU Targets Byte Offset 201 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO200 ,CPU Targets Byte Offset 200 " group.long 0x8CC++0x03 line.long 0x00 "GICD_ITARGETSR51,Interrupt Processor Targets Register 51" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO207 ,CPU Targets Byte Offset 207 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO206 ,CPU Targets Byte Offset 206 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO205 ,CPU Targets Byte Offset 205 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO204 ,CPU Targets Byte Offset 204 " group.long 0x8D0++0x03 line.long 0x00 "GICD_ITARGETSR52,Interrupt Processor Targets Register 52" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO211 ,CPU Targets Byte Offset 211 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO210 ,CPU Targets Byte Offset 210 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO209 ,CPU Targets Byte Offset 209 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO208 ,CPU Targets Byte Offset 208 " group.long 0x8D4++0x03 line.long 0x00 "GICD_ITARGETSR53,Interrupt Processor Targets Register 53" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO215 ,CPU Targets Byte Offset 215 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO214 ,CPU Targets Byte Offset 214 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO213 ,CPU Targets Byte Offset 213 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO212 ,CPU Targets Byte Offset 212 " group.long 0x8D8++0x03 line.long 0x00 "GICD_ITARGETSR54,Interrupt Processor Targets Register 54" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO219 ,CPU Targets Byte Offset 219 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO218 ,CPU Targets Byte Offset 218 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO217 ,CPU Targets Byte Offset 217 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO216 ,CPU Targets Byte Offset 216 " group.long 0x8DC++0x03 line.long 0x00 "GICD_ITARGETSR55,Interrupt Processor Targets Register 55" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO223 ,CPU Targets Byte Offset 223 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO222 ,CPU Targets Byte Offset 222 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO221 ,CPU Targets Byte Offset 221 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO220 ,CPU Targets Byte Offset 220 " else rgroup.long 0x8C0++0x03 line.long 0x00 "GICD_ITARGETSR48,Interrupt Processor Targets Register 48" rgroup.long 0x8C4++0x03 line.long 0x00 "GICD_ITARGETSR49,Interrupt Processor Targets Register 49" rgroup.long 0x8C8++0x03 line.long 0x00 "GICD_ITARGETSR50,Interrupt Processor Targets Register 50" rgroup.long 0x8CC++0x03 line.long 0x00 "GICD_ITARGETSR51,Interrupt Processor Targets Register 51" rgroup.long 0x8D0++0x03 line.long 0x00 "GICD_ITARGETSR52,Interrupt Processor Targets Register 52" rgroup.long 0x8D4++0x03 line.long 0x00 "GICD_ITARGETSR53,Interrupt Processor Targets Register 53" rgroup.long 0x8D8++0x03 line.long 0x00 "GICD_ITARGETSR54,Interrupt Processor Targets Register 54" rgroup.long 0x8DC++0x03 line.long 0x00 "GICD_ITARGETSR55,Interrupt Processor Targets Register 55" endif if (((per.l(ad:(per.long(spr:0x31F30)&0xFFFC0000)+0x04))&0x0000001F)>=0x07) group.long 0x8E0++0x03 line.long 0x00 "GICD_ITARGETSR56,Interrupt Processor Targets Register 56" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO227 ,CPU Targets Byte Offset 227 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO226 ,CPU Targets Byte Offset 226 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO225 ,CPU Targets Byte Offset 225 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO224 ,CPU Targets Byte Offset 224 " group.long 0x8E4++0x03 line.long 0x00 "GICD_ITARGETSR57,Interrupt Processor Targets Register 57" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO231 ,CPU Targets Byte Offset 231 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO230 ,CPU Targets Byte Offset 230 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO229 ,CPU Targets Byte Offset 229 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO228 ,CPU Targets Byte Offset 228 " group.long 0x8E8++0x03 line.long 0x00 "GICD_ITARGETSR58,Interrupt Processor Targets Register 58" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO235 ,CPU Targets Byte Offset 235 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO234 ,CPU Targets Byte Offset 234 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO233 ,CPU Targets Byte Offset 233 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO232 ,CPU Targets Byte Offset 232 " group.long 0x8EC++0x03 line.long 0x00 "GICD_ITARGETSR59,Interrupt Processor Targets Register 59" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO239 ,CPU Targets Byte Offset 239 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO238 ,CPU Targets Byte Offset 238 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO237 ,CPU Targets Byte Offset 237 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO236 ,CPU Targets Byte Offset 236 " group.long 0x8F0++0x03 line.long 0x00 "GICD_ITARGETSR60,Interrupt Processor Targets Register 60" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO243 ,CPU Targets Byte Offset 243 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO242 ,CPU Targets Byte Offset 242 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO241 ,CPU Targets Byte Offset 241 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO240 ,CPU Targets Byte Offset 240 " group.long 0x8F4++0x03 line.long 0x00 "GICD_ITARGETSR61,Interrupt Processor Targets Register 61" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO247 ,CPU Targets Byte Offset 247 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO246 ,CPU Targets Byte Offset 246 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO245 ,CPU Targets Byte Offset 245 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO244 ,CPU Targets Byte Offset 244 " group.long 0x8F8++0x03 line.long 0x00 "GICD_ITARGETSR62,Interrupt Processor Targets Register 62" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO251 ,CPU Targets Byte Offset 251 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO250 ,CPU Targets Byte Offset 250 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO249 ,CPU Targets Byte Offset 249 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO248 ,CPU Targets Byte Offset 248 " group.long 0x8FC++0x03 line.long 0x00 "GICD_ITARGETSR63,Interrupt Processor Targets Register 63" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO255 ,CPU Targets Byte Offset 255 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO254 ,CPU Targets Byte Offset 254 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO253 ,CPU Targets Byte Offset 253 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO252 ,CPU Targets Byte Offset 252 " else rgroup.long 0x8E0++0x03 line.long 0x00 "GICD_ITARGETSR56,Interrupt Processor Targets Register 56" rgroup.long 0x8E4++0x03 line.long 0x00 "GICD_ITARGETSR57,Interrupt Processor Targets Register 57" rgroup.long 0x8E8++0x03 line.long 0x00 "GICD_ITARGETSR58,Interrupt Processor Targets Register 58" rgroup.long 0x8EC++0x03 line.long 0x00 "GICD_ITARGETSR59,Interrupt Processor Targets Register 59" rgroup.long 0x8F0++0x03 line.long 0x00 "GICD_ITARGETSR60,Interrupt Processor Targets Register 60" rgroup.long 0x8F4++0x03 line.long 0x00 "GICD_ITARGETSR61,Interrupt Processor Targets Register 61" rgroup.long 0x8F8++0x03 line.long 0x00 "GICD_ITARGETSR62,Interrupt Processor Targets Register 62" rgroup.long 0x8FC++0x03 line.long 0x00 "GICD_ITARGETSR63,Interrupt Processor Targets Register 63" endif if (((per.l(ad:(per.long(spr:0x31F30)&0xFFFC0000)+0x04))&0x0000001F)>=0x08) group.long 0x900++0x03 line.long 0x00 "GICD_ITARGETSR64,Interrupt Processor Targets Register 64" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO259 ,CPU Targets Byte Offset 259 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO258 ,CPU Targets Byte Offset 258 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO257 ,CPU Targets Byte Offset 257 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO256 ,CPU Targets Byte Offset 256 " group.long 0x904++0x03 line.long 0x00 "GICD_ITARGETSR65,Interrupt Processor Targets Register 65" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO263 ,CPU Targets Byte Offset 263 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO262 ,CPU Targets Byte Offset 262 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO261 ,CPU Targets Byte Offset 261 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO260 ,CPU Targets Byte Offset 260 " group.long 0x908++0x03 line.long 0x00 "GICD_ITARGETSR66,Interrupt Processor Targets Register 66" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO267 ,CPU Targets Byte Offset 267 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO266 ,CPU Targets Byte Offset 266 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO265 ,CPU Targets Byte Offset 265 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO264 ,CPU Targets Byte Offset 264 " group.long 0x90C++0x03 line.long 0x00 "GICD_ITARGETSR67,Interrupt Processor Targets Register 67" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO271 ,CPU Targets Byte Offset 271 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO270 ,CPU Targets Byte Offset 270 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO269 ,CPU Targets Byte Offset 269 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO268 ,CPU Targets Byte Offset 268 " group.long 0x910++0x03 line.long 0x00 "GICD_ITARGETSR68,Interrupt Processor Targets Register 68" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO275 ,CPU Targets Byte Offset 275 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO274 ,CPU Targets Byte Offset 274 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO273 ,CPU Targets Byte Offset 273 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO272 ,CPU Targets Byte Offset 272 " group.long 0x914++0x03 line.long 0x00 "GICD_ITARGETSR69,Interrupt Processor Targets Register 69" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO279 ,CPU Targets Byte Offset 279 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO278 ,CPU Targets Byte Offset 278 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO277 ,CPU Targets Byte Offset 277 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO276 ,CPU Targets Byte Offset 276 " group.long 0x918++0x03 line.long 0x00 "GICD_ITARGETSR70,Interrupt Processor Targets Register 70" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO283 ,CPU Targets Byte Offset 283 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO282 ,CPU Targets Byte Offset 282 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO281 ,CPU Targets Byte Offset 281 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO280 ,CPU Targets Byte Offset 280 " group.long 0x91C++0x03 line.long 0x00 "GICD_ITARGETSR71,Interrupt Processor Targets Register 71" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO287 ,CPU Targets Byte Offset 287 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO286 ,CPU Targets Byte Offset 286 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO285 ,CPU Targets Byte Offset 285 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO284 ,CPU Targets Byte Offset 284 " else rgroup.long 0x900++0x03 line.long 0x00 "GICD_ITARGETSR64,Interrupt Processor Targets Register 64" rgroup.long 0x904++0x03 line.long 0x00 "GICD_ITARGETSR65,Interrupt Processor Targets Register 65" rgroup.long 0x908++0x03 line.long 0x00 "GICD_ITARGETSR66,Interrupt Processor Targets Register 66" rgroup.long 0x90C++0x03 line.long 0x00 "GICD_ITARGETSR67,Interrupt Processor Targets Register 67" rgroup.long 0x910++0x03 line.long 0x00 "GICD_ITARGETSR68,Interrupt Processor Targets Register 68" rgroup.long 0x914++0x03 line.long 0x00 "GICD_ITARGETSR69,Interrupt Processor Targets Register 69" rgroup.long 0x918++0x03 line.long 0x00 "GICD_ITARGETSR70,Interrupt Processor Targets Register 70" rgroup.long 0x91C++0x03 line.long 0x00 "GICD_ITARGETSR71,Interrupt Processor Targets Register 71" endif if (((per.l(ad:(per.long(spr:0x31F30)&0xFFFC0000)+0x04))&0x0000001F)>=0x09) group.long 0x920++0x03 line.long 0x00 "GICD_ITARGETSR72,Interrupt Processor Targets Register 72" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO291 ,CPU Targets Byte Offset 291 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO290 ,CPU Targets Byte Offset 290 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO289 ,CPU Targets Byte Offset 289 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO288 ,CPU Targets Byte Offset 288 " group.long 0x924++0x03 line.long 0x00 "GICD_ITARGETSR73,Interrupt Processor Targets Register 73" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO295 ,CPU Targets Byte Offset 295 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO294 ,CPU Targets Byte Offset 294 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO293 ,CPU Targets Byte Offset 293 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO292 ,CPU Targets Byte Offset 292 " group.long 0x928++0x03 line.long 0x00 "GICD_ITARGETSR74,Interrupt Processor Targets Register 74" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO299 ,CPU Targets Byte Offset 299 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO298 ,CPU Targets Byte Offset 298 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO297 ,CPU Targets Byte Offset 297 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO296 ,CPU Targets Byte Offset 296 " group.long 0x92C++0x03 line.long 0x00 "GICD_ITARGETSR75,Interrupt Processor Targets Register 75" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO303 ,CPU Targets Byte Offset 303 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO302 ,CPU Targets Byte Offset 302 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO301 ,CPU Targets Byte Offset 301 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO300 ,CPU Targets Byte Offset 300 " group.long 0x930++0x03 line.long 0x00 "GICD_ITARGETSR76,Interrupt Processor Targets Register 76" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO307 ,CPU Targets Byte Offset 307 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO306 ,CPU Targets Byte Offset 306 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO305 ,CPU Targets Byte Offset 305 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO304 ,CPU Targets Byte Offset 304 " group.long 0x934++0x03 line.long 0x00 "GICD_ITARGETSR77,Interrupt Processor Targets Register 77" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO311 ,CPU Targets Byte Offset 311 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO310 ,CPU Targets Byte Offset 310 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO309 ,CPU Targets Byte Offset 309 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO308 ,CPU Targets Byte Offset 308 " group.long 0x938++0x03 line.long 0x00 "GICD_ITARGETSR78,Interrupt Processor Targets Register 78" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO315 ,CPU Targets Byte Offset 315 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO314 ,CPU Targets Byte Offset 314 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO313 ,CPU Targets Byte Offset 313 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO312 ,CPU Targets Byte Offset 312 " group.long 0x93C++0x03 line.long 0x00 "GICD_ITARGETSR79,Interrupt Processor Targets Register 79" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO319 ,CPU Targets Byte Offset 319 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO318 ,CPU Targets Byte Offset 318 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO317 ,CPU Targets Byte Offset 317 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO316 ,CPU Targets Byte Offset 316 " else rgroup.long 0x920++0x03 line.long 0x00 "GICD_ITARGETSR72,Interrupt Processor Targets Register 72" rgroup.long 0x924++0x03 line.long 0x00 "GICD_ITARGETSR73,Interrupt Processor Targets Register 73" rgroup.long 0x928++0x03 line.long 0x00 "GICD_ITARGETSR74,Interrupt Processor Targets Register 74" rgroup.long 0x92C++0x03 line.long 0x00 "GICD_ITARGETSR75,Interrupt Processor Targets Register 75" rgroup.long 0x930++0x03 line.long 0x00 "GICD_ITARGETSR76,Interrupt Processor Targets Register 76" rgroup.long 0x934++0x03 line.long 0x00 "GICD_ITARGETSR77,Interrupt Processor Targets Register 77" rgroup.long 0x938++0x03 line.long 0x00 "GICD_ITARGETSR78,Interrupt Processor Targets Register 78" rgroup.long 0x93C++0x03 line.long 0x00 "GICD_ITARGETSR79,Interrupt Processor Targets Register 79" endif if (((per.l(ad:(per.long(spr:0x31F30)&0xFFFC0000)+0x04))&0x0000001F)>=0x0A) group.long 0x940++0x03 line.long 0x00 "GICD_ITARGETSR80,Interrupt Processor Targets Register 80" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO323 ,CPU Targets Byte Offset 323 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO322 ,CPU Targets Byte Offset 322 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO321 ,CPU Targets Byte Offset 321 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO320 ,CPU Targets Byte Offset 320 " group.long 0x944++0x03 line.long 0x00 "GICD_ITARGETSR81,Interrupt Processor Targets Register 81" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO327 ,CPU Targets Byte Offset 327 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO326 ,CPU Targets Byte Offset 326 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO325 ,CPU Targets Byte Offset 325 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO324 ,CPU Targets Byte Offset 324 " group.long 0x948++0x03 line.long 0x00 "GICD_ITARGETSR82,Interrupt Processor Targets Register 82" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO331 ,CPU Targets Byte Offset 331 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO330 ,CPU Targets Byte Offset 330 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO329 ,CPU Targets Byte Offset 329 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO328 ,CPU Targets Byte Offset 328 " group.long 0x94C++0x03 line.long 0x00 "GICD_ITARGETSR83,Interrupt Processor Targets Register 83" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO335 ,CPU Targets Byte Offset 335 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO334 ,CPU Targets Byte Offset 334 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO333 ,CPU Targets Byte Offset 333 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO332 ,CPU Targets Byte Offset 332 " group.long 0x950++0x03 line.long 0x00 "GICD_ITARGETSR84,Interrupt Processor Targets Register 84" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO339 ,CPU Targets Byte Offset 339 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO338 ,CPU Targets Byte Offset 338 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO337 ,CPU Targets Byte Offset 337 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO336 ,CPU Targets Byte Offset 336 " group.long 0x954++0x03 line.long 0x00 "GICD_ITARGETSR85,Interrupt Processor Targets Register 85" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO343 ,CPU Targets Byte Offset 343 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO342 ,CPU Targets Byte Offset 342 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO341 ,CPU Targets Byte Offset 341 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO340 ,CPU Targets Byte Offset 340 " group.long 0x958++0x03 line.long 0x00 "GICD_ITARGETSR86,Interrupt Processor Targets Register 86" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO347 ,CPU Targets Byte Offset 347 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO346 ,CPU Targets Byte Offset 346 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO345 ,CPU Targets Byte Offset 345 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO344 ,CPU Targets Byte Offset 344 " group.long 0x95C++0x03 line.long 0x00 "GICD_ITARGETSR87,Interrupt Processor Targets Register 87" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO351 ,CPU Targets Byte Offset 351 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO350 ,CPU Targets Byte Offset 350 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO349 ,CPU Targets Byte Offset 349 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO348 ,CPU Targets Byte Offset 348 " else rgroup.long 0x940++0x03 line.long 0x00 "GICD_ITARGETSR80,Interrupt Processor Targets Register 80" rgroup.long 0x944++0x03 line.long 0x00 "GICD_ITARGETSR81,Interrupt Processor Targets Register 81" rgroup.long 0x948++0x03 line.long 0x00 "GICD_ITARGETSR82,Interrupt Processor Targets Register 82" rgroup.long 0x94C++0x03 line.long 0x00 "GICD_ITARGETSR83,Interrupt Processor Targets Register 83" rgroup.long 0x950++0x03 line.long 0x00 "GICD_ITARGETSR84,Interrupt Processor Targets Register 84" rgroup.long 0x954++0x03 line.long 0x00 "GICD_ITARGETSR85,Interrupt Processor Targets Register 85" rgroup.long 0x958++0x03 line.long 0x00 "GICD_ITARGETSR86,Interrupt Processor Targets Register 86" rgroup.long 0x95C++0x03 line.long 0x00 "GICD_ITARGETSR87,Interrupt Processor Targets Register 87" endif if (((per.l(ad:(per.long(spr:0x31F30)&0xFFFC0000)+0x04))&0x0000001F)>=0x0B) group.long 0x960++0x03 line.long 0x00 "GICD_ITARGETSR88,Interrupt Processor Targets Register 88" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO355 ,CPU Targets Byte Offset 355 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO354 ,CPU Targets Byte Offset 354 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO353 ,CPU Targets Byte Offset 353 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO352 ,CPU Targets Byte Offset 352 " group.long 0x964++0x03 line.long 0x00 "GICD_ITARGETSR89,Interrupt Processor Targets Register 89" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO359 ,CPU Targets Byte Offset 359 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO358 ,CPU Targets Byte Offset 358 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO357 ,CPU Targets Byte Offset 357 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO356 ,CPU Targets Byte Offset 356 " group.long 0x968++0x03 line.long 0x00 "GICD_ITARGETSR90,Interrupt Processor Targets Register 90" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO363 ,CPU Targets Byte Offset 363 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO362 ,CPU Targets Byte Offset 362 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO361 ,CPU Targets Byte Offset 361 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO360 ,CPU Targets Byte Offset 360 " group.long 0x96C++0x03 line.long 0x00 "GICD_ITARGETSR91,Interrupt Processor Targets Register 91" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO367 ,CPU Targets Byte Offset 367 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO366 ,CPU Targets Byte Offset 366 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO365 ,CPU Targets Byte Offset 365 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO364 ,CPU Targets Byte Offset 364 " group.long 0x970++0x03 line.long 0x00 "GICD_ITARGETSR92,Interrupt Processor Targets Register 92" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO371 ,CPU Targets Byte Offset 371 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO370 ,CPU Targets Byte Offset 370 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO369 ,CPU Targets Byte Offset 369 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO368 ,CPU Targets Byte Offset 368 " group.long 0x974++0x03 line.long 0x00 "GICD_ITARGETSR93,Interrupt Processor Targets Register 93" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO375 ,CPU Targets Byte Offset 375 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO374 ,CPU Targets Byte Offset 374 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO373 ,CPU Targets Byte Offset 373 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO372 ,CPU Targets Byte Offset 372 " group.long 0x978++0x03 line.long 0x00 "GICD_ITARGETSR94,Interrupt Processor Targets Register 94" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO379 ,CPU Targets Byte Offset 379 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO378 ,CPU Targets Byte Offset 378 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO377 ,CPU Targets Byte Offset 377 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO376 ,CPU Targets Byte Offset 376 " group.long 0x97C++0x03 line.long 0x00 "GICD_ITARGETSR95,Interrupt Processor Targets Register 95" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO383 ,CPU Targets Byte Offset 383 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO382 ,CPU Targets Byte Offset 382 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO381 ,CPU Targets Byte Offset 381 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO380 ,CPU Targets Byte Offset 380 " else rgroup.long 0x960++0x03 line.long 0x00 "GICD_ITARGETSR88,Interrupt Processor Targets Register 88" rgroup.long 0x964++0x03 line.long 0x00 "GICD_ITARGETSR89,Interrupt Processor Targets Register 89" rgroup.long 0x968++0x03 line.long 0x00 "GICD_ITARGETSR90,Interrupt Processor Targets Register 90" rgroup.long 0x96C++0x03 line.long 0x00 "GICD_ITARGETSR91,Interrupt Processor Targets Register 91" rgroup.long 0x970++0x03 line.long 0x00 "GICD_ITARGETSR92,Interrupt Processor Targets Register 92" rgroup.long 0x974++0x03 line.long 0x00 "GICD_ITARGETSR93,Interrupt Processor Targets Register 93" rgroup.long 0x978++0x03 line.long 0x00 "GICD_ITARGETSR94,Interrupt Processor Targets Register 94" rgroup.long 0x97C++0x03 line.long 0x00 "GICD_ITARGETSR95,Interrupt Processor Targets Register 95" endif if (((per.l(ad:(per.long(spr:0x31F30)&0xFFFC0000)+0x04))&0x0000001F)>=0x0C) group.long 0x980++0x03 line.long 0x00 "GICD_ITARGETSR96,Interrupt Processor Targets Register 96" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO387 ,CPU Targets Byte Offset 387 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO386 ,CPU Targets Byte Offset 386 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO385 ,CPU Targets Byte Offset 385 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO384 ,CPU Targets Byte Offset 384 " group.long 0x984++0x03 line.long 0x00 "GICD_ITARGETSR97,Interrupt Processor Targets Register 97" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO391 ,CPU Targets Byte Offset 391 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO390 ,CPU Targets Byte Offset 390 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO389 ,CPU Targets Byte Offset 389 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO388 ,CPU Targets Byte Offset 388 " group.long 0x988++0x03 line.long 0x00 "GICD_ITARGETSR98,Interrupt Processor Targets Register 98" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO395 ,CPU Targets Byte Offset 395 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO394 ,CPU Targets Byte Offset 394 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO393 ,CPU Targets Byte Offset 393 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO392 ,CPU Targets Byte Offset 392 " group.long 0x98C++0x03 line.long 0x00 "GICD_ITARGETSR99,Interrupt Processor Targets Register 99" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO399 ,CPU Targets Byte Offset 399 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO398 ,CPU Targets Byte Offset 398 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO397 ,CPU Targets Byte Offset 397 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO396 ,CPU Targets Byte Offset 396 " group.long 0x990++0x03 line.long 0x00 "GICD_ITARGETSR100,Interrupt Processor Targets Register 100" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO403 ,CPU Targets Byte Offset 403 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO402 ,CPU Targets Byte Offset 402 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO401 ,CPU Targets Byte Offset 401 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO400 ,CPU Targets Byte Offset 400 " group.long 0x994++0x03 line.long 0x00 "GICD_ITARGETSR101,Interrupt Processor Targets Register 101" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO407 ,CPU Targets Byte Offset 407 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO406 ,CPU Targets Byte Offset 406 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO405 ,CPU Targets Byte Offset 405 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO404 ,CPU Targets Byte Offset 404 " group.long 0x998++0x03 line.long 0x00 "GICD_ITARGETSR102,Interrupt Processor Targets Register 102" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO411 ,CPU Targets Byte Offset 411 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO410 ,CPU Targets Byte Offset 410 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO409 ,CPU Targets Byte Offset 409 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO408 ,CPU Targets Byte Offset 408 " group.long 0x99C++0x03 line.long 0x00 "GICD_ITARGETSR103,Interrupt Processor Targets Register 103" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO415 ,CPU Targets Byte Offset 415 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO414 ,CPU Targets Byte Offset 414 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO413 ,CPU Targets Byte Offset 413 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO412 ,CPU Targets Byte Offset 412 " else rgroup.long 0x980++0x03 line.long 0x00 "GICD_ITARGETSR96,Interrupt Processor Targets Register 96" rgroup.long 0x984++0x03 line.long 0x00 "GICD_ITARGETSR97,Interrupt Processor Targets Register 97" rgroup.long 0x988++0x03 line.long 0x00 "GICD_ITARGETSR98,Interrupt Processor Targets Register 98" rgroup.long 0x98C++0x03 line.long 0x00 "GICD_ITARGETSR99,Interrupt Processor Targets Register 99" rgroup.long 0x990++0x03 line.long 0x00 "GICD_ITARGETSR100,Interrupt Processor Targets Register 100" rgroup.long 0x994++0x03 line.long 0x00 "GICD_ITARGETSR101,Interrupt Processor Targets Register 101" rgroup.long 0x998++0x03 line.long 0x00 "GICD_ITARGETSR102,Interrupt Processor Targets Register 102" rgroup.long 0x99C++0x03 line.long 0x00 "GICD_ITARGETSR103,Interrupt Processor Targets Register 103" endif if (((per.l(ad:(per.long(spr:0x31F30)&0xFFFC0000)+0x04))&0x0000001F)>=0x0D) group.long 0x9A0++0x03 line.long 0x00 "GICD_ITARGETSR104,Interrupt Processor Targets Register 104" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO419 ,CPU Targets Byte Offset 419 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO418 ,CPU Targets Byte Offset 418 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO417 ,CPU Targets Byte Offset 417 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO416 ,CPU Targets Byte Offset 416 " group.long 0x9A4++0x03 line.long 0x00 "GICD_ITARGETSR105,Interrupt Processor Targets Register 105" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO423 ,CPU Targets Byte Offset 423 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO422 ,CPU Targets Byte Offset 422 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO421 ,CPU Targets Byte Offset 421 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO420 ,CPU Targets Byte Offset 420 " group.long 0x9A8++0x03 line.long 0x00 "GICD_ITARGETSR106,Interrupt Processor Targets Register 106" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO427 ,CPU Targets Byte Offset 427 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO426 ,CPU Targets Byte Offset 426 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO425 ,CPU Targets Byte Offset 425 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO424 ,CPU Targets Byte Offset 424 " group.long 0x9AC++0x03 line.long 0x00 "GICD_ITARGETSR107,Interrupt Processor Targets Register 107" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO431 ,CPU Targets Byte Offset 431 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO430 ,CPU Targets Byte Offset 430 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO429 ,CPU Targets Byte Offset 429 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO428 ,CPU Targets Byte Offset 428 " group.long 0x9B0++0x03 line.long 0x00 "GICD_ITARGETSR108,Interrupt Processor Targets Register 108" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO435 ,CPU Targets Byte Offset 435 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO434 ,CPU Targets Byte Offset 434 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO433 ,CPU Targets Byte Offset 433 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO432 ,CPU Targets Byte Offset 432 " group.long 0x9B4++0x03 line.long 0x00 "GICD_ITARGETSR109,Interrupt Processor Targets Register 109" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO439 ,CPU Targets Byte Offset 439 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO438 ,CPU Targets Byte Offset 438 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO437 ,CPU Targets Byte Offset 437 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO436 ,CPU Targets Byte Offset 436 " group.long 0x9B8++0x03 line.long 0x00 "GICD_ITARGETSR110,Interrupt Processor Targets Register 110" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO443 ,CPU Targets Byte Offset 443 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO442 ,CPU Targets Byte Offset 442 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO441 ,CPU Targets Byte Offset 441 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO440 ,CPU Targets Byte Offset 440 " group.long 0x9BC++0x03 line.long 0x00 "GICD_ITARGETSR111,Interrupt Processor Targets Register 111" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO447 ,CPU Targets Byte Offset 447 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO446 ,CPU Targets Byte Offset 446 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO445 ,CPU Targets Byte Offset 445 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO444 ,CPU Targets Byte Offset 444 " else rgroup.long 0x9A0++0x03 line.long 0x00 "GICD_ITARGETSR104,Interrupt Processor Targets Register 104" rgroup.long 0x9A4++0x03 line.long 0x00 "GICD_ITARGETSR105,Interrupt Processor Targets Register 105" rgroup.long 0x9A8++0x03 line.long 0x00 "GICD_ITARGETSR106,Interrupt Processor Targets Register 106" rgroup.long 0x9AC++0x03 line.long 0x00 "GICD_ITARGETSR107,Interrupt Processor Targets Register 107" rgroup.long 0x9B0++0x03 line.long 0x00 "GICD_ITARGETSR108,Interrupt Processor Targets Register 108" rgroup.long 0x9B4++0x03 line.long 0x00 "GICD_ITARGETSR109,Interrupt Processor Targets Register 109" rgroup.long 0x9B8++0x03 line.long 0x00 "GICD_ITARGETSR110,Interrupt Processor Targets Register 110" rgroup.long 0x9BC++0x03 line.long 0x00 "GICD_ITARGETSR111,Interrupt Processor Targets Register 111" endif if (((per.l(ad:(per.long(spr:0x31F30)&0xFFFC0000)+0x04))&0x0000001F)>=0x0E) group.long 0x9C0++0x03 line.long 0x00 "GICD_ITARGETSR112,Interrupt Processor Targets Register 112" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO451 ,CPU Targets Byte Offset 451 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO450 ,CPU Targets Byte Offset 450 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO449 ,CPU Targets Byte Offset 449 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO448 ,CPU Targets Byte Offset 448 " group.long 0x9C4++0x03 line.long 0x00 "GICD_ITARGETSR113,Interrupt Processor Targets Register 113" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO455 ,CPU Targets Byte Offset 455 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO454 ,CPU Targets Byte Offset 454 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO453 ,CPU Targets Byte Offset 453 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO452 ,CPU Targets Byte Offset 452 " group.long 0x9C8++0x03 line.long 0x00 "GICD_ITARGETSR114,Interrupt Processor Targets Register 114" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO459 ,CPU Targets Byte Offset 459 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO458 ,CPU Targets Byte Offset 458 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO457 ,CPU Targets Byte Offset 457 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO456 ,CPU Targets Byte Offset 456 " group.long 0x9CC++0x03 line.long 0x00 "GICD_ITARGETSR115,Interrupt Processor Targets Register 115" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO463 ,CPU Targets Byte Offset 463 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO462 ,CPU Targets Byte Offset 462 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO461 ,CPU Targets Byte Offset 461 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO460 ,CPU Targets Byte Offset 460 " group.long 0x9D0++0x03 line.long 0x00 "GICD_ITARGETSR116,Interrupt Processor Targets Register 116" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO467 ,CPU Targets Byte Offset 467 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO466 ,CPU Targets Byte Offset 466 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO465 ,CPU Targets Byte Offset 465 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO464 ,CPU Targets Byte Offset 464 " group.long 0x9D4++0x03 line.long 0x00 "GICD_ITARGETSR117,Interrupt Processor Targets Register 117" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO471 ,CPU Targets Byte Offset 471 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO470 ,CPU Targets Byte Offset 470 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO469 ,CPU Targets Byte Offset 469 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO468 ,CPU Targets Byte Offset 468 " group.long 0x9D8++0x03 line.long 0x00 "GICD_ITARGETSR118,Interrupt Processor Targets Register 118" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO475 ,CPU Targets Byte Offset 475 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO474 ,CPU Targets Byte Offset 474 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO473 ,CPU Targets Byte Offset 473 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO472 ,CPU Targets Byte Offset 472 " group.long 0x9DC++0x03 line.long 0x00 "GICD_ITARGETSR119,Interrupt Processor Targets Register 119" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO479 ,CPU Targets Byte Offset 479 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO478 ,CPU Targets Byte Offset 478 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO477 ,CPU Targets Byte Offset 477 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO476 ,CPU Targets Byte Offset 476 " else rgroup.long 0x9C0++0x03 line.long 0x00 "GICD_ITARGETSR112,Interrupt Processor Targets Register 112" rgroup.long 0x9C4++0x03 line.long 0x00 "GICD_ITARGETSR113,Interrupt Processor Targets Register 113" rgroup.long 0x9C8++0x03 line.long 0x00 "GICD_ITARGETSR114,Interrupt Processor Targets Register 114" rgroup.long 0x9CC++0x03 line.long 0x00 "GICD_ITARGETSR115,Interrupt Processor Targets Register 115" rgroup.long 0x9D0++0x03 line.long 0x00 "GICD_ITARGETSR116,Interrupt Processor Targets Register 116" rgroup.long 0x9D4++0x03 line.long 0x00 "GICD_ITARGETSR117,Interrupt Processor Targets Register 117" rgroup.long 0x9D8++0x03 line.long 0x00 "GICD_ITARGETSR118,Interrupt Processor Targets Register 118" rgroup.long 0x9DC++0x03 line.long 0x00 "GICD_ITARGETSR119,Interrupt Processor Targets Register 119" endif if (((per.l(ad:(per.long(spr:0x31F30)&0xFFFC0000)+0x04))&0x0000001F)>=0x0F) group.long 0x9E0++0x03 line.long 0x00 "GICD_ITARGETSR120,Interrupt Processor Targets Register 120" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO483 ,CPU Targets Byte Offset 483 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO482 ,CPU Targets Byte Offset 482 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO481 ,CPU Targets Byte Offset 481 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO480 ,CPU Targets Byte Offset 480 " group.long 0x9E4++0x03 line.long 0x00 "GICD_ITARGETSR121,Interrupt Processor Targets Register 121" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO487 ,CPU Targets Byte Offset 487 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO486 ,CPU Targets Byte Offset 486 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO485 ,CPU Targets Byte Offset 485 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO484 ,CPU Targets Byte Offset 484 " group.long 0x9E8++0x03 line.long 0x00 "GICD_ITARGETSR122,Interrupt Processor Targets Register 122" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO491 ,CPU Targets Byte Offset 491 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO490 ,CPU Targets Byte Offset 490 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO489 ,CPU Targets Byte Offset 489 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO488 ,CPU Targets Byte Offset 488 " group.long 0x9EC++0x03 line.long 0x00 "GICD_ITARGETSR123,Interrupt Processor Targets Register 123" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO495 ,CPU Targets Byte Offset 495 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO494 ,CPU Targets Byte Offset 494 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO493 ,CPU Targets Byte Offset 493 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO492 ,CPU Targets Byte Offset 492 " group.long 0x9F0++0x03 line.long 0x00 "GICD_ITARGETSR124,Interrupt Processor Targets Register 124" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO499 ,CPU Targets Byte Offset 499 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO498 ,CPU Targets Byte Offset 498 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO497 ,CPU Targets Byte Offset 497 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO496 ,CPU Targets Byte Offset 496 " group.long 0x9F4++0x03 line.long 0x00 "GICD_ITARGETSR125,Interrupt Processor Targets Register 125" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO503 ,CPU Targets Byte Offset 503 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO502 ,CPU Targets Byte Offset 502 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO501 ,CPU Targets Byte Offset 501 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO500 ,CPU Targets Byte Offset 500 " group.long 0x9F8++0x03 line.long 0x00 "GICD_ITARGETSR126,Interrupt Processor Targets Register 126" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO507 ,CPU Targets Byte Offset 507 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO506 ,CPU Targets Byte Offset 506 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO505 ,CPU Targets Byte Offset 505 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO504 ,CPU Targets Byte Offset 504 " group.long 0x9FC++0x03 line.long 0x00 "GICD_ITARGETSR127,Interrupt Processor Targets Register 127" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO511 ,CPU Targets Byte Offset 511 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO510 ,CPU Targets Byte Offset 510 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO509 ,CPU Targets Byte Offset 509 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO508 ,CPU Targets Byte Offset 508 " else rgroup.long 0x9E0++0x03 line.long 0x00 "GICD_ITARGETSR120,Interrupt Processor Targets Register 120" rgroup.long 0x9E4++0x03 line.long 0x00 "GICD_ITARGETSR121,Interrupt Processor Targets Register 121" rgroup.long 0x9E8++0x03 line.long 0x00 "GICD_ITARGETSR122,Interrupt Processor Targets Register 122" rgroup.long 0x9EC++0x03 line.long 0x00 "GICD_ITARGETSR123,Interrupt Processor Targets Register 123" rgroup.long 0x9F0++0x03 line.long 0x00 "GICD_ITARGETSR124,Interrupt Processor Targets Register 124" rgroup.long 0x9F4++0x03 line.long 0x00 "GICD_ITARGETSR125,Interrupt Processor Targets Register 125" rgroup.long 0x9F8++0x03 line.long 0x00 "GICD_ITARGETSR126,Interrupt Processor Targets Register 126" rgroup.long 0x9FC++0x03 line.long 0x00 "GICD_ITARGETSR127,Interrupt Processor Targets Register 127" endif if (((per.l(ad:(per.long(spr:0x31F30)&0xFFFC0000)+0x04))&0x0000001F)>=0x10) group.long 0xA00++0x03 line.long 0x00 "GICD_ITARGETSR128,Interrupt Processor Targets Register 128" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO515 ,CPU Targets Byte Offset 515 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO514 ,CPU Targets Byte Offset 514 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO513 ,CPU Targets Byte Offset 513 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO512 ,CPU Targets Byte Offset 512 " group.long 0xA04++0x03 line.long 0x00 "GICD_ITARGETSR129,Interrupt Processor Targets Register 129" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO519 ,CPU Targets Byte Offset 519 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO518 ,CPU Targets Byte Offset 518 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO517 ,CPU Targets Byte Offset 517 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO516 ,CPU Targets Byte Offset 516 " group.long 0xA08++0x03 line.long 0x00 "GICD_ITARGETSR130,Interrupt Processor Targets Register 130" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO523 ,CPU Targets Byte Offset 523 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO522 ,CPU Targets Byte Offset 522 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO521 ,CPU Targets Byte Offset 521 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO520 ,CPU Targets Byte Offset 520 " group.long 0xA0C++0x03 line.long 0x00 "GICD_ITARGETSR131,Interrupt Processor Targets Register 131" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO527 ,CPU Targets Byte Offset 527 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO526 ,CPU Targets Byte Offset 526 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO525 ,CPU Targets Byte Offset 525 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO524 ,CPU Targets Byte Offset 524 " group.long 0xA10++0x03 line.long 0x00 "GICD_ITARGETSR132,Interrupt Processor Targets Register 132" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO531 ,CPU Targets Byte Offset 531 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO530 ,CPU Targets Byte Offset 530 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO529 ,CPU Targets Byte Offset 529 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO528 ,CPU Targets Byte Offset 528 " group.long 0xA14++0x03 line.long 0x00 "GICD_ITARGETSR133,Interrupt Processor Targets Register 133" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO535 ,CPU Targets Byte Offset 535 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO534 ,CPU Targets Byte Offset 534 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO533 ,CPU Targets Byte Offset 533 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO532 ,CPU Targets Byte Offset 532 " group.long 0xA18++0x03 line.long 0x00 "GICD_ITARGETSR134,Interrupt Processor Targets Register 134" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO539 ,CPU Targets Byte Offset 539 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO538 ,CPU Targets Byte Offset 538 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO537 ,CPU Targets Byte Offset 537 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO536 ,CPU Targets Byte Offset 536 " group.long 0xA1C++0x03 line.long 0x00 "GICD_ITARGETSR135,Interrupt Processor Targets Register 135" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO543 ,CPU Targets Byte Offset 543 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO542 ,CPU Targets Byte Offset 542 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO541 ,CPU Targets Byte Offset 541 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO540 ,CPU Targets Byte Offset 540 " else rgroup.long 0xA00++0x03 line.long 0x00 "GICD_ITARGETSR128,Interrupt Processor Targets Register 128" rgroup.long 0xA04++0x03 line.long 0x00 "GICD_ITARGETSR129,Interrupt Processor Targets Register 129" rgroup.long 0xA08++0x03 line.long 0x00 "GICD_ITARGETSR130,Interrupt Processor Targets Register 130" rgroup.long 0xA0C++0x03 line.long 0x00 "GICD_ITARGETSR131,Interrupt Processor Targets Register 131" rgroup.long 0xA10++0x03 line.long 0x00 "GICD_ITARGETSR132,Interrupt Processor Targets Register 132" rgroup.long 0xA14++0x03 line.long 0x00 "GICD_ITARGETSR133,Interrupt Processor Targets Register 133" rgroup.long 0xA18++0x03 line.long 0x00 "GICD_ITARGETSR134,Interrupt Processor Targets Register 134" rgroup.long 0xA1C++0x03 line.long 0x00 "GICD_ITARGETSR135,Interrupt Processor Targets Register 135" endif if (((per.l(ad:(per.long(spr:0x31F30)&0xFFFC0000)+0x04))&0x0000001F)>=0x11) group.long 0xA20++0x03 line.long 0x00 "GICD_ITARGETSR136,Interrupt Processor Targets Register 136" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO547 ,CPU Targets Byte Offset 547 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO546 ,CPU Targets Byte Offset 546 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO545 ,CPU Targets Byte Offset 545 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO544 ,CPU Targets Byte Offset 544 " group.long 0xA24++0x03 line.long 0x00 "GICD_ITARGETSR137,Interrupt Processor Targets Register 137" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO551 ,CPU Targets Byte Offset 551 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO550 ,CPU Targets Byte Offset 550 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO549 ,CPU Targets Byte Offset 549 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO548 ,CPU Targets Byte Offset 548 " group.long 0xA28++0x03 line.long 0x00 "GICD_ITARGETSR138,Interrupt Processor Targets Register 138" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO555 ,CPU Targets Byte Offset 555 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO554 ,CPU Targets Byte Offset 554 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO553 ,CPU Targets Byte Offset 553 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO552 ,CPU Targets Byte Offset 552 " group.long 0xA2C++0x03 line.long 0x00 "GICD_ITARGETSR139,Interrupt Processor Targets Register 139" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO559 ,CPU Targets Byte Offset 559 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO558 ,CPU Targets Byte Offset 558 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO557 ,CPU Targets Byte Offset 557 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO556 ,CPU Targets Byte Offset 556 " group.long 0xA30++0x03 line.long 0x00 "GICD_ITARGETSR140,Interrupt Processor Targets Register 140" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO563 ,CPU Targets Byte Offset 563 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO562 ,CPU Targets Byte Offset 562 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO561 ,CPU Targets Byte Offset 561 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO560 ,CPU Targets Byte Offset 560 " group.long 0xA34++0x03 line.long 0x00 "GICD_ITARGETSR141,Interrupt Processor Targets Register 141" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO567 ,CPU Targets Byte Offset 567 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO566 ,CPU Targets Byte Offset 566 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO565 ,CPU Targets Byte Offset 565 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO564 ,CPU Targets Byte Offset 564 " group.long 0xA38++0x03 line.long 0x00 "GICD_ITARGETSR142,Interrupt Processor Targets Register 142" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO571 ,CPU Targets Byte Offset 571 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO570 ,CPU Targets Byte Offset 570 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO569 ,CPU Targets Byte Offset 569 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO568 ,CPU Targets Byte Offset 568 " group.long 0xA3C++0x03 line.long 0x00 "GICD_ITARGETSR143,Interrupt Processor Targets Register 143" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO575 ,CPU Targets Byte Offset 575 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO574 ,CPU Targets Byte Offset 574 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO573 ,CPU Targets Byte Offset 573 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO572 ,CPU Targets Byte Offset 572 " else rgroup.long 0xA20++0x03 line.long 0x00 "GICD_ITARGETSR136,Interrupt Processor Targets Register 136" rgroup.long 0xA24++0x03 line.long 0x00 "GICD_ITARGETSR137,Interrupt Processor Targets Register 137" rgroup.long 0xA28++0x03 line.long 0x00 "GICD_ITARGETSR138,Interrupt Processor Targets Register 138" rgroup.long 0xA2C++0x03 line.long 0x00 "GICD_ITARGETSR139,Interrupt Processor Targets Register 139" rgroup.long 0xA30++0x03 line.long 0x00 "GICD_ITARGETSR140,Interrupt Processor Targets Register 140" rgroup.long 0xA34++0x03 line.long 0x00 "GICD_ITARGETSR141,Interrupt Processor Targets Register 141" rgroup.long 0xA38++0x03 line.long 0x00 "GICD_ITARGETSR142,Interrupt Processor Targets Register 142" rgroup.long 0xA3C++0x03 line.long 0x00 "GICD_ITARGETSR143,Interrupt Processor Targets Register 143" endif if (((per.l(ad:(per.long(spr:0x31F30)&0xFFFC0000)+0x04))&0x0000001F)>=0x12) group.long 0xA40++0x03 line.long 0x00 "GICD_ITARGETSR144,Interrupt Processor Targets Register 144" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO579 ,CPU Targets Byte Offset 579 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO578 ,CPU Targets Byte Offset 578 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO577 ,CPU Targets Byte Offset 577 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO576 ,CPU Targets Byte Offset 576 " group.long 0xA44++0x03 line.long 0x00 "GICD_ITARGETSR145,Interrupt Processor Targets Register 145" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO583 ,CPU Targets Byte Offset 583 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO582 ,CPU Targets Byte Offset 582 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO581 ,CPU Targets Byte Offset 581 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO580 ,CPU Targets Byte Offset 580 " group.long 0xA48++0x03 line.long 0x00 "GICD_ITARGETSR146,Interrupt Processor Targets Register 146" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO587 ,CPU Targets Byte Offset 587 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO586 ,CPU Targets Byte Offset 586 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO585 ,CPU Targets Byte Offset 585 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO584 ,CPU Targets Byte Offset 584 " group.long 0xA4C++0x03 line.long 0x00 "GICD_ITARGETSR147,Interrupt Processor Targets Register 147" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO591 ,CPU Targets Byte Offset 591 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO590 ,CPU Targets Byte Offset 590 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO589 ,CPU Targets Byte Offset 589 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO588 ,CPU Targets Byte Offset 588 " group.long 0xA50++0x03 line.long 0x00 "GICD_ITARGETSR148,Interrupt Processor Targets Register 148" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO595 ,CPU Targets Byte Offset 595 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO594 ,CPU Targets Byte Offset 594 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO593 ,CPU Targets Byte Offset 593 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO592 ,CPU Targets Byte Offset 592 " group.long 0xA54++0x03 line.long 0x00 "GICD_ITARGETSR149,Interrupt Processor Targets Register 149" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO599 ,CPU Targets Byte Offset 599 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO598 ,CPU Targets Byte Offset 598 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO597 ,CPU Targets Byte Offset 597 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO596 ,CPU Targets Byte Offset 596 " group.long 0xA58++0x03 line.long 0x00 "GICD_ITARGETSR150,Interrupt Processor Targets Register 150" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO603 ,CPU Targets Byte Offset 603 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO602 ,CPU Targets Byte Offset 602 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO601 ,CPU Targets Byte Offset 601 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO600 ,CPU Targets Byte Offset 600 " group.long 0xA5C++0x03 line.long 0x00 "GICD_ITARGETSR151,Interrupt Processor Targets Register 151" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO607 ,CPU Targets Byte Offset 607 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO606 ,CPU Targets Byte Offset 606 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO605 ,CPU Targets Byte Offset 605 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO604 ,CPU Targets Byte Offset 604 " else rgroup.long 0xA40++0x03 line.long 0x00 "GICD_ITARGETSR144,Interrupt Processor Targets Register 144" rgroup.long 0xA44++0x03 line.long 0x00 "GICD_ITARGETSR145,Interrupt Processor Targets Register 145" rgroup.long 0xA48++0x03 line.long 0x00 "GICD_ITARGETSR146,Interrupt Processor Targets Register 146" rgroup.long 0xA4C++0x03 line.long 0x00 "GICD_ITARGETSR147,Interrupt Processor Targets Register 147" rgroup.long 0xA50++0x03 line.long 0x00 "GICD_ITARGETSR148,Interrupt Processor Targets Register 148" rgroup.long 0xA54++0x03 line.long 0x00 "GICD_ITARGETSR149,Interrupt Processor Targets Register 149" rgroup.long 0xA58++0x03 line.long 0x00 "GICD_ITARGETSR150,Interrupt Processor Targets Register 150" rgroup.long 0xA5C++0x03 line.long 0x00 "GICD_ITARGETSR151,Interrupt Processor Targets Register 151" endif if (((per.l(ad:(per.long(spr:0x31F30)&0xFFFC0000)+0x04))&0x0000001F)>=0x13) group.long 0xA60++0x03 line.long 0x00 "GICD_ITARGETSR152,Interrupt Processor Targets Register 152" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO611 ,CPU Targets Byte Offset 611 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO610 ,CPU Targets Byte Offset 610 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO609 ,CPU Targets Byte Offset 609 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO608 ,CPU Targets Byte Offset 608 " group.long 0xA64++0x03 line.long 0x00 "GICD_ITARGETSR153,Interrupt Processor Targets Register 153" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO615 ,CPU Targets Byte Offset 615 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO614 ,CPU Targets Byte Offset 614 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO613 ,CPU Targets Byte Offset 613 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO612 ,CPU Targets Byte Offset 612 " group.long 0xA68++0x03 line.long 0x00 "GICD_ITARGETSR154,Interrupt Processor Targets Register 154" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO619 ,CPU Targets Byte Offset 619 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO618 ,CPU Targets Byte Offset 618 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO617 ,CPU Targets Byte Offset 617 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO616 ,CPU Targets Byte Offset 616 " group.long 0xA6C++0x03 line.long 0x00 "GICD_ITARGETSR155,Interrupt Processor Targets Register 155" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO623 ,CPU Targets Byte Offset 623 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO622 ,CPU Targets Byte Offset 622 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO621 ,CPU Targets Byte Offset 621 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO620 ,CPU Targets Byte Offset 620 " group.long 0xA70++0x03 line.long 0x00 "GICD_ITARGETSR156,Interrupt Processor Targets Register 156" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO627 ,CPU Targets Byte Offset 627 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO626 ,CPU Targets Byte Offset 626 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO625 ,CPU Targets Byte Offset 625 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO624 ,CPU Targets Byte Offset 624 " group.long 0xA74++0x03 line.long 0x00 "GICD_ITARGETSR157,Interrupt Processor Targets Register 157" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO631 ,CPU Targets Byte Offset 631 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO630 ,CPU Targets Byte Offset 630 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO629 ,CPU Targets Byte Offset 629 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO628 ,CPU Targets Byte Offset 628 " group.long 0xA78++0x03 line.long 0x00 "GICD_ITARGETSR158,Interrupt Processor Targets Register 158" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO635 ,CPU Targets Byte Offset 635 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO634 ,CPU Targets Byte Offset 634 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO633 ,CPU Targets Byte Offset 633 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO632 ,CPU Targets Byte Offset 632 " group.long 0xA7C++0x03 line.long 0x00 "GICD_ITARGETSR159,Interrupt Processor Targets Register 159" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO639 ,CPU Targets Byte Offset 639 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO638 ,CPU Targets Byte Offset 638 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO637 ,CPU Targets Byte Offset 637 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO636 ,CPU Targets Byte Offset 636 " else rgroup.long 0xA60++0x03 line.long 0x00 "GICD_ITARGETSR152,Interrupt Processor Targets Register 152" rgroup.long 0xA64++0x03 line.long 0x00 "GICD_ITARGETSR153,Interrupt Processor Targets Register 153" rgroup.long 0xA68++0x03 line.long 0x00 "GICD_ITARGETSR154,Interrupt Processor Targets Register 154" rgroup.long 0xA6C++0x03 line.long 0x00 "GICD_ITARGETSR155,Interrupt Processor Targets Register 155" rgroup.long 0xA70++0x03 line.long 0x00 "GICD_ITARGETSR156,Interrupt Processor Targets Register 156" rgroup.long 0xA74++0x03 line.long 0x00 "GICD_ITARGETSR157,Interrupt Processor Targets Register 157" rgroup.long 0xA78++0x03 line.long 0x00 "GICD_ITARGETSR158,Interrupt Processor Targets Register 158" rgroup.long 0xA7C++0x03 line.long 0x00 "GICD_ITARGETSR159,Interrupt Processor Targets Register 159" endif if (((per.l(ad:(per.long(spr:0x31F30)&0xFFFC0000)+0x04))&0x0000001F)>=0x14) group.long 0xA80++0x03 line.long 0x00 "GICD_ITARGETSR160,Interrupt Processor Targets Register 160" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO643 ,CPU Targets Byte Offset 643 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO642 ,CPU Targets Byte Offset 642 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO641 ,CPU Targets Byte Offset 641 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO640 ,CPU Targets Byte Offset 640 " group.long 0xA84++0x03 line.long 0x00 "GICD_ITARGETSR161,Interrupt Processor Targets Register 161" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO647 ,CPU Targets Byte Offset 647 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO646 ,CPU Targets Byte Offset 646 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO645 ,CPU Targets Byte Offset 645 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO644 ,CPU Targets Byte Offset 644 " group.long 0xA88++0x03 line.long 0x00 "GICD_ITARGETSR162,Interrupt Processor Targets Register 162" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO651 ,CPU Targets Byte Offset 651 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO650 ,CPU Targets Byte Offset 650 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO649 ,CPU Targets Byte Offset 649 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO648 ,CPU Targets Byte Offset 648 " group.long 0xA8C++0x03 line.long 0x00 "GICD_ITARGETSR163,Interrupt Processor Targets Register 163" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO655 ,CPU Targets Byte Offset 655 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO654 ,CPU Targets Byte Offset 654 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO653 ,CPU Targets Byte Offset 653 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO652 ,CPU Targets Byte Offset 652 " group.long 0xA90++0x03 line.long 0x00 "GICD_ITARGETSR164,Interrupt Processor Targets Register 164" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO659 ,CPU Targets Byte Offset 659 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO658 ,CPU Targets Byte Offset 658 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO657 ,CPU Targets Byte Offset 657 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO656 ,CPU Targets Byte Offset 656 " group.long 0xA94++0x03 line.long 0x00 "GICD_ITARGETSR165,Interrupt Processor Targets Register 165" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO663 ,CPU Targets Byte Offset 663 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO662 ,CPU Targets Byte Offset 662 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO661 ,CPU Targets Byte Offset 661 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO660 ,CPU Targets Byte Offset 660 " group.long 0xA98++0x03 line.long 0x00 "GICD_ITARGETSR166,Interrupt Processor Targets Register 166" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO667 ,CPU Targets Byte Offset 667 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO666 ,CPU Targets Byte Offset 666 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO665 ,CPU Targets Byte Offset 665 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO664 ,CPU Targets Byte Offset 664 " group.long 0xA9C++0x03 line.long 0x00 "GICD_ITARGETSR167,Interrupt Processor Targets Register 167" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO671 ,CPU Targets Byte Offset 671 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO670 ,CPU Targets Byte Offset 670 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO669 ,CPU Targets Byte Offset 669 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO668 ,CPU Targets Byte Offset 668 " else rgroup.long 0xA80++0x03 line.long 0x00 "GICD_ITARGETSR160,Interrupt Processor Targets Register 160" rgroup.long 0xA84++0x03 line.long 0x00 "GICD_ITARGETSR161,Interrupt Processor Targets Register 161" rgroup.long 0xA88++0x03 line.long 0x00 "GICD_ITARGETSR162,Interrupt Processor Targets Register 162" rgroup.long 0xA8C++0x03 line.long 0x00 "GICD_ITARGETSR163,Interrupt Processor Targets Register 163" rgroup.long 0xA90++0x03 line.long 0x00 "GICD_ITARGETSR164,Interrupt Processor Targets Register 164" rgroup.long 0xA94++0x03 line.long 0x00 "GICD_ITARGETSR165,Interrupt Processor Targets Register 165" rgroup.long 0xA98++0x03 line.long 0x00 "GICD_ITARGETSR166,Interrupt Processor Targets Register 166" rgroup.long 0xA9C++0x03 line.long 0x00 "GICD_ITARGETSR167,Interrupt Processor Targets Register 167" endif if (((per.l(ad:(per.long(spr:0x31F30)&0xFFFC0000)+0x04))&0x0000001F)>=0x15) group.long 0xAA0++0x03 line.long 0x00 "GICD_ITARGETSR168,Interrupt Processor Targets Register 168" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO675 ,CPU Targets Byte Offset 675 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO674 ,CPU Targets Byte Offset 674 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO673 ,CPU Targets Byte Offset 673 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO672 ,CPU Targets Byte Offset 672 " group.long 0xAA4++0x03 line.long 0x00 "GICD_ITARGETSR169,Interrupt Processor Targets Register 169" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO679 ,CPU Targets Byte Offset 679 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO678 ,CPU Targets Byte Offset 678 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO677 ,CPU Targets Byte Offset 677 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO676 ,CPU Targets Byte Offset 676 " group.long 0xAA8++0x03 line.long 0x00 "GICD_ITARGETSR170,Interrupt Processor Targets Register 170" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO683 ,CPU Targets Byte Offset 683 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO682 ,CPU Targets Byte Offset 682 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO681 ,CPU Targets Byte Offset 681 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO680 ,CPU Targets Byte Offset 680 " group.long 0xAAC++0x03 line.long 0x00 "GICD_ITARGETSR171,Interrupt Processor Targets Register 171" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO687 ,CPU Targets Byte Offset 687 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO686 ,CPU Targets Byte Offset 686 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO685 ,CPU Targets Byte Offset 685 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO684 ,CPU Targets Byte Offset 684 " group.long 0xAB0++0x03 line.long 0x00 "GICD_ITARGETSR172,Interrupt Processor Targets Register 172" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO691 ,CPU Targets Byte Offset 691 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO690 ,CPU Targets Byte Offset 690 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO689 ,CPU Targets Byte Offset 689 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO688 ,CPU Targets Byte Offset 688 " group.long 0xAB4++0x03 line.long 0x00 "GICD_ITARGETSR173,Interrupt Processor Targets Register 173" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO695 ,CPU Targets Byte Offset 695 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO694 ,CPU Targets Byte Offset 694 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO693 ,CPU Targets Byte Offset 693 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO692 ,CPU Targets Byte Offset 692 " group.long 0xAB8++0x03 line.long 0x00 "GICD_ITARGETSR174,Interrupt Processor Targets Register 174" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO699 ,CPU Targets Byte Offset 699 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO698 ,CPU Targets Byte Offset 698 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO697 ,CPU Targets Byte Offset 697 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO696 ,CPU Targets Byte Offset 696 " group.long 0xABC++0x03 line.long 0x00 "GICD_ITARGETSR175,Interrupt Processor Targets Register 175" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO703 ,CPU Targets Byte Offset 703 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO702 ,CPU Targets Byte Offset 702 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO701 ,CPU Targets Byte Offset 701 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO700 ,CPU Targets Byte Offset 700 " else rgroup.long 0xAA0++0x03 line.long 0x00 "GICD_ITARGETSR168,Interrupt Processor Targets Register 168" rgroup.long 0xAA4++0x03 line.long 0x00 "GICD_ITARGETSR169,Interrupt Processor Targets Register 169" rgroup.long 0xAA8++0x03 line.long 0x00 "GICD_ITARGETSR170,Interrupt Processor Targets Register 170" rgroup.long 0xAAC++0x03 line.long 0x00 "GICD_ITARGETSR171,Interrupt Processor Targets Register 171" rgroup.long 0xAB0++0x03 line.long 0x00 "GICD_ITARGETSR172,Interrupt Processor Targets Register 172" rgroup.long 0xAB4++0x03 line.long 0x00 "GICD_ITARGETSR173,Interrupt Processor Targets Register 173" rgroup.long 0xAB8++0x03 line.long 0x00 "GICD_ITARGETSR174,Interrupt Processor Targets Register 174" rgroup.long 0xABC++0x03 line.long 0x00 "GICD_ITARGETSR175,Interrupt Processor Targets Register 175" endif if (((per.l(ad:(per.long(spr:0x31F30)&0xFFFC0000)+0x04))&0x0000001F)>=0x16) group.long 0xAC0++0x03 line.long 0x00 "GICD_ITARGETSR176,Interrupt Processor Targets Register 176" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO707 ,CPU Targets Byte Offset 707 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO706 ,CPU Targets Byte Offset 706 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO705 ,CPU Targets Byte Offset 705 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO704 ,CPU Targets Byte Offset 704 " group.long 0xAC4++0x03 line.long 0x00 "GICD_ITARGETSR177,Interrupt Processor Targets Register 177" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO711 ,CPU Targets Byte Offset 711 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO710 ,CPU Targets Byte Offset 710 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO709 ,CPU Targets Byte Offset 709 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO708 ,CPU Targets Byte Offset 708 " group.long 0xAC8++0x03 line.long 0x00 "GICD_ITARGETSR178,Interrupt Processor Targets Register 178" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO715 ,CPU Targets Byte Offset 715 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO714 ,CPU Targets Byte Offset 714 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO713 ,CPU Targets Byte Offset 713 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO712 ,CPU Targets Byte Offset 712 " group.long 0xACC++0x03 line.long 0x00 "GICD_ITARGETSR179,Interrupt Processor Targets Register 179" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO719 ,CPU Targets Byte Offset 719 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO718 ,CPU Targets Byte Offset 718 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO717 ,CPU Targets Byte Offset 717 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO716 ,CPU Targets Byte Offset 716 " group.long 0xAD0++0x03 line.long 0x00 "GICD_ITARGETSR180,Interrupt Processor Targets Register 180" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO723 ,CPU Targets Byte Offset 723 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO722 ,CPU Targets Byte Offset 722 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO721 ,CPU Targets Byte Offset 721 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO720 ,CPU Targets Byte Offset 720 " group.long 0xAD4++0x03 line.long 0x00 "GICD_ITARGETSR181,Interrupt Processor Targets Register 181" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO727 ,CPU Targets Byte Offset 727 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO726 ,CPU Targets Byte Offset 726 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO725 ,CPU Targets Byte Offset 725 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO724 ,CPU Targets Byte Offset 724 " group.long 0xAD8++0x03 line.long 0x00 "GICD_ITARGETSR182,Interrupt Processor Targets Register 182" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO731 ,CPU Targets Byte Offset 731 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO730 ,CPU Targets Byte Offset 730 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO729 ,CPU Targets Byte Offset 729 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO728 ,CPU Targets Byte Offset 728 " group.long 0xADC++0x03 line.long 0x00 "GICD_ITARGETSR183,Interrupt Processor Targets Register 183" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO735 ,CPU Targets Byte Offset 735 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO734 ,CPU Targets Byte Offset 734 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO733 ,CPU Targets Byte Offset 733 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO732 ,CPU Targets Byte Offset 732 " else rgroup.long 0xAC0++0x03 line.long 0x00 "GICD_ITARGETSR176,Interrupt Processor Targets Register 176" rgroup.long 0xAC4++0x03 line.long 0x00 "GICD_ITARGETSR177,Interrupt Processor Targets Register 177" rgroup.long 0xAC8++0x03 line.long 0x00 "GICD_ITARGETSR178,Interrupt Processor Targets Register 178" rgroup.long 0xACC++0x03 line.long 0x00 "GICD_ITARGETSR179,Interrupt Processor Targets Register 179" rgroup.long 0xAD0++0x03 line.long 0x00 "GICD_ITARGETSR180,Interrupt Processor Targets Register 180" rgroup.long 0xAD4++0x03 line.long 0x00 "GICD_ITARGETSR181,Interrupt Processor Targets Register 181" rgroup.long 0xAD8++0x03 line.long 0x00 "GICD_ITARGETSR182,Interrupt Processor Targets Register 182" rgroup.long 0xADC++0x03 line.long 0x00 "GICD_ITARGETSR183,Interrupt Processor Targets Register 183" endif if (((per.l(ad:(per.long(spr:0x31F30)&0xFFFC0000)+0x04))&0x0000001F)>=0x17) group.long 0xAE0++0x03 line.long 0x00 "GICD_ITARGETSR184,Interrupt Processor Targets Register 184" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO739 ,CPU Targets Byte Offset 739 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO738 ,CPU Targets Byte Offset 738 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO737 ,CPU Targets Byte Offset 737 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO736 ,CPU Targets Byte Offset 736 " group.long 0xAE4++0x03 line.long 0x00 "GICD_ITARGETSR185,Interrupt Processor Targets Register 185" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO743 ,CPU Targets Byte Offset 743 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO742 ,CPU Targets Byte Offset 742 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO741 ,CPU Targets Byte Offset 741 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO740 ,CPU Targets Byte Offset 740 " group.long 0xAE8++0x03 line.long 0x00 "GICD_ITARGETSR186,Interrupt Processor Targets Register 186" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO747 ,CPU Targets Byte Offset 747 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO746 ,CPU Targets Byte Offset 746 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO745 ,CPU Targets Byte Offset 745 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO744 ,CPU Targets Byte Offset 744 " group.long 0xAEC++0x03 line.long 0x00 "GICD_ITARGETSR187,Interrupt Processor Targets Register 187" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO751 ,CPU Targets Byte Offset 751 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO750 ,CPU Targets Byte Offset 750 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO749 ,CPU Targets Byte Offset 749 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO748 ,CPU Targets Byte Offset 748 " group.long 0xAF0++0x03 line.long 0x00 "GICD_ITARGETSR188,Interrupt Processor Targets Register 188" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO755 ,CPU Targets Byte Offset 755 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO754 ,CPU Targets Byte Offset 754 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO753 ,CPU Targets Byte Offset 753 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO752 ,CPU Targets Byte Offset 752 " group.long 0xAF4++0x03 line.long 0x00 "GICD_ITARGETSR189,Interrupt Processor Targets Register 189" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO759 ,CPU Targets Byte Offset 759 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO758 ,CPU Targets Byte Offset 758 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO757 ,CPU Targets Byte Offset 757 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO756 ,CPU Targets Byte Offset 756 " group.long 0xAF8++0x03 line.long 0x00 "GICD_ITARGETSR190,Interrupt Processor Targets Register 190" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO763 ,CPU Targets Byte Offset 763 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO762 ,CPU Targets Byte Offset 762 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO761 ,CPU Targets Byte Offset 761 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO760 ,CPU Targets Byte Offset 760 " group.long 0xAFC++0x03 line.long 0x00 "GICD_ITARGETSR191,Interrupt Processor Targets Register 191" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO767 ,CPU Targets Byte Offset 767 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO766 ,CPU Targets Byte Offset 766 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO765 ,CPU Targets Byte Offset 765 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO764 ,CPU Targets Byte Offset 764 " else rgroup.long 0xAE0++0x03 line.long 0x00 "GICD_ITARGETSR184,Interrupt Processor Targets Register 184" rgroup.long 0xAE4++0x03 line.long 0x00 "GICD_ITARGETSR185,Interrupt Processor Targets Register 185" rgroup.long 0xAE8++0x03 line.long 0x00 "GICD_ITARGETSR186,Interrupt Processor Targets Register 186" rgroup.long 0xAEC++0x03 line.long 0x00 "GICD_ITARGETSR187,Interrupt Processor Targets Register 187" rgroup.long 0xAF0++0x03 line.long 0x00 "GICD_ITARGETSR188,Interrupt Processor Targets Register 188" rgroup.long 0xAF4++0x03 line.long 0x00 "GICD_ITARGETSR189,Interrupt Processor Targets Register 189" rgroup.long 0xAF8++0x03 line.long 0x00 "GICD_ITARGETSR190,Interrupt Processor Targets Register 190" rgroup.long 0xAFC++0x03 line.long 0x00 "GICD_ITARGETSR191,Interrupt Processor Targets Register 191" endif if (((per.l(ad:(per.long(spr:0x31F30)&0xFFFC0000)+0x04))&0x0000001F)>=0x18) group.long 0xB00++0x03 line.long 0x00 "GICD_ITARGETSR192,Interrupt Processor Targets Register 192" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO771 ,CPU Targets Byte Offset 771 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO770 ,CPU Targets Byte Offset 770 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO769 ,CPU Targets Byte Offset 769 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO768 ,CPU Targets Byte Offset 768 " group.long 0xB04++0x03 line.long 0x00 "GICD_ITARGETSR193,Interrupt Processor Targets Register 193" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO775 ,CPU Targets Byte Offset 775 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO774 ,CPU Targets Byte Offset 774 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO773 ,CPU Targets Byte Offset 773 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO772 ,CPU Targets Byte Offset 772 " group.long 0xB08++0x03 line.long 0x00 "GICD_ITARGETSR194,Interrupt Processor Targets Register 194" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO779 ,CPU Targets Byte Offset 779 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO778 ,CPU Targets Byte Offset 778 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO777 ,CPU Targets Byte Offset 777 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO776 ,CPU Targets Byte Offset 776 " group.long 0xB0C++0x03 line.long 0x00 "GICD_ITARGETSR195,Interrupt Processor Targets Register 195" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO783 ,CPU Targets Byte Offset 783 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO782 ,CPU Targets Byte Offset 782 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO781 ,CPU Targets Byte Offset 781 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO780 ,CPU Targets Byte Offset 780 " group.long 0xB10++0x03 line.long 0x00 "GICD_ITARGETSR196,Interrupt Processor Targets Register 196" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO787 ,CPU Targets Byte Offset 787 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO786 ,CPU Targets Byte Offset 786 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO785 ,CPU Targets Byte Offset 785 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO784 ,CPU Targets Byte Offset 784 " group.long 0xB14++0x03 line.long 0x00 "GICD_ITARGETSR197,Interrupt Processor Targets Register 197" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO791 ,CPU Targets Byte Offset 791 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO790 ,CPU Targets Byte Offset 790 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO789 ,CPU Targets Byte Offset 789 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO788 ,CPU Targets Byte Offset 788 " group.long 0xB18++0x03 line.long 0x00 "GICD_ITARGETSR198,Interrupt Processor Targets Register 198" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO795 ,CPU Targets Byte Offset 795 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO794 ,CPU Targets Byte Offset 794 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO793 ,CPU Targets Byte Offset 793 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO792 ,CPU Targets Byte Offset 792 " group.long 0xB1C++0x03 line.long 0x00 "GICD_ITARGETSR199,Interrupt Processor Targets Register 199" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO799 ,CPU Targets Byte Offset 799 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO798 ,CPU Targets Byte Offset 798 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO797 ,CPU Targets Byte Offset 797 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO796 ,CPU Targets Byte Offset 796 " else rgroup.long 0xB00++0x03 line.long 0x00 "GICD_ITARGETSR192,Interrupt Processor Targets Register 192" rgroup.long 0xB04++0x03 line.long 0x00 "GICD_ITARGETSR193,Interrupt Processor Targets Register 193" rgroup.long 0xB08++0x03 line.long 0x00 "GICD_ITARGETSR194,Interrupt Processor Targets Register 194" rgroup.long 0xB0C++0x03 line.long 0x00 "GICD_ITARGETSR195,Interrupt Processor Targets Register 195" rgroup.long 0xB10++0x03 line.long 0x00 "GICD_ITARGETSR196,Interrupt Processor Targets Register 196" rgroup.long 0xB14++0x03 line.long 0x00 "GICD_ITARGETSR197,Interrupt Processor Targets Register 197" rgroup.long 0xB18++0x03 line.long 0x00 "GICD_ITARGETSR198,Interrupt Processor Targets Register 198" rgroup.long 0xB1C++0x03 line.long 0x00 "GICD_ITARGETSR199,Interrupt Processor Targets Register 199" endif if (((per.l(ad:(per.long(spr:0x31F30)&0xFFFC0000)+0x04))&0x0000001F)>=0x19) group.long 0xB20++0x03 line.long 0x00 "GICD_ITARGETSR200,Interrupt Processor Targets Register 200" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO803 ,CPU Targets Byte Offset 803 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO802 ,CPU Targets Byte Offset 802 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO801 ,CPU Targets Byte Offset 801 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO800 ,CPU Targets Byte Offset 800 " group.long 0xB24++0x03 line.long 0x00 "GICD_ITARGETSR201,Interrupt Processor Targets Register 201" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO807 ,CPU Targets Byte Offset 807 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO806 ,CPU Targets Byte Offset 806 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO805 ,CPU Targets Byte Offset 805 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO804 ,CPU Targets Byte Offset 804 " group.long 0xB28++0x03 line.long 0x00 "GICD_ITARGETSR202,Interrupt Processor Targets Register 202" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO811 ,CPU Targets Byte Offset 811 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO810 ,CPU Targets Byte Offset 810 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO809 ,CPU Targets Byte Offset 809 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO808 ,CPU Targets Byte Offset 808 " group.long 0xB2C++0x03 line.long 0x00 "GICD_ITARGETSR203,Interrupt Processor Targets Register 203" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO815 ,CPU Targets Byte Offset 815 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO814 ,CPU Targets Byte Offset 814 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO813 ,CPU Targets Byte Offset 813 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO812 ,CPU Targets Byte Offset 812 " group.long 0xB30++0x03 line.long 0x00 "GICD_ITARGETSR204,Interrupt Processor Targets Register 204" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO819 ,CPU Targets Byte Offset 819 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO818 ,CPU Targets Byte Offset 818 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO817 ,CPU Targets Byte Offset 817 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO816 ,CPU Targets Byte Offset 816 " group.long 0xB34++0x03 line.long 0x00 "GICD_ITARGETSR205,Interrupt Processor Targets Register 205" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO823 ,CPU Targets Byte Offset 823 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO822 ,CPU Targets Byte Offset 822 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO821 ,CPU Targets Byte Offset 821 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO820 ,CPU Targets Byte Offset 820 " group.long 0xB38++0x03 line.long 0x00 "GICD_ITARGETSR206,Interrupt Processor Targets Register 206" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO827 ,CPU Targets Byte Offset 827 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO826 ,CPU Targets Byte Offset 826 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO825 ,CPU Targets Byte Offset 825 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO824 ,CPU Targets Byte Offset 824 " group.long 0xB3C++0x03 line.long 0x00 "GICD_ITARGETSR207,Interrupt Processor Targets Register 207" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO831 ,CPU Targets Byte Offset 831 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO830 ,CPU Targets Byte Offset 830 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO829 ,CPU Targets Byte Offset 829 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO828 ,CPU Targets Byte Offset 828 " else rgroup.long 0xB20++0x03 line.long 0x00 "GICD_ITARGETSR200,Interrupt Processor Targets Register 200" rgroup.long 0xB24++0x03 line.long 0x00 "GICD_ITARGETSR201,Interrupt Processor Targets Register 201" rgroup.long 0xB28++0x03 line.long 0x00 "GICD_ITARGETSR202,Interrupt Processor Targets Register 202" rgroup.long 0xB2C++0x03 line.long 0x00 "GICD_ITARGETSR203,Interrupt Processor Targets Register 203" rgroup.long 0xB30++0x03 line.long 0x00 "GICD_ITARGETSR204,Interrupt Processor Targets Register 204" rgroup.long 0xB34++0x03 line.long 0x00 "GICD_ITARGETSR205,Interrupt Processor Targets Register 205" rgroup.long 0xB38++0x03 line.long 0x00 "GICD_ITARGETSR206,Interrupt Processor Targets Register 206" rgroup.long 0xB3C++0x03 line.long 0x00 "GICD_ITARGETSR207,Interrupt Processor Targets Register 207" endif if (((per.l(ad:(per.long(spr:0x31F30)&0xFFFC0000)+0x04))&0x0000001F)>=0x1A) group.long 0xB40++0x03 line.long 0x00 "GICD_ITARGETSR208,Interrupt Processor Targets Register 208" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO835 ,CPU Targets Byte Offset 835 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO834 ,CPU Targets Byte Offset 834 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO833 ,CPU Targets Byte Offset 833 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO832 ,CPU Targets Byte Offset 832 " group.long 0xB44++0x03 line.long 0x00 "GICD_ITARGETSR209,Interrupt Processor Targets Register 209" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO839 ,CPU Targets Byte Offset 839 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO838 ,CPU Targets Byte Offset 838 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO837 ,CPU Targets Byte Offset 837 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO836 ,CPU Targets Byte Offset 836 " group.long 0xB48++0x03 line.long 0x00 "GICD_ITARGETSR210,Interrupt Processor Targets Register 210" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO843 ,CPU Targets Byte Offset 843 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO842 ,CPU Targets Byte Offset 842 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO841 ,CPU Targets Byte Offset 841 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO840 ,CPU Targets Byte Offset 840 " group.long 0xB4C++0x03 line.long 0x00 "GICD_ITARGETSR211,Interrupt Processor Targets Register 211" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO847 ,CPU Targets Byte Offset 847 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO846 ,CPU Targets Byte Offset 846 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO845 ,CPU Targets Byte Offset 845 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO844 ,CPU Targets Byte Offset 844 " group.long 0xB50++0x03 line.long 0x00 "GICD_ITARGETSR212,Interrupt Processor Targets Register 212" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO851 ,CPU Targets Byte Offset 851 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO850 ,CPU Targets Byte Offset 850 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO849 ,CPU Targets Byte Offset 849 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO848 ,CPU Targets Byte Offset 848 " group.long 0xB54++0x03 line.long 0x00 "GICD_ITARGETSR213,Interrupt Processor Targets Register 213" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO855 ,CPU Targets Byte Offset 855 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO854 ,CPU Targets Byte Offset 854 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO853 ,CPU Targets Byte Offset 853 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO852 ,CPU Targets Byte Offset 852 " group.long 0xB58++0x03 line.long 0x00 "GICD_ITARGETSR214,Interrupt Processor Targets Register 214" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO859 ,CPU Targets Byte Offset 859 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO858 ,CPU Targets Byte Offset 858 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO857 ,CPU Targets Byte Offset 857 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO856 ,CPU Targets Byte Offset 856 " group.long 0xB5C++0x03 line.long 0x00 "GICD_ITARGETSR215,Interrupt Processor Targets Register 215" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO863 ,CPU Targets Byte Offset 863 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO862 ,CPU Targets Byte Offset 862 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO861 ,CPU Targets Byte Offset 861 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO860 ,CPU Targets Byte Offset 860 " else rgroup.long 0xB40++0x03 line.long 0x00 "GICD_ITARGETSR208,Interrupt Processor Targets Register 208" rgroup.long 0xB44++0x03 line.long 0x00 "GICD_ITARGETSR209,Interrupt Processor Targets Register 209" rgroup.long 0xB48++0x03 line.long 0x00 "GICD_ITARGETSR210,Interrupt Processor Targets Register 210" rgroup.long 0xB4C++0x03 line.long 0x00 "GICD_ITARGETSR211,Interrupt Processor Targets Register 211" rgroup.long 0xB50++0x03 line.long 0x00 "GICD_ITARGETSR212,Interrupt Processor Targets Register 212" rgroup.long 0xB54++0x03 line.long 0x00 "GICD_ITARGETSR213,Interrupt Processor Targets Register 213" rgroup.long 0xB58++0x03 line.long 0x00 "GICD_ITARGETSR214,Interrupt Processor Targets Register 214" rgroup.long 0xB5C++0x03 line.long 0x00 "GICD_ITARGETSR215,Interrupt Processor Targets Register 215" endif if (((per.l(ad:(per.long(spr:0x31F30)&0xFFFC0000)+0x04))&0x0000001F)>=0x1B) group.long 0xB60++0x03 line.long 0x00 "GICD_ITARGETSR216,Interrupt Processor Targets Register 216" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO867 ,CPU Targets Byte Offset 867 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO866 ,CPU Targets Byte Offset 866 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO865 ,CPU Targets Byte Offset 865 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO864 ,CPU Targets Byte Offset 864 " group.long 0xB64++0x03 line.long 0x00 "GICD_ITARGETSR217,Interrupt Processor Targets Register 217" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO871 ,CPU Targets Byte Offset 871 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO870 ,CPU Targets Byte Offset 870 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO869 ,CPU Targets Byte Offset 869 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO868 ,CPU Targets Byte Offset 868 " group.long 0xB68++0x03 line.long 0x00 "GICD_ITARGETSR218,Interrupt Processor Targets Register 218" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO875 ,CPU Targets Byte Offset 875 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO874 ,CPU Targets Byte Offset 874 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO873 ,CPU Targets Byte Offset 873 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO872 ,CPU Targets Byte Offset 872 " group.long 0xB6C++0x03 line.long 0x00 "GICD_ITARGETSR219,Interrupt Processor Targets Register 219" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO879 ,CPU Targets Byte Offset 879 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO878 ,CPU Targets Byte Offset 878 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO877 ,CPU Targets Byte Offset 877 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO876 ,CPU Targets Byte Offset 876 " group.long 0xB70++0x03 line.long 0x00 "GICD_ITARGETSR220,Interrupt Processor Targets Register 220" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO883 ,CPU Targets Byte Offset 883 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO882 ,CPU Targets Byte Offset 882 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO881 ,CPU Targets Byte Offset 881 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO880 ,CPU Targets Byte Offset 880 " group.long 0xB74++0x03 line.long 0x00 "GICD_ITARGETSR221,Interrupt Processor Targets Register 221" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO887 ,CPU Targets Byte Offset 887 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO886 ,CPU Targets Byte Offset 886 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO885 ,CPU Targets Byte Offset 885 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO884 ,CPU Targets Byte Offset 884 " group.long 0xB78++0x03 line.long 0x00 "GICD_ITARGETSR222,Interrupt Processor Targets Register 222" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO891 ,CPU Targets Byte Offset 891 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO890 ,CPU Targets Byte Offset 890 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO889 ,CPU Targets Byte Offset 889 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO888 ,CPU Targets Byte Offset 888 " group.long 0xB7C++0x03 line.long 0x00 "GICD_ITARGETSR223,Interrupt Processor Targets Register 223" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO895 ,CPU Targets Byte Offset 895 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO894 ,CPU Targets Byte Offset 894 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO893 ,CPU Targets Byte Offset 893 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO892 ,CPU Targets Byte Offset 892 " else rgroup.long 0xB60++0x03 line.long 0x00 "GICD_ITARGETSR216,Interrupt Processor Targets Register 216" rgroup.long 0xB64++0x03 line.long 0x00 "GICD_ITARGETSR217,Interrupt Processor Targets Register 217" rgroup.long 0xB68++0x03 line.long 0x00 "GICD_ITARGETSR218,Interrupt Processor Targets Register 218" rgroup.long 0xB6C++0x03 line.long 0x00 "GICD_ITARGETSR219,Interrupt Processor Targets Register 219" rgroup.long 0xB70++0x03 line.long 0x00 "GICD_ITARGETSR220,Interrupt Processor Targets Register 220" rgroup.long 0xB74++0x03 line.long 0x00 "GICD_ITARGETSR221,Interrupt Processor Targets Register 221" rgroup.long 0xB78++0x03 line.long 0x00 "GICD_ITARGETSR222,Interrupt Processor Targets Register 222" rgroup.long 0xB7C++0x03 line.long 0x00 "GICD_ITARGETSR223,Interrupt Processor Targets Register 223" endif if (((per.l(ad:(per.long(spr:0x31F30)&0xFFFC0000)+0x04))&0x0000001F)>=0x1C) group.long 0xB80++0x03 line.long 0x00 "GICD_ITARGETSR224,Interrupt Processor Targets Register 224" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO899 ,CPU Targets Byte Offset 899 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO898 ,CPU Targets Byte Offset 898 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO897 ,CPU Targets Byte Offset 897 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO896 ,CPU Targets Byte Offset 896 " group.long 0xB84++0x03 line.long 0x00 "GICD_ITARGETSR225,Interrupt Processor Targets Register 225" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO903 ,CPU Targets Byte Offset 903 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO902 ,CPU Targets Byte Offset 902 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO901 ,CPU Targets Byte Offset 901 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO900 ,CPU Targets Byte Offset 900 " group.long 0xB88++0x03 line.long 0x00 "GICD_ITARGETSR226,Interrupt Processor Targets Register 226" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO907 ,CPU Targets Byte Offset 907 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO906 ,CPU Targets Byte Offset 906 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO905 ,CPU Targets Byte Offset 905 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO904 ,CPU Targets Byte Offset 904 " group.long 0xB8C++0x03 line.long 0x00 "GICD_ITARGETSR227,Interrupt Processor Targets Register 227" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO911 ,CPU Targets Byte Offset 911 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO910 ,CPU Targets Byte Offset 910 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO909 ,CPU Targets Byte Offset 909 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO908 ,CPU Targets Byte Offset 908 " group.long 0xB90++0x03 line.long 0x00 "GICD_ITARGETSR228,Interrupt Processor Targets Register 228" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO915 ,CPU Targets Byte Offset 915 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO914 ,CPU Targets Byte Offset 914 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO913 ,CPU Targets Byte Offset 913 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO912 ,CPU Targets Byte Offset 912 " group.long 0xB94++0x03 line.long 0x00 "GICD_ITARGETSR229,Interrupt Processor Targets Register 229" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO919 ,CPU Targets Byte Offset 919 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO918 ,CPU Targets Byte Offset 918 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO917 ,CPU Targets Byte Offset 917 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO916 ,CPU Targets Byte Offset 916 " group.long 0xB98++0x03 line.long 0x00 "GICD_ITARGETSR230,Interrupt Processor Targets Register 230" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO923 ,CPU Targets Byte Offset 923 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO922 ,CPU Targets Byte Offset 922 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO921 ,CPU Targets Byte Offset 921 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO920 ,CPU Targets Byte Offset 920 " group.long 0xB9C++0x03 line.long 0x00 "GICD_ITARGETSR231,Interrupt Processor Targets Register 231" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO927 ,CPU Targets Byte Offset 927 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO926 ,CPU Targets Byte Offset 926 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO925 ,CPU Targets Byte Offset 925 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO924 ,CPU Targets Byte Offset 924 " else rgroup.long 0xB80++0x03 line.long 0x00 "GICD_ITARGETSR224,Interrupt Processor Targets Register 224" rgroup.long 0xB84++0x03 line.long 0x00 "GICD_ITARGETSR225,Interrupt Processor Targets Register 225" rgroup.long 0xB88++0x03 line.long 0x00 "GICD_ITARGETSR226,Interrupt Processor Targets Register 226" rgroup.long 0xB8C++0x03 line.long 0x00 "GICD_ITARGETSR227,Interrupt Processor Targets Register 227" rgroup.long 0xB90++0x03 line.long 0x00 "GICD_ITARGETSR228,Interrupt Processor Targets Register 228" rgroup.long 0xB94++0x03 line.long 0x00 "GICD_ITARGETSR229,Interrupt Processor Targets Register 229" rgroup.long 0xB98++0x03 line.long 0x00 "GICD_ITARGETSR230,Interrupt Processor Targets Register 230" rgroup.long 0xB9C++0x03 line.long 0x00 "GICD_ITARGETSR231,Interrupt Processor Targets Register 231" endif if (((per.l(ad:(per.long(spr:0x31F30)&0xFFFC0000)+0x04))&0x0000001F)>=0x1D) group.long 0xBA0++0x03 line.long 0x00 "GICD_ITARGETSR232,Interrupt Processor Targets Register 232" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO931 ,CPU Targets Byte Offset 931 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO930 ,CPU Targets Byte Offset 930 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO929 ,CPU Targets Byte Offset 929 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO928 ,CPU Targets Byte Offset 928 " group.long 0xBA4++0x03 line.long 0x00 "GICD_ITARGETSR233,Interrupt Processor Targets Register 233" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO935 ,CPU Targets Byte Offset 935 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO934 ,CPU Targets Byte Offset 934 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO933 ,CPU Targets Byte Offset 933 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO932 ,CPU Targets Byte Offset 932 " group.long 0xBA8++0x03 line.long 0x00 "GICD_ITARGETSR234,Interrupt Processor Targets Register 234" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO939 ,CPU Targets Byte Offset 939 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO938 ,CPU Targets Byte Offset 938 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO937 ,CPU Targets Byte Offset 937 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO936 ,CPU Targets Byte Offset 936 " group.long 0xBAC++0x03 line.long 0x00 "GICD_ITARGETSR235,Interrupt Processor Targets Register 235" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO943 ,CPU Targets Byte Offset 943 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO942 ,CPU Targets Byte Offset 942 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO941 ,CPU Targets Byte Offset 941 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO940 ,CPU Targets Byte Offset 940 " group.long 0xBB0++0x03 line.long 0x00 "GICD_ITARGETSR236,Interrupt Processor Targets Register 236" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO947 ,CPU Targets Byte Offset 947 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO946 ,CPU Targets Byte Offset 946 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO945 ,CPU Targets Byte Offset 945 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO944 ,CPU Targets Byte Offset 944 " group.long 0xBB4++0x03 line.long 0x00 "GICD_ITARGETSR237,Interrupt Processor Targets Register 237" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO951 ,CPU Targets Byte Offset 951 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO950 ,CPU Targets Byte Offset 950 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO949 ,CPU Targets Byte Offset 949 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO948 ,CPU Targets Byte Offset 948 " group.long 0xBB8++0x03 line.long 0x00 "GICD_ITARGETSR238,Interrupt Processor Targets Register 238" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO955 ,CPU Targets Byte Offset 955 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO954 ,CPU Targets Byte Offset 954 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO953 ,CPU Targets Byte Offset 953 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO952 ,CPU Targets Byte Offset 952 " group.long 0xBBC++0x03 line.long 0x00 "GICD_ITARGETSR239,Interrupt Processor Targets Register 239" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO959 ,CPU Targets Byte Offset 959 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO958 ,CPU Targets Byte Offset 958 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO957 ,CPU Targets Byte Offset 957 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO956 ,CPU Targets Byte Offset 956 " else rgroup.long 0xBA0++0x03 line.long 0x00 "GICD_ITARGETSR232,Interrupt Processor Targets Register 232" rgroup.long 0xBA4++0x03 line.long 0x00 "GICD_ITARGETSR233,Interrupt Processor Targets Register 233" rgroup.long 0xBA8++0x03 line.long 0x00 "GICD_ITARGETSR234,Interrupt Processor Targets Register 234" rgroup.long 0xBAC++0x03 line.long 0x00 "GICD_ITARGETSR235,Interrupt Processor Targets Register 235" rgroup.long 0xBB0++0x03 line.long 0x00 "GICD_ITARGETSR236,Interrupt Processor Targets Register 236" rgroup.long 0xBB4++0x03 line.long 0x00 "GICD_ITARGETSR237,Interrupt Processor Targets Register 237" rgroup.long 0xBB8++0x03 line.long 0x00 "GICD_ITARGETSR238,Interrupt Processor Targets Register 238" rgroup.long 0xBBC++0x03 line.long 0x00 "GICD_ITARGETSR239,Interrupt Processor Targets Register 239" endif if (((per.l(ad:(per.long(spr:0x31F30)&0xFFFC0000)+0x04))&0x0000001F)>=0x1E) group.long 0xBC0++0x03 line.long 0x00 "GICD_ITARGETSR240,Interrupt Processor Targets Register 240" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO963 ,CPU Targets Byte Offset 963 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO962 ,CPU Targets Byte Offset 962 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO961 ,CPU Targets Byte Offset 961 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO960 ,CPU Targets Byte Offset 960 " group.long 0xBC4++0x03 line.long 0x00 "GICD_ITARGETSR241,Interrupt Processor Targets Register 241" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO967 ,CPU Targets Byte Offset 967 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO966 ,CPU Targets Byte Offset 966 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO965 ,CPU Targets Byte Offset 965 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO964 ,CPU Targets Byte Offset 964 " group.long 0xBC8++0x03 line.long 0x00 "GICD_ITARGETSR242,Interrupt Processor Targets Register 242" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO971 ,CPU Targets Byte Offset 971 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO970 ,CPU Targets Byte Offset 970 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO969 ,CPU Targets Byte Offset 969 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO968 ,CPU Targets Byte Offset 968 " group.long 0xBCC++0x03 line.long 0x00 "GICD_ITARGETSR243,Interrupt Processor Targets Register 243" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO975 ,CPU Targets Byte Offset 975 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO974 ,CPU Targets Byte Offset 974 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO973 ,CPU Targets Byte Offset 973 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO972 ,CPU Targets Byte Offset 972 " group.long 0xBD0++0x03 line.long 0x00 "GICD_ITARGETSR244,Interrupt Processor Targets Register 244" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO979 ,CPU Targets Byte Offset 979 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO978 ,CPU Targets Byte Offset 978 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO977 ,CPU Targets Byte Offset 977 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO976 ,CPU Targets Byte Offset 976 " group.long 0xBD4++0x03 line.long 0x00 "GICD_ITARGETSR245,Interrupt Processor Targets Register 245" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO983 ,CPU Targets Byte Offset 983 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO982 ,CPU Targets Byte Offset 982 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO981 ,CPU Targets Byte Offset 981 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO980 ,CPU Targets Byte Offset 980 " group.long 0xBD8++0x03 line.long 0x00 "GICD_ITARGETSR246,Interrupt Processor Targets Register 246" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO987 ,CPU Targets Byte Offset 987 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO986 ,CPU Targets Byte Offset 986 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO985 ,CPU Targets Byte Offset 985 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO984 ,CPU Targets Byte Offset 984 " group.long 0xBDC++0x03 line.long 0x00 "GICD_ITARGETSR247,Interrupt Processor Targets Register 247" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO991 ,CPU Targets Byte Offset 991 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO990 ,CPU Targets Byte Offset 990 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO989 ,CPU Targets Byte Offset 989 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO988 ,CPU Targets Byte Offset 988 " else rgroup.long 0xBC0++0x03 line.long 0x00 "GICD_ITARGETSR240,Interrupt Processor Targets Register 240" rgroup.long 0xBC4++0x03 line.long 0x00 "GICD_ITARGETSR241,Interrupt Processor Targets Register 241" rgroup.long 0xBC8++0x03 line.long 0x00 "GICD_ITARGETSR242,Interrupt Processor Targets Register 242" rgroup.long 0xBCC++0x03 line.long 0x00 "GICD_ITARGETSR243,Interrupt Processor Targets Register 243" rgroup.long 0xBD0++0x03 line.long 0x00 "GICD_ITARGETSR244,Interrupt Processor Targets Register 244" rgroup.long 0xBD4++0x03 line.long 0x00 "GICD_ITARGETSR245,Interrupt Processor Targets Register 245" rgroup.long 0xBD8++0x03 line.long 0x00 "GICD_ITARGETSR246,Interrupt Processor Targets Register 246" rgroup.long 0xBDC++0x03 line.long 0x00 "GICD_ITARGETSR247,Interrupt Processor Targets Register 247" endif if (((per.l(ad:(per.long(spr:0x31F30)&0xFFFC0000)+0x04))&0x0000001F)>=0x1F) group.long 0xBE0++0x03 line.long 0x00 "GICD_ITARGETSR248,Interrupt Processor Targets Register 248" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO995 ,CPU Targets Byte Offset 995 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO994 ,CPU Targets Byte Offset 994 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO993 ,CPU Targets Byte Offset 993 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO992 ,CPU Targets Byte Offset 992 " group.long 0xBE4++0x03 line.long 0x00 "GICD_ITARGETSR249,Interrupt Processor Targets Register 249" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO999 ,CPU Targets Byte Offset 999 " hexmask.long.byte 0x00 16.--23. 1. " CPUTBO998 ,CPU Targets Byte Offset 998 " hexmask.long.byte 0x00 8.--15. 1. " CPUTBO997 ,CPU Targets Byte Offset 997 " hexmask.long.byte 0x00 0.--7. 1. " CPUTBO996 ,CPU Targets Byte Offset 996 " group.long 0xBE8++0x03 line.long 0x00 "GICD_ITARGETSR250,Interrupt Processor Targets Register 250" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO1003 ,CPU Targets Byte Offset 1003" hexmask.long.byte 0x00 16.--23. 1. " CPUTBO1002 ,CPU Targets Byte Offset 1002" hexmask.long.byte 0x00 8.--15. 1. " CPUTBO1001 ,CPU Targets Byte Offset 1001" hexmask.long.byte 0x00 0.--7. 1. " CPUTBO1000 ,CPU Targets Byte Offset 1000" group.long 0xBEC++0x03 line.long 0x00 "GICD_ITARGETSR251,Interrupt Processor Targets Register 251" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO1007 ,CPU Targets Byte Offset 1007" hexmask.long.byte 0x00 16.--23. 1. " CPUTBO1006 ,CPU Targets Byte Offset 1006" hexmask.long.byte 0x00 8.--15. 1. " CPUTBO1005 ,CPU Targets Byte Offset 1005" hexmask.long.byte 0x00 0.--7. 1. " CPUTBO1004 ,CPU Targets Byte Offset 1004" group.long 0xBF0++0x03 line.long 0x00 "GICD_ITARGETSR252,Interrupt Processor Targets Register 252" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO1011 ,CPU Targets Byte Offset 1011" hexmask.long.byte 0x00 16.--23. 1. " CPUTBO1010 ,CPU Targets Byte Offset 1010" hexmask.long.byte 0x00 8.--15. 1. " CPUTBO1009 ,CPU Targets Byte Offset 1009" hexmask.long.byte 0x00 0.--7. 1. " CPUTBO1008 ,CPU Targets Byte Offset 1008" group.long 0xBF4++0x03 line.long 0x00 "GICD_ITARGETSR253,Interrupt Processor Targets Register 253" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO1015 ,CPU Targets Byte Offset 1015" hexmask.long.byte 0x00 16.--23. 1. " CPUTBO1014 ,CPU Targets Byte Offset 1014" hexmask.long.byte 0x00 8.--15. 1. " CPUTBO1013 ,CPU Targets Byte Offset 1013" hexmask.long.byte 0x00 0.--7. 1. " CPUTBO1012 ,CPU Targets Byte Offset 1012" group.long 0xBF8++0x03 line.long 0x00 "GICD_ITARGETSR254,Interrupt Processor Targets Register 254" hexmask.long.byte 0x00 24.--31. 1. " CPUTBO1019 ,CPU Targets Byte Offset 1019" hexmask.long.byte 0x00 16.--23. 1. " CPUTBO1018 ,CPU Targets Byte Offset 1018" hexmask.long.byte 0x00 8.--15. 1. " CPUTBO1017 ,CPU Targets Byte Offset 1017" hexmask.long.byte 0x00 0.--7. 1. " CPUTBO1016 ,CPU Targets Byte Offset 1016" else rgroup.long 0xBE0++0x03 line.long 0x00 "GICD_ITARGETSR248,Interrupt Processor Targets Register 248" rgroup.long 0xBE4++0x03 line.long 0x00 "GICD_ITARGETSR249,Interrupt Processor Targets Register 249" rgroup.long 0xBE8++0x03 line.long 0x00 "GICD_ITARGETSR250,Interrupt Processor Targets Register 250" rgroup.long 0xBEC++0x03 line.long 0x00 "GICD_ITARGETSR251,Interrupt Processor Targets Register 251" rgroup.long 0xBF0++0x03 line.long 0x00 "GICD_ITARGETSR252,Interrupt Processor Targets Register 252" rgroup.long 0xBF4++0x03 line.long 0x00 "GICD_ITARGETSR253,Interrupt Processor Targets Register 253" rgroup.long 0xBF8++0x03 line.long 0x00 "GICD_ITARGETSR254,Interrupt Processor Targets Register 254" endif else rgroup.long 0x800++0x03 line.long 0x00 "GICD_ITARGETSR0 ,Interrupt Processor Targets Register 0 " rgroup.long 0x804++0x03 line.long 0x00 "GICD_ITARGETSR1 ,Interrupt Processor Targets Register 1 " rgroup.long 0x808++0x03 line.long 0x00 "GICD_ITARGETSR2 ,Interrupt Processor Targets Register 2 " rgroup.long 0x80C++0x03 line.long 0x00 "GICD_ITARGETSR3 ,Interrupt Processor Targets Register 3 " rgroup.long 0x810++0x03 line.long 0x00 "GICD_ITARGETSR4 ,Interrupt Processor Targets Register 4 " rgroup.long 0x814++0x03 line.long 0x00 "GICD_ITARGETSR5 ,Interrupt Processor Targets Register 5 " rgroup.long 0x818++0x03 line.long 0x00 "GICD_ITARGETSR6 ,Interrupt Processor Targets Register 6 " rgroup.long 0x81C++0x03 line.long 0x00 "GICD_ITARGETSR7 ,Interrupt Processor Targets Register 7 " rgroup.long 0x820++0x03 line.long 0x00 "GICD_ITARGETSR8 ,Interrupt Processor Targets Register 8 " rgroup.long 0x824++0x03 line.long 0x00 "GICD_ITARGETSR9 ,Interrupt Processor Targets Register 9 " rgroup.long 0x828++0x03 line.long 0x00 "GICD_ITARGETSR10 ,Interrupt Processor Targets Register 10 " rgroup.long 0x82C++0x03 line.long 0x00 "GICD_ITARGETSR11 ,Interrupt Processor Targets Register 11 " rgroup.long 0x830++0x03 line.long 0x00 "GICD_ITARGETSR12 ,Interrupt Processor Targets Register 12 " rgroup.long 0x834++0x03 line.long 0x00 "GICD_ITARGETSR13 ,Interrupt Processor Targets Register 13 " rgroup.long 0x838++0x03 line.long 0x00 "GICD_ITARGETSR14 ,Interrupt Processor Targets Register 14 " rgroup.long 0x83C++0x03 line.long 0x00 "GICD_ITARGETSR15 ,Interrupt Processor Targets Register 15 " rgroup.long 0x840++0x03 line.long 0x00 "GICD_ITARGETSR16 ,Interrupt Processor Targets Register 16 " rgroup.long 0x844++0x03 line.long 0x00 "GICD_ITARGETSR17 ,Interrupt Processor Targets Register 17 " rgroup.long 0x848++0x03 line.long 0x00 "GICD_ITARGETSR18 ,Interrupt Processor Targets Register 18 " rgroup.long 0x84C++0x03 line.long 0x00 "GICD_ITARGETSR19 ,Interrupt Processor Targets Register 19 " rgroup.long 0x850++0x03 line.long 0x00 "GICD_ITARGETSR20 ,Interrupt Processor Targets Register 20 " rgroup.long 0x854++0x03 line.long 0x00 "GICD_ITARGETSR21 ,Interrupt Processor Targets Register 21 " rgroup.long 0x858++0x03 line.long 0x00 "GICD_ITARGETSR22 ,Interrupt Processor Targets Register 22 " rgroup.long 0x85C++0x03 line.long 0x00 "GICD_ITARGETSR23 ,Interrupt Processor Targets Register 23 " rgroup.long 0x860++0x03 line.long 0x00 "GICD_ITARGETSR24 ,Interrupt Processor Targets Register 24 " rgroup.long 0x864++0x03 line.long 0x00 "GICD_ITARGETSR25 ,Interrupt Processor Targets Register 25 " rgroup.long 0x868++0x03 line.long 0x00 "GICD_ITARGETSR26 ,Interrupt Processor Targets Register 26 " rgroup.long 0x86C++0x03 line.long 0x00 "GICD_ITARGETSR27 ,Interrupt Processor Targets Register 27 " rgroup.long 0x870++0x03 line.long 0x00 "GICD_ITARGETSR28 ,Interrupt Processor Targets Register 28 " rgroup.long 0x874++0x03 line.long 0x00 "GICD_ITARGETSR29 ,Interrupt Processor Targets Register 29 " rgroup.long 0x878++0x03 line.long 0x00 "GICD_ITARGETSR30 ,Interrupt Processor Targets Register 30 " rgroup.long 0x87C++0x03 line.long 0x00 "GICD_ITARGETSR31 ,Interrupt Processor Targets Register 31 " rgroup.long 0x880++0x03 line.long 0x00 "GICD_ITARGETSR32 ,Interrupt Processor Targets Register 32 " rgroup.long 0x884++0x03 line.long 0x00 "GICD_ITARGETSR33 ,Interrupt Processor Targets Register 33 " rgroup.long 0x888++0x03 line.long 0x00 "GICD_ITARGETSR34 ,Interrupt Processor Targets Register 34 " rgroup.long 0x88C++0x03 line.long 0x00 "GICD_ITARGETSR35 ,Interrupt Processor Targets Register 35 " rgroup.long 0x890++0x03 line.long 0x00 "GICD_ITARGETSR36 ,Interrupt Processor Targets Register 36 " rgroup.long 0x894++0x03 line.long 0x00 "GICD_ITARGETSR37 ,Interrupt Processor Targets Register 37 " rgroup.long 0x898++0x03 line.long 0x00 "GICD_ITARGETSR38 ,Interrupt Processor Targets Register 38 " rgroup.long 0x89C++0x03 line.long 0x00 "GICD_ITARGETSR39 ,Interrupt Processor Targets Register 39 " rgroup.long 0x8A0++0x03 line.long 0x00 "GICD_ITARGETSR40 ,Interrupt Processor Targets Register 40 " rgroup.long 0x8A4++0x03 line.long 0x00 "GICD_ITARGETSR41 ,Interrupt Processor Targets Register 41 " rgroup.long 0x8A8++0x03 line.long 0x00 "GICD_ITARGETSR42 ,Interrupt Processor Targets Register 42 " rgroup.long 0x8AC++0x03 line.long 0x00 "GICD_ITARGETSR43 ,Interrupt Processor Targets Register 43 " rgroup.long 0x8B0++0x03 line.long 0x00 "GICD_ITARGETSR44 ,Interrupt Processor Targets Register 44 " rgroup.long 0x8B4++0x03 line.long 0x00 "GICD_ITARGETSR45 ,Interrupt Processor Targets Register 45 " rgroup.long 0x8B8++0x03 line.long 0x00 "GICD_ITARGETSR46 ,Interrupt Processor Targets Register 46 " rgroup.long 0x8BC++0x03 line.long 0x00 "GICD_ITARGETSR47 ,Interrupt Processor Targets Register 47 " rgroup.long 0x8C0++0x03 line.long 0x00 "GICD_ITARGETSR48 ,Interrupt Processor Targets Register 48 " rgroup.long 0x8C4++0x03 line.long 0x00 "GICD_ITARGETSR49 ,Interrupt Processor Targets Register 49 " rgroup.long 0x8C8++0x03 line.long 0x00 "GICD_ITARGETSR50 ,Interrupt Processor Targets Register 50 " rgroup.long 0x8CC++0x03 line.long 0x00 "GICD_ITARGETSR51 ,Interrupt Processor Targets Register 51 " rgroup.long 0x8D0++0x03 line.long 0x00 "GICD_ITARGETSR52 ,Interrupt Processor Targets Register 52 " rgroup.long 0x8D4++0x03 line.long 0x00 "GICD_ITARGETSR53 ,Interrupt Processor Targets Register 53 " rgroup.long 0x8D8++0x03 line.long 0x00 "GICD_ITARGETSR54 ,Interrupt Processor Targets Register 54 " rgroup.long 0x8DC++0x03 line.long 0x00 "GICD_ITARGETSR55 ,Interrupt Processor Targets Register 55 " rgroup.long 0x8E0++0x03 line.long 0x00 "GICD_ITARGETSR56 ,Interrupt Processor Targets Register 56 " rgroup.long 0x8E4++0x03 line.long 0x00 "GICD_ITARGETSR57 ,Interrupt Processor Targets Register 57 " rgroup.long 0x8E8++0x03 line.long 0x00 "GICD_ITARGETSR58 ,Interrupt Processor Targets Register 58 " rgroup.long 0x8EC++0x03 line.long 0x00 "GICD_ITARGETSR59 ,Interrupt Processor Targets Register 59 " rgroup.long 0x8F0++0x03 line.long 0x00 "GICD_ITARGETSR60 ,Interrupt Processor Targets Register 60 " rgroup.long 0x8F4++0x03 line.long 0x00 "GICD_ITARGETSR61 ,Interrupt Processor Targets Register 61 " rgroup.long 0x8F8++0x03 line.long 0x00 "GICD_ITARGETSR62 ,Interrupt Processor Targets Register 62 " rgroup.long 0x8FC++0x03 line.long 0x00 "GICD_ITARGETSR63 ,Interrupt Processor Targets Register 63 " rgroup.long 0x900++0x03 line.long 0x00 "GICD_ITARGETSR64 ,Interrupt Processor Targets Register 64 " rgroup.long 0x904++0x03 line.long 0x00 "GICD_ITARGETSR65 ,Interrupt Processor Targets Register 65 " rgroup.long 0x908++0x03 line.long 0x00 "GICD_ITARGETSR66 ,Interrupt Processor Targets Register 66 " rgroup.long 0x90C++0x03 line.long 0x00 "GICD_ITARGETSR67 ,Interrupt Processor Targets Register 67 " rgroup.long 0x910++0x03 line.long 0x00 "GICD_ITARGETSR68 ,Interrupt Processor Targets Register 68 " rgroup.long 0x914++0x03 line.long 0x00 "GICD_ITARGETSR69 ,Interrupt Processor Targets Register 69 " rgroup.long 0x918++0x03 line.long 0x00 "GICD_ITARGETSR70 ,Interrupt Processor Targets Register 70 " rgroup.long 0x91C++0x03 line.long 0x00 "GICD_ITARGETSR71 ,Interrupt Processor Targets Register 71 " rgroup.long 0x920++0x03 line.long 0x00 "GICD_ITARGETSR72 ,Interrupt Processor Targets Register 72 " rgroup.long 0x924++0x03 line.long 0x00 "GICD_ITARGETSR73 ,Interrupt Processor Targets Register 73 " rgroup.long 0x928++0x03 line.long 0x00 "GICD_ITARGETSR74 ,Interrupt Processor Targets Register 74 " rgroup.long 0x92C++0x03 line.long 0x00 "GICD_ITARGETSR75 ,Interrupt Processor Targets Register 75 " rgroup.long 0x930++0x03 line.long 0x00 "GICD_ITARGETSR76 ,Interrupt Processor Targets Register 76 " rgroup.long 0x934++0x03 line.long 0x00 "GICD_ITARGETSR77 ,Interrupt Processor Targets Register 77 " rgroup.long 0x938++0x03 line.long 0x00 "GICD_ITARGETSR78 ,Interrupt Processor Targets Register 78 " rgroup.long 0x93C++0x03 line.long 0x00 "GICD_ITARGETSR79 ,Interrupt Processor Targets Register 79 " rgroup.long 0x940++0x03 line.long 0x00 "GICD_ITARGETSR80 ,Interrupt Processor Targets Register 80 " rgroup.long 0x944++0x03 line.long 0x00 "GICD_ITARGETSR81 ,Interrupt Processor Targets Register 81 " rgroup.long 0x948++0x03 line.long 0x00 "GICD_ITARGETSR82 ,Interrupt Processor Targets Register 82 " rgroup.long 0x94C++0x03 line.long 0x00 "GICD_ITARGETSR83 ,Interrupt Processor Targets Register 83 " rgroup.long 0x950++0x03 line.long 0x00 "GICD_ITARGETSR84 ,Interrupt Processor Targets Register 84 " rgroup.long 0x954++0x03 line.long 0x00 "GICD_ITARGETSR85 ,Interrupt Processor Targets Register 85 " rgroup.long 0x958++0x03 line.long 0x00 "GICD_ITARGETSR86 ,Interrupt Processor Targets Register 86 " rgroup.long 0x95C++0x03 line.long 0x00 "GICD_ITARGETSR87 ,Interrupt Processor Targets Register 87 " rgroup.long 0x960++0x03 line.long 0x00 "GICD_ITARGETSR88 ,Interrupt Processor Targets Register 88 " rgroup.long 0x964++0x03 line.long 0x00 "GICD_ITARGETSR89 ,Interrupt Processor Targets Register 89 " rgroup.long 0x968++0x03 line.long 0x00 "GICD_ITARGETSR90 ,Interrupt Processor Targets Register 90 " rgroup.long 0x96C++0x03 line.long 0x00 "GICD_ITARGETSR91 ,Interrupt Processor Targets Register 91 " rgroup.long 0x970++0x03 line.long 0x00 "GICD_ITARGETSR92 ,Interrupt Processor Targets Register 92 " rgroup.long 0x974++0x03 line.long 0x00 "GICD_ITARGETSR93 ,Interrupt Processor Targets Register 93 " rgroup.long 0x978++0x03 line.long 0x00 "GICD_ITARGETSR94 ,Interrupt Processor Targets Register 94 " rgroup.long 0x97C++0x03 line.long 0x00 "GICD_ITARGETSR95 ,Interrupt Processor Targets Register 95 " rgroup.long 0x980++0x03 line.long 0x00 "GICD_ITARGETSR96 ,Interrupt Processor Targets Register 96 " rgroup.long 0x984++0x03 line.long 0x00 "GICD_ITARGETSR97 ,Interrupt Processor Targets Register 97 " rgroup.long 0x988++0x03 line.long 0x00 "GICD_ITARGETSR98 ,Interrupt Processor Targets Register 98 " rgroup.long 0x98C++0x03 line.long 0x00 "GICD_ITARGETSR99 ,Interrupt Processor Targets Register 99 " rgroup.long 0x990++0x03 line.long 0x00 "GICD_ITARGETSR100,Interrupt Processor Targets Register 100" rgroup.long 0x994++0x03 line.long 0x00 "GICD_ITARGETSR101,Interrupt Processor Targets Register 101" rgroup.long 0x998++0x03 line.long 0x00 "GICD_ITARGETSR102,Interrupt Processor Targets Register 102" rgroup.long 0x99C++0x03 line.long 0x00 "GICD_ITARGETSR103,Interrupt Processor Targets Register 103" rgroup.long 0x9A0++0x03 line.long 0x00 "GICD_ITARGETSR104,Interrupt Processor Targets Register 104" rgroup.long 0x9A4++0x03 line.long 0x00 "GICD_ITARGETSR105,Interrupt Processor Targets Register 105" rgroup.long 0x9A8++0x03 line.long 0x00 "GICD_ITARGETSR106,Interrupt Processor Targets Register 106" rgroup.long 0x9AC++0x03 line.long 0x00 "GICD_ITARGETSR107,Interrupt Processor Targets Register 107" rgroup.long 0x9B0++0x03 line.long 0x00 "GICD_ITARGETSR108,Interrupt Processor Targets Register 108" rgroup.long 0x9B4++0x03 line.long 0x00 "GICD_ITARGETSR109,Interrupt Processor Targets Register 109" rgroup.long 0x9B8++0x03 line.long 0x00 "GICD_ITARGETSR110,Interrupt Processor Targets Register 110" rgroup.long 0x9BC++0x03 line.long 0x00 "GICD_ITARGETSR111,Interrupt Processor Targets Register 111" rgroup.long 0x9C0++0x03 line.long 0x00 "GICD_ITARGETSR112,Interrupt Processor Targets Register 112" rgroup.long 0x9C4++0x03 line.long 0x00 "GICD_ITARGETSR113,Interrupt Processor Targets Register 113" rgroup.long 0x9C8++0x03 line.long 0x00 "GICD_ITARGETSR114,Interrupt Processor Targets Register 114" rgroup.long 0x9CC++0x03 line.long 0x00 "GICD_ITARGETSR115,Interrupt Processor Targets Register 115" rgroup.long 0x9D0++0x03 line.long 0x00 "GICD_ITARGETSR116,Interrupt Processor Targets Register 116" rgroup.long 0x9D4++0x03 line.long 0x00 "GICD_ITARGETSR117,Interrupt Processor Targets Register 117" rgroup.long 0x9D8++0x03 line.long 0x00 "GICD_ITARGETSR118,Interrupt Processor Targets Register 118" rgroup.long 0x9DC++0x03 line.long 0x00 "GICD_ITARGETSR119,Interrupt Processor Targets Register 119" rgroup.long 0x9E0++0x03 line.long 0x00 "GICD_ITARGETSR120,Interrupt Processor Targets Register 120" rgroup.long 0x9E4++0x03 line.long 0x00 "GICD_ITARGETSR121,Interrupt Processor Targets Register 121" rgroup.long 0x9E8++0x03 line.long 0x00 "GICD_ITARGETSR122,Interrupt Processor Targets Register 122" rgroup.long 0x9EC++0x03 line.long 0x00 "GICD_ITARGETSR123,Interrupt Processor Targets Register 123" rgroup.long 0x9F0++0x03 line.long 0x00 "GICD_ITARGETSR124,Interrupt Processor Targets Register 124" rgroup.long 0x9F4++0x03 line.long 0x00 "GICD_ITARGETSR125,Interrupt Processor Targets Register 125" rgroup.long 0x9F8++0x03 line.long 0x00 "GICD_ITARGETSR126,Interrupt Processor Targets Register 126" rgroup.long 0x9FC++0x03 line.long 0x00 "GICD_ITARGETSR127,Interrupt Processor Targets Register 127" rgroup.long 0xA00++0x03 line.long 0x00 "GICD_ITARGETSR128,Interrupt Processor Targets Register 128" rgroup.long 0xA04++0x03 line.long 0x00 "GICD_ITARGETSR129,Interrupt Processor Targets Register 129" rgroup.long 0xA08++0x03 line.long 0x00 "GICD_ITARGETSR130,Interrupt Processor Targets Register 130" rgroup.long 0xA0C++0x03 line.long 0x00 "GICD_ITARGETSR131,Interrupt Processor Targets Register 131" rgroup.long 0xA10++0x03 line.long 0x00 "GICD_ITARGETSR132,Interrupt Processor Targets Register 132" rgroup.long 0xA14++0x03 line.long 0x00 "GICD_ITARGETSR133,Interrupt Processor Targets Register 133" rgroup.long 0xA18++0x03 line.long 0x00 "GICD_ITARGETSR134,Interrupt Processor Targets Register 134" rgroup.long 0xA1C++0x03 line.long 0x00 "GICD_ITARGETSR135,Interrupt Processor Targets Register 135" rgroup.long 0xA20++0x03 line.long 0x00 "GICD_ITARGETSR136,Interrupt Processor Targets Register 136" rgroup.long 0xA24++0x03 line.long 0x00 "GICD_ITARGETSR137,Interrupt Processor Targets Register 137" rgroup.long 0xA28++0x03 line.long 0x00 "GICD_ITARGETSR138,Interrupt Processor Targets Register 138" rgroup.long 0xA2C++0x03 line.long 0x00 "GICD_ITARGETSR139,Interrupt Processor Targets Register 139" rgroup.long 0xA30++0x03 line.long 0x00 "GICD_ITARGETSR140,Interrupt Processor Targets Register 140" rgroup.long 0xA34++0x03 line.long 0x00 "GICD_ITARGETSR141,Interrupt Processor Targets Register 141" rgroup.long 0xA38++0x03 line.long 0x00 "GICD_ITARGETSR142,Interrupt Processor Targets Register 142" rgroup.long 0xA3C++0x03 line.long 0x00 "GICD_ITARGETSR143,Interrupt Processor Targets Register 143" rgroup.long 0xA40++0x03 line.long 0x00 "GICD_ITARGETSR144,Interrupt Processor Targets Register 144" rgroup.long 0xA44++0x03 line.long 0x00 "GICD_ITARGETSR145,Interrupt Processor Targets Register 145" rgroup.long 0xA48++0x03 line.long 0x00 "GICD_ITARGETSR146,Interrupt Processor Targets Register 146" rgroup.long 0xA4C++0x03 line.long 0x00 "GICD_ITARGETSR147,Interrupt Processor Targets Register 147" rgroup.long 0xA50++0x03 line.long 0x00 "GICD_ITARGETSR148,Interrupt Processor Targets Register 148" rgroup.long 0xA54++0x03 line.long 0x00 "GICD_ITARGETSR149,Interrupt Processor Targets Register 149" rgroup.long 0xA58++0x03 line.long 0x00 "GICD_ITARGETSR150,Interrupt Processor Targets Register 150" rgroup.long 0xA5C++0x03 line.long 0x00 "GICD_ITARGETSR151,Interrupt Processor Targets Register 151" rgroup.long 0xA60++0x03 line.long 0x00 "GICD_ITARGETSR152,Interrupt Processor Targets Register 152" rgroup.long 0xA64++0x03 line.long 0x00 "GICD_ITARGETSR153,Interrupt Processor Targets Register 153" rgroup.long 0xA68++0x03 line.long 0x00 "GICD_ITARGETSR154,Interrupt Processor Targets Register 154" rgroup.long 0xA6C++0x03 line.long 0x00 "GICD_ITARGETSR155,Interrupt Processor Targets Register 155" rgroup.long 0xA70++0x03 line.long 0x00 "GICD_ITARGETSR156,Interrupt Processor Targets Register 156" rgroup.long 0xA74++0x03 line.long 0x00 "GICD_ITARGETSR157,Interrupt Processor Targets Register 157" rgroup.long 0xA78++0x03 line.long 0x00 "GICD_ITARGETSR158,Interrupt Processor Targets Register 158" rgroup.long 0xA7C++0x03 line.long 0x00 "GICD_ITARGETSR159,Interrupt Processor Targets Register 159" rgroup.long 0xA80++0x03 line.long 0x00 "GICD_ITARGETSR160,Interrupt Processor Targets Register 160" rgroup.long 0xA84++0x03 line.long 0x00 "GICD_ITARGETSR161,Interrupt Processor Targets Register 161" rgroup.long 0xA88++0x03 line.long 0x00 "GICD_ITARGETSR162,Interrupt Processor Targets Register 162" rgroup.long 0xA8C++0x03 line.long 0x00 "GICD_ITARGETSR163,Interrupt Processor Targets Register 163" rgroup.long 0xA90++0x03 line.long 0x00 "GICD_ITARGETSR164,Interrupt Processor Targets Register 164" rgroup.long 0xA94++0x03 line.long 0x00 "GICD_ITARGETSR165,Interrupt Processor Targets Register 165" rgroup.long 0xA98++0x03 line.long 0x00 "GICD_ITARGETSR166,Interrupt Processor Targets Register 166" rgroup.long 0xA9C++0x03 line.long 0x00 "GICD_ITARGETSR167,Interrupt Processor Targets Register 167" rgroup.long 0xAA0++0x03 line.long 0x00 "GICD_ITARGETSR168,Interrupt Processor Targets Register 168" rgroup.long 0xAA4++0x03 line.long 0x00 "GICD_ITARGETSR169,Interrupt Processor Targets Register 169" rgroup.long 0xAA8++0x03 line.long 0x00 "GICD_ITARGETSR170,Interrupt Processor Targets Register 170" rgroup.long 0xAAC++0x03 line.long 0x00 "GICD_ITARGETSR171,Interrupt Processor Targets Register 171" rgroup.long 0xAB0++0x03 line.long 0x00 "GICD_ITARGETSR172,Interrupt Processor Targets Register 172" rgroup.long 0xAB4++0x03 line.long 0x00 "GICD_ITARGETSR173,Interrupt Processor Targets Register 173" rgroup.long 0xAB8++0x03 line.long 0x00 "GICD_ITARGETSR174,Interrupt Processor Targets Register 174" rgroup.long 0xABC++0x03 line.long 0x00 "GICD_ITARGETSR175,Interrupt Processor Targets Register 175" rgroup.long 0xAC0++0x03 line.long 0x00 "GICD_ITARGETSR176,Interrupt Processor Targets Register 176" rgroup.long 0xAC4++0x03 line.long 0x00 "GICD_ITARGETSR177,Interrupt Processor Targets Register 177" rgroup.long 0xAC8++0x03 line.long 0x00 "GICD_ITARGETSR178,Interrupt Processor Targets Register 178" rgroup.long 0xACC++0x03 line.long 0x00 "GICD_ITARGETSR179,Interrupt Processor Targets Register 179" rgroup.long 0xAD0++0x03 line.long 0x00 "GICD_ITARGETSR180,Interrupt Processor Targets Register 180" rgroup.long 0xAD4++0x03 line.long 0x00 "GICD_ITARGETSR181,Interrupt Processor Targets Register 181" rgroup.long 0xAD8++0x03 line.long 0x00 "GICD_ITARGETSR182,Interrupt Processor Targets Register 182" rgroup.long 0xADC++0x03 line.long 0x00 "GICD_ITARGETSR183,Interrupt Processor Targets Register 183" rgroup.long 0xAE0++0x03 line.long 0x00 "GICD_ITARGETSR184,Interrupt Processor Targets Register 184" rgroup.long 0xAE4++0x03 line.long 0x00 "GICD_ITARGETSR185,Interrupt Processor Targets Register 185" rgroup.long 0xAE8++0x03 line.long 0x00 "GICD_ITARGETSR186,Interrupt Processor Targets Register 186" rgroup.long 0xAEC++0x03 line.long 0x00 "GICD_ITARGETSR187,Interrupt Processor Targets Register 187" rgroup.long 0xAF0++0x03 line.long 0x00 "GICD_ITARGETSR188,Interrupt Processor Targets Register 188" rgroup.long 0xAF4++0x03 line.long 0x00 "GICD_ITARGETSR189,Interrupt Processor Targets Register 189" rgroup.long 0xAF8++0x03 line.long 0x00 "GICD_ITARGETSR190,Interrupt Processor Targets Register 190" rgroup.long 0xAFC++0x03 line.long 0x00 "GICD_ITARGETSR191,Interrupt Processor Targets Register 191" rgroup.long 0xB00++0x03 line.long 0x00 "GICD_ITARGETSR192,Interrupt Processor Targets Register 192" rgroup.long 0xB04++0x03 line.long 0x00 "GICD_ITARGETSR193,Interrupt Processor Targets Register 193" rgroup.long 0xB08++0x03 line.long 0x00 "GICD_ITARGETSR194,Interrupt Processor Targets Register 194" rgroup.long 0xB0C++0x03 line.long 0x00 "GICD_ITARGETSR195,Interrupt Processor Targets Register 195" rgroup.long 0xB10++0x03 line.long 0x00 "GICD_ITARGETSR196,Interrupt Processor Targets Register 196" rgroup.long 0xB14++0x03 line.long 0x00 "GICD_ITARGETSR197,Interrupt Processor Targets Register 197" rgroup.long 0xB18++0x03 line.long 0x00 "GICD_ITARGETSR198,Interrupt Processor Targets Register 198" rgroup.long 0xB1C++0x03 line.long 0x00 "GICD_ITARGETSR199,Interrupt Processor Targets Register 199" rgroup.long 0xB20++0x03 line.long 0x00 "GICD_ITARGETSR200,Interrupt Processor Targets Register 200" rgroup.long 0xB24++0x03 line.long 0x00 "GICD_ITARGETSR201,Interrupt Processor Targets Register 201" rgroup.long 0xB28++0x03 line.long 0x00 "GICD_ITARGETSR202,Interrupt Processor Targets Register 202" rgroup.long 0xB2C++0x03 line.long 0x00 "GICD_ITARGETSR203,Interrupt Processor Targets Register 203" rgroup.long 0xB30++0x03 line.long 0x00 "GICD_ITARGETSR204,Interrupt Processor Targets Register 204" rgroup.long 0xB34++0x03 line.long 0x00 "GICD_ITARGETSR205,Interrupt Processor Targets Register 205" rgroup.long 0xB38++0x03 line.long 0x00 "GICD_ITARGETSR206,Interrupt Processor Targets Register 206" rgroup.long 0xB3C++0x03 line.long 0x00 "GICD_ITARGETSR207,Interrupt Processor Targets Register 207" rgroup.long 0xB40++0x03 line.long 0x00 "GICD_ITARGETSR208,Interrupt Processor Targets Register 208" rgroup.long 0xB44++0x03 line.long 0x00 "GICD_ITARGETSR209,Interrupt Processor Targets Register 209" rgroup.long 0xB48++0x03 line.long 0x00 "GICD_ITARGETSR210,Interrupt Processor Targets Register 210" rgroup.long 0xB4C++0x03 line.long 0x00 "GICD_ITARGETSR211,Interrupt Processor Targets Register 211" rgroup.long 0xB50++0x03 line.long 0x00 "GICD_ITARGETSR212,Interrupt Processor Targets Register 212" rgroup.long 0xB54++0x03 line.long 0x00 "GICD_ITARGETSR213,Interrupt Processor Targets Register 213" rgroup.long 0xB58++0x03 line.long 0x00 "GICD_ITARGETSR214,Interrupt Processor Targets Register 214" rgroup.long 0xB5C++0x03 line.long 0x00 "GICD_ITARGETSR215,Interrupt Processor Targets Register 215" rgroup.long 0xB60++0x03 line.long 0x00 "GICD_ITARGETSR216,Interrupt Processor Targets Register 216" rgroup.long 0xB64++0x03 line.long 0x00 "GICD_ITARGETSR217,Interrupt Processor Targets Register 217" rgroup.long 0xB68++0x03 line.long 0x00 "GICD_ITARGETSR218,Interrupt Processor Targets Register 218" rgroup.long 0xB6C++0x03 line.long 0x00 "GICD_ITARGETSR219,Interrupt Processor Targets Register 219" rgroup.long 0xB70++0x03 line.long 0x00 "GICD_ITARGETSR220,Interrupt Processor Targets Register 220" rgroup.long 0xB74++0x03 line.long 0x00 "GICD_ITARGETSR221,Interrupt Processor Targets Register 221" rgroup.long 0xB78++0x03 line.long 0x00 "GICD_ITARGETSR222,Interrupt Processor Targets Register 222" rgroup.long 0xB7C++0x03 line.long 0x00 "GICD_ITARGETSR223,Interrupt Processor Targets Register 223" rgroup.long 0xB80++0x03 line.long 0x00 "GICD_ITARGETSR224,Interrupt Processor Targets Register 224" rgroup.long 0xB84++0x03 line.long 0x00 "GICD_ITARGETSR225,Interrupt Processor Targets Register 225" rgroup.long 0xB88++0x03 line.long 0x00 "GICD_ITARGETSR226,Interrupt Processor Targets Register 226" rgroup.long 0xB8C++0x03 line.long 0x00 "GICD_ITARGETSR227,Interrupt Processor Targets Register 227" rgroup.long 0xB90++0x03 line.long 0x00 "GICD_ITARGETSR228,Interrupt Processor Targets Register 228" rgroup.long 0xB94++0x03 line.long 0x00 "GICD_ITARGETSR229,Interrupt Processor Targets Register 229" rgroup.long 0xB98++0x03 line.long 0x00 "GICD_ITARGETSR230,Interrupt Processor Targets Register 230" rgroup.long 0xB9C++0x03 line.long 0x00 "GICD_ITARGETSR231,Interrupt Processor Targets Register 231" rgroup.long 0xBA0++0x03 line.long 0x00 "GICD_ITARGETSR232,Interrupt Processor Targets Register 232" rgroup.long 0xBA4++0x03 line.long 0x00 "GICD_ITARGETSR233,Interrupt Processor Targets Register 233" rgroup.long 0xBA8++0x03 line.long 0x00 "GICD_ITARGETSR234,Interrupt Processor Targets Register 234" rgroup.long 0xBAC++0x03 line.long 0x00 "GICD_ITARGETSR235,Interrupt Processor Targets Register 235" rgroup.long 0xBB0++0x03 line.long 0x00 "GICD_ITARGETSR236,Interrupt Processor Targets Register 236" rgroup.long 0xBB4++0x03 line.long 0x00 "GICD_ITARGETSR237,Interrupt Processor Targets Register 237" rgroup.long 0xBB8++0x03 line.long 0x00 "GICD_ITARGETSR238,Interrupt Processor Targets Register 238" rgroup.long 0xBBC++0x03 line.long 0x00 "GICD_ITARGETSR239,Interrupt Processor Targets Register 239" rgroup.long 0xBC0++0x03 line.long 0x00 "GICD_ITARGETSR240,Interrupt Processor Targets Register 240" rgroup.long 0xBC4++0x03 line.long 0x00 "GICD_ITARGETSR241,Interrupt Processor Targets Register 241" rgroup.long 0xBC8++0x03 line.long 0x00 "GICD_ITARGETSR242,Interrupt Processor Targets Register 242" rgroup.long 0xBCC++0x03 line.long 0x00 "GICD_ITARGETSR243,Interrupt Processor Targets Register 243" rgroup.long 0xBD0++0x03 line.long 0x00 "GICD_ITARGETSR244,Interrupt Processor Targets Register 244" rgroup.long 0xBD4++0x03 line.long 0x00 "GICD_ITARGETSR245,Interrupt Processor Targets Register 245" rgroup.long 0xBD8++0x03 line.long 0x00 "GICD_ITARGETSR246,Interrupt Processor Targets Register 246" rgroup.long 0xBDC++0x03 line.long 0x00 "GICD_ITARGETSR247,Interrupt Processor Targets Register 247" rgroup.long 0xBE0++0x03 line.long 0x00 "GICD_ITARGETSR248,Interrupt Processor Targets Register 248" rgroup.long 0xBE4++0x03 line.long 0x00 "GICD_ITARGETSR249,Interrupt Processor Targets Register 249" rgroup.long 0xBE8++0x03 line.long 0x00 "GICD_ITARGETSR250,Interrupt Processor Targets Register 250" rgroup.long 0xBEC++0x03 line.long 0x00 "GICD_ITARGETSR251,Interrupt Processor Targets Register 251" rgroup.long 0xBF0++0x03 line.long 0x00 "GICD_ITARGETSR252,Interrupt Processor Targets Register 252" rgroup.long 0xBF4++0x03 line.long 0x00 "GICD_ITARGETSR253,Interrupt Processor Targets Register 253" rgroup.long 0xBF8++0x03 line.long 0x00 "GICD_ITARGETSR254,Interrupt Processor Targets Register 254" endif tree.end width 14. tree "Configuration Registers" rgroup.long 0xC00++0x03 line.long 0x00 "GICD_ICFGR0,Interrupt Configuration Register" textline " " rgroup.long 0xC04++0x03 line.long 0x00 "GICD_ICFGR1,Interrupt Configuration Register" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0" "Level,Edge" if (((per.l(ad:(per.long(spr:0x31F30)&0xFFFC0000)+0x04))&0x0000001F)>=0x1) group.long 0xC08++0x03 line.long 0x00 "GICD_ICFGR2,Interrupt Configuration Register 2" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0" "Level,Edge" group.long 0xC0C++0x03 line.long 0x00 "GICD_ICFGR3,Interrupt Configuration Register 3" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0" "Level,Edge" else rgroup.long 0xC08++0x03 line.long 0x00 "GICD_ICFGR2,Interrupt Configuration Register 2" rgroup.long 0xC0C++0x03 line.long 0x00 "GICD_ICFGR3,Interrupt Configuration Register 3" endif if (((per.l(ad:(per.long(spr:0x31F30)&0xFFFC0000)+0x04))&0x0000001F)>=0x2) group.long 0xC10++0x03 line.long 0x00 "GICD_ICFGR4,Interrupt Configuration Register 4" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0" "Level,Edge" group.long 0xC14++0x03 line.long 0x00 "GICD_ICFGR5,Interrupt Configuration Register 5" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0" "Level,Edge" else rgroup.long 0xC10++0x03 line.long 0x00 "GICD_ICFGR4,Interrupt Configuration Register 4" rgroup.long 0xC14++0x03 line.long 0x00 "GICD_ICFGR5,Interrupt Configuration Register 5" endif if (((per.l(ad:(per.long(spr:0x31F30)&0xFFFC0000)+0x04))&0x0000001F)>=0x3) group.long 0xC18++0x03 line.long 0x00 "GICD_ICFGR6,Interrupt Configuration Register 6" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0" "Level,Edge" group.long 0xC1C++0x03 line.long 0x00 "GICD_ICFGR7,Interrupt Configuration Register 7" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0" "Level,Edge" else rgroup.long 0xC18++0x03 line.long 0x00 "GICD_ICFGR6,Interrupt Configuration Register 6" rgroup.long 0xC1C++0x03 line.long 0x00 "GICD_ICFGR7,Interrupt Configuration Register 7" endif if (((per.l(ad:(per.long(spr:0x31F30)&0xFFFC0000)+0x04))&0x0000001F)>=0x4) group.long 0xC20++0x03 line.long 0x00 "GICD_ICFGR8,Interrupt Configuration Register 8" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0" "Level,Edge" group.long 0xC24++0x03 line.long 0x00 "GICD_ICFGR9,Interrupt Configuration Register 9" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0" "Level,Edge" else rgroup.long 0xC20++0x03 line.long 0x00 "GICD_ICFGR8,Interrupt Configuration Register 8" rgroup.long 0xC24++0x03 line.long 0x00 "GICD_ICFGR9,Interrupt Configuration Register 9" endif if (((per.l(ad:(per.long(spr:0x31F30)&0xFFFC0000)+0x04))&0x0000001F)>=0x5) group.long 0xC28++0x03 line.long 0x00 "GICD_ICFGR10,Interrupt Configuration Register 10" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0" "Level,Edge" group.long 0xC2C++0x03 line.long 0x00 "GICD_ICFGR11,Interrupt Configuration Register 11" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0" "Level,Edge" else rgroup.long 0xC28++0x03 line.long 0x00 "GICD_ICFGR10,Interrupt Configuration Register 10" rgroup.long 0xC2C++0x03 line.long 0x00 "GICD_ICFGR11,Interrupt Configuration Register 11" endif if (((per.l(ad:(per.long(spr:0x31F30)&0xFFFC0000)+0x04))&0x0000001F)>=0x6) group.long 0xC30++0x03 line.long 0x00 "GICD_ICFGR12,Interrupt Configuration Register 12" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0" "Level,Edge" group.long 0xC34++0x03 line.long 0x00 "GICD_ICFGR13,Interrupt Configuration Register 13" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0" "Level,Edge" else rgroup.long 0xC30++0x03 line.long 0x00 "GICD_ICFGR12,Interrupt Configuration Register 12" rgroup.long 0xC34++0x03 line.long 0x00 "GICD_ICFGR13,Interrupt Configuration Register 13" endif if (((per.l(ad:(per.long(spr:0x31F30)&0xFFFC0000)+0x04))&0x0000001F)>=0x7) group.long 0xC38++0x03 line.long 0x00 "GICD_ICFGR14,Interrupt Configuration Register 14" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0" "Level,Edge" group.long 0xC3C++0x03 line.long 0x00 "GICD_ICFGR15,Interrupt Configuration Register 15" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0" "Level,Edge" else rgroup.long 0xC38++0x03 line.long 0x00 "GICD_ICFGR14,Interrupt Configuration Register 14" rgroup.long 0xC3C++0x03 line.long 0x00 "GICD_ICFGR15,Interrupt Configuration Register 15" endif if (((per.l(ad:(per.long(spr:0x31F30)&0xFFFC0000)+0x04))&0x0000001F)>=0x8) group.long 0xC40++0x03 line.long 0x00 "GICD_ICFGR16,Interrupt Configuration Register 16" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0" "Level,Edge" group.long 0xC44++0x03 line.long 0x00 "GICD_ICFGR17,Interrupt Configuration Register 17" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0" "Level,Edge" else rgroup.long 0xC40++0x03 line.long 0x00 "GICD_ICFGR16,Interrupt Configuration Register 16" rgroup.long 0xC44++0x03 line.long 0x00 "GICD_ICFGR17,Interrupt Configuration Register 17" endif if (((per.l(ad:(per.long(spr:0x31F30)&0xFFFC0000)+0x04))&0x0000001F)>=0x9) group.long 0xC48++0x03 line.long 0x00 "GICD_ICFGR18,Interrupt Configuration Register 18" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0" "Level,Edge" group.long 0xC4C++0x03 line.long 0x00 "GICD_ICFGR19,Interrupt Configuration Register 19" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0" "Level,Edge" else rgroup.long 0xC48++0x03 line.long 0x00 "GICD_ICFGR18,Interrupt Configuration Register 18" rgroup.long 0xC4C++0x03 line.long 0x00 "GICD_ICFGR19,Interrupt Configuration Register 19" endif if (((per.l(ad:(per.long(spr:0x31F30)&0xFFFC0000)+0x04))&0x0000001F)>=0xA) group.long 0xC50++0x03 line.long 0x00 "GICD_ICFGR20,Interrupt Configuration Register 20" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0" "Level,Edge" group.long 0xC54++0x03 line.long 0x00 "GICD_ICFGR21,Interrupt Configuration Register 21" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0" "Level,Edge" else rgroup.long 0xC50++0x03 line.long 0x00 "GICD_ICFGR20,Interrupt Configuration Register 20" rgroup.long 0xC54++0x03 line.long 0x00 "GICD_ICFGR21,Interrupt Configuration Register 21" endif if (((per.l(ad:(per.long(spr:0x31F30)&0xFFFC0000)+0x04))&0x0000001F)>=0xB) group.long 0xC58++0x03 line.long 0x00 "GICD_ICFGR22,Interrupt Configuration Register 22" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0" "Level,Edge" group.long 0xC5C++0x03 line.long 0x00 "GICD_ICFGR23,Interrupt Configuration Register 23" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0" "Level,Edge" else rgroup.long 0xC58++0x03 line.long 0x00 "GICD_ICFGR22,Interrupt Configuration Register 22" rgroup.long 0xC5C++0x03 line.long 0x00 "GICD_ICFGR23,Interrupt Configuration Register 23" endif if (((per.l(ad:(per.long(spr:0x31F30)&0xFFFC0000)+0x04))&0x0000001F)>=0xC) group.long 0xC60++0x03 line.long 0x00 "GICD_ICFGR24,Interrupt Configuration Register 24" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0" "Level,Edge" group.long 0xC64++0x03 line.long 0x00 "GICD_ICFGR25,Interrupt Configuration Register 25" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0" "Level,Edge" else rgroup.long 0xC60++0x03 line.long 0x00 "GICD_ICFGR24,Interrupt Configuration Register 24" rgroup.long 0xC64++0x03 line.long 0x00 "GICD_ICFGR25,Interrupt Configuration Register 25" endif if (((per.l(ad:(per.long(spr:0x31F30)&0xFFFC0000)+0x04))&0x0000001F)>=0xD) group.long 0xC68++0x03 line.long 0x00 "GICD_ICFGR26,Interrupt Configuration Register 26" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0" "Level,Edge" group.long 0xC6C++0x03 line.long 0x00 "GICD_ICFGR27,Interrupt Configuration Register 27" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0" "Level,Edge" else rgroup.long 0xC68++0x03 line.long 0x00 "GICD_ICFGR26,Interrupt Configuration Register 26" rgroup.long 0xC6C++0x03 line.long 0x00 "GICD_ICFGR27,Interrupt Configuration Register 27" endif if (((per.l(ad:(per.long(spr:0x31F30)&0xFFFC0000)+0x04))&0x0000001F)>=0xE) group.long 0xC70++0x03 line.long 0x00 "GICD_ICFGR28,Interrupt Configuration Register 28" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0" "Level,Edge" group.long 0xC74++0x03 line.long 0x00 "GICD_ICFGR29,Interrupt Configuration Register 29" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0" "Level,Edge" else rgroup.long 0xC70++0x03 line.long 0x00 "GICD_ICFGR28,Interrupt Configuration Register 28" rgroup.long 0xC74++0x03 line.long 0x00 "GICD_ICFGR29,Interrupt Configuration Register 29" endif if (((per.l(ad:(per.long(spr:0x31F30)&0xFFFC0000)+0x04))&0x0000001F)>=0xF) group.long 0xC78++0x03 line.long 0x00 "GICD_ICFGR30,Interrupt Configuration Register 30" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0" "Level,Edge" group.long 0xC7C++0x03 line.long 0x00 "GICD_ICFGR31,Interrupt Configuration Register 31" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0" "Level,Edge" else rgroup.long 0xC78++0x03 line.long 0x00 "GICD_ICFGR30,Interrupt Configuration Register 30" rgroup.long 0xC7C++0x03 line.long 0x00 "GICD_ICFGR31,Interrupt Configuration Register 31" endif if (((per.l(ad:(per.long(spr:0x31F30)&0xFFFC0000)+0x04))&0x0000001F)>=0x10) group.long 0xC80++0x03 line.long 0x00 "GICD_ICFGR32,Interrupt Configuration Register 32" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0" "Level,Edge" group.long 0xC84++0x03 line.long 0x00 "GICD_ICFGR33,Interrupt Configuration Register 33" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0" "Level,Edge" else rgroup.long 0xC80++0x03 line.long 0x00 "GICD_ICFGR32,Interrupt Configuration Register 32" rgroup.long 0xC84++0x03 line.long 0x00 "GICD_ICFGR33,Interrupt Configuration Register 33" endif if (((per.l(ad:(per.long(spr:0x31F30)&0xFFFC0000)+0x04))&0x0000001F)>=0x11) group.long 0xC88++0x03 line.long 0x00 "GICD_ICFGR34,Interrupt Configuration Register 34" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0" "Level,Edge" group.long 0xC8C++0x03 line.long 0x00 "GICD_ICFGR35,Interrupt Configuration Register 35" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0" "Level,Edge" else rgroup.long 0xC88++0x03 line.long 0x00 "GICD_ICFGR34,Interrupt Configuration Register 34" rgroup.long 0xC8C++0x03 line.long 0x00 "GICD_ICFGR35,Interrupt Configuration Register 35" endif if (((per.l(ad:(per.long(spr:0x31F30)&0xFFFC0000)+0x04))&0x0000001F)>=0x12) group.long 0xC90++0x03 line.long 0x00 "GICD_ICFGR36,Interrupt Configuration Register 36" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0" "Level,Edge" group.long 0xC94++0x03 line.long 0x00 "GICD_ICFGR37,Interrupt Configuration Register 37" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0" "Level,Edge" else rgroup.long 0xC90++0x03 line.long 0x00 "GICD_ICFGR36,Interrupt Configuration Register 36" rgroup.long 0xC94++0x03 line.long 0x00 "GICD_ICFGR37,Interrupt Configuration Register 37" endif if (((per.l(ad:(per.long(spr:0x31F30)&0xFFFC0000)+0x04))&0x0000001F)>=0x13) group.long 0xC98++0x03 line.long 0x00 "GICD_ICFGR38,Interrupt Configuration Register 38" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0" "Level,Edge" group.long 0xC9C++0x03 line.long 0x00 "GICD_ICFGR39,Interrupt Configuration Register 39" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0" "Level,Edge" else rgroup.long 0xC98++0x03 line.long 0x00 "GICD_ICFGR38,Interrupt Configuration Register 38" rgroup.long 0xC9C++0x03 line.long 0x00 "GICD_ICFGR39,Interrupt Configuration Register 39" endif if (((per.l(ad:(per.long(spr:0x31F30)&0xFFFC0000)+0x04))&0x0000001F)>=0x14) group.long 0xCA0++0x03 line.long 0x00 "GICD_ICFGR40,Interrupt Configuration Register 40" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0" "Level,Edge" group.long 0xCA4++0x03 line.long 0x00 "GICD_ICFGR41,Interrupt Configuration Register 41" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0" "Level,Edge" else rgroup.long 0xCA0++0x03 line.long 0x00 "GICD_ICFGR40,Interrupt Configuration Register 40" rgroup.long 0xCA4++0x03 line.long 0x00 "GICD_ICFGR41,Interrupt Configuration Register 41" endif if (((per.l(ad:(per.long(spr:0x31F30)&0xFFFC0000)+0x04))&0x0000001F)>=0x15) group.long 0xCA8++0x03 line.long 0x00 "GICD_ICFGR42,Interrupt Configuration Register 42" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0" "Level,Edge" group.long 0xCAC++0x03 line.long 0x00 "GICD_ICFGR43,Interrupt Configuration Register 43" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0" "Level,Edge" else rgroup.long 0xCA8++0x03 line.long 0x00 "GICD_ICFGR42,Interrupt Configuration Register 42" rgroup.long 0xCAC++0x03 line.long 0x00 "GICD_ICFGR43,Interrupt Configuration Register 43" endif if (((per.l(ad:(per.long(spr:0x31F30)&0xFFFC0000)+0x04))&0x0000001F)>=0x16) group.long 0xCB0++0x03 line.long 0x00 "GICD_ICFGR44,Interrupt Configuration Register 44" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0" "Level,Edge" group.long 0xCB4++0x03 line.long 0x00 "GICD_ICFGR45,Interrupt Configuration Register 45" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0" "Level,Edge" else rgroup.long 0xCB0++0x03 line.long 0x00 "GICD_ICFGR44,Interrupt Configuration Register 44" rgroup.long 0xCB4++0x03 line.long 0x00 "GICD_ICFGR45,Interrupt Configuration Register 45" endif if (((per.l(ad:(per.long(spr:0x31F30)&0xFFFC0000)+0x04))&0x0000001F)>=0x17) group.long 0xCB8++0x03 line.long 0x00 "GICD_ICFGR46,Interrupt Configuration Register 46" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0" "Level,Edge" group.long 0xCBC++0x03 line.long 0x00 "GICD_ICFGR47,Interrupt Configuration Register 47" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0" "Level,Edge" else rgroup.long 0xCB8++0x03 line.long 0x00 "GICD_ICFGR46,Interrupt Configuration Register 46" rgroup.long 0xCBC++0x03 line.long 0x00 "GICD_ICFGR47,Interrupt Configuration Register 47" endif if (((per.l(ad:(per.long(spr:0x31F30)&0xFFFC0000)+0x04))&0x0000001F)>=0x18) group.long 0xCC0++0x03 line.long 0x00 "GICD_ICFGR48,Interrupt Configuration Register 48" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0" "Level,Edge" group.long 0xCC4++0x03 line.long 0x00 "GICD_ICFGR49,Interrupt Configuration Register 49" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0" "Level,Edge" else rgroup.long 0xCC0++0x03 line.long 0x00 "GICD_ICFGR48,Interrupt Configuration Register 48" rgroup.long 0xCC4++0x03 line.long 0x00 "GICD_ICFGR49,Interrupt Configuration Register 49" endif if (((per.l(ad:(per.long(spr:0x31F30)&0xFFFC0000)+0x04))&0x0000001F)>=0x19) group.long 0xCC8++0x03 line.long 0x00 "GICD_ICFGR50,Interrupt Configuration Register 50" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0" "Level,Edge" group.long 0xCCC++0x03 line.long 0x00 "GICD_ICFGR51,Interrupt Configuration Register 51" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0" "Level,Edge" else rgroup.long 0xCC8++0x03 line.long 0x00 "GICD_ICFGR50,Interrupt Configuration Register 50" rgroup.long 0xCCC++0x03 line.long 0x00 "GICD_ICFGR51,Interrupt Configuration Register 51" endif if (((per.l(ad:(per.long(spr:0x31F30)&0xFFFC0000)+0x04))&0x0000001F)>=0x1A) group.long 0xCD0++0x03 line.long 0x00 "GICD_ICFGR52,Interrupt Configuration Register 52" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0" "Level,Edge" group.long 0xCD4++0x03 line.long 0x00 "GICD_ICFGR53,Interrupt Configuration Register 53" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0" "Level,Edge" else rgroup.long 0xCD0++0x03 line.long 0x00 "GICD_ICFGR52,Interrupt Configuration Register 52" rgroup.long 0xCD4++0x03 line.long 0x00 "GICD_ICFGR53,Interrupt Configuration Register 53" endif if (((per.l(ad:(per.long(spr:0x31F30)&0xFFFC0000)+0x04))&0x0000001F)>=0x1B) group.long 0xCD8++0x03 line.long 0x00 "GICD_ICFGR54,Interrupt Configuration Register 54" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0" "Level,Edge" group.long 0xCDC++0x03 line.long 0x00 "GICD_ICFGR55,Interrupt Configuration Register 55" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0" "Level,Edge" else rgroup.long 0xCD8++0x03 line.long 0x00 "GICD_ICFGR54,Interrupt Configuration Register 54" rgroup.long 0xCDC++0x03 line.long 0x00 "GICD_ICFGR55,Interrupt Configuration Register 55" endif if (((per.l(ad:(per.long(spr:0x31F30)&0xFFFC0000)+0x04))&0x0000001F)>=0x1C) group.long 0xCE0++0x03 line.long 0x00 "GICD_ICFGR56,Interrupt Configuration Register 56" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0" "Level,Edge" group.long 0xCE4++0x03 line.long 0x00 "GICD_ICFGR57,Interrupt Configuration Register 57" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0" "Level,Edge" else rgroup.long 0xCE0++0x03 line.long 0x00 "GICD_ICFGR56,Interrupt Configuration Register 56" rgroup.long 0xCE4++0x03 line.long 0x00 "GICD_ICFGR57,Interrupt Configuration Register 57" endif if (((per.l(ad:(per.long(spr:0x31F30)&0xFFFC0000)+0x04))&0x0000001F)>=0x1D) group.long 0xCE8++0x03 line.long 0x00 "GICD_ICFGR58,Interrupt Configuration Register 58" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0" "Level,Edge" group.long 0xCEC++0x03 line.long 0x00 "GICD_ICFGR59,Interrupt Configuration Register 59" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0" "Level,Edge" else rgroup.long 0xCE8++0x03 line.long 0x00 "GICD_ICFGR58,Interrupt Configuration Register 58" rgroup.long 0xCEC++0x03 line.long 0x00 "GICD_ICFGR59,Interrupt Configuration Register 59" endif if (((per.l(ad:(per.long(spr:0x31F30)&0xFFFC0000)+0x04))&0x0000001F)>=0x1E) group.long 0xCF0++0x03 line.long 0x00 "GICD_ICFGR60,Interrupt Configuration Register 60" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0" "Level,Edge" group.long 0xCF4++0x03 line.long 0x00 "GICD_ICFGR61,Interrupt Configuration Register 61" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0" "Level,Edge" else rgroup.long 0xCF0++0x03 line.long 0x00 "GICD_ICFGR60,Interrupt Configuration Register 60" rgroup.long 0xCF4++0x03 line.long 0x00 "GICD_ICFGR61,Interrupt Configuration Register 61" endif if (((per.l(ad:(per.long(spr:0x31F30)&0xFFFC0000)+0x04))&0x0000001F)>=0x1F) group.long 0xCF8++0x03 line.long 0x00 "GICD_ICFGR62,Interrupt Configuration Register 62" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0" "Level,Edge" group.long 0xCFC++0x03 line.long 0x00 "GICD_ICFGR63,Interrupt Configuration Register 63" bitfld.long 0x00 31. " ICF15 ,Interrupt Configuration 15" "Level,Edge" bitfld.long 0x00 29. " ICF14 ,Interrupt Configuration 14" "Level,Edge" bitfld.long 0x00 27. " ICF13 ,Interrupt Configuration 13" "Level,Edge" textline " " bitfld.long 0x00 25. " ICF12 ,Interrupt Configuration 12" "Level,Edge" bitfld.long 0x00 23. " ICF11 ,Interrupt Configuration 11" "Level,Edge" bitfld.long 0x00 21. " ICF10 ,Interrupt Configuration 10" "Level,Edge" textline " " bitfld.long 0x00 19. " ICF9 ,Interrupt Configuration 9" "Level,Edge" bitfld.long 0x00 17. " ICF8 ,Interrupt Configuration 8" "Level,Edge" bitfld.long 0x00 15. " ICF7 ,Interrupt Configuration 7" "Level,Edge" textline " " bitfld.long 0x00 13. " ICF6 ,Interrupt Configuration 6" "Level,Edge" bitfld.long 0x00 11. " ICF5 ,Interrupt Configuration 5" "Level,Edge" bitfld.long 0x00 9. " ICF4 ,Interrupt Configuration 4" "Level,Edge" textline " " bitfld.long 0x00 7. " ICF3 ,Interrupt Configuration 3" "Level,Edge" bitfld.long 0x00 5. " ICF2 ,Interrupt Configuration 2" "Level,Edge" bitfld.long 0x00 3. " ICF1 ,Interrupt Configuration 1" "Level,Edge" textline " " bitfld.long 0x00 1. " ICF0 ,Interrupt Configuration 0" "Level,Edge" else rgroup.long 0xCF8++0x03 line.long 0x00 "GICD_ICFGR62,Interrupt Configuration Register 62" rgroup.long 0xCFC++0x03 line.long 0x00 "GICD_ICFGR63,Interrupt Configuration Register 63" endif tree.end width 12. tree "Peripheral Interrupt Status Registers" rgroup.long 0x0D00++0x03 line.long 0x00 "GICD_PPISR,Private Peripheral Interrupt Status Register" bitfld.long 0x00 15. " PPI3S ,nIRQ pin status" "No interrupt,Interrupt" bitfld.long 0x00 14. " PPI2S ,Non-secure Physical Timer event status" "No interrupt,Interrupt" textline " " bitfld.long 0x00 13. " PPI1S ,Secure Physical Timer event status" "No interrupt,Interrupt" bitfld.long 0x00 12. " PPI0S ,nFIQ pin status" "No interrupt,Interrupt" textline " " bitfld.long 0x00 11. " PPI4S ,Virtual Timer event status" "No interrupt,Interrupt" bitfld.long 0x00 10. " PPI5S ,Hypervisor Timer event status" "No interrupt,Interrupt" textline " " bitfld.long 0x00 9. " PPI6S ,Virtual Maintenance Status" "No interrupt,Interrupt" textline " " width 22. if (((per.l(ad:(per.long(spr:0x31F30)&0xFFFC0000)+0x04))&0x0000001F)>=0x01) rgroup.long 0x0D04++0x03 line.long 0x0 "GICD_SPISR0,Shared Peripheral Interrupt Status Register 0" bitfld.long 0x00 31. " IRQS31 ,IRQS Status Bit 31" "Low,High" bitfld.long 0x00 30. " IRQS30 ,IRQS Status Bit 30" "Low,High" bitfld.long 0x00 29. " IRQS29 ,IRQS Status Bit 29" "Low,High" textline " " bitfld.long 0x00 28. " IRQS28 ,IRQS Status Bit 28" "Low,High" bitfld.long 0x00 27. " IRQS27 ,IRQS Status Bit 27" "Low,High" bitfld.long 0x00 26. " IRQS26 ,IRQS Status Bit 26" "Low,High" textline " " bitfld.long 0x00 25. " IRQS25 ,IRQS Status Bit 25" "Low,High" bitfld.long 0x00 24. " IRQS24 ,IRQS Status Bit 24" "Low,High" bitfld.long 0x00 23. " IRQS23 ,IRQS Status Bit 23" "Low,High" textline " " bitfld.long 0x00 22. " IRQS22 ,IRQS Status Bit 22" "Low,High" bitfld.long 0x00 21. " IRQS21 ,IRQS Status Bit 21" "Low,High" bitfld.long 0x00 20. " IRQS20 ,IRQS Status Bit 20" "Low,High" textline " " bitfld.long 0x00 19. " IRQS19 ,IRQS Status Bit 19" "Low,High" bitfld.long 0x00 18. " IRQS18 ,IRQS Status Bit 18" "Low,High" bitfld.long 0x00 17. " IRQS17 ,IRQS Status Bit 17" "Low,High" textline " " bitfld.long 0x00 16. " IRQS16 ,IRQS Status Bit 16" "Low,High" bitfld.long 0x00 15. " IRQS15 ,IRQS Status Bit 15" "Low,High" bitfld.long 0x00 14. " IRQS14 ,IRQS Status Bit 14" "Low,High" textline " " bitfld.long 0x00 13. " IRQS13 ,IRQS Status Bit 13" "Low,High" bitfld.long 0x00 12. " IRQS12 ,IRQS Status Bit 12" "Low,High" bitfld.long 0x00 11. " IRQS11 ,IRQS Status Bit 11" "Low,High" textline " " bitfld.long 0x00 10. " IRQS10 ,IRQS Status Bit 10" "Low,High" bitfld.long 0x00 9. " IRQS9 ,IRQS Status Bit 9" "Low,High" bitfld.long 0x00 8. " IRQS8 ,IRQS Status Bit 8" "Low,High" textline " " bitfld.long 0x00 7. " IRQS7 ,IRQS Status Bit 7" "Low,High" bitfld.long 0x00 6. " IRQS6 ,IRQS Status Bit 6" "Low,High" bitfld.long 0x00 5. " IRQS5 ,IRQS Status Bit 5" "Low,High" textline " " bitfld.long 0x00 4. " IRQS4 ,IRQS Status Bit 4" "Low,High" bitfld.long 0x00 3. " IRQS3 ,IRQS Status Bit 3" "Low,High" bitfld.long 0x00 2. " IRQS2 ,IRQS Status Bit 2" "Low,High" textline " " bitfld.long 0x00 1. " IRQS1 ,IRQS Status Bit 1" "Low,High" bitfld.long 0x00 0. " IRQS0 ,IRQS Status Bit 0" "Low,High" else rgroup.long 0x0D04++0x03 line.long 0x0 "GICD_SPISR0,Shared Peripheral Interrupt Status Register 1" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(ad:(per.long(spr:0x31F30)&0xFFFC0000)+0x04))&0x0000001F)>=0x02) rgroup.long 0x0D08++0x03 line.long 0x0 "GICD_SPISR1,Shared Peripheral Interrupt Status Register 1" bitfld.long 0x00 31. " IRQS63 ,IRQS Status Bit 63" "Low,High" bitfld.long 0x00 30. " IRQS62 ,IRQS Status Bit 62" "Low,High" bitfld.long 0x00 29. " IRQS61 ,IRQS Status Bit 61" "Low,High" textline " " bitfld.long 0x00 28. " IRQS60 ,IRQS Status Bit 60" "Low,High" bitfld.long 0x00 27. " IRQS59 ,IRQS Status Bit 59" "Low,High" bitfld.long 0x00 26. " IRQS58 ,IRQS Status Bit 58" "Low,High" textline " " bitfld.long 0x00 25. " IRQS57 ,IRQS Status Bit 57" "Low,High" bitfld.long 0x00 24. " IRQS56 ,IRQS Status Bit 56" "Low,High" bitfld.long 0x00 23. " IRQS55 ,IRQS Status Bit 55" "Low,High" textline " " bitfld.long 0x00 22. " IRQS54 ,IRQS Status Bit 54" "Low,High" bitfld.long 0x00 21. " IRQS53 ,IRQS Status Bit 53" "Low,High" bitfld.long 0x00 20. " IRQS52 ,IRQS Status Bit 52" "Low,High" textline " " bitfld.long 0x00 19. " IRQS51 ,IRQS Status Bit 51" "Low,High" bitfld.long 0x00 18. " IRQS50 ,IRQS Status Bit 50" "Low,High" bitfld.long 0x00 17. " IRQS49 ,IRQS Status Bit 49" "Low,High" textline " " bitfld.long 0x00 16. " IRQS48 ,IRQS Status Bit 48" "Low,High" bitfld.long 0x00 15. " IRQS47 ,IRQS Status Bit 47" "Low,High" bitfld.long 0x00 14. " IRQS46 ,IRQS Status Bit 46" "Low,High" textline " " bitfld.long 0x00 13. " IRQS45 ,IRQS Status Bit 45" "Low,High" bitfld.long 0x00 12. " IRQS44 ,IRQS Status Bit 44" "Low,High" bitfld.long 0x00 11. " IRQS43 ,IRQS Status Bit 43" "Low,High" textline " " bitfld.long 0x00 10. " IRQS42 ,IRQS Status Bit 42" "Low,High" bitfld.long 0x00 9. " IRQS41 ,IRQS Status Bit 41" "Low,High" bitfld.long 0x00 8. " IRQS40 ,IRQS Status Bit 40" "Low,High" textline " " bitfld.long 0x00 7. " IRQS39 ,IRQS Status Bit 39" "Low,High" bitfld.long 0x00 6. " IRQS38 ,IRQS Status Bit 38" "Low,High" bitfld.long 0x00 5. " IRQS37 ,IRQS Status Bit 37" "Low,High" textline " " bitfld.long 0x00 4. " IRQS36 ,IRQS Status Bit 36" "Low,High" bitfld.long 0x00 3. " IRQS35 ,IRQS Status Bit 35" "Low,High" bitfld.long 0x00 2. " IRQS34 ,IRQS Status Bit 34" "Low,High" textline " " bitfld.long 0x00 1. " IRQS33 ,IRQS Status Bit 33" "Low,High" bitfld.long 0x00 0. " IRQS32 ,IRQS Status Bit 32" "Low,High" else rgroup.long 0x0D08++0x03 line.long 0x0 "GICD_SPISR1,Shared Peripheral Interrupt Status Register 1" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(ad:(per.long(spr:0x31F30)&0xFFFC0000)+0x04))&0x0000001F)>=0x03) rgroup.long 0x0D0C++0x03 line.long 0x0 "GICD_SPISR2,Shared Peripheral Interrupt Status Register 2" bitfld.long 0x00 31. " IRQS95 ,IRQS Status Bit 95" "Low,High" bitfld.long 0x00 30. " IRQS94 ,IRQS Status Bit 94" "Low,High" bitfld.long 0x00 29. " IRQS93 ,IRQS Status Bit 93" "Low,High" textline " " bitfld.long 0x00 28. " IRQS92 ,IRQS Status Bit 92" "Low,High" bitfld.long 0x00 27. " IRQS91 ,IRQS Status Bit 91" "Low,High" bitfld.long 0x00 26. " IRQS90 ,IRQS Status Bit 90" "Low,High" textline " " bitfld.long 0x00 25. " IRQS89 ,IRQS Status Bit 89" "Low,High" bitfld.long 0x00 24. " IRQS88 ,IRQS Status Bit 88" "Low,High" bitfld.long 0x00 23. " IRQS87 ,IRQS Status Bit 87" "Low,High" textline " " bitfld.long 0x00 22. " IRQS86 ,IRQS Status Bit 86" "Low,High" bitfld.long 0x00 21. " IRQS85 ,IRQS Status Bit 85" "Low,High" bitfld.long 0x00 20. " IRQS84 ,IRQS Status Bit 84" "Low,High" textline " " bitfld.long 0x00 19. " IRQS83 ,IRQS Status Bit 83" "Low,High" bitfld.long 0x00 18. " IRQS82 ,IRQS Status Bit 82" "Low,High" bitfld.long 0x00 17. " IRQS81 ,IRQS Status Bit 81" "Low,High" textline " " bitfld.long 0x00 16. " IRQS80 ,IRQS Status Bit 80" "Low,High" bitfld.long 0x00 15. " IRQS79 ,IRQS Status Bit 79" "Low,High" bitfld.long 0x00 14. " IRQS78 ,IRQS Status Bit 78" "Low,High" textline " " bitfld.long 0x00 13. " IRQS77 ,IRQS Status Bit 77" "Low,High" bitfld.long 0x00 12. " IRQS76 ,IRQS Status Bit 76" "Low,High" bitfld.long 0x00 11. " IRQS75 ,IRQS Status Bit 75" "Low,High" textline " " bitfld.long 0x00 10. " IRQS74 ,IRQS Status Bit 74" "Low,High" bitfld.long 0x00 9. " IRQS73 ,IRQS Status Bit 73" "Low,High" bitfld.long 0x00 8. " IRQS72 ,IRQS Status Bit 72" "Low,High" textline " " bitfld.long 0x00 7. " IRQS71 ,IRQS Status Bit 71" "Low,High" bitfld.long 0x00 6. " IRQS70 ,IRQS Status Bit 70" "Low,High" bitfld.long 0x00 5. " IRQS69 ,IRQS Status Bit 69" "Low,High" textline " " bitfld.long 0x00 4. " IRQS68 ,IRQS Status Bit 68" "Low,High" bitfld.long 0x00 3. " IRQS67 ,IRQS Status Bit 67" "Low,High" bitfld.long 0x00 2. " IRQS66 ,IRQS Status Bit 66" "Low,High" textline " " bitfld.long 0x00 1. " IRQS65 ,IRQS Status Bit 65" "Low,High" bitfld.long 0x00 0. " IRQS64 ,IRQS Status Bit 64" "Low,High" else rgroup.long 0x0D0C++0x03 line.long 0x0 "GICD_SPISR2,Shared Peripheral Interrupt Status Register 2" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(ad:(per.long(spr:0x31F30)&0xFFFC0000)+0x04))&0x0000001F)>=0x04) rgroup.long 0x0D10++0x03 line.long 0x0 "GICD_SPISR3,Shared Peripheral Interrupt Status Register 3" bitfld.long 0x00 31. " IRQS127 ,IRQS Status Bit 127" "Low,High" bitfld.long 0x00 30. " IRQS126 ,IRQS Status Bit 126" "Low,High" bitfld.long 0x00 29. " IRQS125 ,IRQS Status Bit 125" "Low,High" textline " " bitfld.long 0x00 28. " IRQS124 ,IRQS Status Bit 124" "Low,High" bitfld.long 0x00 27. " IRQS123 ,IRQS Status Bit 123" "Low,High" bitfld.long 0x00 26. " IRQS122 ,IRQS Status Bit 122" "Low,High" textline " " bitfld.long 0x00 25. " IRQS121 ,IRQS Status Bit 121" "Low,High" bitfld.long 0x00 24. " IRQS120 ,IRQS Status Bit 120" "Low,High" bitfld.long 0x00 23. " IRQS119 ,IRQS Status Bit 119" "Low,High" textline " " bitfld.long 0x00 22. " IRQS118 ,IRQS Status Bit 118" "Low,High" bitfld.long 0x00 21. " IRQS117 ,IRQS Status Bit 117" "Low,High" bitfld.long 0x00 20. " IRQS116 ,IRQS Status Bit 116" "Low,High" textline " " bitfld.long 0x00 19. " IRQS115 ,IRQS Status Bit 115" "Low,High" bitfld.long 0x00 18. " IRQS114 ,IRQS Status Bit 114" "Low,High" bitfld.long 0x00 17. " IRQS113 ,IRQS Status Bit 113" "Low,High" textline " " bitfld.long 0x00 16. " IRQS112 ,IRQS Status Bit 112" "Low,High" bitfld.long 0x00 15. " IRQS111 ,IRQS Status Bit 111" "Low,High" bitfld.long 0x00 14. " IRQS110 ,IRQS Status Bit 110" "Low,High" textline " " bitfld.long 0x00 13. " IRQS109 ,IRQS Status Bit 109" "Low,High" bitfld.long 0x00 12. " IRQS108 ,IRQS Status Bit 108" "Low,High" bitfld.long 0x00 11. " IRQS107 ,IRQS Status Bit 107" "Low,High" textline " " bitfld.long 0x00 10. " IRQS106 ,IRQS Status Bit 106" "Low,High" bitfld.long 0x00 9. " IRQS105 ,IRQS Status Bit 105" "Low,High" bitfld.long 0x00 8. " IRQS104 ,IRQS Status Bit 104" "Low,High" textline " " bitfld.long 0x00 7. " IRQS103 ,IRQS Status Bit 103" "Low,High" bitfld.long 0x00 6. " IRQS102 ,IRQS Status Bit 102" "Low,High" bitfld.long 0x00 5. " IRQS101 ,IRQS Status Bit 101" "Low,High" textline " " bitfld.long 0x00 4. " IRQS100 ,IRQS Status Bit 100" "Low,High" bitfld.long 0x00 3. " IRQS99 ,IRQS Status Bit 99" "Low,High" bitfld.long 0x00 2. " IRQS98 ,IRQS Status Bit 98" "Low,High" textline " " bitfld.long 0x00 1. " IRQS97 ,IRQS Status Bit 97" "Low,High" bitfld.long 0x00 0. " IRQS96 ,IRQS Status Bit 96" "Low,High" else rgroup.long 0x0D10++0x03 line.long 0x0 "GICD_SPISR3,Shared Peripheral Interrupt Status Register 3" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(ad:(per.long(spr:0x31F30)&0xFFFC0000)+0x04))&0x0000001F)>=0x05) rgroup.long 0x0D14++0x03 line.long 0x0 "GICD_SPISR4,Shared Peripheral Interrupt Status Register 4" bitfld.long 0x00 31. " IRQS159 ,IRQS Status Bit 159" "Low,High" bitfld.long 0x00 30. " IRQS158 ,IRQS Status Bit 158" "Low,High" bitfld.long 0x00 29. " IRQS157 ,IRQS Status Bit 157" "Low,High" textline " " bitfld.long 0x00 28. " IRQS156 ,IRQS Status Bit 156" "Low,High" bitfld.long 0x00 27. " IRQS155 ,IRQS Status Bit 155" "Low,High" bitfld.long 0x00 26. " IRQS154 ,IRQS Status Bit 154" "Low,High" textline " " bitfld.long 0x00 25. " IRQS153 ,IRQS Status Bit 153" "Low,High" bitfld.long 0x00 24. " IRQS152 ,IRQS Status Bit 152" "Low,High" bitfld.long 0x00 23. " IRQS151 ,IRQS Status Bit 151" "Low,High" textline " " bitfld.long 0x00 22. " IRQS150 ,IRQS Status Bit 150" "Low,High" bitfld.long 0x00 21. " IRQS149 ,IRQS Status Bit 149" "Low,High" bitfld.long 0x00 20. " IRQS148 ,IRQS Status Bit 148" "Low,High" textline " " bitfld.long 0x00 19. " IRQS147 ,IRQS Status Bit 147" "Low,High" bitfld.long 0x00 18. " IRQS146 ,IRQS Status Bit 146" "Low,High" bitfld.long 0x00 17. " IRQS145 ,IRQS Status Bit 145" "Low,High" textline " " bitfld.long 0x00 16. " IRQS144 ,IRQS Status Bit 144" "Low,High" bitfld.long 0x00 15. " IRQS143 ,IRQS Status Bit 143" "Low,High" bitfld.long 0x00 14. " IRQS142 ,IRQS Status Bit 142" "Low,High" textline " " bitfld.long 0x00 13. " IRQS141 ,IRQS Status Bit 141" "Low,High" bitfld.long 0x00 12. " IRQS140 ,IRQS Status Bit 140" "Low,High" bitfld.long 0x00 11. " IRQS139 ,IRQS Status Bit 139" "Low,High" textline " " bitfld.long 0x00 10. " IRQS138 ,IRQS Status Bit 138" "Low,High" bitfld.long 0x00 9. " IRQS137 ,IRQS Status Bit 137" "Low,High" bitfld.long 0x00 8. " IRQS136 ,IRQS Status Bit 136" "Low,High" textline " " bitfld.long 0x00 7. " IRQS135 ,IRQS Status Bit 135" "Low,High" bitfld.long 0x00 6. " IRQS134 ,IRQS Status Bit 134" "Low,High" bitfld.long 0x00 5. " IRQS133 ,IRQS Status Bit 133" "Low,High" textline " " bitfld.long 0x00 4. " IRQS132 ,IRQS Status Bit 132" "Low,High" bitfld.long 0x00 3. " IRQS131 ,IRQS Status Bit 131" "Low,High" bitfld.long 0x00 2. " IRQS130 ,IRQS Status Bit 130" "Low,High" textline " " bitfld.long 0x00 1. " IRQS129 ,IRQS Status Bit 129" "Low,High" bitfld.long 0x00 0. " IRQS128 ,IRQS Status Bit 128" "Low,High" else rgroup.long 0x0D14++0x03 line.long 0x0 "GICD_SPISR4,Shared Peripheral Interrupt Status Register 4" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(ad:(per.long(spr:0x31F30)&0xFFFC0000)+0x04))&0x0000001F)>=0x06) rgroup.long 0x0D18++0x03 line.long 0x0 "GICD_SPISR5,Shared Peripheral Interrupt Status Register 5" bitfld.long 0x00 31. " IRQS191 ,IRQS Status Bit 191" "Low,High" bitfld.long 0x00 30. " IRQS190 ,IRQS Status Bit 190" "Low,High" bitfld.long 0x00 29. " IRQS189 ,IRQS Status Bit 189" "Low,High" textline " " bitfld.long 0x00 28. " IRQS188 ,IRQS Status Bit 188" "Low,High" bitfld.long 0x00 27. " IRQS187 ,IRQS Status Bit 187" "Low,High" bitfld.long 0x00 26. " IRQS186 ,IRQS Status Bit 186" "Low,High" textline " " bitfld.long 0x00 25. " IRQS185 ,IRQS Status Bit 185" "Low,High" bitfld.long 0x00 24. " IRQS184 ,IRQS Status Bit 184" "Low,High" bitfld.long 0x00 23. " IRQS183 ,IRQS Status Bit 183" "Low,High" textline " " bitfld.long 0x00 22. " IRQS182 ,IRQS Status Bit 182" "Low,High" bitfld.long 0x00 21. " IRQS181 ,IRQS Status Bit 181" "Low,High" bitfld.long 0x00 20. " IRQS180 ,IRQS Status Bit 180" "Low,High" textline " " bitfld.long 0x00 19. " IRQS179 ,IRQS Status Bit 179" "Low,High" bitfld.long 0x00 18. " IRQS178 ,IRQS Status Bit 178" "Low,High" bitfld.long 0x00 17. " IRQS177 ,IRQS Status Bit 177" "Low,High" textline " " bitfld.long 0x00 16. " IRQS176 ,IRQS Status Bit 176" "Low,High" bitfld.long 0x00 15. " IRQS175 ,IRQS Status Bit 175" "Low,High" bitfld.long 0x00 14. " IRQS174 ,IRQS Status Bit 174" "Low,High" textline " " bitfld.long 0x00 13. " IRQS173 ,IRQS Status Bit 173" "Low,High" bitfld.long 0x00 12. " IRQS172 ,IRQS Status Bit 172" "Low,High" bitfld.long 0x00 11. " IRQS171 ,IRQS Status Bit 171" "Low,High" textline " " bitfld.long 0x00 10. " IRQS170 ,IRQS Status Bit 170" "Low,High" bitfld.long 0x00 9. " IRQS169 ,IRQS Status Bit 169" "Low,High" bitfld.long 0x00 8. " IRQS168 ,IRQS Status Bit 168" "Low,High" textline " " bitfld.long 0x00 7. " IRQS167 ,IRQS Status Bit 167" "Low,High" bitfld.long 0x00 6. " IRQS166 ,IRQS Status Bit 166" "Low,High" bitfld.long 0x00 5. " IRQS165 ,IRQS Status Bit 165" "Low,High" textline " " bitfld.long 0x00 4. " IRQS164 ,IRQS Status Bit 164" "Low,High" bitfld.long 0x00 3. " IRQS163 ,IRQS Status Bit 163" "Low,High" bitfld.long 0x00 2. " IRQS162 ,IRQS Status Bit 162" "Low,High" textline " " bitfld.long 0x00 1. " IRQS161 ,IRQS Status Bit 161" "Low,High" bitfld.long 0x00 0. " IRQS160 ,IRQS Status Bit 160" "Low,High" else rgroup.long 0x0D18++0x03 line.long 0x0 "GICD_SPISR5,Shared Peripheral Interrupt Status Register 5" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(ad:(per.long(spr:0x31F30)&0xFFFC0000)+0x04))&0x0000001F)>=0x07) rgroup.long 0x0D1C++0x03 line.long 0x0 "GICD_SPISR6,Shared Peripheral Interrupt Status Register 6" bitfld.long 0x00 31. " IRQS223 ,IRQS Status Bit 223" "Low,High" bitfld.long 0x00 30. " IRQS222 ,IRQS Status Bit 222" "Low,High" bitfld.long 0x00 29. " IRQS221 ,IRQS Status Bit 221" "Low,High" textline " " bitfld.long 0x00 28. " IRQS220 ,IRQS Status Bit 220" "Low,High" bitfld.long 0x00 27. " IRQS219 ,IRQS Status Bit 219" "Low,High" bitfld.long 0x00 26. " IRQS218 ,IRQS Status Bit 218" "Low,High" textline " " bitfld.long 0x00 25. " IRQS217 ,IRQS Status Bit 217" "Low,High" bitfld.long 0x00 24. " IRQS216 ,IRQS Status Bit 216" "Low,High" bitfld.long 0x00 23. " IRQS215 ,IRQS Status Bit 215" "Low,High" textline " " bitfld.long 0x00 22. " IRQS214 ,IRQS Status Bit 214" "Low,High" bitfld.long 0x00 21. " IRQS213 ,IRQS Status Bit 213" "Low,High" bitfld.long 0x00 20. " IRQS212 ,IRQS Status Bit 212" "Low,High" textline " " bitfld.long 0x00 19. " IRQS211 ,IRQS Status Bit 211" "Low,High" bitfld.long 0x00 18. " IRQS210 ,IRQS Status Bit 210" "Low,High" bitfld.long 0x00 17. " IRQS209 ,IRQS Status Bit 209" "Low,High" textline " " bitfld.long 0x00 16. " IRQS208 ,IRQS Status Bit 208" "Low,High" bitfld.long 0x00 15. " IRQS207 ,IRQS Status Bit 207" "Low,High" bitfld.long 0x00 14. " IRQS206 ,IRQS Status Bit 206" "Low,High" textline " " bitfld.long 0x00 13. " IRQS205 ,IRQS Status Bit 205" "Low,High" bitfld.long 0x00 12. " IRQS204 ,IRQS Status Bit 204" "Low,High" bitfld.long 0x00 11. " IRQS203 ,IRQS Status Bit 203" "Low,High" textline " " bitfld.long 0x00 10. " IRQS202 ,IRQS Status Bit 202" "Low,High" bitfld.long 0x00 9. " IRQS201 ,IRQS Status Bit 201" "Low,High" bitfld.long 0x00 8. " IRQS200 ,IRQS Status Bit 200" "Low,High" textline " " bitfld.long 0x00 7. " IRQS199 ,IRQS Status Bit 199" "Low,High" bitfld.long 0x00 6. " IRQS198 ,IRQS Status Bit 198" "Low,High" bitfld.long 0x00 5. " IRQS197 ,IRQS Status Bit 197" "Low,High" textline " " bitfld.long 0x00 4. " IRQS196 ,IRQS Status Bit 196" "Low,High" bitfld.long 0x00 3. " IRQS195 ,IRQS Status Bit 195" "Low,High" bitfld.long 0x00 2. " IRQS194 ,IRQS Status Bit 194" "Low,High" textline " " bitfld.long 0x00 1. " IRQS193 ,IRQS Status Bit 193" "Low,High" bitfld.long 0x00 0. " IRQS192 ,IRQS Status Bit 192" "Low,High" else rgroup.long 0x0D1C++0x03 line.long 0x0 "GICD_SPISR6,Shared Peripheral Interrupt Status Register 6" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(ad:(per.long(spr:0x31F30)&0xFFFC0000)+0x04))&0x0000001F)>=0x08) rgroup.long 0x0D20++0x03 line.long 0x0 "GICD_SPISR7,Shared Peripheral Interrupt Status Register 7" bitfld.long 0x00 31. " IRQS255 ,IRQS Status Bit 255" "Low,High" bitfld.long 0x00 30. " IRQS254 ,IRQS Status Bit 254" "Low,High" bitfld.long 0x00 29. " IRQS253 ,IRQS Status Bit 253" "Low,High" textline " " bitfld.long 0x00 28. " IRQS252 ,IRQS Status Bit 252" "Low,High" bitfld.long 0x00 27. " IRQS251 ,IRQS Status Bit 251" "Low,High" bitfld.long 0x00 26. " IRQS250 ,IRQS Status Bit 250" "Low,High" textline " " bitfld.long 0x00 25. " IRQS249 ,IRQS Status Bit 249" "Low,High" bitfld.long 0x00 24. " IRQS248 ,IRQS Status Bit 248" "Low,High" bitfld.long 0x00 23. " IRQS247 ,IRQS Status Bit 247" "Low,High" textline " " bitfld.long 0x00 22. " IRQS246 ,IRQS Status Bit 246" "Low,High" bitfld.long 0x00 21. " IRQS245 ,IRQS Status Bit 245" "Low,High" bitfld.long 0x00 20. " IRQS244 ,IRQS Status Bit 244" "Low,High" textline " " bitfld.long 0x00 19. " IRQS243 ,IRQS Status Bit 243" "Low,High" bitfld.long 0x00 18. " IRQS242 ,IRQS Status Bit 242" "Low,High" bitfld.long 0x00 17. " IRQS241 ,IRQS Status Bit 241" "Low,High" textline " " bitfld.long 0x00 16. " IRQS240 ,IRQS Status Bit 240" "Low,High" bitfld.long 0x00 15. " IRQS239 ,IRQS Status Bit 239" "Low,High" bitfld.long 0x00 14. " IRQS238 ,IRQS Status Bit 238" "Low,High" textline " " bitfld.long 0x00 13. " IRQS237 ,IRQS Status Bit 237" "Low,High" bitfld.long 0x00 12. " IRQS236 ,IRQS Status Bit 236" "Low,High" bitfld.long 0x00 11. " IRQS235 ,IRQS Status Bit 235" "Low,High" textline " " bitfld.long 0x00 10. " IRQS234 ,IRQS Status Bit 234" "Low,High" bitfld.long 0x00 9. " IRQS233 ,IRQS Status Bit 233" "Low,High" bitfld.long 0x00 8. " IRQS232 ,IRQS Status Bit 232" "Low,High" textline " " bitfld.long 0x00 7. " IRQS231 ,IRQS Status Bit 231" "Low,High" bitfld.long 0x00 6. " IRQS230 ,IRQS Status Bit 230" "Low,High" bitfld.long 0x00 5. " IRQS229 ,IRQS Status Bit 229" "Low,High" textline " " bitfld.long 0x00 4. " IRQS228 ,IRQS Status Bit 228" "Low,High" bitfld.long 0x00 3. " IRQS227 ,IRQS Status Bit 227" "Low,High" bitfld.long 0x00 2. " IRQS226 ,IRQS Status Bit 226" "Low,High" textline " " bitfld.long 0x00 1. " IRQS225 ,IRQS Status Bit 225" "Low,High" bitfld.long 0x00 0. " IRQS224 ,IRQS Status Bit 224" "Low,High" else rgroup.long 0x0D20++0x03 line.long 0x0 "GICD_SPISR7,Shared Peripheral Interrupt Status Register 7" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(ad:(per.long(spr:0x31F30)&0xFFFC0000)+0x04))&0x0000001F)>=0x09) rgroup.long 0x0D24++0x03 line.long 0x0 "GICD_SPISR8,Shared Peripheral Interrupt Status Register 8" bitfld.long 0x00 31. " IRQS287 ,IRQS Status Bit 287" "Low,High" bitfld.long 0x00 30. " IRQS286 ,IRQS Status Bit 286" "Low,High" bitfld.long 0x00 29. " IRQS285 ,IRQS Status Bit 285" "Low,High" textline " " bitfld.long 0x00 28. " IRQS284 ,IRQS Status Bit 284" "Low,High" bitfld.long 0x00 27. " IRQS283 ,IRQS Status Bit 283" "Low,High" bitfld.long 0x00 26. " IRQS282 ,IRQS Status Bit 282" "Low,High" textline " " bitfld.long 0x00 25. " IRQS281 ,IRQS Status Bit 281" "Low,High" bitfld.long 0x00 24. " IRQS280 ,IRQS Status Bit 280" "Low,High" bitfld.long 0x00 23. " IRQS279 ,IRQS Status Bit 279" "Low,High" textline " " bitfld.long 0x00 22. " IRQS278 ,IRQS Status Bit 278" "Low,High" bitfld.long 0x00 21. " IRQS277 ,IRQS Status Bit 277" "Low,High" bitfld.long 0x00 20. " IRQS276 ,IRQS Status Bit 276" "Low,High" textline " " bitfld.long 0x00 19. " IRQS275 ,IRQS Status Bit 275" "Low,High" bitfld.long 0x00 18. " IRQS274 ,IRQS Status Bit 274" "Low,High" bitfld.long 0x00 17. " IRQS273 ,IRQS Status Bit 273" "Low,High" textline " " bitfld.long 0x00 16. " IRQS272 ,IRQS Status Bit 272" "Low,High" bitfld.long 0x00 15. " IRQS271 ,IRQS Status Bit 271" "Low,High" bitfld.long 0x00 14. " IRQS270 ,IRQS Status Bit 270" "Low,High" textline " " bitfld.long 0x00 13. " IRQS269 ,IRQS Status Bit 269" "Low,High" bitfld.long 0x00 12. " IRQS268 ,IRQS Status Bit 268" "Low,High" bitfld.long 0x00 11. " IRQS267 ,IRQS Status Bit 267" "Low,High" textline " " bitfld.long 0x00 10. " IRQS266 ,IRQS Status Bit 266" "Low,High" bitfld.long 0x00 9. " IRQS265 ,IRQS Status Bit 265" "Low,High" bitfld.long 0x00 8. " IRQS264 ,IRQS Status Bit 264" "Low,High" textline " " bitfld.long 0x00 7. " IRQS263 ,IRQS Status Bit 263" "Low,High" bitfld.long 0x00 6. " IRQS262 ,IRQS Status Bit 262" "Low,High" bitfld.long 0x00 5. " IRQS261 ,IRQS Status Bit 261" "Low,High" textline " " bitfld.long 0x00 4. " IRQS260 ,IRQS Status Bit 260" "Low,High" bitfld.long 0x00 3. " IRQS259 ,IRQS Status Bit 259" "Low,High" bitfld.long 0x00 2. " IRQS258 ,IRQS Status Bit 258" "Low,High" textline " " bitfld.long 0x00 1. " IRQS257 ,IRQS Status Bit 257" "Low,High" bitfld.long 0x00 0. " IRQS256 ,IRQS Status Bit 256" "Low,High" else rgroup.long 0x0D24++0x03 line.long 0x0 "GICD_SPISR8,Shared Peripheral Interrupt Status Register 8" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(ad:(per.long(spr:0x31F30)&0xFFFC0000)+0x04))&0x0000001F)>=0x0A) rgroup.long 0x0D28++0x03 line.long 0x0 "GICD_SPISR9,Shared Peripheral Interrupt Status Register 9" bitfld.long 0x00 31. " IRQS319 ,IRQS Status Bit 319" "Low,High" bitfld.long 0x00 30. " IRQS318 ,IRQS Status Bit 318" "Low,High" bitfld.long 0x00 29. " IRQS317 ,IRQS Status Bit 317" "Low,High" textline " " bitfld.long 0x00 28. " IRQS316 ,IRQS Status Bit 316" "Low,High" bitfld.long 0x00 27. " IRQS315 ,IRQS Status Bit 315" "Low,High" bitfld.long 0x00 26. " IRQS314 ,IRQS Status Bit 314" "Low,High" textline " " bitfld.long 0x00 25. " IRQS313 ,IRQS Status Bit 313" "Low,High" bitfld.long 0x00 24. " IRQS312 ,IRQS Status Bit 312" "Low,High" bitfld.long 0x00 23. " IRQS311 ,IRQS Status Bit 311" "Low,High" textline " " bitfld.long 0x00 22. " IRQS310 ,IRQS Status Bit 310" "Low,High" bitfld.long 0x00 21. " IRQS309 ,IRQS Status Bit 309" "Low,High" bitfld.long 0x00 20. " IRQS308 ,IRQS Status Bit 308" "Low,High" textline " " bitfld.long 0x00 19. " IRQS307 ,IRQS Status Bit 307" "Low,High" bitfld.long 0x00 18. " IRQS306 ,IRQS Status Bit 306" "Low,High" bitfld.long 0x00 17. " IRQS305 ,IRQS Status Bit 305" "Low,High" textline " " bitfld.long 0x00 16. " IRQS304 ,IRQS Status Bit 304" "Low,High" bitfld.long 0x00 15. " IRQS303 ,IRQS Status Bit 303" "Low,High" bitfld.long 0x00 14. " IRQS302 ,IRQS Status Bit 302" "Low,High" textline " " bitfld.long 0x00 13. " IRQS301 ,IRQS Status Bit 301" "Low,High" bitfld.long 0x00 12. " IRQS300 ,IRQS Status Bit 300" "Low,High" bitfld.long 0x00 11. " IRQS299 ,IRQS Status Bit 299" "Low,High" textline " " bitfld.long 0x00 10. " IRQS298 ,IRQS Status Bit 298" "Low,High" bitfld.long 0x00 9. " IRQS297 ,IRQS Status Bit 297" "Low,High" bitfld.long 0x00 8. " IRQS296 ,IRQS Status Bit 296" "Low,High" textline " " bitfld.long 0x00 7. " IRQS295 ,IRQS Status Bit 295" "Low,High" bitfld.long 0x00 6. " IRQS294 ,IRQS Status Bit 294" "Low,High" bitfld.long 0x00 5. " IRQS293 ,IRQS Status Bit 293" "Low,High" textline " " bitfld.long 0x00 4. " IRQS292 ,IRQS Status Bit 292" "Low,High" bitfld.long 0x00 3. " IRQS291 ,IRQS Status Bit 291" "Low,High" bitfld.long 0x00 2. " IRQS290 ,IRQS Status Bit 290" "Low,High" textline " " bitfld.long 0x00 1. " IRQS289 ,IRQS Status Bit 289" "Low,High" bitfld.long 0x00 0. " IRQS288 ,IRQS Status Bit 288" "Low,High" else rgroup.long 0x0D28++0x03 line.long 0x0 "GICD_SPISR9,Shared Peripheral Interrupt Status Register 9" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(ad:(per.long(spr:0x31F30)&0xFFFC0000)+0x04))&0x0000001F)>=0x0B) rgroup.long 0x0D2C++0x03 line.long 0x0 "GICD_SPISR10,Shared Peripheral Interrupt Status Register 10" bitfld.long 0x00 31. " IRQS351 ,IRQS Status Bit 351" "Low,High" bitfld.long 0x00 30. " IRQS350 ,IRQS Status Bit 350" "Low,High" bitfld.long 0x00 29. " IRQS349 ,IRQS Status Bit 349" "Low,High" textline " " bitfld.long 0x00 28. " IRQS348 ,IRQS Status Bit 348" "Low,High" bitfld.long 0x00 27. " IRQS347 ,IRQS Status Bit 347" "Low,High" bitfld.long 0x00 26. " IRQS346 ,IRQS Status Bit 346" "Low,High" textline " " bitfld.long 0x00 25. " IRQS345 ,IRQS Status Bit 345" "Low,High" bitfld.long 0x00 24. " IRQS344 ,IRQS Status Bit 344" "Low,High" bitfld.long 0x00 23. " IRQS343 ,IRQS Status Bit 343" "Low,High" textline " " bitfld.long 0x00 22. " IRQS342 ,IRQS Status Bit 342" "Low,High" bitfld.long 0x00 21. " IRQS341 ,IRQS Status Bit 341" "Low,High" bitfld.long 0x00 20. " IRQS340 ,IRQS Status Bit 340" "Low,High" textline " " bitfld.long 0x00 19. " IRQS339 ,IRQS Status Bit 339" "Low,High" bitfld.long 0x00 18. " IRQS338 ,IRQS Status Bit 338" "Low,High" bitfld.long 0x00 17. " IRQS337 ,IRQS Status Bit 337" "Low,High" textline " " bitfld.long 0x00 16. " IRQS336 ,IRQS Status Bit 336" "Low,High" bitfld.long 0x00 15. " IRQS335 ,IRQS Status Bit 335" "Low,High" bitfld.long 0x00 14. " IRQS334 ,IRQS Status Bit 334" "Low,High" textline " " bitfld.long 0x00 13. " IRQS333 ,IRQS Status Bit 333" "Low,High" bitfld.long 0x00 12. " IRQS332 ,IRQS Status Bit 332" "Low,High" bitfld.long 0x00 11. " IRQS331 ,IRQS Status Bit 331" "Low,High" textline " " bitfld.long 0x00 10. " IRQS330 ,IRQS Status Bit 330" "Low,High" bitfld.long 0x00 9. " IRQS329 ,IRQS Status Bit 329" "Low,High" bitfld.long 0x00 8. " IRQS328 ,IRQS Status Bit 328" "Low,High" textline " " bitfld.long 0x00 7. " IRQS327 ,IRQS Status Bit 327" "Low,High" bitfld.long 0x00 6. " IRQS326 ,IRQS Status Bit 326" "Low,High" bitfld.long 0x00 5. " IRQS325 ,IRQS Status Bit 325" "Low,High" textline " " bitfld.long 0x00 4. " IRQS324 ,IRQS Status Bit 324" "Low,High" bitfld.long 0x00 3. " IRQS323 ,IRQS Status Bit 323" "Low,High" bitfld.long 0x00 2. " IRQS322 ,IRQS Status Bit 322" "Low,High" textline " " bitfld.long 0x00 1. " IRQS321 ,IRQS Status Bit 321" "Low,High" bitfld.long 0x00 0. " IRQS320 ,IRQS Status Bit 320" "Low,High" else rgroup.long 0x0D2C++0x03 line.long 0x0 "GICD_SPISR10,Shared Peripheral Interrupt Status Register 10" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(ad:(per.long(spr:0x31F30)&0xFFFC0000)+0x04))&0x0000001F)>=0x0C) rgroup.long 0x0D30++0x03 line.long 0x0 "GICD_SPISR11,Shared Peripheral Interrupt Status Register 11" bitfld.long 0x00 31. " IRQS383 ,IRQS Status Bit 383" "Low,High" bitfld.long 0x00 30. " IRQS382 ,IRQS Status Bit 382" "Low,High" bitfld.long 0x00 29. " IRQS381 ,IRQS Status Bit 381" "Low,High" textline " " bitfld.long 0x00 28. " IRQS380 ,IRQS Status Bit 380" "Low,High" bitfld.long 0x00 27. " IRQS379 ,IRQS Status Bit 379" "Low,High" bitfld.long 0x00 26. " IRQS378 ,IRQS Status Bit 378" "Low,High" textline " " bitfld.long 0x00 25. " IRQS377 ,IRQS Status Bit 377" "Low,High" bitfld.long 0x00 24. " IRQS376 ,IRQS Status Bit 376" "Low,High" bitfld.long 0x00 23. " IRQS375 ,IRQS Status Bit 375" "Low,High" textline " " bitfld.long 0x00 22. " IRQS374 ,IRQS Status Bit 374" "Low,High" bitfld.long 0x00 21. " IRQS373 ,IRQS Status Bit 373" "Low,High" bitfld.long 0x00 20. " IRQS372 ,IRQS Status Bit 372" "Low,High" textline " " bitfld.long 0x00 19. " IRQS371 ,IRQS Status Bit 371" "Low,High" bitfld.long 0x00 18. " IRQS370 ,IRQS Status Bit 370" "Low,High" bitfld.long 0x00 17. " IRQS369 ,IRQS Status Bit 369" "Low,High" textline " " bitfld.long 0x00 16. " IRQS368 ,IRQS Status Bit 368" "Low,High" bitfld.long 0x00 15. " IRQS367 ,IRQS Status Bit 367" "Low,High" bitfld.long 0x00 14. " IRQS366 ,IRQS Status Bit 366" "Low,High" textline " " bitfld.long 0x00 13. " IRQS365 ,IRQS Status Bit 365" "Low,High" bitfld.long 0x00 12. " IRQS364 ,IRQS Status Bit 364" "Low,High" bitfld.long 0x00 11. " IRQS363 ,IRQS Status Bit 363" "Low,High" textline " " bitfld.long 0x00 10. " IRQS362 ,IRQS Status Bit 362" "Low,High" bitfld.long 0x00 9. " IRQS361 ,IRQS Status Bit 361" "Low,High" bitfld.long 0x00 8. " IRQS360 ,IRQS Status Bit 360" "Low,High" textline " " bitfld.long 0x00 7. " IRQS359 ,IRQS Status Bit 359" "Low,High" bitfld.long 0x00 6. " IRQS358 ,IRQS Status Bit 358" "Low,High" bitfld.long 0x00 5. " IRQS357 ,IRQS Status Bit 357" "Low,High" textline " " bitfld.long 0x00 4. " IRQS356 ,IRQS Status Bit 356" "Low,High" bitfld.long 0x00 3. " IRQS355 ,IRQS Status Bit 355" "Low,High" bitfld.long 0x00 2. " IRQS354 ,IRQS Status Bit 354" "Low,High" textline " " bitfld.long 0x00 1. " IRQS353 ,IRQS Status Bit 353" "Low,High" bitfld.long 0x00 0. " IRQS352 ,IRQS Status Bit 352" "Low,High" else rgroup.long 0x0D30++0x03 line.long 0x0 "GICD_SPISR11,Shared Peripheral Interrupt Status Register 11" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(ad:(per.long(spr:0x31F30)&0xFFFC0000)+0x04))&0x0000001F)>=0x0D) rgroup.long 0x0D34++0x03 line.long 0x0 "GICD_SPISR12,Shared Peripheral Interrupt Status Register 12" bitfld.long 0x00 31. " IRQS415 ,IRQS Status Bit 415" "Low,High" bitfld.long 0x00 30. " IRQS414 ,IRQS Status Bit 414" "Low,High" bitfld.long 0x00 29. " IRQS413 ,IRQS Status Bit 413" "Low,High" textline " " bitfld.long 0x00 28. " IRQS412 ,IRQS Status Bit 412" "Low,High" bitfld.long 0x00 27. " IRQS411 ,IRQS Status Bit 411" "Low,High" bitfld.long 0x00 26. " IRQS410 ,IRQS Status Bit 410" "Low,High" textline " " bitfld.long 0x00 25. " IRQS409 ,IRQS Status Bit 409" "Low,High" bitfld.long 0x00 24. " IRQS408 ,IRQS Status Bit 408" "Low,High" bitfld.long 0x00 23. " IRQS407 ,IRQS Status Bit 407" "Low,High" textline " " bitfld.long 0x00 22. " IRQS406 ,IRQS Status Bit 406" "Low,High" bitfld.long 0x00 21. " IRQS405 ,IRQS Status Bit 405" "Low,High" bitfld.long 0x00 20. " IRQS404 ,IRQS Status Bit 404" "Low,High" textline " " bitfld.long 0x00 19. " IRQS403 ,IRQS Status Bit 403" "Low,High" bitfld.long 0x00 18. " IRQS402 ,IRQS Status Bit 402" "Low,High" bitfld.long 0x00 17. " IRQS401 ,IRQS Status Bit 401" "Low,High" textline " " bitfld.long 0x00 16. " IRQS400 ,IRQS Status Bit 400" "Low,High" bitfld.long 0x00 15. " IRQS399 ,IRQS Status Bit 399" "Low,High" bitfld.long 0x00 14. " IRQS398 ,IRQS Status Bit 398" "Low,High" textline " " bitfld.long 0x00 13. " IRQS397 ,IRQS Status Bit 397" "Low,High" bitfld.long 0x00 12. " IRQS396 ,IRQS Status Bit 396" "Low,High" bitfld.long 0x00 11. " IRQS395 ,IRQS Status Bit 395" "Low,High" textline " " bitfld.long 0x00 10. " IRQS394 ,IRQS Status Bit 394" "Low,High" bitfld.long 0x00 9. " IRQS393 ,IRQS Status Bit 393" "Low,High" bitfld.long 0x00 8. " IRQS392 ,IRQS Status Bit 392" "Low,High" textline " " bitfld.long 0x00 7. " IRQS391 ,IRQS Status Bit 391" "Low,High" bitfld.long 0x00 6. " IRQS390 ,IRQS Status Bit 390" "Low,High" bitfld.long 0x00 5. " IRQS389 ,IRQS Status Bit 389" "Low,High" textline " " bitfld.long 0x00 4. " IRQS388 ,IRQS Status Bit 388" "Low,High" bitfld.long 0x00 3. " IRQS387 ,IRQS Status Bit 387" "Low,High" bitfld.long 0x00 2. " IRQS386 ,IRQS Status Bit 386" "Low,High" textline " " bitfld.long 0x00 1. " IRQS385 ,IRQS Status Bit 385" "Low,High" bitfld.long 0x00 0. " IRQS384 ,IRQS Status Bit 384" "Low,High" else rgroup.long 0x0D34++0x03 line.long 0x0 "GICD_SPISR12,Shared Peripheral Interrupt Status Register 12" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(ad:(per.long(spr:0x31F30)&0xFFFC0000)+0x04))&0x0000001F)>=0x0E) rgroup.long 0x0D38++0x03 line.long 0x0 "GICD_SPISR13,Shared Peripheral Interrupt Status Register 13" bitfld.long 0x00 31. " IRQS447 ,IRQS Status Bit 447" "Low,High" bitfld.long 0x00 30. " IRQS446 ,IRQS Status Bit 446" "Low,High" bitfld.long 0x00 29. " IRQS445 ,IRQS Status Bit 445" "Low,High" textline " " bitfld.long 0x00 28. " IRQS444 ,IRQS Status Bit 444" "Low,High" bitfld.long 0x00 27. " IRQS443 ,IRQS Status Bit 443" "Low,High" bitfld.long 0x00 26. " IRQS442 ,IRQS Status Bit 442" "Low,High" textline " " bitfld.long 0x00 25. " IRQS441 ,IRQS Status Bit 441" "Low,High" bitfld.long 0x00 24. " IRQS440 ,IRQS Status Bit 440" "Low,High" bitfld.long 0x00 23. " IRQS439 ,IRQS Status Bit 439" "Low,High" textline " " bitfld.long 0x00 22. " IRQS438 ,IRQS Status Bit 438" "Low,High" bitfld.long 0x00 21. " IRQS437 ,IRQS Status Bit 437" "Low,High" bitfld.long 0x00 20. " IRQS436 ,IRQS Status Bit 436" "Low,High" textline " " bitfld.long 0x00 19. " IRQS435 ,IRQS Status Bit 435" "Low,High" bitfld.long 0x00 18. " IRQS434 ,IRQS Status Bit 434" "Low,High" bitfld.long 0x00 17. " IRQS433 ,IRQS Status Bit 433" "Low,High" textline " " bitfld.long 0x00 16. " IRQS432 ,IRQS Status Bit 432" "Low,High" bitfld.long 0x00 15. " IRQS431 ,IRQS Status Bit 431" "Low,High" bitfld.long 0x00 14. " IRQS430 ,IRQS Status Bit 430" "Low,High" textline " " bitfld.long 0x00 13. " IRQS429 ,IRQS Status Bit 429" "Low,High" bitfld.long 0x00 12. " IRQS428 ,IRQS Status Bit 428" "Low,High" bitfld.long 0x00 11. " IRQS427 ,IRQS Status Bit 427" "Low,High" textline " " bitfld.long 0x00 10. " IRQS426 ,IRQS Status Bit 426" "Low,High" bitfld.long 0x00 9. " IRQS425 ,IRQS Status Bit 425" "Low,High" bitfld.long 0x00 8. " IRQS424 ,IRQS Status Bit 424" "Low,High" textline " " bitfld.long 0x00 7. " IRQS423 ,IRQS Status Bit 423" "Low,High" bitfld.long 0x00 6. " IRQS422 ,IRQS Status Bit 422" "Low,High" bitfld.long 0x00 5. " IRQS421 ,IRQS Status Bit 421" "Low,High" textline " " bitfld.long 0x00 4. " IRQS420 ,IRQS Status Bit 420" "Low,High" bitfld.long 0x00 3. " IRQS419 ,IRQS Status Bit 419" "Low,High" bitfld.long 0x00 2. " IRQS418 ,IRQS Status Bit 418" "Low,High" textline " " bitfld.long 0x00 1. " IRQS417 ,IRQS Status Bit 417" "Low,High" bitfld.long 0x00 0. " IRQS416 ,IRQS Status Bit 416" "Low,High" else rgroup.long 0x0D38++0x03 line.long 0x0 "GICD_SPISR13,Shared Peripheral Interrupt Status Register 13" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(ad:(per.long(spr:0x31F30)&0xFFFC0000)+0x04))&0x0000001F)>=0x0F) rgroup.long 0x0D3C++0x03 line.long 0x0 "GICD_SPISR14,Shared Peripheral Interrupt Status Register 14" bitfld.long 0x00 31. " IRQS479 ,IRQS Status Bit 479" "Low,High" bitfld.long 0x00 30. " IRQS478 ,IRQS Status Bit 478" "Low,High" bitfld.long 0x00 29. " IRQS477 ,IRQS Status Bit 477" "Low,High" textline " " bitfld.long 0x00 28. " IRQS476 ,IRQS Status Bit 476" "Low,High" bitfld.long 0x00 27. " IRQS475 ,IRQS Status Bit 475" "Low,High" bitfld.long 0x00 26. " IRQS474 ,IRQS Status Bit 474" "Low,High" textline " " bitfld.long 0x00 25. " IRQS473 ,IRQS Status Bit 473" "Low,High" bitfld.long 0x00 24. " IRQS472 ,IRQS Status Bit 472" "Low,High" bitfld.long 0x00 23. " IRQS471 ,IRQS Status Bit 471" "Low,High" textline " " bitfld.long 0x00 22. " IRQS470 ,IRQS Status Bit 470" "Low,High" bitfld.long 0x00 21. " IRQS469 ,IRQS Status Bit 469" "Low,High" bitfld.long 0x00 20. " IRQS468 ,IRQS Status Bit 468" "Low,High" textline " " bitfld.long 0x00 19. " IRQS467 ,IRQS Status Bit 467" "Low,High" bitfld.long 0x00 18. " IRQS466 ,IRQS Status Bit 466" "Low,High" bitfld.long 0x00 17. " IRQS465 ,IRQS Status Bit 465" "Low,High" textline " " bitfld.long 0x00 16. " IRQS464 ,IRQS Status Bit 464" "Low,High" bitfld.long 0x00 15. " IRQS463 ,IRQS Status Bit 463" "Low,High" bitfld.long 0x00 14. " IRQS462 ,IRQS Status Bit 462" "Low,High" textline " " bitfld.long 0x00 13. " IRQS461 ,IRQS Status Bit 461" "Low,High" bitfld.long 0x00 12. " IRQS460 ,IRQS Status Bit 460" "Low,High" bitfld.long 0x00 11. " IRQS459 ,IRQS Status Bit 459" "Low,High" textline " " bitfld.long 0x00 10. " IRQS458 ,IRQS Status Bit 458" "Low,High" bitfld.long 0x00 9. " IRQS457 ,IRQS Status Bit 457" "Low,High" bitfld.long 0x00 8. " IRQS456 ,IRQS Status Bit 456" "Low,High" textline " " bitfld.long 0x00 7. " IRQS455 ,IRQS Status Bit 455" "Low,High" bitfld.long 0x00 6. " IRQS454 ,IRQS Status Bit 454" "Low,High" bitfld.long 0x00 5. " IRQS453 ,IRQS Status Bit 453" "Low,High" textline " " bitfld.long 0x00 4. " IRQS452 ,IRQS Status Bit 452" "Low,High" bitfld.long 0x00 3. " IRQS451 ,IRQS Status Bit 451" "Low,High" bitfld.long 0x00 2. " IRQS450 ,IRQS Status Bit 450" "Low,High" textline " " bitfld.long 0x00 1. " IRQS449 ,IRQS Status Bit 449" "Low,High" bitfld.long 0x00 0. " IRQS448 ,IRQS Status Bit 448" "Low,High" else rgroup.long 0x0D3C++0x03 line.long 0x0 "GICD_SPISR14,Shared Peripheral Interrupt Status Register 14" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(ad:(per.long(spr:0x31F30)&0xFFFC0000)+0x04))&0x0000001F)>=0x10) rgroup.long 0x0D40++0x03 line.long 0x0 "GICD_SPISR15,Shared Peripheral Interrupt Status Register 15" bitfld.long 0x00 31. " IRQS511 ,IRQS Status Bit 511" "Low,High" bitfld.long 0x00 30. " IRQS510 ,IRQS Status Bit 510" "Low,High" bitfld.long 0x00 29. " IRQS509 ,IRQS Status Bit 509" "Low,High" textline " " bitfld.long 0x00 28. " IRQS508 ,IRQS Status Bit 508" "Low,High" bitfld.long 0x00 27. " IRQS507 ,IRQS Status Bit 507" "Low,High" bitfld.long 0x00 26. " IRQS506 ,IRQS Status Bit 506" "Low,High" textline " " bitfld.long 0x00 25. " IRQS505 ,IRQS Status Bit 505" "Low,High" bitfld.long 0x00 24. " IRQS504 ,IRQS Status Bit 504" "Low,High" bitfld.long 0x00 23. " IRQS503 ,IRQS Status Bit 503" "Low,High" textline " " bitfld.long 0x00 22. " IRQS502 ,IRQS Status Bit 502" "Low,High" bitfld.long 0x00 21. " IRQS501 ,IRQS Status Bit 501" "Low,High" bitfld.long 0x00 20. " IRQS500 ,IRQS Status Bit 500" "Low,High" textline " " bitfld.long 0x00 19. " IRQS499 ,IRQS Status Bit 499" "Low,High" bitfld.long 0x00 18. " IRQS498 ,IRQS Status Bit 498" "Low,High" bitfld.long 0x00 17. " IRQS497 ,IRQS Status Bit 497" "Low,High" textline " " bitfld.long 0x00 16. " IRQS496 ,IRQS Status Bit 496" "Low,High" bitfld.long 0x00 15. " IRQS495 ,IRQS Status Bit 495" "Low,High" bitfld.long 0x00 14. " IRQS494 ,IRQS Status Bit 494" "Low,High" textline " " bitfld.long 0x00 13. " IRQS493 ,IRQS Status Bit 493" "Low,High" bitfld.long 0x00 12. " IRQS492 ,IRQS Status Bit 492" "Low,High" bitfld.long 0x00 11. " IRQS491 ,IRQS Status Bit 491" "Low,High" textline " " bitfld.long 0x00 10. " IRQS490 ,IRQS Status Bit 490" "Low,High" bitfld.long 0x00 9. " IRQS489 ,IRQS Status Bit 489" "Low,High" bitfld.long 0x00 8. " IRQS488 ,IRQS Status Bit 488" "Low,High" textline " " bitfld.long 0x00 7. " IRQS487 ,IRQS Status Bit 487" "Low,High" bitfld.long 0x00 6. " IRQS486 ,IRQS Status Bit 486" "Low,High" bitfld.long 0x00 5. " IRQS485 ,IRQS Status Bit 485" "Low,High" textline " " bitfld.long 0x00 4. " IRQS484 ,IRQS Status Bit 484" "Low,High" bitfld.long 0x00 3. " IRQS483 ,IRQS Status Bit 483" "Low,High" bitfld.long 0x00 2. " IRQS482 ,IRQS Status Bit 482" "Low,High" textline " " bitfld.long 0x00 1. " IRQS481 ,IRQS Status Bit 481" "Low,High" bitfld.long 0x00 0. " IRQS480 ,IRQS Status Bit 480" "Low,High" else rgroup.long 0x0D40++0x03 line.long 0x0 "GICD_SPISR15,Shared Peripheral Interrupt Status Register 15" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(ad:(per.long(spr:0x31F30)&0xFFFC0000)+0x04))&0x0000001F)>=0x11) rgroup.long 0x0D44++0x03 line.long 0x0 "GICD_SPISR16,Shared Peripheral Interrupt Status Register 16" bitfld.long 0x00 31. " IRQS543 ,IRQS Status Bit 543" "Low,High" bitfld.long 0x00 30. " IRQS542 ,IRQS Status Bit 542" "Low,High" bitfld.long 0x00 29. " IRQS541 ,IRQS Status Bit 541" "Low,High" textline " " bitfld.long 0x00 28. " IRQS540 ,IRQS Status Bit 540" "Low,High" bitfld.long 0x00 27. " IRQS539 ,IRQS Status Bit 539" "Low,High" bitfld.long 0x00 26. " IRQS538 ,IRQS Status Bit 538" "Low,High" textline " " bitfld.long 0x00 25. " IRQS537 ,IRQS Status Bit 537" "Low,High" bitfld.long 0x00 24. " IRQS536 ,IRQS Status Bit 536" "Low,High" bitfld.long 0x00 23. " IRQS535 ,IRQS Status Bit 535" "Low,High" textline " " bitfld.long 0x00 22. " IRQS534 ,IRQS Status Bit 534" "Low,High" bitfld.long 0x00 21. " IRQS533 ,IRQS Status Bit 533" "Low,High" bitfld.long 0x00 20. " IRQS532 ,IRQS Status Bit 532" "Low,High" textline " " bitfld.long 0x00 19. " IRQS531 ,IRQS Status Bit 531" "Low,High" bitfld.long 0x00 18. " IRQS530 ,IRQS Status Bit 530" "Low,High" bitfld.long 0x00 17. " IRQS529 ,IRQS Status Bit 529" "Low,High" textline " " bitfld.long 0x00 16. " IRQS528 ,IRQS Status Bit 528" "Low,High" bitfld.long 0x00 15. " IRQS527 ,IRQS Status Bit 527" "Low,High" bitfld.long 0x00 14. " IRQS526 ,IRQS Status Bit 526" "Low,High" textline " " bitfld.long 0x00 13. " IRQS525 ,IRQS Status Bit 525" "Low,High" bitfld.long 0x00 12. " IRQS524 ,IRQS Status Bit 524" "Low,High" bitfld.long 0x00 11. " IRQS523 ,IRQS Status Bit 523" "Low,High" textline " " bitfld.long 0x00 10. " IRQS522 ,IRQS Status Bit 522" "Low,High" bitfld.long 0x00 9. " IRQS521 ,IRQS Status Bit 521" "Low,High" bitfld.long 0x00 8. " IRQS520 ,IRQS Status Bit 520" "Low,High" textline " " bitfld.long 0x00 7. " IRQS519 ,IRQS Status Bit 519" "Low,High" bitfld.long 0x00 6. " IRQS518 ,IRQS Status Bit 518" "Low,High" bitfld.long 0x00 5. " IRQS517 ,IRQS Status Bit 517" "Low,High" textline " " bitfld.long 0x00 4. " IRQS516 ,IRQS Status Bit 516" "Low,High" bitfld.long 0x00 3. " IRQS515 ,IRQS Status Bit 515" "Low,High" bitfld.long 0x00 2. " IRQS514 ,IRQS Status Bit 514" "Low,High" textline " " bitfld.long 0x00 1. " IRQS513 ,IRQS Status Bit 513" "Low,High" bitfld.long 0x00 0. " IRQS512 ,IRQS Status Bit 512" "Low,High" else rgroup.long 0x0D44++0x03 line.long 0x0 "GICD_SPISR16,Shared Peripheral Interrupt Status Register 16" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(ad:(per.long(spr:0x31F30)&0xFFFC0000)+0x04))&0x0000001F)>=0x12) rgroup.long 0x0D48++0x03 line.long 0x0 "GICD_SPISR17,Shared Peripheral Interrupt Status Register 17" bitfld.long 0x00 31. " IRQS575 ,IRQS Status Bit 575" "Low,High" bitfld.long 0x00 30. " IRQS574 ,IRQS Status Bit 574" "Low,High" bitfld.long 0x00 29. " IRQS573 ,IRQS Status Bit 573" "Low,High" textline " " bitfld.long 0x00 28. " IRQS572 ,IRQS Status Bit 572" "Low,High" bitfld.long 0x00 27. " IRQS571 ,IRQS Status Bit 571" "Low,High" bitfld.long 0x00 26. " IRQS570 ,IRQS Status Bit 570" "Low,High" textline " " bitfld.long 0x00 25. " IRQS569 ,IRQS Status Bit 569" "Low,High" bitfld.long 0x00 24. " IRQS568 ,IRQS Status Bit 568" "Low,High" bitfld.long 0x00 23. " IRQS567 ,IRQS Status Bit 567" "Low,High" textline " " bitfld.long 0x00 22. " IRQS566 ,IRQS Status Bit 566" "Low,High" bitfld.long 0x00 21. " IRQS565 ,IRQS Status Bit 565" "Low,High" bitfld.long 0x00 20. " IRQS564 ,IRQS Status Bit 564" "Low,High" textline " " bitfld.long 0x00 19. " IRQS563 ,IRQS Status Bit 563" "Low,High" bitfld.long 0x00 18. " IRQS562 ,IRQS Status Bit 562" "Low,High" bitfld.long 0x00 17. " IRQS561 ,IRQS Status Bit 561" "Low,High" textline " " bitfld.long 0x00 16. " IRQS560 ,IRQS Status Bit 560" "Low,High" bitfld.long 0x00 15. " IRQS559 ,IRQS Status Bit 559" "Low,High" bitfld.long 0x00 14. " IRQS558 ,IRQS Status Bit 558" "Low,High" textline " " bitfld.long 0x00 13. " IRQS557 ,IRQS Status Bit 557" "Low,High" bitfld.long 0x00 12. " IRQS556 ,IRQS Status Bit 556" "Low,High" bitfld.long 0x00 11. " IRQS555 ,IRQS Status Bit 555" "Low,High" textline " " bitfld.long 0x00 10. " IRQS554 ,IRQS Status Bit 554" "Low,High" bitfld.long 0x00 9. " IRQS553 ,IRQS Status Bit 553" "Low,High" bitfld.long 0x00 8. " IRQS552 ,IRQS Status Bit 552" "Low,High" textline " " bitfld.long 0x00 7. " IRQS551 ,IRQS Status Bit 551" "Low,High" bitfld.long 0x00 6. " IRQS550 ,IRQS Status Bit 550" "Low,High" bitfld.long 0x00 5. " IRQS549 ,IRQS Status Bit 549" "Low,High" textline " " bitfld.long 0x00 4. " IRQS548 ,IRQS Status Bit 548" "Low,High" bitfld.long 0x00 3. " IRQS547 ,IRQS Status Bit 547" "Low,High" bitfld.long 0x00 2. " IRQS546 ,IRQS Status Bit 546" "Low,High" textline " " bitfld.long 0x00 1. " IRQS545 ,IRQS Status Bit 545" "Low,High" bitfld.long 0x00 0. " IRQS544 ,IRQS Status Bit 544" "Low,High" else rgroup.long 0x0D48++0x03 line.long 0x0 "GICD_SPISR17,Shared Peripheral Interrupt Status Register 17" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(ad:(per.long(spr:0x31F30)&0xFFFC0000)+0x04))&0x0000001F)>=0x13) rgroup.long 0x0D4C++0x03 line.long 0x0 "GICD_SPISR18,Shared Peripheral Interrupt Status Register 18" bitfld.long 0x00 31. " IRQS607 ,IRQS Status Bit 607" "Low,High" bitfld.long 0x00 30. " IRQS606 ,IRQS Status Bit 606" "Low,High" bitfld.long 0x00 29. " IRQS605 ,IRQS Status Bit 605" "Low,High" textline " " bitfld.long 0x00 28. " IRQS604 ,IRQS Status Bit 604" "Low,High" bitfld.long 0x00 27. " IRQS603 ,IRQS Status Bit 603" "Low,High" bitfld.long 0x00 26. " IRQS602 ,IRQS Status Bit 602" "Low,High" textline " " bitfld.long 0x00 25. " IRQS601 ,IRQS Status Bit 601" "Low,High" bitfld.long 0x00 24. " IRQS600 ,IRQS Status Bit 600" "Low,High" bitfld.long 0x00 23. " IRQS599 ,IRQS Status Bit 599" "Low,High" textline " " bitfld.long 0x00 22. " IRQS598 ,IRQS Status Bit 598" "Low,High" bitfld.long 0x00 21. " IRQS597 ,IRQS Status Bit 597" "Low,High" bitfld.long 0x00 20. " IRQS596 ,IRQS Status Bit 596" "Low,High" textline " " bitfld.long 0x00 19. " IRQS595 ,IRQS Status Bit 595" "Low,High" bitfld.long 0x00 18. " IRQS594 ,IRQS Status Bit 594" "Low,High" bitfld.long 0x00 17. " IRQS593 ,IRQS Status Bit 593" "Low,High" textline " " bitfld.long 0x00 16. " IRQS592 ,IRQS Status Bit 592" "Low,High" bitfld.long 0x00 15. " IRQS591 ,IRQS Status Bit 591" "Low,High" bitfld.long 0x00 14. " IRQS590 ,IRQS Status Bit 590" "Low,High" textline " " bitfld.long 0x00 13. " IRQS589 ,IRQS Status Bit 589" "Low,High" bitfld.long 0x00 12. " IRQS588 ,IRQS Status Bit 588" "Low,High" bitfld.long 0x00 11. " IRQS587 ,IRQS Status Bit 587" "Low,High" textline " " bitfld.long 0x00 10. " IRQS586 ,IRQS Status Bit 586" "Low,High" bitfld.long 0x00 9. " IRQS585 ,IRQS Status Bit 585" "Low,High" bitfld.long 0x00 8. " IRQS584 ,IRQS Status Bit 584" "Low,High" textline " " bitfld.long 0x00 7. " IRQS583 ,IRQS Status Bit 583" "Low,High" bitfld.long 0x00 6. " IRQS582 ,IRQS Status Bit 582" "Low,High" bitfld.long 0x00 5. " IRQS581 ,IRQS Status Bit 581" "Low,High" textline " " bitfld.long 0x00 4. " IRQS580 ,IRQS Status Bit 580" "Low,High" bitfld.long 0x00 3. " IRQS579 ,IRQS Status Bit 579" "Low,High" bitfld.long 0x00 2. " IRQS578 ,IRQS Status Bit 578" "Low,High" textline " " bitfld.long 0x00 1. " IRQS577 ,IRQS Status Bit 577" "Low,High" bitfld.long 0x00 0. " IRQS576 ,IRQS Status Bit 576" "Low,High" else rgroup.long 0x0D4C++0x03 line.long 0x0 "GICD_SPISR18,Shared Peripheral Interrupt Status Register 18" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(ad:(per.long(spr:0x31F30)&0xFFFC0000)+0x04))&0x0000001F)>=0x14) rgroup.long 0x0D50++0x03 line.long 0x0 "GICD_SPISR19,Shared Peripheral Interrupt Status Register 19" bitfld.long 0x00 31. " IRQS639 ,IRQS Status Bit 639" "Low,High" bitfld.long 0x00 30. " IRQS638 ,IRQS Status Bit 638" "Low,High" bitfld.long 0x00 29. " IRQS637 ,IRQS Status Bit 637" "Low,High" textline " " bitfld.long 0x00 28. " IRQS636 ,IRQS Status Bit 636" "Low,High" bitfld.long 0x00 27. " IRQS635 ,IRQS Status Bit 635" "Low,High" bitfld.long 0x00 26. " IRQS634 ,IRQS Status Bit 634" "Low,High" textline " " bitfld.long 0x00 25. " IRQS633 ,IRQS Status Bit 633" "Low,High" bitfld.long 0x00 24. " IRQS632 ,IRQS Status Bit 632" "Low,High" bitfld.long 0x00 23. " IRQS631 ,IRQS Status Bit 631" "Low,High" textline " " bitfld.long 0x00 22. " IRQS630 ,IRQS Status Bit 630" "Low,High" bitfld.long 0x00 21. " IRQS629 ,IRQS Status Bit 629" "Low,High" bitfld.long 0x00 20. " IRQS628 ,IRQS Status Bit 628" "Low,High" textline " " bitfld.long 0x00 19. " IRQS627 ,IRQS Status Bit 627" "Low,High" bitfld.long 0x00 18. " IRQS626 ,IRQS Status Bit 626" "Low,High" bitfld.long 0x00 17. " IRQS625 ,IRQS Status Bit 625" "Low,High" textline " " bitfld.long 0x00 16. " IRQS624 ,IRQS Status Bit 624" "Low,High" bitfld.long 0x00 15. " IRQS623 ,IRQS Status Bit 623" "Low,High" bitfld.long 0x00 14. " IRQS622 ,IRQS Status Bit 622" "Low,High" textline " " bitfld.long 0x00 13. " IRQS621 ,IRQS Status Bit 621" "Low,High" bitfld.long 0x00 12. " IRQS620 ,IRQS Status Bit 620" "Low,High" bitfld.long 0x00 11. " IRQS619 ,IRQS Status Bit 619" "Low,High" textline " " bitfld.long 0x00 10. " IRQS618 ,IRQS Status Bit 618" "Low,High" bitfld.long 0x00 9. " IRQS617 ,IRQS Status Bit 617" "Low,High" bitfld.long 0x00 8. " IRQS616 ,IRQS Status Bit 616" "Low,High" textline " " bitfld.long 0x00 7. " IRQS615 ,IRQS Status Bit 615" "Low,High" bitfld.long 0x00 6. " IRQS614 ,IRQS Status Bit 614" "Low,High" bitfld.long 0x00 5. " IRQS613 ,IRQS Status Bit 613" "Low,High" textline " " bitfld.long 0x00 4. " IRQS612 ,IRQS Status Bit 612" "Low,High" bitfld.long 0x00 3. " IRQS611 ,IRQS Status Bit 611" "Low,High" bitfld.long 0x00 2. " IRQS610 ,IRQS Status Bit 610" "Low,High" textline " " bitfld.long 0x00 1. " IRQS609 ,IRQS Status Bit 609" "Low,High" bitfld.long 0x00 0. " IRQS608 ,IRQS Status Bit 608" "Low,High" else rgroup.long 0x0D50++0x03 line.long 0x0 "GICD_SPISR19,Shared Peripheral Interrupt Status Register 19" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(ad:(per.long(spr:0x31F30)&0xFFFC0000)+0x04))&0x0000001F)>=0x15) rgroup.long 0x0D54++0x03 line.long 0x0 "GICD_SPISR20,Shared Peripheral Interrupt Status Register 20" bitfld.long 0x00 31. " IRQS671 ,IRQS Status Bit 671" "Low,High" bitfld.long 0x00 30. " IRQS670 ,IRQS Status Bit 670" "Low,High" bitfld.long 0x00 29. " IRQS669 ,IRQS Status Bit 669" "Low,High" textline " " bitfld.long 0x00 28. " IRQS668 ,IRQS Status Bit 668" "Low,High" bitfld.long 0x00 27. " IRQS667 ,IRQS Status Bit 667" "Low,High" bitfld.long 0x00 26. " IRQS666 ,IRQS Status Bit 666" "Low,High" textline " " bitfld.long 0x00 25. " IRQS665 ,IRQS Status Bit 665" "Low,High" bitfld.long 0x00 24. " IRQS664 ,IRQS Status Bit 664" "Low,High" bitfld.long 0x00 23. " IRQS663 ,IRQS Status Bit 663" "Low,High" textline " " bitfld.long 0x00 22. " IRQS662 ,IRQS Status Bit 662" "Low,High" bitfld.long 0x00 21. " IRQS661 ,IRQS Status Bit 661" "Low,High" bitfld.long 0x00 20. " IRQS660 ,IRQS Status Bit 660" "Low,High" textline " " bitfld.long 0x00 19. " IRQS659 ,IRQS Status Bit 659" "Low,High" bitfld.long 0x00 18. " IRQS658 ,IRQS Status Bit 658" "Low,High" bitfld.long 0x00 17. " IRQS657 ,IRQS Status Bit 657" "Low,High" textline " " bitfld.long 0x00 16. " IRQS656 ,IRQS Status Bit 656" "Low,High" bitfld.long 0x00 15. " IRQS655 ,IRQS Status Bit 655" "Low,High" bitfld.long 0x00 14. " IRQS654 ,IRQS Status Bit 654" "Low,High" textline " " bitfld.long 0x00 13. " IRQS653 ,IRQS Status Bit 653" "Low,High" bitfld.long 0x00 12. " IRQS652 ,IRQS Status Bit 652" "Low,High" bitfld.long 0x00 11. " IRQS651 ,IRQS Status Bit 651" "Low,High" textline " " bitfld.long 0x00 10. " IRQS650 ,IRQS Status Bit 650" "Low,High" bitfld.long 0x00 9. " IRQS649 ,IRQS Status Bit 649" "Low,High" bitfld.long 0x00 8. " IRQS648 ,IRQS Status Bit 648" "Low,High" textline " " bitfld.long 0x00 7. " IRQS647 ,IRQS Status Bit 647" "Low,High" bitfld.long 0x00 6. " IRQS646 ,IRQS Status Bit 646" "Low,High" bitfld.long 0x00 5. " IRQS645 ,IRQS Status Bit 645" "Low,High" textline " " bitfld.long 0x00 4. " IRQS644 ,IRQS Status Bit 644" "Low,High" bitfld.long 0x00 3. " IRQS643 ,IRQS Status Bit 643" "Low,High" bitfld.long 0x00 2. " IRQS642 ,IRQS Status Bit 642" "Low,High" textline " " bitfld.long 0x00 1. " IRQS641 ,IRQS Status Bit 641" "Low,High" bitfld.long 0x00 0. " IRQS640 ,IRQS Status Bit 640" "Low,High" else rgroup.long 0x0D54++0x03 line.long 0x0 "GICD_SPISR20,Shared Peripheral Interrupt Status Register 20" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(ad:(per.long(spr:0x31F30)&0xFFFC0000)+0x04))&0x0000001F)>=0x16) rgroup.long 0x0D58++0x03 line.long 0x0 "GICD_SPISR21,Shared Peripheral Interrupt Status Register 21" bitfld.long 0x00 31. " IRQS703 ,IRQS Status Bit 703" "Low,High" bitfld.long 0x00 30. " IRQS702 ,IRQS Status Bit 702" "Low,High" bitfld.long 0x00 29. " IRQS701 ,IRQS Status Bit 701" "Low,High" textline " " bitfld.long 0x00 28. " IRQS700 ,IRQS Status Bit 700" "Low,High" bitfld.long 0x00 27. " IRQS699 ,IRQS Status Bit 699" "Low,High" bitfld.long 0x00 26. " IRQS698 ,IRQS Status Bit 698" "Low,High" textline " " bitfld.long 0x00 25. " IRQS697 ,IRQS Status Bit 697" "Low,High" bitfld.long 0x00 24. " IRQS696 ,IRQS Status Bit 696" "Low,High" bitfld.long 0x00 23. " IRQS695 ,IRQS Status Bit 695" "Low,High" textline " " bitfld.long 0x00 22. " IRQS694 ,IRQS Status Bit 694" "Low,High" bitfld.long 0x00 21. " IRQS693 ,IRQS Status Bit 693" "Low,High" bitfld.long 0x00 20. " IRQS692 ,IRQS Status Bit 692" "Low,High" textline " " bitfld.long 0x00 19. " IRQS691 ,IRQS Status Bit 691" "Low,High" bitfld.long 0x00 18. " IRQS690 ,IRQS Status Bit 690" "Low,High" bitfld.long 0x00 17. " IRQS689 ,IRQS Status Bit 689" "Low,High" textline " " bitfld.long 0x00 16. " IRQS688 ,IRQS Status Bit 688" "Low,High" bitfld.long 0x00 15. " IRQS687 ,IRQS Status Bit 687" "Low,High" bitfld.long 0x00 14. " IRQS686 ,IRQS Status Bit 686" "Low,High" textline " " bitfld.long 0x00 13. " IRQS685 ,IRQS Status Bit 685" "Low,High" bitfld.long 0x00 12. " IRQS684 ,IRQS Status Bit 684" "Low,High" bitfld.long 0x00 11. " IRQS683 ,IRQS Status Bit 683" "Low,High" textline " " bitfld.long 0x00 10. " IRQS682 ,IRQS Status Bit 682" "Low,High" bitfld.long 0x00 9. " IRQS681 ,IRQS Status Bit 681" "Low,High" bitfld.long 0x00 8. " IRQS680 ,IRQS Status Bit 680" "Low,High" textline " " bitfld.long 0x00 7. " IRQS679 ,IRQS Status Bit 679" "Low,High" bitfld.long 0x00 6. " IRQS678 ,IRQS Status Bit 678" "Low,High" bitfld.long 0x00 5. " IRQS677 ,IRQS Status Bit 677" "Low,High" textline " " bitfld.long 0x00 4. " IRQS676 ,IRQS Status Bit 676" "Low,High" bitfld.long 0x00 3. " IRQS675 ,IRQS Status Bit 675" "Low,High" bitfld.long 0x00 2. " IRQS674 ,IRQS Status Bit 674" "Low,High" textline " " bitfld.long 0x00 1. " IRQS673 ,IRQS Status Bit 673" "Low,High" bitfld.long 0x00 0. " IRQS672 ,IRQS Status Bit 672" "Low,High" else rgroup.long 0x0D58++0x03 line.long 0x0 "GICD_SPISR21,Shared Peripheral Interrupt Status Register 21" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(ad:(per.long(spr:0x31F30)&0xFFFC0000)+0x04))&0x0000001F)>=0x17) rgroup.long 0x0D5C++0x03 line.long 0x0 "GICD_SPISR22,Shared Peripheral Interrupt Status Register 22" bitfld.long 0x00 31. " IRQS735 ,IRQS Status Bit 735" "Low,High" bitfld.long 0x00 30. " IRQS734 ,IRQS Status Bit 734" "Low,High" bitfld.long 0x00 29. " IRQS733 ,IRQS Status Bit 733" "Low,High" textline " " bitfld.long 0x00 28. " IRQS732 ,IRQS Status Bit 732" "Low,High" bitfld.long 0x00 27. " IRQS731 ,IRQS Status Bit 731" "Low,High" bitfld.long 0x00 26. " IRQS730 ,IRQS Status Bit 730" "Low,High" textline " " bitfld.long 0x00 25. " IRQS729 ,IRQS Status Bit 729" "Low,High" bitfld.long 0x00 24. " IRQS728 ,IRQS Status Bit 728" "Low,High" bitfld.long 0x00 23. " IRQS727 ,IRQS Status Bit 727" "Low,High" textline " " bitfld.long 0x00 22. " IRQS726 ,IRQS Status Bit 726" "Low,High" bitfld.long 0x00 21. " IRQS725 ,IRQS Status Bit 725" "Low,High" bitfld.long 0x00 20. " IRQS724 ,IRQS Status Bit 724" "Low,High" textline " " bitfld.long 0x00 19. " IRQS723 ,IRQS Status Bit 723" "Low,High" bitfld.long 0x00 18. " IRQS722 ,IRQS Status Bit 722" "Low,High" bitfld.long 0x00 17. " IRQS721 ,IRQS Status Bit 721" "Low,High" textline " " bitfld.long 0x00 16. " IRQS720 ,IRQS Status Bit 720" "Low,High" bitfld.long 0x00 15. " IRQS719 ,IRQS Status Bit 719" "Low,High" bitfld.long 0x00 14. " IRQS718 ,IRQS Status Bit 718" "Low,High" textline " " bitfld.long 0x00 13. " IRQS717 ,IRQS Status Bit 717" "Low,High" bitfld.long 0x00 12. " IRQS716 ,IRQS Status Bit 716" "Low,High" bitfld.long 0x00 11. " IRQS715 ,IRQS Status Bit 715" "Low,High" textline " " bitfld.long 0x00 10. " IRQS714 ,IRQS Status Bit 714" "Low,High" bitfld.long 0x00 9. " IRQS713 ,IRQS Status Bit 713" "Low,High" bitfld.long 0x00 8. " IRQS712 ,IRQS Status Bit 712" "Low,High" textline " " bitfld.long 0x00 7. " IRQS711 ,IRQS Status Bit 711" "Low,High" bitfld.long 0x00 6. " IRQS710 ,IRQS Status Bit 710" "Low,High" bitfld.long 0x00 5. " IRQS709 ,IRQS Status Bit 709" "Low,High" textline " " bitfld.long 0x00 4. " IRQS708 ,IRQS Status Bit 708" "Low,High" bitfld.long 0x00 3. " IRQS707 ,IRQS Status Bit 707" "Low,High" bitfld.long 0x00 2. " IRQS706 ,IRQS Status Bit 706" "Low,High" textline " " bitfld.long 0x00 1. " IRQS705 ,IRQS Status Bit 705" "Low,High" bitfld.long 0x00 0. " IRQS704 ,IRQS Status Bit 704" "Low,High" else rgroup.long 0x0D5C++0x03 line.long 0x0 "GICD_SPISR22,Shared Peripheral Interrupt Status Register 22" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(ad:(per.long(spr:0x31F30)&0xFFFC0000)+0x04))&0x0000001F)>=0x18) rgroup.long 0x060++0x03 line.long 0x0 "GICD_SPISR23,Shared Peripheral Interrupt Status Register 23" bitfld.long 0x00 31. " IRQS767 ,IRQS Status Bit 767" "Low,High" bitfld.long 0x00 30. " IRQS766 ,IRQS Status Bit 766" "Low,High" bitfld.long 0x00 29. " IRQS765 ,IRQS Status Bit 765" "Low,High" textline " " bitfld.long 0x00 28. " IRQS764 ,IRQS Status Bit 764" "Low,High" bitfld.long 0x00 27. " IRQS763 ,IRQS Status Bit 763" "Low,High" bitfld.long 0x00 26. " IRQS762 ,IRQS Status Bit 762" "Low,High" textline " " bitfld.long 0x00 25. " IRQS761 ,IRQS Status Bit 761" "Low,High" bitfld.long 0x00 24. " IRQS760 ,IRQS Status Bit 760" "Low,High" bitfld.long 0x00 23. " IRQS759 ,IRQS Status Bit 759" "Low,High" textline " " bitfld.long 0x00 22. " IRQS758 ,IRQS Status Bit 758" "Low,High" bitfld.long 0x00 21. " IRQS757 ,IRQS Status Bit 757" "Low,High" bitfld.long 0x00 20. " IRQS756 ,IRQS Status Bit 756" "Low,High" textline " " bitfld.long 0x00 19. " IRQS755 ,IRQS Status Bit 755" "Low,High" bitfld.long 0x00 18. " IRQS754 ,IRQS Status Bit 754" "Low,High" bitfld.long 0x00 17. " IRQS753 ,IRQS Status Bit 753" "Low,High" textline " " bitfld.long 0x00 16. " IRQS752 ,IRQS Status Bit 752" "Low,High" bitfld.long 0x00 15. " IRQS751 ,IRQS Status Bit 751" "Low,High" bitfld.long 0x00 14. " IRQS750 ,IRQS Status Bit 750" "Low,High" textline " " bitfld.long 0x00 13. " IRQS749 ,IRQS Status Bit 749" "Low,High" bitfld.long 0x00 12. " IRQS748 ,IRQS Status Bit 748" "Low,High" bitfld.long 0x00 11. " IRQS747 ,IRQS Status Bit 747" "Low,High" textline " " bitfld.long 0x00 10. " IRQS746 ,IRQS Status Bit 746" "Low,High" bitfld.long 0x00 9. " IRQS745 ,IRQS Status Bit 745" "Low,High" bitfld.long 0x00 8. " IRQS744 ,IRQS Status Bit 744" "Low,High" textline " " bitfld.long 0x00 7. " IRQS743 ,IRQS Status Bit 743" "Low,High" bitfld.long 0x00 6. " IRQS742 ,IRQS Status Bit 742" "Low,High" bitfld.long 0x00 5. " IRQS741 ,IRQS Status Bit 741" "Low,High" textline " " bitfld.long 0x00 4. " IRQS740 ,IRQS Status Bit 740" "Low,High" bitfld.long 0x00 3. " IRQS739 ,IRQS Status Bit 739" "Low,High" bitfld.long 0x00 2. " IRQS738 ,IRQS Status Bit 738" "Low,High" textline " " bitfld.long 0x00 1. " IRQS737 ,IRQS Status Bit 737" "Low,High" bitfld.long 0x00 0. " IRQS736 ,IRQS Status Bit 736" "Low,High" else rgroup.long 0x0D60++0x03 line.long 0x0 "GICD_SPISR23,Shared Peripheral Interrupt Status Register 23" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(ad:(per.long(spr:0x31F30)&0xFFFC0000)+0x04))&0x0000001F)>=0x19) rgroup.long 0x0D64++0x03 line.long 0x0 "GICD_SPISR24,Shared Peripheral Interrupt Status Register 24" bitfld.long 0x00 31. " IRQS799 ,IRQS Status Bit 799" "Low,High" bitfld.long 0x00 30. " IRQS798 ,IRQS Status Bit 798" "Low,High" bitfld.long 0x00 29. " IRQS797 ,IRQS Status Bit 797" "Low,High" textline " " bitfld.long 0x00 28. " IRQS796 ,IRQS Status Bit 796" "Low,High" bitfld.long 0x00 27. " IRQS795 ,IRQS Status Bit 795" "Low,High" bitfld.long 0x00 26. " IRQS794 ,IRQS Status Bit 794" "Low,High" textline " " bitfld.long 0x00 25. " IRQS793 ,IRQS Status Bit 793" "Low,High" bitfld.long 0x00 24. " IRQS792 ,IRQS Status Bit 792" "Low,High" bitfld.long 0x00 23. " IRQS791 ,IRQS Status Bit 791" "Low,High" textline " " bitfld.long 0x00 22. " IRQS790 ,IRQS Status Bit 790" "Low,High" bitfld.long 0x00 21. " IRQS789 ,IRQS Status Bit 789" "Low,High" bitfld.long 0x00 20. " IRQS788 ,IRQS Status Bit 788" "Low,High" textline " " bitfld.long 0x00 19. " IRQS787 ,IRQS Status Bit 787" "Low,High" bitfld.long 0x00 18. " IRQS786 ,IRQS Status Bit 786" "Low,High" bitfld.long 0x00 17. " IRQS785 ,IRQS Status Bit 785" "Low,High" textline " " bitfld.long 0x00 16. " IRQS784 ,IRQS Status Bit 784" "Low,High" bitfld.long 0x00 15. " IRQS783 ,IRQS Status Bit 783" "Low,High" bitfld.long 0x00 14. " IRQS782 ,IRQS Status Bit 782" "Low,High" textline " " bitfld.long 0x00 13. " IRQS781 ,IRQS Status Bit 781" "Low,High" bitfld.long 0x00 12. " IRQS780 ,IRQS Status Bit 780" "Low,High" bitfld.long 0x00 11. " IRQS779 ,IRQS Status Bit 779" "Low,High" textline " " bitfld.long 0x00 10. " IRQS778 ,IRQS Status Bit 778" "Low,High" bitfld.long 0x00 9. " IRQS777 ,IRQS Status Bit 777" "Low,High" bitfld.long 0x00 8. " IRQS776 ,IRQS Status Bit 776" "Low,High" textline " " bitfld.long 0x00 7. " IRQS775 ,IRQS Status Bit 775" "Low,High" bitfld.long 0x00 6. " IRQS774 ,IRQS Status Bit 774" "Low,High" bitfld.long 0x00 5. " IRQS773 ,IRQS Status Bit 773" "Low,High" textline " " bitfld.long 0x00 4. " IRQS772 ,IRQS Status Bit 772" "Low,High" bitfld.long 0x00 3. " IRQS771 ,IRQS Status Bit 771" "Low,High" bitfld.long 0x00 2. " IRQS770 ,IRQS Status Bit 770" "Low,High" textline " " bitfld.long 0x00 1. " IRQS769 ,IRQS Status Bit 769" "Low,High" bitfld.long 0x00 0. " IRQS768 ,IRQS Status Bit 768" "Low,High" else rgroup.long 0x0D64++0x03 line.long 0x0 "GICD_SPISR24,Shared Peripheral Interrupt Status Register 24" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(ad:(per.long(spr:0x31F30)&0xFFFC0000)+0x04))&0x0000001F)>=0x1A) rgroup.long 0x0D68++0x03 line.long 0x0 "GICD_SPISR25,Shared Peripheral Interrupt Status Register 25" bitfld.long 0x00 31. " IRQS831 ,IRQS Status Bit 831" "Low,High" bitfld.long 0x00 30. " IRQS830 ,IRQS Status Bit 830" "Low,High" bitfld.long 0x00 29. " IRQS829 ,IRQS Status Bit 829" "Low,High" textline " " bitfld.long 0x00 28. " IRQS828 ,IRQS Status Bit 828" "Low,High" bitfld.long 0x00 27. " IRQS827 ,IRQS Status Bit 827" "Low,High" bitfld.long 0x00 26. " IRQS826 ,IRQS Status Bit 826" "Low,High" textline " " bitfld.long 0x00 25. " IRQS825 ,IRQS Status Bit 825" "Low,High" bitfld.long 0x00 24. " IRQS824 ,IRQS Status Bit 824" "Low,High" bitfld.long 0x00 23. " IRQS823 ,IRQS Status Bit 823" "Low,High" textline " " bitfld.long 0x00 22. " IRQS822 ,IRQS Status Bit 822" "Low,High" bitfld.long 0x00 21. " IRQS821 ,IRQS Status Bit 821" "Low,High" bitfld.long 0x00 20. " IRQS820 ,IRQS Status Bit 820" "Low,High" textline " " bitfld.long 0x00 19. " IRQS819 ,IRQS Status Bit 819" "Low,High" bitfld.long 0x00 18. " IRQS818 ,IRQS Status Bit 818" "Low,High" bitfld.long 0x00 17. " IRQS817 ,IRQS Status Bit 817" "Low,High" textline " " bitfld.long 0x00 16. " IRQS816 ,IRQS Status Bit 816" "Low,High" bitfld.long 0x00 15. " IRQS815 ,IRQS Status Bit 815" "Low,High" bitfld.long 0x00 14. " IRQS814 ,IRQS Status Bit 814" "Low,High" textline " " bitfld.long 0x00 13. " IRQS813 ,IRQS Status Bit 813" "Low,High" bitfld.long 0x00 12. " IRQS812 ,IRQS Status Bit 812" "Low,High" bitfld.long 0x00 11. " IRQS811 ,IRQS Status Bit 811" "Low,High" textline " " bitfld.long 0x00 10. " IRQS810 ,IRQS Status Bit 810" "Low,High" bitfld.long 0x00 9. " IRQS809 ,IRQS Status Bit 809" "Low,High" bitfld.long 0x00 8. " IRQS808 ,IRQS Status Bit 808" "Low,High" textline " " bitfld.long 0x00 7. " IRQS807 ,IRQS Status Bit 807" "Low,High" bitfld.long 0x00 6. " IRQS806 ,IRQS Status Bit 806" "Low,High" bitfld.long 0x00 5. " IRQS805 ,IRQS Status Bit 805" "Low,High" textline " " bitfld.long 0x00 4. " IRQS804 ,IRQS Status Bit 804" "Low,High" bitfld.long 0x00 3. " IRQS803 ,IRQS Status Bit 803" "Low,High" bitfld.long 0x00 2. " IRQS802 ,IRQS Status Bit 802" "Low,High" textline " " bitfld.long 0x00 1. " IRQS801 ,IRQS Status Bit 801" "Low,High" bitfld.long 0x00 0. " IRQS800 ,IRQS Status Bit 800" "Low,High" else rgroup.long 0x0D68++0x03 line.long 0x0 "GICD_SPISR25,Shared Peripheral Interrupt Status Register 25" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(ad:(per.long(spr:0x31F30)&0xFFFC0000)+0x04))&0x0000001F)>=0x1B) rgroup.long 0x0D6C++0x03 line.long 0x0 "GICD_SPISR26,Shared Peripheral Interrupt Status Register 26" bitfld.long 0x00 31. " IRQS863 ,IRQS Status Bit 863" "Low,High" bitfld.long 0x00 30. " IRQS862 ,IRQS Status Bit 862" "Low,High" bitfld.long 0x00 29. " IRQS861 ,IRQS Status Bit 861" "Low,High" textline " " bitfld.long 0x00 28. " IRQS860 ,IRQS Status Bit 860" "Low,High" bitfld.long 0x00 27. " IRQS859 ,IRQS Status Bit 859" "Low,High" bitfld.long 0x00 26. " IRQS858 ,IRQS Status Bit 858" "Low,High" textline " " bitfld.long 0x00 25. " IRQS857 ,IRQS Status Bit 857" "Low,High" bitfld.long 0x00 24. " IRQS856 ,IRQS Status Bit 856" "Low,High" bitfld.long 0x00 23. " IRQS855 ,IRQS Status Bit 855" "Low,High" textline " " bitfld.long 0x00 22. " IRQS854 ,IRQS Status Bit 854" "Low,High" bitfld.long 0x00 21. " IRQS853 ,IRQS Status Bit 853" "Low,High" bitfld.long 0x00 20. " IRQS852 ,IRQS Status Bit 852" "Low,High" textline " " bitfld.long 0x00 19. " IRQS851 ,IRQS Status Bit 851" "Low,High" bitfld.long 0x00 18. " IRQS850 ,IRQS Status Bit 850" "Low,High" bitfld.long 0x00 17. " IRQS849 ,IRQS Status Bit 849" "Low,High" textline " " bitfld.long 0x00 16. " IRQS848 ,IRQS Status Bit 848" "Low,High" bitfld.long 0x00 15. " IRQS847 ,IRQS Status Bit 847" "Low,High" bitfld.long 0x00 14. " IRQS846 ,IRQS Status Bit 846" "Low,High" textline " " bitfld.long 0x00 13. " IRQS845 ,IRQS Status Bit 845" "Low,High" bitfld.long 0x00 12. " IRQS844 ,IRQS Status Bit 844" "Low,High" bitfld.long 0x00 11. " IRQS843 ,IRQS Status Bit 843" "Low,High" textline " " bitfld.long 0x00 10. " IRQS842 ,IRQS Status Bit 842" "Low,High" bitfld.long 0x00 9. " IRQS841 ,IRQS Status Bit 841" "Low,High" bitfld.long 0x00 8. " IRQS840 ,IRQS Status Bit 840" "Low,High" textline " " bitfld.long 0x00 7. " IRQS839 ,IRQS Status Bit 839" "Low,High" bitfld.long 0x00 6. " IRQS838 ,IRQS Status Bit 838" "Low,High" bitfld.long 0x00 5. " IRQS837 ,IRQS Status Bit 837" "Low,High" textline " " bitfld.long 0x00 4. " IRQS836 ,IRQS Status Bit 836" "Low,High" bitfld.long 0x00 3. " IRQS835 ,IRQS Status Bit 835" "Low,High" bitfld.long 0x00 2. " IRQS834 ,IRQS Status Bit 834" "Low,High" textline " " bitfld.long 0x00 1. " IRQS833 ,IRQS Status Bit 833" "Low,High" bitfld.long 0x00 0. " IRQS832 ,IRQS Status Bit 832" "Low,High" else rgroup.long 0x0D6C++0x03 line.long 0x0 "GICD_SPISR26,Shared Peripheral Interrupt Status Register 26" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(ad:(per.long(spr:0x31F30)&0xFFFC0000)+0x04))&0x0000001F)>=0x1C) rgroup.long 0x0D70++0x03 line.long 0x0 "GICD_SPISR27,Shared Peripheral Interrupt Status Register 27" bitfld.long 0x00 31. " IRQS895 ,IRQS Status Bit 895" "Low,High" bitfld.long 0x00 30. " IRQS894 ,IRQS Status Bit 894" "Low,High" bitfld.long 0x00 29. " IRQS893 ,IRQS Status Bit 893" "Low,High" textline " " bitfld.long 0x00 28. " IRQS892 ,IRQS Status Bit 892" "Low,High" bitfld.long 0x00 27. " IRQS891 ,IRQS Status Bit 891" "Low,High" bitfld.long 0x00 26. " IRQS890 ,IRQS Status Bit 890" "Low,High" textline " " bitfld.long 0x00 25. " IRQS889 ,IRQS Status Bit 889" "Low,High" bitfld.long 0x00 24. " IRQS888 ,IRQS Status Bit 888" "Low,High" bitfld.long 0x00 23. " IRQS887 ,IRQS Status Bit 887" "Low,High" textline " " bitfld.long 0x00 22. " IRQS886 ,IRQS Status Bit 886" "Low,High" bitfld.long 0x00 21. " IRQS885 ,IRQS Status Bit 885" "Low,High" bitfld.long 0x00 20. " IRQS884 ,IRQS Status Bit 884" "Low,High" textline " " bitfld.long 0x00 19. " IRQS883 ,IRQS Status Bit 883" "Low,High" bitfld.long 0x00 18. " IRQS882 ,IRQS Status Bit 882" "Low,High" bitfld.long 0x00 17. " IRQS881 ,IRQS Status Bit 881" "Low,High" textline " " bitfld.long 0x00 16. " IRQS880 ,IRQS Status Bit 880" "Low,High" bitfld.long 0x00 15. " IRQS879 ,IRQS Status Bit 879" "Low,High" bitfld.long 0x00 14. " IRQS878 ,IRQS Status Bit 878" "Low,High" textline " " bitfld.long 0x00 13. " IRQS877 ,IRQS Status Bit 877" "Low,High" bitfld.long 0x00 12. " IRQS876 ,IRQS Status Bit 876" "Low,High" bitfld.long 0x00 11. " IRQS875 ,IRQS Status Bit 875" "Low,High" textline " " bitfld.long 0x00 10. " IRQS874 ,IRQS Status Bit 874" "Low,High" bitfld.long 0x00 9. " IRQS873 ,IRQS Status Bit 873" "Low,High" bitfld.long 0x00 8. " IRQS872 ,IRQS Status Bit 872" "Low,High" textline " " bitfld.long 0x00 7. " IRQS871 ,IRQS Status Bit 871" "Low,High" bitfld.long 0x00 6. " IRQS870 ,IRQS Status Bit 870" "Low,High" bitfld.long 0x00 5. " IRQS869 ,IRQS Status Bit 869" "Low,High" textline " " bitfld.long 0x00 4. " IRQS868 ,IRQS Status Bit 868" "Low,High" bitfld.long 0x00 3. " IRQS867 ,IRQS Status Bit 867" "Low,High" bitfld.long 0x00 2. " IRQS866 ,IRQS Status Bit 866" "Low,High" textline " " bitfld.long 0x00 1. " IRQS865 ,IRQS Status Bit 865" "Low,High" bitfld.long 0x00 0. " IRQS864 ,IRQS Status Bit 864" "Low,High" else rgroup.long 0x0D70++0x03 line.long 0x0 "GICD_SPISR27,Shared Peripheral Interrupt Status Register 27" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(ad:(per.long(spr:0x31F30)&0xFFFC0000)+0x04))&0x0000001F)>=0x1D) rgroup.long 0x0D74++0x03 line.long 0x0 "GICD_SPISR28,Shared Peripheral Interrupt Status Register 28" bitfld.long 0x00 31. " IRQS927 ,IRQS Status Bit 927" "Low,High" bitfld.long 0x00 30. " IRQS926 ,IRQS Status Bit 926" "Low,High" bitfld.long 0x00 29. " IRQS925 ,IRQS Status Bit 925" "Low,High" textline " " bitfld.long 0x00 28. " IRQS924 ,IRQS Status Bit 924" "Low,High" bitfld.long 0x00 27. " IRQS923 ,IRQS Status Bit 923" "Low,High" bitfld.long 0x00 26. " IRQS922 ,IRQS Status Bit 922" "Low,High" textline " " bitfld.long 0x00 25. " IRQS921 ,IRQS Status Bit 921" "Low,High" bitfld.long 0x00 24. " IRQS920 ,IRQS Status Bit 920" "Low,High" bitfld.long 0x00 23. " IRQS919 ,IRQS Status Bit 919" "Low,High" textline " " bitfld.long 0x00 22. " IRQS918 ,IRQS Status Bit 918" "Low,High" bitfld.long 0x00 21. " IRQS917 ,IRQS Status Bit 917" "Low,High" bitfld.long 0x00 20. " IRQS916 ,IRQS Status Bit 916" "Low,High" textline " " bitfld.long 0x00 19. " IRQS915 ,IRQS Status Bit 915" "Low,High" bitfld.long 0x00 18. " IRQS914 ,IRQS Status Bit 914" "Low,High" bitfld.long 0x00 17. " IRQS913 ,IRQS Status Bit 913" "Low,High" textline " " bitfld.long 0x00 16. " IRQS912 ,IRQS Status Bit 912" "Low,High" bitfld.long 0x00 15. " IRQS911 ,IRQS Status Bit 911" "Low,High" bitfld.long 0x00 14. " IRQS910 ,IRQS Status Bit 910" "Low,High" textline " " bitfld.long 0x00 13. " IRQS909 ,IRQS Status Bit 909" "Low,High" bitfld.long 0x00 12. " IRQS908 ,IRQS Status Bit 908" "Low,High" bitfld.long 0x00 11. " IRQS907 ,IRQS Status Bit 907" "Low,High" textline " " bitfld.long 0x00 10. " IRQS906 ,IRQS Status Bit 906" "Low,High" bitfld.long 0x00 9. " IRQS905 ,IRQS Status Bit 905" "Low,High" bitfld.long 0x00 8. " IRQS904 ,IRQS Status Bit 904" "Low,High" textline " " bitfld.long 0x00 7. " IRQS903 ,IRQS Status Bit 903" "Low,High" bitfld.long 0x00 6. " IRQS902 ,IRQS Status Bit 902" "Low,High" bitfld.long 0x00 5. " IRQS901 ,IRQS Status Bit 901" "Low,High" textline " " bitfld.long 0x00 4. " IRQS900 ,IRQS Status Bit 900" "Low,High" bitfld.long 0x00 3. " IRQS899 ,IRQS Status Bit 899" "Low,High" bitfld.long 0x00 2. " IRQS898 ,IRQS Status Bit 898" "Low,High" textline " " bitfld.long 0x00 1. " IRQS897 ,IRQS Status Bit 897" "Low,High" bitfld.long 0x00 0. " IRQS896 ,IRQS Status Bit 896" "Low,High" else rgroup.long 0x0D74++0x03 line.long 0x0 "GICD_SPISR28,Shared Peripheral Interrupt Status Register 28" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(ad:(per.long(spr:0x31F30)&0xFFFC0000)+0x04))&0x0000001F)>=0x1E) rgroup.long 0x0D78++0x03 line.long 0x0 "GICD_SPISR29,Shared Peripheral Interrupt Status Register 29" bitfld.long 0x00 31. " IRQS959 ,IRQS Status Bit 959" "Low,High" bitfld.long 0x00 30. " IRQS958 ,IRQS Status Bit 958" "Low,High" bitfld.long 0x00 29. " IRQS957 ,IRQS Status Bit 957" "Low,High" textline " " bitfld.long 0x00 28. " IRQS956 ,IRQS Status Bit 956" "Low,High" bitfld.long 0x00 27. " IRQS955 ,IRQS Status Bit 955" "Low,High" bitfld.long 0x00 26. " IRQS954 ,IRQS Status Bit 954" "Low,High" textline " " bitfld.long 0x00 25. " IRQS953 ,IRQS Status Bit 953" "Low,High" bitfld.long 0x00 24. " IRQS952 ,IRQS Status Bit 952" "Low,High" bitfld.long 0x00 23. " IRQS951 ,IRQS Status Bit 951" "Low,High" textline " " bitfld.long 0x00 22. " IRQS950 ,IRQS Status Bit 950" "Low,High" bitfld.long 0x00 21. " IRQS949 ,IRQS Status Bit 949" "Low,High" bitfld.long 0x00 20. " IRQS948 ,IRQS Status Bit 948" "Low,High" textline " " bitfld.long 0x00 19. " IRQS947 ,IRQS Status Bit 947" "Low,High" bitfld.long 0x00 18. " IRQS946 ,IRQS Status Bit 946" "Low,High" bitfld.long 0x00 17. " IRQS945 ,IRQS Status Bit 945" "Low,High" textline " " bitfld.long 0x00 16. " IRQS944 ,IRQS Status Bit 944" "Low,High" bitfld.long 0x00 15. " IRQS943 ,IRQS Status Bit 943" "Low,High" bitfld.long 0x00 14. " IRQS942 ,IRQS Status Bit 942" "Low,High" textline " " bitfld.long 0x00 13. " IRQS941 ,IRQS Status Bit 941" "Low,High" bitfld.long 0x00 12. " IRQS940 ,IRQS Status Bit 940" "Low,High" bitfld.long 0x00 11. " IRQS939 ,IRQS Status Bit 939" "Low,High" textline " " bitfld.long 0x00 10. " IRQS938 ,IRQS Status Bit 938" "Low,High" bitfld.long 0x00 9. " IRQS937 ,IRQS Status Bit 937" "Low,High" bitfld.long 0x00 8. " IRQS936 ,IRQS Status Bit 936" "Low,High" textline " " bitfld.long 0x00 7. " IRQS935 ,IRQS Status Bit 935" "Low,High" bitfld.long 0x00 6. " IRQS934 ,IRQS Status Bit 934" "Low,High" bitfld.long 0x00 5. " IRQS933 ,IRQS Status Bit 933" "Low,High" textline " " bitfld.long 0x00 4. " IRQS932 ,IRQS Status Bit 932" "Low,High" bitfld.long 0x00 3. " IRQS931 ,IRQS Status Bit 931" "Low,High" bitfld.long 0x00 2. " IRQS930 ,IRQS Status Bit 930" "Low,High" textline " " bitfld.long 0x00 1. " IRQS929 ,IRQS Status Bit 929" "Low,High" bitfld.long 0x00 0. " IRQS928 ,IRQS Status Bit 928" "Low,High" else rgroup.long 0x0D78++0x03 line.long 0x0 "GICD_SPISR29,Shared Peripheral Interrupt Status Register 29" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif if (((per.l(ad:(per.long(spr:0x31F30)&0xFFFC0000)+0x04))&0x0000001F)>=0x1F) rgroup.long 0x0D7C++0x03 line.long 0x0 "GICD_SPISR30,Shared Peripheral Interrupt Status Register 30" bitfld.long 0x00 27. " IRQS987 ,IRQS Status Bit 987" "Low,High" bitfld.long 0x00 26. " IRQS986 ,IRQS Status Bit 986" "Low,High" textline " " bitfld.long 0x00 25. " IRQS985 ,IRQS Status Bit 985" "Low,High" bitfld.long 0x00 24. " IRQS984 ,IRQS Status Bit 984" "Low,High" bitfld.long 0x00 23. " IRQS983 ,IRQS Status Bit 983" "Low,High" textline " " bitfld.long 0x00 22. " IRQS982 ,IRQS Status Bit 982" "Low,High" bitfld.long 0x00 21. " IRQS981 ,IRQS Status Bit 981" "Low,High" bitfld.long 0x00 20. " IRQS980 ,IRQS Status Bit 980" "Low,High" textline " " bitfld.long 0x00 19. " IRQS979 ,IRQS Status Bit 979" "Low,High" bitfld.long 0x00 18. " IRQS978 ,IRQS Status Bit 978" "Low,High" bitfld.long 0x00 17. " IRQS977 ,IRQS Status Bit 977" "Low,High" textline " " bitfld.long 0x00 16. " IRQS976 ,IRQS Status Bit 976" "Low,High" bitfld.long 0x00 15. " IRQS975 ,IRQS Status Bit 975" "Low,High" bitfld.long 0x00 14. " IRQS974 ,IRQS Status Bit 974" "Low,High" textline " " bitfld.long 0x00 13. " IRQS973 ,IRQS Status Bit 973" "Low,High" bitfld.long 0x00 12. " IRQS972 ,IRQS Status Bit 972" "Low,High" bitfld.long 0x00 11. " IRQS971 ,IRQS Status Bit 971" "Low,High" textline " " bitfld.long 0x00 10. " IRQS970 ,IRQS Status Bit 970" "Low,High" bitfld.long 0x00 9. " IRQS969 ,IRQS Status Bit 969" "Low,High" bitfld.long 0x00 8. " IRQS968 ,IRQS Status Bit 968" "Low,High" textline " " bitfld.long 0x00 7. " IRQS967 ,IRQS Status Bit 967" "Low,High" bitfld.long 0x00 6. " IRQS966 ,IRQS Status Bit 966" "Low,High" bitfld.long 0x00 5. " IRQS965 ,IRQS Status Bit 965" "Low,High" textline " " bitfld.long 0x00 4. " IRQS964 ,IRQS Status Bit 964" "Low,High" bitfld.long 0x00 3. " IRQS963 ,IRQS Status Bit 963" "Low,High" bitfld.long 0x00 2. " IRQS962 ,IRQS Status Bit 962" "Low,High" textline " " bitfld.long 0x00 1. " IRQS961 ,IRQS Status Bit 961" "Low,High" bitfld.long 0x00 0. " IRQS960 ,IRQS Status Bit 960" "Low,High" else rgroup.long 0x0D7C++0x03 line.long 0x0 "GICD_SPISR30,Shared Peripheral Interrupt Status Register 30" textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " textline " " endif tree.end width 25. tree "Software Generated Interrupt" if (((per.l(ad:(per.long(spr:0x31F30)&0xFFFC0000)+0x04))&0x400)==0x400) wgroup.long 0x0F00++0x03 line.long 0x00 "GICD_SGIR,Software Generated Interrupt Register" bitfld.long 0x00 24.--25. " TLF ,Target List Filter" "TargetList,All CPUs,Request CPU,?..." hexmask.long.byte 0x00 16.--23. 1. " CPUTL ,CPU Target List" textline " " bitfld.long 0x00 15. " NSATT ,NSATT" "Secure,Non-secure" bitfld.long 0x00 0.--3. " SGINTID ,SGI Interrupt ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" else wgroup.long 0x0F00++0x03 line.long 0x00 "GICD_SGIR,Software Generated Interrupt Register" bitfld.long 0x00 24.--25. " TLF ,Target List Filter" "TargetList,All CPUs,Request CPU,?..." hexmask.long.byte 0x00 16.--23. 1. " CPUTL ,CPU Target List" textline " " bitfld.long 0x00 0.--3. " SGINTID ,SGI Interrupt ID" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" endif group.long 0x0F20++0x03 line.long 0x00 "GICD_SET/CLR_PENDSGIR0,SGI Set/Clear Pending Register 0" setclrfld.long 0x00 31. 0x00 31. -0x10 31. " SET/CLR_SGI0 ,SGI0 Set/Clear Pending Bit" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. -0x10 30. " SET/CLR_SGI0 ,SGI0 Set/Clear Pending Bit" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. -0x10 29. " SET/CLR_SGI0 ,SGI0 Set/Clear Pending Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 28. 0x00 28. -0x10 28. " SET/CLR_SGI0 ,SGI0 Set/Clear Pending Bit" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. -0x10 27. " SET/CLR_SGI0 ,SGI0 Set/Clear Pending Bit" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. -0x10 26. " SET/CLR_SGI0 ,SGI0 Set/Clear Pending Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. -0x10 25. " SET/CLR_SGI0 ,SGI0 Set/Clear Pending Bit" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. -0x10 24. " SET/CLR_SGI0 ,SGI0 Set/Clear Pending Bit" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. -0x10 23. " SET/CLR_SGI1 ,SGI1 Set/Clear Pending Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 22. 0x00 22. -0x10 22. " SET/CLR_SGI1 ,SGI1 Set/Clear Pending Bit" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. -0x10 21. " SET/CLR_SGI1 ,SGI1 Set/Clear Pending Bit" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. -0x10 20. " SET/CLR_SGI1 ,SGI1 Set/Clear Pending Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. -0x10 19. " SET/CLR_SGI1 ,SGI1 Set/Clear Pending Bit" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. -0x10 18. " SET/CLR_SGI1 ,SGI1 Set/Clear Pending Bit" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. -0x10 17. " SET/CLR_SGI1 ,SGI1 Set/Clear Pending Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 16. 0x00 16. -0x10 16. " SET/CLR_SGI1 ,SGI1 Set/Clear Pending Bit" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. -0x10 15. " SET/CLR_SGI2 ,SGI2 Set/Clear Pending Bit" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. -0x10 14. " SET/CLR_SGI2 ,SGI2 Set/Clear Pending Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. -0x10 13. " SET/CLR_SGI2 ,SGI2 Set/Clear Pending Bit" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. -0x10 12. " SET/CLR_SGI2 ,SGI2 Set/Clear Pending Bit" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. -0x10 11. " SET/CLR_SGI2 ,SGI2 Set/Clear Pending Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 10. 0x00 10. -0x10 10. " SET/CLR_SGI2 ,SGI2 Set/Clear Pending Bit" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. -0x10 9. " SET/CLR_SGI2 ,SGI2 Set/Clear Pending Bit" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. -0x10 8. " SET/CLR_SGI2 ,SGI2 Set/Clear Pending Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. -0x10 7. " SET/CLR_SGI3 ,SGI3 Set/Clear Pending Bit" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. -0x10 6. " SET/CLR_SGI3 ,SGI3 Set/Clear Pending Bit" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. -0x10 5. " SET/CLR_SGI3 ,SGI3 Set/Clear Pending Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 4. 0x00 4. -0x10 4. " SET/CLR_SGI3 ,SGI3 Set/Clear Pending Bit" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. -0x10 3. " SET/CLR_SGI3 ,SGI3 Set/Clear Pending Bit" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. -0x10 2. " SET/CLR_SGI3 ,SGI3 Set/Clear Pending Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. -0x10 1. " SET/CLR_SGI3 ,SGI3 Set/Clear Pending Bit" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. -0x10 0. " SET/CLR_SGI3 ,SGI3 Set/Clear Pending Bit" "Disabled,Enabled" group.long 0x0F24++0x03 line.long 0x00 "GICD_SET/CLR_PENDSGIR1,SGI Set/Clear Pending Register 1" setclrfld.long 0x00 31. 0x00 31. -0x10 31. " SET/CLR_SGI4 ,SGI4 Set/Clear Pending Bit" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. -0x10 30. " SET/CLR_SGI4 ,SGI4 Set/Clear Pending Bit" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. -0x10 29. " SET/CLR_SGI4 ,SGI4 Set/Clear Pending Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 28. 0x00 28. -0x10 28. " SET/CLR_SGI4 ,SGI4 Set/Clear Pending Bit" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. -0x10 27. " SET/CLR_SGI4 ,SGI4 Set/Clear Pending Bit" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. -0x10 26. " SET/CLR_SGI4 ,SGI4 Set/Clear Pending Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. -0x10 25. " SET/CLR_SGI4 ,SGI4 Set/Clear Pending Bit" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. -0x10 24. " SET/CLR_SGI4 ,SGI4 Set/Clear Pending Bit" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. -0x10 23. " SET/CLR_SGI5 ,SGI5 Set/Clear Pending Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 22. 0x00 22. -0x10 22. " SET/CLR_SGI5 ,SGI5 Set/Clear Pending Bit" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. -0x10 21. " SET/CLR_SGI5 ,SGI5 Set/Clear Pending Bit" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. -0x10 20. " SET/CLR_SGI5 ,SGI5 Set/Clear Pending Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. -0x10 19. " SET/CLR_SGI5 ,SGI5 Set/Clear Pending Bit" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. -0x10 18. " SET/CLR_SGI5 ,SGI5 Set/Clear Pending Bit" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. -0x10 17. " SET/CLR_SGI5 ,SGI5 Set/Clear Pending Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 16. 0x00 16. -0x10 16. " SET/CLR_SGI5 ,SGI5 Set/Clear Pending Bit" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. -0x10 15. " SET/CLR_SGI6 ,SGI6 Set/Clear Pending Bit" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. -0x10 14. " SET/CLR_SGI6 ,SGI6 Set/Clear Pending Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. -0x10 13. " SET/CLR_SGI6 ,SGI6 Set/Clear Pending Bit" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. -0x10 12. " SET/CLR_SGI6 ,SGI6 Set/Clear Pending Bit" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. -0x10 11. " SET/CLR_SGI6 ,SGI6 Set/Clear Pending Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 10. 0x00 10. -0x10 10. " SET/CLR_SGI6 ,SGI6 Set/Clear Pending Bit" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. -0x10 9. " SET/CLR_SGI6 ,SGI6 Set/Clear Pending Bit" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. -0x10 8. " SET/CLR_SGI6 ,SGI6 Set/Clear Pending Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. -0x10 7. " SET/CLR_SGI7 ,SGI7 Set/Clear Pending Bit" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. -0x10 6. " SET/CLR_SGI7 ,SGI7 Set/Clear Pending Bit" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. -0x10 5. " SET/CLR_SGI7 ,SGI7 Set/Clear Pending Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 4. 0x00 4. -0x10 4. " SET/CLR_SGI7 ,SGI7 Set/Clear Pending Bit" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. -0x10 3. " SET/CLR_SGI7 ,SGI7 Set/Clear Pending Bit" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. -0x10 2. " SET/CLR_SGI7 ,SGI7 Set/Clear Pending Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. -0x10 1. " SET/CLR_SGI7 ,SGI7 Set/Clear Pending Bit" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. -0x10 0. " SET/CLR_SGI7 ,SGI7 Set/Clear Pending Bit" "Disabled,Enabled" group.long 0x0F28++0x03 line.long 0x00 "GICD_SET/CLR_PENDSGIR2,SGI Set/Clear Pending Register 2" setclrfld.long 0x00 31. 0x00 31. -0x10 31. " SET/CLR_SGI8 ,SGI8 Set/Clear Pending Bit" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. -0x10 30. " SET/CLR_SGI8 ,SGI8 Set/Clear Pending Bit" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. -0x10 29. " SET/CLR_SGI8 ,SGI8 Set/Clear Pending Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 28. 0x00 28. -0x10 28. " SET/CLR_SGI8 ,SGI8 Set/Clear Pending Bit" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. -0x10 27. " SET/CLR_SGI8 ,SGI8 Set/Clear Pending Bit" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. -0x10 26. " SET/CLR_SGI8 ,SGI8 Set/Clear Pending Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. -0x10 25. " SET/CLR_SGI8 ,SGI8 Set/Clear Pending Bit" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. -0x10 24. " SET/CLR_SGI8 ,SGI8 Set/Clear Pending Bit" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. -0x10 23. " SET/CLR_SGI9 ,SGI9 Set/Clear Pending Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 22. 0x00 22. -0x10 22. " SET/CLR_SGI9 ,SGI9 Set/Clear Pending Bit" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. -0x10 21. " SET/CLR_SGI9 ,SGI9 Set/Clear Pending Bit" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. -0x10 20. " SET/CLR_SGI9 ,SGI9 Set/Clear Pending Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. -0x10 19. " SET/CLR_SGI9 ,SGI9 Set/Clear Pending Bit" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. -0x10 18. " SET/CLR_SGI9 ,SGI9 Set/Clear Pending Bit" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. -0x10 17. " SET/CLR_SGI9 ,SGI9 Set/Clear Pending Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 16. 0x00 16. -0x10 16. " SET/CLR_SGI9 ,SGI9 Set/Clear Pending Bit" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. -0x10 15. " SET/CLR_SGI10 ,SGI10 Set/Clear Pending Bit" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. -0x10 14. " SET/CLR_SGI10 ,SGI10 Set/Clear Pending Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. -0x10 13. " SET/CLR_SGI10 ,SGI10 Set/Clear Pending Bit" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. -0x10 12. " SET/CLR_SGI10 ,SGI10 Set/Clear Pending Bit" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. -0x10 11. " SET/CLR_SGI10 ,SGI10 Set/Clear Pending Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 10. 0x00 10. -0x10 10. " SET/CLR_SGI10 ,SGI10 Set/Clear Pending Bit" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. -0x10 9. " SET/CLR_SGI10 ,SGI10 Set/Clear Pending Bit" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. -0x10 8. " SET/CLR_SGI10 ,SGI10 Set/Clear Pending Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. -0x10 7. " SET/CLR_SGI11 ,SGI11 Set/Clear Pending Bit" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. -0x10 6. " SET/CLR_SGI11 ,SGI11 Set/Clear Pending Bit" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. -0x10 5. " SET/CLR_SGI11 ,SGI11 Set/Clear Pending Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 4. 0x00 4. -0x10 4. " SET/CLR_SGI11 ,SGI11 Set/Clear Pending Bit" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. -0x10 3. " SET/CLR_SGI11 ,SGI11 Set/Clear Pending Bit" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. -0x10 2. " SET/CLR_SGI11 ,SGI11 Set/Clear Pending Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. -0x10 1. " SET/CLR_SGI11 ,SGI11 Set/Clear Pending Bit" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. -0x10 0. " SET/CLR_SGI11 ,SGI11 Set/Clear Pending Bit" "Disabled,Enabled" group.long 0x0F2C++0x03 line.long 0x00 "GICD_SET/CLR_PENDSGIR2,SGI Set/Clear Pending Register 3" setclrfld.long 0x00 31. 0x00 31. -0x10 31. " SET/CLR_SGI12 ,SGI12 Set/Clear Pending Bit" "Disabled,Enabled" setclrfld.long 0x00 30. 0x00 30. -0x10 30. " SET/CLR_SGI12 ,SGI12 Set/Clear Pending Bit" "Disabled,Enabled" setclrfld.long 0x00 29. 0x00 29. -0x10 29. " SET/CLR_SGI12 ,SGI12 Set/Clear Pending Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 28. 0x00 28. -0x10 28. " SET/CLR_SGI12 ,SGI12 Set/Clear Pending Bit" "Disabled,Enabled" setclrfld.long 0x00 27. 0x00 27. -0x10 27. " SET/CLR_SGI12 ,SGI12 Set/Clear Pending Bit" "Disabled,Enabled" setclrfld.long 0x00 26. 0x00 26. -0x10 26. " SET/CLR_SGI12 ,SGI12 Set/Clear Pending Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 25. 0x00 25. -0x10 25. " SET/CLR_SGI12 ,SGI12 Set/Clear Pending Bit" "Disabled,Enabled" setclrfld.long 0x00 24. 0x00 24. -0x10 24. " SET/CLR_SGI12 ,SGI12 Set/Clear Pending Bit" "Disabled,Enabled" setclrfld.long 0x00 23. 0x00 23. -0x10 23. " SET/CLR_SGI13 ,SGI13 Set/Clear Pending Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 22. 0x00 22. -0x10 22. " SET/CLR_SGI13 ,SGI13 Set/Clear Pending Bit" "Disabled,Enabled" setclrfld.long 0x00 21. 0x00 21. -0x10 21. " SET/CLR_SGI13 ,SGI13 Set/Clear Pending Bit" "Disabled,Enabled" setclrfld.long 0x00 20. 0x00 20. -0x10 20. " SET/CLR_SGI13 ,SGI13 Set/Clear Pending Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 19. 0x00 19. -0x10 19. " SET/CLR_SGI13 ,SGI13 Set/Clear Pending Bit" "Disabled,Enabled" setclrfld.long 0x00 18. 0x00 18. -0x10 18. " SET/CLR_SGI13 ,SGI13 Set/Clear Pending Bit" "Disabled,Enabled" setclrfld.long 0x00 17. 0x00 17. -0x10 17. " SET/CLR_SGI13 ,SGI13 Set/Clear Pending Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 16. 0x00 16. -0x10 16. " SET/CLR_SGI13 ,SGI13 Set/Clear Pending Bit" "Disabled,Enabled" setclrfld.long 0x00 15. 0x00 15. -0x10 15. " SET/CLR_SGI14 ,SGI14 Set/Clear Pending Bit" "Disabled,Enabled" setclrfld.long 0x00 14. 0x00 14. -0x10 14. " SET/CLR_SGI14 ,SGI14 Set/Clear Pending Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 13. 0x00 13. -0x10 13. " SET/CLR_SGI14 ,SGI14 Set/Clear Pending Bit" "Disabled,Enabled" setclrfld.long 0x00 12. 0x00 12. -0x10 12. " SET/CLR_SGI14 ,SGI14 Set/Clear Pending Bit" "Disabled,Enabled" setclrfld.long 0x00 11. 0x00 11. -0x10 11. " SET/CLR_SGI14 ,SGI14 Set/Clear Pending Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 10. 0x00 10. -0x10 10. " SET/CLR_SGI14 ,SGI14 Set/Clear Pending Bit" "Disabled,Enabled" setclrfld.long 0x00 9. 0x00 9. -0x10 9. " SET/CLR_SGI14 ,SGI14 Set/Clear Pending Bit" "Disabled,Enabled" setclrfld.long 0x00 8. 0x00 8. -0x10 8. " SET/CLR_SGI14 ,SGI14 Set/Clear Pending Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 7. 0x00 7. -0x10 7. " SET/CLR_SGI15 ,SGI15 Set/Clear Pending Bit" "Disabled,Enabled" setclrfld.long 0x00 6. 0x00 6. -0x10 6. " SET/CLR_SGI15 ,SGI15 Set/Clear Pending Bit" "Disabled,Enabled" setclrfld.long 0x00 5. 0x00 5. -0x10 5. " SET/CLR_SGI15 ,SGI15 Set/Clear Pending Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 4. 0x00 4. -0x10 4. " SET/CLR_SGI15 ,SGI15 Set/Clear Pending Bit" "Disabled,Enabled" setclrfld.long 0x00 3. 0x00 3. -0x10 3. " SET/CLR_SGI15 ,SGI15 Set/Clear Pending Bit" "Disabled,Enabled" setclrfld.long 0x00 2. 0x00 2. -0x10 2. " SET/CLR_SGI15 ,SGI15 Set/Clear Pending Bit" "Disabled,Enabled" textline " " setclrfld.long 0x00 1. 0x00 1. -0x10 1. " SET/CLR_SGI15 ,SGI15 Set/Clear Pending Bit" "Disabled,Enabled" setclrfld.long 0x00 0. 0x00 0. -0x10 0. " SET/CLR_SGI15 ,SGI15 Set/Clear Pending Bit" "Disabled,Enabled" tree.end width 12. tree "Peripheral/Component ID Registers" rgroup.byte 0x0FE0++0x00 line.byte 0x00 "GICD_PIDR0,Peripheral ID0 Register" hexmask.byte 0x00 0.--7. 1. " DEVID ,DevID field" rgroup.byte 0x0FE4++0x00 line.byte 0x00 "GICD_PIDR1,Peripheral ID1 Register" bitfld.byte 0x00 4.--7. " ARCHID ,ArchID field" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.byte 0x00 0.--3. " DEVID ,DevID field" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rgroup.byte 0x0FE8++0x00 line.byte 0x00 "GICD_PIDR2,Peripheral ID2 Register" bitfld.byte 0x00 4.--7. " ARCHREV ,ArchRev field" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" bitfld.byte 0x00 3. " UJEPCODE ,UsesJEPcode field" "Low,High" bitfld.byte 0x00 0.--2. " ARCHID ,ArchID field" "0,1,2,3,4,5,6,7" rgroup.byte 0x0FEC++0x00 line.byte 0x00 "GICD_PIDR3,Peripheral ID3 Register" bitfld.byte 0x00 4.--7. " REVID ,Revision field" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rgroup.byte 0x0FD0++0x00 line.byte 0x00 "GICD_PIDR4,Peripheral ID4 Register" bitfld.byte 0x00 0.--3. " CC ,ContinuationCode field" "0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15" rgroup.byte 0xFD4++0x00 line.byte 0x00 "GICD_PIDR5,Peripheral ID5 Register" rgroup.byte 0xFD8++0x00 line.byte 0x00 "GICD_PIDR6,Peripheral ID6 Register" rgroup.byte 0xFDC++0x00 line.byte 0x00 "GICD_PIDR7,Peripheral ID7 Register" textline " " rgroup.byte 0xFF0++0x00 line.byte 0x00 "GICD_CIDR0,Component ID0 Register" hexmask.byte 0x00 0.--7. 1. " FIXVAL ,ARM-defined fixed values for the preamble for component discovery" rgroup.byte 0xFF4++0x00 line.byte 0x00 "GICD_CIDR1,Component ID1 Register" hexmask.byte 0x00 0.--7. 1. " FIXVAL ,ARM-defined fixed values for the preamble for component discovery" rgroup.byte 0xFF8++0x00 line.byte 0x00 "GICD_CIDR2,Component ID2 Register" hexmask.byte 0x00 0.--7. 1. " FIXVAL ,ARM-defined fixed values for the preamble for component discovery" rgroup.byte 0xFFC++0x00 line.byte 0x00 "GICD_CIDR3,Component ID3 Register" hexmask.byte 0x00 0.--7. 1. " FIXVAL ,ARM-defined fixed values for the preamble for component discovery" textline " " tree.end tree.end width 0x0B tree.end tree.end endif AUTOINDENT.ON CENTER TREE ENUMDELIMITER "," base ad:0x0 tree "ADC (12-bit Analog-to-Digital Converter)" sif (CORENAME()=="CORTEXR5F") base ad:0xF0860000 group.long 0x0++0xB line.long 0x0 "ADC_CTRL,ADC control register" bitfld.long 0x0 17. "DWC_SW_RST,ADC analog IP software reset" "0,1" bitfld.long 0x0 16. "SW_RST,ADC Controller Software reset" "0,1" newline bitfld.long 0x0 9. "POWERDOWN,PowerDown mode" "0,1" bitfld.long 0x0 8. "STANDBY,Standby mode" "0,1" bitfld.long 0x0 5. "DIFF_EN,differential mode enable" "0,1" newline bitfld.long 0x0 3.--4. "SELRES,Select the ADC resolution 2'b00: Resolution=6 2'b01: Resolution=8 2'b10: Resolution=10 2'b11: Resolution=12" "Resolution=6,Resolution=8,Resolution=10,Resolution=12" bitfld.long 0x0 2. "SELBG,Enables the internal bandgap voltage generator" "0,1" bitfld.long 0x0 1. "SELREF,Selects if the full-scale input range of the converter" "0,1" bitfld.long 0x0 0. "ENADC,ADC enable" "0,1" line.long 0x4 "ADC_CLK_CFG,ADC clock configuration register" bitfld.long 0x4 15. "DWC_CLK_EN,ADC analog IP clock enable" "0,1" hexmask.long.byte 0x4 2.--9. 1. "DIV_NUM,divider value" newline bitfld.long 0x4 0.--1. "SRC_SEL,select ADC clock source 2'b00: ALT_CLK 2'b01: PCLK 2'b10: EXT_CLK 2'b11: None" "ALT_CLK,PCLK,EXT_CLK,None" line.long 0x8 "ADC_TMR_CFG,ADC timer control register" hexmask.long.word 0x8 16.--31. 1. "TERMINAL_VAL,Timer terminal count value" bitfld.long 0x8 2. "TS_EN,Timestamp enable" "0,1" bitfld.long 0x8 1. "AUTO_EN,enable auto reload at the beginning of sequence conversion and auto stop at the end of it" "0,1" newline bitfld.long 0x8 0. "RELOAD,Force timer reload" "0,1" rgroup.long 0xC++0x3 line.long 0x0 "ADC_TIMER,ADC Timestamp value register" hexmask.long.word 0x0 0.--15. 1. "VALUE,ADC Timer count value" group.long 0x10++0x23 line.long 0x0 "ADC_TEST,ADC test register" bitfld.long 0x0 4.--6. "SEL,ADC test mode SEL[2:0]" "0,1,2,3,4,5,6,7" bitfld.long 0x0 1.--3. "ENCTR,ADC test control" "0,1,2,3,4,5,6,7" bitfld.long 0x0 0. "TEST_MODE,ADC test mode" "0,1" line.long 0x4 "ADC_IMASK,ADC Interrupt mask register" bitfld.long 0x4 4. "TMR_OVF,timer overflow interrupt mask" "0,1" bitfld.long 0x4 3. "EOL,end of entry loop interrupt mask" "0,1" bitfld.long 0x4 2. "CTC,Conversion time reaches preconfigured CTC value interrupt mask bit" "0,1" newline bitfld.long 0x4 1. "WML,Water mark of FIFO reaches a preconfigured level" "0,1" bitfld.long 0x4 0. "EOC,end of conversion interrupt mask bit" "0,1" line.long 0x8 "ADC_IFLAG,ADC Interrupt flag register" bitfld.long 0x8 5. "DUMMY,Indicates a dummy conversion cycle just finished in multi-channel mode." "0,1" bitfld.long 0x8 4. "TMR_OVF,internal timer overflow" "0,1" bitfld.long 0x8 3. "EOL,End of each loop in multi-channel continuous sample mode" "0,1" newline bitfld.long 0x8 2. "CTC,Conversion time reaches preconfigured CTC value" "0,1" bitfld.long 0x8 1. "WML,fifo water mark level reach preconfig value" "0,1" bitfld.long 0x8 0. "EOC,end of conversion interrupt" "0,1" line.long 0xC "ADC_DMA_CFG,ADC DMA configuration" hexmask.long.byte 0xC 8.--15. 1. "FIFO_TRIG_VAL,FIFO threshold to generate dma request" bitfld.long 0xC 2. "SW_ACK,software dma ack" "0,1" newline bitfld.long 0xC 1. "SINGLE_EN,dma single request enable" "0,1" bitfld.long 0xC 0. "DMA_EN,enable DMA request" "0,1" line.long 0x10 "ADC_SSC,ADC SOC Scheduler Control register" hexmask.long.byte 0x10 8.--15. 1. "INTERVAL,Convert interval cycle number config Interval range in [1 256] corresponding to config value [0 255]" bitfld.long 0x10 4. "CONV_STOP,Stop continuous conversion" "0,1" newline bitfld.long 0x10 3. "CONV_START,Start Conversion" "0,1" bitfld.long 0x10 2. "CONV_INIT,Init Conversion" "0,1" bitfld.long 0x10 0.--1. "CONV_MODE,ADC Conversion Mode Select 2'b00: single channel signel conversion 2'b01: single channel back to back 2'b10: single channel fixed interval 2'b11: multi-channel mode" "single channel signel conversion,single channel back to back,single channel fixed interval,multi-channel mode" line.long 0x14 "ADC_SETUP,ADC Setup time config" hexmask.long.byte 0x14 12.--15. 1. "CFG3,SETUP TIME CONFIG 3" hexmask.long.byte 0x14 8.--11. 1. "CFG2,SETUP TIME CONFIG 2" hexmask.long.byte 0x14 4.--7. 1. "CFG1,SETUP TIME CONFIG 1" newline hexmask.long.byte 0x14 0.--3. 1. "CFG0,SETUP TIME CONFIG 0" line.long 0x18 "ADC_SCHC,ADC Single Channel Config" hexmask.long.word 0x18 16.--31. 1. "CTC,Conversion Time Count" hexmask.long.byte 0x18 0.--6. 1. "CSEL,Channel Select for single channel mode" line.long 0x1C "ADC_MCHC,ADC Multi Channel Config" hexmask.long.byte 0x1C 8.--11. 1. "REPEAT,REPEAT" hexmask.long.byte 0x1C 0.--5. 1. "LOOP_END,Entry Loop End When LOOP_END=0 all entries will be enabled. Otherwise active entry number = LOOP_END" line.long 0x20 "ADC_FIFO,ADC FIFO Control and Status Register" bitfld.long 0x20 31. "ENABLE,ADC FIFO Enable" "0,1" bitfld.long 0x20 30. "FLUSH,Flush FIFO" "0,1" hexmask.long.byte 0x20 16.--23. 1. "THRE,FIFO water mark level threshold to generate interrupt" newline rbitfld.long 0x20 10. "IDLE,ADC Idle Status indicator" "0,1" rbitfld.long 0x20 9. "FULL,FIFO Full Flag" "0,1" rbitfld.long 0x20 8. "EMPTY,FIFO Empty Flag" "0,1" newline hexmask.long.byte 0x20 0.--7. 1. "WML,ADC FIFO Water Mark Level" rgroup.long 0x100++0x3 line.long 0x0 "ADC_RSLT,ADC conversion result register" bitfld.long 0x0 31. "TS_IND,Indicate current data is convert result or timestamp" "0,1" hexmask.long.byte 0x0 16.--22. 1. "CSEL,Conversion channel number only available when TS_IND=0" hexmask.long.word 0x0 0.--15. 1. "VALUE,Conversion result or timestamp" repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x4 0x8 0xC 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C ) group.long ($2+0x300)++0x3 line.long 0x0 "ADC_ENTRY_$1,ADC Entry Config" hexmask.long.byte 0x0 24.--31. 1. "TSAMP,Extra sample cycle number" bitfld.long 0x0 23. "ENABLE,entry enable" "0,1" bitfld.long 0x0 22. "SKIP,Skip entry" "0,1" bitfld.long 0x0 21. "DUMMY,Ignore channel conversion output" "0,1" newline bitfld.long 0x0 16.--17. "SETUP_SEL,setup time select" "0,1,2,3" hexmask.long.byte 0x0 8.--14. 1. "CSEL,Entry Channel Select config" newline hexmask.long.byte 0x0 0.--7. 1. "RCT,Request Counter Termination value" repeat.end repeat 16. (list 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1A 0x1B 0x1C 0x1D 0x1E 0x1F )(list 0x40 0x44 0x48 0x4C 0x50 0x54 0x58 0x5C 0x60 0x64 0x68 0x6C 0x70 0x74 0x78 0x7C ) group.long ($2+0x300)++0x3 line.long 0x0 "ADC_ENTRY_$1,ADC Entry Config" hexmask.long.byte 0x0 24.--31. 1. "TSAMP,Extra sample cycle number" bitfld.long 0x0 23. "ENABLE,entry enable" "0,1" bitfld.long 0x0 22. "SKIP,Skip entry" "0,1" bitfld.long 0x0 21. "DUMMY,Ignore channel conversion output" "0,1" newline bitfld.long 0x0 16.--17. "SETUP_SEL,setup time select" "0,1,2,3" hexmask.long.byte 0x0 8.--14. 1. "CSEL,Entry Channel Select config" newline hexmask.long.byte 0x0 0.--7. 1. "RCT,Request Counter Termination value" repeat.end repeat 16. (list 0x20 0x21 0x22 0x23 0x24 0x25 0x26 0x27 0x28 0x29 0x2A 0x2B 0x2C 0x2D 0x2E 0x2F )(list 0x80 0x84 0x88 0x8C 0x90 0x94 0x98 0x9C 0xA0 0xA4 0xA8 0xAC 0xB0 0xB4 0xB8 0xBC ) group.long ($2+0x300)++0x3 line.long 0x0 "ADC_ENTRY_$1,ADC Entry Config" hexmask.long.byte 0x0 24.--31. 1. "TSAMP,Extra sample cycle number" bitfld.long 0x0 23. "ENABLE,entry enable" "0,1" bitfld.long 0x0 22. "SKIP,Skip entry" "0,1" bitfld.long 0x0 21. "DUMMY,Ignore channel conversion output" "0,1" newline bitfld.long 0x0 16.--17. "SETUP_SEL,setup time select" "0,1,2,3" hexmask.long.byte 0x0 8.--14. 1. "CSEL,Entry Channel Select config" newline hexmask.long.byte 0x0 0.--7. 1. "RCT,Request Counter Termination value" repeat.end repeat 16. (list 0x30 0x31 0x32 0x33 0x34 0x35 0x36 0x37 0x38 0x39 0x3A 0x3B 0x3C 0x3D 0x3E 0x3F )(list 0xC0 0xC4 0xC8 0xCC 0xD0 0xD4 0xD8 0xDC 0xE0 0xE4 0xE8 0xEC 0xF0 0xF4 0xF8 0xFC ) group.long ($2+0x300)++0x3 line.long 0x0 "ADC_ENTRY_$1,ADC Entry Config" hexmask.long.byte 0x0 24.--31. 1. "TSAMP,Extra sample cycle number" bitfld.long 0x0 23. "ENABLE,entry enable" "0,1" bitfld.long 0x0 22. "SKIP,Skip entry" "0,1" bitfld.long 0x0 21. "DUMMY,Ignore channel conversion output" "0,1" newline bitfld.long 0x0 16.--17. "SETUP_SEL,setup time select" "0,1,2,3" hexmask.long.byte 0x0 8.--14. 1. "CSEL,Entry Channel Select config" newline hexmask.long.byte 0x0 0.--7. 1. "RCT,Request Counter Termination value" repeat.end repeat 8. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 )(list 0x0 0x8 0x10 0x18 0x20 0x28 0x30 0x38 ) group.long ($2+0x400)++0x3 line.long 0x0 "ADC_MON_CSR_$1,ADC monitor control and status register" bitfld.long 0x0 16. "VIOLATE,voltage violation detected" "0,1" bitfld.long 0x0 12. "FILT_EN,discard voltage violated results" "0,1" newline bitfld.long 0x0 11. "DET_OORNG,detect out-of-range voltage" "0,1" bitfld.long 0x0 10. "DET_INRNG,detect in-range voltage" "0,1" bitfld.long 0x0 9. "DET_HI,detect high voltage" "0,1" bitfld.long 0x0 8. "DET_LO,detect low voltage" "0,1" newline hexmask.long.byte 0x0 1.--7. 1. "CSEL,monitor channel select" bitfld.long 0x0 0. "ENABLE,monitor enable" "0,1" repeat.end repeat 8. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 )(list 0x0 0x8 0x10 0x18 0x20 0x28 0x30 0x38 ) group.long ($2+0x404)++0x3 line.long 0x0 "ADC_MON_THRE_$1,ADC monitor threshold register" hexmask.long.word 0x0 16.--27. 1. "HI,high voltage threshold" hexmask.long.word 0x0 0.--11. 1. "LO,low voltage threshold" repeat.end elif (CORENAME()=="CORTEXA55") base ad:0x30860000 group.long 0x0++0xB line.long 0x0 "ADC_CTRL,ADC control register" bitfld.long 0x0 17. "DWC_SW_RST,ADC analog IP software reset" "0,1" bitfld.long 0x0 16. "SW_RST,ADC Controller Software reset" "0,1" newline bitfld.long 0x0 9. "POWERDOWN,PowerDown mode" "0,1" bitfld.long 0x0 8. "STANDBY,Standby mode" "0,1" bitfld.long 0x0 5. "DIFF_EN,differential mode enable" "0,1" newline bitfld.long 0x0 3.--4. "SELRES,Select the ADC resolution 2'b00: Resolution=6 2'b01: Resolution=8 2'b10: Resolution=10 2'b11: Resolution=12" "Resolution=6,Resolution=8,Resolution=10,Resolution=12" bitfld.long 0x0 2. "SELBG,Enables the internal bandgap voltage generator" "0,1" bitfld.long 0x0 1. "SELREF,Selects if the full-scale input range of the converter" "0,1" bitfld.long 0x0 0. "ENADC,ADC enable" "0,1" line.long 0x4 "ADC_CLK_CFG,ADC clock configuration register" bitfld.long 0x4 15. "DWC_CLK_EN,ADC analog IP clock enable" "0,1" hexmask.long.byte 0x4 2.--9. 1. "DIV_NUM,divider value" newline bitfld.long 0x4 0.--1. "SRC_SEL,select ADC clock source 2'b00: ALT_CLK 2'b01: PCLK 2'b10: EXT_CLK 2'b11: None" "ALT_CLK,PCLK,EXT_CLK,None" line.long 0x8 "ADC_TMR_CFG,ADC timer control register" hexmask.long.word 0x8 16.--31. 1. "TERMINAL_VAL,Timer terminal count value" bitfld.long 0x8 2. "TS_EN,Timestamp enable" "0,1" bitfld.long 0x8 1. "AUTO_EN,enable auto reload at the beginning of sequence conversion and auto stop at the end of it" "0,1" newline bitfld.long 0x8 0. "RELOAD,Force timer reload" "0,1" rgroup.long 0xC++0x3 line.long 0x0 "ADC_TIMER,ADC Timestamp value register" hexmask.long.word 0x0 0.--15. 1. "VALUE,ADC Timer count value" group.long 0x10++0x23 line.long 0x0 "ADC_TEST,ADC test register" bitfld.long 0x0 4.--6. "SEL,ADC test mode SEL[2:0]" "0,1,2,3,4,5,6,7" bitfld.long 0x0 1.--3. "ENCTR,ADC test control" "0,1,2,3,4,5,6,7" bitfld.long 0x0 0. "TEST_MODE,ADC test mode" "0,1" line.long 0x4 "ADC_IMASK,ADC Interrupt mask register" bitfld.long 0x4 4. "TMR_OVF,timer overflow interrupt mask" "0,1" bitfld.long 0x4 3. "EOL,end of entry loop interrupt mask" "0,1" bitfld.long 0x4 2. "CTC,Conversion time reaches preconfigured CTC value interrupt mask bit" "0,1" newline bitfld.long 0x4 1. "WML,Water mark of FIFO reaches a preconfigured level" "0,1" bitfld.long 0x4 0. "EOC,end of conversion interrupt mask bit" "0,1" line.long 0x8 "ADC_IFLAG,ADC Interrupt flag register" bitfld.long 0x8 5. "DUMMY,Indicates a dummy conversion cycle just finished in multi-channel mode." "0,1" bitfld.long 0x8 4. "TMR_OVF,internal timer overflow" "0,1" bitfld.long 0x8 3. "EOL,End of each loop in multi-channel continuous sample mode" "0,1" newline bitfld.long 0x8 2. "CTC,Conversion time reaches preconfigured CTC value" "0,1" bitfld.long 0x8 1. "WML,fifo water mark level reach preconfig value" "0,1" bitfld.long 0x8 0. "EOC,end of conversion interrupt" "0,1" line.long 0xC "ADC_DMA_CFG,ADC DMA configuration" hexmask.long.byte 0xC 8.--15. 1. "FIFO_TRIG_VAL,FIFO threshold to generate dma request" bitfld.long 0xC 2. "SW_ACK,software dma ack" "0,1" newline bitfld.long 0xC 1. "SINGLE_EN,dma single request enable" "0,1" bitfld.long 0xC 0. "DMA_EN,enable DMA request" "0,1" line.long 0x10 "ADC_SSC,ADC SOC Scheduler Control register" hexmask.long.byte 0x10 8.--15. 1. "INTERVAL,Convert interval cycle number config Interval range in [1 256] corresponding to config value [0 255]" bitfld.long 0x10 4. "CONV_STOP,Stop continuous conversion" "0,1" newline bitfld.long 0x10 3. "CONV_START,Start Conversion" "0,1" bitfld.long 0x10 2. "CONV_INIT,Init Conversion" "0,1" bitfld.long 0x10 0.--1. "CONV_MODE,ADC Conversion Mode Select 2'b00: single channel signel conversion 2'b01: single channel back to back 2'b10: single channel fixed interval 2'b11: multi-channel mode" "single channel signel conversion,single channel back to back,single channel fixed interval,multi-channel mode" line.long 0x14 "ADC_SETUP,ADC Setup time config" hexmask.long.byte 0x14 12.--15. 1. "CFG3,SETUP TIME CONFIG 3" hexmask.long.byte 0x14 8.--11. 1. "CFG2,SETUP TIME CONFIG 2" hexmask.long.byte 0x14 4.--7. 1. "CFG1,SETUP TIME CONFIG 1" newline hexmask.long.byte 0x14 0.--3. 1. "CFG0,SETUP TIME CONFIG 0" line.long 0x18 "ADC_SCHC,ADC Single Channel Config" hexmask.long.word 0x18 16.--31. 1. "CTC,Conversion Time Count" hexmask.long.byte 0x18 0.--6. 1. "CSEL,Channel Select for single channel mode" line.long 0x1C "ADC_MCHC,ADC Multi Channel Config" hexmask.long.byte 0x1C 8.--11. 1. "REPEAT,REPEAT" hexmask.long.byte 0x1C 0.--5. 1. "LOOP_END,Entry Loop End When LOOP_END=0 all entries will be enabled. Otherwise active entry number = LOOP_END" line.long 0x20 "ADC_FIFO,ADC FIFO Control and Status Register" bitfld.long 0x20 31. "ENABLE,ADC FIFO Enable" "0,1" bitfld.long 0x20 30. "FLUSH,Flush FIFO" "0,1" hexmask.long.byte 0x20 16.--23. 1. "THRE,FIFO water mark level threshold to generate interrupt" newline rbitfld.long 0x20 10. "IDLE,ADC Idle Status indicator" "0,1" rbitfld.long 0x20 9. "FULL,FIFO Full Flag" "0,1" rbitfld.long 0x20 8. "EMPTY,FIFO Empty Flag" "0,1" newline hexmask.long.byte 0x20 0.--7. 1. "WML,ADC FIFO Water Mark Level" rgroup.long 0x100++0x3 line.long 0x0 "ADC_RSLT,ADC conversion result register" bitfld.long 0x0 31. "TS_IND,Indicate current data is convert result or timestamp" "0,1" hexmask.long.byte 0x0 16.--22. 1. "CSEL,Conversion channel number only available when TS_IND=0" hexmask.long.word 0x0 0.--15. 1. "VALUE,Conversion result or timestamp" repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x4 0x8 0xC 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C ) group.long ($2+0x300)++0x3 line.long 0x0 "ADC_ENTRY_$1,ADC Entry Config" hexmask.long.byte 0x0 24.--31. 1. "TSAMP,Extra sample cycle number" bitfld.long 0x0 23. "ENABLE,entry enable" "0,1" bitfld.long 0x0 22. "SKIP,Skip entry" "0,1" bitfld.long 0x0 21. "DUMMY,Ignore channel conversion output" "0,1" newline bitfld.long 0x0 16.--17. "SETUP_SEL,setup time select" "0,1,2,3" hexmask.long.byte 0x0 8.--14. 1. "CSEL,Entry Channel Select config" newline hexmask.long.byte 0x0 0.--7. 1. "RCT,Request Counter Termination value" repeat.end repeat 16. (list 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1A 0x1B 0x1C 0x1D 0x1E 0x1F )(list 0x40 0x44 0x48 0x4C 0x50 0x54 0x58 0x5C 0x60 0x64 0x68 0x6C 0x70 0x74 0x78 0x7C ) group.long ($2+0x300)++0x3 line.long 0x0 "ADC_ENTRY_$1,ADC Entry Config" hexmask.long.byte 0x0 24.--31. 1. "TSAMP,Extra sample cycle number" bitfld.long 0x0 23. "ENABLE,entry enable" "0,1" bitfld.long 0x0 22. "SKIP,Skip entry" "0,1" bitfld.long 0x0 21. "DUMMY,Ignore channel conversion output" "0,1" newline bitfld.long 0x0 16.--17. "SETUP_SEL,setup time select" "0,1,2,3" hexmask.long.byte 0x0 8.--14. 1. "CSEL,Entry Channel Select config" newline hexmask.long.byte 0x0 0.--7. 1. "RCT,Request Counter Termination value" repeat.end repeat 16. (list 0x20 0x21 0x22 0x23 0x24 0x25 0x26 0x27 0x28 0x29 0x2A 0x2B 0x2C 0x2D 0x2E 0x2F )(list 0x80 0x84 0x88 0x8C 0x90 0x94 0x98 0x9C 0xA0 0xA4 0xA8 0xAC 0xB0 0xB4 0xB8 0xBC ) group.long ($2+0x300)++0x3 line.long 0x0 "ADC_ENTRY_$1,ADC Entry Config" hexmask.long.byte 0x0 24.--31. 1. "TSAMP,Extra sample cycle number" bitfld.long 0x0 23. "ENABLE,entry enable" "0,1" bitfld.long 0x0 22. "SKIP,Skip entry" "0,1" bitfld.long 0x0 21. "DUMMY,Ignore channel conversion output" "0,1" newline bitfld.long 0x0 16.--17. "SETUP_SEL,setup time select" "0,1,2,3" hexmask.long.byte 0x0 8.--14. 1. "CSEL,Entry Channel Select config" newline hexmask.long.byte 0x0 0.--7. 1. "RCT,Request Counter Termination value" repeat.end repeat 16. (list 0x30 0x31 0x32 0x33 0x34 0x35 0x36 0x37 0x38 0x39 0x3A 0x3B 0x3C 0x3D 0x3E 0x3F )(list 0xC0 0xC4 0xC8 0xCC 0xD0 0xD4 0xD8 0xDC 0xE0 0xE4 0xE8 0xEC 0xF0 0xF4 0xF8 0xFC ) group.long ($2+0x300)++0x3 line.long 0x0 "ADC_ENTRY_$1,ADC Entry Config" hexmask.long.byte 0x0 24.--31. 1. "TSAMP,Extra sample cycle number" bitfld.long 0x0 23. "ENABLE,entry enable" "0,1" bitfld.long 0x0 22. "SKIP,Skip entry" "0,1" bitfld.long 0x0 21. "DUMMY,Ignore channel conversion output" "0,1" newline bitfld.long 0x0 16.--17. "SETUP_SEL,setup time select" "0,1,2,3" hexmask.long.byte 0x0 8.--14. 1. "CSEL,Entry Channel Select config" newline hexmask.long.byte 0x0 0.--7. 1. "RCT,Request Counter Termination value" repeat.end repeat 8. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 )(list 0x0 0x8 0x10 0x18 0x20 0x28 0x30 0x38 ) group.long ($2+0x400)++0x3 line.long 0x0 "ADC_MON_CSR_$1,ADC monitor control and status register" bitfld.long 0x0 16. "VIOLATE,voltage violation detected" "0,1" bitfld.long 0x0 12. "FILT_EN,discard voltage violated results" "0,1" newline bitfld.long 0x0 11. "DET_OORNG,detect out-of-range voltage" "0,1" bitfld.long 0x0 10. "DET_INRNG,detect in-range voltage" "0,1" bitfld.long 0x0 9. "DET_HI,detect high voltage" "0,1" bitfld.long 0x0 8. "DET_LO,detect low voltage" "0,1" newline hexmask.long.byte 0x0 1.--7. 1. "CSEL,monitor channel select" bitfld.long 0x0 0. "ENABLE,monitor enable" "0,1" repeat.end repeat 8. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 )(list 0x0 0x8 0x10 0x18 0x20 0x28 0x30 0x38 ) group.long ($2+0x404)++0x3 line.long 0x0 "ADC_MON_THRE_$1,ADC monitor threshold register" hexmask.long.word 0x0 16.--27. 1. "HI,high voltage threshold" hexmask.long.word 0x0 0.--11. 1. "LO,low voltage threshold" repeat.end endif tree.end tree "ATU (Address Translation Unit)" sif (CORENAME()=="CORTEXR5F") tree "FTBU_SECURE_CORE" base ad:0xF1C07000 group.long 0x0++0x13 line.long 0x0 "MSTID_0_ENABLE,master ID enable" bitfld.long 0x0 31. "MSTID_0_ENABLE,Master ID CFG in [7:0] is enabled. 1 - compare master_id input with MSTID_CFG[7:0]. If the master_id matches preconfigured MSTID_CFG[7:0] the corresponding translation array(TLA) is selected 0 - ignore master_id input" "ignore master_id input,compare master_id input with MSTID_CFG[7:0]" hexmask.long.byte 0x0 0.--7. 1. "MSTID_CFG_0,Preconfigured Master ID" line.long 0x4 "TLA_MST_0_3_0,TLA Master mapping value" hexmask.long 0x4 0.--31. 1. "TLA_MST_0_3_0,Translation Array 0 - TLA_MST_3_0[7:0] Translation Array 1 - TLA_MST_3_0[15:8] Translation Array 2 - TLA_MST_3_0[23:16] Translation Array 3 - TLA_MST_3_0[31:24]" line.long 0x8 "TLA_MST_0_7_4,TLA Master mapping value" hexmask.long 0x8 0.--31. 1. "TLA_MST_0_7_4,Translation Array 4 - TLA_MST_7_4[7:0] Translation Array 5 - TLA_MST_7_4[15:8] Translation Array 6 - TLA_MST7_4[23:16] Translation Array 7 - TLA_MST_7_4[31:24]" line.long 0xC "TLA_MST_0_11_8,TLA Master mapping value" hexmask.long 0xC 0.--31. 1. "TLA_MST_0_11_8,Translation Array 8 - TLA_MST_11_8[7:0] Translation Array 9 - TLA_MST_11_8[15:8] Translation Array 10 - TLA_MST_11_8[23:16] Translation Array 11 - TLA_MST_11_8[31:24]" line.long 0x10 "TLA_MST_0_15_12,TLA Master mapping value" hexmask.long 0x10 0.--31. 1. "TLA_MST_0_15_12,Translation Array 12 - TLA_MST_15_12[7:0] Translation Array 13 - TLA_MST_15_12[15:8] Translation Array 14 - TLA_MST_15_12[23:16] Translation Array 15 - TLA_MST_15_12[31:24]" group.long 0x1000++0x13 line.long 0x0 "MSTID_1_ENABLE,master ID enable" bitfld.long 0x0 31. "MSTID_1_ENABLE,Master ID CFG in [7:0] is enabled. 1 - compare master_id input with MSTID_CFG[7:0]. If the master_id matches preconfigured MSTID_CFG[7:0] the corresponding translation array(TLA) is selected 0 - ignore master_id input" "ignore master_id input,compare master_id input with MSTID_CFG[7:0]" hexmask.long.byte 0x0 0.--7. 1. "MSTID_CFG_1,Preconfigured Master ID" line.long 0x4 "TLA_MST_1_3_0,TLA Master mapping value" hexmask.long 0x4 0.--31. 1. "TLA_MST_1_3_0,Translation Array 0 - TLA_MST_3_0[7:0] Translation Array 1 - TLA_MST_3_0[15:8] Translation Array 2 - TLA_MST_3_0[23:16] Translation Array 3 - TLA_MST_3_0[31:24]" line.long 0x8 "TLA_MST_1_7_4,TLA Master mapping value" hexmask.long 0x8 0.--31. 1. "TLA_MST_1_7_4,Translation Array 4 - TLA_MST_7_4[7:0] Translation Array 5 - TLA_MST_7_4[15:8] Translation Array 6 - TLA_MST7_4[23:16] Translation Array 7 - TLA_MST_7_4[31:24]" line.long 0xC "TLA_MST_1_11_8,TLA Master mapping value" hexmask.long 0xC 0.--31. 1. "TLA_MST_1_11_8,Translation Array 8 - TLA_MST_11_8[7:0] Translation Array 9 - TLA_MST_11_8[15:8] Translation Array 10 - TLA_MST_11_8[23:16] Translation Array 11 - TLA_MST_11_8[31:24]" line.long 0x10 "TLA_MST_1_15_12,TLA Master mapping value" hexmask.long 0x10 0.--31. 1. "TLA_MST_1_15_12,Translation Array 12 - TLA_MST_15_12[7:0] Translation Array 13 - TLA_MST_15_12[15:8] Translation Array 14 - TLA_MST_15_12[23:16] Translation Array 15 - TLA_MST_15_12[31:24]" group.long 0x2000++0x13 line.long 0x0 "MSTID_2_ENABLE,master ID enable" bitfld.long 0x0 31. "MSTID_2_ENABLE,Master ID CFG in [7:0] is enabled. 1 - compare master_id input with MSTID_CFG[7:0]. If the master_id matches preconfigured MSTID_CFG[7:0] the corresponding translation array(TLA) is selected 0 - ignore master_id input" "ignore master_id input,compare master_id input with MSTID_CFG[7:0]" hexmask.long.byte 0x0 0.--7. 1. "MSTID_CFG_2,Preconfigured Master ID" line.long 0x4 "TLA_MST_2_3_0,TLA Master mapping value" hexmask.long 0x4 0.--31. 1. "TLA_MST_2_3_0,Translation Array 0 - TLA_MST_3_0[7:0] Translation Array 1 - TLA_MST_3_0[15:8] Translation Array 2 - TLA_MST_3_0[23:16] Translation Array 3 - TLA_MST_3_0[31:24]" line.long 0x8 "TLA_MST_2_7_4,TLA Master mapping value" hexmask.long 0x8 0.--31. 1. "TLA_MST_2_7_4,Translation Array 4 - TLA_MST_7_4[7:0] Translation Array 5 - TLA_MST_7_4[15:8] Translation Array 6 - TLA_MST7_4[23:16] Translation Array 7 - TLA_MST_7_4[31:24]" line.long 0xC "TLA_MST_2_11_8,TLA Master mapping value" hexmask.long 0xC 0.--31. 1. "TLA_MST_2_11_8,Translation Array 8 - TLA_MST_11_8[7:0] Translation Array 9 - TLA_MST_11_8[15:8] Translation Array 10 - TLA_MST_11_8[23:16] Translation Array 11 - TLA_MST_11_8[31:24]" line.long 0x10 "TLA_MST_2_15_12,TLA Master mapping value" hexmask.long 0x10 0.--31. 1. "TLA_MST_2_15_12,Translation Array 12 - TLA_MST_15_12[7:0] Translation Array 13 - TLA_MST_15_12[15:8] Translation Array 14 - TLA_MST_15_12[23:16] Translation Array 15 - TLA_MST_15_12[31:24]" tree.end tree "FTBU_MP_CORE" base ad:0xF1C08000 group.long 0x0++0x13 line.long 0x0 "MSTID_0_ENABLE,master ID enable" bitfld.long 0x0 31. "MSTID_0_ENABLE,Master ID CFG in [7:0] is enabled. 1 - compare master_id input with MSTID_CFG[7:0]. If the master_id matches preconfigured MSTID_CFG[7:0] the corresponding translation array(TLA) is selected 0 - ignore master_id input" "ignore master_id input,compare master_id input with MSTID_CFG[7:0]" hexmask.long.byte 0x0 0.--7. 1. "MSTID_CFG_0,Preconfigured Master ID" line.long 0x4 "TLA_MST_0_3_0,TLA Master mapping value" hexmask.long 0x4 0.--31. 1. "TLA_MST_0_3_0,Translation Array 0 - TLA_MST_3_0[7:0] Translation Array 1 - TLA_MST_3_0[15:8] Translation Array 2 - TLA_MST_3_0[23:16] Translation Array 3 - TLA_MST_3_0[31:24]" line.long 0x8 "TLA_MST_0_7_4,TLA Master mapping value" hexmask.long 0x8 0.--31. 1. "TLA_MST_0_7_4,Translation Array 4 - TLA_MST_7_4[7:0] Translation Array 5 - TLA_MST_7_4[15:8] Translation Array 6 - TLA_MST7_4[23:16] Translation Array 7 - TLA_MST_7_4[31:24]" line.long 0xC "TLA_MST_0_11_8,TLA Master mapping value" hexmask.long 0xC 0.--31. 1. "TLA_MST_0_11_8,Translation Array 8 - TLA_MST_11_8[7:0] Translation Array 9 - TLA_MST_11_8[15:8] Translation Array 10 - TLA_MST_11_8[23:16] Translation Array 11 - TLA_MST_11_8[31:24]" line.long 0x10 "TLA_MST_0_15_12,TLA Master mapping value" hexmask.long 0x10 0.--31. 1. "TLA_MST_0_15_12,Translation Array 12 - TLA_MST_15_12[7:0] Translation Array 13 - TLA_MST_15_12[15:8] Translation Array 14 - TLA_MST_15_12[23:16] Translation Array 15 - TLA_MST_15_12[31:24]" group.long 0x1000++0x13 line.long 0x0 "MSTID_1_ENABLE,master ID enable" bitfld.long 0x0 31. "MSTID_1_ENABLE,Master ID CFG in [7:0] is enabled. 1 - compare master_id input with MSTID_CFG[7:0]. If the master_id matches preconfigured MSTID_CFG[7:0] the corresponding translation array(TLA) is selected 0 - ignore master_id input" "ignore master_id input,compare master_id input with MSTID_CFG[7:0]" hexmask.long.byte 0x0 0.--7. 1. "MSTID_CFG_1,Preconfigured Master ID" line.long 0x4 "TLA_MST_1_3_0,TLA Master mapping value" hexmask.long 0x4 0.--31. 1. "TLA_MST_1_3_0,Translation Array 0 - TLA_MST_3_0[7:0] Translation Array 1 - TLA_MST_3_0[15:8] Translation Array 2 - TLA_MST_3_0[23:16] Translation Array 3 - TLA_MST_3_0[31:24]" line.long 0x8 "TLA_MST_1_7_4,TLA Master mapping value" hexmask.long 0x8 0.--31. 1. "TLA_MST_1_7_4,Translation Array 4 - TLA_MST_7_4[7:0] Translation Array 5 - TLA_MST_7_4[15:8] Translation Array 6 - TLA_MST7_4[23:16] Translation Array 7 - TLA_MST_7_4[31:24]" line.long 0xC "TLA_MST_1_11_8,TLA Master mapping value" hexmask.long 0xC 0.--31. 1. "TLA_MST_1_11_8,Translation Array 8 - TLA_MST_11_8[7:0] Translation Array 9 - TLA_MST_11_8[15:8] Translation Array 10 - TLA_MST_11_8[23:16] Translation Array 11 - TLA_MST_11_8[31:24]" line.long 0x10 "TLA_MST_1_15_12,TLA Master mapping value" hexmask.long 0x10 0.--31. 1. "TLA_MST_1_15_12,Translation Array 12 - TLA_MST_15_12[7:0] Translation Array 13 - TLA_MST_15_12[15:8] Translation Array 14 - TLA_MST_15_12[23:16] Translation Array 15 - TLA_MST_15_12[31:24]" group.long 0x2000++0x13 line.long 0x0 "MSTID_2_ENABLE,master ID enable" bitfld.long 0x0 31. "MSTID_2_ENABLE,Master ID CFG in [7:0] is enabled. 1 - compare master_id input with MSTID_CFG[7:0]. If the master_id matches preconfigured MSTID_CFG[7:0] the corresponding translation array(TLA) is selected 0 - ignore master_id input" "ignore master_id input,compare master_id input with MSTID_CFG[7:0]" hexmask.long.byte 0x0 0.--7. 1. "MSTID_CFG_2,Preconfigured Master ID" line.long 0x4 "TLA_MST_2_3_0,TLA Master mapping value" hexmask.long 0x4 0.--31. 1. "TLA_MST_2_3_0,Translation Array 0 - TLA_MST_3_0[7:0] Translation Array 1 - TLA_MST_3_0[15:8] Translation Array 2 - TLA_MST_3_0[23:16] Translation Array 3 - TLA_MST_3_0[31:24]" line.long 0x8 "TLA_MST_2_7_4,TLA Master mapping value" hexmask.long 0x8 0.--31. 1. "TLA_MST_2_7_4,Translation Array 4 - TLA_MST_7_4[7:0] Translation Array 5 - TLA_MST_7_4[15:8] Translation Array 6 - TLA_MST7_4[23:16] Translation Array 7 - TLA_MST_7_4[31:24]" line.long 0xC "TLA_MST_2_11_8,TLA Master mapping value" hexmask.long 0xC 0.--31. 1. "TLA_MST_2_11_8,Translation Array 8 - TLA_MST_11_8[7:0] Translation Array 9 - TLA_MST_11_8[15:8] Translation Array 10 - TLA_MST_11_8[23:16] Translation Array 11 - TLA_MST_11_8[31:24]" line.long 0x10 "TLA_MST_2_15_12,TLA Master mapping value" hexmask.long 0x10 0.--31. 1. "TLA_MST_2_15_12,Translation Array 12 - TLA_MST_15_12[7:0] Translation Array 13 - TLA_MST_15_12[15:8] Translation Array 14 - TLA_MST_15_12[23:16] Translation Array 15 - TLA_MST_15_12[31:24]" tree.end elif (CORENAME()=="CORTEXA55") tree "FTBU_SECURE_CORE" base ad:0x31C07000 group.long 0x0++0x13 line.long 0x0 "MSTID_0_ENABLE,master ID enable" bitfld.long 0x0 31. "MSTID_0_ENABLE,Master ID CFG in [7:0] is enabled. 1 - compare master_id input with MSTID_CFG[7:0]. If the master_id matches preconfigured MSTID_CFG[7:0] the corresponding translation array(TLA) is selected 0 - ignore master_id input" "ignore master_id input,compare master_id input with MSTID_CFG[7:0]" hexmask.long.byte 0x0 0.--7. 1. "MSTID_CFG_0,Preconfigured Master ID" line.long 0x4 "TLA_MST_0_3_0,TLA Master mapping value" hexmask.long 0x4 0.--31. 1. "TLA_MST_0_3_0,Translation Array 0 - TLA_MST_3_0[7:0] Translation Array 1 - TLA_MST_3_0[15:8] Translation Array 2 - TLA_MST_3_0[23:16] Translation Array 3 - TLA_MST_3_0[31:24]" line.long 0x8 "TLA_MST_0_7_4,TLA Master mapping value" hexmask.long 0x8 0.--31. 1. "TLA_MST_0_7_4,Translation Array 4 - TLA_MST_7_4[7:0] Translation Array 5 - TLA_MST_7_4[15:8] Translation Array 6 - TLA_MST7_4[23:16] Translation Array 7 - TLA_MST_7_4[31:24]" line.long 0xC "TLA_MST_0_11_8,TLA Master mapping value" hexmask.long 0xC 0.--31. 1. "TLA_MST_0_11_8,Translation Array 8 - TLA_MST_11_8[7:0] Translation Array 9 - TLA_MST_11_8[15:8] Translation Array 10 - TLA_MST_11_8[23:16] Translation Array 11 - TLA_MST_11_8[31:24]" line.long 0x10 "TLA_MST_0_15_12,TLA Master mapping value" hexmask.long 0x10 0.--31. 1. "TLA_MST_0_15_12,Translation Array 12 - TLA_MST_15_12[7:0] Translation Array 13 - TLA_MST_15_12[15:8] Translation Array 14 - TLA_MST_15_12[23:16] Translation Array 15 - TLA_MST_15_12[31:24]" group.long 0x1000++0x13 line.long 0x0 "MSTID_1_ENABLE,master ID enable" bitfld.long 0x0 31. "MSTID_1_ENABLE,Master ID CFG in [7:0] is enabled. 1 - compare master_id input with MSTID_CFG[7:0]. If the master_id matches preconfigured MSTID_CFG[7:0] the corresponding translation array(TLA) is selected 0 - ignore master_id input" "ignore master_id input,compare master_id input with MSTID_CFG[7:0]" hexmask.long.byte 0x0 0.--7. 1. "MSTID_CFG_1,Preconfigured Master ID" line.long 0x4 "TLA_MST_1_3_0,TLA Master mapping value" hexmask.long 0x4 0.--31. 1. "TLA_MST_1_3_0,Translation Array 0 - TLA_MST_3_0[7:0] Translation Array 1 - TLA_MST_3_0[15:8] Translation Array 2 - TLA_MST_3_0[23:16] Translation Array 3 - TLA_MST_3_0[31:24]" line.long 0x8 "TLA_MST_1_7_4,TLA Master mapping value" hexmask.long 0x8 0.--31. 1. "TLA_MST_1_7_4,Translation Array 4 - TLA_MST_7_4[7:0] Translation Array 5 - TLA_MST_7_4[15:8] Translation Array 6 - TLA_MST7_4[23:16] Translation Array 7 - TLA_MST_7_4[31:24]" line.long 0xC "TLA_MST_1_11_8,TLA Master mapping value" hexmask.long 0xC 0.--31. 1. "TLA_MST_1_11_8,Translation Array 8 - TLA_MST_11_8[7:0] Translation Array 9 - TLA_MST_11_8[15:8] Translation Array 10 - TLA_MST_11_8[23:16] Translation Array 11 - TLA_MST_11_8[31:24]" line.long 0x10 "TLA_MST_1_15_12,TLA Master mapping value" hexmask.long 0x10 0.--31. 1. "TLA_MST_1_15_12,Translation Array 12 - TLA_MST_15_12[7:0] Translation Array 13 - TLA_MST_15_12[15:8] Translation Array 14 - TLA_MST_15_12[23:16] Translation Array 15 - TLA_MST_15_12[31:24]" group.long 0x2000++0x13 line.long 0x0 "MSTID_2_ENABLE,master ID enable" bitfld.long 0x0 31. "MSTID_2_ENABLE,Master ID CFG in [7:0] is enabled. 1 - compare master_id input with MSTID_CFG[7:0]. If the master_id matches preconfigured MSTID_CFG[7:0] the corresponding translation array(TLA) is selected 0 - ignore master_id input" "ignore master_id input,compare master_id input with MSTID_CFG[7:0]" hexmask.long.byte 0x0 0.--7. 1. "MSTID_CFG_2,Preconfigured Master ID" line.long 0x4 "TLA_MST_2_3_0,TLA Master mapping value" hexmask.long 0x4 0.--31. 1. "TLA_MST_2_3_0,Translation Array 0 - TLA_MST_3_0[7:0] Translation Array 1 - TLA_MST_3_0[15:8] Translation Array 2 - TLA_MST_3_0[23:16] Translation Array 3 - TLA_MST_3_0[31:24]" line.long 0x8 "TLA_MST_2_7_4,TLA Master mapping value" hexmask.long 0x8 0.--31. 1. "TLA_MST_2_7_4,Translation Array 4 - TLA_MST_7_4[7:0] Translation Array 5 - TLA_MST_7_4[15:8] Translation Array 6 - TLA_MST7_4[23:16] Translation Array 7 - TLA_MST_7_4[31:24]" line.long 0xC "TLA_MST_2_11_8,TLA Master mapping value" hexmask.long 0xC 0.--31. 1. "TLA_MST_2_11_8,Translation Array 8 - TLA_MST_11_8[7:0] Translation Array 9 - TLA_MST_11_8[15:8] Translation Array 10 - TLA_MST_11_8[23:16] Translation Array 11 - TLA_MST_11_8[31:24]" line.long 0x10 "TLA_MST_2_15_12,TLA Master mapping value" hexmask.long 0x10 0.--31. 1. "TLA_MST_2_15_12,Translation Array 12 - TLA_MST_15_12[7:0] Translation Array 13 - TLA_MST_15_12[15:8] Translation Array 14 - TLA_MST_15_12[23:16] Translation Array 15 - TLA_MST_15_12[31:24]" tree.end tree "FTBU_MP_CORE" base ad:0x31C08000 group.long 0x0++0x13 line.long 0x0 "MSTID_0_ENABLE,master ID enable" bitfld.long 0x0 31. "MSTID_0_ENABLE,Master ID CFG in [7:0] is enabled. 1 - compare master_id input with MSTID_CFG[7:0]. If the master_id matches preconfigured MSTID_CFG[7:0] the corresponding translation array(TLA) is selected 0 - ignore master_id input" "ignore master_id input,compare master_id input with MSTID_CFG[7:0]" hexmask.long.byte 0x0 0.--7. 1. "MSTID_CFG_0,Preconfigured Master ID" line.long 0x4 "TLA_MST_0_3_0,TLA Master mapping value" hexmask.long 0x4 0.--31. 1. "TLA_MST_0_3_0,Translation Array 0 - TLA_MST_3_0[7:0] Translation Array 1 - TLA_MST_3_0[15:8] Translation Array 2 - TLA_MST_3_0[23:16] Translation Array 3 - TLA_MST_3_0[31:24]" line.long 0x8 "TLA_MST_0_7_4,TLA Master mapping value" hexmask.long 0x8 0.--31. 1. "TLA_MST_0_7_4,Translation Array 4 - TLA_MST_7_4[7:0] Translation Array 5 - TLA_MST_7_4[15:8] Translation Array 6 - TLA_MST7_4[23:16] Translation Array 7 - TLA_MST_7_4[31:24]" line.long 0xC "TLA_MST_0_11_8,TLA Master mapping value" hexmask.long 0xC 0.--31. 1. "TLA_MST_0_11_8,Translation Array 8 - TLA_MST_11_8[7:0] Translation Array 9 - TLA_MST_11_8[15:8] Translation Array 10 - TLA_MST_11_8[23:16] Translation Array 11 - TLA_MST_11_8[31:24]" line.long 0x10 "TLA_MST_0_15_12,TLA Master mapping value" hexmask.long 0x10 0.--31. 1. "TLA_MST_0_15_12,Translation Array 12 - TLA_MST_15_12[7:0] Translation Array 13 - TLA_MST_15_12[15:8] Translation Array 14 - TLA_MST_15_12[23:16] Translation Array 15 - TLA_MST_15_12[31:24]" group.long 0x1000++0x13 line.long 0x0 "MSTID_1_ENABLE,master ID enable" bitfld.long 0x0 31. "MSTID_1_ENABLE,Master ID CFG in [7:0] is enabled. 1 - compare master_id input with MSTID_CFG[7:0]. If the master_id matches preconfigured MSTID_CFG[7:0] the corresponding translation array(TLA) is selected 0 - ignore master_id input" "ignore master_id input,compare master_id input with MSTID_CFG[7:0]" hexmask.long.byte 0x0 0.--7. 1. "MSTID_CFG_1,Preconfigured Master ID" line.long 0x4 "TLA_MST_1_3_0,TLA Master mapping value" hexmask.long 0x4 0.--31. 1. "TLA_MST_1_3_0,Translation Array 0 - TLA_MST_3_0[7:0] Translation Array 1 - TLA_MST_3_0[15:8] Translation Array 2 - TLA_MST_3_0[23:16] Translation Array 3 - TLA_MST_3_0[31:24]" line.long 0x8 "TLA_MST_1_7_4,TLA Master mapping value" hexmask.long 0x8 0.--31. 1. "TLA_MST_1_7_4,Translation Array 4 - TLA_MST_7_4[7:0] Translation Array 5 - TLA_MST_7_4[15:8] Translation Array 6 - TLA_MST7_4[23:16] Translation Array 7 - TLA_MST_7_4[31:24]" line.long 0xC "TLA_MST_1_11_8,TLA Master mapping value" hexmask.long 0xC 0.--31. 1. "TLA_MST_1_11_8,Translation Array 8 - TLA_MST_11_8[7:0] Translation Array 9 - TLA_MST_11_8[15:8] Translation Array 10 - TLA_MST_11_8[23:16] Translation Array 11 - TLA_MST_11_8[31:24]" line.long 0x10 "TLA_MST_1_15_12,TLA Master mapping value" hexmask.long 0x10 0.--31. 1. "TLA_MST_1_15_12,Translation Array 12 - TLA_MST_15_12[7:0] Translation Array 13 - TLA_MST_15_12[15:8] Translation Array 14 - TLA_MST_15_12[23:16] Translation Array 15 - TLA_MST_15_12[31:24]" group.long 0x2000++0x13 line.long 0x0 "MSTID_2_ENABLE,master ID enable" bitfld.long 0x0 31. "MSTID_2_ENABLE,Master ID CFG in [7:0] is enabled. 1 - compare master_id input with MSTID_CFG[7:0]. If the master_id matches preconfigured MSTID_CFG[7:0] the corresponding translation array(TLA) is selected 0 - ignore master_id input" "ignore master_id input,compare master_id input with MSTID_CFG[7:0]" hexmask.long.byte 0x0 0.--7. 1. "MSTID_CFG_2,Preconfigured Master ID" line.long 0x4 "TLA_MST_2_3_0,TLA Master mapping value" hexmask.long 0x4 0.--31. 1. "TLA_MST_2_3_0,Translation Array 0 - TLA_MST_3_0[7:0] Translation Array 1 - TLA_MST_3_0[15:8] Translation Array 2 - TLA_MST_3_0[23:16] Translation Array 3 - TLA_MST_3_0[31:24]" line.long 0x8 "TLA_MST_2_7_4,TLA Master mapping value" hexmask.long 0x8 0.--31. 1. "TLA_MST_2_7_4,Translation Array 4 - TLA_MST_7_4[7:0] Translation Array 5 - TLA_MST_7_4[15:8] Translation Array 6 - TLA_MST7_4[23:16] Translation Array 7 - TLA_MST_7_4[31:24]" line.long 0xC "TLA_MST_2_11_8,TLA Master mapping value" hexmask.long 0xC 0.--31. 1. "TLA_MST_2_11_8,Translation Array 8 - TLA_MST_11_8[7:0] Translation Array 9 - TLA_MST_11_8[15:8] Translation Array 10 - TLA_MST_11_8[23:16] Translation Array 11 - TLA_MST_11_8[31:24]" line.long 0x10 "TLA_MST_2_15_12,TLA Master mapping value" hexmask.long 0x10 0.--31. 1. "TLA_MST_2_15_12,Translation Array 12 - TLA_MST_15_12[7:0] Translation Array 13 - TLA_MST_15_12[15:8] Translation Array 14 - TLA_MST_15_12[23:16] Translation Array 15 - TLA_MST_15_12[31:24]" tree.end tree "FTBU_VDSP" base ad:0x31C0D000 group.long 0x0++0x13 line.long 0x0 "MSTID_0_ENABLE,master ID enable" bitfld.long 0x0 31. "MSTID_0_ENABLE,Master ID CFG in [7:0] is enabled. 1 - compare master_id input with MSTID_CFG[7:0]. If the master_id matches preconfigured MSTID_CFG[7:0] the corresponding translation array(TLA) is selected 0 - ignore master_id input" "ignore master_id input,compare master_id input with MSTID_CFG[7:0]" hexmask.long.byte 0x0 0.--7. 1. "MSTID_CFG_0,Preconfigured Master ID" line.long 0x4 "TLA_MST_0_3_0,TLA Master mapping value" hexmask.long 0x4 0.--31. 1. "TLA_MST_0_3_0,Translation Array 0 - TLA_MST_3_0[7:0] Translation Array 1 - TLA_MST_3_0[15:8] Translation Array 2 - TLA_MST_3_0[23:16] Translation Array 3 - TLA_MST_3_0[31:24]" line.long 0x8 "TLA_MST_0_7_4,TLA Master mapping value" hexmask.long 0x8 0.--31. 1. "TLA_MST_0_7_4,Translation Array 4 - TLA_MST_7_4[7:0] Translation Array 5 - TLA_MST_7_4[15:8] Translation Array 6 - TLA_MST7_4[23:16] Translation Array 7 - TLA_MST_7_4[31:24]" line.long 0xC "TLA_MST_0_11_8,TLA Master mapping value" hexmask.long 0xC 0.--31. 1. "TLA_MST_0_11_8,Translation Array 8 - TLA_MST_11_8[7:0] Translation Array 9 - TLA_MST_11_8[15:8] Translation Array 10 - TLA_MST_11_8[23:16] Translation Array 11 - TLA_MST_11_8[31:24]" line.long 0x10 "TLA_MST_0_15_12,TLA Master mapping value" hexmask.long 0x10 0.--31. 1. "TLA_MST_0_15_12,Translation Array 12 - TLA_MST_15_12[7:0] Translation Array 13 - TLA_MST_15_12[15:8] Translation Array 14 - TLA_MST_15_12[23:16] Translation Array 15 - TLA_MST_15_12[31:24]" group.long 0x1000++0x13 line.long 0x0 "MSTID_1_ENABLE,master ID enable" bitfld.long 0x0 31. "MSTID_1_ENABLE,Master ID CFG in [7:0] is enabled. 1 - compare master_id input with MSTID_CFG[7:0]. If the master_id matches preconfigured MSTID_CFG[7:0] the corresponding translation array(TLA) is selected 0 - ignore master_id input" "ignore master_id input,compare master_id input with MSTID_CFG[7:0]" hexmask.long.byte 0x0 0.--7. 1. "MSTID_CFG_1,Preconfigured Master ID" line.long 0x4 "TLA_MST_1_3_0,TLA Master mapping value" hexmask.long 0x4 0.--31. 1. "TLA_MST_1_3_0,Translation Array 0 - TLA_MST_3_0[7:0] Translation Array 1 - TLA_MST_3_0[15:8] Translation Array 2 - TLA_MST_3_0[23:16] Translation Array 3 - TLA_MST_3_0[31:24]" line.long 0x8 "TLA_MST_1_7_4,TLA Master mapping value" hexmask.long 0x8 0.--31. 1. "TLA_MST_1_7_4,Translation Array 4 - TLA_MST_7_4[7:0] Translation Array 5 - TLA_MST_7_4[15:8] Translation Array 6 - TLA_MST7_4[23:16] Translation Array 7 - TLA_MST_7_4[31:24]" line.long 0xC "TLA_MST_1_11_8,TLA Master mapping value" hexmask.long 0xC 0.--31. 1. "TLA_MST_1_11_8,Translation Array 8 - TLA_MST_11_8[7:0] Translation Array 9 - TLA_MST_11_8[15:8] Translation Array 10 - TLA_MST_11_8[23:16] Translation Array 11 - TLA_MST_11_8[31:24]" line.long 0x10 "TLA_MST_1_15_12,TLA Master mapping value" hexmask.long 0x10 0.--31. 1. "TLA_MST_1_15_12,Translation Array 12 - TLA_MST_15_12[7:0] Translation Array 13 - TLA_MST_15_12[15:8] Translation Array 14 - TLA_MST_15_12[23:16] Translation Array 15 - TLA_MST_15_12[31:24]" group.long 0x2000++0x13 line.long 0x0 "MSTID_2_ENABLE,master ID enable" bitfld.long 0x0 31. "MSTID_2_ENABLE,Master ID CFG in [7:0] is enabled. 1 - compare master_id input with MSTID_CFG[7:0]. If the master_id matches preconfigured MSTID_CFG[7:0] the corresponding translation array(TLA) is selected 0 - ignore master_id input" "ignore master_id input,compare master_id input with MSTID_CFG[7:0]" hexmask.long.byte 0x0 0.--7. 1. "MSTID_CFG_2,Preconfigured Master ID" line.long 0x4 "TLA_MST_2_3_0,TLA Master mapping value" hexmask.long 0x4 0.--31. 1. "TLA_MST_2_3_0,Translation Array 0 - TLA_MST_3_0[7:0] Translation Array 1 - TLA_MST_3_0[15:8] Translation Array 2 - TLA_MST_3_0[23:16] Translation Array 3 - TLA_MST_3_0[31:24]" line.long 0x8 "TLA_MST_2_7_4,TLA Master mapping value" hexmask.long 0x8 0.--31. 1. "TLA_MST_2_7_4,Translation Array 4 - TLA_MST_7_4[7:0] Translation Array 5 - TLA_MST_7_4[15:8] Translation Array 6 - TLA_MST7_4[23:16] Translation Array 7 - TLA_MST_7_4[31:24]" line.long 0xC "TLA_MST_2_11_8,TLA Master mapping value" hexmask.long 0xC 0.--31. 1. "TLA_MST_2_11_8,Translation Array 8 - TLA_MST_11_8[7:0] Translation Array 9 - TLA_MST_11_8[15:8] Translation Array 10 - TLA_MST_11_8[23:16] Translation Array 11 - TLA_MST_11_8[31:24]" line.long 0x10 "TLA_MST_2_15_12,TLA Master mapping value" hexmask.long 0x10 0.--31. 1. "TLA_MST_2_15_12,Translation Array 12 - TLA_MST_15_12[7:0] Translation Array 13 - TLA_MST_15_12[15:8] Translation Array 14 - TLA_MST_15_12[23:16] Translation Array 15 - TLA_MST_15_12[31:24]" tree.end tree "FTBU_JPU_P0" base ad:0x31C0F000 group.long 0x0++0x13 line.long 0x0 "MSTID_0_ENABLE,master ID enable" bitfld.long 0x0 31. "MSTID_0_ENABLE,Master ID CFG in [7:0] is enabled. 1 - compare master_id input with MSTID_CFG[7:0]. If the master_id matches preconfigured MSTID_CFG[7:0] the corresponding translation array(TLA) is selected 0 - ignore master_id input" "ignore master_id input,compare master_id input with MSTID_CFG[7:0]" hexmask.long.byte 0x0 0.--7. 1. "MSTID_CFG_0,Preconfigured Master ID" line.long 0x4 "TLA_MST_0_3_0,TLA Master mapping value" hexmask.long 0x4 0.--31. 1. "TLA_MST_0_3_0,Translation Array 0 - TLA_MST_3_0[7:0] Translation Array 1 - TLA_MST_3_0[15:8] Translation Array 2 - TLA_MST_3_0[23:16] Translation Array 3 - TLA_MST_3_0[31:24]" line.long 0x8 "TLA_MST_0_7_4,TLA Master mapping value" hexmask.long 0x8 0.--31. 1. "TLA_MST_0_7_4,Translation Array 4 - TLA_MST_7_4[7:0] Translation Array 5 - TLA_MST_7_4[15:8] Translation Array 6 - TLA_MST7_4[23:16] Translation Array 7 - TLA_MST_7_4[31:24]" line.long 0xC "TLA_MST_0_11_8,TLA Master mapping value" hexmask.long 0xC 0.--31. 1. "TLA_MST_0_11_8,Translation Array 8 - TLA_MST_11_8[7:0] Translation Array 9 - TLA_MST_11_8[15:8] Translation Array 10 - TLA_MST_11_8[23:16] Translation Array 11 - TLA_MST_11_8[31:24]" line.long 0x10 "TLA_MST_0_15_12,TLA Master mapping value" hexmask.long 0x10 0.--31. 1. "TLA_MST_0_15_12,Translation Array 12 - TLA_MST_15_12[7:0] Translation Array 13 - TLA_MST_15_12[15:8] Translation Array 14 - TLA_MST_15_12[23:16] Translation Array 15 - TLA_MST_15_12[31:24]" group.long 0x1000++0x13 line.long 0x0 "MSTID_1_ENABLE,master ID enable" bitfld.long 0x0 31. "MSTID_1_ENABLE,Master ID CFG in [7:0] is enabled. 1 - compare master_id input with MSTID_CFG[7:0]. If the master_id matches preconfigured MSTID_CFG[7:0] the corresponding translation array(TLA) is selected 0 - ignore master_id input" "ignore master_id input,compare master_id input with MSTID_CFG[7:0]" hexmask.long.byte 0x0 0.--7. 1. "MSTID_CFG_1,Preconfigured Master ID" line.long 0x4 "TLA_MST_1_3_0,TLA Master mapping value" hexmask.long 0x4 0.--31. 1. "TLA_MST_1_3_0,Translation Array 0 - TLA_MST_3_0[7:0] Translation Array 1 - TLA_MST_3_0[15:8] Translation Array 2 - TLA_MST_3_0[23:16] Translation Array 3 - TLA_MST_3_0[31:24]" line.long 0x8 "TLA_MST_1_7_4,TLA Master mapping value" hexmask.long 0x8 0.--31. 1. "TLA_MST_1_7_4,Translation Array 4 - TLA_MST_7_4[7:0] Translation Array 5 - TLA_MST_7_4[15:8] Translation Array 6 - TLA_MST7_4[23:16] Translation Array 7 - TLA_MST_7_4[31:24]" line.long 0xC "TLA_MST_1_11_8,TLA Master mapping value" hexmask.long 0xC 0.--31. 1. "TLA_MST_1_11_8,Translation Array 8 - TLA_MST_11_8[7:0] Translation Array 9 - TLA_MST_11_8[15:8] Translation Array 10 - TLA_MST_11_8[23:16] Translation Array 11 - TLA_MST_11_8[31:24]" line.long 0x10 "TLA_MST_1_15_12,TLA Master mapping value" hexmask.long 0x10 0.--31. 1. "TLA_MST_1_15_12,Translation Array 12 - TLA_MST_15_12[7:0] Translation Array 13 - TLA_MST_15_12[15:8] Translation Array 14 - TLA_MST_15_12[23:16] Translation Array 15 - TLA_MST_15_12[31:24]" group.long 0x2000++0x13 line.long 0x0 "MSTID_2_ENABLE,master ID enable" bitfld.long 0x0 31. "MSTID_2_ENABLE,Master ID CFG in [7:0] is enabled. 1 - compare master_id input with MSTID_CFG[7:0]. If the master_id matches preconfigured MSTID_CFG[7:0] the corresponding translation array(TLA) is selected 0 - ignore master_id input" "ignore master_id input,compare master_id input with MSTID_CFG[7:0]" hexmask.long.byte 0x0 0.--7. 1. "MSTID_CFG_2,Preconfigured Master ID" line.long 0x4 "TLA_MST_2_3_0,TLA Master mapping value" hexmask.long 0x4 0.--31. 1. "TLA_MST_2_3_0,Translation Array 0 - TLA_MST_3_0[7:0] Translation Array 1 - TLA_MST_3_0[15:8] Translation Array 2 - TLA_MST_3_0[23:16] Translation Array 3 - TLA_MST_3_0[31:24]" line.long 0x8 "TLA_MST_2_7_4,TLA Master mapping value" hexmask.long 0x8 0.--31. 1. "TLA_MST_2_7_4,Translation Array 4 - TLA_MST_7_4[7:0] Translation Array 5 - TLA_MST_7_4[15:8] Translation Array 6 - TLA_MST7_4[23:16] Translation Array 7 - TLA_MST_7_4[31:24]" line.long 0xC "TLA_MST_2_11_8,TLA Master mapping value" hexmask.long 0xC 0.--31. 1. "TLA_MST_2_11_8,Translation Array 8 - TLA_MST_11_8[7:0] Translation Array 9 - TLA_MST_11_8[15:8] Translation Array 10 - TLA_MST_11_8[23:16] Translation Array 11 - TLA_MST_11_8[31:24]" line.long 0x10 "TLA_MST_2_15_12,TLA Master mapping value" hexmask.long 0x10 0.--31. 1. "TLA_MST_2_15_12,Translation Array 12 - TLA_MST_15_12[7:0] Translation Array 13 - TLA_MST_15_12[15:8] Translation Array 14 - TLA_MST_15_12[23:16] Translation Array 15 - TLA_MST_15_12[31:24]" tree.end tree "FTBU_VPU2_P0" base ad:0x31C10000 group.long 0x0++0x13 line.long 0x0 "MSTID_0_ENABLE,master ID enable" bitfld.long 0x0 31. "MSTID_0_ENABLE,Master ID CFG in [7:0] is enabled. 1 - compare master_id input with MSTID_CFG[7:0]. If the master_id matches preconfigured MSTID_CFG[7:0] the corresponding translation array(TLA) is selected 0 - ignore master_id input" "ignore master_id input,compare master_id input with MSTID_CFG[7:0]" hexmask.long.byte 0x0 0.--7. 1. "MSTID_CFG_0,Preconfigured Master ID" line.long 0x4 "TLA_MST_0_3_0,TLA Master mapping value" hexmask.long 0x4 0.--31. 1. "TLA_MST_0_3_0,Translation Array 0 - TLA_MST_3_0[7:0] Translation Array 1 - TLA_MST_3_0[15:8] Translation Array 2 - TLA_MST_3_0[23:16] Translation Array 3 - TLA_MST_3_0[31:24]" line.long 0x8 "TLA_MST_0_7_4,TLA Master mapping value" hexmask.long 0x8 0.--31. 1. "TLA_MST_0_7_4,Translation Array 4 - TLA_MST_7_4[7:0] Translation Array 5 - TLA_MST_7_4[15:8] Translation Array 6 - TLA_MST7_4[23:16] Translation Array 7 - TLA_MST_7_4[31:24]" line.long 0xC "TLA_MST_0_11_8,TLA Master mapping value" hexmask.long 0xC 0.--31. 1. "TLA_MST_0_11_8,Translation Array 8 - TLA_MST_11_8[7:0] Translation Array 9 - TLA_MST_11_8[15:8] Translation Array 10 - TLA_MST_11_8[23:16] Translation Array 11 - TLA_MST_11_8[31:24]" line.long 0x10 "TLA_MST_0_15_12,TLA Master mapping value" hexmask.long 0x10 0.--31. 1. "TLA_MST_0_15_12,Translation Array 12 - TLA_MST_15_12[7:0] Translation Array 13 - TLA_MST_15_12[15:8] Translation Array 14 - TLA_MST_15_12[23:16] Translation Array 15 - TLA_MST_15_12[31:24]" group.long 0x1000++0x13 line.long 0x0 "MSTID_1_ENABLE,master ID enable" bitfld.long 0x0 31. "MSTID_1_ENABLE,Master ID CFG in [7:0] is enabled. 1 - compare master_id input with MSTID_CFG[7:0]. If the master_id matches preconfigured MSTID_CFG[7:0] the corresponding translation array(TLA) is selected 0 - ignore master_id input" "ignore master_id input,compare master_id input with MSTID_CFG[7:0]" hexmask.long.byte 0x0 0.--7. 1. "MSTID_CFG_1,Preconfigured Master ID" line.long 0x4 "TLA_MST_1_3_0,TLA Master mapping value" hexmask.long 0x4 0.--31. 1. "TLA_MST_1_3_0,Translation Array 0 - TLA_MST_3_0[7:0] Translation Array 1 - TLA_MST_3_0[15:8] Translation Array 2 - TLA_MST_3_0[23:16] Translation Array 3 - TLA_MST_3_0[31:24]" line.long 0x8 "TLA_MST_1_7_4,TLA Master mapping value" hexmask.long 0x8 0.--31. 1. "TLA_MST_1_7_4,Translation Array 4 - TLA_MST_7_4[7:0] Translation Array 5 - TLA_MST_7_4[15:8] Translation Array 6 - TLA_MST7_4[23:16] Translation Array 7 - TLA_MST_7_4[31:24]" line.long 0xC "TLA_MST_1_11_8,TLA Master mapping value" hexmask.long 0xC 0.--31. 1. "TLA_MST_1_11_8,Translation Array 8 - TLA_MST_11_8[7:0] Translation Array 9 - TLA_MST_11_8[15:8] Translation Array 10 - TLA_MST_11_8[23:16] Translation Array 11 - TLA_MST_11_8[31:24]" line.long 0x10 "TLA_MST_1_15_12,TLA Master mapping value" hexmask.long 0x10 0.--31. 1. "TLA_MST_1_15_12,Translation Array 12 - TLA_MST_15_12[7:0] Translation Array 13 - TLA_MST_15_12[15:8] Translation Array 14 - TLA_MST_15_12[23:16] Translation Array 15 - TLA_MST_15_12[31:24]" group.long 0x2000++0x13 line.long 0x0 "MSTID_2_ENABLE,master ID enable" bitfld.long 0x0 31. "MSTID_2_ENABLE,Master ID CFG in [7:0] is enabled. 1 - compare master_id input with MSTID_CFG[7:0]. If the master_id matches preconfigured MSTID_CFG[7:0] the corresponding translation array(TLA) is selected 0 - ignore master_id input" "ignore master_id input,compare master_id input with MSTID_CFG[7:0]" hexmask.long.byte 0x0 0.--7. 1. "MSTID_CFG_2,Preconfigured Master ID" line.long 0x4 "TLA_MST_2_3_0,TLA Master mapping value" hexmask.long 0x4 0.--31. 1. "TLA_MST_2_3_0,Translation Array 0 - TLA_MST_3_0[7:0] Translation Array 1 - TLA_MST_3_0[15:8] Translation Array 2 - TLA_MST_3_0[23:16] Translation Array 3 - TLA_MST_3_0[31:24]" line.long 0x8 "TLA_MST_2_7_4,TLA Master mapping value" hexmask.long 0x8 0.--31. 1. "TLA_MST_2_7_4,Translation Array 4 - TLA_MST_7_4[7:0] Translation Array 5 - TLA_MST_7_4[15:8] Translation Array 6 - TLA_MST7_4[23:16] Translation Array 7 - TLA_MST_7_4[31:24]" line.long 0xC "TLA_MST_2_11_8,TLA Master mapping value" hexmask.long 0xC 0.--31. 1. "TLA_MST_2_11_8,Translation Array 8 - TLA_MST_11_8[7:0] Translation Array 9 - TLA_MST_11_8[15:8] Translation Array 10 - TLA_MST_11_8[23:16] Translation Array 11 - TLA_MST_11_8[31:24]" line.long 0x10 "TLA_MST_2_15_12,TLA Master mapping value" hexmask.long 0x10 0.--31. 1. "TLA_MST_2_15_12,Translation Array 12 - TLA_MST_15_12[7:0] Translation Array 13 - TLA_MST_15_12[15:8] Translation Array 14 - TLA_MST_15_12[23:16] Translation Array 15 - TLA_MST_15_12[31:24]" tree.end tree "FTBU_VPU1_P0" base ad:0x31C11000 group.long 0x0++0x13 line.long 0x0 "MSTID_0_ENABLE,master ID enable" bitfld.long 0x0 31. "MSTID_0_ENABLE,Master ID CFG in [7:0] is enabled. 1 - compare master_id input with MSTID_CFG[7:0]. If the master_id matches preconfigured MSTID_CFG[7:0] the corresponding translation array(TLA) is selected 0 - ignore master_id input" "ignore master_id input,compare master_id input with MSTID_CFG[7:0]" hexmask.long.byte 0x0 0.--7. 1. "MSTID_CFG_0,Preconfigured Master ID" line.long 0x4 "TLA_MST_0_3_0,TLA Master mapping value" hexmask.long 0x4 0.--31. 1. "TLA_MST_0_3_0,Translation Array 0 - TLA_MST_3_0[7:0] Translation Array 1 - TLA_MST_3_0[15:8] Translation Array 2 - TLA_MST_3_0[23:16] Translation Array 3 - TLA_MST_3_0[31:24]" line.long 0x8 "TLA_MST_0_7_4,TLA Master mapping value" hexmask.long 0x8 0.--31. 1. "TLA_MST_0_7_4,Translation Array 4 - TLA_MST_7_4[7:0] Translation Array 5 - TLA_MST_7_4[15:8] Translation Array 6 - TLA_MST7_4[23:16] Translation Array 7 - TLA_MST_7_4[31:24]" line.long 0xC "TLA_MST_0_11_8,TLA Master mapping value" hexmask.long 0xC 0.--31. 1. "TLA_MST_0_11_8,Translation Array 8 - TLA_MST_11_8[7:0] Translation Array 9 - TLA_MST_11_8[15:8] Translation Array 10 - TLA_MST_11_8[23:16] Translation Array 11 - TLA_MST_11_8[31:24]" line.long 0x10 "TLA_MST_0_15_12,TLA Master mapping value" hexmask.long 0x10 0.--31. 1. "TLA_MST_0_15_12,Translation Array 12 - TLA_MST_15_12[7:0] Translation Array 13 - TLA_MST_15_12[15:8] Translation Array 14 - TLA_MST_15_12[23:16] Translation Array 15 - TLA_MST_15_12[31:24]" group.long 0x1000++0x13 line.long 0x0 "MSTID_1_ENABLE,master ID enable" bitfld.long 0x0 31. "MSTID_1_ENABLE,Master ID CFG in [7:0] is enabled. 1 - compare master_id input with MSTID_CFG[7:0]. If the master_id matches preconfigured MSTID_CFG[7:0] the corresponding translation array(TLA) is selected 0 - ignore master_id input" "ignore master_id input,compare master_id input with MSTID_CFG[7:0]" hexmask.long.byte 0x0 0.--7. 1. "MSTID_CFG_1,Preconfigured Master ID" line.long 0x4 "TLA_MST_1_3_0,TLA Master mapping value" hexmask.long 0x4 0.--31. 1. "TLA_MST_1_3_0,Translation Array 0 - TLA_MST_3_0[7:0] Translation Array 1 - TLA_MST_3_0[15:8] Translation Array 2 - TLA_MST_3_0[23:16] Translation Array 3 - TLA_MST_3_0[31:24]" line.long 0x8 "TLA_MST_1_7_4,TLA Master mapping value" hexmask.long 0x8 0.--31. 1. "TLA_MST_1_7_4,Translation Array 4 - TLA_MST_7_4[7:0] Translation Array 5 - TLA_MST_7_4[15:8] Translation Array 6 - TLA_MST7_4[23:16] Translation Array 7 - TLA_MST_7_4[31:24]" line.long 0xC "TLA_MST_1_11_8,TLA Master mapping value" hexmask.long 0xC 0.--31. 1. "TLA_MST_1_11_8,Translation Array 8 - TLA_MST_11_8[7:0] Translation Array 9 - TLA_MST_11_8[15:8] Translation Array 10 - TLA_MST_11_8[23:16] Translation Array 11 - TLA_MST_11_8[31:24]" line.long 0x10 "TLA_MST_1_15_12,TLA Master mapping value" hexmask.long 0x10 0.--31. 1. "TLA_MST_1_15_12,Translation Array 12 - TLA_MST_15_12[7:0] Translation Array 13 - TLA_MST_15_12[15:8] Translation Array 14 - TLA_MST_15_12[23:16] Translation Array 15 - TLA_MST_15_12[31:24]" group.long 0x2000++0x13 line.long 0x0 "MSTID_2_ENABLE,master ID enable" bitfld.long 0x0 31. "MSTID_2_ENABLE,Master ID CFG in [7:0] is enabled. 1 - compare master_id input with MSTID_CFG[7:0]. If the master_id matches preconfigured MSTID_CFG[7:0] the corresponding translation array(TLA) is selected 0 - ignore master_id input" "ignore master_id input,compare master_id input with MSTID_CFG[7:0]" hexmask.long.byte 0x0 0.--7. 1. "MSTID_CFG_2,Preconfigured Master ID" line.long 0x4 "TLA_MST_2_3_0,TLA Master mapping value" hexmask.long 0x4 0.--31. 1. "TLA_MST_2_3_0,Translation Array 0 - TLA_MST_3_0[7:0] Translation Array 1 - TLA_MST_3_0[15:8] Translation Array 2 - TLA_MST_3_0[23:16] Translation Array 3 - TLA_MST_3_0[31:24]" line.long 0x8 "TLA_MST_2_7_4,TLA Master mapping value" hexmask.long 0x8 0.--31. 1. "TLA_MST_2_7_4,Translation Array 4 - TLA_MST_7_4[7:0] Translation Array 5 - TLA_MST_7_4[15:8] Translation Array 6 - TLA_MST7_4[23:16] Translation Array 7 - TLA_MST_7_4[31:24]" line.long 0xC "TLA_MST_2_11_8,TLA Master mapping value" hexmask.long 0xC 0.--31. 1. "TLA_MST_2_11_8,Translation Array 8 - TLA_MST_11_8[7:0] Translation Array 9 - TLA_MST_11_8[15:8] Translation Array 10 - TLA_MST_11_8[23:16] Translation Array 11 - TLA_MST_11_8[31:24]" line.long 0x10 "TLA_MST_2_15_12,TLA Master mapping value" hexmask.long 0x10 0.--31. 1. "TLA_MST_2_15_12,Translation Array 12 - TLA_MST_15_12[7:0] Translation Array 13 - TLA_MST_15_12[15:8] Translation Array 14 - TLA_MST_15_12[23:16] Translation Array 15 - TLA_MST_15_12[31:24]" tree.end tree "FTBU_JPU_P1" base ad:0x31C13000 group.long 0x0++0x13 line.long 0x0 "MSTID_0_ENABLE,master ID enable" bitfld.long 0x0 31. "MSTID_0_ENABLE,Master ID CFG in [7:0] is enabled. 1 - compare master_id input with MSTID_CFG[7:0]. If the master_id matches preconfigured MSTID_CFG[7:0] the corresponding translation array(TLA) is selected 0 - ignore master_id input" "ignore master_id input,compare master_id input with MSTID_CFG[7:0]" hexmask.long.byte 0x0 0.--7. 1. "MSTID_CFG_0,Preconfigured Master ID" line.long 0x4 "TLA_MST_0_3_0,TLA Master mapping value" hexmask.long 0x4 0.--31. 1. "TLA_MST_0_3_0,Translation Array 0 - TLA_MST_3_0[7:0] Translation Array 1 - TLA_MST_3_0[15:8] Translation Array 2 - TLA_MST_3_0[23:16] Translation Array 3 - TLA_MST_3_0[31:24]" line.long 0x8 "TLA_MST_0_7_4,TLA Master mapping value" hexmask.long 0x8 0.--31. 1. "TLA_MST_0_7_4,Translation Array 4 - TLA_MST_7_4[7:0] Translation Array 5 - TLA_MST_7_4[15:8] Translation Array 6 - TLA_MST7_4[23:16] Translation Array 7 - TLA_MST_7_4[31:24]" line.long 0xC "TLA_MST_0_11_8,TLA Master mapping value" hexmask.long 0xC 0.--31. 1. "TLA_MST_0_11_8,Translation Array 8 - TLA_MST_11_8[7:0] Translation Array 9 - TLA_MST_11_8[15:8] Translation Array 10 - TLA_MST_11_8[23:16] Translation Array 11 - TLA_MST_11_8[31:24]" line.long 0x10 "TLA_MST_0_15_12,TLA Master mapping value" hexmask.long 0x10 0.--31. 1. "TLA_MST_0_15_12,Translation Array 12 - TLA_MST_15_12[7:0] Translation Array 13 - TLA_MST_15_12[15:8] Translation Array 14 - TLA_MST_15_12[23:16] Translation Array 15 - TLA_MST_15_12[31:24]" group.long 0x1000++0x13 line.long 0x0 "MSTID_1_ENABLE,master ID enable" bitfld.long 0x0 31. "MSTID_1_ENABLE,Master ID CFG in [7:0] is enabled. 1 - compare master_id input with MSTID_CFG[7:0]. If the master_id matches preconfigured MSTID_CFG[7:0] the corresponding translation array(TLA) is selected 0 - ignore master_id input" "ignore master_id input,compare master_id input with MSTID_CFG[7:0]" hexmask.long.byte 0x0 0.--7. 1. "MSTID_CFG_1,Preconfigured Master ID" line.long 0x4 "TLA_MST_1_3_0,TLA Master mapping value" hexmask.long 0x4 0.--31. 1. "TLA_MST_1_3_0,Translation Array 0 - TLA_MST_3_0[7:0] Translation Array 1 - TLA_MST_3_0[15:8] Translation Array 2 - TLA_MST_3_0[23:16] Translation Array 3 - TLA_MST_3_0[31:24]" line.long 0x8 "TLA_MST_1_7_4,TLA Master mapping value" hexmask.long 0x8 0.--31. 1. "TLA_MST_1_7_4,Translation Array 4 - TLA_MST_7_4[7:0] Translation Array 5 - TLA_MST_7_4[15:8] Translation Array 6 - TLA_MST7_4[23:16] Translation Array 7 - TLA_MST_7_4[31:24]" line.long 0xC "TLA_MST_1_11_8,TLA Master mapping value" hexmask.long 0xC 0.--31. 1. "TLA_MST_1_11_8,Translation Array 8 - TLA_MST_11_8[7:0] Translation Array 9 - TLA_MST_11_8[15:8] Translation Array 10 - TLA_MST_11_8[23:16] Translation Array 11 - TLA_MST_11_8[31:24]" line.long 0x10 "TLA_MST_1_15_12,TLA Master mapping value" hexmask.long 0x10 0.--31. 1. "TLA_MST_1_15_12,Translation Array 12 - TLA_MST_15_12[7:0] Translation Array 13 - TLA_MST_15_12[15:8] Translation Array 14 - TLA_MST_15_12[23:16] Translation Array 15 - TLA_MST_15_12[31:24]" group.long 0x2000++0x13 line.long 0x0 "MSTID_2_ENABLE,master ID enable" bitfld.long 0x0 31. "MSTID_2_ENABLE,Master ID CFG in [7:0] is enabled. 1 - compare master_id input with MSTID_CFG[7:0]. If the master_id matches preconfigured MSTID_CFG[7:0] the corresponding translation array(TLA) is selected 0 - ignore master_id input" "ignore master_id input,compare master_id input with MSTID_CFG[7:0]" hexmask.long.byte 0x0 0.--7. 1. "MSTID_CFG_2,Preconfigured Master ID" line.long 0x4 "TLA_MST_2_3_0,TLA Master mapping value" hexmask.long 0x4 0.--31. 1. "TLA_MST_2_3_0,Translation Array 0 - TLA_MST_3_0[7:0] Translation Array 1 - TLA_MST_3_0[15:8] Translation Array 2 - TLA_MST_3_0[23:16] Translation Array 3 - TLA_MST_3_0[31:24]" line.long 0x8 "TLA_MST_2_7_4,TLA Master mapping value" hexmask.long 0x8 0.--31. 1. "TLA_MST_2_7_4,Translation Array 4 - TLA_MST_7_4[7:0] Translation Array 5 - TLA_MST_7_4[15:8] Translation Array 6 - TLA_MST7_4[23:16] Translation Array 7 - TLA_MST_7_4[31:24]" line.long 0xC "TLA_MST_2_11_8,TLA Master mapping value" hexmask.long 0xC 0.--31. 1. "TLA_MST_2_11_8,Translation Array 8 - TLA_MST_11_8[7:0] Translation Array 9 - TLA_MST_11_8[15:8] Translation Array 10 - TLA_MST_11_8[23:16] Translation Array 11 - TLA_MST_11_8[31:24]" line.long 0x10 "TLA_MST_2_15_12,TLA Master mapping value" hexmask.long 0x10 0.--31. 1. "TLA_MST_2_15_12,Translation Array 12 - TLA_MST_15_12[7:0] Translation Array 13 - TLA_MST_15_12[15:8] Translation Array 14 - TLA_MST_15_12[23:16] Translation Array 15 - TLA_MST_15_12[31:24]" tree.end tree "FTBU_VPU2_P1" base ad:0x31C14000 group.long 0x0++0x13 line.long 0x0 "MSTID_0_ENABLE,master ID enable" bitfld.long 0x0 31. "MSTID_0_ENABLE,Master ID CFG in [7:0] is enabled. 1 - compare master_id input with MSTID_CFG[7:0]. If the master_id matches preconfigured MSTID_CFG[7:0] the corresponding translation array(TLA) is selected 0 - ignore master_id input" "ignore master_id input,compare master_id input with MSTID_CFG[7:0]" hexmask.long.byte 0x0 0.--7. 1. "MSTID_CFG_0,Preconfigured Master ID" line.long 0x4 "TLA_MST_0_3_0,TLA Master mapping value" hexmask.long 0x4 0.--31. 1. "TLA_MST_0_3_0,Translation Array 0 - TLA_MST_3_0[7:0] Translation Array 1 - TLA_MST_3_0[15:8] Translation Array 2 - TLA_MST_3_0[23:16] Translation Array 3 - TLA_MST_3_0[31:24]" line.long 0x8 "TLA_MST_0_7_4,TLA Master mapping value" hexmask.long 0x8 0.--31. 1. "TLA_MST_0_7_4,Translation Array 4 - TLA_MST_7_4[7:0] Translation Array 5 - TLA_MST_7_4[15:8] Translation Array 6 - TLA_MST7_4[23:16] Translation Array 7 - TLA_MST_7_4[31:24]" line.long 0xC "TLA_MST_0_11_8,TLA Master mapping value" hexmask.long 0xC 0.--31. 1. "TLA_MST_0_11_8,Translation Array 8 - TLA_MST_11_8[7:0] Translation Array 9 - TLA_MST_11_8[15:8] Translation Array 10 - TLA_MST_11_8[23:16] Translation Array 11 - TLA_MST_11_8[31:24]" line.long 0x10 "TLA_MST_0_15_12,TLA Master mapping value" hexmask.long 0x10 0.--31. 1. "TLA_MST_0_15_12,Translation Array 12 - TLA_MST_15_12[7:0] Translation Array 13 - TLA_MST_15_12[15:8] Translation Array 14 - TLA_MST_15_12[23:16] Translation Array 15 - TLA_MST_15_12[31:24]" group.long 0x1000++0x13 line.long 0x0 "MSTID_1_ENABLE,master ID enable" bitfld.long 0x0 31. "MSTID_1_ENABLE,Master ID CFG in [7:0] is enabled. 1 - compare master_id input with MSTID_CFG[7:0]. If the master_id matches preconfigured MSTID_CFG[7:0] the corresponding translation array(TLA) is selected 0 - ignore master_id input" "ignore master_id input,compare master_id input with MSTID_CFG[7:0]" hexmask.long.byte 0x0 0.--7. 1. "MSTID_CFG_1,Preconfigured Master ID" line.long 0x4 "TLA_MST_1_3_0,TLA Master mapping value" hexmask.long 0x4 0.--31. 1. "TLA_MST_1_3_0,Translation Array 0 - TLA_MST_3_0[7:0] Translation Array 1 - TLA_MST_3_0[15:8] Translation Array 2 - TLA_MST_3_0[23:16] Translation Array 3 - TLA_MST_3_0[31:24]" line.long 0x8 "TLA_MST_1_7_4,TLA Master mapping value" hexmask.long 0x8 0.--31. 1. "TLA_MST_1_7_4,Translation Array 4 - TLA_MST_7_4[7:0] Translation Array 5 - TLA_MST_7_4[15:8] Translation Array 6 - TLA_MST7_4[23:16] Translation Array 7 - TLA_MST_7_4[31:24]" line.long 0xC "TLA_MST_1_11_8,TLA Master mapping value" hexmask.long 0xC 0.--31. 1. "TLA_MST_1_11_8,Translation Array 8 - TLA_MST_11_8[7:0] Translation Array 9 - TLA_MST_11_8[15:8] Translation Array 10 - TLA_MST_11_8[23:16] Translation Array 11 - TLA_MST_11_8[31:24]" line.long 0x10 "TLA_MST_1_15_12,TLA Master mapping value" hexmask.long 0x10 0.--31. 1. "TLA_MST_1_15_12,Translation Array 12 - TLA_MST_15_12[7:0] Translation Array 13 - TLA_MST_15_12[15:8] Translation Array 14 - TLA_MST_15_12[23:16] Translation Array 15 - TLA_MST_15_12[31:24]" group.long 0x2000++0x13 line.long 0x0 "MSTID_2_ENABLE,master ID enable" bitfld.long 0x0 31. "MSTID_2_ENABLE,Master ID CFG in [7:0] is enabled. 1 - compare master_id input with MSTID_CFG[7:0]. If the master_id matches preconfigured MSTID_CFG[7:0] the corresponding translation array(TLA) is selected 0 - ignore master_id input" "ignore master_id input,compare master_id input with MSTID_CFG[7:0]" hexmask.long.byte 0x0 0.--7. 1. "MSTID_CFG_2,Preconfigured Master ID" line.long 0x4 "TLA_MST_2_3_0,TLA Master mapping value" hexmask.long 0x4 0.--31. 1. "TLA_MST_2_3_0,Translation Array 0 - TLA_MST_3_0[7:0] Translation Array 1 - TLA_MST_3_0[15:8] Translation Array 2 - TLA_MST_3_0[23:16] Translation Array 3 - TLA_MST_3_0[31:24]" line.long 0x8 "TLA_MST_2_7_4,TLA Master mapping value" hexmask.long 0x8 0.--31. 1. "TLA_MST_2_7_4,Translation Array 4 - TLA_MST_7_4[7:0] Translation Array 5 - TLA_MST_7_4[15:8] Translation Array 6 - TLA_MST7_4[23:16] Translation Array 7 - TLA_MST_7_4[31:24]" line.long 0xC "TLA_MST_2_11_8,TLA Master mapping value" hexmask.long 0xC 0.--31. 1. "TLA_MST_2_11_8,Translation Array 8 - TLA_MST_11_8[7:0] Translation Array 9 - TLA_MST_11_8[15:8] Translation Array 10 - TLA_MST_11_8[23:16] Translation Array 11 - TLA_MST_11_8[31:24]" line.long 0x10 "TLA_MST_2_15_12,TLA Master mapping value" hexmask.long 0x10 0.--31. 1. "TLA_MST_2_15_12,Translation Array 12 - TLA_MST_15_12[7:0] Translation Array 13 - TLA_MST_15_12[15:8] Translation Array 14 - TLA_MST_15_12[23:16] Translation Array 15 - TLA_MST_15_12[31:24]" tree.end tree "FTBU_VPU1_P1" base ad:0x31C15000 group.long 0x0++0x13 line.long 0x0 "MSTID_0_ENABLE,master ID enable" bitfld.long 0x0 31. "MSTID_0_ENABLE,Master ID CFG in [7:0] is enabled. 1 - compare master_id input with MSTID_CFG[7:0]. If the master_id matches preconfigured MSTID_CFG[7:0] the corresponding translation array(TLA) is selected 0 - ignore master_id input" "ignore master_id input,compare master_id input with MSTID_CFG[7:0]" hexmask.long.byte 0x0 0.--7. 1. "MSTID_CFG_0,Preconfigured Master ID" line.long 0x4 "TLA_MST_0_3_0,TLA Master mapping value" hexmask.long 0x4 0.--31. 1. "TLA_MST_0_3_0,Translation Array 0 - TLA_MST_3_0[7:0] Translation Array 1 - TLA_MST_3_0[15:8] Translation Array 2 - TLA_MST_3_0[23:16] Translation Array 3 - TLA_MST_3_0[31:24]" line.long 0x8 "TLA_MST_0_7_4,TLA Master mapping value" hexmask.long 0x8 0.--31. 1. "TLA_MST_0_7_4,Translation Array 4 - TLA_MST_7_4[7:0] Translation Array 5 - TLA_MST_7_4[15:8] Translation Array 6 - TLA_MST7_4[23:16] Translation Array 7 - TLA_MST_7_4[31:24]" line.long 0xC "TLA_MST_0_11_8,TLA Master mapping value" hexmask.long 0xC 0.--31. 1. "TLA_MST_0_11_8,Translation Array 8 - TLA_MST_11_8[7:0] Translation Array 9 - TLA_MST_11_8[15:8] Translation Array 10 - TLA_MST_11_8[23:16] Translation Array 11 - TLA_MST_11_8[31:24]" line.long 0x10 "TLA_MST_0_15_12,TLA Master mapping value" hexmask.long 0x10 0.--31. 1. "TLA_MST_0_15_12,Translation Array 12 - TLA_MST_15_12[7:0] Translation Array 13 - TLA_MST_15_12[15:8] Translation Array 14 - TLA_MST_15_12[23:16] Translation Array 15 - TLA_MST_15_12[31:24]" group.long 0x1000++0x13 line.long 0x0 "MSTID_1_ENABLE,master ID enable" bitfld.long 0x0 31. "MSTID_1_ENABLE,Master ID CFG in [7:0] is enabled. 1 - compare master_id input with MSTID_CFG[7:0]. If the master_id matches preconfigured MSTID_CFG[7:0] the corresponding translation array(TLA) is selected 0 - ignore master_id input" "ignore master_id input,compare master_id input with MSTID_CFG[7:0]" hexmask.long.byte 0x0 0.--7. 1. "MSTID_CFG_1,Preconfigured Master ID" line.long 0x4 "TLA_MST_1_3_0,TLA Master mapping value" hexmask.long 0x4 0.--31. 1. "TLA_MST_1_3_0,Translation Array 0 - TLA_MST_3_0[7:0] Translation Array 1 - TLA_MST_3_0[15:8] Translation Array 2 - TLA_MST_3_0[23:16] Translation Array 3 - TLA_MST_3_0[31:24]" line.long 0x8 "TLA_MST_1_7_4,TLA Master mapping value" hexmask.long 0x8 0.--31. 1. "TLA_MST_1_7_4,Translation Array 4 - TLA_MST_7_4[7:0] Translation Array 5 - TLA_MST_7_4[15:8] Translation Array 6 - TLA_MST7_4[23:16] Translation Array 7 - TLA_MST_7_4[31:24]" line.long 0xC "TLA_MST_1_11_8,TLA Master mapping value" hexmask.long 0xC 0.--31. 1. "TLA_MST_1_11_8,Translation Array 8 - TLA_MST_11_8[7:0] Translation Array 9 - TLA_MST_11_8[15:8] Translation Array 10 - TLA_MST_11_8[23:16] Translation Array 11 - TLA_MST_11_8[31:24]" line.long 0x10 "TLA_MST_1_15_12,TLA Master mapping value" hexmask.long 0x10 0.--31. 1. "TLA_MST_1_15_12,Translation Array 12 - TLA_MST_15_12[7:0] Translation Array 13 - TLA_MST_15_12[15:8] Translation Array 14 - TLA_MST_15_12[23:16] Translation Array 15 - TLA_MST_15_12[31:24]" group.long 0x2000++0x13 line.long 0x0 "MSTID_2_ENABLE,master ID enable" bitfld.long 0x0 31. "MSTID_2_ENABLE,Master ID CFG in [7:0] is enabled. 1 - compare master_id input with MSTID_CFG[7:0]. If the master_id matches preconfigured MSTID_CFG[7:0] the corresponding translation array(TLA) is selected 0 - ignore master_id input" "ignore master_id input,compare master_id input with MSTID_CFG[7:0]" hexmask.long.byte 0x0 0.--7. 1. "MSTID_CFG_2,Preconfigured Master ID" line.long 0x4 "TLA_MST_2_3_0,TLA Master mapping value" hexmask.long 0x4 0.--31. 1. "TLA_MST_2_3_0,Translation Array 0 - TLA_MST_3_0[7:0] Translation Array 1 - TLA_MST_3_0[15:8] Translation Array 2 - TLA_MST_3_0[23:16] Translation Array 3 - TLA_MST_3_0[31:24]" line.long 0x8 "TLA_MST_2_7_4,TLA Master mapping value" hexmask.long 0x8 0.--31. 1. "TLA_MST_2_7_4,Translation Array 4 - TLA_MST_7_4[7:0] Translation Array 5 - TLA_MST_7_4[15:8] Translation Array 6 - TLA_MST7_4[23:16] Translation Array 7 - TLA_MST_7_4[31:24]" line.long 0xC "TLA_MST_2_11_8,TLA Master mapping value" hexmask.long 0xC 0.--31. 1. "TLA_MST_2_11_8,Translation Array 8 - TLA_MST_11_8[7:0] Translation Array 9 - TLA_MST_11_8[15:8] Translation Array 10 - TLA_MST_11_8[23:16] Translation Array 11 - TLA_MST_11_8[31:24]" line.long 0x10 "TLA_MST_2_15_12,TLA Master mapping value" hexmask.long 0x10 0.--31. 1. "TLA_MST_2_15_12,Translation Array 12 - TLA_MST_15_12[7:0] Translation Array 13 - TLA_MST_15_12[15:8] Translation Array 14 - TLA_MST_15_12[23:16] Translation Array 15 - TLA_MST_15_12[31:24]" tree.end endif tree.end tree "CANFD (Controller Area Network with Flexible Data-Rate)" sif (CORENAME()=="CORTEXR5F") repeat 8. (increment 1. 1.) (list ad:0xF0030000 ad:0xF0040000 ad:0xF0050000 ad:0xF0060000 ad:0xF0A80000 ad:0xF0A90000 ad:0xF0AA0000 ad:0xF0AB0000) tree "CANFD$1" base $2 group.long 0x0++0xB line.long 0x0 "CAN_MCR,CAN_MCR defines global system configurations. such as the module operation modes and the maximum message buffer configuration." bitfld.long 0x0 31. "MDIS,Module Disable - Disables or enables the FlexCAN module: - 1: Disable the FlexCAN module. - 0: Enable the FlexCAN module. When disabled the FlexCAN disables the clocks to the PE and CHI submodules. MDIS is not affected by soft reset." "Enable the FlexCAN module,Disable the FlexCAN module" bitfld.long 0x0 30. "FRZ,Freeze Enable: - 1: Enabled to enter Freeze mode. - 0: Not enabled to enter Freeze mode. The FRZ bit specifies the FlexCAN behavior when CAN_MCR.HALT is set or when Debug mode is requested at chip level. When FRZ is asserted the FlexCAN is enabled.." "Not enabled to enter Freeze mode,Enabled to enter Freeze mode" newline bitfld.long 0x0 29. "RFEN,Legacy Rx FIFO Enable - Enables or disables the Legacy Rx FIFO feature: - 1: Enable Legacy Rx FIFO. - 0: Disable Legacy Rx FIFO. When RFEN is set MBs 0-5 cannot be used for normal reception and transmission because the corresponding memory region.." "Disable Legacy Rx FIFO,Enable Legacy Rx FIFO" bitfld.long 0x0 28. "HALT,Halt FlexCAN: - 1: Enter Freeze mode if the FRZ bit is asserted. - 0: No Freeze mode request. Assertion of HALT puts the FlexCAN module into Freeze mode. The CPU should clear HALT after initializing the message buffers and the control registers.." "No Freeze mode request,Enter Freeze mode if the FRZ bit is asserted" newline rbitfld.long 0x0 27. "NOTRDY,FlexCAN Not Ready: - 1: FlexCAN is either in Module Disable Doze Stop or Freeze mode. - 0: FlexCAN is either in Normal Listen-Only or Loop-Back mode. NOTRDY is a read-only bit that indicates that the FlexCAN is either in Module Disable Doze.." "FlexCAN is either in Normal,FlexCAN is either in Module Disable" bitfld.long 0x0 26. "WAKMSK,Wake Up Interrupt Mask - Enables Wake Up interrupt generation under the Self Wake Up mechanism: - 1: Enable Wake Up interrupt. - 0: Disable Wake Up interrupt." "Disable Wake Up interrupt,Enable Wake Up interrupt" newline bitfld.long 0x0 25. "SOFTRST,Soft Reset: - 1: Reset the registers affected by soft reset. - 0: No reset request. When SOFTRST is asserted the FlexCAN resets its internal state machines and some of the memory-mapped registers. SOFTRST can be asserted directly by the CPU by.." "No reset request,Reset the registers affected by soft reset" rbitfld.long 0x0 24. "FRZACK,Freeze Mode Acknowledge: - 1: FlexCAN in Freeze mode prescaler stopped. - 0: FlexCAN not in Freeze mode prescaler running. FRZACK is a read-only bit that indicates that the FlexCAN is in Freeze mode and its prescaler is stopped. A Freeze mode.." "FlexCAN not in Freeze mode,FlexCAN in Freeze mode" newline bitfld.long 0x0 23. "SUPV,Supervisor Mode - Configures the FlexCAN to be either in Supervisor or User mode: - 1: FlexCAN is in Supervisor mode. Affected registers allow only Supervisor access. Unrestricted access behaves as though the access was done to an unimplemented.." "FlexCAN is in User mode,FlexCAN is in Supervisor mode" bitfld.long 0x0 22. "SLFWAK,Self Wake Up - Enables the Self Wake Up feature when the FlexCAN is in a low-power mode other than Module Disable: - 1: Enable FlexCAN Self Wake Up feature. - 0: Disable FlexCAN Self Wake Up feature. When the Self Wake Up feature is enabled the.." "Disable FlexCAN Self Wake Up feature,Enable FlexCAN Self Wake Up feature" newline bitfld.long 0x0 21. "WRNEN,Warning Interrupt Enable: - 1: TWRNINT and RWRNINT bits are set when the respective error counter transitions from less than 96 to greater than or equal to 96. - 0: TWRNINT and RWRNINT bits are zero independent of the values in the error counters." "TWRNINT and RWRNINT bits are zero,TWRNINT and RWRNINT bits are set when the.." rbitfld.long 0x0 20. "LPMACK,Low-Power Mode Acknowledge: - 1: FlexCAN is in a low-power mode. - 0: FlexCAN is not in a low-power mode. LPMACK is a read-only bit that indicates that the FlexCAN is in a low-power mode (Module Disable Doze or Stop). A low-power mode cannot be.." "FlexCAN is not in a low-power mode,FlexCAN is in a low-power mode" newline bitfld.long 0x0 19. "WAKSRC,Wake Up Source - Controls whether the integrated low-pass filter is applied to protect the Rx CAN input from spurious wakeup: - 1: FlexCAN uses the filtered Rx input to detect recessive-to- dominant edges on the CAN bus. - 0: FlexCAN uses the.." "FlexCAN uses the unfiltered Rx input to detect..,FlexCAN uses the filtered Rx input to detect.." bitfld.long 0x0 18. "DOZE,Doze Mode Enable - Controls whether the FlexCAN is allowed to enter low-power mode when Doze mode is requested at chip level: - 1: FlexCAN is enabled to enter low-power mode when Doze mode is requested. - 0: FlexCAN is not enabled to enter low-power.." "FlexCAN is not enabled to enter low-power mode..,FlexCAN is enabled to enter low-power mode when.." newline bitfld.long 0x0 17. "SRXDIS,Self Reception Disable: - 1: Disable self-reception. - 0: Enable self-reception. SRXDIS controls whether the FlexCAN is allowed to receive frames transmitted by itself. If SRXDIS is asserted frames transmitted by the FlexCAN are not stored in any.." "Enable self-reception,Disable self-reception" bitfld.long 0x0 16. "IRMQ,Individual Rx Masking And Queue Enable: - 1: Enable individual Rx masking and queue feature. - 0: Disable individual Rx masking and queue feature. For backward compatibility with legacy applications the reading of C/S word locks the MB even if it.." "Disable individual Rx masking and queue feature,Enable individual Rx masking and queue feature" newline bitfld.long 0x0 15. "DMA,DMA Enable: - 1: Enable DMA feature for Rx FIFO. - 0: Disable DMA feature for Rx FIFO. The DMA bit enables or disables the DMA feature. The DMA feature can only be used with the Legacy Rx FIFO or the Enhanced Rx FIFO; consequently either.." "Disable DMA feature for Rx FIFO,Enable DMA feature for Rx FIFO" bitfld.long 0x0 14. "PNET_EN,Pretended Networking Enable - Enables the Pretended Networking functionality: - 1: Enable Pretended Networking mode. - 0: Disable Pretended Networking mode. When Pretended Networking is enabled the PE submodule is kept operational in Doze mode.." "Disable Pretended Networking mode,Enable Pretended Networking mode" newline bitfld.long 0x0 13. "LPRIOEN,Local Priority Enable: - 1: Enable Local Priority. - 0: Disable Local Priority. The LPRIOEN bit is provided for backward compatibility with legacy applications. LPRIOEN controls whether the Local Priority feature is enabled or not. Local Priority.." "Disable Local Priority,Enable Local Priority" bitfld.long 0x0 12. "AEN,Abort Enable - Enables the Tx abort mechanism: - 1: Enable abort. - 0: Disable abort. The Tx abort mechanism ensures a safe procedure for aborting a pending transmission so that no frame is sent on the CAN bus without notification." "Disable abort,Enable abort" newline bitfld.long 0x0 11. "FDEN,CAN FD Operation Enable - Enables CAN with Flexible Data rate (CAN FD) operation: - 1: CAN FD is enabled. The FlexCAN is able to receive and transmit messages in both CAN FD and CAN 2.0 formats. - 0: CAN FD is disabled. The FlexCAN is able to.." "CAN FD is disabled,CAN FD is enabled" newline bitfld.long 0x0 8.--9. "IDAM,ID Acceptance Mode - Identifies the format of the Legacy Rx FIFO ID Filter Table elements: - 00: Format A- One full ID (standard and extended) per ID Filter Table element. - 01: Format B - Two full standard IDs or two partial 14-bit (standard and.." "Format A,Format B,?,?" newline hexmask.long.byte 0x0 0.--6. 1. "MAXMB,Number of the Last Message Buffer - Defines the number of the last message buffer that will take part in the matching and arbitration processes. The reset value (OxOF) is equivalent to a 16 message buffer configuration. MAXMB can be written only in.." line.long 0x4 "CAN_CTRL1,The CAN_CTRL1 register is defined for specific FlexCAN control features related to the CAN bus. such as bit-rate. programmable sampling point within an Rx bit. Loop-Back mode. Listen-Only mode. Bus Off recovery behavior. and interrupt enabling.." hexmask.long.byte 0x4 24.--31. 1. "PRESDIV,Prescaler Division Factor - Defines the ratio between the PE clock frequency and the serial clock (Sclock) frequency. The Sclock period defines the time quantum of the CAN protocol. For the reset value the Sclock frequency is equal to the PE.." bitfld.long 0x4 22.--23. "RJW,Resync Jump Width - Defines the maximum number of time quanta that a bit time can be changed by one re-synchronization. One time quantum is equal to the Sclock period. The valid programmable values for RJW are 0-3. RJW can be written only in Freeze.." "0,1,2,3" newline bitfld.long 0x4 19.--21. "PSEG1,Phase Segment 1 - Defines the length of phase segment 1 in the bit time. The valid programmable values are 0-7. PSEG1 can be written only in Freeze mode because it is blocked by hardware in other modes. Phase Buffer Segment 1 = (PSEG1 + 1) x.." "?,Defines the length of phase segment 1 in the bit..,?,?,?,?,?,?" bitfld.long 0x4 16.--18. "PSEG2,Phase Segment 2 - Defines the length of phase segment 2 in the bit time. The valid programmable values are 1-7. PSEG2 can be written only in Freeze mode because it is blocked by hardware in other modes. Phase Buffer Segment 2 = (PSEG2 + 1) x.." "?,?,Defines the length of phase segment 2 in the..,?,?,?,?,?" newline bitfld.long 0x4 15. "BOFFMSK,Bus Off Interrupt Mask - Provides a mask for the Bus Off interrupt (CAN_ESR1.BOFFINT): - 1: Bus Off interrupt enabled. - 0: Bus Off interrupt disabled." "Bus Off interrupt disabled,Bus Off interrupt enabled" bitfld.long 0x4 14. "ERRMSK,Error Interrupt Mask - Provides a mask for the Error interrupt (CAN_ESR 1.ERRINT). - 1: Error interrupt enabled. - 0: Error interrupt disabled." "Error interrupt disabled,Error interrupt enabled" newline bitfld.long 0x4 13. "CLKSRC,CAN Engine Clock Source - Selects the clock source to the PE submodule to be either the peripheral clock or the oscillator clock: - 1: The PE clock source is the peripheral clock. - 0: The PE clock source is the oscillator clock. Under this.." "The PE clock source is the oscillator clock,The PE clock source is the peripheral clock" bitfld.long 0x4 12. "LPB,Loop-Back Mode - Configures the FlexCAN to operate in Loop-Back mode: - 1: Loop-Back enabled. - 0: Loop-Back disabled. In Loop-Back mode the FlexCAN performs an internal loop back that can be used for self-test operation. The bit stream output of.." "Loop-Back disabled,Loop-Back enabled" newline bitfld.long 0x4 11. "TWRNMSK,Tx Warning Interrupt Mask - Provides a mask for the Tx Warning interrupt (CAN-ESR1.TWRNINT): - 1: Tx Warning interrupt enabled. - 0: Tx Warning interrupt disabled. TWRNMSK is read as zero when CAN_MCR.WRNEN is negated. TWRNMSK can be written.." "Tx Warning interrupt disabled,Tx Warning interrupt enabled" bitfld.long 0x4 10. "RWRNMSK,Rx Warning Interrupt Mask - Provides a mask for the Rx Warning interrupt (CAN_ESR1.RWRNINT) - 1: Rx Warning interrupt enabled. - 0: Rx Warning interrupt disabled. RWRNMSK is read as zero when CAN_MCR.WRNEN is negated. RWRNMSK can be written only.." "Rx Warning interrupt disabled,Rx Warning interrupt enabled" newline bitfld.long 0x4 7. "SMP,CAN Bit Sampling - Defines the sampling mode of CAN bits at the Rx input: - 0: One sample is used to determine the bit value. - 1: Three samples are used to determine the value of the received bit:the regular sample (sample point) and two.." "One sample is used to determine the bit value,Three samples are used to determine the value of.." newline bitfld.long 0x4 6. "BOFFREC,Bus Off Recovery - Defines how the FlexCAN recovers from Bus Off state: - 0: Automatic recovering from Bus Off state enabled. - 1: Automatic recovering from Bus Off state disabled. If BOFFREC is negated automatic recovering from Bus Off state.." "Automatic recovering from Bus Off state enabled,Automatic recovering from Bus Off state disabled" bitfld.long 0x4 5. "TSYN,Timer Sync - Enables a mechanism that resets the free-running timer each time a message is received in message buffer 0: - 1: Timer Sync feature enabled. - 0: Timer Sync feature disabled. The Timer Sync feature provides a means to synchronize.." "Timer Sync feature disabled,Timer Sync feature enabled" newline bitfld.long 0x4 4. "LBUF,Lowest Buffer Transmitted First - Defines the ordering mechanism for message buffer transmission: - 1: Lowest number buffer is transmitted first. - 0: Buffer with highest priority is transmitted first. When LBUF is asserted the CAN_MCR.LPRIOEN bit.." "Buffer with highest priority is transmitted first,Lowest number buffer is transmitted first" bitfld.long 0x4 3. "LOM,Listen-Only Mode - Configures the FlexCAN to operate in Listen-Only mode: - 1: FlexCAN module operates in Listen-Only mode. - 0: Listen-Only mode is deactivated. In Listen-Only Mode mode transmission is disabled all error counters described in.." "Listen-Only mode is deactivated,FlexCAN module operates in Listen-Only mode" newline bitfld.long 0x4 0.--2. "PROPSEG,Propagation Segment - Defines the length of the propagation segment in the bit time. The valid programmable values are 0-7. PROPSEG can be written only in Freeze mode because it is blocked by hardware in other modes. Propagation segment time =.." "0,1,2,3,4,5,6,7" line.long 0x8 "CAN_TIMER,The CAN_TIMER register represents a 16-bit free-running counter that can be read and written by the CPU. The timer starts from 0x0 after reset. counts linearly to 0xFFFF. and wraps around. When CAN_CTRL2.TIMER_SRC is asserted. the timer is.." hexmask.long.word 0x8 0.--15. 1. "TIMER,Timer Value - Contains the free-running counter value." group.long 0x10++0x27 line.long 0x0 "CAN_RXMGMASK,The CAN_RXMGMASK register is located in RAM. CAN_RXMGMASK is provided for legacy application support: - When the CAN_MCR.IRMQ bit is negated. CAN_RXMGMASK is always in effect (the bits in the MG field will mask the mailbox filter bits). -.." hexmask.long 0x0 0.--31. 1. "MG,Rx Mailboxes Global Mask Bits: - 0: The corresponding bit in the filter is 'don't care'. - 1: The corresponding bit in the filter is checked. The MG bits mask the mailbox filter bits. Note that the alignment with the ID word of the mailbox is not.." line.long 0x4 "CAN_RX14MASK,The CAN_RX14MASK register is located in RAM. CAN_RX14MASK is provided for legacy application support. When the CAN_MCR.IRMQ bit is asserted. CAN_RX14MASK has no effect. CAN_RX14MASK is used to mask the filter fields of message buffer 14." hexmask.long 0x4 0.--31. 1. "RX14M,Rx Buffer 14 Mask Bits: - 0: The corresponding bit in the filter is 'don't care'. - 1: The corresponding bit in the filter is checked. Each mask bit masks the corresponding mailbox 14 filter field in the same way that CAN_RXMGMASK masks other.." line.long 0x8 "CAN_RX15MASK,The CAN_RX15MASK register is located in RAM. CAN_RX15MASK is provided for legacy application support. When the CAN_MCR.IRMQ bit is asserted. CAN_RX15MASK has no effect. CAN_RX15MASK is used to mask the filter fields of message buffer 15." hexmask.long 0x8 0.--31. 1. "RX15M,Rx Buffer 15 Mask Bits: - 0: The corresponding bit in the filter is 'don't care'. - 1: The corresponding bit in the filter is checked. Each mask bit masks the corresponding mailbox 15 filter field in the same way that CAN_RXMGMASK masks other.." line.long 0xC "CAN_ECR,The CAN_ECR register has four 8-bit fields reflecting the value of the FlexCAN error counters: - Transmit Error Counter (TXERRCNT field) - Receive Error Counter (RXERRCNT field) - Transmit Error Counter for errors detected in the Data Phase of.." hexmask.long.byte 0xC 24.--31. 1. "RXERRCNT_FAST,Receive Error Counter for Fast Bits - Receive error counter for errors detected in the Data Phase of received CAN FD messages with the BRS bit set. The RXERRCNT_FAST counter is read-only except in Freeze mode in which the CPU can write an.." hexmask.long.byte 0xC 16.--23. 1. "TXERRCNT_FAST,Transmit Error Counter for Fast Bits - Transmit error counter for errors detected in the Data Phase of transmitted CAN FD messages with the BRS bit set. The TXERRCNT_FAST counter is read-only except in Freeze mode in which the CPU can.." newline hexmask.long.byte 0xC 8.--15. 1. "RXERRCNT,Receive Error Counter - Receive error counter for all errors detected in received messages. The RXERRCNT counter is read-only except in Freeze mode in which it can be written by the CPU." hexmask.long.byte 0xC 0.--7. 1. "TXERRCNT,Transmit Error Counter - Transmit error counter for all errors detected in transmitted messages. The TXERRCNT counter is read-only except in Freeze mode in which it can be written by the CPU." line.long 0x10 "CAN_ESR1,Error and Status 1 Register. The CAN_ESR1 register reports various error conditions detected in the reception and transmission of a CAN frame. some general status of the device. and is the source of some interrupts to the CPU." rbitfld.long 0x10 31. "BIT1ERR_FAST,Bit1 Error in the Data Phase of CAN FD Frames with the BRS Bit Set BIT1ERR_FAST indicates when an inconsistency occurs between the transmitted and the received bitin the Data Phase of CAN FD frames with the BRS bit set: - 1: At least one.." "No such occurrence,At least one bit sent as recessive is received.." rbitfld.long 0x10 30. "BIT0ERR_FAST,Bit0 Error in the Data Phase of CAN FD Frames with the BRS Bit Set BIT0ERR_FAST indicates when an inconsistency occurs between the transmitted and the received bit in the Data Phase of CAN FD frames with the BRS bit set: - 1: At least one.." "No such occurrence,At least one bit sent as dominant is received as.." newline rbitfld.long 0x10 28. "CRCERR_FAST,Cyclic Redundancy Check Error in the CRC field of CAN FD Frames with the BRS Bit Set CRCERR_FAST indicates that a CRC error has been detected by the receivernode in the CRC field of CAN FD frames with the BRS bit set; that is the.." "No such occurrence,A CRC error occurred since last read of this.." newline rbitfld.long 0x10 27. "FRMERR_FAST,From Error in the Data Phase of CAN FD Frames with the BRS Bit Set FRMERR_FAST indicates that a form error has been detected by the receiver node in the Data Phase of CAN FD frames with the BRS bit set; that is a fixed-form bit field.." "No such occurrence,A form error occurred since last read of this.." rbitfld.long 0x10 26. "STFERR_FAST,Stuffing Error in the Data Phase of CAN FD Frames with the BRS Bit Set STFERR_FAST indicates that a stuffing error has been detected in the Data Phase of CAN FD frames with the BRS bit set: - 1: A stuffing error occurred since last read of.." "No such occurrence,A stuffing error occurred since last read of.." newline bitfld.long 0x10 21. "ERROVR,Error Overrun - Indicates that an error condition occurred when any error flag is already set: - 1: Overrun has occurred. - 0: Overrun has not occurred. ERROVR is cleared by writing 1 to it." "Overrun has not occurred,Overrun has occurred" newline bitfld.long 0x10 20. "ERRINT_FAST,Error Interrupt for Errors Detected in the Data Phase of CAN FD Frames with the BRS Bit Set: - 1: Indicates setting of any error bit detected in the Data Phase of CAN FD frames with the BRS bit set. - 0: No such occurrence." "No such occurrence,Indicates setting of any error bit detected in.." bitfld.long 0x10 19. "BOFFDONEINT,Bus Off Done Interrupt: - 1: FlexCAN module has completed Bus Off process. - 0: No such occurrence." "No such occurrence,FlexCAN module has completed Bus Off process" newline rbitfld.long 0x10 18. "SYNCH,CAN Synchronization Status: - 1: FlexCAN is synchronized to the CAN bus. - 0: FlexCAN is not synchronized to the CAN bus. SYNCH is a read-only flag that indicates whether the FlexCAN is synchronized to the CAN bus and able to participate in the.." "FlexCAN is not synchronized to the CAN bus,FlexCAN is synchronized to the CAN bus" bitfld.long 0x10 17. "TWRNINT,Tx Warning Interrupt Flag: - 1: The Tx error counter transitioned from less than 96 to greater than or equal to 96. - 0: No such occurrence." "No such occurrence,The Tx error counter transitioned from less than.." newline bitfld.long 0x10 16. "RWRNINT,Rx Warning Interrupt Flag: - 1: The Rx error counter transitioned from less than 96 to greater than or equal to 96. - 0: No such occurrence." "No such occurrence,The Rx error counter transitioned from less than.." rbitfld.long 0x10 15. "BIT1ERR,Bit1 Error - Indicates when an inconsistency occurs between the transmitted and the received bit in a non-CAN FD message or in the arbitration or Data Phase of a CAN FD message: - 1: At least one bit sent as recessive is received as dominant. -.." "No such occurrence,At least one bit sent as recessive is received.." newline rbitfld.long 0x10 14. "BIT0ERR,Bit0 Error - Indicates when an inconsistency occurs between the transmitted and the received bit in a non-CAN FD message or in the arbitration or Data Phase of a CAN FD message: - 1: At least one bit sent as dominant is received asrecessive. -.." "No such occurrence,At least one bit sent as dominant is received.." rbitfld.long 0x10 13. "ACKERR,Acknowledge Error - Indicates that an Acknowledge error was detected by the transmitter node (that is a dominant bit was detected during the ACK SLOT): - 1: An ACK error occurred since last read of this register. - 0: No such occurrence. ACKERR.." "No such occurrence,An ACK error occurred since last read of this.." newline rbitfld.long 0x10 12. "CRCERR,Cyclic Redundancy Check Error - Indicates that a CRC error was detected by the receiver node either in a non-FD message or in the arbitration or Data Phase of a frame in CAN FD format (that is the calculated CRC is different from the received.." "No such occurrence,A CRC error occurred since last read of this.." rbitfld.long 0x10 11. "FRMERR,Form Error - Indicates that a form error was detected by the receiver node in a non-FD message or in a CAN FD message arbitration or Data Phase (that is a fixed-form bit field contains at least one illegal bit): - 1: A form error occurred since.." "No such occurrence,A form error occurred since last read of this.." newline rbitfld.long 0x10 10. "STFERR,Stuffing Error - Indicates that a stuffing error was detected by the receiver node in a non-FD message or in a CAN FD message arbitration or Data Phase: - 1: A stuffing error occurred since last read of this register. - 0: No such occurrence." "No such occurrence,A stuffing error occurred since last read of.." rbitfld.long 0x10 9. "TXWRN,TX Error Warning - Indicates when repetitive errors are occurring during message transmission: - 1: TXERRCNT is greater than or equal to 96. - 0: No such occurrence. TXWRN is affected by the value of CAN_ECR.TXERRCNT only. TXWRN is not updated.." "No such occurrence,TXERRCNT is greater than or equal to 96" newline rbitfld.long 0x10 8. "RXWRN,Rx Error Warning - Indicates when repetitive errors are occurring during message reception: - 1: RXERRCNT is greater than or equal to 96. - 0: No such occurrence. RXWRN is affected by the value of CAN_ECR.RXERRCNT only. RXWRN is not updated during.." "No such occurrence,RXERRCNT is greater than or equal to 96" rbitfld.long 0x10 7. "IDLE,IDLE - Indicates when the CAN bus is in the IDLE state: - 1: CAN bus is now IDLE. - 0: No such occurrence." "No such occurrence,CAN bus is now IDLE" newline rbitfld.long 0x10 6. "TX,FlexCAN in Transmission - Indicates if the FlexCAN is transmitting a message: - 1: FlexCAN is transmitting a message. - 0: FlexCAN is not transmitting a message." "FlexCAN is not transmitting a message,FlexCAN is transmitting a message" rbitfld.long 0x10 4.--5. "FLTCONF,Fault Confinement State - Indicates the fault confinement state of the FlexCAN module: - 00: Error Active - 01: Error Passive - 1x: Bus Off If CAN_CTRL1.LOM is asserted after a delay that depends on the CAN bit timing the FLTCONF field will.." "Error Active,Error Passive,?,?" newline rbitfld.long 0x10 3. "RX,FlexCAN in Reception - Indicates if the FlexCAN is receiving a message: - 1: FlexCAN is receiving a message. - 0: FlexCAN is not receiving a message." "FlexCAN is not receiving a message,FlexCAN is receiving a message" bitfld.long 0x10 2. "BOFFINT,Bus Off Interrupt: - 1: FlexCAN module entered Bus Off state. - 0: No such occurrence. BOFFINT is set when the FlexCAN enters the Bus Off state. If the corresponding mask bit (CAN-CTRL1.BOFFMSK) is set an interrupt is generated to the CPU." "No such occurrence,FlexCAN module entered Bus Off state" newline bitfld.long 0x10 1. "ERRINT,Error Interrupt: - 1: Indicates setting of any error bit in CAN-ESR1. - 0: No such occurrence. ERRINT indicates that at least one of the error bits (BIT1ERR BITOERR ACKERR CRCERR FRMERR or STFERR) is set. If the corresponding mask bit.." "No such occurrence,Indicates setting of any error bit in CAN-ESR1" bitfld.long 0x10 0. "WAKINT,Wake Up Interrupt - Applies when the FlexCAN is in low-power mode under Self Wake Up mechanism either Doze mode or Stop mode: - 1: Indicates a recessive-to-dominant transition was received on the CAN bus. - 0: No such occurrence. When a.." "No such occurrence,Indicates a recessive-to-dominant transition was.." line.long 0x14 "CAN_IMASK2,Interrupt Masks 2 Register. The CAN_IMASK2 register allows any number of the 32 message buffer interrupts to be enabled or disabled for MB63 to MB32. CAN_IMASK2 contains one interrupt mask bit per buffer. enabling the CPU to determine which.." hexmask.long 0x14 0.--31. 1. "BUF63TO32M,Buffer MB i Mask Each bit enables or disables the corresponding FlexCAN Message Buffer Interrupt for MB63 to MB32: - 1: The corresponding buffer interrupt is enabled. - 0: The corresponding buffer interrupt is disabled." line.long 0x18 "CAN_IMASK1,Interrupt Masks 1 Register. The CAN_IMASK1 register allows any number of the 32 message buffer interrupts to be enabled or disabled for MB31 to MB. CAN_IMASK1 contains one interrupt mask bit per buffer. enabling the CPU to determine which.." hexmask.long 0x18 0.--31. 1. "BUF31TO0M,Buffer MB i Mask Each bit enables or disables the corresponding FlexCAN Message Buffer Interrupt for MB31 to MBO: - 1: The corresponding buffer interrupt is enabled. - 0: The corresponding buffer interrupt is disabled." line.long 0x1C "CAN_IFLAG2,Interrupt Flags 2 Register. The CAN_IFLAG2 register defines the flags for the 32 message buffer interrupts for MB63 to MB32. CAN_IFLAG2 contains one interrupt flag bit per buffer. Each successful transmission or reception sets the respective.." hexmask.long 0x1C 0.--31. 1. "BUF63TO321,Buffer MB i Interrupt Each bit flags the corresponding FlexCAN Message Buffer Interrupt for MB63 to MB32: - 1: The corresponding buffer has successfully completed transmission or reception. - 0: The corresponding buffer has no occurrence of.." line.long 0x20 "CAN_IFLAG1,Interrupt Flags 1 Register. The CAN_IFLAG1 register defines the flags for the 32 message buffer interrupts for MB31 to MB0. CAN_IFLAG1 contains one interrupt flag bit per buffer. Each successful transmission or reception sets the corresponding.." hexmask.long.tbyte 0x20 8.--31. 1. "BUF31T081,Buffer MBi Interrupt Each bit flags the corresponding FlexCAN Message Buffer Interrupt for MB31 to MB8: - 1: The corresponding buffer has successfully completed transmission or reception. - 0: The corresponding buffer has no occurrence of.." bitfld.long 0x20 7. "BUF71,Buffer MB 7 Interrupt or Legacy Rx FIFO Overflow: - 1: MB7 completed transmission/reception when CAN_MCR.RFEN=O or Legacy Rx FIFO overflow when CAN_MCR.RFEN=1. - 0: No occurrence of MB7 completing transmission/reception when CAN_MCR.RFEN=O or of.." "No occurrence of MB7 completing..,MB7 completed transmission/reception when CAN_MCR" newline bitfld.long 0x20 6. "BUF61,Buffer MB6 Interrupt or Legacy Rx FIFO Warning: - 1: MB6 completed transmission/reception when CAN_MCR.RFEN=0 or Legacy Rx FIFO almost full when CAN_MCR.RFEN=1. - 0: No occurrence of MB6 completing transmission/reception when CAN_MCR.RFEN=O or of.." "No occurrence of MB6 completing..,MB6 completed transmission/reception when CAN_MCR" bitfld.long 0x20 5. "BUF51,Buffer MB5 Interrupt or Frames Available in Legacy Rx FIFO: - 1: MB5 completed transmission/reception when CAN_MCR.RFEN=0 or frame(s) available in the Legacy Rx FIFO when CAN_MCR.RFEN=1. BUF51 generates a OMA request when both CAN_MCR.RFEN and.." "No occurrence of MB5 completing..,MB5 completed transmission/reception when CAN_MCR" newline hexmask.long.byte 0x20 1.--4. 1. "BUF4T011,Buffer MB Interrupt or Reserved: - 1: The corresponding buffer has successfully completed transmission or reception when CAN_MCR.RFEN=O. - 0: The corresponding buffer has no occurrence of successfully completed transmission or reception when.." bitfld.long 0x20 0. "BUF01,Buffer MBO Interrupt or Clear Legacy Rx FIFO bit When CAN_MCR.RFEN is cleared (Legacy Rx FIFO disabled) BUF0I flags the interrupt for MB0: - 1: MB0 has successfully completed transmission or reception when CAN_MCR.RFEN=O. - 0: MB0 has no.." "MB0 has no occurrence of successfully completed..,MB0 has successfully completed transmission or.." line.long 0x24 "CAN_CTRL2,Control 2 Register. The CAN_CTRL2 register complements CAN_CTRL1. providing control bits for memory write access in Freeze mode. for extending Legacy Rx FIFO filter quantity. and for adjusting the operation of internal FlexCAN processes like.." bitfld.long 0x24 31. "ERRMSK_FAST,Error Interrupt Mask for errors detected in the Data Phase of fast CAN FD frames ERRMSK_FAST provides a mask for the ERRINT_FAST Interrupt in CAN_ESR1: - 1: ERRINT_FAST error interrupt enabled. - 0: ERRINT_FAST error interrupt disabled." "ERRINT_FAST error interrupt disabled,ERRINT_FAST error interrupt enabled" bitfld.long 0x24 30. "BOFFDONEMSK,Bus Off Done Interrupt Mask - Provides a mask for the Bus Off done interrupt in CAN_ESR1: - 1: Bus Off done interrupt enabled. - 0: Bus Off done interrupt disabled." "Bus Off done interrupt disabled,Bus Off done interrupt enabled" newline bitfld.long 0x24 29. "ECRWRE,Error-Correction Configuration Register Write Enable - Enables the CAN-MECR register to be updated: - 1: Enable update. - 0: Disable update." "Disable update,Enable update" bitfld.long 0x24 28. "WRMFRZ,Write-Access To Memory In Freeze Mode - Enable unrestricted write access to FlexCAN memory in Freeze mode: - 0: Maintain the write access restrictions. - 1: Enable unrestricted write access to FlexCAN memory. WRMFRZ can only be written in Freeze.." "Maintain the write access restrictions,Enable unrestricted write access to FlexCAN memory" newline hexmask.long.byte 0x24 24.--27. 1. "RFFN,Number of Legacy Rx FIFO Filters - Defines the number of Legacy Rx FIFO filters. The maximum selectable number of filters is a function of configuration parameter NUMBER_OF_MB. RFFN must not be programmed with values that cause the number of message.." hexmask.long.byte 0x24 19.--23. 1. "TASD,Tx Arbitration Start Delay - Indicates how many CAN bits the Tx arbitration process start point can be delayed from the first bit of CRC field on CAN bus." newline bitfld.long 0x24 18. "MRP,Mailboxes Reception Priority: - 1: Matching starts from mailboxes and continues on Legacy Rx FIFO. - 0: Matching starts from Legacy Rx FIFO and continues on mailboxes. If MRP is set the matching process starts from the mailboxes and if no match.." "Matching starts from Legacy Rx FIFO and..,Matching starts from mailboxes and continues on.." bitfld.long 0x24 17. "RRS,Remote Request Storing: - 1: Remote Request Frame is stored. - 0: Remote Response Frame is generated. If RRS is asserted a Remote Request Frame is submitted to a matching process and stored in the corresponding message buffer in the same fashion as.." "Remote Response Frame is generated,Remote Request Frame is stored" newline bitfld.long 0x24 16. "EACEN,Entire Frame Arbitration Field Comparison Enable for Rx Mailboxes: - 1: Enables the comparison of both the IDE and RTR bits of an Rx mailbox filter with the corresponding bits of the incoming frame. Mask bits do apply. - 0: Rx mailbox filter's IDE.." "Rx mailbox filter's IDE bit is always compared..,Enables the comparison of both the IDE and RTR.." bitfld.long 0x24 15. "TIMER_SRC,Timer Source - Selects the time tick source used for incrementing the free-running timer counter: - 1: The free-running timer is clocked by an external time tick. The period can be either adjusted to be equal to the baud rate on the CAN bus or.." "The free-running timer is clocked by the CAN bit..,The free-running timer is clocked by an external.." newline bitfld.long 0x24 14. "PREXCEN,Protocol Exception Enable - Enables the protocol exception feature: - 1: Protocol exception is enabled. - 0: Protocol exception is disabled. PREXCEN is writable only in Freeze mode. PREXCEN is not available (reserved write 0) if parameter FD EN.." "Protocol exception is disabled,Protocol exception is enabled" newline bitfld.long 0x24 12. "ISOCANFDEN,ISO CAN FD Enable - 1: Enable ISO CAN FD compliant operation. - 0: Disable ISO CAN FD specific features (non-ISO CAN FD operation). ISOCANFDEN enables ISO CAN FD compliant operation by enabling the following features which are part of the ISO.." "Disable ISO CAN FD specific features,Enable ISO CAN FD compliant operation" bitfld.long 0x24 11. "EDFLTDIS,Edge Filter Disable - Disables the edge filter used during the bus integration state: - 1: Edge filter is disabled. - 0: Edge filter is enabled. When the edge filter is enabled two consecutive nominal time quanta with dominant bus state are.." "Edge filter is enabled,Edge filter is disabled" newline rgroup.long 0x38++0x3 line.long 0x0 "CAN_ESR2,Error and Status 2 Register. The CAN_ESR2 register reports some general status information." hexmask.long.byte 0x0 16.--22. 1. "LPTM,Lowest Priority Tx Mailbox If CAN_ESR2.VPS is asserted LPTM indicates the lowest number inactive mailbox. If there is no inactive mailbox then the mailbox indicated depends on the CAN_CTRL1.LBUF bit value: - If CAN_CTRL1.LBUF is negated the.." newline bitfld.long 0x0 14. "VPS,Valid Priority Status - Indicates whether CAN_ESR2.IMB and CAN_ESR2.LPTM contents are currently valid or not: - 1: Contents of IMB and LPTM are valid. - 0: Contents of IMB and LPTM are invalid. VPS is asserted upon every complete Tx arbitration.." "Contents of IMB and LPTM are invalid,Contents of IMB and LPTM are valid" newline bitfld.long 0x0 13. "IMB,Inactive Mailbox If CAN_ESR2.VPS is asserted IMB indicates whether there is any inactive mailbox (CODE field is either 0b1000 or 0b0000): - 1: If CAN_ESR2.VPS is asserted there is at least one inactive mailbox. CAN_ESR2.LPTM content is the number.." "If CAN_ESR2,If CAN_ESR2" rgroup.long 0x44++0x3 line.long 0x0 "CAN_CRCR,The CAN_CRCR register provides information about the CRC of transmitted messages for non-FD messages. CAN_CRCR only reports the 15 low order bits of CRC calculations for messages in CAN FD format that require either 17 or 21 bits. For CAN FD.." hexmask.long.byte 0x0 16.--22. 1. "MBCRC,CRC Mailbox - Indicates the number of the mailbox corresponding to the value in the CAN CRCR.TXCRC field." newline hexmask.long.word 0x0 0.--14. 1. "TXCRC,Transmitted CRC Value - Indicates the CRC value of the last transmitted message for non-FD frames. For CAN FD frames the CRC value is reported in CAN_FDCRC." group.long 0x48++0x3 line.long 0x0 "CAN_RXFGMASK,Rx FIFO Global Mask Register. The CAN_RXFGMASK register is located in RAM. If the Legacy Rx FIFO is enabled. CAN_RXFGMASK is used to mask the Legacy Rx FIFO ID Filter Table elements that do not have a corresponding CAN_RXIMR according to.." hexmask.long 0x0 0.--31. 1. "FGM,Legacy Rx FIFO Global Mask Bits These bits mask the Legacy Rx FIFO ID Filter Table elements bits in a perfect alignment: - 1: The corresponding bit in the filter is checked. - 0: The corresponding bit in the filter is 'don't care'." rgroup.long 0x4C++0x3 line.long 0x0 "CAN_RXFIR,Rx FIFO Information Register. The CAN_RXFIR register provides information on the Legacy Rx FIFO. CAN_RXFIR is the port through which the CPU accesses the output of the Legacy RXFIR FIFO located in RAM. The Legacy RXFIR FIFO is written by the.." hexmask.long.word 0x0 0.--8. 1. "IDHIT,Identifier Acceptance Filter Hit Indicator - Indicates which Identifier Acceptance Filter was hit by the received message that is in the output of the Legacy Rx FIFO. If multiple filters match the incoming message ID the first matching IDAF found.." group.long 0x50++0x3 line.long 0x0 "CAN_CBT,CAN Bit Timing Register. The CAN_CBT register is an alternative way to store the CAN bit timing variables described in the CAN_CTRL1 register. EPRESDIV. EPROPSEG. EPSEG1. EPSEG2. and ERJW are extended versions of CAN_CTRL1 register PRESDIV." bitfld.long 0x0 31. "BTF,Bit Timing Format Enable - Enables the use of extended CAN bit timing fields EPRESDIV EPROPSEG EPSEG1 EPSEG2 and ERJW replacing the CAN bit timing variables defined in CAN_CTRL1: - 1: Extended bit time definitions enabled. - 0: Extended bit time.." "Extended bit time definitions disabled,Extended bit time definitions enabled" hexmask.long.word 0x0 21.--30. 1. "EPRESDIV,Extended Prescaler Division Factor When CAN_CBT.BTF is asserted EPRESDIV defines the ratio between the PE clock frequency and the Serial Clock (Sclock) frequency. EPRESDIV extends the CAN_CTRL1.PRESDIV value range. Sclock frequency = PE clock.." newline hexmask.long.byte 0x0 16.--20. 1. "ERJW,Extended Resync Jump Width When CAN_CBT.BTF is asserted ERJW defines the maximum number of time quanta that a bit time can be changed by one re- synchronization. ERJW extends the CAN_CTRL1.RJW value range. Resync Jump Width = ERJW + 1 One time.." hexmask.long.byte 0x0 10.--15. 1. "EPROPSEG,Extended Propagation Segment When CAN_CBT.BTF is asserted EPROPSEG defines the length of the Propagation Segment in the bit time. EPROPSEG extends the CAN_CTRL 1.PROPSEG value range. Propagation Segment Time = (EPROPSEG + 1) x Time-Quanta.." newline hexmask.long.byte 0x0 5.--9. 1. "EPSEG1,Extended Phase Segment 1 When CAN_CBT.BTF is asserted EPSEG1 defines the length of Phase Segment 1 in the bit time. EPSEG1 extends the CAN_CTRL 1.PSEG1 value range. Phase Buffer Segment 1 = (EPSEG1 + 1) x Time-Quanta Time-Quantum = one Sclock.." hexmask.long.byte 0x0 0.--4. 1. "EPSEG2,Extended Phase Segment 2 When CAN_CBT.BTF is asserted EPSEG2 defines the length of Phase Segment 2 in the bit time. EPSEG2 extends the CAN_CTRL1.PSEG2 value range. Phase Buffer Segment 1 = (EPSEG2 + 1) x Time-Quanta Time-Quantum = one Sclock.." group.long 0x68++0xF line.long 0x0 "CAN_IMASK4,Interrupt Masks 4 Register. The CAN_IMASK4 register allows any number of the 32 message buffer interrupts to be enabled or disabled for MB127 to MB96. CAN_IMASK4 contains one interrupt mask bit per buffer. enabling the CPU to determine which.." hexmask.long 0x0 0.--31. 1. "BUF127T096M,Buffer MB i Mask Each bit enables or disables the corresponding FlexCAN Message Buffer Interrupt for MB127 to MB96: - 1: The corresponding buffer interrupt is enabled. - 0: The corresponding buffer interrupt is disabled. When CAN FD is.." line.long 0x4 "CAN_IMASK3,Interrupt Masks 3 Register. The CAN_IMASK3 register allows any number of the 32 message buffer interrupts to be enabled or disabled for MB95 to MB64. CAN_IMASK3 contains one interrupt mask bit per buffer. enabling the CPU to determine which.." hexmask.long 0x4 0.--31. 1. "BUF95T064M,Buffer MB i Mask Each bit enables or disables the corresponding FlexCAN Message Buffer Interrupt for MB95 to MB64: - 1: The corresponding buffer interrupt is enabled. - 0: The corresponding buffer interrupt is disabled. When CAN FD is enabled.." line.long 0x8 "CAN_IFLAG4,Interrupt Flags 4 Register. The CAN_IFLAG4 register defines the flags for the 32 message buffer interrupts for MB127 to MB96. CAN_IFLAG4 contains one interrupt flag bit per buffer. Each successful transmission or reception sets the respective.." hexmask.long 0x8 0.--31. 1. "BUF127T096,Buffer MB Interrupt Each bit flags the corresponding FlexCAN Message Buffer Interrupt for MB127 to MB96: - 1: The corresponding buffer has successfully completed transmission or reception. - 0: The corresponding buffer has no occurrence of.." line.long 0xC "CAN_IFLAG3,Interrupt Flags 3 Register. The CAN_IFLAG3 register defines the flags for the 32 Message Buffer interrupts for MB95 to MB64. CAN_IFLAG3 contains one interrupt flag bit per buffer. Each successful transmission or reception sets the respective.." hexmask.long 0xC 0.--31. 1. "BUF95T064,Buffer MB i Interrupt Each bit flags the corresponding FlexCAN Message Buffer Interrupt for MB95 to MB64: - 1: The corresponding buffer has successfully completed transmission or reception. - 0: The corresponding buffer has no occurrence of.." group.long 0x880++0x27 line.long 0x0 "CAN_RXIMR0,Rx Individual Mask Register 0. The Rx Individual Mask Registers are used to store the acceptance masks for ID filtering in Rx MBs and the Legacy Rx FIFO. When the Legacy Rx FIFO is disabled (CAN_MCR.RFEN is negated). an individual mask is.." hexmask.long 0x0 0.--31. 1. "MI,Individual Mask Bits: 1'b1: The corresponding bit in the filter is checked. 1'b0: The corresponding bit in the filter is 'don't care'." line.long 0x4 "CAN_RXIMR1,Rx Individual Mask Register 1. The Rx Individual Mask Registers are used to store the acceptance masks for ID filtering in Rx MBs and the Legacy Rx FIFO. When the Legacy Rx FIFO is disabled (CAN_MCR.RFEN is negated). an individual mask is.." hexmask.long 0x4 0.--31. 1. "MI,Individual Mask Bits: 1'b1: The corresponding bit in the filter is checked. 1'b0: The corresponding bit in the filter is 'don't care'." line.long 0x8 "CAN_RXIMR2,Rx Individual Mask Register 2. The Rx Individual Mask Registers are used to store the acceptance masks for ID filtering in Rx MBs and the Legacy Rx FIFO. When the Legacy Rx FIFO is disabled (CAN_MCR.RFEN is negated). an individual mask is.." hexmask.long 0x8 0.--31. 1. "MI,Individual Mask Bits: - 1'b1: The corresponding bit in the filter is checked. - 1'b0: The corresponding bit in the filter is 'don't care'." line.long 0xC "CAN_RXIMR3,Rx Individual Mask Register 3. The Rx Individual Mask Registers are used to store the acceptance masks for ID filtering in Rx MBs and the Legacy Rx FIFO. When the Legacy Rx FIFO is disabled (CAN_MCR.RFEN is negated). an individual mask is.." hexmask.long 0xC 0.--31. 1. "MI,Individual Mask Bits: 1'b1: The corresponding bit in the filter is checked. 1'b0: The corresponding bit in the filter is 'don't care'." line.long 0x10 "CAN_RXIMR4,Rx Individual Mask Register 4. The Rx Individual Mask Registers are used to store the acceptance masks for ID filtering in Rx MBs and the Legacy Rx FIFO. When the Legacy Rx FIFO is disabled (CAN_MCR.RFEN is negated). an individual mask is.." hexmask.long 0x10 0.--31. 1. "MI,Individual Mask Bits: 1'b1: The corresponding bit in the filter is checked. 1'b0: The corresponding bit in the filter is 'don't care'." line.long 0x14 "CAN_RXIMR5,Rx Individual Mask Register 5. The Rx Individual Mask Registers are used to store the acceptance masks for ID filtering in Rx MBs and the Legacy Rx FIFO. When the Legacy Rx FIFO is disabled (CAN_MCR.RFEN is negated). an individual mask is.." hexmask.long 0x14 0.--31. 1. "MI,Individual Mask Bits: 1'b1: The corresponding bit in the filter is checked. 1'b0: The corresponding bit in the filter is 'don't care'." line.long 0x18 "CAN_RXIMR6,Rx Individual Mask Register 6. The Rx Individual Mask Registers are used to store the acceptance masks for ID filtering in Rx MBs and the Legacy Rx FIFO. When the Legacy Rx FIFO is disabled (CAN_MCR.RFEN is negated). an individual mask is.." hexmask.long 0x18 0.--31. 1. "MI,Individual Mask Bits: 1'b1: The corresponding bit in the filter is checked. 1'b0: The corresponding bit in the filter is 'don't care'." line.long 0x1C "CAN_RXIMR7,Rx Individual Mask Register 7. The Rx Individual Mask Registers are used to store the acceptance masks for ID filtering in Rx MBs and the Legacy Rx FIFO. When the Legacy Rx FIFO is disabled (CAN_MCR.RFEN is negated). an individual mask is.." hexmask.long 0x1C 0.--31. 1. "MI,Individual Mask Bits: 1'b1: The corresponding bit in the filter is checked. 1'b0: The corresponding bit in the filter is 'don't care'." line.long 0x20 "CAN_RXIMR8,Rx Individual Mask Register 8. The Rx Individual Mask Registers are used to store the acceptance masks for ID filtering in Rx MBs and the Legacy Rx FIFO. When the Legacy Rx FIFO is disabled (CAN_MCR.RFEN is negated). an individual mask is.." hexmask.long 0x20 0.--31. 1. "MI,Individual Mask Bits: 1'b1: The corresponding bit in the filter is checked. 1'b0: The corresponding bit in the filter is 'don't care'." line.long 0x24 "CAN_RXIMR9,Rx Individual Mask Register 9.The Rx Individual Mask Registers are used to store the acceptance masks for ID filtering in Rx MBs and the Legacy Rx FIFO. When the Legacy Rx FIFO is disabled (CAN_MCR.RFEN is negated). an individual mask is.." hexmask.long 0x24 0.--31. 1. "MI,Individual Mask Bits: 1'b1: The corresponding bit in the filter is checked. 1'b0: The corresponding bit in the filter is 'don't care'." repeat 16. (list 0xA 0xB 0xC 0xD 0xE 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1A 0x1B 0x1C )(list 0x0 0x4 0x8 0xC 0x10 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C 0x40 0x44 0x48 ) group.long ($2+0x8A8)++0x3 line.long 0x0 "CAN_RXIMR$1,Rx Individual Mask Register 10. The Rx Individual Mask Registers are used to store the acceptance masks for ID filtering in Rx MBs and the Legacy Rx FIFO. When the Legacy Rx FIFO is disabled (CAN_MCR.RFEN is negated). an individual mask is.." hexmask.long 0x0 0.--31. 1. "MI,Individual Mask Bits: 1'b1: The corresponding bit in the filter is checked. 1'b0: The corresponding bit in the filter is 'don't care'." repeat.end repeat 9. (list 0x1D 0x1E 0x24 0x25 0x26 0x27 0x28 0x29 0x3E )(list 0x4C 0x50 0x68 0x6C 0x70 0x74 0x78 0x7C 0xD0 ) group.long ($2+0x8A8)++0x3 line.long 0x0 "CAN_RXIMR$1,Rx Individual Mask Register 10. The Rx Individual Mask Registers are used to store the acceptance masks for ID filtering in Rx MBs and the Legacy Rx FIFO. When the Legacy Rx FIFO is disabled (CAN_MCR.RFEN is negated). an individual mask is.." hexmask.long 0x0 0.--31. 1. "MI,Individual Mask Bits: 1'b1: The corresponding bit in the filter is checked. 1'b0: The corresponding bit in the filter is 'don't care'." repeat.end group.long 0x8BC++0xB line.long 0x0 "CAN_RXIMR15,Rx Individual Mask Register 15.The Rx Individual Mask Registers are used to store the acceptance masks for ID filtering in Rx MBs and the Legacy Rx FIFO. When the Legacy Rx FIFO is disabled (CAN_MCR.RFEN is negated). an individual mask is.." hexmask.long 0x0 0.--31. 1. "MI,Individual Mask Bits: - 1'b1: The corresponding bit in the filter is checked. - 1'b0: The corresponding bit in the filter is 'don't care'." line.long 0x4 "CAN_RXIMR16,Rx Individual Mask Register 16.The Rx Individual Mask Registers are used to store the acceptance masks for ID filtering in Rx MBs and the Legacy Rx FIFO. When the Legacy Rx FIFO is disabled (CAN_MCR.RFEN is negated). an individual mask is.." hexmask.long 0x4 0.--31. 1. "MI,Individual Mask Bits: - 1'b1: The corresponding bit in the filter is checked. - 1'b0: The corresponding bit in the filter is 'don't care'." line.long 0x8 "CAN_RXIMR17,Rx Individual Mask Register 17.The Rx Individual Mask Registers are used to store the acceptance masks for ID filtering in Rx MBs and the Legacy Rx FIFO. When the Legacy Rx FIFO is disabled (CAN_MCR.RFEN is negated). an individual mask is.." hexmask.long 0x8 0.--31. 1. "MI,Individual Mask Bits: - 1'b1: The corresponding bit in the filter is checked. - 1'b0: The corresponding bit in the filter is 'don't care'." group.long 0x8FC++0x13 line.long 0x0 "CAN_RXIMR31,Rx Individual Mask Register 31.The Rx Individual Mask Registers are used to store the acceptance masks for ID filtering in Rx MBs and the Legacy Rx FIFO. When the Legacy Rx FIFO is disabled (CAN_MCR.RFEN is negated). an individual mask is.." hexmask.long 0x0 0.--31. 1. "MI,Individual Mask Bits: - 1'b1: The corresponding bit in the filter is checked. - 1'b0: The corresponding bit in the filter is 'don't care'." line.long 0x4 "CAN_RXIMR32,Rx Individual Mask Register 32.The Rx Individual Mask Registers are used to store the acceptance masks for ID filtering in Rx MBs and the Legacy Rx FIFO. When the Legacy Rx FIFO is disabled (CAN_MCR.RFEN is negated). an individual mask is.." hexmask.long 0x4 0.--31. 1. "MI,Individual Mask Bits: - 1'b1: The corresponding bit in the filter is checked. - 1'b0: The corresponding bit in the filter is 'don't care'." line.long 0x8 "CAN_RXIMR33,Rx Individual Mask Register 33.The Rx Individual Mask Registers are used to store the acceptance masks for ID filtering in Rx MBs and the Legacy Rx FIFO. When the Legacy Rx FIFO is disabled (CAN_MCR.RFEN is negated). an individual mask is.." hexmask.long 0x8 0.--31. 1. "MI,Individual Mask Bits: - 1'b1: The corresponding bit in the filter is checked. - 1'b0: The corresponding bit in the filter is 'don't care'." line.long 0xC "CAN_RXIMR34,Rx Individual Mask Register 34.The Rx Individual Mask Registers are used to store the acceptance masks for ID filtering in Rx MBs and the Legacy Rx FIFO. When the Legacy Rx FIFO is disabled (CAN_MCR.RFEN is negated). an individual mask is.." hexmask.long 0xC 0.--31. 1. "MI,Individual Mask Bits: - 1'b1: The corresponding bit in the filter is checked. - 1'b0: The corresponding bit in the filter is 'don't care'." line.long 0x10 "CAN_RXIMR35,Rx Individual Mask Register 35.The Rx Individual Mask Registers are used to store the acceptance masks for ID filtering in Rx MBs and the Legacy Rx FIFO. When the Legacy Rx FIFO is disabled (CAN_MCR.RFEN is negated). an individual mask is.." hexmask.long 0x10 0.--31. 1. "MI,Individual Mask Bits: - 1'b1: The corresponding bit in the filter is checked. - 1'b0: The corresponding bit in the filter is 'don't care'." group.long 0x928++0x4F line.long 0x0 "CAN_RXIMR42,Rx Individual Mask Register 42.The Rx Individual Mask Registers are used to store the acceptance masks for ID filtering in Rx MBs and the Legacy Rx FIFO. When the Legacy Rx FIFO is disabled (CAN_MCR.RFEN is negated). an individual mask is.." hexmask.long 0x0 0.--31. 1. "MI,Individual Mask Bits: - 1: The corresponding bit in the filter is checked. - 0: The corresponding bit in the filter is 'don't care'." line.long 0x4 "CAN_RXIMR43,Rx Individual Mask Register 43.The Rx Individual Mask Registers are used to store the acceptance masks for ID filtering in Rx MBs and the Legacy Rx FIFO. When the Legacy Rx FIFO is disabled (CAN_MCR.RFEN is negated). an individual mask is.." hexmask.long 0x4 0.--31. 1. "MI,Individual Mask Bits: - 1: The corresponding bit in the filter is checked. - 0: The corresponding bit in the filter is 'don't care'." line.long 0x8 "CAN_RXIMR44,Rx Individual Mask Register 44.The Rx Individual Mask Registers are used to store the acceptance masks for ID filtering in Rx MBs and the Legacy Rx FIFO. When the Legacy Rx FIFO is disabled (CAN_MCR.RFEN is negated). an individual mask is.." hexmask.long 0x8 0.--31. 1. "MI,Individual Mask Bits: - 1: The corresponding bit in the filter is checked. - 0: The corresponding bit in the filter is 'don't care'." line.long 0xC "CAN_RXIMR45,Rx Individual Mask Register 45.The Rx Individual Mask Registers are used to store the acceptance masks for ID filtering in Rx MBs and the Legacy Rx FIFO. When the Legacy Rx FIFO is disabled (CAN_MCR.RFEN is negated). an individual mask is.." hexmask.long 0xC 0.--31. 1. "MI,Individual Mask Bits: - 1: The corresponding bit in the filter is checked. - 0: The corresponding bit in the filter is 'don't care'." line.long 0x10 "CAN_RXIMR46,Rx Individual Mask Register 46.The Rx Individual Mask Registers are used to store the acceptance masks for ID filtering in Rx MBs and the Legacy Rx FIFO. When the Legacy Rx FIFO is disabled (CAN_MCR.RFEN is negated). an individual mask is.." hexmask.long 0x10 0.--31. 1. "MI,Individual Mask Bits: - 1: The corresponding bit in the filter is checked. - 0: The corresponding bit in the filter is 'don't care'." line.long 0x14 "CAN_RXIMR47,Rx Individual Mask Register 47.The Rx Individual Mask Registers are used to store the acceptance masks for ID filtering in Rx MBs and the Legacy Rx FIFO. When the Legacy Rx FIFO is disabled (CAN_MCR.RFEN is negated). an individual mask is.." hexmask.long 0x14 0.--31. 1. "MI,Individual Mask Bits: - 1: The corresponding bit in the filter is checked. - 0: The corresponding bit in the filter is 'don't care'." line.long 0x18 "CAN_RXIMR48,Rx Individual Mask Register 48.The Rx Individual Mask Registers are used to store the acceptance masks for ID filtering in Rx MBs and the Legacy Rx FIFO. When the Legacy Rx FIFO is disabled (CAN_MCR.RFEN is negated). an individual mask is.." hexmask.long 0x18 0.--31. 1. "MI,Individual Mask Bits: - 1: The corresponding bit in the filter is checked. - 0: The corresponding bit in the filter is 'don't care'." line.long 0x1C "CAN_RXIMR49,Rx Individual Mask Register 49.The Rx Individual Mask Registers are used to store the acceptance masks for ID filtering in Rx MBs and the Legacy Rx FIFO. When the Legacy Rx FIFO is disabled (CAN_MCR.RFEN is negated). an individual mask is.." hexmask.long 0x1C 0.--31. 1. "MI,Individual Mask Bits: - 1: The corresponding bit in the filter is checked. - 0: The corresponding bit in the filter is 'don't care'." line.long 0x20 "CAN_RXIMR50,Rx Individual Mask Register 50.The Rx Individual Mask Registers are used to store the acceptance masks for ID filtering in Rx MBs and the Legacy Rx FIFO. When the Legacy Rx FIFO is disabled (CAN_MCR.RFEN is negated). an individual mask is.." hexmask.long 0x20 0.--31. 1. "MI,Individual Mask Bits: - 1: The corresponding bit in the filter is checked. - 0: The corresponding bit in the filter is 'don't care'." line.long 0x24 "CAN_RXIMR51,Rx Individual Mask Register 51.The Rx Individual Mask Registers are used to store the acceptance masks for ID filtering in Rx MBs and the Legacy Rx FIFO. When the Legacy Rx FIFO is disabled (CAN_MCR.RFEN is negated). an individual mask is.." hexmask.long 0x24 0.--31. 1. "MI,Individual Mask Bits: - 1: The corresponding bit in the filter is checked. - 0: The corresponding bit in the filter is 'don't care'." line.long 0x28 "CAN_RXIMR52,Rx Individual Mask Register 52.The Rx Individual Mask Registers are used to store the acceptance masks for ID filtering in Rx MBs and the Legacy Rx FIFO. When the Legacy Rx FIFO is disabled (CAN_MCR.RFEN is negated). an individual mask is.." hexmask.long 0x28 0.--31. 1. "MI,Individual Mask Bits: - 1: The corresponding bit in the filter is checked. - 0: The corresponding bit in the filter is 'don't care'." line.long 0x2C "CAN_RXIMR53,Rx Individual Mask Register 53.The Rx Individual Mask Registers are used to store the acceptance masks for ID filtering in Rx MBs and the Legacy Rx FIFO. When the Legacy Rx FIFO is disabled (CAN_MCR.RFEN is negated). an individual mask is.." hexmask.long 0x2C 0.--31. 1. "MI,Individual Mask Bits: - 1: The corresponding bit in the filter is checked. - 0: The corresponding bit in the filter is 'don't care'." line.long 0x30 "CAN_RXIMR54,Rx Individual Mask Register 54.The Rx Individual Mask Registers are used to store the acceptance masks for ID filtering in Rx MBs and the Legacy Rx FIFO. When the Legacy Rx FIFO is disabled (CAN_MCR.RFEN is negated). an individual mask is.." hexmask.long 0x30 0.--31. 1. "MI,Individual Mask Bits: - 1: The corresponding bit in the filter is checked. - 0: The corresponding bit in the filter is 'don't care'." line.long 0x34 "CAN_RXIMR55,Rx Individual Mask Register 55.The Rx Individual Mask Registers are used to store the acceptance masks for ID filtering in Rx MBs and the Legacy Rx FIFO. When the Legacy Rx FIFO is disabled (CAN_MCR.RFEN is negated). an individual mask is.." hexmask.long 0x34 0.--31. 1. "MI,Individual Mask Bits: - 1: The corresponding bit in the filter is checked. - 0: The corresponding bit in the filter is 'don't care'." line.long 0x38 "CAN_RXIMR56,Rx Individual Mask Register 56.The Rx Individual Mask Registers are used to store the acceptance masks for ID filtering in Rx MBs and the Legacy Rx FIFO. When the Legacy Rx FIFO is disabled (CAN_MCR.RFEN is negated). an individual mask is.." hexmask.long 0x38 0.--31. 1. "MI,Individual Mask Bits: - 1: The corresponding bit in the filter is checked. - 0: The corresponding bit in the filter is 'don't care'." line.long 0x3C "CAN_RXIMR57,Rx Individual Mask Register 57.The Rx Individual Mask Registers are used to store the acceptance masks for ID filtering in Rx MBs and the Legacy Rx FIFO. When the Legacy Rx FIFO is disabled (CAN_MCR.RFEN is negated). an individual mask is.." hexmask.long 0x3C 0.--31. 1. "MI,Individual Mask Bits: - 1: The corresponding bit in the filter is checked. - 0: The corresponding bit in the filter is 'don't care'." line.long 0x40 "CAN_RXIMR58,Rx Individual Mask Register 58.The Rx Individual Mask Registers are used to store the acceptance masks for ID filtering in Rx MBs and the Legacy Rx FIFO. When the Legacy Rx FIFO is disabled (CAN_MCR.RFEN is negated). an individual mask is.." hexmask.long 0x40 0.--31. 1. "MI,Individual Mask Bits: - 1: The corresponding bit in the filter is checked. - 0: The corresponding bit in the filter is 'don't care'." line.long 0x44 "CAN_RXIMR59,Rx Individual Mask Register 59.The Rx Individual Mask Registers are used to store the acceptance masks for ID filtering in Rx MBs and the Legacy Rx FIFO. When the Legacy Rx FIFO is disabled (CAN_MCR.RFEN is negated). an individual mask is.." hexmask.long 0x44 0.--31. 1. "MI,Individual Mask Bits: - 1: The corresponding bit in the filter is checked. - 0: The corresponding bit in the filter is 'don't care'." line.long 0x48 "CAN_RXIMR60,Rx Individual Mask Register 60.The Rx Individual Mask Registers are used to store the acceptance masks for ID filtering in Rx MBs and the Legacy Rx FIFO. When the Legacy Rx FIFO is disabled (CAN_MCR.RFEN is negated). an individual mask is.." hexmask.long 0x48 0.--31. 1. "MI,Individual Mask Bits: - 1: The corresponding bit in the filter is checked. - 0: The corresponding bit in the filter is 'don't care'." line.long 0x4C "CAN_RXIMR61,Rx Individual Mask Register 61.The Rx Individual Mask Registers are used to store the acceptance masks for ID filtering in Rx MBs and the Legacy Rx FIFO. When the Legacy Rx FIFO is disabled (CAN_MCR.RFEN is negated). an individual mask is.." hexmask.long 0x4C 0.--31. 1. "MI,Individual Mask Bits: - 1: The corresponding bit in the filter is checked. - 0: The corresponding bit in the filter is 'don't care'." group.long 0x97C++0x3 line.long 0x0 "CAN_RXIMR63,Rx Individual Mask Register 63. The Rx Individual Mask Registers are used to store the acceptance masks for ID filtering in Rx MBs and the Legacy Rx FIFO. When the Legacy Rx FIFO is disabled (CAN_MCR.RFEN is negated). an individual mask is.." hexmask.long 0x0 0.--31. 1. "MI,Individual Mask Bits: - 1: The corresponding bit in the filter is checked. - 0: The corresponding bit in the filter is 'don't care'. Each Individual Mask Bit masks the corresponding bit in both the mailbox filter and Legacy Rx FIFO ID Filter Table.." group.long 0xAE0++0xF line.long 0x0 "CAN_MECR,The CAN_MECR register contains control bits for memory error detection and correction (ECC). NOTE: When CAN_CTRL2.ECRWRE is 0. writes to CAN_MECR are blocked. with the exception of the ECRWRDIS bit. The CAN_MECR register is not available when.." bitfld.long 0x0 31. "ECRWRDIS,Error Configuration Register Write Disable - Disables writes to this register: - 1: Write is disabled. - 0: Write is enabled. ECRWRDIS is automatically set to 1 (disabled) when CTRL2.ECRWRE is asserted." "Write is enabled,Write is disabled" newline bitfld.long 0x0 19. "HANCEI_MSK,Host Access With Non-Correctable Errors Interrupt Mask Enables the interrupt in case of non-correctable errors detected in memory reads issued by the host (CPU): - 1: Interrupt is enabled. - 0: Interrupt is disabled." "Interrupt is disabled,Interrupt is enabled" bitfld.long 0x0 18. "FANCEI_MSK,FlexCAN Access With Non-Correctable Errors Interrupt Mask Enables the interrupt in case of non-correctable errors detected in memory reads issued by the FlexCAN internal processes: - 1: Interrupt is enabled. - 0: Interrupt is disabled." "Interrupt is disabled,Interrupt is enabled" newline bitfld.long 0x0 16. "CEI_MSK,Correctable Errors Interrupt Mask Enables the interrupt in case of correctable errors detected in memory reads issued by the host or FlexCAN internal processes: - 1: Interrupt is enabled. - 0: Interrupt is disabled." "Interrupt is disabled,Interrupt is enabled" newline bitfld.long 0x0 15. "HAERRIE,Host Access Error Injection Enable Enables the injection of errors only in memory reads issued by the host (CPU): - 1: Injection is enabled. - 0: Injection is disabled." "Injection is disabled,Injection is enabled" bitfld.long 0x0 14. "FAERRIE,FlexCAN Access Error Injection Enable Enables the injection of errors only in memory reads issued by the FlexCAN internal processes: - 1: Injection is enabled. - 0: Injection is disabled." "Injection is disabled,Injection is enabled" newline bitfld.long 0x0 13. "EXTERRIE,Extended Error Injection Enable Memory accesses performed by internal FlexCAN processes are 64-bit accesses. EXTERRIE extends the error injection on 32-bit memory accesses to the complementary 32-bit word using the same 32-bit error injection.." "Error injection is applied only to the 32-bit word,Error injection is applied to the 64-bit word" newline bitfld.long 0x0 9. "RERDIS,Error Report Disable - Disables the update of the error report registers: - 1: Disable updates of the error report registers. The update of error-related flags and the generation of bus transfer errors are still active. - 0: Enable updates of the.." "Enable updates of the error report registers,Disable updates of the error report registers" bitfld.long 0x0 8. "ECCDIS,Error Correction Disable - Disables the memory detection and correction mechanism: - 1: Disable memory error correction. - 0: Enable memory error correction. In addition to disabling the error report mechanism ECCDIS = 1 also stops the update of.." "Enable memory error correction,Disable memory error correction" newline bitfld.long 0x0 7. "NCEFAFRZ,Non-Correctable Errors in FlexCAN Access Put Device In Freeze Mode Determines the response when a non-correctable error is detected in a memory read performed by FlexCAN internal processes: - 1: Put FlexCAN in Freeze mode. In this case entering.." "Keep normal operation,Put FlexCAN in Freeze mode" line.long 0x4 "CAN_ERRIAR,The CAN_ERRIAR register holds the address where a memory read error is to be injected. The size and usage of the FlexCAN RAM depends on the FlexCAN hardware configuration. The CAN_ERRIAR register is not available when parameter ECC_EN is 0." hexmask.long.word 0x4 2.--13. 1. "INJADDR_H,Error Injection Address High - Defines the twelve most significant bits of the physical RAM address where a memory read error is to be injected" newline rbitfld.long 0x4 0.--1. "INJADDR_L,Error Injection Address Low - Read-only field that defines the two least significant bits of the physical RAM address where a memory read error is to be injected. INJADDR - L[1:0] are always zero to ensure that the address is on a 32-bit.." "0,1,2,3" line.long 0x8 "CAN_ERRIDPR,The CAN_ERRIDPR register holds the error pattern to be injected in the data word read from memory. The CAN_ERRIDPR register is not available when parameter ECC_EN is 0." hexmask.long 0x8 0.--31. 1. "DFLIP,Data Flip Pattern Bits set to 1 in the flip pattern cause the corresponding data bit in the word read from memory to invert." line.long 0xC "CAN_ERRIPPR,The CAN_ERRIPPR register holds the error pattern to be injected in parity bits read from memory along with data word. Bits set to 1 in the flip pattern cause the corresponding parity bit in the word read from memory to invert. The CAN_ERRIPPR.." hexmask.long.byte 0xC 24.--28. 1. "PFLIP3,Parity Flip Pattern For Byte 3 (most significant)" newline hexmask.long.byte 0xC 16.--20. 1. "PFLIP2,Parity Flip Pattern For Byte 2" newline hexmask.long.byte 0xC 8.--12. 1. "PFLIP1,Parity Flip Pattern For Byte 2" newline hexmask.long.byte 0xC 0.--4. 1. "PFLIP0,Parity Flip Pattern For Byte O (least significant)" rgroup.long 0xAF0++0xB line.long 0x0 "CAN_RERRAR,The CAN_RERRAR register reports the address used for an access in which an error (correctable or non-correctable) was detected. and reports the identification of the source of that access. The address is always reported using a 32-bit.." bitfld.long 0x0 24. "NCE,Non-Correctable Error - Indicates that the report is due to a non-correctable error: - 1: Reporting a non-correctable error - 0: Reporting a correctable-error" "Reporting a correctable-error,Reporting a non-correctable error" newline bitfld.long 0x0 16.--18. "SAID,SAID[2] - Identification of the requestor of the memory read request: - 0: Requested by FlexCAN internal processes - 1: Requested by host (CPU) SAID[1] - Details of FlexCAN operation: - 0: Move - 1: Scanning SAID[0] - Operation that requested the.." "Transmission,Reception,?,?,?,?,?,?" newline hexmask.long.word 0x0 0.--13. 1. "ERRADDR,Address Where the Error was Detected" line.long 0x4 "CAN_RERRDR,The CAN_RERRDR register reports the raw data (unmodified by the correction performed by ECC logic) read from memory with error. The value reported does not represent the transient values of the BUSY bit when reading a message buffer. The.." hexmask.long 0x4 0.--31. 1. "RDATA,Raw data word read from memory with error." line.long 0x8 "CAN_RERRSYNR,The CAN_RERRSYNR register holds the syndrome detected in a memory read with error. It also reports the bytes that were read in this 32-bit read transaction." bitfld.long 0x8 31. "BE3,Byte Enabled For Byte 3 (most significant) - 1: The byte was read. - 0: The byte was not read." "The byte was not read,The byte was read" newline hexmask.long.byte 0x8 24.--28. 1. "SYND3,Error Syndrome For Byte 3 (most significant)" bitfld.long 0x8 23. "BE2,Byte Enabled for Byte 2." "0,1" newline hexmask.long.byte 0x8 16.--20. 1. "SYND2,Error Syndrome For Byte 2" newline bitfld.long 0x8 15. "BE1,Byte Enabled for Byte 1." "0,1" newline hexmask.long.byte 0x8 8.--12. 1. "SYND1,Error Syndrome For Byte 1" bitfld.long 0x8 7. "BE0,Byte Enabled for Byte 0 (least significant)." "0,1" newline hexmask.long.byte 0x8 0.--4. 1. "SYND0,Error Syndrome For Byte O (least significant)" group.long 0xAFC++0x2B line.long 0x0 "CAN_ERRSR,The CAN_ERRSR register holds the status bits of the error correction and detection operations. These flags can be cleared by writing 1 to them. Writing O has no effect. The CAN_ERRSR register is not available when parameter ECC_EN is 0." bitfld.long 0x0 19. "HANCEIF,FlexCAN Access With Non-Correctable Error Interrupt Flag: - 1: A non-correctable error was detected in a FlexCAN access. - 0: No non-correctable errors were detected in FlexCAN accesses so far. FANCEIF = 1 indicates that a non-correctable error.." "No non-correctable errors were detected in..,A non-correctable error was detected in a.." newline bitfld.long 0x0 18. "FANCEIF,FlexCAN Access With Non-Correctable Error Interrupt Flag: - 1: A non-correctable error was detected in a FlexCAN access. - 0: No non-correctable errors were detected in FlexCAN accesses so far. FANCEIF = 1 indicates that a non-correctable error.." "No non-correctable errors were detected in..,A non-correctable error was detected in a.." newline bitfld.long 0x0 16. "CEIF,Correctable Error Interrupt Flag: - 1: A correctable error was detected. - 0: No correctable errors were detected so far. CEIF = 1 indicates that a correctable error was detected in a memory read. If CAN_MECR.CEI_MSK is set the interrupt is asserted." "No correctable errors were detected so far,A correctable error was detected" newline bitfld.long 0x0 3. "HANCEIOF,Host Access With Non-Correctable Error Interrupt Overrun Flag: - 1: Overrun on non-correctable errors in host access. - 0: No overrun on non-correctable errors in host access. HANCEIOF = 1 indicates that a non-correctable error was detected in a.." "No overrun on non-correctable errors in host..,Overrun on non-correctable errors in host access" bitfld.long 0x0 2. "FANCEIOF,FlexCAN Access With Non-Correctable Error Interrupt Overrun Flag: - 1: Overrun on non-correctable errors in FlexCAN access. - 0: No overrun on non-correctable errors in FlexCAN access. FANCEIOF = 1 indicates that a non-correctable error was.." "No overrun on non-correctable errors in FlexCAN..,Overrun on non-correctable errors in FlexCAN.." newline bitfld.long 0x0 0. "CEIOF,Correctable Error Interrupt Overrun Flag: - 1: Overrun on correctable errors. - 0: No overrun on correctable errors. CEIOF = 1 indicates that a correctable error was detected in a memory read when CEIF was set. No interrupt is associated with this.." "No overrun on correctable errors,Overrun on correctable errors" line.long 0x4 "CAN_CTRL1_PN,The CAN_CTRL1_PN register contains control bits for Pretended Networking mode filtering selection. Configure CAN_CTRL1_PN with the filter criteria to be used to receive wakeup messages. CAN_CTRL1_PN bits other than WTOF_MSK and WUMF_MSK can.." bitfld.long 0x4 17. "WTOF_MSK,Wake Up by Timeout Flag Mask Bit - Masks the generation of a wakeup event originated by a timeout: - 1: Timeout wakeup event is enabled. - 0: Timeout wakeup event is disabled." "Timeout wakeup event is disabled,Timeout wakeup event is enabled" newline bitfld.long 0x4 16. "WUMF_MSK,Wake Up by Match Flag Mask Bit - Masks the generation of a wakeup event originated by a successful filtered Rx message - 1: Wakeup match event is enabled. - 0: Wakeup match event is disabled." "Wakeup match event is disabled,Wakeup match event is enabled" hexmask.long.byte 0x4 8.--15. 1. "NMATCH,Number of Messages Matching the Same Filtering Criteria NMATCH defines the number of times a given message must match the predefined filtering criteria for ID and/or PL before generating a wakeup event. This quantity can be configured in the 1 to.." newline bitfld.long 0x4 4.--5. "PLFS,Payload Filtering Selection - Selects the level of payload filtering to be applied when FlexCAN is under Pretended Networking mode: - 00: Match upon a payload contents against an exact target value. - 01: Match upon a payload value greater than or.." "Match upon a payload contents against an exact..,Match upon a payload value greater than or equal..,?,?" newline bitfld.long 0x4 2.--3. "IDFS,ID Filtering Selection - Selects the level of ID filtering to be applied when FlexCAN is under Pretended Networking mode: - 00: Match upon a ID contents against an exact target value. - 01: Match upon a ID value greater than or equal to a specified.." "Match upon a ID contents against an exact target..,Match upon a ID value greater than or equal to a..,?,?" bitfld.long 0x4 0.--1. "FCS,Filtering Combination Selection - Selects the filtering criteria to be applied when FlexCAN is under Pretended Networking mode: - 00: Message ID filtering only. - 01: Message ID filtering and payload filtering. - 10: Message ID filtering occurring a.." "Message ID filtering only,Message ID filtering and payload filtering,?,?" line.long 0x8 "CAN_CTRL2_PN,The CAN_CTRL2_PN register contains configuration bits for the timeout value under Pretended Networking mode. CAN_CTRL2_PN can be written in Freeze mode only. The CAN_CTRL2_PN register is not available when parameter PNET_EN is 0." hexmask.long.word 0x8 0.--15. 1. "MATCHTO,Timeout for No Message Matching the Filtering Criteria MATCHTO defines a timeout value that generates a wakeup event if CAN_MCR.PNET _EN is asserted. If the timeout counter reaches the target value when the FlexCAN is under Pretended Networking.." line.long 0xC "CAN_WU_MTC,The CAN_WU_MTC register contains wakeup information related to the matching processes performed while the FlexCAN receives frames under Pretended Networking mode. The CAN_WU_MTC register is not available when parameter PNET_EN is 0." bitfld.long 0xC 17. "WTOF,Wake Up by Timeout Flag Bit - Indicates whether the FlexCAN has detected a timeout event during a time interval defined by CAN CTRL2 PN.MATCHTO: - 1: Wakeup by timeout event detected. - 0: No wakeup by timeout event detected. WTOF generates a wakeup.." "No wakeup by timeout event detected,Wakeup by timeout event detected" newline bitfld.long 0xC 16. "WUMF,Wake Up by Match Flag Bit - Indicates whether the FlexCAN has detected a matching Rx incoming message that passed the filtering criteria specified in CAN_CTRL1_PN: - 1: Wakeup by match event detected. - 0: No wakeup by match event detected. WUMF.." "No wakeup by match event detected,Wakeup by match event detected" hexmask.long.byte 0xC 8.--15. 1. "MCOUNTER,Number of Matches while in Pretended Networking MCOUNTER reports the number of times a given message has matched the predefined filtering criteria for ID and/or PL before a wakeup event. MCOUNTER is reset by the FlexCAN when it enters in.." newline line.long 0x10 "CAN_FLT_ID1,The CAN_FLT_1D1 register contains the FLT_1D1 target value and the IDE and RTR target values used to filter an incoming message ID. FLT_1D1 is used either for equal to. smaller than. greater than comparisons. or as the lower limit value in an.." bitfld.long 0x10 30. "FLT_IDE,ID Extended Filter - Identifies whether the frame format is standard or extended: - 1: Accept extended frame format. - 0: Accept standard frame format. FLT_IDE is used as part of the ID reception filter." "Accept standard frame format,Accept extended frame format" newline bitfld.long 0x10 29. "FLT_RTR,Remote Transmission Request Filter - Identifies whether the frame is remote or not: - 1: Accept remote frame. - 0: Reject remote frame (accept data frame). FLT_RTR is used as part of the ID reception Filter." "Reject remote frame,Accept remote frame" hexmask.long 0x10 0.--28. 1. "FLT_ID1,ID Filter 1 for Pretended Networking Filtering - Defines either the 29 bits of an extended frame format considering all bits or the 11 bits of a standard frame format considering just the 11 leftmost bits." line.long 0x14 "CAN_FLT_DLC,The CAN_FLT_DLC register contains the DLC inside range target values (FLT_DLC_LO and FLT_DLC_HI) used to filter an incoming message. The DLC range is used only for payload filtering. CAN_FLT_DLC can be written in Freeze mode only. NOTE: When.." hexmask.long.byte 0x14 16.--19. 1. "FLT_DLC_LO,Lower Limit for Length of Data Bytes Filter - Specifies the lower limit for the number of data bytes considered valid for payload comparison. FLT_DLC_LO is used as part of payload reception Filter." newline hexmask.long.byte 0x14 0.--3. 1. "FLT_DLC_HI,Upper Limit for Length of Data Bytes Filter - Specifies the upper limit for the number of data bytes considered valid for payload comparison. FLT_DLC_HI is used as part of payload reception filter." line.long 0x18 "CAN_PL1_LO,The CAN_PL1_LO register contains Payload Filter 1 low order bits of the target value used to filter incoming message payload. It is used either for 'equal to'. 'smaller than or equal to'. 'greater than or equal to' comparisons. or as the lower.." hexmask.long.byte 0x18 24.--31. 1. "DATA_BYTE_0,Filter 1 low order bits for Pretended Networking payload fittermg corresponding to data byte 0." hexmask.long.byte 0x18 16.--23. 1. "DATA_BYTE_1,Filter 1 low order bits for Pretended Networking payload fittermg corresponding to data byte 1." newline hexmask.long.byte 0x18 8.--15. 1. "DATA_BYTE_2,Filter 1 low order bits for Pretended Networking payload fittermg corresponding to data byte 2." hexmask.long.byte 0x18 0.--7. 1. "DATA_BYTE_3,Filter 1 low order bits for Pretended Networking payload fittermg corresponding to data byte 3." line.long 0x1C "CAN_PL1_HI,The CAN_PL1_HI register contains Payload Filter 1 high order bits of the target value used to filter incoming message payload. It is used either for 'equal to'. 'smaller than or equal to'. 'greater than or equal to' comparisons. or as the.." hexmask.long.byte 0x1C 24.--31. 1. "DATA_BYTE_4,Filter 1 low order bits for Pretended Networking payload filtermg corresponding to data byte 4." hexmask.long.byte 0x1C 16.--23. 1. "DATA_BYTE_5,Filter 1 low order bits for Pretended Networking payload filtermg corresponding to data byte 5." newline hexmask.long.byte 0x1C 8.--15. 1. "DATA_BYTE_6,Filter 1 low order bits for Pretended Networking payload filtermg corresponding to data byte 6." hexmask.long.byte 0x1C 0.--7. 1. "DATA_BYTE_7,Filter 1 low order bits for Pretended Networking payload filtermg corresponding to data byte 7." line.long 0x20 "CAN_FLT_ID2_IDMASK,The CAN_FLT_ID2_1DMASK register contains the FLT_ID2 target value used only as the upper limit value in ID range detection. Also. when exact ID filtering criteria is selected. CAN_FLT_ID2_1DMASK is used to store the ID mask. The.." bitfld.long 0x20 30. "IDE_MSK,ID Extended Mask Bit - Indicates whether the frame format (standard/extended) is used as part of the ID reception filter - 1: The corresponding bit in the filter is checked. - 0: The corresponding bit in the filter is 'don't care'." "The corresponding bit in the filter is 'don't..,The corresponding bit in the filter is checked" newline bitfld.long 0x20 29. "RTR_MSK,Remote Transmission Request Mask Bit - Indicates whether the frame type (data/remote) is part of the ID reception filter: - 1: The corresponding bit in the filter is checked. - 0: The corresponding bit in the filter is 'don't care'." "The corresponding bit in the filter is 'don't..,The corresponding bit in the filter is checked" hexmask.long 0x20 0.--28. 1. "FLT_ID2_IDMASK,ID Filter 2 for Pretended Networking Filtering / ID Mask Bits for Pretended Networking ID Filtering FLT_ID2_1DMASK is used as FLT_ID2 in range of ID filtering to define the ID filter value in either: - Extended frame format (29 bits).." line.long 0x24 "CAN_PL2_PLMASK_LO,The CAN_PL2_PLMASK_LO register has two functions: - It contains the low order bits for the Payload Filter 2 used only as the upper limit value in a payload range detection. - When exact payload filtering criteria is selected." hexmask.long.byte 0x24 24.--31. 1. "DATA_BYTE_0,Payload Filter 2 low order bits / Payload Mask low order bits for Pretended Networking payload filtering corresponding to data byte 0." hexmask.long.byte 0x24 16.--23. 1. "DATA_BYTE_1,Payload Filter 2 low order bits / Payload Mask low order bits for Pretended Networking payload filtering corresponding to data byte 1." newline hexmask.long.byte 0x24 8.--15. 1. "DATA_BYTE_2,Payload Filter 2 low order bits / Payload Mask low order bits for Pretended Networking payload filtering corresponding to data byte 2." hexmask.long.byte 0x24 0.--7. 1. "DATA_BYTE_3,Payload Filter 2 low order bits / Payload Mask low order bits for Pretended Networking payload filtering corresponding to data byte 3." line.long 0x28 "CAN_PL2_PLMASK_HI,The CAN_PL2_PLMASK_HI register has two functions: - It contains the high order bits for the Payload Filter 2 used only as the upper limit value in a payload range detection. - When exact payload filtering criteria is selected." hexmask.long.byte 0x28 24.--31. 1. "DATA_BYTE_4,Payload Filter 2 high order bits / Payload Mask high order bits for Pretended Networking payload filtering corresponding to data byte 4." hexmask.long.byte 0x28 16.--23. 1. "DATA_BYTE_5,Payload Filter 2 high order bits / Payload Mask high order bits for Pretended Networking payload filtering corresponding to data byte 5." newline hexmask.long.byte 0x28 8.--15. 1. "DATA_BYTE_6,Payload Filter 2 high order bits / Payload Mask high order bits for Pretended Networking payload filtering corresponding to data byte 6." hexmask.long.byte 0x28 0.--7. 1. "DATA_BYTE_7,Payload Filter 2 high order bits / Payload Mask high order bits for Pretended Networking payload filtering corresponding to data byte 7." rgroup.long 0xB40++0x37 line.long 0x0 "CAN_WMB0_CS,Wake Up Message Buffer Register for C/S 0. Each of the four WMBs contains a register to store the Control Status (C/S) information (IDE. RTR. and DLC fields) of an incoming Rx message. NOTE: The C/S registers are located at 0x840 for WMB 0." bitfld.long 0x0 22. "SRR,Substitute Remote Request - Can be received either recessive or dominant." "0,1" newline bitfld.long 0x0 21. "IDE,ID Extended Bit - Identifies whether the frame format is standard or extended: - 1: Frame format is extended. - 0: Frame format is standard." "Frame format is standard,Frame format is extended" bitfld.long 0x0 20. "RTR,Remote Transmission Request Bit - Identifies whether the frame is remote or not: - 1: Frame is a remote frame. - 0: Frame is data frame (not remote)." "Frame is data frame,Frame is a remote frame" newline hexmask.long.byte 0x0 16.--19. 1. "DLC,Length of Data in Bytes - Length (in bytes) of the Rx data received when FlexCAN is in Pretended Networking mode. DLC is written by the FlexCAN module copied from the DLC (Data Length Code) field of the received frame. The DLC field indicates which.." line.long 0x4 "CAN_WMB0_ID,Wake Up Message Buffer Register for ID 0.Each of the four WMBs contains a register to store the ID information of an incoming Rx message. NOTE: The ID registers are located at 0x844 for WMB 0 . 0x854 for WMB1. 0x864 for WMB2. and 0x874 for.." hexmask.long 0x4 0.--28. 1. "ID,Received ID under Pretended Networking Mode - Stores the received ID as either: - The 29 bits of the extended frame format (considering the ID[28:0] field) or - The 11 bits of the standard frame format (considering the ID[28:18] field only. The.." line.long 0x8 "CAN_WMB0_D03,Wake Up Message Buffer Register for Data 0-3 0.Each of the four WMBs contains a register to store the data bytes O to 3 of the payload information of an incoming Rx message. This register's content is cleared when the incoming matched.." hexmask.long.byte 0x8 24.--31. 1. "DATA_BYTE_0,Received payload corresponding to data byte 0 under Pretended Networking mode." hexmask.long.byte 0x8 16.--23. 1. "DATA_BYTE_1,Received payload corresponding to data byte 1 under Pretended Networking mode." newline hexmask.long.byte 0x8 8.--15. 1. "DATA_BYTE_2,Received payload corresponding to data byte 2 under Pretended Networking mode." hexmask.long.byte 0x8 0.--7. 1. "DATA_BYTE_3,Received payload corresponding to data byte 3 under Pretended Networking mode." line.long 0xC "CAN_WMB0_D47,Wake Up Message Buffer Register for Data 4-7 0. Each of the four WMBs contains a register to store the data bytes 4 to 7 of the payload information of an incoming Rx message. This register's content is cleared when the incoming matched.." hexmask.long.byte 0xC 24.--31. 1. "DATA_BYTE_4,Received payload corresponding to data byte 4 under Pretended Networking mode." hexmask.long.byte 0xC 16.--23. 1. "DATA_BYTE_5,Received payload corresponding to data byte 5 under Pretended Networking mode." newline hexmask.long.byte 0xC 8.--15. 1. "DATA_BYTE_6,Received payload corresponding to data byte 6 under Pretended Networking mode." hexmask.long.byte 0xC 0.--7. 1. "DATA_BYTE_7,Received payload corresponding to data byte 7 under Pretended Networking mode." line.long 0x10 "CAN_WMB1_CS,Wake Up Message Buffer Register for C/S 1. Each of the four WMBs contains a register to store the Control Status (C/S) information (IDE. RTR. and DLC fields) of an incoming Rx message. NOTE: The C/S registers are located at 0x840 for WMB 0." bitfld.long 0x10 22. "SRR,Substitute Remote Request - Can be received either recessive or dominant." "0,1" newline bitfld.long 0x10 21. "IDE,ID Extended Bit - Identifies whether the frame format is standard or extended: - 1: Frame format is extended. - 0: Frame format is standard." "Frame format is standard,Frame format is extended" bitfld.long 0x10 20. "RTR,Remote Transmission Request Bit - Identifies whether the frame is remote or not: - 1: Frame is a remote frame. - 0: Frame is data frame (not remote)." "Frame is data frame,Frame is a remote frame" newline hexmask.long.byte 0x10 16.--19. 1. "DLC,Length of Data in Bytes - Length (in bytes) of the Rx data received when FlexCAN is in Pretended Networking mode. DLC is written by the FlexCAN module copied from the DLC (Data Length Code) field of the received frame. The DLC field indicates which.." line.long 0x14 "CAN_WMB1_ID,Wake Up Message Buffer Register for ID 1.Each of the four WMBs contains a register to store the ID information of an incoming Rx message. NOTE: The ID registers are located at 0x844 for WMB 0. 0x854 for WMB1. 0x864 for WMB2. and 0x874 for.." hexmask.long 0x14 0.--28. 1. "ID,Received ID under Pretended Networking Mode - Stores the received ID as either: - The 29 bits of the extended frame format (considering the ID[28:0] field) or - The 11 bits of the standard frame format (considering the ID[28:18] field only. The.." line.long 0x18 "CAN_WMB1_D03,Wake Up Message Buffer Register for Data 0-3 1. Each of the four WMBs contains a register to store the data bytes 4 to 7 of the payload information of an incoming Rx message. This register's content is cleared when the incoming matched.." hexmask.long.byte 0x18 24.--31. 1. "Data_byte_0,Data_byte_0" hexmask.long.byte 0x18 16.--23. 1. "Data_byte_1,Data_byte_1" newline hexmask.long.byte 0x18 8.--15. 1. "Data_byte_2,Data_byte_2" hexmask.long.byte 0x18 0.--7. 1. "Data_byte_3,Data_byte_3" line.long 0x1C "CAN_WMB1_D47,Wake Up Message Buffer Register for Data 4-7 1.Each of the four WMBs contains a register to store the data bytes 4 to 7 of the payload information of an incoming Rx message. This register's content is cleared when the incoming matched.." hexmask.long.byte 0x1C 24.--31. 1. "DATA_BYTE_4,Received payload corresponding to data byte 4 under Pretended Networking mode." hexmask.long.byte 0x1C 16.--23. 1. "DATA_BYTE_5,Received payload corresponding to data byte 5 under Pretended Networking mode." newline hexmask.long.byte 0x1C 8.--15. 1. "DATA_BYTE_6,Received payload corresponding to data byte 6 under Pretended Networking mode." hexmask.long.byte 0x1C 0.--7. 1. "DATA_BYTE_7,Received payload corresponding to data byte 7 under Pretended Networking mode." line.long 0x20 "CAN_WMB2_CS,Wake Up Message Buffer Register for C/S 2.Each of the four WMBs contains a register to store the Control Status (C/S) information (IDE. RTR. and DLC fields) of an incoming Rx message. NOTE: The C/S registers are located at 0x840 for WMB 0." bitfld.long 0x20 22. "SRR,Substitute Remote Request - Can be received either recessive or dominant." "0,1" newline bitfld.long 0x20 21. "IDE,ID Extended Bit - Identifies whether the frame format is standard or extended: - 1: Frame format is extended. - 0: Frame format is standard." "Frame format is standard,Frame format is extended" bitfld.long 0x20 20. "RTR,Remote Transmission Request Bit - Identifies whether the frame is remote or not: - 1: Frame is a remote frame. - 0: Frame is data frame (not remote)." "Frame is data frame,Frame is a remote frame" newline hexmask.long.byte 0x20 16.--19. 1. "DLC,Length of Data in Bytes - Length (in bytes) of the Rx data received when FlexCAN is in Pretended Networking mode. DLC is written by the FlexCAN module copied from the DLC (Data Length Code) field of the received frame. The DLC field indicates which.." line.long 0x24 "CAN_WMB2_ID,Wake Up Message Buffer Register for ID 2. Each of the four WMBs contains a register to store the ID information of an incoming Rx message. NOTE: The ID registers are located at 0x844 for WMB 0. 0x854 for WMB1. 0x864 for WMB2. and 0x874 for.." hexmask.long 0x24 0.--28. 1. "ID,Received ID under Pretended Networking Mode - Stores the received ID as either: - The 29 bits of the extended frame format (considering the ID[28:0] field) or - The 11 bits of the standard frame format (considering the ID[28:18] field only. The.." line.long 0x28 "CAN_WMB2_D03,Wake Up Message Buffer Register for Data 0-3 2.Each of the four WMBs contains a register to store the data bytes 4 to 7 of the payload information of an incoming Rx message. This register's content is cleared when the incoming matched.." hexmask.long.byte 0x28 24.--31. 1. "Data_byte_0,Data_byte_0" hexmask.long.byte 0x28 16.--23. 1. "Data_byte_1,Data_byte_1" newline hexmask.long.byte 0x28 8.--15. 1. "Data_byte_2,Data_byte_2" hexmask.long.byte 0x28 0.--7. 1. "Data_byte_3,Data_byte_3" line.long 0x2C "CAN_WMB2_D47,Wake Up Message Buffer Register for Data 4-7 2. Each of the four WMBs contains a register to store the data bytes 4 to 7 of the payload information of an incoming Rx message. This register's content is cleared when the incoming matched.." hexmask.long.byte 0x2C 24.--31. 1. "DATA_BYTE_4,Received payload corresponding to data byte 4 under Pretended Networking mode." hexmask.long.byte 0x2C 16.--23. 1. "DATA_BYTE_5,Received payload corresponding to data byte 5 under Pretended Networking mode." newline hexmask.long.byte 0x2C 8.--15. 1. "DATA_BYTE_6,Received payload corresponding to data byte 6 under Pretended Networking mode." hexmask.long.byte 0x2C 0.--7. 1. "DATA_BYTE_7,Received payload corresponding to data byte 7 under Pretended Networking mode." line.long 0x30 "CAN_WMB3_CS,Wake Up Message Buffer Register for C/S 3.Each of the four WMBs contains a register to store the Control Status (C/S) information (IDE. RTR. and DLC fields) of an incoming Rx message. NOTE: The C/S registers are located at 0x840 for WMB 0." bitfld.long 0x30 22. "SRR,Substitute Remote Request - Can be received either recessive or dominant." "0,1" newline bitfld.long 0x30 21. "IDE,ID Extended Bit - Identifies whether the frame format is standard or extended: - 1: Frame format is extended. - 0: Frame format is standard." "Frame format is standard,Frame format is extended" bitfld.long 0x30 20. "RTR,Remote Transmission Request Bit - Identifies whether the frame is remote or not: - 1: Frame is a remote frame. - 0: Frame is data frame (not remote)." "Frame is data frame,Frame is a remote frame" newline hexmask.long.byte 0x30 16.--19. 1. "DLC,Length of Data in Bytes - Length (in bytes) of the Rx data received when FlexCAN is in Pretended Networking mode. DLC is written by the FlexCAN module copied from the DLC (Data Length Code) field of the received frame. The DLC field indicates which.." line.long 0x34 "CAN_WMB3_ID,Wake Up Message Buffer Register for ID 3. Each of the four WMBs contains a register to store the ID information of an incoming Rx message. NOTE: The ID registers are located at 0x844 for WMB 0. 0x854 for WMB1. 0x864 for WMB2. and 0x874 for.." hexmask.long 0x34 0.--28. 1. "ID,Received ID under Pretended Networking Mode - Stores the received ID as either: - The 29 bits of the extended frame format (considering the ID[28:0] field) or - The 11 bits of the standard frame format (considering the ID[28:18] field only. The.." repeat 2. (list 0x3 0x2F )(list 0x0 0x4 ) rgroup.long ($2+0xB78)++0x3 line.long 0x0 "CAN_WMB3_D$1,Wake Up Message Buffer Register for Data 0-3 3. Each of the four WMBs contains a register to store the data bytes 4 to 7 of the payload information of an incoming Rx message. This register's content is cleared when the incoming matched.." hexmask.long.byte 0x0 24.--31. 1. "Data_byte_0,Data_byte_0" hexmask.long.byte 0x0 16.--23. 1. "Data_byte_1,Data_byte_1" newline hexmask.long.byte 0x0 8.--15. 1. "Data_byte_2,Data_byte_2" hexmask.long.byte 0x0 0.--7. 1. "Data_byte_3,Data_byte_3" repeat.end group.long 0xC00++0x7 line.long 0x0 "CAN_FDCTRL,The CAN_FDCTRL register contains control bits for CAN FD operation. CAN_FDCTRL also defines the data size of message buffers allocated in different partitions of RAM (memory blocks). When an 8-byte payload is selected: - Block RO allocates.." bitfld.long 0x0 31. "FDRATE,Bit Rate Switch Enable - Enables the effect of the Bit Rate Switch (BRS bit) during the data phase of Tx messages: - 1: Transmit a frame with bit rate switching if the BRS bit in the Tx MB is recessive. - 0: Transmit a frame in nominal rate. The.." "Transmit a frame in nominal rate,Transmit a frame with bit rate switching if the.." newline bitfld.long 0x0 25.--26. "MBDSR3,Message Buffer Data Size for Region 3 - Selects the data size for region R3 of message buffers allocated in RAM: - 00: Selects 8 bytes per message buffer. - 01: Selects 16 bytes per message buffer. - 10: Selects 32 bytes per message buffer. - 11:.." "Selects 8 bytes per message buffer,Selects 16 bytes per message buffer,?,Selects the data size for region R3 of message.." newline bitfld.long 0x0 22.--23. "MBDSR2,Message Buffer Data Size for Region 2 - Selects the data size for region R2 of message buffers allocated in RAM: - 00: Selects 8 bytes per message buffer. - 01: Selects 16 bytes per message buffer. - 10: Selects 32 bytes per message buffer. - 11:.." "Selects 8 bytes per message buffer,Selects 16 bytes per message buffer,Selects the data size for region R2 of message..,?" newline bitfld.long 0x0 19.--20. "MBDSR1,Message Buffer Data Size for Region 1 - Selects the data size for region R1 of message buffers allocated in RAM: - 00: Selects 8 bytes per message buffer. - 01: Selects 16 bytes per message buffer. - 10: Selects 32 bytes per message buffer. - 11:.." "Selects 8 bytes per message buffer,Selects 16 bytes per message buffer,?,?" newline bitfld.long 0x0 16.--17. "MBDSR0,Message Buffer Data Size for Region O - Selects the data size for region RO of message buffers allocated in RAM: - 00: Selects 8 bytes per message buffer. - 01: Selects 16 bytes per message buffer. - 10: Selects 32 bytes per message buffer. - 11:.." "Selects 8 bytes per message buffer,Selects 16 bytes per message buffer,?,?" bitfld.long 0x0 15. "TDCEN,Transceiver Delay Compensation Enable - Enables or disables the TDC feature: - 1: TDC is enabled. - 0: TDC is disabled. TDCEN can be written in Freeze mode only. Note: TDC must be disabled when Loop-Back mode is enabled (see CAN_CTRL1.LPB). Note:.." "TDC is disabled,TDC is enabled" newline bitfld.long 0x0 14. "TDCFAIL,Transceiver Delay Compensation Fail TDCFAIL indicates when the Transceiver Delay Compensation (TDC) mechanism is out of range unable to compensate the transceiver's loop delay and successfully compare the delayed received bits to the.." "Measured loop delay is in range,Measured loop delay is out of range" newline hexmask.long.byte 0x0 8.--12. 1. "TDCOFF,Transceiver Delay Compensation Offset TDCOFF contains the offset value to be added to the measured transceiver's loop delay in order to define the position of the delayed comparison point when bit rate switching is active. TDCOFF can be written in.." newline hexmask.long.byte 0x0 0.--5. 1. "TDCVAL,Transceiver Delay Compensation Value TDCVAL contains the value of the transceiver loop delay measured from the transmitted EDL to RO transition edge to the respective received one added to the TDCOFF value. This value is an integer multiple of the.." line.long 0x4 "CAN_FDCBT,The CAN_FDCBT register stores the CAN bit timing variables used in the data phase of CAN FD messages when CAN_FDCTRL.FDRATE is set. compatible with CAN FD specification. FPRESDIV. FPROPSEG. FPSEG1. FPSEG2. and FRJW are used to define the time.." hexmask.long.word 0x4 20.--29. 1. "FPRESDIV,Fast Prescaler Division Factor FPRESDIV defines the ratio between the PE clock frequency and the Serial Clock (Sclock) frequency in the data bit rate portion of a CAN FD message with the BRS bit set. The Sclock period defines the time quantum of.." newline bitfld.long 0x4 16.--18. "FRJW,Fast Resync Jump Width FRJW defines the maximum number of time quanta that a bit time can be changed by one re-synchronization in the data bit rate portion of a CAN FD message with the BRS bit set. Resync Jump Width = FSJW + 1. One time quantum is.." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x4 10.--14. 1. "FPROPSEG,Fast Propagation Segment FPROPSEG defines the length of the Propagation Segment in the bit time in the data bit rate portion of a CAN FD message with the BRS bit set. Propagation Segment Time = FPROPSEG x Time-Quanta Time-Quantum = one Sclock.." newline bitfld.long 0x4 5.--7. "FPSEG1,Fast Phase Segment 1 FPSEG1 defines the length of Phase Segment 1 in the bit time in the data bit rate portion of a CAN FD message with the BRS bit set. Phase Segment 1 = (FPSEG1 + 1) x Time-Quanta Time-Quantum = one Sclock period FPSEG1 can be.." "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 0.--2. "FPSEG2,Fast Phase Segment 2 FPSEG2 defines the length of Phase Segment 2 in the data bit rate portion of a CAN FD message with the BRS bit set. Phase Segment 2 = (FPSEG2 + 1) x Time-Quanta Time-Quantum = one Sclock period FPSEG2 can be written only in.." "0,1,2,3,4,5,6,7" rgroup.long 0xC08++0x3 line.long 0x0 "CAN_FDCRC,The CAN_CRCR register provides information about the CRC of transmitted messages for non-FD messages. CAN_CRCR only reports the 15 low order bits of CRC calculations for messages in CAN FD format that require either 17 or 21 bits. For CAN FD.." hexmask.long.byte 0x0 24.--30. 1. "FD_MBCRC,CRC Mailbox - Indicates the number of the mailbox corresponding to the value in the CAN CRCR.TXCRC field." newline hexmask.long.tbyte 0x0 0.--20. 1. "FD_TXCRC,Transmitted CRC Value - Indicates the CRC value of the last transmitted message for non-FD frames. For CAN FD frames the CRC value is reported in CAN_FDCRC." tree.end repeat.end repeat 12. (increment 9. 1.) (list ad:0xF0740000 ad:0xF0750000 ad:0xF0760000 ad:0xF0770000 ad:0xF0780000 ad:0xF0790000 ad:0xF07A0000 ad:0xF07B0000 ad:0xF07C0000 ad:0xF07D0000 ad:0xF07E0000 ad:0xF07F0000) tree "CANFD$1" base $2 group.long 0x0++0xB line.long 0x0 "CAN_MCR,CAN_MCR defines global system configurations. such as the module operation modes and the maximum message buffer configuration." bitfld.long 0x0 31. "MDIS,Module Disable - Disables or enables the FlexCAN module: - 1: Disable the FlexCAN module. - 0: Enable the FlexCAN module. When disabled the FlexCAN disables the clocks to the PE and CHI submodules. MDIS is not affected by soft reset." "Enable the FlexCAN module,Disable the FlexCAN module" bitfld.long 0x0 30. "FRZ,Freeze Enable: - 1: Enabled to enter Freeze mode. - 0: Not enabled to enter Freeze mode. The FRZ bit specifies the FlexCAN behavior when CAN_MCR.HALT is set or when Debug mode is requested at chip level. When FRZ is asserted the FlexCAN is enabled.." "Not enabled to enter Freeze mode,Enabled to enter Freeze mode" newline bitfld.long 0x0 29. "RFEN,Legacy Rx FIFO Enable - Enables or disables the Legacy Rx FIFO feature: - 1: Enable Legacy Rx FIFO. - 0: Disable Legacy Rx FIFO. When RFEN is set MBs 0-5 cannot be used for normal reception and transmission because the corresponding memory region.." "Disable Legacy Rx FIFO,Enable Legacy Rx FIFO" bitfld.long 0x0 28. "HALT,Halt FlexCAN: - 1: Enter Freeze mode if the FRZ bit is asserted. - 0: No Freeze mode request. Assertion of HALT puts the FlexCAN module into Freeze mode. The CPU should clear HALT after initializing the message buffers and the control registers.." "No Freeze mode request,Enter Freeze mode if the FRZ bit is asserted" newline rbitfld.long 0x0 27. "NOTRDY,FlexCAN Not Ready: - 1: FlexCAN is either in Module Disable Doze Stop or Freeze mode. - 0: FlexCAN is either in Normal Listen-Only or Loop-Back mode. NOTRDY is a read-only bit that indicates that the FlexCAN is either in Module Disable Doze.." "FlexCAN is either in Normal,FlexCAN is either in Module Disable" bitfld.long 0x0 26. "WAKMSK,Wake Up Interrupt Mask - Enables Wake Up interrupt generation under the Self Wake Up mechanism: - 1: Enable Wake Up interrupt. - 0: Disable Wake Up interrupt." "Disable Wake Up interrupt,Enable Wake Up interrupt" newline bitfld.long 0x0 25. "SOFTRST,Soft Reset: - 1: Reset the registers affected by soft reset. - 0: No reset request. When SOFTRST is asserted the FlexCAN resets its internal state machines and some of the memory-mapped registers. SOFTRST can be asserted directly by the CPU by.." "No reset request,Reset the registers affected by soft reset" rbitfld.long 0x0 24. "FRZACK,Freeze Mode Acknowledge: - 1: FlexCAN in Freeze mode prescaler stopped. - 0: FlexCAN not in Freeze mode prescaler running. FRZACK is a read-only bit that indicates that the FlexCAN is in Freeze mode and its prescaler is stopped. A Freeze mode.." "FlexCAN not in Freeze mode,FlexCAN in Freeze mode" newline bitfld.long 0x0 23. "SUPV,Supervisor Mode - Configures the FlexCAN to be either in Supervisor or User mode: - 1: FlexCAN is in Supervisor mode. Affected registers allow only Supervisor access. Unrestricted access behaves as though the access was done to an unimplemented.." "FlexCAN is in User mode,FlexCAN is in Supervisor mode" bitfld.long 0x0 22. "SLFWAK,Self Wake Up - Enables the Self Wake Up feature when the FlexCAN is in a low-power mode other than Module Disable: - 1: Enable FlexCAN Self Wake Up feature. - 0: Disable FlexCAN Self Wake Up feature. When the Self Wake Up feature is enabled the.." "Disable FlexCAN Self Wake Up feature,Enable FlexCAN Self Wake Up feature" newline bitfld.long 0x0 21. "WRNEN,Warning Interrupt Enable: - 1: TWRNINT and RWRNINT bits are set when the respective error counter transitions from less than 96 to greater than or equal to 96. - 0: TWRNINT and RWRNINT bits are zero independent of the values in the error counters." "TWRNINT and RWRNINT bits are zero,TWRNINT and RWRNINT bits are set when the.." rbitfld.long 0x0 20. "LPMACK,Low-Power Mode Acknowledge: - 1: FlexCAN is in a low-power mode. - 0: FlexCAN is not in a low-power mode. LPMACK is a read-only bit that indicates that the FlexCAN is in a low-power mode (Module Disable Doze or Stop). A low-power mode cannot be.." "FlexCAN is not in a low-power mode,FlexCAN is in a low-power mode" newline bitfld.long 0x0 19. "WAKSRC,Wake Up Source - Controls whether the integrated low-pass filter is applied to protect the Rx CAN input from spurious wakeup: - 1: FlexCAN uses the filtered Rx input to detect recessive-to- dominant edges on the CAN bus. - 0: FlexCAN uses the.." "FlexCAN uses the unfiltered Rx input to detect..,FlexCAN uses the filtered Rx input to detect.." bitfld.long 0x0 18. "DOZE,Doze Mode Enable - Controls whether the FlexCAN is allowed to enter low-power mode when Doze mode is requested at chip level: - 1: FlexCAN is enabled to enter low-power mode when Doze mode is requested. - 0: FlexCAN is not enabled to enter low-power.." "FlexCAN is not enabled to enter low-power mode..,FlexCAN is enabled to enter low-power mode when.." newline bitfld.long 0x0 17. "SRXDIS,Self Reception Disable: - 1: Disable self-reception. - 0: Enable self-reception. SRXDIS controls whether the FlexCAN is allowed to receive frames transmitted by itself. If SRXDIS is asserted frames transmitted by the FlexCAN are not stored in any.." "Enable self-reception,Disable self-reception" bitfld.long 0x0 16. "IRMQ,Individual Rx Masking And Queue Enable: - 1: Enable individual Rx masking and queue feature. - 0: Disable individual Rx masking and queue feature. For backward compatibility with legacy applications the reading of C/S word locks the MB even if it.." "Disable individual Rx masking and queue feature,Enable individual Rx masking and queue feature" newline bitfld.long 0x0 15. "DMA,DMA Enable: - 1: Enable DMA feature for Rx FIFO. - 0: Disable DMA feature for Rx FIFO. The DMA bit enables or disables the DMA feature. The DMA feature can only be used with the Legacy Rx FIFO or the Enhanced Rx FIFO; consequently either.." "Disable DMA feature for Rx FIFO,Enable DMA feature for Rx FIFO" bitfld.long 0x0 14. "PNET_EN,Pretended Networking Enable - Enables the Pretended Networking functionality: - 1: Enable Pretended Networking mode. - 0: Disable Pretended Networking mode. When Pretended Networking is enabled the PE submodule is kept operational in Doze mode.." "Disable Pretended Networking mode,Enable Pretended Networking mode" newline bitfld.long 0x0 13. "LPRIOEN,Local Priority Enable: - 1: Enable Local Priority. - 0: Disable Local Priority. The LPRIOEN bit is provided for backward compatibility with legacy applications. LPRIOEN controls whether the Local Priority feature is enabled or not. Local Priority.." "Disable Local Priority,Enable Local Priority" bitfld.long 0x0 12. "AEN,Abort Enable - Enables the Tx abort mechanism: - 1: Enable abort. - 0: Disable abort. The Tx abort mechanism ensures a safe procedure for aborting a pending transmission so that no frame is sent on the CAN bus without notification." "Disable abort,Enable abort" newline bitfld.long 0x0 11. "FDEN,CAN FD Operation Enable - Enables CAN with Flexible Data rate (CAN FD) operation: - 1: CAN FD is enabled. The FlexCAN is able to receive and transmit messages in both CAN FD and CAN 2.0 formats. - 0: CAN FD is disabled. The FlexCAN is able to.." "CAN FD is disabled,CAN FD is enabled" newline bitfld.long 0x0 8.--9. "IDAM,ID Acceptance Mode - Identifies the format of the Legacy Rx FIFO ID Filter Table elements: - 00: Format A- One full ID (standard and extended) per ID Filter Table element. - 01: Format B - Two full standard IDs or two partial 14-bit (standard and.." "Format A,Format B,?,?" newline hexmask.long.byte 0x0 0.--6. 1. "MAXMB,Number of the Last Message Buffer - Defines the number of the last message buffer that will take part in the matching and arbitration processes. The reset value (OxOF) is equivalent to a 16 message buffer configuration. MAXMB can be written only in.." line.long 0x4 "CAN_CTRL1,The CAN_CTRL1 register is defined for specific FlexCAN control features related to the CAN bus. such as bit-rate. programmable sampling point within an Rx bit. Loop-Back mode. Listen-Only mode. Bus Off recovery behavior. and interrupt enabling.." hexmask.long.byte 0x4 24.--31. 1. "PRESDIV,Prescaler Division Factor - Defines the ratio between the PE clock frequency and the serial clock (Sclock) frequency. The Sclock period defines the time quantum of the CAN protocol. For the reset value the Sclock frequency is equal to the PE.." bitfld.long 0x4 22.--23. "RJW,Resync Jump Width - Defines the maximum number of time quanta that a bit time can be changed by one re-synchronization. One time quantum is equal to the Sclock period. The valid programmable values for RJW are 0-3. RJW can be written only in Freeze.." "0,1,2,3" newline bitfld.long 0x4 19.--21. "PSEG1,Phase Segment 1 - Defines the length of phase segment 1 in the bit time. The valid programmable values are 0-7. PSEG1 can be written only in Freeze mode because it is blocked by hardware in other modes. Phase Buffer Segment 1 = (PSEG1 + 1) x.." "?,Defines the length of phase segment 1 in the bit..,?,?,?,?,?,?" bitfld.long 0x4 16.--18. "PSEG2,Phase Segment 2 - Defines the length of phase segment 2 in the bit time. The valid programmable values are 1-7. PSEG2 can be written only in Freeze mode because it is blocked by hardware in other modes. Phase Buffer Segment 2 = (PSEG2 + 1) x.." "?,?,Defines the length of phase segment 2 in the..,?,?,?,?,?" newline bitfld.long 0x4 15. "BOFFMSK,Bus Off Interrupt Mask - Provides a mask for the Bus Off interrupt (CAN_ESR1.BOFFINT): - 1: Bus Off interrupt enabled. - 0: Bus Off interrupt disabled." "Bus Off interrupt disabled,Bus Off interrupt enabled" bitfld.long 0x4 14. "ERRMSK,Error Interrupt Mask - Provides a mask for the Error interrupt (CAN_ESR 1.ERRINT). - 1: Error interrupt enabled. - 0: Error interrupt disabled." "Error interrupt disabled,Error interrupt enabled" newline bitfld.long 0x4 13. "CLKSRC,CAN Engine Clock Source - Selects the clock source to the PE submodule to be either the peripheral clock or the oscillator clock: - 1: The PE clock source is the peripheral clock. - 0: The PE clock source is the oscillator clock. Under this.." "The PE clock source is the oscillator clock,The PE clock source is the peripheral clock" bitfld.long 0x4 12. "LPB,Loop-Back Mode - Configures the FlexCAN to operate in Loop-Back mode: - 1: Loop-Back enabled. - 0: Loop-Back disabled. In Loop-Back mode the FlexCAN performs an internal loop back that can be used for self-test operation. The bit stream output of.." "Loop-Back disabled,Loop-Back enabled" newline bitfld.long 0x4 11. "TWRNMSK,Tx Warning Interrupt Mask - Provides a mask for the Tx Warning interrupt (CAN-ESR1.TWRNINT): - 1: Tx Warning interrupt enabled. - 0: Tx Warning interrupt disabled. TWRNMSK is read as zero when CAN_MCR.WRNEN is negated. TWRNMSK can be written.." "Tx Warning interrupt disabled,Tx Warning interrupt enabled" bitfld.long 0x4 10. "RWRNMSK,Rx Warning Interrupt Mask - Provides a mask for the Rx Warning interrupt (CAN_ESR1.RWRNINT) - 1: Rx Warning interrupt enabled. - 0: Rx Warning interrupt disabled. RWRNMSK is read as zero when CAN_MCR.WRNEN is negated. RWRNMSK can be written only.." "Rx Warning interrupt disabled,Rx Warning interrupt enabled" newline bitfld.long 0x4 7. "SMP,CAN Bit Sampling - Defines the sampling mode of CAN bits at the Rx input: - 0: One sample is used to determine the bit value. - 1: Three samples are used to determine the value of the received bit:the regular sample (sample point) and two.." "One sample is used to determine the bit value,Three samples are used to determine the value of.." newline bitfld.long 0x4 6. "BOFFREC,Bus Off Recovery - Defines how the FlexCAN recovers from Bus Off state: - 0: Automatic recovering from Bus Off state enabled. - 1: Automatic recovering from Bus Off state disabled. If BOFFREC is negated automatic recovering from Bus Off state.." "Automatic recovering from Bus Off state enabled,Automatic recovering from Bus Off state disabled" bitfld.long 0x4 5. "TSYN,Timer Sync - Enables a mechanism that resets the free-running timer each time a message is received in message buffer 0: - 1: Timer Sync feature enabled. - 0: Timer Sync feature disabled. The Timer Sync feature provides a means to synchronize.." "Timer Sync feature disabled,Timer Sync feature enabled" newline bitfld.long 0x4 4. "LBUF,Lowest Buffer Transmitted First - Defines the ordering mechanism for message buffer transmission: - 1: Lowest number buffer is transmitted first. - 0: Buffer with highest priority is transmitted first. When LBUF is asserted the CAN_MCR.LPRIOEN bit.." "Buffer with highest priority is transmitted first,Lowest number buffer is transmitted first" bitfld.long 0x4 3. "LOM,Listen-Only Mode - Configures the FlexCAN to operate in Listen-Only mode: - 1: FlexCAN module operates in Listen-Only mode. - 0: Listen-Only mode is deactivated. In Listen-Only Mode mode transmission is disabled all error counters described in.." "Listen-Only mode is deactivated,FlexCAN module operates in Listen-Only mode" newline bitfld.long 0x4 0.--2. "PROPSEG,Propagation Segment - Defines the length of the propagation segment in the bit time. The valid programmable values are 0-7. PROPSEG can be written only in Freeze mode because it is blocked by hardware in other modes. Propagation segment time =.." "0,1,2,3,4,5,6,7" line.long 0x8 "CAN_TIMER,The CAN_TIMER register represents a 16-bit free-running counter that can be read and written by the CPU. The timer starts from 0x0 after reset. counts linearly to 0xFFFF. and wraps around. When CAN_CTRL2.TIMER_SRC is asserted. the timer is.." hexmask.long.word 0x8 0.--15. 1. "TIMER,Timer Value - Contains the free-running counter value." group.long 0x10++0x27 line.long 0x0 "CAN_RXMGMASK,The CAN_RXMGMASK register is located in RAM. CAN_RXMGMASK is provided for legacy application support: - When the CAN_MCR.IRMQ bit is negated. CAN_RXMGMASK is always in effect (the bits in the MG field will mask the mailbox filter bits). -.." hexmask.long 0x0 0.--31. 1. "MG,Rx Mailboxes Global Mask Bits: - 0: The corresponding bit in the filter is 'don't care'. - 1: The corresponding bit in the filter is checked. The MG bits mask the mailbox filter bits. Note that the alignment with the ID word of the mailbox is not.." line.long 0x4 "CAN_RX14MASK,The CAN_RX14MASK register is located in RAM. CAN_RX14MASK is provided for legacy application support. When the CAN_MCR.IRMQ bit is asserted. CAN_RX14MASK has no effect. CAN_RX14MASK is used to mask the filter fields of message buffer 14." hexmask.long 0x4 0.--31. 1. "RX14M,Rx Buffer 14 Mask Bits: - 0: The corresponding bit in the filter is 'don't care'. - 1: The corresponding bit in the filter is checked. Each mask bit masks the corresponding mailbox 14 filter field in the same way that CAN_RXMGMASK masks other.." line.long 0x8 "CAN_RX15MASK,The CAN_RX15MASK register is located in RAM. CAN_RX15MASK is provided for legacy application support. When the CAN_MCR.IRMQ bit is asserted. CAN_RX15MASK has no effect. CAN_RX15MASK is used to mask the filter fields of message buffer 15." hexmask.long 0x8 0.--31. 1. "RX15M,Rx Buffer 15 Mask Bits: - 0: The corresponding bit in the filter is 'don't care'. - 1: The corresponding bit in the filter is checked. Each mask bit masks the corresponding mailbox 15 filter field in the same way that CAN_RXMGMASK masks other.." line.long 0xC "CAN_ECR,The CAN_ECR register has four 8-bit fields reflecting the value of the FlexCAN error counters: - Transmit Error Counter (TXERRCNT field) - Receive Error Counter (RXERRCNT field) - Transmit Error Counter for errors detected in the Data Phase of.." hexmask.long.byte 0xC 24.--31. 1. "RXERRCNT_FAST,Receive Error Counter for Fast Bits - Receive error counter for errors detected in the Data Phase of received CAN FD messages with the BRS bit set. The RXERRCNT_FAST counter is read-only except in Freeze mode in which the CPU can write an.." hexmask.long.byte 0xC 16.--23. 1. "TXERRCNT_FAST,Transmit Error Counter for Fast Bits - Transmit error counter for errors detected in the Data Phase of transmitted CAN FD messages with the BRS bit set. The TXERRCNT_FAST counter is read-only except in Freeze mode in which the CPU can.." newline hexmask.long.byte 0xC 8.--15. 1. "RXERRCNT,Receive Error Counter - Receive error counter for all errors detected in received messages. The RXERRCNT counter is read-only except in Freeze mode in which it can be written by the CPU." hexmask.long.byte 0xC 0.--7. 1. "TXERRCNT,Transmit Error Counter - Transmit error counter for all errors detected in transmitted messages. The TXERRCNT counter is read-only except in Freeze mode in which it can be written by the CPU." line.long 0x10 "CAN_ESR1,Error and Status 1 Register. The CAN_ESR1 register reports various error conditions detected in the reception and transmission of a CAN frame. some general status of the device. and is the source of some interrupts to the CPU." rbitfld.long 0x10 31. "BIT1ERR_FAST,Bit1 Error in the Data Phase of CAN FD Frames with the BRS Bit Set BIT1ERR_FAST indicates when an inconsistency occurs between the transmitted and the received bitin the Data Phase of CAN FD frames with the BRS bit set: - 1: At least one.." "No such occurrence,At least one bit sent as recessive is received.." rbitfld.long 0x10 30. "BIT0ERR_FAST,Bit0 Error in the Data Phase of CAN FD Frames with the BRS Bit Set BIT0ERR_FAST indicates when an inconsistency occurs between the transmitted and the received bit in the Data Phase of CAN FD frames with the BRS bit set: - 1: At least one.." "No such occurrence,At least one bit sent as dominant is received as.." newline rbitfld.long 0x10 28. "CRCERR_FAST,Cyclic Redundancy Check Error in the CRC field of CAN FD Frames with the BRS Bit Set CRCERR_FAST indicates that a CRC error has been detected by the receivernode in the CRC field of CAN FD frames with the BRS bit set; that is the.." "No such occurrence,A CRC error occurred since last read of this.." newline rbitfld.long 0x10 27. "FRMERR_FAST,From Error in the Data Phase of CAN FD Frames with the BRS Bit Set FRMERR_FAST indicates that a form error has been detected by the receiver node in the Data Phase of CAN FD frames with the BRS bit set; that is a fixed-form bit field.." "No such occurrence,A form error occurred since last read of this.." rbitfld.long 0x10 26. "STFERR_FAST,Stuffing Error in the Data Phase of CAN FD Frames with the BRS Bit Set STFERR_FAST indicates that a stuffing error has been detected in the Data Phase of CAN FD frames with the BRS bit set: - 1: A stuffing error occurred since last read of.." "No such occurrence,A stuffing error occurred since last read of.." newline bitfld.long 0x10 21. "ERROVR,Error Overrun - Indicates that an error condition occurred when any error flag is already set: - 1: Overrun has occurred. - 0: Overrun has not occurred. ERROVR is cleared by writing 1 to it." "Overrun has not occurred,Overrun has occurred" newline bitfld.long 0x10 20. "ERRINT_FAST,Error Interrupt for Errors Detected in the Data Phase of CAN FD Frames with the BRS Bit Set: - 1: Indicates setting of any error bit detected in the Data Phase of CAN FD frames with the BRS bit set. - 0: No such occurrence." "No such occurrence,Indicates setting of any error bit detected in.." bitfld.long 0x10 19. "BOFFDONEINT,Bus Off Done Interrupt: - 1: FlexCAN module has completed Bus Off process. - 0: No such occurrence." "No such occurrence,FlexCAN module has completed Bus Off process" newline rbitfld.long 0x10 18. "SYNCH,CAN Synchronization Status: - 1: FlexCAN is synchronized to the CAN bus. - 0: FlexCAN is not synchronized to the CAN bus. SYNCH is a read-only flag that indicates whether the FlexCAN is synchronized to the CAN bus and able to participate in the.." "FlexCAN is not synchronized to the CAN bus,FlexCAN is synchronized to the CAN bus" bitfld.long 0x10 17. "TWRNINT,Tx Warning Interrupt Flag: - 1: The Tx error counter transitioned from less than 96 to greater than or equal to 96. - 0: No such occurrence." "No such occurrence,The Tx error counter transitioned from less than.." newline bitfld.long 0x10 16. "RWRNINT,Rx Warning Interrupt Flag: - 1: The Rx error counter transitioned from less than 96 to greater than or equal to 96. - 0: No such occurrence." "No such occurrence,The Rx error counter transitioned from less than.." rbitfld.long 0x10 15. "BIT1ERR,Bit1 Error - Indicates when an inconsistency occurs between the transmitted and the received bit in a non-CAN FD message or in the arbitration or Data Phase of a CAN FD message: - 1: At least one bit sent as recessive is received as dominant. -.." "No such occurrence,At least one bit sent as recessive is received.." newline rbitfld.long 0x10 14. "BIT0ERR,Bit0 Error - Indicates when an inconsistency occurs between the transmitted and the received bit in a non-CAN FD message or in the arbitration or Data Phase of a CAN FD message: - 1: At least one bit sent as dominant is received asrecessive. -.." "No such occurrence,At least one bit sent as dominant is received.." rbitfld.long 0x10 13. "ACKERR,Acknowledge Error - Indicates that an Acknowledge error was detected by the transmitter node (that is a dominant bit was detected during the ACK SLOT): - 1: An ACK error occurred since last read of this register. - 0: No such occurrence. ACKERR.." "No such occurrence,An ACK error occurred since last read of this.." newline rbitfld.long 0x10 12. "CRCERR,Cyclic Redundancy Check Error - Indicates that a CRC error was detected by the receiver node either in a non-FD message or in the arbitration or Data Phase of a frame in CAN FD format (that is the calculated CRC is different from the received.." "No such occurrence,A CRC error occurred since last read of this.." rbitfld.long 0x10 11. "FRMERR,Form Error - Indicates that a form error was detected by the receiver node in a non-FD message or in a CAN FD message arbitration or Data Phase (that is a fixed-form bit field contains at least one illegal bit): - 1: A form error occurred since.." "No such occurrence,A form error occurred since last read of this.." newline rbitfld.long 0x10 10. "STFERR,Stuffing Error - Indicates that a stuffing error was detected by the receiver node in a non-FD message or in a CAN FD message arbitration or Data Phase: - 1: A stuffing error occurred since last read of this register. - 0: No such occurrence." "No such occurrence,A stuffing error occurred since last read of.." rbitfld.long 0x10 9. "TXWRN,TX Error Warning - Indicates when repetitive errors are occurring during message transmission: - 1: TXERRCNT is greater than or equal to 96. - 0: No such occurrence. TXWRN is affected by the value of CAN_ECR.TXERRCNT only. TXWRN is not updated.." "No such occurrence,TXERRCNT is greater than or equal to 96" newline rbitfld.long 0x10 8. "RXWRN,Rx Error Warning - Indicates when repetitive errors are occurring during message reception: - 1: RXERRCNT is greater than or equal to 96. - 0: No such occurrence. RXWRN is affected by the value of CAN_ECR.RXERRCNT only. RXWRN is not updated during.." "No such occurrence,RXERRCNT is greater than or equal to 96" rbitfld.long 0x10 7. "IDLE,IDLE - Indicates when the CAN bus is in the IDLE state: - 1: CAN bus is now IDLE. - 0: No such occurrence." "No such occurrence,CAN bus is now IDLE" newline rbitfld.long 0x10 6. "TX,FlexCAN in Transmission - Indicates if the FlexCAN is transmitting a message: - 1: FlexCAN is transmitting a message. - 0: FlexCAN is not transmitting a message." "FlexCAN is not transmitting a message,FlexCAN is transmitting a message" rbitfld.long 0x10 4.--5. "FLTCONF,Fault Confinement State - Indicates the fault confinement state of the FlexCAN module: - 00: Error Active - 01: Error Passive - 1x: Bus Off If CAN_CTRL1.LOM is asserted after a delay that depends on the CAN bit timing the FLTCONF field will.." "Error Active,Error Passive,?,?" newline rbitfld.long 0x10 3. "RX,FlexCAN in Reception - Indicates if the FlexCAN is receiving a message: - 1: FlexCAN is receiving a message. - 0: FlexCAN is not receiving a message." "FlexCAN is not receiving a message,FlexCAN is receiving a message" bitfld.long 0x10 2. "BOFFINT,Bus Off Interrupt: - 1: FlexCAN module entered Bus Off state. - 0: No such occurrence. BOFFINT is set when the FlexCAN enters the Bus Off state. If the corresponding mask bit (CAN-CTRL1.BOFFMSK) is set an interrupt is generated to the CPU." "No such occurrence,FlexCAN module entered Bus Off state" newline bitfld.long 0x10 1. "ERRINT,Error Interrupt: - 1: Indicates setting of any error bit in CAN-ESR1. - 0: No such occurrence. ERRINT indicates that at least one of the error bits (BIT1ERR BITOERR ACKERR CRCERR FRMERR or STFERR) is set. If the corresponding mask bit.." "No such occurrence,Indicates setting of any error bit in CAN-ESR1" bitfld.long 0x10 0. "WAKINT,Wake Up Interrupt - Applies when the FlexCAN is in low-power mode under Self Wake Up mechanism either Doze mode or Stop mode: - 1: Indicates a recessive-to-dominant transition was received on the CAN bus. - 0: No such occurrence. When a.." "No such occurrence,Indicates a recessive-to-dominant transition was.." line.long 0x14 "CAN_IMASK2,Interrupt Masks 2 Register. The CAN_IMASK2 register allows any number of the 32 message buffer interrupts to be enabled or disabled for MB63 to MB32. CAN_IMASK2 contains one interrupt mask bit per buffer. enabling the CPU to determine which.." hexmask.long 0x14 0.--31. 1. "BUF63TO32M,Buffer MB i Mask Each bit enables or disables the corresponding FlexCAN Message Buffer Interrupt for MB63 to MB32: - 1: The corresponding buffer interrupt is enabled. - 0: The corresponding buffer interrupt is disabled." line.long 0x18 "CAN_IMASK1,Interrupt Masks 1 Register. The CAN_IMASK1 register allows any number of the 32 message buffer interrupts to be enabled or disabled for MB31 to MB. CAN_IMASK1 contains one interrupt mask bit per buffer. enabling the CPU to determine which.." hexmask.long 0x18 0.--31. 1. "BUF31TO0M,Buffer MB i Mask Each bit enables or disables the corresponding FlexCAN Message Buffer Interrupt for MB31 to MBO: - 1: The corresponding buffer interrupt is enabled. - 0: The corresponding buffer interrupt is disabled." line.long 0x1C "CAN_IFLAG2,Interrupt Flags 2 Register. The CAN_IFLAG2 register defines the flags for the 32 message buffer interrupts for MB63 to MB32. CAN_IFLAG2 contains one interrupt flag bit per buffer. Each successful transmission or reception sets the respective.." hexmask.long 0x1C 0.--31. 1. "BUF63TO321,Buffer MB i Interrupt Each bit flags the corresponding FlexCAN Message Buffer Interrupt for MB63 to MB32: - 1: The corresponding buffer has successfully completed transmission or reception. - 0: The corresponding buffer has no occurrence of.." line.long 0x20 "CAN_IFLAG1,Interrupt Flags 1 Register. The CAN_IFLAG1 register defines the flags for the 32 message buffer interrupts for MB31 to MB0. CAN_IFLAG1 contains one interrupt flag bit per buffer. Each successful transmission or reception sets the corresponding.." hexmask.long.tbyte 0x20 8.--31. 1. "BUF31T081,Buffer MBi Interrupt Each bit flags the corresponding FlexCAN Message Buffer Interrupt for MB31 to MB8: - 1: The corresponding buffer has successfully completed transmission or reception. - 0: The corresponding buffer has no occurrence of.." bitfld.long 0x20 7. "BUF71,Buffer MB 7 Interrupt or Legacy Rx FIFO Overflow: - 1: MB7 completed transmission/reception when CAN_MCR.RFEN=O or Legacy Rx FIFO overflow when CAN_MCR.RFEN=1. - 0: No occurrence of MB7 completing transmission/reception when CAN_MCR.RFEN=O or of.." "No occurrence of MB7 completing..,MB7 completed transmission/reception when CAN_MCR" newline bitfld.long 0x20 6. "BUF61,Buffer MB6 Interrupt or Legacy Rx FIFO Warning: - 1: MB6 completed transmission/reception when CAN_MCR.RFEN=0 or Legacy Rx FIFO almost full when CAN_MCR.RFEN=1. - 0: No occurrence of MB6 completing transmission/reception when CAN_MCR.RFEN=O or of.." "No occurrence of MB6 completing..,MB6 completed transmission/reception when CAN_MCR" bitfld.long 0x20 5. "BUF51,Buffer MB5 Interrupt or Frames Available in Legacy Rx FIFO: - 1: MB5 completed transmission/reception when CAN_MCR.RFEN=0 or frame(s) available in the Legacy Rx FIFO when CAN_MCR.RFEN=1. BUF51 generates a OMA request when both CAN_MCR.RFEN and.." "No occurrence of MB5 completing..,MB5 completed transmission/reception when CAN_MCR" newline hexmask.long.byte 0x20 1.--4. 1. "BUF4T011,Buffer MB Interrupt or Reserved: - 1: The corresponding buffer has successfully completed transmission or reception when CAN_MCR.RFEN=O. - 0: The corresponding buffer has no occurrence of successfully completed transmission or reception when.." bitfld.long 0x20 0. "BUF01,Buffer MBO Interrupt or Clear Legacy Rx FIFO bit When CAN_MCR.RFEN is cleared (Legacy Rx FIFO disabled) BUF0I flags the interrupt for MB0: - 1: MB0 has successfully completed transmission or reception when CAN_MCR.RFEN=O. - 0: MB0 has no.." "MB0 has no occurrence of successfully completed..,MB0 has successfully completed transmission or.." line.long 0x24 "CAN_CTRL2,Control 2 Register. The CAN_CTRL2 register complements CAN_CTRL1. providing control bits for memory write access in Freeze mode. for extending Legacy Rx FIFO filter quantity. and for adjusting the operation of internal FlexCAN processes like.." bitfld.long 0x24 31. "ERRMSK_FAST,Error Interrupt Mask for errors detected in the Data Phase of fast CAN FD frames ERRMSK_FAST provides a mask for the ERRINT_FAST Interrupt in CAN_ESR1: - 1: ERRINT_FAST error interrupt enabled. - 0: ERRINT_FAST error interrupt disabled." "ERRINT_FAST error interrupt disabled,ERRINT_FAST error interrupt enabled" bitfld.long 0x24 30. "BOFFDONEMSK,Bus Off Done Interrupt Mask - Provides a mask for the Bus Off done interrupt in CAN_ESR1: - 1: Bus Off done interrupt enabled. - 0: Bus Off done interrupt disabled." "Bus Off done interrupt disabled,Bus Off done interrupt enabled" newline bitfld.long 0x24 29. "ECRWRE,Error-Correction Configuration Register Write Enable - Enables the CAN-MECR register to be updated: - 1: Enable update. - 0: Disable update." "Disable update,Enable update" bitfld.long 0x24 28. "WRMFRZ,Write-Access To Memory In Freeze Mode - Enable unrestricted write access to FlexCAN memory in Freeze mode: - 0: Maintain the write access restrictions. - 1: Enable unrestricted write access to FlexCAN memory. WRMFRZ can only be written in Freeze.." "Maintain the write access restrictions,Enable unrestricted write access to FlexCAN memory" newline hexmask.long.byte 0x24 24.--27. 1. "RFFN,Number of Legacy Rx FIFO Filters - Defines the number of Legacy Rx FIFO filters. The maximum selectable number of filters is a function of configuration parameter NUMBER_OF_MB. RFFN must not be programmed with values that cause the number of message.." hexmask.long.byte 0x24 19.--23. 1. "TASD,Tx Arbitration Start Delay - Indicates how many CAN bits the Tx arbitration process start point can be delayed from the first bit of CRC field on CAN bus." newline bitfld.long 0x24 18. "MRP,Mailboxes Reception Priority: - 1: Matching starts from mailboxes and continues on Legacy Rx FIFO. - 0: Matching starts from Legacy Rx FIFO and continues on mailboxes. If MRP is set the matching process starts from the mailboxes and if no match.." "Matching starts from Legacy Rx FIFO and..,Matching starts from mailboxes and continues on.." bitfld.long 0x24 17. "RRS,Remote Request Storing: - 1: Remote Request Frame is stored. - 0: Remote Response Frame is generated. If RRS is asserted a Remote Request Frame is submitted to a matching process and stored in the corresponding message buffer in the same fashion as.." "Remote Response Frame is generated,Remote Request Frame is stored" newline bitfld.long 0x24 16. "EACEN,Entire Frame Arbitration Field Comparison Enable for Rx Mailboxes: - 1: Enables the comparison of both the IDE and RTR bits of an Rx mailbox filter with the corresponding bits of the incoming frame. Mask bits do apply. - 0: Rx mailbox filter's IDE.." "Rx mailbox filter's IDE bit is always compared..,Enables the comparison of both the IDE and RTR.." bitfld.long 0x24 15. "TIMER_SRC,Timer Source - Selects the time tick source used for incrementing the free-running timer counter: - 1: The free-running timer is clocked by an external time tick. The period can be either adjusted to be equal to the baud rate on the CAN bus or.." "The free-running timer is clocked by the CAN bit..,The free-running timer is clocked by an external.." newline bitfld.long 0x24 14. "PREXCEN,Protocol Exception Enable - Enables the protocol exception feature: - 1: Protocol exception is enabled. - 0: Protocol exception is disabled. PREXCEN is writable only in Freeze mode. PREXCEN is not available (reserved write 0) if parameter FD EN.." "Protocol exception is disabled,Protocol exception is enabled" newline bitfld.long 0x24 12. "ISOCANFDEN,ISO CAN FD Enable - 1: Enable ISO CAN FD compliant operation. - 0: Disable ISO CAN FD specific features (non-ISO CAN FD operation). ISOCANFDEN enables ISO CAN FD compliant operation by enabling the following features which are part of the ISO.." "Disable ISO CAN FD specific features,Enable ISO CAN FD compliant operation" bitfld.long 0x24 11. "EDFLTDIS,Edge Filter Disable - Disables the edge filter used during the bus integration state: - 1: Edge filter is disabled. - 0: Edge filter is enabled. When the edge filter is enabled two consecutive nominal time quanta with dominant bus state are.." "Edge filter is enabled,Edge filter is disabled" newline rgroup.long 0x38++0x3 line.long 0x0 "CAN_ESR2,Error and Status 2 Register. The CAN_ESR2 register reports some general status information." hexmask.long.byte 0x0 16.--22. 1. "LPTM,Lowest Priority Tx Mailbox If CAN_ESR2.VPS is asserted LPTM indicates the lowest number inactive mailbox. If there is no inactive mailbox then the mailbox indicated depends on the CAN_CTRL1.LBUF bit value: - If CAN_CTRL1.LBUF is negated the.." newline bitfld.long 0x0 14. "VPS,Valid Priority Status - Indicates whether CAN_ESR2.IMB and CAN_ESR2.LPTM contents are currently valid or not: - 1: Contents of IMB and LPTM are valid. - 0: Contents of IMB and LPTM are invalid. VPS is asserted upon every complete Tx arbitration.." "Contents of IMB and LPTM are invalid,Contents of IMB and LPTM are valid" newline bitfld.long 0x0 13. "IMB,Inactive Mailbox If CAN_ESR2.VPS is asserted IMB indicates whether there is any inactive mailbox (CODE field is either 0b1000 or 0b0000): - 1: If CAN_ESR2.VPS is asserted there is at least one inactive mailbox. CAN_ESR2.LPTM content is the number.." "If CAN_ESR2,If CAN_ESR2" rgroup.long 0x44++0x3 line.long 0x0 "CAN_CRCR,The CAN_CRCR register provides information about the CRC of transmitted messages for non-FD messages. CAN_CRCR only reports the 15 low order bits of CRC calculations for messages in CAN FD format that require either 17 or 21 bits. For CAN FD.." hexmask.long.byte 0x0 16.--22. 1. "MBCRC,CRC Mailbox - Indicates the number of the mailbox corresponding to the value in the CAN CRCR.TXCRC field." newline hexmask.long.word 0x0 0.--14. 1. "TXCRC,Transmitted CRC Value - Indicates the CRC value of the last transmitted message for non-FD frames. For CAN FD frames the CRC value is reported in CAN_FDCRC." group.long 0x48++0x3 line.long 0x0 "CAN_RXFGMASK,Rx FIFO Global Mask Register. The CAN_RXFGMASK register is located in RAM. If the Legacy Rx FIFO is enabled. CAN_RXFGMASK is used to mask the Legacy Rx FIFO ID Filter Table elements that do not have a corresponding CAN_RXIMR according to.." hexmask.long 0x0 0.--31. 1. "FGM,Legacy Rx FIFO Global Mask Bits These bits mask the Legacy Rx FIFO ID Filter Table elements bits in a perfect alignment: - 1: The corresponding bit in the filter is checked. - 0: The corresponding bit in the filter is 'don't care'." rgroup.long 0x4C++0x3 line.long 0x0 "CAN_RXFIR,Rx FIFO Information Register. The CAN_RXFIR register provides information on the Legacy Rx FIFO. CAN_RXFIR is the port through which the CPU accesses the output of the Legacy RXFIR FIFO located in RAM. The Legacy RXFIR FIFO is written by the.." hexmask.long.word 0x0 0.--8. 1. "IDHIT,Identifier Acceptance Filter Hit Indicator - Indicates which Identifier Acceptance Filter was hit by the received message that is in the output of the Legacy Rx FIFO. If multiple filters match the incoming message ID the first matching IDAF found.." group.long 0x50++0x3 line.long 0x0 "CAN_CBT,CAN Bit Timing Register. The CAN_CBT register is an alternative way to store the CAN bit timing variables described in the CAN_CTRL1 register. EPRESDIV. EPROPSEG. EPSEG1. EPSEG2. and ERJW are extended versions of CAN_CTRL1 register PRESDIV." bitfld.long 0x0 31. "BTF,Bit Timing Format Enable - Enables the use of extended CAN bit timing fields EPRESDIV EPROPSEG EPSEG1 EPSEG2 and ERJW replacing the CAN bit timing variables defined in CAN_CTRL1: - 1: Extended bit time definitions enabled. - 0: Extended bit time.." "Extended bit time definitions disabled,Extended bit time definitions enabled" hexmask.long.word 0x0 21.--30. 1. "EPRESDIV,Extended Prescaler Division Factor When CAN_CBT.BTF is asserted EPRESDIV defines the ratio between the PE clock frequency and the Serial Clock (Sclock) frequency. EPRESDIV extends the CAN_CTRL1.PRESDIV value range. Sclock frequency = PE clock.." newline hexmask.long.byte 0x0 16.--20. 1. "ERJW,Extended Resync Jump Width When CAN_CBT.BTF is asserted ERJW defines the maximum number of time quanta that a bit time can be changed by one re- synchronization. ERJW extends the CAN_CTRL1.RJW value range. Resync Jump Width = ERJW + 1 One time.." hexmask.long.byte 0x0 10.--15. 1. "EPROPSEG,Extended Propagation Segment When CAN_CBT.BTF is asserted EPROPSEG defines the length of the Propagation Segment in the bit time. EPROPSEG extends the CAN_CTRL 1.PROPSEG value range. Propagation Segment Time = (EPROPSEG + 1) x Time-Quanta.." newline hexmask.long.byte 0x0 5.--9. 1. "EPSEG1,Extended Phase Segment 1 When CAN_CBT.BTF is asserted EPSEG1 defines the length of Phase Segment 1 in the bit time. EPSEG1 extends the CAN_CTRL 1.PSEG1 value range. Phase Buffer Segment 1 = (EPSEG1 + 1) x Time-Quanta Time-Quantum = one Sclock.." hexmask.long.byte 0x0 0.--4. 1. "EPSEG2,Extended Phase Segment 2 When CAN_CBT.BTF is asserted EPSEG2 defines the length of Phase Segment 2 in the bit time. EPSEG2 extends the CAN_CTRL1.PSEG2 value range. Phase Buffer Segment 1 = (EPSEG2 + 1) x Time-Quanta Time-Quantum = one Sclock.." group.long 0x68++0xF line.long 0x0 "CAN_IMASK4,Interrupt Masks 4 Register. The CAN_IMASK4 register allows any number of the 32 message buffer interrupts to be enabled or disabled for MB127 to MB96. CAN_IMASK4 contains one interrupt mask bit per buffer. enabling the CPU to determine which.." hexmask.long 0x0 0.--31. 1. "BUF127T096M,Buffer MB i Mask Each bit enables or disables the corresponding FlexCAN Message Buffer Interrupt for MB127 to MB96: - 1: The corresponding buffer interrupt is enabled. - 0: The corresponding buffer interrupt is disabled. When CAN FD is.." line.long 0x4 "CAN_IMASK3,Interrupt Masks 3 Register. The CAN_IMASK3 register allows any number of the 32 message buffer interrupts to be enabled or disabled for MB95 to MB64. CAN_IMASK3 contains one interrupt mask bit per buffer. enabling the CPU to determine which.." hexmask.long 0x4 0.--31. 1. "BUF95T064M,Buffer MB i Mask Each bit enables or disables the corresponding FlexCAN Message Buffer Interrupt for MB95 to MB64: - 1: The corresponding buffer interrupt is enabled. - 0: The corresponding buffer interrupt is disabled. When CAN FD is enabled.." line.long 0x8 "CAN_IFLAG4,Interrupt Flags 4 Register. The CAN_IFLAG4 register defines the flags for the 32 message buffer interrupts for MB127 to MB96. CAN_IFLAG4 contains one interrupt flag bit per buffer. Each successful transmission or reception sets the respective.." hexmask.long 0x8 0.--31. 1. "BUF127T096,Buffer MB Interrupt Each bit flags the corresponding FlexCAN Message Buffer Interrupt for MB127 to MB96: - 1: The corresponding buffer has successfully completed transmission or reception. - 0: The corresponding buffer has no occurrence of.." line.long 0xC "CAN_IFLAG3,Interrupt Flags 3 Register. The CAN_IFLAG3 register defines the flags for the 32 Message Buffer interrupts for MB95 to MB64. CAN_IFLAG3 contains one interrupt flag bit per buffer. Each successful transmission or reception sets the respective.." hexmask.long 0xC 0.--31. 1. "BUF95T064,Buffer MB i Interrupt Each bit flags the corresponding FlexCAN Message Buffer Interrupt for MB95 to MB64: - 1: The corresponding buffer has successfully completed transmission or reception. - 0: The corresponding buffer has no occurrence of.." group.long 0x880++0x27 line.long 0x0 "CAN_RXIMR0,Rx Individual Mask Register 0. The Rx Individual Mask Registers are used to store the acceptance masks for ID filtering in Rx MBs and the Legacy Rx FIFO. When the Legacy Rx FIFO is disabled (CAN_MCR.RFEN is negated). an individual mask is.." hexmask.long 0x0 0.--31. 1. "MI,Individual Mask Bits: 1'b1: The corresponding bit in the filter is checked. 1'b0: The corresponding bit in the filter is 'don't care'." line.long 0x4 "CAN_RXIMR1,Rx Individual Mask Register 1. The Rx Individual Mask Registers are used to store the acceptance masks for ID filtering in Rx MBs and the Legacy Rx FIFO. When the Legacy Rx FIFO is disabled (CAN_MCR.RFEN is negated). an individual mask is.." hexmask.long 0x4 0.--31. 1. "MI,Individual Mask Bits: 1'b1: The corresponding bit in the filter is checked. 1'b0: The corresponding bit in the filter is 'don't care'." line.long 0x8 "CAN_RXIMR2,Rx Individual Mask Register 2. The Rx Individual Mask Registers are used to store the acceptance masks for ID filtering in Rx MBs and the Legacy Rx FIFO. When the Legacy Rx FIFO is disabled (CAN_MCR.RFEN is negated). an individual mask is.." hexmask.long 0x8 0.--31. 1. "MI,Individual Mask Bits: - 1'b1: The corresponding bit in the filter is checked. - 1'b0: The corresponding bit in the filter is 'don't care'." line.long 0xC "CAN_RXIMR3,Rx Individual Mask Register 3. The Rx Individual Mask Registers are used to store the acceptance masks for ID filtering in Rx MBs and the Legacy Rx FIFO. When the Legacy Rx FIFO is disabled (CAN_MCR.RFEN is negated). an individual mask is.." hexmask.long 0xC 0.--31. 1. "MI,Individual Mask Bits: 1'b1: The corresponding bit in the filter is checked. 1'b0: The corresponding bit in the filter is 'don't care'." line.long 0x10 "CAN_RXIMR4,Rx Individual Mask Register 4. The Rx Individual Mask Registers are used to store the acceptance masks for ID filtering in Rx MBs and the Legacy Rx FIFO. When the Legacy Rx FIFO is disabled (CAN_MCR.RFEN is negated). an individual mask is.." hexmask.long 0x10 0.--31. 1. "MI,Individual Mask Bits: 1'b1: The corresponding bit in the filter is checked. 1'b0: The corresponding bit in the filter is 'don't care'." line.long 0x14 "CAN_RXIMR5,Rx Individual Mask Register 5. The Rx Individual Mask Registers are used to store the acceptance masks for ID filtering in Rx MBs and the Legacy Rx FIFO. When the Legacy Rx FIFO is disabled (CAN_MCR.RFEN is negated). an individual mask is.." hexmask.long 0x14 0.--31. 1. "MI,Individual Mask Bits: 1'b1: The corresponding bit in the filter is checked. 1'b0: The corresponding bit in the filter is 'don't care'." line.long 0x18 "CAN_RXIMR6,Rx Individual Mask Register 6. The Rx Individual Mask Registers are used to store the acceptance masks for ID filtering in Rx MBs and the Legacy Rx FIFO. When the Legacy Rx FIFO is disabled (CAN_MCR.RFEN is negated). an individual mask is.." hexmask.long 0x18 0.--31. 1. "MI,Individual Mask Bits: 1'b1: The corresponding bit in the filter is checked. 1'b0: The corresponding bit in the filter is 'don't care'." line.long 0x1C "CAN_RXIMR7,Rx Individual Mask Register 7. The Rx Individual Mask Registers are used to store the acceptance masks for ID filtering in Rx MBs and the Legacy Rx FIFO. When the Legacy Rx FIFO is disabled (CAN_MCR.RFEN is negated). an individual mask is.." hexmask.long 0x1C 0.--31. 1. "MI,Individual Mask Bits: 1'b1: The corresponding bit in the filter is checked. 1'b0: The corresponding bit in the filter is 'don't care'." line.long 0x20 "CAN_RXIMR8,Rx Individual Mask Register 8. The Rx Individual Mask Registers are used to store the acceptance masks for ID filtering in Rx MBs and the Legacy Rx FIFO. When the Legacy Rx FIFO is disabled (CAN_MCR.RFEN is negated). an individual mask is.." hexmask.long 0x20 0.--31. 1. "MI,Individual Mask Bits: 1'b1: The corresponding bit in the filter is checked. 1'b0: The corresponding bit in the filter is 'don't care'." line.long 0x24 "CAN_RXIMR9,Rx Individual Mask Register 9.The Rx Individual Mask Registers are used to store the acceptance masks for ID filtering in Rx MBs and the Legacy Rx FIFO. When the Legacy Rx FIFO is disabled (CAN_MCR.RFEN is negated). an individual mask is.." hexmask.long 0x24 0.--31. 1. "MI,Individual Mask Bits: 1'b1: The corresponding bit in the filter is checked. 1'b0: The corresponding bit in the filter is 'don't care'." repeat 16. (list 0xA 0xB 0xC 0xD 0xE 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1A 0x1B 0x1C )(list 0x0 0x4 0x8 0xC 0x10 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C 0x40 0x44 0x48 ) group.long ($2+0x8A8)++0x3 line.long 0x0 "CAN_RXIMR$1,Rx Individual Mask Register 10. The Rx Individual Mask Registers are used to store the acceptance masks for ID filtering in Rx MBs and the Legacy Rx FIFO. When the Legacy Rx FIFO is disabled (CAN_MCR.RFEN is negated). an individual mask is.." hexmask.long 0x0 0.--31. 1. "MI,Individual Mask Bits: 1'b1: The corresponding bit in the filter is checked. 1'b0: The corresponding bit in the filter is 'don't care'." repeat.end repeat 9. (list 0x1D 0x1E 0x24 0x25 0x26 0x27 0x28 0x29 0x3E )(list 0x4C 0x50 0x68 0x6C 0x70 0x74 0x78 0x7C 0xD0 ) group.long ($2+0x8A8)++0x3 line.long 0x0 "CAN_RXIMR$1,Rx Individual Mask Register 10. The Rx Individual Mask Registers are used to store the acceptance masks for ID filtering in Rx MBs and the Legacy Rx FIFO. When the Legacy Rx FIFO is disabled (CAN_MCR.RFEN is negated). an individual mask is.." hexmask.long 0x0 0.--31. 1. "MI,Individual Mask Bits: 1'b1: The corresponding bit in the filter is checked. 1'b0: The corresponding bit in the filter is 'don't care'." repeat.end group.long 0x8BC++0xB line.long 0x0 "CAN_RXIMR15,Rx Individual Mask Register 15.The Rx Individual Mask Registers are used to store the acceptance masks for ID filtering in Rx MBs and the Legacy Rx FIFO. When the Legacy Rx FIFO is disabled (CAN_MCR.RFEN is negated). an individual mask is.." hexmask.long 0x0 0.--31. 1. "MI,Individual Mask Bits: - 1'b1: The corresponding bit in the filter is checked. - 1'b0: The corresponding bit in the filter is 'don't care'." line.long 0x4 "CAN_RXIMR16,Rx Individual Mask Register 16.The Rx Individual Mask Registers are used to store the acceptance masks for ID filtering in Rx MBs and the Legacy Rx FIFO. When the Legacy Rx FIFO is disabled (CAN_MCR.RFEN is negated). an individual mask is.." hexmask.long 0x4 0.--31. 1. "MI,Individual Mask Bits: - 1'b1: The corresponding bit in the filter is checked. - 1'b0: The corresponding bit in the filter is 'don't care'." line.long 0x8 "CAN_RXIMR17,Rx Individual Mask Register 17.The Rx Individual Mask Registers are used to store the acceptance masks for ID filtering in Rx MBs and the Legacy Rx FIFO. When the Legacy Rx FIFO is disabled (CAN_MCR.RFEN is negated). an individual mask is.." hexmask.long 0x8 0.--31. 1. "MI,Individual Mask Bits: - 1'b1: The corresponding bit in the filter is checked. - 1'b0: The corresponding bit in the filter is 'don't care'." group.long 0x8FC++0x13 line.long 0x0 "CAN_RXIMR31,Rx Individual Mask Register 31.The Rx Individual Mask Registers are used to store the acceptance masks for ID filtering in Rx MBs and the Legacy Rx FIFO. When the Legacy Rx FIFO is disabled (CAN_MCR.RFEN is negated). an individual mask is.." hexmask.long 0x0 0.--31. 1. "MI,Individual Mask Bits: - 1'b1: The corresponding bit in the filter is checked. - 1'b0: The corresponding bit in the filter is 'don't care'." line.long 0x4 "CAN_RXIMR32,Rx Individual Mask Register 32.The Rx Individual Mask Registers are used to store the acceptance masks for ID filtering in Rx MBs and the Legacy Rx FIFO. When the Legacy Rx FIFO is disabled (CAN_MCR.RFEN is negated). an individual mask is.." hexmask.long 0x4 0.--31. 1. "MI,Individual Mask Bits: - 1'b1: The corresponding bit in the filter is checked. - 1'b0: The corresponding bit in the filter is 'don't care'." line.long 0x8 "CAN_RXIMR33,Rx Individual Mask Register 33.The Rx Individual Mask Registers are used to store the acceptance masks for ID filtering in Rx MBs and the Legacy Rx FIFO. When the Legacy Rx FIFO is disabled (CAN_MCR.RFEN is negated). an individual mask is.." hexmask.long 0x8 0.--31. 1. "MI,Individual Mask Bits: - 1'b1: The corresponding bit in the filter is checked. - 1'b0: The corresponding bit in the filter is 'don't care'." line.long 0xC "CAN_RXIMR34,Rx Individual Mask Register 34.The Rx Individual Mask Registers are used to store the acceptance masks for ID filtering in Rx MBs and the Legacy Rx FIFO. When the Legacy Rx FIFO is disabled (CAN_MCR.RFEN is negated). an individual mask is.." hexmask.long 0xC 0.--31. 1. "MI,Individual Mask Bits: - 1'b1: The corresponding bit in the filter is checked. - 1'b0: The corresponding bit in the filter is 'don't care'." line.long 0x10 "CAN_RXIMR35,Rx Individual Mask Register 35.The Rx Individual Mask Registers are used to store the acceptance masks for ID filtering in Rx MBs and the Legacy Rx FIFO. When the Legacy Rx FIFO is disabled (CAN_MCR.RFEN is negated). an individual mask is.." hexmask.long 0x10 0.--31. 1. "MI,Individual Mask Bits: - 1'b1: The corresponding bit in the filter is checked. - 1'b0: The corresponding bit in the filter is 'don't care'." group.long 0x928++0x4F line.long 0x0 "CAN_RXIMR42,Rx Individual Mask Register 42.The Rx Individual Mask Registers are used to store the acceptance masks for ID filtering in Rx MBs and the Legacy Rx FIFO. When the Legacy Rx FIFO is disabled (CAN_MCR.RFEN is negated). an individual mask is.." hexmask.long 0x0 0.--31. 1. "MI,Individual Mask Bits: - 1: The corresponding bit in the filter is checked. - 0: The corresponding bit in the filter is 'don't care'." line.long 0x4 "CAN_RXIMR43,Rx Individual Mask Register 43.The Rx Individual Mask Registers are used to store the acceptance masks for ID filtering in Rx MBs and the Legacy Rx FIFO. When the Legacy Rx FIFO is disabled (CAN_MCR.RFEN is negated). an individual mask is.." hexmask.long 0x4 0.--31. 1. "MI,Individual Mask Bits: - 1: The corresponding bit in the filter is checked. - 0: The corresponding bit in the filter is 'don't care'." line.long 0x8 "CAN_RXIMR44,Rx Individual Mask Register 44.The Rx Individual Mask Registers are used to store the acceptance masks for ID filtering in Rx MBs and the Legacy Rx FIFO. When the Legacy Rx FIFO is disabled (CAN_MCR.RFEN is negated). an individual mask is.." hexmask.long 0x8 0.--31. 1. "MI,Individual Mask Bits: - 1: The corresponding bit in the filter is checked. - 0: The corresponding bit in the filter is 'don't care'." line.long 0xC "CAN_RXIMR45,Rx Individual Mask Register 45.The Rx Individual Mask Registers are used to store the acceptance masks for ID filtering in Rx MBs and the Legacy Rx FIFO. When the Legacy Rx FIFO is disabled (CAN_MCR.RFEN is negated). an individual mask is.." hexmask.long 0xC 0.--31. 1. "MI,Individual Mask Bits: - 1: The corresponding bit in the filter is checked. - 0: The corresponding bit in the filter is 'don't care'." line.long 0x10 "CAN_RXIMR46,Rx Individual Mask Register 46.The Rx Individual Mask Registers are used to store the acceptance masks for ID filtering in Rx MBs and the Legacy Rx FIFO. When the Legacy Rx FIFO is disabled (CAN_MCR.RFEN is negated). an individual mask is.." hexmask.long 0x10 0.--31. 1. "MI,Individual Mask Bits: - 1: The corresponding bit in the filter is checked. - 0: The corresponding bit in the filter is 'don't care'." line.long 0x14 "CAN_RXIMR47,Rx Individual Mask Register 47.The Rx Individual Mask Registers are used to store the acceptance masks for ID filtering in Rx MBs and the Legacy Rx FIFO. When the Legacy Rx FIFO is disabled (CAN_MCR.RFEN is negated). an individual mask is.." hexmask.long 0x14 0.--31. 1. "MI,Individual Mask Bits: - 1: The corresponding bit in the filter is checked. - 0: The corresponding bit in the filter is 'don't care'." line.long 0x18 "CAN_RXIMR48,Rx Individual Mask Register 48.The Rx Individual Mask Registers are used to store the acceptance masks for ID filtering in Rx MBs and the Legacy Rx FIFO. When the Legacy Rx FIFO is disabled (CAN_MCR.RFEN is negated). an individual mask is.." hexmask.long 0x18 0.--31. 1. "MI,Individual Mask Bits: - 1: The corresponding bit in the filter is checked. - 0: The corresponding bit in the filter is 'don't care'." line.long 0x1C "CAN_RXIMR49,Rx Individual Mask Register 49.The Rx Individual Mask Registers are used to store the acceptance masks for ID filtering in Rx MBs and the Legacy Rx FIFO. When the Legacy Rx FIFO is disabled (CAN_MCR.RFEN is negated). an individual mask is.." hexmask.long 0x1C 0.--31. 1. "MI,Individual Mask Bits: - 1: The corresponding bit in the filter is checked. - 0: The corresponding bit in the filter is 'don't care'." line.long 0x20 "CAN_RXIMR50,Rx Individual Mask Register 50.The Rx Individual Mask Registers are used to store the acceptance masks for ID filtering in Rx MBs and the Legacy Rx FIFO. When the Legacy Rx FIFO is disabled (CAN_MCR.RFEN is negated). an individual mask is.." hexmask.long 0x20 0.--31. 1. "MI,Individual Mask Bits: - 1: The corresponding bit in the filter is checked. - 0: The corresponding bit in the filter is 'don't care'." line.long 0x24 "CAN_RXIMR51,Rx Individual Mask Register 51.The Rx Individual Mask Registers are used to store the acceptance masks for ID filtering in Rx MBs and the Legacy Rx FIFO. When the Legacy Rx FIFO is disabled (CAN_MCR.RFEN is negated). an individual mask is.." hexmask.long 0x24 0.--31. 1. "MI,Individual Mask Bits: - 1: The corresponding bit in the filter is checked. - 0: The corresponding bit in the filter is 'don't care'." line.long 0x28 "CAN_RXIMR52,Rx Individual Mask Register 52.The Rx Individual Mask Registers are used to store the acceptance masks for ID filtering in Rx MBs and the Legacy Rx FIFO. When the Legacy Rx FIFO is disabled (CAN_MCR.RFEN is negated). an individual mask is.." hexmask.long 0x28 0.--31. 1. "MI,Individual Mask Bits: - 1: The corresponding bit in the filter is checked. - 0: The corresponding bit in the filter is 'don't care'." line.long 0x2C "CAN_RXIMR53,Rx Individual Mask Register 53.The Rx Individual Mask Registers are used to store the acceptance masks for ID filtering in Rx MBs and the Legacy Rx FIFO. When the Legacy Rx FIFO is disabled (CAN_MCR.RFEN is negated). an individual mask is.." hexmask.long 0x2C 0.--31. 1. "MI,Individual Mask Bits: - 1: The corresponding bit in the filter is checked. - 0: The corresponding bit in the filter is 'don't care'." line.long 0x30 "CAN_RXIMR54,Rx Individual Mask Register 54.The Rx Individual Mask Registers are used to store the acceptance masks for ID filtering in Rx MBs and the Legacy Rx FIFO. When the Legacy Rx FIFO is disabled (CAN_MCR.RFEN is negated). an individual mask is.." hexmask.long 0x30 0.--31. 1. "MI,Individual Mask Bits: - 1: The corresponding bit in the filter is checked. - 0: The corresponding bit in the filter is 'don't care'." line.long 0x34 "CAN_RXIMR55,Rx Individual Mask Register 55.The Rx Individual Mask Registers are used to store the acceptance masks for ID filtering in Rx MBs and the Legacy Rx FIFO. When the Legacy Rx FIFO is disabled (CAN_MCR.RFEN is negated). an individual mask is.." hexmask.long 0x34 0.--31. 1. "MI,Individual Mask Bits: - 1: The corresponding bit in the filter is checked. - 0: The corresponding bit in the filter is 'don't care'." line.long 0x38 "CAN_RXIMR56,Rx Individual Mask Register 56.The Rx Individual Mask Registers are used to store the acceptance masks for ID filtering in Rx MBs and the Legacy Rx FIFO. When the Legacy Rx FIFO is disabled (CAN_MCR.RFEN is negated). an individual mask is.." hexmask.long 0x38 0.--31. 1. "MI,Individual Mask Bits: - 1: The corresponding bit in the filter is checked. - 0: The corresponding bit in the filter is 'don't care'." line.long 0x3C "CAN_RXIMR57,Rx Individual Mask Register 57.The Rx Individual Mask Registers are used to store the acceptance masks for ID filtering in Rx MBs and the Legacy Rx FIFO. When the Legacy Rx FIFO is disabled (CAN_MCR.RFEN is negated). an individual mask is.." hexmask.long 0x3C 0.--31. 1. "MI,Individual Mask Bits: - 1: The corresponding bit in the filter is checked. - 0: The corresponding bit in the filter is 'don't care'." line.long 0x40 "CAN_RXIMR58,Rx Individual Mask Register 58.The Rx Individual Mask Registers are used to store the acceptance masks for ID filtering in Rx MBs and the Legacy Rx FIFO. When the Legacy Rx FIFO is disabled (CAN_MCR.RFEN is negated). an individual mask is.." hexmask.long 0x40 0.--31. 1. "MI,Individual Mask Bits: - 1: The corresponding bit in the filter is checked. - 0: The corresponding bit in the filter is 'don't care'." line.long 0x44 "CAN_RXIMR59,Rx Individual Mask Register 59.The Rx Individual Mask Registers are used to store the acceptance masks for ID filtering in Rx MBs and the Legacy Rx FIFO. When the Legacy Rx FIFO is disabled (CAN_MCR.RFEN is negated). an individual mask is.." hexmask.long 0x44 0.--31. 1. "MI,Individual Mask Bits: - 1: The corresponding bit in the filter is checked. - 0: The corresponding bit in the filter is 'don't care'." line.long 0x48 "CAN_RXIMR60,Rx Individual Mask Register 60.The Rx Individual Mask Registers are used to store the acceptance masks for ID filtering in Rx MBs and the Legacy Rx FIFO. When the Legacy Rx FIFO is disabled (CAN_MCR.RFEN is negated). an individual mask is.." hexmask.long 0x48 0.--31. 1. "MI,Individual Mask Bits: - 1: The corresponding bit in the filter is checked. - 0: The corresponding bit in the filter is 'don't care'." line.long 0x4C "CAN_RXIMR61,Rx Individual Mask Register 61.The Rx Individual Mask Registers are used to store the acceptance masks for ID filtering in Rx MBs and the Legacy Rx FIFO. When the Legacy Rx FIFO is disabled (CAN_MCR.RFEN is negated). an individual mask is.." hexmask.long 0x4C 0.--31. 1. "MI,Individual Mask Bits: - 1: The corresponding bit in the filter is checked. - 0: The corresponding bit in the filter is 'don't care'." group.long 0x97C++0x3 line.long 0x0 "CAN_RXIMR63,Rx Individual Mask Register 63. The Rx Individual Mask Registers are used to store the acceptance masks for ID filtering in Rx MBs and the Legacy Rx FIFO. When the Legacy Rx FIFO is disabled (CAN_MCR.RFEN is negated). an individual mask is.." hexmask.long 0x0 0.--31. 1. "MI,Individual Mask Bits: - 1: The corresponding bit in the filter is checked. - 0: The corresponding bit in the filter is 'don't care'. Each Individual Mask Bit masks the corresponding bit in both the mailbox filter and Legacy Rx FIFO ID Filter Table.." group.long 0xAE0++0xF line.long 0x0 "CAN_MECR,The CAN_MECR register contains control bits for memory error detection and correction (ECC). NOTE: When CAN_CTRL2.ECRWRE is 0. writes to CAN_MECR are blocked. with the exception of the ECRWRDIS bit. The CAN_MECR register is not available when.." bitfld.long 0x0 31. "ECRWRDIS,Error Configuration Register Write Disable - Disables writes to this register: - 1: Write is disabled. - 0: Write is enabled. ECRWRDIS is automatically set to 1 (disabled) when CTRL2.ECRWRE is asserted." "Write is enabled,Write is disabled" newline bitfld.long 0x0 19. "HANCEI_MSK,Host Access With Non-Correctable Errors Interrupt Mask Enables the interrupt in case of non-correctable errors detected in memory reads issued by the host (CPU): - 1: Interrupt is enabled. - 0: Interrupt is disabled." "Interrupt is disabled,Interrupt is enabled" bitfld.long 0x0 18. "FANCEI_MSK,FlexCAN Access With Non-Correctable Errors Interrupt Mask Enables the interrupt in case of non-correctable errors detected in memory reads issued by the FlexCAN internal processes: - 1: Interrupt is enabled. - 0: Interrupt is disabled." "Interrupt is disabled,Interrupt is enabled" newline bitfld.long 0x0 16. "CEI_MSK,Correctable Errors Interrupt Mask Enables the interrupt in case of correctable errors detected in memory reads issued by the host or FlexCAN internal processes: - 1: Interrupt is enabled. - 0: Interrupt is disabled." "Interrupt is disabled,Interrupt is enabled" newline bitfld.long 0x0 15. "HAERRIE,Host Access Error Injection Enable Enables the injection of errors only in memory reads issued by the host (CPU): - 1: Injection is enabled. - 0: Injection is disabled." "Injection is disabled,Injection is enabled" bitfld.long 0x0 14. "FAERRIE,FlexCAN Access Error Injection Enable Enables the injection of errors only in memory reads issued by the FlexCAN internal processes: - 1: Injection is enabled. - 0: Injection is disabled." "Injection is disabled,Injection is enabled" newline bitfld.long 0x0 13. "EXTERRIE,Extended Error Injection Enable Memory accesses performed by internal FlexCAN processes are 64-bit accesses. EXTERRIE extends the error injection on 32-bit memory accesses to the complementary 32-bit word using the same 32-bit error injection.." "Error injection is applied only to the 32-bit word,Error injection is applied to the 64-bit word" newline bitfld.long 0x0 9. "RERDIS,Error Report Disable - Disables the update of the error report registers: - 1: Disable updates of the error report registers. The update of error-related flags and the generation of bus transfer errors are still active. - 0: Enable updates of the.." "Enable updates of the error report registers,Disable updates of the error report registers" bitfld.long 0x0 8. "ECCDIS,Error Correction Disable - Disables the memory detection and correction mechanism: - 1: Disable memory error correction. - 0: Enable memory error correction. In addition to disabling the error report mechanism ECCDIS = 1 also stops the update of.." "Enable memory error correction,Disable memory error correction" newline bitfld.long 0x0 7. "NCEFAFRZ,Non-Correctable Errors in FlexCAN Access Put Device In Freeze Mode Determines the response when a non-correctable error is detected in a memory read performed by FlexCAN internal processes: - 1: Put FlexCAN in Freeze mode. In this case entering.." "Keep normal operation,Put FlexCAN in Freeze mode" line.long 0x4 "CAN_ERRIAR,The CAN_ERRIAR register holds the address where a memory read error is to be injected. The size and usage of the FlexCAN RAM depends on the FlexCAN hardware configuration. The CAN_ERRIAR register is not available when parameter ECC_EN is 0." hexmask.long.word 0x4 2.--13. 1. "INJADDR_H,Error Injection Address High - Defines the twelve most significant bits of the physical RAM address where a memory read error is to be injected" newline rbitfld.long 0x4 0.--1. "INJADDR_L,Error Injection Address Low - Read-only field that defines the two least significant bits of the physical RAM address where a memory read error is to be injected. INJADDR - L[1:0] are always zero to ensure that the address is on a 32-bit.." "0,1,2,3" line.long 0x8 "CAN_ERRIDPR,The CAN_ERRIDPR register holds the error pattern to be injected in the data word read from memory. The CAN_ERRIDPR register is not available when parameter ECC_EN is 0." hexmask.long 0x8 0.--31. 1. "DFLIP,Data Flip Pattern Bits set to 1 in the flip pattern cause the corresponding data bit in the word read from memory to invert." line.long 0xC "CAN_ERRIPPR,The CAN_ERRIPPR register holds the error pattern to be injected in parity bits read from memory along with data word. Bits set to 1 in the flip pattern cause the corresponding parity bit in the word read from memory to invert. The CAN_ERRIPPR.." hexmask.long.byte 0xC 24.--28. 1. "PFLIP3,Parity Flip Pattern For Byte 3 (most significant)" newline hexmask.long.byte 0xC 16.--20. 1. "PFLIP2,Parity Flip Pattern For Byte 2" newline hexmask.long.byte 0xC 8.--12. 1. "PFLIP1,Parity Flip Pattern For Byte 2" newline hexmask.long.byte 0xC 0.--4. 1. "PFLIP0,Parity Flip Pattern For Byte O (least significant)" rgroup.long 0xAF0++0xB line.long 0x0 "CAN_RERRAR,The CAN_RERRAR register reports the address used for an access in which an error (correctable or non-correctable) was detected. and reports the identification of the source of that access. The address is always reported using a 32-bit.." bitfld.long 0x0 24. "NCE,Non-Correctable Error - Indicates that the report is due to a non-correctable error: - 1: Reporting a non-correctable error - 0: Reporting a correctable-error" "Reporting a correctable-error,Reporting a non-correctable error" newline bitfld.long 0x0 16.--18. "SAID,SAID[2] - Identification of the requestor of the memory read request: - 0: Requested by FlexCAN internal processes - 1: Requested by host (CPU) SAID[1] - Details of FlexCAN operation: - 0: Move - 1: Scanning SAID[0] - Operation that requested the.." "Transmission,Reception,?,?,?,?,?,?" newline hexmask.long.word 0x0 0.--13. 1. "ERRADDR,Address Where the Error was Detected" line.long 0x4 "CAN_RERRDR,The CAN_RERRDR register reports the raw data (unmodified by the correction performed by ECC logic) read from memory with error. The value reported does not represent the transient values of the BUSY bit when reading a message buffer. The.." hexmask.long 0x4 0.--31. 1. "RDATA,Raw data word read from memory with error." line.long 0x8 "CAN_RERRSYNR,The CAN_RERRSYNR register holds the syndrome detected in a memory read with error. It also reports the bytes that were read in this 32-bit read transaction." bitfld.long 0x8 31. "BE3,Byte Enabled For Byte 3 (most significant) - 1: The byte was read. - 0: The byte was not read." "The byte was not read,The byte was read" newline hexmask.long.byte 0x8 24.--28. 1. "SYND3,Error Syndrome For Byte 3 (most significant)" bitfld.long 0x8 23. "BE2,Byte Enabled for Byte 2." "0,1" newline hexmask.long.byte 0x8 16.--20. 1. "SYND2,Error Syndrome For Byte 2" newline bitfld.long 0x8 15. "BE1,Byte Enabled for Byte 1." "0,1" newline hexmask.long.byte 0x8 8.--12. 1. "SYND1,Error Syndrome For Byte 1" bitfld.long 0x8 7. "BE0,Byte Enabled for Byte 0 (least significant)." "0,1" newline hexmask.long.byte 0x8 0.--4. 1. "SYND0,Error Syndrome For Byte O (least significant)" group.long 0xAFC++0x2B line.long 0x0 "CAN_ERRSR,The CAN_ERRSR register holds the status bits of the error correction and detection operations. These flags can be cleared by writing 1 to them. Writing O has no effect. The CAN_ERRSR register is not available when parameter ECC_EN is 0." bitfld.long 0x0 19. "HANCEIF,FlexCAN Access With Non-Correctable Error Interrupt Flag: - 1: A non-correctable error was detected in a FlexCAN access. - 0: No non-correctable errors were detected in FlexCAN accesses so far. FANCEIF = 1 indicates that a non-correctable error.." "No non-correctable errors were detected in..,A non-correctable error was detected in a.." newline bitfld.long 0x0 18. "FANCEIF,FlexCAN Access With Non-Correctable Error Interrupt Flag: - 1: A non-correctable error was detected in a FlexCAN access. - 0: No non-correctable errors were detected in FlexCAN accesses so far. FANCEIF = 1 indicates that a non-correctable error.." "No non-correctable errors were detected in..,A non-correctable error was detected in a.." newline bitfld.long 0x0 16. "CEIF,Correctable Error Interrupt Flag: - 1: A correctable error was detected. - 0: No correctable errors were detected so far. CEIF = 1 indicates that a correctable error was detected in a memory read. If CAN_MECR.CEI_MSK is set the interrupt is asserted." "No correctable errors were detected so far,A correctable error was detected" newline bitfld.long 0x0 3. "HANCEIOF,Host Access With Non-Correctable Error Interrupt Overrun Flag: - 1: Overrun on non-correctable errors in host access. - 0: No overrun on non-correctable errors in host access. HANCEIOF = 1 indicates that a non-correctable error was detected in a.." "No overrun on non-correctable errors in host..,Overrun on non-correctable errors in host access" bitfld.long 0x0 2. "FANCEIOF,FlexCAN Access With Non-Correctable Error Interrupt Overrun Flag: - 1: Overrun on non-correctable errors in FlexCAN access. - 0: No overrun on non-correctable errors in FlexCAN access. FANCEIOF = 1 indicates that a non-correctable error was.." "No overrun on non-correctable errors in FlexCAN..,Overrun on non-correctable errors in FlexCAN.." newline bitfld.long 0x0 0. "CEIOF,Correctable Error Interrupt Overrun Flag: - 1: Overrun on correctable errors. - 0: No overrun on correctable errors. CEIOF = 1 indicates that a correctable error was detected in a memory read when CEIF was set. No interrupt is associated with this.." "No overrun on correctable errors,Overrun on correctable errors" line.long 0x4 "CAN_CTRL1_PN,The CAN_CTRL1_PN register contains control bits for Pretended Networking mode filtering selection. Configure CAN_CTRL1_PN with the filter criteria to be used to receive wakeup messages. CAN_CTRL1_PN bits other than WTOF_MSK and WUMF_MSK can.." bitfld.long 0x4 17. "WTOF_MSK,Wake Up by Timeout Flag Mask Bit - Masks the generation of a wakeup event originated by a timeout: - 1: Timeout wakeup event is enabled. - 0: Timeout wakeup event is disabled." "Timeout wakeup event is disabled,Timeout wakeup event is enabled" newline bitfld.long 0x4 16. "WUMF_MSK,Wake Up by Match Flag Mask Bit - Masks the generation of a wakeup event originated by a successful filtered Rx message - 1: Wakeup match event is enabled. - 0: Wakeup match event is disabled." "Wakeup match event is disabled,Wakeup match event is enabled" hexmask.long.byte 0x4 8.--15. 1. "NMATCH,Number of Messages Matching the Same Filtering Criteria NMATCH defines the number of times a given message must match the predefined filtering criteria for ID and/or PL before generating a wakeup event. This quantity can be configured in the 1 to.." newline bitfld.long 0x4 4.--5. "PLFS,Payload Filtering Selection - Selects the level of payload filtering to be applied when FlexCAN is under Pretended Networking mode: - 00: Match upon a payload contents against an exact target value. - 01: Match upon a payload value greater than or.." "Match upon a payload contents against an exact..,Match upon a payload value greater than or equal..,?,?" newline bitfld.long 0x4 2.--3. "IDFS,ID Filtering Selection - Selects the level of ID filtering to be applied when FlexCAN is under Pretended Networking mode: - 00: Match upon a ID contents against an exact target value. - 01: Match upon a ID value greater than or equal to a specified.." "Match upon a ID contents against an exact target..,Match upon a ID value greater than or equal to a..,?,?" bitfld.long 0x4 0.--1. "FCS,Filtering Combination Selection - Selects the filtering criteria to be applied when FlexCAN is under Pretended Networking mode: - 00: Message ID filtering only. - 01: Message ID filtering and payload filtering. - 10: Message ID filtering occurring a.." "Message ID filtering only,Message ID filtering and payload filtering,?,?" line.long 0x8 "CAN_CTRL2_PN,The CAN_CTRL2_PN register contains configuration bits for the timeout value under Pretended Networking mode. CAN_CTRL2_PN can be written in Freeze mode only. The CAN_CTRL2_PN register is not available when parameter PNET_EN is 0." hexmask.long.word 0x8 0.--15. 1. "MATCHTO,Timeout for No Message Matching the Filtering Criteria MATCHTO defines a timeout value that generates a wakeup event if CAN_MCR.PNET _EN is asserted. If the timeout counter reaches the target value when the FlexCAN is under Pretended Networking.." line.long 0xC "CAN_WU_MTC,The CAN_WU_MTC register contains wakeup information related to the matching processes performed while the FlexCAN receives frames under Pretended Networking mode. The CAN_WU_MTC register is not available when parameter PNET_EN is 0." bitfld.long 0xC 17. "WTOF,Wake Up by Timeout Flag Bit - Indicates whether the FlexCAN has detected a timeout event during a time interval defined by CAN CTRL2 PN.MATCHTO: - 1: Wakeup by timeout event detected. - 0: No wakeup by timeout event detected. WTOF generates a wakeup.." "No wakeup by timeout event detected,Wakeup by timeout event detected" newline bitfld.long 0xC 16. "WUMF,Wake Up by Match Flag Bit - Indicates whether the FlexCAN has detected a matching Rx incoming message that passed the filtering criteria specified in CAN_CTRL1_PN: - 1: Wakeup by match event detected. - 0: No wakeup by match event detected. WUMF.." "No wakeup by match event detected,Wakeup by match event detected" hexmask.long.byte 0xC 8.--15. 1. "MCOUNTER,Number of Matches while in Pretended Networking MCOUNTER reports the number of times a given message has matched the predefined filtering criteria for ID and/or PL before a wakeup event. MCOUNTER is reset by the FlexCAN when it enters in.." newline line.long 0x10 "CAN_FLT_ID1,The CAN_FLT_1D1 register contains the FLT_1D1 target value and the IDE and RTR target values used to filter an incoming message ID. FLT_1D1 is used either for equal to. smaller than. greater than comparisons. or as the lower limit value in an.." bitfld.long 0x10 30. "FLT_IDE,ID Extended Filter - Identifies whether the frame format is standard or extended: - 1: Accept extended frame format. - 0: Accept standard frame format. FLT_IDE is used as part of the ID reception filter." "Accept standard frame format,Accept extended frame format" newline bitfld.long 0x10 29. "FLT_RTR,Remote Transmission Request Filter - Identifies whether the frame is remote or not: - 1: Accept remote frame. - 0: Reject remote frame (accept data frame). FLT_RTR is used as part of the ID reception Filter." "Reject remote frame,Accept remote frame" hexmask.long 0x10 0.--28. 1. "FLT_ID1,ID Filter 1 for Pretended Networking Filtering - Defines either the 29 bits of an extended frame format considering all bits or the 11 bits of a standard frame format considering just the 11 leftmost bits." line.long 0x14 "CAN_FLT_DLC,The CAN_FLT_DLC register contains the DLC inside range target values (FLT_DLC_LO and FLT_DLC_HI) used to filter an incoming message. The DLC range is used only for payload filtering. CAN_FLT_DLC can be written in Freeze mode only. NOTE: When.." hexmask.long.byte 0x14 16.--19. 1. "FLT_DLC_LO,Lower Limit for Length of Data Bytes Filter - Specifies the lower limit for the number of data bytes considered valid for payload comparison. FLT_DLC_LO is used as part of payload reception Filter." newline hexmask.long.byte 0x14 0.--3. 1. "FLT_DLC_HI,Upper Limit for Length of Data Bytes Filter - Specifies the upper limit for the number of data bytes considered valid for payload comparison. FLT_DLC_HI is used as part of payload reception filter." line.long 0x18 "CAN_PL1_LO,The CAN_PL1_LO register contains Payload Filter 1 low order bits of the target value used to filter incoming message payload. It is used either for 'equal to'. 'smaller than or equal to'. 'greater than or equal to' comparisons. or as the lower.." hexmask.long.byte 0x18 24.--31. 1. "DATA_BYTE_0,Filter 1 low order bits for Pretended Networking payload fittermg corresponding to data byte 0." hexmask.long.byte 0x18 16.--23. 1. "DATA_BYTE_1,Filter 1 low order bits for Pretended Networking payload fittermg corresponding to data byte 1." newline hexmask.long.byte 0x18 8.--15. 1. "DATA_BYTE_2,Filter 1 low order bits for Pretended Networking payload fittermg corresponding to data byte 2." hexmask.long.byte 0x18 0.--7. 1. "DATA_BYTE_3,Filter 1 low order bits for Pretended Networking payload fittermg corresponding to data byte 3." line.long 0x1C "CAN_PL1_HI,The CAN_PL1_HI register contains Payload Filter 1 high order bits of the target value used to filter incoming message payload. It is used either for 'equal to'. 'smaller than or equal to'. 'greater than or equal to' comparisons. or as the.." hexmask.long.byte 0x1C 24.--31. 1. "DATA_BYTE_4,Filter 1 low order bits for Pretended Networking payload filtermg corresponding to data byte 4." hexmask.long.byte 0x1C 16.--23. 1. "DATA_BYTE_5,Filter 1 low order bits for Pretended Networking payload filtermg corresponding to data byte 5." newline hexmask.long.byte 0x1C 8.--15. 1. "DATA_BYTE_6,Filter 1 low order bits for Pretended Networking payload filtermg corresponding to data byte 6." hexmask.long.byte 0x1C 0.--7. 1. "DATA_BYTE_7,Filter 1 low order bits for Pretended Networking payload filtermg corresponding to data byte 7." line.long 0x20 "CAN_FLT_ID2_IDMASK,The CAN_FLT_ID2_1DMASK register contains the FLT_ID2 target value used only as the upper limit value in ID range detection. Also. when exact ID filtering criteria is selected. CAN_FLT_ID2_1DMASK is used to store the ID mask. The.." bitfld.long 0x20 30. "IDE_MSK,ID Extended Mask Bit - Indicates whether the frame format (standard/extended) is used as part of the ID reception filter - 1: The corresponding bit in the filter is checked. - 0: The corresponding bit in the filter is 'don't care'." "The corresponding bit in the filter is 'don't..,The corresponding bit in the filter is checked" newline bitfld.long 0x20 29. "RTR_MSK,Remote Transmission Request Mask Bit - Indicates whether the frame type (data/remote) is part of the ID reception filter: - 1: The corresponding bit in the filter is checked. - 0: The corresponding bit in the filter is 'don't care'." "The corresponding bit in the filter is 'don't..,The corresponding bit in the filter is checked" hexmask.long 0x20 0.--28. 1. "FLT_ID2_IDMASK,ID Filter 2 for Pretended Networking Filtering / ID Mask Bits for Pretended Networking ID Filtering FLT_ID2_1DMASK is used as FLT_ID2 in range of ID filtering to define the ID filter value in either: - Extended frame format (29 bits).." line.long 0x24 "CAN_PL2_PLMASK_LO,The CAN_PL2_PLMASK_LO register has two functions: - It contains the low order bits for the Payload Filter 2 used only as the upper limit value in a payload range detection. - When exact payload filtering criteria is selected." hexmask.long.byte 0x24 24.--31. 1. "DATA_BYTE_0,Payload Filter 2 low order bits / Payload Mask low order bits for Pretended Networking payload filtering corresponding to data byte 0." hexmask.long.byte 0x24 16.--23. 1. "DATA_BYTE_1,Payload Filter 2 low order bits / Payload Mask low order bits for Pretended Networking payload filtering corresponding to data byte 1." newline hexmask.long.byte 0x24 8.--15. 1. "DATA_BYTE_2,Payload Filter 2 low order bits / Payload Mask low order bits for Pretended Networking payload filtering corresponding to data byte 2." hexmask.long.byte 0x24 0.--7. 1. "DATA_BYTE_3,Payload Filter 2 low order bits / Payload Mask low order bits for Pretended Networking payload filtering corresponding to data byte 3." line.long 0x28 "CAN_PL2_PLMASK_HI,The CAN_PL2_PLMASK_HI register has two functions: - It contains the high order bits for the Payload Filter 2 used only as the upper limit value in a payload range detection. - When exact payload filtering criteria is selected." hexmask.long.byte 0x28 24.--31. 1. "DATA_BYTE_4,Payload Filter 2 high order bits / Payload Mask high order bits for Pretended Networking payload filtering corresponding to data byte 4." hexmask.long.byte 0x28 16.--23. 1. "DATA_BYTE_5,Payload Filter 2 high order bits / Payload Mask high order bits for Pretended Networking payload filtering corresponding to data byte 5." newline hexmask.long.byte 0x28 8.--15. 1. "DATA_BYTE_6,Payload Filter 2 high order bits / Payload Mask high order bits for Pretended Networking payload filtering corresponding to data byte 6." hexmask.long.byte 0x28 0.--7. 1. "DATA_BYTE_7,Payload Filter 2 high order bits / Payload Mask high order bits for Pretended Networking payload filtering corresponding to data byte 7." rgroup.long 0xB40++0x37 line.long 0x0 "CAN_WMB0_CS,Wake Up Message Buffer Register for C/S 0. Each of the four WMBs contains a register to store the Control Status (C/S) information (IDE. RTR. and DLC fields) of an incoming Rx message. NOTE: The C/S registers are located at 0x840 for WMB 0." bitfld.long 0x0 22. "SRR,Substitute Remote Request - Can be received either recessive or dominant." "0,1" newline bitfld.long 0x0 21. "IDE,ID Extended Bit - Identifies whether the frame format is standard or extended: - 1: Frame format is extended. - 0: Frame format is standard." "Frame format is standard,Frame format is extended" bitfld.long 0x0 20. "RTR,Remote Transmission Request Bit - Identifies whether the frame is remote or not: - 1: Frame is a remote frame. - 0: Frame is data frame (not remote)." "Frame is data frame,Frame is a remote frame" newline hexmask.long.byte 0x0 16.--19. 1. "DLC,Length of Data in Bytes - Length (in bytes) of the Rx data received when FlexCAN is in Pretended Networking mode. DLC is written by the FlexCAN module copied from the DLC (Data Length Code) field of the received frame. The DLC field indicates which.." line.long 0x4 "CAN_WMB0_ID,Wake Up Message Buffer Register for ID 0.Each of the four WMBs contains a register to store the ID information of an incoming Rx message. NOTE: The ID registers are located at 0x844 for WMB 0 . 0x854 for WMB1. 0x864 for WMB2. and 0x874 for.." hexmask.long 0x4 0.--28. 1. "ID,Received ID under Pretended Networking Mode - Stores the received ID as either: - The 29 bits of the extended frame format (considering the ID[28:0] field) or - The 11 bits of the standard frame format (considering the ID[28:18] field only. The.." line.long 0x8 "CAN_WMB0_D03,Wake Up Message Buffer Register for Data 0-3 0.Each of the four WMBs contains a register to store the data bytes O to 3 of the payload information of an incoming Rx message. This register's content is cleared when the incoming matched.." hexmask.long.byte 0x8 24.--31. 1. "DATA_BYTE_0,Received payload corresponding to data byte 0 under Pretended Networking mode." hexmask.long.byte 0x8 16.--23. 1. "DATA_BYTE_1,Received payload corresponding to data byte 1 under Pretended Networking mode." newline hexmask.long.byte 0x8 8.--15. 1. "DATA_BYTE_2,Received payload corresponding to data byte 2 under Pretended Networking mode." hexmask.long.byte 0x8 0.--7. 1. "DATA_BYTE_3,Received payload corresponding to data byte 3 under Pretended Networking mode." line.long 0xC "CAN_WMB0_D47,Wake Up Message Buffer Register for Data 4-7 0. Each of the four WMBs contains a register to store the data bytes 4 to 7 of the payload information of an incoming Rx message. This register's content is cleared when the incoming matched.." hexmask.long.byte 0xC 24.--31. 1. "DATA_BYTE_4,Received payload corresponding to data byte 4 under Pretended Networking mode." hexmask.long.byte 0xC 16.--23. 1. "DATA_BYTE_5,Received payload corresponding to data byte 5 under Pretended Networking mode." newline hexmask.long.byte 0xC 8.--15. 1. "DATA_BYTE_6,Received payload corresponding to data byte 6 under Pretended Networking mode." hexmask.long.byte 0xC 0.--7. 1. "DATA_BYTE_7,Received payload corresponding to data byte 7 under Pretended Networking mode." line.long 0x10 "CAN_WMB1_CS,Wake Up Message Buffer Register for C/S 1. Each of the four WMBs contains a register to store the Control Status (C/S) information (IDE. RTR. and DLC fields) of an incoming Rx message. NOTE: The C/S registers are located at 0x840 for WMB 0." bitfld.long 0x10 22. "SRR,Substitute Remote Request - Can be received either recessive or dominant." "0,1" newline bitfld.long 0x10 21. "IDE,ID Extended Bit - Identifies whether the frame format is standard or extended: - 1: Frame format is extended. - 0: Frame format is standard." "Frame format is standard,Frame format is extended" bitfld.long 0x10 20. "RTR,Remote Transmission Request Bit - Identifies whether the frame is remote or not: - 1: Frame is a remote frame. - 0: Frame is data frame (not remote)." "Frame is data frame,Frame is a remote frame" newline hexmask.long.byte 0x10 16.--19. 1. "DLC,Length of Data in Bytes - Length (in bytes) of the Rx data received when FlexCAN is in Pretended Networking mode. DLC is written by the FlexCAN module copied from the DLC (Data Length Code) field of the received frame. The DLC field indicates which.." line.long 0x14 "CAN_WMB1_ID,Wake Up Message Buffer Register for ID 1.Each of the four WMBs contains a register to store the ID information of an incoming Rx message. NOTE: The ID registers are located at 0x844 for WMB 0. 0x854 for WMB1. 0x864 for WMB2. and 0x874 for.." hexmask.long 0x14 0.--28. 1. "ID,Received ID under Pretended Networking Mode - Stores the received ID as either: - The 29 bits of the extended frame format (considering the ID[28:0] field) or - The 11 bits of the standard frame format (considering the ID[28:18] field only. The.." line.long 0x18 "CAN_WMB1_D03,Wake Up Message Buffer Register for Data 0-3 1. Each of the four WMBs contains a register to store the data bytes 4 to 7 of the payload information of an incoming Rx message. This register's content is cleared when the incoming matched.." hexmask.long.byte 0x18 24.--31. 1. "Data_byte_0,Data_byte_0" hexmask.long.byte 0x18 16.--23. 1. "Data_byte_1,Data_byte_1" newline hexmask.long.byte 0x18 8.--15. 1. "Data_byte_2,Data_byte_2" hexmask.long.byte 0x18 0.--7. 1. "Data_byte_3,Data_byte_3" line.long 0x1C "CAN_WMB1_D47,Wake Up Message Buffer Register for Data 4-7 1.Each of the four WMBs contains a register to store the data bytes 4 to 7 of the payload information of an incoming Rx message. This register's content is cleared when the incoming matched.." hexmask.long.byte 0x1C 24.--31. 1. "DATA_BYTE_4,Received payload corresponding to data byte 4 under Pretended Networking mode." hexmask.long.byte 0x1C 16.--23. 1. "DATA_BYTE_5,Received payload corresponding to data byte 5 under Pretended Networking mode." newline hexmask.long.byte 0x1C 8.--15. 1. "DATA_BYTE_6,Received payload corresponding to data byte 6 under Pretended Networking mode." hexmask.long.byte 0x1C 0.--7. 1. "DATA_BYTE_7,Received payload corresponding to data byte 7 under Pretended Networking mode." line.long 0x20 "CAN_WMB2_CS,Wake Up Message Buffer Register for C/S 2.Each of the four WMBs contains a register to store the Control Status (C/S) information (IDE. RTR. and DLC fields) of an incoming Rx message. NOTE: The C/S registers are located at 0x840 for WMB 0." bitfld.long 0x20 22. "SRR,Substitute Remote Request - Can be received either recessive or dominant." "0,1" newline bitfld.long 0x20 21. "IDE,ID Extended Bit - Identifies whether the frame format is standard or extended: - 1: Frame format is extended. - 0: Frame format is standard." "Frame format is standard,Frame format is extended" bitfld.long 0x20 20. "RTR,Remote Transmission Request Bit - Identifies whether the frame is remote or not: - 1: Frame is a remote frame. - 0: Frame is data frame (not remote)." "Frame is data frame,Frame is a remote frame" newline hexmask.long.byte 0x20 16.--19. 1. "DLC,Length of Data in Bytes - Length (in bytes) of the Rx data received when FlexCAN is in Pretended Networking mode. DLC is written by the FlexCAN module copied from the DLC (Data Length Code) field of the received frame. The DLC field indicates which.." line.long 0x24 "CAN_WMB2_ID,Wake Up Message Buffer Register for ID 2. Each of the four WMBs contains a register to store the ID information of an incoming Rx message. NOTE: The ID registers are located at 0x844 for WMB 0. 0x854 for WMB1. 0x864 for WMB2. and 0x874 for.." hexmask.long 0x24 0.--28. 1. "ID,Received ID under Pretended Networking Mode - Stores the received ID as either: - The 29 bits of the extended frame format (considering the ID[28:0] field) or - The 11 bits of the standard frame format (considering the ID[28:18] field only. The.." line.long 0x28 "CAN_WMB2_D03,Wake Up Message Buffer Register for Data 0-3 2.Each of the four WMBs contains a register to store the data bytes 4 to 7 of the payload information of an incoming Rx message. This register's content is cleared when the incoming matched.." hexmask.long.byte 0x28 24.--31. 1. "Data_byte_0,Data_byte_0" hexmask.long.byte 0x28 16.--23. 1. "Data_byte_1,Data_byte_1" newline hexmask.long.byte 0x28 8.--15. 1. "Data_byte_2,Data_byte_2" hexmask.long.byte 0x28 0.--7. 1. "Data_byte_3,Data_byte_3" line.long 0x2C "CAN_WMB2_D47,Wake Up Message Buffer Register for Data 4-7 2. Each of the four WMBs contains a register to store the data bytes 4 to 7 of the payload information of an incoming Rx message. This register's content is cleared when the incoming matched.." hexmask.long.byte 0x2C 24.--31. 1. "DATA_BYTE_4,Received payload corresponding to data byte 4 under Pretended Networking mode." hexmask.long.byte 0x2C 16.--23. 1. "DATA_BYTE_5,Received payload corresponding to data byte 5 under Pretended Networking mode." newline hexmask.long.byte 0x2C 8.--15. 1. "DATA_BYTE_6,Received payload corresponding to data byte 6 under Pretended Networking mode." hexmask.long.byte 0x2C 0.--7. 1. "DATA_BYTE_7,Received payload corresponding to data byte 7 under Pretended Networking mode." line.long 0x30 "CAN_WMB3_CS,Wake Up Message Buffer Register for C/S 3.Each of the four WMBs contains a register to store the Control Status (C/S) information (IDE. RTR. and DLC fields) of an incoming Rx message. NOTE: The C/S registers are located at 0x840 for WMB 0." bitfld.long 0x30 22. "SRR,Substitute Remote Request - Can be received either recessive or dominant." "0,1" newline bitfld.long 0x30 21. "IDE,ID Extended Bit - Identifies whether the frame format is standard or extended: - 1: Frame format is extended. - 0: Frame format is standard." "Frame format is standard,Frame format is extended" bitfld.long 0x30 20. "RTR,Remote Transmission Request Bit - Identifies whether the frame is remote or not: - 1: Frame is a remote frame. - 0: Frame is data frame (not remote)." "Frame is data frame,Frame is a remote frame" newline hexmask.long.byte 0x30 16.--19. 1. "DLC,Length of Data in Bytes - Length (in bytes) of the Rx data received when FlexCAN is in Pretended Networking mode. DLC is written by the FlexCAN module copied from the DLC (Data Length Code) field of the received frame. The DLC field indicates which.." line.long 0x34 "CAN_WMB3_ID,Wake Up Message Buffer Register for ID 3. Each of the four WMBs contains a register to store the ID information of an incoming Rx message. NOTE: The ID registers are located at 0x844 for WMB 0. 0x854 for WMB1. 0x864 for WMB2. and 0x874 for.." hexmask.long 0x34 0.--28. 1. "ID,Received ID under Pretended Networking Mode - Stores the received ID as either: - The 29 bits of the extended frame format (considering the ID[28:0] field) or - The 11 bits of the standard frame format (considering the ID[28:18] field only. The.." repeat 2. (list 0x3 0x2F )(list 0x0 0x4 ) rgroup.long ($2+0xB78)++0x3 line.long 0x0 "CAN_WMB3_D$1,Wake Up Message Buffer Register for Data 0-3 3. Each of the four WMBs contains a register to store the data bytes 4 to 7 of the payload information of an incoming Rx message. This register's content is cleared when the incoming matched.." hexmask.long.byte 0x0 24.--31. 1. "Data_byte_0,Data_byte_0" hexmask.long.byte 0x0 16.--23. 1. "Data_byte_1,Data_byte_1" newline hexmask.long.byte 0x0 8.--15. 1. "Data_byte_2,Data_byte_2" hexmask.long.byte 0x0 0.--7. 1. "Data_byte_3,Data_byte_3" repeat.end group.long 0xC00++0x7 line.long 0x0 "CAN_FDCTRL,The CAN_FDCTRL register contains control bits for CAN FD operation. CAN_FDCTRL also defines the data size of message buffers allocated in different partitions of RAM (memory blocks). When an 8-byte payload is selected: - Block RO allocates.." bitfld.long 0x0 31. "FDRATE,Bit Rate Switch Enable - Enables the effect of the Bit Rate Switch (BRS bit) during the data phase of Tx messages: - 1: Transmit a frame with bit rate switching if the BRS bit in the Tx MB is recessive. - 0: Transmit a frame in nominal rate. The.." "Transmit a frame in nominal rate,Transmit a frame with bit rate switching if the.." newline bitfld.long 0x0 25.--26. "MBDSR3,Message Buffer Data Size for Region 3 - Selects the data size for region R3 of message buffers allocated in RAM: - 00: Selects 8 bytes per message buffer. - 01: Selects 16 bytes per message buffer. - 10: Selects 32 bytes per message buffer. - 11:.." "Selects 8 bytes per message buffer,Selects 16 bytes per message buffer,?,Selects the data size for region R3 of message.." newline bitfld.long 0x0 22.--23. "MBDSR2,Message Buffer Data Size for Region 2 - Selects the data size for region R2 of message buffers allocated in RAM: - 00: Selects 8 bytes per message buffer. - 01: Selects 16 bytes per message buffer. - 10: Selects 32 bytes per message buffer. - 11:.." "Selects 8 bytes per message buffer,Selects 16 bytes per message buffer,Selects the data size for region R2 of message..,?" newline bitfld.long 0x0 19.--20. "MBDSR1,Message Buffer Data Size for Region 1 - Selects the data size for region R1 of message buffers allocated in RAM: - 00: Selects 8 bytes per message buffer. - 01: Selects 16 bytes per message buffer. - 10: Selects 32 bytes per message buffer. - 11:.." "Selects 8 bytes per message buffer,Selects 16 bytes per message buffer,?,?" newline bitfld.long 0x0 16.--17. "MBDSR0,Message Buffer Data Size for Region O - Selects the data size for region RO of message buffers allocated in RAM: - 00: Selects 8 bytes per message buffer. - 01: Selects 16 bytes per message buffer. - 10: Selects 32 bytes per message buffer. - 11:.." "Selects 8 bytes per message buffer,Selects 16 bytes per message buffer,?,?" bitfld.long 0x0 15. "TDCEN,Transceiver Delay Compensation Enable - Enables or disables the TDC feature: - 1: TDC is enabled. - 0: TDC is disabled. TDCEN can be written in Freeze mode only. Note: TDC must be disabled when Loop-Back mode is enabled (see CAN_CTRL1.LPB). Note:.." "TDC is disabled,TDC is enabled" newline bitfld.long 0x0 14. "TDCFAIL,Transceiver Delay Compensation Fail TDCFAIL indicates when the Transceiver Delay Compensation (TDC) mechanism is out of range unable to compensate the transceiver's loop delay and successfully compare the delayed received bits to the.." "Measured loop delay is in range,Measured loop delay is out of range" newline hexmask.long.byte 0x0 8.--12. 1. "TDCOFF,Transceiver Delay Compensation Offset TDCOFF contains the offset value to be added to the measured transceiver's loop delay in order to define the position of the delayed comparison point when bit rate switching is active. TDCOFF can be written in.." newline hexmask.long.byte 0x0 0.--5. 1. "TDCVAL,Transceiver Delay Compensation Value TDCVAL contains the value of the transceiver loop delay measured from the transmitted EDL to RO transition edge to the respective received one added to the TDCOFF value. This value is an integer multiple of the.." line.long 0x4 "CAN_FDCBT,The CAN_FDCBT register stores the CAN bit timing variables used in the data phase of CAN FD messages when CAN_FDCTRL.FDRATE is set. compatible with CAN FD specification. FPRESDIV. FPROPSEG. FPSEG1. FPSEG2. and FRJW are used to define the time.." hexmask.long.word 0x4 20.--29. 1. "FPRESDIV,Fast Prescaler Division Factor FPRESDIV defines the ratio between the PE clock frequency and the Serial Clock (Sclock) frequency in the data bit rate portion of a CAN FD message with the BRS bit set. The Sclock period defines the time quantum of.." newline bitfld.long 0x4 16.--18. "FRJW,Fast Resync Jump Width FRJW defines the maximum number of time quanta that a bit time can be changed by one re-synchronization in the data bit rate portion of a CAN FD message with the BRS bit set. Resync Jump Width = FSJW + 1. One time quantum is.." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x4 10.--14. 1. "FPROPSEG,Fast Propagation Segment FPROPSEG defines the length of the Propagation Segment in the bit time in the data bit rate portion of a CAN FD message with the BRS bit set. Propagation Segment Time = FPROPSEG x Time-Quanta Time-Quantum = one Sclock.." newline bitfld.long 0x4 5.--7. "FPSEG1,Fast Phase Segment 1 FPSEG1 defines the length of Phase Segment 1 in the bit time in the data bit rate portion of a CAN FD message with the BRS bit set. Phase Segment 1 = (FPSEG1 + 1) x Time-Quanta Time-Quantum = one Sclock period FPSEG1 can be.." "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 0.--2. "FPSEG2,Fast Phase Segment 2 FPSEG2 defines the length of Phase Segment 2 in the data bit rate portion of a CAN FD message with the BRS bit set. Phase Segment 2 = (FPSEG2 + 1) x Time-Quanta Time-Quantum = one Sclock period FPSEG2 can be written only in.." "0,1,2,3,4,5,6,7" rgroup.long 0xC08++0x3 line.long 0x0 "CAN_FDCRC,The CAN_CRCR register provides information about the CRC of transmitted messages for non-FD messages. CAN_CRCR only reports the 15 low order bits of CRC calculations for messages in CAN FD format that require either 17 or 21 bits. For CAN FD.." hexmask.long.byte 0x0 24.--30. 1. "FD_MBCRC,CRC Mailbox - Indicates the number of the mailbox corresponding to the value in the CAN CRCR.TXCRC field." newline hexmask.long.tbyte 0x0 0.--20. 1. "FD_TXCRC,Transmitted CRC Value - Indicates the CRC value of the last transmitted message for non-FD frames. For CAN FD frames the CRC value is reported in CAN_FDCRC." tree.end repeat.end elif (CORENAME()=="CORTEXA55") repeat 8. (increment 1. 1.) (list ad:0x30030000 ad:0x30040000 ad:0x30050000 ad:0x30060000 ad:0x30A80000 ad:0x30A90000 ad:0x30AA0000 ad:0x30AB0000) tree "CANFD$1" base $2 group.long 0x0++0xB line.long 0x0 "CAN_MCR,CAN_MCR defines global system configurations. such as the module operation modes and the maximum message buffer configuration." bitfld.long 0x0 31. "MDIS,Module Disable - Disables or enables the FlexCAN module: - 1: Disable the FlexCAN module. - 0: Enable the FlexCAN module. When disabled the FlexCAN disables the clocks to the PE and CHI submodules. MDIS is not affected by soft reset." "Enable the FlexCAN module,Disable the FlexCAN module" bitfld.long 0x0 30. "FRZ,Freeze Enable: - 1: Enabled to enter Freeze mode. - 0: Not enabled to enter Freeze mode. The FRZ bit specifies the FlexCAN behavior when CAN_MCR.HALT is set or when Debug mode is requested at chip level. When FRZ is asserted the FlexCAN is enabled.." "Not enabled to enter Freeze mode,Enabled to enter Freeze mode" newline bitfld.long 0x0 29. "RFEN,Legacy Rx FIFO Enable - Enables or disables the Legacy Rx FIFO feature: - 1: Enable Legacy Rx FIFO. - 0: Disable Legacy Rx FIFO. When RFEN is set MBs 0-5 cannot be used for normal reception and transmission because the corresponding memory region.." "Disable Legacy Rx FIFO,Enable Legacy Rx FIFO" bitfld.long 0x0 28. "HALT,Halt FlexCAN: - 1: Enter Freeze mode if the FRZ bit is asserted. - 0: No Freeze mode request. Assertion of HALT puts the FlexCAN module into Freeze mode. The CPU should clear HALT after initializing the message buffers and the control registers.." "No Freeze mode request,Enter Freeze mode if the FRZ bit is asserted" newline rbitfld.long 0x0 27. "NOTRDY,FlexCAN Not Ready: - 1: FlexCAN is either in Module Disable Doze Stop or Freeze mode. - 0: FlexCAN is either in Normal Listen-Only or Loop-Back mode. NOTRDY is a read-only bit that indicates that the FlexCAN is either in Module Disable Doze.." "FlexCAN is either in Normal,FlexCAN is either in Module Disable" bitfld.long 0x0 26. "WAKMSK,Wake Up Interrupt Mask - Enables Wake Up interrupt generation under the Self Wake Up mechanism: - 1: Enable Wake Up interrupt. - 0: Disable Wake Up interrupt." "Disable Wake Up interrupt,Enable Wake Up interrupt" newline bitfld.long 0x0 25. "SOFTRST,Soft Reset: - 1: Reset the registers affected by soft reset. - 0: No reset request. When SOFTRST is asserted the FlexCAN resets its internal state machines and some of the memory-mapped registers. SOFTRST can be asserted directly by the CPU by.." "No reset request,Reset the registers affected by soft reset" rbitfld.long 0x0 24. "FRZACK,Freeze Mode Acknowledge: - 1: FlexCAN in Freeze mode prescaler stopped. - 0: FlexCAN not in Freeze mode prescaler running. FRZACK is a read-only bit that indicates that the FlexCAN is in Freeze mode and its prescaler is stopped. A Freeze mode.." "FlexCAN not in Freeze mode,FlexCAN in Freeze mode" newline bitfld.long 0x0 23. "SUPV,Supervisor Mode - Configures the FlexCAN to be either in Supervisor or User mode: - 1: FlexCAN is in Supervisor mode. Affected registers allow only Supervisor access. Unrestricted access behaves as though the access was done to an unimplemented.." "FlexCAN is in User mode,FlexCAN is in Supervisor mode" bitfld.long 0x0 22. "SLFWAK,Self Wake Up - Enables the Self Wake Up feature when the FlexCAN is in a low-power mode other than Module Disable: - 1: Enable FlexCAN Self Wake Up feature. - 0: Disable FlexCAN Self Wake Up feature. When the Self Wake Up feature is enabled the.." "Disable FlexCAN Self Wake Up feature,Enable FlexCAN Self Wake Up feature" newline bitfld.long 0x0 21. "WRNEN,Warning Interrupt Enable: - 1: TWRNINT and RWRNINT bits are set when the respective error counter transitions from less than 96 to greater than or equal to 96. - 0: TWRNINT and RWRNINT bits are zero independent of the values in the error counters." "TWRNINT and RWRNINT bits are zero,TWRNINT and RWRNINT bits are set when the.." rbitfld.long 0x0 20. "LPMACK,Low-Power Mode Acknowledge: - 1: FlexCAN is in a low-power mode. - 0: FlexCAN is not in a low-power mode. LPMACK is a read-only bit that indicates that the FlexCAN is in a low-power mode (Module Disable Doze or Stop). A low-power mode cannot be.." "FlexCAN is not in a low-power mode,FlexCAN is in a low-power mode" newline bitfld.long 0x0 19. "WAKSRC,Wake Up Source - Controls whether the integrated low-pass filter is applied to protect the Rx CAN input from spurious wakeup: - 1: FlexCAN uses the filtered Rx input to detect recessive-to- dominant edges on the CAN bus. - 0: FlexCAN uses the.." "FlexCAN uses the unfiltered Rx input to detect..,FlexCAN uses the filtered Rx input to detect.." bitfld.long 0x0 18. "DOZE,Doze Mode Enable - Controls whether the FlexCAN is allowed to enter low-power mode when Doze mode is requested at chip level: - 1: FlexCAN is enabled to enter low-power mode when Doze mode is requested. - 0: FlexCAN is not enabled to enter low-power.." "FlexCAN is not enabled to enter low-power mode..,FlexCAN is enabled to enter low-power mode when.." newline bitfld.long 0x0 17. "SRXDIS,Self Reception Disable: - 1: Disable self-reception. - 0: Enable self-reception. SRXDIS controls whether the FlexCAN is allowed to receive frames transmitted by itself. If SRXDIS is asserted frames transmitted by the FlexCAN are not stored in any.." "Enable self-reception,Disable self-reception" bitfld.long 0x0 16. "IRMQ,Individual Rx Masking And Queue Enable: - 1: Enable individual Rx masking and queue feature. - 0: Disable individual Rx masking and queue feature. For backward compatibility with legacy applications the reading of C/S word locks the MB even if it.." "Disable individual Rx masking and queue feature,Enable individual Rx masking and queue feature" newline bitfld.long 0x0 15. "DMA,DMA Enable: - 1: Enable DMA feature for Rx FIFO. - 0: Disable DMA feature for Rx FIFO. The DMA bit enables or disables the DMA feature. The DMA feature can only be used with the Legacy Rx FIFO or the Enhanced Rx FIFO; consequently either.." "Disable DMA feature for Rx FIFO,Enable DMA feature for Rx FIFO" bitfld.long 0x0 14. "PNET_EN,Pretended Networking Enable - Enables the Pretended Networking functionality: - 1: Enable Pretended Networking mode. - 0: Disable Pretended Networking mode. When Pretended Networking is enabled the PE submodule is kept operational in Doze mode.." "Disable Pretended Networking mode,Enable Pretended Networking mode" newline bitfld.long 0x0 13. "LPRIOEN,Local Priority Enable: - 1: Enable Local Priority. - 0: Disable Local Priority. The LPRIOEN bit is provided for backward compatibility with legacy applications. LPRIOEN controls whether the Local Priority feature is enabled or not. Local Priority.." "Disable Local Priority,Enable Local Priority" bitfld.long 0x0 12. "AEN,Abort Enable - Enables the Tx abort mechanism: - 1: Enable abort. - 0: Disable abort. The Tx abort mechanism ensures a safe procedure for aborting a pending transmission so that no frame is sent on the CAN bus without notification." "Disable abort,Enable abort" newline bitfld.long 0x0 11. "FDEN,CAN FD Operation Enable - Enables CAN with Flexible Data rate (CAN FD) operation: - 1: CAN FD is enabled. The FlexCAN is able to receive and transmit messages in both CAN FD and CAN 2.0 formats. - 0: CAN FD is disabled. The FlexCAN is able to.." "CAN FD is disabled,CAN FD is enabled" newline bitfld.long 0x0 8.--9. "IDAM,ID Acceptance Mode - Identifies the format of the Legacy Rx FIFO ID Filter Table elements: - 00: Format A- One full ID (standard and extended) per ID Filter Table element. - 01: Format B - Two full standard IDs or two partial 14-bit (standard and.." "Format A,Format B,?,?" newline hexmask.long.byte 0x0 0.--6. 1. "MAXMB,Number of the Last Message Buffer - Defines the number of the last message buffer that will take part in the matching and arbitration processes. The reset value (OxOF) is equivalent to a 16 message buffer configuration. MAXMB can be written only in.." line.long 0x4 "CAN_CTRL1,The CAN_CTRL1 register is defined for specific FlexCAN control features related to the CAN bus. such as bit-rate. programmable sampling point within an Rx bit. Loop-Back mode. Listen-Only mode. Bus Off recovery behavior. and interrupt enabling.." hexmask.long.byte 0x4 24.--31. 1. "PRESDIV,Prescaler Division Factor - Defines the ratio between the PE clock frequency and the serial clock (Sclock) frequency. The Sclock period defines the time quantum of the CAN protocol. For the reset value the Sclock frequency is equal to the PE.." bitfld.long 0x4 22.--23. "RJW,Resync Jump Width - Defines the maximum number of time quanta that a bit time can be changed by one re-synchronization. One time quantum is equal to the Sclock period. The valid programmable values for RJW are 0-3. RJW can be written only in Freeze.." "0,1,2,3" newline bitfld.long 0x4 19.--21. "PSEG1,Phase Segment 1 - Defines the length of phase segment 1 in the bit time. The valid programmable values are 0-7. PSEG1 can be written only in Freeze mode because it is blocked by hardware in other modes. Phase Buffer Segment 1 = (PSEG1 + 1) x.." "?,Defines the length of phase segment 1 in the bit..,?,?,?,?,?,?" bitfld.long 0x4 16.--18. "PSEG2,Phase Segment 2 - Defines the length of phase segment 2 in the bit time. The valid programmable values are 1-7. PSEG2 can be written only in Freeze mode because it is blocked by hardware in other modes. Phase Buffer Segment 2 = (PSEG2 + 1) x.." "?,?,Defines the length of phase segment 2 in the..,?,?,?,?,?" newline bitfld.long 0x4 15. "BOFFMSK,Bus Off Interrupt Mask - Provides a mask for the Bus Off interrupt (CAN_ESR1.BOFFINT): - 1: Bus Off interrupt enabled. - 0: Bus Off interrupt disabled." "Bus Off interrupt disabled,Bus Off interrupt enabled" bitfld.long 0x4 14. "ERRMSK,Error Interrupt Mask - Provides a mask for the Error interrupt (CAN_ESR 1.ERRINT). - 1: Error interrupt enabled. - 0: Error interrupt disabled." "Error interrupt disabled,Error interrupt enabled" newline bitfld.long 0x4 13. "CLKSRC,CAN Engine Clock Source - Selects the clock source to the PE submodule to be either the peripheral clock or the oscillator clock: - 1: The PE clock source is the peripheral clock. - 0: The PE clock source is the oscillator clock. Under this.." "The PE clock source is the oscillator clock,The PE clock source is the peripheral clock" bitfld.long 0x4 12. "LPB,Loop-Back Mode - Configures the FlexCAN to operate in Loop-Back mode: - 1: Loop-Back enabled. - 0: Loop-Back disabled. In Loop-Back mode the FlexCAN performs an internal loop back that can be used for self-test operation. The bit stream output of.." "Loop-Back disabled,Loop-Back enabled" newline bitfld.long 0x4 11. "TWRNMSK,Tx Warning Interrupt Mask - Provides a mask for the Tx Warning interrupt (CAN-ESR1.TWRNINT): - 1: Tx Warning interrupt enabled. - 0: Tx Warning interrupt disabled. TWRNMSK is read as zero when CAN_MCR.WRNEN is negated. TWRNMSK can be written.." "Tx Warning interrupt disabled,Tx Warning interrupt enabled" bitfld.long 0x4 10. "RWRNMSK,Rx Warning Interrupt Mask - Provides a mask for the Rx Warning interrupt (CAN_ESR1.RWRNINT) - 1: Rx Warning interrupt enabled. - 0: Rx Warning interrupt disabled. RWRNMSK is read as zero when CAN_MCR.WRNEN is negated. RWRNMSK can be written only.." "Rx Warning interrupt disabled,Rx Warning interrupt enabled" newline bitfld.long 0x4 7. "SMP,CAN Bit Sampling - Defines the sampling mode of CAN bits at the Rx input: - 0: One sample is used to determine the bit value. - 1: Three samples are used to determine the value of the received bit:the regular sample (sample point) and two.." "One sample is used to determine the bit value,Three samples are used to determine the value of.." newline bitfld.long 0x4 6. "BOFFREC,Bus Off Recovery - Defines how the FlexCAN recovers from Bus Off state: - 0: Automatic recovering from Bus Off state enabled. - 1: Automatic recovering from Bus Off state disabled. If BOFFREC is negated automatic recovering from Bus Off state.." "Automatic recovering from Bus Off state enabled,Automatic recovering from Bus Off state disabled" bitfld.long 0x4 5. "TSYN,Timer Sync - Enables a mechanism that resets the free-running timer each time a message is received in message buffer 0: - 1: Timer Sync feature enabled. - 0: Timer Sync feature disabled. The Timer Sync feature provides a means to synchronize.." "Timer Sync feature disabled,Timer Sync feature enabled" newline bitfld.long 0x4 4. "LBUF,Lowest Buffer Transmitted First - Defines the ordering mechanism for message buffer transmission: - 1: Lowest number buffer is transmitted first. - 0: Buffer with highest priority is transmitted first. When LBUF is asserted the CAN_MCR.LPRIOEN bit.." "Buffer with highest priority is transmitted first,Lowest number buffer is transmitted first" bitfld.long 0x4 3. "LOM,Listen-Only Mode - Configures the FlexCAN to operate in Listen-Only mode: - 1: FlexCAN module operates in Listen-Only mode. - 0: Listen-Only mode is deactivated. In Listen-Only Mode mode transmission is disabled all error counters described in.." "Listen-Only mode is deactivated,FlexCAN module operates in Listen-Only mode" newline bitfld.long 0x4 0.--2. "PROPSEG,Propagation Segment - Defines the length of the propagation segment in the bit time. The valid programmable values are 0-7. PROPSEG can be written only in Freeze mode because it is blocked by hardware in other modes. Propagation segment time =.." "0,1,2,3,4,5,6,7" line.long 0x8 "CAN_TIMER,The CAN_TIMER register represents a 16-bit free-running counter that can be read and written by the CPU. The timer starts from 0x0 after reset. counts linearly to 0xFFFF. and wraps around. When CAN_CTRL2.TIMER_SRC is asserted. the timer is.." hexmask.long.word 0x8 0.--15. 1. "TIMER,Timer Value - Contains the free-running counter value." group.long 0x10++0x27 line.long 0x0 "CAN_RXMGMASK,The CAN_RXMGMASK register is located in RAM. CAN_RXMGMASK is provided for legacy application support: - When the CAN_MCR.IRMQ bit is negated. CAN_RXMGMASK is always in effect (the bits in the MG field will mask the mailbox filter bits). -.." hexmask.long 0x0 0.--31. 1. "MG,Rx Mailboxes Global Mask Bits: - 0: The corresponding bit in the filter is 'don't care'. - 1: The corresponding bit in the filter is checked. The MG bits mask the mailbox filter bits. Note that the alignment with the ID word of the mailbox is not.." line.long 0x4 "CAN_RX14MASK,The CAN_RX14MASK register is located in RAM. CAN_RX14MASK is provided for legacy application support. When the CAN_MCR.IRMQ bit is asserted. CAN_RX14MASK has no effect. CAN_RX14MASK is used to mask the filter fields of message buffer 14." hexmask.long 0x4 0.--31. 1. "RX14M,Rx Buffer 14 Mask Bits: - 0: The corresponding bit in the filter is 'don't care'. - 1: The corresponding bit in the filter is checked. Each mask bit masks the corresponding mailbox 14 filter field in the same way that CAN_RXMGMASK masks other.." line.long 0x8 "CAN_RX15MASK,The CAN_RX15MASK register is located in RAM. CAN_RX15MASK is provided for legacy application support. When the CAN_MCR.IRMQ bit is asserted. CAN_RX15MASK has no effect. CAN_RX15MASK is used to mask the filter fields of message buffer 15." hexmask.long 0x8 0.--31. 1. "RX15M,Rx Buffer 15 Mask Bits: - 0: The corresponding bit in the filter is 'don't care'. - 1: The corresponding bit in the filter is checked. Each mask bit masks the corresponding mailbox 15 filter field in the same way that CAN_RXMGMASK masks other.." line.long 0xC "CAN_ECR,The CAN_ECR register has four 8-bit fields reflecting the value of the FlexCAN error counters: - Transmit Error Counter (TXERRCNT field) - Receive Error Counter (RXERRCNT field) - Transmit Error Counter for errors detected in the Data Phase of.." hexmask.long.byte 0xC 24.--31. 1. "RXERRCNT_FAST,Receive Error Counter for Fast Bits - Receive error counter for errors detected in the Data Phase of received CAN FD messages with the BRS bit set. The RXERRCNT_FAST counter is read-only except in Freeze mode in which the CPU can write an.." hexmask.long.byte 0xC 16.--23. 1. "TXERRCNT_FAST,Transmit Error Counter for Fast Bits - Transmit error counter for errors detected in the Data Phase of transmitted CAN FD messages with the BRS bit set. The TXERRCNT_FAST counter is read-only except in Freeze mode in which the CPU can.." newline hexmask.long.byte 0xC 8.--15. 1. "RXERRCNT,Receive Error Counter - Receive error counter for all errors detected in received messages. The RXERRCNT counter is read-only except in Freeze mode in which it can be written by the CPU." hexmask.long.byte 0xC 0.--7. 1. "TXERRCNT,Transmit Error Counter - Transmit error counter for all errors detected in transmitted messages. The TXERRCNT counter is read-only except in Freeze mode in which it can be written by the CPU." line.long 0x10 "CAN_ESR1,Error and Status 1 Register. The CAN_ESR1 register reports various error conditions detected in the reception and transmission of a CAN frame. some general status of the device. and is the source of some interrupts to the CPU." rbitfld.long 0x10 31. "BIT1ERR_FAST,Bit1 Error in the Data Phase of CAN FD Frames with the BRS Bit Set BIT1ERR_FAST indicates when an inconsistency occurs between the transmitted and the received bitin the Data Phase of CAN FD frames with the BRS bit set: - 1: At least one.." "No such occurrence,At least one bit sent as recessive is received.." rbitfld.long 0x10 30. "BIT0ERR_FAST,Bit0 Error in the Data Phase of CAN FD Frames with the BRS Bit Set BIT0ERR_FAST indicates when an inconsistency occurs between the transmitted and the received bit in the Data Phase of CAN FD frames with the BRS bit set: - 1: At least one.." "No such occurrence,At least one bit sent as dominant is received as.." newline rbitfld.long 0x10 28. "CRCERR_FAST,Cyclic Redundancy Check Error in the CRC field of CAN FD Frames with the BRS Bit Set CRCERR_FAST indicates that a CRC error has been detected by the receivernode in the CRC field of CAN FD frames with the BRS bit set; that is the.." "No such occurrence,A CRC error occurred since last read of this.." newline rbitfld.long 0x10 27. "FRMERR_FAST,From Error in the Data Phase of CAN FD Frames with the BRS Bit Set FRMERR_FAST indicates that a form error has been detected by the receiver node in the Data Phase of CAN FD frames with the BRS bit set; that is a fixed-form bit field.." "No such occurrence,A form error occurred since last read of this.." rbitfld.long 0x10 26. "STFERR_FAST,Stuffing Error in the Data Phase of CAN FD Frames with the BRS Bit Set STFERR_FAST indicates that a stuffing error has been detected in the Data Phase of CAN FD frames with the BRS bit set: - 1: A stuffing error occurred since last read of.." "No such occurrence,A stuffing error occurred since last read of.." newline bitfld.long 0x10 21. "ERROVR,Error Overrun - Indicates that an error condition occurred when any error flag is already set: - 1: Overrun has occurred. - 0: Overrun has not occurred. ERROVR is cleared by writing 1 to it." "Overrun has not occurred,Overrun has occurred" newline bitfld.long 0x10 20. "ERRINT_FAST,Error Interrupt for Errors Detected in the Data Phase of CAN FD Frames with the BRS Bit Set: - 1: Indicates setting of any error bit detected in the Data Phase of CAN FD frames with the BRS bit set. - 0: No such occurrence." "No such occurrence,Indicates setting of any error bit detected in.." bitfld.long 0x10 19. "BOFFDONEINT,Bus Off Done Interrupt: - 1: FlexCAN module has completed Bus Off process. - 0: No such occurrence." "No such occurrence,FlexCAN module has completed Bus Off process" newline rbitfld.long 0x10 18. "SYNCH,CAN Synchronization Status: - 1: FlexCAN is synchronized to the CAN bus. - 0: FlexCAN is not synchronized to the CAN bus. SYNCH is a read-only flag that indicates whether the FlexCAN is synchronized to the CAN bus and able to participate in the.." "FlexCAN is not synchronized to the CAN bus,FlexCAN is synchronized to the CAN bus" bitfld.long 0x10 17. "TWRNINT,Tx Warning Interrupt Flag: - 1: The Tx error counter transitioned from less than 96 to greater than or equal to 96. - 0: No such occurrence." "No such occurrence,The Tx error counter transitioned from less than.." newline bitfld.long 0x10 16. "RWRNINT,Rx Warning Interrupt Flag: - 1: The Rx error counter transitioned from less than 96 to greater than or equal to 96. - 0: No such occurrence." "No such occurrence,The Rx error counter transitioned from less than.." rbitfld.long 0x10 15. "BIT1ERR,Bit1 Error - Indicates when an inconsistency occurs between the transmitted and the received bit in a non-CAN FD message or in the arbitration or Data Phase of a CAN FD message: - 1: At least one bit sent as recessive is received as dominant. -.." "No such occurrence,At least one bit sent as recessive is received.." newline rbitfld.long 0x10 14. "BIT0ERR,Bit0 Error - Indicates when an inconsistency occurs between the transmitted and the received bit in a non-CAN FD message or in the arbitration or Data Phase of a CAN FD message: - 1: At least one bit sent as dominant is received asrecessive. -.." "No such occurrence,At least one bit sent as dominant is received.." rbitfld.long 0x10 13. "ACKERR,Acknowledge Error - Indicates that an Acknowledge error was detected by the transmitter node (that is a dominant bit was detected during the ACK SLOT): - 1: An ACK error occurred since last read of this register. - 0: No such occurrence. ACKERR.." "No such occurrence,An ACK error occurred since last read of this.." newline rbitfld.long 0x10 12. "CRCERR,Cyclic Redundancy Check Error - Indicates that a CRC error was detected by the receiver node either in a non-FD message or in the arbitration or Data Phase of a frame in CAN FD format (that is the calculated CRC is different from the received.." "No such occurrence,A CRC error occurred since last read of this.." rbitfld.long 0x10 11. "FRMERR,Form Error - Indicates that a form error was detected by the receiver node in a non-FD message or in a CAN FD message arbitration or Data Phase (that is a fixed-form bit field contains at least one illegal bit): - 1: A form error occurred since.." "No such occurrence,A form error occurred since last read of this.." newline rbitfld.long 0x10 10. "STFERR,Stuffing Error - Indicates that a stuffing error was detected by the receiver node in a non-FD message or in a CAN FD message arbitration or Data Phase: - 1: A stuffing error occurred since last read of this register. - 0: No such occurrence." "No such occurrence,A stuffing error occurred since last read of.." rbitfld.long 0x10 9. "TXWRN,TX Error Warning - Indicates when repetitive errors are occurring during message transmission: - 1: TXERRCNT is greater than or equal to 96. - 0: No such occurrence. TXWRN is affected by the value of CAN_ECR.TXERRCNT only. TXWRN is not updated.." "No such occurrence,TXERRCNT is greater than or equal to 96" newline rbitfld.long 0x10 8. "RXWRN,Rx Error Warning - Indicates when repetitive errors are occurring during message reception: - 1: RXERRCNT is greater than or equal to 96. - 0: No such occurrence. RXWRN is affected by the value of CAN_ECR.RXERRCNT only. RXWRN is not updated during.." "No such occurrence,RXERRCNT is greater than or equal to 96" rbitfld.long 0x10 7. "IDLE,IDLE - Indicates when the CAN bus is in the IDLE state: - 1: CAN bus is now IDLE. - 0: No such occurrence." "No such occurrence,CAN bus is now IDLE" newline rbitfld.long 0x10 6. "TX,FlexCAN in Transmission - Indicates if the FlexCAN is transmitting a message: - 1: FlexCAN is transmitting a message. - 0: FlexCAN is not transmitting a message." "FlexCAN is not transmitting a message,FlexCAN is transmitting a message" rbitfld.long 0x10 4.--5. "FLTCONF,Fault Confinement State - Indicates the fault confinement state of the FlexCAN module: - 00: Error Active - 01: Error Passive - 1x: Bus Off If CAN_CTRL1.LOM is asserted after a delay that depends on the CAN bit timing the FLTCONF field will.." "Error Active,Error Passive,?,?" newline rbitfld.long 0x10 3. "RX,FlexCAN in Reception - Indicates if the FlexCAN is receiving a message: - 1: FlexCAN is receiving a message. - 0: FlexCAN is not receiving a message." "FlexCAN is not receiving a message,FlexCAN is receiving a message" bitfld.long 0x10 2. "BOFFINT,Bus Off Interrupt: - 1: FlexCAN module entered Bus Off state. - 0: No such occurrence. BOFFINT is set when the FlexCAN enters the Bus Off state. If the corresponding mask bit (CAN-CTRL1.BOFFMSK) is set an interrupt is generated to the CPU." "No such occurrence,FlexCAN module entered Bus Off state" newline bitfld.long 0x10 1. "ERRINT,Error Interrupt: - 1: Indicates setting of any error bit in CAN-ESR1. - 0: No such occurrence. ERRINT indicates that at least one of the error bits (BIT1ERR BITOERR ACKERR CRCERR FRMERR or STFERR) is set. If the corresponding mask bit.." "No such occurrence,Indicates setting of any error bit in CAN-ESR1" bitfld.long 0x10 0. "WAKINT,Wake Up Interrupt - Applies when the FlexCAN is in low-power mode under Self Wake Up mechanism either Doze mode or Stop mode: - 1: Indicates a recessive-to-dominant transition was received on the CAN bus. - 0: No such occurrence. When a.." "No such occurrence,Indicates a recessive-to-dominant transition was.." line.long 0x14 "CAN_IMASK2,Interrupt Masks 2 Register. The CAN_IMASK2 register allows any number of the 32 message buffer interrupts to be enabled or disabled for MB63 to MB32. CAN_IMASK2 contains one interrupt mask bit per buffer. enabling the CPU to determine which.." hexmask.long 0x14 0.--31. 1. "BUF63TO32M,Buffer MB i Mask Each bit enables or disables the corresponding FlexCAN Message Buffer Interrupt for MB63 to MB32: - 1: The corresponding buffer interrupt is enabled. - 0: The corresponding buffer interrupt is disabled." line.long 0x18 "CAN_IMASK1,Interrupt Masks 1 Register. The CAN_IMASK1 register allows any number of the 32 message buffer interrupts to be enabled or disabled for MB31 to MB. CAN_IMASK1 contains one interrupt mask bit per buffer. enabling the CPU to determine which.." hexmask.long 0x18 0.--31. 1. "BUF31TO0M,Buffer MB i Mask Each bit enables or disables the corresponding FlexCAN Message Buffer Interrupt for MB31 to MBO: - 1: The corresponding buffer interrupt is enabled. - 0: The corresponding buffer interrupt is disabled." line.long 0x1C "CAN_IFLAG2,Interrupt Flags 2 Register. The CAN_IFLAG2 register defines the flags for the 32 message buffer interrupts for MB63 to MB32. CAN_IFLAG2 contains one interrupt flag bit per buffer. Each successful transmission or reception sets the respective.." hexmask.long 0x1C 0.--31. 1. "BUF63TO321,Buffer MB i Interrupt Each bit flags the corresponding FlexCAN Message Buffer Interrupt for MB63 to MB32: - 1: The corresponding buffer has successfully completed transmission or reception. - 0: The corresponding buffer has no occurrence of.." line.long 0x20 "CAN_IFLAG1,Interrupt Flags 1 Register. The CAN_IFLAG1 register defines the flags for the 32 message buffer interrupts for MB31 to MB0. CAN_IFLAG1 contains one interrupt flag bit per buffer. Each successful transmission or reception sets the corresponding.." hexmask.long.tbyte 0x20 8.--31. 1. "BUF31T081,Buffer MBi Interrupt Each bit flags the corresponding FlexCAN Message Buffer Interrupt for MB31 to MB8: - 1: The corresponding buffer has successfully completed transmission or reception. - 0: The corresponding buffer has no occurrence of.." bitfld.long 0x20 7. "BUF71,Buffer MB 7 Interrupt or Legacy Rx FIFO Overflow: - 1: MB7 completed transmission/reception when CAN_MCR.RFEN=O or Legacy Rx FIFO overflow when CAN_MCR.RFEN=1. - 0: No occurrence of MB7 completing transmission/reception when CAN_MCR.RFEN=O or of.." "No occurrence of MB7 completing..,MB7 completed transmission/reception when CAN_MCR" newline bitfld.long 0x20 6. "BUF61,Buffer MB6 Interrupt or Legacy Rx FIFO Warning: - 1: MB6 completed transmission/reception when CAN_MCR.RFEN=0 or Legacy Rx FIFO almost full when CAN_MCR.RFEN=1. - 0: No occurrence of MB6 completing transmission/reception when CAN_MCR.RFEN=O or of.." "No occurrence of MB6 completing..,MB6 completed transmission/reception when CAN_MCR" bitfld.long 0x20 5. "BUF51,Buffer MB5 Interrupt or Frames Available in Legacy Rx FIFO: - 1: MB5 completed transmission/reception when CAN_MCR.RFEN=0 or frame(s) available in the Legacy Rx FIFO when CAN_MCR.RFEN=1. BUF51 generates a OMA request when both CAN_MCR.RFEN and.." "No occurrence of MB5 completing..,MB5 completed transmission/reception when CAN_MCR" newline hexmask.long.byte 0x20 1.--4. 1. "BUF4T011,Buffer MB Interrupt or Reserved: - 1: The corresponding buffer has successfully completed transmission or reception when CAN_MCR.RFEN=O. - 0: The corresponding buffer has no occurrence of successfully completed transmission or reception when.." bitfld.long 0x20 0. "BUF01,Buffer MBO Interrupt or Clear Legacy Rx FIFO bit When CAN_MCR.RFEN is cleared (Legacy Rx FIFO disabled) BUF0I flags the interrupt for MB0: - 1: MB0 has successfully completed transmission or reception when CAN_MCR.RFEN=O. - 0: MB0 has no.." "MB0 has no occurrence of successfully completed..,MB0 has successfully completed transmission or.." line.long 0x24 "CAN_CTRL2,Control 2 Register. The CAN_CTRL2 register complements CAN_CTRL1. providing control bits for memory write access in Freeze mode. for extending Legacy Rx FIFO filter quantity. and for adjusting the operation of internal FlexCAN processes like.." bitfld.long 0x24 31. "ERRMSK_FAST,Error Interrupt Mask for errors detected in the Data Phase of fast CAN FD frames ERRMSK_FAST provides a mask for the ERRINT_FAST Interrupt in CAN_ESR1: - 1: ERRINT_FAST error interrupt enabled. - 0: ERRINT_FAST error interrupt disabled." "ERRINT_FAST error interrupt disabled,ERRINT_FAST error interrupt enabled" bitfld.long 0x24 30. "BOFFDONEMSK,Bus Off Done Interrupt Mask - Provides a mask for the Bus Off done interrupt in CAN_ESR1: - 1: Bus Off done interrupt enabled. - 0: Bus Off done interrupt disabled." "Bus Off done interrupt disabled,Bus Off done interrupt enabled" newline bitfld.long 0x24 29. "ECRWRE,Error-Correction Configuration Register Write Enable - Enables the CAN-MECR register to be updated: - 1: Enable update. - 0: Disable update." "Disable update,Enable update" bitfld.long 0x24 28. "WRMFRZ,Write-Access To Memory In Freeze Mode - Enable unrestricted write access to FlexCAN memory in Freeze mode: - 0: Maintain the write access restrictions. - 1: Enable unrestricted write access to FlexCAN memory. WRMFRZ can only be written in Freeze.." "Maintain the write access restrictions,Enable unrestricted write access to FlexCAN memory" newline hexmask.long.byte 0x24 24.--27. 1. "RFFN,Number of Legacy Rx FIFO Filters - Defines the number of Legacy Rx FIFO filters. The maximum selectable number of filters is a function of configuration parameter NUMBER_OF_MB. RFFN must not be programmed with values that cause the number of message.." hexmask.long.byte 0x24 19.--23. 1. "TASD,Tx Arbitration Start Delay - Indicates how many CAN bits the Tx arbitration process start point can be delayed from the first bit of CRC field on CAN bus." newline bitfld.long 0x24 18. "MRP,Mailboxes Reception Priority: - 1: Matching starts from mailboxes and continues on Legacy Rx FIFO. - 0: Matching starts from Legacy Rx FIFO and continues on mailboxes. If MRP is set the matching process starts from the mailboxes and if no match.." "Matching starts from Legacy Rx FIFO and..,Matching starts from mailboxes and continues on.." bitfld.long 0x24 17. "RRS,Remote Request Storing: - 1: Remote Request Frame is stored. - 0: Remote Response Frame is generated. If RRS is asserted a Remote Request Frame is submitted to a matching process and stored in the corresponding message buffer in the same fashion as.." "Remote Response Frame is generated,Remote Request Frame is stored" newline bitfld.long 0x24 16. "EACEN,Entire Frame Arbitration Field Comparison Enable for Rx Mailboxes: - 1: Enables the comparison of both the IDE and RTR bits of an Rx mailbox filter with the corresponding bits of the incoming frame. Mask bits do apply. - 0: Rx mailbox filter's IDE.." "Rx mailbox filter's IDE bit is always compared..,Enables the comparison of both the IDE and RTR.." bitfld.long 0x24 15. "TIMER_SRC,Timer Source - Selects the time tick source used for incrementing the free-running timer counter: - 1: The free-running timer is clocked by an external time tick. The period can be either adjusted to be equal to the baud rate on the CAN bus or.." "The free-running timer is clocked by the CAN bit..,The free-running timer is clocked by an external.." newline bitfld.long 0x24 14. "PREXCEN,Protocol Exception Enable - Enables the protocol exception feature: - 1: Protocol exception is enabled. - 0: Protocol exception is disabled. PREXCEN is writable only in Freeze mode. PREXCEN is not available (reserved write 0) if parameter FD EN.." "Protocol exception is disabled,Protocol exception is enabled" newline bitfld.long 0x24 12. "ISOCANFDEN,ISO CAN FD Enable - 1: Enable ISO CAN FD compliant operation. - 0: Disable ISO CAN FD specific features (non-ISO CAN FD operation). ISOCANFDEN enables ISO CAN FD compliant operation by enabling the following features which are part of the ISO.." "Disable ISO CAN FD specific features,Enable ISO CAN FD compliant operation" bitfld.long 0x24 11. "EDFLTDIS,Edge Filter Disable - Disables the edge filter used during the bus integration state: - 1: Edge filter is disabled. - 0: Edge filter is enabled. When the edge filter is enabled two consecutive nominal time quanta with dominant bus state are.." "Edge filter is enabled,Edge filter is disabled" newline rgroup.long 0x38++0x3 line.long 0x0 "CAN_ESR2,Error and Status 2 Register. The CAN_ESR2 register reports some general status information." hexmask.long.byte 0x0 16.--22. 1. "LPTM,Lowest Priority Tx Mailbox If CAN_ESR2.VPS is asserted LPTM indicates the lowest number inactive mailbox. If there is no inactive mailbox then the mailbox indicated depends on the CAN_CTRL1.LBUF bit value: - If CAN_CTRL1.LBUF is negated the.." newline bitfld.long 0x0 14. "VPS,Valid Priority Status - Indicates whether CAN_ESR2.IMB and CAN_ESR2.LPTM contents are currently valid or not: - 1: Contents of IMB and LPTM are valid. - 0: Contents of IMB and LPTM are invalid. VPS is asserted upon every complete Tx arbitration.." "Contents of IMB and LPTM are invalid,Contents of IMB and LPTM are valid" newline bitfld.long 0x0 13. "IMB,Inactive Mailbox If CAN_ESR2.VPS is asserted IMB indicates whether there is any inactive mailbox (CODE field is either 0b1000 or 0b0000): - 1: If CAN_ESR2.VPS is asserted there is at least one inactive mailbox. CAN_ESR2.LPTM content is the number.." "If CAN_ESR2,If CAN_ESR2" rgroup.long 0x44++0x3 line.long 0x0 "CAN_CRCR,The CAN_CRCR register provides information about the CRC of transmitted messages for non-FD messages. CAN_CRCR only reports the 15 low order bits of CRC calculations for messages in CAN FD format that require either 17 or 21 bits. For CAN FD.." hexmask.long.byte 0x0 16.--22. 1. "MBCRC,CRC Mailbox - Indicates the number of the mailbox corresponding to the value in the CAN CRCR.TXCRC field." newline hexmask.long.word 0x0 0.--14. 1. "TXCRC,Transmitted CRC Value - Indicates the CRC value of the last transmitted message for non-FD frames. For CAN FD frames the CRC value is reported in CAN_FDCRC." group.long 0x48++0x3 line.long 0x0 "CAN_RXFGMASK,Rx FIFO Global Mask Register. The CAN_RXFGMASK register is located in RAM. If the Legacy Rx FIFO is enabled. CAN_RXFGMASK is used to mask the Legacy Rx FIFO ID Filter Table elements that do not have a corresponding CAN_RXIMR according to.." hexmask.long 0x0 0.--31. 1. "FGM,Legacy Rx FIFO Global Mask Bits These bits mask the Legacy Rx FIFO ID Filter Table elements bits in a perfect alignment: - 1: The corresponding bit in the filter is checked. - 0: The corresponding bit in the filter is 'don't care'." rgroup.long 0x4C++0x3 line.long 0x0 "CAN_RXFIR,Rx FIFO Information Register. The CAN_RXFIR register provides information on the Legacy Rx FIFO. CAN_RXFIR is the port through which the CPU accesses the output of the Legacy RXFIR FIFO located in RAM. The Legacy RXFIR FIFO is written by the.." hexmask.long.word 0x0 0.--8. 1. "IDHIT,Identifier Acceptance Filter Hit Indicator - Indicates which Identifier Acceptance Filter was hit by the received message that is in the output of the Legacy Rx FIFO. If multiple filters match the incoming message ID the first matching IDAF found.." group.long 0x50++0x3 line.long 0x0 "CAN_CBT,CAN Bit Timing Register. The CAN_CBT register is an alternative way to store the CAN bit timing variables described in the CAN_CTRL1 register. EPRESDIV. EPROPSEG. EPSEG1. EPSEG2. and ERJW are extended versions of CAN_CTRL1 register PRESDIV." bitfld.long 0x0 31. "BTF,Bit Timing Format Enable - Enables the use of extended CAN bit timing fields EPRESDIV EPROPSEG EPSEG1 EPSEG2 and ERJW replacing the CAN bit timing variables defined in CAN_CTRL1: - 1: Extended bit time definitions enabled. - 0: Extended bit time.." "Extended bit time definitions disabled,Extended bit time definitions enabled" hexmask.long.word 0x0 21.--30. 1. "EPRESDIV,Extended Prescaler Division Factor When CAN_CBT.BTF is asserted EPRESDIV defines the ratio between the PE clock frequency and the Serial Clock (Sclock) frequency. EPRESDIV extends the CAN_CTRL1.PRESDIV value range. Sclock frequency = PE clock.." newline hexmask.long.byte 0x0 16.--20. 1. "ERJW,Extended Resync Jump Width When CAN_CBT.BTF is asserted ERJW defines the maximum number of time quanta that a bit time can be changed by one re- synchronization. ERJW extends the CAN_CTRL1.RJW value range. Resync Jump Width = ERJW + 1 One time.." hexmask.long.byte 0x0 10.--15. 1. "EPROPSEG,Extended Propagation Segment When CAN_CBT.BTF is asserted EPROPSEG defines the length of the Propagation Segment in the bit time. EPROPSEG extends the CAN_CTRL 1.PROPSEG value range. Propagation Segment Time = (EPROPSEG + 1) x Time-Quanta.." newline hexmask.long.byte 0x0 5.--9. 1. "EPSEG1,Extended Phase Segment 1 When CAN_CBT.BTF is asserted EPSEG1 defines the length of Phase Segment 1 in the bit time. EPSEG1 extends the CAN_CTRL 1.PSEG1 value range. Phase Buffer Segment 1 = (EPSEG1 + 1) x Time-Quanta Time-Quantum = one Sclock.." hexmask.long.byte 0x0 0.--4. 1. "EPSEG2,Extended Phase Segment 2 When CAN_CBT.BTF is asserted EPSEG2 defines the length of Phase Segment 2 in the bit time. EPSEG2 extends the CAN_CTRL1.PSEG2 value range. Phase Buffer Segment 1 = (EPSEG2 + 1) x Time-Quanta Time-Quantum = one Sclock.." group.long 0x68++0xF line.long 0x0 "CAN_IMASK4,Interrupt Masks 4 Register. The CAN_IMASK4 register allows any number of the 32 message buffer interrupts to be enabled or disabled for MB127 to MB96. CAN_IMASK4 contains one interrupt mask bit per buffer. enabling the CPU to determine which.." hexmask.long 0x0 0.--31. 1. "BUF127T096M,Buffer MB i Mask Each bit enables or disables the corresponding FlexCAN Message Buffer Interrupt for MB127 to MB96: - 1: The corresponding buffer interrupt is enabled. - 0: The corresponding buffer interrupt is disabled. When CAN FD is.." line.long 0x4 "CAN_IMASK3,Interrupt Masks 3 Register. The CAN_IMASK3 register allows any number of the 32 message buffer interrupts to be enabled or disabled for MB95 to MB64. CAN_IMASK3 contains one interrupt mask bit per buffer. enabling the CPU to determine which.." hexmask.long 0x4 0.--31. 1. "BUF95T064M,Buffer MB i Mask Each bit enables or disables the corresponding FlexCAN Message Buffer Interrupt for MB95 to MB64: - 1: The corresponding buffer interrupt is enabled. - 0: The corresponding buffer interrupt is disabled. When CAN FD is enabled.." line.long 0x8 "CAN_IFLAG4,Interrupt Flags 4 Register. The CAN_IFLAG4 register defines the flags for the 32 message buffer interrupts for MB127 to MB96. CAN_IFLAG4 contains one interrupt flag bit per buffer. Each successful transmission or reception sets the respective.." hexmask.long 0x8 0.--31. 1. "BUF127T096,Buffer MB Interrupt Each bit flags the corresponding FlexCAN Message Buffer Interrupt for MB127 to MB96: - 1: The corresponding buffer has successfully completed transmission or reception. - 0: The corresponding buffer has no occurrence of.." line.long 0xC "CAN_IFLAG3,Interrupt Flags 3 Register. The CAN_IFLAG3 register defines the flags for the 32 Message Buffer interrupts for MB95 to MB64. CAN_IFLAG3 contains one interrupt flag bit per buffer. Each successful transmission or reception sets the respective.." hexmask.long 0xC 0.--31. 1. "BUF95T064,Buffer MB i Interrupt Each bit flags the corresponding FlexCAN Message Buffer Interrupt for MB95 to MB64: - 1: The corresponding buffer has successfully completed transmission or reception. - 0: The corresponding buffer has no occurrence of.." group.long 0x880++0x27 line.long 0x0 "CAN_RXIMR0,Rx Individual Mask Register 0. The Rx Individual Mask Registers are used to store the acceptance masks for ID filtering in Rx MBs and the Legacy Rx FIFO. When the Legacy Rx FIFO is disabled (CAN_MCR.RFEN is negated). an individual mask is.." hexmask.long 0x0 0.--31. 1. "MI,Individual Mask Bits: 1'b1: The corresponding bit in the filter is checked. 1'b0: The corresponding bit in the filter is 'don't care'." line.long 0x4 "CAN_RXIMR1,Rx Individual Mask Register 1. The Rx Individual Mask Registers are used to store the acceptance masks for ID filtering in Rx MBs and the Legacy Rx FIFO. When the Legacy Rx FIFO is disabled (CAN_MCR.RFEN is negated). an individual mask is.." hexmask.long 0x4 0.--31. 1. "MI,Individual Mask Bits: 1'b1: The corresponding bit in the filter is checked. 1'b0: The corresponding bit in the filter is 'don't care'." line.long 0x8 "CAN_RXIMR2,Rx Individual Mask Register 2. The Rx Individual Mask Registers are used to store the acceptance masks for ID filtering in Rx MBs and the Legacy Rx FIFO. When the Legacy Rx FIFO is disabled (CAN_MCR.RFEN is negated). an individual mask is.." hexmask.long 0x8 0.--31. 1. "MI,Individual Mask Bits: - 1'b1: The corresponding bit in the filter is checked. - 1'b0: The corresponding bit in the filter is 'don't care'." line.long 0xC "CAN_RXIMR3,Rx Individual Mask Register 3. The Rx Individual Mask Registers are used to store the acceptance masks for ID filtering in Rx MBs and the Legacy Rx FIFO. When the Legacy Rx FIFO is disabled (CAN_MCR.RFEN is negated). an individual mask is.." hexmask.long 0xC 0.--31. 1. "MI,Individual Mask Bits: 1'b1: The corresponding bit in the filter is checked. 1'b0: The corresponding bit in the filter is 'don't care'." line.long 0x10 "CAN_RXIMR4,Rx Individual Mask Register 4. The Rx Individual Mask Registers are used to store the acceptance masks for ID filtering in Rx MBs and the Legacy Rx FIFO. When the Legacy Rx FIFO is disabled (CAN_MCR.RFEN is negated). an individual mask is.." hexmask.long 0x10 0.--31. 1. "MI,Individual Mask Bits: 1'b1: The corresponding bit in the filter is checked. 1'b0: The corresponding bit in the filter is 'don't care'." line.long 0x14 "CAN_RXIMR5,Rx Individual Mask Register 5. The Rx Individual Mask Registers are used to store the acceptance masks for ID filtering in Rx MBs and the Legacy Rx FIFO. When the Legacy Rx FIFO is disabled (CAN_MCR.RFEN is negated). an individual mask is.." hexmask.long 0x14 0.--31. 1. "MI,Individual Mask Bits: 1'b1: The corresponding bit in the filter is checked. 1'b0: The corresponding bit in the filter is 'don't care'." line.long 0x18 "CAN_RXIMR6,Rx Individual Mask Register 6. The Rx Individual Mask Registers are used to store the acceptance masks for ID filtering in Rx MBs and the Legacy Rx FIFO. When the Legacy Rx FIFO is disabled (CAN_MCR.RFEN is negated). an individual mask is.." hexmask.long 0x18 0.--31. 1. "MI,Individual Mask Bits: 1'b1: The corresponding bit in the filter is checked. 1'b0: The corresponding bit in the filter is 'don't care'." line.long 0x1C "CAN_RXIMR7,Rx Individual Mask Register 7. The Rx Individual Mask Registers are used to store the acceptance masks for ID filtering in Rx MBs and the Legacy Rx FIFO. When the Legacy Rx FIFO is disabled (CAN_MCR.RFEN is negated). an individual mask is.." hexmask.long 0x1C 0.--31. 1. "MI,Individual Mask Bits: 1'b1: The corresponding bit in the filter is checked. 1'b0: The corresponding bit in the filter is 'don't care'." line.long 0x20 "CAN_RXIMR8,Rx Individual Mask Register 8. The Rx Individual Mask Registers are used to store the acceptance masks for ID filtering in Rx MBs and the Legacy Rx FIFO. When the Legacy Rx FIFO is disabled (CAN_MCR.RFEN is negated). an individual mask is.." hexmask.long 0x20 0.--31. 1. "MI,Individual Mask Bits: 1'b1: The corresponding bit in the filter is checked. 1'b0: The corresponding bit in the filter is 'don't care'." line.long 0x24 "CAN_RXIMR9,Rx Individual Mask Register 9.The Rx Individual Mask Registers are used to store the acceptance masks for ID filtering in Rx MBs and the Legacy Rx FIFO. When the Legacy Rx FIFO is disabled (CAN_MCR.RFEN is negated). an individual mask is.." hexmask.long 0x24 0.--31. 1. "MI,Individual Mask Bits: 1'b1: The corresponding bit in the filter is checked. 1'b0: The corresponding bit in the filter is 'don't care'." repeat 16. (list 0xA 0xB 0xC 0xD 0xE 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1A 0x1B 0x1C )(list 0x0 0x4 0x8 0xC 0x10 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C 0x40 0x44 0x48 ) group.long ($2+0x8A8)++0x3 line.long 0x0 "CAN_RXIMR$1,Rx Individual Mask Register 10. The Rx Individual Mask Registers are used to store the acceptance masks for ID filtering in Rx MBs and the Legacy Rx FIFO. When the Legacy Rx FIFO is disabled (CAN_MCR.RFEN is negated). an individual mask is.." hexmask.long 0x0 0.--31. 1. "MI,Individual Mask Bits: 1'b1: The corresponding bit in the filter is checked. 1'b0: The corresponding bit in the filter is 'don't care'." repeat.end repeat 9. (list 0x1D 0x1E 0x24 0x25 0x26 0x27 0x28 0x29 0x3E )(list 0x4C 0x50 0x68 0x6C 0x70 0x74 0x78 0x7C 0xD0 ) group.long ($2+0x8A8)++0x3 line.long 0x0 "CAN_RXIMR$1,Rx Individual Mask Register 10. The Rx Individual Mask Registers are used to store the acceptance masks for ID filtering in Rx MBs and the Legacy Rx FIFO. When the Legacy Rx FIFO is disabled (CAN_MCR.RFEN is negated). an individual mask is.." hexmask.long 0x0 0.--31. 1. "MI,Individual Mask Bits: 1'b1: The corresponding bit in the filter is checked. 1'b0: The corresponding bit in the filter is 'don't care'." repeat.end group.long 0x8BC++0xB line.long 0x0 "CAN_RXIMR15,Rx Individual Mask Register 15.The Rx Individual Mask Registers are used to store the acceptance masks for ID filtering in Rx MBs and the Legacy Rx FIFO. When the Legacy Rx FIFO is disabled (CAN_MCR.RFEN is negated). an individual mask is.." hexmask.long 0x0 0.--31. 1. "MI,Individual Mask Bits: - 1'b1: The corresponding bit in the filter is checked. - 1'b0: The corresponding bit in the filter is 'don't care'." line.long 0x4 "CAN_RXIMR16,Rx Individual Mask Register 16.The Rx Individual Mask Registers are used to store the acceptance masks for ID filtering in Rx MBs and the Legacy Rx FIFO. When the Legacy Rx FIFO is disabled (CAN_MCR.RFEN is negated). an individual mask is.." hexmask.long 0x4 0.--31. 1. "MI,Individual Mask Bits: - 1'b1: The corresponding bit in the filter is checked. - 1'b0: The corresponding bit in the filter is 'don't care'." line.long 0x8 "CAN_RXIMR17,Rx Individual Mask Register 17.The Rx Individual Mask Registers are used to store the acceptance masks for ID filtering in Rx MBs and the Legacy Rx FIFO. When the Legacy Rx FIFO is disabled (CAN_MCR.RFEN is negated). an individual mask is.." hexmask.long 0x8 0.--31. 1. "MI,Individual Mask Bits: - 1'b1: The corresponding bit in the filter is checked. - 1'b0: The corresponding bit in the filter is 'don't care'." group.long 0x8FC++0x13 line.long 0x0 "CAN_RXIMR31,Rx Individual Mask Register 31.The Rx Individual Mask Registers are used to store the acceptance masks for ID filtering in Rx MBs and the Legacy Rx FIFO. When the Legacy Rx FIFO is disabled (CAN_MCR.RFEN is negated). an individual mask is.." hexmask.long 0x0 0.--31. 1. "MI,Individual Mask Bits: - 1'b1: The corresponding bit in the filter is checked. - 1'b0: The corresponding bit in the filter is 'don't care'." line.long 0x4 "CAN_RXIMR32,Rx Individual Mask Register 32.The Rx Individual Mask Registers are used to store the acceptance masks for ID filtering in Rx MBs and the Legacy Rx FIFO. When the Legacy Rx FIFO is disabled (CAN_MCR.RFEN is negated). an individual mask is.." hexmask.long 0x4 0.--31. 1. "MI,Individual Mask Bits: - 1'b1: The corresponding bit in the filter is checked. - 1'b0: The corresponding bit in the filter is 'don't care'." line.long 0x8 "CAN_RXIMR33,Rx Individual Mask Register 33.The Rx Individual Mask Registers are used to store the acceptance masks for ID filtering in Rx MBs and the Legacy Rx FIFO. When the Legacy Rx FIFO is disabled (CAN_MCR.RFEN is negated). an individual mask is.." hexmask.long 0x8 0.--31. 1. "MI,Individual Mask Bits: - 1'b1: The corresponding bit in the filter is checked. - 1'b0: The corresponding bit in the filter is 'don't care'." line.long 0xC "CAN_RXIMR34,Rx Individual Mask Register 34.The Rx Individual Mask Registers are used to store the acceptance masks for ID filtering in Rx MBs and the Legacy Rx FIFO. When the Legacy Rx FIFO is disabled (CAN_MCR.RFEN is negated). an individual mask is.." hexmask.long 0xC 0.--31. 1. "MI,Individual Mask Bits: - 1'b1: The corresponding bit in the filter is checked. - 1'b0: The corresponding bit in the filter is 'don't care'." line.long 0x10 "CAN_RXIMR35,Rx Individual Mask Register 35.The Rx Individual Mask Registers are used to store the acceptance masks for ID filtering in Rx MBs and the Legacy Rx FIFO. When the Legacy Rx FIFO is disabled (CAN_MCR.RFEN is negated). an individual mask is.." hexmask.long 0x10 0.--31. 1. "MI,Individual Mask Bits: - 1'b1: The corresponding bit in the filter is checked. - 1'b0: The corresponding bit in the filter is 'don't care'." group.long 0x928++0x4F line.long 0x0 "CAN_RXIMR42,Rx Individual Mask Register 42.The Rx Individual Mask Registers are used to store the acceptance masks for ID filtering in Rx MBs and the Legacy Rx FIFO. When the Legacy Rx FIFO is disabled (CAN_MCR.RFEN is negated). an individual mask is.." hexmask.long 0x0 0.--31. 1. "MI,Individual Mask Bits: - 1: The corresponding bit in the filter is checked. - 0: The corresponding bit in the filter is 'don't care'." line.long 0x4 "CAN_RXIMR43,Rx Individual Mask Register 43.The Rx Individual Mask Registers are used to store the acceptance masks for ID filtering in Rx MBs and the Legacy Rx FIFO. When the Legacy Rx FIFO is disabled (CAN_MCR.RFEN is negated). an individual mask is.." hexmask.long 0x4 0.--31. 1. "MI,Individual Mask Bits: - 1: The corresponding bit in the filter is checked. - 0: The corresponding bit in the filter is 'don't care'." line.long 0x8 "CAN_RXIMR44,Rx Individual Mask Register 44.The Rx Individual Mask Registers are used to store the acceptance masks for ID filtering in Rx MBs and the Legacy Rx FIFO. When the Legacy Rx FIFO is disabled (CAN_MCR.RFEN is negated). an individual mask is.." hexmask.long 0x8 0.--31. 1. "MI,Individual Mask Bits: - 1: The corresponding bit in the filter is checked. - 0: The corresponding bit in the filter is 'don't care'." line.long 0xC "CAN_RXIMR45,Rx Individual Mask Register 45.The Rx Individual Mask Registers are used to store the acceptance masks for ID filtering in Rx MBs and the Legacy Rx FIFO. When the Legacy Rx FIFO is disabled (CAN_MCR.RFEN is negated). an individual mask is.." hexmask.long 0xC 0.--31. 1. "MI,Individual Mask Bits: - 1: The corresponding bit in the filter is checked. - 0: The corresponding bit in the filter is 'don't care'." line.long 0x10 "CAN_RXIMR46,Rx Individual Mask Register 46.The Rx Individual Mask Registers are used to store the acceptance masks for ID filtering in Rx MBs and the Legacy Rx FIFO. When the Legacy Rx FIFO is disabled (CAN_MCR.RFEN is negated). an individual mask is.." hexmask.long 0x10 0.--31. 1. "MI,Individual Mask Bits: - 1: The corresponding bit in the filter is checked. - 0: The corresponding bit in the filter is 'don't care'." line.long 0x14 "CAN_RXIMR47,Rx Individual Mask Register 47.The Rx Individual Mask Registers are used to store the acceptance masks for ID filtering in Rx MBs and the Legacy Rx FIFO. When the Legacy Rx FIFO is disabled (CAN_MCR.RFEN is negated). an individual mask is.." hexmask.long 0x14 0.--31. 1. "MI,Individual Mask Bits: - 1: The corresponding bit in the filter is checked. - 0: The corresponding bit in the filter is 'don't care'." line.long 0x18 "CAN_RXIMR48,Rx Individual Mask Register 48.The Rx Individual Mask Registers are used to store the acceptance masks for ID filtering in Rx MBs and the Legacy Rx FIFO. When the Legacy Rx FIFO is disabled (CAN_MCR.RFEN is negated). an individual mask is.." hexmask.long 0x18 0.--31. 1. "MI,Individual Mask Bits: - 1: The corresponding bit in the filter is checked. - 0: The corresponding bit in the filter is 'don't care'." line.long 0x1C "CAN_RXIMR49,Rx Individual Mask Register 49.The Rx Individual Mask Registers are used to store the acceptance masks for ID filtering in Rx MBs and the Legacy Rx FIFO. When the Legacy Rx FIFO is disabled (CAN_MCR.RFEN is negated). an individual mask is.." hexmask.long 0x1C 0.--31. 1. "MI,Individual Mask Bits: - 1: The corresponding bit in the filter is checked. - 0: The corresponding bit in the filter is 'don't care'." line.long 0x20 "CAN_RXIMR50,Rx Individual Mask Register 50.The Rx Individual Mask Registers are used to store the acceptance masks for ID filtering in Rx MBs and the Legacy Rx FIFO. When the Legacy Rx FIFO is disabled (CAN_MCR.RFEN is negated). an individual mask is.." hexmask.long 0x20 0.--31. 1. "MI,Individual Mask Bits: - 1: The corresponding bit in the filter is checked. - 0: The corresponding bit in the filter is 'don't care'." line.long 0x24 "CAN_RXIMR51,Rx Individual Mask Register 51.The Rx Individual Mask Registers are used to store the acceptance masks for ID filtering in Rx MBs and the Legacy Rx FIFO. When the Legacy Rx FIFO is disabled (CAN_MCR.RFEN is negated). an individual mask is.." hexmask.long 0x24 0.--31. 1. "MI,Individual Mask Bits: - 1: The corresponding bit in the filter is checked. - 0: The corresponding bit in the filter is 'don't care'." line.long 0x28 "CAN_RXIMR52,Rx Individual Mask Register 52.The Rx Individual Mask Registers are used to store the acceptance masks for ID filtering in Rx MBs and the Legacy Rx FIFO. When the Legacy Rx FIFO is disabled (CAN_MCR.RFEN is negated). an individual mask is.." hexmask.long 0x28 0.--31. 1. "MI,Individual Mask Bits: - 1: The corresponding bit in the filter is checked. - 0: The corresponding bit in the filter is 'don't care'." line.long 0x2C "CAN_RXIMR53,Rx Individual Mask Register 53.The Rx Individual Mask Registers are used to store the acceptance masks for ID filtering in Rx MBs and the Legacy Rx FIFO. When the Legacy Rx FIFO is disabled (CAN_MCR.RFEN is negated). an individual mask is.." hexmask.long 0x2C 0.--31. 1. "MI,Individual Mask Bits: - 1: The corresponding bit in the filter is checked. - 0: The corresponding bit in the filter is 'don't care'." line.long 0x30 "CAN_RXIMR54,Rx Individual Mask Register 54.The Rx Individual Mask Registers are used to store the acceptance masks for ID filtering in Rx MBs and the Legacy Rx FIFO. When the Legacy Rx FIFO is disabled (CAN_MCR.RFEN is negated). an individual mask is.." hexmask.long 0x30 0.--31. 1. "MI,Individual Mask Bits: - 1: The corresponding bit in the filter is checked. - 0: The corresponding bit in the filter is 'don't care'." line.long 0x34 "CAN_RXIMR55,Rx Individual Mask Register 55.The Rx Individual Mask Registers are used to store the acceptance masks for ID filtering in Rx MBs and the Legacy Rx FIFO. When the Legacy Rx FIFO is disabled (CAN_MCR.RFEN is negated). an individual mask is.." hexmask.long 0x34 0.--31. 1. "MI,Individual Mask Bits: - 1: The corresponding bit in the filter is checked. - 0: The corresponding bit in the filter is 'don't care'." line.long 0x38 "CAN_RXIMR56,Rx Individual Mask Register 56.The Rx Individual Mask Registers are used to store the acceptance masks for ID filtering in Rx MBs and the Legacy Rx FIFO. When the Legacy Rx FIFO is disabled (CAN_MCR.RFEN is negated). an individual mask is.." hexmask.long 0x38 0.--31. 1. "MI,Individual Mask Bits: - 1: The corresponding bit in the filter is checked. - 0: The corresponding bit in the filter is 'don't care'." line.long 0x3C "CAN_RXIMR57,Rx Individual Mask Register 57.The Rx Individual Mask Registers are used to store the acceptance masks for ID filtering in Rx MBs and the Legacy Rx FIFO. When the Legacy Rx FIFO is disabled (CAN_MCR.RFEN is negated). an individual mask is.." hexmask.long 0x3C 0.--31. 1. "MI,Individual Mask Bits: - 1: The corresponding bit in the filter is checked. - 0: The corresponding bit in the filter is 'don't care'." line.long 0x40 "CAN_RXIMR58,Rx Individual Mask Register 58.The Rx Individual Mask Registers are used to store the acceptance masks for ID filtering in Rx MBs and the Legacy Rx FIFO. When the Legacy Rx FIFO is disabled (CAN_MCR.RFEN is negated). an individual mask is.." hexmask.long 0x40 0.--31. 1. "MI,Individual Mask Bits: - 1: The corresponding bit in the filter is checked. - 0: The corresponding bit in the filter is 'don't care'." line.long 0x44 "CAN_RXIMR59,Rx Individual Mask Register 59.The Rx Individual Mask Registers are used to store the acceptance masks for ID filtering in Rx MBs and the Legacy Rx FIFO. When the Legacy Rx FIFO is disabled (CAN_MCR.RFEN is negated). an individual mask is.." hexmask.long 0x44 0.--31. 1. "MI,Individual Mask Bits: - 1: The corresponding bit in the filter is checked. - 0: The corresponding bit in the filter is 'don't care'." line.long 0x48 "CAN_RXIMR60,Rx Individual Mask Register 60.The Rx Individual Mask Registers are used to store the acceptance masks for ID filtering in Rx MBs and the Legacy Rx FIFO. When the Legacy Rx FIFO is disabled (CAN_MCR.RFEN is negated). an individual mask is.." hexmask.long 0x48 0.--31. 1. "MI,Individual Mask Bits: - 1: The corresponding bit in the filter is checked. - 0: The corresponding bit in the filter is 'don't care'." line.long 0x4C "CAN_RXIMR61,Rx Individual Mask Register 61.The Rx Individual Mask Registers are used to store the acceptance masks for ID filtering in Rx MBs and the Legacy Rx FIFO. When the Legacy Rx FIFO is disabled (CAN_MCR.RFEN is negated). an individual mask is.." hexmask.long 0x4C 0.--31. 1. "MI,Individual Mask Bits: - 1: The corresponding bit in the filter is checked. - 0: The corresponding bit in the filter is 'don't care'." group.long 0x97C++0x3 line.long 0x0 "CAN_RXIMR63,Rx Individual Mask Register 63. The Rx Individual Mask Registers are used to store the acceptance masks for ID filtering in Rx MBs and the Legacy Rx FIFO. When the Legacy Rx FIFO is disabled (CAN_MCR.RFEN is negated). an individual mask is.." hexmask.long 0x0 0.--31. 1. "MI,Individual Mask Bits: - 1: The corresponding bit in the filter is checked. - 0: The corresponding bit in the filter is 'don't care'. Each Individual Mask Bit masks the corresponding bit in both the mailbox filter and Legacy Rx FIFO ID Filter Table.." group.long 0xAE0++0xF line.long 0x0 "CAN_MECR,The CAN_MECR register contains control bits for memory error detection and correction (ECC). NOTE: When CAN_CTRL2.ECRWRE is 0. writes to CAN_MECR are blocked. with the exception of the ECRWRDIS bit. The CAN_MECR register is not available when.." bitfld.long 0x0 31. "ECRWRDIS,Error Configuration Register Write Disable - Disables writes to this register: - 1: Write is disabled. - 0: Write is enabled. ECRWRDIS is automatically set to 1 (disabled) when CTRL2.ECRWRE is asserted." "Write is enabled,Write is disabled" newline bitfld.long 0x0 19. "HANCEI_MSK,Host Access With Non-Correctable Errors Interrupt Mask Enables the interrupt in case of non-correctable errors detected in memory reads issued by the host (CPU): - 1: Interrupt is enabled. - 0: Interrupt is disabled." "Interrupt is disabled,Interrupt is enabled" bitfld.long 0x0 18. "FANCEI_MSK,FlexCAN Access With Non-Correctable Errors Interrupt Mask Enables the interrupt in case of non-correctable errors detected in memory reads issued by the FlexCAN internal processes: - 1: Interrupt is enabled. - 0: Interrupt is disabled." "Interrupt is disabled,Interrupt is enabled" newline bitfld.long 0x0 16. "CEI_MSK,Correctable Errors Interrupt Mask Enables the interrupt in case of correctable errors detected in memory reads issued by the host or FlexCAN internal processes: - 1: Interrupt is enabled. - 0: Interrupt is disabled." "Interrupt is disabled,Interrupt is enabled" newline bitfld.long 0x0 15. "HAERRIE,Host Access Error Injection Enable Enables the injection of errors only in memory reads issued by the host (CPU): - 1: Injection is enabled. - 0: Injection is disabled." "Injection is disabled,Injection is enabled" bitfld.long 0x0 14. "FAERRIE,FlexCAN Access Error Injection Enable Enables the injection of errors only in memory reads issued by the FlexCAN internal processes: - 1: Injection is enabled. - 0: Injection is disabled." "Injection is disabled,Injection is enabled" newline bitfld.long 0x0 13. "EXTERRIE,Extended Error Injection Enable Memory accesses performed by internal FlexCAN processes are 64-bit accesses. EXTERRIE extends the error injection on 32-bit memory accesses to the complementary 32-bit word using the same 32-bit error injection.." "Error injection is applied only to the 32-bit word,Error injection is applied to the 64-bit word" newline bitfld.long 0x0 9. "RERDIS,Error Report Disable - Disables the update of the error report registers: - 1: Disable updates of the error report registers. The update of error-related flags and the generation of bus transfer errors are still active. - 0: Enable updates of the.." "Enable updates of the error report registers,Disable updates of the error report registers" bitfld.long 0x0 8. "ECCDIS,Error Correction Disable - Disables the memory detection and correction mechanism: - 1: Disable memory error correction. - 0: Enable memory error correction. In addition to disabling the error report mechanism ECCDIS = 1 also stops the update of.." "Enable memory error correction,Disable memory error correction" newline bitfld.long 0x0 7. "NCEFAFRZ,Non-Correctable Errors in FlexCAN Access Put Device In Freeze Mode Determines the response when a non-correctable error is detected in a memory read performed by FlexCAN internal processes: - 1: Put FlexCAN in Freeze mode. In this case entering.." "Keep normal operation,Put FlexCAN in Freeze mode" line.long 0x4 "CAN_ERRIAR,The CAN_ERRIAR register holds the address where a memory read error is to be injected. The size and usage of the FlexCAN RAM depends on the FlexCAN hardware configuration. The CAN_ERRIAR register is not available when parameter ECC_EN is 0." hexmask.long.word 0x4 2.--13. 1. "INJADDR_H,Error Injection Address High - Defines the twelve most significant bits of the physical RAM address where a memory read error is to be injected" newline rbitfld.long 0x4 0.--1. "INJADDR_L,Error Injection Address Low - Read-only field that defines the two least significant bits of the physical RAM address where a memory read error is to be injected. INJADDR - L[1:0] are always zero to ensure that the address is on a 32-bit.." "0,1,2,3" line.long 0x8 "CAN_ERRIDPR,The CAN_ERRIDPR register holds the error pattern to be injected in the data word read from memory. The CAN_ERRIDPR register is not available when parameter ECC_EN is 0." hexmask.long 0x8 0.--31. 1. "DFLIP,Data Flip Pattern Bits set to 1 in the flip pattern cause the corresponding data bit in the word read from memory to invert." line.long 0xC "CAN_ERRIPPR,The CAN_ERRIPPR register holds the error pattern to be injected in parity bits read from memory along with data word. Bits set to 1 in the flip pattern cause the corresponding parity bit in the word read from memory to invert. The CAN_ERRIPPR.." hexmask.long.byte 0xC 24.--28. 1. "PFLIP3,Parity Flip Pattern For Byte 3 (most significant)" newline hexmask.long.byte 0xC 16.--20. 1. "PFLIP2,Parity Flip Pattern For Byte 2" newline hexmask.long.byte 0xC 8.--12. 1. "PFLIP1,Parity Flip Pattern For Byte 2" newline hexmask.long.byte 0xC 0.--4. 1. "PFLIP0,Parity Flip Pattern For Byte O (least significant)" rgroup.long 0xAF0++0xB line.long 0x0 "CAN_RERRAR,The CAN_RERRAR register reports the address used for an access in which an error (correctable or non-correctable) was detected. and reports the identification of the source of that access. The address is always reported using a 32-bit.." bitfld.long 0x0 24. "NCE,Non-Correctable Error - Indicates that the report is due to a non-correctable error: - 1: Reporting a non-correctable error - 0: Reporting a correctable-error" "Reporting a correctable-error,Reporting a non-correctable error" newline bitfld.long 0x0 16.--18. "SAID,SAID[2] - Identification of the requestor of the memory read request: - 0: Requested by FlexCAN internal processes - 1: Requested by host (CPU) SAID[1] - Details of FlexCAN operation: - 0: Move - 1: Scanning SAID[0] - Operation that requested the.." "Transmission,Reception,?,?,?,?,?,?" newline hexmask.long.word 0x0 0.--13. 1. "ERRADDR,Address Where the Error was Detected" line.long 0x4 "CAN_RERRDR,The CAN_RERRDR register reports the raw data (unmodified by the correction performed by ECC logic) read from memory with error. The value reported does not represent the transient values of the BUSY bit when reading a message buffer. The.." hexmask.long 0x4 0.--31. 1. "RDATA,Raw data word read from memory with error." line.long 0x8 "CAN_RERRSYNR,The CAN_RERRSYNR register holds the syndrome detected in a memory read with error. It also reports the bytes that were read in this 32-bit read transaction." bitfld.long 0x8 31. "BE3,Byte Enabled For Byte 3 (most significant) - 1: The byte was read. - 0: The byte was not read." "The byte was not read,The byte was read" newline hexmask.long.byte 0x8 24.--28. 1. "SYND3,Error Syndrome For Byte 3 (most significant)" bitfld.long 0x8 23. "BE2,Byte Enabled for Byte 2." "0,1" newline hexmask.long.byte 0x8 16.--20. 1. "SYND2,Error Syndrome For Byte 2" newline bitfld.long 0x8 15. "BE1,Byte Enabled for Byte 1." "0,1" newline hexmask.long.byte 0x8 8.--12. 1. "SYND1,Error Syndrome For Byte 1" bitfld.long 0x8 7. "BE0,Byte Enabled for Byte 0 (least significant)." "0,1" newline hexmask.long.byte 0x8 0.--4. 1. "SYND0,Error Syndrome For Byte O (least significant)" group.long 0xAFC++0x2B line.long 0x0 "CAN_ERRSR,The CAN_ERRSR register holds the status bits of the error correction and detection operations. These flags can be cleared by writing 1 to them. Writing O has no effect. The CAN_ERRSR register is not available when parameter ECC_EN is 0." bitfld.long 0x0 19. "HANCEIF,FlexCAN Access With Non-Correctable Error Interrupt Flag: - 1: A non-correctable error was detected in a FlexCAN access. - 0: No non-correctable errors were detected in FlexCAN accesses so far. FANCEIF = 1 indicates that a non-correctable error.." "No non-correctable errors were detected in..,A non-correctable error was detected in a.." newline bitfld.long 0x0 18. "FANCEIF,FlexCAN Access With Non-Correctable Error Interrupt Flag: - 1: A non-correctable error was detected in a FlexCAN access. - 0: No non-correctable errors were detected in FlexCAN accesses so far. FANCEIF = 1 indicates that a non-correctable error.." "No non-correctable errors were detected in..,A non-correctable error was detected in a.." newline bitfld.long 0x0 16. "CEIF,Correctable Error Interrupt Flag: - 1: A correctable error was detected. - 0: No correctable errors were detected so far. CEIF = 1 indicates that a correctable error was detected in a memory read. If CAN_MECR.CEI_MSK is set the interrupt is asserted." "No correctable errors were detected so far,A correctable error was detected" newline bitfld.long 0x0 3. "HANCEIOF,Host Access With Non-Correctable Error Interrupt Overrun Flag: - 1: Overrun on non-correctable errors in host access. - 0: No overrun on non-correctable errors in host access. HANCEIOF = 1 indicates that a non-correctable error was detected in a.." "No overrun on non-correctable errors in host..,Overrun on non-correctable errors in host access" bitfld.long 0x0 2. "FANCEIOF,FlexCAN Access With Non-Correctable Error Interrupt Overrun Flag: - 1: Overrun on non-correctable errors in FlexCAN access. - 0: No overrun on non-correctable errors in FlexCAN access. FANCEIOF = 1 indicates that a non-correctable error was.." "No overrun on non-correctable errors in FlexCAN..,Overrun on non-correctable errors in FlexCAN.." newline bitfld.long 0x0 0. "CEIOF,Correctable Error Interrupt Overrun Flag: - 1: Overrun on correctable errors. - 0: No overrun on correctable errors. CEIOF = 1 indicates that a correctable error was detected in a memory read when CEIF was set. No interrupt is associated with this.." "No overrun on correctable errors,Overrun on correctable errors" line.long 0x4 "CAN_CTRL1_PN,The CAN_CTRL1_PN register contains control bits for Pretended Networking mode filtering selection. Configure CAN_CTRL1_PN with the filter criteria to be used to receive wakeup messages. CAN_CTRL1_PN bits other than WTOF_MSK and WUMF_MSK can.." bitfld.long 0x4 17. "WTOF_MSK,Wake Up by Timeout Flag Mask Bit - Masks the generation of a wakeup event originated by a timeout: - 1: Timeout wakeup event is enabled. - 0: Timeout wakeup event is disabled." "Timeout wakeup event is disabled,Timeout wakeup event is enabled" newline bitfld.long 0x4 16. "WUMF_MSK,Wake Up by Match Flag Mask Bit - Masks the generation of a wakeup event originated by a successful filtered Rx message - 1: Wakeup match event is enabled. - 0: Wakeup match event is disabled." "Wakeup match event is disabled,Wakeup match event is enabled" hexmask.long.byte 0x4 8.--15. 1. "NMATCH,Number of Messages Matching the Same Filtering Criteria NMATCH defines the number of times a given message must match the predefined filtering criteria for ID and/or PL before generating a wakeup event. This quantity can be configured in the 1 to.." newline bitfld.long 0x4 4.--5. "PLFS,Payload Filtering Selection - Selects the level of payload filtering to be applied when FlexCAN is under Pretended Networking mode: - 00: Match upon a payload contents against an exact target value. - 01: Match upon a payload value greater than or.." "Match upon a payload contents against an exact..,Match upon a payload value greater than or equal..,?,?" newline bitfld.long 0x4 2.--3. "IDFS,ID Filtering Selection - Selects the level of ID filtering to be applied when FlexCAN is under Pretended Networking mode: - 00: Match upon a ID contents against an exact target value. - 01: Match upon a ID value greater than or equal to a specified.." "Match upon a ID contents against an exact target..,Match upon a ID value greater than or equal to a..,?,?" bitfld.long 0x4 0.--1. "FCS,Filtering Combination Selection - Selects the filtering criteria to be applied when FlexCAN is under Pretended Networking mode: - 00: Message ID filtering only. - 01: Message ID filtering and payload filtering. - 10: Message ID filtering occurring a.." "Message ID filtering only,Message ID filtering and payload filtering,?,?" line.long 0x8 "CAN_CTRL2_PN,The CAN_CTRL2_PN register contains configuration bits for the timeout value under Pretended Networking mode. CAN_CTRL2_PN can be written in Freeze mode only. The CAN_CTRL2_PN register is not available when parameter PNET_EN is 0." hexmask.long.word 0x8 0.--15. 1. "MATCHTO,Timeout for No Message Matching the Filtering Criteria MATCHTO defines a timeout value that generates a wakeup event if CAN_MCR.PNET _EN is asserted. If the timeout counter reaches the target value when the FlexCAN is under Pretended Networking.." line.long 0xC "CAN_WU_MTC,The CAN_WU_MTC register contains wakeup information related to the matching processes performed while the FlexCAN receives frames under Pretended Networking mode. The CAN_WU_MTC register is not available when parameter PNET_EN is 0." bitfld.long 0xC 17. "WTOF,Wake Up by Timeout Flag Bit - Indicates whether the FlexCAN has detected a timeout event during a time interval defined by CAN CTRL2 PN.MATCHTO: - 1: Wakeup by timeout event detected. - 0: No wakeup by timeout event detected. WTOF generates a wakeup.." "No wakeup by timeout event detected,Wakeup by timeout event detected" newline bitfld.long 0xC 16. "WUMF,Wake Up by Match Flag Bit - Indicates whether the FlexCAN has detected a matching Rx incoming message that passed the filtering criteria specified in CAN_CTRL1_PN: - 1: Wakeup by match event detected. - 0: No wakeup by match event detected. WUMF.." "No wakeup by match event detected,Wakeup by match event detected" hexmask.long.byte 0xC 8.--15. 1. "MCOUNTER,Number of Matches while in Pretended Networking MCOUNTER reports the number of times a given message has matched the predefined filtering criteria for ID and/or PL before a wakeup event. MCOUNTER is reset by the FlexCAN when it enters in.." newline line.long 0x10 "CAN_FLT_ID1,The CAN_FLT_1D1 register contains the FLT_1D1 target value and the IDE and RTR target values used to filter an incoming message ID. FLT_1D1 is used either for equal to. smaller than. greater than comparisons. or as the lower limit value in an.." bitfld.long 0x10 30. "FLT_IDE,ID Extended Filter - Identifies whether the frame format is standard or extended: - 1: Accept extended frame format. - 0: Accept standard frame format. FLT_IDE is used as part of the ID reception filter." "Accept standard frame format,Accept extended frame format" newline bitfld.long 0x10 29. "FLT_RTR,Remote Transmission Request Filter - Identifies whether the frame is remote or not: - 1: Accept remote frame. - 0: Reject remote frame (accept data frame). FLT_RTR is used as part of the ID reception Filter." "Reject remote frame,Accept remote frame" hexmask.long 0x10 0.--28. 1. "FLT_ID1,ID Filter 1 for Pretended Networking Filtering - Defines either the 29 bits of an extended frame format considering all bits or the 11 bits of a standard frame format considering just the 11 leftmost bits." line.long 0x14 "CAN_FLT_DLC,The CAN_FLT_DLC register contains the DLC inside range target values (FLT_DLC_LO and FLT_DLC_HI) used to filter an incoming message. The DLC range is used only for payload filtering. CAN_FLT_DLC can be written in Freeze mode only. NOTE: When.." hexmask.long.byte 0x14 16.--19. 1. "FLT_DLC_LO,Lower Limit for Length of Data Bytes Filter - Specifies the lower limit for the number of data bytes considered valid for payload comparison. FLT_DLC_LO is used as part of payload reception Filter." newline hexmask.long.byte 0x14 0.--3. 1. "FLT_DLC_HI,Upper Limit for Length of Data Bytes Filter - Specifies the upper limit for the number of data bytes considered valid for payload comparison. FLT_DLC_HI is used as part of payload reception filter." line.long 0x18 "CAN_PL1_LO,The CAN_PL1_LO register contains Payload Filter 1 low order bits of the target value used to filter incoming message payload. It is used either for 'equal to'. 'smaller than or equal to'. 'greater than or equal to' comparisons. or as the lower.." hexmask.long.byte 0x18 24.--31. 1. "DATA_BYTE_0,Filter 1 low order bits for Pretended Networking payload fittermg corresponding to data byte 0." hexmask.long.byte 0x18 16.--23. 1. "DATA_BYTE_1,Filter 1 low order bits for Pretended Networking payload fittermg corresponding to data byte 1." newline hexmask.long.byte 0x18 8.--15. 1. "DATA_BYTE_2,Filter 1 low order bits for Pretended Networking payload fittermg corresponding to data byte 2." hexmask.long.byte 0x18 0.--7. 1. "DATA_BYTE_3,Filter 1 low order bits for Pretended Networking payload fittermg corresponding to data byte 3." line.long 0x1C "CAN_PL1_HI,The CAN_PL1_HI register contains Payload Filter 1 high order bits of the target value used to filter incoming message payload. It is used either for 'equal to'. 'smaller than or equal to'. 'greater than or equal to' comparisons. or as the.." hexmask.long.byte 0x1C 24.--31. 1. "DATA_BYTE_4,Filter 1 low order bits for Pretended Networking payload filtermg corresponding to data byte 4." hexmask.long.byte 0x1C 16.--23. 1. "DATA_BYTE_5,Filter 1 low order bits for Pretended Networking payload filtermg corresponding to data byte 5." newline hexmask.long.byte 0x1C 8.--15. 1. "DATA_BYTE_6,Filter 1 low order bits for Pretended Networking payload filtermg corresponding to data byte 6." hexmask.long.byte 0x1C 0.--7. 1. "DATA_BYTE_7,Filter 1 low order bits for Pretended Networking payload filtermg corresponding to data byte 7." line.long 0x20 "CAN_FLT_ID2_IDMASK,The CAN_FLT_ID2_1DMASK register contains the FLT_ID2 target value used only as the upper limit value in ID range detection. Also. when exact ID filtering criteria is selected. CAN_FLT_ID2_1DMASK is used to store the ID mask. The.." bitfld.long 0x20 30. "IDE_MSK,ID Extended Mask Bit - Indicates whether the frame format (standard/extended) is used as part of the ID reception filter - 1: The corresponding bit in the filter is checked. - 0: The corresponding bit in the filter is 'don't care'." "The corresponding bit in the filter is 'don't..,The corresponding bit in the filter is checked" newline bitfld.long 0x20 29. "RTR_MSK,Remote Transmission Request Mask Bit - Indicates whether the frame type (data/remote) is part of the ID reception filter: - 1: The corresponding bit in the filter is checked. - 0: The corresponding bit in the filter is 'don't care'." "The corresponding bit in the filter is 'don't..,The corresponding bit in the filter is checked" hexmask.long 0x20 0.--28. 1. "FLT_ID2_IDMASK,ID Filter 2 for Pretended Networking Filtering / ID Mask Bits for Pretended Networking ID Filtering FLT_ID2_1DMASK is used as FLT_ID2 in range of ID filtering to define the ID filter value in either: - Extended frame format (29 bits).." line.long 0x24 "CAN_PL2_PLMASK_LO,The CAN_PL2_PLMASK_LO register has two functions: - It contains the low order bits for the Payload Filter 2 used only as the upper limit value in a payload range detection. - When exact payload filtering criteria is selected." hexmask.long.byte 0x24 24.--31. 1. "DATA_BYTE_0,Payload Filter 2 low order bits / Payload Mask low order bits for Pretended Networking payload filtering corresponding to data byte 0." hexmask.long.byte 0x24 16.--23. 1. "DATA_BYTE_1,Payload Filter 2 low order bits / Payload Mask low order bits for Pretended Networking payload filtering corresponding to data byte 1." newline hexmask.long.byte 0x24 8.--15. 1. "DATA_BYTE_2,Payload Filter 2 low order bits / Payload Mask low order bits for Pretended Networking payload filtering corresponding to data byte 2." hexmask.long.byte 0x24 0.--7. 1. "DATA_BYTE_3,Payload Filter 2 low order bits / Payload Mask low order bits for Pretended Networking payload filtering corresponding to data byte 3." line.long 0x28 "CAN_PL2_PLMASK_HI,The CAN_PL2_PLMASK_HI register has two functions: - It contains the high order bits for the Payload Filter 2 used only as the upper limit value in a payload range detection. - When exact payload filtering criteria is selected." hexmask.long.byte 0x28 24.--31. 1. "DATA_BYTE_4,Payload Filter 2 high order bits / Payload Mask high order bits for Pretended Networking payload filtering corresponding to data byte 4." hexmask.long.byte 0x28 16.--23. 1. "DATA_BYTE_5,Payload Filter 2 high order bits / Payload Mask high order bits for Pretended Networking payload filtering corresponding to data byte 5." newline hexmask.long.byte 0x28 8.--15. 1. "DATA_BYTE_6,Payload Filter 2 high order bits / Payload Mask high order bits for Pretended Networking payload filtering corresponding to data byte 6." hexmask.long.byte 0x28 0.--7. 1. "DATA_BYTE_7,Payload Filter 2 high order bits / Payload Mask high order bits for Pretended Networking payload filtering corresponding to data byte 7." rgroup.long 0xB40++0x37 line.long 0x0 "CAN_WMB0_CS,Wake Up Message Buffer Register for C/S 0. Each of the four WMBs contains a register to store the Control Status (C/S) information (IDE. RTR. and DLC fields) of an incoming Rx message. NOTE: The C/S registers are located at 0x840 for WMB 0." bitfld.long 0x0 22. "SRR,Substitute Remote Request - Can be received either recessive or dominant." "0,1" newline bitfld.long 0x0 21. "IDE,ID Extended Bit - Identifies whether the frame format is standard or extended: - 1: Frame format is extended. - 0: Frame format is standard." "Frame format is standard,Frame format is extended" bitfld.long 0x0 20. "RTR,Remote Transmission Request Bit - Identifies whether the frame is remote or not: - 1: Frame is a remote frame. - 0: Frame is data frame (not remote)." "Frame is data frame,Frame is a remote frame" newline hexmask.long.byte 0x0 16.--19. 1. "DLC,Length of Data in Bytes - Length (in bytes) of the Rx data received when FlexCAN is in Pretended Networking mode. DLC is written by the FlexCAN module copied from the DLC (Data Length Code) field of the received frame. The DLC field indicates which.." line.long 0x4 "CAN_WMB0_ID,Wake Up Message Buffer Register for ID 0.Each of the four WMBs contains a register to store the ID information of an incoming Rx message. NOTE: The ID registers are located at 0x844 for WMB 0 . 0x854 for WMB1. 0x864 for WMB2. and 0x874 for.." hexmask.long 0x4 0.--28. 1. "ID,Received ID under Pretended Networking Mode - Stores the received ID as either: - The 29 bits of the extended frame format (considering the ID[28:0] field) or - The 11 bits of the standard frame format (considering the ID[28:18] field only. The.." line.long 0x8 "CAN_WMB0_D03,Wake Up Message Buffer Register for Data 0-3 0.Each of the four WMBs contains a register to store the data bytes O to 3 of the payload information of an incoming Rx message. This register's content is cleared when the incoming matched.." hexmask.long.byte 0x8 24.--31. 1. "DATA_BYTE_0,Received payload corresponding to data byte 0 under Pretended Networking mode." hexmask.long.byte 0x8 16.--23. 1. "DATA_BYTE_1,Received payload corresponding to data byte 1 under Pretended Networking mode." newline hexmask.long.byte 0x8 8.--15. 1. "DATA_BYTE_2,Received payload corresponding to data byte 2 under Pretended Networking mode." hexmask.long.byte 0x8 0.--7. 1. "DATA_BYTE_3,Received payload corresponding to data byte 3 under Pretended Networking mode." line.long 0xC "CAN_WMB0_D47,Wake Up Message Buffer Register for Data 4-7 0. Each of the four WMBs contains a register to store the data bytes 4 to 7 of the payload information of an incoming Rx message. This register's content is cleared when the incoming matched.." hexmask.long.byte 0xC 24.--31. 1. "DATA_BYTE_4,Received payload corresponding to data byte 4 under Pretended Networking mode." hexmask.long.byte 0xC 16.--23. 1. "DATA_BYTE_5,Received payload corresponding to data byte 5 under Pretended Networking mode." newline hexmask.long.byte 0xC 8.--15. 1. "DATA_BYTE_6,Received payload corresponding to data byte 6 under Pretended Networking mode." hexmask.long.byte 0xC 0.--7. 1. "DATA_BYTE_7,Received payload corresponding to data byte 7 under Pretended Networking mode." line.long 0x10 "CAN_WMB1_CS,Wake Up Message Buffer Register for C/S 1. Each of the four WMBs contains a register to store the Control Status (C/S) information (IDE. RTR. and DLC fields) of an incoming Rx message. NOTE: The C/S registers are located at 0x840 for WMB 0." bitfld.long 0x10 22. "SRR,Substitute Remote Request - Can be received either recessive or dominant." "0,1" newline bitfld.long 0x10 21. "IDE,ID Extended Bit - Identifies whether the frame format is standard or extended: - 1: Frame format is extended. - 0: Frame format is standard." "Frame format is standard,Frame format is extended" bitfld.long 0x10 20. "RTR,Remote Transmission Request Bit - Identifies whether the frame is remote or not: - 1: Frame is a remote frame. - 0: Frame is data frame (not remote)." "Frame is data frame,Frame is a remote frame" newline hexmask.long.byte 0x10 16.--19. 1. "DLC,Length of Data in Bytes - Length (in bytes) of the Rx data received when FlexCAN is in Pretended Networking mode. DLC is written by the FlexCAN module copied from the DLC (Data Length Code) field of the received frame. The DLC field indicates which.." line.long 0x14 "CAN_WMB1_ID,Wake Up Message Buffer Register for ID 1.Each of the four WMBs contains a register to store the ID information of an incoming Rx message. NOTE: The ID registers are located at 0x844 for WMB 0. 0x854 for WMB1. 0x864 for WMB2. and 0x874 for.." hexmask.long 0x14 0.--28. 1. "ID,Received ID under Pretended Networking Mode - Stores the received ID as either: - The 29 bits of the extended frame format (considering the ID[28:0] field) or - The 11 bits of the standard frame format (considering the ID[28:18] field only. The.." line.long 0x18 "CAN_WMB1_D03,Wake Up Message Buffer Register for Data 0-3 1. Each of the four WMBs contains a register to store the data bytes 4 to 7 of the payload information of an incoming Rx message. This register's content is cleared when the incoming matched.." hexmask.long.byte 0x18 24.--31. 1. "Data_byte_0,Data_byte_0" hexmask.long.byte 0x18 16.--23. 1. "Data_byte_1,Data_byte_1" newline hexmask.long.byte 0x18 8.--15. 1. "Data_byte_2,Data_byte_2" hexmask.long.byte 0x18 0.--7. 1. "Data_byte_3,Data_byte_3" line.long 0x1C "CAN_WMB1_D47,Wake Up Message Buffer Register for Data 4-7 1.Each of the four WMBs contains a register to store the data bytes 4 to 7 of the payload information of an incoming Rx message. This register's content is cleared when the incoming matched.." hexmask.long.byte 0x1C 24.--31. 1. "DATA_BYTE_4,Received payload corresponding to data byte 4 under Pretended Networking mode." hexmask.long.byte 0x1C 16.--23. 1. "DATA_BYTE_5,Received payload corresponding to data byte 5 under Pretended Networking mode." newline hexmask.long.byte 0x1C 8.--15. 1. "DATA_BYTE_6,Received payload corresponding to data byte 6 under Pretended Networking mode." hexmask.long.byte 0x1C 0.--7. 1. "DATA_BYTE_7,Received payload corresponding to data byte 7 under Pretended Networking mode." line.long 0x20 "CAN_WMB2_CS,Wake Up Message Buffer Register for C/S 2.Each of the four WMBs contains a register to store the Control Status (C/S) information (IDE. RTR. and DLC fields) of an incoming Rx message. NOTE: The C/S registers are located at 0x840 for WMB 0." bitfld.long 0x20 22. "SRR,Substitute Remote Request - Can be received either recessive or dominant." "0,1" newline bitfld.long 0x20 21. "IDE,ID Extended Bit - Identifies whether the frame format is standard or extended: - 1: Frame format is extended. - 0: Frame format is standard." "Frame format is standard,Frame format is extended" bitfld.long 0x20 20. "RTR,Remote Transmission Request Bit - Identifies whether the frame is remote or not: - 1: Frame is a remote frame. - 0: Frame is data frame (not remote)." "Frame is data frame,Frame is a remote frame" newline hexmask.long.byte 0x20 16.--19. 1. "DLC,Length of Data in Bytes - Length (in bytes) of the Rx data received when FlexCAN is in Pretended Networking mode. DLC is written by the FlexCAN module copied from the DLC (Data Length Code) field of the received frame. The DLC field indicates which.." line.long 0x24 "CAN_WMB2_ID,Wake Up Message Buffer Register for ID 2. Each of the four WMBs contains a register to store the ID information of an incoming Rx message. NOTE: The ID registers are located at 0x844 for WMB 0. 0x854 for WMB1. 0x864 for WMB2. and 0x874 for.." hexmask.long 0x24 0.--28. 1. "ID,Received ID under Pretended Networking Mode - Stores the received ID as either: - The 29 bits of the extended frame format (considering the ID[28:0] field) or - The 11 bits of the standard frame format (considering the ID[28:18] field only. The.." line.long 0x28 "CAN_WMB2_D03,Wake Up Message Buffer Register for Data 0-3 2.Each of the four WMBs contains a register to store the data bytes 4 to 7 of the payload information of an incoming Rx message. This register's content is cleared when the incoming matched.." hexmask.long.byte 0x28 24.--31. 1. "Data_byte_0,Data_byte_0" hexmask.long.byte 0x28 16.--23. 1. "Data_byte_1,Data_byte_1" newline hexmask.long.byte 0x28 8.--15. 1. "Data_byte_2,Data_byte_2" hexmask.long.byte 0x28 0.--7. 1. "Data_byte_3,Data_byte_3" line.long 0x2C "CAN_WMB2_D47,Wake Up Message Buffer Register for Data 4-7 2. Each of the four WMBs contains a register to store the data bytes 4 to 7 of the payload information of an incoming Rx message. This register's content is cleared when the incoming matched.." hexmask.long.byte 0x2C 24.--31. 1. "DATA_BYTE_4,Received payload corresponding to data byte 4 under Pretended Networking mode." hexmask.long.byte 0x2C 16.--23. 1. "DATA_BYTE_5,Received payload corresponding to data byte 5 under Pretended Networking mode." newline hexmask.long.byte 0x2C 8.--15. 1. "DATA_BYTE_6,Received payload corresponding to data byte 6 under Pretended Networking mode." hexmask.long.byte 0x2C 0.--7. 1. "DATA_BYTE_7,Received payload corresponding to data byte 7 under Pretended Networking mode." line.long 0x30 "CAN_WMB3_CS,Wake Up Message Buffer Register for C/S 3.Each of the four WMBs contains a register to store the Control Status (C/S) information (IDE. RTR. and DLC fields) of an incoming Rx message. NOTE: The C/S registers are located at 0x840 for WMB 0." bitfld.long 0x30 22. "SRR,Substitute Remote Request - Can be received either recessive or dominant." "0,1" newline bitfld.long 0x30 21. "IDE,ID Extended Bit - Identifies whether the frame format is standard or extended: - 1: Frame format is extended. - 0: Frame format is standard." "Frame format is standard,Frame format is extended" bitfld.long 0x30 20. "RTR,Remote Transmission Request Bit - Identifies whether the frame is remote or not: - 1: Frame is a remote frame. - 0: Frame is data frame (not remote)." "Frame is data frame,Frame is a remote frame" newline hexmask.long.byte 0x30 16.--19. 1. "DLC,Length of Data in Bytes - Length (in bytes) of the Rx data received when FlexCAN is in Pretended Networking mode. DLC is written by the FlexCAN module copied from the DLC (Data Length Code) field of the received frame. The DLC field indicates which.." line.long 0x34 "CAN_WMB3_ID,Wake Up Message Buffer Register for ID 3. Each of the four WMBs contains a register to store the ID information of an incoming Rx message. NOTE: The ID registers are located at 0x844 for WMB 0. 0x854 for WMB1. 0x864 for WMB2. and 0x874 for.." hexmask.long 0x34 0.--28. 1. "ID,Received ID under Pretended Networking Mode - Stores the received ID as either: - The 29 bits of the extended frame format (considering the ID[28:0] field) or - The 11 bits of the standard frame format (considering the ID[28:18] field only. The.." repeat 2. (list 0x3 0x2F )(list 0x0 0x4 ) rgroup.long ($2+0xB78)++0x3 line.long 0x0 "CAN_WMB3_D$1,Wake Up Message Buffer Register for Data 0-3 3. Each of the four WMBs contains a register to store the data bytes 4 to 7 of the payload information of an incoming Rx message. This register's content is cleared when the incoming matched.." hexmask.long.byte 0x0 24.--31. 1. "Data_byte_0,Data_byte_0" hexmask.long.byte 0x0 16.--23. 1. "Data_byte_1,Data_byte_1" newline hexmask.long.byte 0x0 8.--15. 1. "Data_byte_2,Data_byte_2" hexmask.long.byte 0x0 0.--7. 1. "Data_byte_3,Data_byte_3" repeat.end group.long 0xC00++0x7 line.long 0x0 "CAN_FDCTRL,The CAN_FDCTRL register contains control bits for CAN FD operation. CAN_FDCTRL also defines the data size of message buffers allocated in different partitions of RAM (memory blocks). When an 8-byte payload is selected: - Block RO allocates.." bitfld.long 0x0 31. "FDRATE,Bit Rate Switch Enable - Enables the effect of the Bit Rate Switch (BRS bit) during the data phase of Tx messages: - 1: Transmit a frame with bit rate switching if the BRS bit in the Tx MB is recessive. - 0: Transmit a frame in nominal rate. The.." "Transmit a frame in nominal rate,Transmit a frame with bit rate switching if the.." newline bitfld.long 0x0 25.--26. "MBDSR3,Message Buffer Data Size for Region 3 - Selects the data size for region R3 of message buffers allocated in RAM: - 00: Selects 8 bytes per message buffer. - 01: Selects 16 bytes per message buffer. - 10: Selects 32 bytes per message buffer. - 11:.." "Selects 8 bytes per message buffer,Selects 16 bytes per message buffer,?,Selects the data size for region R3 of message.." newline bitfld.long 0x0 22.--23. "MBDSR2,Message Buffer Data Size for Region 2 - Selects the data size for region R2 of message buffers allocated in RAM: - 00: Selects 8 bytes per message buffer. - 01: Selects 16 bytes per message buffer. - 10: Selects 32 bytes per message buffer. - 11:.." "Selects 8 bytes per message buffer,Selects 16 bytes per message buffer,Selects the data size for region R2 of message..,?" newline bitfld.long 0x0 19.--20. "MBDSR1,Message Buffer Data Size for Region 1 - Selects the data size for region R1 of message buffers allocated in RAM: - 00: Selects 8 bytes per message buffer. - 01: Selects 16 bytes per message buffer. - 10: Selects 32 bytes per message buffer. - 11:.." "Selects 8 bytes per message buffer,Selects 16 bytes per message buffer,?,?" newline bitfld.long 0x0 16.--17. "MBDSR0,Message Buffer Data Size for Region O - Selects the data size for region RO of message buffers allocated in RAM: - 00: Selects 8 bytes per message buffer. - 01: Selects 16 bytes per message buffer. - 10: Selects 32 bytes per message buffer. - 11:.." "Selects 8 bytes per message buffer,Selects 16 bytes per message buffer,?,?" bitfld.long 0x0 15. "TDCEN,Transceiver Delay Compensation Enable - Enables or disables the TDC feature: - 1: TDC is enabled. - 0: TDC is disabled. TDCEN can be written in Freeze mode only. Note: TDC must be disabled when Loop-Back mode is enabled (see CAN_CTRL1.LPB). Note:.." "TDC is disabled,TDC is enabled" newline bitfld.long 0x0 14. "TDCFAIL,Transceiver Delay Compensation Fail TDCFAIL indicates when the Transceiver Delay Compensation (TDC) mechanism is out of range unable to compensate the transceiver's loop delay and successfully compare the delayed received bits to the.." "Measured loop delay is in range,Measured loop delay is out of range" newline hexmask.long.byte 0x0 8.--12. 1. "TDCOFF,Transceiver Delay Compensation Offset TDCOFF contains the offset value to be added to the measured transceiver's loop delay in order to define the position of the delayed comparison point when bit rate switching is active. TDCOFF can be written in.." newline hexmask.long.byte 0x0 0.--5. 1. "TDCVAL,Transceiver Delay Compensation Value TDCVAL contains the value of the transceiver loop delay measured from the transmitted EDL to RO transition edge to the respective received one added to the TDCOFF value. This value is an integer multiple of the.." line.long 0x4 "CAN_FDCBT,The CAN_FDCBT register stores the CAN bit timing variables used in the data phase of CAN FD messages when CAN_FDCTRL.FDRATE is set. compatible with CAN FD specification. FPRESDIV. FPROPSEG. FPSEG1. FPSEG2. and FRJW are used to define the time.." hexmask.long.word 0x4 20.--29. 1. "FPRESDIV,Fast Prescaler Division Factor FPRESDIV defines the ratio between the PE clock frequency and the Serial Clock (Sclock) frequency in the data bit rate portion of a CAN FD message with the BRS bit set. The Sclock period defines the time quantum of.." newline bitfld.long 0x4 16.--18. "FRJW,Fast Resync Jump Width FRJW defines the maximum number of time quanta that a bit time can be changed by one re-synchronization in the data bit rate portion of a CAN FD message with the BRS bit set. Resync Jump Width = FSJW + 1. One time quantum is.." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x4 10.--14. 1. "FPROPSEG,Fast Propagation Segment FPROPSEG defines the length of the Propagation Segment in the bit time in the data bit rate portion of a CAN FD message with the BRS bit set. Propagation Segment Time = FPROPSEG x Time-Quanta Time-Quantum = one Sclock.." newline bitfld.long 0x4 5.--7. "FPSEG1,Fast Phase Segment 1 FPSEG1 defines the length of Phase Segment 1 in the bit time in the data bit rate portion of a CAN FD message with the BRS bit set. Phase Segment 1 = (FPSEG1 + 1) x Time-Quanta Time-Quantum = one Sclock period FPSEG1 can be.." "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 0.--2. "FPSEG2,Fast Phase Segment 2 FPSEG2 defines the length of Phase Segment 2 in the data bit rate portion of a CAN FD message with the BRS bit set. Phase Segment 2 = (FPSEG2 + 1) x Time-Quanta Time-Quantum = one Sclock period FPSEG2 can be written only in.." "0,1,2,3,4,5,6,7" rgroup.long 0xC08++0x3 line.long 0x0 "CAN_FDCRC,The CAN_CRCR register provides information about the CRC of transmitted messages for non-FD messages. CAN_CRCR only reports the 15 low order bits of CRC calculations for messages in CAN FD format that require either 17 or 21 bits. For CAN FD.." hexmask.long.byte 0x0 24.--30. 1. "FD_MBCRC,CRC Mailbox - Indicates the number of the mailbox corresponding to the value in the CAN CRCR.TXCRC field." newline hexmask.long.tbyte 0x0 0.--20. 1. "FD_TXCRC,Transmitted CRC Value - Indicates the CRC value of the last transmitted message for non-FD frames. For CAN FD frames the CRC value is reported in CAN_FDCRC." tree.end repeat.end repeat 12. (increment 9. 1.) (list ad:0x30740000 ad:0x30750000 ad:0x30760000 ad:0x30770000 ad:0x30780000 ad:0x30790000 ad:0x307A0000 ad:0x307B0000 ad:0x307C0000 ad:0x307D0000 ad:0x307E0000 ad:0x307F0000) tree "CANFD$1" base $2 group.long 0x0++0xB line.long 0x0 "CAN_MCR,CAN_MCR defines global system configurations. such as the module operation modes and the maximum message buffer configuration." bitfld.long 0x0 31. "MDIS,Module Disable - Disables or enables the FlexCAN module: - 1: Disable the FlexCAN module. - 0: Enable the FlexCAN module. When disabled the FlexCAN disables the clocks to the PE and CHI submodules. MDIS is not affected by soft reset." "Enable the FlexCAN module,Disable the FlexCAN module" bitfld.long 0x0 30. "FRZ,Freeze Enable: - 1: Enabled to enter Freeze mode. - 0: Not enabled to enter Freeze mode. The FRZ bit specifies the FlexCAN behavior when CAN_MCR.HALT is set or when Debug mode is requested at chip level. When FRZ is asserted the FlexCAN is enabled.." "Not enabled to enter Freeze mode,Enabled to enter Freeze mode" newline bitfld.long 0x0 29. "RFEN,Legacy Rx FIFO Enable - Enables or disables the Legacy Rx FIFO feature: - 1: Enable Legacy Rx FIFO. - 0: Disable Legacy Rx FIFO. When RFEN is set MBs 0-5 cannot be used for normal reception and transmission because the corresponding memory region.." "Disable Legacy Rx FIFO,Enable Legacy Rx FIFO" bitfld.long 0x0 28. "HALT,Halt FlexCAN: - 1: Enter Freeze mode if the FRZ bit is asserted. - 0: No Freeze mode request. Assertion of HALT puts the FlexCAN module into Freeze mode. The CPU should clear HALT after initializing the message buffers and the control registers.." "No Freeze mode request,Enter Freeze mode if the FRZ bit is asserted" newline rbitfld.long 0x0 27. "NOTRDY,FlexCAN Not Ready: - 1: FlexCAN is either in Module Disable Doze Stop or Freeze mode. - 0: FlexCAN is either in Normal Listen-Only or Loop-Back mode. NOTRDY is a read-only bit that indicates that the FlexCAN is either in Module Disable Doze.." "FlexCAN is either in Normal,FlexCAN is either in Module Disable" bitfld.long 0x0 26. "WAKMSK,Wake Up Interrupt Mask - Enables Wake Up interrupt generation under the Self Wake Up mechanism: - 1: Enable Wake Up interrupt. - 0: Disable Wake Up interrupt." "Disable Wake Up interrupt,Enable Wake Up interrupt" newline bitfld.long 0x0 25. "SOFTRST,Soft Reset: - 1: Reset the registers affected by soft reset. - 0: No reset request. When SOFTRST is asserted the FlexCAN resets its internal state machines and some of the memory-mapped registers. SOFTRST can be asserted directly by the CPU by.." "No reset request,Reset the registers affected by soft reset" rbitfld.long 0x0 24. "FRZACK,Freeze Mode Acknowledge: - 1: FlexCAN in Freeze mode prescaler stopped. - 0: FlexCAN not in Freeze mode prescaler running. FRZACK is a read-only bit that indicates that the FlexCAN is in Freeze mode and its prescaler is stopped. A Freeze mode.." "FlexCAN not in Freeze mode,FlexCAN in Freeze mode" newline bitfld.long 0x0 23. "SUPV,Supervisor Mode - Configures the FlexCAN to be either in Supervisor or User mode: - 1: FlexCAN is in Supervisor mode. Affected registers allow only Supervisor access. Unrestricted access behaves as though the access was done to an unimplemented.." "FlexCAN is in User mode,FlexCAN is in Supervisor mode" bitfld.long 0x0 22. "SLFWAK,Self Wake Up - Enables the Self Wake Up feature when the FlexCAN is in a low-power mode other than Module Disable: - 1: Enable FlexCAN Self Wake Up feature. - 0: Disable FlexCAN Self Wake Up feature. When the Self Wake Up feature is enabled the.." "Disable FlexCAN Self Wake Up feature,Enable FlexCAN Self Wake Up feature" newline bitfld.long 0x0 21. "WRNEN,Warning Interrupt Enable: - 1: TWRNINT and RWRNINT bits are set when the respective error counter transitions from less than 96 to greater than or equal to 96. - 0: TWRNINT and RWRNINT bits are zero independent of the values in the error counters." "TWRNINT and RWRNINT bits are zero,TWRNINT and RWRNINT bits are set when the.." rbitfld.long 0x0 20. "LPMACK,Low-Power Mode Acknowledge: - 1: FlexCAN is in a low-power mode. - 0: FlexCAN is not in a low-power mode. LPMACK is a read-only bit that indicates that the FlexCAN is in a low-power mode (Module Disable Doze or Stop). A low-power mode cannot be.." "FlexCAN is not in a low-power mode,FlexCAN is in a low-power mode" newline bitfld.long 0x0 19. "WAKSRC,Wake Up Source - Controls whether the integrated low-pass filter is applied to protect the Rx CAN input from spurious wakeup: - 1: FlexCAN uses the filtered Rx input to detect recessive-to- dominant edges on the CAN bus. - 0: FlexCAN uses the.." "FlexCAN uses the unfiltered Rx input to detect..,FlexCAN uses the filtered Rx input to detect.." bitfld.long 0x0 18. "DOZE,Doze Mode Enable - Controls whether the FlexCAN is allowed to enter low-power mode when Doze mode is requested at chip level: - 1: FlexCAN is enabled to enter low-power mode when Doze mode is requested. - 0: FlexCAN is not enabled to enter low-power.." "FlexCAN is not enabled to enter low-power mode..,FlexCAN is enabled to enter low-power mode when.." newline bitfld.long 0x0 17. "SRXDIS,Self Reception Disable: - 1: Disable self-reception. - 0: Enable self-reception. SRXDIS controls whether the FlexCAN is allowed to receive frames transmitted by itself. If SRXDIS is asserted frames transmitted by the FlexCAN are not stored in any.." "Enable self-reception,Disable self-reception" bitfld.long 0x0 16. "IRMQ,Individual Rx Masking And Queue Enable: - 1: Enable individual Rx masking and queue feature. - 0: Disable individual Rx masking and queue feature. For backward compatibility with legacy applications the reading of C/S word locks the MB even if it.." "Disable individual Rx masking and queue feature,Enable individual Rx masking and queue feature" newline bitfld.long 0x0 15. "DMA,DMA Enable: - 1: Enable DMA feature for Rx FIFO. - 0: Disable DMA feature for Rx FIFO. The DMA bit enables or disables the DMA feature. The DMA feature can only be used with the Legacy Rx FIFO or the Enhanced Rx FIFO; consequently either.." "Disable DMA feature for Rx FIFO,Enable DMA feature for Rx FIFO" bitfld.long 0x0 14. "PNET_EN,Pretended Networking Enable - Enables the Pretended Networking functionality: - 1: Enable Pretended Networking mode. - 0: Disable Pretended Networking mode. When Pretended Networking is enabled the PE submodule is kept operational in Doze mode.." "Disable Pretended Networking mode,Enable Pretended Networking mode" newline bitfld.long 0x0 13. "LPRIOEN,Local Priority Enable: - 1: Enable Local Priority. - 0: Disable Local Priority. The LPRIOEN bit is provided for backward compatibility with legacy applications. LPRIOEN controls whether the Local Priority feature is enabled or not. Local Priority.." "Disable Local Priority,Enable Local Priority" bitfld.long 0x0 12. "AEN,Abort Enable - Enables the Tx abort mechanism: - 1: Enable abort. - 0: Disable abort. The Tx abort mechanism ensures a safe procedure for aborting a pending transmission so that no frame is sent on the CAN bus without notification." "Disable abort,Enable abort" newline bitfld.long 0x0 11. "FDEN,CAN FD Operation Enable - Enables CAN with Flexible Data rate (CAN FD) operation: - 1: CAN FD is enabled. The FlexCAN is able to receive and transmit messages in both CAN FD and CAN 2.0 formats. - 0: CAN FD is disabled. The FlexCAN is able to.." "CAN FD is disabled,CAN FD is enabled" newline bitfld.long 0x0 8.--9. "IDAM,ID Acceptance Mode - Identifies the format of the Legacy Rx FIFO ID Filter Table elements: - 00: Format A- One full ID (standard and extended) per ID Filter Table element. - 01: Format B - Two full standard IDs or two partial 14-bit (standard and.." "Format A,Format B,?,?" newline hexmask.long.byte 0x0 0.--6. 1. "MAXMB,Number of the Last Message Buffer - Defines the number of the last message buffer that will take part in the matching and arbitration processes. The reset value (OxOF) is equivalent to a 16 message buffer configuration. MAXMB can be written only in.." line.long 0x4 "CAN_CTRL1,The CAN_CTRL1 register is defined for specific FlexCAN control features related to the CAN bus. such as bit-rate. programmable sampling point within an Rx bit. Loop-Back mode. Listen-Only mode. Bus Off recovery behavior. and interrupt enabling.." hexmask.long.byte 0x4 24.--31. 1. "PRESDIV,Prescaler Division Factor - Defines the ratio between the PE clock frequency and the serial clock (Sclock) frequency. The Sclock period defines the time quantum of the CAN protocol. For the reset value the Sclock frequency is equal to the PE.." bitfld.long 0x4 22.--23. "RJW,Resync Jump Width - Defines the maximum number of time quanta that a bit time can be changed by one re-synchronization. One time quantum is equal to the Sclock period. The valid programmable values for RJW are 0-3. RJW can be written only in Freeze.." "0,1,2,3" newline bitfld.long 0x4 19.--21. "PSEG1,Phase Segment 1 - Defines the length of phase segment 1 in the bit time. The valid programmable values are 0-7. PSEG1 can be written only in Freeze mode because it is blocked by hardware in other modes. Phase Buffer Segment 1 = (PSEG1 + 1) x.." "?,Defines the length of phase segment 1 in the bit..,?,?,?,?,?,?" bitfld.long 0x4 16.--18. "PSEG2,Phase Segment 2 - Defines the length of phase segment 2 in the bit time. The valid programmable values are 1-7. PSEG2 can be written only in Freeze mode because it is blocked by hardware in other modes. Phase Buffer Segment 2 = (PSEG2 + 1) x.." "?,?,Defines the length of phase segment 2 in the..,?,?,?,?,?" newline bitfld.long 0x4 15. "BOFFMSK,Bus Off Interrupt Mask - Provides a mask for the Bus Off interrupt (CAN_ESR1.BOFFINT): - 1: Bus Off interrupt enabled. - 0: Bus Off interrupt disabled." "Bus Off interrupt disabled,Bus Off interrupt enabled" bitfld.long 0x4 14. "ERRMSK,Error Interrupt Mask - Provides a mask for the Error interrupt (CAN_ESR 1.ERRINT). - 1: Error interrupt enabled. - 0: Error interrupt disabled." "Error interrupt disabled,Error interrupt enabled" newline bitfld.long 0x4 13. "CLKSRC,CAN Engine Clock Source - Selects the clock source to the PE submodule to be either the peripheral clock or the oscillator clock: - 1: The PE clock source is the peripheral clock. - 0: The PE clock source is the oscillator clock. Under this.." "The PE clock source is the oscillator clock,The PE clock source is the peripheral clock" bitfld.long 0x4 12. "LPB,Loop-Back Mode - Configures the FlexCAN to operate in Loop-Back mode: - 1: Loop-Back enabled. - 0: Loop-Back disabled. In Loop-Back mode the FlexCAN performs an internal loop back that can be used for self-test operation. The bit stream output of.." "Loop-Back disabled,Loop-Back enabled" newline bitfld.long 0x4 11. "TWRNMSK,Tx Warning Interrupt Mask - Provides a mask for the Tx Warning interrupt (CAN-ESR1.TWRNINT): - 1: Tx Warning interrupt enabled. - 0: Tx Warning interrupt disabled. TWRNMSK is read as zero when CAN_MCR.WRNEN is negated. TWRNMSK can be written.." "Tx Warning interrupt disabled,Tx Warning interrupt enabled" bitfld.long 0x4 10. "RWRNMSK,Rx Warning Interrupt Mask - Provides a mask for the Rx Warning interrupt (CAN_ESR1.RWRNINT) - 1: Rx Warning interrupt enabled. - 0: Rx Warning interrupt disabled. RWRNMSK is read as zero when CAN_MCR.WRNEN is negated. RWRNMSK can be written only.." "Rx Warning interrupt disabled,Rx Warning interrupt enabled" newline bitfld.long 0x4 7. "SMP,CAN Bit Sampling - Defines the sampling mode of CAN bits at the Rx input: - 0: One sample is used to determine the bit value. - 1: Three samples are used to determine the value of the received bit:the regular sample (sample point) and two.." "One sample is used to determine the bit value,Three samples are used to determine the value of.." newline bitfld.long 0x4 6. "BOFFREC,Bus Off Recovery - Defines how the FlexCAN recovers from Bus Off state: - 0: Automatic recovering from Bus Off state enabled. - 1: Automatic recovering from Bus Off state disabled. If BOFFREC is negated automatic recovering from Bus Off state.." "Automatic recovering from Bus Off state enabled,Automatic recovering from Bus Off state disabled" bitfld.long 0x4 5. "TSYN,Timer Sync - Enables a mechanism that resets the free-running timer each time a message is received in message buffer 0: - 1: Timer Sync feature enabled. - 0: Timer Sync feature disabled. The Timer Sync feature provides a means to synchronize.." "Timer Sync feature disabled,Timer Sync feature enabled" newline bitfld.long 0x4 4. "LBUF,Lowest Buffer Transmitted First - Defines the ordering mechanism for message buffer transmission: - 1: Lowest number buffer is transmitted first. - 0: Buffer with highest priority is transmitted first. When LBUF is asserted the CAN_MCR.LPRIOEN bit.." "Buffer with highest priority is transmitted first,Lowest number buffer is transmitted first" bitfld.long 0x4 3. "LOM,Listen-Only Mode - Configures the FlexCAN to operate in Listen-Only mode: - 1: FlexCAN module operates in Listen-Only mode. - 0: Listen-Only mode is deactivated. In Listen-Only Mode mode transmission is disabled all error counters described in.." "Listen-Only mode is deactivated,FlexCAN module operates in Listen-Only mode" newline bitfld.long 0x4 0.--2. "PROPSEG,Propagation Segment - Defines the length of the propagation segment in the bit time. The valid programmable values are 0-7. PROPSEG can be written only in Freeze mode because it is blocked by hardware in other modes. Propagation segment time =.." "0,1,2,3,4,5,6,7" line.long 0x8 "CAN_TIMER,The CAN_TIMER register represents a 16-bit free-running counter that can be read and written by the CPU. The timer starts from 0x0 after reset. counts linearly to 0xFFFF. and wraps around. When CAN_CTRL2.TIMER_SRC is asserted. the timer is.." hexmask.long.word 0x8 0.--15. 1. "TIMER,Timer Value - Contains the free-running counter value." group.long 0x10++0x27 line.long 0x0 "CAN_RXMGMASK,The CAN_RXMGMASK register is located in RAM. CAN_RXMGMASK is provided for legacy application support: - When the CAN_MCR.IRMQ bit is negated. CAN_RXMGMASK is always in effect (the bits in the MG field will mask the mailbox filter bits). -.." hexmask.long 0x0 0.--31. 1. "MG,Rx Mailboxes Global Mask Bits: - 0: The corresponding bit in the filter is 'don't care'. - 1: The corresponding bit in the filter is checked. The MG bits mask the mailbox filter bits. Note that the alignment with the ID word of the mailbox is not.." line.long 0x4 "CAN_RX14MASK,The CAN_RX14MASK register is located in RAM. CAN_RX14MASK is provided for legacy application support. When the CAN_MCR.IRMQ bit is asserted. CAN_RX14MASK has no effect. CAN_RX14MASK is used to mask the filter fields of message buffer 14." hexmask.long 0x4 0.--31. 1. "RX14M,Rx Buffer 14 Mask Bits: - 0: The corresponding bit in the filter is 'don't care'. - 1: The corresponding bit in the filter is checked. Each mask bit masks the corresponding mailbox 14 filter field in the same way that CAN_RXMGMASK masks other.." line.long 0x8 "CAN_RX15MASK,The CAN_RX15MASK register is located in RAM. CAN_RX15MASK is provided for legacy application support. When the CAN_MCR.IRMQ bit is asserted. CAN_RX15MASK has no effect. CAN_RX15MASK is used to mask the filter fields of message buffer 15." hexmask.long 0x8 0.--31. 1. "RX15M,Rx Buffer 15 Mask Bits: - 0: The corresponding bit in the filter is 'don't care'. - 1: The corresponding bit in the filter is checked. Each mask bit masks the corresponding mailbox 15 filter field in the same way that CAN_RXMGMASK masks other.." line.long 0xC "CAN_ECR,The CAN_ECR register has four 8-bit fields reflecting the value of the FlexCAN error counters: - Transmit Error Counter (TXERRCNT field) - Receive Error Counter (RXERRCNT field) - Transmit Error Counter for errors detected in the Data Phase of.." hexmask.long.byte 0xC 24.--31. 1. "RXERRCNT_FAST,Receive Error Counter for Fast Bits - Receive error counter for errors detected in the Data Phase of received CAN FD messages with the BRS bit set. The RXERRCNT_FAST counter is read-only except in Freeze mode in which the CPU can write an.." hexmask.long.byte 0xC 16.--23. 1. "TXERRCNT_FAST,Transmit Error Counter for Fast Bits - Transmit error counter for errors detected in the Data Phase of transmitted CAN FD messages with the BRS bit set. The TXERRCNT_FAST counter is read-only except in Freeze mode in which the CPU can.." newline hexmask.long.byte 0xC 8.--15. 1. "RXERRCNT,Receive Error Counter - Receive error counter for all errors detected in received messages. The RXERRCNT counter is read-only except in Freeze mode in which it can be written by the CPU." hexmask.long.byte 0xC 0.--7. 1. "TXERRCNT,Transmit Error Counter - Transmit error counter for all errors detected in transmitted messages. The TXERRCNT counter is read-only except in Freeze mode in which it can be written by the CPU." line.long 0x10 "CAN_ESR1,Error and Status 1 Register. The CAN_ESR1 register reports various error conditions detected in the reception and transmission of a CAN frame. some general status of the device. and is the source of some interrupts to the CPU." rbitfld.long 0x10 31. "BIT1ERR_FAST,Bit1 Error in the Data Phase of CAN FD Frames with the BRS Bit Set BIT1ERR_FAST indicates when an inconsistency occurs between the transmitted and the received bitin the Data Phase of CAN FD frames with the BRS bit set: - 1: At least one.." "No such occurrence,At least one bit sent as recessive is received.." rbitfld.long 0x10 30. "BIT0ERR_FAST,Bit0 Error in the Data Phase of CAN FD Frames with the BRS Bit Set BIT0ERR_FAST indicates when an inconsistency occurs between the transmitted and the received bit in the Data Phase of CAN FD frames with the BRS bit set: - 1: At least one.." "No such occurrence,At least one bit sent as dominant is received as.." newline rbitfld.long 0x10 28. "CRCERR_FAST,Cyclic Redundancy Check Error in the CRC field of CAN FD Frames with the BRS Bit Set CRCERR_FAST indicates that a CRC error has been detected by the receivernode in the CRC field of CAN FD frames with the BRS bit set; that is the.." "No such occurrence,A CRC error occurred since last read of this.." newline rbitfld.long 0x10 27. "FRMERR_FAST,From Error in the Data Phase of CAN FD Frames with the BRS Bit Set FRMERR_FAST indicates that a form error has been detected by the receiver node in the Data Phase of CAN FD frames with the BRS bit set; that is a fixed-form bit field.." "No such occurrence,A form error occurred since last read of this.." rbitfld.long 0x10 26. "STFERR_FAST,Stuffing Error in the Data Phase of CAN FD Frames with the BRS Bit Set STFERR_FAST indicates that a stuffing error has been detected in the Data Phase of CAN FD frames with the BRS bit set: - 1: A stuffing error occurred since last read of.." "No such occurrence,A stuffing error occurred since last read of.." newline bitfld.long 0x10 21. "ERROVR,Error Overrun - Indicates that an error condition occurred when any error flag is already set: - 1: Overrun has occurred. - 0: Overrun has not occurred. ERROVR is cleared by writing 1 to it." "Overrun has not occurred,Overrun has occurred" newline bitfld.long 0x10 20. "ERRINT_FAST,Error Interrupt for Errors Detected in the Data Phase of CAN FD Frames with the BRS Bit Set: - 1: Indicates setting of any error bit detected in the Data Phase of CAN FD frames with the BRS bit set. - 0: No such occurrence." "No such occurrence,Indicates setting of any error bit detected in.." bitfld.long 0x10 19. "BOFFDONEINT,Bus Off Done Interrupt: - 1: FlexCAN module has completed Bus Off process. - 0: No such occurrence." "No such occurrence,FlexCAN module has completed Bus Off process" newline rbitfld.long 0x10 18. "SYNCH,CAN Synchronization Status: - 1: FlexCAN is synchronized to the CAN bus. - 0: FlexCAN is not synchronized to the CAN bus. SYNCH is a read-only flag that indicates whether the FlexCAN is synchronized to the CAN bus and able to participate in the.." "FlexCAN is not synchronized to the CAN bus,FlexCAN is synchronized to the CAN bus" bitfld.long 0x10 17. "TWRNINT,Tx Warning Interrupt Flag: - 1: The Tx error counter transitioned from less than 96 to greater than or equal to 96. - 0: No such occurrence." "No such occurrence,The Tx error counter transitioned from less than.." newline bitfld.long 0x10 16. "RWRNINT,Rx Warning Interrupt Flag: - 1: The Rx error counter transitioned from less than 96 to greater than or equal to 96. - 0: No such occurrence." "No such occurrence,The Rx error counter transitioned from less than.." rbitfld.long 0x10 15. "BIT1ERR,Bit1 Error - Indicates when an inconsistency occurs between the transmitted and the received bit in a non-CAN FD message or in the arbitration or Data Phase of a CAN FD message: - 1: At least one bit sent as recessive is received as dominant. -.." "No such occurrence,At least one bit sent as recessive is received.." newline rbitfld.long 0x10 14. "BIT0ERR,Bit0 Error - Indicates when an inconsistency occurs between the transmitted and the received bit in a non-CAN FD message or in the arbitration or Data Phase of a CAN FD message: - 1: At least one bit sent as dominant is received asrecessive. -.." "No such occurrence,At least one bit sent as dominant is received.." rbitfld.long 0x10 13. "ACKERR,Acknowledge Error - Indicates that an Acknowledge error was detected by the transmitter node (that is a dominant bit was detected during the ACK SLOT): - 1: An ACK error occurred since last read of this register. - 0: No such occurrence. ACKERR.." "No such occurrence,An ACK error occurred since last read of this.." newline rbitfld.long 0x10 12. "CRCERR,Cyclic Redundancy Check Error - Indicates that a CRC error was detected by the receiver node either in a non-FD message or in the arbitration or Data Phase of a frame in CAN FD format (that is the calculated CRC is different from the received.." "No such occurrence,A CRC error occurred since last read of this.." rbitfld.long 0x10 11. "FRMERR,Form Error - Indicates that a form error was detected by the receiver node in a non-FD message or in a CAN FD message arbitration or Data Phase (that is a fixed-form bit field contains at least one illegal bit): - 1: A form error occurred since.." "No such occurrence,A form error occurred since last read of this.." newline rbitfld.long 0x10 10. "STFERR,Stuffing Error - Indicates that a stuffing error was detected by the receiver node in a non-FD message or in a CAN FD message arbitration or Data Phase: - 1: A stuffing error occurred since last read of this register. - 0: No such occurrence." "No such occurrence,A stuffing error occurred since last read of.." rbitfld.long 0x10 9. "TXWRN,TX Error Warning - Indicates when repetitive errors are occurring during message transmission: - 1: TXERRCNT is greater than or equal to 96. - 0: No such occurrence. TXWRN is affected by the value of CAN_ECR.TXERRCNT only. TXWRN is not updated.." "No such occurrence,TXERRCNT is greater than or equal to 96" newline rbitfld.long 0x10 8. "RXWRN,Rx Error Warning - Indicates when repetitive errors are occurring during message reception: - 1: RXERRCNT is greater than or equal to 96. - 0: No such occurrence. RXWRN is affected by the value of CAN_ECR.RXERRCNT only. RXWRN is not updated during.." "No such occurrence,RXERRCNT is greater than or equal to 96" rbitfld.long 0x10 7. "IDLE,IDLE - Indicates when the CAN bus is in the IDLE state: - 1: CAN bus is now IDLE. - 0: No such occurrence." "No such occurrence,CAN bus is now IDLE" newline rbitfld.long 0x10 6. "TX,FlexCAN in Transmission - Indicates if the FlexCAN is transmitting a message: - 1: FlexCAN is transmitting a message. - 0: FlexCAN is not transmitting a message." "FlexCAN is not transmitting a message,FlexCAN is transmitting a message" rbitfld.long 0x10 4.--5. "FLTCONF,Fault Confinement State - Indicates the fault confinement state of the FlexCAN module: - 00: Error Active - 01: Error Passive - 1x: Bus Off If CAN_CTRL1.LOM is asserted after a delay that depends on the CAN bit timing the FLTCONF field will.." "Error Active,Error Passive,?,?" newline rbitfld.long 0x10 3. "RX,FlexCAN in Reception - Indicates if the FlexCAN is receiving a message: - 1: FlexCAN is receiving a message. - 0: FlexCAN is not receiving a message." "FlexCAN is not receiving a message,FlexCAN is receiving a message" bitfld.long 0x10 2. "BOFFINT,Bus Off Interrupt: - 1: FlexCAN module entered Bus Off state. - 0: No such occurrence. BOFFINT is set when the FlexCAN enters the Bus Off state. If the corresponding mask bit (CAN-CTRL1.BOFFMSK) is set an interrupt is generated to the CPU." "No such occurrence,FlexCAN module entered Bus Off state" newline bitfld.long 0x10 1. "ERRINT,Error Interrupt: - 1: Indicates setting of any error bit in CAN-ESR1. - 0: No such occurrence. ERRINT indicates that at least one of the error bits (BIT1ERR BITOERR ACKERR CRCERR FRMERR or STFERR) is set. If the corresponding mask bit.." "No such occurrence,Indicates setting of any error bit in CAN-ESR1" bitfld.long 0x10 0. "WAKINT,Wake Up Interrupt - Applies when the FlexCAN is in low-power mode under Self Wake Up mechanism either Doze mode or Stop mode: - 1: Indicates a recessive-to-dominant transition was received on the CAN bus. - 0: No such occurrence. When a.." "No such occurrence,Indicates a recessive-to-dominant transition was.." line.long 0x14 "CAN_IMASK2,Interrupt Masks 2 Register. The CAN_IMASK2 register allows any number of the 32 message buffer interrupts to be enabled or disabled for MB63 to MB32. CAN_IMASK2 contains one interrupt mask bit per buffer. enabling the CPU to determine which.." hexmask.long 0x14 0.--31. 1. "BUF63TO32M,Buffer MB i Mask Each bit enables or disables the corresponding FlexCAN Message Buffer Interrupt for MB63 to MB32: - 1: The corresponding buffer interrupt is enabled. - 0: The corresponding buffer interrupt is disabled." line.long 0x18 "CAN_IMASK1,Interrupt Masks 1 Register. The CAN_IMASK1 register allows any number of the 32 message buffer interrupts to be enabled or disabled for MB31 to MB. CAN_IMASK1 contains one interrupt mask bit per buffer. enabling the CPU to determine which.." hexmask.long 0x18 0.--31. 1. "BUF31TO0M,Buffer MB i Mask Each bit enables or disables the corresponding FlexCAN Message Buffer Interrupt for MB31 to MBO: - 1: The corresponding buffer interrupt is enabled. - 0: The corresponding buffer interrupt is disabled." line.long 0x1C "CAN_IFLAG2,Interrupt Flags 2 Register. The CAN_IFLAG2 register defines the flags for the 32 message buffer interrupts for MB63 to MB32. CAN_IFLAG2 contains one interrupt flag bit per buffer. Each successful transmission or reception sets the respective.." hexmask.long 0x1C 0.--31. 1. "BUF63TO321,Buffer MB i Interrupt Each bit flags the corresponding FlexCAN Message Buffer Interrupt for MB63 to MB32: - 1: The corresponding buffer has successfully completed transmission or reception. - 0: The corresponding buffer has no occurrence of.." line.long 0x20 "CAN_IFLAG1,Interrupt Flags 1 Register. The CAN_IFLAG1 register defines the flags for the 32 message buffer interrupts for MB31 to MB0. CAN_IFLAG1 contains one interrupt flag bit per buffer. Each successful transmission or reception sets the corresponding.." hexmask.long.tbyte 0x20 8.--31. 1. "BUF31T081,Buffer MBi Interrupt Each bit flags the corresponding FlexCAN Message Buffer Interrupt for MB31 to MB8: - 1: The corresponding buffer has successfully completed transmission or reception. - 0: The corresponding buffer has no occurrence of.." bitfld.long 0x20 7. "BUF71,Buffer MB 7 Interrupt or Legacy Rx FIFO Overflow: - 1: MB7 completed transmission/reception when CAN_MCR.RFEN=O or Legacy Rx FIFO overflow when CAN_MCR.RFEN=1. - 0: No occurrence of MB7 completing transmission/reception when CAN_MCR.RFEN=O or of.." "No occurrence of MB7 completing..,MB7 completed transmission/reception when CAN_MCR" newline bitfld.long 0x20 6. "BUF61,Buffer MB6 Interrupt or Legacy Rx FIFO Warning: - 1: MB6 completed transmission/reception when CAN_MCR.RFEN=0 or Legacy Rx FIFO almost full when CAN_MCR.RFEN=1. - 0: No occurrence of MB6 completing transmission/reception when CAN_MCR.RFEN=O or of.." "No occurrence of MB6 completing..,MB6 completed transmission/reception when CAN_MCR" bitfld.long 0x20 5. "BUF51,Buffer MB5 Interrupt or Frames Available in Legacy Rx FIFO: - 1: MB5 completed transmission/reception when CAN_MCR.RFEN=0 or frame(s) available in the Legacy Rx FIFO when CAN_MCR.RFEN=1. BUF51 generates a OMA request when both CAN_MCR.RFEN and.." "No occurrence of MB5 completing..,MB5 completed transmission/reception when CAN_MCR" newline hexmask.long.byte 0x20 1.--4. 1. "BUF4T011,Buffer MB Interrupt or Reserved: - 1: The corresponding buffer has successfully completed transmission or reception when CAN_MCR.RFEN=O. - 0: The corresponding buffer has no occurrence of successfully completed transmission or reception when.." bitfld.long 0x20 0. "BUF01,Buffer MBO Interrupt or Clear Legacy Rx FIFO bit When CAN_MCR.RFEN is cleared (Legacy Rx FIFO disabled) BUF0I flags the interrupt for MB0: - 1: MB0 has successfully completed transmission or reception when CAN_MCR.RFEN=O. - 0: MB0 has no.." "MB0 has no occurrence of successfully completed..,MB0 has successfully completed transmission or.." line.long 0x24 "CAN_CTRL2,Control 2 Register. The CAN_CTRL2 register complements CAN_CTRL1. providing control bits for memory write access in Freeze mode. for extending Legacy Rx FIFO filter quantity. and for adjusting the operation of internal FlexCAN processes like.." bitfld.long 0x24 31. "ERRMSK_FAST,Error Interrupt Mask for errors detected in the Data Phase of fast CAN FD frames ERRMSK_FAST provides a mask for the ERRINT_FAST Interrupt in CAN_ESR1: - 1: ERRINT_FAST error interrupt enabled. - 0: ERRINT_FAST error interrupt disabled." "ERRINT_FAST error interrupt disabled,ERRINT_FAST error interrupt enabled" bitfld.long 0x24 30. "BOFFDONEMSK,Bus Off Done Interrupt Mask - Provides a mask for the Bus Off done interrupt in CAN_ESR1: - 1: Bus Off done interrupt enabled. - 0: Bus Off done interrupt disabled." "Bus Off done interrupt disabled,Bus Off done interrupt enabled" newline bitfld.long 0x24 29. "ECRWRE,Error-Correction Configuration Register Write Enable - Enables the CAN-MECR register to be updated: - 1: Enable update. - 0: Disable update." "Disable update,Enable update" bitfld.long 0x24 28. "WRMFRZ,Write-Access To Memory In Freeze Mode - Enable unrestricted write access to FlexCAN memory in Freeze mode: - 0: Maintain the write access restrictions. - 1: Enable unrestricted write access to FlexCAN memory. WRMFRZ can only be written in Freeze.." "Maintain the write access restrictions,Enable unrestricted write access to FlexCAN memory" newline hexmask.long.byte 0x24 24.--27. 1. "RFFN,Number of Legacy Rx FIFO Filters - Defines the number of Legacy Rx FIFO filters. The maximum selectable number of filters is a function of configuration parameter NUMBER_OF_MB. RFFN must not be programmed with values that cause the number of message.." hexmask.long.byte 0x24 19.--23. 1. "TASD,Tx Arbitration Start Delay - Indicates how many CAN bits the Tx arbitration process start point can be delayed from the first bit of CRC field on CAN bus." newline bitfld.long 0x24 18. "MRP,Mailboxes Reception Priority: - 1: Matching starts from mailboxes and continues on Legacy Rx FIFO. - 0: Matching starts from Legacy Rx FIFO and continues on mailboxes. If MRP is set the matching process starts from the mailboxes and if no match.." "Matching starts from Legacy Rx FIFO and..,Matching starts from mailboxes and continues on.." bitfld.long 0x24 17. "RRS,Remote Request Storing: - 1: Remote Request Frame is stored. - 0: Remote Response Frame is generated. If RRS is asserted a Remote Request Frame is submitted to a matching process and stored in the corresponding message buffer in the same fashion as.." "Remote Response Frame is generated,Remote Request Frame is stored" newline bitfld.long 0x24 16. "EACEN,Entire Frame Arbitration Field Comparison Enable for Rx Mailboxes: - 1: Enables the comparison of both the IDE and RTR bits of an Rx mailbox filter with the corresponding bits of the incoming frame. Mask bits do apply. - 0: Rx mailbox filter's IDE.." "Rx mailbox filter's IDE bit is always compared..,Enables the comparison of both the IDE and RTR.." bitfld.long 0x24 15. "TIMER_SRC,Timer Source - Selects the time tick source used for incrementing the free-running timer counter: - 1: The free-running timer is clocked by an external time tick. The period can be either adjusted to be equal to the baud rate on the CAN bus or.." "The free-running timer is clocked by the CAN bit..,The free-running timer is clocked by an external.." newline bitfld.long 0x24 14. "PREXCEN,Protocol Exception Enable - Enables the protocol exception feature: - 1: Protocol exception is enabled. - 0: Protocol exception is disabled. PREXCEN is writable only in Freeze mode. PREXCEN is not available (reserved write 0) if parameter FD EN.." "Protocol exception is disabled,Protocol exception is enabled" newline bitfld.long 0x24 12. "ISOCANFDEN,ISO CAN FD Enable - 1: Enable ISO CAN FD compliant operation. - 0: Disable ISO CAN FD specific features (non-ISO CAN FD operation). ISOCANFDEN enables ISO CAN FD compliant operation by enabling the following features which are part of the ISO.." "Disable ISO CAN FD specific features,Enable ISO CAN FD compliant operation" bitfld.long 0x24 11. "EDFLTDIS,Edge Filter Disable - Disables the edge filter used during the bus integration state: - 1: Edge filter is disabled. - 0: Edge filter is enabled. When the edge filter is enabled two consecutive nominal time quanta with dominant bus state are.." "Edge filter is enabled,Edge filter is disabled" newline rgroup.long 0x38++0x3 line.long 0x0 "CAN_ESR2,Error and Status 2 Register. The CAN_ESR2 register reports some general status information." hexmask.long.byte 0x0 16.--22. 1. "LPTM,Lowest Priority Tx Mailbox If CAN_ESR2.VPS is asserted LPTM indicates the lowest number inactive mailbox. If there is no inactive mailbox then the mailbox indicated depends on the CAN_CTRL1.LBUF bit value: - If CAN_CTRL1.LBUF is negated the.." newline bitfld.long 0x0 14. "VPS,Valid Priority Status - Indicates whether CAN_ESR2.IMB and CAN_ESR2.LPTM contents are currently valid or not: - 1: Contents of IMB and LPTM are valid. - 0: Contents of IMB and LPTM are invalid. VPS is asserted upon every complete Tx arbitration.." "Contents of IMB and LPTM are invalid,Contents of IMB and LPTM are valid" newline bitfld.long 0x0 13. "IMB,Inactive Mailbox If CAN_ESR2.VPS is asserted IMB indicates whether there is any inactive mailbox (CODE field is either 0b1000 or 0b0000): - 1: If CAN_ESR2.VPS is asserted there is at least one inactive mailbox. CAN_ESR2.LPTM content is the number.." "If CAN_ESR2,If CAN_ESR2" rgroup.long 0x44++0x3 line.long 0x0 "CAN_CRCR,The CAN_CRCR register provides information about the CRC of transmitted messages for non-FD messages. CAN_CRCR only reports the 15 low order bits of CRC calculations for messages in CAN FD format that require either 17 or 21 bits. For CAN FD.." hexmask.long.byte 0x0 16.--22. 1. "MBCRC,CRC Mailbox - Indicates the number of the mailbox corresponding to the value in the CAN CRCR.TXCRC field." newline hexmask.long.word 0x0 0.--14. 1. "TXCRC,Transmitted CRC Value - Indicates the CRC value of the last transmitted message for non-FD frames. For CAN FD frames the CRC value is reported in CAN_FDCRC." group.long 0x48++0x3 line.long 0x0 "CAN_RXFGMASK,Rx FIFO Global Mask Register. The CAN_RXFGMASK register is located in RAM. If the Legacy Rx FIFO is enabled. CAN_RXFGMASK is used to mask the Legacy Rx FIFO ID Filter Table elements that do not have a corresponding CAN_RXIMR according to.." hexmask.long 0x0 0.--31. 1. "FGM,Legacy Rx FIFO Global Mask Bits These bits mask the Legacy Rx FIFO ID Filter Table elements bits in a perfect alignment: - 1: The corresponding bit in the filter is checked. - 0: The corresponding bit in the filter is 'don't care'." rgroup.long 0x4C++0x3 line.long 0x0 "CAN_RXFIR,Rx FIFO Information Register. The CAN_RXFIR register provides information on the Legacy Rx FIFO. CAN_RXFIR is the port through which the CPU accesses the output of the Legacy RXFIR FIFO located in RAM. The Legacy RXFIR FIFO is written by the.." hexmask.long.word 0x0 0.--8. 1. "IDHIT,Identifier Acceptance Filter Hit Indicator - Indicates which Identifier Acceptance Filter was hit by the received message that is in the output of the Legacy Rx FIFO. If multiple filters match the incoming message ID the first matching IDAF found.." group.long 0x50++0x3 line.long 0x0 "CAN_CBT,CAN Bit Timing Register. The CAN_CBT register is an alternative way to store the CAN bit timing variables described in the CAN_CTRL1 register. EPRESDIV. EPROPSEG. EPSEG1. EPSEG2. and ERJW are extended versions of CAN_CTRL1 register PRESDIV." bitfld.long 0x0 31. "BTF,Bit Timing Format Enable - Enables the use of extended CAN bit timing fields EPRESDIV EPROPSEG EPSEG1 EPSEG2 and ERJW replacing the CAN bit timing variables defined in CAN_CTRL1: - 1: Extended bit time definitions enabled. - 0: Extended bit time.." "Extended bit time definitions disabled,Extended bit time definitions enabled" hexmask.long.word 0x0 21.--30. 1. "EPRESDIV,Extended Prescaler Division Factor When CAN_CBT.BTF is asserted EPRESDIV defines the ratio between the PE clock frequency and the Serial Clock (Sclock) frequency. EPRESDIV extends the CAN_CTRL1.PRESDIV value range. Sclock frequency = PE clock.." newline hexmask.long.byte 0x0 16.--20. 1. "ERJW,Extended Resync Jump Width When CAN_CBT.BTF is asserted ERJW defines the maximum number of time quanta that a bit time can be changed by one re- synchronization. ERJW extends the CAN_CTRL1.RJW value range. Resync Jump Width = ERJW + 1 One time.." hexmask.long.byte 0x0 10.--15. 1. "EPROPSEG,Extended Propagation Segment When CAN_CBT.BTF is asserted EPROPSEG defines the length of the Propagation Segment in the bit time. EPROPSEG extends the CAN_CTRL 1.PROPSEG value range. Propagation Segment Time = (EPROPSEG + 1) x Time-Quanta.." newline hexmask.long.byte 0x0 5.--9. 1. "EPSEG1,Extended Phase Segment 1 When CAN_CBT.BTF is asserted EPSEG1 defines the length of Phase Segment 1 in the bit time. EPSEG1 extends the CAN_CTRL 1.PSEG1 value range. Phase Buffer Segment 1 = (EPSEG1 + 1) x Time-Quanta Time-Quantum = one Sclock.." hexmask.long.byte 0x0 0.--4. 1. "EPSEG2,Extended Phase Segment 2 When CAN_CBT.BTF is asserted EPSEG2 defines the length of Phase Segment 2 in the bit time. EPSEG2 extends the CAN_CTRL1.PSEG2 value range. Phase Buffer Segment 1 = (EPSEG2 + 1) x Time-Quanta Time-Quantum = one Sclock.." group.long 0x68++0xF line.long 0x0 "CAN_IMASK4,Interrupt Masks 4 Register. The CAN_IMASK4 register allows any number of the 32 message buffer interrupts to be enabled or disabled for MB127 to MB96. CAN_IMASK4 contains one interrupt mask bit per buffer. enabling the CPU to determine which.." hexmask.long 0x0 0.--31. 1. "BUF127T096M,Buffer MB i Mask Each bit enables or disables the corresponding FlexCAN Message Buffer Interrupt for MB127 to MB96: - 1: The corresponding buffer interrupt is enabled. - 0: The corresponding buffer interrupt is disabled. When CAN FD is.." line.long 0x4 "CAN_IMASK3,Interrupt Masks 3 Register. The CAN_IMASK3 register allows any number of the 32 message buffer interrupts to be enabled or disabled for MB95 to MB64. CAN_IMASK3 contains one interrupt mask bit per buffer. enabling the CPU to determine which.." hexmask.long 0x4 0.--31. 1. "BUF95T064M,Buffer MB i Mask Each bit enables or disables the corresponding FlexCAN Message Buffer Interrupt for MB95 to MB64: - 1: The corresponding buffer interrupt is enabled. - 0: The corresponding buffer interrupt is disabled. When CAN FD is enabled.." line.long 0x8 "CAN_IFLAG4,Interrupt Flags 4 Register. The CAN_IFLAG4 register defines the flags for the 32 message buffer interrupts for MB127 to MB96. CAN_IFLAG4 contains one interrupt flag bit per buffer. Each successful transmission or reception sets the respective.." hexmask.long 0x8 0.--31. 1. "BUF127T096,Buffer MB Interrupt Each bit flags the corresponding FlexCAN Message Buffer Interrupt for MB127 to MB96: - 1: The corresponding buffer has successfully completed transmission or reception. - 0: The corresponding buffer has no occurrence of.." line.long 0xC "CAN_IFLAG3,Interrupt Flags 3 Register. The CAN_IFLAG3 register defines the flags for the 32 Message Buffer interrupts for MB95 to MB64. CAN_IFLAG3 contains one interrupt flag bit per buffer. Each successful transmission or reception sets the respective.." hexmask.long 0xC 0.--31. 1. "BUF95T064,Buffer MB i Interrupt Each bit flags the corresponding FlexCAN Message Buffer Interrupt for MB95 to MB64: - 1: The corresponding buffer has successfully completed transmission or reception. - 0: The corresponding buffer has no occurrence of.." group.long 0x880++0x27 line.long 0x0 "CAN_RXIMR0,Rx Individual Mask Register 0. The Rx Individual Mask Registers are used to store the acceptance masks for ID filtering in Rx MBs and the Legacy Rx FIFO. When the Legacy Rx FIFO is disabled (CAN_MCR.RFEN is negated). an individual mask is.." hexmask.long 0x0 0.--31. 1. "MI,Individual Mask Bits: 1'b1: The corresponding bit in the filter is checked. 1'b0: The corresponding bit in the filter is 'don't care'." line.long 0x4 "CAN_RXIMR1,Rx Individual Mask Register 1. The Rx Individual Mask Registers are used to store the acceptance masks for ID filtering in Rx MBs and the Legacy Rx FIFO. When the Legacy Rx FIFO is disabled (CAN_MCR.RFEN is negated). an individual mask is.." hexmask.long 0x4 0.--31. 1. "MI,Individual Mask Bits: 1'b1: The corresponding bit in the filter is checked. 1'b0: The corresponding bit in the filter is 'don't care'." line.long 0x8 "CAN_RXIMR2,Rx Individual Mask Register 2. The Rx Individual Mask Registers are used to store the acceptance masks for ID filtering in Rx MBs and the Legacy Rx FIFO. When the Legacy Rx FIFO is disabled (CAN_MCR.RFEN is negated). an individual mask is.." hexmask.long 0x8 0.--31. 1. "MI,Individual Mask Bits: - 1'b1: The corresponding bit in the filter is checked. - 1'b0: The corresponding bit in the filter is 'don't care'." line.long 0xC "CAN_RXIMR3,Rx Individual Mask Register 3. The Rx Individual Mask Registers are used to store the acceptance masks for ID filtering in Rx MBs and the Legacy Rx FIFO. When the Legacy Rx FIFO is disabled (CAN_MCR.RFEN is negated). an individual mask is.." hexmask.long 0xC 0.--31. 1. "MI,Individual Mask Bits: 1'b1: The corresponding bit in the filter is checked. 1'b0: The corresponding bit in the filter is 'don't care'." line.long 0x10 "CAN_RXIMR4,Rx Individual Mask Register 4. The Rx Individual Mask Registers are used to store the acceptance masks for ID filtering in Rx MBs and the Legacy Rx FIFO. When the Legacy Rx FIFO is disabled (CAN_MCR.RFEN is negated). an individual mask is.." hexmask.long 0x10 0.--31. 1. "MI,Individual Mask Bits: 1'b1: The corresponding bit in the filter is checked. 1'b0: The corresponding bit in the filter is 'don't care'." line.long 0x14 "CAN_RXIMR5,Rx Individual Mask Register 5. The Rx Individual Mask Registers are used to store the acceptance masks for ID filtering in Rx MBs and the Legacy Rx FIFO. When the Legacy Rx FIFO is disabled (CAN_MCR.RFEN is negated). an individual mask is.." hexmask.long 0x14 0.--31. 1. "MI,Individual Mask Bits: 1'b1: The corresponding bit in the filter is checked. 1'b0: The corresponding bit in the filter is 'don't care'." line.long 0x18 "CAN_RXIMR6,Rx Individual Mask Register 6. The Rx Individual Mask Registers are used to store the acceptance masks for ID filtering in Rx MBs and the Legacy Rx FIFO. When the Legacy Rx FIFO is disabled (CAN_MCR.RFEN is negated). an individual mask is.." hexmask.long 0x18 0.--31. 1. "MI,Individual Mask Bits: 1'b1: The corresponding bit in the filter is checked. 1'b0: The corresponding bit in the filter is 'don't care'." line.long 0x1C "CAN_RXIMR7,Rx Individual Mask Register 7. The Rx Individual Mask Registers are used to store the acceptance masks for ID filtering in Rx MBs and the Legacy Rx FIFO. When the Legacy Rx FIFO is disabled (CAN_MCR.RFEN is negated). an individual mask is.." hexmask.long 0x1C 0.--31. 1. "MI,Individual Mask Bits: 1'b1: The corresponding bit in the filter is checked. 1'b0: The corresponding bit in the filter is 'don't care'." line.long 0x20 "CAN_RXIMR8,Rx Individual Mask Register 8. The Rx Individual Mask Registers are used to store the acceptance masks for ID filtering in Rx MBs and the Legacy Rx FIFO. When the Legacy Rx FIFO is disabled (CAN_MCR.RFEN is negated). an individual mask is.." hexmask.long 0x20 0.--31. 1. "MI,Individual Mask Bits: 1'b1: The corresponding bit in the filter is checked. 1'b0: The corresponding bit in the filter is 'don't care'." line.long 0x24 "CAN_RXIMR9,Rx Individual Mask Register 9.The Rx Individual Mask Registers are used to store the acceptance masks for ID filtering in Rx MBs and the Legacy Rx FIFO. When the Legacy Rx FIFO is disabled (CAN_MCR.RFEN is negated). an individual mask is.." hexmask.long 0x24 0.--31. 1. "MI,Individual Mask Bits: 1'b1: The corresponding bit in the filter is checked. 1'b0: The corresponding bit in the filter is 'don't care'." repeat 16. (list 0xA 0xB 0xC 0xD 0xE 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1A 0x1B 0x1C )(list 0x0 0x4 0x8 0xC 0x10 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C 0x40 0x44 0x48 ) group.long ($2+0x8A8)++0x3 line.long 0x0 "CAN_RXIMR$1,Rx Individual Mask Register 10. The Rx Individual Mask Registers are used to store the acceptance masks for ID filtering in Rx MBs and the Legacy Rx FIFO. When the Legacy Rx FIFO is disabled (CAN_MCR.RFEN is negated). an individual mask is.." hexmask.long 0x0 0.--31. 1. "MI,Individual Mask Bits: 1'b1: The corresponding bit in the filter is checked. 1'b0: The corresponding bit in the filter is 'don't care'." repeat.end repeat 9. (list 0x1D 0x1E 0x24 0x25 0x26 0x27 0x28 0x29 0x3E )(list 0x4C 0x50 0x68 0x6C 0x70 0x74 0x78 0x7C 0xD0 ) group.long ($2+0x8A8)++0x3 line.long 0x0 "CAN_RXIMR$1,Rx Individual Mask Register 10. The Rx Individual Mask Registers are used to store the acceptance masks for ID filtering in Rx MBs and the Legacy Rx FIFO. When the Legacy Rx FIFO is disabled (CAN_MCR.RFEN is negated). an individual mask is.." hexmask.long 0x0 0.--31. 1. "MI,Individual Mask Bits: 1'b1: The corresponding bit in the filter is checked. 1'b0: The corresponding bit in the filter is 'don't care'." repeat.end group.long 0x8BC++0xB line.long 0x0 "CAN_RXIMR15,Rx Individual Mask Register 15.The Rx Individual Mask Registers are used to store the acceptance masks for ID filtering in Rx MBs and the Legacy Rx FIFO. When the Legacy Rx FIFO is disabled (CAN_MCR.RFEN is negated). an individual mask is.." hexmask.long 0x0 0.--31. 1. "MI,Individual Mask Bits: - 1'b1: The corresponding bit in the filter is checked. - 1'b0: The corresponding bit in the filter is 'don't care'." line.long 0x4 "CAN_RXIMR16,Rx Individual Mask Register 16.The Rx Individual Mask Registers are used to store the acceptance masks for ID filtering in Rx MBs and the Legacy Rx FIFO. When the Legacy Rx FIFO is disabled (CAN_MCR.RFEN is negated). an individual mask is.." hexmask.long 0x4 0.--31. 1. "MI,Individual Mask Bits: - 1'b1: The corresponding bit in the filter is checked. - 1'b0: The corresponding bit in the filter is 'don't care'." line.long 0x8 "CAN_RXIMR17,Rx Individual Mask Register 17.The Rx Individual Mask Registers are used to store the acceptance masks for ID filtering in Rx MBs and the Legacy Rx FIFO. When the Legacy Rx FIFO is disabled (CAN_MCR.RFEN is negated). an individual mask is.." hexmask.long 0x8 0.--31. 1. "MI,Individual Mask Bits: - 1'b1: The corresponding bit in the filter is checked. - 1'b0: The corresponding bit in the filter is 'don't care'." group.long 0x8FC++0x13 line.long 0x0 "CAN_RXIMR31,Rx Individual Mask Register 31.The Rx Individual Mask Registers are used to store the acceptance masks for ID filtering in Rx MBs and the Legacy Rx FIFO. When the Legacy Rx FIFO is disabled (CAN_MCR.RFEN is negated). an individual mask is.." hexmask.long 0x0 0.--31. 1. "MI,Individual Mask Bits: - 1'b1: The corresponding bit in the filter is checked. - 1'b0: The corresponding bit in the filter is 'don't care'." line.long 0x4 "CAN_RXIMR32,Rx Individual Mask Register 32.The Rx Individual Mask Registers are used to store the acceptance masks for ID filtering in Rx MBs and the Legacy Rx FIFO. When the Legacy Rx FIFO is disabled (CAN_MCR.RFEN is negated). an individual mask is.." hexmask.long 0x4 0.--31. 1. "MI,Individual Mask Bits: - 1'b1: The corresponding bit in the filter is checked. - 1'b0: The corresponding bit in the filter is 'don't care'." line.long 0x8 "CAN_RXIMR33,Rx Individual Mask Register 33.The Rx Individual Mask Registers are used to store the acceptance masks for ID filtering in Rx MBs and the Legacy Rx FIFO. When the Legacy Rx FIFO is disabled (CAN_MCR.RFEN is negated). an individual mask is.." hexmask.long 0x8 0.--31. 1. "MI,Individual Mask Bits: - 1'b1: The corresponding bit in the filter is checked. - 1'b0: The corresponding bit in the filter is 'don't care'." line.long 0xC "CAN_RXIMR34,Rx Individual Mask Register 34.The Rx Individual Mask Registers are used to store the acceptance masks for ID filtering in Rx MBs and the Legacy Rx FIFO. When the Legacy Rx FIFO is disabled (CAN_MCR.RFEN is negated). an individual mask is.." hexmask.long 0xC 0.--31. 1. "MI,Individual Mask Bits: - 1'b1: The corresponding bit in the filter is checked. - 1'b0: The corresponding bit in the filter is 'don't care'." line.long 0x10 "CAN_RXIMR35,Rx Individual Mask Register 35.The Rx Individual Mask Registers are used to store the acceptance masks for ID filtering in Rx MBs and the Legacy Rx FIFO. When the Legacy Rx FIFO is disabled (CAN_MCR.RFEN is negated). an individual mask is.." hexmask.long 0x10 0.--31. 1. "MI,Individual Mask Bits: - 1'b1: The corresponding bit in the filter is checked. - 1'b0: The corresponding bit in the filter is 'don't care'." group.long 0x928++0x4F line.long 0x0 "CAN_RXIMR42,Rx Individual Mask Register 42.The Rx Individual Mask Registers are used to store the acceptance masks for ID filtering in Rx MBs and the Legacy Rx FIFO. When the Legacy Rx FIFO is disabled (CAN_MCR.RFEN is negated). an individual mask is.." hexmask.long 0x0 0.--31. 1. "MI,Individual Mask Bits: - 1: The corresponding bit in the filter is checked. - 0: The corresponding bit in the filter is 'don't care'." line.long 0x4 "CAN_RXIMR43,Rx Individual Mask Register 43.The Rx Individual Mask Registers are used to store the acceptance masks for ID filtering in Rx MBs and the Legacy Rx FIFO. When the Legacy Rx FIFO is disabled (CAN_MCR.RFEN is negated). an individual mask is.." hexmask.long 0x4 0.--31. 1. "MI,Individual Mask Bits: - 1: The corresponding bit in the filter is checked. - 0: The corresponding bit in the filter is 'don't care'." line.long 0x8 "CAN_RXIMR44,Rx Individual Mask Register 44.The Rx Individual Mask Registers are used to store the acceptance masks for ID filtering in Rx MBs and the Legacy Rx FIFO. When the Legacy Rx FIFO is disabled (CAN_MCR.RFEN is negated). an individual mask is.." hexmask.long 0x8 0.--31. 1. "MI,Individual Mask Bits: - 1: The corresponding bit in the filter is checked. - 0: The corresponding bit in the filter is 'don't care'." line.long 0xC "CAN_RXIMR45,Rx Individual Mask Register 45.The Rx Individual Mask Registers are used to store the acceptance masks for ID filtering in Rx MBs and the Legacy Rx FIFO. When the Legacy Rx FIFO is disabled (CAN_MCR.RFEN is negated). an individual mask is.." hexmask.long 0xC 0.--31. 1. "MI,Individual Mask Bits: - 1: The corresponding bit in the filter is checked. - 0: The corresponding bit in the filter is 'don't care'." line.long 0x10 "CAN_RXIMR46,Rx Individual Mask Register 46.The Rx Individual Mask Registers are used to store the acceptance masks for ID filtering in Rx MBs and the Legacy Rx FIFO. When the Legacy Rx FIFO is disabled (CAN_MCR.RFEN is negated). an individual mask is.." hexmask.long 0x10 0.--31. 1. "MI,Individual Mask Bits: - 1: The corresponding bit in the filter is checked. - 0: The corresponding bit in the filter is 'don't care'." line.long 0x14 "CAN_RXIMR47,Rx Individual Mask Register 47.The Rx Individual Mask Registers are used to store the acceptance masks for ID filtering in Rx MBs and the Legacy Rx FIFO. When the Legacy Rx FIFO is disabled (CAN_MCR.RFEN is negated). an individual mask is.." hexmask.long 0x14 0.--31. 1. "MI,Individual Mask Bits: - 1: The corresponding bit in the filter is checked. - 0: The corresponding bit in the filter is 'don't care'." line.long 0x18 "CAN_RXIMR48,Rx Individual Mask Register 48.The Rx Individual Mask Registers are used to store the acceptance masks for ID filtering in Rx MBs and the Legacy Rx FIFO. When the Legacy Rx FIFO is disabled (CAN_MCR.RFEN is negated). an individual mask is.." hexmask.long 0x18 0.--31. 1. "MI,Individual Mask Bits: - 1: The corresponding bit in the filter is checked. - 0: The corresponding bit in the filter is 'don't care'." line.long 0x1C "CAN_RXIMR49,Rx Individual Mask Register 49.The Rx Individual Mask Registers are used to store the acceptance masks for ID filtering in Rx MBs and the Legacy Rx FIFO. When the Legacy Rx FIFO is disabled (CAN_MCR.RFEN is negated). an individual mask is.." hexmask.long 0x1C 0.--31. 1. "MI,Individual Mask Bits: - 1: The corresponding bit in the filter is checked. - 0: The corresponding bit in the filter is 'don't care'." line.long 0x20 "CAN_RXIMR50,Rx Individual Mask Register 50.The Rx Individual Mask Registers are used to store the acceptance masks for ID filtering in Rx MBs and the Legacy Rx FIFO. When the Legacy Rx FIFO is disabled (CAN_MCR.RFEN is negated). an individual mask is.." hexmask.long 0x20 0.--31. 1. "MI,Individual Mask Bits: - 1: The corresponding bit in the filter is checked. - 0: The corresponding bit in the filter is 'don't care'." line.long 0x24 "CAN_RXIMR51,Rx Individual Mask Register 51.The Rx Individual Mask Registers are used to store the acceptance masks for ID filtering in Rx MBs and the Legacy Rx FIFO. When the Legacy Rx FIFO is disabled (CAN_MCR.RFEN is negated). an individual mask is.." hexmask.long 0x24 0.--31. 1. "MI,Individual Mask Bits: - 1: The corresponding bit in the filter is checked. - 0: The corresponding bit in the filter is 'don't care'." line.long 0x28 "CAN_RXIMR52,Rx Individual Mask Register 52.The Rx Individual Mask Registers are used to store the acceptance masks for ID filtering in Rx MBs and the Legacy Rx FIFO. When the Legacy Rx FIFO is disabled (CAN_MCR.RFEN is negated). an individual mask is.." hexmask.long 0x28 0.--31. 1. "MI,Individual Mask Bits: - 1: The corresponding bit in the filter is checked. - 0: The corresponding bit in the filter is 'don't care'." line.long 0x2C "CAN_RXIMR53,Rx Individual Mask Register 53.The Rx Individual Mask Registers are used to store the acceptance masks for ID filtering in Rx MBs and the Legacy Rx FIFO. When the Legacy Rx FIFO is disabled (CAN_MCR.RFEN is negated). an individual mask is.." hexmask.long 0x2C 0.--31. 1. "MI,Individual Mask Bits: - 1: The corresponding bit in the filter is checked. - 0: The corresponding bit in the filter is 'don't care'." line.long 0x30 "CAN_RXIMR54,Rx Individual Mask Register 54.The Rx Individual Mask Registers are used to store the acceptance masks for ID filtering in Rx MBs and the Legacy Rx FIFO. When the Legacy Rx FIFO is disabled (CAN_MCR.RFEN is negated). an individual mask is.." hexmask.long 0x30 0.--31. 1. "MI,Individual Mask Bits: - 1: The corresponding bit in the filter is checked. - 0: The corresponding bit in the filter is 'don't care'." line.long 0x34 "CAN_RXIMR55,Rx Individual Mask Register 55.The Rx Individual Mask Registers are used to store the acceptance masks for ID filtering in Rx MBs and the Legacy Rx FIFO. When the Legacy Rx FIFO is disabled (CAN_MCR.RFEN is negated). an individual mask is.." hexmask.long 0x34 0.--31. 1. "MI,Individual Mask Bits: - 1: The corresponding bit in the filter is checked. - 0: The corresponding bit in the filter is 'don't care'." line.long 0x38 "CAN_RXIMR56,Rx Individual Mask Register 56.The Rx Individual Mask Registers are used to store the acceptance masks for ID filtering in Rx MBs and the Legacy Rx FIFO. When the Legacy Rx FIFO is disabled (CAN_MCR.RFEN is negated). an individual mask is.." hexmask.long 0x38 0.--31. 1. "MI,Individual Mask Bits: - 1: The corresponding bit in the filter is checked. - 0: The corresponding bit in the filter is 'don't care'." line.long 0x3C "CAN_RXIMR57,Rx Individual Mask Register 57.The Rx Individual Mask Registers are used to store the acceptance masks for ID filtering in Rx MBs and the Legacy Rx FIFO. When the Legacy Rx FIFO is disabled (CAN_MCR.RFEN is negated). an individual mask is.." hexmask.long 0x3C 0.--31. 1. "MI,Individual Mask Bits: - 1: The corresponding bit in the filter is checked. - 0: The corresponding bit in the filter is 'don't care'." line.long 0x40 "CAN_RXIMR58,Rx Individual Mask Register 58.The Rx Individual Mask Registers are used to store the acceptance masks for ID filtering in Rx MBs and the Legacy Rx FIFO. When the Legacy Rx FIFO is disabled (CAN_MCR.RFEN is negated). an individual mask is.." hexmask.long 0x40 0.--31. 1. "MI,Individual Mask Bits: - 1: The corresponding bit in the filter is checked. - 0: The corresponding bit in the filter is 'don't care'." line.long 0x44 "CAN_RXIMR59,Rx Individual Mask Register 59.The Rx Individual Mask Registers are used to store the acceptance masks for ID filtering in Rx MBs and the Legacy Rx FIFO. When the Legacy Rx FIFO is disabled (CAN_MCR.RFEN is negated). an individual mask is.." hexmask.long 0x44 0.--31. 1. "MI,Individual Mask Bits: - 1: The corresponding bit in the filter is checked. - 0: The corresponding bit in the filter is 'don't care'." line.long 0x48 "CAN_RXIMR60,Rx Individual Mask Register 60.The Rx Individual Mask Registers are used to store the acceptance masks for ID filtering in Rx MBs and the Legacy Rx FIFO. When the Legacy Rx FIFO is disabled (CAN_MCR.RFEN is negated). an individual mask is.." hexmask.long 0x48 0.--31. 1. "MI,Individual Mask Bits: - 1: The corresponding bit in the filter is checked. - 0: The corresponding bit in the filter is 'don't care'." line.long 0x4C "CAN_RXIMR61,Rx Individual Mask Register 61.The Rx Individual Mask Registers are used to store the acceptance masks for ID filtering in Rx MBs and the Legacy Rx FIFO. When the Legacy Rx FIFO is disabled (CAN_MCR.RFEN is negated). an individual mask is.." hexmask.long 0x4C 0.--31. 1. "MI,Individual Mask Bits: - 1: The corresponding bit in the filter is checked. - 0: The corresponding bit in the filter is 'don't care'." group.long 0x97C++0x3 line.long 0x0 "CAN_RXIMR63,Rx Individual Mask Register 63. The Rx Individual Mask Registers are used to store the acceptance masks for ID filtering in Rx MBs and the Legacy Rx FIFO. When the Legacy Rx FIFO is disabled (CAN_MCR.RFEN is negated). an individual mask is.." hexmask.long 0x0 0.--31. 1. "MI,Individual Mask Bits: - 1: The corresponding bit in the filter is checked. - 0: The corresponding bit in the filter is 'don't care'. Each Individual Mask Bit masks the corresponding bit in both the mailbox filter and Legacy Rx FIFO ID Filter Table.." group.long 0xAE0++0xF line.long 0x0 "CAN_MECR,The CAN_MECR register contains control bits for memory error detection and correction (ECC). NOTE: When CAN_CTRL2.ECRWRE is 0. writes to CAN_MECR are blocked. with the exception of the ECRWRDIS bit. The CAN_MECR register is not available when.." bitfld.long 0x0 31. "ECRWRDIS,Error Configuration Register Write Disable - Disables writes to this register: - 1: Write is disabled. - 0: Write is enabled. ECRWRDIS is automatically set to 1 (disabled) when CTRL2.ECRWRE is asserted." "Write is enabled,Write is disabled" newline bitfld.long 0x0 19. "HANCEI_MSK,Host Access With Non-Correctable Errors Interrupt Mask Enables the interrupt in case of non-correctable errors detected in memory reads issued by the host (CPU): - 1: Interrupt is enabled. - 0: Interrupt is disabled." "Interrupt is disabled,Interrupt is enabled" bitfld.long 0x0 18. "FANCEI_MSK,FlexCAN Access With Non-Correctable Errors Interrupt Mask Enables the interrupt in case of non-correctable errors detected in memory reads issued by the FlexCAN internal processes: - 1: Interrupt is enabled. - 0: Interrupt is disabled." "Interrupt is disabled,Interrupt is enabled" newline bitfld.long 0x0 16. "CEI_MSK,Correctable Errors Interrupt Mask Enables the interrupt in case of correctable errors detected in memory reads issued by the host or FlexCAN internal processes: - 1: Interrupt is enabled. - 0: Interrupt is disabled." "Interrupt is disabled,Interrupt is enabled" newline bitfld.long 0x0 15. "HAERRIE,Host Access Error Injection Enable Enables the injection of errors only in memory reads issued by the host (CPU): - 1: Injection is enabled. - 0: Injection is disabled." "Injection is disabled,Injection is enabled" bitfld.long 0x0 14. "FAERRIE,FlexCAN Access Error Injection Enable Enables the injection of errors only in memory reads issued by the FlexCAN internal processes: - 1: Injection is enabled. - 0: Injection is disabled." "Injection is disabled,Injection is enabled" newline bitfld.long 0x0 13. "EXTERRIE,Extended Error Injection Enable Memory accesses performed by internal FlexCAN processes are 64-bit accesses. EXTERRIE extends the error injection on 32-bit memory accesses to the complementary 32-bit word using the same 32-bit error injection.." "Error injection is applied only to the 32-bit word,Error injection is applied to the 64-bit word" newline bitfld.long 0x0 9. "RERDIS,Error Report Disable - Disables the update of the error report registers: - 1: Disable updates of the error report registers. The update of error-related flags and the generation of bus transfer errors are still active. - 0: Enable updates of the.." "Enable updates of the error report registers,Disable updates of the error report registers" bitfld.long 0x0 8. "ECCDIS,Error Correction Disable - Disables the memory detection and correction mechanism: - 1: Disable memory error correction. - 0: Enable memory error correction. In addition to disabling the error report mechanism ECCDIS = 1 also stops the update of.." "Enable memory error correction,Disable memory error correction" newline bitfld.long 0x0 7. "NCEFAFRZ,Non-Correctable Errors in FlexCAN Access Put Device In Freeze Mode Determines the response when a non-correctable error is detected in a memory read performed by FlexCAN internal processes: - 1: Put FlexCAN in Freeze mode. In this case entering.." "Keep normal operation,Put FlexCAN in Freeze mode" line.long 0x4 "CAN_ERRIAR,The CAN_ERRIAR register holds the address where a memory read error is to be injected. The size and usage of the FlexCAN RAM depends on the FlexCAN hardware configuration. The CAN_ERRIAR register is not available when parameter ECC_EN is 0." hexmask.long.word 0x4 2.--13. 1. "INJADDR_H,Error Injection Address High - Defines the twelve most significant bits of the physical RAM address where a memory read error is to be injected" newline rbitfld.long 0x4 0.--1. "INJADDR_L,Error Injection Address Low - Read-only field that defines the two least significant bits of the physical RAM address where a memory read error is to be injected. INJADDR - L[1:0] are always zero to ensure that the address is on a 32-bit.." "0,1,2,3" line.long 0x8 "CAN_ERRIDPR,The CAN_ERRIDPR register holds the error pattern to be injected in the data word read from memory. The CAN_ERRIDPR register is not available when parameter ECC_EN is 0." hexmask.long 0x8 0.--31. 1. "DFLIP,Data Flip Pattern Bits set to 1 in the flip pattern cause the corresponding data bit in the word read from memory to invert." line.long 0xC "CAN_ERRIPPR,The CAN_ERRIPPR register holds the error pattern to be injected in parity bits read from memory along with data word. Bits set to 1 in the flip pattern cause the corresponding parity bit in the word read from memory to invert. The CAN_ERRIPPR.." hexmask.long.byte 0xC 24.--28. 1. "PFLIP3,Parity Flip Pattern For Byte 3 (most significant)" newline hexmask.long.byte 0xC 16.--20. 1. "PFLIP2,Parity Flip Pattern For Byte 2" newline hexmask.long.byte 0xC 8.--12. 1. "PFLIP1,Parity Flip Pattern For Byte 2" newline hexmask.long.byte 0xC 0.--4. 1. "PFLIP0,Parity Flip Pattern For Byte O (least significant)" rgroup.long 0xAF0++0xB line.long 0x0 "CAN_RERRAR,The CAN_RERRAR register reports the address used for an access in which an error (correctable or non-correctable) was detected. and reports the identification of the source of that access. The address is always reported using a 32-bit.." bitfld.long 0x0 24. "NCE,Non-Correctable Error - Indicates that the report is due to a non-correctable error: - 1: Reporting a non-correctable error - 0: Reporting a correctable-error" "Reporting a correctable-error,Reporting a non-correctable error" newline bitfld.long 0x0 16.--18. "SAID,SAID[2] - Identification of the requestor of the memory read request: - 0: Requested by FlexCAN internal processes - 1: Requested by host (CPU) SAID[1] - Details of FlexCAN operation: - 0: Move - 1: Scanning SAID[0] - Operation that requested the.." "Transmission,Reception,?,?,?,?,?,?" newline hexmask.long.word 0x0 0.--13. 1. "ERRADDR,Address Where the Error was Detected" line.long 0x4 "CAN_RERRDR,The CAN_RERRDR register reports the raw data (unmodified by the correction performed by ECC logic) read from memory with error. The value reported does not represent the transient values of the BUSY bit when reading a message buffer. The.." hexmask.long 0x4 0.--31. 1. "RDATA,Raw data word read from memory with error." line.long 0x8 "CAN_RERRSYNR,The CAN_RERRSYNR register holds the syndrome detected in a memory read with error. It also reports the bytes that were read in this 32-bit read transaction." bitfld.long 0x8 31. "BE3,Byte Enabled For Byte 3 (most significant) - 1: The byte was read. - 0: The byte was not read." "The byte was not read,The byte was read" newline hexmask.long.byte 0x8 24.--28. 1. "SYND3,Error Syndrome For Byte 3 (most significant)" bitfld.long 0x8 23. "BE2,Byte Enabled for Byte 2." "0,1" newline hexmask.long.byte 0x8 16.--20. 1. "SYND2,Error Syndrome For Byte 2" newline bitfld.long 0x8 15. "BE1,Byte Enabled for Byte 1." "0,1" newline hexmask.long.byte 0x8 8.--12. 1. "SYND1,Error Syndrome For Byte 1" bitfld.long 0x8 7. "BE0,Byte Enabled for Byte 0 (least significant)." "0,1" newline hexmask.long.byte 0x8 0.--4. 1. "SYND0,Error Syndrome For Byte O (least significant)" group.long 0xAFC++0x2B line.long 0x0 "CAN_ERRSR,The CAN_ERRSR register holds the status bits of the error correction and detection operations. These flags can be cleared by writing 1 to them. Writing O has no effect. The CAN_ERRSR register is not available when parameter ECC_EN is 0." bitfld.long 0x0 19. "HANCEIF,FlexCAN Access With Non-Correctable Error Interrupt Flag: - 1: A non-correctable error was detected in a FlexCAN access. - 0: No non-correctable errors were detected in FlexCAN accesses so far. FANCEIF = 1 indicates that a non-correctable error.." "No non-correctable errors were detected in..,A non-correctable error was detected in a.." newline bitfld.long 0x0 18. "FANCEIF,FlexCAN Access With Non-Correctable Error Interrupt Flag: - 1: A non-correctable error was detected in a FlexCAN access. - 0: No non-correctable errors were detected in FlexCAN accesses so far. FANCEIF = 1 indicates that a non-correctable error.." "No non-correctable errors were detected in..,A non-correctable error was detected in a.." newline bitfld.long 0x0 16. "CEIF,Correctable Error Interrupt Flag: - 1: A correctable error was detected. - 0: No correctable errors were detected so far. CEIF = 1 indicates that a correctable error was detected in a memory read. If CAN_MECR.CEI_MSK is set the interrupt is asserted." "No correctable errors were detected so far,A correctable error was detected" newline bitfld.long 0x0 3. "HANCEIOF,Host Access With Non-Correctable Error Interrupt Overrun Flag: - 1: Overrun on non-correctable errors in host access. - 0: No overrun on non-correctable errors in host access. HANCEIOF = 1 indicates that a non-correctable error was detected in a.." "No overrun on non-correctable errors in host..,Overrun on non-correctable errors in host access" bitfld.long 0x0 2. "FANCEIOF,FlexCAN Access With Non-Correctable Error Interrupt Overrun Flag: - 1: Overrun on non-correctable errors in FlexCAN access. - 0: No overrun on non-correctable errors in FlexCAN access. FANCEIOF = 1 indicates that a non-correctable error was.." "No overrun on non-correctable errors in FlexCAN..,Overrun on non-correctable errors in FlexCAN.." newline bitfld.long 0x0 0. "CEIOF,Correctable Error Interrupt Overrun Flag: - 1: Overrun on correctable errors. - 0: No overrun on correctable errors. CEIOF = 1 indicates that a correctable error was detected in a memory read when CEIF was set. No interrupt is associated with this.." "No overrun on correctable errors,Overrun on correctable errors" line.long 0x4 "CAN_CTRL1_PN,The CAN_CTRL1_PN register contains control bits for Pretended Networking mode filtering selection. Configure CAN_CTRL1_PN with the filter criteria to be used to receive wakeup messages. CAN_CTRL1_PN bits other than WTOF_MSK and WUMF_MSK can.." bitfld.long 0x4 17. "WTOF_MSK,Wake Up by Timeout Flag Mask Bit - Masks the generation of a wakeup event originated by a timeout: - 1: Timeout wakeup event is enabled. - 0: Timeout wakeup event is disabled." "Timeout wakeup event is disabled,Timeout wakeup event is enabled" newline bitfld.long 0x4 16. "WUMF_MSK,Wake Up by Match Flag Mask Bit - Masks the generation of a wakeup event originated by a successful filtered Rx message - 1: Wakeup match event is enabled. - 0: Wakeup match event is disabled." "Wakeup match event is disabled,Wakeup match event is enabled" hexmask.long.byte 0x4 8.--15. 1. "NMATCH,Number of Messages Matching the Same Filtering Criteria NMATCH defines the number of times a given message must match the predefined filtering criteria for ID and/or PL before generating a wakeup event. This quantity can be configured in the 1 to.." newline bitfld.long 0x4 4.--5. "PLFS,Payload Filtering Selection - Selects the level of payload filtering to be applied when FlexCAN is under Pretended Networking mode: - 00: Match upon a payload contents against an exact target value. - 01: Match upon a payload value greater than or.." "Match upon a payload contents against an exact..,Match upon a payload value greater than or equal..,?,?" newline bitfld.long 0x4 2.--3. "IDFS,ID Filtering Selection - Selects the level of ID filtering to be applied when FlexCAN is under Pretended Networking mode: - 00: Match upon a ID contents against an exact target value. - 01: Match upon a ID value greater than or equal to a specified.." "Match upon a ID contents against an exact target..,Match upon a ID value greater than or equal to a..,?,?" bitfld.long 0x4 0.--1. "FCS,Filtering Combination Selection - Selects the filtering criteria to be applied when FlexCAN is under Pretended Networking mode: - 00: Message ID filtering only. - 01: Message ID filtering and payload filtering. - 10: Message ID filtering occurring a.." "Message ID filtering only,Message ID filtering and payload filtering,?,?" line.long 0x8 "CAN_CTRL2_PN,The CAN_CTRL2_PN register contains configuration bits for the timeout value under Pretended Networking mode. CAN_CTRL2_PN can be written in Freeze mode only. The CAN_CTRL2_PN register is not available when parameter PNET_EN is 0." hexmask.long.word 0x8 0.--15. 1. "MATCHTO,Timeout for No Message Matching the Filtering Criteria MATCHTO defines a timeout value that generates a wakeup event if CAN_MCR.PNET _EN is asserted. If the timeout counter reaches the target value when the FlexCAN is under Pretended Networking.." line.long 0xC "CAN_WU_MTC,The CAN_WU_MTC register contains wakeup information related to the matching processes performed while the FlexCAN receives frames under Pretended Networking mode. The CAN_WU_MTC register is not available when parameter PNET_EN is 0." bitfld.long 0xC 17. "WTOF,Wake Up by Timeout Flag Bit - Indicates whether the FlexCAN has detected a timeout event during a time interval defined by CAN CTRL2 PN.MATCHTO: - 1: Wakeup by timeout event detected. - 0: No wakeup by timeout event detected. WTOF generates a wakeup.." "No wakeup by timeout event detected,Wakeup by timeout event detected" newline bitfld.long 0xC 16. "WUMF,Wake Up by Match Flag Bit - Indicates whether the FlexCAN has detected a matching Rx incoming message that passed the filtering criteria specified in CAN_CTRL1_PN: - 1: Wakeup by match event detected. - 0: No wakeup by match event detected. WUMF.." "No wakeup by match event detected,Wakeup by match event detected" hexmask.long.byte 0xC 8.--15. 1. "MCOUNTER,Number of Matches while in Pretended Networking MCOUNTER reports the number of times a given message has matched the predefined filtering criteria for ID and/or PL before a wakeup event. MCOUNTER is reset by the FlexCAN when it enters in.." newline line.long 0x10 "CAN_FLT_ID1,The CAN_FLT_1D1 register contains the FLT_1D1 target value and the IDE and RTR target values used to filter an incoming message ID. FLT_1D1 is used either for equal to. smaller than. greater than comparisons. or as the lower limit value in an.." bitfld.long 0x10 30. "FLT_IDE,ID Extended Filter - Identifies whether the frame format is standard or extended: - 1: Accept extended frame format. - 0: Accept standard frame format. FLT_IDE is used as part of the ID reception filter." "Accept standard frame format,Accept extended frame format" newline bitfld.long 0x10 29. "FLT_RTR,Remote Transmission Request Filter - Identifies whether the frame is remote or not: - 1: Accept remote frame. - 0: Reject remote frame (accept data frame). FLT_RTR is used as part of the ID reception Filter." "Reject remote frame,Accept remote frame" hexmask.long 0x10 0.--28. 1. "FLT_ID1,ID Filter 1 for Pretended Networking Filtering - Defines either the 29 bits of an extended frame format considering all bits or the 11 bits of a standard frame format considering just the 11 leftmost bits." line.long 0x14 "CAN_FLT_DLC,The CAN_FLT_DLC register contains the DLC inside range target values (FLT_DLC_LO and FLT_DLC_HI) used to filter an incoming message. The DLC range is used only for payload filtering. CAN_FLT_DLC can be written in Freeze mode only. NOTE: When.." hexmask.long.byte 0x14 16.--19. 1. "FLT_DLC_LO,Lower Limit for Length of Data Bytes Filter - Specifies the lower limit for the number of data bytes considered valid for payload comparison. FLT_DLC_LO is used as part of payload reception Filter." newline hexmask.long.byte 0x14 0.--3. 1. "FLT_DLC_HI,Upper Limit for Length of Data Bytes Filter - Specifies the upper limit for the number of data bytes considered valid for payload comparison. FLT_DLC_HI is used as part of payload reception filter." line.long 0x18 "CAN_PL1_LO,The CAN_PL1_LO register contains Payload Filter 1 low order bits of the target value used to filter incoming message payload. It is used either for 'equal to'. 'smaller than or equal to'. 'greater than or equal to' comparisons. or as the lower.." hexmask.long.byte 0x18 24.--31. 1. "DATA_BYTE_0,Filter 1 low order bits for Pretended Networking payload fittermg corresponding to data byte 0." hexmask.long.byte 0x18 16.--23. 1. "DATA_BYTE_1,Filter 1 low order bits for Pretended Networking payload fittermg corresponding to data byte 1." newline hexmask.long.byte 0x18 8.--15. 1. "DATA_BYTE_2,Filter 1 low order bits for Pretended Networking payload fittermg corresponding to data byte 2." hexmask.long.byte 0x18 0.--7. 1. "DATA_BYTE_3,Filter 1 low order bits for Pretended Networking payload fittermg corresponding to data byte 3." line.long 0x1C "CAN_PL1_HI,The CAN_PL1_HI register contains Payload Filter 1 high order bits of the target value used to filter incoming message payload. It is used either for 'equal to'. 'smaller than or equal to'. 'greater than or equal to' comparisons. or as the.." hexmask.long.byte 0x1C 24.--31. 1. "DATA_BYTE_4,Filter 1 low order bits for Pretended Networking payload filtermg corresponding to data byte 4." hexmask.long.byte 0x1C 16.--23. 1. "DATA_BYTE_5,Filter 1 low order bits for Pretended Networking payload filtermg corresponding to data byte 5." newline hexmask.long.byte 0x1C 8.--15. 1. "DATA_BYTE_6,Filter 1 low order bits for Pretended Networking payload filtermg corresponding to data byte 6." hexmask.long.byte 0x1C 0.--7. 1. "DATA_BYTE_7,Filter 1 low order bits for Pretended Networking payload filtermg corresponding to data byte 7." line.long 0x20 "CAN_FLT_ID2_IDMASK,The CAN_FLT_ID2_1DMASK register contains the FLT_ID2 target value used only as the upper limit value in ID range detection. Also. when exact ID filtering criteria is selected. CAN_FLT_ID2_1DMASK is used to store the ID mask. The.." bitfld.long 0x20 30. "IDE_MSK,ID Extended Mask Bit - Indicates whether the frame format (standard/extended) is used as part of the ID reception filter - 1: The corresponding bit in the filter is checked. - 0: The corresponding bit in the filter is 'don't care'." "The corresponding bit in the filter is 'don't..,The corresponding bit in the filter is checked" newline bitfld.long 0x20 29. "RTR_MSK,Remote Transmission Request Mask Bit - Indicates whether the frame type (data/remote) is part of the ID reception filter: - 1: The corresponding bit in the filter is checked. - 0: The corresponding bit in the filter is 'don't care'." "The corresponding bit in the filter is 'don't..,The corresponding bit in the filter is checked" hexmask.long 0x20 0.--28. 1. "FLT_ID2_IDMASK,ID Filter 2 for Pretended Networking Filtering / ID Mask Bits for Pretended Networking ID Filtering FLT_ID2_1DMASK is used as FLT_ID2 in range of ID filtering to define the ID filter value in either: - Extended frame format (29 bits).." line.long 0x24 "CAN_PL2_PLMASK_LO,The CAN_PL2_PLMASK_LO register has two functions: - It contains the low order bits for the Payload Filter 2 used only as the upper limit value in a payload range detection. - When exact payload filtering criteria is selected." hexmask.long.byte 0x24 24.--31. 1. "DATA_BYTE_0,Payload Filter 2 low order bits / Payload Mask low order bits for Pretended Networking payload filtering corresponding to data byte 0." hexmask.long.byte 0x24 16.--23. 1. "DATA_BYTE_1,Payload Filter 2 low order bits / Payload Mask low order bits for Pretended Networking payload filtering corresponding to data byte 1." newline hexmask.long.byte 0x24 8.--15. 1. "DATA_BYTE_2,Payload Filter 2 low order bits / Payload Mask low order bits for Pretended Networking payload filtering corresponding to data byte 2." hexmask.long.byte 0x24 0.--7. 1. "DATA_BYTE_3,Payload Filter 2 low order bits / Payload Mask low order bits for Pretended Networking payload filtering corresponding to data byte 3." line.long 0x28 "CAN_PL2_PLMASK_HI,The CAN_PL2_PLMASK_HI register has two functions: - It contains the high order bits for the Payload Filter 2 used only as the upper limit value in a payload range detection. - When exact payload filtering criteria is selected." hexmask.long.byte 0x28 24.--31. 1. "DATA_BYTE_4,Payload Filter 2 high order bits / Payload Mask high order bits for Pretended Networking payload filtering corresponding to data byte 4." hexmask.long.byte 0x28 16.--23. 1. "DATA_BYTE_5,Payload Filter 2 high order bits / Payload Mask high order bits for Pretended Networking payload filtering corresponding to data byte 5." newline hexmask.long.byte 0x28 8.--15. 1. "DATA_BYTE_6,Payload Filter 2 high order bits / Payload Mask high order bits for Pretended Networking payload filtering corresponding to data byte 6." hexmask.long.byte 0x28 0.--7. 1. "DATA_BYTE_7,Payload Filter 2 high order bits / Payload Mask high order bits for Pretended Networking payload filtering corresponding to data byte 7." rgroup.long 0xB40++0x37 line.long 0x0 "CAN_WMB0_CS,Wake Up Message Buffer Register for C/S 0. Each of the four WMBs contains a register to store the Control Status (C/S) information (IDE. RTR. and DLC fields) of an incoming Rx message. NOTE: The C/S registers are located at 0x840 for WMB 0." bitfld.long 0x0 22. "SRR,Substitute Remote Request - Can be received either recessive or dominant." "0,1" newline bitfld.long 0x0 21. "IDE,ID Extended Bit - Identifies whether the frame format is standard or extended: - 1: Frame format is extended. - 0: Frame format is standard." "Frame format is standard,Frame format is extended" bitfld.long 0x0 20. "RTR,Remote Transmission Request Bit - Identifies whether the frame is remote or not: - 1: Frame is a remote frame. - 0: Frame is data frame (not remote)." "Frame is data frame,Frame is a remote frame" newline hexmask.long.byte 0x0 16.--19. 1. "DLC,Length of Data in Bytes - Length (in bytes) of the Rx data received when FlexCAN is in Pretended Networking mode. DLC is written by the FlexCAN module copied from the DLC (Data Length Code) field of the received frame. The DLC field indicates which.." line.long 0x4 "CAN_WMB0_ID,Wake Up Message Buffer Register for ID 0.Each of the four WMBs contains a register to store the ID information of an incoming Rx message. NOTE: The ID registers are located at 0x844 for WMB 0 . 0x854 for WMB1. 0x864 for WMB2. and 0x874 for.." hexmask.long 0x4 0.--28. 1. "ID,Received ID under Pretended Networking Mode - Stores the received ID as either: - The 29 bits of the extended frame format (considering the ID[28:0] field) or - The 11 bits of the standard frame format (considering the ID[28:18] field only. The.." line.long 0x8 "CAN_WMB0_D03,Wake Up Message Buffer Register for Data 0-3 0.Each of the four WMBs contains a register to store the data bytes O to 3 of the payload information of an incoming Rx message. This register's content is cleared when the incoming matched.." hexmask.long.byte 0x8 24.--31. 1. "DATA_BYTE_0,Received payload corresponding to data byte 0 under Pretended Networking mode." hexmask.long.byte 0x8 16.--23. 1. "DATA_BYTE_1,Received payload corresponding to data byte 1 under Pretended Networking mode." newline hexmask.long.byte 0x8 8.--15. 1. "DATA_BYTE_2,Received payload corresponding to data byte 2 under Pretended Networking mode." hexmask.long.byte 0x8 0.--7. 1. "DATA_BYTE_3,Received payload corresponding to data byte 3 under Pretended Networking mode." line.long 0xC "CAN_WMB0_D47,Wake Up Message Buffer Register for Data 4-7 0. Each of the four WMBs contains a register to store the data bytes 4 to 7 of the payload information of an incoming Rx message. This register's content is cleared when the incoming matched.." hexmask.long.byte 0xC 24.--31. 1. "DATA_BYTE_4,Received payload corresponding to data byte 4 under Pretended Networking mode." hexmask.long.byte 0xC 16.--23. 1. "DATA_BYTE_5,Received payload corresponding to data byte 5 under Pretended Networking mode." newline hexmask.long.byte 0xC 8.--15. 1. "DATA_BYTE_6,Received payload corresponding to data byte 6 under Pretended Networking mode." hexmask.long.byte 0xC 0.--7. 1. "DATA_BYTE_7,Received payload corresponding to data byte 7 under Pretended Networking mode." line.long 0x10 "CAN_WMB1_CS,Wake Up Message Buffer Register for C/S 1. Each of the four WMBs contains a register to store the Control Status (C/S) information (IDE. RTR. and DLC fields) of an incoming Rx message. NOTE: The C/S registers are located at 0x840 for WMB 0." bitfld.long 0x10 22. "SRR,Substitute Remote Request - Can be received either recessive or dominant." "0,1" newline bitfld.long 0x10 21. "IDE,ID Extended Bit - Identifies whether the frame format is standard or extended: - 1: Frame format is extended. - 0: Frame format is standard." "Frame format is standard,Frame format is extended" bitfld.long 0x10 20. "RTR,Remote Transmission Request Bit - Identifies whether the frame is remote or not: - 1: Frame is a remote frame. - 0: Frame is data frame (not remote)." "Frame is data frame,Frame is a remote frame" newline hexmask.long.byte 0x10 16.--19. 1. "DLC,Length of Data in Bytes - Length (in bytes) of the Rx data received when FlexCAN is in Pretended Networking mode. DLC is written by the FlexCAN module copied from the DLC (Data Length Code) field of the received frame. The DLC field indicates which.." line.long 0x14 "CAN_WMB1_ID,Wake Up Message Buffer Register for ID 1.Each of the four WMBs contains a register to store the ID information of an incoming Rx message. NOTE: The ID registers are located at 0x844 for WMB 0. 0x854 for WMB1. 0x864 for WMB2. and 0x874 for.." hexmask.long 0x14 0.--28. 1. "ID,Received ID under Pretended Networking Mode - Stores the received ID as either: - The 29 bits of the extended frame format (considering the ID[28:0] field) or - The 11 bits of the standard frame format (considering the ID[28:18] field only. The.." line.long 0x18 "CAN_WMB1_D03,Wake Up Message Buffer Register for Data 0-3 1. Each of the four WMBs contains a register to store the data bytes 4 to 7 of the payload information of an incoming Rx message. This register's content is cleared when the incoming matched.." hexmask.long.byte 0x18 24.--31. 1. "Data_byte_0,Data_byte_0" hexmask.long.byte 0x18 16.--23. 1. "Data_byte_1,Data_byte_1" newline hexmask.long.byte 0x18 8.--15. 1. "Data_byte_2,Data_byte_2" hexmask.long.byte 0x18 0.--7. 1. "Data_byte_3,Data_byte_3" line.long 0x1C "CAN_WMB1_D47,Wake Up Message Buffer Register for Data 4-7 1.Each of the four WMBs contains a register to store the data bytes 4 to 7 of the payload information of an incoming Rx message. This register's content is cleared when the incoming matched.." hexmask.long.byte 0x1C 24.--31. 1. "DATA_BYTE_4,Received payload corresponding to data byte 4 under Pretended Networking mode." hexmask.long.byte 0x1C 16.--23. 1. "DATA_BYTE_5,Received payload corresponding to data byte 5 under Pretended Networking mode." newline hexmask.long.byte 0x1C 8.--15. 1. "DATA_BYTE_6,Received payload corresponding to data byte 6 under Pretended Networking mode." hexmask.long.byte 0x1C 0.--7. 1. "DATA_BYTE_7,Received payload corresponding to data byte 7 under Pretended Networking mode." line.long 0x20 "CAN_WMB2_CS,Wake Up Message Buffer Register for C/S 2.Each of the four WMBs contains a register to store the Control Status (C/S) information (IDE. RTR. and DLC fields) of an incoming Rx message. NOTE: The C/S registers are located at 0x840 for WMB 0." bitfld.long 0x20 22. "SRR,Substitute Remote Request - Can be received either recessive or dominant." "0,1" newline bitfld.long 0x20 21. "IDE,ID Extended Bit - Identifies whether the frame format is standard or extended: - 1: Frame format is extended. - 0: Frame format is standard." "Frame format is standard,Frame format is extended" bitfld.long 0x20 20. "RTR,Remote Transmission Request Bit - Identifies whether the frame is remote or not: - 1: Frame is a remote frame. - 0: Frame is data frame (not remote)." "Frame is data frame,Frame is a remote frame" newline hexmask.long.byte 0x20 16.--19. 1. "DLC,Length of Data in Bytes - Length (in bytes) of the Rx data received when FlexCAN is in Pretended Networking mode. DLC is written by the FlexCAN module copied from the DLC (Data Length Code) field of the received frame. The DLC field indicates which.." line.long 0x24 "CAN_WMB2_ID,Wake Up Message Buffer Register for ID 2. Each of the four WMBs contains a register to store the ID information of an incoming Rx message. NOTE: The ID registers are located at 0x844 for WMB 0. 0x854 for WMB1. 0x864 for WMB2. and 0x874 for.." hexmask.long 0x24 0.--28. 1. "ID,Received ID under Pretended Networking Mode - Stores the received ID as either: - The 29 bits of the extended frame format (considering the ID[28:0] field) or - The 11 bits of the standard frame format (considering the ID[28:18] field only. The.." line.long 0x28 "CAN_WMB2_D03,Wake Up Message Buffer Register for Data 0-3 2.Each of the four WMBs contains a register to store the data bytes 4 to 7 of the payload information of an incoming Rx message. This register's content is cleared when the incoming matched.." hexmask.long.byte 0x28 24.--31. 1. "Data_byte_0,Data_byte_0" hexmask.long.byte 0x28 16.--23. 1. "Data_byte_1,Data_byte_1" newline hexmask.long.byte 0x28 8.--15. 1. "Data_byte_2,Data_byte_2" hexmask.long.byte 0x28 0.--7. 1. "Data_byte_3,Data_byte_3" line.long 0x2C "CAN_WMB2_D47,Wake Up Message Buffer Register for Data 4-7 2. Each of the four WMBs contains a register to store the data bytes 4 to 7 of the payload information of an incoming Rx message. This register's content is cleared when the incoming matched.." hexmask.long.byte 0x2C 24.--31. 1. "DATA_BYTE_4,Received payload corresponding to data byte 4 under Pretended Networking mode." hexmask.long.byte 0x2C 16.--23. 1. "DATA_BYTE_5,Received payload corresponding to data byte 5 under Pretended Networking mode." newline hexmask.long.byte 0x2C 8.--15. 1. "DATA_BYTE_6,Received payload corresponding to data byte 6 under Pretended Networking mode." hexmask.long.byte 0x2C 0.--7. 1. "DATA_BYTE_7,Received payload corresponding to data byte 7 under Pretended Networking mode." line.long 0x30 "CAN_WMB3_CS,Wake Up Message Buffer Register for C/S 3.Each of the four WMBs contains a register to store the Control Status (C/S) information (IDE. RTR. and DLC fields) of an incoming Rx message. NOTE: The C/S registers are located at 0x840 for WMB 0." bitfld.long 0x30 22. "SRR,Substitute Remote Request - Can be received either recessive or dominant." "0,1" newline bitfld.long 0x30 21. "IDE,ID Extended Bit - Identifies whether the frame format is standard or extended: - 1: Frame format is extended. - 0: Frame format is standard." "Frame format is standard,Frame format is extended" bitfld.long 0x30 20. "RTR,Remote Transmission Request Bit - Identifies whether the frame is remote or not: - 1: Frame is a remote frame. - 0: Frame is data frame (not remote)." "Frame is data frame,Frame is a remote frame" newline hexmask.long.byte 0x30 16.--19. 1. "DLC,Length of Data in Bytes - Length (in bytes) of the Rx data received when FlexCAN is in Pretended Networking mode. DLC is written by the FlexCAN module copied from the DLC (Data Length Code) field of the received frame. The DLC field indicates which.." line.long 0x34 "CAN_WMB3_ID,Wake Up Message Buffer Register for ID 3. Each of the four WMBs contains a register to store the ID information of an incoming Rx message. NOTE: The ID registers are located at 0x844 for WMB 0. 0x854 for WMB1. 0x864 for WMB2. and 0x874 for.." hexmask.long 0x34 0.--28. 1. "ID,Received ID under Pretended Networking Mode - Stores the received ID as either: - The 29 bits of the extended frame format (considering the ID[28:0] field) or - The 11 bits of the standard frame format (considering the ID[28:18] field only. The.." repeat 2. (list 0x3 0x2F )(list 0x0 0x4 ) rgroup.long ($2+0xB78)++0x3 line.long 0x0 "CAN_WMB3_D$1,Wake Up Message Buffer Register for Data 0-3 3. Each of the four WMBs contains a register to store the data bytes 4 to 7 of the payload information of an incoming Rx message. This register's content is cleared when the incoming matched.." hexmask.long.byte 0x0 24.--31. 1. "Data_byte_0,Data_byte_0" hexmask.long.byte 0x0 16.--23. 1. "Data_byte_1,Data_byte_1" newline hexmask.long.byte 0x0 8.--15. 1. "Data_byte_2,Data_byte_2" hexmask.long.byte 0x0 0.--7. 1. "Data_byte_3,Data_byte_3" repeat.end group.long 0xC00++0x7 line.long 0x0 "CAN_FDCTRL,The CAN_FDCTRL register contains control bits for CAN FD operation. CAN_FDCTRL also defines the data size of message buffers allocated in different partitions of RAM (memory blocks). When an 8-byte payload is selected: - Block RO allocates.." bitfld.long 0x0 31. "FDRATE,Bit Rate Switch Enable - Enables the effect of the Bit Rate Switch (BRS bit) during the data phase of Tx messages: - 1: Transmit a frame with bit rate switching if the BRS bit in the Tx MB is recessive. - 0: Transmit a frame in nominal rate. The.." "Transmit a frame in nominal rate,Transmit a frame with bit rate switching if the.." newline bitfld.long 0x0 25.--26. "MBDSR3,Message Buffer Data Size for Region 3 - Selects the data size for region R3 of message buffers allocated in RAM: - 00: Selects 8 bytes per message buffer. - 01: Selects 16 bytes per message buffer. - 10: Selects 32 bytes per message buffer. - 11:.." "Selects 8 bytes per message buffer,Selects 16 bytes per message buffer,?,Selects the data size for region R3 of message.." newline bitfld.long 0x0 22.--23. "MBDSR2,Message Buffer Data Size for Region 2 - Selects the data size for region R2 of message buffers allocated in RAM: - 00: Selects 8 bytes per message buffer. - 01: Selects 16 bytes per message buffer. - 10: Selects 32 bytes per message buffer. - 11:.." "Selects 8 bytes per message buffer,Selects 16 bytes per message buffer,Selects the data size for region R2 of message..,?" newline bitfld.long 0x0 19.--20. "MBDSR1,Message Buffer Data Size for Region 1 - Selects the data size for region R1 of message buffers allocated in RAM: - 00: Selects 8 bytes per message buffer. - 01: Selects 16 bytes per message buffer. - 10: Selects 32 bytes per message buffer. - 11:.." "Selects 8 bytes per message buffer,Selects 16 bytes per message buffer,?,?" newline bitfld.long 0x0 16.--17. "MBDSR0,Message Buffer Data Size for Region O - Selects the data size for region RO of message buffers allocated in RAM: - 00: Selects 8 bytes per message buffer. - 01: Selects 16 bytes per message buffer. - 10: Selects 32 bytes per message buffer. - 11:.." "Selects 8 bytes per message buffer,Selects 16 bytes per message buffer,?,?" bitfld.long 0x0 15. "TDCEN,Transceiver Delay Compensation Enable - Enables or disables the TDC feature: - 1: TDC is enabled. - 0: TDC is disabled. TDCEN can be written in Freeze mode only. Note: TDC must be disabled when Loop-Back mode is enabled (see CAN_CTRL1.LPB). Note:.." "TDC is disabled,TDC is enabled" newline bitfld.long 0x0 14. "TDCFAIL,Transceiver Delay Compensation Fail TDCFAIL indicates when the Transceiver Delay Compensation (TDC) mechanism is out of range unable to compensate the transceiver's loop delay and successfully compare the delayed received bits to the.." "Measured loop delay is in range,Measured loop delay is out of range" newline hexmask.long.byte 0x0 8.--12. 1. "TDCOFF,Transceiver Delay Compensation Offset TDCOFF contains the offset value to be added to the measured transceiver's loop delay in order to define the position of the delayed comparison point when bit rate switching is active. TDCOFF can be written in.." newline hexmask.long.byte 0x0 0.--5. 1. "TDCVAL,Transceiver Delay Compensation Value TDCVAL contains the value of the transceiver loop delay measured from the transmitted EDL to RO transition edge to the respective received one added to the TDCOFF value. This value is an integer multiple of the.." line.long 0x4 "CAN_FDCBT,The CAN_FDCBT register stores the CAN bit timing variables used in the data phase of CAN FD messages when CAN_FDCTRL.FDRATE is set. compatible with CAN FD specification. FPRESDIV. FPROPSEG. FPSEG1. FPSEG2. and FRJW are used to define the time.." hexmask.long.word 0x4 20.--29. 1. "FPRESDIV,Fast Prescaler Division Factor FPRESDIV defines the ratio between the PE clock frequency and the Serial Clock (Sclock) frequency in the data bit rate portion of a CAN FD message with the BRS bit set. The Sclock period defines the time quantum of.." newline bitfld.long 0x4 16.--18. "FRJW,Fast Resync Jump Width FRJW defines the maximum number of time quanta that a bit time can be changed by one re-synchronization in the data bit rate portion of a CAN FD message with the BRS bit set. Resync Jump Width = FSJW + 1. One time quantum is.." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x4 10.--14. 1. "FPROPSEG,Fast Propagation Segment FPROPSEG defines the length of the Propagation Segment in the bit time in the data bit rate portion of a CAN FD message with the BRS bit set. Propagation Segment Time = FPROPSEG x Time-Quanta Time-Quantum = one Sclock.." newline bitfld.long 0x4 5.--7. "FPSEG1,Fast Phase Segment 1 FPSEG1 defines the length of Phase Segment 1 in the bit time in the data bit rate portion of a CAN FD message with the BRS bit set. Phase Segment 1 = (FPSEG1 + 1) x Time-Quanta Time-Quantum = one Sclock period FPSEG1 can be.." "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 0.--2. "FPSEG2,Fast Phase Segment 2 FPSEG2 defines the length of Phase Segment 2 in the data bit rate portion of a CAN FD message with the BRS bit set. Phase Segment 2 = (FPSEG2 + 1) x Time-Quanta Time-Quantum = one Sclock period FPSEG2 can be written only in.." "0,1,2,3,4,5,6,7" rgroup.long 0xC08++0x3 line.long 0x0 "CAN_FDCRC,The CAN_CRCR register provides information about the CRC of transmitted messages for non-FD messages. CAN_CRCR only reports the 15 low order bits of CRC calculations for messages in CAN FD format that require either 17 or 21 bits. For CAN FD.." hexmask.long.byte 0x0 24.--30. 1. "FD_MBCRC,CRC Mailbox - Indicates the number of the mailbox corresponding to the value in the CAN CRCR.TXCRC field." newline hexmask.long.tbyte 0x0 0.--20. 1. "FD_TXCRC,Transmitted CRC Value - Indicates the CRC value of the last transmitted message for non-FD frames. For CAN FD frames the CRC value is reported in CAN_FDCRC." tree.end repeat.end endif tree.end tree "CE (Crypto Engine Control Registers)" sif (CORENAME()=="CORTEXR5F") tree "CE1_REG" base ad:0xF0340000 rgroup.long 0x0++0x7 line.long 0x0 "CE0_STAT,CE0 working status" newline bitfld.long 0x0 5. "PKE_BUSY,1: PKE is busy 0:PKE is idle" "?,PKE is busy 0:PKE is idle" newline bitfld.long 0x0 4. "GENKEY_BUSY,1. CE0 generate key function is busy" "0,1" newline bitfld.long 0x0 3. "HASH_BUSY,1: the HASH of CE0 is busy" "?,the HASH of CE0 is busy" newline bitfld.long 0x0 2. "CIPHER_BUSY,1 the CIPHER of CE0 is busy" "0,1" newline bitfld.long 0x0 1. "GETRNDNUM_BUSY,1: get random number function of CE0 is busy" "?,get random number function of CE0 is busy" newline bitfld.long 0x0 0. "DMA_BUSY,1: the DMA of CE0 is busy 0: the DMA of CE0 is idle" "the DMA of CE0 is idle,the DMA of CE0 is busy" line.long 0x4 "CE0_ERRSTAT,CE0 error status" newline hexmask.long.byte 0x4 24.--27. 1. "SKC_ERR_STAT,'the error status of skc sequencer the bit 0 ~ 3 are [sram wr err] [ rand number fetch err] [ secure violation occurs] [reserved]'" newline bitfld.long 0x4 19. "SSRAM_ERR_STAT,'the error status of CE sram" "0,1" newline bitfld.long 0x4 16.--18. "DMA_ERR_STAT,'the error status of dma sequencer the bit of 0 -2 are [sram_rw_err] [wdma ch err] [rdma ch err]'" "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x4 8.--13. 1. "CIPHER_ERR_STAT,'the error status of cipher sequencer the bit 0 - 4 are [key_port_err] [rdma_ch_err] [wdma_ch_err] [sram_wr_err] [sram_rd_err] [decryption from secure to non-secure]'" newline hexmask.long.byte 0x4 0.--3. 1. "HASH_ERR_STAT,'the error status of hash sequencer the bit 0 ~ 3 are [sram_wr_err] [sram rd err] [rdma_err] [wdma err]'" group.long 0xC++0x3F line.long 0x0 "CE0_CIPHER_CTRL,CE0 cipher control register" bitfld.long 0x0 31. "CIPHER_HEADER_SAVE,1 the header will be saved into dst memory 0: header will not be saved" "header will not be saved,?" newline bitfld.long 0x0 28.--29. "CIPHER_KEY2TYPE,key 2 type 10: input keyport 00: secure sram public area 01: secure area others: reserved" "secure sram public area,secure area others: reserved,?,?" newline bitfld.long 0x0 25.--26. "CIPHER_KEYTYPE,key type 10: input keyport 00: secure sram public area 01: secure area others: reserved" "secure sram public area,secure area others: reserved,?,?" newline hexmask.long.word 0x0 16.--24. 1. "AESMODE,'AES mode XTS : 010000000 ECB : 000000001 CBC : 000000010 CTR : 000000100 CFB : 000001000 OFB : 000010000 CCM : 000100000 GCM : 001000000 XTS : 010000000 CMAC: 100000000'" newline bitfld.long 0x0 13. "CIPHER_SAVE,0: normal mode last part of the message 1: operation context will be saved at the end of operation" "normal mode last part of the message,operation context will be saved at the end of.." newline bitfld.long 0x0 12. "CIPHER_LOAD,0 : normal mode first start of the message 1: operation restart from previously save context" "normal mode first start of the message,operation restart from previously save context" newline bitfld.long 0x0 11. "CIPHER_DECKEYCAL,0 use the input key for decryption operations 1: use the pre-calculation of the key is done before" "?,use the pre-calculation of the key is done before" newline bitfld.long 0x0 9.--10. "CIPHER_KEYSIZE,key size 00: 128bit key 01: 256 bit key 10: 192bit key 11: reserved" "0,1,2,3" newline bitfld.long 0x0 8. "CIPHERMODE,0 encryption 1 decryption" "0,1" newline bitfld.long 0x0 0. "CIPHER_GO,'write 1 to this bit will start the cipher operation'" "0,1" line.long 0x4 "CE0_CIPHER_HEADER_LEN,CE0 cipher header length register" hexmask.long 0x4 0.--31. 1. "CIPHER_HEADER_LEN,'cipher data header length in bytes'" line.long 0x8 "CE0_CIPHER_KEY_ADDR,CE0 cipher key address" hexmask.long.word 0x8 16.--31. 1. "CIPHER_KEY2_ADDR,key2 address in secure SRAM or keyport" newline hexmask.long.word 0x8 0.--15. 1. "CIPHER_KEY_ADDR,CIPHER_KEY_ADDR address in secure SRAM or keyport" line.long 0xC "CE0_CIPHER_SRC_ADDR,CE0 cipher source data address register" hexmask.long 0xC 0.--31. 1. "CIPHER_SRC_ADDR,cipher data source address in bytes" line.long 0x10 "CE0_CIPHER_SRC_ADDR_H,CE0 cipher source data address high part" newline bitfld.long 0x10 8.--10. "CIPHER_SRC_TYPE,011: CE SRAM Secure AREA 001:CE SRAM public area 000:external memories other: reserved" "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x10 0.--7. 1. "CIPHER_SRC_ADDR_H,the high part of CE0 cipher source address" line.long 0x14 "CE0_CIPHER_DST_ADDR,CE0 cipher results data address" hexmask.long 0x14 0.--31. 1. "CIPHER_DST_ADDR,CE0 cipher data destination address" line.long 0x18 "CE0_CIPHER_DST_ADDR_H,CE0 cipher results data address high part" newline bitfld.long 0x18 8.--10. "CIPHER_DST_TYPE,011: CE SRAM Secure AREA 001:CE SRAM public area 000:external memories other: reserved" "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x18 0.--7. 1. "CIPHER_DST_ADDR_H,CE0 cipher data destination address" line.long 0x1C "CE0_CIPHER_IV_CONTEXT_ADDR,CE0 cipher IV and context address register" hexmask.long.word 0x1C 16.--31. 1. "CIPHER_CONTEXT_ADDR,CIPHER context storage address the context is always stored into SRAM secure area" newline hexmask.long.word 0x1C 0.--15. 1. "CIPHER_IV_ADDR,CIPHER iv storage address the iv is always stored into SRAM secure area" line.long 0x20 "CE0_CIPHER_PAYLOAD_LEN,CE0 cipher payload length(calcuation length)" hexmask.long 0x20 0.--31. 1. "CIPHER_PAYLOAD_LEN,CIPHER_PAYLOAD_LEN including the header length in byte" line.long 0x24 "CE0_HASH_CTRL,CE0 hash control register" newline bitfld.long 0x24 24. "HASH_HMAC_EN,1: hmac is enabled 0: hmac is disabled" "hmac is disabled,hmac is enabled" newline bitfld.long 0x24 19. "HASH_KEY,1 need to load key 0 donot load key" "0,1" newline bitfld.long 0x24 18. "HASH_INIT_SECURE,1 load IV from secure area 0: load IV from public area" "load IV from public area,?" newline bitfld.long 0x24 17. "HASH_INIT,1 load IV for the hash 0 not load initial vector" "0,1" newline bitfld.long 0x24 16. "HASH_SHAUPDATE,0 final SHA224 output 7 words and SHA384 output 6 words 1: update SHA224/384 output 8 words please don't use this feature in hmac mode" "?,update SHA224/384 output 8 words please don't.." newline bitfld.long 0x24 15. "HASH_PADDINGEN,0: bypass padding logic 1: use hw padding logic" "bypass padding logic,use hw padding logic" newline hexmask.long.byte 0x24 8.--14. 1. "HASH_MODE,0000001 MD5 0000010 SHA1 0000100 SHA224 0001000 SHA256 0010000 SHA384 0100000 SHA512 1000000 SM3" newline bitfld.long 0x24 0. "HASH_GO,HASH Calculation start" "0,1" line.long 0x28 "CE0_HASH_KEYIV_ADDR,CE0 hash key and IV register" hexmask.long.word 0x28 16.--31. 1. "HASH_KEY_ADDR,HASH_KEY address" newline hexmask.long.word 0x28 0.--15. 1. "HASH_IV_ADDR,HASH initial vection address" line.long 0x2C "CE0_HMAC_KEY_CTRL,CE0 HMAC key control register" newline bitfld.long 0x2C 16.--17. "HMAC_KEY_TYPE,10 from key interface 01: from SRAM secure area 00 from SRAM public area" "?,from SRAM secure area 00 from SRAM public area,?,?" newline hexmask.long.word 0x2C 0.--15. 1. "HMAC_KEY_LEN,CE0 hash key length in CE SRAM" line.long 0x30 "CE0_HASH_CALC_LEN,CE0 hash calculation length register" hexmask.long 0x30 0.--31. 1. "HASH_CALC_LEN,CE0 hash calculation length in bytes" line.long 0x34 "CE0_HASH_SRC_ADDR,CE0 hash source data register" hexmask.long 0x34 0.--31. 1. "HASH_SRC_ADDR,CE0 HASH SRC ADDR" line.long 0x38 "CE0_HASH_SRC_ADDR_H,CE0 hash source data register high part" newline bitfld.long 0x38 8.--10. "HASH_SRC_TYPE,000: external memory 001: CE SRAM public area 011 CE sram secure area 1xx: SKC key interface space" "external memory,CE SRAM public area 011 CE sram secure area 1xx:..,?,?,?,?,?,?" newline hexmask.long.byte 0x38 0.--7. 1. "HASH_SRC_ADDR_H,the high part of CE0 hash src address" line.long 0x3C "CE0_HASH_DST_ADDR,CE0 hash results address" newline bitfld.long 0x3C 16.--18. "HASH_DST_TYPE,001 internal secure SRAM 001 public area in secure ram 1xx key interface" "0,1,2,3,4,5,6,7" newline hexmask.long.word 0x3C 0.--15. 1. "HASH_DST_ADDR,the dst address in secure SRAM" group.long 0x50++0x17 line.long 0x0 "CE0_DMA_CTRL,CE0 DMA control register" newline bitfld.long 0x0 10. "DMA_DONEINTEN,1 the interrupt will be generated if the DMA operation is done" "0,1" newline rbitfld.long 0x0 9. "DMA_CMDFIFO_FULL,cmd fifo is full" "0,1" newline rbitfld.long 0x0 8. "DMA_CMDFIFO_EMPTY,cmd fifo is empty" "0,1" newline bitfld.long 0x0 0. "DMA_GO,write 1 to this register start CE0 DMA operation" "0,1" line.long 0x4 "CE0_DMA_SRC_ADDR,CE0 DMA source data address register" hexmask.long 0x4 0.--31. 1. "DMA_SRC_ADDR,CE0 dma source addr" line.long 0x8 "CE0_DMA_SRC_ADDR_H,CE0 DMA source data address register high part" newline bitfld.long 0x8 8.--10. "DMA_SRC_TYPE,011: CE SRAM Secure AREA 001:CE SRAM public area 000:external memories other: reserved" "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x8 0.--7. 1. "DMA_SRC_ADDR_H,CE0 dma source addr high part" line.long 0xC "CE0_DMA_DST_ADDR,CE0 DMA destination data address" hexmask.long 0xC 0.--31. 1. "DMA_DST_ADDR,CE1 DMA DST ADDR" line.long 0x10 "CE0_DMA_DST_ADDR_H,CE0 DMA destination data address high part" newline bitfld.long 0x10 8.--10. "DMA_DST_TYPE,011: CE SRAM Secure AREA 001:CE SRAM public area 000:external memories other: reserved" "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x10 0.--7. 1. "DMA_DST_ADDR_H,CE1 DMA DST ADDR high part" line.long 0x14 "CE0_DMA_LEN,CE0 dma transfer data length" newline hexmask.long.word 0x14 0.--15. 1. "DMA_LEN,DMA transfer length in byte" group.long 0x80++0xB line.long 0x0 "CE0_PK_POINTERREG,CE0 PKE operand point register" newline hexmask.long.byte 0x0 24.--27. 1. "PK_OPPTRN,'When executing primitive arithmetic operations" newline hexmask.long.byte 0x0 16.--19. 1. "PK_OPPTRC,'When executing primitive arithmetic operations" newline hexmask.long.byte 0x0 8.--11. 1. "PK_OPPTRB,'When executing primitive arithmetic operations" newline hexmask.long.byte 0x0 0.--3. 1. "PK_OPPTRA,'When executing primitive arithmetic operations" line.long 0x4 "CE0_PK_COMMANDREG,CE0 PKE command register" bitfld.long 0x4 31. "PK_CALCR2,PK_CALCR2" "0,1" newline bitfld.long 0x4 30. "PK_FLAGB,'B See routine description'" "0,1" newline bitfld.long 0x4 29. "PK_FLAGA,'A See routine description'" "0,1" newline bitfld.long 0x4 28. "PK_SWAP,'bytes Swap the bytes on AHB interface: '0': Native format (little endian) '1': Byte swapped (big endian) See also section 4.2.1. This bit must be programmed before writing/reading any data in data memory.'" "0,1" newline bitfld.long 0x4 27. "PK_BUFFER,PK_BUFFER" "0,1" newline bitfld.long 0x4 26. "PK_EDWARDS,'Enable Edwards curve (see routine description)'" "0,1" newline bitfld.long 0x4 25. "PK_RANDPROJ,'Enable randomization of projective coordinates (counter-measure)'" "0,1" newline bitfld.long 0x4 24. "PK_RANDKE,'Enable randomization of exponent/scalar (counter-measure)'" "0,1" newline hexmask.long.byte 0x4 20.--23. 1. "PK_SELCURVE,'Enable accelerator for specific curve modulus: 0x0: No acceleration (default) 0x1: P256 0x2: P384 0x3: P521/E-521 0x4: P192 0x5: Curve25519/Ed25519 This field has no effect when the optional acceleration hardware is not included.'" newline hexmask.long.word 0x4 8.--18. 1. "PK_SIZE,'Of Operands (in data memory) This field defines the size (= number of bytes minus one) of the operands for the current operation. Possible values are limited by the maximum supported operand size. Examples: 0x014 -> ECC on curve K-163 0x01F ->.." newline bitfld.long 0x4 7. "PK_FIELD,''0': Field is GF(p) '1': Field is GF(2m)'" "0,1" newline hexmask.long.byte 0x4 0.--6. 1. "PK_TYPE,'of operation This field defines the operation to be performed. See table below for details.'" line.long 0x8 "CE0_PKE_CTRL,CE0_PKE_CTRL" newline bitfld.long 0x8 2. "PKE_SOFT_RST,'Writing a 1 to this bit will reset the pke_seq logic'" "0,1" newline bitfld.long 0x8 1. "PK_CLRMEMAFTEROP,'Writing a 1 to this bit will make the pke to clear its memories after all operations are complete'" "0,1" newline bitfld.long 0x8 0. "PKE_GO,'Writing a '1' starts the processing.'" "0,1" rgroup.long 0x8C++0x3 line.long 0x0 "CE0_PK_STATUSREG,CE0_PK_STATUSREG" newline bitfld.long 0x0 17. "PK_INTERRUPT,'status This bit reflects the IRQ output value. It is set to '1' when the operation is finished. It is cleared when the CPU writes the bit 1 of Control Register.'" "0,1" newline bitfld.long 0x0 16. "PK_BUSY,'This bit reflects the BUSY output value. It is set to '1' when the operation starts and it is cleared when the operation is finished.'" "0,1" newline bitfld.long 0x0 13. "PK_NOTQUADRATICRESIDUE,PK_NOTQUADRATICRESIDUE" "0,1" newline bitfld.long 0x0 12. "PK_COMPOSITE,PK_COMPOSITE" "0,1" newline bitfld.long 0x0 11. "PK_NOTINVERTIBLE,PK_NOTINVERTIBLE" "0,1" newline bitfld.long 0x0 10. "PK_PARAM_AB_NOTVALID,PK_PARAM_AB_NOTVALID" "0,1" newline bitfld.long 0x0 9. "PK_SIGNATURE_NOTVALID,PK_SIGNATURE_NOTVALID" "0,1" newline bitfld.long 0x0 8. "PK_NOTIMPLEMENTED,PK_NOTIMPLEMENTED" "0,1" newline bitfld.long 0x0 7. "PK_PARAM_N_NOTVALID,PK_PARAM_N_NOTVALID" "0,1" newline bitfld.long 0x0 6. "PK_COUPLE_NOTVALID,PK_COUPLE_NOTVALID" "0,1" newline bitfld.long 0x0 5. "PK_POINT_PX_ATINFINITY,PK_POINT_PX_ATINFINITY" "0,1" newline bitfld.long 0x0 4. "PK_POINT_PX_NOTONCURVE,PK_POINT_PX_NOTONCURVE" "0,1" newline hexmask.long.byte 0x0 0.--3. 1. "PK_FAIL_ADDRESS,'These bits indicate which data location generated the error flag. They are not available for all error flags.'" group.long 0x94++0x3 line.long 0x0 "CE0_PK_TIMER,CE0_PK_TIMER" hexmask.long 0x0 0.--31. 1. "PK_TIMER,'The timer counts the number of clock cycles when the PK engine is busy. It is not cleared automatically. It can be written by software (when the PK is idle). The register is updated at the end of every operation (reading it when the PK engine.." rgroup.long 0x98++0x3 line.long 0x0 "CE0_PK_HWCONFIGREG,CE0_PK_HWCONFIGREG" bitfld.long 0x0 31. "PK_DISABLECM,'State of DisableCM input (high when counter-measures are disabled)'" "0,1" newline bitfld.long 0x0 24. "PK_25519,'Support Curve25519/Ed25519 acceleration'" "0,1" newline bitfld.long 0x0 23. "PK_P192,'Support ECC P192 acceleration'" "0,1" newline bitfld.long 0x0 22. "PK_P521,'Support ECC P521 acceleration'" "0,1" newline bitfld.long 0x0 21. "PK_P384,'Support ECC P384 acceleration'" "0,1" newline bitfld.long 0x0 20. "PK_P256,'Support ECC P256 acceleration'" "0,1" newline bitfld.long 0x0 18.--19. "RESERVED,'unused'" "0,1,2,3" newline bitfld.long 0x0 17. "PK_BINARYFIELD,'Support binary field'" "0,1" newline bitfld.long 0x0 16. "PK_PRIMEFIELD,'Support prime field'" "0,1" newline hexmask.long.byte 0x0 12.--15. 1. "PK_NBMULT,'Number of multipliers: 0x0: 1 multiplier 0x1: 4 multipliers 0x2: 16 multipliers 0x4: 64 multipliers 0x8: 256 multipliers'" newline hexmask.long.word 0x0 0.--11. 1. "PK_MAXOPSIZE,'Maximum operand size (number of bytes) 4096 bytes'" group.long 0x9C++0xB line.long 0x0 "CE0_PK_RESULTS_CTRL,CE0_PK_RESULTS_CTRL" hexmask.long.word 0x0 16.--31. 1. "PKE_RESULTS_OP_LEN,'pke results each operand length in bytes'" newline hexmask.long.word 0x0 0.--15. 1. "PKE_RESULTS_OP_SELECT,'pke results output select each bit correspnding to the operand position of the pke data memory'" line.long 0x4 "CE0_PK_RESULTS_DST_ADDR,CE0_PK_RESULTS_DST_ADDR" hexmask.long 0x4 0.--31. 1. "PKE_RESULTS_DST_ADDR,'pke results dma dst address low 32bit'" line.long 0x8 "CE0_PK_RESULTS_DST_ADDR_H,CE0_PK_RESULTS_DST_ADDR_H" newline bitfld.long 0x8 8.--10. "PKE_RESULTS_DST_TYPE,'pke results dma dst data type 011: CE SRAM Secure AREA 001:CE SRAM public area 000:external memories other: reserved'" "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x8 0.--7. 1. "PKE_RESULTS_DST_ADDR_H,'pke results dma dst address high 8bit'" rgroup.long 0x100++0x3 line.long 0x0 "CE0_TRNG_STATUS,CE0 TRNG status register" newline bitfld.long 0x0 1. "RNG_SEQ_RUNNING,'1: the rng sequencer is running currently 0: rng sequencer is in idle status'" "rng sequencer is in idle status',the rng sequencer is running currently" newline bitfld.long 0x0 0. "RNG_READY,'1: the value in the random number register of CE0 is valid" "?,the value in the random number register of CE0.." repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) rgroup.long ($2+0x104)++0x3 line.long 0x0 "CE0_TRNG_NUM$1,CE0_TRNG_NUM0" hexmask.long 0x0 0.--31. 1. "TRNG_NUM0,CE0 the random number0 value" repeat.end rgroup.long 0x114++0x3 line.long 0x0 "CE0_HRNG_NUM,CE0_HRNG_NUM" hexmask.long 0x0 0.--31. 1. "HRNG_NUM,CE0 the hybird random number value" group.long 0x120++0xB line.long 0x0 "CE0_SKC_CTRL,CE0 SKC control register" newline bitfld.long 0x0 8.--10. "SKC_CMD,the command of SKC 001: generate random number 010: erase key contrainer" "?,generate random number,?,?,?,?,?,?" newline bitfld.long 0x0 0. "SKC_GO,CE0 secure FSM start trigger" "0,1" line.long 0x4 "CE0_SKC_RNG_ADDR,CE0 SKC random number register" newline bitfld.long 0x4 24. "SKC_RNG_SECURE,CE0 1: random number generated to secure area 0 : in public area" "in public area,random number generated to secure area" newline hexmask.long.byte 0x4 16.--22. 1. "SKC_RNG_LEN,'numbers of bits to generate into sram granularity is 256 bit'" newline hexmask.long.word 0x4 0.--12. 1. "SKC_RNG_ADDR,CE0 random number generation address in CE sram the address granularity is 8 bytes" line.long 0x8 "CE0_SKC_KEYBLOB_CTRL,CE0 SKC key blob control register" newline bitfld.long 0x8 0. "SKC_KEYBLOB_CTRL,CE0 key blob control 1: is key blob :0 : is the secret data" "?,is key blob :0 : is the secret data" group.long 0x140++0x3 line.long 0x0 "CE0_INTEN,CE0 interrupt enable register" newline bitfld.long 0x0 13. "DMA_FIFOERROR_INTEN,DMA fifo error interrupt" "0,1" newline bitfld.long 0x0 12. "PKE_INTEGRITY_ERROR_INTEN,ALGORITHM_INTEGRITY interrupt" "0,1" newline bitfld.long 0x0 11. "HASH_INTEGRITY_ERROR_INTEN,ALGORITHM_INTEGRITY_ERROR interrupt" "0,1" newline bitfld.long 0x0 10. "CIPHER_INTEGRITY_ERROR_INTEN,ALGORITHM_INTEGRITY_ERROR interrupt" "0,1" newline bitfld.long 0x0 9. "SKC_INTEGRITY_ERROR_INTEN,SKC_INTEGRITY_ERROR interrupt" "0,1" newline bitfld.long 0x0 8. "DMA_INTEGRITY_ERROR_INTEN,ALGORITHM_INTEGRITY interrupt" "0,1" newline bitfld.long 0x0 4. "PKE_DONE_INTEN,PKE_DONE interrupt" "0,1" newline bitfld.long 0x0 3. "HASH_DONE_INTEN,HASH_DONE interrupt" "0,1" newline bitfld.long 0x0 2. "CIPHER_DONE_INTEN,CIPHER_DONE_INTEN" "0,1" newline bitfld.long 0x0 1. "SKC_DONE_INTEN,KEYgen done interrupt enable" "0,1" newline bitfld.long 0x0 0. "DMA_DONE_INTEN,DMA_DONE interrupt" "0,1" rgroup.long 0x144++0x3 line.long 0x0 "CE0_INTSTAT,CE0 interrupt status register" newline bitfld.long 0x0 13. "DMA_FIFOERROR_INTSTAT,SSRAM_DMAFIFO error interrupt" "0,1" newline bitfld.long 0x0 12. "PKE_INTEGRITY_ERROR_INTSTAT,ALGORITHM_INTEGRITY interrupt" "0,1" newline bitfld.long 0x0 11. "HASH_INTEGRITY_ERROR_INTSTAT,ALGORITHM_INTEGRITY_ERROR interrupt" "0,1" newline bitfld.long 0x0 10. "CIPHER_INTEGRITY_ERROR_INTSTAT,ALGORITHM_INTEGRITY_ERROR interrupt" "0,1" newline bitfld.long 0x0 9. "SKC_INTEGRITY_ERROR_INTSTAT,SKC_INTEGRITY_ERROR interrupt" "0,1" newline bitfld.long 0x0 8. "DMA_INTEGRITY_ERROR_INTSTAT,ALGORITHM_INTEGRITY interrupt" "0,1" newline bitfld.long 0x0 4. "PKE_DONE_INTSTAT,PKE_DONE interrupt" "0,1" newline bitfld.long 0x0 3. "HASH_DONE_INTSTAT,HASH_DONE interrupt" "0,1" newline bitfld.long 0x0 2. "CIPHER_DONE_INTSTAT,CIPHER_DONE_INTSTATE" "0,1" newline bitfld.long 0x0 1. "SKC_DONE_INTSTAT,KEYgen done interrupt enable" "0,1" newline bitfld.long 0x0 0. "DMA_DONE_INTSTAT,DMA_DONE interrupt" "0,1" group.long 0x148++0x3 line.long 0x0 "CE0_INTCLR,CE0 interrupt clear register" newline bitfld.long 0x0 13. "DMA_FIFOERROR_INTCLR,SSRAM_DMAFIFO error interrupt" "0,1" newline bitfld.long 0x0 12. "PKE_INTEGRITY_ERROR_INTCLR,ALGORITHM_INTEGRITY interrupt" "0,1" newline bitfld.long 0x0 11. "HASH_INTEGRITY_ERROR_INTCLR,ALGORITHM_INTEGRITY_ERROR interrupt" "0,1" newline bitfld.long 0x0 10. "CIPHER_INTEGRITY_ERROR_INTCLR,ALGORITHM_INTEGRITY_ERROR interrupt" "0,1" newline bitfld.long 0x0 9. "SKC_INTEGRITY_ERROR_INTCLR,SKC_INTEGRITY_ERROR interrupt" "0,1" newline bitfld.long 0x0 8. "DMA_INTEGRITY_ERROR_INTCLR,ALGORITHM_INTEGRITY interrupt" "0,1" newline bitfld.long 0x0 4. "PKE_DONE_INTCLR,PKE_DONE interrupt" "0,1" newline bitfld.long 0x0 3. "HASH_DONE_INTCLR,HASH_DONE interrupt" "0,1" newline bitfld.long 0x0 2. "CIPHER_DONE_INTCLR,CIPHER_DONE_INTCLRE" "0,1" newline bitfld.long 0x0 1. "SKC_DONE_INTCLR,KEYgen done interrupt enable" "0,1" newline bitfld.long 0x0 0. "DMA_DONE_INTCLR,DMA_DONE interrupt" "0,1" group.long 0x8000++0x7 line.long 0x0 "SECURE_CTRL,CE secure violation control" hexmask.long.byte 0x0 24.--31. 1. "CE_SRAM_SIZE_VIO,the CE sram size size is not correct" newline rbitfld.long 0x0 17. "SRAM_SIZE_TOTAL_VIO,the CE sram size total size is not correct" "0,1" newline bitfld.long 0x0 16. "PKE_CM_DISABLE,'1: disable the PKE counter measure 0 : enable the counter measure'" "enable the counter measure',disable the PKE counter measure" newline hexmask.long.byte 0x0 8.--15. 1. "SECURE_VIOLATION_STATUS,'secure violation input status'" newline hexmask.long.byte 0x0 0.--7. 1. "SECURE_VIOLATION_ENABLE,'the corresponding bits enable the secure violation source'" line.long 0x4 "SESRAM_SIZE,Secure SRAM size for CE0" newline hexmask.long.byte 0x4 0.--6. 1. "CE0_RAM_SIZE,the CE sram size" group.long 0x800C++0x3 line.long 0x0 "SESRAM_SASIZE,secure SRAM secure area size" newline hexmask.long.byte 0x0 0.--6. 1. "CE0_RAM_SASIZE,the secure area sram size" group.long 0x8014++0x7 line.long 0x0 "VCE_SINATURE_MASK,VCE SIGNAGURE generation mask" hexmask.long 0x0 0.--31. 1. "VCE_SINATURE_MASK,'the mask for the vce to generate signature from id'" line.long 0x4 "VCE_SINATURE_MASK_HIGH,VCE_SINATURE_MASK_HIGH" newline hexmask.long.byte 0x4 0.--7. 1. "VCE_SINATURE_MASK_HIGH,'the mask for the vce to generate signature from id high part'" group.long 0x8020++0x7 line.long 0x0 "HRNG_CTRL,HRNG_CTRL" newline hexmask.long.byte 0x0 8.--11. 1. "HRNG_LOAD_CNT,'the counter to control the frequency for the hrng LFSF load the feedback cycle'" newline bitfld.long 0x0 0. "NOISE_ENABLE,'1: enable the noise source for the hrng 0: disable the noise source'" "disable the noise source',enable the noise source for the hrng" line.long 0x4 "HRNG_SEED_CTRL,HRNG_SEED_CTRL" bitfld.long 0x4 31. "LOAD_SEED_GO,'write 1 to this bit will load the seed into the hrng auto clear'" "0,1" newline hexmask.long 0x4 0.--30. 1. "SEED_NUM,'the seed number" group.long 0x8030++0x3 line.long 0x0 "TRNG_CTRL,TRNG_CTRL" newline bitfld.long 0x0 0. "CE_TRNG_SEQ_GO,'write this bit will start the trng sequencer to fetch the random number for all VCEs'" "0,1" group.long 0x8050++0x3 line.long 0x0 "DEBUG_BUS_SEL,DEBUG_BUS_SEL" newline hexmask.long.word 0x0 0.--15. 1. "DEBUG_BUS_SEL,'debug bus select'" rgroup.long 0x8054++0x3 line.long 0x0 "DEBUG_BUS_STATUS,DEBUG_BUS_STATUS" hexmask.long 0x0 0.--31. 1. "DEBUG_BUS_STATUS,'debug bus output'" group.long 0x8100++0x3 line.long 0x0 "TRNG_CONTROL,TRNG_CONTROL" newline bitfld.long 0x0 20. "TRNG_FIFOWRITESTARTUP,'Enable write of the samples in the FIFO during start-up'" "0,1" newline hexmask.long.byte 0x0 16.--19. 1. "TRNG_NB128BITBLOCKS,'Number of 128 bit blocks used in AES-CBCMAC post-processing. This value cannot be zero.'" newline bitfld.long 0x0 15. "TRNG_AIS31TESTSEL,'Select input to the AIS31 test module 0: Before conditioning 1: After conditioning'" "Before conditioning,After conditioning'" newline bitfld.long 0x0 14. "TRNG_HEALTHTESTSEL,'Select input to health test module 0: Before conditioning 1: After conditioning'" "Before conditioning,After conditioning'" newline bitfld.long 0x0 13. "TRNG_AIS31BYPASS,'Bypass AIS31 tests such that the results of the start-up and online tests do not affect the FSM state'" "0,1" newline bitfld.long 0x0 12. "TRNG_HEALTHTESTBYPASS,'Bypass NIST tests such that the results of the start-up and online test do not affect the FSM state'" "0,1" newline bitfld.long 0x0 11. "TRNG_FORCERUN,'Force oscillators to run when FIFO is full'" "0,1" newline bitfld.long 0x0 10. "TRNG_INTENALM,'Interrupt enable for AIS31 noise alarm'" "0,1" newline bitfld.long 0x0 9. "TRNG_INTENPRE,'Interrupt enable for AIS31 preliminary noise alarm'" "0,1" newline bitfld.long 0x0 8. "TRNG_SOFTRESET,'Software reset 0: Normal mode 1: The continuous test" "Normal mode,The continuous test" newline bitfld.long 0x0 7. "TRNG_INTENFULL,'Interrupt enable for FIFO full'" "0,1" newline bitfld.long 0x0 5. "TRNG_INTENPROP,'Interrupt enable for Adaptive Proportion Test failure (1024-sample window)'" "0,1" newline bitfld.long 0x0 4. "TRNG_INTENREP,'Interrupt enable for Repetition Count Test failure'" "0,1" newline bitfld.long 0x0 3. "TRNG_CONDBYPASS,'0: the conditioning function is used (normal mode) 1: the conditioning function is bypassed (to observe entropy source directly).'" "the conditioning function is used,the conditioning function is bypassed" newline bitfld.long 0x0 2. "TRNG_TESTEN,'Select input for conditioning function and continuous tests: 0: Noise source (normal mode) 1: Test data register (test mode)'" "Noise source,Test data register" newline bitfld.long 0x0 1. "TRNG_LFSREN,TRNG_LFSREN" "0,1" newline bitfld.long 0x0 0. "TRNG_ENABLE,'Enable the NDRNG.'" "0,1" rgroup.long 0x8104++0xB line.long 0x0 "TRNG_FIFOLEVEL,TRNG_FIFOLEVEL" hexmask.long 0x0 0.--31. 1. "TRNG_FIFOLEVEL,'Number of 32 bits words of random available in the FIFO. Any write to this register clears the FullInt flag in the Status register.'" line.long 0x4 "TRNG_FIFOTHD,TRNG_FIFOTHD" hexmask.long 0x4 0.--31. 1. "TRNG_FIFOTHD,'FIFO level below which the module leaves the idle state to refill the fifo" line.long 0x8 "TRNG_FIFODEPTH,TRNG_FIFODEPTH" hexmask.long 0x8 0.--31. 1. "TRNG_FIFODEPTH,'Depth Maximum number of 32 bits words that can be stored in the FIFO: 2g_fifodepth.'" group.long 0x8110++0xF line.long 0x0 "TRNG_KEY0REG,TRNG_KEY0REG" hexmask.long 0x0 0.--31. 1. "TRNG_KEY0REG,'Key (MSB)'" line.long 0x4 "TRNG_KEY1REG,TRNG_KEY1REG" hexmask.long 0x4 0.--31. 1. "TRNG_KEY1REG,'Key'" line.long 0x8 "TRNG_KEY2REG,TRNG_KEY2REG" hexmask.long 0x8 0.--31. 1. "TRNG_KEY2REG,'Key'" line.long 0xC "TRNG_KEY3REG,TRNG_KEY3REG" hexmask.long 0xC 0.--31. 1. "TRNG_KEY3REG,'Key (LSB)'" wgroup.long 0x8120++0x3 line.long 0x0 "TRNG_TESTDATA,TRNG_TESTDATA" hexmask.long 0x0 0.--31. 1. "TRNG_TESTDATA,'feed known data to the conditioning function or to the continous tests.'" group.long 0x8124++0x7 line.long 0x0 "TRNG_REPTHRESREG,TRNG_REPTHRESREG" hexmask.long 0x0 0.--31. 1. "TRNG_REPTHRESREG,'Repetition Test Count Cut-Off value'" line.long 0x4 "TRNG_PROPTHRESREG,TRNG_PROPTHRESREG" hexmask.long 0x4 0.--31. 1. "TRNG_PROPTHRESREG,'Adaptive Proportion Test (1024-sample window) Cut-Off value'" group.long 0x8130++0x17 line.long 0x0 "TRNG_STATUS,TRNG_STATUS" newline bitfld.long 0x0 11. "TRNG_FIFOACCFAIL,'Set when a FIFO data read is performed while the NDRNG is disabled AND has its FIFO empty (FIFOLevel = 0)'" "0,1" newline rbitfld.long 0x0 10. "TRNG_STARTUPFAIL,'Start-up test failure'" "0,1" newline rbitfld.long 0x0 9. "TRNG_ALMINT,'AIS31 noise alarm interrupt status'" "0,1" newline bitfld.long 0x0 8. "TRNG_PREINT,'AIS31 preliminary noise alarm interrupt status'" "0,1" newline bitfld.long 0x0 7. "TRNG_FULLINT,'FIFO full status'" "0,1" newline bitfld.long 0x0 5. "TRNG_PROPFAIL,'NIST-800-90B adaptive Proportion Test (1024-sample window) interrupt status'" "0,1" newline bitfld.long 0x0 4. "TRNG_REPFAIL,'NIST-800-90B repetition Count Test interrupt status'" "0,1" newline rbitfld.long 0x0 1.--3. "TRNG_STATE,'State of the control FSM (see Figure 7-1) 000: Reset 001: Startup 010: Idle (Rings On) 011: Idle (Rings Off) 100: Fill FIFO 101: Error 110: Unused 111: Unused'" "Reset,Startup,?,?,?,?,?,?" newline rbitfld.long 0x0 0. "TRNG_TESTDATABUSY,'High when data written to TestData register is being processed. (see section 4.7)'" "0,1" line.long 0x4 "TRNG_INITWAITVAL,TRNG_INITWAITVAL" newline hexmask.long.word 0x4 0.--15. 1. "TRNG_INITWAITVAL,'Number of clock cycles to wait before sampling data from the noise source. All 16 bits are reset high (reset value = 0xFFFF).'" line.long 0x8 "TRNG_DISABLEOSC,TRNG_DISABLEOSC" hexmask.long 0x8 0.--31. 1. "TRNG_DISABLEOS0,'Disable oscillator rings #0 to #31'" line.long 0xC "TRNG_DISABLEOSC1,TRNG_DISABLEOSC1" hexmask.long 0xC 0.--31. 1. "TRNG_DISABLEOS1,'Disable oscillator rings #32 to #63'" line.long 0x10 "TRNG_SWOFFTMRVAL,TRNG_SWOFFTMRVAL" newline hexmask.long.word 0x10 0.--15. 1. "TRNG_SWOFFTMRVAL,'Number of clk cycles to wait before stopping the rings after the FIFO is full. '" line.long 0x14 "TRNG_CLKDIV,TRNG_CLKDIV" newline hexmask.long.byte 0x14 0.--7. 1. "TRNG_CLKDIV,'Sample clock divider. The frequency at which the outputs of the rings are sampled is given by Fs = Fpclk/(ClkDiv + 1).'" repeat 3. (list 0x0 0x1 0x2 )(list 0x0 0x4 0x8 ) group.long ($2+0x8148)++0x3 line.long 0x0 "TRNG_AIS31CONF$1,TRNG_AIS31CONF0" hexmask.long.word 0x0 16.--31. 1. "TRNG_ONLINETHRESH,'Online threshold'" newline hexmask.long.word 0x0 0.--15. 1. "TRNG_STARTUPTHRESH,'Start-up test threshold'" repeat.end group.long 0x8154++0x3 line.long 0x0 "TRNG_AIS31STATUS,TRNG_AIS31STATUS" newline rbitfld.long 0x0 17. "TRNG_PRELIMNOISEALARMREP,TRNG_PRELIMNOISEALARMREP" "0,1" newline rbitfld.long 0x0 16. "TRNG_PRELIMNOISEALARMRNG,'Last preliminary noise alarm occurred due to history value out of range'" "0,1" newline hexmask.long.word 0x0 0.--15. 1. "TRNG_NUMPRELIMALARMS,'Number of preliminary noise alarms since counter was last cleared'" rgroup.long 0x8158++0x3 line.long 0x0 "TRNG_HWCONF,TRNG_HWCONF" newline bitfld.long 0x0 9. "TRNG_AIS31FULL,'Generic g_AIS31Full value'" "0,1" newline bitfld.long 0x0 8. "TRNG_AIS31,'Generic g_AIS31 value'" "0,1" newline hexmask.long.byte 0x0 0.--7. 1. "TRNG_NUMBOFRINGS,'Generic g_NumRings value'" tree.end tree "CE2_REG" base ad:0xF4000000 rgroup.long 0x0++0x7 line.long 0x0 "CE0_STAT,CE0 working status" newline bitfld.long 0x0 5. "PKE_BUSY,1: PKE is busy 0:PKE is idle" "?,PKE is busy 0:PKE is idle" newline bitfld.long 0x0 4. "GENKEY_BUSY,1. CE0 generate key function is busy" "0,1" newline bitfld.long 0x0 3. "HASH_BUSY,1: the HASH of CE0 is busy" "?,the HASH of CE0 is busy" newline bitfld.long 0x0 2. "CIPHER_BUSY,1 the CIPHER of CE0 is busy" "0,1" newline bitfld.long 0x0 1. "GETRNDNUM_BUSY,1: get random number function of CE0 is busy" "?,get random number function of CE0 is busy" newline bitfld.long 0x0 0. "DMA_BUSY,1: the DMA of CE0 is busy 0: the DMA of CE0 is idle" "the DMA of CE0 is idle,the DMA of CE0 is busy" line.long 0x4 "CE0_ERRSTAT,CE0 error status" newline hexmask.long.byte 0x4 24.--27. 1. "SKC_ERR_STAT,'the error status of skc sequencer the bit 0 ~ 3 are [sram wr err] [ rand number fetch err] [ secure violation occurs] [reserved]'" newline bitfld.long 0x4 19. "SSRAM_ERR_STAT,'the error status of CE sram" "0,1" newline bitfld.long 0x4 16.--18. "DMA_ERR_STAT,'the error status of dma sequencer the bit of 0 -2 are [sram_rw_err] [wdma ch err] [rdma ch err]'" "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x4 8.--13. 1. "CIPHER_ERR_STAT,'the error status of cipher sequencer the bit 0 - 4 are [key_port_err] [rdma_ch_err] [wdma_ch_err] [sram_wr_err] [sram_rd_err] [decryption from secure to non-secure]'" newline hexmask.long.byte 0x4 0.--3. 1. "HASH_ERR_STAT,'the error status of hash sequencer the bit 0 ~ 3 are [sram_wr_err] [sram rd err] [rdma_err] [wdma err]'" group.long 0xC++0x3F line.long 0x0 "CE0_CIPHER_CTRL,CE0 cipher control register" bitfld.long 0x0 31. "CIPHER_HEADER_SAVE,1 the header will be saved into dst memory 0: header will not be saved" "header will not be saved,?" newline bitfld.long 0x0 28.--29. "CIPHER_KEY2TYPE,key 2 type 10: input keyport 00: secure sram public area 01: secure area others: reserved" "secure sram public area,secure area others: reserved,?,?" newline bitfld.long 0x0 25.--26. "CIPHER_KEYTYPE,key type 10: input keyport 00: secure sram public area 01: secure area others: reserved" "secure sram public area,secure area others: reserved,?,?" newline hexmask.long.word 0x0 16.--24. 1. "AESMODE,'AES mode XTS : 010000000 ECB : 000000001 CBC : 000000010 CTR : 000000100 CFB : 000001000 OFB : 000010000 CCM : 000100000 GCM : 001000000 XTS : 010000000 CMAC: 100000000'" newline bitfld.long 0x0 13. "CIPHER_SAVE,0: normal mode last part of the message 1: operation context will be saved at the end of operation" "normal mode last part of the message,operation context will be saved at the end of.." newline bitfld.long 0x0 12. "CIPHER_LOAD,0 : normal mode first start of the message 1: operation restart from previously save context" "normal mode first start of the message,operation restart from previously save context" newline bitfld.long 0x0 11. "CIPHER_DECKEYCAL,0 use the input key for decryption operations 1: use the pre-calculation of the key is done before" "?,use the pre-calculation of the key is done before" newline bitfld.long 0x0 9.--10. "CIPHER_KEYSIZE,key size 00: 128bit key 01: 256 bit key 10: 192bit key 11: reserved" "0,1,2,3" newline bitfld.long 0x0 8. "CIPHERMODE,0 encryption 1 decryption" "0,1" newline bitfld.long 0x0 0. "CIPHER_GO,'write 1 to this bit will start the cipher operation'" "0,1" line.long 0x4 "CE0_CIPHER_HEADER_LEN,CE0 cipher header length register" hexmask.long 0x4 0.--31. 1. "CIPHER_HEADER_LEN,'cipher data header length in bytes'" line.long 0x8 "CE0_CIPHER_KEY_ADDR,CE0 cipher key address" hexmask.long.word 0x8 16.--31. 1. "CIPHER_KEY2_ADDR,key2 address in secure SRAM or keyport" newline hexmask.long.word 0x8 0.--15. 1. "CIPHER_KEY_ADDR,CIPHER_KEY_ADDR address in secure SRAM or keyport" line.long 0xC "CE0_CIPHER_SRC_ADDR,CE0 cipher source data address register" hexmask.long 0xC 0.--31. 1. "CIPHER_SRC_ADDR,cipher data source address in bytes" line.long 0x10 "CE0_CIPHER_SRC_ADDR_H,CE0 cipher source data address high part" newline bitfld.long 0x10 8.--10. "CIPHER_SRC_TYPE,011: CE SRAM Secure AREA 001:CE SRAM public area 000:external memories other: reserved" "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x10 0.--7. 1. "CIPHER_SRC_ADDR_H,the high part of CE0 cipher source address" line.long 0x14 "CE0_CIPHER_DST_ADDR,CE0 cipher results data address" hexmask.long 0x14 0.--31. 1. "CIPHER_DST_ADDR,CE0 cipher data destination address" line.long 0x18 "CE0_CIPHER_DST_ADDR_H,CE0 cipher results data address high part" newline bitfld.long 0x18 8.--10. "CIPHER_DST_TYPE,011: CE SRAM Secure AREA 001:CE SRAM public area 000:external memories other: reserved" "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x18 0.--7. 1. "CIPHER_DST_ADDR_H,CE0 cipher data destination address" line.long 0x1C "CE0_CIPHER_IV_CONTEXT_ADDR,CE0 cipher IV and context address register" hexmask.long.word 0x1C 16.--31. 1. "CIPHER_CONTEXT_ADDR,CIPHER context storage address the context is always stored into SRAM secure area" newline hexmask.long.word 0x1C 0.--15. 1. "CIPHER_IV_ADDR,CIPHER iv storage address the iv is always stored into SRAM secure area" line.long 0x20 "CE0_CIPHER_PAYLOAD_LEN,CE0 cipher payload length(calcuation length)" hexmask.long 0x20 0.--31. 1. "CIPHER_PAYLOAD_LEN,CIPHER_PAYLOAD_LEN including the header length in byte" line.long 0x24 "CE0_HASH_CTRL,CE0 hash control register" newline bitfld.long 0x24 24. "HASH_HMAC_EN,1: hmac is enabled 0: hmac is disabled" "hmac is disabled,hmac is enabled" newline bitfld.long 0x24 19. "HASH_KEY,1 need to load key 0 donot load key" "0,1" newline bitfld.long 0x24 18. "HASH_INIT_SECURE,1 load IV from secure area 0: load IV from public area" "load IV from public area,?" newline bitfld.long 0x24 17. "HASH_INIT,1 load IV for the hash 0 not load initial vector" "0,1" newline bitfld.long 0x24 16. "HASH_SHAUPDATE,0 final SHA224 output 7 words and SHA384 output 6 words 1: update SHA224/384 output 8 words please don't use this feature in hmac mode" "?,update SHA224/384 output 8 words please don't.." newline bitfld.long 0x24 15. "HASH_PADDINGEN,0: bypass padding logic 1: use hw padding logic" "bypass padding logic,use hw padding logic" newline hexmask.long.byte 0x24 8.--14. 1. "HASH_MODE,0000001 MD5 0000010 SHA1 0000100 SHA224 0001000 SHA256 0010000 SHA384 0100000 SHA512 1000000 SM3" newline bitfld.long 0x24 0. "HASH_GO,HASH Calculation start" "0,1" line.long 0x28 "CE0_HASH_KEYIV_ADDR,CE0 hash key and IV register" hexmask.long.word 0x28 16.--31. 1. "HASH_KEY_ADDR,HASH_KEY address" newline hexmask.long.word 0x28 0.--15. 1. "HASH_IV_ADDR,HASH initial vection address" line.long 0x2C "CE0_HMAC_KEY_CTRL,CE0 HMAC key control register" newline bitfld.long 0x2C 16.--17. "HMAC_KEY_TYPE,10 from key interface 01: from SRAM secure area 00 from SRAM public area" "?,from SRAM secure area 00 from SRAM public area,?,?" newline hexmask.long.word 0x2C 0.--15. 1. "HMAC_KEY_LEN,CE0 hash key length in CE SRAM" line.long 0x30 "CE0_HASH_CALC_LEN,CE0 hash calculation length register" hexmask.long 0x30 0.--31. 1. "HASH_CALC_LEN,CE0 hash calculation length in bytes" line.long 0x34 "CE0_HASH_SRC_ADDR,CE0 hash source data register" hexmask.long 0x34 0.--31. 1. "HASH_SRC_ADDR,CE0 HASH SRC ADDR" line.long 0x38 "CE0_HASH_SRC_ADDR_H,CE0 hash source data register high part" newline bitfld.long 0x38 8.--10. "HASH_SRC_TYPE,000: external memory 001: CE SRAM public area 011 CE sram secure area 1xx: SKC key interface space" "external memory,CE SRAM public area 011 CE sram secure area 1xx:..,?,?,?,?,?,?" newline hexmask.long.byte 0x38 0.--7. 1. "HASH_SRC_ADDR_H,the high part of CE0 hash src address" line.long 0x3C "CE0_HASH_DST_ADDR,CE0 hash results address" newline bitfld.long 0x3C 16.--18. "HASH_DST_TYPE,001 internal secure SRAM 001 public area in secure ram 1xx key interface" "0,1,2,3,4,5,6,7" newline hexmask.long.word 0x3C 0.--15. 1. "HASH_DST_ADDR,the dst address in secure SRAM" group.long 0x50++0x17 line.long 0x0 "CE0_DMA_CTRL,CE0 DMA control register" newline bitfld.long 0x0 10. "DMA_DONEINTEN,1 the interrupt will be generated if the DMA operation is done" "0,1" newline rbitfld.long 0x0 9. "DMA_CMDFIFO_FULL,cmd fifo is full" "0,1" newline rbitfld.long 0x0 8. "DMA_CMDFIFO_EMPTY,cmd fifo is empty" "0,1" newline bitfld.long 0x0 0. "DMA_GO,write 1 to this register start CE0 DMA operation" "0,1" line.long 0x4 "CE0_DMA_SRC_ADDR,CE0 DMA source data address register" hexmask.long 0x4 0.--31. 1. "DMA_SRC_ADDR,CE0 dma source addr" line.long 0x8 "CE0_DMA_SRC_ADDR_H,CE0 DMA source data address register high part" newline bitfld.long 0x8 8.--10. "DMA_SRC_TYPE,011: CE SRAM Secure AREA 001:CE SRAM public area 000:external memories other: reserved" "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x8 0.--7. 1. "DMA_SRC_ADDR_H,CE0 dma source addr high part" line.long 0xC "CE0_DMA_DST_ADDR,CE0 DMA destination data address" hexmask.long 0xC 0.--31. 1. "DMA_DST_ADDR,CE1 DMA DST ADDR" line.long 0x10 "CE0_DMA_DST_ADDR_H,CE0 DMA destination data address high part" newline bitfld.long 0x10 8.--10. "DMA_DST_TYPE,011: CE SRAM Secure AREA 001:CE SRAM public area 000:external memories other: reserved" "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x10 0.--7. 1. "DMA_DST_ADDR_H,CE1 DMA DST ADDR high part" line.long 0x14 "CE0_DMA_LEN,CE0 dma transfer data length" newline hexmask.long.word 0x14 0.--15. 1. "DMA_LEN,DMA transfer length in byte" group.long 0x80++0xB line.long 0x0 "CE0_PK_POINTERREG,CE0 PKE operand point register" newline hexmask.long.byte 0x0 24.--27. 1. "PK_OPPTRN,'When executing primitive arithmetic operations" newline hexmask.long.byte 0x0 16.--19. 1. "PK_OPPTRC,'When executing primitive arithmetic operations" newline hexmask.long.byte 0x0 8.--11. 1. "PK_OPPTRB,'When executing primitive arithmetic operations" newline hexmask.long.byte 0x0 0.--3. 1. "PK_OPPTRA,'When executing primitive arithmetic operations" line.long 0x4 "CE0_PK_COMMANDREG,CE0 PKE command register" bitfld.long 0x4 31. "PK_CALCR2,PK_CALCR2" "0,1" newline bitfld.long 0x4 30. "PK_FLAGB,'B See routine description'" "0,1" newline bitfld.long 0x4 29. "PK_FLAGA,'A See routine description'" "0,1" newline bitfld.long 0x4 28. "PK_SWAP,'bytes Swap the bytes on AHB interface: '0': Native format (little endian) '1': Byte swapped (big endian) See also section 4.2.1. This bit must be programmed before writing/reading any data in data memory.'" "0,1" newline bitfld.long 0x4 27. "PK_BUFFER,PK_BUFFER" "0,1" newline bitfld.long 0x4 26. "PK_EDWARDS,'Enable Edwards curve (see routine description)'" "0,1" newline bitfld.long 0x4 25. "PK_RANDPROJ,'Enable randomization of projective coordinates (counter-measure)'" "0,1" newline bitfld.long 0x4 24. "PK_RANDKE,'Enable randomization of exponent/scalar (counter-measure)'" "0,1" newline hexmask.long.byte 0x4 20.--23. 1. "PK_SELCURVE,'Enable accelerator for specific curve modulus: 0x0: No acceleration (default) 0x1: P256 0x2: P384 0x3: P521/E-521 0x4: P192 0x5: Curve25519/Ed25519 This field has no effect when the optional acceleration hardware is not included.'" newline hexmask.long.word 0x4 8.--18. 1. "PK_SIZE,'Of Operands (in data memory) This field defines the size (= number of bytes minus one) of the operands for the current operation. Possible values are limited by the maximum supported operand size. Examples: 0x014 -> ECC on curve K-163 0x01F ->.." newline bitfld.long 0x4 7. "PK_FIELD,''0': Field is GF(p) '1': Field is GF(2m)'" "0,1" newline hexmask.long.byte 0x4 0.--6. 1. "PK_TYPE,'of operation This field defines the operation to be performed. See table below for details.'" line.long 0x8 "CE0_PKE_CTRL,CE0_PKE_CTRL" newline bitfld.long 0x8 2. "PKE_SOFT_RST,'Writing a 1 to this bit will reset the pke_seq logic'" "0,1" newline bitfld.long 0x8 1. "PK_CLRMEMAFTEROP,'Writing a 1 to this bit will make the pke to clear its memories after all operations are complete'" "0,1" newline bitfld.long 0x8 0. "PKE_GO,'Writing a '1' starts the processing.'" "0,1" rgroup.long 0x8C++0x3 line.long 0x0 "CE0_PK_STATUSREG,CE0_PK_STATUSREG" newline bitfld.long 0x0 17. "PK_INTERRUPT,'status This bit reflects the IRQ output value. It is set to '1' when the operation is finished. It is cleared when the CPU writes the bit 1 of Control Register.'" "0,1" newline bitfld.long 0x0 16. "PK_BUSY,'This bit reflects the BUSY output value. It is set to '1' when the operation starts and it is cleared when the operation is finished.'" "0,1" newline bitfld.long 0x0 13. "PK_NOTQUADRATICRESIDUE,PK_NOTQUADRATICRESIDUE" "0,1" newline bitfld.long 0x0 12. "PK_COMPOSITE,PK_COMPOSITE" "0,1" newline bitfld.long 0x0 11. "PK_NOTINVERTIBLE,PK_NOTINVERTIBLE" "0,1" newline bitfld.long 0x0 10. "PK_PARAM_AB_NOTVALID,PK_PARAM_AB_NOTVALID" "0,1" newline bitfld.long 0x0 9. "PK_SIGNATURE_NOTVALID,PK_SIGNATURE_NOTVALID" "0,1" newline bitfld.long 0x0 8. "PK_NOTIMPLEMENTED,PK_NOTIMPLEMENTED" "0,1" newline bitfld.long 0x0 7. "PK_PARAM_N_NOTVALID,PK_PARAM_N_NOTVALID" "0,1" newline bitfld.long 0x0 6. "PK_COUPLE_NOTVALID,PK_COUPLE_NOTVALID" "0,1" newline bitfld.long 0x0 5. "PK_POINT_PX_ATINFINITY,PK_POINT_PX_ATINFINITY" "0,1" newline bitfld.long 0x0 4. "PK_POINT_PX_NOTONCURVE,PK_POINT_PX_NOTONCURVE" "0,1" newline hexmask.long.byte 0x0 0.--3. 1. "PK_FAIL_ADDRESS,'These bits indicate which data location generated the error flag. They are not available for all error flags.'" group.long 0x94++0x3 line.long 0x0 "CE0_PK_TIMER,CE0_PK_TIMER" hexmask.long 0x0 0.--31. 1. "PK_TIMER,'The timer counts the number of clock cycles when the PK engine is busy. It is not cleared automatically. It can be written by software (when the PK is idle). The register is updated at the end of every operation (reading it when the PK engine.." rgroup.long 0x98++0x3 line.long 0x0 "CE0_PK_HWCONFIGREG,CE0_PK_HWCONFIGREG" bitfld.long 0x0 31. "PK_DISABLECM,'State of DisableCM input (high when counter-measures are disabled)'" "0,1" newline bitfld.long 0x0 24. "PK_25519,'Support Curve25519/Ed25519 acceleration'" "0,1" newline bitfld.long 0x0 23. "PK_P192,'Support ECC P192 acceleration'" "0,1" newline bitfld.long 0x0 22. "PK_P521,'Support ECC P521 acceleration'" "0,1" newline bitfld.long 0x0 21. "PK_P384,'Support ECC P384 acceleration'" "0,1" newline bitfld.long 0x0 20. "PK_P256,'Support ECC P256 acceleration'" "0,1" newline bitfld.long 0x0 18.--19. "RESERVED,'unused'" "0,1,2,3" newline bitfld.long 0x0 17. "PK_BINARYFIELD,'Support binary field'" "0,1" newline bitfld.long 0x0 16. "PK_PRIMEFIELD,'Support prime field'" "0,1" newline hexmask.long.byte 0x0 12.--15. 1. "PK_NBMULT,'Number of multipliers: 0x0: 1 multiplier 0x1: 4 multipliers 0x2: 16 multipliers 0x4: 64 multipliers 0x8: 256 multipliers'" newline hexmask.long.word 0x0 0.--11. 1. "PK_MAXOPSIZE,'Maximum operand size (number of bytes) 4096 bytes'" group.long 0x9C++0xB line.long 0x0 "CE0_PK_RESULTS_CTRL,CE0_PK_RESULTS_CTRL" hexmask.long.word 0x0 16.--31. 1. "PKE_RESULTS_OP_LEN,'pke results each operand length in bytes'" newline hexmask.long.word 0x0 0.--15. 1. "PKE_RESULTS_OP_SELECT,'pke results output select each bit correspnding to the operand position of the pke data memory'" line.long 0x4 "CE0_PK_RESULTS_DST_ADDR,CE0_PK_RESULTS_DST_ADDR" hexmask.long 0x4 0.--31. 1. "PKE_RESULTS_DST_ADDR,'pke results dma dst address low 32bit'" line.long 0x8 "CE0_PK_RESULTS_DST_ADDR_H,CE0_PK_RESULTS_DST_ADDR_H" newline bitfld.long 0x8 8.--10. "PKE_RESULTS_DST_TYPE,'pke results dma dst data type 011: CE SRAM Secure AREA 001:CE SRAM public area 000:external memories other: reserved'" "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x8 0.--7. 1. "PKE_RESULTS_DST_ADDR_H,'pke results dma dst address high 8bit'" rgroup.long 0x100++0x3 line.long 0x0 "CE0_TRNG_STATUS,CE0 TRNG status register" newline bitfld.long 0x0 1. "RNG_SEQ_RUNNING,'1: the rng sequencer is running currently 0: rng sequencer is in idle status'" "rng sequencer is in idle status',the rng sequencer is running currently" newline bitfld.long 0x0 0. "RNG_READY,'1: the value in the random number register of CE0 is valid" "?,the value in the random number register of CE0.." repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) rgroup.long ($2+0x104)++0x3 line.long 0x0 "CE0_TRNG_NUM$1,CE0_TRNG_NUM0" hexmask.long 0x0 0.--31. 1. "TRNG_NUM0,CE0 the random number0 value" repeat.end rgroup.long 0x114++0x3 line.long 0x0 "CE0_HRNG_NUM,CE0_HRNG_NUM" hexmask.long 0x0 0.--31. 1. "HRNG_NUM,CE0 the hybird random number value" group.long 0x120++0xB line.long 0x0 "CE0_SKC_CTRL,CE0 SKC control register" newline bitfld.long 0x0 8.--10. "SKC_CMD,the command of SKC 001: generate random number 010: erase key contrainer" "?,generate random number,?,?,?,?,?,?" newline bitfld.long 0x0 0. "SKC_GO,CE0 secure FSM start trigger" "0,1" line.long 0x4 "CE0_SKC_RNG_ADDR,CE0 SKC random number register" newline bitfld.long 0x4 24. "SKC_RNG_SECURE,CE0 1: random number generated to secure area 0 : in public area" "in public area,random number generated to secure area" newline hexmask.long.byte 0x4 16.--22. 1. "SKC_RNG_LEN,'numbers of bits to generate into sram granularity is 256 bit'" newline hexmask.long.word 0x4 0.--12. 1. "SKC_RNG_ADDR,CE0 random number generation address in CE sram the address granularity is 8 bytes" line.long 0x8 "CE0_SKC_KEYBLOB_CTRL,CE0 SKC key blob control register" newline bitfld.long 0x8 0. "SKC_KEYBLOB_CTRL,CE0 key blob control 1: is key blob :0 : is the secret data" "?,is key blob :0 : is the secret data" group.long 0x140++0x3 line.long 0x0 "CE0_INTEN,CE0 interrupt enable register" newline bitfld.long 0x0 13. "DMA_FIFOERROR_INTEN,DMA fifo error interrupt" "0,1" newline bitfld.long 0x0 12. "PKE_INTEGRITY_ERROR_INTEN,ALGORITHM_INTEGRITY interrupt" "0,1" newline bitfld.long 0x0 11. "HASH_INTEGRITY_ERROR_INTEN,ALGORITHM_INTEGRITY_ERROR interrupt" "0,1" newline bitfld.long 0x0 10. "CIPHER_INTEGRITY_ERROR_INTEN,ALGORITHM_INTEGRITY_ERROR interrupt" "0,1" newline bitfld.long 0x0 9. "SKC_INTEGRITY_ERROR_INTEN,SKC_INTEGRITY_ERROR interrupt" "0,1" newline bitfld.long 0x0 8. "DMA_INTEGRITY_ERROR_INTEN,ALGORITHM_INTEGRITY interrupt" "0,1" newline bitfld.long 0x0 4. "PKE_DONE_INTEN,PKE_DONE interrupt" "0,1" newline bitfld.long 0x0 3. "HASH_DONE_INTEN,HASH_DONE interrupt" "0,1" newline bitfld.long 0x0 2. "CIPHER_DONE_INTEN,CIPHER_DONE_INTEN" "0,1" newline bitfld.long 0x0 1. "SKC_DONE_INTEN,KEYgen done interrupt enable" "0,1" newline bitfld.long 0x0 0. "DMA_DONE_INTEN,DMA_DONE interrupt" "0,1" rgroup.long 0x144++0x3 line.long 0x0 "CE0_INTSTAT,CE0 interrupt status register" newline bitfld.long 0x0 13. "DMA_FIFOERROR_INTSTAT,SSRAM_DMAFIFO error interrupt" "0,1" newline bitfld.long 0x0 12. "PKE_INTEGRITY_ERROR_INTSTAT,ALGORITHM_INTEGRITY interrupt" "0,1" newline bitfld.long 0x0 11. "HASH_INTEGRITY_ERROR_INTSTAT,ALGORITHM_INTEGRITY_ERROR interrupt" "0,1" newline bitfld.long 0x0 10. "CIPHER_INTEGRITY_ERROR_INTSTAT,ALGORITHM_INTEGRITY_ERROR interrupt" "0,1" newline bitfld.long 0x0 9. "SKC_INTEGRITY_ERROR_INTSTAT,SKC_INTEGRITY_ERROR interrupt" "0,1" newline bitfld.long 0x0 8. "DMA_INTEGRITY_ERROR_INTSTAT,ALGORITHM_INTEGRITY interrupt" "0,1" newline bitfld.long 0x0 4. "PKE_DONE_INTSTAT,PKE_DONE interrupt" "0,1" newline bitfld.long 0x0 3. "HASH_DONE_INTSTAT,HASH_DONE interrupt" "0,1" newline bitfld.long 0x0 2. "CIPHER_DONE_INTSTAT,CIPHER_DONE_INTSTATE" "0,1" newline bitfld.long 0x0 1. "SKC_DONE_INTSTAT,KEYgen done interrupt enable" "0,1" newline bitfld.long 0x0 0. "DMA_DONE_INTSTAT,DMA_DONE interrupt" "0,1" group.long 0x148++0x3 line.long 0x0 "CE0_INTCLR,CE0 interrupt clear register" newline bitfld.long 0x0 13. "DMA_FIFOERROR_INTCLR,SSRAM_DMAFIFO error interrupt" "0,1" newline bitfld.long 0x0 12. "PKE_INTEGRITY_ERROR_INTCLR,ALGORITHM_INTEGRITY interrupt" "0,1" newline bitfld.long 0x0 11. "HASH_INTEGRITY_ERROR_INTCLR,ALGORITHM_INTEGRITY_ERROR interrupt" "0,1" newline bitfld.long 0x0 10. "CIPHER_INTEGRITY_ERROR_INTCLR,ALGORITHM_INTEGRITY_ERROR interrupt" "0,1" newline bitfld.long 0x0 9. "SKC_INTEGRITY_ERROR_INTCLR,SKC_INTEGRITY_ERROR interrupt" "0,1" newline bitfld.long 0x0 8. "DMA_INTEGRITY_ERROR_INTCLR,ALGORITHM_INTEGRITY interrupt" "0,1" newline bitfld.long 0x0 4. "PKE_DONE_INTCLR,PKE_DONE interrupt" "0,1" newline bitfld.long 0x0 3. "HASH_DONE_INTCLR,HASH_DONE interrupt" "0,1" newline bitfld.long 0x0 2. "CIPHER_DONE_INTCLR,CIPHER_DONE_INTCLRE" "0,1" newline bitfld.long 0x0 1. "SKC_DONE_INTCLR,KEYgen done interrupt enable" "0,1" newline bitfld.long 0x0 0. "DMA_DONE_INTCLR,DMA_DONE interrupt" "0,1" group.long 0x8000++0x7 line.long 0x0 "SECURE_CTRL,CE secure violation control" hexmask.long.byte 0x0 24.--31. 1. "CE_SRAM_SIZE_VIO,the CE sram size size is not correct" newline rbitfld.long 0x0 17. "SRAM_SIZE_TOTAL_VIO,the CE sram size total size is not correct" "0,1" newline bitfld.long 0x0 16. "PKE_CM_DISABLE,'1: disable the PKE counter measure 0 : enable the counter measure'" "enable the counter measure',disable the PKE counter measure" newline hexmask.long.byte 0x0 8.--15. 1. "SECURE_VIOLATION_STATUS,'secure violation input status'" newline hexmask.long.byte 0x0 0.--7. 1. "SECURE_VIOLATION_ENABLE,'the corresponding bits enable the secure violation source'" line.long 0x4 "SESRAM_SIZE,Secure SRAM size for CE0" newline hexmask.long.byte 0x4 0.--6. 1. "CE0_RAM_SIZE,the CE sram size" group.long 0x800C++0x3 line.long 0x0 "SESRAM_SASIZE,secure SRAM secure area size" newline hexmask.long.byte 0x0 0.--6. 1. "CE0_RAM_SASIZE,the secure area sram size" group.long 0x8014++0x7 line.long 0x0 "VCE_SINATURE_MASK,VCE SIGNAGURE generation mask" hexmask.long 0x0 0.--31. 1. "VCE_SINATURE_MASK,'the mask for the vce to generate signature from id'" line.long 0x4 "VCE_SINATURE_MASK_HIGH,VCE_SINATURE_MASK_HIGH" newline hexmask.long.byte 0x4 0.--7. 1. "VCE_SINATURE_MASK_HIGH,'the mask for the vce to generate signature from id high part'" group.long 0x8020++0x7 line.long 0x0 "HRNG_CTRL,HRNG_CTRL" newline hexmask.long.byte 0x0 8.--11. 1. "HRNG_LOAD_CNT,'the counter to control the frequency for the hrng LFSF load the feedback cycle'" newline bitfld.long 0x0 0. "NOISE_ENABLE,'1: enable the noise source for the hrng 0: disable the noise source'" "disable the noise source',enable the noise source for the hrng" line.long 0x4 "HRNG_SEED_CTRL,HRNG_SEED_CTRL" bitfld.long 0x4 31. "LOAD_SEED_GO,'write 1 to this bit will load the seed into the hrng auto clear'" "0,1" newline hexmask.long 0x4 0.--30. 1. "SEED_NUM,'the seed number" group.long 0x8030++0x3 line.long 0x0 "TRNG_CTRL,TRNG_CTRL" newline bitfld.long 0x0 0. "CE_TRNG_SEQ_GO,'write this bit will start the trng sequencer to fetch the random number for all VCEs'" "0,1" group.long 0x8050++0x3 line.long 0x0 "DEBUG_BUS_SEL,DEBUG_BUS_SEL" newline hexmask.long.word 0x0 0.--15. 1. "DEBUG_BUS_SEL,'debug bus select'" rgroup.long 0x8054++0x3 line.long 0x0 "DEBUG_BUS_STATUS,DEBUG_BUS_STATUS" hexmask.long 0x0 0.--31. 1. "DEBUG_BUS_STATUS,'debug bus output'" group.long 0x8100++0x3 line.long 0x0 "TRNG_CONTROL,TRNG_CONTROL" newline bitfld.long 0x0 20. "TRNG_FIFOWRITESTARTUP,'Enable write of the samples in the FIFO during start-up'" "0,1" newline hexmask.long.byte 0x0 16.--19. 1. "TRNG_NB128BITBLOCKS,'Number of 128 bit blocks used in AES-CBCMAC post-processing. This value cannot be zero.'" newline bitfld.long 0x0 15. "TRNG_AIS31TESTSEL,'Select input to the AIS31 test module 0: Before conditioning 1: After conditioning'" "Before conditioning,After conditioning'" newline bitfld.long 0x0 14. "TRNG_HEALTHTESTSEL,'Select input to health test module 0: Before conditioning 1: After conditioning'" "Before conditioning,After conditioning'" newline bitfld.long 0x0 13. "TRNG_AIS31BYPASS,'Bypass AIS31 tests such that the results of the start-up and online tests do not affect the FSM state'" "0,1" newline bitfld.long 0x0 12. "TRNG_HEALTHTESTBYPASS,'Bypass NIST tests such that the results of the start-up and online test do not affect the FSM state'" "0,1" newline bitfld.long 0x0 11. "TRNG_FORCERUN,'Force oscillators to run when FIFO is full'" "0,1" newline bitfld.long 0x0 10. "TRNG_INTENALM,'Interrupt enable for AIS31 noise alarm'" "0,1" newline bitfld.long 0x0 9. "TRNG_INTENPRE,'Interrupt enable for AIS31 preliminary noise alarm'" "0,1" newline bitfld.long 0x0 8. "TRNG_SOFTRESET,'Software reset 0: Normal mode 1: The continuous test" "Normal mode,The continuous test" newline bitfld.long 0x0 7. "TRNG_INTENFULL,'Interrupt enable for FIFO full'" "0,1" newline bitfld.long 0x0 5. "TRNG_INTENPROP,'Interrupt enable for Adaptive Proportion Test failure (1024-sample window)'" "0,1" newline bitfld.long 0x0 4. "TRNG_INTENREP,'Interrupt enable for Repetition Count Test failure'" "0,1" newline bitfld.long 0x0 3. "TRNG_CONDBYPASS,'0: the conditioning function is used (normal mode) 1: the conditioning function is bypassed (to observe entropy source directly).'" "the conditioning function is used,the conditioning function is bypassed" newline bitfld.long 0x0 2. "TRNG_TESTEN,'Select input for conditioning function and continuous tests: 0: Noise source (normal mode) 1: Test data register (test mode)'" "Noise source,Test data register" newline bitfld.long 0x0 1. "TRNG_LFSREN,TRNG_LFSREN" "0,1" newline bitfld.long 0x0 0. "TRNG_ENABLE,'Enable the NDRNG.'" "0,1" rgroup.long 0x8104++0xB line.long 0x0 "TRNG_FIFOLEVEL,TRNG_FIFOLEVEL" hexmask.long 0x0 0.--31. 1. "TRNG_FIFOLEVEL,'Number of 32 bits words of random available in the FIFO. Any write to this register clears the FullInt flag in the Status register.'" line.long 0x4 "TRNG_FIFOTHD,TRNG_FIFOTHD" hexmask.long 0x4 0.--31. 1. "TRNG_FIFOTHD,'FIFO level below which the module leaves the idle state to refill the fifo" line.long 0x8 "TRNG_FIFODEPTH,TRNG_FIFODEPTH" hexmask.long 0x8 0.--31. 1. "TRNG_FIFODEPTH,'Depth Maximum number of 32 bits words that can be stored in the FIFO: 2g_fifodepth.'" group.long 0x8110++0xF line.long 0x0 "TRNG_KEY0REG,TRNG_KEY0REG" hexmask.long 0x0 0.--31. 1. "TRNG_KEY0REG,'Key (MSB)'" line.long 0x4 "TRNG_KEY1REG,TRNG_KEY1REG" hexmask.long 0x4 0.--31. 1. "TRNG_KEY1REG,'Key'" line.long 0x8 "TRNG_KEY2REG,TRNG_KEY2REG" hexmask.long 0x8 0.--31. 1. "TRNG_KEY2REG,'Key'" line.long 0xC "TRNG_KEY3REG,TRNG_KEY3REG" hexmask.long 0xC 0.--31. 1. "TRNG_KEY3REG,'Key (LSB)'" wgroup.long 0x8120++0x3 line.long 0x0 "TRNG_TESTDATA,TRNG_TESTDATA" hexmask.long 0x0 0.--31. 1. "TRNG_TESTDATA,'feed known data to the conditioning function or to the continous tests.'" group.long 0x8124++0x7 line.long 0x0 "TRNG_REPTHRESREG,TRNG_REPTHRESREG" hexmask.long 0x0 0.--31. 1. "TRNG_REPTHRESREG,'Repetition Test Count Cut-Off value'" line.long 0x4 "TRNG_PROPTHRESREG,TRNG_PROPTHRESREG" hexmask.long 0x4 0.--31. 1. "TRNG_PROPTHRESREG,'Adaptive Proportion Test (1024-sample window) Cut-Off value'" group.long 0x8130++0x17 line.long 0x0 "TRNG_STATUS,TRNG_STATUS" newline bitfld.long 0x0 11. "TRNG_FIFOACCFAIL,'Set when a FIFO data read is performed while the NDRNG is disabled AND has its FIFO empty (FIFOLevel = 0)'" "0,1" newline rbitfld.long 0x0 10. "TRNG_STARTUPFAIL,'Start-up test failure'" "0,1" newline rbitfld.long 0x0 9. "TRNG_ALMINT,'AIS31 noise alarm interrupt status'" "0,1" newline bitfld.long 0x0 8. "TRNG_PREINT,'AIS31 preliminary noise alarm interrupt status'" "0,1" newline bitfld.long 0x0 7. "TRNG_FULLINT,'FIFO full status'" "0,1" newline bitfld.long 0x0 5. "TRNG_PROPFAIL,'NIST-800-90B adaptive Proportion Test (1024-sample window) interrupt status'" "0,1" newline bitfld.long 0x0 4. "TRNG_REPFAIL,'NIST-800-90B repetition Count Test interrupt status'" "0,1" newline rbitfld.long 0x0 1.--3. "TRNG_STATE,'State of the control FSM (see Figure 7-1) 000: Reset 001: Startup 010: Idle (Rings On) 011: Idle (Rings Off) 100: Fill FIFO 101: Error 110: Unused 111: Unused'" "Reset,Startup,?,?,?,?,?,?" newline rbitfld.long 0x0 0. "TRNG_TESTDATABUSY,'High when data written to TestData register is being processed. (see section 4.7)'" "0,1" line.long 0x4 "TRNG_INITWAITVAL,TRNG_INITWAITVAL" newline hexmask.long.word 0x4 0.--15. 1. "TRNG_INITWAITVAL,'Number of clock cycles to wait before sampling data from the noise source. All 16 bits are reset high (reset value = 0xFFFF).'" line.long 0x8 "TRNG_DISABLEOSC,TRNG_DISABLEOSC" hexmask.long 0x8 0.--31. 1. "TRNG_DISABLEOS0,'Disable oscillator rings #0 to #31'" line.long 0xC "TRNG_DISABLEOSC1,TRNG_DISABLEOSC1" hexmask.long 0xC 0.--31. 1. "TRNG_DISABLEOS1,'Disable oscillator rings #32 to #63'" line.long 0x10 "TRNG_SWOFFTMRVAL,TRNG_SWOFFTMRVAL" newline hexmask.long.word 0x10 0.--15. 1. "TRNG_SWOFFTMRVAL,'Number of clk cycles to wait before stopping the rings after the FIFO is full. '" line.long 0x14 "TRNG_CLKDIV,TRNG_CLKDIV" newline hexmask.long.byte 0x14 0.--7. 1. "TRNG_CLKDIV,'Sample clock divider. The frequency at which the outputs of the rings are sampled is given by Fs = Fpclk/(ClkDiv + 1).'" repeat 3. (list 0x0 0x1 0x2 )(list 0x0 0x4 0x8 ) group.long ($2+0x8148)++0x3 line.long 0x0 "TRNG_AIS31CONF$1,TRNG_AIS31CONF0" hexmask.long.word 0x0 16.--31. 1. "TRNG_ONLINETHRESH,'Online threshold'" newline hexmask.long.word 0x0 0.--15. 1. "TRNG_STARTUPTHRESH,'Start-up test threshold'" repeat.end group.long 0x8154++0x3 line.long 0x0 "TRNG_AIS31STATUS,TRNG_AIS31STATUS" newline rbitfld.long 0x0 17. "TRNG_PRELIMNOISEALARMREP,TRNG_PRELIMNOISEALARMREP" "0,1" newline rbitfld.long 0x0 16. "TRNG_PRELIMNOISEALARMRNG,'Last preliminary noise alarm occurred due to history value out of range'" "0,1" newline hexmask.long.word 0x0 0.--15. 1. "TRNG_NUMPRELIMALARMS,'Number of preliminary noise alarms since counter was last cleared'" rgroup.long 0x8158++0x3 line.long 0x0 "TRNG_HWCONF,TRNG_HWCONF" newline bitfld.long 0x0 9. "TRNG_AIS31FULL,'Generic g_AIS31Full value'" "0,1" newline bitfld.long 0x0 8. "TRNG_AIS31,'Generic g_AIS31 value'" "0,1" newline hexmask.long.byte 0x0 0.--7. 1. "TRNG_NUMBOFRINGS,'Generic g_NumRings value'" tree.end elif (CORENAME()=="CORTEXA55") tree "CE1_REG" base ad:0x30340000 rgroup.long 0x0++0x7 line.long 0x0 "CE0_STAT,CE0 working status" newline bitfld.long 0x0 5. "PKE_BUSY,1: PKE is busy 0:PKE is idle" "?,PKE is busy 0:PKE is idle" newline bitfld.long 0x0 4. "GENKEY_BUSY,1. CE0 generate key function is busy" "0,1" newline bitfld.long 0x0 3. "HASH_BUSY,1: the HASH of CE0 is busy" "?,the HASH of CE0 is busy" newline bitfld.long 0x0 2. "CIPHER_BUSY,1 the CIPHER of CE0 is busy" "0,1" newline bitfld.long 0x0 1. "GETRNDNUM_BUSY,1: get random number function of CE0 is busy" "?,get random number function of CE0 is busy" newline bitfld.long 0x0 0. "DMA_BUSY,1: the DMA of CE0 is busy 0: the DMA of CE0 is idle" "the DMA of CE0 is idle,the DMA of CE0 is busy" line.long 0x4 "CE0_ERRSTAT,CE0 error status" newline hexmask.long.byte 0x4 24.--27. 1. "SKC_ERR_STAT,'the error status of skc sequencer the bit 0 ~ 3 are [sram wr err] [ rand number fetch err] [ secure violation occurs] [reserved]'" newline bitfld.long 0x4 19. "SSRAM_ERR_STAT,'the error status of CE sram" "0,1" newline bitfld.long 0x4 16.--18. "DMA_ERR_STAT,'the error status of dma sequencer the bit of 0 -2 are [sram_rw_err] [wdma ch err] [rdma ch err]'" "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x4 8.--13. 1. "CIPHER_ERR_STAT,'the error status of cipher sequencer the bit 0 - 4 are [key_port_err] [rdma_ch_err] [wdma_ch_err] [sram_wr_err] [sram_rd_err] [decryption from secure to non-secure]'" newline hexmask.long.byte 0x4 0.--3. 1. "HASH_ERR_STAT,'the error status of hash sequencer the bit 0 ~ 3 are [sram_wr_err] [sram rd err] [rdma_err] [wdma err]'" group.long 0xC++0x3F line.long 0x0 "CE0_CIPHER_CTRL,CE0 cipher control register" bitfld.long 0x0 31. "CIPHER_HEADER_SAVE,1 the header will be saved into dst memory 0: header will not be saved" "header will not be saved,?" newline bitfld.long 0x0 28.--29. "CIPHER_KEY2TYPE,key 2 type 10: input keyport 00: secure sram public area 01: secure area others: reserved" "secure sram public area,secure area others: reserved,?,?" newline bitfld.long 0x0 25.--26. "CIPHER_KEYTYPE,key type 10: input keyport 00: secure sram public area 01: secure area others: reserved" "secure sram public area,secure area others: reserved,?,?" newline hexmask.long.word 0x0 16.--24. 1. "AESMODE,'AES mode XTS : 010000000 ECB : 000000001 CBC : 000000010 CTR : 000000100 CFB : 000001000 OFB : 000010000 CCM : 000100000 GCM : 001000000 XTS : 010000000 CMAC: 100000000'" newline bitfld.long 0x0 13. "CIPHER_SAVE,0: normal mode last part of the message 1: operation context will be saved at the end of operation" "normal mode last part of the message,operation context will be saved at the end of.." newline bitfld.long 0x0 12. "CIPHER_LOAD,0 : normal mode first start of the message 1: operation restart from previously save context" "normal mode first start of the message,operation restart from previously save context" newline bitfld.long 0x0 11. "CIPHER_DECKEYCAL,0 use the input key for decryption operations 1: use the pre-calculation of the key is done before" "?,use the pre-calculation of the key is done before" newline bitfld.long 0x0 9.--10. "CIPHER_KEYSIZE,key size 00: 128bit key 01: 256 bit key 10: 192bit key 11: reserved" "0,1,2,3" newline bitfld.long 0x0 8. "CIPHERMODE,0 encryption 1 decryption" "0,1" newline bitfld.long 0x0 0. "CIPHER_GO,'write 1 to this bit will start the cipher operation'" "0,1" line.long 0x4 "CE0_CIPHER_HEADER_LEN,CE0 cipher header length register" hexmask.long 0x4 0.--31. 1. "CIPHER_HEADER_LEN,'cipher data header length in bytes'" line.long 0x8 "CE0_CIPHER_KEY_ADDR,CE0 cipher key address" hexmask.long.word 0x8 16.--31. 1. "CIPHER_KEY2_ADDR,key2 address in secure SRAM or keyport" newline hexmask.long.word 0x8 0.--15. 1. "CIPHER_KEY_ADDR,CIPHER_KEY_ADDR address in secure SRAM or keyport" line.long 0xC "CE0_CIPHER_SRC_ADDR,CE0 cipher source data address register" hexmask.long 0xC 0.--31. 1. "CIPHER_SRC_ADDR,cipher data source address in bytes" line.long 0x10 "CE0_CIPHER_SRC_ADDR_H,CE0 cipher source data address high part" newline bitfld.long 0x10 8.--10. "CIPHER_SRC_TYPE,011: CE SRAM Secure AREA 001:CE SRAM public area 000:external memories other: reserved" "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x10 0.--7. 1. "CIPHER_SRC_ADDR_H,the high part of CE0 cipher source address" line.long 0x14 "CE0_CIPHER_DST_ADDR,CE0 cipher results data address" hexmask.long 0x14 0.--31. 1. "CIPHER_DST_ADDR,CE0 cipher data destination address" line.long 0x18 "CE0_CIPHER_DST_ADDR_H,CE0 cipher results data address high part" newline bitfld.long 0x18 8.--10. "CIPHER_DST_TYPE,011: CE SRAM Secure AREA 001:CE SRAM public area 000:external memories other: reserved" "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x18 0.--7. 1. "CIPHER_DST_ADDR_H,CE0 cipher data destination address" line.long 0x1C "CE0_CIPHER_IV_CONTEXT_ADDR,CE0 cipher IV and context address register" hexmask.long.word 0x1C 16.--31. 1. "CIPHER_CONTEXT_ADDR,CIPHER context storage address the context is always stored into SRAM secure area" newline hexmask.long.word 0x1C 0.--15. 1. "CIPHER_IV_ADDR,CIPHER iv storage address the iv is always stored into SRAM secure area" line.long 0x20 "CE0_CIPHER_PAYLOAD_LEN,CE0 cipher payload length(calcuation length)" hexmask.long 0x20 0.--31. 1. "CIPHER_PAYLOAD_LEN,CIPHER_PAYLOAD_LEN including the header length in byte" line.long 0x24 "CE0_HASH_CTRL,CE0 hash control register" newline bitfld.long 0x24 24. "HASH_HMAC_EN,1: hmac is enabled 0: hmac is disabled" "hmac is disabled,hmac is enabled" newline bitfld.long 0x24 19. "HASH_KEY,1 need to load key 0 donot load key" "0,1" newline bitfld.long 0x24 18. "HASH_INIT_SECURE,1 load IV from secure area 0: load IV from public area" "load IV from public area,?" newline bitfld.long 0x24 17. "HASH_INIT,1 load IV for the hash 0 not load initial vector" "0,1" newline bitfld.long 0x24 16. "HASH_SHAUPDATE,0 final SHA224 output 7 words and SHA384 output 6 words 1: update SHA224/384 output 8 words please don't use this feature in hmac mode" "?,update SHA224/384 output 8 words please don't.." newline bitfld.long 0x24 15. "HASH_PADDINGEN,0: bypass padding logic 1: use hw padding logic" "bypass padding logic,use hw padding logic" newline hexmask.long.byte 0x24 8.--14. 1. "HASH_MODE,0000001 MD5 0000010 SHA1 0000100 SHA224 0001000 SHA256 0010000 SHA384 0100000 SHA512 1000000 SM3" newline bitfld.long 0x24 0. "HASH_GO,HASH Calculation start" "0,1" line.long 0x28 "CE0_HASH_KEYIV_ADDR,CE0 hash key and IV register" hexmask.long.word 0x28 16.--31. 1. "HASH_KEY_ADDR,HASH_KEY address" newline hexmask.long.word 0x28 0.--15. 1. "HASH_IV_ADDR,HASH initial vection address" line.long 0x2C "CE0_HMAC_KEY_CTRL,CE0 HMAC key control register" newline bitfld.long 0x2C 16.--17. "HMAC_KEY_TYPE,10 from key interface 01: from SRAM secure area 00 from SRAM public area" "?,from SRAM secure area 00 from SRAM public area,?,?" newline hexmask.long.word 0x2C 0.--15. 1. "HMAC_KEY_LEN,CE0 hash key length in CE SRAM" line.long 0x30 "CE0_HASH_CALC_LEN,CE0 hash calculation length register" hexmask.long 0x30 0.--31. 1. "HASH_CALC_LEN,CE0 hash calculation length in bytes" line.long 0x34 "CE0_HASH_SRC_ADDR,CE0 hash source data register" hexmask.long 0x34 0.--31. 1. "HASH_SRC_ADDR,CE0 HASH SRC ADDR" line.long 0x38 "CE0_HASH_SRC_ADDR_H,CE0 hash source data register high part" newline bitfld.long 0x38 8.--10. "HASH_SRC_TYPE,000: external memory 001: CE SRAM public area 011 CE sram secure area 1xx: SKC key interface space" "external memory,CE SRAM public area 011 CE sram secure area 1xx:..,?,?,?,?,?,?" newline hexmask.long.byte 0x38 0.--7. 1. "HASH_SRC_ADDR_H,the high part of CE0 hash src address" line.long 0x3C "CE0_HASH_DST_ADDR,CE0 hash results address" newline bitfld.long 0x3C 16.--18. "HASH_DST_TYPE,001 internal secure SRAM 001 public area in secure ram 1xx key interface" "0,1,2,3,4,5,6,7" newline hexmask.long.word 0x3C 0.--15. 1. "HASH_DST_ADDR,the dst address in secure SRAM" group.long 0x50++0x17 line.long 0x0 "CE0_DMA_CTRL,CE0 DMA control register" newline bitfld.long 0x0 10. "DMA_DONEINTEN,1 the interrupt will be generated if the DMA operation is done" "0,1" newline rbitfld.long 0x0 9. "DMA_CMDFIFO_FULL,cmd fifo is full" "0,1" newline rbitfld.long 0x0 8. "DMA_CMDFIFO_EMPTY,cmd fifo is empty" "0,1" newline bitfld.long 0x0 0. "DMA_GO,write 1 to this register start CE0 DMA operation" "0,1" line.long 0x4 "CE0_DMA_SRC_ADDR,CE0 DMA source data address register" hexmask.long 0x4 0.--31. 1. "DMA_SRC_ADDR,CE0 dma source addr" line.long 0x8 "CE0_DMA_SRC_ADDR_H,CE0 DMA source data address register high part" newline bitfld.long 0x8 8.--10. "DMA_SRC_TYPE,011: CE SRAM Secure AREA 001:CE SRAM public area 000:external memories other: reserved" "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x8 0.--7. 1. "DMA_SRC_ADDR_H,CE0 dma source addr high part" line.long 0xC "CE0_DMA_DST_ADDR,CE0 DMA destination data address" hexmask.long 0xC 0.--31. 1. "DMA_DST_ADDR,CE1 DMA DST ADDR" line.long 0x10 "CE0_DMA_DST_ADDR_H,CE0 DMA destination data address high part" newline bitfld.long 0x10 8.--10. "DMA_DST_TYPE,011: CE SRAM Secure AREA 001:CE SRAM public area 000:external memories other: reserved" "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x10 0.--7. 1. "DMA_DST_ADDR_H,CE1 DMA DST ADDR high part" line.long 0x14 "CE0_DMA_LEN,CE0 dma transfer data length" newline hexmask.long.word 0x14 0.--15. 1. "DMA_LEN,DMA transfer length in byte" group.long 0x80++0xB line.long 0x0 "CE0_PK_POINTERREG,CE0 PKE operand point register" newline hexmask.long.byte 0x0 24.--27. 1. "PK_OPPTRN,'When executing primitive arithmetic operations" newline hexmask.long.byte 0x0 16.--19. 1. "PK_OPPTRC,'When executing primitive arithmetic operations" newline hexmask.long.byte 0x0 8.--11. 1. "PK_OPPTRB,'When executing primitive arithmetic operations" newline hexmask.long.byte 0x0 0.--3. 1. "PK_OPPTRA,'When executing primitive arithmetic operations" line.long 0x4 "CE0_PK_COMMANDREG,CE0 PKE command register" bitfld.long 0x4 31. "PK_CALCR2,PK_CALCR2" "0,1" newline bitfld.long 0x4 30. "PK_FLAGB,'B See routine description'" "0,1" newline bitfld.long 0x4 29. "PK_FLAGA,'A See routine description'" "0,1" newline bitfld.long 0x4 28. "PK_SWAP,'bytes Swap the bytes on AHB interface: '0': Native format (little endian) '1': Byte swapped (big endian) See also section 4.2.1. This bit must be programmed before writing/reading any data in data memory.'" "0,1" newline bitfld.long 0x4 27. "PK_BUFFER,PK_BUFFER" "0,1" newline bitfld.long 0x4 26. "PK_EDWARDS,'Enable Edwards curve (see routine description)'" "0,1" newline bitfld.long 0x4 25. "PK_RANDPROJ,'Enable randomization of projective coordinates (counter-measure)'" "0,1" newline bitfld.long 0x4 24. "PK_RANDKE,'Enable randomization of exponent/scalar (counter-measure)'" "0,1" newline hexmask.long.byte 0x4 20.--23. 1. "PK_SELCURVE,'Enable accelerator for specific curve modulus: 0x0: No acceleration (default) 0x1: P256 0x2: P384 0x3: P521/E-521 0x4: P192 0x5: Curve25519/Ed25519 This field has no effect when the optional acceleration hardware is not included.'" newline hexmask.long.word 0x4 8.--18. 1. "PK_SIZE,'Of Operands (in data memory) This field defines the size (= number of bytes minus one) of the operands for the current operation. Possible values are limited by the maximum supported operand size. Examples: 0x014 -> ECC on curve K-163 0x01F ->.." newline bitfld.long 0x4 7. "PK_FIELD,''0': Field is GF(p) '1': Field is GF(2m)'" "0,1" newline hexmask.long.byte 0x4 0.--6. 1. "PK_TYPE,'of operation This field defines the operation to be performed. See table below for details.'" line.long 0x8 "CE0_PKE_CTRL,CE0_PKE_CTRL" newline bitfld.long 0x8 2. "PKE_SOFT_RST,'Writing a 1 to this bit will reset the pke_seq logic'" "0,1" newline bitfld.long 0x8 1. "PK_CLRMEMAFTEROP,'Writing a 1 to this bit will make the pke to clear its memories after all operations are complete'" "0,1" newline bitfld.long 0x8 0. "PKE_GO,'Writing a '1' starts the processing.'" "0,1" rgroup.long 0x8C++0x3 line.long 0x0 "CE0_PK_STATUSREG,CE0_PK_STATUSREG" newline bitfld.long 0x0 17. "PK_INTERRUPT,'status This bit reflects the IRQ output value. It is set to '1' when the operation is finished. It is cleared when the CPU writes the bit 1 of Control Register.'" "0,1" newline bitfld.long 0x0 16. "PK_BUSY,'This bit reflects the BUSY output value. It is set to '1' when the operation starts and it is cleared when the operation is finished.'" "0,1" newline bitfld.long 0x0 13. "PK_NOTQUADRATICRESIDUE,PK_NOTQUADRATICRESIDUE" "0,1" newline bitfld.long 0x0 12. "PK_COMPOSITE,PK_COMPOSITE" "0,1" newline bitfld.long 0x0 11. "PK_NOTINVERTIBLE,PK_NOTINVERTIBLE" "0,1" newline bitfld.long 0x0 10. "PK_PARAM_AB_NOTVALID,PK_PARAM_AB_NOTVALID" "0,1" newline bitfld.long 0x0 9. "PK_SIGNATURE_NOTVALID,PK_SIGNATURE_NOTVALID" "0,1" newline bitfld.long 0x0 8. "PK_NOTIMPLEMENTED,PK_NOTIMPLEMENTED" "0,1" newline bitfld.long 0x0 7. "PK_PARAM_N_NOTVALID,PK_PARAM_N_NOTVALID" "0,1" newline bitfld.long 0x0 6. "PK_COUPLE_NOTVALID,PK_COUPLE_NOTVALID" "0,1" newline bitfld.long 0x0 5. "PK_POINT_PX_ATINFINITY,PK_POINT_PX_ATINFINITY" "0,1" newline bitfld.long 0x0 4. "PK_POINT_PX_NOTONCURVE,PK_POINT_PX_NOTONCURVE" "0,1" newline hexmask.long.byte 0x0 0.--3. 1. "PK_FAIL_ADDRESS,'These bits indicate which data location generated the error flag. They are not available for all error flags.'" group.long 0x94++0x3 line.long 0x0 "CE0_PK_TIMER,CE0_PK_TIMER" hexmask.long 0x0 0.--31. 1. "PK_TIMER,'The timer counts the number of clock cycles when the PK engine is busy. It is not cleared automatically. It can be written by software (when the PK is idle). The register is updated at the end of every operation (reading it when the PK engine.." rgroup.long 0x98++0x3 line.long 0x0 "CE0_PK_HWCONFIGREG,CE0_PK_HWCONFIGREG" bitfld.long 0x0 31. "PK_DISABLECM,'State of DisableCM input (high when counter-measures are disabled)'" "0,1" newline bitfld.long 0x0 24. "PK_25519,'Support Curve25519/Ed25519 acceleration'" "0,1" newline bitfld.long 0x0 23. "PK_P192,'Support ECC P192 acceleration'" "0,1" newline bitfld.long 0x0 22. "PK_P521,'Support ECC P521 acceleration'" "0,1" newline bitfld.long 0x0 21. "PK_P384,'Support ECC P384 acceleration'" "0,1" newline bitfld.long 0x0 20. "PK_P256,'Support ECC P256 acceleration'" "0,1" newline bitfld.long 0x0 18.--19. "RESERVED,'unused'" "0,1,2,3" newline bitfld.long 0x0 17. "PK_BINARYFIELD,'Support binary field'" "0,1" newline bitfld.long 0x0 16. "PK_PRIMEFIELD,'Support prime field'" "0,1" newline hexmask.long.byte 0x0 12.--15. 1. "PK_NBMULT,'Number of multipliers: 0x0: 1 multiplier 0x1: 4 multipliers 0x2: 16 multipliers 0x4: 64 multipliers 0x8: 256 multipliers'" newline hexmask.long.word 0x0 0.--11. 1. "PK_MAXOPSIZE,'Maximum operand size (number of bytes) 4096 bytes'" group.long 0x9C++0xB line.long 0x0 "CE0_PK_RESULTS_CTRL,CE0_PK_RESULTS_CTRL" hexmask.long.word 0x0 16.--31. 1. "PKE_RESULTS_OP_LEN,'pke results each operand length in bytes'" newline hexmask.long.word 0x0 0.--15. 1. "PKE_RESULTS_OP_SELECT,'pke results output select each bit correspnding to the operand position of the pke data memory'" line.long 0x4 "CE0_PK_RESULTS_DST_ADDR,CE0_PK_RESULTS_DST_ADDR" hexmask.long 0x4 0.--31. 1. "PKE_RESULTS_DST_ADDR,'pke results dma dst address low 32bit'" line.long 0x8 "CE0_PK_RESULTS_DST_ADDR_H,CE0_PK_RESULTS_DST_ADDR_H" newline bitfld.long 0x8 8.--10. "PKE_RESULTS_DST_TYPE,'pke results dma dst data type 011: CE SRAM Secure AREA 001:CE SRAM public area 000:external memories other: reserved'" "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x8 0.--7. 1. "PKE_RESULTS_DST_ADDR_H,'pke results dma dst address high 8bit'" rgroup.long 0x100++0x3 line.long 0x0 "CE0_TRNG_STATUS,CE0 TRNG status register" newline bitfld.long 0x0 1. "RNG_SEQ_RUNNING,'1: the rng sequencer is running currently 0: rng sequencer is in idle status'" "rng sequencer is in idle status',the rng sequencer is running currently" newline bitfld.long 0x0 0. "RNG_READY,'1: the value in the random number register of CE0 is valid" "?,the value in the random number register of CE0.." repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) rgroup.long ($2+0x104)++0x3 line.long 0x0 "CE0_TRNG_NUM$1,CE0_TRNG_NUM0" hexmask.long 0x0 0.--31. 1. "TRNG_NUM0,CE0 the random number0 value" repeat.end rgroup.long 0x114++0x3 line.long 0x0 "CE0_HRNG_NUM,CE0_HRNG_NUM" hexmask.long 0x0 0.--31. 1. "HRNG_NUM,CE0 the hybird random number value" group.long 0x120++0xB line.long 0x0 "CE0_SKC_CTRL,CE0 SKC control register" newline bitfld.long 0x0 8.--10. "SKC_CMD,the command of SKC 001: generate random number 010: erase key contrainer" "?,generate random number,?,?,?,?,?,?" newline bitfld.long 0x0 0. "SKC_GO,CE0 secure FSM start trigger" "0,1" line.long 0x4 "CE0_SKC_RNG_ADDR,CE0 SKC random number register" newline bitfld.long 0x4 24. "SKC_RNG_SECURE,CE0 1: random number generated to secure area 0 : in public area" "in public area,random number generated to secure area" newline hexmask.long.byte 0x4 16.--22. 1. "SKC_RNG_LEN,'numbers of bits to generate into sram granularity is 256 bit'" newline hexmask.long.word 0x4 0.--12. 1. "SKC_RNG_ADDR,CE0 random number generation address in CE sram the address granularity is 8 bytes" line.long 0x8 "CE0_SKC_KEYBLOB_CTRL,CE0 SKC key blob control register" newline bitfld.long 0x8 0. "SKC_KEYBLOB_CTRL,CE0 key blob control 1: is key blob :0 : is the secret data" "?,is key blob :0 : is the secret data" group.long 0x140++0x3 line.long 0x0 "CE0_INTEN,CE0 interrupt enable register" newline bitfld.long 0x0 13. "DMA_FIFOERROR_INTEN,DMA fifo error interrupt" "0,1" newline bitfld.long 0x0 12. "PKE_INTEGRITY_ERROR_INTEN,ALGORITHM_INTEGRITY interrupt" "0,1" newline bitfld.long 0x0 11. "HASH_INTEGRITY_ERROR_INTEN,ALGORITHM_INTEGRITY_ERROR interrupt" "0,1" newline bitfld.long 0x0 10. "CIPHER_INTEGRITY_ERROR_INTEN,ALGORITHM_INTEGRITY_ERROR interrupt" "0,1" newline bitfld.long 0x0 9. "SKC_INTEGRITY_ERROR_INTEN,SKC_INTEGRITY_ERROR interrupt" "0,1" newline bitfld.long 0x0 8. "DMA_INTEGRITY_ERROR_INTEN,ALGORITHM_INTEGRITY interrupt" "0,1" newline bitfld.long 0x0 4. "PKE_DONE_INTEN,PKE_DONE interrupt" "0,1" newline bitfld.long 0x0 3. "HASH_DONE_INTEN,HASH_DONE interrupt" "0,1" newline bitfld.long 0x0 2. "CIPHER_DONE_INTEN,CIPHER_DONE_INTEN" "0,1" newline bitfld.long 0x0 1. "SKC_DONE_INTEN,KEYgen done interrupt enable" "0,1" newline bitfld.long 0x0 0. "DMA_DONE_INTEN,DMA_DONE interrupt" "0,1" rgroup.long 0x144++0x3 line.long 0x0 "CE0_INTSTAT,CE0 interrupt status register" newline bitfld.long 0x0 13. "DMA_FIFOERROR_INTSTAT,SSRAM_DMAFIFO error interrupt" "0,1" newline bitfld.long 0x0 12. "PKE_INTEGRITY_ERROR_INTSTAT,ALGORITHM_INTEGRITY interrupt" "0,1" newline bitfld.long 0x0 11. "HASH_INTEGRITY_ERROR_INTSTAT,ALGORITHM_INTEGRITY_ERROR interrupt" "0,1" newline bitfld.long 0x0 10. "CIPHER_INTEGRITY_ERROR_INTSTAT,ALGORITHM_INTEGRITY_ERROR interrupt" "0,1" newline bitfld.long 0x0 9. "SKC_INTEGRITY_ERROR_INTSTAT,SKC_INTEGRITY_ERROR interrupt" "0,1" newline bitfld.long 0x0 8. "DMA_INTEGRITY_ERROR_INTSTAT,ALGORITHM_INTEGRITY interrupt" "0,1" newline bitfld.long 0x0 4. "PKE_DONE_INTSTAT,PKE_DONE interrupt" "0,1" newline bitfld.long 0x0 3. "HASH_DONE_INTSTAT,HASH_DONE interrupt" "0,1" newline bitfld.long 0x0 2. "CIPHER_DONE_INTSTAT,CIPHER_DONE_INTSTATE" "0,1" newline bitfld.long 0x0 1. "SKC_DONE_INTSTAT,KEYgen done interrupt enable" "0,1" newline bitfld.long 0x0 0. "DMA_DONE_INTSTAT,DMA_DONE interrupt" "0,1" group.long 0x148++0x3 line.long 0x0 "CE0_INTCLR,CE0 interrupt clear register" newline bitfld.long 0x0 13. "DMA_FIFOERROR_INTCLR,SSRAM_DMAFIFO error interrupt" "0,1" newline bitfld.long 0x0 12. "PKE_INTEGRITY_ERROR_INTCLR,ALGORITHM_INTEGRITY interrupt" "0,1" newline bitfld.long 0x0 11. "HASH_INTEGRITY_ERROR_INTCLR,ALGORITHM_INTEGRITY_ERROR interrupt" "0,1" newline bitfld.long 0x0 10. "CIPHER_INTEGRITY_ERROR_INTCLR,ALGORITHM_INTEGRITY_ERROR interrupt" "0,1" newline bitfld.long 0x0 9. "SKC_INTEGRITY_ERROR_INTCLR,SKC_INTEGRITY_ERROR interrupt" "0,1" newline bitfld.long 0x0 8. "DMA_INTEGRITY_ERROR_INTCLR,ALGORITHM_INTEGRITY interrupt" "0,1" newline bitfld.long 0x0 4. "PKE_DONE_INTCLR,PKE_DONE interrupt" "0,1" newline bitfld.long 0x0 3. "HASH_DONE_INTCLR,HASH_DONE interrupt" "0,1" newline bitfld.long 0x0 2. "CIPHER_DONE_INTCLR,CIPHER_DONE_INTCLRE" "0,1" newline bitfld.long 0x0 1. "SKC_DONE_INTCLR,KEYgen done interrupt enable" "0,1" newline bitfld.long 0x0 0. "DMA_DONE_INTCLR,DMA_DONE interrupt" "0,1" group.long 0x8000++0x7 line.long 0x0 "SECURE_CTRL,CE secure violation control" hexmask.long.byte 0x0 24.--31. 1. "CE_SRAM_SIZE_VIO,the CE sram size size is not correct" newline rbitfld.long 0x0 17. "SRAM_SIZE_TOTAL_VIO,the CE sram size total size is not correct" "0,1" newline bitfld.long 0x0 16. "PKE_CM_DISABLE,'1: disable the PKE counter measure 0 : enable the counter measure'" "enable the counter measure',disable the PKE counter measure" newline hexmask.long.byte 0x0 8.--15. 1. "SECURE_VIOLATION_STATUS,'secure violation input status'" newline hexmask.long.byte 0x0 0.--7. 1. "SECURE_VIOLATION_ENABLE,'the corresponding bits enable the secure violation source'" line.long 0x4 "SESRAM_SIZE,Secure SRAM size for CE0" newline hexmask.long.byte 0x4 0.--6. 1. "CE0_RAM_SIZE,the CE sram size" group.long 0x800C++0x3 line.long 0x0 "SESRAM_SASIZE,secure SRAM secure area size" newline hexmask.long.byte 0x0 0.--6. 1. "CE0_RAM_SASIZE,the secure area sram size" group.long 0x8014++0x7 line.long 0x0 "VCE_SINATURE_MASK,VCE SIGNAGURE generation mask" hexmask.long 0x0 0.--31. 1. "VCE_SINATURE_MASK,'the mask for the vce to generate signature from id'" line.long 0x4 "VCE_SINATURE_MASK_HIGH,VCE_SINATURE_MASK_HIGH" newline hexmask.long.byte 0x4 0.--7. 1. "VCE_SINATURE_MASK_HIGH,'the mask for the vce to generate signature from id high part'" group.long 0x8020++0x7 line.long 0x0 "HRNG_CTRL,HRNG_CTRL" newline hexmask.long.byte 0x0 8.--11. 1. "HRNG_LOAD_CNT,'the counter to control the frequency for the hrng LFSF load the feedback cycle'" newline bitfld.long 0x0 0. "NOISE_ENABLE,'1: enable the noise source for the hrng 0: disable the noise source'" "disable the noise source',enable the noise source for the hrng" line.long 0x4 "HRNG_SEED_CTRL,HRNG_SEED_CTRL" bitfld.long 0x4 31. "LOAD_SEED_GO,'write 1 to this bit will load the seed into the hrng auto clear'" "0,1" newline hexmask.long 0x4 0.--30. 1. "SEED_NUM,'the seed number" group.long 0x8030++0x3 line.long 0x0 "TRNG_CTRL,TRNG_CTRL" newline bitfld.long 0x0 0. "CE_TRNG_SEQ_GO,'write this bit will start the trng sequencer to fetch the random number for all VCEs'" "0,1" group.long 0x8050++0x3 line.long 0x0 "DEBUG_BUS_SEL,DEBUG_BUS_SEL" newline hexmask.long.word 0x0 0.--15. 1. "DEBUG_BUS_SEL,'debug bus select'" rgroup.long 0x8054++0x3 line.long 0x0 "DEBUG_BUS_STATUS,DEBUG_BUS_STATUS" hexmask.long 0x0 0.--31. 1. "DEBUG_BUS_STATUS,'debug bus output'" group.long 0x8100++0x3 line.long 0x0 "TRNG_CONTROL,TRNG_CONTROL" newline bitfld.long 0x0 20. "TRNG_FIFOWRITESTARTUP,'Enable write of the samples in the FIFO during start-up'" "0,1" newline hexmask.long.byte 0x0 16.--19. 1. "TRNG_NB128BITBLOCKS,'Number of 128 bit blocks used in AES-CBCMAC post-processing. This value cannot be zero.'" newline bitfld.long 0x0 15. "TRNG_AIS31TESTSEL,'Select input to the AIS31 test module 0: Before conditioning 1: After conditioning'" "Before conditioning,After conditioning'" newline bitfld.long 0x0 14. "TRNG_HEALTHTESTSEL,'Select input to health test module 0: Before conditioning 1: After conditioning'" "Before conditioning,After conditioning'" newline bitfld.long 0x0 13. "TRNG_AIS31BYPASS,'Bypass AIS31 tests such that the results of the start-up and online tests do not affect the FSM state'" "0,1" newline bitfld.long 0x0 12. "TRNG_HEALTHTESTBYPASS,'Bypass NIST tests such that the results of the start-up and online test do not affect the FSM state'" "0,1" newline bitfld.long 0x0 11. "TRNG_FORCERUN,'Force oscillators to run when FIFO is full'" "0,1" newline bitfld.long 0x0 10. "TRNG_INTENALM,'Interrupt enable for AIS31 noise alarm'" "0,1" newline bitfld.long 0x0 9. "TRNG_INTENPRE,'Interrupt enable for AIS31 preliminary noise alarm'" "0,1" newline bitfld.long 0x0 8. "TRNG_SOFTRESET,'Software reset 0: Normal mode 1: The continuous test" "Normal mode,The continuous test" newline bitfld.long 0x0 7. "TRNG_INTENFULL,'Interrupt enable for FIFO full'" "0,1" newline bitfld.long 0x0 5. "TRNG_INTENPROP,'Interrupt enable for Adaptive Proportion Test failure (1024-sample window)'" "0,1" newline bitfld.long 0x0 4. "TRNG_INTENREP,'Interrupt enable for Repetition Count Test failure'" "0,1" newline bitfld.long 0x0 3. "TRNG_CONDBYPASS,'0: the conditioning function is used (normal mode) 1: the conditioning function is bypassed (to observe entropy source directly).'" "the conditioning function is used,the conditioning function is bypassed" newline bitfld.long 0x0 2. "TRNG_TESTEN,'Select input for conditioning function and continuous tests: 0: Noise source (normal mode) 1: Test data register (test mode)'" "Noise source,Test data register" newline bitfld.long 0x0 1. "TRNG_LFSREN,TRNG_LFSREN" "0,1" newline bitfld.long 0x0 0. "TRNG_ENABLE,'Enable the NDRNG.'" "0,1" rgroup.long 0x8104++0xB line.long 0x0 "TRNG_FIFOLEVEL,TRNG_FIFOLEVEL" hexmask.long 0x0 0.--31. 1. "TRNG_FIFOLEVEL,'Number of 32 bits words of random available in the FIFO. Any write to this register clears the FullInt flag in the Status register.'" line.long 0x4 "TRNG_FIFOTHD,TRNG_FIFOTHD" hexmask.long 0x4 0.--31. 1. "TRNG_FIFOTHD,'FIFO level below which the module leaves the idle state to refill the fifo" line.long 0x8 "TRNG_FIFODEPTH,TRNG_FIFODEPTH" hexmask.long 0x8 0.--31. 1. "TRNG_FIFODEPTH,'Depth Maximum number of 32 bits words that can be stored in the FIFO: 2g_fifodepth.'" group.long 0x8110++0xF line.long 0x0 "TRNG_KEY0REG,TRNG_KEY0REG" hexmask.long 0x0 0.--31. 1. "TRNG_KEY0REG,'Key (MSB)'" line.long 0x4 "TRNG_KEY1REG,TRNG_KEY1REG" hexmask.long 0x4 0.--31. 1. "TRNG_KEY1REG,'Key'" line.long 0x8 "TRNG_KEY2REG,TRNG_KEY2REG" hexmask.long 0x8 0.--31. 1. "TRNG_KEY2REG,'Key'" line.long 0xC "TRNG_KEY3REG,TRNG_KEY3REG" hexmask.long 0xC 0.--31. 1. "TRNG_KEY3REG,'Key (LSB)'" wgroup.long 0x8120++0x3 line.long 0x0 "TRNG_TESTDATA,TRNG_TESTDATA" hexmask.long 0x0 0.--31. 1. "TRNG_TESTDATA,'feed known data to the conditioning function or to the continous tests.'" group.long 0x8124++0x7 line.long 0x0 "TRNG_REPTHRESREG,TRNG_REPTHRESREG" hexmask.long 0x0 0.--31. 1. "TRNG_REPTHRESREG,'Repetition Test Count Cut-Off value'" line.long 0x4 "TRNG_PROPTHRESREG,TRNG_PROPTHRESREG" hexmask.long 0x4 0.--31. 1. "TRNG_PROPTHRESREG,'Adaptive Proportion Test (1024-sample window) Cut-Off value'" group.long 0x8130++0x17 line.long 0x0 "TRNG_STATUS,TRNG_STATUS" newline bitfld.long 0x0 11. "TRNG_FIFOACCFAIL,'Set when a FIFO data read is performed while the NDRNG is disabled AND has its FIFO empty (FIFOLevel = 0)'" "0,1" newline rbitfld.long 0x0 10. "TRNG_STARTUPFAIL,'Start-up test failure'" "0,1" newline rbitfld.long 0x0 9. "TRNG_ALMINT,'AIS31 noise alarm interrupt status'" "0,1" newline bitfld.long 0x0 8. "TRNG_PREINT,'AIS31 preliminary noise alarm interrupt status'" "0,1" newline bitfld.long 0x0 7. "TRNG_FULLINT,'FIFO full status'" "0,1" newline bitfld.long 0x0 5. "TRNG_PROPFAIL,'NIST-800-90B adaptive Proportion Test (1024-sample window) interrupt status'" "0,1" newline bitfld.long 0x0 4. "TRNG_REPFAIL,'NIST-800-90B repetition Count Test interrupt status'" "0,1" newline rbitfld.long 0x0 1.--3. "TRNG_STATE,'State of the control FSM (see Figure 7-1) 000: Reset 001: Startup 010: Idle (Rings On) 011: Idle (Rings Off) 100: Fill FIFO 101: Error 110: Unused 111: Unused'" "Reset,Startup,?,?,?,?,?,?" newline rbitfld.long 0x0 0. "TRNG_TESTDATABUSY,'High when data written to TestData register is being processed. (see section 4.7)'" "0,1" line.long 0x4 "TRNG_INITWAITVAL,TRNG_INITWAITVAL" newline hexmask.long.word 0x4 0.--15. 1. "TRNG_INITWAITVAL,'Number of clock cycles to wait before sampling data from the noise source. All 16 bits are reset high (reset value = 0xFFFF).'" line.long 0x8 "TRNG_DISABLEOSC,TRNG_DISABLEOSC" hexmask.long 0x8 0.--31. 1. "TRNG_DISABLEOS0,'Disable oscillator rings #0 to #31'" line.long 0xC "TRNG_DISABLEOSC1,TRNG_DISABLEOSC1" hexmask.long 0xC 0.--31. 1. "TRNG_DISABLEOS1,'Disable oscillator rings #32 to #63'" line.long 0x10 "TRNG_SWOFFTMRVAL,TRNG_SWOFFTMRVAL" newline hexmask.long.word 0x10 0.--15. 1. "TRNG_SWOFFTMRVAL,'Number of clk cycles to wait before stopping the rings after the FIFO is full. '" line.long 0x14 "TRNG_CLKDIV,TRNG_CLKDIV" newline hexmask.long.byte 0x14 0.--7. 1. "TRNG_CLKDIV,'Sample clock divider. The frequency at which the outputs of the rings are sampled is given by Fs = Fpclk/(ClkDiv + 1).'" repeat 3. (list 0x0 0x1 0x2 )(list 0x0 0x4 0x8 ) group.long ($2+0x8148)++0x3 line.long 0x0 "TRNG_AIS31CONF$1,TRNG_AIS31CONF0" hexmask.long.word 0x0 16.--31. 1. "TRNG_ONLINETHRESH,'Online threshold'" newline hexmask.long.word 0x0 0.--15. 1. "TRNG_STARTUPTHRESH,'Start-up test threshold'" repeat.end group.long 0x8154++0x3 line.long 0x0 "TRNG_AIS31STATUS,TRNG_AIS31STATUS" newline rbitfld.long 0x0 17. "TRNG_PRELIMNOISEALARMREP,TRNG_PRELIMNOISEALARMREP" "0,1" newline rbitfld.long 0x0 16. "TRNG_PRELIMNOISEALARMRNG,'Last preliminary noise alarm occurred due to history value out of range'" "0,1" newline hexmask.long.word 0x0 0.--15. 1. "TRNG_NUMPRELIMALARMS,'Number of preliminary noise alarms since counter was last cleared'" rgroup.long 0x8158++0x3 line.long 0x0 "TRNG_HWCONF,TRNG_HWCONF" newline bitfld.long 0x0 9. "TRNG_AIS31FULL,'Generic g_AIS31Full value'" "0,1" newline bitfld.long 0x0 8. "TRNG_AIS31,'Generic g_AIS31 value'" "0,1" newline hexmask.long.byte 0x0 0.--7. 1. "TRNG_NUMBOFRINGS,'Generic g_NumRings value'" tree.end tree "CE2_REG" base ad:0x34000000 rgroup.long 0x0++0x7 line.long 0x0 "CE0_STAT,CE0 working status" newline bitfld.long 0x0 5. "PKE_BUSY,1: PKE is busy 0:PKE is idle" "?,PKE is busy 0:PKE is idle" newline bitfld.long 0x0 4. "GENKEY_BUSY,1. CE0 generate key function is busy" "0,1" newline bitfld.long 0x0 3. "HASH_BUSY,1: the HASH of CE0 is busy" "?,the HASH of CE0 is busy" newline bitfld.long 0x0 2. "CIPHER_BUSY,1 the CIPHER of CE0 is busy" "0,1" newline bitfld.long 0x0 1. "GETRNDNUM_BUSY,1: get random number function of CE0 is busy" "?,get random number function of CE0 is busy" newline bitfld.long 0x0 0. "DMA_BUSY,1: the DMA of CE0 is busy 0: the DMA of CE0 is idle" "the DMA of CE0 is idle,the DMA of CE0 is busy" line.long 0x4 "CE0_ERRSTAT,CE0 error status" newline hexmask.long.byte 0x4 24.--27. 1. "SKC_ERR_STAT,'the error status of skc sequencer the bit 0 ~ 3 are [sram wr err] [ rand number fetch err] [ secure violation occurs] [reserved]'" newline bitfld.long 0x4 19. "SSRAM_ERR_STAT,'the error status of CE sram" "0,1" newline bitfld.long 0x4 16.--18. "DMA_ERR_STAT,'the error status of dma sequencer the bit of 0 -2 are [sram_rw_err] [wdma ch err] [rdma ch err]'" "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x4 8.--13. 1. "CIPHER_ERR_STAT,'the error status of cipher sequencer the bit 5 - 0 are {config err" newline hexmask.long.byte 0x4 0.--3. 1. "HASH_ERR_STAT,'the error status of hash sequencer the bit 0 ~ 3 are [sram_wr_err] [sram rd err] [rdma_err] [wdma err]'" group.long 0xC++0x3F line.long 0x0 "CE0_CIPHER_CTRL,CE0 cipher control register" bitfld.long 0x0 31. "CIPHER_HEADER_SAVE,1 the header will be saved into dst memory 0: header will not be saved" "header will not be saved,?" newline bitfld.long 0x0 28.--29. "CIPHER_KEY2TYPE,key 2 type 10: input keyport 00: secure sram public area 01: secure area others: reserved" "secure sram public area,secure area others: reserved,?,?" newline bitfld.long 0x0 25.--26. "CIPHER_KEYTYPE,key type 10: input keyport 00: secure sram public area 01: secure area others: reserved" "secure sram public area,secure area others: reserved,?,?" newline hexmask.long.word 0x0 16.--24. 1. "AESMODE,'AES mode XTS : 010000000 ECB : 000000001 CBC : 000000010 CTR : 000000100 CFB : 000001000 OFB : 000010000 CCM : 000100000 GCM : 001000000 XTS : 010000000 CMAC: 100000000'" newline bitfld.long 0x0 13. "CIPHER_SAVE,0: normal mode last part of the message 1: operation context will be saved at the end of operation" "normal mode last part of the message,operation context will be saved at the end of.." newline bitfld.long 0x0 12. "CIPHER_LOAD,0 : normal mode first start of the message 1: operation restart from previously save context" "normal mode first start of the message,operation restart from previously save context" newline bitfld.long 0x0 11. "CIPHER_DECKEYCAL,0 use the input key for decryption operations 1: use the pre-calculation of the key is done before" "?,use the pre-calculation of the key is done before" newline bitfld.long 0x0 9.--10. "CIPHER_KEYSIZE,key size 00: 128bit key 01: 256 bit key 10: 192bit key 11: reserved" "0,1,2,3" newline bitfld.long 0x0 8. "CIPHERMODE,0 encryption 1 decryption" "0,1" newline bitfld.long 0x0 0. "CIPHER_GO,'write 1 to this bit will start the cipher operation'" "0,1" line.long 0x4 "CE0_CIPHER_HEADER_LEN,CE0 cipher header length register" hexmask.long 0x4 0.--31. 1. "CIPHER_HEADER_LEN,'cipher data header length in bytes'" line.long 0x8 "CE0_CIPHER_KEY_ADDR,CE0 cipher key addr register" hexmask.long.word 0x8 16.--31. 1. "CIPHER_KEY2_ADDR,key2 address in secure SRAM or keyport" newline hexmask.long.word 0x8 0.--15. 1. "CIPHER_KEY_ADDR,CIPHER_KEY_ADDR address in secure SRAM or keyport" line.long 0xC "CE0_CIPHER_SRC_ADDR,CE0 cipher source data addr register" hexmask.long 0xC 0.--31. 1. "CIPHER_SRC_ADDR,cipher data source address in bytes" line.long 0x10 "CE0_CIPHER_SRC_ADDR_H,CE0 cipher source data addr high register" newline bitfld.long 0x10 8.--10. "CIPHER_SRC_TYPE,011: CE SRAM Secure AREA 001:CE SRAM public area 000:external memories other: reserved" "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x10 0.--7. 1. "CIPHER_SRC_ADDR_H,the high part of CE0 cipher source address" line.long 0x14 "CE0_CIPHER_DST_ADDR,CE0 cipher destination data addr register" hexmask.long 0x14 0.--31. 1. "CIPHER_DST_ADDR,CE0 cipher data destination address" line.long 0x18 "CE0_CIPHER_DST_ADDR_H,CE0 cipher destination data addr high register" newline bitfld.long 0x18 8.--10. "CIPHER_DST_TYPE,011: CE SRAM Secure AREA 001:CE SRAM public area 000:external memories other: reserved" "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x18 0.--7. 1. "CIPHER_DST_ADDR_H,CE0 cipher data destination address" line.long 0x1C "CE0_CIPHER_IV_CONTEXT_ADDR,CE0 cipher IV and context addr register" hexmask.long.word 0x1C 16.--31. 1. "CIPHER_CONTEXT_ADDR,CIPHER context storage address the context is always stored into SRAM secure area" newline hexmask.long.word 0x1C 0.--15. 1. "CIPHER_IV_ADDR,CIPHER iv storage address the iv is always stored into SRAM secure area" line.long 0x20 "CE0_CIPHER_PAYLOAD_LEN,CE0 cipher payload length register" hexmask.long 0x20 0.--31. 1. "CIPHER_PAYLOAD_LEN,CIPHER_PAYLOAD_LEN NOT including the header length in byte" line.long 0x24 "CE0_HASH_CTRL,CE0 hash control register" newline bitfld.long 0x24 24. "HASH_HMAC_EN,1: hmac is enabled 0: hmac is disabled" "hmac is disabled,hmac is enabled" newline bitfld.long 0x24 19. "HASH_KEY,1 need to load key 0 donot load key" "0,1" newline bitfld.long 0x24 18. "HASH_INIT_SECURE,1 load IV from secure area 0: load IV from public area" "load IV from public area,?" newline bitfld.long 0x24 17. "HASH_INIT,1 load IV for the hash 0 not load initial vector" "0,1" newline bitfld.long 0x24 16. "HASH_SHAUPDATE,0 final SHA224 output 7 words and SHA384 output 6 words 1: update SHA224/384 output 8 words please don't use this feature in hmac mode" "?,update SHA224/384 output 8 words please don't.." newline bitfld.long 0x24 15. "HASH_PADDINGEN,0: bypass padding logic 1: use hw padding logic" "bypass padding logic,use hw padding logic" newline hexmask.long.byte 0x24 8.--14. 1. "HASH_MODE,0000001 MD5 0000010 SHA1 0000100 SHA224 0001000 SHA256 0010000 SHA384 0100000 SHA512 1000000 SM3" newline bitfld.long 0x24 0. "HASH_GO,HASH Calculation start" "0,1" line.long 0x28 "CE0_HASH_KEYIV_ADDR,CE0 hash key and IV address register" hexmask.long.word 0x28 16.--31. 1. "HASH_KEY_ADDR,HASH_KEY address" newline hexmask.long.word 0x28 0.--15. 1. "HASH_IV_ADDR,HASH initial vection address" line.long 0x2C "CE0_HMAC_KEY_CTRL,CE0 hmac key control register" newline bitfld.long 0x2C 16.--17. "HMAC_KEY_TYPE,10 from key interface 01: from SRAM secure area 00 from SRAM public area" "?,from SRAM secure area 00 from SRAM public area,?,?" newline hexmask.long.word 0x2C 0.--15. 1. "HMAC_KEY_LEN,CE0 hash key length in CE SRAM" line.long 0x30 "CE0_HASH_CALC_LEN,CE0 hash calcluation length register" hexmask.long 0x30 0.--31. 1. "HASH_CALC_LEN,CE0 hash calculation length in bytes" line.long 0x34 "CE0_HASH_SRC_ADDR,CE0 hash source address register" hexmask.long 0x34 0.--31. 1. "HASH_SRC_ADDR,CE0 HASH SRC ADDR" line.long 0x38 "CE0_HASH_SRC_ADDR_H,CE0 hash source address high register" newline bitfld.long 0x38 8.--10. "HASH_SRC_TYPE,000: external memory 001: CE SRAM public area 011 CE sram secure area 1xx: SKC key interface space" "external memory,CE SRAM public area 011 CE sram secure area 1xx:..,?,?,?,?,?,?" newline hexmask.long.byte 0x38 0.--7. 1. "HASH_SRC_ADDR_H,the high part of CE0 hash src address" line.long 0x3C "CE0_HASH_DST_ADDR,CE0 hash destination address register" newline bitfld.long 0x3C 16.--18. "HASH_DST_TYPE,011 internal secure SRAM 001 public area in secure ram 1xx key interface e.g. key container" "0,1,2,3,4,5,6,7" newline hexmask.long.word 0x3C 0.--15. 1. "HASH_DST_ADDR,the dst address in secure SRAM" group.long 0x50++0x17 line.long 0x0 "CE0_DMA_CTRL,CE0_DMA_CTRL" newline bitfld.long 0x0 10. "DMA_DONEINTEN,1 the interrupt will be generated if the DMA operation is done" "0,1" newline rbitfld.long 0x0 9. "DMA_CMDFIFO_FULL,cmd fifo is full" "0,1" newline rbitfld.long 0x0 8. "DMA_CMDFIFO_EMPTY,cmd fifo is empty" "0,1" newline bitfld.long 0x0 0. "DMA_GO,write 1 to this register start CE0 DMA operation" "0,1" line.long 0x4 "CE0_DMA_SRC_ADDR,CE0 dma source address register" hexmask.long 0x4 0.--31. 1. "DMA_SRC_ADDR,CE0 dma source addr" line.long 0x8 "CE0_DMA_SRC_ADDR_H,CE0 dma source address high register" newline bitfld.long 0x8 8.--10. "DMA_SRC_TYPE,011: CE SRAM Secure AREA 001:CE SRAM public area 000:external memories 010: PKE operand mem other: reserved" "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x8 0.--7. 1. "DMA_SRC_ADDR_H,CE0 dma source addr high part" line.long 0xC "CE0_DMA_DST_ADDR,CE0 dma destination address register" hexmask.long 0xC 0.--31. 1. "DMA_DST_ADDR,CE1 DMA DST ADDR" line.long 0x10 "CE0_DMA_DST_ADDR_H,CE0 dma destination address high register" newline bitfld.long 0x10 8.--10. "DMA_DST_TYPE,011: CE SRAM Secure AREA 001:CE SRAM public area 000:external memories 010: PKE operand mem other: reserved" "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x10 0.--7. 1. "DMA_DST_ADDR_H,CE1 DMA DST ADDR high part" line.long 0x14 "CE0_DMA_LEN,CE0 dma transer length register" newline hexmask.long.word 0x14 0.--15. 1. "DMA_LEN,DMA transfer length in byte" group.long 0x80++0xB line.long 0x0 "CE0_PK_POINTERREG,CE0_PK_POINTERREG" newline hexmask.long.byte 0x0 24.--27. 1. "PK_OPPTRN,'When executing primitive arithmetic operations" newline hexmask.long.byte 0x0 16.--19. 1. "PK_OPPTRC,'When executing primitive arithmetic operations" newline hexmask.long.byte 0x0 8.--11. 1. "PK_OPPTRB,'When executing primitive arithmetic operations" newline hexmask.long.byte 0x0 0.--3. 1. "PK_OPPTRA,'When executing primitive arithmetic operations" line.long 0x4 "CE0_PK_COMMANDREG,CE0_PK_COMMANDREG" bitfld.long 0x4 31. "PK_CALCR2,PK_CALCR2" "0,1" newline bitfld.long 0x4 30. "PK_FLAGB,'B See routine description'" "0,1" newline bitfld.long 0x4 29. "PK_FLAGA,'A See routine description'" "0,1" newline bitfld.long 0x4 28. "PK_SWAP,'bytes Swap the bytes on AHB interface: '0': Native format (little endian) '1': Byte swapped (big endian) See also section 4.2.1. This bit must be programmed before writing/reading any data in data memory.'" "0,1" newline bitfld.long 0x4 27. "PK_BUFFER,PK_BUFFER" "0,1" newline bitfld.long 0x4 26. "PK_EDWARDS,'Enable Edwards curve (see routine description)'" "0,1" newline bitfld.long 0x4 25. "PK_RANDPROJ,'Enable randomization of projective coordinates (counter-measure)'" "0,1" newline bitfld.long 0x4 24. "PK_RANDKE,'Enable randomization of exponent/scalar (counter-measure)'" "0,1" newline hexmask.long.byte 0x4 20.--23. 1. "PK_SELCURVE,'Enable accelerator for specific curve modulus: 0x0: No acceleration (default) 0x1: P256 0x2: P384 0x3: P521/E-521 0x4: P192 0x5: Curve25519/Ed25519 This field has no effect when the optional acceleration hardware is not included.'" newline hexmask.long.word 0x4 8.--18. 1. "PK_SIZE,'Of Operands (in data memory) This field defines the size (= number of bytes minus one) of the operands for the current operation. Possible values are limited by the maximum supported operand size. Examples: 0x014 -> ECC on curve K-163 0x01F ->.." newline bitfld.long 0x4 7. "PK_FIELD,''0': Field is GF(p) '1': Field is GF(2m)'" "0,1" newline hexmask.long.byte 0x4 0.--6. 1. "PK_TYPE,'of operation This field defines the operation to be performed. See table below for details.'" line.long 0x8 "CE0_PKE_CTRL,CE0_PKE_CTRL" newline bitfld.long 0x8 2. "PKE_SOFT_RST,'Writing a 1 to this bit will reset the pke_seq logic'" "0,1" newline bitfld.long 0x8 1. "PK_CLRMEMAFTEROP,'Writing a 1 to this bit will make the pke to clear its memories after all operations are complete'" "0,1" newline bitfld.long 0x8 0. "PKE_GO,'Writing a '1' starts the processing.'" "0,1" rgroup.long 0x8C++0x3 line.long 0x0 "CE0_PK_STATUSREG,CE0_PK_STATUSREG" newline bitfld.long 0x0 17. "PK_INTERRUPT,'status This bit reflects the IRQ output value. It is set to '1' when the operation is finished. It is cleared when the CPU writes the bit 1 of Control Register.'" "0,1" newline bitfld.long 0x0 16. "PK_BUSY,'This bit reflects the BUSY output value. It is set to '1' when the operation starts and it is cleared when the operation is finished.'" "0,1" newline bitfld.long 0x0 13. "PK_NOTQUADRATICRESIDUE,PK_NOTQUADRATICRESIDUE" "0,1" newline bitfld.long 0x0 12. "PK_COMPOSITE,PK_COMPOSITE" "0,1" newline bitfld.long 0x0 11. "PK_NOTINVERTIBLE,PK_NOTINVERTIBLE" "0,1" newline bitfld.long 0x0 10. "PK_PARAM_AB_NOTVALID,PK_PARAM_AB_NOTVALID" "0,1" newline bitfld.long 0x0 9. "PK_SIGNATURE_NOTVALID,PK_SIGNATURE_NOTVALID" "0,1" newline bitfld.long 0x0 8. "PK_NOTIMPLEMENTED,PK_NOTIMPLEMENTED" "0,1" newline bitfld.long 0x0 7. "PK_PARAM_N_NOTVALID,PK_PARAM_N_NOTVALID" "0,1" newline bitfld.long 0x0 6. "PK_COUPLE_NOTVALID,PK_COUPLE_NOTVALID" "0,1" newline bitfld.long 0x0 5. "PK_POINT_PX_ATINFINITY,PK_POINT_PX_ATINFINITY" "0,1" newline bitfld.long 0x0 4. "PK_POINT_PX_NOTONCURVE,PK_POINT_PX_NOTONCURVE" "0,1" newline hexmask.long.byte 0x0 0.--3. 1. "PK_FAIL_ADDRESS,'These bits indicate which data location generated the error flag. They are not available for all error flags.'" group.long 0x94++0x3 line.long 0x0 "CE0_PK_TIMER,CE0_PK_TIMER" hexmask.long 0x0 0.--31. 1. "PK_TIMER,'The timer counts the number of clock cycles when the PK engine is busy. It is not cleared automatically. It can be written by software (when the PK is idle). The register is updated at the end of every operation (reading it when the PK engine.." rgroup.long 0x98++0x3 line.long 0x0 "CE0_PK_HWCONFIGREG,CE0_PK_HWCONFIGREG" bitfld.long 0x0 31. "PK_DISABLECM,'State of DisableCM input (high when counter-measures are disabled)'" "0,1" newline bitfld.long 0x0 24. "PK_25519,'Support Curve25519/Ed25519 acceleration'" "0,1" newline bitfld.long 0x0 23. "PK_P192,'Support ECC P192 acceleration'" "0,1" newline bitfld.long 0x0 22. "PK_P521,'Support ECC P521 acceleration'" "0,1" newline bitfld.long 0x0 21. "PK_P384,'Support ECC P384 acceleration'" "0,1" newline bitfld.long 0x0 20. "PK_P256,'Support ECC P256 acceleration'" "0,1" newline bitfld.long 0x0 17. "PK_BINARYFIELD,'Support binary field'" "0,1" newline bitfld.long 0x0 16. "PK_PRIMEFIELD,'Support prime field'" "0,1" newline hexmask.long.byte 0x0 12.--15. 1. "PK_NBMULT,'Number of multipliers: 0x0: 1 multiplier 0x1: 4 multipliers 0x2: 16 multipliers 0x4: 64 multipliers 0x8: 256 multipliers'" newline hexmask.long.word 0x0 0.--11. 1. "PK_MAXOPSIZE,'Maximum operand size (number of bytes) 4096 bytes'" group.long 0x9C++0xB line.long 0x0 "CE0_PK_RESULTS_CTRL,CE0_PK_RESULTS_CTRL" hexmask.long.word 0x0 16.--31. 1. "PKE_RESULTS_OP_LEN,'pke results each operand length in bytes'" newline hexmask.long.word 0x0 0.--15. 1. "PKE_RESULTS_OP_SELECT,'pke results output select each bit correspnding to the operand position of the pke data memory'" line.long 0x4 "CE0_PK_RESULTS_DST_ADDR,CE0_PK_RESULTS_DST_ADDR" hexmask.long 0x4 0.--31. 1. "PKE_RESULTS_DST_ADDR,'pke results dma dst address low 32bit'" line.long 0x8 "CE0_PK_RESULTS_DST_ADDR_H,CE0_PK_RESULTS_DST_ADDR_H" newline bitfld.long 0x8 8.--10. "PKE_RESULTS_DST_TYPE,'pke results dma dst data type 011: CE SRAM Secure AREA 001:CE SRAM public area 000:external memories other: reserved'" "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x8 0.--7. 1. "PKE_RESULTS_DST_ADDR_H,'pke results dma dst address high 8bit'" rgroup.long 0x100++0x3 line.long 0x0 "CE0_TRNG_STATUS,CE0_TRNG_STATUS" newline bitfld.long 0x0 1. "RNG_SEQ_RUNNING,'1: the rng sequencer is running currently 0: rng sequencer is in idle status'" "rng sequencer is in idle status',the rng sequencer is running currently" newline bitfld.long 0x0 0. "RNG_READY,'1: the value in the random number register of CE0 is valid" "?,the value in the random number register of CE0.." repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) rgroup.long ($2+0x104)++0x3 line.long 0x0 "CE0_TRNG_NUM$1,CE0_TRNG_NUM0" hexmask.long 0x0 0.--31. 1. "TRNG_NUM0,CE0 the random number0 value" repeat.end rgroup.long 0x114++0x3 line.long 0x0 "CE0_HRNG_NUM,CE0_HRNG_NUM" hexmask.long 0x0 0.--31. 1. "HRNG_NUM,CE0 the hybird random number value" group.long 0x120++0xB line.long 0x0 "CE0_SKC_CTRL,CE0_SKC_CTRL" newline bitfld.long 0x0 8.--10. "SKC_CMD,the command of SKC 001: generate random number 010: erase key contrainer" "?,generate random number,?,?,?,?,?,?" newline bitfld.long 0x0 0. "SKC_GO,CE0 secure FSM start trigger" "0,1" line.long 0x4 "CE0_SKC_RNG_ADDR,CE0_SKC_RNG_ADDR" newline bitfld.long 0x4 24. "SKC_RNG_SECURE,CE0 1: random number generated to secure area 0 : in public area" "in public area,random number generated to secure area" newline hexmask.long.byte 0x4 16.--22. 1. "SKC_RNG_LEN,'numbers of bits to generate into sram granularity is 256 bit'" newline hexmask.long.word 0x4 0.--12. 1. "SKC_RNG_ADDR,CE0 random number generation address in CE sram the address granularity is 8 bytes" line.long 0x8 "CE0_SKC_KEYBLOB_CTRL,CE0_SKC_KEYBLOB_CTRL" newline bitfld.long 0x8 0. "SKC_KEYBLOB_CTRL,CE0 key blob control 1: is key blob :0 : is the secret data" "?,is key blob :0 : is the secret data" group.long 0x140++0x3 line.long 0x0 "CE0_INTEN,CE0_INTEN" newline bitfld.long 0x0 13. "DMA_FIFOERROR_INTEN,DMA fifo error interrupt" "0,1" newline bitfld.long 0x0 12. "PKE_INTEGRITY_ERROR_INTEN,ALGORITHM_INTEGRITY interrupt" "0,1" newline bitfld.long 0x0 11. "HASH_INTEGRITY_ERROR_INTEN,ALGORITHM_INTEGRITY_ERROR interrupt" "0,1" newline bitfld.long 0x0 10. "CIPHER_INTEGRITY_ERROR_INTEN,ALGORITHM_INTEGRITY_ERROR interrupt" "0,1" newline bitfld.long 0x0 9. "SKC_INTEGRITY_ERROR_INTEN,SKC_INTEGRITY_ERROR interrupt" "0,1" newline bitfld.long 0x0 8. "DMA_INTEGRITY_ERROR_INTEN,ALGORITHM_INTEGRITY interrupt" "0,1" newline bitfld.long 0x0 4. "PKE_DONE_INTEN,PKE_DONE interrupt" "0,1" newline bitfld.long 0x0 3. "HASH_DONE_INTEN,HASH_DONE interrupt" "0,1" newline bitfld.long 0x0 2. "CIPHER_DONE_INTEN,CIPHER_DONE_INTEN" "0,1" newline bitfld.long 0x0 1. "SKC_DONE_INTEN,KEYgen done interrupt enable" "0,1" newline bitfld.long 0x0 0. "DMA_DONE_INTEN,DMA_DONE interrupt" "0,1" rgroup.long 0x144++0x3 line.long 0x0 "CE0_INTSTAT,CE0_INTSTAT" newline bitfld.long 0x0 13. "DMA_FIFOERROR_INTSTAT,SSRAM_DMAFIFO error interrupt" "0,1" newline bitfld.long 0x0 12. "PKE_INTEGRITY_ERROR_INTSTAT,ALGORITHM_INTEGRITY interrupt" "0,1" newline bitfld.long 0x0 11. "HASH_INTEGRITY_ERROR_INTSTAT,ALGORITHM_INTEGRITY_ERROR interrupt" "0,1" newline bitfld.long 0x0 10. "CIPHER_INTEGRITY_ERROR_INTSTAT,ALGORITHM_INTEGRITY_ERROR interrupt" "0,1" newline bitfld.long 0x0 9. "SKC_INTEGRITY_ERROR_INTSTAT,SKC_INTEGRITY_ERROR interrupt" "0,1" newline bitfld.long 0x0 8. "DMA_INTEGRITY_ERROR_INTSTAT,ALGORITHM_INTEGRITY interrupt" "0,1" newline bitfld.long 0x0 4. "PKE_DONE_INTSTAT,PKE_DONE interrupt" "0,1" newline bitfld.long 0x0 3. "HASH_DONE_INTSTAT,HASH_DONE interrupt" "0,1" newline bitfld.long 0x0 2. "CIPHER_DONE_INTSTAT,CIPHER_DONE_INTSTATE" "0,1" newline bitfld.long 0x0 1. "SKC_DONE_INTSTAT,KEYgen done interrupt enable" "0,1" newline bitfld.long 0x0 0. "DMA_DONE_INTSTAT,DMA_DONE interrupt" "0,1" group.long 0x148++0x3 line.long 0x0 "CE0_INTCLR,CE0_INTCLR" newline bitfld.long 0x0 13. "DMA_FIFOERROR_INTCLR,SSRAM_DMAFIFO error interrupt" "0,1" newline bitfld.long 0x0 12. "PKE_INTEGRITY_ERROR_INTCLR,ALGORITHM_INTEGRITY interrupt" "0,1" newline bitfld.long 0x0 11. "HASH_INTEGRITY_ERROR_INTCLR,ALGORITHM_INTEGRITY_ERROR interrupt" "0,1" newline bitfld.long 0x0 10. "CIPHER_INTEGRITY_ERROR_INTCLR,ALGORITHM_INTEGRITY_ERROR interrupt" "0,1" newline bitfld.long 0x0 9. "SKC_INTEGRITY_ERROR_INTCLR,SKC_INTEGRITY_ERROR interrupt" "0,1" newline bitfld.long 0x0 8. "DMA_INTEGRITY_ERROR_INTCLR,ALGORITHM_INTEGRITY interrupt" "0,1" newline bitfld.long 0x0 4. "PKE_DONE_INTCLR,PKE_DONE interrupt" "0,1" newline bitfld.long 0x0 3. "HASH_DONE_INTCLR,HASH_DONE interrupt" "0,1" newline bitfld.long 0x0 2. "CIPHER_DONE_INTCLR,CIPHER_DONE_INTCLRE" "0,1" newline bitfld.long 0x0 1. "SKC_DONE_INTCLR,KEYgen done interrupt enable" "0,1" newline bitfld.long 0x0 0. "DMA_DONE_INTCLR,DMA_DONE interrupt" "0,1" rgroup.long 0x1000++0x7 line.long 0x0 "CE1_STAT,CE1 working status" newline bitfld.long 0x0 5. "PKE_BUSY,1: PKE is busy 0:PKE is idle" "?,PKE is busy 0:PKE is idle" newline bitfld.long 0x0 4. "GENKEY_BUSY,1. CE1 generate key function is busy" "0,1" newline bitfld.long 0x0 3. "HASH_BUSY,1: the HASH of CE1 is busy" "?,the HASH of CE1 is busy" newline bitfld.long 0x0 2. "CIPHER_BUSY,1 the CIPHER of CE1 is busy" "0,1" newline bitfld.long 0x0 1. "GETRNDNUM_BUSY,1: get random number function of CE1 is busy" "?,get random number function of CE1 is busy" newline bitfld.long 0x0 0. "DMA_BUSY,1: the DMA of CE1 is busy 0: the DMA of CE1 is idle" "the DMA of CE1 is idle,the DMA of CE1 is busy" line.long 0x4 "CE1_ERRSTAT,CE1 error status" newline hexmask.long.byte 0x4 24.--27. 1. "SKC_ERR_STAT,'the error status of skc sequencer the bit 0 ~ 3 are [sram wr err] [ rand number fetch err] [ secure violation occurs] [reserved]'" newline bitfld.long 0x4 19. "SSRAM_ERR_STAT,'the error status of CE sram" "0,1" newline bitfld.long 0x4 16.--18. "DMA_ERR_STAT,'the error status of dma sequencer the bit of 0 -2 are [sram_rw_err] [wdma ch err] [rdma ch err]'" "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x4 8.--13. 1. "CIPHER_ERR_STAT,'the error status of cipher sequencer the bit 0 - 4 are [key_port_err] [rdma_ch_err] [wdma_ch_err] [sram_wr_err] [sram_rd_err] [decryption from secure to non-secure]'" newline hexmask.long.byte 0x4 0.--3. 1. "HASH_ERR_STAT,'the error status of hash sequencer the bit 0 ~ 3 are [sram_wr_err] [sram rd err] [rdma_err] [wdma err]'" group.long 0x100C++0x3F line.long 0x0 "CE1_CIPHER_CTRL,CE1 cipher control register" bitfld.long 0x0 31. "CIPHER_HEADER_SAVE,1 the header will be saved into dst memory 0: header will not be saved" "header will not be saved,?" newline bitfld.long 0x0 28.--29. "CIPHER_KEY2TYPE,key 2 type 10: input keyport 00: secure sram public area 01: secure area others: reserved" "secure sram public area,secure area others: reserved,?,?" newline bitfld.long 0x0 25.--26. "CIPHER_KEYTYPE,key type 10: input keyport 00: secure sram public area 01: secure area others: reserved" "secure sram public area,secure area others: reserved,?,?" newline hexmask.long.word 0x0 16.--24. 1. "AESMODE,'AES mode XTS : 010000000 ECB : 000000001 CBC : 000000010 CTR : 000000100 CFB : 000001000 OFB : 000010000 CCM : 000100000 GCM : 001000000 XTS : 010000000 CMAC: 100000000'" newline bitfld.long 0x0 13. "CIPHER_SAVE,0: normal mode last part of the message 1: operation context will be saved at the end of operation" "normal mode last part of the message,operation context will be saved at the end of.." newline bitfld.long 0x0 12. "CIPHER_LOAD,0 : normal mode first start of the message 1: operation restart from previously save context" "normal mode first start of the message,operation restart from previously save context" newline bitfld.long 0x0 11. "CIPHER_DECKEYCAL,0 use the input key for decryption operations 1: use the pre-calculation of the key is done before" "?,use the pre-calculation of the key is done before" newline bitfld.long 0x0 9.--10. "CIPHER_KEYSIZE,key size 00: 128bit key 01: 256 bit key 10: 192bit key 11: reserved" "0,1,2,3" newline bitfld.long 0x0 8. "CIPHERMODE,0 encryption 1 decryption" "0,1" newline bitfld.long 0x0 0. "CIPHER_GO,'write 1 to this bit will start the cipher operation'" "0,1" line.long 0x4 "CE1_CIPHER_HEADER_LEN,CE1 cipher header length register" hexmask.long 0x4 0.--31. 1. "CIPHER_HEADER_LEN,'cipher data header length in bytes'" line.long 0x8 "CE1_CIPHER_KEY_ADDR,CE1 cipher key addr register" hexmask.long.word 0x8 16.--31. 1. "CIPHER_KEY2_ADDR,key2 address in secure SRAM or keyport" newline hexmask.long.word 0x8 0.--15. 1. "CIPHER_KEY_ADDR,CIPHER_KEY_ADDR address in secure SRAM or keyport" line.long 0xC "CE1_CIPHER_SRC_ADDR,CE1 cipher source data addr register" hexmask.long 0xC 0.--31. 1. "CIPHER_SRC_ADDR,cipher data source address in bytes" line.long 0x10 "CE1_CIPHER_SRC_ADDR_H,CE1 cipher source data addr high register" newline bitfld.long 0x10 8.--10. "CIPHER_SRC_TYPE,011: CE SRAM Secure AREA 001:CE SRAM public area 000:external memories other: reserved" "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x10 0.--7. 1. "CIPHER_SRC_ADDR_H,the high part of CE1 cipher source address" line.long 0x14 "CE1_CIPHER_DST_ADDR,CE1 cipher destination data addr register" hexmask.long 0x14 0.--31. 1. "CIPHER_DST_ADDR,CE1 cipher data destination address" line.long 0x18 "CE1_CIPHER_DST_ADDR_H,CE1 cipher destination data addr high register" newline bitfld.long 0x18 8.--10. "CIPHER_DST_TYPE,011: CE SRAM Secure AREA 001:CE SRAM public area 000:external memories other: reserved" "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x18 0.--7. 1. "CIPHER_DST_ADDR_H,CE1 cipher data destination address" line.long 0x1C "CE1_CIPHER_IV_CONTEXT_ADDR,CE1 cipher IV and context addr register" hexmask.long.word 0x1C 16.--31. 1. "CIPHER_CONTEXT_ADDR,CIPHER context storage address the context is always stored into SRAM secure area" newline hexmask.long.word 0x1C 0.--15. 1. "CIPHER_IV_ADDR,CIPHER iv storage address the iv is always stored into SRAM secure area" line.long 0x20 "CE1_CIPHER_PAYLOAD_LEN,CE1 cipher payload length register" hexmask.long 0x20 0.--31. 1. "CIPHER_PAYLOAD_LEN,CIPHER_PAYLOAD_LEN NOT including the header length in byte" line.long 0x24 "CE1_HASH_CTRL,CE1 hash control register" newline bitfld.long 0x24 24. "HASH_HMAC_EN,1: hmac is enabled 0: hmac is disabled" "hmac is disabled,hmac is enabled" newline bitfld.long 0x24 19. "HASH_KEY,1 need to load key 0 donot load key" "0,1" newline bitfld.long 0x24 18. "HASH_INIT_SECURE,1 load IV from secure area 0: load IV from public area" "load IV from public area,?" newline bitfld.long 0x24 17. "HASH_INIT,1 load IV for the hash 0 not load initial vector" "0,1" newline bitfld.long 0x24 16. "HASH_SHAUPDATE,0 final SHA224 output 7 words and SHA384 output 6 words 1: update SHA224/384 output 8 words please don't use this feature in hmac mode" "?,update SHA224/384 output 8 words please don't.." newline bitfld.long 0x24 15. "HASH_PADDINGEN,0: bypass padding logic 1: use hw padding logic" "bypass padding logic,use hw padding logic" newline hexmask.long.byte 0x24 8.--14. 1. "HASH_MODE,0000001 MD5 0000010 SHA1 0000100 SHA224 0001000 SHA256 0010000 SHA384 0100000 SHA512 1000000 SM3" newline bitfld.long 0x24 0. "HASH_GO,HASH Calculation start" "0,1" line.long 0x28 "CE1_HASH_KEYIV_ADDR,CE1 hash key and IV address register" hexmask.long.word 0x28 16.--31. 1. "HASH_KEY_ADDR,HASH_KEY address" newline hexmask.long.word 0x28 0.--15. 1. "HASH_IV_ADDR,HASH initial vection address" line.long 0x2C "CE1_HMAC_KEY_CTRL,CE1 hmac key control register" newline bitfld.long 0x2C 16.--17. "HMAC_KEY_TYPE,10 from key interface 01: from SRAM secure area 00 from SRAM public area" "?,from SRAM secure area 00 from SRAM public area,?,?" newline hexmask.long.word 0x2C 0.--15. 1. "HMAC_KEY_LEN,CE1 hash key length in CE SRAM" line.long 0x30 "CE1_HASH_CALC_LEN,CE1 hash calcluation length register" hexmask.long 0x30 0.--31. 1. "HASH_CALC_LEN,CE1 hash calculation length in bytes" line.long 0x34 "CE1_HASH_SRC_ADDR,CE1 hash source address register" hexmask.long 0x34 0.--31. 1. "HASH_SRC_ADDR,CE1 HASH SRC ADDR" line.long 0x38 "CE1_HASH_SRC_ADDR_H,CE1 hash source address high register" newline bitfld.long 0x38 8.--10. "HASH_SRC_TYPE,000: external memory 001: CE SRAM public area 011 CE sram secure area 1xx: SKC key interface space" "external memory,CE SRAM public area 011 CE sram secure area 1xx:..,?,?,?,?,?,?" newline hexmask.long.byte 0x38 0.--7. 1. "HASH_SRC_ADDR_H,the high part of CE1 hash src address" line.long 0x3C "CE1_HASH_DST_ADDR,CE1 hash destination address register" newline bitfld.long 0x3C 16.--18. "HASH_DST_TYPE,011 internal secure SRAM 001 public area in secure ram 1xx key interface" "0,1,2,3,4,5,6,7" newline hexmask.long.word 0x3C 0.--15. 1. "HASH_DST_ADDR,the dst address in secure SRAM" group.long 0x1050++0x17 line.long 0x0 "CE1_DMA_CTRL,CE1_DMA_CTRL" newline bitfld.long 0x0 10. "DMA_DONEINTEN,1 the interrupt will be generated if the DMA operation is done" "0,1" newline rbitfld.long 0x0 9. "DMA_CMDFIFO_FULL,cmd fifo is full" "0,1" newline rbitfld.long 0x0 8. "DMA_CMDFIFO_EMPTY,cmd fifo is empty" "0,1" newline bitfld.long 0x0 0. "DMA_GO,write 1 to this register start CE1 DMA operation" "0,1" line.long 0x4 "CE1_DMA_SRC_ADDR,CE1 dma source address register" hexmask.long 0x4 0.--31. 1. "DMA_SRC_ADDR,CE1 dma source addr" line.long 0x8 "CE1_DMA_SRC_ADDR_H,CE1 dma source address high register" newline bitfld.long 0x8 8.--10. "DMA_SRC_TYPE,011: CE SRAM Secure AREA 001:CE SRAM public area 000:external memories 010: PKE operand mem other: reserved" "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x8 0.--7. 1. "DMA_SRC_ADDR_H,CE1 dma source addr high part" line.long 0xC "CE1_DMA_DST_ADDR,CE1 dma destination address register" hexmask.long 0xC 0.--31. 1. "DMA_DST_ADDR,CE1 DMA DST ADDR" line.long 0x10 "CE1_DMA_DST_ADDR_H,CE1 dma destination address high register" newline bitfld.long 0x10 8.--10. "DMA_DST_TYPE,011: CE SRAM Secure AREA 001:CE SRAM public area 000:external memories 010: PKE operand mem other: reserved" "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x10 0.--7. 1. "DMA_DST_ADDR_H,CE1 DMA DST ADDR high part" line.long 0x14 "CE1_DMA_LEN,CE1 dma transer length register" newline hexmask.long.word 0x14 0.--15. 1. "DMA_LEN,DMA transfer length in byte" group.long 0x1080++0xB line.long 0x0 "CE1_PK_POINTERREG,CE1_PK_POINTERREG" newline hexmask.long.byte 0x0 24.--27. 1. "PK_OPPTRN,'When executing primitive arithmetic operations" newline hexmask.long.byte 0x0 16.--19. 1. "PK_OPPTRC,'When executing primitive arithmetic operations" newline hexmask.long.byte 0x0 8.--11. 1. "PK_OPPTRB,'When executing primitive arithmetic operations" newline hexmask.long.byte 0x0 0.--3. 1. "PK_OPPTRA,'When executing primitive arithmetic operations" line.long 0x4 "CE1_PK_COMMANDREG,CE1_PK_COMMANDREG" bitfld.long 0x4 31. "PK_CALCR2,PK_CALCR2" "0,1" newline bitfld.long 0x4 30. "PK_FLAGB,'B See routine description'" "0,1" newline bitfld.long 0x4 29. "PK_FLAGA,'A See routine description'" "0,1" newline bitfld.long 0x4 28. "PK_SWAP,'bytes Swap the bytes on AHB interface: '0': Native format (little endian) '1': Byte swapped (big endian) See also section 4.2.1. This bit must be programmed before writing/reading any data in data memory.'" "0,1" newline bitfld.long 0x4 27. "PK_BUFFER,PK_BUFFER" "0,1" newline bitfld.long 0x4 26. "PK_EDWARDS,'Enable Edwards curve (see routine description)'" "0,1" newline bitfld.long 0x4 25. "PK_RANDPROJ,'Enable randomization of projective coordinates (counter-measure)'" "0,1" newline bitfld.long 0x4 24. "PK_RANDKE,'Enable randomization of exponent/scalar (counter-measure)'" "0,1" newline hexmask.long.byte 0x4 20.--23. 1. "PK_SELCURVE,'Enable accelerator for specific curve modulus: 0x0: No acceleration (default) 0x1: P256 0x2: P384 0x3: P521/E-521 0x4: P192 0x5: Curve25519/Ed25519 This field has no effect when the optional acceleration hardware is not included.'" newline hexmask.long.word 0x4 8.--18. 1. "PK_SIZE,'Of Operands (in data memory) This field defines the size (= number of bytes minus one) of the operands for the current operation. Possible values are limited by the maximum supported operand size. Examples: 0x014 -> ECC on curve K-163 0x01F ->.." newline bitfld.long 0x4 7. "PK_FIELD,''0': Field is GF(p) '1': Field is GF(2m)'" "0,1" newline hexmask.long.byte 0x4 0.--6. 1. "PK_TYPE,'of operation This field defines the operation to be performed. See table below for details.'" line.long 0x8 "CE1_PKE_CTRL,CE1_PKE_CTRL" newline bitfld.long 0x8 2. "PKE_SOFT_RST,'Writing a 1 to this bit will reset the pke_seq logic'" "0,1" newline bitfld.long 0x8 1. "PK_CLRMEMAFTEROP,'Writing a 1 to this bit will make the pke to clear its memories after all operations are complete'" "0,1" newline bitfld.long 0x8 0. "PKE_GO,'Writing a '1' starts the processing.'" "0,1" rgroup.long 0x108C++0x3 line.long 0x0 "CE1_PK_STATUSREG,CE1_PK_STATUSREG" newline bitfld.long 0x0 17. "PK_INTERRUPT,'status This bit reflects the IRQ output value. It is set to '1' when the operation is finished. It is cleared when the CPU writes the bit 1 of Control Register.'" "0,1" newline bitfld.long 0x0 16. "PK_BUSY,'This bit reflects the BUSY output value. It is set to '1' when the operation starts and it is cleared when the operation is finished.'" "0,1" newline bitfld.long 0x0 13. "PK_NOTQUADRATICRESIDUE,PK_NOTQUADRATICRESIDUE" "0,1" newline bitfld.long 0x0 12. "PK_COMPOSITE,PK_COMPOSITE" "0,1" newline bitfld.long 0x0 11. "PK_NOTINVERTIBLE,PK_NOTINVERTIBLE" "0,1" newline bitfld.long 0x0 10. "PK_PARAM_AB_NOTVALID,PK_PARAM_AB_NOTVALID" "0,1" newline bitfld.long 0x0 9. "PK_SIGNATURE_NOTVALID,PK_SIGNATURE_NOTVALID" "0,1" newline bitfld.long 0x0 8. "PK_NOTIMPLEMENTED,PK_NOTIMPLEMENTED" "0,1" newline bitfld.long 0x0 7. "PK_PARAM_N_NOTVALID,PK_PARAM_N_NOTVALID" "0,1" newline bitfld.long 0x0 6. "PK_COUPLE_NOTVALID,PK_COUPLE_NOTVALID" "0,1" newline bitfld.long 0x0 5. "PK_POINT_PX_ATINFINITY,PK_POINT_PX_ATINFINITY" "0,1" newline bitfld.long 0x0 4. "PK_POINT_PX_NOTONCURVE,PK_POINT_PX_NOTONCURVE" "0,1" newline hexmask.long.byte 0x0 0.--3. 1. "PK_FAIL_ADDRESS,'These bits indicate which data location generated the error flag. They are not available for all error flags.'" group.long 0x1094++0x3 line.long 0x0 "CE1_PK_TIMER,CE1_PK_TIMER" hexmask.long 0x0 0.--31. 1. "PK_TIMER,'The timer counts the number of clock cycles when the PK engine is busy. It is not cleared automatically. It can be written by software (when the PK is idle). The register is updated at the end of every operation (reading it when the PK engine.." rgroup.long 0x1098++0x3 line.long 0x0 "CE1_PK_HWCONFIGREG,CE1_PK_HWCONFIGREG" bitfld.long 0x0 31. "PK_DISABLECM,'State of DisableCM input (high when counter-measures are disabled)'" "0,1" newline bitfld.long 0x0 24. "PK_25519,'Support Curve25519/Ed25519 acceleration'" "0,1" newline bitfld.long 0x0 23. "PK_P192,'Support ECC P192 acceleration'" "0,1" newline bitfld.long 0x0 22. "PK_P521,'Support ECC P521 acceleration'" "0,1" newline bitfld.long 0x0 21. "PK_P384,'Support ECC P384 acceleration'" "0,1" newline bitfld.long 0x0 20. "PK_P256,'Support ECC P256 acceleration'" "0,1" newline bitfld.long 0x0 17. "PK_BINARYFIELD,'Support binary field'" "0,1" newline bitfld.long 0x0 16. "PK_PRIMEFIELD,'Support prime field'" "0,1" newline hexmask.long.byte 0x0 12.--15. 1. "PK_NBMULT,'Number of multipliers: 0x0: 1 multiplier 0x1: 4 multipliers 0x2: 16 multipliers 0x4: 64 multipliers 0x8: 256 multipliers'" newline hexmask.long.word 0x0 0.--11. 1. "PK_MAXOPSIZE,'Maximum operand size (number of bytes) 4096 bytes'" group.long 0x109C++0xB line.long 0x0 "CE1_PK_RESULTS_CTRL,CE1_PK_RESULTS_CTRL" hexmask.long.word 0x0 16.--31. 1. "PKE_RESULTS_OP_LEN,'pke results each operand length in bytes'" newline hexmask.long.word 0x0 0.--15. 1. "PKE_RESULTS_OP_SELECT,'pke results output select each bit correspnding to the operand position of the pke data memory'" line.long 0x4 "CE1_PK_RESULTS_DST_ADDR,CE1_PK_RESULTS_DST_ADDR" hexmask.long 0x4 0.--31. 1. "PKE_RESULTS_DST_ADDR,'pke results dma dst address low 32bit'" line.long 0x8 "CE1_PK_RESULTS_DST_ADDR_H,CE1_PK_RESULTS_DST_ADDR_H" newline bitfld.long 0x8 8.--10. "PKE_RESULTS_DST_TYPE,'pke results dma dst data type 011: CE SRAM Secure AREA 001:CE SRAM public area 000:external memories other: reserved'" "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x8 0.--7. 1. "PKE_RESULTS_DST_ADDR_H,'pke results dma dst address high 8bit'" rgroup.long 0x1100++0x3 line.long 0x0 "CE1_TRNG_STATUS,CE1_TRNG_STATUS" newline bitfld.long 0x0 1. "RNG_SEQ_RUNNING,'1: the rng sequencer is running currently 0: rng sequencer is in idle status'" "rng sequencer is in idle status',the rng sequencer is running currently" newline bitfld.long 0x0 0. "RNG_READY,'1: the value in the random number register of CE1 is valid" "?,the value in the random number register of CE1.." repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) rgroup.long ($2+0x1104)++0x3 line.long 0x0 "CE1_TRNG_NUM$1,CE1_TRNG_NUM0" hexmask.long 0x0 0.--31. 1. "TRNG_NUM0,CE1 the random number0 value" repeat.end rgroup.long 0x1114++0x3 line.long 0x0 "CE1_HRNG_NUM,CE1_HRNG_NUM" hexmask.long 0x0 0.--31. 1. "HRNG_NUM,CE1 the hybird random number value" group.long 0x1120++0xB line.long 0x0 "CE1_SKC_CTRL,CE1_SKC_CTRL" newline bitfld.long 0x0 8.--10. "SKC_CMD,the command of SKC 001: generate random number 010: erase key contrainer" "?,generate random number,?,?,?,?,?,?" newline bitfld.long 0x0 0. "SKC_GO,CE1 secure FSM start trigger" "0,1" line.long 0x4 "CE1_SKC_RNG_ADDR,CE1_SKC_RNG_ADDR" newline bitfld.long 0x4 24. "SKC_RNG_SECURE,CE1 1: random number generated to secure area 0 : in public area" "in public area,random number generated to secure area" newline hexmask.long.byte 0x4 16.--22. 1. "SKC_RNG_LEN,'numbers of bits to generate into sram granularity is 256 bit'" newline hexmask.long.word 0x4 0.--12. 1. "SKC_RNG_ADDR,CE1 random number generation address in CE sram the address granularity is 8 bytes" line.long 0x8 "CE1_SKC_KEYBLOB_CTRL,CE1_SKC_KEYBLOB_CTRL" newline bitfld.long 0x8 0. "SKC_KEYBLOB_CTRL,CE1 key blob control 1: is key blob :0 : is the secret data" "?,is key blob :0 : is the secret data" group.long 0x1140++0x3 line.long 0x0 "CE1_INTEN,CE1_INTEN" newline bitfld.long 0x0 13. "DMA_FIFOERROR_INTEN,DMA fifo error interrupt" "0,1" newline bitfld.long 0x0 12. "PKE_INTEGRITY_ERROR_INTEN,ALGORITHM_INTEGRITY interrupt" "0,1" newline bitfld.long 0x0 11. "HASH_INTEGRITY_ERROR_INTEN,ALGORITHM_INTEGRITY_ERROR interrupt" "0,1" newline bitfld.long 0x0 10. "CIPHER_INTEGRITY_ERROR_INTEN,ALGORITHM_INTEGRITY_ERROR interrupt" "0,1" newline bitfld.long 0x0 9. "SKC_INTEGRITY_ERROR_INTEN,SKC_INTEGRITY_ERROR interrupt" "0,1" newline bitfld.long 0x0 8. "DMA_INTEGRITY_ERROR_INTEN,ALGORITHM_INTEGRITY interrupt" "0,1" newline bitfld.long 0x0 4. "PKE_DONE_INTEN,PKE_DONE interrupt" "0,1" newline bitfld.long 0x0 3. "HASH_DONE_INTEN,HASH_DONE interrupt" "0,1" newline bitfld.long 0x0 2. "CIPHER_DONE_INTEN,CIPHER_DONE_INTEN" "0,1" newline bitfld.long 0x0 1. "SKC_DONE_INTEN,KEYgen done interrupt enable" "0,1" newline bitfld.long 0x0 0. "DMA_DONE_INTEN,DMA_DONE interrupt" "0,1" rgroup.long 0x1144++0x3 line.long 0x0 "CE1_INTSTAT,CE1_INTSTAT" newline bitfld.long 0x0 13. "DMA_FIFOERROR_INTSTAT,SSRAM_DMAFIFO error interrupt" "0,1" newline bitfld.long 0x0 12. "PKE_INTEGRITY_ERROR_INTSTAT,ALGORITHM_INTEGRITY interrupt" "0,1" newline bitfld.long 0x0 11. "HASH_INTEGRITY_ERROR_INTSTAT,ALGORITHM_INTEGRITY_ERROR interrupt" "0,1" newline bitfld.long 0x0 10. "CIPHER_INTEGRITY_ERROR_INTSTAT,ALGORITHM_INTEGRITY_ERROR interrupt" "0,1" newline bitfld.long 0x0 9. "SKC_INTEGRITY_ERROR_INTSTAT,SKC_INTEGRITY_ERROR interrupt" "0,1" newline bitfld.long 0x0 8. "DMA_INTEGRITY_ERROR_INTSTAT,ALGORITHM_INTEGRITY interrupt" "0,1" newline bitfld.long 0x0 4. "PKE_DONE_INTSTAT,PKE_DONE interrupt" "0,1" newline bitfld.long 0x0 3. "HASH_DONE_INTSTAT,HASH_DONE interrupt" "0,1" newline bitfld.long 0x0 2. "CIPHER_DONE_INTSTAT,CIPHER_DONE_INTSTATE" "0,1" newline bitfld.long 0x0 1. "SKC_DONE_INTSTAT,KEYgen done interrupt enable" "0,1" newline bitfld.long 0x0 0. "DMA_DONE_INTSTAT,DMA_DONE interrupt" "0,1" group.long 0x1148++0x3 line.long 0x0 "CE1_INTCLR,CE1_INTCLR" newline bitfld.long 0x0 13. "DMA_FIFOERROR_INTCLR,SSRAM_DMAFIFO error interrupt" "0,1" newline bitfld.long 0x0 12. "PKE_INTEGRITY_ERROR_INTCLR,ALGORITHM_INTEGRITY interrupt" "0,1" newline bitfld.long 0x0 11. "HASH_INTEGRITY_ERROR_INTCLR,ALGORITHM_INTEGRITY_ERROR interrupt" "0,1" newline bitfld.long 0x0 10. "CIPHER_INTEGRITY_ERROR_INTCLR,ALGORITHM_INTEGRITY_ERROR interrupt" "0,1" newline bitfld.long 0x0 9. "SKC_INTEGRITY_ERROR_INTCLR,SKC_INTEGRITY_ERROR interrupt" "0,1" newline bitfld.long 0x0 8. "DMA_INTEGRITY_ERROR_INTCLR,ALGORITHM_INTEGRITY interrupt" "0,1" newline bitfld.long 0x0 4. "PKE_DONE_INTCLR,PKE_DONE interrupt" "0,1" newline bitfld.long 0x0 3. "HASH_DONE_INTCLR,HASH_DONE interrupt" "0,1" newline bitfld.long 0x0 2. "CIPHER_DONE_INTCLR,CIPHER_DONE_INTCLRE" "0,1" newline bitfld.long 0x0 1. "SKC_DONE_INTCLR,KEYgen done interrupt enable" "0,1" newline bitfld.long 0x0 0. "DMA_DONE_INTCLR,DMA_DONE interrupt" "0,1" rgroup.long 0x2000++0x7 line.long 0x0 "CE2_STAT,CE2 working status" newline bitfld.long 0x0 5. "PKE_BUSY,1: PKE is busy 0:PKE is idle" "?,PKE is busy 0:PKE is idle" newline bitfld.long 0x0 4. "GENKEY_BUSY,1. CE2 generate key function is busy" "0,1" newline bitfld.long 0x0 3. "HASH_BUSY,1: the HASH of CE2 is busy" "?,the HASH of CE2 is busy" newline bitfld.long 0x0 2. "CIPHER_BUSY,1 the CIPHER of CE2 is busy" "0,1" newline bitfld.long 0x0 1. "GETRNDNUM_BUSY,1: get random number function of CE2 is busy" "?,get random number function of CE2 is busy" newline bitfld.long 0x0 0. "DMA_BUSY,1: the DMA of CE2 is busy 0: the DMA of CE2 is idle" "the DMA of CE2 is idle,the DMA of CE2 is busy" line.long 0x4 "CE2_ERRSTAT,CE2 error status" newline hexmask.long.byte 0x4 24.--27. 1. "SKC_ERR_STAT,'the error status of skc sequencer the bit 0 ~ 3 are [sram wr err] [ rand number fetch err] [ secure violation occurs] [reserved]'" newline bitfld.long 0x4 19. "SSRAM_ERR_STAT,'the error status of CE sram" "0,1" newline bitfld.long 0x4 16.--18. "DMA_ERR_STAT,'the error status of dma sequencer the bit of 0 -2 are [sram_rw_err] [wdma ch err] [rdma ch err]'" "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x4 8.--13. 1. "CIPHER_ERR_STAT,'the error status of cipher sequencer the bit 0 - 4 are [key_port_err] [rdma_ch_err] [wdma_ch_err] [sram_wr_err] [sram_rd_err] [decryption from secure to non-secure]'" newline hexmask.long.byte 0x4 0.--3. 1. "HASH_ERR_STAT,'the error status of hash sequencer the bit 0 ~ 3 are [sram_wr_err] [sram rd err] [rdma_err] [wdma err]'" group.long 0x200C++0x3F line.long 0x0 "CE2_CIPHER_CTRL,CE2 cipher control register" bitfld.long 0x0 31. "CIPHER_HEADER_SAVE,1 the header will be saved into dst memory 0: header will not be saved" "header will not be saved,?" newline bitfld.long 0x0 28.--29. "CIPHER_KEY2TYPE,key 2 type 10: input keyport 00: secure sram public area 01: secure area others: reserved" "secure sram public area,secure area others: reserved,?,?" newline bitfld.long 0x0 25.--26. "CIPHER_KEYTYPE,key type 10: input keyport 00: secure sram public area 01: secure area others: reserved" "secure sram public area,secure area others: reserved,?,?" newline hexmask.long.word 0x0 16.--24. 1. "AESMODE,'AES mode XTS : 010000000 ECB : 000000001 CBC : 000000010 CTR : 000000100 CFB : 000001000 OFB : 000010000 CCM : 000100000 GCM : 001000000 XTS : 010000000 CMAC: 100000000'" newline bitfld.long 0x0 13. "CIPHER_SAVE,0: normal mode last part of the message 1: operation context will be saved at the end of operation" "normal mode last part of the message,operation context will be saved at the end of.." newline bitfld.long 0x0 12. "CIPHER_LOAD,0 : normal mode first start of the message 1: operation restart from previously save context" "normal mode first start of the message,operation restart from previously save context" newline bitfld.long 0x0 11. "CIPHER_DECKEYCAL,0 use the input key for decryption operations 1: use the pre-calculation of the key is done before" "?,use the pre-calculation of the key is done before" newline bitfld.long 0x0 9.--10. "CIPHER_KEYSIZE,key size 00: 128bit key 01: 256 bit key 10: 192bit key 11: reserved" "0,1,2,3" newline bitfld.long 0x0 8. "CIPHERMODE,0 encryption 1 decryption" "0,1" newline bitfld.long 0x0 0. "CIPHER_GO,'write 1 to this bit will start the cipher operation'" "0,1" line.long 0x4 "CE2_CIPHER_HEADER_LEN,CE2 cipher header length register" hexmask.long 0x4 0.--31. 1. "CIPHER_HEADER_LEN,'cipher data header length in bytes'" line.long 0x8 "CE2_CIPHER_KEY_ADDR,CE2 cipher key addr register" hexmask.long.word 0x8 16.--31. 1. "CIPHER_KEY2_ADDR,key2 address in secure SRAM or keyport" newline hexmask.long.word 0x8 0.--15. 1. "CIPHER_KEY_ADDR,CIPHER_KEY_ADDR address in secure SRAM or keyport" line.long 0xC "CE2_CIPHER_SRC_ADDR,CE2 cipher source data addr register" hexmask.long 0xC 0.--31. 1. "CIPHER_SRC_ADDR,cipher data source address in bytes" line.long 0x10 "CE2_CIPHER_SRC_ADDR_H,CE2 cipher source data addr high register" newline bitfld.long 0x10 8.--10. "CIPHER_SRC_TYPE,011: CE SRAM Secure AREA 001:CE SRAM public area 000:external memories other: reserved" "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x10 0.--7. 1. "CIPHER_SRC_ADDR_H,the high part of CE2 cipher source address" line.long 0x14 "CE2_CIPHER_DST_ADDR,CE2 cipher destination data addr register" hexmask.long 0x14 0.--31. 1. "CIPHER_DST_ADDR,CE2 cipher data destination address" line.long 0x18 "CE2_CIPHER_DST_ADDR_H,CE2 cipher destination data addr high register" newline bitfld.long 0x18 8.--10. "CIPHER_DST_TYPE,011: CE SRAM Secure AREA 001:CE SRAM public area 000:external memories other: reserved" "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x18 0.--7. 1. "CIPHER_DST_ADDR_H,CE2 cipher data destination address" line.long 0x1C "CE2_CIPHER_IV_CONTEXT_ADDR,CE2 cipher IV and context addr register" hexmask.long.word 0x1C 16.--31. 1. "CIPHER_CONTEXT_ADDR,CIPHER context storage address the context is always stored into SRAM secure area" newline hexmask.long.word 0x1C 0.--15. 1. "CIPHER_IV_ADDR,CIPHER iv storage address the iv is always stored into SRAM secure area" line.long 0x20 "CE2_CIPHER_PAYLOAD_LEN,CE2 cipher payload length register" hexmask.long 0x20 0.--31. 1. "CIPHER_PAYLOAD_LEN,CIPHER_PAYLOAD_LEN NOT including the header length in byte" line.long 0x24 "CE2_HASH_CTRL,CE2 hash control register" newline bitfld.long 0x24 24. "HASH_HMAC_EN,1: hmac is enabled 0: hmac is disabled" "hmac is disabled,hmac is enabled" newline bitfld.long 0x24 19. "HASH_KEY,1 need to load key 0 donot load key" "0,1" newline bitfld.long 0x24 18. "HASH_INIT_SECURE,1 load IV from secure area 0: load IV from public area" "load IV from public area,?" newline bitfld.long 0x24 17. "HASH_INIT,1 load IV for the hash 0 not load initial vector" "0,1" newline bitfld.long 0x24 16. "HASH_SHAUPDATE,0 final SHA224 output 7 words and SHA384 output 6 words 1: update SHA224/384 output 8 words please don't use this feature in hmac mode" "?,update SHA224/384 output 8 words please don't.." newline bitfld.long 0x24 15. "HASH_PADDINGEN,0: bypass padding logic 1: use hw padding logic" "bypass padding logic,use hw padding logic" newline hexmask.long.byte 0x24 8.--14. 1. "HASH_MODE,0000001 MD5 0000010 SHA1 0000100 SHA224 0001000 SHA256 0010000 SHA384 0100000 SHA512 1000000 SM3" newline bitfld.long 0x24 0. "HASH_GO,HASH Calculation start" "0,1" line.long 0x28 "CE2_HASH_KEYIV_ADDR,CE2 hash key and IV address register" hexmask.long.word 0x28 16.--31. 1. "HASH_KEY_ADDR,HASH_KEY address" newline hexmask.long.word 0x28 0.--15. 1. "HASH_IV_ADDR,HASH initial vection address" line.long 0x2C "CE2_HMAC_KEY_CTRL,CE2 hmac key control register" newline bitfld.long 0x2C 16.--17. "HMAC_KEY_TYPE,10 from key interface 01: from SRAM secure area 00 from SRAM public area" "?,from SRAM secure area 00 from SRAM public area,?,?" newline hexmask.long.word 0x2C 0.--15. 1. "HMAC_KEY_LEN,CE2 hash key length in CE SRAM" line.long 0x30 "CE2_HASH_CALC_LEN,CE2 hash calcluation length register" hexmask.long 0x30 0.--31. 1. "HASH_CALC_LEN,CE2 hash calculation length in bytes" line.long 0x34 "CE2_HASH_SRC_ADDR,CE2 hash source address register" hexmask.long 0x34 0.--31. 1. "HASH_SRC_ADDR,CE2 HASH SRC ADDR" line.long 0x38 "CE2_HASH_SRC_ADDR_H,CE2 hash source address high register" newline bitfld.long 0x38 8.--10. "HASH_SRC_TYPE,000: external memory 001: CE SRAM public area 011 CE sram secure area 1xx: SKC key interface space" "external memory,CE SRAM public area 011 CE sram secure area 1xx:..,?,?,?,?,?,?" newline hexmask.long.byte 0x38 0.--7. 1. "HASH_SRC_ADDR_H,the high part of CE2 hash src address" line.long 0x3C "CE2_HASH_DST_ADDR,CE2 hash destination address register" newline bitfld.long 0x3C 16.--18. "HASH_DST_TYPE,011 internal secure SRAM 001 public area in secure ram 1xx key interface" "0,1,2,3,4,5,6,7" newline hexmask.long.word 0x3C 0.--15. 1. "HASH_DST_ADDR,the dst address in secure SRAM" group.long 0x2050++0x17 line.long 0x0 "CE2_DMA_CTRL,CE2_DMA_CTRL" newline bitfld.long 0x0 10. "DMA_DONEINTEN,1 the interrupt will be generated if the DMA operation is done" "0,1" newline rbitfld.long 0x0 9. "DMA_CMDFIFO_FULL,cmd fifo is full" "0,1" newline rbitfld.long 0x0 8. "DMA_CMDFIFO_EMPTY,cmd fifo is empty" "0,1" newline bitfld.long 0x0 0. "DMA_GO,write 1 to this register start CE2 DMA operation" "0,1" line.long 0x4 "CE2_DMA_SRC_ADDR,CE2 dma source address register" hexmask.long 0x4 0.--31. 1. "DMA_SRC_ADDR,CE2 dma source addr" line.long 0x8 "CE2_DMA_SRC_ADDR_H,CE2 dma source address high register" newline bitfld.long 0x8 8.--10. "DMA_SRC_TYPE,011: CE SRAM Secure AREA 001:CE SRAM public area 000:external memories 010: PKE operand mem other: reserved" "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x8 0.--7. 1. "DMA_SRC_ADDR_H,CE2 dma source addr high part" line.long 0xC "CE2_DMA_DST_ADDR,CE2 dma destination address register" hexmask.long 0xC 0.--31. 1. "DMA_DST_ADDR,CE2 DMA DST ADDR" line.long 0x10 "CE2_DMA_DST_ADDR_H,CE2 dma destination address high register" newline bitfld.long 0x10 8.--10. "DMA_DST_TYPE,011: CE SRAM Secure AREA 001:CE SRAM public area 000:external memories 010: PKE operand mem other: reserved" "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x10 0.--7. 1. "DMA_DST_ADDR_H,CE2 DMA DST ADDR high part" line.long 0x14 "CE2_DMA_LEN,CE2 dma transer length register" newline hexmask.long.word 0x14 0.--15. 1. "DMA_LEN,DMA transfer length in byte" group.long 0x2080++0xB line.long 0x0 "CE2_PK_POINTERREG,CE2_PK_POINTERREG" newline hexmask.long.byte 0x0 24.--27. 1. "PK_OPPTRN,'When executing primitive arithmetic operations" newline hexmask.long.byte 0x0 16.--19. 1. "PK_OPPTRC,'When executing primitive arithmetic operations" newline hexmask.long.byte 0x0 8.--11. 1. "PK_OPPTRB,'When executing primitive arithmetic operations" newline hexmask.long.byte 0x0 0.--3. 1. "PK_OPPTRA,'When executing primitive arithmetic operations" line.long 0x4 "CE2_PK_COMMANDREG,CE2_PK_COMMANDREG" bitfld.long 0x4 31. "PK_CALCR2,PK_CALCR2" "0,1" newline bitfld.long 0x4 30. "PK_FLAGB,'B See routine description'" "0,1" newline bitfld.long 0x4 29. "PK_FLAGA,'A See routine description'" "0,1" newline bitfld.long 0x4 28. "PK_SWAP,'bytes Swap the bytes on AHB interface: '0': Native format (little endian) '1': Byte swapped (big endian) See also section 4.2.1. This bit must be programmed before writing/reading any data in data memory.'" "0,1" newline bitfld.long 0x4 27. "PK_BUFFER,PK_BUFFER" "0,1" newline bitfld.long 0x4 26. "PK_EDWARDS,'Enable Edwards curve (see routine description)'" "0,1" newline bitfld.long 0x4 25. "PK_RANDPROJ,'Enable randomization of projective coordinates (counter-measure)'" "0,1" newline bitfld.long 0x4 24. "PK_RANDKE,'Enable randomization of exponent/scalar (counter-measure)'" "0,1" newline hexmask.long.byte 0x4 20.--23. 1. "PK_SELCURVE,'Enable accelerator for specific curve modulus: 0x0: No acceleration (default) 0x1: P256 0x2: P384 0x3: P521/E-521 0x4: P192 0x5: Curve25519/Ed25519 This field has no effect when the optional acceleration hardware is not included.'" newline hexmask.long.word 0x4 8.--18. 1. "PK_SIZE,'Of Operands (in data memory) This field defines the size (= number of bytes minus one) of the operands for the current operation. Possible values are limited by the maximum supported operand size. Examples: 0x014 -> ECC on curve K-163 0x01F ->.." newline bitfld.long 0x4 7. "PK_FIELD,''0': Field is GF(p) '1': Field is GF(2m)'" "0,1" newline hexmask.long.byte 0x4 0.--6. 1. "PK_TYPE,'of operation This field defines the operation to be performed. See table below for details.'" line.long 0x8 "CE2_PKE_CTRL,CE2_PKE_CTRL" newline bitfld.long 0x8 2. "PKE_SOFT_RST,'Writing a 1 to this bit will reset the pke_seq logic'" "0,1" newline bitfld.long 0x8 1. "PK_CLRMEMAFTEROP,'Writing a 1 to this bit will make the pke to clear its memories after all operations are complete'" "0,1" newline bitfld.long 0x8 0. "PKE_GO,'Writing a '1' starts the processing.'" "0,1" rgroup.long 0x208C++0x3 line.long 0x0 "CE2_PK_STATUSREG,CE2_PK_STATUSREG" newline bitfld.long 0x0 17. "PK_INTERRUPT,'status This bit reflects the IRQ output value. It is set to '1' when the operation is finished. It is cleared when the CPU writes the bit 1 of Control Register.'" "0,1" newline bitfld.long 0x0 16. "PK_BUSY,'This bit reflects the BUSY output value. It is set to '1' when the operation starts and it is cleared when the operation is finished.'" "0,1" newline bitfld.long 0x0 13. "PK_NOTQUADRATICRESIDUE,PK_NOTQUADRATICRESIDUE" "0,1" newline bitfld.long 0x0 12. "PK_COMPOSITE,PK_COMPOSITE" "0,1" newline bitfld.long 0x0 11. "PK_NOTINVERTIBLE,PK_NOTINVERTIBLE" "0,1" newline bitfld.long 0x0 10. "PK_PARAM_AB_NOTVALID,PK_PARAM_AB_NOTVALID" "0,1" newline bitfld.long 0x0 9. "PK_SIGNATURE_NOTVALID,PK_SIGNATURE_NOTVALID" "0,1" newline bitfld.long 0x0 8. "PK_NOTIMPLEMENTED,PK_NOTIMPLEMENTED" "0,1" newline bitfld.long 0x0 7. "PK_PARAM_N_NOTVALID,PK_PARAM_N_NOTVALID" "0,1" newline bitfld.long 0x0 6. "PK_COUPLE_NOTVALID,PK_COUPLE_NOTVALID" "0,1" newline bitfld.long 0x0 5. "PK_POINT_PX_ATINFINITY,PK_POINT_PX_ATINFINITY" "0,1" newline bitfld.long 0x0 4. "PK_POINT_PX_NOTONCURVE,PK_POINT_PX_NOTONCURVE" "0,1" newline hexmask.long.byte 0x0 0.--3. 1. "PK_FAIL_ADDRESS,'These bits indicate which data location generated the error flag. They are not available for all error flags.'" group.long 0x2094++0x3 line.long 0x0 "CE2_PK_TIMER,CE2_PK_TIMER" hexmask.long 0x0 0.--31. 1. "PK_TIMER,'The timer counts the number of clock cycles when the PK engine is busy. It is not cleared automatically. It can be written by software (when the PK is idle). The register is updated at the end of every operation (reading it when the PK engine.." rgroup.long 0x2098++0x3 line.long 0x0 "CE2_PK_HWCONFIGREG,CE2_PK_HWCONFIGREG" bitfld.long 0x0 31. "PK_DISABLECM,'State of DisableCM input (high when counter-measures are disabled)'" "0,1" newline bitfld.long 0x0 24. "PK_25519,'Support Curve25519/Ed25519 acceleration'" "0,1" newline bitfld.long 0x0 23. "PK_P192,'Support ECC P192 acceleration'" "0,1" newline bitfld.long 0x0 22. "PK_P521,'Support ECC P521 acceleration'" "0,1" newline bitfld.long 0x0 21. "PK_P384,'Support ECC P384 acceleration'" "0,1" newline bitfld.long 0x0 20. "PK_P256,'Support ECC P256 acceleration'" "0,1" newline bitfld.long 0x0 17. "PK_BINARYFIELD,'Support binary field'" "0,1" newline bitfld.long 0x0 16. "PK_PRIMEFIELD,'Support prime field'" "0,1" newline hexmask.long.byte 0x0 12.--15. 1. "PK_NBMULT,'Number of multipliers: 0x0: 1 multiplier 0x1: 4 multipliers 0x2: 16 multipliers 0x4: 64 multipliers 0x8: 256 multipliers'" newline hexmask.long.word 0x0 0.--11. 1. "PK_MAXOPSIZE,'Maximum operand size (number of bytes) 4096 bytes'" group.long 0x209C++0xB line.long 0x0 "CE2_PK_RESULTS_CTRL,CE2_PK_RESULTS_CTRL" hexmask.long.word 0x0 16.--31. 1. "PKE_RESULTS_OP_LEN,'pke results each operand length in bytes'" newline hexmask.long.word 0x0 0.--15. 1. "PKE_RESULTS_OP_SELECT,'pke results output select each bit correspnding to the operand position of the pke data memory'" line.long 0x4 "CE2_PK_RESULTS_DST_ADDR,CE2_PK_RESULTS_DST_ADDR" hexmask.long 0x4 0.--31. 1. "PKE_RESULTS_DST_ADDR,'pke results dma dst address low 32bit'" line.long 0x8 "CE2_PK_RESULTS_DST_ADDR_H,CE2_PK_RESULTS_DST_ADDR_H" newline bitfld.long 0x8 8.--10. "PKE_RESULTS_DST_TYPE,'pke results dma dst data type 011: CE SRAM Secure AREA 001:CE SRAM public area 000:external memories other: reserved'" "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x8 0.--7. 1. "PKE_RESULTS_DST_ADDR_H,'pke results dma dst address high 8bit'" rgroup.long 0x2100++0x3 line.long 0x0 "CE2_TRNG_STATUS,CE2_TRNG_STATUS" newline bitfld.long 0x0 1. "RNG_SEQ_RUNNING,'1: the rng sequencer is running currently 0: rng sequencer is in idle status'" "rng sequencer is in idle status',the rng sequencer is running currently" newline bitfld.long 0x0 0. "RNG_READY,'1: the value in the random number register of CE2 is valid" "?,the value in the random number register of CE2.." repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) rgroup.long ($2+0x2104)++0x3 line.long 0x0 "CE2_TRNG_NUM$1,CE2_TRNG_NUM0" hexmask.long 0x0 0.--31. 1. "TRNG_NUM0,CE2 the random number0 value" repeat.end rgroup.long 0x2114++0x3 line.long 0x0 "CE2_HRNG_NUM,CE2_HRNG_NUM" hexmask.long 0x0 0.--31. 1. "HRNG_NUM,CE2 the hybird random number value" group.long 0x2120++0xB line.long 0x0 "CE2_SKC_CTRL,CE2_SKC_CTRL" newline bitfld.long 0x0 8.--10. "SKC_CMD,the command of SKC 001: generate random number 010: erase key contrainer" "?,generate random number,?,?,?,?,?,?" newline bitfld.long 0x0 0. "SKC_GO,CE2 secure FSM start trigger" "0,1" line.long 0x4 "CE2_SKC_RNG_ADDR,CE2_SKC_RNG_ADDR" newline bitfld.long 0x4 24. "SKC_RNG_SECURE,CE2 1: random number generated to secure area 0 : in public area" "in public area,random number generated to secure area" newline hexmask.long.byte 0x4 16.--22. 1. "SKC_RNG_LEN,'numbers of bits to generate into sram granularity is 256 bit'" newline hexmask.long.word 0x4 0.--12. 1. "SKC_RNG_ADDR,CE2 random number generation address in CE sram the address granularity is 8 bytes" line.long 0x8 "CE2_SKC_KEYBLOB_CTRL,CE2_SKC_KEYBLOB_CTRL" newline bitfld.long 0x8 0. "SKC_KEYBLOB_CTRL,CE2 key blob control 1: is key blob :0 : is the secret data" "?,is key blob :0 : is the secret data" group.long 0x2140++0x3 line.long 0x0 "CE2_INTEN,CE2_INTEN" newline bitfld.long 0x0 13. "DMA_FIFOERROR_INTEN,DMA fifo error interrupt" "0,1" newline bitfld.long 0x0 12. "PKE_INTEGRITY_ERROR_INTEN,ALGORITHM_INTEGRITY interrupt" "0,1" newline bitfld.long 0x0 11. "HASH_INTEGRITY_ERROR_INTEN,ALGORITHM_INTEGRITY_ERROR interrupt" "0,1" newline bitfld.long 0x0 10. "CIPHER_INTEGRITY_ERROR_INTEN,ALGORITHM_INTEGRITY_ERROR interrupt" "0,1" newline bitfld.long 0x0 9. "SKC_INTEGRITY_ERROR_INTEN,SKC_INTEGRITY_ERROR interrupt" "0,1" newline bitfld.long 0x0 8. "DMA_INTEGRITY_ERROR_INTEN,ALGORITHM_INTEGRITY interrupt" "0,1" newline bitfld.long 0x0 4. "PKE_DONE_INTEN,PKE_DONE interrupt" "0,1" newline bitfld.long 0x0 3. "HASH_DONE_INTEN,HASH_DONE interrupt" "0,1" newline bitfld.long 0x0 2. "CIPHER_DONE_INTEN,CIPHER_DONE_INTEN" "0,1" newline bitfld.long 0x0 1. "SKC_DONE_INTEN,KEYgen done interrupt enable" "0,1" newline bitfld.long 0x0 0. "DMA_DONE_INTEN,DMA_DONE interrupt" "0,1" rgroup.long 0x2144++0x3 line.long 0x0 "CE2_INTSTAT,CE2_INTSTAT" newline bitfld.long 0x0 13. "DMA_FIFOERROR_INTSTAT,SSRAM_DMAFIFO error interrupt" "0,1" newline bitfld.long 0x0 12. "PKE_INTEGRITY_ERROR_INTSTAT,ALGORITHM_INTEGRITY interrupt" "0,1" newline bitfld.long 0x0 11. "HASH_INTEGRITY_ERROR_INTSTAT,ALGORITHM_INTEGRITY_ERROR interrupt" "0,1" newline bitfld.long 0x0 10. "CIPHER_INTEGRITY_ERROR_INTSTAT,ALGORITHM_INTEGRITY_ERROR interrupt" "0,1" newline bitfld.long 0x0 9. "SKC_INTEGRITY_ERROR_INTSTAT,SKC_INTEGRITY_ERROR interrupt" "0,1" newline bitfld.long 0x0 8. "DMA_INTEGRITY_ERROR_INTSTAT,ALGORITHM_INTEGRITY interrupt" "0,1" newline bitfld.long 0x0 4. "PKE_DONE_INTSTAT,PKE_DONE interrupt" "0,1" newline bitfld.long 0x0 3. "HASH_DONE_INTSTAT,HASH_DONE interrupt" "0,1" newline bitfld.long 0x0 2. "CIPHER_DONE_INTSTAT,CIPHER_DONE_INTSTATE" "0,1" newline bitfld.long 0x0 1. "SKC_DONE_INTSTAT,KEYgen done interrupt enable" "0,1" newline bitfld.long 0x0 0. "DMA_DONE_INTSTAT,DMA_DONE interrupt" "0,1" group.long 0x2148++0x3 line.long 0x0 "CE2_INTCLR,CE2_INTCLR" newline bitfld.long 0x0 13. "DMA_FIFOERROR_INTCLR,SSRAM_DMAFIFO error interrupt" "0,1" newline bitfld.long 0x0 12. "PKE_INTEGRITY_ERROR_INTCLR,ALGORITHM_INTEGRITY interrupt" "0,1" newline bitfld.long 0x0 11. "HASH_INTEGRITY_ERROR_INTCLR,ALGORITHM_INTEGRITY_ERROR interrupt" "0,1" newline bitfld.long 0x0 10. "CIPHER_INTEGRITY_ERROR_INTCLR,ALGORITHM_INTEGRITY_ERROR interrupt" "0,1" newline bitfld.long 0x0 9. "SKC_INTEGRITY_ERROR_INTCLR,SKC_INTEGRITY_ERROR interrupt" "0,1" newline bitfld.long 0x0 8. "DMA_INTEGRITY_ERROR_INTCLR,ALGORITHM_INTEGRITY interrupt" "0,1" newline bitfld.long 0x0 4. "PKE_DONE_INTCLR,PKE_DONE interrupt" "0,1" newline bitfld.long 0x0 3. "HASH_DONE_INTCLR,HASH_DONE interrupt" "0,1" newline bitfld.long 0x0 2. "CIPHER_DONE_INTCLR,CIPHER_DONE_INTCLRE" "0,1" newline bitfld.long 0x0 1. "SKC_DONE_INTCLR,KEYgen done interrupt enable" "0,1" newline bitfld.long 0x0 0. "DMA_DONE_INTCLR,DMA_DONE interrupt" "0,1" rgroup.long 0x3000++0x7 line.long 0x0 "CE3_STAT,CE3 working status" newline bitfld.long 0x0 5. "PKE_BUSY,1: PKE is busy 0:PKE is idle" "?,PKE is busy 0:PKE is idle" newline bitfld.long 0x0 4. "GENKEY_BUSY,1. CE3 generate key function is busy" "0,1" newline bitfld.long 0x0 3. "HASH_BUSY,1: the HASH of CE3 is busy" "?,the HASH of CE3 is busy" newline bitfld.long 0x0 2. "CIPHER_BUSY,1 the CIPHER of CE3 is busy" "0,1" newline bitfld.long 0x0 1. "GETRNDNUM_BUSY,1: get random number function of CE3 is busy" "?,get random number function of CE3 is busy" newline bitfld.long 0x0 0. "DMA_BUSY,1: the DMA of CE3 is busy 0: the DMA of CE3 is idle" "the DMA of CE3 is idle,the DMA of CE3 is busy" line.long 0x4 "CE3_ERRSTAT,CE3 error status" newline hexmask.long.byte 0x4 24.--27. 1. "SKC_ERR_STAT,'the error status of skc sequencer the bit 0 ~ 3 are [sram wr err] [ rand number fetch err] [ secure violation occurs] [reserved]'" newline bitfld.long 0x4 19. "SSRAM_ERR_STAT,'the error status of CE sram" "0,1" newline bitfld.long 0x4 16.--18. "DMA_ERR_STAT,'the error status of dma sequencer the bit of 0 -2 are [sram_rw_err] [wdma ch err] [rdma ch err]'" "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x4 8.--13. 1. "CIPHER_ERR_STAT,'the error status of cipher sequencer the bit 0 - 4 are [key_port_err] [rdma_ch_err] [wdma_ch_err] [sram_wr_err] [sram_rd_err] [decryption from secure to non-secure]'" newline hexmask.long.byte 0x4 0.--3. 1. "HASH_ERR_STAT,'the error status of hash sequencer the bit 0 ~ 3 are [sram_wr_err] [sram rd err] [rdma_err] [wdma err]'" group.long 0x300C++0x3F line.long 0x0 "CE3_CIPHER_CTRL,CE3 cipher control register" bitfld.long 0x0 31. "CIPHER_HEADER_SAVE,1 the header will be saved into dst memory 0: header will not be saved" "header will not be saved,?" newline bitfld.long 0x0 28.--29. "CIPHER_KEY2TYPE,key 2 type 10: input keyport 00: secure sram public area 01: secure area others: reserved" "secure sram public area,secure area others: reserved,?,?" newline bitfld.long 0x0 25.--26. "CIPHER_KEYTYPE,key type 10: input keyport 00: secure sram public area 01: secure area others: reserved" "secure sram public area,secure area others: reserved,?,?" newline hexmask.long.word 0x0 16.--24. 1. "AESMODE,'AES mode XTS : 010000000 ECB : 000000001 CBC : 000000010 CTR : 000000100 CFB : 000001000 OFB : 000010000 CCM : 000100000 GCM : 001000000 XTS : 010000000 CMAC: 100000000'" newline bitfld.long 0x0 13. "CIPHER_SAVE,0: normal mode last part of the message 1: operation context will be saved at the end of operation" "normal mode last part of the message,operation context will be saved at the end of.." newline bitfld.long 0x0 12. "CIPHER_LOAD,0 : normal mode first start of the message 1: operation restart from previously save context" "normal mode first start of the message,operation restart from previously save context" newline bitfld.long 0x0 11. "CIPHER_DECKEYCAL,0 use the input key for decryption operations 1: use the pre-calculation of the key is done before" "?,use the pre-calculation of the key is done before" newline bitfld.long 0x0 9.--10. "CIPHER_KEYSIZE,key size 00: 128bit key 01: 256 bit key 10: 192bit key 11: reserved" "0,1,2,3" newline bitfld.long 0x0 8. "CIPHERMODE,0 encryption 1 decryption" "0,1" newline bitfld.long 0x0 0. "CIPHER_GO,'write 1 to this bit will start the cipher operation'" "0,1" line.long 0x4 "CE3_CIPHER_HEADER_LEN,CE3 cipher header length register" hexmask.long 0x4 0.--31. 1. "CIPHER_HEADER_LEN,'cipher data header length in bytes'" line.long 0x8 "CE3_CIPHER_KEY_ADDR,CE3 cipher key addr register" hexmask.long.word 0x8 16.--31. 1. "CIPHER_KEY2_ADDR,key2 address in secure SRAM or keyport" newline hexmask.long.word 0x8 0.--15. 1. "CIPHER_KEY_ADDR,CIPHER_KEY_ADDR address in secure SRAM or keyport" line.long 0xC "CE3_CIPHER_SRC_ADDR,CE3 cipher source data addr register" hexmask.long 0xC 0.--31. 1. "CIPHER_SRC_ADDR,cipher data source address in bytes" line.long 0x10 "CE3_CIPHER_SRC_ADDR_H,CE3 cipher source data addr high register" newline bitfld.long 0x10 8.--10. "CIPHER_SRC_TYPE,011: CE SRAM Secure AREA 001:CE SRAM public area 000:external memories other: reserved" "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x10 0.--7. 1. "CIPHER_SRC_ADDR_H,the high part of CE3 cipher source address" line.long 0x14 "CE3_CIPHER_DST_ADDR,CE3 cipher destination data addr register" hexmask.long 0x14 0.--31. 1. "CIPHER_DST_ADDR,CE3 cipher data destination address" line.long 0x18 "CE3_CIPHER_DST_ADDR_H,CE3 cipher destination data addr high register" newline bitfld.long 0x18 8.--10. "CIPHER_DST_TYPE,011: CE SRAM Secure AREA 001:CE SRAM public area 000:external memories other: reserved" "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x18 0.--7. 1. "CIPHER_DST_ADDR_H,CE3 cipher data destination address" line.long 0x1C "CE3_CIPHER_IV_CONTEXT_ADDR,CE3 cipher IV and context addr register" hexmask.long.word 0x1C 16.--31. 1. "CIPHER_CONTEXT_ADDR,CIPHER context storage address the context is always stored into SRAM secure area" newline hexmask.long.word 0x1C 0.--15. 1. "CIPHER_IV_ADDR,CIPHER iv storage address the iv is always stored into SRAM secure area" line.long 0x20 "CE3_CIPHER_PAYLOAD_LEN,CE3 cipher payload length register" hexmask.long 0x20 0.--31. 1. "CIPHER_PAYLOAD_LEN,CIPHER_PAYLOAD_LEN NOT including the header length in byte" line.long 0x24 "CE3_HASH_CTRL,CE3 hash control register" newline bitfld.long 0x24 24. "HASH_HMAC_EN,1: hmac is enabled 0: hmac is disabled" "hmac is disabled,hmac is enabled" newline bitfld.long 0x24 19. "HASH_KEY,1 need to load key 0 donot load key" "0,1" newline bitfld.long 0x24 18. "HASH_INIT_SECURE,1 load IV from secure area 0: load IV from public area" "load IV from public area,?" newline bitfld.long 0x24 17. "HASH_INIT,1 load IV for the hash 0 not load initial vector" "0,1" newline bitfld.long 0x24 16. "HASH_SHAUPDATE,0 final SHA224 output 7 words and SHA384 output 6 words 1: update SHA224/384 output 8 words please don't use this feature in hmac mode" "?,update SHA224/384 output 8 words please don't.." newline bitfld.long 0x24 15. "HASH_PADDINGEN,0: bypass padding logic 1: use hw padding logic" "bypass padding logic,use hw padding logic" newline hexmask.long.byte 0x24 8.--14. 1. "HASH_MODE,0000001 MD5 0000010 SHA1 0000100 SHA224 0001000 SHA256 0010000 SHA384 0100000 SHA512 1000000 SM3" newline bitfld.long 0x24 0. "HASH_GO,HASH Calculation start" "0,1" line.long 0x28 "CE3_HASH_KEYIV_ADDR,CE3 hash key and IV address register" hexmask.long.word 0x28 16.--31. 1. "HASH_KEY_ADDR,HASH_KEY address" newline hexmask.long.word 0x28 0.--15. 1. "HASH_IV_ADDR,HASH initial vection address" line.long 0x2C "CE3_HMAC_KEY_CTRL,CE3 hmac key control register" newline bitfld.long 0x2C 16.--17. "HMAC_KEY_TYPE,10 from key interface 01: from SRAM secure area 00 from SRAM public area" "?,from SRAM secure area 00 from SRAM public area,?,?" newline hexmask.long.word 0x2C 0.--15. 1. "HMAC_KEY_LEN,CE3 hash key length in CE SRAM" line.long 0x30 "CE3_HASH_CALC_LEN,CE3 hash calcluation length register" hexmask.long 0x30 0.--31. 1. "HASH_CALC_LEN,CE3 hash calculation length in bytes" line.long 0x34 "CE3_HASH_SRC_ADDR,CE3 hash source address register" hexmask.long 0x34 0.--31. 1. "HASH_SRC_ADDR,CE3 HASH SRC ADDR" line.long 0x38 "CE3_HASH_SRC_ADDR_H,CE3 hash source address high register" newline bitfld.long 0x38 8.--10. "HASH_SRC_TYPE,000: external memory 001: CE SRAM public area 011 CE sram secure area 1xx: SKC key interface space" "external memory,CE SRAM public area 011 CE sram secure area 1xx:..,?,?,?,?,?,?" newline hexmask.long.byte 0x38 0.--7. 1. "HASH_SRC_ADDR_H,the high part of CE3 hash src address" line.long 0x3C "CE3_HASH_DST_ADDR,CE3 hash destination address register" newline bitfld.long 0x3C 16.--18. "HASH_DST_TYPE,011 internal secure SRAM 001 public area in secure ram 1xx key interface" "0,1,2,3,4,5,6,7" newline hexmask.long.word 0x3C 0.--15. 1. "HASH_DST_ADDR,the dst address in secure SRAM" group.long 0x3050++0x17 line.long 0x0 "CE3_DMA_CTRL,CE3_DMA_CTRL" newline bitfld.long 0x0 10. "DMA_DONEINTEN,1 the interrupt will be generated if the DMA operation is done" "0,1" newline rbitfld.long 0x0 9. "DMA_CMDFIFO_FULL,cmd fifo is full" "0,1" newline rbitfld.long 0x0 8. "DMA_CMDFIFO_EMPTY,cmd fifo is empty" "0,1" newline bitfld.long 0x0 0. "DMA_GO,write 1 to this register start CE3 DMA operation" "0,1" line.long 0x4 "CE3_DMA_SRC_ADDR,CE3 dma source address register" hexmask.long 0x4 0.--31. 1. "DMA_SRC_ADDR,CE3 dma source addr" line.long 0x8 "CE3_DMA_SRC_ADDR_H,CE3 dma source address high register" newline bitfld.long 0x8 8.--10. "DMA_SRC_TYPE,011: CE SRAM Secure AREA 001:CE SRAM public area 000:external memories 010: PKE operand mem other: reserved" "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x8 0.--7. 1. "DMA_SRC_ADDR_H,CE3 dma source addr high part" line.long 0xC "CE3_DMA_DST_ADDR,CE3 dma destination address register" hexmask.long 0xC 0.--31. 1. "DMA_DST_ADDR,CE3 DMA DST ADDR" line.long 0x10 "CE3_DMA_DST_ADDR_H,CE3 dma destination address high register" newline bitfld.long 0x10 8.--10. "DMA_DST_TYPE,011: CE SRAM Secure AREA 001:CE SRAM public area 000:external memories 010: PKE operand mem other: reserved" "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x10 0.--7. 1. "DMA_DST_ADDR_H,CE3 DMA DST ADDR high part" line.long 0x14 "CE3_DMA_LEN,CE3 dma transer length register" newline hexmask.long.word 0x14 0.--15. 1. "DMA_LEN,DMA transfer length in byte" group.long 0x3080++0xB line.long 0x0 "CE3_PK_POINTERREG,CE3_PK_POINTERREG" newline hexmask.long.byte 0x0 24.--27. 1. "PK_OPPTRN,'When executing primitive arithmetic operations" newline hexmask.long.byte 0x0 16.--19. 1. "PK_OPPTRC,'When executing primitive arithmetic operations" newline hexmask.long.byte 0x0 8.--11. 1. "PK_OPPTRB,'When executing primitive arithmetic operations" newline hexmask.long.byte 0x0 0.--3. 1. "PK_OPPTRA,'When executing primitive arithmetic operations" line.long 0x4 "CE3_PK_COMMANDREG,CE3_PK_COMMANDREG" bitfld.long 0x4 31. "PK_CALCR2,PK_CALCR2" "0,1" newline bitfld.long 0x4 30. "PK_FLAGB,'B See routine description'" "0,1" newline bitfld.long 0x4 29. "PK_FLAGA,'A See routine description'" "0,1" newline bitfld.long 0x4 28. "PK_SWAP,'bytes Swap the bytes on AHB interface: '0': Native format (little endian) '1': Byte swapped (big endian) See also section 4.2.1. This bit must be programmed before writing/reading any data in data memory.'" "0,1" newline bitfld.long 0x4 27. "PK_BUFFER,PK_BUFFER" "0,1" newline bitfld.long 0x4 26. "PK_EDWARDS,'Enable Edwards curve (see routine description)'" "0,1" newline bitfld.long 0x4 25. "PK_RANDPROJ,'Enable randomization of projective coordinates (counter-measure)'" "0,1" newline bitfld.long 0x4 24. "PK_RANDKE,'Enable randomization of exponent/scalar (counter-measure)'" "0,1" newline hexmask.long.byte 0x4 20.--23. 1. "PK_SELCURVE,'Enable accelerator for specific curve modulus: 0x0: No acceleration (default) 0x1: P256 0x2: P384 0x3: P521/E-521 0x4: P192 0x5: Curve25519/Ed25519 This field has no effect when the optional acceleration hardware is not included.'" newline hexmask.long.word 0x4 8.--18. 1. "PK_SIZE,'Of Operands (in data memory) This field defines the size (= number of bytes minus one) of the operands for the current operation. Possible values are limited by the maximum supported operand size. Examples: 0x014 -> ECC on curve K-163 0x01F ->.." newline bitfld.long 0x4 7. "PK_FIELD,''0': Field is GF(p) '1': Field is GF(2m)'" "0,1" newline hexmask.long.byte 0x4 0.--6. 1. "PK_TYPE,'of operation This field defines the operation to be performed. See table below for details.'" line.long 0x8 "CE3_PKE_CTRL,CE3_PKE_CTRL" newline bitfld.long 0x8 2. "PKE_SOFT_RST,'Writing a 1 to this bit will reset the pke_seq logic'" "0,1" newline bitfld.long 0x8 1. "PK_CLRMEMAFTEROP,'Writing a 1 to this bit will make the pke to clear its memories after all operations are complete'" "0,1" newline bitfld.long 0x8 0. "PKE_GO,'Writing a '1' starts the processing.'" "0,1" rgroup.long 0x308C++0x3 line.long 0x0 "CE3_PK_STATUSREG,CE3_PK_STATUSREG" newline bitfld.long 0x0 17. "PK_INTERRUPT,'status This bit reflects the IRQ output value. It is set to '1' when the operation is finished. It is cleared when the CPU writes the bit 1 of Control Register.'" "0,1" newline bitfld.long 0x0 16. "PK_BUSY,'This bit reflects the BUSY output value. It is set to '1' when the operation starts and it is cleared when the operation is finished.'" "0,1" newline bitfld.long 0x0 13. "PK_NOTQUADRATICRESIDUE,PK_NOTQUADRATICRESIDUE" "0,1" newline bitfld.long 0x0 12. "PK_COMPOSITE,PK_COMPOSITE" "0,1" newline bitfld.long 0x0 11. "PK_NOTINVERTIBLE,PK_NOTINVERTIBLE" "0,1" newline bitfld.long 0x0 10. "PK_PARAM_AB_NOTVALID,PK_PARAM_AB_NOTVALID" "0,1" newline bitfld.long 0x0 9. "PK_SIGNATURE_NOTVALID,PK_SIGNATURE_NOTVALID" "0,1" newline bitfld.long 0x0 8. "PK_NOTIMPLEMENTED,PK_NOTIMPLEMENTED" "0,1" newline bitfld.long 0x0 7. "PK_PARAM_N_NOTVALID,PK_PARAM_N_NOTVALID" "0,1" newline bitfld.long 0x0 6. "PK_COUPLE_NOTVALID,PK_COUPLE_NOTVALID" "0,1" newline bitfld.long 0x0 5. "PK_POINT_PX_ATINFINITY,PK_POINT_PX_ATINFINITY" "0,1" newline bitfld.long 0x0 4. "PK_POINT_PX_NOTONCURVE,PK_POINT_PX_NOTONCURVE" "0,1" newline hexmask.long.byte 0x0 0.--3. 1. "PK_FAIL_ADDRESS,'These bits indicate which data location generated the error flag. They are not available for all error flags.'" group.long 0x3094++0x3 line.long 0x0 "CE3_PK_TIMER,CE3_PK_TIMER" hexmask.long 0x0 0.--31. 1. "PK_TIMER,'The timer counts the number of clock cycles when the PK engine is busy. It is not cleared automatically. It can be written by software (when the PK is idle). The register is updated at the end of every operation (reading it when the PK engine.." rgroup.long 0x3098++0x3 line.long 0x0 "CE3_PK_HWCONFIGREG,CE3_PK_HWCONFIGREG" bitfld.long 0x0 31. "PK_DISABLECM,'State of DisableCM input (high when counter-measures are disabled)'" "0,1" newline bitfld.long 0x0 24. "PK_25519,'Support Curve25519/Ed25519 acceleration'" "0,1" newline bitfld.long 0x0 23. "PK_P192,'Support ECC P192 acceleration'" "0,1" newline bitfld.long 0x0 22. "PK_P521,'Support ECC P521 acceleration'" "0,1" newline bitfld.long 0x0 21. "PK_P384,'Support ECC P384 acceleration'" "0,1" newline bitfld.long 0x0 20. "PK_P256,'Support ECC P256 acceleration'" "0,1" newline bitfld.long 0x0 17. "PK_BINARYFIELD,'Support binary field'" "0,1" newline bitfld.long 0x0 16. "PK_PRIMEFIELD,'Support prime field'" "0,1" newline hexmask.long.byte 0x0 12.--15. 1. "PK_NBMULT,'Number of multipliers: 0x0: 1 multiplier 0x1: 4 multipliers 0x2: 16 multipliers 0x4: 64 multipliers 0x8: 256 multipliers'" newline hexmask.long.word 0x0 0.--11. 1. "PK_MAXOPSIZE,'Maximum operand size (number of bytes) 4096 bytes'" group.long 0x309C++0xB line.long 0x0 "CE3_PK_RESULTS_CTRL,CE3_PK_RESULTS_CTRL" hexmask.long.word 0x0 16.--31. 1. "PKE_RESULTS_OP_LEN,'pke results each operand length in bytes'" newline hexmask.long.word 0x0 0.--15. 1. "PKE_RESULTS_OP_SELECT,'pke results output select each bit correspnding to the operand position of the pke data memory'" line.long 0x4 "CE3_PK_RESULTS_DST_ADDR,CE3_PK_RESULTS_DST_ADDR" hexmask.long 0x4 0.--31. 1. "PKE_RESULTS_DST_ADDR,'pke results dma dst address low 32bit'" line.long 0x8 "CE3_PK_RESULTS_DST_ADDR_H,CE3_PK_RESULTS_DST_ADDR_H" newline bitfld.long 0x8 8.--10. "PKE_RESULTS_DST_TYPE,'pke results dma dst data type 011: CE SRAM Secure AREA 001:CE SRAM public area 000:external memories other: reserved'" "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x8 0.--7. 1. "PKE_RESULTS_DST_ADDR_H,'pke results dma dst address high 8bit'" rgroup.long 0x3100++0x3 line.long 0x0 "CE3_TRNG_STATUS,CE3_TRNG_STATUS" newline bitfld.long 0x0 1. "RNG_SEQ_RUNNING,'1: the rng sequencer is running currently 0: rng sequencer is in idle status'" "rng sequencer is in idle status',the rng sequencer is running currently" newline bitfld.long 0x0 0. "RNG_READY,'1: the value in the random number register of CE3 is valid" "?,the value in the random number register of CE3.." repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) rgroup.long ($2+0x3104)++0x3 line.long 0x0 "CE3_TRNG_NUM$1,CE3_TRNG_NUM0" hexmask.long 0x0 0.--31. 1. "TRNG_NUM0,CE3 the random number0 value" repeat.end rgroup.long 0x3114++0x3 line.long 0x0 "CE3_HRNG_NUM,CE3_HRNG_NUM" hexmask.long 0x0 0.--31. 1. "HRNG_NUM,CE3 the hybird random number value" group.long 0x3120++0xB line.long 0x0 "CE3_SKC_CTRL,CE3_SKC_CTRL" newline bitfld.long 0x0 8.--10. "SKC_CMD,the command of SKC 001: generate random number 010: erase key contrainer" "?,generate random number,?,?,?,?,?,?" newline bitfld.long 0x0 0. "SKC_GO,CE3 secure FSM start trigger" "0,1" line.long 0x4 "CE3_SKC_RNG_ADDR,CE3_SKC_RNG_ADDR" newline bitfld.long 0x4 24. "SKC_RNG_SECURE,CE3 1: random number generated to secure area 0 : in public area" "in public area,random number generated to secure area" newline hexmask.long.byte 0x4 16.--22. 1. "SKC_RNG_LEN,'numbers of bits to generate into sram granularity is 256 bit'" newline hexmask.long.word 0x4 0.--12. 1. "SKC_RNG_ADDR,CE3 random number generation address in CE sram the address granularity is 8 bytes" line.long 0x8 "CE3_SKC_KEYBLOB_CTRL,CE3_SKC_KEYBLOB_CTRL" newline bitfld.long 0x8 0. "SKC_KEYBLOB_CTRL,CE3 key blob control 1: is key blob :0 : is the secret data" "?,is key blob :0 : is the secret data" group.long 0x3140++0x3 line.long 0x0 "CE3_INTEN,CE3_INTEN" newline bitfld.long 0x0 13. "DMA_FIFOERROR_INTEN,DMA fifo error interrupt" "0,1" newline bitfld.long 0x0 12. "PKE_INTEGRITY_ERROR_INTEN,ALGORITHM_INTEGRITY interrupt" "0,1" newline bitfld.long 0x0 11. "HASH_INTEGRITY_ERROR_INTEN,ALGORITHM_INTEGRITY_ERROR interrupt" "0,1" newline bitfld.long 0x0 10. "CIPHER_INTEGRITY_ERROR_INTEN,ALGORITHM_INTEGRITY_ERROR interrupt" "0,1" newline bitfld.long 0x0 9. "SKC_INTEGRITY_ERROR_INTEN,SKC_INTEGRITY_ERROR interrupt" "0,1" newline bitfld.long 0x0 8. "DMA_INTEGRITY_ERROR_INTEN,ALGORITHM_INTEGRITY interrupt" "0,1" newline bitfld.long 0x0 4. "PKE_DONE_INTEN,PKE_DONE interrupt" "0,1" newline bitfld.long 0x0 3. "HASH_DONE_INTEN,HASH_DONE interrupt" "0,1" newline bitfld.long 0x0 2. "CIPHER_DONE_INTEN,CIPHER_DONE_INTEN" "0,1" newline bitfld.long 0x0 1. "SKC_DONE_INTEN,KEYgen done interrupt enable" "0,1" newline bitfld.long 0x0 0. "DMA_DONE_INTEN,DMA_DONE interrupt" "0,1" rgroup.long 0x3144++0x3 line.long 0x0 "CE3_INTSTAT,CE3_INTSTAT" newline bitfld.long 0x0 13. "DMA_FIFOERROR_INTSTAT,SSRAM_DMAFIFO error interrupt" "0,1" newline bitfld.long 0x0 12. "PKE_INTEGRITY_ERROR_INTSTAT,ALGORITHM_INTEGRITY interrupt" "0,1" newline bitfld.long 0x0 11. "HASH_INTEGRITY_ERROR_INTSTAT,ALGORITHM_INTEGRITY_ERROR interrupt" "0,1" newline bitfld.long 0x0 10. "CIPHER_INTEGRITY_ERROR_INTSTAT,ALGORITHM_INTEGRITY_ERROR interrupt" "0,1" newline bitfld.long 0x0 9. "SKC_INTEGRITY_ERROR_INTSTAT,SKC_INTEGRITY_ERROR interrupt" "0,1" newline bitfld.long 0x0 8. "DMA_INTEGRITY_ERROR_INTSTAT,ALGORITHM_INTEGRITY interrupt" "0,1" newline bitfld.long 0x0 4. "PKE_DONE_INTSTAT,PKE_DONE interrupt" "0,1" newline bitfld.long 0x0 3. "HASH_DONE_INTSTAT,HASH_DONE interrupt" "0,1" newline bitfld.long 0x0 2. "CIPHER_DONE_INTSTAT,CIPHER_DONE_INTSTATE" "0,1" newline bitfld.long 0x0 1. "SKC_DONE_INTSTAT,KEYgen done interrupt enable" "0,1" newline bitfld.long 0x0 0. "DMA_DONE_INTSTAT,DMA_DONE interrupt" "0,1" group.long 0x3148++0x3 line.long 0x0 "CE3_INTCLR,CE3_INTCLR" newline bitfld.long 0x0 13. "DMA_FIFOERROR_INTCLR,SSRAM_DMAFIFO error interrupt" "0,1" newline bitfld.long 0x0 12. "PKE_INTEGRITY_ERROR_INTCLR,ALGORITHM_INTEGRITY interrupt" "0,1" newline bitfld.long 0x0 11. "HASH_INTEGRITY_ERROR_INTCLR,ALGORITHM_INTEGRITY_ERROR interrupt" "0,1" newline bitfld.long 0x0 10. "CIPHER_INTEGRITY_ERROR_INTCLR,ALGORITHM_INTEGRITY_ERROR interrupt" "0,1" newline bitfld.long 0x0 9. "SKC_INTEGRITY_ERROR_INTCLR,SKC_INTEGRITY_ERROR interrupt" "0,1" newline bitfld.long 0x0 8. "DMA_INTEGRITY_ERROR_INTCLR,ALGORITHM_INTEGRITY interrupt" "0,1" newline bitfld.long 0x0 4. "PKE_DONE_INTCLR,PKE_DONE interrupt" "0,1" newline bitfld.long 0x0 3. "HASH_DONE_INTCLR,HASH_DONE interrupt" "0,1" newline bitfld.long 0x0 2. "CIPHER_DONE_INTCLR,CIPHER_DONE_INTCLRE" "0,1" newline bitfld.long 0x0 1. "SKC_DONE_INTCLR,KEYgen done interrupt enable" "0,1" newline bitfld.long 0x0 0. "DMA_DONE_INTCLR,DMA_DONE interrupt" "0,1" rgroup.long 0x4000++0x7 line.long 0x0 "CE4_STAT,CE4 working status" newline bitfld.long 0x0 4. "GENKEY_BUSY,1. CE4 generate key function is busy" "0,1" newline bitfld.long 0x0 3. "HASH_BUSY,1: the HASH of CE4 is busy" "?,the HASH of CE4 is busy" newline bitfld.long 0x0 2. "CIPHER_BUSY,1 the CIPHER of CE4 is busy" "0,1" newline bitfld.long 0x0 1. "GETRNDNUM_BUSY,1: get random number function of CE4 is busy" "?,get random number function of CE4 is busy" newline bitfld.long 0x0 0. "DMA_BUSY,1: the DMA of CE4 is busy 0: the DMA of CE4 is idle" "the DMA of CE4 is idle,the DMA of CE4 is busy" line.long 0x4 "CE4_ERRSTAT,CE4 error status" newline hexmask.long.byte 0x4 24.--27. 1. "SKC_ERR_STAT,'the error status of skc sequencer the bit 0 ~ 3 are [sram wr err] [ rand number fetch err] [ secure violation occurs] [reserved]'" newline bitfld.long 0x4 19. "SSRAM_ERR_STAT,'the error status of CE sram" "0,1" newline bitfld.long 0x4 16.--18. "DMA_ERR_STAT,'the error status of dma sequencer the bit of 0 -2 are [sram_rw_err] [wdma ch err] [rdma ch err]'" "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x4 8.--13. 1. "CIPHER_ERR_STAT,'the error status of cipher sequencer the bit 0 - 4 are [key_port_err] [rdma_ch_err] [wdma_ch_err] [sram_wr_err] [sram_rd_err] [decryption from secure to non-secure]'" newline hexmask.long.byte 0x4 0.--3. 1. "HASH_ERR_STAT,'the error status of hash sequencer the bit 0 ~ 3 are [sram_wr_err] [sram rd err] [rdma_err] [wdma err]'" group.long 0x400C++0x3F line.long 0x0 "CE4_CIPHER_CTRL,CE4 cipher control register" bitfld.long 0x0 31. "CIPHER_HEADER_SAVE,1 the header will be saved into dst memory 0: header will not be saved" "header will not be saved,?" newline bitfld.long 0x0 28.--29. "CIPHER_KEY2TYPE,key 2 type 10: input keyport 00: secure sram public area 01: secure area others: reserved" "secure sram public area,secure area others: reserved,?,?" newline bitfld.long 0x0 25.--26. "CIPHER_KEYTYPE,key type 10: input keyport 00: secure sram public area 01: secure area others: reserved" "secure sram public area,secure area others: reserved,?,?" newline hexmask.long.word 0x0 16.--24. 1. "AESMODE,'AES mode XTS : 010000000 ECB : 000000001 CBC : 000000010 CTR : 000000100 CFB : 000001000 OFB : 000010000 CCM : 000100000 GCM : 001000000 XTS : 010000000 CMAC: 100000000'" newline bitfld.long 0x0 13. "CIPHER_SAVE,0: normal mode last part of the message 1: operation context will be saved at the end of operation" "normal mode last part of the message,operation context will be saved at the end of.." newline bitfld.long 0x0 12. "CIPHER_LOAD,0 : normal mode first start of the message 1: operation restart from previously save context" "normal mode first start of the message,operation restart from previously save context" newline bitfld.long 0x0 11. "CIPHER_DECKEYCAL,0 use the input key for decryption operations 1: use the pre-calculation of the key is done before" "?,use the pre-calculation of the key is done before" newline bitfld.long 0x0 9.--10. "CIPHER_KEYSIZE,key size 00: 128bit key 01: 256 bit key 10: 192bit key 11: reserved" "0,1,2,3" newline bitfld.long 0x0 8. "CIPHERMODE,0 encryption 1 decryption" "0,1" newline bitfld.long 0x0 0. "CIPHER_GO,'write 1 to this bit will start the cipher operation'" "0,1" line.long 0x4 "CE4_CIPHER_HEADER_LEN,CE4 cipher header length register" hexmask.long 0x4 0.--31. 1. "CIPHER_HEADER_LEN,'cipher data header length in bytes'" line.long 0x8 "CE4_CIPHER_KEY_ADDR,CE4 cipher key addr register" hexmask.long.word 0x8 16.--31. 1. "CIPHER_KEY2_ADDR,key2 address in secure SRAM or keyport" newline hexmask.long.word 0x8 0.--15. 1. "CIPHER_KEY_ADDR,CIPHER_KEY_ADDR address in secure SRAM or keyport" line.long 0xC "CE4_CIPHER_SRC_ADDR,CE4 cipher source data addr register" hexmask.long 0xC 0.--31. 1. "CIPHER_SRC_ADDR,cipher data source address in bytes" line.long 0x10 "CE4_CIPHER_SRC_ADDR_H,CE4 cipher source data addr high register" newline bitfld.long 0x10 8.--10. "CIPHER_SRC_TYPE,011: CE SRAM Secure AREA 001:CE SRAM public area 000:external memories other: reserved" "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x10 0.--7. 1. "CIPHER_SRC_ADDR_H,the high part of CE4 cipher source address" line.long 0x14 "CE4_CIPHER_DST_ADDR,CE4 cipher destination data addr register" hexmask.long 0x14 0.--31. 1. "CIPHER_DST_ADDR,CE4 cipher data destination address" line.long 0x18 "CE4_CIPHER_DST_ADDR_H,CE4 cipher destination data addr high register" newline bitfld.long 0x18 8.--10. "CIPHER_DST_TYPE,011: CE SRAM Secure AREA 001:CE SRAM public area 000:external memories other: reserved" "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x18 0.--7. 1. "CIPHER_DST_ADDR_H,CE4 cipher data destination address" line.long 0x1C "CE4_CIPHER_IV_CONTEXT_ADDR,CE4 cipher IV and context addr register" hexmask.long.word 0x1C 16.--31. 1. "CIPHER_CONTEXT_ADDR,CIPHER context storage address the context is always stored into SRAM secure area" newline hexmask.long.word 0x1C 0.--15. 1. "CIPHER_IV_ADDR,CIPHER iv storage address the iv is always stored into SRAM secure area" line.long 0x20 "CE4_CIPHER_PAYLOAD_LEN,CE4 cipher payload length register" hexmask.long 0x20 0.--31. 1. "CIPHER_PAYLOAD_LEN,CIPHER_PAYLOAD_LEN NOT including the header length in byte" line.long 0x24 "CE4_HASH_CTRL,CE4 hash control register" newline bitfld.long 0x24 24. "HASH_HMAC_EN,1: hmac is enabled 0: hmac is disabled" "hmac is disabled,hmac is enabled" newline bitfld.long 0x24 19. "HASH_KEY,1 need to load key 0 donot load key" "0,1" newline bitfld.long 0x24 18. "HASH_INIT_SECURE,1 load IV from secure area 0: load IV from public area" "load IV from public area,?" newline bitfld.long 0x24 17. "HASH_INIT,1 load IV for the hash 0 not load initial vector" "0,1" newline bitfld.long 0x24 16. "HASH_SHAUPDATE,0 final SHA224 output 7 words and SHA384 output 6 words 1: update SHA224/384 output 8 words please don't use this feature in hmac mode" "?,update SHA224/384 output 8 words please don't.." newline bitfld.long 0x24 15. "HASH_PADDINGEN,0: bypass padding logic 1: use hw padding logic" "bypass padding logic,use hw padding logic" newline hexmask.long.byte 0x24 8.--14. 1. "HASH_MODE,0000001 MD5 0000010 SHA1 0000100 SHA224 0001000 SHA256 0010000 SHA384 0100000 SHA512 1000000 SM3" newline bitfld.long 0x24 0. "HASH_GO,HASH Calculation start" "0,1" line.long 0x28 "CE4_HASH_KEYIV_ADDR,CE4 hash key and IV address register" hexmask.long.word 0x28 16.--31. 1. "HASH_KEY_ADDR,HASH_KEY address" newline hexmask.long.word 0x28 0.--15. 1. "HASH_IV_ADDR,HASH initial vection address" line.long 0x2C "CE4_HMAC_KEY_CTRL,CE4 hmac key control register" newline bitfld.long 0x2C 16.--17. "HMAC_KEY_TYPE,10 from key interface 01: from SRAM secure area 00 from SRAM public area" "?,from SRAM secure area 00 from SRAM public area,?,?" newline hexmask.long.word 0x2C 0.--15. 1. "HMAC_KEY_LEN,CE4 hash key length in CE SRAM" line.long 0x30 "CE4_HASH_CALC_LEN,CE4 hash calcluation length register" hexmask.long 0x30 0.--31. 1. "HASH_CALC_LEN,CE4 hash calculation length in bytes" line.long 0x34 "CE4_HASH_SRC_ADDR,CE4 hash source address register" hexmask.long 0x34 0.--31. 1. "HASH_SRC_ADDR,CE4 HASH SRC ADDR" line.long 0x38 "CE4_HASH_SRC_ADDR_H,CE4 hash source address high register" newline bitfld.long 0x38 8.--10. "HASH_SRC_TYPE,000: external memory 001: CE SRAM public area 011 CE sram secure area 1xx: SKC key interface space" "external memory,CE SRAM public area 011 CE sram secure area 1xx:..,?,?,?,?,?,?" newline hexmask.long.byte 0x38 0.--7. 1. "HASH_SRC_ADDR_H,the high part of CE4 hash src address" line.long 0x3C "CE4_HASH_DST_ADDR,CE4 hash destination address register" newline bitfld.long 0x3C 16.--18. "HASH_DST_TYPE,011 internal secure SRAM 001 public area in secure ram 1xx key interface" "0,1,2,3,4,5,6,7" newline hexmask.long.word 0x3C 0.--15. 1. "HASH_DST_ADDR,the dst address in secure SRAM" group.long 0x4050++0x17 line.long 0x0 "CE4_DMA_CTRL,CE4_DMA_CTRL" newline bitfld.long 0x0 10. "DMA_DONEINTEN,1 the interrupt will be generated if the DMA operation is done" "0,1" newline bitfld.long 0x0 0. "DMA_GO,write 1 to this register start CE4 DMA operation" "0,1" line.long 0x4 "CE4_DMA_SRC_ADDR,CE4 dma source address register" hexmask.long 0x4 0.--31. 1. "DMA_SRC_ADDR,CE4 dma source addr" line.long 0x8 "CE4_DMA_SRC_ADDR_H,CE4 dma source address high register" newline bitfld.long 0x8 8.--10. "DMA_SRC_TYPE,011: CE SRAM Secure AREA 001/010:CE SRAM public area 000:external memories other: reserved" "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x8 0.--7. 1. "DMA_SRC_ADDR_H,CE4 dma source addr high part" line.long 0xC "CE4_DMA_DST_ADDR,CE4 dma destination address register" hexmask.long 0xC 0.--31. 1. "DMA_DST_ADDR,CE4 DMA DST ADDR" line.long 0x10 "CE4_DMA_DST_ADDR_H,CE4 dma destination address high register" newline bitfld.long 0x10 8.--10. "DMA_DST_TYPE,011: CE SRAM Secure AREA 001/010:CE SRAM public area 000:external memories other: reserved" "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x10 0.--7. 1. "DMA_DST_ADDR_H,CE4 DMA DST ADDR high part" line.long 0x14 "CE4_DMA_LEN,CE4 dma transer length register" newline hexmask.long.word 0x14 0.--15. 1. "DMA_LEN,DMA transfer length in byte" rgroup.long 0x4100++0x3 line.long 0x0 "CE4_TRNG_STATUS,CE4_TRNG_STATUS" newline bitfld.long 0x0 1. "RNG_SEQ_RUNNING,'1: the rng sequencer is running currently 0: rng sequencer is in idle status'" "rng sequencer is in idle status',the rng sequencer is running currently" newline bitfld.long 0x0 0. "RNG_READY,'1: the value in the random number register of CE4 is valid" "?,the value in the random number register of CE4.." repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) rgroup.long ($2+0x4104)++0x3 line.long 0x0 "CE4_TRNG_NUM$1,CE4_TRNG_NUM0" hexmask.long 0x0 0.--31. 1. "TRNG_NUM0,CE4 the random number0 value" repeat.end rgroup.long 0x4114++0x3 line.long 0x0 "CE4_HRNG_NUM,CE4_HRNG_NUM" hexmask.long 0x0 0.--31. 1. "HRNG_NUM,CE4 the hybird random number value" group.long 0x4120++0xB line.long 0x0 "CE4_SKC_CTRL,CE4_SKC_CTRL" newline bitfld.long 0x0 8.--10. "SKC_CMD,the command of SKC 001: generate random number 010: erase key contrainer" "?,generate random number,?,?,?,?,?,?" newline bitfld.long 0x0 0. "SKC_GO,CE4 secure FSM start trigger" "0,1" line.long 0x4 "CE4_SKC_RNG_ADDR,CE4_SKC_RNG_ADDR" newline bitfld.long 0x4 24. "SKC_RNG_SECURE,CE4 1: random number generated to secure area 0 : in public area" "in public area,random number generated to secure area" newline hexmask.long.byte 0x4 16.--22. 1. "SKC_RNG_LEN,'numbers of bits to generate into sram granularity is 256 bit'" newline hexmask.long.word 0x4 0.--12. 1. "SKC_RNG_ADDR,CE4 random number generation address in CE sram the address granularity is 8 bytes" line.long 0x8 "CE4_SKC_KEYBLOB_CTRL,CE4_SKC_KEYBLOB_CTRL" newline bitfld.long 0x8 0. "SKC_KEYBLOB_CTRL,CE4 key blob control 1: is key blob :0 : is the secret data" "?,is key blob :0 : is the secret data" group.long 0x4140++0x3 line.long 0x0 "CE4_INTEN,CE4_INTEN" newline bitfld.long 0x0 11. "HASH_INTEGRITY_ERROR_INTEN,ALGORITHM_INTEGRITY_ERROR interrupt" "0,1" newline bitfld.long 0x0 10. "CIPHER_INTEGRITY_ERROR_INTEN,ALGORITHM_INTEGRITY_ERROR interrupt" "0,1" newline bitfld.long 0x0 9. "SKC_INTEGRITY_ERROR_INTEN,SKC_INTEGRITY_ERROR interrupt" "0,1" newline bitfld.long 0x0 8. "DMA_INTEGRITY_ERROR_INTEN,ALGORITHM_INTEGRITY interrupt" "0,1" newline bitfld.long 0x0 3. "HASH_DONE_INTEN,HASH_DONE interrupt" "0,1" newline bitfld.long 0x0 2. "CIPHER_DONE_INTEN,CIPHER_DONE_INTEN" "0,1" newline bitfld.long 0x0 1. "SKC_DONE_INTEN,KEYgen done interrupt enable" "0,1" newline bitfld.long 0x0 0. "DMA_DONE_INTEN,DMA_DONE interrupt" "0,1" rgroup.long 0x4144++0x3 line.long 0x0 "CE4_INTSTAT,CE4_INTSTAT" newline bitfld.long 0x0 11. "HASH_INTEGRITY_ERROR_INTSTAT,ALGORITHM_INTEGRITY_ERROR interrupt" "0,1" newline bitfld.long 0x0 10. "CIPHER_INTEGRITY_ERROR_INTSTAT,ALGORITHM_INTEGRITY_ERROR interrupt" "0,1" newline bitfld.long 0x0 9. "SKC_INTEGRITY_ERROR_INTSTAT,SKC_INTEGRITY_ERROR interrupt" "0,1" newline bitfld.long 0x0 8. "DMA_INTEGRITY_ERROR_INTSTAT,ALGORITHM_INTEGRITY interrupt" "0,1" newline bitfld.long 0x0 3. "HASH_DONE_INTSTAT,HASH_DONE interrupt" "0,1" newline bitfld.long 0x0 2. "CIPHER_DONE_INTSTAT,CIPHER_DONE_INTSTATE" "0,1" newline bitfld.long 0x0 1. "SKC_DONE_INTSTAT,KEYgen done interrupt enable" "0,1" newline bitfld.long 0x0 0. "DMA_DONE_INTSTAT,DMA_DONE interrupt" "0,1" group.long 0x4148++0x3 line.long 0x0 "CE4_INTCLR,CE4_INTCLR" newline bitfld.long 0x0 11. "HASH_INTEGRITY_ERROR_INTCLR,ALGORITHM_INTEGRITY_ERROR interrupt" "0,1" newline bitfld.long 0x0 10. "CIPHER_INTEGRITY_ERROR_INTCLR,ALGORITHM_INTEGRITY_ERROR interrupt" "0,1" newline bitfld.long 0x0 9. "SKC_INTEGRITY_ERROR_INTCLR,SKC_INTEGRITY_ERROR interrupt" "0,1" newline bitfld.long 0x0 8. "DMA_INTEGRITY_ERROR_INTCLR,ALGORITHM_INTEGRITY interrupt" "0,1" newline bitfld.long 0x0 3. "HASH_DONE_INTCLR,HASH_DONE interrupt" "0,1" newline bitfld.long 0x0 2. "CIPHER_DONE_INTCLR,CIPHER_DONE_INTCLRE" "0,1" newline bitfld.long 0x0 1. "SKC_DONE_INTCLR,KEYgen done interrupt enable" "0,1" newline bitfld.long 0x0 0. "DMA_DONE_INTCLR,DMA_DONE interrupt" "0,1" rgroup.long 0x5000++0x7 line.long 0x0 "CE5_STAT,CE5 working status" newline bitfld.long 0x0 4. "GENKEY_BUSY,1. CE5 generate key function is busy" "0,1" newline bitfld.long 0x0 3. "HASH_BUSY,1: the HASH of CE5 is busy" "?,the HASH of CE5 is busy" newline bitfld.long 0x0 2. "CIPHER_BUSY,1 the CIPHER of CE5 is busy" "0,1" newline bitfld.long 0x0 1. "GETRNDNUM_BUSY,1: get random number function of CE5 is busy" "?,get random number function of CE5 is busy" newline bitfld.long 0x0 0. "DMA_BUSY,1: the DMA of CE5 is busy 0: the DMA of CE5 is idle" "the DMA of CE5 is idle,the DMA of CE5 is busy" line.long 0x4 "CE5_ERRSTAT,CE5 error status" newline hexmask.long.byte 0x4 24.--27. 1. "SKC_ERR_STAT,'the error status of skc sequencer the bit 0 ~ 3 are [sram wr err] [ rand number fetch err] [ secure violation occurs] [reserved]'" newline bitfld.long 0x4 19. "SSRAM_ERR_STAT,'the error status of CE sram" "0,1" newline bitfld.long 0x4 16.--18. "DMA_ERR_STAT,'the error status of dma sequencer the bit of 0 -2 are [sram_rw_err] [wdma ch err] [rdma ch err]'" "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x4 8.--13. 1. "CIPHER_ERR_STAT,'the error status of cipher sequencer the bit 0 - 4 are [key_port_err] [rdma_ch_err] [wdma_ch_err] [sram_wr_err] [sram_rd_err] [decryption from secure to non-secure]'" newline hexmask.long.byte 0x4 0.--3. 1. "HASH_ERR_STAT,'the error status of hash sequencer the bit 0 ~ 3 are [sram_wr_err] [sram rd err] [rdma_err] [wdma err]'" group.long 0x500C++0x3F line.long 0x0 "CE5_CIPHER_CTRL,CE5 cipher control register" bitfld.long 0x0 31. "CIPHER_HEADER_SAVE,1 the header will be saved into dst memory 0: header will not be saved" "header will not be saved,?" newline bitfld.long 0x0 28.--29. "CIPHER_KEY2TYPE,key 2 type 10: input keyport 00: secure sram public area 01: secure area others: reserved" "secure sram public area,secure area others: reserved,?,?" newline bitfld.long 0x0 25.--26. "CIPHER_KEYTYPE,key type 10: input keyport 00: secure sram public area 01: secure area others: reserved" "secure sram public area,secure area others: reserved,?,?" newline hexmask.long.word 0x0 16.--24. 1. "AESMODE,'AES mode XTS : 010000000 ECB : 000000001 CBC : 000000010 CTR : 000000100 CFB : 000001000 OFB : 000010000 CCM : 000100000 GCM : 001000000 XTS : 010000000 CMAC: 100000000'" newline bitfld.long 0x0 13. "CIPHER_SAVE,0: normal mode last part of the message 1: operation context will be saved at the end of operation" "normal mode last part of the message,operation context will be saved at the end of.." newline bitfld.long 0x0 12. "CIPHER_LOAD,0 : normal mode first start of the message 1: operation restart from previously save context" "normal mode first start of the message,operation restart from previously save context" newline bitfld.long 0x0 11. "CIPHER_DECKEYCAL,0 use the input key for decryption operations 1: use the pre-calculation of the key is done before" "?,use the pre-calculation of the key is done before" newline bitfld.long 0x0 9.--10. "CIPHER_KEYSIZE,key size 00: 128bit key 01: 256 bit key 10: 192bit key 11: reserved" "0,1,2,3" newline bitfld.long 0x0 8. "CIPHERMODE,0 encryption 1 decryption" "0,1" newline bitfld.long 0x0 0. "CIPHER_GO,'write 1 to this bit will start the cipher operation'" "0,1" line.long 0x4 "CE5_CIPHER_HEADER_LEN,CE5 cipher header length register" hexmask.long 0x4 0.--31. 1. "CIPHER_HEADER_LEN,'cipher data header length in bytes'" line.long 0x8 "CE5_CIPHER_KEY_ADDR,CE5 cipher key addr register" hexmask.long.word 0x8 16.--31. 1. "CIPHER_KEY2_ADDR,key2 address in secure SRAM or keyport" newline hexmask.long.word 0x8 0.--15. 1. "CIPHER_KEY_ADDR,CIPHER_KEY_ADDR address in secure SRAM or keyport" line.long 0xC "CE5_CIPHER_SRC_ADDR,CE5 cipher source data addr register" hexmask.long 0xC 0.--31. 1. "CIPHER_SRC_ADDR,cipher data source address in bytes" line.long 0x10 "CE5_CIPHER_SRC_ADDR_H,CE5 cipher source data addr high register" newline bitfld.long 0x10 8.--10. "CIPHER_SRC_TYPE,011: CE SRAM Secure AREA 001:CE SRAM public area 000:external memories other: reserved" "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x10 0.--7. 1. "CIPHER_SRC_ADDR_H,the high part of CE5 cipher source address" line.long 0x14 "CE5_CIPHER_DST_ADDR,CE5 cipher destination data addr register" hexmask.long 0x14 0.--31. 1. "CIPHER_DST_ADDR,CE5 cipher data destination address" line.long 0x18 "CE5_CIPHER_DST_ADDR_H,CE5 cipher destination data addr high register" newline bitfld.long 0x18 8.--10. "CIPHER_DST_TYPE,011: CE SRAM Secure AREA 001:CE SRAM public area 000:external memories other: reserved" "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x18 0.--7. 1. "CIPHER_DST_ADDR_H,CE5 cipher data destination address" line.long 0x1C "CE5_CIPHER_IV_CONTEXT_ADDR,CE5 cipher IV and context addr register" hexmask.long.word 0x1C 16.--31. 1. "CIPHER_CONTEXT_ADDR,CIPHER context storage address the context is always stored into SRAM secure area" newline hexmask.long.word 0x1C 0.--15. 1. "CIPHER_IV_ADDR,CIPHER iv storage address the iv is always stored into SRAM secure area" line.long 0x20 "CE5_CIPHER_PAYLOAD_LEN,CE5 cipher payload length register" hexmask.long 0x20 0.--31. 1. "CIPHER_PAYLOAD_LEN,CIPHER_PAYLOAD_LEN including the header length in byte" line.long 0x24 "CE5_HASH_CTRL,CE5 hash control register" newline bitfld.long 0x24 24. "HASH_HMAC_EN,1: hmac is enabled 0: hmac is disabled" "hmac is disabled,hmac is enabled" newline bitfld.long 0x24 19. "HASH_KEY,1 need to load key 0 donot load key" "0,1" newline bitfld.long 0x24 18. "HASH_INIT_SECURE,1 load IV from secure area 0: load IV from public area" "load IV from public area,?" newline bitfld.long 0x24 17. "HASH_INIT,1 load IV for the hash 0 not load initial vector" "0,1" newline bitfld.long 0x24 16. "HASH_SHAUPDATE,0 final SHA224 output 7 words and SHA384 output 6 words 1: update SHA224/384 output 8 words please don't use this feature in hmac mode" "?,update SHA224/384 output 8 words please don't.." newline bitfld.long 0x24 15. "HASH_PADDINGEN,0: bypass padding logic 1: use hw padding logic" "bypass padding logic,use hw padding logic" newline hexmask.long.byte 0x24 8.--14. 1. "HASH_MODE,0000001 MD5 0000010 SHA1 0000100 SHA224 0001000 SHA256 0010000 SHA384 0100000 SHA512 1000000 SM3" newline bitfld.long 0x24 0. "HASH_GO,HASH Calculation start" "0,1" line.long 0x28 "CE5_HASH_KEYIV_ADDR,CE5 hash key and IV address register" hexmask.long.word 0x28 16.--31. 1. "HASH_KEY_ADDR,HASH_KEY address" newline hexmask.long.word 0x28 0.--15. 1. "HASH_IV_ADDR,HASH initial vection address" line.long 0x2C "CE5_HMAC_KEY_CTRL,CE5 hmac key control register" newline bitfld.long 0x2C 16.--17. "HMAC_KEY_TYPE,10 from key interface 01: from SRAM secure area 00 from SRAM public area" "?,from SRAM secure area 00 from SRAM public area,?,?" newline hexmask.long.word 0x2C 0.--15. 1. "HMAC_KEY_LEN,CE5 hash key length in CE SRAM" line.long 0x30 "CE5_HASH_CALC_LEN,CE5 hash calcluation length register" hexmask.long 0x30 0.--31. 1. "HASH_CALC_LEN,CE5 hash calculation length in bytes" line.long 0x34 "CE5_HASH_SRC_ADDR,CE5 hash source address register" hexmask.long 0x34 0.--31. 1. "HASH_SRC_ADDR,CE5 HASH SRC ADDR" line.long 0x38 "CE5_HASH_SRC_ADDR_H,CE5 hash source address high register" newline bitfld.long 0x38 8.--10. "HASH_SRC_TYPE,000: external memory 001: CE SRAM public area 011 CE sram secure area 1xx: SKC key interface space" "external memory,CE SRAM public area 011 CE sram secure area 1xx:..,?,?,?,?,?,?" newline hexmask.long.byte 0x38 0.--7. 1. "HASH_SRC_ADDR_H,the high part of CE5 hash src address" line.long 0x3C "CE5_HASH_DST_ADDR,CE5 hash destination address register" newline bitfld.long 0x3C 16.--18. "HASH_DST_TYPE,001 internal secure SRAM 001 public area in secure ram 1xx key interface" "0,1,2,3,4,5,6,7" newline hexmask.long.word 0x3C 0.--15. 1. "HASH_DST_ADDR,the dst address in secure SRAM" group.long 0x5050++0x17 line.long 0x0 "CE5_DMA_CTRL,CE5_DMA_CTRL" newline bitfld.long 0x0 10. "DMA_DONEINTEN,1 the interrupt will be generated if the DMA operation is done" "0,1" newline bitfld.long 0x0 0. "DMA_GO,write 1 to this register start CE5 DMA operation" "0,1" line.long 0x4 "CE5_DMA_SRC_ADDR,CE5 dma source address register" hexmask.long 0x4 0.--31. 1. "DMA_SRC_ADDR,CE5 dma source addr" line.long 0x8 "CE5_DMA_SRC_ADDR_H,CE5 dma source address high register" newline bitfld.long 0x8 8.--10. "DMA_SRC_TYPE,011: CE SRAM Secure AREA 001/010:CE SRAM public area 000:external memories other: reserved" "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x8 0.--7. 1. "DMA_SRC_ADDR_H,CE5 dma source addr high part" line.long 0xC "CE5_DMA_DST_ADDR,CE5 dma destination address register" hexmask.long 0xC 0.--31. 1. "DMA_DST_ADDR,CE5 DMA DST ADDR" line.long 0x10 "CE5_DMA_DST_ADDR_H,CE5 dma destination address high register" newline bitfld.long 0x10 8.--10. "DMA_DST_TYPE,011: CE SRAM Secure AREA 001/010:CE SRAM public area 000:external memories other: reserved" "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x10 0.--7. 1. "DMA_DST_ADDR_H,CE5 DMA DST ADDR high part" line.long 0x14 "CE5_DMA_LEN,CE5 dma transer length register" newline hexmask.long.word 0x14 0.--15. 1. "DMA_LEN,DMA transfer length in byte" rgroup.long 0x5100++0x3 line.long 0x0 "CE5_TRNG_STATUS,CE5_TRNG_STATUS" newline bitfld.long 0x0 1. "RNG_SEQ_RUNNING,'1: the rng sequencer is running currently 0: rng sequencer is in idle status'" "rng sequencer is in idle status',the rng sequencer is running currently" newline bitfld.long 0x0 0. "RNG_READY,'1: the value in the random number register of CE5 is valid" "?,the value in the random number register of CE5.." repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) rgroup.long ($2+0x5104)++0x3 line.long 0x0 "CE5_TRNG_NUM$1,CE5_TRNG_NUM0" hexmask.long 0x0 0.--31. 1. "TRNG_NUM0,CE5 the random number0 value" repeat.end rgroup.long 0x5114++0x3 line.long 0x0 "CE5_HRNG_NUM,CE5_HRNG_NUM" hexmask.long 0x0 0.--31. 1. "HRNG_NUM,CE5 the hybird random number value" group.long 0x5120++0xB line.long 0x0 "CE5_SKC_CTRL,CE5_SKC_CTRL" newline bitfld.long 0x0 8.--10. "SKC_CMD,the command of SKC 001: generate random number 010: erase key contrainer" "?,generate random number,?,?,?,?,?,?" newline bitfld.long 0x0 0. "SKC_GO,CE5 secure FSM start trigger" "0,1" line.long 0x4 "CE5_SKC_RNG_ADDR,CE5_SKC_RNG_ADDR" newline bitfld.long 0x4 24. "SKC_RNG_SECURE,CE5 1: random number generated to secure area 0 : in public area" "in public area,random number generated to secure area" newline hexmask.long.byte 0x4 16.--22. 1. "SKC_RNG_LEN,'numbers of bits to generate into sram granularity is 256 bit'" newline hexmask.long.word 0x4 0.--12. 1. "SKC_RNG_ADDR,CE5 random number generation address in CE sram the address granularity is 8 bytes" line.long 0x8 "CE5_SKC_KEYBLOB_CTRL,CE5_SKC_KEYBLOB_CTRL" newline bitfld.long 0x8 0. "SKC_KEYBLOB_CTRL,CE5 key blob control 1: is key blob :0 : is the secret data" "?,is key blob :0 : is the secret data" group.long 0x5140++0x3 line.long 0x0 "CE5_INTEN,CE5_INTEN" newline bitfld.long 0x0 11. "HASH_INTEGRITY_ERROR_INTEN,ALGORITHM_INTEGRITY_ERROR interrupt" "0,1" newline bitfld.long 0x0 10. "CIPHER_INTEGRITY_ERROR_INTEN,ALGORITHM_INTEGRITY_ERROR interrupt" "0,1" newline bitfld.long 0x0 9. "SKC_INTEGRITY_ERROR_INTEN,SKC_INTEGRITY_ERROR interrupt" "0,1" newline bitfld.long 0x0 8. "DMA_INTEGRITY_ERROR_INTEN,ALGORITHM_INTEGRITY interrupt" "0,1" newline bitfld.long 0x0 3. "HASH_DONE_INTEN,HASH_DONE interrupt" "0,1" newline bitfld.long 0x0 2. "CIPHER_DONE_INTEN,CIPHER_DONE_INTEN" "0,1" newline bitfld.long 0x0 1. "SKC_DONE_INTEN,KEYgen done interrupt enable" "0,1" newline bitfld.long 0x0 0. "DMA_DONE_INTEN,DMA_DONE interrupt" "0,1" rgroup.long 0x5144++0x3 line.long 0x0 "CE5_INTSTAT,CE5_INTSTAT" newline bitfld.long 0x0 11. "HASH_INTEGRITY_ERROR_INTSTAT,ALGORITHM_INTEGRITY_ERROR interrupt" "0,1" newline bitfld.long 0x0 10. "CIPHER_INTEGRITY_ERROR_INTSTAT,ALGORITHM_INTEGRITY_ERROR interrupt" "0,1" newline bitfld.long 0x0 9. "SKC_INTEGRITY_ERROR_INTSTAT,SKC_INTEGRITY_ERROR interrupt" "0,1" newline bitfld.long 0x0 8. "DMA_INTEGRITY_ERROR_INTSTAT,ALGORITHM_INTEGRITY interrupt" "0,1" newline bitfld.long 0x0 3. "HASH_DONE_INTSTAT,HASH_DONE interrupt" "0,1" newline bitfld.long 0x0 2. "CIPHER_DONE_INTSTAT,CIPHER_DONE_INTSTATE" "0,1" newline bitfld.long 0x0 1. "SKC_DONE_INTSTAT,KEYgen done interrupt enable" "0,1" newline bitfld.long 0x0 0. "DMA_DONE_INTSTAT,DMA_DONE interrupt" "0,1" group.long 0x5148++0x3 line.long 0x0 "CE5_INTCLR,CE5_INTCLR" newline bitfld.long 0x0 11. "HASH_INTEGRITY_ERROR_INTCLR,ALGORITHM_INTEGRITY_ERROR interrupt" "0,1" newline bitfld.long 0x0 10. "CIPHER_INTEGRITY_ERROR_INTCLR,ALGORITHM_INTEGRITY_ERROR interrupt" "0,1" newline bitfld.long 0x0 9. "SKC_INTEGRITY_ERROR_INTCLR,SKC_INTEGRITY_ERROR interrupt" "0,1" newline bitfld.long 0x0 8. "DMA_INTEGRITY_ERROR_INTCLR,ALGORITHM_INTEGRITY interrupt" "0,1" newline bitfld.long 0x0 3. "HASH_DONE_INTCLR,HASH_DONE interrupt" "0,1" newline bitfld.long 0x0 2. "CIPHER_DONE_INTCLR,CIPHER_DONE_INTCLRE" "0,1" newline bitfld.long 0x0 1. "SKC_DONE_INTCLR,KEYgen done interrupt enable" "0,1" newline bitfld.long 0x0 0. "DMA_DONE_INTCLR,DMA_DONE interrupt" "0,1" rgroup.long 0x6000++0x7 line.long 0x0 "CE6_STAT,CE6 working status" newline bitfld.long 0x0 4. "GENKEY_BUSY,1. CE6 generate key function is busy" "0,1" newline bitfld.long 0x0 3. "HASH_BUSY,1: the HASH of CE6 is busy" "?,the HASH of CE6 is busy" newline bitfld.long 0x0 2. "CIPHER_BUSY,1 the CIPHER of CE6 is busy" "0,1" newline bitfld.long 0x0 1. "GETRNDNUM_BUSY,1: get random number function of CE6 is busy" "?,get random number function of CE6 is busy" newline bitfld.long 0x0 0. "DMA_BUSY,1: the DMA of CE6 is busy 0: the DMA of CE6 is idle" "the DMA of CE6 is idle,the DMA of CE6 is busy" line.long 0x4 "CE6_ERRSTAT,CE6 error status" newline hexmask.long.byte 0x4 24.--27. 1. "SKC_ERR_STAT,'the error status of skc sequencer the bit 0 ~ 3 are [sram wr err] [ rand number fetch err] [ secure violation occurs] [reserved]'" newline bitfld.long 0x4 19. "SSRAM_ERR_STAT,'the error status of CE sram" "0,1" newline bitfld.long 0x4 16.--18. "DMA_ERR_STAT,'the error status of dma sequencer the bit of 0 -2 are [sram_rw_err] [wdma ch err] [rdma ch err]'" "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x4 8.--13. 1. "CIPHER_ERR_STAT,'the error status of cipher sequencer the bit 0 - 4 are [key_port_err] [rdma_ch_err] [wdma_ch_err] [sram_wr_err] [sram_rd_err] [decryption from secure to non-secure]'" newline hexmask.long.byte 0x4 0.--3. 1. "HASH_ERR_STAT,'the error status of hash sequencer the bit 0 ~ 3 are [sram_wr_err] [sram rd err] [rdma_err] [wdma err]'" group.long 0x600C++0x3F line.long 0x0 "CE6_CIPHER_CTRL,CE6 cipher control register" bitfld.long 0x0 31. "CIPHER_HEADER_SAVE,1 the header will be saved into dst memory 0: header will not be saved" "header will not be saved,?" newline bitfld.long 0x0 28.--29. "CIPHER_KEY2TYPE,key 2 type 10: input keyport 00: secure sram public area 01: secure area others: reserved" "secure sram public area,secure area others: reserved,?,?" newline bitfld.long 0x0 25.--26. "CIPHER_KEYTYPE,key type 10: input keyport 00: secure sram public area 01: secure area others: reserved" "secure sram public area,secure area others: reserved,?,?" newline hexmask.long.word 0x0 16.--24. 1. "AESMODE,'AES mode XTS : 010000000 ECB : 000000001 CBC : 000000010 CTR : 000000100 CFB : 000001000 OFB : 000010000 CCM : 000100000 GCM : 001000000 XTS : 010000000 CMAC: 100000000'" newline bitfld.long 0x0 13. "CIPHER_SAVE,0: normal mode last part of the message 1: operation context will be saved at the end of operation" "normal mode last part of the message,operation context will be saved at the end of.." newline bitfld.long 0x0 12. "CIPHER_LOAD,0 : normal mode first start of the message 1: operation restart from previously save context" "normal mode first start of the message,operation restart from previously save context" newline bitfld.long 0x0 11. "CIPHER_DECKEYCAL,0 use the input key for decryption operations 1: use the pre-calculation of the key is done before" "?,use the pre-calculation of the key is done before" newline bitfld.long 0x0 9.--10. "CIPHER_KEYSIZE,key size 00: 128bit key 01: 256 bit key 10: 192bit key 11: reserved" "0,1,2,3" newline bitfld.long 0x0 8. "CIPHERMODE,0 encryption 1 decryption" "0,1" newline bitfld.long 0x0 0. "CIPHER_GO,'write 1 to this bit will start the cipher operation'" "0,1" line.long 0x4 "CE6_CIPHER_HEADER_LEN,CE6 cipher header length register" hexmask.long 0x4 0.--31. 1. "CIPHER_HEADER_LEN,'cipher data header length in bytes'" line.long 0x8 "CE6_CIPHER_KEY_ADDR,CE6 cipher key addr register" hexmask.long.word 0x8 16.--31. 1. "CIPHER_KEY2_ADDR,key2 address in secure SRAM or keyport" newline hexmask.long.word 0x8 0.--15. 1. "CIPHER_KEY_ADDR,CIPHER_KEY_ADDR address in secure SRAM or keyport" line.long 0xC "CE6_CIPHER_SRC_ADDR,CE6 cipher source data addr register" hexmask.long 0xC 0.--31. 1. "CIPHER_SRC_ADDR,cipher data source address in bytes" line.long 0x10 "CE6_CIPHER_SRC_ADDR_H,CE6 cipher source data addr high register" newline bitfld.long 0x10 8.--10. "CIPHER_SRC_TYPE,011: CE SRAM Secure AREA 001:CE SRAM public area 000:external memories other: reserved" "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x10 0.--7. 1. "CIPHER_SRC_ADDR_H,the high part of CE6 cipher source address" line.long 0x14 "CE6_CIPHER_DST_ADDR,CE6 cipher destination data addr register" hexmask.long 0x14 0.--31. 1. "CIPHER_DST_ADDR,CE6 cipher data destination address" line.long 0x18 "CE6_CIPHER_DST_ADDR_H,CE6 cipher destination data addr high register" newline bitfld.long 0x18 8.--10. "CIPHER_DST_TYPE,011: CE SRAM Secure AREA 001:CE SRAM public area 000:external memories other: reserved" "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x18 0.--7. 1. "CIPHER_DST_ADDR_H,CE6 cipher data destination address" line.long 0x1C "CE6_CIPHER_IV_CONTEXT_ADDR,CE6 cipher IV and context addr register" hexmask.long.word 0x1C 16.--31. 1. "CIPHER_CONTEXT_ADDR,CIPHER context storage address the context is always stored into SRAM secure area" newline hexmask.long.word 0x1C 0.--15. 1. "CIPHER_IV_ADDR,CIPHER iv storage address the iv is always stored into SRAM secure area" line.long 0x20 "CE6_CIPHER_PAYLOAD_LEN,CE6 cipher payload length register" hexmask.long 0x20 0.--31. 1. "CIPHER_PAYLOAD_LEN,CIPHER_PAYLOAD_LEN including the header length in byte" line.long 0x24 "CE6_HASH_CTRL,CE6 hash control register" newline bitfld.long 0x24 24. "HASH_HMAC_EN,1: hmac is enabled 0: hmac is disabled" "hmac is disabled,hmac is enabled" newline bitfld.long 0x24 19. "HASH_KEY,1 need to load key 0 donot load key" "0,1" newline bitfld.long 0x24 18. "HASH_INIT_SECURE,1 load IV from secure area 0: load IV from public area" "load IV from public area,?" newline bitfld.long 0x24 17. "HASH_INIT,1 load IV for the hash 0 not load initial vector" "0,1" newline bitfld.long 0x24 16. "HASH_SHAUPDATE,0 final SHA224 output 7 words and SHA384 output 6 words 1: update SHA224/384 output 8 words please don't use this feature in hmac mode" "?,update SHA224/384 output 8 words please don't.." newline bitfld.long 0x24 15. "HASH_PADDINGEN,0: bypass padding logic 1: use hw padding logic" "bypass padding logic,use hw padding logic" newline hexmask.long.byte 0x24 8.--14. 1. "HASH_MODE,0000001 MD5 0000010 SHA1 0000100 SHA224 0001000 SHA256 0010000 SHA384 0100000 SHA512 1000000 SM3" newline bitfld.long 0x24 0. "HASH_GO,HASH Calculation start" "0,1" line.long 0x28 "CE6_HASH_KEYIV_ADDR,CE6 hash key and IV address register" hexmask.long.word 0x28 16.--31. 1. "HASH_KEY_ADDR,HASH_KEY address" newline hexmask.long.word 0x28 0.--15. 1. "HASH_IV_ADDR,HASH initial vection address" line.long 0x2C "CE6_HMAC_KEY_CTRL,CE6 hmac key control register" newline bitfld.long 0x2C 16.--17. "HMAC_KEY_TYPE,10 from key interface 01: from SRAM secure area 00 from SRAM public area" "?,from SRAM secure area 00 from SRAM public area,?,?" newline hexmask.long.word 0x2C 0.--15. 1. "HMAC_KEY_LEN,CE6 hash key length in CE SRAM" line.long 0x30 "CE6_HASH_CALC_LEN,CE6 hash calcluation length register" hexmask.long 0x30 0.--31. 1. "HASH_CALC_LEN,CE6 hash calculation length in bytes" line.long 0x34 "CE6_HASH_SRC_ADDR,CE6 hash source address register" hexmask.long 0x34 0.--31. 1. "HASH_SRC_ADDR,CE6 HASH SRC ADDR" line.long 0x38 "CE6_HASH_SRC_ADDR_H,CE6 hash source address high register" newline bitfld.long 0x38 8.--10. "HASH_SRC_TYPE,000: external memory 001: CE SRAM public area 011 CE sram secure area 1xx: SKC key interface space" "external memory,CE SRAM public area 011 CE sram secure area 1xx:..,?,?,?,?,?,?" newline hexmask.long.byte 0x38 0.--7. 1. "HASH_SRC_ADDR_H,the high part of CE6 hash src address" line.long 0x3C "CE6_HASH_DST_ADDR,CE6 hash destination address register" newline bitfld.long 0x3C 16.--18. "HASH_DST_TYPE,001 internal secure SRAM 001 public area in secure ram 1xx key interface" "0,1,2,3,4,5,6,7" newline hexmask.long.word 0x3C 0.--15. 1. "HASH_DST_ADDR,the dst address in secure SRAM" group.long 0x6050++0x17 line.long 0x0 "CE6_DMA_CTRL,CE6_DMA_CTRL" newline bitfld.long 0x0 10. "DMA_DONEINTEN,1 the interrupt will be generated if the DMA operation is done" "0,1" newline bitfld.long 0x0 0. "DMA_GO,write 1 to this register start CE6 DMA operation" "0,1" line.long 0x4 "CE6_DMA_SRC_ADDR,CE6 dma source address register" hexmask.long 0x4 0.--31. 1. "DMA_SRC_ADDR,CE6 dma source addr" line.long 0x8 "CE6_DMA_SRC_ADDR_H,CE6 dma source address high register" newline bitfld.long 0x8 8.--10. "DMA_SRC_TYPE,011: CE SRAM Secure AREA 001/010:CE SRAM public area 000:external memories other: reserved" "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x8 0.--7. 1. "DMA_SRC_ADDR_H,CE6 dma source addr high part" line.long 0xC "CE6_DMA_DST_ADDR,CE6 dma destination address register" hexmask.long 0xC 0.--31. 1. "DMA_DST_ADDR,CE6 DMA DST ADDR" line.long 0x10 "CE6_DMA_DST_ADDR_H,CE6 dma destination address high register" newline bitfld.long 0x10 8.--10. "DMA_DST_TYPE,011: CE SRAM Secure AREA 001/010:CE SRAM public area 000:external memories other: reserved" "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x10 0.--7. 1. "DMA_DST_ADDR_H,CE6 DMA DST ADDR high part" line.long 0x14 "CE6_DMA_LEN,CE6 dma transer length register" newline hexmask.long.word 0x14 0.--15. 1. "DMA_LEN,DMA transfer length in byte" rgroup.long 0x6100++0x3 line.long 0x0 "CE6_TRNG_STATUS,CE6_TRNG_STATUS" newline bitfld.long 0x0 1. "RNG_SEQ_RUNNING,'1: the rng sequencer is running currently 0: rng sequencer is in idle status'" "rng sequencer is in idle status',the rng sequencer is running currently" newline bitfld.long 0x0 0. "RNG_READY,'1: the value in the random number register of CE6 is valid" "?,the value in the random number register of CE6.." repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) rgroup.long ($2+0x6104)++0x3 line.long 0x0 "CE6_TRNG_NUM$1,CE6_TRNG_NUM0" hexmask.long 0x0 0.--31. 1. "TRNG_NUM0,CE6 the random number0 value" repeat.end rgroup.long 0x6114++0x3 line.long 0x0 "CE6_HRNG_NUM,CE6_HRNG_NUM" hexmask.long 0x0 0.--31. 1. "HRNG_NUM,CE6 the hybird random number value" group.long 0x6120++0xB line.long 0x0 "CE6_SKC_CTRL,CE6_SKC_CTRL" newline bitfld.long 0x0 8.--10. "SKC_CMD,the command of SKC 001: generate random number 010: erase key contrainer" "?,generate random number,?,?,?,?,?,?" newline bitfld.long 0x0 0. "SKC_GO,CE6 secure FSM start trigger" "0,1" line.long 0x4 "CE6_SKC_RNG_ADDR,CE6_SKC_RNG_ADDR" newline bitfld.long 0x4 24. "SKC_RNG_SECURE,CE6 1: random number generated to secure area 0 : in public area" "in public area,random number generated to secure area" newline hexmask.long.byte 0x4 16.--22. 1. "SKC_RNG_LEN,'numbers of bits to generate into sram granularity is 256 bit'" newline hexmask.long.word 0x4 0.--12. 1. "SKC_RNG_ADDR,CE6 random number generation address in CE sram the address granularity is 8 bytes" line.long 0x8 "CE6_SKC_KEYBLOB_CTRL,CE6_SKC_KEYBLOB_CTRL" newline bitfld.long 0x8 0. "SKC_KEYBLOB_CTRL,CE6 key blob control 1: is key blob :0 : is the secret data" "?,is key blob :0 : is the secret data" group.long 0x6140++0x3 line.long 0x0 "CE6_INTEN,CE6_INTEN" newline bitfld.long 0x0 11. "HASH_INTEGRITY_ERROR_INTEN,ALGORITHM_INTEGRITY_ERROR interrupt" "0,1" newline bitfld.long 0x0 10. "CIPHER_INTEGRITY_ERROR_INTEN,ALGORITHM_INTEGRITY_ERROR interrupt" "0,1" newline bitfld.long 0x0 9. "SKC_INTEGRITY_ERROR_INTEN,SKC_INTEGRITY_ERROR interrupt" "0,1" newline bitfld.long 0x0 8. "DMA_INTEGRITY_ERROR_INTEN,ALGORITHM_INTEGRITY interrupt" "0,1" newline bitfld.long 0x0 3. "HASH_DONE_INTEN,HASH_DONE interrupt" "0,1" newline bitfld.long 0x0 2. "CIPHER_DONE_INTEN,CIPHER_DONE_INTEN" "0,1" newline bitfld.long 0x0 1. "SKC_DONE_INTEN,KEYgen done interrupt enable" "0,1" newline bitfld.long 0x0 0. "DMA_DONE_INTEN,DMA_DONE interrupt" "0,1" rgroup.long 0x6144++0x3 line.long 0x0 "CE6_INTSTAT,CE6_INTSTAT" newline bitfld.long 0x0 11. "HASH_INTEGRITY_ERROR_INTSTAT,ALGORITHM_INTEGRITY_ERROR interrupt" "0,1" newline bitfld.long 0x0 10. "CIPHER_INTEGRITY_ERROR_INTSTAT,ALGORITHM_INTEGRITY_ERROR interrupt" "0,1" newline bitfld.long 0x0 9. "SKC_INTEGRITY_ERROR_INTSTAT,SKC_INTEGRITY_ERROR interrupt" "0,1" newline bitfld.long 0x0 8. "DMA_INTEGRITY_ERROR_INTSTAT,ALGORITHM_INTEGRITY interrupt" "0,1" newline bitfld.long 0x0 3. "HASH_DONE_INTSTAT,HASH_DONE interrupt" "0,1" newline bitfld.long 0x0 2. "CIPHER_DONE_INTSTAT,CIPHER_DONE_INTSTATE" "0,1" newline bitfld.long 0x0 1. "SKC_DONE_INTSTAT,KEYgen done interrupt enable" "0,1" newline bitfld.long 0x0 0. "DMA_DONE_INTSTAT,DMA_DONE interrupt" "0,1" group.long 0x6148++0x3 line.long 0x0 "CE6_INTCLR,CE6_INTCLR" newline bitfld.long 0x0 11. "HASH_INTEGRITY_ERROR_INTCLR,ALGORITHM_INTEGRITY_ERROR interrupt" "0,1" newline bitfld.long 0x0 10. "CIPHER_INTEGRITY_ERROR_INTCLR,ALGORITHM_INTEGRITY_ERROR interrupt" "0,1" newline bitfld.long 0x0 9. "SKC_INTEGRITY_ERROR_INTCLR,SKC_INTEGRITY_ERROR interrupt" "0,1" newline bitfld.long 0x0 8. "DMA_INTEGRITY_ERROR_INTCLR,ALGORITHM_INTEGRITY interrupt" "0,1" newline bitfld.long 0x0 3. "HASH_DONE_INTCLR,HASH_DONE interrupt" "0,1" newline bitfld.long 0x0 2. "CIPHER_DONE_INTCLR,CIPHER_DONE_INTCLRE" "0,1" newline bitfld.long 0x0 1. "SKC_DONE_INTCLR,KEYgen done interrupt enable" "0,1" newline bitfld.long 0x0 0. "DMA_DONE_INTCLR,DMA_DONE interrupt" "0,1" rgroup.long 0x7000++0x7 line.long 0x0 "CE7_STAT,CE7 working status" newline bitfld.long 0x0 4. "GENKEY_BUSY,1. CE7 generate key function is busy" "0,1" newline bitfld.long 0x0 3. "HASH_BUSY,1: the HASH of CE7 is busy" "?,the HASH of CE7 is busy" newline bitfld.long 0x0 2. "CIPHER_BUSY,1 the CIPHER of CE7 is busy" "0,1" newline bitfld.long 0x0 1. "GETRNDNUM_BUSY,1: get random number function of CE7 is busy" "?,get random number function of CE7 is busy" newline bitfld.long 0x0 0. "DMA_BUSY,1: the DMA of CE7 is busy 0: the DMA of CE7 is idle" "the DMA of CE7 is idle,the DMA of CE7 is busy" line.long 0x4 "CE7_ERRSTAT,CE7 error status" newline hexmask.long.byte 0x4 24.--27. 1. "SKC_ERR_STAT,'the error status of skc sequencer the bit 0 ~ 3 are [sram wr err] [ rand number fetch err] [ secure violation occurs] [reserved]'" newline bitfld.long 0x4 19. "SSRAM_ERR_STAT,'the error status of CE sram" "0,1" newline bitfld.long 0x4 16.--18. "DMA_ERR_STAT,'the error status of dma sequencer the bit of 0 -2 are [sram_rw_err] [wdma ch err] [rdma ch err]'" "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x4 8.--13. 1. "CIPHER_ERR_STAT,'the error status of cipher sequencer the bit 0 - 4 are [key_port_err] [rdma_ch_err] [wdma_ch_err] [sram_wr_err] [sram_rd_err] [decryption from secure to non-secure]'" newline hexmask.long.byte 0x4 0.--3. 1. "HASH_ERR_STAT,'the error status of hash sequencer the bit 0 ~ 3 are [sram_wr_err] [sram rd err] [rdma_err] [wdma err]'" group.long 0x700C++0x3F line.long 0x0 "CE7_CIPHER_CTRL,CE7 cipher control register" bitfld.long 0x0 31. "CIPHER_HEADER_SAVE,1 the header will be saved into dst memory 0: header will not be saved" "header will not be saved,?" newline bitfld.long 0x0 28.--29. "CIPHER_KEY2TYPE,key 2 type 10: input keyport 00: secure sram public area 01: secure area others: reserved" "secure sram public area,secure area others: reserved,?,?" newline bitfld.long 0x0 25.--26. "CIPHER_KEYTYPE,key type 10: input keyport 00: secure sram public area 01: secure area others: reserved" "secure sram public area,secure area others: reserved,?,?" newline hexmask.long.word 0x0 16.--24. 1. "AESMODE,'AES mode XTS : 010000000 ECB : 000000001 CBC : 000000010 CTR : 000000100 CFB : 000001000 OFB : 000010000 CCM : 000100000 GCM : 001000000 XTS : 010000000 CMAC: 100000000'" newline bitfld.long 0x0 13. "CIPHER_SAVE,0: normal mode last part of the message 1: operation context will be saved at the end of operation" "normal mode last part of the message,operation context will be saved at the end of.." newline bitfld.long 0x0 12. "CIPHER_LOAD,0 : normal mode first start of the message 1: operation restart from previously save context" "normal mode first start of the message,operation restart from previously save context" newline bitfld.long 0x0 11. "CIPHER_DECKEYCAL,0 use the input key for decryption operations 1: use the pre-calculation of the key is done before" "?,use the pre-calculation of the key is done before" newline bitfld.long 0x0 9.--10. "CIPHER_KEYSIZE,key size 00: 128bit key 01: 256 bit key 10: 192bit key 11: reserved" "0,1,2,3" newline bitfld.long 0x0 8. "CIPHERMODE,0 encryption 1 decryption" "0,1" newline bitfld.long 0x0 0. "CIPHER_GO,'write 1 to this bit will start the cipher operation'" "0,1" line.long 0x4 "CE7_CIPHER_HEADER_LEN,CE7 cipher header length register" hexmask.long 0x4 0.--31. 1. "CIPHER_HEADER_LEN,'cipher data header length in bytes'" line.long 0x8 "CE7_CIPHER_KEY_ADDR,CE7 cipher key addr register" hexmask.long.word 0x8 16.--31. 1. "CIPHER_KEY2_ADDR,key2 address in secure SRAM or keyport" newline hexmask.long.word 0x8 0.--15. 1. "CIPHER_KEY_ADDR,CIPHER_KEY_ADDR address in secure SRAM or keyport" line.long 0xC "CE7_CIPHER_SRC_ADDR,CE7 cipher source data addr register" hexmask.long 0xC 0.--31. 1. "CIPHER_SRC_ADDR,cipher data source address in bytes" line.long 0x10 "CE7_CIPHER_SRC_ADDR_H,CE7 cipher source data addr high register" newline bitfld.long 0x10 8.--10. "CIPHER_SRC_TYPE,011: CE SRAM Secure AREA 001:CE SRAM public area 000:external memories other: reserved" "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x10 0.--7. 1. "CIPHER_SRC_ADDR_H,the high part of CE7 cipher source address" line.long 0x14 "CE7_CIPHER_DST_ADDR,CE7 cipher destination data addr register" hexmask.long 0x14 0.--31. 1. "CIPHER_DST_ADDR,CE7 cipher data destination address" line.long 0x18 "CE7_CIPHER_DST_ADDR_H,CE7 cipher destination data addr high register" newline bitfld.long 0x18 8.--10. "CIPHER_DST_TYPE,011: CE SRAM Secure AREA 001:CE SRAM public area 000:external memories other: reserved" "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x18 0.--7. 1. "CIPHER_DST_ADDR_H,CE7 cipher data destination address" line.long 0x1C "CE7_CIPHER_IV_CONTEXT_ADDR,CE7 cipher IV and context addr register" hexmask.long.word 0x1C 16.--31. 1. "CIPHER_CONTEXT_ADDR,CIPHER context storage address the context is always stored into SRAM secure area" newline hexmask.long.word 0x1C 0.--15. 1. "CIPHER_IV_ADDR,CIPHER iv storage address the iv is always stored into SRAM secure area" line.long 0x20 "CE7_CIPHER_PAYLOAD_LEN,CE7 cipher payload length register" hexmask.long 0x20 0.--31. 1. "CIPHER_PAYLOAD_LEN,CIPHER_PAYLOAD_LEN including the header length in byte" line.long 0x24 "CE7_HASH_CTRL,CE7 hash control register" newline bitfld.long 0x24 24. "HASH_HMAC_EN,1: hmac is enabled 0: hmac is disabled" "hmac is disabled,hmac is enabled" newline bitfld.long 0x24 19. "HASH_KEY,1 need to load key 0 donot load key" "0,1" newline bitfld.long 0x24 18. "HASH_INIT_SECURE,1 load IV from secure area 0: load IV from public area" "load IV from public area,?" newline bitfld.long 0x24 17. "HASH_INIT,1 load IV for the hash 0 not load initial vector" "0,1" newline bitfld.long 0x24 16. "HASH_SHAUPDATE,0 final SHA224 output 7 words and SHA384 output 6 words 1: update SHA224/384 output 8 words please don't use this feature in hmac mode" "?,update SHA224/384 output 8 words please don't.." newline bitfld.long 0x24 15. "HASH_PADDINGEN,0: bypass padding logic 1: use hw padding logic" "bypass padding logic,use hw padding logic" newline hexmask.long.byte 0x24 8.--14. 1. "HASH_MODE,0000001 MD5 0000010 SHA1 0000100 SHA224 0001000 SHA256 0010000 SHA384 0100000 SHA512 1000000 SM3" newline bitfld.long 0x24 0. "HASH_GO,HASH Calculation start" "0,1" line.long 0x28 "CE7_HASH_KEYIV_ADDR,CE7 hash key and IV address register" hexmask.long.word 0x28 16.--31. 1. "HASH_KEY_ADDR,HASH_KEY address" newline hexmask.long.word 0x28 0.--15. 1. "HASH_IV_ADDR,HASH initial vection address" line.long 0x2C "CE7_HMAC_KEY_CTRL,CE7 hmac key control register" newline bitfld.long 0x2C 16.--17. "HMAC_KEY_TYPE,10 from key interface 01: from SRAM secure area 00 from SRAM public area" "?,from SRAM secure area 00 from SRAM public area,?,?" newline hexmask.long.word 0x2C 0.--15. 1. "HMAC_KEY_LEN,CE7 hash key length in CE SRAM" line.long 0x30 "CE7_HASH_CALC_LEN,CE7 hash calcluation length register" hexmask.long 0x30 0.--31. 1. "HASH_CALC_LEN,CE7 hash calculation length in bytes" line.long 0x34 "CE7_HASH_SRC_ADDR,CE7 hash source address register" hexmask.long 0x34 0.--31. 1. "HASH_SRC_ADDR,CE7 HASH SRC ADDR" line.long 0x38 "CE7_HASH_SRC_ADDR_H,CE7 hash source address high register" newline bitfld.long 0x38 8.--10. "HASH_SRC_TYPE,000: external memory 001: CE SRAM public area 011 CE sram secure area 1xx: SKC key interface space" "external memory,CE SRAM public area 011 CE sram secure area 1xx:..,?,?,?,?,?,?" newline hexmask.long.byte 0x38 0.--7. 1. "HASH_SRC_ADDR_H,the high part of CE7 hash src address" line.long 0x3C "CE7_HASH_DST_ADDR,CE7 hash destination address register" newline bitfld.long 0x3C 16.--18. "HASH_DST_TYPE,001 internal secure SRAM 001 public area in secure ram 1xx key interface" "0,1,2,3,4,5,6,7" newline hexmask.long.word 0x3C 0.--15. 1. "HASH_DST_ADDR,the dst address in secure SRAM" group.long 0x7050++0x17 line.long 0x0 "CE7_DMA_CTRL,CE7_DMA_CTRL" newline bitfld.long 0x0 10. "DMA_DONEINTEN,1 the interrupt will be generated if the DMA operation is done" "0,1" newline bitfld.long 0x0 0. "DMA_GO,write 1 to this register start CE7 DMA operation" "0,1" line.long 0x4 "CE7_DMA_SRC_ADDR,CE7 dma source address register" hexmask.long 0x4 0.--31. 1. "DMA_SRC_ADDR,CE7 dma source addr" line.long 0x8 "CE7_DMA_SRC_ADDR_H,CE7 dma source address high register" newline bitfld.long 0x8 8.--10. "DMA_SRC_TYPE,011: CE SRAM Secure AREA 001/010:CE SRAM public area 000:external memories other: reserved" "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x8 0.--7. 1. "DMA_SRC_ADDR_H,CE7 dma source addr high part" line.long 0xC "CE7_DMA_DST_ADDR,CE7 dma destination address register" hexmask.long 0xC 0.--31. 1. "DMA_DST_ADDR,CE7 DMA DST ADDR" line.long 0x10 "CE7_DMA_DST_ADDR_H,CE7 dma destination address high register" newline bitfld.long 0x10 8.--10. "DMA_DST_TYPE,011: CE SRAM Secure AREA 001/010:CE SRAM public area 000:external memories other: reserved" "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x10 0.--7. 1. "DMA_DST_ADDR_H,CE7 DMA DST ADDR high part" line.long 0x14 "CE7_DMA_LEN,CE7 dma transer length register" newline hexmask.long.word 0x14 0.--15. 1. "DMA_LEN,DMA transfer length in byte" rgroup.long 0x7100++0x3 line.long 0x0 "CE7_TRNG_STATUS,CE7_TRNG_STATUS" newline bitfld.long 0x0 1. "RNG_SEQ_RUNNING,'1: the rng sequencer is running currently 0: rng sequencer is in idle status'" "rng sequencer is in idle status',the rng sequencer is running currently" newline bitfld.long 0x0 0. "RNG_READY,'1: the value in the random number register of CE7 is valid" "?,the value in the random number register of CE7.." repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) rgroup.long ($2+0x7104)++0x3 line.long 0x0 "CE7_TRNG_NUM$1,CE7_TRNG_NUM0" hexmask.long 0x0 0.--31. 1. "TRNG_NUM0,CE7 the random number0 value" repeat.end rgroup.long 0x7114++0x3 line.long 0x0 "CE7_HRNG_NUM,CE7_HRNG_NUM" hexmask.long 0x0 0.--31. 1. "HRNG_NUM,CE7 the hybird random number value" group.long 0x7120++0xB line.long 0x0 "CE7_SKC_CTRL,CE7_SKC_CTRL" newline bitfld.long 0x0 8.--10. "SKC_CMD,the command of SKC 001: generate random number 010: erase key contrainer" "?,generate random number,?,?,?,?,?,?" newline bitfld.long 0x0 0. "SKC_GO,CE7 secure FSM start trigger" "0,1" line.long 0x4 "CE7_SKC_RNG_ADDR,CE7_SKC_RNG_ADDR" newline bitfld.long 0x4 24. "SKC_RNG_SECURE,CE7 1: random number generated to secure area 0 : in public area" "in public area,random number generated to secure area" newline hexmask.long.byte 0x4 16.--22. 1. "SKC_RNG_LEN,'numbers of bits to generate into sram granularity is 256 bit'" newline hexmask.long.word 0x4 0.--12. 1. "SKC_RNG_ADDR,CE7 random number generation address in CE sram the address granularity is 8 bytes" line.long 0x8 "CE7_SKC_KEYBLOB_CTRL,CE7_SKC_KEYBLOB_CTRL" newline bitfld.long 0x8 0. "SKC_KEYBLOB_CTRL,CE7 key blob control 1: is key blob :0 : is the secret data" "?,is key blob :0 : is the secret data" group.long 0x7140++0x3 line.long 0x0 "CE7_INTEN,CE7_INTEN" newline bitfld.long 0x0 11. "HASH_INTEGRITY_ERROR_INTEN,ALGORITHM_INTEGRITY_ERROR interrupt" "0,1" newline bitfld.long 0x0 10. "CIPHER_INTEGRITY_ERROR_INTEN,ALGORITHM_INTEGRITY_ERROR interrupt" "0,1" newline bitfld.long 0x0 9. "SKC_INTEGRITY_ERROR_INTEN,SKC_INTEGRITY_ERROR interrupt" "0,1" newline bitfld.long 0x0 8. "DMA_INTEGRITY_ERROR_INTEN,ALGORITHM_INTEGRITY interrupt" "0,1" newline bitfld.long 0x0 3. "HASH_DONE_INTEN,HASH_DONE interrupt" "0,1" newline bitfld.long 0x0 2. "CIPHER_DONE_INTEN,CIPHER_DONE_INTEN" "0,1" newline bitfld.long 0x0 1. "SKC_DONE_INTEN,KEYgen done interrupt enable" "0,1" newline bitfld.long 0x0 0. "DMA_DONE_INTEN,DMA_DONE interrupt" "0,1" rgroup.long 0x7144++0x3 line.long 0x0 "CE7_INTSTAT,CE7_INTSTAT" newline bitfld.long 0x0 11. "HASH_INTEGRITY_ERROR_INTSTAT,ALGORITHM_INTEGRITY_ERROR interrupt" "0,1" newline bitfld.long 0x0 10. "CIPHER_INTEGRITY_ERROR_INTSTAT,ALGORITHM_INTEGRITY_ERROR interrupt" "0,1" newline bitfld.long 0x0 9. "SKC_INTEGRITY_ERROR_INTSTAT,SKC_INTEGRITY_ERROR interrupt" "0,1" newline bitfld.long 0x0 8. "DMA_INTEGRITY_ERROR_INTSTAT,ALGORITHM_INTEGRITY interrupt" "0,1" newline bitfld.long 0x0 3. "HASH_DONE_INTSTAT,HASH_DONE interrupt" "0,1" newline bitfld.long 0x0 2. "CIPHER_DONE_INTSTAT,CIPHER_DONE_INTSTATE" "0,1" newline bitfld.long 0x0 1. "SKC_DONE_INTSTAT,KEYgen done interrupt enable" "0,1" newline bitfld.long 0x0 0. "DMA_DONE_INTSTAT,DMA_DONE interrupt" "0,1" group.long 0x7148++0x3 line.long 0x0 "CE7_INTCLR,CE7_INTCLR" newline bitfld.long 0x0 11. "HASH_INTEGRITY_ERROR_INTCLR,ALGORITHM_INTEGRITY_ERROR interrupt" "0,1" newline bitfld.long 0x0 10. "CIPHER_INTEGRITY_ERROR_INTCLR,ALGORITHM_INTEGRITY_ERROR interrupt" "0,1" newline bitfld.long 0x0 9. "SKC_INTEGRITY_ERROR_INTCLR,SKC_INTEGRITY_ERROR interrupt" "0,1" newline bitfld.long 0x0 8. "DMA_INTEGRITY_ERROR_INTCLR,ALGORITHM_INTEGRITY interrupt" "0,1" newline bitfld.long 0x0 3. "HASH_DONE_INTCLR,HASH_DONE interrupt" "0,1" newline bitfld.long 0x0 2. "CIPHER_DONE_INTCLR,CIPHER_DONE_INTCLRE" "0,1" newline bitfld.long 0x0 1. "SKC_DONE_INTCLR,KEYgen done interrupt enable" "0,1" newline bitfld.long 0x0 0. "DMA_DONE_INTCLR,DMA_DONE interrupt" "0,1" group.long 0x8000++0x1B line.long 0x0 "SECURE_CTRL,CE secure violation control register" hexmask.long.byte 0x0 24.--31. 1. "CE_SRAM_SIZE_VIO,the CE sram size size is not correct" newline rbitfld.long 0x0 17. "SRAM_SIZE_TOTAL_VIO,the CE sram size total size is not correct" "0,1" newline bitfld.long 0x0 16. "PKE_CM_DISABLE,'1: disable the PKE counter measure 0 : enable the counter measure'" "enable the counter measure',disable the PKE counter measure" newline hexmask.long.byte 0x0 8.--15. 1. "SECURE_VIOLATION_STATUS,'secure violation input status'" newline hexmask.long.byte 0x0 0.--7. 1. "SECURE_VIOLATION_ENABLE,'the corresponding bits enable the secure violation source'" line.long 0x4 "SESRAM_SIZE,Secure SRAM size for CE0~3" newline hexmask.long.byte 0x4 24.--30. 1. "CE3_RAM_SIZE,the secure sram size CE1" newline hexmask.long.byte 0x4 16.--22. 1. "CE2_RAM_SIZE,the secure sram size CE1" newline hexmask.long.byte 0x4 8.--14. 1. "CE1_RAM_SIZE,the secure sram size CE1" newline hexmask.long.byte 0x4 0.--6. 1. "CE0_RAM_SIZE,the secure sram size CE1" line.long 0x8 "SESRAM_SIZE_CONT,secure SRAM size for CE4~7" newline hexmask.long.byte 0x8 24.--30. 1. "CE7_RAM_SIZE,the secure sram size CE1" newline hexmask.long.byte 0x8 16.--22. 1. "CE6_RAM_SIZE,the secure sram size CE1" newline hexmask.long.byte 0x8 8.--14. 1. "CE5_RAM_SIZE,the secure sram size CE1" newline hexmask.long.byte 0x8 0.--6. 1. "CE4_RAM_SIZE,the secure sram size CE1" line.long 0xC "SESRAM_SASIZE,SESRAM secure area size for CE 0~3" newline hexmask.long.byte 0xC 24.--30. 1. "CE3_RAM_SASIZE,the secure sram size CE1" newline hexmask.long.byte 0xC 16.--22. 1. "CE2_RAM_SASIZE,the secure sram size CE1" newline hexmask.long.byte 0xC 8.--14. 1. "CE1_RAM_SASIZE,the secure sram size CE1" newline hexmask.long.byte 0xC 0.--6. 1. "CE0_RAM_SASIZE,the secure sram size CE1" line.long 0x10 "SESRAM_SASIZE_CONT,SESRAM secure area size for CE4~7" newline hexmask.long.byte 0x10 24.--30. 1. "CE7_RAM_SASIZE,the secure sram size CE1" newline hexmask.long.byte 0x10 16.--22. 1. "CE6_RAM_SASIZE,the secure sram size CE1" newline hexmask.long.byte 0x10 8.--14. 1. "CE5_RAM_SASIZE,the secure sram size CE1" newline hexmask.long.byte 0x10 0.--6. 1. "CE4_RAM_SASIZE,the secure sram size CE1" line.long 0x14 "VCE_SINATURE_MASK,VCE_SINATURE_MASK" hexmask.long 0x14 0.--31. 1. "VCE_SINATURE_MASK,'the mask for the vce to generate signature from id'" line.long 0x18 "VCE_SINATURE_MASK_HIGH,VCE_SINATURE_MASK_HIGH" newline hexmask.long.byte 0x18 0.--7. 1. "VCE_SINATURE_MASK_HIGH,'the mask for the vce to generate signature from id high part'" group.long 0x8020++0x7 line.long 0x0 "HRNG_CTRL,HRNG_CTRL" newline hexmask.long.byte 0x0 8.--11. 1. "HRNG_LOAD_CNT,'the counter to control the frequency for the hrng LFSF load the feedback cycle'" newline bitfld.long 0x0 0. "NOISE_ENABLE,'1: enable the noise source for the hrng 0: disable the noise source'" "disable the noise source',enable the noise source for the hrng" line.long 0x4 "HRNG_SEED_CTRL,HRNG_SEED_CTRL" bitfld.long 0x4 31. "LOAD_SEED_GO,'write 1 to this bit will load the seed into the hrng auto clear'" "0,1" newline hexmask.long 0x4 0.--30. 1. "SEED_NUM,'the seed number" group.long 0x8030++0x3 line.long 0x0 "TRNG_CTRL,TRNG_CTRL" newline bitfld.long 0x0 0. "CE_TRNG_SEQ_GO,'write this bit will start the trng sequencer to fetch the random number for all VCEs'" "0,1" group.long 0x8050++0x3 line.long 0x0 "DEBUG_BUS_SEL,DEBUG_BUS_SEL" newline hexmask.long.word 0x0 0.--15. 1. "DEBUG_BUS_SEL,'debug bus select'" rgroup.long 0x8054++0x3 line.long 0x0 "DEBUG_BUS_STATUS,DEBUG_BUS_STATUS" hexmask.long 0x0 0.--31. 1. "DEBUG_BUS_STATUS,'debug bus output'" group.long 0x8100++0x3 line.long 0x0 "TRNG_CONTROL,TRNG_CONTROL" newline bitfld.long 0x0 20. "TRNG_FIFOWRITESTARTUP,'Enable write of the samples in the FIFO during start-up'" "0,1" newline hexmask.long.byte 0x0 16.--19. 1. "TRNG_NB128BITBLOCKS,'Number of 128 bit blocks used in AES-CBCMAC post-processing. This value cannot be zero.'" newline bitfld.long 0x0 15. "TRNG_AIS31TESTSEL,'Select input to the AIS31 test module 0: Before conditioning 1: After conditioning'" "Before conditioning,After conditioning'" newline bitfld.long 0x0 14. "TRNG_HEALTHTESTSEL,'Select input to health test module 0: Before conditioning 1: After conditioning'" "Before conditioning,After conditioning'" newline bitfld.long 0x0 13. "TRNG_AIS31BYPASS,'Bypass AIS31 tests such that the results of the start-up and online tests do not affect the FSM state'" "0,1" newline bitfld.long 0x0 12. "TRNG_HEALTHTESTBYPASS,'Bypass NIST tests such that the results of the start-up and online test do not affect the FSM state'" "0,1" newline bitfld.long 0x0 11. "TRNG_FORCERUN,'Force oscillators to run when FIFO is full'" "0,1" newline bitfld.long 0x0 10. "TRNG_INTENALM,'Interrupt enable for AIS31 noise alarm'" "0,1" newline bitfld.long 0x0 9. "TRNG_INTENPRE,'Interrupt enable for AIS31 preliminary noise alarm'" "0,1" newline bitfld.long 0x0 8. "TRNG_SOFTRESET,'Software reset 0: Normal mode 1: The continuous test" "Normal mode,The continuous test" newline bitfld.long 0x0 7. "TRNG_INTENFULL,'Interrupt enable for FIFO full'" "0,1" newline bitfld.long 0x0 5. "TRNG_INTENPROP,'Interrupt enable for Adaptive Proportion Test failure (1024-sample window)'" "0,1" newline bitfld.long 0x0 4. "TRNG_INTENREP,'Interrupt enable for Repetition Count Test failure'" "0,1" newline bitfld.long 0x0 3. "TRNG_CONDBYPASS,'0: the conditioning function is used (normal mode) 1: the conditioning function is bypassed (to observe entropy source directly).'" "the conditioning function is used,the conditioning function is bypassed" newline bitfld.long 0x0 2. "TRNG_TESTEN,'Select input for conditioning function and continuous tests: 0: Noise source (normal mode) 1: Test data register (test mode)'" "Noise source,Test data register" newline bitfld.long 0x0 1. "TRNG_LFSREN,TRNG_LFSREN" "0,1" newline bitfld.long 0x0 0. "TRNG_ENABLE,'Enable the NDRNG.'" "0,1" rgroup.long 0x8104++0xB line.long 0x0 "TRNG_FIFOLEVEL,TRNG_FIFOLEVEL" hexmask.long 0x0 0.--31. 1. "TRNG_FIFOLEVEL,'Number of 32 bits words of random available in the FIFO. Any write to this register clears the FullInt flag in the Status register.'" line.long 0x4 "TRNG_FIFOTHD,TRNG_FIFOTHD" hexmask.long 0x4 0.--31. 1. "TRNG_FIFOTHD,'FIFO level below which the module leaves the idle state to refill the fifo" line.long 0x8 "TRNG_FIFODEPTH,TRNG_FIFODEPTH" hexmask.long 0x8 0.--31. 1. "TRNG_FIFODEPTH,'Depth Maximum number of 32 bits words that can be stored in the FIFO: 2g_fifodepth.'" group.long 0x8110++0xF line.long 0x0 "TRNG_KEY0REG,TRNG_KEY0REG" hexmask.long 0x0 0.--31. 1. "TRNG_KEY0REG,'Key (MSB)'" line.long 0x4 "TRNG_KEY1REG,TRNG_KEY1REG" hexmask.long 0x4 0.--31. 1. "TRNG_KEY1REG,'Key'" line.long 0x8 "TRNG_KEY2REG,TRNG_KEY2REG" hexmask.long 0x8 0.--31. 1. "TRNG_KEY2REG,'Key'" line.long 0xC "TRNG_KEY3REG,TRNG_KEY3REG" hexmask.long 0xC 0.--31. 1. "TRNG_KEY3REG,'Key (LSB)'" wgroup.long 0x8120++0x3 line.long 0x0 "TRNG_TESTDATA,TRNG_TESTDATA" hexmask.long 0x0 0.--31. 1. "TRNG_TESTDATA,'feed known data to the conditioning function or to the continous tests.'" group.long 0x8124++0x7 line.long 0x0 "TRNG_REPTHRESREG,TRNG_REPTHRESREG" hexmask.long 0x0 0.--31. 1. "TRNG_REPTHRESREG,'Repetition Test Count Cut-Off value'" line.long 0x4 "TRNG_PROPTHRESREG,TRNG_PROPTHRESREG" hexmask.long 0x4 0.--31. 1. "TRNG_PROPTHRESREG,'Adaptive Proportion Test (1024-sample window) Cut-Off value'" group.long 0x8130++0x17 line.long 0x0 "TRNG_STATUS,TRNG_STATUS" newline bitfld.long 0x0 11. "TRNG_FIFOACCFAIL,'Set when a FIFO data read is performed while the NDRNG is disabled AND has its FIFO empty (FIFOLevel = 0)'" "0,1" newline rbitfld.long 0x0 10. "TRNG_STARTUPFAIL,'Start-up test failure'" "0,1" newline rbitfld.long 0x0 9. "TRNG_ALMINT,'AIS31 noise alarm interrupt status'" "0,1" newline bitfld.long 0x0 8. "TRNG_PREINT,'AIS31 preliminary noise alarm interrupt status'" "0,1" newline bitfld.long 0x0 7. "TRNG_FULLINT,'FIFO full status'" "0,1" newline bitfld.long 0x0 5. "TRNG_PROPFAIL,'NIST-800-90B adaptive Proportion Test (1024-sample window) interrupt status'" "0,1" newline bitfld.long 0x0 4. "TRNG_REPFAIL,'NIST-800-90B repetition Count Test interrupt status'" "0,1" newline rbitfld.long 0x0 1.--3. "TRNG_STATE,'State of the control FSM (see Figure 7-1) 000: Reset 001: Startup 010: Idle (Rings On) 011: Idle (Rings Off) 100: Fill FIFO 101: Error 110: Unused 111: Unused'" "Reset,Startup,?,?,?,?,?,?" newline rbitfld.long 0x0 0. "TRNG_TESTDATABUSY,'High when data written to TestData register is being processed. (see section 4.7)'" "0,1" line.long 0x4 "TRNG_INITWAITVAL,TRNG_INITWAITVAL" newline hexmask.long.word 0x4 0.--15. 1. "TRNG_INITWAITVAL,'Number of clock cycles to wait before sampling data from the noise source. All 16 bits are reset high (reset value = 0xFFFF).'" line.long 0x8 "TRNG_DISABLEOSC,TRNG_DISABLEOSC" hexmask.long 0x8 0.--31. 1. "TRNG_DISABLEOS0,'Disable oscillator rings #0 to #31'" line.long 0xC "TRNG_DISABLEOSC1,TRNG_DISABLEOSC1" hexmask.long 0xC 0.--31. 1. "TRNG_DISABLEOS1,'Disable oscillator rings #32 to #63'" line.long 0x10 "TRNG_SWOFFTMRVAL,TRNG_SWOFFTMRVAL" newline hexmask.long.word 0x10 0.--15. 1. "TRNG_SWOFFTMRVAL,'Number of clk cycles to wait before stopping the rings after the FIFO is full. '" line.long 0x14 "TRNG_CLKDIV,TRNG_CLKDIV" newline hexmask.long.byte 0x14 0.--7. 1. "TRNG_CLKDIV,'Sample clock divider. The frequency at which the outputs of the rings are sampled is given by Fs = Fpclk/(ClkDiv + 1).'" repeat 3. (list 0x0 0x1 0x2 )(list 0x0 0x4 0x8 ) group.long ($2+0x8148)++0x3 line.long 0x0 "TRNG_AIS31CONF$1,TRNG_AIS31CONF0" hexmask.long.word 0x0 16.--31. 1. "TRNG_ONLINETHRESH,'Online threshold'" newline hexmask.long.word 0x0 0.--15. 1. "TRNG_STARTUPTHRESH,'Start-up test threshold'" repeat.end group.long 0x8154++0x3 line.long 0x0 "TRNG_AIS31STATUS,TRNG_AIS31STATUS" newline rbitfld.long 0x0 17. "TRNG_PRELIMNOISEALARMREP,TRNG_PRELIMNOISEALARMREP" "0,1" newline rbitfld.long 0x0 16. "TRNG_PRELIMNOISEALARMRNG,'Last preliminary noise alarm occurred due to history value out of range'" "0,1" newline hexmask.long.word 0x0 0.--15. 1. "TRNG_NUMPRELIMALARMS,'Number of preliminary noise alarms since counter was last cleared'" rgroup.long 0x8158++0x3 line.long 0x0 "TRNG_HWCONF,TRNG_HWCONF" newline bitfld.long 0x0 9. "TRNG_AIS31FULL,'Generic g_AIS31Full value'" "0,1" newline bitfld.long 0x0 8. "TRNG_AIS31,'Generic g_AIS31 value'" "0,1" newline hexmask.long.byte 0x0 0.--7. 1. "TRNG_NUMBOFRINGS,'Generic g_NumRings value'" tree.end endif tree.end tree "CKGEN (Clock Generation)" sif (CORENAME()=="CORTEXR5F") tree "CKGEN_XPU" base ad:0xF6000000 repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) group.long ($2)++0x3 line.long 0x0 "CKGEN_IP_SLICE_CTL_$1,ip slice control reg" rbitfld.long 0x0 31. "POST_BUSY,ck gen ip slice post_div busy status. indicate post divider update status. 1: post divider update on progress. 0: post divider update done." "post divider update done,post divider update on progress" rbitfld.long 0x0 30. "PRE_BUSY,ck gen ip slice pre_div busy status. indicate pre divider update status. 1: pre divider update on progress. 0: pre divider update done." "pre divider update done,pre divider update on progress" newline bitfld.long 0x0 28. "CG_EN_STATUS,clock gating enable status indicate CG_EN change doen since CG_EN is asynchronous to ip slice this bit indicate the CG_EN is received(active) in ip slice. when you change CG_EN you need to read this bit after that to make sure CG_EN is.." "0,1" newline hexmask.long.byte 0x0 10.--15. 1. "POST_DIV_NUM,post_div num. like PRE_DIV_NUM this field can be updated on-the-fly. and ip slice frequency will be selected clock source frequency/(PRE_DIV_NUM+1)/(POST_DIV_NUM+1)" newline bitfld.long 0x0 4.--6. "PRE_DIV_NUM,pre_div_num. each ip slice have 2 dividers pre_divider and post_divider. this field can be updated on-the-fly. ip slice frequency will be selected clock source frequency/(PRE_DIV_NUM+1)/(POST_DIV_NUM+1)" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 1.--3. "CLK_SRC_SEL,clock source select. each ip slice has 8 clock source(from clock source 0 to clock source 7) clock source information are in clock table. 0: clock source 0 1: clock source 1 .... 7: clock source 7" "clock source 0,clock source 1,?,?,?,?,?,clock source 7" bitfld.long 0x0 0. "CG_EN,clock gating enable. control the gating cell after ip slice 8-1 clock mux. 1: clock not gated. 0: clock gated. clock need to be gated before changing clock source. eg. if you want to change clock source from source 0 to source 1 you need to follow.." "clock gated,clock not gated" repeat.end repeat 2. (list 0x0 0x1 )(list 0x0 0x8 ) group.long ($2+0x200)++0x3 line.long 0x0 "CKGEN_BUS_SLICE_CTL_$1,bus slice control reg" rbitfld.long 0x0 31. "POST_BUSY,ck gen bus slice post_div busy status. indicate post divider update status. 1: post divider update on progress. 0: post divider update done." "post divider update done,post divider update on progress" rbitfld.long 0x0 30. "PRE_BUSY_A,ck gen bus slice pre_div_a busy status. indicate pre divider a update status. 1: pre divider a update on progress. 0: pre divider a update done." "pre divider a update done,pre divider a update on progress" newline rbitfld.long 0x0 29. "PRE_BUSY_B,ck gen bus slice pre_div_b busy. indicate pre divider b update status. 1: pre divider b update on progress. 0: pre divider b update done." "pre divider b update done,pre divider b update on progress" bitfld.long 0x0 28. "CG_EN_A_STATUS,clock gating enable a status indicate CG_EN_A change doen. since CG_EN_A is asynchronous to bus slice this bit indicate the CG_EN_A is received(active) in bus slice. when you change CG_EN_A you need to read this bit after that to make.." "0,1" newline bitfld.long 0x0 27. "CG_EN_B_STATUS,clock gating enable b status indicate CG_EN_B change doen. since CG_EN_B is asynchronous to bus slice this bit indicate the CG_EN_B is received(active) in bus slice. when you change CG_EN_B you need to read this bit after that to make.." "0,1" newline bitfld.long 0x0 20.--22. "PRE_DIV_NUM_B,pre_div_b num. each bus slice have 3 dividers pre_divider_a pre_divider_b and post_divider. this field can be updated on-the-fly. bus slice frequency will be selected clock source frequency/(PRE_DIV_NUM+1)/(POST_DIV_NUM+1). in which.." "0,1,2,3,4,5,6,7" bitfld.long 0x0 17.--19. "CLK_SRC_SEL_B,path b clock source select. each path in bus slice has 8 clock source(from clock source 0 to clock source 7 and path a and path b clock sources are totally the same) clock source information are in clock table. 0: clock source 0 1: clock.." "clock source 0,clock source 1,?,?,?,?,?,clock source 7" newline bitfld.long 0x0 16. "CG_EN_B,path b clock gating enable. control the gating cell after bus slice path b 8-1 clock mux. 1: clock not gated. 0: clock gated. clock need to be gated before changing clock source. eg. if you want to change clock source from source 0 to source 1.." "clock gated,clock not gated" hexmask.long.byte 0x0 10.--15. 1. "POST_DIV_NUM,post_div num. each bus slice have 3 dividers pre_divider_a pre_divider_b and post_divider. this field can be updated on-the-fly. bus slice frequency will be selected clock source frequency/(PRE_DIV_NUM+1)/(POST_DIV_NUM+1). in which.." newline bitfld.long 0x0 9. "A_B_SEL,select between path a and path b clock source. 0: path a is selected. 1: path b is selected. this can be changed on-the-fly. please make sure both path a frequency and path b frequency are within spec." "path a is selected,path b is selected" newline bitfld.long 0x0 4.--6. "PRE_DIV_NUM_A,pre_div_a num. each bus slice have 3 dividers pre_divider_a pre_divider_b and post_divider. this field can be updated on-the-fly. bus slice frequency will be selected clock source frequency/(PRE_DIV_NUM+1)/(POST_DIV_NUM+1). in which.." "0,1,2,3,4,5,6,7" bitfld.long 0x0 1.--3. "CLK_SRC_SEL_A,path a clock source select. each path in bus slice has 8 clock source(from clock source 0 to clock source 7 and path a and path b clock sources are totally the same) clock source information are in clock table. 0: clock source 0 1: clock.." "clock source 0,clock source 1,?,?,?,?,?,clock source 7" newline bitfld.long 0x0 0. "CG_EN_A,path a clock gating enable. control the gating cell after bus slice path a 8-1 clock mux. 1: clock not gated. 0: clock gated. clock need to be gated before changing clock source. eg. if you want to change clock source from source 0 to source 1.." "clock gated,clock not gated" repeat.end repeat 2. (list 0x0 0x1 )(list 0x0 0x8 ) group.long ($2+0x204)++0x3 line.long 0x0 "CKGEN_BUS_SLICE_GASKET_$1,bus slice gasket control" rbitfld.long 0x0 31. "DIV_M_BUSY,clock/m divider busy status. indicate clock/m divider update status. 1: clock/m divider update on progress. 0: clock/m divider update done." "clock/m divider update done,clock/m divider update on progress" rbitfld.long 0x0 30. "DIV_N_BUSY,clock/n divider busy status. indicate clock/n divider update status. 1: clock/n divider update on progress. 0: clock/n divider update done." "clock/n divider update done,clock/n divider update on progress" newline rbitfld.long 0x0 29. "DIV_P_BUSY,clock/p divider busy status. indicate clock/p divider update status. 1: clock/p divider update on progress. 0: clock/p divider update done." "clock/p divider update done,clock/p divider update on progress" rbitfld.long 0x0 28. "DIV_Q_BUSY,clock/q divider busy status. indicate clock/q divider update status. 1: clock/q divider update on progress. 0: clock/q divider update done." "clock/q divider update done,clock/q divider update on progress" newline bitfld.long 0x0 9.--11. "M_DIV_NUM,divider number for clock/m. this field can be updated on-the-fly. and bus slice gasket m frequency will be the corresponding bus clock frequency/(M_DIV_NUM+1)" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 6.--8. "N_DIV_NUM,divider number for clock/n this field can be updated on-the-fly. and bus slice gasket m frequency will be the corresponding bus clock frequency/(N_DIV_NUM+1)" "0,1,2,3,4,5,6,7" bitfld.long 0x0 3.--5. "P_DIV_NUM,divider number for clock/p this field can be updated on-the-fly. and bus slice gasket m frequency will be the corresponding bus clock frequency/(P_DIV_NUM+1)" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 0.--2. "Q_DIV_NUM,divider number for clock/q this field can be updated on-the-fly. and bus slice gasket m frequency will be the corresponding bus clock frequency/(Q_DIV_NUM+1)" "0,1,2,3,4,5,6,7" repeat.end repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) group.long ($2+0x300)++0x3 line.long 0x0 "CKGEN_CORE_SLICE_CTL_$1,core slice control reg" rbitfld.long 0x0 31. "POST_BUSY,ckgen core slice post_div busy status. indicate post divider update status. 1: post divider update on progress. 0: post divider update done." "post divider update done,post divider update on progress" newline bitfld.long 0x0 28. "CG_EN_A_STATUS,clock gating enable a status indicate CG_EN_A change done. since CG_EN_A is asynchronous to core slice this bit indicate the CG_EN_A is received(active) in core slice. when you change CG_EN_A you need to read this bit after that to make.." "0,1" bitfld.long 0x0 27. "CG_EN_B_STATUS,clock gating enable b status indicate CG_EN_B change doen. since CG_EN_B is asynchronous to core slice this bit indicate the CG_EN_B is received(active) in core slice. when you change CG_EN_B you need to read this bit after that to make.." "0,1" newline bitfld.long 0x0 17.--19. "CLK_SRC_SEL_B,path b clock source select. each path in bus slice has 8 clock source(from clock source 0 to clock source 7 and path a and path b clock sources are totally the same) clock source information are in clock table. 0: clock source 0 1: clock.." "clock source 0,clock source 1,?,?,?,?,?,clock source 7" newline bitfld.long 0x0 16. "CG_EN_B,path b clock gating enable. control the gating cell after core slice path b 8-1 clock mux. 1: clock not gated. 0: clock gated. clock need to be gated before changing clock source. eg. if you want to change clock source from source 0 to source 1.." "clock gated,clock not gated" hexmask.long.byte 0x0 10.--15. 1. "POST_DIV_NUM,post_div num. this field can be updated on-the-fly. core slice frequency will be selected clock source frequency/(POST_DIV_NUM+1)." newline bitfld.long 0x0 9. "A_B_SEL,select between path a and path b clock source. 0: path a is selected. 1: path b is selected. this can be changed on-the-fly. please make sure both path a frequency and path b frequency are within spec." "path a is selected,path b is selected" newline bitfld.long 0x0 1.--3. "CLK_SRC_SEL_A,path a clock source select. each path in core slice has 8 clock source(from clock source 0 to clock source 7 and path a and path b clock sources are totally the same) clock source information are in clock table. 0: clock source 0 1: clock.." "clock source 0,clock source 1,?,?,?,?,?,clock source 7" bitfld.long 0x0 0. "CG_EN_A,path a clock gating enable. control the gating cell after core slice path a 8-1 clock mux. 1: clock not gated. 0: clock gated. clock need to be gated before changing clock source. eg. if you want to change clock source from source 0 to source 1.." "clock gated,clock not gated" repeat.end repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) group.long ($2+0x400)++0x3 line.long 0x0 "CKGEN_LP_GATING_EN_$1,ip slice sw gating enable" bitfld.long 0x0 31. "CKGEN_GATING_LOCK,LOCK SW_GATING_EN/DIS 1: locked. SW_GATING_DIS/EN will keep what they are 0: unlocked SW_GATING_DIS/EN can be changed" "unlocked,locked" newline bitfld.long 0x0 1. "SW_GATING_DIS,ckgen software gating disable has higher priority than sw_gating_en. if this bit is 1'b1 then the controlled clock will be forced on(ignore the SW_GATING_EN." "0,1" bitfld.long 0x0 0. "SW_GATING_EN,ckgen software gating enable. control the gating cell IP clock in most IPs have different gating cells you can refer to clock gating control table. 1: clock not gated. 0: clock gated." "clock gated,clock not gated" repeat.end group.long 0x600++0x3 line.long 0x0 "CKGEN_UUU_SLICE_0,uuu clock wrapper control" bitfld.long 0x0 31. "UUU_DBG_GATING_EN,gating enable for debug output. control the gating cell before uuu dbg divider 1: clock not gated. 0: clock gated." "clock gated,clock not gated" hexmask.long.byte 0x0 27.--30. 1. "DBG_DIV_NUM,divder number for debug output. this field can be updated on-the-fly. dbg clock frequence will be selected clk_out_0/(DBG_DIV_NUM+1)" newline bitfld.long 0x0 20. "UUU_GATING_ACK,reserved" "0,1" newline hexmask.long.byte 0x0 16.--19. 1. "UUU_SEL,for uuu wrapper clock gating control and clock source select uuu_sel[1:0]: clk_sel in uuu_clock_wrapper uuu_sel[1]: 1: clk_out_0 from pll 0: clk_out_0 from clk_m uuu_sel_[0]: 1: uuu input clock from pll 2: uuu input clock from ckgen_hpi slice.." hexmask.long.byte 0x0 12.--15. 1. "M_DIV_NUM,divider number for clock/m. this field can be updated on-the-fly. and uuu clock m frequency will be the corresponding uuu clock frequency/(M_DIV_NUM+1)" newline hexmask.long.byte 0x0 8.--11. 1. "N_DIV_NUM,divider number for clock/n. this field can be updated on-the-fly. and uuu clock m frequency will be the corresponding uuu clock frequency/(N_DIV_NUM+1)" hexmask.long.byte 0x0 4.--7. 1. "P_DIV_NUM,divider number for clock/p this field can be updated on-the-fly. and uuu clock m frequency will be the corresponding uuu clock frequency/(P_DIV_NUM+1)" newline hexmask.long.byte 0x0 0.--3. 1. "Q_DIV_NUM,divider number for clock/q this field can be updated on-the-fly. and uuu clock m frequency will be the corresponding uuu clock frequency/(Q_DIV_NUM+1)" group.long 0x700++0xF line.long 0x0 "CKGEN_IP_SLICE_DBG_CTL,ip slice debug control" hexmask.long.word 0x0 0.--15. 1. "IP_SLICE_DBG_SEL,ip slice debug clock source select. for ckgen_saf/ckgen_sec/ckgen_disp when ip clock is selected to be the debug source. this register choose debug clock source from ip_slice[0] to ip_slice[IP_SLICE_NUM] for ckgen_hpi from.." line.long 0x4 "CKGEN_BUS_SLICE_DBG_CTL,bus slice debug control" hexmask.long.word 0x4 0.--15. 1. "BUS_SLICE_DBG_SEL,bus slice debug clock source select. when bus clock is selected to be the debug source. this register choose debug clock source from bus_slice[0] to bus_slice[BUS_SLICE_NUM]" line.long 0x8 "CKGEN_CORE_SLICE_DBG_CTL,core slice debug control" hexmask.long.word 0x8 0.--15. 1. "CORE_SLICE_DBG_SEL,core slice debug clock source select. when core clock is selected to be the debug source. this register choose debug clock source from core_slice[0] to core_slice[CORE_SLICE_NUM]" line.long 0xC "CKGEN_DBG_CTL,ckgen debug control" bitfld.long 0xC 31. "DBG_CLK_DIS,disable ckgen debug function. 0: ckgen debug function enable 1: ckgen debug function disable" "ckgen debug function enable,ckgen debug function disable" bitfld.long 0xC 29.--30. "DBG_SEL,dbg clock out select: 2'b01: from bus slice clock which is controlled by CKGEN_BUS_SLICE_DBG_CTL 2'b10: from core slice clock which is controlled by CKGEN_CORE_SLICE_DBG_CTL others: from ip slice clock which is controlled by.." "?,from bus slice clock,from core slice clock,?" newline hexmask.long.word 0xC 0.--15. 1. "DBG_DIV_NUM,debug divider number only bit[3:0] are used since debug clock is monitored through pad only clock frequency less than 100MHz can be accepted. and divide the debug clock as early as possible from clock source." group.long 0x720++0x1B line.long 0x0 "CKGEN_IP_SLICE_MON_CTL,ip slice monitor control" hexmask.long.word 0x0 0.--15. 1. "IP_SLICE_MON_SEL,ip slice mon clock source select. for ckgen_saf/ckgen_sec/ckgen_disp when ip clock is selected to be the monitor source. this register choose monitor clock source from ip_slice[0] to ip_slice[IP_SLICE_NUM] for ckgen_hpi from.." line.long 0x4 "CKGEN_BUS_SLICE_MON_CTL,bus slice monitor control" hexmask.long.word 0x4 0.--15. 1. "BUS_SLICE_MON_SEL,bus slice mon clock source select. when bus clock is selected to be the monitor source. this register choose monitor clock source from bus_slice[0] to bus_slice[BUS_SLICE_NUM]" line.long 0x8 "CKGEN_CORE_SLICE_MON_CTL,core slice monitor control" hexmask.long.word 0x8 0.--15. 1. "CORE_SLICE_MON_SEL,core slice monitor clock source select. when core clock is selected to be the monitor source. this register choose monitor clock source from core_slice[0] to core_slice[CORE_SLICE_NUM]" line.long 0xC "CKGEN_MON_CTL,ckgen monitor control" bitfld.long 0xC 31. "MON_CLK_DIS,disable ckgen monitor function. 0: ckgen monitor function enable 1: ckgen monitor function disable" "ckgen monitor function enable,ckgen monitor function disable" bitfld.long 0xC 29.--30. "MON_SEL,monitor clock out select: 2'b01: from bus slice clock which is controlled by CKGEN_BUS_SLICE_MON_CTL 2'b10: from core slice clock which is controlled by CKGEN_CORE_SLICE_MON_CTL others: from ip slice clock which is controlled by.." "?,from bus slice clock,from core slice clock,?" newline bitfld.long 0xC 28. "MON_VAL_UPD_EN,latch monitor value enable 1: latch 0: latch disable" "latch disable,latch" rbitfld.long 0xC 27. "FREQ_RDY_STA,frequency calculate ready indicator." "0,1" newline rbitfld.long 0xC 26. "MON_CLK_DIS_STA,mon_clk_dis status. need to check after program mon_clk_dis" "0,1" bitfld.long 0xC 25. "CLK_SLOW_SRC,clk slow source select. this is the referenc clock source for clock monitor. 1: 32k 0: 24M" "0,1" newline rbitfld.long 0xC 16. "MON_DIV_BUSY,monitor divider update busy. indicate monitor divider update status. 1: monitor divider update on progress. 0: monitor divider update done." "monitor divider update done,monitor divider update on progress" newline hexmask.long.word 0xC 0.--15. 1. "MON_DIV_NUM,monitor divider number only bit[3:0] are used this field can be changed on-the-fly." line.long 0x10 "CKGEN_MON_MAX_FREQ,clock monitor max freq value" hexmask.long.word 0x10 0.--15. 1. "MON_MAX_FREQ,monitor clock max freq value. monitored max freq. this is only for debug" line.long 0x14 "CKGEN_MON_AVE_FREQ,clock monitor average freq value" hexmask.long.word 0x14 0.--15. 1. "MON_AVE_FREQ,monitor clock average freq value. the monitored clock frequency should be MON_AVE_FREQ * CLK_SLOW_SRC" line.long 0x18 "CKGEN_MON_MIN_FREQ,clock monitor min freq value" hexmask.long.word 0x18 0.--15. 1. "MON_MIN_FREQ,monitor clock mininum freq value. monitored min freq. this is only for debug" rgroup.long 0x73C++0x7 line.long 0x0 "CKGEN_MON_MAX_DUTY,clock monitor max high duty value" hexmask.long.word 0x0 16.--31. 1. "MON_MAX_PERIOD,monitor clock max period corresponding to the max high level value" hexmask.long.word 0x0 0.--15. 1. "MON_MAX_HIGH,monitor clock max high level value" line.long 0x4 "CKGEN_MON_MIN_DUTY,clock monitor min duty value" hexmask.long.word 0x4 16.--31. 1. "MON_MIN_PERIOD,monitor clock min period corresponding to the min high level value" hexmask.long.word 0x4 0.--15. 1. "MON_MIN_HIGH,monitor clock min high level value" tree.end tree "CKGEN_DISP" base ad:0xF6200000 repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) group.long ($2)++0x3 line.long 0x0 "CKGEN_IP_SLICE_CTL_$1,ip slice control reg" rbitfld.long 0x0 31. "POST_BUSY,ck gen ip slice post_div busy status. indicate post divider update status. 1: post divider update on progress. 0: post divider update done." "post divider update done,post divider update on progress" rbitfld.long 0x0 30. "PRE_BUSY,ck gen ip slice pre_div busy status. indicate pre divider update status. 1: pre divider update on progress. 0: pre divider update done." "pre divider update done,pre divider update on progress" newline bitfld.long 0x0 28. "CG_EN_STATUS,clock gating enable status indicate CG_EN change doen since CG_EN is asynchronous to ip slice this bit indicate the CG_EN is received(active) in ip slice. when you change CG_EN you need to read this bit after that to make sure CG_EN is.." "0,1" newline hexmask.long.byte 0x0 10.--15. 1. "POST_DIV_NUM,post_div num. like PRE_DIV_NUM this field can be updated on-the-fly. and ip slice frequency will be selected clock source frequency/(PRE_DIV_NUM+1)/(POST_DIV_NUM+1)" newline bitfld.long 0x0 4.--6. "PRE_DIV_NUM,pre_div_num. each ip slice have 2 dividers pre_divider and post_divider. this field can be updated on-the-fly. ip slice frequency will be selected clock source frequency/(PRE_DIV_NUM+1)/(POST_DIV_NUM+1)" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 1.--3. "CLK_SRC_SEL,clock source select. each ip slice has 8 clock source(from clock source 0 to clock source 7) clock source information are in clock table. 0: clock source 0 1: clock source 1 .... 7: clock source 7" "clock source 0,clock source 1,?,?,?,?,?,clock source 7" bitfld.long 0x0 0. "CG_EN,clock gating enable. control the gating cell after ip slice 8-1 clock mux. 1: clock not gated. 0: clock gated. clock need to be gated before changing clock source. eg. if you want to change clock source from source 0 to source 1 you need to follow.." "clock gated,clock not gated" repeat.end repeat 2. (list 0x0 0x1 )(list 0x0 0x8 ) group.long ($2+0x200)++0x3 line.long 0x0 "CKGEN_BUS_SLICE_CTL_$1,bus slice control reg" rbitfld.long 0x0 31. "POST_BUSY,ck gen bus slice post_div busy status. indicate post divider update status. 1: post divider update on progress. 0: post divider update done." "post divider update done,post divider update on progress" rbitfld.long 0x0 30. "PRE_BUSY_A,ck gen bus slice pre_div_a busy status. indicate pre divider a update status. 1: pre divider a update on progress. 0: pre divider a update done." "pre divider a update done,pre divider a update on progress" newline rbitfld.long 0x0 29. "PRE_BUSY_B,ck gen bus slice pre_div_b busy. indicate pre divider b update status. 1: pre divider b update on progress. 0: pre divider b update done." "pre divider b update done,pre divider b update on progress" bitfld.long 0x0 28. "CG_EN_A_STATUS,clock gating enable a status indicate CG_EN_A change doen. since CG_EN_A is asynchronous to bus slice this bit indicate the CG_EN_A is received(active) in bus slice. when you change CG_EN_A you need to read this bit after that to make.." "0,1" newline bitfld.long 0x0 27. "CG_EN_B_STATUS,clock gating enable b status indicate CG_EN_B change doen. since CG_EN_B is asynchronous to bus slice this bit indicate the CG_EN_B is received(active) in bus slice. when you change CG_EN_B you need to read this bit after that to make.." "0,1" newline bitfld.long 0x0 20.--22. "PRE_DIV_NUM_B,pre_div_b num. each bus slice have 3 dividers pre_divider_a pre_divider_b and post_divider. this field can be updated on-the-fly. bus slice frequency will be selected clock source frequency/(PRE_DIV_NUM+1)/(POST_DIV_NUM+1). in which.." "0,1,2,3,4,5,6,7" bitfld.long 0x0 17.--19. "CLK_SRC_SEL_B,path b clock source select. each path in bus slice has 8 clock source(from clock source 0 to clock source 7 and path a and path b clock sources are totally the same) clock source information are in clock table. 0: clock source 0 1: clock.." "clock source 0,clock source 1,?,?,?,?,?,clock source 7" newline bitfld.long 0x0 16. "CG_EN_B,path b clock gating enable. control the gating cell after bus slice path b 8-1 clock mux. 1: clock not gated. 0: clock gated. clock need to be gated before changing clock source. eg. if you want to change clock source from source 0 to source 1.." "clock gated,clock not gated" hexmask.long.byte 0x0 10.--15. 1. "POST_DIV_NUM,post_div num. each bus slice have 3 dividers pre_divider_a pre_divider_b and post_divider. this field can be updated on-the-fly. bus slice frequency will be selected clock source frequency/(PRE_DIV_NUM+1)/(POST_DIV_NUM+1). in which.." newline bitfld.long 0x0 9. "A_B_SEL,select between path a and path b clock source. 0: path a is selected. 1: path b is selected. this can be changed on-the-fly. please make sure both path a frequency and path b frequency are within spec." "path a is selected,path b is selected" newline bitfld.long 0x0 4.--6. "PRE_DIV_NUM_A,pre_div_a num. each bus slice have 3 dividers pre_divider_a pre_divider_b and post_divider. this field can be updated on-the-fly. bus slice frequency will be selected clock source frequency/(PRE_DIV_NUM+1)/(POST_DIV_NUM+1). in which.." "0,1,2,3,4,5,6,7" bitfld.long 0x0 1.--3. "CLK_SRC_SEL_A,path a clock source select. each path in bus slice has 8 clock source(from clock source 0 to clock source 7 and path a and path b clock sources are totally the same) clock source information are in clock table. 0: clock source 0 1: clock.." "clock source 0,clock source 1,?,?,?,?,?,clock source 7" newline bitfld.long 0x0 0. "CG_EN_A,path a clock gating enable. control the gating cell after bus slice path a 8-1 clock mux. 1: clock not gated. 0: clock gated. clock need to be gated before changing clock source. eg. if you want to change clock source from source 0 to source 1.." "clock gated,clock not gated" repeat.end repeat 2. (list 0x0 0x1 )(list 0x0 0x8 ) group.long ($2+0x204)++0x3 line.long 0x0 "CKGEN_BUS_SLICE_GASKET_$1,bus slice gasket control" rbitfld.long 0x0 31. "DIV_M_BUSY,clock/m divider busy status. indicate clock/m divider update status. 1: clock/m divider update on progress. 0: clock/m divider update done." "clock/m divider update done,clock/m divider update on progress" rbitfld.long 0x0 30. "DIV_N_BUSY,clock/n divider busy status. indicate clock/n divider update status. 1: clock/n divider update on progress. 0: clock/n divider update done." "clock/n divider update done,clock/n divider update on progress" newline rbitfld.long 0x0 29. "DIV_P_BUSY,clock/p divider busy status. indicate clock/p divider update status. 1: clock/p divider update on progress. 0: clock/p divider update done." "clock/p divider update done,clock/p divider update on progress" rbitfld.long 0x0 28. "DIV_Q_BUSY,clock/q divider busy status. indicate clock/q divider update status. 1: clock/q divider update on progress. 0: clock/q divider update done." "clock/q divider update done,clock/q divider update on progress" newline bitfld.long 0x0 9.--11. "M_DIV_NUM,divider number for clock/m. this field can be updated on-the-fly. and bus slice gasket m frequency will be the corresponding bus clock frequency/(M_DIV_NUM+1)" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 6.--8. "N_DIV_NUM,divider number for clock/n this field can be updated on-the-fly. and bus slice gasket m frequency will be the corresponding bus clock frequency/(N_DIV_NUM+1)" "0,1,2,3,4,5,6,7" bitfld.long 0x0 3.--5. "P_DIV_NUM,divider number for clock/p this field can be updated on-the-fly. and bus slice gasket m frequency will be the corresponding bus clock frequency/(P_DIV_NUM+1)" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 0.--2. "Q_DIV_NUM,divider number for clock/q this field can be updated on-the-fly. and bus slice gasket m frequency will be the corresponding bus clock frequency/(Q_DIV_NUM+1)" "0,1,2,3,4,5,6,7" repeat.end repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) group.long ($2+0x300)++0x3 line.long 0x0 "CKGEN_CORE_SLICE_CTL_$1,core slice control reg" rbitfld.long 0x0 31. "POST_BUSY,ckgen core slice post_div busy status. indicate post divider update status. 1: post divider update on progress. 0: post divider update done." "post divider update done,post divider update on progress" newline bitfld.long 0x0 28. "CG_EN_A_STATUS,clock gating enable a status indicate CG_EN_A change done. since CG_EN_A is asynchronous to core slice this bit indicate the CG_EN_A is received(active) in core slice. when you change CG_EN_A you need to read this bit after that to make.." "0,1" bitfld.long 0x0 27. "CG_EN_B_STATUS,clock gating enable b status indicate CG_EN_B change doen. since CG_EN_B is asynchronous to core slice this bit indicate the CG_EN_B is received(active) in core slice. when you change CG_EN_B you need to read this bit after that to make.." "0,1" newline bitfld.long 0x0 17.--19. "CLK_SRC_SEL_B,path b clock source select. each path in bus slice has 8 clock source(from clock source 0 to clock source 7 and path a and path b clock sources are totally the same) clock source information are in clock table. 0: clock source 0 1: clock.." "clock source 0,clock source 1,?,?,?,?,?,clock source 7" newline bitfld.long 0x0 16. "CG_EN_B,path b clock gating enable. control the gating cell after core slice path b 8-1 clock mux. 1: clock not gated. 0: clock gated. clock need to be gated before changing clock source. eg. if you want to change clock source from source 0 to source 1.." "clock gated,clock not gated" hexmask.long.byte 0x0 10.--15. 1. "POST_DIV_NUM,post_div num. this field can be updated on-the-fly. core slice frequency will be selected clock source frequency/(POST_DIV_NUM+1)." newline bitfld.long 0x0 9. "A_B_SEL,select between path a and path b clock source. 0: path a is selected. 1: path b is selected. this can be changed on-the-fly. please make sure both path a frequency and path b frequency are within spec." "path a is selected,path b is selected" newline bitfld.long 0x0 1.--3. "CLK_SRC_SEL_A,path a clock source select. each path in core slice has 8 clock source(from clock source 0 to clock source 7 and path a and path b clock sources are totally the same) clock source information are in clock table. 0: clock source 0 1: clock.." "clock source 0,clock source 1,?,?,?,?,?,clock source 7" bitfld.long 0x0 0. "CG_EN_A,path a clock gating enable. control the gating cell after core slice path a 8-1 clock mux. 1: clock not gated. 0: clock gated. clock need to be gated before changing clock source. eg. if you want to change clock source from source 0 to source 1.." "clock gated,clock not gated" repeat.end repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) group.long ($2+0x400)++0x3 line.long 0x0 "CKGEN_LP_GATING_EN_$1,ip slice sw gating enable" bitfld.long 0x0 31. "CKGEN_GATING_LOCK,LOCK SW_GATING_EN/DIS 1: locked. SW_GATING_DIS/EN will keep what they are 0: unlocked SW_GATING_DIS/EN can be changed" "unlocked,locked" newline bitfld.long 0x0 1. "SW_GATING_DIS,ckgen software gating disable has higher priority than sw_gating_en. if this bit is 1'b1 then the controlled clock will be forced on(ignore the SW_GATING_EN." "0,1" bitfld.long 0x0 0. "SW_GATING_EN,ckgen software gating enable. control the gating cell IP clock in most IPs have different gating cells you can refer to clock gating control table. 1: clock not gated. 0: clock gated." "clock gated,clock not gated" repeat.end group.long 0x600++0x3 line.long 0x0 "CKGEN_UUU_SLICE_0,uuu clock wrapper control" bitfld.long 0x0 31. "UUU_DBG_GATING_EN,gating enable for debug output. control the gating cell before uuu dbg divider 1: clock not gated. 0: clock gated." "clock gated,clock not gated" hexmask.long.byte 0x0 27.--30. 1. "DBG_DIV_NUM,divder number for debug output. this field can be updated on-the-fly. dbg clock frequence will be selected clk_out_0/(DBG_DIV_NUM+1)" newline bitfld.long 0x0 20. "UUU_GATING_ACK,reserved" "0,1" newline hexmask.long.byte 0x0 16.--19. 1. "UUU_SEL,for uuu wrapper clock gating control and clock source select uuu_sel[1:0]: clk_sel in uuu_clock_wrapper uuu_sel[1]: 1: clk_out_0 from pll 0: clk_out_0 from clk_m uuu_sel_[0]: 1: uuu input clock from pll 2: uuu input clock from ckgen_hpi slice.." hexmask.long.byte 0x0 12.--15. 1. "M_DIV_NUM,divider number for clock/m. this field can be updated on-the-fly. and uuu clock m frequency will be the corresponding uuu clock frequency/(M_DIV_NUM+1)" newline hexmask.long.byte 0x0 8.--11. 1. "N_DIV_NUM,divider number for clock/n. this field can be updated on-the-fly. and uuu clock m frequency will be the corresponding uuu clock frequency/(N_DIV_NUM+1)" hexmask.long.byte 0x0 4.--7. 1. "P_DIV_NUM,divider number for clock/p this field can be updated on-the-fly. and uuu clock m frequency will be the corresponding uuu clock frequency/(P_DIV_NUM+1)" newline hexmask.long.byte 0x0 0.--3. 1. "Q_DIV_NUM,divider number for clock/q this field can be updated on-the-fly. and uuu clock m frequency will be the corresponding uuu clock frequency/(Q_DIV_NUM+1)" group.long 0x700++0xF line.long 0x0 "CKGEN_IP_SLICE_DBG_CTL,ip slice debug control" hexmask.long.word 0x0 0.--15. 1. "IP_SLICE_DBG_SEL,ip slice debug clock source select. for ckgen_saf/ckgen_sec/ckgen_disp when ip clock is selected to be the debug source. this register choose debug clock source from ip_slice[0] to ip_slice[IP_SLICE_NUM] for ckgen_hpi from.." line.long 0x4 "CKGEN_BUS_SLICE_DBG_CTL,bus slice debug control" hexmask.long.word 0x4 0.--15. 1. "BUS_SLICE_DBG_SEL,bus slice debug clock source select. when bus clock is selected to be the debug source. this register choose debug clock source from bus_slice[0] to bus_slice[BUS_SLICE_NUM]" line.long 0x8 "CKGEN_CORE_SLICE_DBG_CTL,core slice debug control" hexmask.long.word 0x8 0.--15. 1. "CORE_SLICE_DBG_SEL,core slice debug clock source select. when core clock is selected to be the debug source. this register choose debug clock source from core_slice[0] to core_slice[CORE_SLICE_NUM]" line.long 0xC "CKGEN_DBG_CTL,ckgen debug control" bitfld.long 0xC 31. "DBG_CLK_DIS,disable ckgen debug function. 0: ckgen debug function enable 1: ckgen debug function disable" "ckgen debug function enable,ckgen debug function disable" bitfld.long 0xC 29.--30. "DBG_SEL,dbg clock out select: 2'b01: from bus slice clock which is controlled by CKGEN_BUS_SLICE_DBG_CTL 2'b10: from core slice clock which is controlled by CKGEN_CORE_SLICE_DBG_CTL others: from ip slice clock which is controlled by.." "?,from bus slice clock,from core slice clock,?" newline hexmask.long.word 0xC 0.--15. 1. "DBG_DIV_NUM,debug divider number only bit[3:0] are used since debug clock is monitored through pad only clock frequency less than 100MHz can be accepted. and divide the debug clock as early as possible from clock source." group.long 0x720++0x1B line.long 0x0 "CKGEN_IP_SLICE_MON_CTL,ip slice monitor control" hexmask.long.word 0x0 0.--15. 1. "IP_SLICE_MON_SEL,ip slice mon clock source select. for ckgen_saf/ckgen_sec/ckgen_disp when ip clock is selected to be the monitor source. this register choose monitor clock source from ip_slice[0] to ip_slice[IP_SLICE_NUM] for ckgen_hpi from.." line.long 0x4 "CKGEN_BUS_SLICE_MON_CTL,bus slice monitor control" hexmask.long.word 0x4 0.--15. 1. "BUS_SLICE_MON_SEL,bus slice mon clock source select. when bus clock is selected to be the monitor source. this register choose monitor clock source from bus_slice[0] to bus_slice[BUS_SLICE_NUM]" line.long 0x8 "CKGEN_CORE_SLICE_MON_CTL,core slice monitor control" hexmask.long.word 0x8 0.--15. 1. "CORE_SLICE_MON_SEL,core slice monitor clock source select. when core clock is selected to be the monitor source. this register choose monitor clock source from core_slice[0] to core_slice[CORE_SLICE_NUM]" line.long 0xC "CKGEN_MON_CTL,ckgen monitor control" bitfld.long 0xC 31. "MON_CLK_DIS,disable ckgen monitor function. 0: ckgen monitor function enable 1: ckgen monitor function disable" "ckgen monitor function enable,ckgen monitor function disable" bitfld.long 0xC 29.--30. "MON_SEL,monitor clock out select: 2'b01: from bus slice clock which is controlled by CKGEN_BUS_SLICE_MON_CTL 2'b10: from core slice clock which is controlled by CKGEN_CORE_SLICE_MON_CTL others: from ip slice clock which is controlled by.." "?,from bus slice clock,from core slice clock,?" newline bitfld.long 0xC 28. "MON_VAL_UPD_EN,latch monitor value enable 1: latch 0: latch disable" "latch disable,latch" rbitfld.long 0xC 27. "FREQ_RDY_STA,frequency calculate ready indicator." "0,1" newline rbitfld.long 0xC 26. "MON_CLK_DIS_STA,mon_clk_dis status. need to check after program mon_clk_dis" "0,1" bitfld.long 0xC 25. "CLK_SLOW_SRC,clk slow source select. this is the referenc clock source for clock monitor. 1: 32k 0: 24M" "0,1" newline rbitfld.long 0xC 16. "MON_DIV_BUSY,monitor divider update busy. indicate monitor divider update status. 1: monitor divider update on progress. 0: monitor divider update done." "monitor divider update done,monitor divider update on progress" newline hexmask.long.word 0xC 0.--15. 1. "MON_DIV_NUM,monitor divider number only bit[3:0] are used this field can be changed on-the-fly." line.long 0x10 "CKGEN_MON_MAX_FREQ,clock monitor max freq value" hexmask.long.word 0x10 0.--15. 1. "MON_MAX_FREQ,monitor clock max freq value. monitored max freq. this is only for debug" line.long 0x14 "CKGEN_MON_AVE_FREQ,clock monitor average freq value" hexmask.long.word 0x14 0.--15. 1. "MON_AVE_FREQ,monitor clock average freq value. the monitored clock frequency should be MON_AVE_FREQ * CLK_SLOW_SRC" line.long 0x18 "CKGEN_MON_MIN_FREQ,clock monitor min freq value" hexmask.long.word 0x18 0.--15. 1. "MON_MIN_FREQ,monitor clock mininum freq value. monitored min freq. this is only for debug" rgroup.long 0x73C++0x7 line.long 0x0 "CKGEN_MON_MAX_DUTY,clock monitor max high duty value" hexmask.long.word 0x0 16.--31. 1. "MON_MAX_PERIOD,monitor clock max period corresponding to the max high level value" hexmask.long.word 0x0 0.--15. 1. "MON_MAX_HIGH,monitor clock max high level value" line.long 0x4 "CKGEN_MON_MIN_DUTY,clock monitor min duty value" hexmask.long.word 0x4 16.--31. 1. "MON_MIN_PERIOD,monitor clock min period corresponding to the min high level value" hexmask.long.word 0x4 0.--15. 1. "MON_MIN_HIGH,monitor clock min high level value" tree.end tree "CKGEN_AP" base ad:0xF8000000 repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) group.long ($2)++0x3 line.long 0x0 "CKGEN_IP_SLICE_CTL_$1,ip slice control reg" rbitfld.long 0x0 31. "POST_BUSY,ck gen ip slice post_div busy status. indicate post divider update status. 1: post divider update on progress. 0: post divider update done." "post divider update done,post divider update on progress" rbitfld.long 0x0 30. "PRE_BUSY,ck gen ip slice pre_div busy status. indicate pre divider update status. 1: pre divider update on progress. 0: pre divider update done." "pre divider update done,pre divider update on progress" newline bitfld.long 0x0 28. "CG_EN_STATUS,clock gating enable status indicate CG_EN change doen since CG_EN is asynchronous to ip slice this bit indicate the CG_EN is received(active) in ip slice. when you change CG_EN you need to read this bit after that to make sure CG_EN is.." "0,1" newline hexmask.long.byte 0x0 10.--15. 1. "POST_DIV_NUM,post_div num. like PRE_DIV_NUM this field can be updated on-the-fly. and ip slice frequency will be selected clock source frequency/(PRE_DIV_NUM+1)/(POST_DIV_NUM+1)" newline bitfld.long 0x0 4.--6. "PRE_DIV_NUM,pre_div_num. each ip slice have 2 dividers pre_divider and post_divider. this field can be updated on-the-fly. ip slice frequency will be selected clock source frequency/(PRE_DIV_NUM+1)/(POST_DIV_NUM+1)" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 1.--3. "CLK_SRC_SEL,clock source select. each ip slice has 8 clock source(from clock source 0 to clock source 7) clock source information are in clock table. 0: clock source 0 1: clock source 1 .... 7: clock source 7" "clock source 0,clock source 1,?,?,?,?,?,clock source 7" bitfld.long 0x0 0. "CG_EN,clock gating enable. control the gating cell after ip slice 8-1 clock mux. 1: clock not gated. 0: clock gated. clock need to be gated before changing clock source. eg. if you want to change clock source from source 0 to source 1 you need to follow.." "clock gated,clock not gated" repeat.end repeat 2. (list 0x0 0x1 )(list 0x0 0x8 ) group.long ($2+0x200)++0x3 line.long 0x0 "CKGEN_BUS_SLICE_CTL_$1,bus slice control reg" rbitfld.long 0x0 31. "POST_BUSY,ck gen bus slice post_div busy status. indicate post divider update status. 1: post divider update on progress. 0: post divider update done." "post divider update done,post divider update on progress" rbitfld.long 0x0 30. "PRE_BUSY_A,ck gen bus slice pre_div_a busy status. indicate pre divider a update status. 1: pre divider a update on progress. 0: pre divider a update done." "pre divider a update done,pre divider a update on progress" newline rbitfld.long 0x0 29. "PRE_BUSY_B,ck gen bus slice pre_div_b busy. indicate pre divider b update status. 1: pre divider b update on progress. 0: pre divider b update done." "pre divider b update done,pre divider b update on progress" bitfld.long 0x0 28. "CG_EN_A_STATUS,clock gating enable a status indicate CG_EN_A change doen. since CG_EN_A is asynchronous to bus slice this bit indicate the CG_EN_A is received(active) in bus slice. when you change CG_EN_A you need to read this bit after that to make.." "0,1" newline bitfld.long 0x0 27. "CG_EN_B_STATUS,clock gating enable b status indicate CG_EN_B change doen. since CG_EN_B is asynchronous to bus slice this bit indicate the CG_EN_B is received(active) in bus slice. when you change CG_EN_B you need to read this bit after that to make.." "0,1" newline bitfld.long 0x0 20.--22. "PRE_DIV_NUM_B,pre_div_b num. each bus slice have 3 dividers pre_divider_a pre_divider_b and post_divider. this field can be updated on-the-fly. bus slice frequency will be selected clock source frequency/(PRE_DIV_NUM+1)/(POST_DIV_NUM+1). in which.." "0,1,2,3,4,5,6,7" bitfld.long 0x0 17.--19. "CLK_SRC_SEL_B,path b clock source select. each path in bus slice has 8 clock source(from clock source 0 to clock source 7 and path a and path b clock sources are totally the same) clock source information are in clock table. 0: clock source 0 1: clock.." "clock source 0,clock source 1,?,?,?,?,?,clock source 7" newline bitfld.long 0x0 16. "CG_EN_B,path b clock gating enable. control the gating cell after bus slice path b 8-1 clock mux. 1: clock not gated. 0: clock gated. clock need to be gated before changing clock source. eg. if you want to change clock source from source 0 to source 1.." "clock gated,clock not gated" hexmask.long.byte 0x0 10.--15. 1. "POST_DIV_NUM,post_div num. each bus slice have 3 dividers pre_divider_a pre_divider_b and post_divider. this field can be updated on-the-fly. bus slice frequency will be selected clock source frequency/(PRE_DIV_NUM+1)/(POST_DIV_NUM+1). in which.." newline bitfld.long 0x0 9. "A_B_SEL,select between path a and path b clock source. 0: path a is selected. 1: path b is selected. this can be changed on-the-fly. please make sure both path a frequency and path b frequency are within spec." "path a is selected,path b is selected" newline bitfld.long 0x0 4.--6. "PRE_DIV_NUM_A,pre_div_a num. each bus slice have 3 dividers pre_divider_a pre_divider_b and post_divider. this field can be updated on-the-fly. bus slice frequency will be selected clock source frequency/(PRE_DIV_NUM+1)/(POST_DIV_NUM+1). in which.." "0,1,2,3,4,5,6,7" bitfld.long 0x0 1.--3. "CLK_SRC_SEL_A,path a clock source select. each path in bus slice has 8 clock source(from clock source 0 to clock source 7 and path a and path b clock sources are totally the same) clock source information are in clock table. 0: clock source 0 1: clock.." "clock source 0,clock source 1,?,?,?,?,?,clock source 7" newline bitfld.long 0x0 0. "CG_EN_A,path a clock gating enable. control the gating cell after bus slice path a 8-1 clock mux. 1: clock not gated. 0: clock gated. clock need to be gated before changing clock source. eg. if you want to change clock source from source 0 to source 1.." "clock gated,clock not gated" repeat.end repeat 2. (list 0x0 0x1 )(list 0x0 0x8 ) group.long ($2+0x204)++0x3 line.long 0x0 "CKGEN_BUS_SLICE_GASKET_$1,bus slice gasket control" rbitfld.long 0x0 31. "DIV_M_BUSY,clock/m divider busy status. indicate clock/m divider update status. 1: clock/m divider update on progress. 0: clock/m divider update done." "clock/m divider update done,clock/m divider update on progress" rbitfld.long 0x0 30. "DIV_N_BUSY,clock/n divider busy status. indicate clock/n divider update status. 1: clock/n divider update on progress. 0: clock/n divider update done." "clock/n divider update done,clock/n divider update on progress" newline rbitfld.long 0x0 29. "DIV_P_BUSY,clock/p divider busy status. indicate clock/p divider update status. 1: clock/p divider update on progress. 0: clock/p divider update done." "clock/p divider update done,clock/p divider update on progress" rbitfld.long 0x0 28. "DIV_Q_BUSY,clock/q divider busy status. indicate clock/q divider update status. 1: clock/q divider update on progress. 0: clock/q divider update done." "clock/q divider update done,clock/q divider update on progress" newline bitfld.long 0x0 9.--11. "M_DIV_NUM,divider number for clock/m. this field can be updated on-the-fly. and bus slice gasket m frequency will be the corresponding bus clock frequency/(M_DIV_NUM+1)" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 6.--8. "N_DIV_NUM,divider number for clock/n this field can be updated on-the-fly. and bus slice gasket m frequency will be the corresponding bus clock frequency/(N_DIV_NUM+1)" "0,1,2,3,4,5,6,7" bitfld.long 0x0 3.--5. "P_DIV_NUM,divider number for clock/p this field can be updated on-the-fly. and bus slice gasket m frequency will be the corresponding bus clock frequency/(P_DIV_NUM+1)" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 0.--2. "Q_DIV_NUM,divider number for clock/q this field can be updated on-the-fly. and bus slice gasket m frequency will be the corresponding bus clock frequency/(Q_DIV_NUM+1)" "0,1,2,3,4,5,6,7" repeat.end repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) group.long ($2+0x300)++0x3 line.long 0x0 "CKGEN_CORE_SLICE_CTL_$1,core slice control reg" rbitfld.long 0x0 31. "POST_BUSY,ckgen core slice post_div busy status. indicate post divider update status. 1: post divider update on progress. 0: post divider update done." "post divider update done,post divider update on progress" newline bitfld.long 0x0 28. "CG_EN_A_STATUS,clock gating enable a status indicate CG_EN_A change done. since CG_EN_A is asynchronous to core slice this bit indicate the CG_EN_A is received(active) in core slice. when you change CG_EN_A you need to read this bit after that to make.." "0,1" bitfld.long 0x0 27. "CG_EN_B_STATUS,clock gating enable b status indicate CG_EN_B change doen. since CG_EN_B is asynchronous to core slice this bit indicate the CG_EN_B is received(active) in core slice. when you change CG_EN_B you need to read this bit after that to make.." "0,1" newline bitfld.long 0x0 17.--19. "CLK_SRC_SEL_B,path b clock source select. each path in bus slice has 8 clock source(from clock source 0 to clock source 7 and path a and path b clock sources are totally the same) clock source information are in clock table. 0: clock source 0 1: clock.." "clock source 0,clock source 1,?,?,?,?,?,clock source 7" newline bitfld.long 0x0 16. "CG_EN_B,path b clock gating enable. control the gating cell after core slice path b 8-1 clock mux. 1: clock not gated. 0: clock gated. clock need to be gated before changing clock source. eg. if you want to change clock source from source 0 to source 1.." "clock gated,clock not gated" hexmask.long.byte 0x0 10.--15. 1. "POST_DIV_NUM,post_div num. this field can be updated on-the-fly. core slice frequency will be selected clock source frequency/(POST_DIV_NUM+1)." newline bitfld.long 0x0 9. "A_B_SEL,select between path a and path b clock source. 0: path a is selected. 1: path b is selected. this can be changed on-the-fly. please make sure both path a frequency and path b frequency are within spec." "path a is selected,path b is selected" newline bitfld.long 0x0 1.--3. "CLK_SRC_SEL_A,path a clock source select. each path in core slice has 8 clock source(from clock source 0 to clock source 7 and path a and path b clock sources are totally the same) clock source information are in clock table. 0: clock source 0 1: clock.." "clock source 0,clock source 1,?,?,?,?,?,clock source 7" bitfld.long 0x0 0. "CG_EN_A,path a clock gating enable. control the gating cell after core slice path a 8-1 clock mux. 1: clock not gated. 0: clock gated. clock need to be gated before changing clock source. eg. if you want to change clock source from source 0 to source 1.." "clock gated,clock not gated" repeat.end repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) group.long ($2+0x400)++0x3 line.long 0x0 "CKGEN_LP_GATING_EN_$1,ip slice sw gating enable" bitfld.long 0x0 31. "CKGEN_GATING_LOCK,LOCK SW_GATING_EN/DIS 1: locked. SW_GATING_DIS/EN will keep what they are 0: unlocked SW_GATING_DIS/EN can be changed" "unlocked,locked" newline bitfld.long 0x0 1. "SW_GATING_DIS,ckgen software gating disable has higher priority than sw_gating_en. if this bit is 1'b1 then the controlled clock will be forced on(ignore the SW_GATING_EN." "0,1" bitfld.long 0x0 0. "SW_GATING_EN,ckgen software gating enable. control the gating cell IP clock in most IPs have different gating cells you can refer to clock gating control table. 1: clock not gated. 0: clock gated." "clock gated,clock not gated" repeat.end group.long 0x600++0x3 line.long 0x0 "CKGEN_UUU_SLICE_0,uuu clock wrapper control" bitfld.long 0x0 31. "UUU_DBG_GATING_EN,gating enable for debug output. control the gating cell before uuu dbg divider 1: clock not gated. 0: clock gated." "clock gated,clock not gated" hexmask.long.byte 0x0 27.--30. 1. "DBG_DIV_NUM,divder number for debug output. this field can be updated on-the-fly. dbg clock frequence will be selected clk_out_0/(DBG_DIV_NUM+1)" newline bitfld.long 0x0 20. "UUU_GATING_ACK,reserved" "0,1" newline hexmask.long.byte 0x0 16.--19. 1. "UUU_SEL,for uuu wrapper clock gating control and clock source select uuu_sel[1:0]: clk_sel in uuu_clock_wrapper uuu_sel[1]: 1: clk_out_0 from pll 0: clk_out_0 from clk_m uuu_sel_[0]: 1: uuu input clock from pll 2: uuu input clock from ckgen_hpi slice.." hexmask.long.byte 0x0 12.--15. 1. "M_DIV_NUM,divider number for clock/m. this field can be updated on-the-fly. and uuu clock m frequency will be the corresponding uuu clock frequency/(M_DIV_NUM+1)" newline hexmask.long.byte 0x0 8.--11. 1. "N_DIV_NUM,divider number for clock/n. this field can be updated on-the-fly. and uuu clock m frequency will be the corresponding uuu clock frequency/(N_DIV_NUM+1)" hexmask.long.byte 0x0 4.--7. 1. "P_DIV_NUM,divider number for clock/p this field can be updated on-the-fly. and uuu clock m frequency will be the corresponding uuu clock frequency/(P_DIV_NUM+1)" newline hexmask.long.byte 0x0 0.--3. 1. "Q_DIV_NUM,divider number for clock/q this field can be updated on-the-fly. and uuu clock m frequency will be the corresponding uuu clock frequency/(Q_DIV_NUM+1)" group.long 0x700++0xF line.long 0x0 "CKGEN_IP_SLICE_DBG_CTL,ip slice debug control" hexmask.long.word 0x0 0.--15. 1. "IP_SLICE_DBG_SEL,ip slice debug clock source select. for ckgen_saf/ckgen_sec/ckgen_disp when ip clock is selected to be the debug source. this register choose debug clock source from ip_slice[0] to ip_slice[IP_SLICE_NUM] for ckgen_hpi from.." line.long 0x4 "CKGEN_BUS_SLICE_DBG_CTL,bus slice debug control" hexmask.long.word 0x4 0.--15. 1. "BUS_SLICE_DBG_SEL,bus slice debug clock source select. when bus clock is selected to be the debug source. this register choose debug clock source from bus_slice[0] to bus_slice[BUS_SLICE_NUM]" line.long 0x8 "CKGEN_CORE_SLICE_DBG_CTL,core slice debug control" hexmask.long.word 0x8 0.--15. 1. "CORE_SLICE_DBG_SEL,core slice debug clock source select. when core clock is selected to be the debug source. this register choose debug clock source from core_slice[0] to core_slice[CORE_SLICE_NUM]" line.long 0xC "CKGEN_DBG_CTL,ckgen debug control" bitfld.long 0xC 31. "DBG_CLK_DIS,disable ckgen debug function. 0: ckgen debug function enable 1: ckgen debug function disable" "ckgen debug function enable,ckgen debug function disable" bitfld.long 0xC 29.--30. "DBG_SEL,dbg clock out select: 2'b01: from bus slice clock which is controlled by CKGEN_BUS_SLICE_DBG_CTL 2'b10: from core slice clock which is controlled by CKGEN_CORE_SLICE_DBG_CTL others: from ip slice clock which is controlled by.." "?,from bus slice clock,from core slice clock,?" newline hexmask.long.word 0xC 0.--15. 1. "DBG_DIV_NUM,debug divider number only bit[3:0] are used since debug clock is monitored through pad only clock frequency less than 100MHz can be accepted. and divide the debug clock as early as possible from clock source." group.long 0x720++0x1B line.long 0x0 "CKGEN_IP_SLICE_MON_CTL,ip slice monitor control" hexmask.long.word 0x0 0.--15. 1. "IP_SLICE_MON_SEL,ip slice mon clock source select. for ckgen_saf/ckgen_sec/ckgen_disp when ip clock is selected to be the monitor source. this register choose monitor clock source from ip_slice[0] to ip_slice[IP_SLICE_NUM] for ckgen_hpi from.." line.long 0x4 "CKGEN_BUS_SLICE_MON_CTL,bus slice monitor control" hexmask.long.word 0x4 0.--15. 1. "BUS_SLICE_MON_SEL,bus slice mon clock source select. when bus clock is selected to be the monitor source. this register choose monitor clock source from bus_slice[0] to bus_slice[BUS_SLICE_NUM]" line.long 0x8 "CKGEN_CORE_SLICE_MON_CTL,core slice monitor control" hexmask.long.word 0x8 0.--15. 1. "CORE_SLICE_MON_SEL,core slice monitor clock source select. when core clock is selected to be the monitor source. this register choose monitor clock source from core_slice[0] to core_slice[CORE_SLICE_NUM]" line.long 0xC "CKGEN_MON_CTL,ckgen monitor control" bitfld.long 0xC 31. "MON_CLK_DIS,disable ckgen monitor function. 0: ckgen monitor function enable 1: ckgen monitor function disable" "ckgen monitor function enable,ckgen monitor function disable" bitfld.long 0xC 29.--30. "MON_SEL,monitor clock out select: 2'b01: from bus slice clock which is controlled by CKGEN_BUS_SLICE_MON_CTL 2'b10: from core slice clock which is controlled by CKGEN_CORE_SLICE_MON_CTL others: from ip slice clock which is controlled by.." "?,from bus slice clock,from core slice clock,?" newline bitfld.long 0xC 28. "MON_VAL_UPD_EN,latch monitor value enable 1: latch 0: latch disable" "latch disable,latch" rbitfld.long 0xC 27. "FREQ_RDY_STA,frequency calculate ready indicator." "0,1" newline rbitfld.long 0xC 26. "MON_CLK_DIS_STA,mon_clk_dis status. need to check after program mon_clk_dis" "0,1" bitfld.long 0xC 25. "CLK_SLOW_SRC,clk slow source select. this is the referenc clock source for clock monitor. 1: 32k 0: 24M" "0,1" newline rbitfld.long 0xC 16. "MON_DIV_BUSY,monitor divider update busy. indicate monitor divider update status. 1: monitor divider update on progress. 0: monitor divider update done." "monitor divider update done,monitor divider update on progress" newline hexmask.long.word 0xC 0.--15. 1. "MON_DIV_NUM,monitor divider number only bit[3:0] are used this field can be changed on-the-fly." line.long 0x10 "CKGEN_MON_MAX_FREQ,clock monitor max freq value" hexmask.long.word 0x10 0.--15. 1. "MON_MAX_FREQ,monitor clock max freq value. monitored max freq. this is only for debug" line.long 0x14 "CKGEN_MON_AVE_FREQ,clock monitor average freq value" hexmask.long.word 0x14 0.--15. 1. "MON_AVE_FREQ,monitor clock average freq value. the monitored clock frequency should be MON_AVE_FREQ * CLK_SLOW_SRC" line.long 0x18 "CKGEN_MON_MIN_FREQ,clock monitor min freq value" hexmask.long.word 0x18 0.--15. 1. "MON_MIN_FREQ,monitor clock mininum freq value. monitored min freq. this is only for debug" rgroup.long 0x73C++0x7 line.long 0x0 "CKGEN_MON_MAX_DUTY,clock monitor max high duty value" hexmask.long.word 0x0 16.--31. 1. "MON_MAX_PERIOD,monitor clock max period corresponding to the max high level value" hexmask.long.word 0x0 0.--15. 1. "MON_MAX_HIGH,monitor clock max high level value" line.long 0x4 "CKGEN_MON_MIN_DUTY,clock monitor min duty value" hexmask.long.word 0x4 16.--31. 1. "MON_MIN_PERIOD,monitor clock min period corresponding to the min high level value" hexmask.long.word 0x4 0.--15. 1. "MON_MIN_HIGH,monitor clock min high level value" tree.end tree "CKGEN_SAFETY" base ad:0xFC000000 repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) group.long ($2)++0x3 line.long 0x0 "CKGEN_IP_SLICE_CTL_$1,ip slice control reg" rbitfld.long 0x0 31. "POST_BUSY,ck gen ip slice post_div busy status. indicate post divider update status. 1: post divider update on progress. 0: post divider update done." "post divider update done,post divider update on progress" rbitfld.long 0x0 30. "PRE_BUSY,ck gen ip slice pre_div busy status. indicate pre divider update status. 1: pre divider update on progress. 0: pre divider update done." "pre divider update done,pre divider update on progress" newline bitfld.long 0x0 28. "CG_EN_STATUS,clock gating enable status indicate CG_EN change doen since CG_EN is asynchronous to ip slice this bit indicate the CG_EN is received(active) in ip slice. when you change CG_EN you need to read this bit after that to make sure CG_EN is.." "0,1" newline hexmask.long.byte 0x0 10.--15. 1. "POST_DIV_NUM,post_div num. like PRE_DIV_NUM this field can be updated on-the-fly. and ip slice frequency will be selected clock source frequency/(PRE_DIV_NUM+1)/(POST_DIV_NUM+1)" newline bitfld.long 0x0 4.--6. "PRE_DIV_NUM,pre_div_num. each ip slice have 2 dividers pre_divider and post_divider. this field can be updated on-the-fly. ip slice frequency will be selected clock source frequency/(PRE_DIV_NUM+1)/(POST_DIV_NUM+1)" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 1.--3. "CLK_SRC_SEL,clock source select. each ip slice has 8 clock source(from clock source 0 to clock source 7) clock source information are in clock table. 0: clock source 0 1: clock source 1 .... 7: clock source 7" "clock source 0,clock source 1,?,?,?,?,?,clock source 7" bitfld.long 0x0 0. "CG_EN,clock gating enable. control the gating cell after ip slice 8-1 clock mux. 1: clock not gated. 0: clock gated. clock need to be gated before changing clock source. eg. if you want to change clock source from source 0 to source 1 you need to follow.." "clock gated,clock not gated" repeat.end repeat 2. (list 0x0 0x1 )(list 0x0 0x8 ) group.long ($2+0x200)++0x3 line.long 0x0 "CKGEN_BUS_SLICE_CTL_$1,bus slice control reg" rbitfld.long 0x0 31. "POST_BUSY,ck gen bus slice post_div busy status. indicate post divider update status. 1: post divider update on progress. 0: post divider update done." "post divider update done,post divider update on progress" rbitfld.long 0x0 30. "PRE_BUSY_A,ck gen bus slice pre_div_a busy status. indicate pre divider a update status. 1: pre divider a update on progress. 0: pre divider a update done." "pre divider a update done,pre divider a update on progress" newline rbitfld.long 0x0 29. "PRE_BUSY_B,ck gen bus slice pre_div_b busy. indicate pre divider b update status. 1: pre divider b update on progress. 0: pre divider b update done." "pre divider b update done,pre divider b update on progress" bitfld.long 0x0 28. "CG_EN_A_STATUS,clock gating enable a status indicate CG_EN_A change doen. since CG_EN_A is asynchronous to bus slice this bit indicate the CG_EN_A is received(active) in bus slice. when you change CG_EN_A you need to read this bit after that to make.." "0,1" newline bitfld.long 0x0 27. "CG_EN_B_STATUS,clock gating enable b status indicate CG_EN_B change doen. since CG_EN_B is asynchronous to bus slice this bit indicate the CG_EN_B is received(active) in bus slice. when you change CG_EN_B you need to read this bit after that to make.." "0,1" newline bitfld.long 0x0 20.--22. "PRE_DIV_NUM_B,pre_div_b num. each bus slice have 3 dividers pre_divider_a pre_divider_b and post_divider. this field can be updated on-the-fly. bus slice frequency will be selected clock source frequency/(PRE_DIV_NUM+1)/(POST_DIV_NUM+1). in which.." "0,1,2,3,4,5,6,7" bitfld.long 0x0 17.--19. "CLK_SRC_SEL_B,path b clock source select. each path in bus slice has 8 clock source(from clock source 0 to clock source 7 and path a and path b clock sources are totally the same) clock source information are in clock table. 0: clock source 0 1: clock.." "clock source 0,clock source 1,?,?,?,?,?,clock source 7" newline bitfld.long 0x0 16. "CG_EN_B,path b clock gating enable. control the gating cell after bus slice path b 8-1 clock mux. 1: clock not gated. 0: clock gated. clock need to be gated before changing clock source. eg. if you want to change clock source from source 0 to source 1.." "clock gated,clock not gated" hexmask.long.byte 0x0 10.--15. 1. "POST_DIV_NUM,post_div num. each bus slice have 3 dividers pre_divider_a pre_divider_b and post_divider. this field can be updated on-the-fly. bus slice frequency will be selected clock source frequency/(PRE_DIV_NUM+1)/(POST_DIV_NUM+1). in which.." newline bitfld.long 0x0 9. "A_B_SEL,select between path a and path b clock source. 0: path a is selected. 1: path b is selected. this can be changed on-the-fly. please make sure both path a frequency and path b frequency are within spec." "path a is selected,path b is selected" newline bitfld.long 0x0 4.--6. "PRE_DIV_NUM_A,pre_div_a num. each bus slice have 3 dividers pre_divider_a pre_divider_b and post_divider. this field can be updated on-the-fly. bus slice frequency will be selected clock source frequency/(PRE_DIV_NUM+1)/(POST_DIV_NUM+1). in which.." "0,1,2,3,4,5,6,7" bitfld.long 0x0 1.--3. "CLK_SRC_SEL_A,path a clock source select. each path in bus slice has 8 clock source(from clock source 0 to clock source 7 and path a and path b clock sources are totally the same) clock source information are in clock table. 0: clock source 0 1: clock.." "clock source 0,clock source 1,?,?,?,?,?,clock source 7" newline bitfld.long 0x0 0. "CG_EN_A,path a clock gating enable. control the gating cell after bus slice path a 8-1 clock mux. 1: clock not gated. 0: clock gated. clock need to be gated before changing clock source. eg. if you want to change clock source from source 0 to source 1.." "clock gated,clock not gated" repeat.end repeat 2. (list 0x0 0x1 )(list 0x0 0x8 ) group.long ($2+0x204)++0x3 line.long 0x0 "CKGEN_BUS_SLICE_GASKET_$1,bus slice gasket control" rbitfld.long 0x0 31. "DIV_M_BUSY,clock/m divider busy status. indicate clock/m divider update status. 1: clock/m divider update on progress. 0: clock/m divider update done." "clock/m divider update done,clock/m divider update on progress" rbitfld.long 0x0 30. "DIV_N_BUSY,clock/n divider busy status. indicate clock/n divider update status. 1: clock/n divider update on progress. 0: clock/n divider update done." "clock/n divider update done,clock/n divider update on progress" newline rbitfld.long 0x0 29. "DIV_P_BUSY,clock/p divider busy status. indicate clock/p divider update status. 1: clock/p divider update on progress. 0: clock/p divider update done." "clock/p divider update done,clock/p divider update on progress" rbitfld.long 0x0 28. "DIV_Q_BUSY,clock/q divider busy status. indicate clock/q divider update status. 1: clock/q divider update on progress. 0: clock/q divider update done." "clock/q divider update done,clock/q divider update on progress" newline bitfld.long 0x0 9.--11. "M_DIV_NUM,divider number for clock/m. this field can be updated on-the-fly. and bus slice gasket m frequency will be the corresponding bus clock frequency/(M_DIV_NUM+1)" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 6.--8. "N_DIV_NUM,divider number for clock/n this field can be updated on-the-fly. and bus slice gasket m frequency will be the corresponding bus clock frequency/(N_DIV_NUM+1)" "0,1,2,3,4,5,6,7" bitfld.long 0x0 3.--5. "P_DIV_NUM,divider number for clock/p this field can be updated on-the-fly. and bus slice gasket m frequency will be the corresponding bus clock frequency/(P_DIV_NUM+1)" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 0.--2. "Q_DIV_NUM,divider number for clock/q this field can be updated on-the-fly. and bus slice gasket m frequency will be the corresponding bus clock frequency/(Q_DIV_NUM+1)" "0,1,2,3,4,5,6,7" repeat.end repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) group.long ($2+0x300)++0x3 line.long 0x0 "CKGEN_CORE_SLICE_CTL_$1,core slice control reg" rbitfld.long 0x0 31. "POST_BUSY,ckgen core slice post_div busy status. indicate post divider update status. 1: post divider update on progress. 0: post divider update done." "post divider update done,post divider update on progress" newline bitfld.long 0x0 28. "CG_EN_A_STATUS,clock gating enable a status indicate CG_EN_A change done. since CG_EN_A is asynchronous to core slice this bit indicate the CG_EN_A is received(active) in core slice. when you change CG_EN_A you need to read this bit after that to make.." "0,1" bitfld.long 0x0 27. "CG_EN_B_STATUS,clock gating enable b status indicate CG_EN_B change doen. since CG_EN_B is asynchronous to core slice this bit indicate the CG_EN_B is received(active) in core slice. when you change CG_EN_B you need to read this bit after that to make.." "0,1" newline bitfld.long 0x0 17.--19. "CLK_SRC_SEL_B,path b clock source select. each path in bus slice has 8 clock source(from clock source 0 to clock source 7 and path a and path b clock sources are totally the same) clock source information are in clock table. 0: clock source 0 1: clock.." "clock source 0,clock source 1,?,?,?,?,?,clock source 7" newline bitfld.long 0x0 16. "CG_EN_B,path b clock gating enable. control the gating cell after core slice path b 8-1 clock mux. 1: clock not gated. 0: clock gated. clock need to be gated before changing clock source. eg. if you want to change clock source from source 0 to source 1.." "clock gated,clock not gated" hexmask.long.byte 0x0 10.--15. 1. "POST_DIV_NUM,post_div num. this field can be updated on-the-fly. core slice frequency will be selected clock source frequency/(POST_DIV_NUM+1)." newline bitfld.long 0x0 9. "A_B_SEL,select between path a and path b clock source. 0: path a is selected. 1: path b is selected. this can be changed on-the-fly. please make sure both path a frequency and path b frequency are within spec." "path a is selected,path b is selected" newline bitfld.long 0x0 1.--3. "CLK_SRC_SEL_A,path a clock source select. each path in core slice has 8 clock source(from clock source 0 to clock source 7 and path a and path b clock sources are totally the same) clock source information are in clock table. 0: clock source 0 1: clock.." "clock source 0,clock source 1,?,?,?,?,?,clock source 7" bitfld.long 0x0 0. "CG_EN_A,path a clock gating enable. control the gating cell after core slice path a 8-1 clock mux. 1: clock not gated. 0: clock gated. clock need to be gated before changing clock source. eg. if you want to change clock source from source 0 to source 1.." "clock gated,clock not gated" repeat.end repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) group.long ($2+0x400)++0x3 line.long 0x0 "CKGEN_LP_GATING_EN_$1,ip slice sw gating enable" bitfld.long 0x0 31. "CKGEN_GATING_LOCK,LOCK SW_GATING_EN/DIS 1: locked. SW_GATING_DIS/EN will keep what they are 0: unlocked SW_GATING_DIS/EN can be changed" "unlocked,locked" newline bitfld.long 0x0 1. "SW_GATING_DIS,ckgen software gating disable has higher priority than sw_gating_en. if this bit is 1'b1 then the controlled clock will be forced on(ignore the SW_GATING_EN." "0,1" bitfld.long 0x0 0. "SW_GATING_EN,ckgen software gating enable. control the gating cell IP clock in most IPs have different gating cells you can refer to clock gating control table. 1: clock not gated. 0: clock gated." "clock gated,clock not gated" repeat.end group.long 0x600++0x3 line.long 0x0 "CKGEN_UUU_SLICE_0,uuu clock wrapper control" bitfld.long 0x0 31. "UUU_DBG_GATING_EN,gating enable for debug output. control the gating cell before uuu dbg divider 1: clock not gated. 0: clock gated." "clock gated,clock not gated" hexmask.long.byte 0x0 27.--30. 1. "DBG_DIV_NUM,divder number for debug output. this field can be updated on-the-fly. dbg clock frequence will be selected clk_out_0/(DBG_DIV_NUM+1)" newline bitfld.long 0x0 20. "UUU_GATING_ACK,reserved" "0,1" newline hexmask.long.byte 0x0 16.--19. 1. "UUU_SEL,for uuu wrapper clock gating control and clock source select uuu_sel[1:0]: clk_sel in uuu_clock_wrapper uuu_sel[1]: 1: clk_out_0 from pll 0: clk_out_0 from clk_m uuu_sel_[0]: 1: uuu input clock from pll 2: uuu input clock from ckgen_hpi slice.." hexmask.long.byte 0x0 12.--15. 1. "M_DIV_NUM,divider number for clock/m. this field can be updated on-the-fly. and uuu clock m frequency will be the corresponding uuu clock frequency/(M_DIV_NUM+1)" newline hexmask.long.byte 0x0 8.--11. 1. "N_DIV_NUM,divider number for clock/n. this field can be updated on-the-fly. and uuu clock m frequency will be the corresponding uuu clock frequency/(N_DIV_NUM+1)" hexmask.long.byte 0x0 4.--7. 1. "P_DIV_NUM,divider number for clock/p this field can be updated on-the-fly. and uuu clock m frequency will be the corresponding uuu clock frequency/(P_DIV_NUM+1)" newline hexmask.long.byte 0x0 0.--3. 1. "Q_DIV_NUM,divider number for clock/q this field can be updated on-the-fly. and uuu clock m frequency will be the corresponding uuu clock frequency/(Q_DIV_NUM+1)" group.long 0x700++0xF line.long 0x0 "CKGEN_IP_SLICE_DBG_CTL,ip slice debug control" hexmask.long.word 0x0 0.--15. 1. "IP_SLICE_DBG_SEL,ip slice debug clock source select. for ckgen_saf/ckgen_sec/ckgen_disp when ip clock is selected to be the debug source. this register choose debug clock source from ip_slice[0] to ip_slice[IP_SLICE_NUM] for ckgen_hpi from.." line.long 0x4 "CKGEN_BUS_SLICE_DBG_CTL,bus slice debug control" hexmask.long.word 0x4 0.--15. 1. "BUS_SLICE_DBG_SEL,bus slice debug clock source select. when bus clock is selected to be the debug source. this register choose debug clock source from bus_slice[0] to bus_slice[BUS_SLICE_NUM]" line.long 0x8 "CKGEN_CORE_SLICE_DBG_CTL,core slice debug control" hexmask.long.word 0x8 0.--15. 1. "CORE_SLICE_DBG_SEL,core slice debug clock source select. when core clock is selected to be the debug source. this register choose debug clock source from core_slice[0] to core_slice[CORE_SLICE_NUM]" line.long 0xC "CKGEN_DBG_CTL,ckgen debug control" bitfld.long 0xC 31. "DBG_CLK_DIS,disable ckgen debug function. 0: ckgen debug function enable 1: ckgen debug function disable" "ckgen debug function enable,ckgen debug function disable" bitfld.long 0xC 29.--30. "DBG_SEL,dbg clock out select: 2'b01: from bus slice clock which is controlled by CKGEN_BUS_SLICE_DBG_CTL 2'b10: from core slice clock which is controlled by CKGEN_CORE_SLICE_DBG_CTL others: from ip slice clock which is controlled by.." "?,from bus slice clock,from core slice clock,?" newline hexmask.long.word 0xC 0.--15. 1. "DBG_DIV_NUM,debug divider number only bit[3:0] are used since debug clock is monitored through pad only clock frequency less than 100MHz can be accepted. and divide the debug clock as early as possible from clock source." group.long 0x720++0x1B line.long 0x0 "CKGEN_IP_SLICE_MON_CTL,ip slice monitor control" hexmask.long.word 0x0 0.--15. 1. "IP_SLICE_MON_SEL,ip slice mon clock source select. for ckgen_saf/ckgen_sec/ckgen_disp when ip clock is selected to be the monitor source. this register choose monitor clock source from ip_slice[0] to ip_slice[IP_SLICE_NUM] for ckgen_hpi from.." line.long 0x4 "CKGEN_BUS_SLICE_MON_CTL,bus slice monitor control" hexmask.long.word 0x4 0.--15. 1. "BUS_SLICE_MON_SEL,bus slice mon clock source select. when bus clock is selected to be the monitor source. this register choose monitor clock source from bus_slice[0] to bus_slice[BUS_SLICE_NUM]" line.long 0x8 "CKGEN_CORE_SLICE_MON_CTL,core slice monitor control" hexmask.long.word 0x8 0.--15. 1. "CORE_SLICE_MON_SEL,core slice monitor clock source select. when core clock is selected to be the monitor source. this register choose monitor clock source from core_slice[0] to core_slice[CORE_SLICE_NUM]" line.long 0xC "CKGEN_MON_CTL,ckgen monitor control" bitfld.long 0xC 31. "MON_CLK_DIS,disable ckgen monitor function. 0: ckgen monitor function enable 1: ckgen monitor function disable" "ckgen monitor function enable,ckgen monitor function disable" bitfld.long 0xC 29.--30. "MON_SEL,monitor clock out select: 2'b01: from bus slice clock which is controlled by CKGEN_BUS_SLICE_MON_CTL 2'b10: from core slice clock which is controlled by CKGEN_CORE_SLICE_MON_CTL others: from ip slice clock which is controlled by.." "?,from bus slice clock,from core slice clock,?" newline bitfld.long 0xC 28. "MON_VAL_UPD_EN,latch monitor value enable 1: latch 0: latch disable" "latch disable,latch" rbitfld.long 0xC 27. "FREQ_RDY_STA,frequency calculate ready indicator." "0,1" newline rbitfld.long 0xC 26. "MON_CLK_DIS_STA,mon_clk_dis status. need to check after program mon_clk_dis" "0,1" bitfld.long 0xC 25. "CLK_SLOW_SRC,clk slow source select. this is the referenc clock source for clock monitor. 1: 32k 0: 24M" "0,1" newline rbitfld.long 0xC 16. "MON_DIV_BUSY,monitor divider update busy. indicate monitor divider update status. 1: monitor divider update on progress. 0: monitor divider update done." "monitor divider update done,monitor divider update on progress" newline hexmask.long.word 0xC 0.--15. 1. "MON_DIV_NUM,monitor divider number only bit[3:0] are used this field can be changed on-the-fly." line.long 0x10 "CKGEN_MON_MAX_FREQ,clock monitor max freq value" hexmask.long.word 0x10 0.--15. 1. "MON_MAX_FREQ,monitor clock max freq value. monitored max freq. this is only for debug" line.long 0x14 "CKGEN_MON_AVE_FREQ,clock monitor average freq value" hexmask.long.word 0x14 0.--15. 1. "MON_AVE_FREQ,monitor clock average freq value. the monitored clock frequency should be MON_AVE_FREQ * CLK_SLOW_SRC" line.long 0x18 "CKGEN_MON_MIN_FREQ,clock monitor min freq value" hexmask.long.word 0x18 0.--15. 1. "MON_MIN_FREQ,monitor clock mininum freq value. monitored min freq. this is only for debug" rgroup.long 0x73C++0x7 line.long 0x0 "CKGEN_MON_MAX_DUTY,clock monitor max high duty value" hexmask.long.word 0x0 16.--31. 1. "MON_MAX_PERIOD,monitor clock max period corresponding to the max high level value" hexmask.long.word 0x0 0.--15. 1. "MON_MAX_HIGH,monitor clock max high level value" line.long 0x4 "CKGEN_MON_MIN_DUTY,clock monitor min duty value" hexmask.long.word 0x4 16.--31. 1. "MON_MIN_PERIOD,monitor clock min period corresponding to the min high level value" hexmask.long.word 0x4 0.--15. 1. "MON_MIN_HIGH,monitor clock min high level value" tree.end elif (CORENAME()=="CORTEXA55") tree "CKGEN_XPU" base ad:0x36000000 repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) group.long ($2)++0x3 line.long 0x0 "CKGEN_IP_SLICE_CTL_$1,ip slice control reg" rbitfld.long 0x0 31. "POST_BUSY,ck gen ip slice post_div busy status. indicate post divider update status. 1: post divider update on progress. 0: post divider update done." "post divider update done,post divider update on progress" rbitfld.long 0x0 30. "PRE_BUSY,ck gen ip slice pre_div busy status. indicate pre divider update status. 1: pre divider update on progress. 0: pre divider update done." "pre divider update done,pre divider update on progress" newline bitfld.long 0x0 28. "CG_EN_STATUS,clock gating enable status indicate CG_EN change doen since CG_EN is asynchronous to ip slice this bit indicate the CG_EN is received(active) in ip slice. when you change CG_EN you need to read this bit after that to make sure CG_EN is.." "0,1" newline hexmask.long.byte 0x0 10.--15. 1. "POST_DIV_NUM,post_div num. like PRE_DIV_NUM this field can be updated on-the-fly. and ip slice frequency will be selected clock source frequency/(PRE_DIV_NUM+1)/(POST_DIV_NUM+1)" newline bitfld.long 0x0 4.--6. "PRE_DIV_NUM,pre_div_num. each ip slice have 2 dividers pre_divider and post_divider. this field can be updated on-the-fly. ip slice frequency will be selected clock source frequency/(PRE_DIV_NUM+1)/(POST_DIV_NUM+1)" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 1.--3. "CLK_SRC_SEL,clock source select. each ip slice has 8 clock source(from clock source 0 to clock source 7) clock source information are in clock table. 0: clock source 0 1: clock source 1 .... 7: clock source 7" "clock source 0,clock source 1,?,?,?,?,?,clock source 7" bitfld.long 0x0 0. "CG_EN,clock gating enable. control the gating cell after ip slice 8-1 clock mux. 1: clock not gated. 0: clock gated. clock need to be gated before changing clock source. eg. if you want to change clock source from source 0 to source 1 you need to follow.." "clock gated,clock not gated" repeat.end repeat 2. (list 0x0 0x1 )(list 0x0 0x8 ) group.long ($2+0x200)++0x3 line.long 0x0 "CKGEN_BUS_SLICE_CTL_$1,bus slice control reg" rbitfld.long 0x0 31. "POST_BUSY,ck gen bus slice post_div busy status. indicate post divider update status. 1: post divider update on progress. 0: post divider update done." "post divider update done,post divider update on progress" rbitfld.long 0x0 30. "PRE_BUSY_A,ck gen bus slice pre_div_a busy status. indicate pre divider a update status. 1: pre divider a update on progress. 0: pre divider a update done." "pre divider a update done,pre divider a update on progress" newline rbitfld.long 0x0 29. "PRE_BUSY_B,ck gen bus slice pre_div_b busy. indicate pre divider b update status. 1: pre divider b update on progress. 0: pre divider b update done." "pre divider b update done,pre divider b update on progress" bitfld.long 0x0 28. "CG_EN_A_STATUS,clock gating enable a status indicate CG_EN_A change doen. since CG_EN_A is asynchronous to bus slice this bit indicate the CG_EN_A is received(active) in bus slice. when you change CG_EN_A you need to read this bit after that to make.." "0,1" newline bitfld.long 0x0 27. "CG_EN_B_STATUS,clock gating enable b status indicate CG_EN_B change doen. since CG_EN_B is asynchronous to bus slice this bit indicate the CG_EN_B is received(active) in bus slice. when you change CG_EN_B you need to read this bit after that to make.." "0,1" newline bitfld.long 0x0 20.--22. "PRE_DIV_NUM_B,pre_div_b num. each bus slice have 3 dividers pre_divider_a pre_divider_b and post_divider. this field can be updated on-the-fly. bus slice frequency will be selected clock source frequency/(PRE_DIV_NUM+1)/(POST_DIV_NUM+1). in which.." "0,1,2,3,4,5,6,7" bitfld.long 0x0 17.--19. "CLK_SRC_SEL_B,path b clock source select. each path in bus slice has 8 clock source(from clock source 0 to clock source 7 and path a and path b clock sources are totally the same) clock source information are in clock table. 0: clock source 0 1: clock.." "clock source 0,clock source 1,?,?,?,?,?,clock source 7" newline bitfld.long 0x0 16. "CG_EN_B,path b clock gating enable. control the gating cell after bus slice path b 8-1 clock mux. 1: clock not gated. 0: clock gated. clock need to be gated before changing clock source. eg. if you want to change clock source from source 0 to source 1.." "clock gated,clock not gated" hexmask.long.byte 0x0 10.--15. 1. "POST_DIV_NUM,post_div num. each bus slice have 3 dividers pre_divider_a pre_divider_b and post_divider. this field can be updated on-the-fly. bus slice frequency will be selected clock source frequency/(PRE_DIV_NUM+1)/(POST_DIV_NUM+1). in which.." newline bitfld.long 0x0 9. "A_B_SEL,select between path a and path b clock source. 0: path a is selected. 1: path b is selected. this can be changed on-the-fly. please make sure both path a frequency and path b frequency are within spec." "path a is selected,path b is selected" newline bitfld.long 0x0 4.--6. "PRE_DIV_NUM_A,pre_div_a num. each bus slice have 3 dividers pre_divider_a pre_divider_b and post_divider. this field can be updated on-the-fly. bus slice frequency will be selected clock source frequency/(PRE_DIV_NUM+1)/(POST_DIV_NUM+1). in which.." "0,1,2,3,4,5,6,7" bitfld.long 0x0 1.--3. "CLK_SRC_SEL_A,path a clock source select. each path in bus slice has 8 clock source(from clock source 0 to clock source 7 and path a and path b clock sources are totally the same) clock source information are in clock table. 0: clock source 0 1: clock.." "clock source 0,clock source 1,?,?,?,?,?,clock source 7" newline bitfld.long 0x0 0. "CG_EN_A,path a clock gating enable. control the gating cell after bus slice path a 8-1 clock mux. 1: clock not gated. 0: clock gated. clock need to be gated before changing clock source. eg. if you want to change clock source from source 0 to source 1.." "clock gated,clock not gated" repeat.end repeat 2. (list 0x0 0x1 )(list 0x0 0x8 ) group.long ($2+0x204)++0x3 line.long 0x0 "CKGEN_BUS_SLICE_GASKET_$1,bus slice gasket control" rbitfld.long 0x0 31. "DIV_M_BUSY,clock/m divider busy status. indicate clock/m divider update status. 1: clock/m divider update on progress. 0: clock/m divider update done." "clock/m divider update done,clock/m divider update on progress" rbitfld.long 0x0 30. "DIV_N_BUSY,clock/n divider busy status. indicate clock/n divider update status. 1: clock/n divider update on progress. 0: clock/n divider update done." "clock/n divider update done,clock/n divider update on progress" newline rbitfld.long 0x0 29. "DIV_P_BUSY,clock/p divider busy status. indicate clock/p divider update status. 1: clock/p divider update on progress. 0: clock/p divider update done." "clock/p divider update done,clock/p divider update on progress" rbitfld.long 0x0 28. "DIV_Q_BUSY,clock/q divider busy status. indicate clock/q divider update status. 1: clock/q divider update on progress. 0: clock/q divider update done." "clock/q divider update done,clock/q divider update on progress" newline bitfld.long 0x0 9.--11. "M_DIV_NUM,divider number for clock/m. this field can be updated on-the-fly. and bus slice gasket m frequency will be the corresponding bus clock frequency/(M_DIV_NUM+1)" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 6.--8. "N_DIV_NUM,divider number for clock/n this field can be updated on-the-fly. and bus slice gasket m frequency will be the corresponding bus clock frequency/(N_DIV_NUM+1)" "0,1,2,3,4,5,6,7" bitfld.long 0x0 3.--5. "P_DIV_NUM,divider number for clock/p this field can be updated on-the-fly. and bus slice gasket m frequency will be the corresponding bus clock frequency/(P_DIV_NUM+1)" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 0.--2. "Q_DIV_NUM,divider number for clock/q this field can be updated on-the-fly. and bus slice gasket m frequency will be the corresponding bus clock frequency/(Q_DIV_NUM+1)" "0,1,2,3,4,5,6,7" repeat.end repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) group.long ($2+0x300)++0x3 line.long 0x0 "CKGEN_CORE_SLICE_CTL_$1,core slice control reg" rbitfld.long 0x0 31. "POST_BUSY,ckgen core slice post_div busy status. indicate post divider update status. 1: post divider update on progress. 0: post divider update done." "post divider update done,post divider update on progress" newline bitfld.long 0x0 28. "CG_EN_A_STATUS,clock gating enable a status indicate CG_EN_A change done. since CG_EN_A is asynchronous to core slice this bit indicate the CG_EN_A is received(active) in core slice. when you change CG_EN_A you need to read this bit after that to make.." "0,1" bitfld.long 0x0 27. "CG_EN_B_STATUS,clock gating enable b status indicate CG_EN_B change doen. since CG_EN_B is asynchronous to core slice this bit indicate the CG_EN_B is received(active) in core slice. when you change CG_EN_B you need to read this bit after that to make.." "0,1" newline bitfld.long 0x0 17.--19. "CLK_SRC_SEL_B,path b clock source select. each path in bus slice has 8 clock source(from clock source 0 to clock source 7 and path a and path b clock sources are totally the same) clock source information are in clock table. 0: clock source 0 1: clock.." "clock source 0,clock source 1,?,?,?,?,?,clock source 7" newline bitfld.long 0x0 16. "CG_EN_B,path b clock gating enable. control the gating cell after core slice path b 8-1 clock mux. 1: clock not gated. 0: clock gated. clock need to be gated before changing clock source. eg. if you want to change clock source from source 0 to source 1.." "clock gated,clock not gated" hexmask.long.byte 0x0 10.--15. 1. "POST_DIV_NUM,post_div num. this field can be updated on-the-fly. core slice frequency will be selected clock source frequency/(POST_DIV_NUM+1)." newline bitfld.long 0x0 9. "A_B_SEL,select between path a and path b clock source. 0: path a is selected. 1: path b is selected. this can be changed on-the-fly. please make sure both path a frequency and path b frequency are within spec." "path a is selected,path b is selected" newline bitfld.long 0x0 1.--3. "CLK_SRC_SEL_A,path a clock source select. each path in core slice has 8 clock source(from clock source 0 to clock source 7 and path a and path b clock sources are totally the same) clock source information are in clock table. 0: clock source 0 1: clock.." "clock source 0,clock source 1,?,?,?,?,?,clock source 7" bitfld.long 0x0 0. "CG_EN_A,path a clock gating enable. control the gating cell after core slice path a 8-1 clock mux. 1: clock not gated. 0: clock gated. clock need to be gated before changing clock source. eg. if you want to change clock source from source 0 to source 1.." "clock gated,clock not gated" repeat.end repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) group.long ($2+0x400)++0x3 line.long 0x0 "CKGEN_LP_GATING_EN_$1,ip slice sw gating enable" bitfld.long 0x0 31. "CKGEN_GATING_LOCK,LOCK SW_GATING_EN/DIS 1: locked. SW_GATING_DIS/EN will keep what they are 0: unlocked SW_GATING_DIS/EN can be changed" "unlocked,locked" newline bitfld.long 0x0 1. "SW_GATING_DIS,ckgen software gating disable has higher priority than sw_gating_en. if this bit is 1'b1 then the controlled clock will be forced on(ignore the SW_GATING_EN." "0,1" bitfld.long 0x0 0. "SW_GATING_EN,ckgen software gating enable. control the gating cell IP clock in most IPs have different gating cells you can refer to clock gating control table. 1: clock not gated. 0: clock gated." "clock gated,clock not gated" repeat.end group.long 0x600++0x3 line.long 0x0 "CKGEN_UUU_SLICE_0,uuu clock wrapper control" bitfld.long 0x0 31. "UUU_DBG_GATING_EN,gating enable for debug output. control the gating cell before uuu dbg divider 1: clock not gated. 0: clock gated." "clock gated,clock not gated" hexmask.long.byte 0x0 27.--30. 1. "DBG_DIV_NUM,divder number for debug output. this field can be updated on-the-fly. dbg clock frequence will be selected clk_out_0/(DBG_DIV_NUM+1)" newline bitfld.long 0x0 20. "UUU_GATING_ACK,reserved" "0,1" newline hexmask.long.byte 0x0 16.--19. 1. "UUU_SEL,for uuu wrapper clock gating control and clock source select uuu_sel[1:0]: clk_sel in uuu_clock_wrapper uuu_sel[1]: 1: clk_out_0 from pll 0: clk_out_0 from clk_m uuu_sel_[0]: 1: uuu input clock from pll 2: uuu input clock from ckgen_hpi slice.." hexmask.long.byte 0x0 12.--15. 1. "M_DIV_NUM,divider number for clock/m. this field can be updated on-the-fly. and uuu clock m frequency will be the corresponding uuu clock frequency/(M_DIV_NUM+1)" newline hexmask.long.byte 0x0 8.--11. 1. "N_DIV_NUM,divider number for clock/n. this field can be updated on-the-fly. and uuu clock m frequency will be the corresponding uuu clock frequency/(N_DIV_NUM+1)" hexmask.long.byte 0x0 4.--7. 1. "P_DIV_NUM,divider number for clock/p this field can be updated on-the-fly. and uuu clock m frequency will be the corresponding uuu clock frequency/(P_DIV_NUM+1)" newline hexmask.long.byte 0x0 0.--3. 1. "Q_DIV_NUM,divider number for clock/q this field can be updated on-the-fly. and uuu clock m frequency will be the corresponding uuu clock frequency/(Q_DIV_NUM+1)" group.long 0x700++0xF line.long 0x0 "CKGEN_IP_SLICE_DBG_CTL,ip slice debug control" hexmask.long.word 0x0 0.--15. 1. "IP_SLICE_DBG_SEL,ip slice debug clock source select. for ckgen_saf/ckgen_sec/ckgen_disp when ip clock is selected to be the debug source. this register choose debug clock source from ip_slice[0] to ip_slice[IP_SLICE_NUM] for ckgen_hpi from.." line.long 0x4 "CKGEN_BUS_SLICE_DBG_CTL,bus slice debug control" hexmask.long.word 0x4 0.--15. 1. "BUS_SLICE_DBG_SEL,bus slice debug clock source select. when bus clock is selected to be the debug source. this register choose debug clock source from bus_slice[0] to bus_slice[BUS_SLICE_NUM]" line.long 0x8 "CKGEN_CORE_SLICE_DBG_CTL,core slice debug control" hexmask.long.word 0x8 0.--15. 1. "CORE_SLICE_DBG_SEL,core slice debug clock source select. when core clock is selected to be the debug source. this register choose debug clock source from core_slice[0] to core_slice[CORE_SLICE_NUM]" line.long 0xC "CKGEN_DBG_CTL,ckgen debug control" bitfld.long 0xC 31. "DBG_CLK_DIS,disable ckgen debug function. 0: ckgen debug function enable 1: ckgen debug function disable" "ckgen debug function enable,ckgen debug function disable" bitfld.long 0xC 29.--30. "DBG_SEL,dbg clock out select: 2'b01: from bus slice clock which is controlled by CKGEN_BUS_SLICE_DBG_CTL 2'b10: from core slice clock which is controlled by CKGEN_CORE_SLICE_DBG_CTL others: from ip slice clock which is controlled by.." "?,from bus slice clock,from core slice clock,?" newline hexmask.long.word 0xC 0.--15. 1. "DBG_DIV_NUM,debug divider number only bit[3:0] are used since debug clock is monitored through pad only clock frequency less than 100MHz can be accepted. and divide the debug clock as early as possible from clock source." group.long 0x720++0x1B line.long 0x0 "CKGEN_IP_SLICE_MON_CTL,ip slice monitor control" hexmask.long.word 0x0 0.--15. 1. "IP_SLICE_MON_SEL,ip slice mon clock source select. for ckgen_saf/ckgen_sec/ckgen_disp when ip clock is selected to be the monitor source. this register choose monitor clock source from ip_slice[0] to ip_slice[IP_SLICE_NUM] for ckgen_hpi from.." line.long 0x4 "CKGEN_BUS_SLICE_MON_CTL,bus slice monitor control" hexmask.long.word 0x4 0.--15. 1. "BUS_SLICE_MON_SEL,bus slice mon clock source select. when bus clock is selected to be the monitor source. this register choose monitor clock source from bus_slice[0] to bus_slice[BUS_SLICE_NUM]" line.long 0x8 "CKGEN_CORE_SLICE_MON_CTL,core slice monitor control" hexmask.long.word 0x8 0.--15. 1. "CORE_SLICE_MON_SEL,core slice monitor clock source select. when core clock is selected to be the monitor source. this register choose monitor clock source from core_slice[0] to core_slice[CORE_SLICE_NUM]" line.long 0xC "CKGEN_MON_CTL,ckgen monitor control" bitfld.long 0xC 31. "MON_CLK_DIS,disable ckgen monitor function. 0: ckgen monitor function enable 1: ckgen monitor function disable" "ckgen monitor function enable,ckgen monitor function disable" bitfld.long 0xC 29.--30. "MON_SEL,monitor clock out select: 2'b01: from bus slice clock which is controlled by CKGEN_BUS_SLICE_MON_CTL 2'b10: from core slice clock which is controlled by CKGEN_CORE_SLICE_MON_CTL others: from ip slice clock which is controlled by.." "?,from bus slice clock,from core slice clock,?" newline bitfld.long 0xC 28. "MON_VAL_UPD_EN,latch monitor value enable 1: latch 0: latch disable" "latch disable,latch" rbitfld.long 0xC 27. "FREQ_RDY_STA,frequency calculate ready indicator." "0,1" newline rbitfld.long 0xC 26. "MON_CLK_DIS_STA,mon_clk_dis status. need to check after program mon_clk_dis" "0,1" bitfld.long 0xC 25. "CLK_SLOW_SRC,clk slow source select. this is the referenc clock source for clock monitor. 1: 32k 0: 24M" "0,1" newline rbitfld.long 0xC 16. "MON_DIV_BUSY,monitor divider update busy. indicate monitor divider update status. 1: monitor divider update on progress. 0: monitor divider update done." "monitor divider update done,monitor divider update on progress" newline hexmask.long.word 0xC 0.--15. 1. "MON_DIV_NUM,monitor divider number only bit[3:0] are used this field can be changed on-the-fly." line.long 0x10 "CKGEN_MON_MAX_FREQ,clock monitor max freq value" hexmask.long.word 0x10 0.--15. 1. "MON_MAX_FREQ,monitor clock max freq value. monitored max freq. this is only for debug" line.long 0x14 "CKGEN_MON_AVE_FREQ,clock monitor average freq value" hexmask.long.word 0x14 0.--15. 1. "MON_AVE_FREQ,monitor clock average freq value. the monitored clock frequency should be MON_AVE_FREQ * CLK_SLOW_SRC" line.long 0x18 "CKGEN_MON_MIN_FREQ,clock monitor min freq value" hexmask.long.word 0x18 0.--15. 1. "MON_MIN_FREQ,monitor clock mininum freq value. monitored min freq. this is only for debug" rgroup.long 0x73C++0x7 line.long 0x0 "CKGEN_MON_MAX_DUTY,clock monitor max high duty value" hexmask.long.word 0x0 16.--31. 1. "MON_MAX_PERIOD,monitor clock max period corresponding to the max high level value" hexmask.long.word 0x0 0.--15. 1. "MON_MAX_HIGH,monitor clock max high level value" line.long 0x4 "CKGEN_MON_MIN_DUTY,clock monitor min duty value" hexmask.long.word 0x4 16.--31. 1. "MON_MIN_PERIOD,monitor clock min period corresponding to the min high level value" hexmask.long.word 0x4 0.--15. 1. "MON_MIN_HIGH,monitor clock min high level value" tree.end tree "CKGEN_DISP" base ad:0x36200000 repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) group.long ($2)++0x3 line.long 0x0 "CKGEN_IP_SLICE_CTL_$1,ip slice control reg" rbitfld.long 0x0 31. "POST_BUSY,ck gen ip slice post_div busy status. indicate post divider update status. 1: post divider update on progress. 0: post divider update done." "post divider update done,post divider update on progress" rbitfld.long 0x0 30. "PRE_BUSY,ck gen ip slice pre_div busy status. indicate pre divider update status. 1: pre divider update on progress. 0: pre divider update done." "pre divider update done,pre divider update on progress" newline bitfld.long 0x0 28. "CG_EN_STATUS,clock gating enable status indicate CG_EN change doen since CG_EN is asynchronous to ip slice this bit indicate the CG_EN is received(active) in ip slice. when you change CG_EN you need to read this bit after that to make sure CG_EN is.." "0,1" newline hexmask.long.byte 0x0 10.--15. 1. "POST_DIV_NUM,post_div num. like PRE_DIV_NUM this field can be updated on-the-fly. and ip slice frequency will be selected clock source frequency/(PRE_DIV_NUM+1)/(POST_DIV_NUM+1)" newline bitfld.long 0x0 4.--6. "PRE_DIV_NUM,pre_div_num. each ip slice have 2 dividers pre_divider and post_divider. this field can be updated on-the-fly. ip slice frequency will be selected clock source frequency/(PRE_DIV_NUM+1)/(POST_DIV_NUM+1)" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 1.--3. "CLK_SRC_SEL,clock source select. each ip slice has 8 clock source(from clock source 0 to clock source 7) clock source information are in clock table. 0: clock source 0 1: clock source 1 .... 7: clock source 7" "clock source 0,clock source 1,?,?,?,?,?,clock source 7" bitfld.long 0x0 0. "CG_EN,clock gating enable. control the gating cell after ip slice 8-1 clock mux. 1: clock not gated. 0: clock gated. clock need to be gated before changing clock source. eg. if you want to change clock source from source 0 to source 1 you need to follow.." "clock gated,clock not gated" repeat.end repeat 2. (list 0x0 0x1 )(list 0x0 0x8 ) group.long ($2+0x200)++0x3 line.long 0x0 "CKGEN_BUS_SLICE_CTL_$1,bus slice control reg" rbitfld.long 0x0 31. "POST_BUSY,ck gen bus slice post_div busy status. indicate post divider update status. 1: post divider update on progress. 0: post divider update done." "post divider update done,post divider update on progress" rbitfld.long 0x0 30. "PRE_BUSY_A,ck gen bus slice pre_div_a busy status. indicate pre divider a update status. 1: pre divider a update on progress. 0: pre divider a update done." "pre divider a update done,pre divider a update on progress" newline rbitfld.long 0x0 29. "PRE_BUSY_B,ck gen bus slice pre_div_b busy. indicate pre divider b update status. 1: pre divider b update on progress. 0: pre divider b update done." "pre divider b update done,pre divider b update on progress" bitfld.long 0x0 28. "CG_EN_A_STATUS,clock gating enable a status indicate CG_EN_A change doen. since CG_EN_A is asynchronous to bus slice this bit indicate the CG_EN_A is received(active) in bus slice. when you change CG_EN_A you need to read this bit after that to make.." "0,1" newline bitfld.long 0x0 27. "CG_EN_B_STATUS,clock gating enable b status indicate CG_EN_B change doen. since CG_EN_B is asynchronous to bus slice this bit indicate the CG_EN_B is received(active) in bus slice. when you change CG_EN_B you need to read this bit after that to make.." "0,1" newline bitfld.long 0x0 20.--22. "PRE_DIV_NUM_B,pre_div_b num. each bus slice have 3 dividers pre_divider_a pre_divider_b and post_divider. this field can be updated on-the-fly. bus slice frequency will be selected clock source frequency/(PRE_DIV_NUM+1)/(POST_DIV_NUM+1). in which.." "0,1,2,3,4,5,6,7" bitfld.long 0x0 17.--19. "CLK_SRC_SEL_B,path b clock source select. each path in bus slice has 8 clock source(from clock source 0 to clock source 7 and path a and path b clock sources are totally the same) clock source information are in clock table. 0: clock source 0 1: clock.." "clock source 0,clock source 1,?,?,?,?,?,clock source 7" newline bitfld.long 0x0 16. "CG_EN_B,path b clock gating enable. control the gating cell after bus slice path b 8-1 clock mux. 1: clock not gated. 0: clock gated. clock need to be gated before changing clock source. eg. if you want to change clock source from source 0 to source 1.." "clock gated,clock not gated" hexmask.long.byte 0x0 10.--15. 1. "POST_DIV_NUM,post_div num. each bus slice have 3 dividers pre_divider_a pre_divider_b and post_divider. this field can be updated on-the-fly. bus slice frequency will be selected clock source frequency/(PRE_DIV_NUM+1)/(POST_DIV_NUM+1). in which.." newline bitfld.long 0x0 9. "A_B_SEL,select between path a and path b clock source. 0: path a is selected. 1: path b is selected. this can be changed on-the-fly. please make sure both path a frequency and path b frequency are within spec." "path a is selected,path b is selected" newline bitfld.long 0x0 4.--6. "PRE_DIV_NUM_A,pre_div_a num. each bus slice have 3 dividers pre_divider_a pre_divider_b and post_divider. this field can be updated on-the-fly. bus slice frequency will be selected clock source frequency/(PRE_DIV_NUM+1)/(POST_DIV_NUM+1). in which.." "0,1,2,3,4,5,6,7" bitfld.long 0x0 1.--3. "CLK_SRC_SEL_A,path a clock source select. each path in bus slice has 8 clock source(from clock source 0 to clock source 7 and path a and path b clock sources are totally the same) clock source information are in clock table. 0: clock source 0 1: clock.." "clock source 0,clock source 1,?,?,?,?,?,clock source 7" newline bitfld.long 0x0 0. "CG_EN_A,path a clock gating enable. control the gating cell after bus slice path a 8-1 clock mux. 1: clock not gated. 0: clock gated. clock need to be gated before changing clock source. eg. if you want to change clock source from source 0 to source 1.." "clock gated,clock not gated" repeat.end repeat 2. (list 0x0 0x1 )(list 0x0 0x8 ) group.long ($2+0x204)++0x3 line.long 0x0 "CKGEN_BUS_SLICE_GASKET_$1,bus slice gasket control" rbitfld.long 0x0 31. "DIV_M_BUSY,clock/m divider busy status. indicate clock/m divider update status. 1: clock/m divider update on progress. 0: clock/m divider update done." "clock/m divider update done,clock/m divider update on progress" rbitfld.long 0x0 30. "DIV_N_BUSY,clock/n divider busy status. indicate clock/n divider update status. 1: clock/n divider update on progress. 0: clock/n divider update done." "clock/n divider update done,clock/n divider update on progress" newline rbitfld.long 0x0 29. "DIV_P_BUSY,clock/p divider busy status. indicate clock/p divider update status. 1: clock/p divider update on progress. 0: clock/p divider update done." "clock/p divider update done,clock/p divider update on progress" rbitfld.long 0x0 28. "DIV_Q_BUSY,clock/q divider busy status. indicate clock/q divider update status. 1: clock/q divider update on progress. 0: clock/q divider update done." "clock/q divider update done,clock/q divider update on progress" newline bitfld.long 0x0 9.--11. "M_DIV_NUM,divider number for clock/m. this field can be updated on-the-fly. and bus slice gasket m frequency will be the corresponding bus clock frequency/(M_DIV_NUM+1)" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 6.--8. "N_DIV_NUM,divider number for clock/n this field can be updated on-the-fly. and bus slice gasket m frequency will be the corresponding bus clock frequency/(N_DIV_NUM+1)" "0,1,2,3,4,5,6,7" bitfld.long 0x0 3.--5. "P_DIV_NUM,divider number for clock/p this field can be updated on-the-fly. and bus slice gasket m frequency will be the corresponding bus clock frequency/(P_DIV_NUM+1)" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 0.--2. "Q_DIV_NUM,divider number for clock/q this field can be updated on-the-fly. and bus slice gasket m frequency will be the corresponding bus clock frequency/(Q_DIV_NUM+1)" "0,1,2,3,4,5,6,7" repeat.end repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) group.long ($2+0x300)++0x3 line.long 0x0 "CKGEN_CORE_SLICE_CTL_$1,core slice control reg" rbitfld.long 0x0 31. "POST_BUSY,ckgen core slice post_div busy status. indicate post divider update status. 1: post divider update on progress. 0: post divider update done." "post divider update done,post divider update on progress" newline bitfld.long 0x0 28. "CG_EN_A_STATUS,clock gating enable a status indicate CG_EN_A change done. since CG_EN_A is asynchronous to core slice this bit indicate the CG_EN_A is received(active) in core slice. when you change CG_EN_A you need to read this bit after that to make.." "0,1" bitfld.long 0x0 27. "CG_EN_B_STATUS,clock gating enable b status indicate CG_EN_B change doen. since CG_EN_B is asynchronous to core slice this bit indicate the CG_EN_B is received(active) in core slice. when you change CG_EN_B you need to read this bit after that to make.." "0,1" newline bitfld.long 0x0 17.--19. "CLK_SRC_SEL_B,path b clock source select. each path in bus slice has 8 clock source(from clock source 0 to clock source 7 and path a and path b clock sources are totally the same) clock source information are in clock table. 0: clock source 0 1: clock.." "clock source 0,clock source 1,?,?,?,?,?,clock source 7" newline bitfld.long 0x0 16. "CG_EN_B,path b clock gating enable. control the gating cell after core slice path b 8-1 clock mux. 1: clock not gated. 0: clock gated. clock need to be gated before changing clock source. eg. if you want to change clock source from source 0 to source 1.." "clock gated,clock not gated" hexmask.long.byte 0x0 10.--15. 1. "POST_DIV_NUM,post_div num. this field can be updated on-the-fly. core slice frequency will be selected clock source frequency/(POST_DIV_NUM+1)." newline bitfld.long 0x0 9. "A_B_SEL,select between path a and path b clock source. 0: path a is selected. 1: path b is selected. this can be changed on-the-fly. please make sure both path a frequency and path b frequency are within spec." "path a is selected,path b is selected" newline bitfld.long 0x0 1.--3. "CLK_SRC_SEL_A,path a clock source select. each path in core slice has 8 clock source(from clock source 0 to clock source 7 and path a and path b clock sources are totally the same) clock source information are in clock table. 0: clock source 0 1: clock.." "clock source 0,clock source 1,?,?,?,?,?,clock source 7" bitfld.long 0x0 0. "CG_EN_A,path a clock gating enable. control the gating cell after core slice path a 8-1 clock mux. 1: clock not gated. 0: clock gated. clock need to be gated before changing clock source. eg. if you want to change clock source from source 0 to source 1.." "clock gated,clock not gated" repeat.end repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) group.long ($2+0x400)++0x3 line.long 0x0 "CKGEN_LP_GATING_EN_$1,ip slice sw gating enable" bitfld.long 0x0 31. "CKGEN_GATING_LOCK,LOCK SW_GATING_EN/DIS 1: locked. SW_GATING_DIS/EN will keep what they are 0: unlocked SW_GATING_DIS/EN can be changed" "unlocked,locked" newline bitfld.long 0x0 1. "SW_GATING_DIS,ckgen software gating disable has higher priority than sw_gating_en. if this bit is 1'b1 then the controlled clock will be forced on(ignore the SW_GATING_EN." "0,1" bitfld.long 0x0 0. "SW_GATING_EN,ckgen software gating enable. control the gating cell IP clock in most IPs have different gating cells you can refer to clock gating control table. 1: clock not gated. 0: clock gated." "clock gated,clock not gated" repeat.end group.long 0x600++0x3 line.long 0x0 "CKGEN_UUU_SLICE_0,uuu clock wrapper control" bitfld.long 0x0 31. "UUU_DBG_GATING_EN,gating enable for debug output. control the gating cell before uuu dbg divider 1: clock not gated. 0: clock gated." "clock gated,clock not gated" hexmask.long.byte 0x0 27.--30. 1. "DBG_DIV_NUM,divder number for debug output. this field can be updated on-the-fly. dbg clock frequence will be selected clk_out_0/(DBG_DIV_NUM+1)" newline bitfld.long 0x0 20. "UUU_GATING_ACK,reserved" "0,1" newline hexmask.long.byte 0x0 16.--19. 1. "UUU_SEL,for uuu wrapper clock gating control and clock source select uuu_sel[1:0]: clk_sel in uuu_clock_wrapper uuu_sel[1]: 1: clk_out_0 from pll 0: clk_out_0 from clk_m uuu_sel_[0]: 1: uuu input clock from pll 2: uuu input clock from ckgen_hpi slice.." hexmask.long.byte 0x0 12.--15. 1. "M_DIV_NUM,divider number for clock/m. this field can be updated on-the-fly. and uuu clock m frequency will be the corresponding uuu clock frequency/(M_DIV_NUM+1)" newline hexmask.long.byte 0x0 8.--11. 1. "N_DIV_NUM,divider number for clock/n. this field can be updated on-the-fly. and uuu clock m frequency will be the corresponding uuu clock frequency/(N_DIV_NUM+1)" hexmask.long.byte 0x0 4.--7. 1. "P_DIV_NUM,divider number for clock/p this field can be updated on-the-fly. and uuu clock m frequency will be the corresponding uuu clock frequency/(P_DIV_NUM+1)" newline hexmask.long.byte 0x0 0.--3. 1. "Q_DIV_NUM,divider number for clock/q this field can be updated on-the-fly. and uuu clock m frequency will be the corresponding uuu clock frequency/(Q_DIV_NUM+1)" group.long 0x700++0xF line.long 0x0 "CKGEN_IP_SLICE_DBG_CTL,ip slice debug control" hexmask.long.word 0x0 0.--15. 1. "IP_SLICE_DBG_SEL,ip slice debug clock source select. for ckgen_saf/ckgen_sec/ckgen_disp when ip clock is selected to be the debug source. this register choose debug clock source from ip_slice[0] to ip_slice[IP_SLICE_NUM] for ckgen_hpi from.." line.long 0x4 "CKGEN_BUS_SLICE_DBG_CTL,bus slice debug control" hexmask.long.word 0x4 0.--15. 1. "BUS_SLICE_DBG_SEL,bus slice debug clock source select. when bus clock is selected to be the debug source. this register choose debug clock source from bus_slice[0] to bus_slice[BUS_SLICE_NUM]" line.long 0x8 "CKGEN_CORE_SLICE_DBG_CTL,core slice debug control" hexmask.long.word 0x8 0.--15. 1. "CORE_SLICE_DBG_SEL,core slice debug clock source select. when core clock is selected to be the debug source. this register choose debug clock source from core_slice[0] to core_slice[CORE_SLICE_NUM]" line.long 0xC "CKGEN_DBG_CTL,ckgen debug control" bitfld.long 0xC 31. "DBG_CLK_DIS,disable ckgen debug function. 0: ckgen debug function enable 1: ckgen debug function disable" "ckgen debug function enable,ckgen debug function disable" bitfld.long 0xC 29.--30. "DBG_SEL,dbg clock out select: 2'b01: from bus slice clock which is controlled by CKGEN_BUS_SLICE_DBG_CTL 2'b10: from core slice clock which is controlled by CKGEN_CORE_SLICE_DBG_CTL others: from ip slice clock which is controlled by.." "?,from bus slice clock,from core slice clock,?" newline hexmask.long.word 0xC 0.--15. 1. "DBG_DIV_NUM,debug divider number only bit[3:0] are used since debug clock is monitored through pad only clock frequency less than 100MHz can be accepted. and divide the debug clock as early as possible from clock source." group.long 0x720++0x1B line.long 0x0 "CKGEN_IP_SLICE_MON_CTL,ip slice monitor control" hexmask.long.word 0x0 0.--15. 1. "IP_SLICE_MON_SEL,ip slice mon clock source select. for ckgen_saf/ckgen_sec/ckgen_disp when ip clock is selected to be the monitor source. this register choose monitor clock source from ip_slice[0] to ip_slice[IP_SLICE_NUM] for ckgen_hpi from.." line.long 0x4 "CKGEN_BUS_SLICE_MON_CTL,bus slice monitor control" hexmask.long.word 0x4 0.--15. 1. "BUS_SLICE_MON_SEL,bus slice mon clock source select. when bus clock is selected to be the monitor source. this register choose monitor clock source from bus_slice[0] to bus_slice[BUS_SLICE_NUM]" line.long 0x8 "CKGEN_CORE_SLICE_MON_CTL,core slice monitor control" hexmask.long.word 0x8 0.--15. 1. "CORE_SLICE_MON_SEL,core slice monitor clock source select. when core clock is selected to be the monitor source. this register choose monitor clock source from core_slice[0] to core_slice[CORE_SLICE_NUM]" line.long 0xC "CKGEN_MON_CTL,ckgen monitor control" bitfld.long 0xC 31. "MON_CLK_DIS,disable ckgen monitor function. 0: ckgen monitor function enable 1: ckgen monitor function disable" "ckgen monitor function enable,ckgen monitor function disable" bitfld.long 0xC 29.--30. "MON_SEL,monitor clock out select: 2'b01: from bus slice clock which is controlled by CKGEN_BUS_SLICE_MON_CTL 2'b10: from core slice clock which is controlled by CKGEN_CORE_SLICE_MON_CTL others: from ip slice clock which is controlled by.." "?,from bus slice clock,from core slice clock,?" newline bitfld.long 0xC 28. "MON_VAL_UPD_EN,latch monitor value enable 1: latch 0: latch disable" "latch disable,latch" rbitfld.long 0xC 27. "FREQ_RDY_STA,frequency calculate ready indicator." "0,1" newline rbitfld.long 0xC 26. "MON_CLK_DIS_STA,mon_clk_dis status. need to check after program mon_clk_dis" "0,1" bitfld.long 0xC 25. "CLK_SLOW_SRC,clk slow source select. this is the referenc clock source for clock monitor. 1: 32k 0: 24M" "0,1" newline rbitfld.long 0xC 16. "MON_DIV_BUSY,monitor divider update busy. indicate monitor divider update status. 1: monitor divider update on progress. 0: monitor divider update done." "monitor divider update done,monitor divider update on progress" newline hexmask.long.word 0xC 0.--15. 1. "MON_DIV_NUM,monitor divider number only bit[3:0] are used this field can be changed on-the-fly." line.long 0x10 "CKGEN_MON_MAX_FREQ,clock monitor max freq value" hexmask.long.word 0x10 0.--15. 1. "MON_MAX_FREQ,monitor clock max freq value. monitored max freq. this is only for debug" line.long 0x14 "CKGEN_MON_AVE_FREQ,clock monitor average freq value" hexmask.long.word 0x14 0.--15. 1. "MON_AVE_FREQ,monitor clock average freq value. the monitored clock frequency should be MON_AVE_FREQ * CLK_SLOW_SRC" line.long 0x18 "CKGEN_MON_MIN_FREQ,clock monitor min freq value" hexmask.long.word 0x18 0.--15. 1. "MON_MIN_FREQ,monitor clock mininum freq value. monitored min freq. this is only for debug" rgroup.long 0x73C++0x7 line.long 0x0 "CKGEN_MON_MAX_DUTY,clock monitor max high duty value" hexmask.long.word 0x0 16.--31. 1. "MON_MAX_PERIOD,monitor clock max period corresponding to the max high level value" hexmask.long.word 0x0 0.--15. 1. "MON_MAX_HIGH,monitor clock max high level value" line.long 0x4 "CKGEN_MON_MIN_DUTY,clock monitor min duty value" hexmask.long.word 0x4 16.--31. 1. "MON_MIN_PERIOD,monitor clock min period corresponding to the min high level value" hexmask.long.word 0x4 0.--15. 1. "MON_MIN_HIGH,monitor clock min high level value" tree.end tree "CKGEN_AP" base ad:0x38000000 repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) group.long ($2)++0x3 line.long 0x0 "CKGEN_IP_SLICE_CTL_$1,ip slice control reg" rbitfld.long 0x0 31. "POST_BUSY,ck gen ip slice post_div busy status. indicate post divider update status. 1: post divider update on progress. 0: post divider update done." "post divider update done,post divider update on progress" rbitfld.long 0x0 30. "PRE_BUSY,ck gen ip slice pre_div busy status. indicate pre divider update status. 1: pre divider update on progress. 0: pre divider update done." "pre divider update done,pre divider update on progress" newline bitfld.long 0x0 28. "CG_EN_STATUS,clock gating enable status indicate CG_EN change doen since CG_EN is asynchronous to ip slice this bit indicate the CG_EN is received(active) in ip slice. when you change CG_EN you need to read this bit after that to make sure CG_EN is.." "0,1" newline hexmask.long.byte 0x0 10.--15. 1. "POST_DIV_NUM,post_div num. like PRE_DIV_NUM this field can be updated on-the-fly. and ip slice frequency will be selected clock source frequency/(PRE_DIV_NUM+1)/(POST_DIV_NUM+1)" newline bitfld.long 0x0 4.--6. "PRE_DIV_NUM,pre_div_num. each ip slice have 2 dividers pre_divider and post_divider. this field can be updated on-the-fly. ip slice frequency will be selected clock source frequency/(PRE_DIV_NUM+1)/(POST_DIV_NUM+1)" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 1.--3. "CLK_SRC_SEL,clock source select. each ip slice has 8 clock source(from clock source 0 to clock source 7) clock source information are in clock table. 0: clock source 0 1: clock source 1 .... 7: clock source 7" "clock source 0,clock source 1,?,?,?,?,?,clock source 7" bitfld.long 0x0 0. "CG_EN,clock gating enable. control the gating cell after ip slice 8-1 clock mux. 1: clock not gated. 0: clock gated. clock need to be gated before changing clock source. eg. if you want to change clock source from source 0 to source 1 you need to follow.." "clock gated,clock not gated" repeat.end repeat 2. (list 0x0 0x1 )(list 0x0 0x8 ) group.long ($2+0x200)++0x3 line.long 0x0 "CKGEN_BUS_SLICE_CTL_$1,bus slice control reg" rbitfld.long 0x0 31. "POST_BUSY,ck gen bus slice post_div busy status. indicate post divider update status. 1: post divider update on progress. 0: post divider update done." "post divider update done,post divider update on progress" rbitfld.long 0x0 30. "PRE_BUSY_A,ck gen bus slice pre_div_a busy status. indicate pre divider a update status. 1: pre divider a update on progress. 0: pre divider a update done." "pre divider a update done,pre divider a update on progress" newline rbitfld.long 0x0 29. "PRE_BUSY_B,ck gen bus slice pre_div_b busy. indicate pre divider b update status. 1: pre divider b update on progress. 0: pre divider b update done." "pre divider b update done,pre divider b update on progress" bitfld.long 0x0 28. "CG_EN_A_STATUS,clock gating enable a status indicate CG_EN_A change doen. since CG_EN_A is asynchronous to bus slice this bit indicate the CG_EN_A is received(active) in bus slice. when you change CG_EN_A you need to read this bit after that to make.." "0,1" newline bitfld.long 0x0 27. "CG_EN_B_STATUS,clock gating enable b status indicate CG_EN_B change doen. since CG_EN_B is asynchronous to bus slice this bit indicate the CG_EN_B is received(active) in bus slice. when you change CG_EN_B you need to read this bit after that to make.." "0,1" newline bitfld.long 0x0 20.--22. "PRE_DIV_NUM_B,pre_div_b num. each bus slice have 3 dividers pre_divider_a pre_divider_b and post_divider. this field can be updated on-the-fly. bus slice frequency will be selected clock source frequency/(PRE_DIV_NUM+1)/(POST_DIV_NUM+1). in which.." "0,1,2,3,4,5,6,7" bitfld.long 0x0 17.--19. "CLK_SRC_SEL_B,path b clock source select. each path in bus slice has 8 clock source(from clock source 0 to clock source 7 and path a and path b clock sources are totally the same) clock source information are in clock table. 0: clock source 0 1: clock.." "clock source 0,clock source 1,?,?,?,?,?,clock source 7" newline bitfld.long 0x0 16. "CG_EN_B,path b clock gating enable. control the gating cell after bus slice path b 8-1 clock mux. 1: clock not gated. 0: clock gated. clock need to be gated before changing clock source. eg. if you want to change clock source from source 0 to source 1.." "clock gated,clock not gated" hexmask.long.byte 0x0 10.--15. 1. "POST_DIV_NUM,post_div num. each bus slice have 3 dividers pre_divider_a pre_divider_b and post_divider. this field can be updated on-the-fly. bus slice frequency will be selected clock source frequency/(PRE_DIV_NUM+1)/(POST_DIV_NUM+1). in which.." newline bitfld.long 0x0 9. "A_B_SEL,select between path a and path b clock source. 0: path a is selected. 1: path b is selected. this can be changed on-the-fly. please make sure both path a frequency and path b frequency are within spec." "path a is selected,path b is selected" newline bitfld.long 0x0 4.--6. "PRE_DIV_NUM_A,pre_div_a num. each bus slice have 3 dividers pre_divider_a pre_divider_b and post_divider. this field can be updated on-the-fly. bus slice frequency will be selected clock source frequency/(PRE_DIV_NUM+1)/(POST_DIV_NUM+1). in which.." "0,1,2,3,4,5,6,7" bitfld.long 0x0 1.--3. "CLK_SRC_SEL_A,path a clock source select. each path in bus slice has 8 clock source(from clock source 0 to clock source 7 and path a and path b clock sources are totally the same) clock source information are in clock table. 0: clock source 0 1: clock.." "clock source 0,clock source 1,?,?,?,?,?,clock source 7" newline bitfld.long 0x0 0. "CG_EN_A,path a clock gating enable. control the gating cell after bus slice path a 8-1 clock mux. 1: clock not gated. 0: clock gated. clock need to be gated before changing clock source. eg. if you want to change clock source from source 0 to source 1.." "clock gated,clock not gated" repeat.end repeat 2. (list 0x0 0x1 )(list 0x0 0x8 ) group.long ($2+0x204)++0x3 line.long 0x0 "CKGEN_BUS_SLICE_GASKET_$1,bus slice gasket control" rbitfld.long 0x0 31. "DIV_M_BUSY,clock/m divider busy status. indicate clock/m divider update status. 1: clock/m divider update on progress. 0: clock/m divider update done." "clock/m divider update done,clock/m divider update on progress" rbitfld.long 0x0 30. "DIV_N_BUSY,clock/n divider busy status. indicate clock/n divider update status. 1: clock/n divider update on progress. 0: clock/n divider update done." "clock/n divider update done,clock/n divider update on progress" newline rbitfld.long 0x0 29. "DIV_P_BUSY,clock/p divider busy status. indicate clock/p divider update status. 1: clock/p divider update on progress. 0: clock/p divider update done." "clock/p divider update done,clock/p divider update on progress" rbitfld.long 0x0 28. "DIV_Q_BUSY,clock/q divider busy status. indicate clock/q divider update status. 1: clock/q divider update on progress. 0: clock/q divider update done." "clock/q divider update done,clock/q divider update on progress" newline bitfld.long 0x0 9.--11. "M_DIV_NUM,divider number for clock/m. this field can be updated on-the-fly. and bus slice gasket m frequency will be the corresponding bus clock frequency/(M_DIV_NUM+1)" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 6.--8. "N_DIV_NUM,divider number for clock/n this field can be updated on-the-fly. and bus slice gasket m frequency will be the corresponding bus clock frequency/(N_DIV_NUM+1)" "0,1,2,3,4,5,6,7" bitfld.long 0x0 3.--5. "P_DIV_NUM,divider number for clock/p this field can be updated on-the-fly. and bus slice gasket m frequency will be the corresponding bus clock frequency/(P_DIV_NUM+1)" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 0.--2. "Q_DIV_NUM,divider number for clock/q this field can be updated on-the-fly. and bus slice gasket m frequency will be the corresponding bus clock frequency/(Q_DIV_NUM+1)" "0,1,2,3,4,5,6,7" repeat.end repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) group.long ($2+0x300)++0x3 line.long 0x0 "CKGEN_CORE_SLICE_CTL_$1,core slice control reg" rbitfld.long 0x0 31. "POST_BUSY,ckgen core slice post_div busy status. indicate post divider update status. 1: post divider update on progress. 0: post divider update done." "post divider update done,post divider update on progress" newline bitfld.long 0x0 28. "CG_EN_A_STATUS,clock gating enable a status indicate CG_EN_A change done. since CG_EN_A is asynchronous to core slice this bit indicate the CG_EN_A is received(active) in core slice. when you change CG_EN_A you need to read this bit after that to make.." "0,1" bitfld.long 0x0 27. "CG_EN_B_STATUS,clock gating enable b status indicate CG_EN_B change doen. since CG_EN_B is asynchronous to core slice this bit indicate the CG_EN_B is received(active) in core slice. when you change CG_EN_B you need to read this bit after that to make.." "0,1" newline bitfld.long 0x0 17.--19. "CLK_SRC_SEL_B,path b clock source select. each path in bus slice has 8 clock source(from clock source 0 to clock source 7 and path a and path b clock sources are totally the same) clock source information are in clock table. 0: clock source 0 1: clock.." "clock source 0,clock source 1,?,?,?,?,?,clock source 7" newline bitfld.long 0x0 16. "CG_EN_B,path b clock gating enable. control the gating cell after core slice path b 8-1 clock mux. 1: clock not gated. 0: clock gated. clock need to be gated before changing clock source. eg. if you want to change clock source from source 0 to source 1.." "clock gated,clock not gated" hexmask.long.byte 0x0 10.--15. 1. "POST_DIV_NUM,post_div num. this field can be updated on-the-fly. core slice frequency will be selected clock source frequency/(POST_DIV_NUM+1)." newline bitfld.long 0x0 9. "A_B_SEL,select between path a and path b clock source. 0: path a is selected. 1: path b is selected. this can be changed on-the-fly. please make sure both path a frequency and path b frequency are within spec." "path a is selected,path b is selected" newline bitfld.long 0x0 1.--3. "CLK_SRC_SEL_A,path a clock source select. each path in core slice has 8 clock source(from clock source 0 to clock source 7 and path a and path b clock sources are totally the same) clock source information are in clock table. 0: clock source 0 1: clock.." "clock source 0,clock source 1,?,?,?,?,?,clock source 7" bitfld.long 0x0 0. "CG_EN_A,path a clock gating enable. control the gating cell after core slice path a 8-1 clock mux. 1: clock not gated. 0: clock gated. clock need to be gated before changing clock source. eg. if you want to change clock source from source 0 to source 1.." "clock gated,clock not gated" repeat.end repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) group.long ($2+0x400)++0x3 line.long 0x0 "CKGEN_LP_GATING_EN_$1,ip slice sw gating enable" bitfld.long 0x0 31. "CKGEN_GATING_LOCK,LOCK SW_GATING_EN/DIS 1: locked. SW_GATING_DIS/EN will keep what they are 0: unlocked SW_GATING_DIS/EN can be changed" "unlocked,locked" newline bitfld.long 0x0 1. "SW_GATING_DIS,ckgen software gating disable has higher priority than sw_gating_en. if this bit is 1'b1 then the controlled clock will be forced on(ignore the SW_GATING_EN." "0,1" bitfld.long 0x0 0. "SW_GATING_EN,ckgen software gating enable. control the gating cell IP clock in most IPs have different gating cells you can refer to clock gating control table. 1: clock not gated. 0: clock gated." "clock gated,clock not gated" repeat.end group.long 0x600++0x3 line.long 0x0 "CKGEN_UUU_SLICE_0,uuu clock wrapper control" bitfld.long 0x0 31. "UUU_DBG_GATING_EN,gating enable for debug output. control the gating cell before uuu dbg divider 1: clock not gated. 0: clock gated." "clock gated,clock not gated" hexmask.long.byte 0x0 27.--30. 1. "DBG_DIV_NUM,divder number for debug output. this field can be updated on-the-fly. dbg clock frequence will be selected clk_out_0/(DBG_DIV_NUM+1)" newline bitfld.long 0x0 20. "UUU_GATING_ACK,reserved" "0,1" newline hexmask.long.byte 0x0 16.--19. 1. "UUU_SEL,for uuu wrapper clock gating control and clock source select uuu_sel[1:0]: clk_sel in uuu_clock_wrapper uuu_sel[1]: 1: clk_out_0 from pll 0: clk_out_0 from clk_m uuu_sel_[0]: 1: uuu input clock from pll 2: uuu input clock from ckgen_hpi slice.." hexmask.long.byte 0x0 12.--15. 1. "M_DIV_NUM,divider number for clock/m. this field can be updated on-the-fly. and uuu clock m frequency will be the corresponding uuu clock frequency/(M_DIV_NUM+1)" newline hexmask.long.byte 0x0 8.--11. 1. "N_DIV_NUM,divider number for clock/n. this field can be updated on-the-fly. and uuu clock m frequency will be the corresponding uuu clock frequency/(N_DIV_NUM+1)" hexmask.long.byte 0x0 4.--7. 1. "P_DIV_NUM,divider number for clock/p this field can be updated on-the-fly. and uuu clock m frequency will be the corresponding uuu clock frequency/(P_DIV_NUM+1)" newline hexmask.long.byte 0x0 0.--3. 1. "Q_DIV_NUM,divider number for clock/q this field can be updated on-the-fly. and uuu clock m frequency will be the corresponding uuu clock frequency/(Q_DIV_NUM+1)" group.long 0x700++0xF line.long 0x0 "CKGEN_IP_SLICE_DBG_CTL,ip slice debug control" hexmask.long.word 0x0 0.--15. 1. "IP_SLICE_DBG_SEL,ip slice debug clock source select. for ckgen_saf/ckgen_sec/ckgen_disp when ip clock is selected to be the debug source. this register choose debug clock source from ip_slice[0] to ip_slice[IP_SLICE_NUM] for ckgen_hpi from.." line.long 0x4 "CKGEN_BUS_SLICE_DBG_CTL,bus slice debug control" hexmask.long.word 0x4 0.--15. 1. "BUS_SLICE_DBG_SEL,bus slice debug clock source select. when bus clock is selected to be the debug source. this register choose debug clock source from bus_slice[0] to bus_slice[BUS_SLICE_NUM]" line.long 0x8 "CKGEN_CORE_SLICE_DBG_CTL,core slice debug control" hexmask.long.word 0x8 0.--15. 1. "CORE_SLICE_DBG_SEL,core slice debug clock source select. when core clock is selected to be the debug source. this register choose debug clock source from core_slice[0] to core_slice[CORE_SLICE_NUM]" line.long 0xC "CKGEN_DBG_CTL,ckgen debug control" bitfld.long 0xC 31. "DBG_CLK_DIS,disable ckgen debug function. 0: ckgen debug function enable 1: ckgen debug function disable" "ckgen debug function enable,ckgen debug function disable" bitfld.long 0xC 29.--30. "DBG_SEL,dbg clock out select: 2'b01: from bus slice clock which is controlled by CKGEN_BUS_SLICE_DBG_CTL 2'b10: from core slice clock which is controlled by CKGEN_CORE_SLICE_DBG_CTL others: from ip slice clock which is controlled by.." "?,from bus slice clock,from core slice clock,?" newline hexmask.long.word 0xC 0.--15. 1. "DBG_DIV_NUM,debug divider number only bit[3:0] are used since debug clock is monitored through pad only clock frequency less than 100MHz can be accepted. and divide the debug clock as early as possible from clock source." group.long 0x720++0x1B line.long 0x0 "CKGEN_IP_SLICE_MON_CTL,ip slice monitor control" hexmask.long.word 0x0 0.--15. 1. "IP_SLICE_MON_SEL,ip slice mon clock source select. for ckgen_saf/ckgen_sec/ckgen_disp when ip clock is selected to be the monitor source. this register choose monitor clock source from ip_slice[0] to ip_slice[IP_SLICE_NUM] for ckgen_hpi from.." line.long 0x4 "CKGEN_BUS_SLICE_MON_CTL,bus slice monitor control" hexmask.long.word 0x4 0.--15. 1. "BUS_SLICE_MON_SEL,bus slice mon clock source select. when bus clock is selected to be the monitor source. this register choose monitor clock source from bus_slice[0] to bus_slice[BUS_SLICE_NUM]" line.long 0x8 "CKGEN_CORE_SLICE_MON_CTL,core slice monitor control" hexmask.long.word 0x8 0.--15. 1. "CORE_SLICE_MON_SEL,core slice monitor clock source select. when core clock is selected to be the monitor source. this register choose monitor clock source from core_slice[0] to core_slice[CORE_SLICE_NUM]" line.long 0xC "CKGEN_MON_CTL,ckgen monitor control" bitfld.long 0xC 31. "MON_CLK_DIS,disable ckgen monitor function. 0: ckgen monitor function enable 1: ckgen monitor function disable" "ckgen monitor function enable,ckgen monitor function disable" bitfld.long 0xC 29.--30. "MON_SEL,monitor clock out select: 2'b01: from bus slice clock which is controlled by CKGEN_BUS_SLICE_MON_CTL 2'b10: from core slice clock which is controlled by CKGEN_CORE_SLICE_MON_CTL others: from ip slice clock which is controlled by.." "?,from bus slice clock,from core slice clock,?" newline bitfld.long 0xC 28. "MON_VAL_UPD_EN,latch monitor value enable 1: latch 0: latch disable" "latch disable,latch" rbitfld.long 0xC 27. "FREQ_RDY_STA,frequency calculate ready indicator." "0,1" newline rbitfld.long 0xC 26. "MON_CLK_DIS_STA,mon_clk_dis status. need to check after program mon_clk_dis" "0,1" bitfld.long 0xC 25. "CLK_SLOW_SRC,clk slow source select. this is the referenc clock source for clock monitor. 1: 32k 0: 24M" "0,1" newline rbitfld.long 0xC 16. "MON_DIV_BUSY,monitor divider update busy. indicate monitor divider update status. 1: monitor divider update on progress. 0: monitor divider update done." "monitor divider update done,monitor divider update on progress" newline hexmask.long.word 0xC 0.--15. 1. "MON_DIV_NUM,monitor divider number only bit[3:0] are used this field can be changed on-the-fly." line.long 0x10 "CKGEN_MON_MAX_FREQ,clock monitor max freq value" hexmask.long.word 0x10 0.--15. 1. "MON_MAX_FREQ,monitor clock max freq value. monitored max freq. this is only for debug" line.long 0x14 "CKGEN_MON_AVE_FREQ,clock monitor average freq value" hexmask.long.word 0x14 0.--15. 1. "MON_AVE_FREQ,monitor clock average freq value. the monitored clock frequency should be MON_AVE_FREQ * CLK_SLOW_SRC" line.long 0x18 "CKGEN_MON_MIN_FREQ,clock monitor min freq value" hexmask.long.word 0x18 0.--15. 1. "MON_MIN_FREQ,monitor clock mininum freq value. monitored min freq. this is only for debug" rgroup.long 0x73C++0x7 line.long 0x0 "CKGEN_MON_MAX_DUTY,clock monitor max high duty value" hexmask.long.word 0x0 16.--31. 1. "MON_MAX_PERIOD,monitor clock max period corresponding to the max high level value" hexmask.long.word 0x0 0.--15. 1. "MON_MAX_HIGH,monitor clock max high level value" line.long 0x4 "CKGEN_MON_MIN_DUTY,clock monitor min duty value" hexmask.long.word 0x4 16.--31. 1. "MON_MIN_PERIOD,monitor clock min period corresponding to the min high level value" hexmask.long.word 0x4 0.--15. 1. "MON_MIN_HIGH,monitor clock min high level value" tree.end tree "CKGEN_SAFETY" base ad:0x3C000000 repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) group.long ($2)++0x3 line.long 0x0 "CKGEN_IP_SLICE_CTL_$1,ip slice control reg" rbitfld.long 0x0 31. "POST_BUSY,ck gen ip slice post_div busy status. indicate post divider update status. 1: post divider update on progress. 0: post divider update done." "post divider update done,post divider update on progress" rbitfld.long 0x0 30. "PRE_BUSY,ck gen ip slice pre_div busy status. indicate pre divider update status. 1: pre divider update on progress. 0: pre divider update done." "pre divider update done,pre divider update on progress" newline bitfld.long 0x0 28. "CG_EN_STATUS,clock gating enable status indicate CG_EN change doen since CG_EN is asynchronous to ip slice this bit indicate the CG_EN is received(active) in ip slice. when you change CG_EN you need to read this bit after that to make sure CG_EN is.." "0,1" newline hexmask.long.byte 0x0 10.--15. 1. "POST_DIV_NUM,post_div num. like PRE_DIV_NUM this field can be updated on-the-fly. and ip slice frequency will be selected clock source frequency/(PRE_DIV_NUM+1)/(POST_DIV_NUM+1)" newline bitfld.long 0x0 4.--6. "PRE_DIV_NUM,pre_div_num. each ip slice have 2 dividers pre_divider and post_divider. this field can be updated on-the-fly. ip slice frequency will be selected clock source frequency/(PRE_DIV_NUM+1)/(POST_DIV_NUM+1)" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 1.--3. "CLK_SRC_SEL,clock source select. each ip slice has 8 clock source(from clock source 0 to clock source 7) clock source information are in clock table. 0: clock source 0 1: clock source 1 .... 7: clock source 7" "clock source 0,clock source 1,?,?,?,?,?,clock source 7" bitfld.long 0x0 0. "CG_EN,clock gating enable. control the gating cell after ip slice 8-1 clock mux. 1: clock not gated. 0: clock gated. clock need to be gated before changing clock source. eg. if you want to change clock source from source 0 to source 1 you need to follow.." "clock gated,clock not gated" repeat.end repeat 2. (list 0x0 0x1 )(list 0x0 0x8 ) group.long ($2+0x200)++0x3 line.long 0x0 "CKGEN_BUS_SLICE_CTL_$1,bus slice control reg" rbitfld.long 0x0 31. "POST_BUSY,ck gen bus slice post_div busy status. indicate post divider update status. 1: post divider update on progress. 0: post divider update done." "post divider update done,post divider update on progress" rbitfld.long 0x0 30. "PRE_BUSY_A,ck gen bus slice pre_div_a busy status. indicate pre divider a update status. 1: pre divider a update on progress. 0: pre divider a update done." "pre divider a update done,pre divider a update on progress" newline rbitfld.long 0x0 29. "PRE_BUSY_B,ck gen bus slice pre_div_b busy. indicate pre divider b update status. 1: pre divider b update on progress. 0: pre divider b update done." "pre divider b update done,pre divider b update on progress" bitfld.long 0x0 28. "CG_EN_A_STATUS,clock gating enable a status indicate CG_EN_A change doen. since CG_EN_A is asynchronous to bus slice this bit indicate the CG_EN_A is received(active) in bus slice. when you change CG_EN_A you need to read this bit after that to make.." "0,1" newline bitfld.long 0x0 27. "CG_EN_B_STATUS,clock gating enable b status indicate CG_EN_B change doen. since CG_EN_B is asynchronous to bus slice this bit indicate the CG_EN_B is received(active) in bus slice. when you change CG_EN_B you need to read this bit after that to make.." "0,1" newline bitfld.long 0x0 20.--22. "PRE_DIV_NUM_B,pre_div_b num. each bus slice have 3 dividers pre_divider_a pre_divider_b and post_divider. this field can be updated on-the-fly. bus slice frequency will be selected clock source frequency/(PRE_DIV_NUM+1)/(POST_DIV_NUM+1). in which.." "0,1,2,3,4,5,6,7" bitfld.long 0x0 17.--19. "CLK_SRC_SEL_B,path b clock source select. each path in bus slice has 8 clock source(from clock source 0 to clock source 7 and path a and path b clock sources are totally the same) clock source information are in clock table. 0: clock source 0 1: clock.." "clock source 0,clock source 1,?,?,?,?,?,clock source 7" newline bitfld.long 0x0 16. "CG_EN_B,path b clock gating enable. control the gating cell after bus slice path b 8-1 clock mux. 1: clock not gated. 0: clock gated. clock need to be gated before changing clock source. eg. if you want to change clock source from source 0 to source 1.." "clock gated,clock not gated" hexmask.long.byte 0x0 10.--15. 1. "POST_DIV_NUM,post_div num. each bus slice have 3 dividers pre_divider_a pre_divider_b and post_divider. this field can be updated on-the-fly. bus slice frequency will be selected clock source frequency/(PRE_DIV_NUM+1)/(POST_DIV_NUM+1). in which.." newline bitfld.long 0x0 9. "A_B_SEL,select between path a and path b clock source. 0: path a is selected. 1: path b is selected. this can be changed on-the-fly. please make sure both path a frequency and path b frequency are within spec." "path a is selected,path b is selected" newline bitfld.long 0x0 4.--6. "PRE_DIV_NUM_A,pre_div_a num. each bus slice have 3 dividers pre_divider_a pre_divider_b and post_divider. this field can be updated on-the-fly. bus slice frequency will be selected clock source frequency/(PRE_DIV_NUM+1)/(POST_DIV_NUM+1). in which.." "0,1,2,3,4,5,6,7" bitfld.long 0x0 1.--3. "CLK_SRC_SEL_A,path a clock source select. each path in bus slice has 8 clock source(from clock source 0 to clock source 7 and path a and path b clock sources are totally the same) clock source information are in clock table. 0: clock source 0 1: clock.." "clock source 0,clock source 1,?,?,?,?,?,clock source 7" newline bitfld.long 0x0 0. "CG_EN_A,path a clock gating enable. control the gating cell after bus slice path a 8-1 clock mux. 1: clock not gated. 0: clock gated. clock need to be gated before changing clock source. eg. if you want to change clock source from source 0 to source 1.." "clock gated,clock not gated" repeat.end repeat 2. (list 0x0 0x1 )(list 0x0 0x8 ) group.long ($2+0x204)++0x3 line.long 0x0 "CKGEN_BUS_SLICE_GASKET_$1,bus slice gasket control" rbitfld.long 0x0 31. "DIV_M_BUSY,clock/m divider busy status. indicate clock/m divider update status. 1: clock/m divider update on progress. 0: clock/m divider update done." "clock/m divider update done,clock/m divider update on progress" rbitfld.long 0x0 30. "DIV_N_BUSY,clock/n divider busy status. indicate clock/n divider update status. 1: clock/n divider update on progress. 0: clock/n divider update done." "clock/n divider update done,clock/n divider update on progress" newline rbitfld.long 0x0 29. "DIV_P_BUSY,clock/p divider busy status. indicate clock/p divider update status. 1: clock/p divider update on progress. 0: clock/p divider update done." "clock/p divider update done,clock/p divider update on progress" rbitfld.long 0x0 28. "DIV_Q_BUSY,clock/q divider busy status. indicate clock/q divider update status. 1: clock/q divider update on progress. 0: clock/q divider update done." "clock/q divider update done,clock/q divider update on progress" newline bitfld.long 0x0 9.--11. "M_DIV_NUM,divider number for clock/m. this field can be updated on-the-fly. and bus slice gasket m frequency will be the corresponding bus clock frequency/(M_DIV_NUM+1)" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 6.--8. "N_DIV_NUM,divider number for clock/n this field can be updated on-the-fly. and bus slice gasket m frequency will be the corresponding bus clock frequency/(N_DIV_NUM+1)" "0,1,2,3,4,5,6,7" bitfld.long 0x0 3.--5. "P_DIV_NUM,divider number for clock/p this field can be updated on-the-fly. and bus slice gasket m frequency will be the corresponding bus clock frequency/(P_DIV_NUM+1)" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 0.--2. "Q_DIV_NUM,divider number for clock/q this field can be updated on-the-fly. and bus slice gasket m frequency will be the corresponding bus clock frequency/(Q_DIV_NUM+1)" "0,1,2,3,4,5,6,7" repeat.end repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) group.long ($2+0x300)++0x3 line.long 0x0 "CKGEN_CORE_SLICE_CTL_$1,core slice control reg" rbitfld.long 0x0 31. "POST_BUSY,ckgen core slice post_div busy status. indicate post divider update status. 1: post divider update on progress. 0: post divider update done." "post divider update done,post divider update on progress" newline bitfld.long 0x0 28. "CG_EN_A_STATUS,clock gating enable a status indicate CG_EN_A change done. since CG_EN_A is asynchronous to core slice this bit indicate the CG_EN_A is received(active) in core slice. when you change CG_EN_A you need to read this bit after that to make.." "0,1" bitfld.long 0x0 27. "CG_EN_B_STATUS,clock gating enable b status indicate CG_EN_B change doen. since CG_EN_B is asynchronous to core slice this bit indicate the CG_EN_B is received(active) in core slice. when you change CG_EN_B you need to read this bit after that to make.." "0,1" newline bitfld.long 0x0 17.--19. "CLK_SRC_SEL_B,path b clock source select. each path in bus slice has 8 clock source(from clock source 0 to clock source 7 and path a and path b clock sources are totally the same) clock source information are in clock table. 0: clock source 0 1: clock.." "clock source 0,clock source 1,?,?,?,?,?,clock source 7" newline bitfld.long 0x0 16. "CG_EN_B,path b clock gating enable. control the gating cell after core slice path b 8-1 clock mux. 1: clock not gated. 0: clock gated. clock need to be gated before changing clock source. eg. if you want to change clock source from source 0 to source 1.." "clock gated,clock not gated" hexmask.long.byte 0x0 10.--15. 1. "POST_DIV_NUM,post_div num. this field can be updated on-the-fly. core slice frequency will be selected clock source frequency/(POST_DIV_NUM+1)." newline bitfld.long 0x0 9. "A_B_SEL,select between path a and path b clock source. 0: path a is selected. 1: path b is selected. this can be changed on-the-fly. please make sure both path a frequency and path b frequency are within spec." "path a is selected,path b is selected" newline bitfld.long 0x0 1.--3. "CLK_SRC_SEL_A,path a clock source select. each path in core slice has 8 clock source(from clock source 0 to clock source 7 and path a and path b clock sources are totally the same) clock source information are in clock table. 0: clock source 0 1: clock.." "clock source 0,clock source 1,?,?,?,?,?,clock source 7" bitfld.long 0x0 0. "CG_EN_A,path a clock gating enable. control the gating cell after core slice path a 8-1 clock mux. 1: clock not gated. 0: clock gated. clock need to be gated before changing clock source. eg. if you want to change clock source from source 0 to source 1.." "clock gated,clock not gated" repeat.end repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) group.long ($2+0x400)++0x3 line.long 0x0 "CKGEN_LP_GATING_EN_$1,ip slice sw gating enable" bitfld.long 0x0 31. "CKGEN_GATING_LOCK,LOCK SW_GATING_EN/DIS 1: locked. SW_GATING_DIS/EN will keep what they are 0: unlocked SW_GATING_DIS/EN can be changed" "unlocked,locked" newline bitfld.long 0x0 1. "SW_GATING_DIS,ckgen software gating disable has higher priority than sw_gating_en. if this bit is 1'b1 then the controlled clock will be forced on(ignore the SW_GATING_EN." "0,1" bitfld.long 0x0 0. "SW_GATING_EN,ckgen software gating enable. control the gating cell IP clock in most IPs have different gating cells you can refer to clock gating control table. 1: clock not gated. 0: clock gated." "clock gated,clock not gated" repeat.end group.long 0x600++0x3 line.long 0x0 "CKGEN_UUU_SLICE_0,uuu clock wrapper control" bitfld.long 0x0 31. "UUU_DBG_GATING_EN,gating enable for debug output. control the gating cell before uuu dbg divider 1: clock not gated. 0: clock gated." "clock gated,clock not gated" hexmask.long.byte 0x0 27.--30. 1. "DBG_DIV_NUM,divder number for debug output. this field can be updated on-the-fly. dbg clock frequence will be selected clk_out_0/(DBG_DIV_NUM+1)" newline bitfld.long 0x0 20. "UUU_GATING_ACK,reserved" "0,1" newline hexmask.long.byte 0x0 16.--19. 1. "UUU_SEL,for uuu wrapper clock gating control and clock source select uuu_sel[1:0]: clk_sel in uuu_clock_wrapper uuu_sel[1]: 1: clk_out_0 from pll 0: clk_out_0 from clk_m uuu_sel_[0]: 1: uuu input clock from pll 2: uuu input clock from ckgen_hpi slice.." hexmask.long.byte 0x0 12.--15. 1. "M_DIV_NUM,divider number for clock/m. this field can be updated on-the-fly. and uuu clock m frequency will be the corresponding uuu clock frequency/(M_DIV_NUM+1)" newline hexmask.long.byte 0x0 8.--11. 1. "N_DIV_NUM,divider number for clock/n. this field can be updated on-the-fly. and uuu clock m frequency will be the corresponding uuu clock frequency/(N_DIV_NUM+1)" hexmask.long.byte 0x0 4.--7. 1. "P_DIV_NUM,divider number for clock/p this field can be updated on-the-fly. and uuu clock m frequency will be the corresponding uuu clock frequency/(P_DIV_NUM+1)" newline hexmask.long.byte 0x0 0.--3. 1. "Q_DIV_NUM,divider number for clock/q this field can be updated on-the-fly. and uuu clock m frequency will be the corresponding uuu clock frequency/(Q_DIV_NUM+1)" group.long 0x700++0xF line.long 0x0 "CKGEN_IP_SLICE_DBG_CTL,ip slice debug control" hexmask.long.word 0x0 0.--15. 1. "IP_SLICE_DBG_SEL,ip slice debug clock source select. for ckgen_saf/ckgen_sec/ckgen_disp when ip clock is selected to be the debug source. this register choose debug clock source from ip_slice[0] to ip_slice[IP_SLICE_NUM] for ckgen_hpi from.." line.long 0x4 "CKGEN_BUS_SLICE_DBG_CTL,bus slice debug control" hexmask.long.word 0x4 0.--15. 1. "BUS_SLICE_DBG_SEL,bus slice debug clock source select. when bus clock is selected to be the debug source. this register choose debug clock source from bus_slice[0] to bus_slice[BUS_SLICE_NUM]" line.long 0x8 "CKGEN_CORE_SLICE_DBG_CTL,core slice debug control" hexmask.long.word 0x8 0.--15. 1. "CORE_SLICE_DBG_SEL,core slice debug clock source select. when core clock is selected to be the debug source. this register choose debug clock source from core_slice[0] to core_slice[CORE_SLICE_NUM]" line.long 0xC "CKGEN_DBG_CTL,ckgen debug control" bitfld.long 0xC 31. "DBG_CLK_DIS,disable ckgen debug function. 0: ckgen debug function enable 1: ckgen debug function disable" "ckgen debug function enable,ckgen debug function disable" bitfld.long 0xC 29.--30. "DBG_SEL,dbg clock out select: 2'b01: from bus slice clock which is controlled by CKGEN_BUS_SLICE_DBG_CTL 2'b10: from core slice clock which is controlled by CKGEN_CORE_SLICE_DBG_CTL others: from ip slice clock which is controlled by.." "?,from bus slice clock,from core slice clock,?" newline hexmask.long.word 0xC 0.--15. 1. "DBG_DIV_NUM,debug divider number only bit[3:0] are used since debug clock is monitored through pad only clock frequency less than 100MHz can be accepted. and divide the debug clock as early as possible from clock source." group.long 0x720++0x1B line.long 0x0 "CKGEN_IP_SLICE_MON_CTL,ip slice monitor control" hexmask.long.word 0x0 0.--15. 1. "IP_SLICE_MON_SEL,ip slice mon clock source select. for ckgen_saf/ckgen_sec/ckgen_disp when ip clock is selected to be the monitor source. this register choose monitor clock source from ip_slice[0] to ip_slice[IP_SLICE_NUM] for ckgen_hpi from.." line.long 0x4 "CKGEN_BUS_SLICE_MON_CTL,bus slice monitor control" hexmask.long.word 0x4 0.--15. 1. "BUS_SLICE_MON_SEL,bus slice mon clock source select. when bus clock is selected to be the monitor source. this register choose monitor clock source from bus_slice[0] to bus_slice[BUS_SLICE_NUM]" line.long 0x8 "CKGEN_CORE_SLICE_MON_CTL,core slice monitor control" hexmask.long.word 0x8 0.--15. 1. "CORE_SLICE_MON_SEL,core slice monitor clock source select. when core clock is selected to be the monitor source. this register choose monitor clock source from core_slice[0] to core_slice[CORE_SLICE_NUM]" line.long 0xC "CKGEN_MON_CTL,ckgen monitor control" bitfld.long 0xC 31. "MON_CLK_DIS,disable ckgen monitor function. 0: ckgen monitor function enable 1: ckgen monitor function disable" "ckgen monitor function enable,ckgen monitor function disable" bitfld.long 0xC 29.--30. "MON_SEL,monitor clock out select: 2'b01: from bus slice clock which is controlled by CKGEN_BUS_SLICE_MON_CTL 2'b10: from core slice clock which is controlled by CKGEN_CORE_SLICE_MON_CTL others: from ip slice clock which is controlled by.." "?,from bus slice clock,from core slice clock,?" newline bitfld.long 0xC 28. "MON_VAL_UPD_EN,latch monitor value enable 1: latch 0: latch disable" "latch disable,latch" rbitfld.long 0xC 27. "FREQ_RDY_STA,frequency calculate ready indicator." "0,1" newline rbitfld.long 0xC 26. "MON_CLK_DIS_STA,mon_clk_dis status. need to check after program mon_clk_dis" "0,1" bitfld.long 0xC 25. "CLK_SLOW_SRC,clk slow source select. this is the referenc clock source for clock monitor. 1: 32k 0: 24M" "0,1" newline rbitfld.long 0xC 16. "MON_DIV_BUSY,monitor divider update busy. indicate monitor divider update status. 1: monitor divider update on progress. 0: monitor divider update done." "monitor divider update done,monitor divider update on progress" newline hexmask.long.word 0xC 0.--15. 1. "MON_DIV_NUM,monitor divider number only bit[3:0] are used this field can be changed on-the-fly." line.long 0x10 "CKGEN_MON_MAX_FREQ,clock monitor max freq value" hexmask.long.word 0x10 0.--15. 1. "MON_MAX_FREQ,monitor clock max freq value. monitored max freq. this is only for debug" line.long 0x14 "CKGEN_MON_AVE_FREQ,clock monitor average freq value" hexmask.long.word 0x14 0.--15. 1. "MON_AVE_FREQ,monitor clock average freq value. the monitored clock frequency should be MON_AVE_FREQ * CLK_SLOW_SRC" line.long 0x18 "CKGEN_MON_MIN_FREQ,clock monitor min freq value" hexmask.long.word 0x18 0.--15. 1. "MON_MIN_FREQ,monitor clock mininum freq value. monitored min freq. this is only for debug" rgroup.long 0x73C++0x7 line.long 0x0 "CKGEN_MON_MAX_DUTY,clock monitor max high duty value" hexmask.long.word 0x0 16.--31. 1. "MON_MAX_PERIOD,monitor clock max period corresponding to the max high level value" hexmask.long.word 0x0 0.--15. 1. "MON_MAX_HIGH,monitor clock max high level value" line.long 0x4 "CKGEN_MON_MIN_DUTY,clock monitor min duty value" hexmask.long.word 0x4 16.--31. 1. "MON_MIN_PERIOD,monitor clock min period corresponding to the min high level value" hexmask.long.word 0x4 0.--15. 1. "MON_MIN_HIGH,monitor clock min high level value" tree.end endif tree.end tree "CSI (CSI Interface)" sif (CORENAME()=="CORTEXR5F") repeat 3. (increment 1. 1.) (list ad:0xF0CC0000 ad:0xF0CD0000 ad:0xF0CE0000) tree "CSI$1" base $2 rgroup.long 0x0++0x3 line.long 0x0 "VERSION,Read-only register Contains the version of DWC_mipi_csi2_host coded in 32-bit ASCII code." hexmask.long 0x0 0.--31. 1. "VERSION,This field indicates the version of the DWC_mipi_csi2_host." group.long 0x4++0x7 line.long 0x0 "N_LANES,Static read and write register Configures the number of active lanes that the DWC_mipi_csi2_host uses to receive the camera device data." hexmask.long 0x0 3.--31. 1. "RESERVED_31_3,Reserved and read as zero." newline bitfld.long 0x0 0.--2. "N_LANES,Number of active data lanes: -000: 1 Data Lane -001: 2 Data Lanes -010: 3 Data Lanes -011: 4 Data Lanes - Only on D-PHY -100: 5 Data Lanes - Only on D-PHY -101: 6 Data Lanes - Only on D-PHY -110: 7 Data Lanes - Only on D-PHY -111: 8 Data Lanes -.." "0,1,2,3,4,5,6,7" line.long 0x4 "CSI2_RESETN,Static read and write register Controls the DWC_mipi_csi2_host logic reset state. When activated. the internal logic of the controller goes into the reset state. The configuration is not reset to default values with this register. instead." hexmask.long 0x4 1.--31. 1. "RESERVED_31_1,Reserved and read as zero." newline bitfld.long 0x4 0. "CSI2_RESETN,DWC_mipi_csi2_host reset output. Active Low." "0,1" rgroup.long 0xC++0x3 line.long 0x0 "INT_ST_MAIN,Clear on read register Contains the status of individual interrupt sources. regardless of the contents of the associated interrupt mask registers. so it is possible to service the interrupt status registers by polling. Reading INT_ST_MAIN.." hexmask.long.word 0x0 23.--31. 1. "RESERVED_31_23,Reserved and read as zero." newline bitfld.long 0x0 22. "STATUS_INT_IPI4,Status of int_st_ipi4" "0,1" newline bitfld.long 0x0 21. "STATUS_INT_IPI3,Status of int_st_ipi3" "0,1" newline bitfld.long 0x0 20. "STATUS_INT_IPI2,Status of int_st_ipi2" "0,1" newline bitfld.long 0x0 19. "STATUS_INT_IPI,Status of int_st_ipi" "0,1" newline bitfld.long 0x0 18. "STATUS_INT_LINE,Status of int_st_line" "0,1" newline bitfld.long 0x0 17. "STATUS_INT_PKT,Status of int_st_pkt." "0,1" newline bitfld.long 0x0 16. "STATUS_INT_PHY,Status of int_st_phy." "0,1" newline hexmask.long.word 0x0 3.--15. 1. "RESERVED_15_3,Reserved" newline bitfld.long 0x0 2. "STATUS_INT_FRAME_FATAL,Status of int_st_frame_fatal." "0,1" newline bitfld.long 0x0 1. "STATUS_INT_PKT_FATAL,Status of int_st_pkt_fatal." "0,1" newline bitfld.long 0x0 0. "STATUS_INT_PHY_FATAL,Status of int_st_phy_fatal." "0,1" repeat 2. (list 0x1 0x2 )(list 0x0 0x4 ) group.long ($2+0x10)++0x3 line.long 0x0 "DATA_IDS_$1,Static read and write register Programs the data Ids for matching line error reporting. Enables up to eight different data Ids that can be identified simultaneously." bitfld.long 0x0 30.--31. "DI3_VC,Virtual channel for programmed data Id 3." "0,1,2,3" newline hexmask.long.byte 0x0 24.--29. 1. "DI3_DT,Data type for programmed data Id 3." newline bitfld.long 0x0 22.--23. "DI2_VC,Virtual channel for programmed data Id 2." "0,1,2,3" newline hexmask.long.byte 0x0 16.--21. 1. "DI2_DT,Data type for programmed Data ID 2." newline bitfld.long 0x0 14.--15. "DI1_VC,Virtual channel for programmed data Id 1." "0,1,2,3" newline hexmask.long.byte 0x0 8.--13. 1. "DI1_DT,Data type for programmed data Id 1." newline bitfld.long 0x0 6.--7. "DI0_VC,Virtual channel for programmed data Id 0." "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "DI0_DT,Data type for programmed data Id 0." repeat.end rgroup.long 0x2C++0x3 line.long 0x0 "INT_ST_AP_MAIN,Clear on read register Contains the status of individual interrupt sources. regardless of the contents of the associated interrupt mask registers. so it is possible to service the interrupt status registers by polling. Reading.." hexmask.long.tbyte 0x0 15.--31. 1. "RESERVED_31_15,Reserved and read as zero." newline bitfld.long 0x0 14. "STATUS_INT_IPI4,Status of int_st_ipi4" "0,1" newline bitfld.long 0x0 13. "STATUS_INT_ST_AP_IPI4,Status of int_st_ap_ipi4" "0,1" newline bitfld.long 0x0 12. "STATUS_INT_IPI3,Status of int_st_ipi3" "0,1" newline bitfld.long 0x0 11. "STATUS_INT_ST_AP_IPI3,Status of int_st_ap_ipi3" "0,1" newline bitfld.long 0x0 10. "STATUS_INT_IPI2,Status of int_st_ipi2" "0,1" newline bitfld.long 0x0 9. "STATUS_INT_ST_AP_IPI2,Status of int_st_ap_ipi2" "0,1" newline bitfld.long 0x0 8. "STATUS_INT_IPI,Status of int_st_ipi" "0,1" newline bitfld.long 0x0 7. "STATUS_INT_ST_AP_IPI,Status of int_st_ap_ipi" "0,1" newline bitfld.long 0x0 6. "STATUS_INT_LINE,Status of int_st_line" "0,1" newline bitfld.long 0x0 5. "STATUS_INT_PKT,Status of int_st_pkt." "0,1" newline bitfld.long 0x0 4. "STATUS_INT_PHY,Status of int_st_phy." "0,1" newline bitfld.long 0x0 3. "STATUS_INT_FRAME_FATAL,Status of int_st_frame_fatal." "0,1" newline bitfld.long 0x0 2. "STATUS_INT_PKT_FATAL,Status of int_st_pkt_fatal." "0,1" newline bitfld.long 0x0 1. "STATUS_INT_PHY_FATAL,Status of int_st_phy_fatal." "0,1" newline bitfld.long 0x0 0. "STATUS_INT_ST_AP_GENERIC,Status of int_st_ap_generic." "0,1" group.long 0x40++0x7 line.long 0x0 "PHY_SHUTDOWNZ,Active low Controls the PHY Shutdown mode. In this state. the PHY sets the analog and digital circuitry in the Reset state." hexmask.long 0x0 1.--31. 1. "RESERVED_31_1,Reserved and read as zero." newline bitfld.long 0x0 0. "PHY_SHUTDOWNZ,Shutdown input. This line is used to place the complete macro in power down. All analog blocks are in power down mode and digital logic is cleared. Active Low." "0,1" line.long 0x4 "DPHY_RSTZ,Active low Controls the PHY Reset mode. in this state. the PHY sets the digital circuitry in the Reset State." hexmask.long 0x4 1.--31. 1. "RESERVED_31_1,Reserved and read as zero." newline bitfld.long 0x4 0. "DPHY_RSTZ,PHY reset output. Active Low." "0,1" rgroup.long 0x48++0x7 line.long 0x0 "PHY_RX,Read-only register Contains the status of RX-related signals from PHY: RXULPSESC* RXCLKACTIVEHS (D-PHY) It contains information such as. if the clock lane is receiving high-speed clock signal. or if the data and clock lanes are in Ultra Low Power.." hexmask.long.word 0x0 18.--31. 1. "RESERVED_31_18,Reserved and read as zero." newline bitfld.long 0x0 17. "PHY_RXCLKACTIVEHS,Indicates that D-PHY clock lane is actively receiving a DDR clock" "0,1" newline bitfld.long 0x0 16. "PHY_RXULPSCLKNOT,Active Low. This signal indicates that D-PHY Clock Lane module has entered the Ultra Low Power state" "0,1" newline hexmask.long.byte 0x0 8.--15. 1. "RESERVED_15_8,Reserved and read as zero." newline bitfld.long 0x0 7. "RESERVED_7,Reserved and read as zero" "0,1" newline bitfld.long 0x0 6. "RESERVED_6,Reserved and read as zero" "0,1" newline bitfld.long 0x0 5. "RESERVED_5,Reserved and read as zero" "0,1" newline bitfld.long 0x0 4. "RESERVED_4,Reserved and read as zero" "0,1" newline bitfld.long 0x0 3. "PHY_RXULPSESC_3,Lane module 3 has entered the Ultra Low Power mode" "0,1" newline bitfld.long 0x0 2. "PHY_RXULPSESC_2,Lane module 2 has entered the Ultra Low Power mode" "0,1" newline bitfld.long 0x0 1. "PHY_RXULPSESC_1,Lane module 1 has entered the Ultra Low Power mode" "0,1" newline bitfld.long 0x0 0. "PHY_RXULPSESC_0,Lane module 0 has entered the Ultra Low Power mode." "0,1" line.long 0x4 "PHY_STOPSTATE,Read-only register Contains the STOPSTATE signal status from PHY." hexmask.long.word 0x4 17.--31. 1. "RESERVED_31_17,Reserved and read as zero." newline bitfld.long 0x4 16. "PHY_STOPSTATECLK,D-PHY Clock lane in Stop state" "0,1" newline hexmask.long.byte 0x4 8.--15. 1. "RESERVED_15_8,Reserved and read as zero." newline bitfld.long 0x4 7. "RESERVED_7,Reserved and read as zero" "0,1" newline bitfld.long 0x4 6. "RESERVED_6,Reserved and read as zero" "0,1" newline bitfld.long 0x4 5. "RESERVED_5,Reserved and read as zero" "0,1" newline bitfld.long 0x4 4. "RESERVED_4,Reserved and read as zero" "0,1" newline bitfld.long 0x4 3. "PHY_STOPSTATEDATA_3,Data lane 3 in Stop state" "0,1" newline bitfld.long 0x4 2. "PHY_STOPSTATEDATA_2,Data lane 2 in Stop state" "0,1" newline bitfld.long 0x4 1. "PHY_STOPSTATEDATA_1,Data lane 1 in Stop state" "0,1" newline bitfld.long 0x4 0. "PHY_STOPSTATEDATA_0,Data lane 0 in Stop state." "0,1" group.long 0x50++0x7 line.long 0x0 "PHY_TEST_CTRL0,Dynamic register Control for vendor specific interface in the PHY. Controls the Synopsys D-PHY Test and Control interface. This register controls the TESTCLR and TESTCLK signals." hexmask.long 0x0 2.--31. 1. "RESERVED_31_2,Reserved and read as zero." newline bitfld.long 0x0 1. "PHY_TESTCLK,Clock to capture testdin bus contents into the macro with testen signal controlling the operation selection." "0,1" newline bitfld.long 0x0 0. "PHY_TESTCLR,When active performs vendor specific interface initialization. Active High. Note: This line needs an initial high pulse after power up for analog programmability default values to be preset." "0,1" line.long 0x4 "PHY_TEST_CTRL1,Dynamic register Control for vendor specific interface in the PHY. Controls the Synopsys D-PHY Test and Control interface. This register controls the TESTENABLE signal and the TESTDIN bus. Reading from this register retrieves the value.." hexmask.long.word 0x4 17.--31. 1. "RESERVED_31_17,Reserved and read as zero." newline bitfld.long 0x4 16. "PHY_TESTEN,When asserted high it configures an address write operation on the falling edge of testclk. When asserted low it configures a data write operation on the rising edge of testclk." "0,1" newline hexmask.long.byte 0x4 8.--15. 1. "PHY_TESTDOUT,Vendor-specific 8-bit data output for reading data and other probing functionalities." newline hexmask.long.byte 0x4 0.--7. 1. "PHY_TESTDIN,Test interface 8-bit data input for programming internal registers and accessing test functionalities." group.long 0x80++0x23 line.long 0x0 "IPI_MODE,This register selects how the IPI interface generates the video frame." hexmask.long.byte 0x0 25.--31. 1. "RESERVED_31_25,Reserved and read as zero." newline bitfld.long 0x0 24. "IPI_ENABLE,This register enables the interface." "0,1" newline hexmask.long.byte 0x0 17.--23. 1. "RESERVED_23_17,Reserved and read as zero." newline bitfld.long 0x0 16. "IPI_CUT_THROUGH,This field indicates cut-through mode state: -0: cut-through mode inactive -1: cut-through mode active" "cut-through mode inactive,cut-through mode active" newline hexmask.long.byte 0x0 9.--15. 1. "RESERVED_15_9,Reserved and read as zero." newline bitfld.long 0x0 8. "IPI_COLOR_COM,This field indicates if color mode components are delivered as follows: -0: 48 bits interface -1: 16 bits interface" "0,1" newline hexmask.long.byte 0x0 1.--7. 1. "RESERVED_7_1,Reserved and read as zero." newline bitfld.long 0x0 0. "IPI_MODE,This field indicates the video mode transmission type as follows: -0: Camera timing -1: Controller timing" "Camera timing,Controller timing" line.long 0x4 "IPI_VCID,This register selects the virtual channel processed by IPI." hexmask.long 0x4 2.--31. 1. "RESERVED_31_2,Reserved and read as zero." newline bitfld.long 0x4 0.--1. "IP_VCID,Virtual channel of data to be processed by pixel interface." "0,1,2,3" line.long 0x8 "IPI_DATA_TYPE,This register selects the data type processed by IPI." hexmask.long.tbyte 0x8 9.--31. 1. "RESERVED_31_9,Reserved and read as zero." newline bitfld.long 0x8 8. "EMBEDDED_DATA,This bit enables embedded data processing on IPI interface." "0,1" newline rbitfld.long 0x8 6.--7. "RESERVED_7_6,Reserved and read as zero." "0,1,2,3" newline hexmask.long.byte 0x8 0.--5. 1. "IPI_DATA_TYPE,Data type of data to be processed by pixel interface." line.long 0xC "IPI_MEM_FLUSH,This register control the flush of IPI memory." hexmask.long.tbyte 0xC 9.--31. 1. "RESERVED_31_9,Reserved and read as zero." newline bitfld.long 0xC 8. "IPI_AUTO_FLUSH,Memory is automatically flushed at each vsync." "0,1" newline hexmask.long.byte 0xC 1.--7. 1. "RESERVED_7_1,Reserved and read as zero." newline bitfld.long 0xC 0. "IPI_FLUSH,Flush IPI memory. This bit is auto clear." "0,1" line.long 0x10 "IPI_HSA_TIME,This register configures the video Horizontal Synchronism Active (HSA) time." hexmask.long.tbyte 0x10 12.--31. 1. "RESERVED_31_12,Reserved and read as zero." newline hexmask.long.word 0x10 0.--11. 1. "IPI_HSA_TIME,This field configures the Horizontal Synchronism Active period in pixclk cycles." line.long 0x14 "IPI_HBP_TIME,This register configures the video Horizontal Back Porch (HBP) time." hexmask.long.tbyte 0x14 12.--31. 1. "RESERVED_31_12,Reserved and read as zero." newline hexmask.long.word 0x14 0.--11. 1. "IPI_HBP_TIME,This field configures the Horizontal Back Porch period in pixclk cycles." line.long 0x18 "IPI_HSD_TIME,This register configures the video Horizontal Sync Delay (HSD) time." hexmask.long.tbyte 0x18 12.--31. 1. "RESERVED_31_12,Reserved and read as zero." newline hexmask.long.word 0x18 0.--11. 1. "IPI_HSD_TIME,This field configures the Horizontal Sync Porch delay period in pixclk cycles." line.long 0x1C "IPI_HLINE_TIME,This register configures the overall time for each video line." hexmask.long.tbyte 0x1C 15.--31. 1. "RESERVED_31_15,Reserved and read as zero." newline hexmask.long.word 0x1C 0.--14. 1. "IPI_HLINE_TIME,This field configures the size of the line time counted in pixclk cycles." line.long 0x20 "IPI_SOFTRSTN,Static read and write register Controls the IPI logic reset state. When activated. the internal logic of the IPI goes into the reset state.Only the internal IPI logic is affected." hexmask.long.tbyte 0x20 13.--31. 1. "RESERVED_31_13,Reserved and read as zero." newline bitfld.long 0x20 12. "IPI4_SOFTRSTN,This field resets IPI four. Active Low" "0,1" newline rbitfld.long 0x20 9.--11. "RESERVED_11_9,Reserved and read as zero." "0,1,2,3,4,5,6,7" newline bitfld.long 0x20 8. "IPI3_SOFTRSTN,This field resets IPI three. Active Low" "0,1" newline rbitfld.long 0x20 5.--7. "RESERVED_7_5,Reserved and read as zero." "0,1,2,3,4,5,6,7" newline bitfld.long 0x20 4. "IPI2_SOFTRSTN,This field resets IPI two. Active Low" "0,1" newline rbitfld.long 0x20 1.--3. "RESERVED_3_1,Reserved and read as zero." "0,1,2,3,4,5,6,7" newline bitfld.long 0x20 0. "IPI_SOFTRSTN,This field resets IPI one. Active Low." "0,1" group.long 0xAC++0x13 line.long 0x0 "IPI_ADV_FEATURES,This register configures advanced features for IPI mode." hexmask.long.byte 0x0 25.--31. 1. "RESERVED_31_25,Reserved and read as zero." newline bitfld.long 0x0 24. "IPI_SYNC_EVENT_MODE,For Camera Mode: -0: Frame Start dont trigger any sync event -1: Legaccy mode. Frame start will trigger a sync event" "Frame Start dont trigger any sync event,Legaccy mode" newline rbitfld.long 0x0 22.--23. "RESERVED_23_22,Reserved and read as zero." "0,1,2,3" newline bitfld.long 0x0 21. "EN_EMBEDDED,This register allows to use embedded packets for IPI synchronization events." "0,1" newline bitfld.long 0x0 20. "EN_BLANKING,This register allows to use blanking packets for IPI synchronization events." "0,1" newline bitfld.long 0x0 19. "EN_NULL,This register allows to use null packets for IPI synchronization events." "0,1" newline bitfld.long 0x0 18. "EN_LINE_START,This register allows to use line start packets for IPI synchronization events." "0,1" newline bitfld.long 0x0 17. "EN_VIDEO,This register allows to use video packets for IPI synchronization events." "0,1" newline bitfld.long 0x0 16. "LINE_EVENT_SELECTION,For Camera Mode this register allows to manualy select the Packet for line delimiter as follows: -0: controller select it automatically -1: select packets from list programmed in [17:21]." "controller select it automatically,select packets from list programmed in [17:21]" newline rbitfld.long 0x0 14.--15. "RESERVED_15_14,Reserved and read as zero." "0,1,2,3" newline hexmask.long.byte 0x0 8.--13. 1. "IPI_DT,Datatype to overwrite." newline hexmask.long.byte 0x0 1.--7. 1. "RESERVED_7_1,Reserved and read as zero." newline bitfld.long 0x0 0. "IPI_DT_OVERWRITE,Ignore datatype of the header using the programed datatype for decoding." "0,1" line.long 0x4 "IPI_VSA_LINES,This register configures the Vertical Synchronism Active (VSA) period." hexmask.long.tbyte 0x4 10.--31. 1. "RESERVED_31_10,Reserved and read as zero." newline hexmask.long.word 0x4 0.--9. 1. "IPI_VSA_LINES,This field configures the Vertical Synchronism Active period measured in number of horizontal lines." line.long 0x8 "IPI_VBP_LINES,This register configures the Vertical Back Porch (VBP) period." hexmask.long.tbyte 0x8 10.--31. 1. "RESERVED_31_10,Reserved and read as zero." newline hexmask.long.word 0x8 0.--9. 1. "IPI_VBP_LINES,This field configures the Vertical Back Porch period measured in number of horizontal lines." line.long 0xC "IPI_VFP_LINES,This register configures the Vertical Front Porch (VFP) period." hexmask.long.tbyte 0xC 10.--31. 1. "RESERVED_31_10,Reserved and read as zero." newline hexmask.long.word 0xC 0.--9. 1. "IPI_VFP_LINES,This field configures the Vertical Front Porch period measured in number of horizontal lines." line.long 0x10 "IPI_VACTIVE_LINES,This register configures the vertical resolution of the video." hexmask.long.tbyte 0x10 14.--31. 1. "RESERVED_31_14,Reserved and read as zero." newline hexmask.long.word 0x10 0.--13. 1. "IPI_VACTIVE_LINES,This field configures the Vertical Active period measured in number of horizontal lines." rgroup.long 0xCC++0x3 line.long 0x0 "PHY_CAL,Clear on read register Contains the CALIBRATION signal status from Synopsys D-PHY." hexmask.long 0x0 1.--31. 1. "RESERVED_31_1,Reserved and read as zero." newline bitfld.long 0x0 0. "RXSKEWCALHS,A low-to-high transition on rxskewcalhs signal means that the PHY has initiated the de-skew calibration.." "0,1" rgroup.long 0xE0++0x3 line.long 0x0 "INT_ST_PHY_FATAL,Clear on read register Groups the fatal interruptions caused by PHY Packet discarded. Stores the source of the error. Reading INT_ST_PHY_FATAL register does not clear the interrupt pin." hexmask.long.word 0x0 19.--31. 1. "RESERVED_31_19,Reserved and read as zero." newline bitfld.long 0x0 18. "RESERVED_18,Reserved and read as zero" "0,1" newline bitfld.long 0x0 17. "RESERVED_17,Reserved and read as zero" "0,1" newline bitfld.long 0x0 16. "RESERVED_16,Reserved and read as zero" "0,1" newline hexmask.long.byte 0x0 8.--15. 1. "RESERVED_15_8,Reserved and read as zero." newline bitfld.long 0x0 7. "RESERVED_7,Reserved and read as zero" "0,1" newline bitfld.long 0x0 6. "RESERVED_6,Reserved and read as zero" "0,1" newline bitfld.long 0x0 5. "RESERVED_5,Reserved and read as zero" "0,1" newline bitfld.long 0x0 4. "RESERVED_4,Reserved and read as zero" "0,1" newline bitfld.long 0x0 3. "PHY_ERRSOTSYNCHS_3,Start of transmission error on data lane 3 (no synchronization achieved)" "0,1" newline bitfld.long 0x0 2. "PHY_ERRSOTSYNCHS_2,Start of transmission error on data lane 2 (no synchronization achieved)" "0,1" newline bitfld.long 0x0 1. "PHY_ERRSOTSYNCHS_1,Start of transmission error on data lane 1 (no synchronization achieved)" "0,1" newline bitfld.long 0x0 0. "PHY_ERRSOTSYNCHS_0,Start of transmission error on data lane 0 (no synchronization achieved)." "0,1" group.long 0xE4++0x7 line.long 0x0 "INT_MSK_PHY_FATAL,Static read and write register Interrupt mask for INT_ST_PHY_FATAL controls which interrupt status bits will trigger the interrupt pin. Bit at 1 - Enable the interrupt source. Bit at 0 - Interrupt source is masked." hexmask.long.word 0x0 19.--31. 1. "RESERVED_31_19,Reserved and read as zero." newline rbitfld.long 0x0 18. "RESERVED_18,Reserved and read as zero" "0,1" newline rbitfld.long 0x0 17. "RESERVED_17,Reserved and read as zero" "0,1" newline rbitfld.long 0x0 16. "RESERVED_16,Reserved and read as zero" "0,1" newline hexmask.long.byte 0x0 8.--15. 1. "RESERVED_15_8,Reserved and read as zero." newline rbitfld.long 0x0 7. "RESERVED_7,Reserved and read as zero" "0,1" newline rbitfld.long 0x0 6. "RESERVED_6,Reserved and read as zero" "0,1" newline rbitfld.long 0x0 5. "RESERVED_5,Reserved and read as zero" "0,1" newline rbitfld.long 0x0 4. "RESERVED_4,Reserved and read as zero" "0,1" newline bitfld.long 0x0 3. "MASK_PHY_ERRSOTSYNCHS_3,Mask for phy_errsotsynchs_3" "0,1" newline bitfld.long 0x0 2. "MASK_PHY_ERRSOTSYNCHS_2,Mask for phy_errsotsynchs_2" "0,1" newline bitfld.long 0x0 1. "MASK_PHY_ERRSOTSYNCHS_1,Mask for phy_errsotsynchs_1" "0,1" newline bitfld.long 0x0 0. "MASK_PHY_ERRSOTSYNCHS_0,Mask for phy_errsotsynchs_0." "0,1" line.long 0x4 "INT_FORCE_PHY_FATAL,Static read and write register Interrupt Force register is used for test purposes. and allows triggering INT_ST_PHY_FATAL interrupt events individually. without the need to activate the conditions that trigger the interrupt sources." hexmask.long.word 0x4 19.--31. 1. "RESERVED_31_19,Reserved and read as zero." newline rbitfld.long 0x4 18. "RESERVED_18,Reserved and read as zero" "0,1" newline rbitfld.long 0x4 17. "RESERVED_17,Reserved and read as zero" "0,1" newline rbitfld.long 0x4 16. "RESERVED_16,Reserved and read as zero" "0,1" newline hexmask.long.byte 0x4 8.--15. 1. "RESERVED_15_8,Reserved and read as zero." newline rbitfld.long 0x4 7. "RESERVED_7,Reserved and read as zero" "0,1" newline rbitfld.long 0x4 6. "RESERVED_6,Reserved and read as zero" "0,1" newline rbitfld.long 0x4 5. "RESERVED_5,Reserved and read as zero" "0,1" newline rbitfld.long 0x4 4. "RESERVED_4,Reserved and read as zero" "0,1" newline bitfld.long 0x4 3. "FORCE_PHY_ERRSOTSYNCHS_3,Force phy_errsotsynchs_3" "0,1" newline bitfld.long 0x4 2. "FORCE_PHY_ERRSOTSYNCHS_2,Force phy_errsotsynchs_2" "0,1" newline bitfld.long 0x4 1. "FORCE_PHY_ERRSOTSYNCHS_1,Force phy_errsotsynchs_1" "0,1" newline bitfld.long 0x4 0. "FORCE_PHY_ERRSOTSYNCHS_0,Force phy_errsotsynchs_0." "0,1" rgroup.long 0xF0++0x3 line.long 0x0 "INT_ST_PKT_FATAL,Clear on read register Groups the fatal interruption related with Packet construction. Packet discarded. Notifies which interruption bit has caused the interruption. Stores the source of the error. Reading INT_ST_PKT_FATAL register does.." hexmask.long.word 0x0 17.--31. 1. "RESERVED_31_17,Reserved and read as zero." newline bitfld.long 0x0 16. "ERR_ECC_DOUBLE,D-PHY mode : Header ECC contains at least 2 errors unrecoverable. C-PHY mode : Header CRC unrecoverable." "0,1" newline hexmask.long.word 0x0 4.--15. 1. "RESERVED_15_4,Reserved and read as zero." newline bitfld.long 0x0 3. "VC3_ERR_CRC,Payload Checksum error detected on virtual channel 3." "0,1" newline bitfld.long 0x0 2. "VC2_ERR_CRC,Payload Checksum error detected on virtual channel 2." "0,1" newline bitfld.long 0x0 1. "VC1_ERR_CRC,Payload Checksum error detected on virtual channel 1." "0,1" newline bitfld.long 0x0 0. "VC0_ERR_CRC,Payload Checksum error detected on virtual channel 0." "0,1" group.long 0xF4++0x7 line.long 0x0 "INT_MSK_PKT_FATAL,Static read and write register Interrupt mask for INT_ST_PKT_FATAL controls which interrupt status bits will trigger the interrupt pin. Bit at 1 - Enable the interrupt source. Bit at 0 - Interrupt source is masked." hexmask.long.word 0x0 17.--31. 1. "RESERVED_31_17,Reserved and read as zero." newline bitfld.long 0x0 16. "MASK_ERR_ECC_DOUBLE,Mask for err_ecc_double." "0,1" newline hexmask.long.word 0x0 4.--15. 1. "RESERVED_15_4,Reserved and read as zero." newline bitfld.long 0x0 3. "MASK_VC3_ERR_CRC,Mask for vc3_err_crc." "0,1" newline bitfld.long 0x0 2. "MASK_VC2_ERR_CRC,Mask for vc2_err_crc." "0,1" newline bitfld.long 0x0 1. "MASK_VC1_ERR_CRC,Mask for vc1_err_crc." "0,1" newline bitfld.long 0x0 0. "MASK_VC0_ERR_CRC,Mask for vc0_err_crc." "0,1" line.long 0x4 "INT_FORCE_PKT_FATAL,Static read and write register Interrupt force register is used for test purposes. and allows triggering INT_ST_PKT_FATAL interrupt events individually. without the need to activate the conditions that trigger the interrupt sources." hexmask.long.word 0x4 17.--31. 1. "RESERVED_31_17,Reserved and read as zero." newline bitfld.long 0x4 16. "FORCE_ERR_ECC_DOUBLE,Force err_ecc_double." "0,1" newline hexmask.long.word 0x4 4.--15. 1. "RESERVED_15_4,Reserved and read as zero." newline bitfld.long 0x4 3. "FORCE_VC3_ERR_CRC,Force vc3_err_crc." "0,1" newline bitfld.long 0x4 2. "FORCE_VC2_ERR_CRC,Force vc2_err_crc." "0,1" newline bitfld.long 0x4 1. "FORCE_VC1_ERR_CRC,Force vc1_err_crc." "0,1" newline bitfld.long 0x4 0. "FORCE_VC0_ERR_CRC,Force vc0_err_crc." "0,1" rgroup.long 0x100++0x3 line.long 0x0 "INT_ST_FRAME_FATAL,Clear on read register Fatal interruption related with Frame construction. Packet discarded. Groups and notifies which interruption bits caused the interruption. Stores the source of the error. Reading INT_ST_FRAME_FATAL register does.." hexmask.long.word 0x0 20.--31. 1. "RESERVED_31_20,Reserved and read as zero." newline bitfld.long 0x0 19. "ERR_FRAME_DATA_VC3,Last received Frame in virtual channel 3 had at least one CRC error." "0,1" newline bitfld.long 0x0 18. "ERR_FRAME_DATA_VC2,Last received Frame in virtual channel 2 had at least one CRC error." "0,1" newline bitfld.long 0x0 17. "ERR_FRAME_DATA_VC1,Last received Frame in virtual channel 1 had at least one CRC error." "0,1" newline bitfld.long 0x0 16. "ERR_FRAME_DATA_VC0,Last received Frame in virtual channel 0 had at least one CRC error." "0,1" newline hexmask.long.byte 0x0 12.--15. 1. "RESERVED_15_12,Reserved and read as zero." newline bitfld.long 0x0 11. "ERR_F_SEQ_VC3,Incorrect Frame sequence detected in Virtual Channel 3." "0,1" newline bitfld.long 0x0 10. "ERR_F_SEQ_VC2,Incorrect Frame sequence detected in Virtual Channel 2." "0,1" newline bitfld.long 0x0 9. "ERR_F_SEQ_VC1,Incorrect Frame sequence detected in Virtual Channel 1." "0,1" newline bitfld.long 0x0 8. "ERR_F_SEQ_VC0,Incorrect Frame sequence detected in Virtual Channel 0." "0,1" newline hexmask.long.byte 0x0 4.--7. 1. "RESERVED_7_4,Reserved and read as zero." newline bitfld.long 0x0 3. "ERR_F_BNDRY_MATCH_VC3,Error matching Frame Start with Frame End for virtual channel 3." "0,1" newline bitfld.long 0x0 2. "ERR_F_BNDRY_MATCH_VC2,Error matching Frame Start with Frame End for virtual channel 2." "0,1" newline bitfld.long 0x0 1. "ERR_F_BNDRY_MATCH_VC1,Error matching Frame Start with Frame End for virtual channel 1." "0,1" newline bitfld.long 0x0 0. "ERR_F_BNDRY_MATCH_VC0,Error matching Frame Start with Frame End for virtual channel 0." "0,1" group.long 0x104++0x7 line.long 0x0 "INT_MSK_FRAME_FATAL,Static read and write register Interrupt mask for INT_ST_FRAME_FATAL controls which interrupt status bits will trigger the interrupt pin. Bit at 1 - Enable the interrupt source. Bit at 0 - Interrupt source is masked." hexmask.long.word 0x0 20.--31. 1. "RESERVED_31_20,Reserved and read as zero." newline bitfld.long 0x0 19. "MASK_ERR_FRAME_DATA_VC3,Mask for err_frame_data_vc3." "0,1" newline bitfld.long 0x0 18. "MASK_ERR_FRAME_DATA_VC2,Mask for err_frame_data_vc2." "0,1" newline bitfld.long 0x0 17. "MASK_ERR_FRAME_DATA_VC1,Mask for err_frame_data_vc1." "0,1" newline bitfld.long 0x0 16. "MASK_ERR_FRAME_DATA_VC0,Mask for err_frame_data_vc0." "0,1" newline hexmask.long.byte 0x0 12.--15. 1. "RESERVED_15_12,Reserved and read as zero." newline bitfld.long 0x0 11. "MASK_ERR_F_SEQ_VC3,Mask for err_f_seq_vc3." "0,1" newline bitfld.long 0x0 10. "MASK_ERR_F_SEQ_VC2,Mask for err_f_seq_vc2." "0,1" newline bitfld.long 0x0 9. "MASK_ERR_F_SEQ_VC1,Mask for err_f_seq_vc1." "0,1" newline bitfld.long 0x0 8. "MASK_ERR_F_SEQ_VC0,Mask for err_f_seq_vc0." "0,1" newline hexmask.long.byte 0x0 4.--7. 1. "RESERVED_7_4,Reserved and read as zero." newline bitfld.long 0x0 3. "MASK_ERR_F_BNDRY_MATCH_VC3,Mask for err_f_bndry_match_vc3." "0,1" newline bitfld.long 0x0 2. "MASK_ERR_F_BNDRY_MATCH_VC2,Mask for err_f_bndry_match_vc2." "0,1" newline bitfld.long 0x0 1. "MASK_ERR_F_BNDRY_MATCH_VC1,Mask for err_f_bndry_match_vc1." "0,1" newline bitfld.long 0x0 0. "MASK_ERR_F_BNDRY_MATCH_VC0,Mask for err_f_bndry_match_vc0." "0,1" line.long 0x4 "INT_FORCE_FRAME_FATAL,Static read and write register Interrupt force register is used for test purposes. and allows triggering INT_ST_FRAME_FATAL interrupt events individually. without the need to activate the conditions that trigger the interrupt.." hexmask.long.word 0x4 20.--31. 1. "RESERVED_31_20,Reserved and read as zero." newline bitfld.long 0x4 19. "FORCE_ERR_FRAME_DATA_VC3,Force err_frame_data_vc3." "0,1" newline bitfld.long 0x4 18. "FORCE_ERR_FRAME_DATA_VC2,Force err_frame_data_vc2." "0,1" newline bitfld.long 0x4 17. "FORCE_ERR_FRAME_DATA_VC1,Force err_frame_data_vc1." "0,1" newline bitfld.long 0x4 16. "FORCE_ERR_FRAME_DATA_VC0,Force err_frame_data_vc0." "0,1" newline hexmask.long.byte 0x4 12.--15. 1. "RESERVED_15_12,Reserved and read as zero." newline bitfld.long 0x4 11. "FORCE_ERR_F_SEQ_VC3,Force err_f_seq_vc3." "0,1" newline bitfld.long 0x4 10. "FORCE_ERR_F_SEQ_VC2,Force err_f_seq_vc2." "0,1" newline bitfld.long 0x4 9. "FORCE_ERR_F_SEQ_VC1,Force err_f_seq_vc1." "0,1" newline bitfld.long 0x4 8. "FORCE_ERR_F_SEQ_VC0,Force err_f_seq_vc0." "0,1" newline hexmask.long.byte 0x4 4.--7. 1. "RESERVED_7_4,Reserved and read as zero." newline bitfld.long 0x4 3. "FORCE_ERR_F_BNDRY_MATCH_VC3,Force err_f_bndry_match_vc3." "0,1" newline bitfld.long 0x4 2. "FORCE_ERR_F_BNDRY_MATCH_VC2,Force err_f_bndry_match_vc2." "0,1" newline bitfld.long 0x4 1. "FORCE_ERR_F_BNDRY_MATCH_VC1,Force err_f_bndry_match_vc1." "0,1" newline bitfld.long 0x4 0. "FORCE_ERR_F_BNDRY_MATCH_VC0,Force err_f_bndry_match_vc0." "0,1" rgroup.long 0x110++0x3 line.long 0x0 "INT_ST_PHY,Clear on read register Interruption caused by PHY. Groups and notifies which interruption bits caused the interruption. Stores the source of the error. Reading INT_ST_PHY register does not clear the interrupt pin." hexmask.long.byte 0x0 24.--31. 1. "RESERVED_31_24,Reserved and read as zero." newline bitfld.long 0x0 23. "RESERVED_23,Reserved and read as zero" "0,1" newline bitfld.long 0x0 22. "RESERVED_22,Reserved and read as zero" "0,1" newline bitfld.long 0x0 21. "RESERVED_21,Reserved and read as zero" "0,1" newline bitfld.long 0x0 20. "RESERVED_20,Reserved and read as zero" "0,1" newline bitfld.long 0x0 19. "PHY_ERRESC_3,Start of Transmission Error on data lane 3 (no synchronization achieved)" "0,1" newline bitfld.long 0x0 18. "PHY_ERRESC_2,Start of Transmission Error on data lane 2 (no synchronization achieved)" "0,1" newline bitfld.long 0x0 17. "PHY_ERRESC_1,Start of Transmission Error on data lane 1 (no synchronization achieved)" "0,1" newline bitfld.long 0x0 16. "PHY_ERRESC_0,Start of Transmission Error on data lane 0 (no synchronization achieved)." "0,1" newline hexmask.long.byte 0x0 8.--15. 1. "RESERVED_15_8,Reserved and read as zero." newline bitfld.long 0x0 7. "RESERVED_7,Reserved and read as zero" "0,1" newline bitfld.long 0x0 6. "RESERVED_6,Reserved and read as zero" "0,1" newline bitfld.long 0x0 5. "RESERVED_5,Reserved and read as zero" "0,1" newline bitfld.long 0x0 4. "RESERVED_4,Reserved and read as zero" "0,1" newline bitfld.long 0x0 3. "PHY_ERRSOTHS_3,Start of transmission error on data lane 3 (synchronization can still be achieved)" "0,1" newline bitfld.long 0x0 2. "PHY_ERRSOTHS_2,Start of transmission error on data lane 2 (synchronization can still be achieved)" "0,1" newline bitfld.long 0x0 1. "PHY_ERRSOTHS_1,Start of transmission error on data lane 1 (synchronization can still be achieved)" "0,1" newline bitfld.long 0x0 0. "PHY_ERRSOTHS_0,Start of transmission error on data lane 0 (synchronization can still be achieved)." "0,1" group.long 0x114++0x7 line.long 0x0 "INT_MSK_PHY,Static read and write register Interrupt mask for INT_ST_PHY controls which interrupt status bits will trigger the interrupt pin. Bit at 1 - Enable the interrupt source. Bit at 0 - Interrupt source is masked." hexmask.long.byte 0x0 24.--31. 1. "RESERVED_31_24,Reserved and read as zero." newline rbitfld.long 0x0 23. "RESERVED_23,Reserved and read as zero" "0,1" newline rbitfld.long 0x0 22. "RESERVED_22,Reserved and read as zero" "0,1" newline rbitfld.long 0x0 21. "RESERVED_21,Reserved and read as zero" "0,1" newline rbitfld.long 0x0 20. "RESERVED_20,Reserved and read as zero" "0,1" newline bitfld.long 0x0 19. "MASK_PHY_ERRESC_3,Mask for phy_erresc_3" "0,1" newline bitfld.long 0x0 18. "MASK_PHY_ERRESC_2,Mask for phy_erresc_2" "0,1" newline bitfld.long 0x0 17. "MASK_PHY_ERRESC_1,Mask for phy_erresc_1" "0,1" newline bitfld.long 0x0 16. "MASK_PHY_ERRESC_0,Mask for phy_erresc_0." "0,1" newline hexmask.long.byte 0x0 8.--15. 1. "RESERVED_15_8,Reserved and read as zero." newline rbitfld.long 0x0 7. "RESERVED_7,Reserved and read as zero" "0,1" newline rbitfld.long 0x0 6. "RESERVED_6,Reserved and read as zero" "0,1" newline rbitfld.long 0x0 5. "RESERVED_5,Reserved and read as zero" "0,1" newline rbitfld.long 0x0 4. "RESERVED_4,Reserved and read as zero" "0,1" newline bitfld.long 0x0 3. "MASK_PHY_ERRSOTHS_3,Mask for phy_errsoths_3" "0,1" newline bitfld.long 0x0 2. "MASK_PHY_ERRSOTHS_2,Mask for phy_errsoths_2" "0,1" newline bitfld.long 0x0 1. "MASK_PHY_ERRSOTHS_1,Mask for phy_errsoths_1" "0,1" newline bitfld.long 0x0 0. "MASK_PHY_ERRSOTHS_0,Mask for phy_errsoths_0." "0,1" line.long 0x4 "INT_FORCE_PHY,Static read and write register Interrupt force register is used for test purposes. and allows triggering INT_ST_PHY interrupt events individually. without the need to activate the conditions that trigger the interrupt sources. because it.." hexmask.long.byte 0x4 24.--31. 1. "RESERVED_31_24,Reserved and read as zero." newline rbitfld.long 0x4 23. "RESERVED_23,Reserved and read as zero" "0,1" newline rbitfld.long 0x4 22. "RESERVED_22,Reserved and read as zero" "0,1" newline rbitfld.long 0x4 21. "RESERVED_21,Reserved and read as zero" "0,1" newline rbitfld.long 0x4 20. "RESERVED_20,Reserved and read as zero" "0,1" newline bitfld.long 0x4 19. "FORCE_PHY_ERRESC_3,Force phy_erresc_3" "0,1" newline bitfld.long 0x4 18. "FORCE_PHY_ERRESC_2,Force phy_erresc_2" "0,1" newline bitfld.long 0x4 17. "FORCE_PHY_ERRESC_1,Force phy_erresc_1" "0,1" newline bitfld.long 0x4 16. "FORCE_PHY_ERRESC_0,Force phy_erresc_0" "0,1" newline hexmask.long.byte 0x4 8.--15. 1. "RESERVED_15_8,Reserved and read as zero." newline rbitfld.long 0x4 7. "RESERVED_7,Reserved and read as zero" "0,1" newline rbitfld.long 0x4 6. "RESERVED_6,Reserved and read as zero" "0,1" newline rbitfld.long 0x4 5. "RESERVED_5,Reserved and read as zero" "0,1" newline rbitfld.long 0x4 4. "RESERVED_4,Reserved and read as zero" "0,1" newline bitfld.long 0x4 3. "FORCE_PHY_ERRSOTHS_3,Force phy_errsoths_3" "0,1" newline bitfld.long 0x4 2. "FORCE_PHY_ERRSOTHS_2,Force phy_errsoths_2" "0,1" newline bitfld.long 0x4 1. "FORCE_PHY_ERRSOTHS_1,Force phy_errsoths_1" "0,1" newline bitfld.long 0x4 0. "FORCE_PHY_ERRSOTHS_0,Force phy_errsoths_0." "0,1" rgroup.long 0x120++0x3 line.long 0x0 "INT_ST_PKT,Clear on read register Interruption related with Packet construction. Packet discarded. Groups and notifies which interruption bits caused the interruption. Stores the source of the error. Reading INT_ST_PKT register does not clear the.." hexmask.long.word 0x0 20.--31. 1. "RESERVED_31_20,Reserved and read as zero." newline bitfld.long 0x0 19. "VC3_ERR_ECC_CORRECTED,D-PHY mode : Header error detected and corrected on virtual channel 3. C-PHY mode : Header CRC recoverable on virtual channel 3." "0,1" newline bitfld.long 0x0 18. "VC2_ERR_ECC_CORRECTED,D-PHY mode : Header error detected and corrected on virtual channel 2. C-PHY mode : Header CRC recoverable on virtual channel 2." "0,1" newline bitfld.long 0x0 17. "VC1_ERR_ECC_CORRECTED,D-PHY mode : Header error detected and corrected on virtual channel 1. C-PHY mode : Header CRC recoverable on virtual channel 1." "0,1" newline bitfld.long 0x0 16. "VC0_ERR_ECC_CORRECTED,D-PHY mode : Header error detected and corrected on virtual channel 0. C-PHY mode : Header CRC recoverable on virtual channel 0." "0,1" newline hexmask.long.word 0x0 4.--15. 1. "RESERVED_15_4,Reserved and read as zero." newline bitfld.long 0x0 3. "ERR_ID_VC3,Unrecognized or unimplemented data type detected in virtual channel 3." "0,1" newline bitfld.long 0x0 2. "ERR_ID_VC2,Unrecognized or unimplemented data type detected in virtual channel 2." "0,1" newline bitfld.long 0x0 1. "ERR_ID_VC1,Unrecognized or unimplemented data type detected in virtual channel 1." "0,1" newline bitfld.long 0x0 0. "ERR_ID_VC0,Unrecognized or unimplemented data type detected in virtual channel 0." "0,1" group.long 0x124++0x7 line.long 0x0 "INT_MSK_PKT,Static read and write register Interrupt mask for INT_ST_PKT controls which interrupt status bits will trigger the interrupt pin. Bit at 1 - Enable the interrupt source. Bit at 0 - Interrupt source is masked." hexmask.long.word 0x0 20.--31. 1. "RESERVED_31_20,Reserved and read as zero." newline bitfld.long 0x0 19. "MASK_VC3_ERR_ECC_CORRECTED,Mask for vc3_err_ecc_corrected." "0,1" newline bitfld.long 0x0 18. "MASK_VC2_ERR_ECC_CORRECTED,Mask for vc2_err_ecc_corrected." "0,1" newline bitfld.long 0x0 17. "MASK_VC1_ERR_ECC_CORRECTED,Mask for vc1_err_ecc_corrected." "0,1" newline bitfld.long 0x0 16. "MASK_VC0_ERR_ECC_CORRECTED,Mask for vc0_err_ecc_corrected." "0,1" newline hexmask.long.word 0x0 4.--15. 1. "RESERVED_15_4,Reserved and read as zero." newline bitfld.long 0x0 3. "MASK_ERR_ID_VC3,Mask for err_id_vc3." "0,1" newline bitfld.long 0x0 2. "MASK_ERR_ID_VC2,Mask for err_id_vc2." "0,1" newline bitfld.long 0x0 1. "MASK_ERR_ID_VC1,Mask for err_id_vc1." "0,1" newline bitfld.long 0x0 0. "MASK_ERR_ID_VC0,Mask for err_id_vc0." "0,1" line.long 0x4 "INT_FORCE_PKT,Static read and write register Interrupt force register is used for test purposes. and allows triggering INT_ST_PKT interrupt events individually. without the need to activate the conditions that trigger the interrupt sources. because it.." hexmask.long.word 0x4 20.--31. 1. "RESERVED_31_20,Reserved and read as zero." newline bitfld.long 0x4 19. "FORCE_VC3_ERR_ECC_CORRECTED,Force vc3_err_ecc_corrected." "0,1" newline bitfld.long 0x4 18. "FORCE_VC2_ERR_ECC_CORRECTED,Force vc2_err_ecc_corrected." "0,1" newline bitfld.long 0x4 17. "FORCE_VC1_ERR_ECC_CORRECTED,Force vc1_err_ecc_corrected." "0,1" newline bitfld.long 0x4 16. "FORCE_VC0_ERR_ECC_CORRECTED,Force vc0_err_ecc_corrected." "0,1" newline hexmask.long.word 0x4 4.--15. 1. "RESERVED_15_4,Reserved and read as zero." newline bitfld.long 0x4 3. "FORCE_ERR_ID_VC3,Force err_id_vc3." "0,1" newline bitfld.long 0x4 2. "FORCE_ERR_ID_VC2,Force err_id_vc2." "0,1" newline bitfld.long 0x4 1. "FORCE_ERR_ID_VC1,Force err_id_vc1." "0,1" newline bitfld.long 0x4 0. "FORCE_ERR_ID_VC0,Force err_id_vc0." "0,1" rgroup.long 0x130++0x3 line.long 0x0 "INT_ST_LINE,Clear on read register Interruption related with Line construction. Groups and notifies which interruption bits caused the interruption. Stores the source of the error. Reading INT_ST_LINE register does not clear the interrupt pin." hexmask.long.byte 0x0 24.--31. 1. "RESERVED_31_24,Reserved and read as zero." newline bitfld.long 0x0 23. "ERR_L_SEQ_DI7,Error in the sequence of lines for vc7 and dt7" "0,1" newline bitfld.long 0x0 22. "ERR_L_SEQ_DI6,Error in the sequence of lines for vc6 and dt6" "0,1" newline bitfld.long 0x0 21. "ERR_L_SEQ_DI5,Error in the sequence of lines for vc5 and dt5" "0,1" newline bitfld.long 0x0 20. "ERR_L_SEQ_DI4,Error in the sequence of lines for vc4 and dt4" "0,1" newline bitfld.long 0x0 19. "ERR_L_SEQ_DI3,Error in the sequence of lines for vc3 and dt3" "0,1" newline bitfld.long 0x0 18. "ERR_L_SEQ_DI2,Error in the sequence of lines for vc2 and dt2" "0,1" newline bitfld.long 0x0 17. "ERR_L_SEQ_DI1,Error in the sequence of lines for vc1 and dt1" "0,1" newline bitfld.long 0x0 16. "ERR_L_SEQ_DI0,Error in the sequence of lines for vc0 and dt0" "0,1" newline hexmask.long.byte 0x0 8.--15. 1. "RESERVED_15_8,Reserved and read as zero." newline bitfld.long 0x0 7. "ERR_L_BNDRY_MATCH_DI7,Error matching line start with line end for vc7 and dt7" "0,1" newline bitfld.long 0x0 6. "ERR_L_BNDRY_MATCH_DI6,Error matching line start with line end for vc6 and dt6" "0,1" newline bitfld.long 0x0 5. "ERR_L_BNDRY_MATCH_DI5,Error matching line start with line end for vc5 and dt5" "0,1" newline bitfld.long 0x0 4. "ERR_L_BNDRY_MATCH_DI4,Error matching line start with line end for vc4 and dt4" "0,1" newline bitfld.long 0x0 3. "ERR_L_BNDRY_MATCH_DI3,Error matching line start with line end for vc3 and dt3" "0,1" newline bitfld.long 0x0 2. "ERR_L_BNDRY_MATCH_DI2,Error matching line start with line end for vc2 and dt2" "0,1" newline bitfld.long 0x0 1. "ERR_L_BNDRY_MATCH_DI1,Error matching line start with line end for vc1 and dt1" "0,1" newline bitfld.long 0x0 0. "ERR_L_BNDRY_MATCH_DI0,Error matching line start with line end for vc0 and dt0" "0,1" group.long 0x134++0x7 line.long 0x0 "INT_MSK_LINE,Static read and write register Interrupt mask for INT_ST_LINE controls which interrupt status bits will trigger the interrupt pin. Bit at 1 - Enable the interrupt source. Bit at 0 - Interrupt source is masked." hexmask.long.byte 0x0 24.--31. 1. "RESERVED_31_24,Reserved and read as zero." newline bitfld.long 0x0 23. "MASK_ERR_L_SEQ_DI7,Mask for err_l_seq_di7" "0,1" newline bitfld.long 0x0 22. "MASK_ERR_L_SEQ_DI6,Mask for err_l_seq_di6" "0,1" newline bitfld.long 0x0 21. "MASK_ERR_L_SEQ_DI5,Mask for err_l_seq_di5" "0,1" newline bitfld.long 0x0 20. "MASK_ERR_L_SEQ_DI4,Mask for err_l_seq_di4" "0,1" newline bitfld.long 0x0 19. "MASK_ERR_L_SEQ_DI3,Mask for err_l_seq_di3" "0,1" newline bitfld.long 0x0 18. "MASK_ERR_L_SEQ_DI2,Mask for err_l_seq_di2" "0,1" newline bitfld.long 0x0 17. "MASK_ERR_L_SEQ_DI1,Mask for err_l_seq_di1" "0,1" newline bitfld.long 0x0 16. "MASK_ERR_L_SEQ_DI0,Mask for err_l_seq_di0" "0,1" newline hexmask.long.byte 0x0 8.--15. 1. "RESERVED_15_8,Reserved and read as zero." newline bitfld.long 0x0 7. "MASK_ERR_L_BNDRY_MATCH_DI7,Mask for err_l_bndry_match_di7" "0,1" newline bitfld.long 0x0 6. "MASK_ERR_L_BNDRY_MATCH_DI6,Mask for err_l_bndry_match_di6" "0,1" newline bitfld.long 0x0 5. "MASK_ERR_L_BNDRY_MATCH_DI5,Mask for err_l_bndry_match_di5" "0,1" newline bitfld.long 0x0 4. "MASK_ERR_L_BNDRY_MATCH_DI4,Mask for err_l_bndry_match_di4" "0,1" newline bitfld.long 0x0 3. "MASK_ERR_L_BNDRY_MATCH_DI3,Mask for err_l_bndry_match_di3" "0,1" newline bitfld.long 0x0 2. "MASK_ERR_L_BNDRY_MATCH_DI2,Mask for err_l_bndry_match_di2" "0,1" newline bitfld.long 0x0 1. "MASK_ERR_L_BNDRY_MATCH_DI1,Mask for err_l_bndry_match_di1" "0,1" newline bitfld.long 0x0 0. "MASK_ERR_L_BNDRY_MATCH_DI0,Mask for err_l_bndry_match_di0" "0,1" line.long 0x4 "INT_FORCE_LINE,Static read and write register Interrupt force register is used for test purposes. and allows triggering INT_ST_LINE interrupt events individually. without the need to activate the conditions that trigger the interrupt sources. because it.." hexmask.long.byte 0x4 24.--31. 1. "RESERVED_31_24,Reserved and read as zero." newline bitfld.long 0x4 23. "FORCE_ERR_L_SEQ_DI7,Force err_l_seq_di7" "0,1" newline bitfld.long 0x4 22. "FORCE_ERR_L_SEQ_DI6,Force err_l_seq_di6" "0,1" newline bitfld.long 0x4 21. "FORCE_ERR_L_SEQ_DI5,Force err_l_seq_di5" "0,1" newline bitfld.long 0x4 20. "FORCE_ERR_L_SEQ_DI4,Force err_l_seq_di4" "0,1" newline bitfld.long 0x4 19. "FORCE_ERR_L_SEQ_DI3,Force err_l_seq_di3" "0,1" newline bitfld.long 0x4 18. "FORCE_ERR_L_SEQ_DI2,Force err_l_seq_di2" "0,1" newline bitfld.long 0x4 17. "FORCE_ERR_L_SEQ_DI1,Force err_l_seq_di1" "0,1" newline bitfld.long 0x4 16. "FORCE_ERR_L_SEQ_DI0,Force err_l_seq_di0" "0,1" newline hexmask.long.byte 0x4 8.--15. 1. "RESERVED_15_8,Reserved and read as zero." newline bitfld.long 0x4 7. "FORCE_ERR_L_BNDRY_MATCH_DI7,Force err_l_bndry_match_di7" "0,1" newline bitfld.long 0x4 6. "FORCE_ERR_L_BNDRY_MATCH_DI6,Force err_l_bndry_match_di6" "0,1" newline bitfld.long 0x4 5. "FORCE_ERR_L_BNDRY_MATCH_DI5,Force err_l_bndry_match_di5" "0,1" newline bitfld.long 0x4 4. "FORCE_ERR_L_BNDRY_MATCH_DI4,Force err_l_bndry_match_di4" "0,1" newline bitfld.long 0x4 3. "FORCE_ERR_L_BNDRY_MATCH_DI3,Force err_l_bndry_match_di3" "0,1" newline bitfld.long 0x4 2. "FORCE_ERR_L_BNDRY_MATCH_DI2,Force err_l_bndry_match_di2" "0,1" newline bitfld.long 0x4 1. "FORCE_ERR_L_BNDRY_MATCH_DI1,Force err_l_bndry_match_di1" "0,1" newline bitfld.long 0x4 0. "FORCE_ERR_L_BNDRY_MATCH_DI0,Force err_l_bndry_match_di0" "0,1" rgroup.long 0x140++0x3 line.long 0x0 "INT_ST_IPI,Clear on read register Fatal Interruption caused by IPI interface. Groups and notifies which interruption bits caused the interruption. Stores the source of the error. Reading INT_ST_IPI register does not clear the interrupt pin." hexmask.long 0x0 6.--31. 1. "RESERVED_31_6,Reserved and read as zero." newline bitfld.long 0x0 5. "INT_EVENT_FIFO_OVERFLOW,Reporting internal fifo overflow." "0,1" newline bitfld.long 0x0 4. "PIXEL_IF_HLINE_ERR,Horizontal line time error (only available in controller mode)." "0,1" newline bitfld.long 0x0 3. "PIXEL_IF_FIFO_NEMPTY_FS,The FIFO of pixel interface is not empty at the start of a new frame. If this is expected this interrupt should be masked." "0,1" newline bitfld.long 0x0 2. "PIXEL_IF_FRAME_SYNC_ERR,New frame is received but previous has not been completed." "0,1" newline bitfld.long 0x0 1. "PIXEL_IF_FIFO_OVERFLOW,The FIFO of pixel interface has lost information because some more data arrived when it was full." "0,1" newline bitfld.long 0x0 0. "PIXEL_IF_FIFO_UNDERFLOW,The FIFO has become empty before the expected number of pixels (calculated from the packet's header) could be extracted to the pixel interface." "0,1" group.long 0x144++0x7 line.long 0x0 "INT_MSK_IPI,Static read and write register Interrupt mask for INT_ST_IPI controls which interrupt status bits will trigger the interrupt pin. Bit at 1 - Enable the interrupt source. Bit at 0 - Interrupt source is masked." hexmask.long 0x0 6.--31. 1. "RESERVED_31_6,Reserved and read as zero." newline bitfld.long 0x0 5. "MSK_INT_EVENT_FIFO_OVERFLOW,Mask int_event_fifo_overflow." "0,1" newline bitfld.long 0x0 4. "MSK_PIXEL_IF_HLINE_ERR,Mask pixel_if_hline_err." "0,1" newline bitfld.long 0x0 3. "MSK_PIXEL_IF_FIFO_NEMPTY_FS,Mask pixel_if_fifo_nempty_fs." "0,1" newline bitfld.long 0x0 2. "MSK_FRAME_SYNC_ERR,Mask for pixel_if_frame_sync_err." "0,1" newline bitfld.long 0x0 1. "MSK_PIXEL_IF_FIFO_OVERFLOW,Mask for pixel_if_fifo_overflow." "0,1" newline bitfld.long 0x0 0. "MSK_PIXEL_IF_FIFO_UNDERFLOW,Mask for pixel_if_fifo_underflow." "0,1" line.long 0x4 "INT_FORCE_IPI,Static read and write register Interrupt force register is used for test purposes. and allows triggering INT_ST_IPI interrupt events individually. without the need to activate the conditions that trigger the interrupt sources. because it.." hexmask.long 0x4 6.--31. 1. "RESERVED_31_6,Reserved and read as zero." newline bitfld.long 0x4 5. "FORCE_INT_EVENT_FIFO_OVERFLOW,Force int_event_fifo_overflow." "0,1" newline bitfld.long 0x4 4. "FORCE_PIXEL_IF_HLINE_ERR,Force pixel_if_hline_err." "0,1" newline bitfld.long 0x4 3. "FORCE_PIXEL_IF_FIFO_NEMPTY_FS,Force pixel_if_fifo_nempty_fs." "0,1" newline bitfld.long 0x4 2. "FORCE_FRAME_SYNC_ERR,Force for frame_sync_err." "0,1" newline bitfld.long 0x4 1. "FORCE_PIXEL_IF_FIFO_OVERFLOW,Force for pixel_if_fifo_overflow." "0,1" newline bitfld.long 0x4 0. "FORCE_PIXEL_IF_FIFO_UNDERFLOW,Force for pixel_if_fifo_underflow." "0,1" repeat 3. (list 0x2 0x3 0x4 )(list 0x0 0x10 0x20 ) rgroup.long ($2+0x150)++0x3 line.long 0x0 "INT_ST_IPI$1,Clear on read register Fatal Interruption caused by IPI interface 2. Groups and notifies which interruption bits caused the interruption. Stores the source of the error. Reading INT_ST_IPI2 register does not clear the interrupt pin." hexmask.long 0x0 6.--31. 1. "RESERVED_31_6,Reserved and read as zero." newline bitfld.long 0x0 5. "INT_EVENT_FIFO_OVERFLOW,Reporting internal fifo overflow." "0,1" newline bitfld.long 0x0 4. "PIXEL_IF_HLINE_ERR,Horizontal line time error (only available in controller mode)." "0,1" newline bitfld.long 0x0 3. "PIXEL_IF_FIFO_NEMPTY_FS,The FIFO of pixel interface is not empty at the start of a new frame. If this is expected this interrupt should be masked." "0,1" newline bitfld.long 0x0 2. "PIXEL_IF_FRAME_SYNC_ERR,New frame is received but previous has not been completed." "0,1" newline bitfld.long 0x0 1. "PIXEL_IF_FIFO_OVERFLOW,The FIFO of pixel interface has lost information because some more data arrived when it was full." "0,1" newline bitfld.long 0x0 0. "PIXEL_IF_FIFO_UNDERFLOW,The FIFO has become empty before the expected number of pixels (calculated from the packet's header) could be extracted to the pixel interface." "0,1" repeat.end repeat 3. (list 0x2 0x3 0x4 )(list 0x0 0x10 0x20 ) group.long ($2+0x154)++0x3 line.long 0x0 "INT_MSK_IPI$1,Static read and write register Interrupt mask for INT_ST_IPI2 controls which interrupt status bits will trigger the interrupt pin. Bit at 1 - Enable the interrupt source. Bit at 0 - Interrupt source is masked." hexmask.long 0x0 6.--31. 1. "RESERVED_31_6,Reserved and read as zero." newline bitfld.long 0x0 5. "MSK_INT_EVENT_FIFO_OVERFLOW,Mask int_event_fifo_overflow." "0,1" newline bitfld.long 0x0 4. "MSK_PIXEL_IF_HLINE_ERR,Mask pixel_if_hline_err." "0,1" newline bitfld.long 0x0 3. "MSK_PIXEL_IF_FIFO_NEMPTY_FS,Mask pixel_if_fifo_nempty_fs." "0,1" newline bitfld.long 0x0 2. "MSK_FRAME_SYNC_ERR,Mask for pixel_if_frame_sync_err." "0,1" newline bitfld.long 0x0 1. "MSK_PIXEL_IF_FIFO_OVERFLOW,Mask for pixel_if_fifo_overflow." "0,1" newline bitfld.long 0x0 0. "MSK_PIXEL_IF_FIFO_UNDERFLOW,Mask for pixel_if_fifo_underflow." "0,1" repeat.end repeat 3. (list 0x2 0x3 0x4 )(list 0x0 0x10 0x20 ) group.long ($2+0x158)++0x3 line.long 0x0 "INT_FORCE_IPI$1,Static read and write register Interrupt force register is used for test purposes. and allows triggering INT_ST_IPI2 interrupt events individually. without the need to activate the conditions that trigger the interrupt sources. because it.." hexmask.long 0x0 6.--31. 1. "RESERVED_31_6,Reserved and read as zero." newline bitfld.long 0x0 5. "FORCE_INT_EVENT_FIFO_OVERFLOW,Force int_event_fifo_overflow." "0,1" newline bitfld.long 0x0 4. "FORCE_PIXEL_IF_HLINE_ERR,Force pixel_if_hline_err." "0,1" newline bitfld.long 0x0 3. "FORCE_PIXEL_IF_FIFO_NEMPTY_FS,Force pixel_if_fifo_nempty_fs." "0,1" newline bitfld.long 0x0 2. "FORCE_FRAME_SYNC_ERR,Force for frame_sync_err." "0,1" newline bitfld.long 0x0 1. "FORCE_PIXEL_IF_FIFO_OVERFLOW,Force for pixel_if_fifo_overflow." "0,1" newline bitfld.long 0x0 0. "FORCE_PIXEL_IF_FIFO_UNDERFLOW,Force for pixel_if_fifo_underflow." "0,1" repeat.end rgroup.long 0x180++0x3 line.long 0x0 "INT_ST_AP_GENERIC,Clear on read register Groups and notifies which interruption bits caused the interruption. Stores the source of the error. Reading INT_ST_AP_GENERIC register clears the interrupt pin." hexmask.long.word 0x0 20.--31. 1. "RESERVED_31_20,Reserved and read as zero." newline bitfld.long 0x0 19. "SYNCHRONIZER_PIXCLK_4IF_AP_ERR,AP error in synchronizer block for pixclk_4if domain" "0,1" newline bitfld.long 0x0 18. "SYNCHRONIZER_PIXCLK_3IF_AP_ERR,AP error in synchronizer block for pixclk_3if domain" "0,1" newline bitfld.long 0x0 17. "SYNCHRONIZER_PIXCLK_2IF_AP_ERR,AP error in synchronizer block for pixclk_2if domain" "0,1" newline bitfld.long 0x0 16. "SYNCHRONIZER_PIXCLK_AP_ERR,AP error in synchronizer block for pixclk domain" "0,1" newline bitfld.long 0x0 15. "SYNCHRONIZER_RXBYTECLKHS_AP_ERR,AP error in synchronizer block for rxbyteclkhs domain" "0,1" newline bitfld.long 0x0 14. "SYNCHRONIZER_FPCLK_AP_ERR,AP error in synchronizer block for fpclk domain." "0,1" newline bitfld.long 0x0 13. "ERR_HANDLER_AP_ERR,AP error in Error Handler block." "0,1" newline bitfld.long 0x0 12. "ERR_MSGR_AP_ERR,AP error in Err Msgr block." "0,1" newline bitfld.long 0x0 10.--11. "PREP_OUTS_AP_ERR,AP error in Prepare Outs block.: -01: parity error -10: redundancy error" "?,parity error,?,?" newline bitfld.long 0x0 8.--9. "PACKET_ANALYZER_AP_ERR,AP error in Packet analyzer block.: -01: parity error -10: redundancy error2: Choosen by MSTR2.target_frequency register. Programming Mode: Quasi-dynamic Group 2" "Original registers,When UMCTL2_FREQUENCY_NUM=2: FREQ1 registers" newline rbitfld.long 0x0 26.--28. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 24.--25. "ACTIVE_RANKS,Only present for multi-rank configurations. Each bit represents one rank. For two-rank configurations only bits[25:24] are present. - 1 - Populated - 0 - Unpopulated LSB is the lowest rank number. For two ranks following combinations are.." "Unpopulated,One rank,?,?" newline hexmask.long.byte 0x0 20.--23. 1. "RESERVED,Reserved" newline hexmask.long.byte 0x0 16.--19. 1. "BURST_RDWR,Indicates SDRAM burst length used: - 0001 - Burst length of 2 (only supported for mDDR) - 0010 - Burst length of 4 - 0100 - Burst length of 8 - 1000 - Burst length of 16 (only supported for mDDR LPDDR2 and LPDDR4) All other values are.." newline bitfld.long 0x0 15. "DLL_OFF_MODE,Set to: - 1 - When the uMCTL2 and DRAM has to be put in DLL-off mode for low frequency operation - 0 - To put uMCTL2 and DRAM in DLL-on mode for normal frequency operation If DDR4 CRC/parity retry is enabled.." "To put uMCTL2 and DRAM in DLL-on mode for normal..,When the uMCTL2 and DRAM has to be put in.." newline rbitfld.long 0x0 14. "RESERVED,Reserved" "0,1" newline bitfld.long 0x0 12.--13. "DATA_BUS_WIDTH,Selects proportion of DQ bus width that is used by the SDRAM. - 00 - Full DQ bus width to SDRAM - 01 - Half DQ bus width to SDRAM - 10 - Quarter DQ bus width to SDRAM - 11 - Reserved Note that half bus width mode is only supported when the.." "Full DQ bus width to SDRAM,Half DQ bus width to SDRAM,?,?" newline bitfld.long 0x0 11. "GEARDOWN_MODE,- 1 - Indicates the DRAM in geardown mode (2N) - 0 - Indicates the DRAM in normal mode (1N) This register can be changed only when the controller is in the self-refresh mode. This signal must be set the same value as MR3 bit A3. Note: -.." "Indicates the DRAM in normal mode,Indicates the DRAM in geardown mode" newline bitfld.long 0x0 10. "EN_2T_TIMING_MODE,If 1 then uMCTL2 uses 2T timing otherwise uses 1T timing. In 2T timing all command signals (except chip select) are held for 2 clocks on the SDRAM bus. Chip select is asserted on the second cycle of the command. Note: - 2T timing is.." "0,1" newline bitfld.long 0x0 9. "BURSTCHOP,When this bit is set enables burst-chop (BC4 or 8 on-the-fly) in DDR3/DDR4. Burst Chop for reads is exercised only: - In HIF configurations (UMCTL2_INCL_ARB not set) - If in full bus width mode (MSTR.data_bus_width = 00) - If.." "0,1" newline rbitfld.long 0x0 6.--8. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 5. "LPDDR4,Selects LPDDR4 SDRAM. - 1 - LPDDR4 SDRAM device in use - 0 - non-LPDDR4 device in use Present only in designs configured to support LPDDR4. Programming Mode: Static" "non-LPDDR4 device in use,LPDDR4 SDRAM device in use" newline bitfld.long 0x0 4. "DDR4,Selects DDR4 SDRAM. - 1 - DDR4 SDRAM device in use - 0 - non-DDR4 device in use Present only in designs configured to support DDR4. Programming Mode: Static" "non-DDR4 device in use,DDR4 SDRAM device in use" newline bitfld.long 0x0 3. "LPDDR3,Selects LPDDR3 SDRAM. - 1 - LPDDR3 SDRAM device in use - 0 - non-LPDDR3 device in use Present only in designs configured to support LPDDR3. Programming Mode: Static" "non-LPDDR3 device in use,LPDDR3 SDRAM device in use" newline bitfld.long 0x0 2. "LPDDR2,Selects LPDDR2 SDRAM. - 1 - LPDDR2 SDRAM device in use - 0 - non-LPDDR2 device in use Present only in designs configured to support LPDDR2. Programming Mode: Static" "non-LPDDR2 device in use,LPDDR2 SDRAM device in use" newline rbitfld.long 0x0 1. "RESERVED,Reserved" "0,1" newline bitfld.long 0x0 0. "DDR3,Selects DDR3 SDRAM. - 1 - DDR3 SDRAM device in use - 0 - non-DDR3 SDRAM device in use Present only in designs configured to support DDR3. Programming Mode: Static" "non-DDR3 SDRAM device in use,DDR3 SDRAM device in use" rgroup.long 0x4++0x3 line.long 0x0 "STAT,Operating Mode Status Register" hexmask.long.tbyte 0x0 13.--31. 1. "RESERVED,Reserved" newline bitfld.long 0x0 12. "SELFREF_CAM_NOT_EMPTY,Self-refresh with CAMs not empty. Set to 1 when self-refresh is entered but CAMs are not drained. Cleared after exiting self-refresh. Programming Mode: Static" "0,1" newline bitfld.long 0x0 10.--11. "RESERVED,Reserved" "0,1,2,3" newline bitfld.long 0x0 8.--9. "SELFREF_STATE,This indicates self-refresh or self-refresh power down state for LPDDR4. This register is used for frequency change and MRR/MRW access during self-refresh. - 00 - SDRAM is not in self-refresh - 01 - Self-refresh 1 - 10 - Self-refresh power.." "SDRAM is not in self-refresh,Self-refresh 1,?,?" newline bitfld.long 0x0 6.--7. "RESERVED,Reserved" "0,1,2,3" newline bitfld.long 0x0 4.--5. "SELFREF_TYPE,Flags if self-refresh (except LPDDR4) or SR-Powerdown (LPDDR4) is entered and if it is under automatic self-refresh control only or not. - 00 - SDRAM is not in self-refresh (except LPDDR4) or SR-Powerdown (LPDDR4). If retry is enabled by.." "SDRAM is not in self-refresh,SDRAM is in self-refresh,?,?" newline bitfld.long 0x0 3. "RESERVED,Reserved" "0,1" newline bitfld.long 0x0 0.--2. "OPERATING_MODE,This is 3-bits wide in configurations with mDDR/LPDDR2/LPDDR3/LPDDR4/DDR4 support and 2-bits in all other configurations. non-mDDR/LPDDR2/LPDDR3/LPDDR4 and non-DDR4 designs: - 00 - Init - 01 - Normal - 10 - Power-down - 11 - Self-refresh.." "Init,Normal,?,bits wide in configurations with..,?,?,?,?" group.long 0x10++0x7 line.long 0x0 "MRCTRL0,Mode Register Read/Write Control Register 0. Note: Do not enable more than one of the following fields simultaneously: - sw_init_int - pda_en - mpr_en" bitfld.long 0x0 31. "MR_WR,Setting this register bit to 1 triggers a mode register read or write operation. When the MR operation is complete the uMCTL2 automatically clears this bit. The other fields of this register must be written in a separate APB transaction before.." "0,1" newline bitfld.long 0x0 30. "PBA_MODE,Indicates whether PBA access is executed. When setting this bit to 1 along with setting pda_en to 1 uMCTL2 initiates PBA access instead of PDA access. - 0 - Per DRAM Addressability mode - 1 - Per Buffer Addressability mode The completion of PBA.." "Per DRAM Addressability mode,Per Buffer Addressability mode" newline hexmask.long.word 0x0 16.--29. 1. "RESERVED,Reserved" newline hexmask.long.byte 0x0 12.--15. 1. "MR_ADDR,Address of the mode register that is to be written to. - 0000 - MR0 - 0001 - MR1 - 0010 - MR2 - 0011 - MR3 - 0100 - MR4 - 0101 - MR5 - 0110 - MR6 - 0111 - MR7 Don't Care for LPDDR2/LPDDR3/LPDDR4 (see MRCTRL1.mr_data for mode register addressing.." newline hexmask.long.byte 0x0 6.--11. 1. "RESERVED,Reserved" newline bitfld.long 0x0 4.--5. "MR_RANK,Controls which rank is accessed by MRCTRL0.mr_wr. Normally it is desired to access all ranks so all bits must be set to 1. However for multi-rank UDIMMs/RDIMMs/LRDIMMs which implement address mirroring it might be necessary to access ranks.." "?,Select rank 0 only,Select rank 1 only,?" newline bitfld.long 0x0 3. "SW_INIT_INT,Indicates whether software intervention is allowed through MRCTRL0/MRCTRL1 before automatic SDRAM initialization routine or not. For DDR4 this bit can be used to initialize the DDR4 RCD (MR7) before automatic SDRAM initialization. For LPDDR4.." "Software intervention is not allowed,Software intervention is allowed" newline bitfld.long 0x0 2. "PDA_EN,Indicates whether the mode register operation is MRS in PDA mode or not. - 0 - MRS - 1 - MRS in Per DRAM Addressability mode Note that when pba_mode=1 PBA access is initiated instead of PDA access. Programming Mode: Dynamic" "MRS,MRS in Per DRAM Addressability mode" newline bitfld.long 0x0 1. "MPR_EN,Indicates whether the mode register operation is MRS or WR/RD for MPR (only supported for DDR4). - 0 - MRS - 1 - WR/RD for MPR Programming Mode: Dynamic" "MRS,WR/RD for MPR" newline bitfld.long 0x0 0. "MR_TYPE,Indicates whether the mode register operation is read or write. Only used for LPDDR2/LPDDR3/LPDDR4/DDR4. - 0 - Write - 1 - Read Programming Mode: Dynamic" "Write,Read" line.long 0x4 "MRCTRL1,Mode Register Read/Write Control Register 1" hexmask.long.word 0x4 18.--31. 1. "RESERVED,Reserved" newline hexmask.long.tbyte 0x4 0.--17. 1. "MR_DATA,Mode register write data for all non-LPDDR2/non-LPDDR3/non-LPDDR4 modes. For LPDDR2/LPDDR3/LPDDR4 MRCTRL1[15:0] are interpreted as: - [15:8] - MR Address - [7:0] - MR data for writes don't care for reads This is 18-bits wide in configurations.." rgroup.long 0x18++0x3 line.long 0x0 "MRSTAT,Mode Register Read/Write Status Register" hexmask.long.tbyte 0x0 9.--31. 1. "RESERVED,Reserved" newline bitfld.long 0x0 8. "PDA_DONE,The SoC might initiate a MR write operation in PDA/PBA mode only if this signal is low. This signal goes: - High when three consecutive MRS commands related to the PDA/PBA mode are issued to the SDRAM - Low when MRCTRL0.pda_en becomes 0.." "Indicates that mode register write operation..,Indicates that mode register write operation.." newline hexmask.long.byte 0x0 1.--7. 1. "RESERVED,Reserved" newline bitfld.long 0x0 0. "MR_WR_BUSY,The SoC might initiate a MR write operation only if this signal is low. This signal goes: - High in the clock after the uMCTL2 accepts the MRW/MRR request - Low when the MRW/MRR command is issued to the SDRAM It is recommended not to perform.." "Indicates that the SoC can initiate a mode..,Indicates that mode register write operation is.." group.long 0x1C++0x1F line.long 0x0 "MRCTRL2,Mode Register Read/Write Control Register 2" hexmask.long 0x0 0.--31. 1. "MR_DEVICE_SEL,Indicates the devices to be selected during the MRS that happens in PDA mode. Each bit is associated with one device. For example bit[0] corresponds to Device 0 bit[1] to Device 1 and so on. - 1 - Indicates that the MRS command must be.." line.long 0x4 "DERATEEN,Temperature Derate Enable Register" hexmask.long.tbyte 0x4 13.--31. 1. "RESERVED,Reserved" newline bitfld.long 0x4 12. "DERATE_MR4_TUF_DIS,Disables use of MR4 TUF flag (MR4[7]) bit. - 0 - Use MR4 TUF flag (MR4[7]) - 1 - Do not use MR4 TUF Flag (MR4[7]) For LPDDR4 it is recommended to set this register to 1. For LPDDR2 and LPDDR3 contact your memory vendor for.." "Use MR4 TUF flag,Do not use MR4 TUF Flag" newline rbitfld.long 0x4 11. "RESERVED,Reserved" "0,1" newline bitfld.long 0x4 8.--10. "RC_DERATE_VALUE,Derate value of tRC for LPDDR4. - 0 - Derating uses +1 - 1 - Derating uses +2 - 2 - Derating uses +3 - 3 - Derating uses +4 Present only in designs configured to support LPDDR4. The required cycles for derating can be determined by.." "Derating uses +1,Derating uses +2,Derating uses +3,Derating uses +4,?,?,?,?" newline hexmask.long.byte 0x4 4.--7. 1. "DERATE_BYTE,This bit indicates which byte of the MRR data is used for derating. The maximum valid value depends on MEMC_DRAM_TOTAL_DATA_WIDTH. Present only in designs configured to support LPDDR2/LPDDR3/LPDDR4. Programming Mode: Static" newline rbitfld.long 0x4 3. "RESERVED,Reserved" "0,1" newline bitfld.long 0x4 1.--2. "DERATE_VALUE,Derate value. - 0 - Derating uses +1 - 1 - Derating uses +2 Present only in designs configured to support LPDDR2/LPDDR3/LPDDR4. Set to 0 for all LPDDR2 speed grades as derating value of +1.875 ns is less than a core_ddrc_core_clk period. For.." "Derating uses +1,Derating uses +2,?,?" newline bitfld.long 0x4 0. "DERATE_ENABLE,Enables derating. - 0 - Timing parameter derating is disabled - 1 - Timing parameter derating is enabled using MR4 read value Present only in designs configured to support LPDDR2/LPDDR3/LPDDR4. This field must be set to '0' for.." "Timing parameter derating is disabled,Timing parameter derating is enabled using MR4.." line.long 0x8 "DERATEINT,Temperature Derate Interval Register" hexmask.long 0x8 0.--31. 1. "MR4_READ_INTERVAL,Interval between two MR4 reads used to derate the timing parameters. Present only in designs configured to support LPDDR2/LPDDR3/LPDDR4. This register must not be set to zero. Unit: DFI clock cycles. Programming Mode: Static" line.long 0xC "MSTR2,Master Register2" hexmask.long 0xC 2.--31. 1. "RESERVED,Reserved" newline bitfld.long 0xC 0.--1. "TARGET_FREQUENCY,If MSTR.frequency_mode = 1 this field specifies the target frequency. - 0 - Frequency 0/Normal - 1 - Frequency 1/FREQ1 - 2 - Frequency 2/FREQ2 - 3 - Frequency 3/FREQ3 If MSTR.frequency_mode=0 this field is ignored. Note: If the target.." "Frequency 0/Normal,Frequency 1/FREQ1,Frequency 2/FREQ2,Frequency 3/FREQ3" line.long 0x10 "DERATECTL,Temperature Derate Control Register" hexmask.long 0x10 3.--31. 1. "RESERVED,Reserved" newline bitfld.long 0x10 2. "DERATE_TEMP_LIMIT_INTR_FORCE,Interrupt force bit for derate_temp_limit_intr. Setting this field to 1 causes the derate_temp_limit_intr output pin to be asserted. At the end of the interrupt force operation the uMCTL2 automatically clears this bit." "0,1" newline bitfld.long 0x10 1. "DERATE_TEMP_LIMIT_INTR_CLR,Interrupt clear bit for derate_temp_limit_intr. At the end of the interrupt clear operation the uMCTL2 automatically clears this bit. Programming Mode: Dynamic" "0,1" newline bitfld.long 0x10 0. "DERATE_TEMP_LIMIT_INTR_EN,Interrupt enable bit for derate_temp_limit_intr output pin. - 1 - Enabled - 0 - Disabled Programming Mode: Dynamic" "Disabled,Enabled" line.long 0x14 "PWRCTL,Low Power Control Register" hexmask.long.tbyte 0x14 9.--31. 1. "RESERVED,Reserved" newline bitfld.long 0x14 8. "LPDDR4_SR_ALLOWED,Indicates whether transition from SR-PD to SR and back to SR-PD is allowed. This register field cannot be modified while PWRCTL.selfref_sw == 1. - 0 - SR-PD -> SR -> SR-PD not allowed - 1 - SR-PD -> SR -> SR-PD allowed Programming Mode:.." "SR-PD,SR-PD" newline bitfld.long 0x14 7. "DIS_CAM_DRAIN_SELFREF,Indicates whether skipping CAM draining is allowed when entering self-refresh. This register field cannot be modified while PWRCTL.selfref_sw == 1. - 0 - CAMs must be empty before entering SR - 1 - CAMs are not emptied before.." "CAMs must be empty before entering SR,CAMs are not emptied before entering SR" newline bitfld.long 0x14 6. "STAY_IN_SELFREF,Self-refresh state is an intermediate state to enter to self-refresh power down state or exit self-refresh power down state for LPDDR4. This register controls transition from the self-refresh state. - 1 - Prohibit transition from.." "Allow transition from self-refresh state,Prohibit transition from self-refresh state" newline bitfld.long 0x14 5. "SELFREF_SW,A value of 1 to this register causes system to move to self-refresh state immediately as long as it is not in INIT or DPD/MPSM operating_mode. This is referred to as Software Entry/Exit to self-refresh. - 1 - Software Entry to self-refresh -.." "Software Exit from self-refresh,Software Entry to self-refresh" newline bitfld.long 0x14 4. "MPSM_EN,When this bit is 1 the uMCTL2 puts the SDRAM into maximum power saving mode when the transaction store is empty. This register must be reset to '0' to bring uMCTL2 out of maximum power saving mode. Present only in designs configured to support.." "0,1" newline bitfld.long 0x14 3. "EN_DFI_DRAM_CLK_DISABLE,Enables the assertion of dfi_dram_clk_disable whenever a clock is not required by the SDRAM. If set to 0 dfi_dram_clk_disable is never asserted. Assertion of dfi_dram_clk_disable is as follows: In DDR2/DDR3 can only be asserted.." "0,1" newline bitfld.long 0x14 2. "DEEPPOWERDOWN_EN,When this bit is 1 uMCTL2 puts the SDRAM into deep power-down mode when the transaction store is empty. This register must be reset to '0' to bring uMCTL2 out of deep power-down mode. The controller performs automatic SDRAM.." "0,1" newline bitfld.long 0x14 1. "POWERDOWN_EN,If true then the uMCTL2 goes into power-down after a programmable number of cycles 'maximum idle clocks before power down' (PWRTMG.powerdown_to_x32). This register bit may be re-programmed during the course of normal operation. Programming.." "0,1" newline bitfld.long 0x14 0. "SELFREF_EN,If true then the uMCTL2 puts the SDRAM into self-refresh after a programmable number of cycles 'maximum idle clocks before self-refresh (PWRTMG.selfref_to_x32)'. This register bit may be re-programmed during the course of normal operation." "0,1" line.long 0x18 "PWRTMG,Low Power Timing Register" hexmask.long.byte 0x18 24.--31. 1. "RESERVED,Reserved" newline hexmask.long.byte 0x18 16.--23. 1. "SELFREF_TO_X32,After this many clocks of the DDRC command channel being idle the uMCTL2 automatically puts the SDRAM into self-refresh. The DDRC command channel is considered idle when there are no HIF commands outstanding. This must be enabled in the.." newline hexmask.long.byte 0x18 8.--15. 1. "T_DPD_X4096,Minimum deep power-down time. For mDDR value from the JEDEC specification is 0 as mDDR exits from deep power-down mode immediately after PWRCTL.deeppowerdown_en is de-asserted. For LPDDR2/LPDDR3 value from the JEDEC specification is 500us." newline rbitfld.long 0x18 5.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x18 0.--4. 1. "POWERDOWN_TO_X32,After this many clocks of the DDRC command channel being idle the uMCTL2 automatically puts the SDRAM into power-down. The DDRC command channel is considered idle when there are no HIF commands outstanding. This must be enabled in the.." line.long 0x1C "HWLPCTL,Hardware Low Power Control Register" hexmask.long.byte 0x1C 28.--31. 1. "RESERVED,Reserved" newline hexmask.long.word 0x1C 16.--27. 1. "HW_LP_IDLE_X32,Hardware idle period. The cactive_ddrc output is driven low if the DDRC command channel is idle for hw_lp_idle * 32 cycles if not in INIT or DPD/MPSM operating_mode. The DDRC command channel is considered idle when there are no HIF.." newline hexmask.long.word 0x1C 2.--15. 1. "RESERVED,Reserved" newline bitfld.long 0x1C 1. "HW_LP_EXIT_IDLE_EN,When this bit is programmed to 1 the cactive_in_ddrc pin of the DDRC can be used to exit from the automatic clock stop automatic power down or automatic self-refresh modes. Note it does not cause exit of self-refresh that was caused.." "0,1" newline bitfld.long 0x1C 0. "HW_LP_EN,Enable this bit for Hardware Low Power Interface. Programming Mode: Quasi-dynamic Group 2" "0,1" group.long 0x50++0x7 line.long 0x0 "RFSHCTL0,Refresh Control Register 0" hexmask.long.byte 0x0 24.--31. 1. "RESERVED,Reserved" newline hexmask.long.byte 0x0 20.--23. 1. "REFRESH_MARGIN,Threshold value in number of DFI clock cycles before the critical refresh or page timer expires. A critical refresh is to be issued before this threshold is reached. It is recommended that this not be changed from the default value.." newline rbitfld.long 0x0 17.--19. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x0 12.--16. 1. "REFRESH_TO_X1_X32,If the refresh timer (tRFCnom also known as tREFI) has expired at least once then a speculative refresh may be performed. A speculative refresh is a refresh performed at a time when refresh would be useful. When the SDRAM bus is idle.." newline rbitfld.long 0x0 10.--11. "RESERVED,Reserved" "0,1,2,3" newline hexmask.long.byte 0x0 4.--9. 1. "REFRESH_BURST,The programmed value + 1 is the number of refresh timeouts that is allowed to accumulate before traffic is blocked and the refreshes are forced to execute. Closing pages to perform a refresh is a one-time penalty that must be paid for each.." newline rbitfld.long 0x0 3. "RESERVED,Reserved" "0,1" newline bitfld.long 0x0 2. "PER_BANK_REFRESH,- 1 - Per bank refresh - 0 - All bank refresh Per bank refresh allows traffic to flow to other banks. Per bank refresh is not supported by all LPDDR2 devices but must be supported by all LPDDR3/LPDDR4 devices. Present only in designs.." "All bank refresh,Per bank refresh" newline rbitfld.long 0x0 0.--1. "RESERVED,Reserved" "0,1,2,3" line.long 0x4 "RFSHCTL1,Refresh Control Register 1" hexmask.long.byte 0x4 28.--31. 1. "RESERVED,Reserved" newline hexmask.long.word 0x4 16.--27. 1. "REFRESH_TIMER1_START_VALUE_X32,Refresh timer start for rank 1 (only present in multi-rank configurations). This is useful in staggering the refreshes to multiple ranks to help traffic to proceed. This is explained in Refresh Controls section of the.." newline hexmask.long.byte 0x4 12.--15. 1. "RESERVED,Reserved" newline hexmask.long.word 0x4 0.--11. 1. "REFRESH_TIMER0_START_VALUE_X32,Refresh timer start for rank 0 (only present in multi-rank configurations). This is useful in staggering the refreshes to multiple ranks to help traffic to proceed. This is explained in Refresh Controls section of the.." group.long 0x60++0xB line.long 0x0 "RFSHCTL3,Refresh Control Register 3" hexmask.long 0x0 7.--31. 1. "RESERVED,Reserved" newline bitfld.long 0x0 4.--6. "REFRESH_MODE,Indicates fine granularity refresh mode. - 000 - Fixed 1x (Normal mode) - 001 - Fixed 2x - 010 - Fixed 4x - 101 - Enable on the fly 2x (not supported) - 110 - Enable on the fly 4x (not supported) - Everything else - reserved Note: - Only.." "Fixed 1x,The on-the-fly modes are not supported in this..,This register field has effect only if a DDR4..,?,?,?,?,?" newline rbitfld.long 0x0 2.--3. "RESERVED,Reserved" "0,1,2,3" newline bitfld.long 0x0 1. "REFRESH_UPDATE_LEVEL,Toggle this signal (either from 0 to 1 or from 1 to 0) to indicate that the refresh registers have been updated. refresh_update_level must not be toggled when the DDRC is in reset (core_ddrc_rstn = 0). The refresh registers are.." "0,1" newline bitfld.long 0x0 0. "DIS_AUTO_REFRESH,When '1' disable auto-refresh generated by the uMCTL2. When auto-refresh is disabled the SoC must generate refreshes using the registers DBGCMD.rankn_refresh. When dis_auto_refresh transitions from 0 to 1 any pending refreshes are.." "0,1" line.long 0x4 "RFSHTMG,Refresh Timing Register" bitfld.long 0x4 31. "T_RFC_NOM_X1_SEL,Specifies whether the RFSHTMG.t_rfc_nom_x1_x32 and RFSHCTL0.refresh_to_x1_x32 register values are x1 or x32. - 0 - x32 register values are used - 1 - x1 register values are used This applies only when per-bank refresh is enabled.." "x32 register values are used,x1 register values are used" newline rbitfld.long 0x4 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline hexmask.long.word 0x4 16.--27. 1. "T_RFC_NOM_X1_X32,Average time interval between refreshes per rank (Specification: 7.8us for DDR2 DDR3 and DDR4. See JEDEC specification for mDDR LPDDR2 LPDDR3 and LPDDR4). When the controller is operating in 1:1 mode set this register to.." newline bitfld.long 0x4 15. "LPDDR3_TREFBW_EN,Used only when LPDDR3 memory type is connected. Should only be changed when uMCTL2 is in reset. Specifies whether to use the tREFBW parameter (required by some LPDDR3 devices which comply with earlier versions of the LPDDR3 JEDEC.." "tREFBW parameter not used,tREFBW parameter used" newline hexmask.long.byte 0x4 10.--14. 1. "RESERVED,Reserved" newline hexmask.long.word 0x4 0.--9. 1. "T_RFC_MIN,tRFC (min): Minimum time from refresh to refresh or activate. When the controller is operating in 1:1 mode t_rfc_min must be set to RoundUp(tRFCmin/tCK). When the controller is operating in 1:2 mode t_rfc_min must be set to.." line.long 0x8 "RFSHTMG1,Refresh Timing Register1" hexmask.long.byte 0x8 24.--31. 1. "RESERVED,Reserved" newline hexmask.long.byte 0x8 16.--23. 1. "T_PBR2PBR,LPDDR4:tpbR2pbR. Per-bank refresh to Per-bank refresh different bank Time. When the controller is operating in 1:1 frequency ratio mode program this to RoundUp(tpbR2pbR/tCK). When the controller is operating in 1:2 frequency ratio mode.." newline hexmask.long.word 0x8 0.--15. 1. "RESERVED,Reserved" group.long 0x70++0x7 line.long 0x0 "ECCCFG0,ECC Configuration Register 0" bitfld.long 0x0 30.--31. "ECC_REGION_MAP_GRANU,Indicates granularity of selectable protected region. Define one region size for ECCCFG0.ecc_region_map. - 0 - 1/8 of memory spaces - 1 - 1/16 of memory spaces - 2 - 1/32 of memory spaces - 3 - 1/64 of memory spaces Programming Mode:.." "0,1,2,3" newline bitfld.long 0x0 29. "ECC_REGION_MAP_OTHER,When ECCCFG0.ecc_region_map_granu>0 there is a region which is not controlled by ecc_region_map. This register defines the region to be protected or non-protected for Inline ECC. - 0 - Non-Protected - 1 - Protected This register is.." "Non-Protected,Protected" newline rbitfld.long 0x0 27.--28. "RESERVED,Reserved" "0,1,2,3" newline bitfld.long 0x0 24.--26. "ECC_AP_ERR_THRESHOLD,Sets threshold for address parity error. ECCAPSTAT.ecc_ap_err is asserted if number of ECC errors (correctable/uncorrectable) within one burst exceeds this threshold. This register value must be less than 'Total number of ECC checks.." "0,1,2,3,4,5,6,7" newline rbitfld.long 0x0 22.--23. "RESERVED,Reserved" "0,1,2,3" newline hexmask.long.byte 0x0 16.--21. 1. "BLK_CHANNEL_IDLE_TIME_X32,Indicates the number of cycles on HIF interface with no access to protected regions which causes flush of all the block channels. In order to flush block channel uMCTL2 injects write ECC command (when there is no incoming HIF.." newline rbitfld.long 0x0 15. "RESERVED,Reserved" "0,1" newline hexmask.long.byte 0x0 8.--14. 1. "ECC_REGION_MAP,Selectable Protected Region setting. Memory space is divided to 8/16/32/64 regions which is determined by ECCCFG0.ecc_region_map_granu. Note: Highest 1/8 memory space is always ECC region. Lowest 7 regions are Selectable Protected Regions." newline bitfld.long 0x0 7. "ECC_REGION_REMAP_EN,Enables remapping ECC region feature. Only supported when inline ECC is enabled. - 0 - Disable - 1 - Enable Programming Mode: Static" "Disable,Enable" newline bitfld.long 0x0 6. "ECC_AP_EN,Enables address protection feature. Only supported when inline ECC is enabled. - 0 - Disable - 1 - Enable Programming Mode: Static" "Disable,Enable" newline rbitfld.long 0x0 5. "RESERVED,Reserved" "0,1" newline bitfld.long 0x0 4. "DIS_SCRUB,Disables ECC scrubs. Valid only when ECCCFG0.ecc_mode = 3'b100 or 3'b101 and MEMC_USE_RMW is defined. Note: Scrub is not supported in inline ECC mode and the register value is don't care. Programming Mode: Static" "0,1" newline rbitfld.long 0x0 3. "RESERVED,Reserved" "0,1" newline bitfld.long 0x0 0.--2. "ECC_MODE,ECC mode indicator. - 000 - ECC disabled - 100 - ECC enabled - SEC/DED over 1 beat - 101 - ECC enabled - Advanced ECC (Illegal value when MEMC_INLINE_ECC=1) - all other settings are reserved for future use Programming Mode: Static" "ECC disabled,?,?,?,?,?,?,?" line.long 0x4 "ECCCFG1,ECC Configuration Register 1" hexmask.long.tbyte 0x4 12.--31. 1. "RESERVED,Reserved" newline hexmask.long.byte 0x4 8.--11. 1. "ACTIVE_BLK_CHANNEL,Indicated the number of active block channels. Total number of ECC block channels are defined by MEMC_NO_OF_BLK_CHANNEL hardware parameter. This register can limit the number of available channels. For example if set to 0 only one.." newline bitfld.long 0x4 7. "BLK_CHANNEL_ACTIVE_TERM,If enabled block channel is terminated when full block write or full block read is performed (all address within block are written or read). - 0 - Disable (only for debug purpose) - 1 - Enable (default) This is debug register.." "Disable,Enable" newline rbitfld.long 0x4 6. "RESERVED,Reserved" "0,1" newline bitfld.long 0x4 5. "ECC_REGION_WASTE_LOCK,Locks the remaining waste parts of the ECC region (hole) that are not locked by ecc_region_parity_lock. - 1 - Locked; if this region is accessed error response is generated - 0 - Unlocked; this region can be accessed normally.." "Unlocked; this region can be accessed normally,Locked; if this region is accessed" newline bitfld.long 0x4 4. "ECC_REGION_PARITY_LOCK,Locks the parity section of the ECC region (hole) which is the highest system address part of the memory that stores ECC parity for protected region. - 1 - Locked; if this region is accessed error response is generated - 0 -.." "Unlocked; this region can be accessed normally,Locked; if this region is accessed" newline rbitfld.long 0x4 2.--3. "RESERVED,Reserved" "0,1,2,3" newline bitfld.long 0x4 1. "DATA_POISON_BIT,Selects whether to poison 1 or 2 bits. - if 0 -> 2-bit (uncorrectable) data poisoning - if 1 -> 1-bit (correctable) data poisoning if ECCCFG1.data_poison_en=1 Valid only when MEMC_ECC_SUPPORT==1 (SECDED ECC mode) Programming Mode:.." "?,bit" newline bitfld.long 0x4 0. "DATA_POISON_EN,Enables ECC data poisoning - introduces ECC errors on writes to address specified by the ECCPOISONADDR0/1 registers. This field must be set to 0 if ECC is disabled (ECCCFG0.ecc_mode = 0). Programming Mode: Quasi-dynamic Group 3" "0,1" rgroup.long 0x78++0x3 line.long 0x0 "ECCSTAT,SECDED ECC Status Register (Valid only in MEMC_ECC_SUPPORT==1 (SECDED ECC mode))" hexmask.long.word 0x0 17.--31. 1. "RESERVED,Reserved" newline bitfld.long 0x0 16. "ECC_UNCORRECTED_ERR,Double-bit error indicator. In sideband ECC mode 1 bit per ECC lane. When the controller is operating in 1:1 frequency ratio mode there are only two lanes so only the lower two bits are used. In inline ECC mode the register is.." "0,1" newline hexmask.long.byte 0x0 9.--15. 1. "RESERVED,Reserved" newline bitfld.long 0x0 8. "ECC_CORRECTED_ERR,Single-bit error indicator. In sideband ECC mode 1 bit per ECC lane. When the controller is operating in 1:1 frequency ratio mode there are only two lanes so only the lower two bits are used. In inline ECC mode the register is.." "0,1" newline bitfld.long 0x0 7. "RESERVED,Reserved" "0,1" newline hexmask.long.byte 0x0 0.--6. 1. "ECC_CORRECTED_BIT_NUM,Indicates the bit number corrected by single-bit ECC error. For encoding of this field see ECC section in the Architecture chapter. If more than one data lane has an error the lower data lane is selected. This register is 7 bits.." group.long 0x7C++0x3 line.long 0x0 "ECCCTL,ECC Clear Register" hexmask.long.word 0x0 19.--31. 1. "RESERVED,Reserved" newline bitfld.long 0x0 18. "ECC_AP_ERR_INTR_FORCE,Interrupt force bit for ecc_ap_err_intr. Setting this register causes the output interrupt to be asserted. The uMCTL2 automatically clears this bit. There is no interaction between functionally triggering an interrupt and forcing an.." "0,1" newline bitfld.long 0x0 17. "ECC_UNCORRECTED_ERR_INTR_FORCE,Interrupt force bit for ecc_uncorrected_err_intr. Setting this register causes the output interrupt to be asserted. The uMCTL2 automatically clears this bit. There is no interaction between functionally triggering an.." "0,1" newline bitfld.long 0x0 16. "ECC_CORRECTED_ERR_INTR_FORCE,Interrupt force bit for ecc_corrected_err_intr. Setting this register causes the output interrupt to be asserted. The uMCTL2 automatically clears this bit. There is no interaction between functionally triggering an interrupt.." "0,1" newline hexmask.long.byte 0x0 11.--15. 1. "RESERVED,Reserved" newline bitfld.long 0x0 10. "ECC_AP_ERR_INTR_EN,Interrupt enable bit for ecc_ap_err_intr. - 1 - Enabled - 0 - Disabled Programming Mode: Dynamic" "Disabled,Enabled" newline bitfld.long 0x0 9. "ECC_UNCORRECTED_ERR_INTR_EN,Interrupt enable bit for ecc_uncorrected_err_intr. - 1 - Enabled - 0 - Disabled Programming Mode: Dynamic" "Disabled,Enabled" newline bitfld.long 0x0 8. "ECC_CORRECTED_ERR_INTR_EN,Interrupt enable bit for ecc_corrected_err_intr. - 1 - Enabled - 0 - Disabled Programming Mode: Dynamic" "Disabled,Enabled" newline rbitfld.long 0x0 5.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 4. "ECC_AP_ERR_INTR_CLR,Interrupt clear bit for ecc_ap_err. If this bit is set the ECCAPSTAT.ecc_ap_err/ecc_ap_err_intr is cleared. The uMCTL2 automatically clears this bit. Programming Mode: Dynamic" "0,1" newline bitfld.long 0x0 3. "ECC_UNCORR_ERR_CNT_CLR,Setting this register bit to 1 clears the currently stored uncorrected ECC error count. The ECCERRCNT.ecc_uncorr_err_cnt register is cleared by this operation. The uMCTL2 automatically clears this bit. Programming Mode: Dynamic" "0,1" newline bitfld.long 0x0 2. "ECC_CORR_ERR_CNT_CLR,Setting this register bit to 1 clears the currently stored corrected ECC error count. The ECCERRCNT.ecc_corr_err_cnt register is cleared by this operation. The uMCTL2 automatically clears this bit. Programming Mode: Dynamic" "0,1" newline bitfld.long 0x0 1. "ECC_UNCORRECTED_ERR_CLR,Setting this register bit to 1 clears the currently stored uncorrected ECC error. The following registers are cleared: - ECCSTAT.ecc_uncorrected_err - ADVECCSTAT.advecc_uncorrected_err - ECCUSYN0 - ECCUSYN1 - ECCUSYN2 uMCTL2.." "ECCUSYN1,?" newline bitfld.long 0x0 0. "ECC_CORRECTED_ERR_CLR,Setting this register bit to 1 clears the currently stored corrected ECC error. The following registers are cleared: - ECCSTAT.ecc_corrected_err - ADVECCSTAT.advecc_corrected_err - ADVECCSTAT.advecc_num_err_symbol -.." "ECCCSYN1,ECCBITMASK2" rgroup.long 0x80++0xB line.long 0x0 "ECCERRCNT,ECC Error Counter Register" hexmask.long.word 0x0 16.--31. 1. "ECC_UNCORR_ERR_CNT,Indicates the number of uncorrectable ECC errors detected. Note that the saturation behavior of this register is different depending on the type of ECC. For advanced ECC or Inline ECC it saturates at 0xFFFF while for Side-band ECC.." newline hexmask.long.word 0x0 0.--15. 1. "ECC_CORR_ERR_CNT,Indicates the number of correctable ECC errors detected. Note that the saturation behavior of this register is different depending on the type of ECC. For advanced ECC or Inline ECC it saturates at 0xFFFF while for Side-band ECC with.." line.long 0x4 "ECCCADDR0,ECC Corrected Error Address Register 0" hexmask.long.byte 0x4 25.--31. 1. "RESERVED,Reserved" newline bitfld.long 0x4 24. "ECC_CORR_RANK,Indicates the rank number of a read resulting in a corrected ECC error. Programming Mode: Dynamic" "0,1" newline hexmask.long.byte 0x4 18.--23. 1. "RESERVED,Reserved" newline hexmask.long.tbyte 0x4 0.--17. 1. "ECC_CORR_ROW,Indicates the page/row number of a read resulting in a corrected ECC error. This is 18-bits wide in configurations with DDR4 support and 16-bits in all other configurations. Programming Mode: Dynamic" line.long 0x8 "ECCCADDR1,ECC Corrected Error Address Register 1" hexmask.long.byte 0x8 26.--31. 1. "RESERVED,Reserved" newline bitfld.long 0x8 24.--25. "ECC_CORR_BG,Indicates the bank group number of a read resulting in a corrected ECC error. Programming Mode: Dynamic" "0,1,2,3" newline hexmask.long.byte 0x8 19.--23. 1. "RESERVED,Reserved" newline bitfld.long 0x8 16.--18. "ECC_CORR_BANK,Indicates the bank number of a read resulting in a corrected ECC error. Programming Mode: Dynamic" "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x8 12.--15. 1. "RESERVED,Reserved" newline hexmask.long.word 0x8 0.--11. 1. "ECC_CORR_COL,Indicates the block number of a read resulting in a corrected ECC error (lowest bit not assigned here). Programming Mode: Dynamic" repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) rgroup.long ($2+0x8C)++0x3 line.long 0x0 "ECCCSYN$1,ECC Corrected Syndrome Register 0" hexmask.long 0x0 0.--31. 1. "ECC_CORR_SYNDROMES_31_0,Indicates the data pattern that resulted in a corrected error. For 16-bit ECC only bits [15:0] are used. Programming Mode: Dynamic" repeat.end rgroup.long 0x94++0x3 line.long 0x0 "ECCCSYN2,ECC Corrected Syndrome Register 2" hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED,Reserved" newline hexmask.long.byte 0x0 0.--7. 1. "ECC_CORR_SYNDROMES_71_64,Indicates the data pattern that resulted in a corrected error one for each ECC lane all concatenated together. This register refers to the ECC byte which is bits [71:64] for 64-bit ECC [39:32] for 32-bit ECC or [23:16] for.." repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) rgroup.long ($2+0x98)++0x3 line.long 0x0 "ECCBITMASK$1,ECC Corrected Data Bit Mask Register 0" hexmask.long 0x0 0.--31. 1. "ECC_CORR_BIT_MASK_31_0,Indicates the mask for the corrected data portion. - 1 on any bit indicates that the bit has been corrected by the ECC logic - 0 on any bit indicates that the bit has not been corrected by the ECC logic This register accumulates.." repeat.end rgroup.long 0xA0++0xB line.long 0x0 "ECCBITMASK2,ECC Corrected Data Bit Mask Register 2" hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED,Reserved" newline hexmask.long.byte 0x0 0.--7. 1. "ECC_CORR_BIT_MASK_71_64,Indicates the mask for the corrected data portion. - 1 on any bit indicates that the bit has been corrected by the ECC logic - 0 on any bit indicates that the bit has not been corrected by the ECC logic This register accumulates.." line.long 0x4 "ECCUADDR0,ECC Uncorrected Error Address Register 0" hexmask.long.byte 0x4 25.--31. 1. "RESERVED,Reserved" newline bitfld.long 0x4 24. "ECC_UNCORR_RANK,Indicates the rank number of a read resulting in an uncorrected ECC error. Programming Mode: Dynamic" "0,1" newline hexmask.long.byte 0x4 18.--23. 1. "RESERVED,Reserved" newline hexmask.long.tbyte 0x4 0.--17. 1. "ECC_UNCORR_ROW,Indicates the page/row number of a read resulting in an uncorrected ECC error. This is 18-bits wide in configurations with DDR4 support and 16-bits in all other configurations. Programming Mode: Dynamic" line.long 0x8 "ECCUADDR1,ECC Uncorrected Error Address Register 1" hexmask.long.byte 0x8 26.--31. 1. "RESERVED,Reserved" newline bitfld.long 0x8 24.--25. "ECC_UNCORR_BG,Indicates the bank group number of a read resulting in an uncorrected ECC error. Programming Mode: Dynamic" "0,1,2,3" newline hexmask.long.byte 0x8 19.--23. 1. "RESERVED,Reserved" newline bitfld.long 0x8 16.--18. "ECC_UNCORR_BANK,Indicates the bank number of a read resulting in an uncorrected ECC error. Programming Mode: Dynamic" "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x8 12.--15. 1. "RESERVED,Reserved" newline hexmask.long.word 0x8 0.--11. 1. "ECC_UNCORR_COL,Indicates the block number of a read resulting in an uncorrected ECC error (lowest bit not assigned here). Programming Mode: Dynamic" repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) rgroup.long ($2+0xAC)++0x3 line.long 0x0 "ECCUSYN$1,ECC Uncorrected Syndrome Register 0" hexmask.long 0x0 0.--31. 1. "ECC_UNCORR_SYNDROMES_31_0,Indicates the data pattern that resulted in an uncorrected error one for each ECC lane all concatenated together. For 16-bit ECC only bits [15:0] are used. Programming Mode: Dynamic" repeat.end rgroup.long 0xB4++0x3 line.long 0x0 "ECCUSYN2,ECC Uncorrected Syndrome Register 2" hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED,Reserved" newline hexmask.long.byte 0x0 0.--7. 1. "ECC_UNCORR_SYNDROMES_71_64,Indicates the data pattern that resulted in an uncorrected error one for each ECC lane all concatenated together. This register refers to the ECC byte which is bits [71:64] for 64-bit ECC [39:32] for 32-bit ECC or [23:16].." group.long 0xB8++0xF line.long 0x0 "ECCPOISONADDR0,ECC Data Poisoning Address Register 0. If a HIF write data beat matches the address specified in this register. an ECC error is introduced on that transaction (write/RMW). if ECCCFG1.data_poison_en=1." hexmask.long.byte 0x0 25.--31. 1. "RESERVED,Reserved" newline bitfld.long 0x0 24. "ECC_POISON_RANK,Indicates the rank address for ECC poisoning. Programming Mode: Static" "0,1" newline hexmask.long.word 0x0 12.--23. 1. "RESERVED,Reserved" newline hexmask.long.word 0x0 0.--11. 1. "ECC_POISON_COL,Indicates the column address for ECC poisoning. Note that this column address must be burst aligned: - In full bus width mode ecc_poison_col[2:0] must be set to 0 - In half bus width mode ecc_poison_col[3:0] must be set to 0 - In quarter.." line.long 0x4 "ECCPOISONADDR1,ECC Data Poisoning Address Register 1. If a HIF write data beat matches the address specified in this register. an ECC error is introduced on that transaction (write/RMW). if ECCCFG1.data_poison_en=1." rbitfld.long 0x4 30.--31. "RESERVED,Reserved" "0,1,2,3" newline bitfld.long 0x4 28.--29. "ECC_POISON_BG,Bank Group address for ECC poisoning. Programming Mode: Static" "0,1,2,3" newline rbitfld.long 0x4 27. "RESERVED,Reserved" "0,1" newline bitfld.long 0x4 24.--26. "ECC_POISON_BANK,Bank address for ECC poisoning. Programming Mode: Static" "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x4 18.--23. 1. "RESERVED,Reserved" newline hexmask.long.tbyte 0x4 0.--17. 1. "ECC_POISON_ROW,Row address for ECC poisoning. This is 18-bits wide in configurations with DDR4 support and 16-bits in all other configurations. Programming Mode: Static" line.long 0x8 "CRCPARCTL0,CRC Parity Control Register0. Note: Do not perform any APB access to CRCPARCTL0 within 32 pclk cycles of previous access to CRCPARCTL0. as this might lead to data loss." hexmask.long 0x8 3.--31. 1. "RESERVED,Reserved" newline bitfld.long 0x8 2. "DFI_ALERT_ERR_CNT_CLR,Indicates the clear bit for DFI alert error counter. Asserting this bit clears the DFI alert error counter CRCPARSTAT.dfi_alert_err_cnt. uMCTL2 automatically clears this bit. Programming Mode: Dynamic" "0,1" newline bitfld.long 0x8 1. "DFI_ALERT_ERR_INT_CLR,Interrupt clear bit for DFI alert error. If this bit is set the alert error interrupt on CRCPARSTAT.dfi_alert_err_int is cleared. uMCTL2 automatically clears this bit. Programming Mode: Dynamic" "0,1" newline bitfld.long 0x8 0. "DFI_ALERT_ERR_INT_EN,Interrupt enable bit for DFI alert error. If this bit is set any parity/CRC error detected on the dfi_alert_n input results in an interrupt being set on CRCPARSTAT.dfi_alert_err_int. Programming Mode: Dynamic" "0,1" line.long 0xC "CRCPARCTL1,CRC Parity Control Register1" hexmask.long.tbyte 0xC 13.--31. 1. "RESERVED,Reserved" newline bitfld.long 0xC 12. "CAPARITY_DISABLE_BEFORE_SR,If DDR4-SDRAM's CA parity is enabled by INIT6.mr5[2:0]!=0 and this register is set to 1 CA parity is automatically disabled before self-refresh entry and enabled after self-refresh exit by issuing MR5. - 1 - CA parity is.." "CA parity is not disabled before self-refresh..,CA parity is disabled before self-refresh entry" newline hexmask.long.byte 0xC 8.--11. 1. "RESERVED,Reserved" newline bitfld.long 0xC 7. "CRC_INC_DM,CRC calculation setting register. - 1 - CRC includes DM signal - 0 - CRC not includes DM signal Present only in designs configured to support DDR4. Programming Mode: Static" "CRC not includes DM signal,CRC includes DM signal" newline rbitfld.long 0xC 5.--6. "RESERVED,Reserved" "0,1,2,3" newline bitfld.long 0xC 4. "CRC_ENABLE,CRC enable Register. - 1 - Enable generation of CRC - 0 - Disable generation of CRC The setting of this register should match the CRC mode register setting in the DRAM. Programming Mode: Quasi-dynamic Group 2" "Disable generation of CRC,Enable generation of CRC" newline rbitfld.long 0xC 1.--3. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline bitfld.long 0xC 0. "PARITY_ENABLE,C/A Parity enable register. - 1 - Enable generation of C/A parity and detection of C/A parity error - 0 - Disable generation of C/A parity and disable detection of C/A parity error If RCD's parity error detection or SDRAM's parity detection.." "Disable generation of C/A parity and disable..,Enable generation of C/A parity and detection of.." rgroup.long 0xCC++0x3 line.long 0x0 "CRCPARSTAT,CRC Parity Status Register" hexmask.long.word 0x0 17.--31. 1. "RESERVED,Reserved" newline bitfld.long 0x0 16. "DFI_ALERT_ERR_INT,DFI alert error interrupt. If a parity/CRC error is detected on dfi_alert_n and the interrupt is enabled by CRCPARCTL0.dfi_alert_err_int_en this interrupt bit is set. It remains set until cleared by CRCPARCTL0.dfi_alert_err_int_clr." "0,1" newline hexmask.long.word 0x0 0.--15. 1. "DFI_ALERT_ERR_CNT,DFI alert error count. If a parity/CRC error is detected on dfi_alert_n this counter be incremented. This is independent of the setting of CRCPARCTL0.dfi_alert_err_int_en. It saturates at 0xFFFF and can be cleared by asserting.." group.long 0xD0++0xB line.long 0x0 "INIT0,SDRAM Initialization Register 0" bitfld.long 0x0 30.--31. "SKIP_DRAM_INIT,If lower bit is enabled the SDRAM initialization routine is skipped. The upper bit decides what state the controller starts up in when reset is removed. - 00 - SDRAM Initialization routine is run after power-up - 01 - SDRAM Initialization.." "SDRAM Initialization routine is run after power-up,SDRAM Initialization routine is skipped after..,?,?" newline hexmask.long.byte 0x0 26.--29. 1. "RESERVED,Reserved" newline hexmask.long.word 0x0 16.--25. 1. "POST_CKE_X1024,Indicates the number of cycles to wait after driving CKE high to start the SDRAM initialization sequence. DDR2 typically requires a 400 ns delay requiring this value to be programmed to 2 at all clock speeds. LPDDR2/LPDDR3 typically.." newline hexmask.long.byte 0x0 12.--15. 1. "RESERVED,Reserved" newline hexmask.long.word 0x0 0.--11. 1. "PRE_CKE_X1024,Indicates the number of cycles to wait after reset before driving CKE high to start the SDRAM initialization sequence. DDR2 specifications typically require this to be programmed for a delay of >= 200 us. LPDDR2/LPDDR3: tINIT1 of 100 ns.." line.long 0x4 "INIT1,SDRAM Initialization Register 1" hexmask.long.byte 0x4 25.--31. 1. "RESERVED,Reserved" newline hexmask.long.word 0x4 16.--24. 1. "DRAM_RSTN_X1024,Indicates the number of cycles to assert SDRAM reset signal during init sequence. This is only present for designs supporting DDR3 DDR4 or LPDDR4 devices. For use with a Synopsys DDR PHY this must be set to a minimum of 1. When the.." newline hexmask.long.word 0x4 4.--15. 1. "RESERVED,Reserved" newline hexmask.long.byte 0x4 0.--3. 1. "PRE_OCD_X32,Indicates the wait period before driving the OCD complete command to SDRAM. There is no known specific requirement for this; it may be set to zero. Unit: Multiples of 32 DFI clock cycles. For more information on how to program this register.." line.long 0x8 "INIT2,SDRAM Initialization Register 2" hexmask.long.word 0x8 16.--31. 1. "RESERVED,Reserved" newline hexmask.long.byte 0x8 8.--15. 1. "IDLE_AFTER_RESET_X32,Indicates the idle time after the reset command tINIT4. Present only in designs configured to support LPDDR2. When the controller is operating in 1:2 frequency ratio mode program this to JEDEC spec value divided by 2 and round it.." newline hexmask.long.byte 0x8 4.--7. 1. "RESERVED,Reserved" newline hexmask.long.byte 0x8 0.--3. 1. "MIN_STABLE_CLOCK_X1,Indicates the time to wait after the first CKE high tINIT2. Present only in designs configured to support LPDDR2/LPDDR3. LPDDR2/LPDDR3 typically requires 5 x tCK delay. When the controller is operating in 1:2 frequency ratio mode.." repeat 4. (list 0x3 0x4 0x6 0x7 )(list 0x0 0x4 0xC 0x10 ) group.long ($2+0xDC)++0x3 line.long 0x0 "INIT$1,SDRAM Initialization Register 3" hexmask.long.word 0x0 16.--31. 1. "MR,DDR2:Indicates the value to write to MR register. Bit 8 is for DLL and the setting here is ignored. The uMCTL2 sets this bit appropriately. DDR3/DDR4: Value loaded into MR0 register. mDDR: Value to write to MR register. LPDDR2/LPDDR3/LPDDR4 - Value to.." newline hexmask.long.word 0x0 0.--15. 1. "EMR,DDR2: Indicates the value to write to EMR register. Bits 9:7 are for OCD and the setting in this register is ignored. The uMCTL2 sets those bits appropriately. DDR3/DDR4: Value to write to MR1 register Set bit 7 to 0. mDDR: Value to write to EMR.." repeat.end group.long 0xE4++0x3 line.long 0x0 "INIT5,SDRAM Initialization Register 5" hexmask.long.byte 0x0 24.--31. 1. "RESERVED,Reserved" newline hexmask.long.byte 0x0 16.--23. 1. "DEV_ZQINIT_X32,ZQ initial calibration tZQINIT. Present only in designs configured to support DDR3 or DDR4 or LPDDR2/LPDDR3. DDR3 typically requires 512 SDRAM clock cycles. DDR4 requires 1024 SDRAM clock cycles. LPDDR2/LPDDR3 requires 1 us. When the.." newline hexmask.long.byte 0x0 10.--15. 1. "RESERVED,Reserved" newline hexmask.long.word 0x0 0.--9. 1. "MAX_AUTO_INIT_X1024,Indicates the maximum duration of the auto initialization tINIT5. Present only in designs configured to support LPDDR2/LPDDR3. LPDDR2/LPDDR3 typically requires 10 us. Unit: Multiples of 1024 DFI clock cycles. For more information on.." group.long 0xF0++0x7 line.long 0x0 "DIMMCTL,DIMM Control Register" hexmask.long.tbyte 0x0 15.--31. 1. "RESERVED,Reserved" newline bitfld.long 0x0 14. "RCD_B_OUTPUT_DISABLED,Disables RCD outputs to B-side DRAMs. This field is used only when the uMCTL2 disables CAL mode. This value is written to F0RC0 DA[3] before and after disabling CAL mode. It is recommended to set it to ~DIMMCTL.dimm_output_inv_en.." "Enable B outputs,Disable B outputs" newline bitfld.long 0x0 13. "RCD_A_OUTPUT_DISABLED,Disables RCD outputs to A-side DRAMs. This field is used only when the uMCTL2 disables CAL mode. This value is written to F0RC0 DA[2] before and after disabling CAL mode. It is recommended to set it to 0 except for debug. - 1 -.." "Enable A outputs,Disable A outputs" newline bitfld.long 0x0 12. "RCD_WEAK_DRIVE,Indicates the weak drive mode to be set to the RCD. This field is used only when the uMCTL2 disables CAL mode. When weak drive mode in the RCD is enabled during initialization this field must be set to 1. When RCD is not used this field.." "Disable Weak Drive mode,Enable Weak Drive mode" newline hexmask.long.byte 0x0 7.--11. 1. "RESERVED,Reserved" newline bitfld.long 0x0 6. "LRDIMM_BCOM_CMD_PROT,Protects the timing restrictions (tBCW/tMRC) between consecutive BCOM commands defined in the Data Buffer specification. When using DDR4 LRDIMM this bit must be set to 1. Otherwise this bit must be set to 0. Programming Mode: Static" "0,1" newline bitfld.long 0x0 5. "DIMM_DIS_BG_MIRRORING,Disables address mirroring for BG bits. When this is set to 1 BG0 and BG1 are NOT swapped even if Address Mirroring is enabled. This is required for DDR4 DIMMs with x16 devices. - 1 - BG0 and BG1 are NOT swapped - 0 - BG0 and BG1.." "BG0 and BG1 are swapped if address mirroring is..,BG0 and BG1 are NOT swapped" newline bitfld.long 0x0 4. "MRS_BG1_EN,Enable this field for BG1 bit of MRS command. BG1 bit of the mode register address is specified as RFU (Reserved for Future Use) and must be programmed to 0 during MRS. In case where DRAMs that do not have BG1 are attached and both the CA.." "Disabled,Enabled" newline bitfld.long 0x0 3. "MRS_A17_EN,Enable this field for A17 bit of MRS command. A17 bit of the mode register address is specified as RFU (Reserved for Future Use) and must be programmed to 0 during MRS. In case where DRAMs that do not have A17 are attached as DDR4 RDIMM/LRDIMM.." "Disabled,Enabled" newline bitfld.long 0x0 2. "DIMM_OUTPUT_INV_EN,Enables output inversion (for DDR4 RDIMM/LRDIMM implementations only). DDR4 RDIMM/LRDIMM implements the Output Inversion feature by default which means that the following address bank address and bank group bits of B-side DRAMs are.." "Do not implement output inversion for B-side DRAMs,Implement output inversion for B-side DRAMs" newline bitfld.long 0x0 1. "DIMM_ADDR_MIRR_EN,Enables address mirroring (for multi-rank UDIMM implementations and multi-rank DDR4 RDIMM/LRDIMM implementations). Some UDIMMs and DDR4 RDIMMs/LRDIMMs implement address mirroring for odd ranks which means that the following address.." "Do not implement address mirroring,For odd ranks" newline bitfld.long 0x0 0. "DIMM_STAGGER_CS_EN,Staggering enable for multi-rank accesses (for multi-rank UDIMM RDIMM and LRDIMM implementations only). This is not supported for mDDR LPDDR2 LPDDR3 or LPDDR4 SDRAMs. Note: Even if this bit is set it does not take care of software.." "Do not stagger accesses,?" line.long 0x4 "RANKCTL,Rank Control Register" hexmask.long.byte 0x4 27.--31. 1. "RESERVED,Reserved" newline bitfld.long 0x4 26. "DIFF_RANK_WR_GAP_MSB,Only present for multi-rank configurations. 1-bit extension to be used when RANKCTL.diff_rank_wr_gap field needs to be set to a value greater than 0xF. Programming Mode: Quasi-dynamic Group 2" "?,bit extension to be used when RANKCTL" newline rbitfld.long 0x4 25. "RESERVED,Reserved" "0,1" newline bitfld.long 0x4 24. "DIFF_RANK_RD_GAP_MSB,Only present for multi-rank configurations. 1-bit extension to be used when RANKCTL.diff_rank_rd_gap field needs to be set to a value greater than 0xF. Programming Mode: Quasi-dynamic Group 2" "?,bit extension to be used when RANKCTL" newline hexmask.long.byte 0x4 16.--23. 1. "RESERVED,Reserved" newline hexmask.long.byte 0x4 12.--15. 1. "MAX_RANK_WR,Only present for multi-rank configurations. Background: Writes to the same rank can be performed back-to-back. Writes to different ranks require additional gap dictated by the register RANKCTL.diff_rank_wr_gap. This is to avoid possible data.." newline hexmask.long.byte 0x4 8.--11. 1. "DIFF_RANK_WR_GAP,Only present for multi-rank configurations. Indicates the number of clocks of gap in data responses when performing consecutive writes to different ranks. This is used to switch the delays in the PHY to match the rank requirements. This.." newline hexmask.long.byte 0x4 4.--7. 1. "DIFF_RANK_RD_GAP,Only present for multi-rank configurations. Indicates the number of clocks of gap in data responses when performing consecutive reads to different ranks. This is used to switch the delays in the PHY to match the rank requirements. This.." newline hexmask.long.byte 0x4 0.--3. 1. "MAX_RANK_RD,Only present for multi-rank configurations. Background: Reads to the same rank can be performed back-to-back. Reads to different ranks require additional gap dictated by the register RANKCTL.diff_rank_rd_gap. This is to avoid possible data.." group.long 0x100++0x3F line.long 0x0 "DRAMTMG0,SDRAM Timing Register 0" rbitfld.long 0x0 31. "RESERVED,Reserved" "0,1" newline hexmask.long.byte 0x0 24.--30. 1. "WR2PRE,Specifies the minimum time between write and precharge to same bank. Specifications: WL + BL/2 + tWR = approximately 8 cycles + 15 ns = 14 clocks @400MHz and less for lower frequencies. where: - WL - Write latency - BL - Burst length. This must.." newline rbitfld.long 0x0 22.--23. "RESERVED,Reserved" "0,1,2,3" newline hexmask.long.byte 0x0 16.--21. 1. "T_FAW,tFAW - valid only when 8 or more banks(or banks x bank groups) are present. In 8-bank design at most 4 banks must be activated in a rolling window of tFAW cycles. When the controller is operating in 1:2 frequency ratio mode program this to.." newline rbitfld.long 0x0 15. "RESERVED,Reserved" "0,1" newline hexmask.long.byte 0x0 8.--14. 1. "T_RAS_MAX,tRAS(max) - Specifies the maximum time between activate and precharge to same bank. This is the maximum time that a page can be kept open Minimum value of this register is 1. Zero is invalid. When the controller is operating in 1:1 frequency.." newline rbitfld.long 0x0 6.--7. "RESERVED,Reserved" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "T_RAS_MIN,tRAS(min) - Specifies the minimum time between activate and precharge to the same bank. When the controller is operating in 1:2 frequency mode 1T mode program this to tRAS(min)/2. No rounding up. When the controller is operating in 1:2.." line.long 0x4 "DRAMTMG1,SDRAM Timing Register 1" hexmask.long.word 0x4 21.--31. 1. "RESERVED,Reserved" newline hexmask.long.byte 0x4 16.--20. 1. "T_XP,tXP - Specifies the minimum time after power-down exit to any operation. For DDR3 this must be programmed to tXPDLL if slow powerdown exit is selected in MR0[12]. If C/A parity for DDR4 is used set to (tXP+PL) instead. If LPDDR4 is selected and.." newline rbitfld.long 0x4 14.--15. "RESERVED,Reserved" "0,1,2,3" newline hexmask.long.byte 0x4 8.--13. 1. "RD2PRE,tRTP - Specifies the minimum time from read to precharge of same bank. - DDR2 - tAL + BL/2 + max(tRTP 2) - 2 - DDR3 - tAL + max (tRTP 4) - DDR4 - Max of following two equations: tAL + max (tRTP 4) or RL + BL/2 - tRP (*). - mDDR - BL/2 - LPDDR2.." newline rbitfld.long 0x4 7. "RESERVED,Reserved" "0,1" newline hexmask.long.byte 0x4 0.--6. 1. "T_RC,tRC - Specifies the minimum time between activates to same bank. When the controller is operating in 1:2 frequency ratio mode program this to (tRC/2) and round up to next integer value. Unit: DFI clock cycles. Programming Mode: Quasi-dynamic Group.." line.long 0x8 "DRAMTMG2,SDRAM Timing Register 2" rbitfld.long 0x8 30.--31. "RESERVED,Reserved" "0,1,2,3" newline hexmask.long.byte 0x8 24.--29. 1. "WRITE_LATENCY,Set this field to WL. Indicates the Time from write command to write data on SDRAM interface. This must be set to WL. For mDDR it must be set to 1. Note that depending on the PHY if using RDIMM/LRDIMM it might be necessary to adjust the.." newline rbitfld.long 0x8 22.--23. "RESERVED,Reserved" "0,1,2,3" newline hexmask.long.byte 0x8 16.--21. 1. "READ_LATENCY,Set this field to RL. Indicates the time from read command to read data on SDRAM interface. This must be set to RL. Note that depending on the PHY if using RDIMM/LRDIMM it might be necessary to adjust the value of RL to compensate for the.." newline rbitfld.long 0x8 14.--15. "RESERVED,Reserved" "0,1,2,3" newline hexmask.long.byte 0x8 8.--13. 1. "RD2WR,DDR2/3/mDDR: RL + BL/2 + 2 - WL DDR4: RL + BL/2 + 1 + WR_PREAMBLE - WL LPDDR2/LPDDR3: RL + BL/2 + RU(tDQSCKmax/tCK) + 1 - WL LPDDR4(DQ ODT is Disabled): RL + BL/2 + RU(tDQSCKmax/tCK) + WR_PREAMBLE + RD_POSTAMBLE - WL LPDDR4(DQ ODT is Enabled): RL +.." newline rbitfld.long 0x8 6.--7. "RESERVED,Reserved" "0,1,2,3" newline hexmask.long.byte 0x8 0.--5. 1. "WR2RD,DDR4: CWL + PL + BL/2 + tWTR_L LPDDR2/3/4: WL + BL/2 + tWTR + 1 Others: CWL + BL/2 + tWTR In DDR4 minimum time from write command to read command for same bank group. In others minimum time from write command to read command. Includes time for.." line.long 0xC "DRAMTMG3,SDRAM Timing Register 3" rbitfld.long 0xC 30.--31. "RESERVED,Reserved" "0,1,2,3" newline hexmask.long.word 0xC 20.--29. 1. "T_MRW,Indicates the time to wait after a mode register write or read (MRW or MRR). Present only in designs configured to support LPDDR2 LPDDR3 or LPDDR4. LPDDR2 typically requires value of 5. LPDDR3 typically requires value of 10. LPDDR4: Set this to.." newline rbitfld.long 0xC 18.--19. "RESERVED,Reserved" "0,1,2,3" newline hexmask.long.byte 0xC 12.--17. 1. "T_MRD,tMRD- Indicates the number of cycles to wait after a mode register write or read. Depending on the connected SDRAM tMRD represents: - DDR2/mDDR: Time from MRS to any command - DDR3/4: Time from MRS to MRS command - LPDDR2: not used - LPDDR3/4:.." newline rbitfld.long 0xC 10.--11. "RESERVED,Reserved" "0,1,2,3" newline hexmask.long.word 0xC 0.--9. 1. "T_MOD,tMOD - Parameter used only in DDR3 and DDR4. Indicates the number of cycles between load mode command and following non-load mode command. If C/A parity for DDR4 is used set to tMOD_PAR(tMOD+PL) instead. If CAL mode is enabled.." line.long 0x10 "DRAMTMG4,SDRAM Timing Register 4" rbitfld.long 0x10 29.--31. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x10 24.--28. 1. "T_RCD,tRCD - tAL: Indicates the minimum time from activate to read or write command to same bank. When the controller is operating in 1:2 frequency ratio mode program this to ((tRCD - tAL)/2) and round it up to the next integer value. Minimum value.." newline hexmask.long.byte 0x10 20.--23. 1. "RESERVED,Reserved" newline hexmask.long.byte 0x10 16.--19. 1. "T_CCD,DDR4: tCCD_L: This is the minimum time between two reads or two writes for same bank group. Others: tCCD: This is the minimum time between two reads or two writes. When the controller is operating in 1:2 frequency ratio mode program this to.." newline hexmask.long.byte 0x10 12.--15. 1. "RESERVED,Reserved" newline hexmask.long.byte 0x10 8.--11. 1. "T_RRD,DDR4: tRRD_L: This is the minimum time between activates from bank 'a' to bank 'b' for same bank group. Others: tRRD: Minimum time between activates from bank 'a' to bank 'b' When the controller is operating in 1:2 frequency ratio mode program.." newline rbitfld.long 0x10 5.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x10 0.--4. 1. "T_RP,tRP: Indicates the minimum time from single-bank precharge to activate of same bank. When the controller is operating in 1:1 frequency ratio mode t_rp must be set to RoundUp(tRP/tCK). When the controller is operating in 1:2 frequency ratio mode.." line.long 0x14 "DRAMTMG5,SDRAM Timing Register 5" hexmask.long.byte 0x14 28.--31. 1. "RESERVED,Reserved" newline hexmask.long.byte 0x14 24.--27. 1. "T_CKSRX,This is the time before self-refresh Exit that CK is maintained as a valid clock before issuing SRX. Specifies the clock stable time before SRX. Recommended settings: - mDDR - 1 - LPDDR2 - 2 - LPDDR3 - 2 - LPDDR4 - tCKCKEH - DDR2 - 1 - DDR3 -.." newline hexmask.long.byte 0x14 20.--23. 1. "RESERVED,Reserved" newline hexmask.long.byte 0x14 16.--19. 1. "T_CKSRE,This is the time after self-refresh Down Entry that CK is maintained as a valid clock. Specifies the clock disable delay after SRE. Recommended settings: - mDDR - 0 - LPDDR2 - 2 - LPDDR3 - 2 - LPDDR4 - tCKELCK - DDR2 - 1 - DDR3 - Max (10 ns 5.." newline rbitfld.long 0x14 14.--15. "RESERVED,Reserved" "0,1,2,3" newline hexmask.long.byte 0x14 8.--13. 1. "T_CKESR,Indicates the minimum CKE low width for self-refresh or self-refresh power down entry to exit timing in memory clock cycles. Recommended settings: - mDDR - tRFC - LPDDR2 - tCKESR - LPDDR3 - tCKESR - LPDDR4 - max(tCKE tSR) - DDR2 - tCKE - DDR3 -.." newline rbitfld.long 0x14 5.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x14 0.--4. 1. "T_CKE,Indicates the minimum number of cycles of CKE HIGH/LOW during power-down and self-refresh. - LPDDR2/LPDDR3 mode - Set this to the larger of tCKE or tCKESR - LPDDR4 mode - Set this to the larger of tCKE or tSR - Non-LPDDR2/non-LPDDR3/non-LPDDR4.." line.long 0x18 "DRAMTMG6,SDRAM Timing Register 6" hexmask.long.byte 0x18 28.--31. 1. "RESERVED,Reserved" newline hexmask.long.byte 0x18 24.--27. 1. "T_CKDPDE,This is the time after Deep Power Down Entry that CK is maintained as a valid clock. Specifies the clock disable delay after DPDE. Recommended settings: - mDDR: 0 - LPDDR2: 2 - LPDDR3: 2 When the controller is operating in 1:2 frequency ratio.." newline hexmask.long.byte 0x18 20.--23. 1. "RESERVED,Reserved" newline hexmask.long.byte 0x18 16.--19. 1. "T_CKDPDX,This is the time before Deep Power Down Exit that CK is maintained as a valid clock before issuing DPDX. Specifies the clock stable time before DPDX. Recommended settings: - mDDR - 1 - LPDDR2 - 2 - LPDDR3 - 2 When the controller is operating in.." newline hexmask.long.word 0x18 4.--15. 1. "RESERVED,Reserved" newline hexmask.long.byte 0x18 0.--3. 1. "T_CKCSX,This is the time before Clock Stop Exit that CK is maintained as a valid clock before issuing Clock Stop Exit. Specifies the clock stable time before next command after Clock Stop Exit. Recommended settings: - mDDR - 1 - LPDDR2 - tXP + 2 - LPDDR3.." line.long 0x1C "DRAMTMG7,SDRAM Timing Register 7" hexmask.long.tbyte 0x1C 12.--31. 1. "RESERVED,Reserved" newline hexmask.long.byte 0x1C 8.--11. 1. "T_CKPDE,This is the time after Power Down Entry that CK is maintained as a valid clock. Specifies the clock disable delay after PDE. Recommended settings: - mDDR - 0 - LPDDR2 - 2 - LPDDR3 - 2 - LPDDR4 - tCKELCK When using DDR2/3/4 SDRAM this register.." newline hexmask.long.byte 0x1C 4.--7. 1. "RESERVED,Reserved" newline hexmask.long.byte 0x1C 0.--3. 1. "T_CKPDX,This is the time before Power Down Exit that CK is maintained as a valid clock before issuing PDX. Specifies the clock stable time before PDX. Recommended settings: - mDDR - 0 - LPDDR2 - 2 - LPDDR3 - 2 - LPDDR4 - tCKCKEH When using DDR2/3/4 SDRAM.." line.long 0x20 "DRAMTMG8,SDRAM Timing Register 8" rbitfld.long 0x20 31. "RESERVED,Reserved" "0,1" newline hexmask.long.byte 0x20 24.--30. 1. "T_XS_FAST_X32,tXS_FAST: Exit self-refresh to ZQCL ZQCS and MRS (only CL WR RTP and Geardown mode). When the controller is operating in 1:2 frequency ratio mode program this to the previous value divided by 2 and round up to next integer value. Note:.." newline rbitfld.long 0x20 23. "RESERVED,Reserved" "0,1" newline hexmask.long.byte 0x20 16.--22. 1. "T_XS_ABORT_X32,tXS_ABORT: Exit self-refresh to commands not requiring a locked DLL in self-refresh Abort. When the controller is operating in 1:2 frequency ratio mode program this to the previous value divided by 2 and round up to next integer value." newline rbitfld.long 0x20 15. "RESERVED,Reserved" "0,1" newline hexmask.long.byte 0x20 8.--14. 1. "T_XS_DLL_X32,tXSDLL: Exit self-refresh to commands requiring a locked DLL. When the controller is operating in 1:2 frequency ratio mode program this to the previous value divided by 2 and round up to next integer value. Note: Used only for DDR2 DDR3.." newline rbitfld.long 0x20 7. "RESERVED,Reserved" "0,1" newline hexmask.long.byte 0x20 0.--6. 1. "T_XS_X32,tXS: Exit self-refresh to commands not requiring a locked DLL. When the controller is operating in 1:2 frequency ratio mode program this to the previous value divided by 2 and round up to next integer value. Note: Used only for DDR2 DDR3 and.." line.long 0x24 "DRAMTMG9,SDRAM Timing Register 9" rbitfld.long 0x24 31. "RESERVED,Reserved" "0,1" newline bitfld.long 0x24 30. "DDR4_WR_PREAMBLE,DDR4 Write preamble mode. - 0 - 1tCK preamble - 1 - 2tCK preamble Present only with MEMC_FREQ_RATIO=2. Programming Mode: Quasi-dynamic Group 2 Group 4" "0,1" newline hexmask.long.word 0x24 19.--29. 1. "RESERVED,Reserved" newline bitfld.long 0x24 16.--18. "T_CCD_S,tCCD_S: This is the minimum time between two reads or two writes for different bank group. For bank switching (from bank 'a' to bank 'b') the minimum time is this value + 1. When the controller is operating in 1:2 frequency ratio mode program.." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x24 12.--15. 1. "RESERVED,Reserved" newline hexmask.long.byte 0x24 8.--11. 1. "T_RRD_S,tRRD_S: This is the minimum time between activates from bank 'a' to bank 'b' for different bank group. When the controller is operating in 1:2 frequency ratio mode program this to (tRRD_S/2) and round it up to the next integer value. Present.." newline rbitfld.long 0x24 6.--7. "RESERVED,Reserved" "0,1,2,3" newline hexmask.long.byte 0x24 0.--5. 1. "WR2RD_S,CWL + PL + BL/2 + tWTR_S Minimum time from write command to read command for different bank group. Includes time for bus turnaround recovery times and all per-bank per-rank and global constraints. Present only in designs configured to support.." line.long 0x28 "DRAMTMG10,SDRAM Timing Register 10" hexmask.long.word 0x28 21.--31. 1. "RESERVED,Reserved" newline hexmask.long.byte 0x28 16.--20. 1. "T_SYNC_GEAR,Indicates the time between MRS command and the sync pulse time. This must be even number of clocks. For DDR4-2666 and DDR4-3200 this parameter is defined as tMOD(min)+4nCK tMOD(min) is greater of 24nCK or 15ns 15ns / .625ns = 24 Max value.." newline rbitfld.long 0x28 13.--15. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x28 8.--12. 1. "T_CMD_GEAR,Indicates a sync pulse to first valid command. For DDR4-2666 and DDR4-3200 this parameter is defined as tMOD(min) tMOD(min) is greater of 24nCK or 15ns 15ns / .625ns = 24 Max value for this register is 24 When the controller is operating in.." newline hexmask.long.byte 0x28 4.--7. 1. "RESERVED,Reserved" newline bitfld.long 0x28 2.--3. "T_GEAR_SETUP,Indicates the geardown setup time. Minimum value of this register is 1. Zero is invalid. For DDR4-2666 and DDR4-3200 this parameter is defined as 2 clks When the controller is operating in 1:2 frequency ratio mode program this to.." "0,1,2,3" newline bitfld.long 0x28 0.--1. "T_GEAR_HOLD,Indicates the geardown hold time. Minimum value of this register is 1. Zero is invalid. For DDR4-2666 and DDR4-3200 this parameter is defined as 2 clks When the controller is operating in 1:2 frequency ratio mode program this to.." "0,1,2,3" line.long 0x2C "DRAMTMG11,SDRAM Timing Register 11" rbitfld.long 0x2C 31. "RESERVED,Reserved" "0,1" newline hexmask.long.byte 0x2C 24.--30. 1. "POST_MPSM_GAP_X32,tXMPDLL: This is the minimum Exit MPSM to commands requiring a locked DLL. When the controller is operating in 1:2 frequency ratio mode program this to (tXMPDLL/2) and round it up to the next integer value. Present only in designs.." newline rbitfld.long 0x2C 21.--23. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x2C 16.--20. 1. "T_MPX_LH,tMPX_LH: This is the minimum CS_n Low hold time to CKE rising edge. When the controller is operating in 1:2 frequency ratio mode program this to RoundUp(tMPX_LH/2)+1. Present only in designs configured to support DDR4. Unit: DFI clock cycles." newline hexmask.long.byte 0x2C 10.--15. 1. "RESERVED,Reserved" newline bitfld.long 0x2C 8.--9. "T_MPX_S,tMPX_S: This is the minimum time CS setup time to CKE. When the controller is operating in 1:2 frequency ratio mode program this to (tMPX_S/2) and round it up to the next integer value. Present only in designs configured to support DDR4. Unit:.." "0,1,2,3" newline rbitfld.long 0x2C 5.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x2C 0.--4. 1. "T_CKMPE,tCKMPE: This is the minimum valid clock requirement after MPSM entry. Present only in designs configured to support DDR4. When the controller is operating in 1:2 frequency ratio mode divide the value calculated using the previous equation by 2.." line.long 0x30 "DRAMTMG12,SDRAM Timing Register 12" rbitfld.long 0x30 30.--31. "RESERVED,Reserved" "0,1,2,3" newline hexmask.long.byte 0x30 24.--29. 1. "T_WR_MPR,This bit is used only in DDR4. Cycles between MPR Write and other command. Set this to tMOD + AL (or tMOD + PL + AL if C/A parity is also used). When the controller is operating in 1:2 frequency ratio mode program this to (tWR_MPR/2) and round.." newline hexmask.long.byte 0x30 18.--23. 1. "RESERVED,Reserved" newline bitfld.long 0x30 16.--17. "T_CMDCKE,tCMDCKE: Indicates the delay from valid command to CKE input LOW. Set this to the larger of tESCKE or tCMDCKE When the controller is operating in 1:2 frequency ratio mode program this to (max(tESCKE tCMDCKE)/2) and round it up to the next.." "0,1,2,3" newline hexmask.long.word 0x30 5.--15. 1. "RESERVED,Reserved" newline hexmask.long.byte 0x30 0.--4. 1. "T_MRD_PDA,tMRD_PDA: This is the Mode Register Set command cycle time in PDA mode. When the controller is operating in 1:2 frequency ratio mode program this to (tMRD_PDA/2) and round it up to the next integer value. Unit: DFI clock cycles. Programming.." line.long 0x34 "DRAMTMG13,SDRAM Timing Register 13" rbitfld.long 0x34 31. "RESERVED,Reserved" "0,1" newline hexmask.long.byte 0x34 24.--30. 1. "ODTLOFF,LPDDR4: ODTLoff: This is the latency from CAS-2 command to ODToff reference. When the controller is operating in 1:2 frequency ratio mode program this to (ODTLoff/2) and round it up to the next integer value. Unit: DFI clock cycles. Programming.." newline rbitfld.long 0x34 22.--23. "RESERVED,Reserved" "0,1,2,3" newline hexmask.long.byte 0x34 16.--21. 1. "T_CCD_MW,LPDDR4: tCCDMW: This is the minimum time from write or masked write to masked write command for same bank. When the controller is operating in 1:2 frequency ratio mode program this to (tCCDMW/2) and round it up to the next integer value. Unit:.." newline hexmask.long.word 0x34 3.--15. 1. "RESERVED,Reserved" newline bitfld.long 0x34 0.--2. "T_PPD,LPDDR4: tPPD: This is the minimum time from precharge to precharge command. When the controller is operating in 1:2 frequency ratio mode program this to (tPPD/2) and round it up to the next integer value. Unit: DFI clock cycles. Programming Mode:.." "?,?,?,?,tPPD: This is the minimum time from precharge to..,?,?,?" line.long 0x38 "DRAMTMG14,SDRAM Timing Register 14" hexmask.long.tbyte 0x38 12.--31. 1. "RESERVED,Reserved" newline hexmask.long.word 0x38 0.--11. 1. "T_XSR,tXSR: This is the exit self-refresh to any command. When the controller is operating in 1:2 frequency ratio mode program this to the previous value divided by 2 and round up to next integer value. The value 0xfff is illegal for this register.." line.long 0x3C "DRAMTMG15,SDRAM Timing Register 15" bitfld.long 0x3C 31. "EN_DFI_LP_T_STAB,- 1 - Enable using tSTAB when exiting DFI LP. This must be set when the PHY is stopping the clock during DFI LP to save maximum power. - 0 - Disable using tSTAB when exiting DFI LP. Programming Mode: Quasi-dynamic Group 2 Group 4" "Disable using tSTAB when exiting DFI LP,Enable using tSTAB when exiting DFI LP" newline hexmask.long.tbyte 0x3C 8.--30. 1. "RESERVED,Reserved" newline hexmask.long.byte 0x3C 0.--7. 1. "T_STAB_X32,tSTAB: Stabilization time. It is required in the following two cases for DDR3/DDR4 RDIMM: - When exiting power saving mode if the clock is stopped after re-enabling it the clock must be stable for a time specified by tSTAB - In the case of.." group.long 0x180++0xB line.long 0x0 "ZQCTL0,ZQ Control Register 0" bitfld.long 0x0 31. "DIS_AUTO_ZQ,- 1 - Disable uMCTL2 generation of ZQCS/MPC(ZQ calibration) command. Register DBGCMD.zq_calib_short can be used instead to issue ZQ calibration request from APB module - 0 - Internally generate ZQCS/MPC(ZQ calibration) commands based on.." "Internally generate ZQCS/MPC,Disable uMCTL2 generation of ZQCS/MPC" newline bitfld.long 0x0 30. "DIS_SRX_ZQCL,- 1 - Disable issuing of ZQCL/MPC(ZQ calibration) command at self-refresh/SR-Powerdown exit. Only applicable when run in DDR3 or DDR4 or LPDDR2 or LPDDR3 or LPDDR4 mode - 0 - Enable issuing of ZQCL/MPC(ZQ calibration) command at.." "Enable issuing of ZQCL/MPC,Disable issuing of ZQCL/MPC" newline bitfld.long 0x0 29. "ZQ_RESISTOR_SHARED,- 1 - Denotes that ZQ resistor is shared between ranks. Means ZQinit/ZQCL/ZQCS/MPC(ZQ calibration) commands are sent to one rank at a time with tZQinit/tZQCL/tZQCS/tZQCAL/tZQLAT timing met between commands so that commands to different.." "ZQ resistor is not shared,Denotes that ZQ resistor is shared between ranks" newline bitfld.long 0x0 28. "DIS_MPSMX_ZQCL,- 1 - Disable issuing of ZQCL command at Maximum Power Saving Mode exit. Only applicable when run in DDR4 mode - 0 - Enable issuing of ZQCL command at Maximum Power Saving Mode exit. Only applicable when run in DDR4 mode This is only.." "Enable issuing of ZQCL command at Maximum Power..,Disable issuing of ZQCL command at Maximum Power.." newline rbitfld.long 0x0 27. "RESERVED,Reserved" "0,1" newline hexmask.long.word 0x0 16.--26. 1. "T_ZQ_LONG_NOP,tZQoper for DDR3/DDR4 tZQCL for LPDDR2/LPDDR3 tZQCAL for LPDDR4: Number of DFI clock cycles of NOP required after a ZQCL (ZQ calibration long)/MPC(ZQ Start) command is issued to SDRAM. When the controller is operating in 1:2 frequency.." newline hexmask.long.byte 0x0 10.--15. 1. "RESERVED,Reserved" newline hexmask.long.word 0x0 0.--9. 1. "T_ZQ_SHORT_NOP,tZQCS for DDR3/DD4/LPDDR2/LPDDR3 tZQLAT for LPDDR4: Number of DFI clock cycles of NOP required after a ZQCS (ZQ calibration short)/MPC(ZQ Latch) command is issued to SDRAM. When the controller is operating in 1:2 frequency ratio mode.." line.long 0x4 "ZQCTL1,ZQ Control Register 1" rbitfld.long 0x4 30.--31. "RESERVED,Reserved" "0,1,2,3" newline hexmask.long.word 0x4 20.--29. 1. "T_ZQ_RESET_NOP,tZQReset: Number of DFI clock cycles of NOP required after a ZQReset (ZQ calibration Reset) command is issued to SDRAM. When the controller is operating in 1:2 frequency ratio mode program this to tZQReset/2 and round it up to the next.." newline hexmask.long.tbyte 0x4 0.--19. 1. "T_ZQ_SHORT_INTERVAL_X1024,Indicates the average interval to wait between automatically issuing ZQCS (ZQ calibration short)/MPC(ZQ calibration) commands to DDR3/DDR4/LPDDR2/LPDDR3/LPDDR4 devices. Meaningless if ZQCTL0.dis_auto_zq=1. This is only present.." line.long 0x8 "ZQCTL2,ZQ Control Register 2" hexmask.long 0x8 1.--31. 1. "RESERVED,Reserved" newline bitfld.long 0x8 0. "ZQ_RESET,Setting this register bit to 1 triggers a ZQ Reset operation. When the ZQ Reset operation is complete the uMCTL2 automatically clears this bit. It is recommended NOT to set this register bit if in Init in self-refresh(except LPDDR4) or.." "0,1" rgroup.long 0x18C++0x3 line.long 0x0 "ZQSTAT,ZQ Status Register" hexmask.long 0x0 1.--31. 1. "RESERVED,Reserved" newline bitfld.long 0x0 0. "ZQ_RESET_BUSY,SoC might initiate a ZQ Reset operation only if this signal is low. This signal goes high in the clock after the uMCTL2 accepts the ZQ Reset request. It goes low when the ZQ Reset command is issued to the SDRAM and the associated NOP period.." "Indicates that the SoC can initiate a ZQ Reset..,Indicates that ZQ Reset operation is in progress" group.long 0x190++0x1B line.long 0x0 "DFITMG0,DFI Timing Register 0" rbitfld.long 0x0 29.--31. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x0 24.--28. 1. "DFI_T_CTRL_DELAY,Specifies the number of DFI clock cycles after an assertion or de-assertion of the DFI control signals that the control signals at the PHY-DRAM interface reflect the assertion or de-assertion. If the DFI clock and the memory clock are.." newline bitfld.long 0x0 23. "DFI_RDDATA_USE_DFI_PHY_CLK,Defines whether dfi_rddata_en/dfi_rddata/dfi_rddata_valid is generated using HDR (DFI clock) or SDR (DFI PHY clock) values. Selects whether value in DFITMG0.dfi_t_rddata_en is in terms of HDR (DFI clock) or SDR (DFI PHY clock).." "Else,?" newline hexmask.long.byte 0x0 16.--22. 1. "DFI_T_RDDATA_EN,Time from the assertion of a read command on the DFI interface to the assertion of the dfi_rddata_en signal. Refer to PHY specification for correct value. This corresponds to the DFI parameter trddata_en. Note that depending on the PHY.." newline bitfld.long 0x0 15. "DFI_WRDATA_USE_DFI_PHY_CLK,Defines whether dfi_wrdata_en/dfi_wrdata/dfi_wrdata_mask is generated using HDR (DFI clock) or SDR (DFI PHY clock) values. Selects whether value in DFITMG0.dfi_tphy_wrlat is in terms of HDR (DFI clock) or SDR (DFI PHY clock).." "Else,?" newline rbitfld.long 0x0 14. "RESERVED,Reserved" "0,1" newline hexmask.long.byte 0x0 8.--13. 1. "DFI_TPHY_WRDATA,Specifies the number of clock cycles between when dfi_wrdata_en is asserted to when the associated write data is driven on the dfi_wrdata signal. This corresponds to the DFI timing parameter tphy_wrdata. For more information on correct.." newline rbitfld.long 0x0 6.--7. "RESERVED,Reserved" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "DFI_TPHY_WRLAT,Write latency. Number of clocks from the write command to write data enable (dfi_wrdata_en). This corresponds to the DFI timing parameter tphy_wrlat. Refer to PHY specification for correct value.Note that depending on the PHY if using.." line.long 0x4 "DFITMG1,DFI Timing Register 1" hexmask.long.byte 0x4 28.--31. 1. "DFI_T_CMD_LAT,Specifies the number of DFI PHY clock cycles between when the dfi_cs signal is asserted and when the associated command is driven. This field is used for CAL mode must be set to '0' or tCAL which matches the CAL mode register setting in.." newline rbitfld.long 0x4 26.--27. "RESERVED,Reserved" "0,1,2,3" newline bitfld.long 0x4 24.--25. "DFI_T_PARIN_LAT,Specifies the number of DFI PHY clock cycles between when the dfi_cs signal is asserted and when the associated dfi_parity_in signal is driven. Unit: DFI PHY clock cycles. Programming Mode: Quasi-dynamic Group 4" "0,1,2,3" newline rbitfld.long 0x4 21.--23. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x4 16.--20. 1. "DFI_T_WRDATA_DELAY,Specifies the number of DFI clock cycles between when the dfi_wrdata_en signal is asserted and when the corresponding write data transfer is completed on the DRAM bus. This corresponds to the DFI timing parameter twrdata_delay. For.." newline rbitfld.long 0x4 13.--15. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x4 8.--12. 1. "DFI_T_DRAM_CLK_DISABLE,Specifies the number of DFI clock cycles from the assertion of the dfi_dram_clk_disable signal on the DFI until the clock to the DRAM memory devices at the PHY-DRAM boundary maintains a low value. If the DFI clock and the memory.." newline rbitfld.long 0x4 5.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x4 0.--4. 1. "DFI_T_DRAM_CLK_ENABLE,Specifies the number of DFI clock cycles from the de-assertion of the dfi_dram_clk_disable signal on the DFI until the first valid rising edge of the clock to the DRAM memory devices at the PHY-DRAM boundary. If the DFI clock and.." line.long 0x8 "DFILPCFG0,DFI Low Power Configuration Register 0" rbitfld.long 0x8 29.--31. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x8 24.--28. 1. "DFI_TLP_RESP,Indicates the setting in DFI clock cycles for DFI's tlp_resp time. Same value is used for both Power Down self-refresh Deep Power Down and Maximum Power Saving modes. For more information on recommended values see PHY databook Unit: DFI.." newline hexmask.long.byte 0x8 20.--23. 1. "DFI_LP_WAKEUP_DPD,Indicates the value in DFI clock cycles to drive on dfi_lp_wakeup signal when Deep Power Down mode is entered. Determines the DFI's tlp_wakeup time: - 0x0 - 16 cycles - 0x1 - 32 cycles - 0x2 - 64 cycles - 0x3 - 128 cycles - 0x4 - 256.." newline rbitfld.long 0x8 17.--19. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 16. "DFI_LP_EN_DPD,Enables DFI Low Power interface handshaking during Deep Power Down Entry/Exit. - 0 - Disabled - 1 - Enabled This is only present for designs supporting mDDR or LPDDR2/LPDDR3 devices. Programming Mode: Static" "Disabled,Enabled" newline hexmask.long.byte 0x8 12.--15. 1. "DFI_LP_WAKEUP_SR,Indicates the value in DFI clock cycles to drive on dfi_lp_wakeup signal when self-refresh mode is entered. Determines the DFI's tlp_wakeup time: - 0x0 - 16 cycles - 0x1 - 32 cycles - 0x2 - 64 cycles - 0x3 - 128 cycles - 0x4 - 256 cycles.." newline rbitfld.long 0x8 9.--11. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 8. "DFI_LP_EN_SR,Enables DFI Low Power interface handshaking during self-refresh Entry/Exit. - 0 - Disabled - 1 - Enabled Programming Mode: Static" "Disabled,Enabled" newline hexmask.long.byte 0x8 4.--7. 1. "DFI_LP_WAKEUP_PD,Indicates the value in DFI clock cycles to drive on dfi_lp_wakeup signal when Power Down mode is entered. Determines the DFI's tlp_wakeup time: - 0x0 - 16 cycles - 0x1 - 32 cycles - 0x2 - 64 cycles - 0x3 - 128 cycles - 0x4 - 256 cycles -.." newline rbitfld.long 0x8 1.--3. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 0. "DFI_LP_EN_PD,Enables DFI Low Power interface handshaking during Power Down Entry/Exit. - 0 - Disabled - 1 - Enabled Programming Mode: Static" "Disabled,Enabled" line.long 0xC "DFILPCFG1,DFI Low Power Configuration Register 1" hexmask.long.tbyte 0xC 8.--31. 1. "RESERVED,Reserved" newline hexmask.long.byte 0xC 4.--7. 1. "DFI_LP_WAKEUP_MPSM,Indicates the value in DFI clock cycles to drive on dfi_lp_wakeup signal when Maximum Power Saving Mode is entered. Determines the DFI's tlp_wakeup time: - 0x0 - 16 cycles - 0x1 - 32 cycles - 0x2 - 64 cycles - 0x3 - 128 cycles - 0x4 -.." newline rbitfld.long 0xC 1.--3. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline bitfld.long 0xC 0. "DFI_LP_EN_MPSM,Enables DFI Low Power interface handshaking during Maximum Power Saving Mode Entry/Exit. - 0 - Disabled - 1 - Enabled This is only present for designs supporting DDR4 devices. Programming Mode: Static" "Disabled,Enabled" line.long 0x10 "DFIUPD0,DFI Update Register 0" bitfld.long 0x10 31. "DIS_AUTO_CTRLUPD,When '1' disable the automatic dfi_ctrlupd_req generation by the uMCTL2. The controller must issue the dfi_ctrlupd_req signal using register DBGCMD.ctrlupd. When '0' uMCTL2 issues dfi_ctrlupd_req periodically. Programming Mode:.." "0,1" newline bitfld.long 0x10 30. "DIS_AUTO_CTRLUPD_SRX,When '1' disable the automatic dfi_ctrlupd_req generation by the uMCTL2 at self-refresh exit. When '0' uMCTL2 issues a dfi_ctrlupd_req before or after exiting self-refresh depending on DFIUPD0.ctrlupd_pre_srx. Programming Mode:.." "0,1" newline bitfld.long 0x10 29. "CTRLUPD_PRE_SRX,Selects dfi_ctrlupd_req requirements at SRX: - 0 - Send ctrlupd after SRX - 1 - Send ctrlupd before SRX If DFIUPD0.dis_auto_ctrlupd_srx=1 this register has no impact because no dfi_ctrlupd_req is issued when SRX. Programming Mode: Static" "Send ctrlupd after SRX,Send ctrlupd before SRX" newline rbitfld.long 0x10 26.--28. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline hexmask.long.word 0x10 16.--25. 1. "DFI_T_CTRLUP_MAX,Specifies the maximum number of DFI clock cycles that the dfi_ctrlupd_req signal can assert. Lowest value to assign to this variable is 0x40. Unit: DFI clock cycles. Programming Mode: Static" newline hexmask.long.byte 0x10 10.--15. 1. "RESERVED,Reserved" newline hexmask.long.word 0x10 0.--9. 1. "DFI_T_CTRLUP_MIN,Specifies the minimum number of DFI clock cycles that the dfi_ctrlupd_req signal must be asserted. The uMCTL2 expects the PHY to respond within this time. If the PHY does not respond the uMCTL2 de-asserts dfi_ctrlupd_req after.." line.long 0x14 "DFIUPD1,DFI Update Register 1" hexmask.long.byte 0x14 24.--31. 1. "RESERVED,Reserved" newline hexmask.long.byte 0x14 16.--23. 1. "DFI_T_CTRLUPD_INTERVAL_MIN_X1024,This is the minimum amount of time between uMCTL2 initiated DFI update requests (which is executed whenever the uMCTL2 is idle). Set this number higher to reduce the frequency of update requests which can have a small.." newline hexmask.long.byte 0x14 8.--15. 1. "RESERVED,Reserved" newline hexmask.long.byte 0x14 0.--7. 1. "DFI_T_CTRLUPD_INTERVAL_MAX_X1024,This is the maximum amount of time between uMCTL2 initiated DFI update requests. This timer resets with each update request; when the timer expires dfi_ctrlupd_req is sent and traffic is blocked until the dfi_ctrlupd_ackx.." line.long 0x18 "DFIUPD2,DFI Update Register 2" bitfld.long 0x18 31. "DFI_PHYUPD_EN,Enables the support for acknowledging PHY-initiated updates: - 0 - Disabled - 1 - Enabled Programming Mode: Static" "Disabled,Enabled" newline hexmask.long 0x18 0.--30. 1. "RESERVED,Reserved" group.long 0x1B0++0xB line.long 0x0 "DFIMISC,DFI Miscellaneous Control Register" hexmask.long.tbyte 0x0 13.--31. 1. "RESERVED,Reserved" newline hexmask.long.byte 0x0 8.--12. 1. "DFI_FREQUENCY,Indicates the operating frequency of the system. The number of supported frequencies and the mapping of signal values to clock frequencies are defined by the PHY. Programming Mode: Quasi-dynamic Group 1" newline bitfld.long 0x0 7. "LP_OPTIMIZED_WRITE,If this bit is 1 LPDDR4 write DQ is set to 8'hF8 if masked write with enabling DBI; otherwise that value is set to 8'hFF. Programming Mode: Quasi-dynamic Group 3" "0,1" newline bitfld.long 0x0 6. "DIS_DYN_ADR_TRI,If this bit is 1 PHY specific Dynamic Tristating which is a specific feature to certain Synopsys PHYs is disabled. If this bit is 0 a special IDLE command is issued on the DFI while dfi_cs is inactive state so that the PHY can detect.." "?,phase 0 and 1) dfi_we_n= 1" newline bitfld.long 0x0 5. "DFI_INIT_START,PHY init start request signal.When asserted it triggers the PHY init start request. Programming Mode: Quasi-dynamic Group 3" "0,1" newline bitfld.long 0x0 4. "CTL_IDLE_EN,Enables support of ctl_idle signal which is non-DFI related pin specific to certain Synopsys PHYs. For more information on ctl_idle functionality see signal description of ctl_idle signal. Programming Mode: Static" "0,1" newline rbitfld.long 0x0 3. "RESERVED,Reserved" "0,1" newline bitfld.long 0x0 2. "DFI_DATA_CS_POLARITY,Defines polarity of dfi_wrdata_cs and dfi_rddata_cs signals. - 0 - Signals are active low - 1 - Signals are active high Programming Mode: Static" "Signals are active low,Signals are active high" newline bitfld.long 0x0 1. "PHY_DBI_MODE,DBI implemented in DDRC or PHY. - 0 - DDRC implements DBI functionality - 1 - PHY implements DBI functionality Present only in designs configured to support DDR4 and LPDDR4. Programming Mode: Static" "DDRC implements DBI functionality,PHY implements DBI functionality" newline bitfld.long 0x0 0. "DFI_INIT_COMPLETE_EN,PHY initialization complete enable signal. When asserted the dfi_init_complete signal can be used to trigger SDRAM initialisation Programming Mode: Quasi-dynamic Group 3" "0,1" line.long 0x4 "DFITMG2,DFI Timing Register 2" hexmask.long.tbyte 0x4 15.--31. 1. "RESERVED,Reserved" newline hexmask.long.byte 0x4 8.--14. 1. "DFI_TPHY_RDCSLAT,specifies the number of DFI PHY clock cycles between when a read command is sent on the DFI control interface and when the associated dfi_rddata_cs signal is asserted. This corresponds to the DFI timing parameter tphy_rdcslat. Refer to.." newline rbitfld.long 0x4 6.--7. "RESERVED,Reserved" "0,1,2,3" newline hexmask.long.byte 0x4 0.--5. 1. "DFI_TPHY_WRCSLAT,Specifies the number of DFI PHY clock cycles between when a write command is sent on the DFI control interface and when the associated dfi_wrdata_cs signal is asserted. This corresponds to the DFI timing parameter tphy_wrcslat. For more.." line.long 0x8 "DFITMG3,DFI Timing Register 3" hexmask.long 0x8 5.--31. 1. "RESERVED,Reserved" newline hexmask.long.byte 0x8 0.--4. 1. "DFI_T_GEARDOWN_DELAY,The delay from dfi_geardown_en assertion to the time of the PHY being ready to receive commands. Refer to PHY specification for correct value. When the controller is operating in 1:2 frequency ratio mode program this to.." rgroup.long 0x1BC++0x3 line.long 0x0 "DFISTAT,DFI Status Register" hexmask.long 0x0 2.--31. 1. "RESERVED,Reserved" newline bitfld.long 0x0 1. "DFI_LP_ACK,Stores the value of the dfi_lp_ack input to the controller. Programming Mode: Dynamic" "0,1" newline bitfld.long 0x0 0. "DFI_INIT_COMPLETE,This a status flag register which announces when the DFI initialization has been completed. The DFI INIT triggered by dfi_init_start signal and then the dfi_init_complete flag is polled to know when the initialization is done." "0,1" group.long 0x1C0++0x7 line.long 0x0 "DBICTL,DM/DBI Control Register" hexmask.long 0x0 3.--31. 1. "RESERVED,Reserved" newline bitfld.long 0x0 2. "RD_DBI_EN,Read DBI enable signal in DDRC. - 0 - Read DBI is disabled - 1 - Read DBI is enabled This signal must be set the same value as DRAM's mode register. - DDR4 - MR5 bit A12. When x4 devices are used this signal must be set to 0 - LPDDR4 - MR3[6].." "LPDDR4,Read DBI is enabled" newline bitfld.long 0x0 1. "WR_DBI_EN,Write DBI enable signal in DDRC. - 0 - Write DBI is disabled - 1 - Write DBI is enabled This signal must be set the same value as DRAM's mode register. - DDR4 - MR5 bit A11. When x4 devices are used this signal must be set to 0 - LPDDR4 -.." "LPDDR4,Write DBI is enabled" newline bitfld.long 0x0 0. "DM_EN,Indicates the DM enable signal in DDRC. - 0 - DM is disabled - 1 - DM is enabled This signal must be set the same logical value as DRAM's mode register. - DDR4 - Set this to same value as MR5 bit A10. When x4 devices are used this signal must be.." "LPDDR4,DM is enabled" line.long 0x4 "DFIPHYMSTR,DFI PHY Master" hexmask.long 0x4 1.--31. 1. "RESERVED,Reserved" newline bitfld.long 0x4 0. "DFI_PHYMSTR_EN,Enables the PHY Master Interface: - 0 - Disabled - 1 - Enabled Programming Mode: Static" "Disabled,Enabled" group.long 0x200++0x13 line.long 0x0 "ADDRMAP0,Address Map Register 0" hexmask.long 0x0 5.--31. 1. "RESERVED,Reserved" newline hexmask.long.byte 0x0 0.--4. 1. "ADDRMAP_CS_BIT0,Selects the HIF address bit used as rank address bit 0. Valid Range: 0 to 29 and 31 Internal Base: 6 The selected HIF address bit is determined by adding the internal base to the value of this field. If unused set to 31 and then rank.." line.long 0x4 "ADDRMAP1,Address Map Register 1" hexmask.long.word 0x4 22.--31. 1. "RESERVED,Reserved" newline hexmask.long.byte 0x4 16.--21. 1. "ADDRMAP_BANK_B2,Selects the HIF address bit used as bank address bit 2. Valid Range: 0 to 31 and 63 Internal Base: 4 The selected HIF address bit is determined by adding the internal base to the value of this field. If unused set to 63 and then bank.." newline rbitfld.long 0x4 14.--15. "RESERVED,Reserved" "0,1,2,3" newline hexmask.long.byte 0x4 8.--13. 1. "ADDRMAP_BANK_B1,Selects the HIF address bits used as bank address bit 1. Valid Range: 0 to 32 and 63 Internal Base: 3 The selected HIF address bit for each of the bank address bits is determined by adding the internal base to the value of this field. If.." newline rbitfld.long 0x4 6.--7. "RESERVED,Reserved" "0,1,2,3" newline hexmask.long.byte 0x4 0.--5. 1. "ADDRMAP_BANK_B0,Selects the HIF address bits used as bank address bit 0. Valid Range: 0 to 32 and 63 Internal Base: 2 The selected HIF address bit for each of the bank address bits is determined by adding the internal base to the value of this field. If.." line.long 0x8 "ADDRMAP2,Address Map Register 2" hexmask.long.byte 0x8 28.--31. 1. "RESERVED,Reserved" newline hexmask.long.byte 0x8 24.--27. 1. "ADDRMAP_COL_B5,- Full bus width mode - Selects the HIF address bit used as column address bit 5 - Half bus width mode - Selects the HIF address bit used as column address bit 6 - Quarter bus width mode - Selects the HIF address bit used as column address.." newline hexmask.long.byte 0x8 20.--23. 1. "RESERVED,Reserved" newline hexmask.long.byte 0x8 16.--19. 1. "ADDRMAP_COL_B4,- Full bus width mode - Selects the HIF address bit used as column address bit 4 - Half bus width mode - Selects the HIF address bit used as column address bit 5 - Quarter bus width mode - Selects the HIF address bit used as column address.." newline rbitfld.long 0x8 13.--15. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x8 8.--12. 1. "ADDRMAP_COL_B3,- Full bus width mode - Selects the HIF address bit used as column address bit 3 - Half bus width mode - Selects the HIF address bit used as column address bit 4 - Quarter bus width mode - Selects the HIF address bit used as column address.." newline hexmask.long.byte 0x8 4.--7. 1. "RESERVED,Reserved" newline hexmask.long.byte 0x8 0.--3. 1. "ADDRMAP_COL_B2,- Full bus width mode - Selects the HIF address bit used as column address bit 2 - Half bus width mode - Selects the HIF address bit used as column address bit 3 - Quarter bus width mode - Selects the HIF address bit used as column address.." line.long 0xC "ADDRMAP3,Address Map Register 3" rbitfld.long 0xC 29.--31. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0xC 24.--28. 1. "ADDRMAP_COL_B9,- Full bus width mode - Selects the HIF address bit used as column address bit 9 - Half bus width mode - Selects the HIF address bit used as column address bit 11 (10 in LPDDR2/LPDDR3 mode) - Quarter bus width mode - Selects the HIF.." newline rbitfld.long 0xC 21.--23. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0xC 16.--20. 1. "ADDRMAP_COL_B8,- Full bus width mode - Selects the HIF address bit used as column address bit 8 - Half bus width mode - Selects the HIF address bit used as column address bit 9 - Quarter bus width mode - Selects the HIF address bit used as column address.." newline rbitfld.long 0xC 13.--15. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0xC 8.--12. 1. "ADDRMAP_COL_B7,- Full bus width mode - Selects the HIF address bit used as column address bit 7 - Half bus width mode - Selects the HIF address bit used as column address bit 8 - Quarter bus width mode - Selects the HIF address bit used as column address.." newline rbitfld.long 0xC 5.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0xC 0.--4. 1. "ADDRMAP_COL_B6,- Full bus width mode - Selects the HIF address bit used as column address bit 6. - Half bus width mode - Selects the HIF address bit used as column address bit 7. - Quarter bus width mode - Selects the HIF address bit used as column.." line.long 0x10 "ADDRMAP4,Address Map Register 4" bitfld.long 0x10 31. "COL_ADDR_SHIFT,The register provides a capability to map column address to lower HIF address in specific cases required by inline ECC configuration. - If it is 1 internal base of all the column address can be -2 to make mapping range of column address.." "0,1" newline hexmask.long.tbyte 0x10 13.--30. 1. "RESERVED,Reserved" newline hexmask.long.byte 0x10 8.--12. 1. "ADDRMAP_COL_B11,- Full bus width mode - Selects the HIF address bit used as column address bit 13 (11 in LPDDR2/LPDDR3 mode) - Half bus width mode - UNUSED. See later in this description for value you need to set to make it unused - Quarter bus width.." newline rbitfld.long 0x10 5.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x10 0.--4. 1. "ADDRMAP_COL_B10,- Full bus width mode: Selects the HIF address bit used as column address bit 11 (10 in LPDDR2/LPDDR3 mode) - Half bus width mode: Selects the HIF address bit used as column address bit 13 (11 in LPDDR2/LPDDR3 mode) - Quarter bus width.." repeat 3. (list 0x5 0x9 0xA )(list 0x0 0x10 0x14 ) group.long ($2+0x214)++0x3 line.long 0x0 "ADDRMAP$1,Address Map Register 5" hexmask.long.byte 0x0 28.--31. 1. "RESERVED,Reserved" newline hexmask.long.byte 0x0 24.--27. 1. "ADDRMAP_ROW_B11,Selects the HIF address bit used as row address bit 11. Valid Range: 0 to 11 and 15 Internal Base: 17 The selected HIF address bit is determined by adding the internal base to the value of this field. If unused set to 15 and then row.." newline hexmask.long.byte 0x0 20.--23. 1. "RESERVED,Reserved" newline hexmask.long.byte 0x0 16.--19. 1. "ADDRMAP_ROW_B2_10,Selects the HIF address bits used as row address bits 2 to 10. Valid Range: 0 to 11 and 15 Internal Base: 8 (for row address bit 2) 9 (for row address bit 3) 10 (for row address bit 4) and so on increasing to 16 (for row address bit.." newline hexmask.long.byte 0x0 12.--15. 1. "RESERVED,Reserved" newline hexmask.long.byte 0x0 8.--11. 1. "ADDRMAP_ROW_B1,Selects the HIF address bits used as row address bit 1. Valid Range: 0 to 11 Internal Base: 7 The selected HIF address bit for each of the row address bits is determined by adding the internal base to the value of this field. Programming.." newline hexmask.long.byte 0x0 4.--7. 1. "RESERVED,Reserved" newline hexmask.long.byte 0x0 0.--3. 1. "ADDRMAP_ROW_B0,Selects the HIF address bits used as row address bit 0. Valid Range: 0 to 11 Internal Base: 6 The selected HIF address bit for each of the row address bits is determined by adding the internal base to the value of this field. Programming.." repeat.end group.long 0x218++0xB line.long 0x0 "ADDRMAP6,Address Map Register 6" bitfld.long 0x0 31. "LPDDR3_6GB_12GB,Set this to 1 if there is an LPDDR3 SDRAM 6Gb or 12Gb device in use. - 1 - LPDDR3 SDRAM 6Gb/12Gb device in use. Every address having row[14:13]==2'b11 is considered as invalid - 0 - non-LPDDR3 6Gb/12Gb device in use. All addresses are.." "non-LPDDR3 6Gb/12Gb device in use,LPDDR3 SDRAM 6Gb/12Gb device in use" newline bitfld.long 0x0 29.--30. "LPDDR4_3GB_6GB_12GB,Indicates what type of LPDDR4 SDRAM device is in use. Here the density size is per channel. - 2'b00 - No LPDDR4 SDRAM 3Gb/6Gb/12Gb device in use. All addresses are valid - 2'b01 - LPDDR4 SDRAM 3Gb device with x16 mode in use. Every.." "No LPDDR4 SDRAM 3Gb/6Gb/12Gb device in use,LPDDR4 SDRAM 3Gb device with x16 mode in use,LPDDR4 SDRAM 6Gb device with x16 mode or 3Gb..,LPDDR4 SDRAM 12Gb device with x16 mode or 6Gb.." newline rbitfld.long 0x0 28. "RESERVED,Reserved" "0,1" newline hexmask.long.byte 0x0 24.--27. 1. "ADDRMAP_ROW_B15,Selects the HIF address bit used as row address bit 15. Valid Range: 0 to 11 and 15 Internal Base: 21 The selected HIF address bit is determined by adding the internal base to the value of this field. If unused set to 15 and then row.." newline hexmask.long.byte 0x0 20.--23. 1. "RESERVED,Reserved" newline hexmask.long.byte 0x0 16.--19. 1. "ADDRMAP_ROW_B14,Selects the HIF address bit used as row address bit 14. Valid Range: 0 to 11 and 15 Internal Base: 20 The selected HIF address bit is determined by adding the internal base to the value of this field. If unused set to 15 and then row.." newline hexmask.long.byte 0x0 12.--15. 1. "RESERVED,Reserved" newline hexmask.long.byte 0x0 8.--11. 1. "ADDRMAP_ROW_B13,Selects the HIF address bit used as row address bit 13. Valid Range: 0 to 11 and 15 Internal Base: 19 The selected HIF address bit is determined by adding the internal base to the value of this field. If unused set to 15 and then row.." newline hexmask.long.byte 0x0 4.--7. 1. "RESERVED,Reserved" newline hexmask.long.byte 0x0 0.--3. 1. "ADDRMAP_ROW_B12,Selects the HIF address bit used as row address bit 12. Valid Range: 0 to 11 and 15 Internal Base: 18 The selected HIF address bit is determined by adding the internal base to the value of this field. If unused set to 15 and then row.." line.long 0x4 "ADDRMAP7,Address Map Register 7" hexmask.long.tbyte 0x4 12.--31. 1. "RESERVED,Reserved" newline hexmask.long.byte 0x4 8.--11. 1. "ADDRMAP_ROW_B17,Selects the HIF address bit used as row address bit 17. Valid Range: 0 to 11 and 15 Internal Base: 23 The selected HIF address bit is determined by adding the internal base to the value of this field. If unused set to 15 and then row.." newline hexmask.long.byte 0x4 4.--7. 1. "RESERVED,Reserved" newline hexmask.long.byte 0x4 0.--3. 1. "ADDRMAP_ROW_B16,Selects the HIF address bit used as row address bit 16. Valid Range: 0 to 11 and 15 Internal Base: 22 The selected HIF address bit is determined by adding the internal base to the value of this field. If unused set to 15 and then row.." line.long 0x8 "ADDRMAP8,Address Map Register 8" hexmask.long.tbyte 0x8 14.--31. 1. "RESERVED,Reserved" newline hexmask.long.byte 0x8 8.--13. 1. "ADDRMAP_BG_B1,Selects the HIF address bits used as bank group address bit 1. Valid Range: 0 to 32 and 63 Internal Base: 3 The selected HIF address bit for each of the bank group address bits is determined by adding the internal base to the value of this.." newline rbitfld.long 0x8 6.--7. "RESERVED,Reserved" "0,1,2,3" newline hexmask.long.byte 0x8 0.--5. 1. "ADDRMAP_BG_B0,Selects the HIF address bits used as bank group address bit 0. Valid Range: 0 to 32 and 63 Internal Base: 2 The selected HIF address bit for each of the bank group address bits is determined by adding the internal base to the value of this.." group.long 0x22C++0x3 line.long 0x0 "ADDRMAP11,Address Map Register 11" hexmask.long 0x0 4.--31. 1. "RESERVED,Reserved" newline hexmask.long.byte 0x0 0.--3. 1. "ADDRMAP_ROW_B10,Selects the HIF address bits used as row address bit 10. Valid Range: 0 to 11 Internal Base: 16 The selected HIF address bit for each of the row address bits is determined by adding the internal base to the value of this field. This.." group.long 0x240++0x7 line.long 0x0 "ODTCFG,ODT Configuration Register" hexmask.long.byte 0x0 28.--31. 1. "RESERVED,Reserved" newline hexmask.long.byte 0x0 24.--27. 1. "WR_ODT_HOLD,DFI PHY clock cycles to hold ODT for a write command. The minimum supported value is 2. Recommended values: DDR2: - BL8 - 0x5 (DDR2-400/533/667) 0x6 (DDR2-800) 0x7 (DDR2-1066) - BL4 - 0x3 (DDR2-400/533/667) 0x4 (DDR2-800) 0x5 (DDR2-1066).." newline rbitfld.long 0x0 21.--23. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x0 16.--20. 1. "WR_ODT_DELAY,Indicates the delay in DFI PHY clock cycles from issuing a write command to setting ODT values associated with that command. ODT setting must remain constant for the entire time that DQS is driven by the uMCTL2. Recommended values: DDR2: -.." newline hexmask.long.byte 0x0 12.--15. 1. "RESERVED,Reserved" newline hexmask.long.byte 0x0 8.--11. 1. "RD_ODT_HOLD,DFI PHY clock cycles to hold ODT for a read command. The minimum supported value is 2. Recommended values: DDR2: - BL8 - 0x6 (not DDR2-1066) 0x7 (DDR2-1066) - BL4 - 0x4 (not DDR2-1066) 0x5 (DDR2-1066) DDR3: - BL8 - 0x6 DDR4: - BL8 - 5 +.." newline rbitfld.long 0x0 7. "RESERVED,Reserved" "0,1" newline hexmask.long.byte 0x0 2.--6. 1. "RD_ODT_DELAY,Indicates the delay in DFI PHY clock cycles from issuing a read command to setting ODT values associated with that command. ODT setting must remain constant for the entire time that DQS is driven by the uMCTL2. Recommended values: DDR2: -.." newline rbitfld.long 0x0 0.--1. "RESERVED,Reserved" "0,1,2,3" line.long 0x4 "ODTMAP,ODT/Rank Map Register" hexmask.long.tbyte 0x4 14.--31. 1. "RESERVED,Reserved" newline bitfld.long 0x4 12.--13. "RANK1_RD_ODT,Indicates which remote ODTs must be turned on during a read from rank 1. Each rank has a remote ODT (in the SDRAM) which can be turned on by setting the appropriate bit here. Rank 0 is controlled by the LSB; rank 1 is controlled by bit next.." "0,1,2,3" newline rbitfld.long 0x4 10.--11. "RESERVED,Reserved" "0,1,2,3" newline bitfld.long 0x4 8.--9. "RANK1_WR_ODT,Indicates which remote ODTs must be turned on during a write to rank 1. Each rank has a remote ODT (in the SDRAM) which can be turned on by setting the appropriate bit here. Rank 0 is controlled by the LSB; rank 1 is controlled by bit next.." "0,1,2,3" newline rbitfld.long 0x4 6.--7. "RESERVED,Reserved" "0,1,2,3" newline bitfld.long 0x4 4.--5. "RANK0_RD_ODT,Indicates which remote ODTs must be turned on during a read from rank 0. Each rank has a remote ODT (in the SDRAM) which can be turned on by setting the appropriate bit here. Rank 0 is controlled by the LSB; rank 1 is controlled by bit next.." "0,1,2,3" newline rbitfld.long 0x4 2.--3. "RESERVED,Reserved" "0,1,2,3" newline bitfld.long 0x4 0.--1. "RANK0_WR_ODT,Indicates which remote ODTs must be turned on during a write to rank 0. Each rank has a remote ODT (in the SDRAM) which can be turned on by setting the appropriate bit here. Rank 0 is controlled by the LSB; rank 1 is controlled by bit next.." "0,1,2,3" group.long 0x250++0x7 line.long 0x0 "SCHED,Scheduler Control Register" rbitfld.long 0x0 31. "RESERVED,Reserved" "0,1" newline hexmask.long.byte 0x0 24.--30. 1. "RDWR_IDLE_GAP,When the preferred transaction store is empty for these many clock cycles switch to the alternate transaction store if it is non-empty. The read transaction store (both high and low priority) is the default preferred transaction store and.." newline hexmask.long.byte 0x0 16.--23. 1. "GO2CRITICAL_HYSTERESIS,UNUSED. Programming Mode: Static" newline bitfld.long 0x0 15. "LPDDR4_OPT_ACT_TIMING,Optimized ACT timing control for LPDDR4. In LPDDR4 RD/WR/ACT takes 4 cycle. To stream Read/Write there are only 4 cycle space between Reads/Writes. If ACT is scheduled-out after RD/WR with 1 2 or 3 cycle gap next RD/WR may be.." "Disable this feature,Enable this feature" newline rbitfld.long 0x0 13.--14. "RESERVED,Reserved" "0,1,2,3" newline hexmask.long.byte 0x0 8.--12. 1. "LPR_NUM_ENTRIES,Number of entries in the low priority transaction store is this value + 1. (MEMC_NO_OF_ENTRY - (SCHED.lpr_num_entries + 1)) is the number of entries available for the high priority transaction store. Setting this to maximum value.." newline bitfld.long 0x0 7. "AUTOPRE_RMW,Selects behavior of hif_cmd_autopre if a RMW is received on HIF with hif_cmd_autopre=1 - 1 - Apply Autopre only for write part of RMW - 0 - Apply Autopre for both read and write parts of RMW Programming Mode: Static" "Apply Autopre for both read and write parts of RMW,Apply Autopre only for write part of RMW" newline hexmask.long.byte 0x0 3.--6. 1. "RESERVED,Reserved" newline bitfld.long 0x0 2. "PAGECLOSE,If true bank is kept open only while there are page hit transactions available in the CAM to that bank. The last read or write command in the CAM with a bank and page hit is executed with auto-precharge if SCHED1.pageclose_timer=0. Even if.." "0,1" newline bitfld.long 0x0 1. "PREFER_WRITE,If set then the bank selector prefers writes over reads. FOR DEBUG ONLY. Programming Mode: Static" "0,1" newline rbitfld.long 0x0 0. "RESERVED,Reserved" "0,1" line.long 0x4 "SCHED1,Scheduler Control Register 1" hexmask.long.tbyte 0x4 8.--31. 1. "RESERVED,Reserved" newline hexmask.long.byte 0x4 0.--7. 1. "PAGECLOSE_TIMER,This field works in conjunction with SCHED.pageclose.It only has meaning if SCHED.pageclose==1. If SCHED.pageclose==1 and pageclose_timer==0 then an auto-precharge may be scheduled for last read or write command in the CAM with a bank.." group.long 0x25C++0x3 line.long 0x0 "PERFHPR1,High Priority Read CAM Register 1" hexmask.long.byte 0x0 24.--31. 1. "HPR_XACT_RUN_LENGTH,Indicates the number of transactions that are serviced once the HPR queue goes critical is the smaller of: - (a) This number - (b) Number of transactions available Unit: Transaction. FOR PERFORMANCE ONLY. Programming Mode:.." newline hexmask.long.byte 0x0 16.--23. 1. "RESERVED,Reserved" newline hexmask.long.word 0x0 0.--15. 1. "HPR_MAX_STARVE,Indicates the number of DFI clocks that the HPR queue can be starved before it goes critical. The minimum valid functional value for this register is 0x1. Programming it to 0x0 disables the starvation functionality. During normal operation.." group.long 0x264++0x3 line.long 0x0 "PERFLPR1,Low Priority Read CAM Register 1" hexmask.long.byte 0x0 24.--31. 1. "LPR_XACT_RUN_LENGTH,Indicates the number of transactions that are serviced once the LPR queue goes critical is the smaller of: - (a) This number - (b) Number of transactions available Unit: Transaction. FOR PERFORMANCE ONLY. Programming Mode:.." newline hexmask.long.byte 0x0 16.--23. 1. "RESERVED,Reserved" newline hexmask.long.word 0x0 0.--15. 1. "LPR_MAX_STARVE,Indicates the number of DFI clocks that the LPR queue can be starved before it goes critical. The minimum valid functional value for this register is 0x1. Programming it to 0x0 disables the starvation functionality. During normal operation.." group.long 0x26C++0x3 line.long 0x0 "PERFWR1,Write CAM Register 1" hexmask.long.byte 0x0 24.--31. 1. "W_XACT_RUN_LENGTH,Indicates the number of transactions that are serviced once the WR queue goes critical is the smaller of: - (a) This number - (b) Number of transactions available Unit: Transaction. FOR PERFORMANCE ONLY. Programming Mode: Quasi-dynamic.." newline hexmask.long.byte 0x0 16.--23. 1. "RESERVED,Reserved" newline hexmask.long.word 0x0 0.--15. 1. "W_MAX_STARVE,Indicates the number of DFI clocks that the WR queue can be starved before it goes critical. The minimum valid functional value for this register is 0x1. Programming it to 0x0 disables the starvation functionality. During normal operation.." group.long 0x300++0x7 line.long 0x0 "DBG0,Debug Register 0" hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED,Reserved" newline bitfld.long 0x0 7. "DIS_MAX_RANK_WR_OPT,Indicates the disable optimized max_rank_wr and max_logical_rank_wr feature. This register is for debug purpose only. For normal operation This register must be set to 0. Programming Mode: Static" "0,1" newline bitfld.long 0x0 6. "DIS_MAX_RANK_RD_OPT,Indicates the disable optimized max_rank_rd and max_logical_rank_rd feature. This register is for debug purpose only. For normal operation This register must be set to 0. Programming Mode: Static" "0,1" newline rbitfld.long 0x0 5. "RESERVED,Reserved" "0,1" newline bitfld.long 0x0 4. "DIS_COLLISION_PAGE_OPT,When this is set to '0' auto-precharge is disabled for the flushed command in a collision case. Collision cases are write followed by read to same address read followed by write to same address or write followed by write to same.." "0,1" newline rbitfld.long 0x0 1.--3. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 0. "DIS_WC,When 1 disable write combine. FOR DEBUG ONLY. Programming Mode: Static" "0,1" line.long 0x4 "DBG1,Debug Register 1" hexmask.long 0x4 2.--31. 1. "RESERVED,Reserved" newline bitfld.long 0x4 1. "DIS_HIF,When 1 uMCTL2 asserts the HIF command signal hif_cmd_stall. uMCTL2 ignores the hif_cmd_valid and all other associated request signals. This bit is intended to be switched on-the-fly. Programming Mode: Dynamic" "0,1" newline bitfld.long 0x4 0. "DIS_DQ,When 1 uMCTL2 does not de-queue any transactions from the CAM. Bypass is also disabled. All transactions are queued in the CAM. No reads or writes are issued to SDRAM as long as this is asserted. This bit may be used to prevent reads or writes.." "0,1" rgroup.long 0x308++0x3 line.long 0x0 "DBGCAM,CAM Debug Register" bitfld.long 0x0 30.--31. "RESERVED,Reserved" "0,1,2,3" newline bitfld.long 0x0 29. "WR_DATA_PIPELINE_EMPTY,This bit indicates that the write data pipeline on the DFI interface is empty. This register is intended to be polled at least twice after setting DBG1.dis_dq to ensure that all remaining commands/data have completed. Programming.." "0,1" newline bitfld.long 0x0 28. "RD_DATA_PIPELINE_EMPTY,This bit indicates that the read data pipeline on the DFI interface is empty. This register is intended to be polled at least twice after setting DBG1.dis_dq to ensure that all remaining commands/data have completed. Programming.." "0,1" newline bitfld.long 0x0 27. "RESERVED,Reserved" "0,1" newline bitfld.long 0x0 26. "DBG_WR_Q_EMPTY,When 1 all the Write command queues and Write data buffers inside DDRC are empty. This register is to be used for debug purpose. An example use-case scenario: When the controller enters self-refresh using the Low-Power entry sequence.." "0,1" newline bitfld.long 0x0 25. "DBG_RD_Q_EMPTY,When 1 all the Read command queues and Read data buffers inside DDRC are empty. This register is to be used for debug purpose. An example use-case scenario: When the controller enters self-refresh using the Low-Power entry sequence.." "0,1" newline bitfld.long 0x0 24. "DBG_STALL,Stall. FOR DEBUG ONLY. Programming Mode: Dynamic" "0,1" newline bitfld.long 0x0 22.--23. "RESERVED,Reserved" "0,1,2,3" newline hexmask.long.byte 0x0 16.--21. 1. "DBG_W_Q_DEPTH,This field indicates the Write queue depth. The last entry of WR queue is reserved for ECC SCRUB operation. This entry is not included in the calculation of the queue depth. FOR DEBUG ONLY Programming Mode: Dynamic" newline bitfld.long 0x0 14.--15. "RESERVED,Reserved" "0,1,2,3" newline hexmask.long.byte 0x0 8.--13. 1. "DBG_LPR_Q_DEPTH,This field indicates the low priority read queue depth. The last entry of Lpr queue is reserved for ECC SCRUB operation. This entry is not included in the calculation of the queue depth. FOR DEBUG ONLY Programming Mode: Dynamic" newline bitfld.long 0x0 6.--7. "RESERVED,Reserved" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "DBG_HPR_Q_DEPTH,This field indicates the high priority read queue depth. FOR DEBUG ONLY. Programming Mode: Dynamic" group.long 0x30C++0x3 line.long 0x0 "DBGCMD,Command Debug Register" hexmask.long 0x0 6.--31. 1. "RESERVED,Reserved" newline bitfld.long 0x0 5. "CTRLUPD,Setting this register bit to 1 indicates to the uMCTL2 to issue a dfi_ctrlupd_req to the PHY. When this request is stored in the uMCTL2 the bit is automatically cleared. This operation must only be performed when DFIUPD0.dis_auto_ctrlupd=1." "0,1" newline bitfld.long 0x0 4. "ZQ_CALIB_SHORT,Setting this register bit to 1 indicates to the uMCTL2 to issue a ZQCS (ZQ calibration short)/MPC(ZQ calibration) command to the SDRAM. When this request is stored in the uMCTL2 the bit is automatically cleared. This operation can be.." "0,1" newline rbitfld.long 0x0 2.--3. "RESERVED,Reserved" "0,1,2,3" newline bitfld.long 0x0 1. "RANK1_REFRESH,Setting this register bit to 1 indicates to the uMCTL2 to issue a refresh to rank 1. Writing to this bit causes DBGSTAT.rank1_refresh_busy to be set. When DBGSTAT.rank1_refresh_busy is cleared the command has been stored in uMCTL2. For 3DS.." "0,1" newline bitfld.long 0x0 0. "RANK0_REFRESH,Setting this register bit to 1 indicates to the uMCTL2 to issue a refresh to rank 0. Writing to this bit causes DBGSTAT.rank0_refresh_busy to be set. When DBGSTAT.rank0_refresh_busy is cleared the command has been stored in uMCTL2. For 3DS.." "0,1" rgroup.long 0x310++0x3 line.long 0x0 "DBGSTAT,Status Debug Register" hexmask.long 0x0 6.--31. 1. "RESERVED,Reserved" newline bitfld.long 0x0 5. "CTRLUPD_BUSY,SoC might initiate a ctrlupd operation only if this signal is low. This signal goes high in the clock after the uMCTL2 accepts the ctrlupd request. It goes low when the ctrlupd operation is initiated in the uMCTL2. It is recommended not to.." "Indicates that the SoC can initiate a ctrlupd..,Indicates that ctrlupd operation has not been.." newline bitfld.long 0x0 4. "ZQ_CALIB_SHORT_BUSY,SoC might initiate a ZQCS (ZQ calibration short) operation only if this signal is low. This signal goes high in the clock after the uMCTL2 accepts the ZQCS request. It goes low when the ZQCS operation is initiated in the uMCTL2. It is.." "Indicates that the SoC can initiate a ZQCS..,Indicates that ZQCS operation has not been.." newline bitfld.long 0x0 2.--3. "RESERVED,Reserved" "0,1,2,3" newline bitfld.long 0x0 1. "RANK1_REFRESH_BUSY,SoC might initiate a rank1_refresh operation (refresh operation to rank 1) only if this signal is low. This signal goes high in the clock after DBGCMD.rank1_refresh is set to one. It goes low when the rank1_refresh operation is stored.." "Indicates that the SoC can initiate a..,Indicates that rank1_refresh operation has not.." newline bitfld.long 0x0 0. "RANK0_REFRESH_BUSY,SoC might initiate a rank0_refresh operation (refresh operation to rank 0) only if this signal is low. This signal goes high in the clock after DBGCMD.rank0_refresh is set to one. It goes low when the rank0_refresh operation is stored.." "Indicates that the SoC can initiate a..,Indicates that rank0_refresh operation has not.." rgroup.long 0x318++0x3 line.long 0x0 "DBGCAM1,CAM Debug Register 1" hexmask.long 0x0 6.--31. 1. "RESERVED,Reserved" newline hexmask.long.byte 0x0 0.--5. 1. "DBG_WRECC_Q_DEPTH,This field indicates the write ECC queue depth. FOR DEBUG ONLY. Programming Mode: Dynamic" group.long 0x320++0x3 line.long 0x0 "SWCTL,Software Register Programming Control Enable" hexmask.long 0x0 1.--31. 1. "RESERVED,Reserved" newline bitfld.long 0x0 0. "SW_DONE,Enables quasi-dynamic register programming outside reset. Program this register to 0 to enable quasi-dynamic programming. Set back register to 1 once programming is done. Programming Mode: Dynamic" "0,1" rgroup.long 0x324++0x3 line.long 0x0 "SWSTAT,Software Register Programming Control Status" hexmask.long 0x0 1.--31. 1. "RESERVED,Reserved" newline bitfld.long 0x0 0. "SW_DONE_ACK,Register programming done. This register is the echo of SWCTL.sw_done. Wait for sw_done value 1 to propagate to sw_done_ack at the end of the programming sequence to ensure that the correct registers values are propagated to the destination.." "0,1" group.long 0x328++0x3 line.long 0x0 "SWCTLSTATIC,Static Registers Write Enable" hexmask.long 0x0 1.--31. 1. "RESERVED,Reserved" newline bitfld.long 0x0 0. "SW_STATIC_UNLOCK,Enables static register programming outside reset. Program this register to 1 to enable static register programming. Set register back to 0 once programming is done. Programming Mode: Dynamic" "0,1" group.long 0x330++0x7 line.long 0x0 "OCPARCFG0,On-Chip Parity Configuration Register 0" hexmask.long.byte 0x0 27.--31. 1. "RESERVED,Reserved" newline bitfld.long 0x0 26. "PAR_RADDR_ERR_INTR_FORCE,Interrupt force bit for all par_raddr_err_intr. uMCTL2 automatically clears this bit. Programming Mode: Dynamic" "0,1" newline bitfld.long 0x0 25. "PAR_WADDR_ERR_INTR_FORCE,Interrupt force bit for all par_waddr_err_intr. uMCTL2 automatically clears this bit. Programming Mode: Dynamic" "0,1" newline bitfld.long 0x0 24. "PAR_RADDR_ERR_INTR_CLR,Interrupt clear bit for all par_raddr_err_intr. uMCTL2 automatically clears this bit. Programming Mode: Dynamic" "0,1" newline bitfld.long 0x0 23. "PAR_RADDR_ERR_INTR_EN,Enables interrupt generation if set to 1 for all ports on signal par_raddr_err_intr_n upon detection of parity error on the AXI interface. Programming Mode: Dynamic" "0,1" newline bitfld.long 0x0 22. "PAR_WADDR_ERR_INTR_CLR,Interrupt clear bit for all par_waddr_err_intr. uMCTL2 automatically clears this bit. Programming Mode: Dynamic" "0,1" newline bitfld.long 0x0 21. "PAR_WADDR_ERR_INTR_EN,Enables interrupt generation if set to 1 for all ports on signal par_waddr_err_intr_n upon detection of parity error on the AXI interface. Programming Mode: Dynamic" "0,1" newline bitfld.long 0x0 20. "PAR_ADDR_SLVERR_EN,Enables SLVERR generation on read response or write response when address parity error is detected at the AXI interface. Programming Mode: Quasi-dynamic Group 3" "0,1" newline hexmask.long.byte 0x0 16.--19. 1. "RESERVED,Reserved" newline bitfld.long 0x0 15. "PAR_RDATA_ERR_INTR_FORCE,Interrupt force bit for all par_rdata_err_intr_n and par_rdata_in_err_ecc_intr (Inline-ECC only). uMCTL2 automatically clears this bit. Programming Mode: Dynamic" "0,1" newline bitfld.long 0x0 14. "PAR_RDATA_ERR_INTR_CLR,Interrupt clear bit for par_rdata_err_intr. uMCTL2 automatically clears this bit. Programming Mode: Dynamic" "0,1" newline bitfld.long 0x0 13. "PAR_RDATA_ERR_INTR_EN,Enables interrupt generation if set to 1 for all ports on signal par_rdata_err_intr_n upon detection of parity error at the AXI interface. Programming Mode: Dynamic" "0,1" newline bitfld.long 0x0 12. "PAR_RDATA_SLVERR_EN,Enables SLVERR generation on read response when read data parity error is detected at the AXI interface. Programming Mode: Quasi-dynamic Group 3" "0,1" newline hexmask.long.byte 0x0 8.--11. 1. "RESERVED,Reserved" newline bitfld.long 0x0 7. "PAR_WDATA_ERR_INTR_FORCE,Interrupt force bit for par_wdata_err_intr. uMCTL2 automatically clears this bit. Programming Mode: Dynamic" "0,1" newline bitfld.long 0x0 6. "PAR_WDATA_ERR_INTR_CLR,Interrupt clear bit for par_wdata_err_intr. uMCTL2 automatically clears this bit. Programming Mode: Dynamic" "0,1" newline bitfld.long 0x0 5. "PAR_WDATA_SLVERR_EN,Enables SLVERR generation on write response when write data parity error is detected at the AXI interface. Programming Mode: Quasi-dynamic Group 3" "0,1" newline bitfld.long 0x0 4. "PAR_WDATA_ERR_INTR_EN,Enables write data interrupt generation (par_wdata_err_intr) upon detection of parity error at the AXI or DFI interface. Programming Mode: Dynamic" "0,1" newline rbitfld.long 0x0 2.--3. "RESERVED,Reserved" "0,1,2,3" newline bitfld.long 0x0 1. "OC_PARITY_TYPE,Parity type: - 0 - Even parity - 1 - Odd parity Programming Mode: Quasi-dynamic Group 3" "Even parity,Odd parity" newline bitfld.long 0x0 0. "OC_PARITY_EN,Parity enable register. Enables On-Chip parity for all interfaces. Programming Mode: Quasi-dynamic Group 3" "0,1" line.long 0x4 "OCPARCFG1,On-Chip Parity Configuration Register 1" hexmask.long.tbyte 0x4 12.--31. 1. "RESERVED,Reserved" newline hexmask.long.byte 0x4 8.--11. 1. "PAR_POISON_LOC_WR_PORT,Enables parity poisoning on write data at the AXI interface before the input parity check logic. The value specifies the binary encoded port number of the AXI interface to be injected with parity error. Programming Mode:.." newline hexmask.long.byte 0x4 4.--7. 1. "PAR_POISON_LOC_RD_PORT,Enables parity poisoning on read data at the AXI interface after the parity check logic. The value specifies the binary encoded port number of the AXI interface to be injected with parity error. Error can be injected to one port at.." newline bitfld.long 0x4 3. "PAR_POISON_LOC_RD_IECC_TYPE,Selects which parity to poison at the DFI when inline ECC is enabled. If this register is set to 0 parity error is injected on the first read data going through the ECC path. If this register is set to 1 parity error is.." "0,1" newline bitfld.long 0x4 2. "PAR_POISON_LOC_RD_DFI,Enables parity poisoning on read data at the DFI interface after the parity generation logic. When MEMC_INLINE_ECC=1 enables poisoning of ECC word after the ECC encoder at the write data interface at the DFI. Programming Mode:.." "0,1" newline rbitfld.long 0x4 1. "RESERVED,Reserved" "0,1" newline bitfld.long 0x4 0. "PAR_POISON_EN,Enables on-chip parity poisoning on the data interfaces. Programming Mode: Quasi-dynamic Group 3" "0,1" repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) rgroup.long ($2+0x338)++0x3 line.long 0x0 "OCPARSTAT$1,On-Chip Parity Status Register 0" hexmask.long.word 0x0 17.--31. 1. "RESERVED,Reserved" newline bitfld.long 0x0 16. "PAR_RADDR_ERR_INTR_0,Read address parity error interrupt for port 0. This interrupt is asserted when an on-chip read address parity error occurred on the corresponding AXI port's read address channel. Programming Mode: Static" "0,1" newline hexmask.long.word 0x0 1.--15. 1. "RESERVED,Reserved" newline bitfld.long 0x0 0. "PAR_WADDR_ERR_INTR_0,Write address parity error interrupt for port 0. This interrupt is asserted when an on-chip write address parity error occurred on the corresponding AXI port's write address channel. Programming Mode: Static" "0,1" repeat.end rgroup.long 0x340++0x3 line.long 0x0 "OCPARSTAT2,On-Chip Parity Status Register 2" hexmask.long 0x0 5.--31. 1. "RESERVED,Reserved" newline bitfld.long 0x0 4. "PAR_RDATA_IN_ERR_ECC_INTR,Interrupt on ECC data going into inline ECC decoder. Cleared by par_rdata_err_intr_clr. Programming Mode: Static" "0,1" newline bitfld.long 0x0 2.--3. "RESERVED,Reserved" "0,1,2,3" newline bitfld.long 0x0 0.--1. "PAR_WDATA_OUT_ERR_INTR,Write data parity error interrupt on output. Cleared by register par_wdata_err_intr_clr. Programming Mode: Static" "0,1,2,3" group.long 0x36C++0x3 line.long 0x0 "POISONCFG,AXI Poison Configuration Register. Common for all AXI ports." hexmask.long.byte 0x0 25.--31. 1. "RESERVED,Reserved" newline bitfld.long 0x0 24. "RD_POISON_INTR_CLR,Interrupt clear for read transaction poisoning. Allow 2/3 clock cycles for correct value to propagate to controller logic and clear the interrupts. uMCTL2 automatically clears this bit. Programming Mode: Dynamic" "0,1" newline rbitfld.long 0x0 21.--23. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 20. "RD_POISON_INTR_EN,If set to 1 enables interrupts for read transaction poisoning. Programming Mode: Dynamic" "0,1" newline rbitfld.long 0x0 17.--19. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 16. "RD_POISON_SLVERR_EN,If set to 1 enables SLVERR response for read transaction poisoning. Programming Mode: Dynamic" "0,1" newline hexmask.long.byte 0x0 9.--15. 1. "RESERVED,Reserved" newline bitfld.long 0x0 8. "WR_POISON_INTR_CLR,Interrupt clear for write transaction poisoning. Allow 2/3 clock cycles for correct value to propagate to controller logic and clear the interrupts. uMCTL2 automatically clears this bit. Programming Mode: Dynamic" "0,1" newline rbitfld.long 0x0 5.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 4. "WR_POISON_INTR_EN,If set to 1 enables interrupts for write transaction poisoning. Programming Mode: Dynamic" "0,1" newline rbitfld.long 0x0 1.--3. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 0. "WR_POISON_SLVERR_EN,If set to 1 enables SLVERR response for write transaction poisoning. Programming Mode: Dynamic" "0,1" rgroup.long 0x370++0x3 line.long 0x0 "POISONSTAT,AXI Poison Status Register" hexmask.long.word 0x0 17.--31. 1. "RESERVED,Reserved" newline bitfld.long 0x0 16. "RD_POISON_INTR_0,Read transaction poisoning error interrupt for port 0. This register is a APB clock copy (double register synchronizer) of the interrupt asserted when a transaction is poisoned on the corresponding AXI port's read address channel. Bit 0.." "0,1" newline hexmask.long.word 0x0 1.--15. 1. "RESERVED,Reserved" newline bitfld.long 0x0 0. "WR_POISON_INTR_0,Write transaction poisoning error interrupt for port 0. This register is a APB clock copy (double register synchronizer) of the interrupt asserted when a transaction is poisoned on the corresponding AXI port's write address channel. Bit.." "0,1" group.long 0x374++0x3 line.long 0x0 "ADVECCINDEX,Advanced ECC Index Register" hexmask.long.tbyte 0x0 9.--31. 1. "RESERVED,Reserved" newline hexmask.long.byte 0x0 5.--8. 1. "ECC_POISON_BEATS_SEL,Selector of which DRAM beat's poison pattern is set by ECCPOISONPAT0/1/2 registers. For frequency ratio 1:1 mode 2 DRAM beats can be poisoned. Set ecc_poison_beats_sel to 0 and given ECCPOISONPAT0/1/2 to set 1st beat's poison.." newline bitfld.long 0x0 3.--4. "ECC_ERR_SYMBOL_SEL,Selector of which error symbol's status output to ADVECCSTAT.advecc_err_symbol_pos and advecc_err_symbol_bits. The default is first error symbol. The value must be less than ADVECCSTAT.advecc_num_err_symbol. Programming Mode:.." "0,1,2,3" newline bitfld.long 0x0 0.--2. "ECC_SYNDROME_SEL,Selector of which DRAM beat data output to ECCCSYN0/1/2 as well as ECCUCSYN. In Advanced ECC the syndrome consists of number of DRAM beats. This register selects which beats of data is output to ECCCSYN0/1/2 and ECCUCSYN0/1/2 registers." "0,1,2,3,4,5,6,7" group.long 0x37C++0x3 line.long 0x0 "ECCPOISONPAT0,ECC Poison Pattern 0 Register" hexmask.long 0x0 0.--31. 1. "ECC_POISON_DATA_31_0,Indicates the poison pattern for DRAM data[31:0]. setting this bit to 1 indicates poison (invert) corresponding DRAM bit. It is indirect register. Selector is ADVECCINDEX.ecc_poison_beats_sel. Programming Mode: Quasi-dynamic Group 3" group.long 0x384++0x3 line.long 0x0 "ECCPOISONPAT2,ECC Poison Pattern 2 Register" hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED,Reserved" newline hexmask.long.byte 0x0 0.--7. 1. "ECC_POISON_DATA_71_64,Indicates the poison pattern for DRAM data[71:64]. Setting this bit to 1 indicates poison (invert) corresponding DRAM bit. It is indirect register. Selector is ADVECCINDEX.ecc_poison_beats_sel. Programming Mode: Quasi-dynamic Group 3" rgroup.long 0x388++0x3 line.long 0x0 "ECCAPSTAT,Address protection within ECC Status Register" hexmask.long 0x0 1.--31. 1. "RESERVED,Reserved" newline bitfld.long 0x0 0. "ECC_AP_ERR,Indicates the number of ECC errors (correctable/uncorrectable) within one burst exceeded the threshold(ECCCFG0.ecc_ap_err_threshold). Programming Mode: Dynamic" "0,1" group.long 0x3C0++0x3 line.long 0x0 "REGPARCFG,Register Parity Configuration Register (Note that all fields must be programmed with single write operation)." hexmask.long.tbyte 0x0 9.--31. 1. "RESERVED,Reserved" newline bitfld.long 0x0 8. "REG_PAR_POISON_EN,Enable Register Parity poisoning. Programming Mode: Dynamic" "0,1" newline hexmask.long.byte 0x0 4.--7. 1. "RESERVED,Reserved" newline bitfld.long 0x0 3. "REG_PAR_ERR_INTR_FORCE,Interrupt force bit for reg_par_err_intr setting this register causes the output interrupt to be asserted. uMCTL2 automatically clears this bit. There is no interaction between functionally triggering an interrupt and forcing an.." "0,1" newline bitfld.long 0x0 2. "REG_PAR_ERR_INTR_CLR,Interupt clear bit for reg_par_err_intr. uMCTL2 automatically clears this bit. Programming Mode: Dynamic" "0,1" newline bitfld.long 0x0 1. "REG_PAR_ERR_INTR_EN,Enables interrupt generation if set to 1 on signal reg_par_err_intr upon detection of register parity error. Programming Mode: Dynamic" "0,1" newline bitfld.long 0x0 0. "REG_PAR_EN,Register Parity enable register. Programming Mode: Dynamic" "0,1" rgroup.long 0x3C4++0x3 line.long 0x0 "REGPARSTAT,Register Parity Status Register" hexmask.long 0x0 1.--31. 1. "RESERVED,Reserved" newline bitfld.long 0x0 0. "REG_PAR_ERR_INTR,Interrupt asserted when Register Parity error is detected. Cleared by setting REGPARCFG.reg_par_err_intr_clr to 1. Programming Mode: Static" "0,1" group.long 0x3E0++0x3 line.long 0x0 "OCCAPCFG,On-Chip command/Address Protection Configuration Register" hexmask.long.byte 0x0 28.--31. 1. "RESERVED,Reserved" newline bitfld.long 0x0 27. "OCCAP_ARB_RAQ_POISON_EN,Enables poisoning for the Read Address Queues (RAQ) inside each XPI. Poisoning inverts all parity bits generated by the parity generator. Error is flagged as soon as the first RAQ is read. This register is not cleared.." "0,1" newline bitfld.long 0x0 26. "OCCAP_ARB_CMP_POISON_ERR_INJ,Enables error injection in the poisoning of OCCAP Arbiter logic. Injects error into poisoning logic (either parallel or seq) such that XOR logic for one signal is not poisoned when expected. If set it allows ability to.." "OCCAPSTAT,OCCAPSTAT" newline bitfld.long 0x0 25. "OCCAP_ARB_CMP_POISON_PARALLEL,Enables full poisoning for compare logic inside XPI. Poisoning inverts all bits of all outputs coming from the duplicated modules before the XOR comparators together. uMCTL2 automatically clears this bit. Programming Mode:.." "0,1" newline bitfld.long 0x0 24. "OCCAP_ARB_CMP_POISON_SEQ,Enables poisoning for compare logic inside XPI. Poisoning inverts all bits coming from the duplicated modules before the XOR comparators one output at the time per each comparator. uMCTL2 automatically clears this bit." "0,1" newline hexmask.long.byte 0x0 19.--23. 1. "RESERVED,Reserved" newline bitfld.long 0x0 18. "OCCAP_ARB_INTR_FORCE,Interrupt force bit for occap_arb_err_intr setting this register causes the output interrupt to be asserted. uMCTL2 automatically clears this bit. There is no interaction between functionally triggering an interrupt and forcing an.." "0,1" newline bitfld.long 0x0 17. "OCCAP_ARB_INTR_CLR,Interrupt clear bit for occap_arb_err_intr and occap_arb_cmp_poison_complete. uMCTL2 automatically clears this bit. Programming Mode: Dynamic" "0,1" newline bitfld.long 0x0 16. "OCCAP_ARB_INTR_EN,Enables interrupt generation upon detection of OCCAP Arbiter errors. Programming Mode: Dynamic" "0,1" newline hexmask.long.word 0x0 1.--15. 1. "RESERVED,Reserved" newline bitfld.long 0x0 0. "OCCAP_EN,On Chip Command/Address Path Protection (OCCAP) enable register. Programming Mode: Quasi-dynamic Group 3" "0,1" rgroup.long 0x3E4++0x3 line.long 0x0 "OCCAPSTAT,On-Chip command/Address Protection Status Register" hexmask.long.byte 0x0 26.--31. 1. "RESERVED,Reserved" newline bitfld.long 0x0 25. "OCCAP_ARB_CMP_POISON_PARALLEL_ERR,Error when occap_arb_cmp_poison_full_en is active due to incorrect number of errors being occurring. Internal logic checks the number of errors detected while poisoning occurred for occap_arb_cmp_poison_full_en. It.." "0,1" newline bitfld.long 0x0 24. "OCCAP_ARB_CMP_POISON_SEQ_ERR,Error when occap_arb_cmp_poison_en is active due to incorrect number of errors being occurring. Internal logic checks that the correct number of errors detected while poisoning one output at the time occurred for.." "0,1" newline hexmask.long.byte 0x0 18.--23. 1. "RESERVED,Reserved" newline bitfld.long 0x0 17. "OCCAP_ARB_CMP_POISON_COMPLETE,OCCAP ARB comparator poisoning complete interrupt status. Register cleared by OCCAPCFG.occap_arb_intr_clr. Programming Mode: Static" "0,1" newline bitfld.long 0x0 16. "OCCAP_ARB_ERR_INTR,OCCAP Arbiter error interrupt status. Register cleared by OCCAPCFG.occap_arb_intr_clr. Programming Mode: Static" "0,1" newline hexmask.long.word 0x0 0.--15. 1. "RESERVED,Reserved" group.long 0x3E8++0x3 line.long 0x0 "OCCAPCFG1,On-Chip command/Address Protection Configuration Register 1" hexmask.long.byte 0x0 27.--31. 1. "RESERVED,Reserved" newline bitfld.long 0x0 26. "OCCAP_DDRC_CTRL_POISON_ERR_INJ,Enables error injection in the poisoning of OCCAP DDRC CTRL logic. Injects error into poisoning logic (either parallel or seq) such that XOR logic for one signal is not poisoned when expected. If set it allows ability to.." "OCCAPSTAT1,OCCAPSTAT1" newline bitfld.long 0x0 25. "OCCAP_DDRC_CTRL_POISON_PARALLEL,Enables poisoning of OCCAP DDRC CTRL logic for all parts of comparison logic in parallel. Poisons comparison logic for one core_ddrc_core_clk cycle by inverting a ddrc_ctrl[0]'s signal to XOR logic. ddrc_ctrl[1] related.." "0,1" newline bitfld.long 0x0 24. "OCCAP_DDRC_CTRL_POISON_SEQ,Enables poisoning of OCCAP DDRC CTRL logic for all parts of comparison logic in sequence. Poisons comparison logic for one core_ddrc_core_clk cycle by inverting a ddrc_ctrl[0]'s signal to XOR logic. ddrc_ctrl[1] related.." "0,1" newline hexmask.long.byte 0x0 19.--23. 1. "RESERVED,Reserved" newline bitfld.long 0x0 18. "OCCAP_DDRC_CTRL_INTR_FORCE,Interrupt force bit for occap_ddrc_ctrl_err_intr setting this register causes the output interrupt to be asserted. uMCTL2 automatically clears this bit. There is no interaction between functionally triggering an interrupt and.." "0,1" newline bitfld.long 0x0 17. "OCCAP_DDRC_CTRL_INTR_CLR,Interrupt clear bit for occap_ddrc_ctrl_err_intr. uMCTL2 automatically clears this bit. Programming Mode: Dynamic" "0,1" newline bitfld.long 0x0 16. "OCCAP_DDRC_CTRL_INTR_EN,Enables interrupt generation on signal occap_ddrc_ctrl_err_intr upon detection of OCCAP DDRC CTRL errors. Programming Mode: Dynamic" "0,1" newline hexmask.long.byte 0x0 11.--15. 1. "RESERVED,Reserved" newline bitfld.long 0x0 10. "OCCAP_DDRC_DATA_POISON_ERR_INJ,Enables error injection in the poisoning of OCCAP DDRC DATA logic. Injects error into poisoning logic (either parallel or seq) such that XOR logic for one signal is not poisoned when expected. If set it allows ability to.." "OCCAPSTAT1,OCCAPSTAT1" newline bitfld.long 0x0 9. "OCCAP_DDRC_DATA_POISON_PARALLEL,Enables poisoning of OCCAP DDRC DATA logic for all parts of comparison logic in parallel. Poisons comparison logic for one core_ddrc_core_clk cycle by inverting all bits of a signal to XOR logic. All signals of.." "0,1" newline bitfld.long 0x0 8. "OCCAP_DDRC_DATA_POISON_SEQ,Enables poisoning of OCCAP DDRC DATA logic for all parts of comparison logic in sequence. Poisons comparison logic for one core_ddrc_core_clk cycle by inverting all bits of a signal to XOR logic. All signals of instance[0] of.." "0,1" newline hexmask.long.byte 0x0 3.--7. 1. "RESERVED,Reserved" newline bitfld.long 0x0 2. "OCCAP_DDRC_DATA_INTR_FORCE,Interrupt force bit for occap_ddrc_data_err_intr setting this register causes the output interrupt to be asserted. uMCTL2 automatically clears this bit. There is no interaction between functionally triggering an interrupt and.." "0,1" newline bitfld.long 0x0 1. "OCCAP_DDRC_DATA_INTR_CLR,Interrupt clear bit for occap_ddrc_data_err_intr. uMCTL2 automatically clears this bit. Programming Mode: Dynamic" "0,1" newline bitfld.long 0x0 0. "OCCAP_DDRC_DATA_INTR_EN,Enables interrupt generation on signal occap_ddrc_data_err_intr upon detection of OCCAP DDRC DATA errors. Programming Mode: Dynamic" "0,1" rgroup.long 0x3EC++0x7 line.long 0x0 "OCCAPSTAT1,On-Chip command/Address Protection Status Register 1" hexmask.long.byte 0x0 26.--31. 1. "RESERVED,Reserved" newline bitfld.long 0x0 25. "OCCAP_DDRC_CTRL_POISON_PARALLEL_ERR,Error when occap_ddrc_ctrl_poison_parallel is active due to incorrect number of errors being occurring. Internal logic checks the number of errors detected while poisoning occurred for occap_ddrc_ctrl_poison_parallel." "0,1" newline bitfld.long 0x0 24. "OCCAP_DDRC_CTRL_POISON_SEQ_ERR,Error when occap_ddrc_ctrl_poison_seq is active due to incorrect number of errors being occurring. Internal logic checks the number of errors detected while poisoning occurred for occap_ddrc_ctrl_poison_seq. It checks for.." "0,1" newline hexmask.long.byte 0x0 18.--23. 1. "RESERVED,Reserved" newline bitfld.long 0x0 17. "OCCAP_DDRC_CTRL_POISON_COMPLETE,Indicates the OCCAP DDRC CTRL poisoning complete interrupt status. Register cleared by OCCAPCFG1.occap_ddrc_ctrl_err_intr_clr. Programming Mode: Static" "0,1" newline bitfld.long 0x0 16. "OCCAP_DDRC_CTRL_ERR_INTR,Indicates the OCCAP DDRC CTRL error interrupt status. Register cleared by OCCAPCFG1.occap_ddrc_ctrl_err_intr_clr. Programming Mode: Static" "0,1" newline hexmask.long.byte 0x0 10.--15. 1. "RESERVED,Reserved" newline bitfld.long 0x0 9. "OCCAP_DDRC_DATA_POISON_PARALLEL_ERR,Error when occap_ddrc_data_poison_parallel is active due to incorrect number of errors being occurring. Internal logic checks the number of errors detected while poisoning occurred for occap_ddrc_data_poison_parallel." "0,1" newline bitfld.long 0x0 8. "OCCAP_DDRC_DATA_POISON_SEQ_ERR,Error when occap_ddrc_data_poison_seq is active due to incorrect number of errors being occurring. Internal logic checks the number of errors detected while poisoning occurred for occap_ddrc_data_poison_seq. It checks for.." "0,1" newline hexmask.long.byte 0x0 2.--7. 1. "RESERVED,Reserved" newline bitfld.long 0x0 1. "OCCAP_DDRC_DATA_POISON_COMPLETE,Indicates the OCCAP DDRC DATA poisoning complete interrupt status. Register cleared by OCCAPCFG1.occap_ddrc_data_err_intr_clr. Programming Mode: Static" "0,1" newline bitfld.long 0x0 0. "OCCAP_DDRC_DATA_ERR_INTR,Indicates the OCCAP DDRC DATA error interrupt status. Register cleared by OCCAPCFG1.occap_ddrc_data_err_intr_clr. Programming Mode: Static" "0,1" line.long 0x4 "DERATESTAT,Temperature Derate Status Register" hexmask.long 0x4 1.--31. 1. "RESERVED,Reserved" newline bitfld.long 0x4 0. "DERATE_TEMP_LIMIT_INTR,Derate temperature interrupt indicating LPDDR2/3/4 SDRAM temperature operating limit is exceeded. This register field is set to 1 when the value read from MR4[2:0] is 3'b000 or 3'b111. Cleared by register.." "0,1" tree.end tree "UMCTL2_MP (uMCTL2 Multi-Port Registers)" base ad:0x1016 rgroup.long 0x4++0x3 line.long 0x0 "PSTAT,Port Status Register" bitfld.long 0x0 16. "WR_PORT_BUSY_0,Indicates if there are outstanding writes for AXI port 0. Programming Mode: Dynamic" "0,1" bitfld.long 0x0 0. "RD_PORT_BUSY_0,Indicates if there are outstanding reads for AXI port 0. Programming Mode: Dynamic" "0,1" group.long 0x8++0xB line.long 0x0 "PCCFG,Port Common Configuration Register" bitfld.long 0x0 8. "BL_EXP_MODE,Burst length expansion mode. By default (that is bl_exp_mode==0) XPI expands every AXI burst into multiple HIF commands using the memory burst length as a unit. If set to 1 then XPI uses half of the memory burst length as a unit. This.." "UMCTL2_PARTIAL_WR=1,?" bitfld.long 0x0 4. "PAGEMATCH_LIMIT,Page match four limit. If set to 1 limits the number of consecutive same page DDRC transactions that can be granted by the Port Arbiter to four when Page Match feature is enabled. If set to 0 there is no limit imposed on number of.." "0,1" bitfld.long 0x0 0. "GO2CRITICAL_EN,If set to 1 (enabled) sets co_gs_go2critical_wr and co_gs_go2critical_lpr/co_gs_go2critical_hpr signals going to DDRC based on urgent input (awurgent arurgent) coming from AXI master. If set to 0 (disabled) co_gs_go2critical_wr and.." "0,1" line.long 0x4 "PCFGR_0,Port n Configuration Read Register" bitfld.long 0x4 16. "RDWR_ORDERED_EN,Enables ordered read/writes. If set to 1 preserves the ordering between read transaction and write transaction issued to the same address on a given port. In other words the controller ensures that all same address read and write.." "0,1" bitfld.long 0x4 14. "RD_PORT_PAGEMATCH_EN,If set to 1 enables the Page Match feature. If enabled once a requesting port is granted the port is continued to be granted if the following immediate commands are to the same memory page (same rank same bank and same row). See.." "0,1" bitfld.long 0x4 13. "RD_PORT_URGENT_EN,If set to 1 enables the AXI urgent sideband signal (arurgent). When enabled and arurgent is asserted by the master that port becomes the highest priority and co_gs_go2critical_lpr/co_gs_go2critical_hpr signal to DDRC is asserted if.." "0,1" newline bitfld.long 0x4 12. "RD_PORT_AGING_EN,If set to 1 enables aging function for the read channel of the port. Programming Mode: Static" "0,1" hexmask.long.word 0x4 0.--9. 1. "RD_PORT_PRIORITY,Determines the initial load value of read aging counters. These counters are parallel loaded after reset or after each grant to the corresponding port. The aging counters down-count every clock cycle where the port is requesting but not.." line.long 0x8 "PCFGW_0,Port n Configuration Write Register" bitfld.long 0x8 14. "WR_PORT_PAGEMATCH_EN,If set to 1 enables the Page Match feature. If enabled once a requesting port is granted the port is continued to be granted if the following immediate commands are to the same memory page (same rank same bank and same row). See.." "0,1" bitfld.long 0x8 13. "WR_PORT_URGENT_EN,If set to 1 enables the AXI urgent sideband signal (awurgent). When enabled and awurgent is asserted by the master that port becomes the highest priority and co_gs_go2critical_wr signal to DDRC is asserted if enabled in.." "0,1" bitfld.long 0x8 12. "WR_PORT_AGING_EN,If set to 1 enables aging function for the write channel of the port. Programming Mode: Static" "0,1" newline hexmask.long.word 0x8 0.--9. 1. "WR_PORT_PRIORITY,Determines the initial load value of write aging counters. These counters are parallel loaded after reset or after each grant to the corresponding port. The aging counters down-count every clock cycle where the port is requesting but.." group.long 0x98++0x13 line.long 0x0 "PCTRL_0,Port n Control Register" bitfld.long 0x0 0. "PORT_EN,Enables AXI port n. Programming Mode: Dynamic" "0,1" line.long 0x4 "PCFGQOS0_0,Port n Read QoS Configuration Register 0" bitfld.long 0x4 24.--25. "RQOS_MAP_REGION2,This bitfield indicates the traffic class of region2. For dual address queue configurations region2 maps to the red address queue. Valid values are 1: VPR and 2: HPR only. When VPR support is disabled (UMCTL2_VPR_EN = 0) and traffic.." "?,VPR and,HPR only,?" bitfld.long 0x4 20.--21. "RQOS_MAP_REGION1,This bit field indicates the traffic class of region 1. Valid values are: - 0 - LPR - 1 - VPR - 2 - HPR For dual address queue configurations region1 maps to the blue address queue. In this case valid values are - 0 - LPR - 1 - VPR.." "LPR,VPR only,HPR,?" bitfld.long 0x4 16.--17. "RQOS_MAP_REGION0,This bit field indicates the traffic class of region 0. Valid values are: - 0 - LPR - 1 - VPR - 2 - HPR For dual address queue configurations region 0 maps to the blue address queue. In this case valid values are: 0: LPR and 1: VPR.." "LPR and,VPR only,HPR,?" newline hexmask.long.byte 0x4 8.--11. 1. "RQOS_MAP_LEVEL2,Separation level2 indicating the end of region1 mapping; start of region1 is (level1 + 1). Possible values for level2 are (level1 + 1) to 14 which corresponds to arqos. Region2 starts from (level2 + 1) up to 15. Note that for PA arqos.." hexmask.long.byte 0x4 0.--3. 1. "RQOS_MAP_LEVEL1,Separation level1 indicating the end of region0 mapping; start of region0 is 0. Possible values for level1 are 0 to 13 (for dual RAQ) or 0 to 14 (for single RAQ) which corresponds to arqos. Note that for PA arqos values are used directly.." line.long 0x8 "PCFGQOS1_0,Port n Read QoS Configuration Register 1" hexmask.long.word 0x8 16.--26. 1. "RQOS_MAP_TIMEOUTR,Specifies the timeout value for transactions mapped to the red address queue. Programming Mode: Quasi-dynamic Group 3" hexmask.long.word 0x8 0.--10. 1. "RQOS_MAP_TIMEOUTB,Specifies the timeout value for transactions mapped to the blue address queue. Programming Mode: Quasi-dynamic Group 3" line.long 0xC "PCFGWQOS0_0,Port n Write QoS Configuration Register 0" bitfld.long 0xC 24.--25. "WQOS_MAP_REGION2,This bit field indicates the traffic class of region 2. Valid values are: - 0 - NPW - 1 - VPW When VPW support is disabled (UMCTL2_VPW_EN = 0) and traffic class of region 2 is set to 1 (VPW) VPW traffic is aliased to NPW traffic." "NPW,VPW,?,?" bitfld.long 0xC 20.--21. "WQOS_MAP_REGION1,This bit field indicates the traffic class of region 1. Valid values are: 0: NPW 1: VPW. When VPW support is disabled (UMCTL2_VPW_EN = 0) and traffic class of region 1 is set to 1 (VPW) VPW traffic is aliased to NPW traffic." "NPW,VPW,?,?" bitfld.long 0xC 16.--17. "WQOS_MAP_REGION0,This bit field indicates the traffic class of region 0. Valid values are: - 0 - NPW - 1 - VPW When VPW support is disabled (UMCTL2_VPW_EN = 0) and traffic class of region 0 is set to 1 (VPW) VPW traffic is aliased to NPW traffic." "NPW,VPW,?,?" newline hexmask.long.byte 0xC 8.--11. 1. "WQOS_MAP_LEVEL2,Separation level2 indicating the end of region1 mapping; start of region1 is (level1 + 1). Possible values for level2 are (level1 + 1) to 14 which corresponds to awqos. Region2 starts from (level2 + 1) up to 15. Note that for PA awqos.." hexmask.long.byte 0xC 0.--3. 1. "WQOS_MAP_LEVEL1,Separation level indicating the end of region0 mapping; start of region0 is 0. Possible values for level1 are 0 to 13 which corresponds to awqos. Note that for PA awqos values are used directly as port priorities where the higher the.." line.long 0x10 "PCFGWQOS1_0,Port n Write QoS Configuration Register 1" hexmask.long.word 0x10 16.--26. 1. "WQOS_MAP_TIMEOUT2,Specifies the timeout value for write transactions in region 2. Programming Mode: Quasi-dynamic Group 3" hexmask.long.word 0x10 0.--10. 1. "WQOS_MAP_TIMEOUT1,Specifies the timeout value for write transactions in region 0 and 1. Programming Mode: Quasi-dynamic Group 3" repeat 4. (list 0x0 0x1 0x2 0x3 )(list 0x0 0x8 0x10 0x18 ) group.long ($2+0xB0C)++0x3 line.long 0x0 "SARBASE$1,SAR Base Address Register n" hexmask.long.word 0x0 0.--11. 1. "BASE_ADDR,Base address for address region n specified as awaddr[UMCTL2_A_ADDRW-1:x] and araddr[UMCTL2_A_ADDRW-1:x] where x is determined by the minimum block size parameter UMCTL2_SARMINSIZE: (x=log2(block size)). Programming Mode: Static" repeat.end repeat 4. (list 0x0 0x1 0x2 0x3 )(list 0x0 0x8 0x10 0x18 ) group.long ($2+0xB10)++0x3 line.long 0x0 "SARSIZE$1,SAR Size Register n" hexmask.long.byte 0x0 0.--7. 1. "NBLOCKS,Number of blocks for address region n. This register determines the total size of the region in multiples of minimum block size as specified by the hardware parameter UMCTL2_SARMINSIZE. The register value is encoded as number of blocks = nblocks.." repeat.end group.long 0xB2C++0x3 line.long 0x0 "SBRCTL,Scrubber Control Register" hexmask.long.word 0x0 8.--20. 1. "SCRUB_INTERVAL,Scrub interval. (512 x scrub_interval) number of clock cycles between two scrub read commands. If set to 0 scrub commands are issued back-to-back. This mode of operation (scrub_interval=0) can typically be used for scrubbing the full.." bitfld.long 0x0 4.--6. "SCRUB_BURST,Scrub burst count. Determines the number of back-to-back scrub read commands that can be issued together when the controller is in one of the HW controlled low power modes with Sideband ECC both normal operation mode and low-power mode with.." "0,1,2,3,4,5,6,7" bitfld.long 0x0 2. "SCRUB_MODE,- scrub_mode:0 ECC scrubber performs reads - scrub_mode:1 ECC scrubber performs writes Programming Mode: Dynamic" "0,1" newline bitfld.long 0x0 1. "SCRUB_DURING_LOWPOWER,Continue scrubbing during low power. If set to 1 burst of scrubs is issued in hardware controlled low power modes. There are two such modes: automatically initiated by idleness or initiated by Hardware low power interface. If set.." "0,1" bitfld.long 0x0 0. "SCRUB_EN,Enables ECC scrubber. If set to 1 enables the scrubber to generate background read commands after the memories are initialized. If set to 0 disables the scrubber resets the address generator to 0 and clears the scrubber status. This bitfield.." "0,1" rgroup.long 0xB30++0x3 line.long 0x0 "SBRSTAT,Scrubber Status Register" bitfld.long 0x0 1. "SCRUB_DONE,Scrubber done. The controller sets this bit to 1 after full range of addresses are scrubbed once while scrub_interval is set to 0. Cleared if scrub_en is set to 0 (scrubber disabled) or scrub_interval is set to a non-zero value for normal.." "0,1" bitfld.long 0x0 0. "SCRUB_BUSY,Scrubber busy. The controller sets this bit to 1 when the scrubber logic has outstanding read commands being executed. Cleared when there are no active outstanding scrub reads in the system. Programming Mode: Dynamic" "0,1" group.long 0xB34++0x3 line.long 0x0 "SBRWDATA0,Scrubber Write Data Pattern0" hexmask.long 0x0 0.--31. 1. "SCRUB_PATTERN0,ECC Scrubber write data pattern for data bus[31:0] Programming Mode: Dynamic" group.long 0xB40++0xF line.long 0x0 "SBRSTART0,Scrubber Start Address Mask Register 0" hexmask.long 0x0 0.--31. 1. "SBR_ADDRESS_START_MASK_0,sbr_address_start_mask_0 holds the bits [31:0] of the starting address the ECC scrubber generates. The register must be programmed as explained in Address Configuration in ECC Scrub and Scrubber. The scrubber address registers.." line.long 0x4 "SBRSTART1,Scrubber Start Address Mask Register 1" hexmask.long.byte 0x4 0.--3. 1. "SBR_ADDRESS_START_MASK_1,sbr_address_start_mask_1 holds bits [MEMC_HIF_ADDR_WIDTH_MAX-1:32] of the starting address the ECC scrubber generates.The register must be programmed as explained in Address Configuration in ECC Scrub and Scrubber. The scrubber.." line.long 0x8 "SBRRANGE0,Scrubber Address Range Mask Register 0" hexmask.long 0x8 0.--31. 1. "SBR_ADDRESS_RANGE_MASK_0,sbr_address_range_mask_0 holds the bits [31:0] of the scrubber address range mask. The scrubber address range mask limits the address range that the ECC scrubber can generate.The register must be programmed as explained in.." line.long 0xC "SBRRANGE1,Scrubber Address Range Mask Register 1" hexmask.long.byte 0xC 0.--3. 1. "SBR_ADDRESS_RANGE_MASK_1,sbr_address_range_mask_1 holds the bits [MEMC_HIF_ADDR_WIDTH_MAX-1:32] of the scrubber address range mask. The scrubber address range mask limits the address range that the ECC scrubber can generate.The register must be.." rgroup.long 0xBF8++0x7 line.long 0x0 "UMCTL2_VER_NUMBER,UMCTL2 Version Number Register" hexmask.long 0x0 0.--31. 1. "VER_NUMBER,Indicates the Device Version Number value. Programming Mode: Static" line.long 0x4 "UMCTL2_VER_TYPE,UMCTL2 Version Type Register" hexmask.long 0x4 0.--31. 1. "VER_TYPE,Indicates the Device Version Type value. Programming Mode: Static" tree.end tree "UMCTL2_REGS_FREQ1 (uMCTL2 DDRC FREQ1 Registers)" base ad:0x8192 group.long 0x20++0x7 line.long 0x0 "DERATEEN,[FREQ1] Temperature Derate Enable Register" bitfld.long 0x0 12. "DERATE_MR4_TUF_DIS,Disables use of MR4 TUF flag (MR4[7]) bit. - 0 - Use MR4 TUF flag (MR4[7]) - 1 - Do not use MR4 TUF Flag (MR4[7]) For LPDDR4 it is recommended to set this register to 1. For LPDDR2 and LPDDR3 contact your memory vendor for.." "Use MR4 TUF flag,Do not use MR4 TUF Flag" newline bitfld.long 0x0 8.--10. "RC_DERATE_VALUE,Derate value of tRC for LPDDR4. - 0 - Derating uses +1 - 1 - Derating uses +2 - 2 - Derating uses +3 - 3 - Derating uses +4 Present only in designs configured to support LPDDR4. The required cycles for derating can be determined by.." "Derating uses +1,Derating uses +2,Derating uses +3,Derating uses +4,?,?,?,?" newline hexmask.long.byte 0x0 4.--7. 1. "DERATE_BYTE,This bit indicates which byte of the MRR data is used for derating. The maximum valid value depends on MEMC_DRAM_TOTAL_DATA_WIDTH. Present only in designs configured to support LPDDR2/LPDDR3/LPDDR4. Programming Mode: Static" newline bitfld.long 0x0 1.--2. "DERATE_VALUE,Derate value. - 0 - Derating uses +1 - 1 - Derating uses +2 Present only in designs configured to support LPDDR2/LPDDR3/LPDDR4. Set to 0 for all LPDDR2 speed grades as derating value of +1.875 ns is less than a core_ddrc_core_clk period. For.." "Derating uses +1,Derating uses +2,?,?" newline bitfld.long 0x0 0. "DERATE_ENABLE,Enables derating. - 0 - Timing parameter derating is disabled - 1 - Timing parameter derating is enabled using MR4 read value Present only in designs configured to support LPDDR2/LPDDR3/LPDDR4. This field must be set to '0' for.." "Timing parameter derating is disabled,Timing parameter derating is enabled using MR4.." line.long 0x4 "DERATEINT,[FREQ1] Temperature Derate Interval Register" hexmask.long 0x4 0.--31. 1. "MR4_READ_INTERVAL,Interval between two MR4 reads used to derate the timing parameters. Present only in designs configured to support LPDDR2/LPDDR3/LPDDR4. This register must not be set to zero. Unit: DFI clock cycles. Programming Mode: Static" group.long 0x34++0x3 line.long 0x0 "PWRTMG,[FREQ1] Low Power Timing Register" hexmask.long.byte 0x0 16.--23. 1. "SELFREF_TO_X32,After this many clocks of the DDRC command channel being idle the uMCTL2 automatically puts the SDRAM into self-refresh. The DDRC command channel is considered idle when there are no HIF commands outstanding. This must be enabled in the.." newline hexmask.long.byte 0x0 8.--15. 1. "T_DPD_X4096,Minimum deep power-down time. For mDDR value from the JEDEC specification is 0 as mDDR exits from deep power-down mode immediately after PWRCTL.deeppowerdown_en is de-asserted. For LPDDR2/LPDDR3 value from the JEDEC specification is 500us." newline hexmask.long.byte 0x0 0.--4. 1. "POWERDOWN_TO_X32,After this many clocks of the DDRC command channel being idle the uMCTL2 automatically puts the SDRAM into power-down. The DDRC command channel is considered idle when there are no HIF commands outstanding. This must be enabled in the.." group.long 0x50++0x3 line.long 0x0 "RFSHCTL0,[FREQ1] Refresh Control Register 0" hexmask.long.byte 0x0 20.--23. 1. "REFRESH_MARGIN,Threshold value in number of DFI clock cycles before the critical refresh or page timer expires. A critical refresh is to be issued before this threshold is reached. It is recommended that this not be changed from the default value.." newline hexmask.long.byte 0x0 12.--16. 1. "REFRESH_TO_X1_X32,If the refresh timer (tRFCnom also known as tREFI) has expired at least once then a speculative refresh may be performed. A speculative refresh is a refresh performed at a time when refresh would be useful. When the SDRAM bus is idle.." newline hexmask.long.byte 0x0 4.--9. 1. "REFRESH_BURST,The programmed value + 1 is the number of refresh timeouts that is allowed to accumulate before traffic is blocked and the refreshes are forced to execute. Closing pages to perform a refresh is a one-time penalty that must be paid for each.." newline bitfld.long 0x0 2. "PER_BANK_REFRESH,- 1 - Per bank refresh - 0 - All bank refresh Per bank refresh allows traffic to flow to other banks. Per bank refresh is not supported by all LPDDR2 devices but must be supported by all LPDDR3/LPDDR4 devices. Present only in designs.." "All bank refresh,Per bank refresh" group.long 0x64++0x7 line.long 0x0 "RFSHTMG,[FREQ1] Refresh Timing Register" bitfld.long 0x0 31. "T_RFC_NOM_X1_SEL,Specifies whether the RFSHTMG.t_rfc_nom_x1_x32 and RFSHCTL0.refresh_to_x1_x32 register values are x1 or x32. - 0 - x32 register values are used - 1 - x1 register values are used This applies only when per-bank refresh is enabled.." "x32 register values are used,x1 register values are used" newline hexmask.long.word 0x0 16.--27. 1. "T_RFC_NOM_X1_X32,Average time interval between refreshes per rank (Specification: 7.8us for DDR2 DDR3 and DDR4. See JEDEC specification for mDDR LPDDR2 LPDDR3 and LPDDR4). When the controller is operating in 1:1 mode set this register to.." newline bitfld.long 0x0 15. "LPDDR3_TREFBW_EN,Used only when LPDDR3 memory type is connected. Should only be changed when uMCTL2 is in reset. Specifies whether to use the tREFBW parameter (required by some LPDDR3 devices which comply with earlier versions of the LPDDR3 JEDEC.." "tREFBW parameter not used,tREFBW parameter used" newline hexmask.long.word 0x0 0.--9. 1. "T_RFC_MIN,tRFC (min): Minimum time from refresh to refresh or activate. When the controller is operating in 1:1 mode t_rfc_min must be set to RoundUp(tRFCmin/tCK). When the controller is operating in 1:2 mode t_rfc_min must be set to.." line.long 0x4 "RFSHTMG1,[FREQ1] Refresh Timing Register1" hexmask.long.byte 0x4 16.--23. 1. "T_PBR2PBR,LPDDR4:tpbR2pbR. Per-bank refresh to Per-bank refresh different bank Time. When the controller is operating in 1:1 frequency ratio mode program this to RoundUp(tpbR2pbR/tCK). When the controller is operating in 1:2 frequency ratio mode.." repeat 4. (list 0x3 0x4 0x6 0x7 )(list 0x0 0x4 0xC 0x10 ) group.long ($2+0xDC)++0x3 line.long 0x0 "INIT$1,[FREQ1] SDRAM Initialization Register 3" hexmask.long.word 0x0 16.--31. 1. "MR,DDR2:Indicates the value to write to MR register. Bit 8 is for DLL and the setting here is ignored. The uMCTL2 sets this bit appropriately. DDR3/DDR4: Value loaded into MR0 register. mDDR: Value to write to MR register. LPDDR2/LPDDR3/LPDDR4 - Value to.." newline hexmask.long.word 0x0 0.--15. 1. "EMR,DDR2: Indicates the value to write to EMR register. Bits 9:7 are for OCD and the setting in this register is ignored. The uMCTL2 sets those bits appropriately. DDR3/DDR4: Value to write to MR1 register Set bit 7 to 0. mDDR: Value to write to EMR.." repeat.end group.long 0xF4++0x3 line.long 0x0 "RANKCTL,[FREQ1] Rank Control Register" bitfld.long 0x0 26. "DIFF_RANK_WR_GAP_MSB,Only present for multi-rank configurations. 1-bit extension to be used when RANKCTL.diff_rank_wr_gap field needs to be set to a value greater than 0xF. Programming Mode: Quasi-dynamic Group 2" "?,bit extension to be used when RANKCTL" newline bitfld.long 0x0 24. "DIFF_RANK_RD_GAP_MSB,Only present for multi-rank configurations. 1-bit extension to be used when RANKCTL.diff_rank_rd_gap field needs to be set to a value greater than 0xF. Programming Mode: Quasi-dynamic Group 2" "?,bit extension to be used when RANKCTL" newline hexmask.long.byte 0x0 12.--15. 1. "MAX_RANK_WR,Only present for multi-rank configurations. Background: Writes to the same rank can be performed back-to-back. Writes to different ranks require additional gap dictated by the register RANKCTL.diff_rank_wr_gap. This is to avoid possible data.." newline hexmask.long.byte 0x0 8.--11. 1. "DIFF_RANK_WR_GAP,Only present for multi-rank configurations. Indicates the number of clocks of gap in data responses when performing consecutive writes to different ranks. This is used to switch the delays in the PHY to match the rank requirements. This.." newline hexmask.long.byte 0x0 4.--7. 1. "DIFF_RANK_RD_GAP,Only present for multi-rank configurations. Indicates the number of clocks of gap in data responses when performing consecutive reads to different ranks. This is used to switch the delays in the PHY to match the rank requirements. This.." newline hexmask.long.byte 0x0 0.--3. 1. "MAX_RANK_RD,Only present for multi-rank configurations. Background: Reads to the same rank can be performed back-to-back. Reads to different ranks require additional gap dictated by the register RANKCTL.diff_rank_rd_gap. This is to avoid possible data.." group.long 0x100++0x3F line.long 0x0 "DRAMTMG0,[FREQ1] SDRAM Timing Register 0" hexmask.long.byte 0x0 24.--30. 1. "WR2PRE,Specifies the minimum time between write and precharge to same bank. Specifications: WL + BL/2 + tWR = approximately 8 cycles + 15 ns = 14 clocks @400MHz and less for lower frequencies. where: - WL - Write latency - BL - Burst length. This must.." newline hexmask.long.byte 0x0 16.--21. 1. "T_FAW,tFAW - valid only when 8 or more banks(or banks x bank groups) are present. In 8-bank design at most 4 banks must be activated in a rolling window of tFAW cycles. When the controller is operating in 1:2 frequency ratio mode program this to.." newline hexmask.long.byte 0x0 8.--14. 1. "T_RAS_MAX,tRAS(max) - Specifies the maximum time between activate and precharge to same bank. This is the maximum time that a page can be kept open Minimum value of this register is 1. Zero is invalid. When the controller is operating in 1:1 frequency.." newline hexmask.long.byte 0x0 0.--5. 1. "T_RAS_MIN,tRAS(min) - Specifies the minimum time between activate and precharge to the same bank. When the controller is operating in 1:2 frequency mode 1T mode program this to tRAS(min)/2. No rounding up. When the controller is operating in 1:2.." line.long 0x4 "DRAMTMG1,[FREQ1] SDRAM Timing Register 1" hexmask.long.byte 0x4 16.--20. 1. "T_XP,tXP - Specifies the minimum time after power-down exit to any operation. For DDR3 this must be programmed to tXPDLL if slow powerdown exit is selected in MR0[12]. If C/A parity for DDR4 is used set to (tXP+PL) instead. If LPDDR4 is selected and.." newline hexmask.long.byte 0x4 8.--13. 1. "RD2PRE,tRTP - Specifies the minimum time from read to precharge of same bank. - DDR2 - tAL + BL/2 + max(tRTP 2) - 2 - DDR3 - tAL + max (tRTP 4) - DDR4 - Max of following two equations: tAL + max (tRTP 4) or RL + BL/2 - tRP (*). - mDDR - BL/2 - LPDDR2.." newline hexmask.long.byte 0x4 0.--6. 1. "T_RC,tRC - Specifies the minimum time between activates to same bank. When the controller is operating in 1:2 frequency ratio mode program this to (tRC/2) and round up to next integer value. Unit: DFI clock cycles. Programming Mode: Quasi-dynamic Group.." line.long 0x8 "DRAMTMG2,[FREQ1] SDRAM Timing Register 2" hexmask.long.byte 0x8 24.--29. 1. "WRITE_LATENCY,Set this field to WL. Indicates the Time from write command to write data on SDRAM interface. This must be set to WL. For mDDR it must be set to 1. Note that depending on the PHY if using RDIMM/LRDIMM it might be necessary to adjust the.." newline hexmask.long.byte 0x8 16.--21. 1. "READ_LATENCY,Set this field to RL. Indicates the time from read command to read data on SDRAM interface. This must be set to RL. Note that depending on the PHY if using RDIMM/LRDIMM it might be necessary to adjust the value of RL to compensate for the.." newline hexmask.long.byte 0x8 8.--13. 1. "RD2WR,DDR2/3/mDDR: RL + BL/2 + 2 - WL DDR4: RL + BL/2 + 1 + WR_PREAMBLE - WL LPDDR2/LPDDR3: RL + BL/2 + RU(tDQSCKmax/tCK) + 1 - WL LPDDR4(DQ ODT is Disabled): RL + BL/2 + RU(tDQSCKmax/tCK) + WR_PREAMBLE + RD_POSTAMBLE - WL LPDDR4(DQ ODT is Enabled): RL +.." newline hexmask.long.byte 0x8 0.--5. 1. "WR2RD,DDR4: CWL + PL + BL/2 + tWTR_L LPDDR2/3/4: WL + BL/2 + tWTR + 1 Others: CWL + BL/2 + tWTR In DDR4 minimum time from write command to read command for same bank group. In others minimum time from write command to read command. Includes time for.." line.long 0xC "DRAMTMG3,[FREQ1] SDRAM Timing Register 3" hexmask.long.word 0xC 20.--29. 1. "T_MRW,Indicates the time to wait after a mode register write or read (MRW or MRR). Present only in designs configured to support LPDDR2 LPDDR3 or LPDDR4. LPDDR2 typically requires value of 5. LPDDR3 typically requires value of 10. LPDDR4: Set this to.." newline hexmask.long.byte 0xC 12.--17. 1. "T_MRD,tMRD- Indicates the number of cycles to wait after a mode register write or read. Depending on the connected SDRAM tMRD represents: - DDR2/mDDR: Time from MRS to any command - DDR3/4: Time from MRS to MRS command - LPDDR2: not used - LPDDR3/4:.." newline hexmask.long.word 0xC 0.--9. 1. "T_MOD,tMOD - Parameter used only in DDR3 and DDR4. Indicates the number of cycles between load mode command and following non-load mode command. If C/A parity for DDR4 is used set to tMOD_PAR(tMOD+PL) instead. If CAL mode is enabled.." line.long 0x10 "DRAMTMG4,[FREQ1] SDRAM Timing Register 4" hexmask.long.byte 0x10 24.--28. 1. "T_RCD,tRCD - tAL: Indicates the minimum time from activate to read or write command to same bank. When the controller is operating in 1:2 frequency ratio mode program this to ((tRCD - tAL)/2) and round it up to the next integer value. Minimum value.." newline hexmask.long.byte 0x10 16.--19. 1. "T_CCD,DDR4: tCCD_L: This is the minimum time between two reads or two writes for same bank group. Others: tCCD: This is the minimum time between two reads or two writes. When the controller is operating in 1:2 frequency ratio mode program this to.." newline hexmask.long.byte 0x10 8.--11. 1. "T_RRD,DDR4: tRRD_L: This is the minimum time between activates from bank 'a' to bank 'b' for same bank group. Others: tRRD: Minimum time between activates from bank 'a' to bank 'b' When the controller is operating in 1:2 frequency ratio mode program.." newline hexmask.long.byte 0x10 0.--4. 1. "T_RP,tRP: Indicates the minimum time from single-bank precharge to activate of same bank. When the controller is operating in 1:1 frequency ratio mode t_rp must be set to RoundUp(tRP/tCK). When the controller is operating in 1:2 frequency ratio mode.." line.long 0x14 "DRAMTMG5,[FREQ1] SDRAM Timing Register 5" hexmask.long.byte 0x14 24.--27. 1. "T_CKSRX,This is the time before self-refresh Exit that CK is maintained as a valid clock before issuing SRX. Specifies the clock stable time before SRX. Recommended settings: - mDDR - 1 - LPDDR2 - 2 - LPDDR3 - 2 - LPDDR4 - tCKCKEH - DDR2 - 1 - DDR3 -.." newline hexmask.long.byte 0x14 16.--19. 1. "T_CKSRE,This is the time after self-refresh Down Entry that CK is maintained as a valid clock. Specifies the clock disable delay after SRE. Recommended settings: - mDDR - 0 - LPDDR2 - 2 - LPDDR3 - 2 - LPDDR4 - tCKELCK - DDR2 - 1 - DDR3 - Max (10 ns 5.." newline hexmask.long.byte 0x14 8.--13. 1. "T_CKESR,Indicates the minimum CKE low width for self-refresh or self-refresh power down entry to exit timing in memory clock cycles. Recommended settings: - mDDR - tRFC - LPDDR2 - tCKESR - LPDDR3 - tCKESR - LPDDR4 - max(tCKE tSR) - DDR2 - tCKE - DDR3 -.." newline hexmask.long.byte 0x14 0.--4. 1. "T_CKE,Indicates the minimum number of cycles of CKE HIGH/LOW during power-down and self-refresh. - LPDDR2/LPDDR3 mode - Set this to the larger of tCKE or tCKESR - LPDDR4 mode - Set this to the larger of tCKE or tSR - Non-LPDDR2/non-LPDDR3/non-LPDDR4.." line.long 0x18 "DRAMTMG6,[FREQ1] SDRAM Timing Register 6" hexmask.long.byte 0x18 24.--27. 1. "T_CKDPDE,This is the time after Deep Power Down Entry that CK is maintained as a valid clock. Specifies the clock disable delay after DPDE. Recommended settings: - mDDR: 0 - LPDDR2: 2 - LPDDR3: 2 When the controller is operating in 1:2 frequency ratio.." newline hexmask.long.byte 0x18 16.--19. 1. "T_CKDPDX,This is the time before Deep Power Down Exit that CK is maintained as a valid clock before issuing DPDX. Specifies the clock stable time before DPDX. Recommended settings: - mDDR - 1 - LPDDR2 - 2 - LPDDR3 - 2 When the controller is operating in.." newline hexmask.long.byte 0x18 0.--3. 1. "T_CKCSX,This is the time before Clock Stop Exit that CK is maintained as a valid clock before issuing Clock Stop Exit. Specifies the clock stable time before next command after Clock Stop Exit. Recommended settings: - mDDR - 1 - LPDDR2 - tXP + 2 - LPDDR3.." line.long 0x1C "DRAMTMG7,[FREQ1] SDRAM Timing Register 7" hexmask.long.byte 0x1C 8.--11. 1. "T_CKPDE,This is the time after Power Down Entry that CK is maintained as a valid clock. Specifies the clock disable delay after PDE. Recommended settings: - mDDR - 0 - LPDDR2 - 2 - LPDDR3 - 2 - LPDDR4 - tCKELCK When using DDR2/3/4 SDRAM this register.." newline hexmask.long.byte 0x1C 0.--3. 1. "T_CKPDX,This is the time before Power Down Exit that CK is maintained as a valid clock before issuing PDX. Specifies the clock stable time before PDX. Recommended settings: - mDDR - 0 - LPDDR2 - 2 - LPDDR3 - 2 - LPDDR4 - tCKCKEH When using DDR2/3/4 SDRAM.." line.long 0x20 "DRAMTMG8,[FREQ1] SDRAM Timing Register 8" hexmask.long.byte 0x20 24.--30. 1. "T_XS_FAST_X32,tXS_FAST: Exit self-refresh to ZQCL ZQCS and MRS (only CL WR RTP and Geardown mode). When the controller is operating in 1:2 frequency ratio mode program this to the previous value divided by 2 and round up to next integer value. Note:.." newline hexmask.long.byte 0x20 16.--22. 1. "T_XS_ABORT_X32,tXS_ABORT: Exit self-refresh to commands not requiring a locked DLL in self-refresh Abort. When the controller is operating in 1:2 frequency ratio mode program this to the previous value divided by 2 and round up to next integer value." newline hexmask.long.byte 0x20 8.--14. 1. "T_XS_DLL_X32,tXSDLL: Exit self-refresh to commands requiring a locked DLL. When the controller is operating in 1:2 frequency ratio mode program this to the previous value divided by 2 and round up to next integer value. Note: Used only for DDR2 DDR3.." newline hexmask.long.byte 0x20 0.--6. 1. "T_XS_X32,tXS: Exit self-refresh to commands not requiring a locked DLL. When the controller is operating in 1:2 frequency ratio mode program this to the previous value divided by 2 and round up to next integer value. Note: Used only for DDR2 DDR3 and.." line.long 0x24 "DRAMTMG9,[FREQ1] SDRAM Timing Register 9" bitfld.long 0x24 30. "DDR4_WR_PREAMBLE,DDR4 Write preamble mode. - 0 - 1tCK preamble - 1 - 2tCK preamble Present only with MEMC_FREQ_RATIO=2. Programming Mode: Quasi-dynamic Group 2 Group 4" "0,1" newline bitfld.long 0x24 16.--18. "T_CCD_S,tCCD_S: This is the minimum time between two reads or two writes for different bank group. For bank switching (from bank 'a' to bank 'b') the minimum time is this value + 1. When the controller is operating in 1:2 frequency ratio mode program.." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x24 8.--11. 1. "T_RRD_S,tRRD_S: This is the minimum time between activates from bank 'a' to bank 'b' for different bank group. When the controller is operating in 1:2 frequency ratio mode program this to (tRRD_S/2) and round it up to the next integer value. Present.." newline hexmask.long.byte 0x24 0.--5. 1. "WR2RD_S,CWL + PL + BL/2 + tWTR_S Minimum time from write command to read command for different bank group. Includes time for bus turnaround recovery times and all per-bank per-rank and global constraints. Present only in designs configured to support.." line.long 0x28 "DRAMTMG10,[FREQ1] SDRAM Timing Register 10" hexmask.long.byte 0x28 16.--20. 1. "T_SYNC_GEAR,Indicates the time between MRS command and the sync pulse time. This must be even number of clocks. For DDR4-2666 and DDR4-3200 this parameter is defined as tMOD(min)+4nCK tMOD(min) is greater of 24nCK or 15ns 15ns / .625ns = 24 Max value.." newline hexmask.long.byte 0x28 8.--12. 1. "T_CMD_GEAR,Indicates a sync pulse to first valid command. For DDR4-2666 and DDR4-3200 this parameter is defined as tMOD(min) tMOD(min) is greater of 24nCK or 15ns 15ns / .625ns = 24 Max value for this register is 24 When the controller is operating in.." newline bitfld.long 0x28 2.--3. "T_GEAR_SETUP,Indicates the geardown setup time. Minimum value of this register is 1. Zero is invalid. For DDR4-2666 and DDR4-3200 this parameter is defined as 2 clks When the controller is operating in 1:2 frequency ratio mode program this to.." "0,1,2,3" newline bitfld.long 0x28 0.--1. "T_GEAR_HOLD,Indicates the geardown hold time. Minimum value of this register is 1. Zero is invalid. For DDR4-2666 and DDR4-3200 this parameter is defined as 2 clks When the controller is operating in 1:2 frequency ratio mode program this to.." "0,1,2,3" line.long 0x2C "DRAMTMG11,[FREQ1] SDRAM Timing Register 11" hexmask.long.byte 0x2C 24.--30. 1. "POST_MPSM_GAP_X32,tXMPDLL: This is the minimum Exit MPSM to commands requiring a locked DLL. When the controller is operating in 1:2 frequency ratio mode program this to (tXMPDLL/2) and round it up to the next integer value. Present only in designs.." newline hexmask.long.byte 0x2C 16.--20. 1. "T_MPX_LH,tMPX_LH: This is the minimum CS_n Low hold time to CKE rising edge. When the controller is operating in 1:2 frequency ratio mode program this to RoundUp(tMPX_LH/2)+1. Present only in designs configured to support DDR4. Unit: DFI clock cycles." newline bitfld.long 0x2C 8.--9. "T_MPX_S,tMPX_S: This is the minimum time CS setup time to CKE. When the controller is operating in 1:2 frequency ratio mode program this to (tMPX_S/2) and round it up to the next integer value. Present only in designs configured to support DDR4. Unit:.." "0,1,2,3" newline hexmask.long.byte 0x2C 0.--4. 1. "T_CKMPE,tCKMPE: This is the minimum valid clock requirement after MPSM entry. Present only in designs configured to support DDR4. When the controller is operating in 1:2 frequency ratio mode divide the value calculated using the previous equation by 2.." line.long 0x30 "DRAMTMG12,[FREQ1] SDRAM Timing Register 12" hexmask.long.byte 0x30 24.--29. 1. "T_WR_MPR,This bit is used only in DDR4. Cycles between MPR Write and other command. Set this to tMOD + AL (or tMOD + PL + AL if C/A parity is also used). When the controller is operating in 1:2 frequency ratio mode program this to (tWR_MPR/2) and round.." newline bitfld.long 0x30 16.--17. "T_CMDCKE,tCMDCKE: Indicates the delay from valid command to CKE input LOW. Set this to the larger of tESCKE or tCMDCKE When the controller is operating in 1:2 frequency ratio mode program this to (max(tESCKE tCMDCKE)/2) and round it up to the next.." "0,1,2,3" newline hexmask.long.byte 0x30 0.--4. 1. "T_MRD_PDA,tMRD_PDA: This is the Mode Register Set command cycle time in PDA mode. When the controller is operating in 1:2 frequency ratio mode program this to (tMRD_PDA/2) and round it up to the next integer value. Unit: DFI clock cycles. Programming.." line.long 0x34 "DRAMTMG13,[FREQ1] SDRAM Timing Register 13" hexmask.long.byte 0x34 24.--30. 1. "ODTLOFF,LPDDR4: ODTLoff: This is the latency from CAS-2 command to ODToff reference. When the controller is operating in 1:2 frequency ratio mode program this to (ODTLoff/2) and round it up to the next integer value. Unit: DFI clock cycles. Programming.." newline hexmask.long.byte 0x34 16.--21. 1. "T_CCD_MW,LPDDR4: tCCDMW: This is the minimum time from write or masked write to masked write command for same bank. When the controller is operating in 1:2 frequency ratio mode program this to (tCCDMW/2) and round it up to the next integer value. Unit:.." newline bitfld.long 0x34 0.--2. "T_PPD,LPDDR4: tPPD: This is the minimum time from precharge to precharge command. When the controller is operating in 1:2 frequency ratio mode program this to (tPPD/2) and round it up to the next integer value. Unit: DFI clock cycles. Programming Mode:.." "?,?,?,?,tPPD: This is the minimum time from precharge to..,?,?,?" line.long 0x38 "DRAMTMG14,[FREQ1] SDRAM Timing Register 14" hexmask.long.word 0x38 0.--11. 1. "T_XSR,tXSR: This is the exit self-refresh to any command. When the controller is operating in 1:2 frequency ratio mode program this to the previous value divided by 2 and round up to next integer value. The value 0xfff is illegal for this register.." line.long 0x3C "DRAMTMG15,[FREQ1] SDRAM Timing Register 15" bitfld.long 0x3C 31. "EN_DFI_LP_T_STAB,- 1 - Enable using tSTAB when exiting DFI LP. This must be set when the PHY is stopping the clock during DFI LP to save maximum power. - 0 - Disable using tSTAB when exiting DFI LP. Programming Mode: Quasi-dynamic Group 2 Group 4" "Disable using tSTAB when exiting DFI LP,Enable using tSTAB when exiting DFI LP" newline hexmask.long.byte 0x3C 0.--7. 1. "T_STAB_X32,tSTAB: Stabilization time. It is required in the following two cases for DDR3/DDR4 RDIMM: - When exiting power saving mode if the clock is stopped after re-enabling it the clock must be stable for a time specified by tSTAB - In the case of.." group.long 0x180++0x3 line.long 0x0 "ZQCTL0,[FREQ1] ZQ Control Register 0" bitfld.long 0x0 31. "DIS_AUTO_ZQ,- 1 - Disable uMCTL2 generation of ZQCS/MPC(ZQ calibration) command. Register DBGCMD.zq_calib_short can be used instead to issue ZQ calibration request from APB module - 0 - Internally generate ZQCS/MPC(ZQ calibration) commands based on.." "Internally generate ZQCS/MPC,Disable uMCTL2 generation of ZQCS/MPC" newline bitfld.long 0x0 30. "DIS_SRX_ZQCL,- 1 - Disable issuing of ZQCL/MPC(ZQ calibration) command at self-refresh/SR-Powerdown exit. Only applicable when run in DDR3 or DDR4 or LPDDR2 or LPDDR3 or LPDDR4 mode - 0 - Enable issuing of ZQCL/MPC(ZQ calibration) command at.." "Enable issuing of ZQCL/MPC,Disable issuing of ZQCL/MPC" newline bitfld.long 0x0 29. "ZQ_RESISTOR_SHARED,- 1 - Denotes that ZQ resistor is shared between ranks. Means ZQinit/ZQCL/ZQCS/MPC(ZQ calibration) commands are sent to one rank at a time with tZQinit/tZQCL/tZQCS/tZQCAL/tZQLAT timing met between commands so that commands to different.." "ZQ resistor is not shared,Denotes that ZQ resistor is shared between ranks" newline bitfld.long 0x0 28. "DIS_MPSMX_ZQCL,- 1 - Disable issuing of ZQCL command at Maximum Power Saving Mode exit. Only applicable when run in DDR4 mode - 0 - Enable issuing of ZQCL command at Maximum Power Saving Mode exit. Only applicable when run in DDR4 mode This is only.." "Enable issuing of ZQCL command at Maximum Power..,Disable issuing of ZQCL command at Maximum Power.." newline hexmask.long.word 0x0 16.--26. 1. "T_ZQ_LONG_NOP,tZQoper for DDR3/DDR4 tZQCL for LPDDR2/LPDDR3 tZQCAL for LPDDR4: Number of DFI clock cycles of NOP required after a ZQCL (ZQ calibration long)/MPC(ZQ Start) command is issued to SDRAM. When the controller is operating in 1:2 frequency.." newline hexmask.long.word 0x0 0.--9. 1. "T_ZQ_SHORT_NOP,tZQCS for DDR3/DD4/LPDDR2/LPDDR3 tZQLAT for LPDDR4: Number of DFI clock cycles of NOP required after a ZQCS (ZQ calibration short)/MPC(ZQ Latch) command is issued to SDRAM. When the controller is operating in 1:2 frequency ratio mode.." group.long 0x190++0x7 line.long 0x0 "DFITMG0,[FREQ1] DFI Timing Register 0" hexmask.long.byte 0x0 24.--28. 1. "DFI_T_CTRL_DELAY,Specifies the number of DFI clock cycles after an assertion or de-assertion of the DFI control signals that the control signals at the PHY-DRAM interface reflect the assertion or de-assertion. If the DFI clock and the memory clock are.." newline bitfld.long 0x0 23. "DFI_RDDATA_USE_DFI_PHY_CLK,Defines whether dfi_rddata_en/dfi_rddata/dfi_rddata_valid is generated using HDR (DFI clock) or SDR (DFI PHY clock) values. Selects whether value in DFITMG0.dfi_t_rddata_en is in terms of HDR (DFI clock) or SDR (DFI PHY clock).." "Else,?" newline hexmask.long.byte 0x0 16.--22. 1. "DFI_T_RDDATA_EN,Time from the assertion of a read command on the DFI interface to the assertion of the dfi_rddata_en signal. Refer to PHY specification for correct value. This corresponds to the DFI parameter trddata_en. Note that depending on the PHY.." newline bitfld.long 0x0 15. "DFI_WRDATA_USE_DFI_PHY_CLK,Defines whether dfi_wrdata_en/dfi_wrdata/dfi_wrdata_mask is generated using HDR (DFI clock) or SDR (DFI PHY clock) values. Selects whether value in DFITMG0.dfi_tphy_wrlat is in terms of HDR (DFI clock) or SDR (DFI PHY clock).." "Else,?" newline hexmask.long.byte 0x0 8.--13. 1. "DFI_TPHY_WRDATA,Specifies the number of clock cycles between when dfi_wrdata_en is asserted to when the associated write data is driven on the dfi_wrdata signal. This corresponds to the DFI timing parameter tphy_wrdata. For more information on correct.." newline hexmask.long.byte 0x0 0.--5. 1. "DFI_TPHY_WRLAT,Write latency. Number of clocks from the write command to write data enable (dfi_wrdata_en). This corresponds to the DFI timing parameter tphy_wrlat. Refer to PHY specification for correct value.Note that depending on the PHY if using.." line.long 0x4 "DFITMG1,[FREQ1] DFI Timing Register 1" hexmask.long.byte 0x4 28.--31. 1. "DFI_T_CMD_LAT,Specifies the number of DFI PHY clock cycles between when the dfi_cs signal is asserted and when the associated command is driven. This field is used for CAL mode must be set to '0' or tCAL which matches the CAL mode register setting in.." newline bitfld.long 0x4 24.--25. "DFI_T_PARIN_LAT,Specifies the number of DFI PHY clock cycles between when the dfi_cs signal is asserted and when the associated dfi_parity_in signal is driven. Unit: DFI PHY clock cycles. Programming Mode: Quasi-dynamic Group 4" "0,1,2,3" newline hexmask.long.byte 0x4 16.--20. 1. "DFI_T_WRDATA_DELAY,Specifies the number of DFI clock cycles between when the dfi_wrdata_en signal is asserted and when the corresponding write data transfer is completed on the DRAM bus. This corresponds to the DFI timing parameter twrdata_delay. For.." newline hexmask.long.byte 0x4 8.--12. 1. "DFI_T_DRAM_CLK_DISABLE,Specifies the number of DFI clock cycles from the assertion of the dfi_dram_clk_disable signal on the DFI until the clock to the DRAM memory devices at the PHY-DRAM boundary maintains a low value. If the DFI clock and the memory.." newline hexmask.long.byte 0x4 0.--4. 1. "DFI_T_DRAM_CLK_ENABLE,Specifies the number of DFI clock cycles from the de-assertion of the dfi_dram_clk_disable signal on the DFI until the first valid rising edge of the clock to the DRAM memory devices at the PHY-DRAM boundary. If the DFI clock and.." group.long 0x1B4++0x7 line.long 0x0 "DFITMG2,[FREQ1] DFI Timing Register 2" hexmask.long.byte 0x0 8.--14. 1. "DFI_TPHY_RDCSLAT,specifies the number of DFI PHY clock cycles between when a read command is sent on the DFI control interface and when the associated dfi_rddata_cs signal is asserted. This corresponds to the DFI timing parameter tphy_rdcslat. Refer to.." newline hexmask.long.byte 0x0 0.--5. 1. "DFI_TPHY_WRCSLAT,Specifies the number of DFI PHY clock cycles between when a write command is sent on the DFI control interface and when the associated dfi_wrdata_cs signal is asserted. This corresponds to the DFI timing parameter tphy_wrcslat. For more.." line.long 0x4 "DFITMG3,[FREQ1] DFI Timing Register 3" hexmask.long.byte 0x4 0.--4. 1. "DFI_T_GEARDOWN_DELAY,The delay from dfi_geardown_en assertion to the time of the PHY being ready to receive commands. Refer to PHY specification for correct value. When the controller is operating in 1:2 frequency ratio mode program this to.." group.long 0x240++0x3 line.long 0x0 "ODTCFG,[FREQ1] ODT Configuration Register" hexmask.long.byte 0x0 24.--27. 1. "WR_ODT_HOLD,DFI PHY clock cycles to hold ODT for a write command. The minimum supported value is 2. Recommended values: DDR2: - BL8 - 0x5 (DDR2-400/533/667) 0x6 (DDR2-800) 0x7 (DDR2-1066) - BL4 - 0x3 (DDR2-400/533/667) 0x4 (DDR2-800) 0x5 (DDR2-1066).." newline hexmask.long.byte 0x0 16.--20. 1. "WR_ODT_DELAY,Indicates the delay in DFI PHY clock cycles from issuing a write command to setting ODT values associated with that command. ODT setting must remain constant for the entire time that DQS is driven by the uMCTL2. Recommended values: DDR2: -.." newline hexmask.long.byte 0x0 8.--11. 1. "RD_ODT_HOLD,DFI PHY clock cycles to hold ODT for a read command. The minimum supported value is 2. Recommended values: DDR2: - BL8 - 0x6 (not DDR2-1066) 0x7 (DDR2-1066) - BL4 - 0x4 (not DDR2-1066) 0x5 (DDR2-1066) DDR3: - BL8 - 0x6 DDR4: - BL8 - 5 +.." newline hexmask.long.byte 0x0 2.--6. 1. "RD_ODT_DELAY,Indicates the delay in DFI PHY clock cycles from issuing a read command to setting ODT values associated with that command. ODT setting must remain constant for the entire time that DQS is driven by the uMCTL2. Recommended values: DDR2: -.." tree.end tree "UMCTL2_REGS_FREQ2 (uMCTL2 DDRC FERQ2 Registers)" base ad:0x12288 group.long 0x20++0x7 line.long 0x0 "DERATEEN,[FREQ2] Temperature Derate Enable Register" bitfld.long 0x0 12. "DERATE_MR4_TUF_DIS,Disables use of MR4 TUF flag (MR4[7]) bit. - 0 - Use MR4 TUF flag (MR4[7]) - 1 - Do not use MR4 TUF Flag (MR4[7]) For LPDDR4 it is recommended to set this register to 1. For LPDDR2 and LPDDR3 contact your memory vendor for.." "Use MR4 TUF flag,Do not use MR4 TUF Flag" newline bitfld.long 0x0 8.--10. "RC_DERATE_VALUE,Derate value of tRC for LPDDR4. - 0 - Derating uses +1 - 1 - Derating uses +2 - 2 - Derating uses +3 - 3 - Derating uses +4 Present only in designs configured to support LPDDR4. The required cycles for derating can be determined by.." "Derating uses +1,Derating uses +2,Derating uses +3,Derating uses +4,?,?,?,?" newline hexmask.long.byte 0x0 4.--7. 1. "DERATE_BYTE,This bit indicates which byte of the MRR data is used for derating. The maximum valid value depends on MEMC_DRAM_TOTAL_DATA_WIDTH. Present only in designs configured to support LPDDR2/LPDDR3/LPDDR4. Programming Mode: Static" newline bitfld.long 0x0 1.--2. "DERATE_VALUE,Derate value. - 0 - Derating uses +1 - 1 - Derating uses +2 Present only in designs configured to support LPDDR2/LPDDR3/LPDDR4. Set to 0 for all LPDDR2 speed grades as derating value of +1.875 ns is less than a core_ddrc_core_clk period. For.." "Derating uses +1,Derating uses +2,?,?" newline bitfld.long 0x0 0. "DERATE_ENABLE,Enables derating. - 0 - Timing parameter derating is disabled - 1 - Timing parameter derating is enabled using MR4 read value Present only in designs configured to support LPDDR2/LPDDR3/LPDDR4. This field must be set to '0' for.." "Timing parameter derating is disabled,Timing parameter derating is enabled using MR4.." line.long 0x4 "DERATEINT,[FREQ2] Temperature Derate Interval Register" hexmask.long 0x4 0.--31. 1. "MR4_READ_INTERVAL,Interval between two MR4 reads used to derate the timing parameters. Present only in designs configured to support LPDDR2/LPDDR3/LPDDR4. This register must not be set to zero. Unit: DFI clock cycles. Programming Mode: Static" group.long 0x34++0x3 line.long 0x0 "PWRTMG,[FREQ2] Low Power Timing Register" hexmask.long.byte 0x0 16.--23. 1. "SELFREF_TO_X32,After this many clocks of the DDRC command channel being idle the uMCTL2 automatically puts the SDRAM into self-refresh. The DDRC command channel is considered idle when there are no HIF commands outstanding. This must be enabled in the.." newline hexmask.long.byte 0x0 8.--15. 1. "T_DPD_X4096,Minimum deep power-down time. For mDDR value from the JEDEC specification is 0 as mDDR exits from deep power-down mode immediately after PWRCTL.deeppowerdown_en is de-asserted. For LPDDR2/LPDDR3 value from the JEDEC specification is 500us." newline hexmask.long.byte 0x0 0.--4. 1. "POWERDOWN_TO_X32,After this many clocks of the DDRC command channel being idle the uMCTL2 automatically puts the SDRAM into power-down. The DDRC command channel is considered idle when there are no HIF commands outstanding. This must be enabled in the.." group.long 0x50++0x3 line.long 0x0 "RFSHCTL0,[FREQ2] Refresh Control Register 0" hexmask.long.byte 0x0 20.--23. 1. "REFRESH_MARGIN,Threshold value in number of DFI clock cycles before the critical refresh or page timer expires. A critical refresh is to be issued before this threshold is reached. It is recommended that this not be changed from the default value.." newline hexmask.long.byte 0x0 12.--16. 1. "REFRESH_TO_X1_X32,If the refresh timer (tRFCnom also known as tREFI) has expired at least once then a speculative refresh may be performed. A speculative refresh is a refresh performed at a time when refresh would be useful. When the SDRAM bus is idle.." newline hexmask.long.byte 0x0 4.--9. 1. "REFRESH_BURST,The programmed value + 1 is the number of refresh timeouts that is allowed to accumulate before traffic is blocked and the refreshes are forced to execute. Closing pages to perform a refresh is a one-time penalty that must be paid for each.." newline bitfld.long 0x0 2. "PER_BANK_REFRESH,- 1 - Per bank refresh - 0 - All bank refresh Per bank refresh allows traffic to flow to other banks. Per bank refresh is not supported by all LPDDR2 devices but must be supported by all LPDDR3/LPDDR4 devices. Present only in designs.." "All bank refresh,Per bank refresh" group.long 0x64++0x7 line.long 0x0 "RFSHTMG,[FREQ2] Refresh Timing Register" bitfld.long 0x0 31. "T_RFC_NOM_X1_SEL,Specifies whether the RFSHTMG.t_rfc_nom_x1_x32 and RFSHCTL0.refresh_to_x1_x32 register values are x1 or x32. - 0 - x32 register values are used - 1 - x1 register values are used This applies only when per-bank refresh is enabled.." "x32 register values are used,x1 register values are used" newline hexmask.long.word 0x0 16.--27. 1. "T_RFC_NOM_X1_X32,Average time interval between refreshes per rank (Specification: 7.8us for DDR2 DDR3 and DDR4. See JEDEC specification for mDDR LPDDR2 LPDDR3 and LPDDR4). When the controller is operating in 1:1 mode set this register to.." newline bitfld.long 0x0 15. "LPDDR3_TREFBW_EN,Used only when LPDDR3 memory type is connected. Should only be changed when uMCTL2 is in reset. Specifies whether to use the tREFBW parameter (required by some LPDDR3 devices which comply with earlier versions of the LPDDR3 JEDEC.." "tREFBW parameter not used,tREFBW parameter used" newline hexmask.long.word 0x0 0.--9. 1. "T_RFC_MIN,tRFC (min): Minimum time from refresh to refresh or activate. When the controller is operating in 1:1 mode t_rfc_min must be set to RoundUp(tRFCmin/tCK). When the controller is operating in 1:2 mode t_rfc_min must be set to.." line.long 0x4 "RFSHTMG1,[FREQ2] Refresh Timing Register1" hexmask.long.byte 0x4 16.--23. 1. "T_PBR2PBR,LPDDR4:tpbR2pbR. Per-bank refresh to Per-bank refresh different bank Time. When the controller is operating in 1:1 frequency ratio mode program this to RoundUp(tpbR2pbR/tCK). When the controller is operating in 1:2 frequency ratio mode.." repeat 4. (list 0x3 0x4 0x6 0x7 )(list 0x0 0x4 0xC 0x10 ) group.long ($2+0xDC)++0x3 line.long 0x0 "INIT$1,[FREQ2] SDRAM Initialization Register 3" hexmask.long.word 0x0 16.--31. 1. "MR,DDR2:Indicates the value to write to MR register. Bit 8 is for DLL and the setting here is ignored. The uMCTL2 sets this bit appropriately. DDR3/DDR4: Value loaded into MR0 register. mDDR: Value to write to MR register. LPDDR2/LPDDR3/LPDDR4 - Value to.." newline hexmask.long.word 0x0 0.--15. 1. "EMR,DDR2: Indicates the value to write to EMR register. Bits 9:7 are for OCD and the setting in this register is ignored. The uMCTL2 sets those bits appropriately. DDR3/DDR4: Value to write to MR1 register Set bit 7 to 0. mDDR: Value to write to EMR.." repeat.end group.long 0xF4++0x3 line.long 0x0 "RANKCTL,[FREQ2] Rank Control Register" bitfld.long 0x0 26. "DIFF_RANK_WR_GAP_MSB,Only present for multi-rank configurations. 1-bit extension to be used when RANKCTL.diff_rank_wr_gap field needs to be set to a value greater than 0xF. Programming Mode: Quasi-dynamic Group 2" "?,bit extension to be used when RANKCTL" newline bitfld.long 0x0 24. "DIFF_RANK_RD_GAP_MSB,Only present for multi-rank configurations. 1-bit extension to be used when RANKCTL.diff_rank_rd_gap field needs to be set to a value greater than 0xF. Programming Mode: Quasi-dynamic Group 2" "?,bit extension to be used when RANKCTL" newline hexmask.long.byte 0x0 12.--15. 1. "MAX_RANK_WR,Only present for multi-rank configurations. Background: Writes to the same rank can be performed back-to-back. Writes to different ranks require additional gap dictated by the register RANKCTL.diff_rank_wr_gap. This is to avoid possible data.." newline hexmask.long.byte 0x0 8.--11. 1. "DIFF_RANK_WR_GAP,Only present for multi-rank configurations. Indicates the number of clocks of gap in data responses when performing consecutive writes to different ranks. This is used to switch the delays in the PHY to match the rank requirements. This.." newline hexmask.long.byte 0x0 4.--7. 1. "DIFF_RANK_RD_GAP,Only present for multi-rank configurations. Indicates the number of clocks of gap in data responses when performing consecutive reads to different ranks. This is used to switch the delays in the PHY to match the rank requirements. This.." newline hexmask.long.byte 0x0 0.--3. 1. "MAX_RANK_RD,Only present for multi-rank configurations. Background: Reads to the same rank can be performed back-to-back. Reads to different ranks require additional gap dictated by the register RANKCTL.diff_rank_rd_gap. This is to avoid possible data.." group.long 0x100++0x3F line.long 0x0 "DRAMTMG0,[FREQ2] SDRAM Timing Register 0" hexmask.long.byte 0x0 24.--30. 1. "WR2PRE,Specifies the minimum time between write and precharge to same bank. Specifications: WL + BL/2 + tWR = approximately 8 cycles + 15 ns = 14 clocks @400MHz and less for lower frequencies. where: - WL - Write latency - BL - Burst length. This must.." newline hexmask.long.byte 0x0 16.--21. 1. "T_FAW,tFAW - valid only when 8 or more banks(or banks x bank groups) are present. In 8-bank design at most 4 banks must be activated in a rolling window of tFAW cycles. When the controller is operating in 1:2 frequency ratio mode program this to.." newline hexmask.long.byte 0x0 8.--14. 1. "T_RAS_MAX,tRAS(max) - Specifies the maximum time between activate and precharge to same bank. This is the maximum time that a page can be kept open Minimum value of this register is 1. Zero is invalid. When the controller is operating in 1:1 frequency.." newline hexmask.long.byte 0x0 0.--5. 1. "T_RAS_MIN,tRAS(min) - Specifies the minimum time between activate and precharge to the same bank. When the controller is operating in 1:2 frequency mode 1T mode program this to tRAS(min)/2. No rounding up. When the controller is operating in 1:2.." line.long 0x4 "DRAMTMG1,[FREQ2] SDRAM Timing Register 1" hexmask.long.byte 0x4 16.--20. 1. "T_XP,tXP - Specifies the minimum time after power-down exit to any operation. For DDR3 this must be programmed to tXPDLL if slow powerdown exit is selected in MR0[12]. If C/A parity for DDR4 is used set to (tXP+PL) instead. If LPDDR4 is selected and.." newline hexmask.long.byte 0x4 8.--13. 1. "RD2PRE,tRTP - Specifies the minimum time from read to precharge of same bank. - DDR2 - tAL + BL/2 + max(tRTP 2) - 2 - DDR3 - tAL + max (tRTP 4) - DDR4 - Max of following two equations: tAL + max (tRTP 4) or RL + BL/2 - tRP (*). - mDDR - BL/2 - LPDDR2.." newline hexmask.long.byte 0x4 0.--6. 1. "T_RC,tRC - Specifies the minimum time between activates to same bank. When the controller is operating in 1:2 frequency ratio mode program this to (tRC/2) and round up to next integer value. Unit: DFI clock cycles. Programming Mode: Quasi-dynamic Group.." line.long 0x8 "DRAMTMG2,[FREQ2] SDRAM Timing Register 2" hexmask.long.byte 0x8 24.--29. 1. "WRITE_LATENCY,Set this field to WL. Indicates the Time from write command to write data on SDRAM interface. This must be set to WL. For mDDR it must be set to 1. Note that depending on the PHY if using RDIMM/LRDIMM it might be necessary to adjust the.." newline hexmask.long.byte 0x8 16.--21. 1. "READ_LATENCY,Set this field to RL. Indicates the time from read command to read data on SDRAM interface. This must be set to RL. Note that depending on the PHY if using RDIMM/LRDIMM it might be necessary to adjust the value of RL to compensate for the.." newline hexmask.long.byte 0x8 8.--13. 1. "RD2WR,DDR2/3/mDDR: RL + BL/2 + 2 - WL DDR4: RL + BL/2 + 1 + WR_PREAMBLE - WL LPDDR2/LPDDR3: RL + BL/2 + RU(tDQSCKmax/tCK) + 1 - WL LPDDR4(DQ ODT is Disabled): RL + BL/2 + RU(tDQSCKmax/tCK) + WR_PREAMBLE + RD_POSTAMBLE - WL LPDDR4(DQ ODT is Enabled): RL +.." newline hexmask.long.byte 0x8 0.--5. 1. "WR2RD,DDR4: CWL + PL + BL/2 + tWTR_L LPDDR2/3/4: WL + BL/2 + tWTR + 1 Others: CWL + BL/2 + tWTR In DDR4 minimum time from write command to read command for same bank group. In others minimum time from write command to read command. Includes time for.." line.long 0xC "DRAMTMG3,[FREQ2] SDRAM Timing Register 3" hexmask.long.word 0xC 20.--29. 1. "T_MRW,Indicates the time to wait after a mode register write or read (MRW or MRR). Present only in designs configured to support LPDDR2 LPDDR3 or LPDDR4. LPDDR2 typically requires value of 5. LPDDR3 typically requires value of 10. LPDDR4: Set this to.." newline hexmask.long.byte 0xC 12.--17. 1. "T_MRD,tMRD- Indicates the number of cycles to wait after a mode register write or read. Depending on the connected SDRAM tMRD represents: - DDR2/mDDR: Time from MRS to any command - DDR3/4: Time from MRS to MRS command - LPDDR2: not used - LPDDR3/4:.." newline hexmask.long.word 0xC 0.--9. 1. "T_MOD,tMOD - Parameter used only in DDR3 and DDR4. Indicates the number of cycles between load mode command and following non-load mode command. If C/A parity for DDR4 is used set to tMOD_PAR(tMOD+PL) instead. If CAL mode is enabled.." line.long 0x10 "DRAMTMG4,[FREQ2] SDRAM Timing Register 4" hexmask.long.byte 0x10 24.--28. 1. "T_RCD,tRCD - tAL: Indicates the minimum time from activate to read or write command to same bank. When the controller is operating in 1:2 frequency ratio mode program this to ((tRCD - tAL)/2) and round it up to the next integer value. Minimum value.." newline hexmask.long.byte 0x10 16.--19. 1. "T_CCD,DDR4: tCCD_L: This is the minimum time between two reads or two writes for same bank group. Others: tCCD: This is the minimum time between two reads or two writes. When the controller is operating in 1:2 frequency ratio mode program this to.." newline hexmask.long.byte 0x10 8.--11. 1. "T_RRD,DDR4: tRRD_L: This is the minimum time between activates from bank 'a' to bank 'b' for same bank group. Others: tRRD: Minimum time between activates from bank 'a' to bank 'b' When the controller is operating in 1:2 frequency ratio mode program.." newline hexmask.long.byte 0x10 0.--4. 1. "T_RP,tRP: Indicates the minimum time from single-bank precharge to activate of same bank. When the controller is operating in 1:1 frequency ratio mode t_rp must be set to RoundUp(tRP/tCK). When the controller is operating in 1:2 frequency ratio mode.." line.long 0x14 "DRAMTMG5,[FREQ2] SDRAM Timing Register 5" hexmask.long.byte 0x14 24.--27. 1. "T_CKSRX,This is the time before self-refresh Exit that CK is maintained as a valid clock before issuing SRX. Specifies the clock stable time before SRX. Recommended settings: - mDDR - 1 - LPDDR2 - 2 - LPDDR3 - 2 - LPDDR4 - tCKCKEH - DDR2 - 1 - DDR3 -.." newline hexmask.long.byte 0x14 16.--19. 1. "T_CKSRE,This is the time after self-refresh Down Entry that CK is maintained as a valid clock. Specifies the clock disable delay after SRE. Recommended settings: - mDDR - 0 - LPDDR2 - 2 - LPDDR3 - 2 - LPDDR4 - tCKELCK - DDR2 - 1 - DDR3 - Max (10 ns 5.." newline hexmask.long.byte 0x14 8.--13. 1. "T_CKESR,Indicates the minimum CKE low width for self-refresh or self-refresh power down entry to exit timing in memory clock cycles. Recommended settings: - mDDR - tRFC - LPDDR2 - tCKESR - LPDDR3 - tCKESR - LPDDR4 - max(tCKE tSR) - DDR2 - tCKE - DDR3 -.." newline hexmask.long.byte 0x14 0.--4. 1. "T_CKE,Indicates the minimum number of cycles of CKE HIGH/LOW during power-down and self-refresh. - LPDDR2/LPDDR3 mode - Set this to the larger of tCKE or tCKESR - LPDDR4 mode - Set this to the larger of tCKE or tSR - Non-LPDDR2/non-LPDDR3/non-LPDDR4.." line.long 0x18 "DRAMTMG6,[FREQ2] SDRAM Timing Register 6" hexmask.long.byte 0x18 24.--27. 1. "T_CKDPDE,This is the time after Deep Power Down Entry that CK is maintained as a valid clock. Specifies the clock disable delay after DPDE. Recommended settings: - mDDR: 0 - LPDDR2: 2 - LPDDR3: 2 When the controller is operating in 1:2 frequency ratio.." newline hexmask.long.byte 0x18 16.--19. 1. "T_CKDPDX,This is the time before Deep Power Down Exit that CK is maintained as a valid clock before issuing DPDX. Specifies the clock stable time before DPDX. Recommended settings: - mDDR - 1 - LPDDR2 - 2 - LPDDR3 - 2 When the controller is operating in.." newline hexmask.long.byte 0x18 0.--3. 1. "T_CKCSX,This is the time before Clock Stop Exit that CK is maintained as a valid clock before issuing Clock Stop Exit. Specifies the clock stable time before next command after Clock Stop Exit. Recommended settings: - mDDR - 1 - LPDDR2 - tXP + 2 - LPDDR3.." line.long 0x1C "DRAMTMG7,[FREQ2] SDRAM Timing Register 7" hexmask.long.byte 0x1C 8.--11. 1. "T_CKPDE,This is the time after Power Down Entry that CK is maintained as a valid clock. Specifies the clock disable delay after PDE. Recommended settings: - mDDR - 0 - LPDDR2 - 2 - LPDDR3 - 2 - LPDDR4 - tCKELCK When using DDR2/3/4 SDRAM this register.." newline hexmask.long.byte 0x1C 0.--3. 1. "T_CKPDX,This is the time before Power Down Exit that CK is maintained as a valid clock before issuing PDX. Specifies the clock stable time before PDX. Recommended settings: - mDDR - 0 - LPDDR2 - 2 - LPDDR3 - 2 - LPDDR4 - tCKCKEH When using DDR2/3/4 SDRAM.." line.long 0x20 "DRAMTMG8,[FREQ2] SDRAM Timing Register 8" hexmask.long.byte 0x20 24.--30. 1. "T_XS_FAST_X32,tXS_FAST: Exit self-refresh to ZQCL ZQCS and MRS (only CL WR RTP and Geardown mode). When the controller is operating in 1:2 frequency ratio mode program this to the previous value divided by 2 and round up to next integer value. Note:.." newline hexmask.long.byte 0x20 16.--22. 1. "T_XS_ABORT_X32,tXS_ABORT: Exit self-refresh to commands not requiring a locked DLL in self-refresh Abort. When the controller is operating in 1:2 frequency ratio mode program this to the previous value divided by 2 and round up to next integer value." newline hexmask.long.byte 0x20 8.--14. 1. "T_XS_DLL_X32,tXSDLL: Exit self-refresh to commands requiring a locked DLL. When the controller is operating in 1:2 frequency ratio mode program this to the previous value divided by 2 and round up to next integer value. Note: Used only for DDR2 DDR3.." newline hexmask.long.byte 0x20 0.--6. 1. "T_XS_X32,tXS: Exit self-refresh to commands not requiring a locked DLL. When the controller is operating in 1:2 frequency ratio mode program this to the previous value divided by 2 and round up to next integer value. Note: Used only for DDR2 DDR3 and.." line.long 0x24 "DRAMTMG9,[FREQ2] SDRAM Timing Register 9" bitfld.long 0x24 30. "DDR4_WR_PREAMBLE,DDR4 Write preamble mode. - 0 - 1tCK preamble - 1 - 2tCK preamble Present only with MEMC_FREQ_RATIO=2. Programming Mode: Quasi-dynamic Group 2 Group 4" "0,1" newline bitfld.long 0x24 16.--18. "T_CCD_S,tCCD_S: This is the minimum time between two reads or two writes for different bank group. For bank switching (from bank 'a' to bank 'b') the minimum time is this value + 1. When the controller is operating in 1:2 frequency ratio mode program.." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x24 8.--11. 1. "T_RRD_S,tRRD_S: This is the minimum time between activates from bank 'a' to bank 'b' for different bank group. When the controller is operating in 1:2 frequency ratio mode program this to (tRRD_S/2) and round it up to the next integer value. Present.." newline hexmask.long.byte 0x24 0.--5. 1. "WR2RD_S,CWL + PL + BL/2 + tWTR_S Minimum time from write command to read command for different bank group. Includes time for bus turnaround recovery times and all per-bank per-rank and global constraints. Present only in designs configured to support.." line.long 0x28 "DRAMTMG10,[FREQ2] SDRAM Timing Register 10" hexmask.long.byte 0x28 16.--20. 1. "T_SYNC_GEAR,Indicates the time between MRS command and the sync pulse time. This must be even number of clocks. For DDR4-2666 and DDR4-3200 this parameter is defined as tMOD(min)+4nCK tMOD(min) is greater of 24nCK or 15ns 15ns / .625ns = 24 Max value.." newline hexmask.long.byte 0x28 8.--12. 1. "T_CMD_GEAR,Indicates a sync pulse to first valid command. For DDR4-2666 and DDR4-3200 this parameter is defined as tMOD(min) tMOD(min) is greater of 24nCK or 15ns 15ns / .625ns = 24 Max value for this register is 24 When the controller is operating in.." newline bitfld.long 0x28 2.--3. "T_GEAR_SETUP,Indicates the geardown setup time. Minimum value of this register is 1. Zero is invalid. For DDR4-2666 and DDR4-3200 this parameter is defined as 2 clks When the controller is operating in 1:2 frequency ratio mode program this to.." "0,1,2,3" newline bitfld.long 0x28 0.--1. "T_GEAR_HOLD,Indicates the geardown hold time. Minimum value of this register is 1. Zero is invalid. For DDR4-2666 and DDR4-3200 this parameter is defined as 2 clks When the controller is operating in 1:2 frequency ratio mode program this to.." "0,1,2,3" line.long 0x2C "DRAMTMG11,[FREQ2] SDRAM Timing Register 11" hexmask.long.byte 0x2C 24.--30. 1. "POST_MPSM_GAP_X32,tXMPDLL: This is the minimum Exit MPSM to commands requiring a locked DLL. When the controller is operating in 1:2 frequency ratio mode program this to (tXMPDLL/2) and round it up to the next integer value. Present only in designs.." newline hexmask.long.byte 0x2C 16.--20. 1. "T_MPX_LH,tMPX_LH: This is the minimum CS_n Low hold time to CKE rising edge. When the controller is operating in 1:2 frequency ratio mode program this to RoundUp(tMPX_LH/2)+1. Present only in designs configured to support DDR4. Unit: DFI clock cycles." newline bitfld.long 0x2C 8.--9. "T_MPX_S,tMPX_S: This is the minimum time CS setup time to CKE. When the controller is operating in 1:2 frequency ratio mode program this to (tMPX_S/2) and round it up to the next integer value. Present only in designs configured to support DDR4. Unit:.." "0,1,2,3" newline hexmask.long.byte 0x2C 0.--4. 1. "T_CKMPE,tCKMPE: This is the minimum valid clock requirement after MPSM entry. Present only in designs configured to support DDR4. When the controller is operating in 1:2 frequency ratio mode divide the value calculated using the previous equation by 2.." line.long 0x30 "DRAMTMG12,[FREQ2] SDRAM Timing Register 12" hexmask.long.byte 0x30 24.--29. 1. "T_WR_MPR,This bit is used only in DDR4. Cycles between MPR Write and other command. Set this to tMOD + AL (or tMOD + PL + AL if C/A parity is also used). When the controller is operating in 1:2 frequency ratio mode program this to (tWR_MPR/2) and round.." newline bitfld.long 0x30 16.--17. "T_CMDCKE,tCMDCKE: Indicates the delay from valid command to CKE input LOW. Set this to the larger of tESCKE or tCMDCKE When the controller is operating in 1:2 frequency ratio mode program this to (max(tESCKE tCMDCKE)/2) and round it up to the next.." "0,1,2,3" newline hexmask.long.byte 0x30 0.--4. 1. "T_MRD_PDA,tMRD_PDA: This is the Mode Register Set command cycle time in PDA mode. When the controller is operating in 1:2 frequency ratio mode program this to (tMRD_PDA/2) and round it up to the next integer value. Unit: DFI clock cycles. Programming.." line.long 0x34 "DRAMTMG13,[FREQ2] SDRAM Timing Register 13" hexmask.long.byte 0x34 24.--30. 1. "ODTLOFF,LPDDR4: ODTLoff: This is the latency from CAS-2 command to ODToff reference. When the controller is operating in 1:2 frequency ratio mode program this to (ODTLoff/2) and round it up to the next integer value. Unit: DFI clock cycles. Programming.." newline hexmask.long.byte 0x34 16.--21. 1. "T_CCD_MW,LPDDR4: tCCDMW: This is the minimum time from write or masked write to masked write command for same bank. When the controller is operating in 1:2 frequency ratio mode program this to (tCCDMW/2) and round it up to the next integer value. Unit:.." newline bitfld.long 0x34 0.--2. "T_PPD,LPDDR4: tPPD: This is the minimum time from precharge to precharge command. When the controller is operating in 1:2 frequency ratio mode program this to (tPPD/2) and round it up to the next integer value. Unit: DFI clock cycles. Programming Mode:.." "?,?,?,?,tPPD: This is the minimum time from precharge to..,?,?,?" line.long 0x38 "DRAMTMG14,[FREQ2] SDRAM Timing Register 14" hexmask.long.word 0x38 0.--11. 1. "T_XSR,tXSR: This is the exit self-refresh to any command. When the controller is operating in 1:2 frequency ratio mode program this to the previous value divided by 2 and round up to next integer value. The value 0xfff is illegal for this register.." line.long 0x3C "DRAMTMG15,[FREQ2] SDRAM Timing Register 15" bitfld.long 0x3C 31. "EN_DFI_LP_T_STAB,- 1 - Enable using tSTAB when exiting DFI LP. This must be set when the PHY is stopping the clock during DFI LP to save maximum power. - 0 - Disable using tSTAB when exiting DFI LP. Programming Mode: Quasi-dynamic Group 2 Group 4" "Disable using tSTAB when exiting DFI LP,Enable using tSTAB when exiting DFI LP" newline hexmask.long.byte 0x3C 0.--7. 1. "T_STAB_X32,tSTAB: Stabilization time. It is required in the following two cases for DDR3/DDR4 RDIMM: - When exiting power saving mode if the clock is stopped after re-enabling it the clock must be stable for a time specified by tSTAB - In the case of.." group.long 0x180++0x3 line.long 0x0 "ZQCTL0,[FREQ2] ZQ Control Register 0" bitfld.long 0x0 31. "DIS_AUTO_ZQ,- 1 - Disable uMCTL2 generation of ZQCS/MPC(ZQ calibration) command. Register DBGCMD.zq_calib_short can be used instead to issue ZQ calibration request from APB module - 0 - Internally generate ZQCS/MPC(ZQ calibration) commands based on.." "Internally generate ZQCS/MPC,Disable uMCTL2 generation of ZQCS/MPC" newline bitfld.long 0x0 30. "DIS_SRX_ZQCL,- 1 - Disable issuing of ZQCL/MPC(ZQ calibration) command at self-refresh/SR-Powerdown exit. Only applicable when run in DDR3 or DDR4 or LPDDR2 or LPDDR3 or LPDDR4 mode - 0 - Enable issuing of ZQCL/MPC(ZQ calibration) command at.." "Enable issuing of ZQCL/MPC,Disable issuing of ZQCL/MPC" newline bitfld.long 0x0 29. "ZQ_RESISTOR_SHARED,- 1 - Denotes that ZQ resistor is shared between ranks. Means ZQinit/ZQCL/ZQCS/MPC(ZQ calibration) commands are sent to one rank at a time with tZQinit/tZQCL/tZQCS/tZQCAL/tZQLAT timing met between commands so that commands to different.." "ZQ resistor is not shared,Denotes that ZQ resistor is shared between ranks" newline bitfld.long 0x0 28. "DIS_MPSMX_ZQCL,- 1 - Disable issuing of ZQCL command at Maximum Power Saving Mode exit. Only applicable when run in DDR4 mode - 0 - Enable issuing of ZQCL command at Maximum Power Saving Mode exit. Only applicable when run in DDR4 mode This is only.." "Enable issuing of ZQCL command at Maximum Power..,Disable issuing of ZQCL command at Maximum Power.." newline hexmask.long.word 0x0 16.--26. 1. "T_ZQ_LONG_NOP,tZQoper for DDR3/DDR4 tZQCL for LPDDR2/LPDDR3 tZQCAL for LPDDR4: Number of DFI clock cycles of NOP required after a ZQCL (ZQ calibration long)/MPC(ZQ Start) command is issued to SDRAM. When the controller is operating in 1:2 frequency.." newline hexmask.long.word 0x0 0.--9. 1. "T_ZQ_SHORT_NOP,tZQCS for DDR3/DD4/LPDDR2/LPDDR3 tZQLAT for LPDDR4: Number of DFI clock cycles of NOP required after a ZQCS (ZQ calibration short)/MPC(ZQ Latch) command is issued to SDRAM. When the controller is operating in 1:2 frequency ratio mode.." group.long 0x190++0x7 line.long 0x0 "DFITMG0,[FREQ2] DFI Timing Register 0" hexmask.long.byte 0x0 24.--28. 1. "DFI_T_CTRL_DELAY,Specifies the number of DFI clock cycles after an assertion or de-assertion of the DFI control signals that the control signals at the PHY-DRAM interface reflect the assertion or de-assertion. If the DFI clock and the memory clock are.." newline bitfld.long 0x0 23. "DFI_RDDATA_USE_DFI_PHY_CLK,Defines whether dfi_rddata_en/dfi_rddata/dfi_rddata_valid is generated using HDR (DFI clock) or SDR (DFI PHY clock) values. Selects whether value in DFITMG0.dfi_t_rddata_en is in terms of HDR (DFI clock) or SDR (DFI PHY clock).." "Else,?" newline hexmask.long.byte 0x0 16.--22. 1. "DFI_T_RDDATA_EN,Time from the assertion of a read command on the DFI interface to the assertion of the dfi_rddata_en signal. Refer to PHY specification for correct value. This corresponds to the DFI parameter trddata_en. Note that depending on the PHY.." newline bitfld.long 0x0 15. "DFI_WRDATA_USE_DFI_PHY_CLK,Defines whether dfi_wrdata_en/dfi_wrdata/dfi_wrdata_mask is generated using HDR (DFI clock) or SDR (DFI PHY clock) values. Selects whether value in DFITMG0.dfi_tphy_wrlat is in terms of HDR (DFI clock) or SDR (DFI PHY clock).." "Else,?" newline hexmask.long.byte 0x0 8.--13. 1. "DFI_TPHY_WRDATA,Specifies the number of clock cycles between when dfi_wrdata_en is asserted to when the associated write data is driven on the dfi_wrdata signal. This corresponds to the DFI timing parameter tphy_wrdata. For more information on correct.." newline hexmask.long.byte 0x0 0.--5. 1. "DFI_TPHY_WRLAT,Write latency. Number of clocks from the write command to write data enable (dfi_wrdata_en). This corresponds to the DFI timing parameter tphy_wrlat. Refer to PHY specification for correct value.Note that depending on the PHY if using.." line.long 0x4 "DFITMG1,[FREQ2] DFI Timing Register 1" hexmask.long.byte 0x4 28.--31. 1. "DFI_T_CMD_LAT,Specifies the number of DFI PHY clock cycles between when the dfi_cs signal is asserted and when the associated command is driven. This field is used for CAL mode must be set to '0' or tCAL which matches the CAL mode register setting in.." newline bitfld.long 0x4 24.--25. "DFI_T_PARIN_LAT,Specifies the number of DFI PHY clock cycles between when the dfi_cs signal is asserted and when the associated dfi_parity_in signal is driven. Unit: DFI PHY clock cycles. Programming Mode: Quasi-dynamic Group 4" "0,1,2,3" newline hexmask.long.byte 0x4 16.--20. 1. "DFI_T_WRDATA_DELAY,Specifies the number of DFI clock cycles between when the dfi_wrdata_en signal is asserted and when the corresponding write data transfer is completed on the DRAM bus. This corresponds to the DFI timing parameter twrdata_delay. For.." newline hexmask.long.byte 0x4 8.--12. 1. "DFI_T_DRAM_CLK_DISABLE,Specifies the number of DFI clock cycles from the assertion of the dfi_dram_clk_disable signal on the DFI until the clock to the DRAM memory devices at the PHY-DRAM boundary maintains a low value. If the DFI clock and the memory.." newline hexmask.long.byte 0x4 0.--4. 1. "DFI_T_DRAM_CLK_ENABLE,Specifies the number of DFI clock cycles from the de-assertion of the dfi_dram_clk_disable signal on the DFI until the first valid rising edge of the clock to the DRAM memory devices at the PHY-DRAM boundary. If the DFI clock and.." group.long 0x1B4++0x7 line.long 0x0 "DFITMG2,[FREQ2] DFI Timing Register 2" hexmask.long.byte 0x0 8.--14. 1. "DFI_TPHY_RDCSLAT,specifies the number of DFI PHY clock cycles between when a read command is sent on the DFI control interface and when the associated dfi_rddata_cs signal is asserted. This corresponds to the DFI timing parameter tphy_rdcslat. Refer to.." newline hexmask.long.byte 0x0 0.--5. 1. "DFI_TPHY_WRCSLAT,Specifies the number of DFI PHY clock cycles between when a write command is sent on the DFI control interface and when the associated dfi_wrdata_cs signal is asserted. This corresponds to the DFI timing parameter tphy_wrcslat. For more.." line.long 0x4 "DFITMG3,[FREQ2] DFI Timing Register 3" hexmask.long.byte 0x4 0.--4. 1. "DFI_T_GEARDOWN_DELAY,The delay from dfi_geardown_en assertion to the time of the PHY being ready to receive commands. Refer to PHY specification for correct value. When the controller is operating in 1:2 frequency ratio mode program this to.." group.long 0x240++0x3 line.long 0x0 "ODTCFG,[FREQ2] ODT Configuration Register" hexmask.long.byte 0x0 24.--27. 1. "WR_ODT_HOLD,DFI PHY clock cycles to hold ODT for a write command. The minimum supported value is 2. Recommended values: DDR2: - BL8 - 0x5 (DDR2-400/533/667) 0x6 (DDR2-800) 0x7 (DDR2-1066) - BL4 - 0x3 (DDR2-400/533/667) 0x4 (DDR2-800) 0x5 (DDR2-1066).." newline hexmask.long.byte 0x0 16.--20. 1. "WR_ODT_DELAY,Indicates the delay in DFI PHY clock cycles from issuing a write command to setting ODT values associated with that command. ODT setting must remain constant for the entire time that DQS is driven by the uMCTL2. Recommended values: DDR2: -.." newline hexmask.long.byte 0x0 8.--11. 1. "RD_ODT_HOLD,DFI PHY clock cycles to hold ODT for a read command. The minimum supported value is 2. Recommended values: DDR2: - BL8 - 0x6 (not DDR2-1066) 0x7 (DDR2-1066) - BL4 - 0x4 (not DDR2-1066) 0x5 (DDR2-1066) DDR3: - BL8 - 0x6 DDR4: - BL8 - 5 +.." newline hexmask.long.byte 0x0 2.--6. 1. "RD_ODT_DELAY,Indicates the delay in DFI PHY clock cycles from issuing a read command to setting ODT values associated with that command. ODT setting must remain constant for the entire time that DQS is driven by the uMCTL2. Recommended values: DDR2: -.." tree.end tree "UMCTL2_REGS_FREQ3 (uMCTL2 DDRC FREQ3 Registers)" base ad:0x16384 group.long 0x20++0x7 line.long 0x0 "DERATEEN,[FREQ3] Temperature Derate Enable Register" bitfld.long 0x0 12. "DERATE_MR4_TUF_DIS,Disables use of MR4 TUF flag (MR4[7]) bit. - 0 - Use MR4 TUF flag (MR4[7]) - 1 - Do not use MR4 TUF Flag (MR4[7]) For LPDDR4 it is recommended to set this register to 1. For LPDDR2 and LPDDR3 contact your memory vendor for.." "Use MR4 TUF flag,Do not use MR4 TUF Flag" newline bitfld.long 0x0 8.--10. "RC_DERATE_VALUE,Derate value of tRC for LPDDR4. - 0 - Derating uses +1 - 1 - Derating uses +2 - 2 - Derating uses +3 - 3 - Derating uses +4 Present only in designs configured to support LPDDR4. The required cycles for derating can be determined by.." "Derating uses +1,Derating uses +2,Derating uses +3,Derating uses +4,?,?,?,?" newline hexmask.long.byte 0x0 4.--7. 1. "DERATE_BYTE,This bit indicates which byte of the MRR data is used for derating. The maximum valid value depends on MEMC_DRAM_TOTAL_DATA_WIDTH. Present only in designs configured to support LPDDR2/LPDDR3/LPDDR4. Programming Mode: Static" newline bitfld.long 0x0 1.--2. "DERATE_VALUE,Derate value. - 0 - Derating uses +1 - 1 - Derating uses +2 Present only in designs configured to support LPDDR2/LPDDR3/LPDDR4. Set to 0 for all LPDDR2 speed grades as derating value of +1.875 ns is less than a core_ddrc_core_clk period. For.." "Derating uses +1,Derating uses +2,?,?" newline bitfld.long 0x0 0. "DERATE_ENABLE,Enables derating. - 0 - Timing parameter derating is disabled - 1 - Timing parameter derating is enabled using MR4 read value Present only in designs configured to support LPDDR2/LPDDR3/LPDDR4. This field must be set to '0' for.." "Timing parameter derating is disabled,Timing parameter derating is enabled using MR4.." line.long 0x4 "DERATEINT,[FREQ3] Temperature Derate Interval Register" hexmask.long 0x4 0.--31. 1. "MR4_READ_INTERVAL,Interval between two MR4 reads used to derate the timing parameters. Present only in designs configured to support LPDDR2/LPDDR3/LPDDR4. This register must not be set to zero. Unit: DFI clock cycles. Programming Mode: Static" group.long 0x34++0x3 line.long 0x0 "PWRTMG,[FREQ3] Low Power Timing Register" hexmask.long.byte 0x0 16.--23. 1. "SELFREF_TO_X32,After this many clocks of the DDRC command channel being idle the uMCTL2 automatically puts the SDRAM into self-refresh. The DDRC command channel is considered idle when there are no HIF commands outstanding. This must be enabled in the.." newline hexmask.long.byte 0x0 8.--15. 1. "T_DPD_X4096,Minimum deep power-down time. For mDDR value from the JEDEC specification is 0 as mDDR exits from deep power-down mode immediately after PWRCTL.deeppowerdown_en is de-asserted. For LPDDR2/LPDDR3 value from the JEDEC specification is 500us." newline hexmask.long.byte 0x0 0.--4. 1. "POWERDOWN_TO_X32,After this many clocks of the DDRC command channel being idle the uMCTL2 automatically puts the SDRAM into power-down. The DDRC command channel is considered idle when there are no HIF commands outstanding. This must be enabled in the.." group.long 0x50++0x3 line.long 0x0 "RFSHCTL0,[FREQ3] Refresh Control Register 0" hexmask.long.byte 0x0 20.--23. 1. "REFRESH_MARGIN,Threshold value in number of DFI clock cycles before the critical refresh or page timer expires. A critical refresh is to be issued before this threshold is reached. It is recommended that this not be changed from the default value.." newline hexmask.long.byte 0x0 12.--16. 1. "REFRESH_TO_X1_X32,If the refresh timer (tRFCnom also known as tREFI) has expired at least once then a speculative refresh may be performed. A speculative refresh is a refresh performed at a time when refresh would be useful. When the SDRAM bus is idle.." newline hexmask.long.byte 0x0 4.--9. 1. "REFRESH_BURST,The programmed value + 1 is the number of refresh timeouts that is allowed to accumulate before traffic is blocked and the refreshes are forced to execute. Closing pages to perform a refresh is a one-time penalty that must be paid for each.." newline bitfld.long 0x0 2. "PER_BANK_REFRESH,- 1 - Per bank refresh - 0 - All bank refresh Per bank refresh allows traffic to flow to other banks. Per bank refresh is not supported by all LPDDR2 devices but must be supported by all LPDDR3/LPDDR4 devices. Present only in designs.." "All bank refresh,Per bank refresh" group.long 0x64++0x7 line.long 0x0 "RFSHTMG,[FREQ3] Refresh Timing Register" bitfld.long 0x0 31. "T_RFC_NOM_X1_SEL,Specifies whether the RFSHTMG.t_rfc_nom_x1_x32 and RFSHCTL0.refresh_to_x1_x32 register values are x1 or x32. - 0 - x32 register values are used - 1 - x1 register values are used This applies only when per-bank refresh is enabled.." "x32 register values are used,x1 register values are used" newline hexmask.long.word 0x0 16.--27. 1. "T_RFC_NOM_X1_X32,Average time interval between refreshes per rank (Specification: 7.8us for DDR2 DDR3 and DDR4. See JEDEC specification for mDDR LPDDR2 LPDDR3 and LPDDR4). When the controller is operating in 1:1 mode set this register to.." newline bitfld.long 0x0 15. "LPDDR3_TREFBW_EN,Used only when LPDDR3 memory type is connected. Should only be changed when uMCTL2 is in reset. Specifies whether to use the tREFBW parameter (required by some LPDDR3 devices which comply with earlier versions of the LPDDR3 JEDEC.." "tREFBW parameter not used,tREFBW parameter used" newline hexmask.long.word 0x0 0.--9. 1. "T_RFC_MIN,tRFC (min): Minimum time from refresh to refresh or activate. When the controller is operating in 1:1 mode t_rfc_min must be set to RoundUp(tRFCmin/tCK). When the controller is operating in 1:2 mode t_rfc_min must be set to.." line.long 0x4 "RFSHTMG1,[FREQ3] Refresh Timing Register1" hexmask.long.byte 0x4 16.--23. 1. "T_PBR2PBR,LPDDR4:tpbR2pbR. Per-bank refresh to Per-bank refresh different bank Time. When the controller is operating in 1:1 frequency ratio mode program this to RoundUp(tpbR2pbR/tCK). When the controller is operating in 1:2 frequency ratio mode.." repeat 4. (list 0x3 0x4 0x6 0x7 )(list 0x0 0x4 0xC 0x10 ) group.long ($2+0xDC)++0x3 line.long 0x0 "INIT$1,[FREQ3] SDRAM Initialization Register 3" hexmask.long.word 0x0 16.--31. 1. "MR,DDR2:Indicates the value to write to MR register. Bit 8 is for DLL and the setting here is ignored. The uMCTL2 sets this bit appropriately. DDR3/DDR4: Value loaded into MR0 register. mDDR: Value to write to MR register. LPDDR2/LPDDR3/LPDDR4 - Value to.." newline hexmask.long.word 0x0 0.--15. 1. "EMR,DDR2: Indicates the value to write to EMR register. Bits 9:7 are for OCD and the setting in this register is ignored. The uMCTL2 sets those bits appropriately. DDR3/DDR4: Value to write to MR1 register Set bit 7 to 0. mDDR: Value to write to EMR.." repeat.end group.long 0xF4++0x3 line.long 0x0 "RANKCTL,[FREQ3] Rank Control Register" bitfld.long 0x0 26. "DIFF_RANK_WR_GAP_MSB,Only present for multi-rank configurations. 1-bit extension to be used when RANKCTL.diff_rank_wr_gap field needs to be set to a value greater than 0xF. Programming Mode: Quasi-dynamic Group 2" "?,bit extension to be used when RANKCTL" newline bitfld.long 0x0 24. "DIFF_RANK_RD_GAP_MSB,Only present for multi-rank configurations. 1-bit extension to be used when RANKCTL.diff_rank_rd_gap field needs to be set to a value greater than 0xF. Programming Mode: Quasi-dynamic Group 2" "?,bit extension to be used when RANKCTL" newline hexmask.long.byte 0x0 12.--15. 1. "MAX_RANK_WR,Only present for multi-rank configurations. Background: Writes to the same rank can be performed back-to-back. Writes to different ranks require additional gap dictated by the register RANKCTL.diff_rank_wr_gap. This is to avoid possible data.." newline hexmask.long.byte 0x0 8.--11. 1. "DIFF_RANK_WR_GAP,Only present for multi-rank configurations. Indicates the number of clocks of gap in data responses when performing consecutive writes to different ranks. This is used to switch the delays in the PHY to match the rank requirements. This.." newline hexmask.long.byte 0x0 4.--7. 1. "DIFF_RANK_RD_GAP,Only present for multi-rank configurations. Indicates the number of clocks of gap in data responses when performing consecutive reads to different ranks. This is used to switch the delays in the PHY to match the rank requirements. This.." newline hexmask.long.byte 0x0 0.--3. 1. "MAX_RANK_RD,Only present for multi-rank configurations. Background: Reads to the same rank can be performed back-to-back. Reads to different ranks require additional gap dictated by the register RANKCTL.diff_rank_rd_gap. This is to avoid possible data.." group.long 0x100++0x3F line.long 0x0 "DRAMTMG0,[FREQ3] SDRAM Timing Register 0" hexmask.long.byte 0x0 24.--30. 1. "WR2PRE,Specifies the minimum time between write and precharge to same bank. Specifications: WL + BL/2 + tWR = approximately 8 cycles + 15 ns = 14 clocks @400MHz and less for lower frequencies. where: - WL - Write latency - BL - Burst length. This must.." newline hexmask.long.byte 0x0 16.--21. 1. "T_FAW,tFAW - valid only when 8 or more banks(or banks x bank groups) are present. In 8-bank design at most 4 banks must be activated in a rolling window of tFAW cycles. When the controller is operating in 1:2 frequency ratio mode program this to.." newline hexmask.long.byte 0x0 8.--14. 1. "T_RAS_MAX,tRAS(max) - Specifies the maximum time between activate and precharge to same bank. This is the maximum time that a page can be kept open Minimum value of this register is 1. Zero is invalid. When the controller is operating in 1:1 frequency.." newline hexmask.long.byte 0x0 0.--5. 1. "T_RAS_MIN,tRAS(min) - Specifies the minimum time between activate and precharge to the same bank. When the controller is operating in 1:2 frequency mode 1T mode program this to tRAS(min)/2. No rounding up. When the controller is operating in 1:2.." line.long 0x4 "DRAMTMG1,[FREQ3] SDRAM Timing Register 1" hexmask.long.byte 0x4 16.--20. 1. "T_XP,tXP - Specifies the minimum time after power-down exit to any operation. For DDR3 this must be programmed to tXPDLL if slow powerdown exit is selected in MR0[12]. If C/A parity for DDR4 is used set to (tXP+PL) instead. If LPDDR4 is selected and.." newline hexmask.long.byte 0x4 8.--13. 1. "RD2PRE,tRTP - Specifies the minimum time from read to precharge of same bank. - DDR2 - tAL + BL/2 + max(tRTP 2) - 2 - DDR3 - tAL + max (tRTP 4) - DDR4 - Max of following two equations: tAL + max (tRTP 4) or RL + BL/2 - tRP (*). - mDDR - BL/2 - LPDDR2.." newline hexmask.long.byte 0x4 0.--6. 1. "T_RC,tRC - Specifies the minimum time between activates to same bank. When the controller is operating in 1:2 frequency ratio mode program this to (tRC/2) and round up to next integer value. Unit: DFI clock cycles. Programming Mode: Quasi-dynamic Group.." line.long 0x8 "DRAMTMG2,[FREQ3] SDRAM Timing Register 2" hexmask.long.byte 0x8 24.--29. 1. "WRITE_LATENCY,Set this field to WL. Indicates the Time from write command to write data on SDRAM interface. This must be set to WL. For mDDR it must be set to 1. Note that depending on the PHY if using RDIMM/LRDIMM it might be necessary to adjust the.." newline hexmask.long.byte 0x8 16.--21. 1. "READ_LATENCY,Set this field to RL. Indicates the time from read command to read data on SDRAM interface. This must be set to RL. Note that depending on the PHY if using RDIMM/LRDIMM it might be necessary to adjust the value of RL to compensate for the.." newline hexmask.long.byte 0x8 8.--13. 1. "RD2WR,DDR2/3/mDDR: RL + BL/2 + 2 - WL DDR4: RL + BL/2 + 1 + WR_PREAMBLE - WL LPDDR2/LPDDR3: RL + BL/2 + RU(tDQSCKmax/tCK) + 1 - WL LPDDR4(DQ ODT is Disabled): RL + BL/2 + RU(tDQSCKmax/tCK) + WR_PREAMBLE + RD_POSTAMBLE - WL LPDDR4(DQ ODT is Enabled): RL +.." newline hexmask.long.byte 0x8 0.--5. 1. "WR2RD,DDR4: CWL + PL + BL/2 + tWTR_L LPDDR2/3/4: WL + BL/2 + tWTR + 1 Others: CWL + BL/2 + tWTR In DDR4 minimum time from write command to read command for same bank group. In others minimum time from write command to read command. Includes time for.." line.long 0xC "DRAMTMG3,[FREQ3] SDRAM Timing Register 3" hexmask.long.word 0xC 20.--29. 1. "T_MRW,Indicates the time to wait after a mode register write or read (MRW or MRR). Present only in designs configured to support LPDDR2 LPDDR3 or LPDDR4. LPDDR2 typically requires value of 5. LPDDR3 typically requires value of 10. LPDDR4: Set this to.." newline hexmask.long.byte 0xC 12.--17. 1. "T_MRD,tMRD- Indicates the number of cycles to wait after a mode register write or read. Depending on the connected SDRAM tMRD represents: - DDR2/mDDR: Time from MRS to any command - DDR3/4: Time from MRS to MRS command - LPDDR2: not used - LPDDR3/4:.." newline hexmask.long.word 0xC 0.--9. 1. "T_MOD,tMOD - Parameter used only in DDR3 and DDR4. Indicates the number of cycles between load mode command and following non-load mode command. If C/A parity for DDR4 is used set to tMOD_PAR(tMOD+PL) instead. If CAL mode is enabled.." line.long 0x10 "DRAMTMG4,[FREQ3] SDRAM Timing Register 4" hexmask.long.byte 0x10 24.--28. 1. "T_RCD,tRCD - tAL: Indicates the minimum time from activate to read or write command to same bank. When the controller is operating in 1:2 frequency ratio mode program this to ((tRCD - tAL)/2) and round it up to the next integer value. Minimum value.." newline hexmask.long.byte 0x10 16.--19. 1. "T_CCD,DDR4: tCCD_L: This is the minimum time between two reads or two writes for same bank group. Others: tCCD: This is the minimum time between two reads or two writes. When the controller is operating in 1:2 frequency ratio mode program this to.." newline hexmask.long.byte 0x10 8.--11. 1. "T_RRD,DDR4: tRRD_L: This is the minimum time between activates from bank 'a' to bank 'b' for same bank group. Others: tRRD: Minimum time between activates from bank 'a' to bank 'b' When the controller is operating in 1:2 frequency ratio mode program.." newline hexmask.long.byte 0x10 0.--4. 1. "T_RP,tRP: Indicates the minimum time from single-bank precharge to activate of same bank. When the controller is operating in 1:1 frequency ratio mode t_rp must be set to RoundUp(tRP/tCK). When the controller is operating in 1:2 frequency ratio mode.." line.long 0x14 "DRAMTMG5,[FREQ3] SDRAM Timing Register 5" hexmask.long.byte 0x14 24.--27. 1. "T_CKSRX,This is the time before self-refresh Exit that CK is maintained as a valid clock before issuing SRX. Specifies the clock stable time before SRX. Recommended settings: - mDDR - 1 - LPDDR2 - 2 - LPDDR3 - 2 - LPDDR4 - tCKCKEH - DDR2 - 1 - DDR3 -.." newline hexmask.long.byte 0x14 16.--19. 1. "T_CKSRE,This is the time after self-refresh Down Entry that CK is maintained as a valid clock. Specifies the clock disable delay after SRE. Recommended settings: - mDDR - 0 - LPDDR2 - 2 - LPDDR3 - 2 - LPDDR4 - tCKELCK - DDR2 - 1 - DDR3 - Max (10 ns 5.." newline hexmask.long.byte 0x14 8.--13. 1. "T_CKESR,Indicates the minimum CKE low width for self-refresh or self-refresh power down entry to exit timing in memory clock cycles. Recommended settings: - mDDR - tRFC - LPDDR2 - tCKESR - LPDDR3 - tCKESR - LPDDR4 - max(tCKE tSR) - DDR2 - tCKE - DDR3 -.." newline hexmask.long.byte 0x14 0.--4. 1. "T_CKE,Indicates the minimum number of cycles of CKE HIGH/LOW during power-down and self-refresh. - LPDDR2/LPDDR3 mode - Set this to the larger of tCKE or tCKESR - LPDDR4 mode - Set this to the larger of tCKE or tSR - Non-LPDDR2/non-LPDDR3/non-LPDDR4.." line.long 0x18 "DRAMTMG6,[FREQ3] SDRAM Timing Register 6" hexmask.long.byte 0x18 24.--27. 1. "T_CKDPDE,This is the time after Deep Power Down Entry that CK is maintained as a valid clock. Specifies the clock disable delay after DPDE. Recommended settings: - mDDR: 0 - LPDDR2: 2 - LPDDR3: 2 When the controller is operating in 1:2 frequency ratio.." newline hexmask.long.byte 0x18 16.--19. 1. "T_CKDPDX,This is the time before Deep Power Down Exit that CK is maintained as a valid clock before issuing DPDX. Specifies the clock stable time before DPDX. Recommended settings: - mDDR - 1 - LPDDR2 - 2 - LPDDR3 - 2 When the controller is operating in.." newline hexmask.long.byte 0x18 0.--3. 1. "T_CKCSX,This is the time before Clock Stop Exit that CK is maintained as a valid clock before issuing Clock Stop Exit. Specifies the clock stable time before next command after Clock Stop Exit. Recommended settings: - mDDR - 1 - LPDDR2 - tXP + 2 - LPDDR3.." line.long 0x1C "DRAMTMG7,[FREQ3] SDRAM Timing Register 7" hexmask.long.byte 0x1C 8.--11. 1. "T_CKPDE,This is the time after Power Down Entry that CK is maintained as a valid clock. Specifies the clock disable delay after PDE. Recommended settings: - mDDR - 0 - LPDDR2 - 2 - LPDDR3 - 2 - LPDDR4 - tCKELCK When using DDR2/3/4 SDRAM this register.." newline hexmask.long.byte 0x1C 0.--3. 1. "T_CKPDX,This is the time before Power Down Exit that CK is maintained as a valid clock before issuing PDX. Specifies the clock stable time before PDX. Recommended settings: - mDDR - 0 - LPDDR2 - 2 - LPDDR3 - 2 - LPDDR4 - tCKCKEH When using DDR2/3/4 SDRAM.." line.long 0x20 "DRAMTMG8,[FREQ3] SDRAM Timing Register 8" hexmask.long.byte 0x20 24.--30. 1. "T_XS_FAST_X32,tXS_FAST: Exit self-refresh to ZQCL ZQCS and MRS (only CL WR RTP and Geardown mode). When the controller is operating in 1:2 frequency ratio mode program this to the previous value divided by 2 and round up to next integer value. Note:.." newline hexmask.long.byte 0x20 16.--22. 1. "T_XS_ABORT_X32,tXS_ABORT: Exit self-refresh to commands not requiring a locked DLL in self-refresh Abort. When the controller is operating in 1:2 frequency ratio mode program this to the previous value divided by 2 and round up to next integer value." newline hexmask.long.byte 0x20 8.--14. 1. "T_XS_DLL_X32,tXSDLL: Exit self-refresh to commands requiring a locked DLL. When the controller is operating in 1:2 frequency ratio mode program this to the previous value divided by 2 and round up to next integer value. Note: Used only for DDR2 DDR3.." newline hexmask.long.byte 0x20 0.--6. 1. "T_XS_X32,tXS: Exit self-refresh to commands not requiring a locked DLL. When the controller is operating in 1:2 frequency ratio mode program this to the previous value divided by 2 and round up to next integer value. Note: Used only for DDR2 DDR3 and.." line.long 0x24 "DRAMTMG9,[FREQ3] SDRAM Timing Register 9" bitfld.long 0x24 30. "DDR4_WR_PREAMBLE,DDR4 Write preamble mode. - 0 - 1tCK preamble - 1 - 2tCK preamble Present only with MEMC_FREQ_RATIO=2. Programming Mode: Quasi-dynamic Group 2 Group 4" "0,1" newline bitfld.long 0x24 16.--18. "T_CCD_S,tCCD_S: This is the minimum time between two reads or two writes for different bank group. For bank switching (from bank 'a' to bank 'b') the minimum time is this value + 1. When the controller is operating in 1:2 frequency ratio mode program.." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x24 8.--11. 1. "T_RRD_S,tRRD_S: This is the minimum time between activates from bank 'a' to bank 'b' for different bank group. When the controller is operating in 1:2 frequency ratio mode program this to (tRRD_S/2) and round it up to the next integer value. Present.." newline hexmask.long.byte 0x24 0.--5. 1. "WR2RD_S,CWL + PL + BL/2 + tWTR_S Minimum time from write command to read command for different bank group. Includes time for bus turnaround recovery times and all per-bank per-rank and global constraints. Present only in designs configured to support.." line.long 0x28 "DRAMTMG10,[FREQ3] SDRAM Timing Register 10" hexmask.long.byte 0x28 16.--20. 1. "T_SYNC_GEAR,Indicates the time between MRS command and the sync pulse time. This must be even number of clocks. For DDR4-2666 and DDR4-3200 this parameter is defined as tMOD(min)+4nCK tMOD(min) is greater of 24nCK or 15ns 15ns / .625ns = 24 Max value.." newline hexmask.long.byte 0x28 8.--12. 1. "T_CMD_GEAR,Indicates a sync pulse to first valid command. For DDR4-2666 and DDR4-3200 this parameter is defined as tMOD(min) tMOD(min) is greater of 24nCK or 15ns 15ns / .625ns = 24 Max value for this register is 24 When the controller is operating in.." newline bitfld.long 0x28 2.--3. "T_GEAR_SETUP,Indicates the geardown setup time. Minimum value of this register is 1. Zero is invalid. For DDR4-2666 and DDR4-3200 this parameter is defined as 2 clks When the controller is operating in 1:2 frequency ratio mode program this to.." "0,1,2,3" newline bitfld.long 0x28 0.--1. "T_GEAR_HOLD,Indicates the geardown hold time. Minimum value of this register is 1. Zero is invalid. For DDR4-2666 and DDR4-3200 this parameter is defined as 2 clks When the controller is operating in 1:2 frequency ratio mode program this to.." "0,1,2,3" line.long 0x2C "DRAMTMG11,[FREQ3] SDRAM Timing Register 11" hexmask.long.byte 0x2C 24.--30. 1. "POST_MPSM_GAP_X32,tXMPDLL: This is the minimum Exit MPSM to commands requiring a locked DLL. When the controller is operating in 1:2 frequency ratio mode program this to (tXMPDLL/2) and round it up to the next integer value. Present only in designs.." newline hexmask.long.byte 0x2C 16.--20. 1. "T_MPX_LH,tMPX_LH: This is the minimum CS_n Low hold time to CKE rising edge. When the controller is operating in 1:2 frequency ratio mode program this to RoundUp(tMPX_LH/2)+1. Present only in designs configured to support DDR4. Unit: DFI clock cycles." newline bitfld.long 0x2C 8.--9. "T_MPX_S,tMPX_S: This is the minimum time CS setup time to CKE. When the controller is operating in 1:2 frequency ratio mode program this to (tMPX_S/2) and round it up to the next integer value. Present only in designs configured to support DDR4. Unit:.." "0,1,2,3" newline hexmask.long.byte 0x2C 0.--4. 1. "T_CKMPE,tCKMPE: This is the minimum valid clock requirement after MPSM entry. Present only in designs configured to support DDR4. When the controller is operating in 1:2 frequency ratio mode divide the value calculated using the previous equation by 2.." line.long 0x30 "DRAMTMG12,[FREQ3] SDRAM Timing Register 12" hexmask.long.byte 0x30 24.--29. 1. "T_WR_MPR,This bit is used only in DDR4. Cycles between MPR Write and other command. Set this to tMOD + AL (or tMOD + PL + AL if C/A parity is also used). When the controller is operating in 1:2 frequency ratio mode program this to (tWR_MPR/2) and round.." newline bitfld.long 0x30 16.--17. "T_CMDCKE,tCMDCKE: Indicates the delay from valid command to CKE input LOW. Set this to the larger of tESCKE or tCMDCKE When the controller is operating in 1:2 frequency ratio mode program this to (max(tESCKE tCMDCKE)/2) and round it up to the next.." "0,1,2,3" newline hexmask.long.byte 0x30 0.--4. 1. "T_MRD_PDA,tMRD_PDA: This is the Mode Register Set command cycle time in PDA mode. When the controller is operating in 1:2 frequency ratio mode program this to (tMRD_PDA/2) and round it up to the next integer value. Unit: DFI clock cycles. Programming.." line.long 0x34 "DRAMTMG13,[FREQ3] SDRAM Timing Register 13" hexmask.long.byte 0x34 24.--30. 1. "ODTLOFF,LPDDR4: ODTLoff: This is the latency from CAS-2 command to ODToff reference. When the controller is operating in 1:2 frequency ratio mode program this to (ODTLoff/2) and round it up to the next integer value. Unit: DFI clock cycles. Programming.." newline hexmask.long.byte 0x34 16.--21. 1. "T_CCD_MW,LPDDR4: tCCDMW: This is the minimum time from write or masked write to masked write command for same bank. When the controller is operating in 1:2 frequency ratio mode program this to (tCCDMW/2) and round it up to the next integer value. Unit:.." newline bitfld.long 0x34 0.--2. "T_PPD,LPDDR4: tPPD: This is the minimum time from precharge to precharge command. When the controller is operating in 1:2 frequency ratio mode program this to (tPPD/2) and round it up to the next integer value. Unit: DFI clock cycles. Programming Mode:.." "?,?,?,?,tPPD: This is the minimum time from precharge to..,?,?,?" line.long 0x38 "DRAMTMG14,[FREQ3] SDRAM Timing Register 14" hexmask.long.word 0x38 0.--11. 1. "T_XSR,tXSR: This is the exit self-refresh to any command. When the controller is operating in 1:2 frequency ratio mode program this to the previous value divided by 2 and round up to next integer value. The value 0xfff is illegal for this register.." line.long 0x3C "DRAMTMG15,[FREQ3] SDRAM Timing Register 15" bitfld.long 0x3C 31. "EN_DFI_LP_T_STAB,- 1 - Enable using tSTAB when exiting DFI LP. This must be set when the PHY is stopping the clock during DFI LP to save maximum power. - 0 - Disable using tSTAB when exiting DFI LP. Programming Mode: Quasi-dynamic Group 2 Group 4" "Disable using tSTAB when exiting DFI LP,Enable using tSTAB when exiting DFI LP" newline hexmask.long.byte 0x3C 0.--7. 1. "T_STAB_X32,tSTAB: Stabilization time. It is required in the following two cases for DDR3/DDR4 RDIMM: - When exiting power saving mode if the clock is stopped after re-enabling it the clock must be stable for a time specified by tSTAB - In the case of.." group.long 0x180++0x3 line.long 0x0 "ZQCTL0,[FREQ3] ZQ Control Register 0" bitfld.long 0x0 31. "DIS_AUTO_ZQ,- 1 - Disable uMCTL2 generation of ZQCS/MPC(ZQ calibration) command. Register DBGCMD.zq_calib_short can be used instead to issue ZQ calibration request from APB module - 0 - Internally generate ZQCS/MPC(ZQ calibration) commands based on.." "Internally generate ZQCS/MPC,Disable uMCTL2 generation of ZQCS/MPC" newline bitfld.long 0x0 30. "DIS_SRX_ZQCL,- 1 - Disable issuing of ZQCL/MPC(ZQ calibration) command at self-refresh/SR-Powerdown exit. Only applicable when run in DDR3 or DDR4 or LPDDR2 or LPDDR3 or LPDDR4 mode - 0 - Enable issuing of ZQCL/MPC(ZQ calibration) command at.." "Enable issuing of ZQCL/MPC,Disable issuing of ZQCL/MPC" newline bitfld.long 0x0 29. "ZQ_RESISTOR_SHARED,- 1 - Denotes that ZQ resistor is shared between ranks. Means ZQinit/ZQCL/ZQCS/MPC(ZQ calibration) commands are sent to one rank at a time with tZQinit/tZQCL/tZQCS/tZQCAL/tZQLAT timing met between commands so that commands to different.." "ZQ resistor is not shared,Denotes that ZQ resistor is shared between ranks" newline bitfld.long 0x0 28. "DIS_MPSMX_ZQCL,- 1 - Disable issuing of ZQCL command at Maximum Power Saving Mode exit. Only applicable when run in DDR4 mode - 0 - Enable issuing of ZQCL command at Maximum Power Saving Mode exit. Only applicable when run in DDR4 mode This is only.." "Enable issuing of ZQCL command at Maximum Power..,Disable issuing of ZQCL command at Maximum Power.." newline hexmask.long.word 0x0 16.--26. 1. "T_ZQ_LONG_NOP,tZQoper for DDR3/DDR4 tZQCL for LPDDR2/LPDDR3 tZQCAL for LPDDR4: Number of DFI clock cycles of NOP required after a ZQCL (ZQ calibration long)/MPC(ZQ Start) command is issued to SDRAM. When the controller is operating in 1:2 frequency.." newline hexmask.long.word 0x0 0.--9. 1. "T_ZQ_SHORT_NOP,tZQCS for DDR3/DD4/LPDDR2/LPDDR3 tZQLAT for LPDDR4: Number of DFI clock cycles of NOP required after a ZQCS (ZQ calibration short)/MPC(ZQ Latch) command is issued to SDRAM. When the controller is operating in 1:2 frequency ratio mode.." group.long 0x190++0x7 line.long 0x0 "DFITMG0,[FREQ3] DFI Timing Register 0" hexmask.long.byte 0x0 24.--28. 1. "DFI_T_CTRL_DELAY,Specifies the number of DFI clock cycles after an assertion or de-assertion of the DFI control signals that the control signals at the PHY-DRAM interface reflect the assertion or de-assertion. If the DFI clock and the memory clock are.." newline bitfld.long 0x0 23. "DFI_RDDATA_USE_DFI_PHY_CLK,Defines whether dfi_rddata_en/dfi_rddata/dfi_rddata_valid is generated using HDR (DFI clock) or SDR (DFI PHY clock) values. Selects whether value in DFITMG0.dfi_t_rddata_en is in terms of HDR (DFI clock) or SDR (DFI PHY clock).." "Else,?" newline hexmask.long.byte 0x0 16.--22. 1. "DFI_T_RDDATA_EN,Time from the assertion of a read command on the DFI interface to the assertion of the dfi_rddata_en signal. Refer to PHY specification for correct value. This corresponds to the DFI parameter trddata_en. Note that depending on the PHY.." newline bitfld.long 0x0 15. "DFI_WRDATA_USE_DFI_PHY_CLK,Defines whether dfi_wrdata_en/dfi_wrdata/dfi_wrdata_mask is generated using HDR (DFI clock) or SDR (DFI PHY clock) values. Selects whether value in DFITMG0.dfi_tphy_wrlat is in terms of HDR (DFI clock) or SDR (DFI PHY clock).." "Else,?" newline hexmask.long.byte 0x0 8.--13. 1. "DFI_TPHY_WRDATA,Specifies the number of clock cycles between when dfi_wrdata_en is asserted to when the associated write data is driven on the dfi_wrdata signal. This corresponds to the DFI timing parameter tphy_wrdata. For more information on correct.." newline hexmask.long.byte 0x0 0.--5. 1. "DFI_TPHY_WRLAT,Write latency. Number of clocks from the write command to write data enable (dfi_wrdata_en). This corresponds to the DFI timing parameter tphy_wrlat. Refer to PHY specification for correct value.Note that depending on the PHY if using.." line.long 0x4 "DFITMG1,[FREQ3] DFI Timing Register 1" hexmask.long.byte 0x4 28.--31. 1. "DFI_T_CMD_LAT,Specifies the number of DFI PHY clock cycles between when the dfi_cs signal is asserted and when the associated command is driven. This field is used for CAL mode must be set to '0' or tCAL which matches the CAL mode register setting in.." newline bitfld.long 0x4 24.--25. "DFI_T_PARIN_LAT,Specifies the number of DFI PHY clock cycles between when the dfi_cs signal is asserted and when the associated dfi_parity_in signal is driven. Unit: DFI PHY clock cycles. Programming Mode: Quasi-dynamic Group 4" "0,1,2,3" newline hexmask.long.byte 0x4 16.--20. 1. "DFI_T_WRDATA_DELAY,Specifies the number of DFI clock cycles between when the dfi_wrdata_en signal is asserted and when the corresponding write data transfer is completed on the DRAM bus. This corresponds to the DFI timing parameter twrdata_delay. For.." newline hexmask.long.byte 0x4 8.--12. 1. "DFI_T_DRAM_CLK_DISABLE,Specifies the number of DFI clock cycles from the assertion of the dfi_dram_clk_disable signal on the DFI until the clock to the DRAM memory devices at the PHY-DRAM boundary maintains a low value. If the DFI clock and the memory.." newline hexmask.long.byte 0x4 0.--4. 1. "DFI_T_DRAM_CLK_ENABLE,Specifies the number of DFI clock cycles from the de-assertion of the dfi_dram_clk_disable signal on the DFI until the first valid rising edge of the clock to the DRAM memory devices at the PHY-DRAM boundary. If the DFI clock and.." group.long 0x1B4++0x7 line.long 0x0 "DFITMG2,[FREQ3] DFI Timing Register 2" hexmask.long.byte 0x0 8.--14. 1. "DFI_TPHY_RDCSLAT,specifies the number of DFI PHY clock cycles between when a read command is sent on the DFI control interface and when the associated dfi_rddata_cs signal is asserted. This corresponds to the DFI timing parameter tphy_rdcslat. Refer to.." newline hexmask.long.byte 0x0 0.--5. 1. "DFI_TPHY_WRCSLAT,Specifies the number of DFI PHY clock cycles between when a write command is sent on the DFI control interface and when the associated dfi_wrdata_cs signal is asserted. This corresponds to the DFI timing parameter tphy_wrcslat. For more.." line.long 0x4 "DFITMG3,[FREQ3] DFI Timing Register 3" hexmask.long.byte 0x4 0.--4. 1. "DFI_T_GEARDOWN_DELAY,The delay from dfi_geardown_en assertion to the time of the PHY being ready to receive commands. Refer to PHY specification for correct value. When the controller is operating in 1:2 frequency ratio mode program this to.." group.long 0x240++0x3 line.long 0x0 "ODTCFG,[FREQ3] ODT Configuration Register" hexmask.long.byte 0x0 24.--27. 1. "WR_ODT_HOLD,DFI PHY clock cycles to hold ODT for a write command. The minimum supported value is 2. Recommended values: DDR2: - BL8 - 0x5 (DDR2-400/533/667) 0x6 (DDR2-800) 0x7 (DDR2-1066) - BL4 - 0x3 (DDR2-400/533/667) 0x4 (DDR2-800) 0x5 (DDR2-1066).." newline hexmask.long.byte 0x0 16.--20. 1. "WR_ODT_DELAY,Indicates the delay in DFI PHY clock cycles from issuing a write command to setting ODT values associated with that command. ODT setting must remain constant for the entire time that DQS is driven by the uMCTL2. Recommended values: DDR2: -.." newline hexmask.long.byte 0x0 8.--11. 1. "RD_ODT_HOLD,DFI PHY clock cycles to hold ODT for a read command. The minimum supported value is 2. Recommended values: DDR2: - BL8 - 0x6 (not DDR2-1066) 0x7 (DDR2-1066) - BL4 - 0x4 (not DDR2-1066) 0x5 (DDR2-1066) DDR3: - BL8 - 0x6 DDR4: - BL8 - 5 +.." newline hexmask.long.byte 0x0 2.--6. 1. "RD_ODT_DELAY,Indicates the delay in DFI PHY clock cycles from issuing a read command to setting ODT values associated with that command. ODT setting must remain constant for the entire time that DQS is driven by the uMCTL2. Recommended values: DDR2: -.." tree.end tree.end tree "DDR_PHY" base ad:0xF2000000 tree "UMCTL2_REGS (uMCTL2 DDRC Registers)" group.long 0x0++0x3 line.long 0x0 "MSTR,Master Register0" bitfld.long 0x0 30.--31. "DEVICE_CONFIG,Indicates the configuration of the device used in the system. - 00 - x4 device - 01 - x8 device - 10 - x16 device - 11 - x32 device Programming Mode: Static" "x4 device,x8 device,?,?" newline bitfld.long 0x0 29. "FREQUENCY_MODE,Selects which registers are used. - 0 - Original registers - 1 - When UMCTL2_FREQUENCY_NUM=2: FREQ1 registers When UMCTL2_FREQUENCY_NUM>2: Choosen by MSTR2.target_frequency register. Programming Mode: Quasi-dynamic Group 2" "Original registers,When UMCTL2_FREQUENCY_NUM=2: FREQ1 registers" newline rbitfld.long 0x0 26.--28. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 24.--25. "ACTIVE_RANKS,Only present for multi-rank configurations. Each bit represents one rank. For two-rank configurations only bits[25:24] are present. - 1 - Populated - 0 - Unpopulated LSB is the lowest rank number. For two ranks following combinations are.." "Unpopulated,One rank,?,?" newline hexmask.long.byte 0x0 20.--23. 1. "RESERVED,Reserved" newline hexmask.long.byte 0x0 16.--19. 1. "BURST_RDWR,Indicates SDRAM burst length used: - 0001 - Burst length of 2 (only supported for mDDR) - 0010 - Burst length of 4 - 0100 - Burst length of 8 - 1000 - Burst length of 16 (only supported for mDDR LPDDR2 and LPDDR4) All other values are.." newline bitfld.long 0x0 15. "DLL_OFF_MODE,Set to: - 1 - When the uMCTL2 and DRAM has to be put in DLL-off mode for low frequency operation - 0 - To put uMCTL2 and DRAM in DLL-on mode for normal frequency operation If DDR4 CRC/parity retry is enabled.." "To put uMCTL2 and DRAM in DLL-on mode for normal..,When the uMCTL2 and DRAM has to be put in.." newline rbitfld.long 0x0 14. "RESERVED,Reserved" "0,1" newline bitfld.long 0x0 12.--13. "DATA_BUS_WIDTH,Selects proportion of DQ bus width that is used by the SDRAM. - 00 - Full DQ bus width to SDRAM - 01 - Half DQ bus width to SDRAM - 10 - Quarter DQ bus width to SDRAM - 11 - Reserved Note that half bus width mode is only supported when the.." "Full DQ bus width to SDRAM,Half DQ bus width to SDRAM,?,?" newline bitfld.long 0x0 11. "GEARDOWN_MODE,- 1 - Indicates the DRAM in geardown mode (2N) - 0 - Indicates the DRAM in normal mode (1N) This register can be changed only when the controller is in the self-refresh mode. This signal must be set the same value as MR3 bit A3. Note: -.." "Indicates the DRAM in normal mode,Indicates the DRAM in geardown mode" newline bitfld.long 0x0 10. "EN_2T_TIMING_MODE,If 1 then uMCTL2 uses 2T timing otherwise uses 1T timing. In 2T timing all command signals (except chip select) are held for 2 clocks on the SDRAM bus. Chip select is asserted on the second cycle of the command. Note: - 2T timing is.." "0,1" newline bitfld.long 0x0 9. "BURSTCHOP,When this bit is set enables burst-chop (BC4 or 8 on-the-fly) in DDR3/DDR4. Burst Chop for reads is exercised only: - In HIF configurations (UMCTL2_INCL_ARB not set) - If in full bus width mode (MSTR.data_bus_width = 00) - If.." "0,1" newline rbitfld.long 0x0 6.--8. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 5. "LPDDR4,Selects LPDDR4 SDRAM. - 1 - LPDDR4 SDRAM device in use - 0 - non-LPDDR4 device in use Present only in designs configured to support LPDDR4. Programming Mode: Static" "non-LPDDR4 device in use,LPDDR4 SDRAM device in use" newline bitfld.long 0x0 4. "DDR4,Selects DDR4 SDRAM. - 1 - DDR4 SDRAM device in use - 0 - non-DDR4 device in use Present only in designs configured to support DDR4. Programming Mode: Static" "non-DDR4 device in use,DDR4 SDRAM device in use" newline bitfld.long 0x0 3. "LPDDR3,Selects LPDDR3 SDRAM. - 1 - LPDDR3 SDRAM device in use - 0 - non-LPDDR3 device in use Present only in designs configured to support LPDDR3. Programming Mode: Static" "non-LPDDR3 device in use,LPDDR3 SDRAM device in use" newline bitfld.long 0x0 2. "LPDDR2,Selects LPDDR2 SDRAM. - 1 - LPDDR2 SDRAM device in use - 0 - non-LPDDR2 device in use Present only in designs configured to support LPDDR2. Programming Mode: Static" "non-LPDDR2 device in use,LPDDR2 SDRAM device in use" newline rbitfld.long 0x0 1. "RESERVED,Reserved" "0,1" newline bitfld.long 0x0 0. "DDR3,Selects DDR3 SDRAM. - 1 - DDR3 SDRAM device in use - 0 - non-DDR3 SDRAM device in use Present only in designs configured to support DDR3. Programming Mode: Static" "non-DDR3 SDRAM device in use,DDR3 SDRAM device in use" rgroup.long 0x4++0x3 line.long 0x0 "STAT,Operating Mode Status Register" hexmask.long.tbyte 0x0 13.--31. 1. "RESERVED,Reserved" newline bitfld.long 0x0 12. "SELFREF_CAM_NOT_EMPTY,Self-refresh with CAMs not empty. Set to 1 when self-refresh is entered but CAMs are not drained. Cleared after exiting self-refresh. Programming Mode: Static" "0,1" newline bitfld.long 0x0 10.--11. "RESERVED,Reserved" "0,1,2,3" newline bitfld.long 0x0 8.--9. "SELFREF_STATE,This indicates self-refresh or self-refresh power down state for LPDDR4. This register is used for frequency change and MRR/MRW access during self-refresh. - 00 - SDRAM is not in self-refresh - 01 - Self-refresh 1 - 10 - Self-refresh power.." "SDRAM is not in self-refresh,Self-refresh 1,?,?" newline bitfld.long 0x0 6.--7. "RESERVED,Reserved" "0,1,2,3" newline bitfld.long 0x0 4.--5. "SELFREF_TYPE,Flags if self-refresh (except LPDDR4) or SR-Powerdown (LPDDR4) is entered and if it is under automatic self-refresh control only or not. - 00 - SDRAM is not in self-refresh (except LPDDR4) or SR-Powerdown (LPDDR4). If retry is enabled by.." "SDRAM is not in self-refresh,SDRAM is in self-refresh,?,?" newline bitfld.long 0x0 3. "RESERVED,Reserved" "0,1" newline bitfld.long 0x0 0.--2. "OPERATING_MODE,This is 3-bits wide in configurations with mDDR/LPDDR2/LPDDR3/LPDDR4/DDR4 support and 2-bits in all other configurations. non-mDDR/LPDDR2/LPDDR3/LPDDR4 and non-DDR4 designs: - 00 - Init - 01 - Normal - 10 - Power-down - 11 - Self-refresh.." "Init,Normal,?,bits wide in configurations with..,?,?,?,?" group.long 0x10++0x7 line.long 0x0 "MRCTRL0,Mode Register Read/Write Control Register 0. Note: Do not enable more than one of the following fields simultaneously: - sw_init_int - pda_en - mpr_en" bitfld.long 0x0 31. "MR_WR,Setting this register bit to 1 triggers a mode register read or write operation. When the MR operation is complete the uMCTL2 automatically clears this bit. The other fields of this register must be written in a separate APB transaction before.." "0,1" newline bitfld.long 0x0 30. "PBA_MODE,Indicates whether PBA access is executed. When setting this bit to 1 along with setting pda_en to 1 uMCTL2 initiates PBA access instead of PDA access. - 0 - Per DRAM Addressability mode - 1 - Per Buffer Addressability mode The completion of PBA.." "Per DRAM Addressability mode,Per Buffer Addressability mode" newline hexmask.long.word 0x0 16.--29. 1. "RESERVED,Reserved" newline hexmask.long.byte 0x0 12.--15. 1. "MR_ADDR,Address of the mode register that is to be written to. - 0000 - MR0 - 0001 - MR1 - 0010 - MR2 - 0011 - MR3 - 0100 - MR4 - 0101 - MR5 - 0110 - MR6 - 0111 - MR7 Don't Care for LPDDR2/LPDDR3/LPDDR4 (see MRCTRL1.mr_data for mode register addressing.." newline hexmask.long.byte 0x0 6.--11. 1. "RESERVED,Reserved" newline bitfld.long 0x0 4.--5. "MR_RANK,Controls which rank is accessed by MRCTRL0.mr_wr. Normally it is desired to access all ranks so all bits must be set to 1. However for multi-rank UDIMMs/RDIMMs/LRDIMMs which implement address mirroring it might be necessary to access ranks.." "?,Select rank 0 only,Select rank 1 only,?" newline bitfld.long 0x0 3. "SW_INIT_INT,Indicates whether software intervention is allowed through MRCTRL0/MRCTRL1 before automatic SDRAM initialization routine or not. For DDR4 this bit can be used to initialize the DDR4 RCD (MR7) before automatic SDRAM initialization. For LPDDR4.." "Software intervention is not allowed,Software intervention is allowed" newline bitfld.long 0x0 2. "PDA_EN,Indicates whether the mode register operation is MRS in PDA mode or not. - 0 - MRS - 1 - MRS in Per DRAM Addressability mode Note that when pba_mode=1 PBA access is initiated instead of PDA access. Programming Mode: Dynamic" "MRS,MRS in Per DRAM Addressability mode" newline bitfld.long 0x0 1. "MPR_EN,Indicates whether the mode register operation is MRS or WR/RD for MPR (only supported for DDR4). - 0 - MRS - 1 - WR/RD for MPR Programming Mode: Dynamic" "MRS,WR/RD for MPR" newline bitfld.long 0x0 0. "MR_TYPE,Indicates whether the mode register operation is read or write. Only used for LPDDR2/LPDDR3/LPDDR4/DDR4. - 0 - Write - 1 - Read Programming Mode: Dynamic" "Write,Read" line.long 0x4 "MRCTRL1,Mode Register Read/Write Control Register 1" hexmask.long.word 0x4 18.--31. 1. "RESERVED,Reserved" newline hexmask.long.tbyte 0x4 0.--17. 1. "MR_DATA,Mode register write data for all non-LPDDR2/non-LPDDR3/non-LPDDR4 modes. For LPDDR2/LPDDR3/LPDDR4 MRCTRL1[15:0] are interpreted as: - [15:8] - MR Address - [7:0] - MR data for writes don't care for reads This is 18-bits wide in configurations.." rgroup.long 0x18++0x3 line.long 0x0 "MRSTAT,Mode Register Read/Write Status Register" hexmask.long.tbyte 0x0 9.--31. 1. "RESERVED,Reserved" newline bitfld.long 0x0 8. "PDA_DONE,The SoC might initiate a MR write operation in PDA/PBA mode only if this signal is low. This signal goes: - High when three consecutive MRS commands related to the PDA/PBA mode are issued to the SDRAM - Low when MRCTRL0.pda_en becomes 0.." "Indicates that mode register write operation..,Indicates that mode register write operation.." newline hexmask.long.byte 0x0 1.--7. 1. "RESERVED,Reserved" newline bitfld.long 0x0 0. "MR_WR_BUSY,The SoC might initiate a MR write operation only if this signal is low. This signal goes: - High in the clock after the uMCTL2 accepts the MRW/MRR request - Low when the MRW/MRR command is issued to the SDRAM It is recommended not to perform.." "Indicates that the SoC can initiate a mode..,Indicates that mode register write operation is.." group.long 0x1C++0x1F line.long 0x0 "MRCTRL2,Mode Register Read/Write Control Register 2" hexmask.long 0x0 0.--31. 1. "MR_DEVICE_SEL,Indicates the devices to be selected during the MRS that happens in PDA mode. Each bit is associated with one device. For example bit[0] corresponds to Device 0 bit[1] to Device 1 and so on. - 1 - Indicates that the MRS command must be.." line.long 0x4 "DERATEEN,Temperature Derate Enable Register" hexmask.long.tbyte 0x4 13.--31. 1. "RESERVED,Reserved" newline bitfld.long 0x4 12. "DERATE_MR4_TUF_DIS,Disables use of MR4 TUF flag (MR4[7]) bit. - 0 - Use MR4 TUF flag (MR4[7]) - 1 - Do not use MR4 TUF Flag (MR4[7]) For LPDDR4 it is recommended to set this register to 1. For LPDDR2 and LPDDR3 contact your memory vendor for.." "Use MR4 TUF flag,Do not use MR4 TUF Flag" newline rbitfld.long 0x4 11. "RESERVED,Reserved" "0,1" newline bitfld.long 0x4 8.--10. "RC_DERATE_VALUE,Derate value of tRC for LPDDR4. - 0 - Derating uses +1 - 1 - Derating uses +2 - 2 - Derating uses +3 - 3 - Derating uses +4 Present only in designs configured to support LPDDR4. The required cycles for derating can be determined by.." "Derating uses +1,Derating uses +2,Derating uses +3,Derating uses +4,?,?,?,?" newline hexmask.long.byte 0x4 4.--7. 1. "DERATE_BYTE,This bit indicates which byte of the MRR data is used for derating. The maximum valid value depends on MEMC_DRAM_TOTAL_DATA_WIDTH. Present only in designs configured to support LPDDR2/LPDDR3/LPDDR4. Programming Mode: Static" newline rbitfld.long 0x4 3. "RESERVED,Reserved" "0,1" newline bitfld.long 0x4 1.--2. "DERATE_VALUE,Derate value. - 0 - Derating uses +1 - 1 - Derating uses +2 Present only in designs configured to support LPDDR2/LPDDR3/LPDDR4. Set to 0 for all LPDDR2 speed grades as derating value of +1.875 ns is less than a core_ddrc_core_clk period. For.." "Derating uses +1,Derating uses +2,?,?" newline bitfld.long 0x4 0. "DERATE_ENABLE,Enables derating. - 0 - Timing parameter derating is disabled - 1 - Timing parameter derating is enabled using MR4 read value Present only in designs configured to support LPDDR2/LPDDR3/LPDDR4. This field must be set to '0' for.." "Timing parameter derating is disabled,Timing parameter derating is enabled using MR4.." line.long 0x8 "DERATEINT,Temperature Derate Interval Register" hexmask.long 0x8 0.--31. 1. "MR4_READ_INTERVAL,Interval between two MR4 reads used to derate the timing parameters. Present only in designs configured to support LPDDR2/LPDDR3/LPDDR4. This register must not be set to zero. Unit: DFI clock cycles. Programming Mode: Static" line.long 0xC "MSTR2,Master Register2" hexmask.long 0xC 2.--31. 1. "RESERVED,Reserved" newline bitfld.long 0xC 0.--1. "TARGET_FREQUENCY,If MSTR.frequency_mode = 1 this field specifies the target frequency. - 0 - Frequency 0/Normal - 1 - Frequency 1/FREQ1 - 2 - Frequency 2/FREQ2 - 3 - Frequency 3/FREQ3 If MSTR.frequency_mode=0 this field is ignored. Note: If the target.." "Frequency 0/Normal,Frequency 1/FREQ1,Frequency 2/FREQ2,Frequency 3/FREQ3" line.long 0x10 "DERATECTL,Temperature Derate Control Register" hexmask.long 0x10 3.--31. 1. "RESERVED,Reserved" newline bitfld.long 0x10 2. "DERATE_TEMP_LIMIT_INTR_FORCE,Interrupt force bit for derate_temp_limit_intr. Setting this field to 1 causes the derate_temp_limit_intr output pin to be asserted. At the end of the interrupt force operation the uMCTL2 automatically clears this bit." "0,1" newline bitfld.long 0x10 1. "DERATE_TEMP_LIMIT_INTR_CLR,Interrupt clear bit for derate_temp_limit_intr. At the end of the interrupt clear operation the uMCTL2 automatically clears this bit. Programming Mode: Dynamic" "0,1" newline bitfld.long 0x10 0. "DERATE_TEMP_LIMIT_INTR_EN,Interrupt enable bit for derate_temp_limit_intr output pin. - 1 - Enabled - 0 - Disabled Programming Mode: Dynamic" "Disabled,Enabled" line.long 0x14 "PWRCTL,Low Power Control Register" hexmask.long.tbyte 0x14 9.--31. 1. "RESERVED,Reserved" newline bitfld.long 0x14 8. "LPDDR4_SR_ALLOWED,Indicates whether transition from SR-PD to SR and back to SR-PD is allowed. This register field cannot be modified while PWRCTL.selfref_sw == 1. - 0 - SR-PD -> SR -> SR-PD not allowed - 1 - SR-PD -> SR -> SR-PD allowed Programming Mode:.." "SR-PD,SR-PD" newline bitfld.long 0x14 7. "DIS_CAM_DRAIN_SELFREF,Indicates whether skipping CAM draining is allowed when entering self-refresh. This register field cannot be modified while PWRCTL.selfref_sw == 1. - 0 - CAMs must be empty before entering SR - 1 - CAMs are not emptied before.." "CAMs must be empty before entering SR,CAMs are not emptied before entering SR" newline bitfld.long 0x14 6. "STAY_IN_SELFREF,Self-refresh state is an intermediate state to enter to self-refresh power down state or exit self-refresh power down state for LPDDR4. This register controls transition from the self-refresh state. - 1 - Prohibit transition from.." "Allow transition from self-refresh state,Prohibit transition from self-refresh state" newline bitfld.long 0x14 5. "SELFREF_SW,A value of 1 to this register causes system to move to self-refresh state immediately as long as it is not in INIT or DPD/MPSM operating_mode. This is referred to as Software Entry/Exit to self-refresh. - 1 - Software Entry to self-refresh -.." "Software Exit from self-refresh,Software Entry to self-refresh" newline bitfld.long 0x14 4. "MPSM_EN,When this bit is 1 the uMCTL2 puts the SDRAM into maximum power saving mode when the transaction store is empty. This register must be reset to '0' to bring uMCTL2 out of maximum power saving mode. Present only in designs configured to support.." "0,1" newline bitfld.long 0x14 3. "EN_DFI_DRAM_CLK_DISABLE,Enables the assertion of dfi_dram_clk_disable whenever a clock is not required by the SDRAM. If set to 0 dfi_dram_clk_disable is never asserted. Assertion of dfi_dram_clk_disable is as follows: In DDR2/DDR3 can only be asserted.." "0,1" newline bitfld.long 0x14 2. "DEEPPOWERDOWN_EN,When this bit is 1 uMCTL2 puts the SDRAM into deep power-down mode when the transaction store is empty. This register must be reset to '0' to bring uMCTL2 out of deep power-down mode. The controller performs automatic SDRAM.." "0,1" newline bitfld.long 0x14 1. "POWERDOWN_EN,If true then the uMCTL2 goes into power-down after a programmable number of cycles 'maximum idle clocks before power down' (PWRTMG.powerdown_to_x32). This register bit may be re-programmed during the course of normal operation. Programming.." "0,1" newline bitfld.long 0x14 0. "SELFREF_EN,If true then the uMCTL2 puts the SDRAM into self-refresh after a programmable number of cycles 'maximum idle clocks before self-refresh (PWRTMG.selfref_to_x32)'. This register bit may be re-programmed during the course of normal operation." "0,1" line.long 0x18 "PWRTMG,Low Power Timing Register" hexmask.long.byte 0x18 24.--31. 1. "RESERVED,Reserved" newline hexmask.long.byte 0x18 16.--23. 1. "SELFREF_TO_X32,After this many clocks of the DDRC command channel being idle the uMCTL2 automatically puts the SDRAM into self-refresh. The DDRC command channel is considered idle when there are no HIF commands outstanding. This must be enabled in the.." newline hexmask.long.byte 0x18 8.--15. 1. "T_DPD_X4096,Minimum deep power-down time. For mDDR value from the JEDEC specification is 0 as mDDR exits from deep power-down mode immediately after PWRCTL.deeppowerdown_en is de-asserted. For LPDDR2/LPDDR3 value from the JEDEC specification is 500us." newline rbitfld.long 0x18 5.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x18 0.--4. 1. "POWERDOWN_TO_X32,After this many clocks of the DDRC command channel being idle the uMCTL2 automatically puts the SDRAM into power-down. The DDRC command channel is considered idle when there are no HIF commands outstanding. This must be enabled in the.." line.long 0x1C "HWLPCTL,Hardware Low Power Control Register" hexmask.long.byte 0x1C 28.--31. 1. "RESERVED,Reserved" newline hexmask.long.word 0x1C 16.--27. 1. "HW_LP_IDLE_X32,Hardware idle period. The cactive_ddrc output is driven low if the DDRC command channel is idle for hw_lp_idle * 32 cycles if not in INIT or DPD/MPSM operating_mode. The DDRC command channel is considered idle when there are no HIF.." newline hexmask.long.word 0x1C 2.--15. 1. "RESERVED,Reserved" newline bitfld.long 0x1C 1. "HW_LP_EXIT_IDLE_EN,When this bit is programmed to 1 the cactive_in_ddrc pin of the DDRC can be used to exit from the automatic clock stop automatic power down or automatic self-refresh modes. Note it does not cause exit of self-refresh that was caused.." "0,1" newline bitfld.long 0x1C 0. "HW_LP_EN,Enable this bit for Hardware Low Power Interface. Programming Mode: Quasi-dynamic Group 2" "0,1" group.long 0x50++0x7 line.long 0x0 "RFSHCTL0,Refresh Control Register 0" hexmask.long.byte 0x0 24.--31. 1. "RESERVED,Reserved" newline hexmask.long.byte 0x0 20.--23. 1. "REFRESH_MARGIN,Threshold value in number of DFI clock cycles before the critical refresh or page timer expires. A critical refresh is to be issued before this threshold is reached. It is recommended that this not be changed from the default value.." newline rbitfld.long 0x0 17.--19. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x0 12.--16. 1. "REFRESH_TO_X1_X32,If the refresh timer (tRFCnom also known as tREFI) has expired at least once then a speculative refresh may be performed. A speculative refresh is a refresh performed at a time when refresh would be useful. When the SDRAM bus is idle.." newline rbitfld.long 0x0 10.--11. "RESERVED,Reserved" "0,1,2,3" newline hexmask.long.byte 0x0 4.--9. 1. "REFRESH_BURST,The programmed value + 1 is the number of refresh timeouts that is allowed to accumulate before traffic is blocked and the refreshes are forced to execute. Closing pages to perform a refresh is a one-time penalty that must be paid for each.." newline rbitfld.long 0x0 3. "RESERVED,Reserved" "0,1" newline bitfld.long 0x0 2. "PER_BANK_REFRESH,- 1 - Per bank refresh - 0 - All bank refresh Per bank refresh allows traffic to flow to other banks. Per bank refresh is not supported by all LPDDR2 devices but must be supported by all LPDDR3/LPDDR4 devices. Present only in designs.." "All bank refresh,Per bank refresh" newline rbitfld.long 0x0 0.--1. "RESERVED,Reserved" "0,1,2,3" line.long 0x4 "RFSHCTL1,Refresh Control Register 1" hexmask.long.byte 0x4 28.--31. 1. "RESERVED,Reserved" newline hexmask.long.word 0x4 16.--27. 1. "REFRESH_TIMER1_START_VALUE_X32,Refresh timer start for rank 1 (only present in multi-rank configurations). This is useful in staggering the refreshes to multiple ranks to help traffic to proceed. This is explained in Refresh Controls section of the.." newline hexmask.long.byte 0x4 12.--15. 1. "RESERVED,Reserved" newline hexmask.long.word 0x4 0.--11. 1. "REFRESH_TIMER0_START_VALUE_X32,Refresh timer start for rank 0 (only present in multi-rank configurations). This is useful in staggering the refreshes to multiple ranks to help traffic to proceed. This is explained in Refresh Controls section of the.." group.long 0x60++0xB line.long 0x0 "RFSHCTL3,Refresh Control Register 3" hexmask.long 0x0 7.--31. 1. "RESERVED,Reserved" newline bitfld.long 0x0 4.--6. "REFRESH_MODE,Indicates fine granularity refresh mode. - 000 - Fixed 1x (Normal mode) - 001 - Fixed 2x - 010 - Fixed 4x - 101 - Enable on the fly 2x (not supported) - 110 - Enable on the fly 4x (not supported) - Everything else - reserved Note: - Only.." "Fixed 1x,The on-the-fly modes are not supported in this..,This register field has effect only if a DDR4..,?,?,?,?,?" newline rbitfld.long 0x0 2.--3. "RESERVED,Reserved" "0,1,2,3" newline bitfld.long 0x0 1. "REFRESH_UPDATE_LEVEL,Toggle this signal (either from 0 to 1 or from 1 to 0) to indicate that the refresh registers have been updated. refresh_update_level must not be toggled when the DDRC is in reset (core_ddrc_rstn = 0). The refresh registers are.." "0,1" newline bitfld.long 0x0 0. "DIS_AUTO_REFRESH,When '1' disable auto-refresh generated by the uMCTL2. When auto-refresh is disabled the SoC must generate refreshes using the registers DBGCMD.rankn_refresh. When dis_auto_refresh transitions from 0 to 1 any pending refreshes are.." "0,1" line.long 0x4 "RFSHTMG,Refresh Timing Register" bitfld.long 0x4 31. "T_RFC_NOM_X1_SEL,Specifies whether the RFSHTMG.t_rfc_nom_x1_x32 and RFSHCTL0.refresh_to_x1_x32 register values are x1 or x32. - 0 - x32 register values are used - 1 - x1 register values are used This applies only when per-bank refresh is enabled.." "x32 register values are used,x1 register values are used" newline rbitfld.long 0x4 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline hexmask.long.word 0x4 16.--27. 1. "T_RFC_NOM_X1_X32,Average time interval between refreshes per rank (Specification: 7.8us for DDR2 DDR3 and DDR4. See JEDEC specification for mDDR LPDDR2 LPDDR3 and LPDDR4). When the controller is operating in 1:1 mode set this register to.." newline bitfld.long 0x4 15. "LPDDR3_TREFBW_EN,Used only when LPDDR3 memory type is connected. Should only be changed when uMCTL2 is in reset. Specifies whether to use the tREFBW parameter (required by some LPDDR3 devices which comply with earlier versions of the LPDDR3 JEDEC.." "tREFBW parameter not used,tREFBW parameter used" newline hexmask.long.byte 0x4 10.--14. 1. "RESERVED,Reserved" newline hexmask.long.word 0x4 0.--9. 1. "T_RFC_MIN,tRFC (min): Minimum time from refresh to refresh or activate. When the controller is operating in 1:1 mode t_rfc_min must be set to RoundUp(tRFCmin/tCK). When the controller is operating in 1:2 mode t_rfc_min must be set to.." line.long 0x8 "RFSHTMG1,Refresh Timing Register1" hexmask.long.byte 0x8 24.--31. 1. "RESERVED,Reserved" newline hexmask.long.byte 0x8 16.--23. 1. "T_PBR2PBR,LPDDR4:tpbR2pbR. Per-bank refresh to Per-bank refresh different bank Time. When the controller is operating in 1:1 frequency ratio mode program this to RoundUp(tpbR2pbR/tCK). When the controller is operating in 1:2 frequency ratio mode.." newline hexmask.long.word 0x8 0.--15. 1. "RESERVED,Reserved" group.long 0x70++0x7 line.long 0x0 "ECCCFG0,ECC Configuration Register 0" bitfld.long 0x0 30.--31. "ECC_REGION_MAP_GRANU,Indicates granularity of selectable protected region. Define one region size for ECCCFG0.ecc_region_map. - 0 - 1/8 of memory spaces - 1 - 1/16 of memory spaces - 2 - 1/32 of memory spaces - 3 - 1/64 of memory spaces Programming Mode:.." "0,1,2,3" newline bitfld.long 0x0 29. "ECC_REGION_MAP_OTHER,When ECCCFG0.ecc_region_map_granu>0 there is a region which is not controlled by ecc_region_map. This register defines the region to be protected or non-protected for Inline ECC. - 0 - Non-Protected - 1 - Protected This register is.." "Non-Protected,Protected" newline rbitfld.long 0x0 27.--28. "RESERVED,Reserved" "0,1,2,3" newline bitfld.long 0x0 24.--26. "ECC_AP_ERR_THRESHOLD,Sets threshold for address parity error. ECCAPSTAT.ecc_ap_err is asserted if number of ECC errors (correctable/uncorrectable) within one burst exceeds this threshold. This register value must be less than 'Total number of ECC checks.." "0,1,2,3,4,5,6,7" newline rbitfld.long 0x0 22.--23. "RESERVED,Reserved" "0,1,2,3" newline hexmask.long.byte 0x0 16.--21. 1. "BLK_CHANNEL_IDLE_TIME_X32,Indicates the number of cycles on HIF interface with no access to protected regions which causes flush of all the block channels. In order to flush block channel uMCTL2 injects write ECC command (when there is no incoming HIF.." newline rbitfld.long 0x0 15. "RESERVED,Reserved" "0,1" newline hexmask.long.byte 0x0 8.--14. 1. "ECC_REGION_MAP,Selectable Protected Region setting. Memory space is divided to 8/16/32/64 regions which is determined by ECCCFG0.ecc_region_map_granu. Note: Highest 1/8 memory space is always ECC region. Lowest 7 regions are Selectable Protected Regions." newline bitfld.long 0x0 7. "ECC_REGION_REMAP_EN,Enables remapping ECC region feature. Only supported when inline ECC is enabled. - 0 - Disable - 1 - Enable Programming Mode: Static" "Disable,Enable" newline bitfld.long 0x0 6. "ECC_AP_EN,Enables address protection feature. Only supported when inline ECC is enabled. - 0 - Disable - 1 - Enable Programming Mode: Static" "Disable,Enable" newline rbitfld.long 0x0 5. "RESERVED,Reserved" "0,1" newline bitfld.long 0x0 4. "DIS_SCRUB,Disables ECC scrubs. Valid only when ECCCFG0.ecc_mode = 3'b100 or 3'b101 and MEMC_USE_RMW is defined. Note: Scrub is not supported in inline ECC mode and the register value is don't care. Programming Mode: Static" "0,1" newline rbitfld.long 0x0 3. "RESERVED,Reserved" "0,1" newline bitfld.long 0x0 0.--2. "ECC_MODE,ECC mode indicator. - 000 - ECC disabled - 100 - ECC enabled - SEC/DED over 1 beat - 101 - ECC enabled - Advanced ECC (Illegal value when MEMC_INLINE_ECC=1) - all other settings are reserved for future use Programming Mode: Static" "ECC disabled,?,?,?,?,?,?,?" line.long 0x4 "ECCCFG1,ECC Configuration Register 1" hexmask.long.tbyte 0x4 12.--31. 1. "RESERVED,Reserved" newline hexmask.long.byte 0x4 8.--11. 1. "ACTIVE_BLK_CHANNEL,Indicated the number of active block channels. Total number of ECC block channels are defined by MEMC_NO_OF_BLK_CHANNEL hardware parameter. This register can limit the number of available channels. For example if set to 0 only one.." newline bitfld.long 0x4 7. "BLK_CHANNEL_ACTIVE_TERM,If enabled block channel is terminated when full block write or full block read is performed (all address within block are written or read). - 0 - Disable (only for debug purpose) - 1 - Enable (default) This is debug register.." "Disable,Enable" newline rbitfld.long 0x4 6. "RESERVED,Reserved" "0,1" newline bitfld.long 0x4 5. "ECC_REGION_WASTE_LOCK,Locks the remaining waste parts of the ECC region (hole) that are not locked by ecc_region_parity_lock. - 1 - Locked; if this region is accessed error response is generated - 0 - Unlocked; this region can be accessed normally.." "Unlocked; this region can be accessed normally,Locked; if this region is accessed" newline bitfld.long 0x4 4. "ECC_REGION_PARITY_LOCK,Locks the parity section of the ECC region (hole) which is the highest system address part of the memory that stores ECC parity for protected region. - 1 - Locked; if this region is accessed error response is generated - 0 -.." "Unlocked; this region can be accessed normally,Locked; if this region is accessed" newline rbitfld.long 0x4 2.--3. "RESERVED,Reserved" "0,1,2,3" newline bitfld.long 0x4 1. "DATA_POISON_BIT,Selects whether to poison 1 or 2 bits. - if 0 -> 2-bit (uncorrectable) data poisoning - if 1 -> 1-bit (correctable) data poisoning if ECCCFG1.data_poison_en=1 Valid only when MEMC_ECC_SUPPORT==1 (SECDED ECC mode) Programming Mode:.." "?,bit" newline bitfld.long 0x4 0. "DATA_POISON_EN,Enables ECC data poisoning - introduces ECC errors on writes to address specified by the ECCPOISONADDR0/1 registers. This field must be set to 0 if ECC is disabled (ECCCFG0.ecc_mode = 0). Programming Mode: Quasi-dynamic Group 3" "0,1" rgroup.long 0x78++0x3 line.long 0x0 "ECCSTAT,SECDED ECC Status Register (Valid only in MEMC_ECC_SUPPORT==1 (SECDED ECC mode))" hexmask.long.word 0x0 17.--31. 1. "RESERVED,Reserved" newline bitfld.long 0x0 16. "ECC_UNCORRECTED_ERR,Double-bit error indicator. In sideband ECC mode 1 bit per ECC lane. When the controller is operating in 1:1 frequency ratio mode there are only two lanes so only the lower two bits are used. In inline ECC mode the register is.." "0,1" newline hexmask.long.byte 0x0 9.--15. 1. "RESERVED,Reserved" newline bitfld.long 0x0 8. "ECC_CORRECTED_ERR,Single-bit error indicator. In sideband ECC mode 1 bit per ECC lane. When the controller is operating in 1:1 frequency ratio mode there are only two lanes so only the lower two bits are used. In inline ECC mode the register is.." "0,1" newline bitfld.long 0x0 7. "RESERVED,Reserved" "0,1" newline hexmask.long.byte 0x0 0.--6. 1. "ECC_CORRECTED_BIT_NUM,Indicates the bit number corrected by single-bit ECC error. For encoding of this field see ECC section in the Architecture chapter. If more than one data lane has an error the lower data lane is selected. This register is 7 bits.." group.long 0x7C++0x3 line.long 0x0 "ECCCTL,ECC Clear Register" hexmask.long.word 0x0 19.--31. 1. "RESERVED,Reserved" newline bitfld.long 0x0 18. "ECC_AP_ERR_INTR_FORCE,Interrupt force bit for ecc_ap_err_intr. Setting this register causes the output interrupt to be asserted. The uMCTL2 automatically clears this bit. There is no interaction between functionally triggering an interrupt and forcing an.." "0,1" newline bitfld.long 0x0 17. "ECC_UNCORRECTED_ERR_INTR_FORCE,Interrupt force bit for ecc_uncorrected_err_intr. Setting this register causes the output interrupt to be asserted. The uMCTL2 automatically clears this bit. There is no interaction between functionally triggering an.." "0,1" newline bitfld.long 0x0 16. "ECC_CORRECTED_ERR_INTR_FORCE,Interrupt force bit for ecc_corrected_err_intr. Setting this register causes the output interrupt to be asserted. The uMCTL2 automatically clears this bit. There is no interaction between functionally triggering an interrupt.." "0,1" newline hexmask.long.byte 0x0 11.--15. 1. "RESERVED,Reserved" newline bitfld.long 0x0 10. "ECC_AP_ERR_INTR_EN,Interrupt enable bit for ecc_ap_err_intr. - 1 - Enabled - 0 - Disabled Programming Mode: Dynamic" "Disabled,Enabled" newline bitfld.long 0x0 9. "ECC_UNCORRECTED_ERR_INTR_EN,Interrupt enable bit for ecc_uncorrected_err_intr. - 1 - Enabled - 0 - Disabled Programming Mode: Dynamic" "Disabled,Enabled" newline bitfld.long 0x0 8. "ECC_CORRECTED_ERR_INTR_EN,Interrupt enable bit for ecc_corrected_err_intr. - 1 - Enabled - 0 - Disabled Programming Mode: Dynamic" "Disabled,Enabled" newline rbitfld.long 0x0 5.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 4. "ECC_AP_ERR_INTR_CLR,Interrupt clear bit for ecc_ap_err. If this bit is set the ECCAPSTAT.ecc_ap_err/ecc_ap_err_intr is cleared. The uMCTL2 automatically clears this bit. Programming Mode: Dynamic" "0,1" newline bitfld.long 0x0 3. "ECC_UNCORR_ERR_CNT_CLR,Setting this register bit to 1 clears the currently stored uncorrected ECC error count. The ECCERRCNT.ecc_uncorr_err_cnt register is cleared by this operation. The uMCTL2 automatically clears this bit. Programming Mode: Dynamic" "0,1" newline bitfld.long 0x0 2. "ECC_CORR_ERR_CNT_CLR,Setting this register bit to 1 clears the currently stored corrected ECC error count. The ECCERRCNT.ecc_corr_err_cnt register is cleared by this operation. The uMCTL2 automatically clears this bit. Programming Mode: Dynamic" "0,1" newline bitfld.long 0x0 1. "ECC_UNCORRECTED_ERR_CLR,Setting this register bit to 1 clears the currently stored uncorrected ECC error. The following registers are cleared: - ECCSTAT.ecc_uncorrected_err - ADVECCSTAT.advecc_uncorrected_err - ECCUSYN0 - ECCUSYN1 - ECCUSYN2 uMCTL2.." "ECCUSYN1,?" newline bitfld.long 0x0 0. "ECC_CORRECTED_ERR_CLR,Setting this register bit to 1 clears the currently stored corrected ECC error. The following registers are cleared: - ECCSTAT.ecc_corrected_err - ADVECCSTAT.advecc_corrected_err - ADVECCSTAT.advecc_num_err_symbol -.." "ECCCSYN1,ECCBITMASK2" rgroup.long 0x80++0xB line.long 0x0 "ECCERRCNT,ECC Error Counter Register" hexmask.long.word 0x0 16.--31. 1. "ECC_UNCORR_ERR_CNT,Indicates the number of uncorrectable ECC errors detected. Note that the saturation behavior of this register is different depending on the type of ECC. For advanced ECC or Inline ECC it saturates at 0xFFFF while for Side-band ECC.." newline hexmask.long.word 0x0 0.--15. 1. "ECC_CORR_ERR_CNT,Indicates the number of correctable ECC errors detected. Note that the saturation behavior of this register is different depending on the type of ECC. For advanced ECC or Inline ECC it saturates at 0xFFFF while for Side-band ECC with.." line.long 0x4 "ECCCADDR0,ECC Corrected Error Address Register 0" hexmask.long.byte 0x4 25.--31. 1. "RESERVED,Reserved" newline bitfld.long 0x4 24. "ECC_CORR_RANK,Indicates the rank number of a read resulting in a corrected ECC error. Programming Mode: Dynamic" "0,1" newline hexmask.long.byte 0x4 18.--23. 1. "RESERVED,Reserved" newline hexmask.long.tbyte 0x4 0.--17. 1. "ECC_CORR_ROW,Indicates the page/row number of a read resulting in a corrected ECC error. This is 18-bits wide in configurations with DDR4 support and 16-bits in all other configurations. Programming Mode: Dynamic" line.long 0x8 "ECCCADDR1,ECC Corrected Error Address Register 1" hexmask.long.byte 0x8 26.--31. 1. "RESERVED,Reserved" newline bitfld.long 0x8 24.--25. "ECC_CORR_BG,Indicates the bank group number of a read resulting in a corrected ECC error. Programming Mode: Dynamic" "0,1,2,3" newline hexmask.long.byte 0x8 19.--23. 1. "RESERVED,Reserved" newline bitfld.long 0x8 16.--18. "ECC_CORR_BANK,Indicates the bank number of a read resulting in a corrected ECC error. Programming Mode: Dynamic" "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x8 12.--15. 1. "RESERVED,Reserved" newline hexmask.long.word 0x8 0.--11. 1. "ECC_CORR_COL,Indicates the block number of a read resulting in a corrected ECC error (lowest bit not assigned here). Programming Mode: Dynamic" repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) rgroup.long ($2+0x8C)++0x3 line.long 0x0 "ECCCSYN$1,ECC Corrected Syndrome Register 0" hexmask.long 0x0 0.--31. 1. "ECC_CORR_SYNDROMES_31_0,Indicates the data pattern that resulted in a corrected error. For 16-bit ECC only bits [15:0] are used. Programming Mode: Dynamic" repeat.end rgroup.long 0x94++0x3 line.long 0x0 "ECCCSYN2,ECC Corrected Syndrome Register 2" hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED,Reserved" newline hexmask.long.byte 0x0 0.--7. 1. "ECC_CORR_SYNDROMES_71_64,Indicates the data pattern that resulted in a corrected error one for each ECC lane all concatenated together. This register refers to the ECC byte which is bits [71:64] for 64-bit ECC [39:32] for 32-bit ECC or [23:16] for.." repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) rgroup.long ($2+0x98)++0x3 line.long 0x0 "ECCBITMASK$1,ECC Corrected Data Bit Mask Register 0" hexmask.long 0x0 0.--31. 1. "ECC_CORR_BIT_MASK_31_0,Indicates the mask for the corrected data portion. - 1 on any bit indicates that the bit has been corrected by the ECC logic - 0 on any bit indicates that the bit has not been corrected by the ECC logic This register accumulates.." repeat.end rgroup.long 0xA0++0xB line.long 0x0 "ECCBITMASK2,ECC Corrected Data Bit Mask Register 2" hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED,Reserved" newline hexmask.long.byte 0x0 0.--7. 1. "ECC_CORR_BIT_MASK_71_64,Indicates the mask for the corrected data portion. - 1 on any bit indicates that the bit has been corrected by the ECC logic - 0 on any bit indicates that the bit has not been corrected by the ECC logic This register accumulates.." line.long 0x4 "ECCUADDR0,ECC Uncorrected Error Address Register 0" hexmask.long.byte 0x4 25.--31. 1. "RESERVED,Reserved" newline bitfld.long 0x4 24. "ECC_UNCORR_RANK,Indicates the rank number of a read resulting in an uncorrected ECC error. Programming Mode: Dynamic" "0,1" newline hexmask.long.byte 0x4 18.--23. 1. "RESERVED,Reserved" newline hexmask.long.tbyte 0x4 0.--17. 1. "ECC_UNCORR_ROW,Indicates the page/row number of a read resulting in an uncorrected ECC error. This is 18-bits wide in configurations with DDR4 support and 16-bits in all other configurations. Programming Mode: Dynamic" line.long 0x8 "ECCUADDR1,ECC Uncorrected Error Address Register 1" hexmask.long.byte 0x8 26.--31. 1. "RESERVED,Reserved" newline bitfld.long 0x8 24.--25. "ECC_UNCORR_BG,Indicates the bank group number of a read resulting in an uncorrected ECC error. Programming Mode: Dynamic" "0,1,2,3" newline hexmask.long.byte 0x8 19.--23. 1. "RESERVED,Reserved" newline bitfld.long 0x8 16.--18. "ECC_UNCORR_BANK,Indicates the bank number of a read resulting in an uncorrected ECC error. Programming Mode: Dynamic" "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x8 12.--15. 1. "RESERVED,Reserved" newline hexmask.long.word 0x8 0.--11. 1. "ECC_UNCORR_COL,Indicates the block number of a read resulting in an uncorrected ECC error (lowest bit not assigned here). Programming Mode: Dynamic" repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) rgroup.long ($2+0xAC)++0x3 line.long 0x0 "ECCUSYN$1,ECC Uncorrected Syndrome Register 0" hexmask.long 0x0 0.--31. 1. "ECC_UNCORR_SYNDROMES_31_0,Indicates the data pattern that resulted in an uncorrected error one for each ECC lane all concatenated together. For 16-bit ECC only bits [15:0] are used. Programming Mode: Dynamic" repeat.end rgroup.long 0xB4++0x3 line.long 0x0 "ECCUSYN2,ECC Uncorrected Syndrome Register 2" hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED,Reserved" newline hexmask.long.byte 0x0 0.--7. 1. "ECC_UNCORR_SYNDROMES_71_64,Indicates the data pattern that resulted in an uncorrected error one for each ECC lane all concatenated together. This register refers to the ECC byte which is bits [71:64] for 64-bit ECC [39:32] for 32-bit ECC or [23:16].." group.long 0xB8++0xF line.long 0x0 "ECCPOISONADDR0,ECC Data Poisoning Address Register 0. If a HIF write data beat matches the address specified in this register. an ECC error is introduced on that transaction (write/RMW). if ECCCFG1.data_poison_en=1." hexmask.long.byte 0x0 25.--31. 1. "RESERVED,Reserved" newline bitfld.long 0x0 24. "ECC_POISON_RANK,Indicates the rank address for ECC poisoning. Programming Mode: Static" "0,1" newline hexmask.long.word 0x0 12.--23. 1. "RESERVED,Reserved" newline hexmask.long.word 0x0 0.--11. 1. "ECC_POISON_COL,Indicates the column address for ECC poisoning. Note that this column address must be burst aligned: - In full bus width mode ecc_poison_col[2:0] must be set to 0 - In half bus width mode ecc_poison_col[3:0] must be set to 0 - In quarter.." line.long 0x4 "ECCPOISONADDR1,ECC Data Poisoning Address Register 1. If a HIF write data beat matches the address specified in this register. an ECC error is introduced on that transaction (write/RMW). if ECCCFG1.data_poison_en=1." rbitfld.long 0x4 30.--31. "RESERVED,Reserved" "0,1,2,3" newline bitfld.long 0x4 28.--29. "ECC_POISON_BG,Bank Group address for ECC poisoning. Programming Mode: Static" "0,1,2,3" newline rbitfld.long 0x4 27. "RESERVED,Reserved" "0,1" newline bitfld.long 0x4 24.--26. "ECC_POISON_BANK,Bank address for ECC poisoning. Programming Mode: Static" "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x4 18.--23. 1. "RESERVED,Reserved" newline hexmask.long.tbyte 0x4 0.--17. 1. "ECC_POISON_ROW,Row address for ECC poisoning. This is 18-bits wide in configurations with DDR4 support and 16-bits in all other configurations. Programming Mode: Static" line.long 0x8 "CRCPARCTL0,CRC Parity Control Register0. Note: Do not perform any APB access to CRCPARCTL0 within 32 pclk cycles of previous access to CRCPARCTL0. as this might lead to data loss." hexmask.long 0x8 3.--31. 1. "RESERVED,Reserved" newline bitfld.long 0x8 2. "DFI_ALERT_ERR_CNT_CLR,Indicates the clear bit for DFI alert error counter. Asserting this bit clears the DFI alert error counter CRCPARSTAT.dfi_alert_err_cnt. uMCTL2 automatically clears this bit. Programming Mode: Dynamic" "0,1" newline bitfld.long 0x8 1. "DFI_ALERT_ERR_INT_CLR,Interrupt clear bit for DFI alert error. If this bit is set the alert error interrupt on CRCPARSTAT.dfi_alert_err_int is cleared. uMCTL2 automatically clears this bit. Programming Mode: Dynamic" "0,1" newline bitfld.long 0x8 0. "DFI_ALERT_ERR_INT_EN,Interrupt enable bit for DFI alert error. If this bit is set any parity/CRC error detected on the dfi_alert_n input results in an interrupt being set on CRCPARSTAT.dfi_alert_err_int. Programming Mode: Dynamic" "0,1" line.long 0xC "CRCPARCTL1,CRC Parity Control Register1" hexmask.long.tbyte 0xC 13.--31. 1. "RESERVED,Reserved" newline bitfld.long 0xC 12. "CAPARITY_DISABLE_BEFORE_SR,If DDR4-SDRAM's CA parity is enabled by INIT6.mr5[2:0]!=0 and this register is set to 1 CA parity is automatically disabled before self-refresh entry and enabled after self-refresh exit by issuing MR5. - 1 - CA parity is.." "CA parity is not disabled before self-refresh..,CA parity is disabled before self-refresh entry" newline hexmask.long.byte 0xC 8.--11. 1. "RESERVED,Reserved" newline bitfld.long 0xC 7. "CRC_INC_DM,CRC calculation setting register. - 1 - CRC includes DM signal - 0 - CRC not includes DM signal Present only in designs configured to support DDR4. Programming Mode: Static" "CRC not includes DM signal,CRC includes DM signal" newline rbitfld.long 0xC 5.--6. "RESERVED,Reserved" "0,1,2,3" newline bitfld.long 0xC 4. "CRC_ENABLE,CRC enable Register. - 1 - Enable generation of CRC - 0 - Disable generation of CRC The setting of this register should match the CRC mode register setting in the DRAM. Programming Mode: Quasi-dynamic Group 2" "Disable generation of CRC,Enable generation of CRC" newline rbitfld.long 0xC 1.--3. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline bitfld.long 0xC 0. "PARITY_ENABLE,C/A Parity enable register. - 1 - Enable generation of C/A parity and detection of C/A parity error - 0 - Disable generation of C/A parity and disable detection of C/A parity error If RCD's parity error detection or SDRAM's parity detection.." "Disable generation of C/A parity and disable..,Enable generation of C/A parity and detection of.." rgroup.long 0xCC++0x3 line.long 0x0 "CRCPARSTAT,CRC Parity Status Register" hexmask.long.word 0x0 17.--31. 1. "RESERVED,Reserved" newline bitfld.long 0x0 16. "DFI_ALERT_ERR_INT,DFI alert error interrupt. If a parity/CRC error is detected on dfi_alert_n and the interrupt is enabled by CRCPARCTL0.dfi_alert_err_int_en this interrupt bit is set. It remains set until cleared by CRCPARCTL0.dfi_alert_err_int_clr." "0,1" newline hexmask.long.word 0x0 0.--15. 1. "DFI_ALERT_ERR_CNT,DFI alert error count. If a parity/CRC error is detected on dfi_alert_n this counter be incremented. This is independent of the setting of CRCPARCTL0.dfi_alert_err_int_en. It saturates at 0xFFFF and can be cleared by asserting.." group.long 0xD0++0xB line.long 0x0 "INIT0,SDRAM Initialization Register 0" bitfld.long 0x0 30.--31. "SKIP_DRAM_INIT,If lower bit is enabled the SDRAM initialization routine is skipped. The upper bit decides what state the controller starts up in when reset is removed. - 00 - SDRAM Initialization routine is run after power-up - 01 - SDRAM Initialization.." "SDRAM Initialization routine is run after power-up,SDRAM Initialization routine is skipped after..,?,?" newline hexmask.long.byte 0x0 26.--29. 1. "RESERVED,Reserved" newline hexmask.long.word 0x0 16.--25. 1. "POST_CKE_X1024,Indicates the number of cycles to wait after driving CKE high to start the SDRAM initialization sequence. DDR2 typically requires a 400 ns delay requiring this value to be programmed to 2 at all clock speeds. LPDDR2/LPDDR3 typically.." newline hexmask.long.byte 0x0 12.--15. 1. "RESERVED,Reserved" newline hexmask.long.word 0x0 0.--11. 1. "PRE_CKE_X1024,Indicates the number of cycles to wait after reset before driving CKE high to start the SDRAM initialization sequence. DDR2 specifications typically require this to be programmed for a delay of >= 200 us. LPDDR2/LPDDR3: tINIT1 of 100 ns.." line.long 0x4 "INIT1,SDRAM Initialization Register 1" hexmask.long.byte 0x4 25.--31. 1. "RESERVED,Reserved" newline hexmask.long.word 0x4 16.--24. 1. "DRAM_RSTN_X1024,Indicates the number of cycles to assert SDRAM reset signal during init sequence. This is only present for designs supporting DDR3 DDR4 or LPDDR4 devices. For use with a Synopsys DDR PHY this must be set to a minimum of 1. When the.." newline hexmask.long.word 0x4 4.--15. 1. "RESERVED,Reserved" newline hexmask.long.byte 0x4 0.--3. 1. "PRE_OCD_X32,Indicates the wait period before driving the OCD complete command to SDRAM. There is no known specific requirement for this; it may be set to zero. Unit: Multiples of 32 DFI clock cycles. For more information on how to program this register.." line.long 0x8 "INIT2,SDRAM Initialization Register 2" hexmask.long.word 0x8 16.--31. 1. "RESERVED,Reserved" newline hexmask.long.byte 0x8 8.--15. 1. "IDLE_AFTER_RESET_X32,Indicates the idle time after the reset command tINIT4. Present only in designs configured to support LPDDR2. When the controller is operating in 1:2 frequency ratio mode program this to JEDEC spec value divided by 2 and round it.." newline hexmask.long.byte 0x8 4.--7. 1. "RESERVED,Reserved" newline hexmask.long.byte 0x8 0.--3. 1. "MIN_STABLE_CLOCK_X1,Indicates the time to wait after the first CKE high tINIT2. Present only in designs configured to support LPDDR2/LPDDR3. LPDDR2/LPDDR3 typically requires 5 x tCK delay. When the controller is operating in 1:2 frequency ratio mode.." repeat 4. (list 0x3 0x4 0x6 0x7 )(list 0x0 0x4 0xC 0x10 ) group.long ($2+0xDC)++0x3 line.long 0x0 "INIT$1,SDRAM Initialization Register 3" hexmask.long.word 0x0 16.--31. 1. "MR,DDR2:Indicates the value to write to MR register. Bit 8 is for DLL and the setting here is ignored. The uMCTL2 sets this bit appropriately. DDR3/DDR4: Value loaded into MR0 register. mDDR: Value to write to MR register. LPDDR2/LPDDR3/LPDDR4 - Value to.." newline hexmask.long.word 0x0 0.--15. 1. "EMR,DDR2: Indicates the value to write to EMR register. Bits 9:7 are for OCD and the setting in this register is ignored. The uMCTL2 sets those bits appropriately. DDR3/DDR4: Value to write to MR1 register Set bit 7 to 0. mDDR: Value to write to EMR.." repeat.end group.long 0xE4++0x3 line.long 0x0 "INIT5,SDRAM Initialization Register 5" hexmask.long.byte 0x0 24.--31. 1. "RESERVED,Reserved" newline hexmask.long.byte 0x0 16.--23. 1. "DEV_ZQINIT_X32,ZQ initial calibration tZQINIT. Present only in designs configured to support DDR3 or DDR4 or LPDDR2/LPDDR3. DDR3 typically requires 512 SDRAM clock cycles. DDR4 requires 1024 SDRAM clock cycles. LPDDR2/LPDDR3 requires 1 us. When the.." newline hexmask.long.byte 0x0 10.--15. 1. "RESERVED,Reserved" newline hexmask.long.word 0x0 0.--9. 1. "MAX_AUTO_INIT_X1024,Indicates the maximum duration of the auto initialization tINIT5. Present only in designs configured to support LPDDR2/LPDDR3. LPDDR2/LPDDR3 typically requires 10 us. Unit: Multiples of 1024 DFI clock cycles. For more information on.." group.long 0xF0++0x7 line.long 0x0 "DIMMCTL,DIMM Control Register" hexmask.long.tbyte 0x0 15.--31. 1. "RESERVED,Reserved" newline bitfld.long 0x0 14. "RCD_B_OUTPUT_DISABLED,Disables RCD outputs to B-side DRAMs. This field is used only when the uMCTL2 disables CAL mode. This value is written to F0RC0 DA[3] before and after disabling CAL mode. It is recommended to set it to ~DIMMCTL.dimm_output_inv_en.." "Enable B outputs,Disable B outputs" newline bitfld.long 0x0 13. "RCD_A_OUTPUT_DISABLED,Disables RCD outputs to A-side DRAMs. This field is used only when the uMCTL2 disables CAL mode. This value is written to F0RC0 DA[2] before and after disabling CAL mode. It is recommended to set it to 0 except for debug. - 1 -.." "Enable A outputs,Disable A outputs" newline bitfld.long 0x0 12. "RCD_WEAK_DRIVE,Indicates the weak drive mode to be set to the RCD. This field is used only when the uMCTL2 disables CAL mode. When weak drive mode in the RCD is enabled during initialization this field must be set to 1. When RCD is not used this field.." "Disable Weak Drive mode,Enable Weak Drive mode" newline hexmask.long.byte 0x0 7.--11. 1. "RESERVED,Reserved" newline bitfld.long 0x0 6. "LRDIMM_BCOM_CMD_PROT,Protects the timing restrictions (tBCW/tMRC) between consecutive BCOM commands defined in the Data Buffer specification. When using DDR4 LRDIMM this bit must be set to 1. Otherwise this bit must be set to 0. Programming Mode: Static" "0,1" newline bitfld.long 0x0 5. "DIMM_DIS_BG_MIRRORING,Disables address mirroring for BG bits. When this is set to 1 BG0 and BG1 are NOT swapped even if Address Mirroring is enabled. This is required for DDR4 DIMMs with x16 devices. - 1 - BG0 and BG1 are NOT swapped - 0 - BG0 and BG1.." "BG0 and BG1 are swapped if address mirroring is..,BG0 and BG1 are NOT swapped" newline bitfld.long 0x0 4. "MRS_BG1_EN,Enable this field for BG1 bit of MRS command. BG1 bit of the mode register address is specified as RFU (Reserved for Future Use) and must be programmed to 0 during MRS. In case where DRAMs that do not have BG1 are attached and both the CA.." "Disabled,Enabled" newline bitfld.long 0x0 3. "MRS_A17_EN,Enable this field for A17 bit of MRS command. A17 bit of the mode register address is specified as RFU (Reserved for Future Use) and must be programmed to 0 during MRS. In case where DRAMs that do not have A17 are attached as DDR4 RDIMM/LRDIMM.." "Disabled,Enabled" newline bitfld.long 0x0 2. "DIMM_OUTPUT_INV_EN,Enables output inversion (for DDR4 RDIMM/LRDIMM implementations only). DDR4 RDIMM/LRDIMM implements the Output Inversion feature by default which means that the following address bank address and bank group bits of B-side DRAMs are.." "Do not implement output inversion for B-side DRAMs,Implement output inversion for B-side DRAMs" newline bitfld.long 0x0 1. "DIMM_ADDR_MIRR_EN,Enables address mirroring (for multi-rank UDIMM implementations and multi-rank DDR4 RDIMM/LRDIMM implementations). Some UDIMMs and DDR4 RDIMMs/LRDIMMs implement address mirroring for odd ranks which means that the following address.." "Do not implement address mirroring,For odd ranks" newline bitfld.long 0x0 0. "DIMM_STAGGER_CS_EN,Staggering enable for multi-rank accesses (for multi-rank UDIMM RDIMM and LRDIMM implementations only). This is not supported for mDDR LPDDR2 LPDDR3 or LPDDR4 SDRAMs. Note: Even if this bit is set it does not take care of software.." "Do not stagger accesses,?" line.long 0x4 "RANKCTL,Rank Control Register" hexmask.long.byte 0x4 27.--31. 1. "RESERVED,Reserved" newline bitfld.long 0x4 26. "DIFF_RANK_WR_GAP_MSB,Only present for multi-rank configurations. 1-bit extension to be used when RANKCTL.diff_rank_wr_gap field needs to be set to a value greater than 0xF. Programming Mode: Quasi-dynamic Group 2" "?,bit extension to be used when RANKCTL" newline rbitfld.long 0x4 25. "RESERVED,Reserved" "0,1" newline bitfld.long 0x4 24. "DIFF_RANK_RD_GAP_MSB,Only present for multi-rank configurations. 1-bit extension to be used when RANKCTL.diff_rank_rd_gap field needs to be set to a value greater than 0xF. Programming Mode: Quasi-dynamic Group 2" "?,bit extension to be used when RANKCTL" newline hexmask.long.byte 0x4 16.--23. 1. "RESERVED,Reserved" newline hexmask.long.byte 0x4 12.--15. 1. "MAX_RANK_WR,Only present for multi-rank configurations. Background: Writes to the same rank can be performed back-to-back. Writes to different ranks require additional gap dictated by the register RANKCTL.diff_rank_wr_gap. This is to avoid possible data.." newline hexmask.long.byte 0x4 8.--11. 1. "DIFF_RANK_WR_GAP,Only present for multi-rank configurations. Indicates the number of clocks of gap in data responses when performing consecutive writes to different ranks. This is used to switch the delays in the PHY to match the rank requirements. This.." newline hexmask.long.byte 0x4 4.--7. 1. "DIFF_RANK_RD_GAP,Only present for multi-rank configurations. Indicates the number of clocks of gap in data responses when performing consecutive reads to different ranks. This is used to switch the delays in the PHY to match the rank requirements. This.." newline hexmask.long.byte 0x4 0.--3. 1. "MAX_RANK_RD,Only present for multi-rank configurations. Background: Reads to the same rank can be performed back-to-back. Reads to different ranks require additional gap dictated by the register RANKCTL.diff_rank_rd_gap. This is to avoid possible data.." group.long 0x100++0x3F line.long 0x0 "DRAMTMG0,SDRAM Timing Register 0" rbitfld.long 0x0 31. "RESERVED,Reserved" "0,1" newline hexmask.long.byte 0x0 24.--30. 1. "WR2PRE,Specifies the minimum time between write and precharge to same bank. Specifications: WL + BL/2 + tWR = approximately 8 cycles + 15 ns = 14 clocks @400MHz and less for lower frequencies. where: - WL - Write latency - BL - Burst length. This must.." newline rbitfld.long 0x0 22.--23. "RESERVED,Reserved" "0,1,2,3" newline hexmask.long.byte 0x0 16.--21. 1. "T_FAW,tFAW - valid only when 8 or more banks(or banks x bank groups) are present. In 8-bank design at most 4 banks must be activated in a rolling window of tFAW cycles. When the controller is operating in 1:2 frequency ratio mode program this to.." newline rbitfld.long 0x0 15. "RESERVED,Reserved" "0,1" newline hexmask.long.byte 0x0 8.--14. 1. "T_RAS_MAX,tRAS(max) - Specifies the maximum time between activate and precharge to same bank. This is the maximum time that a page can be kept open Minimum value of this register is 1. Zero is invalid. When the controller is operating in 1:1 frequency.." newline rbitfld.long 0x0 6.--7. "RESERVED,Reserved" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "T_RAS_MIN,tRAS(min) - Specifies the minimum time between activate and precharge to the same bank. When the controller is operating in 1:2 frequency mode 1T mode program this to tRAS(min)/2. No rounding up. When the controller is operating in 1:2.." line.long 0x4 "DRAMTMG1,SDRAM Timing Register 1" hexmask.long.word 0x4 21.--31. 1. "RESERVED,Reserved" newline hexmask.long.byte 0x4 16.--20. 1. "T_XP,tXP - Specifies the minimum time after power-down exit to any operation. For DDR3 this must be programmed to tXPDLL if slow powerdown exit is selected in MR0[12]. If C/A parity for DDR4 is used set to (tXP+PL) instead. If LPDDR4 is selected and.." newline rbitfld.long 0x4 14.--15. "RESERVED,Reserved" "0,1,2,3" newline hexmask.long.byte 0x4 8.--13. 1. "RD2PRE,tRTP - Specifies the minimum time from read to precharge of same bank. - DDR2 - tAL + BL/2 + max(tRTP 2) - 2 - DDR3 - tAL + max (tRTP 4) - DDR4 - Max of following two equations: tAL + max (tRTP 4) or RL + BL/2 - tRP (*). - mDDR - BL/2 - LPDDR2.." newline rbitfld.long 0x4 7. "RESERVED,Reserved" "0,1" newline hexmask.long.byte 0x4 0.--6. 1. "T_RC,tRC - Specifies the minimum time between activates to same bank. When the controller is operating in 1:2 frequency ratio mode program this to (tRC/2) and round up to next integer value. Unit: DFI clock cycles. Programming Mode: Quasi-dynamic Group.." line.long 0x8 "DRAMTMG2,SDRAM Timing Register 2" rbitfld.long 0x8 30.--31. "RESERVED,Reserved" "0,1,2,3" newline hexmask.long.byte 0x8 24.--29. 1. "WRITE_LATENCY,Set this field to WL. Indicates the Time from write command to write data on SDRAM interface. This must be set to WL. For mDDR it must be set to 1. Note that depending on the PHY if using RDIMM/LRDIMM it might be necessary to adjust the.." newline rbitfld.long 0x8 22.--23. "RESERVED,Reserved" "0,1,2,3" newline hexmask.long.byte 0x8 16.--21. 1. "READ_LATENCY,Set this field to RL. Indicates the time from read command to read data on SDRAM interface. This must be set to RL. Note that depending on the PHY if using RDIMM/LRDIMM it might be necessary to adjust the value of RL to compensate for the.." newline rbitfld.long 0x8 14.--15. "RESERVED,Reserved" "0,1,2,3" newline hexmask.long.byte 0x8 8.--13. 1. "RD2WR,DDR2/3/mDDR: RL + BL/2 + 2 - WL DDR4: RL + BL/2 + 1 + WR_PREAMBLE - WL LPDDR2/LPDDR3: RL + BL/2 + RU(tDQSCKmax/tCK) + 1 - WL LPDDR4(DQ ODT is Disabled): RL + BL/2 + RU(tDQSCKmax/tCK) + WR_PREAMBLE + RD_POSTAMBLE - WL LPDDR4(DQ ODT is Enabled): RL +.." newline rbitfld.long 0x8 6.--7. "RESERVED,Reserved" "0,1,2,3" newline hexmask.long.byte 0x8 0.--5. 1. "WR2RD,DDR4: CWL + PL + BL/2 + tWTR_L LPDDR2/3/4: WL + BL/2 + tWTR + 1 Others: CWL + BL/2 + tWTR In DDR4 minimum time from write command to read command for same bank group. In others minimum time from write command to read command. Includes time for.." line.long 0xC "DRAMTMG3,SDRAM Timing Register 3" rbitfld.long 0xC 30.--31. "RESERVED,Reserved" "0,1,2,3" newline hexmask.long.word 0xC 20.--29. 1. "T_MRW,Indicates the time to wait after a mode register write or read (MRW or MRR). Present only in designs configured to support LPDDR2 LPDDR3 or LPDDR4. LPDDR2 typically requires value of 5. LPDDR3 typically requires value of 10. LPDDR4: Set this to.." newline rbitfld.long 0xC 18.--19. "RESERVED,Reserved" "0,1,2,3" newline hexmask.long.byte 0xC 12.--17. 1. "T_MRD,tMRD- Indicates the number of cycles to wait after a mode register write or read. Depending on the connected SDRAM tMRD represents: - DDR2/mDDR: Time from MRS to any command - DDR3/4: Time from MRS to MRS command - LPDDR2: not used - LPDDR3/4:.." newline rbitfld.long 0xC 10.--11. "RESERVED,Reserved" "0,1,2,3" newline hexmask.long.word 0xC 0.--9. 1. "T_MOD,tMOD - Parameter used only in DDR3 and DDR4. Indicates the number of cycles between load mode command and following non-load mode command. If C/A parity for DDR4 is used set to tMOD_PAR(tMOD+PL) instead. If CAL mode is enabled.." line.long 0x10 "DRAMTMG4,SDRAM Timing Register 4" rbitfld.long 0x10 29.--31. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x10 24.--28. 1. "T_RCD,tRCD - tAL: Indicates the minimum time from activate to read or write command to same bank. When the controller is operating in 1:2 frequency ratio mode program this to ((tRCD - tAL)/2) and round it up to the next integer value. Minimum value.." newline hexmask.long.byte 0x10 20.--23. 1. "RESERVED,Reserved" newline hexmask.long.byte 0x10 16.--19. 1. "T_CCD,DDR4: tCCD_L: This is the minimum time between two reads or two writes for same bank group. Others: tCCD: This is the minimum time between two reads or two writes. When the controller is operating in 1:2 frequency ratio mode program this to.." newline hexmask.long.byte 0x10 12.--15. 1. "RESERVED,Reserved" newline hexmask.long.byte 0x10 8.--11. 1. "T_RRD,DDR4: tRRD_L: This is the minimum time between activates from bank 'a' to bank 'b' for same bank group. Others: tRRD: Minimum time between activates from bank 'a' to bank 'b' When the controller is operating in 1:2 frequency ratio mode program.." newline rbitfld.long 0x10 5.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x10 0.--4. 1. "T_RP,tRP: Indicates the minimum time from single-bank precharge to activate of same bank. When the controller is operating in 1:1 frequency ratio mode t_rp must be set to RoundUp(tRP/tCK). When the controller is operating in 1:2 frequency ratio mode.." line.long 0x14 "DRAMTMG5,SDRAM Timing Register 5" hexmask.long.byte 0x14 28.--31. 1. "RESERVED,Reserved" newline hexmask.long.byte 0x14 24.--27. 1. "T_CKSRX,This is the time before self-refresh Exit that CK is maintained as a valid clock before issuing SRX. Specifies the clock stable time before SRX. Recommended settings: - mDDR - 1 - LPDDR2 - 2 - LPDDR3 - 2 - LPDDR4 - tCKCKEH - DDR2 - 1 - DDR3 -.." newline hexmask.long.byte 0x14 20.--23. 1. "RESERVED,Reserved" newline hexmask.long.byte 0x14 16.--19. 1. "T_CKSRE,This is the time after self-refresh Down Entry that CK is maintained as a valid clock. Specifies the clock disable delay after SRE. Recommended settings: - mDDR - 0 - LPDDR2 - 2 - LPDDR3 - 2 - LPDDR4 - tCKELCK - DDR2 - 1 - DDR3 - Max (10 ns 5.." newline rbitfld.long 0x14 14.--15. "RESERVED,Reserved" "0,1,2,3" newline hexmask.long.byte 0x14 8.--13. 1. "T_CKESR,Indicates the minimum CKE low width for self-refresh or self-refresh power down entry to exit timing in memory clock cycles. Recommended settings: - mDDR - tRFC - LPDDR2 - tCKESR - LPDDR3 - tCKESR - LPDDR4 - max(tCKE tSR) - DDR2 - tCKE - DDR3 -.." newline rbitfld.long 0x14 5.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x14 0.--4. 1. "T_CKE,Indicates the minimum number of cycles of CKE HIGH/LOW during power-down and self-refresh. - LPDDR2/LPDDR3 mode - Set this to the larger of tCKE or tCKESR - LPDDR4 mode - Set this to the larger of tCKE or tSR - Non-LPDDR2/non-LPDDR3/non-LPDDR4.." line.long 0x18 "DRAMTMG6,SDRAM Timing Register 6" hexmask.long.byte 0x18 28.--31. 1. "RESERVED,Reserved" newline hexmask.long.byte 0x18 24.--27. 1. "T_CKDPDE,This is the time after Deep Power Down Entry that CK is maintained as a valid clock. Specifies the clock disable delay after DPDE. Recommended settings: - mDDR: 0 - LPDDR2: 2 - LPDDR3: 2 When the controller is operating in 1:2 frequency ratio.." newline hexmask.long.byte 0x18 20.--23. 1. "RESERVED,Reserved" newline hexmask.long.byte 0x18 16.--19. 1. "T_CKDPDX,This is the time before Deep Power Down Exit that CK is maintained as a valid clock before issuing DPDX. Specifies the clock stable time before DPDX. Recommended settings: - mDDR - 1 - LPDDR2 - 2 - LPDDR3 - 2 When the controller is operating in.." newline hexmask.long.word 0x18 4.--15. 1. "RESERVED,Reserved" newline hexmask.long.byte 0x18 0.--3. 1. "T_CKCSX,This is the time before Clock Stop Exit that CK is maintained as a valid clock before issuing Clock Stop Exit. Specifies the clock stable time before next command after Clock Stop Exit. Recommended settings: - mDDR - 1 - LPDDR2 - tXP + 2 - LPDDR3.." line.long 0x1C "DRAMTMG7,SDRAM Timing Register 7" hexmask.long.tbyte 0x1C 12.--31. 1. "RESERVED,Reserved" newline hexmask.long.byte 0x1C 8.--11. 1. "T_CKPDE,This is the time after Power Down Entry that CK is maintained as a valid clock. Specifies the clock disable delay after PDE. Recommended settings: - mDDR - 0 - LPDDR2 - 2 - LPDDR3 - 2 - LPDDR4 - tCKELCK When using DDR2/3/4 SDRAM this register.." newline hexmask.long.byte 0x1C 4.--7. 1. "RESERVED,Reserved" newline hexmask.long.byte 0x1C 0.--3. 1. "T_CKPDX,This is the time before Power Down Exit that CK is maintained as a valid clock before issuing PDX. Specifies the clock stable time before PDX. Recommended settings: - mDDR - 0 - LPDDR2 - 2 - LPDDR3 - 2 - LPDDR4 - tCKCKEH When using DDR2/3/4 SDRAM.." line.long 0x20 "DRAMTMG8,SDRAM Timing Register 8" rbitfld.long 0x20 31. "RESERVED,Reserved" "0,1" newline hexmask.long.byte 0x20 24.--30. 1. "T_XS_FAST_X32,tXS_FAST: Exit self-refresh to ZQCL ZQCS and MRS (only CL WR RTP and Geardown mode). When the controller is operating in 1:2 frequency ratio mode program this to the previous value divided by 2 and round up to next integer value. Note:.." newline rbitfld.long 0x20 23. "RESERVED,Reserved" "0,1" newline hexmask.long.byte 0x20 16.--22. 1. "T_XS_ABORT_X32,tXS_ABORT: Exit self-refresh to commands not requiring a locked DLL in self-refresh Abort. When the controller is operating in 1:2 frequency ratio mode program this to the previous value divided by 2 and round up to next integer value." newline rbitfld.long 0x20 15. "RESERVED,Reserved" "0,1" newline hexmask.long.byte 0x20 8.--14. 1. "T_XS_DLL_X32,tXSDLL: Exit self-refresh to commands requiring a locked DLL. When the controller is operating in 1:2 frequency ratio mode program this to the previous value divided by 2 and round up to next integer value. Note: Used only for DDR2 DDR3.." newline rbitfld.long 0x20 7. "RESERVED,Reserved" "0,1" newline hexmask.long.byte 0x20 0.--6. 1. "T_XS_X32,tXS: Exit self-refresh to commands not requiring a locked DLL. When the controller is operating in 1:2 frequency ratio mode program this to the previous value divided by 2 and round up to next integer value. Note: Used only for DDR2 DDR3 and.." line.long 0x24 "DRAMTMG9,SDRAM Timing Register 9" rbitfld.long 0x24 31. "RESERVED,Reserved" "0,1" newline bitfld.long 0x24 30. "DDR4_WR_PREAMBLE,DDR4 Write preamble mode. - 0 - 1tCK preamble - 1 - 2tCK preamble Present only with MEMC_FREQ_RATIO=2. Programming Mode: Quasi-dynamic Group 2 Group 4" "0,1" newline hexmask.long.word 0x24 19.--29. 1. "RESERVED,Reserved" newline bitfld.long 0x24 16.--18. "T_CCD_S,tCCD_S: This is the minimum time between two reads or two writes for different bank group. For bank switching (from bank 'a' to bank 'b') the minimum time is this value + 1. When the controller is operating in 1:2 frequency ratio mode program.." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x24 12.--15. 1. "RESERVED,Reserved" newline hexmask.long.byte 0x24 8.--11. 1. "T_RRD_S,tRRD_S: This is the minimum time between activates from bank 'a' to bank 'b' for different bank group. When the controller is operating in 1:2 frequency ratio mode program this to (tRRD_S/2) and round it up to the next integer value. Present.." newline rbitfld.long 0x24 6.--7. "RESERVED,Reserved" "0,1,2,3" newline hexmask.long.byte 0x24 0.--5. 1. "WR2RD_S,CWL + PL + BL/2 + tWTR_S Minimum time from write command to read command for different bank group. Includes time for bus turnaround recovery times and all per-bank per-rank and global constraints. Present only in designs configured to support.." line.long 0x28 "DRAMTMG10,SDRAM Timing Register 10" hexmask.long.word 0x28 21.--31. 1. "RESERVED,Reserved" newline hexmask.long.byte 0x28 16.--20. 1. "T_SYNC_GEAR,Indicates the time between MRS command and the sync pulse time. This must be even number of clocks. For DDR4-2666 and DDR4-3200 this parameter is defined as tMOD(min)+4nCK tMOD(min) is greater of 24nCK or 15ns 15ns / .625ns = 24 Max value.." newline rbitfld.long 0x28 13.--15. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x28 8.--12. 1. "T_CMD_GEAR,Indicates a sync pulse to first valid command. For DDR4-2666 and DDR4-3200 this parameter is defined as tMOD(min) tMOD(min) is greater of 24nCK or 15ns 15ns / .625ns = 24 Max value for this register is 24 When the controller is operating in.." newline hexmask.long.byte 0x28 4.--7. 1. "RESERVED,Reserved" newline bitfld.long 0x28 2.--3. "T_GEAR_SETUP,Indicates the geardown setup time. Minimum value of this register is 1. Zero is invalid. For DDR4-2666 and DDR4-3200 this parameter is defined as 2 clks When the controller is operating in 1:2 frequency ratio mode program this to.." "0,1,2,3" newline bitfld.long 0x28 0.--1. "T_GEAR_HOLD,Indicates the geardown hold time. Minimum value of this register is 1. Zero is invalid. For DDR4-2666 and DDR4-3200 this parameter is defined as 2 clks When the controller is operating in 1:2 frequency ratio mode program this to.." "0,1,2,3" line.long 0x2C "DRAMTMG11,SDRAM Timing Register 11" rbitfld.long 0x2C 31. "RESERVED,Reserved" "0,1" newline hexmask.long.byte 0x2C 24.--30. 1. "POST_MPSM_GAP_X32,tXMPDLL: This is the minimum Exit MPSM to commands requiring a locked DLL. When the controller is operating in 1:2 frequency ratio mode program this to (tXMPDLL/2) and round it up to the next integer value. Present only in designs.." newline rbitfld.long 0x2C 21.--23. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x2C 16.--20. 1. "T_MPX_LH,tMPX_LH: This is the minimum CS_n Low hold time to CKE rising edge. When the controller is operating in 1:2 frequency ratio mode program this to RoundUp(tMPX_LH/2)+1. Present only in designs configured to support DDR4. Unit: DFI clock cycles." newline hexmask.long.byte 0x2C 10.--15. 1. "RESERVED,Reserved" newline bitfld.long 0x2C 8.--9. "T_MPX_S,tMPX_S: This is the minimum time CS setup time to CKE. When the controller is operating in 1:2 frequency ratio mode program this to (tMPX_S/2) and round it up to the next integer value. Present only in designs configured to support DDR4. Unit:.." "0,1,2,3" newline rbitfld.long 0x2C 5.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x2C 0.--4. 1. "T_CKMPE,tCKMPE: This is the minimum valid clock requirement after MPSM entry. Present only in designs configured to support DDR4. When the controller is operating in 1:2 frequency ratio mode divide the value calculated using the previous equation by 2.." line.long 0x30 "DRAMTMG12,SDRAM Timing Register 12" rbitfld.long 0x30 30.--31. "RESERVED,Reserved" "0,1,2,3" newline hexmask.long.byte 0x30 24.--29. 1. "T_WR_MPR,This bit is used only in DDR4. Cycles between MPR Write and other command. Set this to tMOD + AL (or tMOD + PL + AL if C/A parity is also used). When the controller is operating in 1:2 frequency ratio mode program this to (tWR_MPR/2) and round.." newline hexmask.long.byte 0x30 18.--23. 1. "RESERVED,Reserved" newline bitfld.long 0x30 16.--17. "T_CMDCKE,tCMDCKE: Indicates the delay from valid command to CKE input LOW. Set this to the larger of tESCKE or tCMDCKE When the controller is operating in 1:2 frequency ratio mode program this to (max(tESCKE tCMDCKE)/2) and round it up to the next.." "0,1,2,3" newline hexmask.long.word 0x30 5.--15. 1. "RESERVED,Reserved" newline hexmask.long.byte 0x30 0.--4. 1. "T_MRD_PDA,tMRD_PDA: This is the Mode Register Set command cycle time in PDA mode. When the controller is operating in 1:2 frequency ratio mode program this to (tMRD_PDA/2) and round it up to the next integer value. Unit: DFI clock cycles. Programming.." line.long 0x34 "DRAMTMG13,SDRAM Timing Register 13" rbitfld.long 0x34 31. "RESERVED,Reserved" "0,1" newline hexmask.long.byte 0x34 24.--30. 1. "ODTLOFF,LPDDR4: ODTLoff: This is the latency from CAS-2 command to ODToff reference. When the controller is operating in 1:2 frequency ratio mode program this to (ODTLoff/2) and round it up to the next integer value. Unit: DFI clock cycles. Programming.." newline rbitfld.long 0x34 22.--23. "RESERVED,Reserved" "0,1,2,3" newline hexmask.long.byte 0x34 16.--21. 1. "T_CCD_MW,LPDDR4: tCCDMW: This is the minimum time from write or masked write to masked write command for same bank. When the controller is operating in 1:2 frequency ratio mode program this to (tCCDMW/2) and round it up to the next integer value. Unit:.." newline hexmask.long.word 0x34 3.--15. 1. "RESERVED,Reserved" newline bitfld.long 0x34 0.--2. "T_PPD,LPDDR4: tPPD: This is the minimum time from precharge to precharge command. When the controller is operating in 1:2 frequency ratio mode program this to (tPPD/2) and round it up to the next integer value. Unit: DFI clock cycles. Programming Mode:.." "?,?,?,?,tPPD: This is the minimum time from precharge to..,?,?,?" line.long 0x38 "DRAMTMG14,SDRAM Timing Register 14" hexmask.long.tbyte 0x38 12.--31. 1. "RESERVED,Reserved" newline hexmask.long.word 0x38 0.--11. 1. "T_XSR,tXSR: This is the exit self-refresh to any command. When the controller is operating in 1:2 frequency ratio mode program this to the previous value divided by 2 and round up to next integer value. The value 0xfff is illegal for this register.." line.long 0x3C "DRAMTMG15,SDRAM Timing Register 15" bitfld.long 0x3C 31. "EN_DFI_LP_T_STAB,- 1 - Enable using tSTAB when exiting DFI LP. This must be set when the PHY is stopping the clock during DFI LP to save maximum power. - 0 - Disable using tSTAB when exiting DFI LP. Programming Mode: Quasi-dynamic Group 2 Group 4" "Disable using tSTAB when exiting DFI LP,Enable using tSTAB when exiting DFI LP" newline hexmask.long.tbyte 0x3C 8.--30. 1. "RESERVED,Reserved" newline hexmask.long.byte 0x3C 0.--7. 1. "T_STAB_X32,tSTAB: Stabilization time. It is required in the following two cases for DDR3/DDR4 RDIMM: - When exiting power saving mode if the clock is stopped after re-enabling it the clock must be stable for a time specified by tSTAB - In the case of.." group.long 0x180++0xB line.long 0x0 "ZQCTL0,ZQ Control Register 0" bitfld.long 0x0 31. "DIS_AUTO_ZQ,- 1 - Disable uMCTL2 generation of ZQCS/MPC(ZQ calibration) command. Register DBGCMD.zq_calib_short can be used instead to issue ZQ calibration request from APB module - 0 - Internally generate ZQCS/MPC(ZQ calibration) commands based on.." "Internally generate ZQCS/MPC,Disable uMCTL2 generation of ZQCS/MPC" newline bitfld.long 0x0 30. "DIS_SRX_ZQCL,- 1 - Disable issuing of ZQCL/MPC(ZQ calibration) command at self-refresh/SR-Powerdown exit. Only applicable when run in DDR3 or DDR4 or LPDDR2 or LPDDR3 or LPDDR4 mode - 0 - Enable issuing of ZQCL/MPC(ZQ calibration) command at.." "Enable issuing of ZQCL/MPC,Disable issuing of ZQCL/MPC" newline bitfld.long 0x0 29. "ZQ_RESISTOR_SHARED,- 1 - Denotes that ZQ resistor is shared between ranks. Means ZQinit/ZQCL/ZQCS/MPC(ZQ calibration) commands are sent to one rank at a time with tZQinit/tZQCL/tZQCS/tZQCAL/tZQLAT timing met between commands so that commands to different.." "ZQ resistor is not shared,Denotes that ZQ resistor is shared between ranks" newline bitfld.long 0x0 28. "DIS_MPSMX_ZQCL,- 1 - Disable issuing of ZQCL command at Maximum Power Saving Mode exit. Only applicable when run in DDR4 mode - 0 - Enable issuing of ZQCL command at Maximum Power Saving Mode exit. Only applicable when run in DDR4 mode This is only.." "Enable issuing of ZQCL command at Maximum Power..,Disable issuing of ZQCL command at Maximum Power.." newline rbitfld.long 0x0 27. "RESERVED,Reserved" "0,1" newline hexmask.long.word 0x0 16.--26. 1. "T_ZQ_LONG_NOP,tZQoper for DDR3/DDR4 tZQCL for LPDDR2/LPDDR3 tZQCAL for LPDDR4: Number of DFI clock cycles of NOP required after a ZQCL (ZQ calibration long)/MPC(ZQ Start) command is issued to SDRAM. When the controller is operating in 1:2 frequency.." newline hexmask.long.byte 0x0 10.--15. 1. "RESERVED,Reserved" newline hexmask.long.word 0x0 0.--9. 1. "T_ZQ_SHORT_NOP,tZQCS for DDR3/DD4/LPDDR2/LPDDR3 tZQLAT for LPDDR4: Number of DFI clock cycles of NOP required after a ZQCS (ZQ calibration short)/MPC(ZQ Latch) command is issued to SDRAM. When the controller is operating in 1:2 frequency ratio mode.." line.long 0x4 "ZQCTL1,ZQ Control Register 1" rbitfld.long 0x4 30.--31. "RESERVED,Reserved" "0,1,2,3" newline hexmask.long.word 0x4 20.--29. 1. "T_ZQ_RESET_NOP,tZQReset: Number of DFI clock cycles of NOP required after a ZQReset (ZQ calibration Reset) command is issued to SDRAM. When the controller is operating in 1:2 frequency ratio mode program this to tZQReset/2 and round it up to the next.." newline hexmask.long.tbyte 0x4 0.--19. 1. "T_ZQ_SHORT_INTERVAL_X1024,Indicates the average interval to wait between automatically issuing ZQCS (ZQ calibration short)/MPC(ZQ calibration) commands to DDR3/DDR4/LPDDR2/LPDDR3/LPDDR4 devices. Meaningless if ZQCTL0.dis_auto_zq=1. This is only present.." line.long 0x8 "ZQCTL2,ZQ Control Register 2" hexmask.long 0x8 1.--31. 1. "RESERVED,Reserved" newline bitfld.long 0x8 0. "ZQ_RESET,Setting this register bit to 1 triggers a ZQ Reset operation. When the ZQ Reset operation is complete the uMCTL2 automatically clears this bit. It is recommended NOT to set this register bit if in Init in self-refresh(except LPDDR4) or.." "0,1" rgroup.long 0x18C++0x3 line.long 0x0 "ZQSTAT,ZQ Status Register" hexmask.long 0x0 1.--31. 1. "RESERVED,Reserved" newline bitfld.long 0x0 0. "ZQ_RESET_BUSY,SoC might initiate a ZQ Reset operation only if this signal is low. This signal goes high in the clock after the uMCTL2 accepts the ZQ Reset request. It goes low when the ZQ Reset command is issued to the SDRAM and the associated NOP period.." "Indicates that the SoC can initiate a ZQ Reset..,Indicates that ZQ Reset operation is in progress" group.long 0x190++0x1B line.long 0x0 "DFITMG0,DFI Timing Register 0" rbitfld.long 0x0 29.--31. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x0 24.--28. 1. "DFI_T_CTRL_DELAY,Specifies the number of DFI clock cycles after an assertion or de-assertion of the DFI control signals that the control signals at the PHY-DRAM interface reflect the assertion or de-assertion. If the DFI clock and the memory clock are.." newline bitfld.long 0x0 23. "DFI_RDDATA_USE_DFI_PHY_CLK,Defines whether dfi_rddata_en/dfi_rddata/dfi_rddata_valid is generated using HDR (DFI clock) or SDR (DFI PHY clock) values. Selects whether value in DFITMG0.dfi_t_rddata_en is in terms of HDR (DFI clock) or SDR (DFI PHY clock).." "Else,?" newline hexmask.long.byte 0x0 16.--22. 1. "DFI_T_RDDATA_EN,Time from the assertion of a read command on the DFI interface to the assertion of the dfi_rddata_en signal. Refer to PHY specification for correct value. This corresponds to the DFI parameter trddata_en. Note that depending on the PHY.." newline bitfld.long 0x0 15. "DFI_WRDATA_USE_DFI_PHY_CLK,Defines whether dfi_wrdata_en/dfi_wrdata/dfi_wrdata_mask is generated using HDR (DFI clock) or SDR (DFI PHY clock) values. Selects whether value in DFITMG0.dfi_tphy_wrlat is in terms of HDR (DFI clock) or SDR (DFI PHY clock).." "Else,?" newline rbitfld.long 0x0 14. "RESERVED,Reserved" "0,1" newline hexmask.long.byte 0x0 8.--13. 1. "DFI_TPHY_WRDATA,Specifies the number of clock cycles between when dfi_wrdata_en is asserted to when the associated write data is driven on the dfi_wrdata signal. This corresponds to the DFI timing parameter tphy_wrdata. For more information on correct.." newline rbitfld.long 0x0 6.--7. "RESERVED,Reserved" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "DFI_TPHY_WRLAT,Write latency. Number of clocks from the write command to write data enable (dfi_wrdata_en). This corresponds to the DFI timing parameter tphy_wrlat. Refer to PHY specification for correct value.Note that depending on the PHY if using.." line.long 0x4 "DFITMG1,DFI Timing Register 1" hexmask.long.byte 0x4 28.--31. 1. "DFI_T_CMD_LAT,Specifies the number of DFI PHY clock cycles between when the dfi_cs signal is asserted and when the associated command is driven. This field is used for CAL mode must be set to '0' or tCAL which matches the CAL mode register setting in.." newline rbitfld.long 0x4 26.--27. "RESERVED,Reserved" "0,1,2,3" newline bitfld.long 0x4 24.--25. "DFI_T_PARIN_LAT,Specifies the number of DFI PHY clock cycles between when the dfi_cs signal is asserted and when the associated dfi_parity_in signal is driven. Unit: DFI PHY clock cycles. Programming Mode: Quasi-dynamic Group 4" "0,1,2,3" newline rbitfld.long 0x4 21.--23. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x4 16.--20. 1. "DFI_T_WRDATA_DELAY,Specifies the number of DFI clock cycles between when the dfi_wrdata_en signal is asserted and when the corresponding write data transfer is completed on the DRAM bus. This corresponds to the DFI timing parameter twrdata_delay. For.." newline rbitfld.long 0x4 13.--15. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x4 8.--12. 1. "DFI_T_DRAM_CLK_DISABLE,Specifies the number of DFI clock cycles from the assertion of the dfi_dram_clk_disable signal on the DFI until the clock to the DRAM memory devices at the PHY-DRAM boundary maintains a low value. If the DFI clock and the memory.." newline rbitfld.long 0x4 5.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x4 0.--4. 1. "DFI_T_DRAM_CLK_ENABLE,Specifies the number of DFI clock cycles from the de-assertion of the dfi_dram_clk_disable signal on the DFI until the first valid rising edge of the clock to the DRAM memory devices at the PHY-DRAM boundary. If the DFI clock and.." line.long 0x8 "DFILPCFG0,DFI Low Power Configuration Register 0" rbitfld.long 0x8 29.--31. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x8 24.--28. 1. "DFI_TLP_RESP,Indicates the setting in DFI clock cycles for DFI's tlp_resp time. Same value is used for both Power Down self-refresh Deep Power Down and Maximum Power Saving modes. For more information on recommended values see PHY databook Unit: DFI.." newline hexmask.long.byte 0x8 20.--23. 1. "DFI_LP_WAKEUP_DPD,Indicates the value in DFI clock cycles to drive on dfi_lp_wakeup signal when Deep Power Down mode is entered. Determines the DFI's tlp_wakeup time: - 0x0 - 16 cycles - 0x1 - 32 cycles - 0x2 - 64 cycles - 0x3 - 128 cycles - 0x4 - 256.." newline rbitfld.long 0x8 17.--19. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 16. "DFI_LP_EN_DPD,Enables DFI Low Power interface handshaking during Deep Power Down Entry/Exit. - 0 - Disabled - 1 - Enabled This is only present for designs supporting mDDR or LPDDR2/LPDDR3 devices. Programming Mode: Static" "Disabled,Enabled" newline hexmask.long.byte 0x8 12.--15. 1. "DFI_LP_WAKEUP_SR,Indicates the value in DFI clock cycles to drive on dfi_lp_wakeup signal when self-refresh mode is entered. Determines the DFI's tlp_wakeup time: - 0x0 - 16 cycles - 0x1 - 32 cycles - 0x2 - 64 cycles - 0x3 - 128 cycles - 0x4 - 256 cycles.." newline rbitfld.long 0x8 9.--11. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 8. "DFI_LP_EN_SR,Enables DFI Low Power interface handshaking during self-refresh Entry/Exit. - 0 - Disabled - 1 - Enabled Programming Mode: Static" "Disabled,Enabled" newline hexmask.long.byte 0x8 4.--7. 1. "DFI_LP_WAKEUP_PD,Indicates the value in DFI clock cycles to drive on dfi_lp_wakeup signal when Power Down mode is entered. Determines the DFI's tlp_wakeup time: - 0x0 - 16 cycles - 0x1 - 32 cycles - 0x2 - 64 cycles - 0x3 - 128 cycles - 0x4 - 256 cycles -.." newline rbitfld.long 0x8 1.--3. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 0. "DFI_LP_EN_PD,Enables DFI Low Power interface handshaking during Power Down Entry/Exit. - 0 - Disabled - 1 - Enabled Programming Mode: Static" "Disabled,Enabled" line.long 0xC "DFILPCFG1,DFI Low Power Configuration Register 1" hexmask.long.tbyte 0xC 8.--31. 1. "RESERVED,Reserved" newline hexmask.long.byte 0xC 4.--7. 1. "DFI_LP_WAKEUP_MPSM,Indicates the value in DFI clock cycles to drive on dfi_lp_wakeup signal when Maximum Power Saving Mode is entered. Determines the DFI's tlp_wakeup time: - 0x0 - 16 cycles - 0x1 - 32 cycles - 0x2 - 64 cycles - 0x3 - 128 cycles - 0x4 -.." newline rbitfld.long 0xC 1.--3. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline bitfld.long 0xC 0. "DFI_LP_EN_MPSM,Enables DFI Low Power interface handshaking during Maximum Power Saving Mode Entry/Exit. - 0 - Disabled - 1 - Enabled This is only present for designs supporting DDR4 devices. Programming Mode: Static" "Disabled,Enabled" line.long 0x10 "DFIUPD0,DFI Update Register 0" bitfld.long 0x10 31. "DIS_AUTO_CTRLUPD,When '1' disable the automatic dfi_ctrlupd_req generation by the uMCTL2. The controller must issue the dfi_ctrlupd_req signal using register DBGCMD.ctrlupd. When '0' uMCTL2 issues dfi_ctrlupd_req periodically. Programming Mode:.." "0,1" newline bitfld.long 0x10 30. "DIS_AUTO_CTRLUPD_SRX,When '1' disable the automatic dfi_ctrlupd_req generation by the uMCTL2 at self-refresh exit. When '0' uMCTL2 issues a dfi_ctrlupd_req before or after exiting self-refresh depending on DFIUPD0.ctrlupd_pre_srx. Programming Mode:.." "0,1" newline bitfld.long 0x10 29. "CTRLUPD_PRE_SRX,Selects dfi_ctrlupd_req requirements at SRX: - 0 - Send ctrlupd after SRX - 1 - Send ctrlupd before SRX If DFIUPD0.dis_auto_ctrlupd_srx=1 this register has no impact because no dfi_ctrlupd_req is issued when SRX. Programming Mode: Static" "Send ctrlupd after SRX,Send ctrlupd before SRX" newline rbitfld.long 0x10 26.--28. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline hexmask.long.word 0x10 16.--25. 1. "DFI_T_CTRLUP_MAX,Specifies the maximum number of DFI clock cycles that the dfi_ctrlupd_req signal can assert. Lowest value to assign to this variable is 0x40. Unit: DFI clock cycles. Programming Mode: Static" newline hexmask.long.byte 0x10 10.--15. 1. "RESERVED,Reserved" newline hexmask.long.word 0x10 0.--9. 1. "DFI_T_CTRLUP_MIN,Specifies the minimum number of DFI clock cycles that the dfi_ctrlupd_req signal must be asserted. The uMCTL2 expects the PHY to respond within this time. If the PHY does not respond the uMCTL2 de-asserts dfi_ctrlupd_req after.." line.long 0x14 "DFIUPD1,DFI Update Register 1" hexmask.long.byte 0x14 24.--31. 1. "RESERVED,Reserved" newline hexmask.long.byte 0x14 16.--23. 1. "DFI_T_CTRLUPD_INTERVAL_MIN_X1024,This is the minimum amount of time between uMCTL2 initiated DFI update requests (which is executed whenever the uMCTL2 is idle). Set this number higher to reduce the frequency of update requests which can have a small.." newline hexmask.long.byte 0x14 8.--15. 1. "RESERVED,Reserved" newline hexmask.long.byte 0x14 0.--7. 1. "DFI_T_CTRLUPD_INTERVAL_MAX_X1024,This is the maximum amount of time between uMCTL2 initiated DFI update requests. This timer resets with each update request; when the timer expires dfi_ctrlupd_req is sent and traffic is blocked until the dfi_ctrlupd_ackx.." line.long 0x18 "DFIUPD2,DFI Update Register 2" bitfld.long 0x18 31. "DFI_PHYUPD_EN,Enables the support for acknowledging PHY-initiated updates: - 0 - Disabled - 1 - Enabled Programming Mode: Static" "Disabled,Enabled" newline hexmask.long 0x18 0.--30. 1. "RESERVED,Reserved" group.long 0x1B0++0xB line.long 0x0 "DFIMISC,DFI Miscellaneous Control Register" hexmask.long.tbyte 0x0 13.--31. 1. "RESERVED,Reserved" newline hexmask.long.byte 0x0 8.--12. 1. "DFI_FREQUENCY,Indicates the operating frequency of the system. The number of supported frequencies and the mapping of signal values to clock frequencies are defined by the PHY. Programming Mode: Quasi-dynamic Group 1" newline bitfld.long 0x0 7. "LP_OPTIMIZED_WRITE,If this bit is 1 LPDDR4 write DQ is set to 8'hF8 if masked write with enabling DBI; otherwise that value is set to 8'hFF. Programming Mode: Quasi-dynamic Group 3" "0,1" newline bitfld.long 0x0 6. "DIS_DYN_ADR_TRI,If this bit is 1 PHY specific Dynamic Tristating which is a specific feature to certain Synopsys PHYs is disabled. If this bit is 0 a special IDLE command is issued on the DFI while dfi_cs is inactive state so that the PHY can detect.." "?,phase 0 and 1) dfi_we_n= 1" newline bitfld.long 0x0 5. "DFI_INIT_START,PHY init start request signal.When asserted it triggers the PHY init start request. Programming Mode: Quasi-dynamic Group 3" "0,1" newline bitfld.long 0x0 4. "CTL_IDLE_EN,Enables support of ctl_idle signal which is non-DFI related pin specific to certain Synopsys PHYs. For more information on ctl_idle functionality see signal description of ctl_idle signal. Programming Mode: Static" "0,1" newline rbitfld.long 0x0 3. "RESERVED,Reserved" "0,1" newline bitfld.long 0x0 2. "DFI_DATA_CS_POLARITY,Defines polarity of dfi_wrdata_cs and dfi_rddata_cs signals. - 0 - Signals are active low - 1 - Signals are active high Programming Mode: Static" "Signals are active low,Signals are active high" newline bitfld.long 0x0 1. "PHY_DBI_MODE,DBI implemented in DDRC or PHY. - 0 - DDRC implements DBI functionality - 1 - PHY implements DBI functionality Present only in designs configured to support DDR4 and LPDDR4. Programming Mode: Static" "DDRC implements DBI functionality,PHY implements DBI functionality" newline bitfld.long 0x0 0. "DFI_INIT_COMPLETE_EN,PHY initialization complete enable signal. When asserted the dfi_init_complete signal can be used to trigger SDRAM initialisation Programming Mode: Quasi-dynamic Group 3" "0,1" line.long 0x4 "DFITMG2,DFI Timing Register 2" hexmask.long.tbyte 0x4 15.--31. 1. "RESERVED,Reserved" newline hexmask.long.byte 0x4 8.--14. 1. "DFI_TPHY_RDCSLAT,specifies the number of DFI PHY clock cycles between when a read command is sent on the DFI control interface and when the associated dfi_rddata_cs signal is asserted. This corresponds to the DFI timing parameter tphy_rdcslat. Refer to.." newline rbitfld.long 0x4 6.--7. "RESERVED,Reserved" "0,1,2,3" newline hexmask.long.byte 0x4 0.--5. 1. "DFI_TPHY_WRCSLAT,Specifies the number of DFI PHY clock cycles between when a write command is sent on the DFI control interface and when the associated dfi_wrdata_cs signal is asserted. This corresponds to the DFI timing parameter tphy_wrcslat. For more.." line.long 0x8 "DFITMG3,DFI Timing Register 3" hexmask.long 0x8 5.--31. 1. "RESERVED,Reserved" newline hexmask.long.byte 0x8 0.--4. 1. "DFI_T_GEARDOWN_DELAY,The delay from dfi_geardown_en assertion to the time of the PHY being ready to receive commands. Refer to PHY specification for correct value. When the controller is operating in 1:2 frequency ratio mode program this to.." rgroup.long 0x1BC++0x3 line.long 0x0 "DFISTAT,DFI Status Register" hexmask.long 0x0 2.--31. 1. "RESERVED,Reserved" newline bitfld.long 0x0 1. "DFI_LP_ACK,Stores the value of the dfi_lp_ack input to the controller. Programming Mode: Dynamic" "0,1" newline bitfld.long 0x0 0. "DFI_INIT_COMPLETE,This a status flag register which announces when the DFI initialization has been completed. The DFI INIT triggered by dfi_init_start signal and then the dfi_init_complete flag is polled to know when the initialization is done." "0,1" group.long 0x1C0++0x7 line.long 0x0 "DBICTL,DM/DBI Control Register" hexmask.long 0x0 3.--31. 1. "RESERVED,Reserved" newline bitfld.long 0x0 2. "RD_DBI_EN,Read DBI enable signal in DDRC. - 0 - Read DBI is disabled - 1 - Read DBI is enabled This signal must be set the same value as DRAM's mode register. - DDR4 - MR5 bit A12. When x4 devices are used this signal must be set to 0 - LPDDR4 - MR3[6].." "LPDDR4,Read DBI is enabled" newline bitfld.long 0x0 1. "WR_DBI_EN,Write DBI enable signal in DDRC. - 0 - Write DBI is disabled - 1 - Write DBI is enabled This signal must be set the same value as DRAM's mode register. - DDR4 - MR5 bit A11. When x4 devices are used this signal must be set to 0 - LPDDR4 -.." "LPDDR4,Write DBI is enabled" newline bitfld.long 0x0 0. "DM_EN,Indicates the DM enable signal in DDRC. - 0 - DM is disabled - 1 - DM is enabled This signal must be set the same logical value as DRAM's mode register. - DDR4 - Set this to same value as MR5 bit A10. When x4 devices are used this signal must be.." "LPDDR4,DM is enabled" line.long 0x4 "DFIPHYMSTR,DFI PHY Master" hexmask.long 0x4 1.--31. 1. "RESERVED,Reserved" newline bitfld.long 0x4 0. "DFI_PHYMSTR_EN,Enables the PHY Master Interface: - 0 - Disabled - 1 - Enabled Programming Mode: Static" "Disabled,Enabled" group.long 0x200++0x13 line.long 0x0 "ADDRMAP0,Address Map Register 0" hexmask.long 0x0 5.--31. 1. "RESERVED,Reserved" newline hexmask.long.byte 0x0 0.--4. 1. "ADDRMAP_CS_BIT0,Selects the HIF address bit used as rank address bit 0. Valid Range: 0 to 29 and 31 Internal Base: 6 The selected HIF address bit is determined by adding the internal base to the value of this field. If unused set to 31 and then rank.." line.long 0x4 "ADDRMAP1,Address Map Register 1" hexmask.long.word 0x4 22.--31. 1. "RESERVED,Reserved" newline hexmask.long.byte 0x4 16.--21. 1. "ADDRMAP_BANK_B2,Selects the HIF address bit used as bank address bit 2. Valid Range: 0 to 31 and 63 Internal Base: 4 The selected HIF address bit is determined by adding the internal base to the value of this field. If unused set to 63 and then bank.." newline rbitfld.long 0x4 14.--15. "RESERVED,Reserved" "0,1,2,3" newline hexmask.long.byte 0x4 8.--13. 1. "ADDRMAP_BANK_B1,Selects the HIF address bits used as bank address bit 1. Valid Range: 0 to 32 and 63 Internal Base: 3 The selected HIF address bit for each of the bank address bits is determined by adding the internal base to the value of this field. If.." newline rbitfld.long 0x4 6.--7. "RESERVED,Reserved" "0,1,2,3" newline hexmask.long.byte 0x4 0.--5. 1. "ADDRMAP_BANK_B0,Selects the HIF address bits used as bank address bit 0. Valid Range: 0 to 32 and 63 Internal Base: 2 The selected HIF address bit for each of the bank address bits is determined by adding the internal base to the value of this field. If.." line.long 0x8 "ADDRMAP2,Address Map Register 2" hexmask.long.byte 0x8 28.--31. 1. "RESERVED,Reserved" newline hexmask.long.byte 0x8 24.--27. 1. "ADDRMAP_COL_B5,- Full bus width mode - Selects the HIF address bit used as column address bit 5 - Half bus width mode - Selects the HIF address bit used as column address bit 6 - Quarter bus width mode - Selects the HIF address bit used as column address.." newline hexmask.long.byte 0x8 20.--23. 1. "RESERVED,Reserved" newline hexmask.long.byte 0x8 16.--19. 1. "ADDRMAP_COL_B4,- Full bus width mode - Selects the HIF address bit used as column address bit 4 - Half bus width mode - Selects the HIF address bit used as column address bit 5 - Quarter bus width mode - Selects the HIF address bit used as column address.." newline rbitfld.long 0x8 13.--15. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x8 8.--12. 1. "ADDRMAP_COL_B3,- Full bus width mode - Selects the HIF address bit used as column address bit 3 - Half bus width mode - Selects the HIF address bit used as column address bit 4 - Quarter bus width mode - Selects the HIF address bit used as column address.." newline hexmask.long.byte 0x8 4.--7. 1. "RESERVED,Reserved" newline hexmask.long.byte 0x8 0.--3. 1. "ADDRMAP_COL_B2,- Full bus width mode - Selects the HIF address bit used as column address bit 2 - Half bus width mode - Selects the HIF address bit used as column address bit 3 - Quarter bus width mode - Selects the HIF address bit used as column address.." line.long 0xC "ADDRMAP3,Address Map Register 3" rbitfld.long 0xC 29.--31. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0xC 24.--28. 1. "ADDRMAP_COL_B9,- Full bus width mode - Selects the HIF address bit used as column address bit 9 - Half bus width mode - Selects the HIF address bit used as column address bit 11 (10 in LPDDR2/LPDDR3 mode) - Quarter bus width mode - Selects the HIF.." newline rbitfld.long 0xC 21.--23. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0xC 16.--20. 1. "ADDRMAP_COL_B8,- Full bus width mode - Selects the HIF address bit used as column address bit 8 - Half bus width mode - Selects the HIF address bit used as column address bit 9 - Quarter bus width mode - Selects the HIF address bit used as column address.." newline rbitfld.long 0xC 13.--15. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0xC 8.--12. 1. "ADDRMAP_COL_B7,- Full bus width mode - Selects the HIF address bit used as column address bit 7 - Half bus width mode - Selects the HIF address bit used as column address bit 8 - Quarter bus width mode - Selects the HIF address bit used as column address.." newline rbitfld.long 0xC 5.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0xC 0.--4. 1. "ADDRMAP_COL_B6,- Full bus width mode - Selects the HIF address bit used as column address bit 6. - Half bus width mode - Selects the HIF address bit used as column address bit 7. - Quarter bus width mode - Selects the HIF address bit used as column.." line.long 0x10 "ADDRMAP4,Address Map Register 4" bitfld.long 0x10 31. "COL_ADDR_SHIFT,The register provides a capability to map column address to lower HIF address in specific cases required by inline ECC configuration. - If it is 1 internal base of all the column address can be -2 to make mapping range of column address.." "0,1" newline hexmask.long.tbyte 0x10 13.--30. 1. "RESERVED,Reserved" newline hexmask.long.byte 0x10 8.--12. 1. "ADDRMAP_COL_B11,- Full bus width mode - Selects the HIF address bit used as column address bit 13 (11 in LPDDR2/LPDDR3 mode) - Half bus width mode - UNUSED. See later in this description for value you need to set to make it unused - Quarter bus width.." newline rbitfld.long 0x10 5.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x10 0.--4. 1. "ADDRMAP_COL_B10,- Full bus width mode: Selects the HIF address bit used as column address bit 11 (10 in LPDDR2/LPDDR3 mode) - Half bus width mode: Selects the HIF address bit used as column address bit 13 (11 in LPDDR2/LPDDR3 mode) - Quarter bus width.." repeat 3. (list 0x5 0x9 0xA )(list 0x0 0x10 0x14 ) group.long ($2+0x214)++0x3 line.long 0x0 "ADDRMAP$1,Address Map Register 5" hexmask.long.byte 0x0 28.--31. 1. "RESERVED,Reserved" newline hexmask.long.byte 0x0 24.--27. 1. "ADDRMAP_ROW_B11,Selects the HIF address bit used as row address bit 11. Valid Range: 0 to 11 and 15 Internal Base: 17 The selected HIF address bit is determined by adding the internal base to the value of this field. If unused set to 15 and then row.." newline hexmask.long.byte 0x0 20.--23. 1. "RESERVED,Reserved" newline hexmask.long.byte 0x0 16.--19. 1. "ADDRMAP_ROW_B2_10,Selects the HIF address bits used as row address bits 2 to 10. Valid Range: 0 to 11 and 15 Internal Base: 8 (for row address bit 2) 9 (for row address bit 3) 10 (for row address bit 4) and so on increasing to 16 (for row address bit.." newline hexmask.long.byte 0x0 12.--15. 1. "RESERVED,Reserved" newline hexmask.long.byte 0x0 8.--11. 1. "ADDRMAP_ROW_B1,Selects the HIF address bits used as row address bit 1. Valid Range: 0 to 11 Internal Base: 7 The selected HIF address bit for each of the row address bits is determined by adding the internal base to the value of this field. Programming.." newline hexmask.long.byte 0x0 4.--7. 1. "RESERVED,Reserved" newline hexmask.long.byte 0x0 0.--3. 1. "ADDRMAP_ROW_B0,Selects the HIF address bits used as row address bit 0. Valid Range: 0 to 11 Internal Base: 6 The selected HIF address bit for each of the row address bits is determined by adding the internal base to the value of this field. Programming.." repeat.end group.long 0x218++0xB line.long 0x0 "ADDRMAP6,Address Map Register 6" bitfld.long 0x0 31. "LPDDR3_6GB_12GB,Set this to 1 if there is an LPDDR3 SDRAM 6Gb or 12Gb device in use. - 1 - LPDDR3 SDRAM 6Gb/12Gb device in use. Every address having row[14:13]==2'b11 is considered as invalid - 0 - non-LPDDR3 6Gb/12Gb device in use. All addresses are.." "non-LPDDR3 6Gb/12Gb device in use,LPDDR3 SDRAM 6Gb/12Gb device in use" newline bitfld.long 0x0 29.--30. "LPDDR4_3GB_6GB_12GB,Indicates what type of LPDDR4 SDRAM device is in use. Here the density size is per channel. - 2'b00 - No LPDDR4 SDRAM 3Gb/6Gb/12Gb device in use. All addresses are valid - 2'b01 - LPDDR4 SDRAM 3Gb device with x16 mode in use. Every.." "No LPDDR4 SDRAM 3Gb/6Gb/12Gb device in use,LPDDR4 SDRAM 3Gb device with x16 mode in use,LPDDR4 SDRAM 6Gb device with x16 mode or 3Gb..,LPDDR4 SDRAM 12Gb device with x16 mode or 6Gb.." newline rbitfld.long 0x0 28. "RESERVED,Reserved" "0,1" newline hexmask.long.byte 0x0 24.--27. 1. "ADDRMAP_ROW_B15,Selects the HIF address bit used as row address bit 15. Valid Range: 0 to 11 and 15 Internal Base: 21 The selected HIF address bit is determined by adding the internal base to the value of this field. If unused set to 15 and then row.." newline hexmask.long.byte 0x0 20.--23. 1. "RESERVED,Reserved" newline hexmask.long.byte 0x0 16.--19. 1. "ADDRMAP_ROW_B14,Selects the HIF address bit used as row address bit 14. Valid Range: 0 to 11 and 15 Internal Base: 20 The selected HIF address bit is determined by adding the internal base to the value of this field. If unused set to 15 and then row.." newline hexmask.long.byte 0x0 12.--15. 1. "RESERVED,Reserved" newline hexmask.long.byte 0x0 8.--11. 1. "ADDRMAP_ROW_B13,Selects the HIF address bit used as row address bit 13. Valid Range: 0 to 11 and 15 Internal Base: 19 The selected HIF address bit is determined by adding the internal base to the value of this field. If unused set to 15 and then row.." newline hexmask.long.byte 0x0 4.--7. 1. "RESERVED,Reserved" newline hexmask.long.byte 0x0 0.--3. 1. "ADDRMAP_ROW_B12,Selects the HIF address bit used as row address bit 12. Valid Range: 0 to 11 and 15 Internal Base: 18 The selected HIF address bit is determined by adding the internal base to the value of this field. If unused set to 15 and then row.." line.long 0x4 "ADDRMAP7,Address Map Register 7" hexmask.long.tbyte 0x4 12.--31. 1. "RESERVED,Reserved" newline hexmask.long.byte 0x4 8.--11. 1. "ADDRMAP_ROW_B17,Selects the HIF address bit used as row address bit 17. Valid Range: 0 to 11 and 15 Internal Base: 23 The selected HIF address bit is determined by adding the internal base to the value of this field. If unused set to 15 and then row.." newline hexmask.long.byte 0x4 4.--7. 1. "RESERVED,Reserved" newline hexmask.long.byte 0x4 0.--3. 1. "ADDRMAP_ROW_B16,Selects the HIF address bit used as row address bit 16. Valid Range: 0 to 11 and 15 Internal Base: 22 The selected HIF address bit is determined by adding the internal base to the value of this field. If unused set to 15 and then row.." line.long 0x8 "ADDRMAP8,Address Map Register 8" hexmask.long.tbyte 0x8 14.--31. 1. "RESERVED,Reserved" newline hexmask.long.byte 0x8 8.--13. 1. "ADDRMAP_BG_B1,Selects the HIF address bits used as bank group address bit 1. Valid Range: 0 to 32 and 63 Internal Base: 3 The selected HIF address bit for each of the bank group address bits is determined by adding the internal base to the value of this.." newline rbitfld.long 0x8 6.--7. "RESERVED,Reserved" "0,1,2,3" newline hexmask.long.byte 0x8 0.--5. 1. "ADDRMAP_BG_B0,Selects the HIF address bits used as bank group address bit 0. Valid Range: 0 to 32 and 63 Internal Base: 2 The selected HIF address bit for each of the bank group address bits is determined by adding the internal base to the value of this.." group.long 0x22C++0x3 line.long 0x0 "ADDRMAP11,Address Map Register 11" hexmask.long 0x0 4.--31. 1. "RESERVED,Reserved" newline hexmask.long.byte 0x0 0.--3. 1. "ADDRMAP_ROW_B10,Selects the HIF address bits used as row address bit 10. Valid Range: 0 to 11 Internal Base: 16 The selected HIF address bit for each of the row address bits is determined by adding the internal base to the value of this field. This.." group.long 0x240++0x7 line.long 0x0 "ODTCFG,ODT Configuration Register" hexmask.long.byte 0x0 28.--31. 1. "RESERVED,Reserved" newline hexmask.long.byte 0x0 24.--27. 1. "WR_ODT_HOLD,DFI PHY clock cycles to hold ODT for a write command. The minimum supported value is 2. Recommended values: DDR2: - BL8 - 0x5 (DDR2-400/533/667) 0x6 (DDR2-800) 0x7 (DDR2-1066) - BL4 - 0x3 (DDR2-400/533/667) 0x4 (DDR2-800) 0x5 (DDR2-1066).." newline rbitfld.long 0x0 21.--23. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x0 16.--20. 1. "WR_ODT_DELAY,Indicates the delay in DFI PHY clock cycles from issuing a write command to setting ODT values associated with that command. ODT setting must remain constant for the entire time that DQS is driven by the uMCTL2. Recommended values: DDR2: -.." newline hexmask.long.byte 0x0 12.--15. 1. "RESERVED,Reserved" newline hexmask.long.byte 0x0 8.--11. 1. "RD_ODT_HOLD,DFI PHY clock cycles to hold ODT for a read command. The minimum supported value is 2. Recommended values: DDR2: - BL8 - 0x6 (not DDR2-1066) 0x7 (DDR2-1066) - BL4 - 0x4 (not DDR2-1066) 0x5 (DDR2-1066) DDR3: - BL8 - 0x6 DDR4: - BL8 - 5 +.." newline rbitfld.long 0x0 7. "RESERVED,Reserved" "0,1" newline hexmask.long.byte 0x0 2.--6. 1. "RD_ODT_DELAY,Indicates the delay in DFI PHY clock cycles from issuing a read command to setting ODT values associated with that command. ODT setting must remain constant for the entire time that DQS is driven by the uMCTL2. Recommended values: DDR2: -.." newline rbitfld.long 0x0 0.--1. "RESERVED,Reserved" "0,1,2,3" line.long 0x4 "ODTMAP,ODT/Rank Map Register" hexmask.long.tbyte 0x4 14.--31. 1. "RESERVED,Reserved" newline bitfld.long 0x4 12.--13. "RANK1_RD_ODT,Indicates which remote ODTs must be turned on during a read from rank 1. Each rank has a remote ODT (in the SDRAM) which can be turned on by setting the appropriate bit here. Rank 0 is controlled by the LSB; rank 1 is controlled by bit next.." "0,1,2,3" newline rbitfld.long 0x4 10.--11. "RESERVED,Reserved" "0,1,2,3" newline bitfld.long 0x4 8.--9. "RANK1_WR_ODT,Indicates which remote ODTs must be turned on during a write to rank 1. Each rank has a remote ODT (in the SDRAM) which can be turned on by setting the appropriate bit here. Rank 0 is controlled by the LSB; rank 1 is controlled by bit next.." "0,1,2,3" newline rbitfld.long 0x4 6.--7. "RESERVED,Reserved" "0,1,2,3" newline bitfld.long 0x4 4.--5. "RANK0_RD_ODT,Indicates which remote ODTs must be turned on during a read from rank 0. Each rank has a remote ODT (in the SDRAM) which can be turned on by setting the appropriate bit here. Rank 0 is controlled by the LSB; rank 1 is controlled by bit next.." "0,1,2,3" newline rbitfld.long 0x4 2.--3. "RESERVED,Reserved" "0,1,2,3" newline bitfld.long 0x4 0.--1. "RANK0_WR_ODT,Indicates which remote ODTs must be turned on during a write to rank 0. Each rank has a remote ODT (in the SDRAM) which can be turned on by setting the appropriate bit here. Rank 0 is controlled by the LSB; rank 1 is controlled by bit next.." "0,1,2,3" group.long 0x250++0x7 line.long 0x0 "SCHED,Scheduler Control Register" rbitfld.long 0x0 31. "RESERVED,Reserved" "0,1" newline hexmask.long.byte 0x0 24.--30. 1. "RDWR_IDLE_GAP,When the preferred transaction store is empty for these many clock cycles switch to the alternate transaction store if it is non-empty. The read transaction store (both high and low priority) is the default preferred transaction store and.." newline hexmask.long.byte 0x0 16.--23. 1. "GO2CRITICAL_HYSTERESIS,UNUSED. Programming Mode: Static" newline bitfld.long 0x0 15. "LPDDR4_OPT_ACT_TIMING,Optimized ACT timing control for LPDDR4. In LPDDR4 RD/WR/ACT takes 4 cycle. To stream Read/Write there are only 4 cycle space between Reads/Writes. If ACT is scheduled-out after RD/WR with 1 2 or 3 cycle gap next RD/WR may be.." "Disable this feature,Enable this feature" newline rbitfld.long 0x0 13.--14. "RESERVED,Reserved" "0,1,2,3" newline hexmask.long.byte 0x0 8.--12. 1. "LPR_NUM_ENTRIES,Number of entries in the low priority transaction store is this value + 1. (MEMC_NO_OF_ENTRY - (SCHED.lpr_num_entries + 1)) is the number of entries available for the high priority transaction store. Setting this to maximum value.." newline bitfld.long 0x0 7. "AUTOPRE_RMW,Selects behavior of hif_cmd_autopre if a RMW is received on HIF with hif_cmd_autopre=1 - 1 - Apply Autopre only for write part of RMW - 0 - Apply Autopre for both read and write parts of RMW Programming Mode: Static" "Apply Autopre for both read and write parts of RMW,Apply Autopre only for write part of RMW" newline hexmask.long.byte 0x0 3.--6. 1. "RESERVED,Reserved" newline bitfld.long 0x0 2. "PAGECLOSE,If true bank is kept open only while there are page hit transactions available in the CAM to that bank. The last read or write command in the CAM with a bank and page hit is executed with auto-precharge if SCHED1.pageclose_timer=0. Even if.." "0,1" newline bitfld.long 0x0 1. "PREFER_WRITE,If set then the bank selector prefers writes over reads. FOR DEBUG ONLY. Programming Mode: Static" "0,1" newline rbitfld.long 0x0 0. "RESERVED,Reserved" "0,1" line.long 0x4 "SCHED1,Scheduler Control Register 1" hexmask.long.tbyte 0x4 8.--31. 1. "RESERVED,Reserved" newline hexmask.long.byte 0x4 0.--7. 1. "PAGECLOSE_TIMER,This field works in conjunction with SCHED.pageclose.It only has meaning if SCHED.pageclose==1. If SCHED.pageclose==1 and pageclose_timer==0 then an auto-precharge may be scheduled for last read or write command in the CAM with a bank.." group.long 0x25C++0x3 line.long 0x0 "PERFHPR1,High Priority Read CAM Register 1" hexmask.long.byte 0x0 24.--31. 1. "HPR_XACT_RUN_LENGTH,Indicates the number of transactions that are serviced once the HPR queue goes critical is the smaller of: - (a) This number - (b) Number of transactions available Unit: Transaction. FOR PERFORMANCE ONLY. Programming Mode:.." newline hexmask.long.byte 0x0 16.--23. 1. "RESERVED,Reserved" newline hexmask.long.word 0x0 0.--15. 1. "HPR_MAX_STARVE,Indicates the number of DFI clocks that the HPR queue can be starved before it goes critical. The minimum valid functional value for this register is 0x1. Programming it to 0x0 disables the starvation functionality. During normal operation.." group.long 0x264++0x3 line.long 0x0 "PERFLPR1,Low Priority Read CAM Register 1" hexmask.long.byte 0x0 24.--31. 1. "LPR_XACT_RUN_LENGTH,Indicates the number of transactions that are serviced once the LPR queue goes critical is the smaller of: - (a) This number - (b) Number of transactions available Unit: Transaction. FOR PERFORMANCE ONLY. Programming Mode:.." newline hexmask.long.byte 0x0 16.--23. 1. "RESERVED,Reserved" newline hexmask.long.word 0x0 0.--15. 1. "LPR_MAX_STARVE,Indicates the number of DFI clocks that the LPR queue can be starved before it goes critical. The minimum valid functional value for this register is 0x1. Programming it to 0x0 disables the starvation functionality. During normal operation.." group.long 0x26C++0x3 line.long 0x0 "PERFWR1,Write CAM Register 1" hexmask.long.byte 0x0 24.--31. 1. "W_XACT_RUN_LENGTH,Indicates the number of transactions that are serviced once the WR queue goes critical is the smaller of: - (a) This number - (b) Number of transactions available Unit: Transaction. FOR PERFORMANCE ONLY. Programming Mode: Quasi-dynamic.." newline hexmask.long.byte 0x0 16.--23. 1. "RESERVED,Reserved" newline hexmask.long.word 0x0 0.--15. 1. "W_MAX_STARVE,Indicates the number of DFI clocks that the WR queue can be starved before it goes critical. The minimum valid functional value for this register is 0x1. Programming it to 0x0 disables the starvation functionality. During normal operation.." group.long 0x300++0x7 line.long 0x0 "DBG0,Debug Register 0" hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED,Reserved" newline bitfld.long 0x0 7. "DIS_MAX_RANK_WR_OPT,Indicates the disable optimized max_rank_wr and max_logical_rank_wr feature. This register is for debug purpose only. For normal operation This register must be set to 0. Programming Mode: Static" "0,1" newline bitfld.long 0x0 6. "DIS_MAX_RANK_RD_OPT,Indicates the disable optimized max_rank_rd and max_logical_rank_rd feature. This register is for debug purpose only. For normal operation This register must be set to 0. Programming Mode: Static" "0,1" newline rbitfld.long 0x0 5. "RESERVED,Reserved" "0,1" newline bitfld.long 0x0 4. "DIS_COLLISION_PAGE_OPT,When this is set to '0' auto-precharge is disabled for the flushed command in a collision case. Collision cases are write followed by read to same address read followed by write to same address or write followed by write to same.." "0,1" newline rbitfld.long 0x0 1.--3. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 0. "DIS_WC,When 1 disable write combine. FOR DEBUG ONLY. Programming Mode: Static" "0,1" line.long 0x4 "DBG1,Debug Register 1" hexmask.long 0x4 2.--31. 1. "RESERVED,Reserved" newline bitfld.long 0x4 1. "DIS_HIF,When 1 uMCTL2 asserts the HIF command signal hif_cmd_stall. uMCTL2 ignores the hif_cmd_valid and all other associated request signals. This bit is intended to be switched on-the-fly. Programming Mode: Dynamic" "0,1" newline bitfld.long 0x4 0. "DIS_DQ,When 1 uMCTL2 does not de-queue any transactions from the CAM. Bypass is also disabled. All transactions are queued in the CAM. No reads or writes are issued to SDRAM as long as this is asserted. This bit may be used to prevent reads or writes.." "0,1" rgroup.long 0x308++0x3 line.long 0x0 "DBGCAM,CAM Debug Register" bitfld.long 0x0 30.--31. "RESERVED,Reserved" "0,1,2,3" newline bitfld.long 0x0 29. "WR_DATA_PIPELINE_EMPTY,This bit indicates that the write data pipeline on the DFI interface is empty. This register is intended to be polled at least twice after setting DBG1.dis_dq to ensure that all remaining commands/data have completed. Programming.." "0,1" newline bitfld.long 0x0 28. "RD_DATA_PIPELINE_EMPTY,This bit indicates that the read data pipeline on the DFI interface is empty. This register is intended to be polled at least twice after setting DBG1.dis_dq to ensure that all remaining commands/data have completed. Programming.." "0,1" newline bitfld.long 0x0 27. "RESERVED,Reserved" "0,1" newline bitfld.long 0x0 26. "DBG_WR_Q_EMPTY,When 1 all the Write command queues and Write data buffers inside DDRC are empty. This register is to be used for debug purpose. An example use-case scenario: When the controller enters self-refresh using the Low-Power entry sequence.." "0,1" newline bitfld.long 0x0 25. "DBG_RD_Q_EMPTY,When 1 all the Read command queues and Read data buffers inside DDRC are empty. This register is to be used for debug purpose. An example use-case scenario: When the controller enters self-refresh using the Low-Power entry sequence.." "0,1" newline bitfld.long 0x0 24. "DBG_STALL,Stall. FOR DEBUG ONLY. Programming Mode: Dynamic" "0,1" newline bitfld.long 0x0 22.--23. "RESERVED,Reserved" "0,1,2,3" newline hexmask.long.byte 0x0 16.--21. 1. "DBG_W_Q_DEPTH,This field indicates the Write queue depth. The last entry of WR queue is reserved for ECC SCRUB operation. This entry is not included in the calculation of the queue depth. FOR DEBUG ONLY Programming Mode: Dynamic" newline bitfld.long 0x0 14.--15. "RESERVED,Reserved" "0,1,2,3" newline hexmask.long.byte 0x0 8.--13. 1. "DBG_LPR_Q_DEPTH,This field indicates the low priority read queue depth. The last entry of Lpr queue is reserved for ECC SCRUB operation. This entry is not included in the calculation of the queue depth. FOR DEBUG ONLY Programming Mode: Dynamic" newline bitfld.long 0x0 6.--7. "RESERVED,Reserved" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "DBG_HPR_Q_DEPTH,This field indicates the high priority read queue depth. FOR DEBUG ONLY. Programming Mode: Dynamic" group.long 0x30C++0x3 line.long 0x0 "DBGCMD,Command Debug Register" hexmask.long 0x0 6.--31. 1. "RESERVED,Reserved" newline bitfld.long 0x0 5. "CTRLUPD,Setting this register bit to 1 indicates to the uMCTL2 to issue a dfi_ctrlupd_req to the PHY. When this request is stored in the uMCTL2 the bit is automatically cleared. This operation must only be performed when DFIUPD0.dis_auto_ctrlupd=1." "0,1" newline bitfld.long 0x0 4. "ZQ_CALIB_SHORT,Setting this register bit to 1 indicates to the uMCTL2 to issue a ZQCS (ZQ calibration short)/MPC(ZQ calibration) command to the SDRAM. When this request is stored in the uMCTL2 the bit is automatically cleared. This operation can be.." "0,1" newline rbitfld.long 0x0 2.--3. "RESERVED,Reserved" "0,1,2,3" newline bitfld.long 0x0 1. "RANK1_REFRESH,Setting this register bit to 1 indicates to the uMCTL2 to issue a refresh to rank 1. Writing to this bit causes DBGSTAT.rank1_refresh_busy to be set. When DBGSTAT.rank1_refresh_busy is cleared the command has been stored in uMCTL2. For 3DS.." "0,1" newline bitfld.long 0x0 0. "RANK0_REFRESH,Setting this register bit to 1 indicates to the uMCTL2 to issue a refresh to rank 0. Writing to this bit causes DBGSTAT.rank0_refresh_busy to be set. When DBGSTAT.rank0_refresh_busy is cleared the command has been stored in uMCTL2. For 3DS.." "0,1" rgroup.long 0x310++0x3 line.long 0x0 "DBGSTAT,Status Debug Register" hexmask.long 0x0 6.--31. 1. "RESERVED,Reserved" newline bitfld.long 0x0 5. "CTRLUPD_BUSY,SoC might initiate a ctrlupd operation only if this signal is low. This signal goes high in the clock after the uMCTL2 accepts the ctrlupd request. It goes low when the ctrlupd operation is initiated in the uMCTL2. It is recommended not to.." "Indicates that the SoC can initiate a ctrlupd..,Indicates that ctrlupd operation has not been.." newline bitfld.long 0x0 4. "ZQ_CALIB_SHORT_BUSY,SoC might initiate a ZQCS (ZQ calibration short) operation only if this signal is low. This signal goes high in the clock after the uMCTL2 accepts the ZQCS request. It goes low when the ZQCS operation is initiated in the uMCTL2. It is.." "Indicates that the SoC can initiate a ZQCS..,Indicates that ZQCS operation has not been.." newline bitfld.long 0x0 2.--3. "RESERVED,Reserved" "0,1,2,3" newline bitfld.long 0x0 1. "RANK1_REFRESH_BUSY,SoC might initiate a rank1_refresh operation (refresh operation to rank 1) only if this signal is low. This signal goes high in the clock after DBGCMD.rank1_refresh is set to one. It goes low when the rank1_refresh operation is stored.." "Indicates that the SoC can initiate a..,Indicates that rank1_refresh operation has not.." newline bitfld.long 0x0 0. "RANK0_REFRESH_BUSY,SoC might initiate a rank0_refresh operation (refresh operation to rank 0) only if this signal is low. This signal goes high in the clock after DBGCMD.rank0_refresh is set to one. It goes low when the rank0_refresh operation is stored.." "Indicates that the SoC can initiate a..,Indicates that rank0_refresh operation has not.." rgroup.long 0x318++0x3 line.long 0x0 "DBGCAM1,CAM Debug Register 1" hexmask.long 0x0 6.--31. 1. "RESERVED,Reserved" newline hexmask.long.byte 0x0 0.--5. 1. "DBG_WRECC_Q_DEPTH,This field indicates the write ECC queue depth. FOR DEBUG ONLY. Programming Mode: Dynamic" group.long 0x320++0x3 line.long 0x0 "SWCTL,Software Register Programming Control Enable" hexmask.long 0x0 1.--31. 1. "RESERVED,Reserved" newline bitfld.long 0x0 0. "SW_DONE,Enables quasi-dynamic register programming outside reset. Program this register to 0 to enable quasi-dynamic programming. Set back register to 1 once programming is done. Programming Mode: Dynamic" "0,1" rgroup.long 0x324++0x3 line.long 0x0 "SWSTAT,Software Register Programming Control Status" hexmask.long 0x0 1.--31. 1. "RESERVED,Reserved" newline bitfld.long 0x0 0. "SW_DONE_ACK,Register programming done. This register is the echo of SWCTL.sw_done. Wait for sw_done value 1 to propagate to sw_done_ack at the end of the programming sequence to ensure that the correct registers values are propagated to the destination.." "0,1" group.long 0x328++0x3 line.long 0x0 "SWCTLSTATIC,Static Registers Write Enable" hexmask.long 0x0 1.--31. 1. "RESERVED,Reserved" newline bitfld.long 0x0 0. "SW_STATIC_UNLOCK,Enables static register programming outside reset. Program this register to 1 to enable static register programming. Set register back to 0 once programming is done. Programming Mode: Dynamic" "0,1" group.long 0x330++0x7 line.long 0x0 "OCPARCFG0,On-Chip Parity Configuration Register 0" hexmask.long.byte 0x0 27.--31. 1. "RESERVED,Reserved" newline bitfld.long 0x0 26. "PAR_RADDR_ERR_INTR_FORCE,Interrupt force bit for all par_raddr_err_intr. uMCTL2 automatically clears this bit. Programming Mode: Dynamic" "0,1" newline bitfld.long 0x0 25. "PAR_WADDR_ERR_INTR_FORCE,Interrupt force bit for all par_waddr_err_intr. uMCTL2 automatically clears this bit. Programming Mode: Dynamic" "0,1" newline bitfld.long 0x0 24. "PAR_RADDR_ERR_INTR_CLR,Interrupt clear bit for all par_raddr_err_intr. uMCTL2 automatically clears this bit. Programming Mode: Dynamic" "0,1" newline bitfld.long 0x0 23. "PAR_RADDR_ERR_INTR_EN,Enables interrupt generation if set to 1 for all ports on signal par_raddr_err_intr_n upon detection of parity error on the AXI interface. Programming Mode: Dynamic" "0,1" newline bitfld.long 0x0 22. "PAR_WADDR_ERR_INTR_CLR,Interrupt clear bit for all par_waddr_err_intr. uMCTL2 automatically clears this bit. Programming Mode: Dynamic" "0,1" newline bitfld.long 0x0 21. "PAR_WADDR_ERR_INTR_EN,Enables interrupt generation if set to 1 for all ports on signal par_waddr_err_intr_n upon detection of parity error on the AXI interface. Programming Mode: Dynamic" "0,1" newline bitfld.long 0x0 20. "PAR_ADDR_SLVERR_EN,Enables SLVERR generation on read response or write response when address parity error is detected at the AXI interface. Programming Mode: Quasi-dynamic Group 3" "0,1" newline hexmask.long.byte 0x0 16.--19. 1. "RESERVED,Reserved" newline bitfld.long 0x0 15. "PAR_RDATA_ERR_INTR_FORCE,Interrupt force bit for all par_rdata_err_intr_n and par_rdata_in_err_ecc_intr (Inline-ECC only). uMCTL2 automatically clears this bit. Programming Mode: Dynamic" "0,1" newline bitfld.long 0x0 14. "PAR_RDATA_ERR_INTR_CLR,Interrupt clear bit for par_rdata_err_intr. uMCTL2 automatically clears this bit. Programming Mode: Dynamic" "0,1" newline bitfld.long 0x0 13. "PAR_RDATA_ERR_INTR_EN,Enables interrupt generation if set to 1 for all ports on signal par_rdata_err_intr_n upon detection of parity error at the AXI interface. Programming Mode: Dynamic" "0,1" newline bitfld.long 0x0 12. "PAR_RDATA_SLVERR_EN,Enables SLVERR generation on read response when read data parity error is detected at the AXI interface. Programming Mode: Quasi-dynamic Group 3" "0,1" newline hexmask.long.byte 0x0 8.--11. 1. "RESERVED,Reserved" newline bitfld.long 0x0 7. "PAR_WDATA_ERR_INTR_FORCE,Interrupt force bit for par_wdata_err_intr. uMCTL2 automatically clears this bit. Programming Mode: Dynamic" "0,1" newline bitfld.long 0x0 6. "PAR_WDATA_ERR_INTR_CLR,Interrupt clear bit for par_wdata_err_intr. uMCTL2 automatically clears this bit. Programming Mode: Dynamic" "0,1" newline bitfld.long 0x0 5. "PAR_WDATA_SLVERR_EN,Enables SLVERR generation on write response when write data parity error is detected at the AXI interface. Programming Mode: Quasi-dynamic Group 3" "0,1" newline bitfld.long 0x0 4. "PAR_WDATA_ERR_INTR_EN,Enables write data interrupt generation (par_wdata_err_intr) upon detection of parity error at the AXI or DFI interface. Programming Mode: Dynamic" "0,1" newline rbitfld.long 0x0 2.--3. "RESERVED,Reserved" "0,1,2,3" newline bitfld.long 0x0 1. "OC_PARITY_TYPE,Parity type: - 0 - Even parity - 1 - Odd parity Programming Mode: Quasi-dynamic Group 3" "Even parity,Odd parity" newline bitfld.long 0x0 0. "OC_PARITY_EN,Parity enable register. Enables On-Chip parity for all interfaces. Programming Mode: Quasi-dynamic Group 3" "0,1" line.long 0x4 "OCPARCFG1,On-Chip Parity Configuration Register 1" hexmask.long.tbyte 0x4 12.--31. 1. "RESERVED,Reserved" newline hexmask.long.byte 0x4 8.--11. 1. "PAR_POISON_LOC_WR_PORT,Enables parity poisoning on write data at the AXI interface before the input parity check logic. The value specifies the binary encoded port number of the AXI interface to be injected with parity error. Programming Mode:.." newline hexmask.long.byte 0x4 4.--7. 1. "PAR_POISON_LOC_RD_PORT,Enables parity poisoning on read data at the AXI interface after the parity check logic. The value specifies the binary encoded port number of the AXI interface to be injected with parity error. Error can be injected to one port at.." newline bitfld.long 0x4 3. "PAR_POISON_LOC_RD_IECC_TYPE,Selects which parity to poison at the DFI when inline ECC is enabled. If this register is set to 0 parity error is injected on the first read data going through the ECC path. If this register is set to 1 parity error is.." "0,1" newline bitfld.long 0x4 2. "PAR_POISON_LOC_RD_DFI,Enables parity poisoning on read data at the DFI interface after the parity generation logic. When MEMC_INLINE_ECC=1 enables poisoning of ECC word after the ECC encoder at the write data interface at the DFI. Programming Mode:.." "0,1" newline rbitfld.long 0x4 1. "RESERVED,Reserved" "0,1" newline bitfld.long 0x4 0. "PAR_POISON_EN,Enables on-chip parity poisoning on the data interfaces. Programming Mode: Quasi-dynamic Group 3" "0,1" repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) rgroup.long ($2+0x338)++0x3 line.long 0x0 "OCPARSTAT$1,On-Chip Parity Status Register 0" hexmask.long.word 0x0 17.--31. 1. "RESERVED,Reserved" newline bitfld.long 0x0 16. "PAR_RADDR_ERR_INTR_0,Read address parity error interrupt for port 0. This interrupt is asserted when an on-chip read address parity error occurred on the corresponding AXI port's read address channel. Programming Mode: Static" "0,1" newline hexmask.long.word 0x0 1.--15. 1. "RESERVED,Reserved" newline bitfld.long 0x0 0. "PAR_WADDR_ERR_INTR_0,Write address parity error interrupt for port 0. This interrupt is asserted when an on-chip write address parity error occurred on the corresponding AXI port's write address channel. Programming Mode: Static" "0,1" repeat.end rgroup.long 0x340++0x3 line.long 0x0 "OCPARSTAT2,On-Chip Parity Status Register 2" hexmask.long 0x0 5.--31. 1. "RESERVED,Reserved" newline bitfld.long 0x0 4. "PAR_RDATA_IN_ERR_ECC_INTR,Interrupt on ECC data going into inline ECC decoder. Cleared by par_rdata_err_intr_clr. Programming Mode: Static" "0,1" newline bitfld.long 0x0 2.--3. "RESERVED,Reserved" "0,1,2,3" newline bitfld.long 0x0 0.--1. "PAR_WDATA_OUT_ERR_INTR,Write data parity error interrupt on output. Cleared by register par_wdata_err_intr_clr. Programming Mode: Static" "0,1,2,3" group.long 0x36C++0x3 line.long 0x0 "POISONCFG,AXI Poison Configuration Register. Common for all AXI ports." hexmask.long.byte 0x0 25.--31. 1. "RESERVED,Reserved" newline bitfld.long 0x0 24. "RD_POISON_INTR_CLR,Interrupt clear for read transaction poisoning. Allow 2/3 clock cycles for correct value to propagate to controller logic and clear the interrupts. uMCTL2 automatically clears this bit. Programming Mode: Dynamic" "0,1" newline rbitfld.long 0x0 21.--23. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 20. "RD_POISON_INTR_EN,If set to 1 enables interrupts for read transaction poisoning. Programming Mode: Dynamic" "0,1" newline rbitfld.long 0x0 17.--19. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 16. "RD_POISON_SLVERR_EN,If set to 1 enables SLVERR response for read transaction poisoning. Programming Mode: Dynamic" "0,1" newline hexmask.long.byte 0x0 9.--15. 1. "RESERVED,Reserved" newline bitfld.long 0x0 8. "WR_POISON_INTR_CLR,Interrupt clear for write transaction poisoning. Allow 2/3 clock cycles for correct value to propagate to controller logic and clear the interrupts. uMCTL2 automatically clears this bit. Programming Mode: Dynamic" "0,1" newline rbitfld.long 0x0 5.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 4. "WR_POISON_INTR_EN,If set to 1 enables interrupts for write transaction poisoning. Programming Mode: Dynamic" "0,1" newline rbitfld.long 0x0 1.--3. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 0. "WR_POISON_SLVERR_EN,If set to 1 enables SLVERR response for write transaction poisoning. Programming Mode: Dynamic" "0,1" rgroup.long 0x370++0x3 line.long 0x0 "POISONSTAT,AXI Poison Status Register" hexmask.long.word 0x0 17.--31. 1. "RESERVED,Reserved" newline bitfld.long 0x0 16. "RD_POISON_INTR_0,Read transaction poisoning error interrupt for port 0. This register is a APB clock copy (double register synchronizer) of the interrupt asserted when a transaction is poisoned on the corresponding AXI port's read address channel. Bit 0.." "0,1" newline hexmask.long.word 0x0 1.--15. 1. "RESERVED,Reserved" newline bitfld.long 0x0 0. "WR_POISON_INTR_0,Write transaction poisoning error interrupt for port 0. This register is a APB clock copy (double register synchronizer) of the interrupt asserted when a transaction is poisoned on the corresponding AXI port's write address channel. Bit.." "0,1" group.long 0x374++0x3 line.long 0x0 "ADVECCINDEX,Advanced ECC Index Register" hexmask.long.tbyte 0x0 9.--31. 1. "RESERVED,Reserved" newline hexmask.long.byte 0x0 5.--8. 1. "ECC_POISON_BEATS_SEL,Selector of which DRAM beat's poison pattern is set by ECCPOISONPAT0/1/2 registers. For frequency ratio 1:1 mode 2 DRAM beats can be poisoned. Set ecc_poison_beats_sel to 0 and given ECCPOISONPAT0/1/2 to set 1st beat's poison.." newline bitfld.long 0x0 3.--4. "ECC_ERR_SYMBOL_SEL,Selector of which error symbol's status output to ADVECCSTAT.advecc_err_symbol_pos and advecc_err_symbol_bits. The default is first error symbol. The value must be less than ADVECCSTAT.advecc_num_err_symbol. Programming Mode:.." "0,1,2,3" newline bitfld.long 0x0 0.--2. "ECC_SYNDROME_SEL,Selector of which DRAM beat data output to ECCCSYN0/1/2 as well as ECCUCSYN. In Advanced ECC the syndrome consists of number of DRAM beats. This register selects which beats of data is output to ECCCSYN0/1/2 and ECCUCSYN0/1/2 registers." "0,1,2,3,4,5,6,7" group.long 0x37C++0x3 line.long 0x0 "ECCPOISONPAT0,ECC Poison Pattern 0 Register" hexmask.long 0x0 0.--31. 1. "ECC_POISON_DATA_31_0,Indicates the poison pattern for DRAM data[31:0]. setting this bit to 1 indicates poison (invert) corresponding DRAM bit. It is indirect register. Selector is ADVECCINDEX.ecc_poison_beats_sel. Programming Mode: Quasi-dynamic Group 3" group.long 0x384++0x3 line.long 0x0 "ECCPOISONPAT2,ECC Poison Pattern 2 Register" hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED,Reserved" newline hexmask.long.byte 0x0 0.--7. 1. "ECC_POISON_DATA_71_64,Indicates the poison pattern for DRAM data[71:64]. Setting this bit to 1 indicates poison (invert) corresponding DRAM bit. It is indirect register. Selector is ADVECCINDEX.ecc_poison_beats_sel. Programming Mode: Quasi-dynamic Group 3" rgroup.long 0x388++0x3 line.long 0x0 "ECCAPSTAT,Address protection within ECC Status Register" hexmask.long 0x0 1.--31. 1. "RESERVED,Reserved" newline bitfld.long 0x0 0. "ECC_AP_ERR,Indicates the number of ECC errors (correctable/uncorrectable) within one burst exceeded the threshold(ECCCFG0.ecc_ap_err_threshold). Programming Mode: Dynamic" "0,1" group.long 0x3C0++0x3 line.long 0x0 "REGPARCFG,Register Parity Configuration Register (Note that all fields must be programmed with single write operation)." hexmask.long.tbyte 0x0 9.--31. 1. "RESERVED,Reserved" newline bitfld.long 0x0 8. "REG_PAR_POISON_EN,Enable Register Parity poisoning. Programming Mode: Dynamic" "0,1" newline hexmask.long.byte 0x0 4.--7. 1. "RESERVED,Reserved" newline bitfld.long 0x0 3. "REG_PAR_ERR_INTR_FORCE,Interrupt force bit for reg_par_err_intr setting this register causes the output interrupt to be asserted. uMCTL2 automatically clears this bit. There is no interaction between functionally triggering an interrupt and forcing an.." "0,1" newline bitfld.long 0x0 2. "REG_PAR_ERR_INTR_CLR,Interupt clear bit for reg_par_err_intr. uMCTL2 automatically clears this bit. Programming Mode: Dynamic" "0,1" newline bitfld.long 0x0 1. "REG_PAR_ERR_INTR_EN,Enables interrupt generation if set to 1 on signal reg_par_err_intr upon detection of register parity error. Programming Mode: Dynamic" "0,1" newline bitfld.long 0x0 0. "REG_PAR_EN,Register Parity enable register. Programming Mode: Dynamic" "0,1" rgroup.long 0x3C4++0x3 line.long 0x0 "REGPARSTAT,Register Parity Status Register" hexmask.long 0x0 1.--31. 1. "RESERVED,Reserved" newline bitfld.long 0x0 0. "REG_PAR_ERR_INTR,Interrupt asserted when Register Parity error is detected. Cleared by setting REGPARCFG.reg_par_err_intr_clr to 1. Programming Mode: Static" "0,1" group.long 0x3E0++0x3 line.long 0x0 "OCCAPCFG,On-Chip command/Address Protection Configuration Register" hexmask.long.byte 0x0 28.--31. 1. "RESERVED,Reserved" newline bitfld.long 0x0 27. "OCCAP_ARB_RAQ_POISON_EN,Enables poisoning for the Read Address Queues (RAQ) inside each XPI. Poisoning inverts all parity bits generated by the parity generator. Error is flagged as soon as the first RAQ is read. This register is not cleared.." "0,1" newline bitfld.long 0x0 26. "OCCAP_ARB_CMP_POISON_ERR_INJ,Enables error injection in the poisoning of OCCAP Arbiter logic. Injects error into poisoning logic (either parallel or seq) such that XOR logic for one signal is not poisoned when expected. If set it allows ability to.." "OCCAPSTAT,OCCAPSTAT" newline bitfld.long 0x0 25. "OCCAP_ARB_CMP_POISON_PARALLEL,Enables full poisoning for compare logic inside XPI. Poisoning inverts all bits of all outputs coming from the duplicated modules before the XOR comparators together. uMCTL2 automatically clears this bit. Programming Mode:.." "0,1" newline bitfld.long 0x0 24. "OCCAP_ARB_CMP_POISON_SEQ,Enables poisoning for compare logic inside XPI. Poisoning inverts all bits coming from the duplicated modules before the XOR comparators one output at the time per each comparator. uMCTL2 automatically clears this bit." "0,1" newline hexmask.long.byte 0x0 19.--23. 1. "RESERVED,Reserved" newline bitfld.long 0x0 18. "OCCAP_ARB_INTR_FORCE,Interrupt force bit for occap_arb_err_intr setting this register causes the output interrupt to be asserted. uMCTL2 automatically clears this bit. There is no interaction between functionally triggering an interrupt and forcing an.." "0,1" newline bitfld.long 0x0 17. "OCCAP_ARB_INTR_CLR,Interrupt clear bit for occap_arb_err_intr and occap_arb_cmp_poison_complete. uMCTL2 automatically clears this bit. Programming Mode: Dynamic" "0,1" newline bitfld.long 0x0 16. "OCCAP_ARB_INTR_EN,Enables interrupt generation upon detection of OCCAP Arbiter errors. Programming Mode: Dynamic" "0,1" newline hexmask.long.word 0x0 1.--15. 1. "RESERVED,Reserved" newline bitfld.long 0x0 0. "OCCAP_EN,On Chip Command/Address Path Protection (OCCAP) enable register. Programming Mode: Quasi-dynamic Group 3" "0,1" rgroup.long 0x3E4++0x3 line.long 0x0 "OCCAPSTAT,On-Chip command/Address Protection Status Register" hexmask.long.byte 0x0 26.--31. 1. "RESERVED,Reserved" newline bitfld.long 0x0 25. "OCCAP_ARB_CMP_POISON_PARALLEL_ERR,Error when occap_arb_cmp_poison_full_en is active due to incorrect number of errors being occurring. Internal logic checks the number of errors detected while poisoning occurred for occap_arb_cmp_poison_full_en. It.." "0,1" newline bitfld.long 0x0 24. "OCCAP_ARB_CMP_POISON_SEQ_ERR,Error when occap_arb_cmp_poison_en is active due to incorrect number of errors being occurring. Internal logic checks that the correct number of errors detected while poisoning one output at the time occurred for.." "0,1" newline hexmask.long.byte 0x0 18.--23. 1. "RESERVED,Reserved" newline bitfld.long 0x0 17. "OCCAP_ARB_CMP_POISON_COMPLETE,OCCAP ARB comparator poisoning complete interrupt status. Register cleared by OCCAPCFG.occap_arb_intr_clr. Programming Mode: Static" "0,1" newline bitfld.long 0x0 16. "OCCAP_ARB_ERR_INTR,OCCAP Arbiter error interrupt status. Register cleared by OCCAPCFG.occap_arb_intr_clr. Programming Mode: Static" "0,1" newline hexmask.long.word 0x0 0.--15. 1. "RESERVED,Reserved" group.long 0x3E8++0x3 line.long 0x0 "OCCAPCFG1,On-Chip command/Address Protection Configuration Register 1" hexmask.long.byte 0x0 27.--31. 1. "RESERVED,Reserved" newline bitfld.long 0x0 26. "OCCAP_DDRC_CTRL_POISON_ERR_INJ,Enables error injection in the poisoning of OCCAP DDRC CTRL logic. Injects error into poisoning logic (either parallel or seq) such that XOR logic for one signal is not poisoned when expected. If set it allows ability to.." "OCCAPSTAT1,OCCAPSTAT1" newline bitfld.long 0x0 25. "OCCAP_DDRC_CTRL_POISON_PARALLEL,Enables poisoning of OCCAP DDRC CTRL logic for all parts of comparison logic in parallel. Poisons comparison logic for one core_ddrc_core_clk cycle by inverting a ddrc_ctrl[0]'s signal to XOR logic. ddrc_ctrl[1] related.." "0,1" newline bitfld.long 0x0 24. "OCCAP_DDRC_CTRL_POISON_SEQ,Enables poisoning of OCCAP DDRC CTRL logic for all parts of comparison logic in sequence. Poisons comparison logic for one core_ddrc_core_clk cycle by inverting a ddrc_ctrl[0]'s signal to XOR logic. ddrc_ctrl[1] related.." "0,1" newline hexmask.long.byte 0x0 19.--23. 1. "RESERVED,Reserved" newline bitfld.long 0x0 18. "OCCAP_DDRC_CTRL_INTR_FORCE,Interrupt force bit for occap_ddrc_ctrl_err_intr setting this register causes the output interrupt to be asserted. uMCTL2 automatically clears this bit. There is no interaction between functionally triggering an interrupt and.." "0,1" newline bitfld.long 0x0 17. "OCCAP_DDRC_CTRL_INTR_CLR,Interrupt clear bit for occap_ddrc_ctrl_err_intr. uMCTL2 automatically clears this bit. Programming Mode: Dynamic" "0,1" newline bitfld.long 0x0 16. "OCCAP_DDRC_CTRL_INTR_EN,Enables interrupt generation on signal occap_ddrc_ctrl_err_intr upon detection of OCCAP DDRC CTRL errors. Programming Mode: Dynamic" "0,1" newline hexmask.long.byte 0x0 11.--15. 1. "RESERVED,Reserved" newline bitfld.long 0x0 10. "OCCAP_DDRC_DATA_POISON_ERR_INJ,Enables error injection in the poisoning of OCCAP DDRC DATA logic. Injects error into poisoning logic (either parallel or seq) such that XOR logic for one signal is not poisoned when expected. If set it allows ability to.." "OCCAPSTAT1,OCCAPSTAT1" newline bitfld.long 0x0 9. "OCCAP_DDRC_DATA_POISON_PARALLEL,Enables poisoning of OCCAP DDRC DATA logic for all parts of comparison logic in parallel. Poisons comparison logic for one core_ddrc_core_clk cycle by inverting all bits of a signal to XOR logic. All signals of.." "0,1" newline bitfld.long 0x0 8. "OCCAP_DDRC_DATA_POISON_SEQ,Enables poisoning of OCCAP DDRC DATA logic for all parts of comparison logic in sequence. Poisons comparison logic for one core_ddrc_core_clk cycle by inverting all bits of a signal to XOR logic. All signals of instance[0] of.." "0,1" newline hexmask.long.byte 0x0 3.--7. 1. "RESERVED,Reserved" newline bitfld.long 0x0 2. "OCCAP_DDRC_DATA_INTR_FORCE,Interrupt force bit for occap_ddrc_data_err_intr setting this register causes the output interrupt to be asserted. uMCTL2 automatically clears this bit. There is no interaction between functionally triggering an interrupt and.." "0,1" newline bitfld.long 0x0 1. "OCCAP_DDRC_DATA_INTR_CLR,Interrupt clear bit for occap_ddrc_data_err_intr. uMCTL2 automatically clears this bit. Programming Mode: Dynamic" "0,1" newline bitfld.long 0x0 0. "OCCAP_DDRC_DATA_INTR_EN,Enables interrupt generation on signal occap_ddrc_data_err_intr upon detection of OCCAP DDRC DATA errors. Programming Mode: Dynamic" "0,1" rgroup.long 0x3EC++0x7 line.long 0x0 "OCCAPSTAT1,On-Chip command/Address Protection Status Register 1" hexmask.long.byte 0x0 26.--31. 1. "RESERVED,Reserved" newline bitfld.long 0x0 25. "OCCAP_DDRC_CTRL_POISON_PARALLEL_ERR,Error when occap_ddrc_ctrl_poison_parallel is active due to incorrect number of errors being occurring. Internal logic checks the number of errors detected while poisoning occurred for occap_ddrc_ctrl_poison_parallel." "0,1" newline bitfld.long 0x0 24. "OCCAP_DDRC_CTRL_POISON_SEQ_ERR,Error when occap_ddrc_ctrl_poison_seq is active due to incorrect number of errors being occurring. Internal logic checks the number of errors detected while poisoning occurred for occap_ddrc_ctrl_poison_seq. It checks for.." "0,1" newline hexmask.long.byte 0x0 18.--23. 1. "RESERVED,Reserved" newline bitfld.long 0x0 17. "OCCAP_DDRC_CTRL_POISON_COMPLETE,Indicates the OCCAP DDRC CTRL poisoning complete interrupt status. Register cleared by OCCAPCFG1.occap_ddrc_ctrl_err_intr_clr. Programming Mode: Static" "0,1" newline bitfld.long 0x0 16. "OCCAP_DDRC_CTRL_ERR_INTR,Indicates the OCCAP DDRC CTRL error interrupt status. Register cleared by OCCAPCFG1.occap_ddrc_ctrl_err_intr_clr. Programming Mode: Static" "0,1" newline hexmask.long.byte 0x0 10.--15. 1. "RESERVED,Reserved" newline bitfld.long 0x0 9. "OCCAP_DDRC_DATA_POISON_PARALLEL_ERR,Error when occap_ddrc_data_poison_parallel is active due to incorrect number of errors being occurring. Internal logic checks the number of errors detected while poisoning occurred for occap_ddrc_data_poison_parallel." "0,1" newline bitfld.long 0x0 8. "OCCAP_DDRC_DATA_POISON_SEQ_ERR,Error when occap_ddrc_data_poison_seq is active due to incorrect number of errors being occurring. Internal logic checks the number of errors detected while poisoning occurred for occap_ddrc_data_poison_seq. It checks for.." "0,1" newline hexmask.long.byte 0x0 2.--7. 1. "RESERVED,Reserved" newline bitfld.long 0x0 1. "OCCAP_DDRC_DATA_POISON_COMPLETE,Indicates the OCCAP DDRC DATA poisoning complete interrupt status. Register cleared by OCCAPCFG1.occap_ddrc_data_err_intr_clr. Programming Mode: Static" "0,1" newline bitfld.long 0x0 0. "OCCAP_DDRC_DATA_ERR_INTR,Indicates the OCCAP DDRC DATA error interrupt status. Register cleared by OCCAPCFG1.occap_ddrc_data_err_intr_clr. Programming Mode: Static" "0,1" line.long 0x4 "DERATESTAT,Temperature Derate Status Register" hexmask.long 0x4 1.--31. 1. "RESERVED,Reserved" newline bitfld.long 0x4 0. "DERATE_TEMP_LIMIT_INTR,Derate temperature interrupt indicating LPDDR2/3/4 SDRAM temperature operating limit is exceeded. This register field is set to 1 when the value read from MR4[2:0] is 3'b000 or 3'b111. Cleared by register.." "0,1" tree.end tree "UMCTL2_MP (uMCTL2 Multi-Port Registers)" base ad:0x1016 rgroup.long 0x4++0x3 line.long 0x0 "PSTAT,Port Status Register" bitfld.long 0x0 16. "WR_PORT_BUSY_0,Indicates if there are outstanding writes for AXI port 0. Programming Mode: Dynamic" "0,1" bitfld.long 0x0 0. "RD_PORT_BUSY_0,Indicates if there are outstanding reads for AXI port 0. Programming Mode: Dynamic" "0,1" group.long 0x8++0xB line.long 0x0 "PCCFG,Port Common Configuration Register" bitfld.long 0x0 8. "BL_EXP_MODE,Burst length expansion mode. By default (that is bl_exp_mode==0) XPI expands every AXI burst into multiple HIF commands using the memory burst length as a unit. If set to 1 then XPI uses half of the memory burst length as a unit. This.." "UMCTL2_PARTIAL_WR=1,?" bitfld.long 0x0 4. "PAGEMATCH_LIMIT,Page match four limit. If set to 1 limits the number of consecutive same page DDRC transactions that can be granted by the Port Arbiter to four when Page Match feature is enabled. If set to 0 there is no limit imposed on number of.." "0,1" bitfld.long 0x0 0. "GO2CRITICAL_EN,If set to 1 (enabled) sets co_gs_go2critical_wr and co_gs_go2critical_lpr/co_gs_go2critical_hpr signals going to DDRC based on urgent input (awurgent arurgent) coming from AXI master. If set to 0 (disabled) co_gs_go2critical_wr and.." "0,1" line.long 0x4 "PCFGR_0,Port n Configuration Read Register" bitfld.long 0x4 16. "RDWR_ORDERED_EN,Enables ordered read/writes. If set to 1 preserves the ordering between read transaction and write transaction issued to the same address on a given port. In other words the controller ensures that all same address read and write.." "0,1" bitfld.long 0x4 14. "RD_PORT_PAGEMATCH_EN,If set to 1 enables the Page Match feature. If enabled once a requesting port is granted the port is continued to be granted if the following immediate commands are to the same memory page (same rank same bank and same row). See.." "0,1" bitfld.long 0x4 13. "RD_PORT_URGENT_EN,If set to 1 enables the AXI urgent sideband signal (arurgent). When enabled and arurgent is asserted by the master that port becomes the highest priority and co_gs_go2critical_lpr/co_gs_go2critical_hpr signal to DDRC is asserted if.." "0,1" newline bitfld.long 0x4 12. "RD_PORT_AGING_EN,If set to 1 enables aging function for the read channel of the port. Programming Mode: Static" "0,1" hexmask.long.word 0x4 0.--9. 1. "RD_PORT_PRIORITY,Determines the initial load value of read aging counters. These counters are parallel loaded after reset or after each grant to the corresponding port. The aging counters down-count every clock cycle where the port is requesting but not.." line.long 0x8 "PCFGW_0,Port n Configuration Write Register" bitfld.long 0x8 14. "WR_PORT_PAGEMATCH_EN,If set to 1 enables the Page Match feature. If enabled once a requesting port is granted the port is continued to be granted if the following immediate commands are to the same memory page (same rank same bank and same row). See.." "0,1" bitfld.long 0x8 13. "WR_PORT_URGENT_EN,If set to 1 enables the AXI urgent sideband signal (awurgent). When enabled and awurgent is asserted by the master that port becomes the highest priority and co_gs_go2critical_wr signal to DDRC is asserted if enabled in.." "0,1" bitfld.long 0x8 12. "WR_PORT_AGING_EN,If set to 1 enables aging function for the write channel of the port. Programming Mode: Static" "0,1" newline hexmask.long.word 0x8 0.--9. 1. "WR_PORT_PRIORITY,Determines the initial load value of write aging counters. These counters are parallel loaded after reset or after each grant to the corresponding port. The aging counters down-count every clock cycle where the port is requesting but.." group.long 0x98++0x13 line.long 0x0 "PCTRL_0,Port n Control Register" bitfld.long 0x0 0. "PORT_EN,Enables AXI port n. Programming Mode: Dynamic" "0,1" line.long 0x4 "PCFGQOS0_0,Port n Read QoS Configuration Register 0" bitfld.long 0x4 24.--25. "RQOS_MAP_REGION2,This bitfield indicates the traffic class of region2. For dual address queue configurations region2 maps to the red address queue. Valid values are 1: VPR and 2: HPR only. When VPR support is disabled (UMCTL2_VPR_EN = 0) and traffic.." "?,VPR and,HPR only,?" bitfld.long 0x4 20.--21. "RQOS_MAP_REGION1,This bit field indicates the traffic class of region 1. Valid values are: - 0 - LPR - 1 - VPR - 2 - HPR For dual address queue configurations region1 maps to the blue address queue. In this case valid values are - 0 - LPR - 1 - VPR.." "LPR,VPR only,HPR,?" bitfld.long 0x4 16.--17. "RQOS_MAP_REGION0,This bit field indicates the traffic class of region 0. Valid values are: - 0 - LPR - 1 - VPR - 2 - HPR For dual address queue configurations region 0 maps to the blue address queue. In this case valid values are: 0: LPR and 1: VPR.." "LPR and,VPR only,HPR,?" newline hexmask.long.byte 0x4 8.--11. 1. "RQOS_MAP_LEVEL2,Separation level2 indicating the end of region1 mapping; start of region1 is (level1 + 1). Possible values for level2 are (level1 + 1) to 14 which corresponds to arqos. Region2 starts from (level2 + 1) up to 15. Note that for PA arqos.." hexmask.long.byte 0x4 0.--3. 1. "RQOS_MAP_LEVEL1,Separation level1 indicating the end of region0 mapping; start of region0 is 0. Possible values for level1 are 0 to 13 (for dual RAQ) or 0 to 14 (for single RAQ) which corresponds to arqos. Note that for PA arqos values are used directly.." line.long 0x8 "PCFGQOS1_0,Port n Read QoS Configuration Register 1" hexmask.long.word 0x8 16.--26. 1. "RQOS_MAP_TIMEOUTR,Specifies the timeout value for transactions mapped to the red address queue. Programming Mode: Quasi-dynamic Group 3" hexmask.long.word 0x8 0.--10. 1. "RQOS_MAP_TIMEOUTB,Specifies the timeout value for transactions mapped to the blue address queue. Programming Mode: Quasi-dynamic Group 3" line.long 0xC "PCFGWQOS0_0,Port n Write QoS Configuration Register 0" bitfld.long 0xC 24.--25. "WQOS_MAP_REGION2,This bit field indicates the traffic class of region 2. Valid values are: - 0 - NPW - 1 - VPW When VPW support is disabled (UMCTL2_VPW_EN = 0) and traffic class of region 2 is set to 1 (VPW) VPW traffic is aliased to NPW traffic." "NPW,VPW,?,?" bitfld.long 0xC 20.--21. "WQOS_MAP_REGION1,This bit field indicates the traffic class of region 1. Valid values are: 0: NPW 1: VPW. When VPW support is disabled (UMCTL2_VPW_EN = 0) and traffic class of region 1 is set to 1 (VPW) VPW traffic is aliased to NPW traffic." "NPW,VPW,?,?" bitfld.long 0xC 16.--17. "WQOS_MAP_REGION0,This bit field indicates the traffic class of region 0. Valid values are: - 0 - NPW - 1 - VPW When VPW support is disabled (UMCTL2_VPW_EN = 0) and traffic class of region 0 is set to 1 (VPW) VPW traffic is aliased to NPW traffic." "NPW,VPW,?,?" newline hexmask.long.byte 0xC 8.--11. 1. "WQOS_MAP_LEVEL2,Separation level2 indicating the end of region1 mapping; start of region1 is (level1 + 1). Possible values for level2 are (level1 + 1) to 14 which corresponds to awqos. Region2 starts from (level2 + 1) up to 15. Note that for PA awqos.." hexmask.long.byte 0xC 0.--3. 1. "WQOS_MAP_LEVEL1,Separation level indicating the end of region0 mapping; start of region0 is 0. Possible values for level1 are 0 to 13 which corresponds to awqos. Note that for PA awqos values are used directly as port priorities where the higher the.." line.long 0x10 "PCFGWQOS1_0,Port n Write QoS Configuration Register 1" hexmask.long.word 0x10 16.--26. 1. "WQOS_MAP_TIMEOUT2,Specifies the timeout value for write transactions in region 2. Programming Mode: Quasi-dynamic Group 3" hexmask.long.word 0x10 0.--10. 1. "WQOS_MAP_TIMEOUT1,Specifies the timeout value for write transactions in region 0 and 1. Programming Mode: Quasi-dynamic Group 3" repeat 4. (list 0x0 0x1 0x2 0x3 )(list 0x0 0x8 0x10 0x18 ) group.long ($2+0xB0C)++0x3 line.long 0x0 "SARBASE$1,SAR Base Address Register n" hexmask.long.word 0x0 0.--11. 1. "BASE_ADDR,Base address for address region n specified as awaddr[UMCTL2_A_ADDRW-1:x] and araddr[UMCTL2_A_ADDRW-1:x] where x is determined by the minimum block size parameter UMCTL2_SARMINSIZE: (x=log2(block size)). Programming Mode: Static" repeat.end repeat 4. (list 0x0 0x1 0x2 0x3 )(list 0x0 0x8 0x10 0x18 ) group.long ($2+0xB10)++0x3 line.long 0x0 "SARSIZE$1,SAR Size Register n" hexmask.long.byte 0x0 0.--7. 1. "NBLOCKS,Number of blocks for address region n. This register determines the total size of the region in multiples of minimum block size as specified by the hardware parameter UMCTL2_SARMINSIZE. The register value is encoded as number of blocks = nblocks.." repeat.end group.long 0xB2C++0x3 line.long 0x0 "SBRCTL,Scrubber Control Register" hexmask.long.word 0x0 8.--20. 1. "SCRUB_INTERVAL,Scrub interval. (512 x scrub_interval) number of clock cycles between two scrub read commands. If set to 0 scrub commands are issued back-to-back. This mode of operation (scrub_interval=0) can typically be used for scrubbing the full.." bitfld.long 0x0 4.--6. "SCRUB_BURST,Scrub burst count. Determines the number of back-to-back scrub read commands that can be issued together when the controller is in one of the HW controlled low power modes with Sideband ECC both normal operation mode and low-power mode with.." "0,1,2,3,4,5,6,7" bitfld.long 0x0 2. "SCRUB_MODE,- scrub_mode:0 ECC scrubber performs reads - scrub_mode:1 ECC scrubber performs writes Programming Mode: Dynamic" "0,1" newline bitfld.long 0x0 1. "SCRUB_DURING_LOWPOWER,Continue scrubbing during low power. If set to 1 burst of scrubs is issued in hardware controlled low power modes. There are two such modes: automatically initiated by idleness or initiated by Hardware low power interface. If set.." "0,1" bitfld.long 0x0 0. "SCRUB_EN,Enables ECC scrubber. If set to 1 enables the scrubber to generate background read commands after the memories are initialized. If set to 0 disables the scrubber resets the address generator to 0 and clears the scrubber status. This bitfield.." "0,1" rgroup.long 0xB30++0x3 line.long 0x0 "SBRSTAT,Scrubber Status Register" bitfld.long 0x0 1. "SCRUB_DONE,Scrubber done. The controller sets this bit to 1 after full range of addresses are scrubbed once while scrub_interval is set to 0. Cleared if scrub_en is set to 0 (scrubber disabled) or scrub_interval is set to a non-zero value for normal.." "0,1" bitfld.long 0x0 0. "SCRUB_BUSY,Scrubber busy. The controller sets this bit to 1 when the scrubber logic has outstanding read commands being executed. Cleared when there are no active outstanding scrub reads in the system. Programming Mode: Dynamic" "0,1" group.long 0xB34++0x3 line.long 0x0 "SBRWDATA0,Scrubber Write Data Pattern0" hexmask.long 0x0 0.--31. 1. "SCRUB_PATTERN0,ECC Scrubber write data pattern for data bus[31:0] Programming Mode: Dynamic" group.long 0xB40++0xF line.long 0x0 "SBRSTART0,Scrubber Start Address Mask Register 0" hexmask.long 0x0 0.--31. 1. "SBR_ADDRESS_START_MASK_0,sbr_address_start_mask_0 holds the bits [31:0] of the starting address the ECC scrubber generates. The register must be programmed as explained in Address Configuration in ECC Scrub and Scrubber. The scrubber address registers.." line.long 0x4 "SBRSTART1,Scrubber Start Address Mask Register 1" hexmask.long.byte 0x4 0.--3. 1. "SBR_ADDRESS_START_MASK_1,sbr_address_start_mask_1 holds bits [MEMC_HIF_ADDR_WIDTH_MAX-1:32] of the starting address the ECC scrubber generates.The register must be programmed as explained in Address Configuration in ECC Scrub and Scrubber. The scrubber.." line.long 0x8 "SBRRANGE0,Scrubber Address Range Mask Register 0" hexmask.long 0x8 0.--31. 1. "SBR_ADDRESS_RANGE_MASK_0,sbr_address_range_mask_0 holds the bits [31:0] of the scrubber address range mask. The scrubber address range mask limits the address range that the ECC scrubber can generate.The register must be programmed as explained in.." line.long 0xC "SBRRANGE1,Scrubber Address Range Mask Register 1" hexmask.long.byte 0xC 0.--3. 1. "SBR_ADDRESS_RANGE_MASK_1,sbr_address_range_mask_1 holds the bits [MEMC_HIF_ADDR_WIDTH_MAX-1:32] of the scrubber address range mask. The scrubber address range mask limits the address range that the ECC scrubber can generate.The register must be.." rgroup.long 0xBF8++0x7 line.long 0x0 "UMCTL2_VER_NUMBER,UMCTL2 Version Number Register" hexmask.long 0x0 0.--31. 1. "VER_NUMBER,Indicates the Device Version Number value. Programming Mode: Static" line.long 0x4 "UMCTL2_VER_TYPE,UMCTL2 Version Type Register" hexmask.long 0x4 0.--31. 1. "VER_TYPE,Indicates the Device Version Type value. Programming Mode: Static" tree.end tree "UMCTL2_REGS_FREQ1 (uMCTL2 DDRC FREQ1 Registers)" base ad:0x8192 group.long 0x20++0x7 line.long 0x0 "DERATEEN,[FREQ1] Temperature Derate Enable Register" bitfld.long 0x0 12. "DERATE_MR4_TUF_DIS,Disables use of MR4 TUF flag (MR4[7]) bit. - 0 - Use MR4 TUF flag (MR4[7]) - 1 - Do not use MR4 TUF Flag (MR4[7]) For LPDDR4 it is recommended to set this register to 1. For LPDDR2 and LPDDR3 contact your memory vendor for.." "Use MR4 TUF flag,Do not use MR4 TUF Flag" newline bitfld.long 0x0 8.--10. "RC_DERATE_VALUE,Derate value of tRC for LPDDR4. - 0 - Derating uses +1 - 1 - Derating uses +2 - 2 - Derating uses +3 - 3 - Derating uses +4 Present only in designs configured to support LPDDR4. The required cycles for derating can be determined by.." "Derating uses +1,Derating uses +2,Derating uses +3,Derating uses +4,?,?,?,?" newline hexmask.long.byte 0x0 4.--7. 1. "DERATE_BYTE,This bit indicates which byte of the MRR data is used for derating. The maximum valid value depends on MEMC_DRAM_TOTAL_DATA_WIDTH. Present only in designs configured to support LPDDR2/LPDDR3/LPDDR4. Programming Mode: Static" newline bitfld.long 0x0 1.--2. "DERATE_VALUE,Derate value. - 0 - Derating uses +1 - 1 - Derating uses +2 Present only in designs configured to support LPDDR2/LPDDR3/LPDDR4. Set to 0 for all LPDDR2 speed grades as derating value of +1.875 ns is less than a core_ddrc_core_clk period. For.." "Derating uses +1,Derating uses +2,?,?" newline bitfld.long 0x0 0. "DERATE_ENABLE,Enables derating. - 0 - Timing parameter derating is disabled - 1 - Timing parameter derating is enabled using MR4 read value Present only in designs configured to support LPDDR2/LPDDR3/LPDDR4. This field must be set to '0' for.." "Timing parameter derating is disabled,Timing parameter derating is enabled using MR4.." line.long 0x4 "DERATEINT,[FREQ1] Temperature Derate Interval Register" hexmask.long 0x4 0.--31. 1. "MR4_READ_INTERVAL,Interval between two MR4 reads used to derate the timing parameters. Present only in designs configured to support LPDDR2/LPDDR3/LPDDR4. This register must not be set to zero. Unit: DFI clock cycles. Programming Mode: Static" group.long 0x34++0x3 line.long 0x0 "PWRTMG,[FREQ1] Low Power Timing Register" hexmask.long.byte 0x0 16.--23. 1. "SELFREF_TO_X32,After this many clocks of the DDRC command channel being idle the uMCTL2 automatically puts the SDRAM into self-refresh. The DDRC command channel is considered idle when there are no HIF commands outstanding. This must be enabled in the.." newline hexmask.long.byte 0x0 8.--15. 1. "T_DPD_X4096,Minimum deep power-down time. For mDDR value from the JEDEC specification is 0 as mDDR exits from deep power-down mode immediately after PWRCTL.deeppowerdown_en is de-asserted. For LPDDR2/LPDDR3 value from the JEDEC specification is 500us." newline hexmask.long.byte 0x0 0.--4. 1. "POWERDOWN_TO_X32,After this many clocks of the DDRC command channel being idle the uMCTL2 automatically puts the SDRAM into power-down. The DDRC command channel is considered idle when there are no HIF commands outstanding. This must be enabled in the.." group.long 0x50++0x3 line.long 0x0 "RFSHCTL0,[FREQ1] Refresh Control Register 0" hexmask.long.byte 0x0 20.--23. 1. "REFRESH_MARGIN,Threshold value in number of DFI clock cycles before the critical refresh or page timer expires. A critical refresh is to be issued before this threshold is reached. It is recommended that this not be changed from the default value.." newline hexmask.long.byte 0x0 12.--16. 1. "REFRESH_TO_X1_X32,If the refresh timer (tRFCnom also known as tREFI) has expired at least once then a speculative refresh may be performed. A speculative refresh is a refresh performed at a time when refresh would be useful. When the SDRAM bus is idle.." newline hexmask.long.byte 0x0 4.--9. 1. "REFRESH_BURST,The programmed value + 1 is the number of refresh timeouts that is allowed to accumulate before traffic is blocked and the refreshes are forced to execute. Closing pages to perform a refresh is a one-time penalty that must be paid for each.." newline bitfld.long 0x0 2. "PER_BANK_REFRESH,- 1 - Per bank refresh - 0 - All bank refresh Per bank refresh allows traffic to flow to other banks. Per bank refresh is not supported by all LPDDR2 devices but must be supported by all LPDDR3/LPDDR4 devices. Present only in designs.." "All bank refresh,Per bank refresh" group.long 0x64++0x7 line.long 0x0 "RFSHTMG,[FREQ1] Refresh Timing Register" bitfld.long 0x0 31. "T_RFC_NOM_X1_SEL,Specifies whether the RFSHTMG.t_rfc_nom_x1_x32 and RFSHCTL0.refresh_to_x1_x32 register values are x1 or x32. - 0 - x32 register values are used - 1 - x1 register values are used This applies only when per-bank refresh is enabled.." "x32 register values are used,x1 register values are used" newline hexmask.long.word 0x0 16.--27. 1. "T_RFC_NOM_X1_X32,Average time interval between refreshes per rank (Specification: 7.8us for DDR2 DDR3 and DDR4. See JEDEC specification for mDDR LPDDR2 LPDDR3 and LPDDR4). When the controller is operating in 1:1 mode set this register to.." newline bitfld.long 0x0 15. "LPDDR3_TREFBW_EN,Used only when LPDDR3 memory type is connected. Should only be changed when uMCTL2 is in reset. Specifies whether to use the tREFBW parameter (required by some LPDDR3 devices which comply with earlier versions of the LPDDR3 JEDEC.." "tREFBW parameter not used,tREFBW parameter used" newline hexmask.long.word 0x0 0.--9. 1. "T_RFC_MIN,tRFC (min): Minimum time from refresh to refresh or activate. When the controller is operating in 1:1 mode t_rfc_min must be set to RoundUp(tRFCmin/tCK). When the controller is operating in 1:2 mode t_rfc_min must be set to.." line.long 0x4 "RFSHTMG1,[FREQ1] Refresh Timing Register1" hexmask.long.byte 0x4 16.--23. 1. "T_PBR2PBR,LPDDR4:tpbR2pbR. Per-bank refresh to Per-bank refresh different bank Time. When the controller is operating in 1:1 frequency ratio mode program this to RoundUp(tpbR2pbR/tCK). When the controller is operating in 1:2 frequency ratio mode.." repeat 4. (list 0x3 0x4 0x6 0x7 )(list 0x0 0x4 0xC 0x10 ) group.long ($2+0xDC)++0x3 line.long 0x0 "INIT$1,[FREQ1] SDRAM Initialization Register 3" hexmask.long.word 0x0 16.--31. 1. "MR,DDR2:Indicates the value to write to MR register. Bit 8 is for DLL and the setting here is ignored. The uMCTL2 sets this bit appropriately. DDR3/DDR4: Value loaded into MR0 register. mDDR: Value to write to MR register. LPDDR2/LPDDR3/LPDDR4 - Value to.." newline hexmask.long.word 0x0 0.--15. 1. "EMR,DDR2: Indicates the value to write to EMR register. Bits 9:7 are for OCD and the setting in this register is ignored. The uMCTL2 sets those bits appropriately. DDR3/DDR4: Value to write to MR1 register Set bit 7 to 0. mDDR: Value to write to EMR.." repeat.end group.long 0xF4++0x3 line.long 0x0 "RANKCTL,[FREQ1] Rank Control Register" bitfld.long 0x0 26. "DIFF_RANK_WR_GAP_MSB,Only present for multi-rank configurations. 1-bit extension to be used when RANKCTL.diff_rank_wr_gap field needs to be set to a value greater than 0xF. Programming Mode: Quasi-dynamic Group 2" "?,bit extension to be used when RANKCTL" newline bitfld.long 0x0 24. "DIFF_RANK_RD_GAP_MSB,Only present for multi-rank configurations. 1-bit extension to be used when RANKCTL.diff_rank_rd_gap field needs to be set to a value greater than 0xF. Programming Mode: Quasi-dynamic Group 2" "?,bit extension to be used when RANKCTL" newline hexmask.long.byte 0x0 12.--15. 1. "MAX_RANK_WR,Only present for multi-rank configurations. Background: Writes to the same rank can be performed back-to-back. Writes to different ranks require additional gap dictated by the register RANKCTL.diff_rank_wr_gap. This is to avoid possible data.." newline hexmask.long.byte 0x0 8.--11. 1. "DIFF_RANK_WR_GAP,Only present for multi-rank configurations. Indicates the number of clocks of gap in data responses when performing consecutive writes to different ranks. This is used to switch the delays in the PHY to match the rank requirements. This.." newline hexmask.long.byte 0x0 4.--7. 1. "DIFF_RANK_RD_GAP,Only present for multi-rank configurations. Indicates the number of clocks of gap in data responses when performing consecutive reads to different ranks. This is used to switch the delays in the PHY to match the rank requirements. This.." newline hexmask.long.byte 0x0 0.--3. 1. "MAX_RANK_RD,Only present for multi-rank configurations. Background: Reads to the same rank can be performed back-to-back. Reads to different ranks require additional gap dictated by the register RANKCTL.diff_rank_rd_gap. This is to avoid possible data.." group.long 0x100++0x3F line.long 0x0 "DRAMTMG0,[FREQ1] SDRAM Timing Register 0" hexmask.long.byte 0x0 24.--30. 1. "WR2PRE,Specifies the minimum time between write and precharge to same bank. Specifications: WL + BL/2 + tWR = approximately 8 cycles + 15 ns = 14 clocks @400MHz and less for lower frequencies. where: - WL - Write latency - BL - Burst length. This must.." newline hexmask.long.byte 0x0 16.--21. 1. "T_FAW,tFAW - valid only when 8 or more banks(or banks x bank groups) are present. In 8-bank design at most 4 banks must be activated in a rolling window of tFAW cycles. When the controller is operating in 1:2 frequency ratio mode program this to.." newline hexmask.long.byte 0x0 8.--14. 1. "T_RAS_MAX,tRAS(max) - Specifies the maximum time between activate and precharge to same bank. This is the maximum time that a page can be kept open Minimum value of this register is 1. Zero is invalid. When the controller is operating in 1:1 frequency.." newline hexmask.long.byte 0x0 0.--5. 1. "T_RAS_MIN,tRAS(min) - Specifies the minimum time between activate and precharge to the same bank. When the controller is operating in 1:2 frequency mode 1T mode program this to tRAS(min)/2. No rounding up. When the controller is operating in 1:2.." line.long 0x4 "DRAMTMG1,[FREQ1] SDRAM Timing Register 1" hexmask.long.byte 0x4 16.--20. 1. "T_XP,tXP - Specifies the minimum time after power-down exit to any operation. For DDR3 this must be programmed to tXPDLL if slow powerdown exit is selected in MR0[12]. If C/A parity for DDR4 is used set to (tXP+PL) instead. If LPDDR4 is selected and.." newline hexmask.long.byte 0x4 8.--13. 1. "RD2PRE,tRTP - Specifies the minimum time from read to precharge of same bank. - DDR2 - tAL + BL/2 + max(tRTP 2) - 2 - DDR3 - tAL + max (tRTP 4) - DDR4 - Max of following two equations: tAL + max (tRTP 4) or RL + BL/2 - tRP (*). - mDDR - BL/2 - LPDDR2.." newline hexmask.long.byte 0x4 0.--6. 1. "T_RC,tRC - Specifies the minimum time between activates to same bank. When the controller is operating in 1:2 frequency ratio mode program this to (tRC/2) and round up to next integer value. Unit: DFI clock cycles. Programming Mode: Quasi-dynamic Group.." line.long 0x8 "DRAMTMG2,[FREQ1] SDRAM Timing Register 2" hexmask.long.byte 0x8 24.--29. 1. "WRITE_LATENCY,Set this field to WL. Indicates the Time from write command to write data on SDRAM interface. This must be set to WL. For mDDR it must be set to 1. Note that depending on the PHY if using RDIMM/LRDIMM it might be necessary to adjust the.." newline hexmask.long.byte 0x8 16.--21. 1. "READ_LATENCY,Set this field to RL. Indicates the time from read command to read data on SDRAM interface. This must be set to RL. Note that depending on the PHY if using RDIMM/LRDIMM it might be necessary to adjust the value of RL to compensate for the.." newline hexmask.long.byte 0x8 8.--13. 1. "RD2WR,DDR2/3/mDDR: RL + BL/2 + 2 - WL DDR4: RL + BL/2 + 1 + WR_PREAMBLE - WL LPDDR2/LPDDR3: RL + BL/2 + RU(tDQSCKmax/tCK) + 1 - WL LPDDR4(DQ ODT is Disabled): RL + BL/2 + RU(tDQSCKmax/tCK) + WR_PREAMBLE + RD_POSTAMBLE - WL LPDDR4(DQ ODT is Enabled): RL +.." newline hexmask.long.byte 0x8 0.--5. 1. "WR2RD,DDR4: CWL + PL + BL/2 + tWTR_L LPDDR2/3/4: WL + BL/2 + tWTR + 1 Others: CWL + BL/2 + tWTR In DDR4 minimum time from write command to read command for same bank group. In others minimum time from write command to read command. Includes time for.." line.long 0xC "DRAMTMG3,[FREQ1] SDRAM Timing Register 3" hexmask.long.word 0xC 20.--29. 1. "T_MRW,Indicates the time to wait after a mode register write or read (MRW or MRR). Present only in designs configured to support LPDDR2 LPDDR3 or LPDDR4. LPDDR2 typically requires value of 5. LPDDR3 typically requires value of 10. LPDDR4: Set this to.." newline hexmask.long.byte 0xC 12.--17. 1. "T_MRD,tMRD- Indicates the number of cycles to wait after a mode register write or read. Depending on the connected SDRAM tMRD represents: - DDR2/mDDR: Time from MRS to any command - DDR3/4: Time from MRS to MRS command - LPDDR2: not used - LPDDR3/4:.." newline hexmask.long.word 0xC 0.--9. 1. "T_MOD,tMOD - Parameter used only in DDR3 and DDR4. Indicates the number of cycles between load mode command and following non-load mode command. If C/A parity for DDR4 is used set to tMOD_PAR(tMOD+PL) instead. If CAL mode is enabled.." line.long 0x10 "DRAMTMG4,[FREQ1] SDRAM Timing Register 4" hexmask.long.byte 0x10 24.--28. 1. "T_RCD,tRCD - tAL: Indicates the minimum time from activate to read or write command to same bank. When the controller is operating in 1:2 frequency ratio mode program this to ((tRCD - tAL)/2) and round it up to the next integer value. Minimum value.." newline hexmask.long.byte 0x10 16.--19. 1. "T_CCD,DDR4: tCCD_L: This is the minimum time between two reads or two writes for same bank group. Others: tCCD: This is the minimum time between two reads or two writes. When the controller is operating in 1:2 frequency ratio mode program this to.." newline hexmask.long.byte 0x10 8.--11. 1. "T_RRD,DDR4: tRRD_L: This is the minimum time between activates from bank 'a' to bank 'b' for same bank group. Others: tRRD: Minimum time between activates from bank 'a' to bank 'b' When the controller is operating in 1:2 frequency ratio mode program.." newline hexmask.long.byte 0x10 0.--4. 1. "T_RP,tRP: Indicates the minimum time from single-bank precharge to activate of same bank. When the controller is operating in 1:1 frequency ratio mode t_rp must be set to RoundUp(tRP/tCK). When the controller is operating in 1:2 frequency ratio mode.." line.long 0x14 "DRAMTMG5,[FREQ1] SDRAM Timing Register 5" hexmask.long.byte 0x14 24.--27. 1. "T_CKSRX,This is the time before self-refresh Exit that CK is maintained as a valid clock before issuing SRX. Specifies the clock stable time before SRX. Recommended settings: - mDDR - 1 - LPDDR2 - 2 - LPDDR3 - 2 - LPDDR4 - tCKCKEH - DDR2 - 1 - DDR3 -.." newline hexmask.long.byte 0x14 16.--19. 1. "T_CKSRE,This is the time after self-refresh Down Entry that CK is maintained as a valid clock. Specifies the clock disable delay after SRE. Recommended settings: - mDDR - 0 - LPDDR2 - 2 - LPDDR3 - 2 - LPDDR4 - tCKELCK - DDR2 - 1 - DDR3 - Max (10 ns 5.." newline hexmask.long.byte 0x14 8.--13. 1. "T_CKESR,Indicates the minimum CKE low width for self-refresh or self-refresh power down entry to exit timing in memory clock cycles. Recommended settings: - mDDR - tRFC - LPDDR2 - tCKESR - LPDDR3 - tCKESR - LPDDR4 - max(tCKE tSR) - DDR2 - tCKE - DDR3 -.." newline hexmask.long.byte 0x14 0.--4. 1. "T_CKE,Indicates the minimum number of cycles of CKE HIGH/LOW during power-down and self-refresh. - LPDDR2/LPDDR3 mode - Set this to the larger of tCKE or tCKESR - LPDDR4 mode - Set this to the larger of tCKE or tSR - Non-LPDDR2/non-LPDDR3/non-LPDDR4.." line.long 0x18 "DRAMTMG6,[FREQ1] SDRAM Timing Register 6" hexmask.long.byte 0x18 24.--27. 1. "T_CKDPDE,This is the time after Deep Power Down Entry that CK is maintained as a valid clock. Specifies the clock disable delay after DPDE. Recommended settings: - mDDR: 0 - LPDDR2: 2 - LPDDR3: 2 When the controller is operating in 1:2 frequency ratio.." newline hexmask.long.byte 0x18 16.--19. 1. "T_CKDPDX,This is the time before Deep Power Down Exit that CK is maintained as a valid clock before issuing DPDX. Specifies the clock stable time before DPDX. Recommended settings: - mDDR - 1 - LPDDR2 - 2 - LPDDR3 - 2 When the controller is operating in.." newline hexmask.long.byte 0x18 0.--3. 1. "T_CKCSX,This is the time before Clock Stop Exit that CK is maintained as a valid clock before issuing Clock Stop Exit. Specifies the clock stable time before next command after Clock Stop Exit. Recommended settings: - mDDR - 1 - LPDDR2 - tXP + 2 - LPDDR3.." line.long 0x1C "DRAMTMG7,[FREQ1] SDRAM Timing Register 7" hexmask.long.byte 0x1C 8.--11. 1. "T_CKPDE,This is the time after Power Down Entry that CK is maintained as a valid clock. Specifies the clock disable delay after PDE. Recommended settings: - mDDR - 0 - LPDDR2 - 2 - LPDDR3 - 2 - LPDDR4 - tCKELCK When using DDR2/3/4 SDRAM this register.." newline hexmask.long.byte 0x1C 0.--3. 1. "T_CKPDX,This is the time before Power Down Exit that CK is maintained as a valid clock before issuing PDX. Specifies the clock stable time before PDX. Recommended settings: - mDDR - 0 - LPDDR2 - 2 - LPDDR3 - 2 - LPDDR4 - tCKCKEH When using DDR2/3/4 SDRAM.." line.long 0x20 "DRAMTMG8,[FREQ1] SDRAM Timing Register 8" hexmask.long.byte 0x20 24.--30. 1. "T_XS_FAST_X32,tXS_FAST: Exit self-refresh to ZQCL ZQCS and MRS (only CL WR RTP and Geardown mode). When the controller is operating in 1:2 frequency ratio mode program this to the previous value divided by 2 and round up to next integer value. Note:.." newline hexmask.long.byte 0x20 16.--22. 1. "T_XS_ABORT_X32,tXS_ABORT: Exit self-refresh to commands not requiring a locked DLL in self-refresh Abort. When the controller is operating in 1:2 frequency ratio mode program this to the previous value divided by 2 and round up to next integer value." newline hexmask.long.byte 0x20 8.--14. 1. "T_XS_DLL_X32,tXSDLL: Exit self-refresh to commands requiring a locked DLL. When the controller is operating in 1:2 frequency ratio mode program this to the previous value divided by 2 and round up to next integer value. Note: Used only for DDR2 DDR3.." newline hexmask.long.byte 0x20 0.--6. 1. "T_XS_X32,tXS: Exit self-refresh to commands not requiring a locked DLL. When the controller is operating in 1:2 frequency ratio mode program this to the previous value divided by 2 and round up to next integer value. Note: Used only for DDR2 DDR3 and.." line.long 0x24 "DRAMTMG9,[FREQ1] SDRAM Timing Register 9" bitfld.long 0x24 30. "DDR4_WR_PREAMBLE,DDR4 Write preamble mode. - 0 - 1tCK preamble - 1 - 2tCK preamble Present only with MEMC_FREQ_RATIO=2. Programming Mode: Quasi-dynamic Group 2 Group 4" "0,1" newline bitfld.long 0x24 16.--18. "T_CCD_S,tCCD_S: This is the minimum time between two reads or two writes for different bank group. For bank switching (from bank 'a' to bank 'b') the minimum time is this value + 1. When the controller is operating in 1:2 frequency ratio mode program.." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x24 8.--11. 1. "T_RRD_S,tRRD_S: This is the minimum time between activates from bank 'a' to bank 'b' for different bank group. When the controller is operating in 1:2 frequency ratio mode program this to (tRRD_S/2) and round it up to the next integer value. Present.." newline hexmask.long.byte 0x24 0.--5. 1. "WR2RD_S,CWL + PL + BL/2 + tWTR_S Minimum time from write command to read command for different bank group. Includes time for bus turnaround recovery times and all per-bank per-rank and global constraints. Present only in designs configured to support.." line.long 0x28 "DRAMTMG10,[FREQ1] SDRAM Timing Register 10" hexmask.long.byte 0x28 16.--20. 1. "T_SYNC_GEAR,Indicates the time between MRS command and the sync pulse time. This must be even number of clocks. For DDR4-2666 and DDR4-3200 this parameter is defined as tMOD(min)+4nCK tMOD(min) is greater of 24nCK or 15ns 15ns / .625ns = 24 Max value.." newline hexmask.long.byte 0x28 8.--12. 1. "T_CMD_GEAR,Indicates a sync pulse to first valid command. For DDR4-2666 and DDR4-3200 this parameter is defined as tMOD(min) tMOD(min) is greater of 24nCK or 15ns 15ns / .625ns = 24 Max value for this register is 24 When the controller is operating in.." newline bitfld.long 0x28 2.--3. "T_GEAR_SETUP,Indicates the geardown setup time. Minimum value of this register is 1. Zero is invalid. For DDR4-2666 and DDR4-3200 this parameter is defined as 2 clks When the controller is operating in 1:2 frequency ratio mode program this to.." "0,1,2,3" newline bitfld.long 0x28 0.--1. "T_GEAR_HOLD,Indicates the geardown hold time. Minimum value of this register is 1. Zero is invalid. For DDR4-2666 and DDR4-3200 this parameter is defined as 2 clks When the controller is operating in 1:2 frequency ratio mode program this to.." "0,1,2,3" line.long 0x2C "DRAMTMG11,[FREQ1] SDRAM Timing Register 11" hexmask.long.byte 0x2C 24.--30. 1. "POST_MPSM_GAP_X32,tXMPDLL: This is the minimum Exit MPSM to commands requiring a locked DLL. When the controller is operating in 1:2 frequency ratio mode program this to (tXMPDLL/2) and round it up to the next integer value. Present only in designs.." newline hexmask.long.byte 0x2C 16.--20. 1. "T_MPX_LH,tMPX_LH: This is the minimum CS_n Low hold time to CKE rising edge. When the controller is operating in 1:2 frequency ratio mode program this to RoundUp(tMPX_LH/2)+1. Present only in designs configured to support DDR4. Unit: DFI clock cycles." newline bitfld.long 0x2C 8.--9. "T_MPX_S,tMPX_S: This is the minimum time CS setup time to CKE. When the controller is operating in 1:2 frequency ratio mode program this to (tMPX_S/2) and round it up to the next integer value. Present only in designs configured to support DDR4. Unit:.." "0,1,2,3" newline hexmask.long.byte 0x2C 0.--4. 1. "T_CKMPE,tCKMPE: This is the minimum valid clock requirement after MPSM entry. Present only in designs configured to support DDR4. When the controller is operating in 1:2 frequency ratio mode divide the value calculated using the previous equation by 2.." line.long 0x30 "DRAMTMG12,[FREQ1] SDRAM Timing Register 12" hexmask.long.byte 0x30 24.--29. 1. "T_WR_MPR,This bit is used only in DDR4. Cycles between MPR Write and other command. Set this to tMOD + AL (or tMOD + PL + AL if C/A parity is also used). When the controller is operating in 1:2 frequency ratio mode program this to (tWR_MPR/2) and round.." newline bitfld.long 0x30 16.--17. "T_CMDCKE,tCMDCKE: Indicates the delay from valid command to CKE input LOW. Set this to the larger of tESCKE or tCMDCKE When the controller is operating in 1:2 frequency ratio mode program this to (max(tESCKE tCMDCKE)/2) and round it up to the next.." "0,1,2,3" newline hexmask.long.byte 0x30 0.--4. 1. "T_MRD_PDA,tMRD_PDA: This is the Mode Register Set command cycle time in PDA mode. When the controller is operating in 1:2 frequency ratio mode program this to (tMRD_PDA/2) and round it up to the next integer value. Unit: DFI clock cycles. Programming.." line.long 0x34 "DRAMTMG13,[FREQ1] SDRAM Timing Register 13" hexmask.long.byte 0x34 24.--30. 1. "ODTLOFF,LPDDR4: ODTLoff: This is the latency from CAS-2 command to ODToff reference. When the controller is operating in 1:2 frequency ratio mode program this to (ODTLoff/2) and round it up to the next integer value. Unit: DFI clock cycles. Programming.." newline hexmask.long.byte 0x34 16.--21. 1. "T_CCD_MW,LPDDR4: tCCDMW: This is the minimum time from write or masked write to masked write command for same bank. When the controller is operating in 1:2 frequency ratio mode program this to (tCCDMW/2) and round it up to the next integer value. Unit:.." newline bitfld.long 0x34 0.--2. "T_PPD,LPDDR4: tPPD: This is the minimum time from precharge to precharge command. When the controller is operating in 1:2 frequency ratio mode program this to (tPPD/2) and round it up to the next integer value. Unit: DFI clock cycles. Programming Mode:.." "?,?,?,?,tPPD: This is the minimum time from precharge to..,?,?,?" line.long 0x38 "DRAMTMG14,[FREQ1] SDRAM Timing Register 14" hexmask.long.word 0x38 0.--11. 1. "T_XSR,tXSR: This is the exit self-refresh to any command. When the controller is operating in 1:2 frequency ratio mode program this to the previous value divided by 2 and round up to next integer value. The value 0xfff is illegal for this register.." line.long 0x3C "DRAMTMG15,[FREQ1] SDRAM Timing Register 15" bitfld.long 0x3C 31. "EN_DFI_LP_T_STAB,- 1 - Enable using tSTAB when exiting DFI LP. This must be set when the PHY is stopping the clock during DFI LP to save maximum power. - 0 - Disable using tSTAB when exiting DFI LP. Programming Mode: Quasi-dynamic Group 2 Group 4" "Disable using tSTAB when exiting DFI LP,Enable using tSTAB when exiting DFI LP" newline hexmask.long.byte 0x3C 0.--7. 1. "T_STAB_X32,tSTAB: Stabilization time. It is required in the following two cases for DDR3/DDR4 RDIMM: - When exiting power saving mode if the clock is stopped after re-enabling it the clock must be stable for a time specified by tSTAB - In the case of.." group.long 0x180++0x3 line.long 0x0 "ZQCTL0,[FREQ1] ZQ Control Register 0" bitfld.long 0x0 31. "DIS_AUTO_ZQ,- 1 - Disable uMCTL2 generation of ZQCS/MPC(ZQ calibration) command. Register DBGCMD.zq_calib_short can be used instead to issue ZQ calibration request from APB module - 0 - Internally generate ZQCS/MPC(ZQ calibration) commands based on.." "Internally generate ZQCS/MPC,Disable uMCTL2 generation of ZQCS/MPC" newline bitfld.long 0x0 30. "DIS_SRX_ZQCL,- 1 - Disable issuing of ZQCL/MPC(ZQ calibration) command at self-refresh/SR-Powerdown exit. Only applicable when run in DDR3 or DDR4 or LPDDR2 or LPDDR3 or LPDDR4 mode - 0 - Enable issuing of ZQCL/MPC(ZQ calibration) command at.." "Enable issuing of ZQCL/MPC,Disable issuing of ZQCL/MPC" newline bitfld.long 0x0 29. "ZQ_RESISTOR_SHARED,- 1 - Denotes that ZQ resistor is shared between ranks. Means ZQinit/ZQCL/ZQCS/MPC(ZQ calibration) commands are sent to one rank at a time with tZQinit/tZQCL/tZQCS/tZQCAL/tZQLAT timing met between commands so that commands to different.." "ZQ resistor is not shared,Denotes that ZQ resistor is shared between ranks" newline bitfld.long 0x0 28. "DIS_MPSMX_ZQCL,- 1 - Disable issuing of ZQCL command at Maximum Power Saving Mode exit. Only applicable when run in DDR4 mode - 0 - Enable issuing of ZQCL command at Maximum Power Saving Mode exit. Only applicable when run in DDR4 mode This is only.." "Enable issuing of ZQCL command at Maximum Power..,Disable issuing of ZQCL command at Maximum Power.." newline hexmask.long.word 0x0 16.--26. 1. "T_ZQ_LONG_NOP,tZQoper for DDR3/DDR4 tZQCL for LPDDR2/LPDDR3 tZQCAL for LPDDR4: Number of DFI clock cycles of NOP required after a ZQCL (ZQ calibration long)/MPC(ZQ Start) command is issued to SDRAM. When the controller is operating in 1:2 frequency.." newline hexmask.long.word 0x0 0.--9. 1. "T_ZQ_SHORT_NOP,tZQCS for DDR3/DD4/LPDDR2/LPDDR3 tZQLAT for LPDDR4: Number of DFI clock cycles of NOP required after a ZQCS (ZQ calibration short)/MPC(ZQ Latch) command is issued to SDRAM. When the controller is operating in 1:2 frequency ratio mode.." group.long 0x190++0x7 line.long 0x0 "DFITMG0,[FREQ1] DFI Timing Register 0" hexmask.long.byte 0x0 24.--28. 1. "DFI_T_CTRL_DELAY,Specifies the number of DFI clock cycles after an assertion or de-assertion of the DFI control signals that the control signals at the PHY-DRAM interface reflect the assertion or de-assertion. If the DFI clock and the memory clock are.." newline bitfld.long 0x0 23. "DFI_RDDATA_USE_DFI_PHY_CLK,Defines whether dfi_rddata_en/dfi_rddata/dfi_rddata_valid is generated using HDR (DFI clock) or SDR (DFI PHY clock) values. Selects whether value in DFITMG0.dfi_t_rddata_en is in terms of HDR (DFI clock) or SDR (DFI PHY clock).." "Else,?" newline hexmask.long.byte 0x0 16.--22. 1. "DFI_T_RDDATA_EN,Time from the assertion of a read command on the DFI interface to the assertion of the dfi_rddata_en signal. Refer to PHY specification for correct value. This corresponds to the DFI parameter trddata_en. Note that depending on the PHY.." newline bitfld.long 0x0 15. "DFI_WRDATA_USE_DFI_PHY_CLK,Defines whether dfi_wrdata_en/dfi_wrdata/dfi_wrdata_mask is generated using HDR (DFI clock) or SDR (DFI PHY clock) values. Selects whether value in DFITMG0.dfi_tphy_wrlat is in terms of HDR (DFI clock) or SDR (DFI PHY clock).." "Else,?" newline hexmask.long.byte 0x0 8.--13. 1. "DFI_TPHY_WRDATA,Specifies the number of clock cycles between when dfi_wrdata_en is asserted to when the associated write data is driven on the dfi_wrdata signal. This corresponds to the DFI timing parameter tphy_wrdata. For more information on correct.." newline hexmask.long.byte 0x0 0.--5. 1. "DFI_TPHY_WRLAT,Write latency. Number of clocks from the write command to write data enable (dfi_wrdata_en). This corresponds to the DFI timing parameter tphy_wrlat. Refer to PHY specification for correct value.Note that depending on the PHY if using.." line.long 0x4 "DFITMG1,[FREQ1] DFI Timing Register 1" hexmask.long.byte 0x4 28.--31. 1. "DFI_T_CMD_LAT,Specifies the number of DFI PHY clock cycles between when the dfi_cs signal is asserted and when the associated command is driven. This field is used for CAL mode must be set to '0' or tCAL which matches the CAL mode register setting in.." newline bitfld.long 0x4 24.--25. "DFI_T_PARIN_LAT,Specifies the number of DFI PHY clock cycles between when the dfi_cs signal is asserted and when the associated dfi_parity_in signal is driven. Unit: DFI PHY clock cycles. Programming Mode: Quasi-dynamic Group 4" "0,1,2,3" newline hexmask.long.byte 0x4 16.--20. 1. "DFI_T_WRDATA_DELAY,Specifies the number of DFI clock cycles between when the dfi_wrdata_en signal is asserted and when the corresponding write data transfer is completed on the DRAM bus. This corresponds to the DFI timing parameter twrdata_delay. For.." newline hexmask.long.byte 0x4 8.--12. 1. "DFI_T_DRAM_CLK_DISABLE,Specifies the number of DFI clock cycles from the assertion of the dfi_dram_clk_disable signal on the DFI until the clock to the DRAM memory devices at the PHY-DRAM boundary maintains a low value. If the DFI clock and the memory.." newline hexmask.long.byte 0x4 0.--4. 1. "DFI_T_DRAM_CLK_ENABLE,Specifies the number of DFI clock cycles from the de-assertion of the dfi_dram_clk_disable signal on the DFI until the first valid rising edge of the clock to the DRAM memory devices at the PHY-DRAM boundary. If the DFI clock and.." group.long 0x1B4++0x7 line.long 0x0 "DFITMG2,[FREQ1] DFI Timing Register 2" hexmask.long.byte 0x0 8.--14. 1. "DFI_TPHY_RDCSLAT,specifies the number of DFI PHY clock cycles between when a read command is sent on the DFI control interface and when the associated dfi_rddata_cs signal is asserted. This corresponds to the DFI timing parameter tphy_rdcslat. Refer to.." newline hexmask.long.byte 0x0 0.--5. 1. "DFI_TPHY_WRCSLAT,Specifies the number of DFI PHY clock cycles between when a write command is sent on the DFI control interface and when the associated dfi_wrdata_cs signal is asserted. This corresponds to the DFI timing parameter tphy_wrcslat. For more.." line.long 0x4 "DFITMG3,[FREQ1] DFI Timing Register 3" hexmask.long.byte 0x4 0.--4. 1. "DFI_T_GEARDOWN_DELAY,The delay from dfi_geardown_en assertion to the time of the PHY being ready to receive commands. Refer to PHY specification for correct value. When the controller is operating in 1:2 frequency ratio mode program this to.." group.long 0x240++0x3 line.long 0x0 "ODTCFG,[FREQ1] ODT Configuration Register" hexmask.long.byte 0x0 24.--27. 1. "WR_ODT_HOLD,DFI PHY clock cycles to hold ODT for a write command. The minimum supported value is 2. Recommended values: DDR2: - BL8 - 0x5 (DDR2-400/533/667) 0x6 (DDR2-800) 0x7 (DDR2-1066) - BL4 - 0x3 (DDR2-400/533/667) 0x4 (DDR2-800) 0x5 (DDR2-1066).." newline hexmask.long.byte 0x0 16.--20. 1. "WR_ODT_DELAY,Indicates the delay in DFI PHY clock cycles from issuing a write command to setting ODT values associated with that command. ODT setting must remain constant for the entire time that DQS is driven by the uMCTL2. Recommended values: DDR2: -.." newline hexmask.long.byte 0x0 8.--11. 1. "RD_ODT_HOLD,DFI PHY clock cycles to hold ODT for a read command. The minimum supported value is 2. Recommended values: DDR2: - BL8 - 0x6 (not DDR2-1066) 0x7 (DDR2-1066) - BL4 - 0x4 (not DDR2-1066) 0x5 (DDR2-1066) DDR3: - BL8 - 0x6 DDR4: - BL8 - 5 +.." newline hexmask.long.byte 0x0 2.--6. 1. "RD_ODT_DELAY,Indicates the delay in DFI PHY clock cycles from issuing a read command to setting ODT values associated with that command. ODT setting must remain constant for the entire time that DQS is driven by the uMCTL2. Recommended values: DDR2: -.." tree.end tree "UMCTL2_REGS_FREQ2 (uMCTL2 DDRC FERQ2 Registers)" base ad:0x12288 group.long 0x20++0x7 line.long 0x0 "DERATEEN,[FREQ2] Temperature Derate Enable Register" bitfld.long 0x0 12. "DERATE_MR4_TUF_DIS,Disables use of MR4 TUF flag (MR4[7]) bit. - 0 - Use MR4 TUF flag (MR4[7]) - 1 - Do not use MR4 TUF Flag (MR4[7]) For LPDDR4 it is recommended to set this register to 1. For LPDDR2 and LPDDR3 contact your memory vendor for.." "Use MR4 TUF flag,Do not use MR4 TUF Flag" newline bitfld.long 0x0 8.--10. "RC_DERATE_VALUE,Derate value of tRC for LPDDR4. - 0 - Derating uses +1 - 1 - Derating uses +2 - 2 - Derating uses +3 - 3 - Derating uses +4 Present only in designs configured to support LPDDR4. The required cycles for derating can be determined by.." "Derating uses +1,Derating uses +2,Derating uses +3,Derating uses +4,?,?,?,?" newline hexmask.long.byte 0x0 4.--7. 1. "DERATE_BYTE,This bit indicates which byte of the MRR data is used for derating. The maximum valid value depends on MEMC_DRAM_TOTAL_DATA_WIDTH. Present only in designs configured to support LPDDR2/LPDDR3/LPDDR4. Programming Mode: Static" newline bitfld.long 0x0 1.--2. "DERATE_VALUE,Derate value. - 0 - Derating uses +1 - 1 - Derating uses +2 Present only in designs configured to support LPDDR2/LPDDR3/LPDDR4. Set to 0 for all LPDDR2 speed grades as derating value of +1.875 ns is less than a core_ddrc_core_clk period. For.." "Derating uses +1,Derating uses +2,?,?" newline bitfld.long 0x0 0. "DERATE_ENABLE,Enables derating. - 0 - Timing parameter derating is disabled - 1 - Timing parameter derating is enabled using MR4 read value Present only in designs configured to support LPDDR2/LPDDR3/LPDDR4. This field must be set to '0' for.." "Timing parameter derating is disabled,Timing parameter derating is enabled using MR4.." line.long 0x4 "DERATEINT,[FREQ2] Temperature Derate Interval Register" hexmask.long 0x4 0.--31. 1. "MR4_READ_INTERVAL,Interval between two MR4 reads used to derate the timing parameters. Present only in designs configured to support LPDDR2/LPDDR3/LPDDR4. This register must not be set to zero. Unit: DFI clock cycles. Programming Mode: Static" group.long 0x34++0x3 line.long 0x0 "PWRTMG,[FREQ2] Low Power Timing Register" hexmask.long.byte 0x0 16.--23. 1. "SELFREF_TO_X32,After this many clocks of the DDRC command channel being idle the uMCTL2 automatically puts the SDRAM into self-refresh. The DDRC command channel is considered idle when there are no HIF commands outstanding. This must be enabled in the.." newline hexmask.long.byte 0x0 8.--15. 1. "T_DPD_X4096,Minimum deep power-down time. For mDDR value from the JEDEC specification is 0 as mDDR exits from deep power-down mode immediately after PWRCTL.deeppowerdown_en is de-asserted. For LPDDR2/LPDDR3 value from the JEDEC specification is 500us." newline hexmask.long.byte 0x0 0.--4. 1. "POWERDOWN_TO_X32,After this many clocks of the DDRC command channel being idle the uMCTL2 automatically puts the SDRAM into power-down. The DDRC command channel is considered idle when there are no HIF commands outstanding. This must be enabled in the.." group.long 0x50++0x3 line.long 0x0 "RFSHCTL0,[FREQ2] Refresh Control Register 0" hexmask.long.byte 0x0 20.--23. 1. "REFRESH_MARGIN,Threshold value in number of DFI clock cycles before the critical refresh or page timer expires. A critical refresh is to be issued before this threshold is reached. It is recommended that this not be changed from the default value.." newline hexmask.long.byte 0x0 12.--16. 1. "REFRESH_TO_X1_X32,If the refresh timer (tRFCnom also known as tREFI) has expired at least once then a speculative refresh may be performed. A speculative refresh is a refresh performed at a time when refresh would be useful. When the SDRAM bus is idle.." newline hexmask.long.byte 0x0 4.--9. 1. "REFRESH_BURST,The programmed value + 1 is the number of refresh timeouts that is allowed to accumulate before traffic is blocked and the refreshes are forced to execute. Closing pages to perform a refresh is a one-time penalty that must be paid for each.." newline bitfld.long 0x0 2. "PER_BANK_REFRESH,- 1 - Per bank refresh - 0 - All bank refresh Per bank refresh allows traffic to flow to other banks. Per bank refresh is not supported by all LPDDR2 devices but must be supported by all LPDDR3/LPDDR4 devices. Present only in designs.." "All bank refresh,Per bank refresh" group.long 0x64++0x7 line.long 0x0 "RFSHTMG,[FREQ2] Refresh Timing Register" bitfld.long 0x0 31. "T_RFC_NOM_X1_SEL,Specifies whether the RFSHTMG.t_rfc_nom_x1_x32 and RFSHCTL0.refresh_to_x1_x32 register values are x1 or x32. - 0 - x32 register values are used - 1 - x1 register values are used This applies only when per-bank refresh is enabled.." "x32 register values are used,x1 register values are used" newline hexmask.long.word 0x0 16.--27. 1. "T_RFC_NOM_X1_X32,Average time interval between refreshes per rank (Specification: 7.8us for DDR2 DDR3 and DDR4. See JEDEC specification for mDDR LPDDR2 LPDDR3 and LPDDR4). When the controller is operating in 1:1 mode set this register to.." newline bitfld.long 0x0 15. "LPDDR3_TREFBW_EN,Used only when LPDDR3 memory type is connected. Should only be changed when uMCTL2 is in reset. Specifies whether to use the tREFBW parameter (required by some LPDDR3 devices which comply with earlier versions of the LPDDR3 JEDEC.." "tREFBW parameter not used,tREFBW parameter used" newline hexmask.long.word 0x0 0.--9. 1. "T_RFC_MIN,tRFC (min): Minimum time from refresh to refresh or activate. When the controller is operating in 1:1 mode t_rfc_min must be set to RoundUp(tRFCmin/tCK). When the controller is operating in 1:2 mode t_rfc_min must be set to.." line.long 0x4 "RFSHTMG1,[FREQ2] Refresh Timing Register1" hexmask.long.byte 0x4 16.--23. 1. "T_PBR2PBR,LPDDR4:tpbR2pbR. Per-bank refresh to Per-bank refresh different bank Time. When the controller is operating in 1:1 frequency ratio mode program this to RoundUp(tpbR2pbR/tCK). When the controller is operating in 1:2 frequency ratio mode.." repeat 4. (list 0x3 0x4 0x6 0x7 )(list 0x0 0x4 0xC 0x10 ) group.long ($2+0xDC)++0x3 line.long 0x0 "INIT$1,[FREQ2] SDRAM Initialization Register 3" hexmask.long.word 0x0 16.--31. 1. "MR,DDR2:Indicates the value to write to MR register. Bit 8 is for DLL and the setting here is ignored. The uMCTL2 sets this bit appropriately. DDR3/DDR4: Value loaded into MR0 register. mDDR: Value to write to MR register. LPDDR2/LPDDR3/LPDDR4 - Value to.." newline hexmask.long.word 0x0 0.--15. 1. "EMR,DDR2: Indicates the value to write to EMR register. Bits 9:7 are for OCD and the setting in this register is ignored. The uMCTL2 sets those bits appropriately. DDR3/DDR4: Value to write to MR1 register Set bit 7 to 0. mDDR: Value to write to EMR.." repeat.end group.long 0xF4++0x3 line.long 0x0 "RANKCTL,[FREQ2] Rank Control Register" bitfld.long 0x0 26. "DIFF_RANK_WR_GAP_MSB,Only present for multi-rank configurations. 1-bit extension to be used when RANKCTL.diff_rank_wr_gap field needs to be set to a value greater than 0xF. Programming Mode: Quasi-dynamic Group 2" "?,bit extension to be used when RANKCTL" newline bitfld.long 0x0 24. "DIFF_RANK_RD_GAP_MSB,Only present for multi-rank configurations. 1-bit extension to be used when RANKCTL.diff_rank_rd_gap field needs to be set to a value greater than 0xF. Programming Mode: Quasi-dynamic Group 2" "?,bit extension to be used when RANKCTL" newline hexmask.long.byte 0x0 12.--15. 1. "MAX_RANK_WR,Only present for multi-rank configurations. Background: Writes to the same rank can be performed back-to-back. Writes to different ranks require additional gap dictated by the register RANKCTL.diff_rank_wr_gap. This is to avoid possible data.." newline hexmask.long.byte 0x0 8.--11. 1. "DIFF_RANK_WR_GAP,Only present for multi-rank configurations. Indicates the number of clocks of gap in data responses when performing consecutive writes to different ranks. This is used to switch the delays in the PHY to match the rank requirements. This.." newline hexmask.long.byte 0x0 4.--7. 1. "DIFF_RANK_RD_GAP,Only present for multi-rank configurations. Indicates the number of clocks of gap in data responses when performing consecutive reads to different ranks. This is used to switch the delays in the PHY to match the rank requirements. This.." newline hexmask.long.byte 0x0 0.--3. 1. "MAX_RANK_RD,Only present for multi-rank configurations. Background: Reads to the same rank can be performed back-to-back. Reads to different ranks require additional gap dictated by the register RANKCTL.diff_rank_rd_gap. This is to avoid possible data.." group.long 0x100++0x3F line.long 0x0 "DRAMTMG0,[FREQ2] SDRAM Timing Register 0" hexmask.long.byte 0x0 24.--30. 1. "WR2PRE,Specifies the minimum time between write and precharge to same bank. Specifications: WL + BL/2 + tWR = approximately 8 cycles + 15 ns = 14 clocks @400MHz and less for lower frequencies. where: - WL - Write latency - BL - Burst length. This must.." newline hexmask.long.byte 0x0 16.--21. 1. "T_FAW,tFAW - valid only when 8 or more banks(or banks x bank groups) are present. In 8-bank design at most 4 banks must be activated in a rolling window of tFAW cycles. When the controller is operating in 1:2 frequency ratio mode program this to.." newline hexmask.long.byte 0x0 8.--14. 1. "T_RAS_MAX,tRAS(max) - Specifies the maximum time between activate and precharge to same bank. This is the maximum time that a page can be kept open Minimum value of this register is 1. Zero is invalid. When the controller is operating in 1:1 frequency.." newline hexmask.long.byte 0x0 0.--5. 1. "T_RAS_MIN,tRAS(min) - Specifies the minimum time between activate and precharge to the same bank. When the controller is operating in 1:2 frequency mode 1T mode program this to tRAS(min)/2. No rounding up. When the controller is operating in 1:2.." line.long 0x4 "DRAMTMG1,[FREQ2] SDRAM Timing Register 1" hexmask.long.byte 0x4 16.--20. 1. "T_XP,tXP - Specifies the minimum time after power-down exit to any operation. For DDR3 this must be programmed to tXPDLL if slow powerdown exit is selected in MR0[12]. If C/A parity for DDR4 is used set to (tXP+PL) instead. If LPDDR4 is selected and.." newline hexmask.long.byte 0x4 8.--13. 1. "RD2PRE,tRTP - Specifies the minimum time from read to precharge of same bank. - DDR2 - tAL + BL/2 + max(tRTP 2) - 2 - DDR3 - tAL + max (tRTP 4) - DDR4 - Max of following two equations: tAL + max (tRTP 4) or RL + BL/2 - tRP (*). - mDDR - BL/2 - LPDDR2.." newline hexmask.long.byte 0x4 0.--6. 1. "T_RC,tRC - Specifies the minimum time between activates to same bank. When the controller is operating in 1:2 frequency ratio mode program this to (tRC/2) and round up to next integer value. Unit: DFI clock cycles. Programming Mode: Quasi-dynamic Group.." line.long 0x8 "DRAMTMG2,[FREQ2] SDRAM Timing Register 2" hexmask.long.byte 0x8 24.--29. 1. "WRITE_LATENCY,Set this field to WL. Indicates the Time from write command to write data on SDRAM interface. This must be set to WL. For mDDR it must be set to 1. Note that depending on the PHY if using RDIMM/LRDIMM it might be necessary to adjust the.." newline hexmask.long.byte 0x8 16.--21. 1. "READ_LATENCY,Set this field to RL. Indicates the time from read command to read data on SDRAM interface. This must be set to RL. Note that depending on the PHY if using RDIMM/LRDIMM it might be necessary to adjust the value of RL to compensate for the.." newline hexmask.long.byte 0x8 8.--13. 1. "RD2WR,DDR2/3/mDDR: RL + BL/2 + 2 - WL DDR4: RL + BL/2 + 1 + WR_PREAMBLE - WL LPDDR2/LPDDR3: RL + BL/2 + RU(tDQSCKmax/tCK) + 1 - WL LPDDR4(DQ ODT is Disabled): RL + BL/2 + RU(tDQSCKmax/tCK) + WR_PREAMBLE + RD_POSTAMBLE - WL LPDDR4(DQ ODT is Enabled): RL +.." newline hexmask.long.byte 0x8 0.--5. 1. "WR2RD,DDR4: CWL + PL + BL/2 + tWTR_L LPDDR2/3/4: WL + BL/2 + tWTR + 1 Others: CWL + BL/2 + tWTR In DDR4 minimum time from write command to read command for same bank group. In others minimum time from write command to read command. Includes time for.." line.long 0xC "DRAMTMG3,[FREQ2] SDRAM Timing Register 3" hexmask.long.word 0xC 20.--29. 1. "T_MRW,Indicates the time to wait after a mode register write or read (MRW or MRR). Present only in designs configured to support LPDDR2 LPDDR3 or LPDDR4. LPDDR2 typically requires value of 5. LPDDR3 typically requires value of 10. LPDDR4: Set this to.." newline hexmask.long.byte 0xC 12.--17. 1. "T_MRD,tMRD- Indicates the number of cycles to wait after a mode register write or read. Depending on the connected SDRAM tMRD represents: - DDR2/mDDR: Time from MRS to any command - DDR3/4: Time from MRS to MRS command - LPDDR2: not used - LPDDR3/4:.." newline hexmask.long.word 0xC 0.--9. 1. "T_MOD,tMOD - Parameter used only in DDR3 and DDR4. Indicates the number of cycles between load mode command and following non-load mode command. If C/A parity for DDR4 is used set to tMOD_PAR(tMOD+PL) instead. If CAL mode is enabled.." line.long 0x10 "DRAMTMG4,[FREQ2] SDRAM Timing Register 4" hexmask.long.byte 0x10 24.--28. 1. "T_RCD,tRCD - tAL: Indicates the minimum time from activate to read or write command to same bank. When the controller is operating in 1:2 frequency ratio mode program this to ((tRCD - tAL)/2) and round it up to the next integer value. Minimum value.." newline hexmask.long.byte 0x10 16.--19. 1. "T_CCD,DDR4: tCCD_L: This is the minimum time between two reads or two writes for same bank group. Others: tCCD: This is the minimum time between two reads or two writes. When the controller is operating in 1:2 frequency ratio mode program this to.." newline hexmask.long.byte 0x10 8.--11. 1. "T_RRD,DDR4: tRRD_L: This is the minimum time between activates from bank 'a' to bank 'b' for same bank group. Others: tRRD: Minimum time between activates from bank 'a' to bank 'b' When the controller is operating in 1:2 frequency ratio mode program.." newline hexmask.long.byte 0x10 0.--4. 1. "T_RP,tRP: Indicates the minimum time from single-bank precharge to activate of same bank. When the controller is operating in 1:1 frequency ratio mode t_rp must be set to RoundUp(tRP/tCK). When the controller is operating in 1:2 frequency ratio mode.." line.long 0x14 "DRAMTMG5,[FREQ2] SDRAM Timing Register 5" hexmask.long.byte 0x14 24.--27. 1. "T_CKSRX,This is the time before self-refresh Exit that CK is maintained as a valid clock before issuing SRX. Specifies the clock stable time before SRX. Recommended settings: - mDDR - 1 - LPDDR2 - 2 - LPDDR3 - 2 - LPDDR4 - tCKCKEH - DDR2 - 1 - DDR3 -.." newline hexmask.long.byte 0x14 16.--19. 1. "T_CKSRE,This is the time after self-refresh Down Entry that CK is maintained as a valid clock. Specifies the clock disable delay after SRE. Recommended settings: - mDDR - 0 - LPDDR2 - 2 - LPDDR3 - 2 - LPDDR4 - tCKELCK - DDR2 - 1 - DDR3 - Max (10 ns 5.." newline hexmask.long.byte 0x14 8.--13. 1. "T_CKESR,Indicates the minimum CKE low width for self-refresh or self-refresh power down entry to exit timing in memory clock cycles. Recommended settings: - mDDR - tRFC - LPDDR2 - tCKESR - LPDDR3 - tCKESR - LPDDR4 - max(tCKE tSR) - DDR2 - tCKE - DDR3 -.." newline hexmask.long.byte 0x14 0.--4. 1. "T_CKE,Indicates the minimum number of cycles of CKE HIGH/LOW during power-down and self-refresh. - LPDDR2/LPDDR3 mode - Set this to the larger of tCKE or tCKESR - LPDDR4 mode - Set this to the larger of tCKE or tSR - Non-LPDDR2/non-LPDDR3/non-LPDDR4.." line.long 0x18 "DRAMTMG6,[FREQ2] SDRAM Timing Register 6" hexmask.long.byte 0x18 24.--27. 1. "T_CKDPDE,This is the time after Deep Power Down Entry that CK is maintained as a valid clock. Specifies the clock disable delay after DPDE. Recommended settings: - mDDR: 0 - LPDDR2: 2 - LPDDR3: 2 When the controller is operating in 1:2 frequency ratio.." newline hexmask.long.byte 0x18 16.--19. 1. "T_CKDPDX,This is the time before Deep Power Down Exit that CK is maintained as a valid clock before issuing DPDX. Specifies the clock stable time before DPDX. Recommended settings: - mDDR - 1 - LPDDR2 - 2 - LPDDR3 - 2 When the controller is operating in.." newline hexmask.long.byte 0x18 0.--3. 1. "T_CKCSX,This is the time before Clock Stop Exit that CK is maintained as a valid clock before issuing Clock Stop Exit. Specifies the clock stable time before next command after Clock Stop Exit. Recommended settings: - mDDR - 1 - LPDDR2 - tXP + 2 - LPDDR3.." line.long 0x1C "DRAMTMG7,[FREQ2] SDRAM Timing Register 7" hexmask.long.byte 0x1C 8.--11. 1. "T_CKPDE,This is the time after Power Down Entry that CK is maintained as a valid clock. Specifies the clock disable delay after PDE. Recommended settings: - mDDR - 0 - LPDDR2 - 2 - LPDDR3 - 2 - LPDDR4 - tCKELCK When using DDR2/3/4 SDRAM this register.." newline hexmask.long.byte 0x1C 0.--3. 1. "T_CKPDX,This is the time before Power Down Exit that CK is maintained as a valid clock before issuing PDX. Specifies the clock stable time before PDX. Recommended settings: - mDDR - 0 - LPDDR2 - 2 - LPDDR3 - 2 - LPDDR4 - tCKCKEH When using DDR2/3/4 SDRAM.." line.long 0x20 "DRAMTMG8,[FREQ2] SDRAM Timing Register 8" hexmask.long.byte 0x20 24.--30. 1. "T_XS_FAST_X32,tXS_FAST: Exit self-refresh to ZQCL ZQCS and MRS (only CL WR RTP and Geardown mode). When the controller is operating in 1:2 frequency ratio mode program this to the previous value divided by 2 and round up to next integer value. Note:.." newline hexmask.long.byte 0x20 16.--22. 1. "T_XS_ABORT_X32,tXS_ABORT: Exit self-refresh to commands not requiring a locked DLL in self-refresh Abort. When the controller is operating in 1:2 frequency ratio mode program this to the previous value divided by 2 and round up to next integer value." newline hexmask.long.byte 0x20 8.--14. 1. "T_XS_DLL_X32,tXSDLL: Exit self-refresh to commands requiring a locked DLL. When the controller is operating in 1:2 frequency ratio mode program this to the previous value divided by 2 and round up to next integer value. Note: Used only for DDR2 DDR3.." newline hexmask.long.byte 0x20 0.--6. 1. "T_XS_X32,tXS: Exit self-refresh to commands not requiring a locked DLL. When the controller is operating in 1:2 frequency ratio mode program this to the previous value divided by 2 and round up to next integer value. Note: Used only for DDR2 DDR3 and.." line.long 0x24 "DRAMTMG9,[FREQ2] SDRAM Timing Register 9" bitfld.long 0x24 30. "DDR4_WR_PREAMBLE,DDR4 Write preamble mode. - 0 - 1tCK preamble - 1 - 2tCK preamble Present only with MEMC_FREQ_RATIO=2. Programming Mode: Quasi-dynamic Group 2 Group 4" "0,1" newline bitfld.long 0x24 16.--18. "T_CCD_S,tCCD_S: This is the minimum time between two reads or two writes for different bank group. For bank switching (from bank 'a' to bank 'b') the minimum time is this value + 1. When the controller is operating in 1:2 frequency ratio mode program.." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x24 8.--11. 1. "T_RRD_S,tRRD_S: This is the minimum time between activates from bank 'a' to bank 'b' for different bank group. When the controller is operating in 1:2 frequency ratio mode program this to (tRRD_S/2) and round it up to the next integer value. Present.." newline hexmask.long.byte 0x24 0.--5. 1. "WR2RD_S,CWL + PL + BL/2 + tWTR_S Minimum time from write command to read command for different bank group. Includes time for bus turnaround recovery times and all per-bank per-rank and global constraints. Present only in designs configured to support.." line.long 0x28 "DRAMTMG10,[FREQ2] SDRAM Timing Register 10" hexmask.long.byte 0x28 16.--20. 1. "T_SYNC_GEAR,Indicates the time between MRS command and the sync pulse time. This must be even number of clocks. For DDR4-2666 and DDR4-3200 this parameter is defined as tMOD(min)+4nCK tMOD(min) is greater of 24nCK or 15ns 15ns / .625ns = 24 Max value.." newline hexmask.long.byte 0x28 8.--12. 1. "T_CMD_GEAR,Indicates a sync pulse to first valid command. For DDR4-2666 and DDR4-3200 this parameter is defined as tMOD(min) tMOD(min) is greater of 24nCK or 15ns 15ns / .625ns = 24 Max value for this register is 24 When the controller is operating in.." newline bitfld.long 0x28 2.--3. "T_GEAR_SETUP,Indicates the geardown setup time. Minimum value of this register is 1. Zero is invalid. For DDR4-2666 and DDR4-3200 this parameter is defined as 2 clks When the controller is operating in 1:2 frequency ratio mode program this to.." "0,1,2,3" newline bitfld.long 0x28 0.--1. "T_GEAR_HOLD,Indicates the geardown hold time. Minimum value of this register is 1. Zero is invalid. For DDR4-2666 and DDR4-3200 this parameter is defined as 2 clks When the controller is operating in 1:2 frequency ratio mode program this to.." "0,1,2,3" line.long 0x2C "DRAMTMG11,[FREQ2] SDRAM Timing Register 11" hexmask.long.byte 0x2C 24.--30. 1. "POST_MPSM_GAP_X32,tXMPDLL: This is the minimum Exit MPSM to commands requiring a locked DLL. When the controller is operating in 1:2 frequency ratio mode program this to (tXMPDLL/2) and round it up to the next integer value. Present only in designs.." newline hexmask.long.byte 0x2C 16.--20. 1. "T_MPX_LH,tMPX_LH: This is the minimum CS_n Low hold time to CKE rising edge. When the controller is operating in 1:2 frequency ratio mode program this to RoundUp(tMPX_LH/2)+1. Present only in designs configured to support DDR4. Unit: DFI clock cycles." newline bitfld.long 0x2C 8.--9. "T_MPX_S,tMPX_S: This is the minimum time CS setup time to CKE. When the controller is operating in 1:2 frequency ratio mode program this to (tMPX_S/2) and round it up to the next integer value. Present only in designs configured to support DDR4. Unit:.." "0,1,2,3" newline hexmask.long.byte 0x2C 0.--4. 1. "T_CKMPE,tCKMPE: This is the minimum valid clock requirement after MPSM entry. Present only in designs configured to support DDR4. When the controller is operating in 1:2 frequency ratio mode divide the value calculated using the previous equation by 2.." line.long 0x30 "DRAMTMG12,[FREQ2] SDRAM Timing Register 12" hexmask.long.byte 0x30 24.--29. 1. "T_WR_MPR,This bit is used only in DDR4. Cycles between MPR Write and other command. Set this to tMOD + AL (or tMOD + PL + AL if C/A parity is also used). When the controller is operating in 1:2 frequency ratio mode program this to (tWR_MPR/2) and round.." newline bitfld.long 0x30 16.--17. "T_CMDCKE,tCMDCKE: Indicates the delay from valid command to CKE input LOW. Set this to the larger of tESCKE or tCMDCKE When the controller is operating in 1:2 frequency ratio mode program this to (max(tESCKE tCMDCKE)/2) and round it up to the next.." "0,1,2,3" newline hexmask.long.byte 0x30 0.--4. 1. "T_MRD_PDA,tMRD_PDA: This is the Mode Register Set command cycle time in PDA mode. When the controller is operating in 1:2 frequency ratio mode program this to (tMRD_PDA/2) and round it up to the next integer value. Unit: DFI clock cycles. Programming.." line.long 0x34 "DRAMTMG13,[FREQ2] SDRAM Timing Register 13" hexmask.long.byte 0x34 24.--30. 1. "ODTLOFF,LPDDR4: ODTLoff: This is the latency from CAS-2 command to ODToff reference. When the controller is operating in 1:2 frequency ratio mode program this to (ODTLoff/2) and round it up to the next integer value. Unit: DFI clock cycles. Programming.." newline hexmask.long.byte 0x34 16.--21. 1. "T_CCD_MW,LPDDR4: tCCDMW: This is the minimum time from write or masked write to masked write command for same bank. When the controller is operating in 1:2 frequency ratio mode program this to (tCCDMW/2) and round it up to the next integer value. Unit:.." newline bitfld.long 0x34 0.--2. "T_PPD,LPDDR4: tPPD: This is the minimum time from precharge to precharge command. When the controller is operating in 1:2 frequency ratio mode program this to (tPPD/2) and round it up to the next integer value. Unit: DFI clock cycles. Programming Mode:.." "?,?,?,?,tPPD: This is the minimum time from precharge to..,?,?,?" line.long 0x38 "DRAMTMG14,[FREQ2] SDRAM Timing Register 14" hexmask.long.word 0x38 0.--11. 1. "T_XSR,tXSR: This is the exit self-refresh to any command. When the controller is operating in 1:2 frequency ratio mode program this to the previous value divided by 2 and round up to next integer value. The value 0xfff is illegal for this register.." line.long 0x3C "DRAMTMG15,[FREQ2] SDRAM Timing Register 15" bitfld.long 0x3C 31. "EN_DFI_LP_T_STAB,- 1 - Enable using tSTAB when exiting DFI LP. This must be set when the PHY is stopping the clock during DFI LP to save maximum power. - 0 - Disable using tSTAB when exiting DFI LP. Programming Mode: Quasi-dynamic Group 2 Group 4" "Disable using tSTAB when exiting DFI LP,Enable using tSTAB when exiting DFI LP" newline hexmask.long.byte 0x3C 0.--7. 1. "T_STAB_X32,tSTAB: Stabilization time. It is required in the following two cases for DDR3/DDR4 RDIMM: - When exiting power saving mode if the clock is stopped after re-enabling it the clock must be stable for a time specified by tSTAB - In the case of.." group.long 0x180++0x3 line.long 0x0 "ZQCTL0,[FREQ2] ZQ Control Register 0" bitfld.long 0x0 31. "DIS_AUTO_ZQ,- 1 - Disable uMCTL2 generation of ZQCS/MPC(ZQ calibration) command. Register DBGCMD.zq_calib_short can be used instead to issue ZQ calibration request from APB module - 0 - Internally generate ZQCS/MPC(ZQ calibration) commands based on.." "Internally generate ZQCS/MPC,Disable uMCTL2 generation of ZQCS/MPC" newline bitfld.long 0x0 30. "DIS_SRX_ZQCL,- 1 - Disable issuing of ZQCL/MPC(ZQ calibration) command at self-refresh/SR-Powerdown exit. Only applicable when run in DDR3 or DDR4 or LPDDR2 or LPDDR3 or LPDDR4 mode - 0 - Enable issuing of ZQCL/MPC(ZQ calibration) command at.." "Enable issuing of ZQCL/MPC,Disable issuing of ZQCL/MPC" newline bitfld.long 0x0 29. "ZQ_RESISTOR_SHARED,- 1 - Denotes that ZQ resistor is shared between ranks. Means ZQinit/ZQCL/ZQCS/MPC(ZQ calibration) commands are sent to one rank at a time with tZQinit/tZQCL/tZQCS/tZQCAL/tZQLAT timing met between commands so that commands to different.." "ZQ resistor is not shared,Denotes that ZQ resistor is shared between ranks" newline bitfld.long 0x0 28. "DIS_MPSMX_ZQCL,- 1 - Disable issuing of ZQCL command at Maximum Power Saving Mode exit. Only applicable when run in DDR4 mode - 0 - Enable issuing of ZQCL command at Maximum Power Saving Mode exit. Only applicable when run in DDR4 mode This is only.." "Enable issuing of ZQCL command at Maximum Power..,Disable issuing of ZQCL command at Maximum Power.." newline hexmask.long.word 0x0 16.--26. 1. "T_ZQ_LONG_NOP,tZQoper for DDR3/DDR4 tZQCL for LPDDR2/LPDDR3 tZQCAL for LPDDR4: Number of DFI clock cycles of NOP required after a ZQCL (ZQ calibration long)/MPC(ZQ Start) command is issued to SDRAM. When the controller is operating in 1:2 frequency.." newline hexmask.long.word 0x0 0.--9. 1. "T_ZQ_SHORT_NOP,tZQCS for DDR3/DD4/LPDDR2/LPDDR3 tZQLAT for LPDDR4: Number of DFI clock cycles of NOP required after a ZQCS (ZQ calibration short)/MPC(ZQ Latch) command is issued to SDRAM. When the controller is operating in 1:2 frequency ratio mode.." group.long 0x190++0x7 line.long 0x0 "DFITMG0,[FREQ2] DFI Timing Register 0" hexmask.long.byte 0x0 24.--28. 1. "DFI_T_CTRL_DELAY,Specifies the number of DFI clock cycles after an assertion or de-assertion of the DFI control signals that the control signals at the PHY-DRAM interface reflect the assertion or de-assertion. If the DFI clock and the memory clock are.." newline bitfld.long 0x0 23. "DFI_RDDATA_USE_DFI_PHY_CLK,Defines whether dfi_rddata_en/dfi_rddata/dfi_rddata_valid is generated using HDR (DFI clock) or SDR (DFI PHY clock) values. Selects whether value in DFITMG0.dfi_t_rddata_en is in terms of HDR (DFI clock) or SDR (DFI PHY clock).." "Else,?" newline hexmask.long.byte 0x0 16.--22. 1. "DFI_T_RDDATA_EN,Time from the assertion of a read command on the DFI interface to the assertion of the dfi_rddata_en signal. Refer to PHY specification for correct value. This corresponds to the DFI parameter trddata_en. Note that depending on the PHY.." newline bitfld.long 0x0 15. "DFI_WRDATA_USE_DFI_PHY_CLK,Defines whether dfi_wrdata_en/dfi_wrdata/dfi_wrdata_mask is generated using HDR (DFI clock) or SDR (DFI PHY clock) values. Selects whether value in DFITMG0.dfi_tphy_wrlat is in terms of HDR (DFI clock) or SDR (DFI PHY clock).." "Else,?" newline hexmask.long.byte 0x0 8.--13. 1. "DFI_TPHY_WRDATA,Specifies the number of clock cycles between when dfi_wrdata_en is asserted to when the associated write data is driven on the dfi_wrdata signal. This corresponds to the DFI timing parameter tphy_wrdata. For more information on correct.." newline hexmask.long.byte 0x0 0.--5. 1. "DFI_TPHY_WRLAT,Write latency. Number of clocks from the write command to write data enable (dfi_wrdata_en). This corresponds to the DFI timing parameter tphy_wrlat. Refer to PHY specification for correct value.Note that depending on the PHY if using.." line.long 0x4 "DFITMG1,[FREQ2] DFI Timing Register 1" hexmask.long.byte 0x4 28.--31. 1. "DFI_T_CMD_LAT,Specifies the number of DFI PHY clock cycles between when the dfi_cs signal is asserted and when the associated command is driven. This field is used for CAL mode must be set to '0' or tCAL which matches the CAL mode register setting in.." newline bitfld.long 0x4 24.--25. "DFI_T_PARIN_LAT,Specifies the number of DFI PHY clock cycles between when the dfi_cs signal is asserted and when the associated dfi_parity_in signal is driven. Unit: DFI PHY clock cycles. Programming Mode: Quasi-dynamic Group 4" "0,1,2,3" newline hexmask.long.byte 0x4 16.--20. 1. "DFI_T_WRDATA_DELAY,Specifies the number of DFI clock cycles between when the dfi_wrdata_en signal is asserted and when the corresponding write data transfer is completed on the DRAM bus. This corresponds to the DFI timing parameter twrdata_delay. For.." newline hexmask.long.byte 0x4 8.--12. 1. "DFI_T_DRAM_CLK_DISABLE,Specifies the number of DFI clock cycles from the assertion of the dfi_dram_clk_disable signal on the DFI until the clock to the DRAM memory devices at the PHY-DRAM boundary maintains a low value. If the DFI clock and the memory.." newline hexmask.long.byte 0x4 0.--4. 1. "DFI_T_DRAM_CLK_ENABLE,Specifies the number of DFI clock cycles from the de-assertion of the dfi_dram_clk_disable signal on the DFI until the first valid rising edge of the clock to the DRAM memory devices at the PHY-DRAM boundary. If the DFI clock and.." group.long 0x1B4++0x7 line.long 0x0 "DFITMG2,[FREQ2] DFI Timing Register 2" hexmask.long.byte 0x0 8.--14. 1. "DFI_TPHY_RDCSLAT,specifies the number of DFI PHY clock cycles between when a read command is sent on the DFI control interface and when the associated dfi_rddata_cs signal is asserted. This corresponds to the DFI timing parameter tphy_rdcslat. Refer to.." newline hexmask.long.byte 0x0 0.--5. 1. "DFI_TPHY_WRCSLAT,Specifies the number of DFI PHY clock cycles between when a write command is sent on the DFI control interface and when the associated dfi_wrdata_cs signal is asserted. This corresponds to the DFI timing parameter tphy_wrcslat. For more.." line.long 0x4 "DFITMG3,[FREQ2] DFI Timing Register 3" hexmask.long.byte 0x4 0.--4. 1. "DFI_T_GEARDOWN_DELAY,The delay from dfi_geardown_en assertion to the time of the PHY being ready to receive commands. Refer to PHY specification for correct value. When the controller is operating in 1:2 frequency ratio mode program this to.." group.long 0x240++0x3 line.long 0x0 "ODTCFG,[FREQ2] ODT Configuration Register" hexmask.long.byte 0x0 24.--27. 1. "WR_ODT_HOLD,DFI PHY clock cycles to hold ODT for a write command. The minimum supported value is 2. Recommended values: DDR2: - BL8 - 0x5 (DDR2-400/533/667) 0x6 (DDR2-800) 0x7 (DDR2-1066) - BL4 - 0x3 (DDR2-400/533/667) 0x4 (DDR2-800) 0x5 (DDR2-1066).." newline hexmask.long.byte 0x0 16.--20. 1. "WR_ODT_DELAY,Indicates the delay in DFI PHY clock cycles from issuing a write command to setting ODT values associated with that command. ODT setting must remain constant for the entire time that DQS is driven by the uMCTL2. Recommended values: DDR2: -.." newline hexmask.long.byte 0x0 8.--11. 1. "RD_ODT_HOLD,DFI PHY clock cycles to hold ODT for a read command. The minimum supported value is 2. Recommended values: DDR2: - BL8 - 0x6 (not DDR2-1066) 0x7 (DDR2-1066) - BL4 - 0x4 (not DDR2-1066) 0x5 (DDR2-1066) DDR3: - BL8 - 0x6 DDR4: - BL8 - 5 +.." newline hexmask.long.byte 0x0 2.--6. 1. "RD_ODT_DELAY,Indicates the delay in DFI PHY clock cycles from issuing a read command to setting ODT values associated with that command. ODT setting must remain constant for the entire time that DQS is driven by the uMCTL2. Recommended values: DDR2: -.." tree.end tree "UMCTL2_REGS_FREQ3 (uMCTL2 DDRC FREQ3 Registers)" base ad:0x16384 group.long 0x20++0x7 line.long 0x0 "DERATEEN,[FREQ3] Temperature Derate Enable Register" bitfld.long 0x0 12. "DERATE_MR4_TUF_DIS,Disables use of MR4 TUF flag (MR4[7]) bit. - 0 - Use MR4 TUF flag (MR4[7]) - 1 - Do not use MR4 TUF Flag (MR4[7]) For LPDDR4 it is recommended to set this register to 1. For LPDDR2 and LPDDR3 contact your memory vendor for.." "Use MR4 TUF flag,Do not use MR4 TUF Flag" newline bitfld.long 0x0 8.--10. "RC_DERATE_VALUE,Derate value of tRC for LPDDR4. - 0 - Derating uses +1 - 1 - Derating uses +2 - 2 - Derating uses +3 - 3 - Derating uses +4 Present only in designs configured to support LPDDR4. The required cycles for derating can be determined by.." "Derating uses +1,Derating uses +2,Derating uses +3,Derating uses +4,?,?,?,?" newline hexmask.long.byte 0x0 4.--7. 1. "DERATE_BYTE,This bit indicates which byte of the MRR data is used for derating. The maximum valid value depends on MEMC_DRAM_TOTAL_DATA_WIDTH. Present only in designs configured to support LPDDR2/LPDDR3/LPDDR4. Programming Mode: Static" newline bitfld.long 0x0 1.--2. "DERATE_VALUE,Derate value. - 0 - Derating uses +1 - 1 - Derating uses +2 Present only in designs configured to support LPDDR2/LPDDR3/LPDDR4. Set to 0 for all LPDDR2 speed grades as derating value of +1.875 ns is less than a core_ddrc_core_clk period. For.." "Derating uses +1,Derating uses +2,?,?" newline bitfld.long 0x0 0. "DERATE_ENABLE,Enables derating. - 0 - Timing parameter derating is disabled - 1 - Timing parameter derating is enabled using MR4 read value Present only in designs configured to support LPDDR2/LPDDR3/LPDDR4. This field must be set to '0' for.." "Timing parameter derating is disabled,Timing parameter derating is enabled using MR4.." line.long 0x4 "DERATEINT,[FREQ3] Temperature Derate Interval Register" hexmask.long 0x4 0.--31. 1. "MR4_READ_INTERVAL,Interval between two MR4 reads used to derate the timing parameters. Present only in designs configured to support LPDDR2/LPDDR3/LPDDR4. This register must not be set to zero. Unit: DFI clock cycles. Programming Mode: Static" group.long 0x34++0x3 line.long 0x0 "PWRTMG,[FREQ3] Low Power Timing Register" hexmask.long.byte 0x0 16.--23. 1. "SELFREF_TO_X32,After this many clocks of the DDRC command channel being idle the uMCTL2 automatically puts the SDRAM into self-refresh. The DDRC command channel is considered idle when there are no HIF commands outstanding. This must be enabled in the.." newline hexmask.long.byte 0x0 8.--15. 1. "T_DPD_X4096,Minimum deep power-down time. For mDDR value from the JEDEC specification is 0 as mDDR exits from deep power-down mode immediately after PWRCTL.deeppowerdown_en is de-asserted. For LPDDR2/LPDDR3 value from the JEDEC specification is 500us." newline hexmask.long.byte 0x0 0.--4. 1. "POWERDOWN_TO_X32,After this many clocks of the DDRC command channel being idle the uMCTL2 automatically puts the SDRAM into power-down. The DDRC command channel is considered idle when there are no HIF commands outstanding. This must be enabled in the.." group.long 0x50++0x3 line.long 0x0 "RFSHCTL0,[FREQ3] Refresh Control Register 0" hexmask.long.byte 0x0 20.--23. 1. "REFRESH_MARGIN,Threshold value in number of DFI clock cycles before the critical refresh or page timer expires. A critical refresh is to be issued before this threshold is reached. It is recommended that this not be changed from the default value.." newline hexmask.long.byte 0x0 12.--16. 1. "REFRESH_TO_X1_X32,If the refresh timer (tRFCnom also known as tREFI) has expired at least once then a speculative refresh may be performed. A speculative refresh is a refresh performed at a time when refresh would be useful. When the SDRAM bus is idle.." newline hexmask.long.byte 0x0 4.--9. 1. "REFRESH_BURST,The programmed value + 1 is the number of refresh timeouts that is allowed to accumulate before traffic is blocked and the refreshes are forced to execute. Closing pages to perform a refresh is a one-time penalty that must be paid for each.." newline bitfld.long 0x0 2. "PER_BANK_REFRESH,- 1 - Per bank refresh - 0 - All bank refresh Per bank refresh allows traffic to flow to other banks. Per bank refresh is not supported by all LPDDR2 devices but must be supported by all LPDDR3/LPDDR4 devices. Present only in designs.." "All bank refresh,Per bank refresh" group.long 0x64++0x7 line.long 0x0 "RFSHTMG,[FREQ3] Refresh Timing Register" bitfld.long 0x0 31. "T_RFC_NOM_X1_SEL,Specifies whether the RFSHTMG.t_rfc_nom_x1_x32 and RFSHCTL0.refresh_to_x1_x32 register values are x1 or x32. - 0 - x32 register values are used - 1 - x1 register values are used This applies only when per-bank refresh is enabled.." "x32 register values are used,x1 register values are used" newline hexmask.long.word 0x0 16.--27. 1. "T_RFC_NOM_X1_X32,Average time interval between refreshes per rank (Specification: 7.8us for DDR2 DDR3 and DDR4. See JEDEC specification for mDDR LPDDR2 LPDDR3 and LPDDR4). When the controller is operating in 1:1 mode set this register to.." newline bitfld.long 0x0 15. "LPDDR3_TREFBW_EN,Used only when LPDDR3 memory type is connected. Should only be changed when uMCTL2 is in reset. Specifies whether to use the tREFBW parameter (required by some LPDDR3 devices which comply with earlier versions of the LPDDR3 JEDEC.." "tREFBW parameter not used,tREFBW parameter used" newline hexmask.long.word 0x0 0.--9. 1. "T_RFC_MIN,tRFC (min): Minimum time from refresh to refresh or activate. When the controller is operating in 1:1 mode t_rfc_min must be set to RoundUp(tRFCmin/tCK). When the controller is operating in 1:2 mode t_rfc_min must be set to.." line.long 0x4 "RFSHTMG1,[FREQ3] Refresh Timing Register1" hexmask.long.byte 0x4 16.--23. 1. "T_PBR2PBR,LPDDR4:tpbR2pbR. Per-bank refresh to Per-bank refresh different bank Time. When the controller is operating in 1:1 frequency ratio mode program this to RoundUp(tpbR2pbR/tCK). When the controller is operating in 1:2 frequency ratio mode.." repeat 4. (list 0x3 0x4 0x6 0x7 )(list 0x0 0x4 0xC 0x10 ) group.long ($2+0xDC)++0x3 line.long 0x0 "INIT$1,[FREQ3] SDRAM Initialization Register 3" hexmask.long.word 0x0 16.--31. 1. "MR,DDR2:Indicates the value to write to MR register. Bit 8 is for DLL and the setting here is ignored. The uMCTL2 sets this bit appropriately. DDR3/DDR4: Value loaded into MR0 register. mDDR: Value to write to MR register. LPDDR2/LPDDR3/LPDDR4 - Value to.." newline hexmask.long.word 0x0 0.--15. 1. "EMR,DDR2: Indicates the value to write to EMR register. Bits 9:7 are for OCD and the setting in this register is ignored. The uMCTL2 sets those bits appropriately. DDR3/DDR4: Value to write to MR1 register Set bit 7 to 0. mDDR: Value to write to EMR.." repeat.end group.long 0xF4++0x3 line.long 0x0 "RANKCTL,[FREQ3] Rank Control Register" bitfld.long 0x0 26. "DIFF_RANK_WR_GAP_MSB,Only present for multi-rank configurations. 1-bit extension to be used when RANKCTL.diff_rank_wr_gap field needs to be set to a value greater than 0xF. Programming Mode: Quasi-dynamic Group 2" "?,bit extension to be used when RANKCTL" newline bitfld.long 0x0 24. "DIFF_RANK_RD_GAP_MSB,Only present for multi-rank configurations. 1-bit extension to be used when RANKCTL.diff_rank_rd_gap field needs to be set to a value greater than 0xF. Programming Mode: Quasi-dynamic Group 2" "?,bit extension to be used when RANKCTL" newline hexmask.long.byte 0x0 12.--15. 1. "MAX_RANK_WR,Only present for multi-rank configurations. Background: Writes to the same rank can be performed back-to-back. Writes to different ranks require additional gap dictated by the register RANKCTL.diff_rank_wr_gap. This is to avoid possible data.." newline hexmask.long.byte 0x0 8.--11. 1. "DIFF_RANK_WR_GAP,Only present for multi-rank configurations. Indicates the number of clocks of gap in data responses when performing consecutive writes to different ranks. This is used to switch the delays in the PHY to match the rank requirements. This.." newline hexmask.long.byte 0x0 4.--7. 1. "DIFF_RANK_RD_GAP,Only present for multi-rank configurations. Indicates the number of clocks of gap in data responses when performing consecutive reads to different ranks. This is used to switch the delays in the PHY to match the rank requirements. This.." newline hexmask.long.byte 0x0 0.--3. 1. "MAX_RANK_RD,Only present for multi-rank configurations. Background: Reads to the same rank can be performed back-to-back. Reads to different ranks require additional gap dictated by the register RANKCTL.diff_rank_rd_gap. This is to avoid possible data.." group.long 0x100++0x3F line.long 0x0 "DRAMTMG0,[FREQ3] SDRAM Timing Register 0" hexmask.long.byte 0x0 24.--30. 1. "WR2PRE,Specifies the minimum time between write and precharge to same bank. Specifications: WL + BL/2 + tWR = approximately 8 cycles + 15 ns = 14 clocks @400MHz and less for lower frequencies. where: - WL - Write latency - BL - Burst length. This must.." newline hexmask.long.byte 0x0 16.--21. 1. "T_FAW,tFAW - valid only when 8 or more banks(or banks x bank groups) are present. In 8-bank design at most 4 banks must be activated in a rolling window of tFAW cycles. When the controller is operating in 1:2 frequency ratio mode program this to.." newline hexmask.long.byte 0x0 8.--14. 1. "T_RAS_MAX,tRAS(max) - Specifies the maximum time between activate and precharge to same bank. This is the maximum time that a page can be kept open Minimum value of this register is 1. Zero is invalid. When the controller is operating in 1:1 frequency.." newline hexmask.long.byte 0x0 0.--5. 1. "T_RAS_MIN,tRAS(min) - Specifies the minimum time between activate and precharge to the same bank. When the controller is operating in 1:2 frequency mode 1T mode program this to tRAS(min)/2. No rounding up. When the controller is operating in 1:2.." line.long 0x4 "DRAMTMG1,[FREQ3] SDRAM Timing Register 1" hexmask.long.byte 0x4 16.--20. 1. "T_XP,tXP - Specifies the minimum time after power-down exit to any operation. For DDR3 this must be programmed to tXPDLL if slow powerdown exit is selected in MR0[12]. If C/A parity for DDR4 is used set to (tXP+PL) instead. If LPDDR4 is selected and.." newline hexmask.long.byte 0x4 8.--13. 1. "RD2PRE,tRTP - Specifies the minimum time from read to precharge of same bank. - DDR2 - tAL + BL/2 + max(tRTP 2) - 2 - DDR3 - tAL + max (tRTP 4) - DDR4 - Max of following two equations: tAL + max (tRTP 4) or RL + BL/2 - tRP (*). - mDDR - BL/2 - LPDDR2.." newline hexmask.long.byte 0x4 0.--6. 1. "T_RC,tRC - Specifies the minimum time between activates to same bank. When the controller is operating in 1:2 frequency ratio mode program this to (tRC/2) and round up to next integer value. Unit: DFI clock cycles. Programming Mode: Quasi-dynamic Group.." line.long 0x8 "DRAMTMG2,[FREQ3] SDRAM Timing Register 2" hexmask.long.byte 0x8 24.--29. 1. "WRITE_LATENCY,Set this field to WL. Indicates the Time from write command to write data on SDRAM interface. This must be set to WL. For mDDR it must be set to 1. Note that depending on the PHY if using RDIMM/LRDIMM it might be necessary to adjust the.." newline hexmask.long.byte 0x8 16.--21. 1. "READ_LATENCY,Set this field to RL. Indicates the time from read command to read data on SDRAM interface. This must be set to RL. Note that depending on the PHY if using RDIMM/LRDIMM it might be necessary to adjust the value of RL to compensate for the.." newline hexmask.long.byte 0x8 8.--13. 1. "RD2WR,DDR2/3/mDDR: RL + BL/2 + 2 - WL DDR4: RL + BL/2 + 1 + WR_PREAMBLE - WL LPDDR2/LPDDR3: RL + BL/2 + RU(tDQSCKmax/tCK) + 1 - WL LPDDR4(DQ ODT is Disabled): RL + BL/2 + RU(tDQSCKmax/tCK) + WR_PREAMBLE + RD_POSTAMBLE - WL LPDDR4(DQ ODT is Enabled): RL +.." newline hexmask.long.byte 0x8 0.--5. 1. "WR2RD,DDR4: CWL + PL + BL/2 + tWTR_L LPDDR2/3/4: WL + BL/2 + tWTR + 1 Others: CWL + BL/2 + tWTR In DDR4 minimum time from write command to read command for same bank group. In others minimum time from write command to read command. Includes time for.." line.long 0xC "DRAMTMG3,[FREQ3] SDRAM Timing Register 3" hexmask.long.word 0xC 20.--29. 1. "T_MRW,Indicates the time to wait after a mode register write or read (MRW or MRR). Present only in designs configured to support LPDDR2 LPDDR3 or LPDDR4. LPDDR2 typically requires value of 5. LPDDR3 typically requires value of 10. LPDDR4: Set this to.." newline hexmask.long.byte 0xC 12.--17. 1. "T_MRD,tMRD- Indicates the number of cycles to wait after a mode register write or read. Depending on the connected SDRAM tMRD represents: - DDR2/mDDR: Time from MRS to any command - DDR3/4: Time from MRS to MRS command - LPDDR2: not used - LPDDR3/4:.." newline hexmask.long.word 0xC 0.--9. 1. "T_MOD,tMOD - Parameter used only in DDR3 and DDR4. Indicates the number of cycles between load mode command and following non-load mode command. If C/A parity for DDR4 is used set to tMOD_PAR(tMOD+PL) instead. If CAL mode is enabled.." line.long 0x10 "DRAMTMG4,[FREQ3] SDRAM Timing Register 4" hexmask.long.byte 0x10 24.--28. 1. "T_RCD,tRCD - tAL: Indicates the minimum time from activate to read or write command to same bank. When the controller is operating in 1:2 frequency ratio mode program this to ((tRCD - tAL)/2) and round it up to the next integer value. Minimum value.." newline hexmask.long.byte 0x10 16.--19. 1. "T_CCD,DDR4: tCCD_L: This is the minimum time between two reads or two writes for same bank group. Others: tCCD: This is the minimum time between two reads or two writes. When the controller is operating in 1:2 frequency ratio mode program this to.." newline hexmask.long.byte 0x10 8.--11. 1. "T_RRD,DDR4: tRRD_L: This is the minimum time between activates from bank 'a' to bank 'b' for same bank group. Others: tRRD: Minimum time between activates from bank 'a' to bank 'b' When the controller is operating in 1:2 frequency ratio mode program.." newline hexmask.long.byte 0x10 0.--4. 1. "T_RP,tRP: Indicates the minimum time from single-bank precharge to activate of same bank. When the controller is operating in 1:1 frequency ratio mode t_rp must be set to RoundUp(tRP/tCK). When the controller is operating in 1:2 frequency ratio mode.." line.long 0x14 "DRAMTMG5,[FREQ3] SDRAM Timing Register 5" hexmask.long.byte 0x14 24.--27. 1. "T_CKSRX,This is the time before self-refresh Exit that CK is maintained as a valid clock before issuing SRX. Specifies the clock stable time before SRX. Recommended settings: - mDDR - 1 - LPDDR2 - 2 - LPDDR3 - 2 - LPDDR4 - tCKCKEH - DDR2 - 1 - DDR3 -.." newline hexmask.long.byte 0x14 16.--19. 1. "T_CKSRE,This is the time after self-refresh Down Entry that CK is maintained as a valid clock. Specifies the clock disable delay after SRE. Recommended settings: - mDDR - 0 - LPDDR2 - 2 - LPDDR3 - 2 - LPDDR4 - tCKELCK - DDR2 - 1 - DDR3 - Max (10 ns 5.." newline hexmask.long.byte 0x14 8.--13. 1. "T_CKESR,Indicates the minimum CKE low width for self-refresh or self-refresh power down entry to exit timing in memory clock cycles. Recommended settings: - mDDR - tRFC - LPDDR2 - tCKESR - LPDDR3 - tCKESR - LPDDR4 - max(tCKE tSR) - DDR2 - tCKE - DDR3 -.." newline hexmask.long.byte 0x14 0.--4. 1. "T_CKE,Indicates the minimum number of cycles of CKE HIGH/LOW during power-down and self-refresh. - LPDDR2/LPDDR3 mode - Set this to the larger of tCKE or tCKESR - LPDDR4 mode - Set this to the larger of tCKE or tSR - Non-LPDDR2/non-LPDDR3/non-LPDDR4.." line.long 0x18 "DRAMTMG6,[FREQ3] SDRAM Timing Register 6" hexmask.long.byte 0x18 24.--27. 1. "T_CKDPDE,This is the time after Deep Power Down Entry that CK is maintained as a valid clock. Specifies the clock disable delay after DPDE. Recommended settings: - mDDR: 0 - LPDDR2: 2 - LPDDR3: 2 When the controller is operating in 1:2 frequency ratio.." newline hexmask.long.byte 0x18 16.--19. 1. "T_CKDPDX,This is the time before Deep Power Down Exit that CK is maintained as a valid clock before issuing DPDX. Specifies the clock stable time before DPDX. Recommended settings: - mDDR - 1 - LPDDR2 - 2 - LPDDR3 - 2 When the controller is operating in.." newline hexmask.long.byte 0x18 0.--3. 1. "T_CKCSX,This is the time before Clock Stop Exit that CK is maintained as a valid clock before issuing Clock Stop Exit. Specifies the clock stable time before next command after Clock Stop Exit. Recommended settings: - mDDR - 1 - LPDDR2 - tXP + 2 - LPDDR3.." line.long 0x1C "DRAMTMG7,[FREQ3] SDRAM Timing Register 7" hexmask.long.byte 0x1C 8.--11. 1. "T_CKPDE,This is the time after Power Down Entry that CK is maintained as a valid clock. Specifies the clock disable delay after PDE. Recommended settings: - mDDR - 0 - LPDDR2 - 2 - LPDDR3 - 2 - LPDDR4 - tCKELCK When using DDR2/3/4 SDRAM this register.." newline hexmask.long.byte 0x1C 0.--3. 1. "T_CKPDX,This is the time before Power Down Exit that CK is maintained as a valid clock before issuing PDX. Specifies the clock stable time before PDX. Recommended settings: - mDDR - 0 - LPDDR2 - 2 - LPDDR3 - 2 - LPDDR4 - tCKCKEH When using DDR2/3/4 SDRAM.." line.long 0x20 "DRAMTMG8,[FREQ3] SDRAM Timing Register 8" hexmask.long.byte 0x20 24.--30. 1. "T_XS_FAST_X32,tXS_FAST: Exit self-refresh to ZQCL ZQCS and MRS (only CL WR RTP and Geardown mode). When the controller is operating in 1:2 frequency ratio mode program this to the previous value divided by 2 and round up to next integer value. Note:.." newline hexmask.long.byte 0x20 16.--22. 1. "T_XS_ABORT_X32,tXS_ABORT: Exit self-refresh to commands not requiring a locked DLL in self-refresh Abort. When the controller is operating in 1:2 frequency ratio mode program this to the previous value divided by 2 and round up to next integer value." newline hexmask.long.byte 0x20 8.--14. 1. "T_XS_DLL_X32,tXSDLL: Exit self-refresh to commands requiring a locked DLL. When the controller is operating in 1:2 frequency ratio mode program this to the previous value divided by 2 and round up to next integer value. Note: Used only for DDR2 DDR3.." newline hexmask.long.byte 0x20 0.--6. 1. "T_XS_X32,tXS: Exit self-refresh to commands not requiring a locked DLL. When the controller is operating in 1:2 frequency ratio mode program this to the previous value divided by 2 and round up to next integer value. Note: Used only for DDR2 DDR3 and.." line.long 0x24 "DRAMTMG9,[FREQ3] SDRAM Timing Register 9" bitfld.long 0x24 30. "DDR4_WR_PREAMBLE,DDR4 Write preamble mode. - 0 - 1tCK preamble - 1 - 2tCK preamble Present only with MEMC_FREQ_RATIO=2. Programming Mode: Quasi-dynamic Group 2 Group 4" "0,1" newline bitfld.long 0x24 16.--18. "T_CCD_S,tCCD_S: This is the minimum time between two reads or two writes for different bank group. For bank switching (from bank 'a' to bank 'b') the minimum time is this value + 1. When the controller is operating in 1:2 frequency ratio mode program.." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x24 8.--11. 1. "T_RRD_S,tRRD_S: This is the minimum time between activates from bank 'a' to bank 'b' for different bank group. When the controller is operating in 1:2 frequency ratio mode program this to (tRRD_S/2) and round it up to the next integer value. Present.." newline hexmask.long.byte 0x24 0.--5. 1. "WR2RD_S,CWL + PL + BL/2 + tWTR_S Minimum time from write command to read command for different bank group. Includes time for bus turnaround recovery times and all per-bank per-rank and global constraints. Present only in designs configured to support.." line.long 0x28 "DRAMTMG10,[FREQ3] SDRAM Timing Register 10" hexmask.long.byte 0x28 16.--20. 1. "T_SYNC_GEAR,Indicates the time between MRS command and the sync pulse time. This must be even number of clocks. For DDR4-2666 and DDR4-3200 this parameter is defined as tMOD(min)+4nCK tMOD(min) is greater of 24nCK or 15ns 15ns / .625ns = 24 Max value.." newline hexmask.long.byte 0x28 8.--12. 1. "T_CMD_GEAR,Indicates a sync pulse to first valid command. For DDR4-2666 and DDR4-3200 this parameter is defined as tMOD(min) tMOD(min) is greater of 24nCK or 15ns 15ns / .625ns = 24 Max value for this register is 24 When the controller is operating in.." newline bitfld.long 0x28 2.--3. "T_GEAR_SETUP,Indicates the geardown setup time. Minimum value of this register is 1. Zero is invalid. For DDR4-2666 and DDR4-3200 this parameter is defined as 2 clks When the controller is operating in 1:2 frequency ratio mode program this to.." "0,1,2,3" newline bitfld.long 0x28 0.--1. "T_GEAR_HOLD,Indicates the geardown hold time. Minimum value of this register is 1. Zero is invalid. For DDR4-2666 and DDR4-3200 this parameter is defined as 2 clks When the controller is operating in 1:2 frequency ratio mode program this to.." "0,1,2,3" line.long 0x2C "DRAMTMG11,[FREQ3] SDRAM Timing Register 11" hexmask.long.byte 0x2C 24.--30. 1. "POST_MPSM_GAP_X32,tXMPDLL: This is the minimum Exit MPSM to commands requiring a locked DLL. When the controller is operating in 1:2 frequency ratio mode program this to (tXMPDLL/2) and round it up to the next integer value. Present only in designs.." newline hexmask.long.byte 0x2C 16.--20. 1. "T_MPX_LH,tMPX_LH: This is the minimum CS_n Low hold time to CKE rising edge. When the controller is operating in 1:2 frequency ratio mode program this to RoundUp(tMPX_LH/2)+1. Present only in designs configured to support DDR4. Unit: DFI clock cycles." newline bitfld.long 0x2C 8.--9. "T_MPX_S,tMPX_S: This is the minimum time CS setup time to CKE. When the controller is operating in 1:2 frequency ratio mode program this to (tMPX_S/2) and round it up to the next integer value. Present only in designs configured to support DDR4. Unit:.." "0,1,2,3" newline hexmask.long.byte 0x2C 0.--4. 1. "T_CKMPE,tCKMPE: This is the minimum valid clock requirement after MPSM entry. Present only in designs configured to support DDR4. When the controller is operating in 1:2 frequency ratio mode divide the value calculated using the previous equation by 2.." line.long 0x30 "DRAMTMG12,[FREQ3] SDRAM Timing Register 12" hexmask.long.byte 0x30 24.--29. 1. "T_WR_MPR,This bit is used only in DDR4. Cycles between MPR Write and other command. Set this to tMOD + AL (or tMOD + PL + AL if C/A parity is also used). When the controller is operating in 1:2 frequency ratio mode program this to (tWR_MPR/2) and round.." newline bitfld.long 0x30 16.--17. "T_CMDCKE,tCMDCKE: Indicates the delay from valid command to CKE input LOW. Set this to the larger of tESCKE or tCMDCKE When the controller is operating in 1:2 frequency ratio mode program this to (max(tESCKE tCMDCKE)/2) and round it up to the next.." "0,1,2,3" newline hexmask.long.byte 0x30 0.--4. 1. "T_MRD_PDA,tMRD_PDA: This is the Mode Register Set command cycle time in PDA mode. When the controller is operating in 1:2 frequency ratio mode program this to (tMRD_PDA/2) and round it up to the next integer value. Unit: DFI clock cycles. Programming.." line.long 0x34 "DRAMTMG13,[FREQ3] SDRAM Timing Register 13" hexmask.long.byte 0x34 24.--30. 1. "ODTLOFF,LPDDR4: ODTLoff: This is the latency from CAS-2 command to ODToff reference. When the controller is operating in 1:2 frequency ratio mode program this to (ODTLoff/2) and round it up to the next integer value. Unit: DFI clock cycles. Programming.." newline hexmask.long.byte 0x34 16.--21. 1. "T_CCD_MW,LPDDR4: tCCDMW: This is the minimum time from write or masked write to masked write command for same bank. When the controller is operating in 1:2 frequency ratio mode program this to (tCCDMW/2) and round it up to the next integer value. Unit:.." newline bitfld.long 0x34 0.--2. "T_PPD,LPDDR4: tPPD: This is the minimum time from precharge to precharge command. When the controller is operating in 1:2 frequency ratio mode program this to (tPPD/2) and round it up to the next integer value. Unit: DFI clock cycles. Programming Mode:.." "?,?,?,?,tPPD: This is the minimum time from precharge to..,?,?,?" line.long 0x38 "DRAMTMG14,[FREQ3] SDRAM Timing Register 14" hexmask.long.word 0x38 0.--11. 1. "T_XSR,tXSR: This is the exit self-refresh to any command. When the controller is operating in 1:2 frequency ratio mode program this to the previous value divided by 2 and round up to next integer value. The value 0xfff is illegal for this register.." line.long 0x3C "DRAMTMG15,[FREQ3] SDRAM Timing Register 15" bitfld.long 0x3C 31. "EN_DFI_LP_T_STAB,- 1 - Enable using tSTAB when exiting DFI LP. This must be set when the PHY is stopping the clock during DFI LP to save maximum power. - 0 - Disable using tSTAB when exiting DFI LP. Programming Mode: Quasi-dynamic Group 2 Group 4" "Disable using tSTAB when exiting DFI LP,Enable using tSTAB when exiting DFI LP" newline hexmask.long.byte 0x3C 0.--7. 1. "T_STAB_X32,tSTAB: Stabilization time. It is required in the following two cases for DDR3/DDR4 RDIMM: - When exiting power saving mode if the clock is stopped after re-enabling it the clock must be stable for a time specified by tSTAB - In the case of.." group.long 0x180++0x3 line.long 0x0 "ZQCTL0,[FREQ3] ZQ Control Register 0" bitfld.long 0x0 31. "DIS_AUTO_ZQ,- 1 - Disable uMCTL2 generation of ZQCS/MPC(ZQ calibration) command. Register DBGCMD.zq_calib_short can be used instead to issue ZQ calibration request from APB module - 0 - Internally generate ZQCS/MPC(ZQ calibration) commands based on.." "Internally generate ZQCS/MPC,Disable uMCTL2 generation of ZQCS/MPC" newline bitfld.long 0x0 30. "DIS_SRX_ZQCL,- 1 - Disable issuing of ZQCL/MPC(ZQ calibration) command at self-refresh/SR-Powerdown exit. Only applicable when run in DDR3 or DDR4 or LPDDR2 or LPDDR3 or LPDDR4 mode - 0 - Enable issuing of ZQCL/MPC(ZQ calibration) command at.." "Enable issuing of ZQCL/MPC,Disable issuing of ZQCL/MPC" newline bitfld.long 0x0 29. "ZQ_RESISTOR_SHARED,- 1 - Denotes that ZQ resistor is shared between ranks. Means ZQinit/ZQCL/ZQCS/MPC(ZQ calibration) commands are sent to one rank at a time with tZQinit/tZQCL/tZQCS/tZQCAL/tZQLAT timing met between commands so that commands to different.." "ZQ resistor is not shared,Denotes that ZQ resistor is shared between ranks" newline bitfld.long 0x0 28. "DIS_MPSMX_ZQCL,- 1 - Disable issuing of ZQCL command at Maximum Power Saving Mode exit. Only applicable when run in DDR4 mode - 0 - Enable issuing of ZQCL command at Maximum Power Saving Mode exit. Only applicable when run in DDR4 mode This is only.." "Enable issuing of ZQCL command at Maximum Power..,Disable issuing of ZQCL command at Maximum Power.." newline hexmask.long.word 0x0 16.--26. 1. "T_ZQ_LONG_NOP,tZQoper for DDR3/DDR4 tZQCL for LPDDR2/LPDDR3 tZQCAL for LPDDR4: Number of DFI clock cycles of NOP required after a ZQCL (ZQ calibration long)/MPC(ZQ Start) command is issued to SDRAM. When the controller is operating in 1:2 frequency.." newline hexmask.long.word 0x0 0.--9. 1. "T_ZQ_SHORT_NOP,tZQCS for DDR3/DD4/LPDDR2/LPDDR3 tZQLAT for LPDDR4: Number of DFI clock cycles of NOP required after a ZQCS (ZQ calibration short)/MPC(ZQ Latch) command is issued to SDRAM. When the controller is operating in 1:2 frequency ratio mode.." group.long 0x190++0x7 line.long 0x0 "DFITMG0,[FREQ3] DFI Timing Register 0" hexmask.long.byte 0x0 24.--28. 1. "DFI_T_CTRL_DELAY,Specifies the number of DFI clock cycles after an assertion or de-assertion of the DFI control signals that the control signals at the PHY-DRAM interface reflect the assertion or de-assertion. If the DFI clock and the memory clock are.." newline bitfld.long 0x0 23. "DFI_RDDATA_USE_DFI_PHY_CLK,Defines whether dfi_rddata_en/dfi_rddata/dfi_rddata_valid is generated using HDR (DFI clock) or SDR (DFI PHY clock) values. Selects whether value in DFITMG0.dfi_t_rddata_en is in terms of HDR (DFI clock) or SDR (DFI PHY clock).." "Else,?" newline hexmask.long.byte 0x0 16.--22. 1. "DFI_T_RDDATA_EN,Time from the assertion of a read command on the DFI interface to the assertion of the dfi_rddata_en signal. Refer to PHY specification for correct value. This corresponds to the DFI parameter trddata_en. Note that depending on the PHY.." newline bitfld.long 0x0 15. "DFI_WRDATA_USE_DFI_PHY_CLK,Defines whether dfi_wrdata_en/dfi_wrdata/dfi_wrdata_mask is generated using HDR (DFI clock) or SDR (DFI PHY clock) values. Selects whether value in DFITMG0.dfi_tphy_wrlat is in terms of HDR (DFI clock) or SDR (DFI PHY clock).." "Else,?" newline hexmask.long.byte 0x0 8.--13. 1. "DFI_TPHY_WRDATA,Specifies the number of clock cycles between when dfi_wrdata_en is asserted to when the associated write data is driven on the dfi_wrdata signal. This corresponds to the DFI timing parameter tphy_wrdata. For more information on correct.." newline hexmask.long.byte 0x0 0.--5. 1. "DFI_TPHY_WRLAT,Write latency. Number of clocks from the write command to write data enable (dfi_wrdata_en). This corresponds to the DFI timing parameter tphy_wrlat. Refer to PHY specification for correct value.Note that depending on the PHY if using.." line.long 0x4 "DFITMG1,[FREQ3] DFI Timing Register 1" hexmask.long.byte 0x4 28.--31. 1. "DFI_T_CMD_LAT,Specifies the number of DFI PHY clock cycles between when the dfi_cs signal is asserted and when the associated command is driven. This field is used for CAL mode must be set to '0' or tCAL which matches the CAL mode register setting in.." newline bitfld.long 0x4 24.--25. "DFI_T_PARIN_LAT,Specifies the number of DFI PHY clock cycles between when the dfi_cs signal is asserted and when the associated dfi_parity_in signal is driven. Unit: DFI PHY clock cycles. Programming Mode: Quasi-dynamic Group 4" "0,1,2,3" newline hexmask.long.byte 0x4 16.--20. 1. "DFI_T_WRDATA_DELAY,Specifies the number of DFI clock cycles between when the dfi_wrdata_en signal is asserted and when the corresponding write data transfer is completed on the DRAM bus. This corresponds to the DFI timing parameter twrdata_delay. For.." newline hexmask.long.byte 0x4 8.--12. 1. "DFI_T_DRAM_CLK_DISABLE,Specifies the number of DFI clock cycles from the assertion of the dfi_dram_clk_disable signal on the DFI until the clock to the DRAM memory devices at the PHY-DRAM boundary maintains a low value. If the DFI clock and the memory.." newline hexmask.long.byte 0x4 0.--4. 1. "DFI_T_DRAM_CLK_ENABLE,Specifies the number of DFI clock cycles from the de-assertion of the dfi_dram_clk_disable signal on the DFI until the first valid rising edge of the clock to the DRAM memory devices at the PHY-DRAM boundary. If the DFI clock and.." group.long 0x1B4++0x7 line.long 0x0 "DFITMG2,[FREQ3] DFI Timing Register 2" hexmask.long.byte 0x0 8.--14. 1. "DFI_TPHY_RDCSLAT,specifies the number of DFI PHY clock cycles between when a read command is sent on the DFI control interface and when the associated dfi_rddata_cs signal is asserted. This corresponds to the DFI timing parameter tphy_rdcslat. Refer to.." newline hexmask.long.byte 0x0 0.--5. 1. "DFI_TPHY_WRCSLAT,Specifies the number of DFI PHY clock cycles between when a write command is sent on the DFI control interface and when the associated dfi_wrdata_cs signal is asserted. This corresponds to the DFI timing parameter tphy_wrcslat. For more.." line.long 0x4 "DFITMG3,[FREQ3] DFI Timing Register 3" hexmask.long.byte 0x4 0.--4. 1. "DFI_T_GEARDOWN_DELAY,The delay from dfi_geardown_en assertion to the time of the PHY being ready to receive commands. Refer to PHY specification for correct value. When the controller is operating in 1:2 frequency ratio mode program this to.." group.long 0x240++0x3 line.long 0x0 "ODTCFG,[FREQ3] ODT Configuration Register" hexmask.long.byte 0x0 24.--27. 1. "WR_ODT_HOLD,DFI PHY clock cycles to hold ODT for a write command. The minimum supported value is 2. Recommended values: DDR2: - BL8 - 0x5 (DDR2-400/533/667) 0x6 (DDR2-800) 0x7 (DDR2-1066) - BL4 - 0x3 (DDR2-400/533/667) 0x4 (DDR2-800) 0x5 (DDR2-1066).." newline hexmask.long.byte 0x0 16.--20. 1. "WR_ODT_DELAY,Indicates the delay in DFI PHY clock cycles from issuing a write command to setting ODT values associated with that command. ODT setting must remain constant for the entire time that DQS is driven by the uMCTL2. Recommended values: DDR2: -.." newline hexmask.long.byte 0x0 8.--11. 1. "RD_ODT_HOLD,DFI PHY clock cycles to hold ODT for a read command. The minimum supported value is 2. Recommended values: DDR2: - BL8 - 0x6 (not DDR2-1066) 0x7 (DDR2-1066) - BL4 - 0x4 (not DDR2-1066) 0x5 (DDR2-1066) DDR3: - BL8 - 0x6 DDR4: - BL8 - 5 +.." newline hexmask.long.byte 0x0 2.--6. 1. "RD_ODT_DELAY,Indicates the delay in DFI PHY clock cycles from issuing a read command to setting ODT values associated with that command. ODT setting must remain constant for the entire time that DQS is driven by the uMCTL2. Recommended values: DDR2: -.." tree.end tree.end elif (CORENAME()=="CORTEXA55") tree "DDR_CTRL" base ad:0x33000000 tree "UMCTL2_REGS (uMCTL2 DDRC Registers)" group.long 0x0++0x3 line.long 0x0 "MSTR,Master Register0" bitfld.long 0x0 30.--31. "DEVICE_CONFIG,Indicates the configuration of the device used in the system. - 00 - x4 device - 01 - x8 device - 10 - x16 device - 11 - x32 device Programming Mode: Static" "x4 device,x8 device,?,?" newline bitfld.long 0x0 29. "FREQUENCY_MODE,Selects which registers are used. - 0 - Original registers - 1 - When UMCTL2_FREQUENCY_NUM=2: FREQ1 registers When UMCTL2_FREQUENCY_NUM>2: Choosen by MSTR2.target_frequency register. Programming Mode: Quasi-dynamic Group 2" "Original registers,When UMCTL2_FREQUENCY_NUM=2: FREQ1 registers" newline rbitfld.long 0x0 26.--28. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 24.--25. "ACTIVE_RANKS,Only present for multi-rank configurations. Each bit represents one rank. For two-rank configurations only bits[25:24] are present. - 1 - Populated - 0 - Unpopulated LSB is the lowest rank number. For two ranks following combinations are.." "Unpopulated,One rank,?,?" newline hexmask.long.byte 0x0 20.--23. 1. "RESERVED,Reserved" newline hexmask.long.byte 0x0 16.--19. 1. "BURST_RDWR,Indicates SDRAM burst length used: - 0001 - Burst length of 2 (only supported for mDDR) - 0010 - Burst length of 4 - 0100 - Burst length of 8 - 1000 - Burst length of 16 (only supported for mDDR LPDDR2 and LPDDR4) All other values are.." newline bitfld.long 0x0 15. "DLL_OFF_MODE,Set to: - 1 - When the uMCTL2 and DRAM has to be put in DLL-off mode for low frequency operation - 0 - To put uMCTL2 and DRAM in DLL-on mode for normal frequency operation If DDR4 CRC/parity retry is enabled.." "To put uMCTL2 and DRAM in DLL-on mode for normal..,When the uMCTL2 and DRAM has to be put in.." newline rbitfld.long 0x0 14. "RESERVED,Reserved" "0,1" newline bitfld.long 0x0 12.--13. "DATA_BUS_WIDTH,Selects proportion of DQ bus width that is used by the SDRAM. - 00 - Full DQ bus width to SDRAM - 01 - Half DQ bus width to SDRAM - 10 - Quarter DQ bus width to SDRAM - 11 - Reserved Note that half bus width mode is only supported when the.." "Full DQ bus width to SDRAM,Half DQ bus width to SDRAM,?,?" newline bitfld.long 0x0 11. "GEARDOWN_MODE,- 1 - Indicates the DRAM in geardown mode (2N) - 0 - Indicates the DRAM in normal mode (1N) This register can be changed only when the controller is in the self-refresh mode. This signal must be set the same value as MR3 bit A3. Note: -.." "Indicates the DRAM in normal mode,Indicates the DRAM in geardown mode" newline bitfld.long 0x0 10. "EN_2T_TIMING_MODE,If 1 then uMCTL2 uses 2T timing otherwise uses 1T timing. In 2T timing all command signals (except chip select) are held for 2 clocks on the SDRAM bus. Chip select is asserted on the second cycle of the command. Note: - 2T timing is.." "0,1" newline bitfld.long 0x0 9. "BURSTCHOP,When this bit is set enables burst-chop (BC4 or 8 on-the-fly) in DDR3/DDR4. Burst Chop for reads is exercised only: - In HIF configurations (UMCTL2_INCL_ARB not set) - If in full bus width mode (MSTR.data_bus_width = 00) - If.." "0,1" newline rbitfld.long 0x0 6.--8. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 5. "LPDDR4,Selects LPDDR4 SDRAM. - 1 - LPDDR4 SDRAM device in use - 0 - non-LPDDR4 device in use Present only in designs configured to support LPDDR4. Programming Mode: Static" "non-LPDDR4 device in use,LPDDR4 SDRAM device in use" newline bitfld.long 0x0 4. "DDR4,Selects DDR4 SDRAM. - 1 - DDR4 SDRAM device in use - 0 - non-DDR4 device in use Present only in designs configured to support DDR4. Programming Mode: Static" "non-DDR4 device in use,DDR4 SDRAM device in use" newline bitfld.long 0x0 3. "LPDDR3,Selects LPDDR3 SDRAM. - 1 - LPDDR3 SDRAM device in use - 0 - non-LPDDR3 device in use Present only in designs configured to support LPDDR3. Programming Mode: Static" "non-LPDDR3 device in use,LPDDR3 SDRAM device in use" newline bitfld.long 0x0 2. "LPDDR2,Selects LPDDR2 SDRAM. - 1 - LPDDR2 SDRAM device in use - 0 - non-LPDDR2 device in use Present only in designs configured to support LPDDR2. Programming Mode: Static" "non-LPDDR2 device in use,LPDDR2 SDRAM device in use" newline rbitfld.long 0x0 1. "RESERVED,Reserved" "0,1" newline bitfld.long 0x0 0. "DDR3,Selects DDR3 SDRAM. - 1 - DDR3 SDRAM device in use - 0 - non-DDR3 SDRAM device in use Present only in designs configured to support DDR3. Programming Mode: Static" "non-DDR3 SDRAM device in use,DDR3 SDRAM device in use" rgroup.long 0x4++0x3 line.long 0x0 "STAT,Operating Mode Status Register" hexmask.long.tbyte 0x0 13.--31. 1. "RESERVED,Reserved" newline bitfld.long 0x0 12. "SELFREF_CAM_NOT_EMPTY,Self-refresh with CAMs not empty. Set to 1 when self-refresh is entered but CAMs are not drained. Cleared after exiting self-refresh. Programming Mode: Static" "0,1" newline bitfld.long 0x0 10.--11. "RESERVED,Reserved" "0,1,2,3" newline bitfld.long 0x0 8.--9. "SELFREF_STATE,This indicates self-refresh or self-refresh power down state for LPDDR4. This register is used for frequency change and MRR/MRW access during self-refresh. - 00 - SDRAM is not in self-refresh - 01 - Self-refresh 1 - 10 - Self-refresh power.." "SDRAM is not in self-refresh,Self-refresh 1,?,?" newline bitfld.long 0x0 6.--7. "RESERVED,Reserved" "0,1,2,3" newline bitfld.long 0x0 4.--5. "SELFREF_TYPE,Flags if self-refresh (except LPDDR4) or SR-Powerdown (LPDDR4) is entered and if it is under automatic self-refresh control only or not. - 00 - SDRAM is not in self-refresh (except LPDDR4) or SR-Powerdown (LPDDR4). If retry is enabled by.." "SDRAM is not in self-refresh,SDRAM is in self-refresh,?,?" newline bitfld.long 0x0 3. "RESERVED,Reserved" "0,1" newline bitfld.long 0x0 0.--2. "OPERATING_MODE,This is 3-bits wide in configurations with mDDR/LPDDR2/LPDDR3/LPDDR4/DDR4 support and 2-bits in all other configurations. non-mDDR/LPDDR2/LPDDR3/LPDDR4 and non-DDR4 designs: - 00 - Init - 01 - Normal - 10 - Power-down - 11 - Self-refresh.." "Init,Normal,?,bits wide in configurations with..,?,?,?,?" group.long 0x10++0x7 line.long 0x0 "MRCTRL0,Mode Register Read/Write Control Register 0. Note: Do not enable more than one of the following fields simultaneously: - sw_init_int - pda_en - mpr_en" bitfld.long 0x0 31. "MR_WR,Setting this register bit to 1 triggers a mode register read or write operation. When the MR operation is complete the uMCTL2 automatically clears this bit. The other fields of this register must be written in a separate APB transaction before.." "0,1" newline bitfld.long 0x0 30. "PBA_MODE,Indicates whether PBA access is executed. When setting this bit to 1 along with setting pda_en to 1 uMCTL2 initiates PBA access instead of PDA access. - 0 - Per DRAM Addressability mode - 1 - Per Buffer Addressability mode The completion of PBA.." "Per DRAM Addressability mode,Per Buffer Addressability mode" newline hexmask.long.word 0x0 16.--29. 1. "RESERVED,Reserved" newline hexmask.long.byte 0x0 12.--15. 1. "MR_ADDR,Address of the mode register that is to be written to. - 0000 - MR0 - 0001 - MR1 - 0010 - MR2 - 0011 - MR3 - 0100 - MR4 - 0101 - MR5 - 0110 - MR6 - 0111 - MR7 Don't Care for LPDDR2/LPDDR3/LPDDR4 (see MRCTRL1.mr_data for mode register addressing.." newline hexmask.long.byte 0x0 6.--11. 1. "RESERVED,Reserved" newline bitfld.long 0x0 4.--5. "MR_RANK,Controls which rank is accessed by MRCTRL0.mr_wr. Normally it is desired to access all ranks so all bits must be set to 1. However for multi-rank UDIMMs/RDIMMs/LRDIMMs which implement address mirroring it might be necessary to access ranks.." "?,Select rank 0 only,Select rank 1 only,?" newline bitfld.long 0x0 3. "SW_INIT_INT,Indicates whether software intervention is allowed through MRCTRL0/MRCTRL1 before automatic SDRAM initialization routine or not. For DDR4 this bit can be used to initialize the DDR4 RCD (MR7) before automatic SDRAM initialization. For LPDDR4.." "Software intervention is not allowed,Software intervention is allowed" newline bitfld.long 0x0 2. "PDA_EN,Indicates whether the mode register operation is MRS in PDA mode or not. - 0 - MRS - 1 - MRS in Per DRAM Addressability mode Note that when pba_mode=1 PBA access is initiated instead of PDA access. Programming Mode: Dynamic" "MRS,MRS in Per DRAM Addressability mode" newline bitfld.long 0x0 1. "MPR_EN,Indicates whether the mode register operation is MRS or WR/RD for MPR (only supported for DDR4). - 0 - MRS - 1 - WR/RD for MPR Programming Mode: Dynamic" "MRS,WR/RD for MPR" newline bitfld.long 0x0 0. "MR_TYPE,Indicates whether the mode register operation is read or write. Only used for LPDDR2/LPDDR3/LPDDR4/DDR4. - 0 - Write - 1 - Read Programming Mode: Dynamic" "Write,Read" line.long 0x4 "MRCTRL1,Mode Register Read/Write Control Register 1" hexmask.long.word 0x4 18.--31. 1. "RESERVED,Reserved" newline hexmask.long.tbyte 0x4 0.--17. 1. "MR_DATA,Mode register write data for all non-LPDDR2/non-LPDDR3/non-LPDDR4 modes. For LPDDR2/LPDDR3/LPDDR4 MRCTRL1[15:0] are interpreted as: - [15:8] - MR Address - [7:0] - MR data for writes don't care for reads This is 18-bits wide in configurations.." rgroup.long 0x18++0x3 line.long 0x0 "MRSTAT,Mode Register Read/Write Status Register" hexmask.long.tbyte 0x0 9.--31. 1. "RESERVED,Reserved" newline bitfld.long 0x0 8. "PDA_DONE,The SoC might initiate a MR write operation in PDA/PBA mode only if this signal is low. This signal goes: - High when three consecutive MRS commands related to the PDA/PBA mode are issued to the SDRAM - Low when MRCTRL0.pda_en becomes 0.." "Indicates that mode register write operation..,Indicates that mode register write operation.." newline hexmask.long.byte 0x0 1.--7. 1. "RESERVED,Reserved" newline bitfld.long 0x0 0. "MR_WR_BUSY,The SoC might initiate a MR write operation only if this signal is low. This signal goes: - High in the clock after the uMCTL2 accepts the MRW/MRR request - Low when the MRW/MRR command is issued to the SDRAM It is recommended not to perform.." "Indicates that the SoC can initiate a mode..,Indicates that mode register write operation is.." group.long 0x1C++0x1F line.long 0x0 "MRCTRL2,Mode Register Read/Write Control Register 2" hexmask.long 0x0 0.--31. 1. "MR_DEVICE_SEL,Indicates the devices to be selected during the MRS that happens in PDA mode. Each bit is associated with one device. For example bit[0] corresponds to Device 0 bit[1] to Device 1 and so on. - 1 - Indicates that the MRS command must be.." line.long 0x4 "DERATEEN,Temperature Derate Enable Register" hexmask.long.tbyte 0x4 13.--31. 1. "RESERVED,Reserved" newline bitfld.long 0x4 12. "DERATE_MR4_TUF_DIS,Disables use of MR4 TUF flag (MR4[7]) bit. - 0 - Use MR4 TUF flag (MR4[7]) - 1 - Do not use MR4 TUF Flag (MR4[7]) For LPDDR4 it is recommended to set this register to 1. For LPDDR2 and LPDDR3 contact your memory vendor for.." "Use MR4 TUF flag,Do not use MR4 TUF Flag" newline rbitfld.long 0x4 11. "RESERVED,Reserved" "0,1" newline bitfld.long 0x4 8.--10. "RC_DERATE_VALUE,Derate value of tRC for LPDDR4. - 0 - Derating uses +1 - 1 - Derating uses +2 - 2 - Derating uses +3 - 3 - Derating uses +4 Present only in designs configured to support LPDDR4. The required cycles for derating can be determined by.." "Derating uses +1,Derating uses +2,Derating uses +3,Derating uses +4,?,?,?,?" newline hexmask.long.byte 0x4 4.--7. 1. "DERATE_BYTE,This bit indicates which byte of the MRR data is used for derating. The maximum valid value depends on MEMC_DRAM_TOTAL_DATA_WIDTH. Present only in designs configured to support LPDDR2/LPDDR3/LPDDR4. Programming Mode: Static" newline rbitfld.long 0x4 3. "RESERVED,Reserved" "0,1" newline bitfld.long 0x4 1.--2. "DERATE_VALUE,Derate value. - 0 - Derating uses +1 - 1 - Derating uses +2 Present only in designs configured to support LPDDR2/LPDDR3/LPDDR4. Set to 0 for all LPDDR2 speed grades as derating value of +1.875 ns is less than a core_ddrc_core_clk period. For.." "Derating uses +1,Derating uses +2,?,?" newline bitfld.long 0x4 0. "DERATE_ENABLE,Enables derating. - 0 - Timing parameter derating is disabled - 1 - Timing parameter derating is enabled using MR4 read value Present only in designs configured to support LPDDR2/LPDDR3/LPDDR4. This field must be set to '0' for.." "Timing parameter derating is disabled,Timing parameter derating is enabled using MR4.." line.long 0x8 "DERATEINT,Temperature Derate Interval Register" hexmask.long 0x8 0.--31. 1. "MR4_READ_INTERVAL,Interval between two MR4 reads used to derate the timing parameters. Present only in designs configured to support LPDDR2/LPDDR3/LPDDR4. This register must not be set to zero. Unit: DFI clock cycles. Programming Mode: Static" line.long 0xC "MSTR2,Master Register2" hexmask.long 0xC 2.--31. 1. "RESERVED,Reserved" newline bitfld.long 0xC 0.--1. "TARGET_FREQUENCY,If MSTR.frequency_mode = 1 this field specifies the target frequency. - 0 - Frequency 0/Normal - 1 - Frequency 1/FREQ1 - 2 - Frequency 2/FREQ2 - 3 - Frequency 3/FREQ3 If MSTR.frequency_mode=0 this field is ignored. Note: If the target.." "Frequency 0/Normal,Frequency 1/FREQ1,Frequency 2/FREQ2,Frequency 3/FREQ3" line.long 0x10 "DERATECTL,Temperature Derate Control Register" hexmask.long 0x10 3.--31. 1. "RESERVED,Reserved" newline bitfld.long 0x10 2. "DERATE_TEMP_LIMIT_INTR_FORCE,Interrupt force bit for derate_temp_limit_intr. Setting this field to 1 causes the derate_temp_limit_intr output pin to be asserted. At the end of the interrupt force operation the uMCTL2 automatically clears this bit." "0,1" newline bitfld.long 0x10 1. "DERATE_TEMP_LIMIT_INTR_CLR,Interrupt clear bit for derate_temp_limit_intr. At the end of the interrupt clear operation the uMCTL2 automatically clears this bit. Programming Mode: Dynamic" "0,1" newline bitfld.long 0x10 0. "DERATE_TEMP_LIMIT_INTR_EN,Interrupt enable bit for derate_temp_limit_intr output pin. - 1 - Enabled - 0 - Disabled Programming Mode: Dynamic" "Disabled,Enabled" line.long 0x14 "PWRCTL,Low Power Control Register" hexmask.long.tbyte 0x14 9.--31. 1. "RESERVED,Reserved" newline bitfld.long 0x14 8. "LPDDR4_SR_ALLOWED,Indicates whether transition from SR-PD to SR and back to SR-PD is allowed. This register field cannot be modified while PWRCTL.selfref_sw == 1. - 0 - SR-PD -> SR -> SR-PD not allowed - 1 - SR-PD -> SR -> SR-PD allowed Programming Mode:.." "SR-PD,SR-PD" newline bitfld.long 0x14 7. "DIS_CAM_DRAIN_SELFREF,Indicates whether skipping CAM draining is allowed when entering self-refresh. This register field cannot be modified while PWRCTL.selfref_sw == 1. - 0 - CAMs must be empty before entering SR - 1 - CAMs are not emptied before.." "CAMs must be empty before entering SR,CAMs are not emptied before entering SR" newline bitfld.long 0x14 6. "STAY_IN_SELFREF,Self-refresh state is an intermediate state to enter to self-refresh power down state or exit self-refresh power down state for LPDDR4. This register controls transition from the self-refresh state. - 1 - Prohibit transition from.." "Allow transition from self-refresh state,Prohibit transition from self-refresh state" newline bitfld.long 0x14 5. "SELFREF_SW,A value of 1 to this register causes system to move to self-refresh state immediately as long as it is not in INIT or DPD/MPSM operating_mode. This is referred to as Software Entry/Exit to self-refresh. - 1 - Software Entry to self-refresh -.." "Software Exit from self-refresh,Software Entry to self-refresh" newline bitfld.long 0x14 4. "MPSM_EN,When this bit is 1 the uMCTL2 puts the SDRAM into maximum power saving mode when the transaction store is empty. This register must be reset to '0' to bring uMCTL2 out of maximum power saving mode. Present only in designs configured to support.." "0,1" newline bitfld.long 0x14 3. "EN_DFI_DRAM_CLK_DISABLE,Enables the assertion of dfi_dram_clk_disable whenever a clock is not required by the SDRAM. If set to 0 dfi_dram_clk_disable is never asserted. Assertion of dfi_dram_clk_disable is as follows: In DDR2/DDR3 can only be asserted.." "0,1" newline bitfld.long 0x14 2. "DEEPPOWERDOWN_EN,When this bit is 1 uMCTL2 puts the SDRAM into deep power-down mode when the transaction store is empty. This register must be reset to '0' to bring uMCTL2 out of deep power-down mode. The controller performs automatic SDRAM.." "0,1" newline bitfld.long 0x14 1. "POWERDOWN_EN,If true then the uMCTL2 goes into power-down after a programmable number of cycles 'maximum idle clocks before power down' (PWRTMG.powerdown_to_x32). This register bit may be re-programmed during the course of normal operation. Programming.." "0,1" newline bitfld.long 0x14 0. "SELFREF_EN,If true then the uMCTL2 puts the SDRAM into self-refresh after a programmable number of cycles 'maximum idle clocks before self-refresh (PWRTMG.selfref_to_x32)'. This register bit may be re-programmed during the course of normal operation." "0,1" line.long 0x18 "PWRTMG,Low Power Timing Register" hexmask.long.byte 0x18 24.--31. 1. "RESERVED,Reserved" newline hexmask.long.byte 0x18 16.--23. 1. "SELFREF_TO_X32,After this many clocks of the DDRC command channel being idle the uMCTL2 automatically puts the SDRAM into self-refresh. The DDRC command channel is considered idle when there are no HIF commands outstanding. This must be enabled in the.." newline hexmask.long.byte 0x18 8.--15. 1. "T_DPD_X4096,Minimum deep power-down time. For mDDR value from the JEDEC specification is 0 as mDDR exits from deep power-down mode immediately after PWRCTL.deeppowerdown_en is de-asserted. For LPDDR2/LPDDR3 value from the JEDEC specification is 500us." newline rbitfld.long 0x18 5.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x18 0.--4. 1. "POWERDOWN_TO_X32,After this many clocks of the DDRC command channel being idle the uMCTL2 automatically puts the SDRAM into power-down. The DDRC command channel is considered idle when there are no HIF commands outstanding. This must be enabled in the.." line.long 0x1C "HWLPCTL,Hardware Low Power Control Register" hexmask.long.byte 0x1C 28.--31. 1. "RESERVED,Reserved" newline hexmask.long.word 0x1C 16.--27. 1. "HW_LP_IDLE_X32,Hardware idle period. The cactive_ddrc output is driven low if the DDRC command channel is idle for hw_lp_idle * 32 cycles if not in INIT or DPD/MPSM operating_mode. The DDRC command channel is considered idle when there are no HIF.." newline hexmask.long.word 0x1C 2.--15. 1. "RESERVED,Reserved" newline bitfld.long 0x1C 1. "HW_LP_EXIT_IDLE_EN,When this bit is programmed to 1 the cactive_in_ddrc pin of the DDRC can be used to exit from the automatic clock stop automatic power down or automatic self-refresh modes. Note it does not cause exit of self-refresh that was caused.." "0,1" newline bitfld.long 0x1C 0. "HW_LP_EN,Enable this bit for Hardware Low Power Interface. Programming Mode: Quasi-dynamic Group 2" "0,1" group.long 0x50++0x7 line.long 0x0 "RFSHCTL0,Refresh Control Register 0" hexmask.long.byte 0x0 24.--31. 1. "RESERVED,Reserved" newline hexmask.long.byte 0x0 20.--23. 1. "REFRESH_MARGIN,Threshold value in number of DFI clock cycles before the critical refresh or page timer expires. A critical refresh is to be issued before this threshold is reached. It is recommended that this not be changed from the default value.." newline rbitfld.long 0x0 17.--19. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x0 12.--16. 1. "REFRESH_TO_X1_X32,If the refresh timer (tRFCnom also known as tREFI) has expired at least once then a speculative refresh may be performed. A speculative refresh is a refresh performed at a time when refresh would be useful. When the SDRAM bus is idle.." newline rbitfld.long 0x0 10.--11. "RESERVED,Reserved" "0,1,2,3" newline hexmask.long.byte 0x0 4.--9. 1. "REFRESH_BURST,The programmed value + 1 is the number of refresh timeouts that is allowed to accumulate before traffic is blocked and the refreshes are forced to execute. Closing pages to perform a refresh is a one-time penalty that must be paid for each.." newline rbitfld.long 0x0 3. "RESERVED,Reserved" "0,1" newline bitfld.long 0x0 2. "PER_BANK_REFRESH,- 1 - Per bank refresh - 0 - All bank refresh Per bank refresh allows traffic to flow to other banks. Per bank refresh is not supported by all LPDDR2 devices but must be supported by all LPDDR3/LPDDR4 devices. Present only in designs.." "All bank refresh,Per bank refresh" newline rbitfld.long 0x0 0.--1. "RESERVED,Reserved" "0,1,2,3" line.long 0x4 "RFSHCTL1,Refresh Control Register 1" hexmask.long.byte 0x4 28.--31. 1. "RESERVED,Reserved" newline hexmask.long.word 0x4 16.--27. 1. "REFRESH_TIMER1_START_VALUE_X32,Refresh timer start for rank 1 (only present in multi-rank configurations). This is useful in staggering the refreshes to multiple ranks to help traffic to proceed. This is explained in Refresh Controls section of the.." newline hexmask.long.byte 0x4 12.--15. 1. "RESERVED,Reserved" newline hexmask.long.word 0x4 0.--11. 1. "REFRESH_TIMER0_START_VALUE_X32,Refresh timer start for rank 0 (only present in multi-rank configurations). This is useful in staggering the refreshes to multiple ranks to help traffic to proceed. This is explained in Refresh Controls section of the.." group.long 0x60++0xB line.long 0x0 "RFSHCTL3,Refresh Control Register 3" hexmask.long 0x0 7.--31. 1. "RESERVED,Reserved" newline bitfld.long 0x0 4.--6. "REFRESH_MODE,Indicates fine granularity refresh mode. - 000 - Fixed 1x (Normal mode) - 001 - Fixed 2x - 010 - Fixed 4x - 101 - Enable on the fly 2x (not supported) - 110 - Enable on the fly 4x (not supported) - Everything else - reserved Note: - Only.." "Fixed 1x,The on-the-fly modes are not supported in this..,This register field has effect only if a DDR4..,?,?,?,?,?" newline rbitfld.long 0x0 2.--3. "RESERVED,Reserved" "0,1,2,3" newline bitfld.long 0x0 1. "REFRESH_UPDATE_LEVEL,Toggle this signal (either from 0 to 1 or from 1 to 0) to indicate that the refresh registers have been updated. refresh_update_level must not be toggled when the DDRC is in reset (core_ddrc_rstn = 0). The refresh registers are.." "0,1" newline bitfld.long 0x0 0. "DIS_AUTO_REFRESH,When '1' disable auto-refresh generated by the uMCTL2. When auto-refresh is disabled the SoC must generate refreshes using the registers DBGCMD.rankn_refresh. When dis_auto_refresh transitions from 0 to 1 any pending refreshes are.." "0,1" line.long 0x4 "RFSHTMG,Refresh Timing Register" bitfld.long 0x4 31. "T_RFC_NOM_X1_SEL,Specifies whether the RFSHTMG.t_rfc_nom_x1_x32 and RFSHCTL0.refresh_to_x1_x32 register values are x1 or x32. - 0 - x32 register values are used - 1 - x1 register values are used This applies only when per-bank refresh is enabled.." "x32 register values are used,x1 register values are used" newline rbitfld.long 0x4 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline hexmask.long.word 0x4 16.--27. 1. "T_RFC_NOM_X1_X32,Average time interval between refreshes per rank (Specification: 7.8us for DDR2 DDR3 and DDR4. See JEDEC specification for mDDR LPDDR2 LPDDR3 and LPDDR4). When the controller is operating in 1:1 mode set this register to.." newline bitfld.long 0x4 15. "LPDDR3_TREFBW_EN,Used only when LPDDR3 memory type is connected. Should only be changed when uMCTL2 is in reset. Specifies whether to use the tREFBW parameter (required by some LPDDR3 devices which comply with earlier versions of the LPDDR3 JEDEC.." "tREFBW parameter not used,tREFBW parameter used" newline hexmask.long.byte 0x4 10.--14. 1. "RESERVED,Reserved" newline hexmask.long.word 0x4 0.--9. 1. "T_RFC_MIN,tRFC (min): Minimum time from refresh to refresh or activate. When the controller is operating in 1:1 mode t_rfc_min must be set to RoundUp(tRFCmin/tCK). When the controller is operating in 1:2 mode t_rfc_min must be set to.." line.long 0x8 "RFSHTMG1,Refresh Timing Register1" hexmask.long.byte 0x8 24.--31. 1. "RESERVED,Reserved" newline hexmask.long.byte 0x8 16.--23. 1. "T_PBR2PBR,LPDDR4:tpbR2pbR. Per-bank refresh to Per-bank refresh different bank Time. When the controller is operating in 1:1 frequency ratio mode program this to RoundUp(tpbR2pbR/tCK). When the controller is operating in 1:2 frequency ratio mode.." newline hexmask.long.word 0x8 0.--15. 1. "RESERVED,Reserved" group.long 0x70++0x7 line.long 0x0 "ECCCFG0,ECC Configuration Register 0" bitfld.long 0x0 30.--31. "ECC_REGION_MAP_GRANU,Indicates granularity of selectable protected region. Define one region size for ECCCFG0.ecc_region_map. - 0 - 1/8 of memory spaces - 1 - 1/16 of memory spaces - 2 - 1/32 of memory spaces - 3 - 1/64 of memory spaces Programming Mode:.." "0,1,2,3" newline bitfld.long 0x0 29. "ECC_REGION_MAP_OTHER,When ECCCFG0.ecc_region_map_granu>0 there is a region which is not controlled by ecc_region_map. This register defines the region to be protected or non-protected for Inline ECC. - 0 - Non-Protected - 1 - Protected This register is.." "Non-Protected,Protected" newline rbitfld.long 0x0 27.--28. "RESERVED,Reserved" "0,1,2,3" newline bitfld.long 0x0 24.--26. "ECC_AP_ERR_THRESHOLD,Sets threshold for address parity error. ECCAPSTAT.ecc_ap_err is asserted if number of ECC errors (correctable/uncorrectable) within one burst exceeds this threshold. This register value must be less than 'Total number of ECC checks.." "0,1,2,3,4,5,6,7" newline rbitfld.long 0x0 22.--23. "RESERVED,Reserved" "0,1,2,3" newline hexmask.long.byte 0x0 16.--21. 1. "BLK_CHANNEL_IDLE_TIME_X32,Indicates the number of cycles on HIF interface with no access to protected regions which causes flush of all the block channels. In order to flush block channel uMCTL2 injects write ECC command (when there is no incoming HIF.." newline rbitfld.long 0x0 15. "RESERVED,Reserved" "0,1" newline hexmask.long.byte 0x0 8.--14. 1. "ECC_REGION_MAP,Selectable Protected Region setting. Memory space is divided to 8/16/32/64 regions which is determined by ECCCFG0.ecc_region_map_granu. Note: Highest 1/8 memory space is always ECC region. Lowest 7 regions are Selectable Protected Regions." newline bitfld.long 0x0 7. "ECC_REGION_REMAP_EN,Enables remapping ECC region feature. Only supported when inline ECC is enabled. - 0 - Disable - 1 - Enable Programming Mode: Static" "Disable,Enable" newline bitfld.long 0x0 6. "ECC_AP_EN,Enables address protection feature. Only supported when inline ECC is enabled. - 0 - Disable - 1 - Enable Programming Mode: Static" "Disable,Enable" newline rbitfld.long 0x0 5. "RESERVED,Reserved" "0,1" newline bitfld.long 0x0 4. "DIS_SCRUB,Disables ECC scrubs. Valid only when ECCCFG0.ecc_mode = 3'b100 or 3'b101 and MEMC_USE_RMW is defined. Note: Scrub is not supported in inline ECC mode and the register value is don't care. Programming Mode: Static" "0,1" newline rbitfld.long 0x0 3. "RESERVED,Reserved" "0,1" newline bitfld.long 0x0 0.--2. "ECC_MODE,ECC mode indicator. - 000 - ECC disabled - 100 - ECC enabled - SEC/DED over 1 beat - 101 - ECC enabled - Advanced ECC (Illegal value when MEMC_INLINE_ECC=1) - all other settings are reserved for future use Programming Mode: Static" "ECC disabled,?,?,?,?,?,?,?" line.long 0x4 "ECCCFG1,ECC Configuration Register 1" hexmask.long.tbyte 0x4 12.--31. 1. "RESERVED,Reserved" newline hexmask.long.byte 0x4 8.--11. 1. "ACTIVE_BLK_CHANNEL,Indicated the number of active block channels. Total number of ECC block channels are defined by MEMC_NO_OF_BLK_CHANNEL hardware parameter. This register can limit the number of available channels. For example if set to 0 only one.." newline bitfld.long 0x4 7. "BLK_CHANNEL_ACTIVE_TERM,If enabled block channel is terminated when full block write or full block read is performed (all address within block are written or read). - 0 - Disable (only for debug purpose) - 1 - Enable (default) This is debug register.." "Disable,Enable" newline rbitfld.long 0x4 6. "RESERVED,Reserved" "0,1" newline bitfld.long 0x4 5. "ECC_REGION_WASTE_LOCK,Locks the remaining waste parts of the ECC region (hole) that are not locked by ecc_region_parity_lock. - 1 - Locked; if this region is accessed error response is generated - 0 - Unlocked; this region can be accessed normally.." "Unlocked; this region can be accessed normally,Locked; if this region is accessed" newline bitfld.long 0x4 4. "ECC_REGION_PARITY_LOCK,Locks the parity section of the ECC region (hole) which is the highest system address part of the memory that stores ECC parity for protected region. - 1 - Locked; if this region is accessed error response is generated - 0 -.." "Unlocked; this region can be accessed normally,Locked; if this region is accessed" newline rbitfld.long 0x4 2.--3. "RESERVED,Reserved" "0,1,2,3" newline bitfld.long 0x4 1. "DATA_POISON_BIT,Selects whether to poison 1 or 2 bits. - if 0 -> 2-bit (uncorrectable) data poisoning - if 1 -> 1-bit (correctable) data poisoning if ECCCFG1.data_poison_en=1 Valid only when MEMC_ECC_SUPPORT==1 (SECDED ECC mode) Programming Mode:.." "?,bit" newline bitfld.long 0x4 0. "DATA_POISON_EN,Enables ECC data poisoning - introduces ECC errors on writes to address specified by the ECCPOISONADDR0/1 registers. This field must be set to 0 if ECC is disabled (ECCCFG0.ecc_mode = 0). Programming Mode: Quasi-dynamic Group 3" "0,1" rgroup.long 0x78++0x3 line.long 0x0 "ECCSTAT,SECDED ECC Status Register (Valid only in MEMC_ECC_SUPPORT==1 (SECDED ECC mode))" hexmask.long.word 0x0 17.--31. 1. "RESERVED,Reserved" newline bitfld.long 0x0 16. "ECC_UNCORRECTED_ERR,Double-bit error indicator. In sideband ECC mode 1 bit per ECC lane. When the controller is operating in 1:1 frequency ratio mode there are only two lanes so only the lower two bits are used. In inline ECC mode the register is.." "0,1" newline hexmask.long.byte 0x0 9.--15. 1. "RESERVED,Reserved" newline bitfld.long 0x0 8. "ECC_CORRECTED_ERR,Single-bit error indicator. In sideband ECC mode 1 bit per ECC lane. When the controller is operating in 1:1 frequency ratio mode there are only two lanes so only the lower two bits are used. In inline ECC mode the register is.." "0,1" newline bitfld.long 0x0 7. "RESERVED,Reserved" "0,1" newline hexmask.long.byte 0x0 0.--6. 1. "ECC_CORRECTED_BIT_NUM,Indicates the bit number corrected by single-bit ECC error. For encoding of this field see ECC section in the Architecture chapter. If more than one data lane has an error the lower data lane is selected. This register is 7 bits.." group.long 0x7C++0x3 line.long 0x0 "ECCCTL,ECC Clear Register" hexmask.long.word 0x0 19.--31. 1. "RESERVED,Reserved" newline bitfld.long 0x0 18. "ECC_AP_ERR_INTR_FORCE,Interrupt force bit for ecc_ap_err_intr. Setting this register causes the output interrupt to be asserted. The uMCTL2 automatically clears this bit. There is no interaction between functionally triggering an interrupt and forcing an.." "0,1" newline bitfld.long 0x0 17. "ECC_UNCORRECTED_ERR_INTR_FORCE,Interrupt force bit for ecc_uncorrected_err_intr. Setting this register causes the output interrupt to be asserted. The uMCTL2 automatically clears this bit. There is no interaction between functionally triggering an.." "0,1" newline bitfld.long 0x0 16. "ECC_CORRECTED_ERR_INTR_FORCE,Interrupt force bit for ecc_corrected_err_intr. Setting this register causes the output interrupt to be asserted. The uMCTL2 automatically clears this bit. There is no interaction between functionally triggering an interrupt.." "0,1" newline hexmask.long.byte 0x0 11.--15. 1. "RESERVED,Reserved" newline bitfld.long 0x0 10. "ECC_AP_ERR_INTR_EN,Interrupt enable bit for ecc_ap_err_intr. - 1 - Enabled - 0 - Disabled Programming Mode: Dynamic" "Disabled,Enabled" newline bitfld.long 0x0 9. "ECC_UNCORRECTED_ERR_INTR_EN,Interrupt enable bit for ecc_uncorrected_err_intr. - 1 - Enabled - 0 - Disabled Programming Mode: Dynamic" "Disabled,Enabled" newline bitfld.long 0x0 8. "ECC_CORRECTED_ERR_INTR_EN,Interrupt enable bit for ecc_corrected_err_intr. - 1 - Enabled - 0 - Disabled Programming Mode: Dynamic" "Disabled,Enabled" newline rbitfld.long 0x0 5.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 4. "ECC_AP_ERR_INTR_CLR,Interrupt clear bit for ecc_ap_err. If this bit is set the ECCAPSTAT.ecc_ap_err/ecc_ap_err_intr is cleared. The uMCTL2 automatically clears this bit. Programming Mode: Dynamic" "0,1" newline bitfld.long 0x0 3. "ECC_UNCORR_ERR_CNT_CLR,Setting this register bit to 1 clears the currently stored uncorrected ECC error count. The ECCERRCNT.ecc_uncorr_err_cnt register is cleared by this operation. The uMCTL2 automatically clears this bit. Programming Mode: Dynamic" "0,1" newline bitfld.long 0x0 2. "ECC_CORR_ERR_CNT_CLR,Setting this register bit to 1 clears the currently stored corrected ECC error count. The ECCERRCNT.ecc_corr_err_cnt register is cleared by this operation. The uMCTL2 automatically clears this bit. Programming Mode: Dynamic" "0,1" newline bitfld.long 0x0 1. "ECC_UNCORRECTED_ERR_CLR,Setting this register bit to 1 clears the currently stored uncorrected ECC error. The following registers are cleared: - ECCSTAT.ecc_uncorrected_err - ADVECCSTAT.advecc_uncorrected_err - ECCUSYN0 - ECCUSYN1 - ECCUSYN2 uMCTL2.." "ECCUSYN1,?" newline bitfld.long 0x0 0. "ECC_CORRECTED_ERR_CLR,Setting this register bit to 1 clears the currently stored corrected ECC error. The following registers are cleared: - ECCSTAT.ecc_corrected_err - ADVECCSTAT.advecc_corrected_err - ADVECCSTAT.advecc_num_err_symbol -.." "ECCCSYN1,ECCBITMASK2" rgroup.long 0x80++0xB line.long 0x0 "ECCERRCNT,ECC Error Counter Register" hexmask.long.word 0x0 16.--31. 1. "ECC_UNCORR_ERR_CNT,Indicates the number of uncorrectable ECC errors detected. Note that the saturation behavior of this register is different depending on the type of ECC. For advanced ECC or Inline ECC it saturates at 0xFFFF while for Side-band ECC.." newline hexmask.long.word 0x0 0.--15. 1. "ECC_CORR_ERR_CNT,Indicates the number of correctable ECC errors detected. Note that the saturation behavior of this register is different depending on the type of ECC. For advanced ECC or Inline ECC it saturates at 0xFFFF while for Side-band ECC with.." line.long 0x4 "ECCCADDR0,ECC Corrected Error Address Register 0" hexmask.long.byte 0x4 25.--31. 1. "RESERVED,Reserved" newline bitfld.long 0x4 24. "ECC_CORR_RANK,Indicates the rank number of a read resulting in a corrected ECC error. Programming Mode: Dynamic" "0,1" newline hexmask.long.byte 0x4 18.--23. 1. "RESERVED,Reserved" newline hexmask.long.tbyte 0x4 0.--17. 1. "ECC_CORR_ROW,Indicates the page/row number of a read resulting in a corrected ECC error. This is 18-bits wide in configurations with DDR4 support and 16-bits in all other configurations. Programming Mode: Dynamic" line.long 0x8 "ECCCADDR1,ECC Corrected Error Address Register 1" hexmask.long.byte 0x8 26.--31. 1. "RESERVED,Reserved" newline bitfld.long 0x8 24.--25. "ECC_CORR_BG,Indicates the bank group number of a read resulting in a corrected ECC error. Programming Mode: Dynamic" "0,1,2,3" newline hexmask.long.byte 0x8 19.--23. 1. "RESERVED,Reserved" newline bitfld.long 0x8 16.--18. "ECC_CORR_BANK,Indicates the bank number of a read resulting in a corrected ECC error. Programming Mode: Dynamic" "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x8 12.--15. 1. "RESERVED,Reserved" newline hexmask.long.word 0x8 0.--11. 1. "ECC_CORR_COL,Indicates the block number of a read resulting in a corrected ECC error (lowest bit not assigned here). Programming Mode: Dynamic" repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) rgroup.long ($2+0x8C)++0x3 line.long 0x0 "ECCCSYN$1,ECC Corrected Syndrome Register 0" hexmask.long 0x0 0.--31. 1. "ECC_CORR_SYNDROMES_31_0,Indicates the data pattern that resulted in a corrected error. For 16-bit ECC only bits [15:0] are used. Programming Mode: Dynamic" repeat.end rgroup.long 0x94++0x3 line.long 0x0 "ECCCSYN2,ECC Corrected Syndrome Register 2" hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED,Reserved" newline hexmask.long.byte 0x0 0.--7. 1. "ECC_CORR_SYNDROMES_71_64,Indicates the data pattern that resulted in a corrected error one for each ECC lane all concatenated together. This register refers to the ECC byte which is bits [71:64] for 64-bit ECC [39:32] for 32-bit ECC or [23:16] for.." repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) rgroup.long ($2+0x98)++0x3 line.long 0x0 "ECCBITMASK$1,ECC Corrected Data Bit Mask Register 0" hexmask.long 0x0 0.--31. 1. "ECC_CORR_BIT_MASK_31_0,Indicates the mask for the corrected data portion. - 1 on any bit indicates that the bit has been corrected by the ECC logic - 0 on any bit indicates that the bit has not been corrected by the ECC logic This register accumulates.." repeat.end rgroup.long 0xA0++0xB line.long 0x0 "ECCBITMASK2,ECC Corrected Data Bit Mask Register 2" hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED,Reserved" newline hexmask.long.byte 0x0 0.--7. 1. "ECC_CORR_BIT_MASK_71_64,Indicates the mask for the corrected data portion. - 1 on any bit indicates that the bit has been corrected by the ECC logic - 0 on any bit indicates that the bit has not been corrected by the ECC logic This register accumulates.." line.long 0x4 "ECCUADDR0,ECC Uncorrected Error Address Register 0" hexmask.long.byte 0x4 25.--31. 1. "RESERVED,Reserved" newline bitfld.long 0x4 24. "ECC_UNCORR_RANK,Indicates the rank number of a read resulting in an uncorrected ECC error. Programming Mode: Dynamic" "0,1" newline hexmask.long.byte 0x4 18.--23. 1. "RESERVED,Reserved" newline hexmask.long.tbyte 0x4 0.--17. 1. "ECC_UNCORR_ROW,Indicates the page/row number of a read resulting in an uncorrected ECC error. This is 18-bits wide in configurations with DDR4 support and 16-bits in all other configurations. Programming Mode: Dynamic" line.long 0x8 "ECCUADDR1,ECC Uncorrected Error Address Register 1" hexmask.long.byte 0x8 26.--31. 1. "RESERVED,Reserved" newline bitfld.long 0x8 24.--25. "ECC_UNCORR_BG,Indicates the bank group number of a read resulting in an uncorrected ECC error. Programming Mode: Dynamic" "0,1,2,3" newline hexmask.long.byte 0x8 19.--23. 1. "RESERVED,Reserved" newline bitfld.long 0x8 16.--18. "ECC_UNCORR_BANK,Indicates the bank number of a read resulting in an uncorrected ECC error. Programming Mode: Dynamic" "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x8 12.--15. 1. "RESERVED,Reserved" newline hexmask.long.word 0x8 0.--11. 1. "ECC_UNCORR_COL,Indicates the block number of a read resulting in an uncorrected ECC error (lowest bit not assigned here). Programming Mode: Dynamic" repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) rgroup.long ($2+0xAC)++0x3 line.long 0x0 "ECCUSYN$1,ECC Uncorrected Syndrome Register 0" hexmask.long 0x0 0.--31. 1. "ECC_UNCORR_SYNDROMES_31_0,Indicates the data pattern that resulted in an uncorrected error one for each ECC lane all concatenated together. For 16-bit ECC only bits [15:0] are used. Programming Mode: Dynamic" repeat.end rgroup.long 0xB4++0x3 line.long 0x0 "ECCUSYN2,ECC Uncorrected Syndrome Register 2" hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED,Reserved" newline hexmask.long.byte 0x0 0.--7. 1. "ECC_UNCORR_SYNDROMES_71_64,Indicates the data pattern that resulted in an uncorrected error one for each ECC lane all concatenated together. This register refers to the ECC byte which is bits [71:64] for 64-bit ECC [39:32] for 32-bit ECC or [23:16].." group.long 0xB8++0xF line.long 0x0 "ECCPOISONADDR0,ECC Data Poisoning Address Register 0. If a HIF write data beat matches the address specified in this register. an ECC error is introduced on that transaction (write/RMW). if ECCCFG1.data_poison_en=1." hexmask.long.byte 0x0 25.--31. 1. "RESERVED,Reserved" newline bitfld.long 0x0 24. "ECC_POISON_RANK,Indicates the rank address for ECC poisoning. Programming Mode: Static" "0,1" newline hexmask.long.word 0x0 12.--23. 1. "RESERVED,Reserved" newline hexmask.long.word 0x0 0.--11. 1. "ECC_POISON_COL,Indicates the column address for ECC poisoning. Note that this column address must be burst aligned: - In full bus width mode ecc_poison_col[2:0] must be set to 0 - In half bus width mode ecc_poison_col[3:0] must be set to 0 - In quarter.." line.long 0x4 "ECCPOISONADDR1,ECC Data Poisoning Address Register 1. If a HIF write data beat matches the address specified in this register. an ECC error is introduced on that transaction (write/RMW). if ECCCFG1.data_poison_en=1." rbitfld.long 0x4 30.--31. "RESERVED,Reserved" "0,1,2,3" newline bitfld.long 0x4 28.--29. "ECC_POISON_BG,Bank Group address for ECC poisoning. Programming Mode: Static" "0,1,2,3" newline rbitfld.long 0x4 27. "RESERVED,Reserved" "0,1" newline bitfld.long 0x4 24.--26. "ECC_POISON_BANK,Bank address for ECC poisoning. Programming Mode: Static" "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x4 18.--23. 1. "RESERVED,Reserved" newline hexmask.long.tbyte 0x4 0.--17. 1. "ECC_POISON_ROW,Row address for ECC poisoning. This is 18-bits wide in configurations with DDR4 support and 16-bits in all other configurations. Programming Mode: Static" line.long 0x8 "CRCPARCTL0,CRC Parity Control Register0. Note: Do not perform any APB access to CRCPARCTL0 within 32 pclk cycles of previous access to CRCPARCTL0. as this might lead to data loss." hexmask.long 0x8 3.--31. 1. "RESERVED,Reserved" newline bitfld.long 0x8 2. "DFI_ALERT_ERR_CNT_CLR,Indicates the clear bit for DFI alert error counter. Asserting this bit clears the DFI alert error counter CRCPARSTAT.dfi_alert_err_cnt. uMCTL2 automatically clears this bit. Programming Mode: Dynamic" "0,1" newline bitfld.long 0x8 1. "DFI_ALERT_ERR_INT_CLR,Interrupt clear bit for DFI alert error. If this bit is set the alert error interrupt on CRCPARSTAT.dfi_alert_err_int is cleared. uMCTL2 automatically clears this bit. Programming Mode: Dynamic" "0,1" newline bitfld.long 0x8 0. "DFI_ALERT_ERR_INT_EN,Interrupt enable bit for DFI alert error. If this bit is set any parity/CRC error detected on the dfi_alert_n input results in an interrupt being set on CRCPARSTAT.dfi_alert_err_int. Programming Mode: Dynamic" "0,1" line.long 0xC "CRCPARCTL1,CRC Parity Control Register1" hexmask.long.tbyte 0xC 13.--31. 1. "RESERVED,Reserved" newline bitfld.long 0xC 12. "CAPARITY_DISABLE_BEFORE_SR,If DDR4-SDRAM's CA parity is enabled by INIT6.mr5[2:0]!=0 and this register is set to 1 CA parity is automatically disabled before self-refresh entry and enabled after self-refresh exit by issuing MR5. - 1 - CA parity is.." "CA parity is not disabled before self-refresh..,CA parity is disabled before self-refresh entry" newline hexmask.long.byte 0xC 8.--11. 1. "RESERVED,Reserved" newline bitfld.long 0xC 7. "CRC_INC_DM,CRC calculation setting register. - 1 - CRC includes DM signal - 0 - CRC not includes DM signal Present only in designs configured to support DDR4. Programming Mode: Static" "CRC not includes DM signal,CRC includes DM signal" newline rbitfld.long 0xC 5.--6. "RESERVED,Reserved" "0,1,2,3" newline bitfld.long 0xC 4. "CRC_ENABLE,CRC enable Register. - 1 - Enable generation of CRC - 0 - Disable generation of CRC The setting of this register should match the CRC mode register setting in the DRAM. Programming Mode: Quasi-dynamic Group 2" "Disable generation of CRC,Enable generation of CRC" newline rbitfld.long 0xC 1.--3. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline bitfld.long 0xC 0. "PARITY_ENABLE,C/A Parity enable register. - 1 - Enable generation of C/A parity and detection of C/A parity error - 0 - Disable generation of C/A parity and disable detection of C/A parity error If RCD's parity error detection or SDRAM's parity detection.." "Disable generation of C/A parity and disable..,Enable generation of C/A parity and detection of.." rgroup.long 0xCC++0x3 line.long 0x0 "CRCPARSTAT,CRC Parity Status Register" hexmask.long.word 0x0 17.--31. 1. "RESERVED,Reserved" newline bitfld.long 0x0 16. "DFI_ALERT_ERR_INT,DFI alert error interrupt. If a parity/CRC error is detected on dfi_alert_n and the interrupt is enabled by CRCPARCTL0.dfi_alert_err_int_en this interrupt bit is set. It remains set until cleared by CRCPARCTL0.dfi_alert_err_int_clr." "0,1" newline hexmask.long.word 0x0 0.--15. 1. "DFI_ALERT_ERR_CNT,DFI alert error count. If a parity/CRC error is detected on dfi_alert_n this counter be incremented. This is independent of the setting of CRCPARCTL0.dfi_alert_err_int_en. It saturates at 0xFFFF and can be cleared by asserting.." group.long 0xD0++0xB line.long 0x0 "INIT0,SDRAM Initialization Register 0" bitfld.long 0x0 30.--31. "SKIP_DRAM_INIT,If lower bit is enabled the SDRAM initialization routine is skipped. The upper bit decides what state the controller starts up in when reset is removed. - 00 - SDRAM Initialization routine is run after power-up - 01 - SDRAM Initialization.." "SDRAM Initialization routine is run after power-up,SDRAM Initialization routine is skipped after..,?,?" newline hexmask.long.byte 0x0 26.--29. 1. "RESERVED,Reserved" newline hexmask.long.word 0x0 16.--25. 1. "POST_CKE_X1024,Indicates the number of cycles to wait after driving CKE high to start the SDRAM initialization sequence. DDR2 typically requires a 400 ns delay requiring this value to be programmed to 2 at all clock speeds. LPDDR2/LPDDR3 typically.." newline hexmask.long.byte 0x0 12.--15. 1. "RESERVED,Reserved" newline hexmask.long.word 0x0 0.--11. 1. "PRE_CKE_X1024,Indicates the number of cycles to wait after reset before driving CKE high to start the SDRAM initialization sequence. DDR2 specifications typically require this to be programmed for a delay of >= 200 us. LPDDR2/LPDDR3: tINIT1 of 100 ns.." line.long 0x4 "INIT1,SDRAM Initialization Register 1" hexmask.long.byte 0x4 25.--31. 1. "RESERVED,Reserved" newline hexmask.long.word 0x4 16.--24. 1. "DRAM_RSTN_X1024,Indicates the number of cycles to assert SDRAM reset signal during init sequence. This is only present for designs supporting DDR3 DDR4 or LPDDR4 devices. For use with a Synopsys DDR PHY this must be set to a minimum of 1. When the.." newline hexmask.long.word 0x4 4.--15. 1. "RESERVED,Reserved" newline hexmask.long.byte 0x4 0.--3. 1. "PRE_OCD_X32,Indicates the wait period before driving the OCD complete command to SDRAM. There is no known specific requirement for this; it may be set to zero. Unit: Multiples of 32 DFI clock cycles. For more information on how to program this register.." line.long 0x8 "INIT2,SDRAM Initialization Register 2" hexmask.long.word 0x8 16.--31. 1. "RESERVED,Reserved" newline hexmask.long.byte 0x8 8.--15. 1. "IDLE_AFTER_RESET_X32,Indicates the idle time after the reset command tINIT4. Present only in designs configured to support LPDDR2. When the controller is operating in 1:2 frequency ratio mode program this to JEDEC spec value divided by 2 and round it.." newline hexmask.long.byte 0x8 4.--7. 1. "RESERVED,Reserved" newline hexmask.long.byte 0x8 0.--3. 1. "MIN_STABLE_CLOCK_X1,Indicates the time to wait after the first CKE high tINIT2. Present only in designs configured to support LPDDR2/LPDDR3. LPDDR2/LPDDR3 typically requires 5 x tCK delay. When the controller is operating in 1:2 frequency ratio mode.." repeat 4. (list 0x3 0x4 0x6 0x7 )(list 0x0 0x4 0xC 0x10 ) group.long ($2+0xDC)++0x3 line.long 0x0 "INIT$1,SDRAM Initialization Register 3" hexmask.long.word 0x0 16.--31. 1. "MR,DDR2:Indicates the value to write to MR register. Bit 8 is for DLL and the setting here is ignored. The uMCTL2 sets this bit appropriately. DDR3/DDR4: Value loaded into MR0 register. mDDR: Value to write to MR register. LPDDR2/LPDDR3/LPDDR4 - Value to.." newline hexmask.long.word 0x0 0.--15. 1. "EMR,DDR2: Indicates the value to write to EMR register. Bits 9:7 are for OCD and the setting in this register is ignored. The uMCTL2 sets those bits appropriately. DDR3/DDR4: Value to write to MR1 register Set bit 7 to 0. mDDR: Value to write to EMR.." repeat.end group.long 0xE4++0x3 line.long 0x0 "INIT5,SDRAM Initialization Register 5" hexmask.long.byte 0x0 24.--31. 1. "RESERVED,Reserved" newline hexmask.long.byte 0x0 16.--23. 1. "DEV_ZQINIT_X32,ZQ initial calibration tZQINIT. Present only in designs configured to support DDR3 or DDR4 or LPDDR2/LPDDR3. DDR3 typically requires 512 SDRAM clock cycles. DDR4 requires 1024 SDRAM clock cycles. LPDDR2/LPDDR3 requires 1 us. When the.." newline hexmask.long.byte 0x0 10.--15. 1. "RESERVED,Reserved" newline hexmask.long.word 0x0 0.--9. 1. "MAX_AUTO_INIT_X1024,Indicates the maximum duration of the auto initialization tINIT5. Present only in designs configured to support LPDDR2/LPDDR3. LPDDR2/LPDDR3 typically requires 10 us. Unit: Multiples of 1024 DFI clock cycles. For more information on.." group.long 0xF0++0x7 line.long 0x0 "DIMMCTL,DIMM Control Register" hexmask.long.tbyte 0x0 15.--31. 1. "RESERVED,Reserved" newline bitfld.long 0x0 14. "RCD_B_OUTPUT_DISABLED,Disables RCD outputs to B-side DRAMs. This field is used only when the uMCTL2 disables CAL mode. This value is written to F0RC0 DA[3] before and after disabling CAL mode. It is recommended to set it to ~DIMMCTL.dimm_output_inv_en.." "Enable B outputs,Disable B outputs" newline bitfld.long 0x0 13. "RCD_A_OUTPUT_DISABLED,Disables RCD outputs to A-side DRAMs. This field is used only when the uMCTL2 disables CAL mode. This value is written to F0RC0 DA[2] before and after disabling CAL mode. It is recommended to set it to 0 except for debug. - 1 -.." "Enable A outputs,Disable A outputs" newline bitfld.long 0x0 12. "RCD_WEAK_DRIVE,Indicates the weak drive mode to be set to the RCD. This field is used only when the uMCTL2 disables CAL mode. When weak drive mode in the RCD is enabled during initialization this field must be set to 1. When RCD is not used this field.." "Disable Weak Drive mode,Enable Weak Drive mode" newline hexmask.long.byte 0x0 7.--11. 1. "RESERVED,Reserved" newline bitfld.long 0x0 6. "LRDIMM_BCOM_CMD_PROT,Protects the timing restrictions (tBCW/tMRC) between consecutive BCOM commands defined in the Data Buffer specification. When using DDR4 LRDIMM this bit must be set to 1. Otherwise this bit must be set to 0. Programming Mode: Static" "0,1" newline bitfld.long 0x0 5. "DIMM_DIS_BG_MIRRORING,Disables address mirroring for BG bits. When this is set to 1 BG0 and BG1 are NOT swapped even if Address Mirroring is enabled. This is required for DDR4 DIMMs with x16 devices. - 1 - BG0 and BG1 are NOT swapped - 0 - BG0 and BG1.." "BG0 and BG1 are swapped if address mirroring is..,BG0 and BG1 are NOT swapped" newline bitfld.long 0x0 4. "MRS_BG1_EN,Enable this field for BG1 bit of MRS command. BG1 bit of the mode register address is specified as RFU (Reserved for Future Use) and must be programmed to 0 during MRS. In case where DRAMs that do not have BG1 are attached and both the CA.." "Disabled,Enabled" newline bitfld.long 0x0 3. "MRS_A17_EN,Enable this field for A17 bit of MRS command. A17 bit of the mode register address is specified as RFU (Reserved for Future Use) and must be programmed to 0 during MRS. In case where DRAMs that do not have A17 are attached as DDR4 RDIMM/LRDIMM.." "Disabled,Enabled" newline bitfld.long 0x0 2. "DIMM_OUTPUT_INV_EN,Enables output inversion (for DDR4 RDIMM/LRDIMM implementations only). DDR4 RDIMM/LRDIMM implements the Output Inversion feature by default which means that the following address bank address and bank group bits of B-side DRAMs are.." "Do not implement output inversion for B-side DRAMs,Implement output inversion for B-side DRAMs" newline bitfld.long 0x0 1. "DIMM_ADDR_MIRR_EN,Enables address mirroring (for multi-rank UDIMM implementations and multi-rank DDR4 RDIMM/LRDIMM implementations). Some UDIMMs and DDR4 RDIMMs/LRDIMMs implement address mirroring for odd ranks which means that the following address.." "Do not implement address mirroring,For odd ranks" newline bitfld.long 0x0 0. "DIMM_STAGGER_CS_EN,Staggering enable for multi-rank accesses (for multi-rank UDIMM RDIMM and LRDIMM implementations only). This is not supported for mDDR LPDDR2 LPDDR3 or LPDDR4 SDRAMs. Note: Even if this bit is set it does not take care of software.." "Do not stagger accesses,?" line.long 0x4 "RANKCTL,Rank Control Register" hexmask.long.byte 0x4 27.--31. 1. "RESERVED,Reserved" newline bitfld.long 0x4 26. "DIFF_RANK_WR_GAP_MSB,Only present for multi-rank configurations. 1-bit extension to be used when RANKCTL.diff_rank_wr_gap field needs to be set to a value greater than 0xF. Programming Mode: Quasi-dynamic Group 2" "?,bit extension to be used when RANKCTL" newline rbitfld.long 0x4 25. "RESERVED,Reserved" "0,1" newline bitfld.long 0x4 24. "DIFF_RANK_RD_GAP_MSB,Only present for multi-rank configurations. 1-bit extension to be used when RANKCTL.diff_rank_rd_gap field needs to be set to a value greater than 0xF. Programming Mode: Quasi-dynamic Group 2" "?,bit extension to be used when RANKCTL" newline hexmask.long.byte 0x4 16.--23. 1. "RESERVED,Reserved" newline hexmask.long.byte 0x4 12.--15. 1. "MAX_RANK_WR,Only present for multi-rank configurations. Background: Writes to the same rank can be performed back-to-back. Writes to different ranks require additional gap dictated by the register RANKCTL.diff_rank_wr_gap. This is to avoid possible data.." newline hexmask.long.byte 0x4 8.--11. 1. "DIFF_RANK_WR_GAP,Only present for multi-rank configurations. Indicates the number of clocks of gap in data responses when performing consecutive writes to different ranks. This is used to switch the delays in the PHY to match the rank requirements. This.." newline hexmask.long.byte 0x4 4.--7. 1. "DIFF_RANK_RD_GAP,Only present for multi-rank configurations. Indicates the number of clocks of gap in data responses when performing consecutive reads to different ranks. This is used to switch the delays in the PHY to match the rank requirements. This.." newline hexmask.long.byte 0x4 0.--3. 1. "MAX_RANK_RD,Only present for multi-rank configurations. Background: Reads to the same rank can be performed back-to-back. Reads to different ranks require additional gap dictated by the register RANKCTL.diff_rank_rd_gap. This is to avoid possible data.." group.long 0x100++0x3F line.long 0x0 "DRAMTMG0,SDRAM Timing Register 0" rbitfld.long 0x0 31. "RESERVED,Reserved" "0,1" newline hexmask.long.byte 0x0 24.--30. 1. "WR2PRE,Specifies the minimum time between write and precharge to same bank. Specifications: WL + BL/2 + tWR = approximately 8 cycles + 15 ns = 14 clocks @400MHz and less for lower frequencies. where: - WL - Write latency - BL - Burst length. This must.." newline rbitfld.long 0x0 22.--23. "RESERVED,Reserved" "0,1,2,3" newline hexmask.long.byte 0x0 16.--21. 1. "T_FAW,tFAW - valid only when 8 or more banks(or banks x bank groups) are present. In 8-bank design at most 4 banks must be activated in a rolling window of tFAW cycles. When the controller is operating in 1:2 frequency ratio mode program this to.." newline rbitfld.long 0x0 15. "RESERVED,Reserved" "0,1" newline hexmask.long.byte 0x0 8.--14. 1. "T_RAS_MAX,tRAS(max) - Specifies the maximum time between activate and precharge to same bank. This is the maximum time that a page can be kept open Minimum value of this register is 1. Zero is invalid. When the controller is operating in 1:1 frequency.." newline rbitfld.long 0x0 6.--7. "RESERVED,Reserved" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "T_RAS_MIN,tRAS(min) - Specifies the minimum time between activate and precharge to the same bank. When the controller is operating in 1:2 frequency mode 1T mode program this to tRAS(min)/2. No rounding up. When the controller is operating in 1:2.." line.long 0x4 "DRAMTMG1,SDRAM Timing Register 1" hexmask.long.word 0x4 21.--31. 1. "RESERVED,Reserved" newline hexmask.long.byte 0x4 16.--20. 1. "T_XP,tXP - Specifies the minimum time after power-down exit to any operation. For DDR3 this must be programmed to tXPDLL if slow powerdown exit is selected in MR0[12]. If C/A parity for DDR4 is used set to (tXP+PL) instead. If LPDDR4 is selected and.." newline rbitfld.long 0x4 14.--15. "RESERVED,Reserved" "0,1,2,3" newline hexmask.long.byte 0x4 8.--13. 1. "RD2PRE,tRTP - Specifies the minimum time from read to precharge of same bank. - DDR2 - tAL + BL/2 + max(tRTP 2) - 2 - DDR3 - tAL + max (tRTP 4) - DDR4 - Max of following two equations: tAL + max (tRTP 4) or RL + BL/2 - tRP (*). - mDDR - BL/2 - LPDDR2.." newline rbitfld.long 0x4 7. "RESERVED,Reserved" "0,1" newline hexmask.long.byte 0x4 0.--6. 1. "T_RC,tRC - Specifies the minimum time between activates to same bank. When the controller is operating in 1:2 frequency ratio mode program this to (tRC/2) and round up to next integer value. Unit: DFI clock cycles. Programming Mode: Quasi-dynamic Group.." line.long 0x8 "DRAMTMG2,SDRAM Timing Register 2" rbitfld.long 0x8 30.--31. "RESERVED,Reserved" "0,1,2,3" newline hexmask.long.byte 0x8 24.--29. 1. "WRITE_LATENCY,Set this field to WL. Indicates the Time from write command to write data on SDRAM interface. This must be set to WL. For mDDR it must be set to 1. Note that depending on the PHY if using RDIMM/LRDIMM it might be necessary to adjust the.." newline rbitfld.long 0x8 22.--23. "RESERVED,Reserved" "0,1,2,3" newline hexmask.long.byte 0x8 16.--21. 1. "READ_LATENCY,Set this field to RL. Indicates the time from read command to read data on SDRAM interface. This must be set to RL. Note that depending on the PHY if using RDIMM/LRDIMM it might be necessary to adjust the value of RL to compensate for the.." newline rbitfld.long 0x8 14.--15. "RESERVED,Reserved" "0,1,2,3" newline hexmask.long.byte 0x8 8.--13. 1. "RD2WR,DDR2/3/mDDR: RL + BL/2 + 2 - WL DDR4: RL + BL/2 + 1 + WR_PREAMBLE - WL LPDDR2/LPDDR3: RL + BL/2 + RU(tDQSCKmax/tCK) + 1 - WL LPDDR4(DQ ODT is Disabled): RL + BL/2 + RU(tDQSCKmax/tCK) + WR_PREAMBLE + RD_POSTAMBLE - WL LPDDR4(DQ ODT is Enabled): RL +.." newline rbitfld.long 0x8 6.--7. "RESERVED,Reserved" "0,1,2,3" newline hexmask.long.byte 0x8 0.--5. 1. "WR2RD,DDR4: CWL + PL + BL/2 + tWTR_L LPDDR2/3/4: WL + BL/2 + tWTR + 1 Others: CWL + BL/2 + tWTR In DDR4 minimum time from write command to read command for same bank group. In others minimum time from write command to read command. Includes time for.." line.long 0xC "DRAMTMG3,SDRAM Timing Register 3" rbitfld.long 0xC 30.--31. "RESERVED,Reserved" "0,1,2,3" newline hexmask.long.word 0xC 20.--29. 1. "T_MRW,Indicates the time to wait after a mode register write or read (MRW or MRR). Present only in designs configured to support LPDDR2 LPDDR3 or LPDDR4. LPDDR2 typically requires value of 5. LPDDR3 typically requires value of 10. LPDDR4: Set this to.." newline rbitfld.long 0xC 18.--19. "RESERVED,Reserved" "0,1,2,3" newline hexmask.long.byte 0xC 12.--17. 1. "T_MRD,tMRD- Indicates the number of cycles to wait after a mode register write or read. Depending on the connected SDRAM tMRD represents: - DDR2/mDDR: Time from MRS to any command - DDR3/4: Time from MRS to MRS command - LPDDR2: not used - LPDDR3/4:.." newline rbitfld.long 0xC 10.--11. "RESERVED,Reserved" "0,1,2,3" newline hexmask.long.word 0xC 0.--9. 1. "T_MOD,tMOD - Parameter used only in DDR3 and DDR4. Indicates the number of cycles between load mode command and following non-load mode command. If C/A parity for DDR4 is used set to tMOD_PAR(tMOD+PL) instead. If CAL mode is enabled.." line.long 0x10 "DRAMTMG4,SDRAM Timing Register 4" rbitfld.long 0x10 29.--31. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x10 24.--28. 1. "T_RCD,tRCD - tAL: Indicates the minimum time from activate to read or write command to same bank. When the controller is operating in 1:2 frequency ratio mode program this to ((tRCD - tAL)/2) and round it up to the next integer value. Minimum value.." newline hexmask.long.byte 0x10 20.--23. 1. "RESERVED,Reserved" newline hexmask.long.byte 0x10 16.--19. 1. "T_CCD,DDR4: tCCD_L: This is the minimum time between two reads or two writes for same bank group. Others: tCCD: This is the minimum time between two reads or two writes. When the controller is operating in 1:2 frequency ratio mode program this to.." newline hexmask.long.byte 0x10 12.--15. 1. "RESERVED,Reserved" newline hexmask.long.byte 0x10 8.--11. 1. "T_RRD,DDR4: tRRD_L: This is the minimum time between activates from bank 'a' to bank 'b' for same bank group. Others: tRRD: Minimum time between activates from bank 'a' to bank 'b' When the controller is operating in 1:2 frequency ratio mode program.." newline rbitfld.long 0x10 5.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x10 0.--4. 1. "T_RP,tRP: Indicates the minimum time from single-bank precharge to activate of same bank. When the controller is operating in 1:1 frequency ratio mode t_rp must be set to RoundUp(tRP/tCK). When the controller is operating in 1:2 frequency ratio mode.." line.long 0x14 "DRAMTMG5,SDRAM Timing Register 5" hexmask.long.byte 0x14 28.--31. 1. "RESERVED,Reserved" newline hexmask.long.byte 0x14 24.--27. 1. "T_CKSRX,This is the time before self-refresh Exit that CK is maintained as a valid clock before issuing SRX. Specifies the clock stable time before SRX. Recommended settings: - mDDR - 1 - LPDDR2 - 2 - LPDDR3 - 2 - LPDDR4 - tCKCKEH - DDR2 - 1 - DDR3 -.." newline hexmask.long.byte 0x14 20.--23. 1. "RESERVED,Reserved" newline hexmask.long.byte 0x14 16.--19. 1. "T_CKSRE,This is the time after self-refresh Down Entry that CK is maintained as a valid clock. Specifies the clock disable delay after SRE. Recommended settings: - mDDR - 0 - LPDDR2 - 2 - LPDDR3 - 2 - LPDDR4 - tCKELCK - DDR2 - 1 - DDR3 - Max (10 ns 5.." newline rbitfld.long 0x14 14.--15. "RESERVED,Reserved" "0,1,2,3" newline hexmask.long.byte 0x14 8.--13. 1. "T_CKESR,Indicates the minimum CKE low width for self-refresh or self-refresh power down entry to exit timing in memory clock cycles. Recommended settings: - mDDR - tRFC - LPDDR2 - tCKESR - LPDDR3 - tCKESR - LPDDR4 - max(tCKE tSR) - DDR2 - tCKE - DDR3 -.." newline rbitfld.long 0x14 5.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x14 0.--4. 1. "T_CKE,Indicates the minimum number of cycles of CKE HIGH/LOW during power-down and self-refresh. - LPDDR2/LPDDR3 mode - Set this to the larger of tCKE or tCKESR - LPDDR4 mode - Set this to the larger of tCKE or tSR - Non-LPDDR2/non-LPDDR3/non-LPDDR4.." line.long 0x18 "DRAMTMG6,SDRAM Timing Register 6" hexmask.long.byte 0x18 28.--31. 1. "RESERVED,Reserved" newline hexmask.long.byte 0x18 24.--27. 1. "T_CKDPDE,This is the time after Deep Power Down Entry that CK is maintained as a valid clock. Specifies the clock disable delay after DPDE. Recommended settings: - mDDR: 0 - LPDDR2: 2 - LPDDR3: 2 When the controller is operating in 1:2 frequency ratio.." newline hexmask.long.byte 0x18 20.--23. 1. "RESERVED,Reserved" newline hexmask.long.byte 0x18 16.--19. 1. "T_CKDPDX,This is the time before Deep Power Down Exit that CK is maintained as a valid clock before issuing DPDX. Specifies the clock stable time before DPDX. Recommended settings: - mDDR - 1 - LPDDR2 - 2 - LPDDR3 - 2 When the controller is operating in.." newline hexmask.long.word 0x18 4.--15. 1. "RESERVED,Reserved" newline hexmask.long.byte 0x18 0.--3. 1. "T_CKCSX,This is the time before Clock Stop Exit that CK is maintained as a valid clock before issuing Clock Stop Exit. Specifies the clock stable time before next command after Clock Stop Exit. Recommended settings: - mDDR - 1 - LPDDR2 - tXP + 2 - LPDDR3.." line.long 0x1C "DRAMTMG7,SDRAM Timing Register 7" hexmask.long.tbyte 0x1C 12.--31. 1. "RESERVED,Reserved" newline hexmask.long.byte 0x1C 8.--11. 1. "T_CKPDE,This is the time after Power Down Entry that CK is maintained as a valid clock. Specifies the clock disable delay after PDE. Recommended settings: - mDDR - 0 - LPDDR2 - 2 - LPDDR3 - 2 - LPDDR4 - tCKELCK When using DDR2/3/4 SDRAM this register.." newline hexmask.long.byte 0x1C 4.--7. 1. "RESERVED,Reserved" newline hexmask.long.byte 0x1C 0.--3. 1. "T_CKPDX,This is the time before Power Down Exit that CK is maintained as a valid clock before issuing PDX. Specifies the clock stable time before PDX. Recommended settings: - mDDR - 0 - LPDDR2 - 2 - LPDDR3 - 2 - LPDDR4 - tCKCKEH When using DDR2/3/4 SDRAM.." line.long 0x20 "DRAMTMG8,SDRAM Timing Register 8" rbitfld.long 0x20 31. "RESERVED,Reserved" "0,1" newline hexmask.long.byte 0x20 24.--30. 1. "T_XS_FAST_X32,tXS_FAST: Exit self-refresh to ZQCL ZQCS and MRS (only CL WR RTP and Geardown mode). When the controller is operating in 1:2 frequency ratio mode program this to the previous value divided by 2 and round up to next integer value. Note:.." newline rbitfld.long 0x20 23. "RESERVED,Reserved" "0,1" newline hexmask.long.byte 0x20 16.--22. 1. "T_XS_ABORT_X32,tXS_ABORT: Exit self-refresh to commands not requiring a locked DLL in self-refresh Abort. When the controller is operating in 1:2 frequency ratio mode program this to the previous value divided by 2 and round up to next integer value." newline rbitfld.long 0x20 15. "RESERVED,Reserved" "0,1" newline hexmask.long.byte 0x20 8.--14. 1. "T_XS_DLL_X32,tXSDLL: Exit self-refresh to commands requiring a locked DLL. When the controller is operating in 1:2 frequency ratio mode program this to the previous value divided by 2 and round up to next integer value. Note: Used only for DDR2 DDR3.." newline rbitfld.long 0x20 7. "RESERVED,Reserved" "0,1" newline hexmask.long.byte 0x20 0.--6. 1. "T_XS_X32,tXS: Exit self-refresh to commands not requiring a locked DLL. When the controller is operating in 1:2 frequency ratio mode program this to the previous value divided by 2 and round up to next integer value. Note: Used only for DDR2 DDR3 and.." line.long 0x24 "DRAMTMG9,SDRAM Timing Register 9" rbitfld.long 0x24 31. "RESERVED,Reserved" "0,1" newline bitfld.long 0x24 30. "DDR4_WR_PREAMBLE,DDR4 Write preamble mode. - 0 - 1tCK preamble - 1 - 2tCK preamble Present only with MEMC_FREQ_RATIO=2. Programming Mode: Quasi-dynamic Group 2 Group 4" "0,1" newline hexmask.long.word 0x24 19.--29. 1. "RESERVED,Reserved" newline bitfld.long 0x24 16.--18. "T_CCD_S,tCCD_S: This is the minimum time between two reads or two writes for different bank group. For bank switching (from bank 'a' to bank 'b') the minimum time is this value + 1. When the controller is operating in 1:2 frequency ratio mode program.." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x24 12.--15. 1. "RESERVED,Reserved" newline hexmask.long.byte 0x24 8.--11. 1. "T_RRD_S,tRRD_S: This is the minimum time between activates from bank 'a' to bank 'b' for different bank group. When the controller is operating in 1:2 frequency ratio mode program this to (tRRD_S/2) and round it up to the next integer value. Present.." newline rbitfld.long 0x24 6.--7. "RESERVED,Reserved" "0,1,2,3" newline hexmask.long.byte 0x24 0.--5. 1. "WR2RD_S,CWL + PL + BL/2 + tWTR_S Minimum time from write command to read command for different bank group. Includes time for bus turnaround recovery times and all per-bank per-rank and global constraints. Present only in designs configured to support.." line.long 0x28 "DRAMTMG10,SDRAM Timing Register 10" hexmask.long.word 0x28 21.--31. 1. "RESERVED,Reserved" newline hexmask.long.byte 0x28 16.--20. 1. "T_SYNC_GEAR,Indicates the time between MRS command and the sync pulse time. This must be even number of clocks. For DDR4-2666 and DDR4-3200 this parameter is defined as tMOD(min)+4nCK tMOD(min) is greater of 24nCK or 15ns 15ns / .625ns = 24 Max value.." newline rbitfld.long 0x28 13.--15. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x28 8.--12. 1. "T_CMD_GEAR,Indicates a sync pulse to first valid command. For DDR4-2666 and DDR4-3200 this parameter is defined as tMOD(min) tMOD(min) is greater of 24nCK or 15ns 15ns / .625ns = 24 Max value for this register is 24 When the controller is operating in.." newline hexmask.long.byte 0x28 4.--7. 1. "RESERVED,Reserved" newline bitfld.long 0x28 2.--3. "T_GEAR_SETUP,Indicates the geardown setup time. Minimum value of this register is 1. Zero is invalid. For DDR4-2666 and DDR4-3200 this parameter is defined as 2 clks When the controller is operating in 1:2 frequency ratio mode program this to.." "0,1,2,3" newline bitfld.long 0x28 0.--1. "T_GEAR_HOLD,Indicates the geardown hold time. Minimum value of this register is 1. Zero is invalid. For DDR4-2666 and DDR4-3200 this parameter is defined as 2 clks When the controller is operating in 1:2 frequency ratio mode program this to.." "0,1,2,3" line.long 0x2C "DRAMTMG11,SDRAM Timing Register 11" rbitfld.long 0x2C 31. "RESERVED,Reserved" "0,1" newline hexmask.long.byte 0x2C 24.--30. 1. "POST_MPSM_GAP_X32,tXMPDLL: This is the minimum Exit MPSM to commands requiring a locked DLL. When the controller is operating in 1:2 frequency ratio mode program this to (tXMPDLL/2) and round it up to the next integer value. Present only in designs.." newline rbitfld.long 0x2C 21.--23. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x2C 16.--20. 1. "T_MPX_LH,tMPX_LH: This is the minimum CS_n Low hold time to CKE rising edge. When the controller is operating in 1:2 frequency ratio mode program this to RoundUp(tMPX_LH/2)+1. Present only in designs configured to support DDR4. Unit: DFI clock cycles." newline hexmask.long.byte 0x2C 10.--15. 1. "RESERVED,Reserved" newline bitfld.long 0x2C 8.--9. "T_MPX_S,tMPX_S: This is the minimum time CS setup time to CKE. When the controller is operating in 1:2 frequency ratio mode program this to (tMPX_S/2) and round it up to the next integer value. Present only in designs configured to support DDR4. Unit:.." "0,1,2,3" newline rbitfld.long 0x2C 5.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x2C 0.--4. 1. "T_CKMPE,tCKMPE: This is the minimum valid clock requirement after MPSM entry. Present only in designs configured to support DDR4. When the controller is operating in 1:2 frequency ratio mode divide the value calculated using the previous equation by 2.." line.long 0x30 "DRAMTMG12,SDRAM Timing Register 12" rbitfld.long 0x30 30.--31. "RESERVED,Reserved" "0,1,2,3" newline hexmask.long.byte 0x30 24.--29. 1. "T_WR_MPR,This bit is used only in DDR4. Cycles between MPR Write and other command. Set this to tMOD + AL (or tMOD + PL + AL if C/A parity is also used). When the controller is operating in 1:2 frequency ratio mode program this to (tWR_MPR/2) and round.." newline hexmask.long.byte 0x30 18.--23. 1. "RESERVED,Reserved" newline bitfld.long 0x30 16.--17. "T_CMDCKE,tCMDCKE: Indicates the delay from valid command to CKE input LOW. Set this to the larger of tESCKE or tCMDCKE When the controller is operating in 1:2 frequency ratio mode program this to (max(tESCKE tCMDCKE)/2) and round it up to the next.." "0,1,2,3" newline hexmask.long.word 0x30 5.--15. 1. "RESERVED,Reserved" newline hexmask.long.byte 0x30 0.--4. 1. "T_MRD_PDA,tMRD_PDA: This is the Mode Register Set command cycle time in PDA mode. When the controller is operating in 1:2 frequency ratio mode program this to (tMRD_PDA/2) and round it up to the next integer value. Unit: DFI clock cycles. Programming.." line.long 0x34 "DRAMTMG13,SDRAM Timing Register 13" rbitfld.long 0x34 31. "RESERVED,Reserved" "0,1" newline hexmask.long.byte 0x34 24.--30. 1. "ODTLOFF,LPDDR4: ODTLoff: This is the latency from CAS-2 command to ODToff reference. When the controller is operating in 1:2 frequency ratio mode program this to (ODTLoff/2) and round it up to the next integer value. Unit: DFI clock cycles. Programming.." newline rbitfld.long 0x34 22.--23. "RESERVED,Reserved" "0,1,2,3" newline hexmask.long.byte 0x34 16.--21. 1. "T_CCD_MW,LPDDR4: tCCDMW: This is the minimum time from write or masked write to masked write command for same bank. When the controller is operating in 1:2 frequency ratio mode program this to (tCCDMW/2) and round it up to the next integer value. Unit:.." newline hexmask.long.word 0x34 3.--15. 1. "RESERVED,Reserved" newline bitfld.long 0x34 0.--2. "T_PPD,LPDDR4: tPPD: This is the minimum time from precharge to precharge command. When the controller is operating in 1:2 frequency ratio mode program this to (tPPD/2) and round it up to the next integer value. Unit: DFI clock cycles. Programming Mode:.." "?,?,?,?,tPPD: This is the minimum time from precharge to..,?,?,?" line.long 0x38 "DRAMTMG14,SDRAM Timing Register 14" hexmask.long.tbyte 0x38 12.--31. 1. "RESERVED,Reserved" newline hexmask.long.word 0x38 0.--11. 1. "T_XSR,tXSR: This is the exit self-refresh to any command. When the controller is operating in 1:2 frequency ratio mode program this to the previous value divided by 2 and round up to next integer value. The value 0xfff is illegal for this register.." line.long 0x3C "DRAMTMG15,SDRAM Timing Register 15" bitfld.long 0x3C 31. "EN_DFI_LP_T_STAB,- 1 - Enable using tSTAB when exiting DFI LP. This must be set when the PHY is stopping the clock during DFI LP to save maximum power. - 0 - Disable using tSTAB when exiting DFI LP. Programming Mode: Quasi-dynamic Group 2 Group 4" "Disable using tSTAB when exiting DFI LP,Enable using tSTAB when exiting DFI LP" newline hexmask.long.tbyte 0x3C 8.--30. 1. "RESERVED,Reserved" newline hexmask.long.byte 0x3C 0.--7. 1. "T_STAB_X32,tSTAB: Stabilization time. It is required in the following two cases for DDR3/DDR4 RDIMM: - When exiting power saving mode if the clock is stopped after re-enabling it the clock must be stable for a time specified by tSTAB - In the case of.." group.long 0x180++0xB line.long 0x0 "ZQCTL0,ZQ Control Register 0" bitfld.long 0x0 31. "DIS_AUTO_ZQ,- 1 - Disable uMCTL2 generation of ZQCS/MPC(ZQ calibration) command. Register DBGCMD.zq_calib_short can be used instead to issue ZQ calibration request from APB module - 0 - Internally generate ZQCS/MPC(ZQ calibration) commands based on.." "Internally generate ZQCS/MPC,Disable uMCTL2 generation of ZQCS/MPC" newline bitfld.long 0x0 30. "DIS_SRX_ZQCL,- 1 - Disable issuing of ZQCL/MPC(ZQ calibration) command at self-refresh/SR-Powerdown exit. Only applicable when run in DDR3 or DDR4 or LPDDR2 or LPDDR3 or LPDDR4 mode - 0 - Enable issuing of ZQCL/MPC(ZQ calibration) command at.." "Enable issuing of ZQCL/MPC,Disable issuing of ZQCL/MPC" newline bitfld.long 0x0 29. "ZQ_RESISTOR_SHARED,- 1 - Denotes that ZQ resistor is shared between ranks. Means ZQinit/ZQCL/ZQCS/MPC(ZQ calibration) commands are sent to one rank at a time with tZQinit/tZQCL/tZQCS/tZQCAL/tZQLAT timing met between commands so that commands to different.." "ZQ resistor is not shared,Denotes that ZQ resistor is shared between ranks" newline bitfld.long 0x0 28. "DIS_MPSMX_ZQCL,- 1 - Disable issuing of ZQCL command at Maximum Power Saving Mode exit. Only applicable when run in DDR4 mode - 0 - Enable issuing of ZQCL command at Maximum Power Saving Mode exit. Only applicable when run in DDR4 mode This is only.." "Enable issuing of ZQCL command at Maximum Power..,Disable issuing of ZQCL command at Maximum Power.." newline rbitfld.long 0x0 27. "RESERVED,Reserved" "0,1" newline hexmask.long.word 0x0 16.--26. 1. "T_ZQ_LONG_NOP,tZQoper for DDR3/DDR4 tZQCL for LPDDR2/LPDDR3 tZQCAL for LPDDR4: Number of DFI clock cycles of NOP required after a ZQCL (ZQ calibration long)/MPC(ZQ Start) command is issued to SDRAM. When the controller is operating in 1:2 frequency.." newline hexmask.long.byte 0x0 10.--15. 1. "RESERVED,Reserved" newline hexmask.long.word 0x0 0.--9. 1. "T_ZQ_SHORT_NOP,tZQCS for DDR3/DD4/LPDDR2/LPDDR3 tZQLAT for LPDDR4: Number of DFI clock cycles of NOP required after a ZQCS (ZQ calibration short)/MPC(ZQ Latch) command is issued to SDRAM. When the controller is operating in 1:2 frequency ratio mode.." line.long 0x4 "ZQCTL1,ZQ Control Register 1" rbitfld.long 0x4 30.--31. "RESERVED,Reserved" "0,1,2,3" newline hexmask.long.word 0x4 20.--29. 1. "T_ZQ_RESET_NOP,tZQReset: Number of DFI clock cycles of NOP required after a ZQReset (ZQ calibration Reset) command is issued to SDRAM. When the controller is operating in 1:2 frequency ratio mode program this to tZQReset/2 and round it up to the next.." newline hexmask.long.tbyte 0x4 0.--19. 1. "T_ZQ_SHORT_INTERVAL_X1024,Indicates the average interval to wait between automatically issuing ZQCS (ZQ calibration short)/MPC(ZQ calibration) commands to DDR3/DDR4/LPDDR2/LPDDR3/LPDDR4 devices. Meaningless if ZQCTL0.dis_auto_zq=1. This is only present.." line.long 0x8 "ZQCTL2,ZQ Control Register 2" hexmask.long 0x8 1.--31. 1. "RESERVED,Reserved" newline bitfld.long 0x8 0. "ZQ_RESET,Setting this register bit to 1 triggers a ZQ Reset operation. When the ZQ Reset operation is complete the uMCTL2 automatically clears this bit. It is recommended NOT to set this register bit if in Init in self-refresh(except LPDDR4) or.." "0,1" rgroup.long 0x18C++0x3 line.long 0x0 "ZQSTAT,ZQ Status Register" hexmask.long 0x0 1.--31. 1. "RESERVED,Reserved" newline bitfld.long 0x0 0. "ZQ_RESET_BUSY,SoC might initiate a ZQ Reset operation only if this signal is low. This signal goes high in the clock after the uMCTL2 accepts the ZQ Reset request. It goes low when the ZQ Reset command is issued to the SDRAM and the associated NOP period.." "Indicates that the SoC can initiate a ZQ Reset..,Indicates that ZQ Reset operation is in progress" group.long 0x190++0x1B line.long 0x0 "DFITMG0,DFI Timing Register 0" rbitfld.long 0x0 29.--31. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x0 24.--28. 1. "DFI_T_CTRL_DELAY,Specifies the number of DFI clock cycles after an assertion or de-assertion of the DFI control signals that the control signals at the PHY-DRAM interface reflect the assertion or de-assertion. If the DFI clock and the memory clock are.." newline bitfld.long 0x0 23. "DFI_RDDATA_USE_DFI_PHY_CLK,Defines whether dfi_rddata_en/dfi_rddata/dfi_rddata_valid is generated using HDR (DFI clock) or SDR (DFI PHY clock) values. Selects whether value in DFITMG0.dfi_t_rddata_en is in terms of HDR (DFI clock) or SDR (DFI PHY clock).." "Else,?" newline hexmask.long.byte 0x0 16.--22. 1. "DFI_T_RDDATA_EN,Time from the assertion of a read command on the DFI interface to the assertion of the dfi_rddata_en signal. Refer to PHY specification for correct value. This corresponds to the DFI parameter trddata_en. Note that depending on the PHY.." newline bitfld.long 0x0 15. "DFI_WRDATA_USE_DFI_PHY_CLK,Defines whether dfi_wrdata_en/dfi_wrdata/dfi_wrdata_mask is generated using HDR (DFI clock) or SDR (DFI PHY clock) values. Selects whether value in DFITMG0.dfi_tphy_wrlat is in terms of HDR (DFI clock) or SDR (DFI PHY clock).." "Else,?" newline rbitfld.long 0x0 14. "RESERVED,Reserved" "0,1" newline hexmask.long.byte 0x0 8.--13. 1. "DFI_TPHY_WRDATA,Specifies the number of clock cycles between when dfi_wrdata_en is asserted to when the associated write data is driven on the dfi_wrdata signal. This corresponds to the DFI timing parameter tphy_wrdata. For more information on correct.." newline rbitfld.long 0x0 6.--7. "RESERVED,Reserved" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "DFI_TPHY_WRLAT,Write latency. Number of clocks from the write command to write data enable (dfi_wrdata_en). This corresponds to the DFI timing parameter tphy_wrlat. Refer to PHY specification for correct value.Note that depending on the PHY if using.." line.long 0x4 "DFITMG1,DFI Timing Register 1" hexmask.long.byte 0x4 28.--31. 1. "DFI_T_CMD_LAT,Specifies the number of DFI PHY clock cycles between when the dfi_cs signal is asserted and when the associated command is driven. This field is used for CAL mode must be set to '0' or tCAL which matches the CAL mode register setting in.." newline rbitfld.long 0x4 26.--27. "RESERVED,Reserved" "0,1,2,3" newline bitfld.long 0x4 24.--25. "DFI_T_PARIN_LAT,Specifies the number of DFI PHY clock cycles between when the dfi_cs signal is asserted and when the associated dfi_parity_in signal is driven. Unit: DFI PHY clock cycles. Programming Mode: Quasi-dynamic Group 4" "0,1,2,3" newline rbitfld.long 0x4 21.--23. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x4 16.--20. 1. "DFI_T_WRDATA_DELAY,Specifies the number of DFI clock cycles between when the dfi_wrdata_en signal is asserted and when the corresponding write data transfer is completed on the DRAM bus. This corresponds to the DFI timing parameter twrdata_delay. For.." newline rbitfld.long 0x4 13.--15. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x4 8.--12. 1. "DFI_T_DRAM_CLK_DISABLE,Specifies the number of DFI clock cycles from the assertion of the dfi_dram_clk_disable signal on the DFI until the clock to the DRAM memory devices at the PHY-DRAM boundary maintains a low value. If the DFI clock and the memory.." newline rbitfld.long 0x4 5.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x4 0.--4. 1. "DFI_T_DRAM_CLK_ENABLE,Specifies the number of DFI clock cycles from the de-assertion of the dfi_dram_clk_disable signal on the DFI until the first valid rising edge of the clock to the DRAM memory devices at the PHY-DRAM boundary. If the DFI clock and.." line.long 0x8 "DFILPCFG0,DFI Low Power Configuration Register 0" rbitfld.long 0x8 29.--31. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x8 24.--28. 1. "DFI_TLP_RESP,Indicates the setting in DFI clock cycles for DFI's tlp_resp time. Same value is used for both Power Down self-refresh Deep Power Down and Maximum Power Saving modes. For more information on recommended values see PHY databook Unit: DFI.." newline hexmask.long.byte 0x8 20.--23. 1. "DFI_LP_WAKEUP_DPD,Indicates the value in DFI clock cycles to drive on dfi_lp_wakeup signal when Deep Power Down mode is entered. Determines the DFI's tlp_wakeup time: - 0x0 - 16 cycles - 0x1 - 32 cycles - 0x2 - 64 cycles - 0x3 - 128 cycles - 0x4 - 256.." newline rbitfld.long 0x8 17.--19. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 16. "DFI_LP_EN_DPD,Enables DFI Low Power interface handshaking during Deep Power Down Entry/Exit. - 0 - Disabled - 1 - Enabled This is only present for designs supporting mDDR or LPDDR2/LPDDR3 devices. Programming Mode: Static" "Disabled,Enabled" newline hexmask.long.byte 0x8 12.--15. 1. "DFI_LP_WAKEUP_SR,Indicates the value in DFI clock cycles to drive on dfi_lp_wakeup signal when self-refresh mode is entered. Determines the DFI's tlp_wakeup time: - 0x0 - 16 cycles - 0x1 - 32 cycles - 0x2 - 64 cycles - 0x3 - 128 cycles - 0x4 - 256 cycles.." newline rbitfld.long 0x8 9.--11. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 8. "DFI_LP_EN_SR,Enables DFI Low Power interface handshaking during self-refresh Entry/Exit. - 0 - Disabled - 1 - Enabled Programming Mode: Static" "Disabled,Enabled" newline hexmask.long.byte 0x8 4.--7. 1. "DFI_LP_WAKEUP_PD,Indicates the value in DFI clock cycles to drive on dfi_lp_wakeup signal when Power Down mode is entered. Determines the DFI's tlp_wakeup time: - 0x0 - 16 cycles - 0x1 - 32 cycles - 0x2 - 64 cycles - 0x3 - 128 cycles - 0x4 - 256 cycles -.." newline rbitfld.long 0x8 1.--3. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 0. "DFI_LP_EN_PD,Enables DFI Low Power interface handshaking during Power Down Entry/Exit. - 0 - Disabled - 1 - Enabled Programming Mode: Static" "Disabled,Enabled" line.long 0xC "DFILPCFG1,DFI Low Power Configuration Register 1" hexmask.long.tbyte 0xC 8.--31. 1. "RESERVED,Reserved" newline hexmask.long.byte 0xC 4.--7. 1. "DFI_LP_WAKEUP_MPSM,Indicates the value in DFI clock cycles to drive on dfi_lp_wakeup signal when Maximum Power Saving Mode is entered. Determines the DFI's tlp_wakeup time: - 0x0 - 16 cycles - 0x1 - 32 cycles - 0x2 - 64 cycles - 0x3 - 128 cycles - 0x4 -.." newline rbitfld.long 0xC 1.--3. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline bitfld.long 0xC 0. "DFI_LP_EN_MPSM,Enables DFI Low Power interface handshaking during Maximum Power Saving Mode Entry/Exit. - 0 - Disabled - 1 - Enabled This is only present for designs supporting DDR4 devices. Programming Mode: Static" "Disabled,Enabled" line.long 0x10 "DFIUPD0,DFI Update Register 0" bitfld.long 0x10 31. "DIS_AUTO_CTRLUPD,When '1' disable the automatic dfi_ctrlupd_req generation by the uMCTL2. The controller must issue the dfi_ctrlupd_req signal using register DBGCMD.ctrlupd. When '0' uMCTL2 issues dfi_ctrlupd_req periodically. Programming Mode:.." "0,1" newline bitfld.long 0x10 30. "DIS_AUTO_CTRLUPD_SRX,When '1' disable the automatic dfi_ctrlupd_req generation by the uMCTL2 at self-refresh exit. When '0' uMCTL2 issues a dfi_ctrlupd_req before or after exiting self-refresh depending on DFIUPD0.ctrlupd_pre_srx. Programming Mode:.." "0,1" newline bitfld.long 0x10 29. "CTRLUPD_PRE_SRX,Selects dfi_ctrlupd_req requirements at SRX: - 0 - Send ctrlupd after SRX - 1 - Send ctrlupd before SRX If DFIUPD0.dis_auto_ctrlupd_srx=1 this register has no impact because no dfi_ctrlupd_req is issued when SRX. Programming Mode: Static" "Send ctrlupd after SRX,Send ctrlupd before SRX" newline rbitfld.long 0x10 26.--28. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline hexmask.long.word 0x10 16.--25. 1. "DFI_T_CTRLUP_MAX,Specifies the maximum number of DFI clock cycles that the dfi_ctrlupd_req signal can assert. Lowest value to assign to this variable is 0x40. Unit: DFI clock cycles. Programming Mode: Static" newline hexmask.long.byte 0x10 10.--15. 1. "RESERVED,Reserved" newline hexmask.long.word 0x10 0.--9. 1. "DFI_T_CTRLUP_MIN,Specifies the minimum number of DFI clock cycles that the dfi_ctrlupd_req signal must be asserted. The uMCTL2 expects the PHY to respond within this time. If the PHY does not respond the uMCTL2 de-asserts dfi_ctrlupd_req after.." line.long 0x14 "DFIUPD1,DFI Update Register 1" hexmask.long.byte 0x14 24.--31. 1. "RESERVED,Reserved" newline hexmask.long.byte 0x14 16.--23. 1. "DFI_T_CTRLUPD_INTERVAL_MIN_X1024,This is the minimum amount of time between uMCTL2 initiated DFI update requests (which is executed whenever the uMCTL2 is idle). Set this number higher to reduce the frequency of update requests which can have a small.." newline hexmask.long.byte 0x14 8.--15. 1. "RESERVED,Reserved" newline hexmask.long.byte 0x14 0.--7. 1. "DFI_T_CTRLUPD_INTERVAL_MAX_X1024,This is the maximum amount of time between uMCTL2 initiated DFI update requests. This timer resets with each update request; when the timer expires dfi_ctrlupd_req is sent and traffic is blocked until the dfi_ctrlupd_ackx.." line.long 0x18 "DFIUPD2,DFI Update Register 2" bitfld.long 0x18 31. "DFI_PHYUPD_EN,Enables the support for acknowledging PHY-initiated updates: - 0 - Disabled - 1 - Enabled Programming Mode: Static" "Disabled,Enabled" newline hexmask.long 0x18 0.--30. 1. "RESERVED,Reserved" group.long 0x1B0++0xB line.long 0x0 "DFIMISC,DFI Miscellaneous Control Register" hexmask.long.tbyte 0x0 13.--31. 1. "RESERVED,Reserved" newline hexmask.long.byte 0x0 8.--12. 1. "DFI_FREQUENCY,Indicates the operating frequency of the system. The number of supported frequencies and the mapping of signal values to clock frequencies are defined by the PHY. Programming Mode: Quasi-dynamic Group 1" newline bitfld.long 0x0 7. "LP_OPTIMIZED_WRITE,If this bit is 1 LPDDR4 write DQ is set to 8'hF8 if masked write with enabling DBI; otherwise that value is set to 8'hFF. Programming Mode: Quasi-dynamic Group 3" "0,1" newline bitfld.long 0x0 6. "DIS_DYN_ADR_TRI,If this bit is 1 PHY specific Dynamic Tristating which is a specific feature to certain Synopsys PHYs is disabled. If this bit is 0 a special IDLE command is issued on the DFI while dfi_cs is inactive state so that the PHY can detect.." "?,phase 0 and 1) dfi_we_n= 1" newline bitfld.long 0x0 5. "DFI_INIT_START,PHY init start request signal.When asserted it triggers the PHY init start request. Programming Mode: Quasi-dynamic Group 3" "0,1" newline bitfld.long 0x0 4. "CTL_IDLE_EN,Enables support of ctl_idle signal which is non-DFI related pin specific to certain Synopsys PHYs. For more information on ctl_idle functionality see signal description of ctl_idle signal. Programming Mode: Static" "0,1" newline rbitfld.long 0x0 3. "RESERVED,Reserved" "0,1" newline bitfld.long 0x0 2. "DFI_DATA_CS_POLARITY,Defines polarity of dfi_wrdata_cs and dfi_rddata_cs signals. - 0 - Signals are active low - 1 - Signals are active high Programming Mode: Static" "Signals are active low,Signals are active high" newline bitfld.long 0x0 1. "PHY_DBI_MODE,DBI implemented in DDRC or PHY. - 0 - DDRC implements DBI functionality - 1 - PHY implements DBI functionality Present only in designs configured to support DDR4 and LPDDR4. Programming Mode: Static" "DDRC implements DBI functionality,PHY implements DBI functionality" newline bitfld.long 0x0 0. "DFI_INIT_COMPLETE_EN,PHY initialization complete enable signal. When asserted the dfi_init_complete signal can be used to trigger SDRAM initialisation Programming Mode: Quasi-dynamic Group 3" "0,1" line.long 0x4 "DFITMG2,DFI Timing Register 2" hexmask.long.tbyte 0x4 15.--31. 1. "RESERVED,Reserved" newline hexmask.long.byte 0x4 8.--14. 1. "DFI_TPHY_RDCSLAT,specifies the number of DFI PHY clock cycles between when a read command is sent on the DFI control interface and when the associated dfi_rddata_cs signal is asserted. This corresponds to the DFI timing parameter tphy_rdcslat. Refer to.." newline rbitfld.long 0x4 6.--7. "RESERVED,Reserved" "0,1,2,3" newline hexmask.long.byte 0x4 0.--5. 1. "DFI_TPHY_WRCSLAT,Specifies the number of DFI PHY clock cycles between when a write command is sent on the DFI control interface and when the associated dfi_wrdata_cs signal is asserted. This corresponds to the DFI timing parameter tphy_wrcslat. For more.." line.long 0x8 "DFITMG3,DFI Timing Register 3" hexmask.long 0x8 5.--31. 1. "RESERVED,Reserved" newline hexmask.long.byte 0x8 0.--4. 1. "DFI_T_GEARDOWN_DELAY,The delay from dfi_geardown_en assertion to the time of the PHY being ready to receive commands. Refer to PHY specification for correct value. When the controller is operating in 1:2 frequency ratio mode program this to.." rgroup.long 0x1BC++0x3 line.long 0x0 "DFISTAT,DFI Status Register" hexmask.long 0x0 2.--31. 1. "RESERVED,Reserved" newline bitfld.long 0x0 1. "DFI_LP_ACK,Stores the value of the dfi_lp_ack input to the controller. Programming Mode: Dynamic" "0,1" newline bitfld.long 0x0 0. "DFI_INIT_COMPLETE,This a status flag register which announces when the DFI initialization has been completed. The DFI INIT triggered by dfi_init_start signal and then the dfi_init_complete flag is polled to know when the initialization is done." "0,1" group.long 0x1C0++0x7 line.long 0x0 "DBICTL,DM/DBI Control Register" hexmask.long 0x0 3.--31. 1. "RESERVED,Reserved" newline bitfld.long 0x0 2. "RD_DBI_EN,Read DBI enable signal in DDRC. - 0 - Read DBI is disabled - 1 - Read DBI is enabled This signal must be set the same value as DRAM's mode register. - DDR4 - MR5 bit A12. When x4 devices are used this signal must be set to 0 - LPDDR4 - MR3[6].." "LPDDR4,Read DBI is enabled" newline bitfld.long 0x0 1. "WR_DBI_EN,Write DBI enable signal in DDRC. - 0 - Write DBI is disabled - 1 - Write DBI is enabled This signal must be set the same value as DRAM's mode register. - DDR4 - MR5 bit A11. When x4 devices are used this signal must be set to 0 - LPDDR4 -.." "LPDDR4,Write DBI is enabled" newline bitfld.long 0x0 0. "DM_EN,Indicates the DM enable signal in DDRC. - 0 - DM is disabled - 1 - DM is enabled This signal must be set the same logical value as DRAM's mode register. - DDR4 - Set this to same value as MR5 bit A10. When x4 devices are used this signal must be.." "LPDDR4,DM is enabled" line.long 0x4 "DFIPHYMSTR,DFI PHY Master" hexmask.long 0x4 1.--31. 1. "RESERVED,Reserved" newline bitfld.long 0x4 0. "DFI_PHYMSTR_EN,Enables the PHY Master Interface: - 0 - Disabled - 1 - Enabled Programming Mode: Static" "Disabled,Enabled" group.long 0x200++0x13 line.long 0x0 "ADDRMAP0,Address Map Register 0" hexmask.long 0x0 5.--31. 1. "RESERVED,Reserved" newline hexmask.long.byte 0x0 0.--4. 1. "ADDRMAP_CS_BIT0,Selects the HIF address bit used as rank address bit 0. Valid Range: 0 to 29 and 31 Internal Base: 6 The selected HIF address bit is determined by adding the internal base to the value of this field. If unused set to 31 and then rank.." line.long 0x4 "ADDRMAP1,Address Map Register 1" hexmask.long.word 0x4 22.--31. 1. "RESERVED,Reserved" newline hexmask.long.byte 0x4 16.--21. 1. "ADDRMAP_BANK_B2,Selects the HIF address bit used as bank address bit 2. Valid Range: 0 to 31 and 63 Internal Base: 4 The selected HIF address bit is determined by adding the internal base to the value of this field. If unused set to 63 and then bank.." newline rbitfld.long 0x4 14.--15. "RESERVED,Reserved" "0,1,2,3" newline hexmask.long.byte 0x4 8.--13. 1. "ADDRMAP_BANK_B1,Selects the HIF address bits used as bank address bit 1. Valid Range: 0 to 32 and 63 Internal Base: 3 The selected HIF address bit for each of the bank address bits is determined by adding the internal base to the value of this field. If.." newline rbitfld.long 0x4 6.--7. "RESERVED,Reserved" "0,1,2,3" newline hexmask.long.byte 0x4 0.--5. 1. "ADDRMAP_BANK_B0,Selects the HIF address bits used as bank address bit 0. Valid Range: 0 to 32 and 63 Internal Base: 2 The selected HIF address bit for each of the bank address bits is determined by adding the internal base to the value of this field. If.." line.long 0x8 "ADDRMAP2,Address Map Register 2" hexmask.long.byte 0x8 28.--31. 1. "RESERVED,Reserved" newline hexmask.long.byte 0x8 24.--27. 1. "ADDRMAP_COL_B5,- Full bus width mode - Selects the HIF address bit used as column address bit 5 - Half bus width mode - Selects the HIF address bit used as column address bit 6 - Quarter bus width mode - Selects the HIF address bit used as column address.." newline hexmask.long.byte 0x8 20.--23. 1. "RESERVED,Reserved" newline hexmask.long.byte 0x8 16.--19. 1. "ADDRMAP_COL_B4,- Full bus width mode - Selects the HIF address bit used as column address bit 4 - Half bus width mode - Selects the HIF address bit used as column address bit 5 - Quarter bus width mode - Selects the HIF address bit used as column address.." newline rbitfld.long 0x8 13.--15. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x8 8.--12. 1. "ADDRMAP_COL_B3,- Full bus width mode - Selects the HIF address bit used as column address bit 3 - Half bus width mode - Selects the HIF address bit used as column address bit 4 - Quarter bus width mode - Selects the HIF address bit used as column address.." newline hexmask.long.byte 0x8 4.--7. 1. "RESERVED,Reserved" newline hexmask.long.byte 0x8 0.--3. 1. "ADDRMAP_COL_B2,- Full bus width mode - Selects the HIF address bit used as column address bit 2 - Half bus width mode - Selects the HIF address bit used as column address bit 3 - Quarter bus width mode - Selects the HIF address bit used as column address.." line.long 0xC "ADDRMAP3,Address Map Register 3" rbitfld.long 0xC 29.--31. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0xC 24.--28. 1. "ADDRMAP_COL_B9,- Full bus width mode - Selects the HIF address bit used as column address bit 9 - Half bus width mode - Selects the HIF address bit used as column address bit 11 (10 in LPDDR2/LPDDR3 mode) - Quarter bus width mode - Selects the HIF.." newline rbitfld.long 0xC 21.--23. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0xC 16.--20. 1. "ADDRMAP_COL_B8,- Full bus width mode - Selects the HIF address bit used as column address bit 8 - Half bus width mode - Selects the HIF address bit used as column address bit 9 - Quarter bus width mode - Selects the HIF address bit used as column address.." newline rbitfld.long 0xC 13.--15. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0xC 8.--12. 1. "ADDRMAP_COL_B7,- Full bus width mode - Selects the HIF address bit used as column address bit 7 - Half bus width mode - Selects the HIF address bit used as column address bit 8 - Quarter bus width mode - Selects the HIF address bit used as column address.." newline rbitfld.long 0xC 5.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0xC 0.--4. 1. "ADDRMAP_COL_B6,- Full bus width mode - Selects the HIF address bit used as column address bit 6. - Half bus width mode - Selects the HIF address bit used as column address bit 7. - Quarter bus width mode - Selects the HIF address bit used as column.." line.long 0x10 "ADDRMAP4,Address Map Register 4" bitfld.long 0x10 31. "COL_ADDR_SHIFT,The register provides a capability to map column address to lower HIF address in specific cases required by inline ECC configuration. - If it is 1 internal base of all the column address can be -2 to make mapping range of column address.." "0,1" newline hexmask.long.tbyte 0x10 13.--30. 1. "RESERVED,Reserved" newline hexmask.long.byte 0x10 8.--12. 1. "ADDRMAP_COL_B11,- Full bus width mode - Selects the HIF address bit used as column address bit 13 (11 in LPDDR2/LPDDR3 mode) - Half bus width mode - UNUSED. See later in this description for value you need to set to make it unused - Quarter bus width.." newline rbitfld.long 0x10 5.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x10 0.--4. 1. "ADDRMAP_COL_B10,- Full bus width mode: Selects the HIF address bit used as column address bit 11 (10 in LPDDR2/LPDDR3 mode) - Half bus width mode: Selects the HIF address bit used as column address bit 13 (11 in LPDDR2/LPDDR3 mode) - Quarter bus width.." repeat 3. (list 0x5 0x9 0xA )(list 0x0 0x10 0x14 ) group.long ($2+0x214)++0x3 line.long 0x0 "ADDRMAP$1,Address Map Register 5" hexmask.long.byte 0x0 28.--31. 1. "RESERVED,Reserved" newline hexmask.long.byte 0x0 24.--27. 1. "ADDRMAP_ROW_B11,Selects the HIF address bit used as row address bit 11. Valid Range: 0 to 11 and 15 Internal Base: 17 The selected HIF address bit is determined by adding the internal base to the value of this field. If unused set to 15 and then row.." newline hexmask.long.byte 0x0 20.--23. 1. "RESERVED,Reserved" newline hexmask.long.byte 0x0 16.--19. 1. "ADDRMAP_ROW_B2_10,Selects the HIF address bits used as row address bits 2 to 10. Valid Range: 0 to 11 and 15 Internal Base: 8 (for row address bit 2) 9 (for row address bit 3) 10 (for row address bit 4) and so on increasing to 16 (for row address bit.." newline hexmask.long.byte 0x0 12.--15. 1. "RESERVED,Reserved" newline hexmask.long.byte 0x0 8.--11. 1. "ADDRMAP_ROW_B1,Selects the HIF address bits used as row address bit 1. Valid Range: 0 to 11 Internal Base: 7 The selected HIF address bit for each of the row address bits is determined by adding the internal base to the value of this field. Programming.." newline hexmask.long.byte 0x0 4.--7. 1. "RESERVED,Reserved" newline hexmask.long.byte 0x0 0.--3. 1. "ADDRMAP_ROW_B0,Selects the HIF address bits used as row address bit 0. Valid Range: 0 to 11 Internal Base: 6 The selected HIF address bit for each of the row address bits is determined by adding the internal base to the value of this field. Programming.." repeat.end group.long 0x218++0xB line.long 0x0 "ADDRMAP6,Address Map Register 6" bitfld.long 0x0 31. "LPDDR3_6GB_12GB,Set this to 1 if there is an LPDDR3 SDRAM 6Gb or 12Gb device in use. - 1 - LPDDR3 SDRAM 6Gb/12Gb device in use. Every address having row[14:13]==2'b11 is considered as invalid - 0 - non-LPDDR3 6Gb/12Gb device in use. All addresses are.." "non-LPDDR3 6Gb/12Gb device in use,LPDDR3 SDRAM 6Gb/12Gb device in use" newline bitfld.long 0x0 29.--30. "LPDDR4_3GB_6GB_12GB,Indicates what type of LPDDR4 SDRAM device is in use. Here the density size is per channel. - 2'b00 - No LPDDR4 SDRAM 3Gb/6Gb/12Gb device in use. All addresses are valid - 2'b01 - LPDDR4 SDRAM 3Gb device with x16 mode in use. Every.." "No LPDDR4 SDRAM 3Gb/6Gb/12Gb device in use,LPDDR4 SDRAM 3Gb device with x16 mode in use,LPDDR4 SDRAM 6Gb device with x16 mode or 3Gb..,LPDDR4 SDRAM 12Gb device with x16 mode or 6Gb.." newline rbitfld.long 0x0 28. "RESERVED,Reserved" "0,1" newline hexmask.long.byte 0x0 24.--27. 1. "ADDRMAP_ROW_B15,Selects the HIF address bit used as row address bit 15. Valid Range: 0 to 11 and 15 Internal Base: 21 The selected HIF address bit is determined by adding the internal base to the value of this field. If unused set to 15 and then row.." newline hexmask.long.byte 0x0 20.--23. 1. "RESERVED,Reserved" newline hexmask.long.byte 0x0 16.--19. 1. "ADDRMAP_ROW_B14,Selects the HIF address bit used as row address bit 14. Valid Range: 0 to 11 and 15 Internal Base: 20 The selected HIF address bit is determined by adding the internal base to the value of this field. If unused set to 15 and then row.." newline hexmask.long.byte 0x0 12.--15. 1. "RESERVED,Reserved" newline hexmask.long.byte 0x0 8.--11. 1. "ADDRMAP_ROW_B13,Selects the HIF address bit used as row address bit 13. Valid Range: 0 to 11 and 15 Internal Base: 19 The selected HIF address bit is determined by adding the internal base to the value of this field. If unused set to 15 and then row.." newline hexmask.long.byte 0x0 4.--7. 1. "RESERVED,Reserved" newline hexmask.long.byte 0x0 0.--3. 1. "ADDRMAP_ROW_B12,Selects the HIF address bit used as row address bit 12. Valid Range: 0 to 11 and 15 Internal Base: 18 The selected HIF address bit is determined by adding the internal base to the value of this field. If unused set to 15 and then row.." line.long 0x4 "ADDRMAP7,Address Map Register 7" hexmask.long.tbyte 0x4 12.--31. 1. "RESERVED,Reserved" newline hexmask.long.byte 0x4 8.--11. 1. "ADDRMAP_ROW_B17,Selects the HIF address bit used as row address bit 17. Valid Range: 0 to 11 and 15 Internal Base: 23 The selected HIF address bit is determined by adding the internal base to the value of this field. If unused set to 15 and then row.." newline hexmask.long.byte 0x4 4.--7. 1. "RESERVED,Reserved" newline hexmask.long.byte 0x4 0.--3. 1. "ADDRMAP_ROW_B16,Selects the HIF address bit used as row address bit 16. Valid Range: 0 to 11 and 15 Internal Base: 22 The selected HIF address bit is determined by adding the internal base to the value of this field. If unused set to 15 and then row.." line.long 0x8 "ADDRMAP8,Address Map Register 8" hexmask.long.tbyte 0x8 14.--31. 1. "RESERVED,Reserved" newline hexmask.long.byte 0x8 8.--13. 1. "ADDRMAP_BG_B1,Selects the HIF address bits used as bank group address bit 1. Valid Range: 0 to 32 and 63 Internal Base: 3 The selected HIF address bit for each of the bank group address bits is determined by adding the internal base to the value of this.." newline rbitfld.long 0x8 6.--7. "RESERVED,Reserved" "0,1,2,3" newline hexmask.long.byte 0x8 0.--5. 1. "ADDRMAP_BG_B0,Selects the HIF address bits used as bank group address bit 0. Valid Range: 0 to 32 and 63 Internal Base: 2 The selected HIF address bit for each of the bank group address bits is determined by adding the internal base to the value of this.." group.long 0x22C++0x3 line.long 0x0 "ADDRMAP11,Address Map Register 11" hexmask.long 0x0 4.--31. 1. "RESERVED,Reserved" newline hexmask.long.byte 0x0 0.--3. 1. "ADDRMAP_ROW_B10,Selects the HIF address bits used as row address bit 10. Valid Range: 0 to 11 Internal Base: 16 The selected HIF address bit for each of the row address bits is determined by adding the internal base to the value of this field. This.." group.long 0x240++0x7 line.long 0x0 "ODTCFG,ODT Configuration Register" hexmask.long.byte 0x0 28.--31. 1. "RESERVED,Reserved" newline hexmask.long.byte 0x0 24.--27. 1. "WR_ODT_HOLD,DFI PHY clock cycles to hold ODT for a write command. The minimum supported value is 2. Recommended values: DDR2: - BL8 - 0x5 (DDR2-400/533/667) 0x6 (DDR2-800) 0x7 (DDR2-1066) - BL4 - 0x3 (DDR2-400/533/667) 0x4 (DDR2-800) 0x5 (DDR2-1066).." newline rbitfld.long 0x0 21.--23. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x0 16.--20. 1. "WR_ODT_DELAY,Indicates the delay in DFI PHY clock cycles from issuing a write command to setting ODT values associated with that command. ODT setting must remain constant for the entire time that DQS is driven by the uMCTL2. Recommended values: DDR2: -.." newline hexmask.long.byte 0x0 12.--15. 1. "RESERVED,Reserved" newline hexmask.long.byte 0x0 8.--11. 1. "RD_ODT_HOLD,DFI PHY clock cycles to hold ODT for a read command. The minimum supported value is 2. Recommended values: DDR2: - BL8 - 0x6 (not DDR2-1066) 0x7 (DDR2-1066) - BL4 - 0x4 (not DDR2-1066) 0x5 (DDR2-1066) DDR3: - BL8 - 0x6 DDR4: - BL8 - 5 +.." newline rbitfld.long 0x0 7. "RESERVED,Reserved" "0,1" newline hexmask.long.byte 0x0 2.--6. 1. "RD_ODT_DELAY,Indicates the delay in DFI PHY clock cycles from issuing a read command to setting ODT values associated with that command. ODT setting must remain constant for the entire time that DQS is driven by the uMCTL2. Recommended values: DDR2: -.." newline rbitfld.long 0x0 0.--1. "RESERVED,Reserved" "0,1,2,3" line.long 0x4 "ODTMAP,ODT/Rank Map Register" hexmask.long.tbyte 0x4 14.--31. 1. "RESERVED,Reserved" newline bitfld.long 0x4 12.--13. "RANK1_RD_ODT,Indicates which remote ODTs must be turned on during a read from rank 1. Each rank has a remote ODT (in the SDRAM) which can be turned on by setting the appropriate bit here. Rank 0 is controlled by the LSB; rank 1 is controlled by bit next.." "0,1,2,3" newline rbitfld.long 0x4 10.--11. "RESERVED,Reserved" "0,1,2,3" newline bitfld.long 0x4 8.--9. "RANK1_WR_ODT,Indicates which remote ODTs must be turned on during a write to rank 1. Each rank has a remote ODT (in the SDRAM) which can be turned on by setting the appropriate bit here. Rank 0 is controlled by the LSB; rank 1 is controlled by bit next.." "0,1,2,3" newline rbitfld.long 0x4 6.--7. "RESERVED,Reserved" "0,1,2,3" newline bitfld.long 0x4 4.--5. "RANK0_RD_ODT,Indicates which remote ODTs must be turned on during a read from rank 0. Each rank has a remote ODT (in the SDRAM) which can be turned on by setting the appropriate bit here. Rank 0 is controlled by the LSB; rank 1 is controlled by bit next.." "0,1,2,3" newline rbitfld.long 0x4 2.--3. "RESERVED,Reserved" "0,1,2,3" newline bitfld.long 0x4 0.--1. "RANK0_WR_ODT,Indicates which remote ODTs must be turned on during a write to rank 0. Each rank has a remote ODT (in the SDRAM) which can be turned on by setting the appropriate bit here. Rank 0 is controlled by the LSB; rank 1 is controlled by bit next.." "0,1,2,3" group.long 0x250++0x7 line.long 0x0 "SCHED,Scheduler Control Register" rbitfld.long 0x0 31. "RESERVED,Reserved" "0,1" newline hexmask.long.byte 0x0 24.--30. 1. "RDWR_IDLE_GAP,When the preferred transaction store is empty for these many clock cycles switch to the alternate transaction store if it is non-empty. The read transaction store (both high and low priority) is the default preferred transaction store and.." newline hexmask.long.byte 0x0 16.--23. 1. "GO2CRITICAL_HYSTERESIS,UNUSED. Programming Mode: Static" newline bitfld.long 0x0 15. "LPDDR4_OPT_ACT_TIMING,Optimized ACT timing control for LPDDR4. In LPDDR4 RD/WR/ACT takes 4 cycle. To stream Read/Write there are only 4 cycle space between Reads/Writes. If ACT is scheduled-out after RD/WR with 1 2 or 3 cycle gap next RD/WR may be.." "Disable this feature,Enable this feature" newline rbitfld.long 0x0 13.--14. "RESERVED,Reserved" "0,1,2,3" newline hexmask.long.byte 0x0 8.--12. 1. "LPR_NUM_ENTRIES,Number of entries in the low priority transaction store is this value + 1. (MEMC_NO_OF_ENTRY - (SCHED.lpr_num_entries + 1)) is the number of entries available for the high priority transaction store. Setting this to maximum value.." newline bitfld.long 0x0 7. "AUTOPRE_RMW,Selects behavior of hif_cmd_autopre if a RMW is received on HIF with hif_cmd_autopre=1 - 1 - Apply Autopre only for write part of RMW - 0 - Apply Autopre for both read and write parts of RMW Programming Mode: Static" "Apply Autopre for both read and write parts of RMW,Apply Autopre only for write part of RMW" newline hexmask.long.byte 0x0 3.--6. 1. "RESERVED,Reserved" newline bitfld.long 0x0 2. "PAGECLOSE,If true bank is kept open only while there are page hit transactions available in the CAM to that bank. The last read or write command in the CAM with a bank and page hit is executed with auto-precharge if SCHED1.pageclose_timer=0. Even if.." "0,1" newline bitfld.long 0x0 1. "PREFER_WRITE,If set then the bank selector prefers writes over reads. FOR DEBUG ONLY. Programming Mode: Static" "0,1" newline rbitfld.long 0x0 0. "RESERVED,Reserved" "0,1" line.long 0x4 "SCHED1,Scheduler Control Register 1" hexmask.long.tbyte 0x4 8.--31. 1. "RESERVED,Reserved" newline hexmask.long.byte 0x4 0.--7. 1. "PAGECLOSE_TIMER,This field works in conjunction with SCHED.pageclose.It only has meaning if SCHED.pageclose==1. If SCHED.pageclose==1 and pageclose_timer==0 then an auto-precharge may be scheduled for last read or write command in the CAM with a bank.." group.long 0x25C++0x3 line.long 0x0 "PERFHPR1,High Priority Read CAM Register 1" hexmask.long.byte 0x0 24.--31. 1. "HPR_XACT_RUN_LENGTH,Indicates the number of transactions that are serviced once the HPR queue goes critical is the smaller of: - (a) This number - (b) Number of transactions available Unit: Transaction. FOR PERFORMANCE ONLY. Programming Mode:.." newline hexmask.long.byte 0x0 16.--23. 1. "RESERVED,Reserved" newline hexmask.long.word 0x0 0.--15. 1. "HPR_MAX_STARVE,Indicates the number of DFI clocks that the HPR queue can be starved before it goes critical. The minimum valid functional value for this register is 0x1. Programming it to 0x0 disables the starvation functionality. During normal operation.." group.long 0x264++0x3 line.long 0x0 "PERFLPR1,Low Priority Read CAM Register 1" hexmask.long.byte 0x0 24.--31. 1. "LPR_XACT_RUN_LENGTH,Indicates the number of transactions that are serviced once the LPR queue goes critical is the smaller of: - (a) This number - (b) Number of transactions available Unit: Transaction. FOR PERFORMANCE ONLY. Programming Mode:.." newline hexmask.long.byte 0x0 16.--23. 1. "RESERVED,Reserved" newline hexmask.long.word 0x0 0.--15. 1. "LPR_MAX_STARVE,Indicates the number of DFI clocks that the LPR queue can be starved before it goes critical. The minimum valid functional value for this register is 0x1. Programming it to 0x0 disables the starvation functionality. During normal operation.." group.long 0x26C++0x3 line.long 0x0 "PERFWR1,Write CAM Register 1" hexmask.long.byte 0x0 24.--31. 1. "W_XACT_RUN_LENGTH,Indicates the number of transactions that are serviced once the WR queue goes critical is the smaller of: - (a) This number - (b) Number of transactions available Unit: Transaction. FOR PERFORMANCE ONLY. Programming Mode: Quasi-dynamic.." newline hexmask.long.byte 0x0 16.--23. 1. "RESERVED,Reserved" newline hexmask.long.word 0x0 0.--15. 1. "W_MAX_STARVE,Indicates the number of DFI clocks that the WR queue can be starved before it goes critical. The minimum valid functional value for this register is 0x1. Programming it to 0x0 disables the starvation functionality. During normal operation.." group.long 0x300++0x7 line.long 0x0 "DBG0,Debug Register 0" hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED,Reserved" newline bitfld.long 0x0 7. "DIS_MAX_RANK_WR_OPT,Indicates the disable optimized max_rank_wr and max_logical_rank_wr feature. This register is for debug purpose only. For normal operation This register must be set to 0. Programming Mode: Static" "0,1" newline bitfld.long 0x0 6. "DIS_MAX_RANK_RD_OPT,Indicates the disable optimized max_rank_rd and max_logical_rank_rd feature. This register is for debug purpose only. For normal operation This register must be set to 0. Programming Mode: Static" "0,1" newline rbitfld.long 0x0 5. "RESERVED,Reserved" "0,1" newline bitfld.long 0x0 4. "DIS_COLLISION_PAGE_OPT,When this is set to '0' auto-precharge is disabled for the flushed command in a collision case. Collision cases are write followed by read to same address read followed by write to same address or write followed by write to same.." "0,1" newline rbitfld.long 0x0 1.--3. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 0. "DIS_WC,When 1 disable write combine. FOR DEBUG ONLY. Programming Mode: Static" "0,1" line.long 0x4 "DBG1,Debug Register 1" hexmask.long 0x4 2.--31. 1. "RESERVED,Reserved" newline bitfld.long 0x4 1. "DIS_HIF,When 1 uMCTL2 asserts the HIF command signal hif_cmd_stall. uMCTL2 ignores the hif_cmd_valid and all other associated request signals. This bit is intended to be switched on-the-fly. Programming Mode: Dynamic" "0,1" newline bitfld.long 0x4 0. "DIS_DQ,When 1 uMCTL2 does not de-queue any transactions from the CAM. Bypass is also disabled. All transactions are queued in the CAM. No reads or writes are issued to SDRAM as long as this is asserted. This bit may be used to prevent reads or writes.." "0,1" rgroup.long 0x308++0x3 line.long 0x0 "DBGCAM,CAM Debug Register" bitfld.long 0x0 30.--31. "RESERVED,Reserved" "0,1,2,3" newline bitfld.long 0x0 29. "WR_DATA_PIPELINE_EMPTY,This bit indicates that the write data pipeline on the DFI interface is empty. This register is intended to be polled at least twice after setting DBG1.dis_dq to ensure that all remaining commands/data have completed. Programming.." "0,1" newline bitfld.long 0x0 28. "RD_DATA_PIPELINE_EMPTY,This bit indicates that the read data pipeline on the DFI interface is empty. This register is intended to be polled at least twice after setting DBG1.dis_dq to ensure that all remaining commands/data have completed. Programming.." "0,1" newline bitfld.long 0x0 27. "RESERVED,Reserved" "0,1" newline bitfld.long 0x0 26. "DBG_WR_Q_EMPTY,When 1 all the Write command queues and Write data buffers inside DDRC are empty. This register is to be used for debug purpose. An example use-case scenario: When the controller enters self-refresh using the Low-Power entry sequence.." "0,1" newline bitfld.long 0x0 25. "DBG_RD_Q_EMPTY,When 1 all the Read command queues and Read data buffers inside DDRC are empty. This register is to be used for debug purpose. An example use-case scenario: When the controller enters self-refresh using the Low-Power entry sequence.." "0,1" newline bitfld.long 0x0 24. "DBG_STALL,Stall. FOR DEBUG ONLY. Programming Mode: Dynamic" "0,1" newline bitfld.long 0x0 22.--23. "RESERVED,Reserved" "0,1,2,3" newline hexmask.long.byte 0x0 16.--21. 1. "DBG_W_Q_DEPTH,This field indicates the Write queue depth. The last entry of WR queue is reserved for ECC SCRUB operation. This entry is not included in the calculation of the queue depth. FOR DEBUG ONLY Programming Mode: Dynamic" newline bitfld.long 0x0 14.--15. "RESERVED,Reserved" "0,1,2,3" newline hexmask.long.byte 0x0 8.--13. 1. "DBG_LPR_Q_DEPTH,This field indicates the low priority read queue depth. The last entry of Lpr queue is reserved for ECC SCRUB operation. This entry is not included in the calculation of the queue depth. FOR DEBUG ONLY Programming Mode: Dynamic" newline bitfld.long 0x0 6.--7. "RESERVED,Reserved" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "DBG_HPR_Q_DEPTH,This field indicates the high priority read queue depth. FOR DEBUG ONLY. Programming Mode: Dynamic" group.long 0x30C++0x3 line.long 0x0 "DBGCMD,Command Debug Register" hexmask.long 0x0 6.--31. 1. "RESERVED,Reserved" newline bitfld.long 0x0 5. "CTRLUPD,Setting this register bit to 1 indicates to the uMCTL2 to issue a dfi_ctrlupd_req to the PHY. When this request is stored in the uMCTL2 the bit is automatically cleared. This operation must only be performed when DFIUPD0.dis_auto_ctrlupd=1." "0,1" newline bitfld.long 0x0 4. "ZQ_CALIB_SHORT,Setting this register bit to 1 indicates to the uMCTL2 to issue a ZQCS (ZQ calibration short)/MPC(ZQ calibration) command to the SDRAM. When this request is stored in the uMCTL2 the bit is automatically cleared. This operation can be.." "0,1" newline rbitfld.long 0x0 2.--3. "RESERVED,Reserved" "0,1,2,3" newline bitfld.long 0x0 1. "RANK1_REFRESH,Setting this register bit to 1 indicates to the uMCTL2 to issue a refresh to rank 1. Writing to this bit causes DBGSTAT.rank1_refresh_busy to be set. When DBGSTAT.rank1_refresh_busy is cleared the command has been stored in uMCTL2. For 3DS.." "0,1" newline bitfld.long 0x0 0. "RANK0_REFRESH,Setting this register bit to 1 indicates to the uMCTL2 to issue a refresh to rank 0. Writing to this bit causes DBGSTAT.rank0_refresh_busy to be set. When DBGSTAT.rank0_refresh_busy is cleared the command has been stored in uMCTL2. For 3DS.." "0,1" rgroup.long 0x310++0x3 line.long 0x0 "DBGSTAT,Status Debug Register" hexmask.long 0x0 6.--31. 1. "RESERVED,Reserved" newline bitfld.long 0x0 5. "CTRLUPD_BUSY,SoC might initiate a ctrlupd operation only if this signal is low. This signal goes high in the clock after the uMCTL2 accepts the ctrlupd request. It goes low when the ctrlupd operation is initiated in the uMCTL2. It is recommended not to.." "Indicates that the SoC can initiate a ctrlupd..,Indicates that ctrlupd operation has not been.." newline bitfld.long 0x0 4. "ZQ_CALIB_SHORT_BUSY,SoC might initiate a ZQCS (ZQ calibration short) operation only if this signal is low. This signal goes high in the clock after the uMCTL2 accepts the ZQCS request. It goes low when the ZQCS operation is initiated in the uMCTL2. It is.." "Indicates that the SoC can initiate a ZQCS..,Indicates that ZQCS operation has not been.." newline bitfld.long 0x0 2.--3. "RESERVED,Reserved" "0,1,2,3" newline bitfld.long 0x0 1. "RANK1_REFRESH_BUSY,SoC might initiate a rank1_refresh operation (refresh operation to rank 1) only if this signal is low. This signal goes high in the clock after DBGCMD.rank1_refresh is set to one. It goes low when the rank1_refresh operation is stored.." "Indicates that the SoC can initiate a..,Indicates that rank1_refresh operation has not.." newline bitfld.long 0x0 0. "RANK0_REFRESH_BUSY,SoC might initiate a rank0_refresh operation (refresh operation to rank 0) only if this signal is low. This signal goes high in the clock after DBGCMD.rank0_refresh is set to one. It goes low when the rank0_refresh operation is stored.." "Indicates that the SoC can initiate a..,Indicates that rank0_refresh operation has not.." rgroup.long 0x318++0x3 line.long 0x0 "DBGCAM1,CAM Debug Register 1" hexmask.long 0x0 6.--31. 1. "RESERVED,Reserved" newline hexmask.long.byte 0x0 0.--5. 1. "DBG_WRECC_Q_DEPTH,This field indicates the write ECC queue depth. FOR DEBUG ONLY. Programming Mode: Dynamic" group.long 0x320++0x3 line.long 0x0 "SWCTL,Software Register Programming Control Enable" hexmask.long 0x0 1.--31. 1. "RESERVED,Reserved" newline bitfld.long 0x0 0. "SW_DONE,Enables quasi-dynamic register programming outside reset. Program this register to 0 to enable quasi-dynamic programming. Set back register to 1 once programming is done. Programming Mode: Dynamic" "0,1" rgroup.long 0x324++0x3 line.long 0x0 "SWSTAT,Software Register Programming Control Status" hexmask.long 0x0 1.--31. 1. "RESERVED,Reserved" newline bitfld.long 0x0 0. "SW_DONE_ACK,Register programming done. This register is the echo of SWCTL.sw_done. Wait for sw_done value 1 to propagate to sw_done_ack at the end of the programming sequence to ensure that the correct registers values are propagated to the destination.." "0,1" group.long 0x328++0x3 line.long 0x0 "SWCTLSTATIC,Static Registers Write Enable" hexmask.long 0x0 1.--31. 1. "RESERVED,Reserved" newline bitfld.long 0x0 0. "SW_STATIC_UNLOCK,Enables static register programming outside reset. Program this register to 1 to enable static register programming. Set register back to 0 once programming is done. Programming Mode: Dynamic" "0,1" group.long 0x330++0x7 line.long 0x0 "OCPARCFG0,On-Chip Parity Configuration Register 0" hexmask.long.byte 0x0 27.--31. 1. "RESERVED,Reserved" newline bitfld.long 0x0 26. "PAR_RADDR_ERR_INTR_FORCE,Interrupt force bit for all par_raddr_err_intr. uMCTL2 automatically clears this bit. Programming Mode: Dynamic" "0,1" newline bitfld.long 0x0 25. "PAR_WADDR_ERR_INTR_FORCE,Interrupt force bit for all par_waddr_err_intr. uMCTL2 automatically clears this bit. Programming Mode: Dynamic" "0,1" newline bitfld.long 0x0 24. "PAR_RADDR_ERR_INTR_CLR,Interrupt clear bit for all par_raddr_err_intr. uMCTL2 automatically clears this bit. Programming Mode: Dynamic" "0,1" newline bitfld.long 0x0 23. "PAR_RADDR_ERR_INTR_EN,Enables interrupt generation if set to 1 for all ports on signal par_raddr_err_intr_n upon detection of parity error on the AXI interface. Programming Mode: Dynamic" "0,1" newline bitfld.long 0x0 22. "PAR_WADDR_ERR_INTR_CLR,Interrupt clear bit for all par_waddr_err_intr. uMCTL2 automatically clears this bit. Programming Mode: Dynamic" "0,1" newline bitfld.long 0x0 21. "PAR_WADDR_ERR_INTR_EN,Enables interrupt generation if set to 1 for all ports on signal par_waddr_err_intr_n upon detection of parity error on the AXI interface. Programming Mode: Dynamic" "0,1" newline bitfld.long 0x0 20. "PAR_ADDR_SLVERR_EN,Enables SLVERR generation on read response or write response when address parity error is detected at the AXI interface. Programming Mode: Quasi-dynamic Group 3" "0,1" newline hexmask.long.byte 0x0 16.--19. 1. "RESERVED,Reserved" newline bitfld.long 0x0 15. "PAR_RDATA_ERR_INTR_FORCE,Interrupt force bit for all par_rdata_err_intr_n and par_rdata_in_err_ecc_intr (Inline-ECC only). uMCTL2 automatically clears this bit. Programming Mode: Dynamic" "0,1" newline bitfld.long 0x0 14. "PAR_RDATA_ERR_INTR_CLR,Interrupt clear bit for par_rdata_err_intr. uMCTL2 automatically clears this bit. Programming Mode: Dynamic" "0,1" newline bitfld.long 0x0 13. "PAR_RDATA_ERR_INTR_EN,Enables interrupt generation if set to 1 for all ports on signal par_rdata_err_intr_n upon detection of parity error at the AXI interface. Programming Mode: Dynamic" "0,1" newline bitfld.long 0x0 12. "PAR_RDATA_SLVERR_EN,Enables SLVERR generation on read response when read data parity error is detected at the AXI interface. Programming Mode: Quasi-dynamic Group 3" "0,1" newline hexmask.long.byte 0x0 8.--11. 1. "RESERVED,Reserved" newline bitfld.long 0x0 7. "PAR_WDATA_ERR_INTR_FORCE,Interrupt force bit for par_wdata_err_intr. uMCTL2 automatically clears this bit. Programming Mode: Dynamic" "0,1" newline bitfld.long 0x0 6. "PAR_WDATA_ERR_INTR_CLR,Interrupt clear bit for par_wdata_err_intr. uMCTL2 automatically clears this bit. Programming Mode: Dynamic" "0,1" newline bitfld.long 0x0 5. "PAR_WDATA_SLVERR_EN,Enables SLVERR generation on write response when write data parity error is detected at the AXI interface. Programming Mode: Quasi-dynamic Group 3" "0,1" newline bitfld.long 0x0 4. "PAR_WDATA_ERR_INTR_EN,Enables write data interrupt generation (par_wdata_err_intr) upon detection of parity error at the AXI or DFI interface. Programming Mode: Dynamic" "0,1" newline rbitfld.long 0x0 2.--3. "RESERVED,Reserved" "0,1,2,3" newline bitfld.long 0x0 1. "OC_PARITY_TYPE,Parity type: - 0 - Even parity - 1 - Odd parity Programming Mode: Quasi-dynamic Group 3" "Even parity,Odd parity" newline bitfld.long 0x0 0. "OC_PARITY_EN,Parity enable register. Enables On-Chip parity for all interfaces. Programming Mode: Quasi-dynamic Group 3" "0,1" line.long 0x4 "OCPARCFG1,On-Chip Parity Configuration Register 1" hexmask.long.tbyte 0x4 12.--31. 1. "RESERVED,Reserved" newline hexmask.long.byte 0x4 8.--11. 1. "PAR_POISON_LOC_WR_PORT,Enables parity poisoning on write data at the AXI interface before the input parity check logic. The value specifies the binary encoded port number of the AXI interface to be injected with parity error. Programming Mode:.." newline hexmask.long.byte 0x4 4.--7. 1. "PAR_POISON_LOC_RD_PORT,Enables parity poisoning on read data at the AXI interface after the parity check logic. The value specifies the binary encoded port number of the AXI interface to be injected with parity error. Error can be injected to one port at.." newline bitfld.long 0x4 3. "PAR_POISON_LOC_RD_IECC_TYPE,Selects which parity to poison at the DFI when inline ECC is enabled. If this register is set to 0 parity error is injected on the first read data going through the ECC path. If this register is set to 1 parity error is.." "0,1" newline bitfld.long 0x4 2. "PAR_POISON_LOC_RD_DFI,Enables parity poisoning on read data at the DFI interface after the parity generation logic. When MEMC_INLINE_ECC=1 enables poisoning of ECC word after the ECC encoder at the write data interface at the DFI. Programming Mode:.." "0,1" newline rbitfld.long 0x4 1. "RESERVED,Reserved" "0,1" newline bitfld.long 0x4 0. "PAR_POISON_EN,Enables on-chip parity poisoning on the data interfaces. Programming Mode: Quasi-dynamic Group 3" "0,1" repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) rgroup.long ($2+0x338)++0x3 line.long 0x0 "OCPARSTAT$1,On-Chip Parity Status Register 0" hexmask.long.word 0x0 17.--31. 1. "RESERVED,Reserved" newline bitfld.long 0x0 16. "PAR_RADDR_ERR_INTR_0,Read address parity error interrupt for port 0. This interrupt is asserted when an on-chip read address parity error occurred on the corresponding AXI port's read address channel. Programming Mode: Static" "0,1" newline hexmask.long.word 0x0 1.--15. 1. "RESERVED,Reserved" newline bitfld.long 0x0 0. "PAR_WADDR_ERR_INTR_0,Write address parity error interrupt for port 0. This interrupt is asserted when an on-chip write address parity error occurred on the corresponding AXI port's write address channel. Programming Mode: Static" "0,1" repeat.end rgroup.long 0x340++0x3 line.long 0x0 "OCPARSTAT2,On-Chip Parity Status Register 2" hexmask.long 0x0 5.--31. 1. "RESERVED,Reserved" newline bitfld.long 0x0 4. "PAR_RDATA_IN_ERR_ECC_INTR,Interrupt on ECC data going into inline ECC decoder. Cleared by par_rdata_err_intr_clr. Programming Mode: Static" "0,1" newline bitfld.long 0x0 2.--3. "RESERVED,Reserved" "0,1,2,3" newline bitfld.long 0x0 0.--1. "PAR_WDATA_OUT_ERR_INTR,Write data parity error interrupt on output. Cleared by register par_wdata_err_intr_clr. Programming Mode: Static" "0,1,2,3" group.long 0x36C++0x3 line.long 0x0 "POISONCFG,AXI Poison Configuration Register. Common for all AXI ports." hexmask.long.byte 0x0 25.--31. 1. "RESERVED,Reserved" newline bitfld.long 0x0 24. "RD_POISON_INTR_CLR,Interrupt clear for read transaction poisoning. Allow 2/3 clock cycles for correct value to propagate to controller logic and clear the interrupts. uMCTL2 automatically clears this bit. Programming Mode: Dynamic" "0,1" newline rbitfld.long 0x0 21.--23. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 20. "RD_POISON_INTR_EN,If set to 1 enables interrupts for read transaction poisoning. Programming Mode: Dynamic" "0,1" newline rbitfld.long 0x0 17.--19. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 16. "RD_POISON_SLVERR_EN,If set to 1 enables SLVERR response for read transaction poisoning. Programming Mode: Dynamic" "0,1" newline hexmask.long.byte 0x0 9.--15. 1. "RESERVED,Reserved" newline bitfld.long 0x0 8. "WR_POISON_INTR_CLR,Interrupt clear for write transaction poisoning. Allow 2/3 clock cycles for correct value to propagate to controller logic and clear the interrupts. uMCTL2 automatically clears this bit. Programming Mode: Dynamic" "0,1" newline rbitfld.long 0x0 5.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 4. "WR_POISON_INTR_EN,If set to 1 enables interrupts for write transaction poisoning. Programming Mode: Dynamic" "0,1" newline rbitfld.long 0x0 1.--3. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 0. "WR_POISON_SLVERR_EN,If set to 1 enables SLVERR response for write transaction poisoning. Programming Mode: Dynamic" "0,1" rgroup.long 0x370++0x3 line.long 0x0 "POISONSTAT,AXI Poison Status Register" hexmask.long.word 0x0 17.--31. 1. "RESERVED,Reserved" newline bitfld.long 0x0 16. "RD_POISON_INTR_0,Read transaction poisoning error interrupt for port 0. This register is a APB clock copy (double register synchronizer) of the interrupt asserted when a transaction is poisoned on the corresponding AXI port's read address channel. Bit 0.." "0,1" newline hexmask.long.word 0x0 1.--15. 1. "RESERVED,Reserved" newline bitfld.long 0x0 0. "WR_POISON_INTR_0,Write transaction poisoning error interrupt for port 0. This register is a APB clock copy (double register synchronizer) of the interrupt asserted when a transaction is poisoned on the corresponding AXI port's write address channel. Bit.." "0,1" group.long 0x374++0x3 line.long 0x0 "ADVECCINDEX,Advanced ECC Index Register" hexmask.long.tbyte 0x0 9.--31. 1. "RESERVED,Reserved" newline hexmask.long.byte 0x0 5.--8. 1. "ECC_POISON_BEATS_SEL,Selector of which DRAM beat's poison pattern is set by ECCPOISONPAT0/1/2 registers. For frequency ratio 1:1 mode 2 DRAM beats can be poisoned. Set ecc_poison_beats_sel to 0 and given ECCPOISONPAT0/1/2 to set 1st beat's poison.." newline bitfld.long 0x0 3.--4. "ECC_ERR_SYMBOL_SEL,Selector of which error symbol's status output to ADVECCSTAT.advecc_err_symbol_pos and advecc_err_symbol_bits. The default is first error symbol. The value must be less than ADVECCSTAT.advecc_num_err_symbol. Programming Mode:.." "0,1,2,3" newline bitfld.long 0x0 0.--2. "ECC_SYNDROME_SEL,Selector of which DRAM beat data output to ECCCSYN0/1/2 as well as ECCUCSYN. In Advanced ECC the syndrome consists of number of DRAM beats. This register selects which beats of data is output to ECCCSYN0/1/2 and ECCUCSYN0/1/2 registers." "0,1,2,3,4,5,6,7" group.long 0x37C++0x3 line.long 0x0 "ECCPOISONPAT0,ECC Poison Pattern 0 Register" hexmask.long 0x0 0.--31. 1. "ECC_POISON_DATA_31_0,Indicates the poison pattern for DRAM data[31:0]. setting this bit to 1 indicates poison (invert) corresponding DRAM bit. It is indirect register. Selector is ADVECCINDEX.ecc_poison_beats_sel. Programming Mode: Quasi-dynamic Group 3" group.long 0x384++0x3 line.long 0x0 "ECCPOISONPAT2,ECC Poison Pattern 2 Register" hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED,Reserved" newline hexmask.long.byte 0x0 0.--7. 1. "ECC_POISON_DATA_71_64,Indicates the poison pattern for DRAM data[71:64]. Setting this bit to 1 indicates poison (invert) corresponding DRAM bit. It is indirect register. Selector is ADVECCINDEX.ecc_poison_beats_sel. Programming Mode: Quasi-dynamic Group 3" rgroup.long 0x388++0x3 line.long 0x0 "ECCAPSTAT,Address protection within ECC Status Register" hexmask.long 0x0 1.--31. 1. "RESERVED,Reserved" newline bitfld.long 0x0 0. "ECC_AP_ERR,Indicates the number of ECC errors (correctable/uncorrectable) within one burst exceeded the threshold(ECCCFG0.ecc_ap_err_threshold). Programming Mode: Dynamic" "0,1" group.long 0x3C0++0x3 line.long 0x0 "REGPARCFG,Register Parity Configuration Register (Note that all fields must be programmed with single write operation)." hexmask.long.tbyte 0x0 9.--31. 1. "RESERVED,Reserved" newline bitfld.long 0x0 8. "REG_PAR_POISON_EN,Enable Register Parity poisoning. Programming Mode: Dynamic" "0,1" newline hexmask.long.byte 0x0 4.--7. 1. "RESERVED,Reserved" newline bitfld.long 0x0 3. "REG_PAR_ERR_INTR_FORCE,Interrupt force bit for reg_par_err_intr setting this register causes the output interrupt to be asserted. uMCTL2 automatically clears this bit. There is no interaction between functionally triggering an interrupt and forcing an.." "0,1" newline bitfld.long 0x0 2. "REG_PAR_ERR_INTR_CLR,Interupt clear bit for reg_par_err_intr. uMCTL2 automatically clears this bit. Programming Mode: Dynamic" "0,1" newline bitfld.long 0x0 1. "REG_PAR_ERR_INTR_EN,Enables interrupt generation if set to 1 on signal reg_par_err_intr upon detection of register parity error. Programming Mode: Dynamic" "0,1" newline bitfld.long 0x0 0. "REG_PAR_EN,Register Parity enable register. Programming Mode: Dynamic" "0,1" rgroup.long 0x3C4++0x3 line.long 0x0 "REGPARSTAT,Register Parity Status Register" hexmask.long 0x0 1.--31. 1. "RESERVED,Reserved" newline bitfld.long 0x0 0. "REG_PAR_ERR_INTR,Interrupt asserted when Register Parity error is detected. Cleared by setting REGPARCFG.reg_par_err_intr_clr to 1. Programming Mode: Static" "0,1" group.long 0x3E0++0x3 line.long 0x0 "OCCAPCFG,On-Chip command/Address Protection Configuration Register" hexmask.long.byte 0x0 28.--31. 1. "RESERVED,Reserved" newline bitfld.long 0x0 27. "OCCAP_ARB_RAQ_POISON_EN,Enables poisoning for the Read Address Queues (RAQ) inside each XPI. Poisoning inverts all parity bits generated by the parity generator. Error is flagged as soon as the first RAQ is read. This register is not cleared.." "0,1" newline bitfld.long 0x0 26. "OCCAP_ARB_CMP_POISON_ERR_INJ,Enables error injection in the poisoning of OCCAP Arbiter logic. Injects error into poisoning logic (either parallel or seq) such that XOR logic for one signal is not poisoned when expected. If set it allows ability to.." "OCCAPSTAT,OCCAPSTAT" newline bitfld.long 0x0 25. "OCCAP_ARB_CMP_POISON_PARALLEL,Enables full poisoning for compare logic inside XPI. Poisoning inverts all bits of all outputs coming from the duplicated modules before the XOR comparators together. uMCTL2 automatically clears this bit. Programming Mode:.." "0,1" newline bitfld.long 0x0 24. "OCCAP_ARB_CMP_POISON_SEQ,Enables poisoning for compare logic inside XPI. Poisoning inverts all bits coming from the duplicated modules before the XOR comparators one output at the time per each comparator. uMCTL2 automatically clears this bit." "0,1" newline hexmask.long.byte 0x0 19.--23. 1. "RESERVED,Reserved" newline bitfld.long 0x0 18. "OCCAP_ARB_INTR_FORCE,Interrupt force bit for occap_arb_err_intr setting this register causes the output interrupt to be asserted. uMCTL2 automatically clears this bit. There is no interaction between functionally triggering an interrupt and forcing an.." "0,1" newline bitfld.long 0x0 17. "OCCAP_ARB_INTR_CLR,Interrupt clear bit for occap_arb_err_intr and occap_arb_cmp_poison_complete. uMCTL2 automatically clears this bit. Programming Mode: Dynamic" "0,1" newline bitfld.long 0x0 16. "OCCAP_ARB_INTR_EN,Enables interrupt generation upon detection of OCCAP Arbiter errors. Programming Mode: Dynamic" "0,1" newline hexmask.long.word 0x0 1.--15. 1. "RESERVED,Reserved" newline bitfld.long 0x0 0. "OCCAP_EN,On Chip Command/Address Path Protection (OCCAP) enable register. Programming Mode: Quasi-dynamic Group 3" "0,1" rgroup.long 0x3E4++0x3 line.long 0x0 "OCCAPSTAT,On-Chip command/Address Protection Status Register" hexmask.long.byte 0x0 26.--31. 1. "RESERVED,Reserved" newline bitfld.long 0x0 25. "OCCAP_ARB_CMP_POISON_PARALLEL_ERR,Error when occap_arb_cmp_poison_full_en is active due to incorrect number of errors being occurring. Internal logic checks the number of errors detected while poisoning occurred for occap_arb_cmp_poison_full_en. It.." "0,1" newline bitfld.long 0x0 24. "OCCAP_ARB_CMP_POISON_SEQ_ERR,Error when occap_arb_cmp_poison_en is active due to incorrect number of errors being occurring. Internal logic checks that the correct number of errors detected while poisoning one output at the time occurred for.." "0,1" newline hexmask.long.byte 0x0 18.--23. 1. "RESERVED,Reserved" newline bitfld.long 0x0 17. "OCCAP_ARB_CMP_POISON_COMPLETE,OCCAP ARB comparator poisoning complete interrupt status. Register cleared by OCCAPCFG.occap_arb_intr_clr. Programming Mode: Static" "0,1" newline bitfld.long 0x0 16. "OCCAP_ARB_ERR_INTR,OCCAP Arbiter error interrupt status. Register cleared by OCCAPCFG.occap_arb_intr_clr. Programming Mode: Static" "0,1" newline hexmask.long.word 0x0 0.--15. 1. "RESERVED,Reserved" group.long 0x3E8++0x3 line.long 0x0 "OCCAPCFG1,On-Chip command/Address Protection Configuration Register 1" hexmask.long.byte 0x0 27.--31. 1. "RESERVED,Reserved" newline bitfld.long 0x0 26. "OCCAP_DDRC_CTRL_POISON_ERR_INJ,Enables error injection in the poisoning of OCCAP DDRC CTRL logic. Injects error into poisoning logic (either parallel or seq) such that XOR logic for one signal is not poisoned when expected. If set it allows ability to.." "OCCAPSTAT1,OCCAPSTAT1" newline bitfld.long 0x0 25. "OCCAP_DDRC_CTRL_POISON_PARALLEL,Enables poisoning of OCCAP DDRC CTRL logic for all parts of comparison logic in parallel. Poisons comparison logic for one core_ddrc_core_clk cycle by inverting a ddrc_ctrl[0]'s signal to XOR logic. ddrc_ctrl[1] related.." "0,1" newline bitfld.long 0x0 24. "OCCAP_DDRC_CTRL_POISON_SEQ,Enables poisoning of OCCAP DDRC CTRL logic for all parts of comparison logic in sequence. Poisons comparison logic for one core_ddrc_core_clk cycle by inverting a ddrc_ctrl[0]'s signal to XOR logic. ddrc_ctrl[1] related.." "0,1" newline hexmask.long.byte 0x0 19.--23. 1. "RESERVED,Reserved" newline bitfld.long 0x0 18. "OCCAP_DDRC_CTRL_INTR_FORCE,Interrupt force bit for occap_ddrc_ctrl_err_intr setting this register causes the output interrupt to be asserted. uMCTL2 automatically clears this bit. There is no interaction between functionally triggering an interrupt and.." "0,1" newline bitfld.long 0x0 17. "OCCAP_DDRC_CTRL_INTR_CLR,Interrupt clear bit for occap_ddrc_ctrl_err_intr. uMCTL2 automatically clears this bit. Programming Mode: Dynamic" "0,1" newline bitfld.long 0x0 16. "OCCAP_DDRC_CTRL_INTR_EN,Enables interrupt generation on signal occap_ddrc_ctrl_err_intr upon detection of OCCAP DDRC CTRL errors. Programming Mode: Dynamic" "0,1" newline hexmask.long.byte 0x0 11.--15. 1. "RESERVED,Reserved" newline bitfld.long 0x0 10. "OCCAP_DDRC_DATA_POISON_ERR_INJ,Enables error injection in the poisoning of OCCAP DDRC DATA logic. Injects error into poisoning logic (either parallel or seq) such that XOR logic for one signal is not poisoned when expected. If set it allows ability to.." "OCCAPSTAT1,OCCAPSTAT1" newline bitfld.long 0x0 9. "OCCAP_DDRC_DATA_POISON_PARALLEL,Enables poisoning of OCCAP DDRC DATA logic for all parts of comparison logic in parallel. Poisons comparison logic for one core_ddrc_core_clk cycle by inverting all bits of a signal to XOR logic. All signals of.." "0,1" newline bitfld.long 0x0 8. "OCCAP_DDRC_DATA_POISON_SEQ,Enables poisoning of OCCAP DDRC DATA logic for all parts of comparison logic in sequence. Poisons comparison logic for one core_ddrc_core_clk cycle by inverting all bits of a signal to XOR logic. All signals of instance[0] of.." "0,1" newline hexmask.long.byte 0x0 3.--7. 1. "RESERVED,Reserved" newline bitfld.long 0x0 2. "OCCAP_DDRC_DATA_INTR_FORCE,Interrupt force bit for occap_ddrc_data_err_intr setting this register causes the output interrupt to be asserted. uMCTL2 automatically clears this bit. There is no interaction between functionally triggering an interrupt and.." "0,1" newline bitfld.long 0x0 1. "OCCAP_DDRC_DATA_INTR_CLR,Interrupt clear bit for occap_ddrc_data_err_intr. uMCTL2 automatically clears this bit. Programming Mode: Dynamic" "0,1" newline bitfld.long 0x0 0. "OCCAP_DDRC_DATA_INTR_EN,Enables interrupt generation on signal occap_ddrc_data_err_intr upon detection of OCCAP DDRC DATA errors. Programming Mode: Dynamic" "0,1" rgroup.long 0x3EC++0x7 line.long 0x0 "OCCAPSTAT1,On-Chip command/Address Protection Status Register 1" hexmask.long.byte 0x0 26.--31. 1. "RESERVED,Reserved" newline bitfld.long 0x0 25. "OCCAP_DDRC_CTRL_POISON_PARALLEL_ERR,Error when occap_ddrc_ctrl_poison_parallel is active due to incorrect number of errors being occurring. Internal logic checks the number of errors detected while poisoning occurred for occap_ddrc_ctrl_poison_parallel." "0,1" newline bitfld.long 0x0 24. "OCCAP_DDRC_CTRL_POISON_SEQ_ERR,Error when occap_ddrc_ctrl_poison_seq is active due to incorrect number of errors being occurring. Internal logic checks the number of errors detected while poisoning occurred for occap_ddrc_ctrl_poison_seq. It checks for.." "0,1" newline hexmask.long.byte 0x0 18.--23. 1. "RESERVED,Reserved" newline bitfld.long 0x0 17. "OCCAP_DDRC_CTRL_POISON_COMPLETE,Indicates the OCCAP DDRC CTRL poisoning complete interrupt status. Register cleared by OCCAPCFG1.occap_ddrc_ctrl_err_intr_clr. Programming Mode: Static" "0,1" newline bitfld.long 0x0 16. "OCCAP_DDRC_CTRL_ERR_INTR,Indicates the OCCAP DDRC CTRL error interrupt status. Register cleared by OCCAPCFG1.occap_ddrc_ctrl_err_intr_clr. Programming Mode: Static" "0,1" newline hexmask.long.byte 0x0 10.--15. 1. "RESERVED,Reserved" newline bitfld.long 0x0 9. "OCCAP_DDRC_DATA_POISON_PARALLEL_ERR,Error when occap_ddrc_data_poison_parallel is active due to incorrect number of errors being occurring. Internal logic checks the number of errors detected while poisoning occurred for occap_ddrc_data_poison_parallel." "0,1" newline bitfld.long 0x0 8. "OCCAP_DDRC_DATA_POISON_SEQ_ERR,Error when occap_ddrc_data_poison_seq is active due to incorrect number of errors being occurring. Internal logic checks the number of errors detected while poisoning occurred for occap_ddrc_data_poison_seq. It checks for.." "0,1" newline hexmask.long.byte 0x0 2.--7. 1. "RESERVED,Reserved" newline bitfld.long 0x0 1. "OCCAP_DDRC_DATA_POISON_COMPLETE,Indicates the OCCAP DDRC DATA poisoning complete interrupt status. Register cleared by OCCAPCFG1.occap_ddrc_data_err_intr_clr. Programming Mode: Static" "0,1" newline bitfld.long 0x0 0. "OCCAP_DDRC_DATA_ERR_INTR,Indicates the OCCAP DDRC DATA error interrupt status. Register cleared by OCCAPCFG1.occap_ddrc_data_err_intr_clr. Programming Mode: Static" "0,1" line.long 0x4 "DERATESTAT,Temperature Derate Status Register" hexmask.long 0x4 1.--31. 1. "RESERVED,Reserved" newline bitfld.long 0x4 0. "DERATE_TEMP_LIMIT_INTR,Derate temperature interrupt indicating LPDDR2/3/4 SDRAM temperature operating limit is exceeded. This register field is set to 1 when the value read from MR4[2:0] is 3'b000 or 3'b111. Cleared by register.." "0,1" tree.end tree "UMCTL2_MP (uMCTL2 Multi-Port Registers)" base ad:0x1016 rgroup.long 0x4++0x3 line.long 0x0 "PSTAT,Port Status Register" bitfld.long 0x0 16. "WR_PORT_BUSY_0,Indicates if there are outstanding writes for AXI port 0. Programming Mode: Dynamic" "0,1" bitfld.long 0x0 0. "RD_PORT_BUSY_0,Indicates if there are outstanding reads for AXI port 0. Programming Mode: Dynamic" "0,1" group.long 0x8++0xB line.long 0x0 "PCCFG,Port Common Configuration Register" bitfld.long 0x0 8. "BL_EXP_MODE,Burst length expansion mode. By default (that is bl_exp_mode==0) XPI expands every AXI burst into multiple HIF commands using the memory burst length as a unit. If set to 1 then XPI uses half of the memory burst length as a unit. This.." "UMCTL2_PARTIAL_WR=1,?" bitfld.long 0x0 4. "PAGEMATCH_LIMIT,Page match four limit. If set to 1 limits the number of consecutive same page DDRC transactions that can be granted by the Port Arbiter to four when Page Match feature is enabled. If set to 0 there is no limit imposed on number of.." "0,1" bitfld.long 0x0 0. "GO2CRITICAL_EN,If set to 1 (enabled) sets co_gs_go2critical_wr and co_gs_go2critical_lpr/co_gs_go2critical_hpr signals going to DDRC based on urgent input (awurgent arurgent) coming from AXI master. If set to 0 (disabled) co_gs_go2critical_wr and.." "0,1" line.long 0x4 "PCFGR_0,Port n Configuration Read Register" bitfld.long 0x4 16. "RDWR_ORDERED_EN,Enables ordered read/writes. If set to 1 preserves the ordering between read transaction and write transaction issued to the same address on a given port. In other words the controller ensures that all same address read and write.." "0,1" bitfld.long 0x4 14. "RD_PORT_PAGEMATCH_EN,If set to 1 enables the Page Match feature. If enabled once a requesting port is granted the port is continued to be granted if the following immediate commands are to the same memory page (same rank same bank and same row). See.." "0,1" bitfld.long 0x4 13. "RD_PORT_URGENT_EN,If set to 1 enables the AXI urgent sideband signal (arurgent). When enabled and arurgent is asserted by the master that port becomes the highest priority and co_gs_go2critical_lpr/co_gs_go2critical_hpr signal to DDRC is asserted if.." "0,1" newline bitfld.long 0x4 12. "RD_PORT_AGING_EN,If set to 1 enables aging function for the read channel of the port. Programming Mode: Static" "0,1" hexmask.long.word 0x4 0.--9. 1. "RD_PORT_PRIORITY,Determines the initial load value of read aging counters. These counters are parallel loaded after reset or after each grant to the corresponding port. The aging counters down-count every clock cycle where the port is requesting but not.." line.long 0x8 "PCFGW_0,Port n Configuration Write Register" bitfld.long 0x8 14. "WR_PORT_PAGEMATCH_EN,If set to 1 enables the Page Match feature. If enabled once a requesting port is granted the port is continued to be granted if the following immediate commands are to the same memory page (same rank same bank and same row). See.." "0,1" bitfld.long 0x8 13. "WR_PORT_URGENT_EN,If set to 1 enables the AXI urgent sideband signal (awurgent). When enabled and awurgent is asserted by the master that port becomes the highest priority and co_gs_go2critical_wr signal to DDRC is asserted if enabled in.." "0,1" bitfld.long 0x8 12. "WR_PORT_AGING_EN,If set to 1 enables aging function for the write channel of the port. Programming Mode: Static" "0,1" newline hexmask.long.word 0x8 0.--9. 1. "WR_PORT_PRIORITY,Determines the initial load value of write aging counters. These counters are parallel loaded after reset or after each grant to the corresponding port. The aging counters down-count every clock cycle where the port is requesting but.." group.long 0x98++0x13 line.long 0x0 "PCTRL_0,Port n Control Register" bitfld.long 0x0 0. "PORT_EN,Enables AXI port n. Programming Mode: Dynamic" "0,1" line.long 0x4 "PCFGQOS0_0,Port n Read QoS Configuration Register 0" bitfld.long 0x4 24.--25. "RQOS_MAP_REGION2,This bitfield indicates the traffic class of region2. For dual address queue configurations region2 maps to the red address queue. Valid values are 1: VPR and 2: HPR only. When VPR support is disabled (UMCTL2_VPR_EN = 0) and traffic.." "?,VPR and,HPR only,?" bitfld.long 0x4 20.--21. "RQOS_MAP_REGION1,This bit field indicates the traffic class of region 1. Valid values are: - 0 - LPR - 1 - VPR - 2 - HPR For dual address queue configurations region1 maps to the blue address queue. In this case valid values are - 0 - LPR - 1 - VPR.." "LPR,VPR only,HPR,?" bitfld.long 0x4 16.--17. "RQOS_MAP_REGION0,This bit field indicates the traffic class of region 0. Valid values are: - 0 - LPR - 1 - VPR - 2 - HPR For dual address queue configurations region 0 maps to the blue address queue. In this case valid values are: 0: LPR and 1: VPR.." "LPR and,VPR only,HPR,?" newline hexmask.long.byte 0x4 8.--11. 1. "RQOS_MAP_LEVEL2,Separation level2 indicating the end of region1 mapping; start of region1 is (level1 + 1). Possible values for level2 are (level1 + 1) to 14 which corresponds to arqos. Region2 starts from (level2 + 1) up to 15. Note that for PA arqos.." hexmask.long.byte 0x4 0.--3. 1. "RQOS_MAP_LEVEL1,Separation level1 indicating the end of region0 mapping; start of region0 is 0. Possible values for level1 are 0 to 13 (for dual RAQ) or 0 to 14 (for single RAQ) which corresponds to arqos. Note that for PA arqos values are used directly.." line.long 0x8 "PCFGQOS1_0,Port n Read QoS Configuration Register 1" hexmask.long.word 0x8 16.--26. 1. "RQOS_MAP_TIMEOUTR,Specifies the timeout value for transactions mapped to the red address queue. Programming Mode: Quasi-dynamic Group 3" hexmask.long.word 0x8 0.--10. 1. "RQOS_MAP_TIMEOUTB,Specifies the timeout value for transactions mapped to the blue address queue. Programming Mode: Quasi-dynamic Group 3" line.long 0xC "PCFGWQOS0_0,Port n Write QoS Configuration Register 0" bitfld.long 0xC 24.--25. "WQOS_MAP_REGION2,This bit field indicates the traffic class of region 2. Valid values are: - 0 - NPW - 1 - VPW When VPW support is disabled (UMCTL2_VPW_EN = 0) and traffic class of region 2 is set to 1 (VPW) VPW traffic is aliased to NPW traffic." "NPW,VPW,?,?" bitfld.long 0xC 20.--21. "WQOS_MAP_REGION1,This bit field indicates the traffic class of region 1. Valid values are: 0: NPW 1: VPW. When VPW support is disabled (UMCTL2_VPW_EN = 0) and traffic class of region 1 is set to 1 (VPW) VPW traffic is aliased to NPW traffic." "NPW,VPW,?,?" bitfld.long 0xC 16.--17. "WQOS_MAP_REGION0,This bit field indicates the traffic class of region 0. Valid values are: - 0 - NPW - 1 - VPW When VPW support is disabled (UMCTL2_VPW_EN = 0) and traffic class of region 0 is set to 1 (VPW) VPW traffic is aliased to NPW traffic." "NPW,VPW,?,?" newline hexmask.long.byte 0xC 8.--11. 1. "WQOS_MAP_LEVEL2,Separation level2 indicating the end of region1 mapping; start of region1 is (level1 + 1). Possible values for level2 are (level1 + 1) to 14 which corresponds to awqos. Region2 starts from (level2 + 1) up to 15. Note that for PA awqos.." hexmask.long.byte 0xC 0.--3. 1. "WQOS_MAP_LEVEL1,Separation level indicating the end of region0 mapping; start of region0 is 0. Possible values for level1 are 0 to 13 which corresponds to awqos. Note that for PA awqos values are used directly as port priorities where the higher the.." line.long 0x10 "PCFGWQOS1_0,Port n Write QoS Configuration Register 1" hexmask.long.word 0x10 16.--26. 1. "WQOS_MAP_TIMEOUT2,Specifies the timeout value for write transactions in region 2. Programming Mode: Quasi-dynamic Group 3" hexmask.long.word 0x10 0.--10. 1. "WQOS_MAP_TIMEOUT1,Specifies the timeout value for write transactions in region 0 and 1. Programming Mode: Quasi-dynamic Group 3" repeat 4. (list 0x0 0x1 0x2 0x3 )(list 0x0 0x8 0x10 0x18 ) group.long ($2+0xB0C)++0x3 line.long 0x0 "SARBASE$1,SAR Base Address Register n" hexmask.long.word 0x0 0.--11. 1. "BASE_ADDR,Base address for address region n specified as awaddr[UMCTL2_A_ADDRW-1:x] and araddr[UMCTL2_A_ADDRW-1:x] where x is determined by the minimum block size parameter UMCTL2_SARMINSIZE: (x=log2(block size)). Programming Mode: Static" repeat.end repeat 4. (list 0x0 0x1 0x2 0x3 )(list 0x0 0x8 0x10 0x18 ) group.long ($2+0xB10)++0x3 line.long 0x0 "SARSIZE$1,SAR Size Register n" hexmask.long.byte 0x0 0.--7. 1. "NBLOCKS,Number of blocks for address region n. This register determines the total size of the region in multiples of minimum block size as specified by the hardware parameter UMCTL2_SARMINSIZE. The register value is encoded as number of blocks = nblocks.." repeat.end group.long 0xB2C++0x3 line.long 0x0 "SBRCTL,Scrubber Control Register" hexmask.long.word 0x0 8.--20. 1. "SCRUB_INTERVAL,Scrub interval. (512 x scrub_interval) number of clock cycles between two scrub read commands. If set to 0 scrub commands are issued back-to-back. This mode of operation (scrub_interval=0) can typically be used for scrubbing the full.." bitfld.long 0x0 4.--6. "SCRUB_BURST,Scrub burst count. Determines the number of back-to-back scrub read commands that can be issued together when the controller is in one of the HW controlled low power modes with Sideband ECC both normal operation mode and low-power mode with.." "0,1,2,3,4,5,6,7" bitfld.long 0x0 2. "SCRUB_MODE,- scrub_mode:0 ECC scrubber performs reads - scrub_mode:1 ECC scrubber performs writes Programming Mode: Dynamic" "0,1" newline bitfld.long 0x0 1. "SCRUB_DURING_LOWPOWER,Continue scrubbing during low power. If set to 1 burst of scrubs is issued in hardware controlled low power modes. There are two such modes: automatically initiated by idleness or initiated by Hardware low power interface. If set.." "0,1" bitfld.long 0x0 0. "SCRUB_EN,Enables ECC scrubber. If set to 1 enables the scrubber to generate background read commands after the memories are initialized. If set to 0 disables the scrubber resets the address generator to 0 and clears the scrubber status. This bitfield.." "0,1" rgroup.long 0xB30++0x3 line.long 0x0 "SBRSTAT,Scrubber Status Register" bitfld.long 0x0 1. "SCRUB_DONE,Scrubber done. The controller sets this bit to 1 after full range of addresses are scrubbed once while scrub_interval is set to 0. Cleared if scrub_en is set to 0 (scrubber disabled) or scrub_interval is set to a non-zero value for normal.." "0,1" bitfld.long 0x0 0. "SCRUB_BUSY,Scrubber busy. The controller sets this bit to 1 when the scrubber logic has outstanding read commands being executed. Cleared when there are no active outstanding scrub reads in the system. Programming Mode: Dynamic" "0,1" group.long 0xB34++0x3 line.long 0x0 "SBRWDATA0,Scrubber Write Data Pattern0" hexmask.long 0x0 0.--31. 1. "SCRUB_PATTERN0,ECC Scrubber write data pattern for data bus[31:0] Programming Mode: Dynamic" group.long 0xB40++0xF line.long 0x0 "SBRSTART0,Scrubber Start Address Mask Register 0" hexmask.long 0x0 0.--31. 1. "SBR_ADDRESS_START_MASK_0,sbr_address_start_mask_0 holds the bits [31:0] of the starting address the ECC scrubber generates. The register must be programmed as explained in Address Configuration in ECC Scrub and Scrubber. The scrubber address registers.." line.long 0x4 "SBRSTART1,Scrubber Start Address Mask Register 1" hexmask.long.byte 0x4 0.--3. 1. "SBR_ADDRESS_START_MASK_1,sbr_address_start_mask_1 holds bits [MEMC_HIF_ADDR_WIDTH_MAX-1:32] of the starting address the ECC scrubber generates.The register must be programmed as explained in Address Configuration in ECC Scrub and Scrubber. The scrubber.." line.long 0x8 "SBRRANGE0,Scrubber Address Range Mask Register 0" hexmask.long 0x8 0.--31. 1. "SBR_ADDRESS_RANGE_MASK_0,sbr_address_range_mask_0 holds the bits [31:0] of the scrubber address range mask. The scrubber address range mask limits the address range that the ECC scrubber can generate.The register must be programmed as explained in.." line.long 0xC "SBRRANGE1,Scrubber Address Range Mask Register 1" hexmask.long.byte 0xC 0.--3. 1. "SBR_ADDRESS_RANGE_MASK_1,sbr_address_range_mask_1 holds the bits [MEMC_HIF_ADDR_WIDTH_MAX-1:32] of the scrubber address range mask. The scrubber address range mask limits the address range that the ECC scrubber can generate.The register must be.." rgroup.long 0xBF8++0x7 line.long 0x0 "UMCTL2_VER_NUMBER,UMCTL2 Version Number Register" hexmask.long 0x0 0.--31. 1. "VER_NUMBER,Indicates the Device Version Number value. Programming Mode: Static" line.long 0x4 "UMCTL2_VER_TYPE,UMCTL2 Version Type Register" hexmask.long 0x4 0.--31. 1. "VER_TYPE,Indicates the Device Version Type value. Programming Mode: Static" tree.end tree "UMCTL2_REGS_FREQ1 (uMCTL2 DDRC FREQ1 Registers)" base ad:0x8192 group.long 0x20++0x7 line.long 0x0 "DERATEEN,[FREQ1] Temperature Derate Enable Register" bitfld.long 0x0 12. "DERATE_MR4_TUF_DIS,Disables use of MR4 TUF flag (MR4[7]) bit. - 0 - Use MR4 TUF flag (MR4[7]) - 1 - Do not use MR4 TUF Flag (MR4[7]) For LPDDR4 it is recommended to set this register to 1. For LPDDR2 and LPDDR3 contact your memory vendor for.." "Use MR4 TUF flag,Do not use MR4 TUF Flag" newline bitfld.long 0x0 8.--10. "RC_DERATE_VALUE,Derate value of tRC for LPDDR4. - 0 - Derating uses +1 - 1 - Derating uses +2 - 2 - Derating uses +3 - 3 - Derating uses +4 Present only in designs configured to support LPDDR4. The required cycles for derating can be determined by.." "Derating uses +1,Derating uses +2,Derating uses +3,Derating uses +4,?,?,?,?" newline hexmask.long.byte 0x0 4.--7. 1. "DERATE_BYTE,This bit indicates which byte of the MRR data is used for derating. The maximum valid value depends on MEMC_DRAM_TOTAL_DATA_WIDTH. Present only in designs configured to support LPDDR2/LPDDR3/LPDDR4. Programming Mode: Static" newline bitfld.long 0x0 1.--2. "DERATE_VALUE,Derate value. - 0 - Derating uses +1 - 1 - Derating uses +2 Present only in designs configured to support LPDDR2/LPDDR3/LPDDR4. Set to 0 for all LPDDR2 speed grades as derating value of +1.875 ns is less than a core_ddrc_core_clk period. For.." "Derating uses +1,Derating uses +2,?,?" newline bitfld.long 0x0 0. "DERATE_ENABLE,Enables derating. - 0 - Timing parameter derating is disabled - 1 - Timing parameter derating is enabled using MR4 read value Present only in designs configured to support LPDDR2/LPDDR3/LPDDR4. This field must be set to '0' for.." "Timing parameter derating is disabled,Timing parameter derating is enabled using MR4.." line.long 0x4 "DERATEINT,[FREQ1] Temperature Derate Interval Register" hexmask.long 0x4 0.--31. 1. "MR4_READ_INTERVAL,Interval between two MR4 reads used to derate the timing parameters. Present only in designs configured to support LPDDR2/LPDDR3/LPDDR4. This register must not be set to zero. Unit: DFI clock cycles. Programming Mode: Static" group.long 0x34++0x3 line.long 0x0 "PWRTMG,[FREQ1] Low Power Timing Register" hexmask.long.byte 0x0 16.--23. 1. "SELFREF_TO_X32,After this many clocks of the DDRC command channel being idle the uMCTL2 automatically puts the SDRAM into self-refresh. The DDRC command channel is considered idle when there are no HIF commands outstanding. This must be enabled in the.." newline hexmask.long.byte 0x0 8.--15. 1. "T_DPD_X4096,Minimum deep power-down time. For mDDR value from the JEDEC specification is 0 as mDDR exits from deep power-down mode immediately after PWRCTL.deeppowerdown_en is de-asserted. For LPDDR2/LPDDR3 value from the JEDEC specification is 500us." newline hexmask.long.byte 0x0 0.--4. 1. "POWERDOWN_TO_X32,After this many clocks of the DDRC command channel being idle the uMCTL2 automatically puts the SDRAM into power-down. The DDRC command channel is considered idle when there are no HIF commands outstanding. This must be enabled in the.." group.long 0x50++0x3 line.long 0x0 "RFSHCTL0,[FREQ1] Refresh Control Register 0" hexmask.long.byte 0x0 20.--23. 1. "REFRESH_MARGIN,Threshold value in number of DFI clock cycles before the critical refresh or page timer expires. A critical refresh is to be issued before this threshold is reached. It is recommended that this not be changed from the default value.." newline hexmask.long.byte 0x0 12.--16. 1. "REFRESH_TO_X1_X32,If the refresh timer (tRFCnom also known as tREFI) has expired at least once then a speculative refresh may be performed. A speculative refresh is a refresh performed at a time when refresh would be useful. When the SDRAM bus is idle.." newline hexmask.long.byte 0x0 4.--9. 1. "REFRESH_BURST,The programmed value + 1 is the number of refresh timeouts that is allowed to accumulate before traffic is blocked and the refreshes are forced to execute. Closing pages to perform a refresh is a one-time penalty that must be paid for each.." newline bitfld.long 0x0 2. "PER_BANK_REFRESH,- 1 - Per bank refresh - 0 - All bank refresh Per bank refresh allows traffic to flow to other banks. Per bank refresh is not supported by all LPDDR2 devices but must be supported by all LPDDR3/LPDDR4 devices. Present only in designs.." "All bank refresh,Per bank refresh" group.long 0x64++0x7 line.long 0x0 "RFSHTMG,[FREQ1] Refresh Timing Register" bitfld.long 0x0 31. "T_RFC_NOM_X1_SEL,Specifies whether the RFSHTMG.t_rfc_nom_x1_x32 and RFSHCTL0.refresh_to_x1_x32 register values are x1 or x32. - 0 - x32 register values are used - 1 - x1 register values are used This applies only when per-bank refresh is enabled.." "x32 register values are used,x1 register values are used" newline hexmask.long.word 0x0 16.--27. 1. "T_RFC_NOM_X1_X32,Average time interval between refreshes per rank (Specification: 7.8us for DDR2 DDR3 and DDR4. See JEDEC specification for mDDR LPDDR2 LPDDR3 and LPDDR4). When the controller is operating in 1:1 mode set this register to.." newline bitfld.long 0x0 15. "LPDDR3_TREFBW_EN,Used only when LPDDR3 memory type is connected. Should only be changed when uMCTL2 is in reset. Specifies whether to use the tREFBW parameter (required by some LPDDR3 devices which comply with earlier versions of the LPDDR3 JEDEC.." "tREFBW parameter not used,tREFBW parameter used" newline hexmask.long.word 0x0 0.--9. 1. "T_RFC_MIN,tRFC (min): Minimum time from refresh to refresh or activate. When the controller is operating in 1:1 mode t_rfc_min must be set to RoundUp(tRFCmin/tCK). When the controller is operating in 1:2 mode t_rfc_min must be set to.." line.long 0x4 "RFSHTMG1,[FREQ1] Refresh Timing Register1" hexmask.long.byte 0x4 16.--23. 1. "T_PBR2PBR,LPDDR4:tpbR2pbR. Per-bank refresh to Per-bank refresh different bank Time. When the controller is operating in 1:1 frequency ratio mode program this to RoundUp(tpbR2pbR/tCK). When the controller is operating in 1:2 frequency ratio mode.." repeat 4. (list 0x3 0x4 0x6 0x7 )(list 0x0 0x4 0xC 0x10 ) group.long ($2+0xDC)++0x3 line.long 0x0 "INIT$1,[FREQ1] SDRAM Initialization Register 3" hexmask.long.word 0x0 16.--31. 1. "MR,DDR2:Indicates the value to write to MR register. Bit 8 is for DLL and the setting here is ignored. The uMCTL2 sets this bit appropriately. DDR3/DDR4: Value loaded into MR0 register. mDDR: Value to write to MR register. LPDDR2/LPDDR3/LPDDR4 - Value to.." newline hexmask.long.word 0x0 0.--15. 1. "EMR,DDR2: Indicates the value to write to EMR register. Bits 9:7 are for OCD and the setting in this register is ignored. The uMCTL2 sets those bits appropriately. DDR3/DDR4: Value to write to MR1 register Set bit 7 to 0. mDDR: Value to write to EMR.." repeat.end group.long 0xF4++0x3 line.long 0x0 "RANKCTL,[FREQ1] Rank Control Register" bitfld.long 0x0 26. "DIFF_RANK_WR_GAP_MSB,Only present for multi-rank configurations. 1-bit extension to be used when RANKCTL.diff_rank_wr_gap field needs to be set to a value greater than 0xF. Programming Mode: Quasi-dynamic Group 2" "?,bit extension to be used when RANKCTL" newline bitfld.long 0x0 24. "DIFF_RANK_RD_GAP_MSB,Only present for multi-rank configurations. 1-bit extension to be used when RANKCTL.diff_rank_rd_gap field needs to be set to a value greater than 0xF. Programming Mode: Quasi-dynamic Group 2" "?,bit extension to be used when RANKCTL" newline hexmask.long.byte 0x0 12.--15. 1. "MAX_RANK_WR,Only present for multi-rank configurations. Background: Writes to the same rank can be performed back-to-back. Writes to different ranks require additional gap dictated by the register RANKCTL.diff_rank_wr_gap. This is to avoid possible data.." newline hexmask.long.byte 0x0 8.--11. 1. "DIFF_RANK_WR_GAP,Only present for multi-rank configurations. Indicates the number of clocks of gap in data responses when performing consecutive writes to different ranks. This is used to switch the delays in the PHY to match the rank requirements. This.." newline hexmask.long.byte 0x0 4.--7. 1. "DIFF_RANK_RD_GAP,Only present for multi-rank configurations. Indicates the number of clocks of gap in data responses when performing consecutive reads to different ranks. This is used to switch the delays in the PHY to match the rank requirements. This.." newline hexmask.long.byte 0x0 0.--3. 1. "MAX_RANK_RD,Only present for multi-rank configurations. Background: Reads to the same rank can be performed back-to-back. Reads to different ranks require additional gap dictated by the register RANKCTL.diff_rank_rd_gap. This is to avoid possible data.." group.long 0x100++0x3F line.long 0x0 "DRAMTMG0,[FREQ1] SDRAM Timing Register 0" hexmask.long.byte 0x0 24.--30. 1. "WR2PRE,Specifies the minimum time between write and precharge to same bank. Specifications: WL + BL/2 + tWR = approximately 8 cycles + 15 ns = 14 clocks @400MHz and less for lower frequencies. where: - WL - Write latency - BL - Burst length. This must.." newline hexmask.long.byte 0x0 16.--21. 1. "T_FAW,tFAW - valid only when 8 or more banks(or banks x bank groups) are present. In 8-bank design at most 4 banks must be activated in a rolling window of tFAW cycles. When the controller is operating in 1:2 frequency ratio mode program this to.." newline hexmask.long.byte 0x0 8.--14. 1. "T_RAS_MAX,tRAS(max) - Specifies the maximum time between activate and precharge to same bank. This is the maximum time that a page can be kept open Minimum value of this register is 1. Zero is invalid. When the controller is operating in 1:1 frequency.." newline hexmask.long.byte 0x0 0.--5. 1. "T_RAS_MIN,tRAS(min) - Specifies the minimum time between activate and precharge to the same bank. When the controller is operating in 1:2 frequency mode 1T mode program this to tRAS(min)/2. No rounding up. When the controller is operating in 1:2.." line.long 0x4 "DRAMTMG1,[FREQ1] SDRAM Timing Register 1" hexmask.long.byte 0x4 16.--20. 1. "T_XP,tXP - Specifies the minimum time after power-down exit to any operation. For DDR3 this must be programmed to tXPDLL if slow powerdown exit is selected in MR0[12]. If C/A parity for DDR4 is used set to (tXP+PL) instead. If LPDDR4 is selected and.." newline hexmask.long.byte 0x4 8.--13. 1. "RD2PRE,tRTP - Specifies the minimum time from read to precharge of same bank. - DDR2 - tAL + BL/2 + max(tRTP 2) - 2 - DDR3 - tAL + max (tRTP 4) - DDR4 - Max of following two equations: tAL + max (tRTP 4) or RL + BL/2 - tRP (*). - mDDR - BL/2 - LPDDR2.." newline hexmask.long.byte 0x4 0.--6. 1. "T_RC,tRC - Specifies the minimum time between activates to same bank. When the controller is operating in 1:2 frequency ratio mode program this to (tRC/2) and round up to next integer value. Unit: DFI clock cycles. Programming Mode: Quasi-dynamic Group.." line.long 0x8 "DRAMTMG2,[FREQ1] SDRAM Timing Register 2" hexmask.long.byte 0x8 24.--29. 1. "WRITE_LATENCY,Set this field to WL. Indicates the Time from write command to write data on SDRAM interface. This must be set to WL. For mDDR it must be set to 1. Note that depending on the PHY if using RDIMM/LRDIMM it might be necessary to adjust the.." newline hexmask.long.byte 0x8 16.--21. 1. "READ_LATENCY,Set this field to RL. Indicates the time from read command to read data on SDRAM interface. This must be set to RL. Note that depending on the PHY if using RDIMM/LRDIMM it might be necessary to adjust the value of RL to compensate for the.." newline hexmask.long.byte 0x8 8.--13. 1. "RD2WR,DDR2/3/mDDR: RL + BL/2 + 2 - WL DDR4: RL + BL/2 + 1 + WR_PREAMBLE - WL LPDDR2/LPDDR3: RL + BL/2 + RU(tDQSCKmax/tCK) + 1 - WL LPDDR4(DQ ODT is Disabled): RL + BL/2 + RU(tDQSCKmax/tCK) + WR_PREAMBLE + RD_POSTAMBLE - WL LPDDR4(DQ ODT is Enabled): RL +.." newline hexmask.long.byte 0x8 0.--5. 1. "WR2RD,DDR4: CWL + PL + BL/2 + tWTR_L LPDDR2/3/4: WL + BL/2 + tWTR + 1 Others: CWL + BL/2 + tWTR In DDR4 minimum time from write command to read command for same bank group. In others minimum time from write command to read command. Includes time for.." line.long 0xC "DRAMTMG3,[FREQ1] SDRAM Timing Register 3" hexmask.long.word 0xC 20.--29. 1. "T_MRW,Indicates the time to wait after a mode register write or read (MRW or MRR). Present only in designs configured to support LPDDR2 LPDDR3 or LPDDR4. LPDDR2 typically requires value of 5. LPDDR3 typically requires value of 10. LPDDR4: Set this to.." newline hexmask.long.byte 0xC 12.--17. 1. "T_MRD,tMRD- Indicates the number of cycles to wait after a mode register write or read. Depending on the connected SDRAM tMRD represents: - DDR2/mDDR: Time from MRS to any command - DDR3/4: Time from MRS to MRS command - LPDDR2: not used - LPDDR3/4:.." newline hexmask.long.word 0xC 0.--9. 1. "T_MOD,tMOD - Parameter used only in DDR3 and DDR4. Indicates the number of cycles between load mode command and following non-load mode command. If C/A parity for DDR4 is used set to tMOD_PAR(tMOD+PL) instead. If CAL mode is enabled.." line.long 0x10 "DRAMTMG4,[FREQ1] SDRAM Timing Register 4" hexmask.long.byte 0x10 24.--28. 1. "T_RCD,tRCD - tAL: Indicates the minimum time from activate to read or write command to same bank. When the controller is operating in 1:2 frequency ratio mode program this to ((tRCD - tAL)/2) and round it up to the next integer value. Minimum value.." newline hexmask.long.byte 0x10 16.--19. 1. "T_CCD,DDR4: tCCD_L: This is the minimum time between two reads or two writes for same bank group. Others: tCCD: This is the minimum time between two reads or two writes. When the controller is operating in 1:2 frequency ratio mode program this to.." newline hexmask.long.byte 0x10 8.--11. 1. "T_RRD,DDR4: tRRD_L: This is the minimum time between activates from bank 'a' to bank 'b' for same bank group. Others: tRRD: Minimum time between activates from bank 'a' to bank 'b' When the controller is operating in 1:2 frequency ratio mode program.." newline hexmask.long.byte 0x10 0.--4. 1. "T_RP,tRP: Indicates the minimum time from single-bank precharge to activate of same bank. When the controller is operating in 1:1 frequency ratio mode t_rp must be set to RoundUp(tRP/tCK). When the controller is operating in 1:2 frequency ratio mode.." line.long 0x14 "DRAMTMG5,[FREQ1] SDRAM Timing Register 5" hexmask.long.byte 0x14 24.--27. 1. "T_CKSRX,This is the time before self-refresh Exit that CK is maintained as a valid clock before issuing SRX. Specifies the clock stable time before SRX. Recommended settings: - mDDR - 1 - LPDDR2 - 2 - LPDDR3 - 2 - LPDDR4 - tCKCKEH - DDR2 - 1 - DDR3 -.." newline hexmask.long.byte 0x14 16.--19. 1. "T_CKSRE,This is the time after self-refresh Down Entry that CK is maintained as a valid clock. Specifies the clock disable delay after SRE. Recommended settings: - mDDR - 0 - LPDDR2 - 2 - LPDDR3 - 2 - LPDDR4 - tCKELCK - DDR2 - 1 - DDR3 - Max (10 ns 5.." newline hexmask.long.byte 0x14 8.--13. 1. "T_CKESR,Indicates the minimum CKE low width for self-refresh or self-refresh power down entry to exit timing in memory clock cycles. Recommended settings: - mDDR - tRFC - LPDDR2 - tCKESR - LPDDR3 - tCKESR - LPDDR4 - max(tCKE tSR) - DDR2 - tCKE - DDR3 -.." newline hexmask.long.byte 0x14 0.--4. 1. "T_CKE,Indicates the minimum number of cycles of CKE HIGH/LOW during power-down and self-refresh. - LPDDR2/LPDDR3 mode - Set this to the larger of tCKE or tCKESR - LPDDR4 mode - Set this to the larger of tCKE or tSR - Non-LPDDR2/non-LPDDR3/non-LPDDR4.." line.long 0x18 "DRAMTMG6,[FREQ1] SDRAM Timing Register 6" hexmask.long.byte 0x18 24.--27. 1. "T_CKDPDE,This is the time after Deep Power Down Entry that CK is maintained as a valid clock. Specifies the clock disable delay after DPDE. Recommended settings: - mDDR: 0 - LPDDR2: 2 - LPDDR3: 2 When the controller is operating in 1:2 frequency ratio.." newline hexmask.long.byte 0x18 16.--19. 1. "T_CKDPDX,This is the time before Deep Power Down Exit that CK is maintained as a valid clock before issuing DPDX. Specifies the clock stable time before DPDX. Recommended settings: - mDDR - 1 - LPDDR2 - 2 - LPDDR3 - 2 When the controller is operating in.." newline hexmask.long.byte 0x18 0.--3. 1. "T_CKCSX,This is the time before Clock Stop Exit that CK is maintained as a valid clock before issuing Clock Stop Exit. Specifies the clock stable time before next command after Clock Stop Exit. Recommended settings: - mDDR - 1 - LPDDR2 - tXP + 2 - LPDDR3.." line.long 0x1C "DRAMTMG7,[FREQ1] SDRAM Timing Register 7" hexmask.long.byte 0x1C 8.--11. 1. "T_CKPDE,This is the time after Power Down Entry that CK is maintained as a valid clock. Specifies the clock disable delay after PDE. Recommended settings: - mDDR - 0 - LPDDR2 - 2 - LPDDR3 - 2 - LPDDR4 - tCKELCK When using DDR2/3/4 SDRAM this register.." newline hexmask.long.byte 0x1C 0.--3. 1. "T_CKPDX,This is the time before Power Down Exit that CK is maintained as a valid clock before issuing PDX. Specifies the clock stable time before PDX. Recommended settings: - mDDR - 0 - LPDDR2 - 2 - LPDDR3 - 2 - LPDDR4 - tCKCKEH When using DDR2/3/4 SDRAM.." line.long 0x20 "DRAMTMG8,[FREQ1] SDRAM Timing Register 8" hexmask.long.byte 0x20 24.--30. 1. "T_XS_FAST_X32,tXS_FAST: Exit self-refresh to ZQCL ZQCS and MRS (only CL WR RTP and Geardown mode). When the controller is operating in 1:2 frequency ratio mode program this to the previous value divided by 2 and round up to next integer value. Note:.." newline hexmask.long.byte 0x20 16.--22. 1. "T_XS_ABORT_X32,tXS_ABORT: Exit self-refresh to commands not requiring a locked DLL in self-refresh Abort. When the controller is operating in 1:2 frequency ratio mode program this to the previous value divided by 2 and round up to next integer value." newline hexmask.long.byte 0x20 8.--14. 1. "T_XS_DLL_X32,tXSDLL: Exit self-refresh to commands requiring a locked DLL. When the controller is operating in 1:2 frequency ratio mode program this to the previous value divided by 2 and round up to next integer value. Note: Used only for DDR2 DDR3.." newline hexmask.long.byte 0x20 0.--6. 1. "T_XS_X32,tXS: Exit self-refresh to commands not requiring a locked DLL. When the controller is operating in 1:2 frequency ratio mode program this to the previous value divided by 2 and round up to next integer value. Note: Used only for DDR2 DDR3 and.." line.long 0x24 "DRAMTMG9,[FREQ1] SDRAM Timing Register 9" bitfld.long 0x24 30. "DDR4_WR_PREAMBLE,DDR4 Write preamble mode. - 0 - 1tCK preamble - 1 - 2tCK preamble Present only with MEMC_FREQ_RATIO=2. Programming Mode: Quasi-dynamic Group 2 Group 4" "0,1" newline bitfld.long 0x24 16.--18. "T_CCD_S,tCCD_S: This is the minimum time between two reads or two writes for different bank group. For bank switching (from bank 'a' to bank 'b') the minimum time is this value + 1. When the controller is operating in 1:2 frequency ratio mode program.." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x24 8.--11. 1. "T_RRD_S,tRRD_S: This is the minimum time between activates from bank 'a' to bank 'b' for different bank group. When the controller is operating in 1:2 frequency ratio mode program this to (tRRD_S/2) and round it up to the next integer value. Present.." newline hexmask.long.byte 0x24 0.--5. 1. "WR2RD_S,CWL + PL + BL/2 + tWTR_S Minimum time from write command to read command for different bank group. Includes time for bus turnaround recovery times and all per-bank per-rank and global constraints. Present only in designs configured to support.." line.long 0x28 "DRAMTMG10,[FREQ1] SDRAM Timing Register 10" hexmask.long.byte 0x28 16.--20. 1. "T_SYNC_GEAR,Indicates the time between MRS command and the sync pulse time. This must be even number of clocks. For DDR4-2666 and DDR4-3200 this parameter is defined as tMOD(min)+4nCK tMOD(min) is greater of 24nCK or 15ns 15ns / .625ns = 24 Max value.." newline hexmask.long.byte 0x28 8.--12. 1. "T_CMD_GEAR,Indicates a sync pulse to first valid command. For DDR4-2666 and DDR4-3200 this parameter is defined as tMOD(min) tMOD(min) is greater of 24nCK or 15ns 15ns / .625ns = 24 Max value for this register is 24 When the controller is operating in.." newline bitfld.long 0x28 2.--3. "T_GEAR_SETUP,Indicates the geardown setup time. Minimum value of this register is 1. Zero is invalid. For DDR4-2666 and DDR4-3200 this parameter is defined as 2 clks When the controller is operating in 1:2 frequency ratio mode program this to.." "0,1,2,3" newline bitfld.long 0x28 0.--1. "T_GEAR_HOLD,Indicates the geardown hold time. Minimum value of this register is 1. Zero is invalid. For DDR4-2666 and DDR4-3200 this parameter is defined as 2 clks When the controller is operating in 1:2 frequency ratio mode program this to.." "0,1,2,3" line.long 0x2C "DRAMTMG11,[FREQ1] SDRAM Timing Register 11" hexmask.long.byte 0x2C 24.--30. 1. "POST_MPSM_GAP_X32,tXMPDLL: This is the minimum Exit MPSM to commands requiring a locked DLL. When the controller is operating in 1:2 frequency ratio mode program this to (tXMPDLL/2) and round it up to the next integer value. Present only in designs.." newline hexmask.long.byte 0x2C 16.--20. 1. "T_MPX_LH,tMPX_LH: This is the minimum CS_n Low hold time to CKE rising edge. When the controller is operating in 1:2 frequency ratio mode program this to RoundUp(tMPX_LH/2)+1. Present only in designs configured to support DDR4. Unit: DFI clock cycles." newline bitfld.long 0x2C 8.--9. "T_MPX_S,tMPX_S: This is the minimum time CS setup time to CKE. When the controller is operating in 1:2 frequency ratio mode program this to (tMPX_S/2) and round it up to the next integer value. Present only in designs configured to support DDR4. Unit:.." "0,1,2,3" newline hexmask.long.byte 0x2C 0.--4. 1. "T_CKMPE,tCKMPE: This is the minimum valid clock requirement after MPSM entry. Present only in designs configured to support DDR4. When the controller is operating in 1:2 frequency ratio mode divide the value calculated using the previous equation by 2.." line.long 0x30 "DRAMTMG12,[FREQ1] SDRAM Timing Register 12" hexmask.long.byte 0x30 24.--29. 1. "T_WR_MPR,This bit is used only in DDR4. Cycles between MPR Write and other command. Set this to tMOD + AL (or tMOD + PL + AL if C/A parity is also used). When the controller is operating in 1:2 frequency ratio mode program this to (tWR_MPR/2) and round.." newline bitfld.long 0x30 16.--17. "T_CMDCKE,tCMDCKE: Indicates the delay from valid command to CKE input LOW. Set this to the larger of tESCKE or tCMDCKE When the controller is operating in 1:2 frequency ratio mode program this to (max(tESCKE tCMDCKE)/2) and round it up to the next.." "0,1,2,3" newline hexmask.long.byte 0x30 0.--4. 1. "T_MRD_PDA,tMRD_PDA: This is the Mode Register Set command cycle time in PDA mode. When the controller is operating in 1:2 frequency ratio mode program this to (tMRD_PDA/2) and round it up to the next integer value. Unit: DFI clock cycles. Programming.." line.long 0x34 "DRAMTMG13,[FREQ1] SDRAM Timing Register 13" hexmask.long.byte 0x34 24.--30. 1. "ODTLOFF,LPDDR4: ODTLoff: This is the latency from CAS-2 command to ODToff reference. When the controller is operating in 1:2 frequency ratio mode program this to (ODTLoff/2) and round it up to the next integer value. Unit: DFI clock cycles. Programming.." newline hexmask.long.byte 0x34 16.--21. 1. "T_CCD_MW,LPDDR4: tCCDMW: This is the minimum time from write or masked write to masked write command for same bank. When the controller is operating in 1:2 frequency ratio mode program this to (tCCDMW/2) and round it up to the next integer value. Unit:.." newline bitfld.long 0x34 0.--2. "T_PPD,LPDDR4: tPPD: This is the minimum time from precharge to precharge command. When the controller is operating in 1:2 frequency ratio mode program this to (tPPD/2) and round it up to the next integer value. Unit: DFI clock cycles. Programming Mode:.." "?,?,?,?,tPPD: This is the minimum time from precharge to..,?,?,?" line.long 0x38 "DRAMTMG14,[FREQ1] SDRAM Timing Register 14" hexmask.long.word 0x38 0.--11. 1. "T_XSR,tXSR: This is the exit self-refresh to any command. When the controller is operating in 1:2 frequency ratio mode program this to the previous value divided by 2 and round up to next integer value. The value 0xfff is illegal for this register.." line.long 0x3C "DRAMTMG15,[FREQ1] SDRAM Timing Register 15" bitfld.long 0x3C 31. "EN_DFI_LP_T_STAB,- 1 - Enable using tSTAB when exiting DFI LP. This must be set when the PHY is stopping the clock during DFI LP to save maximum power. - 0 - Disable using tSTAB when exiting DFI LP. Programming Mode: Quasi-dynamic Group 2 Group 4" "Disable using tSTAB when exiting DFI LP,Enable using tSTAB when exiting DFI LP" newline hexmask.long.byte 0x3C 0.--7. 1. "T_STAB_X32,tSTAB: Stabilization time. It is required in the following two cases for DDR3/DDR4 RDIMM: - When exiting power saving mode if the clock is stopped after re-enabling it the clock must be stable for a time specified by tSTAB - In the case of.." group.long 0x180++0x3 line.long 0x0 "ZQCTL0,[FREQ1] ZQ Control Register 0" bitfld.long 0x0 31. "DIS_AUTO_ZQ,- 1 - Disable uMCTL2 generation of ZQCS/MPC(ZQ calibration) command. Register DBGCMD.zq_calib_short can be used instead to issue ZQ calibration request from APB module - 0 - Internally generate ZQCS/MPC(ZQ calibration) commands based on.." "Internally generate ZQCS/MPC,Disable uMCTL2 generation of ZQCS/MPC" newline bitfld.long 0x0 30. "DIS_SRX_ZQCL,- 1 - Disable issuing of ZQCL/MPC(ZQ calibration) command at self-refresh/SR-Powerdown exit. Only applicable when run in DDR3 or DDR4 or LPDDR2 or LPDDR3 or LPDDR4 mode - 0 - Enable issuing of ZQCL/MPC(ZQ calibration) command at.." "Enable issuing of ZQCL/MPC,Disable issuing of ZQCL/MPC" newline bitfld.long 0x0 29. "ZQ_RESISTOR_SHARED,- 1 - Denotes that ZQ resistor is shared between ranks. Means ZQinit/ZQCL/ZQCS/MPC(ZQ calibration) commands are sent to one rank at a time with tZQinit/tZQCL/tZQCS/tZQCAL/tZQLAT timing met between commands so that commands to different.." "ZQ resistor is not shared,Denotes that ZQ resistor is shared between ranks" newline bitfld.long 0x0 28. "DIS_MPSMX_ZQCL,- 1 - Disable issuing of ZQCL command at Maximum Power Saving Mode exit. Only applicable when run in DDR4 mode - 0 - Enable issuing of ZQCL command at Maximum Power Saving Mode exit. Only applicable when run in DDR4 mode This is only.." "Enable issuing of ZQCL command at Maximum Power..,Disable issuing of ZQCL command at Maximum Power.." newline hexmask.long.word 0x0 16.--26. 1. "T_ZQ_LONG_NOP,tZQoper for DDR3/DDR4 tZQCL for LPDDR2/LPDDR3 tZQCAL for LPDDR4: Number of DFI clock cycles of NOP required after a ZQCL (ZQ calibration long)/MPC(ZQ Start) command is issued to SDRAM. When the controller is operating in 1:2 frequency.." newline hexmask.long.word 0x0 0.--9. 1. "T_ZQ_SHORT_NOP,tZQCS for DDR3/DD4/LPDDR2/LPDDR3 tZQLAT for LPDDR4: Number of DFI clock cycles of NOP required after a ZQCS (ZQ calibration short)/MPC(ZQ Latch) command is issued to SDRAM. When the controller is operating in 1:2 frequency ratio mode.." group.long 0x190++0x7 line.long 0x0 "DFITMG0,[FREQ1] DFI Timing Register 0" hexmask.long.byte 0x0 24.--28. 1. "DFI_T_CTRL_DELAY,Specifies the number of DFI clock cycles after an assertion or de-assertion of the DFI control signals that the control signals at the PHY-DRAM interface reflect the assertion or de-assertion. If the DFI clock and the memory clock are.." newline bitfld.long 0x0 23. "DFI_RDDATA_USE_DFI_PHY_CLK,Defines whether dfi_rddata_en/dfi_rddata/dfi_rddata_valid is generated using HDR (DFI clock) or SDR (DFI PHY clock) values. Selects whether value in DFITMG0.dfi_t_rddata_en is in terms of HDR (DFI clock) or SDR (DFI PHY clock).." "Else,?" newline hexmask.long.byte 0x0 16.--22. 1. "DFI_T_RDDATA_EN,Time from the assertion of a read command on the DFI interface to the assertion of the dfi_rddata_en signal. Refer to PHY specification for correct value. This corresponds to the DFI parameter trddata_en. Note that depending on the PHY.." newline bitfld.long 0x0 15. "DFI_WRDATA_USE_DFI_PHY_CLK,Defines whether dfi_wrdata_en/dfi_wrdata/dfi_wrdata_mask is generated using HDR (DFI clock) or SDR (DFI PHY clock) values. Selects whether value in DFITMG0.dfi_tphy_wrlat is in terms of HDR (DFI clock) or SDR (DFI PHY clock).." "Else,?" newline hexmask.long.byte 0x0 8.--13. 1. "DFI_TPHY_WRDATA,Specifies the number of clock cycles between when dfi_wrdata_en is asserted to when the associated write data is driven on the dfi_wrdata signal. This corresponds to the DFI timing parameter tphy_wrdata. For more information on correct.." newline hexmask.long.byte 0x0 0.--5. 1. "DFI_TPHY_WRLAT,Write latency. Number of clocks from the write command to write data enable (dfi_wrdata_en). This corresponds to the DFI timing parameter tphy_wrlat. Refer to PHY specification for correct value.Note that depending on the PHY if using.." line.long 0x4 "DFITMG1,[FREQ1] DFI Timing Register 1" hexmask.long.byte 0x4 28.--31. 1. "DFI_T_CMD_LAT,Specifies the number of DFI PHY clock cycles between when the dfi_cs signal is asserted and when the associated command is driven. This field is used for CAL mode must be set to '0' or tCAL which matches the CAL mode register setting in.." newline bitfld.long 0x4 24.--25. "DFI_T_PARIN_LAT,Specifies the number of DFI PHY clock cycles between when the dfi_cs signal is asserted and when the associated dfi_parity_in signal is driven. Unit: DFI PHY clock cycles. Programming Mode: Quasi-dynamic Group 4" "0,1,2,3" newline hexmask.long.byte 0x4 16.--20. 1. "DFI_T_WRDATA_DELAY,Specifies the number of DFI clock cycles between when the dfi_wrdata_en signal is asserted and when the corresponding write data transfer is completed on the DRAM bus. This corresponds to the DFI timing parameter twrdata_delay. For.." newline hexmask.long.byte 0x4 8.--12. 1. "DFI_T_DRAM_CLK_DISABLE,Specifies the number of DFI clock cycles from the assertion of the dfi_dram_clk_disable signal on the DFI until the clock to the DRAM memory devices at the PHY-DRAM boundary maintains a low value. If the DFI clock and the memory.." newline hexmask.long.byte 0x4 0.--4. 1. "DFI_T_DRAM_CLK_ENABLE,Specifies the number of DFI clock cycles from the de-assertion of the dfi_dram_clk_disable signal on the DFI until the first valid rising edge of the clock to the DRAM memory devices at the PHY-DRAM boundary. If the DFI clock and.." group.long 0x1B4++0x7 line.long 0x0 "DFITMG2,[FREQ1] DFI Timing Register 2" hexmask.long.byte 0x0 8.--14. 1. "DFI_TPHY_RDCSLAT,specifies the number of DFI PHY clock cycles between when a read command is sent on the DFI control interface and when the associated dfi_rddata_cs signal is asserted. This corresponds to the DFI timing parameter tphy_rdcslat. Refer to.." newline hexmask.long.byte 0x0 0.--5. 1. "DFI_TPHY_WRCSLAT,Specifies the number of DFI PHY clock cycles between when a write command is sent on the DFI control interface and when the associated dfi_wrdata_cs signal is asserted. This corresponds to the DFI timing parameter tphy_wrcslat. For more.." line.long 0x4 "DFITMG3,[FREQ1] DFI Timing Register 3" hexmask.long.byte 0x4 0.--4. 1. "DFI_T_GEARDOWN_DELAY,The delay from dfi_geardown_en assertion to the time of the PHY being ready to receive commands. Refer to PHY specification for correct value. When the controller is operating in 1:2 frequency ratio mode program this to.." group.long 0x240++0x3 line.long 0x0 "ODTCFG,[FREQ1] ODT Configuration Register" hexmask.long.byte 0x0 24.--27. 1. "WR_ODT_HOLD,DFI PHY clock cycles to hold ODT for a write command. The minimum supported value is 2. Recommended values: DDR2: - BL8 - 0x5 (DDR2-400/533/667) 0x6 (DDR2-800) 0x7 (DDR2-1066) - BL4 - 0x3 (DDR2-400/533/667) 0x4 (DDR2-800) 0x5 (DDR2-1066).." newline hexmask.long.byte 0x0 16.--20. 1. "WR_ODT_DELAY,Indicates the delay in DFI PHY clock cycles from issuing a write command to setting ODT values associated with that command. ODT setting must remain constant for the entire time that DQS is driven by the uMCTL2. Recommended values: DDR2: -.." newline hexmask.long.byte 0x0 8.--11. 1. "RD_ODT_HOLD,DFI PHY clock cycles to hold ODT for a read command. The minimum supported value is 2. Recommended values: DDR2: - BL8 - 0x6 (not DDR2-1066) 0x7 (DDR2-1066) - BL4 - 0x4 (not DDR2-1066) 0x5 (DDR2-1066) DDR3: - BL8 - 0x6 DDR4: - BL8 - 5 +.." newline hexmask.long.byte 0x0 2.--6. 1. "RD_ODT_DELAY,Indicates the delay in DFI PHY clock cycles from issuing a read command to setting ODT values associated with that command. ODT setting must remain constant for the entire time that DQS is driven by the uMCTL2. Recommended values: DDR2: -.." tree.end tree "UMCTL2_REGS_FREQ2 (uMCTL2 DDRC FERQ2 Registers)" base ad:0x12288 group.long 0x20++0x7 line.long 0x0 "DERATEEN,[FREQ2] Temperature Derate Enable Register" bitfld.long 0x0 12. "DERATE_MR4_TUF_DIS,Disables use of MR4 TUF flag (MR4[7]) bit. - 0 - Use MR4 TUF flag (MR4[7]) - 1 - Do not use MR4 TUF Flag (MR4[7]) For LPDDR4 it is recommended to set this register to 1. For LPDDR2 and LPDDR3 contact your memory vendor for.." "Use MR4 TUF flag,Do not use MR4 TUF Flag" newline bitfld.long 0x0 8.--10. "RC_DERATE_VALUE,Derate value of tRC for LPDDR4. - 0 - Derating uses +1 - 1 - Derating uses +2 - 2 - Derating uses +3 - 3 - Derating uses +4 Present only in designs configured to support LPDDR4. The required cycles for derating can be determined by.." "Derating uses +1,Derating uses +2,Derating uses +3,Derating uses +4,?,?,?,?" newline hexmask.long.byte 0x0 4.--7. 1. "DERATE_BYTE,This bit indicates which byte of the MRR data is used for derating. The maximum valid value depends on MEMC_DRAM_TOTAL_DATA_WIDTH. Present only in designs configured to support LPDDR2/LPDDR3/LPDDR4. Programming Mode: Static" newline bitfld.long 0x0 1.--2. "DERATE_VALUE,Derate value. - 0 - Derating uses +1 - 1 - Derating uses +2 Present only in designs configured to support LPDDR2/LPDDR3/LPDDR4. Set to 0 for all LPDDR2 speed grades as derating value of +1.875 ns is less than a core_ddrc_core_clk period. For.." "Derating uses +1,Derating uses +2,?,?" newline bitfld.long 0x0 0. "DERATE_ENABLE,Enables derating. - 0 - Timing parameter derating is disabled - 1 - Timing parameter derating is enabled using MR4 read value Present only in designs configured to support LPDDR2/LPDDR3/LPDDR4. This field must be set to '0' for.." "Timing parameter derating is disabled,Timing parameter derating is enabled using MR4.." line.long 0x4 "DERATEINT,[FREQ2] Temperature Derate Interval Register" hexmask.long 0x4 0.--31. 1. "MR4_READ_INTERVAL,Interval between two MR4 reads used to derate the timing parameters. Present only in designs configured to support LPDDR2/LPDDR3/LPDDR4. This register must not be set to zero. Unit: DFI clock cycles. Programming Mode: Static" group.long 0x34++0x3 line.long 0x0 "PWRTMG,[FREQ2] Low Power Timing Register" hexmask.long.byte 0x0 16.--23. 1. "SELFREF_TO_X32,After this many clocks of the DDRC command channel being idle the uMCTL2 automatically puts the SDRAM into self-refresh. The DDRC command channel is considered idle when there are no HIF commands outstanding. This must be enabled in the.." newline hexmask.long.byte 0x0 8.--15. 1. "T_DPD_X4096,Minimum deep power-down time. For mDDR value from the JEDEC specification is 0 as mDDR exits from deep power-down mode immediately after PWRCTL.deeppowerdown_en is de-asserted. For LPDDR2/LPDDR3 value from the JEDEC specification is 500us." newline hexmask.long.byte 0x0 0.--4. 1. "POWERDOWN_TO_X32,After this many clocks of the DDRC command channel being idle the uMCTL2 automatically puts the SDRAM into power-down. The DDRC command channel is considered idle when there are no HIF commands outstanding. This must be enabled in the.." group.long 0x50++0x3 line.long 0x0 "RFSHCTL0,[FREQ2] Refresh Control Register 0" hexmask.long.byte 0x0 20.--23. 1. "REFRESH_MARGIN,Threshold value in number of DFI clock cycles before the critical refresh or page timer expires. A critical refresh is to be issued before this threshold is reached. It is recommended that this not be changed from the default value.." newline hexmask.long.byte 0x0 12.--16. 1. "REFRESH_TO_X1_X32,If the refresh timer (tRFCnom also known as tREFI) has expired at least once then a speculative refresh may be performed. A speculative refresh is a refresh performed at a time when refresh would be useful. When the SDRAM bus is idle.." newline hexmask.long.byte 0x0 4.--9. 1. "REFRESH_BURST,The programmed value + 1 is the number of refresh timeouts that is allowed to accumulate before traffic is blocked and the refreshes are forced to execute. Closing pages to perform a refresh is a one-time penalty that must be paid for each.." newline bitfld.long 0x0 2. "PER_BANK_REFRESH,- 1 - Per bank refresh - 0 - All bank refresh Per bank refresh allows traffic to flow to other banks. Per bank refresh is not supported by all LPDDR2 devices but must be supported by all LPDDR3/LPDDR4 devices. Present only in designs.." "All bank refresh,Per bank refresh" group.long 0x64++0x7 line.long 0x0 "RFSHTMG,[FREQ2] Refresh Timing Register" bitfld.long 0x0 31. "T_RFC_NOM_X1_SEL,Specifies whether the RFSHTMG.t_rfc_nom_x1_x32 and RFSHCTL0.refresh_to_x1_x32 register values are x1 or x32. - 0 - x32 register values are used - 1 - x1 register values are used This applies only when per-bank refresh is enabled.." "x32 register values are used,x1 register values are used" newline hexmask.long.word 0x0 16.--27. 1. "T_RFC_NOM_X1_X32,Average time interval between refreshes per rank (Specification: 7.8us for DDR2 DDR3 and DDR4. See JEDEC specification for mDDR LPDDR2 LPDDR3 and LPDDR4). When the controller is operating in 1:1 mode set this register to.." newline bitfld.long 0x0 15. "LPDDR3_TREFBW_EN,Used only when LPDDR3 memory type is connected. Should only be changed when uMCTL2 is in reset. Specifies whether to use the tREFBW parameter (required by some LPDDR3 devices which comply with earlier versions of the LPDDR3 JEDEC.." "tREFBW parameter not used,tREFBW parameter used" newline hexmask.long.word 0x0 0.--9. 1. "T_RFC_MIN,tRFC (min): Minimum time from refresh to refresh or activate. When the controller is operating in 1:1 mode t_rfc_min must be set to RoundUp(tRFCmin/tCK). When the controller is operating in 1:2 mode t_rfc_min must be set to.." line.long 0x4 "RFSHTMG1,[FREQ2] Refresh Timing Register1" hexmask.long.byte 0x4 16.--23. 1. "T_PBR2PBR,LPDDR4:tpbR2pbR. Per-bank refresh to Per-bank refresh different bank Time. When the controller is operating in 1:1 frequency ratio mode program this to RoundUp(tpbR2pbR/tCK). When the controller is operating in 1:2 frequency ratio mode.." repeat 4. (list 0x3 0x4 0x6 0x7 )(list 0x0 0x4 0xC 0x10 ) group.long ($2+0xDC)++0x3 line.long 0x0 "INIT$1,[FREQ2] SDRAM Initialization Register 3" hexmask.long.word 0x0 16.--31. 1. "MR,DDR2:Indicates the value to write to MR register. Bit 8 is for DLL and the setting here is ignored. The uMCTL2 sets this bit appropriately. DDR3/DDR4: Value loaded into MR0 register. mDDR: Value to write to MR register. LPDDR2/LPDDR3/LPDDR4 - Value to.." newline hexmask.long.word 0x0 0.--15. 1. "EMR,DDR2: Indicates the value to write to EMR register. Bits 9:7 are for OCD and the setting in this register is ignored. The uMCTL2 sets those bits appropriately. DDR3/DDR4: Value to write to MR1 register Set bit 7 to 0. mDDR: Value to write to EMR.." repeat.end group.long 0xF4++0x3 line.long 0x0 "RANKCTL,[FREQ2] Rank Control Register" bitfld.long 0x0 26. "DIFF_RANK_WR_GAP_MSB,Only present for multi-rank configurations. 1-bit extension to be used when RANKCTL.diff_rank_wr_gap field needs to be set to a value greater than 0xF. Programming Mode: Quasi-dynamic Group 2" "?,bit extension to be used when RANKCTL" newline bitfld.long 0x0 24. "DIFF_RANK_RD_GAP_MSB,Only present for multi-rank configurations. 1-bit extension to be used when RANKCTL.diff_rank_rd_gap field needs to be set to a value greater than 0xF. Programming Mode: Quasi-dynamic Group 2" "?,bit extension to be used when RANKCTL" newline hexmask.long.byte 0x0 12.--15. 1. "MAX_RANK_WR,Only present for multi-rank configurations. Background: Writes to the same rank can be performed back-to-back. Writes to different ranks require additional gap dictated by the register RANKCTL.diff_rank_wr_gap. This is to avoid possible data.." newline hexmask.long.byte 0x0 8.--11. 1. "DIFF_RANK_WR_GAP,Only present for multi-rank configurations. Indicates the number of clocks of gap in data responses when performing consecutive writes to different ranks. This is used to switch the delays in the PHY to match the rank requirements. This.." newline hexmask.long.byte 0x0 4.--7. 1. "DIFF_RANK_RD_GAP,Only present for multi-rank configurations. Indicates the number of clocks of gap in data responses when performing consecutive reads to different ranks. This is used to switch the delays in the PHY to match the rank requirements. This.." newline hexmask.long.byte 0x0 0.--3. 1. "MAX_RANK_RD,Only present for multi-rank configurations. Background: Reads to the same rank can be performed back-to-back. Reads to different ranks require additional gap dictated by the register RANKCTL.diff_rank_rd_gap. This is to avoid possible data.." group.long 0x100++0x3F line.long 0x0 "DRAMTMG0,[FREQ2] SDRAM Timing Register 0" hexmask.long.byte 0x0 24.--30. 1. "WR2PRE,Specifies the minimum time between write and precharge to same bank. Specifications: WL + BL/2 + tWR = approximately 8 cycles + 15 ns = 14 clocks @400MHz and less for lower frequencies. where: - WL - Write latency - BL - Burst length. This must.." newline hexmask.long.byte 0x0 16.--21. 1. "T_FAW,tFAW - valid only when 8 or more banks(or banks x bank groups) are present. In 8-bank design at most 4 banks must be activated in a rolling window of tFAW cycles. When the controller is operating in 1:2 frequency ratio mode program this to.." newline hexmask.long.byte 0x0 8.--14. 1. "T_RAS_MAX,tRAS(max) - Specifies the maximum time between activate and precharge to same bank. This is the maximum time that a page can be kept open Minimum value of this register is 1. Zero is invalid. When the controller is operating in 1:1 frequency.." newline hexmask.long.byte 0x0 0.--5. 1. "T_RAS_MIN,tRAS(min) - Specifies the minimum time between activate and precharge to the same bank. When the controller is operating in 1:2 frequency mode 1T mode program this to tRAS(min)/2. No rounding up. When the controller is operating in 1:2.." line.long 0x4 "DRAMTMG1,[FREQ2] SDRAM Timing Register 1" hexmask.long.byte 0x4 16.--20. 1. "T_XP,tXP - Specifies the minimum time after power-down exit to any operation. For DDR3 this must be programmed to tXPDLL if slow powerdown exit is selected in MR0[12]. If C/A parity for DDR4 is used set to (tXP+PL) instead. If LPDDR4 is selected and.." newline hexmask.long.byte 0x4 8.--13. 1. "RD2PRE,tRTP - Specifies the minimum time from read to precharge of same bank. - DDR2 - tAL + BL/2 + max(tRTP 2) - 2 - DDR3 - tAL + max (tRTP 4) - DDR4 - Max of following two equations: tAL + max (tRTP 4) or RL + BL/2 - tRP (*). - mDDR - BL/2 - LPDDR2.." newline hexmask.long.byte 0x4 0.--6. 1. "T_RC,tRC - Specifies the minimum time between activates to same bank. When the controller is operating in 1:2 frequency ratio mode program this to (tRC/2) and round up to next integer value. Unit: DFI clock cycles. Programming Mode: Quasi-dynamic Group.." line.long 0x8 "DRAMTMG2,[FREQ2] SDRAM Timing Register 2" hexmask.long.byte 0x8 24.--29. 1. "WRITE_LATENCY,Set this field to WL. Indicates the Time from write command to write data on SDRAM interface. This must be set to WL. For mDDR it must be set to 1. Note that depending on the PHY if using RDIMM/LRDIMM it might be necessary to adjust the.." newline hexmask.long.byte 0x8 16.--21. 1. "READ_LATENCY,Set this field to RL. Indicates the time from read command to read data on SDRAM interface. This must be set to RL. Note that depending on the PHY if using RDIMM/LRDIMM it might be necessary to adjust the value of RL to compensate for the.." newline hexmask.long.byte 0x8 8.--13. 1. "RD2WR,DDR2/3/mDDR: RL + BL/2 + 2 - WL DDR4: RL + BL/2 + 1 + WR_PREAMBLE - WL LPDDR2/LPDDR3: RL + BL/2 + RU(tDQSCKmax/tCK) + 1 - WL LPDDR4(DQ ODT is Disabled): RL + BL/2 + RU(tDQSCKmax/tCK) + WR_PREAMBLE + RD_POSTAMBLE - WL LPDDR4(DQ ODT is Enabled): RL +.." newline hexmask.long.byte 0x8 0.--5. 1. "WR2RD,DDR4: CWL + PL + BL/2 + tWTR_L LPDDR2/3/4: WL + BL/2 + tWTR + 1 Others: CWL + BL/2 + tWTR In DDR4 minimum time from write command to read command for same bank group. In others minimum time from write command to read command. Includes time for.." line.long 0xC "DRAMTMG3,[FREQ2] SDRAM Timing Register 3" hexmask.long.word 0xC 20.--29. 1. "T_MRW,Indicates the time to wait after a mode register write or read (MRW or MRR). Present only in designs configured to support LPDDR2 LPDDR3 or LPDDR4. LPDDR2 typically requires value of 5. LPDDR3 typically requires value of 10. LPDDR4: Set this to.." newline hexmask.long.byte 0xC 12.--17. 1. "T_MRD,tMRD- Indicates the number of cycles to wait after a mode register write or read. Depending on the connected SDRAM tMRD represents: - DDR2/mDDR: Time from MRS to any command - DDR3/4: Time from MRS to MRS command - LPDDR2: not used - LPDDR3/4:.." newline hexmask.long.word 0xC 0.--9. 1. "T_MOD,tMOD - Parameter used only in DDR3 and DDR4. Indicates the number of cycles between load mode command and following non-load mode command. If C/A parity for DDR4 is used set to tMOD_PAR(tMOD+PL) instead. If CAL mode is enabled.." line.long 0x10 "DRAMTMG4,[FREQ2] SDRAM Timing Register 4" hexmask.long.byte 0x10 24.--28. 1. "T_RCD,tRCD - tAL: Indicates the minimum time from activate to read or write command to same bank. When the controller is operating in 1:2 frequency ratio mode program this to ((tRCD - tAL)/2) and round it up to the next integer value. Minimum value.." newline hexmask.long.byte 0x10 16.--19. 1. "T_CCD,DDR4: tCCD_L: This is the minimum time between two reads or two writes for same bank group. Others: tCCD: This is the minimum time between two reads or two writes. When the controller is operating in 1:2 frequency ratio mode program this to.." newline hexmask.long.byte 0x10 8.--11. 1. "T_RRD,DDR4: tRRD_L: This is the minimum time between activates from bank 'a' to bank 'b' for same bank group. Others: tRRD: Minimum time between activates from bank 'a' to bank 'b' When the controller is operating in 1:2 frequency ratio mode program.." newline hexmask.long.byte 0x10 0.--4. 1. "T_RP,tRP: Indicates the minimum time from single-bank precharge to activate of same bank. When the controller is operating in 1:1 frequency ratio mode t_rp must be set to RoundUp(tRP/tCK). When the controller is operating in 1:2 frequency ratio mode.." line.long 0x14 "DRAMTMG5,[FREQ2] SDRAM Timing Register 5" hexmask.long.byte 0x14 24.--27. 1. "T_CKSRX,This is the time before self-refresh Exit that CK is maintained as a valid clock before issuing SRX. Specifies the clock stable time before SRX. Recommended settings: - mDDR - 1 - LPDDR2 - 2 - LPDDR3 - 2 - LPDDR4 - tCKCKEH - DDR2 - 1 - DDR3 -.." newline hexmask.long.byte 0x14 16.--19. 1. "T_CKSRE,This is the time after self-refresh Down Entry that CK is maintained as a valid clock. Specifies the clock disable delay after SRE. Recommended settings: - mDDR - 0 - LPDDR2 - 2 - LPDDR3 - 2 - LPDDR4 - tCKELCK - DDR2 - 1 - DDR3 - Max (10 ns 5.." newline hexmask.long.byte 0x14 8.--13. 1. "T_CKESR,Indicates the minimum CKE low width for self-refresh or self-refresh power down entry to exit timing in memory clock cycles. Recommended settings: - mDDR - tRFC - LPDDR2 - tCKESR - LPDDR3 - tCKESR - LPDDR4 - max(tCKE tSR) - DDR2 - tCKE - DDR3 -.." newline hexmask.long.byte 0x14 0.--4. 1. "T_CKE,Indicates the minimum number of cycles of CKE HIGH/LOW during power-down and self-refresh. - LPDDR2/LPDDR3 mode - Set this to the larger of tCKE or tCKESR - LPDDR4 mode - Set this to the larger of tCKE or tSR - Non-LPDDR2/non-LPDDR3/non-LPDDR4.." line.long 0x18 "DRAMTMG6,[FREQ2] SDRAM Timing Register 6" hexmask.long.byte 0x18 24.--27. 1. "T_CKDPDE,This is the time after Deep Power Down Entry that CK is maintained as a valid clock. Specifies the clock disable delay after DPDE. Recommended settings: - mDDR: 0 - LPDDR2: 2 - LPDDR3: 2 When the controller is operating in 1:2 frequency ratio.." newline hexmask.long.byte 0x18 16.--19. 1. "T_CKDPDX,This is the time before Deep Power Down Exit that CK is maintained as a valid clock before issuing DPDX. Specifies the clock stable time before DPDX. Recommended settings: - mDDR - 1 - LPDDR2 - 2 - LPDDR3 - 2 When the controller is operating in.." newline hexmask.long.byte 0x18 0.--3. 1. "T_CKCSX,This is the time before Clock Stop Exit that CK is maintained as a valid clock before issuing Clock Stop Exit. Specifies the clock stable time before next command after Clock Stop Exit. Recommended settings: - mDDR - 1 - LPDDR2 - tXP + 2 - LPDDR3.." line.long 0x1C "DRAMTMG7,[FREQ2] SDRAM Timing Register 7" hexmask.long.byte 0x1C 8.--11. 1. "T_CKPDE,This is the time after Power Down Entry that CK is maintained as a valid clock. Specifies the clock disable delay after PDE. Recommended settings: - mDDR - 0 - LPDDR2 - 2 - LPDDR3 - 2 - LPDDR4 - tCKELCK When using DDR2/3/4 SDRAM this register.." newline hexmask.long.byte 0x1C 0.--3. 1. "T_CKPDX,This is the time before Power Down Exit that CK is maintained as a valid clock before issuing PDX. Specifies the clock stable time before PDX. Recommended settings: - mDDR - 0 - LPDDR2 - 2 - LPDDR3 - 2 - LPDDR4 - tCKCKEH When using DDR2/3/4 SDRAM.." line.long 0x20 "DRAMTMG8,[FREQ2] SDRAM Timing Register 8" hexmask.long.byte 0x20 24.--30. 1. "T_XS_FAST_X32,tXS_FAST: Exit self-refresh to ZQCL ZQCS and MRS (only CL WR RTP and Geardown mode). When the controller is operating in 1:2 frequency ratio mode program this to the previous value divided by 2 and round up to next integer value. Note:.." newline hexmask.long.byte 0x20 16.--22. 1. "T_XS_ABORT_X32,tXS_ABORT: Exit self-refresh to commands not requiring a locked DLL in self-refresh Abort. When the controller is operating in 1:2 frequency ratio mode program this to the previous value divided by 2 and round up to next integer value." newline hexmask.long.byte 0x20 8.--14. 1. "T_XS_DLL_X32,tXSDLL: Exit self-refresh to commands requiring a locked DLL. When the controller is operating in 1:2 frequency ratio mode program this to the previous value divided by 2 and round up to next integer value. Note: Used only for DDR2 DDR3.." newline hexmask.long.byte 0x20 0.--6. 1. "T_XS_X32,tXS: Exit self-refresh to commands not requiring a locked DLL. When the controller is operating in 1:2 frequency ratio mode program this to the previous value divided by 2 and round up to next integer value. Note: Used only for DDR2 DDR3 and.." line.long 0x24 "DRAMTMG9,[FREQ2] SDRAM Timing Register 9" bitfld.long 0x24 30. "DDR4_WR_PREAMBLE,DDR4 Write preamble mode. - 0 - 1tCK preamble - 1 - 2tCK preamble Present only with MEMC_FREQ_RATIO=2. Programming Mode: Quasi-dynamic Group 2 Group 4" "0,1" newline bitfld.long 0x24 16.--18. "T_CCD_S,tCCD_S: This is the minimum time between two reads or two writes for different bank group. For bank switching (from bank 'a' to bank 'b') the minimum time is this value + 1. When the controller is operating in 1:2 frequency ratio mode program.." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x24 8.--11. 1. "T_RRD_S,tRRD_S: This is the minimum time between activates from bank 'a' to bank 'b' for different bank group. When the controller is operating in 1:2 frequency ratio mode program this to (tRRD_S/2) and round it up to the next integer value. Present.." newline hexmask.long.byte 0x24 0.--5. 1. "WR2RD_S,CWL + PL + BL/2 + tWTR_S Minimum time from write command to read command for different bank group. Includes time for bus turnaround recovery times and all per-bank per-rank and global constraints. Present only in designs configured to support.." line.long 0x28 "DRAMTMG10,[FREQ2] SDRAM Timing Register 10" hexmask.long.byte 0x28 16.--20. 1. "T_SYNC_GEAR,Indicates the time between MRS command and the sync pulse time. This must be even number of clocks. For DDR4-2666 and DDR4-3200 this parameter is defined as tMOD(min)+4nCK tMOD(min) is greater of 24nCK or 15ns 15ns / .625ns = 24 Max value.." newline hexmask.long.byte 0x28 8.--12. 1. "T_CMD_GEAR,Indicates a sync pulse to first valid command. For DDR4-2666 and DDR4-3200 this parameter is defined as tMOD(min) tMOD(min) is greater of 24nCK or 15ns 15ns / .625ns = 24 Max value for this register is 24 When the controller is operating in.." newline bitfld.long 0x28 2.--3. "T_GEAR_SETUP,Indicates the geardown setup time. Minimum value of this register is 1. Zero is invalid. For DDR4-2666 and DDR4-3200 this parameter is defined as 2 clks When the controller is operating in 1:2 frequency ratio mode program this to.." "0,1,2,3" newline bitfld.long 0x28 0.--1. "T_GEAR_HOLD,Indicates the geardown hold time. Minimum value of this register is 1. Zero is invalid. For DDR4-2666 and DDR4-3200 this parameter is defined as 2 clks When the controller is operating in 1:2 frequency ratio mode program this to.." "0,1,2,3" line.long 0x2C "DRAMTMG11,[FREQ2] SDRAM Timing Register 11" hexmask.long.byte 0x2C 24.--30. 1. "POST_MPSM_GAP_X32,tXMPDLL: This is the minimum Exit MPSM to commands requiring a locked DLL. When the controller is operating in 1:2 frequency ratio mode program this to (tXMPDLL/2) and round it up to the next integer value. Present only in designs.." newline hexmask.long.byte 0x2C 16.--20. 1. "T_MPX_LH,tMPX_LH: This is the minimum CS_n Low hold time to CKE rising edge. When the controller is operating in 1:2 frequency ratio mode program this to RoundUp(tMPX_LH/2)+1. Present only in designs configured to support DDR4. Unit: DFI clock cycles." newline bitfld.long 0x2C 8.--9. "T_MPX_S,tMPX_S: This is the minimum time CS setup time to CKE. When the controller is operating in 1:2 frequency ratio mode program this to (tMPX_S/2) and round it up to the next integer value. Present only in designs configured to support DDR4. Unit:.." "0,1,2,3" newline hexmask.long.byte 0x2C 0.--4. 1. "T_CKMPE,tCKMPE: This is the minimum valid clock requirement after MPSM entry. Present only in designs configured to support DDR4. When the controller is operating in 1:2 frequency ratio mode divide the value calculated using the previous equation by 2.." line.long 0x30 "DRAMTMG12,[FREQ2] SDRAM Timing Register 12" hexmask.long.byte 0x30 24.--29. 1. "T_WR_MPR,This bit is used only in DDR4. Cycles between MPR Write and other command. Set this to tMOD + AL (or tMOD + PL + AL if C/A parity is also used). When the controller is operating in 1:2 frequency ratio mode program this to (tWR_MPR/2) and round.." newline bitfld.long 0x30 16.--17. "T_CMDCKE,tCMDCKE: Indicates the delay from valid command to CKE input LOW. Set this to the larger of tESCKE or tCMDCKE When the controller is operating in 1:2 frequency ratio mode program this to (max(tESCKE tCMDCKE)/2) and round it up to the next.." "0,1,2,3" newline hexmask.long.byte 0x30 0.--4. 1. "T_MRD_PDA,tMRD_PDA: This is the Mode Register Set command cycle time in PDA mode. When the controller is operating in 1:2 frequency ratio mode program this to (tMRD_PDA/2) and round it up to the next integer value. Unit: DFI clock cycles. Programming.." line.long 0x34 "DRAMTMG13,[FREQ2] SDRAM Timing Register 13" hexmask.long.byte 0x34 24.--30. 1. "ODTLOFF,LPDDR4: ODTLoff: This is the latency from CAS-2 command to ODToff reference. When the controller is operating in 1:2 frequency ratio mode program this to (ODTLoff/2) and round it up to the next integer value. Unit: DFI clock cycles. Programming.." newline hexmask.long.byte 0x34 16.--21. 1. "T_CCD_MW,LPDDR4: tCCDMW: This is the minimum time from write or masked write to masked write command for same bank. When the controller is operating in 1:2 frequency ratio mode program this to (tCCDMW/2) and round it up to the next integer value. Unit:.." newline bitfld.long 0x34 0.--2. "T_PPD,LPDDR4: tPPD: This is the minimum time from precharge to precharge command. When the controller is operating in 1:2 frequency ratio mode program this to (tPPD/2) and round it up to the next integer value. Unit: DFI clock cycles. Programming Mode:.." "?,?,?,?,tPPD: This is the minimum time from precharge to..,?,?,?" line.long 0x38 "DRAMTMG14,[FREQ2] SDRAM Timing Register 14" hexmask.long.word 0x38 0.--11. 1. "T_XSR,tXSR: This is the exit self-refresh to any command. When the controller is operating in 1:2 frequency ratio mode program this to the previous value divided by 2 and round up to next integer value. The value 0xfff is illegal for this register.." line.long 0x3C "DRAMTMG15,[FREQ2] SDRAM Timing Register 15" bitfld.long 0x3C 31. "EN_DFI_LP_T_STAB,- 1 - Enable using tSTAB when exiting DFI LP. This must be set when the PHY is stopping the clock during DFI LP to save maximum power. - 0 - Disable using tSTAB when exiting DFI LP. Programming Mode: Quasi-dynamic Group 2 Group 4" "Disable using tSTAB when exiting DFI LP,Enable using tSTAB when exiting DFI LP" newline hexmask.long.byte 0x3C 0.--7. 1. "T_STAB_X32,tSTAB: Stabilization time. It is required in the following two cases for DDR3/DDR4 RDIMM: - When exiting power saving mode if the clock is stopped after re-enabling it the clock must be stable for a time specified by tSTAB - In the case of.." group.long 0x180++0x3 line.long 0x0 "ZQCTL0,[FREQ2] ZQ Control Register 0" bitfld.long 0x0 31. "DIS_AUTO_ZQ,- 1 - Disable uMCTL2 generation of ZQCS/MPC(ZQ calibration) command. Register DBGCMD.zq_calib_short can be used instead to issue ZQ calibration request from APB module - 0 - Internally generate ZQCS/MPC(ZQ calibration) commands based on.." "Internally generate ZQCS/MPC,Disable uMCTL2 generation of ZQCS/MPC" newline bitfld.long 0x0 30. "DIS_SRX_ZQCL,- 1 - Disable issuing of ZQCL/MPC(ZQ calibration) command at self-refresh/SR-Powerdown exit. Only applicable when run in DDR3 or DDR4 or LPDDR2 or LPDDR3 or LPDDR4 mode - 0 - Enable issuing of ZQCL/MPC(ZQ calibration) command at.." "Enable issuing of ZQCL/MPC,Disable issuing of ZQCL/MPC" newline bitfld.long 0x0 29. "ZQ_RESISTOR_SHARED,- 1 - Denotes that ZQ resistor is shared between ranks. Means ZQinit/ZQCL/ZQCS/MPC(ZQ calibration) commands are sent to one rank at a time with tZQinit/tZQCL/tZQCS/tZQCAL/tZQLAT timing met between commands so that commands to different.." "ZQ resistor is not shared,Denotes that ZQ resistor is shared between ranks" newline bitfld.long 0x0 28. "DIS_MPSMX_ZQCL,- 1 - Disable issuing of ZQCL command at Maximum Power Saving Mode exit. Only applicable when run in DDR4 mode - 0 - Enable issuing of ZQCL command at Maximum Power Saving Mode exit. Only applicable when run in DDR4 mode This is only.." "Enable issuing of ZQCL command at Maximum Power..,Disable issuing of ZQCL command at Maximum Power.." newline hexmask.long.word 0x0 16.--26. 1. "T_ZQ_LONG_NOP,tZQoper for DDR3/DDR4 tZQCL for LPDDR2/LPDDR3 tZQCAL for LPDDR4: Number of DFI clock cycles of NOP required after a ZQCL (ZQ calibration long)/MPC(ZQ Start) command is issued to SDRAM. When the controller is operating in 1:2 frequency.." newline hexmask.long.word 0x0 0.--9. 1. "T_ZQ_SHORT_NOP,tZQCS for DDR3/DD4/LPDDR2/LPDDR3 tZQLAT for LPDDR4: Number of DFI clock cycles of NOP required after a ZQCS (ZQ calibration short)/MPC(ZQ Latch) command is issued to SDRAM. When the controller is operating in 1:2 frequency ratio mode.." group.long 0x190++0x7 line.long 0x0 "DFITMG0,[FREQ2] DFI Timing Register 0" hexmask.long.byte 0x0 24.--28. 1. "DFI_T_CTRL_DELAY,Specifies the number of DFI clock cycles after an assertion or de-assertion of the DFI control signals that the control signals at the PHY-DRAM interface reflect the assertion or de-assertion. If the DFI clock and the memory clock are.." newline bitfld.long 0x0 23. "DFI_RDDATA_USE_DFI_PHY_CLK,Defines whether dfi_rddata_en/dfi_rddata/dfi_rddata_valid is generated using HDR (DFI clock) or SDR (DFI PHY clock) values. Selects whether value in DFITMG0.dfi_t_rddata_en is in terms of HDR (DFI clock) or SDR (DFI PHY clock).." "Else,?" newline hexmask.long.byte 0x0 16.--22. 1. "DFI_T_RDDATA_EN,Time from the assertion of a read command on the DFI interface to the assertion of the dfi_rddata_en signal. Refer to PHY specification for correct value. This corresponds to the DFI parameter trddata_en. Note that depending on the PHY.." newline bitfld.long 0x0 15. "DFI_WRDATA_USE_DFI_PHY_CLK,Defines whether dfi_wrdata_en/dfi_wrdata/dfi_wrdata_mask is generated using HDR (DFI clock) or SDR (DFI PHY clock) values. Selects whether value in DFITMG0.dfi_tphy_wrlat is in terms of HDR (DFI clock) or SDR (DFI PHY clock).." "Else,?" newline hexmask.long.byte 0x0 8.--13. 1. "DFI_TPHY_WRDATA,Specifies the number of clock cycles between when dfi_wrdata_en is asserted to when the associated write data is driven on the dfi_wrdata signal. This corresponds to the DFI timing parameter tphy_wrdata. For more information on correct.." newline hexmask.long.byte 0x0 0.--5. 1. "DFI_TPHY_WRLAT,Write latency. Number of clocks from the write command to write data enable (dfi_wrdata_en). This corresponds to the DFI timing parameter tphy_wrlat. Refer to PHY specification for correct value.Note that depending on the PHY if using.." line.long 0x4 "DFITMG1,[FREQ2] DFI Timing Register 1" hexmask.long.byte 0x4 28.--31. 1. "DFI_T_CMD_LAT,Specifies the number of DFI PHY clock cycles between when the dfi_cs signal is asserted and when the associated command is driven. This field is used for CAL mode must be set to '0' or tCAL which matches the CAL mode register setting in.." newline bitfld.long 0x4 24.--25. "DFI_T_PARIN_LAT,Specifies the number of DFI PHY clock cycles between when the dfi_cs signal is asserted and when the associated dfi_parity_in signal is driven. Unit: DFI PHY clock cycles. Programming Mode: Quasi-dynamic Group 4" "0,1,2,3" newline hexmask.long.byte 0x4 16.--20. 1. "DFI_T_WRDATA_DELAY,Specifies the number of DFI clock cycles between when the dfi_wrdata_en signal is asserted and when the corresponding write data transfer is completed on the DRAM bus. This corresponds to the DFI timing parameter twrdata_delay. For.." newline hexmask.long.byte 0x4 8.--12. 1. "DFI_T_DRAM_CLK_DISABLE,Specifies the number of DFI clock cycles from the assertion of the dfi_dram_clk_disable signal on the DFI until the clock to the DRAM memory devices at the PHY-DRAM boundary maintains a low value. If the DFI clock and the memory.." newline hexmask.long.byte 0x4 0.--4. 1. "DFI_T_DRAM_CLK_ENABLE,Specifies the number of DFI clock cycles from the de-assertion of the dfi_dram_clk_disable signal on the DFI until the first valid rising edge of the clock to the DRAM memory devices at the PHY-DRAM boundary. If the DFI clock and.." group.long 0x1B4++0x7 line.long 0x0 "DFITMG2,[FREQ2] DFI Timing Register 2" hexmask.long.byte 0x0 8.--14. 1. "DFI_TPHY_RDCSLAT,specifies the number of DFI PHY clock cycles between when a read command is sent on the DFI control interface and when the associated dfi_rddata_cs signal is asserted. This corresponds to the DFI timing parameter tphy_rdcslat. Refer to.." newline hexmask.long.byte 0x0 0.--5. 1. "DFI_TPHY_WRCSLAT,Specifies the number of DFI PHY clock cycles between when a write command is sent on the DFI control interface and when the associated dfi_wrdata_cs signal is asserted. This corresponds to the DFI timing parameter tphy_wrcslat. For more.." line.long 0x4 "DFITMG3,[FREQ2] DFI Timing Register 3" hexmask.long.byte 0x4 0.--4. 1. "DFI_T_GEARDOWN_DELAY,The delay from dfi_geardown_en assertion to the time of the PHY being ready to receive commands. Refer to PHY specification for correct value. When the controller is operating in 1:2 frequency ratio mode program this to.." group.long 0x240++0x3 line.long 0x0 "ODTCFG,[FREQ2] ODT Configuration Register" hexmask.long.byte 0x0 24.--27. 1. "WR_ODT_HOLD,DFI PHY clock cycles to hold ODT for a write command. The minimum supported value is 2. Recommended values: DDR2: - BL8 - 0x5 (DDR2-400/533/667) 0x6 (DDR2-800) 0x7 (DDR2-1066) - BL4 - 0x3 (DDR2-400/533/667) 0x4 (DDR2-800) 0x5 (DDR2-1066).." newline hexmask.long.byte 0x0 16.--20. 1. "WR_ODT_DELAY,Indicates the delay in DFI PHY clock cycles from issuing a write command to setting ODT values associated with that command. ODT setting must remain constant for the entire time that DQS is driven by the uMCTL2. Recommended values: DDR2: -.." newline hexmask.long.byte 0x0 8.--11. 1. "RD_ODT_HOLD,DFI PHY clock cycles to hold ODT for a read command. The minimum supported value is 2. Recommended values: DDR2: - BL8 - 0x6 (not DDR2-1066) 0x7 (DDR2-1066) - BL4 - 0x4 (not DDR2-1066) 0x5 (DDR2-1066) DDR3: - BL8 - 0x6 DDR4: - BL8 - 5 +.." newline hexmask.long.byte 0x0 2.--6. 1. "RD_ODT_DELAY,Indicates the delay in DFI PHY clock cycles from issuing a read command to setting ODT values associated with that command. ODT setting must remain constant for the entire time that DQS is driven by the uMCTL2. Recommended values: DDR2: -.." tree.end tree "UMCTL2_REGS_FREQ3 (uMCTL2 DDRC FREQ3 Registers)" base ad:0x16384 group.long 0x20++0x7 line.long 0x0 "DERATEEN,[FREQ3] Temperature Derate Enable Register" bitfld.long 0x0 12. "DERATE_MR4_TUF_DIS,Disables use of MR4 TUF flag (MR4[7]) bit. - 0 - Use MR4 TUF flag (MR4[7]) - 1 - Do not use MR4 TUF Flag (MR4[7]) For LPDDR4 it is recommended to set this register to 1. For LPDDR2 and LPDDR3 contact your memory vendor for.." "Use MR4 TUF flag,Do not use MR4 TUF Flag" newline bitfld.long 0x0 8.--10. "RC_DERATE_VALUE,Derate value of tRC for LPDDR4. - 0 - Derating uses +1 - 1 - Derating uses +2 - 2 - Derating uses +3 - 3 - Derating uses +4 Present only in designs configured to support LPDDR4. The required cycles for derating can be determined by.." "Derating uses +1,Derating uses +2,Derating uses +3,Derating uses +4,?,?,?,?" newline hexmask.long.byte 0x0 4.--7. 1. "DERATE_BYTE,This bit indicates which byte of the MRR data is used for derating. The maximum valid value depends on MEMC_DRAM_TOTAL_DATA_WIDTH. Present only in designs configured to support LPDDR2/LPDDR3/LPDDR4. Programming Mode: Static" newline bitfld.long 0x0 1.--2. "DERATE_VALUE,Derate value. - 0 - Derating uses +1 - 1 - Derating uses +2 Present only in designs configured to support LPDDR2/LPDDR3/LPDDR4. Set to 0 for all LPDDR2 speed grades as derating value of +1.875 ns is less than a core_ddrc_core_clk period. For.." "Derating uses +1,Derating uses +2,?,?" newline bitfld.long 0x0 0. "DERATE_ENABLE,Enables derating. - 0 - Timing parameter derating is disabled - 1 - Timing parameter derating is enabled using MR4 read value Present only in designs configured to support LPDDR2/LPDDR3/LPDDR4. This field must be set to '0' for.." "Timing parameter derating is disabled,Timing parameter derating is enabled using MR4.." line.long 0x4 "DERATEINT,[FREQ3] Temperature Derate Interval Register" hexmask.long 0x4 0.--31. 1. "MR4_READ_INTERVAL,Interval between two MR4 reads used to derate the timing parameters. Present only in designs configured to support LPDDR2/LPDDR3/LPDDR4. This register must not be set to zero. Unit: DFI clock cycles. Programming Mode: Static" group.long 0x34++0x3 line.long 0x0 "PWRTMG,[FREQ3] Low Power Timing Register" hexmask.long.byte 0x0 16.--23. 1. "SELFREF_TO_X32,After this many clocks of the DDRC command channel being idle the uMCTL2 automatically puts the SDRAM into self-refresh. The DDRC command channel is considered idle when there are no HIF commands outstanding. This must be enabled in the.." newline hexmask.long.byte 0x0 8.--15. 1. "T_DPD_X4096,Minimum deep power-down time. For mDDR value from the JEDEC specification is 0 as mDDR exits from deep power-down mode immediately after PWRCTL.deeppowerdown_en is de-asserted. For LPDDR2/LPDDR3 value from the JEDEC specification is 500us." newline hexmask.long.byte 0x0 0.--4. 1. "POWERDOWN_TO_X32,After this many clocks of the DDRC command channel being idle the uMCTL2 automatically puts the SDRAM into power-down. The DDRC command channel is considered idle when there are no HIF commands outstanding. This must be enabled in the.." group.long 0x50++0x3 line.long 0x0 "RFSHCTL0,[FREQ3] Refresh Control Register 0" hexmask.long.byte 0x0 20.--23. 1. "REFRESH_MARGIN,Threshold value in number of DFI clock cycles before the critical refresh or page timer expires. A critical refresh is to be issued before this threshold is reached. It is recommended that this not be changed from the default value.." newline hexmask.long.byte 0x0 12.--16. 1. "REFRESH_TO_X1_X32,If the refresh timer (tRFCnom also known as tREFI) has expired at least once then a speculative refresh may be performed. A speculative refresh is a refresh performed at a time when refresh would be useful. When the SDRAM bus is idle.." newline hexmask.long.byte 0x0 4.--9. 1. "REFRESH_BURST,The programmed value + 1 is the number of refresh timeouts that is allowed to accumulate before traffic is blocked and the refreshes are forced to execute. Closing pages to perform a refresh is a one-time penalty that must be paid for each.." newline bitfld.long 0x0 2. "PER_BANK_REFRESH,- 1 - Per bank refresh - 0 - All bank refresh Per bank refresh allows traffic to flow to other banks. Per bank refresh is not supported by all LPDDR2 devices but must be supported by all LPDDR3/LPDDR4 devices. Present only in designs.." "All bank refresh,Per bank refresh" group.long 0x64++0x7 line.long 0x0 "RFSHTMG,[FREQ3] Refresh Timing Register" bitfld.long 0x0 31. "T_RFC_NOM_X1_SEL,Specifies whether the RFSHTMG.t_rfc_nom_x1_x32 and RFSHCTL0.refresh_to_x1_x32 register values are x1 or x32. - 0 - x32 register values are used - 1 - x1 register values are used This applies only when per-bank refresh is enabled.." "x32 register values are used,x1 register values are used" newline hexmask.long.word 0x0 16.--27. 1. "T_RFC_NOM_X1_X32,Average time interval between refreshes per rank (Specification: 7.8us for DDR2 DDR3 and DDR4. See JEDEC specification for mDDR LPDDR2 LPDDR3 and LPDDR4). When the controller is operating in 1:1 mode set this register to.." newline bitfld.long 0x0 15. "LPDDR3_TREFBW_EN,Used only when LPDDR3 memory type is connected. Should only be changed when uMCTL2 is in reset. Specifies whether to use the tREFBW parameter (required by some LPDDR3 devices which comply with earlier versions of the LPDDR3 JEDEC.." "tREFBW parameter not used,tREFBW parameter used" newline hexmask.long.word 0x0 0.--9. 1. "T_RFC_MIN,tRFC (min): Minimum time from refresh to refresh or activate. When the controller is operating in 1:1 mode t_rfc_min must be set to RoundUp(tRFCmin/tCK). When the controller is operating in 1:2 mode t_rfc_min must be set to.." line.long 0x4 "RFSHTMG1,[FREQ3] Refresh Timing Register1" hexmask.long.byte 0x4 16.--23. 1. "T_PBR2PBR,LPDDR4:tpbR2pbR. Per-bank refresh to Per-bank refresh different bank Time. When the controller is operating in 1:1 frequency ratio mode program this to RoundUp(tpbR2pbR/tCK). When the controller is operating in 1:2 frequency ratio mode.." repeat 4. (list 0x3 0x4 0x6 0x7 )(list 0x0 0x4 0xC 0x10 ) group.long ($2+0xDC)++0x3 line.long 0x0 "INIT$1,[FREQ3] SDRAM Initialization Register 3" hexmask.long.word 0x0 16.--31. 1. "MR,DDR2:Indicates the value to write to MR register. Bit 8 is for DLL and the setting here is ignored. The uMCTL2 sets this bit appropriately. DDR3/DDR4: Value loaded into MR0 register. mDDR: Value to write to MR register. LPDDR2/LPDDR3/LPDDR4 - Value to.." newline hexmask.long.word 0x0 0.--15. 1. "EMR,DDR2: Indicates the value to write to EMR register. Bits 9:7 are for OCD and the setting in this register is ignored. The uMCTL2 sets those bits appropriately. DDR3/DDR4: Value to write to MR1 register Set bit 7 to 0. mDDR: Value to write to EMR.." repeat.end group.long 0xF4++0x3 line.long 0x0 "RANKCTL,[FREQ3] Rank Control Register" bitfld.long 0x0 26. "DIFF_RANK_WR_GAP_MSB,Only present for multi-rank configurations. 1-bit extension to be used when RANKCTL.diff_rank_wr_gap field needs to be set to a value greater than 0xF. Programming Mode: Quasi-dynamic Group 2" "?,bit extension to be used when RANKCTL" newline bitfld.long 0x0 24. "DIFF_RANK_RD_GAP_MSB,Only present for multi-rank configurations. 1-bit extension to be used when RANKCTL.diff_rank_rd_gap field needs to be set to a value greater than 0xF. Programming Mode: Quasi-dynamic Group 2" "?,bit extension to be used when RANKCTL" newline hexmask.long.byte 0x0 12.--15. 1. "MAX_RANK_WR,Only present for multi-rank configurations. Background: Writes to the same rank can be performed back-to-back. Writes to different ranks require additional gap dictated by the register RANKCTL.diff_rank_wr_gap. This is to avoid possible data.." newline hexmask.long.byte 0x0 8.--11. 1. "DIFF_RANK_WR_GAP,Only present for multi-rank configurations. Indicates the number of clocks of gap in data responses when performing consecutive writes to different ranks. This is used to switch the delays in the PHY to match the rank requirements. This.." newline hexmask.long.byte 0x0 4.--7. 1. "DIFF_RANK_RD_GAP,Only present for multi-rank configurations. Indicates the number of clocks of gap in data responses when performing consecutive reads to different ranks. This is used to switch the delays in the PHY to match the rank requirements. This.." newline hexmask.long.byte 0x0 0.--3. 1. "MAX_RANK_RD,Only present for multi-rank configurations. Background: Reads to the same rank can be performed back-to-back. Reads to different ranks require additional gap dictated by the register RANKCTL.diff_rank_rd_gap. This is to avoid possible data.." group.long 0x100++0x3F line.long 0x0 "DRAMTMG0,[FREQ3] SDRAM Timing Register 0" hexmask.long.byte 0x0 24.--30. 1. "WR2PRE,Specifies the minimum time between write and precharge to same bank. Specifications: WL + BL/2 + tWR = approximately 8 cycles + 15 ns = 14 clocks @400MHz and less for lower frequencies. where: - WL - Write latency - BL - Burst length. This must.." newline hexmask.long.byte 0x0 16.--21. 1. "T_FAW,tFAW - valid only when 8 or more banks(or banks x bank groups) are present. In 8-bank design at most 4 banks must be activated in a rolling window of tFAW cycles. When the controller is operating in 1:2 frequency ratio mode program this to.." newline hexmask.long.byte 0x0 8.--14. 1. "T_RAS_MAX,tRAS(max) - Specifies the maximum time between activate and precharge to same bank. This is the maximum time that a page can be kept open Minimum value of this register is 1. Zero is invalid. When the controller is operating in 1:1 frequency.." newline hexmask.long.byte 0x0 0.--5. 1. "T_RAS_MIN,tRAS(min) - Specifies the minimum time between activate and precharge to the same bank. When the controller is operating in 1:2 frequency mode 1T mode program this to tRAS(min)/2. No rounding up. When the controller is operating in 1:2.." line.long 0x4 "DRAMTMG1,[FREQ3] SDRAM Timing Register 1" hexmask.long.byte 0x4 16.--20. 1. "T_XP,tXP - Specifies the minimum time after power-down exit to any operation. For DDR3 this must be programmed to tXPDLL if slow powerdown exit is selected in MR0[12]. If C/A parity for DDR4 is used set to (tXP+PL) instead. If LPDDR4 is selected and.." newline hexmask.long.byte 0x4 8.--13. 1. "RD2PRE,tRTP - Specifies the minimum time from read to precharge of same bank. - DDR2 - tAL + BL/2 + max(tRTP 2) - 2 - DDR3 - tAL + max (tRTP 4) - DDR4 - Max of following two equations: tAL + max (tRTP 4) or RL + BL/2 - tRP (*). - mDDR - BL/2 - LPDDR2.." newline hexmask.long.byte 0x4 0.--6. 1. "T_RC,tRC - Specifies the minimum time between activates to same bank. When the controller is operating in 1:2 frequency ratio mode program this to (tRC/2) and round up to next integer value. Unit: DFI clock cycles. Programming Mode: Quasi-dynamic Group.." line.long 0x8 "DRAMTMG2,[FREQ3] SDRAM Timing Register 2" hexmask.long.byte 0x8 24.--29. 1. "WRITE_LATENCY,Set this field to WL. Indicates the Time from write command to write data on SDRAM interface. This must be set to WL. For mDDR it must be set to 1. Note that depending on the PHY if using RDIMM/LRDIMM it might be necessary to adjust the.." newline hexmask.long.byte 0x8 16.--21. 1. "READ_LATENCY,Set this field to RL. Indicates the time from read command to read data on SDRAM interface. This must be set to RL. Note that depending on the PHY if using RDIMM/LRDIMM it might be necessary to adjust the value of RL to compensate for the.." newline hexmask.long.byte 0x8 8.--13. 1. "RD2WR,DDR2/3/mDDR: RL + BL/2 + 2 - WL DDR4: RL + BL/2 + 1 + WR_PREAMBLE - WL LPDDR2/LPDDR3: RL + BL/2 + RU(tDQSCKmax/tCK) + 1 - WL LPDDR4(DQ ODT is Disabled): RL + BL/2 + RU(tDQSCKmax/tCK) + WR_PREAMBLE + RD_POSTAMBLE - WL LPDDR4(DQ ODT is Enabled): RL +.." newline hexmask.long.byte 0x8 0.--5. 1. "WR2RD,DDR4: CWL + PL + BL/2 + tWTR_L LPDDR2/3/4: WL + BL/2 + tWTR + 1 Others: CWL + BL/2 + tWTR In DDR4 minimum time from write command to read command for same bank group. In others minimum time from write command to read command. Includes time for.." line.long 0xC "DRAMTMG3,[FREQ3] SDRAM Timing Register 3" hexmask.long.word 0xC 20.--29. 1. "T_MRW,Indicates the time to wait after a mode register write or read (MRW or MRR). Present only in designs configured to support LPDDR2 LPDDR3 or LPDDR4. LPDDR2 typically requires value of 5. LPDDR3 typically requires value of 10. LPDDR4: Set this to.." newline hexmask.long.byte 0xC 12.--17. 1. "T_MRD,tMRD- Indicates the number of cycles to wait after a mode register write or read. Depending on the connected SDRAM tMRD represents: - DDR2/mDDR: Time from MRS to any command - DDR3/4: Time from MRS to MRS command - LPDDR2: not used - LPDDR3/4:.." newline hexmask.long.word 0xC 0.--9. 1. "T_MOD,tMOD - Parameter used only in DDR3 and DDR4. Indicates the number of cycles between load mode command and following non-load mode command. If C/A parity for DDR4 is used set to tMOD_PAR(tMOD+PL) instead. If CAL mode is enabled.." line.long 0x10 "DRAMTMG4,[FREQ3] SDRAM Timing Register 4" hexmask.long.byte 0x10 24.--28. 1. "T_RCD,tRCD - tAL: Indicates the minimum time from activate to read or write command to same bank. When the controller is operating in 1:2 frequency ratio mode program this to ((tRCD - tAL)/2) and round it up to the next integer value. Minimum value.." newline hexmask.long.byte 0x10 16.--19. 1. "T_CCD,DDR4: tCCD_L: This is the minimum time between two reads or two writes for same bank group. Others: tCCD: This is the minimum time between two reads or two writes. When the controller is operating in 1:2 frequency ratio mode program this to.." newline hexmask.long.byte 0x10 8.--11. 1. "T_RRD,DDR4: tRRD_L: This is the minimum time between activates from bank 'a' to bank 'b' for same bank group. Others: tRRD: Minimum time between activates from bank 'a' to bank 'b' When the controller is operating in 1:2 frequency ratio mode program.." newline hexmask.long.byte 0x10 0.--4. 1. "T_RP,tRP: Indicates the minimum time from single-bank precharge to activate of same bank. When the controller is operating in 1:1 frequency ratio mode t_rp must be set to RoundUp(tRP/tCK). When the controller is operating in 1:2 frequency ratio mode.." line.long 0x14 "DRAMTMG5,[FREQ3] SDRAM Timing Register 5" hexmask.long.byte 0x14 24.--27. 1. "T_CKSRX,This is the time before self-refresh Exit that CK is maintained as a valid clock before issuing SRX. Specifies the clock stable time before SRX. Recommended settings: - mDDR - 1 - LPDDR2 - 2 - LPDDR3 - 2 - LPDDR4 - tCKCKEH - DDR2 - 1 - DDR3 -.." newline hexmask.long.byte 0x14 16.--19. 1. "T_CKSRE,This is the time after self-refresh Down Entry that CK is maintained as a valid clock. Specifies the clock disable delay after SRE. Recommended settings: - mDDR - 0 - LPDDR2 - 2 - LPDDR3 - 2 - LPDDR4 - tCKELCK - DDR2 - 1 - DDR3 - Max (10 ns 5.." newline hexmask.long.byte 0x14 8.--13. 1. "T_CKESR,Indicates the minimum CKE low width for self-refresh or self-refresh power down entry to exit timing in memory clock cycles. Recommended settings: - mDDR - tRFC - LPDDR2 - tCKESR - LPDDR3 - tCKESR - LPDDR4 - max(tCKE tSR) - DDR2 - tCKE - DDR3 -.." newline hexmask.long.byte 0x14 0.--4. 1. "T_CKE,Indicates the minimum number of cycles of CKE HIGH/LOW during power-down and self-refresh. - LPDDR2/LPDDR3 mode - Set this to the larger of tCKE or tCKESR - LPDDR4 mode - Set this to the larger of tCKE or tSR - Non-LPDDR2/non-LPDDR3/non-LPDDR4.." line.long 0x18 "DRAMTMG6,[FREQ3] SDRAM Timing Register 6" hexmask.long.byte 0x18 24.--27. 1. "T_CKDPDE,This is the time after Deep Power Down Entry that CK is maintained as a valid clock. Specifies the clock disable delay after DPDE. Recommended settings: - mDDR: 0 - LPDDR2: 2 - LPDDR3: 2 When the controller is operating in 1:2 frequency ratio.." newline hexmask.long.byte 0x18 16.--19. 1. "T_CKDPDX,This is the time before Deep Power Down Exit that CK is maintained as a valid clock before issuing DPDX. Specifies the clock stable time before DPDX. Recommended settings: - mDDR - 1 - LPDDR2 - 2 - LPDDR3 - 2 When the controller is operating in.." newline hexmask.long.byte 0x18 0.--3. 1. "T_CKCSX,This is the time before Clock Stop Exit that CK is maintained as a valid clock before issuing Clock Stop Exit. Specifies the clock stable time before next command after Clock Stop Exit. Recommended settings: - mDDR - 1 - LPDDR2 - tXP + 2 - LPDDR3.." line.long 0x1C "DRAMTMG7,[FREQ3] SDRAM Timing Register 7" hexmask.long.byte 0x1C 8.--11. 1. "T_CKPDE,This is the time after Power Down Entry that CK is maintained as a valid clock. Specifies the clock disable delay after PDE. Recommended settings: - mDDR - 0 - LPDDR2 - 2 - LPDDR3 - 2 - LPDDR4 - tCKELCK When using DDR2/3/4 SDRAM this register.." newline hexmask.long.byte 0x1C 0.--3. 1. "T_CKPDX,This is the time before Power Down Exit that CK is maintained as a valid clock before issuing PDX. Specifies the clock stable time before PDX. Recommended settings: - mDDR - 0 - LPDDR2 - 2 - LPDDR3 - 2 - LPDDR4 - tCKCKEH When using DDR2/3/4 SDRAM.." line.long 0x20 "DRAMTMG8,[FREQ3] SDRAM Timing Register 8" hexmask.long.byte 0x20 24.--30. 1. "T_XS_FAST_X32,tXS_FAST: Exit self-refresh to ZQCL ZQCS and MRS (only CL WR RTP and Geardown mode). When the controller is operating in 1:2 frequency ratio mode program this to the previous value divided by 2 and round up to next integer value. Note:.." newline hexmask.long.byte 0x20 16.--22. 1. "T_XS_ABORT_X32,tXS_ABORT: Exit self-refresh to commands not requiring a locked DLL in self-refresh Abort. When the controller is operating in 1:2 frequency ratio mode program this to the previous value divided by 2 and round up to next integer value." newline hexmask.long.byte 0x20 8.--14. 1. "T_XS_DLL_X32,tXSDLL: Exit self-refresh to commands requiring a locked DLL. When the controller is operating in 1:2 frequency ratio mode program this to the previous value divided by 2 and round up to next integer value. Note: Used only for DDR2 DDR3.." newline hexmask.long.byte 0x20 0.--6. 1. "T_XS_X32,tXS: Exit self-refresh to commands not requiring a locked DLL. When the controller is operating in 1:2 frequency ratio mode program this to the previous value divided by 2 and round up to next integer value. Note: Used only for DDR2 DDR3 and.." line.long 0x24 "DRAMTMG9,[FREQ3] SDRAM Timing Register 9" bitfld.long 0x24 30. "DDR4_WR_PREAMBLE,DDR4 Write preamble mode. - 0 - 1tCK preamble - 1 - 2tCK preamble Present only with MEMC_FREQ_RATIO=2. Programming Mode: Quasi-dynamic Group 2 Group 4" "0,1" newline bitfld.long 0x24 16.--18. "T_CCD_S,tCCD_S: This is the minimum time between two reads or two writes for different bank group. For bank switching (from bank 'a' to bank 'b') the minimum time is this value + 1. When the controller is operating in 1:2 frequency ratio mode program.." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x24 8.--11. 1. "T_RRD_S,tRRD_S: This is the minimum time between activates from bank 'a' to bank 'b' for different bank group. When the controller is operating in 1:2 frequency ratio mode program this to (tRRD_S/2) and round it up to the next integer value. Present.." newline hexmask.long.byte 0x24 0.--5. 1. "WR2RD_S,CWL + PL + BL/2 + tWTR_S Minimum time from write command to read command for different bank group. Includes time for bus turnaround recovery times and all per-bank per-rank and global constraints. Present only in designs configured to support.." line.long 0x28 "DRAMTMG10,[FREQ3] SDRAM Timing Register 10" hexmask.long.byte 0x28 16.--20. 1. "T_SYNC_GEAR,Indicates the time between MRS command and the sync pulse time. This must be even number of clocks. For DDR4-2666 and DDR4-3200 this parameter is defined as tMOD(min)+4nCK tMOD(min) is greater of 24nCK or 15ns 15ns / .625ns = 24 Max value.." newline hexmask.long.byte 0x28 8.--12. 1. "T_CMD_GEAR,Indicates a sync pulse to first valid command. For DDR4-2666 and DDR4-3200 this parameter is defined as tMOD(min) tMOD(min) is greater of 24nCK or 15ns 15ns / .625ns = 24 Max value for this register is 24 When the controller is operating in.." newline bitfld.long 0x28 2.--3. "T_GEAR_SETUP,Indicates the geardown setup time. Minimum value of this register is 1. Zero is invalid. For DDR4-2666 and DDR4-3200 this parameter is defined as 2 clks When the controller is operating in 1:2 frequency ratio mode program this to.." "0,1,2,3" newline bitfld.long 0x28 0.--1. "T_GEAR_HOLD,Indicates the geardown hold time. Minimum value of this register is 1. Zero is invalid. For DDR4-2666 and DDR4-3200 this parameter is defined as 2 clks When the controller is operating in 1:2 frequency ratio mode program this to.." "0,1,2,3" line.long 0x2C "DRAMTMG11,[FREQ3] SDRAM Timing Register 11" hexmask.long.byte 0x2C 24.--30. 1. "POST_MPSM_GAP_X32,tXMPDLL: This is the minimum Exit MPSM to commands requiring a locked DLL. When the controller is operating in 1:2 frequency ratio mode program this to (tXMPDLL/2) and round it up to the next integer value. Present only in designs.." newline hexmask.long.byte 0x2C 16.--20. 1. "T_MPX_LH,tMPX_LH: This is the minimum CS_n Low hold time to CKE rising edge. When the controller is operating in 1:2 frequency ratio mode program this to RoundUp(tMPX_LH/2)+1. Present only in designs configured to support DDR4. Unit: DFI clock cycles." newline bitfld.long 0x2C 8.--9. "T_MPX_S,tMPX_S: This is the minimum time CS setup time to CKE. When the controller is operating in 1:2 frequency ratio mode program this to (tMPX_S/2) and round it up to the next integer value. Present only in designs configured to support DDR4. Unit:.." "0,1,2,3" newline hexmask.long.byte 0x2C 0.--4. 1. "T_CKMPE,tCKMPE: This is the minimum valid clock requirement after MPSM entry. Present only in designs configured to support DDR4. When the controller is operating in 1:2 frequency ratio mode divide the value calculated using the previous equation by 2.." line.long 0x30 "DRAMTMG12,[FREQ3] SDRAM Timing Register 12" hexmask.long.byte 0x30 24.--29. 1. "T_WR_MPR,This bit is used only in DDR4. Cycles between MPR Write and other command. Set this to tMOD + AL (or tMOD + PL + AL if C/A parity is also used). When the controller is operating in 1:2 frequency ratio mode program this to (tWR_MPR/2) and round.." newline bitfld.long 0x30 16.--17. "T_CMDCKE,tCMDCKE: Indicates the delay from valid command to CKE input LOW. Set this to the larger of tESCKE or tCMDCKE When the controller is operating in 1:2 frequency ratio mode program this to (max(tESCKE tCMDCKE)/2) and round it up to the next.." "0,1,2,3" newline hexmask.long.byte 0x30 0.--4. 1. "T_MRD_PDA,tMRD_PDA: This is the Mode Register Set command cycle time in PDA mode. When the controller is operating in 1:2 frequency ratio mode program this to (tMRD_PDA/2) and round it up to the next integer value. Unit: DFI clock cycles. Programming.." line.long 0x34 "DRAMTMG13,[FREQ3] SDRAM Timing Register 13" hexmask.long.byte 0x34 24.--30. 1. "ODTLOFF,LPDDR4: ODTLoff: This is the latency from CAS-2 command to ODToff reference. When the controller is operating in 1:2 frequency ratio mode program this to (ODTLoff/2) and round it up to the next integer value. Unit: DFI clock cycles. Programming.." newline hexmask.long.byte 0x34 16.--21. 1. "T_CCD_MW,LPDDR4: tCCDMW: This is the minimum time from write or masked write to masked write command for same bank. When the controller is operating in 1:2 frequency ratio mode program this to (tCCDMW/2) and round it up to the next integer value. Unit:.." newline bitfld.long 0x34 0.--2. "T_PPD,LPDDR4: tPPD: This is the minimum time from precharge to precharge command. When the controller is operating in 1:2 frequency ratio mode program this to (tPPD/2) and round it up to the next integer value. Unit: DFI clock cycles. Programming Mode:.." "?,?,?,?,tPPD: This is the minimum time from precharge to..,?,?,?" line.long 0x38 "DRAMTMG14,[FREQ3] SDRAM Timing Register 14" hexmask.long.word 0x38 0.--11. 1. "T_XSR,tXSR: This is the exit self-refresh to any command. When the controller is operating in 1:2 frequency ratio mode program this to the previous value divided by 2 and round up to next integer value. The value 0xfff is illegal for this register.." line.long 0x3C "DRAMTMG15,[FREQ3] SDRAM Timing Register 15" bitfld.long 0x3C 31. "EN_DFI_LP_T_STAB,- 1 - Enable using tSTAB when exiting DFI LP. This must be set when the PHY is stopping the clock during DFI LP to save maximum power. - 0 - Disable using tSTAB when exiting DFI LP. Programming Mode: Quasi-dynamic Group 2 Group 4" "Disable using tSTAB when exiting DFI LP,Enable using tSTAB when exiting DFI LP" newline hexmask.long.byte 0x3C 0.--7. 1. "T_STAB_X32,tSTAB: Stabilization time. It is required in the following two cases for DDR3/DDR4 RDIMM: - When exiting power saving mode if the clock is stopped after re-enabling it the clock must be stable for a time specified by tSTAB - In the case of.." group.long 0x180++0x3 line.long 0x0 "ZQCTL0,[FREQ3] ZQ Control Register 0" bitfld.long 0x0 31. "DIS_AUTO_ZQ,- 1 - Disable uMCTL2 generation of ZQCS/MPC(ZQ calibration) command. Register DBGCMD.zq_calib_short can be used instead to issue ZQ calibration request from APB module - 0 - Internally generate ZQCS/MPC(ZQ calibration) commands based on.." "Internally generate ZQCS/MPC,Disable uMCTL2 generation of ZQCS/MPC" newline bitfld.long 0x0 30. "DIS_SRX_ZQCL,- 1 - Disable issuing of ZQCL/MPC(ZQ calibration) command at self-refresh/SR-Powerdown exit. Only applicable when run in DDR3 or DDR4 or LPDDR2 or LPDDR3 or LPDDR4 mode - 0 - Enable issuing of ZQCL/MPC(ZQ calibration) command at.." "Enable issuing of ZQCL/MPC,Disable issuing of ZQCL/MPC" newline bitfld.long 0x0 29. "ZQ_RESISTOR_SHARED,- 1 - Denotes that ZQ resistor is shared between ranks. Means ZQinit/ZQCL/ZQCS/MPC(ZQ calibration) commands are sent to one rank at a time with tZQinit/tZQCL/tZQCS/tZQCAL/tZQLAT timing met between commands so that commands to different.." "ZQ resistor is not shared,Denotes that ZQ resistor is shared between ranks" newline bitfld.long 0x0 28. "DIS_MPSMX_ZQCL,- 1 - Disable issuing of ZQCL command at Maximum Power Saving Mode exit. Only applicable when run in DDR4 mode - 0 - Enable issuing of ZQCL command at Maximum Power Saving Mode exit. Only applicable when run in DDR4 mode This is only.." "Enable issuing of ZQCL command at Maximum Power..,Disable issuing of ZQCL command at Maximum Power.." newline hexmask.long.word 0x0 16.--26. 1. "T_ZQ_LONG_NOP,tZQoper for DDR3/DDR4 tZQCL for LPDDR2/LPDDR3 tZQCAL for LPDDR4: Number of DFI clock cycles of NOP required after a ZQCL (ZQ calibration long)/MPC(ZQ Start) command is issued to SDRAM. When the controller is operating in 1:2 frequency.." newline hexmask.long.word 0x0 0.--9. 1. "T_ZQ_SHORT_NOP,tZQCS for DDR3/DD4/LPDDR2/LPDDR3 tZQLAT for LPDDR4: Number of DFI clock cycles of NOP required after a ZQCS (ZQ calibration short)/MPC(ZQ Latch) command is issued to SDRAM. When the controller is operating in 1:2 frequency ratio mode.." group.long 0x190++0x7 line.long 0x0 "DFITMG0,[FREQ3] DFI Timing Register 0" hexmask.long.byte 0x0 24.--28. 1. "DFI_T_CTRL_DELAY,Specifies the number of DFI clock cycles after an assertion or de-assertion of the DFI control signals that the control signals at the PHY-DRAM interface reflect the assertion or de-assertion. If the DFI clock and the memory clock are.." newline bitfld.long 0x0 23. "DFI_RDDATA_USE_DFI_PHY_CLK,Defines whether dfi_rddata_en/dfi_rddata/dfi_rddata_valid is generated using HDR (DFI clock) or SDR (DFI PHY clock) values. Selects whether value in DFITMG0.dfi_t_rddata_en is in terms of HDR (DFI clock) or SDR (DFI PHY clock).." "Else,?" newline hexmask.long.byte 0x0 16.--22. 1. "DFI_T_RDDATA_EN,Time from the assertion of a read command on the DFI interface to the assertion of the dfi_rddata_en signal. Refer to PHY specification for correct value. This corresponds to the DFI parameter trddata_en. Note that depending on the PHY.." newline bitfld.long 0x0 15. "DFI_WRDATA_USE_DFI_PHY_CLK,Defines whether dfi_wrdata_en/dfi_wrdata/dfi_wrdata_mask is generated using HDR (DFI clock) or SDR (DFI PHY clock) values. Selects whether value in DFITMG0.dfi_tphy_wrlat is in terms of HDR (DFI clock) or SDR (DFI PHY clock).." "Else,?" newline hexmask.long.byte 0x0 8.--13. 1. "DFI_TPHY_WRDATA,Specifies the number of clock cycles between when dfi_wrdata_en is asserted to when the associated write data is driven on the dfi_wrdata signal. This corresponds to the DFI timing parameter tphy_wrdata. For more information on correct.." newline hexmask.long.byte 0x0 0.--5. 1. "DFI_TPHY_WRLAT,Write latency. Number of clocks from the write command to write data enable (dfi_wrdata_en). This corresponds to the DFI timing parameter tphy_wrlat. Refer to PHY specification for correct value.Note that depending on the PHY if using.." line.long 0x4 "DFITMG1,[FREQ3] DFI Timing Register 1" hexmask.long.byte 0x4 28.--31. 1. "DFI_T_CMD_LAT,Specifies the number of DFI PHY clock cycles between when the dfi_cs signal is asserted and when the associated command is driven. This field is used for CAL mode must be set to '0' or tCAL which matches the CAL mode register setting in.." newline bitfld.long 0x4 24.--25. "DFI_T_PARIN_LAT,Specifies the number of DFI PHY clock cycles between when the dfi_cs signal is asserted and when the associated dfi_parity_in signal is driven. Unit: DFI PHY clock cycles. Programming Mode: Quasi-dynamic Group 4" "0,1,2,3" newline hexmask.long.byte 0x4 16.--20. 1. "DFI_T_WRDATA_DELAY,Specifies the number of DFI clock cycles between when the dfi_wrdata_en signal is asserted and when the corresponding write data transfer is completed on the DRAM bus. This corresponds to the DFI timing parameter twrdata_delay. For.." newline hexmask.long.byte 0x4 8.--12. 1. "DFI_T_DRAM_CLK_DISABLE,Specifies the number of DFI clock cycles from the assertion of the dfi_dram_clk_disable signal on the DFI until the clock to the DRAM memory devices at the PHY-DRAM boundary maintains a low value. If the DFI clock and the memory.." newline hexmask.long.byte 0x4 0.--4. 1. "DFI_T_DRAM_CLK_ENABLE,Specifies the number of DFI clock cycles from the de-assertion of the dfi_dram_clk_disable signal on the DFI until the first valid rising edge of the clock to the DRAM memory devices at the PHY-DRAM boundary. If the DFI clock and.." group.long 0x1B4++0x7 line.long 0x0 "DFITMG2,[FREQ3] DFI Timing Register 2" hexmask.long.byte 0x0 8.--14. 1. "DFI_TPHY_RDCSLAT,specifies the number of DFI PHY clock cycles between when a read command is sent on the DFI control interface and when the associated dfi_rddata_cs signal is asserted. This corresponds to the DFI timing parameter tphy_rdcslat. Refer to.." newline hexmask.long.byte 0x0 0.--5. 1. "DFI_TPHY_WRCSLAT,Specifies the number of DFI PHY clock cycles between when a write command is sent on the DFI control interface and when the associated dfi_wrdata_cs signal is asserted. This corresponds to the DFI timing parameter tphy_wrcslat. For more.." line.long 0x4 "DFITMG3,[FREQ3] DFI Timing Register 3" hexmask.long.byte 0x4 0.--4. 1. "DFI_T_GEARDOWN_DELAY,The delay from dfi_geardown_en assertion to the time of the PHY being ready to receive commands. Refer to PHY specification for correct value. When the controller is operating in 1:2 frequency ratio mode program this to.." group.long 0x240++0x3 line.long 0x0 "ODTCFG,[FREQ3] ODT Configuration Register" hexmask.long.byte 0x0 24.--27. 1. "WR_ODT_HOLD,DFI PHY clock cycles to hold ODT for a write command. The minimum supported value is 2. Recommended values: DDR2: - BL8 - 0x5 (DDR2-400/533/667) 0x6 (DDR2-800) 0x7 (DDR2-1066) - BL4 - 0x3 (DDR2-400/533/667) 0x4 (DDR2-800) 0x5 (DDR2-1066).." newline hexmask.long.byte 0x0 16.--20. 1. "WR_ODT_DELAY,Indicates the delay in DFI PHY clock cycles from issuing a write command to setting ODT values associated with that command. ODT setting must remain constant for the entire time that DQS is driven by the uMCTL2. Recommended values: DDR2: -.." newline hexmask.long.byte 0x0 8.--11. 1. "RD_ODT_HOLD,DFI PHY clock cycles to hold ODT for a read command. The minimum supported value is 2. Recommended values: DDR2: - BL8 - 0x6 (not DDR2-1066) 0x7 (DDR2-1066) - BL4 - 0x4 (not DDR2-1066) 0x5 (DDR2-1066) DDR3: - BL8 - 0x6 DDR4: - BL8 - 5 +.." newline hexmask.long.byte 0x0 2.--6. 1. "RD_ODT_DELAY,Indicates the delay in DFI PHY clock cycles from issuing a read command to setting ODT values associated with that command. ODT setting must remain constant for the entire time that DQS is driven by the uMCTL2. Recommended values: DDR2: -.." tree.end tree.end tree "DDR_PHY" base ad:0x32000000 tree "UMCTL2_REGS (uMCTL2 DDRC Registers)" group.long 0x0++0x3 line.long 0x0 "MSTR,Master Register0" bitfld.long 0x0 30.--31. "DEVICE_CONFIG,Indicates the configuration of the device used in the system. - 00 - x4 device - 01 - x8 device - 10 - x16 device - 11 - x32 device Programming Mode: Static" "x4 device,x8 device,?,?" newline bitfld.long 0x0 29. "FREQUENCY_MODE,Selects which registers are used. - 0 - Original registers - 1 - When UMCTL2_FREQUENCY_NUM=2: FREQ1 registers When UMCTL2_FREQUENCY_NUM>2: Choosen by MSTR2.target_frequency register. Programming Mode: Quasi-dynamic Group 2" "Original registers,When UMCTL2_FREQUENCY_NUM=2: FREQ1 registers" newline rbitfld.long 0x0 26.--28. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 24.--25. "ACTIVE_RANKS,Only present for multi-rank configurations. Each bit represents one rank. For two-rank configurations only bits[25:24] are present. - 1 - Populated - 0 - Unpopulated LSB is the lowest rank number. For two ranks following combinations are.." "Unpopulated,One rank,?,?" newline hexmask.long.byte 0x0 20.--23. 1. "RESERVED,Reserved" newline hexmask.long.byte 0x0 16.--19. 1. "BURST_RDWR,Indicates SDRAM burst length used: - 0001 - Burst length of 2 (only supported for mDDR) - 0010 - Burst length of 4 - 0100 - Burst length of 8 - 1000 - Burst length of 16 (only supported for mDDR LPDDR2 and LPDDR4) All other values are.." newline bitfld.long 0x0 15. "DLL_OFF_MODE,Set to: - 1 - When the uMCTL2 and DRAM has to be put in DLL-off mode for low frequency operation - 0 - To put uMCTL2 and DRAM in DLL-on mode for normal frequency operation If DDR4 CRC/parity retry is enabled.." "To put uMCTL2 and DRAM in DLL-on mode for normal..,When the uMCTL2 and DRAM has to be put in.." newline rbitfld.long 0x0 14. "RESERVED,Reserved" "0,1" newline bitfld.long 0x0 12.--13. "DATA_BUS_WIDTH,Selects proportion of DQ bus width that is used by the SDRAM. - 00 - Full DQ bus width to SDRAM - 01 - Half DQ bus width to SDRAM - 10 - Quarter DQ bus width to SDRAM - 11 - Reserved Note that half bus width mode is only supported when the.." "Full DQ bus width to SDRAM,Half DQ bus width to SDRAM,?,?" newline bitfld.long 0x0 11. "GEARDOWN_MODE,- 1 - Indicates the DRAM in geardown mode (2N) - 0 - Indicates the DRAM in normal mode (1N) This register can be changed only when the controller is in the self-refresh mode. This signal must be set the same value as MR3 bit A3. Note: -.." "Indicates the DRAM in normal mode,Indicates the DRAM in geardown mode" newline bitfld.long 0x0 10. "EN_2T_TIMING_MODE,If 1 then uMCTL2 uses 2T timing otherwise uses 1T timing. In 2T timing all command signals (except chip select) are held for 2 clocks on the SDRAM bus. Chip select is asserted on the second cycle of the command. Note: - 2T timing is.." "0,1" newline bitfld.long 0x0 9. "BURSTCHOP,When this bit is set enables burst-chop (BC4 or 8 on-the-fly) in DDR3/DDR4. Burst Chop for reads is exercised only: - In HIF configurations (UMCTL2_INCL_ARB not set) - If in full bus width mode (MSTR.data_bus_width = 00) - If.." "0,1" newline rbitfld.long 0x0 6.--8. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 5. "LPDDR4,Selects LPDDR4 SDRAM. - 1 - LPDDR4 SDRAM device in use - 0 - non-LPDDR4 device in use Present only in designs configured to support LPDDR4. Programming Mode: Static" "non-LPDDR4 device in use,LPDDR4 SDRAM device in use" newline bitfld.long 0x0 4. "DDR4,Selects DDR4 SDRAM. - 1 - DDR4 SDRAM device in use - 0 - non-DDR4 device in use Present only in designs configured to support DDR4. Programming Mode: Static" "non-DDR4 device in use,DDR4 SDRAM device in use" newline bitfld.long 0x0 3. "LPDDR3,Selects LPDDR3 SDRAM. - 1 - LPDDR3 SDRAM device in use - 0 - non-LPDDR3 device in use Present only in designs configured to support LPDDR3. Programming Mode: Static" "non-LPDDR3 device in use,LPDDR3 SDRAM device in use" newline bitfld.long 0x0 2. "LPDDR2,Selects LPDDR2 SDRAM. - 1 - LPDDR2 SDRAM device in use - 0 - non-LPDDR2 device in use Present only in designs configured to support LPDDR2. Programming Mode: Static" "non-LPDDR2 device in use,LPDDR2 SDRAM device in use" newline rbitfld.long 0x0 1. "RESERVED,Reserved" "0,1" newline bitfld.long 0x0 0. "DDR3,Selects DDR3 SDRAM. - 1 - DDR3 SDRAM device in use - 0 - non-DDR3 SDRAM device in use Present only in designs configured to support DDR3. Programming Mode: Static" "non-DDR3 SDRAM device in use,DDR3 SDRAM device in use" rgroup.long 0x4++0x3 line.long 0x0 "STAT,Operating Mode Status Register" hexmask.long.tbyte 0x0 13.--31. 1. "RESERVED,Reserved" newline bitfld.long 0x0 12. "SELFREF_CAM_NOT_EMPTY,Self-refresh with CAMs not empty. Set to 1 when self-refresh is entered but CAMs are not drained. Cleared after exiting self-refresh. Programming Mode: Static" "0,1" newline bitfld.long 0x0 10.--11. "RESERVED,Reserved" "0,1,2,3" newline bitfld.long 0x0 8.--9. "SELFREF_STATE,This indicates self-refresh or self-refresh power down state for LPDDR4. This register is used for frequency change and MRR/MRW access during self-refresh. - 00 - SDRAM is not in self-refresh - 01 - Self-refresh 1 - 10 - Self-refresh power.." "SDRAM is not in self-refresh,Self-refresh 1,?,?" newline bitfld.long 0x0 6.--7. "RESERVED,Reserved" "0,1,2,3" newline bitfld.long 0x0 4.--5. "SELFREF_TYPE,Flags if self-refresh (except LPDDR4) or SR-Powerdown (LPDDR4) is entered and if it is under automatic self-refresh control only or not. - 00 - SDRAM is not in self-refresh (except LPDDR4) or SR-Powerdown (LPDDR4). If retry is enabled by.." "SDRAM is not in self-refresh,SDRAM is in self-refresh,?,?" newline bitfld.long 0x0 3. "RESERVED,Reserved" "0,1" newline bitfld.long 0x0 0.--2. "OPERATING_MODE,This is 3-bits wide in configurations with mDDR/LPDDR2/LPDDR3/LPDDR4/DDR4 support and 2-bits in all other configurations. non-mDDR/LPDDR2/LPDDR3/LPDDR4 and non-DDR4 designs: - 00 - Init - 01 - Normal - 10 - Power-down - 11 - Self-refresh.." "Init,Normal,?,bits wide in configurations with..,?,?,?,?" group.long 0x10++0x7 line.long 0x0 "MRCTRL0,Mode Register Read/Write Control Register 0. Note: Do not enable more than one of the following fields simultaneously: - sw_init_int - pda_en - mpr_en" bitfld.long 0x0 31. "MR_WR,Setting this register bit to 1 triggers a mode register read or write operation. When the MR operation is complete the uMCTL2 automatically clears this bit. The other fields of this register must be written in a separate APB transaction before.." "0,1" newline bitfld.long 0x0 30. "PBA_MODE,Indicates whether PBA access is executed. When setting this bit to 1 along with setting pda_en to 1 uMCTL2 initiates PBA access instead of PDA access. - 0 - Per DRAM Addressability mode - 1 - Per Buffer Addressability mode The completion of PBA.." "Per DRAM Addressability mode,Per Buffer Addressability mode" newline hexmask.long.word 0x0 16.--29. 1. "RESERVED,Reserved" newline hexmask.long.byte 0x0 12.--15. 1. "MR_ADDR,Address of the mode register that is to be written to. - 0000 - MR0 - 0001 - MR1 - 0010 - MR2 - 0011 - MR3 - 0100 - MR4 - 0101 - MR5 - 0110 - MR6 - 0111 - MR7 Don't Care for LPDDR2/LPDDR3/LPDDR4 (see MRCTRL1.mr_data for mode register addressing.." newline hexmask.long.byte 0x0 6.--11. 1. "RESERVED,Reserved" newline bitfld.long 0x0 4.--5. "MR_RANK,Controls which rank is accessed by MRCTRL0.mr_wr. Normally it is desired to access all ranks so all bits must be set to 1. However for multi-rank UDIMMs/RDIMMs/LRDIMMs which implement address mirroring it might be necessary to access ranks.." "?,Select rank 0 only,Select rank 1 only,?" newline bitfld.long 0x0 3. "SW_INIT_INT,Indicates whether software intervention is allowed through MRCTRL0/MRCTRL1 before automatic SDRAM initialization routine or not. For DDR4 this bit can be used to initialize the DDR4 RCD (MR7) before automatic SDRAM initialization. For LPDDR4.." "Software intervention is not allowed,Software intervention is allowed" newline bitfld.long 0x0 2. "PDA_EN,Indicates whether the mode register operation is MRS in PDA mode or not. - 0 - MRS - 1 - MRS in Per DRAM Addressability mode Note that when pba_mode=1 PBA access is initiated instead of PDA access. Programming Mode: Dynamic" "MRS,MRS in Per DRAM Addressability mode" newline bitfld.long 0x0 1. "MPR_EN,Indicates whether the mode register operation is MRS or WR/RD for MPR (only supported for DDR4). - 0 - MRS - 1 - WR/RD for MPR Programming Mode: Dynamic" "MRS,WR/RD for MPR" newline bitfld.long 0x0 0. "MR_TYPE,Indicates whether the mode register operation is read or write. Only used for LPDDR2/LPDDR3/LPDDR4/DDR4. - 0 - Write - 1 - Read Programming Mode: Dynamic" "Write,Read" line.long 0x4 "MRCTRL1,Mode Register Read/Write Control Register 1" hexmask.long.word 0x4 18.--31. 1. "RESERVED,Reserved" newline hexmask.long.tbyte 0x4 0.--17. 1. "MR_DATA,Mode register write data for all non-LPDDR2/non-LPDDR3/non-LPDDR4 modes. For LPDDR2/LPDDR3/LPDDR4 MRCTRL1[15:0] are interpreted as: - [15:8] - MR Address - [7:0] - MR data for writes don't care for reads This is 18-bits wide in configurations.." rgroup.long 0x18++0x3 line.long 0x0 "MRSTAT,Mode Register Read/Write Status Register" hexmask.long.tbyte 0x0 9.--31. 1. "RESERVED,Reserved" newline bitfld.long 0x0 8. "PDA_DONE,The SoC might initiate a MR write operation in PDA/PBA mode only if this signal is low. This signal goes: - High when three consecutive MRS commands related to the PDA/PBA mode are issued to the SDRAM - Low when MRCTRL0.pda_en becomes 0.." "Indicates that mode register write operation..,Indicates that mode register write operation.." newline hexmask.long.byte 0x0 1.--7. 1. "RESERVED,Reserved" newline bitfld.long 0x0 0. "MR_WR_BUSY,The SoC might initiate a MR write operation only if this signal is low. This signal goes: - High in the clock after the uMCTL2 accepts the MRW/MRR request - Low when the MRW/MRR command is issued to the SDRAM It is recommended not to perform.." "Indicates that the SoC can initiate a mode..,Indicates that mode register write operation is.." group.long 0x1C++0x1F line.long 0x0 "MRCTRL2,Mode Register Read/Write Control Register 2" hexmask.long 0x0 0.--31. 1. "MR_DEVICE_SEL,Indicates the devices to be selected during the MRS that happens in PDA mode. Each bit is associated with one device. For example bit[0] corresponds to Device 0 bit[1] to Device 1 and so on. - 1 - Indicates that the MRS command must be.." line.long 0x4 "DERATEEN,Temperature Derate Enable Register" hexmask.long.tbyte 0x4 13.--31. 1. "RESERVED,Reserved" newline bitfld.long 0x4 12. "DERATE_MR4_TUF_DIS,Disables use of MR4 TUF flag (MR4[7]) bit. - 0 - Use MR4 TUF flag (MR4[7]) - 1 - Do not use MR4 TUF Flag (MR4[7]) For LPDDR4 it is recommended to set this register to 1. For LPDDR2 and LPDDR3 contact your memory vendor for.." "Use MR4 TUF flag,Do not use MR4 TUF Flag" newline rbitfld.long 0x4 11. "RESERVED,Reserved" "0,1" newline bitfld.long 0x4 8.--10. "RC_DERATE_VALUE,Derate value of tRC for LPDDR4. - 0 - Derating uses +1 - 1 - Derating uses +2 - 2 - Derating uses +3 - 3 - Derating uses +4 Present only in designs configured to support LPDDR4. The required cycles for derating can be determined by.." "Derating uses +1,Derating uses +2,Derating uses +3,Derating uses +4,?,?,?,?" newline hexmask.long.byte 0x4 4.--7. 1. "DERATE_BYTE,This bit indicates which byte of the MRR data is used for derating. The maximum valid value depends on MEMC_DRAM_TOTAL_DATA_WIDTH. Present only in designs configured to support LPDDR2/LPDDR3/LPDDR4. Programming Mode: Static" newline rbitfld.long 0x4 3. "RESERVED,Reserved" "0,1" newline bitfld.long 0x4 1.--2. "DERATE_VALUE,Derate value. - 0 - Derating uses +1 - 1 - Derating uses +2 Present only in designs configured to support LPDDR2/LPDDR3/LPDDR4. Set to 0 for all LPDDR2 speed grades as derating value of +1.875 ns is less than a core_ddrc_core_clk period. For.." "Derating uses +1,Derating uses +2,?,?" newline bitfld.long 0x4 0. "DERATE_ENABLE,Enables derating. - 0 - Timing parameter derating is disabled - 1 - Timing parameter derating is enabled using MR4 read value Present only in designs configured to support LPDDR2/LPDDR3/LPDDR4. This field must be set to '0' for.." "Timing parameter derating is disabled,Timing parameter derating is enabled using MR4.." line.long 0x8 "DERATEINT,Temperature Derate Interval Register" hexmask.long 0x8 0.--31. 1. "MR4_READ_INTERVAL,Interval between two MR4 reads used to derate the timing parameters. Present only in designs configured to support LPDDR2/LPDDR3/LPDDR4. This register must not be set to zero. Unit: DFI clock cycles. Programming Mode: Static" line.long 0xC "MSTR2,Master Register2" hexmask.long 0xC 2.--31. 1. "RESERVED,Reserved" newline bitfld.long 0xC 0.--1. "TARGET_FREQUENCY,If MSTR.frequency_mode = 1 this field specifies the target frequency. - 0 - Frequency 0/Normal - 1 - Frequency 1/FREQ1 - 2 - Frequency 2/FREQ2 - 3 - Frequency 3/FREQ3 If MSTR.frequency_mode=0 this field is ignored. Note: If the target.." "Frequency 0/Normal,Frequency 1/FREQ1,Frequency 2/FREQ2,Frequency 3/FREQ3" line.long 0x10 "DERATECTL,Temperature Derate Control Register" hexmask.long 0x10 3.--31. 1. "RESERVED,Reserved" newline bitfld.long 0x10 2. "DERATE_TEMP_LIMIT_INTR_FORCE,Interrupt force bit for derate_temp_limit_intr. Setting this field to 1 causes the derate_temp_limit_intr output pin to be asserted. At the end of the interrupt force operation the uMCTL2 automatically clears this bit." "0,1" newline bitfld.long 0x10 1. "DERATE_TEMP_LIMIT_INTR_CLR,Interrupt clear bit for derate_temp_limit_intr. At the end of the interrupt clear operation the uMCTL2 automatically clears this bit. Programming Mode: Dynamic" "0,1" newline bitfld.long 0x10 0. "DERATE_TEMP_LIMIT_INTR_EN,Interrupt enable bit for derate_temp_limit_intr output pin. - 1 - Enabled - 0 - Disabled Programming Mode: Dynamic" "Disabled,Enabled" line.long 0x14 "PWRCTL,Low Power Control Register" hexmask.long.tbyte 0x14 9.--31. 1. "RESERVED,Reserved" newline bitfld.long 0x14 8. "LPDDR4_SR_ALLOWED,Indicates whether transition from SR-PD to SR and back to SR-PD is allowed. This register field cannot be modified while PWRCTL.selfref_sw == 1. - 0 - SR-PD -> SR -> SR-PD not allowed - 1 - SR-PD -> SR -> SR-PD allowed Programming Mode:.." "SR-PD,SR-PD" newline bitfld.long 0x14 7. "DIS_CAM_DRAIN_SELFREF,Indicates whether skipping CAM draining is allowed when entering self-refresh. This register field cannot be modified while PWRCTL.selfref_sw == 1. - 0 - CAMs must be empty before entering SR - 1 - CAMs are not emptied before.." "CAMs must be empty before entering SR,CAMs are not emptied before entering SR" newline bitfld.long 0x14 6. "STAY_IN_SELFREF,Self-refresh state is an intermediate state to enter to self-refresh power down state or exit self-refresh power down state for LPDDR4. This register controls transition from the self-refresh state. - 1 - Prohibit transition from.." "Allow transition from self-refresh state,Prohibit transition from self-refresh state" newline bitfld.long 0x14 5. "SELFREF_SW,A value of 1 to this register causes system to move to self-refresh state immediately as long as it is not in INIT or DPD/MPSM operating_mode. This is referred to as Software Entry/Exit to self-refresh. - 1 - Software Entry to self-refresh -.." "Software Exit from self-refresh,Software Entry to self-refresh" newline bitfld.long 0x14 4. "MPSM_EN,When this bit is 1 the uMCTL2 puts the SDRAM into maximum power saving mode when the transaction store is empty. This register must be reset to '0' to bring uMCTL2 out of maximum power saving mode. Present only in designs configured to support.." "0,1" newline bitfld.long 0x14 3. "EN_DFI_DRAM_CLK_DISABLE,Enables the assertion of dfi_dram_clk_disable whenever a clock is not required by the SDRAM. If set to 0 dfi_dram_clk_disable is never asserted. Assertion of dfi_dram_clk_disable is as follows: In DDR2/DDR3 can only be asserted.." "0,1" newline bitfld.long 0x14 2. "DEEPPOWERDOWN_EN,When this bit is 1 uMCTL2 puts the SDRAM into deep power-down mode when the transaction store is empty. This register must be reset to '0' to bring uMCTL2 out of deep power-down mode. The controller performs automatic SDRAM.." "0,1" newline bitfld.long 0x14 1. "POWERDOWN_EN,If true then the uMCTL2 goes into power-down after a programmable number of cycles 'maximum idle clocks before power down' (PWRTMG.powerdown_to_x32). This register bit may be re-programmed during the course of normal operation. Programming.." "0,1" newline bitfld.long 0x14 0. "SELFREF_EN,If true then the uMCTL2 puts the SDRAM into self-refresh after a programmable number of cycles 'maximum idle clocks before self-refresh (PWRTMG.selfref_to_x32)'. This register bit may be re-programmed during the course of normal operation." "0,1" line.long 0x18 "PWRTMG,Low Power Timing Register" hexmask.long.byte 0x18 24.--31. 1. "RESERVED,Reserved" newline hexmask.long.byte 0x18 16.--23. 1. "SELFREF_TO_X32,After this many clocks of the DDRC command channel being idle the uMCTL2 automatically puts the SDRAM into self-refresh. The DDRC command channel is considered idle when there are no HIF commands outstanding. This must be enabled in the.." newline hexmask.long.byte 0x18 8.--15. 1. "T_DPD_X4096,Minimum deep power-down time. For mDDR value from the JEDEC specification is 0 as mDDR exits from deep power-down mode immediately after PWRCTL.deeppowerdown_en is de-asserted. For LPDDR2/LPDDR3 value from the JEDEC specification is 500us." newline rbitfld.long 0x18 5.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x18 0.--4. 1. "POWERDOWN_TO_X32,After this many clocks of the DDRC command channel being idle the uMCTL2 automatically puts the SDRAM into power-down. The DDRC command channel is considered idle when there are no HIF commands outstanding. This must be enabled in the.." line.long 0x1C "HWLPCTL,Hardware Low Power Control Register" hexmask.long.byte 0x1C 28.--31. 1. "RESERVED,Reserved" newline hexmask.long.word 0x1C 16.--27. 1. "HW_LP_IDLE_X32,Hardware idle period. The cactive_ddrc output is driven low if the DDRC command channel is idle for hw_lp_idle * 32 cycles if not in INIT or DPD/MPSM operating_mode. The DDRC command channel is considered idle when there are no HIF.." newline hexmask.long.word 0x1C 2.--15. 1. "RESERVED,Reserved" newline bitfld.long 0x1C 1. "HW_LP_EXIT_IDLE_EN,When this bit is programmed to 1 the cactive_in_ddrc pin of the DDRC can be used to exit from the automatic clock stop automatic power down or automatic self-refresh modes. Note it does not cause exit of self-refresh that was caused.." "0,1" newline bitfld.long 0x1C 0. "HW_LP_EN,Enable this bit for Hardware Low Power Interface. Programming Mode: Quasi-dynamic Group 2" "0,1" group.long 0x50++0x7 line.long 0x0 "RFSHCTL0,Refresh Control Register 0" hexmask.long.byte 0x0 24.--31. 1. "RESERVED,Reserved" newline hexmask.long.byte 0x0 20.--23. 1. "REFRESH_MARGIN,Threshold value in number of DFI clock cycles before the critical refresh or page timer expires. A critical refresh is to be issued before this threshold is reached. It is recommended that this not be changed from the default value.." newline rbitfld.long 0x0 17.--19. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x0 12.--16. 1. "REFRESH_TO_X1_X32,If the refresh timer (tRFCnom also known as tREFI) has expired at least once then a speculative refresh may be performed. A speculative refresh is a refresh performed at a time when refresh would be useful. When the SDRAM bus is idle.." newline rbitfld.long 0x0 10.--11. "RESERVED,Reserved" "0,1,2,3" newline hexmask.long.byte 0x0 4.--9. 1. "REFRESH_BURST,The programmed value + 1 is the number of refresh timeouts that is allowed to accumulate before traffic is blocked and the refreshes are forced to execute. Closing pages to perform a refresh is a one-time penalty that must be paid for each.." newline rbitfld.long 0x0 3. "RESERVED,Reserved" "0,1" newline bitfld.long 0x0 2. "PER_BANK_REFRESH,- 1 - Per bank refresh - 0 - All bank refresh Per bank refresh allows traffic to flow to other banks. Per bank refresh is not supported by all LPDDR2 devices but must be supported by all LPDDR3/LPDDR4 devices. Present only in designs.." "All bank refresh,Per bank refresh" newline rbitfld.long 0x0 0.--1. "RESERVED,Reserved" "0,1,2,3" line.long 0x4 "RFSHCTL1,Refresh Control Register 1" hexmask.long.byte 0x4 28.--31. 1. "RESERVED,Reserved" newline hexmask.long.word 0x4 16.--27. 1. "REFRESH_TIMER1_START_VALUE_X32,Refresh timer start for rank 1 (only present in multi-rank configurations). This is useful in staggering the refreshes to multiple ranks to help traffic to proceed. This is explained in Refresh Controls section of the.." newline hexmask.long.byte 0x4 12.--15. 1. "RESERVED,Reserved" newline hexmask.long.word 0x4 0.--11. 1. "REFRESH_TIMER0_START_VALUE_X32,Refresh timer start for rank 0 (only present in multi-rank configurations). This is useful in staggering the refreshes to multiple ranks to help traffic to proceed. This is explained in Refresh Controls section of the.." group.long 0x60++0xB line.long 0x0 "RFSHCTL3,Refresh Control Register 3" hexmask.long 0x0 7.--31. 1. "RESERVED,Reserved" newline bitfld.long 0x0 4.--6. "REFRESH_MODE,Indicates fine granularity refresh mode. - 000 - Fixed 1x (Normal mode) - 001 - Fixed 2x - 010 - Fixed 4x - 101 - Enable on the fly 2x (not supported) - 110 - Enable on the fly 4x (not supported) - Everything else - reserved Note: - Only.." "Fixed 1x,The on-the-fly modes are not supported in this..,This register field has effect only if a DDR4..,?,?,?,?,?" newline rbitfld.long 0x0 2.--3. "RESERVED,Reserved" "0,1,2,3" newline bitfld.long 0x0 1. "REFRESH_UPDATE_LEVEL,Toggle this signal (either from 0 to 1 or from 1 to 0) to indicate that the refresh registers have been updated. refresh_update_level must not be toggled when the DDRC is in reset (core_ddrc_rstn = 0). The refresh registers are.." "0,1" newline bitfld.long 0x0 0. "DIS_AUTO_REFRESH,When '1' disable auto-refresh generated by the uMCTL2. When auto-refresh is disabled the SoC must generate refreshes using the registers DBGCMD.rankn_refresh. When dis_auto_refresh transitions from 0 to 1 any pending refreshes are.." "0,1" line.long 0x4 "RFSHTMG,Refresh Timing Register" bitfld.long 0x4 31. "T_RFC_NOM_X1_SEL,Specifies whether the RFSHTMG.t_rfc_nom_x1_x32 and RFSHCTL0.refresh_to_x1_x32 register values are x1 or x32. - 0 - x32 register values are used - 1 - x1 register values are used This applies only when per-bank refresh is enabled.." "x32 register values are used,x1 register values are used" newline rbitfld.long 0x4 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline hexmask.long.word 0x4 16.--27. 1. "T_RFC_NOM_X1_X32,Average time interval between refreshes per rank (Specification: 7.8us for DDR2 DDR3 and DDR4. See JEDEC specification for mDDR LPDDR2 LPDDR3 and LPDDR4). When the controller is operating in 1:1 mode set this register to.." newline bitfld.long 0x4 15. "LPDDR3_TREFBW_EN,Used only when LPDDR3 memory type is connected. Should only be changed when uMCTL2 is in reset. Specifies whether to use the tREFBW parameter (required by some LPDDR3 devices which comply with earlier versions of the LPDDR3 JEDEC.." "tREFBW parameter not used,tREFBW parameter used" newline hexmask.long.byte 0x4 10.--14. 1. "RESERVED,Reserved" newline hexmask.long.word 0x4 0.--9. 1. "T_RFC_MIN,tRFC (min): Minimum time from refresh to refresh or activate. When the controller is operating in 1:1 mode t_rfc_min must be set to RoundUp(tRFCmin/tCK). When the controller is operating in 1:2 mode t_rfc_min must be set to.." line.long 0x8 "RFSHTMG1,Refresh Timing Register1" hexmask.long.byte 0x8 24.--31. 1. "RESERVED,Reserved" newline hexmask.long.byte 0x8 16.--23. 1. "T_PBR2PBR,LPDDR4:tpbR2pbR. Per-bank refresh to Per-bank refresh different bank Time. When the controller is operating in 1:1 frequency ratio mode program this to RoundUp(tpbR2pbR/tCK). When the controller is operating in 1:2 frequency ratio mode.." newline hexmask.long.word 0x8 0.--15. 1. "RESERVED,Reserved" group.long 0x70++0x7 line.long 0x0 "ECCCFG0,ECC Configuration Register 0" bitfld.long 0x0 30.--31. "ECC_REGION_MAP_GRANU,Indicates granularity of selectable protected region. Define one region size for ECCCFG0.ecc_region_map. - 0 - 1/8 of memory spaces - 1 - 1/16 of memory spaces - 2 - 1/32 of memory spaces - 3 - 1/64 of memory spaces Programming Mode:.." "0,1,2,3" newline bitfld.long 0x0 29. "ECC_REGION_MAP_OTHER,When ECCCFG0.ecc_region_map_granu>0 there is a region which is not controlled by ecc_region_map. This register defines the region to be protected or non-protected for Inline ECC. - 0 - Non-Protected - 1 - Protected This register is.." "Non-Protected,Protected" newline rbitfld.long 0x0 27.--28. "RESERVED,Reserved" "0,1,2,3" newline bitfld.long 0x0 24.--26. "ECC_AP_ERR_THRESHOLD,Sets threshold for address parity error. ECCAPSTAT.ecc_ap_err is asserted if number of ECC errors (correctable/uncorrectable) within one burst exceeds this threshold. This register value must be less than 'Total number of ECC checks.." "0,1,2,3,4,5,6,7" newline rbitfld.long 0x0 22.--23. "RESERVED,Reserved" "0,1,2,3" newline hexmask.long.byte 0x0 16.--21. 1. "BLK_CHANNEL_IDLE_TIME_X32,Indicates the number of cycles on HIF interface with no access to protected regions which causes flush of all the block channels. In order to flush block channel uMCTL2 injects write ECC command (when there is no incoming HIF.." newline rbitfld.long 0x0 15. "RESERVED,Reserved" "0,1" newline hexmask.long.byte 0x0 8.--14. 1. "ECC_REGION_MAP,Selectable Protected Region setting. Memory space is divided to 8/16/32/64 regions which is determined by ECCCFG0.ecc_region_map_granu. Note: Highest 1/8 memory space is always ECC region. Lowest 7 regions are Selectable Protected Regions." newline bitfld.long 0x0 7. "ECC_REGION_REMAP_EN,Enables remapping ECC region feature. Only supported when inline ECC is enabled. - 0 - Disable - 1 - Enable Programming Mode: Static" "Disable,Enable" newline bitfld.long 0x0 6. "ECC_AP_EN,Enables address protection feature. Only supported when inline ECC is enabled. - 0 - Disable - 1 - Enable Programming Mode: Static" "Disable,Enable" newline rbitfld.long 0x0 5. "RESERVED,Reserved" "0,1" newline bitfld.long 0x0 4. "DIS_SCRUB,Disables ECC scrubs. Valid only when ECCCFG0.ecc_mode = 3'b100 or 3'b101 and MEMC_USE_RMW is defined. Note: Scrub is not supported in inline ECC mode and the register value is don't care. Programming Mode: Static" "0,1" newline rbitfld.long 0x0 3. "RESERVED,Reserved" "0,1" newline bitfld.long 0x0 0.--2. "ECC_MODE,ECC mode indicator. - 000 - ECC disabled - 100 - ECC enabled - SEC/DED over 1 beat - 101 - ECC enabled - Advanced ECC (Illegal value when MEMC_INLINE_ECC=1) - all other settings are reserved for future use Programming Mode: Static" "ECC disabled,?,?,?,?,?,?,?" line.long 0x4 "ECCCFG1,ECC Configuration Register 1" hexmask.long.tbyte 0x4 12.--31. 1. "RESERVED,Reserved" newline hexmask.long.byte 0x4 8.--11. 1. "ACTIVE_BLK_CHANNEL,Indicated the number of active block channels. Total number of ECC block channels are defined by MEMC_NO_OF_BLK_CHANNEL hardware parameter. This register can limit the number of available channels. For example if set to 0 only one.." newline bitfld.long 0x4 7. "BLK_CHANNEL_ACTIVE_TERM,If enabled block channel is terminated when full block write or full block read is performed (all address within block are written or read). - 0 - Disable (only for debug purpose) - 1 - Enable (default) This is debug register.." "Disable,Enable" newline rbitfld.long 0x4 6. "RESERVED,Reserved" "0,1" newline bitfld.long 0x4 5. "ECC_REGION_WASTE_LOCK,Locks the remaining waste parts of the ECC region (hole) that are not locked by ecc_region_parity_lock. - 1 - Locked; if this region is accessed error response is generated - 0 - Unlocked; this region can be accessed normally.." "Unlocked; this region can be accessed normally,Locked; if this region is accessed" newline bitfld.long 0x4 4. "ECC_REGION_PARITY_LOCK,Locks the parity section of the ECC region (hole) which is the highest system address part of the memory that stores ECC parity for protected region. - 1 - Locked; if this region is accessed error response is generated - 0 -.." "Unlocked; this region can be accessed normally,Locked; if this region is accessed" newline rbitfld.long 0x4 2.--3. "RESERVED,Reserved" "0,1,2,3" newline bitfld.long 0x4 1. "DATA_POISON_BIT,Selects whether to poison 1 or 2 bits. - if 0 -> 2-bit (uncorrectable) data poisoning - if 1 -> 1-bit (correctable) data poisoning if ECCCFG1.data_poison_en=1 Valid only when MEMC_ECC_SUPPORT==1 (SECDED ECC mode) Programming Mode:.." "?,bit" newline bitfld.long 0x4 0. "DATA_POISON_EN,Enables ECC data poisoning - introduces ECC errors on writes to address specified by the ECCPOISONADDR0/1 registers. This field must be set to 0 if ECC is disabled (ECCCFG0.ecc_mode = 0). Programming Mode: Quasi-dynamic Group 3" "0,1" rgroup.long 0x78++0x3 line.long 0x0 "ECCSTAT,SECDED ECC Status Register (Valid only in MEMC_ECC_SUPPORT==1 (SECDED ECC mode))" hexmask.long.word 0x0 17.--31. 1. "RESERVED,Reserved" newline bitfld.long 0x0 16. "ECC_UNCORRECTED_ERR,Double-bit error indicator. In sideband ECC mode 1 bit per ECC lane. When the controller is operating in 1:1 frequency ratio mode there are only two lanes so only the lower two bits are used. In inline ECC mode the register is.." "0,1" newline hexmask.long.byte 0x0 9.--15. 1. "RESERVED,Reserved" newline bitfld.long 0x0 8. "ECC_CORRECTED_ERR,Single-bit error indicator. In sideband ECC mode 1 bit per ECC lane. When the controller is operating in 1:1 frequency ratio mode there are only two lanes so only the lower two bits are used. In inline ECC mode the register is.." "0,1" newline bitfld.long 0x0 7. "RESERVED,Reserved" "0,1" newline hexmask.long.byte 0x0 0.--6. 1. "ECC_CORRECTED_BIT_NUM,Indicates the bit number corrected by single-bit ECC error. For encoding of this field see ECC section in the Architecture chapter. If more than one data lane has an error the lower data lane is selected. This register is 7 bits.." group.long 0x7C++0x3 line.long 0x0 "ECCCTL,ECC Clear Register" hexmask.long.word 0x0 19.--31. 1. "RESERVED,Reserved" newline bitfld.long 0x0 18. "ECC_AP_ERR_INTR_FORCE,Interrupt force bit for ecc_ap_err_intr. Setting this register causes the output interrupt to be asserted. The uMCTL2 automatically clears this bit. There is no interaction between functionally triggering an interrupt and forcing an.." "0,1" newline bitfld.long 0x0 17. "ECC_UNCORRECTED_ERR_INTR_FORCE,Interrupt force bit for ecc_uncorrected_err_intr. Setting this register causes the output interrupt to be asserted. The uMCTL2 automatically clears this bit. There is no interaction between functionally triggering an.." "0,1" newline bitfld.long 0x0 16. "ECC_CORRECTED_ERR_INTR_FORCE,Interrupt force bit for ecc_corrected_err_intr. Setting this register causes the output interrupt to be asserted. The uMCTL2 automatically clears this bit. There is no interaction between functionally triggering an interrupt.." "0,1" newline hexmask.long.byte 0x0 11.--15. 1. "RESERVED,Reserved" newline bitfld.long 0x0 10. "ECC_AP_ERR_INTR_EN,Interrupt enable bit for ecc_ap_err_intr. - 1 - Enabled - 0 - Disabled Programming Mode: Dynamic" "Disabled,Enabled" newline bitfld.long 0x0 9. "ECC_UNCORRECTED_ERR_INTR_EN,Interrupt enable bit for ecc_uncorrected_err_intr. - 1 - Enabled - 0 - Disabled Programming Mode: Dynamic" "Disabled,Enabled" newline bitfld.long 0x0 8. "ECC_CORRECTED_ERR_INTR_EN,Interrupt enable bit for ecc_corrected_err_intr. - 1 - Enabled - 0 - Disabled Programming Mode: Dynamic" "Disabled,Enabled" newline rbitfld.long 0x0 5.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 4. "ECC_AP_ERR_INTR_CLR,Interrupt clear bit for ecc_ap_err. If this bit is set the ECCAPSTAT.ecc_ap_err/ecc_ap_err_intr is cleared. The uMCTL2 automatically clears this bit. Programming Mode: Dynamic" "0,1" newline bitfld.long 0x0 3. "ECC_UNCORR_ERR_CNT_CLR,Setting this register bit to 1 clears the currently stored uncorrected ECC error count. The ECCERRCNT.ecc_uncorr_err_cnt register is cleared by this operation. The uMCTL2 automatically clears this bit. Programming Mode: Dynamic" "0,1" newline bitfld.long 0x0 2. "ECC_CORR_ERR_CNT_CLR,Setting this register bit to 1 clears the currently stored corrected ECC error count. The ECCERRCNT.ecc_corr_err_cnt register is cleared by this operation. The uMCTL2 automatically clears this bit. Programming Mode: Dynamic" "0,1" newline bitfld.long 0x0 1. "ECC_UNCORRECTED_ERR_CLR,Setting this register bit to 1 clears the currently stored uncorrected ECC error. The following registers are cleared: - ECCSTAT.ecc_uncorrected_err - ADVECCSTAT.advecc_uncorrected_err - ECCUSYN0 - ECCUSYN1 - ECCUSYN2 uMCTL2.." "ECCUSYN1,?" newline bitfld.long 0x0 0. "ECC_CORRECTED_ERR_CLR,Setting this register bit to 1 clears the currently stored corrected ECC error. The following registers are cleared: - ECCSTAT.ecc_corrected_err - ADVECCSTAT.advecc_corrected_err - ADVECCSTAT.advecc_num_err_symbol -.." "ECCCSYN1,ECCBITMASK2" rgroup.long 0x80++0xB line.long 0x0 "ECCERRCNT,ECC Error Counter Register" hexmask.long.word 0x0 16.--31. 1. "ECC_UNCORR_ERR_CNT,Indicates the number of uncorrectable ECC errors detected. Note that the saturation behavior of this register is different depending on the type of ECC. For advanced ECC or Inline ECC it saturates at 0xFFFF while for Side-band ECC.." newline hexmask.long.word 0x0 0.--15. 1. "ECC_CORR_ERR_CNT,Indicates the number of correctable ECC errors detected. Note that the saturation behavior of this register is different depending on the type of ECC. For advanced ECC or Inline ECC it saturates at 0xFFFF while for Side-band ECC with.." line.long 0x4 "ECCCADDR0,ECC Corrected Error Address Register 0" hexmask.long.byte 0x4 25.--31. 1. "RESERVED,Reserved" newline bitfld.long 0x4 24. "ECC_CORR_RANK,Indicates the rank number of a read resulting in a corrected ECC error. Programming Mode: Dynamic" "0,1" newline hexmask.long.byte 0x4 18.--23. 1. "RESERVED,Reserved" newline hexmask.long.tbyte 0x4 0.--17. 1. "ECC_CORR_ROW,Indicates the page/row number of a read resulting in a corrected ECC error. This is 18-bits wide in configurations with DDR4 support and 16-bits in all other configurations. Programming Mode: Dynamic" line.long 0x8 "ECCCADDR1,ECC Corrected Error Address Register 1" hexmask.long.byte 0x8 26.--31. 1. "RESERVED,Reserved" newline bitfld.long 0x8 24.--25. "ECC_CORR_BG,Indicates the bank group number of a read resulting in a corrected ECC error. Programming Mode: Dynamic" "0,1,2,3" newline hexmask.long.byte 0x8 19.--23. 1. "RESERVED,Reserved" newline bitfld.long 0x8 16.--18. "ECC_CORR_BANK,Indicates the bank number of a read resulting in a corrected ECC error. Programming Mode: Dynamic" "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x8 12.--15. 1. "RESERVED,Reserved" newline hexmask.long.word 0x8 0.--11. 1. "ECC_CORR_COL,Indicates the block number of a read resulting in a corrected ECC error (lowest bit not assigned here). Programming Mode: Dynamic" repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) rgroup.long ($2+0x8C)++0x3 line.long 0x0 "ECCCSYN$1,ECC Corrected Syndrome Register 0" hexmask.long 0x0 0.--31. 1. "ECC_CORR_SYNDROMES_31_0,Indicates the data pattern that resulted in a corrected error. For 16-bit ECC only bits [15:0] are used. Programming Mode: Dynamic" repeat.end rgroup.long 0x94++0x3 line.long 0x0 "ECCCSYN2,ECC Corrected Syndrome Register 2" hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED,Reserved" newline hexmask.long.byte 0x0 0.--7. 1. "ECC_CORR_SYNDROMES_71_64,Indicates the data pattern that resulted in a corrected error one for each ECC lane all concatenated together. This register refers to the ECC byte which is bits [71:64] for 64-bit ECC [39:32] for 32-bit ECC or [23:16] for.." repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) rgroup.long ($2+0x98)++0x3 line.long 0x0 "ECCBITMASK$1,ECC Corrected Data Bit Mask Register 0" hexmask.long 0x0 0.--31. 1. "ECC_CORR_BIT_MASK_31_0,Indicates the mask for the corrected data portion. - 1 on any bit indicates that the bit has been corrected by the ECC logic - 0 on any bit indicates that the bit has not been corrected by the ECC logic This register accumulates.." repeat.end rgroup.long 0xA0++0xB line.long 0x0 "ECCBITMASK2,ECC Corrected Data Bit Mask Register 2" hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED,Reserved" newline hexmask.long.byte 0x0 0.--7. 1. "ECC_CORR_BIT_MASK_71_64,Indicates the mask for the corrected data portion. - 1 on any bit indicates that the bit has been corrected by the ECC logic - 0 on any bit indicates that the bit has not been corrected by the ECC logic This register accumulates.." line.long 0x4 "ECCUADDR0,ECC Uncorrected Error Address Register 0" hexmask.long.byte 0x4 25.--31. 1. "RESERVED,Reserved" newline bitfld.long 0x4 24. "ECC_UNCORR_RANK,Indicates the rank number of a read resulting in an uncorrected ECC error. Programming Mode: Dynamic" "0,1" newline hexmask.long.byte 0x4 18.--23. 1. "RESERVED,Reserved" newline hexmask.long.tbyte 0x4 0.--17. 1. "ECC_UNCORR_ROW,Indicates the page/row number of a read resulting in an uncorrected ECC error. This is 18-bits wide in configurations with DDR4 support and 16-bits in all other configurations. Programming Mode: Dynamic" line.long 0x8 "ECCUADDR1,ECC Uncorrected Error Address Register 1" hexmask.long.byte 0x8 26.--31. 1. "RESERVED,Reserved" newline bitfld.long 0x8 24.--25. "ECC_UNCORR_BG,Indicates the bank group number of a read resulting in an uncorrected ECC error. Programming Mode: Dynamic" "0,1,2,3" newline hexmask.long.byte 0x8 19.--23. 1. "RESERVED,Reserved" newline bitfld.long 0x8 16.--18. "ECC_UNCORR_BANK,Indicates the bank number of a read resulting in an uncorrected ECC error. Programming Mode: Dynamic" "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x8 12.--15. 1. "RESERVED,Reserved" newline hexmask.long.word 0x8 0.--11. 1. "ECC_UNCORR_COL,Indicates the block number of a read resulting in an uncorrected ECC error (lowest bit not assigned here). Programming Mode: Dynamic" repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) rgroup.long ($2+0xAC)++0x3 line.long 0x0 "ECCUSYN$1,ECC Uncorrected Syndrome Register 0" hexmask.long 0x0 0.--31. 1. "ECC_UNCORR_SYNDROMES_31_0,Indicates the data pattern that resulted in an uncorrected error one for each ECC lane all concatenated together. For 16-bit ECC only bits [15:0] are used. Programming Mode: Dynamic" repeat.end rgroup.long 0xB4++0x3 line.long 0x0 "ECCUSYN2,ECC Uncorrected Syndrome Register 2" hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED,Reserved" newline hexmask.long.byte 0x0 0.--7. 1. "ECC_UNCORR_SYNDROMES_71_64,Indicates the data pattern that resulted in an uncorrected error one for each ECC lane all concatenated together. This register refers to the ECC byte which is bits [71:64] for 64-bit ECC [39:32] for 32-bit ECC or [23:16].." group.long 0xB8++0xF line.long 0x0 "ECCPOISONADDR0,ECC Data Poisoning Address Register 0. If a HIF write data beat matches the address specified in this register. an ECC error is introduced on that transaction (write/RMW). if ECCCFG1.data_poison_en=1." hexmask.long.byte 0x0 25.--31. 1. "RESERVED,Reserved" newline bitfld.long 0x0 24. "ECC_POISON_RANK,Indicates the rank address for ECC poisoning. Programming Mode: Static" "0,1" newline hexmask.long.word 0x0 12.--23. 1. "RESERVED,Reserved" newline hexmask.long.word 0x0 0.--11. 1. "ECC_POISON_COL,Indicates the column address for ECC poisoning. Note that this column address must be burst aligned: - In full bus width mode ecc_poison_col[2:0] must be set to 0 - In half bus width mode ecc_poison_col[3:0] must be set to 0 - In quarter.." line.long 0x4 "ECCPOISONADDR1,ECC Data Poisoning Address Register 1. If a HIF write data beat matches the address specified in this register. an ECC error is introduced on that transaction (write/RMW). if ECCCFG1.data_poison_en=1." rbitfld.long 0x4 30.--31. "RESERVED,Reserved" "0,1,2,3" newline bitfld.long 0x4 28.--29. "ECC_POISON_BG,Bank Group address for ECC poisoning. Programming Mode: Static" "0,1,2,3" newline rbitfld.long 0x4 27. "RESERVED,Reserved" "0,1" newline bitfld.long 0x4 24.--26. "ECC_POISON_BANK,Bank address for ECC poisoning. Programming Mode: Static" "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x4 18.--23. 1. "RESERVED,Reserved" newline hexmask.long.tbyte 0x4 0.--17. 1. "ECC_POISON_ROW,Row address for ECC poisoning. This is 18-bits wide in configurations with DDR4 support and 16-bits in all other configurations. Programming Mode: Static" line.long 0x8 "CRCPARCTL0,CRC Parity Control Register0. Note: Do not perform any APB access to CRCPARCTL0 within 32 pclk cycles of previous access to CRCPARCTL0. as this might lead to data loss." hexmask.long 0x8 3.--31. 1. "RESERVED,Reserved" newline bitfld.long 0x8 2. "DFI_ALERT_ERR_CNT_CLR,Indicates the clear bit for DFI alert error counter. Asserting this bit clears the DFI alert error counter CRCPARSTAT.dfi_alert_err_cnt. uMCTL2 automatically clears this bit. Programming Mode: Dynamic" "0,1" newline bitfld.long 0x8 1. "DFI_ALERT_ERR_INT_CLR,Interrupt clear bit for DFI alert error. If this bit is set the alert error interrupt on CRCPARSTAT.dfi_alert_err_int is cleared. uMCTL2 automatically clears this bit. Programming Mode: Dynamic" "0,1" newline bitfld.long 0x8 0. "DFI_ALERT_ERR_INT_EN,Interrupt enable bit for DFI alert error. If this bit is set any parity/CRC error detected on the dfi_alert_n input results in an interrupt being set on CRCPARSTAT.dfi_alert_err_int. Programming Mode: Dynamic" "0,1" line.long 0xC "CRCPARCTL1,CRC Parity Control Register1" hexmask.long.tbyte 0xC 13.--31. 1. "RESERVED,Reserved" newline bitfld.long 0xC 12. "CAPARITY_DISABLE_BEFORE_SR,If DDR4-SDRAM's CA parity is enabled by INIT6.mr5[2:0]!=0 and this register is set to 1 CA parity is automatically disabled before self-refresh entry and enabled after self-refresh exit by issuing MR5. - 1 - CA parity is.." "CA parity is not disabled before self-refresh..,CA parity is disabled before self-refresh entry" newline hexmask.long.byte 0xC 8.--11. 1. "RESERVED,Reserved" newline bitfld.long 0xC 7. "CRC_INC_DM,CRC calculation setting register. - 1 - CRC includes DM signal - 0 - CRC not includes DM signal Present only in designs configured to support DDR4. Programming Mode: Static" "CRC not includes DM signal,CRC includes DM signal" newline rbitfld.long 0xC 5.--6. "RESERVED,Reserved" "0,1,2,3" newline bitfld.long 0xC 4. "CRC_ENABLE,CRC enable Register. - 1 - Enable generation of CRC - 0 - Disable generation of CRC The setting of this register should match the CRC mode register setting in the DRAM. Programming Mode: Quasi-dynamic Group 2" "Disable generation of CRC,Enable generation of CRC" newline rbitfld.long 0xC 1.--3. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline bitfld.long 0xC 0. "PARITY_ENABLE,C/A Parity enable register. - 1 - Enable generation of C/A parity and detection of C/A parity error - 0 - Disable generation of C/A parity and disable detection of C/A parity error If RCD's parity error detection or SDRAM's parity detection.." "Disable generation of C/A parity and disable..,Enable generation of C/A parity and detection of.." rgroup.long 0xCC++0x3 line.long 0x0 "CRCPARSTAT,CRC Parity Status Register" hexmask.long.word 0x0 17.--31. 1. "RESERVED,Reserved" newline bitfld.long 0x0 16. "DFI_ALERT_ERR_INT,DFI alert error interrupt. If a parity/CRC error is detected on dfi_alert_n and the interrupt is enabled by CRCPARCTL0.dfi_alert_err_int_en this interrupt bit is set. It remains set until cleared by CRCPARCTL0.dfi_alert_err_int_clr." "0,1" newline hexmask.long.word 0x0 0.--15. 1. "DFI_ALERT_ERR_CNT,DFI alert error count. If a parity/CRC error is detected on dfi_alert_n this counter be incremented. This is independent of the setting of CRCPARCTL0.dfi_alert_err_int_en. It saturates at 0xFFFF and can be cleared by asserting.." group.long 0xD0++0xB line.long 0x0 "INIT0,SDRAM Initialization Register 0" bitfld.long 0x0 30.--31. "SKIP_DRAM_INIT,If lower bit is enabled the SDRAM initialization routine is skipped. The upper bit decides what state the controller starts up in when reset is removed. - 00 - SDRAM Initialization routine is run after power-up - 01 - SDRAM Initialization.." "SDRAM Initialization routine is run after power-up,SDRAM Initialization routine is skipped after..,?,?" newline hexmask.long.byte 0x0 26.--29. 1. "RESERVED,Reserved" newline hexmask.long.word 0x0 16.--25. 1. "POST_CKE_X1024,Indicates the number of cycles to wait after driving CKE high to start the SDRAM initialization sequence. DDR2 typically requires a 400 ns delay requiring this value to be programmed to 2 at all clock speeds. LPDDR2/LPDDR3 typically.." newline hexmask.long.byte 0x0 12.--15. 1. "RESERVED,Reserved" newline hexmask.long.word 0x0 0.--11. 1. "PRE_CKE_X1024,Indicates the number of cycles to wait after reset before driving CKE high to start the SDRAM initialization sequence. DDR2 specifications typically require this to be programmed for a delay of >= 200 us. LPDDR2/LPDDR3: tINIT1 of 100 ns.." line.long 0x4 "INIT1,SDRAM Initialization Register 1" hexmask.long.byte 0x4 25.--31. 1. "RESERVED,Reserved" newline hexmask.long.word 0x4 16.--24. 1. "DRAM_RSTN_X1024,Indicates the number of cycles to assert SDRAM reset signal during init sequence. This is only present for designs supporting DDR3 DDR4 or LPDDR4 devices. For use with a Synopsys DDR PHY this must be set to a minimum of 1. When the.." newline hexmask.long.word 0x4 4.--15. 1. "RESERVED,Reserved" newline hexmask.long.byte 0x4 0.--3. 1. "PRE_OCD_X32,Indicates the wait period before driving the OCD complete command to SDRAM. There is no known specific requirement for this; it may be set to zero. Unit: Multiples of 32 DFI clock cycles. For more information on how to program this register.." line.long 0x8 "INIT2,SDRAM Initialization Register 2" hexmask.long.word 0x8 16.--31. 1. "RESERVED,Reserved" newline hexmask.long.byte 0x8 8.--15. 1. "IDLE_AFTER_RESET_X32,Indicates the idle time after the reset command tINIT4. Present only in designs configured to support LPDDR2. When the controller is operating in 1:2 frequency ratio mode program this to JEDEC spec value divided by 2 and round it.." newline hexmask.long.byte 0x8 4.--7. 1. "RESERVED,Reserved" newline hexmask.long.byte 0x8 0.--3. 1. "MIN_STABLE_CLOCK_X1,Indicates the time to wait after the first CKE high tINIT2. Present only in designs configured to support LPDDR2/LPDDR3. LPDDR2/LPDDR3 typically requires 5 x tCK delay. When the controller is operating in 1:2 frequency ratio mode.." repeat 4. (list 0x3 0x4 0x6 0x7 )(list 0x0 0x4 0xC 0x10 ) group.long ($2+0xDC)++0x3 line.long 0x0 "INIT$1,SDRAM Initialization Register 3" hexmask.long.word 0x0 16.--31. 1. "MR,DDR2:Indicates the value to write to MR register. Bit 8 is for DLL and the setting here is ignored. The uMCTL2 sets this bit appropriately. DDR3/DDR4: Value loaded into MR0 register. mDDR: Value to write to MR register. LPDDR2/LPDDR3/LPDDR4 - Value to.." newline hexmask.long.word 0x0 0.--15. 1. "EMR,DDR2: Indicates the value to write to EMR register. Bits 9:7 are for OCD and the setting in this register is ignored. The uMCTL2 sets those bits appropriately. DDR3/DDR4: Value to write to MR1 register Set bit 7 to 0. mDDR: Value to write to EMR.." repeat.end group.long 0xE4++0x3 line.long 0x0 "INIT5,SDRAM Initialization Register 5" hexmask.long.byte 0x0 24.--31. 1. "RESERVED,Reserved" newline hexmask.long.byte 0x0 16.--23. 1. "DEV_ZQINIT_X32,ZQ initial calibration tZQINIT. Present only in designs configured to support DDR3 or DDR4 or LPDDR2/LPDDR3. DDR3 typically requires 512 SDRAM clock cycles. DDR4 requires 1024 SDRAM clock cycles. LPDDR2/LPDDR3 requires 1 us. When the.." newline hexmask.long.byte 0x0 10.--15. 1. "RESERVED,Reserved" newline hexmask.long.word 0x0 0.--9. 1. "MAX_AUTO_INIT_X1024,Indicates the maximum duration of the auto initialization tINIT5. Present only in designs configured to support LPDDR2/LPDDR3. LPDDR2/LPDDR3 typically requires 10 us. Unit: Multiples of 1024 DFI clock cycles. For more information on.." group.long 0xF0++0x7 line.long 0x0 "DIMMCTL,DIMM Control Register" hexmask.long.tbyte 0x0 15.--31. 1. "RESERVED,Reserved" newline bitfld.long 0x0 14. "RCD_B_OUTPUT_DISABLED,Disables RCD outputs to B-side DRAMs. This field is used only when the uMCTL2 disables CAL mode. This value is written to F0RC0 DA[3] before and after disabling CAL mode. It is recommended to set it to ~DIMMCTL.dimm_output_inv_en.." "Enable B outputs,Disable B outputs" newline bitfld.long 0x0 13. "RCD_A_OUTPUT_DISABLED,Disables RCD outputs to A-side DRAMs. This field is used only when the uMCTL2 disables CAL mode. This value is written to F0RC0 DA[2] before and after disabling CAL mode. It is recommended to set it to 0 except for debug. - 1 -.." "Enable A outputs,Disable A outputs" newline bitfld.long 0x0 12. "RCD_WEAK_DRIVE,Indicates the weak drive mode to be set to the RCD. This field is used only when the uMCTL2 disables CAL mode. When weak drive mode in the RCD is enabled during initialization this field must be set to 1. When RCD is not used this field.." "Disable Weak Drive mode,Enable Weak Drive mode" newline hexmask.long.byte 0x0 7.--11. 1. "RESERVED,Reserved" newline bitfld.long 0x0 6. "LRDIMM_BCOM_CMD_PROT,Protects the timing restrictions (tBCW/tMRC) between consecutive BCOM commands defined in the Data Buffer specification. When using DDR4 LRDIMM this bit must be set to 1. Otherwise this bit must be set to 0. Programming Mode: Static" "0,1" newline bitfld.long 0x0 5. "DIMM_DIS_BG_MIRRORING,Disables address mirroring for BG bits. When this is set to 1 BG0 and BG1 are NOT swapped even if Address Mirroring is enabled. This is required for DDR4 DIMMs with x16 devices. - 1 - BG0 and BG1 are NOT swapped - 0 - BG0 and BG1.." "BG0 and BG1 are swapped if address mirroring is..,BG0 and BG1 are NOT swapped" newline bitfld.long 0x0 4. "MRS_BG1_EN,Enable this field for BG1 bit of MRS command. BG1 bit of the mode register address is specified as RFU (Reserved for Future Use) and must be programmed to 0 during MRS. In case where DRAMs that do not have BG1 are attached and both the CA.." "Disabled,Enabled" newline bitfld.long 0x0 3. "MRS_A17_EN,Enable this field for A17 bit of MRS command. A17 bit of the mode register address is specified as RFU (Reserved for Future Use) and must be programmed to 0 during MRS. In case where DRAMs that do not have A17 are attached as DDR4 RDIMM/LRDIMM.." "Disabled,Enabled" newline bitfld.long 0x0 2. "DIMM_OUTPUT_INV_EN,Enables output inversion (for DDR4 RDIMM/LRDIMM implementations only). DDR4 RDIMM/LRDIMM implements the Output Inversion feature by default which means that the following address bank address and bank group bits of B-side DRAMs are.." "Do not implement output inversion for B-side DRAMs,Implement output inversion for B-side DRAMs" newline bitfld.long 0x0 1. "DIMM_ADDR_MIRR_EN,Enables address mirroring (for multi-rank UDIMM implementations and multi-rank DDR4 RDIMM/LRDIMM implementations). Some UDIMMs and DDR4 RDIMMs/LRDIMMs implement address mirroring for odd ranks which means that the following address.." "Do not implement address mirroring,For odd ranks" newline bitfld.long 0x0 0. "DIMM_STAGGER_CS_EN,Staggering enable for multi-rank accesses (for multi-rank UDIMM RDIMM and LRDIMM implementations only). This is not supported for mDDR LPDDR2 LPDDR3 or LPDDR4 SDRAMs. Note: Even if this bit is set it does not take care of software.." "Do not stagger accesses,?" line.long 0x4 "RANKCTL,Rank Control Register" hexmask.long.byte 0x4 27.--31. 1. "RESERVED,Reserved" newline bitfld.long 0x4 26. "DIFF_RANK_WR_GAP_MSB,Only present for multi-rank configurations. 1-bit extension to be used when RANKCTL.diff_rank_wr_gap field needs to be set to a value greater than 0xF. Programming Mode: Quasi-dynamic Group 2" "?,bit extension to be used when RANKCTL" newline rbitfld.long 0x4 25. "RESERVED,Reserved" "0,1" newline bitfld.long 0x4 24. "DIFF_RANK_RD_GAP_MSB,Only present for multi-rank configurations. 1-bit extension to be used when RANKCTL.diff_rank_rd_gap field needs to be set to a value greater than 0xF. Programming Mode: Quasi-dynamic Group 2" "?,bit extension to be used when RANKCTL" newline hexmask.long.byte 0x4 16.--23. 1. "RESERVED,Reserved" newline hexmask.long.byte 0x4 12.--15. 1. "MAX_RANK_WR,Only present for multi-rank configurations. Background: Writes to the same rank can be performed back-to-back. Writes to different ranks require additional gap dictated by the register RANKCTL.diff_rank_wr_gap. This is to avoid possible data.." newline hexmask.long.byte 0x4 8.--11. 1. "DIFF_RANK_WR_GAP,Only present for multi-rank configurations. Indicates the number of clocks of gap in data responses when performing consecutive writes to different ranks. This is used to switch the delays in the PHY to match the rank requirements. This.." newline hexmask.long.byte 0x4 4.--7. 1. "DIFF_RANK_RD_GAP,Only present for multi-rank configurations. Indicates the number of clocks of gap in data responses when performing consecutive reads to different ranks. This is used to switch the delays in the PHY to match the rank requirements. This.." newline hexmask.long.byte 0x4 0.--3. 1. "MAX_RANK_RD,Only present for multi-rank configurations. Background: Reads to the same rank can be performed back-to-back. Reads to different ranks require additional gap dictated by the register RANKCTL.diff_rank_rd_gap. This is to avoid possible data.." group.long 0x100++0x3F line.long 0x0 "DRAMTMG0,SDRAM Timing Register 0" rbitfld.long 0x0 31. "RESERVED,Reserved" "0,1" newline hexmask.long.byte 0x0 24.--30. 1. "WR2PRE,Specifies the minimum time between write and precharge to same bank. Specifications: WL + BL/2 + tWR = approximately 8 cycles + 15 ns = 14 clocks @400MHz and less for lower frequencies. where: - WL - Write latency - BL - Burst length. This must.." newline rbitfld.long 0x0 22.--23. "RESERVED,Reserved" "0,1,2,3" newline hexmask.long.byte 0x0 16.--21. 1. "T_FAW,tFAW - valid only when 8 or more banks(or banks x bank groups) are present. In 8-bank design at most 4 banks must be activated in a rolling window of tFAW cycles. When the controller is operating in 1:2 frequency ratio mode program this to.." newline rbitfld.long 0x0 15. "RESERVED,Reserved" "0,1" newline hexmask.long.byte 0x0 8.--14. 1. "T_RAS_MAX,tRAS(max) - Specifies the maximum time between activate and precharge to same bank. This is the maximum time that a page can be kept open Minimum value of this register is 1. Zero is invalid. When the controller is operating in 1:1 frequency.." newline rbitfld.long 0x0 6.--7. "RESERVED,Reserved" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "T_RAS_MIN,tRAS(min) - Specifies the minimum time between activate and precharge to the same bank. When the controller is operating in 1:2 frequency mode 1T mode program this to tRAS(min)/2. No rounding up. When the controller is operating in 1:2.." line.long 0x4 "DRAMTMG1,SDRAM Timing Register 1" hexmask.long.word 0x4 21.--31. 1. "RESERVED,Reserved" newline hexmask.long.byte 0x4 16.--20. 1. "T_XP,tXP - Specifies the minimum time after power-down exit to any operation. For DDR3 this must be programmed to tXPDLL if slow powerdown exit is selected in MR0[12]. If C/A parity for DDR4 is used set to (tXP+PL) instead. If LPDDR4 is selected and.." newline rbitfld.long 0x4 14.--15. "RESERVED,Reserved" "0,1,2,3" newline hexmask.long.byte 0x4 8.--13. 1. "RD2PRE,tRTP - Specifies the minimum time from read to precharge of same bank. - DDR2 - tAL + BL/2 + max(tRTP 2) - 2 - DDR3 - tAL + max (tRTP 4) - DDR4 - Max of following two equations: tAL + max (tRTP 4) or RL + BL/2 - tRP (*). - mDDR - BL/2 - LPDDR2.." newline rbitfld.long 0x4 7. "RESERVED,Reserved" "0,1" newline hexmask.long.byte 0x4 0.--6. 1. "T_RC,tRC - Specifies the minimum time between activates to same bank. When the controller is operating in 1:2 frequency ratio mode program this to (tRC/2) and round up to next integer value. Unit: DFI clock cycles. Programming Mode: Quasi-dynamic Group.." line.long 0x8 "DRAMTMG2,SDRAM Timing Register 2" rbitfld.long 0x8 30.--31. "RESERVED,Reserved" "0,1,2,3" newline hexmask.long.byte 0x8 24.--29. 1. "WRITE_LATENCY,Set this field to WL. Indicates the Time from write command to write data on SDRAM interface. This must be set to WL. For mDDR it must be set to 1. Note that depending on the PHY if using RDIMM/LRDIMM it might be necessary to adjust the.." newline rbitfld.long 0x8 22.--23. "RESERVED,Reserved" "0,1,2,3" newline hexmask.long.byte 0x8 16.--21. 1. "READ_LATENCY,Set this field to RL. Indicates the time from read command to read data on SDRAM interface. This must be set to RL. Note that depending on the PHY if using RDIMM/LRDIMM it might be necessary to adjust the value of RL to compensate for the.." newline rbitfld.long 0x8 14.--15. "RESERVED,Reserved" "0,1,2,3" newline hexmask.long.byte 0x8 8.--13. 1. "RD2WR,DDR2/3/mDDR: RL + BL/2 + 2 - WL DDR4: RL + BL/2 + 1 + WR_PREAMBLE - WL LPDDR2/LPDDR3: RL + BL/2 + RU(tDQSCKmax/tCK) + 1 - WL LPDDR4(DQ ODT is Disabled): RL + BL/2 + RU(tDQSCKmax/tCK) + WR_PREAMBLE + RD_POSTAMBLE - WL LPDDR4(DQ ODT is Enabled): RL +.." newline rbitfld.long 0x8 6.--7. "RESERVED,Reserved" "0,1,2,3" newline hexmask.long.byte 0x8 0.--5. 1. "WR2RD,DDR4: CWL + PL + BL/2 + tWTR_L LPDDR2/3/4: WL + BL/2 + tWTR + 1 Others: CWL + BL/2 + tWTR In DDR4 minimum time from write command to read command for same bank group. In others minimum time from write command to read command. Includes time for.." line.long 0xC "DRAMTMG3,SDRAM Timing Register 3" rbitfld.long 0xC 30.--31. "RESERVED,Reserved" "0,1,2,3" newline hexmask.long.word 0xC 20.--29. 1. "T_MRW,Indicates the time to wait after a mode register write or read (MRW or MRR). Present only in designs configured to support LPDDR2 LPDDR3 or LPDDR4. LPDDR2 typically requires value of 5. LPDDR3 typically requires value of 10. LPDDR4: Set this to.." newline rbitfld.long 0xC 18.--19. "RESERVED,Reserved" "0,1,2,3" newline hexmask.long.byte 0xC 12.--17. 1. "T_MRD,tMRD- Indicates the number of cycles to wait after a mode register write or read. Depending on the connected SDRAM tMRD represents: - DDR2/mDDR: Time from MRS to any command - DDR3/4: Time from MRS to MRS command - LPDDR2: not used - LPDDR3/4:.." newline rbitfld.long 0xC 10.--11. "RESERVED,Reserved" "0,1,2,3" newline hexmask.long.word 0xC 0.--9. 1. "T_MOD,tMOD - Parameter used only in DDR3 and DDR4. Indicates the number of cycles between load mode command and following non-load mode command. If C/A parity for DDR4 is used set to tMOD_PAR(tMOD+PL) instead. If CAL mode is enabled.." line.long 0x10 "DRAMTMG4,SDRAM Timing Register 4" rbitfld.long 0x10 29.--31. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x10 24.--28. 1. "T_RCD,tRCD - tAL: Indicates the minimum time from activate to read or write command to same bank. When the controller is operating in 1:2 frequency ratio mode program this to ((tRCD - tAL)/2) and round it up to the next integer value. Minimum value.." newline hexmask.long.byte 0x10 20.--23. 1. "RESERVED,Reserved" newline hexmask.long.byte 0x10 16.--19. 1. "T_CCD,DDR4: tCCD_L: This is the minimum time between two reads or two writes for same bank group. Others: tCCD: This is the minimum time between two reads or two writes. When the controller is operating in 1:2 frequency ratio mode program this to.." newline hexmask.long.byte 0x10 12.--15. 1. "RESERVED,Reserved" newline hexmask.long.byte 0x10 8.--11. 1. "T_RRD,DDR4: tRRD_L: This is the minimum time between activates from bank 'a' to bank 'b' for same bank group. Others: tRRD: Minimum time between activates from bank 'a' to bank 'b' When the controller is operating in 1:2 frequency ratio mode program.." newline rbitfld.long 0x10 5.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x10 0.--4. 1. "T_RP,tRP: Indicates the minimum time from single-bank precharge to activate of same bank. When the controller is operating in 1:1 frequency ratio mode t_rp must be set to RoundUp(tRP/tCK). When the controller is operating in 1:2 frequency ratio mode.." line.long 0x14 "DRAMTMG5,SDRAM Timing Register 5" hexmask.long.byte 0x14 28.--31. 1. "RESERVED,Reserved" newline hexmask.long.byte 0x14 24.--27. 1. "T_CKSRX,This is the time before self-refresh Exit that CK is maintained as a valid clock before issuing SRX. Specifies the clock stable time before SRX. Recommended settings: - mDDR - 1 - LPDDR2 - 2 - LPDDR3 - 2 - LPDDR4 - tCKCKEH - DDR2 - 1 - DDR3 -.." newline hexmask.long.byte 0x14 20.--23. 1. "RESERVED,Reserved" newline hexmask.long.byte 0x14 16.--19. 1. "T_CKSRE,This is the time after self-refresh Down Entry that CK is maintained as a valid clock. Specifies the clock disable delay after SRE. Recommended settings: - mDDR - 0 - LPDDR2 - 2 - LPDDR3 - 2 - LPDDR4 - tCKELCK - DDR2 - 1 - DDR3 - Max (10 ns 5.." newline rbitfld.long 0x14 14.--15. "RESERVED,Reserved" "0,1,2,3" newline hexmask.long.byte 0x14 8.--13. 1. "T_CKESR,Indicates the minimum CKE low width for self-refresh or self-refresh power down entry to exit timing in memory clock cycles. Recommended settings: - mDDR - tRFC - LPDDR2 - tCKESR - LPDDR3 - tCKESR - LPDDR4 - max(tCKE tSR) - DDR2 - tCKE - DDR3 -.." newline rbitfld.long 0x14 5.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x14 0.--4. 1. "T_CKE,Indicates the minimum number of cycles of CKE HIGH/LOW during power-down and self-refresh. - LPDDR2/LPDDR3 mode - Set this to the larger of tCKE or tCKESR - LPDDR4 mode - Set this to the larger of tCKE or tSR - Non-LPDDR2/non-LPDDR3/non-LPDDR4.." line.long 0x18 "DRAMTMG6,SDRAM Timing Register 6" hexmask.long.byte 0x18 28.--31. 1. "RESERVED,Reserved" newline hexmask.long.byte 0x18 24.--27. 1. "T_CKDPDE,This is the time after Deep Power Down Entry that CK is maintained as a valid clock. Specifies the clock disable delay after DPDE. Recommended settings: - mDDR: 0 - LPDDR2: 2 - LPDDR3: 2 When the controller is operating in 1:2 frequency ratio.." newline hexmask.long.byte 0x18 20.--23. 1. "RESERVED,Reserved" newline hexmask.long.byte 0x18 16.--19. 1. "T_CKDPDX,This is the time before Deep Power Down Exit that CK is maintained as a valid clock before issuing DPDX. Specifies the clock stable time before DPDX. Recommended settings: - mDDR - 1 - LPDDR2 - 2 - LPDDR3 - 2 When the controller is operating in.." newline hexmask.long.word 0x18 4.--15. 1. "RESERVED,Reserved" newline hexmask.long.byte 0x18 0.--3. 1. "T_CKCSX,This is the time before Clock Stop Exit that CK is maintained as a valid clock before issuing Clock Stop Exit. Specifies the clock stable time before next command after Clock Stop Exit. Recommended settings: - mDDR - 1 - LPDDR2 - tXP + 2 - LPDDR3.." line.long 0x1C "DRAMTMG7,SDRAM Timing Register 7" hexmask.long.tbyte 0x1C 12.--31. 1. "RESERVED,Reserved" newline hexmask.long.byte 0x1C 8.--11. 1. "T_CKPDE,This is the time after Power Down Entry that CK is maintained as a valid clock. Specifies the clock disable delay after PDE. Recommended settings: - mDDR - 0 - LPDDR2 - 2 - LPDDR3 - 2 - LPDDR4 - tCKELCK When using DDR2/3/4 SDRAM this register.." newline hexmask.long.byte 0x1C 4.--7. 1. "RESERVED,Reserved" newline hexmask.long.byte 0x1C 0.--3. 1. "T_CKPDX,This is the time before Power Down Exit that CK is maintained as a valid clock before issuing PDX. Specifies the clock stable time before PDX. Recommended settings: - mDDR - 0 - LPDDR2 - 2 - LPDDR3 - 2 - LPDDR4 - tCKCKEH When using DDR2/3/4 SDRAM.." line.long 0x20 "DRAMTMG8,SDRAM Timing Register 8" rbitfld.long 0x20 31. "RESERVED,Reserved" "0,1" newline hexmask.long.byte 0x20 24.--30. 1. "T_XS_FAST_X32,tXS_FAST: Exit self-refresh to ZQCL ZQCS and MRS (only CL WR RTP and Geardown mode). When the controller is operating in 1:2 frequency ratio mode program this to the previous value divided by 2 and round up to next integer value. Note:.." newline rbitfld.long 0x20 23. "RESERVED,Reserved" "0,1" newline hexmask.long.byte 0x20 16.--22. 1. "T_XS_ABORT_X32,tXS_ABORT: Exit self-refresh to commands not requiring a locked DLL in self-refresh Abort. When the controller is operating in 1:2 frequency ratio mode program this to the previous value divided by 2 and round up to next integer value." newline rbitfld.long 0x20 15. "RESERVED,Reserved" "0,1" newline hexmask.long.byte 0x20 8.--14. 1. "T_XS_DLL_X32,tXSDLL: Exit self-refresh to commands requiring a locked DLL. When the controller is operating in 1:2 frequency ratio mode program this to the previous value divided by 2 and round up to next integer value. Note: Used only for DDR2 DDR3.." newline rbitfld.long 0x20 7. "RESERVED,Reserved" "0,1" newline hexmask.long.byte 0x20 0.--6. 1. "T_XS_X32,tXS: Exit self-refresh to commands not requiring a locked DLL. When the controller is operating in 1:2 frequency ratio mode program this to the previous value divided by 2 and round up to next integer value. Note: Used only for DDR2 DDR3 and.." line.long 0x24 "DRAMTMG9,SDRAM Timing Register 9" rbitfld.long 0x24 31. "RESERVED,Reserved" "0,1" newline bitfld.long 0x24 30. "DDR4_WR_PREAMBLE,DDR4 Write preamble mode. - 0 - 1tCK preamble - 1 - 2tCK preamble Present only with MEMC_FREQ_RATIO=2. Programming Mode: Quasi-dynamic Group 2 Group 4" "0,1" newline hexmask.long.word 0x24 19.--29. 1. "RESERVED,Reserved" newline bitfld.long 0x24 16.--18. "T_CCD_S,tCCD_S: This is the minimum time between two reads or two writes for different bank group. For bank switching (from bank 'a' to bank 'b') the minimum time is this value + 1. When the controller is operating in 1:2 frequency ratio mode program.." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x24 12.--15. 1. "RESERVED,Reserved" newline hexmask.long.byte 0x24 8.--11. 1. "T_RRD_S,tRRD_S: This is the minimum time between activates from bank 'a' to bank 'b' for different bank group. When the controller is operating in 1:2 frequency ratio mode program this to (tRRD_S/2) and round it up to the next integer value. Present.." newline rbitfld.long 0x24 6.--7. "RESERVED,Reserved" "0,1,2,3" newline hexmask.long.byte 0x24 0.--5. 1. "WR2RD_S,CWL + PL + BL/2 + tWTR_S Minimum time from write command to read command for different bank group. Includes time for bus turnaround recovery times and all per-bank per-rank and global constraints. Present only in designs configured to support.." line.long 0x28 "DRAMTMG10,SDRAM Timing Register 10" hexmask.long.word 0x28 21.--31. 1. "RESERVED,Reserved" newline hexmask.long.byte 0x28 16.--20. 1. "T_SYNC_GEAR,Indicates the time between MRS command and the sync pulse time. This must be even number of clocks. For DDR4-2666 and DDR4-3200 this parameter is defined as tMOD(min)+4nCK tMOD(min) is greater of 24nCK or 15ns 15ns / .625ns = 24 Max value.." newline rbitfld.long 0x28 13.--15. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x28 8.--12. 1. "T_CMD_GEAR,Indicates a sync pulse to first valid command. For DDR4-2666 and DDR4-3200 this parameter is defined as tMOD(min) tMOD(min) is greater of 24nCK or 15ns 15ns / .625ns = 24 Max value for this register is 24 When the controller is operating in.." newline hexmask.long.byte 0x28 4.--7. 1. "RESERVED,Reserved" newline bitfld.long 0x28 2.--3. "T_GEAR_SETUP,Indicates the geardown setup time. Minimum value of this register is 1. Zero is invalid. For DDR4-2666 and DDR4-3200 this parameter is defined as 2 clks When the controller is operating in 1:2 frequency ratio mode program this to.." "0,1,2,3" newline bitfld.long 0x28 0.--1. "T_GEAR_HOLD,Indicates the geardown hold time. Minimum value of this register is 1. Zero is invalid. For DDR4-2666 and DDR4-3200 this parameter is defined as 2 clks When the controller is operating in 1:2 frequency ratio mode program this to.." "0,1,2,3" line.long 0x2C "DRAMTMG11,SDRAM Timing Register 11" rbitfld.long 0x2C 31. "RESERVED,Reserved" "0,1" newline hexmask.long.byte 0x2C 24.--30. 1. "POST_MPSM_GAP_X32,tXMPDLL: This is the minimum Exit MPSM to commands requiring a locked DLL. When the controller is operating in 1:2 frequency ratio mode program this to (tXMPDLL/2) and round it up to the next integer value. Present only in designs.." newline rbitfld.long 0x2C 21.--23. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x2C 16.--20. 1. "T_MPX_LH,tMPX_LH: This is the minimum CS_n Low hold time to CKE rising edge. When the controller is operating in 1:2 frequency ratio mode program this to RoundUp(tMPX_LH/2)+1. Present only in designs configured to support DDR4. Unit: DFI clock cycles." newline hexmask.long.byte 0x2C 10.--15. 1. "RESERVED,Reserved" newline bitfld.long 0x2C 8.--9. "T_MPX_S,tMPX_S: This is the minimum time CS setup time to CKE. When the controller is operating in 1:2 frequency ratio mode program this to (tMPX_S/2) and round it up to the next integer value. Present only in designs configured to support DDR4. Unit:.." "0,1,2,3" newline rbitfld.long 0x2C 5.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x2C 0.--4. 1. "T_CKMPE,tCKMPE: This is the minimum valid clock requirement after MPSM entry. Present only in designs configured to support DDR4. When the controller is operating in 1:2 frequency ratio mode divide the value calculated using the previous equation by 2.." line.long 0x30 "DRAMTMG12,SDRAM Timing Register 12" rbitfld.long 0x30 30.--31. "RESERVED,Reserved" "0,1,2,3" newline hexmask.long.byte 0x30 24.--29. 1. "T_WR_MPR,This bit is used only in DDR4. Cycles between MPR Write and other command. Set this to tMOD + AL (or tMOD + PL + AL if C/A parity is also used). When the controller is operating in 1:2 frequency ratio mode program this to (tWR_MPR/2) and round.." newline hexmask.long.byte 0x30 18.--23. 1. "RESERVED,Reserved" newline bitfld.long 0x30 16.--17. "T_CMDCKE,tCMDCKE: Indicates the delay from valid command to CKE input LOW. Set this to the larger of tESCKE or tCMDCKE When the controller is operating in 1:2 frequency ratio mode program this to (max(tESCKE tCMDCKE)/2) and round it up to the next.." "0,1,2,3" newline hexmask.long.word 0x30 5.--15. 1. "RESERVED,Reserved" newline hexmask.long.byte 0x30 0.--4. 1. "T_MRD_PDA,tMRD_PDA: This is the Mode Register Set command cycle time in PDA mode. When the controller is operating in 1:2 frequency ratio mode program this to (tMRD_PDA/2) and round it up to the next integer value. Unit: DFI clock cycles. Programming.." line.long 0x34 "DRAMTMG13,SDRAM Timing Register 13" rbitfld.long 0x34 31. "RESERVED,Reserved" "0,1" newline hexmask.long.byte 0x34 24.--30. 1. "ODTLOFF,LPDDR4: ODTLoff: This is the latency from CAS-2 command to ODToff reference. When the controller is operating in 1:2 frequency ratio mode program this to (ODTLoff/2) and round it up to the next integer value. Unit: DFI clock cycles. Programming.." newline rbitfld.long 0x34 22.--23. "RESERVED,Reserved" "0,1,2,3" newline hexmask.long.byte 0x34 16.--21. 1. "T_CCD_MW,LPDDR4: tCCDMW: This is the minimum time from write or masked write to masked write command for same bank. When the controller is operating in 1:2 frequency ratio mode program this to (tCCDMW/2) and round it up to the next integer value. Unit:.." newline hexmask.long.word 0x34 3.--15. 1. "RESERVED,Reserved" newline bitfld.long 0x34 0.--2. "T_PPD,LPDDR4: tPPD: This is the minimum time from precharge to precharge command. When the controller is operating in 1:2 frequency ratio mode program this to (tPPD/2) and round it up to the next integer value. Unit: DFI clock cycles. Programming Mode:.." "?,?,?,?,tPPD: This is the minimum time from precharge to..,?,?,?" line.long 0x38 "DRAMTMG14,SDRAM Timing Register 14" hexmask.long.tbyte 0x38 12.--31. 1. "RESERVED,Reserved" newline hexmask.long.word 0x38 0.--11. 1. "T_XSR,tXSR: This is the exit self-refresh to any command. When the controller is operating in 1:2 frequency ratio mode program this to the previous value divided by 2 and round up to next integer value. The value 0xfff is illegal for this register.." line.long 0x3C "DRAMTMG15,SDRAM Timing Register 15" bitfld.long 0x3C 31. "EN_DFI_LP_T_STAB,- 1 - Enable using tSTAB when exiting DFI LP. This must be set when the PHY is stopping the clock during DFI LP to save maximum power. - 0 - Disable using tSTAB when exiting DFI LP. Programming Mode: Quasi-dynamic Group 2 Group 4" "Disable using tSTAB when exiting DFI LP,Enable using tSTAB when exiting DFI LP" newline hexmask.long.tbyte 0x3C 8.--30. 1. "RESERVED,Reserved" newline hexmask.long.byte 0x3C 0.--7. 1. "T_STAB_X32,tSTAB: Stabilization time. It is required in the following two cases for DDR3/DDR4 RDIMM: - When exiting power saving mode if the clock is stopped after re-enabling it the clock must be stable for a time specified by tSTAB - In the case of.." group.long 0x180++0xB line.long 0x0 "ZQCTL0,ZQ Control Register 0" bitfld.long 0x0 31. "DIS_AUTO_ZQ,- 1 - Disable uMCTL2 generation of ZQCS/MPC(ZQ calibration) command. Register DBGCMD.zq_calib_short can be used instead to issue ZQ calibration request from APB module - 0 - Internally generate ZQCS/MPC(ZQ calibration) commands based on.." "Internally generate ZQCS/MPC,Disable uMCTL2 generation of ZQCS/MPC" newline bitfld.long 0x0 30. "DIS_SRX_ZQCL,- 1 - Disable issuing of ZQCL/MPC(ZQ calibration) command at self-refresh/SR-Powerdown exit. Only applicable when run in DDR3 or DDR4 or LPDDR2 or LPDDR3 or LPDDR4 mode - 0 - Enable issuing of ZQCL/MPC(ZQ calibration) command at.." "Enable issuing of ZQCL/MPC,Disable issuing of ZQCL/MPC" newline bitfld.long 0x0 29. "ZQ_RESISTOR_SHARED,- 1 - Denotes that ZQ resistor is shared between ranks. Means ZQinit/ZQCL/ZQCS/MPC(ZQ calibration) commands are sent to one rank at a time with tZQinit/tZQCL/tZQCS/tZQCAL/tZQLAT timing met between commands so that commands to different.." "ZQ resistor is not shared,Denotes that ZQ resistor is shared between ranks" newline bitfld.long 0x0 28. "DIS_MPSMX_ZQCL,- 1 - Disable issuing of ZQCL command at Maximum Power Saving Mode exit. Only applicable when run in DDR4 mode - 0 - Enable issuing of ZQCL command at Maximum Power Saving Mode exit. Only applicable when run in DDR4 mode This is only.." "Enable issuing of ZQCL command at Maximum Power..,Disable issuing of ZQCL command at Maximum Power.." newline rbitfld.long 0x0 27. "RESERVED,Reserved" "0,1" newline hexmask.long.word 0x0 16.--26. 1. "T_ZQ_LONG_NOP,tZQoper for DDR3/DDR4 tZQCL for LPDDR2/LPDDR3 tZQCAL for LPDDR4: Number of DFI clock cycles of NOP required after a ZQCL (ZQ calibration long)/MPC(ZQ Start) command is issued to SDRAM. When the controller is operating in 1:2 frequency.." newline hexmask.long.byte 0x0 10.--15. 1. "RESERVED,Reserved" newline hexmask.long.word 0x0 0.--9. 1. "T_ZQ_SHORT_NOP,tZQCS for DDR3/DD4/LPDDR2/LPDDR3 tZQLAT for LPDDR4: Number of DFI clock cycles of NOP required after a ZQCS (ZQ calibration short)/MPC(ZQ Latch) command is issued to SDRAM. When the controller is operating in 1:2 frequency ratio mode.." line.long 0x4 "ZQCTL1,ZQ Control Register 1" rbitfld.long 0x4 30.--31. "RESERVED,Reserved" "0,1,2,3" newline hexmask.long.word 0x4 20.--29. 1. "T_ZQ_RESET_NOP,tZQReset: Number of DFI clock cycles of NOP required after a ZQReset (ZQ calibration Reset) command is issued to SDRAM. When the controller is operating in 1:2 frequency ratio mode program this to tZQReset/2 and round it up to the next.." newline hexmask.long.tbyte 0x4 0.--19. 1. "T_ZQ_SHORT_INTERVAL_X1024,Indicates the average interval to wait between automatically issuing ZQCS (ZQ calibration short)/MPC(ZQ calibration) commands to DDR3/DDR4/LPDDR2/LPDDR3/LPDDR4 devices. Meaningless if ZQCTL0.dis_auto_zq=1. This is only present.." line.long 0x8 "ZQCTL2,ZQ Control Register 2" hexmask.long 0x8 1.--31. 1. "RESERVED,Reserved" newline bitfld.long 0x8 0. "ZQ_RESET,Setting this register bit to 1 triggers a ZQ Reset operation. When the ZQ Reset operation is complete the uMCTL2 automatically clears this bit. It is recommended NOT to set this register bit if in Init in self-refresh(except LPDDR4) or.." "0,1" rgroup.long 0x18C++0x3 line.long 0x0 "ZQSTAT,ZQ Status Register" hexmask.long 0x0 1.--31. 1. "RESERVED,Reserved" newline bitfld.long 0x0 0. "ZQ_RESET_BUSY,SoC might initiate a ZQ Reset operation only if this signal is low. This signal goes high in the clock after the uMCTL2 accepts the ZQ Reset request. It goes low when the ZQ Reset command is issued to the SDRAM and the associated NOP period.." "Indicates that the SoC can initiate a ZQ Reset..,Indicates that ZQ Reset operation is in progress" group.long 0x190++0x1B line.long 0x0 "DFITMG0,DFI Timing Register 0" rbitfld.long 0x0 29.--31. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x0 24.--28. 1. "DFI_T_CTRL_DELAY,Specifies the number of DFI clock cycles after an assertion or de-assertion of the DFI control signals that the control signals at the PHY-DRAM interface reflect the assertion or de-assertion. If the DFI clock and the memory clock are.." newline bitfld.long 0x0 23. "DFI_RDDATA_USE_DFI_PHY_CLK,Defines whether dfi_rddata_en/dfi_rddata/dfi_rddata_valid is generated using HDR (DFI clock) or SDR (DFI PHY clock) values. Selects whether value in DFITMG0.dfi_t_rddata_en is in terms of HDR (DFI clock) or SDR (DFI PHY clock).." "Else,?" newline hexmask.long.byte 0x0 16.--22. 1. "DFI_T_RDDATA_EN,Time from the assertion of a read command on the DFI interface to the assertion of the dfi_rddata_en signal. Refer to PHY specification for correct value. This corresponds to the DFI parameter trddata_en. Note that depending on the PHY.." newline bitfld.long 0x0 15. "DFI_WRDATA_USE_DFI_PHY_CLK,Defines whether dfi_wrdata_en/dfi_wrdata/dfi_wrdata_mask is generated using HDR (DFI clock) or SDR (DFI PHY clock) values. Selects whether value in DFITMG0.dfi_tphy_wrlat is in terms of HDR (DFI clock) or SDR (DFI PHY clock).." "Else,?" newline rbitfld.long 0x0 14. "RESERVED,Reserved" "0,1" newline hexmask.long.byte 0x0 8.--13. 1. "DFI_TPHY_WRDATA,Specifies the number of clock cycles between when dfi_wrdata_en is asserted to when the associated write data is driven on the dfi_wrdata signal. This corresponds to the DFI timing parameter tphy_wrdata. For more information on correct.." newline rbitfld.long 0x0 6.--7. "RESERVED,Reserved" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "DFI_TPHY_WRLAT,Write latency. Number of clocks from the write command to write data enable (dfi_wrdata_en). This corresponds to the DFI timing parameter tphy_wrlat. Refer to PHY specification for correct value.Note that depending on the PHY if using.." line.long 0x4 "DFITMG1,DFI Timing Register 1" hexmask.long.byte 0x4 28.--31. 1. "DFI_T_CMD_LAT,Specifies the number of DFI PHY clock cycles between when the dfi_cs signal is asserted and when the associated command is driven. This field is used for CAL mode must be set to '0' or tCAL which matches the CAL mode register setting in.." newline rbitfld.long 0x4 26.--27. "RESERVED,Reserved" "0,1,2,3" newline bitfld.long 0x4 24.--25. "DFI_T_PARIN_LAT,Specifies the number of DFI PHY clock cycles between when the dfi_cs signal is asserted and when the associated dfi_parity_in signal is driven. Unit: DFI PHY clock cycles. Programming Mode: Quasi-dynamic Group 4" "0,1,2,3" newline rbitfld.long 0x4 21.--23. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x4 16.--20. 1. "DFI_T_WRDATA_DELAY,Specifies the number of DFI clock cycles between when the dfi_wrdata_en signal is asserted and when the corresponding write data transfer is completed on the DRAM bus. This corresponds to the DFI timing parameter twrdata_delay. For.." newline rbitfld.long 0x4 13.--15. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x4 8.--12. 1. "DFI_T_DRAM_CLK_DISABLE,Specifies the number of DFI clock cycles from the assertion of the dfi_dram_clk_disable signal on the DFI until the clock to the DRAM memory devices at the PHY-DRAM boundary maintains a low value. If the DFI clock and the memory.." newline rbitfld.long 0x4 5.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x4 0.--4. 1. "DFI_T_DRAM_CLK_ENABLE,Specifies the number of DFI clock cycles from the de-assertion of the dfi_dram_clk_disable signal on the DFI until the first valid rising edge of the clock to the DRAM memory devices at the PHY-DRAM boundary. If the DFI clock and.." line.long 0x8 "DFILPCFG0,DFI Low Power Configuration Register 0" rbitfld.long 0x8 29.--31. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x8 24.--28. 1. "DFI_TLP_RESP,Indicates the setting in DFI clock cycles for DFI's tlp_resp time. Same value is used for both Power Down self-refresh Deep Power Down and Maximum Power Saving modes. For more information on recommended values see PHY databook Unit: DFI.." newline hexmask.long.byte 0x8 20.--23. 1. "DFI_LP_WAKEUP_DPD,Indicates the value in DFI clock cycles to drive on dfi_lp_wakeup signal when Deep Power Down mode is entered. Determines the DFI's tlp_wakeup time: - 0x0 - 16 cycles - 0x1 - 32 cycles - 0x2 - 64 cycles - 0x3 - 128 cycles - 0x4 - 256.." newline rbitfld.long 0x8 17.--19. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 16. "DFI_LP_EN_DPD,Enables DFI Low Power interface handshaking during Deep Power Down Entry/Exit. - 0 - Disabled - 1 - Enabled This is only present for designs supporting mDDR or LPDDR2/LPDDR3 devices. Programming Mode: Static" "Disabled,Enabled" newline hexmask.long.byte 0x8 12.--15. 1. "DFI_LP_WAKEUP_SR,Indicates the value in DFI clock cycles to drive on dfi_lp_wakeup signal when self-refresh mode is entered. Determines the DFI's tlp_wakeup time: - 0x0 - 16 cycles - 0x1 - 32 cycles - 0x2 - 64 cycles - 0x3 - 128 cycles - 0x4 - 256 cycles.." newline rbitfld.long 0x8 9.--11. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 8. "DFI_LP_EN_SR,Enables DFI Low Power interface handshaking during self-refresh Entry/Exit. - 0 - Disabled - 1 - Enabled Programming Mode: Static" "Disabled,Enabled" newline hexmask.long.byte 0x8 4.--7. 1. "DFI_LP_WAKEUP_PD,Indicates the value in DFI clock cycles to drive on dfi_lp_wakeup signal when Power Down mode is entered. Determines the DFI's tlp_wakeup time: - 0x0 - 16 cycles - 0x1 - 32 cycles - 0x2 - 64 cycles - 0x3 - 128 cycles - 0x4 - 256 cycles -.." newline rbitfld.long 0x8 1.--3. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 0. "DFI_LP_EN_PD,Enables DFI Low Power interface handshaking during Power Down Entry/Exit. - 0 - Disabled - 1 - Enabled Programming Mode: Static" "Disabled,Enabled" line.long 0xC "DFILPCFG1,DFI Low Power Configuration Register 1" hexmask.long.tbyte 0xC 8.--31. 1. "RESERVED,Reserved" newline hexmask.long.byte 0xC 4.--7. 1. "DFI_LP_WAKEUP_MPSM,Indicates the value in DFI clock cycles to drive on dfi_lp_wakeup signal when Maximum Power Saving Mode is entered. Determines the DFI's tlp_wakeup time: - 0x0 - 16 cycles - 0x1 - 32 cycles - 0x2 - 64 cycles - 0x3 - 128 cycles - 0x4 -.." newline rbitfld.long 0xC 1.--3. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline bitfld.long 0xC 0. "DFI_LP_EN_MPSM,Enables DFI Low Power interface handshaking during Maximum Power Saving Mode Entry/Exit. - 0 - Disabled - 1 - Enabled This is only present for designs supporting DDR4 devices. Programming Mode: Static" "Disabled,Enabled" line.long 0x10 "DFIUPD0,DFI Update Register 0" bitfld.long 0x10 31. "DIS_AUTO_CTRLUPD,When '1' disable the automatic dfi_ctrlupd_req generation by the uMCTL2. The controller must issue the dfi_ctrlupd_req signal using register DBGCMD.ctrlupd. When '0' uMCTL2 issues dfi_ctrlupd_req periodically. Programming Mode:.." "0,1" newline bitfld.long 0x10 30. "DIS_AUTO_CTRLUPD_SRX,When '1' disable the automatic dfi_ctrlupd_req generation by the uMCTL2 at self-refresh exit. When '0' uMCTL2 issues a dfi_ctrlupd_req before or after exiting self-refresh depending on DFIUPD0.ctrlupd_pre_srx. Programming Mode:.." "0,1" newline bitfld.long 0x10 29. "CTRLUPD_PRE_SRX,Selects dfi_ctrlupd_req requirements at SRX: - 0 - Send ctrlupd after SRX - 1 - Send ctrlupd before SRX If DFIUPD0.dis_auto_ctrlupd_srx=1 this register has no impact because no dfi_ctrlupd_req is issued when SRX. Programming Mode: Static" "Send ctrlupd after SRX,Send ctrlupd before SRX" newline rbitfld.long 0x10 26.--28. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline hexmask.long.word 0x10 16.--25. 1. "DFI_T_CTRLUP_MAX,Specifies the maximum number of DFI clock cycles that the dfi_ctrlupd_req signal can assert. Lowest value to assign to this variable is 0x40. Unit: DFI clock cycles. Programming Mode: Static" newline hexmask.long.byte 0x10 10.--15. 1. "RESERVED,Reserved" newline hexmask.long.word 0x10 0.--9. 1. "DFI_T_CTRLUP_MIN,Specifies the minimum number of DFI clock cycles that the dfi_ctrlupd_req signal must be asserted. The uMCTL2 expects the PHY to respond within this time. If the PHY does not respond the uMCTL2 de-asserts dfi_ctrlupd_req after.." line.long 0x14 "DFIUPD1,DFI Update Register 1" hexmask.long.byte 0x14 24.--31. 1. "RESERVED,Reserved" newline hexmask.long.byte 0x14 16.--23. 1. "DFI_T_CTRLUPD_INTERVAL_MIN_X1024,This is the minimum amount of time between uMCTL2 initiated DFI update requests (which is executed whenever the uMCTL2 is idle). Set this number higher to reduce the frequency of update requests which can have a small.." newline hexmask.long.byte 0x14 8.--15. 1. "RESERVED,Reserved" newline hexmask.long.byte 0x14 0.--7. 1. "DFI_T_CTRLUPD_INTERVAL_MAX_X1024,This is the maximum amount of time between uMCTL2 initiated DFI update requests. This timer resets with each update request; when the timer expires dfi_ctrlupd_req is sent and traffic is blocked until the dfi_ctrlupd_ackx.." line.long 0x18 "DFIUPD2,DFI Update Register 2" bitfld.long 0x18 31. "DFI_PHYUPD_EN,Enables the support for acknowledging PHY-initiated updates: - 0 - Disabled - 1 - Enabled Programming Mode: Static" "Disabled,Enabled" newline hexmask.long 0x18 0.--30. 1. "RESERVED,Reserved" group.long 0x1B0++0xB line.long 0x0 "DFIMISC,DFI Miscellaneous Control Register" hexmask.long.tbyte 0x0 13.--31. 1. "RESERVED,Reserved" newline hexmask.long.byte 0x0 8.--12. 1. "DFI_FREQUENCY,Indicates the operating frequency of the system. The number of supported frequencies and the mapping of signal values to clock frequencies are defined by the PHY. Programming Mode: Quasi-dynamic Group 1" newline bitfld.long 0x0 7. "LP_OPTIMIZED_WRITE,If this bit is 1 LPDDR4 write DQ is set to 8'hF8 if masked write with enabling DBI; otherwise that value is set to 8'hFF. Programming Mode: Quasi-dynamic Group 3" "0,1" newline bitfld.long 0x0 6. "DIS_DYN_ADR_TRI,If this bit is 1 PHY specific Dynamic Tristating which is a specific feature to certain Synopsys PHYs is disabled. If this bit is 0 a special IDLE command is issued on the DFI while dfi_cs is inactive state so that the PHY can detect.." "?,phase 0 and 1) dfi_we_n= 1" newline bitfld.long 0x0 5. "DFI_INIT_START,PHY init start request signal.When asserted it triggers the PHY init start request. Programming Mode: Quasi-dynamic Group 3" "0,1" newline bitfld.long 0x0 4. "CTL_IDLE_EN,Enables support of ctl_idle signal which is non-DFI related pin specific to certain Synopsys PHYs. For more information on ctl_idle functionality see signal description of ctl_idle signal. Programming Mode: Static" "0,1" newline rbitfld.long 0x0 3. "RESERVED,Reserved" "0,1" newline bitfld.long 0x0 2. "DFI_DATA_CS_POLARITY,Defines polarity of dfi_wrdata_cs and dfi_rddata_cs signals. - 0 - Signals are active low - 1 - Signals are active high Programming Mode: Static" "Signals are active low,Signals are active high" newline bitfld.long 0x0 1. "PHY_DBI_MODE,DBI implemented in DDRC or PHY. - 0 - DDRC implements DBI functionality - 1 - PHY implements DBI functionality Present only in designs configured to support DDR4 and LPDDR4. Programming Mode: Static" "DDRC implements DBI functionality,PHY implements DBI functionality" newline bitfld.long 0x0 0. "DFI_INIT_COMPLETE_EN,PHY initialization complete enable signal. When asserted the dfi_init_complete signal can be used to trigger SDRAM initialisation Programming Mode: Quasi-dynamic Group 3" "0,1" line.long 0x4 "DFITMG2,DFI Timing Register 2" hexmask.long.tbyte 0x4 15.--31. 1. "RESERVED,Reserved" newline hexmask.long.byte 0x4 8.--14. 1. "DFI_TPHY_RDCSLAT,specifies the number of DFI PHY clock cycles between when a read command is sent on the DFI control interface and when the associated dfi_rddata_cs signal is asserted. This corresponds to the DFI timing parameter tphy_rdcslat. Refer to.." newline rbitfld.long 0x4 6.--7. "RESERVED,Reserved" "0,1,2,3" newline hexmask.long.byte 0x4 0.--5. 1. "DFI_TPHY_WRCSLAT,Specifies the number of DFI PHY clock cycles between when a write command is sent on the DFI control interface and when the associated dfi_wrdata_cs signal is asserted. This corresponds to the DFI timing parameter tphy_wrcslat. For more.." line.long 0x8 "DFITMG3,DFI Timing Register 3" hexmask.long 0x8 5.--31. 1. "RESERVED,Reserved" newline hexmask.long.byte 0x8 0.--4. 1. "DFI_T_GEARDOWN_DELAY,The delay from dfi_geardown_en assertion to the time of the PHY being ready to receive commands. Refer to PHY specification for correct value. When the controller is operating in 1:2 frequency ratio mode program this to.." rgroup.long 0x1BC++0x3 line.long 0x0 "DFISTAT,DFI Status Register" hexmask.long 0x0 2.--31. 1. "RESERVED,Reserved" newline bitfld.long 0x0 1. "DFI_LP_ACK,Stores the value of the dfi_lp_ack input to the controller. Programming Mode: Dynamic" "0,1" newline bitfld.long 0x0 0. "DFI_INIT_COMPLETE,This a status flag register which announces when the DFI initialization has been completed. The DFI INIT triggered by dfi_init_start signal and then the dfi_init_complete flag is polled to know when the initialization is done." "0,1" group.long 0x1C0++0x7 line.long 0x0 "DBICTL,DM/DBI Control Register" hexmask.long 0x0 3.--31. 1. "RESERVED,Reserved" newline bitfld.long 0x0 2. "RD_DBI_EN,Read DBI enable signal in DDRC. - 0 - Read DBI is disabled - 1 - Read DBI is enabled This signal must be set the same value as DRAM's mode register. - DDR4 - MR5 bit A12. When x4 devices are used this signal must be set to 0 - LPDDR4 - MR3[6].." "LPDDR4,Read DBI is enabled" newline bitfld.long 0x0 1. "WR_DBI_EN,Write DBI enable signal in DDRC. - 0 - Write DBI is disabled - 1 - Write DBI is enabled This signal must be set the same value as DRAM's mode register. - DDR4 - MR5 bit A11. When x4 devices are used this signal must be set to 0 - LPDDR4 -.." "LPDDR4,Write DBI is enabled" newline bitfld.long 0x0 0. "DM_EN,Indicates the DM enable signal in DDRC. - 0 - DM is disabled - 1 - DM is enabled This signal must be set the same logical value as DRAM's mode register. - DDR4 - Set this to same value as MR5 bit A10. When x4 devices are used this signal must be.." "LPDDR4,DM is enabled" line.long 0x4 "DFIPHYMSTR,DFI PHY Master" hexmask.long 0x4 1.--31. 1. "RESERVED,Reserved" newline bitfld.long 0x4 0. "DFI_PHYMSTR_EN,Enables the PHY Master Interface: - 0 - Disabled - 1 - Enabled Programming Mode: Static" "Disabled,Enabled" group.long 0x200++0x13 line.long 0x0 "ADDRMAP0,Address Map Register 0" hexmask.long 0x0 5.--31. 1. "RESERVED,Reserved" newline hexmask.long.byte 0x0 0.--4. 1. "ADDRMAP_CS_BIT0,Selects the HIF address bit used as rank address bit 0. Valid Range: 0 to 29 and 31 Internal Base: 6 The selected HIF address bit is determined by adding the internal base to the value of this field. If unused set to 31 and then rank.." line.long 0x4 "ADDRMAP1,Address Map Register 1" hexmask.long.word 0x4 22.--31. 1. "RESERVED,Reserved" newline hexmask.long.byte 0x4 16.--21. 1. "ADDRMAP_BANK_B2,Selects the HIF address bit used as bank address bit 2. Valid Range: 0 to 31 and 63 Internal Base: 4 The selected HIF address bit is determined by adding the internal base to the value of this field. If unused set to 63 and then bank.." newline rbitfld.long 0x4 14.--15. "RESERVED,Reserved" "0,1,2,3" newline hexmask.long.byte 0x4 8.--13. 1. "ADDRMAP_BANK_B1,Selects the HIF address bits used as bank address bit 1. Valid Range: 0 to 32 and 63 Internal Base: 3 The selected HIF address bit for each of the bank address bits is determined by adding the internal base to the value of this field. If.." newline rbitfld.long 0x4 6.--7. "RESERVED,Reserved" "0,1,2,3" newline hexmask.long.byte 0x4 0.--5. 1. "ADDRMAP_BANK_B0,Selects the HIF address bits used as bank address bit 0. Valid Range: 0 to 32 and 63 Internal Base: 2 The selected HIF address bit for each of the bank address bits is determined by adding the internal base to the value of this field. If.." line.long 0x8 "ADDRMAP2,Address Map Register 2" hexmask.long.byte 0x8 28.--31. 1. "RESERVED,Reserved" newline hexmask.long.byte 0x8 24.--27. 1. "ADDRMAP_COL_B5,- Full bus width mode - Selects the HIF address bit used as column address bit 5 - Half bus width mode - Selects the HIF address bit used as column address bit 6 - Quarter bus width mode - Selects the HIF address bit used as column address.." newline hexmask.long.byte 0x8 20.--23. 1. "RESERVED,Reserved" newline hexmask.long.byte 0x8 16.--19. 1. "ADDRMAP_COL_B4,- Full bus width mode - Selects the HIF address bit used as column address bit 4 - Half bus width mode - Selects the HIF address bit used as column address bit 5 - Quarter bus width mode - Selects the HIF address bit used as column address.." newline rbitfld.long 0x8 13.--15. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x8 8.--12. 1. "ADDRMAP_COL_B3,- Full bus width mode - Selects the HIF address bit used as column address bit 3 - Half bus width mode - Selects the HIF address bit used as column address bit 4 - Quarter bus width mode - Selects the HIF address bit used as column address.." newline hexmask.long.byte 0x8 4.--7. 1. "RESERVED,Reserved" newline hexmask.long.byte 0x8 0.--3. 1. "ADDRMAP_COL_B2,- Full bus width mode - Selects the HIF address bit used as column address bit 2 - Half bus width mode - Selects the HIF address bit used as column address bit 3 - Quarter bus width mode - Selects the HIF address bit used as column address.." line.long 0xC "ADDRMAP3,Address Map Register 3" rbitfld.long 0xC 29.--31. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0xC 24.--28. 1. "ADDRMAP_COL_B9,- Full bus width mode - Selects the HIF address bit used as column address bit 9 - Half bus width mode - Selects the HIF address bit used as column address bit 11 (10 in LPDDR2/LPDDR3 mode) - Quarter bus width mode - Selects the HIF.." newline rbitfld.long 0xC 21.--23. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0xC 16.--20. 1. "ADDRMAP_COL_B8,- Full bus width mode - Selects the HIF address bit used as column address bit 8 - Half bus width mode - Selects the HIF address bit used as column address bit 9 - Quarter bus width mode - Selects the HIF address bit used as column address.." newline rbitfld.long 0xC 13.--15. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0xC 8.--12. 1. "ADDRMAP_COL_B7,- Full bus width mode - Selects the HIF address bit used as column address bit 7 - Half bus width mode - Selects the HIF address bit used as column address bit 8 - Quarter bus width mode - Selects the HIF address bit used as column address.." newline rbitfld.long 0xC 5.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0xC 0.--4. 1. "ADDRMAP_COL_B6,- Full bus width mode - Selects the HIF address bit used as column address bit 6. - Half bus width mode - Selects the HIF address bit used as column address bit 7. - Quarter bus width mode - Selects the HIF address bit used as column.." line.long 0x10 "ADDRMAP4,Address Map Register 4" bitfld.long 0x10 31. "COL_ADDR_SHIFT,The register provides a capability to map column address to lower HIF address in specific cases required by inline ECC configuration. - If it is 1 internal base of all the column address can be -2 to make mapping range of column address.." "0,1" newline hexmask.long.tbyte 0x10 13.--30. 1. "RESERVED,Reserved" newline hexmask.long.byte 0x10 8.--12. 1. "ADDRMAP_COL_B11,- Full bus width mode - Selects the HIF address bit used as column address bit 13 (11 in LPDDR2/LPDDR3 mode) - Half bus width mode - UNUSED. See later in this description for value you need to set to make it unused - Quarter bus width.." newline rbitfld.long 0x10 5.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x10 0.--4. 1. "ADDRMAP_COL_B10,- Full bus width mode: Selects the HIF address bit used as column address bit 11 (10 in LPDDR2/LPDDR3 mode) - Half bus width mode: Selects the HIF address bit used as column address bit 13 (11 in LPDDR2/LPDDR3 mode) - Quarter bus width.." repeat 3. (list 0x5 0x9 0xA )(list 0x0 0x10 0x14 ) group.long ($2+0x214)++0x3 line.long 0x0 "ADDRMAP$1,Address Map Register 5" hexmask.long.byte 0x0 28.--31. 1. "RESERVED,Reserved" newline hexmask.long.byte 0x0 24.--27. 1. "ADDRMAP_ROW_B11,Selects the HIF address bit used as row address bit 11. Valid Range: 0 to 11 and 15 Internal Base: 17 The selected HIF address bit is determined by adding the internal base to the value of this field. If unused set to 15 and then row.." newline hexmask.long.byte 0x0 20.--23. 1. "RESERVED,Reserved" newline hexmask.long.byte 0x0 16.--19. 1. "ADDRMAP_ROW_B2_10,Selects the HIF address bits used as row address bits 2 to 10. Valid Range: 0 to 11 and 15 Internal Base: 8 (for row address bit 2) 9 (for row address bit 3) 10 (for row address bit 4) and so on increasing to 16 (for row address bit.." newline hexmask.long.byte 0x0 12.--15. 1. "RESERVED,Reserved" newline hexmask.long.byte 0x0 8.--11. 1. "ADDRMAP_ROW_B1,Selects the HIF address bits used as row address bit 1. Valid Range: 0 to 11 Internal Base: 7 The selected HIF address bit for each of the row address bits is determined by adding the internal base to the value of this field. Programming.." newline hexmask.long.byte 0x0 4.--7. 1. "RESERVED,Reserved" newline hexmask.long.byte 0x0 0.--3. 1. "ADDRMAP_ROW_B0,Selects the HIF address bits used as row address bit 0. Valid Range: 0 to 11 Internal Base: 6 The selected HIF address bit for each of the row address bits is determined by adding the internal base to the value of this field. Programming.." repeat.end group.long 0x218++0xB line.long 0x0 "ADDRMAP6,Address Map Register 6" bitfld.long 0x0 31. "LPDDR3_6GB_12GB,Set this to 1 if there is an LPDDR3 SDRAM 6Gb or 12Gb device in use. - 1 - LPDDR3 SDRAM 6Gb/12Gb device in use. Every address having row[14:13]==2'b11 is considered as invalid - 0 - non-LPDDR3 6Gb/12Gb device in use. All addresses are.." "non-LPDDR3 6Gb/12Gb device in use,LPDDR3 SDRAM 6Gb/12Gb device in use" newline bitfld.long 0x0 29.--30. "LPDDR4_3GB_6GB_12GB,Indicates what type of LPDDR4 SDRAM device is in use. Here the density size is per channel. - 2'b00 - No LPDDR4 SDRAM 3Gb/6Gb/12Gb device in use. All addresses are valid - 2'b01 - LPDDR4 SDRAM 3Gb device with x16 mode in use. Every.." "No LPDDR4 SDRAM 3Gb/6Gb/12Gb device in use,LPDDR4 SDRAM 3Gb device with x16 mode in use,LPDDR4 SDRAM 6Gb device with x16 mode or 3Gb..,LPDDR4 SDRAM 12Gb device with x16 mode or 6Gb.." newline rbitfld.long 0x0 28. "RESERVED,Reserved" "0,1" newline hexmask.long.byte 0x0 24.--27. 1. "ADDRMAP_ROW_B15,Selects the HIF address bit used as row address bit 15. Valid Range: 0 to 11 and 15 Internal Base: 21 The selected HIF address bit is determined by adding the internal base to the value of this field. If unused set to 15 and then row.." newline hexmask.long.byte 0x0 20.--23. 1. "RESERVED,Reserved" newline hexmask.long.byte 0x0 16.--19. 1. "ADDRMAP_ROW_B14,Selects the HIF address bit used as row address bit 14. Valid Range: 0 to 11 and 15 Internal Base: 20 The selected HIF address bit is determined by adding the internal base to the value of this field. If unused set to 15 and then row.." newline hexmask.long.byte 0x0 12.--15. 1. "RESERVED,Reserved" newline hexmask.long.byte 0x0 8.--11. 1. "ADDRMAP_ROW_B13,Selects the HIF address bit used as row address bit 13. Valid Range: 0 to 11 and 15 Internal Base: 19 The selected HIF address bit is determined by adding the internal base to the value of this field. If unused set to 15 and then row.." newline hexmask.long.byte 0x0 4.--7. 1. "RESERVED,Reserved" newline hexmask.long.byte 0x0 0.--3. 1. "ADDRMAP_ROW_B12,Selects the HIF address bit used as row address bit 12. Valid Range: 0 to 11 and 15 Internal Base: 18 The selected HIF address bit is determined by adding the internal base to the value of this field. If unused set to 15 and then row.." line.long 0x4 "ADDRMAP7,Address Map Register 7" hexmask.long.tbyte 0x4 12.--31. 1. "RESERVED,Reserved" newline hexmask.long.byte 0x4 8.--11. 1. "ADDRMAP_ROW_B17,Selects the HIF address bit used as row address bit 17. Valid Range: 0 to 11 and 15 Internal Base: 23 The selected HIF address bit is determined by adding the internal base to the value of this field. If unused set to 15 and then row.." newline hexmask.long.byte 0x4 4.--7. 1. "RESERVED,Reserved" newline hexmask.long.byte 0x4 0.--3. 1. "ADDRMAP_ROW_B16,Selects the HIF address bit used as row address bit 16. Valid Range: 0 to 11 and 15 Internal Base: 22 The selected HIF address bit is determined by adding the internal base to the value of this field. If unused set to 15 and then row.." line.long 0x8 "ADDRMAP8,Address Map Register 8" hexmask.long.tbyte 0x8 14.--31. 1. "RESERVED,Reserved" newline hexmask.long.byte 0x8 8.--13. 1. "ADDRMAP_BG_B1,Selects the HIF address bits used as bank group address bit 1. Valid Range: 0 to 32 and 63 Internal Base: 3 The selected HIF address bit for each of the bank group address bits is determined by adding the internal base to the value of this.." newline rbitfld.long 0x8 6.--7. "RESERVED,Reserved" "0,1,2,3" newline hexmask.long.byte 0x8 0.--5. 1. "ADDRMAP_BG_B0,Selects the HIF address bits used as bank group address bit 0. Valid Range: 0 to 32 and 63 Internal Base: 2 The selected HIF address bit for each of the bank group address bits is determined by adding the internal base to the value of this.." group.long 0x22C++0x3 line.long 0x0 "ADDRMAP11,Address Map Register 11" hexmask.long 0x0 4.--31. 1. "RESERVED,Reserved" newline hexmask.long.byte 0x0 0.--3. 1. "ADDRMAP_ROW_B10,Selects the HIF address bits used as row address bit 10. Valid Range: 0 to 11 Internal Base: 16 The selected HIF address bit for each of the row address bits is determined by adding the internal base to the value of this field. This.." group.long 0x240++0x7 line.long 0x0 "ODTCFG,ODT Configuration Register" hexmask.long.byte 0x0 28.--31. 1. "RESERVED,Reserved" newline hexmask.long.byte 0x0 24.--27. 1. "WR_ODT_HOLD,DFI PHY clock cycles to hold ODT for a write command. The minimum supported value is 2. Recommended values: DDR2: - BL8 - 0x5 (DDR2-400/533/667) 0x6 (DDR2-800) 0x7 (DDR2-1066) - BL4 - 0x3 (DDR2-400/533/667) 0x4 (DDR2-800) 0x5 (DDR2-1066).." newline rbitfld.long 0x0 21.--23. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x0 16.--20. 1. "WR_ODT_DELAY,Indicates the delay in DFI PHY clock cycles from issuing a write command to setting ODT values associated with that command. ODT setting must remain constant for the entire time that DQS is driven by the uMCTL2. Recommended values: DDR2: -.." newline hexmask.long.byte 0x0 12.--15. 1. "RESERVED,Reserved" newline hexmask.long.byte 0x0 8.--11. 1. "RD_ODT_HOLD,DFI PHY clock cycles to hold ODT for a read command. The minimum supported value is 2. Recommended values: DDR2: - BL8 - 0x6 (not DDR2-1066) 0x7 (DDR2-1066) - BL4 - 0x4 (not DDR2-1066) 0x5 (DDR2-1066) DDR3: - BL8 - 0x6 DDR4: - BL8 - 5 +.." newline rbitfld.long 0x0 7. "RESERVED,Reserved" "0,1" newline hexmask.long.byte 0x0 2.--6. 1. "RD_ODT_DELAY,Indicates the delay in DFI PHY clock cycles from issuing a read command to setting ODT values associated with that command. ODT setting must remain constant for the entire time that DQS is driven by the uMCTL2. Recommended values: DDR2: -.." newline rbitfld.long 0x0 0.--1. "RESERVED,Reserved" "0,1,2,3" line.long 0x4 "ODTMAP,ODT/Rank Map Register" hexmask.long.tbyte 0x4 14.--31. 1. "RESERVED,Reserved" newline bitfld.long 0x4 12.--13. "RANK1_RD_ODT,Indicates which remote ODTs must be turned on during a read from rank 1. Each rank has a remote ODT (in the SDRAM) which can be turned on by setting the appropriate bit here. Rank 0 is controlled by the LSB; rank 1 is controlled by bit next.." "0,1,2,3" newline rbitfld.long 0x4 10.--11. "RESERVED,Reserved" "0,1,2,3" newline bitfld.long 0x4 8.--9. "RANK1_WR_ODT,Indicates which remote ODTs must be turned on during a write to rank 1. Each rank has a remote ODT (in the SDRAM) which can be turned on by setting the appropriate bit here. Rank 0 is controlled by the LSB; rank 1 is controlled by bit next.." "0,1,2,3" newline rbitfld.long 0x4 6.--7. "RESERVED,Reserved" "0,1,2,3" newline bitfld.long 0x4 4.--5. "RANK0_RD_ODT,Indicates which remote ODTs must be turned on during a read from rank 0. Each rank has a remote ODT (in the SDRAM) which can be turned on by setting the appropriate bit here. Rank 0 is controlled by the LSB; rank 1 is controlled by bit next.." "0,1,2,3" newline rbitfld.long 0x4 2.--3. "RESERVED,Reserved" "0,1,2,3" newline bitfld.long 0x4 0.--1. "RANK0_WR_ODT,Indicates which remote ODTs must be turned on during a write to rank 0. Each rank has a remote ODT (in the SDRAM) which can be turned on by setting the appropriate bit here. Rank 0 is controlled by the LSB; rank 1 is controlled by bit next.." "0,1,2,3" group.long 0x250++0x7 line.long 0x0 "SCHED,Scheduler Control Register" rbitfld.long 0x0 31. "RESERVED,Reserved" "0,1" newline hexmask.long.byte 0x0 24.--30. 1. "RDWR_IDLE_GAP,When the preferred transaction store is empty for these many clock cycles switch to the alternate transaction store if it is non-empty. The read transaction store (both high and low priority) is the default preferred transaction store and.." newline hexmask.long.byte 0x0 16.--23. 1. "GO2CRITICAL_HYSTERESIS,UNUSED. Programming Mode: Static" newline bitfld.long 0x0 15. "LPDDR4_OPT_ACT_TIMING,Optimized ACT timing control for LPDDR4. In LPDDR4 RD/WR/ACT takes 4 cycle. To stream Read/Write there are only 4 cycle space between Reads/Writes. If ACT is scheduled-out after RD/WR with 1 2 or 3 cycle gap next RD/WR may be.." "Disable this feature,Enable this feature" newline rbitfld.long 0x0 13.--14. "RESERVED,Reserved" "0,1,2,3" newline hexmask.long.byte 0x0 8.--12. 1. "LPR_NUM_ENTRIES,Number of entries in the low priority transaction store is this value + 1. (MEMC_NO_OF_ENTRY - (SCHED.lpr_num_entries + 1)) is the number of entries available for the high priority transaction store. Setting this to maximum value.." newline bitfld.long 0x0 7. "AUTOPRE_RMW,Selects behavior of hif_cmd_autopre if a RMW is received on HIF with hif_cmd_autopre=1 - 1 - Apply Autopre only for write part of RMW - 0 - Apply Autopre for both read and write parts of RMW Programming Mode: Static" "Apply Autopre for both read and write parts of RMW,Apply Autopre only for write part of RMW" newline hexmask.long.byte 0x0 3.--6. 1. "RESERVED,Reserved" newline bitfld.long 0x0 2. "PAGECLOSE,If true bank is kept open only while there are page hit transactions available in the CAM to that bank. The last read or write command in the CAM with a bank and page hit is executed with auto-precharge if SCHED1.pageclose_timer=0. Even if.." "0,1" newline bitfld.long 0x0 1. "PREFER_WRITE,If set then the bank selector prefers writes over reads. FOR DEBUG ONLY. Programming Mode: Static" "0,1" newline rbitfld.long 0x0 0. "RESERVED,Reserved" "0,1" line.long 0x4 "SCHED1,Scheduler Control Register 1" hexmask.long.tbyte 0x4 8.--31. 1. "RESERVED,Reserved" newline hexmask.long.byte 0x4 0.--7. 1. "PAGECLOSE_TIMER,This field works in conjunction with SCHED.pageclose.It only has meaning if SCHED.pageclose==1. If SCHED.pageclose==1 and pageclose_timer==0 then an auto-precharge may be scheduled for last read or write command in the CAM with a bank.." group.long 0x25C++0x3 line.long 0x0 "PERFHPR1,High Priority Read CAM Register 1" hexmask.long.byte 0x0 24.--31. 1. "HPR_XACT_RUN_LENGTH,Indicates the number of transactions that are serviced once the HPR queue goes critical is the smaller of: - (a) This number - (b) Number of transactions available Unit: Transaction. FOR PERFORMANCE ONLY. Programming Mode:.." newline hexmask.long.byte 0x0 16.--23. 1. "RESERVED,Reserved" newline hexmask.long.word 0x0 0.--15. 1. "HPR_MAX_STARVE,Indicates the number of DFI clocks that the HPR queue can be starved before it goes critical. The minimum valid functional value for this register is 0x1. Programming it to 0x0 disables the starvation functionality. During normal operation.." group.long 0x264++0x3 line.long 0x0 "PERFLPR1,Low Priority Read CAM Register 1" hexmask.long.byte 0x0 24.--31. 1. "LPR_XACT_RUN_LENGTH,Indicates the number of transactions that are serviced once the LPR queue goes critical is the smaller of: - (a) This number - (b) Number of transactions available Unit: Transaction. FOR PERFORMANCE ONLY. Programming Mode:.." newline hexmask.long.byte 0x0 16.--23. 1. "RESERVED,Reserved" newline hexmask.long.word 0x0 0.--15. 1. "LPR_MAX_STARVE,Indicates the number of DFI clocks that the LPR queue can be starved before it goes critical. The minimum valid functional value for this register is 0x1. Programming it to 0x0 disables the starvation functionality. During normal operation.." group.long 0x26C++0x3 line.long 0x0 "PERFWR1,Write CAM Register 1" hexmask.long.byte 0x0 24.--31. 1. "W_XACT_RUN_LENGTH,Indicates the number of transactions that are serviced once the WR queue goes critical is the smaller of: - (a) This number - (b) Number of transactions available Unit: Transaction. FOR PERFORMANCE ONLY. Programming Mode: Quasi-dynamic.." newline hexmask.long.byte 0x0 16.--23. 1. "RESERVED,Reserved" newline hexmask.long.word 0x0 0.--15. 1. "W_MAX_STARVE,Indicates the number of DFI clocks that the WR queue can be starved before it goes critical. The minimum valid functional value for this register is 0x1. Programming it to 0x0 disables the starvation functionality. During normal operation.." group.long 0x300++0x7 line.long 0x0 "DBG0,Debug Register 0" hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED,Reserved" newline bitfld.long 0x0 7. "DIS_MAX_RANK_WR_OPT,Indicates the disable optimized max_rank_wr and max_logical_rank_wr feature. This register is for debug purpose only. For normal operation This register must be set to 0. Programming Mode: Static" "0,1" newline bitfld.long 0x0 6. "DIS_MAX_RANK_RD_OPT,Indicates the disable optimized max_rank_rd and max_logical_rank_rd feature. This register is for debug purpose only. For normal operation This register must be set to 0. Programming Mode: Static" "0,1" newline rbitfld.long 0x0 5. "RESERVED,Reserved" "0,1" newline bitfld.long 0x0 4. "DIS_COLLISION_PAGE_OPT,When this is set to '0' auto-precharge is disabled for the flushed command in a collision case. Collision cases are write followed by read to same address read followed by write to same address or write followed by write to same.." "0,1" newline rbitfld.long 0x0 1.--3. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 0. "DIS_WC,When 1 disable write combine. FOR DEBUG ONLY. Programming Mode: Static" "0,1" line.long 0x4 "DBG1,Debug Register 1" hexmask.long 0x4 2.--31. 1. "RESERVED,Reserved" newline bitfld.long 0x4 1. "DIS_HIF,When 1 uMCTL2 asserts the HIF command signal hif_cmd_stall. uMCTL2 ignores the hif_cmd_valid and all other associated request signals. This bit is intended to be switched on-the-fly. Programming Mode: Dynamic" "0,1" newline bitfld.long 0x4 0. "DIS_DQ,When 1 uMCTL2 does not de-queue any transactions from the CAM. Bypass is also disabled. All transactions are queued in the CAM. No reads or writes are issued to SDRAM as long as this is asserted. This bit may be used to prevent reads or writes.." "0,1" rgroup.long 0x308++0x3 line.long 0x0 "DBGCAM,CAM Debug Register" bitfld.long 0x0 30.--31. "RESERVED,Reserved" "0,1,2,3" newline bitfld.long 0x0 29. "WR_DATA_PIPELINE_EMPTY,This bit indicates that the write data pipeline on the DFI interface is empty. This register is intended to be polled at least twice after setting DBG1.dis_dq to ensure that all remaining commands/data have completed. Programming.." "0,1" newline bitfld.long 0x0 28. "RD_DATA_PIPELINE_EMPTY,This bit indicates that the read data pipeline on the DFI interface is empty. This register is intended to be polled at least twice after setting DBG1.dis_dq to ensure that all remaining commands/data have completed. Programming.." "0,1" newline bitfld.long 0x0 27. "RESERVED,Reserved" "0,1" newline bitfld.long 0x0 26. "DBG_WR_Q_EMPTY,When 1 all the Write command queues and Write data buffers inside DDRC are empty. This register is to be used for debug purpose. An example use-case scenario: When the controller enters self-refresh using the Low-Power entry sequence.." "0,1" newline bitfld.long 0x0 25. "DBG_RD_Q_EMPTY,When 1 all the Read command queues and Read data buffers inside DDRC are empty. This register is to be used for debug purpose. An example use-case scenario: When the controller enters self-refresh using the Low-Power entry sequence.." "0,1" newline bitfld.long 0x0 24. "DBG_STALL,Stall. FOR DEBUG ONLY. Programming Mode: Dynamic" "0,1" newline bitfld.long 0x0 22.--23. "RESERVED,Reserved" "0,1,2,3" newline hexmask.long.byte 0x0 16.--21. 1. "DBG_W_Q_DEPTH,This field indicates the Write queue depth. The last entry of WR queue is reserved for ECC SCRUB operation. This entry is not included in the calculation of the queue depth. FOR DEBUG ONLY Programming Mode: Dynamic" newline bitfld.long 0x0 14.--15. "RESERVED,Reserved" "0,1,2,3" newline hexmask.long.byte 0x0 8.--13. 1. "DBG_LPR_Q_DEPTH,This field indicates the low priority read queue depth. The last entry of Lpr queue is reserved for ECC SCRUB operation. This entry is not included in the calculation of the queue depth. FOR DEBUG ONLY Programming Mode: Dynamic" newline bitfld.long 0x0 6.--7. "RESERVED,Reserved" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "DBG_HPR_Q_DEPTH,This field indicates the high priority read queue depth. FOR DEBUG ONLY. Programming Mode: Dynamic" group.long 0x30C++0x3 line.long 0x0 "DBGCMD,Command Debug Register" hexmask.long 0x0 6.--31. 1. "RESERVED,Reserved" newline bitfld.long 0x0 5. "CTRLUPD,Setting this register bit to 1 indicates to the uMCTL2 to issue a dfi_ctrlupd_req to the PHY. When this request is stored in the uMCTL2 the bit is automatically cleared. This operation must only be performed when DFIUPD0.dis_auto_ctrlupd=1." "0,1" newline bitfld.long 0x0 4. "ZQ_CALIB_SHORT,Setting this register bit to 1 indicates to the uMCTL2 to issue a ZQCS (ZQ calibration short)/MPC(ZQ calibration) command to the SDRAM. When this request is stored in the uMCTL2 the bit is automatically cleared. This operation can be.." "0,1" newline rbitfld.long 0x0 2.--3. "RESERVED,Reserved" "0,1,2,3" newline bitfld.long 0x0 1. "RANK1_REFRESH,Setting this register bit to 1 indicates to the uMCTL2 to issue a refresh to rank 1. Writing to this bit causes DBGSTAT.rank1_refresh_busy to be set. When DBGSTAT.rank1_refresh_busy is cleared the command has been stored in uMCTL2. For 3DS.." "0,1" newline bitfld.long 0x0 0. "RANK0_REFRESH,Setting this register bit to 1 indicates to the uMCTL2 to issue a refresh to rank 0. Writing to this bit causes DBGSTAT.rank0_refresh_busy to be set. When DBGSTAT.rank0_refresh_busy is cleared the command has been stored in uMCTL2. For 3DS.." "0,1" rgroup.long 0x310++0x3 line.long 0x0 "DBGSTAT,Status Debug Register" hexmask.long 0x0 6.--31. 1. "RESERVED,Reserved" newline bitfld.long 0x0 5. "CTRLUPD_BUSY,SoC might initiate a ctrlupd operation only if this signal is low. This signal goes high in the clock after the uMCTL2 accepts the ctrlupd request. It goes low when the ctrlupd operation is initiated in the uMCTL2. It is recommended not to.." "Indicates that the SoC can initiate a ctrlupd..,Indicates that ctrlupd operation has not been.." newline bitfld.long 0x0 4. "ZQ_CALIB_SHORT_BUSY,SoC might initiate a ZQCS (ZQ calibration short) operation only if this signal is low. This signal goes high in the clock after the uMCTL2 accepts the ZQCS request. It goes low when the ZQCS operation is initiated in the uMCTL2. It is.." "Indicates that the SoC can initiate a ZQCS..,Indicates that ZQCS operation has not been.." newline bitfld.long 0x0 2.--3. "RESERVED,Reserved" "0,1,2,3" newline bitfld.long 0x0 1. "RANK1_REFRESH_BUSY,SoC might initiate a rank1_refresh operation (refresh operation to rank 1) only if this signal is low. This signal goes high in the clock after DBGCMD.rank1_refresh is set to one. It goes low when the rank1_refresh operation is stored.." "Indicates that the SoC can initiate a..,Indicates that rank1_refresh operation has not.." newline bitfld.long 0x0 0. "RANK0_REFRESH_BUSY,SoC might initiate a rank0_refresh operation (refresh operation to rank 0) only if this signal is low. This signal goes high in the clock after DBGCMD.rank0_refresh is set to one. It goes low when the rank0_refresh operation is stored.." "Indicates that the SoC can initiate a..,Indicates that rank0_refresh operation has not.." rgroup.long 0x318++0x3 line.long 0x0 "DBGCAM1,CAM Debug Register 1" hexmask.long 0x0 6.--31. 1. "RESERVED,Reserved" newline hexmask.long.byte 0x0 0.--5. 1. "DBG_WRECC_Q_DEPTH,This field indicates the write ECC queue depth. FOR DEBUG ONLY. Programming Mode: Dynamic" group.long 0x320++0x3 line.long 0x0 "SWCTL,Software Register Programming Control Enable" hexmask.long 0x0 1.--31. 1. "RESERVED,Reserved" newline bitfld.long 0x0 0. "SW_DONE,Enables quasi-dynamic register programming outside reset. Program this register to 0 to enable quasi-dynamic programming. Set back register to 1 once programming is done. Programming Mode: Dynamic" "0,1" rgroup.long 0x324++0x3 line.long 0x0 "SWSTAT,Software Register Programming Control Status" hexmask.long 0x0 1.--31. 1. "RESERVED,Reserved" newline bitfld.long 0x0 0. "SW_DONE_ACK,Register programming done. This register is the echo of SWCTL.sw_done. Wait for sw_done value 1 to propagate to sw_done_ack at the end of the programming sequence to ensure that the correct registers values are propagated to the destination.." "0,1" group.long 0x328++0x3 line.long 0x0 "SWCTLSTATIC,Static Registers Write Enable" hexmask.long 0x0 1.--31. 1. "RESERVED,Reserved" newline bitfld.long 0x0 0. "SW_STATIC_UNLOCK,Enables static register programming outside reset. Program this register to 1 to enable static register programming. Set register back to 0 once programming is done. Programming Mode: Dynamic" "0,1" group.long 0x330++0x7 line.long 0x0 "OCPARCFG0,On-Chip Parity Configuration Register 0" hexmask.long.byte 0x0 27.--31. 1. "RESERVED,Reserved" newline bitfld.long 0x0 26. "PAR_RADDR_ERR_INTR_FORCE,Interrupt force bit for all par_raddr_err_intr. uMCTL2 automatically clears this bit. Programming Mode: Dynamic" "0,1" newline bitfld.long 0x0 25. "PAR_WADDR_ERR_INTR_FORCE,Interrupt force bit for all par_waddr_err_intr. uMCTL2 automatically clears this bit. Programming Mode: Dynamic" "0,1" newline bitfld.long 0x0 24. "PAR_RADDR_ERR_INTR_CLR,Interrupt clear bit for all par_raddr_err_intr. uMCTL2 automatically clears this bit. Programming Mode: Dynamic" "0,1" newline bitfld.long 0x0 23. "PAR_RADDR_ERR_INTR_EN,Enables interrupt generation if set to 1 for all ports on signal par_raddr_err_intr_n upon detection of parity error on the AXI interface. Programming Mode: Dynamic" "0,1" newline bitfld.long 0x0 22. "PAR_WADDR_ERR_INTR_CLR,Interrupt clear bit for all par_waddr_err_intr. uMCTL2 automatically clears this bit. Programming Mode: Dynamic" "0,1" newline bitfld.long 0x0 21. "PAR_WADDR_ERR_INTR_EN,Enables interrupt generation if set to 1 for all ports on signal par_waddr_err_intr_n upon detection of parity error on the AXI interface. Programming Mode: Dynamic" "0,1" newline bitfld.long 0x0 20. "PAR_ADDR_SLVERR_EN,Enables SLVERR generation on read response or write response when address parity error is detected at the AXI interface. Programming Mode: Quasi-dynamic Group 3" "0,1" newline hexmask.long.byte 0x0 16.--19. 1. "RESERVED,Reserved" newline bitfld.long 0x0 15. "PAR_RDATA_ERR_INTR_FORCE,Interrupt force bit for all par_rdata_err_intr_n and par_rdata_in_err_ecc_intr (Inline-ECC only). uMCTL2 automatically clears this bit. Programming Mode: Dynamic" "0,1" newline bitfld.long 0x0 14. "PAR_RDATA_ERR_INTR_CLR,Interrupt clear bit for par_rdata_err_intr. uMCTL2 automatically clears this bit. Programming Mode: Dynamic" "0,1" newline bitfld.long 0x0 13. "PAR_RDATA_ERR_INTR_EN,Enables interrupt generation if set to 1 for all ports on signal par_rdata_err_intr_n upon detection of parity error at the AXI interface. Programming Mode: Dynamic" "0,1" newline bitfld.long 0x0 12. "PAR_RDATA_SLVERR_EN,Enables SLVERR generation on read response when read data parity error is detected at the AXI interface. Programming Mode: Quasi-dynamic Group 3" "0,1" newline hexmask.long.byte 0x0 8.--11. 1. "RESERVED,Reserved" newline bitfld.long 0x0 7. "PAR_WDATA_ERR_INTR_FORCE,Interrupt force bit for par_wdata_err_intr. uMCTL2 automatically clears this bit. Programming Mode: Dynamic" "0,1" newline bitfld.long 0x0 6. "PAR_WDATA_ERR_INTR_CLR,Interrupt clear bit for par_wdata_err_intr. uMCTL2 automatically clears this bit. Programming Mode: Dynamic" "0,1" newline bitfld.long 0x0 5. "PAR_WDATA_SLVERR_EN,Enables SLVERR generation on write response when write data parity error is detected at the AXI interface. Programming Mode: Quasi-dynamic Group 3" "0,1" newline bitfld.long 0x0 4. "PAR_WDATA_ERR_INTR_EN,Enables write data interrupt generation (par_wdata_err_intr) upon detection of parity error at the AXI or DFI interface. Programming Mode: Dynamic" "0,1" newline rbitfld.long 0x0 2.--3. "RESERVED,Reserved" "0,1,2,3" newline bitfld.long 0x0 1. "OC_PARITY_TYPE,Parity type: - 0 - Even parity - 1 - Odd parity Programming Mode: Quasi-dynamic Group 3" "Even parity,Odd parity" newline bitfld.long 0x0 0. "OC_PARITY_EN,Parity enable register. Enables On-Chip parity for all interfaces. Programming Mode: Quasi-dynamic Group 3" "0,1" line.long 0x4 "OCPARCFG1,On-Chip Parity Configuration Register 1" hexmask.long.tbyte 0x4 12.--31. 1. "RESERVED,Reserved" newline hexmask.long.byte 0x4 8.--11. 1. "PAR_POISON_LOC_WR_PORT,Enables parity poisoning on write data at the AXI interface before the input parity check logic. The value specifies the binary encoded port number of the AXI interface to be injected with parity error. Programming Mode:.." newline hexmask.long.byte 0x4 4.--7. 1. "PAR_POISON_LOC_RD_PORT,Enables parity poisoning on read data at the AXI interface after the parity check logic. The value specifies the binary encoded port number of the AXI interface to be injected with parity error. Error can be injected to one port at.." newline bitfld.long 0x4 3. "PAR_POISON_LOC_RD_IECC_TYPE,Selects which parity to poison at the DFI when inline ECC is enabled. If this register is set to 0 parity error is injected on the first read data going through the ECC path. If this register is set to 1 parity error is.." "0,1" newline bitfld.long 0x4 2. "PAR_POISON_LOC_RD_DFI,Enables parity poisoning on read data at the DFI interface after the parity generation logic. When MEMC_INLINE_ECC=1 enables poisoning of ECC word after the ECC encoder at the write data interface at the DFI. Programming Mode:.." "0,1" newline rbitfld.long 0x4 1. "RESERVED,Reserved" "0,1" newline bitfld.long 0x4 0. "PAR_POISON_EN,Enables on-chip parity poisoning on the data interfaces. Programming Mode: Quasi-dynamic Group 3" "0,1" repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) rgroup.long ($2+0x338)++0x3 line.long 0x0 "OCPARSTAT$1,On-Chip Parity Status Register 0" hexmask.long.word 0x0 17.--31. 1. "RESERVED,Reserved" newline bitfld.long 0x0 16. "PAR_RADDR_ERR_INTR_0,Read address parity error interrupt for port 0. This interrupt is asserted when an on-chip read address parity error occurred on the corresponding AXI port's read address channel. Programming Mode: Static" "0,1" newline hexmask.long.word 0x0 1.--15. 1. "RESERVED,Reserved" newline bitfld.long 0x0 0. "PAR_WADDR_ERR_INTR_0,Write address parity error interrupt for port 0. This interrupt is asserted when an on-chip write address parity error occurred on the corresponding AXI port's write address channel. Programming Mode: Static" "0,1" repeat.end rgroup.long 0x340++0x3 line.long 0x0 "OCPARSTAT2,On-Chip Parity Status Register 2" hexmask.long 0x0 5.--31. 1. "RESERVED,Reserved" newline bitfld.long 0x0 4. "PAR_RDATA_IN_ERR_ECC_INTR,Interrupt on ECC data going into inline ECC decoder. Cleared by par_rdata_err_intr_clr. Programming Mode: Static" "0,1" newline bitfld.long 0x0 2.--3. "RESERVED,Reserved" "0,1,2,3" newline bitfld.long 0x0 0.--1. "PAR_WDATA_OUT_ERR_INTR,Write data parity error interrupt on output. Cleared by register par_wdata_err_intr_clr. Programming Mode: Static" "0,1,2,3" group.long 0x36C++0x3 line.long 0x0 "POISONCFG,AXI Poison Configuration Register. Common for all AXI ports." hexmask.long.byte 0x0 25.--31. 1. "RESERVED,Reserved" newline bitfld.long 0x0 24. "RD_POISON_INTR_CLR,Interrupt clear for read transaction poisoning. Allow 2/3 clock cycles for correct value to propagate to controller logic and clear the interrupts. uMCTL2 automatically clears this bit. Programming Mode: Dynamic" "0,1" newline rbitfld.long 0x0 21.--23. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 20. "RD_POISON_INTR_EN,If set to 1 enables interrupts for read transaction poisoning. Programming Mode: Dynamic" "0,1" newline rbitfld.long 0x0 17.--19. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 16. "RD_POISON_SLVERR_EN,If set to 1 enables SLVERR response for read transaction poisoning. Programming Mode: Dynamic" "0,1" newline hexmask.long.byte 0x0 9.--15. 1. "RESERVED,Reserved" newline bitfld.long 0x0 8. "WR_POISON_INTR_CLR,Interrupt clear for write transaction poisoning. Allow 2/3 clock cycles for correct value to propagate to controller logic and clear the interrupts. uMCTL2 automatically clears this bit. Programming Mode: Dynamic" "0,1" newline rbitfld.long 0x0 5.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 4. "WR_POISON_INTR_EN,If set to 1 enables interrupts for write transaction poisoning. Programming Mode: Dynamic" "0,1" newline rbitfld.long 0x0 1.--3. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 0. "WR_POISON_SLVERR_EN,If set to 1 enables SLVERR response for write transaction poisoning. Programming Mode: Dynamic" "0,1" rgroup.long 0x370++0x3 line.long 0x0 "POISONSTAT,AXI Poison Status Register" hexmask.long.word 0x0 17.--31. 1. "RESERVED,Reserved" newline bitfld.long 0x0 16. "RD_POISON_INTR_0,Read transaction poisoning error interrupt for port 0. This register is a APB clock copy (double register synchronizer) of the interrupt asserted when a transaction is poisoned on the corresponding AXI port's read address channel. Bit 0.." "0,1" newline hexmask.long.word 0x0 1.--15. 1. "RESERVED,Reserved" newline bitfld.long 0x0 0. "WR_POISON_INTR_0,Write transaction poisoning error interrupt for port 0. This register is a APB clock copy (double register synchronizer) of the interrupt asserted when a transaction is poisoned on the corresponding AXI port's write address channel. Bit.." "0,1" group.long 0x374++0x3 line.long 0x0 "ADVECCINDEX,Advanced ECC Index Register" hexmask.long.tbyte 0x0 9.--31. 1. "RESERVED,Reserved" newline hexmask.long.byte 0x0 5.--8. 1. "ECC_POISON_BEATS_SEL,Selector of which DRAM beat's poison pattern is set by ECCPOISONPAT0/1/2 registers. For frequency ratio 1:1 mode 2 DRAM beats can be poisoned. Set ecc_poison_beats_sel to 0 and given ECCPOISONPAT0/1/2 to set 1st beat's poison.." newline bitfld.long 0x0 3.--4. "ECC_ERR_SYMBOL_SEL,Selector of which error symbol's status output to ADVECCSTAT.advecc_err_symbol_pos and advecc_err_symbol_bits. The default is first error symbol. The value must be less than ADVECCSTAT.advecc_num_err_symbol. Programming Mode:.." "0,1,2,3" newline bitfld.long 0x0 0.--2. "ECC_SYNDROME_SEL,Selector of which DRAM beat data output to ECCCSYN0/1/2 as well as ECCUCSYN. In Advanced ECC the syndrome consists of number of DRAM beats. This register selects which beats of data is output to ECCCSYN0/1/2 and ECCUCSYN0/1/2 registers." "0,1,2,3,4,5,6,7" group.long 0x37C++0x3 line.long 0x0 "ECCPOISONPAT0,ECC Poison Pattern 0 Register" hexmask.long 0x0 0.--31. 1. "ECC_POISON_DATA_31_0,Indicates the poison pattern for DRAM data[31:0]. setting this bit to 1 indicates poison (invert) corresponding DRAM bit. It is indirect register. Selector is ADVECCINDEX.ecc_poison_beats_sel. Programming Mode: Quasi-dynamic Group 3" group.long 0x384++0x3 line.long 0x0 "ECCPOISONPAT2,ECC Poison Pattern 2 Register" hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED,Reserved" newline hexmask.long.byte 0x0 0.--7. 1. "ECC_POISON_DATA_71_64,Indicates the poison pattern for DRAM data[71:64]. Setting this bit to 1 indicates poison (invert) corresponding DRAM bit. It is indirect register. Selector is ADVECCINDEX.ecc_poison_beats_sel. Programming Mode: Quasi-dynamic Group 3" rgroup.long 0x388++0x3 line.long 0x0 "ECCAPSTAT,Address protection within ECC Status Register" hexmask.long 0x0 1.--31. 1. "RESERVED,Reserved" newline bitfld.long 0x0 0. "ECC_AP_ERR,Indicates the number of ECC errors (correctable/uncorrectable) within one burst exceeded the threshold(ECCCFG0.ecc_ap_err_threshold). Programming Mode: Dynamic" "0,1" group.long 0x3C0++0x3 line.long 0x0 "REGPARCFG,Register Parity Configuration Register (Note that all fields must be programmed with single write operation)." hexmask.long.tbyte 0x0 9.--31. 1. "RESERVED,Reserved" newline bitfld.long 0x0 8. "REG_PAR_POISON_EN,Enable Register Parity poisoning. Programming Mode: Dynamic" "0,1" newline hexmask.long.byte 0x0 4.--7. 1. "RESERVED,Reserved" newline bitfld.long 0x0 3. "REG_PAR_ERR_INTR_FORCE,Interrupt force bit for reg_par_err_intr setting this register causes the output interrupt to be asserted. uMCTL2 automatically clears this bit. There is no interaction between functionally triggering an interrupt and forcing an.." "0,1" newline bitfld.long 0x0 2. "REG_PAR_ERR_INTR_CLR,Interupt clear bit for reg_par_err_intr. uMCTL2 automatically clears this bit. Programming Mode: Dynamic" "0,1" newline bitfld.long 0x0 1. "REG_PAR_ERR_INTR_EN,Enables interrupt generation if set to 1 on signal reg_par_err_intr upon detection of register parity error. Programming Mode: Dynamic" "0,1" newline bitfld.long 0x0 0. "REG_PAR_EN,Register Parity enable register. Programming Mode: Dynamic" "0,1" rgroup.long 0x3C4++0x3 line.long 0x0 "REGPARSTAT,Register Parity Status Register" hexmask.long 0x0 1.--31. 1. "RESERVED,Reserved" newline bitfld.long 0x0 0. "REG_PAR_ERR_INTR,Interrupt asserted when Register Parity error is detected. Cleared by setting REGPARCFG.reg_par_err_intr_clr to 1. Programming Mode: Static" "0,1" group.long 0x3E0++0x3 line.long 0x0 "OCCAPCFG,On-Chip command/Address Protection Configuration Register" hexmask.long.byte 0x0 28.--31. 1. "RESERVED,Reserved" newline bitfld.long 0x0 27. "OCCAP_ARB_RAQ_POISON_EN,Enables poisoning for the Read Address Queues (RAQ) inside each XPI. Poisoning inverts all parity bits generated by the parity generator. Error is flagged as soon as the first RAQ is read. This register is not cleared.." "0,1" newline bitfld.long 0x0 26. "OCCAP_ARB_CMP_POISON_ERR_INJ,Enables error injection in the poisoning of OCCAP Arbiter logic. Injects error into poisoning logic (either parallel or seq) such that XOR logic for one signal is not poisoned when expected. If set it allows ability to.." "OCCAPSTAT,OCCAPSTAT" newline bitfld.long 0x0 25. "OCCAP_ARB_CMP_POISON_PARALLEL,Enables full poisoning for compare logic inside XPI. Poisoning inverts all bits of all outputs coming from the duplicated modules before the XOR comparators together. uMCTL2 automatically clears this bit. Programming Mode:.." "0,1" newline bitfld.long 0x0 24. "OCCAP_ARB_CMP_POISON_SEQ,Enables poisoning for compare logic inside XPI. Poisoning inverts all bits coming from the duplicated modules before the XOR comparators one output at the time per each comparator. uMCTL2 automatically clears this bit." "0,1" newline hexmask.long.byte 0x0 19.--23. 1. "RESERVED,Reserved" newline bitfld.long 0x0 18. "OCCAP_ARB_INTR_FORCE,Interrupt force bit for occap_arb_err_intr setting this register causes the output interrupt to be asserted. uMCTL2 automatically clears this bit. There is no interaction between functionally triggering an interrupt and forcing an.." "0,1" newline bitfld.long 0x0 17. "OCCAP_ARB_INTR_CLR,Interrupt clear bit for occap_arb_err_intr and occap_arb_cmp_poison_complete. uMCTL2 automatically clears this bit. Programming Mode: Dynamic" "0,1" newline bitfld.long 0x0 16. "OCCAP_ARB_INTR_EN,Enables interrupt generation upon detection of OCCAP Arbiter errors. Programming Mode: Dynamic" "0,1" newline hexmask.long.word 0x0 1.--15. 1. "RESERVED,Reserved" newline bitfld.long 0x0 0. "OCCAP_EN,On Chip Command/Address Path Protection (OCCAP) enable register. Programming Mode: Quasi-dynamic Group 3" "0,1" rgroup.long 0x3E4++0x3 line.long 0x0 "OCCAPSTAT,On-Chip command/Address Protection Status Register" hexmask.long.byte 0x0 26.--31. 1. "RESERVED,Reserved" newline bitfld.long 0x0 25. "OCCAP_ARB_CMP_POISON_PARALLEL_ERR,Error when occap_arb_cmp_poison_full_en is active due to incorrect number of errors being occurring. Internal logic checks the number of errors detected while poisoning occurred for occap_arb_cmp_poison_full_en. It.." "0,1" newline bitfld.long 0x0 24. "OCCAP_ARB_CMP_POISON_SEQ_ERR,Error when occap_arb_cmp_poison_en is active due to incorrect number of errors being occurring. Internal logic checks that the correct number of errors detected while poisoning one output at the time occurred for.." "0,1" newline hexmask.long.byte 0x0 18.--23. 1. "RESERVED,Reserved" newline bitfld.long 0x0 17. "OCCAP_ARB_CMP_POISON_COMPLETE,OCCAP ARB comparator poisoning complete interrupt status. Register cleared by OCCAPCFG.occap_arb_intr_clr. Programming Mode: Static" "0,1" newline bitfld.long 0x0 16. "OCCAP_ARB_ERR_INTR,OCCAP Arbiter error interrupt status. Register cleared by OCCAPCFG.occap_arb_intr_clr. Programming Mode: Static" "0,1" newline hexmask.long.word 0x0 0.--15. 1. "RESERVED,Reserved" group.long 0x3E8++0x3 line.long 0x0 "OCCAPCFG1,On-Chip command/Address Protection Configuration Register 1" hexmask.long.byte 0x0 27.--31. 1. "RESERVED,Reserved" newline bitfld.long 0x0 26. "OCCAP_DDRC_CTRL_POISON_ERR_INJ,Enables error injection in the poisoning of OCCAP DDRC CTRL logic. Injects error into poisoning logic (either parallel or seq) such that XOR logic for one signal is not poisoned when expected. If set it allows ability to.." "OCCAPSTAT1,OCCAPSTAT1" newline bitfld.long 0x0 25. "OCCAP_DDRC_CTRL_POISON_PARALLEL,Enables poisoning of OCCAP DDRC CTRL logic for all parts of comparison logic in parallel. Poisons comparison logic for one core_ddrc_core_clk cycle by inverting a ddrc_ctrl[0]'s signal to XOR logic. ddrc_ctrl[1] related.." "0,1" newline bitfld.long 0x0 24. "OCCAP_DDRC_CTRL_POISON_SEQ,Enables poisoning of OCCAP DDRC CTRL logic for all parts of comparison logic in sequence. Poisons comparison logic for one core_ddrc_core_clk cycle by inverting a ddrc_ctrl[0]'s signal to XOR logic. ddrc_ctrl[1] related.." "0,1" newline hexmask.long.byte 0x0 19.--23. 1. "RESERVED,Reserved" newline bitfld.long 0x0 18. "OCCAP_DDRC_CTRL_INTR_FORCE,Interrupt force bit for occap_ddrc_ctrl_err_intr setting this register causes the output interrupt to be asserted. uMCTL2 automatically clears this bit. There is no interaction between functionally triggering an interrupt and.." "0,1" newline bitfld.long 0x0 17. "OCCAP_DDRC_CTRL_INTR_CLR,Interrupt clear bit for occap_ddrc_ctrl_err_intr. uMCTL2 automatically clears this bit. Programming Mode: Dynamic" "0,1" newline bitfld.long 0x0 16. "OCCAP_DDRC_CTRL_INTR_EN,Enables interrupt generation on signal occap_ddrc_ctrl_err_intr upon detection of OCCAP DDRC CTRL errors. Programming Mode: Dynamic" "0,1" newline hexmask.long.byte 0x0 11.--15. 1. "RESERVED,Reserved" newline bitfld.long 0x0 10. "OCCAP_DDRC_DATA_POISON_ERR_INJ,Enables error injection in the poisoning of OCCAP DDRC DATA logic. Injects error into poisoning logic (either parallel or seq) such that XOR logic for one signal is not poisoned when expected. If set it allows ability to.." "OCCAPSTAT1,OCCAPSTAT1" newline bitfld.long 0x0 9. "OCCAP_DDRC_DATA_POISON_PARALLEL,Enables poisoning of OCCAP DDRC DATA logic for all parts of comparison logic in parallel. Poisons comparison logic for one core_ddrc_core_clk cycle by inverting all bits of a signal to XOR logic. All signals of.." "0,1" newline bitfld.long 0x0 8. "OCCAP_DDRC_DATA_POISON_SEQ,Enables poisoning of OCCAP DDRC DATA logic for all parts of comparison logic in sequence. Poisons comparison logic for one core_ddrc_core_clk cycle by inverting all bits of a signal to XOR logic. All signals of instance[0] of.." "0,1" newline hexmask.long.byte 0x0 3.--7. 1. "RESERVED,Reserved" newline bitfld.long 0x0 2. "OCCAP_DDRC_DATA_INTR_FORCE,Interrupt force bit for occap_ddrc_data_err_intr setting this register causes the output interrupt to be asserted. uMCTL2 automatically clears this bit. There is no interaction between functionally triggering an interrupt and.." "0,1" newline bitfld.long 0x0 1. "OCCAP_DDRC_DATA_INTR_CLR,Interrupt clear bit for occap_ddrc_data_err_intr. uMCTL2 automatically clears this bit. Programming Mode: Dynamic" "0,1" newline bitfld.long 0x0 0. "OCCAP_DDRC_DATA_INTR_EN,Enables interrupt generation on signal occap_ddrc_data_err_intr upon detection of OCCAP DDRC DATA errors. Programming Mode: Dynamic" "0,1" rgroup.long 0x3EC++0x7 line.long 0x0 "OCCAPSTAT1,On-Chip command/Address Protection Status Register 1" hexmask.long.byte 0x0 26.--31. 1. "RESERVED,Reserved" newline bitfld.long 0x0 25. "OCCAP_DDRC_CTRL_POISON_PARALLEL_ERR,Error when occap_ddrc_ctrl_poison_parallel is active due to incorrect number of errors being occurring. Internal logic checks the number of errors detected while poisoning occurred for occap_ddrc_ctrl_poison_parallel." "0,1" newline bitfld.long 0x0 24. "OCCAP_DDRC_CTRL_POISON_SEQ_ERR,Error when occap_ddrc_ctrl_poison_seq is active due to incorrect number of errors being occurring. Internal logic checks the number of errors detected while poisoning occurred for occap_ddrc_ctrl_poison_seq. It checks for.." "0,1" newline hexmask.long.byte 0x0 18.--23. 1. "RESERVED,Reserved" newline bitfld.long 0x0 17. "OCCAP_DDRC_CTRL_POISON_COMPLETE,Indicates the OCCAP DDRC CTRL poisoning complete interrupt status. Register cleared by OCCAPCFG1.occap_ddrc_ctrl_err_intr_clr. Programming Mode: Static" "0,1" newline bitfld.long 0x0 16. "OCCAP_DDRC_CTRL_ERR_INTR,Indicates the OCCAP DDRC CTRL error interrupt status. Register cleared by OCCAPCFG1.occap_ddrc_ctrl_err_intr_clr. Programming Mode: Static" "0,1" newline hexmask.long.byte 0x0 10.--15. 1. "RESERVED,Reserved" newline bitfld.long 0x0 9. "OCCAP_DDRC_DATA_POISON_PARALLEL_ERR,Error when occap_ddrc_data_poison_parallel is active due to incorrect number of errors being occurring. Internal logic checks the number of errors detected while poisoning occurred for occap_ddrc_data_poison_parallel." "0,1" newline bitfld.long 0x0 8. "OCCAP_DDRC_DATA_POISON_SEQ_ERR,Error when occap_ddrc_data_poison_seq is active due to incorrect number of errors being occurring. Internal logic checks the number of errors detected while poisoning occurred for occap_ddrc_data_poison_seq. It checks for.." "0,1" newline hexmask.long.byte 0x0 2.--7. 1. "RESERVED,Reserved" newline bitfld.long 0x0 1. "OCCAP_DDRC_DATA_POISON_COMPLETE,Indicates the OCCAP DDRC DATA poisoning complete interrupt status. Register cleared by OCCAPCFG1.occap_ddrc_data_err_intr_clr. Programming Mode: Static" "0,1" newline bitfld.long 0x0 0. "OCCAP_DDRC_DATA_ERR_INTR,Indicates the OCCAP DDRC DATA error interrupt status. Register cleared by OCCAPCFG1.occap_ddrc_data_err_intr_clr. Programming Mode: Static" "0,1" line.long 0x4 "DERATESTAT,Temperature Derate Status Register" hexmask.long 0x4 1.--31. 1. "RESERVED,Reserved" newline bitfld.long 0x4 0. "DERATE_TEMP_LIMIT_INTR,Derate temperature interrupt indicating LPDDR2/3/4 SDRAM temperature operating limit is exceeded. This register field is set to 1 when the value read from MR4[2:0] is 3'b000 or 3'b111. Cleared by register.." "0,1" tree.end tree "UMCTL2_MP (uMCTL2 Multi-Port Registers)" base ad:0x1016 rgroup.long 0x4++0x3 line.long 0x0 "PSTAT,Port Status Register" bitfld.long 0x0 16. "WR_PORT_BUSY_0,Indicates if there are outstanding writes for AXI port 0. Programming Mode: Dynamic" "0,1" bitfld.long 0x0 0. "RD_PORT_BUSY_0,Indicates if there are outstanding reads for AXI port 0. Programming Mode: Dynamic" "0,1" group.long 0x8++0xB line.long 0x0 "PCCFG,Port Common Configuration Register" bitfld.long 0x0 8. "BL_EXP_MODE,Burst length expansion mode. By default (that is bl_exp_mode==0) XPI expands every AXI burst into multiple HIF commands using the memory burst length as a unit. If set to 1 then XPI uses half of the memory burst length as a unit. This.." "UMCTL2_PARTIAL_WR=1,?" bitfld.long 0x0 4. "PAGEMATCH_LIMIT,Page match four limit. If set to 1 limits the number of consecutive same page DDRC transactions that can be granted by the Port Arbiter to four when Page Match feature is enabled. If set to 0 there is no limit imposed on number of.." "0,1" bitfld.long 0x0 0. "GO2CRITICAL_EN,If set to 1 (enabled) sets co_gs_go2critical_wr and co_gs_go2critical_lpr/co_gs_go2critical_hpr signals going to DDRC based on urgent input (awurgent arurgent) coming from AXI master. If set to 0 (disabled) co_gs_go2critical_wr and.." "0,1" line.long 0x4 "PCFGR_0,Port n Configuration Read Register" bitfld.long 0x4 16. "RDWR_ORDERED_EN,Enables ordered read/writes. If set to 1 preserves the ordering between read transaction and write transaction issued to the same address on a given port. In other words the controller ensures that all same address read and write.." "0,1" bitfld.long 0x4 14. "RD_PORT_PAGEMATCH_EN,If set to 1 enables the Page Match feature. If enabled once a requesting port is granted the port is continued to be granted if the following immediate commands are to the same memory page (same rank same bank and same row). See.." "0,1" bitfld.long 0x4 13. "RD_PORT_URGENT_EN,If set to 1 enables the AXI urgent sideband signal (arurgent). When enabled and arurgent is asserted by the master that port becomes the highest priority and co_gs_go2critical_lpr/co_gs_go2critical_hpr signal to DDRC is asserted if.." "0,1" newline bitfld.long 0x4 12. "RD_PORT_AGING_EN,If set to 1 enables aging function for the read channel of the port. Programming Mode: Static" "0,1" hexmask.long.word 0x4 0.--9. 1. "RD_PORT_PRIORITY,Determines the initial load value of read aging counters. These counters are parallel loaded after reset or after each grant to the corresponding port. The aging counters down-count every clock cycle where the port is requesting but not.." line.long 0x8 "PCFGW_0,Port n Configuration Write Register" bitfld.long 0x8 14. "WR_PORT_PAGEMATCH_EN,If set to 1 enables the Page Match feature. If enabled once a requesting port is granted the port is continued to be granted if the following immediate commands are to the same memory page (same rank same bank and same row). See.." "0,1" bitfld.long 0x8 13. "WR_PORT_URGENT_EN,If set to 1 enables the AXI urgent sideband signal (awurgent). When enabled and awurgent is asserted by the master that port becomes the highest priority and co_gs_go2critical_wr signal to DDRC is asserted if enabled in.." "0,1" bitfld.long 0x8 12. "WR_PORT_AGING_EN,If set to 1 enables aging function for the write channel of the port. Programming Mode: Static" "0,1" newline hexmask.long.word 0x8 0.--9. 1. "WR_PORT_PRIORITY,Determines the initial load value of write aging counters. These counters are parallel loaded after reset or after each grant to the corresponding port. The aging counters down-count every clock cycle where the port is requesting but.." group.long 0x98++0x13 line.long 0x0 "PCTRL_0,Port n Control Register" bitfld.long 0x0 0. "PORT_EN,Enables AXI port n. Programming Mode: Dynamic" "0,1" line.long 0x4 "PCFGQOS0_0,Port n Read QoS Configuration Register 0" bitfld.long 0x4 24.--25. "RQOS_MAP_REGION2,This bitfield indicates the traffic class of region2. For dual address queue configurations region2 maps to the red address queue. Valid values are 1: VPR and 2: HPR only. When VPR support is disabled (UMCTL2_VPR_EN = 0) and traffic.." "?,VPR and,HPR only,?" bitfld.long 0x4 20.--21. "RQOS_MAP_REGION1,This bit field indicates the traffic class of region 1. Valid values are: - 0 - LPR - 1 - VPR - 2 - HPR For dual address queue configurations region1 maps to the blue address queue. In this case valid values are - 0 - LPR - 1 - VPR.." "LPR,VPR only,HPR,?" bitfld.long 0x4 16.--17. "RQOS_MAP_REGION0,This bit field indicates the traffic class of region 0. Valid values are: - 0 - LPR - 1 - VPR - 2 - HPR For dual address queue configurations region 0 maps to the blue address queue. In this case valid values are: 0: LPR and 1: VPR.." "LPR and,VPR only,HPR,?" newline hexmask.long.byte 0x4 8.--11. 1. "RQOS_MAP_LEVEL2,Separation level2 indicating the end of region1 mapping; start of region1 is (level1 + 1). Possible values for level2 are (level1 + 1) to 14 which corresponds to arqos. Region2 starts from (level2 + 1) up to 15. Note that for PA arqos.." hexmask.long.byte 0x4 0.--3. 1. "RQOS_MAP_LEVEL1,Separation level1 indicating the end of region0 mapping; start of region0 is 0. Possible values for level1 are 0 to 13 (for dual RAQ) or 0 to 14 (for single RAQ) which corresponds to arqos. Note that for PA arqos values are used directly.." line.long 0x8 "PCFGQOS1_0,Port n Read QoS Configuration Register 1" hexmask.long.word 0x8 16.--26. 1. "RQOS_MAP_TIMEOUTR,Specifies the timeout value for transactions mapped to the red address queue. Programming Mode: Quasi-dynamic Group 3" hexmask.long.word 0x8 0.--10. 1. "RQOS_MAP_TIMEOUTB,Specifies the timeout value for transactions mapped to the blue address queue. Programming Mode: Quasi-dynamic Group 3" line.long 0xC "PCFGWQOS0_0,Port n Write QoS Configuration Register 0" bitfld.long 0xC 24.--25. "WQOS_MAP_REGION2,This bit field indicates the traffic class of region 2. Valid values are: - 0 - NPW - 1 - VPW When VPW support is disabled (UMCTL2_VPW_EN = 0) and traffic class of region 2 is set to 1 (VPW) VPW traffic is aliased to NPW traffic." "NPW,VPW,?,?" bitfld.long 0xC 20.--21. "WQOS_MAP_REGION1,This bit field indicates the traffic class of region 1. Valid values are: 0: NPW 1: VPW. When VPW support is disabled (UMCTL2_VPW_EN = 0) and traffic class of region 1 is set to 1 (VPW) VPW traffic is aliased to NPW traffic." "NPW,VPW,?,?" bitfld.long 0xC 16.--17. "WQOS_MAP_REGION0,This bit field indicates the traffic class of region 0. Valid values are: - 0 - NPW - 1 - VPW When VPW support is disabled (UMCTL2_VPW_EN = 0) and traffic class of region 0 is set to 1 (VPW) VPW traffic is aliased to NPW traffic." "NPW,VPW,?,?" newline hexmask.long.byte 0xC 8.--11. 1. "WQOS_MAP_LEVEL2,Separation level2 indicating the end of region1 mapping; start of region1 is (level1 + 1). Possible values for level2 are (level1 + 1) to 14 which corresponds to awqos. Region2 starts from (level2 + 1) up to 15. Note that for PA awqos.." hexmask.long.byte 0xC 0.--3. 1. "WQOS_MAP_LEVEL1,Separation level indicating the end of region0 mapping; start of region0 is 0. Possible values for level1 are 0 to 13 which corresponds to awqos. Note that for PA awqos values are used directly as port priorities where the higher the.." line.long 0x10 "PCFGWQOS1_0,Port n Write QoS Configuration Register 1" hexmask.long.word 0x10 16.--26. 1. "WQOS_MAP_TIMEOUT2,Specifies the timeout value for write transactions in region 2. Programming Mode: Quasi-dynamic Group 3" hexmask.long.word 0x10 0.--10. 1. "WQOS_MAP_TIMEOUT1,Specifies the timeout value for write transactions in region 0 and 1. Programming Mode: Quasi-dynamic Group 3" repeat 4. (list 0x0 0x1 0x2 0x3 )(list 0x0 0x8 0x10 0x18 ) group.long ($2+0xB0C)++0x3 line.long 0x0 "SARBASE$1,SAR Base Address Register n" hexmask.long.word 0x0 0.--11. 1. "BASE_ADDR,Base address for address region n specified as awaddr[UMCTL2_A_ADDRW-1:x] and araddr[UMCTL2_A_ADDRW-1:x] where x is determined by the minimum block size parameter UMCTL2_SARMINSIZE: (x=log2(block size)). Programming Mode: Static" repeat.end repeat 4. (list 0x0 0x1 0x2 0x3 )(list 0x0 0x8 0x10 0x18 ) group.long ($2+0xB10)++0x3 line.long 0x0 "SARSIZE$1,SAR Size Register n" hexmask.long.byte 0x0 0.--7. 1. "NBLOCKS,Number of blocks for address region n. This register determines the total size of the region in multiples of minimum block size as specified by the hardware parameter UMCTL2_SARMINSIZE. The register value is encoded as number of blocks = nblocks.." repeat.end group.long 0xB2C++0x3 line.long 0x0 "SBRCTL,Scrubber Control Register" hexmask.long.word 0x0 8.--20. 1. "SCRUB_INTERVAL,Scrub interval. (512 x scrub_interval) number of clock cycles between two scrub read commands. If set to 0 scrub commands are issued back-to-back. This mode of operation (scrub_interval=0) can typically be used for scrubbing the full.." bitfld.long 0x0 4.--6. "SCRUB_BURST,Scrub burst count. Determines the number of back-to-back scrub read commands that can be issued together when the controller is in one of the HW controlled low power modes with Sideband ECC both normal operation mode and low-power mode with.." "0,1,2,3,4,5,6,7" bitfld.long 0x0 2. "SCRUB_MODE,- scrub_mode:0 ECC scrubber performs reads - scrub_mode:1 ECC scrubber performs writes Programming Mode: Dynamic" "0,1" newline bitfld.long 0x0 1. "SCRUB_DURING_LOWPOWER,Continue scrubbing during low power. If set to 1 burst of scrubs is issued in hardware controlled low power modes. There are two such modes: automatically initiated by idleness or initiated by Hardware low power interface. If set.." "0,1" bitfld.long 0x0 0. "SCRUB_EN,Enables ECC scrubber. If set to 1 enables the scrubber to generate background read commands after the memories are initialized. If set to 0 disables the scrubber resets the address generator to 0 and clears the scrubber status. This bitfield.." "0,1" rgroup.long 0xB30++0x3 line.long 0x0 "SBRSTAT,Scrubber Status Register" bitfld.long 0x0 1. "SCRUB_DONE,Scrubber done. The controller sets this bit to 1 after full range of addresses are scrubbed once while scrub_interval is set to 0. Cleared if scrub_en is set to 0 (scrubber disabled) or scrub_interval is set to a non-zero value for normal.." "0,1" bitfld.long 0x0 0. "SCRUB_BUSY,Scrubber busy. The controller sets this bit to 1 when the scrubber logic has outstanding read commands being executed. Cleared when there are no active outstanding scrub reads in the system. Programming Mode: Dynamic" "0,1" group.long 0xB34++0x3 line.long 0x0 "SBRWDATA0,Scrubber Write Data Pattern0" hexmask.long 0x0 0.--31. 1. "SCRUB_PATTERN0,ECC Scrubber write data pattern for data bus[31:0] Programming Mode: Dynamic" group.long 0xB40++0xF line.long 0x0 "SBRSTART0,Scrubber Start Address Mask Register 0" hexmask.long 0x0 0.--31. 1. "SBR_ADDRESS_START_MASK_0,sbr_address_start_mask_0 holds the bits [31:0] of the starting address the ECC scrubber generates. The register must be programmed as explained in Address Configuration in ECC Scrub and Scrubber. The scrubber address registers.." line.long 0x4 "SBRSTART1,Scrubber Start Address Mask Register 1" hexmask.long.byte 0x4 0.--3. 1. "SBR_ADDRESS_START_MASK_1,sbr_address_start_mask_1 holds bits [MEMC_HIF_ADDR_WIDTH_MAX-1:32] of the starting address the ECC scrubber generates.The register must be programmed as explained in Address Configuration in ECC Scrub and Scrubber. The scrubber.." line.long 0x8 "SBRRANGE0,Scrubber Address Range Mask Register 0" hexmask.long 0x8 0.--31. 1. "SBR_ADDRESS_RANGE_MASK_0,sbr_address_range_mask_0 holds the bits [31:0] of the scrubber address range mask. The scrubber address range mask limits the address range that the ECC scrubber can generate.The register must be programmed as explained in.." line.long 0xC "SBRRANGE1,Scrubber Address Range Mask Register 1" hexmask.long.byte 0xC 0.--3. 1. "SBR_ADDRESS_RANGE_MASK_1,sbr_address_range_mask_1 holds the bits [MEMC_HIF_ADDR_WIDTH_MAX-1:32] of the scrubber address range mask. The scrubber address range mask limits the address range that the ECC scrubber can generate.The register must be.." rgroup.long 0xBF8++0x7 line.long 0x0 "UMCTL2_VER_NUMBER,UMCTL2 Version Number Register" hexmask.long 0x0 0.--31. 1. "VER_NUMBER,Indicates the Device Version Number value. Programming Mode: Static" line.long 0x4 "UMCTL2_VER_TYPE,UMCTL2 Version Type Register" hexmask.long 0x4 0.--31. 1. "VER_TYPE,Indicates the Device Version Type value. Programming Mode: Static" tree.end tree "UMCTL2_REGS_FREQ1 (uMCTL2 DDRC FREQ1 Registers)" base ad:0x8192 group.long 0x20++0x7 line.long 0x0 "DERATEEN,[FREQ1] Temperature Derate Enable Register" bitfld.long 0x0 12. "DERATE_MR4_TUF_DIS,Disables use of MR4 TUF flag (MR4[7]) bit. - 0 - Use MR4 TUF flag (MR4[7]) - 1 - Do not use MR4 TUF Flag (MR4[7]) For LPDDR4 it is recommended to set this register to 1. For LPDDR2 and LPDDR3 contact your memory vendor for.." "Use MR4 TUF flag,Do not use MR4 TUF Flag" newline bitfld.long 0x0 8.--10. "RC_DERATE_VALUE,Derate value of tRC for LPDDR4. - 0 - Derating uses +1 - 1 - Derating uses +2 - 2 - Derating uses +3 - 3 - Derating uses +4 Present only in designs configured to support LPDDR4. The required cycles for derating can be determined by.." "Derating uses +1,Derating uses +2,Derating uses +3,Derating uses +4,?,?,?,?" newline hexmask.long.byte 0x0 4.--7. 1. "DERATE_BYTE,This bit indicates which byte of the MRR data is used for derating. The maximum valid value depends on MEMC_DRAM_TOTAL_DATA_WIDTH. Present only in designs configured to support LPDDR2/LPDDR3/LPDDR4. Programming Mode: Static" newline bitfld.long 0x0 1.--2. "DERATE_VALUE,Derate value. - 0 - Derating uses +1 - 1 - Derating uses +2 Present only in designs configured to support LPDDR2/LPDDR3/LPDDR4. Set to 0 for all LPDDR2 speed grades as derating value of +1.875 ns is less than a core_ddrc_core_clk period. For.." "Derating uses +1,Derating uses +2,?,?" newline bitfld.long 0x0 0. "DERATE_ENABLE,Enables derating. - 0 - Timing parameter derating is disabled - 1 - Timing parameter derating is enabled using MR4 read value Present only in designs configured to support LPDDR2/LPDDR3/LPDDR4. This field must be set to '0' for.." "Timing parameter derating is disabled,Timing parameter derating is enabled using MR4.." line.long 0x4 "DERATEINT,[FREQ1] Temperature Derate Interval Register" hexmask.long 0x4 0.--31. 1. "MR4_READ_INTERVAL,Interval between two MR4 reads used to derate the timing parameters. Present only in designs configured to support LPDDR2/LPDDR3/LPDDR4. This register must not be set to zero. Unit: DFI clock cycles. Programming Mode: Static" group.long 0x34++0x3 line.long 0x0 "PWRTMG,[FREQ1] Low Power Timing Register" hexmask.long.byte 0x0 16.--23. 1. "SELFREF_TO_X32,After this many clocks of the DDRC command channel being idle the uMCTL2 automatically puts the SDRAM into self-refresh. The DDRC command channel is considered idle when there are no HIF commands outstanding. This must be enabled in the.." newline hexmask.long.byte 0x0 8.--15. 1. "T_DPD_X4096,Minimum deep power-down time. For mDDR value from the JEDEC specification is 0 as mDDR exits from deep power-down mode immediately after PWRCTL.deeppowerdown_en is de-asserted. For LPDDR2/LPDDR3 value from the JEDEC specification is 500us." newline hexmask.long.byte 0x0 0.--4. 1. "POWERDOWN_TO_X32,After this many clocks of the DDRC command channel being idle the uMCTL2 automatically puts the SDRAM into power-down. The DDRC command channel is considered idle when there are no HIF commands outstanding. This must be enabled in the.." group.long 0x50++0x3 line.long 0x0 "RFSHCTL0,[FREQ1] Refresh Control Register 0" hexmask.long.byte 0x0 20.--23. 1. "REFRESH_MARGIN,Threshold value in number of DFI clock cycles before the critical refresh or page timer expires. A critical refresh is to be issued before this threshold is reached. It is recommended that this not be changed from the default value.." newline hexmask.long.byte 0x0 12.--16. 1. "REFRESH_TO_X1_X32,If the refresh timer (tRFCnom also known as tREFI) has expired at least once then a speculative refresh may be performed. A speculative refresh is a refresh performed at a time when refresh would be useful. When the SDRAM bus is idle.." newline hexmask.long.byte 0x0 4.--9. 1. "REFRESH_BURST,The programmed value + 1 is the number of refresh timeouts that is allowed to accumulate before traffic is blocked and the refreshes are forced to execute. Closing pages to perform a refresh is a one-time penalty that must be paid for each.." newline bitfld.long 0x0 2. "PER_BANK_REFRESH,- 1 - Per bank refresh - 0 - All bank refresh Per bank refresh allows traffic to flow to other banks. Per bank refresh is not supported by all LPDDR2 devices but must be supported by all LPDDR3/LPDDR4 devices. Present only in designs.." "All bank refresh,Per bank refresh" group.long 0x64++0x7 line.long 0x0 "RFSHTMG,[FREQ1] Refresh Timing Register" bitfld.long 0x0 31. "T_RFC_NOM_X1_SEL,Specifies whether the RFSHTMG.t_rfc_nom_x1_x32 and RFSHCTL0.refresh_to_x1_x32 register values are x1 or x32. - 0 - x32 register values are used - 1 - x1 register values are used This applies only when per-bank refresh is enabled.." "x32 register values are used,x1 register values are used" newline hexmask.long.word 0x0 16.--27. 1. "T_RFC_NOM_X1_X32,Average time interval between refreshes per rank (Specification: 7.8us for DDR2 DDR3 and DDR4. See JEDEC specification for mDDR LPDDR2 LPDDR3 and LPDDR4). When the controller is operating in 1:1 mode set this register to.." newline bitfld.long 0x0 15. "LPDDR3_TREFBW_EN,Used only when LPDDR3 memory type is connected. Should only be changed when uMCTL2 is in reset. Specifies whether to use the tREFBW parameter (required by some LPDDR3 devices which comply with earlier versions of the LPDDR3 JEDEC.." "tREFBW parameter not used,tREFBW parameter used" newline hexmask.long.word 0x0 0.--9. 1. "T_RFC_MIN,tRFC (min): Minimum time from refresh to refresh or activate. When the controller is operating in 1:1 mode t_rfc_min must be set to RoundUp(tRFCmin/tCK). When the controller is operating in 1:2 mode t_rfc_min must be set to.." line.long 0x4 "RFSHTMG1,[FREQ1] Refresh Timing Register1" hexmask.long.byte 0x4 16.--23. 1. "T_PBR2PBR,LPDDR4:tpbR2pbR. Per-bank refresh to Per-bank refresh different bank Time. When the controller is operating in 1:1 frequency ratio mode program this to RoundUp(tpbR2pbR/tCK). When the controller is operating in 1:2 frequency ratio mode.." repeat 4. (list 0x3 0x4 0x6 0x7 )(list 0x0 0x4 0xC 0x10 ) group.long ($2+0xDC)++0x3 line.long 0x0 "INIT$1,[FREQ1] SDRAM Initialization Register 3" hexmask.long.word 0x0 16.--31. 1. "MR,DDR2:Indicates the value to write to MR register. Bit 8 is for DLL and the setting here is ignored. The uMCTL2 sets this bit appropriately. DDR3/DDR4: Value loaded into MR0 register. mDDR: Value to write to MR register. LPDDR2/LPDDR3/LPDDR4 - Value to.." newline hexmask.long.word 0x0 0.--15. 1. "EMR,DDR2: Indicates the value to write to EMR register. Bits 9:7 are for OCD and the setting in this register is ignored. The uMCTL2 sets those bits appropriately. DDR3/DDR4: Value to write to MR1 register Set bit 7 to 0. mDDR: Value to write to EMR.." repeat.end group.long 0xF4++0x3 line.long 0x0 "RANKCTL,[FREQ1] Rank Control Register" bitfld.long 0x0 26. "DIFF_RANK_WR_GAP_MSB,Only present for multi-rank configurations. 1-bit extension to be used when RANKCTL.diff_rank_wr_gap field needs to be set to a value greater than 0xF. Programming Mode: Quasi-dynamic Group 2" "?,bit extension to be used when RANKCTL" newline bitfld.long 0x0 24. "DIFF_RANK_RD_GAP_MSB,Only present for multi-rank configurations. 1-bit extension to be used when RANKCTL.diff_rank_rd_gap field needs to be set to a value greater than 0xF. Programming Mode: Quasi-dynamic Group 2" "?,bit extension to be used when RANKCTL" newline hexmask.long.byte 0x0 12.--15. 1. "MAX_RANK_WR,Only present for multi-rank configurations. Background: Writes to the same rank can be performed back-to-back. Writes to different ranks require additional gap dictated by the register RANKCTL.diff_rank_wr_gap. This is to avoid possible data.." newline hexmask.long.byte 0x0 8.--11. 1. "DIFF_RANK_WR_GAP,Only present for multi-rank configurations. Indicates the number of clocks of gap in data responses when performing consecutive writes to different ranks. This is used to switch the delays in the PHY to match the rank requirements. This.." newline hexmask.long.byte 0x0 4.--7. 1. "DIFF_RANK_RD_GAP,Only present for multi-rank configurations. Indicates the number of clocks of gap in data responses when performing consecutive reads to different ranks. This is used to switch the delays in the PHY to match the rank requirements. This.." newline hexmask.long.byte 0x0 0.--3. 1. "MAX_RANK_RD,Only present for multi-rank configurations. Background: Reads to the same rank can be performed back-to-back. Reads to different ranks require additional gap dictated by the register RANKCTL.diff_rank_rd_gap. This is to avoid possible data.." group.long 0x100++0x3F line.long 0x0 "DRAMTMG0,[FREQ1] SDRAM Timing Register 0" hexmask.long.byte 0x0 24.--30. 1. "WR2PRE,Specifies the minimum time between write and precharge to same bank. Specifications: WL + BL/2 + tWR = approximately 8 cycles + 15 ns = 14 clocks @400MHz and less for lower frequencies. where: - WL - Write latency - BL - Burst length. This must.." newline hexmask.long.byte 0x0 16.--21. 1. "T_FAW,tFAW - valid only when 8 or more banks(or banks x bank groups) are present. In 8-bank design at most 4 banks must be activated in a rolling window of tFAW cycles. When the controller is operating in 1:2 frequency ratio mode program this to.." newline hexmask.long.byte 0x0 8.--14. 1. "T_RAS_MAX,tRAS(max) - Specifies the maximum time between activate and precharge to same bank. This is the maximum time that a page can be kept open Minimum value of this register is 1. Zero is invalid. When the controller is operating in 1:1 frequency.." newline hexmask.long.byte 0x0 0.--5. 1. "T_RAS_MIN,tRAS(min) - Specifies the minimum time between activate and precharge to the same bank. When the controller is operating in 1:2 frequency mode 1T mode program this to tRAS(min)/2. No rounding up. When the controller is operating in 1:2.." line.long 0x4 "DRAMTMG1,[FREQ1] SDRAM Timing Register 1" hexmask.long.byte 0x4 16.--20. 1. "T_XP,tXP - Specifies the minimum time after power-down exit to any operation. For DDR3 this must be programmed to tXPDLL if slow powerdown exit is selected in MR0[12]. If C/A parity for DDR4 is used set to (tXP+PL) instead. If LPDDR4 is selected and.." newline hexmask.long.byte 0x4 8.--13. 1. "RD2PRE,tRTP - Specifies the minimum time from read to precharge of same bank. - DDR2 - tAL + BL/2 + max(tRTP 2) - 2 - DDR3 - tAL + max (tRTP 4) - DDR4 - Max of following two equations: tAL + max (tRTP 4) or RL + BL/2 - tRP (*). - mDDR - BL/2 - LPDDR2.." newline hexmask.long.byte 0x4 0.--6. 1. "T_RC,tRC - Specifies the minimum time between activates to same bank. When the controller is operating in 1:2 frequency ratio mode program this to (tRC/2) and round up to next integer value. Unit: DFI clock cycles. Programming Mode: Quasi-dynamic Group.." line.long 0x8 "DRAMTMG2,[FREQ1] SDRAM Timing Register 2" hexmask.long.byte 0x8 24.--29. 1. "WRITE_LATENCY,Set this field to WL. Indicates the Time from write command to write data on SDRAM interface. This must be set to WL. For mDDR it must be set to 1. Note that depending on the PHY if using RDIMM/LRDIMM it might be necessary to adjust the.." newline hexmask.long.byte 0x8 16.--21. 1. "READ_LATENCY,Set this field to RL. Indicates the time from read command to read data on SDRAM interface. This must be set to RL. Note that depending on the PHY if using RDIMM/LRDIMM it might be necessary to adjust the value of RL to compensate for the.." newline hexmask.long.byte 0x8 8.--13. 1. "RD2WR,DDR2/3/mDDR: RL + BL/2 + 2 - WL DDR4: RL + BL/2 + 1 + WR_PREAMBLE - WL LPDDR2/LPDDR3: RL + BL/2 + RU(tDQSCKmax/tCK) + 1 - WL LPDDR4(DQ ODT is Disabled): RL + BL/2 + RU(tDQSCKmax/tCK) + WR_PREAMBLE + RD_POSTAMBLE - WL LPDDR4(DQ ODT is Enabled): RL +.." newline hexmask.long.byte 0x8 0.--5. 1. "WR2RD,DDR4: CWL + PL + BL/2 + tWTR_L LPDDR2/3/4: WL + BL/2 + tWTR + 1 Others: CWL + BL/2 + tWTR In DDR4 minimum time from write command to read command for same bank group. In others minimum time from write command to read command. Includes time for.." line.long 0xC "DRAMTMG3,[FREQ1] SDRAM Timing Register 3" hexmask.long.word 0xC 20.--29. 1. "T_MRW,Indicates the time to wait after a mode register write or read (MRW or MRR). Present only in designs configured to support LPDDR2 LPDDR3 or LPDDR4. LPDDR2 typically requires value of 5. LPDDR3 typically requires value of 10. LPDDR4: Set this to.." newline hexmask.long.byte 0xC 12.--17. 1. "T_MRD,tMRD- Indicates the number of cycles to wait after a mode register write or read. Depending on the connected SDRAM tMRD represents: - DDR2/mDDR: Time from MRS to any command - DDR3/4: Time from MRS to MRS command - LPDDR2: not used - LPDDR3/4:.." newline hexmask.long.word 0xC 0.--9. 1. "T_MOD,tMOD - Parameter used only in DDR3 and DDR4. Indicates the number of cycles between load mode command and following non-load mode command. If C/A parity for DDR4 is used set to tMOD_PAR(tMOD+PL) instead. If CAL mode is enabled.." line.long 0x10 "DRAMTMG4,[FREQ1] SDRAM Timing Register 4" hexmask.long.byte 0x10 24.--28. 1. "T_RCD,tRCD - tAL: Indicates the minimum time from activate to read or write command to same bank. When the controller is operating in 1:2 frequency ratio mode program this to ((tRCD - tAL)/2) and round it up to the next integer value. Minimum value.." newline hexmask.long.byte 0x10 16.--19. 1. "T_CCD,DDR4: tCCD_L: This is the minimum time between two reads or two writes for same bank group. Others: tCCD: This is the minimum time between two reads or two writes. When the controller is operating in 1:2 frequency ratio mode program this to.." newline hexmask.long.byte 0x10 8.--11. 1. "T_RRD,DDR4: tRRD_L: This is the minimum time between activates from bank 'a' to bank 'b' for same bank group. Others: tRRD: Minimum time between activates from bank 'a' to bank 'b' When the controller is operating in 1:2 frequency ratio mode program.." newline hexmask.long.byte 0x10 0.--4. 1. "T_RP,tRP: Indicates the minimum time from single-bank precharge to activate of same bank. When the controller is operating in 1:1 frequency ratio mode t_rp must be set to RoundUp(tRP/tCK). When the controller is operating in 1:2 frequency ratio mode.." line.long 0x14 "DRAMTMG5,[FREQ1] SDRAM Timing Register 5" hexmask.long.byte 0x14 24.--27. 1. "T_CKSRX,This is the time before self-refresh Exit that CK is maintained as a valid clock before issuing SRX. Specifies the clock stable time before SRX. Recommended settings: - mDDR - 1 - LPDDR2 - 2 - LPDDR3 - 2 - LPDDR4 - tCKCKEH - DDR2 - 1 - DDR3 -.." newline hexmask.long.byte 0x14 16.--19. 1. "T_CKSRE,This is the time after self-refresh Down Entry that CK is maintained as a valid clock. Specifies the clock disable delay after SRE. Recommended settings: - mDDR - 0 - LPDDR2 - 2 - LPDDR3 - 2 - LPDDR4 - tCKELCK - DDR2 - 1 - DDR3 - Max (10 ns 5.." newline hexmask.long.byte 0x14 8.--13. 1. "T_CKESR,Indicates the minimum CKE low width for self-refresh or self-refresh power down entry to exit timing in memory clock cycles. Recommended settings: - mDDR - tRFC - LPDDR2 - tCKESR - LPDDR3 - tCKESR - LPDDR4 - max(tCKE tSR) - DDR2 - tCKE - DDR3 -.." newline hexmask.long.byte 0x14 0.--4. 1. "T_CKE,Indicates the minimum number of cycles of CKE HIGH/LOW during power-down and self-refresh. - LPDDR2/LPDDR3 mode - Set this to the larger of tCKE or tCKESR - LPDDR4 mode - Set this to the larger of tCKE or tSR - Non-LPDDR2/non-LPDDR3/non-LPDDR4.." line.long 0x18 "DRAMTMG6,[FREQ1] SDRAM Timing Register 6" hexmask.long.byte 0x18 24.--27. 1. "T_CKDPDE,This is the time after Deep Power Down Entry that CK is maintained as a valid clock. Specifies the clock disable delay after DPDE. Recommended settings: - mDDR: 0 - LPDDR2: 2 - LPDDR3: 2 When the controller is operating in 1:2 frequency ratio.." newline hexmask.long.byte 0x18 16.--19. 1. "T_CKDPDX,This is the time before Deep Power Down Exit that CK is maintained as a valid clock before issuing DPDX. Specifies the clock stable time before DPDX. Recommended settings: - mDDR - 1 - LPDDR2 - 2 - LPDDR3 - 2 When the controller is operating in.." newline hexmask.long.byte 0x18 0.--3. 1. "T_CKCSX,This is the time before Clock Stop Exit that CK is maintained as a valid clock before issuing Clock Stop Exit. Specifies the clock stable time before next command after Clock Stop Exit. Recommended settings: - mDDR - 1 - LPDDR2 - tXP + 2 - LPDDR3.." line.long 0x1C "DRAMTMG7,[FREQ1] SDRAM Timing Register 7" hexmask.long.byte 0x1C 8.--11. 1. "T_CKPDE,This is the time after Power Down Entry that CK is maintained as a valid clock. Specifies the clock disable delay after PDE. Recommended settings: - mDDR - 0 - LPDDR2 - 2 - LPDDR3 - 2 - LPDDR4 - tCKELCK When using DDR2/3/4 SDRAM this register.." newline hexmask.long.byte 0x1C 0.--3. 1. "T_CKPDX,This is the time before Power Down Exit that CK is maintained as a valid clock before issuing PDX. Specifies the clock stable time before PDX. Recommended settings: - mDDR - 0 - LPDDR2 - 2 - LPDDR3 - 2 - LPDDR4 - tCKCKEH When using DDR2/3/4 SDRAM.." line.long 0x20 "DRAMTMG8,[FREQ1] SDRAM Timing Register 8" hexmask.long.byte 0x20 24.--30. 1. "T_XS_FAST_X32,tXS_FAST: Exit self-refresh to ZQCL ZQCS and MRS (only CL WR RTP and Geardown mode). When the controller is operating in 1:2 frequency ratio mode program this to the previous value divided by 2 and round up to next integer value. Note:.." newline hexmask.long.byte 0x20 16.--22. 1. "T_XS_ABORT_X32,tXS_ABORT: Exit self-refresh to commands not requiring a locked DLL in self-refresh Abort. When the controller is operating in 1:2 frequency ratio mode program this to the previous value divided by 2 and round up to next integer value." newline hexmask.long.byte 0x20 8.--14. 1. "T_XS_DLL_X32,tXSDLL: Exit self-refresh to commands requiring a locked DLL. When the controller is operating in 1:2 frequency ratio mode program this to the previous value divided by 2 and round up to next integer value. Note: Used only for DDR2 DDR3.." newline hexmask.long.byte 0x20 0.--6. 1. "T_XS_X32,tXS: Exit self-refresh to commands not requiring a locked DLL. When the controller is operating in 1:2 frequency ratio mode program this to the previous value divided by 2 and round up to next integer value. Note: Used only for DDR2 DDR3 and.." line.long 0x24 "DRAMTMG9,[FREQ1] SDRAM Timing Register 9" bitfld.long 0x24 30. "DDR4_WR_PREAMBLE,DDR4 Write preamble mode. - 0 - 1tCK preamble - 1 - 2tCK preamble Present only with MEMC_FREQ_RATIO=2. Programming Mode: Quasi-dynamic Group 2 Group 4" "0,1" newline bitfld.long 0x24 16.--18. "T_CCD_S,tCCD_S: This is the minimum time between two reads or two writes for different bank group. For bank switching (from bank 'a' to bank 'b') the minimum time is this value + 1. When the controller is operating in 1:2 frequency ratio mode program.." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x24 8.--11. 1. "T_RRD_S,tRRD_S: This is the minimum time between activates from bank 'a' to bank 'b' for different bank group. When the controller is operating in 1:2 frequency ratio mode program this to (tRRD_S/2) and round it up to the next integer value. Present.." newline hexmask.long.byte 0x24 0.--5. 1. "WR2RD_S,CWL + PL + BL/2 + tWTR_S Minimum time from write command to read command for different bank group. Includes time for bus turnaround recovery times and all per-bank per-rank and global constraints. Present only in designs configured to support.." line.long 0x28 "DRAMTMG10,[FREQ1] SDRAM Timing Register 10" hexmask.long.byte 0x28 16.--20. 1. "T_SYNC_GEAR,Indicates the time between MRS command and the sync pulse time. This must be even number of clocks. For DDR4-2666 and DDR4-3200 this parameter is defined as tMOD(min)+4nCK tMOD(min) is greater of 24nCK or 15ns 15ns / .625ns = 24 Max value.." newline hexmask.long.byte 0x28 8.--12. 1. "T_CMD_GEAR,Indicates a sync pulse to first valid command. For DDR4-2666 and DDR4-3200 this parameter is defined as tMOD(min) tMOD(min) is greater of 24nCK or 15ns 15ns / .625ns = 24 Max value for this register is 24 When the controller is operating in.." newline bitfld.long 0x28 2.--3. "T_GEAR_SETUP,Indicates the geardown setup time. Minimum value of this register is 1. Zero is invalid. For DDR4-2666 and DDR4-3200 this parameter is defined as 2 clks When the controller is operating in 1:2 frequency ratio mode program this to.." "0,1,2,3" newline bitfld.long 0x28 0.--1. "T_GEAR_HOLD,Indicates the geardown hold time. Minimum value of this register is 1. Zero is invalid. For DDR4-2666 and DDR4-3200 this parameter is defined as 2 clks When the controller is operating in 1:2 frequency ratio mode program this to.." "0,1,2,3" line.long 0x2C "DRAMTMG11,[FREQ1] SDRAM Timing Register 11" hexmask.long.byte 0x2C 24.--30. 1. "POST_MPSM_GAP_X32,tXMPDLL: This is the minimum Exit MPSM to commands requiring a locked DLL. When the controller is operating in 1:2 frequency ratio mode program this to (tXMPDLL/2) and round it up to the next integer value. Present only in designs.." newline hexmask.long.byte 0x2C 16.--20. 1. "T_MPX_LH,tMPX_LH: This is the minimum CS_n Low hold time to CKE rising edge. When the controller is operating in 1:2 frequency ratio mode program this to RoundUp(tMPX_LH/2)+1. Present only in designs configured to support DDR4. Unit: DFI clock cycles." newline bitfld.long 0x2C 8.--9. "T_MPX_S,tMPX_S: This is the minimum time CS setup time to CKE. When the controller is operating in 1:2 frequency ratio mode program this to (tMPX_S/2) and round it up to the next integer value. Present only in designs configured to support DDR4. Unit:.." "0,1,2,3" newline hexmask.long.byte 0x2C 0.--4. 1. "T_CKMPE,tCKMPE: This is the minimum valid clock requirement after MPSM entry. Present only in designs configured to support DDR4. When the controller is operating in 1:2 frequency ratio mode divide the value calculated using the previous equation by 2.." line.long 0x30 "DRAMTMG12,[FREQ1] SDRAM Timing Register 12" hexmask.long.byte 0x30 24.--29. 1. "T_WR_MPR,This bit is used only in DDR4. Cycles between MPR Write and other command. Set this to tMOD + AL (or tMOD + PL + AL if C/A parity is also used). When the controller is operating in 1:2 frequency ratio mode program this to (tWR_MPR/2) and round.." newline bitfld.long 0x30 16.--17. "T_CMDCKE,tCMDCKE: Indicates the delay from valid command to CKE input LOW. Set this to the larger of tESCKE or tCMDCKE When the controller is operating in 1:2 frequency ratio mode program this to (max(tESCKE tCMDCKE)/2) and round it up to the next.." "0,1,2,3" newline hexmask.long.byte 0x30 0.--4. 1. "T_MRD_PDA,tMRD_PDA: This is the Mode Register Set command cycle time in PDA mode. When the controller is operating in 1:2 frequency ratio mode program this to (tMRD_PDA/2) and round it up to the next integer value. Unit: DFI clock cycles. Programming.." line.long 0x34 "DRAMTMG13,[FREQ1] SDRAM Timing Register 13" hexmask.long.byte 0x34 24.--30. 1. "ODTLOFF,LPDDR4: ODTLoff: This is the latency from CAS-2 command to ODToff reference. When the controller is operating in 1:2 frequency ratio mode program this to (ODTLoff/2) and round it up to the next integer value. Unit: DFI clock cycles. Programming.." newline hexmask.long.byte 0x34 16.--21. 1. "T_CCD_MW,LPDDR4: tCCDMW: This is the minimum time from write or masked write to masked write command for same bank. When the controller is operating in 1:2 frequency ratio mode program this to (tCCDMW/2) and round it up to the next integer value. Unit:.." newline bitfld.long 0x34 0.--2. "T_PPD,LPDDR4: tPPD: This is the minimum time from precharge to precharge command. When the controller is operating in 1:2 frequency ratio mode program this to (tPPD/2) and round it up to the next integer value. Unit: DFI clock cycles. Programming Mode:.." "?,?,?,?,tPPD: This is the minimum time from precharge to..,?,?,?" line.long 0x38 "DRAMTMG14,[FREQ1] SDRAM Timing Register 14" hexmask.long.word 0x38 0.--11. 1. "T_XSR,tXSR: This is the exit self-refresh to any command. When the controller is operating in 1:2 frequency ratio mode program this to the previous value divided by 2 and round up to next integer value. The value 0xfff is illegal for this register.." line.long 0x3C "DRAMTMG15,[FREQ1] SDRAM Timing Register 15" bitfld.long 0x3C 31. "EN_DFI_LP_T_STAB,- 1 - Enable using tSTAB when exiting DFI LP. This must be set when the PHY is stopping the clock during DFI LP to save maximum power. - 0 - Disable using tSTAB when exiting DFI LP. Programming Mode: Quasi-dynamic Group 2 Group 4" "Disable using tSTAB when exiting DFI LP,Enable using tSTAB when exiting DFI LP" newline hexmask.long.byte 0x3C 0.--7. 1. "T_STAB_X32,tSTAB: Stabilization time. It is required in the following two cases for DDR3/DDR4 RDIMM: - When exiting power saving mode if the clock is stopped after re-enabling it the clock must be stable for a time specified by tSTAB - In the case of.." group.long 0x180++0x3 line.long 0x0 "ZQCTL0,[FREQ1] ZQ Control Register 0" bitfld.long 0x0 31. "DIS_AUTO_ZQ,- 1 - Disable uMCTL2 generation of ZQCS/MPC(ZQ calibration) command. Register DBGCMD.zq_calib_short can be used instead to issue ZQ calibration request from APB module - 0 - Internally generate ZQCS/MPC(ZQ calibration) commands based on.." "Internally generate ZQCS/MPC,Disable uMCTL2 generation of ZQCS/MPC" newline bitfld.long 0x0 30. "DIS_SRX_ZQCL,- 1 - Disable issuing of ZQCL/MPC(ZQ calibration) command at self-refresh/SR-Powerdown exit. Only applicable when run in DDR3 or DDR4 or LPDDR2 or LPDDR3 or LPDDR4 mode - 0 - Enable issuing of ZQCL/MPC(ZQ calibration) command at.." "Enable issuing of ZQCL/MPC,Disable issuing of ZQCL/MPC" newline bitfld.long 0x0 29. "ZQ_RESISTOR_SHARED,- 1 - Denotes that ZQ resistor is shared between ranks. Means ZQinit/ZQCL/ZQCS/MPC(ZQ calibration) commands are sent to one rank at a time with tZQinit/tZQCL/tZQCS/tZQCAL/tZQLAT timing met between commands so that commands to different.." "ZQ resistor is not shared,Denotes that ZQ resistor is shared between ranks" newline bitfld.long 0x0 28. "DIS_MPSMX_ZQCL,- 1 - Disable issuing of ZQCL command at Maximum Power Saving Mode exit. Only applicable when run in DDR4 mode - 0 - Enable issuing of ZQCL command at Maximum Power Saving Mode exit. Only applicable when run in DDR4 mode This is only.." "Enable issuing of ZQCL command at Maximum Power..,Disable issuing of ZQCL command at Maximum Power.." newline hexmask.long.word 0x0 16.--26. 1. "T_ZQ_LONG_NOP,tZQoper for DDR3/DDR4 tZQCL for LPDDR2/LPDDR3 tZQCAL for LPDDR4: Number of DFI clock cycles of NOP required after a ZQCL (ZQ calibration long)/MPC(ZQ Start) command is issued to SDRAM. When the controller is operating in 1:2 frequency.." newline hexmask.long.word 0x0 0.--9. 1. "T_ZQ_SHORT_NOP,tZQCS for DDR3/DD4/LPDDR2/LPDDR3 tZQLAT for LPDDR4: Number of DFI clock cycles of NOP required after a ZQCS (ZQ calibration short)/MPC(ZQ Latch) command is issued to SDRAM. When the controller is operating in 1:2 frequency ratio mode.." group.long 0x190++0x7 line.long 0x0 "DFITMG0,[FREQ1] DFI Timing Register 0" hexmask.long.byte 0x0 24.--28. 1. "DFI_T_CTRL_DELAY,Specifies the number of DFI clock cycles after an assertion or de-assertion of the DFI control signals that the control signals at the PHY-DRAM interface reflect the assertion or de-assertion. If the DFI clock and the memory clock are.." newline bitfld.long 0x0 23. "DFI_RDDATA_USE_DFI_PHY_CLK,Defines whether dfi_rddata_en/dfi_rddata/dfi_rddata_valid is generated using HDR (DFI clock) or SDR (DFI PHY clock) values. Selects whether value in DFITMG0.dfi_t_rddata_en is in terms of HDR (DFI clock) or SDR (DFI PHY clock).." "Else,?" newline hexmask.long.byte 0x0 16.--22. 1. "DFI_T_RDDATA_EN,Time from the assertion of a read command on the DFI interface to the assertion of the dfi_rddata_en signal. Refer to PHY specification for correct value. This corresponds to the DFI parameter trddata_en. Note that depending on the PHY.." newline bitfld.long 0x0 15. "DFI_WRDATA_USE_DFI_PHY_CLK,Defines whether dfi_wrdata_en/dfi_wrdata/dfi_wrdata_mask is generated using HDR (DFI clock) or SDR (DFI PHY clock) values. Selects whether value in DFITMG0.dfi_tphy_wrlat is in terms of HDR (DFI clock) or SDR (DFI PHY clock).." "Else,?" newline hexmask.long.byte 0x0 8.--13. 1. "DFI_TPHY_WRDATA,Specifies the number of clock cycles between when dfi_wrdata_en is asserted to when the associated write data is driven on the dfi_wrdata signal. This corresponds to the DFI timing parameter tphy_wrdata. For more information on correct.." newline hexmask.long.byte 0x0 0.--5. 1. "DFI_TPHY_WRLAT,Write latency. Number of clocks from the write command to write data enable (dfi_wrdata_en). This corresponds to the DFI timing parameter tphy_wrlat. Refer to PHY specification for correct value.Note that depending on the PHY if using.." line.long 0x4 "DFITMG1,[FREQ1] DFI Timing Register 1" hexmask.long.byte 0x4 28.--31. 1. "DFI_T_CMD_LAT,Specifies the number of DFI PHY clock cycles between when the dfi_cs signal is asserted and when the associated command is driven. This field is used for CAL mode must be set to '0' or tCAL which matches the CAL mode register setting in.." newline bitfld.long 0x4 24.--25. "DFI_T_PARIN_LAT,Specifies the number of DFI PHY clock cycles between when the dfi_cs signal is asserted and when the associated dfi_parity_in signal is driven. Unit: DFI PHY clock cycles. Programming Mode: Quasi-dynamic Group 4" "0,1,2,3" newline hexmask.long.byte 0x4 16.--20. 1. "DFI_T_WRDATA_DELAY,Specifies the number of DFI clock cycles between when the dfi_wrdata_en signal is asserted and when the corresponding write data transfer is completed on the DRAM bus. This corresponds to the DFI timing parameter twrdata_delay. For.." newline hexmask.long.byte 0x4 8.--12. 1. "DFI_T_DRAM_CLK_DISABLE,Specifies the number of DFI clock cycles from the assertion of the dfi_dram_clk_disable signal on the DFI until the clock to the DRAM memory devices at the PHY-DRAM boundary maintains a low value. If the DFI clock and the memory.." newline hexmask.long.byte 0x4 0.--4. 1. "DFI_T_DRAM_CLK_ENABLE,Specifies the number of DFI clock cycles from the de-assertion of the dfi_dram_clk_disable signal on the DFI until the first valid rising edge of the clock to the DRAM memory devices at the PHY-DRAM boundary. If the DFI clock and.." group.long 0x1B4++0x7 line.long 0x0 "DFITMG2,[FREQ1] DFI Timing Register 2" hexmask.long.byte 0x0 8.--14. 1. "DFI_TPHY_RDCSLAT,specifies the number of DFI PHY clock cycles between when a read command is sent on the DFI control interface and when the associated dfi_rddata_cs signal is asserted. This corresponds to the DFI timing parameter tphy_rdcslat. Refer to.." newline hexmask.long.byte 0x0 0.--5. 1. "DFI_TPHY_WRCSLAT,Specifies the number of DFI PHY clock cycles between when a write command is sent on the DFI control interface and when the associated dfi_wrdata_cs signal is asserted. This corresponds to the DFI timing parameter tphy_wrcslat. For more.." line.long 0x4 "DFITMG3,[FREQ1] DFI Timing Register 3" hexmask.long.byte 0x4 0.--4. 1. "DFI_T_GEARDOWN_DELAY,The delay from dfi_geardown_en assertion to the time of the PHY being ready to receive commands. Refer to PHY specification for correct value. When the controller is operating in 1:2 frequency ratio mode program this to.." group.long 0x240++0x3 line.long 0x0 "ODTCFG,[FREQ1] ODT Configuration Register" hexmask.long.byte 0x0 24.--27. 1. "WR_ODT_HOLD,DFI PHY clock cycles to hold ODT for a write command. The minimum supported value is 2. Recommended values: DDR2: - BL8 - 0x5 (DDR2-400/533/667) 0x6 (DDR2-800) 0x7 (DDR2-1066) - BL4 - 0x3 (DDR2-400/533/667) 0x4 (DDR2-800) 0x5 (DDR2-1066).." newline hexmask.long.byte 0x0 16.--20. 1. "WR_ODT_DELAY,Indicates the delay in DFI PHY clock cycles from issuing a write command to setting ODT values associated with that command. ODT setting must remain constant for the entire time that DQS is driven by the uMCTL2. Recommended values: DDR2: -.." newline hexmask.long.byte 0x0 8.--11. 1. "RD_ODT_HOLD,DFI PHY clock cycles to hold ODT for a read command. The minimum supported value is 2. Recommended values: DDR2: - BL8 - 0x6 (not DDR2-1066) 0x7 (DDR2-1066) - BL4 - 0x4 (not DDR2-1066) 0x5 (DDR2-1066) DDR3: - BL8 - 0x6 DDR4: - BL8 - 5 +.." newline hexmask.long.byte 0x0 2.--6. 1. "RD_ODT_DELAY,Indicates the delay in DFI PHY clock cycles from issuing a read command to setting ODT values associated with that command. ODT setting must remain constant for the entire time that DQS is driven by the uMCTL2. Recommended values: DDR2: -.." tree.end tree "UMCTL2_REGS_FREQ2 (uMCTL2 DDRC FERQ2 Registers)" base ad:0x12288 group.long 0x20++0x7 line.long 0x0 "DERATEEN,[FREQ2] Temperature Derate Enable Register" bitfld.long 0x0 12. "DERATE_MR4_TUF_DIS,Disables use of MR4 TUF flag (MR4[7]) bit. - 0 - Use MR4 TUF flag (MR4[7]) - 1 - Do not use MR4 TUF Flag (MR4[7]) For LPDDR4 it is recommended to set this register to 1. For LPDDR2 and LPDDR3 contact your memory vendor for.." "Use MR4 TUF flag,Do not use MR4 TUF Flag" newline bitfld.long 0x0 8.--10. "RC_DERATE_VALUE,Derate value of tRC for LPDDR4. - 0 - Derating uses +1 - 1 - Derating uses +2 - 2 - Derating uses +3 - 3 - Derating uses +4 Present only in designs configured to support LPDDR4. The required cycles for derating can be determined by.." "Derating uses +1,Derating uses +2,Derating uses +3,Derating uses +4,?,?,?,?" newline hexmask.long.byte 0x0 4.--7. 1. "DERATE_BYTE,This bit indicates which byte of the MRR data is used for derating. The maximum valid value depends on MEMC_DRAM_TOTAL_DATA_WIDTH. Present only in designs configured to support LPDDR2/LPDDR3/LPDDR4. Programming Mode: Static" newline bitfld.long 0x0 1.--2. "DERATE_VALUE,Derate value. - 0 - Derating uses +1 - 1 - Derating uses +2 Present only in designs configured to support LPDDR2/LPDDR3/LPDDR4. Set to 0 for all LPDDR2 speed grades as derating value of +1.875 ns is less than a core_ddrc_core_clk period. For.." "Derating uses +1,Derating uses +2,?,?" newline bitfld.long 0x0 0. "DERATE_ENABLE,Enables derating. - 0 - Timing parameter derating is disabled - 1 - Timing parameter derating is enabled using MR4 read value Present only in designs configured to support LPDDR2/LPDDR3/LPDDR4. This field must be set to '0' for.." "Timing parameter derating is disabled,Timing parameter derating is enabled using MR4.." line.long 0x4 "DERATEINT,[FREQ2] Temperature Derate Interval Register" hexmask.long 0x4 0.--31. 1. "MR4_READ_INTERVAL,Interval between two MR4 reads used to derate the timing parameters. Present only in designs configured to support LPDDR2/LPDDR3/LPDDR4. This register must not be set to zero. Unit: DFI clock cycles. Programming Mode: Static" group.long 0x34++0x3 line.long 0x0 "PWRTMG,[FREQ2] Low Power Timing Register" hexmask.long.byte 0x0 16.--23. 1. "SELFREF_TO_X32,After this many clocks of the DDRC command channel being idle the uMCTL2 automatically puts the SDRAM into self-refresh. The DDRC command channel is considered idle when there are no HIF commands outstanding. This must be enabled in the.." newline hexmask.long.byte 0x0 8.--15. 1. "T_DPD_X4096,Minimum deep power-down time. For mDDR value from the JEDEC specification is 0 as mDDR exits from deep power-down mode immediately after PWRCTL.deeppowerdown_en is de-asserted. For LPDDR2/LPDDR3 value from the JEDEC specification is 500us." newline hexmask.long.byte 0x0 0.--4. 1. "POWERDOWN_TO_X32,After this many clocks of the DDRC command channel being idle the uMCTL2 automatically puts the SDRAM into power-down. The DDRC command channel is considered idle when there are no HIF commands outstanding. This must be enabled in the.." group.long 0x50++0x3 line.long 0x0 "RFSHCTL0,[FREQ2] Refresh Control Register 0" hexmask.long.byte 0x0 20.--23. 1. "REFRESH_MARGIN,Threshold value in number of DFI clock cycles before the critical refresh or page timer expires. A critical refresh is to be issued before this threshold is reached. It is recommended that this not be changed from the default value.." newline hexmask.long.byte 0x0 12.--16. 1. "REFRESH_TO_X1_X32,If the refresh timer (tRFCnom also known as tREFI) has expired at least once then a speculative refresh may be performed. A speculative refresh is a refresh performed at a time when refresh would be useful. When the SDRAM bus is idle.." newline hexmask.long.byte 0x0 4.--9. 1. "REFRESH_BURST,The programmed value + 1 is the number of refresh timeouts that is allowed to accumulate before traffic is blocked and the refreshes are forced to execute. Closing pages to perform a refresh is a one-time penalty that must be paid for each.." newline bitfld.long 0x0 2. "PER_BANK_REFRESH,- 1 - Per bank refresh - 0 - All bank refresh Per bank refresh allows traffic to flow to other banks. Per bank refresh is not supported by all LPDDR2 devices but must be supported by all LPDDR3/LPDDR4 devices. Present only in designs.." "All bank refresh,Per bank refresh" group.long 0x64++0x7 line.long 0x0 "RFSHTMG,[FREQ2] Refresh Timing Register" bitfld.long 0x0 31. "T_RFC_NOM_X1_SEL,Specifies whether the RFSHTMG.t_rfc_nom_x1_x32 and RFSHCTL0.refresh_to_x1_x32 register values are x1 or x32. - 0 - x32 register values are used - 1 - x1 register values are used This applies only when per-bank refresh is enabled.." "x32 register values are used,x1 register values are used" newline hexmask.long.word 0x0 16.--27. 1. "T_RFC_NOM_X1_X32,Average time interval between refreshes per rank (Specification: 7.8us for DDR2 DDR3 and DDR4. See JEDEC specification for mDDR LPDDR2 LPDDR3 and LPDDR4). When the controller is operating in 1:1 mode set this register to.." newline bitfld.long 0x0 15. "LPDDR3_TREFBW_EN,Used only when LPDDR3 memory type is connected. Should only be changed when uMCTL2 is in reset. Specifies whether to use the tREFBW parameter (required by some LPDDR3 devices which comply with earlier versions of the LPDDR3 JEDEC.." "tREFBW parameter not used,tREFBW parameter used" newline hexmask.long.word 0x0 0.--9. 1. "T_RFC_MIN,tRFC (min): Minimum time from refresh to refresh or activate. When the controller is operating in 1:1 mode t_rfc_min must be set to RoundUp(tRFCmin/tCK). When the controller is operating in 1:2 mode t_rfc_min must be set to.." line.long 0x4 "RFSHTMG1,[FREQ2] Refresh Timing Register1" hexmask.long.byte 0x4 16.--23. 1. "T_PBR2PBR,LPDDR4:tpbR2pbR. Per-bank refresh to Per-bank refresh different bank Time. When the controller is operating in 1:1 frequency ratio mode program this to RoundUp(tpbR2pbR/tCK). When the controller is operating in 1:2 frequency ratio mode.." repeat 4. (list 0x3 0x4 0x6 0x7 )(list 0x0 0x4 0xC 0x10 ) group.long ($2+0xDC)++0x3 line.long 0x0 "INIT$1,[FREQ2] SDRAM Initialization Register 3" hexmask.long.word 0x0 16.--31. 1. "MR,DDR2:Indicates the value to write to MR register. Bit 8 is for DLL and the setting here is ignored. The uMCTL2 sets this bit appropriately. DDR3/DDR4: Value loaded into MR0 register. mDDR: Value to write to MR register. LPDDR2/LPDDR3/LPDDR4 - Value to.." newline hexmask.long.word 0x0 0.--15. 1. "EMR,DDR2: Indicates the value to write to EMR register. Bits 9:7 are for OCD and the setting in this register is ignored. The uMCTL2 sets those bits appropriately. DDR3/DDR4: Value to write to MR1 register Set bit 7 to 0. mDDR: Value to write to EMR.." repeat.end group.long 0xF4++0x3 line.long 0x0 "RANKCTL,[FREQ2] Rank Control Register" bitfld.long 0x0 26. "DIFF_RANK_WR_GAP_MSB,Only present for multi-rank configurations. 1-bit extension to be used when RANKCTL.diff_rank_wr_gap field needs to be set to a value greater than 0xF. Programming Mode: Quasi-dynamic Group 2" "?,bit extension to be used when RANKCTL" newline bitfld.long 0x0 24. "DIFF_RANK_RD_GAP_MSB,Only present for multi-rank configurations. 1-bit extension to be used when RANKCTL.diff_rank_rd_gap field needs to be set to a value greater than 0xF. Programming Mode: Quasi-dynamic Group 2" "?,bit extension to be used when RANKCTL" newline hexmask.long.byte 0x0 12.--15. 1. "MAX_RANK_WR,Only present for multi-rank configurations. Background: Writes to the same rank can be performed back-to-back. Writes to different ranks require additional gap dictated by the register RANKCTL.diff_rank_wr_gap. This is to avoid possible data.." newline hexmask.long.byte 0x0 8.--11. 1. "DIFF_RANK_WR_GAP,Only present for multi-rank configurations. Indicates the number of clocks of gap in data responses when performing consecutive writes to different ranks. This is used to switch the delays in the PHY to match the rank requirements. This.." newline hexmask.long.byte 0x0 4.--7. 1. "DIFF_RANK_RD_GAP,Only present for multi-rank configurations. Indicates the number of clocks of gap in data responses when performing consecutive reads to different ranks. This is used to switch the delays in the PHY to match the rank requirements. This.." newline hexmask.long.byte 0x0 0.--3. 1. "MAX_RANK_RD,Only present for multi-rank configurations. Background: Reads to the same rank can be performed back-to-back. Reads to different ranks require additional gap dictated by the register RANKCTL.diff_rank_rd_gap. This is to avoid possible data.." group.long 0x100++0x3F line.long 0x0 "DRAMTMG0,[FREQ2] SDRAM Timing Register 0" hexmask.long.byte 0x0 24.--30. 1. "WR2PRE,Specifies the minimum time between write and precharge to same bank. Specifications: WL + BL/2 + tWR = approximately 8 cycles + 15 ns = 14 clocks @400MHz and less for lower frequencies. where: - WL - Write latency - BL - Burst length. This must.." newline hexmask.long.byte 0x0 16.--21. 1. "T_FAW,tFAW - valid only when 8 or more banks(or banks x bank groups) are present. In 8-bank design at most 4 banks must be activated in a rolling window of tFAW cycles. When the controller is operating in 1:2 frequency ratio mode program this to.." newline hexmask.long.byte 0x0 8.--14. 1. "T_RAS_MAX,tRAS(max) - Specifies the maximum time between activate and precharge to same bank. This is the maximum time that a page can be kept open Minimum value of this register is 1. Zero is invalid. When the controller is operating in 1:1 frequency.." newline hexmask.long.byte 0x0 0.--5. 1. "T_RAS_MIN,tRAS(min) - Specifies the minimum time between activate and precharge to the same bank. When the controller is operating in 1:2 frequency mode 1T mode program this to tRAS(min)/2. No rounding up. When the controller is operating in 1:2.." line.long 0x4 "DRAMTMG1,[FREQ2] SDRAM Timing Register 1" hexmask.long.byte 0x4 16.--20. 1. "T_XP,tXP - Specifies the minimum time after power-down exit to any operation. For DDR3 this must be programmed to tXPDLL if slow powerdown exit is selected in MR0[12]. If C/A parity for DDR4 is used set to (tXP+PL) instead. If LPDDR4 is selected and.." newline hexmask.long.byte 0x4 8.--13. 1. "RD2PRE,tRTP - Specifies the minimum time from read to precharge of same bank. - DDR2 - tAL + BL/2 + max(tRTP 2) - 2 - DDR3 - tAL + max (tRTP 4) - DDR4 - Max of following two equations: tAL + max (tRTP 4) or RL + BL/2 - tRP (*). - mDDR - BL/2 - LPDDR2.." newline hexmask.long.byte 0x4 0.--6. 1. "T_RC,tRC - Specifies the minimum time between activates to same bank. When the controller is operating in 1:2 frequency ratio mode program this to (tRC/2) and round up to next integer value. Unit: DFI clock cycles. Programming Mode: Quasi-dynamic Group.." line.long 0x8 "DRAMTMG2,[FREQ2] SDRAM Timing Register 2" hexmask.long.byte 0x8 24.--29. 1. "WRITE_LATENCY,Set this field to WL. Indicates the Time from write command to write data on SDRAM interface. This must be set to WL. For mDDR it must be set to 1. Note that depending on the PHY if using RDIMM/LRDIMM it might be necessary to adjust the.." newline hexmask.long.byte 0x8 16.--21. 1. "READ_LATENCY,Set this field to RL. Indicates the time from read command to read data on SDRAM interface. This must be set to RL. Note that depending on the PHY if using RDIMM/LRDIMM it might be necessary to adjust the value of RL to compensate for the.." newline hexmask.long.byte 0x8 8.--13. 1. "RD2WR,DDR2/3/mDDR: RL + BL/2 + 2 - WL DDR4: RL + BL/2 + 1 + WR_PREAMBLE - WL LPDDR2/LPDDR3: RL + BL/2 + RU(tDQSCKmax/tCK) + 1 - WL LPDDR4(DQ ODT is Disabled): RL + BL/2 + RU(tDQSCKmax/tCK) + WR_PREAMBLE + RD_POSTAMBLE - WL LPDDR4(DQ ODT is Enabled): RL +.." newline hexmask.long.byte 0x8 0.--5. 1. "WR2RD,DDR4: CWL + PL + BL/2 + tWTR_L LPDDR2/3/4: WL + BL/2 + tWTR + 1 Others: CWL + BL/2 + tWTR In DDR4 minimum time from write command to read command for same bank group. In others minimum time from write command to read command. Includes time for.." line.long 0xC "DRAMTMG3,[FREQ2] SDRAM Timing Register 3" hexmask.long.word 0xC 20.--29. 1. "T_MRW,Indicates the time to wait after a mode register write or read (MRW or MRR). Present only in designs configured to support LPDDR2 LPDDR3 or LPDDR4. LPDDR2 typically requires value of 5. LPDDR3 typically requires value of 10. LPDDR4: Set this to.." newline hexmask.long.byte 0xC 12.--17. 1. "T_MRD,tMRD- Indicates the number of cycles to wait after a mode register write or read. Depending on the connected SDRAM tMRD represents: - DDR2/mDDR: Time from MRS to any command - DDR3/4: Time from MRS to MRS command - LPDDR2: not used - LPDDR3/4:.." newline hexmask.long.word 0xC 0.--9. 1. "T_MOD,tMOD - Parameter used only in DDR3 and DDR4. Indicates the number of cycles between load mode command and following non-load mode command. If C/A parity for DDR4 is used set to tMOD_PAR(tMOD+PL) instead. If CAL mode is enabled.." line.long 0x10 "DRAMTMG4,[FREQ2] SDRAM Timing Register 4" hexmask.long.byte 0x10 24.--28. 1. "T_RCD,tRCD - tAL: Indicates the minimum time from activate to read or write command to same bank. When the controller is operating in 1:2 frequency ratio mode program this to ((tRCD - tAL)/2) and round it up to the next integer value. Minimum value.." newline hexmask.long.byte 0x10 16.--19. 1. "T_CCD,DDR4: tCCD_L: This is the minimum time between two reads or two writes for same bank group. Others: tCCD: This is the minimum time between two reads or two writes. When the controller is operating in 1:2 frequency ratio mode program this to.." newline hexmask.long.byte 0x10 8.--11. 1. "T_RRD,DDR4: tRRD_L: This is the minimum time between activates from bank 'a' to bank 'b' for same bank group. Others: tRRD: Minimum time between activates from bank 'a' to bank 'b' When the controller is operating in 1:2 frequency ratio mode program.." newline hexmask.long.byte 0x10 0.--4. 1. "T_RP,tRP: Indicates the minimum time from single-bank precharge to activate of same bank. When the controller is operating in 1:1 frequency ratio mode t_rp must be set to RoundUp(tRP/tCK). When the controller is operating in 1:2 frequency ratio mode.." line.long 0x14 "DRAMTMG5,[FREQ2] SDRAM Timing Register 5" hexmask.long.byte 0x14 24.--27. 1. "T_CKSRX,This is the time before self-refresh Exit that CK is maintained as a valid clock before issuing SRX. Specifies the clock stable time before SRX. Recommended settings: - mDDR - 1 - LPDDR2 - 2 - LPDDR3 - 2 - LPDDR4 - tCKCKEH - DDR2 - 1 - DDR3 -.." newline hexmask.long.byte 0x14 16.--19. 1. "T_CKSRE,This is the time after self-refresh Down Entry that CK is maintained as a valid clock. Specifies the clock disable delay after SRE. Recommended settings: - mDDR - 0 - LPDDR2 - 2 - LPDDR3 - 2 - LPDDR4 - tCKELCK - DDR2 - 1 - DDR3 - Max (10 ns 5.." newline hexmask.long.byte 0x14 8.--13. 1. "T_CKESR,Indicates the minimum CKE low width for self-refresh or self-refresh power down entry to exit timing in memory clock cycles. Recommended settings: - mDDR - tRFC - LPDDR2 - tCKESR - LPDDR3 - tCKESR - LPDDR4 - max(tCKE tSR) - DDR2 - tCKE - DDR3 -.." newline hexmask.long.byte 0x14 0.--4. 1. "T_CKE,Indicates the minimum number of cycles of CKE HIGH/LOW during power-down and self-refresh. - LPDDR2/LPDDR3 mode - Set this to the larger of tCKE or tCKESR - LPDDR4 mode - Set this to the larger of tCKE or tSR - Non-LPDDR2/non-LPDDR3/non-LPDDR4.." line.long 0x18 "DRAMTMG6,[FREQ2] SDRAM Timing Register 6" hexmask.long.byte 0x18 24.--27. 1. "T_CKDPDE,This is the time after Deep Power Down Entry that CK is maintained as a valid clock. Specifies the clock disable delay after DPDE. Recommended settings: - mDDR: 0 - LPDDR2: 2 - LPDDR3: 2 When the controller is operating in 1:2 frequency ratio.." newline hexmask.long.byte 0x18 16.--19. 1. "T_CKDPDX,This is the time before Deep Power Down Exit that CK is maintained as a valid clock before issuing DPDX. Specifies the clock stable time before DPDX. Recommended settings: - mDDR - 1 - LPDDR2 - 2 - LPDDR3 - 2 When the controller is operating in.." newline hexmask.long.byte 0x18 0.--3. 1. "T_CKCSX,This is the time before Clock Stop Exit that CK is maintained as a valid clock before issuing Clock Stop Exit. Specifies the clock stable time before next command after Clock Stop Exit. Recommended settings: - mDDR - 1 - LPDDR2 - tXP + 2 - LPDDR3.." line.long 0x1C "DRAMTMG7,[FREQ2] SDRAM Timing Register 7" hexmask.long.byte 0x1C 8.--11. 1. "T_CKPDE,This is the time after Power Down Entry that CK is maintained as a valid clock. Specifies the clock disable delay after PDE. Recommended settings: - mDDR - 0 - LPDDR2 - 2 - LPDDR3 - 2 - LPDDR4 - tCKELCK When using DDR2/3/4 SDRAM this register.." newline hexmask.long.byte 0x1C 0.--3. 1. "T_CKPDX,This is the time before Power Down Exit that CK is maintained as a valid clock before issuing PDX. Specifies the clock stable time before PDX. Recommended settings: - mDDR - 0 - LPDDR2 - 2 - LPDDR3 - 2 - LPDDR4 - tCKCKEH When using DDR2/3/4 SDRAM.." line.long 0x20 "DRAMTMG8,[FREQ2] SDRAM Timing Register 8" hexmask.long.byte 0x20 24.--30. 1. "T_XS_FAST_X32,tXS_FAST: Exit self-refresh to ZQCL ZQCS and MRS (only CL WR RTP and Geardown mode). When the controller is operating in 1:2 frequency ratio mode program this to the previous value divided by 2 and round up to next integer value. Note:.." newline hexmask.long.byte 0x20 16.--22. 1. "T_XS_ABORT_X32,tXS_ABORT: Exit self-refresh to commands not requiring a locked DLL in self-refresh Abort. When the controller is operating in 1:2 frequency ratio mode program this to the previous value divided by 2 and round up to next integer value." newline hexmask.long.byte 0x20 8.--14. 1. "T_XS_DLL_X32,tXSDLL: Exit self-refresh to commands requiring a locked DLL. When the controller is operating in 1:2 frequency ratio mode program this to the previous value divided by 2 and round up to next integer value. Note: Used only for DDR2 DDR3.." newline hexmask.long.byte 0x20 0.--6. 1. "T_XS_X32,tXS: Exit self-refresh to commands not requiring a locked DLL. When the controller is operating in 1:2 frequency ratio mode program this to the previous value divided by 2 and round up to next integer value. Note: Used only for DDR2 DDR3 and.." line.long 0x24 "DRAMTMG9,[FREQ2] SDRAM Timing Register 9" bitfld.long 0x24 30. "DDR4_WR_PREAMBLE,DDR4 Write preamble mode. - 0 - 1tCK preamble - 1 - 2tCK preamble Present only with MEMC_FREQ_RATIO=2. Programming Mode: Quasi-dynamic Group 2 Group 4" "0,1" newline bitfld.long 0x24 16.--18. "T_CCD_S,tCCD_S: This is the minimum time between two reads or two writes for different bank group. For bank switching (from bank 'a' to bank 'b') the minimum time is this value + 1. When the controller is operating in 1:2 frequency ratio mode program.." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x24 8.--11. 1. "T_RRD_S,tRRD_S: This is the minimum time between activates from bank 'a' to bank 'b' for different bank group. When the controller is operating in 1:2 frequency ratio mode program this to (tRRD_S/2) and round it up to the next integer value. Present.." newline hexmask.long.byte 0x24 0.--5. 1. "WR2RD_S,CWL + PL + BL/2 + tWTR_S Minimum time from write command to read command for different bank group. Includes time for bus turnaround recovery times and all per-bank per-rank and global constraints. Present only in designs configured to support.." line.long 0x28 "DRAMTMG10,[FREQ2] SDRAM Timing Register 10" hexmask.long.byte 0x28 16.--20. 1. "T_SYNC_GEAR,Indicates the time between MRS command and the sync pulse time. This must be even number of clocks. For DDR4-2666 and DDR4-3200 this parameter is defined as tMOD(min)+4nCK tMOD(min) is greater of 24nCK or 15ns 15ns / .625ns = 24 Max value.." newline hexmask.long.byte 0x28 8.--12. 1. "T_CMD_GEAR,Indicates a sync pulse to first valid command. For DDR4-2666 and DDR4-3200 this parameter is defined as tMOD(min) tMOD(min) is greater of 24nCK or 15ns 15ns / .625ns = 24 Max value for this register is 24 When the controller is operating in.." newline bitfld.long 0x28 2.--3. "T_GEAR_SETUP,Indicates the geardown setup time. Minimum value of this register is 1. Zero is invalid. For DDR4-2666 and DDR4-3200 this parameter is defined as 2 clks When the controller is operating in 1:2 frequency ratio mode program this to.." "0,1,2,3" newline bitfld.long 0x28 0.--1. "T_GEAR_HOLD,Indicates the geardown hold time. Minimum value of this register is 1. Zero is invalid. For DDR4-2666 and DDR4-3200 this parameter is defined as 2 clks When the controller is operating in 1:2 frequency ratio mode program this to.." "0,1,2,3" line.long 0x2C "DRAMTMG11,[FREQ2] SDRAM Timing Register 11" hexmask.long.byte 0x2C 24.--30. 1. "POST_MPSM_GAP_X32,tXMPDLL: This is the minimum Exit MPSM to commands requiring a locked DLL. When the controller is operating in 1:2 frequency ratio mode program this to (tXMPDLL/2) and round it up to the next integer value. Present only in designs.." newline hexmask.long.byte 0x2C 16.--20. 1. "T_MPX_LH,tMPX_LH: This is the minimum CS_n Low hold time to CKE rising edge. When the controller is operating in 1:2 frequency ratio mode program this to RoundUp(tMPX_LH/2)+1. Present only in designs configured to support DDR4. Unit: DFI clock cycles." newline bitfld.long 0x2C 8.--9. "T_MPX_S,tMPX_S: This is the minimum time CS setup time to CKE. When the controller is operating in 1:2 frequency ratio mode program this to (tMPX_S/2) and round it up to the next integer value. Present only in designs configured to support DDR4. Unit:.." "0,1,2,3" newline hexmask.long.byte 0x2C 0.--4. 1. "T_CKMPE,tCKMPE: This is the minimum valid clock requirement after MPSM entry. Present only in designs configured to support DDR4. When the controller is operating in 1:2 frequency ratio mode divide the value calculated using the previous equation by 2.." line.long 0x30 "DRAMTMG12,[FREQ2] SDRAM Timing Register 12" hexmask.long.byte 0x30 24.--29. 1. "T_WR_MPR,This bit is used only in DDR4. Cycles between MPR Write and other command. Set this to tMOD + AL (or tMOD + PL + AL if C/A parity is also used). When the controller is operating in 1:2 frequency ratio mode program this to (tWR_MPR/2) and round.." newline bitfld.long 0x30 16.--17. "T_CMDCKE,tCMDCKE: Indicates the delay from valid command to CKE input LOW. Set this to the larger of tESCKE or tCMDCKE When the controller is operating in 1:2 frequency ratio mode program this to (max(tESCKE tCMDCKE)/2) and round it up to the next.." "0,1,2,3" newline hexmask.long.byte 0x30 0.--4. 1. "T_MRD_PDA,tMRD_PDA: This is the Mode Register Set command cycle time in PDA mode. When the controller is operating in 1:2 frequency ratio mode program this to (tMRD_PDA/2) and round it up to the next integer value. Unit: DFI clock cycles. Programming.." line.long 0x34 "DRAMTMG13,[FREQ2] SDRAM Timing Register 13" hexmask.long.byte 0x34 24.--30. 1. "ODTLOFF,LPDDR4: ODTLoff: This is the latency from CAS-2 command to ODToff reference. When the controller is operating in 1:2 frequency ratio mode program this to (ODTLoff/2) and round it up to the next integer value. Unit: DFI clock cycles. Programming.." newline hexmask.long.byte 0x34 16.--21. 1. "T_CCD_MW,LPDDR4: tCCDMW: This is the minimum time from write or masked write to masked write command for same bank. When the controller is operating in 1:2 frequency ratio mode program this to (tCCDMW/2) and round it up to the next integer value. Unit:.." newline bitfld.long 0x34 0.--2. "T_PPD,LPDDR4: tPPD: This is the minimum time from precharge to precharge command. When the controller is operating in 1:2 frequency ratio mode program this to (tPPD/2) and round it up to the next integer value. Unit: DFI clock cycles. Programming Mode:.." "?,?,?,?,tPPD: This is the minimum time from precharge to..,?,?,?" line.long 0x38 "DRAMTMG14,[FREQ2] SDRAM Timing Register 14" hexmask.long.word 0x38 0.--11. 1. "T_XSR,tXSR: This is the exit self-refresh to any command. When the controller is operating in 1:2 frequency ratio mode program this to the previous value divided by 2 and round up to next integer value. The value 0xfff is illegal for this register.." line.long 0x3C "DRAMTMG15,[FREQ2] SDRAM Timing Register 15" bitfld.long 0x3C 31. "EN_DFI_LP_T_STAB,- 1 - Enable using tSTAB when exiting DFI LP. This must be set when the PHY is stopping the clock during DFI LP to save maximum power. - 0 - Disable using tSTAB when exiting DFI LP. Programming Mode: Quasi-dynamic Group 2 Group 4" "Disable using tSTAB when exiting DFI LP,Enable using tSTAB when exiting DFI LP" newline hexmask.long.byte 0x3C 0.--7. 1. "T_STAB_X32,tSTAB: Stabilization time. It is required in the following two cases for DDR3/DDR4 RDIMM: - When exiting power saving mode if the clock is stopped after re-enabling it the clock must be stable for a time specified by tSTAB - In the case of.." group.long 0x180++0x3 line.long 0x0 "ZQCTL0,[FREQ2] ZQ Control Register 0" bitfld.long 0x0 31. "DIS_AUTO_ZQ,- 1 - Disable uMCTL2 generation of ZQCS/MPC(ZQ calibration) command. Register DBGCMD.zq_calib_short can be used instead to issue ZQ calibration request from APB module - 0 - Internally generate ZQCS/MPC(ZQ calibration) commands based on.." "Internally generate ZQCS/MPC,Disable uMCTL2 generation of ZQCS/MPC" newline bitfld.long 0x0 30. "DIS_SRX_ZQCL,- 1 - Disable issuing of ZQCL/MPC(ZQ calibration) command at self-refresh/SR-Powerdown exit. Only applicable when run in DDR3 or DDR4 or LPDDR2 or LPDDR3 or LPDDR4 mode - 0 - Enable issuing of ZQCL/MPC(ZQ calibration) command at.." "Enable issuing of ZQCL/MPC,Disable issuing of ZQCL/MPC" newline bitfld.long 0x0 29. "ZQ_RESISTOR_SHARED,- 1 - Denotes that ZQ resistor is shared between ranks. Means ZQinit/ZQCL/ZQCS/MPC(ZQ calibration) commands are sent to one rank at a time with tZQinit/tZQCL/tZQCS/tZQCAL/tZQLAT timing met between commands so that commands to different.." "ZQ resistor is not shared,Denotes that ZQ resistor is shared between ranks" newline bitfld.long 0x0 28. "DIS_MPSMX_ZQCL,- 1 - Disable issuing of ZQCL command at Maximum Power Saving Mode exit. Only applicable when run in DDR4 mode - 0 - Enable issuing of ZQCL command at Maximum Power Saving Mode exit. Only applicable when run in DDR4 mode This is only.." "Enable issuing of ZQCL command at Maximum Power..,Disable issuing of ZQCL command at Maximum Power.." newline hexmask.long.word 0x0 16.--26. 1. "T_ZQ_LONG_NOP,tZQoper for DDR3/DDR4 tZQCL for LPDDR2/LPDDR3 tZQCAL for LPDDR4: Number of DFI clock cycles of NOP required after a ZQCL (ZQ calibration long)/MPC(ZQ Start) command is issued to SDRAM. When the controller is operating in 1:2 frequency.." newline hexmask.long.word 0x0 0.--9. 1. "T_ZQ_SHORT_NOP,tZQCS for DDR3/DD4/LPDDR2/LPDDR3 tZQLAT for LPDDR4: Number of DFI clock cycles of NOP required after a ZQCS (ZQ calibration short)/MPC(ZQ Latch) command is issued to SDRAM. When the controller is operating in 1:2 frequency ratio mode.." group.long 0x190++0x7 line.long 0x0 "DFITMG0,[FREQ2] DFI Timing Register 0" hexmask.long.byte 0x0 24.--28. 1. "DFI_T_CTRL_DELAY,Specifies the number of DFI clock cycles after an assertion or de-assertion of the DFI control signals that the control signals at the PHY-DRAM interface reflect the assertion or de-assertion. If the DFI clock and the memory clock are.." newline bitfld.long 0x0 23. "DFI_RDDATA_USE_DFI_PHY_CLK,Defines whether dfi_rddata_en/dfi_rddata/dfi_rddata_valid is generated using HDR (DFI clock) or SDR (DFI PHY clock) values. Selects whether value in DFITMG0.dfi_t_rddata_en is in terms of HDR (DFI clock) or SDR (DFI PHY clock).." "Else,?" newline hexmask.long.byte 0x0 16.--22. 1. "DFI_T_RDDATA_EN,Time from the assertion of a read command on the DFI interface to the assertion of the dfi_rddata_en signal. Refer to PHY specification for correct value. This corresponds to the DFI parameter trddata_en. Note that depending on the PHY.." newline bitfld.long 0x0 15. "DFI_WRDATA_USE_DFI_PHY_CLK,Defines whether dfi_wrdata_en/dfi_wrdata/dfi_wrdata_mask is generated using HDR (DFI clock) or SDR (DFI PHY clock) values. Selects whether value in DFITMG0.dfi_tphy_wrlat is in terms of HDR (DFI clock) or SDR (DFI PHY clock).." "Else,?" newline hexmask.long.byte 0x0 8.--13. 1. "DFI_TPHY_WRDATA,Specifies the number of clock cycles between when dfi_wrdata_en is asserted to when the associated write data is driven on the dfi_wrdata signal. This corresponds to the DFI timing parameter tphy_wrdata. For more information on correct.." newline hexmask.long.byte 0x0 0.--5. 1. "DFI_TPHY_WRLAT,Write latency. Number of clocks from the write command to write data enable (dfi_wrdata_en). This corresponds to the DFI timing parameter tphy_wrlat. Refer to PHY specification for correct value.Note that depending on the PHY if using.." line.long 0x4 "DFITMG1,[FREQ2] DFI Timing Register 1" hexmask.long.byte 0x4 28.--31. 1. "DFI_T_CMD_LAT,Specifies the number of DFI PHY clock cycles between when the dfi_cs signal is asserted and when the associated command is driven. This field is used for CAL mode must be set to '0' or tCAL which matches the CAL mode register setting in.." newline bitfld.long 0x4 24.--25. "DFI_T_PARIN_LAT,Specifies the number of DFI PHY clock cycles between when the dfi_cs signal is asserted and when the associated dfi_parity_in signal is driven. Unit: DFI PHY clock cycles. Programming Mode: Quasi-dynamic Group 4" "0,1,2,3" newline hexmask.long.byte 0x4 16.--20. 1. "DFI_T_WRDATA_DELAY,Specifies the number of DFI clock cycles between when the dfi_wrdata_en signal is asserted and when the corresponding write data transfer is completed on the DRAM bus. This corresponds to the DFI timing parameter twrdata_delay. For.." newline hexmask.long.byte 0x4 8.--12. 1. "DFI_T_DRAM_CLK_DISABLE,Specifies the number of DFI clock cycles from the assertion of the dfi_dram_clk_disable signal on the DFI until the clock to the DRAM memory devices at the PHY-DRAM boundary maintains a low value. If the DFI clock and the memory.." newline hexmask.long.byte 0x4 0.--4. 1. "DFI_T_DRAM_CLK_ENABLE,Specifies the number of DFI clock cycles from the de-assertion of the dfi_dram_clk_disable signal on the DFI until the first valid rising edge of the clock to the DRAM memory devices at the PHY-DRAM boundary. If the DFI clock and.." group.long 0x1B4++0x7 line.long 0x0 "DFITMG2,[FREQ2] DFI Timing Register 2" hexmask.long.byte 0x0 8.--14. 1. "DFI_TPHY_RDCSLAT,specifies the number of DFI PHY clock cycles between when a read command is sent on the DFI control interface and when the associated dfi_rddata_cs signal is asserted. This corresponds to the DFI timing parameter tphy_rdcslat. Refer to.." newline hexmask.long.byte 0x0 0.--5. 1. "DFI_TPHY_WRCSLAT,Specifies the number of DFI PHY clock cycles between when a write command is sent on the DFI control interface and when the associated dfi_wrdata_cs signal is asserted. This corresponds to the DFI timing parameter tphy_wrcslat. For more.." line.long 0x4 "DFITMG3,[FREQ2] DFI Timing Register 3" hexmask.long.byte 0x4 0.--4. 1. "DFI_T_GEARDOWN_DELAY,The delay from dfi_geardown_en assertion to the time of the PHY being ready to receive commands. Refer to PHY specification for correct value. When the controller is operating in 1:2 frequency ratio mode program this to.." group.long 0x240++0x3 line.long 0x0 "ODTCFG,[FREQ2] ODT Configuration Register" hexmask.long.byte 0x0 24.--27. 1. "WR_ODT_HOLD,DFI PHY clock cycles to hold ODT for a write command. The minimum supported value is 2. Recommended values: DDR2: - BL8 - 0x5 (DDR2-400/533/667) 0x6 (DDR2-800) 0x7 (DDR2-1066) - BL4 - 0x3 (DDR2-400/533/667) 0x4 (DDR2-800) 0x5 (DDR2-1066).." newline hexmask.long.byte 0x0 16.--20. 1. "WR_ODT_DELAY,Indicates the delay in DFI PHY clock cycles from issuing a write command to setting ODT values associated with that command. ODT setting must remain constant for the entire time that DQS is driven by the uMCTL2. Recommended values: DDR2: -.." newline hexmask.long.byte 0x0 8.--11. 1. "RD_ODT_HOLD,DFI PHY clock cycles to hold ODT for a read command. The minimum supported value is 2. Recommended values: DDR2: - BL8 - 0x6 (not DDR2-1066) 0x7 (DDR2-1066) - BL4 - 0x4 (not DDR2-1066) 0x5 (DDR2-1066) DDR3: - BL8 - 0x6 DDR4: - BL8 - 5 +.." newline hexmask.long.byte 0x0 2.--6. 1. "RD_ODT_DELAY,Indicates the delay in DFI PHY clock cycles from issuing a read command to setting ODT values associated with that command. ODT setting must remain constant for the entire time that DQS is driven by the uMCTL2. Recommended values: DDR2: -.." tree.end tree "UMCTL2_REGS_FREQ3 (uMCTL2 DDRC FREQ3 Registers)" base ad:0x16384 group.long 0x20++0x7 line.long 0x0 "DERATEEN,[FREQ3] Temperature Derate Enable Register" bitfld.long 0x0 12. "DERATE_MR4_TUF_DIS,Disables use of MR4 TUF flag (MR4[7]) bit. - 0 - Use MR4 TUF flag (MR4[7]) - 1 - Do not use MR4 TUF Flag (MR4[7]) For LPDDR4 it is recommended to set this register to 1. For LPDDR2 and LPDDR3 contact your memory vendor for.." "Use MR4 TUF flag,Do not use MR4 TUF Flag" newline bitfld.long 0x0 8.--10. "RC_DERATE_VALUE,Derate value of tRC for LPDDR4. - 0 - Derating uses +1 - 1 - Derating uses +2 - 2 - Derating uses +3 - 3 - Derating uses +4 Present only in designs configured to support LPDDR4. The required cycles for derating can be determined by.." "Derating uses +1,Derating uses +2,Derating uses +3,Derating uses +4,?,?,?,?" newline hexmask.long.byte 0x0 4.--7. 1. "DERATE_BYTE,This bit indicates which byte of the MRR data is used for derating. The maximum valid value depends on MEMC_DRAM_TOTAL_DATA_WIDTH. Present only in designs configured to support LPDDR2/LPDDR3/LPDDR4. Programming Mode: Static" newline bitfld.long 0x0 1.--2. "DERATE_VALUE,Derate value. - 0 - Derating uses +1 - 1 - Derating uses +2 Present only in designs configured to support LPDDR2/LPDDR3/LPDDR4. Set to 0 for all LPDDR2 speed grades as derating value of +1.875 ns is less than a core_ddrc_core_clk period. For.." "Derating uses +1,Derating uses +2,?,?" newline bitfld.long 0x0 0. "DERATE_ENABLE,Enables derating. - 0 - Timing parameter derating is disabled - 1 - Timing parameter derating is enabled using MR4 read value Present only in designs configured to support LPDDR2/LPDDR3/LPDDR4. This field must be set to '0' for.." "Timing parameter derating is disabled,Timing parameter derating is enabled using MR4.." line.long 0x4 "DERATEINT,[FREQ3] Temperature Derate Interval Register" hexmask.long 0x4 0.--31. 1. "MR4_READ_INTERVAL,Interval between two MR4 reads used to derate the timing parameters. Present only in designs configured to support LPDDR2/LPDDR3/LPDDR4. This register must not be set to zero. Unit: DFI clock cycles. Programming Mode: Static" group.long 0x34++0x3 line.long 0x0 "PWRTMG,[FREQ3] Low Power Timing Register" hexmask.long.byte 0x0 16.--23. 1. "SELFREF_TO_X32,After this many clocks of the DDRC command channel being idle the uMCTL2 automatically puts the SDRAM into self-refresh. The DDRC command channel is considered idle when there are no HIF commands outstanding. This must be enabled in the.." newline hexmask.long.byte 0x0 8.--15. 1. "T_DPD_X4096,Minimum deep power-down time. For mDDR value from the JEDEC specification is 0 as mDDR exits from deep power-down mode immediately after PWRCTL.deeppowerdown_en is de-asserted. For LPDDR2/LPDDR3 value from the JEDEC specification is 500us." newline hexmask.long.byte 0x0 0.--4. 1. "POWERDOWN_TO_X32,After this many clocks of the DDRC command channel being idle the uMCTL2 automatically puts the SDRAM into power-down. The DDRC command channel is considered idle when there are no HIF commands outstanding. This must be enabled in the.." group.long 0x50++0x3 line.long 0x0 "RFSHCTL0,[FREQ3] Refresh Control Register 0" hexmask.long.byte 0x0 20.--23. 1. "REFRESH_MARGIN,Threshold value in number of DFI clock cycles before the critical refresh or page timer expires. A critical refresh is to be issued before this threshold is reached. It is recommended that this not be changed from the default value.." newline hexmask.long.byte 0x0 12.--16. 1. "REFRESH_TO_X1_X32,If the refresh timer (tRFCnom also known as tREFI) has expired at least once then a speculative refresh may be performed. A speculative refresh is a refresh performed at a time when refresh would be useful. When the SDRAM bus is idle.." newline hexmask.long.byte 0x0 4.--9. 1. "REFRESH_BURST,The programmed value + 1 is the number of refresh timeouts that is allowed to accumulate before traffic is blocked and the refreshes are forced to execute. Closing pages to perform a refresh is a one-time penalty that must be paid for each.." newline bitfld.long 0x0 2. "PER_BANK_REFRESH,- 1 - Per bank refresh - 0 - All bank refresh Per bank refresh allows traffic to flow to other banks. Per bank refresh is not supported by all LPDDR2 devices but must be supported by all LPDDR3/LPDDR4 devices. Present only in designs.." "All bank refresh,Per bank refresh" group.long 0x64++0x7 line.long 0x0 "RFSHTMG,[FREQ3] Refresh Timing Register" bitfld.long 0x0 31. "T_RFC_NOM_X1_SEL,Specifies whether the RFSHTMG.t_rfc_nom_x1_x32 and RFSHCTL0.refresh_to_x1_x32 register values are x1 or x32. - 0 - x32 register values are used - 1 - x1 register values are used This applies only when per-bank refresh is enabled.." "x32 register values are used,x1 register values are used" newline hexmask.long.word 0x0 16.--27. 1. "T_RFC_NOM_X1_X32,Average time interval between refreshes per rank (Specification: 7.8us for DDR2 DDR3 and DDR4. See JEDEC specification for mDDR LPDDR2 LPDDR3 and LPDDR4). When the controller is operating in 1:1 mode set this register to.." newline bitfld.long 0x0 15. "LPDDR3_TREFBW_EN,Used only when LPDDR3 memory type is connected. Should only be changed when uMCTL2 is in reset. Specifies whether to use the tREFBW parameter (required by some LPDDR3 devices which comply with earlier versions of the LPDDR3 JEDEC.." "tREFBW parameter not used,tREFBW parameter used" newline hexmask.long.word 0x0 0.--9. 1. "T_RFC_MIN,tRFC (min): Minimum time from refresh to refresh or activate. When the controller is operating in 1:1 mode t_rfc_min must be set to RoundUp(tRFCmin/tCK). When the controller is operating in 1:2 mode t_rfc_min must be set to.." line.long 0x4 "RFSHTMG1,[FREQ3] Refresh Timing Register1" hexmask.long.byte 0x4 16.--23. 1. "T_PBR2PBR,LPDDR4:tpbR2pbR. Per-bank refresh to Per-bank refresh different bank Time. When the controller is operating in 1:1 frequency ratio mode program this to RoundUp(tpbR2pbR/tCK). When the controller is operating in 1:2 frequency ratio mode.." repeat 4. (list 0x3 0x4 0x6 0x7 )(list 0x0 0x4 0xC 0x10 ) group.long ($2+0xDC)++0x3 line.long 0x0 "INIT$1,[FREQ3] SDRAM Initialization Register 3" hexmask.long.word 0x0 16.--31. 1. "MR,DDR2:Indicates the value to write to MR register. Bit 8 is for DLL and the setting here is ignored. The uMCTL2 sets this bit appropriately. DDR3/DDR4: Value loaded into MR0 register. mDDR: Value to write to MR register. LPDDR2/LPDDR3/LPDDR4 - Value to.." newline hexmask.long.word 0x0 0.--15. 1. "EMR,DDR2: Indicates the value to write to EMR register. Bits 9:7 are for OCD and the setting in this register is ignored. The uMCTL2 sets those bits appropriately. DDR3/DDR4: Value to write to MR1 register Set bit 7 to 0. mDDR: Value to write to EMR.." repeat.end group.long 0xF4++0x3 line.long 0x0 "RANKCTL,[FREQ3] Rank Control Register" bitfld.long 0x0 26. "DIFF_RANK_WR_GAP_MSB,Only present for multi-rank configurations. 1-bit extension to be used when RANKCTL.diff_rank_wr_gap field needs to be set to a value greater than 0xF. Programming Mode: Quasi-dynamic Group 2" "?,bit extension to be used when RANKCTL" newline bitfld.long 0x0 24. "DIFF_RANK_RD_GAP_MSB,Only present for multi-rank configurations. 1-bit extension to be used when RANKCTL.diff_rank_rd_gap field needs to be set to a value greater than 0xF. Programming Mode: Quasi-dynamic Group 2" "?,bit extension to be used when RANKCTL" newline hexmask.long.byte 0x0 12.--15. 1. "MAX_RANK_WR,Only present for multi-rank configurations. Background: Writes to the same rank can be performed back-to-back. Writes to different ranks require additional gap dictated by the register RANKCTL.diff_rank_wr_gap. This is to avoid possible data.." newline hexmask.long.byte 0x0 8.--11. 1. "DIFF_RANK_WR_GAP,Only present for multi-rank configurations. Indicates the number of clocks of gap in data responses when performing consecutive writes to different ranks. This is used to switch the delays in the PHY to match the rank requirements. This.." newline hexmask.long.byte 0x0 4.--7. 1. "DIFF_RANK_RD_GAP,Only present for multi-rank configurations. Indicates the number of clocks of gap in data responses when performing consecutive reads to different ranks. This is used to switch the delays in the PHY to match the rank requirements. This.." newline hexmask.long.byte 0x0 0.--3. 1. "MAX_RANK_RD,Only present for multi-rank configurations. Background: Reads to the same rank can be performed back-to-back. Reads to different ranks require additional gap dictated by the register RANKCTL.diff_rank_rd_gap. This is to avoid possible data.." group.long 0x100++0x3F line.long 0x0 "DRAMTMG0,[FREQ3] SDRAM Timing Register 0" hexmask.long.byte 0x0 24.--30. 1. "WR2PRE,Specifies the minimum time between write and precharge to same bank. Specifications: WL + BL/2 + tWR = approximately 8 cycles + 15 ns = 14 clocks @400MHz and less for lower frequencies. where: - WL - Write latency - BL - Burst length. This must.." newline hexmask.long.byte 0x0 16.--21. 1. "T_FAW,tFAW - valid only when 8 or more banks(or banks x bank groups) are present. In 8-bank design at most 4 banks must be activated in a rolling window of tFAW cycles. When the controller is operating in 1:2 frequency ratio mode program this to.." newline hexmask.long.byte 0x0 8.--14. 1. "T_RAS_MAX,tRAS(max) - Specifies the maximum time between activate and precharge to same bank. This is the maximum time that a page can be kept open Minimum value of this register is 1. Zero is invalid. When the controller is operating in 1:1 frequency.." newline hexmask.long.byte 0x0 0.--5. 1. "T_RAS_MIN,tRAS(min) - Specifies the minimum time between activate and precharge to the same bank. When the controller is operating in 1:2 frequency mode 1T mode program this to tRAS(min)/2. No rounding up. When the controller is operating in 1:2.." line.long 0x4 "DRAMTMG1,[FREQ3] SDRAM Timing Register 1" hexmask.long.byte 0x4 16.--20. 1. "T_XP,tXP - Specifies the minimum time after power-down exit to any operation. For DDR3 this must be programmed to tXPDLL if slow powerdown exit is selected in MR0[12]. If C/A parity for DDR4 is used set to (tXP+PL) instead. If LPDDR4 is selected and.." newline hexmask.long.byte 0x4 8.--13. 1. "RD2PRE,tRTP - Specifies the minimum time from read to precharge of same bank. - DDR2 - tAL + BL/2 + max(tRTP 2) - 2 - DDR3 - tAL + max (tRTP 4) - DDR4 - Max of following two equations: tAL + max (tRTP 4) or RL + BL/2 - tRP (*). - mDDR - BL/2 - LPDDR2.." newline hexmask.long.byte 0x4 0.--6. 1. "T_RC,tRC - Specifies the minimum time between activates to same bank. When the controller is operating in 1:2 frequency ratio mode program this to (tRC/2) and round up to next integer value. Unit: DFI clock cycles. Programming Mode: Quasi-dynamic Group.." line.long 0x8 "DRAMTMG2,[FREQ3] SDRAM Timing Register 2" hexmask.long.byte 0x8 24.--29. 1. "WRITE_LATENCY,Set this field to WL. Indicates the Time from write command to write data on SDRAM interface. This must be set to WL. For mDDR it must be set to 1. Note that depending on the PHY if using RDIMM/LRDIMM it might be necessary to adjust the.." newline hexmask.long.byte 0x8 16.--21. 1. "READ_LATENCY,Set this field to RL. Indicates the time from read command to read data on SDRAM interface. This must be set to RL. Note that depending on the PHY if using RDIMM/LRDIMM it might be necessary to adjust the value of RL to compensate for the.." newline hexmask.long.byte 0x8 8.--13. 1. "RD2WR,DDR2/3/mDDR: RL + BL/2 + 2 - WL DDR4: RL + BL/2 + 1 + WR_PREAMBLE - WL LPDDR2/LPDDR3: RL + BL/2 + RU(tDQSCKmax/tCK) + 1 - WL LPDDR4(DQ ODT is Disabled): RL + BL/2 + RU(tDQSCKmax/tCK) + WR_PREAMBLE + RD_POSTAMBLE - WL LPDDR4(DQ ODT is Enabled): RL +.." newline hexmask.long.byte 0x8 0.--5. 1. "WR2RD,DDR4: CWL + PL + BL/2 + tWTR_L LPDDR2/3/4: WL + BL/2 + tWTR + 1 Others: CWL + BL/2 + tWTR In DDR4 minimum time from write command to read command for same bank group. In others minimum time from write command to read command. Includes time for.." line.long 0xC "DRAMTMG3,[FREQ3] SDRAM Timing Register 3" hexmask.long.word 0xC 20.--29. 1. "T_MRW,Indicates the time to wait after a mode register write or read (MRW or MRR). Present only in designs configured to support LPDDR2 LPDDR3 or LPDDR4. LPDDR2 typically requires value of 5. LPDDR3 typically requires value of 10. LPDDR4: Set this to.." newline hexmask.long.byte 0xC 12.--17. 1. "T_MRD,tMRD- Indicates the number of cycles to wait after a mode register write or read. Depending on the connected SDRAM tMRD represents: - DDR2/mDDR: Time from MRS to any command - DDR3/4: Time from MRS to MRS command - LPDDR2: not used - LPDDR3/4:.." newline hexmask.long.word 0xC 0.--9. 1. "T_MOD,tMOD - Parameter used only in DDR3 and DDR4. Indicates the number of cycles between load mode command and following non-load mode command. If C/A parity for DDR4 is used set to tMOD_PAR(tMOD+PL) instead. If CAL mode is enabled.." line.long 0x10 "DRAMTMG4,[FREQ3] SDRAM Timing Register 4" hexmask.long.byte 0x10 24.--28. 1. "T_RCD,tRCD - tAL: Indicates the minimum time from activate to read or write command to same bank. When the controller is operating in 1:2 frequency ratio mode program this to ((tRCD - tAL)/2) and round it up to the next integer value. Minimum value.." newline hexmask.long.byte 0x10 16.--19. 1. "T_CCD,DDR4: tCCD_L: This is the minimum time between two reads or two writes for same bank group. Others: tCCD: This is the minimum time between two reads or two writes. When the controller is operating in 1:2 frequency ratio mode program this to.." newline hexmask.long.byte 0x10 8.--11. 1. "T_RRD,DDR4: tRRD_L: This is the minimum time between activates from bank 'a' to bank 'b' for same bank group. Others: tRRD: Minimum time between activates from bank 'a' to bank 'b' When the controller is operating in 1:2 frequency ratio mode program.." newline hexmask.long.byte 0x10 0.--4. 1. "T_RP,tRP: Indicates the minimum time from single-bank precharge to activate of same bank. When the controller is operating in 1:1 frequency ratio mode t_rp must be set to RoundUp(tRP/tCK). When the controller is operating in 1:2 frequency ratio mode.." line.long 0x14 "DRAMTMG5,[FREQ3] SDRAM Timing Register 5" hexmask.long.byte 0x14 24.--27. 1. "T_CKSRX,This is the time before self-refresh Exit that CK is maintained as a valid clock before issuing SRX. Specifies the clock stable time before SRX. Recommended settings: - mDDR - 1 - LPDDR2 - 2 - LPDDR3 - 2 - LPDDR4 - tCKCKEH - DDR2 - 1 - DDR3 -.." newline hexmask.long.byte 0x14 16.--19. 1. "T_CKSRE,This is the time after self-refresh Down Entry that CK is maintained as a valid clock. Specifies the clock disable delay after SRE. Recommended settings: - mDDR - 0 - LPDDR2 - 2 - LPDDR3 - 2 - LPDDR4 - tCKELCK - DDR2 - 1 - DDR3 - Max (10 ns 5.." newline hexmask.long.byte 0x14 8.--13. 1. "T_CKESR,Indicates the minimum CKE low width for self-refresh or self-refresh power down entry to exit timing in memory clock cycles. Recommended settings: - mDDR - tRFC - LPDDR2 - tCKESR - LPDDR3 - tCKESR - LPDDR4 - max(tCKE tSR) - DDR2 - tCKE - DDR3 -.." newline hexmask.long.byte 0x14 0.--4. 1. "T_CKE,Indicates the minimum number of cycles of CKE HIGH/LOW during power-down and self-refresh. - LPDDR2/LPDDR3 mode - Set this to the larger of tCKE or tCKESR - LPDDR4 mode - Set this to the larger of tCKE or tSR - Non-LPDDR2/non-LPDDR3/non-LPDDR4.." line.long 0x18 "DRAMTMG6,[FREQ3] SDRAM Timing Register 6" hexmask.long.byte 0x18 24.--27. 1. "T_CKDPDE,This is the time after Deep Power Down Entry that CK is maintained as a valid clock. Specifies the clock disable delay after DPDE. Recommended settings: - mDDR: 0 - LPDDR2: 2 - LPDDR3: 2 When the controller is operating in 1:2 frequency ratio.." newline hexmask.long.byte 0x18 16.--19. 1. "T_CKDPDX,This is the time before Deep Power Down Exit that CK is maintained as a valid clock before issuing DPDX. Specifies the clock stable time before DPDX. Recommended settings: - mDDR - 1 - LPDDR2 - 2 - LPDDR3 - 2 When the controller is operating in.." newline hexmask.long.byte 0x18 0.--3. 1. "T_CKCSX,This is the time before Clock Stop Exit that CK is maintained as a valid clock before issuing Clock Stop Exit. Specifies the clock stable time before next command after Clock Stop Exit. Recommended settings: - mDDR - 1 - LPDDR2 - tXP + 2 - LPDDR3.." line.long 0x1C "DRAMTMG7,[FREQ3] SDRAM Timing Register 7" hexmask.long.byte 0x1C 8.--11. 1. "T_CKPDE,This is the time after Power Down Entry that CK is maintained as a valid clock. Specifies the clock disable delay after PDE. Recommended settings: - mDDR - 0 - LPDDR2 - 2 - LPDDR3 - 2 - LPDDR4 - tCKELCK When using DDR2/3/4 SDRAM this register.." newline hexmask.long.byte 0x1C 0.--3. 1. "T_CKPDX,This is the time before Power Down Exit that CK is maintained as a valid clock before issuing PDX. Specifies the clock stable time before PDX. Recommended settings: - mDDR - 0 - LPDDR2 - 2 - LPDDR3 - 2 - LPDDR4 - tCKCKEH When using DDR2/3/4 SDRAM.." line.long 0x20 "DRAMTMG8,[FREQ3] SDRAM Timing Register 8" hexmask.long.byte 0x20 24.--30. 1. "T_XS_FAST_X32,tXS_FAST: Exit self-refresh to ZQCL ZQCS and MRS (only CL WR RTP and Geardown mode). When the controller is operating in 1:2 frequency ratio mode program this to the previous value divided by 2 and round up to next integer value. Note:.." newline hexmask.long.byte 0x20 16.--22. 1. "T_XS_ABORT_X32,tXS_ABORT: Exit self-refresh to commands not requiring a locked DLL in self-refresh Abort. When the controller is operating in 1:2 frequency ratio mode program this to the previous value divided by 2 and round up to next integer value." newline hexmask.long.byte 0x20 8.--14. 1. "T_XS_DLL_X32,tXSDLL: Exit self-refresh to commands requiring a locked DLL. When the controller is operating in 1:2 frequency ratio mode program this to the previous value divided by 2 and round up to next integer value. Note: Used only for DDR2 DDR3.." newline hexmask.long.byte 0x20 0.--6. 1. "T_XS_X32,tXS: Exit self-refresh to commands not requiring a locked DLL. When the controller is operating in 1:2 frequency ratio mode program this to the previous value divided by 2 and round up to next integer value. Note: Used only for DDR2 DDR3 and.." line.long 0x24 "DRAMTMG9,[FREQ3] SDRAM Timing Register 9" bitfld.long 0x24 30. "DDR4_WR_PREAMBLE,DDR4 Write preamble mode. - 0 - 1tCK preamble - 1 - 2tCK preamble Present only with MEMC_FREQ_RATIO=2. Programming Mode: Quasi-dynamic Group 2 Group 4" "0,1" newline bitfld.long 0x24 16.--18. "T_CCD_S,tCCD_S: This is the minimum time between two reads or two writes for different bank group. For bank switching (from bank 'a' to bank 'b') the minimum time is this value + 1. When the controller is operating in 1:2 frequency ratio mode program.." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x24 8.--11. 1. "T_RRD_S,tRRD_S: This is the minimum time between activates from bank 'a' to bank 'b' for different bank group. When the controller is operating in 1:2 frequency ratio mode program this to (tRRD_S/2) and round it up to the next integer value. Present.." newline hexmask.long.byte 0x24 0.--5. 1. "WR2RD_S,CWL + PL + BL/2 + tWTR_S Minimum time from write command to read command for different bank group. Includes time for bus turnaround recovery times and all per-bank per-rank and global constraints. Present only in designs configured to support.." line.long 0x28 "DRAMTMG10,[FREQ3] SDRAM Timing Register 10" hexmask.long.byte 0x28 16.--20. 1. "T_SYNC_GEAR,Indicates the time between MRS command and the sync pulse time. This must be even number of clocks. For DDR4-2666 and DDR4-3200 this parameter is defined as tMOD(min)+4nCK tMOD(min) is greater of 24nCK or 15ns 15ns / .625ns = 24 Max value.." newline hexmask.long.byte 0x28 8.--12. 1. "T_CMD_GEAR,Indicates a sync pulse to first valid command. For DDR4-2666 and DDR4-3200 this parameter is defined as tMOD(min) tMOD(min) is greater of 24nCK or 15ns 15ns / .625ns = 24 Max value for this register is 24 When the controller is operating in.." newline bitfld.long 0x28 2.--3. "T_GEAR_SETUP,Indicates the geardown setup time. Minimum value of this register is 1. Zero is invalid. For DDR4-2666 and DDR4-3200 this parameter is defined as 2 clks When the controller is operating in 1:2 frequency ratio mode program this to.." "0,1,2,3" newline bitfld.long 0x28 0.--1. "T_GEAR_HOLD,Indicates the geardown hold time. Minimum value of this register is 1. Zero is invalid. For DDR4-2666 and DDR4-3200 this parameter is defined as 2 clks When the controller is operating in 1:2 frequency ratio mode program this to.." "0,1,2,3" line.long 0x2C "DRAMTMG11,[FREQ3] SDRAM Timing Register 11" hexmask.long.byte 0x2C 24.--30. 1. "POST_MPSM_GAP_X32,tXMPDLL: This is the minimum Exit MPSM to commands requiring a locked DLL. When the controller is operating in 1:2 frequency ratio mode program this to (tXMPDLL/2) and round it up to the next integer value. Present only in designs.." newline hexmask.long.byte 0x2C 16.--20. 1. "T_MPX_LH,tMPX_LH: This is the minimum CS_n Low hold time to CKE rising edge. When the controller is operating in 1:2 frequency ratio mode program this to RoundUp(tMPX_LH/2)+1. Present only in designs configured to support DDR4. Unit: DFI clock cycles." newline bitfld.long 0x2C 8.--9. "T_MPX_S,tMPX_S: This is the minimum time CS setup time to CKE. When the controller is operating in 1:2 frequency ratio mode program this to (tMPX_S/2) and round it up to the next integer value. Present only in designs configured to support DDR4. Unit:.." "0,1,2,3" newline hexmask.long.byte 0x2C 0.--4. 1. "T_CKMPE,tCKMPE: This is the minimum valid clock requirement after MPSM entry. Present only in designs configured to support DDR4. When the controller is operating in 1:2 frequency ratio mode divide the value calculated using the previous equation by 2.." line.long 0x30 "DRAMTMG12,[FREQ3] SDRAM Timing Register 12" hexmask.long.byte 0x30 24.--29. 1. "T_WR_MPR,This bit is used only in DDR4. Cycles between MPR Write and other command. Set this to tMOD + AL (or tMOD + PL + AL if C/A parity is also used). When the controller is operating in 1:2 frequency ratio mode program this to (tWR_MPR/2) and round.." newline bitfld.long 0x30 16.--17. "T_CMDCKE,tCMDCKE: Indicates the delay from valid command to CKE input LOW. Set this to the larger of tESCKE or tCMDCKE When the controller is operating in 1:2 frequency ratio mode program this to (max(tESCKE tCMDCKE)/2) and round it up to the next.." "0,1,2,3" newline hexmask.long.byte 0x30 0.--4. 1. "T_MRD_PDA,tMRD_PDA: This is the Mode Register Set command cycle time in PDA mode. When the controller is operating in 1:2 frequency ratio mode program this to (tMRD_PDA/2) and round it up to the next integer value. Unit: DFI clock cycles. Programming.." line.long 0x34 "DRAMTMG13,[FREQ3] SDRAM Timing Register 13" hexmask.long.byte 0x34 24.--30. 1. "ODTLOFF,LPDDR4: ODTLoff: This is the latency from CAS-2 command to ODToff reference. When the controller is operating in 1:2 frequency ratio mode program this to (ODTLoff/2) and round it up to the next integer value. Unit: DFI clock cycles. Programming.." newline hexmask.long.byte 0x34 16.--21. 1. "T_CCD_MW,LPDDR4: tCCDMW: This is the minimum time from write or masked write to masked write command for same bank. When the controller is operating in 1:2 frequency ratio mode program this to (tCCDMW/2) and round it up to the next integer value. Unit:.." newline bitfld.long 0x34 0.--2. "T_PPD,LPDDR4: tPPD: This is the minimum time from precharge to precharge command. When the controller is operating in 1:2 frequency ratio mode program this to (tPPD/2) and round it up to the next integer value. Unit: DFI clock cycles. Programming Mode:.." "?,?,?,?,tPPD: This is the minimum time from precharge to..,?,?,?" line.long 0x38 "DRAMTMG14,[FREQ3] SDRAM Timing Register 14" hexmask.long.word 0x38 0.--11. 1. "T_XSR,tXSR: This is the exit self-refresh to any command. When the controller is operating in 1:2 frequency ratio mode program this to the previous value divided by 2 and round up to next integer value. The value 0xfff is illegal for this register.." line.long 0x3C "DRAMTMG15,[FREQ3] SDRAM Timing Register 15" bitfld.long 0x3C 31. "EN_DFI_LP_T_STAB,- 1 - Enable using tSTAB when exiting DFI LP. This must be set when the PHY is stopping the clock during DFI LP to save maximum power. - 0 - Disable using tSTAB when exiting DFI LP. Programming Mode: Quasi-dynamic Group 2 Group 4" "Disable using tSTAB when exiting DFI LP,Enable using tSTAB when exiting DFI LP" newline hexmask.long.byte 0x3C 0.--7. 1. "T_STAB_X32,tSTAB: Stabilization time. It is required in the following two cases for DDR3/DDR4 RDIMM: - When exiting power saving mode if the clock is stopped after re-enabling it the clock must be stable for a time specified by tSTAB - In the case of.." group.long 0x180++0x3 line.long 0x0 "ZQCTL0,[FREQ3] ZQ Control Register 0" bitfld.long 0x0 31. "DIS_AUTO_ZQ,- 1 - Disable uMCTL2 generation of ZQCS/MPC(ZQ calibration) command. Register DBGCMD.zq_calib_short can be used instead to issue ZQ calibration request from APB module - 0 - Internally generate ZQCS/MPC(ZQ calibration) commands based on.." "Internally generate ZQCS/MPC,Disable uMCTL2 generation of ZQCS/MPC" newline bitfld.long 0x0 30. "DIS_SRX_ZQCL,- 1 - Disable issuing of ZQCL/MPC(ZQ calibration) command at self-refresh/SR-Powerdown exit. Only applicable when run in DDR3 or DDR4 or LPDDR2 or LPDDR3 or LPDDR4 mode - 0 - Enable issuing of ZQCL/MPC(ZQ calibration) command at.." "Enable issuing of ZQCL/MPC,Disable issuing of ZQCL/MPC" newline bitfld.long 0x0 29. "ZQ_RESISTOR_SHARED,- 1 - Denotes that ZQ resistor is shared between ranks. Means ZQinit/ZQCL/ZQCS/MPC(ZQ calibration) commands are sent to one rank at a time with tZQinit/tZQCL/tZQCS/tZQCAL/tZQLAT timing met between commands so that commands to different.." "ZQ resistor is not shared,Denotes that ZQ resistor is shared between ranks" newline bitfld.long 0x0 28. "DIS_MPSMX_ZQCL,- 1 - Disable issuing of ZQCL command at Maximum Power Saving Mode exit. Only applicable when run in DDR4 mode - 0 - Enable issuing of ZQCL command at Maximum Power Saving Mode exit. Only applicable when run in DDR4 mode This is only.." "Enable issuing of ZQCL command at Maximum Power..,Disable issuing of ZQCL command at Maximum Power.." newline hexmask.long.word 0x0 16.--26. 1. "T_ZQ_LONG_NOP,tZQoper for DDR3/DDR4 tZQCL for LPDDR2/LPDDR3 tZQCAL for LPDDR4: Number of DFI clock cycles of NOP required after a ZQCL (ZQ calibration long)/MPC(ZQ Start) command is issued to SDRAM. When the controller is operating in 1:2 frequency.." newline hexmask.long.word 0x0 0.--9. 1. "T_ZQ_SHORT_NOP,tZQCS for DDR3/DD4/LPDDR2/LPDDR3 tZQLAT for LPDDR4: Number of DFI clock cycles of NOP required after a ZQCS (ZQ calibration short)/MPC(ZQ Latch) command is issued to SDRAM. When the controller is operating in 1:2 frequency ratio mode.." group.long 0x190++0x7 line.long 0x0 "DFITMG0,[FREQ3] DFI Timing Register 0" hexmask.long.byte 0x0 24.--28. 1. "DFI_T_CTRL_DELAY,Specifies the number of DFI clock cycles after an assertion or de-assertion of the DFI control signals that the control signals at the PHY-DRAM interface reflect the assertion or de-assertion. If the DFI clock and the memory clock are.." newline bitfld.long 0x0 23. "DFI_RDDATA_USE_DFI_PHY_CLK,Defines whether dfi_rddata_en/dfi_rddata/dfi_rddata_valid is generated using HDR (DFI clock) or SDR (DFI PHY clock) values. Selects whether value in DFITMG0.dfi_t_rddata_en is in terms of HDR (DFI clock) or SDR (DFI PHY clock).." "Else,?" newline hexmask.long.byte 0x0 16.--22. 1. "DFI_T_RDDATA_EN,Time from the assertion of a read command on the DFI interface to the assertion of the dfi_rddata_en signal. Refer to PHY specification for correct value. This corresponds to the DFI parameter trddata_en. Note that depending on the PHY.." newline bitfld.long 0x0 15. "DFI_WRDATA_USE_DFI_PHY_CLK,Defines whether dfi_wrdata_en/dfi_wrdata/dfi_wrdata_mask is generated using HDR (DFI clock) or SDR (DFI PHY clock) values. Selects whether value in DFITMG0.dfi_tphy_wrlat is in terms of HDR (DFI clock) or SDR (DFI PHY clock).." "Else,?" newline hexmask.long.byte 0x0 8.--13. 1. "DFI_TPHY_WRDATA,Specifies the number of clock cycles between when dfi_wrdata_en is asserted to when the associated write data is driven on the dfi_wrdata signal. This corresponds to the DFI timing parameter tphy_wrdata. For more information on correct.." newline hexmask.long.byte 0x0 0.--5. 1. "DFI_TPHY_WRLAT,Write latency. Number of clocks from the write command to write data enable (dfi_wrdata_en). This corresponds to the DFI timing parameter tphy_wrlat. Refer to PHY specification for correct value.Note that depending on the PHY if using.." line.long 0x4 "DFITMG1,[FREQ3] DFI Timing Register 1" hexmask.long.byte 0x4 28.--31. 1. "DFI_T_CMD_LAT,Specifies the number of DFI PHY clock cycles between when the dfi_cs signal is asserted and when the associated command is driven. This field is used for CAL mode must be set to '0' or tCAL which matches the CAL mode register setting in.." newline bitfld.long 0x4 24.--25. "DFI_T_PARIN_LAT,Specifies the number of DFI PHY clock cycles between when the dfi_cs signal is asserted and when the associated dfi_parity_in signal is driven. Unit: DFI PHY clock cycles. Programming Mode: Quasi-dynamic Group 4" "0,1,2,3" newline hexmask.long.byte 0x4 16.--20. 1. "DFI_T_WRDATA_DELAY,Specifies the number of DFI clock cycles between when the dfi_wrdata_en signal is asserted and when the corresponding write data transfer is completed on the DRAM bus. This corresponds to the DFI timing parameter twrdata_delay. For.." newline hexmask.long.byte 0x4 8.--12. 1. "DFI_T_DRAM_CLK_DISABLE,Specifies the number of DFI clock cycles from the assertion of the dfi_dram_clk_disable signal on the DFI until the clock to the DRAM memory devices at the PHY-DRAM boundary maintains a low value. If the DFI clock and the memory.." newline hexmask.long.byte 0x4 0.--4. 1. "DFI_T_DRAM_CLK_ENABLE,Specifies the number of DFI clock cycles from the de-assertion of the dfi_dram_clk_disable signal on the DFI until the first valid rising edge of the clock to the DRAM memory devices at the PHY-DRAM boundary. If the DFI clock and.." group.long 0x1B4++0x7 line.long 0x0 "DFITMG2,[FREQ3] DFI Timing Register 2" hexmask.long.byte 0x0 8.--14. 1. "DFI_TPHY_RDCSLAT,specifies the number of DFI PHY clock cycles between when a read command is sent on the DFI control interface and when the associated dfi_rddata_cs signal is asserted. This corresponds to the DFI timing parameter tphy_rdcslat. Refer to.." newline hexmask.long.byte 0x0 0.--5. 1. "DFI_TPHY_WRCSLAT,Specifies the number of DFI PHY clock cycles between when a write command is sent on the DFI control interface and when the associated dfi_wrdata_cs signal is asserted. This corresponds to the DFI timing parameter tphy_wrcslat. For more.." line.long 0x4 "DFITMG3,[FREQ3] DFI Timing Register 3" hexmask.long.byte 0x4 0.--4. 1. "DFI_T_GEARDOWN_DELAY,The delay from dfi_geardown_en assertion to the time of the PHY being ready to receive commands. Refer to PHY specification for correct value. When the controller is operating in 1:2 frequency ratio mode program this to.." group.long 0x240++0x3 line.long 0x0 "ODTCFG,[FREQ3] ODT Configuration Register" hexmask.long.byte 0x0 24.--27. 1. "WR_ODT_HOLD,DFI PHY clock cycles to hold ODT for a write command. The minimum supported value is 2. Recommended values: DDR2: - BL8 - 0x5 (DDR2-400/533/667) 0x6 (DDR2-800) 0x7 (DDR2-1066) - BL4 - 0x3 (DDR2-400/533/667) 0x4 (DDR2-800) 0x5 (DDR2-1066).." newline hexmask.long.byte 0x0 16.--20. 1. "WR_ODT_DELAY,Indicates the delay in DFI PHY clock cycles from issuing a write command to setting ODT values associated with that command. ODT setting must remain constant for the entire time that DQS is driven by the uMCTL2. Recommended values: DDR2: -.." newline hexmask.long.byte 0x0 8.--11. 1. "RD_ODT_HOLD,DFI PHY clock cycles to hold ODT for a read command. The minimum supported value is 2. Recommended values: DDR2: - BL8 - 0x6 (not DDR2-1066) 0x7 (DDR2-1066) - BL4 - 0x4 (not DDR2-1066) 0x5 (DDR2-1066) DDR3: - BL8 - 0x6 DDR4: - BL8 - 5 +.." newline hexmask.long.byte 0x0 2.--6. 1. "RD_ODT_DELAY,Indicates the delay in DFI PHY clock cycles from issuing a read command to setting ODT values associated with that command. ODT setting must remain constant for the entire time that DQS is driven by the uMCTL2. Recommended values: DDR2: -.." tree.end tree.end endif tree.end tree "DISP_MUX (Display MUX)" sif (CORENAME()=="CORTEXR5F") base ad:0xF0D50000 tree "UMCTL2_REGS (uMCTL2 DDRC Registers)" group.long 0x0++0x3 line.long 0x0 "MSTR,Master Register0" bitfld.long 0x0 30.--31. "DEVICE_CONFIG,Indicates the configuration of the device used in the system. - 00 - x4 device - 01 - x8 device - 10 - x16 device - 11 - x32 device Programming Mode: Static" "x4 device,x8 device,?,?" newline bitfld.long 0x0 29. "FREQUENCY_MODE,Selects which registers are used. - 0 - Original registers - 1 - When UMCTL2_FREQUENCY_NUM=2: FREQ1 registers When UMCTL2_FREQUENCY_NUM>2: Choosen by MSTR2.target_frequency register. Programming Mode: Quasi-dynamic Group 2" "Original registers,When UMCTL2_FREQUENCY_NUM=2: FREQ1 registers" newline rbitfld.long 0x0 26.--28. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 24.--25. "ACTIVE_RANKS,Only present for multi-rank configurations. Each bit represents one rank. For two-rank configurations only bits[25:24] are present. - 1 - Populated - 0 - Unpopulated LSB is the lowest rank number. For two ranks following combinations are.." "Unpopulated,One rank,?,?" newline hexmask.long.byte 0x0 20.--23. 1. "RESERVED,Reserved" newline hexmask.long.byte 0x0 16.--19. 1. "BURST_RDWR,Indicates SDRAM burst length used: - 0001 - Burst length of 2 (only supported for mDDR) - 0010 - Burst length of 4 - 0100 - Burst length of 8 - 1000 - Burst length of 16 (only supported for mDDR LPDDR2 and LPDDR4) All other values are.." newline bitfld.long 0x0 15. "DLL_OFF_MODE,Set to: - 1 - When the uMCTL2 and DRAM has to be put in DLL-off mode for low frequency operation - 0 - To put uMCTL2 and DRAM in DLL-on mode for normal frequency operation If DDR4 CRC/parity retry is enabled.." "To put uMCTL2 and DRAM in DLL-on mode for normal..,When the uMCTL2 and DRAM has to be put in.." newline rbitfld.long 0x0 14. "RESERVED,Reserved" "0,1" newline bitfld.long 0x0 12.--13. "DATA_BUS_WIDTH,Selects proportion of DQ bus width that is used by the SDRAM. - 00 - Full DQ bus width to SDRAM - 01 - Half DQ bus width to SDRAM - 10 - Quarter DQ bus width to SDRAM - 11 - Reserved Note that half bus width mode is only supported when the.." "Full DQ bus width to SDRAM,Half DQ bus width to SDRAM,?,?" newline bitfld.long 0x0 11. "GEARDOWN_MODE,- 1 - Indicates the DRAM in geardown mode (2N) - 0 - Indicates the DRAM in normal mode (1N) This register can be changed only when the controller is in the self-refresh mode. This signal must be set the same value as MR3 bit A3. Note: -.." "Indicates the DRAM in normal mode,Indicates the DRAM in geardown mode" newline bitfld.long 0x0 10. "EN_2T_TIMING_MODE,If 1 then uMCTL2 uses 2T timing otherwise uses 1T timing. In 2T timing all command signals (except chip select) are held for 2 clocks on the SDRAM bus. Chip select is asserted on the second cycle of the command. Note: - 2T timing is.." "0,1" newline bitfld.long 0x0 9. "BURSTCHOP,When this bit is set enables burst-chop (BC4 or 8 on-the-fly) in DDR3/DDR4. Burst Chop for reads is exercised only: - In HIF configurations (UMCTL2_INCL_ARB not set) - If in full bus width mode (MSTR.data_bus_width = 00) - If.." "0,1" newline rbitfld.long 0x0 6.--8. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 5. "LPDDR4,Selects LPDDR4 SDRAM. - 1 - LPDDR4 SDRAM device in use - 0 - non-LPDDR4 device in use Present only in designs configured to support LPDDR4. Programming Mode: Static" "non-LPDDR4 device in use,LPDDR4 SDRAM device in use" newline bitfld.long 0x0 4. "DDR4,Selects DDR4 SDRAM. - 1 - DDR4 SDRAM device in use - 0 - non-DDR4 device in use Present only in designs configured to support DDR4. Programming Mode: Static" "non-DDR4 device in use,DDR4 SDRAM device in use" newline bitfld.long 0x0 3. "LPDDR3,Selects LPDDR3 SDRAM. - 1 - LPDDR3 SDRAM device in use - 0 - non-LPDDR3 device in use Present only in designs configured to support LPDDR3. Programming Mode: Static" "non-LPDDR3 device in use,LPDDR3 SDRAM device in use" newline bitfld.long 0x0 2. "LPDDR2,Selects LPDDR2 SDRAM. - 1 - LPDDR2 SDRAM device in use - 0 - non-LPDDR2 device in use Present only in designs configured to support LPDDR2. Programming Mode: Static" "non-LPDDR2 device in use,LPDDR2 SDRAM device in use" newline rbitfld.long 0x0 1. "RESERVED,Reserved" "0,1" newline bitfld.long 0x0 0. "DDR3,Selects DDR3 SDRAM. - 1 - DDR3 SDRAM device in use - 0 - non-DDR3 SDRAM device in use Present only in designs configured to support DDR3. Programming Mode: Static" "non-DDR3 SDRAM device in use,DDR3 SDRAM device in use" rgroup.long 0x4++0x3 line.long 0x0 "STAT,Operating Mode Status Register" hexmask.long.tbyte 0x0 13.--31. 1. "RESERVED,Reserved" newline bitfld.long 0x0 12. "SELFREF_CAM_NOT_EMPTY,Self-refresh with CAMs not empty. Set to 1 when self-refresh is entered but CAMs are not drained. Cleared after exiting self-refresh. Programming Mode: Static" "0,1" newline bitfld.long 0x0 10.--11. "RESERVED,Reserved" "0,1,2,3" newline bitfld.long 0x0 8.--9. "SELFREF_STATE,This indicates self-refresh or self-refresh power down state for LPDDR4. This register is used for frequency change and MRR/MRW access during self-refresh. - 00 - SDRAM is not in self-refresh - 01 - Self-refresh 1 - 10 - Self-refresh power.." "SDRAM is not in self-refresh,Self-refresh 1,?,?" newline bitfld.long 0x0 6.--7. "RESERVED,Reserved" "0,1,2,3" newline bitfld.long 0x0 4.--5. "SELFREF_TYPE,Flags if self-refresh (except LPDDR4) or SR-Powerdown (LPDDR4) is entered and if it is under automatic self-refresh control only or not. - 00 - SDRAM is not in self-refresh (except LPDDR4) or SR-Powerdown (LPDDR4). If retry is enabled by.." "SDRAM is not in self-refresh,SDRAM is in self-refresh,?,?" newline bitfld.long 0x0 3. "RESERVED,Reserved" "0,1" newline bitfld.long 0x0 0.--2. "OPERATING_MODE,This is 3-bits wide in configurations with mDDR/LPDDR2/LPDDR3/LPDDR4/DDR4 support and 2-bits in all other configurations. non-mDDR/LPDDR2/LPDDR3/LPDDR4 and non-DDR4 designs: - 00 - Init - 01 - Normal - 10 - Power-down - 11 - Self-refresh.." "Init,Normal,?,bits wide in configurations with..,?,?,?,?" group.long 0x10++0x7 line.long 0x0 "MRCTRL0,Mode Register Read/Write Control Register 0. Note: Do not enable more than one of the following fields simultaneously: - sw_init_int - pda_en - mpr_en" bitfld.long 0x0 31. "MR_WR,Setting this register bit to 1 triggers a mode register read or write operation. When the MR operation is complete the uMCTL2 automatically clears this bit. The other fields of this register must be written in a separate APB transaction before.." "0,1" newline bitfld.long 0x0 30. "PBA_MODE,Indicates whether PBA access is executed. When setting this bit to 1 along with setting pda_en to 1 uMCTL2 initiates PBA access instead of PDA access. - 0 - Per DRAM Addressability mode - 1 - Per Buffer Addressability mode The completion of PBA.." "Per DRAM Addressability mode,Per Buffer Addressability mode" newline hexmask.long.word 0x0 16.--29. 1. "RESERVED,Reserved" newline hexmask.long.byte 0x0 12.--15. 1. "MR_ADDR,Address of the mode register that is to be written to. - 0000 - MR0 - 0001 - MR1 - 0010 - MR2 - 0011 - MR3 - 0100 - MR4 - 0101 - MR5 - 0110 - MR6 - 0111 - MR7 Don't Care for LPDDR2/LPDDR3/LPDDR4 (see MRCTRL1.mr_data for mode register addressing.." newline hexmask.long.byte 0x0 6.--11. 1. "RESERVED,Reserved" newline bitfld.long 0x0 4.--5. "MR_RANK,Controls which rank is accessed by MRCTRL0.mr_wr. Normally it is desired to access all ranks so all bits must be set to 1. However for multi-rank UDIMMs/RDIMMs/LRDIMMs which implement address mirroring it might be necessary to access ranks.." "?,Select rank 0 only,Select rank 1 only,?" newline bitfld.long 0x0 3. "SW_INIT_INT,Indicates whether software intervention is allowed through MRCTRL0/MRCTRL1 before automatic SDRAM initialization routine or not. For DDR4 this bit can be used to initialize the DDR4 RCD (MR7) before automatic SDRAM initialization. For LPDDR4.." "Software intervention is not allowed,Software intervention is allowed" newline bitfld.long 0x0 2. "PDA_EN,Indicates whether the mode register operation is MRS in PDA mode or not. - 0 - MRS - 1 - MRS in Per DRAM Addressability mode Note that when pba_mode=1 PBA access is initiated instead of PDA access. Programming Mode: Dynamic" "MRS,MRS in Per DRAM Addressability mode" newline bitfld.long 0x0 1. "MPR_EN,Indicates whether the mode register operation is MRS or WR/RD for MPR (only supported for DDR4). - 0 - MRS - 1 - WR/RD for MPR Programming Mode: Dynamic" "MRS,WR/RD for MPR" newline bitfld.long 0x0 0. "MR_TYPE,Indicates whether the mode register operation is read or write. Only used for LPDDR2/LPDDR3/LPDDR4/DDR4. - 0 - Write - 1 - Read Programming Mode: Dynamic" "Write,Read" line.long 0x4 "MRCTRL1,Mode Register Read/Write Control Register 1" hexmask.long.word 0x4 18.--31. 1. "RESERVED,Reserved" newline hexmask.long.tbyte 0x4 0.--17. 1. "MR_DATA,Mode register write data for all non-LPDDR2/non-LPDDR3/non-LPDDR4 modes. For LPDDR2/LPDDR3/LPDDR4 MRCTRL1[15:0] are interpreted as: - [15:8] - MR Address - [7:0] - MR data for writes don't care for reads This is 18-bits wide in configurations.." rgroup.long 0x18++0x3 line.long 0x0 "MRSTAT,Mode Register Read/Write Status Register" hexmask.long.tbyte 0x0 9.--31. 1. "RESERVED,Reserved" newline bitfld.long 0x0 8. "PDA_DONE,The SoC might initiate a MR write operation in PDA/PBA mode only if this signal is low. This signal goes: - High when three consecutive MRS commands related to the PDA/PBA mode are issued to the SDRAM - Low when MRCTRL0.pda_en becomes 0.." "Indicates that mode register write operation..,Indicates that mode register write operation.." newline hexmask.long.byte 0x0 1.--7. 1. "RESERVED,Reserved" newline bitfld.long 0x0 0. "MR_WR_BUSY,The SoC might initiate a MR write operation only if this signal is low. This signal goes: - High in the clock after the uMCTL2 accepts the MRW/MRR request - Low when the MRW/MRR command is issued to the SDRAM It is recommended not to perform.." "Indicates that the SoC can initiate a mode..,Indicates that mode register write operation is.." group.long 0x1C++0x1F line.long 0x0 "MRCTRL2,Mode Register Read/Write Control Register 2" hexmask.long 0x0 0.--31. 1. "MR_DEVICE_SEL,Indicates the devices to be selected during the MRS that happens in PDA mode. Each bit is associated with one device. For example bit[0] corresponds to Device 0 bit[1] to Device 1 and so on. - 1 - Indicates that the MRS command must be.." line.long 0x4 "DERATEEN,Temperature Derate Enable Register" hexmask.long.tbyte 0x4 13.--31. 1. "RESERVED,Reserved" newline bitfld.long 0x4 12. "DERATE_MR4_TUF_DIS,Disables use of MR4 TUF flag (MR4[7]) bit. - 0 - Use MR4 TUF flag (MR4[7]) - 1 - Do not use MR4 TUF Flag (MR4[7]) For LPDDR4 it is recommended to set this register to 1. For LPDDR2 and LPDDR3 contact your memory vendor for.." "Use MR4 TUF flag,Do not use MR4 TUF Flag" newline rbitfld.long 0x4 11. "RESERVED,Reserved" "0,1" newline bitfld.long 0x4 8.--10. "RC_DERATE_VALUE,Derate value of tRC for LPDDR4. - 0 - Derating uses +1 - 1 - Derating uses +2 - 2 - Derating uses +3 - 3 - Derating uses +4 Present only in designs configured to support LPDDR4. The required cycles for derating can be determined by.." "Derating uses +1,Derating uses +2,Derating uses +3,Derating uses +4,?,?,?,?" newline hexmask.long.byte 0x4 4.--7. 1. "DERATE_BYTE,This bit indicates which byte of the MRR data is used for derating. The maximum valid value depends on MEMC_DRAM_TOTAL_DATA_WIDTH. Present only in designs configured to support LPDDR2/LPDDR3/LPDDR4. Programming Mode: Static" newline rbitfld.long 0x4 3. "RESERVED,Reserved" "0,1" newline bitfld.long 0x4 1.--2. "DERATE_VALUE,Derate value. - 0 - Derating uses +1 - 1 - Derating uses +2 Present only in designs configured to support LPDDR2/LPDDR3/LPDDR4. Set to 0 for all LPDDR2 speed grades as derating value of +1.875 ns is less than a core_ddrc_core_clk period. For.." "Derating uses +1,Derating uses +2,?,?" newline bitfld.long 0x4 0. "DERATE_ENABLE,Enables derating. - 0 - Timing parameter derating is disabled - 1 - Timing parameter derating is enabled using MR4 read value Present only in designs configured to support LPDDR2/LPDDR3/LPDDR4. This field must be set to '0' for.." "Timing parameter derating is disabled,Timing parameter derating is enabled using MR4.." line.long 0x8 "DERATEINT,Temperature Derate Interval Register" hexmask.long 0x8 0.--31. 1. "MR4_READ_INTERVAL,Interval between two MR4 reads used to derate the timing parameters. Present only in designs configured to support LPDDR2/LPDDR3/LPDDR4. This register must not be set to zero. Unit: DFI clock cycles. Programming Mode: Static" line.long 0xC "MSTR2,Master Register2" hexmask.long 0xC 2.--31. 1. "RESERVED,Reserved" newline bitfld.long 0xC 0.--1. "TARGET_FREQUENCY,If MSTR.frequency_mode = 1 this field specifies the target frequency. - 0 - Frequency 0/Normal - 1 - Frequency 1/FREQ1 - 2 - Frequency 2/FREQ2 - 3 - Frequency 3/FREQ3 If MSTR.frequency_mode=0 this field is ignored. Note: If the target.." "Frequency 0/Normal,Frequency 1/FREQ1,Frequency 2/FREQ2,Frequency 3/FREQ3" line.long 0x10 "DERATECTL,Temperature Derate Control Register" hexmask.long 0x10 3.--31. 1. "RESERVED,Reserved" newline bitfld.long 0x10 2. "DERATE_TEMP_LIMIT_INTR_FORCE,Interrupt force bit for derate_temp_limit_intr. Setting this field to 1 causes the derate_temp_limit_intr output pin to be asserted. At the end of the interrupt force operation the uMCTL2 automatically clears this bit." "0,1" newline bitfld.long 0x10 1. "DERATE_TEMP_LIMIT_INTR_CLR,Interrupt clear bit for derate_temp_limit_intr. At the end of the interrupt clear operation the uMCTL2 automatically clears this bit. Programming Mode: Dynamic" "0,1" newline bitfld.long 0x10 0. "DERATE_TEMP_LIMIT_INTR_EN,Interrupt enable bit for derate_temp_limit_intr output pin. - 1 - Enabled - 0 - Disabled Programming Mode: Dynamic" "Disabled,Enabled" line.long 0x14 "PWRCTL,Low Power Control Register" hexmask.long.tbyte 0x14 9.--31. 1. "RESERVED,Reserved" newline bitfld.long 0x14 8. "LPDDR4_SR_ALLOWED,Indicates whether transition from SR-PD to SR and back to SR-PD is allowed. This register field cannot be modified while PWRCTL.selfref_sw == 1. - 0 - SR-PD -> SR -> SR-PD not allowed - 1 - SR-PD -> SR -> SR-PD allowed Programming Mode:.." "SR-PD,SR-PD" newline bitfld.long 0x14 7. "DIS_CAM_DRAIN_SELFREF,Indicates whether skipping CAM draining is allowed when entering self-refresh. This register field cannot be modified while PWRCTL.selfref_sw == 1. - 0 - CAMs must be empty before entering SR - 1 - CAMs are not emptied before.." "CAMs must be empty before entering SR,CAMs are not emptied before entering SR" newline bitfld.long 0x14 6. "STAY_IN_SELFREF,Self-refresh state is an intermediate state to enter to self-refresh power down state or exit self-refresh power down state for LPDDR4. This register controls transition from the self-refresh state. - 1 - Prohibit transition from.." "Allow transition from self-refresh state,Prohibit transition from self-refresh state" newline bitfld.long 0x14 5. "SELFREF_SW,A value of 1 to this register causes system to move to self-refresh state immediately as long as it is not in INIT or DPD/MPSM operating_mode. This is referred to as Software Entry/Exit to self-refresh. - 1 - Software Entry to self-refresh -.." "Software Exit from self-refresh,Software Entry to self-refresh" newline bitfld.long 0x14 4. "MPSM_EN,When this bit is 1 the uMCTL2 puts the SDRAM into maximum power saving mode when the transaction store is empty. This register must be reset to '0' to bring uMCTL2 out of maximum power saving mode. Present only in designs configured to support.." "0,1" newline bitfld.long 0x14 3. "EN_DFI_DRAM_CLK_DISABLE,Enables the assertion of dfi_dram_clk_disable whenever a clock is not required by the SDRAM. If set to 0 dfi_dram_clk_disable is never asserted. Assertion of dfi_dram_clk_disable is as follows: In DDR2/DDR3 can only be asserted.." "0,1" newline bitfld.long 0x14 2. "DEEPPOWERDOWN_EN,When this bit is 1 uMCTL2 puts the SDRAM into deep power-down mode when the transaction store is empty. This register must be reset to '0' to bring uMCTL2 out of deep power-down mode. The controller performs automatic SDRAM.." "0,1" newline bitfld.long 0x14 1. "POWERDOWN_EN,If true then the uMCTL2 goes into power-down after a programmable number of cycles 'maximum idle clocks before power down' (PWRTMG.powerdown_to_x32). This register bit may be re-programmed during the course of normal operation. Programming.." "0,1" newline bitfld.long 0x14 0. "SELFREF_EN,If true then the uMCTL2 puts the SDRAM into self-refresh after a programmable number of cycles 'maximum idle clocks before self-refresh (PWRTMG.selfref_to_x32)'. This register bit may be re-programmed during the course of normal operation." "0,1" line.long 0x18 "PWRTMG,Low Power Timing Register" hexmask.long.byte 0x18 24.--31. 1. "RESERVED,Reserved" newline hexmask.long.byte 0x18 16.--23. 1. "SELFREF_TO_X32,After this many clocks of the DDRC command channel being idle the uMCTL2 automatically puts the SDRAM into self-refresh. The DDRC command channel is considered idle when there are no HIF commands outstanding. This must be enabled in the.." newline hexmask.long.byte 0x18 8.--15. 1. "T_DPD_X4096,Minimum deep power-down time. For mDDR value from the JEDEC specification is 0 as mDDR exits from deep power-down mode immediately after PWRCTL.deeppowerdown_en is de-asserted. For LPDDR2/LPDDR3 value from the JEDEC specification is 500us." newline rbitfld.long 0x18 5.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x18 0.--4. 1. "POWERDOWN_TO_X32,After this many clocks of the DDRC command channel being idle the uMCTL2 automatically puts the SDRAM into power-down. The DDRC command channel is considered idle when there are no HIF commands outstanding. This must be enabled in the.." line.long 0x1C "HWLPCTL,Hardware Low Power Control Register" hexmask.long.byte 0x1C 28.--31. 1. "RESERVED,Reserved" newline hexmask.long.word 0x1C 16.--27. 1. "HW_LP_IDLE_X32,Hardware idle period. The cactive_ddrc output is driven low if the DDRC command channel is idle for hw_lp_idle * 32 cycles if not in INIT or DPD/MPSM operating_mode. The DDRC command channel is considered idle when there are no HIF.." newline hexmask.long.word 0x1C 2.--15. 1. "RESERVED,Reserved" newline bitfld.long 0x1C 1. "HW_LP_EXIT_IDLE_EN,When this bit is programmed to 1 the cactive_in_ddrc pin of the DDRC can be used to exit from the automatic clock stop automatic power down or automatic self-refresh modes. Note it does not cause exit of self-refresh that was caused.." "0,1" newline bitfld.long 0x1C 0. "HW_LP_EN,Enable this bit for Hardware Low Power Interface. Programming Mode: Quasi-dynamic Group 2" "0,1" group.long 0x50++0x7 line.long 0x0 "RFSHCTL0,Refresh Control Register 0" hexmask.long.byte 0x0 24.--31. 1. "RESERVED,Reserved" newline hexmask.long.byte 0x0 20.--23. 1. "REFRESH_MARGIN,Threshold value in number of DFI clock cycles before the critical refresh or page timer expires. A critical refresh is to be issued before this threshold is reached. It is recommended that this not be changed from the default value.." newline rbitfld.long 0x0 17.--19. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x0 12.--16. 1. "REFRESH_TO_X1_X32,If the refresh timer (tRFCnom also known as tREFI) has expired at least once then a speculative refresh may be performed. A speculative refresh is a refresh performed at a time when refresh would be useful. When the SDRAM bus is idle.." newline rbitfld.long 0x0 10.--11. "RESERVED,Reserved" "0,1,2,3" newline hexmask.long.byte 0x0 4.--9. 1. "REFRESH_BURST,The programmed value + 1 is the number of refresh timeouts that is allowed to accumulate before traffic is blocked and the refreshes are forced to execute. Closing pages to perform a refresh is a one-time penalty that must be paid for each.." newline rbitfld.long 0x0 3. "RESERVED,Reserved" "0,1" newline bitfld.long 0x0 2. "PER_BANK_REFRESH,- 1 - Per bank refresh - 0 - All bank refresh Per bank refresh allows traffic to flow to other banks. Per bank refresh is not supported by all LPDDR2 devices but must be supported by all LPDDR3/LPDDR4 devices. Present only in designs.." "All bank refresh,Per bank refresh" newline rbitfld.long 0x0 0.--1. "RESERVED,Reserved" "0,1,2,3" line.long 0x4 "RFSHCTL1,Refresh Control Register 1" hexmask.long.byte 0x4 28.--31. 1. "RESERVED,Reserved" newline hexmask.long.word 0x4 16.--27. 1. "REFRESH_TIMER1_START_VALUE_X32,Refresh timer start for rank 1 (only present in multi-rank configurations). This is useful in staggering the refreshes to multiple ranks to help traffic to proceed. This is explained in Refresh Controls section of the.." newline hexmask.long.byte 0x4 12.--15. 1. "RESERVED,Reserved" newline hexmask.long.word 0x4 0.--11. 1. "REFRESH_TIMER0_START_VALUE_X32,Refresh timer start for rank 0 (only present in multi-rank configurations). This is useful in staggering the refreshes to multiple ranks to help traffic to proceed. This is explained in Refresh Controls section of the.." group.long 0x60++0xB line.long 0x0 "RFSHCTL3,Refresh Control Register 3" hexmask.long 0x0 7.--31. 1. "RESERVED,Reserved" newline bitfld.long 0x0 4.--6. "REFRESH_MODE,Indicates fine granularity refresh mode. - 000 - Fixed 1x (Normal mode) - 001 - Fixed 2x - 010 - Fixed 4x - 101 - Enable on the fly 2x (not supported) - 110 - Enable on the fly 4x (not supported) - Everything else - reserved Note: - Only.." "Fixed 1x,The on-the-fly modes are not supported in this..,This register field has effect only if a DDR4..,?,?,?,?,?" newline rbitfld.long 0x0 2.--3. "RESERVED,Reserved" "0,1,2,3" newline bitfld.long 0x0 1. "REFRESH_UPDATE_LEVEL,Toggle this signal (either from 0 to 1 or from 1 to 0) to indicate that the refresh registers have been updated. refresh_update_level must not be toggled when the DDRC is in reset (core_ddrc_rstn = 0). The refresh registers are.." "0,1" newline bitfld.long 0x0 0. "DIS_AUTO_REFRESH,When '1' disable auto-refresh generated by the uMCTL2. When auto-refresh is disabled the SoC must generate refreshes using the registers DBGCMD.rankn_refresh. When dis_auto_refresh transitions from 0 to 1 any pending refreshes are.." "0,1" line.long 0x4 "RFSHTMG,Refresh Timing Register" bitfld.long 0x4 31. "T_RFC_NOM_X1_SEL,Specifies whether the RFSHTMG.t_rfc_nom_x1_x32 and RFSHCTL0.refresh_to_x1_x32 register values are x1 or x32. - 0 - x32 register values are used - 1 - x1 register values are used This applies only when per-bank refresh is enabled.." "x32 register values are used,x1 register values are used" newline rbitfld.long 0x4 28.--30. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline hexmask.long.word 0x4 16.--27. 1. "T_RFC_NOM_X1_X32,Average time interval between refreshes per rank (Specification: 7.8us for DDR2 DDR3 and DDR4. See JEDEC specification for mDDR LPDDR2 LPDDR3 and LPDDR4). When the controller is operating in 1:1 mode set this register to.." newline bitfld.long 0x4 15. "LPDDR3_TREFBW_EN,Used only when LPDDR3 memory type is connected. Should only be changed when uMCTL2 is in reset. Specifies whether to use the tREFBW parameter (required by some LPDDR3 devices which comply with earlier versions of the LPDDR3 JEDEC.." "tREFBW parameter not used,tREFBW parameter used" newline hexmask.long.byte 0x4 10.--14. 1. "RESERVED,Reserved" newline hexmask.long.word 0x4 0.--9. 1. "T_RFC_MIN,tRFC (min): Minimum time from refresh to refresh or activate. When the controller is operating in 1:1 mode t_rfc_min must be set to RoundUp(tRFCmin/tCK). When the controller is operating in 1:2 mode t_rfc_min must be set to.." line.long 0x8 "RFSHTMG1,Refresh Timing Register1" hexmask.long.byte 0x8 24.--31. 1. "RESERVED,Reserved" newline hexmask.long.byte 0x8 16.--23. 1. "T_PBR2PBR,LPDDR4:tpbR2pbR. Per-bank refresh to Per-bank refresh different bank Time. When the controller is operating in 1:1 frequency ratio mode program this to RoundUp(tpbR2pbR/tCK). When the controller is operating in 1:2 frequency ratio mode.." newline hexmask.long.word 0x8 0.--15. 1. "RESERVED,Reserved" group.long 0x70++0x7 line.long 0x0 "ECCCFG0,ECC Configuration Register 0" bitfld.long 0x0 30.--31. "ECC_REGION_MAP_GRANU,Indicates granularity of selectable protected region. Define one region size for ECCCFG0.ecc_region_map. - 0 - 1/8 of memory spaces - 1 - 1/16 of memory spaces - 2 - 1/32 of memory spaces - 3 - 1/64 of memory spaces Programming Mode:.." "0,1,2,3" newline bitfld.long 0x0 29. "ECC_REGION_MAP_OTHER,When ECCCFG0.ecc_region_map_granu>0 there is a region which is not controlled by ecc_region_map. This register defines the region to be protected or non-protected for Inline ECC. - 0 - Non-Protected - 1 - Protected This register is.." "Non-Protected,Protected" newline rbitfld.long 0x0 27.--28. "RESERVED,Reserved" "0,1,2,3" newline bitfld.long 0x0 24.--26. "ECC_AP_ERR_THRESHOLD,Sets threshold for address parity error. ECCAPSTAT.ecc_ap_err is asserted if number of ECC errors (correctable/uncorrectable) within one burst exceeds this threshold. This register value must be less than 'Total number of ECC checks.." "0,1,2,3,4,5,6,7" newline rbitfld.long 0x0 22.--23. "RESERVED,Reserved" "0,1,2,3" newline hexmask.long.byte 0x0 16.--21. 1. "BLK_CHANNEL_IDLE_TIME_X32,Indicates the number of cycles on HIF interface with no access to protected regions which causes flush of all the block channels. In order to flush block channel uMCTL2 injects write ECC command (when there is no incoming HIF.." newline rbitfld.long 0x0 15. "RESERVED,Reserved" "0,1" newline hexmask.long.byte 0x0 8.--14. 1. "ECC_REGION_MAP,Selectable Protected Region setting. Memory space is divided to 8/16/32/64 regions which is determined by ECCCFG0.ecc_region_map_granu. Note: Highest 1/8 memory space is always ECC region. Lowest 7 regions are Selectable Protected Regions." newline bitfld.long 0x0 7. "ECC_REGION_REMAP_EN,Enables remapping ECC region feature. Only supported when inline ECC is enabled. - 0 - Disable - 1 - Enable Programming Mode: Static" "Disable,Enable" newline bitfld.long 0x0 6. "ECC_AP_EN,Enables address protection feature. Only supported when inline ECC is enabled. - 0 - Disable - 1 - Enable Programming Mode: Static" "Disable,Enable" newline rbitfld.long 0x0 5. "RESERVED,Reserved" "0,1" newline bitfld.long 0x0 4. "DIS_SCRUB,Disables ECC scrubs. Valid only when ECCCFG0.ecc_mode = 3'b100 or 3'b101 and MEMC_USE_RMW is defined. Note: Scrub is not supported in inline ECC mode and the register value is don't care. Programming Mode: Static" "0,1" newline rbitfld.long 0x0 3. "RESERVED,Reserved" "0,1" newline bitfld.long 0x0 0.--2. "ECC_MODE,ECC mode indicator. - 000 - ECC disabled - 100 - ECC enabled - SEC/DED over 1 beat - 101 - ECC enabled - Advanced ECC (Illegal value when MEMC_INLINE_ECC=1) - all other settings are reserved for future use Programming Mode: Static" "ECC disabled,?,?,?,?,?,?,?" line.long 0x4 "ECCCFG1,ECC Configuration Register 1" hexmask.long.tbyte 0x4 12.--31. 1. "RESERVED,Reserved" newline hexmask.long.byte 0x4 8.--11. 1. "ACTIVE_BLK_CHANNEL,Indicated the number of active block channels. Total number of ECC block channels are defined by MEMC_NO_OF_BLK_CHANNEL hardware parameter. This register can limit the number of available channels. For example if set to 0 only one.." newline bitfld.long 0x4 7. "BLK_CHANNEL_ACTIVE_TERM,If enabled block channel is terminated when full block write or full block read is performed (all address within block are written or read). - 0 - Disable (only for debug purpose) - 1 - Enable (default) This is debug register.." "Disable,Enable" newline rbitfld.long 0x4 6. "RESERVED,Reserved" "0,1" newline bitfld.long 0x4 5. "ECC_REGION_WASTE_LOCK,Locks the remaining waste parts of the ECC region (hole) that are not locked by ecc_region_parity_lock. - 1 - Locked; if this region is accessed error response is generated - 0 - Unlocked; this region can be accessed normally.." "Unlocked; this region can be accessed normally,Locked; if this region is accessed" newline bitfld.long 0x4 4. "ECC_REGION_PARITY_LOCK,Locks the parity section of the ECC region (hole) which is the highest system address part of the memory that stores ECC parity for protected region. - 1 - Locked; if this region is accessed error response is generated - 0 -.." "Unlocked; this region can be accessed normally,Locked; if this region is accessed" newline rbitfld.long 0x4 2.--3. "RESERVED,Reserved" "0,1,2,3" newline bitfld.long 0x4 1. "DATA_POISON_BIT,Selects whether to poison 1 or 2 bits. - if 0 -> 2-bit (uncorrectable) data poisoning - if 1 -> 1-bit (correctable) data poisoning if ECCCFG1.data_poison_en=1 Valid only when MEMC_ECC_SUPPORT==1 (SECDED ECC mode) Programming Mode:.." "?,bit" newline bitfld.long 0x4 0. "DATA_POISON_EN,Enables ECC data poisoning - introduces ECC errors on writes to address specified by the ECCPOISONADDR0/1 registers. This field must be set to 0 if ECC is disabled (ECCCFG0.ecc_mode = 0). Programming Mode: Quasi-dynamic Group 3" "0,1" rgroup.long 0x78++0x3 line.long 0x0 "ECCSTAT,SECDED ECC Status Register (Valid only in MEMC_ECC_SUPPORT==1 (SECDED ECC mode))" hexmask.long.word 0x0 17.--31. 1. "RESERVED,Reserved" newline bitfld.long 0x0 16. "ECC_UNCORRECTED_ERR,Double-bit error indicator. In sideband ECC mode 1 bit per ECC lane. When the controller is operating in 1:1 frequency ratio mode there are only two lanes so only the lower two bits are used. In inline ECC mode the register is.." "0,1" newline hexmask.long.byte 0x0 9.--15. 1. "RESERVED,Reserved" newline bitfld.long 0x0 8. "ECC_CORRECTED_ERR,Single-bit error indicator. In sideband ECC mode 1 bit per ECC lane. When the controller is operating in 1:1 frequency ratio mode there are only two lanes so only the lower two bits are used. In inline ECC mode the register is.." "0,1" newline bitfld.long 0x0 7. "RESERVED,Reserved" "0,1" newline hexmask.long.byte 0x0 0.--6. 1. "ECC_CORRECTED_BIT_NUM,Indicates the bit number corrected by single-bit ECC error. For encoding of this field see ECC section in the Architecture chapter. If more than one data lane has an error the lower data lane is selected. This register is 7 bits.." group.long 0x7C++0x3 line.long 0x0 "ECCCTL,ECC Clear Register" hexmask.long.word 0x0 19.--31. 1. "RESERVED,Reserved" newline bitfld.long 0x0 18. "ECC_AP_ERR_INTR_FORCE,Interrupt force bit for ecc_ap_err_intr. Setting this register causes the output interrupt to be asserted. The uMCTL2 automatically clears this bit. There is no interaction between functionally triggering an interrupt and forcing an.." "0,1" newline bitfld.long 0x0 17. "ECC_UNCORRECTED_ERR_INTR_FORCE,Interrupt force bit for ecc_uncorrected_err_intr. Setting this register causes the output interrupt to be asserted. The uMCTL2 automatically clears this bit. There is no interaction between functionally triggering an.." "0,1" newline bitfld.long 0x0 16. "ECC_CORRECTED_ERR_INTR_FORCE,Interrupt force bit for ecc_corrected_err_intr. Setting this register causes the output interrupt to be asserted. The uMCTL2 automatically clears this bit. There is no interaction between functionally triggering an interrupt.." "0,1" newline hexmask.long.byte 0x0 11.--15. 1. "RESERVED,Reserved" newline bitfld.long 0x0 10. "ECC_AP_ERR_INTR_EN,Interrupt enable bit for ecc_ap_err_intr. - 1 - Enabled - 0 - Disabled Programming Mode: Dynamic" "Disabled,Enabled" newline bitfld.long 0x0 9. "ECC_UNCORRECTED_ERR_INTR_EN,Interrupt enable bit for ecc_uncorrected_err_intr. - 1 - Enabled - 0 - Disabled Programming Mode: Dynamic" "Disabled,Enabled" newline bitfld.long 0x0 8. "ECC_CORRECTED_ERR_INTR_EN,Interrupt enable bit for ecc_corrected_err_intr. - 1 - Enabled - 0 - Disabled Programming Mode: Dynamic" "Disabled,Enabled" newline rbitfld.long 0x0 5.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 4. "ECC_AP_ERR_INTR_CLR,Interrupt clear bit for ecc_ap_err. If this bit is set the ECCAPSTAT.ecc_ap_err/ecc_ap_err_intr is cleared. The uMCTL2 automatically clears this bit. Programming Mode: Dynamic" "0,1" newline bitfld.long 0x0 3. "ECC_UNCORR_ERR_CNT_CLR,Setting this register bit to 1 clears the currently stored uncorrected ECC error count. The ECCERRCNT.ecc_uncorr_err_cnt register is cleared by this operation. The uMCTL2 automatically clears this bit. Programming Mode: Dynamic" "0,1" newline bitfld.long 0x0 2. "ECC_CORR_ERR_CNT_CLR,Setting this register bit to 1 clears the currently stored corrected ECC error count. The ECCERRCNT.ecc_corr_err_cnt register is cleared by this operation. The uMCTL2 automatically clears this bit. Programming Mode: Dynamic" "0,1" newline bitfld.long 0x0 1. "ECC_UNCORRECTED_ERR_CLR,Setting this register bit to 1 clears the currently stored uncorrected ECC error. The following registers are cleared: - ECCSTAT.ecc_uncorrected_err - ADVECCSTAT.advecc_uncorrected_err - ECCUSYN0 - ECCUSYN1 - ECCUSYN2 uMCTL2.." "ECCUSYN1,?" newline bitfld.long 0x0 0. "ECC_CORRECTED_ERR_CLR,Setting this register bit to 1 clears the currently stored corrected ECC error. The following registers are cleared: - ECCSTAT.ecc_corrected_err - ADVECCSTAT.advecc_corrected_err - ADVECCSTAT.advecc_num_err_symbol -.." "ECCCSYN1,ECCBITMASK2" rgroup.long 0x80++0xB line.long 0x0 "ECCERRCNT,ECC Error Counter Register" hexmask.long.word 0x0 16.--31. 1. "ECC_UNCORR_ERR_CNT,Indicates the number of uncorrectable ECC errors detected. Note that the saturation behavior of this register is different depending on the type of ECC. For advanced ECC or Inline ECC it saturates at 0xFFFF while for Side-band ECC.." newline hexmask.long.word 0x0 0.--15. 1. "ECC_CORR_ERR_CNT,Indicates the number of correctable ECC errors detected. Note that the saturation behavior of this register is different depending on the type of ECC. For advanced ECC or Inline ECC it saturates at 0xFFFF while for Side-band ECC with.." line.long 0x4 "ECCCADDR0,ECC Corrected Error Address Register 0" hexmask.long.byte 0x4 25.--31. 1. "RESERVED,Reserved" newline bitfld.long 0x4 24. "ECC_CORR_RANK,Indicates the rank number of a read resulting in a corrected ECC error. Programming Mode: Dynamic" "0,1" newline hexmask.long.byte 0x4 18.--23. 1. "RESERVED,Reserved" newline hexmask.long.tbyte 0x4 0.--17. 1. "ECC_CORR_ROW,Indicates the page/row number of a read resulting in a corrected ECC error. This is 18-bits wide in configurations with DDR4 support and 16-bits in all other configurations. Programming Mode: Dynamic" line.long 0x8 "ECCCADDR1,ECC Corrected Error Address Register 1" hexmask.long.byte 0x8 26.--31. 1. "RESERVED,Reserved" newline bitfld.long 0x8 24.--25. "ECC_CORR_BG,Indicates the bank group number of a read resulting in a corrected ECC error. Programming Mode: Dynamic" "0,1,2,3" newline hexmask.long.byte 0x8 19.--23. 1. "RESERVED,Reserved" newline bitfld.long 0x8 16.--18. "ECC_CORR_BANK,Indicates the bank number of a read resulting in a corrected ECC error. Programming Mode: Dynamic" "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x8 12.--15. 1. "RESERVED,Reserved" newline hexmask.long.word 0x8 0.--11. 1. "ECC_CORR_COL,Indicates the block number of a read resulting in a corrected ECC error (lowest bit not assigned here). Programming Mode: Dynamic" repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) rgroup.long ($2+0x8C)++0x3 line.long 0x0 "ECCCSYN$1,ECC Corrected Syndrome Register 0" hexmask.long 0x0 0.--31. 1. "ECC_CORR_SYNDROMES_31_0,Indicates the data pattern that resulted in a corrected error. For 16-bit ECC only bits [15:0] are used. Programming Mode: Dynamic" repeat.end rgroup.long 0x94++0x3 line.long 0x0 "ECCCSYN2,ECC Corrected Syndrome Register 2" hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED,Reserved" newline hexmask.long.byte 0x0 0.--7. 1. "ECC_CORR_SYNDROMES_71_64,Indicates the data pattern that resulted in a corrected error one for each ECC lane all concatenated together. This register refers to the ECC byte which is bits [71:64] for 64-bit ECC [39:32] for 32-bit ECC or [23:16] for.." repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) rgroup.long ($2+0x98)++0x3 line.long 0x0 "ECCBITMASK$1,ECC Corrected Data Bit Mask Register 0" hexmask.long 0x0 0.--31. 1. "ECC_CORR_BIT_MASK_31_0,Indicates the mask for the corrected data portion. - 1 on any bit indicates that the bit has been corrected by the ECC logic - 0 on any bit indicates that the bit has not been corrected by the ECC logic This register accumulates.." repeat.end rgroup.long 0xA0++0xB line.long 0x0 "ECCBITMASK2,ECC Corrected Data Bit Mask Register 2" hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED,Reserved" newline hexmask.long.byte 0x0 0.--7. 1. "ECC_CORR_BIT_MASK_71_64,Indicates the mask for the corrected data portion. - 1 on any bit indicates that the bit has been corrected by the ECC logic - 0 on any bit indicates that the bit has not been corrected by the ECC logic This register accumulates.." line.long 0x4 "ECCUADDR0,ECC Uncorrected Error Address Register 0" hexmask.long.byte 0x4 25.--31. 1. "RESERVED,Reserved" newline bitfld.long 0x4 24. "ECC_UNCORR_RANK,Indicates the rank number of a read resulting in an uncorrected ECC error. Programming Mode: Dynamic" "0,1" newline hexmask.long.byte 0x4 18.--23. 1. "RESERVED,Reserved" newline hexmask.long.tbyte 0x4 0.--17. 1. "ECC_UNCORR_ROW,Indicates the page/row number of a read resulting in an uncorrected ECC error. This is 18-bits wide in configurations with DDR4 support and 16-bits in all other configurations. Programming Mode: Dynamic" line.long 0x8 "ECCUADDR1,ECC Uncorrected Error Address Register 1" hexmask.long.byte 0x8 26.--31. 1. "RESERVED,Reserved" newline bitfld.long 0x8 24.--25. "ECC_UNCORR_BG,Indicates the bank group number of a read resulting in an uncorrected ECC error. Programming Mode: Dynamic" "0,1,2,3" newline hexmask.long.byte 0x8 19.--23. 1. "RESERVED,Reserved" newline bitfld.long 0x8 16.--18. "ECC_UNCORR_BANK,Indicates the bank number of a read resulting in an uncorrected ECC error. Programming Mode: Dynamic" "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x8 12.--15. 1. "RESERVED,Reserved" newline hexmask.long.word 0x8 0.--11. 1. "ECC_UNCORR_COL,Indicates the block number of a read resulting in an uncorrected ECC error (lowest bit not assigned here). Programming Mode: Dynamic" repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) rgroup.long ($2+0xAC)++0x3 line.long 0x0 "ECCUSYN$1,ECC Uncorrected Syndrome Register 0" hexmask.long 0x0 0.--31. 1. "ECC_UNCORR_SYNDROMES_31_0,Indicates the data pattern that resulted in an uncorrected error one for each ECC lane all concatenated together. For 16-bit ECC only bits [15:0] are used. Programming Mode: Dynamic" repeat.end rgroup.long 0xB4++0x3 line.long 0x0 "ECCUSYN2,ECC Uncorrected Syndrome Register 2" hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED,Reserved" newline hexmask.long.byte 0x0 0.--7. 1. "ECC_UNCORR_SYNDROMES_71_64,Indicates the data pattern that resulted in an uncorrected error one for each ECC lane all concatenated together. This register refers to the ECC byte which is bits [71:64] for 64-bit ECC [39:32] for 32-bit ECC or [23:16].." group.long 0xB8++0xF line.long 0x0 "ECCPOISONADDR0,ECC Data Poisoning Address Register 0. If a HIF write data beat matches the address specified in this register. an ECC error is introduced on that transaction (write/RMW). if ECCCFG1.data_poison_en=1." hexmask.long.byte 0x0 25.--31. 1. "RESERVED,Reserved" newline bitfld.long 0x0 24. "ECC_POISON_RANK,Indicates the rank address for ECC poisoning. Programming Mode: Static" "0,1" newline hexmask.long.word 0x0 12.--23. 1. "RESERVED,Reserved" newline hexmask.long.word 0x0 0.--11. 1. "ECC_POISON_COL,Indicates the column address for ECC poisoning. Note that this column address must be burst aligned: - In full bus width mode ecc_poison_col[2:0] must be set to 0 - In half bus width mode ecc_poison_col[3:0] must be set to 0 - In quarter.." line.long 0x4 "ECCPOISONADDR1,ECC Data Poisoning Address Register 1. If a HIF write data beat matches the address specified in this register. an ECC error is introduced on that transaction (write/RMW). if ECCCFG1.data_poison_en=1." rbitfld.long 0x4 30.--31. "RESERVED,Reserved" "0,1,2,3" newline bitfld.long 0x4 28.--29. "ECC_POISON_BG,Bank Group address for ECC poisoning. Programming Mode: Static" "0,1,2,3" newline rbitfld.long 0x4 27. "RESERVED,Reserved" "0,1" newline bitfld.long 0x4 24.--26. "ECC_POISON_BANK,Bank address for ECC poisoning. Programming Mode: Static" "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x4 18.--23. 1. "RESERVED,Reserved" newline hexmask.long.tbyte 0x4 0.--17. 1. "ECC_POISON_ROW,Row address for ECC poisoning. This is 18-bits wide in configurations with DDR4 support and 16-bits in all other configurations. Programming Mode: Static" line.long 0x8 "CRCPARCTL0,CRC Parity Control Register0. Note: Do not perform any APB access to CRCPARCTL0 within 32 pclk cycles of previous access to CRCPARCTL0. as this might lead to data loss." hexmask.long 0x8 3.--31. 1. "RESERVED,Reserved" newline bitfld.long 0x8 2. "DFI_ALERT_ERR_CNT_CLR,Indicates the clear bit for DFI alert error counter. Asserting this bit clears the DFI alert error counter CRCPARSTAT.dfi_alert_err_cnt. uMCTL2 automatically clears this bit. Programming Mode: Dynamic" "0,1" newline bitfld.long 0x8 1. "DFI_ALERT_ERR_INT_CLR,Interrupt clear bit for DFI alert error. If this bit is set the alert error interrupt on CRCPARSTAT.dfi_alert_err_int is cleared. uMCTL2 automatically clears this bit. Programming Mode: Dynamic" "0,1" newline bitfld.long 0x8 0. "DFI_ALERT_ERR_INT_EN,Interrupt enable bit for DFI alert error. If this bit is set any parity/CRC error detected on the dfi_alert_n input results in an interrupt being set on CRCPARSTAT.dfi_alert_err_int. Programming Mode: Dynamic" "0,1" line.long 0xC "CRCPARCTL1,CRC Parity Control Register1" hexmask.long.tbyte 0xC 13.--31. 1. "RESERVED,Reserved" newline bitfld.long 0xC 12. "CAPARITY_DISABLE_BEFORE_SR,If DDR4-SDRAM's CA parity is enabled by INIT6.mr5[2:0]!=0 and this register is set to 1 CA parity is automatically disabled before self-refresh entry and enabled after self-refresh exit by issuing MR5. - 1 - CA parity is.." "CA parity is not disabled before self-refresh..,CA parity is disabled before self-refresh entry" newline hexmask.long.byte 0xC 8.--11. 1. "RESERVED,Reserved" newline bitfld.long 0xC 7. "CRC_INC_DM,CRC calculation setting register. - 1 - CRC includes DM signal - 0 - CRC not includes DM signal Present only in designs configured to support DDR4. Programming Mode: Static" "CRC not includes DM signal,CRC includes DM signal" newline rbitfld.long 0xC 5.--6. "RESERVED,Reserved" "0,1,2,3" newline bitfld.long 0xC 4. "CRC_ENABLE,CRC enable Register. - 1 - Enable generation of CRC - 0 - Disable generation of CRC The setting of this register should match the CRC mode register setting in the DRAM. Programming Mode: Quasi-dynamic Group 2" "Disable generation of CRC,Enable generation of CRC" newline rbitfld.long 0xC 1.--3. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline bitfld.long 0xC 0. "PARITY_ENABLE,C/A Parity enable register. - 1 - Enable generation of C/A parity and detection of C/A parity error - 0 - Disable generation of C/A parity and disable detection of C/A parity error If RCD's parity error detection or SDRAM's parity detection.." "Disable generation of C/A parity and disable..,Enable generation of C/A parity and detection of.." rgroup.long 0xCC++0x3 line.long 0x0 "CRCPARSTAT,CRC Parity Status Register" hexmask.long.word 0x0 17.--31. 1. "RESERVED,Reserved" newline bitfld.long 0x0 16. "DFI_ALERT_ERR_INT,DFI alert error interrupt. If a parity/CRC error is detected on dfi_alert_n and the interrupt is enabled by CRCPARCTL0.dfi_alert_err_int_en this interrupt bit is set. It remains set until cleared by CRCPARCTL0.dfi_alert_err_int_clr." "0,1" newline hexmask.long.word 0x0 0.--15. 1. "DFI_ALERT_ERR_CNT,DFI alert error count. If a parity/CRC error is detected on dfi_alert_n this counter be incremented. This is independent of the setting of CRCPARCTL0.dfi_alert_err_int_en. It saturates at 0xFFFF and can be cleared by asserting.." group.long 0xD0++0xB line.long 0x0 "INIT0,SDRAM Initialization Register 0" bitfld.long 0x0 30.--31. "SKIP_DRAM_INIT,If lower bit is enabled the SDRAM initialization routine is skipped. The upper bit decides what state the controller starts up in when reset is removed. - 00 - SDRAM Initialization routine is run after power-up - 01 - SDRAM Initialization.." "SDRAM Initialization routine is run after power-up,SDRAM Initialization routine is skipped after..,?,?" newline hexmask.long.byte 0x0 26.--29. 1. "RESERVED,Reserved" newline hexmask.long.word 0x0 16.--25. 1. "POST_CKE_X1024,Indicates the number of cycles to wait after driving CKE high to start the SDRAM initialization sequence. DDR2 typically requires a 400 ns delay requiring this value to be programmed to 2 at all clock speeds. LPDDR2/LPDDR3 typically.." newline hexmask.long.byte 0x0 12.--15. 1. "RESERVED,Reserved" newline hexmask.long.word 0x0 0.--11. 1. "PRE_CKE_X1024,Indicates the number of cycles to wait after reset before driving CKE high to start the SDRAM initialization sequence. DDR2 specifications typically require this to be programmed for a delay of >= 200 us. LPDDR2/LPDDR3: tINIT1 of 100 ns.." line.long 0x4 "INIT1,SDRAM Initialization Register 1" hexmask.long.byte 0x4 25.--31. 1. "RESERVED,Reserved" newline hexmask.long.word 0x4 16.--24. 1. "DRAM_RSTN_X1024,Indicates the number of cycles to assert SDRAM reset signal during init sequence. This is only present for designs supporting DDR3 DDR4 or LPDDR4 devices. For use with a Synopsys DDR PHY this must be set to a minimum of 1. When the.." newline hexmask.long.word 0x4 4.--15. 1. "RESERVED,Reserved" newline hexmask.long.byte 0x4 0.--3. 1. "PRE_OCD_X32,Indicates the wait period before driving the OCD complete command to SDRAM. There is no known specific requirement for this; it may be set to zero. Unit: Multiples of 32 DFI clock cycles. For more information on how to program this register.." line.long 0x8 "INIT2,SDRAM Initialization Register 2" hexmask.long.word 0x8 16.--31. 1. "RESERVED,Reserved" newline hexmask.long.byte 0x8 8.--15. 1. "IDLE_AFTER_RESET_X32,Indicates the idle time after the reset command tINIT4. Present only in designs configured to support LPDDR2. When the controller is operating in 1:2 frequency ratio mode program this to JEDEC spec value divided by 2 and round it.." newline hexmask.long.byte 0x8 4.--7. 1. "RESERVED,Reserved" newline hexmask.long.byte 0x8 0.--3. 1. "MIN_STABLE_CLOCK_X1,Indicates the time to wait after the first CKE high tINIT2. Present only in designs configured to support LPDDR2/LPDDR3. LPDDR2/LPDDR3 typically requires 5 x tCK delay. When the controller is operating in 1:2 frequency ratio mode.." repeat 4. (list 0x3 0x4 0x6 0x7 )(list 0x0 0x4 0xC 0x10 ) group.long ($2+0xDC)++0x3 line.long 0x0 "INIT$1,SDRAM Initialization Register 3" hexmask.long.word 0x0 16.--31. 1. "MR,DDR2:Indicates the value to write to MR register. Bit 8 is for DLL and the setting here is ignored. The uMCTL2 sets this bit appropriately. DDR3/DDR4: Value loaded into MR0 register. mDDR: Value to write to MR register. LPDDR2/LPDDR3/LPDDR4 - Value to.." newline hexmask.long.word 0x0 0.--15. 1. "EMR,DDR2: Indicates the value to write to EMR register. Bits 9:7 are for OCD and the setting in this register is ignored. The uMCTL2 sets those bits appropriately. DDR3/DDR4: Value to write to MR1 register Set bit 7 to 0. mDDR: Value to write to EMR.." repeat.end group.long 0xE4++0x3 line.long 0x0 "INIT5,SDRAM Initialization Register 5" hexmask.long.byte 0x0 24.--31. 1. "RESERVED,Reserved" newline hexmask.long.byte 0x0 16.--23. 1. "DEV_ZQINIT_X32,ZQ initial calibration tZQINIT. Present only in designs configured to support DDR3 or DDR4 or LPDDR2/LPDDR3. DDR3 typically requires 512 SDRAM clock cycles. DDR4 requires 1024 SDRAM clock cycles. LPDDR2/LPDDR3 requires 1 us. When the.." newline hexmask.long.byte 0x0 10.--15. 1. "RESERVED,Reserved" newline hexmask.long.word 0x0 0.--9. 1. "MAX_AUTO_INIT_X1024,Indicates the maximum duration of the auto initialization tINIT5. Present only in designs configured to support LPDDR2/LPDDR3. LPDDR2/LPDDR3 typically requires 10 us. Unit: Multiples of 1024 DFI clock cycles. For more information on.." group.long 0xF0++0x7 line.long 0x0 "DIMMCTL,DIMM Control Register" hexmask.long.tbyte 0x0 15.--31. 1. "RESERVED,Reserved" newline bitfld.long 0x0 14. "RCD_B_OUTPUT_DISABLED,Disables RCD outputs to B-side DRAMs. This field is used only when the uMCTL2 disables CAL mode. This value is written to F0RC0 DA[3] before and after disabling CAL mode. It is recommended to set it to ~DIMMCTL.dimm_output_inv_en.." "Enable B outputs,Disable B outputs" newline bitfld.long 0x0 13. "RCD_A_OUTPUT_DISABLED,Disables RCD outputs to A-side DRAMs. This field is used only when the uMCTL2 disables CAL mode. This value is written to F0RC0 DA[2] before and after disabling CAL mode. It is recommended to set it to 0 except for debug. - 1 -.." "Enable A outputs,Disable A outputs" newline bitfld.long 0x0 12. "RCD_WEAK_DRIVE,Indicates the weak drive mode to be set to the RCD. This field is used only when the uMCTL2 disables CAL mode. When weak drive mode in the RCD is enabled during initialization this field must be set to 1. When RCD is not used this field.." "Disable Weak Drive mode,Enable Weak Drive mode" newline hexmask.long.byte 0x0 7.--11. 1. "RESERVED,Reserved" newline bitfld.long 0x0 6. "LRDIMM_BCOM_CMD_PROT,Protects the timing restrictions (tBCW/tMRC) between consecutive BCOM commands defined in the Data Buffer specification. When using DDR4 LRDIMM this bit must be set to 1. Otherwise this bit must be set to 0. Programming Mode: Static" "0,1" newline bitfld.long 0x0 5. "DIMM_DIS_BG_MIRRORING,Disables address mirroring for BG bits. When this is set to 1 BG0 and BG1 are NOT swapped even if Address Mirroring is enabled. This is required for DDR4 DIMMs with x16 devices. - 1 - BG0 and BG1 are NOT swapped - 0 - BG0 and BG1.." "BG0 and BG1 are swapped if address mirroring is..,BG0 and BG1 are NOT swapped" newline bitfld.long 0x0 4. "MRS_BG1_EN,Enable this field for BG1 bit of MRS command. BG1 bit of the mode register address is specified as RFU (Reserved for Future Use) and must be programmed to 0 during MRS. In case where DRAMs that do not have BG1 are attached and both the CA.." "Disabled,Enabled" newline bitfld.long 0x0 3. "MRS_A17_EN,Enable this field for A17 bit of MRS command. A17 bit of the mode register address is specified as RFU (Reserved for Future Use) and must be programmed to 0 during MRS. In case where DRAMs that do not have A17 are attached as DDR4 RDIMM/LRDIMM.." "Disabled,Enabled" newline bitfld.long 0x0 2. "DIMM_OUTPUT_INV_EN,Enables output inversion (for DDR4 RDIMM/LRDIMM implementations only). DDR4 RDIMM/LRDIMM implements the Output Inversion feature by default which means that the following address bank address and bank group bits of B-side DRAMs are.." "Do not implement output inversion for B-side DRAMs,Implement output inversion for B-side DRAMs" newline bitfld.long 0x0 1. "DIMM_ADDR_MIRR_EN,Enables address mirroring (for multi-rank UDIMM implementations and multi-rank DDR4 RDIMM/LRDIMM implementations). Some UDIMMs and DDR4 RDIMMs/LRDIMMs implement address mirroring for odd ranks which means that the following address.." "Do not implement address mirroring,For odd ranks" newline bitfld.long 0x0 0. "DIMM_STAGGER_CS_EN,Staggering enable for multi-rank accesses (for multi-rank UDIMM RDIMM and LRDIMM implementations only). This is not supported for mDDR LPDDR2 LPDDR3 or LPDDR4 SDRAMs. Note: Even if this bit is set it does not take care of software.." "Do not stagger accesses,?" line.long 0x4 "RANKCTL,Rank Control Register" hexmask.long.byte 0x4 27.--31. 1. "RESERVED,Reserved" newline bitfld.long 0x4 26. "DIFF_RANK_WR_GAP_MSB,Only present for multi-rank configurations. 1-bit extension to be used when RANKCTL.diff_rank_wr_gap field needs to be set to a value greater than 0xF. Programming Mode: Quasi-dynamic Group 2" "?,bit extension to be used when RANKCTL" newline rbitfld.long 0x4 25. "RESERVED,Reserved" "0,1" newline bitfld.long 0x4 24. "DIFF_RANK_RD_GAP_MSB,Only present for multi-rank configurations. 1-bit extension to be used when RANKCTL.diff_rank_rd_gap field needs to be set to a value greater than 0xF. Programming Mode: Quasi-dynamic Group 2" "?,bit extension to be used when RANKCTL" newline hexmask.long.byte 0x4 16.--23. 1. "RESERVED,Reserved" newline hexmask.long.byte 0x4 12.--15. 1. "MAX_RANK_WR,Only present for multi-rank configurations. Background: Writes to the same rank can be performed back-to-back. Writes to different ranks require additional gap dictated by the register RANKCTL.diff_rank_wr_gap. This is to avoid possible data.." newline hexmask.long.byte 0x4 8.--11. 1. "DIFF_RANK_WR_GAP,Only present for multi-rank configurations. Indicates the number of clocks of gap in data responses when performing consecutive writes to different ranks. This is used to switch the delays in the PHY to match the rank requirements. This.." newline hexmask.long.byte 0x4 4.--7. 1. "DIFF_RANK_RD_GAP,Only present for multi-rank configurations. Indicates the number of clocks of gap in data responses when performing consecutive reads to different ranks. This is used to switch the delays in the PHY to match the rank requirements. This.." newline hexmask.long.byte 0x4 0.--3. 1. "MAX_RANK_RD,Only present for multi-rank configurations. Background: Reads to the same rank can be performed back-to-back. Reads to different ranks require additional gap dictated by the register RANKCTL.diff_rank_rd_gap. This is to avoid possible data.." group.long 0x100++0x3F line.long 0x0 "DRAMTMG0,SDRAM Timing Register 0" rbitfld.long 0x0 31. "RESERVED,Reserved" "0,1" newline hexmask.long.byte 0x0 24.--30. 1. "WR2PRE,Specifies the minimum time between write and precharge to same bank. Specifications: WL + BL/2 + tWR = approximately 8 cycles + 15 ns = 14 clocks @400MHz and less for lower frequencies. where: - WL - Write latency - BL - Burst length. This must.." newline rbitfld.long 0x0 22.--23. "RESERVED,Reserved" "0,1,2,3" newline hexmask.long.byte 0x0 16.--21. 1. "T_FAW,tFAW - valid only when 8 or more banks(or banks x bank groups) are present. In 8-bank design at most 4 banks must be activated in a rolling window of tFAW cycles. When the controller is operating in 1:2 frequency ratio mode program this to.." newline rbitfld.long 0x0 15. "RESERVED,Reserved" "0,1" newline hexmask.long.byte 0x0 8.--14. 1. "T_RAS_MAX,tRAS(max) - Specifies the maximum time between activate and precharge to same bank. This is the maximum time that a page can be kept open Minimum value of this register is 1. Zero is invalid. When the controller is operating in 1:1 frequency.." newline rbitfld.long 0x0 6.--7. "RESERVED,Reserved" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "T_RAS_MIN,tRAS(min) - Specifies the minimum time between activate and precharge to the same bank. When the controller is operating in 1:2 frequency mode 1T mode program this to tRAS(min)/2. No rounding up. When the controller is operating in 1:2.." line.long 0x4 "DRAMTMG1,SDRAM Timing Register 1" hexmask.long.word 0x4 21.--31. 1. "RESERVED,Reserved" newline hexmask.long.byte 0x4 16.--20. 1. "T_XP,tXP - Specifies the minimum time after power-down exit to any operation. For DDR3 this must be programmed to tXPDLL if slow powerdown exit is selected in MR0[12]. If C/A parity for DDR4 is used set to (tXP+PL) instead. If LPDDR4 is selected and.." newline rbitfld.long 0x4 14.--15. "RESERVED,Reserved" "0,1,2,3" newline hexmask.long.byte 0x4 8.--13. 1. "RD2PRE,tRTP - Specifies the minimum time from read to precharge of same bank. - DDR2 - tAL + BL/2 + max(tRTP 2) - 2 - DDR3 - tAL + max (tRTP 4) - DDR4 - Max of following two equations: tAL + max (tRTP 4) or RL + BL/2 - tRP (*). - mDDR - BL/2 - LPDDR2.." newline rbitfld.long 0x4 7. "RESERVED,Reserved" "0,1" newline hexmask.long.byte 0x4 0.--6. 1. "T_RC,tRC - Specifies the minimum time between activates to same bank. When the controller is operating in 1:2 frequency ratio mode program this to (tRC/2) and round up to next integer value. Unit: DFI clock cycles. Programming Mode: Quasi-dynamic Group.." line.long 0x8 "DRAMTMG2,SDRAM Timing Register 2" rbitfld.long 0x8 30.--31. "RESERVED,Reserved" "0,1,2,3" newline hexmask.long.byte 0x8 24.--29. 1. "WRITE_LATENCY,Set this field to WL. Indicates the Time from write command to write data on SDRAM interface. This must be set to WL. For mDDR it must be set to 1. Note that depending on the PHY if using RDIMM/LRDIMM it might be necessary to adjust the.." newline rbitfld.long 0x8 22.--23. "RESERVED,Reserved" "0,1,2,3" newline hexmask.long.byte 0x8 16.--21. 1. "READ_LATENCY,Set this field to RL. Indicates the time from read command to read data on SDRAM interface. This must be set to RL. Note that depending on the PHY if using RDIMM/LRDIMM it might be necessary to adjust the value of RL to compensate for the.." newline rbitfld.long 0x8 14.--15. "RESERVED,Reserved" "0,1,2,3" newline hexmask.long.byte 0x8 8.--13. 1. "RD2WR,DDR2/3/mDDR: RL + BL/2 + 2 - WL DDR4: RL + BL/2 + 1 + WR_PREAMBLE - WL LPDDR2/LPDDR3: RL + BL/2 + RU(tDQSCKmax/tCK) + 1 - WL LPDDR4(DQ ODT is Disabled): RL + BL/2 + RU(tDQSCKmax/tCK) + WR_PREAMBLE + RD_POSTAMBLE - WL LPDDR4(DQ ODT is Enabled): RL +.." newline rbitfld.long 0x8 6.--7. "RESERVED,Reserved" "0,1,2,3" newline hexmask.long.byte 0x8 0.--5. 1. "WR2RD,DDR4: CWL + PL + BL/2 + tWTR_L LPDDR2/3/4: WL + BL/2 + tWTR + 1 Others: CWL + BL/2 + tWTR In DDR4 minimum time from write command to read command for same bank group. In others minimum time from write command to read command. Includes time for.." line.long 0xC "DRAMTMG3,SDRAM Timing Register 3" rbitfld.long 0xC 30.--31. "RESERVED,Reserved" "0,1,2,3" newline hexmask.long.word 0xC 20.--29. 1. "T_MRW,Indicates the time to wait after a mode register write or read (MRW or MRR). Present only in designs configured to support LPDDR2 LPDDR3 or LPDDR4. LPDDR2 typically requires value of 5. LPDDR3 typically requires value of 10. LPDDR4: Set this to.." newline rbitfld.long 0xC 18.--19. "RESERVED,Reserved" "0,1,2,3" newline hexmask.long.byte 0xC 12.--17. 1. "T_MRD,tMRD- Indicates the number of cycles to wait after a mode register write or read. Depending on the connected SDRAM tMRD represents: - DDR2/mDDR: Time from MRS to any command - DDR3/4: Time from MRS to MRS command - LPDDR2: not used - LPDDR3/4:.." newline rbitfld.long 0xC 10.--11. "RESERVED,Reserved" "0,1,2,3" newline hexmask.long.word 0xC 0.--9. 1. "T_MOD,tMOD - Parameter used only in DDR3 and DDR4. Indicates the number of cycles between load mode command and following non-load mode command. If C/A parity for DDR4 is used set to tMOD_PAR(tMOD+PL) instead. If CAL mode is enabled.." line.long 0x10 "DRAMTMG4,SDRAM Timing Register 4" rbitfld.long 0x10 29.--31. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x10 24.--28. 1. "T_RCD,tRCD - tAL: Indicates the minimum time from activate to read or write command to same bank. When the controller is operating in 1:2 frequency ratio mode program this to ((tRCD - tAL)/2) and round it up to the next integer value. Minimum value.." newline hexmask.long.byte 0x10 20.--23. 1. "RESERVED,Reserved" newline hexmask.long.byte 0x10 16.--19. 1. "T_CCD,DDR4: tCCD_L: This is the minimum time between two reads or two writes for same bank group. Others: tCCD: This is the minimum time between two reads or two writes. When the controller is operating in 1:2 frequency ratio mode program this to.." newline hexmask.long.byte 0x10 12.--15. 1. "RESERVED,Reserved" newline hexmask.long.byte 0x10 8.--11. 1. "T_RRD,DDR4: tRRD_L: This is the minimum time between activates from bank 'a' to bank 'b' for same bank group. Others: tRRD: Minimum time between activates from bank 'a' to bank 'b' When the controller is operating in 1:2 frequency ratio mode program.." newline rbitfld.long 0x10 5.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x10 0.--4. 1. "T_RP,tRP: Indicates the minimum time from single-bank precharge to activate of same bank. When the controller is operating in 1:1 frequency ratio mode t_rp must be set to RoundUp(tRP/tCK). When the controller is operating in 1:2 frequency ratio mode.." line.long 0x14 "DRAMTMG5,SDRAM Timing Register 5" hexmask.long.byte 0x14 28.--31. 1. "RESERVED,Reserved" newline hexmask.long.byte 0x14 24.--27. 1. "T_CKSRX,This is the time before self-refresh Exit that CK is maintained as a valid clock before issuing SRX. Specifies the clock stable time before SRX. Recommended settings: - mDDR - 1 - LPDDR2 - 2 - LPDDR3 - 2 - LPDDR4 - tCKCKEH - DDR2 - 1 - DDR3 -.." newline hexmask.long.byte 0x14 20.--23. 1. "RESERVED,Reserved" newline hexmask.long.byte 0x14 16.--19. 1. "T_CKSRE,This is the time after self-refresh Down Entry that CK is maintained as a valid clock. Specifies the clock disable delay after SRE. Recommended settings: - mDDR - 0 - LPDDR2 - 2 - LPDDR3 - 2 - LPDDR4 - tCKELCK - DDR2 - 1 - DDR3 - Max (10 ns 5.." newline rbitfld.long 0x14 14.--15. "RESERVED,Reserved" "0,1,2,3" newline hexmask.long.byte 0x14 8.--13. 1. "T_CKESR,Indicates the minimum CKE low width for self-refresh or self-refresh power down entry to exit timing in memory clock cycles. Recommended settings: - mDDR - tRFC - LPDDR2 - tCKESR - LPDDR3 - tCKESR - LPDDR4 - max(tCKE tSR) - DDR2 - tCKE - DDR3 -.." newline rbitfld.long 0x14 5.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x14 0.--4. 1. "T_CKE,Indicates the minimum number of cycles of CKE HIGH/LOW during power-down and self-refresh. - LPDDR2/LPDDR3 mode - Set this to the larger of tCKE or tCKESR - LPDDR4 mode - Set this to the larger of tCKE or tSR - Non-LPDDR2/non-LPDDR3/non-LPDDR4.." line.long 0x18 "DRAMTMG6,SDRAM Timing Register 6" hexmask.long.byte 0x18 28.--31. 1. "RESERVED,Reserved" newline hexmask.long.byte 0x18 24.--27. 1. "T_CKDPDE,This is the time after Deep Power Down Entry that CK is maintained as a valid clock. Specifies the clock disable delay after DPDE. Recommended settings: - mDDR: 0 - LPDDR2: 2 - LPDDR3: 2 When the controller is operating in 1:2 frequency ratio.." newline hexmask.long.byte 0x18 20.--23. 1. "RESERVED,Reserved" newline hexmask.long.byte 0x18 16.--19. 1. "T_CKDPDX,This is the time before Deep Power Down Exit that CK is maintained as a valid clock before issuing DPDX. Specifies the clock stable time before DPDX. Recommended settings: - mDDR - 1 - LPDDR2 - 2 - LPDDR3 - 2 When the controller is operating in.." newline hexmask.long.word 0x18 4.--15. 1. "RESERVED,Reserved" newline hexmask.long.byte 0x18 0.--3. 1. "T_CKCSX,This is the time before Clock Stop Exit that CK is maintained as a valid clock before issuing Clock Stop Exit. Specifies the clock stable time before next command after Clock Stop Exit. Recommended settings: - mDDR - 1 - LPDDR2 - tXP + 2 - LPDDR3.." line.long 0x1C "DRAMTMG7,SDRAM Timing Register 7" hexmask.long.tbyte 0x1C 12.--31. 1. "RESERVED,Reserved" newline hexmask.long.byte 0x1C 8.--11. 1. "T_CKPDE,This is the time after Power Down Entry that CK is maintained as a valid clock. Specifies the clock disable delay after PDE. Recommended settings: - mDDR - 0 - LPDDR2 - 2 - LPDDR3 - 2 - LPDDR4 - tCKELCK When using DDR2/3/4 SDRAM this register.." newline hexmask.long.byte 0x1C 4.--7. 1. "RESERVED,Reserved" newline hexmask.long.byte 0x1C 0.--3. 1. "T_CKPDX,This is the time before Power Down Exit that CK is maintained as a valid clock before issuing PDX. Specifies the clock stable time before PDX. Recommended settings: - mDDR - 0 - LPDDR2 - 2 - LPDDR3 - 2 - LPDDR4 - tCKCKEH When using DDR2/3/4 SDRAM.." line.long 0x20 "DRAMTMG8,SDRAM Timing Register 8" rbitfld.long 0x20 31. "RESERVED,Reserved" "0,1" newline hexmask.long.byte 0x20 24.--30. 1. "T_XS_FAST_X32,tXS_FAST: Exit self-refresh to ZQCL ZQCS and MRS (only CL WR RTP and Geardown mode). When the controller is operating in 1:2 frequency ratio mode program this to the previous value divided by 2 and round up to next integer value. Note:.." newline rbitfld.long 0x20 23. "RESERVED,Reserved" "0,1" newline hexmask.long.byte 0x20 16.--22. 1. "T_XS_ABORT_X32,tXS_ABORT: Exit self-refresh to commands not requiring a locked DLL in self-refresh Abort. When the controller is operating in 1:2 frequency ratio mode program this to the previous value divided by 2 and round up to next integer value." newline rbitfld.long 0x20 15. "RESERVED,Reserved" "0,1" newline hexmask.long.byte 0x20 8.--14. 1. "T_XS_DLL_X32,tXSDLL: Exit self-refresh to commands requiring a locked DLL. When the controller is operating in 1:2 frequency ratio mode program this to the previous value divided by 2 and round up to next integer value. Note: Used only for DDR2 DDR3.." newline rbitfld.long 0x20 7. "RESERVED,Reserved" "0,1" newline hexmask.long.byte 0x20 0.--6. 1. "T_XS_X32,tXS: Exit self-refresh to commands not requiring a locked DLL. When the controller is operating in 1:2 frequency ratio mode program this to the previous value divided by 2 and round up to next integer value. Note: Used only for DDR2 DDR3 and.." line.long 0x24 "DRAMTMG9,SDRAM Timing Register 9" rbitfld.long 0x24 31. "RESERVED,Reserved" "0,1" newline bitfld.long 0x24 30. "DDR4_WR_PREAMBLE,DDR4 Write preamble mode. - 0 - 1tCK preamble - 1 - 2tCK preamble Present only with MEMC_FREQ_RATIO=2. Programming Mode: Quasi-dynamic Group 2 Group 4" "0,1" newline hexmask.long.word 0x24 19.--29. 1. "RESERVED,Reserved" newline bitfld.long 0x24 16.--18. "T_CCD_S,tCCD_S: This is the minimum time between two reads or two writes for different bank group. For bank switching (from bank 'a' to bank 'b') the minimum time is this value + 1. When the controller is operating in 1:2 frequency ratio mode program.." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x24 12.--15. 1. "RESERVED,Reserved" newline hexmask.long.byte 0x24 8.--11. 1. "T_RRD_S,tRRD_S: This is the minimum time between activates from bank 'a' to bank 'b' for different bank group. When the controller is operating in 1:2 frequency ratio mode program this to (tRRD_S/2) and round it up to the next integer value. Present.." newline rbitfld.long 0x24 6.--7. "RESERVED,Reserved" "0,1,2,3" newline hexmask.long.byte 0x24 0.--5. 1. "WR2RD_S,CWL + PL + BL/2 + tWTR_S Minimum time from write command to read command for different bank group. Includes time for bus turnaround recovery times and all per-bank per-rank and global constraints. Present only in designs configured to support.." line.long 0x28 "DRAMTMG10,SDRAM Timing Register 10" hexmask.long.word 0x28 21.--31. 1. "RESERVED,Reserved" newline hexmask.long.byte 0x28 16.--20. 1. "T_SYNC_GEAR,Indicates the time between MRS command and the sync pulse time. This must be even number of clocks. For DDR4-2666 and DDR4-3200 this parameter is defined as tMOD(min)+4nCK tMOD(min) is greater of 24nCK or 15ns 15ns / .625ns = 24 Max value.." newline rbitfld.long 0x28 13.--15. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x28 8.--12. 1. "T_CMD_GEAR,Indicates a sync pulse to first valid command. For DDR4-2666 and DDR4-3200 this parameter is defined as tMOD(min) tMOD(min) is greater of 24nCK or 15ns 15ns / .625ns = 24 Max value for this register is 24 When the controller is operating in.." newline hexmask.long.byte 0x28 4.--7. 1. "RESERVED,Reserved" newline bitfld.long 0x28 2.--3. "T_GEAR_SETUP,Indicates the geardown setup time. Minimum value of this register is 1. Zero is invalid. For DDR4-2666 and DDR4-3200 this parameter is defined as 2 clks When the controller is operating in 1:2 frequency ratio mode program this to.." "0,1,2,3" newline bitfld.long 0x28 0.--1. "T_GEAR_HOLD,Indicates the geardown hold time. Minimum value of this register is 1. Zero is invalid. For DDR4-2666 and DDR4-3200 this parameter is defined as 2 clks When the controller is operating in 1:2 frequency ratio mode program this to.." "0,1,2,3" line.long 0x2C "DRAMTMG11,SDRAM Timing Register 11" rbitfld.long 0x2C 31. "RESERVED,Reserved" "0,1" newline hexmask.long.byte 0x2C 24.--30. 1. "POST_MPSM_GAP_X32,tXMPDLL: This is the minimum Exit MPSM to commands requiring a locked DLL. When the controller is operating in 1:2 frequency ratio mode program this to (tXMPDLL/2) and round it up to the next integer value. Present only in designs.." newline rbitfld.long 0x2C 21.--23. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x2C 16.--20. 1. "T_MPX_LH,tMPX_LH: This is the minimum CS_n Low hold time to CKE rising edge. When the controller is operating in 1:2 frequency ratio mode program this to RoundUp(tMPX_LH/2)+1. Present only in designs configured to support DDR4. Unit: DFI clock cycles." newline hexmask.long.byte 0x2C 10.--15. 1. "RESERVED,Reserved" newline bitfld.long 0x2C 8.--9. "T_MPX_S,tMPX_S: This is the minimum time CS setup time to CKE. When the controller is operating in 1:2 frequency ratio mode program this to (tMPX_S/2) and round it up to the next integer value. Present only in designs configured to support DDR4. Unit:.." "0,1,2,3" newline rbitfld.long 0x2C 5.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x2C 0.--4. 1. "T_CKMPE,tCKMPE: This is the minimum valid clock requirement after MPSM entry. Present only in designs configured to support DDR4. When the controller is operating in 1:2 frequency ratio mode divide the value calculated using the previous equation by 2.." line.long 0x30 "DRAMTMG12,SDRAM Timing Register 12" rbitfld.long 0x30 30.--31. "RESERVED,Reserved" "0,1,2,3" newline hexmask.long.byte 0x30 24.--29. 1. "T_WR_MPR,This bit is used only in DDR4. Cycles between MPR Write and other command. Set this to tMOD + AL (or tMOD + PL + AL if C/A parity is also used). When the controller is operating in 1:2 frequency ratio mode program this to (tWR_MPR/2) and round.." newline hexmask.long.byte 0x30 18.--23. 1. "RESERVED,Reserved" newline bitfld.long 0x30 16.--17. "T_CMDCKE,tCMDCKE: Indicates the delay from valid command to CKE input LOW. Set this to the larger of tESCKE or tCMDCKE When the controller is operating in 1:2 frequency ratio mode program this to (max(tESCKE tCMDCKE)/2) and round it up to the next.." "0,1,2,3" newline hexmask.long.word 0x30 5.--15. 1. "RESERVED,Reserved" newline hexmask.long.byte 0x30 0.--4. 1. "T_MRD_PDA,tMRD_PDA: This is the Mode Register Set command cycle time in PDA mode. When the controller is operating in 1:2 frequency ratio mode program this to (tMRD_PDA/2) and round it up to the next integer value. Unit: DFI clock cycles. Programming.." line.long 0x34 "DRAMTMG13,SDRAM Timing Register 13" rbitfld.long 0x34 31. "RESERVED,Reserved" "0,1" newline hexmask.long.byte 0x34 24.--30. 1. "ODTLOFF,LPDDR4: ODTLoff: This is the latency from CAS-2 command to ODToff reference. When the controller is operating in 1:2 frequency ratio mode program this to (ODTLoff/2) and round it up to the next integer value. Unit: DFI clock cycles. Programming.." newline rbitfld.long 0x34 22.--23. "RESERVED,Reserved" "0,1,2,3" newline hexmask.long.byte 0x34 16.--21. 1. "T_CCD_MW,LPDDR4: tCCDMW: This is the minimum time from write or masked write to masked write command for same bank. When the controller is operating in 1:2 frequency ratio mode program this to (tCCDMW/2) and round it up to the next integer value. Unit:.." newline hexmask.long.word 0x34 3.--15. 1. "RESERVED,Reserved" newline bitfld.long 0x34 0.--2. "T_PPD,LPDDR4: tPPD: This is the minimum time from precharge to precharge command. When the controller is operating in 1:2 frequency ratio mode program this to (tPPD/2) and round it up to the next integer value. Unit: DFI clock cycles. Programming Mode:.." "?,?,?,?,tPPD: This is the minimum time from precharge to..,?,?,?" line.long 0x38 "DRAMTMG14,SDRAM Timing Register 14" hexmask.long.tbyte 0x38 12.--31. 1. "RESERVED,Reserved" newline hexmask.long.word 0x38 0.--11. 1. "T_XSR,tXSR: This is the exit self-refresh to any command. When the controller is operating in 1:2 frequency ratio mode program this to the previous value divided by 2 and round up to next integer value. The value 0xfff is illegal for this register.." line.long 0x3C "DRAMTMG15,SDRAM Timing Register 15" bitfld.long 0x3C 31. "EN_DFI_LP_T_STAB,- 1 - Enable using tSTAB when exiting DFI LP. This must be set when the PHY is stopping the clock during DFI LP to save maximum power. - 0 - Disable using tSTAB when exiting DFI LP. Programming Mode: Quasi-dynamic Group 2 Group 4" "Disable using tSTAB when exiting DFI LP,Enable using tSTAB when exiting DFI LP" newline hexmask.long.tbyte 0x3C 8.--30. 1. "RESERVED,Reserved" newline hexmask.long.byte 0x3C 0.--7. 1. "T_STAB_X32,tSTAB: Stabilization time. It is required in the following two cases for DDR3/DDR4 RDIMM: - When exiting power saving mode if the clock is stopped after re-enabling it the clock must be stable for a time specified by tSTAB - In the case of.." group.long 0x180++0xB line.long 0x0 "ZQCTL0,ZQ Control Register 0" bitfld.long 0x0 31. "DIS_AUTO_ZQ,- 1 - Disable uMCTL2 generation of ZQCS/MPC(ZQ calibration) command. Register DBGCMD.zq_calib_short can be used instead to issue ZQ calibration request from APB module - 0 - Internally generate ZQCS/MPC(ZQ calibration) commands based on.." "Internally generate ZQCS/MPC,Disable uMCTL2 generation of ZQCS/MPC" newline bitfld.long 0x0 30. "DIS_SRX_ZQCL,- 1 - Disable issuing of ZQCL/MPC(ZQ calibration) command at self-refresh/SR-Powerdown exit. Only applicable when run in DDR3 or DDR4 or LPDDR2 or LPDDR3 or LPDDR4 mode - 0 - Enable issuing of ZQCL/MPC(ZQ calibration) command at.." "Enable issuing of ZQCL/MPC,Disable issuing of ZQCL/MPC" newline bitfld.long 0x0 29. "ZQ_RESISTOR_SHARED,- 1 - Denotes that ZQ resistor is shared between ranks. Means ZQinit/ZQCL/ZQCS/MPC(ZQ calibration) commands are sent to one rank at a time with tZQinit/tZQCL/tZQCS/tZQCAL/tZQLAT timing met between commands so that commands to different.." "ZQ resistor is not shared,Denotes that ZQ resistor is shared between ranks" newline bitfld.long 0x0 28. "DIS_MPSMX_ZQCL,- 1 - Disable issuing of ZQCL command at Maximum Power Saving Mode exit. Only applicable when run in DDR4 mode - 0 - Enable issuing of ZQCL command at Maximum Power Saving Mode exit. Only applicable when run in DDR4 mode This is only.." "Enable issuing of ZQCL command at Maximum Power..,Disable issuing of ZQCL command at Maximum Power.." newline rbitfld.long 0x0 27. "RESERVED,Reserved" "0,1" newline hexmask.long.word 0x0 16.--26. 1. "T_ZQ_LONG_NOP,tZQoper for DDR3/DDR4 tZQCL for LPDDR2/LPDDR3 tZQCAL for LPDDR4: Number of DFI clock cycles of NOP required after a ZQCL (ZQ calibration long)/MPC(ZQ Start) command is issued to SDRAM. When the controller is operating in 1:2 frequency.." newline hexmask.long.byte 0x0 10.--15. 1. "RESERVED,Reserved" newline hexmask.long.word 0x0 0.--9. 1. "T_ZQ_SHORT_NOP,tZQCS for DDR3/DD4/LPDDR2/LPDDR3 tZQLAT for LPDDR4: Number of DFI clock cycles of NOP required after a ZQCS (ZQ calibration short)/MPC(ZQ Latch) command is issued to SDRAM. When the controller is operating in 1:2 frequency ratio mode.." line.long 0x4 "ZQCTL1,ZQ Control Register 1" rbitfld.long 0x4 30.--31. "RESERVED,Reserved" "0,1,2,3" newline hexmask.long.word 0x4 20.--29. 1. "T_ZQ_RESET_NOP,tZQReset: Number of DFI clock cycles of NOP required after a ZQReset (ZQ calibration Reset) command is issued to SDRAM. When the controller is operating in 1:2 frequency ratio mode program this to tZQReset/2 and round it up to the next.." newline hexmask.long.tbyte 0x4 0.--19. 1. "T_ZQ_SHORT_INTERVAL_X1024,Indicates the average interval to wait between automatically issuing ZQCS (ZQ calibration short)/MPC(ZQ calibration) commands to DDR3/DDR4/LPDDR2/LPDDR3/LPDDR4 devices. Meaningless if ZQCTL0.dis_auto_zq=1. This is only present.." line.long 0x8 "ZQCTL2,ZQ Control Register 2" hexmask.long 0x8 1.--31. 1. "RESERVED,Reserved" newline bitfld.long 0x8 0. "ZQ_RESET,Setting this register bit to 1 triggers a ZQ Reset operation. When the ZQ Reset operation is complete the uMCTL2 automatically clears this bit. It is recommended NOT to set this register bit if in Init in self-refresh(except LPDDR4) or.." "0,1" rgroup.long 0x18C++0x3 line.long 0x0 "ZQSTAT,ZQ Status Register" hexmask.long 0x0 1.--31. 1. "RESERVED,Reserved" newline bitfld.long 0x0 0. "ZQ_RESET_BUSY,SoC might initiate a ZQ Reset operation only if this signal is low. This signal goes high in the clock after the uMCTL2 accepts the ZQ Reset request. It goes low when the ZQ Reset command is issued to the SDRAM and the associated NOP period.." "Indicates that the SoC can initiate a ZQ Reset..,Indicates that ZQ Reset operation is in progress" group.long 0x190++0x1B line.long 0x0 "DFITMG0,DFI Timing Register 0" rbitfld.long 0x0 29.--31. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x0 24.--28. 1. "DFI_T_CTRL_DELAY,Specifies the number of DFI clock cycles after an assertion or de-assertion of the DFI control signals that the control signals at the PHY-DRAM interface reflect the assertion or de-assertion. If the DFI clock and the memory clock are.." newline bitfld.long 0x0 23. "DFI_RDDATA_USE_DFI_PHY_CLK,Defines whether dfi_rddata_en/dfi_rddata/dfi_rddata_valid is generated using HDR (DFI clock) or SDR (DFI PHY clock) values. Selects whether value in DFITMG0.dfi_t_rddata_en is in terms of HDR (DFI clock) or SDR (DFI PHY clock).." "Else,?" newline hexmask.long.byte 0x0 16.--22. 1. "DFI_T_RDDATA_EN,Time from the assertion of a read command on the DFI interface to the assertion of the dfi_rddata_en signal. Refer to PHY specification for correct value. This corresponds to the DFI parameter trddata_en. Note that depending on the PHY.." newline bitfld.long 0x0 15. "DFI_WRDATA_USE_DFI_PHY_CLK,Defines whether dfi_wrdata_en/dfi_wrdata/dfi_wrdata_mask is generated using HDR (DFI clock) or SDR (DFI PHY clock) values. Selects whether value in DFITMG0.dfi_tphy_wrlat is in terms of HDR (DFI clock) or SDR (DFI PHY clock).." "Else,?" newline rbitfld.long 0x0 14. "RESERVED,Reserved" "0,1" newline hexmask.long.byte 0x0 8.--13. 1. "DFI_TPHY_WRDATA,Specifies the number of clock cycles between when dfi_wrdata_en is asserted to when the associated write data is driven on the dfi_wrdata signal. This corresponds to the DFI timing parameter tphy_wrdata. For more information on correct.." newline rbitfld.long 0x0 6.--7. "RESERVED,Reserved" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "DFI_TPHY_WRLAT,Write latency. Number of clocks from the write command to write data enable (dfi_wrdata_en). This corresponds to the DFI timing parameter tphy_wrlat. Refer to PHY specification for correct value.Note that depending on the PHY if using.." line.long 0x4 "DFITMG1,DFI Timing Register 1" hexmask.long.byte 0x4 28.--31. 1. "DFI_T_CMD_LAT,Specifies the number of DFI PHY clock cycles between when the dfi_cs signal is asserted and when the associated command is driven. This field is used for CAL mode must be set to '0' or tCAL which matches the CAL mode register setting in.." newline rbitfld.long 0x4 26.--27. "RESERVED,Reserved" "0,1,2,3" newline bitfld.long 0x4 24.--25. "DFI_T_PARIN_LAT,Specifies the number of DFI PHY clock cycles between when the dfi_cs signal is asserted and when the associated dfi_parity_in signal is driven. Unit: DFI PHY clock cycles. Programming Mode: Quasi-dynamic Group 4" "0,1,2,3" newline rbitfld.long 0x4 21.--23. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x4 16.--20. 1. "DFI_T_WRDATA_DELAY,Specifies the number of DFI clock cycles between when the dfi_wrdata_en signal is asserted and when the corresponding write data transfer is completed on the DRAM bus. This corresponds to the DFI timing parameter twrdata_delay. For.." newline rbitfld.long 0x4 13.--15. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x4 8.--12. 1. "DFI_T_DRAM_CLK_DISABLE,Specifies the number of DFI clock cycles from the assertion of the dfi_dram_clk_disable signal on the DFI until the clock to the DRAM memory devices at the PHY-DRAM boundary maintains a low value. If the DFI clock and the memory.." newline rbitfld.long 0x4 5.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x4 0.--4. 1. "DFI_T_DRAM_CLK_ENABLE,Specifies the number of DFI clock cycles from the de-assertion of the dfi_dram_clk_disable signal on the DFI until the first valid rising edge of the clock to the DRAM memory devices at the PHY-DRAM boundary. If the DFI clock and.." line.long 0x8 "DFILPCFG0,DFI Low Power Configuration Register 0" rbitfld.long 0x8 29.--31. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x8 24.--28. 1. "DFI_TLP_RESP,Indicates the setting in DFI clock cycles for DFI's tlp_resp time. Same value is used for both Power Down self-refresh Deep Power Down and Maximum Power Saving modes. For more information on recommended values see PHY databook Unit: DFI.." newline hexmask.long.byte 0x8 20.--23. 1. "DFI_LP_WAKEUP_DPD,Indicates the value in DFI clock cycles to drive on dfi_lp_wakeup signal when Deep Power Down mode is entered. Determines the DFI's tlp_wakeup time: - 0x0 - 16 cycles - 0x1 - 32 cycles - 0x2 - 64 cycles - 0x3 - 128 cycles - 0x4 - 256.." newline rbitfld.long 0x8 17.--19. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 16. "DFI_LP_EN_DPD,Enables DFI Low Power interface handshaking during Deep Power Down Entry/Exit. - 0 - Disabled - 1 - Enabled This is only present for designs supporting mDDR or LPDDR2/LPDDR3 devices. Programming Mode: Static" "Disabled,Enabled" newline hexmask.long.byte 0x8 12.--15. 1. "DFI_LP_WAKEUP_SR,Indicates the value in DFI clock cycles to drive on dfi_lp_wakeup signal when self-refresh mode is entered. Determines the DFI's tlp_wakeup time: - 0x0 - 16 cycles - 0x1 - 32 cycles - 0x2 - 64 cycles - 0x3 - 128 cycles - 0x4 - 256 cycles.." newline rbitfld.long 0x8 9.--11. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 8. "DFI_LP_EN_SR,Enables DFI Low Power interface handshaking during self-refresh Entry/Exit. - 0 - Disabled - 1 - Enabled Programming Mode: Static" "Disabled,Enabled" newline hexmask.long.byte 0x8 4.--7. 1. "DFI_LP_WAKEUP_PD,Indicates the value in DFI clock cycles to drive on dfi_lp_wakeup signal when Power Down mode is entered. Determines the DFI's tlp_wakeup time: - 0x0 - 16 cycles - 0x1 - 32 cycles - 0x2 - 64 cycles - 0x3 - 128 cycles - 0x4 - 256 cycles -.." newline rbitfld.long 0x8 1.--3. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 0. "DFI_LP_EN_PD,Enables DFI Low Power interface handshaking during Power Down Entry/Exit. - 0 - Disabled - 1 - Enabled Programming Mode: Static" "Disabled,Enabled" line.long 0xC "DFILPCFG1,DFI Low Power Configuration Register 1" hexmask.long.tbyte 0xC 8.--31. 1. "RESERVED,Reserved" newline hexmask.long.byte 0xC 4.--7. 1. "DFI_LP_WAKEUP_MPSM,Indicates the value in DFI clock cycles to drive on dfi_lp_wakeup signal when Maximum Power Saving Mode is entered. Determines the DFI's tlp_wakeup time: - 0x0 - 16 cycles - 0x1 - 32 cycles - 0x2 - 64 cycles - 0x3 - 128 cycles - 0x4 -.." newline rbitfld.long 0xC 1.--3. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline bitfld.long 0xC 0. "DFI_LP_EN_MPSM,Enables DFI Low Power interface handshaking during Maximum Power Saving Mode Entry/Exit. - 0 - Disabled - 1 - Enabled This is only present for designs supporting DDR4 devices. Programming Mode: Static" "Disabled,Enabled" line.long 0x10 "DFIUPD0,DFI Update Register 0" bitfld.long 0x10 31. "DIS_AUTO_CTRLUPD,When '1' disable the automatic dfi_ctrlupd_req generation by the uMCTL2. The controller must issue the dfi_ctrlupd_req signal using register DBGCMD.ctrlupd. When '0' uMCTL2 issues dfi_ctrlupd_req periodically. Programming Mode:.." "0,1" newline bitfld.long 0x10 30. "DIS_AUTO_CTRLUPD_SRX,When '1' disable the automatic dfi_ctrlupd_req generation by the uMCTL2 at self-refresh exit. When '0' uMCTL2 issues a dfi_ctrlupd_req before or after exiting self-refresh depending on DFIUPD0.ctrlupd_pre_srx. Programming Mode:.." "0,1" newline bitfld.long 0x10 29. "CTRLUPD_PRE_SRX,Selects dfi_ctrlupd_req requirements at SRX: - 0 - Send ctrlupd after SRX - 1 - Send ctrlupd before SRX If DFIUPD0.dis_auto_ctrlupd_srx=1 this register has no impact because no dfi_ctrlupd_req is issued when SRX. Programming Mode: Static" "Send ctrlupd after SRX,Send ctrlupd before SRX" newline rbitfld.long 0x10 26.--28. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline hexmask.long.word 0x10 16.--25. 1. "DFI_T_CTRLUP_MAX,Specifies the maximum number of DFI clock cycles that the dfi_ctrlupd_req signal can assert. Lowest value to assign to this variable is 0x40. Unit: DFI clock cycles. Programming Mode: Static" newline hexmask.long.byte 0x10 10.--15. 1. "RESERVED,Reserved" newline hexmask.long.word 0x10 0.--9. 1. "DFI_T_CTRLUP_MIN,Specifies the minimum number of DFI clock cycles that the dfi_ctrlupd_req signal must be asserted. The uMCTL2 expects the PHY to respond within this time. If the PHY does not respond the uMCTL2 de-asserts dfi_ctrlupd_req after.." line.long 0x14 "DFIUPD1,DFI Update Register 1" hexmask.long.byte 0x14 24.--31. 1. "RESERVED,Reserved" newline hexmask.long.byte 0x14 16.--23. 1. "DFI_T_CTRLUPD_INTERVAL_MIN_X1024,This is the minimum amount of time between uMCTL2 initiated DFI update requests (which is executed whenever the uMCTL2 is idle). Set this number higher to reduce the frequency of update requests which can have a small.." newline hexmask.long.byte 0x14 8.--15. 1. "RESERVED,Reserved" newline hexmask.long.byte 0x14 0.--7. 1. "DFI_T_CTRLUPD_INTERVAL_MAX_X1024,This is the maximum amount of time between uMCTL2 initiated DFI update requests. This timer resets with each update request; when the timer expires dfi_ctrlupd_req is sent and traffic is blocked until the dfi_ctrlupd_ackx.." line.long 0x18 "DFIUPD2,DFI Update Register 2" bitfld.long 0x18 31. "DFI_PHYUPD_EN,Enables the support for acknowledging PHY-initiated updates: - 0 - Disabled - 1 - Enabled Programming Mode: Static" "Disabled,Enabled" newline hexmask.long 0x18 0.--30. 1. "RESERVED,Reserved" group.long 0x1B0++0xB line.long 0x0 "DFIMISC,DFI Miscellaneous Control Register" hexmask.long.tbyte 0x0 13.--31. 1. "RESERVED,Reserved" newline hexmask.long.byte 0x0 8.--12. 1. "DFI_FREQUENCY,Indicates the operating frequency of the system. The number of supported frequencies and the mapping of signal values to clock frequencies are defined by the PHY. Programming Mode: Quasi-dynamic Group 1" newline bitfld.long 0x0 7. "LP_OPTIMIZED_WRITE,If this bit is 1 LPDDR4 write DQ is set to 8'hF8 if masked write with enabling DBI; otherwise that value is set to 8'hFF. Programming Mode: Quasi-dynamic Group 3" "0,1" newline bitfld.long 0x0 6. "DIS_DYN_ADR_TRI,If this bit is 1 PHY specific Dynamic Tristating which is a specific feature to certain Synopsys PHYs is disabled. If this bit is 0 a special IDLE command is issued on the DFI while dfi_cs is inactive state so that the PHY can detect.." "?,phase 0 and 1) dfi_we_n= 1" newline bitfld.long 0x0 5. "DFI_INIT_START,PHY init start request signal.When asserted it triggers the PHY init start request. Programming Mode: Quasi-dynamic Group 3" "0,1" newline bitfld.long 0x0 4. "CTL_IDLE_EN,Enables support of ctl_idle signal which is non-DFI related pin specific to certain Synopsys PHYs. For more information on ctl_idle functionality see signal description of ctl_idle signal. Programming Mode: Static" "0,1" newline rbitfld.long 0x0 3. "RESERVED,Reserved" "0,1" newline bitfld.long 0x0 2. "DFI_DATA_CS_POLARITY,Defines polarity of dfi_wrdata_cs and dfi_rddata_cs signals. - 0 - Signals are active low - 1 - Signals are active high Programming Mode: Static" "Signals are active low,Signals are active high" newline bitfld.long 0x0 1. "PHY_DBI_MODE,DBI implemented in DDRC or PHY. - 0 - DDRC implements DBI functionality - 1 - PHY implements DBI functionality Present only in designs configured to support DDR4 and LPDDR4. Programming Mode: Static" "DDRC implements DBI functionality,PHY implements DBI functionality" newline bitfld.long 0x0 0. "DFI_INIT_COMPLETE_EN,PHY initialization complete enable signal. When asserted the dfi_init_complete signal can be used to trigger SDRAM initialisation Programming Mode: Quasi-dynamic Group 3" "0,1" line.long 0x4 "DFITMG2,DFI Timing Register 2" hexmask.long.tbyte 0x4 15.--31. 1. "RESERVED,Reserved" newline hexmask.long.byte 0x4 8.--14. 1. "DFI_TPHY_RDCSLAT,specifies the number of DFI PHY clock cycles between when a read command is sent on the DFI control interface and when the associated dfi_rddata_cs signal is asserted. This corresponds to the DFI timing parameter tphy_rdcslat. Refer to.." newline rbitfld.long 0x4 6.--7. "RESERVED,Reserved" "0,1,2,3" newline hexmask.long.byte 0x4 0.--5. 1. "DFI_TPHY_WRCSLAT,Specifies the number of DFI PHY clock cycles between when a write command is sent on the DFI control interface and when the associated dfi_wrdata_cs signal is asserted. This corresponds to the DFI timing parameter tphy_wrcslat. For more.." line.long 0x8 "DFITMG3,DFI Timing Register 3" hexmask.long 0x8 5.--31. 1. "RESERVED,Reserved" newline hexmask.long.byte 0x8 0.--4. 1. "DFI_T_GEARDOWN_DELAY,The delay from dfi_geardown_en assertion to the time of the PHY being ready to receive commands. Refer to PHY specification for correct value. When the controller is operating in 1:2 frequency ratio mode program this to.." rgroup.long 0x1BC++0x3 line.long 0x0 "DFISTAT,DFI Status Register" hexmask.long 0x0 2.--31. 1. "RESERVED,Reserved" newline bitfld.long 0x0 1. "DFI_LP_ACK,Stores the value of the dfi_lp_ack input to the controller. Programming Mode: Dynamic" "0,1" newline bitfld.long 0x0 0. "DFI_INIT_COMPLETE,This a status flag register which announces when the DFI initialization has been completed. The DFI INIT triggered by dfi_init_start signal and then the dfi_init_complete flag is polled to know when the initialization is done." "0,1" group.long 0x1C0++0x7 line.long 0x0 "DBICTL,DM/DBI Control Register" hexmask.long 0x0 3.--31. 1. "RESERVED,Reserved" newline bitfld.long 0x0 2. "RD_DBI_EN,Read DBI enable signal in DDRC. - 0 - Read DBI is disabled - 1 - Read DBI is enabled This signal must be set the same value as DRAM's mode register. - DDR4 - MR5 bit A12. When x4 devices are used this signal must be set to 0 - LPDDR4 - MR3[6].." "LPDDR4,Read DBI is enabled" newline bitfld.long 0x0 1. "WR_DBI_EN,Write DBI enable signal in DDRC. - 0 - Write DBI is disabled - 1 - Write DBI is enabled This signal must be set the same value as DRAM's mode register. - DDR4 - MR5 bit A11. When x4 devices are used this signal must be set to 0 - LPDDR4 -.." "LPDDR4,Write DBI is enabled" newline bitfld.long 0x0 0. "DM_EN,Indicates the DM enable signal in DDRC. - 0 - DM is disabled - 1 - DM is enabled This signal must be set the same logical value as DRAM's mode register. - DDR4 - Set this to same value as MR5 bit A10. When x4 devices are used this signal must be.." "LPDDR4,DM is enabled" line.long 0x4 "DFIPHYMSTR,DFI PHY Master" hexmask.long 0x4 1.--31. 1. "RESERVED,Reserved" newline bitfld.long 0x4 0. "DFI_PHYMSTR_EN,Enables the PHY Master Interface: - 0 - Disabled - 1 - Enabled Programming Mode: Static" "Disabled,Enabled" group.long 0x200++0x13 line.long 0x0 "ADDRMAP0,Address Map Register 0" hexmask.long 0x0 5.--31. 1. "RESERVED,Reserved" newline hexmask.long.byte 0x0 0.--4. 1. "ADDRMAP_CS_BIT0,Selects the HIF address bit used as rank address bit 0. Valid Range: 0 to 29 and 31 Internal Base: 6 The selected HIF address bit is determined by adding the internal base to the value of this field. If unused set to 31 and then rank.." line.long 0x4 "ADDRMAP1,Address Map Register 1" hexmask.long.word 0x4 22.--31. 1. "RESERVED,Reserved" newline hexmask.long.byte 0x4 16.--21. 1. "ADDRMAP_BANK_B2,Selects the HIF address bit used as bank address bit 2. Valid Range: 0 to 31 and 63 Internal Base: 4 The selected HIF address bit is determined by adding the internal base to the value of this field. If unused set to 63 and then bank.." newline rbitfld.long 0x4 14.--15. "RESERVED,Reserved" "0,1,2,3" newline hexmask.long.byte 0x4 8.--13. 1. "ADDRMAP_BANK_B1,Selects the HIF address bits used as bank address bit 1. Valid Range: 0 to 32 and 63 Internal Base: 3 The selected HIF address bit for each of the bank address bits is determined by adding the internal base to the value of this field. If.." newline rbitfld.long 0x4 6.--7. "RESERVED,Reserved" "0,1,2,3" newline hexmask.long.byte 0x4 0.--5. 1. "ADDRMAP_BANK_B0,Selects the HIF address bits used as bank address bit 0. Valid Range: 0 to 32 and 63 Internal Base: 2 The selected HIF address bit for each of the bank address bits is determined by adding the internal base to the value of this field. If.." line.long 0x8 "ADDRMAP2,Address Map Register 2" hexmask.long.byte 0x8 28.--31. 1. "RESERVED,Reserved" newline hexmask.long.byte 0x8 24.--27. 1. "ADDRMAP_COL_B5,- Full bus width mode - Selects the HIF address bit used as column address bit 5 - Half bus width mode - Selects the HIF address bit used as column address bit 6 - Quarter bus width mode - Selects the HIF address bit used as column address.." newline hexmask.long.byte 0x8 20.--23. 1. "RESERVED,Reserved" newline hexmask.long.byte 0x8 16.--19. 1. "ADDRMAP_COL_B4,- Full bus width mode - Selects the HIF address bit used as column address bit 4 - Half bus width mode - Selects the HIF address bit used as column address bit 5 - Quarter bus width mode - Selects the HIF address bit used as column address.." newline rbitfld.long 0x8 13.--15. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x8 8.--12. 1. "ADDRMAP_COL_B3,- Full bus width mode - Selects the HIF address bit used as column address bit 3 - Half bus width mode - Selects the HIF address bit used as column address bit 4 - Quarter bus width mode - Selects the HIF address bit used as column address.." newline hexmask.long.byte 0x8 4.--7. 1. "RESERVED,Reserved" newline hexmask.long.byte 0x8 0.--3. 1. "ADDRMAP_COL_B2,- Full bus width mode - Selects the HIF address bit used as column address bit 2 - Half bus width mode - Selects the HIF address bit used as column address bit 3 - Quarter bus width mode - Selects the HIF address bit used as column address.." line.long 0xC "ADDRMAP3,Address Map Register 3" rbitfld.long 0xC 29.--31. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0xC 24.--28. 1. "ADDRMAP_COL_B9,- Full bus width mode - Selects the HIF address bit used as column address bit 9 - Half bus width mode - Selects the HIF address bit used as column address bit 11 (10 in LPDDR2/LPDDR3 mode) - Quarter bus width mode - Selects the HIF.." newline rbitfld.long 0xC 21.--23. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0xC 16.--20. 1. "ADDRMAP_COL_B8,- Full bus width mode - Selects the HIF address bit used as column address bit 8 - Half bus width mode - Selects the HIF address bit used as column address bit 9 - Quarter bus width mode - Selects the HIF address bit used as column address.." newline rbitfld.long 0xC 13.--15. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0xC 8.--12. 1. "ADDRMAP_COL_B7,- Full bus width mode - Selects the HIF address bit used as column address bit 7 - Half bus width mode - Selects the HIF address bit used as column address bit 8 - Quarter bus width mode - Selects the HIF address bit used as column address.." newline rbitfld.long 0xC 5.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0xC 0.--4. 1. "ADDRMAP_COL_B6,- Full bus width mode - Selects the HIF address bit used as column address bit 6. - Half bus width mode - Selects the HIF address bit used as column address bit 7. - Quarter bus width mode - Selects the HIF address bit used as column.." line.long 0x10 "ADDRMAP4,Address Map Register 4" bitfld.long 0x10 31. "COL_ADDR_SHIFT,The register provides a capability to map column address to lower HIF address in specific cases required by inline ECC configuration. - If it is 1 internal base of all the column address can be -2 to make mapping range of column address.." "0,1" newline hexmask.long.tbyte 0x10 13.--30. 1. "RESERVED,Reserved" newline hexmask.long.byte 0x10 8.--12. 1. "ADDRMAP_COL_B11,- Full bus width mode - Selects the HIF address bit used as column address bit 13 (11 in LPDDR2/LPDDR3 mode) - Half bus width mode - UNUSED. See later in this description for value you need to set to make it unused - Quarter bus width.." newline rbitfld.long 0x10 5.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x10 0.--4. 1. "ADDRMAP_COL_B10,- Full bus width mode: Selects the HIF address bit used as column address bit 11 (10 in LPDDR2/LPDDR3 mode) - Half bus width mode: Selects the HIF address bit used as column address bit 13 (11 in LPDDR2/LPDDR3 mode) - Quarter bus width.." repeat 3. (list 0x5 0x9 0xA )(list 0x0 0x10 0x14 ) group.long ($2+0x214)++0x3 line.long 0x0 "ADDRMAP$1,Address Map Register 5" hexmask.long.byte 0x0 28.--31. 1. "RESERVED,Reserved" newline hexmask.long.byte 0x0 24.--27. 1. "ADDRMAP_ROW_B11,Selects the HIF address bit used as row address bit 11. Valid Range: 0 to 11 and 15 Internal Base: 17 The selected HIF address bit is determined by adding the internal base to the value of this field. If unused set to 15 and then row.." newline hexmask.long.byte 0x0 20.--23. 1. "RESERVED,Reserved" newline hexmask.long.byte 0x0 16.--19. 1. "ADDRMAP_ROW_B2_10,Selects the HIF address bits used as row address bits 2 to 10. Valid Range: 0 to 11 and 15 Internal Base: 8 (for row address bit 2) 9 (for row address bit 3) 10 (for row address bit 4) and so on increasing to 16 (for row address bit.." newline hexmask.long.byte 0x0 12.--15. 1. "RESERVED,Reserved" newline hexmask.long.byte 0x0 8.--11. 1. "ADDRMAP_ROW_B1,Selects the HIF address bits used as row address bit 1. Valid Range: 0 to 11 Internal Base: 7 The selected HIF address bit for each of the row address bits is determined by adding the internal base to the value of this field. Programming.." newline hexmask.long.byte 0x0 4.--7. 1. "RESERVED,Reserved" newline hexmask.long.byte 0x0 0.--3. 1. "ADDRMAP_ROW_B0,Selects the HIF address bits used as row address bit 0. Valid Range: 0 to 11 Internal Base: 6 The selected HIF address bit for each of the row address bits is determined by adding the internal base to the value of this field. Programming.." repeat.end group.long 0x218++0xB line.long 0x0 "ADDRMAP6,Address Map Register 6" bitfld.long 0x0 31. "LPDDR3_6GB_12GB,Set this to 1 if there is an LPDDR3 SDRAM 6Gb or 12Gb device in use. - 1 - LPDDR3 SDRAM 6Gb/12Gb device in use. Every address having row[14:13]==2'b11 is considered as invalid - 0 - non-LPDDR3 6Gb/12Gb device in use. All addresses are.." "non-LPDDR3 6Gb/12Gb device in use,LPDDR3 SDRAM 6Gb/12Gb device in use" newline bitfld.long 0x0 29.--30. "LPDDR4_3GB_6GB_12GB,Indicates what type of LPDDR4 SDRAM device is in use. Here the density size is per channel. - 2'b00 - No LPDDR4 SDRAM 3Gb/6Gb/12Gb device in use. All addresses are valid - 2'b01 - LPDDR4 SDRAM 3Gb device with x16 mode in use. Every.." "No LPDDR4 SDRAM 3Gb/6Gb/12Gb device in use,LPDDR4 SDRAM 3Gb device with x16 mode in use,LPDDR4 SDRAM 6Gb device with x16 mode or 3Gb..,LPDDR4 SDRAM 12Gb device with x16 mode or 6Gb.." newline rbitfld.long 0x0 28. "RESERVED,Reserved" "0,1" newline hexmask.long.byte 0x0 24.--27. 1. "ADDRMAP_ROW_B15,Selects the HIF address bit used as row address bit 15. Valid Range: 0 to 11 and 15 Internal Base: 21 The selected HIF address bit is determined by adding the internal base to the value of this field. If unused set to 15 and then row.." newline hexmask.long.byte 0x0 20.--23. 1. "RESERVED,Reserved" newline hexmask.long.byte 0x0 16.--19. 1. "ADDRMAP_ROW_B14,Selects the HIF address bit used as row address bit 14. Valid Range: 0 to 11 and 15 Internal Base: 20 The selected HIF address bit is determined by adding the internal base to the value of this field. If unused set to 15 and then row.." newline hexmask.long.byte 0x0 12.--15. 1. "RESERVED,Reserved" newline hexmask.long.byte 0x0 8.--11. 1. "ADDRMAP_ROW_B13,Selects the HIF address bit used as row address bit 13. Valid Range: 0 to 11 and 15 Internal Base: 19 The selected HIF address bit is determined by adding the internal base to the value of this field. If unused set to 15 and then row.." newline hexmask.long.byte 0x0 4.--7. 1. "RESERVED,Reserved" newline hexmask.long.byte 0x0 0.--3. 1. "ADDRMAP_ROW_B12,Selects the HIF address bit used as row address bit 12. Valid Range: 0 to 11 and 15 Internal Base: 18 The selected HIF address bit is determined by adding the internal base to the value of this field. If unused set to 15 and then row.." line.long 0x4 "ADDRMAP7,Address Map Register 7" hexmask.long.tbyte 0x4 12.--31. 1. "RESERVED,Reserved" newline hexmask.long.byte 0x4 8.--11. 1. "ADDRMAP_ROW_B17,Selects the HIF address bit used as row address bit 17. Valid Range: 0 to 11 and 15 Internal Base: 23 The selected HIF address bit is determined by adding the internal base to the value of this field. If unused set to 15 and then row.." newline hexmask.long.byte 0x4 4.--7. 1. "RESERVED,Reserved" newline hexmask.long.byte 0x4 0.--3. 1. "ADDRMAP_ROW_B16,Selects the HIF address bit used as row address bit 16. Valid Range: 0 to 11 and 15 Internal Base: 22 The selected HIF address bit is determined by adding the internal base to the value of this field. If unused set to 15 and then row.." line.long 0x8 "ADDRMAP8,Address Map Register 8" hexmask.long.tbyte 0x8 14.--31. 1. "RESERVED,Reserved" newline hexmask.long.byte 0x8 8.--13. 1. "ADDRMAP_BG_B1,Selects the HIF address bits used as bank group address bit 1. Valid Range: 0 to 32 and 63 Internal Base: 3 The selected HIF address bit for each of the bank group address bits is determined by adding the internal base to the value of this.." newline rbitfld.long 0x8 6.--7. "RESERVED,Reserved" "0,1,2,3" newline hexmask.long.byte 0x8 0.--5. 1. "ADDRMAP_BG_B0,Selects the HIF address bits used as bank group address bit 0. Valid Range: 0 to 32 and 63 Internal Base: 2 The selected HIF address bit for each of the bank group address bits is determined by adding the internal base to the value of this.." group.long 0x22C++0x3 line.long 0x0 "ADDRMAP11,Address Map Register 11" hexmask.long 0x0 4.--31. 1. "RESERVED,Reserved" newline hexmask.long.byte 0x0 0.--3. 1. "ADDRMAP_ROW_B10,Selects the HIF address bits used as row address bit 10. Valid Range: 0 to 11 Internal Base: 16 The selected HIF address bit for each of the row address bits is determined by adding the internal base to the value of this field. This.." group.long 0x240++0x7 line.long 0x0 "ODTCFG,ODT Configuration Register" hexmask.long.byte 0x0 28.--31. 1. "RESERVED,Reserved" newline hexmask.long.byte 0x0 24.--27. 1. "WR_ODT_HOLD,DFI PHY clock cycles to hold ODT for a write command. The minimum supported value is 2. Recommended values: DDR2: - BL8 - 0x5 (DDR2-400/533/667) 0x6 (DDR2-800) 0x7 (DDR2-1066) - BL4 - 0x3 (DDR2-400/533/667) 0x4 (DDR2-800) 0x5 (DDR2-1066).." newline rbitfld.long 0x0 21.--23. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x0 16.--20. 1. "WR_ODT_DELAY,Indicates the delay in DFI PHY clock cycles from issuing a write command to setting ODT values associated with that command. ODT setting must remain constant for the entire time that DQS is driven by the uMCTL2. Recommended values: DDR2: -.." newline hexmask.long.byte 0x0 12.--15. 1. "RESERVED,Reserved" newline hexmask.long.byte 0x0 8.--11. 1. "RD_ODT_HOLD,DFI PHY clock cycles to hold ODT for a read command. The minimum supported value is 2. Recommended values: DDR2: - BL8 - 0x6 (not DDR2-1066) 0x7 (DDR2-1066) - BL4 - 0x4 (not DDR2-1066) 0x5 (DDR2-1066) DDR3: - BL8 - 0x6 DDR4: - BL8 - 5 +.." newline rbitfld.long 0x0 7. "RESERVED,Reserved" "0,1" newline hexmask.long.byte 0x0 2.--6. 1. "RD_ODT_DELAY,Indicates the delay in DFI PHY clock cycles from issuing a read command to setting ODT values associated with that command. ODT setting must remain constant for the entire time that DQS is driven by the uMCTL2. Recommended values: DDR2: -.." newline rbitfld.long 0x0 0.--1. "RESERVED,Reserved" "0,1,2,3" line.long 0x4 "ODTMAP,ODT/Rank Map Register" hexmask.long.tbyte 0x4 14.--31. 1. "RESERVED,Reserved" newline bitfld.long 0x4 12.--13. "RANK1_RD_ODT,Indicates which remote ODTs must be turned on during a read from rank 1. Each rank has a remote ODT (in the SDRAM) which can be turned on by setting the appropriate bit here. Rank 0 is controlled by the LSB; rank 1 is controlled by bit next.." "0,1,2,3" newline rbitfld.long 0x4 10.--11. "RESERVED,Reserved" "0,1,2,3" newline bitfld.long 0x4 8.--9. "RANK1_WR_ODT,Indicates which remote ODTs must be turned on during a write to rank 1. Each rank has a remote ODT (in the SDRAM) which can be turned on by setting the appropriate bit here. Rank 0 is controlled by the LSB; rank 1 is controlled by bit next.." "0,1,2,3" newline rbitfld.long 0x4 6.--7. "RESERVED,Reserved" "0,1,2,3" newline bitfld.long 0x4 4.--5. "RANK0_RD_ODT,Indicates which remote ODTs must be turned on during a read from rank 0. Each rank has a remote ODT (in the SDRAM) which can be turned on by setting the appropriate bit here. Rank 0 is controlled by the LSB; rank 1 is controlled by bit next.." "0,1,2,3" newline rbitfld.long 0x4 2.--3. "RESERVED,Reserved" "0,1,2,3" newline bitfld.long 0x4 0.--1. "RANK0_WR_ODT,Indicates which remote ODTs must be turned on during a write to rank 0. Each rank has a remote ODT (in the SDRAM) which can be turned on by setting the appropriate bit here. Rank 0 is controlled by the LSB; rank 1 is controlled by bit next.." "0,1,2,3" group.long 0x250++0x7 line.long 0x0 "SCHED,Scheduler Control Register" rbitfld.long 0x0 31. "RESERVED,Reserved" "0,1" newline hexmask.long.byte 0x0 24.--30. 1. "RDWR_IDLE_GAP,When the preferred transaction store is empty for these many clock cycles switch to the alternate transaction store if it is non-empty. The read transaction store (both high and low priority) is the default preferred transaction store and.." newline hexmask.long.byte 0x0 16.--23. 1. "GO2CRITICAL_HYSTERESIS,UNUSED. Programming Mode: Static" newline bitfld.long 0x0 15. "LPDDR4_OPT_ACT_TIMING,Optimized ACT timing control for LPDDR4. In LPDDR4 RD/WR/ACT takes 4 cycle. To stream Read/Write there are only 4 cycle space between Reads/Writes. If ACT is scheduled-out after RD/WR with 1 2 or 3 cycle gap next RD/WR may be.." "Disable this feature,Enable this feature" newline rbitfld.long 0x0 13.--14. "RESERVED,Reserved" "0,1,2,3" newline hexmask.long.byte 0x0 8.--12. 1. "LPR_NUM_ENTRIES,Number of entries in the low priority transaction store is this value + 1. (MEMC_NO_OF_ENTRY - (SCHED.lpr_num_entries + 1)) is the number of entries available for the high priority transaction store. Setting this to maximum value.." newline bitfld.long 0x0 7. "AUTOPRE_RMW,Selects behavior of hif_cmd_autopre if a RMW is received on HIF with hif_cmd_autopre=1 - 1 - Apply Autopre only for write part of RMW - 0 - Apply Autopre for both read and write parts of RMW Programming Mode: Static" "Apply Autopre for both read and write parts of RMW,Apply Autopre only for write part of RMW" newline hexmask.long.byte 0x0 3.--6. 1. "RESERVED,Reserved" newline bitfld.long 0x0 2. "PAGECLOSE,If true bank is kept open only while there are page hit transactions available in the CAM to that bank. The last read or write command in the CAM with a bank and page hit is executed with auto-precharge if SCHED1.pageclose_timer=0. Even if.." "0,1" newline bitfld.long 0x0 1. "PREFER_WRITE,If set then the bank selector prefers writes over reads. FOR DEBUG ONLY. Programming Mode: Static" "0,1" newline rbitfld.long 0x0 0. "RESERVED,Reserved" "0,1" line.long 0x4 "SCHED1,Scheduler Control Register 1" hexmask.long.tbyte 0x4 8.--31. 1. "RESERVED,Reserved" newline hexmask.long.byte 0x4 0.--7. 1. "PAGECLOSE_TIMER,This field works in conjunction with SCHED.pageclose.It only has meaning if SCHED.pageclose==1. If SCHED.pageclose==1 and pageclose_timer==0 then an auto-precharge may be scheduled for last read or write command in the CAM with a bank.." group.long 0x25C++0x3 line.long 0x0 "PERFHPR1,High Priority Read CAM Register 1" hexmask.long.byte 0x0 24.--31. 1. "HPR_XACT_RUN_LENGTH,Indicates the number of transactions that are serviced once the HPR queue goes critical is the smaller of: - (a) This number - (b) Number of transactions available Unit: Transaction. FOR PERFORMANCE ONLY. Programming Mode:.." newline hexmask.long.byte 0x0 16.--23. 1. "RESERVED,Reserved" newline hexmask.long.word 0x0 0.--15. 1. "HPR_MAX_STARVE,Indicates the number of DFI clocks that the HPR queue can be starved before it goes critical. The minimum valid functional value for this register is 0x1. Programming it to 0x0 disables the starvation functionality. During normal operation.." group.long 0x264++0x3 line.long 0x0 "PERFLPR1,Low Priority Read CAM Register 1" hexmask.long.byte 0x0 24.--31. 1. "LPR_XACT_RUN_LENGTH,Indicates the number of transactions that are serviced once the LPR queue goes critical is the smaller of: - (a) This number - (b) Number of transactions available Unit: Transaction. FOR PERFORMANCE ONLY. Programming Mode:.." newline hexmask.long.byte 0x0 16.--23. 1. "RESERVED,Reserved" newline hexmask.long.word 0x0 0.--15. 1. "LPR_MAX_STARVE,Indicates the number of DFI clocks that the LPR queue can be starved before it goes critical. The minimum valid functional value for this register is 0x1. Programming it to 0x0 disables the starvation functionality. During normal operation.." group.long 0x26C++0x3 line.long 0x0 "PERFWR1,Write CAM Register 1" hexmask.long.byte 0x0 24.--31. 1. "W_XACT_RUN_LENGTH,Indicates the number of transactions that are serviced once the WR queue goes critical is the smaller of: - (a) This number - (b) Number of transactions available Unit: Transaction. FOR PERFORMANCE ONLY. Programming Mode: Quasi-dynamic.." newline hexmask.long.byte 0x0 16.--23. 1. "RESERVED,Reserved" newline hexmask.long.word 0x0 0.--15. 1. "W_MAX_STARVE,Indicates the number of DFI clocks that the WR queue can be starved before it goes critical. The minimum valid functional value for this register is 0x1. Programming it to 0x0 disables the starvation functionality. During normal operation.." group.long 0x300++0x7 line.long 0x0 "DBG0,Debug Register 0" hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED,Reserved" newline bitfld.long 0x0 7. "DIS_MAX_RANK_WR_OPT,Indicates the disable optimized max_rank_wr and max_logical_rank_wr feature. This register is for debug purpose only. For normal operation This register must be set to 0. Programming Mode: Static" "0,1" newline bitfld.long 0x0 6. "DIS_MAX_RANK_RD_OPT,Indicates the disable optimized max_rank_rd and max_logical_rank_rd feature. This register is for debug purpose only. For normal operation This register must be set to 0. Programming Mode: Static" "0,1" newline rbitfld.long 0x0 5. "RESERVED,Reserved" "0,1" newline bitfld.long 0x0 4. "DIS_COLLISION_PAGE_OPT,When this is set to '0' auto-precharge is disabled for the flushed command in a collision case. Collision cases are write followed by read to same address read followed by write to same address or write followed by write to same.." "0,1" newline rbitfld.long 0x0 1.--3. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 0. "DIS_WC,When 1 disable write combine. FOR DEBUG ONLY. Programming Mode: Static" "0,1" line.long 0x4 "DBG1,Debug Register 1" hexmask.long 0x4 2.--31. 1. "RESERVED,Reserved" newline bitfld.long 0x4 1. "DIS_HIF,When 1 uMCTL2 asserts the HIF command signal hif_cmd_stall. uMCTL2 ignores the hif_cmd_valid and all other associated request signals. This bit is intended to be switched on-the-fly. Programming Mode: Dynamic" "0,1" newline bitfld.long 0x4 0. "DIS_DQ,When 1 uMCTL2 does not de-queue any transactions from the CAM. Bypass is also disabled. All transactions are queued in the CAM. No reads or writes are issued to SDRAM as long as this is asserted. This bit may be used to prevent reads or writes.." "0,1" rgroup.long 0x308++0x3 line.long 0x0 "DBGCAM,CAM Debug Register" bitfld.long 0x0 30.--31. "RESERVED,Reserved" "0,1,2,3" newline bitfld.long 0x0 29. "WR_DATA_PIPELINE_EMPTY,This bit indicates that the write data pipeline on the DFI interface is empty. This register is intended to be polled at least twice after setting DBG1.dis_dq to ensure that all remaining commands/data have completed. Programming.." "0,1" newline bitfld.long 0x0 28. "RD_DATA_PIPELINE_EMPTY,This bit indicates that the read data pipeline on the DFI interface is empty. This register is intended to be polled at least twice after setting DBG1.dis_dq to ensure that all remaining commands/data have completed. Programming.." "0,1" newline bitfld.long 0x0 27. "RESERVED,Reserved" "0,1" newline bitfld.long 0x0 26. "DBG_WR_Q_EMPTY,When 1 all the Write command queues and Write data buffers inside DDRC are empty. This register is to be used for debug purpose. An example use-case scenario: When the controller enters self-refresh using the Low-Power entry sequence.." "0,1" newline bitfld.long 0x0 25. "DBG_RD_Q_EMPTY,When 1 all the Read command queues and Read data buffers inside DDRC are empty. This register is to be used for debug purpose. An example use-case scenario: When the controller enters self-refresh using the Low-Power entry sequence.." "0,1" newline bitfld.long 0x0 24. "DBG_STALL,Stall. FOR DEBUG ONLY. Programming Mode: Dynamic" "0,1" newline bitfld.long 0x0 22.--23. "RESERVED,Reserved" "0,1,2,3" newline hexmask.long.byte 0x0 16.--21. 1. "DBG_W_Q_DEPTH,This field indicates the Write queue depth. The last entry of WR queue is reserved for ECC SCRUB operation. This entry is not included in the calculation of the queue depth. FOR DEBUG ONLY Programming Mode: Dynamic" newline bitfld.long 0x0 14.--15. "RESERVED,Reserved" "0,1,2,3" newline hexmask.long.byte 0x0 8.--13. 1. "DBG_LPR_Q_DEPTH,This field indicates the low priority read queue depth. The last entry of Lpr queue is reserved for ECC SCRUB operation. This entry is not included in the calculation of the queue depth. FOR DEBUG ONLY Programming Mode: Dynamic" newline bitfld.long 0x0 6.--7. "RESERVED,Reserved" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "DBG_HPR_Q_DEPTH,This field indicates the high priority read queue depth. FOR DEBUG ONLY. Programming Mode: Dynamic" group.long 0x30C++0x3 line.long 0x0 "DBGCMD,Command Debug Register" hexmask.long 0x0 6.--31. 1. "RESERVED,Reserved" newline bitfld.long 0x0 5. "CTRLUPD,Setting this register bit to 1 indicates to the uMCTL2 to issue a dfi_ctrlupd_req to the PHY. When this request is stored in the uMCTL2 the bit is automatically cleared. This operation must only be performed when DFIUPD0.dis_auto_ctrlupd=1." "0,1" newline bitfld.long 0x0 4. "ZQ_CALIB_SHORT,Setting this register bit to 1 indicates to the uMCTL2 to issue a ZQCS (ZQ calibration short)/MPC(ZQ calibration) command to the SDRAM. When this request is stored in the uMCTL2 the bit is automatically cleared. This operation can be.." "0,1" newline rbitfld.long 0x0 2.--3. "RESERVED,Reserved" "0,1,2,3" newline bitfld.long 0x0 1. "RANK1_REFRESH,Setting this register bit to 1 indicates to the uMCTL2 to issue a refresh to rank 1. Writing to this bit causes DBGSTAT.rank1_refresh_busy to be set. When DBGSTAT.rank1_refresh_busy is cleared the command has been stored in uMCTL2. For 3DS.." "0,1" newline bitfld.long 0x0 0. "RANK0_REFRESH,Setting this register bit to 1 indicates to the uMCTL2 to issue a refresh to rank 0. Writing to this bit causes DBGSTAT.rank0_refresh_busy to be set. When DBGSTAT.rank0_refresh_busy is cleared the command has been stored in uMCTL2. For 3DS.." "0,1" rgroup.long 0x310++0x3 line.long 0x0 "DBGSTAT,Status Debug Register" hexmask.long 0x0 6.--31. 1. "RESERVED,Reserved" newline bitfld.long 0x0 5. "CTRLUPD_BUSY,SoC might initiate a ctrlupd operation only if this signal is low. This signal goes high in the clock after the uMCTL2 accepts the ctrlupd request. It goes low when the ctrlupd operation is initiated in the uMCTL2. It is recommended not to.." "Indicates that the SoC can initiate a ctrlupd..,Indicates that ctrlupd operation has not been.." newline bitfld.long 0x0 4. "ZQ_CALIB_SHORT_BUSY,SoC might initiate a ZQCS (ZQ calibration short) operation only if this signal is low. This signal goes high in the clock after the uMCTL2 accepts the ZQCS request. It goes low when the ZQCS operation is initiated in the uMCTL2. It is.." "Indicates that the SoC can initiate a ZQCS..,Indicates that ZQCS operation has not been.." newline bitfld.long 0x0 2.--3. "RESERVED,Reserved" "0,1,2,3" newline bitfld.long 0x0 1. "RANK1_REFRESH_BUSY,SoC might initiate a rank1_refresh operation (refresh operation to rank 1) only if this signal is low. This signal goes high in the clock after DBGCMD.rank1_refresh is set to one. It goes low when the rank1_refresh operation is stored.." "Indicates that the SoC can initiate a..,Indicates that rank1_refresh operation has not.." newline bitfld.long 0x0 0. "RANK0_REFRESH_BUSY,SoC might initiate a rank0_refresh operation (refresh operation to rank 0) only if this signal is low. This signal goes high in the clock after DBGCMD.rank0_refresh is set to one. It goes low when the rank0_refresh operation is stored.." "Indicates that the SoC can initiate a..,Indicates that rank0_refresh operation has not.." rgroup.long 0x318++0x3 line.long 0x0 "DBGCAM1,CAM Debug Register 1" hexmask.long 0x0 6.--31. 1. "RESERVED,Reserved" newline hexmask.long.byte 0x0 0.--5. 1. "DBG_WRECC_Q_DEPTH,This field indicates the write ECC queue depth. FOR DEBUG ONLY. Programming Mode: Dynamic" group.long 0x320++0x3 line.long 0x0 "SWCTL,Software Register Programming Control Enable" hexmask.long 0x0 1.--31. 1. "RESERVED,Reserved" newline bitfld.long 0x0 0. "SW_DONE,Enables quasi-dynamic register programming outside reset. Program this register to 0 to enable quasi-dynamic programming. Set back register to 1 once programming is done. Programming Mode: Dynamic" "0,1" rgroup.long 0x324++0x3 line.long 0x0 "SWSTAT,Software Register Programming Control Status" hexmask.long 0x0 1.--31. 1. "RESERVED,Reserved" newline bitfld.long 0x0 0. "SW_DONE_ACK,Register programming done. This register is the echo of SWCTL.sw_done. Wait for sw_done value 1 to propagate to sw_done_ack at the end of the programming sequence to ensure that the correct registers values are propagated to the destination.." "0,1" group.long 0x328++0x3 line.long 0x0 "SWCTLSTATIC,Static Registers Write Enable" hexmask.long 0x0 1.--31. 1. "RESERVED,Reserved" newline bitfld.long 0x0 0. "SW_STATIC_UNLOCK,Enables static register programming outside reset. Program this register to 1 to enable static register programming. Set register back to 0 once programming is done. Programming Mode: Dynamic" "0,1" group.long 0x330++0x7 line.long 0x0 "OCPARCFG0,On-Chip Parity Configuration Register 0" hexmask.long.byte 0x0 27.--31. 1. "RESERVED,Reserved" newline bitfld.long 0x0 26. "PAR_RADDR_ERR_INTR_FORCE,Interrupt force bit for all par_raddr_err_intr. uMCTL2 automatically clears this bit. Programming Mode: Dynamic" "0,1" newline bitfld.long 0x0 25. "PAR_WADDR_ERR_INTR_FORCE,Interrupt force bit for all par_waddr_err_intr. uMCTL2 automatically clears this bit. Programming Mode: Dynamic" "0,1" newline bitfld.long 0x0 24. "PAR_RADDR_ERR_INTR_CLR,Interrupt clear bit for all par_raddr_err_intr. uMCTL2 automatically clears this bit. Programming Mode: Dynamic" "0,1" newline bitfld.long 0x0 23. "PAR_RADDR_ERR_INTR_EN,Enables interrupt generation if set to 1 for all ports on signal par_raddr_err_intr_n upon detection of parity error on the AXI interface. Programming Mode: Dynamic" "0,1" newline bitfld.long 0x0 22. "PAR_WADDR_ERR_INTR_CLR,Interrupt clear bit for all par_waddr_err_intr. uMCTL2 automatically clears this bit. Programming Mode: Dynamic" "0,1" newline bitfld.long 0x0 21. "PAR_WADDR_ERR_INTR_EN,Enables interrupt generation if set to 1 for all ports on signal par_waddr_err_intr_n upon detection of parity error on the AXI interface. Programming Mode: Dynamic" "0,1" newline bitfld.long 0x0 20. "PAR_ADDR_SLVERR_EN,Enables SLVERR generation on read response or write response when address parity error is detected at the AXI interface. Programming Mode: Quasi-dynamic Group 3" "0,1" newline hexmask.long.byte 0x0 16.--19. 1. "RESERVED,Reserved" newline bitfld.long 0x0 15. "PAR_RDATA_ERR_INTR_FORCE,Interrupt force bit for all par_rdata_err_intr_n and par_rdata_in_err_ecc_intr (Inline-ECC only). uMCTL2 automatically clears this bit. Programming Mode: Dynamic" "0,1" newline bitfld.long 0x0 14. "PAR_RDATA_ERR_INTR_CLR,Interrupt clear bit for par_rdata_err_intr. uMCTL2 automatically clears this bit. Programming Mode: Dynamic" "0,1" newline bitfld.long 0x0 13. "PAR_RDATA_ERR_INTR_EN,Enables interrupt generation if set to 1 for all ports on signal par_rdata_err_intr_n upon detection of parity error at the AXI interface. Programming Mode: Dynamic" "0,1" newline bitfld.long 0x0 12. "PAR_RDATA_SLVERR_EN,Enables SLVERR generation on read response when read data parity error is detected at the AXI interface. Programming Mode: Quasi-dynamic Group 3" "0,1" newline hexmask.long.byte 0x0 8.--11. 1. "RESERVED,Reserved" newline bitfld.long 0x0 7. "PAR_WDATA_ERR_INTR_FORCE,Interrupt force bit for par_wdata_err_intr. uMCTL2 automatically clears this bit. Programming Mode: Dynamic" "0,1" newline bitfld.long 0x0 6. "PAR_WDATA_ERR_INTR_CLR,Interrupt clear bit for par_wdata_err_intr. uMCTL2 automatically clears this bit. Programming Mode: Dynamic" "0,1" newline bitfld.long 0x0 5. "PAR_WDATA_SLVERR_EN,Enables SLVERR generation on write response when write data parity error is detected at the AXI interface. Programming Mode: Quasi-dynamic Group 3" "0,1" newline bitfld.long 0x0 4. "PAR_WDATA_ERR_INTR_EN,Enables write data interrupt generation (par_wdata_err_intr) upon detection of parity error at the AXI or DFI interface. Programming Mode: Dynamic" "0,1" newline rbitfld.long 0x0 2.--3. "RESERVED,Reserved" "0,1,2,3" newline bitfld.long 0x0 1. "OC_PARITY_TYPE,Parity type: - 0 - Even parity - 1 - Odd parity Programming Mode: Quasi-dynamic Group 3" "Even parity,Odd parity" newline bitfld.long 0x0 0. "OC_PARITY_EN,Parity enable register. Enables On-Chip parity for all interfaces. Programming Mode: Quasi-dynamic Group 3" "0,1" line.long 0x4 "OCPARCFG1,On-Chip Parity Configuration Register 1" hexmask.long.tbyte 0x4 12.--31. 1. "RESERVED,Reserved" newline hexmask.long.byte 0x4 8.--11. 1. "PAR_POISON_LOC_WR_PORT,Enables parity poisoning on write data at the AXI interface before the input parity check logic. The value specifies the binary encoded port number of the AXI interface to be injected with parity error. Programming Mode:.." newline hexmask.long.byte 0x4 4.--7. 1. "PAR_POISON_LOC_RD_PORT,Enables parity poisoning on read data at the AXI interface after the parity check logic. The value specifies the binary encoded port number of the AXI interface to be injected with parity error. Error can be injected to one port at.." newline bitfld.long 0x4 3. "PAR_POISON_LOC_RD_IECC_TYPE,Selects which parity to poison at the DFI when inline ECC is enabled. If this register is set to 0 parity error is injected on the first read data going through the ECC path. If this register is set to 1 parity error is.." "0,1" newline bitfld.long 0x4 2. "PAR_POISON_LOC_RD_DFI,Enables parity poisoning on read data at the DFI interface after the parity generation logic. When MEMC_INLINE_ECC=1 enables poisoning of ECC word after the ECC encoder at the write data interface at the DFI. Programming Mode:.." "0,1" newline rbitfld.long 0x4 1. "RESERVED,Reserved" "0,1" newline bitfld.long 0x4 0. "PAR_POISON_EN,Enables on-chip parity poisoning on the data interfaces. Programming Mode: Quasi-dynamic Group 3" "0,1" repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) rgroup.long ($2+0x338)++0x3 line.long 0x0 "OCPARSTAT$1,On-Chip Parity Status Register 0" hexmask.long.word 0x0 17.--31. 1. "RESERVED,Reserved" newline bitfld.long 0x0 16. "PAR_RADDR_ERR_INTR_0,Read address parity error interrupt for port 0. This interrupt is asserted when an on-chip read address parity error occurred on the corresponding AXI port's read address channel. Programming Mode: Static" "0,1" newline hexmask.long.word 0x0 1.--15. 1. "RESERVED,Reserved" newline bitfld.long 0x0 0. "PAR_WADDR_ERR_INTR_0,Write address parity error interrupt for port 0. This interrupt is asserted when an on-chip write address parity error occurred on the corresponding AXI port's write address channel. Programming Mode: Static" "0,1" repeat.end rgroup.long 0x340++0x3 line.long 0x0 "OCPARSTAT2,On-Chip Parity Status Register 2" hexmask.long 0x0 5.--31. 1. "RESERVED,Reserved" newline bitfld.long 0x0 4. "PAR_RDATA_IN_ERR_ECC_INTR,Interrupt on ECC data going into inline ECC decoder. Cleared by par_rdata_err_intr_clr. Programming Mode: Static" "0,1" newline bitfld.long 0x0 2.--3. "RESERVED,Reserved" "0,1,2,3" newline bitfld.long 0x0 0.--1. "PAR_WDATA_OUT_ERR_INTR,Write data parity error interrupt on output. Cleared by register par_wdata_err_intr_clr. Programming Mode: Static" "0,1,2,3" group.long 0x36C++0x3 line.long 0x0 "POISONCFG,AXI Poison Configuration Register. Common for all AXI ports." hexmask.long.byte 0x0 25.--31. 1. "RESERVED,Reserved" newline bitfld.long 0x0 24. "RD_POISON_INTR_CLR,Interrupt clear for read transaction poisoning. Allow 2/3 clock cycles for correct value to propagate to controller logic and clear the interrupts. uMCTL2 automatically clears this bit. Programming Mode: Dynamic" "0,1" newline rbitfld.long 0x0 21.--23. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 20. "RD_POISON_INTR_EN,If set to 1 enables interrupts for read transaction poisoning. Programming Mode: Dynamic" "0,1" newline rbitfld.long 0x0 17.--19. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 16. "RD_POISON_SLVERR_EN,If set to 1 enables SLVERR response for read transaction poisoning. Programming Mode: Dynamic" "0,1" newline hexmask.long.byte 0x0 9.--15. 1. "RESERVED,Reserved" newline bitfld.long 0x0 8. "WR_POISON_INTR_CLR,Interrupt clear for write transaction poisoning. Allow 2/3 clock cycles for correct value to propagate to controller logic and clear the interrupts. uMCTL2 automatically clears this bit. Programming Mode: Dynamic" "0,1" newline rbitfld.long 0x0 5.--7. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 4. "WR_POISON_INTR_EN,If set to 1 enables interrupts for write transaction poisoning. Programming Mode: Dynamic" "0,1" newline rbitfld.long 0x0 1.--3. "RESERVED,Reserved" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 0. "WR_POISON_SLVERR_EN,If set to 1 enables SLVERR response for write transaction poisoning. Programming Mode: Dynamic" "0,1" rgroup.long 0x370++0x3 line.long 0x0 "POISONSTAT,AXI Poison Status Register" hexmask.long.word 0x0 17.--31. 1. "RESERVED,Reserved" newline bitfld.long 0x0 16. "RD_POISON_INTR_0,Read transaction poisoning error interrupt for port 0. This register is a APB clock copy (double register synchronizer) of the interrupt asserted when a transaction is poisoned on the corresponding AXI port's read address channel. Bit 0.." "0,1" newline hexmask.long.word 0x0 1.--15. 1. "RESERVED,Reserved" newline bitfld.long 0x0 0. "WR_POISON_INTR_0,Write transaction poisoning error interrupt for port 0. This register is a APB clock copy (double register synchronizer) of the interrupt asserted when a transaction is poisoned on the corresponding AXI port's write address channel. Bit.." "0,1" group.long 0x374++0x3 line.long 0x0 "ADVECCINDEX,Advanced ECC Index Register" hexmask.long.tbyte 0x0 9.--31. 1. "RESERVED,Reserved" newline hexmask.long.byte 0x0 5.--8. 1. "ECC_POISON_BEATS_SEL,Selector of which DRAM beat's poison pattern is set by ECCPOISONPAT0/1/2 registers. For frequency ratio 1:1 mode 2 DRAM beats can be poisoned. Set ecc_poison_beats_sel to 0 and given ECCPOISONPAT0/1/2 to set 1st beat's poison.." newline bitfld.long 0x0 3.--4. "ECC_ERR_SYMBOL_SEL,Selector of which error symbol's status output to ADVECCSTAT.advecc_err_symbol_pos and advecc_err_symbol_bits. The default is first error symbol. The value must be less than ADVECCSTAT.advecc_num_err_symbol. Programming Mode:.." "0,1,2,3" newline bitfld.long 0x0 0.--2. "ECC_SYNDROME_SEL,Selector of which DRAM beat data output to ECCCSYN0/1/2 as well as ECCUCSYN. In Advanced ECC the syndrome consists of number of DRAM beats. This register selects which beats of data is output to ECCCSYN0/1/2 and ECCUCSYN0/1/2 registers." "0,1,2,3,4,5,6,7" group.long 0x37C++0x3 line.long 0x0 "ECCPOISONPAT0,ECC Poison Pattern 0 Register" hexmask.long 0x0 0.--31. 1. "ECC_POISON_DATA_31_0,Indicates the poison pattern for DRAM data[31:0]. setting this bit to 1 indicates poison (invert) corresponding DRAM bit. It is indirect register. Selector is ADVECCINDEX.ecc_poison_beats_sel. Programming Mode: Quasi-dynamic Group 3" group.long 0x384++0x3 line.long 0x0 "ECCPOISONPAT2,ECC Poison Pattern 2 Register" hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED,Reserved" newline hexmask.long.byte 0x0 0.--7. 1. "ECC_POISON_DATA_71_64,Indicates the poison pattern for DRAM data[71:64]. Setting this bit to 1 indicates poison (invert) corresponding DRAM bit. It is indirect register. Selector is ADVECCINDEX.ecc_poison_beats_sel. Programming Mode: Quasi-dynamic Group 3" rgroup.long 0x388++0x3 line.long 0x0 "ECCAPSTAT,Address protection within ECC Status Register" hexmask.long 0x0 1.--31. 1. "RESERVED,Reserved" newline bitfld.long 0x0 0. "ECC_AP_ERR,Indicates the number of ECC errors (correctable/uncorrectable) within one burst exceeded the threshold(ECCCFG0.ecc_ap_err_threshold). Programming Mode: Dynamic" "0,1" group.long 0x3C0++0x3 line.long 0x0 "REGPARCFG,Register Parity Configuration Register (Note that all fields must be programmed with single write operation)." hexmask.long.tbyte 0x0 9.--31. 1. "RESERVED,Reserved" newline bitfld.long 0x0 8. "REG_PAR_POISON_EN,Enable Register Parity poisoning. Programming Mode: Dynamic" "0,1" newline hexmask.long.byte 0x0 4.--7. 1. "RESERVED,Reserved" newline bitfld.long 0x0 3. "REG_PAR_ERR_INTR_FORCE,Interrupt force bit for reg_par_err_intr setting this register causes the output interrupt to be asserted. uMCTL2 automatically clears this bit. There is no interaction between functionally triggering an interrupt and forcing an.." "0,1" newline bitfld.long 0x0 2. "REG_PAR_ERR_INTR_CLR,Interupt clear bit for reg_par_err_intr. uMCTL2 automatically clears this bit. Programming Mode: Dynamic" "0,1" newline bitfld.long 0x0 1. "REG_PAR_ERR_INTR_EN,Enables interrupt generation if set to 1 on signal reg_par_err_intr upon detection of register parity error. Programming Mode: Dynamic" "0,1" newline bitfld.long 0x0 0. "REG_PAR_EN,Register Parity enable register. Programming Mode: Dynamic" "0,1" rgroup.long 0x3C4++0x3 line.long 0x0 "REGPARSTAT,Register Parity Status Register" hexmask.long 0x0 1.--31. 1. "RESERVED,Reserved" newline bitfld.long 0x0 0. "REG_PAR_ERR_INTR,Interrupt asserted when Register Parity error is detected. Cleared by setting REGPARCFG.reg_par_err_intr_clr to 1. Programming Mode: Static" "0,1" group.long 0x3E0++0x3 line.long 0x0 "OCCAPCFG,On-Chip command/Address Protection Configuration Register" hexmask.long.byte 0x0 28.--31. 1. "RESERVED,Reserved" newline bitfld.long 0x0 27. "OCCAP_ARB_RAQ_POISON_EN,Enables poisoning for the Read Address Queues (RAQ) inside each XPI. Poisoning inverts all parity bits generated by the parity generator. Error is flagged as soon as the first RAQ is read. This register is not cleared.." "0,1" newline bitfld.long 0x0 26. "OCCAP_ARB_CMP_POISON_ERR_INJ,Enables error injection in the poisoning of OCCAP Arbiter logic. Injects error into poisoning logic (either parallel or seq) such that XOR logic for one signal is not poisoned when expected. If set it allows ability to.." "OCCAPSTAT,OCCAPSTAT" newline bitfld.long 0x0 25. "OCCAP_ARB_CMP_POISON_PARALLEL,Enables full poisoning for compare logic inside XPI. Poisoning inverts all bits of all outputs coming from the duplicated modules before the XOR comparators together. uMCTL2 automatically clears this bit. Programming Mode:.." "0,1" newline bitfld.long 0x0 24. "OCCAP_ARB_CMP_POISON_SEQ,Enables poisoning for compare logic inside XPI. Poisoning inverts all bits coming from the duplicated modules before the XOR comparators one output at the time per each comparator. uMCTL2 automatically clears this bit." "0,1" newline hexmask.long.byte 0x0 19.--23. 1. "RESERVED,Reserved" newline bitfld.long 0x0 18. "OCCAP_ARB_INTR_FORCE,Interrupt force bit for occap_arb_err_intr setting this register causes the output interrupt to be asserted. uMCTL2 automatically clears this bit. There is no interaction between functionally triggering an interrupt and forcing an.." "0,1" newline bitfld.long 0x0 17. "OCCAP_ARB_INTR_CLR,Interrupt clear bit for occap_arb_err_intr and occap_arb_cmp_poison_complete. uMCTL2 automatically clears this bit. Programming Mode: Dynamic" "0,1" newline bitfld.long 0x0 16. "OCCAP_ARB_INTR_EN,Enables interrupt generation upon detection of OCCAP Arbiter errors. Programming Mode: Dynamic" "0,1" newline hexmask.long.word 0x0 1.--15. 1. "RESERVED,Reserved" newline bitfld.long 0x0 0. "OCCAP_EN,On Chip Command/Address Path Protection (OCCAP) enable register. Programming Mode: Quasi-dynamic Group 3" "0,1" rgroup.long 0x3E4++0x3 line.long 0x0 "OCCAPSTAT,On-Chip command/Address Protection Status Register" hexmask.long.byte 0x0 26.--31. 1. "RESERVED,Reserved" newline bitfld.long 0x0 25. "OCCAP_ARB_CMP_POISON_PARALLEL_ERR,Error when occap_arb_cmp_poison_full_en is active due to incorrect number of errors being occurring. Internal logic checks the number of errors detected while poisoning occurred for occap_arb_cmp_poison_full_en. It.." "0,1" newline bitfld.long 0x0 24. "OCCAP_ARB_CMP_POISON_SEQ_ERR,Error when occap_arb_cmp_poison_en is active due to incorrect number of errors being occurring. Internal logic checks that the correct number of errors detected while poisoning one output at the time occurred for.." "0,1" newline hexmask.long.byte 0x0 18.--23. 1. "RESERVED,Reserved" newline bitfld.long 0x0 17. "OCCAP_ARB_CMP_POISON_COMPLETE,OCCAP ARB comparator poisoning complete interrupt status. Register cleared by OCCAPCFG.occap_arb_intr_clr. Programming Mode: Static" "0,1" newline bitfld.long 0x0 16. "OCCAP_ARB_ERR_INTR,OCCAP Arbiter error interrupt status. Register cleared by OCCAPCFG.occap_arb_intr_clr. Programming Mode: Static" "0,1" newline hexmask.long.word 0x0 0.--15. 1. "RESERVED,Reserved" group.long 0x3E8++0x3 line.long 0x0 "OCCAPCFG1,On-Chip command/Address Protection Configuration Register 1" hexmask.long.byte 0x0 27.--31. 1. "RESERVED,Reserved" newline bitfld.long 0x0 26. "OCCAP_DDRC_CTRL_POISON_ERR_INJ,Enables error injection in the poisoning of OCCAP DDRC CTRL logic. Injects error into poisoning logic (either parallel or seq) such that XOR logic for one signal is not poisoned when expected. If set it allows ability to.." "OCCAPSTAT1,OCCAPSTAT1" newline bitfld.long 0x0 25. "OCCAP_DDRC_CTRL_POISON_PARALLEL,Enables poisoning of OCCAP DDRC CTRL logic for all parts of comparison logic in parallel. Poisons comparison logic for one core_ddrc_core_clk cycle by inverting a ddrc_ctrl[0]'s signal to XOR logic. ddrc_ctrl[1] related.." "0,1" newline bitfld.long 0x0 24. "OCCAP_DDRC_CTRL_POISON_SEQ,Enables poisoning of OCCAP DDRC CTRL logic for all parts of comparison logic in sequence. Poisons comparison logic for one core_ddrc_core_clk cycle by inverting a ddrc_ctrl[0]'s signal to XOR logic. ddrc_ctrl[1] related.." "0,1" newline hexmask.long.byte 0x0 19.--23. 1. "RESERVED,Reserved" newline bitfld.long 0x0 18. "OCCAP_DDRC_CTRL_INTR_FORCE,Interrupt force bit for occap_ddrc_ctrl_err_intr setting this register causes the output interrupt to be asserted. uMCTL2 automatically clears this bit. There is no interaction between functionally triggering an interrupt and.." "0,1" newline bitfld.long 0x0 17. "OCCAP_DDRC_CTRL_INTR_CLR,Interrupt clear bit for occap_ddrc_ctrl_err_intr. uMCTL2 automatically clears this bit. Programming Mode: Dynamic" "0,1" newline bitfld.long 0x0 16. "OCCAP_DDRC_CTRL_INTR_EN,Enables interrupt generation on signal occap_ddrc_ctrl_err_intr upon detection of OCCAP DDRC CTRL errors. Programming Mode: Dynamic" "0,1" newline hexmask.long.byte 0x0 11.--15. 1. "RESERVED,Reserved" newline bitfld.long 0x0 10. "OCCAP_DDRC_DATA_POISON_ERR_INJ,Enables error injection in the poisoning of OCCAP DDRC DATA logic. Injects error into poisoning logic (either parallel or seq) such that XOR logic for one signal is not poisoned when expected. If set it allows ability to.." "OCCAPSTAT1,OCCAPSTAT1" newline bitfld.long 0x0 9. "OCCAP_DDRC_DATA_POISON_PARALLEL,Enables poisoning of OCCAP DDRC DATA logic for all parts of comparison logic in parallel. Poisons comparison logic for one core_ddrc_core_clk cycle by inverting all bits of a signal to XOR logic. All signals of.." "0,1" newline bitfld.long 0x0 8. "OCCAP_DDRC_DATA_POISON_SEQ,Enables poisoning of OCCAP DDRC DATA logic for all parts of comparison logic in sequence. Poisons comparison logic for one core_ddrc_core_clk cycle by inverting all bits of a signal to XOR logic. All signals of instance[0] of.." "0,1" newline hexmask.long.byte 0x0 3.--7. 1. "RESERVED,Reserved" newline bitfld.long 0x0 2. "OCCAP_DDRC_DATA_INTR_FORCE,Interrupt force bit for occap_ddrc_data_err_intr setting this register causes the output interrupt to be asserted. uMCTL2 automatically clears this bit. There is no interaction between functionally triggering an interrupt and.." "0,1" newline bitfld.long 0x0 1. "OCCAP_DDRC_DATA_INTR_CLR,Interrupt clear bit for occap_ddrc_data_err_intr. uMCTL2 automatically clears this bit. Programming Mode: Dynamic" "0,1" newline bitfld.long 0x0 0. "OCCAP_DDRC_DATA_INTR_EN,Enables interrupt generation on signal occap_ddrc_data_err_intr upon detection of OCCAP DDRC DATA errors. Programming Mode: Dynamic" "0,1" rgroup.long 0x3EC++0x7 line.long 0x0 "OCCAPSTAT1,On-Chip command/Address Protection Status Register 1" hexmask.long.byte 0x0 26.--31. 1. "RESERVED,Reserved" newline bitfld.long 0x0 25. "OCCAP_DDRC_CTRL_POISON_PARALLEL_ERR,Error when occap_ddrc_ctrl_poison_parallel is active due to incorrect number of errors being occurring. Internal logic checks the number of errors detected while poisoning occurred for occap_ddrc_ctrl_poison_parallel." "0,1" newline bitfld.long 0x0 24. "OCCAP_DDRC_CTRL_POISON_SEQ_ERR,Error when occap_ddrc_ctrl_poison_seq is active due to incorrect number of errors being occurring. Internal logic checks the number of errors detected while poisoning occurred for occap_ddrc_ctrl_poison_seq. It checks for.." "0,1" newline hexmask.long.byte 0x0 18.--23. 1. "RESERVED,Reserved" newline bitfld.long 0x0 17. "OCCAP_DDRC_CTRL_POISON_COMPLETE,Indicates the OCCAP DDRC CTRL poisoning complete interrupt status. Register cleared by OCCAPCFG1.occap_ddrc_ctrl_err_intr_clr. Programming Mode: Static" "0,1" newline bitfld.long 0x0 16. "OCCAP_DDRC_CTRL_ERR_INTR,Indicates the OCCAP DDRC CTRL error interrupt status. Register cleared by OCCAPCFG1.occap_ddrc_ctrl_err_intr_clr. Programming Mode: Static" "0,1" newline hexmask.long.byte 0x0 10.--15. 1. "RESERVED,Reserved" newline bitfld.long 0x0 9. "OCCAP_DDRC_DATA_POISON_PARALLEL_ERR,Error when occap_ddrc_data_poison_parallel is active due to incorrect number of errors being occurring. Internal logic checks the number of errors detected while poisoning occurred for occap_ddrc_data_poison_parallel." "0,1" newline bitfld.long 0x0 8. "OCCAP_DDRC_DATA_POISON_SEQ_ERR,Error when occap_ddrc_data_poison_seq is active due to incorrect number of errors being occurring. Internal logic checks the number of errors detected while poisoning occurred for occap_ddrc_data_poison_seq. It checks for.." "0,1" newline hexmask.long.byte 0x0 2.--7. 1. "RESERVED,Reserved" newline bitfld.long 0x0 1. "OCCAP_DDRC_DATA_POISON_COMPLETE,Indicates the OCCAP DDRC DATA poisoning complete interrupt status. Register cleared by OCCAPCFG1.occap_ddrc_data_err_intr_clr. Programming Mode: Static" "0,1" newline bitfld.long 0x0 0. "OCCAP_DDRC_DATA_ERR_INTR,Indicates the OCCAP DDRC DATA error interrupt status. Register cleared by OCCAPCFG1.occap_ddrc_data_err_intr_clr. Programming Mode: Static" "0,1" line.long 0x4 "DERATESTAT,Temperature Derate Status Register" hexmask.long 0x4 1.--31. 1. "RESERVED,Reserved" newline bitfld.long 0x4 0. "DERATE_TEMP_LIMIT_INTR,Derate temperature interrupt indicating LPDDR2/3/4 SDRAM temperature operating limit is exceeded. This register field is set to 1 when the value read from MR4[2:0] is 3'b000 or 3'b111. Cleared by register.." "0,1" tree.end tree "UMCTL2_MP (uMCTL2 Multi-Port Registers)" base ad:0x1016 rgroup.long 0x4++0x3 line.long 0x0 "PSTAT,Port Status Register" bitfld.long 0x0 16. "WR_PORT_BUSY_0,Indicates if there are outstanding writes for AXI port 0. Programming Mode: Dynamic" "0,1" bitfld.long 0x0 0. "RD_PORT_BUSY_0,Indicates if there are outstanding reads for AXI port 0. Programming Mode: Dynamic" "0,1" group.long 0x8++0xB line.long 0x0 "PCCFG,Port Common Configuration Register" bitfld.long 0x0 8. "BL_EXP_MODE,Burst length expansion mode. By default (that is bl_exp_mode==0) XPI expands every AXI burst into multiple HIF commands using the memory burst length as a unit. If set to 1 then XPI uses half of the memory burst length as a unit. This.." "UMCTL2_PARTIAL_WR=1,?" bitfld.long 0x0 4. "PAGEMATCH_LIMIT,Page match four limit. If set to 1 limits the number of consecutive same page DDRC transactions that can be granted by the Port Arbiter to four when Page Match feature is enabled. If set to 0 there is no limit imposed on number of.." "0,1" bitfld.long 0x0 0. "GO2CRITICAL_EN,If set to 1 (enabled) sets co_gs_go2critical_wr and co_gs_go2critical_lpr/co_gs_go2critical_hpr signals going to DDRC based on urgent input (awurgent arurgent) coming from AXI master. If set to 0 (disabled) co_gs_go2critical_wr and.." "0,1" line.long 0x4 "PCFGR_0,Port n Configuration Read Register" bitfld.long 0x4 16. "RDWR_ORDERED_EN,Enables ordered read/writes. If set to 1 preserves the ordering between read transaction and write transaction issued to the same address on a given port. In other words the controller ensures that all same address read and write.." "0,1" bitfld.long 0x4 14. "RD_PORT_PAGEMATCH_EN,If set to 1 enables the Page Match feature. If enabled once a requesting port is granted the port is continued to be granted if the following immediate commands are to the same memory page (same rank same bank and same row). See.." "0,1" bitfld.long 0x4 13. "RD_PORT_URGENT_EN,If set to 1 enables the AXI urgent sideband signal (arurgent). When enabled and arurgent is asserted by the master that port becomes the highest priority and co_gs_go2critical_lpr/co_gs_go2critical_hpr signal to DDRC is asserted if.." "0,1" newline bitfld.long 0x4 12. "RD_PORT_AGING_EN,If set to 1 enables aging function for the read channel of the port. Programming Mode: Static" "0,1" hexmask.long.word 0x4 0.--9. 1. "RD_PORT_PRIORITY,Determines the initial load value of read aging counters. These counters are parallel loaded after reset or after each grant to the corresponding port. The aging counters down-count every clock cycle where the port is requesting but not.." line.long 0x8 "PCFGW_0,Port n Configuration Write Register" bitfld.long 0x8 14. "WR_PORT_PAGEMATCH_EN,If set to 1 enables the Page Match feature. If enabled once a requesting port is granted the port is continued to be granted if the following immediate commands are to the same memory page (same rank same bank and same row). See.." "0,1" bitfld.long 0x8 13. "WR_PORT_URGENT_EN,If set to 1 enables the AXI urgent sideband signal (awurgent). When enabled and awurgent is asserted by the master that port becomes the highest priority and co_gs_go2critical_wr signal to DDRC is asserted if enabled in.." "0,1" bitfld.long 0x8 12. "WR_PORT_AGING_EN,If set to 1 enables aging function for the write channel of the port. Programming Mode: Static" "0,1" newline hexmask.long.word 0x8 0.--9. 1. "WR_PORT_PRIORITY,Determines the initial load value of write aging counters. These counters are parallel loaded after reset or after each grant to the corresponding port. The aging counters down-count every clock cycle where the port is requesting but.." group.long 0x98++0x13 line.long 0x0 "PCTRL_0,Port n Control Register" bitfld.long 0x0 0. "PORT_EN,Enables AXI port n. Programming Mode: Dynamic" "0,1" line.long 0x4 "PCFGQOS0_0,Port n Read QoS Configuration Register 0" bitfld.long 0x4 24.--25. "RQOS_MAP_REGION2,This bitfield indicates the traffic class of region2. For dual address queue configurations region2 maps to the red address queue. Valid values are 1: VPR and 2: HPR only. When VPR support is disabled (UMCTL2_VPR_EN = 0) and traffic.." "?,VPR and,HPR only,?" bitfld.long 0x4 20.--21. "RQOS_MAP_REGION1,This bit field indicates the traffic class of region 1. Valid values are: - 0 - LPR - 1 - VPR - 2 - HPR For dual address queue configurations region1 maps to the blue address queue. In this case valid values are - 0 - LPR - 1 - VPR.." "LPR,VPR only,HPR,?" bitfld.long 0x4 16.--17. "RQOS_MAP_REGION0,This bit field indicates the traffic class of region 0. Valid values are: - 0 - LPR - 1 - VPR - 2 - HPR For dual address queue configurations region 0 maps to the blue address queue. In this case valid values are: 0: LPR and 1: VPR.." "LPR and,VPR only,HPR,?" newline hexmask.long.byte 0x4 8.--11. 1. "RQOS_MAP_LEVEL2,Separation level2 indicating the end of region1 mapping; start of region1 is (level1 + 1). Possible values for level2 are (level1 + 1) to 14 which corresponds to arqos. Region2 starts from (level2 + 1) up to 15. Note that for PA arqos.." hexmask.long.byte 0x4 0.--3. 1. "RQOS_MAP_LEVEL1,Separation level1 indicating the end of region0 mapping; start of region0 is 0. Possible values for level1 are 0 to 13 (for dual RAQ) or 0 to 14 (for single RAQ) which corresponds to arqos. Note that for PA arqos values are used directly.." line.long 0x8 "PCFGQOS1_0,Port n Read QoS Configuration Register 1" hexmask.long.word 0x8 16.--26. 1. "RQOS_MAP_TIMEOUTR,Specifies the timeout value for transactions mapped to the red address queue. Programming Mode: Quasi-dynamic Group 3" hexmask.long.word 0x8 0.--10. 1. "RQOS_MAP_TIMEOUTB,Specifies the timeout value for transactions mapped to the blue address queue. Programming Mode: Quasi-dynamic Group 3" line.long 0xC "PCFGWQOS0_0,Port n Write QoS Configuration Register 0" bitfld.long 0xC 24.--25. "WQOS_MAP_REGION2,This bit field indicates the traffic class of region 2. Valid values are: - 0 - NPW - 1 - VPW When VPW support is disabled (UMCTL2_VPW_EN = 0) and traffic class of region 2 is set to 1 (VPW) VPW traffic is aliased to NPW traffic." "NPW,VPW,?,?" bitfld.long 0xC 20.--21. "WQOS_MAP_REGION1,This bit field indicates the traffic class of region 1. Valid values are: 0: NPW 1: VPW. When VPW support is disabled (UMCTL2_VPW_EN = 0) and traffic class of region 1 is set to 1 (VPW) VPW traffic is aliased to NPW traffic." "NPW,VPW,?,?" bitfld.long 0xC 16.--17. "WQOS_MAP_REGION0,This bit field indicates the traffic class of region 0. Valid values are: - 0 - NPW - 1 - VPW When VPW support is disabled (UMCTL2_VPW_EN = 0) and traffic class of region 0 is set to 1 (VPW) VPW traffic is aliased to NPW traffic." "NPW,VPW,?,?" newline hexmask.long.byte 0xC 8.--11. 1. "WQOS_MAP_LEVEL2,Separation level2 indicating the end of region1 mapping; start of region1 is (level1 + 1). Possible values for level2 are (level1 + 1) to 14 which corresponds to awqos. Region2 starts from (level2 + 1) up to 15. Note that for PA awqos.." hexmask.long.byte 0xC 0.--3. 1. "WQOS_MAP_LEVEL1,Separation level indicating the end of region0 mapping; start of region0 is 0. Possible values for level1 are 0 to 13 which corresponds to awqos. Note that for PA awqos values are used directly as port priorities where the higher the.." line.long 0x10 "PCFGWQOS1_0,Port n Write QoS Configuration Register 1" hexmask.long.word 0x10 16.--26. 1. "WQOS_MAP_TIMEOUT2,Specifies the timeout value for write transactions in region 2. Programming Mode: Quasi-dynamic Group 3" hexmask.long.word 0x10 0.--10. 1. "WQOS_MAP_TIMEOUT1,Specifies the timeout value for write transactions in region 0 and 1. Programming Mode: Quasi-dynamic Group 3" repeat 4. (list 0x0 0x1 0x2 0x3 )(list 0x0 0x8 0x10 0x18 ) group.long ($2+0xB0C)++0x3 line.long 0x0 "SARBASE$1,SAR Base Address Register n" hexmask.long.word 0x0 0.--11. 1. "BASE_ADDR,Base address for address region n specified as awaddr[UMCTL2_A_ADDRW-1:x] and araddr[UMCTL2_A_ADDRW-1:x] where x is determined by the minimum block size parameter UMCTL2_SARMINSIZE: (x=log2(block size)). Programming Mode: Static" repeat.end repeat 4. (list 0x0 0x1 0x2 0x3 )(list 0x0 0x8 0x10 0x18 ) group.long ($2+0xB10)++0x3 line.long 0x0 "SARSIZE$1,SAR Size Register n" hexmask.long.byte 0x0 0.--7. 1. "NBLOCKS,Number of blocks for address region n. This register determines the total size of the region in multiples of minimum block size as specified by the hardware parameter UMCTL2_SARMINSIZE. The register value is encoded as number of blocks = nblocks.." repeat.end group.long 0xB2C++0x3 line.long 0x0 "SBRCTL,Scrubber Control Register" hexmask.long.word 0x0 8.--20. 1. "SCRUB_INTERVAL,Scrub interval. (512 x scrub_interval) number of clock cycles between two scrub read commands. If set to 0 scrub commands are issued back-to-back. This mode of operation (scrub_interval=0) can typically be used for scrubbing the full.." bitfld.long 0x0 4.--6. "SCRUB_BURST,Scrub burst count. Determines the number of back-to-back scrub read commands that can be issued together when the controller is in one of the HW controlled low power modes with Sideband ECC both normal operation mode and low-power mode with.." "0,1,2,3,4,5,6,7" bitfld.long 0x0 2. "SCRUB_MODE,- scrub_mode:0 ECC scrubber performs reads - scrub_mode:1 ECC scrubber performs writes Programming Mode: Dynamic" "0,1" newline bitfld.long 0x0 1. "SCRUB_DURING_LOWPOWER,Continue scrubbing during low power. If set to 1 burst of scrubs is issued in hardware controlled low power modes. There are two such modes: automatically initiated by idleness or initiated by Hardware low power interface. If set.." "0,1" bitfld.long 0x0 0. "SCRUB_EN,Enables ECC scrubber. If set to 1 enables the scrubber to generate background read commands after the memories are initialized. If set to 0 disables the scrubber resets the address generator to 0 and clears the scrubber status. This bitfield.." "0,1" rgroup.long 0xB30++0x3 line.long 0x0 "SBRSTAT,Scrubber Status Register" bitfld.long 0x0 1. "SCRUB_DONE,Scrubber done. The controller sets this bit to 1 after full range of addresses are scrubbed once while scrub_interval is set to 0. Cleared if scrub_en is set to 0 (scrubber disabled) or scrub_interval is set to a non-zero value for normal.." "0,1" bitfld.long 0x0 0. "SCRUB_BUSY,Scrubber busy. The controller sets this bit to 1 when the scrubber logic has outstanding read commands being executed. Cleared when there are no active outstanding scrub reads in the system. Programming Mode: Dynamic" "0,1" group.long 0xB34++0x3 line.long 0x0 "SBRWDATA0,Scrubber Write Data Pattern0" hexmask.long 0x0 0.--31. 1. "SCRUB_PATTERN0,ECC Scrubber write data pattern for data bus[31:0] Programming Mode: Dynamic" group.long 0xB40++0xF line.long 0x0 "SBRSTART0,Scrubber Start Address Mask Register 0" hexmask.long 0x0 0.--31. 1. "SBR_ADDRESS_START_MASK_0,sbr_address_start_mask_0 holds the bits [31:0] of the starting address the ECC scrubber generates. The register must be programmed as explained in Address Configuration in ECC Scrub and Scrubber. The scrubber address registers.." line.long 0x4 "SBRSTART1,Scrubber Start Address Mask Register 1" hexmask.long.byte 0x4 0.--3. 1. "SBR_ADDRESS_START_MASK_1,sbr_address_start_mask_1 holds bits [MEMC_HIF_ADDR_WIDTH_MAX-1:32] of the starting address the ECC scrubber generates.The register must be programmed as explained in Address Configuration in ECC Scrub and Scrubber. The scrubber.." line.long 0x8 "SBRRANGE0,Scrubber Address Range Mask Register 0" hexmask.long 0x8 0.--31. 1. "SBR_ADDRESS_RANGE_MASK_0,sbr_address_range_mask_0 holds the bits [31:0] of the scrubber address range mask. The scrubber address range mask limits the address range that the ECC scrubber can generate.The register must be programmed as explained in.." line.long 0xC "SBRRANGE1,Scrubber Address Range Mask Register 1" hexmask.long.byte 0xC 0.--3. 1. "SBR_ADDRESS_RANGE_MASK_1,sbr_address_range_mask_1 holds the bits [MEMC_HIF_ADDR_WIDTH_MAX-1:32] of the scrubber address range mask. The scrubber address range mask limits the address range that the ECC scrubber can generate.The register must be.." rgroup.long 0xBF8++0x7 line.long 0x0 "UMCTL2_VER_NUMBER,UMCTL2 Version Number Register" hexmask.long 0x0 0.--31. 1. "VER_NUMBER,Indicates the Device Version Number value. Programming Mode: Static" line.long 0x4 "UMCTL2_VER_TYPE,UMCTL2 Version Type Register" hexmask.long 0x4 0.--31. 1. "VER_TYPE,Indicates the Device Version Type value. Programming Mode: Static" tree.end tree "UMCTL2_REGS_FREQ1 (uMCTL2 DDRC FREQ1 Registers)" base ad:0x8192 group.long 0x20++0x7 line.long 0x0 "DERATEEN,[FREQ1] Temperature Derate Enable Register" bitfld.long 0x0 12. "DERATE_MR4_TUF_DIS,Disables use of MR4 TUF flag (MR4[7]) bit. - 0 - Use MR4 TUF flag (MR4[7]) - 1 - Do not use MR4 TUF Flag (MR4[7]) For LPDDR4 it is recommended to set this register to 1. For LPDDR2 and LPDDR3 contact your memory vendor for.." "Use MR4 TUF flag,Do not use MR4 TUF Flag" newline bitfld.long 0x0 8.--10. "RC_DERATE_VALUE,Derate value of tRC for LPDDR4. - 0 - Derating uses +1 - 1 - Derating uses +2 - 2 - Derating uses +3 - 3 - Derating uses +4 Present only in designs configured to support LPDDR4. The required cycles for derating can be determined by.." "Derating uses +1,Derating uses +2,Derating uses +3,Derating uses +4,?,?,?,?" newline hexmask.long.byte 0x0 4.--7. 1. "DERATE_BYTE,This bit indicates which byte of the MRR data is used for derating. The maximum valid value depends on MEMC_DRAM_TOTAL_DATA_WIDTH. Present only in designs configured to support LPDDR2/LPDDR3/LPDDR4. Programming Mode: Static" newline bitfld.long 0x0 1.--2. "DERATE_VALUE,Derate value. - 0 - Derating uses +1 - 1 - Derating uses +2 Present only in designs configured to support LPDDR2/LPDDR3/LPDDR4. Set to 0 for all LPDDR2 speed grades as derating value of +1.875 ns is less than a core_ddrc_core_clk period. For.." "Derating uses +1,Derating uses +2,?,?" newline bitfld.long 0x0 0. "DERATE_ENABLE,Enables derating. - 0 - Timing parameter derating is disabled - 1 - Timing parameter derating is enabled using MR4 read value Present only in designs configured to support LPDDR2/LPDDR3/LPDDR4. This field must be set to '0' for.." "Timing parameter derating is disabled,Timing parameter derating is enabled using MR4.." line.long 0x4 "DERATEINT,[FREQ1] Temperature Derate Interval Register" hexmask.long 0x4 0.--31. 1. "MR4_READ_INTERVAL,Interval between two MR4 reads used to derate the timing parameters. Present only in designs configured to support LPDDR2/LPDDR3/LPDDR4. This register must not be set to zero. Unit: DFI clock cycles. Programming Mode: Static" group.long 0x34++0x3 line.long 0x0 "PWRTMG,[FREQ1] Low Power Timing Register" hexmask.long.byte 0x0 16.--23. 1. "SELFREF_TO_X32,After this many clocks of the DDRC command channel being idle the uMCTL2 automatically puts the SDRAM into self-refresh. The DDRC command channel is considered idle when there are no HIF commands outstanding. This must be enabled in the.." newline hexmask.long.byte 0x0 8.--15. 1. "T_DPD_X4096,Minimum deep power-down time. For mDDR value from the JEDEC specification is 0 as mDDR exits from deep power-down mode immediately after PWRCTL.deeppowerdown_en is de-asserted. For LPDDR2/LPDDR3 value from the JEDEC specification is 500us." newline hexmask.long.byte 0x0 0.--4. 1. "POWERDOWN_TO_X32,After this many clocks of the DDRC command channel being idle the uMCTL2 automatically puts the SDRAM into power-down. The DDRC command channel is considered idle when there are no HIF commands outstanding. This must be enabled in the.." group.long 0x50++0x3 line.long 0x0 "RFSHCTL0,[FREQ1] Refresh Control Register 0" hexmask.long.byte 0x0 20.--23. 1. "REFRESH_MARGIN,Threshold value in number of DFI clock cycles before the critical refresh or page timer expires. A critical refresh is to be issued before this threshold is reached. It is recommended that this not be changed from the default value.." newline hexmask.long.byte 0x0 12.--16. 1. "REFRESH_TO_X1_X32,If the refresh timer (tRFCnom also known as tREFI) has expired at least once then a speculative refresh may be performed. A speculative refresh is a refresh performed at a time when refresh would be useful. When the SDRAM bus is idle.." newline hexmask.long.byte 0x0 4.--9. 1. "REFRESH_BURST,The programmed value + 1 is the number of refresh timeouts that is allowed to accumulate before traffic is blocked and the refreshes are forced to execute. Closing pages to perform a refresh is a one-time penalty that must be paid for each.." newline bitfld.long 0x0 2. "PER_BANK_REFRESH,- 1 - Per bank refresh - 0 - All bank refresh Per bank refresh allows traffic to flow to other banks. Per bank refresh is not supported by all LPDDR2 devices but must be supported by all LPDDR3/LPDDR4 devices. Present only in designs.." "All bank refresh,Per bank refresh" group.long 0x64++0x7 line.long 0x0 "RFSHTMG,[FREQ1] Refresh Timing Register" bitfld.long 0x0 31. "T_RFC_NOM_X1_SEL,Specifies whether the RFSHTMG.t_rfc_nom_x1_x32 and RFSHCTL0.refresh_to_x1_x32 register values are x1 or x32. - 0 - x32 register values are used - 1 - x1 register values are used This applies only when per-bank refresh is enabled.." "x32 register values are used,x1 register values are used" newline hexmask.long.word 0x0 16.--27. 1. "T_RFC_NOM_X1_X32,Average time interval between refreshes per rank (Specification: 7.8us for DDR2 DDR3 and DDR4. See JEDEC specification for mDDR LPDDR2 LPDDR3 and LPDDR4). When the controller is operating in 1:1 mode set this register to.." newline bitfld.long 0x0 15. "LPDDR3_TREFBW_EN,Used only when LPDDR3 memory type is connected. Should only be changed when uMCTL2 is in reset. Specifies whether to use the tREFBW parameter (required by some LPDDR3 devices which comply with earlier versions of the LPDDR3 JEDEC.." "tREFBW parameter not used,tREFBW parameter used" newline hexmask.long.word 0x0 0.--9. 1. "T_RFC_MIN,tRFC (min): Minimum time from refresh to refresh or activate. When the controller is operating in 1:1 mode t_rfc_min must be set to RoundUp(tRFCmin/tCK). When the controller is operating in 1:2 mode t_rfc_min must be set to.." line.long 0x4 "RFSHTMG1,[FREQ1] Refresh Timing Register1" hexmask.long.byte 0x4 16.--23. 1. "T_PBR2PBR,LPDDR4:tpbR2pbR. Per-bank refresh to Per-bank refresh different bank Time. When the controller is operating in 1:1 frequency ratio mode program this to RoundUp(tpbR2pbR/tCK). When the controller is operating in 1:2 frequency ratio mode.." repeat 4. (list 0x3 0x4 0x6 0x7 )(list 0x0 0x4 0xC 0x10 ) group.long ($2+0xDC)++0x3 line.long 0x0 "INIT$1,[FREQ1] SDRAM Initialization Register 3" hexmask.long.word 0x0 16.--31. 1. "MR,DDR2:Indicates the value to write to MR register. Bit 8 is for DLL and the setting here is ignored. The uMCTL2 sets this bit appropriately. DDR3/DDR4: Value loaded into MR0 register. mDDR: Value to write to MR register. LPDDR2/LPDDR3/LPDDR4 - Value to.." newline hexmask.long.word 0x0 0.--15. 1. "EMR,DDR2: Indicates the value to write to EMR register. Bits 9:7 are for OCD and the setting in this register is ignored. The uMCTL2 sets those bits appropriately. DDR3/DDR4: Value to write to MR1 register Set bit 7 to 0. mDDR: Value to write to EMR.." repeat.end group.long 0xF4++0x3 line.long 0x0 "RANKCTL,[FREQ1] Rank Control Register" bitfld.long 0x0 26. "DIFF_RANK_WR_GAP_MSB,Only present for multi-rank configurations. 1-bit extension to be used when RANKCTL.diff_rank_wr_gap field needs to be set to a value greater than 0xF. Programming Mode: Quasi-dynamic Group 2" "?,bit extension to be used when RANKCTL" newline bitfld.long 0x0 24. "DIFF_RANK_RD_GAP_MSB,Only present for multi-rank configurations. 1-bit extension to be used when RANKCTL.diff_rank_rd_gap field needs to be set to a value greater than 0xF. Programming Mode: Quasi-dynamic Group 2" "?,bit extension to be used when RANKCTL" newline hexmask.long.byte 0x0 12.--15. 1. "MAX_RANK_WR,Only present for multi-rank configurations. Background: Writes to the same rank can be performed back-to-back. Writes to different ranks require additional gap dictated by the register RANKCTL.diff_rank_wr_gap. This is to avoid possible data.." newline hexmask.long.byte 0x0 8.--11. 1. "DIFF_RANK_WR_GAP,Only present for multi-rank configurations. Indicates the number of clocks of gap in data responses when performing consecutive writes to different ranks. This is used to switch the delays in the PHY to match the rank requirements. This.." newline hexmask.long.byte 0x0 4.--7. 1. "DIFF_RANK_RD_GAP,Only present for multi-rank configurations. Indicates the number of clocks of gap in data responses when performing consecutive reads to different ranks. This is used to switch the delays in the PHY to match the rank requirements. This.." newline hexmask.long.byte 0x0 0.--3. 1. "MAX_RANK_RD,Only present for multi-rank configurations. Background: Reads to the same rank can be performed back-to-back. Reads to different ranks require additional gap dictated by the register RANKCTL.diff_rank_rd_gap. This is to avoid possible data.." group.long 0x100++0x3F line.long 0x0 "DRAMTMG0,[FREQ1] SDRAM Timing Register 0" hexmask.long.byte 0x0 24.--30. 1. "WR2PRE,Specifies the minimum time between write and precharge to same bank. Specifications: WL + BL/2 + tWR = approximately 8 cycles + 15 ns = 14 clocks @400MHz and less for lower frequencies. where: - WL - Write latency - BL - Burst length. This must.." newline hexmask.long.byte 0x0 16.--21. 1. "T_FAW,tFAW - valid only when 8 or more banks(or banks x bank groups) are present. In 8-bank design at most 4 banks must be activated in a rolling window of tFAW cycles. When the controller is operating in 1:2 frequency ratio mode program this to.." newline hexmask.long.byte 0x0 8.--14. 1. "T_RAS_MAX,tRAS(max) - Specifies the maximum time between activate and precharge to same bank. This is the maximum time that a page can be kept open Minimum value of this register is 1. Zero is invalid. When the controller is operating in 1:1 frequency.." newline hexmask.long.byte 0x0 0.--5. 1. "T_RAS_MIN,tRAS(min) - Specifies the minimum time between activate and precharge to the same bank. When the controller is operating in 1:2 frequency mode 1T mode program this to tRAS(min)/2. No rounding up. When the controller is operating in 1:2.." line.long 0x4 "DRAMTMG1,[FREQ1] SDRAM Timing Register 1" hexmask.long.byte 0x4 16.--20. 1. "T_XP,tXP - Specifies the minimum time after power-down exit to any operation. For DDR3 this must be programmed to tXPDLL if slow powerdown exit is selected in MR0[12]. If C/A parity for DDR4 is used set to (tXP+PL) instead. If LPDDR4 is selected and.." newline hexmask.long.byte 0x4 8.--13. 1. "RD2PRE,tRTP - Specifies the minimum time from read to precharge of same bank. - DDR2 - tAL + BL/2 + max(tRTP 2) - 2 - DDR3 - tAL + max (tRTP 4) - DDR4 - Max of following two equations: tAL + max (tRTP 4) or RL + BL/2 - tRP (*). - mDDR - BL/2 - LPDDR2.." newline hexmask.long.byte 0x4 0.--6. 1. "T_RC,tRC - Specifies the minimum time between activates to same bank. When the controller is operating in 1:2 frequency ratio mode program this to (tRC/2) and round up to next integer value. Unit: DFI clock cycles. Programming Mode: Quasi-dynamic Group.." line.long 0x8 "DRAMTMG2,[FREQ1] SDRAM Timing Register 2" hexmask.long.byte 0x8 24.--29. 1. "WRITE_LATENCY,Set this field to WL. Indicates the Time from write command to write data on SDRAM interface. This must be set to WL. For mDDR it must be set to 1. Note that depending on the PHY if using RDIMM/LRDIMM it might be necessary to adjust the.." newline hexmask.long.byte 0x8 16.--21. 1. "READ_LATENCY,Set this field to RL. Indicates the time from read command to read data on SDRAM interface. This must be set to RL. Note that depending on the PHY if using RDIMM/LRDIMM it might be necessary to adjust the value of RL to compensate for the.." newline hexmask.long.byte 0x8 8.--13. 1. "RD2WR,DDR2/3/mDDR: RL + BL/2 + 2 - WL DDR4: RL + BL/2 + 1 + WR_PREAMBLE - WL LPDDR2/LPDDR3: RL + BL/2 + RU(tDQSCKmax/tCK) + 1 - WL LPDDR4(DQ ODT is Disabled): RL + BL/2 + RU(tDQSCKmax/tCK) + WR_PREAMBLE + RD_POSTAMBLE - WL LPDDR4(DQ ODT is Enabled): RL +.." newline hexmask.long.byte 0x8 0.--5. 1. "WR2RD,DDR4: CWL + PL + BL/2 + tWTR_L LPDDR2/3/4: WL + BL/2 + tWTR + 1 Others: CWL + BL/2 + tWTR In DDR4 minimum time from write command to read command for same bank group. In others minimum time from write command to read command. Includes time for.." line.long 0xC "DRAMTMG3,[FREQ1] SDRAM Timing Register 3" hexmask.long.word 0xC 20.--29. 1. "T_MRW,Indicates the time to wait after a mode register write or read (MRW or MRR). Present only in designs configured to support LPDDR2 LPDDR3 or LPDDR4. LPDDR2 typically requires value of 5. LPDDR3 typically requires value of 10. LPDDR4: Set this to.." newline hexmask.long.byte 0xC 12.--17. 1. "T_MRD,tMRD- Indicates the number of cycles to wait after a mode register write or read. Depending on the connected SDRAM tMRD represents: - DDR2/mDDR: Time from MRS to any command - DDR3/4: Time from MRS to MRS command - LPDDR2: not used - LPDDR3/4:.." newline hexmask.long.word 0xC 0.--9. 1. "T_MOD,tMOD - Parameter used only in DDR3 and DDR4. Indicates the number of cycles between load mode command and following non-load mode command. If C/A parity for DDR4 is used set to tMOD_PAR(tMOD+PL) instead. If CAL mode is enabled.." line.long 0x10 "DRAMTMG4,[FREQ1] SDRAM Timing Register 4" hexmask.long.byte 0x10 24.--28. 1. "T_RCD,tRCD - tAL: Indicates the minimum time from activate to read or write command to same bank. When the controller is operating in 1:2 frequency ratio mode program this to ((tRCD - tAL)/2) and round it up to the next integer value. Minimum value.." newline hexmask.long.byte 0x10 16.--19. 1. "T_CCD,DDR4: tCCD_L: This is the minimum time between two reads or two writes for same bank group. Others: tCCD: This is the minimum time between two reads or two writes. When the controller is operating in 1:2 frequency ratio mode program this to.." newline hexmask.long.byte 0x10 8.--11. 1. "T_RRD,DDR4: tRRD_L: This is the minimum time between activates from bank 'a' to bank 'b' for same bank group. Others: tRRD: Minimum time between activates from bank 'a' to bank 'b' When the controller is operating in 1:2 frequency ratio mode program.." newline hexmask.long.byte 0x10 0.--4. 1. "T_RP,tRP: Indicates the minimum time from single-bank precharge to activate of same bank. When the controller is operating in 1:1 frequency ratio mode t_rp must be set to RoundUp(tRP/tCK). When the controller is operating in 1:2 frequency ratio mode.." line.long 0x14 "DRAMTMG5,[FREQ1] SDRAM Timing Register 5" hexmask.long.byte 0x14 24.--27. 1. "T_CKSRX,This is the time before self-refresh Exit that CK is maintained as a valid clock before issuing SRX. Specifies the clock stable time before SRX. Recommended settings: - mDDR - 1 - LPDDR2 - 2 - LPDDR3 - 2 - LPDDR4 - tCKCKEH - DDR2 - 1 - DDR3 -.." newline hexmask.long.byte 0x14 16.--19. 1. "T_CKSRE,This is the time after self-refresh Down Entry that CK is maintained as a valid clock. Specifies the clock disable delay after SRE. Recommended settings: - mDDR - 0 - LPDDR2 - 2 - LPDDR3 - 2 - LPDDR4 - tCKELCK - DDR2 - 1 - DDR3 - Max (10 ns 5.." newline hexmask.long.byte 0x14 8.--13. 1. "T_CKESR,Indicates the minimum CKE low width for self-refresh or self-refresh power down entry to exit timing in memory clock cycles. Recommended settings: - mDDR - tRFC - LPDDR2 - tCKESR - LPDDR3 - tCKESR - LPDDR4 - max(tCKE tSR) - DDR2 - tCKE - DDR3 -.." newline hexmask.long.byte 0x14 0.--4. 1. "T_CKE,Indicates the minimum number of cycles of CKE HIGH/LOW during power-down and self-refresh. - LPDDR2/LPDDR3 mode - Set this to the larger of tCKE or tCKESR - LPDDR4 mode - Set this to the larger of tCKE or tSR - Non-LPDDR2/non-LPDDR3/non-LPDDR4.." line.long 0x18 "DRAMTMG6,[FREQ1] SDRAM Timing Register 6" hexmask.long.byte 0x18 24.--27. 1. "T_CKDPDE,This is the time after Deep Power Down Entry that CK is maintained as a valid clock. Specifies the clock disable delay after DPDE. Recommended settings: - mDDR: 0 - LPDDR2: 2 - LPDDR3: 2 When the controller is operating in 1:2 frequency ratio.." newline hexmask.long.byte 0x18 16.--19. 1. "T_CKDPDX,This is the time before Deep Power Down Exit that CK is maintained as a valid clock before issuing DPDX. Specifies the clock stable time before DPDX. Recommended settings: - mDDR - 1 - LPDDR2 - 2 - LPDDR3 - 2 When the controller is operating in.." newline hexmask.long.byte 0x18 0.--3. 1. "T_CKCSX,This is the time before Clock Stop Exit that CK is maintained as a valid clock before issuing Clock Stop Exit. Specifies the clock stable time before next command after Clock Stop Exit. Recommended settings: - mDDR - 1 - LPDDR2 - tXP + 2 - LPDDR3.." line.long 0x1C "DRAMTMG7,[FREQ1] SDRAM Timing Register 7" hexmask.long.byte 0x1C 8.--11. 1. "T_CKPDE,This is the time after Power Down Entry that CK is maintained as a valid clock. Specifies the clock disable delay after PDE. Recommended settings: - mDDR - 0 - LPDDR2 - 2 - LPDDR3 - 2 - LPDDR4 - tCKELCK When using DDR2/3/4 SDRAM this register.." newline hexmask.long.byte 0x1C 0.--3. 1. "T_CKPDX,This is the time before Power Down Exit that CK is maintained as a valid clock before issuing PDX. Specifies the clock stable time before PDX. Recommended settings: - mDDR - 0 - LPDDR2 - 2 - LPDDR3 - 2 - LPDDR4 - tCKCKEH When using DDR2/3/4 SDRAM.." line.long 0x20 "DRAMTMG8,[FREQ1] SDRAM Timing Register 8" hexmask.long.byte 0x20 24.--30. 1. "T_XS_FAST_X32,tXS_FAST: Exit self-refresh to ZQCL ZQCS and MRS (only CL WR RTP and Geardown mode). When the controller is operating in 1:2 frequency ratio mode program this to the previous value divided by 2 and round up to next integer value. Note:.." newline hexmask.long.byte 0x20 16.--22. 1. "T_XS_ABORT_X32,tXS_ABORT: Exit self-refresh to commands not requiring a locked DLL in self-refresh Abort. When the controller is operating in 1:2 frequency ratio mode program this to the previous value divided by 2 and round up to next integer value." newline hexmask.long.byte 0x20 8.--14. 1. "T_XS_DLL_X32,tXSDLL: Exit self-refresh to commands requiring a locked DLL. When the controller is operating in 1:2 frequency ratio mode program this to the previous value divided by 2 and round up to next integer value. Note: Used only for DDR2 DDR3.." newline hexmask.long.byte 0x20 0.--6. 1. "T_XS_X32,tXS: Exit self-refresh to commands not requiring a locked DLL. When the controller is operating in 1:2 frequency ratio mode program this to the previous value divided by 2 and round up to next integer value. Note: Used only for DDR2 DDR3 and.." line.long 0x24 "DRAMTMG9,[FREQ1] SDRAM Timing Register 9" bitfld.long 0x24 30. "DDR4_WR_PREAMBLE,DDR4 Write preamble mode. - 0 - 1tCK preamble - 1 - 2tCK preamble Present only with MEMC_FREQ_RATIO=2. Programming Mode: Quasi-dynamic Group 2 Group 4" "0,1" newline bitfld.long 0x24 16.--18. "T_CCD_S,tCCD_S: This is the minimum time between two reads or two writes for different bank group. For bank switching (from bank 'a' to bank 'b') the minimum time is this value + 1. When the controller is operating in 1:2 frequency ratio mode program.." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x24 8.--11. 1. "T_RRD_S,tRRD_S: This is the minimum time between activates from bank 'a' to bank 'b' for different bank group. When the controller is operating in 1:2 frequency ratio mode program this to (tRRD_S/2) and round it up to the next integer value. Present.." newline hexmask.long.byte 0x24 0.--5. 1. "WR2RD_S,CWL + PL + BL/2 + tWTR_S Minimum time from write command to read command for different bank group. Includes time for bus turnaround recovery times and all per-bank per-rank and global constraints. Present only in designs configured to support.." line.long 0x28 "DRAMTMG10,[FREQ1] SDRAM Timing Register 10" hexmask.long.byte 0x28 16.--20. 1. "T_SYNC_GEAR,Indicates the time between MRS command and the sync pulse time. This must be even number of clocks. For DDR4-2666 and DDR4-3200 this parameter is defined as tMOD(min)+4nCK tMOD(min) is greater of 24nCK or 15ns 15ns / .625ns = 24 Max value.." newline hexmask.long.byte 0x28 8.--12. 1. "T_CMD_GEAR,Indicates a sync pulse to first valid command. For DDR4-2666 and DDR4-3200 this parameter is defined as tMOD(min) tMOD(min) is greater of 24nCK or 15ns 15ns / .625ns = 24 Max value for this register is 24 When the controller is operating in.." newline bitfld.long 0x28 2.--3. "T_GEAR_SETUP,Indicates the geardown setup time. Minimum value of this register is 1. Zero is invalid. For DDR4-2666 and DDR4-3200 this parameter is defined as 2 clks When the controller is operating in 1:2 frequency ratio mode program this to.." "0,1,2,3" newline bitfld.long 0x28 0.--1. "T_GEAR_HOLD,Indicates the geardown hold time. Minimum value of this register is 1. Zero is invalid. For DDR4-2666 and DDR4-3200 this parameter is defined as 2 clks When the controller is operating in 1:2 frequency ratio mode program this to.." "0,1,2,3" line.long 0x2C "DRAMTMG11,[FREQ1] SDRAM Timing Register 11" hexmask.long.byte 0x2C 24.--30. 1. "POST_MPSM_GAP_X32,tXMPDLL: This is the minimum Exit MPSM to commands requiring a locked DLL. When the controller is operating in 1:2 frequency ratio mode program this to (tXMPDLL/2) and round it up to the next integer value. Present only in designs.." newline hexmask.long.byte 0x2C 16.--20. 1. "T_MPX_LH,tMPX_LH: This is the minimum CS_n Low hold time to CKE rising edge. When the controller is operating in 1:2 frequency ratio mode program this to RoundUp(tMPX_LH/2)+1. Present only in designs configured to support DDR4. Unit: DFI clock cycles." newline bitfld.long 0x2C 8.--9. "T_MPX_S,tMPX_S: This is the minimum time CS setup time to CKE. When the controller is operating in 1:2 frequency ratio mode program this to (tMPX_S/2) and round it up to the next integer value. Present only in designs configured to support DDR4. Unit:.." "0,1,2,3" newline hexmask.long.byte 0x2C 0.--4. 1. "T_CKMPE,tCKMPE: This is the minimum valid clock requirement after MPSM entry. Present only in designs configured to support DDR4. When the controller is operating in 1:2 frequency ratio mode divide the value calculated using the previous equation by 2.." line.long 0x30 "DRAMTMG12,[FREQ1] SDRAM Timing Register 12" hexmask.long.byte 0x30 24.--29. 1. "T_WR_MPR,This bit is used only in DDR4. Cycles between MPR Write and other command. Set this to tMOD + AL (or tMOD + PL + AL if C/A parity is also used). When the controller is operating in 1:2 frequency ratio mode program this to (tWR_MPR/2) and round.." newline bitfld.long 0x30 16.--17. "T_CMDCKE,tCMDCKE: Indicates the delay from valid command to CKE input LOW. Set this to the larger of tESCKE or tCMDCKE When the controller is operating in 1:2 frequency ratio mode program this to (max(tESCKE tCMDCKE)/2) and round it up to the next.." "0,1,2,3" newline hexmask.long.byte 0x30 0.--4. 1. "T_MRD_PDA,tMRD_PDA: This is the Mode Register Set command cycle time in PDA mode. When the controller is operating in 1:2 frequency ratio mode program this to (tMRD_PDA/2) and round it up to the next integer value. Unit: DFI clock cycles. Programming.." line.long 0x34 "DRAMTMG13,[FREQ1] SDRAM Timing Register 13" hexmask.long.byte 0x34 24.--30. 1. "ODTLOFF,LPDDR4: ODTLoff: This is the latency from CAS-2 command to ODToff reference. When the controller is operating in 1:2 frequency ratio mode program this to (ODTLoff/2) and round it up to the next integer value. Unit: DFI clock cycles. Programming.." newline hexmask.long.byte 0x34 16.--21. 1. "T_CCD_MW,LPDDR4: tCCDMW: This is the minimum time from write or masked write to masked write command for same bank. When the controller is operating in 1:2 frequency ratio mode program this to (tCCDMW/2) and round it up to the next integer value. Unit:.." newline bitfld.long 0x34 0.--2. "T_PPD,LPDDR4: tPPD: This is the minimum time from precharge to precharge command. When the controller is operating in 1:2 frequency ratio mode program this to (tPPD/2) and round it up to the next integer value. Unit: DFI clock cycles. Programming Mode:.." "?,?,?,?,tPPD: This is the minimum time from precharge to..,?,?,?" line.long 0x38 "DRAMTMG14,[FREQ1] SDRAM Timing Register 14" hexmask.long.word 0x38 0.--11. 1. "T_XSR,tXSR: This is the exit self-refresh to any command. When the controller is operating in 1:2 frequency ratio mode program this to the previous value divided by 2 and round up to next integer value. The value 0xfff is illegal for this register.." line.long 0x3C "DRAMTMG15,[FREQ1] SDRAM Timing Register 15" bitfld.long 0x3C 31. "EN_DFI_LP_T_STAB,- 1 - Enable using tSTAB when exiting DFI LP. This must be set when the PHY is stopping the clock during DFI LP to save maximum power. - 0 - Disable using tSTAB when exiting DFI LP. Programming Mode: Quasi-dynamic Group 2 Group 4" "Disable using tSTAB when exiting DFI LP,Enable using tSTAB when exiting DFI LP" newline hexmask.long.byte 0x3C 0.--7. 1. "T_STAB_X32,tSTAB: Stabilization time. It is required in the following two cases for DDR3/DDR4 RDIMM: - When exiting power saving mode if the clock is stopped after re-enabling it the clock must be stable for a time specified by tSTAB - In the case of.." group.long 0x180++0x3 line.long 0x0 "ZQCTL0,[FREQ1] ZQ Control Register 0" bitfld.long 0x0 31. "DIS_AUTO_ZQ,- 1 - Disable uMCTL2 generation of ZQCS/MPC(ZQ calibration) command. Register DBGCMD.zq_calib_short can be used instead to issue ZQ calibration request from APB module - 0 - Internally generate ZQCS/MPC(ZQ calibration) commands based on.." "Internally generate ZQCS/MPC,Disable uMCTL2 generation of ZQCS/MPC" newline bitfld.long 0x0 30. "DIS_SRX_ZQCL,- 1 - Disable issuing of ZQCL/MPC(ZQ calibration) command at self-refresh/SR-Powerdown exit. Only applicable when run in DDR3 or DDR4 or LPDDR2 or LPDDR3 or LPDDR4 mode - 0 - Enable issuing of ZQCL/MPC(ZQ calibration) command at.." "Enable issuing of ZQCL/MPC,Disable issuing of ZQCL/MPC" newline bitfld.long 0x0 29. "ZQ_RESISTOR_SHARED,- 1 - Denotes that ZQ resistor is shared between ranks. Means ZQinit/ZQCL/ZQCS/MPC(ZQ calibration) commands are sent to one rank at a time with tZQinit/tZQCL/tZQCS/tZQCAL/tZQLAT timing met between commands so that commands to different.." "ZQ resistor is not shared,Denotes that ZQ resistor is shared between ranks" newline bitfld.long 0x0 28. "DIS_MPSMX_ZQCL,- 1 - Disable issuing of ZQCL command at Maximum Power Saving Mode exit. Only applicable when run in DDR4 mode - 0 - Enable issuing of ZQCL command at Maximum Power Saving Mode exit. Only applicable when run in DDR4 mode This is only.." "Enable issuing of ZQCL command at Maximum Power..,Disable issuing of ZQCL command at Maximum Power.." newline hexmask.long.word 0x0 16.--26. 1. "T_ZQ_LONG_NOP,tZQoper for DDR3/DDR4 tZQCL for LPDDR2/LPDDR3 tZQCAL for LPDDR4: Number of DFI clock cycles of NOP required after a ZQCL (ZQ calibration long)/MPC(ZQ Start) command is issued to SDRAM. When the controller is operating in 1:2 frequency.." newline hexmask.long.word 0x0 0.--9. 1. "T_ZQ_SHORT_NOP,tZQCS for DDR3/DD4/LPDDR2/LPDDR3 tZQLAT for LPDDR4: Number of DFI clock cycles of NOP required after a ZQCS (ZQ calibration short)/MPC(ZQ Latch) command is issued to SDRAM. When the controller is operating in 1:2 frequency ratio mode.." group.long 0x190++0x7 line.long 0x0 "DFITMG0,[FREQ1] DFI Timing Register 0" hexmask.long.byte 0x0 24.--28. 1. "DFI_T_CTRL_DELAY,Specifies the number of DFI clock cycles after an assertion or de-assertion of the DFI control signals that the control signals at the PHY-DRAM interface reflect the assertion or de-assertion. If the DFI clock and the memory clock are.." newline bitfld.long 0x0 23. "DFI_RDDATA_USE_DFI_PHY_CLK,Defines whether dfi_rddata_en/dfi_rddata/dfi_rddata_valid is generated using HDR (DFI clock) or SDR (DFI PHY clock) values. Selects whether value in DFITMG0.dfi_t_rddata_en is in terms of HDR (DFI clock) or SDR (DFI PHY clock).." "Else,?" newline hexmask.long.byte 0x0 16.--22. 1. "DFI_T_RDDATA_EN,Time from the assertion of a read command on the DFI interface to the assertion of the dfi_rddata_en signal. Refer to PHY specification for correct value. This corresponds to the DFI parameter trddata_en. Note that depending on the PHY.." newline bitfld.long 0x0 15. "DFI_WRDATA_USE_DFI_PHY_CLK,Defines whether dfi_wrdata_en/dfi_wrdata/dfi_wrdata_mask is generated using HDR (DFI clock) or SDR (DFI PHY clock) values. Selects whether value in DFITMG0.dfi_tphy_wrlat is in terms of HDR (DFI clock) or SDR (DFI PHY clock).." "Else,?" newline hexmask.long.byte 0x0 8.--13. 1. "DFI_TPHY_WRDATA,Specifies the number of clock cycles between when dfi_wrdata_en is asserted to when the associated write data is driven on the dfi_wrdata signal. This corresponds to the DFI timing parameter tphy_wrdata. For more information on correct.." newline hexmask.long.byte 0x0 0.--5. 1. "DFI_TPHY_WRLAT,Write latency. Number of clocks from the write command to write data enable (dfi_wrdata_en). This corresponds to the DFI timing parameter tphy_wrlat. Refer to PHY specification for correct value.Note that depending on the PHY if using.." line.long 0x4 "DFITMG1,[FREQ1] DFI Timing Register 1" hexmask.long.byte 0x4 28.--31. 1. "DFI_T_CMD_LAT,Specifies the number of DFI PHY clock cycles between when the dfi_cs signal is asserted and when the associated command is driven. This field is used for CAL mode must be set to '0' or tCAL which matches the CAL mode register setting in.." newline bitfld.long 0x4 24.--25. "DFI_T_PARIN_LAT,Specifies the number of DFI PHY clock cycles between when the dfi_cs signal is asserted and when the associated dfi_parity_in signal is driven. Unit: DFI PHY clock cycles. Programming Mode: Quasi-dynamic Group 4" "0,1,2,3" newline hexmask.long.byte 0x4 16.--20. 1. "DFI_T_WRDATA_DELAY,Specifies the number of DFI clock cycles between when the dfi_wrdata_en signal is asserted and when the corresponding write data transfer is completed on the DRAM bus. This corresponds to the DFI timing parameter twrdata_delay. For.." newline hexmask.long.byte 0x4 8.--12. 1. "DFI_T_DRAM_CLK_DISABLE,Specifies the number of DFI clock cycles from the assertion of the dfi_dram_clk_disable signal on the DFI until the clock to the DRAM memory devices at the PHY-DRAM boundary maintains a low value. If the DFI clock and the memory.." newline hexmask.long.byte 0x4 0.--4. 1. "DFI_T_DRAM_CLK_ENABLE,Specifies the number of DFI clock cycles from the de-assertion of the dfi_dram_clk_disable signal on the DFI until the first valid rising edge of the clock to the DRAM memory devices at the PHY-DRAM boundary. If the DFI clock and.." group.long 0x1B4++0x7 line.long 0x0 "DFITMG2,[FREQ1] DFI Timing Register 2" hexmask.long.byte 0x0 8.--14. 1. "DFI_TPHY_RDCSLAT,specifies the number of DFI PHY clock cycles between when a read command is sent on the DFI control interface and when the associated dfi_rddata_cs signal is asserted. This corresponds to the DFI timing parameter tphy_rdcslat. Refer to.." newline hexmask.long.byte 0x0 0.--5. 1. "DFI_TPHY_WRCSLAT,Specifies the number of DFI PHY clock cycles between when a write command is sent on the DFI control interface and when the associated dfi_wrdata_cs signal is asserted. This corresponds to the DFI timing parameter tphy_wrcslat. For more.." line.long 0x4 "DFITMG3,[FREQ1] DFI Timing Register 3" hexmask.long.byte 0x4 0.--4. 1. "DFI_T_GEARDOWN_DELAY,The delay from dfi_geardown_en assertion to the time of the PHY being ready to receive commands. Refer to PHY specification for correct value. When the controller is operating in 1:2 frequency ratio mode program this to.." group.long 0x240++0x3 line.long 0x0 "ODTCFG,[FREQ1] ODT Configuration Register" hexmask.long.byte 0x0 24.--27. 1. "WR_ODT_HOLD,DFI PHY clock cycles to hold ODT for a write command. The minimum supported value is 2. Recommended values: DDR2: - BL8 - 0x5 (DDR2-400/533/667) 0x6 (DDR2-800) 0x7 (DDR2-1066) - BL4 - 0x3 (DDR2-400/533/667) 0x4 (DDR2-800) 0x5 (DDR2-1066).." newline hexmask.long.byte 0x0 16.--20. 1. "WR_ODT_DELAY,Indicates the delay in DFI PHY clock cycles from issuing a write command to setting ODT values associated with that command. ODT setting must remain constant for the entire time that DQS is driven by the uMCTL2. Recommended values: DDR2: -.." newline hexmask.long.byte 0x0 8.--11. 1. "RD_ODT_HOLD,DFI PHY clock cycles to hold ODT for a read command. The minimum supported value is 2. Recommended values: DDR2: - BL8 - 0x6 (not DDR2-1066) 0x7 (DDR2-1066) - BL4 - 0x4 (not DDR2-1066) 0x5 (DDR2-1066) DDR3: - BL8 - 0x6 DDR4: - BL8 - 5 +.." newline hexmask.long.byte 0x0 2.--6. 1. "RD_ODT_DELAY,Indicates the delay in DFI PHY clock cycles from issuing a read command to setting ODT values associated with that command. ODT setting must remain constant for the entire time that DQS is driven by the uMCTL2. Recommended values: DDR2: -.." tree.end tree "UMCTL2_REGS_FREQ2 (uMCTL2 DDRC FERQ2 Registers)" base ad:0x12288 group.long 0x20++0x7 line.long 0x0 "DERATEEN,[FREQ2] Temperature Derate Enable Register" bitfld.long 0x0 12. "DERATE_MR4_TUF_DIS,Disables use of MR4 TUF flag (MR4[7]) bit. - 0 - Use MR4 TUF flag (MR4[7]) - 1 - Do not use MR4 TUF Flag (MR4[7]) For LPDDR4 it is recommended to set this register to 1. For LPDDR2 and LPDDR3 contact your memory vendor for.." "Use MR4 TUF flag,Do not use MR4 TUF Flag" newline bitfld.long 0x0 8.--10. "RC_DERATE_VALUE,Derate value of tRC for LPDDR4. - 0 - Derating uses +1 - 1 - Derating uses +2 - 2 - Derating uses +3 - 3 - Derating uses +4 Present only in designs configured to support LPDDR4. The required cycles for derating can be determined by.." "Derating uses +1,Derating uses +2,Derating uses +3,Derating uses +4,?,?,?,?" newline hexmask.long.byte 0x0 4.--7. 1. "DERATE_BYTE,This bit indicates which byte of the MRR data is used for derating. The maximum valid value depends on MEMC_DRAM_TOTAL_DATA_WIDTH. Present only in designs configured to support LPDDR2/LPDDR3/LPDDR4. Programming Mode: Static" newline bitfld.long 0x0 1.--2. "DERATE_VALUE,Derate value. - 0 - Derating uses +1 - 1 - Derating uses +2 Present only in designs configured to support LPDDR2/LPDDR3/LPDDR4. Set to 0 for all LPDDR2 speed grades as derating value of +1.875 ns is less than a core_ddrc_core_clk period. For.." "Derating uses +1,Derating uses +2,?,?" newline bitfld.long 0x0 0. "DERATE_ENABLE,Enables derating. - 0 - Timing parameter derating is disabled - 1 - Timing parameter derating is enabled using MR4 read value Present only in designs configured to support LPDDR2/LPDDR3/LPDDR4. This field must be set to '0' for.." "Timing parameter derating is disabled,Timing parameter derating is enabled using MR4.." line.long 0x4 "DERATEINT,[FREQ2] Temperature Derate Interval Register" hexmask.long 0x4 0.--31. 1. "MR4_READ_INTERVAL,Interval between two MR4 reads used to derate the timing parameters. Present only in designs configured to support LPDDR2/LPDDR3/LPDDR4. This register must not be set to zero. Unit: DFI clock cycles. Programming Mode: Static" group.long 0x34++0x3 line.long 0x0 "PWRTMG,[FREQ2] Low Power Timing Register" hexmask.long.byte 0x0 16.--23. 1. "SELFREF_TO_X32,After this many clocks of the DDRC command channel being idle the uMCTL2 automatically puts the SDRAM into self-refresh. The DDRC command channel is considered idle when there are no HIF commands outstanding. This must be enabled in the.." newline hexmask.long.byte 0x0 8.--15. 1. "T_DPD_X4096,Minimum deep power-down time. For mDDR value from the JEDEC specification is 0 as mDDR exits from deep power-down mode immediately after PWRCTL.deeppowerdown_en is de-asserted. For LPDDR2/LPDDR3 value from the JEDEC specification is 500us." newline hexmask.long.byte 0x0 0.--4. 1. "POWERDOWN_TO_X32,After this many clocks of the DDRC command channel being idle the uMCTL2 automatically puts the SDRAM into power-down. The DDRC command channel is considered idle when there are no HIF commands outstanding. This must be enabled in the.." group.long 0x50++0x3 line.long 0x0 "RFSHCTL0,[FREQ2] Refresh Control Register 0" hexmask.long.byte 0x0 20.--23. 1. "REFRESH_MARGIN,Threshold value in number of DFI clock cycles before the critical refresh or page timer expires. A critical refresh is to be issued before this threshold is reached. It is recommended that this not be changed from the default value.." newline hexmask.long.byte 0x0 12.--16. 1. "REFRESH_TO_X1_X32,If the refresh timer (tRFCnom also known as tREFI) has expired at least once then a speculative refresh may be performed. A speculative refresh is a refresh performed at a time when refresh would be useful. When the SDRAM bus is idle.." newline hexmask.long.byte 0x0 4.--9. 1. "REFRESH_BURST,The programmed value + 1 is the number of refresh timeouts that is allowed to accumulate before traffic is blocked and the refreshes are forced to execute. Closing pages to perform a refresh is a one-time penalty that must be paid for each.." newline bitfld.long 0x0 2. "PER_BANK_REFRESH,- 1 - Per bank refresh - 0 - All bank refresh Per bank refresh allows traffic to flow to other banks. Per bank refresh is not supported by all LPDDR2 devices but must be supported by all LPDDR3/LPDDR4 devices. Present only in designs.." "All bank refresh,Per bank refresh" group.long 0x64++0x7 line.long 0x0 "RFSHTMG,[FREQ2] Refresh Timing Register" bitfld.long 0x0 31. "T_RFC_NOM_X1_SEL,Specifies whether the RFSHTMG.t_rfc_nom_x1_x32 and RFSHCTL0.refresh_to_x1_x32 register values are x1 or x32. - 0 - x32 register values are used - 1 - x1 register values are used This applies only when per-bank refresh is enabled.." "x32 register values are used,x1 register values are used" newline hexmask.long.word 0x0 16.--27. 1. "T_RFC_NOM_X1_X32,Average time interval between refreshes per rank (Specification: 7.8us for DDR2 DDR3 and DDR4. See JEDEC specification for mDDR LPDDR2 LPDDR3 and LPDDR4). When the controller is operating in 1:1 mode set this register to.." newline bitfld.long 0x0 15. "LPDDR3_TREFBW_EN,Used only when LPDDR3 memory type is connected. Should only be changed when uMCTL2 is in reset. Specifies whether to use the tREFBW parameter (required by some LPDDR3 devices which comply with earlier versions of the LPDDR3 JEDEC.." "tREFBW parameter not used,tREFBW parameter used" newline hexmask.long.word 0x0 0.--9. 1. "T_RFC_MIN,tRFC (min): Minimum time from refresh to refresh or activate. When the controller is operating in 1:1 mode t_rfc_min must be set to RoundUp(tRFCmin/tCK). When the controller is operating in 1:2 mode t_rfc_min must be set to.." line.long 0x4 "RFSHTMG1,[FREQ2] Refresh Timing Register1" hexmask.long.byte 0x4 16.--23. 1. "T_PBR2PBR,LPDDR4:tpbR2pbR. Per-bank refresh to Per-bank refresh different bank Time. When the controller is operating in 1:1 frequency ratio mode program this to RoundUp(tpbR2pbR/tCK). When the controller is operating in 1:2 frequency ratio mode.." repeat 4. (list 0x3 0x4 0x6 0x7 )(list 0x0 0x4 0xC 0x10 ) group.long ($2+0xDC)++0x3 line.long 0x0 "INIT$1,[FREQ2] SDRAM Initialization Register 3" hexmask.long.word 0x0 16.--31. 1. "MR,DDR2:Indicates the value to write to MR register. Bit 8 is for DLL and the setting here is ignored. The uMCTL2 sets this bit appropriately. DDR3/DDR4: Value loaded into MR0 register. mDDR: Value to write to MR register. LPDDR2/LPDDR3/LPDDR4 - Value to.." newline hexmask.long.word 0x0 0.--15. 1. "EMR,DDR2: Indicates the value to write to EMR register. Bits 9:7 are for OCD and the setting in this register is ignored. The uMCTL2 sets those bits appropriately. DDR3/DDR4: Value to write to MR1 register Set bit 7 to 0. mDDR: Value to write to EMR.." repeat.end group.long 0xF4++0x3 line.long 0x0 "RANKCTL,[FREQ2] Rank Control Register" bitfld.long 0x0 26. "DIFF_RANK_WR_GAP_MSB,Only present for multi-rank configurations. 1-bit extension to be used when RANKCTL.diff_rank_wr_gap field needs to be set to a value greater than 0xF. Programming Mode: Quasi-dynamic Group 2" "?,bit extension to be used when RANKCTL" newline bitfld.long 0x0 24. "DIFF_RANK_RD_GAP_MSB,Only present for multi-rank configurations. 1-bit extension to be used when RANKCTL.diff_rank_rd_gap field needs to be set to a value greater than 0xF. Programming Mode: Quasi-dynamic Group 2" "?,bit extension to be used when RANKCTL" newline hexmask.long.byte 0x0 12.--15. 1. "MAX_RANK_WR,Only present for multi-rank configurations. Background: Writes to the same rank can be performed back-to-back. Writes to different ranks require additional gap dictated by the register RANKCTL.diff_rank_wr_gap. This is to avoid possible data.." newline hexmask.long.byte 0x0 8.--11. 1. "DIFF_RANK_WR_GAP,Only present for multi-rank configurations. Indicates the number of clocks of gap in data responses when performing consecutive writes to different ranks. This is used to switch the delays in the PHY to match the rank requirements. This.." newline hexmask.long.byte 0x0 4.--7. 1. "DIFF_RANK_RD_GAP,Only present for multi-rank configurations. Indicates the number of clocks of gap in data responses when performing consecutive reads to different ranks. This is used to switch the delays in the PHY to match the rank requirements. This.." newline hexmask.long.byte 0x0 0.--3. 1. "MAX_RANK_RD,Only present for multi-rank configurations. Background: Reads to the same rank can be performed back-to-back. Reads to different ranks require additional gap dictated by the register RANKCTL.diff_rank_rd_gap. This is to avoid possible data.." group.long 0x100++0x3F line.long 0x0 "DRAMTMG0,[FREQ2] SDRAM Timing Register 0" hexmask.long.byte 0x0 24.--30. 1. "WR2PRE,Specifies the minimum time between write and precharge to same bank. Specifications: WL + BL/2 + tWR = approximately 8 cycles + 15 ns = 14 clocks @400MHz and less for lower frequencies. where: - WL - Write latency - BL - Burst length. This must.." newline hexmask.long.byte 0x0 16.--21. 1. "T_FAW,tFAW - valid only when 8 or more banks(or banks x bank groups) are present. In 8-bank design at most 4 banks must be activated in a rolling window of tFAW cycles. When the controller is operating in 1:2 frequency ratio mode program this to.." newline hexmask.long.byte 0x0 8.--14. 1. "T_RAS_MAX,tRAS(max) - Specifies the maximum time between activate and precharge to same bank. This is the maximum time that a page can be kept open Minimum value of this register is 1. Zero is invalid. When the controller is operating in 1:1 frequency.." newline hexmask.long.byte 0x0 0.--5. 1. "T_RAS_MIN,tRAS(min) - Specifies the minimum time between activate and precharge to the same bank. When the controller is operating in 1:2 frequency mode 1T mode program this to tRAS(min)/2. No rounding up. When the controller is operating in 1:2.." line.long 0x4 "DRAMTMG1,[FREQ2] SDRAM Timing Register 1" hexmask.long.byte 0x4 16.--20. 1. "T_XP,tXP - Specifies the minimum time after power-down exit to any operation. For DDR3 this must be programmed to tXPDLL if slow powerdown exit is selected in MR0[12]. If C/A parity for DDR4 is used set to (tXP+PL) instead. If LPDDR4 is selected and.." newline hexmask.long.byte 0x4 8.--13. 1. "RD2PRE,tRTP - Specifies the minimum time from read to precharge of same bank. - DDR2 - tAL + BL/2 + max(tRTP 2) - 2 - DDR3 - tAL + max (tRTP 4) - DDR4 - Max of following two equations: tAL + max (tRTP 4) or RL + BL/2 - tRP (*). - mDDR - BL/2 - LPDDR2.." newline hexmask.long.byte 0x4 0.--6. 1. "T_RC,tRC - Specifies the minimum time between activates to same bank. When the controller is operating in 1:2 frequency ratio mode program this to (tRC/2) and round up to next integer value. Unit: DFI clock cycles. Programming Mode: Quasi-dynamic Group.." line.long 0x8 "DRAMTMG2,[FREQ2] SDRAM Timing Register 2" hexmask.long.byte 0x8 24.--29. 1. "WRITE_LATENCY,Set this field to WL. Indicates the Time from write command to write data on SDRAM interface. This must be set to WL. For mDDR it must be set to 1. Note that depending on the PHY if using RDIMM/LRDIMM it might be necessary to adjust the.." newline hexmask.long.byte 0x8 16.--21. 1. "READ_LATENCY,Set this field to RL. Indicates the time from read command to read data on SDRAM interface. This must be set to RL. Note that depending on the PHY if using RDIMM/LRDIMM it might be necessary to adjust the value of RL to compensate for the.." newline hexmask.long.byte 0x8 8.--13. 1. "RD2WR,DDR2/3/mDDR: RL + BL/2 + 2 - WL DDR4: RL + BL/2 + 1 + WR_PREAMBLE - WL LPDDR2/LPDDR3: RL + BL/2 + RU(tDQSCKmax/tCK) + 1 - WL LPDDR4(DQ ODT is Disabled): RL + BL/2 + RU(tDQSCKmax/tCK) + WR_PREAMBLE + RD_POSTAMBLE - WL LPDDR4(DQ ODT is Enabled): RL +.." newline hexmask.long.byte 0x8 0.--5. 1. "WR2RD,DDR4: CWL + PL + BL/2 + tWTR_L LPDDR2/3/4: WL + BL/2 + tWTR + 1 Others: CWL + BL/2 + tWTR In DDR4 minimum time from write command to read command for same bank group. In others minimum time from write command to read command. Includes time for.." line.long 0xC "DRAMTMG3,[FREQ2] SDRAM Timing Register 3" hexmask.long.word 0xC 20.--29. 1. "T_MRW,Indicates the time to wait after a mode register write or read (MRW or MRR). Present only in designs configured to support LPDDR2 LPDDR3 or LPDDR4. LPDDR2 typically requires value of 5. LPDDR3 typically requires value of 10. LPDDR4: Set this to.." newline hexmask.long.byte 0xC 12.--17. 1. "T_MRD,tMRD- Indicates the number of cycles to wait after a mode register write or read. Depending on the connected SDRAM tMRD represents: - DDR2/mDDR: Time from MRS to any command - DDR3/4: Time from MRS to MRS command - LPDDR2: not used - LPDDR3/4:.." newline hexmask.long.word 0xC 0.--9. 1. "T_MOD,tMOD - Parameter used only in DDR3 and DDR4. Indicates the number of cycles between load mode command and following non-load mode command. If C/A parity for DDR4 is used set to tMOD_PAR(tMOD+PL) instead. If CAL mode is enabled.." line.long 0x10 "DRAMTMG4,[FREQ2] SDRAM Timing Register 4" hexmask.long.byte 0x10 24.--28. 1. "T_RCD,tRCD - tAL: Indicates the minimum time from activate to read or write command to same bank. When the controller is operating in 1:2 frequency ratio mode program this to ((tRCD - tAL)/2) and round it up to the next integer value. Minimum value.." newline hexmask.long.byte 0x10 16.--19. 1. "T_CCD,DDR4: tCCD_L: This is the minimum time between two reads or two writes for same bank group. Others: tCCD: This is the minimum time between two reads or two writes. When the controller is operating in 1:2 frequency ratio mode program this to.." newline hexmask.long.byte 0x10 8.--11. 1. "T_RRD,DDR4: tRRD_L: This is the minimum time between activates from bank 'a' to bank 'b' for same bank group. Others: tRRD: Minimum time between activates from bank 'a' to bank 'b' When the controller is operating in 1:2 frequency ratio mode program.." newline hexmask.long.byte 0x10 0.--4. 1. "T_RP,tRP: Indicates the minimum time from single-bank precharge to activate of same bank. When the controller is operating in 1:1 frequency ratio mode t_rp must be set to RoundUp(tRP/tCK). When the controller is operating in 1:2 frequency ratio mode.." line.long 0x14 "DRAMTMG5,[FREQ2] SDRAM Timing Register 5" hexmask.long.byte 0x14 24.--27. 1. "T_CKSRX,This is the time before self-refresh Exit that CK is maintained as a valid clock before issuing SRX. Specifies the clock stable time before SRX. Recommended settings: - mDDR - 1 - LPDDR2 - 2 - LPDDR3 - 2 - LPDDR4 - tCKCKEH - DDR2 - 1 - DDR3 -.." newline hexmask.long.byte 0x14 16.--19. 1. "T_CKSRE,This is the time after self-refresh Down Entry that CK is maintained as a valid clock. Specifies the clock disable delay after SRE. Recommended settings: - mDDR - 0 - LPDDR2 - 2 - LPDDR3 - 2 - LPDDR4 - tCKELCK - DDR2 - 1 - DDR3 - Max (10 ns 5.." newline hexmask.long.byte 0x14 8.--13. 1. "T_CKESR,Indicates the minimum CKE low width for self-refresh or self-refresh power down entry to exit timing in memory clock cycles. Recommended settings: - mDDR - tRFC - LPDDR2 - tCKESR - LPDDR3 - tCKESR - LPDDR4 - max(tCKE tSR) - DDR2 - tCKE - DDR3 -.." newline hexmask.long.byte 0x14 0.--4. 1. "T_CKE,Indicates the minimum number of cycles of CKE HIGH/LOW during power-down and self-refresh. - LPDDR2/LPDDR3 mode - Set this to the larger of tCKE or tCKESR - LPDDR4 mode - Set this to the larger of tCKE or tSR - Non-LPDDR2/non-LPDDR3/non-LPDDR4.." line.long 0x18 "DRAMTMG6,[FREQ2] SDRAM Timing Register 6" hexmask.long.byte 0x18 24.--27. 1. "T_CKDPDE,This is the time after Deep Power Down Entry that CK is maintained as a valid clock. Specifies the clock disable delay after DPDE. Recommended settings: - mDDR: 0 - LPDDR2: 2 - LPDDR3: 2 When the controller is operating in 1:2 frequency ratio.." newline hexmask.long.byte 0x18 16.--19. 1. "T_CKDPDX,This is the time before Deep Power Down Exit that CK is maintained as a valid clock before issuing DPDX. Specifies the clock stable time before DPDX. Recommended settings: - mDDR - 1 - LPDDR2 - 2 - LPDDR3 - 2 When the controller is operating in.." newline hexmask.long.byte 0x18 0.--3. 1. "T_CKCSX,This is the time before Clock Stop Exit that CK is maintained as a valid clock before issuing Clock Stop Exit. Specifies the clock stable time before next command after Clock Stop Exit. Recommended settings: - mDDR - 1 - LPDDR2 - tXP + 2 - LPDDR3.." line.long 0x1C "DRAMTMG7,[FREQ2] SDRAM Timing Register 7" hexmask.long.byte 0x1C 8.--11. 1. "T_CKPDE,This is the time after Power Down Entry that CK is maintained as a valid clock. Specifies the clock disable delay after PDE. Recommended settings: - mDDR - 0 - LPDDR2 - 2 - LPDDR3 - 2 - LPDDR4 - tCKELCK When using DDR2/3/4 SDRAM this register.." newline hexmask.long.byte 0x1C 0.--3. 1. "T_CKPDX,This is the time before Power Down Exit that CK is maintained as a valid clock before issuing PDX. Specifies the clock stable time before PDX. Recommended settings: - mDDR - 0 - LPDDR2 - 2 - LPDDR3 - 2 - LPDDR4 - tCKCKEH When using DDR2/3/4 SDRAM.." line.long 0x20 "DRAMTMG8,[FREQ2] SDRAM Timing Register 8" hexmask.long.byte 0x20 24.--30. 1. "T_XS_FAST_X32,tXS_FAST: Exit self-refresh to ZQCL ZQCS and MRS (only CL WR RTP and Geardown mode). When the controller is operating in 1:2 frequency ratio mode program this to the previous value divided by 2 and round up to next integer value. Note:.." newline hexmask.long.byte 0x20 16.--22. 1. "T_XS_ABORT_X32,tXS_ABORT: Exit self-refresh to commands not requiring a locked DLL in self-refresh Abort. When the controller is operating in 1:2 frequency ratio mode program this to the previous value divided by 2 and round up to next integer value." newline hexmask.long.byte 0x20 8.--14. 1. "T_XS_DLL_X32,tXSDLL: Exit self-refresh to commands requiring a locked DLL. When the controller is operating in 1:2 frequency ratio mode program this to the previous value divided by 2 and round up to next integer value. Note: Used only for DDR2 DDR3.." newline hexmask.long.byte 0x20 0.--6. 1. "T_XS_X32,tXS: Exit self-refresh to commands not requiring a locked DLL. When the controller is operating in 1:2 frequency ratio mode program this to the previous value divided by 2 and round up to next integer value. Note: Used only for DDR2 DDR3 and.." line.long 0x24 "DRAMTMG9,[FREQ2] SDRAM Timing Register 9" bitfld.long 0x24 30. "DDR4_WR_PREAMBLE,DDR4 Write preamble mode. - 0 - 1tCK preamble - 1 - 2tCK preamble Present only with MEMC_FREQ_RATIO=2. Programming Mode: Quasi-dynamic Group 2 Group 4" "0,1" newline bitfld.long 0x24 16.--18. "T_CCD_S,tCCD_S: This is the minimum time between two reads or two writes for different bank group. For bank switching (from bank 'a' to bank 'b') the minimum time is this value + 1. When the controller is operating in 1:2 frequency ratio mode program.." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x24 8.--11. 1. "T_RRD_S,tRRD_S: This is the minimum time between activates from bank 'a' to bank 'b' for different bank group. When the controller is operating in 1:2 frequency ratio mode program this to (tRRD_S/2) and round it up to the next integer value. Present.." newline hexmask.long.byte 0x24 0.--5. 1. "WR2RD_S,CWL + PL + BL/2 + tWTR_S Minimum time from write command to read command for different bank group. Includes time for bus turnaround recovery times and all per-bank per-rank and global constraints. Present only in designs configured to support.." line.long 0x28 "DRAMTMG10,[FREQ2] SDRAM Timing Register 10" hexmask.long.byte 0x28 16.--20. 1. "T_SYNC_GEAR,Indicates the time between MRS command and the sync pulse time. This must be even number of clocks. For DDR4-2666 and DDR4-3200 this parameter is defined as tMOD(min)+4nCK tMOD(min) is greater of 24nCK or 15ns 15ns / .625ns = 24 Max value.." newline hexmask.long.byte 0x28 8.--12. 1. "T_CMD_GEAR,Indicates a sync pulse to first valid command. For DDR4-2666 and DDR4-3200 this parameter is defined as tMOD(min) tMOD(min) is greater of 24nCK or 15ns 15ns / .625ns = 24 Max value for this register is 24 When the controller is operating in.." newline bitfld.long 0x28 2.--3. "T_GEAR_SETUP,Indicates the geardown setup time. Minimum value of this register is 1. Zero is invalid. For DDR4-2666 and DDR4-3200 this parameter is defined as 2 clks When the controller is operating in 1:2 frequency ratio mode program this to.." "0,1,2,3" newline bitfld.long 0x28 0.--1. "T_GEAR_HOLD,Indicates the geardown hold time. Minimum value of this register is 1. Zero is invalid. For DDR4-2666 and DDR4-3200 this parameter is defined as 2 clks When the controller is operating in 1:2 frequency ratio mode program this to.." "0,1,2,3" line.long 0x2C "DRAMTMG11,[FREQ2] SDRAM Timing Register 11" hexmask.long.byte 0x2C 24.--30. 1. "POST_MPSM_GAP_X32,tXMPDLL: This is the minimum Exit MPSM to commands requiring a locked DLL. When the controller is operating in 1:2 frequency ratio mode program this to (tXMPDLL/2) and round it up to the next integer value. Present only in designs.." newline hexmask.long.byte 0x2C 16.--20. 1. "T_MPX_LH,tMPX_LH: This is the minimum CS_n Low hold time to CKE rising edge. When the controller is operating in 1:2 frequency ratio mode program this to RoundUp(tMPX_LH/2)+1. Present only in designs configured to support DDR4. Unit: DFI clock cycles." newline bitfld.long 0x2C 8.--9. "T_MPX_S,tMPX_S: This is the minimum time CS setup time to CKE. When the controller is operating in 1:2 frequency ratio mode program this to (tMPX_S/2) and round it up to the next integer value. Present only in designs configured to support DDR4. Unit:.." "0,1,2,3" newline hexmask.long.byte 0x2C 0.--4. 1. "T_CKMPE,tCKMPE: This is the minimum valid clock requirement after MPSM entry. Present only in designs configured to support DDR4. When the controller is operating in 1:2 frequency ratio mode divide the value calculated using the previous equation by 2.." line.long 0x30 "DRAMTMG12,[FREQ2] SDRAM Timing Register 12" hexmask.long.byte 0x30 24.--29. 1. "T_WR_MPR,This bit is used only in DDR4. Cycles between MPR Write and other command. Set this to tMOD + AL (or tMOD + PL + AL if C/A parity is also used). When the controller is operating in 1:2 frequency ratio mode program this to (tWR_MPR/2) and round.." newline bitfld.long 0x30 16.--17. "T_CMDCKE,tCMDCKE: Indicates the delay from valid command to CKE input LOW. Set this to the larger of tESCKE or tCMDCKE When the controller is operating in 1:2 frequency ratio mode program this to (max(tESCKE tCMDCKE)/2) and round it up to the next.." "0,1,2,3" newline hexmask.long.byte 0x30 0.--4. 1. "T_MRD_PDA,tMRD_PDA: This is the Mode Register Set command cycle time in PDA mode. When the controller is operating in 1:2 frequency ratio mode program this to (tMRD_PDA/2) and round it up to the next integer value. Unit: DFI clock cycles. Programming.." line.long 0x34 "DRAMTMG13,[FREQ2] SDRAM Timing Register 13" hexmask.long.byte 0x34 24.--30. 1. "ODTLOFF,LPDDR4: ODTLoff: This is the latency from CAS-2 command to ODToff reference. When the controller is operating in 1:2 frequency ratio mode program this to (ODTLoff/2) and round it up to the next integer value. Unit: DFI clock cycles. Programming.." newline hexmask.long.byte 0x34 16.--21. 1. "T_CCD_MW,LPDDR4: tCCDMW: This is the minimum time from write or masked write to masked write command for same bank. When the controller is operating in 1:2 frequency ratio mode program this to (tCCDMW/2) and round it up to the next integer value. Unit:.." newline bitfld.long 0x34 0.--2. "T_PPD,LPDDR4: tPPD: This is the minimum time from precharge to precharge command. When the controller is operating in 1:2 frequency ratio mode program this to (tPPD/2) and round it up to the next integer value. Unit: DFI clock cycles. Programming Mode:.." "?,?,?,?,tPPD: This is the minimum time from precharge to..,?,?,?" line.long 0x38 "DRAMTMG14,[FREQ2] SDRAM Timing Register 14" hexmask.long.word 0x38 0.--11. 1. "T_XSR,tXSR: This is the exit self-refresh to any command. When the controller is operating in 1:2 frequency ratio mode program this to the previous value divided by 2 and round up to next integer value. The value 0xfff is illegal for this register.." line.long 0x3C "DRAMTMG15,[FREQ2] SDRAM Timing Register 15" bitfld.long 0x3C 31. "EN_DFI_LP_T_STAB,- 1 - Enable using tSTAB when exiting DFI LP. This must be set when the PHY is stopping the clock during DFI LP to save maximum power. - 0 - Disable using tSTAB when exiting DFI LP. Programming Mode: Quasi-dynamic Group 2 Group 4" "Disable using tSTAB when exiting DFI LP,Enable using tSTAB when exiting DFI LP" newline hexmask.long.byte 0x3C 0.--7. 1. "T_STAB_X32,tSTAB: Stabilization time. It is required in the following two cases for DDR3/DDR4 RDIMM: - When exiting power saving mode if the clock is stopped after re-enabling it the clock must be stable for a time specified by tSTAB - In the case of.." group.long 0x180++0x3 line.long 0x0 "ZQCTL0,[FREQ2] ZQ Control Register 0" bitfld.long 0x0 31. "DIS_AUTO_ZQ,- 1 - Disable uMCTL2 generation of ZQCS/MPC(ZQ calibration) command. Register DBGCMD.zq_calib_short can be used instead to issue ZQ calibration request from APB module - 0 - Internally generate ZQCS/MPC(ZQ calibration) commands based on.." "Internally generate ZQCS/MPC,Disable uMCTL2 generation of ZQCS/MPC" newline bitfld.long 0x0 30. "DIS_SRX_ZQCL,- 1 - Disable issuing of ZQCL/MPC(ZQ calibration) command at self-refresh/SR-Powerdown exit. Only applicable when run in DDR3 or DDR4 or LPDDR2 or LPDDR3 or LPDDR4 mode - 0 - Enable issuing of ZQCL/MPC(ZQ calibration) command at.." "Enable issuing of ZQCL/MPC,Disable issuing of ZQCL/MPC" newline bitfld.long 0x0 29. "ZQ_RESISTOR_SHARED,- 1 - Denotes that ZQ resistor is shared between ranks. Means ZQinit/ZQCL/ZQCS/MPC(ZQ calibration) commands are sent to one rank at a time with tZQinit/tZQCL/tZQCS/tZQCAL/tZQLAT timing met between commands so that commands to different.." "ZQ resistor is not shared,Denotes that ZQ resistor is shared between ranks" newline bitfld.long 0x0 28. "DIS_MPSMX_ZQCL,- 1 - Disable issuing of ZQCL command at Maximum Power Saving Mode exit. Only applicable when run in DDR4 mode - 0 - Enable issuing of ZQCL command at Maximum Power Saving Mode exit. Only applicable when run in DDR4 mode This is only.." "Enable issuing of ZQCL command at Maximum Power..,Disable issuing of ZQCL command at Maximum Power.." newline hexmask.long.word 0x0 16.--26. 1. "T_ZQ_LONG_NOP,tZQoper for DDR3/DDR4 tZQCL for LPDDR2/LPDDR3 tZQCAL for LPDDR4: Number of DFI clock cycles of NOP required after a ZQCL (ZQ calibration long)/MPC(ZQ Start) command is issued to SDRAM. When the controller is operating in 1:2 frequency.." newline hexmask.long.word 0x0 0.--9. 1. "T_ZQ_SHORT_NOP,tZQCS for DDR3/DD4/LPDDR2/LPDDR3 tZQLAT for LPDDR4: Number of DFI clock cycles of NOP required after a ZQCS (ZQ calibration short)/MPC(ZQ Latch) command is issued to SDRAM. When the controller is operating in 1:2 frequency ratio mode.." group.long 0x190++0x7 line.long 0x0 "DFITMG0,[FREQ2] DFI Timing Register 0" hexmask.long.byte 0x0 24.--28. 1. "DFI_T_CTRL_DELAY,Specifies the number of DFI clock cycles after an assertion or de-assertion of the DFI control signals that the control signals at the PHY-DRAM interface reflect the assertion or de-assertion. If the DFI clock and the memory clock are.." newline bitfld.long 0x0 23. "DFI_RDDATA_USE_DFI_PHY_CLK,Defines whether dfi_rddata_en/dfi_rddata/dfi_rddata_valid is generated using HDR (DFI clock) or SDR (DFI PHY clock) values. Selects whether value in DFITMG0.dfi_t_rddata_en is in terms of HDR (DFI clock) or SDR (DFI PHY clock).." "Else,?" newline hexmask.long.byte 0x0 16.--22. 1. "DFI_T_RDDATA_EN,Time from the assertion of a read command on the DFI interface to the assertion of the dfi_rddata_en signal. Refer to PHY specification for correct value. This corresponds to the DFI parameter trddata_en. Note that depending on the PHY.." newline bitfld.long 0x0 15. "DFI_WRDATA_USE_DFI_PHY_CLK,Defines whether dfi_wrdata_en/dfi_wrdata/dfi_wrdata_mask is generated using HDR (DFI clock) or SDR (DFI PHY clock) values. Selects whether value in DFITMG0.dfi_tphy_wrlat is in terms of HDR (DFI clock) or SDR (DFI PHY clock).." "Else,?" newline hexmask.long.byte 0x0 8.--13. 1. "DFI_TPHY_WRDATA,Specifies the number of clock cycles between when dfi_wrdata_en is asserted to when the associated write data is driven on the dfi_wrdata signal. This corresponds to the DFI timing parameter tphy_wrdata. For more information on correct.." newline hexmask.long.byte 0x0 0.--5. 1. "DFI_TPHY_WRLAT,Write latency. Number of clocks from the write command to write data enable (dfi_wrdata_en). This corresponds to the DFI timing parameter tphy_wrlat. Refer to PHY specification for correct value.Note that depending on the PHY if using.." line.long 0x4 "DFITMG1,[FREQ2] DFI Timing Register 1" hexmask.long.byte 0x4 28.--31. 1. "DFI_T_CMD_LAT,Specifies the number of DFI PHY clock cycles between when the dfi_cs signal is asserted and when the associated command is driven. This field is used for CAL mode must be set to '0' or tCAL which matches the CAL mode register setting in.." newline bitfld.long 0x4 24.--25. "DFI_T_PARIN_LAT,Specifies the number of DFI PHY clock cycles between when the dfi_cs signal is asserted and when the associated dfi_parity_in signal is driven. Unit: DFI PHY clock cycles. Programming Mode: Quasi-dynamic Group 4" "0,1,2,3" newline hexmask.long.byte 0x4 16.--20. 1. "DFI_T_WRDATA_DELAY,Specifies the number of DFI clock cycles between when the dfi_wrdata_en signal is asserted and when the corresponding write data transfer is completed on the DRAM bus. This corresponds to the DFI timing parameter twrdata_delay. For.." newline hexmask.long.byte 0x4 8.--12. 1. "DFI_T_DRAM_CLK_DISABLE,Specifies the number of DFI clock cycles from the assertion of the dfi_dram_clk_disable signal on the DFI until the clock to the DRAM memory devices at the PHY-DRAM boundary maintains a low value. If the DFI clock and the memory.." newline hexmask.long.byte 0x4 0.--4. 1. "DFI_T_DRAM_CLK_ENABLE,Specifies the number of DFI clock cycles from the de-assertion of the dfi_dram_clk_disable signal on the DFI until the first valid rising edge of the clock to the DRAM memory devices at the PHY-DRAM boundary. If the DFI clock and.." group.long 0x1B4++0x7 line.long 0x0 "DFITMG2,[FREQ2] DFI Timing Register 2" hexmask.long.byte 0x0 8.--14. 1. "DFI_TPHY_RDCSLAT,specifies the number of DFI PHY clock cycles between when a read command is sent on the DFI control interface and when the associated dfi_rddata_cs signal is asserted. This corresponds to the DFI timing parameter tphy_rdcslat. Refer to.." newline hexmask.long.byte 0x0 0.--5. 1. "DFI_TPHY_WRCSLAT,Specifies the number of DFI PHY clock cycles between when a write command is sent on the DFI control interface and when the associated dfi_wrdata_cs signal is asserted. This corresponds to the DFI timing parameter tphy_wrcslat. For more.." line.long 0x4 "DFITMG3,[FREQ2] DFI Timing Register 3" hexmask.long.byte 0x4 0.--4. 1. "DFI_T_GEARDOWN_DELAY,The delay from dfi_geardown_en assertion to the time of the PHY being ready to receive commands. Refer to PHY specification for correct value. When the controller is operating in 1:2 frequency ratio mode program this to.." group.long 0x240++0x3 line.long 0x0 "ODTCFG,[FREQ2] ODT Configuration Register" hexmask.long.byte 0x0 24.--27. 1. "WR_ODT_HOLD,DFI PHY clock cycles to hold ODT for a write command. The minimum supported value is 2. Recommended values: DDR2: - BL8 - 0x5 (DDR2-400/533/667) 0x6 (DDR2-800) 0x7 (DDR2-1066) - BL4 - 0x3 (DDR2-400/533/667) 0x4 (DDR2-800) 0x5 (DDR2-1066).." newline hexmask.long.byte 0x0 16.--20. 1. "WR_ODT_DELAY,Indicates the delay in DFI PHY clock cycles from issuing a write command to setting ODT values associated with that command. ODT setting must remain constant for the entire time that DQS is driven by the uMCTL2. Recommended values: DDR2: -.." newline hexmask.long.byte 0x0 8.--11. 1. "RD_ODT_HOLD,DFI PHY clock cycles to hold ODT for a read command. The minimum supported value is 2. Recommended values: DDR2: - BL8 - 0x6 (not DDR2-1066) 0x7 (DDR2-1066) - BL4 - 0x4 (not DDR2-1066) 0x5 (DDR2-1066) DDR3: - BL8 - 0x6 DDR4: - BL8 - 5 +.." newline hexmask.long.byte 0x0 2.--6. 1. "RD_ODT_DELAY,Indicates the delay in DFI PHY clock cycles from issuing a read command to setting ODT values associated with that command. ODT setting must remain constant for the entire time that DQS is driven by the uMCTL2. Recommended values: DDR2: -.." tree.end tree "UMCTL2_REGS_FREQ3 (uMCTL2 DDRC FREQ3 Registers)" base ad:0x16384 group.long 0x20++0x7 line.long 0x0 "DERATEEN,[FREQ3] Temperature Derate Enable Register" bitfld.long 0x0 12. "DERATE_MR4_TUF_DIS,Disables use of MR4 TUF flag (MR4[7]) bit. - 0 - Use MR4 TUF flag (MR4[7]) - 1 - Do not use MR4 TUF Flag (MR4[7]) For LPDDR4 it is recommended to set this register to 1. For LPDDR2 and LPDDR3 contact your memory vendor for.." "Use MR4 TUF flag,Do not use MR4 TUF Flag" newline bitfld.long 0x0 8.--10. "RC_DERATE_VALUE,Derate value of tRC for LPDDR4. - 0 - Derating uses +1 - 1 - Derating uses +2 - 2 - Derating uses +3 - 3 - Derating uses +4 Present only in designs configured to support LPDDR4. The required cycles for derating can be determined by.." "Derating uses +1,Derating uses +2,Derating uses +3,Derating uses +4,?,?,?,?" newline hexmask.long.byte 0x0 4.--7. 1. "DERATE_BYTE,This bit indicates which byte of the MRR data is used for derating. The maximum valid value depends on MEMC_DRAM_TOTAL_DATA_WIDTH. Present only in designs configured to support LPDDR2/LPDDR3/LPDDR4. Programming Mode: Static" newline bitfld.long 0x0 1.--2. "DERATE_VALUE,Derate value. - 0 - Derating uses +1 - 1 - Derating uses +2 Present only in designs configured to support LPDDR2/LPDDR3/LPDDR4. Set to 0 for all LPDDR2 speed grades as derating value of +1.875 ns is less than a core_ddrc_core_clk period. For.." "Derating uses +1,Derating uses +2,?,?" newline bitfld.long 0x0 0. "DERATE_ENABLE,Enables derating. - 0 - Timing parameter derating is disabled - 1 - Timing parameter derating is enabled using MR4 read value Present only in designs configured to support LPDDR2/LPDDR3/LPDDR4. This field must be set to '0' for.." "Timing parameter derating is disabled,Timing parameter derating is enabled using MR4.." line.long 0x4 "DERATEINT,[FREQ3] Temperature Derate Interval Register" hexmask.long 0x4 0.--31. 1. "MR4_READ_INTERVAL,Interval between two MR4 reads used to derate the timing parameters. Present only in designs configured to support LPDDR2/LPDDR3/LPDDR4. This register must not be set to zero. Unit: DFI clock cycles. Programming Mode: Static" group.long 0x34++0x3 line.long 0x0 "PWRTMG,[FREQ3] Low Power Timing Register" hexmask.long.byte 0x0 16.--23. 1. "SELFREF_TO_X32,After this many clocks of the DDRC command channel being idle the uMCTL2 automatically puts the SDRAM into self-refresh. The DDRC command channel is considered idle when there are no HIF commands outstanding. This must be enabled in the.." newline hexmask.long.byte 0x0 8.--15. 1. "T_DPD_X4096,Minimum deep power-down time. For mDDR value from the JEDEC specification is 0 as mDDR exits from deep power-down mode immediately after PWRCTL.deeppowerdown_en is de-asserted. For LPDDR2/LPDDR3 value from the JEDEC specification is 500us." newline hexmask.long.byte 0x0 0.--4. 1. "POWERDOWN_TO_X32,After this many clocks of the DDRC command channel being idle the uMCTL2 automatically puts the SDRAM into power-down. The DDRC command channel is considered idle when there are no HIF commands outstanding. This must be enabled in the.." group.long 0x50++0x3 line.long 0x0 "RFSHCTL0,[FREQ3] Refresh Control Register 0" hexmask.long.byte 0x0 20.--23. 1. "REFRESH_MARGIN,Threshold value in number of DFI clock cycles before the critical refresh or page timer expires. A critical refresh is to be issued before this threshold is reached. It is recommended that this not be changed from the default value.." newline hexmask.long.byte 0x0 12.--16. 1. "REFRESH_TO_X1_X32,If the refresh timer (tRFCnom also known as tREFI) has expired at least once then a speculative refresh may be performed. A speculative refresh is a refresh performed at a time when refresh would be useful. When the SDRAM bus is idle.." newline hexmask.long.byte 0x0 4.--9. 1. "REFRESH_BURST,The programmed value + 1 is the number of refresh timeouts that is allowed to accumulate before traffic is blocked and the refreshes are forced to execute. Closing pages to perform a refresh is a one-time penalty that must be paid for each.." newline bitfld.long 0x0 2. "PER_BANK_REFRESH,- 1 - Per bank refresh - 0 - All bank refresh Per bank refresh allows traffic to flow to other banks. Per bank refresh is not supported by all LPDDR2 devices but must be supported by all LPDDR3/LPDDR4 devices. Present only in designs.." "All bank refresh,Per bank refresh" group.long 0x64++0x7 line.long 0x0 "RFSHTMG,[FREQ3] Refresh Timing Register" bitfld.long 0x0 31. "T_RFC_NOM_X1_SEL,Specifies whether the RFSHTMG.t_rfc_nom_x1_x32 and RFSHCTL0.refresh_to_x1_x32 register values are x1 or x32. - 0 - x32 register values are used - 1 - x1 register values are used This applies only when per-bank refresh is enabled.." "x32 register values are used,x1 register values are used" newline hexmask.long.word 0x0 16.--27. 1. "T_RFC_NOM_X1_X32,Average time interval between refreshes per rank (Specification: 7.8us for DDR2 DDR3 and DDR4. See JEDEC specification for mDDR LPDDR2 LPDDR3 and LPDDR4). When the controller is operating in 1:1 mode set this register to.." newline bitfld.long 0x0 15. "LPDDR3_TREFBW_EN,Used only when LPDDR3 memory type is connected. Should only be changed when uMCTL2 is in reset. Specifies whether to use the tREFBW parameter (required by some LPDDR3 devices which comply with earlier versions of the LPDDR3 JEDEC.." "tREFBW parameter not used,tREFBW parameter used" newline hexmask.long.word 0x0 0.--9. 1. "T_RFC_MIN,tRFC (min): Minimum time from refresh to refresh or activate. When the controller is operating in 1:1 mode t_rfc_min must be set to RoundUp(tRFCmin/tCK). When the controller is operating in 1:2 mode t_rfc_min must be set to.." line.long 0x4 "RFSHTMG1,[FREQ3] Refresh Timing Register1" hexmask.long.byte 0x4 16.--23. 1. "T_PBR2PBR,LPDDR4:tpbR2pbR. Per-bank refresh to Per-bank refresh different bank Time. When the controller is operating in 1:1 frequency ratio mode program this to RoundUp(tpbR2pbR/tCK). When the controller is operating in 1:2 frequency ratio mode.." repeat 4. (list 0x3 0x4 0x6 0x7 )(list 0x0 0x4 0xC 0x10 ) group.long ($2+0xDC)++0x3 line.long 0x0 "INIT$1,[FREQ3] SDRAM Initialization Register 3" hexmask.long.word 0x0 16.--31. 1. "MR,DDR2:Indicates the value to write to MR register. Bit 8 is for DLL and the setting here is ignored. The uMCTL2 sets this bit appropriately. DDR3/DDR4: Value loaded into MR0 register. mDDR: Value to write to MR register. LPDDR2/LPDDR3/LPDDR4 - Value to.." newline hexmask.long.word 0x0 0.--15. 1. "EMR,DDR2: Indicates the value to write to EMR register. Bits 9:7 are for OCD and the setting in this register is ignored. The uMCTL2 sets those bits appropriately. DDR3/DDR4: Value to write to MR1 register Set bit 7 to 0. mDDR: Value to write to EMR.." repeat.end group.long 0xF4++0x3 line.long 0x0 "RANKCTL,[FREQ3] Rank Control Register" bitfld.long 0x0 26. "DIFF_RANK_WR_GAP_MSB,Only present for multi-rank configurations. 1-bit extension to be used when RANKCTL.diff_rank_wr_gap field needs to be set to a value greater than 0xF. Programming Mode: Quasi-dynamic Group 2" "?,bit extension to be used when RANKCTL" newline bitfld.long 0x0 24. "DIFF_RANK_RD_GAP_MSB,Only present for multi-rank configurations. 1-bit extension to be used when RANKCTL.diff_rank_rd_gap field needs to be set to a value greater than 0xF. Programming Mode: Quasi-dynamic Group 2" "?,bit extension to be used when RANKCTL" newline hexmask.long.byte 0x0 12.--15. 1. "MAX_RANK_WR,Only present for multi-rank configurations. Background: Writes to the same rank can be performed back-to-back. Writes to different ranks require additional gap dictated by the register RANKCTL.diff_rank_wr_gap. This is to avoid possible data.." newline hexmask.long.byte 0x0 8.--11. 1. "DIFF_RANK_WR_GAP,Only present for multi-rank configurations. Indicates the number of clocks of gap in data responses when performing consecutive writes to different ranks. This is used to switch the delays in the PHY to match the rank requirements. This.." newline hexmask.long.byte 0x0 4.--7. 1. "DIFF_RANK_RD_GAP,Only present for multi-rank configurations. Indicates the number of clocks of gap in data responses when performing consecutive reads to different ranks. This is used to switch the delays in the PHY to match the rank requirements. This.." newline hexmask.long.byte 0x0 0.--3. 1. "MAX_RANK_RD,Only present for multi-rank configurations. Background: Reads to the same rank can be performed back-to-back. Reads to different ranks require additional gap dictated by the register RANKCTL.diff_rank_rd_gap. This is to avoid possible data.." group.long 0x100++0x3F line.long 0x0 "DRAMTMG0,[FREQ3] SDRAM Timing Register 0" hexmask.long.byte 0x0 24.--30. 1. "WR2PRE,Specifies the minimum time between write and precharge to same bank. Specifications: WL + BL/2 + tWR = approximately 8 cycles + 15 ns = 14 clocks @400MHz and less for lower frequencies. where: - WL - Write latency - BL - Burst length. This must.." newline hexmask.long.byte 0x0 16.--21. 1. "T_FAW,tFAW - valid only when 8 or more banks(or banks x bank groups) are present. In 8-bank design at most 4 banks must be activated in a rolling window of tFAW cycles. When the controller is operating in 1:2 frequency ratio mode program this to.." newline hexmask.long.byte 0x0 8.--14. 1. "T_RAS_MAX,tRAS(max) - Specifies the maximum time between activate and precharge to same bank. This is the maximum time that a page can be kept open Minimum value of this register is 1. Zero is invalid. When the controller is operating in 1:1 frequency.." newline hexmask.long.byte 0x0 0.--5. 1. "T_RAS_MIN,tRAS(min) - Specifies the minimum time between activate and precharge to the same bank. When the controller is operating in 1:2 frequency mode 1T mode program this to tRAS(min)/2. No rounding up. When the controller is operating in 1:2.." line.long 0x4 "DRAMTMG1,[FREQ3] SDRAM Timing Register 1" hexmask.long.byte 0x4 16.--20. 1. "T_XP,tXP - Specifies the minimum time after power-down exit to any operation. For DDR3 this must be programmed to tXPDLL if slow powerdown exit is selected in MR0[12]. If C/A parity for DDR4 is used set to (tXP+PL) instead. If LPDDR4 is selected and.." newline hexmask.long.byte 0x4 8.--13. 1. "RD2PRE,tRTP - Specifies the minimum time from read to precharge of same bank. - DDR2 - tAL + BL/2 + max(tRTP 2) - 2 - DDR3 - tAL + max (tRTP 4) - DDR4 - Max of following two equations: tAL + max (tRTP 4) or RL + BL/2 - tRP (*). - mDDR - BL/2 - LPDDR2.." newline hexmask.long.byte 0x4 0.--6. 1. "T_RC,tRC - Specifies the minimum time between activates to same bank. When the controller is operating in 1:2 frequency ratio mode program this to (tRC/2) and round up to next integer value. Unit: DFI clock cycles. Programming Mode: Quasi-dynamic Group.." line.long 0x8 "DRAMTMG2,[FREQ3] SDRAM Timing Register 2" hexmask.long.byte 0x8 24.--29. 1. "WRITE_LATENCY,Set this field to WL. Indicates the Time from write command to write data on SDRAM interface. This must be set to WL. For mDDR it must be set to 1. Note that depending on the PHY if using RDIMM/LRDIMM it might be necessary to adjust the.." newline hexmask.long.byte 0x8 16.--21. 1. "READ_LATENCY,Set this field to RL. Indicates the time from read command to read data on SDRAM interface. This must be set to RL. Note that depending on the PHY if using RDIMM/LRDIMM it might be necessary to adjust the value of RL to compensate for the.." newline hexmask.long.byte 0x8 8.--13. 1. "RD2WR,DDR2/3/mDDR: RL + BL/2 + 2 - WL DDR4: RL + BL/2 + 1 + WR_PREAMBLE - WL LPDDR2/LPDDR3: RL + BL/2 + RU(tDQSCKmax/tCK) + 1 - WL LPDDR4(DQ ODT is Disabled): RL + BL/2 + RU(tDQSCKmax/tCK) + WR_PREAMBLE + RD_POSTAMBLE - WL LPDDR4(DQ ODT is Enabled): RL +.." newline hexmask.long.byte 0x8 0.--5. 1. "WR2RD,DDR4: CWL + PL + BL/2 + tWTR_L LPDDR2/3/4: WL + BL/2 + tWTR + 1 Others: CWL + BL/2 + tWTR In DDR4 minimum time from write command to read command for same bank group. In others minimum time from write command to read command. Includes time for.." line.long 0xC "DRAMTMG3,[FREQ3] SDRAM Timing Register 3" hexmask.long.word 0xC 20.--29. 1. "T_MRW,Indicates the time to wait after a mode register write or read (MRW or MRR). Present only in designs configured to support LPDDR2 LPDDR3 or LPDDR4. LPDDR2 typically requires value of 5. LPDDR3 typically requires value of 10. LPDDR4: Set this to.." newline hexmask.long.byte 0xC 12.--17. 1. "T_MRD,tMRD- Indicates the number of cycles to wait after a mode register write or read. Depending on the connected SDRAM tMRD represents: - DDR2/mDDR: Time from MRS to any command - DDR3/4: Time from MRS to MRS command - LPDDR2: not used - LPDDR3/4:.." newline hexmask.long.word 0xC 0.--9. 1. "T_MOD,tMOD - Parameter used only in DDR3 and DDR4. Indicates the number of cycles between load mode command and following non-load mode command. If C/A parity for DDR4 is used set to tMOD_PAR(tMOD+PL) instead. If CAL mode is enabled.." line.long 0x10 "DRAMTMG4,[FREQ3] SDRAM Timing Register 4" hexmask.long.byte 0x10 24.--28. 1. "T_RCD,tRCD - tAL: Indicates the minimum time from activate to read or write command to same bank. When the controller is operating in 1:2 frequency ratio mode program this to ((tRCD - tAL)/2) and round it up to the next integer value. Minimum value.." newline hexmask.long.byte 0x10 16.--19. 1. "T_CCD,DDR4: tCCD_L: This is the minimum time between two reads or two writes for same bank group. Others: tCCD: This is the minimum time between two reads or two writes. When the controller is operating in 1:2 frequency ratio mode program this to.." newline hexmask.long.byte 0x10 8.--11. 1. "T_RRD,DDR4: tRRD_L: This is the minimum time between activates from bank 'a' to bank 'b' for same bank group. Others: tRRD: Minimum time between activates from bank 'a' to bank 'b' When the controller is operating in 1:2 frequency ratio mode program.." newline hexmask.long.byte 0x10 0.--4. 1. "T_RP,tRP: Indicates the minimum time from single-bank precharge to activate of same bank. When the controller is operating in 1:1 frequency ratio mode t_rp must be set to RoundUp(tRP/tCK). When the controller is operating in 1:2 frequency ratio mode.." line.long 0x14 "DRAMTMG5,[FREQ3] SDRAM Timing Register 5" hexmask.long.byte 0x14 24.--27. 1. "T_CKSRX,This is the time before self-refresh Exit that CK is maintained as a valid clock before issuing SRX. Specifies the clock stable time before SRX. Recommended settings: - mDDR - 1 - LPDDR2 - 2 - LPDDR3 - 2 - LPDDR4 - tCKCKEH - DDR2 - 1 - DDR3 -.." newline hexmask.long.byte 0x14 16.--19. 1. "T_CKSRE,This is the time after self-refresh Down Entry that CK is maintained as a valid clock. Specifies the clock disable delay after SRE. Recommended settings: - mDDR - 0 - LPDDR2 - 2 - LPDDR3 - 2 - LPDDR4 - tCKELCK - DDR2 - 1 - DDR3 - Max (10 ns 5.." newline hexmask.long.byte 0x14 8.--13. 1. "T_CKESR,Indicates the minimum CKE low width for self-refresh or self-refresh power down entry to exit timing in memory clock cycles. Recommended settings: - mDDR - tRFC - LPDDR2 - tCKESR - LPDDR3 - tCKESR - LPDDR4 - max(tCKE tSR) - DDR2 - tCKE - DDR3 -.." newline hexmask.long.byte 0x14 0.--4. 1. "T_CKE,Indicates the minimum number of cycles of CKE HIGH/LOW during power-down and self-refresh. - LPDDR2/LPDDR3 mode - Set this to the larger of tCKE or tCKESR - LPDDR4 mode - Set this to the larger of tCKE or tSR - Non-LPDDR2/non-LPDDR3/non-LPDDR4.." line.long 0x18 "DRAMTMG6,[FREQ3] SDRAM Timing Register 6" hexmask.long.byte 0x18 24.--27. 1. "T_CKDPDE,This is the time after Deep Power Down Entry that CK is maintained as a valid clock. Specifies the clock disable delay after DPDE. Recommended settings: - mDDR: 0 - LPDDR2: 2 - LPDDR3: 2 When the controller is operating in 1:2 frequency ratio.." newline hexmask.long.byte 0x18 16.--19. 1. "T_CKDPDX,This is the time before Deep Power Down Exit that CK is maintained as a valid clock before issuing DPDX. Specifies the clock stable time before DPDX. Recommended settings: - mDDR - 1 - LPDDR2 - 2 - LPDDR3 - 2 When the controller is operating in.." newline hexmask.long.byte 0x18 0.--3. 1. "T_CKCSX,This is the time before Clock Stop Exit that CK is maintained as a valid clock before issuing Clock Stop Exit. Specifies the clock stable time before next command after Clock Stop Exit. Recommended settings: - mDDR - 1 - LPDDR2 - tXP + 2 - LPDDR3.." line.long 0x1C "DRAMTMG7,[FREQ3] SDRAM Timing Register 7" hexmask.long.byte 0x1C 8.--11. 1. "T_CKPDE,This is the time after Power Down Entry that CK is maintained as a valid clock. Specifies the clock disable delay after PDE. Recommended settings: - mDDR - 0 - LPDDR2 - 2 - LPDDR3 - 2 - LPDDR4 - tCKELCK When using DDR2/3/4 SDRAM this register.." newline hexmask.long.byte 0x1C 0.--3. 1. "T_CKPDX,This is the time before Power Down Exit that CK is maintained as a valid clock before issuing PDX. Specifies the clock stable time before PDX. Recommended settings: - mDDR - 0 - LPDDR2 - 2 - LPDDR3 - 2 - LPDDR4 - tCKCKEH When using DDR2/3/4 SDRAM.." line.long 0x20 "DRAMTMG8,[FREQ3] SDRAM Timing Register 8" hexmask.long.byte 0x20 24.--30. 1. "T_XS_FAST_X32,tXS_FAST: Exit self-refresh to ZQCL ZQCS and MRS (only CL WR RTP and Geardown mode). When the controller is operating in 1:2 frequency ratio mode program this to the previous value divided by 2 and round up to next integer value. Note:.." newline hexmask.long.byte 0x20 16.--22. 1. "T_XS_ABORT_X32,tXS_ABORT: Exit self-refresh to commands not requiring a locked DLL in self-refresh Abort. When the controller is operating in 1:2 frequency ratio mode program this to the previous value divided by 2 and round up to next integer value." newline hexmask.long.byte 0x20 8.--14. 1. "T_XS_DLL_X32,tXSDLL: Exit self-refresh to commands requiring a locked DLL. When the controller is operating in 1:2 frequency ratio mode program this to the previous value divided by 2 and round up to next integer value. Note: Used only for DDR2 DDR3.." newline hexmask.long.byte 0x20 0.--6. 1. "T_XS_X32,tXS: Exit self-refresh to commands not requiring a locked DLL. When the controller is operating in 1:2 frequency ratio mode program this to the previous value divided by 2 and round up to next integer value. Note: Used only for DDR2 DDR3 and.." line.long 0x24 "DRAMTMG9,[FREQ3] SDRAM Timing Register 9" bitfld.long 0x24 30. "DDR4_WR_PREAMBLE,DDR4 Write preamble mode. - 0 - 1tCK preamble - 1 - 2tCK preamble Present only with MEMC_FREQ_RATIO=2. Programming Mode: Quasi-dynamic Group 2 Group 4" "0,1" newline bitfld.long 0x24 16.--18. "T_CCD_S,tCCD_S: This is the minimum time between two reads or two writes for different bank group. For bank switching (from bank 'a' to bank 'b') the minimum time is this value + 1. When the controller is operating in 1:2 frequency ratio mode program.." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x24 8.--11. 1. "T_RRD_S,tRRD_S: This is the minimum time between activates from bank 'a' to bank 'b' for different bank group. When the controller is operating in 1:2 frequency ratio mode program this to (tRRD_S/2) and round it up to the next integer value. Present.." newline hexmask.long.byte 0x24 0.--5. 1. "WR2RD_S,CWL + PL + BL/2 + tWTR_S Minimum time from write command to read command for different bank group. Includes time for bus turnaround recovery times and all per-bank per-rank and global constraints. Present only in designs configured to support.." line.long 0x28 "DRAMTMG10,[FREQ3] SDRAM Timing Register 10" hexmask.long.byte 0x28 16.--20. 1. "T_SYNC_GEAR,Indicates the time between MRS command and the sync pulse time. This must be even number of clocks. For DDR4-2666 and DDR4-3200 this parameter is defined as tMOD(min)+4nCK tMOD(min) is greater of 24nCK or 15ns 15ns / .625ns = 24 Max value.." newline hexmask.long.byte 0x28 8.--12. 1. "T_CMD_GEAR,Indicates a sync pulse to first valid command. For DDR4-2666 and DDR4-3200 this parameter is defined as tMOD(min) tMOD(min) is greater of 24nCK or 15ns 15ns / .625ns = 24 Max value for this register is 24 When the controller is operating in.." newline bitfld.long 0x28 2.--3. "T_GEAR_SETUP,Indicates the geardown setup time. Minimum value of this register is 1. Zero is invalid. For DDR4-2666 and DDR4-3200 this parameter is defined as 2 clks When the controller is operating in 1:2 frequency ratio mode program this to.." "0,1,2,3" newline bitfld.long 0x28 0.--1. "T_GEAR_HOLD,Indicates the geardown hold time. Minimum value of this register is 1. Zero is invalid. For DDR4-2666 and DDR4-3200 this parameter is defined as 2 clks When the controller is operating in 1:2 frequency ratio mode program this to.." "0,1,2,3" line.long 0x2C "DRAMTMG11,[FREQ3] SDRAM Timing Register 11" hexmask.long.byte 0x2C 24.--30. 1. "POST_MPSM_GAP_X32,tXMPDLL: This is the minimum Exit MPSM to commands requiring a locked DLL. When the controller is operating in 1:2 frequency ratio mode program this to (tXMPDLL/2) and round it up to the next integer value. Present only in designs.." newline hexmask.long.byte 0x2C 16.--20. 1. "T_MPX_LH,tMPX_LH: This is the minimum CS_n Low hold time to CKE rising edge. When the controller is operating in 1:2 frequency ratio mode program this to RoundUp(tMPX_LH/2)+1. Present only in designs configured to support DDR4. Unit: DFI clock cycles." newline bitfld.long 0x2C 8.--9. "T_MPX_S,tMPX_S: This is the minimum time CS setup time to CKE. When the controller is operating in 1:2 frequency ratio mode program this to (tMPX_S/2) and round it up to the next integer value. Present only in designs configured to support DDR4. Unit:.." "0,1,2,3" newline hexmask.long.byte 0x2C 0.--4. 1. "T_CKMPE,tCKMPE: This is the minimum valid clock requirement after MPSM entry. Present only in designs configured to support DDR4. When the controller is operating in 1:2 frequency ratio mode divide the value calculated using the previous equation by 2.." line.long 0x30 "DRAMTMG12,[FREQ3] SDRAM Timing Register 12" hexmask.long.byte 0x30 24.--29. 1. "T_WR_MPR,This bit is used only in DDR4. Cycles between MPR Write and other command. Set this to tMOD + AL (or tMOD + PL + AL if C/A parity is also used). When the controller is operating in 1:2 frequency ratio mode program this to (tWR_MPR/2) and round.." newline bitfld.long 0x30 16.--17. "T_CMDCKE,tCMDCKE: Indicates the delay from valid command to CKE input LOW. Set this to the larger of tESCKE or tCMDCKE When the controller is operating in 1:2 frequency ratio mode program this to (max(tESCKE tCMDCKE)/2) and round it up to the next.." "0,1,2,3" newline hexmask.long.byte 0x30 0.--4. 1. "T_MRD_PDA,tMRD_PDA: This is the Mode Register Set command cycle time in PDA mode. When the controller is operating in 1:2 frequency ratio mode program this to (tMRD_PDA/2) and round it up to the next integer value. Unit: DFI clock cycles. Programming.." line.long 0x34 "DRAMTMG13,[FREQ3] SDRAM Timing Register 13" hexmask.long.byte 0x34 24.--30. 1. "ODTLOFF,LPDDR4: ODTLoff: This is the latency from CAS-2 command to ODToff reference. When the controller is operating in 1:2 frequency ratio mode program this to (ODTLoff/2) and round it up to the next integer value. Unit: DFI clock cycles. Programming.." newline hexmask.long.byte 0x34 16.--21. 1. "T_CCD_MW,LPDDR4: tCCDMW: This is the minimum time from write or masked write to masked write command for same bank. When the controller is operating in 1:2 frequency ratio mode program this to (tCCDMW/2) and round it up to the next integer value. Unit:.." newline bitfld.long 0x34 0.--2. "T_PPD,LPDDR4: tPPD: This is the minimum time from precharge to precharge command. When the controller is operating in 1:2 frequency ratio mode program this to (tPPD/2) and round it up to the next integer value. Unit: DFI clock cycles. Programming Mode:.." "?,?,?,?,tPPD: This is the minimum time from precharge to..,?,?,?" line.long 0x38 "DRAMTMG14,[FREQ3] SDRAM Timing Register 14" hexmask.long.word 0x38 0.--11. 1. "T_XSR,tXSR: This is the exit self-refresh to any command. When the controller is operating in 1:2 frequency ratio mode program this to the previous value divided by 2 and round up to next integer value. The value 0xfff is illegal for this register.." line.long 0x3C "DRAMTMG15,[FREQ3] SDRAM Timing Register 15" bitfld.long 0x3C 31. "EN_DFI_LP_T_STAB,- 1 - Enable using tSTAB when exiting DFI LP. This must be set when the PHY is stopping the clock during DFI LP to save maximum power. - 0 - Disable using tSTAB when exiting DFI LP. Programming Mode: Quasi-dynamic Group 2 Group 4" "Disable using tSTAB when exiting DFI LP,Enable using tSTAB when exiting DFI LP" newline hexmask.long.byte 0x3C 0.--7. 1. "T_STAB_X32,tSTAB: Stabilization time. It is required in the following two cases for DDR3/DDR4 RDIMM: - When exiting power saving mode if the clock is stopped after re-enabling it the clock must be stable for a time specified by tSTAB - In the case of.." group.long 0x180++0x3 line.long 0x0 "ZQCTL0,[FREQ3] ZQ Control Register 0" bitfld.long 0x0 31. "DIS_AUTO_ZQ,- 1 - Disable uMCTL2 generation of ZQCS/MPC(ZQ calibration) command. Register DBGCMD.zq_calib_short can be used instead to issue ZQ calibration request from APB module - 0 - Internally generate ZQCS/MPC(ZQ calibration) commands based on.." "Internally generate ZQCS/MPC,Disable uMCTL2 generation of ZQCS/MPC" newline bitfld.long 0x0 30. "DIS_SRX_ZQCL,- 1 - Disable issuing of ZQCL/MPC(ZQ calibration) command at self-refresh/SR-Powerdown exit. Only applicable when run in DDR3 or DDR4 or LPDDR2 or LPDDR3 or LPDDR4 mode - 0 - Enable issuing of ZQCL/MPC(ZQ calibration) command at.." "Enable issuing of ZQCL/MPC,Disable issuing of ZQCL/MPC" newline bitfld.long 0x0 29. "ZQ_RESISTOR_SHARED,- 1 - Denotes that ZQ resistor is shared between ranks. Means ZQinit/ZQCL/ZQCS/MPC(ZQ calibration) commands are sent to one rank at a time with tZQinit/tZQCL/tZQCS/tZQCAL/tZQLAT timing met between commands so that commands to different.." "ZQ resistor is not shared,Denotes that ZQ resistor is shared between ranks" newline bitfld.long 0x0 28. "DIS_MPSMX_ZQCL,- 1 - Disable issuing of ZQCL command at Maximum Power Saving Mode exit. Only applicable when run in DDR4 mode - 0 - Enable issuing of ZQCL command at Maximum Power Saving Mode exit. Only applicable when run in DDR4 mode This is only.." "Enable issuing of ZQCL command at Maximum Power..,Disable issuing of ZQCL command at Maximum Power.." newline hexmask.long.word 0x0 16.--26. 1. "T_ZQ_LONG_NOP,tZQoper for DDR3/DDR4 tZQCL for LPDDR2/LPDDR3 tZQCAL for LPDDR4: Number of DFI clock cycles of NOP required after a ZQCL (ZQ calibration long)/MPC(ZQ Start) command is issued to SDRAM. When the controller is operating in 1:2 frequency.." newline hexmask.long.word 0x0 0.--9. 1. "T_ZQ_SHORT_NOP,tZQCS for DDR3/DD4/LPDDR2/LPDDR3 tZQLAT for LPDDR4: Number of DFI clock cycles of NOP required after a ZQCS (ZQ calibration short)/MPC(ZQ Latch) command is issued to SDRAM. When the controller is operating in 1:2 frequency ratio mode.." group.long 0x190++0x7 line.long 0x0 "DFITMG0,[FREQ3] DFI Timing Register 0" hexmask.long.byte 0x0 24.--28. 1. "DFI_T_CTRL_DELAY,Specifies the number of DFI clock cycles after an assertion or de-assertion of the DFI control signals that the control signals at the PHY-DRAM interface reflect the assertion or de-assertion. If the DFI clock and the memory clock are.." newline bitfld.long 0x0 23. "DFI_RDDATA_USE_DFI_PHY_CLK,Defines whether dfi_rddata_en/dfi_rddata/dfi_rddata_valid is generated using HDR (DFI clock) or SDR (DFI PHY clock) values. Selects whether value in DFITMG0.dfi_t_rddata_en is in terms of HDR (DFI clock) or SDR (DFI PHY clock).." "Else,?" newline hexmask.long.byte 0x0 16.--22. 1. "DFI_T_RDDATA_EN,Time from the assertion of a read command on the DFI interface to the assertion of the dfi_rddata_en signal. Refer to PHY specification for correct value. This corresponds to the DFI parameter trddata_en. Note that depending on the PHY.." newline bitfld.long 0x0 15. "DFI_WRDATA_USE_DFI_PHY_CLK,Defines whether dfi_wrdata_en/dfi_wrdata/dfi_wrdata_mask is generated using HDR (DFI clock) or SDR (DFI PHY clock) values. Selects whether value in DFITMG0.dfi_tphy_wrlat is in terms of HDR (DFI clock) or SDR (DFI PHY clock).." "Else,?" newline hexmask.long.byte 0x0 8.--13. 1. "DFI_TPHY_WRDATA,Specifies the number of clock cycles between when dfi_wrdata_en is asserted to when the associated write data is driven on the dfi_wrdata signal. This corresponds to the DFI timing parameter tphy_wrdata. For more information on correct.." newline hexmask.long.byte 0x0 0.--5. 1. "DFI_TPHY_WRLAT,Write latency. Number of clocks from the write command to write data enable (dfi_wrdata_en). This corresponds to the DFI timing parameter tphy_wrlat. Refer to PHY specification for correct value.Note that depending on the PHY if using.." line.long 0x4 "DFITMG1,[FREQ3] DFI Timing Register 1" hexmask.long.byte 0x4 28.--31. 1. "DFI_T_CMD_LAT,Specifies the number of DFI PHY clock cycles between when the dfi_cs signal is asserted and when the associated command is driven. This field is used for CAL mode must be set to '0' or tCAL which matches the CAL mode register setting in.." newline bitfld.long 0x4 24.--25. "DFI_T_PARIN_LAT,Specifies the number of DFI PHY clock cycles between when the dfi_cs signal is asserted and when the associated dfi_parity_in signal is driven. Unit: DFI PHY clock cycles. Programming Mode: Quasi-dynamic Group 4" "0,1,2,3" newline hexmask.long.byte 0x4 16.--20. 1. "DFI_T_WRDATA_DELAY,Specifies the number of DFI clock cycles between when the dfi_wrdata_en signal is asserted and when the corresponding write data transfer is completed on the DRAM bus. This corresponds to the DFI timing parameter twrdata_delay. For.." newline hexmask.long.byte 0x4 8.--12. 1. "DFI_T_DRAM_CLK_DISABLE,Specifies the number of DFI clock cycles from the assertion of the dfi_dram_clk_disable signal on the DFI until the clock to the DRAM memory devices at the PHY-DRAM boundary maintains a low value. If the DFI clock and the memory.." newline hexmask.long.byte 0x4 0.--4. 1. "DFI_T_DRAM_CLK_ENABLE,Specifies the number of DFI clock cycles from the de-assertion of the dfi_dram_clk_disable signal on the DFI until the first valid rising edge of the clock to the DRAM memory devices at the PHY-DRAM boundary. If the DFI clock and.." group.long 0x1B4++0x7 line.long 0x0 "DFITMG2,[FREQ3] DFI Timing Register 2" hexmask.long.byte 0x0 8.--14. 1. "DFI_TPHY_RDCSLAT,specifies the number of DFI PHY clock cycles between when a read command is sent on the DFI control interface and when the associated dfi_rddata_cs signal is asserted. This corresponds to the DFI timing parameter tphy_rdcslat. Refer to.." newline hexmask.long.byte 0x0 0.--5. 1. "DFI_TPHY_WRCSLAT,Specifies the number of DFI PHY clock cycles between when a write command is sent on the DFI control interface and when the associated dfi_wrdata_cs signal is asserted. This corresponds to the DFI timing parameter tphy_wrcslat. For more.." line.long 0x4 "DFITMG3,[FREQ3] DFI Timing Register 3" hexmask.long.byte 0x4 0.--4. 1. "DFI_T_GEARDOWN_DELAY,The delay from dfi_geardown_en assertion to the time of the PHY being ready to receive commands. Refer to PHY specification for correct value. When the controller is operating in 1:2 frequency ratio mode program this to.." group.long 0x240++0x3 line.long 0x0 "ODTCFG,[FREQ3] ODT Configuration Register" hexmask.long.byte 0x0 24.--27. 1. "WR_ODT_HOLD,DFI PHY clock cycles to hold ODT for a write command. The minimum supported value is 2. Recommended values: DDR2: - BL8 - 0x5 (DDR2-400/533/667) 0x6 (DDR2-800) 0x7 (DDR2-1066) - BL4 - 0x3 (DDR2-400/533/667) 0x4 (DDR2-800) 0x5 (DDR2-1066).." newline hexmask.long.byte 0x0 16.--20. 1. "WR_ODT_DELAY,Indicates the delay in DFI PHY clock cycles from issuing a write command to setting ODT values associated with that command. ODT setting must remain constant for the entire time that DQS is driven by the uMCTL2. Recommended values: DDR2: -.." newline hexmask.long.byte 0x0 8.--11. 1. "RD_ODT_HOLD,DFI PHY clock cycles to hold ODT for a read command. The minimum supported value is 2. Recommended values: DDR2: - BL8 - 0x6 (not DDR2-1066) 0x7 (DDR2-1066) - BL4 - 0x4 (not DDR2-1066) 0x5 (DDR2-1066) DDR3: - BL8 - 0x6 DDR4: - BL8 - 5 +.." newline hexmask.long.byte 0x0 2.--6. 1. "RD_ODT_DELAY,Indicates the delay in DFI PHY clock cycles from issuing a read command to setting ODT values associated with that command. ODT setting must remain constant for the entire time that DQS is driven by the uMCTL2. Recommended values: DDR2: -.." tree.end elif (CORENAME()=="CORTEXA55") base ad:0x30D50000 group.long 0x0++0x23 line.long 0x0 "MIPI_DSI1_MUX,mipi dsi1 mux selection" bitfld.long 0x0 0.--2. "DISP_MUX,mipi_dsi1_mux selection 000: DC1 001: DC2 010: DC3 011: DC4 100: DC5 others: not support" "DC1,DC2,?,?,?,?,?,?" line.long 0x4 "MIPI_DSI2_MUX,mipi dsi2 mux selection" bitfld.long 0x4 0.--2. "DISP_MUX,mipi_dsi2_mux selection 000: DC1 001: DC2 010: DC3 011: DC4 100: DC5 others: not support" "DC1,DC2,?,?,?,?,?,?" line.long 0x8 "PARALLEL_MUX,parallel mux selection" bitfld.long 0x8 0.--2. "DISP_MUX,parallel_mux selection 000: DC1 001: DC2 010: DC3 011: DC4 100: DC5 others: not support" "DC1,DC2,?,?,?,?,?,?" line.long 0xC "DC1_PIX_CLOCK_MUX,DC1 clock selection" bitfld.long 0xC 0.--1. "CLK_MUX,dc1_dsp_clock_mux 00: pll1 01: pll2 10: pll3 11: pll4" "pll1,pll2,?,?" line.long 0x10 "DC2_PIX_CLOCK_MUX,DC2 clock selection" bitfld.long 0x10 0.--1. "CLK_MUX,dc2_dsp_clock_mux 00: pll1 01: pll2 10: pll3 11: pll4" "pll1,pll2,?,?" line.long 0x14 "DC3_PIX_CLOCK_MUX,DC3 clock selection" bitfld.long 0x14 0.--1. "CLK_MUX,dc3_dsp_clock_mux 00: pll1 01: pll2 10: pll3 11: pll4" "pll1,pll2,?,?" line.long 0x18 "DC4_PIX_CLOCK_MUX,DC4 clock selection" bitfld.long 0x18 0.--1. "CLK_MUX,dc4_dsp_clock_mux 00: pll1 01: pll2 10: pll3 11: pll4" "pll1,pll2,?,?" line.long 0x1C "DC5_PIX_CLOCK_MUX,DC5 clock selection" bitfld.long 0x1C 0.--2. "CLK_MUX,dc5_dsp_clock_mux 00: pll1 01: pll2 10: pll3 11: pll4" "pll1,pll2,?,?,?,?,?,?" line.long 0x20 "CRC32_MUX_1,CRC32 MUX" bitfld.long 0x20 5. "CLK_POL,crc32 feedback clock polarity" "0,1" bitfld.long 0x20 4. "DC5,dc5 crc32 mux 1: from parallel 0: from dc5" "from dc5,from parallel" newline bitfld.long 0x20 3. "DC4,dc1 crc32 mux 1: from parallel 0: from dc3" "from dc3,from parallel" bitfld.long 0x20 2. "DC3,dc1 crc32 mux 1: from parallel 0: from dc2" "from dc2,from parallel" bitfld.long 0x20 1. "DC2,dc1 crc32 mux 1: from parallel 0: from dc4" "from dc4,from parallel" newline bitfld.long 0x20 0. "DC1,dc1 crc32 mux 1: from parallel 0: from dc1" "from dc1,from parallel" group.long 0x30++0x13 line.long 0x0 "MIPI_DSI1_CTRL1,MIPI DSI1 control" hexmask.long.byte 0x0 14.--19. 1. "CSI_DT,changed CSI data_type" hexmask.long.byte 0x0 8.--13. 1. "DSI_DT,DSI target data_type" newline bitfld.long 0x0 7. "IGORE_HSYNC,0: disable that igore the hsync short command 1: enable that igore the hsync short command" "disable that igore the hsync short command,enable that igore the hsync short command" bitfld.long 0x0 6. "DSI2CSI_EN,dsi change to csi 0:disable 1:enable" "disable,enable" bitfld.long 0x0 5. "DPI_EDPIHALT,record the MIPI dsi1 edpihalt" "0,1" newline bitfld.long 0x0 4. "DPI_UPDATECFG,control the MIPI dsi1 updatecfg" "0,1" bitfld.long 0x0 3. "DPI_COLORM,control the MIPI dsi1 colorm" "0,1" bitfld.long 0x0 2. "DPI_SHUTDN,control the MIPI dsi1 shutdn" "0,1" newline bitfld.long 0x0 0.--1. "PIXEL_MAP,pixel_map: 00: RGB101010 01: RBG565 10: RGB666 11: RGB888" "RGB101010,RBG565,?,?" line.long 0x4 "MIPI_DSI1_CTRL2,MIPI DSI1 control" hexmask.long.word 0x4 13.--28. 1. "LINE_NUM,the line number when add the fake frame end" bitfld.long 0x4 12. "FVSE,fake frame end" "0,1" newline rbitfld.long 0x4 11. "LOCK,pll_lcok" "0,1" bitfld.long 0x4 9.--10. "CLKSEL,Control of PLL clock output selection. 00 - Clocks stopped 01 - Clock generation 10 - Buffered clkext 11 - Forbidden" "Clocks stopped,Clock generation,?,?" bitfld.long 0x4 8. "FORCE_LOCK,force lock 0: according to lock detector-default 1: lock indication forced" "according to lock detector-default,lock indication forced" newline bitfld.long 0x4 7. "GP_CLK_EN,clkout gate enable default 1'b1" "0,1" hexmask.long.byte 0x4 0.--6. 1. "HSFREQRANGE,High-speed Frequency Range Selection" line.long 0x8 "MIPI_DSI2_CTRL1,MIPI DSI2 control" hexmask.long.byte 0x8 14.--19. 1. "CSI_DT,changed CSI data_type" hexmask.long.byte 0x8 8.--13. 1. "DSI_DT,DSI target data_type" newline bitfld.long 0x8 7. "IGORE_HSYNC,0: disable that igore the hsync short command 1: enable that igore the hsync short command" "disable that igore the hsync short command,enable that igore the hsync short command" bitfld.long 0x8 6. "DSI2CSI_EN,dsi change to csi 0:disable 1:enable" "disable,enable" bitfld.long 0x8 5. "DPI_EDPIHALT,record the MIPI dsi1 edpihalt" "0,1" newline bitfld.long 0x8 4. "DPI_UPDATECFG,control the MIPI dsi1 updatecfg" "0,1" bitfld.long 0x8 3. "DPI_COLORM,control the MIPI dsi1 colorm" "0,1" bitfld.long 0x8 2. "DPI_SHUTDN,control the MIPI dsi1 shutdn" "0,1" newline bitfld.long 0x8 0.--1. "PIXEL_MAP,pixel_map: 00: RGB101010 01: RBG565 10: RGB666 11: RGB888" "RGB101010,RBG565,?,?" line.long 0xC "MIPI_DSI2_CTRL2,MIPI DSI2 control" hexmask.long.word 0xC 13.--28. 1. "LINE_NUM,the line number when add the fake frame end" bitfld.long 0xC 12. "FVSE,fake frame end" "0,1" newline rbitfld.long 0xC 11. "LOCK,pll_lcok" "0,1" bitfld.long 0xC 9.--10. "CLKSEL,Control of PLL clock output selection. 00 - Clocks stopped 01 - Clock generation 10 - Buffered clkext 11 - Forbidden" "Clocks stopped,Clock generation,?,?" bitfld.long 0xC 8. "FORCE_LOCK,force lock 0: according to lock detector-default 1: lock indication forced" "according to lock detector-default,lock indication forced" newline bitfld.long 0xC 7. "GP_CLK_EN,clkout gate enable default 1'b1" "0,1" hexmask.long.byte 0xC 0.--6. 1. "HSFREQRANGE,High-speed Frequency Range Selection" line.long 0x10 "DP_FWD,DP data forward" bitfld.long 0x10 2. "DP3,DP3 data forward 0: dc3 channel 1: dc4 channel" "dc3 channel,dc4 channel" bitfld.long 0x10 1. "DP2,DP2 data forward 0: dc2 channel 1: dc1 channel" "dc2 channel,dc1 channel" newline bitfld.long 0x10 0. "DP1,DP1 data forward 0: dc2 channel 1: dc1 channel" "dc2 channel,dc1 channel" group.long 0x50++0x13 line.long 0x0 "CSI1_CH2_MUX,CSI1 channel2 mux selection" bitfld.long 0x0 0.--2. "DISP_MUX,CSI1 channel2 mux selection 000: DC1 001: DC2 010: DC3 011: DC4 100: DC5 others: not support" "DC1,DC2,?,?,?,?,?,?" line.long 0x4 "CSI2_CH2_MUX,CSI2 channel2 mux selection" bitfld.long 0x4 0.--2. "DISP_MUX,CSI2 channel2 mux selection 000: DC1 001: DC2 010: DC3 011: DC4 100: DC5 others: not support" "DC1,DC2,?,?,?,?,?,?" line.long 0x8 "CSI3_CH1_MUX,CSI3 channel1 mux selection" bitfld.long 0x8 0.--2. "DISP_MUX,CSI3 channel1 mux selection 000: DC1 001: DC2 010: DC3 011: DC4 100: DC5 others: not support" "DC1,DC2,?,?,?,?,?,?" line.long 0xC "CSI3_CH2_MUX,CSI3 channel2 mux selection" bitfld.long 0xC 0.--2. "DISP_MUX,CSI3 channel2 mux selection 000: DC1 001: DC2 010: DC3 011: DC4 100: DC5 others: not support" "DC1,DC2,?,?,?,?,?,?" line.long 0x10 "MIPI_CSI1_CTRL,MIPI CSI1 control" hexmask.long.byte 0x10 0.--6. 1. "HSFREQRANGE,High-speed Frequency Range Selection default:1GHz" group.long 0x68++0x3 line.long 0x0 "MIPI_CSI2_CTRL,MIPI CSI2 control" hexmask.long.byte 0x0 0.--6. 1. "HSFREQRANGE,High-speed Frequency Range Selection default:1GHz" group.long 0x70++0x3 line.long 0x0 "MIPI_CSI3_CTRL,MIPI CSI3 control" hexmask.long.byte 0x0 0.--6. 1. "HSFREQRANGE,High-speed Frequency Range Selection default:1GHz" repeat 4. (list 0x1 0x2 0x3 0x4 )(list 0x0 0x4 0x8 0xC ) group.long ($2+0x80)++0x3 line.long 0x0 "SPARE_$1,spare 1" hexmask.long 0x0 0.--31. 1. "SPARE,spare" repeat.end repeat 10. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 )(list 0x0 0x4 0x8 0xC 0x10 0x14 0x18 0x1C 0x20 0x24 ) group.long ($2+0x100)++0x3 line.long 0x0 "SPIN_LOCK_$1,SPIN LOCK" bitfld.long 0x0 0. "LOCK,read : set write: clear" "0,1" repeat.end rgroup.long 0x200++0x3 line.long 0x0 "NOC_STATUS,noc no pending status" hexmask.long 0x0 0.--31. 1. "NOC_STATUS,noc_status 0: pending 1: no pending noc_status[0] csi1 noc_status[1] csi2 noc_status[2] csi3 noc_status[3] g2d noc_status[4] g2d_lite noc_status[5] dp1 noc_status[6] dc1 noc_status[7] dp2 noc_status[8] dc2 noc_status[9] dp3 noc_status[10] dc3.." endif tree.end tree "DMAC (DMA Controller)" sif (CORENAME()=="CORTEXR5F") repeat 8. (increment 1. 1.) (list ad:0xF5500000 ad:0xF5510000 ad:0xF5520000 ad:0xF5530000 ad:0xF5540000 ad:0xF5550000 ad:0xF5560000 ad:0xF5570000) tree "DMA$1" base $2 tree "Common" repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) rgroup.long ($2)++0x3 line.long 0x0 "DMAC_IDREG_$1,DMAC ID Register contains a 64-bit value that is hardwired and read back by a read to the DW_axi_dmac ID Register." hexmask.long 0x0 0.--31. 1. "DMAC_ID,DMAC ID Number." repeat.end repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) rgroup.long ($2+0x8)++0x3 line.long 0x0 "DMAC_COMPVERREG_$1,This register contains a 64-bit value that is hardwired and read back by a read to the DW_axi_dmac Component Version Register." hexmask.long 0x0 0.--31. 1. "DMAC_COMPVER,DMAC Component Version Number." repeat.end group.long 0x10++0x3 line.long 0x0 "DMAC_CFGREG_0,This register is used to enable the DW_axi_dmac. which must be done before any channel activity can begin. This register also contains global interrupt enable bit." hexmask.long 0x0 2.--31. 1. "RSVD_DMAC_CFGREG,DMAC_CFGREG Reserved bits - Read Only" newline bitfld.long 0x0 1. "INT_EN,This bit is used to globally enable the interrupt generation. - 0: DW_axi_dmac Interrupts are disabled - 1: DW_axi_dmac Interrupt logic is enabled. 0x0: DW_axi_dmac Interrupts are disabled 0x1: DW_axi_dmac Interrupts are enabled" "DW_axi_dmac Interrupts are disabled,DW_axi_dmac Interrupts are enabled" newline bitfld.long 0x0 0. "DMAC_EN,This bit is used to enable the DW_axi_dmac. - 0: DW_axi_dmac disabled - 1: DW_axi_dmac enabled NOTE: If this bit DMAC_EN bit is cleared while any channel is still active then this bit still returns 1 to indicate that there are channels still.." "DW_axi_dmac is disabled,DW_axi_dmac is enabled" rgroup.long 0x14++0x3 line.long 0x0 "DMAC_CFGREG_1,This register is used to enable the DW_axi_dmac. which must be done before any channel activity can begin. This register also contains global interrupt enable bit." hexmask.long 0x0 0.--31. 1. "RSVD_DMAC_CFGREG,DMAC_CFGREG Reserved bits - Read Only" group.long 0x18++0x3 line.long 0x0 "DMAC_CHENREG_0,This is DW_axi_dmac Channel Enable Register. If software wants to set up a new channel. it can read this register to find out which channels are currently inactive and then enable an inactive channel with the required priority. All bits of.." bitfld.long 0x0 31. "CH8_SUSP_WE,This bit is used as a write enable to the Channel-8 Suspend bit. The read back value of this register bit is always 0. 0x0: Disable Write to CH8_SUSP bit 0x1: Enable Write to respective CH8_SUSP bit" "Disable Write to CH8_SUSP bit,Enable Write to respective CH8_SUSP bit" newline bitfld.long 0x0 30. "CH7_SUSP_WE,This bit is used as a write enable to the Channel-7 Suspend bit. The read back value of this register bit is always 0. 0x0: Disable Write to CH7_SUSP bit 0x1: Enable Write to respective CH7_SUSP bit" "Disable Write to CH7_SUSP bit,Enable Write to respective CH7_SUSP bit" newline bitfld.long 0x0 29. "CH6_SUSP_WE,This bit is used as a write enable to the Channel-6 Suspend bit. The read back value of this register bit is always 0. 0x0: Disable Write to CH6_SUSP bit 0x1: Enable Write to respective CH6_SUSP bit" "Disable Write to CH6_SUSP bit,Enable Write to respective CH6_SUSP bit" newline bitfld.long 0x0 28. "CH5_SUSP_WE,This bit is used as a write enable to the Channel-5 Suspend bit. The read back value of this register bit is always 0. 0x0: Disable Write to CH5_SUSP bit 0x1: Enable Write to respective CH5_SUSP bit" "Disable Write to CH5_SUSP bit,Enable Write to respective CH5_SUSP bit" newline bitfld.long 0x0 27. "CH4_SUSP_WE,This bit is used as a write enable to the Channel-4 Suspend bit. The read back value of this register bit is always 0. 0x0: Disable Write to CH4_SUSP bit 0x1: Enable Write to respective CH4_SUSP bit" "Disable Write to CH4_SUSP bit,Enable Write to respective CH4_SUSP bit" newline bitfld.long 0x0 26. "CH3_SUSP_WE,This bit is used as a write enable to the Channel-3 Suspend bit. The read back value of this register bit is always 0. 0x0: Disable Write to CH3_SUSP bit 0x1: Enable Write to respective CH3_SUSP bit" "Disable Write to CH3_SUSP bit,Enable Write to respective CH3_SUSP bit" newline bitfld.long 0x0 25. "CH2_SUSP_WE,This bit is used as a write enable to the Channel-2 Suspend bit. The read back value of this register bit is always 0. 0x0: Disable Write to CH2_SUSP bit 0x1: Enable Write to respective CH2_SUSP bit" "Disable Write to CH2_SUSP bit,Enable Write to respective CH2_SUSP bit" newline bitfld.long 0x0 24. "CH1_SUSP_WE,This bit is used as a write enable to the Channel-1 Suspend bit. The read back value of this register bit is always 0. 0x0: Disable Write to CH1_SUSP bit 0x1: Enable Write to respective CH1_SUSP bit" "Disable Write to CH1_SUSP bit,Enable Write to respective CH1_SUSP bit" newline bitfld.long 0x0 23. "CH8_SUSP,Channel-8 Suspend Request. Software sets this bit to 1 to request channel suspend. If this bit is set to 1 DW_axi_dmac suspends all DMA data transfers from the source gracefully until this bit is cleared. There is no guarantee that the current.." "No Channel Suspend Request,Request to Suspended Channel-8" newline bitfld.long 0x0 22. "CH7_SUSP,Channel-7 Suspend Request. Software sets this bit to 1 to request channel suspend. If this bit is set to 1 DW_axi_dmac suspends all DMA data transfers from the source gracefully until this bit is cleared. There is no guarantee that the current.." "No Channel Suspend Request,Request to Suspended Channel-7" newline bitfld.long 0x0 21. "CH6_SUSP,Channel-6 Suspend Request. Software sets this bit to 1 to request channel suspend. If this bit is set to 1 DW_axi_dmac suspends all DMA data transfers from the source gracefully until this bit is cleared. There is no guarantee that the current.." "No Channel Suspend Request,Request to Suspended Channel-6" newline bitfld.long 0x0 20. "CH5_SUSP,Channel-5 Suspend Request. Software sets this bit to 1 to request channel suspend. If this bit is set to 1 DW_axi_dmac suspends all DMA data transfers from the source gracefully until this bit is cleared. There is no guarantee that the current.." "No Channel Suspend Request,Request to Suspended Channel-5" newline bitfld.long 0x0 19. "CH4_SUSP,Channel-4 Suspend Request. Software sets this bit to 1 to request channel suspend. If this bit is set to 1 DW_axi_dmac suspends all DMA data transfers from the source gracefully until this bit is cleared. There is no guarantee that the current.." "No Channel Suspend Request,Request to Suspended Channel-4" newline bitfld.long 0x0 18. "CH3_SUSP,Channel-3 Suspend Request. Software sets this bit to 1 to request channel suspend. If this bit is set to 1 DW_axi_dmac suspends all DMA data transfers from the source gracefully until this bit is cleared. There is no guarantee that the current.." "No Channel Suspend Request,Request to Suspended Channel-3" newline bitfld.long 0x0 17. "CH2_SUSP,Channel-2 Suspend Request. Software sets this bit to 1 to request channel suspend. If this bit is set to 1 DW_axi_dmac suspends all DMA data transfers from the source gracefully until this bit is cleared. There is no guarantee that the current.." "No Channel Suspend Request,Request to Suspended Channel-2" newline bitfld.long 0x0 16. "CH1_SUSP,Channel-1 Suspend Request. Software sets this bit to 1 to request channel suspend. If this bit is set to 1 DW_axi_dmac suspends all DMA data transfers from the source gracefully until this bit is cleared. There is no guarantee that the current.." "No Channel Suspend Request,Request to Suspended Channel-1" newline bitfld.long 0x0 15. "CH8_EN_WE,DW_axi_dmac Channel-8 Enable Write Enable bit. Read back value of this register bit is always '0'. 0x0: Disable Write to respective CH8_EN bit 0x1: Enable Write to CH8_EN bit" "Disable Write to respective CH8_EN bit,Enable Write to CH8_EN bit" newline bitfld.long 0x0 14. "CH7_EN_WE,DW_axi_dmac Channel-7 Enable Write Enable bit. Read back value of this register bit is always '0'. 0x0: Disable Write to respective CH7_EN bit 0x1: Enable Write to CH7_EN bit" "Disable Write to respective CH7_EN bit,Enable Write to CH7_EN bit" newline bitfld.long 0x0 13. "CH6_EN_WE,DW_axi_dmac Channel-6 Enable Write Enable bit. Read back value of this register bit is always '0'. 0x0: Disable Write to respective CH6_EN bit 0x1: Enable Write to CH6_EN bit" "Disable Write to respective CH6_EN bit,Enable Write to CH6_EN bit" newline bitfld.long 0x0 12. "CH5_EN_WE,DW_axi_dmac Channel-5 Enable Write Enable bit. Read back value of this register bit is always '0'. 0x0: Disable Write to respective CH5_EN bit 0x1: Enable Write to CH5_EN bit" "Disable Write to respective CH5_EN bit,Enable Write to CH5_EN bit" newline bitfld.long 0x0 11. "CH4_EN_WE,DW_axi_dmac Channel-4 Enable Write Enable bit. Read back value of this register bit is always '0'. 0x0: Disable Write to respective CH4_EN bit 0x1: Enable Write to CH4_EN bit" "Disable Write to respective CH4_EN bit,Enable Write to CH4_EN bit" newline bitfld.long 0x0 10. "CH3_EN_WE,DW_axi_dmac Channel-3 Enable Write Enable bit. Read back value of this register bit is always '0'. 0x0: Disable Write to respective CH3_EN bit 0x1: Enable Write to CH3_EN bit" "Disable Write to respective CH3_EN bit,Enable Write to CH3_EN bit" newline bitfld.long 0x0 9. "CH2_EN_WE,DW_axi_dmac Channel-2 Enable Write Enable bit. Read back value of this register bit is always '0'. 0x0: Disable Write to respective CH2_EN bit 0x1: Enable Write to CH2_EN bit" "Disable Write to respective CH2_EN bit,Enable Write to CH2_EN bit" newline bitfld.long 0x0 8. "CH1_EN_WE,DW_axi_dmac Channel-1 Enable Write Enable bit. Read back value of this register bit is always '0'. 0x0: Disable Write to respective CH1_EN bit 0x1: Enable Write to CH1_EN bit" "Disable Write to respective CH1_EN bit,Enable Write to CH1_EN bit" newline bitfld.long 0x0 7. "CH8_EN,This bit is used to enable the DW_axi_dmac Channel-8. - 0: DW_axi_dmac Channel-8 is disabled - 1: DW_axi_dmac Channel-8 is enabled The bit 'DMAC_ChEnReg.CH8_EN' is automatically cleared by hardware to disable the channel after the last AMBA.." "DW_axi_dmac: Channel-8 is disabled,DW_axi_dmac: Channel-8 is enabled" newline bitfld.long 0x0 6. "CH7_EN,This bit is used to enable the DW_axi_dmac Channel-7. - 0: DW_axi_dmac Channel-7 is disabled - 1: DW_axi_dmac Channel-7 is enabled The bit 'DMAC_ChEnReg.CH7_EN' is automatically cleared by hardware to disable the channel after the last AMBA.." "DW_axi_dmac: Channel-7 is disabled,DW_axi_dmac: Channel-7 is enabled" newline bitfld.long 0x0 5. "CH6_EN,This bit is used to enable the DW_axi_dmac Channel-6. - 0: DW_axi_dmac Channel-6 is disabled - 1: DW_axi_dmac Channel-6 is enabled The bit 'DMAC_ChEnReg.CH6_EN' is automatically cleared by hardware to disable the channel after the last AMBA.." "DW_axi_dmac: Channel-6 is disabled,DW_axi_dmac: Channel-6 is enabled" newline bitfld.long 0x0 4. "CH5_EN,This bit is used to enable the DW_axi_dmac Channel-5. - 0: DW_axi_dmac Channel-5 is disabled - 1: DW_axi_dmac Channel-5 is enabled The bit 'DMAC_ChEnReg.CH5_EN' is automatically cleared by hardware to disable the channel after the last AMBA.." "DW_axi_dmac: Channel-5 is disabled,DW_axi_dmac: Channel-5 is enabled" newline bitfld.long 0x0 3. "CH4_EN,This bit is used to enable the DW_axi_dmac Channel-4. - 0: DW_axi_dmac Channel-4 is disabled - 1: DW_axi_dmac Channel-4 is enabled The bit 'DMAC_ChEnReg.CH4_EN' is automatically cleared by hardware to disable the channel after the last AMBA.." "DW_axi_dmac: Channel-4 is disabled,DW_axi_dmac: Channel-4 is enabled" newline bitfld.long 0x0 2. "CH3_EN,This bit is used to enable the DW_axi_dmac Channel-3. - 0: DW_axi_dmac Channel-3 is disabled - 1: DW_axi_dmac Channel-3 is enabled The bit 'DMAC_ChEnReg.CH3_EN' is automatically cleared by hardware to disable the channel after the last AMBA.." "DW_axi_dmac: Channel-3 is disabled,DW_axi_dmac: Channel-3 is enabled" newline bitfld.long 0x0 1. "CH2_EN,This bit is used to enable the DW_axi_dmac Channel-2. - 0: DW_axi_dmac Channel-2 is disabled - 1: DW_axi_dmac Channel-2 is enabled The bit 'DMAC_ChEnReg.CH2_EN' is automatically cleared by hardware to disable the channel after the last AMBA.." "DW_axi_dmac: Channel-2 is disabled,DW_axi_dmac: Channel-2 is enabled" newline bitfld.long 0x0 0. "CH1_EN,This bit is used to enable the DW_axi_dmac Channel-1. - 0: DW_axi_dmac Channel-1 is disabled - 1: DW_axi_dmac Channel-1 is enabled The bit 'DMAC_ChEnReg.CH1_EN' is automatically cleared by hardware to disable the channel after the last AMBA.." "DW_axi_dmac: Channel-1 is disabled,DW_axi_dmac: Channel-1 is enabled" rgroup.long 0x1C++0x3 line.long 0x0 "DMAC_CHENREG_1,This is DW_axi_dmac Channel Enable Register. If software wants to set up a new channel. it can read this register to find out which channels are currently inactive and then enable an inactive channel with the required priority. All bits of.." hexmask.long.word 0x0 16.--31. 1. "RSVD_DMAC_CHENREG,DMAC_CHENREG Reserved bits - Read Only" newline bitfld.long 0x0 15. "CH8_ABORT_WE,This bit is used to write enable the Channel-8 Abort bit. The read back value of this register bit is always 0. 0x0: Disable Write to CH8_ABORT bit 0x1: Enable Write to CH8_ABORT bit" "Disable Write to CH8_ABORT bit,Enable Write to CH8_ABORT bit" newline bitfld.long 0x0 14. "CH7_ABORT_WE,This bit is used to write enable the Channel-7 Abort bit. The read back value of this register bit is always 0. 0x0: Disable Write to CH7_ABORT bit 0x1: Enable Write to CH7_ABORT bit" "Disable Write to CH7_ABORT bit,Enable Write to CH7_ABORT bit" newline bitfld.long 0x0 13. "CH6_ABORT_WE,This bit is used to write enable the Channel-6 Abort bit. The read back value of this register bit is always 0. 0x0: Disable Write to CH6_ABORT bit 0x1: Enable Write to CH6_ABORT bit" "Disable Write to CH6_ABORT bit,Enable Write to CH6_ABORT bit" newline bitfld.long 0x0 12. "CH5_ABORT_WE,This bit is used to write enable the Channel-5 Abort bit. The read back value of this register bit is always 0. 0x0: Disable Write to CH5_ABORT bit 0x1: Enable Write to CH5_ABORT bit" "Disable Write to CH5_ABORT bit,Enable Write to CH5_ABORT bit" newline bitfld.long 0x0 11. "CH4_ABORT_WE,This bit is used to write enable the Channel-4 Abort bit. The read back value of this register bit is always 0. 0x0: Disable Write to CH4_ABORT bit 0x1: Enable Write to CH4_ABORT bit" "Disable Write to CH4_ABORT bit,Enable Write to CH4_ABORT bit" newline bitfld.long 0x0 10. "CH3_ABORT_WE,This bit is used to write enable the Channel-3 Abort bit. The read back value of this register bit is always 0. 0x0: Disable Write to CH3_ABORT bit 0x1: Enable Write to CH3_ABORT bit" "Disable Write to CH3_ABORT bit,Enable Write to CH3_ABORT bit" newline bitfld.long 0x0 9. "CH2_ABORT_WE,This bit is used to write enable the Channel-2 Abort bit. The read back value of this register bit is always 0. 0x0: Disable Write to CH2_ABORT bit 0x1: Enable Write to CH2_ABORT bit" "Disable Write to CH2_ABORT bit,Enable Write to CH2_ABORT bit" newline bitfld.long 0x0 8. "CH1_ABORT_WE,This bit is used to write enable the Channel-1 Abort bit. The read back value of this register bit is always 0. 0x0: Disable Write to CH1_ABORT bit 0x1: Enable Write to CH1_ABORT bit" "Disable Write to CH1_ABORT bit,Enable Write to CH1_ABORT bit" newline bitfld.long 0x0 7. "CH8_ABORT,Channel-8 Abort Request. Software sets this bit to 1 to request channel abort. If this bit is set to 1 DW_axi_dmac disables the channel immediately. Aborting the channel might result in AXI Protocol violation as DW_axi_dmac does not make sure.." "No Request for Channel-8 Abort,Request for Channel-8 Abort" newline bitfld.long 0x0 6. "CH7_ABORT,Channel-7 Abort Request. Software sets this bit to 1 to request channel abort. If this bit is set to 1 DW_axi_dmac disables the channel immediately. Aborting the channel might result in AXI Protocol violation as DW_axi_dmac does not make sure.." "No Request for Channel-7 Abort,Request for Channel-7 Abort" newline bitfld.long 0x0 5. "CH6_ABORT,Channel-6 Abort Request. Software sets this bit to 1 to request channel abort. If this bit is set to 1 DW_axi_dmac disables the channel immediately. Aborting the channel might result in AXI Protocol violation as DW_axi_dmac does not make sure.." "No Request for Channel-6 Abort,Request for Channel-6 Abort" newline bitfld.long 0x0 4. "CH5_ABORT,Channel-5 Abort Request. Software sets this bit to 1 to request channel abort. If this bit is set to 1 DW_axi_dmac disables the channel immediately. Aborting the channel might result in AXI Protocol violation as DW_axi_dmac does not make sure.." "No Request for Channel-5 Abort,Request for Channel-5 Abort" newline bitfld.long 0x0 3. "CH4_ABORT,Channel-4 Abort Request. Software sets this bit to 1 to request channel abort. If this bit is set to 1 DW_axi_dmac disables the channel immediately. Aborting the channel might result in AXI Protocol violation as DW_axi_dmac does not make sure.." "No Request for Channel-4 Abort,Request for Channel-4 Abort" newline bitfld.long 0x0 2. "CH3_ABORT,Channel-3 Abort Request. Software sets this bit to 1 to request channel abort. If this bit is set to 1 DW_axi_dmac disables the channel immediately. Aborting the channel might result in AXI Protocol violation as DW_axi_dmac does not make sure.." "No Request for Channel-3 Abort,Request for Channel-3 Abort" newline bitfld.long 0x0 1. "CH2_ABORT,Channel-2 Abort Request. Software sets this bit to 1 to request channel abort. If this bit is set to 1 DW_axi_dmac disables the channel immediately. Aborting the channel might result in AXI Protocol violation as DW_axi_dmac does not make sure.." "No Request for Channel-2 Abort,Request for Channel-2 Abort" newline bitfld.long 0x0 0. "CH1_ABORT,Channel-1 Abort Request. Software sets this bit to 1 to request channel abort. If this bit is set to 1 DW_axi_dmac disables the channel immediately. Aborting the channel might result in AXI Protocol violation as DW_axi_dmac does not make sure.." "No Request for Channel-1 Abort,Request for Channel-1 Abort" rgroup.long 0x30++0x7 line.long 0x0 "DMAC_INTSTATUSREG_0,DMAC Interrupt Status Register captures the combined channel interrupt for each channel and Combined common register block interrupt. This register is present provided number of DMA channels are greater than 8." hexmask.long.word 0x0 17.--31. 1. "RSVD_DMAC_INTSTATUSREG_63TO17,DMAC Interrupt Status Register (bits 63to17) Reserved bits - Read Only" newline bitfld.long 0x0 16. "COMMONREG_INTSTAT,Common Register Interrupt Status Bit. 0x1: Common Register Interrupt is Active 0x0: Common Register Interrupt is Inactive" "Common Register Interrupt is Inactive,Common Register Interrupt is Active" newline hexmask.long.byte 0x0 8.--15. 1. "RSVD_DMAC_INTSTATUSREG,DMAC Interrupt Status Register (bits 15to8) Reserved bits - Read Only" newline bitfld.long 0x0 7. "CH8_INTSTAT,Channel 8 Interrupt Status Bit. 0x1: Channel 8 Interrupt is Active 0x0: Channel 8 Interrupt is Inactive" "Channel 8 Interrupt is Inactive,Channel 8 Interrupt is Active" newline bitfld.long 0x0 6. "CH7_INTSTAT,Channel 7 Interrupt Status Bit. 0x1: Channel 7 Interrupt is Active 0x0: Channel 7 Interrupt is Inactive" "Channel 7 Interrupt is Inactive,Channel 7 Interrupt is Active" newline bitfld.long 0x0 5. "CH6_INTSTAT,Channel 6 Interrupt Status Bit. 0x1: Channel 6 Interrupt is Active 0x0: Channel 6 Interrupt is Inactive" "Channel 6 Interrupt is Inactive,Channel 6 Interrupt is Active" newline bitfld.long 0x0 4. "CH5_INTSTAT,Channel 5 Interrupt Status Bit. 0x1: Channel 5 Interrupt is Active 0x0: Channel 5 Interrupt is Inactive" "Channel 5 Interrupt is Inactive,Channel 5 Interrupt is Active" newline bitfld.long 0x0 3. "CH4_INTSTAT,Channel 4 Interrupt Status Bit. 0x1: Channel 4 Interrupt is Active 0x0: Channel 4 Interrupt is Inactive" "Channel 4 Interrupt is Inactive,Channel 4 Interrupt is Active" newline bitfld.long 0x0 2. "CH3_INTSTAT,Channel 3 Interrupt Status Bit. 0x1: Channel 3 Interrupt is Active 0x0: Channel 3 Interrupt is Inactive" "Channel 3 Interrupt is Inactive,Channel 3 Interrupt is Active" newline bitfld.long 0x0 1. "CH2_INTSTAT,Channel 2 Interrupt Status Bit. 0x1: Channel 2 Interrupt is Active 0x0: Channel 2 Interrupt is Inactive" "Channel 2 Interrupt is Inactive,Channel 2 Interrupt is Active" newline bitfld.long 0x0 0. "CH1_INTSTAT,Channel 1 Interrupt Status Bit. 0x1: Channel 1 Interrupt is Active 0x0: Channel 1 Interrupt is Inactive" "Channel 1 Interrupt is Inactive,Channel 1 Interrupt is Active" line.long 0x4 "DMAC_INTSTATUSREG_1,DMAC Interrupt Status Register captures the combined channel interrupt for each channel and Combined common register block interrupt. This register is present provided number of DMA channels are greater than 8." hexmask.long 0x4 0.--31. 1. "RSVD_DMAC_INTSTATUSREG_63TO17,DMAC Interrupt Status Register (bits 63to17) Reserved bits - Read Only" wgroup.long 0x38++0x7 line.long 0x0 "DMAC_COMMONREG_INTCLEARREG_0,Writing 1 to specific field clears the corresponding field in DMAC Common register Interrupt Status Register (DMAC_CommonReg_IntStatusReg)." hexmask.long.tbyte 0x0 9.--31. 1. "RSVD_DMAC_COMMONREG_INTCLEARREG_63TO9,DMAC Common Register Interrupt Clear Register (bits 63to9) Reserved bits - Read Only" newline bitfld.long 0x0 8. "CLEAR_SLVIF_UNDEFINEDREG_DEC_ERR_INTSTAT,Slave Interface Undefined register Decode Error Interrupt clear Bit. This bit is used to clear the corresponding channel interrupt status bit(SLVIF_UndefinedReg_DEC_ERR_IntStat in DMAC_CommonReg_IntStatusReg. 0x1:.." "Inactive signal,Clear the SLVIF_UndefinedReg_DEC_ERR interrupt.." newline hexmask.long.byte 0x0 4.--7. 1. "RSVD_DMAC_COMMONREG_INTCLEARREG_7TO4,DMAC Common Register Interrupt Clear Register (bits 7to4) Reserved bits - Read Only" newline bitfld.long 0x0 3. "CLEAR_SLVIF_COMMONREG_WRONHOLD_ERR_INTSTAT,Slave Interface Common Register Write On Hold Error Interrupt clear Bit. This bit is used to clear the corresponding channel interrupt status bit(SLVIF_CommonReg_WrOnHold_ERR_IntStat in.." "Inactive signal,Clear the SLVIF_CommonReg_WrOnHold_ERR interrupt.." newline bitfld.long 0x0 2. "CLEAR_SLVIF_COMMONREG_RD2WO_ERR_INTSTAT,Slave Interface Common Register Read to Write only Error Interrupt clear Bit. This bit is used to clear the corresponding channel interrupt status bit(SLVIF_CommonReg_RD2WO_ERR_IntStat in.." "Inactive signal,Clear the SLVIF_CommonReg_RD2WO_ERR interrupt in.." newline bitfld.long 0x0 1. "CLEAR_SLVIF_COMMONREG_WR2RO_ERR_INTSTAT,Slave Interface Common Register Write to Read only Error Interrupt clear Bit. This bit is used to clear the corresponding channel interrupt status bit(SLVIF_CommonReg_WR2RO_ERR_IntStat in.." "Inactive signal,Clear the SLVIF_CommonReg_WR2RO_ERR interrupt in.." newline bitfld.long 0x0 0. "CLEAR_SLVIF_COMMONREG_DEC_ERR_INTSTAT,Slave Interface Common Register Decode Error Interrupt clear Bit. This bit is used to clear the corresponding channel interrupt status bit (SLVIF_CommonReg_DEC_ERR_IntStat in DMAC_CommonReg_IntStatusReg. 0x1: Clear.." "Inactive signal,Clear the SLVIF_CommonReg_DEC_ERR interrupt in.." line.long 0x4 "DMAC_COMMONREG_INTCLEARREG_1,Writing 1 to specific field clears the corresponding field in DMAC Common register Interrupt Status Register (DMAC_CommonReg_IntStatusReg)." hexmask.long 0x4 0.--31. 1. "RSVD_DMAC_COMMONREG_INTCLEARREG_63TO9,DMAC Common Register Interrupt Clear Register (bits 63to9) Reserved bits - Read Only" group.long 0x40++0x3 line.long 0x0 "DMAC_COMMONREG_INTSTATUS_ENABLEREG_0,Writing 1 to specific field enables the corresponding interrupt status generation in DMAC Common register Interrupt Status Register (DMAC_CommonReg_IntStatusReg)." hexmask.long.tbyte 0x0 9.--31. 1. "RSVD_DMAC_COMMONREG_INTSTATUS_ENABLEREG_63TO9,DMAC Common Register Interrupt Status Enable Register (bits 63to9) Reserved bits - Read Only" newline bitfld.long 0x0 8. "ENABLE_SLVIF_UNDEFINEDREG_DEC_ERR_INTSTAT,Slave Interface Undefined register Decode Error Interrupt Status enable Bit. This bit is used to enable the corresponding channel interrupt status bit (SLVIF_UndefinedReg_DEC_ERR_IntStat in.." "SLVIF_UndefinedReg_DEC_ERR_IntStat bit in..,SLVIF_UndefinedReg_DEC_ERR_IntStat bit in.." newline hexmask.long.byte 0x0 4.--7. 1. "RSVD_DMAC_COMMONREG_INTSTATUS_ENABLEREG_7TO4,DMAC Common Register Interrupt Status Enable Register (bits 7to4) Reserved bits - Read Only" newline bitfld.long 0x0 3. "ENABLE_SLVIF_COMMONREG_WRONHOLD_ERR_INTSTAT,Slave Interface Common Register Write On Hold Error Interrupt Status Enable Bit. This bit is used to enable the corresponding channel interrupt status bit (SLVIF_CommonReg_WrOnHold_ERR_IntStat in.." "SLVIF_CommonReg_WrOnHold_ERR_IntStat bit in..,SLVIF_CommonReg_WrOnHold_ERR_IntStat bit in.." newline bitfld.long 0x0 2. "ENABLE_SLVIF_COMMONREG_RD2WO_ERR_INTSTAT,Slave Interface Common Register Read to Write only Error Interrupt Status Enable Bit. This bit is used to enable the corresponding channel interrupt status bit (SLVIF_CommonReg_RD2WO_ERR_IntStat in.." "SLVIF_CommonReg_RD2WO_ERR_IntStat bit in..,SLVIF_CommonReg_RD2WO_ERR_IntStat bit in.." newline bitfld.long 0x0 1. "ENABLE_SLVIF_COMMONREG_WR2RO_ERR_INTSTAT,Slave Interface Common Register Write to Read only Error Interrupt Status Enable Bit. This bit is used to enable the corresponding channel interrupt status bit (SLVIF_CommonReg_WR2RO_ERR_IntStat in.." "SLVIF_CommonReg_WR2RO_ERR_IntStat bit in..,SLVIF_CommonReg_WR2RO_ERR_IntStat bit in.." newline bitfld.long 0x0 0. "ENABLE_SLVIF_COMMONREG_DEC_ERR_INTSTAT,Slave Interface Common Register Decode Error Interrupt Status Enable Bit. This bit is used to enable the corresponding channel interrupt status bit (SLVIF_CommonReg_DEC_ERR_IntStat in DMAC_CommonReg_IntStatusReg." "SLVIF_CommonReg_DEC_ERR_IntStat bit in..,SLVIF_CommonReg_DEC_ERR_IntStat bit in.." rgroup.long 0x44++0x3 line.long 0x0 "DMAC_COMMONREG_INTSTATUS_ENABLEREG_1,Writing 1 to specific field enables the corresponding interrupt status generation in DMAC Common register Interrupt Status Register (DMAC_CommonReg_IntStatusReg)." hexmask.long 0x0 0.--31. 1. "RSVD_DMAC_COMMONREG_INTSTATUS_ENABLEREG_63TO9,DMAC Common Register Interrupt Status Enable Register (bits 63to9) Reserved bits - Read Only" group.long 0x48++0x3 line.long 0x0 "DMAC_COMMONREG_INTSIGNAL_ENABLEREG_0,Writing 1 to specific field will propagate the corresponding interrupt status in DMAC Common register Interrupt Status Register (DMAC_CommonReg_IntStatusReg) to generate an port level interrupt." hexmask.long.tbyte 0x0 9.--31. 1. "RSVD_DMAC_COMMONREG_INTSIGNAL_ENABLEREG_63TO9,DMAC Common Register Interrupt Signal Enable Register (bits 63to9) Reserved bits - Read Only" newline bitfld.long 0x0 8. "ENABLE_SLVIF_UNDEFINEDREG_DEC_ERR_INTSIGNAL,Slave Interface Undefined register Decode Error Interrupt Signal Enable Bit. This bit is used to enable the propagation of corresponding channel interrupt status bit(SLVIF_UndefinedReg_DEC_ERR_IntStat in.." "SLVIF_UndefinedReg_DEC_ERR_IntStat signal in..,SLVIF_UndefinedReg_DEC_ERR_IntStat signal in.." newline hexmask.long.byte 0x0 4.--7. 1. "RSVD_DMAC_COMMONREG_INTSIGNAL_ENABLEREG_7TO4,DMAC Common Register Interrupt Signal Enable Register (bits 7to4) Reserved bits - Read Only" newline bitfld.long 0x0 3. "ENABLE_SLVIF_COMMONREG_WRONHOLD_ERR_INTSIGNAL,Slave Interface Common Register Write On Hold Error Interrupt Signal Enable Bit. This bit is used to enable the propagation of corresponding channel interrupt status bit(SLVIF_CommonReg_WrOnHold_ERR_IntStat.." "SLVIF_CommonReg_WrOnHold_ERR_IntStat signal in..,SLVIF_CommonReg_WrOnHold_ERR_IntStat signal in.." newline bitfld.long 0x0 2. "ENABLE_SLVIF_COMMONREG_RD2WO_ERR_INTSIGNAL,Slave Interface Common Register Read to Write only Error Interrupt Signal Enable Bit. This bit is used to enable the propagation of corresponding channel interrupt status bit (SLVIF_CommonReg_RD2WO_ERR_IntStat.." "SLVIF_CommonReg_RD2WO_ERR_IntStat signal in..,SLVIF_CommonReg_RD2WO_ERR_IntStat signal in.." newline bitfld.long 0x0 1. "ENABLE_SLVIF_COMMONREG_WR2RO_ERR_INTSIGNAL,Slave Interface Common Register Write to Read only Error Interrupt Signal Enable Bit. This bit is used to enable the propagation of corresponding channel interrupt status bit (SLVIF_CommonReg_WR2RO_ERR_IntStat.." "SLVIF_CommonReg_WR2RO_ERR_IntStat signal in..,SLVIF_CommonReg_WR2RO_ERR_IntStat signal in.." newline bitfld.long 0x0 0. "ENABLE_SLVIF_COMMONREG_DEC_ERR_INTSIGNAL,Slave Interface Common Register Decode Error Interrupt Signal Enable Bit. This bit is used to enable the propagation of corresponding channel interrupt status bit (SLVIF_CommonReg_DEC_ERR_IntStat in.." "SLVIF_CommonReg_DEC_ERR_IntStat signal in..,SLVIF_CommonReg_DEC_ERR_IntStat signal in.." rgroup.long 0x4C++0xB line.long 0x0 "DMAC_COMMONREG_INTSIGNAL_ENABLEREG_1,Writing 1 to specific field will propagate the corresponding interrupt status in DMAC Common register Interrupt Status Register (DMAC_CommonReg_IntStatusReg) to generate an port level interrupt." hexmask.long 0x0 0.--31. 1. "RSVD_DMAC_COMMONREG_INTSIGNAL_ENABLEREG_63TO9,DMAC Common Register Interrupt Signal Enable Register (bits 63to9) Reserved bits - Read Only" line.long 0x4 "DMAC_COMMONREG_INTSTATUSREG_0,This Register captures Slave interface access errors. - Decode Error. - Write to read only register. - Read to write only register. - write on hold. - undefined address." hexmask.long.tbyte 0x4 9.--31. 1. "RSVD_DMAC_COMMONREG_INTSTATUSREG_63TO9,DMAC Common Register Interrupt Signal Enable Register (bits 63to9) Reserved bits - Read Only" newline bitfld.long 0x4 8. "SLVIF_UNDEFINEDREG_DEC_ERR_INTSTAT,Slave Interface Undefined register Decode Error Interrupt Signal Enable Bit. Decode Error generated by DW_axi_dmac during register access. This error occurs if the register access is to undefined address range (>0x8FF.." "No Slave Interface Decode Errors,Slave Interface Decode Error detected" newline hexmask.long.byte 0x4 4.--7. 1. "RSVD_DMAC_COMMONREG_INTSTATUSREG_7TO4,DMAC Common Register Interrupt Status Register (bits 7to4) Reserved bits - Read Only" newline bitfld.long 0x4 3. "SLVIF_COMMONREG_WRONHOLD_ERR_INTSTAT,Slave Interface Common Register Write On Hold Error Interrupt Status Bit. This error occurs if an illegal write operation is performed on a common register; this happens if a write operation is performed on a common.." "No Slave Interface Common Register Write On Hold..,Slave Interface Common Register Write On Hold.." newline bitfld.long 0x4 2. "SLVIF_COMMONREG_RD2WO_ERR_INTSTAT,Slave Interface Common Register Read to Write only Error Interrupt Status bit. This error occurs if Read operation is performed to a Write Only register in the common register space (0x000 to 0x0FF). - 0: No Slave.." "No Slave Interface Read to Write Only Errors,Slave Interface Read to Write Only Error detected" newline bitfld.long 0x4 1. "SLVIF_COMMONREG_WR2RO_ERR_INTSTAT,Slave Interface Common Register Write to Read Only Error Interrupt Status bit. This error occurs if write operation is performed to a Read Only register in the common register space (0x000 to 0x0FF). - 0: No Slave.." "Slave Interface Write to Read Only Error detected,No Slave Interface Write to Read Only Errors" newline bitfld.long 0x4 0. "SLVIF_COMMONREG_DEC_ERR_INTSTAT,Slave Interface Common Register Decode Error Interrupt Status Bit. Decode Error generated by DW_axi_dmac during register access. This error occurs if the register access is to an invalid address in the common register.." "No Slave Interface Decode Errors,Slave Interface Decode Error detected" line.long 0x8 "DMAC_COMMONREG_INTSTATUSREG_1,This Register captures Slave interface access errors. - Decode Error. - Write to read only register. - Read to write only register. - write on hold. - undefined address." hexmask.long 0x8 0.--31. 1. "RSVD_DMAC_COMMONREG_INTSTATUSREG_63TO9,DMAC Common Register Interrupt Signal Enable Register (bits 63to9) Reserved bits - Read Only" group.long 0x58++0x3 line.long 0x0 "DMAC_RESETREG_0,This register is used to initiate the Software Reset to DW_axi_dmac." hexmask.long 0x0 1.--31. 1. "RSVD_DMAC_RESETREG_1TO63,DMAC_ResetReg (bits 1to63) Reserved bits - Read Only" newline bitfld.long 0x0 0. "DMAC_RST,DMAC Reset Request bit Software writes 1 to this bit to reset the DW_axi_dmac and polls this bit to see it as 0. DW_axi_dmac resets all the modules except the slave bus interface module and clears this bit to 0. NOTE: Software is not allowed to.." "0,1" rgroup.long 0x5C++0x3 line.long 0x0 "DMAC_RESETREG_1,This register is used to initiate the Software Reset to DW_axi_dmac." hexmask.long 0x0 0.--31. 1. "RSVD_DMAC_RESETREG_1TO63,DMAC_ResetReg (bits 1to63) Reserved bits - Read Only" group.long 0x60++0x7 line.long 0x0 "DMAC_LOWPOWER_CFGREG_0,This register contains the fields that configures the Context Sensitive Low Power feature. This register should be programmed prior to enabling the channel." hexmask.long 0x0 4.--31. 1. "RSVD_DMAC_LOWPOWER_CFGREG_31TO4,DMAC_LOWPOWER_CFGREG (bits 4to31) Reserved bits - Read Only" newline bitfld.long 0x0 3. "MXIF_CSLP_EN,AXI Master Interface Context Sensitive Low Power feature enable. 0x0: AXI Master Interface Context Sensitive Low Power feature is disabled 0x1: AXI Master Interface Context Sensitive Low Power feature is enabled" "AXI Master Interface Context Sensitive Low Power..,AXI Master Interface Context Sensitive Low Power.." newline bitfld.long 0x0 2. "SBIU_CSLP_EN,SBIU Context Sensitive Low Power feature enable. 0x0: SBIU Context Sensitive Low Power feature is disabled 0x1: SBIU Context Sensitive Low Power feature is enabled" "SBIU Context Sensitive Low Power feature is..,SBIU Context Sensitive Low Power feature is.." newline bitfld.long 0x0 1. "CHNL_CSLP_EN,DMA Channel Context Sensitive Low Power feature enable. 0x0: DMA Channel Context Sensitive Low Power feature is disabled 0x1: DMA Channel Context Sensitive Low Power feature is enabled" "DMA Channel Context Sensitive Low Power feature..,DMA Channel Context Sensitive Low Power feature.." newline bitfld.long 0x0 0. "GBL_CSLP_EN,Global Context Sensitive Low Power feature enable. 0x0: Global Context Sensitive Low Power feature is disabled 0x1: Global Context Sensitive Low Power feature is enabled" "Global Context Sensitive Low Power feature is..,Global Context Sensitive Low Power feature is.." line.long 0x4 "DMAC_LOWPOWER_CFGREG_1,This register contains the fields that configures the Context Sensitive Low Power feature. This register should be programmed prior to enabling the channel." hexmask.long.byte 0x4 24.--31. 1. "RSVD_DMAC_LOWPOWER_CFGREG_63TO56,DMAC_LOWPOWER_CFGREG (bits 56to63) Reserved bits - Read Only" newline hexmask.long.byte 0x4 16.--23. 1. "MXIF_LPDLY,Defines the load value to be programmed into the AXI Master Interface low power delay counter. The programmed value must be greater than or equal to 0x4. If value programmed is less than 0x4 then the register value is reset to.." newline hexmask.long.byte 0x4 8.--15. 1. "SBIU_LPDLY,Defines the load value to be programmed into the SBIU low power delay counter. The programmed value must be greater than or equal to 0x4. If value programmed is less than 0x4 then the register value is reset to DMAX_SBIU_LPDLY. The maximum.." newline hexmask.long.byte 0x4 0.--7. 1. "GLCH_LPDLY,Defines the load value to be programmed into the Global and DMA Channel low power delay counter. The programmed value must be greater than or equal to 0x4. If value programmed is less than 0x4 then the register value is reset to.." tree.end tree "CH$1" repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) group.long ($2)++0x3 line.long 0x0 "CH$1_SAR_$1,The starting source address is programmed by software before the DMA channel is enabled. or by an LLI update before the start of the DMA transfer. While the DMA transfer is in progress. this register is updated to reflect the source address.." hexmask.long 0x0 0.--31. 1. "SAR,Current Source Address of DMA transfer. Updated after each source transfer. The SINC fields in the CHx_CTL register determines whether the address increments or is left unchanged on every source transfer throughout the block transfer." repeat.end repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) group.long ($2+0x8)++0x3 line.long 0x0 "CH$1_DAR_$1,The starting destination address is programmed by the software before the DMA channel is enabled. or by an LLI update before the start of the DMA transfer. While the DMA transfer is in progress. this register is updated to reflect the.." hexmask.long 0x0 0.--31. 1. "DAR,Current Destination Address of DMA transfer. Updated after each destination transfer. The DINC fields in the CHx_CTL register determines whether the address increments or is left unchanged on every destination transfer throughout the block transfer." repeat.end group.long 0x10++0x3 line.long 0x0 "CH$1_BLOCK_TS_0,When DW_axi_dmac is the flow controller. the DMAC uses this register before the channel is enabled for block-size." hexmask.long.word 0x0 16.--31. 1. "RSVD_DMAC_CHX_BLOCK_TSREG_63TO16,DMAC Channelx Block Transfer Size Register (bits 63to16) Reserved bits - Read Only" newline hexmask.long.word 0x0 0.--15. 1. "BLOCK_TS,Block Transfer Size. The number programmed into BLOCK_TS field indicates the total number of data of width CHx_CTL.SRC_TR_WIDTH to be transferred in a DMA block transfer. Block Transfer Size = BLOCK_TS+1 When the transfer starts the read-back.." rgroup.long 0x14++0x3 line.long 0x0 "CH$1_BLOCK_TS_1,When DW_axi_dmac is the flow controller. the DMAC uses this register before the channel is enabled for block-size." hexmask.long 0x0 0.--31. 1. "RSVD_DMAC_CHX_BLOCK_TSREG_63TO16,DMAC Channelx Block Transfer Size Register (bits 63to16) Reserved bits - Read Only" group.long 0x18++0x17 line.long 0x0 "CH$1_CTL_0,This register contains fields that control the DMA transfer. This register should be programmed prior to enabling the channel except for LLI-based multi-block transfer. When LLI-based multi-block transfer is enabled. the CHx_CTL register is.." rbitfld.long 0x0 31. "RSVD_DMAC_CHX_CTL_31,DMAC Channelx Control Transfer Register bit31 Reserved bits - Read Only" "0,1" newline bitfld.long 0x0 30. "NONPOSTED_LASTWRITE_EN,Non Posted Last Write Enable This bit decides whether posted writes can be used throughout the block transfer. - 0: Posted writes may be used throughout the block transfer. - 1: Posted writes may be used till the end of the block.." "Posted writes may be used throughout the block..,Last write in the block must be non-posted" newline hexmask.long.byte 0x0 26.--29. 1. "AW_CACHE,AXI 'aw_cache' signal" newline hexmask.long.byte 0x0 22.--25. 1. "AR_CACHE,AXI 'ar_cache' signal" newline hexmask.long.byte 0x0 18.--21. 1. "DST_MSIZE,Destination Burst Transaction Length. Number of data items each of width CHx_CTL.DST_TR_WIDTH to be written to the destination every time a destination burst transaction request is made from the corresponding hardware or software handshaking.." newline hexmask.long.byte 0x0 14.--17. 1. "SRC_MSIZE,Source Burst Transaction Length. Number of data items each of width CHx_CTL.SRC_TR_WIDTH to be read from the source every time a source burst transaction request is made from the corresponding hardware or software handshaking interface. The.." newline rbitfld.long 0x0 11.--13. "DST_TR_WIDTH,Destination Transfer Width. Mapped to AXI bus awsize this value must be less than or equal to DMAX_M_DATA_WIDTH. 0x4: Destination Transfer Width is 128 bits 0x1: Destination Transfer Width is 16 bits 0x5: Destination Transfer Width is 256.." "Destination Transfer Width is 8 bits,Destination Transfer Width is 16 bits,Destination Transfer Width is 32 bits,Destination Transfer Width is 64 bits,Destination Transfer Width is 128 bits,Destination Transfer Width is 256 bits,Destination Transfer Width is 512 bits,?" newline rbitfld.long 0x0 8.--10. "SRC_TR_WIDTH,Source Transfer Width. Mapped to AXI bus arsize this value must be less than or equal to DMAX_M_DATA_WIDTH. 0x4: Source Transfer Width is 128 bits 0x1: Source Transfer Width is 16 bits 0x5: Source Transfer Width is 256 bits 0x2: Source.." "Source Transfer Width is 8 bits,Source Transfer Width is 16 bits,Source Transfer Width is 32 bits,Source Transfer Width is 64 bits,Source Transfer Width is 128 bits,Source Transfer Width is 256 bits,Source Transfer Width is 512 bits,?" newline rbitfld.long 0x0 7. "RSVD_DMAC_CHX_CTL_7,DMAC Channelx Control Transfer Register bit7 Reserved bits - Read Only" "0,1" newline bitfld.long 0x0 6. "DINC,Destination Address Increment. Indicates whether to increment the destination address on every destination transfer. If the device is writing data from a source peripheral FIFO with a fixed address then set this field to 'No change'. - 0: Increment.." "Destination address incremented on every source..,Destination address is fixed" newline rbitfld.long 0x0 5. "RSVD_DMAC_CHX_CTL_5,DMAC Channelx Control Transfer Register bit5 Reserved bits - Read Only" "0,1" newline bitfld.long 0x0 4. "SINC,Source Address Increment. Indicates whether to increment the source address on every source transfer. If the device is fetching data from a source peripheral FIFO with a fixed address then set this field to 'No change'. - 0: Increment - 1: No.." "Source address incremented on every source..,Source address is fixed" newline rbitfld.long 0x0 3. "RSVD_DMAC_CHX_CTL_3,DMAC Channelx Control Transfer Register bit3 Reserved bits - Read Only" "0,1" newline rbitfld.long 0x0 2. "DMS,Destination Master Select. Identifies the Master Interface layer from which the destination device (peripheral or memory) is accessed. - 0: AXI master 1 - 1: AXI Master 2 0x0: Destination device on Master-1 interface layer 0x1: Destination device on.." "Destination device on Master-1 interface layer,Destination device on Master-2 interface layer" newline rbitfld.long 0x0 1. "RSVD_DMAC_CHX_CTL_1,DMAC Channelx Control Transfer Register bit1 Reserved bits - Read Only" "0,1" newline rbitfld.long 0x0 0. "SMS,Source Master Select. Identifies the Master Interface layer from which the source device (peripheral or memory) is accessed. - 0: AXI master 1 - 1: AXI Master 2 0x0: Source device on Master-1 interface layer 0x1: Source device on Master-2 interface.." "Source device on Master-1 interface layer,Source device on Master-2 interface layer" line.long 0x4 "CH$1_CTL_1,This register contains fields that control the DMA transfer. This register should be programmed prior to enabling the channel except for LLI-based multi-block transfer. When LLI-based multi-block transfer is enabled. the CHx_CTL register is.." bitfld.long 0x4 31. "SHADOWREG_OR_LLI_VALID,Shadow Register content/Linked List Item valid. Indicates whether the content of shadow register or the linked list item fetched from the memory is valid. - 0: Shadow Register content/LLI is invalid. - 1: Last Shadow Register/LLI.." "Shadow Register content/LLI is invalid,Last Shadow Register/LLI is valid" newline bitfld.long 0x4 30. "SHADOWREG_OR_LLI_LAST,Last Shadow Register/Linked List Item. Indicates whether shadow register content or the linked list item fetched from the memory is the last one or not. - 0: Not last Shadow Register/LLI - 1: Last Shadow Register/LLI LLI based.." "Indicates shadowreg/LLI content is not the last..,Indicates shadowreg/LLI content is the last one" newline rbitfld.long 0x4 27.--29. "RSVD_DMAC_CHX_CTL_59TO61,DMAC Channelx Control Transfer Register (bits 59to61) Reserved bits - Read Only" "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 26. "IOC_BLKTFR,Interrupt On completion of Block Transfer This bit is used to control the block transfer completion interrupt generation on a block by block basis for shadow register or linked list based multi-block transfers. Writing 1 to this register field.." "Disables CHx_IntStatusReg,Enables CHx_IntStatusReg" newline rbitfld.long 0x4 25. "DST_STAT_EN,Destination Status Enable Enable the logic to fetch status from destination peripheral of channel x pointed to by the content of CHx_DSTATAR register and stores it in CHx_DSTAT register. This value is written back to the CHx_DSTAT location of.." "No status fetch for Destination device,Enables status fetch for Destination and store.." newline rbitfld.long 0x4 24. "SRC_STAT_EN,Source Status Enable Enable the logic to fetch status from source peripheral of channel x pointed to by the content of CHx_SSTATAR register and stores it in CHx_SSTAT register. This value is written back to the CHx_SSTAT location of linked.." "No status fetch for Source device,Enables status fetch for Source and store the.." newline hexmask.long.byte 0x4 16.--23. 1. "AWLEN,Destination Burst Length AXI Burst length used for destination data transfer. The specified burst length is used for destination data transfer till the extent possible; remaining transfers use maximum possible value that is less than or equal to.." newline bitfld.long 0x4 15. "AWLEN_EN,Destination Burst Length Enable If this bit is set to 1 DW_axi_dmac uses the value of CHx_CTL.AWLEN as AXI Burst length for destination data transfer till the extent possible; remaining transfers use maximum possible burst length. If this bit.." "AXI Burst Length is any possible value <=..,AXI Burst Length is CH$1_CTL" newline hexmask.long.byte 0x4 7.--14. 1. "ARLEN,Source Burst Length AXI Burst length used for source data transfer. The specified burst length is used for source data transfer till the extent possible; remaining transfers use maximum possible value that is less than or equal to.." newline bitfld.long 0x4 6. "ARLEN_EN,Source Burst Length Enable If this bit is set to 1 DW_axi_dmac uses the value of CHx_CTL.ARLEN as AXI Burst length for source data transfer till the extent possible; remaining transfers use maximum possible burst length. If this bit is set to 0.." "AXI Burst Length is any possible value <=..,AXI Burst Length is CH$1_CTL" newline bitfld.long 0x4 3.--5. "AW_PROT,AXI 'aw_prot' signal" "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 0.--2. "AR_PROT,AXI 'ar_prot' signal" "0,1,2,3,4,5,6,7" line.long 0x8 "CH$1_CFG_0,This register contains fields that configure the DMA transfer. This register should be programmed prior to enabling the channel. Bits [63:32] of the channel configuration register remains fixed for all blocks of a multi-block transfer and can.." hexmask.long 0x8 4.--31. 1. "RSVD_DMAC_CHX_CFG_4TO31,DMAC Channelx Transfer Configuration Register (bits 4to31) Reserved bits - Read Only" newline bitfld.long 0x8 2.--3. "DST_MULTBLK_TYPE,Destination Multi Block Transfer Type. These bits define the type of multi-block transfer used for destination peripheral. - 00: Contiguous - 01: Reload - 10: Shadow Register - 11: Linked List If the type selected is Contiguous the.." "Contiguous Multiblock Type used for Destination..,Reload Multiblock Type used for Destination..,Shadow Register based Multiblock Type used for..,Linked List based Multiblock Type used for.." newline bitfld.long 0x8 0.--1. "SRC_MULTBLK_TYPE,Source Multi Block Transfer Type. These bits define the type of multi-block transfer used for source peripheral. - 00: Contiguous - 01: Reload - 10: Shadow Register - 11: Linked List If the type selected is Contiguous the CHx_SAR.." "Contiguous Multiblock Type used for Source..,Reload Multiblock Type used for Source Transfer,Shadow Register based Multiblock Type used for..,Linked List based Multiblock Type used for.." line.long 0xC "CH$1_CFG_1,This register contains fields that configure the DMA transfer. This register should be programmed prior to enabling the channel. Bits [63:32] of the channel configuration register remains fixed for all blocks of a multi-block transfer and can.." rbitfld.long 0xC 31. "RSVD_DMAC_CHX_CFG_63,DMAC Channelx Transfer Configuration Register (63bit) Reserved bit - Read Only" "0,1" newline hexmask.long.byte 0xC 27.--30. 1. "DST_OSR_LMT,Destination Outstanding Request Limit - Maximum outstanding request supported is 16. - Source Outstanding Request Limit = DST_OSR_LMT + 1" newline hexmask.long.byte 0xC 23.--26. 1. "SRC_OSR_LMT,Source Outstanding Request Limit - Maximum outstanding request supported is 16. - Source Outstanding Request Limit = SRC_OSR_LMT + 1" newline rbitfld.long 0xC 21.--22. "LOCK_CH_L,Channel Lock Level This bit indicates the duration over which CHx_CFG.LOCK_CH bit applies. - 00: Over complete DMA transfer - 01: Over DMA block transfer - 1x: Reserved This field does not exist if the configuration parameter DMAX_CHx_LOCK_EN.." "Duration of the Channel locking is for the..,Duration of the Channel locking is for the..,?,?" newline rbitfld.long 0xC 20. "LOCK_CH,Channel Lock bit When the channel is granted control of the master bus interface and if the CHx_CFG.LOCK_CH bit is asserted then no other channels are granted control of the master bus interface for the duration specified in CHx_CFG.LOCK_CH_L." "Channel is not locked during the transfers,Channel is locked and granted exclusive access.." newline bitfld.long 0xC 17.--19. "CH_PRIOR,Channel Priority A priority of DMAX_NUM_CHANNELS-1 is the highest priority and 0 is the lowest. This field must be programmed within the following range: 0: DMAX_NUM_CHANNELS-1 A programmed value outside this range will cause erroneous behavior." "DMAX_NUM_CHANNELS-1,?,?,?,?,?,?,?" newline rbitfld.long 0xC 16. "RSVD_DMAC_CHX_CFG_48,DMAC Channelx Transfer Configuration Register (48bit) Reserved bit - Read Only" "0,1" newline hexmask.long.byte 0xC 12.--15. 1. "DST_PER,Assigns a hardware handshaking interface (0 - DMAX_NUM_HS_IF-1) to the destination of Channelx if the CHx_CFG.HS_SEL_DST field is 0; otherwise this field is ignored. The channel can then communicate with the destination peripheral connected to.." newline rbitfld.long 0xC 11. "RSVD_DMAC_CHX_CFG_43,DMAC Channelx Transfer Configuration Register (43bit) Reserved bit - Read Only" "0,1" newline hexmask.long.byte 0xC 7.--10. 1. "SRC_PER,Assigns a hardware handshaking interface (0 - DMAX_NUM_HS_IF-1) to the source of Channelx if the CHx_CFG.HS_SEL_SRC field is 0; otherwise this field is ignored. The channel can then communicate with the source peripheral connected to that.." newline rbitfld.long 0xC 6. "DST_HWHS_POL,Destination Hardware Handshaking Interface Polarity. - 0: ACTIVE HIGH - 1: ACTIVE LOW 0x0: Polarity of the Handshaking Interface used for the Destination peripheral is Active High 0x1: Polarity of the Handshaking Interface used for the.." "Polarity of the Handshaking Interface used for..,Polarity of the Handshaking Interface used for.." newline rbitfld.long 0xC 5. "SRC_HWHS_POL,Source Hardware Handshaking Interface Polarity. - 0: ACTIVE HIGH - 1: ACTIVE LOW 0x0: Polarity of the Handshaking Interface used for the Source peripheral is Active High 0x1: Polarity of the Handshaking Interface used for the Source.." "Polarity of the Handshaking Interface used for..,Polarity of the Handshaking Interface used for.." newline bitfld.long 0xC 4. "HS_SEL_DST,Destination Software or Hardware Handshaking Select. This register selects which of the handshaking interfaces (hardware or software) is active for destination requests on this channel. - 0: Hardware handshaking interface. Software-initiated.." "Hardware Handshaking Interface is used for the..,Software Handshaking Interface is used for the.." newline bitfld.long 0xC 3. "HS_SEL_SRC,Source Software or Hardware Handshaking Select. This register selects which of the handshaking interfaces (hardware or software) is active for source requests on this channel. - 0: Hardware handshaking interface. Software-initiated transaction.." "Hardware Handshaking Interface is used for the..,Software Handshaking Interface is used for the.." newline bitfld.long 0xC 0.--2. "TT_FC,Transfer Type and Flow Control. The following transfer types are supported. - Memory to Memory - Memory to Peripheral - Peripheral to Memory - Peripheral to Peripheral Flow Control can be assigned to the DW_axi_dmac the source peripheral or hte.." "Transfer Type is memory to memory and Flow..,Transfer Type is memory to peripheral and Flow..,Transfer Type is peripheral to memory and Flow..,Transfer Type is peripheral to peripheral and..,?,?,?,Reserved" line.long 0x10 "CH$1_LLP_0,This is the Linked List Pointer register. This register must be programmed to point to the first Linked List Item (LLI) in memory prior to enabling the channel if linked-list-based block chaining is enabled. This register is updated with new.." hexmask.long 0x10 6.--31. 1. "LOC,Starting Address Memory of LLI block Starting Address In Memory of next LLI if block chaining is enabled. The six LSBs of the starting address are not stored because the address is assumed to be aligned to a 64-byte boundary. LLI access always uses.." newline hexmask.long.byte 0x10 1.--5. 1. "RSVD_DMAC_CHX_LLP_1TO5,DMAC Channelx Linked List Pointer Register (bits 1to5) Reserved bits - Read Only" newline rbitfld.long 0x10 0. "LMS,LLI master Select This bit identifies the AXI layer/interface where the memory device that stores the next linked list item resides. - 0: AXI Master 1 - 1: AXI Master 2 This field does not exist if the configuration parameter DMAX_CHx_LMS is not set.." "next Linked List item resides on AXI Master1..,next Linked List item resides on AXI Master2.." line.long 0x14 "CH$1_LLP_1,This is the Linked List Pointer register. This register must be programmed to point to the first Linked List Item (LLI) in memory prior to enabling the channel if linked-list-based block chaining is enabled. This register is updated with new.." hexmask.long 0x14 0.--31. 1. "LOC,Starting Address Memory of LLI block Starting Address In Memory of next LLI if block chaining is enabled. The six LSBs of the starting address are not stored because the address is assumed to be aligned to a 64-byte boundary. LLI access always uses.." rgroup.long 0x30++0x7 line.long 0x0 "CH$1_STATUSREG_0,Channelx Status Register contains fields that indicate the status of DMA transfers for Channelx." hexmask.long.word 0x0 22.--31. 1. "RSVD_DMAC_CHX_STATUSREG_22TO31,DMAC Channelx Status Register (bits 22to31) Reserved bits - Read Only" newline hexmask.long.tbyte 0x0 0.--21. 1. "CMPLTD_BLK_TFR_SIZE,Completed Block Transfer Size. This bit indicates the total number of data of width CHx_CTL.SRC_TR_WIDTH transferred for the previous block transfer. For normal block transfer completion without any errors this value will be equal to.." line.long 0x4 "CH$1_STATUSREG_1,Channelx Status Register contains fields that indicate the status of DMA transfers for Channelx." hexmask.long.tbyte 0x4 15.--31. 1. "RSVD_DMAC_CHX_STATUSREG_47TO63,DMAC Channelx Status Register (bits 47to63) Reserved bits - Read Only" newline hexmask.long.word 0x4 0.--14. 1. "DATA_LEFT_IN_FIFO,Data Left in FIFO. This bit indicates the total number of data left in DW_axi_dmac channel FIFO after completing the current block transfer. The width of the data in channel FIFO is equal to CHx_CTL.SRC_TR_WIDTH. For normal block.." group.long 0x38++0x3 line.long 0x0 "CH$1_SWHSSRCREG_0,Channelx Software handshake Source Register." hexmask.long 0x0 6.--31. 1. "RSVD_DMAC_CHX_SWHSSRCREG_6TO63,DMAC Channelx Software Handshake Source Register (bits 6to63) Reserved bits - Read Only" newline bitfld.long 0x0 5. "SWHS_LST_SRC_WE,Write Enable bit for Software Handshake Last Request for Channel Source. 0x0: Disables write to the SWHS_LAST_SRC bit 0x1: Enables write to the SWHS_LAST_SRC bit" "Disables write to the SWHS_LAST_SRC bit,Enables write to the SWHS_LAST_SRC bit" newline bitfld.long 0x0 4. "SWHS_LST_SRC,Software Handshake Last Request for Channel Source. This bit is used to request LAST dma source data transfer if software handshaking method is selected for the source of the corresponding channel. This bit is ignored if software handshaking.." "Source peripheral indication that the curent..,Source peripheral indication to dmac that the.." newline bitfld.long 0x0 3. "SWHS_SGLREQ_SRC_WE,Write Enable bit for Software Handshake Single Request for Channel Source. 0x0: Disables write to the SWHS_SGLREQ_SRC bit 0x1: Enables write to the SWHS_SGLREQ_SRC bit" "Disables write to the SWHS_SGLREQ_SRC bit,Enables write to the SWHS_SGLREQ_SRC bit" newline bitfld.long 0x0 2. "SWHS_SGLREQ_SRC,Software Handshake Single Request for Channel Source. This bit is used to request SINGLE (AXI burst length = 1) dma source data transfer if software handshaking method is selected for the source of the corresponding channel. This bit is.." "Source peripheral is not requesting for a single..,Source peripheral request for a single dma.." newline bitfld.long 0x0 1. "SWHS_REQ_SRC_WE,Write Enable bit for Software Handshake Request for Channel Source. Note: This bit always returns 0 on a read back. 0x0: Disables write to the SWHS_REQ_SRC bit 0x1: Enables write to the SWHS_REQ_SRC bit" "Disables write to the SWHS_REQ_SRC bit,Enables write to the SWHS_REQ_SRC bit" newline bitfld.long 0x0 0. "SWHS_REQ_SRC,Software Handshake Request for Channel Source. This bit is used to request dma source data transfer if software handshaking method is selected for the source of the corresponding channel. This bit is ignored if software handshaking is not.." "Source peripheral is not requesting for a burst..,Source peripheral request for a dma transfer" rgroup.long 0x3C++0x3 line.long 0x0 "CH$1_SWHSSRCREG_1,Channelx Software handshake Source Register." hexmask.long 0x0 0.--31. 1. "RSVD_DMAC_CHX_SWHSSRCREG_6TO63,DMAC Channelx Software Handshake Source Register (bits 6to63) Reserved bits - Read Only" group.long 0x40++0x3 line.long 0x0 "CH$1_SWHSDSTREG_0,Channelx Software handshake Destination Register." hexmask.long 0x0 6.--31. 1. "RSVD_DMAC_CHX_SWHSDSTREG_6TO63,DMAC Channelx Software Handshake Destination Register (bits 6to63) Reserved bits - Read Only" newline bitfld.long 0x0 5. "SWHS_LST_DST_WE,Write Enable bit for Software Handshake Last Request for Channel Destination. Note: This bit always returns 0 on a read back. 0x0: Disables write to the SWHS_LAST_DST bit 0x1: Enables write to the SWHS_LAST_DST bit" "Disables write to the SWHS_LAST_DST bit,Enables write to the SWHS_LAST_DST bit" newline bitfld.long 0x0 4. "SWHS_LST_DST,Software Handshake Last Request for Channel Destination. This bit is used to request LAST dma destination data transfer if software handshaking method is selected for the destination of the corresponding channel. This bit is ignored if.." "Destination peripheral indication that the..,Destination peripheral indication to dmac that.." newline bitfld.long 0x0 3. "SWHS_SGLREQ_DST_WE,Write Enable bit for Software Handshake Single Request for Channel Destination. Note: This bit always returns 0 on a read block. 0x0: Disables write to the SWHS_SGLREQ_DST bit 0x1: Enables write to the SWHS_SGLREQ_DST bit" "Disables write to the SWHS_SGLREQ_DST bit,Enables write to the SWHS_SGLREQ_DST bit" newline bitfld.long 0x0 2. "SWHS_SGLREQ_DST,Software Handshake Single Request for Channel Destination. This bit is used to request SINGLE (AXI burst length = 1) dma destination data transfer if software handshaking method is selected for the destination of the corresponding.." "Destination peripheral is not requesting for a..,Destination peripheral request for a single dma.." newline bitfld.long 0x0 1. "SWHS_REQ_DST_WE,Write Enable bit for Software Handshake Request for Channel Destination. Note: This bit always returns 0 on a read block. 0x0: Disables write to the SWHS_REQ_DST bit 0x1: Enables write to the SWHS_REQ_DST bit" "Disables write to the SWHS_REQ_DST bit,Enables write to the SWHS_REQ_DST bit" newline bitfld.long 0x0 0. "SWHS_REQ_DST,Software Handshake Request for Channel Destination. This bit is used to request dma destination data transfer if software handshaking method is selected for the destination of the corresponding channel. This bit is ignored if software.." "Destination peripheral is not requesting for a..,Destination peripheral request for a dma transfer" rgroup.long 0x44++0x3 line.long 0x0 "CH$1_SWHSDSTREG_1,Channelx Software handshake Destination Register." hexmask.long 0x0 0.--31. 1. "RSVD_DMAC_CHX_SWHSDSTREG_6TO63,DMAC Channelx Software Handshake Destination Register (bits 6to63) Reserved bits - Read Only" wgroup.long 0x48++0x7 line.long 0x0 "CH$1_BLK_TFR_RESUMEREQREG_0,Channelx Block Transfer Resume Request Register. This register is used during Linked List or Shadow Register based multi-block transfer. - For Linked-List-based multi-block transfer. ShadowReg_Or_LLI_Valid bit in LLI.CHx_CTL.." hexmask.long 0x0 1.--31. 1. "RSVD_DMAC_CHX_BLK_TFR_RESUMEREQREG_1TO63,DMAC Channelx Block Transfer Resume Request Register (bits 1to63) Reserved bits - Read Only" newline bitfld.long 0x0 0. "BLK_TFR_RESUMEREQ,Block Transfer Resume Request during Linked-List or Shadow-Register-based multi-block transfer. 0x1: Request for resuming the block transfer 0x0: No request to resume the block transfer" "No request to resume the block transfer,Request for resuming the block transfer" line.long 0x4 "CH$1_BLK_TFR_RESUMEREQREG_1,Channelx Block Transfer Resume Request Register. This register is used during Linked List or Shadow Register based multi-block transfer. - For Linked-List-based multi-block transfer. ShadowReg_Or_LLI_Valid bit in LLI.CHx_CTL.." hexmask.long 0x4 0.--31. 1. "RSVD_DMAC_CHX_BLK_TFR_RESUMEREQREG_1TO63,DMAC Channelx Block Transfer Resume Request Register (bits 1to63) Reserved bits - Read Only" group.long 0x50++0x3 line.long 0x0 "CH$1_AXI_IDREG_0,Channelx AXI ID Register. This register is allowed to be updated only when the channel is disabled. which means that it remains fixed for the entire DMA transfer. Note: The presence of this register is determined by the DMAC_M_ID_WIDTH.." hexmask.long.word 0x0 18.--31. 1. "RSVD_DMAC_CHX_AXI_IDREG_IDW_L2NCM32TO63,DMAC Channelx AXI ID Register (bits (IDW-L2NC-1)to32) Reserved bits - Read Only" newline bitfld.long 0x0 16.--17. "AXI_WRITE_ID_SUFFIX,AXI Write ID Suffix. These bits form part of the AWID output of AXI3/AXI4 master interface. IDW = DMAX_M_ID_WIDTH L2NC = log2(DMAX_NUM_CHANNELS) The upper L2NC+1 bits of awidN is derived from the channel number which is currently.." "0,1,2,3" newline hexmask.long.word 0x0 2.--15. 1. "RSVD_DMAC_CHX_AXI_IDREG_IDW_L2NCM1TO31,DMAC Channelx AXI ID Register (bits (IDW-L2NC-1)to31) Reserved bits - Read Only" newline bitfld.long 0x0 0.--1. "AXI_READ_ID_SUFFIX,AXI Read ID Suffix These bits form part of the ARID output of AXI3/AXI4 master interface. IDW = DMAX_M_ID_WIDTH L2NC = log2(DMAX_NUM_CHANNELS) The upper L2NC+1 bits of aridN is derived from the channel number which is currently.." "0,1,2,3" rgroup.long 0x54++0x3 line.long 0x0 "CH$1_AXI_IDREG_1,Channelx AXI ID Register. This register is allowed to be updated only when the channel is disabled. which means that it remains fixed for the entire DMA transfer. Note: The presence of this register is determined by the DMAC_M_ID_WIDTH.." hexmask.long 0x0 0.--31. 1. "RSVD_DMAC_CHX_AXI_IDREG_32TO63,DMAC Channelx AXI ID Register (bits 32to63) Reserved bits - Read Only" group.long 0x58++0x3 line.long 0x0 "CH$1_AXI_QOSREG_0,Channelx AXI QOS Register. This register is allowed to be updated only when the channel is disabled. which means that it remains fixed for the entire DMA transfer." hexmask.long.tbyte 0x0 8.--31. 1. "RSVD_DMAC_CHX_AXI_QOSREG_8TO63,DMAC Channelx AXI QOS Register (bits 8to63) Reserved bits - Read Only" newline hexmask.long.byte 0x0 4.--7. 1. "AXI_ARQOS,AXI ARQOS. These bits form the arqos output of AXI4 master interface." newline hexmask.long.byte 0x0 0.--3. 1. "AXI_AWQOS,AXI AWQOS. These bits form the awqos output of AXI4 master interface." rgroup.long 0x5C++0x3 line.long 0x0 "CH$1_AXI_QOSREG_1,Channelx AXI QOS Register. This register is allowed to be updated only when the channel is disabled. which means that it remains fixed for the entire DMA transfer." hexmask.long 0x0 0.--31. 1. "RSVD_DMAC_CHX_AXI_QOSREG_8TO63,DMAC Channelx AXI QOS Register (bits 8to63) Reserved bits - Read Only" group.long 0x80++0x3 line.long 0x0 "CH$1_INTSTATUS_ENABLEREG_0,Writing 1 to specific field enables the corresponding interrupt status generation in Channelx Interrupt Status Register(CH$1_IntStatusReg)." bitfld.long 0x0 31. "ENABLE_CH_ABORTED_INTSTAT,Channel Aborted Status Enable. - 0: Disable the generation of Channel Aborted Interrupt in CHx_INTSTATUSREG - 1: Enable the generation of Channel Aborted Interrupt in CHx_INTSTATUSREG 0x0: Disable the generation of Channel.." "Disable the generation of Channel Aborted..,Enable the generation of Channel Aborted.." newline bitfld.long 0x0 30. "ENABLE_CH_DISABLED_INTSTAT,Channel Disabled Status Enable. - 0: Disable the generation of Channel Disabled Interrupt in CHx_INTSTATUSREG - 1: Enable the generation of Channel Disabled Interrupt in CHx_INTSTATUSREG 0x0: Disable the generation of Channel.." "Disable the generation of Channel Disabled..,Enable the generation of Channel Disabled.." newline bitfld.long 0x0 29. "ENABLE_CH_SUSPENDED_INTSTAT,Channel Suspended Status Enable. - 0: Disable the generation of Channel Suspended Interrupt in CHx_INTSTATUSREG - 1: Enable the generation of Channel Suspended Interrupt in CHx_INTSTATUSREG 0x0: Disable the generation of.." "Disable the generation of Channel Suspended..,Enable the generation of Channel Suspended.." newline bitfld.long 0x0 28. "ENABLE_CH_SRC_SUSPENDED_INTSTAT,Channel Source Suspended Status Enable. - 0: Disable the generation of Channel Source Suspended Interrupt in CHx_INTSTATUSREG - 1: Enable the generation of Channel Source Suspended Interrupt in CHx_INTSTATUSREG 0x0:.." "Disable the generation of Channel Source..,Enable the generation of Channel Source.." newline bitfld.long 0x0 27. "ENABLE_CH_LOCK_CLEARED_INTSTAT,Channel Lock Cleared Status Enable. - 0: Disable the generation of Channel LOCK CLEARED Interrupt in CHx_INTSTATUSREG - 1: Enable the generation of Channel LOCK CLEARED Interrupt in CHx_INTSTATUSREG 0x0: Disable the.." "Disable the generation of Channel LOCK CLEARED..,Enable the generation of Channel LOCK CLEARED.." newline hexmask.long.byte 0x0 22.--26. 1. "RSVD_DMAC_CHX_INTSTATUS_ENABLEREG_22TO26,DMAC Channelx Interrupt Status Register (bits 22to26) Reserved bits - Read Only" newline bitfld.long 0x0 21. "ENABLE_SLVIF_WRONHOLD_ERR_INTSTAT,Slave Interface Write On Hold Error Status Enable. - 0: Disable the generation of Slave Interface Write On Hold Error Interrupt in CHx_INTSTATUSREG - 1: Enable the generation of Slave Interface Write On Hold Error.." "Disable the generation of Slave Interface Write..,Enable the generation of Slave Interface Write.." newline bitfld.long 0x0 20. "ENABLE_SLVIF_SHADOWREG_WRON_VALID_ERR_INTSTAT,Shadow Register Write On Valid Error Status Enable. - 0: Disable the generation of Shadow Register Write On Valid Error Interrupt in CHx_INTSTATUSREG - 1: Enable the generation of Shadow register Write On.." "Disable the generation of Shadow Register Write..,Enable the generation of Shadow register Write.." newline bitfld.long 0x0 19. "ENABLE_SLVIF_WRONCHEN_ERR_INTSTAT,Slave Interface Write On Channel Enabled Error Status Enable. - 0: Disable the generation of Slave Interface Write On Channel enabled Error Interrupt in CHx_INTSTATUSREG - 1: Enable the generation of Slave Interface.." "Disable the generation of Slave Interface Write..,Enable the generation of Slave Interface Write.." newline bitfld.long 0x0 18. "ENABLE_SLVIF_RD2RWO_ERR_INTSTAT,Slave Interface Read to write Only Error Status Enable. - 0: Disable the generation of Slave Interface Read to Write only Error Interrupt in CHx_INTSTATUSREG - 1: Enable the generation of Slave Interface Read to Write Only.." "Disable the generation of Slave Interface Read..,Enable the generation of Slave Interface Read to.." newline bitfld.long 0x0 17. "ENABLE_SLVIF_WR2RO_ERR_INTSTAT,Slave Interface Write to Read Only Error Status Enable. - 0: Disable the generation of Slave Interface Write to Read only Error Interrupt in CHx_INTSTATUSREG - 1: Enable the generation of Slave Interface Write to Read Only.." "Disable the generation of Slave Interface Write..,Enable the generation of Slave Interface Write.." newline bitfld.long 0x0 16. "ENABLE_SLVIF_DEC_ERR_INTSTAT,Slave Interface Decode Error Status Enable. - 0: Disable the generation of Slave Interface Decode Error Interrupt in CHx_INTSTATUSREG - 1: Enable the generation of Slave Interface Decode Error Interrupt in CHx_INTSTATUSREG.." "Disable the generation of Slave Interface Decode..,Enable the generation of Slave Interface Decode.." newline rbitfld.long 0x0 15. "RSVD_DMAC_CHX_INTSTATUS_ENABLEREG_15,DMAC Channelx Interrupt Status Register (bit 15) Reserved bit - Read Only" "0,1" newline bitfld.long 0x0 14. "ENABLE_SLVIF_MULTIBLKTYPE_ERR_INTSTAT,Slave Interface Multi Block type Error Status Enable. - 0: Disable the generation of Slave Interface Multi Block type Error Interrupt in CHx_INTSTATUSREG - 1: Enable the generation of Slave Interface Multi Block type.." "Disable the generation of Slave Interface Multi..,Enable the generation of Slave Interface Multi.." newline bitfld.long 0x0 13. "ENABLE_SHADOWREG_OR_LLI_INVALID_ERR_INTSTAT,Shadow register or LLI Invalid Error Status Enable. - 0: Disable the generation of Shadow Register or LLI Invalid Error Interrupt in CHx_INTSTATUSREG - 1: Enable the generation of Shadow Register or LLI Invalid.." "Disable the generation of Shadow Register or LLI..,Enable the generation of Shadow Register or LLI.." newline bitfld.long 0x0 12. "ENABLE_LLI_WR_SLV_ERR_INTSTAT,LLI WRITE Slave Error Status Enable. - 0: Disable the generation of LLI WRITE Slave Error Interrupt in CHx_INTSTATUSREG - 1: Enable the generation of LLI WRITE Slave Error Interrupt in CHx_INTSTATUSREG 0x0: Disable the.." "Disable the generation of LLI WRITE Slave Error..,Enable the generation of LLI WRITE Slave Error.." newline bitfld.long 0x0 11. "ENABLE_LLI_RD_SLV_ERR_INTSTAT,LLI Read Slave Error Status Enable. - 0: Disable the generation of LLI Read Slave Error Interrupt in CHx_INTSTATUSREG - 1: Enable the generation of LLI Read Slave Error Interrupt in CHx_INTSTATUSREG 0x0: Disable the.." "Disable the generation of LLI Read Slave Error..,Enable the generation of LLI Read Slave Error.." newline bitfld.long 0x0 10. "ENABLE_LLI_WR_DEC_ERR_INTSTAT,LLI WRITE Decode Error Status Enable. - 0: Disable the generation of LLI WRITE Decode Error Interrupt in CHx_INTSTATUSREG - 1: Enable the generation of LLI WRITE Decode Error Interrupt in CHx_INTSTATUSREG 0x0: Disable the.." "Disable the generation of LLI WRITE Decode Error..,Enable the generation of LLI WRITE Decode Error.." newline bitfld.long 0x0 9. "ENABLE_LLI_RD_DEC_ERR_INTSTAT,LLI Read Decode Error Status Enable. - 0: Disable the generation of LLI Read Decode Error Interrupt in CHx_INTSTATUSREG - 1: Enable the generation of LLI Read Decode Error Interrupt in CHx_INTSTATUSREG 0x0: Disable the.." "Disable the generation of LLI Read Decode Error..,Enable the generation of LLI Read Decode Error.." newline bitfld.long 0x0 8. "ENABLE_DST_SLV_ERR_INTSTAT,Destination Slave Error Status Enable. - 0: Disable the generation of Destination Slave Error Interrupt in CHx_INTSTATUSREG - 1: Enable the generation of Destination Slave Error Interrupt in CHx_INTSTATUSREG 0x0: Disable the.." "Disable the generation of Destination Slave..,Enable the generation of Destination Slave Error.." newline bitfld.long 0x0 7. "ENABLE_SRC_SLV_ERR_INTSTAT,Source Slave Error Status Enable. - 0: Disable the generation of Source Slave Error Interrupt in CHx_INTSTATUSREG - 1: Enable the generation of Source Slave Error Interrupt in CHx_INTSTATUSREG 0x0: Disable the generation of.." "Disable the generation of Source Slave Error..,Enable the generation of Source Slave Error.." newline bitfld.long 0x0 6. "ENABLE_DST_DEC_ERR_INTSTAT,Destination Decode Error Status Enable. - 0: Disable the generation of Destination Decode Error Interrupt in CHx_INTSTATUSREG - 1: Enable the generation of Destination Decode Error Interrupt in CHx_INTSTATUSREG 0x0: Disable the.." "Disable the generation of Destination Decode..,Enable the generation of Destination Decode.." newline bitfld.long 0x0 5. "ENABLE_SRC_DEC_ERR_INTSTAT,Source Decode Error Status Enable. - 0: Disable the generation of Source Decode Error Interrupt in CHx_INTSTATUSREG - 1: Enable the generation of Source Decode Error Interrupt in CHx_INTSTATUSREG 0x0: Disable the generation of.." "Disable the generation of Source Decode Error..,Enable the generation of Source Decode Error.." newline bitfld.long 0x0 4. "ENABLE_DST_TRANSCOMP_INTSTAT,Destination Transaction Completed Status Enable. - 0: Disable the generation of Destination Transaction complete Interrupt in CHx_INTSTATUSREG - 1: Enable the generation of Destination Transaction complete Interrupt in.." "Disable the generation of Destination..,Enable the generation of Destination Transaction.." newline bitfld.long 0x0 3. "ENABLE_SRC_TRANSCOMP_INTSTAT,Source Transaction Completed Status Enable. - 0: Disable the generation of Source Transaction Complete Interrupt in CHx_INTSTATUSREG - 1: Enable the generation of Source Transaction Complete Interrupt in CHx_INTSTATUSREG 0x0:.." "Disable the generation of Source Transaction..,Enable the generation of Source Transaction.." newline rbitfld.long 0x0 2. "RSVD_DMAC_CHX_INTSTATUS_ENABLEREG_2,DMAC Channelx Interrupt Status Register (bit 2) Reserved bit - Read Only" "0,1" newline bitfld.long 0x0 1. "ENABLE_DMA_TFR_DONE_INTSTAT,DMA Transfer Done Interrupt Status Enable. - 0: Disable the generation of DMA Transfer Done Interrupt in CHx_INTSTATUSREG - 1: Enable the generation of DMA Transfer Done Interrupt in CHx_INTSTATUSREG 0x0: Disable the.." "Disable the generation of DMA Transfer Done..,Enable the generation of DMA Transfer Done.." newline bitfld.long 0x0 0. "ENABLE_BLOCK_TFR_DONE_INTSTAT,Block Transfer Done Interrupt Status Enable. - 0: Disable the generation of Block Transfer Done Interrupt in CHx_INTSTATUSREG - 1: Enable the generation of Block Transfer Done Interrupt in CHx_INTSTATUSREG 0x0: Disable the.." "Disable the generation of Block Transfer Done..,Enable the generation of Block Transfer Done.." rgroup.long 0x84++0xB line.long 0x0 "CH$1_INTSTATUS_ENABLEREG_1,Writing 1 to specific field enables the corresponding interrupt status generation in Channelx Interrupt Status Register(CH$1_IntStatusReg)." hexmask.long 0x0 0.--31. 1. "RSVD_DMAC_CHX_INTSTATUS_ENABLEREG_32TO63,DMAC Channelx Interrupt Status Register (bits 32to63) Reserved bits - Read Only" line.long 0x4 "CH$1_INTSTATUS_0,Channelx Interrupt Status Register captures the Channelx specific interrupts" bitfld.long 0x4 31. "CH_ABORTED_INTSTAT,Channel Aborted. This indicates to the software that the corresponding channel in DW_axi_dmac is aborted. - 0: Channel is not aborted - 1: Channel is aborted Error Interrupt is generated if the corresponding bit in.." "Channel is not aborted,Channel is aborted" newline bitfld.long 0x4 30. "CH_DISABLED_INTSTAT,Channel Disabled. This indicates to the software that the corresponding channel in DW_axi_dmac is disabled. - 0: Channel is not disabled. - 1: Channel is disabled. Error Interrupt is generated if the corresponding bit in.." "Channel is not disabled,Channel is disabled" newline bitfld.long 0x4 29. "CH_SUSPENDED_INTSTAT,Channel Suspended. This indicates to the software that the corresponding channel in DW_axi_dmac is suspended. - 0: Channel is not suspended. - 1: Channel is suspended. Error Interrupt is generated if the corresponding bit in.." "Channel is not suspended,Channel is suspended" newline bitfld.long 0x4 28. "CH_SRC_SUSPENDED_INTSTAT,Channel Source Suspended. This indicates to the software that the corresponding channel source data transfer in DW_axi_dmac is suspended. - 0: Channel source is not suspended - 1: Channel Source is suspended. Error Interrupt is.." "Channel source is not suspended,Channel Source is suspended" newline bitfld.long 0x4 27. "CH_LOCK_CLEARED_INTSTAT,Channel Lock Cleared. This indicates to the software that the locking of the corresponding channel in DW_axi_dmac is cleared. - 0: Channel locking is not cleared. - 1: Channel locking is cleared. Channel locking is cleared by.." "Channel locking is not cleared,Channel Locking is cleared" newline hexmask.long.byte 0x4 22.--26. 1. "RSVD_DMAC_CHX_INTSTATUSREG_22TO26,DMAC Channelx Specific Interrupt Register (bits 22to26) Reserved bits - Read Only" newline bitfld.long 0x4 21. "SLVIF_WRONHOLD_ERR_INTSTAT,Slave Interface Write On Hold Error. This error occurs if an illegal write operation is performed on a register; this happens if a write operation is performed on a channel register when DW_axi_dmac is in Hold mode. - 0: No.." "No Slave Interface Write On Hold Errors,Slave Interface Write On Hold Error detected" newline bitfld.long 0x4 20. "SLVIF_SHADOWREG_WRON_VALID_ERR_INTSTAT,Shadow Register Write On Valid Error. This error occurs if shadow register based multi-block transfer is enabled and software tries to write to the shadow register when CHx_CTL.ShadowReg_Or_LLI_Valid bit is 1. - 0:.." "No Slave Interface Shadow Register Write On..,Slave Interface Shadow Register Write On Valid.." newline bitfld.long 0x4 19. "SLVIF_WRONCHEN_ERR_INTSTAT,Slave Interface Write On Channel Enabled Error. This error occurs if an illegal write operation is performed on a register; this happens if a write operation is performed on a register when the channel is enabled and if it is.." "No Slave Interface Write On Channel Enabled Errors,Slave Interface Write On Channel Enabled Error.." newline bitfld.long 0x4 18. "SLVIF_RD2RWO_ERR_INTSTAT,Slave Interface Read to write Only Error. This error occurs if read operation is performed to a Write Only register. - 0: No Slave Interface Read to Write Only Errors. - 1: Slave Interface Read to Write Only Error detected. Error.." "No Slave Interface Read to Write Only Errors,Slave Interface Read to Write Only Error detected" newline bitfld.long 0x4 17. "SLVIF_WR2RO_ERR_INTSTAT,Slave Interface Write to Read Only Error. This error occurs if write operation is performed to a Read Only register. - 0: No Slave Interface Write to Read Only Errors. - 1: Slave Interface Write to Read Only Error detected. Error.." "No Slave Interface Write to Read Only Errors,Slave Interface Write to Read Only Error detected" newline bitfld.long 0x4 16. "SLVIF_DEC_ERR_INTSTAT,Slave Interface Decode Error. Decode Error generated by DW_axi_dmac during register access. This error occurs if the register access is to invalid address in Channelx register space resulting in error response by DW_axi_dmac slave.." "No Slave Interface Decode errors,Slave Interface Decode Error detected" newline bitfld.long 0x4 15. "RSVD_DMAC_CHX_INTSTATUSREG_15,DMAC Channelx Specific Interrupt Register (bit 15) Reserved bit - Read Only" "0,1" newline bitfld.long 0x4 14. "SLVIF_MULTIBLKTYPE_ERR_INTSTAT,Slave Interface Multi Block type Error. This error occurs if multi-block transfer type programmed in CHx_CFG register (SRC_MLTBLK_TYPE and DST_MLTBLK_TYPE) is invalid. This error condition causes the DW_axi_dmac to halt the.." "No Multi-block transfer type Errors,Multi-block transfer type Error detected" newline bitfld.long 0x4 13. "SHADOWREG_OR_LLI_INVALID_ERR_INTSTAT,Shadow register or LLI Invalid Error. This error occurs if CHx_CTL.ShadowReg_Or_LLI_Valid bit is seen to be 0 during DW_axi_dmac Shadow Register / LLI fetch phase. This error condition causes the DW_axi_dmac to halt.." "No Shadow Register / LLI Invalid errors,Shadow Register / LLI Invalid error detected" newline bitfld.long 0x4 12. "LLI_WR_SLV_ERR_INTSTAT,LLI WRITE Slave Error. Slave Error detected by Master Interface during LLI write-back operation. This error occurs if the slave interface on which LLI resides issues a Slave Error. This error condition causes the DW_axi_dmac to.." "No LLI write Slave Errors,LLI Write SLAVE Error detected" newline bitfld.long 0x4 11. "LLI_RD_SLV_ERR_INTSTAT,LLI Read Slave Error. Slave Error detected by Master Interface during LLI read operation. This error occurs if the slave interface on which LLI resides issues a Slave Error. This error condition causes the DW_axi_dmac to disable.." "No LLI Read Slave Errors,LLI read Slave Error detected" newline bitfld.long 0x4 10. "LLI_WR_DEC_ERR_INTSTAT,LLI WRITE Decode Error. Decode Error detected by Master Interface during LLI write-back operation. This error occurs if the access is to invalid address and a Decode Error is returned from interconnect/slave. This error condition.." "NO LLI Write Decode Errors,LLI write Decode Error detected" newline bitfld.long 0x4 9. "LLI_RD_DEC_ERR_INTSTAT,LLI Read Decode Error. Decode Error detected by Master Interface during LLI read operation. This error occurs if the access is to invalid address and a Decode Error is returned from interconnect/slave. This error condition causes.." "NO LLI Read Decode Errors,LLI Read Decode Error detected" newline bitfld.long 0x4 8. "DST_SLV_ERR_INTSTAT,Destination Slave Error. Slave Error detected by Master Interface during destination data transfer. This error occurs if the slave interface to which the data is written issues a Slave Error. This error condition causes the.." "No Destination Slave Errors,Destination Slave Errors Detected" newline bitfld.long 0x4 7. "SRC_SLV_ERR_INTSTAT,Source Slave Error. Slave Error detected by Master Interface during source data transfer. This error occurs if the slave interface from which the data is read issues a Slave Error. This error condition causes the DW_axi_dmac to.." "No Source Slave Errors,Source Slave Error Detected" newline bitfld.long 0x4 6. "DST_DEC_ERR_INTSTAT,Destination Decode Error. Decode Error detected by Master Interface during destination data transfer. This error occurs if the access is to invalid address and a Decode Error is returned from interconnect/slave. This error condition.." "No destination Decode Errors,Destination Decode Error Detected" newline bitfld.long 0x4 5. "SRC_DEC_ERR_INTSTAT,Source Decode Error. Decode Error detected by Master Interface during source data transfer. This error occurs if the access is to invalid address and a Decode Error is returned from interconnect/slave. This error condition causes the.." "No Source Decode Errors,Source Decode Error detected" newline bitfld.long 0x4 4. "DST_TRANSCOMP_INTSTAT,Destination Transaction Completed. This bit is cleared to 0 on writing 1 to the corresponding channel interrupt clear bit in CHx_IntClearReg register or on enabling the channel (needed when interrupt is not enabled. 0x1: Destination.." "Destination transaction is not complete,Destination transaction is complete" newline bitfld.long 0x4 3. "SRC_TRANSCOMP_INTSTAT,Source Transaction Completed. This bit is cleared to 0 on writing 1 to the corresponding channel interrupt clear bit in CHx_IntClearReg register or on enabling the channel (needed when interrupt is not enabled. 0x1: Source.." "Source transation is not complete,Source transaction is complete" newline bitfld.long 0x4 2. "RSVD_DMAC_CHX_INTSTATUSREG_2,DMAC Channelx Specific Interrupt Register (bit 2) Reserved bit - Read Only" "0,1" newline bitfld.long 0x4 1. "DMA_TFR_DONE_INTSTAT,DMA Transfer Done. This indicates to the software that the DW_axi_dmac has completed the requested DMA transfer. The DW_axi_dmac sets this bit to 1 along with setting CHx_INTSTATUS.BLOCK_TFR_DONE bit to 1 when the last block transfer.." "DMA Transfer not complete,DMA Transfer completed" newline bitfld.long 0x4 0. "BLOCK_TFR_DONE_INTSTAT,Block Transfer Done. This indicates to the software that the DW_axi_dmac has completed the requested block transfer. The DW_axi_dmac sets this bit to 1 when the transfer is successfully completed. - 0: Block Transfer not completed." "Block Transfer not complete,Block Transfer completed" line.long 0x8 "CH$1_INTSTATUS_1,Channelx Interrupt Status Register captures the Channelx specific interrupts" hexmask.long 0x8 0.--31. 1. "RSVD_DMAC_CHX_INTSTATUSREG_32TO63,DMAC Channelx Specific Interrupt Register (bits 32to63) Reserved bits - Read Only" group.long 0x90++0x3 line.long 0x0 "CH$1_INTSIGNAL_ENABLEREG_0,This register contains fields that are used to enable the generation of port level interrupt at the channel level." bitfld.long 0x0 31. "ENABLE_CH_ABORTED_INTSIGNAL,Channel Aborted Signal Enable. - 0: Disable the propagation of Channel Aborted Interrupt to generate a port level interrupt - 1: Enable the propagation of Channel Aborted Interrupt to generate a port level interrupt 0x0:.." "Disable the propagation of Channel Aborted..,Enable the propagation of Channel Aborted.." newline bitfld.long 0x0 30. "ENABLE_CH_DISABLED_INTSIGNAL,Channel Disabled Signal Enable. - 0: Disable the propagation of Channel Disabled Interrupt to generate a port level interrupt - 1: Enable the propagation of Channel Disabled Interrupt to generate a port level interrupt 0x0:.." "Disable the propagation of Channel Disabled..,Enable the propagation of Channel Disabled.." newline bitfld.long 0x0 29. "ENABLE_CH_SUSPENDED_INTSIGNAL,Channel Suspended Signal Enable. - 0: Disable the propagation of Channel Suspended Interrupt to generate a port level interrupt - 1: Enable the propagation of Channel Suspended Interrupt to generate a port level interrupt.." "Disable the propagation of Channel Suspended..,Enable the propagation of Channel Suspended.." newline bitfld.long 0x0 28. "ENABLE_CH_SRC_SUSPENDED_INTSIGNAL,Channel Source Suspended Signal Enable. - 0: Disable the propagation of Channel Source Suspended Interrupt to generate a port level interrupt - 1: Enable the propagation of Channel Source Suspended Interrupt to generate.." "Disable the propagation of Channel Source..,Enable the propagation of Channel Source.." newline bitfld.long 0x0 27. "ENABLE_CH_LOCK_CLEARED_INTSIGNAL,Channel Lock Cleared Signal Enable. - 0: Disable the propagation of Channel Lock Cleared Interrupt to generate a port level interrupt - 1: Enable the propagation of Channel Lock Cleared Interrupt to generate a port level.." "Disable the propagation of Channel Lock Cleared..,Enable the propagation of Channel Lock Cleared.." newline hexmask.long.byte 0x0 22.--26. 1. "RSVD_DMAC_CHX_INTSTATUS_ENABLEREG_22TO26,DMAC Channelx Interrupt Status Enable Register (bits 22to26) Reserved bits - Read Only" newline bitfld.long 0x0 21. "ENABLE_SLVIF_WRONHOLD_ERR_INTSIGNAL,Slave Interface Write On Hold Error Signal Enable. - 0: Disable the propagation of Slave Interface Write On Hold Error Interrupt to generate a port level interrupt - 1: Enable the propagation of Slave Interface Write.." "Disable the propagation of Slave Interface Write..,Enable the propagation of Slave Interface Write.." newline bitfld.long 0x0 20. "ENABLE_SLVIF_SHADOWREG_WRON_VALID_ERR_INTSIGNAL,Shadow Register Write On Valid Error Signal Enable. - 0: Disable the propagation of Shadow Register Write On Valid Error Interrupt to generate a port level interrupt - 1: Enable the propagation of Shadow.." "Disable the propagation of Shadow Register Write..,Enable the propagation of Shadow register Write.." newline bitfld.long 0x0 19. "ENABLE_SLVIF_WRONCHEN_ERR_INTSIGNAL,Slave Interface Write On Channel Enabled Error Signal Enable. - 0: Disable the propagation of Slave Interface Write On Channel enabled Error Interrupt to generate a port level interrupt - 1: Enable the propagation of.." "Disable the propagation of Slave Interface Write..,Enable the propagation of Slave Interface Write.." newline bitfld.long 0x0 18. "ENABLE_SLVIF_RD2RWO_ERR_INTSIGNAL,Slave Interface Read to write Only Error Signal Enable. - 0: Disable the propagation of Slave Interface Read to Write only Error Interrupt to generate a port level interrupt - 1: Enable the propagation of Slave Interface.." "Disable the propagation of Slave Interface Read..,Enable the propagation of Slave Interface Read.." newline bitfld.long 0x0 17. "ENABLE_SLVIF_WR2RO_ERR_INTSIGNAL,Slave Interface Write to Read Only Error Signal Enable. - 0: Disable the propagation of Slave Interface Write to Read only Error Interrupt to generate a port level interrupt - 1: Enable the propagation of Slave Interface.." "Disable the propagation of Slave Interface Write..,Enable the propagation of Slave Interface Write.." newline bitfld.long 0x0 16. "ENABLE_SLVIF_DEC_ERR_INTSIGNAL,Slave Interface Decode Error Signal Enable. - 0: Disable the propagation of Slave Interface Decode Error Interrupt to generate a port level interrupt - 1: Enable the propagation of Slave Interface Decode Error Interrupt to.." "Disable the propagation of Slave Interface..,Enable the propagation of Slave Interface Decode.." newline rbitfld.long 0x0 15. "RSVD_DMAC_CHX_INTSTATUS_ENABLEREG_15,DMAC Channelx Interrupt Status Enable Register (bit 15) Reserved bit - Read Only" "0,1" newline bitfld.long 0x0 14. "ENABLE_SLVIF_MULTIBLKTYPE_ERR_INTSIGNAL,Slave Interface Multi Block type Error Signal Enable. - 0: Disable the propagation of Slave Interface Multi Block type Error Interrupt to generate a port level interrupt - 1: Enable the propagation of Slave.." "Disable the propagation of Slave Interface Multi..,Enable the propagation of Slave Interface Multi.." newline bitfld.long 0x0 13. "ENABLE_SHADOWREG_OR_LLI_INVALID_ERR_INTSIGNAL,Shadow register or LLI Invalid Error Signal Enable. - 0: Disable the propagation of Shadow Register or LLI Invalid Error Interrupt to generate a port level interrupt - 1: Enable the propagation of Shadow.." "Disable the propagation of Shadow Register or..,Enable the propagation of Shadow Register or LLI.." newline bitfld.long 0x0 12. "ENABLE_LLI_WR_SLV_ERR_INTSIGNAL,LLI WRITE Slave Error Signal Enable. - 0: Disable the propagation of LLI WRITE Slave Error Interrupt to generate a port level interrupt - 1: Enable the propagation of LLI WRITE Slave Error Interrupt to generate a port.." "Disable the propagation of LLI WRITE Slave Error..,Enable the propagation of LLI WRITE Slave Error.." newline bitfld.long 0x0 11. "ENABLE_LLI_RD_SLV_ERR_INTSIGNAL,LLI Read Slave Error Signal Enable. - 0: Disable the propagation of LLI Read Slave Error Interrupt to generate a port level interrupt - 1: Enable the propagation of LLI Read Slave Error Interrupt to generate a port level.." "Disable the propagation of LLI Read Slave Error..,Enable the propagation of LLI Read Slave Error.." newline bitfld.long 0x0 10. "ENABLE_LLI_WR_DEC_ERR_INTSIGNAL,LLI WRITE Decode Error Signal Enable. - 0: Disable the propagation of LLI WRITE Decode Error Interrupt to generate a port level interrupt - 1: Enable the propagation of LLI WRITE Decode Error Interrupt to generate a port.." "Disable the propagation of LLI WRITE Decode..,Enable the propagation of LLI WRITE Decode Error.." newline bitfld.long 0x0 9. "ENABLE_LLI_RD_DEC_ERR_INTSIGNAL,LLI Read Decode Error Signal Enable. - 0: Disable the propagation of LLI Read Decode Error Interrupt to generate a port level interrupt - 1: Enable the propagation of LLI Read Decode Error Interrupt to generate a port.." "Disable the propagation of LLI Read Decode Error..,Enable the propagation of LLI Read Decode Error.." newline bitfld.long 0x0 8. "ENABLE_DST_SLV_ERR_INTSIGNAL,Destination Slave Error Signal Enable. - 0: Disable the propagation of Destination Slave Error Interrupt to generate a port level interrupt - 1: Enable the propagation of Destination Slave Error Interrupt to generate a port.." "Disable the propagation of Destination Slave..,Enable the propagation of Destination Slave.." newline bitfld.long 0x0 7. "ENABLE_SRC_SLV_ERR_INTSIGNAL,Source Slave Error Signal Enable. - 0: Disable the propagation of Source Slave Error Interrupt to generate a port level interrupt - 1: Enable the propagation of Source Slave Error Interrupt to generate a port level interrupt.." "Disable the propagation of Source Slave Error..,Enable the propagation of Source Slave Error.." newline bitfld.long 0x0 6. "ENABLE_DST_DEC_ERR_INTSIGNAL,Destination Decode Error Signal Enable. - 0: Disable the propagation of Destination Decode Error Interrupt to generate a port level interrupt - 1: Enable the propagation of Destination Decode Error Interrupt to generate a.." "Disable the propagation of Destination Decode..,Enable the propagation of Destination Decode.." newline bitfld.long 0x0 5. "ENABLE_SRC_DEC_ERR_INTSIGNAL,Source Decode Error Signal Enable. - 0: Disable the propagation of Source Decode Error Interrupt to generate a port level interrupt - 1: Enable the propagation of Source Decode Error Interrupt to generate a port level.." "Disable the propagation of Source Decode Error..,Enable the propagation of Source Decode Error.." newline bitfld.long 0x0 4. "ENABLE_DST_TRANSCOMP_INTSIGNAL,Destination Transaction Completed Signal Enable. - 0: Disable the propagation of Destination Transaction complete Interrupt to generate a port level interrupt - 1: Enable the propagation of Destination Transaction complete.." "Disable the propagation of Destination..,Enable the propagation of Destination.." newline bitfld.long 0x0 3. "ENABLE_SRC_TRANSCOMP_INTSIGNAL,Source Transaction Completed Signal Enable. - 0: Disable the propagation of Source Transaction Complete Interrupt to generate a port level interrupt - 1: Enable the propagation of Source Transaction Complete Interrupt to.." "Disable the propagation of Source Transaction..,Enable the propagation of Source Transaction.." newline rbitfld.long 0x0 2. "RSVD_DMAC_CHX_INTSTATUS_ENABLEREG_2,DMAC Channelx Interrupt Status Enable Register (bit 2) Reserved bit - Read Only" "0,1" newline bitfld.long 0x0 1. "ENABLE_DMA_TFR_DONE_INTSIGNAL,DMA Transfer Done Interrupt Signal Enable. - 0: Disable the propagation of DMA Transfer Done Interrupt to generate a port level interrupt - 1: Enable the propagation of DMA Transfer Done Interrupt to generate a port level.." "Disable the propagation of DMA Transfer Done..,Enable the propagation of DMA Transfer Done.." newline bitfld.long 0x0 0. "ENABLE_BLOCK_TFR_DONE_INTSIGNAL,Block Transfer Done Interrupt Signal Enable. - 0: Disable the propagation of Block Transfer Done Interrupt to generate a port level interrupt - 1: Enable the propagation of Block Transfer Done Interrupt to generate a port.." "Disable the propagation of Block Transfer Done..,Enable the propagation of Block Transfer Done.." rgroup.long 0x94++0x3 line.long 0x0 "CH$1_INTSIGNAL_ENABLEREG_1,This register contains fields that are used to enable the generation of port level interrupt at the channel level." hexmask.long 0x0 0.--31. 1. "RSVD_DMAC_CHX_INTSTATUS_ENABLEREG_32TO63,DMAC Channelx Interrupt Status Enable Register (bits 32to63) Reserved bits - Read Only" wgroup.long 0x98++0x7 line.long 0x0 "CH$1_INTCLEARREG_0,Writing 1 to specific field will clear the corresponding field in Channelx Interrupt Status Register(CHx_IntStatusReg)." bitfld.long 0x0 31. "CLEAR_CH_ABORTED_INTSTAT,Channel Aborted Interrupt Clear Bit. This bit is used to clear the corresponding channel interrupt status bit in CHx_INTSTATUSREG. 0x1: Clear the CH_ABORTED interrupt in the Interrupt Status Register(CH$1_IntStatusReg). 0x0:.." "Inactive signal,Clear the CH_ABORTED interrupt in the Interrupt.." newline bitfld.long 0x0 30. "CLEAR_CH_DISABLED_INTSTAT,Channel Disabled Interrupt Clear Bit. This bit is used to clear the corresponding channel interrupt status bit in CHx_INTSTATUSREG. 0x1: Clear the CH_DISABLED interrupt in the Interrupt Status Register(CH$1_IntStatusReg). 0x0:.." "Inactive signal,Clear the CH_DISABLED interrupt in the Interrupt.." newline bitfld.long 0x0 29. "CLEAR_CH_SUSPENDED_INTSTAT,Channel Suspended Interrupt Clear Bit. This bit is used to clear the corresponding channel interrupt status bit in CHx_INTSTATUSREG. 0x1: Clear the CH_SUSPENDED interrupt in the Interrupt Status Register(CH$1_IntStatusReg). 0x0:.." "Inactive signal,Clear the CH_SUSPENDED interrupt in the.." newline bitfld.long 0x0 28. "CLEAR_CH_SRC_SUSPENDED_INTSTAT,Channel Source Suspended Interrupt Clear Bit. This bit is used to clear the corresponding channel interrupt status bit in CHx_INTSTATUSREG. 0x1: Clear the CH_SRC_SUSPENDED interrupt in the Interrupt Status.." "Inactive signal,Clear the CH_SRC_SUSPENDED interrupt in the.." newline bitfld.long 0x0 27. "CLEAR_CH_LOCK_CLEARED_INTSTAT,Channel Lock Cleared Interrupt Clear Bit. This bit is used to clear the corresponding channel interrupt status bit in CHx_INTSTATUSREG. 0x1: Clear the CH_LOCK_CLEARED interrupt in the Interrupt Status.." "Inactive signal,Clear the CH_LOCK_CLEARED interrupt in the.." newline hexmask.long.byte 0x0 22.--26. 1. "RSVD_DMAC_CHX_INTCLEARREG_22TO26,DMAC Channelx Interrupt Clear Register (bits 22to26) Reserved bit - Read Only" newline bitfld.long 0x0 21. "CLEAR_SLVIF_WRONHOLD_ERR_INTSTAT,Slave Interface Write On Hold Error Interrupt Clear Bit. This bit is used to clear the corresponding channel interrupt status bit in CHx_INTSTATUSREG. 0x1: Clear the SLVIF_WRONHOLD_ERR interrupt in the Interrupt Status.." "Inactive signal,Clear the SLVIF_WRONHOLD_ERR interrupt in the.." newline bitfld.long 0x0 20. "CLEAR_SLVIF_SHADOWREG_WRON_VALID_ERR_INTSTAT,Shadow Register Write On Valid Error Interrupt Clear Bit. This bit is used to clear the corresponding channel interrupt status bit in CHx_INTSTATUSREG. 0x1: Clear the SLVIF_SHADOWREG_WRON_VALID_ERR interrupt.." "Inactive signal,Clear the SLVIF_SHADOWREG_WRON_VALID_ERR.." newline bitfld.long 0x0 19. "CLEAR_SLVIF_WRONCHEN_ERR_INTSTAT,Slave Interface Write On Channel Enabled Error Interrupt Clear Bit. This bit is used to clear the corresponding channel interrupt status bit in CHx_INTSTATUSREG. 0x1: Clear the SLVIF_WRONCHEN_ERR interrupt in the.." "Inactive signal,Clear the SLVIF_WRONCHEN_ERR interrupt in the.." newline bitfld.long 0x0 18. "CLEAR_SLVIF_RD2RWO_ERR_INTSTAT,Slave Interface Read to write Only Error Interrupt Clear Bit. This bit is used to clear the corresponding channel interrupt status bit in CHx_INTSTATUSREG. 0x1: Clear the SLVIF_RD2RWO_ERR interrupt in the Interrupt Status.." "Inactive signal,Clear the SLVIF_RD2RWO_ERR interrupt in the.." newline bitfld.long 0x0 17. "CLEAR_SLVIF_WR2RO_ERR_INTSTAT,Slave Interface Write to Read Only Error Interrupt Clear Bit. This bit is used to clear the corresponding channel interrupt status bit in CHx_INTSTATUSREG. 0x1: Clear the SLVIF_WR2RO_ERR interrupt in the Interrupt Status.." "Inactive signal,Clear the SLVIF_WR2RO_ERR interrupt in the.." newline bitfld.long 0x0 16. "CLEAR_SLVIF_DEC_ERR_INTSTAT,Slave Interface Decode Error Interrupt Clear Bit. This bit is used to clear the corresponding channel interrupt status bit in CHx_INTSTATUSREG. 0x1: Clear the SLVIF_DEC_ERR interrupt in the Interrupt Status.." "Inactive signal,Clear the SLVIF_DEC_ERR interrupt in the.." newline bitfld.long 0x0 15. "RSVD_DMAC_CHX_INTCLEARREG_15,DMAC Channelx Interrupt Clear Register (bit 15) Reserved bit - Read Only" "0,1" newline bitfld.long 0x0 14. "CLEAR_SLVIF_MULTIBLKTYPE_ERR_INTSTAT,Slave Interface Multi Block type Error Interrupt Clear Bit. This bit is used to clear the corresponding channel interrupt status bit in CHx_INTSTATUSREG. 0x1: Clear the SLVIF_MULTIBLKTYPE_ERR interrupt in the.." "Inactive signal,Clear the SLVIF_MULTIBLKTYPE_ERR interrupt in.." newline bitfld.long 0x0 13. "CLEAR_SHADOWREG_OR_LLI_INVALID_ERR_INTSTAT,Shadow register or LLI Invalid Error Interrupt Clear Bit. This bit is used to clear the corresponding channel interrupt status bit in CHx_INTSTATUSREG. 0x1: Clear the SHADOWREG_OR_LLI_INVALID_ERR interrupt in.." "Inactive signal,Clear the SHADOWREG_OR_LLI_INVALID_ERR interrupt.." newline bitfld.long 0x0 12. "CLEAR_LLI_WR_SLV_ERR_INTSTAT,LLI WRITE Slave Error Interrupt Clear Bit. This bit is used to clear the corresponding channel interrupt status bit in CHx_INTSTATUSREG. 0x1: Clear the LLI_WR_SLV_ERR interrupt in the Interrupt Status.." "Inactive signal,Clear the LLI_WR_SLV_ERR interrupt in the.." newline bitfld.long 0x0 11. "CLEAR_LLI_RD_SLV_ERR_INTSTAT,LLI Read Slave Error Interrupt Clear Bit. This bit is used to clear the corresponding channel interrupt status bit in CHx_INTSTATUSREG. 0x1: Clear the LLI_RD_SLV_ERR interrupt in the Interrupt Status.." "Inactive signal,Clear the LLI_RD_SLV_ERR interrupt in the.." newline bitfld.long 0x0 10. "CLEAR_LLI_WR_DEC_ERR_INTSTAT,LLI WRITE Decode Error Interrupt Clear Bit. This bit is used to clear the corresponding channel interrupt status bit in CHx_INTSTATUSREG. 0x1: Clear the LLI_WR_DEC_ERR interrupt in the Interrupt Status.." "Inactive signal,Clear the LLI_WR_DEC_ERR interrupt in the.." newline bitfld.long 0x0 9. "CLEAR_LLI_RD_DEC_ERR_INTSTAT,LLI Read Decode Error Interrupt Clear Bit. This bit is used to clear the corresponding channel interrupt status bit in CHx_INTSTATUSREG. 0x1: Clear the LLI_RD_DEC_ERR interrupt in the Interrupt Status.." "Inactive signal,Clear the LLI_RD_DEC_ERR interrupt in the.." newline bitfld.long 0x0 8. "CLEAR_DST_SLV_ERR_INTSTAT,Destination Slave Error Interrupt Clear Bit. This bit is used to clear the corresponding channel interrupt status bit in CHx_INTSTATUSREG. 0x1: Clear the DST_SLV_ERR interrupt in the Interrupt Status Register(CH$1_IntStatusReg)." "Inactive signal,Clear the DST_SLV_ERR interrupt in the Interrupt.." newline bitfld.long 0x0 7. "CLEAR_SRC_SLV_ERR_INTSTAT,Source Slave Error Interrupt Clear Bit. This bit is used to clear the corresponding channel interrupt status bit in CHx_INTSTATUSREG. 0x1: Clear the SRC_SLV_ERR interrupt in the Interrupt Status Register(CH$1_IntStatusReg). 0x0:.." "Inactive signal,Clear the SRC_SLV_ERR interrupt in the Interrupt.." newline bitfld.long 0x0 6. "CLEAR_DST_DEC_ERR_INTSTAT,Destination Decode Error Interrupt Clear Bit. This bit is used to clear the corresponding channel interrupt status bit in CHx_INTSTATUSREG. 0x1: Clear the DST_DEC_ERR interrupt in the Interrupt Status Register(CH$1_IntStatusReg)." "Inactive signal,Clear the DST_DEC_ERR interrupt in the Interrupt.." newline bitfld.long 0x0 5. "CLEAR_SRC_DEC_ERR_INTSTAT,Source Decode Error Interrupt Clear Bit. This bit is used to clear the corresponding channel interrupt status bit in CHx_INTSTATUSREG. 0x1: Clear the SRC_DEC_ERR interrupt in the Interrupt Status Register(CH$1_IntStatusReg). 0x0:.." "Inactive signal,Clear the SRC_DEC_ERR interrupt in the Interrupt.." newline bitfld.long 0x0 4. "CLEAR_DST_TRANSCOMP_INTSTAT,Destination Transaction Completed Interrupt Clear Bit. This bit is used to clear the corresponding channel interrupt status bit in CHx_INTSTATUSREG. 0x1: Clear the DST_TRANSCOMP interrupt in the Interrupt Status.." "Inactive signal,Clear the DST_TRANSCOMP interrupt in the.." newline bitfld.long 0x0 3. "CLEAR_SRC_TRANSCOMP_INTSTAT,Source Transaction Completed Interrupt Clear Bit. This bit is used to clear the corresponding channel interrupt status bit in CHx_INTSTATUSREG. 0x1: Clear the SRC_TRANSCOMP interrupt in the Interrupt Status.." "Inactive signal,Clear the SRC_TRANSCOMP interrupt in the.." newline bitfld.long 0x0 2. "RSVD_DMAC_CHX_INTCLEARREG_2,DMAC Channelx Interrupt Clear Register (bit 2) Reserved bit - Read Only" "0,1" newline bitfld.long 0x0 1. "CLEAR_DMA_TFR_DONE_INTSTAT,DMA Transfer Done Interrupt Clear Bit. This bit is used to clear the corresponding channel interrupt status bit in CHx_INTSTATUSREG. 0x1: Clear the DMA_TFR_DONE interrupt in the Interrupt Status Register(CH$1_IntStatusReg). 0x0:.." "Inactive signal,Clear the DMA_TFR_DONE interrupt in the.." newline bitfld.long 0x0 0. "CLEAR_BLOCK_TFR_DONE_INTSTAT,Block Transfer Done Interrupt Clear Bit. This bit is used to clear the corresponding channel interrupt status bit in CH$1_INTSTATUSREG 0x1: Clear the interrupt in the Interrupt Status Register(CHx_IntStatusReg). Writing a 1 to.." "Inactive signal,Clear the interrupt in the Interrupt Status.." line.long 0x4 "CH$1_INTCLEARREG_1,Writing 1 to specific field will clear the corresponding field in Channelx Interrupt Status Register(CHx_IntStatusReg)." hexmask.long 0x4 0.--31. 1. "RSVD_DMAC_CHX_INTCLEARREG_32TO63,DMAC Channelx Interrupt Clear Register (bits 32to63) Reserved bit - Read Only" tree.end tree.end repeat.end elif (CORENAME()=="CORTEXA55") repeat 8. (increment 1. 1.) (list ad:0x35500000 ad:0x35510000 ad:0x35520000 ad:0x35530000 ad:0x35540000 ad:0x35550000 ad:0x35560000 ad:0x35570000) tree "DMA$1" base $2 tree "Common" repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) rgroup.long ($2)++0x3 line.long 0x0 "DMAC_IDREG_$1,DMAC ID Register contains a 64-bit value that is hardwired and read back by a read to the DW_axi_dmac ID Register." hexmask.long 0x0 0.--31. 1. "DMAC_ID,DMAC ID Number." repeat.end repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) rgroup.long ($2+0x8)++0x3 line.long 0x0 "DMAC_COMPVERREG_$1,This register contains a 64-bit value that is hardwired and read back by a read to the DW_axi_dmac Component Version Register." hexmask.long 0x0 0.--31. 1. "DMAC_COMPVER,DMAC Component Version Number." repeat.end group.long 0x10++0x3 line.long 0x0 "DMAC_CFGREG_0,This register is used to enable the DW_axi_dmac. which must be done before any channel activity can begin. This register also contains global interrupt enable bit." hexmask.long 0x0 2.--31. 1. "RSVD_DMAC_CFGREG,DMAC_CFGREG Reserved bits - Read Only" newline bitfld.long 0x0 1. "INT_EN,This bit is used to globally enable the interrupt generation. - 0: DW_axi_dmac Interrupts are disabled - 1: DW_axi_dmac Interrupt logic is enabled. 0x0: DW_axi_dmac Interrupts are disabled 0x1: DW_axi_dmac Interrupts are enabled" "DW_axi_dmac Interrupts are disabled,DW_axi_dmac Interrupts are enabled" newline bitfld.long 0x0 0. "DMAC_EN,This bit is used to enable the DW_axi_dmac. - 0: DW_axi_dmac disabled - 1: DW_axi_dmac enabled NOTE: If this bit DMAC_EN bit is cleared while any channel is still active then this bit still returns 1 to indicate that there are channels still.." "DW_axi_dmac is disabled,DW_axi_dmac is enabled" rgroup.long 0x14++0x3 line.long 0x0 "DMAC_CFGREG_1,This register is used to enable the DW_axi_dmac. which must be done before any channel activity can begin. This register also contains global interrupt enable bit." hexmask.long 0x0 0.--31. 1. "RSVD_DMAC_CFGREG,DMAC_CFGREG Reserved bits - Read Only" group.long 0x18++0x3 line.long 0x0 "DMAC_CHENREG_0,This is DW_axi_dmac Channel Enable Register. If software wants to set up a new channel. it can read this register to find out which channels are currently inactive and then enable an inactive channel with the required priority. All bits of.." bitfld.long 0x0 31. "CH8_SUSP_WE,This bit is used as a write enable to the Channel-8 Suspend bit. The read back value of this register bit is always 0. 0x0: Disable Write to CH8_SUSP bit 0x1: Enable Write to respective CH8_SUSP bit" "Disable Write to CH8_SUSP bit,Enable Write to respective CH8_SUSP bit" newline bitfld.long 0x0 30. "CH7_SUSP_WE,This bit is used as a write enable to the Channel-7 Suspend bit. The read back value of this register bit is always 0. 0x0: Disable Write to CH7_SUSP bit 0x1: Enable Write to respective CH7_SUSP bit" "Disable Write to CH7_SUSP bit,Enable Write to respective CH7_SUSP bit" newline bitfld.long 0x0 29. "CH6_SUSP_WE,This bit is used as a write enable to the Channel-6 Suspend bit. The read back value of this register bit is always 0. 0x0: Disable Write to CH6_SUSP bit 0x1: Enable Write to respective CH6_SUSP bit" "Disable Write to CH6_SUSP bit,Enable Write to respective CH6_SUSP bit" newline bitfld.long 0x0 28. "CH5_SUSP_WE,This bit is used as a write enable to the Channel-5 Suspend bit. The read back value of this register bit is always 0. 0x0: Disable Write to CH5_SUSP bit 0x1: Enable Write to respective CH5_SUSP bit" "Disable Write to CH5_SUSP bit,Enable Write to respective CH5_SUSP bit" newline bitfld.long 0x0 27. "CH4_SUSP_WE,This bit is used as a write enable to the Channel-4 Suspend bit. The read back value of this register bit is always 0. 0x0: Disable Write to CH4_SUSP bit 0x1: Enable Write to respective CH4_SUSP bit" "Disable Write to CH4_SUSP bit,Enable Write to respective CH4_SUSP bit" newline bitfld.long 0x0 26. "CH3_SUSP_WE,This bit is used as a write enable to the Channel-3 Suspend bit. The read back value of this register bit is always 0. 0x0: Disable Write to CH3_SUSP bit 0x1: Enable Write to respective CH3_SUSP bit" "Disable Write to CH3_SUSP bit,Enable Write to respective CH3_SUSP bit" newline bitfld.long 0x0 25. "CH2_SUSP_WE,This bit is used as a write enable to the Channel-2 Suspend bit. The read back value of this register bit is always 0. 0x0: Disable Write to CH2_SUSP bit 0x1: Enable Write to respective CH2_SUSP bit" "Disable Write to CH2_SUSP bit,Enable Write to respective CH2_SUSP bit" newline bitfld.long 0x0 24. "CH1_SUSP_WE,This bit is used as a write enable to the Channel-1 Suspend bit. The read back value of this register bit is always 0. 0x0: Disable Write to CH1_SUSP bit 0x1: Enable Write to respective CH1_SUSP bit" "Disable Write to CH1_SUSP bit,Enable Write to respective CH1_SUSP bit" newline bitfld.long 0x0 23. "CH8_SUSP,Channel-8 Suspend Request. Software sets this bit to 1 to request channel suspend. If this bit is set to 1 DW_axi_dmac suspends all DMA data transfers from the source gracefully until this bit is cleared. There is no guarantee that the current.." "No Channel Suspend Request,Request to Suspended Channel-8" newline bitfld.long 0x0 22. "CH7_SUSP,Channel-7 Suspend Request. Software sets this bit to 1 to request channel suspend. If this bit is set to 1 DW_axi_dmac suspends all DMA data transfers from the source gracefully until this bit is cleared. There is no guarantee that the current.." "No Channel Suspend Request,Request to Suspended Channel-7" newline bitfld.long 0x0 21. "CH6_SUSP,Channel-6 Suspend Request. Software sets this bit to 1 to request channel suspend. If this bit is set to 1 DW_axi_dmac suspends all DMA data transfers from the source gracefully until this bit is cleared. There is no guarantee that the current.." "No Channel Suspend Request,Request to Suspended Channel-6" newline bitfld.long 0x0 20. "CH5_SUSP,Channel-5 Suspend Request. Software sets this bit to 1 to request channel suspend. If this bit is set to 1 DW_axi_dmac suspends all DMA data transfers from the source gracefully until this bit is cleared. There is no guarantee that the current.." "No Channel Suspend Request,Request to Suspended Channel-5" newline bitfld.long 0x0 19. "CH4_SUSP,Channel-4 Suspend Request. Software sets this bit to 1 to request channel suspend. If this bit is set to 1 DW_axi_dmac suspends all DMA data transfers from the source gracefully until this bit is cleared. There is no guarantee that the current.." "No Channel Suspend Request,Request to Suspended Channel-4" newline bitfld.long 0x0 18. "CH3_SUSP,Channel-3 Suspend Request. Software sets this bit to 1 to request channel suspend. If this bit is set to 1 DW_axi_dmac suspends all DMA data transfers from the source gracefully until this bit is cleared. There is no guarantee that the current.." "No Channel Suspend Request,Request to Suspended Channel-3" newline bitfld.long 0x0 17. "CH2_SUSP,Channel-2 Suspend Request. Software sets this bit to 1 to request channel suspend. If this bit is set to 1 DW_axi_dmac suspends all DMA data transfers from the source gracefully until this bit is cleared. There is no guarantee that the current.." "No Channel Suspend Request,Request to Suspended Channel-2" newline bitfld.long 0x0 16. "CH1_SUSP,Channel-1 Suspend Request. Software sets this bit to 1 to request channel suspend. If this bit is set to 1 DW_axi_dmac suspends all DMA data transfers from the source gracefully until this bit is cleared. There is no guarantee that the current.." "No Channel Suspend Request,Request to Suspended Channel-1" newline bitfld.long 0x0 15. "CH8_EN_WE,DW_axi_dmac Channel-8 Enable Write Enable bit. Read back value of this register bit is always '0'. 0x0: Disable Write to respective CH8_EN bit 0x1: Enable Write to CH8_EN bit" "Disable Write to respective CH8_EN bit,Enable Write to CH8_EN bit" newline bitfld.long 0x0 14. "CH7_EN_WE,DW_axi_dmac Channel-7 Enable Write Enable bit. Read back value of this register bit is always '0'. 0x0: Disable Write to respective CH7_EN bit 0x1: Enable Write to CH7_EN bit" "Disable Write to respective CH7_EN bit,Enable Write to CH7_EN bit" newline bitfld.long 0x0 13. "CH6_EN_WE,DW_axi_dmac Channel-6 Enable Write Enable bit. Read back value of this register bit is always '0'. 0x0: Disable Write to respective CH6_EN bit 0x1: Enable Write to CH6_EN bit" "Disable Write to respective CH6_EN bit,Enable Write to CH6_EN bit" newline bitfld.long 0x0 12. "CH5_EN_WE,DW_axi_dmac Channel-5 Enable Write Enable bit. Read back value of this register bit is always '0'. 0x0: Disable Write to respective CH5_EN bit 0x1: Enable Write to CH5_EN bit" "Disable Write to respective CH5_EN bit,Enable Write to CH5_EN bit" newline bitfld.long 0x0 11. "CH4_EN_WE,DW_axi_dmac Channel-4 Enable Write Enable bit. Read back value of this register bit is always '0'. 0x0: Disable Write to respective CH4_EN bit 0x1: Enable Write to CH4_EN bit" "Disable Write to respective CH4_EN bit,Enable Write to CH4_EN bit" newline bitfld.long 0x0 10. "CH3_EN_WE,DW_axi_dmac Channel-3 Enable Write Enable bit. Read back value of this register bit is always '0'. 0x0: Disable Write to respective CH3_EN bit 0x1: Enable Write to CH3_EN bit" "Disable Write to respective CH3_EN bit,Enable Write to CH3_EN bit" newline bitfld.long 0x0 9. "CH2_EN_WE,DW_axi_dmac Channel-2 Enable Write Enable bit. Read back value of this register bit is always '0'. 0x0: Disable Write to respective CH2_EN bit 0x1: Enable Write to CH2_EN bit" "Disable Write to respective CH2_EN bit,Enable Write to CH2_EN bit" newline bitfld.long 0x0 8. "CH1_EN_WE,DW_axi_dmac Channel-1 Enable Write Enable bit. Read back value of this register bit is always '0'. 0x0: Disable Write to respective CH1_EN bit 0x1: Enable Write to CH1_EN bit" "Disable Write to respective CH1_EN bit,Enable Write to CH1_EN bit" newline bitfld.long 0x0 7. "CH8_EN,This bit is used to enable the DW_axi_dmac Channel-8. - 0: DW_axi_dmac Channel-8 is disabled - 1: DW_axi_dmac Channel-8 is enabled The bit 'DMAC_ChEnReg.CH8_EN' is automatically cleared by hardware to disable the channel after the last AMBA.." "DW_axi_dmac: Channel-8 is disabled,DW_axi_dmac: Channel-8 is enabled" newline bitfld.long 0x0 6. "CH7_EN,This bit is used to enable the DW_axi_dmac Channel-7. - 0: DW_axi_dmac Channel-7 is disabled - 1: DW_axi_dmac Channel-7 is enabled The bit 'DMAC_ChEnReg.CH7_EN' is automatically cleared by hardware to disable the channel after the last AMBA.." "DW_axi_dmac: Channel-7 is disabled,DW_axi_dmac: Channel-7 is enabled" newline bitfld.long 0x0 5. "CH6_EN,This bit is used to enable the DW_axi_dmac Channel-6. - 0: DW_axi_dmac Channel-6 is disabled - 1: DW_axi_dmac Channel-6 is enabled The bit 'DMAC_ChEnReg.CH6_EN' is automatically cleared by hardware to disable the channel after the last AMBA.." "DW_axi_dmac: Channel-6 is disabled,DW_axi_dmac: Channel-6 is enabled" newline bitfld.long 0x0 4. "CH5_EN,This bit is used to enable the DW_axi_dmac Channel-5. - 0: DW_axi_dmac Channel-5 is disabled - 1: DW_axi_dmac Channel-5 is enabled The bit 'DMAC_ChEnReg.CH5_EN' is automatically cleared by hardware to disable the channel after the last AMBA.." "DW_axi_dmac: Channel-5 is disabled,DW_axi_dmac: Channel-5 is enabled" newline bitfld.long 0x0 3. "CH4_EN,This bit is used to enable the DW_axi_dmac Channel-4. - 0: DW_axi_dmac Channel-4 is disabled - 1: DW_axi_dmac Channel-4 is enabled The bit 'DMAC_ChEnReg.CH4_EN' is automatically cleared by hardware to disable the channel after the last AMBA.." "DW_axi_dmac: Channel-4 is disabled,DW_axi_dmac: Channel-4 is enabled" newline bitfld.long 0x0 2. "CH3_EN,This bit is used to enable the DW_axi_dmac Channel-3. - 0: DW_axi_dmac Channel-3 is disabled - 1: DW_axi_dmac Channel-3 is enabled The bit 'DMAC_ChEnReg.CH3_EN' is automatically cleared by hardware to disable the channel after the last AMBA.." "DW_axi_dmac: Channel-3 is disabled,DW_axi_dmac: Channel-3 is enabled" newline bitfld.long 0x0 1. "CH2_EN,This bit is used to enable the DW_axi_dmac Channel-2. - 0: DW_axi_dmac Channel-2 is disabled - 1: DW_axi_dmac Channel-2 is enabled The bit 'DMAC_ChEnReg.CH2_EN' is automatically cleared by hardware to disable the channel after the last AMBA.." "DW_axi_dmac: Channel-2 is disabled,DW_axi_dmac: Channel-2 is enabled" newline bitfld.long 0x0 0. "CH1_EN,This bit is used to enable the DW_axi_dmac Channel-1. - 0: DW_axi_dmac Channel-1 is disabled - 1: DW_axi_dmac Channel-1 is enabled The bit 'DMAC_ChEnReg.CH1_EN' is automatically cleared by hardware to disable the channel after the last AMBA.." "DW_axi_dmac: Channel-1 is disabled,DW_axi_dmac: Channel-1 is enabled" rgroup.long 0x1C++0x3 line.long 0x0 "DMAC_CHENREG_1,This is DW_axi_dmac Channel Enable Register. If software wants to set up a new channel. it can read this register to find out which channels are currently inactive and then enable an inactive channel with the required priority. All bits of.." hexmask.long.word 0x0 16.--31. 1. "RSVD_DMAC_CHENREG,DMAC_CHENREG Reserved bits - Read Only" newline bitfld.long 0x0 15. "CH8_ABORT_WE,This bit is used to write enable the Channel-8 Abort bit. The read back value of this register bit is always 0. 0x0: Disable Write to CH8_ABORT bit 0x1: Enable Write to CH8_ABORT bit" "Disable Write to CH8_ABORT bit,Enable Write to CH8_ABORT bit" newline bitfld.long 0x0 14. "CH7_ABORT_WE,This bit is used to write enable the Channel-7 Abort bit. The read back value of this register bit is always 0. 0x0: Disable Write to CH7_ABORT bit 0x1: Enable Write to CH7_ABORT bit" "Disable Write to CH7_ABORT bit,Enable Write to CH7_ABORT bit" newline bitfld.long 0x0 13. "CH6_ABORT_WE,This bit is used to write enable the Channel-6 Abort bit. The read back value of this register bit is always 0. 0x0: Disable Write to CH6_ABORT bit 0x1: Enable Write to CH6_ABORT bit" "Disable Write to CH6_ABORT bit,Enable Write to CH6_ABORT bit" newline bitfld.long 0x0 12. "CH5_ABORT_WE,This bit is used to write enable the Channel-5 Abort bit. The read back value of this register bit is always 0. 0x0: Disable Write to CH5_ABORT bit 0x1: Enable Write to CH5_ABORT bit" "Disable Write to CH5_ABORT bit,Enable Write to CH5_ABORT bit" newline bitfld.long 0x0 11. "CH4_ABORT_WE,This bit is used to write enable the Channel-4 Abort bit. The read back value of this register bit is always 0. 0x0: Disable Write to CH4_ABORT bit 0x1: Enable Write to CH4_ABORT bit" "Disable Write to CH4_ABORT bit,Enable Write to CH4_ABORT bit" newline bitfld.long 0x0 10. "CH3_ABORT_WE,This bit is used to write enable the Channel-3 Abort bit. The read back value of this register bit is always 0. 0x0: Disable Write to CH3_ABORT bit 0x1: Enable Write to CH3_ABORT bit" "Disable Write to CH3_ABORT bit,Enable Write to CH3_ABORT bit" newline bitfld.long 0x0 9. "CH2_ABORT_WE,This bit is used to write enable the Channel-2 Abort bit. The read back value of this register bit is always 0. 0x0: Disable Write to CH2_ABORT bit 0x1: Enable Write to CH2_ABORT bit" "Disable Write to CH2_ABORT bit,Enable Write to CH2_ABORT bit" newline bitfld.long 0x0 8. "CH1_ABORT_WE,This bit is used to write enable the Channel-1 Abort bit. The read back value of this register bit is always 0. 0x0: Disable Write to CH1_ABORT bit 0x1: Enable Write to CH1_ABORT bit" "Disable Write to CH1_ABORT bit,Enable Write to CH1_ABORT bit" newline bitfld.long 0x0 7. "CH8_ABORT,Channel-8 Abort Request. Software sets this bit to 1 to request channel abort. If this bit is set to 1 DW_axi_dmac disables the channel immediately. Aborting the channel might result in AXI Protocol violation as DW_axi_dmac does not make sure.." "No Request for Channel-8 Abort,Request for Channel-8 Abort" newline bitfld.long 0x0 6. "CH7_ABORT,Channel-7 Abort Request. Software sets this bit to 1 to request channel abort. If this bit is set to 1 DW_axi_dmac disables the channel immediately. Aborting the channel might result in AXI Protocol violation as DW_axi_dmac does not make sure.." "No Request for Channel-7 Abort,Request for Channel-7 Abort" newline bitfld.long 0x0 5. "CH6_ABORT,Channel-6 Abort Request. Software sets this bit to 1 to request channel abort. If this bit is set to 1 DW_axi_dmac disables the channel immediately. Aborting the channel might result in AXI Protocol violation as DW_axi_dmac does not make sure.." "No Request for Channel-6 Abort,Request for Channel-6 Abort" newline bitfld.long 0x0 4. "CH5_ABORT,Channel-5 Abort Request. Software sets this bit to 1 to request channel abort. If this bit is set to 1 DW_axi_dmac disables the channel immediately. Aborting the channel might result in AXI Protocol violation as DW_axi_dmac does not make sure.." "No Request for Channel-5 Abort,Request for Channel-5 Abort" newline bitfld.long 0x0 3. "CH4_ABORT,Channel-4 Abort Request. Software sets this bit to 1 to request channel abort. If this bit is set to 1 DW_axi_dmac disables the channel immediately. Aborting the channel might result in AXI Protocol violation as DW_axi_dmac does not make sure.." "No Request for Channel-4 Abort,Request for Channel-4 Abort" newline bitfld.long 0x0 2. "CH3_ABORT,Channel-3 Abort Request. Software sets this bit to 1 to request channel abort. If this bit is set to 1 DW_axi_dmac disables the channel immediately. Aborting the channel might result in AXI Protocol violation as DW_axi_dmac does not make sure.." "No Request for Channel-3 Abort,Request for Channel-3 Abort" newline bitfld.long 0x0 1. "CH2_ABORT,Channel-2 Abort Request. Software sets this bit to 1 to request channel abort. If this bit is set to 1 DW_axi_dmac disables the channel immediately. Aborting the channel might result in AXI Protocol violation as DW_axi_dmac does not make sure.." "No Request for Channel-2 Abort,Request for Channel-2 Abort" newline bitfld.long 0x0 0. "CH1_ABORT,Channel-1 Abort Request. Software sets this bit to 1 to request channel abort. If this bit is set to 1 DW_axi_dmac disables the channel immediately. Aborting the channel might result in AXI Protocol violation as DW_axi_dmac does not make sure.." "No Request for Channel-1 Abort,Request for Channel-1 Abort" rgroup.long 0x30++0x7 line.long 0x0 "DMAC_INTSTATUSREG_0,DMAC Interrupt Status Register captures the combined channel interrupt for each channel and Combined common register block interrupt. This register is present provided number of DMA channels are greater than 8." hexmask.long.word 0x0 17.--31. 1. "RSVD_DMAC_INTSTATUSREG_63TO17,DMAC Interrupt Status Register (bits 63to17) Reserved bits - Read Only" newline bitfld.long 0x0 16. "COMMONREG_INTSTAT,Common Register Interrupt Status Bit. 0x1: Common Register Interrupt is Active 0x0: Common Register Interrupt is Inactive" "Common Register Interrupt is Inactive,Common Register Interrupt is Active" newline hexmask.long.byte 0x0 8.--15. 1. "RSVD_DMAC_INTSTATUSREG,DMAC Interrupt Status Register (bits 15to8) Reserved bits - Read Only" newline bitfld.long 0x0 7. "CH8_INTSTAT,Channel 8 Interrupt Status Bit. 0x1: Channel 8 Interrupt is Active 0x0: Channel 8 Interrupt is Inactive" "Channel 8 Interrupt is Inactive,Channel 8 Interrupt is Active" newline bitfld.long 0x0 6. "CH7_INTSTAT,Channel 7 Interrupt Status Bit. 0x1: Channel 7 Interrupt is Active 0x0: Channel 7 Interrupt is Inactive" "Channel 7 Interrupt is Inactive,Channel 7 Interrupt is Active" newline bitfld.long 0x0 5. "CH6_INTSTAT,Channel 6 Interrupt Status Bit. 0x1: Channel 6 Interrupt is Active 0x0: Channel 6 Interrupt is Inactive" "Channel 6 Interrupt is Inactive,Channel 6 Interrupt is Active" newline bitfld.long 0x0 4. "CH5_INTSTAT,Channel 5 Interrupt Status Bit. 0x1: Channel 5 Interrupt is Active 0x0: Channel 5 Interrupt is Inactive" "Channel 5 Interrupt is Inactive,Channel 5 Interrupt is Active" newline bitfld.long 0x0 3. "CH4_INTSTAT,Channel 4 Interrupt Status Bit. 0x1: Channel 4 Interrupt is Active 0x0: Channel 4 Interrupt is Inactive" "Channel 4 Interrupt is Inactive,Channel 4 Interrupt is Active" newline bitfld.long 0x0 2. "CH3_INTSTAT,Channel 3 Interrupt Status Bit. 0x1: Channel 3 Interrupt is Active 0x0: Channel 3 Interrupt is Inactive" "Channel 3 Interrupt is Inactive,Channel 3 Interrupt is Active" newline bitfld.long 0x0 1. "CH2_INTSTAT,Channel 2 Interrupt Status Bit. 0x1: Channel 2 Interrupt is Active 0x0: Channel 2 Interrupt is Inactive" "Channel 2 Interrupt is Inactive,Channel 2 Interrupt is Active" newline bitfld.long 0x0 0. "CH1_INTSTAT,Channel 1 Interrupt Status Bit. 0x1: Channel 1 Interrupt is Active 0x0: Channel 1 Interrupt is Inactive" "Channel 1 Interrupt is Inactive,Channel 1 Interrupt is Active" line.long 0x4 "DMAC_INTSTATUSREG_1,DMAC Interrupt Status Register captures the combined channel interrupt for each channel and Combined common register block interrupt. This register is present provided number of DMA channels are greater than 8." hexmask.long 0x4 0.--31. 1. "RSVD_DMAC_INTSTATUSREG_63TO17,DMAC Interrupt Status Register (bits 63to17) Reserved bits - Read Only" wgroup.long 0x38++0x7 line.long 0x0 "DMAC_COMMONREG_INTCLEARREG_0,Writing 1 to specific field clears the corresponding field in DMAC Common register Interrupt Status Register (DMAC_CommonReg_IntStatusReg)." hexmask.long.tbyte 0x0 9.--31. 1. "RSVD_DMAC_COMMONREG_INTCLEARREG_63TO9,DMAC Common Register Interrupt Clear Register (bits 63to9) Reserved bits - Read Only" newline bitfld.long 0x0 8. "CLEAR_SLVIF_UNDEFINEDREG_DEC_ERR_INTSTAT,Slave Interface Undefined register Decode Error Interrupt clear Bit. This bit is used to clear the corresponding channel interrupt status bit(SLVIF_UndefinedReg_DEC_ERR_IntStat in DMAC_CommonReg_IntStatusReg. 0x1:.." "Inactive signal,Clear the SLVIF_UndefinedReg_DEC_ERR interrupt.." newline hexmask.long.byte 0x0 4.--7. 1. "RSVD_DMAC_COMMONREG_INTCLEARREG_7TO4,DMAC Common Register Interrupt Clear Register (bits 7to4) Reserved bits - Read Only" newline bitfld.long 0x0 3. "CLEAR_SLVIF_COMMONREG_WRONHOLD_ERR_INTSTAT,Slave Interface Common Register Write On Hold Error Interrupt clear Bit. This bit is used to clear the corresponding channel interrupt status bit(SLVIF_CommonReg_WrOnHold_ERR_IntStat in.." "Inactive signal,Clear the SLVIF_CommonReg_WrOnHold_ERR interrupt.." newline bitfld.long 0x0 2. "CLEAR_SLVIF_COMMONREG_RD2WO_ERR_INTSTAT,Slave Interface Common Register Read to Write only Error Interrupt clear Bit. This bit is used to clear the corresponding channel interrupt status bit(SLVIF_CommonReg_RD2WO_ERR_IntStat in.." "Inactive signal,Clear the SLVIF_CommonReg_RD2WO_ERR interrupt in.." newline bitfld.long 0x0 1. "CLEAR_SLVIF_COMMONREG_WR2RO_ERR_INTSTAT,Slave Interface Common Register Write to Read only Error Interrupt clear Bit. This bit is used to clear the corresponding channel interrupt status bit(SLVIF_CommonReg_WR2RO_ERR_IntStat in.." "Inactive signal,Clear the SLVIF_CommonReg_WR2RO_ERR interrupt in.." newline bitfld.long 0x0 0. "CLEAR_SLVIF_COMMONREG_DEC_ERR_INTSTAT,Slave Interface Common Register Decode Error Interrupt clear Bit. This bit is used to clear the corresponding channel interrupt status bit (SLVIF_CommonReg_DEC_ERR_IntStat in DMAC_CommonReg_IntStatusReg. 0x1: Clear.." "Inactive signal,Clear the SLVIF_CommonReg_DEC_ERR interrupt in.." line.long 0x4 "DMAC_COMMONREG_INTCLEARREG_1,Writing 1 to specific field clears the corresponding field in DMAC Common register Interrupt Status Register (DMAC_CommonReg_IntStatusReg)." hexmask.long 0x4 0.--31. 1. "RSVD_DMAC_COMMONREG_INTCLEARREG_63TO9,DMAC Common Register Interrupt Clear Register (bits 63to9) Reserved bits - Read Only" group.long 0x40++0x3 line.long 0x0 "DMAC_COMMONREG_INTSTATUS_ENABLEREG_0,Writing 1 to specific field enables the corresponding interrupt status generation in DMAC Common register Interrupt Status Register (DMAC_CommonReg_IntStatusReg)." hexmask.long.tbyte 0x0 9.--31. 1. "RSVD_DMAC_COMMONREG_INTSTATUS_ENABLEREG_63TO9,DMAC Common Register Interrupt Status Enable Register (bits 63to9) Reserved bits - Read Only" newline bitfld.long 0x0 8. "ENABLE_SLVIF_UNDEFINEDREG_DEC_ERR_INTSTAT,Slave Interface Undefined register Decode Error Interrupt Status enable Bit. This bit is used to enable the corresponding channel interrupt status bit (SLVIF_UndefinedReg_DEC_ERR_IntStat in.." "SLVIF_UndefinedReg_DEC_ERR_IntStat bit in..,SLVIF_UndefinedReg_DEC_ERR_IntStat bit in.." newline hexmask.long.byte 0x0 4.--7. 1. "RSVD_DMAC_COMMONREG_INTSTATUS_ENABLEREG_7TO4,DMAC Common Register Interrupt Status Enable Register (bits 7to4) Reserved bits - Read Only" newline bitfld.long 0x0 3. "ENABLE_SLVIF_COMMONREG_WRONHOLD_ERR_INTSTAT,Slave Interface Common Register Write On Hold Error Interrupt Status Enable Bit. This bit is used to enable the corresponding channel interrupt status bit (SLVIF_CommonReg_WrOnHold_ERR_IntStat in.." "SLVIF_CommonReg_WrOnHold_ERR_IntStat bit in..,SLVIF_CommonReg_WrOnHold_ERR_IntStat bit in.." newline bitfld.long 0x0 2. "ENABLE_SLVIF_COMMONREG_RD2WO_ERR_INTSTAT,Slave Interface Common Register Read to Write only Error Interrupt Status Enable Bit. This bit is used to enable the corresponding channel interrupt status bit (SLVIF_CommonReg_RD2WO_ERR_IntStat in.." "SLVIF_CommonReg_RD2WO_ERR_IntStat bit in..,SLVIF_CommonReg_RD2WO_ERR_IntStat bit in.." newline bitfld.long 0x0 1. "ENABLE_SLVIF_COMMONREG_WR2RO_ERR_INTSTAT,Slave Interface Common Register Write to Read only Error Interrupt Status Enable Bit. This bit is used to enable the corresponding channel interrupt status bit (SLVIF_CommonReg_WR2RO_ERR_IntStat in.." "SLVIF_CommonReg_WR2RO_ERR_IntStat bit in..,SLVIF_CommonReg_WR2RO_ERR_IntStat bit in.." newline bitfld.long 0x0 0. "ENABLE_SLVIF_COMMONREG_DEC_ERR_INTSTAT,Slave Interface Common Register Decode Error Interrupt Status Enable Bit. This bit is used to enable the corresponding channel interrupt status bit (SLVIF_CommonReg_DEC_ERR_IntStat in DMAC_CommonReg_IntStatusReg." "SLVIF_CommonReg_DEC_ERR_IntStat bit in..,SLVIF_CommonReg_DEC_ERR_IntStat bit in.." rgroup.long 0x44++0x3 line.long 0x0 "DMAC_COMMONREG_INTSTATUS_ENABLEREG_1,Writing 1 to specific field enables the corresponding interrupt status generation in DMAC Common register Interrupt Status Register (DMAC_CommonReg_IntStatusReg)." hexmask.long 0x0 0.--31. 1. "RSVD_DMAC_COMMONREG_INTSTATUS_ENABLEREG_63TO9,DMAC Common Register Interrupt Status Enable Register (bits 63to9) Reserved bits - Read Only" group.long 0x48++0x3 line.long 0x0 "DMAC_COMMONREG_INTSIGNAL_ENABLEREG_0,Writing 1 to specific field will propagate the corresponding interrupt status in DMAC Common register Interrupt Status Register (DMAC_CommonReg_IntStatusReg) to generate an port level interrupt." hexmask.long.tbyte 0x0 9.--31. 1. "RSVD_DMAC_COMMONREG_INTSIGNAL_ENABLEREG_63TO9,DMAC Common Register Interrupt Signal Enable Register (bits 63to9) Reserved bits - Read Only" newline bitfld.long 0x0 8. "ENABLE_SLVIF_UNDEFINEDREG_DEC_ERR_INTSIGNAL,Slave Interface Undefined register Decode Error Interrupt Signal Enable Bit. This bit is used to enable the propagation of corresponding channel interrupt status bit(SLVIF_UndefinedReg_DEC_ERR_IntStat in.." "SLVIF_UndefinedReg_DEC_ERR_IntStat signal in..,SLVIF_UndefinedReg_DEC_ERR_IntStat signal in.." newline hexmask.long.byte 0x0 4.--7. 1. "RSVD_DMAC_COMMONREG_INTSIGNAL_ENABLEREG_7TO4,DMAC Common Register Interrupt Signal Enable Register (bits 7to4) Reserved bits - Read Only" newline bitfld.long 0x0 3. "ENABLE_SLVIF_COMMONREG_WRONHOLD_ERR_INTSIGNAL,Slave Interface Common Register Write On Hold Error Interrupt Signal Enable Bit. This bit is used to enable the propagation of corresponding channel interrupt status bit(SLVIF_CommonReg_WrOnHold_ERR_IntStat.." "SLVIF_CommonReg_WrOnHold_ERR_IntStat signal in..,SLVIF_CommonReg_WrOnHold_ERR_IntStat signal in.." newline bitfld.long 0x0 2. "ENABLE_SLVIF_COMMONREG_RD2WO_ERR_INTSIGNAL,Slave Interface Common Register Read to Write only Error Interrupt Signal Enable Bit. This bit is used to enable the propagation of corresponding channel interrupt status bit (SLVIF_CommonReg_RD2WO_ERR_IntStat.." "SLVIF_CommonReg_RD2WO_ERR_IntStat signal in..,SLVIF_CommonReg_RD2WO_ERR_IntStat signal in.." newline bitfld.long 0x0 1. "ENABLE_SLVIF_COMMONREG_WR2RO_ERR_INTSIGNAL,Slave Interface Common Register Write to Read only Error Interrupt Signal Enable Bit. This bit is used to enable the propagation of corresponding channel interrupt status bit (SLVIF_CommonReg_WR2RO_ERR_IntStat.." "SLVIF_CommonReg_WR2RO_ERR_IntStat signal in..,SLVIF_CommonReg_WR2RO_ERR_IntStat signal in.." newline bitfld.long 0x0 0. "ENABLE_SLVIF_COMMONREG_DEC_ERR_INTSIGNAL,Slave Interface Common Register Decode Error Interrupt Signal Enable Bit. This bit is used to enable the propagation of corresponding channel interrupt status bit (SLVIF_CommonReg_DEC_ERR_IntStat in.." "SLVIF_CommonReg_DEC_ERR_IntStat signal in..,SLVIF_CommonReg_DEC_ERR_IntStat signal in.." rgroup.long 0x4C++0xB line.long 0x0 "DMAC_COMMONREG_INTSIGNAL_ENABLEREG_1,Writing 1 to specific field will propagate the corresponding interrupt status in DMAC Common register Interrupt Status Register (DMAC_CommonReg_IntStatusReg) to generate an port level interrupt." hexmask.long 0x0 0.--31. 1. "RSVD_DMAC_COMMONREG_INTSIGNAL_ENABLEREG_63TO9,DMAC Common Register Interrupt Signal Enable Register (bits 63to9) Reserved bits - Read Only" line.long 0x4 "DMAC_COMMONREG_INTSTATUSREG_0,This Register captures Slave interface access errors. - Decode Error. - Write to read only register. - Read to write only register. - write on hold. - undefined address." hexmask.long.tbyte 0x4 9.--31. 1. "RSVD_DMAC_COMMONREG_INTSTATUSREG_63TO9,DMAC Common Register Interrupt Signal Enable Register (bits 63to9) Reserved bits - Read Only" newline bitfld.long 0x4 8. "SLVIF_UNDEFINEDREG_DEC_ERR_INTSTAT,Slave Interface Undefined register Decode Error Interrupt Signal Enable Bit. Decode Error generated by DW_axi_dmac during register access. This error occurs if the register access is to undefined address range (>0x8FF.." "No Slave Interface Decode Errors,Slave Interface Decode Error detected" newline hexmask.long.byte 0x4 4.--7. 1. "RSVD_DMAC_COMMONREG_INTSTATUSREG_7TO4,DMAC Common Register Interrupt Status Register (bits 7to4) Reserved bits - Read Only" newline bitfld.long 0x4 3. "SLVIF_COMMONREG_WRONHOLD_ERR_INTSTAT,Slave Interface Common Register Write On Hold Error Interrupt Status Bit. This error occurs if an illegal write operation is performed on a common register; this happens if a write operation is performed on a common.." "No Slave Interface Common Register Write On Hold..,Slave Interface Common Register Write On Hold.." newline bitfld.long 0x4 2. "SLVIF_COMMONREG_RD2WO_ERR_INTSTAT,Slave Interface Common Register Read to Write only Error Interrupt Status bit. This error occurs if Read operation is performed to a Write Only register in the common register space (0x000 to 0x0FF). - 0: No Slave.." "No Slave Interface Read to Write Only Errors,Slave Interface Read to Write Only Error detected" newline bitfld.long 0x4 1. "SLVIF_COMMONREG_WR2RO_ERR_INTSTAT,Slave Interface Common Register Write to Read Only Error Interrupt Status bit. This error occurs if write operation is performed to a Read Only register in the common register space (0x000 to 0x0FF). - 0: No Slave.." "Slave Interface Write to Read Only Error detected,No Slave Interface Write to Read Only Errors" newline bitfld.long 0x4 0. "SLVIF_COMMONREG_DEC_ERR_INTSTAT,Slave Interface Common Register Decode Error Interrupt Status Bit. Decode Error generated by DW_axi_dmac during register access. This error occurs if the register access is to an invalid address in the common register.." "No Slave Interface Decode Errors,Slave Interface Decode Error detected" line.long 0x8 "DMAC_COMMONREG_INTSTATUSREG_1,This Register captures Slave interface access errors. - Decode Error. - Write to read only register. - Read to write only register. - write on hold. - undefined address." hexmask.long 0x8 0.--31. 1. "RSVD_DMAC_COMMONREG_INTSTATUSREG_63TO9,DMAC Common Register Interrupt Signal Enable Register (bits 63to9) Reserved bits - Read Only" group.long 0x58++0x3 line.long 0x0 "DMAC_RESETREG_0,This register is used to initiate the Software Reset to DW_axi_dmac." hexmask.long 0x0 1.--31. 1. "RSVD_DMAC_RESETREG_1TO63,DMAC_ResetReg (bits 1to63) Reserved bits - Read Only" newline bitfld.long 0x0 0. "DMAC_RST,DMAC Reset Request bit Software writes 1 to this bit to reset the DW_axi_dmac and polls this bit to see it as 0. DW_axi_dmac resets all the modules except the slave bus interface module and clears this bit to 0. NOTE: Software is not allowed to.." "0,1" rgroup.long 0x5C++0x3 line.long 0x0 "DMAC_RESETREG_1,This register is used to initiate the Software Reset to DW_axi_dmac." hexmask.long 0x0 0.--31. 1. "RSVD_DMAC_RESETREG_1TO63,DMAC_ResetReg (bits 1to63) Reserved bits - Read Only" group.long 0x60++0x7 line.long 0x0 "DMAC_LOWPOWER_CFGREG_0,This register contains the fields that configures the Context Sensitive Low Power feature. This register should be programmed prior to enabling the channel." hexmask.long 0x0 4.--31. 1. "RSVD_DMAC_LOWPOWER_CFGREG_31TO4,DMAC_LOWPOWER_CFGREG (bits 4to31) Reserved bits - Read Only" newline bitfld.long 0x0 3. "MXIF_CSLP_EN,AXI Master Interface Context Sensitive Low Power feature enable. 0x0: AXI Master Interface Context Sensitive Low Power feature is disabled 0x1: AXI Master Interface Context Sensitive Low Power feature is enabled" "AXI Master Interface Context Sensitive Low Power..,AXI Master Interface Context Sensitive Low Power.." newline bitfld.long 0x0 2. "SBIU_CSLP_EN,SBIU Context Sensitive Low Power feature enable. 0x0: SBIU Context Sensitive Low Power feature is disabled 0x1: SBIU Context Sensitive Low Power feature is enabled" "SBIU Context Sensitive Low Power feature is..,SBIU Context Sensitive Low Power feature is.." newline bitfld.long 0x0 1. "CHNL_CSLP_EN,DMA Channel Context Sensitive Low Power feature enable. 0x0: DMA Channel Context Sensitive Low Power feature is disabled 0x1: DMA Channel Context Sensitive Low Power feature is enabled" "DMA Channel Context Sensitive Low Power feature..,DMA Channel Context Sensitive Low Power feature.." newline bitfld.long 0x0 0. "GBL_CSLP_EN,Global Context Sensitive Low Power feature enable. 0x0: Global Context Sensitive Low Power feature is disabled 0x1: Global Context Sensitive Low Power feature is enabled" "Global Context Sensitive Low Power feature is..,Global Context Sensitive Low Power feature is.." line.long 0x4 "DMAC_LOWPOWER_CFGREG_1,This register contains the fields that configures the Context Sensitive Low Power feature. This register should be programmed prior to enabling the channel." hexmask.long.byte 0x4 24.--31. 1. "RSVD_DMAC_LOWPOWER_CFGREG_63TO56,DMAC_LOWPOWER_CFGREG (bits 56to63) Reserved bits - Read Only" newline hexmask.long.byte 0x4 16.--23. 1. "MXIF_LPDLY,Defines the load value to be programmed into the AXI Master Interface low power delay counter. The programmed value must be greater than or equal to 0x4. If value programmed is less than 0x4 then the register value is reset to.." newline hexmask.long.byte 0x4 8.--15. 1. "SBIU_LPDLY,Defines the load value to be programmed into the SBIU low power delay counter. The programmed value must be greater than or equal to 0x4. If value programmed is less than 0x4 then the register value is reset to DMAX_SBIU_LPDLY. The maximum.." newline hexmask.long.byte 0x4 0.--7. 1. "GLCH_LPDLY,Defines the load value to be programmed into the Global and DMA Channel low power delay counter. The programmed value must be greater than or equal to 0x4. If value programmed is less than 0x4 then the register value is reset to.." tree.end tree "CH$1" repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) group.long ($2)++0x3 line.long 0x0 "CH$1_SAR_$1,The starting source address is programmed by software before the DMA channel is enabled. or by an LLI update before the start of the DMA transfer. While the DMA transfer is in progress. this register is updated to reflect the source address.." hexmask.long 0x0 0.--31. 1. "SAR,Current Source Address of DMA transfer. Updated after each source transfer. The SINC fields in the CHx_CTL register determines whether the address increments or is left unchanged on every source transfer throughout the block transfer." repeat.end repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) group.long ($2+0x8)++0x3 line.long 0x0 "CH$1_DAR_$1,The starting destination address is programmed by the software before the DMA channel is enabled. or by an LLI update before the start of the DMA transfer. While the DMA transfer is in progress. this register is updated to reflect the.." hexmask.long 0x0 0.--31. 1. "DAR,Current Destination Address of DMA transfer. Updated after each destination transfer. The DINC fields in the CHx_CTL register determines whether the address increments or is left unchanged on every destination transfer throughout the block transfer." repeat.end group.long 0x10++0x3 line.long 0x0 "CH$1_BLOCK_TS_0,When DW_axi_dmac is the flow controller. the DMAC uses this register before the channel is enabled for block-size." hexmask.long.word 0x0 16.--31. 1. "RSVD_DMAC_CHX_BLOCK_TSREG_63TO16,DMAC Channelx Block Transfer Size Register (bits 63to16) Reserved bits - Read Only" newline hexmask.long.word 0x0 0.--15. 1. "BLOCK_TS,Block Transfer Size. The number programmed into BLOCK_TS field indicates the total number of data of width CHx_CTL.SRC_TR_WIDTH to be transferred in a DMA block transfer. Block Transfer Size = BLOCK_TS+1 When the transfer starts the read-back.." rgroup.long 0x14++0x3 line.long 0x0 "CH$1_BLOCK_TS_1,When DW_axi_dmac is the flow controller. the DMAC uses this register before the channel is enabled for block-size." hexmask.long 0x0 0.--31. 1. "RSVD_DMAC_CHX_BLOCK_TSREG_63TO16,DMAC Channelx Block Transfer Size Register (bits 63to16) Reserved bits - Read Only" group.long 0x18++0x17 line.long 0x0 "CH$1_CTL_0,This register contains fields that control the DMA transfer. This register should be programmed prior to enabling the channel except for LLI-based multi-block transfer. When LLI-based multi-block transfer is enabled. the CHx_CTL register is.." rbitfld.long 0x0 31. "RSVD_DMAC_CHX_CTL_31,DMAC Channelx Control Transfer Register bit31 Reserved bits - Read Only" "0,1" newline bitfld.long 0x0 30. "NONPOSTED_LASTWRITE_EN,Non Posted Last Write Enable This bit decides whether posted writes can be used throughout the block transfer. - 0: Posted writes may be used throughout the block transfer. - 1: Posted writes may be used till the end of the block.." "Posted writes may be used throughout the block..,Last write in the block must be non-posted" newline hexmask.long.byte 0x0 26.--29. 1. "AW_CACHE,AXI 'aw_cache' signal" newline hexmask.long.byte 0x0 22.--25. 1. "AR_CACHE,AXI 'ar_cache' signal" newline hexmask.long.byte 0x0 18.--21. 1. "DST_MSIZE,Destination Burst Transaction Length. Number of data items each of width CHx_CTL.DST_TR_WIDTH to be written to the destination every time a destination burst transaction request is made from the corresponding hardware or software handshaking.." newline hexmask.long.byte 0x0 14.--17. 1. "SRC_MSIZE,Source Burst Transaction Length. Number of data items each of width CHx_CTL.SRC_TR_WIDTH to be read from the source every time a source burst transaction request is made from the corresponding hardware or software handshaking interface. The.." newline rbitfld.long 0x0 11.--13. "DST_TR_WIDTH,Destination Transfer Width. Mapped to AXI bus awsize this value must be less than or equal to DMAX_M_DATA_WIDTH. 0x4: Destination Transfer Width is 128 bits 0x1: Destination Transfer Width is 16 bits 0x5: Destination Transfer Width is 256.." "Destination Transfer Width is 8 bits,Destination Transfer Width is 16 bits,Destination Transfer Width is 32 bits,Destination Transfer Width is 64 bits,Destination Transfer Width is 128 bits,Destination Transfer Width is 256 bits,Destination Transfer Width is 512 bits,?" newline rbitfld.long 0x0 8.--10. "SRC_TR_WIDTH,Source Transfer Width. Mapped to AXI bus arsize this value must be less than or equal to DMAX_M_DATA_WIDTH. 0x4: Source Transfer Width is 128 bits 0x1: Source Transfer Width is 16 bits 0x5: Source Transfer Width is 256 bits 0x2: Source.." "Source Transfer Width is 8 bits,Source Transfer Width is 16 bits,Source Transfer Width is 32 bits,Source Transfer Width is 64 bits,Source Transfer Width is 128 bits,Source Transfer Width is 256 bits,Source Transfer Width is 512 bits,?" newline rbitfld.long 0x0 7. "RSVD_DMAC_CHX_CTL_7,DMAC Channelx Control Transfer Register bit7 Reserved bits - Read Only" "0,1" newline bitfld.long 0x0 6. "DINC,Destination Address Increment. Indicates whether to increment the destination address on every destination transfer. If the device is writing data from a source peripheral FIFO with a fixed address then set this field to 'No change'. - 0: Increment.." "Destination address incremented on every source..,Destination address is fixed" newline rbitfld.long 0x0 5. "RSVD_DMAC_CHX_CTL_5,DMAC Channelx Control Transfer Register bit5 Reserved bits - Read Only" "0,1" newline bitfld.long 0x0 4. "SINC,Source Address Increment. Indicates whether to increment the source address on every source transfer. If the device is fetching data from a source peripheral FIFO with a fixed address then set this field to 'No change'. - 0: Increment - 1: No.." "Source address incremented on every source..,Source address is fixed" newline rbitfld.long 0x0 3. "RSVD_DMAC_CHX_CTL_3,DMAC Channelx Control Transfer Register bit3 Reserved bits - Read Only" "0,1" newline rbitfld.long 0x0 2. "DMS,Destination Master Select. Identifies the Master Interface layer from which the destination device (peripheral or memory) is accessed. - 0: AXI master 1 - 1: AXI Master 2 0x0: Destination device on Master-1 interface layer 0x1: Destination device on.." "Destination device on Master-1 interface layer,Destination device on Master-2 interface layer" newline rbitfld.long 0x0 1. "RSVD_DMAC_CHX_CTL_1,DMAC Channelx Control Transfer Register bit1 Reserved bits - Read Only" "0,1" newline rbitfld.long 0x0 0. "SMS,Source Master Select. Identifies the Master Interface layer from which the source device (peripheral or memory) is accessed. - 0: AXI master 1 - 1: AXI Master 2 0x0: Source device on Master-1 interface layer 0x1: Source device on Master-2 interface.." "Source device on Master-1 interface layer,Source device on Master-2 interface layer" line.long 0x4 "CH$1_CTL_1,This register contains fields that control the DMA transfer. This register should be programmed prior to enabling the channel except for LLI-based multi-block transfer. When LLI-based multi-block transfer is enabled. the CHx_CTL register is.." bitfld.long 0x4 31. "SHADOWREG_OR_LLI_VALID,Shadow Register content/Linked List Item valid. Indicates whether the content of shadow register or the linked list item fetched from the memory is valid. - 0: Shadow Register content/LLI is invalid. - 1: Last Shadow Register/LLI.." "Shadow Register content/LLI is invalid,Last Shadow Register/LLI is valid" newline bitfld.long 0x4 30. "SHADOWREG_OR_LLI_LAST,Last Shadow Register/Linked List Item. Indicates whether shadow register content or the linked list item fetched from the memory is the last one or not. - 0: Not last Shadow Register/LLI - 1: Last Shadow Register/LLI LLI based.." "Indicates shadowreg/LLI content is not the last..,Indicates shadowreg/LLI content is the last one" newline rbitfld.long 0x4 27.--29. "RSVD_DMAC_CHX_CTL_59TO61,DMAC Channelx Control Transfer Register (bits 59to61) Reserved bits - Read Only" "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 26. "IOC_BLKTFR,Interrupt On completion of Block Transfer This bit is used to control the block transfer completion interrupt generation on a block by block basis for shadow register or linked list based multi-block transfers. Writing 1 to this register field.." "Disables CHx_IntStatusReg,Enables CHx_IntStatusReg" newline rbitfld.long 0x4 25. "DST_STAT_EN,Destination Status Enable Enable the logic to fetch status from destination peripheral of channel x pointed to by the content of CHx_DSTATAR register and stores it in CHx_DSTAT register. This value is written back to the CHx_DSTAT location of.." "No status fetch for Destination device,Enables status fetch for Destination and store.." newline rbitfld.long 0x4 24. "SRC_STAT_EN,Source Status Enable Enable the logic to fetch status from source peripheral of channel x pointed to by the content of CHx_SSTATAR register and stores it in CHx_SSTAT register. This value is written back to the CHx_SSTAT location of linked.." "No status fetch for Source device,Enables status fetch for Source and store the.." newline hexmask.long.byte 0x4 16.--23. 1. "AWLEN,Destination Burst Length AXI Burst length used for destination data transfer. The specified burst length is used for destination data transfer till the extent possible; remaining transfers use maximum possible value that is less than or equal to.." newline bitfld.long 0x4 15. "AWLEN_EN,Destination Burst Length Enable If this bit is set to 1 DW_axi_dmac uses the value of CHx_CTL.AWLEN as AXI Burst length for destination data transfer till the extent possible; remaining transfers use maximum possible burst length. If this bit.." "AXI Burst Length is any possible value <=..,AXI Burst Length is CH$1_CTL" newline hexmask.long.byte 0x4 7.--14. 1. "ARLEN,Source Burst Length AXI Burst length used for source data transfer. The specified burst length is used for source data transfer till the extent possible; remaining transfers use maximum possible value that is less than or equal to.." newline bitfld.long 0x4 6. "ARLEN_EN,Source Burst Length Enable If this bit is set to 1 DW_axi_dmac uses the value of CHx_CTL.ARLEN as AXI Burst length for source data transfer till the extent possible; remaining transfers use maximum possible burst length. If this bit is set to 0.." "AXI Burst Length is any possible value <=..,AXI Burst Length is CH$1_CTL" newline bitfld.long 0x4 3.--5. "AW_PROT,AXI 'aw_prot' signal" "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 0.--2. "AR_PROT,AXI 'ar_prot' signal" "0,1,2,3,4,5,6,7" line.long 0x8 "CH$1_CFG_0,This register contains fields that configure the DMA transfer. This register should be programmed prior to enabling the channel. Bits [63:32] of the channel configuration register remains fixed for all blocks of a multi-block transfer and can.." hexmask.long 0x8 4.--31. 1. "RSVD_DMAC_CHX_CFG_4TO31,DMAC Channelx Transfer Configuration Register (bits 4to31) Reserved bits - Read Only" newline bitfld.long 0x8 2.--3. "DST_MULTBLK_TYPE,Destination Multi Block Transfer Type. These bits define the type of multi-block transfer used for destination peripheral. - 00: Contiguous - 01: Reload - 10: Shadow Register - 11: Linked List If the type selected is Contiguous the.." "Contiguous Multiblock Type used for Destination..,Reload Multiblock Type used for Destination..,Shadow Register based Multiblock Type used for..,Linked List based Multiblock Type used for.." newline bitfld.long 0x8 0.--1. "SRC_MULTBLK_TYPE,Source Multi Block Transfer Type. These bits define the type of multi-block transfer used for source peripheral. - 00: Contiguous - 01: Reload - 10: Shadow Register - 11: Linked List If the type selected is Contiguous the CHx_SAR.." "Contiguous Multiblock Type used for Source..,Reload Multiblock Type used for Source Transfer,Shadow Register based Multiblock Type used for..,Linked List based Multiblock Type used for.." line.long 0xC "CH$1_CFG_1,This register contains fields that configure the DMA transfer. This register should be programmed prior to enabling the channel. Bits [63:32] of the channel configuration register remains fixed for all blocks of a multi-block transfer and can.." rbitfld.long 0xC 31. "RSVD_DMAC_CHX_CFG_63,DMAC Channelx Transfer Configuration Register (63bit) Reserved bit - Read Only" "0,1" newline hexmask.long.byte 0xC 27.--30. 1. "DST_OSR_LMT,Destination Outstanding Request Limit - Maximum outstanding request supported is 16. - Source Outstanding Request Limit = DST_OSR_LMT + 1" newline hexmask.long.byte 0xC 23.--26. 1. "SRC_OSR_LMT,Source Outstanding Request Limit - Maximum outstanding request supported is 16. - Source Outstanding Request Limit = SRC_OSR_LMT + 1" newline rbitfld.long 0xC 21.--22. "LOCK_CH_L,Channel Lock Level This bit indicates the duration over which CHx_CFG.LOCK_CH bit applies. - 00: Over complete DMA transfer - 01: Over DMA block transfer - 1x: Reserved This field does not exist if the configuration parameter DMAX_CHx_LOCK_EN.." "Duration of the Channel locking is for the..,Duration of the Channel locking is for the..,?,?" newline rbitfld.long 0xC 20. "LOCK_CH,Channel Lock bit When the channel is granted control of the master bus interface and if the CHx_CFG.LOCK_CH bit is asserted then no other channels are granted control of the master bus interface for the duration specified in CHx_CFG.LOCK_CH_L." "Channel is not locked during the transfers,Channel is locked and granted exclusive access.." newline bitfld.long 0xC 17.--19. "CH_PRIOR,Channel Priority A priority of DMAX_NUM_CHANNELS-1 is the highest priority and 0 is the lowest. This field must be programmed within the following range: 0: DMAX_NUM_CHANNELS-1 A programmed value outside this range will cause erroneous behavior." "DMAX_NUM_CHANNELS-1,?,?,?,?,?,?,?" newline rbitfld.long 0xC 16. "RSVD_DMAC_CHX_CFG_48,DMAC Channelx Transfer Configuration Register (48bit) Reserved bit - Read Only" "0,1" newline hexmask.long.byte 0xC 12.--15. 1. "DST_PER,Assigns a hardware handshaking interface (0 - DMAX_NUM_HS_IF-1) to the destination of Channelx if the CHx_CFG.HS_SEL_DST field is 0; otherwise this field is ignored. The channel can then communicate with the destination peripheral connected to.." newline rbitfld.long 0xC 11. "RSVD_DMAC_CHX_CFG_43,DMAC Channelx Transfer Configuration Register (43bit) Reserved bit - Read Only" "0,1" newline hexmask.long.byte 0xC 7.--10. 1. "SRC_PER,Assigns a hardware handshaking interface (0 - DMAX_NUM_HS_IF-1) to the source of Channelx if the CHx_CFG.HS_SEL_SRC field is 0; otherwise this field is ignored. The channel can then communicate with the source peripheral connected to that.." newline rbitfld.long 0xC 6. "DST_HWHS_POL,Destination Hardware Handshaking Interface Polarity. - 0: ACTIVE HIGH - 1: ACTIVE LOW 0x0: Polarity of the Handshaking Interface used for the Destination peripheral is Active High 0x1: Polarity of the Handshaking Interface used for the.." "Polarity of the Handshaking Interface used for..,Polarity of the Handshaking Interface used for.." newline rbitfld.long 0xC 5. "SRC_HWHS_POL,Source Hardware Handshaking Interface Polarity. - 0: ACTIVE HIGH - 1: ACTIVE LOW 0x0: Polarity of the Handshaking Interface used for the Source peripheral is Active High 0x1: Polarity of the Handshaking Interface used for the Source.." "Polarity of the Handshaking Interface used for..,Polarity of the Handshaking Interface used for.." newline bitfld.long 0xC 4. "HS_SEL_DST,Destination Software or Hardware Handshaking Select. This register selects which of the handshaking interfaces (hardware or software) is active for destination requests on this channel. - 0: Hardware handshaking interface. Software-initiated.." "Hardware Handshaking Interface is used for the..,Software Handshaking Interface is used for the.." newline bitfld.long 0xC 3. "HS_SEL_SRC,Source Software or Hardware Handshaking Select. This register selects which of the handshaking interfaces (hardware or software) is active for source requests on this channel. - 0: Hardware handshaking interface. Software-initiated transaction.." "Hardware Handshaking Interface is used for the..,Software Handshaking Interface is used for the.." newline bitfld.long 0xC 0.--2. "TT_FC,Transfer Type and Flow Control. The following transfer types are supported. - Memory to Memory - Memory to Peripheral - Peripheral to Memory - Peripheral to Peripheral Flow Control can be assigned to the DW_axi_dmac the source peripheral or hte.." "Transfer Type is memory to memory and Flow..,Transfer Type is memory to peripheral and Flow..,Transfer Type is peripheral to memory and Flow..,Transfer Type is peripheral to peripheral and..,?,?,?,Reserved" line.long 0x10 "CH$1_LLP_0,This is the Linked List Pointer register. This register must be programmed to point to the first Linked List Item (LLI) in memory prior to enabling the channel if linked-list-based block chaining is enabled. This register is updated with new.." hexmask.long 0x10 6.--31. 1. "LOC,Starting Address Memory of LLI block Starting Address In Memory of next LLI if block chaining is enabled. The six LSBs of the starting address are not stored because the address is assumed to be aligned to a 64-byte boundary. LLI access always uses.." newline hexmask.long.byte 0x10 1.--5. 1. "RSVD_DMAC_CHX_LLP_1TO5,DMAC Channelx Linked List Pointer Register (bits 1to5) Reserved bits - Read Only" newline rbitfld.long 0x10 0. "LMS,LLI master Select This bit identifies the AXI layer/interface where the memory device that stores the next linked list item resides. - 0: AXI Master 1 - 1: AXI Master 2 This field does not exist if the configuration parameter DMAX_CHx_LMS is not set.." "next Linked List item resides on AXI Master1..,next Linked List item resides on AXI Master2.." line.long 0x14 "CH$1_LLP_1,This is the Linked List Pointer register. This register must be programmed to point to the first Linked List Item (LLI) in memory prior to enabling the channel if linked-list-based block chaining is enabled. This register is updated with new.." hexmask.long 0x14 0.--31. 1. "LOC,Starting Address Memory of LLI block Starting Address In Memory of next LLI if block chaining is enabled. The six LSBs of the starting address are not stored because the address is assumed to be aligned to a 64-byte boundary. LLI access always uses.." rgroup.long 0x30++0x7 line.long 0x0 "CH$1_STATUSREG_0,Channelx Status Register contains fields that indicate the status of DMA transfers for Channelx." hexmask.long.word 0x0 22.--31. 1. "RSVD_DMAC_CHX_STATUSREG_22TO31,DMAC Channelx Status Register (bits 22to31) Reserved bits - Read Only" newline hexmask.long.tbyte 0x0 0.--21. 1. "CMPLTD_BLK_TFR_SIZE,Completed Block Transfer Size. This bit indicates the total number of data of width CHx_CTL.SRC_TR_WIDTH transferred for the previous block transfer. For normal block transfer completion without any errors this value will be equal to.." line.long 0x4 "CH$1_STATUSREG_1,Channelx Status Register contains fields that indicate the status of DMA transfers for Channelx." hexmask.long.tbyte 0x4 15.--31. 1. "RSVD_DMAC_CHX_STATUSREG_47TO63,DMAC Channelx Status Register (bits 47to63) Reserved bits - Read Only" newline hexmask.long.word 0x4 0.--14. 1. "DATA_LEFT_IN_FIFO,Data Left in FIFO. This bit indicates the total number of data left in DW_axi_dmac channel FIFO after completing the current block transfer. The width of the data in channel FIFO is equal to CHx_CTL.SRC_TR_WIDTH. For normal block.." group.long 0x38++0x3 line.long 0x0 "CH$1_SWHSSRCREG_0,Channelx Software handshake Source Register." hexmask.long 0x0 6.--31. 1. "RSVD_DMAC_CHX_SWHSSRCREG_6TO63,DMAC Channelx Software Handshake Source Register (bits 6to63) Reserved bits - Read Only" newline bitfld.long 0x0 5. "SWHS_LST_SRC_WE,Write Enable bit for Software Handshake Last Request for Channel Source. 0x0: Disables write to the SWHS_LAST_SRC bit 0x1: Enables write to the SWHS_LAST_SRC bit" "Disables write to the SWHS_LAST_SRC bit,Enables write to the SWHS_LAST_SRC bit" newline bitfld.long 0x0 4. "SWHS_LST_SRC,Software Handshake Last Request for Channel Source. This bit is used to request LAST dma source data transfer if software handshaking method is selected for the source of the corresponding channel. This bit is ignored if software handshaking.." "Source peripheral indication that the curent..,Source peripheral indication to dmac that the.." newline bitfld.long 0x0 3. "SWHS_SGLREQ_SRC_WE,Write Enable bit for Software Handshake Single Request for Channel Source. 0x0: Disables write to the SWHS_SGLREQ_SRC bit 0x1: Enables write to the SWHS_SGLREQ_SRC bit" "Disables write to the SWHS_SGLREQ_SRC bit,Enables write to the SWHS_SGLREQ_SRC bit" newline bitfld.long 0x0 2. "SWHS_SGLREQ_SRC,Software Handshake Single Request for Channel Source. This bit is used to request SINGLE (AXI burst length = 1) dma source data transfer if software handshaking method is selected for the source of the corresponding channel. This bit is.." "Source peripheral is not requesting for a single..,Source peripheral request for a single dma.." newline bitfld.long 0x0 1. "SWHS_REQ_SRC_WE,Write Enable bit for Software Handshake Request for Channel Source. Note: This bit always returns 0 on a read back. 0x0: Disables write to the SWHS_REQ_SRC bit 0x1: Enables write to the SWHS_REQ_SRC bit" "Disables write to the SWHS_REQ_SRC bit,Enables write to the SWHS_REQ_SRC bit" newline bitfld.long 0x0 0. "SWHS_REQ_SRC,Software Handshake Request for Channel Source. This bit is used to request dma source data transfer if software handshaking method is selected for the source of the corresponding channel. This bit is ignored if software handshaking is not.." "Source peripheral is not requesting for a burst..,Source peripheral request for a dma transfer" rgroup.long 0x3C++0x3 line.long 0x0 "CH$1_SWHSSRCREG_1,Channelx Software handshake Source Register." hexmask.long 0x0 0.--31. 1. "RSVD_DMAC_CHX_SWHSSRCREG_6TO63,DMAC Channelx Software Handshake Source Register (bits 6to63) Reserved bits - Read Only" group.long 0x40++0x3 line.long 0x0 "CH$1_SWHSDSTREG_0,Channelx Software handshake Destination Register." hexmask.long 0x0 6.--31. 1. "RSVD_DMAC_CHX_SWHSDSTREG_6TO63,DMAC Channelx Software Handshake Destination Register (bits 6to63) Reserved bits - Read Only" newline bitfld.long 0x0 5. "SWHS_LST_DST_WE,Write Enable bit for Software Handshake Last Request for Channel Destination. Note: This bit always returns 0 on a read back. 0x0: Disables write to the SWHS_LAST_DST bit 0x1: Enables write to the SWHS_LAST_DST bit" "Disables write to the SWHS_LAST_DST bit,Enables write to the SWHS_LAST_DST bit" newline bitfld.long 0x0 4. "SWHS_LST_DST,Software Handshake Last Request for Channel Destination. This bit is used to request LAST dma destination data transfer if software handshaking method is selected for the destination of the corresponding channel. This bit is ignored if.." "Destination peripheral indication that the..,Destination peripheral indication to dmac that.." newline bitfld.long 0x0 3. "SWHS_SGLREQ_DST_WE,Write Enable bit for Software Handshake Single Request for Channel Destination. Note: This bit always returns 0 on a read block. 0x0: Disables write to the SWHS_SGLREQ_DST bit 0x1: Enables write to the SWHS_SGLREQ_DST bit" "Disables write to the SWHS_SGLREQ_DST bit,Enables write to the SWHS_SGLREQ_DST bit" newline bitfld.long 0x0 2. "SWHS_SGLREQ_DST,Software Handshake Single Request for Channel Destination. This bit is used to request SINGLE (AXI burst length = 1) dma destination data transfer if software handshaking method is selected for the destination of the corresponding.." "Destination peripheral is not requesting for a..,Destination peripheral request for a single dma.." newline bitfld.long 0x0 1. "SWHS_REQ_DST_WE,Write Enable bit for Software Handshake Request for Channel Destination. Note: This bit always returns 0 on a read block. 0x0: Disables write to the SWHS_REQ_DST bit 0x1: Enables write to the SWHS_REQ_DST bit" "Disables write to the SWHS_REQ_DST bit,Enables write to the SWHS_REQ_DST bit" newline bitfld.long 0x0 0. "SWHS_REQ_DST,Software Handshake Request for Channel Destination. This bit is used to request dma destination data transfer if software handshaking method is selected for the destination of the corresponding channel. This bit is ignored if software.." "Destination peripheral is not requesting for a..,Destination peripheral request for a dma transfer" rgroup.long 0x44++0x3 line.long 0x0 "CH$1_SWHSDSTREG_1,Channelx Software handshake Destination Register." hexmask.long 0x0 0.--31. 1. "RSVD_DMAC_CHX_SWHSDSTREG_6TO63,DMAC Channelx Software Handshake Destination Register (bits 6to63) Reserved bits - Read Only" wgroup.long 0x48++0x7 line.long 0x0 "CH$1_BLK_TFR_RESUMEREQREG_0,Channelx Block Transfer Resume Request Register. This register is used during Linked List or Shadow Register based multi-block transfer. - For Linked-List-based multi-block transfer. ShadowReg_Or_LLI_Valid bit in LLI.CHx_CTL.." hexmask.long 0x0 1.--31. 1. "RSVD_DMAC_CHX_BLK_TFR_RESUMEREQREG_1TO63,DMAC Channelx Block Transfer Resume Request Register (bits 1to63) Reserved bits - Read Only" newline bitfld.long 0x0 0. "BLK_TFR_RESUMEREQ,Block Transfer Resume Request during Linked-List or Shadow-Register-based multi-block transfer. 0x1: Request for resuming the block transfer 0x0: No request to resume the block transfer" "No request to resume the block transfer,Request for resuming the block transfer" line.long 0x4 "CH$1_BLK_TFR_RESUMEREQREG_1,Channelx Block Transfer Resume Request Register. This register is used during Linked List or Shadow Register based multi-block transfer. - For Linked-List-based multi-block transfer. ShadowReg_Or_LLI_Valid bit in LLI.CHx_CTL.." hexmask.long 0x4 0.--31. 1. "RSVD_DMAC_CHX_BLK_TFR_RESUMEREQREG_1TO63,DMAC Channelx Block Transfer Resume Request Register (bits 1to63) Reserved bits - Read Only" group.long 0x50++0x3 line.long 0x0 "CH$1_AXI_IDREG_0,Channelx AXI ID Register. This register is allowed to be updated only when the channel is disabled. which means that it remains fixed for the entire DMA transfer. Note: The presence of this register is determined by the DMAC_M_ID_WIDTH.." hexmask.long.word 0x0 18.--31. 1. "RSVD_DMAC_CHX_AXI_IDREG_IDW_L2NCM32TO63,DMAC Channelx AXI ID Register (bits (IDW-L2NC-1)to32) Reserved bits - Read Only" newline bitfld.long 0x0 16.--17. "AXI_WRITE_ID_SUFFIX,AXI Write ID Suffix. These bits form part of the AWID output of AXI3/AXI4 master interface. IDW = DMAX_M_ID_WIDTH L2NC = log2(DMAX_NUM_CHANNELS) The upper L2NC+1 bits of awidN is derived from the channel number which is currently.." "0,1,2,3" newline hexmask.long.word 0x0 2.--15. 1. "RSVD_DMAC_CHX_AXI_IDREG_IDW_L2NCM1TO31,DMAC Channelx AXI ID Register (bits (IDW-L2NC-1)to31) Reserved bits - Read Only" newline bitfld.long 0x0 0.--1. "AXI_READ_ID_SUFFIX,AXI Read ID Suffix These bits form part of the ARID output of AXI3/AXI4 master interface. IDW = DMAX_M_ID_WIDTH L2NC = log2(DMAX_NUM_CHANNELS) The upper L2NC+1 bits of aridN is derived from the channel number which is currently.." "0,1,2,3" rgroup.long 0x54++0x3 line.long 0x0 "CH$1_AXI_IDREG_1,Channelx AXI ID Register. This register is allowed to be updated only when the channel is disabled. which means that it remains fixed for the entire DMA transfer. Note: The presence of this register is determined by the DMAC_M_ID_WIDTH.." hexmask.long 0x0 0.--31. 1. "RSVD_DMAC_CHX_AXI_IDREG_32TO63,DMAC Channelx AXI ID Register (bits 32to63) Reserved bits - Read Only" group.long 0x58++0x3 line.long 0x0 "CH$1_AXI_QOSREG_0,Channelx AXI QOS Register. This register is allowed to be updated only when the channel is disabled. which means that it remains fixed for the entire DMA transfer." hexmask.long.tbyte 0x0 8.--31. 1. "RSVD_DMAC_CHX_AXI_QOSREG_8TO63,DMAC Channelx AXI QOS Register (bits 8to63) Reserved bits - Read Only" newline hexmask.long.byte 0x0 4.--7. 1. "AXI_ARQOS,AXI ARQOS. These bits form the arqos output of AXI4 master interface." newline hexmask.long.byte 0x0 0.--3. 1. "AXI_AWQOS,AXI AWQOS. These bits form the awqos output of AXI4 master interface." rgroup.long 0x5C++0x3 line.long 0x0 "CH$1_AXI_QOSREG_1,Channelx AXI QOS Register. This register is allowed to be updated only when the channel is disabled. which means that it remains fixed for the entire DMA transfer." hexmask.long 0x0 0.--31. 1. "RSVD_DMAC_CHX_AXI_QOSREG_8TO63,DMAC Channelx AXI QOS Register (bits 8to63) Reserved bits - Read Only" group.long 0x80++0x3 line.long 0x0 "CH$1_INTSTATUS_ENABLEREG_0,Writing 1 to specific field enables the corresponding interrupt status generation in Channelx Interrupt Status Register(CH$1_IntStatusReg)." bitfld.long 0x0 31. "ENABLE_CH_ABORTED_INTSTAT,Channel Aborted Status Enable. - 0: Disable the generation of Channel Aborted Interrupt in CHx_INTSTATUSREG - 1: Enable the generation of Channel Aborted Interrupt in CHx_INTSTATUSREG 0x0: Disable the generation of Channel.." "Disable the generation of Channel Aborted..,Enable the generation of Channel Aborted.." newline bitfld.long 0x0 30. "ENABLE_CH_DISABLED_INTSTAT,Channel Disabled Status Enable. - 0: Disable the generation of Channel Disabled Interrupt in CHx_INTSTATUSREG - 1: Enable the generation of Channel Disabled Interrupt in CHx_INTSTATUSREG 0x0: Disable the generation of Channel.." "Disable the generation of Channel Disabled..,Enable the generation of Channel Disabled.." newline bitfld.long 0x0 29. "ENABLE_CH_SUSPENDED_INTSTAT,Channel Suspended Status Enable. - 0: Disable the generation of Channel Suspended Interrupt in CHx_INTSTATUSREG - 1: Enable the generation of Channel Suspended Interrupt in CHx_INTSTATUSREG 0x0: Disable the generation of.." "Disable the generation of Channel Suspended..,Enable the generation of Channel Suspended.." newline bitfld.long 0x0 28. "ENABLE_CH_SRC_SUSPENDED_INTSTAT,Channel Source Suspended Status Enable. - 0: Disable the generation of Channel Source Suspended Interrupt in CHx_INTSTATUSREG - 1: Enable the generation of Channel Source Suspended Interrupt in CHx_INTSTATUSREG 0x0:.." "Disable the generation of Channel Source..,Enable the generation of Channel Source.." newline bitfld.long 0x0 27. "ENABLE_CH_LOCK_CLEARED_INTSTAT,Channel Lock Cleared Status Enable. - 0: Disable the generation of Channel LOCK CLEARED Interrupt in CHx_INTSTATUSREG - 1: Enable the generation of Channel LOCK CLEARED Interrupt in CHx_INTSTATUSREG 0x0: Disable the.." "Disable the generation of Channel LOCK CLEARED..,Enable the generation of Channel LOCK CLEARED.." newline hexmask.long.byte 0x0 22.--26. 1. "RSVD_DMAC_CHX_INTSTATUS_ENABLEREG_22TO26,DMAC Channelx Interrupt Status Register (bits 22to26) Reserved bits - Read Only" newline bitfld.long 0x0 21. "ENABLE_SLVIF_WRONHOLD_ERR_INTSTAT,Slave Interface Write On Hold Error Status Enable. - 0: Disable the generation of Slave Interface Write On Hold Error Interrupt in CHx_INTSTATUSREG - 1: Enable the generation of Slave Interface Write On Hold Error.." "Disable the generation of Slave Interface Write..,Enable the generation of Slave Interface Write.." newline bitfld.long 0x0 20. "ENABLE_SLVIF_SHADOWREG_WRON_VALID_ERR_INTSTAT,Shadow Register Write On Valid Error Status Enable. - 0: Disable the generation of Shadow Register Write On Valid Error Interrupt in CHx_INTSTATUSREG - 1: Enable the generation of Shadow register Write On.." "Disable the generation of Shadow Register Write..,Enable the generation of Shadow register Write.." newline bitfld.long 0x0 19. "ENABLE_SLVIF_WRONCHEN_ERR_INTSTAT,Slave Interface Write On Channel Enabled Error Status Enable. - 0: Disable the generation of Slave Interface Write On Channel enabled Error Interrupt in CHx_INTSTATUSREG - 1: Enable the generation of Slave Interface.." "Disable the generation of Slave Interface Write..,Enable the generation of Slave Interface Write.." newline bitfld.long 0x0 18. "ENABLE_SLVIF_RD2RWO_ERR_INTSTAT,Slave Interface Read to write Only Error Status Enable. - 0: Disable the generation of Slave Interface Read to Write only Error Interrupt in CHx_INTSTATUSREG - 1: Enable the generation of Slave Interface Read to Write Only.." "Disable the generation of Slave Interface Read..,Enable the generation of Slave Interface Read to.." newline bitfld.long 0x0 17. "ENABLE_SLVIF_WR2RO_ERR_INTSTAT,Slave Interface Write to Read Only Error Status Enable. - 0: Disable the generation of Slave Interface Write to Read only Error Interrupt in CHx_INTSTATUSREG - 1: Enable the generation of Slave Interface Write to Read Only.." "Disable the generation of Slave Interface Write..,Enable the generation of Slave Interface Write.." newline bitfld.long 0x0 16. "ENABLE_SLVIF_DEC_ERR_INTSTAT,Slave Interface Decode Error Status Enable. - 0: Disable the generation of Slave Interface Decode Error Interrupt in CHx_INTSTATUSREG - 1: Enable the generation of Slave Interface Decode Error Interrupt in CHx_INTSTATUSREG.." "Disable the generation of Slave Interface Decode..,Enable the generation of Slave Interface Decode.." newline rbitfld.long 0x0 15. "RSVD_DMAC_CHX_INTSTATUS_ENABLEREG_15,DMAC Channelx Interrupt Status Register (bit 15) Reserved bit - Read Only" "0,1" newline bitfld.long 0x0 14. "ENABLE_SLVIF_MULTIBLKTYPE_ERR_INTSTAT,Slave Interface Multi Block type Error Status Enable. - 0: Disable the generation of Slave Interface Multi Block type Error Interrupt in CHx_INTSTATUSREG - 1: Enable the generation of Slave Interface Multi Block type.." "Disable the generation of Slave Interface Multi..,Enable the generation of Slave Interface Multi.." newline bitfld.long 0x0 13. "ENABLE_SHADOWREG_OR_LLI_INVALID_ERR_INTSTAT,Shadow register or LLI Invalid Error Status Enable. - 0: Disable the generation of Shadow Register or LLI Invalid Error Interrupt in CHx_INTSTATUSREG - 1: Enable the generation of Shadow Register or LLI Invalid.." "Disable the generation of Shadow Register or LLI..,Enable the generation of Shadow Register or LLI.." newline bitfld.long 0x0 12. "ENABLE_LLI_WR_SLV_ERR_INTSTAT,LLI WRITE Slave Error Status Enable. - 0: Disable the generation of LLI WRITE Slave Error Interrupt in CHx_INTSTATUSREG - 1: Enable the generation of LLI WRITE Slave Error Interrupt in CHx_INTSTATUSREG 0x0: Disable the.." "Disable the generation of LLI WRITE Slave Error..,Enable the generation of LLI WRITE Slave Error.." newline bitfld.long 0x0 11. "ENABLE_LLI_RD_SLV_ERR_INTSTAT,LLI Read Slave Error Status Enable. - 0: Disable the generation of LLI Read Slave Error Interrupt in CHx_INTSTATUSREG - 1: Enable the generation of LLI Read Slave Error Interrupt in CHx_INTSTATUSREG 0x0: Disable the.." "Disable the generation of LLI Read Slave Error..,Enable the generation of LLI Read Slave Error.." newline bitfld.long 0x0 10. "ENABLE_LLI_WR_DEC_ERR_INTSTAT,LLI WRITE Decode Error Status Enable. - 0: Disable the generation of LLI WRITE Decode Error Interrupt in CHx_INTSTATUSREG - 1: Enable the generation of LLI WRITE Decode Error Interrupt in CHx_INTSTATUSREG 0x0: Disable the.." "Disable the generation of LLI WRITE Decode Error..,Enable the generation of LLI WRITE Decode Error.." newline bitfld.long 0x0 9. "ENABLE_LLI_RD_DEC_ERR_INTSTAT,LLI Read Decode Error Status Enable. - 0: Disable the generation of LLI Read Decode Error Interrupt in CHx_INTSTATUSREG - 1: Enable the generation of LLI Read Decode Error Interrupt in CHx_INTSTATUSREG 0x0: Disable the.." "Disable the generation of LLI Read Decode Error..,Enable the generation of LLI Read Decode Error.." newline bitfld.long 0x0 8. "ENABLE_DST_SLV_ERR_INTSTAT,Destination Slave Error Status Enable. - 0: Disable the generation of Destination Slave Error Interrupt in CHx_INTSTATUSREG - 1: Enable the generation of Destination Slave Error Interrupt in CHx_INTSTATUSREG 0x0: Disable the.." "Disable the generation of Destination Slave..,Enable the generation of Destination Slave Error.." newline bitfld.long 0x0 7. "ENABLE_SRC_SLV_ERR_INTSTAT,Source Slave Error Status Enable. - 0: Disable the generation of Source Slave Error Interrupt in CHx_INTSTATUSREG - 1: Enable the generation of Source Slave Error Interrupt in CHx_INTSTATUSREG 0x0: Disable the generation of.." "Disable the generation of Source Slave Error..,Enable the generation of Source Slave Error.." newline bitfld.long 0x0 6. "ENABLE_DST_DEC_ERR_INTSTAT,Destination Decode Error Status Enable. - 0: Disable the generation of Destination Decode Error Interrupt in CHx_INTSTATUSREG - 1: Enable the generation of Destination Decode Error Interrupt in CHx_INTSTATUSREG 0x0: Disable the.." "Disable the generation of Destination Decode..,Enable the generation of Destination Decode.." newline bitfld.long 0x0 5. "ENABLE_SRC_DEC_ERR_INTSTAT,Source Decode Error Status Enable. - 0: Disable the generation of Source Decode Error Interrupt in CHx_INTSTATUSREG - 1: Enable the generation of Source Decode Error Interrupt in CHx_INTSTATUSREG 0x0: Disable the generation of.." "Disable the generation of Source Decode Error..,Enable the generation of Source Decode Error.." newline bitfld.long 0x0 4. "ENABLE_DST_TRANSCOMP_INTSTAT,Destination Transaction Completed Status Enable. - 0: Disable the generation of Destination Transaction complete Interrupt in CHx_INTSTATUSREG - 1: Enable the generation of Destination Transaction complete Interrupt in.." "Disable the generation of Destination..,Enable the generation of Destination Transaction.." newline bitfld.long 0x0 3. "ENABLE_SRC_TRANSCOMP_INTSTAT,Source Transaction Completed Status Enable. - 0: Disable the generation of Source Transaction Complete Interrupt in CHx_INTSTATUSREG - 1: Enable the generation of Source Transaction Complete Interrupt in CHx_INTSTATUSREG 0x0:.." "Disable the generation of Source Transaction..,Enable the generation of Source Transaction.." newline rbitfld.long 0x0 2. "RSVD_DMAC_CHX_INTSTATUS_ENABLEREG_2,DMAC Channelx Interrupt Status Register (bit 2) Reserved bit - Read Only" "0,1" newline bitfld.long 0x0 1. "ENABLE_DMA_TFR_DONE_INTSTAT,DMA Transfer Done Interrupt Status Enable. - 0: Disable the generation of DMA Transfer Done Interrupt in CHx_INTSTATUSREG - 1: Enable the generation of DMA Transfer Done Interrupt in CHx_INTSTATUSREG 0x0: Disable the.." "Disable the generation of DMA Transfer Done..,Enable the generation of DMA Transfer Done.." newline bitfld.long 0x0 0. "ENABLE_BLOCK_TFR_DONE_INTSTAT,Block Transfer Done Interrupt Status Enable. - 0: Disable the generation of Block Transfer Done Interrupt in CHx_INTSTATUSREG - 1: Enable the generation of Block Transfer Done Interrupt in CHx_INTSTATUSREG 0x0: Disable the.." "Disable the generation of Block Transfer Done..,Enable the generation of Block Transfer Done.." rgroup.long 0x84++0xB line.long 0x0 "CH$1_INTSTATUS_ENABLEREG_1,Writing 1 to specific field enables the corresponding interrupt status generation in Channelx Interrupt Status Register(CH$1_IntStatusReg)." hexmask.long 0x0 0.--31. 1. "RSVD_DMAC_CHX_INTSTATUS_ENABLEREG_32TO63,DMAC Channelx Interrupt Status Register (bits 32to63) Reserved bits - Read Only" line.long 0x4 "CH$1_INTSTATUS_0,Channelx Interrupt Status Register captures the Channelx specific interrupts" bitfld.long 0x4 31. "CH_ABORTED_INTSTAT,Channel Aborted. This indicates to the software that the corresponding channel in DW_axi_dmac is aborted. - 0: Channel is not aborted - 1: Channel is aborted Error Interrupt is generated if the corresponding bit in.." "Channel is not aborted,Channel is aborted" newline bitfld.long 0x4 30. "CH_DISABLED_INTSTAT,Channel Disabled. This indicates to the software that the corresponding channel in DW_axi_dmac is disabled. - 0: Channel is not disabled. - 1: Channel is disabled. Error Interrupt is generated if the corresponding bit in.." "Channel is not disabled,Channel is disabled" newline bitfld.long 0x4 29. "CH_SUSPENDED_INTSTAT,Channel Suspended. This indicates to the software that the corresponding channel in DW_axi_dmac is suspended. - 0: Channel is not suspended. - 1: Channel is suspended. Error Interrupt is generated if the corresponding bit in.." "Channel is not suspended,Channel is suspended" newline bitfld.long 0x4 28. "CH_SRC_SUSPENDED_INTSTAT,Channel Source Suspended. This indicates to the software that the corresponding channel source data transfer in DW_axi_dmac is suspended. - 0: Channel source is not suspended - 1: Channel Source is suspended. Error Interrupt is.." "Channel source is not suspended,Channel Source is suspended" newline bitfld.long 0x4 27. "CH_LOCK_CLEARED_INTSTAT,Channel Lock Cleared. This indicates to the software that the locking of the corresponding channel in DW_axi_dmac is cleared. - 0: Channel locking is not cleared. - 1: Channel locking is cleared. Channel locking is cleared by.." "Channel locking is not cleared,Channel Locking is cleared" newline hexmask.long.byte 0x4 22.--26. 1. "RSVD_DMAC_CHX_INTSTATUSREG_22TO26,DMAC Channelx Specific Interrupt Register (bits 22to26) Reserved bits - Read Only" newline bitfld.long 0x4 21. "SLVIF_WRONHOLD_ERR_INTSTAT,Slave Interface Write On Hold Error. This error occurs if an illegal write operation is performed on a register; this happens if a write operation is performed on a channel register when DW_axi_dmac is in Hold mode. - 0: No.." "No Slave Interface Write On Hold Errors,Slave Interface Write On Hold Error detected" newline bitfld.long 0x4 20. "SLVIF_SHADOWREG_WRON_VALID_ERR_INTSTAT,Shadow Register Write On Valid Error. This error occurs if shadow register based multi-block transfer is enabled and software tries to write to the shadow register when CHx_CTL.ShadowReg_Or_LLI_Valid bit is 1. - 0:.." "No Slave Interface Shadow Register Write On..,Slave Interface Shadow Register Write On Valid.." newline bitfld.long 0x4 19. "SLVIF_WRONCHEN_ERR_INTSTAT,Slave Interface Write On Channel Enabled Error. This error occurs if an illegal write operation is performed on a register; this happens if a write operation is performed on a register when the channel is enabled and if it is.." "No Slave Interface Write On Channel Enabled Errors,Slave Interface Write On Channel Enabled Error.." newline bitfld.long 0x4 18. "SLVIF_RD2RWO_ERR_INTSTAT,Slave Interface Read to write Only Error. This error occurs if read operation is performed to a Write Only register. - 0: No Slave Interface Read to Write Only Errors. - 1: Slave Interface Read to Write Only Error detected. Error.." "No Slave Interface Read to Write Only Errors,Slave Interface Read to Write Only Error detected" newline bitfld.long 0x4 17. "SLVIF_WR2RO_ERR_INTSTAT,Slave Interface Write to Read Only Error. This error occurs if write operation is performed to a Read Only register. - 0: No Slave Interface Write to Read Only Errors. - 1: Slave Interface Write to Read Only Error detected. Error.." "No Slave Interface Write to Read Only Errors,Slave Interface Write to Read Only Error detected" newline bitfld.long 0x4 16. "SLVIF_DEC_ERR_INTSTAT,Slave Interface Decode Error. Decode Error generated by DW_axi_dmac during register access. This error occurs if the register access is to invalid address in Channelx register space resulting in error response by DW_axi_dmac slave.." "No Slave Interface Decode errors,Slave Interface Decode Error detected" newline bitfld.long 0x4 15. "RSVD_DMAC_CHX_INTSTATUSREG_15,DMAC Channelx Specific Interrupt Register (bit 15) Reserved bit - Read Only" "0,1" newline bitfld.long 0x4 14. "SLVIF_MULTIBLKTYPE_ERR_INTSTAT,Slave Interface Multi Block type Error. This error occurs if multi-block transfer type programmed in CHx_CFG register (SRC_MLTBLK_TYPE and DST_MLTBLK_TYPE) is invalid. This error condition causes the DW_axi_dmac to halt the.." "No Multi-block transfer type Errors,Multi-block transfer type Error detected" newline bitfld.long 0x4 13. "SHADOWREG_OR_LLI_INVALID_ERR_INTSTAT,Shadow register or LLI Invalid Error. This error occurs if CHx_CTL.ShadowReg_Or_LLI_Valid bit is seen to be 0 during DW_axi_dmac Shadow Register / LLI fetch phase. This error condition causes the DW_axi_dmac to halt.." "No Shadow Register / LLI Invalid errors,Shadow Register / LLI Invalid error detected" newline bitfld.long 0x4 12. "LLI_WR_SLV_ERR_INTSTAT,LLI WRITE Slave Error. Slave Error detected by Master Interface during LLI write-back operation. This error occurs if the slave interface on which LLI resides issues a Slave Error. This error condition causes the DW_axi_dmac to.." "No LLI write Slave Errors,LLI Write SLAVE Error detected" newline bitfld.long 0x4 11. "LLI_RD_SLV_ERR_INTSTAT,LLI Read Slave Error. Slave Error detected by Master Interface during LLI read operation. This error occurs if the slave interface on which LLI resides issues a Slave Error. This error condition causes the DW_axi_dmac to disable.." "No LLI Read Slave Errors,LLI read Slave Error detected" newline bitfld.long 0x4 10. "LLI_WR_DEC_ERR_INTSTAT,LLI WRITE Decode Error. Decode Error detected by Master Interface during LLI write-back operation. This error occurs if the access is to invalid address and a Decode Error is returned from interconnect/slave. This error condition.." "NO LLI Write Decode Errors,LLI write Decode Error detected" newline bitfld.long 0x4 9. "LLI_RD_DEC_ERR_INTSTAT,LLI Read Decode Error. Decode Error detected by Master Interface during LLI read operation. This error occurs if the access is to invalid address and a Decode Error is returned from interconnect/slave. This error condition causes.." "NO LLI Read Decode Errors,LLI Read Decode Error detected" newline bitfld.long 0x4 8. "DST_SLV_ERR_INTSTAT,Destination Slave Error. Slave Error detected by Master Interface during destination data transfer. This error occurs if the slave interface to which the data is written issues a Slave Error. This error condition causes the.." "No Destination Slave Errors,Destination Slave Errors Detected" newline bitfld.long 0x4 7. "SRC_SLV_ERR_INTSTAT,Source Slave Error. Slave Error detected by Master Interface during source data transfer. This error occurs if the slave interface from which the data is read issues a Slave Error. This error condition causes the DW_axi_dmac to.." "No Source Slave Errors,Source Slave Error Detected" newline bitfld.long 0x4 6. "DST_DEC_ERR_INTSTAT,Destination Decode Error. Decode Error detected by Master Interface during destination data transfer. This error occurs if the access is to invalid address and a Decode Error is returned from interconnect/slave. This error condition.." "No destination Decode Errors,Destination Decode Error Detected" newline bitfld.long 0x4 5. "SRC_DEC_ERR_INTSTAT,Source Decode Error. Decode Error detected by Master Interface during source data transfer. This error occurs if the access is to invalid address and a Decode Error is returned from interconnect/slave. This error condition causes the.." "No Source Decode Errors,Source Decode Error detected" newline bitfld.long 0x4 4. "DST_TRANSCOMP_INTSTAT,Destination Transaction Completed. This bit is cleared to 0 on writing 1 to the corresponding channel interrupt clear bit in CHx_IntClearReg register or on enabling the channel (needed when interrupt is not enabled. 0x1: Destination.." "Destination transaction is not complete,Destination transaction is complete" newline bitfld.long 0x4 3. "SRC_TRANSCOMP_INTSTAT,Source Transaction Completed. This bit is cleared to 0 on writing 1 to the corresponding channel interrupt clear bit in CHx_IntClearReg register or on enabling the channel (needed when interrupt is not enabled. 0x1: Source.." "Source transation is not complete,Source transaction is complete" newline bitfld.long 0x4 2. "RSVD_DMAC_CHX_INTSTATUSREG_2,DMAC Channelx Specific Interrupt Register (bit 2) Reserved bit - Read Only" "0,1" newline bitfld.long 0x4 1. "DMA_TFR_DONE_INTSTAT,DMA Transfer Done. This indicates to the software that the DW_axi_dmac has completed the requested DMA transfer. The DW_axi_dmac sets this bit to 1 along with setting CHx_INTSTATUS.BLOCK_TFR_DONE bit to 1 when the last block transfer.." "DMA Transfer not complete,DMA Transfer completed" newline bitfld.long 0x4 0. "BLOCK_TFR_DONE_INTSTAT,Block Transfer Done. This indicates to the software that the DW_axi_dmac has completed the requested block transfer. The DW_axi_dmac sets this bit to 1 when the transfer is successfully completed. - 0: Block Transfer not completed." "Block Transfer not complete,Block Transfer completed" line.long 0x8 "CH$1_INTSTATUS_1,Channelx Interrupt Status Register captures the Channelx specific interrupts" hexmask.long 0x8 0.--31. 1. "RSVD_DMAC_CHX_INTSTATUSREG_32TO63,DMAC Channelx Specific Interrupt Register (bits 32to63) Reserved bits - Read Only" group.long 0x90++0x3 line.long 0x0 "CH$1_INTSIGNAL_ENABLEREG_0,This register contains fields that are used to enable the generation of port level interrupt at the channel level." bitfld.long 0x0 31. "ENABLE_CH_ABORTED_INTSIGNAL,Channel Aborted Signal Enable. - 0: Disable the propagation of Channel Aborted Interrupt to generate a port level interrupt - 1: Enable the propagation of Channel Aborted Interrupt to generate a port level interrupt 0x0:.." "Disable the propagation of Channel Aborted..,Enable the propagation of Channel Aborted.." newline bitfld.long 0x0 30. "ENABLE_CH_DISABLED_INTSIGNAL,Channel Disabled Signal Enable. - 0: Disable the propagation of Channel Disabled Interrupt to generate a port level interrupt - 1: Enable the propagation of Channel Disabled Interrupt to generate a port level interrupt 0x0:.." "Disable the propagation of Channel Disabled..,Enable the propagation of Channel Disabled.." newline bitfld.long 0x0 29. "ENABLE_CH_SUSPENDED_INTSIGNAL,Channel Suspended Signal Enable. - 0: Disable the propagation of Channel Suspended Interrupt to generate a port level interrupt - 1: Enable the propagation of Channel Suspended Interrupt to generate a port level interrupt.." "Disable the propagation of Channel Suspended..,Enable the propagation of Channel Suspended.." newline bitfld.long 0x0 28. "ENABLE_CH_SRC_SUSPENDED_INTSIGNAL,Channel Source Suspended Signal Enable. - 0: Disable the propagation of Channel Source Suspended Interrupt to generate a port level interrupt - 1: Enable the propagation of Channel Source Suspended Interrupt to generate.." "Disable the propagation of Channel Source..,Enable the propagation of Channel Source.." newline bitfld.long 0x0 27. "ENABLE_CH_LOCK_CLEARED_INTSIGNAL,Channel Lock Cleared Signal Enable. - 0: Disable the propagation of Channel Lock Cleared Interrupt to generate a port level interrupt - 1: Enable the propagation of Channel Lock Cleared Interrupt to generate a port level.." "Disable the propagation of Channel Lock Cleared..,Enable the propagation of Channel Lock Cleared.." newline hexmask.long.byte 0x0 22.--26. 1. "RSVD_DMAC_CHX_INTSTATUS_ENABLEREG_22TO26,DMAC Channelx Interrupt Status Enable Register (bits 22to26) Reserved bits - Read Only" newline bitfld.long 0x0 21. "ENABLE_SLVIF_WRONHOLD_ERR_INTSIGNAL,Slave Interface Write On Hold Error Signal Enable. - 0: Disable the propagation of Slave Interface Write On Hold Error Interrupt to generate a port level interrupt - 1: Enable the propagation of Slave Interface Write.." "Disable the propagation of Slave Interface Write..,Enable the propagation of Slave Interface Write.." newline bitfld.long 0x0 20. "ENABLE_SLVIF_SHADOWREG_WRON_VALID_ERR_INTSIGNAL,Shadow Register Write On Valid Error Signal Enable. - 0: Disable the propagation of Shadow Register Write On Valid Error Interrupt to generate a port level interrupt - 1: Enable the propagation of Shadow.." "Disable the propagation of Shadow Register Write..,Enable the propagation of Shadow register Write.." newline bitfld.long 0x0 19. "ENABLE_SLVIF_WRONCHEN_ERR_INTSIGNAL,Slave Interface Write On Channel Enabled Error Signal Enable. - 0: Disable the propagation of Slave Interface Write On Channel enabled Error Interrupt to generate a port level interrupt - 1: Enable the propagation of.." "Disable the propagation of Slave Interface Write..,Enable the propagation of Slave Interface Write.." newline bitfld.long 0x0 18. "ENABLE_SLVIF_RD2RWO_ERR_INTSIGNAL,Slave Interface Read to write Only Error Signal Enable. - 0: Disable the propagation of Slave Interface Read to Write only Error Interrupt to generate a port level interrupt - 1: Enable the propagation of Slave Interface.." "Disable the propagation of Slave Interface Read..,Enable the propagation of Slave Interface Read.." newline bitfld.long 0x0 17. "ENABLE_SLVIF_WR2RO_ERR_INTSIGNAL,Slave Interface Write to Read Only Error Signal Enable. - 0: Disable the propagation of Slave Interface Write to Read only Error Interrupt to generate a port level interrupt - 1: Enable the propagation of Slave Interface.." "Disable the propagation of Slave Interface Write..,Enable the propagation of Slave Interface Write.." newline bitfld.long 0x0 16. "ENABLE_SLVIF_DEC_ERR_INTSIGNAL,Slave Interface Decode Error Signal Enable. - 0: Disable the propagation of Slave Interface Decode Error Interrupt to generate a port level interrupt - 1: Enable the propagation of Slave Interface Decode Error Interrupt to.." "Disable the propagation of Slave Interface..,Enable the propagation of Slave Interface Decode.." newline rbitfld.long 0x0 15. "RSVD_DMAC_CHX_INTSTATUS_ENABLEREG_15,DMAC Channelx Interrupt Status Enable Register (bit 15) Reserved bit - Read Only" "0,1" newline bitfld.long 0x0 14. "ENABLE_SLVIF_MULTIBLKTYPE_ERR_INTSIGNAL,Slave Interface Multi Block type Error Signal Enable. - 0: Disable the propagation of Slave Interface Multi Block type Error Interrupt to generate a port level interrupt - 1: Enable the propagation of Slave.." "Disable the propagation of Slave Interface Multi..,Enable the propagation of Slave Interface Multi.." newline bitfld.long 0x0 13. "ENABLE_SHADOWREG_OR_LLI_INVALID_ERR_INTSIGNAL,Shadow register or LLI Invalid Error Signal Enable. - 0: Disable the propagation of Shadow Register or LLI Invalid Error Interrupt to generate a port level interrupt - 1: Enable the propagation of Shadow.." "Disable the propagation of Shadow Register or..,Enable the propagation of Shadow Register or LLI.." newline bitfld.long 0x0 12. "ENABLE_LLI_WR_SLV_ERR_INTSIGNAL,LLI WRITE Slave Error Signal Enable. - 0: Disable the propagation of LLI WRITE Slave Error Interrupt to generate a port level interrupt - 1: Enable the propagation of LLI WRITE Slave Error Interrupt to generate a port.." "Disable the propagation of LLI WRITE Slave Error..,Enable the propagation of LLI WRITE Slave Error.." newline bitfld.long 0x0 11. "ENABLE_LLI_RD_SLV_ERR_INTSIGNAL,LLI Read Slave Error Signal Enable. - 0: Disable the propagation of LLI Read Slave Error Interrupt to generate a port level interrupt - 1: Enable the propagation of LLI Read Slave Error Interrupt to generate a port level.." "Disable the propagation of LLI Read Slave Error..,Enable the propagation of LLI Read Slave Error.." newline bitfld.long 0x0 10. "ENABLE_LLI_WR_DEC_ERR_INTSIGNAL,LLI WRITE Decode Error Signal Enable. - 0: Disable the propagation of LLI WRITE Decode Error Interrupt to generate a port level interrupt - 1: Enable the propagation of LLI WRITE Decode Error Interrupt to generate a port.." "Disable the propagation of LLI WRITE Decode..,Enable the propagation of LLI WRITE Decode Error.." newline bitfld.long 0x0 9. "ENABLE_LLI_RD_DEC_ERR_INTSIGNAL,LLI Read Decode Error Signal Enable. - 0: Disable the propagation of LLI Read Decode Error Interrupt to generate a port level interrupt - 1: Enable the propagation of LLI Read Decode Error Interrupt to generate a port.." "Disable the propagation of LLI Read Decode Error..,Enable the propagation of LLI Read Decode Error.." newline bitfld.long 0x0 8. "ENABLE_DST_SLV_ERR_INTSIGNAL,Destination Slave Error Signal Enable. - 0: Disable the propagation of Destination Slave Error Interrupt to generate a port level interrupt - 1: Enable the propagation of Destination Slave Error Interrupt to generate a port.." "Disable the propagation of Destination Slave..,Enable the propagation of Destination Slave.." newline bitfld.long 0x0 7. "ENABLE_SRC_SLV_ERR_INTSIGNAL,Source Slave Error Signal Enable. - 0: Disable the propagation of Source Slave Error Interrupt to generate a port level interrupt - 1: Enable the propagation of Source Slave Error Interrupt to generate a port level interrupt.." "Disable the propagation of Source Slave Error..,Enable the propagation of Source Slave Error.." newline bitfld.long 0x0 6. "ENABLE_DST_DEC_ERR_INTSIGNAL,Destination Decode Error Signal Enable. - 0: Disable the propagation of Destination Decode Error Interrupt to generate a port level interrupt - 1: Enable the propagation of Destination Decode Error Interrupt to generate a.." "Disable the propagation of Destination Decode..,Enable the propagation of Destination Decode.." newline bitfld.long 0x0 5. "ENABLE_SRC_DEC_ERR_INTSIGNAL,Source Decode Error Signal Enable. - 0: Disable the propagation of Source Decode Error Interrupt to generate a port level interrupt - 1: Enable the propagation of Source Decode Error Interrupt to generate a port level.." "Disable the propagation of Source Decode Error..,Enable the propagation of Source Decode Error.." newline bitfld.long 0x0 4. "ENABLE_DST_TRANSCOMP_INTSIGNAL,Destination Transaction Completed Signal Enable. - 0: Disable the propagation of Destination Transaction complete Interrupt to generate a port level interrupt - 1: Enable the propagation of Destination Transaction complete.." "Disable the propagation of Destination..,Enable the propagation of Destination.." newline bitfld.long 0x0 3. "ENABLE_SRC_TRANSCOMP_INTSIGNAL,Source Transaction Completed Signal Enable. - 0: Disable the propagation of Source Transaction Complete Interrupt to generate a port level interrupt - 1: Enable the propagation of Source Transaction Complete Interrupt to.." "Disable the propagation of Source Transaction..,Enable the propagation of Source Transaction.." newline rbitfld.long 0x0 2. "RSVD_DMAC_CHX_INTSTATUS_ENABLEREG_2,DMAC Channelx Interrupt Status Enable Register (bit 2) Reserved bit - Read Only" "0,1" newline bitfld.long 0x0 1. "ENABLE_DMA_TFR_DONE_INTSIGNAL,DMA Transfer Done Interrupt Signal Enable. - 0: Disable the propagation of DMA Transfer Done Interrupt to generate a port level interrupt - 1: Enable the propagation of DMA Transfer Done Interrupt to generate a port level.." "Disable the propagation of DMA Transfer Done..,Enable the propagation of DMA Transfer Done.." newline bitfld.long 0x0 0. "ENABLE_BLOCK_TFR_DONE_INTSIGNAL,Block Transfer Done Interrupt Signal Enable. - 0: Disable the propagation of Block Transfer Done Interrupt to generate a port level interrupt - 1: Enable the propagation of Block Transfer Done Interrupt to generate a port.." "Disable the propagation of Block Transfer Done..,Enable the propagation of Block Transfer Done.." rgroup.long 0x94++0x3 line.long 0x0 "CH$1_INTSIGNAL_ENABLEREG_1,This register contains fields that are used to enable the generation of port level interrupt at the channel level." hexmask.long 0x0 0.--31. 1. "RSVD_DMAC_CHX_INTSTATUS_ENABLEREG_32TO63,DMAC Channelx Interrupt Status Enable Register (bits 32to63) Reserved bits - Read Only" wgroup.long 0x98++0x7 line.long 0x0 "CH$1_INTCLEARREG_0,Writing 1 to specific field will clear the corresponding field in Channelx Interrupt Status Register(CHx_IntStatusReg)." bitfld.long 0x0 31. "CLEAR_CH_ABORTED_INTSTAT,Channel Aborted Interrupt Clear Bit. This bit is used to clear the corresponding channel interrupt status bit in CHx_INTSTATUSREG. 0x1: Clear the CH_ABORTED interrupt in the Interrupt Status Register(CH$1_IntStatusReg). 0x0:.." "Inactive signal,Clear the CH_ABORTED interrupt in the Interrupt.." newline bitfld.long 0x0 30. "CLEAR_CH_DISABLED_INTSTAT,Channel Disabled Interrupt Clear Bit. This bit is used to clear the corresponding channel interrupt status bit in CHx_INTSTATUSREG. 0x1: Clear the CH_DISABLED interrupt in the Interrupt Status Register(CH$1_IntStatusReg). 0x0:.." "Inactive signal,Clear the CH_DISABLED interrupt in the Interrupt.." newline bitfld.long 0x0 29. "CLEAR_CH_SUSPENDED_INTSTAT,Channel Suspended Interrupt Clear Bit. This bit is used to clear the corresponding channel interrupt status bit in CHx_INTSTATUSREG. 0x1: Clear the CH_SUSPENDED interrupt in the Interrupt Status Register(CH$1_IntStatusReg). 0x0:.." "Inactive signal,Clear the CH_SUSPENDED interrupt in the.." newline bitfld.long 0x0 28. "CLEAR_CH_SRC_SUSPENDED_INTSTAT,Channel Source Suspended Interrupt Clear Bit. This bit is used to clear the corresponding channel interrupt status bit in CHx_INTSTATUSREG. 0x1: Clear the CH_SRC_SUSPENDED interrupt in the Interrupt Status.." "Inactive signal,Clear the CH_SRC_SUSPENDED interrupt in the.." newline bitfld.long 0x0 27. "CLEAR_CH_LOCK_CLEARED_INTSTAT,Channel Lock Cleared Interrupt Clear Bit. This bit is used to clear the corresponding channel interrupt status bit in CHx_INTSTATUSREG. 0x1: Clear the CH_LOCK_CLEARED interrupt in the Interrupt Status.." "Inactive signal,Clear the CH_LOCK_CLEARED interrupt in the.." newline hexmask.long.byte 0x0 22.--26. 1. "RSVD_DMAC_CHX_INTCLEARREG_22TO26,DMAC Channelx Interrupt Clear Register (bits 22to26) Reserved bit - Read Only" newline bitfld.long 0x0 21. "CLEAR_SLVIF_WRONHOLD_ERR_INTSTAT,Slave Interface Write On Hold Error Interrupt Clear Bit. This bit is used to clear the corresponding channel interrupt status bit in CHx_INTSTATUSREG. 0x1: Clear the SLVIF_WRONHOLD_ERR interrupt in the Interrupt Status.." "Inactive signal,Clear the SLVIF_WRONHOLD_ERR interrupt in the.." newline bitfld.long 0x0 20. "CLEAR_SLVIF_SHADOWREG_WRON_VALID_ERR_INTSTAT,Shadow Register Write On Valid Error Interrupt Clear Bit. This bit is used to clear the corresponding channel interrupt status bit in CHx_INTSTATUSREG. 0x1: Clear the SLVIF_SHADOWREG_WRON_VALID_ERR interrupt.." "Inactive signal,Clear the SLVIF_SHADOWREG_WRON_VALID_ERR.." newline bitfld.long 0x0 19. "CLEAR_SLVIF_WRONCHEN_ERR_INTSTAT,Slave Interface Write On Channel Enabled Error Interrupt Clear Bit. This bit is used to clear the corresponding channel interrupt status bit in CHx_INTSTATUSREG. 0x1: Clear the SLVIF_WRONCHEN_ERR interrupt in the.." "Inactive signal,Clear the SLVIF_WRONCHEN_ERR interrupt in the.." newline bitfld.long 0x0 18. "CLEAR_SLVIF_RD2RWO_ERR_INTSTAT,Slave Interface Read to write Only Error Interrupt Clear Bit. This bit is used to clear the corresponding channel interrupt status bit in CHx_INTSTATUSREG. 0x1: Clear the SLVIF_RD2RWO_ERR interrupt in the Interrupt Status.." "Inactive signal,Clear the SLVIF_RD2RWO_ERR interrupt in the.." newline bitfld.long 0x0 17. "CLEAR_SLVIF_WR2RO_ERR_INTSTAT,Slave Interface Write to Read Only Error Interrupt Clear Bit. This bit is used to clear the corresponding channel interrupt status bit in CHx_INTSTATUSREG. 0x1: Clear the SLVIF_WR2RO_ERR interrupt in the Interrupt Status.." "Inactive signal,Clear the SLVIF_WR2RO_ERR interrupt in the.." newline bitfld.long 0x0 16. "CLEAR_SLVIF_DEC_ERR_INTSTAT,Slave Interface Decode Error Interrupt Clear Bit. This bit is used to clear the corresponding channel interrupt status bit in CHx_INTSTATUSREG. 0x1: Clear the SLVIF_DEC_ERR interrupt in the Interrupt Status.." "Inactive signal,Clear the SLVIF_DEC_ERR interrupt in the.." newline bitfld.long 0x0 15. "RSVD_DMAC_CHX_INTCLEARREG_15,DMAC Channelx Interrupt Clear Register (bit 15) Reserved bit - Read Only" "0,1" newline bitfld.long 0x0 14. "CLEAR_SLVIF_MULTIBLKTYPE_ERR_INTSTAT,Slave Interface Multi Block type Error Interrupt Clear Bit. This bit is used to clear the corresponding channel interrupt status bit in CHx_INTSTATUSREG. 0x1: Clear the SLVIF_MULTIBLKTYPE_ERR interrupt in the.." "Inactive signal,Clear the SLVIF_MULTIBLKTYPE_ERR interrupt in.." newline bitfld.long 0x0 13. "CLEAR_SHADOWREG_OR_LLI_INVALID_ERR_INTSTAT,Shadow register or LLI Invalid Error Interrupt Clear Bit. This bit is used to clear the corresponding channel interrupt status bit in CHx_INTSTATUSREG. 0x1: Clear the SHADOWREG_OR_LLI_INVALID_ERR interrupt in.." "Inactive signal,Clear the SHADOWREG_OR_LLI_INVALID_ERR interrupt.." newline bitfld.long 0x0 12. "CLEAR_LLI_WR_SLV_ERR_INTSTAT,LLI WRITE Slave Error Interrupt Clear Bit. This bit is used to clear the corresponding channel interrupt status bit in CHx_INTSTATUSREG. 0x1: Clear the LLI_WR_SLV_ERR interrupt in the Interrupt Status.." "Inactive signal,Clear the LLI_WR_SLV_ERR interrupt in the.." newline bitfld.long 0x0 11. "CLEAR_LLI_RD_SLV_ERR_INTSTAT,LLI Read Slave Error Interrupt Clear Bit. This bit is used to clear the corresponding channel interrupt status bit in CHx_INTSTATUSREG. 0x1: Clear the LLI_RD_SLV_ERR interrupt in the Interrupt Status.." "Inactive signal,Clear the LLI_RD_SLV_ERR interrupt in the.." newline bitfld.long 0x0 10. "CLEAR_LLI_WR_DEC_ERR_INTSTAT,LLI WRITE Decode Error Interrupt Clear Bit. This bit is used to clear the corresponding channel interrupt status bit in CHx_INTSTATUSREG. 0x1: Clear the LLI_WR_DEC_ERR interrupt in the Interrupt Status.." "Inactive signal,Clear the LLI_WR_DEC_ERR interrupt in the.." newline bitfld.long 0x0 9. "CLEAR_LLI_RD_DEC_ERR_INTSTAT,LLI Read Decode Error Interrupt Clear Bit. This bit is used to clear the corresponding channel interrupt status bit in CHx_INTSTATUSREG. 0x1: Clear the LLI_RD_DEC_ERR interrupt in the Interrupt Status.." "Inactive signal,Clear the LLI_RD_DEC_ERR interrupt in the.." newline bitfld.long 0x0 8. "CLEAR_DST_SLV_ERR_INTSTAT,Destination Slave Error Interrupt Clear Bit. This bit is used to clear the corresponding channel interrupt status bit in CHx_INTSTATUSREG. 0x1: Clear the DST_SLV_ERR interrupt in the Interrupt Status Register(CH$1_IntStatusReg)." "Inactive signal,Clear the DST_SLV_ERR interrupt in the Interrupt.." newline bitfld.long 0x0 7. "CLEAR_SRC_SLV_ERR_INTSTAT,Source Slave Error Interrupt Clear Bit. This bit is used to clear the corresponding channel interrupt status bit in CHx_INTSTATUSREG. 0x1: Clear the SRC_SLV_ERR interrupt in the Interrupt Status Register(CH$1_IntStatusReg). 0x0:.." "Inactive signal,Clear the SRC_SLV_ERR interrupt in the Interrupt.." newline bitfld.long 0x0 6. "CLEAR_DST_DEC_ERR_INTSTAT,Destination Decode Error Interrupt Clear Bit. This bit is used to clear the corresponding channel interrupt status bit in CHx_INTSTATUSREG. 0x1: Clear the DST_DEC_ERR interrupt in the Interrupt Status Register(CH$1_IntStatusReg)." "Inactive signal,Clear the DST_DEC_ERR interrupt in the Interrupt.." newline bitfld.long 0x0 5. "CLEAR_SRC_DEC_ERR_INTSTAT,Source Decode Error Interrupt Clear Bit. This bit is used to clear the corresponding channel interrupt status bit in CHx_INTSTATUSREG. 0x1: Clear the SRC_DEC_ERR interrupt in the Interrupt Status Register(CH$1_IntStatusReg). 0x0:.." "Inactive signal,Clear the SRC_DEC_ERR interrupt in the Interrupt.." newline bitfld.long 0x0 4. "CLEAR_DST_TRANSCOMP_INTSTAT,Destination Transaction Completed Interrupt Clear Bit. This bit is used to clear the corresponding channel interrupt status bit in CHx_INTSTATUSREG. 0x1: Clear the DST_TRANSCOMP interrupt in the Interrupt Status.." "Inactive signal,Clear the DST_TRANSCOMP interrupt in the.." newline bitfld.long 0x0 3. "CLEAR_SRC_TRANSCOMP_INTSTAT,Source Transaction Completed Interrupt Clear Bit. This bit is used to clear the corresponding channel interrupt status bit in CHx_INTSTATUSREG. 0x1: Clear the SRC_TRANSCOMP interrupt in the Interrupt Status.." "Inactive signal,Clear the SRC_TRANSCOMP interrupt in the.." newline bitfld.long 0x0 2. "RSVD_DMAC_CHX_INTCLEARREG_2,DMAC Channelx Interrupt Clear Register (bit 2) Reserved bit - Read Only" "0,1" newline bitfld.long 0x0 1. "CLEAR_DMA_TFR_DONE_INTSTAT,DMA Transfer Done Interrupt Clear Bit. This bit is used to clear the corresponding channel interrupt status bit in CHx_INTSTATUSREG. 0x1: Clear the DMA_TFR_DONE interrupt in the Interrupt Status Register(CH$1_IntStatusReg). 0x0:.." "Inactive signal,Clear the DMA_TFR_DONE interrupt in the.." newline bitfld.long 0x0 0. "CLEAR_BLOCK_TFR_DONE_INTSTAT,Block Transfer Done Interrupt Clear Bit. This bit is used to clear the corresponding channel interrupt status bit in CH$1_INTSTATUSREG 0x1: Clear the interrupt in the Interrupt Status Register(CHx_IntStatusReg). Writing a 1 to.." "Inactive signal,Clear the interrupt in the Interrupt Status.." line.long 0x4 "CH$1_INTCLEARREG_1,Writing 1 to specific field will clear the corresponding field in Channelx Interrupt Status Register(CHx_IntStatusReg)." hexmask.long 0x4 0.--31. 1. "RSVD_DMAC_CHX_INTCLEARREG_32TO63,DMAC Channelx Interrupt Clear Register (bits 32to63) Reserved bit - Read Only" tree.end tree.end repeat.end endif tree.end tree "DMA_MUX (DMA MUX Controller)" sif (CORENAME()=="CORTEXR5F") tree "DMA_MUX_PCIE1" base ad:0xF13C0000 group.long 0x0++0x23 line.long 0x0 "MUX_CHANNEL1,MUX channel 1 mapping parameter" hexmask.long.byte 0x0 24.--31. 1. "UPDATED_RD_HDSK_MAPPING,MUX channel 1 read handshaking mapping parameter after DMA updating." hexmask.long.byte 0x0 16.--23. 1. "RD_HDSK_MAPPING,MUX channel 1 read handshaking mapping parameter" hexmask.long.byte 0x0 8.--15. 1. "UPDATED_WR_HDSK_MAPPING,MUX channel 1 write handshaking mapping parameter after DMA updating." hexmask.long.byte 0x0 0.--7. 1. "WR_HDSK_MAPPING,MUX channel 1 write handshaking mapping parameter" line.long 0x4 "MUX_CHANNEL2,MUX channel 2 mapping parameter" hexmask.long.byte 0x4 24.--31. 1. "UPDATED_RD_HDSK_MAPPING,MUX channel 2 read handshaking mapping parameter after DMA updating." hexmask.long.byte 0x4 16.--23. 1. "RD_HDSK_MAPPING,MUX channel 2 read handshaking mapping parameter" hexmask.long.byte 0x4 8.--15. 1. "UPDATED_WR_HDSK_MAPPING,MUX channel 2 write handshaking mapping parameter after DMA updating." hexmask.long.byte 0x4 0.--7. 1. "WR_HDSK_MAPPING,MUX channel 2 write handshaking mapping parameter" line.long 0x8 "MUX_CHANNEL3,MUX channel 3 mapping parameter" hexmask.long.byte 0x8 24.--31. 1. "UPDATED_RD_HDSK_MAPPING,MUX channel 3 read handshaking mapping parameter after DMA updating." hexmask.long.byte 0x8 16.--23. 1. "RD_HDSK_MAPPING,MUX channel 3 read handshaking mapping parameter" hexmask.long.byte 0x8 8.--15. 1. "UPDATED_WR_HDSK_MAPPING,MUX channel 3 write handshaking mapping parameter after DMA updating." hexmask.long.byte 0x8 0.--7. 1. "WR_HDSK_MAPPING,MUX channel 3 write handshaking mapping parameter" line.long 0xC "MUX_CHANNEL4,MUX channel 4 mapping parameter" hexmask.long.byte 0xC 24.--31. 1. "UPDATED_RD_HDSK_MAPPING,MUX channel 4 read handshaking mapping parameter after DMA updating." hexmask.long.byte 0xC 16.--23. 1. "RD_HDSK_MAPPING,MUX channel 4 read handshaking mapping parameter" hexmask.long.byte 0xC 8.--15. 1. "UPDATED_WR_HDSK_MAPPING,MUX channel 4 write handshaking mapping parameter after DMA updating." hexmask.long.byte 0xC 0.--7. 1. "WR_HDSK_MAPPING,MUX channel 4 write handshaking mapping parameter" line.long 0x10 "MUX_CHANNEL5,MUX channel 5 mapping parameter" hexmask.long.byte 0x10 24.--31. 1. "UPDATED_RD_HDSK_MAPPING,MUX channel 5 read handshaking mapping parameter after DMA updating." hexmask.long.byte 0x10 16.--23. 1. "RD_HDSK_MAPPING,MUX channel 5 read handshaking mapping parameter" hexmask.long.byte 0x10 8.--15. 1. "UPDATED_WR_HDSK_MAPPING,MUX channel 5 write handshaking mapping parameter after DMA updating." hexmask.long.byte 0x10 0.--7. 1. "WR_HDSK_MAPPING,MUX channel 5 write handshaking mapping parameter" line.long 0x14 "MUX_CHANNEL6,MUX channel 6 mapping parameter" hexmask.long.byte 0x14 24.--31. 1. "UPDATED_RD_HDSK_MAPPING,MUX channel 6 read handshaking mapping parameter after DMA updating." hexmask.long.byte 0x14 16.--23. 1. "RD_HDSK_MAPPING,MUX channel 6 read handshaking mapping parameter" hexmask.long.byte 0x14 8.--15. 1. "UPDATED_WR_HDSK_MAPPING,MUX channel 6 write handshaking mapping parameter after DMA updating." hexmask.long.byte 0x14 0.--7. 1. "WR_HDSK_MAPPING,MUX channel 6 write handshaking mapping parameter" line.long 0x18 "MUX_CHANNEL7,MUX channel 7 mapping parameter" hexmask.long.byte 0x18 24.--31. 1. "UPDATED_RD_HDSK_MAPPING,MUX channel 7 read handshaking mapping parameter after DMA updating." hexmask.long.byte 0x18 16.--23. 1. "RD_HDSK_MAPPING,MUX channel 7 read handshaking mapping parameter" hexmask.long.byte 0x18 8.--15. 1. "UPDATED_WR_HDSK_MAPPING,MUX channel 7 write handshaking mapping parameter after DMA updating." hexmask.long.byte 0x18 0.--7. 1. "WR_HDSK_MAPPING,MUX channel 7 write handshaking mapping parameter" line.long 0x1C "MUX_CHANNEL8,MUX channel 8 mapping parameter" hexmask.long.byte 0x1C 24.--31. 1. "UPDATED_RD_HDSK_MAPPING,MUX channel 8 read handshaking mapping parameter after DMA updating." hexmask.long.byte 0x1C 16.--23. 1. "RD_HDSK_MAPPING,MUX channel 8 read handshaking mapping parameter" hexmask.long.byte 0x1C 8.--15. 1. "UPDATED_WR_HDSK_MAPPING,MUX channel 8 write handshaking mapping parameter after DMA updating." hexmask.long.byte 0x1C 0.--7. 1. "WR_HDSK_MAPPING,MUX channel 8 write handshaking mapping parameter" line.long 0x20 "MUX_REG_UPDATE,MUX register update" bitfld.long 0x20 0. "ENABLE,MUX register update enable" "0,1" tree.end tree "DMA_MUX_PCIE2" base ad:0xF13E0000 group.long 0x0++0x23 line.long 0x0 "MUX_CHANNEL1,MUX channel 1 mapping parameter" hexmask.long.byte 0x0 24.--31. 1. "UPDATED_RD_HDSK_MAPPING,MUX channel 1 read handshaking mapping parameter after DMA updating." hexmask.long.byte 0x0 16.--23. 1. "RD_HDSK_MAPPING,MUX channel 1 read handshaking mapping parameter" hexmask.long.byte 0x0 8.--15. 1. "UPDATED_WR_HDSK_MAPPING,MUX channel 1 write handshaking mapping parameter after DMA updating." hexmask.long.byte 0x0 0.--7. 1. "WR_HDSK_MAPPING,MUX channel 1 write handshaking mapping parameter" line.long 0x4 "MUX_CHANNEL2,MUX channel 2 mapping parameter" hexmask.long.byte 0x4 24.--31. 1. "UPDATED_RD_HDSK_MAPPING,MUX channel 2 read handshaking mapping parameter after DMA updating." hexmask.long.byte 0x4 16.--23. 1. "RD_HDSK_MAPPING,MUX channel 2 read handshaking mapping parameter" hexmask.long.byte 0x4 8.--15. 1. "UPDATED_WR_HDSK_MAPPING,MUX channel 2 write handshaking mapping parameter after DMA updating." hexmask.long.byte 0x4 0.--7. 1. "WR_HDSK_MAPPING,MUX channel 2 write handshaking mapping parameter" line.long 0x8 "MUX_CHANNEL3,MUX channel 3 mapping parameter" hexmask.long.byte 0x8 24.--31. 1. "UPDATED_RD_HDSK_MAPPING,MUX channel 3 read handshaking mapping parameter after DMA updating." hexmask.long.byte 0x8 16.--23. 1. "RD_HDSK_MAPPING,MUX channel 3 read handshaking mapping parameter" hexmask.long.byte 0x8 8.--15. 1. "UPDATED_WR_HDSK_MAPPING,MUX channel 3 write handshaking mapping parameter after DMA updating." hexmask.long.byte 0x8 0.--7. 1. "WR_HDSK_MAPPING,MUX channel 3 write handshaking mapping parameter" line.long 0xC "MUX_CHANNEL4,MUX channel 4 mapping parameter" hexmask.long.byte 0xC 24.--31. 1. "UPDATED_RD_HDSK_MAPPING,MUX channel 4 read handshaking mapping parameter after DMA updating." hexmask.long.byte 0xC 16.--23. 1. "RD_HDSK_MAPPING,MUX channel 4 read handshaking mapping parameter" hexmask.long.byte 0xC 8.--15. 1. "UPDATED_WR_HDSK_MAPPING,MUX channel 4 write handshaking mapping parameter after DMA updating." hexmask.long.byte 0xC 0.--7. 1. "WR_HDSK_MAPPING,MUX channel 4 write handshaking mapping parameter" line.long 0x10 "MUX_CHANNEL5,MUX channel 5 mapping parameter" hexmask.long.byte 0x10 24.--31. 1. "UPDATED_RD_HDSK_MAPPING,MUX channel 5 read handshaking mapping parameter after DMA updating." hexmask.long.byte 0x10 16.--23. 1. "RD_HDSK_MAPPING,MUX channel 5 read handshaking mapping parameter" hexmask.long.byte 0x10 8.--15. 1. "UPDATED_WR_HDSK_MAPPING,MUX channel 5 write handshaking mapping parameter after DMA updating." hexmask.long.byte 0x10 0.--7. 1. "WR_HDSK_MAPPING,MUX channel 5 write handshaking mapping parameter" line.long 0x14 "MUX_CHANNEL6,MUX channel 6 mapping parameter" hexmask.long.byte 0x14 24.--31. 1. "UPDATED_RD_HDSK_MAPPING,MUX channel 6 read handshaking mapping parameter after DMA updating." hexmask.long.byte 0x14 16.--23. 1. "RD_HDSK_MAPPING,MUX channel 6 read handshaking mapping parameter" hexmask.long.byte 0x14 8.--15. 1. "UPDATED_WR_HDSK_MAPPING,MUX channel 6 write handshaking mapping parameter after DMA updating." hexmask.long.byte 0x14 0.--7. 1. "WR_HDSK_MAPPING,MUX channel 6 write handshaking mapping parameter" line.long 0x18 "MUX_CHANNEL7,MUX channel 7 mapping parameter" hexmask.long.byte 0x18 24.--31. 1. "UPDATED_RD_HDSK_MAPPING,MUX channel 7 read handshaking mapping parameter after DMA updating." hexmask.long.byte 0x18 16.--23. 1. "RD_HDSK_MAPPING,MUX channel 7 read handshaking mapping parameter" hexmask.long.byte 0x18 8.--15. 1. "UPDATED_WR_HDSK_MAPPING,MUX channel 7 write handshaking mapping parameter after DMA updating." hexmask.long.byte 0x18 0.--7. 1. "WR_HDSK_MAPPING,MUX channel 7 write handshaking mapping parameter" line.long 0x1C "MUX_CHANNEL8,MUX channel 8 mapping parameter" hexmask.long.byte 0x1C 24.--31. 1. "UPDATED_RD_HDSK_MAPPING,MUX channel 8 read handshaking mapping parameter after DMA updating." hexmask.long.byte 0x1C 16.--23. 1. "RD_HDSK_MAPPING,MUX channel 8 read handshaking mapping parameter" hexmask.long.byte 0x1C 8.--15. 1. "UPDATED_WR_HDSK_MAPPING,MUX channel 8 write handshaking mapping parameter after DMA updating." hexmask.long.byte 0x1C 0.--7. 1. "WR_HDSK_MAPPING,MUX channel 8 write handshaking mapping parameter" line.long 0x20 "MUX_REG_UPDATE,MUX register update" bitfld.long 0x20 0. "ENABLE,MUX register update enable" "0,1" tree.end repeat 8. (increment 1. 1.) (list ad:0xF01E0000 ad:0xF0440000 ad:0xF0450000 ad:0xF0460000 ad:0xF0470000 ad:0xF0480000 ad:0xF0490000 ad:0xF04A0000) tree "DMA_MUX$1" base $2 group.long 0x0++0x23 line.long 0x0 "MUX_CHANNEL1,MUX channel 1 mapping parameter" hexmask.long.byte 0x0 24.--31. 1. "UPDATED_RD_HDSK_MAPPING,MUX channel 1 read handshaking mapping parameter after DMA updating." hexmask.long.byte 0x0 16.--23. 1. "RD_HDSK_MAPPING,MUX channel 1 read handshaking mapping parameter" hexmask.long.byte 0x0 8.--15. 1. "UPDATED_WR_HDSK_MAPPING,MUX channel 1 write handshaking mapping parameter after DMA updating." hexmask.long.byte 0x0 0.--7. 1. "WR_HDSK_MAPPING,MUX channel 1 write handshaking mapping parameter" line.long 0x4 "MUX_CHANNEL2,MUX channel 2 mapping parameter" hexmask.long.byte 0x4 24.--31. 1. "UPDATED_RD_HDSK_MAPPING,MUX channel 2 read handshaking mapping parameter after DMA updating." hexmask.long.byte 0x4 16.--23. 1. "RD_HDSK_MAPPING,MUX channel 2 read handshaking mapping parameter" hexmask.long.byte 0x4 8.--15. 1. "UPDATED_WR_HDSK_MAPPING,MUX channel 2 write handshaking mapping parameter after DMA updating." hexmask.long.byte 0x4 0.--7. 1. "WR_HDSK_MAPPING,MUX channel 2 write handshaking mapping parameter" line.long 0x8 "MUX_CHANNEL3,MUX channel 3 mapping parameter" hexmask.long.byte 0x8 24.--31. 1. "UPDATED_RD_HDSK_MAPPING,MUX channel 3 read handshaking mapping parameter after DMA updating." hexmask.long.byte 0x8 16.--23. 1. "RD_HDSK_MAPPING,MUX channel 3 read handshaking mapping parameter" hexmask.long.byte 0x8 8.--15. 1. "UPDATED_WR_HDSK_MAPPING,MUX channel 3 write handshaking mapping parameter after DMA updating." hexmask.long.byte 0x8 0.--7. 1. "WR_HDSK_MAPPING,MUX channel 3 write handshaking mapping parameter" line.long 0xC "MUX_CHANNEL4,MUX channel 4 mapping parameter" hexmask.long.byte 0xC 24.--31. 1. "UPDATED_RD_HDSK_MAPPING,MUX channel 4 read handshaking mapping parameter after DMA updating." hexmask.long.byte 0xC 16.--23. 1. "RD_HDSK_MAPPING,MUX channel 4 read handshaking mapping parameter" hexmask.long.byte 0xC 8.--15. 1. "UPDATED_WR_HDSK_MAPPING,MUX channel 4 write handshaking mapping parameter after DMA updating." hexmask.long.byte 0xC 0.--7. 1. "WR_HDSK_MAPPING,MUX channel 4 write handshaking mapping parameter" line.long 0x10 "MUX_CHANNEL5,MUX channel 5 mapping parameter" hexmask.long.byte 0x10 24.--31. 1. "UPDATED_RD_HDSK_MAPPING,MUX channel 5 read handshaking mapping parameter after DMA updating." hexmask.long.byte 0x10 16.--23. 1. "RD_HDSK_MAPPING,MUX channel 5 read handshaking mapping parameter" hexmask.long.byte 0x10 8.--15. 1. "UPDATED_WR_HDSK_MAPPING,MUX channel 5 write handshaking mapping parameter after DMA updating." hexmask.long.byte 0x10 0.--7. 1. "WR_HDSK_MAPPING,MUX channel 5 write handshaking mapping parameter" line.long 0x14 "MUX_CHANNEL6,MUX channel 6 mapping parameter" hexmask.long.byte 0x14 24.--31. 1. "UPDATED_RD_HDSK_MAPPING,MUX channel 6 read handshaking mapping parameter after DMA updating." hexmask.long.byte 0x14 16.--23. 1. "RD_HDSK_MAPPING,MUX channel 6 read handshaking mapping parameter" hexmask.long.byte 0x14 8.--15. 1. "UPDATED_WR_HDSK_MAPPING,MUX channel 6 write handshaking mapping parameter after DMA updating." hexmask.long.byte 0x14 0.--7. 1. "WR_HDSK_MAPPING,MUX channel 6 write handshaking mapping parameter" line.long 0x18 "MUX_CHANNEL7,MUX channel 7 mapping parameter" hexmask.long.byte 0x18 24.--31. 1. "UPDATED_RD_HDSK_MAPPING,MUX channel 7 read handshaking mapping parameter after DMA updating." hexmask.long.byte 0x18 16.--23. 1. "RD_HDSK_MAPPING,MUX channel 7 read handshaking mapping parameter" hexmask.long.byte 0x18 8.--15. 1. "UPDATED_WR_HDSK_MAPPING,MUX channel 7 write handshaking mapping parameter after DMA updating." hexmask.long.byte 0x18 0.--7. 1. "WR_HDSK_MAPPING,MUX channel 7 write handshaking mapping parameter" line.long 0x1C "MUX_CHANNEL8,MUX channel 8 mapping parameter" hexmask.long.byte 0x1C 24.--31. 1. "UPDATED_RD_HDSK_MAPPING,MUX channel 8 read handshaking mapping parameter after DMA updating." hexmask.long.byte 0x1C 16.--23. 1. "RD_HDSK_MAPPING,MUX channel 8 read handshaking mapping parameter" hexmask.long.byte 0x1C 8.--15. 1. "UPDATED_WR_HDSK_MAPPING,MUX channel 8 write handshaking mapping parameter after DMA updating." hexmask.long.byte 0x1C 0.--7. 1. "WR_HDSK_MAPPING,MUX channel 8 write handshaking mapping parameter" line.long 0x20 "MUX_REG_UPDATE,MUX register update" bitfld.long 0x20 0. "ENABLE,MUX register update enable" "0,1" tree.end repeat.end elif (CORENAME()=="CORTEXA55") tree "DMA_MUX_PCIE1" base ad:0x313C0000 group.long 0x0++0x23 line.long 0x0 "MUX_CHANNEL1,MUX channel 1 mapping parameter" hexmask.long.byte 0x0 24.--31. 1. "UPDATED_RD_HDSK_MAPPING,MUX channel 1 read handshaking mapping parameter after DMA updating." hexmask.long.byte 0x0 16.--23. 1. "RD_HDSK_MAPPING,MUX channel 1 read handshaking mapping parameter" hexmask.long.byte 0x0 8.--15. 1. "UPDATED_WR_HDSK_MAPPING,MUX channel 1 write handshaking mapping parameter after DMA updating." hexmask.long.byte 0x0 0.--7. 1. "WR_HDSK_MAPPING,MUX channel 1 write handshaking mapping parameter" line.long 0x4 "MUX_CHANNEL2,MUX channel 2 mapping parameter" hexmask.long.byte 0x4 24.--31. 1. "UPDATED_RD_HDSK_MAPPING,MUX channel 2 read handshaking mapping parameter after DMA updating." hexmask.long.byte 0x4 16.--23. 1. "RD_HDSK_MAPPING,MUX channel 2 read handshaking mapping parameter" hexmask.long.byte 0x4 8.--15. 1. "UPDATED_WR_HDSK_MAPPING,MUX channel 2 write handshaking mapping parameter after DMA updating." hexmask.long.byte 0x4 0.--7. 1. "WR_HDSK_MAPPING,MUX channel 2 write handshaking mapping parameter" line.long 0x8 "MUX_CHANNEL3,MUX channel 3 mapping parameter" hexmask.long.byte 0x8 24.--31. 1. "UPDATED_RD_HDSK_MAPPING,MUX channel 3 read handshaking mapping parameter after DMA updating." hexmask.long.byte 0x8 16.--23. 1. "RD_HDSK_MAPPING,MUX channel 3 read handshaking mapping parameter" hexmask.long.byte 0x8 8.--15. 1. "UPDATED_WR_HDSK_MAPPING,MUX channel 3 write handshaking mapping parameter after DMA updating." hexmask.long.byte 0x8 0.--7. 1. "WR_HDSK_MAPPING,MUX channel 3 write handshaking mapping parameter" line.long 0xC "MUX_CHANNEL4,MUX channel 4 mapping parameter" hexmask.long.byte 0xC 24.--31. 1. "UPDATED_RD_HDSK_MAPPING,MUX channel 4 read handshaking mapping parameter after DMA updating." hexmask.long.byte 0xC 16.--23. 1. "RD_HDSK_MAPPING,MUX channel 4 read handshaking mapping parameter" hexmask.long.byte 0xC 8.--15. 1. "UPDATED_WR_HDSK_MAPPING,MUX channel 4 write handshaking mapping parameter after DMA updating." hexmask.long.byte 0xC 0.--7. 1. "WR_HDSK_MAPPING,MUX channel 4 write handshaking mapping parameter" line.long 0x10 "MUX_CHANNEL5,MUX channel 5 mapping parameter" hexmask.long.byte 0x10 24.--31. 1. "UPDATED_RD_HDSK_MAPPING,MUX channel 5 read handshaking mapping parameter after DMA updating." hexmask.long.byte 0x10 16.--23. 1. "RD_HDSK_MAPPING,MUX channel 5 read handshaking mapping parameter" hexmask.long.byte 0x10 8.--15. 1. "UPDATED_WR_HDSK_MAPPING,MUX channel 5 write handshaking mapping parameter after DMA updating." hexmask.long.byte 0x10 0.--7. 1. "WR_HDSK_MAPPING,MUX channel 5 write handshaking mapping parameter" line.long 0x14 "MUX_CHANNEL6,MUX channel 6 mapping parameter" hexmask.long.byte 0x14 24.--31. 1. "UPDATED_RD_HDSK_MAPPING,MUX channel 6 read handshaking mapping parameter after DMA updating." hexmask.long.byte 0x14 16.--23. 1. "RD_HDSK_MAPPING,MUX channel 6 read handshaking mapping parameter" hexmask.long.byte 0x14 8.--15. 1. "UPDATED_WR_HDSK_MAPPING,MUX channel 6 write handshaking mapping parameter after DMA updating." hexmask.long.byte 0x14 0.--7. 1. "WR_HDSK_MAPPING,MUX channel 6 write handshaking mapping parameter" line.long 0x18 "MUX_CHANNEL7,MUX channel 7 mapping parameter" hexmask.long.byte 0x18 24.--31. 1. "UPDATED_RD_HDSK_MAPPING,MUX channel 7 read handshaking mapping parameter after DMA updating." hexmask.long.byte 0x18 16.--23. 1. "RD_HDSK_MAPPING,MUX channel 7 read handshaking mapping parameter" hexmask.long.byte 0x18 8.--15. 1. "UPDATED_WR_HDSK_MAPPING,MUX channel 7 write handshaking mapping parameter after DMA updating." hexmask.long.byte 0x18 0.--7. 1. "WR_HDSK_MAPPING,MUX channel 7 write handshaking mapping parameter" line.long 0x1C "MUX_CHANNEL8,MUX channel 8 mapping parameter" hexmask.long.byte 0x1C 24.--31. 1. "UPDATED_RD_HDSK_MAPPING,MUX channel 8 read handshaking mapping parameter after DMA updating." hexmask.long.byte 0x1C 16.--23. 1. "RD_HDSK_MAPPING,MUX channel 8 read handshaking mapping parameter" hexmask.long.byte 0x1C 8.--15. 1. "UPDATED_WR_HDSK_MAPPING,MUX channel 8 write handshaking mapping parameter after DMA updating." hexmask.long.byte 0x1C 0.--7. 1. "WR_HDSK_MAPPING,MUX channel 8 write handshaking mapping parameter" line.long 0x20 "MUX_REG_UPDATE,MUX register update" bitfld.long 0x20 0. "ENABLE,MUX register update enable" "0,1" tree.end tree "DMA_MUX_PCIE2" base ad:0x313E0000 group.long 0x0++0x23 line.long 0x0 "MUX_CHANNEL1,MUX channel 1 mapping parameter" hexmask.long.byte 0x0 24.--31. 1. "UPDATED_RD_HDSK_MAPPING,MUX channel 1 read handshaking mapping parameter after DMA updating." hexmask.long.byte 0x0 16.--23. 1. "RD_HDSK_MAPPING,MUX channel 1 read handshaking mapping parameter" hexmask.long.byte 0x0 8.--15. 1. "UPDATED_WR_HDSK_MAPPING,MUX channel 1 write handshaking mapping parameter after DMA updating." hexmask.long.byte 0x0 0.--7. 1. "WR_HDSK_MAPPING,MUX channel 1 write handshaking mapping parameter" line.long 0x4 "MUX_CHANNEL2,MUX channel 2 mapping parameter" hexmask.long.byte 0x4 24.--31. 1. "UPDATED_RD_HDSK_MAPPING,MUX channel 2 read handshaking mapping parameter after DMA updating." hexmask.long.byte 0x4 16.--23. 1. "RD_HDSK_MAPPING,MUX channel 2 read handshaking mapping parameter" hexmask.long.byte 0x4 8.--15. 1. "UPDATED_WR_HDSK_MAPPING,MUX channel 2 write handshaking mapping parameter after DMA updating." hexmask.long.byte 0x4 0.--7. 1. "WR_HDSK_MAPPING,MUX channel 2 write handshaking mapping parameter" line.long 0x8 "MUX_CHANNEL3,MUX channel 3 mapping parameter" hexmask.long.byte 0x8 24.--31. 1. "UPDATED_RD_HDSK_MAPPING,MUX channel 3 read handshaking mapping parameter after DMA updating." hexmask.long.byte 0x8 16.--23. 1. "RD_HDSK_MAPPING,MUX channel 3 read handshaking mapping parameter" hexmask.long.byte 0x8 8.--15. 1. "UPDATED_WR_HDSK_MAPPING,MUX channel 3 write handshaking mapping parameter after DMA updating." hexmask.long.byte 0x8 0.--7. 1. "WR_HDSK_MAPPING,MUX channel 3 write handshaking mapping parameter" line.long 0xC "MUX_CHANNEL4,MUX channel 4 mapping parameter" hexmask.long.byte 0xC 24.--31. 1. "UPDATED_RD_HDSK_MAPPING,MUX channel 4 read handshaking mapping parameter after DMA updating." hexmask.long.byte 0xC 16.--23. 1. "RD_HDSK_MAPPING,MUX channel 4 read handshaking mapping parameter" hexmask.long.byte 0xC 8.--15. 1. "UPDATED_WR_HDSK_MAPPING,MUX channel 4 write handshaking mapping parameter after DMA updating." hexmask.long.byte 0xC 0.--7. 1. "WR_HDSK_MAPPING,MUX channel 4 write handshaking mapping parameter" line.long 0x10 "MUX_CHANNEL5,MUX channel 5 mapping parameter" hexmask.long.byte 0x10 24.--31. 1. "UPDATED_RD_HDSK_MAPPING,MUX channel 5 read handshaking mapping parameter after DMA updating." hexmask.long.byte 0x10 16.--23. 1. "RD_HDSK_MAPPING,MUX channel 5 read handshaking mapping parameter" hexmask.long.byte 0x10 8.--15. 1. "UPDATED_WR_HDSK_MAPPING,MUX channel 5 write handshaking mapping parameter after DMA updating." hexmask.long.byte 0x10 0.--7. 1. "WR_HDSK_MAPPING,MUX channel 5 write handshaking mapping parameter" line.long 0x14 "MUX_CHANNEL6,MUX channel 6 mapping parameter" hexmask.long.byte 0x14 24.--31. 1. "UPDATED_RD_HDSK_MAPPING,MUX channel 6 read handshaking mapping parameter after DMA updating." hexmask.long.byte 0x14 16.--23. 1. "RD_HDSK_MAPPING,MUX channel 6 read handshaking mapping parameter" hexmask.long.byte 0x14 8.--15. 1. "UPDATED_WR_HDSK_MAPPING,MUX channel 6 write handshaking mapping parameter after DMA updating." hexmask.long.byte 0x14 0.--7. 1. "WR_HDSK_MAPPING,MUX channel 6 write handshaking mapping parameter" line.long 0x18 "MUX_CHANNEL7,MUX channel 7 mapping parameter" hexmask.long.byte 0x18 24.--31. 1. "UPDATED_RD_HDSK_MAPPING,MUX channel 7 read handshaking mapping parameter after DMA updating." hexmask.long.byte 0x18 16.--23. 1. "RD_HDSK_MAPPING,MUX channel 7 read handshaking mapping parameter" hexmask.long.byte 0x18 8.--15. 1. "UPDATED_WR_HDSK_MAPPING,MUX channel 7 write handshaking mapping parameter after DMA updating." hexmask.long.byte 0x18 0.--7. 1. "WR_HDSK_MAPPING,MUX channel 7 write handshaking mapping parameter" line.long 0x1C "MUX_CHANNEL8,MUX channel 8 mapping parameter" hexmask.long.byte 0x1C 24.--31. 1. "UPDATED_RD_HDSK_MAPPING,MUX channel 8 read handshaking mapping parameter after DMA updating." hexmask.long.byte 0x1C 16.--23. 1. "RD_HDSK_MAPPING,MUX channel 8 read handshaking mapping parameter" hexmask.long.byte 0x1C 8.--15. 1. "UPDATED_WR_HDSK_MAPPING,MUX channel 8 write handshaking mapping parameter after DMA updating." hexmask.long.byte 0x1C 0.--7. 1. "WR_HDSK_MAPPING,MUX channel 8 write handshaking mapping parameter" line.long 0x20 "MUX_REG_UPDATE,MUX register update" bitfld.long 0x20 0. "ENABLE,MUX register update enable" "0,1" tree.end repeat 8. (increment 1. 1.) (list ad:0x301E0000 ad:0x30440000 ad:0x30450000 ad:0x30460000 ad:0x30470000 ad:0x30480000 ad:0x30490000 ad:0x304A0000) tree "DMA_MUX$1" base $2 group.long 0x0++0x23 line.long 0x0 "MUX_CHANNEL1,MUX channel 1 mapping parameter" hexmask.long.byte 0x0 24.--31. 1. "UPDATED_RD_HDSK_MAPPING,MUX channel 1 read handshaking mapping parameter after DMA updating." hexmask.long.byte 0x0 16.--23. 1. "RD_HDSK_MAPPING,MUX channel 1 read handshaking mapping parameter" hexmask.long.byte 0x0 8.--15. 1. "UPDATED_WR_HDSK_MAPPING,MUX channel 1 write handshaking mapping parameter after DMA updating." hexmask.long.byte 0x0 0.--7. 1. "WR_HDSK_MAPPING,MUX channel 1 write handshaking mapping parameter" line.long 0x4 "MUX_CHANNEL2,MUX channel 2 mapping parameter" hexmask.long.byte 0x4 24.--31. 1. "UPDATED_RD_HDSK_MAPPING,MUX channel 2 read handshaking mapping parameter after DMA updating." hexmask.long.byte 0x4 16.--23. 1. "RD_HDSK_MAPPING,MUX channel 2 read handshaking mapping parameter" hexmask.long.byte 0x4 8.--15. 1. "UPDATED_WR_HDSK_MAPPING,MUX channel 2 write handshaking mapping parameter after DMA updating." hexmask.long.byte 0x4 0.--7. 1. "WR_HDSK_MAPPING,MUX channel 2 write handshaking mapping parameter" line.long 0x8 "MUX_CHANNEL3,MUX channel 3 mapping parameter" hexmask.long.byte 0x8 24.--31. 1. "UPDATED_RD_HDSK_MAPPING,MUX channel 3 read handshaking mapping parameter after DMA updating." hexmask.long.byte 0x8 16.--23. 1. "RD_HDSK_MAPPING,MUX channel 3 read handshaking mapping parameter" hexmask.long.byte 0x8 8.--15. 1. "UPDATED_WR_HDSK_MAPPING,MUX channel 3 write handshaking mapping parameter after DMA updating." hexmask.long.byte 0x8 0.--7. 1. "WR_HDSK_MAPPING,MUX channel 3 write handshaking mapping parameter" line.long 0xC "MUX_CHANNEL4,MUX channel 4 mapping parameter" hexmask.long.byte 0xC 24.--31. 1. "UPDATED_RD_HDSK_MAPPING,MUX channel 4 read handshaking mapping parameter after DMA updating." hexmask.long.byte 0xC 16.--23. 1. "RD_HDSK_MAPPING,MUX channel 4 read handshaking mapping parameter" hexmask.long.byte 0xC 8.--15. 1. "UPDATED_WR_HDSK_MAPPING,MUX channel 4 write handshaking mapping parameter after DMA updating." hexmask.long.byte 0xC 0.--7. 1. "WR_HDSK_MAPPING,MUX channel 4 write handshaking mapping parameter" line.long 0x10 "MUX_CHANNEL5,MUX channel 5 mapping parameter" hexmask.long.byte 0x10 24.--31. 1. "UPDATED_RD_HDSK_MAPPING,MUX channel 5 read handshaking mapping parameter after DMA updating." hexmask.long.byte 0x10 16.--23. 1. "RD_HDSK_MAPPING,MUX channel 5 read handshaking mapping parameter" hexmask.long.byte 0x10 8.--15. 1. "UPDATED_WR_HDSK_MAPPING,MUX channel 5 write handshaking mapping parameter after DMA updating." hexmask.long.byte 0x10 0.--7. 1. "WR_HDSK_MAPPING,MUX channel 5 write handshaking mapping parameter" line.long 0x14 "MUX_CHANNEL6,MUX channel 6 mapping parameter" hexmask.long.byte 0x14 24.--31. 1. "UPDATED_RD_HDSK_MAPPING,MUX channel 6 read handshaking mapping parameter after DMA updating." hexmask.long.byte 0x14 16.--23. 1. "RD_HDSK_MAPPING,MUX channel 6 read handshaking mapping parameter" hexmask.long.byte 0x14 8.--15. 1. "UPDATED_WR_HDSK_MAPPING,MUX channel 6 write handshaking mapping parameter after DMA updating." hexmask.long.byte 0x14 0.--7. 1. "WR_HDSK_MAPPING,MUX channel 6 write handshaking mapping parameter" line.long 0x18 "MUX_CHANNEL7,MUX channel 7 mapping parameter" hexmask.long.byte 0x18 24.--31. 1. "UPDATED_RD_HDSK_MAPPING,MUX channel 7 read handshaking mapping parameter after DMA updating." hexmask.long.byte 0x18 16.--23. 1. "RD_HDSK_MAPPING,MUX channel 7 read handshaking mapping parameter" hexmask.long.byte 0x18 8.--15. 1. "UPDATED_WR_HDSK_MAPPING,MUX channel 7 write handshaking mapping parameter after DMA updating." hexmask.long.byte 0x18 0.--7. 1. "WR_HDSK_MAPPING,MUX channel 7 write handshaking mapping parameter" line.long 0x1C "MUX_CHANNEL8,MUX channel 8 mapping parameter" hexmask.long.byte 0x1C 24.--31. 1. "UPDATED_RD_HDSK_MAPPING,MUX channel 8 read handshaking mapping parameter after DMA updating." hexmask.long.byte 0x1C 16.--23. 1. "RD_HDSK_MAPPING,MUX channel 8 read handshaking mapping parameter" hexmask.long.byte 0x1C 8.--15. 1. "UPDATED_WR_HDSK_MAPPING,MUX channel 8 write handshaking mapping parameter after DMA updating." hexmask.long.byte 0x1C 0.--7. 1. "WR_HDSK_MAPPING,MUX channel 8 write handshaking mapping parameter" line.long 0x20 "MUX_REG_UPDATE,MUX register update" bitfld.long 0x20 0. "ENABLE,MUX register update enable" "0,1" tree.end repeat.end endif tree.end tree "EFUSEC (Fuse Controller)" sif (CORENAME()=="CORTEXR5F") base ad:0xF0010000 group.long 0x0++0xB line.long 0x0 "FUSE_CTRL,This register provides controll setting and save status for fuse opeation" hexmask.long.word 0x0 16.--31. 1. "PROG_KEY,Write special key to enable fuse program operation." bitfld.long 0x0 12. "ERROR,It indicates fuse operation is failed when set." "0,1" rbitfld.long 0x0 11. "BUSY,It indicates fuse operation is not complete when set" "0,1" bitfld.long 0x0 9.--10. "AT,It is used to assert AT1 and AT0 pin of fuse macro in Test row and column fuse programming and reading." "0,1,2,3" newline bitfld.long 0x0 8. "MARGIN,It is used to assert MR pin of fuse macro in fuse margin reading." "0,1" hexmask.long.byte 0x0 0.--7. 1. "ADDR,Fuse program and read access address register. In normal program and read ADDR[7:0] is used to select one of 256 fuse words. In test program mode ADDR[6:0] is used to select which bit is programmed in selected test row. In test read mode.." line.long 0x4 "PROG_DATA,This register is used to provide programming data." hexmask.long 0x4 0.--31. 1. "DATA,fuse program data" line.long 0x8 "FUSE_TRIG,Fuse operation trigger register. It is in conjuction with FUSE_CTRL and FUSE_DATA register to trigger fuse operation." bitfld.long 0x8 4. "LOAD,After set fuse_ctrl wil reload fuse into shadow registers in order. It will be clear after reload is complete." "0,1" bitfld.long 0x8 3. "TPROG,After set it will trigger fuse program operation for test row/column fuse word which address is assigned by ADDR in FUSE_CTRL register. It will be clear after operation is complete" "0,1" bitfld.long 0x8 2. "PROG,After set it will trigger fuse program operation for fuse word which address is assigned by ADDR in FUSE_CTRL register. It will be clear after operation is complete" "0,1" bitfld.long 0x8 1. "TREAD,After set it will trigger fuse read operation for test row/column fuse word which address is assigned by ADDR in FUSE_CTRL register. It will be clear after operation is complete" "0,1" newline bitfld.long 0x8 0. "READ,After set it will trigger fuse read oeration for fuse word which address is assigned by ADDR in FUSE_CTRL register. It will be clear after operation is complete." "0,1" rgroup.long 0xC++0x3 line.long 0x0 "READ_FUSE_DATA,This register is used to save fuse data read from fuse macro." hexmask.long 0x0 0.--31. 1. "DATA,The fuse data read from fuse macro." group.long 0x10++0x1B line.long 0x0 "FUSE_TIMING_0,Fuse timing register 0. It provides timing configuration for fuse programming and reading." hexmask.long.byte 0x0 24.--31. 1. "PD_SETUP_CNT,Specifiy setup time from PD to PS or PD to CS" hexmask.long.byte 0x0 18.--23. 1. "PD_HOLD_CNT,Specifiy hold time from PD to PS or PD to CS" hexmask.long.byte 0x0 13.--17. 1. "PS_SETUP_CNT,Specifiy setup time from PS to other signals." hexmask.long.byte 0x0 8.--12. 1. "PS_HOLD_CNT,Specifiy hold time from PS to other signals." hexmask.long.byte 0x0 4.--7. 1. "CS_SETUP_CNT,Specifiy setup time to address signals." newline hexmask.long.byte 0x0 0.--3. 1. "CS_HOLD_CNT,Specifiy hold time to address signals." line.long 0x4 "FUSE_TIMING_1,Fuse timing register1. It provides timing configuration for fuse programming and reading." hexmask.long.byte 0x4 24.--31. 1. "RD_TO_PROG_CNT,Specify timing interval between fuse reading and programming" hexmask.long.byte 0x4 18.--23. 1. "MR_RD_STRB_CNT,Specify strobe signal width in fuse margin reading" hexmask.long.byte 0x4 12.--17. 1. "RD_STRB_CNT,Specify strobe signal width in fuse normal reading" hexmask.long.word 0x4 0.--11. 1. "PROG_STRB_CNT,Sepcify strobe signal width in fuse programming." line.long 0x8 "CHECK_FUSE_ADDR,It indicates which fuse word need be checked. Need set between188~255" hexmask.long.byte 0x8 0.--7. 1. "ADDR,Indicate which fuse word need be checked. Need set between 188~255" line.long 0xC "SEMA_LOCK,It provides semaphore lock for SE and AP access" rbitfld.long 0xC 2. "AP_LOCK,This bit shows that LOCK bit is set by AP APB bus." "0,1" rbitfld.long 0xC 1. "SE_LOCK,This bit shows that LOCK bit is set by SE APB bus" "0,1" bitfld.long 0xC 0. "LOCK,When this bit is set by SE or AP APB bus Other APB bus can not access register 0x0~0x18 and clear this bit." "0,1" line.long 0x10 "INT_STA,Interrupt status register" bitfld.long 0x10 3. "FATAL,It reports ECC correction logic error." "0,1" bitfld.long 0x10 2. "MUL_ERR,Indicate ECC mulitple bit error happen" "0,1" bitfld.long 0x10 1. "RED_ERR,Indicate redundancy fuse has been corrected" "0,1" bitfld.long 0x10 0. "SIG_ERR,Indicate ECC single bit correction happens" "0,1" line.long 0x14 "INT_STA_EN,Interrupt status enable" bitfld.long 0x14 3. "FATAL,ECC correction logic error interrupt status enable" "0,1" bitfld.long 0x14 2. "MUL_ERR,ECC multiple bit errors interrupt status enable" "0,1" bitfld.long 0x14 1. "RED_ERR,redundancy fuse correction interrupt status enable" "0,1" bitfld.long 0x14 0. "SIG_ERR,ECC single bit error interrupt status enable" "0,1" line.long 0x18 "INT_SIG_EN,Interrupt signal enable" bitfld.long 0x18 3. "FATAL,ECC correction logic error interrupt signal enable" "0,1" bitfld.long 0x18 2. "MUL_ERR,Multiple fuse bits error interrupt signal enable" "0,1" bitfld.long 0x18 1. "RED_ERR,Redundancy fuse correction interrupt signal enable" "0,1" bitfld.long 0x18 0. "SIG_ERR,ECC single error bit interrupt signal enable" "0,1" repeat 5. (list 0x0 0x1 0x2 0x3 0x4 )(list 0x0 0x4 0x8 0xC 0x10 ) group.long ($2+0x100)++0x3 line.long 0x0 "ECC_SIG_ERROR$1,Indicate single bit error in ecc word0~31" bitfld.long 0x0 31. "ERR_31,ecc fuse word single bit error" "0,1" bitfld.long 0x0 30. "ERR_30,ecc fuse word single bit error" "0,1" bitfld.long 0x0 29. "ERR_29,ecc fuse word single bit error" "0,1" bitfld.long 0x0 28. "ERR_28,ecc fuse word single bit error" "0,1" bitfld.long 0x0 27. "ERR_27,ecc fuse word single bit error" "0,1" newline bitfld.long 0x0 26. "ERR_26,ecc fuse word single bit error" "0,1" bitfld.long 0x0 25. "ERR_25,ecc fuse word single bit error" "0,1" bitfld.long 0x0 24. "ERR_24,ecc fuse word single bit error" "0,1" bitfld.long 0x0 23. "ERR_23,ecc fuse word single bit error" "0,1" bitfld.long 0x0 22. "ERR_22,ecc fuse word single bit error" "0,1" newline bitfld.long 0x0 21. "ERR_21,ecc fuse word single bit error" "0,1" bitfld.long 0x0 20. "ERR_20,ecc fuse word single bit error" "0,1" bitfld.long 0x0 19. "ERR_19,ecc fuse word single bit error" "0,1" bitfld.long 0x0 18. "ERR_18,ecc fuse word single bit error" "0,1" bitfld.long 0x0 17. "ERR_17,ecc fuse word single bit error" "0,1" newline bitfld.long 0x0 16. "ERR_16,ecc fuse word single bit error" "0,1" bitfld.long 0x0 15. "ERR_15,ecc fuse word single bit error" "0,1" bitfld.long 0x0 14. "ERR_14,ecc fuse word single bit error" "0,1" bitfld.long 0x0 13. "ERR_13,ecc fuse word single bit error" "0,1" bitfld.long 0x0 12. "ERR_12,ecc fuse word single bit error" "0,1" newline bitfld.long 0x0 11. "ERR_11,ecc fuse word single bit error" "0,1" bitfld.long 0x0 10. "ERR_10,ecc fuse word single bit error" "0,1" bitfld.long 0x0 9. "ERR_9,ecc fuse word single bit error" "0,1" bitfld.long 0x0 8. "ERR_8,ecc fuse word single bit error" "0,1" bitfld.long 0x0 7. "ERR_7,ecc fuse word single bit error" "0,1" newline bitfld.long 0x0 6. "ERR_6,ecc fuse word single bit error" "0,1" bitfld.long 0x0 5. "ERR_5,ecc fuse word single bit error" "0,1" bitfld.long 0x0 4. "ERR_4,ecc fuse word single bit error" "0,1" bitfld.long 0x0 3. "ERR_3,ecc fuse word single bit error" "0,1" bitfld.long 0x0 2. "ERR_2,ecc fuse word single bit error" "0,1" newline bitfld.long 0x0 1. "ERR_1,ecc fuse word single bit error" "0,1" bitfld.long 0x0 0. "ERR_0,ecc fuse word single bit error" "0,1" repeat.end repeat 5. (list 0x0 0x1 0x2 0x3 0x4 )(list 0x0 0x4 0x8 0xC 0x10 ) group.long ($2+0x114)++0x3 line.long 0x0 "ECC_MUL_ERROR$1,Indicate mulltiple bit error in ecc word0~31" bitfld.long 0x0 31. "ERR_31,ecc fuse word multiple bits error" "0,1" bitfld.long 0x0 30. "ERR_30,ecc fuse word multiple bits error" "0,1" bitfld.long 0x0 29. "ERR_29,ecc fuse word multiple bits error" "0,1" bitfld.long 0x0 28. "ERR_28,ecc fuse word multiple bits error" "0,1" bitfld.long 0x0 27. "ERR_27,ecc fuse word multiple bits error" "0,1" newline bitfld.long 0x0 26. "ERR_26,ecc fuse word multiple bits error" "0,1" bitfld.long 0x0 25. "ERR_25,ecc fuse word multiple bits error" "0,1" bitfld.long 0x0 24. "ERR_24,ecc fuse word multiple bits error" "0,1" bitfld.long 0x0 23. "ERR_23,ecc fuse word multiple bits error" "0,1" bitfld.long 0x0 22. "ERR_22,ecc fuse word multiple bits error" "0,1" newline bitfld.long 0x0 21. "ERR_21,ecc fuse word multiple bits error" "0,1" bitfld.long 0x0 20. "ERR_20,ecc fuse word multiple bits error" "0,1" bitfld.long 0x0 19. "ERR_19,ecc fuse word multiple bits error" "0,1" bitfld.long 0x0 18. "ERR_18,ecc fuse word multiple bits error" "0,1" bitfld.long 0x0 17. "ERR_17,ecc fuse word multiple bits error" "0,1" newline bitfld.long 0x0 16. "ERR_16,ecc fuse word multiple bits error" "0,1" bitfld.long 0x0 15. "ERR_15,ecc fuse word multiple bits error" "0,1" bitfld.long 0x0 14. "ERR_14,ecc fuse word multiple bits error" "0,1" bitfld.long 0x0 13. "ERR_13,ecc fuse word multiple bits error" "0,1" bitfld.long 0x0 12. "ERR_12,ecc fuse word multiple bits error" "0,1" newline bitfld.long 0x0 11. "ERR_11,ecc fuse word multiple bits error" "0,1" bitfld.long 0x0 10. "ERR_10,ecc fuse word multiple bits error" "0,1" bitfld.long 0x0 9. "ERR_9,ecc fuse word multiple bits error" "0,1" bitfld.long 0x0 8. "ERR_8,ecc fuse word multiple bits error" "0,1" bitfld.long 0x0 7. "ERR_7,ecc fuse word multiple bits error" "0,1" newline bitfld.long 0x0 6. "ERR_6,ecc fuse word multiple bits error" "0,1" bitfld.long 0x0 5. "ERR_5,ecc fuse word multiple bits error" "0,1" bitfld.long 0x0 4. "ERR_4,ecc fuse word multiple bits error" "0,1" bitfld.long 0x0 3. "ERR_3,ecc fuse word multiple bits error" "0,1" bitfld.long 0x0 2. "ERR_2,ecc fuse word multiple bits error" "0,1" newline bitfld.long 0x0 1. "ERR_1,ecc fuse word multiple bits error" "0,1" bitfld.long 0x0 0. "ERR_0,ecc fuse word multiple bits error" "0,1" repeat.end group.long 0x128++0x7 line.long 0x0 "RED_ERROR0,Indicate error in redundancy word0~19" bitfld.long 0x0 19. "ERR_19,Redundancy fuse word error" "0,1" bitfld.long 0x0 18. "ERR_18,Redundancy fuse word error" "0,1" bitfld.long 0x0 17. "ERR_17,Redundancy fuse word error" "0,1" bitfld.long 0x0 16. "ERR_16,Redundancy fuse word error" "0,1" newline bitfld.long 0x0 15. "ERR_15,Redundancy fuse word error" "0,1" bitfld.long 0x0 14. "ERR_14,Redundancy fuse word error" "0,1" bitfld.long 0x0 13. "ERR_13,Redundancy fuse word error" "0,1" bitfld.long 0x0 12. "ERR_12,Redundancy fuse word error" "0,1" bitfld.long 0x0 11. "ERR_11,Redundancy fuse word error" "0,1" newline bitfld.long 0x0 10. "ERR_10,Redundancy fuse word error" "0,1" bitfld.long 0x0 9. "ERR_9,Redundancy fuse word error" "0,1" bitfld.long 0x0 8. "ERR_8,Redundancy fuse word error" "0,1" bitfld.long 0x0 7. "ERR_7,Redundancy fuse word error" "0,1" bitfld.long 0x0 6. "ERR_6,Redundancy fuse word error" "0,1" newline bitfld.long 0x0 5. "ERR_5,Redundancy fuse word error" "0,1" bitfld.long 0x0 4. "ERR_4,Redundancy fuse word error" "0,1" bitfld.long 0x0 3. "ERR_3,Redundancy fuse word error" "0,1" bitfld.long 0x0 2. "ERR_2,Redundancy fuse word error" "0,1" bitfld.long 0x0 1. "ERR_1,Redundancy fuse word error" "0,1" newline bitfld.long 0x0 0. "ERR_0,Redundancy fuse word error" "0,1" line.long 0x4 "LOCK_RED_ERROR,Indicate error in lock fuse word0~7" bitfld.long 0x4 7. "ERR_7,Redundancy fuse word error" "0,1" bitfld.long 0x4 6. "ERR_6,Redundancy fuse word error" "0,1" bitfld.long 0x4 5. "ERR_5,Redundancy fuse word error" "0,1" bitfld.long 0x4 4. "ERR_4,Redundancy fuse word error" "0,1" newline bitfld.long 0x4 3. "ERR_3,Redundancy fuse word error" "0,1" bitfld.long 0x4 2. "ERR_2,Redundancy fuse word error" "0,1" bitfld.long 0x4 1. "ERR_1,Redundancy fuse word error" "0,1" bitfld.long 0x4 0. "ERR_0,Redundancy fuse word error" "0,1" repeat 4. (list 0x0 0x1 0x2 0x3 )(list 0x0 0x8 0x10 0x18 ) rgroup.long ($2+0x200)++0x3 line.long 0x0 "ECC_DATA_CORR_$1,indictor which data bit has been corrected." hexmask.long 0x0 0.--31. 1. "DATA,Indicate which data bit has been corrected" repeat.end repeat 4. (list 0x0 0x1 0x2 0x3 )(list 0x0 0x8 0x10 0x18 ) rgroup.long ($2+0x204)++0x3 line.long 0x0 "ECC_CORR_$1,Indicate which ecc bit is not correct" hexmask.long.byte 0x0 0.--6. 1. "ECC,Indicate which ecc bit has been corrected." repeat.end rgroup.long 0x220++0x7 line.long 0x0 "RED_DATA_CORR,Indicate which bit in redudancy bits are not corrected." hexmask.long 0x0 0.--31. 1. "DATA,Indicate which redundancy data bit are not correct." line.long 0x4 "RED_CORR,Indicate which redundancy data bit are not correct." hexmask.long 0x4 0.--31. 1. "RED,Indicate which redundancy data bit are not correct." group.long 0x300++0x27 line.long 0x0 "SE_GLB_LOCK,Global setting for SE bank lock. Sticky register." bitfld.long 0x0 0. "SE_LOCK,Lock SE lock register bits" "0,1" line.long 0x4 "SE_BANK_LOCK0,Bank0~7 lock bit for SE. Sticky register." bitfld.long 0x4 31. "HLOCK7,Lock for HW key bus." "0,1" bitfld.long 0x4 30. "OLOCK7,Lock for write shadow registers." "0,1" bitfld.long 0x4 29. "RLOCK7,Lock for read fuse and shadow register." "0,1" bitfld.long 0x4 28. "PLOCK7,Lock for program fuse." "0,1" bitfld.long 0x4 27. "HLOCK6,Lock for HW key bus." "0,1" newline bitfld.long 0x4 26. "OLOCK6,Lock for write shadow registers." "0,1" bitfld.long 0x4 25. "RLOCK6,Lock for read fuse and shadow register." "0,1" bitfld.long 0x4 24. "PLOCK6,Lock for program fuse." "0,1" bitfld.long 0x4 23. "HLOCK5,Lock for HW key bus." "0,1" bitfld.long 0x4 22. "OLOCK5,Lock for write shadow registers." "0,1" newline bitfld.long 0x4 21. "RLOCK5,Lock for read fuse and shadow register." "0,1" bitfld.long 0x4 20. "PLOCK5,Lock for program fuse." "0,1" bitfld.long 0x4 19. "HLOCK4,Lock for HW key bus." "0,1" bitfld.long 0x4 18. "OLOCK4,Lock for write shadow registers." "0,1" bitfld.long 0x4 17. "RLOCK4,Lock for read fuse and shadow register." "0,1" newline bitfld.long 0x4 16. "PLOCK4,Lock for program fuse." "0,1" bitfld.long 0x4 15. "HLOCK3,Lock for HW key bus." "0,1" bitfld.long 0x4 14. "OLOCK3,Lock for write shadow registers." "0,1" bitfld.long 0x4 13. "RLOCK3,Lock for read fuse and shadow register." "0,1" bitfld.long 0x4 12. "PLOCK3,Lock for program fuse." "0,1" newline bitfld.long 0x4 11. "HLOCK2,Lock for HW key bus." "0,1" bitfld.long 0x4 10. "OLOCK2,Lock for write shadow registers." "0,1" bitfld.long 0x4 9. "RLOCK2,Lock for read fuse and shadow register." "0,1" bitfld.long 0x4 8. "PLOCK2,Lock for program fuse." "0,1" bitfld.long 0x4 7. "HLOCK1,Lock for HW key bus." "0,1" newline bitfld.long 0x4 6. "OLOCK1,Lock for write shadow registers." "0,1" bitfld.long 0x4 5. "RLOCK1,Lock for read fuse and shadow register." "0,1" bitfld.long 0x4 4. "PLOCK1,Lock for program fuse." "0,1" bitfld.long 0x4 3. "HLOCK0,Lock for HW key bus." "0,1" bitfld.long 0x4 2. "OLOCK0,Lock for write shadow registers." "0,1" newline bitfld.long 0x4 1. "RLOCK0,Lock for read fuse and shadow register." "0,1" bitfld.long 0x4 0. "PLOCK0,Lock for program fuse." "0,1" line.long 0x8 "SE_BANK_LOCK1,Bank8~15 lock bit for SE. Sticky register." bitfld.long 0x8 31. "HLOCK7,Lock for HW key bus." "0,1" bitfld.long 0x8 30. "OLOCK7,Lock for write shadow registers." "0,1" bitfld.long 0x8 29. "RLOCK7,Lock for read fuse and shadow register." "0,1" bitfld.long 0x8 28. "PLOCK7,Lock for program fuse." "0,1" bitfld.long 0x8 27. "HLOCK6,Lock for HW key bus." "0,1" newline bitfld.long 0x8 26. "OLOCK6,Lock for write shadow registers." "0,1" bitfld.long 0x8 25. "RLOCK6,Lock for read fuse and shadow register." "0,1" bitfld.long 0x8 24. "PLOCK6,Lock for program fuse." "0,1" bitfld.long 0x8 23. "HLOCK5,Lock for HW key bus." "0,1" bitfld.long 0x8 22. "OLOCK5,Lock for write shadow registers." "0,1" newline bitfld.long 0x8 21. "RLOCK5,Lock for read fuse and shadow register." "0,1" bitfld.long 0x8 20. "PLOCK5,Lock for program fuse." "0,1" bitfld.long 0x8 19. "HLOCK4,Lock for HW key bus." "0,1" bitfld.long 0x8 18. "OLOCK4,Lock for write shadow registers." "0,1" bitfld.long 0x8 17. "RLOCK4,Lock for read fuse and shadow register." "0,1" newline bitfld.long 0x8 16. "PLOCK4,Lock for program fuse." "0,1" bitfld.long 0x8 15. "HLOCK3,Lock for HW key bus." "0,1" bitfld.long 0x8 14. "OLOCK3,Lock for write shadow registers." "0,1" bitfld.long 0x8 13. "RLOCK3,Lock for read fuse and shadow register." "0,1" bitfld.long 0x8 12. "PLOCK3,Lock for program fuse." "0,1" newline bitfld.long 0x8 11. "HLOCK2,Lock for HW key bus." "0,1" bitfld.long 0x8 10. "OLOCK2,Lock for write shadow registers." "0,1" bitfld.long 0x8 9. "RLOCK2,Lock for read fuse and shadow register." "0,1" bitfld.long 0x8 8. "PLOCK2,Lock for program fuse." "0,1" bitfld.long 0x8 7. "HLOCK1,Lock for HW key bus." "0,1" newline bitfld.long 0x8 6. "OLOCK1,Lock for write shadow registers." "0,1" bitfld.long 0x8 5. "RLOCK1,Lock for read fuse and shadow register." "0,1" bitfld.long 0x8 4. "PLOCK1,Lock for program fuse." "0,1" bitfld.long 0x8 3. "HLOCK0,Lock for HW key bus." "0,1" bitfld.long 0x8 2. "OLOCK0,Lock for write shadow registers." "0,1" newline bitfld.long 0x8 1. "RLOCK0,Lock for read fuse and shadow register." "0,1" bitfld.long 0x8 0. "PLOCK0,Lock for program fuse." "0,1" line.long 0xC "SE_BANK_LOCK2,Bank16~23 lock bit for SE. Sticky register." bitfld.long 0xC 31. "HLOCK7,Lock for HW key bus." "0,1" bitfld.long 0xC 30. "OLOCK7,Lock for write shadow registers." "0,1" bitfld.long 0xC 29. "RLOCK7,Lock for read fuse and shadow register." "0,1" bitfld.long 0xC 28. "PLOCK7,Lock for program fuse." "0,1" bitfld.long 0xC 27. "HLOCK6,Lock for HW key bus." "0,1" newline bitfld.long 0xC 26. "OLOCK6,Lock for write shadow registers." "0,1" bitfld.long 0xC 25. "RLOCK6,Lock for read fuse and shadow register." "0,1" bitfld.long 0xC 24. "PLOCK6,Lock for program fuse." "0,1" bitfld.long 0xC 23. "HLOCK5,Lock for HW key bus." "0,1" bitfld.long 0xC 22. "OLOCK5,Lock for write shadow registers." "0,1" newline bitfld.long 0xC 21. "RLOCK5,Lock for read fuse and shadow register." "0,1" bitfld.long 0xC 20. "PLOCK5,Lock for program fuse." "0,1" bitfld.long 0xC 19. "HLOCK4,Lock for HW key bus." "0,1" bitfld.long 0xC 18. "OLOCK4,Lock for write shadow registers." "0,1" bitfld.long 0xC 17. "RLOCK4,Lock for read fuse and shadow register." "0,1" newline bitfld.long 0xC 16. "PLOCK4,Lock for program fuse." "0,1" bitfld.long 0xC 15. "HLOCK3,Lock for HW key bus." "0,1" bitfld.long 0xC 14. "OLOCK3,Lock for write shadow registers." "0,1" bitfld.long 0xC 13. "RLOCK3,Lock for read fuse and shadow register." "0,1" bitfld.long 0xC 12. "PLOCK3,Lock for program fuse." "0,1" newline bitfld.long 0xC 11. "HLOCK2,Lock for HW key bus." "0,1" bitfld.long 0xC 10. "OLOCK2,Lock for write shadow registers." "0,1" bitfld.long 0xC 9. "RLOCK2,Lock for read fuse and shadow register." "0,1" bitfld.long 0xC 8. "PLOCK2,Lock for program fuse." "0,1" bitfld.long 0xC 7. "HLOCK1,Lock for HW key bus." "0,1" newline bitfld.long 0xC 6. "OLOCK1,Lock for write shadow registers." "0,1" bitfld.long 0xC 5. "RLOCK1,Lock for read fuse and shadow register." "0,1" bitfld.long 0xC 4. "PLOCK1,Lock for program fuse." "0,1" bitfld.long 0xC 3. "HLOCK0,Lock for HW key bus." "0,1" bitfld.long 0xC 2. "OLOCK0,Lock for write shadow registers." "0,1" newline bitfld.long 0xC 1. "RLOCK0,Lock for read fuse and shadow register." "0,1" bitfld.long 0xC 0. "PLOCK0,Lock for program fuse." "0,1" line.long 0x10 "SE_BANK_LOCK3,Bank24~31 lock bit for SE. Sticky register." bitfld.long 0x10 31. "HLOCK7,Lock for HW key bus." "0,1" bitfld.long 0x10 30. "OLOCK7,Lock for write shadow registers." "0,1" bitfld.long 0x10 29. "RLOCK7,Lock for read fuse and shadow register." "0,1" bitfld.long 0x10 28. "PLOCK7,Lock for program fuse." "0,1" bitfld.long 0x10 27. "HLOCK6,Lock for HW key bus." "0,1" newline bitfld.long 0x10 26. "OLOCK6,Lock for write shadow registers." "0,1" bitfld.long 0x10 25. "RLOCK6,Lock for read fuse and shadow register." "0,1" bitfld.long 0x10 24. "PLOCK6,Lock for program fuse." "0,1" bitfld.long 0x10 23. "HLOCK5,Lock for HW key bus." "0,1" bitfld.long 0x10 22. "OLOCK5,Lock for write shadow registers." "0,1" newline bitfld.long 0x10 21. "RLOCK5,Lock for read fuse and shadow register." "0,1" bitfld.long 0x10 20. "PLOCK5,Lock for program fuse." "0,1" bitfld.long 0x10 19. "HLOCK4,Lock for HW key bus." "0,1" bitfld.long 0x10 18. "OLOCK4,Lock for write shadow registers." "0,1" bitfld.long 0x10 17. "RLOCK4,Lock for read fuse and shadow register." "0,1" newline bitfld.long 0x10 16. "PLOCK4,Lock for program fuse." "0,1" bitfld.long 0x10 15. "HLOCK3,Lock for HW key bus." "0,1" bitfld.long 0x10 14. "OLOCK3,Lock for write shadow registers." "0,1" bitfld.long 0x10 13. "RLOCK3,Lock for read fuse and shadow register." "0,1" bitfld.long 0x10 12. "PLOCK3,Lock for program fuse." "0,1" newline bitfld.long 0x10 11. "HLOCK2,Lock for HW key bus." "0,1" bitfld.long 0x10 10. "OLOCK2,Lock for write shadow registers." "0,1" bitfld.long 0x10 9. "RLOCK2,Lock for read fuse and shadow register." "0,1" bitfld.long 0x10 8. "PLOCK2,Lock for program fuse." "0,1" bitfld.long 0x10 7. "HLOCK1,Lock for HW key bus." "0,1" newline bitfld.long 0x10 6. "OLOCK1,Lock for write shadow registers." "0,1" bitfld.long 0x10 5. "RLOCK1,Lock for read fuse and shadow register." "0,1" bitfld.long 0x10 4. "PLOCK1,Lock for program fuse." "0,1" bitfld.long 0x10 3. "HLOCK0,Lock for HW key bus." "0,1" bitfld.long 0x10 2. "OLOCK0,Lock for write shadow registers." "0,1" newline bitfld.long 0x10 1. "RLOCK0,Lock for read fuse and shadow register." "0,1" bitfld.long 0x10 0. "PLOCK0,Lock for program fuse." "0,1" line.long 0x14 "AP_GLB_LOCK,Global setting for AP bank lock. Sticky register." bitfld.long 0x14 0. "AP_LOCK,Lock AP lock register bits." "0,1" line.long 0x18 "AP_BANK_LOCK0,Bank0~7 lock bit for AP. Sticky register." bitfld.long 0x18 31. "HLOCK7,Lock for HW key bus." "0,1" bitfld.long 0x18 30. "OLOCK7,Lock for write shadow registers." "0,1" bitfld.long 0x18 29. "RLOCK7,Lock for read fuse and shadow register." "0,1" bitfld.long 0x18 28. "PLOCK7,Lock for program fuse." "0,1" bitfld.long 0x18 27. "HLOCK6,Lock for HW key bus." "0,1" newline bitfld.long 0x18 26. "OLOCK6,Lock for write shadow registers." "0,1" bitfld.long 0x18 25. "RLOCK6,Lock for read fuse and shadow register." "0,1" bitfld.long 0x18 24. "PLOCK6,Lock for program fuse." "0,1" bitfld.long 0x18 23. "HLOCK5,Lock for HW key bus." "0,1" bitfld.long 0x18 22. "OLOCK5,Lock for write shadow registers." "0,1" newline bitfld.long 0x18 21. "RLOCK5,Lock for read fuse and shadow register." "0,1" bitfld.long 0x18 20. "PLOCK5,Lock for program fuse." "0,1" bitfld.long 0x18 19. "HLOCK4,Lock for HW key bus." "0,1" bitfld.long 0x18 18. "OLOCK4,Lock for write shadow registers." "0,1" bitfld.long 0x18 17. "RLOCK4,Lock for read fuse and shadow register." "0,1" newline bitfld.long 0x18 16. "PLOCK4,Lock for program fuse." "0,1" bitfld.long 0x18 15. "HLOCK3,Lock for HW key bus." "0,1" bitfld.long 0x18 14. "OLOCK3,Lock for write shadow registers." "0,1" bitfld.long 0x18 13. "RLOCK3,Lock for read fuse and shadow register." "0,1" bitfld.long 0x18 12. "PLOCK3,Lock for program fuse." "0,1" newline bitfld.long 0x18 11. "HLOCK2,Lock for HW key bus." "0,1" bitfld.long 0x18 10. "OLOCK2,Lock for write shadow registers." "0,1" bitfld.long 0x18 9. "RLOCK2,Lock for read fuse and shadow register." "0,1" bitfld.long 0x18 8. "PLOCK2,Lock for program fuse." "0,1" bitfld.long 0x18 7. "HLOCK1,Lock for HW key bus." "0,1" newline bitfld.long 0x18 6. "OLOCK1,Lock for write shadow registers." "0,1" bitfld.long 0x18 5. "RLOCK1,Lock for read fuse and shadow register." "0,1" bitfld.long 0x18 4. "PLOCK1,Lock for program fuse." "0,1" bitfld.long 0x18 3. "HLOCK0,Lock for HW key bus." "0,1" bitfld.long 0x18 2. "OLOCK0,Lock for write shadow registers." "0,1" newline bitfld.long 0x18 1. "RLOCK0,Lock for read fuse and shadow register." "0,1" bitfld.long 0x18 0. "PLOCK0,Lock for program fuse." "0,1" line.long 0x1C "AP_BANK_LOCK1,Bank8~15 lock bit for AP. Sticky register." bitfld.long 0x1C 31. "HLOCK7,Lock for HW key bus." "0,1" bitfld.long 0x1C 30. "OLOCK7,Lock for write shadow registers." "0,1" bitfld.long 0x1C 29. "RLOCK7,Lock for read fuse and shadow register." "0,1" bitfld.long 0x1C 28. "PLOCK7,Lock for program fuse." "0,1" bitfld.long 0x1C 27. "HLOCK6,Lock for HW key bus." "0,1" newline bitfld.long 0x1C 26. "OLOCK6,Lock for write shadow registers." "0,1" bitfld.long 0x1C 25. "RLOCK6,Lock for read fuse and shadow register." "0,1" bitfld.long 0x1C 24. "PLOCK6,Lock for program fuse." "0,1" bitfld.long 0x1C 23. "HLOCK5,Lock for HW key bus." "0,1" bitfld.long 0x1C 22. "OLOCK5,Lock for write shadow registers." "0,1" newline bitfld.long 0x1C 21. "RLOCK5,Lock for read fuse and shadow register." "0,1" bitfld.long 0x1C 20. "PLOCK5,Lock for program fuse." "0,1" bitfld.long 0x1C 19. "HLOCK4,Lock for HW key bus." "0,1" bitfld.long 0x1C 18. "OLOCK4,Lock for write shadow registers." "0,1" bitfld.long 0x1C 17. "RLOCK4,Lock for read fuse and shadow register." "0,1" newline bitfld.long 0x1C 16. "PLOCK4,Lock for program fuse." "0,1" bitfld.long 0x1C 15. "HLOCK3,Lock for HW key bus." "0,1" bitfld.long 0x1C 14. "OLOCK3,Lock for write shadow registers." "0,1" bitfld.long 0x1C 13. "RLOCK3,Lock for read fuse and shadow register." "0,1" bitfld.long 0x1C 12. "PLOCK3,Lock for program fuse." "0,1" newline bitfld.long 0x1C 11. "HLOCK2,Lock for HW key bus." "0,1" bitfld.long 0x1C 10. "OLOCK2,Lock for write shadow registers." "0,1" bitfld.long 0x1C 9. "RLOCK2,Lock for read fuse and shadow register." "0,1" bitfld.long 0x1C 8. "PLOCK2,Lock for program fuse." "0,1" bitfld.long 0x1C 7. "HLOCK1,Lock for HW key bus." "0,1" newline bitfld.long 0x1C 6. "OLOCK1,Lock for write shadow registers." "0,1" bitfld.long 0x1C 5. "RLOCK1,Lock for read fuse and shadow register." "0,1" bitfld.long 0x1C 4. "PLOCK1,Lock for program fuse." "0,1" bitfld.long 0x1C 3. "HLOCK0,Lock for HW key bus." "0,1" bitfld.long 0x1C 2. "OLOCK0,Lock for write shadow registers." "0,1" newline bitfld.long 0x1C 1. "RLOCK0,Lock for read fuse and shadow register." "0,1" bitfld.long 0x1C 0. "PLOCK0,Lock for program fuse." "0,1" line.long 0x20 "AP_BANK_LOCK2,Bank16~23 lock bit for AP. Sticky register." bitfld.long 0x20 31. "HLOCK7,Lock for HW key bus." "0,1" bitfld.long 0x20 30. "OLOCK7,Lock for write shadow registers." "0,1" bitfld.long 0x20 29. "RLOCK7,Lock for read fuse and shadow register." "0,1" bitfld.long 0x20 28. "PLOCK7,Lock for program fuse." "0,1" bitfld.long 0x20 27. "HLOCK6,Lock for HW key bus." "0,1" newline bitfld.long 0x20 26. "OLOCK6,Lock for write shadow registers." "0,1" bitfld.long 0x20 25. "RLOCK6,Lock for read fuse and shadow register." "0,1" bitfld.long 0x20 24. "PLOCK6,Lock for program fuse." "0,1" bitfld.long 0x20 23. "HLOCK5,Lock for HW key bus." "0,1" bitfld.long 0x20 22. "OLOCK5,Lock for write shadow registers." "0,1" newline bitfld.long 0x20 21. "RLOCK5,Lock for read fuse and shadow register." "0,1" bitfld.long 0x20 20. "PLOCK5,Lock for program fuse." "0,1" bitfld.long 0x20 19. "HLOCK4,Lock for HW key bus." "0,1" bitfld.long 0x20 18. "OLOCK4,Lock for write shadow registers." "0,1" bitfld.long 0x20 17. "RLOCK4,Lock for read fuse and shadow register." "0,1" newline bitfld.long 0x20 16. "PLOCK4,Lock for program fuse." "0,1" bitfld.long 0x20 15. "HLOCK3,Lock for HW key bus." "0,1" bitfld.long 0x20 14. "OLOCK3,Lock for write shadow registers." "0,1" bitfld.long 0x20 13. "RLOCK3,Lock for read fuse and shadow register." "0,1" bitfld.long 0x20 12. "PLOCK3,Lock for program fuse." "0,1" newline bitfld.long 0x20 11. "HLOCK2,Lock for HW key bus." "0,1" bitfld.long 0x20 10. "OLOCK2,Lock for write shadow registers." "0,1" bitfld.long 0x20 9. "RLOCK2,Lock for read fuse and shadow register." "0,1" bitfld.long 0x20 8. "PLOCK2,Lock for program fuse." "0,1" bitfld.long 0x20 7. "HLOCK1,Lock for HW key bus." "0,1" newline bitfld.long 0x20 6. "OLOCK1,Lock for write shadow registers." "0,1" bitfld.long 0x20 5. "RLOCK1,Lock for read fuse and shadow register." "0,1" bitfld.long 0x20 4. "PLOCK1,Lock for program fuse." "0,1" bitfld.long 0x20 3. "HLOCK0,Lock for HW key bus." "0,1" bitfld.long 0x20 2. "OLOCK0,Lock for write shadow registers." "0,1" newline bitfld.long 0x20 1. "RLOCK0,Lock for read fuse and shadow register." "0,1" bitfld.long 0x20 0. "PLOCK0,Lock for program fuse." "0,1" line.long 0x24 "AP_BANK_LOCK3,Bank24~31 lock bit for AP. Sticky register." bitfld.long 0x24 31. "HLOCK7,Lock for HW key bus." "0,1" bitfld.long 0x24 30. "OLOCK7,Lock for write shadow registers." "0,1" bitfld.long 0x24 29. "RLOCK7,Lock for read fuse and shadow register." "0,1" bitfld.long 0x24 28. "PLOCK7,Lock for program fuse." "0,1" bitfld.long 0x24 27. "HLOCK6,Lock for HW key bus." "0,1" newline bitfld.long 0x24 26. "OLOCK6,Lock for write shadow registers." "0,1" bitfld.long 0x24 25. "RLOCK6,Lock for read fuse and shadow register." "0,1" bitfld.long 0x24 24. "PLOCK6,Lock for program fuse." "0,1" bitfld.long 0x24 23. "HLOCK5,Lock for HW key bus." "0,1" bitfld.long 0x24 22. "OLOCK5,Lock for write shadow registers." "0,1" newline bitfld.long 0x24 21. "RLOCK5,Lock for read fuse and shadow register." "0,1" bitfld.long 0x24 20. "PLOCK5,Lock for program fuse." "0,1" bitfld.long 0x24 19. "HLOCK4,Lock for HW key bus." "0,1" bitfld.long 0x24 18. "OLOCK4,Lock for write shadow registers." "0,1" bitfld.long 0x24 17. "RLOCK4,Lock for read fuse and shadow register." "0,1" newline bitfld.long 0x24 16. "PLOCK4,Lock for program fuse." "0,1" bitfld.long 0x24 15. "HLOCK3,Lock for HW key bus." "0,1" bitfld.long 0x24 14. "OLOCK3,Lock for write shadow registers." "0,1" bitfld.long 0x24 13. "RLOCK3,Lock for read fuse and shadow register." "0,1" bitfld.long 0x24 12. "PLOCK3,Lock for program fuse." "0,1" newline bitfld.long 0x24 11. "HLOCK2,Lock for HW key bus." "0,1" bitfld.long 0x24 10. "OLOCK2,Lock for write shadow registers." "0,1" bitfld.long 0x24 9. "RLOCK2,Lock for read fuse and shadow register." "0,1" bitfld.long 0x24 8. "PLOCK2,Lock for program fuse." "0,1" bitfld.long 0x24 7. "HLOCK1,Lock for HW key bus." "0,1" newline bitfld.long 0x24 6. "OLOCK1,Lock for write shadow registers." "0,1" bitfld.long 0x24 5. "RLOCK1,Lock for read fuse and shadow register." "0,1" bitfld.long 0x24 4. "PLOCK1,Lock for program fuse." "0,1" bitfld.long 0x24 3. "HLOCK0,Lock for HW key bus." "0,1" bitfld.long 0x24 2. "OLOCK0,Lock for write shadow registers." "0,1" newline bitfld.long 0x24 1. "RLOCK0,Lock for read fuse and shadow register." "0,1" bitfld.long 0x24 0. "PLOCK0,Lock for program fuse." "0,1" group.long 0x400++0x17 line.long 0x0 "DATA_INJ_ECC,Error jnjection for read data for ECC mode." hexmask.long 0x0 0.--31. 1. "INJ,Error jnjection for read data." line.long 0x4 "ECC_INJ_ECC,Error injection for ecc code for ECC mode" hexmask.long.byte 0x4 0.--6. 1. "INJ,Error injection for ecc code" line.long 0x8 "DATA_INJ_RED,Error injection for read data for redundancy fuse data" hexmask.long 0x8 0.--31. 1. "INJ,Error injection for redundancy fuse data" line.long 0xC "RED_INJ_RED,Error injection for redundancy fuse data for redundancy mode" hexmask.long 0xC 0.--31. 1. "INJ,Error injection for redundancy fuse data" line.long 0x10 "RDATA_INJ_ECC,Error jnjection for read correction data for ECC mode." hexmask.long 0x10 0.--31. 1. "INJ,Error jnjection for read data." line.long 0x14 "RECC_INJ_ECC_1,Error injection for ecc correction code for ECC mode" hexmask.long.byte 0x14 0.--6. 1. "INJ,Error injection for ecc code" repeat 4. (list 0x0 0x1 0x2 0x3 )(list 0x0 0x4 0x8 0xC ) group.long ($2+0x500)++0x3 line.long 0x0 "SW_STICKY_SE$1,SW sticky register bit for safety domain." bitfld.long 0x0 31. "BIT_31,SW sticky bit" "0,1" bitfld.long 0x0 30. "BIT_30,SW sticky bit" "0,1" bitfld.long 0x0 29. "BIT_29,SW sticky bit" "0,1" bitfld.long 0x0 28. "BIT_28,SW sticky bit" "0,1" bitfld.long 0x0 27. "BIT_27,SW sticky bit" "0,1" newline bitfld.long 0x0 26. "BIT_26,SW sticky bit" "0,1" bitfld.long 0x0 25. "BIT_25,SW sticky bit" "0,1" bitfld.long 0x0 24. "BIT_24,SW sticky bit" "0,1" bitfld.long 0x0 23. "BIT_23,SW sticky bit" "0,1" bitfld.long 0x0 22. "BIT_22,SW sticky bit" "0,1" newline bitfld.long 0x0 21. "BIT_21,SW sticky bit" "0,1" bitfld.long 0x0 20. "BIT_20,SW sticky bit" "0,1" bitfld.long 0x0 19. "BIT_19,SW sticky bit" "0,1" bitfld.long 0x0 18. "BIT_18,SW sticky bit" "0,1" bitfld.long 0x0 17. "BIT_17,SW sticky bit" "0,1" newline bitfld.long 0x0 16. "BIT_16,SW sticky bit" "0,1" bitfld.long 0x0 15. "BIT_15,SW sticky bit" "0,1" bitfld.long 0x0 14. "BIT_14,SW sticky bit" "0,1" bitfld.long 0x0 13. "BIT_13,SW sticky bit" "0,1" bitfld.long 0x0 12. "BIT_12,SW sticky bit" "0,1" newline bitfld.long 0x0 11. "BIT_11,SW sticky bit" "0,1" bitfld.long 0x0 10. "BIT_10,SW sticky bit" "0,1" bitfld.long 0x0 9. "BIT_9,SW sticky bit" "0,1" bitfld.long 0x0 8. "BIT_8,SW sticky bit" "0,1" bitfld.long 0x0 7. "BIT_7,SW sticky bit" "0,1" newline bitfld.long 0x0 6. "BIT_6,SW sticky bit" "0,1" bitfld.long 0x0 5. "BIT_5,SW sticky bit" "0,1" bitfld.long 0x0 4. "BIT_4,SW sticky bit" "0,1" bitfld.long 0x0 3. "BIT_3,SW sticky bit" "0,1" bitfld.long 0x0 2. "BIT_2,SW sticky bit" "0,1" newline bitfld.long 0x0 1. "BIT_1,SW sticky bit" "0,1" bitfld.long 0x0 0. "BIT_0,SW sticky bit" "0,1" repeat.end repeat 4. (list 0x0 0x1 0x2 0x3 )(list 0x0 0x4 0x8 0xC ) group.long ($2+0x510)++0x3 line.long 0x0 "SW_STICKY_AP$1,SW sticky register bit for AP domain." bitfld.long 0x0 31. "BIT_31,SW sticky bit" "0,1" bitfld.long 0x0 30. "BIT_30,SW sticky bit" "0,1" bitfld.long 0x0 29. "BIT_29,SW sticky bit" "0,1" bitfld.long 0x0 28. "BIT_28,SW sticky bit" "0,1" bitfld.long 0x0 27. "BIT_27,SW sticky bit" "0,1" newline bitfld.long 0x0 26. "BIT_26,SW sticky bit" "0,1" bitfld.long 0x0 25. "BIT_25,SW sticky bit" "0,1" bitfld.long 0x0 24. "BIT_24,SW sticky bit" "0,1" bitfld.long 0x0 23. "BIT_23,SW sticky bit" "0,1" bitfld.long 0x0 22. "BIT_22,SW sticky bit" "0,1" newline bitfld.long 0x0 21. "BIT_21,SW sticky bit" "0,1" bitfld.long 0x0 20. "BIT_20,SW sticky bit" "0,1" bitfld.long 0x0 19. "BIT_19,SW sticky bit" "0,1" bitfld.long 0x0 18. "BIT_18,SW sticky bit" "0,1" bitfld.long 0x0 17. "BIT_17,SW sticky bit" "0,1" newline bitfld.long 0x0 16. "BIT_16,SW sticky bit" "0,1" bitfld.long 0x0 15. "BIT_15,SW sticky bit" "0,1" bitfld.long 0x0 14. "BIT_14,SW sticky bit" "0,1" bitfld.long 0x0 13. "BIT_13,SW sticky bit" "0,1" bitfld.long 0x0 12. "BIT_12,SW sticky bit" "0,1" newline bitfld.long 0x0 11. "BIT_11,SW sticky bit" "0,1" bitfld.long 0x0 10. "BIT_10,SW sticky bit" "0,1" bitfld.long 0x0 9. "BIT_9,SW sticky bit" "0,1" bitfld.long 0x0 8. "BIT_8,SW sticky bit" "0,1" bitfld.long 0x0 7. "BIT_7,SW sticky bit" "0,1" newline bitfld.long 0x0 6. "BIT_6,SW sticky bit" "0,1" bitfld.long 0x0 5. "BIT_5,SW sticky bit" "0,1" bitfld.long 0x0 4. "BIT_4,SW sticky bit" "0,1" bitfld.long 0x0 3. "BIT_3,SW sticky bit" "0,1" bitfld.long 0x0 2. "BIT_2,SW sticky bit" "0,1" newline bitfld.long 0x0 1. "BIT_1,SW sticky bit" "0,1" bitfld.long 0x0 0. "BIT_0,SW sticky bit" "0,1" repeat.end repeat 8. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 )(list 0x0 0x4 0x8 0xC 0x10 0x14 0x18 0x1C ) rgroup.long ($2+0x1000)++0x3 line.long 0x0 "LOCK_FUSE_$1,Shadow register for lock fuse word" hexmask.long 0x0 0.--31. 1. "LOCK,shadow register for lock fuse word" repeat.end repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x4 0x8 0xC 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C ) group.long ($2+0x1020)++0x3 line.long 0x0 "FUSE_WORD_$1,Shadow register for fuse word" hexmask.long 0x0 0.--31. 1. "DATA,Shadow register for fuse word" repeat.end repeat 16. (list 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1A 0x1B 0x1C 0x1D 0x1E 0x1F )(list 0x40 0x44 0x48 0x4C 0x50 0x54 0x58 0x5C 0x60 0x64 0x68 0x6C 0x70 0x74 0x78 0x7C ) group.long ($2+0x1020)++0x3 line.long 0x0 "FUSE_WORD_$1,Shadow register for fuse word" hexmask.long 0x0 0.--31. 1. "DATA,Shadow register for fuse word" repeat.end repeat 16. (list 0x20 0x21 0x22 0x23 0x24 0x25 0x26 0x27 0x28 0x29 0x2A 0x2B 0x2C 0x2D 0x2E 0x2F )(list 0x80 0x84 0x88 0x8C 0x90 0x94 0x98 0x9C 0xA0 0xA4 0xA8 0xAC 0xB0 0xB4 0xB8 0xBC ) group.long ($2+0x1020)++0x3 line.long 0x0 "FUSE_WORD_$1,Shadow register for fuse word" hexmask.long 0x0 0.--31. 1. "DATA,Shadow register for fuse word" repeat.end repeat 16. (list 0x30 0x31 0x32 0x33 0x34 0x35 0x36 0x37 0x38 0x39 0x3A 0x3B 0x3C 0x3D 0x3E 0x3F )(list 0xC0 0xC4 0xC8 0xCC 0xD0 0xD4 0xD8 0xDC 0xE0 0xE4 0xE8 0xEC 0xF0 0xF4 0xF8 0xFC ) group.long ($2+0x1020)++0x3 line.long 0x0 "FUSE_WORD_$1,Shadow register for fuse word" hexmask.long 0x0 0.--31. 1. "DATA,Shadow register for fuse word" repeat.end repeat 16. (list 0x40 0x41 0x42 0x43 0x44 0x45 0x46 0x47 0x48 0x49 0x4A 0x4B 0x4C 0x4D 0x4E 0x4F )(list 0x100 0x104 0x108 0x10C 0x110 0x114 0x118 0x11C 0x120 0x124 0x128 0x12C 0x130 0x134 0x138 0x13C ) group.long ($2+0x1020)++0x3 line.long 0x0 "FUSE_WORD_$1,Shadow register for fuse word" hexmask.long 0x0 0.--31. 1. "DATA,Shadow register for fuse word" repeat.end repeat 16. (list 0x50 0x51 0x52 0x53 0x54 0x55 0x56 0x57 0x58 0x59 0x5A 0x5B 0x5C 0x5D 0x5E 0x5F )(list 0x140 0x144 0x148 0x14C 0x150 0x154 0x158 0x15C 0x160 0x164 0x168 0x16C 0x170 0x174 0x178 0x17C ) group.long ($2+0x1020)++0x3 line.long 0x0 "FUSE_WORD_$1,Shadow register for fuse word" hexmask.long 0x0 0.--31. 1. "DATA,Shadow register for fuse word" repeat.end repeat 16. (list 0x60 0x61 0x62 0x63 0x64 0x65 0x66 0x67 0x68 0x69 0x6A 0x6B 0x6C 0x6D 0x6E 0x6F )(list 0x180 0x184 0x188 0x18C 0x190 0x194 0x198 0x19C 0x1A0 0x1A4 0x1A8 0x1AC 0x1B0 0x1B4 0x1B8 0x1BC ) group.long ($2+0x1020)++0x3 line.long 0x0 "FUSE_WORD_$1,Shadow register for fuse word" hexmask.long 0x0 0.--31. 1. "DATA,Shadow register for fuse word" repeat.end repeat 16. (list 0x70 0x71 0x72 0x73 0x74 0x75 0x76 0x77 0x78 0x79 0x7A 0x7B 0x7C 0x7D 0x7E 0x7F )(list 0x1C0 0x1C4 0x1C8 0x1CC 0x1D0 0x1D4 0x1D8 0x1DC 0x1E0 0x1E4 0x1E8 0x1EC 0x1F0 0x1F4 0x1F8 0x1FC ) group.long ($2+0x1020)++0x3 line.long 0x0 "FUSE_WORD_$1,Shadow register for fuse word" hexmask.long 0x0 0.--31. 1. "DATA,Shadow register for fuse word" repeat.end repeat 16. (list 0x80 0x81 0x82 0x83 0x84 0x85 0x86 0x87 0x88 0x89 0x8A 0x8B 0x8C 0x8D 0x8E 0x8F )(list 0x200 0x204 0x208 0x20C 0x210 0x214 0x218 0x21C 0x220 0x224 0x228 0x22C 0x230 0x234 0x238 0x23C ) group.long ($2+0x1020)++0x3 line.long 0x0 "FUSE_WORD_$1,Shadow register for fuse word" hexmask.long 0x0 0.--31. 1. "DATA,Shadow register for fuse word" repeat.end repeat 16. (list 0x90 0x91 0x92 0x93 0x94 0x95 0x96 0x97 0x98 0x99 0x9A 0x9B 0x9C 0x9D 0x9E 0x9F )(list 0x240 0x244 0x248 0x24C 0x250 0x254 0x258 0x25C 0x260 0x264 0x268 0x26C 0x270 0x274 0x278 0x27C ) group.long ($2+0x1020)++0x3 line.long 0x0 "FUSE_WORD_$1,Shadow register for fuse word" hexmask.long 0x0 0.--31. 1. "DATA,Shadow register for fuse word" repeat.end repeat 16. (list 0xA0 0xA1 0xA2 0xA3 0xA4 0xA5 0xA6 0xA7 0xA8 0xA9 0xAA 0xAB 0xAC 0xAD 0xAE 0xAF )(list 0x280 0x284 0x288 0x28C 0x290 0x294 0x298 0x29C 0x2A0 0x2A4 0x2A8 0x2AC 0x2B0 0x2B4 0x2B8 0x2BC ) group.long ($2+0x1020)++0x3 line.long 0x0 "FUSE_WORD_$1,Shadow register for fuse word" hexmask.long 0x0 0.--31. 1. "DATA,Shadow register for fuse word" repeat.end repeat 4. (list 0xB0 0xB1 0xB2 0xB3 )(list 0x2C0 0x2C4 0x2C8 0x2CC ) group.long ($2+0x1020)++0x3 line.long 0x0 "FUSE_WORD_$1,Shadow register for fuse word" hexmask.long 0x0 0.--31. 1. "DATA,Shadow register for fuse word" repeat.end elif (CORENAME()=="CORTEXA55") base ad:0x30010000 group.long 0x0++0xB line.long 0x0 "FUSE_CTRL,This register provides controll setting and save status for fuse opeation" hexmask.long.word 0x0 16.--31. 1. "PROG_KEY,Write special key to enable fuse program operation." bitfld.long 0x0 12. "ERROR,It indicates fuse operation is failed when set." "0,1" rbitfld.long 0x0 11. "BUSY,It indicates fuse operation is not complete when set" "0,1" bitfld.long 0x0 9.--10. "AT,It is used to assert AT1 and AT0 pin of fuse macro in Test row and column fuse programming and reading." "0,1,2,3" newline bitfld.long 0x0 8. "MARGIN,It is used to assert MR pin of fuse macro in fuse margin reading." "0,1" hexmask.long.byte 0x0 0.--7. 1. "ADDR,Fuse program and read access address register. In normal program and read ADDR[7:0] is used to select one of 256 fuse words. In test program mode ADDR[6:0] is used to select which bit is programmed in selected test row. In test read mode.." line.long 0x4 "PROG_DATA,This register is used to provide programming data." hexmask.long 0x4 0.--31. 1. "DATA,fuse program data" line.long 0x8 "FUSE_TRIG,Fuse operation trigger register. It is in conjuction with FUSE_CTRL and FUSE_DATA register to trigger fuse operation." bitfld.long 0x8 4. "LOAD,After set fuse_ctrl wil reload fuse into shadow registers in order. It will be clear after reload is complete." "0,1" bitfld.long 0x8 3. "TPROG,After set it will trigger fuse program operation for test row/column fuse word which address is assigned by ADDR in FUSE_CTRL register. It will be clear after operation is complete" "0,1" bitfld.long 0x8 2. "PROG,After set it will trigger fuse program operation for fuse word which address is assigned by ADDR in FUSE_CTRL register. It will be clear after operation is complete" "0,1" bitfld.long 0x8 1. "TREAD,After set it will trigger fuse read operation for test row/column fuse word which address is assigned by ADDR in FUSE_CTRL register. It will be clear after operation is complete" "0,1" newline bitfld.long 0x8 0. "READ,After set it will trigger fuse read oeration for fuse word which address is assigned by ADDR in FUSE_CTRL register. It will be clear after operation is complete." "0,1" rgroup.long 0xC++0x3 line.long 0x0 "READ_FUSE_DATA,This register is used to save fuse data read from fuse macro." hexmask.long 0x0 0.--31. 1. "DATA,The fuse data read from fuse macro." group.long 0x10++0x1B line.long 0x0 "FUSE_TIMING_0,Fuse timing register 0. It provides timing configuration for fuse programming and reading." hexmask.long.byte 0x0 24.--31. 1. "PD_SETUP_CNT,Specifiy setup time from PD to PS or PD to CS" hexmask.long.byte 0x0 18.--23. 1. "PD_HOLD_CNT,Specifiy hold time from PD to PS or PD to CS" hexmask.long.byte 0x0 13.--17. 1. "PS_SETUP_CNT,Specifiy setup time from PS to other signals." hexmask.long.byte 0x0 8.--12. 1. "PS_HOLD_CNT,Specifiy hold time from PS to other signals." hexmask.long.byte 0x0 4.--7. 1. "CS_SETUP_CNT,Specifiy setup time to address signals." newline hexmask.long.byte 0x0 0.--3. 1. "CS_HOLD_CNT,Specifiy hold time to address signals." line.long 0x4 "FUSE_TIMING_1,Fuse timing register1. It provides timing configuration for fuse programming and reading." hexmask.long.byte 0x4 24.--31. 1. "RD_TO_PROG_CNT,Specify timing interval between fuse reading and programming" hexmask.long.byte 0x4 18.--23. 1. "MR_RD_STRB_CNT,Specify strobe signal width in fuse margin reading" hexmask.long.byte 0x4 12.--17. 1. "RD_STRB_CNT,Specify strobe signal width in fuse normal reading" hexmask.long.word 0x4 0.--11. 1. "PROG_STRB_CNT,Sepcify strobe signal width in fuse programming." line.long 0x8 "CHECK_FUSE_ADDR,It indicates which fuse word need be checked. Need set between188~255" hexmask.long.byte 0x8 0.--7. 1. "ADDR,Indicate which fuse word need be checked. Need set between 188~255" line.long 0xC "SEMA_LOCK,It provides semaphore lock for SE and AP access" rbitfld.long 0xC 2. "AP_LOCK,This bit shows that LOCK bit is set by AP APB bus." "0,1" rbitfld.long 0xC 1. "SE_LOCK,This bit shows that LOCK bit is set by SE APB bus" "0,1" bitfld.long 0xC 0. "LOCK,When this bit is set by SE or AP APB bus Other APB bus can not access register 0x0~0x18 and clear this bit." "0,1" line.long 0x10 "INT_STA,Interrupt status register" bitfld.long 0x10 3. "FATAL,It reports ECC correction logic error." "0,1" bitfld.long 0x10 2. "MUL_ERR,Indicate ECC mulitple bit error happen" "0,1" bitfld.long 0x10 1. "RED_ERR,Indicate redundancy fuse has been corrected" "0,1" bitfld.long 0x10 0. "SIG_ERR,Indicate ECC single bit correction happens" "0,1" line.long 0x14 "INT_STA_EN,Interrupt status enable" bitfld.long 0x14 3. "FATAL,ECC correction logic error interrupt status enable" "0,1" bitfld.long 0x14 2. "MUL_ERR,ECC multiple bit errors interrupt status enable" "0,1" bitfld.long 0x14 1. "RED_ERR,redundancy fuse correction interrupt status enable" "0,1" bitfld.long 0x14 0. "SIG_ERR,ECC single bit error interrupt status enable" "0,1" line.long 0x18 "INT_SIG_EN,Interrupt signal enable" bitfld.long 0x18 3. "FATAL,ECC correction logic error interrupt signal enable" "0,1" bitfld.long 0x18 2. "MUL_ERR,Multiple fuse bits error interrupt signal enable" "0,1" bitfld.long 0x18 1. "RED_ERR,Redundancy fuse correction interrupt signal enable" "0,1" bitfld.long 0x18 0. "SIG_ERR,ECC single error bit interrupt signal enable" "0,1" repeat 5. (list 0x0 0x1 0x2 0x3 0x4 )(list 0x0 0x4 0x8 0xC 0x10 ) group.long ($2+0x100)++0x3 line.long 0x0 "ECC_SIG_ERROR$1,Indicate single bit error in ecc word0~31" bitfld.long 0x0 31. "ERR_31,ecc fuse word single bit error" "0,1" bitfld.long 0x0 30. "ERR_30,ecc fuse word single bit error" "0,1" bitfld.long 0x0 29. "ERR_29,ecc fuse word single bit error" "0,1" bitfld.long 0x0 28. "ERR_28,ecc fuse word single bit error" "0,1" bitfld.long 0x0 27. "ERR_27,ecc fuse word single bit error" "0,1" newline bitfld.long 0x0 26. "ERR_26,ecc fuse word single bit error" "0,1" bitfld.long 0x0 25. "ERR_25,ecc fuse word single bit error" "0,1" bitfld.long 0x0 24. "ERR_24,ecc fuse word single bit error" "0,1" bitfld.long 0x0 23. "ERR_23,ecc fuse word single bit error" "0,1" bitfld.long 0x0 22. "ERR_22,ecc fuse word single bit error" "0,1" newline bitfld.long 0x0 21. "ERR_21,ecc fuse word single bit error" "0,1" bitfld.long 0x0 20. "ERR_20,ecc fuse word single bit error" "0,1" bitfld.long 0x0 19. "ERR_19,ecc fuse word single bit error" "0,1" bitfld.long 0x0 18. "ERR_18,ecc fuse word single bit error" "0,1" bitfld.long 0x0 17. "ERR_17,ecc fuse word single bit error" "0,1" newline bitfld.long 0x0 16. "ERR_16,ecc fuse word single bit error" "0,1" bitfld.long 0x0 15. "ERR_15,ecc fuse word single bit error" "0,1" bitfld.long 0x0 14. "ERR_14,ecc fuse word single bit error" "0,1" bitfld.long 0x0 13. "ERR_13,ecc fuse word single bit error" "0,1" bitfld.long 0x0 12. "ERR_12,ecc fuse word single bit error" "0,1" newline bitfld.long 0x0 11. "ERR_11,ecc fuse word single bit error" "0,1" bitfld.long 0x0 10. "ERR_10,ecc fuse word single bit error" "0,1" bitfld.long 0x0 9. "ERR_9,ecc fuse word single bit error" "0,1" bitfld.long 0x0 8. "ERR_8,ecc fuse word single bit error" "0,1" bitfld.long 0x0 7. "ERR_7,ecc fuse word single bit error" "0,1" newline bitfld.long 0x0 6. "ERR_6,ecc fuse word single bit error" "0,1" bitfld.long 0x0 5. "ERR_5,ecc fuse word single bit error" "0,1" bitfld.long 0x0 4. "ERR_4,ecc fuse word single bit error" "0,1" bitfld.long 0x0 3. "ERR_3,ecc fuse word single bit error" "0,1" bitfld.long 0x0 2. "ERR_2,ecc fuse word single bit error" "0,1" newline bitfld.long 0x0 1. "ERR_1,ecc fuse word single bit error" "0,1" bitfld.long 0x0 0. "ERR_0,ecc fuse word single bit error" "0,1" repeat.end repeat 5. (list 0x0 0x1 0x2 0x3 0x4 )(list 0x0 0x4 0x8 0xC 0x10 ) group.long ($2+0x114)++0x3 line.long 0x0 "ECC_MUL_ERROR$1,Indicate mulltiple bit error in ecc word0~31" bitfld.long 0x0 31. "ERR_31,ecc fuse word multiple bits error" "0,1" bitfld.long 0x0 30. "ERR_30,ecc fuse word multiple bits error" "0,1" bitfld.long 0x0 29. "ERR_29,ecc fuse word multiple bits error" "0,1" bitfld.long 0x0 28. "ERR_28,ecc fuse word multiple bits error" "0,1" bitfld.long 0x0 27. "ERR_27,ecc fuse word multiple bits error" "0,1" newline bitfld.long 0x0 26. "ERR_26,ecc fuse word multiple bits error" "0,1" bitfld.long 0x0 25. "ERR_25,ecc fuse word multiple bits error" "0,1" bitfld.long 0x0 24. "ERR_24,ecc fuse word multiple bits error" "0,1" bitfld.long 0x0 23. "ERR_23,ecc fuse word multiple bits error" "0,1" bitfld.long 0x0 22. "ERR_22,ecc fuse word multiple bits error" "0,1" newline bitfld.long 0x0 21. "ERR_21,ecc fuse word multiple bits error" "0,1" bitfld.long 0x0 20. "ERR_20,ecc fuse word multiple bits error" "0,1" bitfld.long 0x0 19. "ERR_19,ecc fuse word multiple bits error" "0,1" bitfld.long 0x0 18. "ERR_18,ecc fuse word multiple bits error" "0,1" bitfld.long 0x0 17. "ERR_17,ecc fuse word multiple bits error" "0,1" newline bitfld.long 0x0 16. "ERR_16,ecc fuse word multiple bits error" "0,1" bitfld.long 0x0 15. "ERR_15,ecc fuse word multiple bits error" "0,1" bitfld.long 0x0 14. "ERR_14,ecc fuse word multiple bits error" "0,1" bitfld.long 0x0 13. "ERR_13,ecc fuse word multiple bits error" "0,1" bitfld.long 0x0 12. "ERR_12,ecc fuse word multiple bits error" "0,1" newline bitfld.long 0x0 11. "ERR_11,ecc fuse word multiple bits error" "0,1" bitfld.long 0x0 10. "ERR_10,ecc fuse word multiple bits error" "0,1" bitfld.long 0x0 9. "ERR_9,ecc fuse word multiple bits error" "0,1" bitfld.long 0x0 8. "ERR_8,ecc fuse word multiple bits error" "0,1" bitfld.long 0x0 7. "ERR_7,ecc fuse word multiple bits error" "0,1" newline bitfld.long 0x0 6. "ERR_6,ecc fuse word multiple bits error" "0,1" bitfld.long 0x0 5. "ERR_5,ecc fuse word multiple bits error" "0,1" bitfld.long 0x0 4. "ERR_4,ecc fuse word multiple bits error" "0,1" bitfld.long 0x0 3. "ERR_3,ecc fuse word multiple bits error" "0,1" bitfld.long 0x0 2. "ERR_2,ecc fuse word multiple bits error" "0,1" newline bitfld.long 0x0 1. "ERR_1,ecc fuse word multiple bits error" "0,1" bitfld.long 0x0 0. "ERR_0,ecc fuse word multiple bits error" "0,1" repeat.end group.long 0x128++0x7 line.long 0x0 "RED_ERROR0,Indicate error in redundancy word0~19" bitfld.long 0x0 19. "ERR_19,Redundancy fuse word error" "0,1" bitfld.long 0x0 18. "ERR_18,Redundancy fuse word error" "0,1" bitfld.long 0x0 17. "ERR_17,Redundancy fuse word error" "0,1" bitfld.long 0x0 16. "ERR_16,Redundancy fuse word error" "0,1" newline bitfld.long 0x0 15. "ERR_15,Redundancy fuse word error" "0,1" bitfld.long 0x0 14. "ERR_14,Redundancy fuse word error" "0,1" bitfld.long 0x0 13. "ERR_13,Redundancy fuse word error" "0,1" bitfld.long 0x0 12. "ERR_12,Redundancy fuse word error" "0,1" bitfld.long 0x0 11. "ERR_11,Redundancy fuse word error" "0,1" newline bitfld.long 0x0 10. "ERR_10,Redundancy fuse word error" "0,1" bitfld.long 0x0 9. "ERR_9,Redundancy fuse word error" "0,1" bitfld.long 0x0 8. "ERR_8,Redundancy fuse word error" "0,1" bitfld.long 0x0 7. "ERR_7,Redundancy fuse word error" "0,1" bitfld.long 0x0 6. "ERR_6,Redundancy fuse word error" "0,1" newline bitfld.long 0x0 5. "ERR_5,Redundancy fuse word error" "0,1" bitfld.long 0x0 4. "ERR_4,Redundancy fuse word error" "0,1" bitfld.long 0x0 3. "ERR_3,Redundancy fuse word error" "0,1" bitfld.long 0x0 2. "ERR_2,Redundancy fuse word error" "0,1" bitfld.long 0x0 1. "ERR_1,Redundancy fuse word error" "0,1" newline bitfld.long 0x0 0. "ERR_0,Redundancy fuse word error" "0,1" line.long 0x4 "LOCK_RED_ERROR,Indicate error in lock fuse word0~7" bitfld.long 0x4 7. "ERR_7,Redundancy fuse word error" "0,1" bitfld.long 0x4 6. "ERR_6,Redundancy fuse word error" "0,1" bitfld.long 0x4 5. "ERR_5,Redundancy fuse word error" "0,1" bitfld.long 0x4 4. "ERR_4,Redundancy fuse word error" "0,1" newline bitfld.long 0x4 3. "ERR_3,Redundancy fuse word error" "0,1" bitfld.long 0x4 2. "ERR_2,Redundancy fuse word error" "0,1" bitfld.long 0x4 1. "ERR_1,Redundancy fuse word error" "0,1" bitfld.long 0x4 0. "ERR_0,Redundancy fuse word error" "0,1" repeat 4. (list 0x0 0x1 0x2 0x3 )(list 0x0 0x8 0x10 0x18 ) rgroup.long ($2+0x200)++0x3 line.long 0x0 "ECC_DATA_CORR_$1,indictor which data bit has been corrected." hexmask.long 0x0 0.--31. 1. "DATA,Indicate which data bit has been corrected" repeat.end repeat 4. (list 0x0 0x1 0x2 0x3 )(list 0x0 0x8 0x10 0x18 ) rgroup.long ($2+0x204)++0x3 line.long 0x0 "ECC_CORR_$1,Indicate which ecc bit is not correct" hexmask.long.byte 0x0 0.--6. 1. "ECC,Indicate which ecc bit has been corrected." repeat.end rgroup.long 0x220++0x7 line.long 0x0 "RED_DATA_CORR,Indicate which bit in redudancy bits are not corrected." hexmask.long 0x0 0.--31. 1. "DATA,Indicate which redundancy data bit are not correct." line.long 0x4 "RED_CORR,Indicate which redundancy data bit are not correct." hexmask.long 0x4 0.--31. 1. "RED,Indicate which redundancy data bit are not correct." group.long 0x300++0x27 line.long 0x0 "SE_GLB_LOCK,Global setting for SE bank lock. Sticky register." bitfld.long 0x0 0. "SE_LOCK,Lock SE lock register bits" "0,1" line.long 0x4 "SE_BANK_LOCK0,Bank0~7 lock bit for SE. Sticky register." bitfld.long 0x4 31. "HLOCK7,Lock for HW key bus." "0,1" bitfld.long 0x4 30. "OLOCK7,Lock for write shadow registers." "0,1" bitfld.long 0x4 29. "RLOCK7,Lock for read fuse and shadow register." "0,1" bitfld.long 0x4 28. "PLOCK7,Lock for program fuse." "0,1" bitfld.long 0x4 27. "HLOCK6,Lock for HW key bus." "0,1" newline bitfld.long 0x4 26. "OLOCK6,Lock for write shadow registers." "0,1" bitfld.long 0x4 25. "RLOCK6,Lock for read fuse and shadow register." "0,1" bitfld.long 0x4 24. "PLOCK6,Lock for program fuse." "0,1" bitfld.long 0x4 23. "HLOCK5,Lock for HW key bus." "0,1" bitfld.long 0x4 22. "OLOCK5,Lock for write shadow registers." "0,1" newline bitfld.long 0x4 21. "RLOCK5,Lock for read fuse and shadow register." "0,1" bitfld.long 0x4 20. "PLOCK5,Lock for program fuse." "0,1" bitfld.long 0x4 19. "HLOCK4,Lock for HW key bus." "0,1" bitfld.long 0x4 18. "OLOCK4,Lock for write shadow registers." "0,1" bitfld.long 0x4 17. "RLOCK4,Lock for read fuse and shadow register." "0,1" newline bitfld.long 0x4 16. "PLOCK4,Lock for program fuse." "0,1" bitfld.long 0x4 15. "HLOCK3,Lock for HW key bus." "0,1" bitfld.long 0x4 14. "OLOCK3,Lock for write shadow registers." "0,1" bitfld.long 0x4 13. "RLOCK3,Lock for read fuse and shadow register." "0,1" bitfld.long 0x4 12. "PLOCK3,Lock for program fuse." "0,1" newline bitfld.long 0x4 11. "HLOCK2,Lock for HW key bus." "0,1" bitfld.long 0x4 10. "OLOCK2,Lock for write shadow registers." "0,1" bitfld.long 0x4 9. "RLOCK2,Lock for read fuse and shadow register." "0,1" bitfld.long 0x4 8. "PLOCK2,Lock for program fuse." "0,1" bitfld.long 0x4 7. "HLOCK1,Lock for HW key bus." "0,1" newline bitfld.long 0x4 6. "OLOCK1,Lock for write shadow registers." "0,1" bitfld.long 0x4 5. "RLOCK1,Lock for read fuse and shadow register." "0,1" bitfld.long 0x4 4. "PLOCK1,Lock for program fuse." "0,1" bitfld.long 0x4 3. "HLOCK0,Lock for HW key bus." "0,1" bitfld.long 0x4 2. "OLOCK0,Lock for write shadow registers." "0,1" newline bitfld.long 0x4 1. "RLOCK0,Lock for read fuse and shadow register." "0,1" bitfld.long 0x4 0. "PLOCK0,Lock for program fuse." "0,1" line.long 0x8 "SE_BANK_LOCK1,Bank8~15 lock bit for SE. Sticky register." bitfld.long 0x8 31. "HLOCK7,Lock for HW key bus." "0,1" bitfld.long 0x8 30. "OLOCK7,Lock for write shadow registers." "0,1" bitfld.long 0x8 29. "RLOCK7,Lock for read fuse and shadow register." "0,1" bitfld.long 0x8 28. "PLOCK7,Lock for program fuse." "0,1" bitfld.long 0x8 27. "HLOCK6,Lock for HW key bus." "0,1" newline bitfld.long 0x8 26. "OLOCK6,Lock for write shadow registers." "0,1" bitfld.long 0x8 25. "RLOCK6,Lock for read fuse and shadow register." "0,1" bitfld.long 0x8 24. "PLOCK6,Lock for program fuse." "0,1" bitfld.long 0x8 23. "HLOCK5,Lock for HW key bus." "0,1" bitfld.long 0x8 22. "OLOCK5,Lock for write shadow registers." "0,1" newline bitfld.long 0x8 21. "RLOCK5,Lock for read fuse and shadow register." "0,1" bitfld.long 0x8 20. "PLOCK5,Lock for program fuse." "0,1" bitfld.long 0x8 19. "HLOCK4,Lock for HW key bus." "0,1" bitfld.long 0x8 18. "OLOCK4,Lock for write shadow registers." "0,1" bitfld.long 0x8 17. "RLOCK4,Lock for read fuse and shadow register." "0,1" newline bitfld.long 0x8 16. "PLOCK4,Lock for program fuse." "0,1" bitfld.long 0x8 15. "HLOCK3,Lock for HW key bus." "0,1" bitfld.long 0x8 14. "OLOCK3,Lock for write shadow registers." "0,1" bitfld.long 0x8 13. "RLOCK3,Lock for read fuse and shadow register." "0,1" bitfld.long 0x8 12. "PLOCK3,Lock for program fuse." "0,1" newline bitfld.long 0x8 11. "HLOCK2,Lock for HW key bus." "0,1" bitfld.long 0x8 10. "OLOCK2,Lock for write shadow registers." "0,1" bitfld.long 0x8 9. "RLOCK2,Lock for read fuse and shadow register." "0,1" bitfld.long 0x8 8. "PLOCK2,Lock for program fuse." "0,1" bitfld.long 0x8 7. "HLOCK1,Lock for HW key bus." "0,1" newline bitfld.long 0x8 6. "OLOCK1,Lock for write shadow registers." "0,1" bitfld.long 0x8 5. "RLOCK1,Lock for read fuse and shadow register." "0,1" bitfld.long 0x8 4. "PLOCK1,Lock for program fuse." "0,1" bitfld.long 0x8 3. "HLOCK0,Lock for HW key bus." "0,1" bitfld.long 0x8 2. "OLOCK0,Lock for write shadow registers." "0,1" newline bitfld.long 0x8 1. "RLOCK0,Lock for read fuse and shadow register." "0,1" bitfld.long 0x8 0. "PLOCK0,Lock for program fuse." "0,1" line.long 0xC "SE_BANK_LOCK2,Bank16~23 lock bit for SE. Sticky register." bitfld.long 0xC 31. "HLOCK7,Lock for HW key bus." "0,1" bitfld.long 0xC 30. "OLOCK7,Lock for write shadow registers." "0,1" bitfld.long 0xC 29. "RLOCK7,Lock for read fuse and shadow register." "0,1" bitfld.long 0xC 28. "PLOCK7,Lock for program fuse." "0,1" bitfld.long 0xC 27. "HLOCK6,Lock for HW key bus." "0,1" newline bitfld.long 0xC 26. "OLOCK6,Lock for write shadow registers." "0,1" bitfld.long 0xC 25. "RLOCK6,Lock for read fuse and shadow register." "0,1" bitfld.long 0xC 24. "PLOCK6,Lock for program fuse." "0,1" bitfld.long 0xC 23. "HLOCK5,Lock for HW key bus." "0,1" bitfld.long 0xC 22. "OLOCK5,Lock for write shadow registers." "0,1" newline bitfld.long 0xC 21. "RLOCK5,Lock for read fuse and shadow register." "0,1" bitfld.long 0xC 20. "PLOCK5,Lock for program fuse." "0,1" bitfld.long 0xC 19. "HLOCK4,Lock for HW key bus." "0,1" bitfld.long 0xC 18. "OLOCK4,Lock for write shadow registers." "0,1" bitfld.long 0xC 17. "RLOCK4,Lock for read fuse and shadow register." "0,1" newline bitfld.long 0xC 16. "PLOCK4,Lock for program fuse." "0,1" bitfld.long 0xC 15. "HLOCK3,Lock for HW key bus." "0,1" bitfld.long 0xC 14. "OLOCK3,Lock for write shadow registers." "0,1" bitfld.long 0xC 13. "RLOCK3,Lock for read fuse and shadow register." "0,1" bitfld.long 0xC 12. "PLOCK3,Lock for program fuse." "0,1" newline bitfld.long 0xC 11. "HLOCK2,Lock for HW key bus." "0,1" bitfld.long 0xC 10. "OLOCK2,Lock for write shadow registers." "0,1" bitfld.long 0xC 9. "RLOCK2,Lock for read fuse and shadow register." "0,1" bitfld.long 0xC 8. "PLOCK2,Lock for program fuse." "0,1" bitfld.long 0xC 7. "HLOCK1,Lock for HW key bus." "0,1" newline bitfld.long 0xC 6. "OLOCK1,Lock for write shadow registers." "0,1" bitfld.long 0xC 5. "RLOCK1,Lock for read fuse and shadow register." "0,1" bitfld.long 0xC 4. "PLOCK1,Lock for program fuse." "0,1" bitfld.long 0xC 3. "HLOCK0,Lock for HW key bus." "0,1" bitfld.long 0xC 2. "OLOCK0,Lock for write shadow registers." "0,1" newline bitfld.long 0xC 1. "RLOCK0,Lock for read fuse and shadow register." "0,1" bitfld.long 0xC 0. "PLOCK0,Lock for program fuse." "0,1" line.long 0x10 "SE_BANK_LOCK3,Bank24~31 lock bit for SE. Sticky register." bitfld.long 0x10 31. "HLOCK7,Lock for HW key bus." "0,1" bitfld.long 0x10 30. "OLOCK7,Lock for write shadow registers." "0,1" bitfld.long 0x10 29. "RLOCK7,Lock for read fuse and shadow register." "0,1" bitfld.long 0x10 28. "PLOCK7,Lock for program fuse." "0,1" bitfld.long 0x10 27. "HLOCK6,Lock for HW key bus." "0,1" newline bitfld.long 0x10 26. "OLOCK6,Lock for write shadow registers." "0,1" bitfld.long 0x10 25. "RLOCK6,Lock for read fuse and shadow register." "0,1" bitfld.long 0x10 24. "PLOCK6,Lock for program fuse." "0,1" bitfld.long 0x10 23. "HLOCK5,Lock for HW key bus." "0,1" bitfld.long 0x10 22. "OLOCK5,Lock for write shadow registers." "0,1" newline bitfld.long 0x10 21. "RLOCK5,Lock for read fuse and shadow register." "0,1" bitfld.long 0x10 20. "PLOCK5,Lock for program fuse." "0,1" bitfld.long 0x10 19. "HLOCK4,Lock for HW key bus." "0,1" bitfld.long 0x10 18. "OLOCK4,Lock for write shadow registers." "0,1" bitfld.long 0x10 17. "RLOCK4,Lock for read fuse and shadow register." "0,1" newline bitfld.long 0x10 16. "PLOCK4,Lock for program fuse." "0,1" bitfld.long 0x10 15. "HLOCK3,Lock for HW key bus." "0,1" bitfld.long 0x10 14. "OLOCK3,Lock for write shadow registers." "0,1" bitfld.long 0x10 13. "RLOCK3,Lock for read fuse and shadow register." "0,1" bitfld.long 0x10 12. "PLOCK3,Lock for program fuse." "0,1" newline bitfld.long 0x10 11. "HLOCK2,Lock for HW key bus." "0,1" bitfld.long 0x10 10. "OLOCK2,Lock for write shadow registers." "0,1" bitfld.long 0x10 9. "RLOCK2,Lock for read fuse and shadow register." "0,1" bitfld.long 0x10 8. "PLOCK2,Lock for program fuse." "0,1" bitfld.long 0x10 7. "HLOCK1,Lock for HW key bus." "0,1" newline bitfld.long 0x10 6. "OLOCK1,Lock for write shadow registers." "0,1" bitfld.long 0x10 5. "RLOCK1,Lock for read fuse and shadow register." "0,1" bitfld.long 0x10 4. "PLOCK1,Lock for program fuse." "0,1" bitfld.long 0x10 3. "HLOCK0,Lock for HW key bus." "0,1" bitfld.long 0x10 2. "OLOCK0,Lock for write shadow registers." "0,1" newline bitfld.long 0x10 1. "RLOCK0,Lock for read fuse and shadow register." "0,1" bitfld.long 0x10 0. "PLOCK0,Lock for program fuse." "0,1" line.long 0x14 "AP_GLB_LOCK,Global setting for AP bank lock. Sticky register." bitfld.long 0x14 0. "AP_LOCK,Lock AP lock register bits." "0,1" line.long 0x18 "AP_BANK_LOCK0,Bank0~7 lock bit for AP. Sticky register." bitfld.long 0x18 31. "HLOCK7,Lock for HW key bus." "0,1" bitfld.long 0x18 30. "OLOCK7,Lock for write shadow registers." "0,1" bitfld.long 0x18 29. "RLOCK7,Lock for read fuse and shadow register." "0,1" bitfld.long 0x18 28. "PLOCK7,Lock for program fuse." "0,1" bitfld.long 0x18 27. "HLOCK6,Lock for HW key bus." "0,1" newline bitfld.long 0x18 26. "OLOCK6,Lock for write shadow registers." "0,1" bitfld.long 0x18 25. "RLOCK6,Lock for read fuse and shadow register." "0,1" bitfld.long 0x18 24. "PLOCK6,Lock for program fuse." "0,1" bitfld.long 0x18 23. "HLOCK5,Lock for HW key bus." "0,1" bitfld.long 0x18 22. "OLOCK5,Lock for write shadow registers." "0,1" newline bitfld.long 0x18 21. "RLOCK5,Lock for read fuse and shadow register." "0,1" bitfld.long 0x18 20. "PLOCK5,Lock for program fuse." "0,1" bitfld.long 0x18 19. "HLOCK4,Lock for HW key bus." "0,1" bitfld.long 0x18 18. "OLOCK4,Lock for write shadow registers." "0,1" bitfld.long 0x18 17. "RLOCK4,Lock for read fuse and shadow register." "0,1" newline bitfld.long 0x18 16. "PLOCK4,Lock for program fuse." "0,1" bitfld.long 0x18 15. "HLOCK3,Lock for HW key bus." "0,1" bitfld.long 0x18 14. "OLOCK3,Lock for write shadow registers." "0,1" bitfld.long 0x18 13. "RLOCK3,Lock for read fuse and shadow register." "0,1" bitfld.long 0x18 12. "PLOCK3,Lock for program fuse." "0,1" newline bitfld.long 0x18 11. "HLOCK2,Lock for HW key bus." "0,1" bitfld.long 0x18 10. "OLOCK2,Lock for write shadow registers." "0,1" bitfld.long 0x18 9. "RLOCK2,Lock for read fuse and shadow register." "0,1" bitfld.long 0x18 8. "PLOCK2,Lock for program fuse." "0,1" bitfld.long 0x18 7. "HLOCK1,Lock for HW key bus." "0,1" newline bitfld.long 0x18 6. "OLOCK1,Lock for write shadow registers." "0,1" bitfld.long 0x18 5. "RLOCK1,Lock for read fuse and shadow register." "0,1" bitfld.long 0x18 4. "PLOCK1,Lock for program fuse." "0,1" bitfld.long 0x18 3. "HLOCK0,Lock for HW key bus." "0,1" bitfld.long 0x18 2. "OLOCK0,Lock for write shadow registers." "0,1" newline bitfld.long 0x18 1. "RLOCK0,Lock for read fuse and shadow register." "0,1" bitfld.long 0x18 0. "PLOCK0,Lock for program fuse." "0,1" line.long 0x1C "AP_BANK_LOCK1,Bank8~15 lock bit for AP. Sticky register." bitfld.long 0x1C 31. "HLOCK7,Lock for HW key bus." "0,1" bitfld.long 0x1C 30. "OLOCK7,Lock for write shadow registers." "0,1" bitfld.long 0x1C 29. "RLOCK7,Lock for read fuse and shadow register." "0,1" bitfld.long 0x1C 28. "PLOCK7,Lock for program fuse." "0,1" bitfld.long 0x1C 27. "HLOCK6,Lock for HW key bus." "0,1" newline bitfld.long 0x1C 26. "OLOCK6,Lock for write shadow registers." "0,1" bitfld.long 0x1C 25. "RLOCK6,Lock for read fuse and shadow register." "0,1" bitfld.long 0x1C 24. "PLOCK6,Lock for program fuse." "0,1" bitfld.long 0x1C 23. "HLOCK5,Lock for HW key bus." "0,1" bitfld.long 0x1C 22. "OLOCK5,Lock for write shadow registers." "0,1" newline bitfld.long 0x1C 21. "RLOCK5,Lock for read fuse and shadow register." "0,1" bitfld.long 0x1C 20. "PLOCK5,Lock for program fuse." "0,1" bitfld.long 0x1C 19. "HLOCK4,Lock for HW key bus." "0,1" bitfld.long 0x1C 18. "OLOCK4,Lock for write shadow registers." "0,1" bitfld.long 0x1C 17. "RLOCK4,Lock for read fuse and shadow register." "0,1" newline bitfld.long 0x1C 16. "PLOCK4,Lock for program fuse." "0,1" bitfld.long 0x1C 15. "HLOCK3,Lock for HW key bus." "0,1" bitfld.long 0x1C 14. "OLOCK3,Lock for write shadow registers." "0,1" bitfld.long 0x1C 13. "RLOCK3,Lock for read fuse and shadow register." "0,1" bitfld.long 0x1C 12. "PLOCK3,Lock for program fuse." "0,1" newline bitfld.long 0x1C 11. "HLOCK2,Lock for HW key bus." "0,1" bitfld.long 0x1C 10. "OLOCK2,Lock for write shadow registers." "0,1" bitfld.long 0x1C 9. "RLOCK2,Lock for read fuse and shadow register." "0,1" bitfld.long 0x1C 8. "PLOCK2,Lock for program fuse." "0,1" bitfld.long 0x1C 7. "HLOCK1,Lock for HW key bus." "0,1" newline bitfld.long 0x1C 6. "OLOCK1,Lock for write shadow registers." "0,1" bitfld.long 0x1C 5. "RLOCK1,Lock for read fuse and shadow register." "0,1" bitfld.long 0x1C 4. "PLOCK1,Lock for program fuse." "0,1" bitfld.long 0x1C 3. "HLOCK0,Lock for HW key bus." "0,1" bitfld.long 0x1C 2. "OLOCK0,Lock for write shadow registers." "0,1" newline bitfld.long 0x1C 1. "RLOCK0,Lock for read fuse and shadow register." "0,1" bitfld.long 0x1C 0. "PLOCK0,Lock for program fuse." "0,1" line.long 0x20 "AP_BANK_LOCK2,Bank16~23 lock bit for AP. Sticky register." bitfld.long 0x20 31. "HLOCK7,Lock for HW key bus." "0,1" bitfld.long 0x20 30. "OLOCK7,Lock for write shadow registers." "0,1" bitfld.long 0x20 29. "RLOCK7,Lock for read fuse and shadow register." "0,1" bitfld.long 0x20 28. "PLOCK7,Lock for program fuse." "0,1" bitfld.long 0x20 27. "HLOCK6,Lock for HW key bus." "0,1" newline bitfld.long 0x20 26. "OLOCK6,Lock for write shadow registers." "0,1" bitfld.long 0x20 25. "RLOCK6,Lock for read fuse and shadow register." "0,1" bitfld.long 0x20 24. "PLOCK6,Lock for program fuse." "0,1" bitfld.long 0x20 23. "HLOCK5,Lock for HW key bus." "0,1" bitfld.long 0x20 22. "OLOCK5,Lock for write shadow registers." "0,1" newline bitfld.long 0x20 21. "RLOCK5,Lock for read fuse and shadow register." "0,1" bitfld.long 0x20 20. "PLOCK5,Lock for program fuse." "0,1" bitfld.long 0x20 19. "HLOCK4,Lock for HW key bus." "0,1" bitfld.long 0x20 18. "OLOCK4,Lock for write shadow registers." "0,1" bitfld.long 0x20 17. "RLOCK4,Lock for read fuse and shadow register." "0,1" newline bitfld.long 0x20 16. "PLOCK4,Lock for program fuse." "0,1" bitfld.long 0x20 15. "HLOCK3,Lock for HW key bus." "0,1" bitfld.long 0x20 14. "OLOCK3,Lock for write shadow registers." "0,1" bitfld.long 0x20 13. "RLOCK3,Lock for read fuse and shadow register." "0,1" bitfld.long 0x20 12. "PLOCK3,Lock for program fuse." "0,1" newline bitfld.long 0x20 11. "HLOCK2,Lock for HW key bus." "0,1" bitfld.long 0x20 10. "OLOCK2,Lock for write shadow registers." "0,1" bitfld.long 0x20 9. "RLOCK2,Lock for read fuse and shadow register." "0,1" bitfld.long 0x20 8. "PLOCK2,Lock for program fuse." "0,1" bitfld.long 0x20 7. "HLOCK1,Lock for HW key bus." "0,1" newline bitfld.long 0x20 6. "OLOCK1,Lock for write shadow registers." "0,1" bitfld.long 0x20 5. "RLOCK1,Lock for read fuse and shadow register." "0,1" bitfld.long 0x20 4. "PLOCK1,Lock for program fuse." "0,1" bitfld.long 0x20 3. "HLOCK0,Lock for HW key bus." "0,1" bitfld.long 0x20 2. "OLOCK0,Lock for write shadow registers." "0,1" newline bitfld.long 0x20 1. "RLOCK0,Lock for read fuse and shadow register." "0,1" bitfld.long 0x20 0. "PLOCK0,Lock for program fuse." "0,1" line.long 0x24 "AP_BANK_LOCK3,Bank24~31 lock bit for AP. Sticky register." bitfld.long 0x24 31. "HLOCK7,Lock for HW key bus." "0,1" bitfld.long 0x24 30. "OLOCK7,Lock for write shadow registers." "0,1" bitfld.long 0x24 29. "RLOCK7,Lock for read fuse and shadow register." "0,1" bitfld.long 0x24 28. "PLOCK7,Lock for program fuse." "0,1" bitfld.long 0x24 27. "HLOCK6,Lock for HW key bus." "0,1" newline bitfld.long 0x24 26. "OLOCK6,Lock for write shadow registers." "0,1" bitfld.long 0x24 25. "RLOCK6,Lock for read fuse and shadow register." "0,1" bitfld.long 0x24 24. "PLOCK6,Lock for program fuse." "0,1" bitfld.long 0x24 23. "HLOCK5,Lock for HW key bus." "0,1" bitfld.long 0x24 22. "OLOCK5,Lock for write shadow registers." "0,1" newline bitfld.long 0x24 21. "RLOCK5,Lock for read fuse and shadow register." "0,1" bitfld.long 0x24 20. "PLOCK5,Lock for program fuse." "0,1" bitfld.long 0x24 19. "HLOCK4,Lock for HW key bus." "0,1" bitfld.long 0x24 18. "OLOCK4,Lock for write shadow registers." "0,1" bitfld.long 0x24 17. "RLOCK4,Lock for read fuse and shadow register." "0,1" newline bitfld.long 0x24 16. "PLOCK4,Lock for program fuse." "0,1" bitfld.long 0x24 15. "HLOCK3,Lock for HW key bus." "0,1" bitfld.long 0x24 14. "OLOCK3,Lock for write shadow registers." "0,1" bitfld.long 0x24 13. "RLOCK3,Lock for read fuse and shadow register." "0,1" bitfld.long 0x24 12. "PLOCK3,Lock for program fuse." "0,1" newline bitfld.long 0x24 11. "HLOCK2,Lock for HW key bus." "0,1" bitfld.long 0x24 10. "OLOCK2,Lock for write shadow registers." "0,1" bitfld.long 0x24 9. "RLOCK2,Lock for read fuse and shadow register." "0,1" bitfld.long 0x24 8. "PLOCK2,Lock for program fuse." "0,1" bitfld.long 0x24 7. "HLOCK1,Lock for HW key bus." "0,1" newline bitfld.long 0x24 6. "OLOCK1,Lock for write shadow registers." "0,1" bitfld.long 0x24 5. "RLOCK1,Lock for read fuse and shadow register." "0,1" bitfld.long 0x24 4. "PLOCK1,Lock for program fuse." "0,1" bitfld.long 0x24 3. "HLOCK0,Lock for HW key bus." "0,1" bitfld.long 0x24 2. "OLOCK0,Lock for write shadow registers." "0,1" newline bitfld.long 0x24 1. "RLOCK0,Lock for read fuse and shadow register." "0,1" bitfld.long 0x24 0. "PLOCK0,Lock for program fuse." "0,1" group.long 0x400++0x17 line.long 0x0 "DATA_INJ_ECC,Error jnjection for read data for ECC mode." hexmask.long 0x0 0.--31. 1. "INJ,Error jnjection for read data." line.long 0x4 "ECC_INJ_ECC,Error injection for ecc code for ECC mode" hexmask.long.byte 0x4 0.--6. 1. "INJ,Error injection for ecc code" line.long 0x8 "DATA_INJ_RED,Error injection for read data for redundancy fuse data" hexmask.long 0x8 0.--31. 1. "INJ,Error injection for redundancy fuse data" line.long 0xC "RED_INJ_RED,Error injection for redundancy fuse data for redundancy mode" hexmask.long 0xC 0.--31. 1. "INJ,Error injection for redundancy fuse data" line.long 0x10 "RDATA_INJ_ECC,Error jnjection for read correction data for ECC mode." hexmask.long 0x10 0.--31. 1. "INJ,Error jnjection for read data." line.long 0x14 "RECC_INJ_ECC_1,Error injection for ecc correction code for ECC mode" hexmask.long.byte 0x14 0.--6. 1. "INJ,Error injection for ecc code" repeat 4. (list 0x0 0x1 0x2 0x3 )(list 0x0 0x4 0x8 0xC ) group.long ($2+0x500)++0x3 line.long 0x0 "SW_STICKY_SE$1,SW sticky register bit for safety domain." bitfld.long 0x0 31. "BIT_31,SW sticky bit" "0,1" bitfld.long 0x0 30. "BIT_30,SW sticky bit" "0,1" bitfld.long 0x0 29. "BIT_29,SW sticky bit" "0,1" bitfld.long 0x0 28. "BIT_28,SW sticky bit" "0,1" bitfld.long 0x0 27. "BIT_27,SW sticky bit" "0,1" newline bitfld.long 0x0 26. "BIT_26,SW sticky bit" "0,1" bitfld.long 0x0 25. "BIT_25,SW sticky bit" "0,1" bitfld.long 0x0 24. "BIT_24,SW sticky bit" "0,1" bitfld.long 0x0 23. "BIT_23,SW sticky bit" "0,1" bitfld.long 0x0 22. "BIT_22,SW sticky bit" "0,1" newline bitfld.long 0x0 21. "BIT_21,SW sticky bit" "0,1" bitfld.long 0x0 20. "BIT_20,SW sticky bit" "0,1" bitfld.long 0x0 19. "BIT_19,SW sticky bit" "0,1" bitfld.long 0x0 18. "BIT_18,SW sticky bit" "0,1" bitfld.long 0x0 17. "BIT_17,SW sticky bit" "0,1" newline bitfld.long 0x0 16. "BIT_16,SW sticky bit" "0,1" bitfld.long 0x0 15. "BIT_15,SW sticky bit" "0,1" bitfld.long 0x0 14. "BIT_14,SW sticky bit" "0,1" bitfld.long 0x0 13. "BIT_13,SW sticky bit" "0,1" bitfld.long 0x0 12. "BIT_12,SW sticky bit" "0,1" newline bitfld.long 0x0 11. "BIT_11,SW sticky bit" "0,1" bitfld.long 0x0 10. "BIT_10,SW sticky bit" "0,1" bitfld.long 0x0 9. "BIT_9,SW sticky bit" "0,1" bitfld.long 0x0 8. "BIT_8,SW sticky bit" "0,1" bitfld.long 0x0 7. "BIT_7,SW sticky bit" "0,1" newline bitfld.long 0x0 6. "BIT_6,SW sticky bit" "0,1" bitfld.long 0x0 5. "BIT_5,SW sticky bit" "0,1" bitfld.long 0x0 4. "BIT_4,SW sticky bit" "0,1" bitfld.long 0x0 3. "BIT_3,SW sticky bit" "0,1" bitfld.long 0x0 2. "BIT_2,SW sticky bit" "0,1" newline bitfld.long 0x0 1. "BIT_1,SW sticky bit" "0,1" bitfld.long 0x0 0. "BIT_0,SW sticky bit" "0,1" repeat.end repeat 4. (list 0x0 0x1 0x2 0x3 )(list 0x0 0x4 0x8 0xC ) group.long ($2+0x510)++0x3 line.long 0x0 "SW_STICKY_AP$1,SW sticky register bit for AP domain." bitfld.long 0x0 31. "BIT_31,SW sticky bit" "0,1" bitfld.long 0x0 30. "BIT_30,SW sticky bit" "0,1" bitfld.long 0x0 29. "BIT_29,SW sticky bit" "0,1" bitfld.long 0x0 28. "BIT_28,SW sticky bit" "0,1" bitfld.long 0x0 27. "BIT_27,SW sticky bit" "0,1" newline bitfld.long 0x0 26. "BIT_26,SW sticky bit" "0,1" bitfld.long 0x0 25. "BIT_25,SW sticky bit" "0,1" bitfld.long 0x0 24. "BIT_24,SW sticky bit" "0,1" bitfld.long 0x0 23. "BIT_23,SW sticky bit" "0,1" bitfld.long 0x0 22. "BIT_22,SW sticky bit" "0,1" newline bitfld.long 0x0 21. "BIT_21,SW sticky bit" "0,1" bitfld.long 0x0 20. "BIT_20,SW sticky bit" "0,1" bitfld.long 0x0 19. "BIT_19,SW sticky bit" "0,1" bitfld.long 0x0 18. "BIT_18,SW sticky bit" "0,1" bitfld.long 0x0 17. "BIT_17,SW sticky bit" "0,1" newline bitfld.long 0x0 16. "BIT_16,SW sticky bit" "0,1" bitfld.long 0x0 15. "BIT_15,SW sticky bit" "0,1" bitfld.long 0x0 14. "BIT_14,SW sticky bit" "0,1" bitfld.long 0x0 13. "BIT_13,SW sticky bit" "0,1" bitfld.long 0x0 12. "BIT_12,SW sticky bit" "0,1" newline bitfld.long 0x0 11. "BIT_11,SW sticky bit" "0,1" bitfld.long 0x0 10. "BIT_10,SW sticky bit" "0,1" bitfld.long 0x0 9. "BIT_9,SW sticky bit" "0,1" bitfld.long 0x0 8. "BIT_8,SW sticky bit" "0,1" bitfld.long 0x0 7. "BIT_7,SW sticky bit" "0,1" newline bitfld.long 0x0 6. "BIT_6,SW sticky bit" "0,1" bitfld.long 0x0 5. "BIT_5,SW sticky bit" "0,1" bitfld.long 0x0 4. "BIT_4,SW sticky bit" "0,1" bitfld.long 0x0 3. "BIT_3,SW sticky bit" "0,1" bitfld.long 0x0 2. "BIT_2,SW sticky bit" "0,1" newline bitfld.long 0x0 1. "BIT_1,SW sticky bit" "0,1" bitfld.long 0x0 0. "BIT_0,SW sticky bit" "0,1" repeat.end repeat 8. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 )(list 0x0 0x4 0x8 0xC 0x10 0x14 0x18 0x1C ) rgroup.long ($2+0x1000)++0x3 line.long 0x0 "LOCK_FUSE_$1,Shadow register for lock fuse word" hexmask.long 0x0 0.--31. 1. "LOCK,shadow register for lock fuse word" repeat.end repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x4 0x8 0xC 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C ) group.long ($2+0x1020)++0x3 line.long 0x0 "FUSE_WORD_$1,Shadow register for fuse word" hexmask.long 0x0 0.--31. 1. "DATA,Shadow register for fuse word" repeat.end repeat 16. (list 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1A 0x1B 0x1C 0x1D 0x1E 0x1F )(list 0x40 0x44 0x48 0x4C 0x50 0x54 0x58 0x5C 0x60 0x64 0x68 0x6C 0x70 0x74 0x78 0x7C ) group.long ($2+0x1020)++0x3 line.long 0x0 "FUSE_WORD_$1,Shadow register for fuse word" hexmask.long 0x0 0.--31. 1. "DATA,Shadow register for fuse word" repeat.end repeat 16. (list 0x20 0x21 0x22 0x23 0x24 0x25 0x26 0x27 0x28 0x29 0x2A 0x2B 0x2C 0x2D 0x2E 0x2F )(list 0x80 0x84 0x88 0x8C 0x90 0x94 0x98 0x9C 0xA0 0xA4 0xA8 0xAC 0xB0 0xB4 0xB8 0xBC ) group.long ($2+0x1020)++0x3 line.long 0x0 "FUSE_WORD_$1,Shadow register for fuse word" hexmask.long 0x0 0.--31. 1. "DATA,Shadow register for fuse word" repeat.end repeat 16. (list 0x30 0x31 0x32 0x33 0x34 0x35 0x36 0x37 0x38 0x39 0x3A 0x3B 0x3C 0x3D 0x3E 0x3F )(list 0xC0 0xC4 0xC8 0xCC 0xD0 0xD4 0xD8 0xDC 0xE0 0xE4 0xE8 0xEC 0xF0 0xF4 0xF8 0xFC ) group.long ($2+0x1020)++0x3 line.long 0x0 "FUSE_WORD_$1,Shadow register for fuse word" hexmask.long 0x0 0.--31. 1. "DATA,Shadow register for fuse word" repeat.end repeat 16. (list 0x40 0x41 0x42 0x43 0x44 0x45 0x46 0x47 0x48 0x49 0x4A 0x4B 0x4C 0x4D 0x4E 0x4F )(list 0x100 0x104 0x108 0x10C 0x110 0x114 0x118 0x11C 0x120 0x124 0x128 0x12C 0x130 0x134 0x138 0x13C ) group.long ($2+0x1020)++0x3 line.long 0x0 "FUSE_WORD_$1,Shadow register for fuse word" hexmask.long 0x0 0.--31. 1. "DATA,Shadow register for fuse word" repeat.end repeat 16. (list 0x50 0x51 0x52 0x53 0x54 0x55 0x56 0x57 0x58 0x59 0x5A 0x5B 0x5C 0x5D 0x5E 0x5F )(list 0x140 0x144 0x148 0x14C 0x150 0x154 0x158 0x15C 0x160 0x164 0x168 0x16C 0x170 0x174 0x178 0x17C ) group.long ($2+0x1020)++0x3 line.long 0x0 "FUSE_WORD_$1,Shadow register for fuse word" hexmask.long 0x0 0.--31. 1. "DATA,Shadow register for fuse word" repeat.end repeat 16. (list 0x60 0x61 0x62 0x63 0x64 0x65 0x66 0x67 0x68 0x69 0x6A 0x6B 0x6C 0x6D 0x6E 0x6F )(list 0x180 0x184 0x188 0x18C 0x190 0x194 0x198 0x19C 0x1A0 0x1A4 0x1A8 0x1AC 0x1B0 0x1B4 0x1B8 0x1BC ) group.long ($2+0x1020)++0x3 line.long 0x0 "FUSE_WORD_$1,Shadow register for fuse word" hexmask.long 0x0 0.--31. 1. "DATA,Shadow register for fuse word" repeat.end repeat 16. (list 0x70 0x71 0x72 0x73 0x74 0x75 0x76 0x77 0x78 0x79 0x7A 0x7B 0x7C 0x7D 0x7E 0x7F )(list 0x1C0 0x1C4 0x1C8 0x1CC 0x1D0 0x1D4 0x1D8 0x1DC 0x1E0 0x1E4 0x1E8 0x1EC 0x1F0 0x1F4 0x1F8 0x1FC ) group.long ($2+0x1020)++0x3 line.long 0x0 "FUSE_WORD_$1,Shadow register for fuse word" hexmask.long 0x0 0.--31. 1. "DATA,Shadow register for fuse word" repeat.end repeat 16. (list 0x80 0x81 0x82 0x83 0x84 0x85 0x86 0x87 0x88 0x89 0x8A 0x8B 0x8C 0x8D 0x8E 0x8F )(list 0x200 0x204 0x208 0x20C 0x210 0x214 0x218 0x21C 0x220 0x224 0x228 0x22C 0x230 0x234 0x238 0x23C ) group.long ($2+0x1020)++0x3 line.long 0x0 "FUSE_WORD_$1,Shadow register for fuse word" hexmask.long 0x0 0.--31. 1. "DATA,Shadow register for fuse word" repeat.end repeat 16. (list 0x90 0x91 0x92 0x93 0x94 0x95 0x96 0x97 0x98 0x99 0x9A 0x9B 0x9C 0x9D 0x9E 0x9F )(list 0x240 0x244 0x248 0x24C 0x250 0x254 0x258 0x25C 0x260 0x264 0x268 0x26C 0x270 0x274 0x278 0x27C ) group.long ($2+0x1020)++0x3 line.long 0x0 "FUSE_WORD_$1,Shadow register for fuse word" hexmask.long 0x0 0.--31. 1. "DATA,Shadow register for fuse word" repeat.end repeat 16. (list 0xA0 0xA1 0xA2 0xA3 0xA4 0xA5 0xA6 0xA7 0xA8 0xA9 0xAA 0xAB 0xAC 0xAD 0xAE 0xAF )(list 0x280 0x284 0x288 0x28C 0x290 0x294 0x298 0x29C 0x2A0 0x2A4 0x2A8 0x2AC 0x2B0 0x2B4 0x2B8 0x2BC ) group.long ($2+0x1020)++0x3 line.long 0x0 "FUSE_WORD_$1,Shadow register for fuse word" hexmask.long 0x0 0.--31. 1. "DATA,Shadow register for fuse word" repeat.end repeat 4. (list 0xB0 0xB1 0xB2 0xB3 )(list 0x2C0 0x2C4 0x2C8 0x2CC ) group.long ($2+0x1020)++0x3 line.long 0x0 "FUSE_WORD_$1,Shadow register for fuse word" hexmask.long 0x0 0.--31. 1. "DATA,Shadow register for fuse word" repeat.end endif tree.end tree "ETHERNET (Ethernet Controller)" sif (CORENAME()=="CORTEXR5F") repeat 2. (increment 1. 1.) (list ad:0xF0170000 ad:0xF06A0000) tree "ETHERNET$1" base $2 tree "EQOS_MAC" group.long 0x0++0x1F line.long 0x0 "MAC_CONFIGURATION,The MAC Configuration Register establishes the operating mode of the MAC." rbitfld.long 0x0 31. "RESERVED_ARPEN,Reserved." "0,1" newline bitfld.long 0x0 28.--30. "SARC,Source Address Insertion or Replacement Control This field controls the source address insertion or replacement for all transmitted packets. Bit 30 specifies which MAC Address register (0 or 1) is used for source address insertion or replacement.." "mti_sa_ctrl_i and ati_sa_ctrl_i input signals..,?,Contents of MAC Addr-0 inserted in SA field,Contents of MAC Addr-0 replaces SA field,?,?,Contents of MAC Addr-1 inserted in SA field,Contents of MAC Addr-1 replaces SA field" newline bitfld.long 0x0 27. "IPC,Checksum Offload When set this bit enables the IPv4 header checksum checking and IPv4 or IPv6 TCP UDP or ICMP payload checksum checking. When this bit is reset the COE function in the receiver is disabled. The Layer 3 and Layer 4 Packet Filter.." "IP header/payload checksum checking is disabled,IP header/payload checksum checking is enabled" newline bitfld.long 0x0 24.--26. "IPG,Inter-Packet Gap These bits control the minimum IPG between packets during transmission. This range of minimum IPG is valid in full-duplex mode. In the half-duplex mode the minimum IPG can be configured only for 64-bit times (IPG = 100). Lower.." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 23. "GPSLCE,Giant Packet Size Limit Control Enable When this bit is set the MAC considers the value in GPSL field in MAC_Ext_Configuration register to declare a received packet as Giant packet. This field must be programmed to more than 1 518 bytes." "Giant Packet Size Limit Control is disabled,Giant Packet Size Limit Control is enabled" newline bitfld.long 0x0 22. "S2KP,IEEE 802.3as Support for 2K Packets When this bit is set the MAC considers all packets with up to 2 000 bytes length as normal packets. When the JE bit is not set the MAC considers all received packets of size more than 2K bytes as Giant packets." "Support upto 2K packet is disabled,Support upto 2K packet is Enabled" newline bitfld.long 0x0 21. "CST,CRC stripping for Type packets When this bit is set the last four bytes (FCS) of all packets of Ether type (type field greater than 1 536) are stripped and dropped before forwarding the packet to the application. Note: For information about how the.." "CRC stripping for Type packets is disabled,CRC stripping for Type packets is enabled" newline bitfld.long 0x0 20. "ACS,Automatic Pad or CRC Stripping When this bit is set the MAC strips the Pad or FCS field on the incoming packets only if the value of the length field is less than 1 536 bytes. All received packets with length field greater than or equal to 1 536.." "Automatic Pad or CRC Stripping is disabled,Automatic Pad or CRC Stripping is enabled" newline bitfld.long 0x0 19. "WD,Watchdog Disable When this bit is set the MAC disables the watchdog timer on the receiver. The MAC can receive packets of up to 16 383 bytes. When this bit is reset the MAC does not allow more than 2 048 bytes (10 240 if JE is set high) of the.." "Watchdog is enabled,Watchdog is disabled" newline bitfld.long 0x0 18. "BE,Packet Burst Enable When this bit is set the MAC allows packet bursting during transmission in the GMII half-duplex mode. 0x0: Packet Burst is disabled 0x1: Packet Burst is enabled" "Packet Burst is disabled,Packet Burst is enabled" newline bitfld.long 0x0 17. "JD,Jabber Disable When this bit is set the MAC disables the jabber timer on the transmitter. The MAC can transfer packets of up to 16 383 bytes. When this bit is reset if the application sends more than 2 048 bytes of data (10 240 if JE is set high).." "Jabber is enabled,Jabber is disabled" newline bitfld.long 0x0 16. "JE,Jumbo Packet Enable When this bit is set the MAC allows jumbo packets of 9 018 bytes (9 022 bytes for VLAN tagged packets) without reporting a giant packet error in the Rx packet status. 0x0: Jumbo packet is disabled 0x1: Jumbo packet is enabled" "Jumbo packet is disabled,Jumbo packet is enabled" newline bitfld.long 0x0 15. "PS,Port Select This bit selects the Ethernet line speed. This bit along with Bit 14 selects the exact line speed. In the 10/100 Mbps-only (always 1) or 1000 Mbps-only (always 0) configurations this bit is read-only (RO) with appropriate value. In.." "For 1000 or 2500 Mbps operations,For 10 or 100 Mbps operations" newline bitfld.long 0x0 14. "FES,Speed This bit selects the speed mode. The mac_speed_o[0] signal reflects the value of this bit. 0x1: 100 Mbps when PS bit is 1 and 2.5 Gbps when PS bit is 0 0x0: 10 Mbps when PS bit is 1 and 1 Gbps when PS bit is 0" "0,1" newline bitfld.long 0x0 13. "DM,Duplex Mode When this bit is set the MAC operates in the full-duplex mode in which it can transmit and receive simultaneously. This bit is RO with default value of 1'b1 in the full-duplex-only configurations. 0x1: Full-duplex mode 0x0: Half-duplex mode" "Half-duplex mode,Full-duplex mode" newline bitfld.long 0x0 12. "LM,Loopback Mode When this bit is set the MAC operates in the loopback mode at GMII or MII. The (G)MII Rx clock input (clk_rx_i) is required for the loopback to work properly. This is because the Tx clock is not internally looped back. 0x0: Loopback is.." "Loopback is disabled,Loopback is enabled" newline bitfld.long 0x0 11. "ECRSFD,Enable Carrier Sense Before Transmission in Full-Duplex Mode When this bit is set the MAC transmitter checks the CRS signal before packet transmission in the full-duplex mode. The MAC starts the transmission only when the CRS signal is low. When.." "ECRSFD is disabled,ECRSFD is enabled" newline bitfld.long 0x0 10. "DO,Disable Receive Own When this bit is set the MAC disables the reception of packets when the gmii_txen_o is asserted in the half-duplex mode. When this bit is reset the MAC receives all packets given by the PHY. This bit is not applicable in the.." "Enable Receive Own,Disable Receive Own" newline bitfld.long 0x0 9. "DCRS,Disable Carrier Sense During Transmission When this bit is set the MAC transmitter ignores the (G)MII CRS signal during packet transmission in the half-duplex mode. As a result no errors are generated because of Loss of Carrier or No Carrier.." "Enable Carrier Sense During Transmission,Disable Carrier Sense During Transmission" newline bitfld.long 0x0 8. "DR,Disable Retry When this bit is set the MAC attempts only one transmission. When a collision occurs on the GMII or MII interface the MAC ignores the current packet transmission and reports a Packet Abort with excessive collision error in the Tx.." "Enable Retry,Disable Retry" newline rbitfld.long 0x0 7. "RESERVED_7,Reserved." "0,1" newline bitfld.long 0x0 5.--6. "BL,Back-Off Limit The back-off limit determines the random integer number (r) of slot time delays (4 096 bit times for 1000/2500 Mbps; 512 bit times for 10/100 Mbps) for which the MAC waits before rescheduling a transmission attempt during retries after.." "k = min,k = min,k = min,k = min" newline bitfld.long 0x0 4. "DC,Deferral Check When this bit is set the deferral check function is enabled in the MAC. The MAC issues a Packet Abort status along with the excessive deferral error bit set in the Tx packet status when the Tx state machine is deferred for more than.." "Deferral check function is disabled,Deferral check function is enabled" newline bitfld.long 0x0 2.--3. "PRELEN,Preamble Length for Transmit packets These bits control the number of preamble bytes that are added to the beginning of every Tx packet. The preamble reduction occurs only when the MAC is operating in the full-duplex mode. 0x2: 3 bytes of preamble.." "?,?,?,Reserved" newline bitfld.long 0x0 1. "TE,Transmitter Enable When this bit is set the Tx state machine of the MAC is enabled for transmission on the GMII or MII interface. When this bit is reset the MAC Tx state machine is disabled after it completes the transmission of the current packet." "Transmitter is disabled,Transmitter is enabled" newline bitfld.long 0x0 0. "RE,Receiver Enable When this bit is set the Rx state machine of the MAC is enabled for receiving packets from the GMII or MII interface. When this bit is reset the MAC Rx state machine is disabled after it completes the reception of the current packet." "Receiver is disabled,Receiver is enabled" line.long 0x4 "MAC_EXT_CONFIGURATION,The MAC Extended Configuration Register establishes the operating mode of the MAC." rbitfld.long 0x4 31. "RESERVED_FHE,Reserved." "0,1" newline rbitfld.long 0x4 30. "RESERVED_30,Reserved." "0,1" newline hexmask.long.byte 0x4 25.--29. 1. "EIPG,Extended Inter-Packet Gap The value in this field is applicable when the EIPGEN bit is set. This field (as Most Significant bits) along with IPG field in MAC_Configuration register gives the minimum IPG greater than 96 bit times in steps of 8 bit.." newline bitfld.long 0x4 24. "EIPGEN,Extended Inter-Packet Gap Enable When this bit is set the MAC interprets EIPG field and IPG field in MAC_Configuration register together as minimum IPG greater than 96 bit times in steps of 8 bit times. When this bit is reset the MAC ignores.." "Extended Inter-Packet Gap is disabled,Extended Inter-Packet Gap is enabled" newline rbitfld.long 0x4 23. "RESERVED_23,Reserved." "0,1" newline rbitfld.long 0x4 20.--22. "RESERVED_HDSMS,Reserved." "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 19. "PDC,Packet Duplication Control When this bit is set the received packet with Multicast/Broadcast Destination address is routed to multiple Receive DMA Channels. The Receive DMA Channels is identified by the DCS field of MAC_Address(#i)_High register.." "Packet Duplication Control is disabled,Packet Duplication Control is enabled" newline bitfld.long 0x4 18. "USP,Unicast Slow Protocol Packet Detect When this bit is set the MAC detects the Slow Protocol packets with unicast address of the station specified in the MAC_Address0_High and MAC_Address0_Low registers. The MAC also detects the Slow Protocol packets.." "Unicast Slow Protocol Packet Detection is disabled,Unicast Slow Protocol Packet Detection is enabled" newline bitfld.long 0x4 17. "SPEN,Slow Protocol Detection Enable When this bit is set MAC processes the Slow Protocol packets (Ether Type 0x8809) and provides the Rx status. The MAC discards the Slow Protocol packets with invalid sub-types. When this bit is reset the MAC forwards.." "Slow Protocol Detection is disabled,Slow Protocol Detection is enabled" newline bitfld.long 0x4 16. "DCRCC,Disable CRC Checking for Received Packets When this bit is set the MAC receiver does not check the CRC field in the received packets. When this bit is reset the MAC receiver always checks the CRC field in the received packets. 0x1: CRC Checking.." "CRC Checking is enabled,CRC Checking is disabled" newline rbitfld.long 0x4 14.--15. "RESERVED_15_14,Reserved." "0,1,2,3" newline hexmask.long.word 0x4 0.--13. 1. "GPSL,Giant Packet Size Limit If the received packet size is greater than the value programmed in this field in units of bytes the MAC declares the received packet as Giant packet. The value programmed in this field must be greater than or equal to 1 518.." line.long 0x8 "MAC_PACKET_FILTER,The MAC Packet Filter register contains the filter controls for receiving packets. Some of the controls from this register go to the address check block of the MAC which performs the first level of address filtering. The second level of.." bitfld.long 0x8 31. "RA,Receive All When this bit is set the MAC Receiver module passes all received packets to the application irrespective of whether they pass the address filter or not. The result of the SA or DA filtering is updated (pass or fail) in the corresponding.." "Receive All is disabled,Receive All is enabled" newline hexmask.long.word 0x8 22.--30. 1. "RESERVED_30_22,Reserved." newline bitfld.long 0x8 21. "DNTU,Drop Non-TCP/UDP over IP Packets When this bit is set the MAC drops the non-TCP or UDP over IP packets. The MAC forward only those packets that are processed by the Layer 4 filter. When this bit is reset the MAC forwards all non-TCP or UDP over IP.." "Forward Non-TCP/UDP over IP Packets,Drop Non-TCP/UDP over IP Packets" newline bitfld.long 0x8 20. "IPFE,Layer 3 and Layer 4 Filter Enable When this bit is set the MAC drops packets that do not match the enabled Layer 3 and Layer 4 filters. If Layer 3 or Layer 4 filters are not enabled for matching this bit does not have any effect. When this bit is.." "Layer 3 and Layer 4 Filters are disabled,Layer 3 and Layer 4 Filters are enabled" newline rbitfld.long 0x8 17.--19. "RESERVED_19_17,Reserved." "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 16. "VTFE,VLAN Tag Filter Enable When this bit is set the MAC drops the VLAN tagged packets that do not match the VLAN Tag. When this bit is reset the MAC forwards all packets irrespective of the match status of the VLAN Tag. 0x0: VLAN Tag Filter is.." "VLAN Tag Filter is disabled,VLAN Tag Filter is enabled" newline hexmask.long.byte 0x8 11.--15. 1. "RESERVED_15_11,Reserved." newline bitfld.long 0x8 10. "HPF,Hash or Perfect Filter When this bit is set the address filter passes a packet if it matches either the perfect filtering or hash filtering as set by the HMC or HUC bit. When this bit is reset and the HUC or HMC bit is set the packet is passed only.." "Hash or Perfect Filter is disabled,Hash or Perfect Filter is enabled" newline bitfld.long 0x8 9. "SAF,Source Address Filter Enable When this bit is set the MAC compares the SA field of the received packets with the values programmed in the enabled SA registers. If the comparison fails the MAC drops the packet. When this bit is reset the MAC.." "SA Filtering is disabled,SA Filtering is enabled" newline bitfld.long 0x8 8. "SAIF,SA Inverse Filtering When this bit is set the Address Check block operates in the inverse filtering mode for SA address comparison. If the SA of a packet matches the values programmed in the SA registers it is marked as failing the SA Address.." "SA Inverse Filtering is disabled,SA Inverse Filtering is enabled" newline bitfld.long 0x8 6.--7. "PCF,Pass Control Packets These bits control the forwarding of all control packets (including unicast and multicast Pause packets). 0x0: MAC filters all control packets from reaching the application 0x2: MAC forwards all control packets to the application.." "MAC filters all control packets from reaching..,MAC forwards all control packets except Pause..,MAC forwards all control packets to the..,MAC forwards the control packets that pass the.." newline bitfld.long 0x8 5. "DBF,Disable Broadcast Packets When this bit is set the AFM module blocks all incoming broadcast packets. In addition it overrides all other filter settings. When this bit is reset the AFM module passes all received broadcast packets. 0x1: Disable.." "Enable Broadcast Packets,Disable Broadcast Packets" newline bitfld.long 0x8 4. "PM,Pass All Multicast When this bit is set it indicates that all received packets with a multicast destination address (first bit in the destination address field is '1') are passed. When this bit is reset filtering of multicast packet depends on HMC.." "Pass All Multicast is disabled,Pass All Multicast is enabled" newline bitfld.long 0x8 3. "DAIF,DA Inverse Filtering When this bit is set the Address Check block operates in inverse filtering mode for the DA address comparison for both unicast and multicast packets. When this bit is reset normal filtering of packets is performed. 0x0: DA.." "DA Inverse Filtering is disabled,DA Inverse Filtering is enabled" newline bitfld.long 0x8 2. "HMC,Hash Multicast When this bit is set the MAC performs the destination address filtering of received multicast packets according to the hash table. When this bit is reset the MAC performs the perfect destination address filtering for multicast.." "Hash Multicast is disabled,Hash Multicast is enabled" newline bitfld.long 0x8 1. "HUC,Hash Unicast When this bit is set the MAC performs the destination address filtering of unicast packets according to the hash table. When this bit is reset the MAC performs a perfect destination address filtering for unicast packets that is it.." "Hash Unicast is disabled,Hash Unicast is enabled" newline bitfld.long 0x8 0. "PR,Promiscuous Mode When this bit is set the Address Filtering module passes all incoming packets irrespective of the destination or source address. The SA or DA Filter Fails status bits of the Rx Status Word are always cleared when PR is set. 0x0:.." "Promiscuous Mode is disabled,Promiscuous Mode is enabled" line.long 0xC "MAC_WATCHDOG_TIMEOUT,The Watchdog Timeout register controls the watchdog timeout for received packets." hexmask.long.tbyte 0xC 9.--31. 1. "RESERVED_31_9,Reserved." newline bitfld.long 0xC 8. "PWE,Programmable Watchdog Enable When this bit is set and the WD bit of the MAC_Configuration register is reset the WTO field is used as watchdog timeout for a received packet. When this bit is cleared the watchdog timeout for a received packet is.." "Programmable Watchdog is disabled,Programmable Watchdog is enabled" newline hexmask.long.byte 0xC 4.--7. 1. "RESERVED_7_4,Reserved." newline hexmask.long.byte 0xC 0.--3. 1. "WTO,Watchdog Timeout When the PWE bit is set and the WD bit of the MAC_Configuration register is reset this field is used as watchdog timeout for a received packet. If the length of a received packet exceeds the value of this field such packet is.." line.long 0x10 "MAC_HASH_TABLE_REG0,The Hash Table Register 0 contains the first 32 bits of the hash table. when the width of the hash table is 128 or 256 bits. You can specify the width of the hash table by using the Hash Table Size option in coreConsultant. The Hash.." hexmask.long 0x10 0.--31. 1. "HT31T0,MAC Hash Table First 32 Bits This field contains the first 32 Bits [31:0] of the Hash table." line.long 0x14 "MAC_HASH_TABLE_REG1,The Hash Table Register 1 contains the second 32 bits of the hash table. You can specify the width of the hash table by using the Hash Table Size option in coreConsultant. The Hash table is used for group address filtering. For hash.." hexmask.long 0x14 0.--31. 1. "HT63T32,MAC Hash Table Second 32 Bits This field contains the second 32 Bits [63:32] of the Hash table." line.long 0x18 "MAC_HASH_TABLE_REG2,The Hash Table Register 2 contains the third 32 bits of the hash table. You can specify the width of the hash table by using the Hash Table Size option in coreConsultant. The Hash table is used for group address filtering. For hash.." hexmask.long 0x18 0.--31. 1. "HT95T64,MAC Hash Table Third 32 Bits This field contains the third 32 Bits [95:64] of the Hash table." line.long 0x1C "MAC_HASH_TABLE_REG3,The Hash Table Register 3 contains the fourth 32 bits of the hash table. You can specify the width of the hash table by using the Hash Table Size option in coreConsultant. The Hash table is used for group address filtering. For hash.." hexmask.long 0x1C 0.--31. 1. "HT127T96,MAC Hash Table Fourth 32 Bits This field contains the fourth 32 Bits [127:96] of the Hash table." group.long 0x50++0xB line.long 0x0 "MAC_VLAN_TAG_CTRL,This register is the redefined format of the MAC VLAN Tag Register. It is used for indirect addressing. It contains the address offset. command type and Busy Bit for CSR access of the Per VLAN Tag registers." bitfld.long 0x0 31. "EIVLRXS,Enable Inner VLAN Tag in Rx Status When this bit is set the MAC provides the inner VLAN Tag in the Rx status. When this bit is reset the MAC does not provide the inner VLAN Tag in Rx status. 0x0: Inner VLAN Tag in Rx status is disabled 0x1:.." "Inner VLAN Tag in Rx status is disabled,Inner VLAN Tag in Rx status is enabled" newline rbitfld.long 0x0 30. "RESERVED_30,Reserved." "0,1" newline bitfld.long 0x0 28.--29. "EIVLS,Enable Inner VLAN Tag Stripping on Receive This field indicates the stripping operation on inner VLAN Tag in received packet. 0x3: Always strip 0x0: Do not strip 0x2: Strip if VLAN filter fails 0x1: Strip if VLAN filter passes" "Do not strip,Strip if VLAN filter passes,Strip if VLAN filter fails,Always strip" newline bitfld.long 0x0 27. "ERIVLT,null 0x0: Inner VLAN tag is disabled 0x1: Inner VLAN tag is enabled" "Inner VLAN tag is disabled,Inner VLAN tag is enabled" newline bitfld.long 0x0 26. "EDVLP,Enable Double VLAN Processing When this bit is set the MAC enables processing of up to two VLAN Tags on Tx and Rx (if present). When this bit is reset the MAC enables processing of up to one VLAN Tag on Tx and Rx (if present). 0x0: Double VLAN.." "Double VLAN Processing is disabled,Double VLAN Processing is enabled" newline bitfld.long 0x0 25. "VTHM,VLAN Tag Hash Table Match Enable When this bit is set the most significant four bits of CRC of VLAN Tag (ones-complement of most significant four bits of CRC of VLAN Tag when ETV bit is reset) are used to index the content of the.." "VLAN Tag Hash Table Match is disabled,VLAN Tag Hash Table Match is enabled" newline bitfld.long 0x0 24. "EVLRXS,Enable VLAN Tag in Rx status When this bit is set MAC provides the outer VLAN Tag in the Rx status. When this bit is reset the MAC does not provide the outer VLAN Tag in Rx status. 0x0: VLAN Tag in Rx status is disabled 0x1: VLAN Tag in Rx.." "VLAN Tag in Rx status is disabled,VLAN Tag in Rx status is enabled" newline rbitfld.long 0x0 23. "RESERVED_23,Reserved." "0,1" newline bitfld.long 0x0 21.--22. "EVLS,Enable VLAN Tag Stripping on Receive This field indicates the stripping operation on the outer VLAN Tag in received packet. 0x3: Always strip 0x0: Do not strip 0x2: Strip if VLAN filter fails 0x1: Strip if VLAN filter passes" "Do not strip,Strip if VLAN filter passes,Strip if VLAN filter fails,Always strip" newline rbitfld.long 0x0 19.--20. "RESERVED_20_19,Reserved." "0,1,2,3" newline bitfld.long 0x0 18. "ESVL,Enable S-VLAN When this bit is set the MAC transmitter and receiver consider the S-VLAN packets (Type = 0x88A8) as valid VLAN tagged packets. 0x0: S-VLAN is disabled 0x1: S-VLAN is enabled" "S-VLAN is disabled,S-VLAN is enabled" newline bitfld.long 0x0 17. "VTIM,VLAN Tag Inverse Match Enable When this bit is set this bit enables the VLAN Tag inverse matching. The packets without matching VLAN Tag are marked as matched. When reset this bit enables the VLAN Tag perfect matching. The packets with matched.." "VLAN Tag Inverse Match is disabled,VLAN Tag Inverse Match is enabled" newline hexmask.long.word 0x0 7.--16. 1. "RESERVED_16_7,Reserved." newline hexmask.long.byte 0x0 2.--6. 1. "OFS,Offset This field holds the address offset of the MAC VLAN Tag Filter Register which the application is trying to access. The width of the field depends on the number of MAC VLAN Tag Registers enabled." newline bitfld.long 0x0 1. "CT,Command Type This bit indicates if the current register access is a read or a write. When set it indicate a read operation. When reset it indicates a write operation. 0x1: Read operation 0x0: Write operation" "Write operation,Read operation" newline bitfld.long 0x0 0. "OB,Operation Busy This bit is set along with a read or write command for initiating the indirect access to per VLAN Tag Filter register. This bit is reset when the read or write command to per VLAN Tag Filter indirect access register is complete. The.." "Operation Busy is disabled,Operation Busy is enabled" line.long 0x4 "MAC_VLAN_TAG_DATA,This register holds the read/write data for Indirect Access of the Per VLAN Tag registers. During the read access. this field contains valid read data only after the OB bit is reset. During the write access. this field should be valid.." hexmask.long.byte 0x4 28.--31. 1. "RESERVED_31_Y,Reserved." newline bitfld.long 0x4 25.--27. "DMACHN,DMA Channel Number The DMA Channel number to which the VLAN Tagged Frame is to be routed if it passes this VLAN Tag Filter is programmed in this field. If the Routing based on VLAN Tag Filter is not necessary this field need not be programmed." "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 24. "DMACHEN,DMA Channel Number Enable This bit is the Enable for the DMA Channel Number value programmed in the field DMACH. When this bit is reset the Routing does not occur based on VLAN Filter result. The frame is routed based on DA Based DMA Channel.." "DMA Channel Number is disabled,DMA Channel Number is enabled" newline rbitfld.long 0x4 21.--23. "RESERVED_23_21,Reserved." "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 20. "ERIVLT,Enable Inner VLAN Tag Comparison This bit is valid only when VLAN Tag Enable of the Filter is set. When this bit and the EDVLP field are set the MAC receiver enables operation on the inner VLAN Tag (if present). When this bit is reset the MAC.." "Inner VLAN tag comparison is disabled,Inner VLAN tag comparison is enabled" newline bitfld.long 0x4 19. "ERSVLM,Enable S-VLAN Match for received Frames This bit is valid only when VLAN Tag Enable of the Filter is set. When this bit is set the MAC receiver enables filtering or matching for S-VLAN (Type = 0x88A8) packets. When this bit is reset the MAC.." "Receive S-VLAN Match is disabled,Receive S-VLAN Match is enabled" newline bitfld.long 0x4 18. "DOVLTC,Disable VLAN Type Comparison This bit is valid only when VLAN Tag Enable of the Filter is set. When this bit is set the MAC does not check whether the VLAN Tag specified by the Enable Inner VLAN Tag Comparison bit is of type S-VLAN or C-VLAN." "VLAN type comparison is enabled,VLAN type comparison is disabled" newline bitfld.long 0x4 17. "ETV,12bits or 16bits VLAN comparison This bit is valid only when VEN of the Filter is set. When this bit is set a 12-bit VLAN identifier is used for comparing and filtering instead of the complete 16-bit VLAN tag. Bits [11:0] of VLAN tag are compared.." "0,1" newline bitfld.long 0x4 16. "VEN,VLAN Tag Enable This bit is used to enable or disable the VLAN Tag. When this bit is set the MAC compares the VLAN Tag of received packet with the VLAN Tag ID. When this bit is reset no comparison is performed irrespective of the programming of the.." "VLAN Tag is disabled,VLAN Tag is enabled" newline hexmask.long.word 0x4 0.--15. 1. "VID,VLAN Tag ID This field holds the VLAN Tag value which is used by the MAC for perfect comparison. It is valid when VLAN Tag Enable is set." line.long 0x8 "MAC_VLAN_HASH_TABLE,When VTHM bit of the MAC_VLAN_Tag register is set. the 16-bit VLAN Hash Table register is used for group address filtering based on the VLAN tag. For hash filtering. the content of the 16-bit VLAN tag or 12-bit VLAN ID (based on the.." hexmask.long.word 0x8 16.--31. 1. "RESERVED_31_16,Reserved." newline hexmask.long.word 0x8 0.--15. 1. "VLHT,VLAN Hash Table This field contains the 16-bit VLAN Hash Table." group.long 0x60++0x7 line.long 0x0 "MAC_VLAN_INCL,The VLAN Tag Inclusion or Replacement register contains the VLAN tag for insertion or replacement in the Transmit packets. It also contains the VLAN tag insertion controls." rbitfld.long 0x0 31. "BUSY,Busy This bit indicates the status of the read/write operation of indirect access to the queue/channel specific VLAN inclusion register. For write operation write to a register is complete when this bit is reset. For read operation the read data is.." "Busy status not detected,Busy status detected" newline bitfld.long 0x0 30. "RDWR,Read write control This bit controls the read or write operation for indirectly accessing the queue/channel specific VLAN Inclusion register. When set indicates write operation and when reset indicates read operation. This does not have any effect.." "Read operation of indirect access,Write operation of indirect access" newline rbitfld.long 0x0 27.--29. "RESERVED_29_Y,Reserved." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 24.--26. "ADDR,Address This field selects one of the queue/channel specific VLAN Inclusion register for read/write access. This does not have any effect when CBTI is reset." "0,1,2,3,4,5,6,7" newline rbitfld.long 0x0 22.--23. "RESERVED_23_22,Reserved." "0,1,2,3" newline bitfld.long 0x0 21. "CBTI,Channel based tag insertion When this bit is set outer VLAN tag is inserted for every packets transmitted by the MAC. The tag value is taken from the queue/channel specific VLAN tag register. The VLTI VLP VLC and VLT fields of this register are.." "Channel based tag insertion is disabled,Channel based tag insertion is enabled" newline bitfld.long 0x0 20. "VLTI,VLAN Tag Input When this bit is set it indicates that the VLAN tag to be inserted or replaced in Tx packet should be taken from: - The Tx descriptor 0x0: VLAN Tag Input is disabled 0x1: VLAN Tag Input is enabled" "VLAN Tag Input is disabled,VLAN Tag Input is enabled" newline bitfld.long 0x0 19. "CSVL,C-VLAN or S-VLAN When this bit is set S-VLAN type (0x88A8) is inserted or replaced in the 13th and 14th bytes of transmitted packets. When this bit is reset C-VLAN type (0x8100) is inserted or replaced in the 13th and 14th bytes of transmitted.." "C-VLAN type,S-VLAN type" newline bitfld.long 0x0 18. "VLP,VLAN Priority Control When this bit is set the control bits[17:16] are used for VLAN deletion insertion or replacement. When this bit is reset the mti_vlan_ctrl_i control input is used and bits[17:16] are ignored. 0x0: VLAN Priority Control is.." "VLAN Priority Control is disabled,VLAN Priority Control is enabled" newline bitfld.long 0x0 16.--17. "VLC,VLAN Tag Control in Transmit Packets - 2'b00: No VLAN tag deletion insertion or replacement - 2'b01: VLAN tag deletion The MAC removes the VLAN type (bytes 13 and 14) and VLAN tag (bytes 15 and 16) of all transmitted packets with VLAN tags. -.." "No VLAN tag deletion,VLAN tag deletion,VLAN tag insertion,VLAN tag replacement" newline hexmask.long.word 0x0 0.--15. 1. "VLT,VLAN Tag for Transmit Packets This field contains the value of the VLAN tag to be inserted or replaced. The value must only be changed when the transmit lines are inactive or during the initialization phase. Bits[15:13] are the User Priority field.." line.long 0x4 "MAC_INNER_VLAN_INCL,The Inner VLAN Tag Inclusion or Replacement register contains the inner VLAN tag to be inserted or replaced in the Transmit packet. It also contains the inner VLAN tag insertion controls." hexmask.long.word 0x4 21.--31. 1. "RESERVED_31_21,Reserved." newline bitfld.long 0x4 20. "VLTI,VLAN Tag Input When this bit is set it indicates that the VLAN tag to be inserted or replaced in Tx packet should be taken from: - The Tx descriptor 0x0: VLAN Tag Input is disabled 0x1: VLAN Tag Input is enabled" "VLAN Tag Input is disabled,VLAN Tag Input is enabled" newline bitfld.long 0x4 19. "CSVL,C-VLAN or S-VLAN When this bit is set S-VLAN type (0x88A8) is inserted or replaced in the 13th and 14th bytes of transmitted packets. When this bit is reset C-VLAN type (0x8100) is inserted or replaced in the 13th and 14th bytes of transmitted.." "C-VLAN type,S-VLAN type" newline bitfld.long 0x4 18. "VLP,VLAN Priority Control When this bit is set the VLC field is used for VLAN deletion insertion or replacement. When this bit is reset the mti_vlan_ctrl_i control input is used and the VLC field is ignored. 0x0: VLAN Priority Control is disabled.." "VLAN Priority Control is disabled,VLAN Priority Control is enabled" newline bitfld.long 0x4 16.--17. "VLC,VLAN Tag Control in Transmit Packets - 2'b00: No VLAN tag deletion insertion or replacement - 2'b01: VLAN tag deletion The MAC removes the VLAN type (bytes 17 and 18) and VLAN tag (bytes 19 and 20) of all transmitted packets with VLAN tags. -.." "No VLAN tag deletion,VLAN tag deletion,VLAN tag insertion,VLAN tag replacement" newline hexmask.long.word 0x4 0.--15. 1. "VLT,VLAN Tag for Transmit Packets This field contains the value of the VLAN tag to be inserted or replaced. The value must only be changed when the transmit lines are inactive or during the initialization phase. Bits[15:13] are the User Priority field.." group.long 0x70++0x13 line.long 0x0 "MAC_Q0_TX_FLOW_CTRL,The Flow Control register controls the generation and reception of the Control (Pause Command) packets by the Flow control module of the MAC. A Write to a register with the Busy bit set to 1 triggers the Flow Control block to generate.." hexmask.long.word 0x0 16.--31. 1. "PT,Pause Time This field holds the value to be used in the Pause Time field in the Tx control packet. If the Pause Time bits are configured to be double-synchronized to the (G)MII clock domain consecutive writes to this register should be performed only.." newline hexmask.long.byte 0x0 8.--15. 1. "RESERVED_15_8,Reserved." newline bitfld.long 0x0 7. "DZPQ,Disable Zero-Quanta Pause When this bit is set it disables the automatic generation of the zero-quanta Pause packets on de-assertion of the flow-control signal from the FIFO layer (MTL or external sideband flow control signal sbd_flowctrl_i or.." "Zero-Quanta Pause packet generation is enabled,Zero-Quanta Pause packet generation is disabled" newline bitfld.long 0x0 4.--6. "PLT,Pause Low Threshold This field configures the threshold of the Pause timer at which the input flow control signal mti_flowctrl_i (or sbd_flowctrl_i) is checked for automatic retransmission of the Pause packet. The threshold values should be always.." "Pause Time minus 4 Slot Times,Pause Time minus 28 Slot Times,Pause Time minus 36 Slot Times,Pause Time minus 144 Slot Times,Pause Time minus 256 Slot Times,Pause Time minus 512 Slot Times,Reserved,?" newline rbitfld.long 0x0 2.--3. "RESERVED_3_2,Reserved." "0,1,2,3" newline bitfld.long 0x0 1. "TFE,Transmit Flow Control Enable Full-Duplex Mode: In the full-duplex mode when this bit is set the MAC enables the flow control operation to Tx Pause packets. When this bit is reset the flow control operation in the MAC is disabled and the MAC does.." "Transmit Flow Control is disabled,Transmit Flow Control is enabled" newline bitfld.long 0x0 0. "FCB_BPA,Flow Control Busy or Backpressure Activate This bit initiates a Pause packet in the full-duplex mode and activates the backpressure function in the half-duplex mode if the TFE bit is set. Full-Duplex Mode: In the full-duplex mode this bit should.." "Flow Control Busy or Backpressure Activate is..,Flow Control Busy or Backpressure Activate is.." line.long 0x4 "MAC_Q1_TX_FLOW_CTRL,This register controls the generation of PFC Control packets of priorities mapped as per the PSRQi field in the MAC_RxQ_Ctrl2/MAC_RxQ_Ctrl3 registers." hexmask.long.word 0x4 16.--31. 1. "PT,Pause Time This field holds the value to be used in the Pause Time field in the Tx control packet. If the Pause Time bits are configured to be double-synchronized to the (G)MII clock domain consecutive writes to this register should be performed only.." newline hexmask.long.byte 0x4 8.--15. 1. "RESERVED_15_8,Reserved." newline bitfld.long 0x4 7. "DZPQ,Disable Zero-Quanta Pause When this bit is set it disables the automatic generation of the zero-quanta Pause packets on de-assertion of the flow-control signal from the FIFO layer (MTL or external sideband flow control signal sbd_flowctrl_i or.." "Zero-Quanta Pause packet generation is enabled,Zero-Quanta Pause packet generation is disabled" newline bitfld.long 0x4 4.--6. "PLT,Pause Low Threshold This field configures the threshold of the Pause timer at which the input flow control signal mti_flowctrl_i (or sbd_flowctrl_i) is checked for automatic retransmission of the Pause packet. The threshold values should be always.." "Pause Time minus 4 Slot Times,Pause Time minus 28 Slot Times,Pause Time minus 36 Slot Times,Pause Time minus 144 Slot Times,Pause Time minus 256 Slot Times,Pause Time minus 512 Slot Times,Reserved,?" newline rbitfld.long 0x4 2.--3. "RESERVED_3_2,Reserved." "0,1,2,3" newline bitfld.long 0x4 1. "TFE,Transmit Flow Control Enable When this bit is set in full-duplex mode the MAC enables the flow control operation to Tx Pause packets. When this bit is reset the flow control operation in the MAC is disabled and the MAC does not transmit any Pause.." "Transmit Flow Control is disabled,Transmit Flow Control is enabled" newline bitfld.long 0x4 0. "FCB_BPA,Flow Control Busy This bit initiates a PFC packet if the TFE bit is set. To initiate a PFC packet the application must set this bit to 1'b1. During Control packet transfer this bit continues to be set to indicate that a packet transmission is.." "Flow Control Busy or Backpressure Activate is..,Flow Control Busy or Backpressure Activate is.." line.long 0x8 "MAC_Q2_TX_FLOW_CTRL,This register controls the generation of PFC Control packets of priorities mapped as per the PSRQi field in the MAC_RxQ_Ctrl2/MAC_RxQ_Ctrl3 registers." hexmask.long.word 0x8 16.--31. 1. "PT,Pause Time This field holds the value to be used in the Pause Time field in the Tx control packet. If the Pause Time bits are configured to be double-synchronized to the (G)MII clock domain consecutive writes to this register should be performed only.." newline hexmask.long.byte 0x8 8.--15. 1. "RESERVED_15_8,Reserved." newline bitfld.long 0x8 7. "DZPQ,Disable Zero-Quanta Pause When this bit is set it disables the automatic generation of the zero-quanta Pause packets on de-assertion of the flow-control signal from the FIFO layer (MTL or external sideband flow control signal sbd_flowctrl_i or.." "Zero-Quanta Pause packet generation is enabled,Zero-Quanta Pause packet generation is disabled" newline bitfld.long 0x8 4.--6. "PLT,Pause Low Threshold This field configures the threshold of the Pause timer at which the input flow control signal mti_flowctrl_i (or sbd_flowctrl_i) is checked for automatic retransmission of the Pause packet. The threshold values should be always.." "Pause Time minus 4 Slot Times,Pause Time minus 28 Slot Times,Pause Time minus 36 Slot Times,Pause Time minus 144 Slot Times,Pause Time minus 256 Slot Times,Pause Time minus 512 Slot Times,Reserved,?" newline rbitfld.long 0x8 2.--3. "RESERVED_3_2,Reserved." "0,1,2,3" newline bitfld.long 0x8 1. "TFE,Transmit Flow Control Enable When this bit is set in full-duplex mode the MAC enables the flow control operation to Tx Pause packets. When this bit is reset the flow control operation in the MAC is disabled and the MAC does not transmit any Pause.." "Transmit Flow Control is disabled,Transmit Flow Control is enabled" newline bitfld.long 0x8 0. "FCB_BPA,Flow Control Busy This bit initiates a PFC packet if the TFE bit is set. To initiate a PFC packet the application must set this bit to 1'b1. During Control packet transfer this bit continues to be set to indicate that a packet transmission is.." "Flow Control Busy or Backpressure Activate is..,Flow Control Busy or Backpressure Activate is.." line.long 0xC "MAC_Q3_TX_FLOW_CTRL,This register controls the generation of PFC Control packets of priorities mapped as per the PSRQi field in the MAC_RxQ_Ctrl2/MAC_RxQ_Ctrl3 registers." hexmask.long.word 0xC 16.--31. 1. "PT,Pause Time This field holds the value to be used in the Pause Time field in the Tx control packet. If the Pause Time bits are configured to be double-synchronized to the (G)MII clock domain consecutive writes to this register should be performed only.." newline hexmask.long.byte 0xC 8.--15. 1. "RESERVED_15_8,Reserved." newline bitfld.long 0xC 7. "DZPQ,Disable Zero-Quanta Pause When this bit is set it disables the automatic generation of the zero-quanta Pause packets on de-assertion of the flow-control signal from the FIFO layer (MTL or external sideband flow control signal sbd_flowctrl_i or.." "Zero-Quanta Pause packet generation is enabled,Zero-Quanta Pause packet generation is disabled" newline bitfld.long 0xC 4.--6. "PLT,Pause Low Threshold This field configures the threshold of the Pause timer at which the input flow control signal mti_flowctrl_i (or sbd_flowctrl_i) is checked for automatic retransmission of the Pause packet. The threshold values should be always.." "Pause Time minus 4 Slot Times,Pause Time minus 28 Slot Times,Pause Time minus 36 Slot Times,Pause Time minus 144 Slot Times,Pause Time minus 256 Slot Times,Pause Time minus 512 Slot Times,Reserved,?" newline rbitfld.long 0xC 2.--3. "RESERVED_3_2,Reserved." "0,1,2,3" newline bitfld.long 0xC 1. "TFE,Transmit Flow Control Enable When this bit is set in full-duplex mode the MAC enables the flow control operation to Tx Pause packets. When this bit is reset the flow control operation in the MAC is disabled and the MAC does not transmit any Pause.." "Transmit Flow Control is disabled,Transmit Flow Control is enabled" newline bitfld.long 0xC 0. "FCB_BPA,Flow Control Busy This bit initiates a PFC packet if the TFE bit is set. To initiate a PFC packet the application must set this bit to 1'b1. During Control packet transfer this bit continues to be set to indicate that a packet transmission is.." "Flow Control Busy or Backpressure Activate is..,Flow Control Busy or Backpressure Activate is.." line.long 0x10 "MAC_Q4_TX_FLOW_CTRL,This register controls the generation of PFC Control packets of priorities mapped as per the PSRQi field in the MAC_RxQ_Ctrl2/MAC_RxQ_Ctrl3 registers." hexmask.long.word 0x10 16.--31. 1. "PT,Pause Time This field holds the value to be used in the Pause Time field in the Tx control packet. If the Pause Time bits are configured to be double-synchronized to the (G)MII clock domain consecutive writes to this register should be performed only.." newline hexmask.long.byte 0x10 8.--15. 1. "RESERVED_15_8,Reserved." newline bitfld.long 0x10 7. "DZPQ,Disable Zero-Quanta Pause When this bit is set it disables the automatic generation of the zero-quanta Pause packets on de-assertion of the flow-control signal from the FIFO layer (MTL or external sideband flow control signal sbd_flowctrl_i or.." "Zero-Quanta Pause packet generation is enabled,Zero-Quanta Pause packet generation is disabled" newline bitfld.long 0x10 4.--6. "PLT,Pause Low Threshold This field configures the threshold of the Pause timer at which the input flow control signal mti_flowctrl_i (or sbd_flowctrl_i) is checked for automatic retransmission of the Pause packet. The threshold values should be always.." "Pause Time minus 4 Slot Times,Pause Time minus 28 Slot Times,Pause Time minus 36 Slot Times,Pause Time minus 144 Slot Times,Pause Time minus 256 Slot Times,Pause Time minus 512 Slot Times,Reserved,?" newline rbitfld.long 0x10 2.--3. "RESERVED_3_2,Reserved." "0,1,2,3" newline bitfld.long 0x10 1. "TFE,Transmit Flow Control Enable When this bit is set in full-duplex mode the MAC enables the flow control operation to Tx Pause packets. When this bit is reset the flow control operation in the MAC is disabled and the MAC does not transmit any Pause.." "Transmit Flow Control is disabled,Transmit Flow Control is enabled" newline bitfld.long 0x10 0. "FCB_BPA,Flow Control Busy This bit initiates a PFC packet if the TFE bit is set. To initiate a PFC packet the application must set this bit to 1'b1. During Control packet transfer this bit continues to be set to indicate that a packet transmission is.." "Flow Control Busy or Backpressure Activate is..,Flow Control Busy or Backpressure Activate is.." group.long 0x90++0x1F line.long 0x0 "MAC_RX_FLOW_CTRL,The Receive Flow Control register controls the pausing of MAC Transmit based on the received Pause packet." hexmask.long.tbyte 0x0 9.--31. 1. "RESERVED_31_9,Reserved." newline bitfld.long 0x0 8. "PFCE,Priority Based Flow Control Enable When this bit is set it enables generation and reception of priority-based flow control (PFC) packets. When this bit is reset it enables generation and reception of 802.3x Pause control packets. 0x0: Priority.." "Priority Based Flow Control is disabled,Priority Based Flow Control is enabled" newline hexmask.long.byte 0x0 2.--7. 1. "RESERVED_7_2,Reserved." newline bitfld.long 0x0 1. "UP,Unicast Pause Packet Detect A pause packet is processed when it has the unique multicast address specified in the IEEE 802.3. When this bit is set the MAC can also detect Pause packets with unicast address of the station. This unicast address should.." "Unicast Pause Packet Detect disabled,Unicast Pause Packet Detect enabled" newline bitfld.long 0x0 0. "RFE,Receive Flow Control Enable When this bit is set and the MAC is operating in full-duplex mode the MAC decodes the received Pause packet and disables its transmitter for a specified (Pause) time. When this bit is reset or the MAC is operating in.." "Receive Flow Control is disabled,Receive Flow Control is enabled" line.long 0x4 "MAC_RXQ_CTRL4,The Receive Queue Control 4 register controls the routing of unicast and multicast packets that fail the Destination or Source address filter to the Rx queues." hexmask.long.word 0x4 20.--31. 1. "RESERVED_31_Y,Reserved." newline bitfld.long 0x4 17.--19. "VFFQ,VLAN Tag Filter Fail Packets Queue This field holds the Rx queue number to which the tagged packets failing the Destination or Source Address filter (and UFFQE/MFFQE not enabled) or failing the VLAN tag filter must be routed to. This field is valid.." "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 16. "VFFQE,VLAN Tag Filter Fail Packets Queuing Enable When this bit is set the tagged packets which fail the Destination or Source address filter or fail the VLAN tag filter are routed to the Rx Queue Number programmed in the VFFQ. When this bit is reset.." "VLAN tag Filter Fail Packets Queuing is disabled,VLAN tag Filter Fail Packets Queuing is enabled" newline hexmask.long.byte 0x4 12.--15. 1. "RESERVED_15_Y,Reserved." newline bitfld.long 0x4 9.--11. "MFFQ,Multicast Address Filter Fail Packets Queue. This field holds the Rx queue number to which the Multicast packets failing the Destination or Source Address filter are routed to. This field is valid only when the MFFQE bit is set." "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 8. "MFFQE,Multicast Address Filter Fail Packets Queuing Enable. When this bit is set the Multicast packets which fail the Destination or Source address filter is routed to the Rx Queue Number programmed in the MFFQ. When this bit is reset the Multicast.." "Multicast Address Filter Fail Packets Queuing is..,Multicast Address Filter Fail Packets Queuing is.." newline hexmask.long.byte 0x4 4.--7. 1. "RESERVED_7_Y,Reserved." newline bitfld.long 0x4 1.--3. "UFFQ,Unicast Address Filter Fail Packets Queue. This field holds the Rx queue number to which the Unicast packets failing the Destination or Source Address filter are routed to. This field is valid only when the UFFQE bit is set." "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 0. "UFFQE,Unicast Address Filter Fail Packets Queuing Enable. When this bit is set the Unicast packets which fail the Destination or Source address filter is routed to the Rx Queue Number programmed in the UFFQ. When this bit is reset the Unicast packets.." "Unicast Address Filter Fail Packets Queuing is..,Unicast Address Filter Fail Packets Queuing is.." line.long 0x8 "MAC_TXQ_PRTY_MAP0,The Transmit Queue Priority Mapping 0 register contains the priority values assigned to Tx Queue 0 through Tx Queue 3." hexmask.long.byte 0x8 24.--31. 1. "PSTQ3,Priorities Selected in Transmit Queue 3 This bit is similar to the PSTQ0 bit." newline hexmask.long.byte 0x8 16.--23. 1. "PSTQ2,Priorities Selected in Transmit Queue 2 This bit is similar to the PSTQ0 bit." newline hexmask.long.byte 0x8 8.--15. 1. "PSTQ1,Priorities Selected in Transmit Queue 1 This bit is similar to the PSTQ0 bit." newline hexmask.long.byte 0x8 0.--7. 1. "PSTQ0,Priorities Selected in Transmit Queue 0 This field holds the priorities assigned to Tx Queue 0 by the software. This field determines if Tx Queue 0 should be blocked from transmitting specified pause time when a PFC packet is received with.." line.long 0xC "MAC_TXQ_PRTY_MAP1,The Transmit Queue Priority Mapping 1 register contains the priority values assigned to Tx Queue 4 through Tx Queue 7." hexmask.long.byte 0xC 24.--31. 1. "RESERVED_PSTQ7,Reserved." newline hexmask.long.byte 0xC 16.--23. 1. "RESERVED_PSTQ6,Reserved." newline hexmask.long.byte 0xC 8.--15. 1. "RESERVED_PSTQ5,Reserved." newline hexmask.long.byte 0xC 0.--7. 1. "PSTQ4,Priorities Selected in Transmit Queue 4 This field holds the priorities assigned to Tx Queue 4 by the software. This field determines if Tx Queue 4 should be blocked from transmitting specified pause time when a PFC packet is received with.." line.long 0x10 "MAC_RXQ_CTRL0,The Receive Queue Control 0 register controls the queue management in the MAC Receiver. Note: In multiple Rx queues configuration. all the queues are disabled by default. Enable the Rx queue by programming the corresponding field in this.." hexmask.long.word 0x10 16.--31. 1. "RESERVED_31_16,Reserved." newline rbitfld.long 0x10 14.--15. "RESERVED_RXQ7EN,Reserved." "0,1,2,3" newline rbitfld.long 0x10 12.--13. "RESERVED_RXQ6EN,Reserved." "0,1,2,3" newline rbitfld.long 0x10 10.--11. "RESERVED_RXQ5EN,Reserved." "0,1,2,3" newline bitfld.long 0x10 8.--9. "RXQ4EN,Receive Queue 4 Enable This field is similar to the RXQ0EN field. 0x0: Queue not enabled 0x1: Queue enabled for AV 0x2: Queue enabled for DCB/Generic 0x3: Reserved" "Queue not enabled,Queue enabled for AV,Queue enabled for DCB/Generic,Reserved" newline bitfld.long 0x10 6.--7. "RXQ3EN,Receive Queue 3 Enable This field is similar to the RXQ0EN field. 0x0: Queue not enabled 0x1: Queue enabled for AV 0x2: Queue enabled for DCB/Generic 0x3: Reserved" "Queue not enabled,Queue enabled for AV,Queue enabled for DCB/Generic,Reserved" newline bitfld.long 0x10 4.--5. "RXQ2EN,Receive Queue 2 Enable This field is similar to the RXQ0EN field. 0x0: Queue not enabled 0x1: Queue enabled for AV 0x2: Queue enabled for DCB/Generic 0x3: Reserved" "Queue not enabled,Queue enabled for AV,Queue enabled for DCB/Generic,Reserved" newline bitfld.long 0x10 2.--3. "RXQ1EN,Receive Queue 1 Enable This field is similar to the RXQ0EN field. 0x0: Queue not enabled 0x1: Queue enabled for AV 0x2: Queue enabled for DCB/Generic 0x3: Reserved" "Queue not enabled,Queue enabled for AV,Queue enabled for DCB/Generic,Reserved" newline bitfld.long 0x10 0.--1. "RXQ0EN,Receive Queue 0 Enable This field indicates whether Rx Queue 0 is enabled for AV or DCB. 0x0: Queue not enabled 0x1: Queue enabled for AV 0x2: Queue enabled for DCB/Generic 0x3: Reserved" "Queue not enabled,Queue enabled for AV,Queue enabled for DCB/Generic,Reserved" line.long 0x14 "MAC_RXQ_CTRL1,The Receive Queue Control 1 register controls the routing of multicast. broadcast. AV. DCB. and untagged packets to the Rx queues." hexmask.long.byte 0x14 27.--31. 1. "RESERVED_31_Y,Reserved." newline bitfld.long 0x14 24.--26. "FPRQ,Frame Preemption Residue Queue This field holds the Rx queue number to which the residual preemption frames must be forwarded. Preemption frames that are tagged and pass the SA/DA/VLAN filtering are routed based on PSRQ and all other frames are.." "0,1,2,3,4,5,6,7" newline bitfld.long 0x14 22.--23. "TPQC,Tagged PTP over Ethernet Packets Queuing Control. This field controls the routing of the VLAN Tagged PTPoE packets. If DWC_EQOS_AV_ENABLE is selected in the configuration the following programmable options are allowed. - 2'b00: VLAN Tagged PTPoE.." "VLAN Tagged PTPoE packets are routed as generic..,VLAN Tagged PTPoE packets are routed to Rx..,VLAN Tagged PTPoE packets are routed to only AV..,Reserved" newline bitfld.long 0x14 21. "TACPQE,Tagged AV Control Packets Queuing Enable. When set the MAC routes the received Tagged AV Control packets to the Rx queue specified by AVCPQ field. When reset the MAC routes the received Tagged AV Control packets based on the tag priority.." "Tagged AV Control Packets Queuing is disabled,Tagged AV Control Packets Queuing is enabled" newline bitfld.long 0x14 20. "MCBCQEN,Multicast and Broadcast Queue Enable This bit specifies that Multicast or Broadcast packets routing to the Rx Queue is enabled and the Multicast or Broadcast packets must be routed to Rx Queue specified in MCBCQ field. 0x0: Multicast and.." "Multicast and Broadcast Queue is disabled,Multicast and Broadcast Queue is enabled" newline rbitfld.long 0x14 19. "RESERVED_19,Reserved." "0,1" newline bitfld.long 0x14 16.--18. "MCBCQ,Multicast and Broadcast Queue This field specifies the Rx Queue onto which Multicast or Broadcast Packets are routed. Any Rx Queue enabled for Generic/DCB/AV traffic can be used to route the Multicast or Broadcast Packets. 0x0: Receive Queue 0 0x1:.." "Receive Queue 0,Receive Queue 1,Receive Queue 2,Receive Queue 3,Receive Queue 4,Receive Queue 5,Receive Queue 6,Receive Queue 7" newline rbitfld.long 0x14 15. "RESERVED_15,Reserved." "0,1" newline bitfld.long 0x14 12.--14. "UPQ,Untagged Packet Queue This field indicates the Rx Queue to which Untagged Packets are to be routed. Any Rx Queue enabled for Generic/DCB/AV traffic can be used to route the Untagged Packets. 0x0: Receive Queue 0 0x1: Receive Queue 1 0x2: Receive.." "Receive Queue 0,Receive Queue 1,Receive Queue 2,Receive Queue 3,Receive Queue 4,Receive Queue 5,Receive Queue 6,Receive Queue 7" newline rbitfld.long 0x14 11. "RESERVED_11,Reserved." "0,1" newline bitfld.long 0x14 8.--10. "DCBCPQ,DCB Control Packets Queue This field specifies the Rx queue on which the received DCB control packets are routed. The DCB data packets are routed based on the PSRQ field of the Transmit Flow Control Register of corresponding queue. 0x0: Receive.." "Receive Queue 0,Receive Queue 1,Receive Queue 2,Receive Queue 3,Receive Queue 4,Receive Queue 5,Receive Queue 6,Receive Queue 7" newline rbitfld.long 0x14 7. "RESERVED_7,Reserved." "0,1" newline bitfld.long 0x14 4.--6. "PTPQ,PTP Packets Queue This field specifies the Rx queue on which the PTP packets sent over the Ethernet payload (not over IPv4 or IPv6) are routed. When the AV8021ASMEN bit of MAC_Timestamp_Control register is set only untagged PTP over Ethernet.." "Receive Queue 0,Receive Queue 1,Receive Queue 2,Receive Queue 3,Receive Queue 4,Receive Queue 5,Receive Queue 6,Receive Queue 7" newline rbitfld.long 0x14 3. "RESERVED_3,Reserved." "0,1" newline bitfld.long 0x14 0.--2. "AVCPQ,AV Untagged Control Packets Queue This field specifies the Receive queue on which the received AV tagged and untagged control packets are routed. The AV tagged (when TACPQE bit is set) and untagged control packets are routed to Receive queue.." "Receive Queue 0,Receive Queue 1,Receive Queue 2,Receive Queue 3,Receive Queue 4,Receive Queue 5,Receive Queue 6,Receive Queue 7" line.long 0x18 "MAC_RXQ_CTRL2,This register controls the routing of tagged packets based on the USP (user Priority) field of the received packets to the RxQueues 0 to 3." hexmask.long.byte 0x18 24.--31. 1. "PSRQ3,Priorities Selected in the Receive Queue 3 This field decides the priorities assigned to Rx Queue 3. All packets with priorities that match the values set in this field are routed to Rx Queue 3. For example if PSRQ3[6 3] are set packets with USP.." newline hexmask.long.byte 0x18 16.--23. 1. "PSRQ2,Priorities Selected in the Receive Queue 2 This field decides the priorities assigned to Rx Queue 2. All packets with priorities that match the values set in this field are routed to Rx Queue 2. For example if PSRQ2[1 0] are set packets with USP.." newline hexmask.long.byte 0x18 8.--15. 1. "PSRQ1,Priorities Selected in the Receive Queue 1 This field decides the priorities assigned to Rx Queue 1. All packets with priorities that match the values set in this field are routed to Rx Queue 1. For example if PSRQ1[4] is set packets with USP.." newline hexmask.long.byte 0x18 0.--7. 1. "PSRQ0,Priorities Selected in the Receive Queue 0 This field decides the priorities assigned to Rx Queue 0. All packets with priorities that match the values set in this field are routed to Rx Queue 0. For example if PSRQ0[5] is set packets with USP.." line.long 0x1C "MAC_RXQ_CTRL3,This register controls the routing of tagged packets based on the USP (user Priority) field of the received packets to the RxQueues 4 to 7." hexmask.long.byte 0x1C 24.--31. 1. "RESERVED_PSRQ7,Reserved." newline hexmask.long.byte 0x1C 16.--23. 1. "RESERVED_PSRQ6,Reserved." newline hexmask.long.byte 0x1C 8.--15. 1. "RESERVED_PSRQ5,Reserved." newline hexmask.long.byte 0x1C 0.--7. 1. "PSRQ4,Priorities Selected in the Receive Queue 4 This field decides the priorities assigned to Rx Queue 4. All packets with priorities that match the values set in this field are routed to Rx Queue 4. For example if PSRQ4[7:4] is set packets with USP.." rgroup.long 0xB0++0x3 line.long 0x0 "MAC_INTERRUPT_STATUS,The Interrupt Status register contains the status of interrupts." hexmask.long.word 0x0 21.--31. 1. "RESERVED_31_21,Reserved." newline bitfld.long 0x0 20. "MFRIS,MMC FPE Receive Interrupt Status This bit is set high when an interrupt is generated in the MMC FPE Receive Interrupt Register. This bit is cleared when all bits in this interrupt register are cleared. This bit is valid only when you select the.." "MMC FPE Receive Interrupt status not active,MMC FPE Receive Interrupt status active" newline bitfld.long 0x0 19. "MFTIS,MMC FPE Transmit Interrupt Status This bit is set high when an interrupt is generated in the MMC FPE Transmit Interrupt Register. This bit is cleared when all bits in this interrupt register are cleared. This bit is valid only when you select the.." "MMC FPE Transmit Interrupt status not active,MMC FPE Transmit Interrupt status active" newline bitfld.long 0x0 18. "MDIOIS,MDIO Interrupt Status This bit indicates an interrupt event after the completion of MDIO operation. To reset this bit the application has to read this bit/Write 1 to this bit when RCWE bit of MAC_CSR_SW_Ctrl register is set. Access restriction.." "MDIO Interrupt status not active,MDIO Interrupt status active" newline bitfld.long 0x0 17. "FPEIS,Frame Preemption Interrupt Status This bit indicates an interrupt event during the operation of Frame Preemption (Bits[19:16] of MAC_FPE_CTRL_STS register is set). To reset this bit the application must clear the event in MAC_FPE_CTRL_STS that has.." "Frame Preemption Interrupt status not active,Frame Preemption Interrupt status active" newline bitfld.long 0x0 16. "RESERVED_16,Reserved." "0,1" newline bitfld.long 0x0 15. "RESERVED_GPIIS,Reserved." "0,1" newline bitfld.long 0x0 14. "RXSTSIS,Receive Status Interrupt This bit indicates the status of received packets. This bit is set when the RWT bit is set in the MAC_Rx_Tx_Status register. This bit is cleared when the corresponding interrupt source bit is read (or corresponding.." "Receive Interrupt status not active,Receive Interrupt status active" newline bitfld.long 0x0 13. "TXSTSIS,Transmit Status Interrupt This bit indicates the status of transmitted packets. This bit is set when any of the following bits is set in the MAC_Rx_Tx_Status register: - Excessive Collision (EXCOL) - Late Collision (LCOL) - Excessive Deferral.." "Transmit Interrupt status not active,Transmit Interrupt status active" newline bitfld.long 0x0 12. "TSIS,Timestamp Interrupt Status If the Timestamp feature is enabled this bit is set when any of the following conditions is true: - The system time value is equal to or exceeds the value specified in the Target Time High and Low registers. - There is an.." "Timestamp Interrupt status not active,Timestamp Interrupt status active" newline bitfld.long 0x0 11. "MMCRXIPIS,MMC Receive Checksum Offload Interrupt Status This bit is set high when an interrupt is generated in the MMC Receive Checksum Offload Interrupt Register. This bit is cleared when all bits in this interrupt register are cleared. This bit is.." "MMC Receive Checksum Offload Interrupt status..,MMC Receive Checksum Offload Interrupt status.." newline bitfld.long 0x0 10. "MMCTXIS,MMC Transmit Interrupt Status This bit is set high when an interrupt is generated in the MMC Transmit Interrupt Register. This bit is cleared when all bits in this interrupt register are cleared. This bit is valid only when you select the Enable.." "MMC Transmit Interrupt status not active,MMC Transmit Interrupt status active" newline bitfld.long 0x0 9. "MMCRXIS,MMC Receive Interrupt Status This bit is set high when an interrupt is generated in the MMC Receive Interrupt Register. This bit is cleared when all bits in this interrupt register are cleared. This bit is valid only when you select the Enable.." "MMC Receive Interrupt status not active,MMC Receive Interrupt status active" newline bitfld.long 0x0 8. "MMCIS,MMC Interrupt Status This bit is set high when Bit 11 Bit 10 or Bit 9 is set high. This bit is cleared only when all these bits are low. This bit is valid only when you select the Enable MAC Management Counters (MMC) option. 0x1: MMC Interrupt.." "MMC Interrupt status not active,MMC Interrupt status active" newline bitfld.long 0x0 6.--7. "RESERVED_7_6,Reserved." "0,1,2,3" newline bitfld.long 0x0 5. "LPIIS,LPI Interrupt Status When the Energy Efficient Ethernet feature is enabled this bit is set for any LPI state entry or exit in the MAC Transmitter or Receiver. This bit is cleared when the corresponding interrupt source bit of.." "LPI Interrupt status not active,LPI Interrupt status active" newline bitfld.long 0x0 4. "PMTIS,PMT Interrupt Status This bit is set when a Magic packet or Wake-on-LAN packet is received in the power-down mode (RWKPRCVD and MGKPRCVD bits in MAC_PMT_Control_Status register). This bit is cleared when corresponding interrupt source bit are.." "PMT Interrupt status not active,PMT Interrupt status active" newline bitfld.long 0x0 3. "PHYIS,PHY Interrupt This bit is set when rising edge is detected on the phy_intr_i input. This bit is cleared when this register is read (or this bit is written to 1 when RCWE bit of MAC_CSR_SW_Ctrl register is set). 0x1: PHY Interrupt detected 0x0: PHY.." "PHY Interrupt not detected,PHY Interrupt detected" newline bitfld.long 0x0 2. "RESERVED_PCSANCIS,Reserved." "0,1" newline bitfld.long 0x0 1. "RESERVED_PCSLCHGIS,Reserved." "0,1" newline bitfld.long 0x0 0. "RGSMIIIS,RGMII or SMII Interrupt Status This bit is set because of any change in value of the Link Status of RGMII or SMII interface (LNKSTS bit in MAC_PHYIF_Control_Status register). This bit is cleared when the MAC_PHYIF_Control_Status register is read.." "RGMII or SMII Interrupt Status is not active,RGMII or SMII Interrupt Status is active" group.long 0xB4++0x3 line.long 0x0 "MAC_INTERRUPT_ENABLE,The Interrupt Enable register contains the masks for generating the interrupts." hexmask.long.word 0x0 19.--31. 1. "RESERVED_31_19,Reserved." newline bitfld.long 0x0 18. "MDIOIE,MDIO Interrupt Enable When this bit is set it enables the assertion of the interrupt when MDIOIS field is set in the MAC_Interrupt_Status register. 0x0: MDIO Interrupt is disabled 0x1: MDIO Interrupt is enabled" "MDIO Interrupt is disabled,MDIO Interrupt is enabled" newline bitfld.long 0x0 17. "FPEIE,Frame Preemption Interrupt Enable When this bit is set it enables the assertion of the interrupt when FPEIS field is set in the MAC_Interrupt_Status register. 0x0: Frame Preemption Interrupt is disabled 0x1: Frame Preemption Interrupt is enabled" "Frame Preemption Interrupt is disabled,Frame Preemption Interrupt is enabled" newline rbitfld.long 0x0 16. "RESERVED_16,Reserved." "0,1" newline rbitfld.long 0x0 15. "RESERVED_15,Reserved." "0,1" newline bitfld.long 0x0 14. "RXSTSIE,Receive Status Interrupt Enable When this bit is set it enables the assertion of the interrupt signal because of the setting of RXSTSIS bit in the MAC_Interrupt_Status register. 0x0: Receive Status Interrupt is disabled 0x1: Receive Status.." "Receive Status Interrupt is disabled,Receive Status Interrupt is enabled" newline bitfld.long 0x0 13. "TXSTSIE,Transmit Status Interrupt Enable When this bit is set it enables the assertion of the interrupt signal because of the setting of TXSTSIS bit in the MAC_Interrupt_Status register. 0x0: Timestamp Status Interrupt is disabled 0x1: Timestamp Status.." "Timestamp Status Interrupt is disabled,Timestamp Status Interrupt is enabled" newline bitfld.long 0x0 12. "TSIE,Timestamp Interrupt Enable When this bit is set it enables the assertion of the interrupt signal because of the setting of TSIS bit in MAC_Interrupt_Status register. 0x0: Timestamp Interrupt is disabled 0x1: Timestamp Interrupt is enabled" "Timestamp Interrupt is disabled,Timestamp Interrupt is enabled" newline hexmask.long.byte 0x0 6.--11. 1. "RESERVED_11_6,Reserved." newline bitfld.long 0x0 5. "LPIIE,LPI Interrupt Enable When this bit is set it enables the assertion of the interrupt signal because of the setting of LPIIS bit in MAC_Interrupt_Status register. 0x0: LPI Interrupt is disabled 0x1: LPI Interrupt is enabled" "LPI Interrupt is disabled,LPI Interrupt is enabled" newline bitfld.long 0x0 4. "PMTIE,PMT Interrupt Enable When this bit is set it enables the assertion of the interrupt signal because of the setting of PMTIS bit in MAC_Interrupt_Status register. 0x0: PMT Interrupt is disabled 0x1: PMT Interrupt is enabled" "PMT Interrupt is disabled,PMT Interrupt is enabled" newline bitfld.long 0x0 3. "PHYIE,PHY Interrupt Enable When this bit is set it enables the assertion of the interrupt signal because of the setting of PHYIS bit in MAC_Interrupt_Status register. 0x0: PHY Interrupt is disabled 0x1: PHY Interrupt is enabled" "PHY Interrupt is disabled,PHY Interrupt is enabled" newline rbitfld.long 0x0 2. "RESERVED_PCSANCIE,Reserved." "0,1" newline rbitfld.long 0x0 1. "RESERVED_PCSLCHGIE,Reserved." "0,1" newline bitfld.long 0x0 0. "RGSMIIIE,RGMII or SMII Interrupt Enable When this bit is set it enables the assertion of the interrupt signal because of the setting of RGSMIIIS bit in MAC_Interrupt_Status register. 0x0: RGMII or SMII Interrupt is disabled 0x1: RGMII or SMII Interrupt.." "RGMII or SMII Interrupt is disabled,RGMII or SMII Interrupt is enabled" rgroup.long 0xB8++0x3 line.long 0x0 "MAC_RX_TX_STATUS,The Receive Transmit Status register contains the Receive and Transmit Error status." hexmask.long.tbyte 0x0 9.--31. 1. "RESERVED_31_9,Reserved." newline bitfld.long 0x0 8. "RWT,Receive Watchdog Timeout This bit is set when a packet with length greater than 2 048 bytes is received (10 240 bytes when Jumbo Packet mode is enabled) and the WD bit is reset in the MAC_Configuration register. This bit is set when a packet with.." "No receive watchdog timeout,Receive watchdog timed out" newline bitfld.long 0x0 6.--7. "RESERVED_7_6,Reserved." "0,1,2,3" newline bitfld.long 0x0 5. "EXCOL,Excessive Collisions When the DTXSTS bit is set in the MTL_Operation_Mode register this bit indicates that the transmission aborted after 16 successive collisions while attempting to transmit the current packet. If the DR bit is set in the.." "No collision,Excessive collision is sensed" newline bitfld.long 0x0 4. "LCOL,Late Collision When the DTXSTS bit is set in the MTL_Operation_Mode register this bit indicates that the packet transmission aborted because a collision occurred after the collision window (64 bytes including Preamble in MII mode; 512 bytes.." "No collision,Late collision is sensed" newline bitfld.long 0x0 3. "EXDEF,Excessive Deferral When the DTXSTS bit is set in the MTL_Operation_Mode register and the DC bit is set in the MAC_Configuration register this bit indicates that the transmission ended because of excessive deferral of over 24 288 bit times (155 680.." "No Excessive deferral,Excessive deferral" newline bitfld.long 0x0 2. "LCARR,Loss of Carrier When the DTXSTS bit is set in the MTL_Operation_Mode register this bit indicates that the loss of carrier occurred during packet transmission that is the phy_crs_i signal was inactive for one or more transmission clock periods.." "Carrier is present,Loss of carrier" newline bitfld.long 0x0 1. "NCARR,No Carrier When the DTXSTS bit is set in the MTL_Operation_Mode register this bit indicates that the carrier signal from the PHY is not present at the end of preamble transmission. Access restriction applies. Clears on read (or write of 1 when.." "Carrier is present,No carrier" newline bitfld.long 0x0 0. "TJT,Transmit Jabber Timeout This bit indicates that the Transmit Jabber Timer expired which happens when the packet size exceeds 2 048 bytes (10 240 bytes when the Jumbo packet is enabled) and JD bit is reset in the MAC_Configuration register. This bit.." "No Transmit Jabber Timeout,Transmit Jabber Timeout occurred" group.long 0xC0++0x7 line.long 0x0 "MAC_PMT_CONTROL_STATUS,The PMT Control and Status Register." bitfld.long 0x0 31. "RWKFILTRST,Remote Wake-Up Packet Filter Register Pointer Reset When this bit is set the remote wake-up packet filter register pointer is reset to 3'b000. It is automatically cleared after 1 clock cycle. Access restriction applies. Setting 1 sets." "Remote Wake-Up Packet Filter Register Pointer is..,Remote Wake-Up Packet Filter Register Pointer is.." newline rbitfld.long 0x0 29.--30. "RESERVED_30_29,Reserved." "0,1,2,3" newline hexmask.long.byte 0x0 24.--28. 1. "RWKPTR,Remote Wake-up FIFO Pointer This field gives the current value (0 to 7 15 or 31 when 4 8 or 16 Remote Wake-up Packet Filters are selected) of the Remote Wake-up Packet Filter register pointer. When the value of this pointer is equal to maximum.." newline hexmask.long.word 0x0 11.--23. 1. "RESERVED_23_11,Reserved." newline bitfld.long 0x0 10. "RWKPFE,Remote Wake-up Packet Forwarding Enable When this bit is set along with RWKPKTEN the MAC receiver drops all received frames until it receives the expected Wake-up frame. All frames after that event including the received wake-up frame are.." "Remote Wake-up Packet Forwarding is disabled,Remote Wake-up Packet Forwarding is enabled" newline bitfld.long 0x0 9. "GLBLUCAST,Global Unicast When this bit set any unicast packet filtered by the MAC (DAF) address recognition is detected as a remote wake-up packet. 0x0: Global unicast is disabled 0x1: Global unicast is enabled" "Global unicast is disabled,Global unicast is enabled" newline rbitfld.long 0x0 7.--8. "RESERVED_8_7,Reserved." "0,1,2,3" newline rbitfld.long 0x0 6. "RWKPRCVD,Remote Wake-Up Packet Received When this bit is set it indicates that the power management event is generated because of the reception of a remote wake-up packet. This bit is cleared when this register is read. Access restriction applies." "Remote wake-up packet is received,Remote wake-up packet is received" newline rbitfld.long 0x0 5. "MGKPRCVD,Magic Packet Received When this bit is set it indicates that the power management event is generated because of the reception of a magic packet. This bit is cleared when this register is read. Access restriction applies. Clears on read (or.." "No Magic packet is received,Magic packet is received" newline rbitfld.long 0x0 3.--4. "RESERVED_4_3,Reserved." "0,1,2,3" newline bitfld.long 0x0 2. "RWKPKTEN,Remote Wake-Up Packet Enable When this bit is set a power management event is generated when the MAC receives a remote wake-up packet. 0x0: Remote wake-up packet is disabled 0x1: Remote wake-up packet is enabled" "Remote wake-up packet is disabled,Remote wake-up packet is enabled" newline bitfld.long 0x0 1. "MGKPKTEN,Magic Packet Enable When this bit is set a power management event is generated when the MAC receives a magic packet. 0x0: Magic Packet is disabled 0x1: Magic Packet is enabled" "Magic Packet is disabled,Magic Packet is enabled" newline bitfld.long 0x0 0. "PWRDWN,Power Down When this bit is set the MAC receiver drops all received packets until it receives the expected magic packet or remote wake-up packet. This bit is then self-cleared and the power-down mode is disabled. The software can clear this bit.." "Power down is disabled,Power down is enabled" line.long 0x4 "MAC_RWK_PACKET_FILTER,The Remote Wakeup Filter registers are implemented as 8. 16. or 32 indirect access registers (wkuppktfilter_reg#i) based on whether 4. 8. or 16 Remote Wakeup Filters are selected in the configuration and accessed by application.." hexmask.long 0x4 0.--31. 1. "WKUPFRMFTR,RWK Packet Filter This field contains the various controls of RWK Packet filter." group.long 0xD0++0xF line.long 0x0 "MAC_LPI_CONTROL_STATUS,The LPI Control and Status Register controls the LPI functions and provides the LPI interrupt status. The status bits are cleared when this register is read." hexmask.long.word 0x0 22.--31. 1. "RESERVED_31_22,Reserved." newline bitfld.long 0x0 21. "LPITCSE,LPI Tx Clock Stop Enable When this bit is set the MAC asserts sbd_tx_clk_gating_ctrl_o signal high after it enters Tx LPI mode to indicate that the Tx clock to MAC can be stopped. When this bit is reset the MAC does not assert.." "LPI Tx Clock Stop is disabled,LPI Tx Clock Stop is enabled" newline bitfld.long 0x0 20. "LPIATE,LPI Timer Enable This bit controls the automatic entry of the MAC Transmitter into and exit out of the LPI state. When LPIATE LPITXA and LPIEN bits are set the MAC Transmitter enters LPI state only when the complete MAC TX data path is IDLE for.." "LPI Timer is disabled,LPI Timer is enabled" newline bitfld.long 0x0 19. "LPITXA,LPI Tx Automate This bit controls the behavior of the MAC when it is entering or coming out of the LPI mode on the Transmit side. This bit is not functional in the EQOS-CORE configurations in which the Tx clock gating is done during the LPI mode." "LPI Tx Automate is disabled,LPI Tx Automate is enabled" newline bitfld.long 0x0 18. "PLSEN,PHY Link Status Enable This bit enables the link status received on the RGMII Receive paths to be used for activating the LPI LS TIMER. When this bit is set the MAC uses the link-status bits of the MAC_PHYIF_Control_Status register and the PLS bit.." "PHY Link Status is disabled,PHY Link Status is enabled" newline bitfld.long 0x0 17. "PLS,PHY Link Status This bit indicates the link status of the PHY. The MAC Transmitter asserts the LPI pattern only when the link status is up (OKAY) at least for the time indicated by the LPI LS TIMER. When this bit is set the link is considered to be.." "link is down,link is okay" newline bitfld.long 0x0 16. "LPIEN,LPI Enable When this bit is set it instructs the MAC Transmitter to enter the LPI state. When this bit is reset it instructs the MAC to exit the LPI state and resume normal transmission. This bit is cleared when the LPITXA bit is set and the MAC.." "LPI state is disabled,LPI state is enabled" newline hexmask.long.byte 0x0 10.--15. 1. "RESERVED_15_10,Reserved." newline rbitfld.long 0x0 9. "RLPIST,Receive LPI State When this bit is set it indicates that the MAC is receiving the LPI pattern on the GMII or MII interface. 0x1: Receive LPI state detected 0x0: Receive LPI state not detected" "Receive LPI state not detected,Receive LPI state detected" newline rbitfld.long 0x0 8. "TLPIST,Transmit LPI State When this bit is set it indicates that the MAC is transmitting the LPI pattern on the GMII or MII interface. 0x1: Transmit LPI state detected 0x0: Transmit LPI state not detected" "Transmit LPI state not detected,Transmit LPI state detected" newline hexmask.long.byte 0x0 4.--7. 1. "RESERVED_7_4,Reserved." newline rbitfld.long 0x0 3. "RLPIEX,Receive LPI Exit When this bit is set it indicates that the MAC Receiver has stopped receiving the LPI pattern on the GMII or MII interface exited the LPI state and resumed the normal reception. This bit is cleared by a read into this register.." "Receive LPI exit not detected,Receive LPI exit detected" newline rbitfld.long 0x0 2. "RLPIEN,Receive LPI Entry When this bit is set it indicates that the MAC Receiver has received an LPI pattern and entered the LPI state. This bit is cleared by a read into this register (or this bit is written to 1 when RCWE bit in MAC_CSR_SW_Ctrl.." "Receive LPI entry not detected,Receive LPI entry detected" newline rbitfld.long 0x0 1. "TLPIEX,Transmit LPI Exit When this bit is set it indicates that the MAC transmitter exited the LPI state after the application cleared the LPIEN bit and the LPI TW Timer has expired. This bit is cleared by a read into this register (or this bit is.." "Transmit LPI exit not detected,Transmit LPI exit detected" newline rbitfld.long 0x0 0. "TLPIEN,Transmit LPI Entry When this bit is set it indicates that the MAC Transmitter has entered the LPI state because of the setting of the LPIEN bit. This bit is cleared by a read into this register (or this bit is written to 1 when RCWE bit in.." "Transmit LPI entry not detected,Transmit LPI entry detected" line.long 0x4 "MAC_LPI_TIMERS_CONTROL,The LPI Timers Control register controls the timeout values in the LPI states. It specifies the time for which the MAC transmits the LPI pattern and also the time for which the MAC waits before resuming the normal transmission." hexmask.long.byte 0x4 26.--31. 1. "RESERVED_31_26,Reserved." newline hexmask.long.word 0x4 16.--25. 1. "LST,LPI LS Timer This field specifies the minimum time (in milliseconds) for which the link status from the PHY should be up (OKAY) before the LPI pattern can be transmitted to the PHY. The MAC does not transmit the LPI pattern even when the LPIEN bit is.." newline hexmask.long.word 0x4 0.--15. 1. "TWT,LPI TW Timer This field specifies the minimum time (in microseconds) for which the MAC waits after it stops transmitting the LPI pattern to the PHY and before it resumes the normal transmission. The TLPIEX status bit is set after the expiry of this.." line.long 0x8 "MAC_LPI_ENTRY_TIMER,This register controls the Tx LPI entry timer. This counter is enabled only when bit[20](LPITE) bit of MAC_LPI_Control_Status is set to 1." hexmask.long.word 0x8 20.--31. 1. "RESERVED_31_20,Reserved." newline hexmask.long.tbyte 0x8 3.--19. 1. "LPIET,LPI Entry Timer This field specifies the time in microseconds the MAC waits to enter LPI mode after it has transmitted all the frames. This field is valid and used only when LPITE and LPITXA are set to 1. Bits [2:0] are read-only so that the.." newline rbitfld.long 0x8 0.--2. "RESERVED_2_0,Reserved." "0,1,2,3,4,5,6,7" line.long 0xC "MAC_1US_TIC_COUNTER,This register controls the generation of the Reference time (1 microsecond tic) for all the LPI timers. This timer has to be programmed by the software initially." hexmask.long.tbyte 0xC 12.--31. 1. "RESERVED_31_12,Reserved." newline hexmask.long.word 0xC 0.--11. 1. "TIC_1US_CNTR,1US TIC Counter The application must program this counter so that the number of clock cycles of CSR clock is 1us. (Subtract 1 from the value before programming). For example if the CSR clock is 100MHz then this field needs to be programmed.." group.long 0xF8++0x3 line.long 0x0 "MAC_PHYIF_CONTROL_STATUS,The PHY Interface Control and Status register indicates the status signals received by the SGMII. RGMII. or SMII interface (selected at reset) from the PHY. This register is optional." hexmask.long.word 0x0 22.--31. 1. "RESERVED_31_22,Reserved." newline rbitfld.long 0x0 21. "RESERVED_FALSCARDET,Reserved." "0,1" newline rbitfld.long 0x0 20. "RESERVED_JABTO,Reserved." "0,1" newline rbitfld.long 0x0 19. "LNKSTS,Link Status This bit indicates whether the link is up (1'b1) or down (1'b0). 0x1: Link up 0x0: Link down" "Link down,Link up" newline rbitfld.long 0x0 17.--18. "LNKSPEED,Link Speed This bit indicates the current speed of the link. 0x2: 125 MHz 0x0: 2.5 MHz 0x1: 25 MHz 0x3: Reserved" "?,?,?,Reserved" newline rbitfld.long 0x0 16. "LNKMOD,Link Mode This bit indicates the current mode of operation of the link. 0x1: Full-duplex mode 0x0: Half-duplex mode" "Half-duplex mode,Full-duplex mode" newline hexmask.long.word 0x0 5.--15. 1. "RESERVED_15_5,Reserved." newline rbitfld.long 0x0 4. "RESERVED_SMIDRXS,Reserved." "0,1" newline rbitfld.long 0x0 3. "RESERVED_3,Reserved." "0,1" newline rbitfld.long 0x0 2. "RESERVED_SFTERR,Reserved." "0,1" newline bitfld.long 0x0 1. "LUD,Link Up or Down This bit indicates whether the link is up or down during transmission of configuration in the RGMII interface. 0x0: Link down 0x1: Link up" "Link down,Link up" newline bitfld.long 0x0 0. "TC,Transmit Configuration in RGMII. When set this bit enables the transmission of duplex mode link speed and link up or down information to the PHY in the RGMII port. When this bit is reset no such information is driven to the PHY. The details of.." "Disable Transmit Configuration in RGMII,Enable Transmit Configuration in RGMII" rgroup.long 0x110++0x7 line.long 0x0 "MAC_VERSION,The version register identifies the version of the DWC_ether_qos. This register contains two bytes: one that Synopsys uses to identify the core release number. and the other that you set while configuring the core." hexmask.long.word 0x0 16.--31. 1. "RESERVED_31_16,Reserved." newline hexmask.long.byte 0x0 8.--15. 1. "USERVER,User-defined Version (configured with coreConsultant)" newline hexmask.long.byte 0x0 0.--7. 1. "SNPSVER,Synopsys-defined Version" line.long 0x4 "MAC_DEBUG,The Debug register provides the debug status of various MAC blocks." hexmask.long.word 0x4 19.--31. 1. "RESERVED_31_19,Reserved." newline bitfld.long 0x4 17.--18. "TFCSTS,MAC Transmit Packet Controller Status This field indicates the state of the MAC Transmit Packet Controller module. 0x2: Generating and transmitting a Pause control packet (in full-duplex mode) 0x0: Idle state 0x3: Transferring input packet for.." "Idle state,Waiting for one of the following: Status of the..,Generating and transmitting a Pause control..,Transferring input packet for transmission" newline bitfld.long 0x4 16. "TPESTS,MAC GMII or MII Transmit Protocol Engine Status When this bit is set it indicates that the MAC GMII or MII transmit protocol engine is actively transmitting data and it is not in the Idle state. 0x1: MAC GMII or MII Transmit Protocol Engine.." "MAC GMII or MII Transmit Protocol Engine Status..,MAC GMII or MII Transmit Protocol Engine Status.." newline hexmask.long.word 0x4 3.--15. 1. "RESERVED_15_3,Reserved." newline bitfld.long 0x4 1.--2. "RFCFCSTS,MAC Receive Packet Controller FIFO Status When this bit is set this field indicates the active state of the small FIFO Read and Write controllers of the MAC Receive Packet Controller module." "0,1,2,3" newline bitfld.long 0x4 0. "RPESTS,MAC GMII or MII Receive Protocol Engine Status When this bit is set it indicates that the MAC GMII or MII receive protocol engine is actively receiving data and it is not in the Idle state. 0x1: MAC GMII or MII Receive Protocol Engine Status.." "MAC GMII or MII Receive Protocol Engine Status..,MAC GMII or MII Receive Protocol Engine Status.." rgroup.long 0x11C++0xF line.long 0x0 "MAC_HW_FEATURE0,This register indicates the presence of first set of the optional features or functions of the DWC_ether_qos. The software driver can use this register to dynamically enable or disable the programs related to the optional blocks. Note:.." bitfld.long 0x0 31. "RESERVED_31,Reserved." "0,1" newline bitfld.long 0x0 28.--30. "ACTPHYSEL,Active PHY Selected When you have multiple PHY interfaces in your configuration this field indicates the sampled value of phy_intf_sel_i during reset de-assertion. 0x0: Reserved 0x7: Reserved 0x1: RGMII 0x4: RMII 0x5: Reserved 0x2: Reserved.." "Reserved,RGMII,Reserved,Reserved,RMII,Reserved,Reserved,Reserved" newline bitfld.long 0x0 27. "SAVLANINS,Source Address or VLAN Insertion Enable This bit is set to 1 when the Enable SA and VLAN Insertion on Tx option is selected 0x1: Source Address or VLAN Insertion Enable option is selected 0x0: Source Address or VLAN Insertion Enable option is.." "Source Address or VLAN Insertion Enable option..,Source Address or VLAN Insertion Enable option.." newline bitfld.long 0x0 25.--26. "TSSTSSEL,Timestamp System Time Source This bit indicates the source of the Timestamp system time: This bit is set to 1 when the Enable IEEE 1588 Timestamp Support option is selected 0x2: Both 0x1: External 0x0: Internal 0x3: Reserved" "Internal,External,Both,Reserved" newline bitfld.long 0x0 24. "MACADR64SEL,MAC Addresses 64-127 Selected This bit is set to 1 when the Enable Additional 64 MAC Address Registers (64-127) option is selected 0x1: MAC Addresses 64-127 Select option is selected 0x0: MAC Addresses 64-127 Select option is not selected" "MAC Addresses 64-127 Select option is not selected,MAC Addresses 64-127 Select option is selected" newline bitfld.long 0x0 23. "MACADR32SEL,MAC Addresses 32-63 Selected This bit is set to 1 when the Enable Additional 32 MAC Address Registers (32-63) option is selected 0x1: MAC Addresses 32-63 Select option is selected 0x0: MAC Addresses 32-63 Select option is not selected" "MAC Addresses 32-63 Select option is not selected,MAC Addresses 32-63 Select option is selected" newline hexmask.long.byte 0x0 18.--22. 1. "ADDMACADRSEL,MAC Addresses 1-31 Selected This bit is set to 1 when the non-zero value is selected for Enable Additional 1-31 MAC Address Registers option" newline bitfld.long 0x0 17. "RESERVED_17,Reserved." "0,1" newline bitfld.long 0x0 16. "RXCOESEL,Receive Checksum Offload Enabled This bit is set to 1 when the Enable Receive TCP/IP Checksum Check option is selected 0x1: Receive Checksum Offload Enable option is selected 0x0: Receive Checksum Offload Enable option is not selected" "Receive Checksum Offload Enable option is not..,Receive Checksum Offload Enable option is selected" newline bitfld.long 0x0 15. "RESERVED_15,Reserved." "0,1" newline bitfld.long 0x0 14. "TXCOESEL,Transmit Checksum Offload Enabled This bit is set to 1 when the Enable Transmit TCP/IP Checksum Insertion option is selected 0x1: Transmit Checksum Offload Enable option is selected 0x0: Transmit Checksum Offload Enable option is not selected" "Transmit Checksum Offload Enable option is not..,Transmit Checksum Offload Enable option is.." newline bitfld.long 0x0 13. "EEESEL,Energy Efficient Ethernet Enabled This bit is set to 1 when the Enable Energy Efficient Ethernet (EEE) option is selected 0x1: Energy Efficient Ethernet Enable option is selected 0x0: Energy Efficient Ethernet Enable option is not selected" "Energy Efficient Ethernet Enable option is not..,Energy Efficient Ethernet Enable option is.." newline bitfld.long 0x0 12. "TSSEL,IEEE 1588-2008 Timestamp Enabled This bit is set to 1 when the Enable IEEE 1588 Timestamp Support option is selected 0x1: IEEE 1588-2008 Timestamp Enable option is selected 0x0: IEEE 1588-2008 Timestamp Enable option is not selected" "IEEE 1588-2008 Timestamp Enable option is not..,IEEE 1588-2008 Timestamp Enable option is selected" newline bitfld.long 0x0 10.--11. "RESERVED_11_10,Reserved." "0,1,2,3" newline bitfld.long 0x0 9. "ARPOFFSEL,ARP Offload Enabled This bit is set to 1 when the Enable IPv4 ARP Offload option is selected 0x1: ARP Offload Enable option is selected 0x0: ARP Offload Enable option is not selected" "ARP Offload Enable option is not selected,ARP Offload Enable option is selected" newline bitfld.long 0x0 8. "MMCSEL,RMON Module Enable This bit is set to 1 when the Enable MAC Management Counters (MMC) option is selected 0x1: RMON Module Enable option is selected 0x0: RMON Module Enable option is not selected" "RMON Module Enable option is not selected,RMON Module Enable option is selected" newline bitfld.long 0x0 7. "MGKSEL,PMT Magic Packet Enable This bit is set to 1 when the Enable Magic Packet Detection option is selected 0x1: PMT Magic Packet Enable option is selected 0x0: PMT Magic Packet Enable option is not selected" "PMT Magic Packet Enable option is not selected,PMT Magic Packet Enable option is selected" newline bitfld.long 0x0 6. "RWKSEL,PMT Remote Wake-up Packet Enable This bit is set to 1 when the Enable Remote Wake-Up Packet Detection option is selected 0x1: PMT Remote Wake-up Packet Enable option is selected 0x0: PMT Remote Wake-up Packet Enable option is not selected" "PMT Remote Wake-up Packet Enable option is not..,PMT Remote Wake-up Packet Enable option is.." newline bitfld.long 0x0 5. "SMASEL,SMA (MDIO) Interface This bit is set to 1 when the Enable Station Management (MDIO Interface) option is selected 0x1: SMA (MDIO) Interface selected 0x0: SMA (MDIO) Interface not selected" "SMA,SMA" newline bitfld.long 0x0 4. "VLHASH,VLAN Hash Filter Selected This bit is set to 1 when the Enable VLAN Hash Table Based Filtering option is selected 0x1: VLAN Hash Filter selected 0x0: VLAN Hash Filter not selected" "VLAN Hash Filter not selected,VLAN Hash Filter selected" newline bitfld.long 0x0 3. "PCSSEL,Reserved" "0,1" newline bitfld.long 0x0 2. "HDSEL,Half-duplex Support This bit is set to 1 when the half-duplex mode is selected 0x1: Half-duplex support 0x0: No Half-duplex support" "No Half-duplex support,Half-duplex support" newline bitfld.long 0x0 1. "GMIISEL,1000 Mbps Support This bit is set to 1 when 1000 Mbps is selected as the Mode of Operation 0x1: 1000 Mbps support 0x0: No 1000 Mbps support" "No 1000 Mbps support,?" newline bitfld.long 0x0 0. "MIISEL,10 or 100 Mbps Support This bit is set to 1 when 10/100 Mbps is selected as the Mode of Operation 0x1: 10 or 100 Mbps support 0x0: No 10 or 100 Mbps support" "No 10 or 100 Mbps support,?" line.long 0x4 "MAC_HW_FEATURE1,This register indicates the presence of second set of the optional features or functions of the DWC_ether_qos. The software driver can use this register to dynamically enable or disable the programs related to the optional blocks. Note:.." bitfld.long 0x4 31. "RESERVED_31,Reserved." "0,1" newline hexmask.long.byte 0x4 27.--30. 1. "L3L4FNUM,Total number of L3 or L4 Filters This field indicates the total number of L3 or L4 filters: 0x1: 1 L3 or L4 Filter 0x2: 2 L3 or L4 Filters 0x3: 3 L3 or L4 Filters 0x4: 4 L3 or L4 Filters 0x5: 5 L3 or L4 Filters 0x6: 6 L3 or L4 Filters 0x7: 7 L3.." newline bitfld.long 0x4 26. "RESERVED_26,Reserved." "0,1" newline bitfld.long 0x4 24.--25. "HASHTBLSZ,Hash Table Size This field indicates the size of the hash table: 0x2: 128 0x3: 256 0x1: 64 0x0: No hash table" "No hash table,?,?,?" newline bitfld.long 0x4 23. "POUOST,One Step for PTP over UDP/IP Feature Enable This bit is set to 1 when the Enable One step timestamp for PTP over UDP/IP feature is selected. 0x1: One Step for PTP over UDP/IP Feature is selected 0x0: One Step for PTP over UDP/IP Feature is not.." "One Step for PTP over UDP/IP Feature is not..,One Step for PTP over UDP/IP Feature is selected" newline bitfld.long 0x4 22. "RESERVED_22,Reserved." "0,1" newline bitfld.long 0x4 21. "RAVSEL,Rx Side Only AV Feature Enable This bit is set to 1 when the Enable Audio Video Bridging option on Rx Side Only is selected. 0x1: Rx Side Only AV Feature is selected 0x0: Rx Side Only AV Feature is not selected" "Rx Side Only AV Feature is not selected,Rx Side Only AV Feature is selected" newline bitfld.long 0x4 20. "AVSEL,AV Feature Enable This bit is set to 1 when the Enable Audio Video Bridging option is selected. 0x1: AV Feature is selected 0x0: AV Feature is not selected" "AV Feature is not selected,AV Feature is selected" newline bitfld.long 0x4 19. "DBGMEMA,DMA Debug Registers Enable This bit is set to 1 when the Debug Mode Enable option is selected 0x1: DMA Debug Registers option is selected 0x0: DMA Debug Registers option is not selected" "DMA Debug Registers option is not selected,DMA Debug Registers option is selected" newline bitfld.long 0x4 18. "TSOEN,TCP Segmentation Offload Enable This bit is set to 1 when the Enable TCP Segmentation Offloading for TCP/IP Packets option is selected 0x1: TCP Segmentation Offload Feature is selected 0x0: TCP Segmentation Offload Feature is not selected" "TCP Segmentation Offload Feature is not selected,TCP Segmentation Offload Feature is selected" newline bitfld.long 0x4 17. "SPHEN,Split Header Feature Enable This bit is set to 1 when the Enable Split Header Structure option is selected 0x1: Split Header Feature is selected 0x0: Split Header Feature is not selected" "Split Header Feature is not selected,Split Header Feature is selected" newline bitfld.long 0x4 16. "DCBEN,DCB Feature Enable This bit is set to 1 when the Enable Data Center Bridging option is selected 0x1: DCB Feature is selected 0x0: DCB Feature is not selected" "DCB Feature is not selected,DCB Feature is selected" newline bitfld.long 0x4 14.--15. "ADDR64,Address Width. This field indicates the configured address width: 0x0: 32 0x1: 40 0x2: 48 0x3: Reserved" "?,?,?,Reserved" newline bitfld.long 0x4 13. "ADVTHWORD,IEEE 1588 High Word Register Enable This bit is set to 1 when the Add IEEE 1588 Higher Word Register option is selected 0x1: IEEE 1588 High Word Register option is selected 0x0: IEEE 1588 High Word Register option is not selected" "IEEE 1588 High Word Register option is not..,IEEE 1588 High Word Register option is selected" newline bitfld.long 0x4 12. "PTOEN,PTP Offload Enable This bit is set to 1 when the Enable PTP Timestamp Offload Feature is selected. 0x1: PTP Offload feature is selected 0x0: PTP Offload feature is not selected" "PTP Offload feature is not selected,PTP Offload feature is selected" newline bitfld.long 0x4 11. "OSTEN,One-Step Timestamping Enable This bit is set to 1 when the Enable One-Step Timestamp Feature is selected. 0x1: One-Step Timestamping feature is selected 0x0: One-Step Timestamping feature is not selected" "One-Step Timestamping feature is not selected,One-Step Timestamping feature is selected" newline hexmask.long.byte 0x4 6.--10. 1. "TXFIFOSIZE,MTL Transmit FIFO Size This field contains the configured value of MTL Tx FIFO in bytes expressed as Log to base 2 minus 7 that is Log2(TXFIFO_SIZE) -7: 0x3: 1024 bytes 0x0: 128 bytes 0xa: 128 KB 0x7: 16384 bytes 0x4: 2048 bytes 0x1: 256.." newline bitfld.long 0x4 5. "SPRAM,Single Port RAM Enable This bit is set to 1 when the Use single port RAM Feature is selected. 0x1: Single Port RAM feature is selected 0x0: Single Port RAM feature is not selected" "Single Port RAM feature is not selected,Single Port RAM feature is selected" newline hexmask.long.byte 0x4 0.--4. 1. "RXFIFOSIZE,MTL Receive FIFO Size This field contains the configured value of MTL Rx FIFO in bytes expressed as Log to base 2 minus 7 that is Log2(RXFIFO_SIZE) -7: 0x3: 1024 bytes 0x0: 128 bytes 0xa: 128 KB 0x7: 16384 bytes 0x4: 2048 bytes 0x1: 256.." line.long 0x8 "MAC_HW_FEATURE2,This register indicates the presence of third set of the optional features or functions of the DWC_ether_qos. The software driver can use this register to dynamically enable or disable the programs related to the optional blocks." bitfld.long 0x8 31. "RESERVED_31,Reserved." "0,1" newline bitfld.long 0x8 28.--30. "AUXSNAPNUM,Number of Auxiliary Snapshot Inputs This field indicates the number of auxiliary snapshot inputs: 0x1: 1 auxiliary input 0x2: 2 auxiliary input 0x3: 3 auxiliary input 0x4: 4 auxiliary input 0x0: No auxiliary input 0x5: Reserved" "No auxiliary input,?,?,?,?,Reserved,?,?" newline bitfld.long 0x8 27. "RESERVED_27,Reserved." "0,1" newline bitfld.long 0x8 24.--26. "PPSOUTNUM,Number of PPS Outputs This field indicates the number of PPS outputs: 0x1: 1 PPS output 0x2: 2 PPS output 0x3: 3 PPS output 0x4: 4 PPS output 0x0: No PPS output 0x5: Reserved" "No PPS output,?,?,?,?,Reserved,?,?" newline bitfld.long 0x8 22.--23. "RESERVED_23_22,Reserved." "0,1,2,3" newline hexmask.long.byte 0x8 18.--21. 1. "TXCHCNT,Number of DMA Transmit Channels This field indicates the number of DMA Transmit channels: 0x0: 1 MTL Tx Channel 0x1: 2 MTL Tx Channels 0x2: 3 MTL Tx Channels 0x3: 4 MTL Tx Channels 0x4: 5 MTL Tx Channels 0x5: 6 MTL Tx Channels 0x6: 7 MTL Tx.." newline bitfld.long 0x8 16.--17. "RESERVED_17_16,Reserved." "0,1,2,3" newline hexmask.long.byte 0x8 12.--15. 1. "RXCHCNT,Number of DMA Receive Channels This field indicates the number of DMA Receive channels: 0x0: 1 MTL Rx Channel 0x1: 2 MTL Rx Channels 0x2: 3 MTL Rx Channels 0x3: 4 MTL Rx Channels 0x4: 5 MTL Rx Channels 0x5: 6 MTL Rx Channels 0x6: 7 MTL Rx.." newline bitfld.long 0x8 10.--11. "RESERVED_11_10,Reserved." "0,1,2,3" newline hexmask.long.byte 0x8 6.--9. 1. "TXQCNT,Number of MTL Transmit Queues This field indicates the number of MTL Transmit queues: 0x0: 1 MTL Tx Queue 0x1: 2 MTL Tx Queues 0x2: 3 MTL Tx Queues 0x3: 4 MTL Tx Queues 0x4: 5 MTL Tx Queues 0x5: 6 MTL Tx Queues 0x6: 7 MTL Tx Queues 0x7: 8 MTL Tx.." newline bitfld.long 0x8 4.--5. "RESERVED_5_4,Reserved." "0,1,2,3" newline hexmask.long.byte 0x8 0.--3. 1. "RXQCNT,Number of MTL Receive Queues This field indicates the number of MTL Receive queues: 0x0: 1 MTL Rx Queue 0x1: 2 MTL Rx Queues 0x2: 3 MTL Rx Queues 0x3: 4 MTL Rx Queues 0x4: 5 MTL Rx Queues 0x5: 6 MTL Rx Queues 0x6: 7 MTL Rx Queues 0x7: 8 MTL Rx.." line.long 0xC "MAC_HW_FEATURE3,This register indicates the presence of fourth set the optional features or functions of the DWC_ether_qos. The software driver can use this register to dynamically enable or disable the programs related to the optional blocks." bitfld.long 0xC 30.--31. "RESERVED_31_30,Reserved." "0,1,2,3" newline bitfld.long 0xC 28.--29. "ASP,Automotive Safety Package Following are the encoding for the different Safety features 0x2: All the Automotive Safety features are selected without the 'Parity Port Enable for external interface' feature 0x3: All the Automotive Safety features are.." "No Safety features selected,Only 'ECC protection for external memory'..,All the Automotive Safety features are selected..,All the Automotive Safety features are selected.." newline bitfld.long 0xC 27. "TBSSEL,Time Based Scheduling Enable This bit is set to 1 when the Time Based Scheduling feature is selected. 0x1: Time Based Scheduling Enable feature is selected 0x0: Time Based Scheduling Enable feature is not selected" "Time Based Scheduling Enable feature is not..,Time Based Scheduling Enable feature is selected" newline bitfld.long 0xC 26. "FPESEL,Frame Preemption Enable This bit is set to 1 when the Enable Frame preemption feature is selected. 0x1: Frame Preemption Enable feature is selected 0x0: Frame Preemption Enable feature is not selected" "Frame Preemption Enable feature is not selected,Frame Preemption Enable feature is selected" newline hexmask.long.byte 0xC 22.--25. 1. "RESERVED_25_22,Reserved." newline bitfld.long 0xC 20.--21. "ESTWID,Width of the Time Interval field in the Gate Control List This field indicates the width of the Configured Time Interval Field 0x0: Width not configured 0x1: 16 0x2: 20 0x3: 24" "Width not configured,?,?,?" newline bitfld.long 0xC 17.--19. "ESTDEP,Depth of the Gate Control List This field indicates the depth of Gate Control list expressed as Log2(DWC_EQOS_EST_DEP)-5 0x5: 1024 0x2: 128 0x3: 256 0x4: 512 0x1: 64 0x0: No Depth configured 0x6: Reserved" "No Depth configured,?,?,?,?,?,Reserved,?" newline bitfld.long 0xC 16. "ESTSEL,Enhancements to Scheduling Traffic Enable This bit is set to 1 when the Enable Enhancements to Scheduling Traffic feature is selected. 0x1: Enable Enhancements to Scheduling Traffic feature is selected 0x0: Enable Enhancements to Scheduling.." "Enable Enhancements to Scheduling Traffic..,Enable Enhancements to Scheduling Traffic.." newline bitfld.long 0xC 15. "RESERVED_15,Reserved." "0,1" newline bitfld.long 0xC 13.--14. "FRPES,Flexible Receive Parser Table Entries size This field indicates the Max Number of Parser Entries supported by Flexible Receive Parser. 0x1: 128 Entries 0x2: 256 Entries 0x0: 64 Entries 0x3: Reserved" "?,?,?,Reserved" newline bitfld.long 0xC 11.--12. "FRPBS,Flexible Receive Parser Buffer size This field indicates the supported Max Number of bytes of the packet data to be Parsed by Flexible Receive Parser. 0x1: 128 Bytes 0x2: 256 Bytes 0x0: 64 Bytes 0x3: Reserved" "?,?,?,Reserved" newline bitfld.long 0xC 10. "FRPSEL,Flexible Receive Parser Selected This bit is set to 1 when the Enable Flexible Programmable Receive Parser option is selected. 0x1: Flexible Receive Parser feature is selected 0x0: Flexible Receive Parser feature is not selected" "Flexible Receive Parser feature is not selected,Flexible Receive Parser feature is selected" newline bitfld.long 0xC 9. "PDUPSEL,Broadcast/Multicast Packet Duplication This bit is set to 1 when the Broadcast/Multicast Packet Duplication feature is selected. 0x1: Broadcast/Multicast Packet Duplication feature is selected 0x0: Broadcast/Multicast Packet Duplication feature.." "Broadcast/Multicast Packet Duplication feature..,Broadcast/Multicast Packet Duplication feature.." newline bitfld.long 0xC 6.--8. "RESERVED_7_6,Reserved." "0,1,2,3,4,5,6,7" newline bitfld.long 0xC 5. "DVLAN,Double VLAN Tag Processing Selected This bit is set to 1 when the Enable Double VLAN Processing Feature is selected. 0x1: Double VLAN option is selected 0x0: Double VLAN option is not selected" "Double VLAN option is not selected,Double VLAN option is selected" newline bitfld.long 0xC 4. "CBTISEL,Queue/Channel based VLAN tag insertion on Tx Enable This bit is set to 1 when the Enable Queue/Channel based VLAN tag insertion on Tx Feature is selected. 0x1: Enable Queue/Channel based VLAN tag insertion on Tx feature is selected 0x0: Enable.." "Enable Queue/Channel based VLAN tag insertion on..,Enable Queue/Channel based VLAN tag insertion on.." newline bitfld.long 0xC 3. "RESERVED_3,Reserved." "0,1" newline bitfld.long 0xC 0.--2. "NRVF,Number of Extended VLAN Tag Filters Enabled This field indicates the Number of Extended VLAN Tag Filters selected: 0x3: 16 Extended Rx VLAN Filters 0x4: 24 Extended Rx VLAN Filters 0x5: 32 Extended Rx VLAN Filters 0x1: 4 Extended Rx VLAN Filters.." "No Extended Rx VLAN Filters,?,?,?,?,?,Reserved,?" group.long 0x140++0x3 line.long 0x0 "MAC_DPP_FSM_INTERRUPT_STATUS,This register contains the status of Automotive Safety related Data Path Parity Errors. Interface Timeout Errors. FSM State Parity Errors and FSM State Timeout Errors." hexmask.long.byte 0x0 25.--31. 1. "RESERVED_31_25,Reserved." newline bitfld.long 0x0 24. "FSMPES,FSM State Parity Error Status This field when set indicates one of the FSMs State registers has a parity error detected. 0x1: FSM State Parity Error Status detected 0x0: FSM State Parity Error Status not detected" "FSM State Parity Error Status not detected,FSM State Parity Error Status detected" newline hexmask.long.byte 0x0 18.--23. 1. "RESERVED_23_18,Reserved." newline rbitfld.long 0x0 17. "RESERVED_SLVTES,Reserved." "0,1" newline bitfld.long 0x0 16. "MSTTES,Master Read/Write Timeout Error Status This field when set indicates that an Application/CSR Timeout has occurred on the master (AXI/AHB/ARI/ATI) interface. 0x1: Master Read/Write Timeout Error Status detected 0x0: Master Read/Write Timeout Error.." "Master Read/Write Timeout Error Status not..,Master Read/Write Timeout Error Status detected" newline rbitfld.long 0x0 15. "RESERVED_RVCTES,Reserved." "0,1" newline rbitfld.long 0x0 14. "RESERVED_R125ES,Reserved." "0,1" newline rbitfld.long 0x0 13. "RESERVED_T125ES,Reserved." "0,1" newline bitfld.long 0x0 12. "PTES,PTP FSM Timeout Error Status This field when set indicates that one of the PTP FSM Timeout has occurred. 0x1: PTP FSM Timeout Error Status detected 0x0: PTP FSM Timeout Error Status not detected" "PTP FSM Timeout Error Status not detected,PTP FSM Timeout Error Status detected" newline bitfld.long 0x0 11. "ATES,APP FSM Timeout Error Status This field when set indicates that one of the APP FSM Timeout has occurred. 0x1: APP FSM Timeout Error Status detected 0x0: APP FSM Timeout Error Status not detected" "APP FSM Timeout Error Status not detected,APP FSM Timeout Error Status detected" newline bitfld.long 0x0 10. "CTES,CSR FSM Timeout Error Status This field when set indicates that one of the CSR FSM Timeout has occurred. 0x1: CSR FSM Timeout Error Status detected 0x0: CSR FSM Timeout Error Status not detected" "CSR FSM Timeout Error Status not detected,CSR FSM Timeout Error Status detected" newline bitfld.long 0x0 9. "RTES,Rx FSM Timeout Error Status This field when set indicates that one of the Rx FSM Timeout has occurred. 0x1: Rx FSM Timeout Error Status detected 0x0: Rx FSM Timeout Error Status not detected" "Rx FSM Timeout Error Status not detected,Rx FSM Timeout Error Status detected" newline bitfld.long 0x0 8. "TTES,Tx FSM Timeout Error Status This field when set indicates that one of the Tx FSM Timeout has occurred. 0x1: Tx FSM Timeout Error Status detected 0x0: Tx FSM Timeout Error Status not detected" "Tx FSM Timeout Error Status not detected,Tx FSM Timeout Error Status detected" newline rbitfld.long 0x0 7. "RESERVED_ASRPES,Reserved." "0,1" newline rbitfld.long 0x0 6. "RESERVED_CWPES,Reserved." "0,1" newline bitfld.long 0x0 5. "ARPES,Application Receive interface data path Parity Error Status This bit when set indicates that a parity error is detected at following checkers based on the system configuration as described below - In MTL configuration (DWC_EQOS_SYS=1) parity.." "Application Receive interface data path Parity..,Application Receive interface data path Parity.." newline bitfld.long 0x0 4. "MTSPES,MTL TX Status data path Parity checker Error Status This filed when set indicates that parity error is detected on the MTL TX Status data on ati interface (or at PC5 as shown in Fig.Transmit data path parity protection). 0x1: MTL TX Status data.." "MTL TX Status data path Parity checker Error..,MTL TX Status data path Parity checker Error.." newline bitfld.long 0x0 3. "MPES,MTL data path Parity checker Error Status This bit when set indicates that a parity error is detected at the MTL transmit write controller parity checker (or at PC4 as shown in Fig.Transmit data path parity protection). 0x1: MTL data path Parity.." "MTL data path Parity checker Error Status not..,MTL data path Parity checker Error Status detected" newline bitfld.long 0x0 2. "RDPES,Read Descriptor Parity checker Error Status This bit when set indicates that a parity error is detected at the DMA Read descriptor parity checker (or at PC3 as shown in Fig.Transmit data path parity protection). 0x1: Read Descriptor Parity checker.." "Read Descriptor Parity checker Error Status not..,Read Descriptor Parity checker Error Status.." newline rbitfld.long 0x0 1. "RESERVED_TPES,Reserved." "0,1" newline bitfld.long 0x0 0. "ATPES,Application Transmit Interface Parity checker Error Status This bit when set indicates that a parity error is detected on the AXI/AHB Master read data parity checker. This bit when set indicates that a parity error is detected on the interface port.." "Application Transmit Interface Parity checker..,Application Transmit Interface Parity checker.." group.long 0x148++0xB line.long 0x0 "MAC_FSM_CONTROL,This register is used to control the FSM State parity and timeout error injection in Debug mode." rbitfld.long 0x0 31. "RESERVED_RVCLGRNML,Reserved." "0,1" newline rbitfld.long 0x0 30. "RESERVED_R125LGRNML,Reserved." "0,1" newline rbitfld.long 0x0 29. "RESERVED_T125LGRNML,Reserved." "0,1" newline bitfld.long 0x0 28. "PLGRNML,PTP Large/Normal Mode Select This field when set indicates that large mode tic generation is used for PTP domain else normal mode tic generation is used. 0x0: normal mode tic generation is used for PTP domain 0x1: large mode tic generation is.." "normal mode tic generation is used for PTP domain,large mode tic generation is used for PTP domain" newline bitfld.long 0x0 27. "ALGRNML,APP Large/Normal Mode Select This field when set indicates that large mode tic generation is used for APP domain else normal mode tic generation is used. 0x0: normal mode tic generation is used for APP domain 0x1: large mode tic generation is.." "normal mode tic generation is used for APP domain,large mode tic generation is used for APP domain" newline bitfld.long 0x0 26. "CLGRNML,CSR Large/Normal Mode Select This field when set indicates that large mode tic generation is used for CSR domain else normal mode tic generation is used. 0x0: normal mode tic generation is used for CSR domain 0x1: large mode tic generation is.." "normal mode tic generation is used for CSR domain,large mode tic generation is used for CSR domain" newline bitfld.long 0x0 25. "RLGRNML,Rx Large/Normal Mode Select This field when set indicates that large mode tic generation is used for Rx domain else normal mode tic generation is used. 0x0: normal mode tic generation is used for Rx domain 0x1: large mode tic generation is used.." "normal mode tic generation is used for Rx domain,large mode tic generation is used for Rx domain" newline bitfld.long 0x0 24. "TLGRNML,Tx Large/Normal Mode Select This field when set indicates that large mode tic generation is used for Tx domain else normal mode tic generation is used. 0x0: normal mode tic generation is used for Tx domain 0x1: large mode tic generation is used.." "normal mode tic generation is used for Tx domain,large mode tic generation is used for Tx domain" newline rbitfld.long 0x0 23. "RESERVED_RVCPEIN,Reserved." "0,1" newline rbitfld.long 0x0 22. "RESERVED_R125PEIN,Reserved." "0,1" newline rbitfld.long 0x0 21. "RESERVED_T125PEIN,Reserved." "0,1" newline bitfld.long 0x0 20. "PPEIN,PTP FSM Parity Error Injection This field when set indicates that Error Injection for PTP FSM Parity is enabled. 0x0: PTP FSM Parity Error Injection is disabled 0x1: PTP FSM Parity Error Injection is enabled" "PTP FSM Parity Error Injection is disabled,PTP FSM Parity Error Injection is enabled" newline bitfld.long 0x0 19. "APEIN,APP FSM Parity Error Injection This field when set indicates that Error Injection for APP FSM Parity is enabled. 0x0: APP FSM Parity Error Injection is disabled 0x1: APP FSM Parity Error Injection is enabled" "APP FSM Parity Error Injection is disabled,APP FSM Parity Error Injection is enabled" newline bitfld.long 0x0 18. "CPEIN,CSR FSM Parity Error Injection This field when set indicates that Error Injection for CSR Parity is enabled. 0x0: CSR FSM Parity Error Injection is disabled 0x1: CSR FSM Parity Error Injection is enabled" "CSR FSM Parity Error Injection is disabled,CSR FSM Parity Error Injection is enabled" newline bitfld.long 0x0 17. "RPEIN,Rx FSM Parity Error Injection This field when set indicates that Error Injection for RX FSM Parity is enabled. 0x0: Rx FSM Parity Error Injection is disabled 0x1: Rx FSM Parity Error Injection is enabled" "Rx FSM Parity Error Injection is disabled,Rx FSM Parity Error Injection is enabled" newline bitfld.long 0x0 16. "TPEIN,Tx FSM Parity Error Injection This field when set indicates that Error Injection for TX FSM Parity is enabled. 0x0: Tx FSM Parity Error Injection is disabled 0x1: Tx FSM Parity Error Injection is enabled" "Tx FSM Parity Error Injection is disabled,Tx FSM Parity Error Injection is enabled" newline rbitfld.long 0x0 15. "RESERVED_RVCTEIN,Reserved." "0,1" newline rbitfld.long 0x0 14. "RESERVED_R125TEIN,Reserved." "0,1" newline rbitfld.long 0x0 13. "RESERVED_T125TEIN,Reserved." "0,1" newline bitfld.long 0x0 12. "PTEIN,PTP FSM Timeout Error Injection This field when set indicates that Error Injection for PTP FSM timeout is enabled. 0x0: PTP FSM Timeout Error Injection is disabled 0x1: PTP FSM Timeout Error Injection is enabled" "PTP FSM Timeout Error Injection is disabled,PTP FSM Timeout Error Injection is enabled" newline bitfld.long 0x0 11. "ATEIN,APP FSM Timeout Error Injection This field when set indicates that Error Injection for APP FSM timeout is enabled. 0x0: APP FSM Timeout Error Injection is disabled 0x1: APP FSM Timeout Error Injection is enabled" "APP FSM Timeout Error Injection is disabled,APP FSM Timeout Error Injection is enabled" newline bitfld.long 0x0 10. "CTEIN,CSR FSM Timeout Error Injection This field when set indicates that Error Injection for CSR timeout is enabled. 0x0: CSR FSM Timeout Error Injection is disabled 0x1: CSR FSM Timeout Error Injection is enabled" "CSR FSM Timeout Error Injection is disabled,CSR FSM Timeout Error Injection is enabled" newline bitfld.long 0x0 9. "RTEIN,Rx FSM Timeout Error Injection This field when set indicates that Error Injection for RX FSM timeout is enabled. 0x0: Rx FSM Timeout Error Injection is disabled 0x1: Rx FSM Timeout Error Injection is enabled" "Rx FSM Timeout Error Injection is disabled,Rx FSM Timeout Error Injection is enabled" newline bitfld.long 0x0 8. "TTEIN,Tx FSM Timeout Error Injection This field when set indicates that Error Injection for TX FSM timeout is enabled. 0x0: Tx FSM Timeout Error Injection is disabled 0x1: Tx FSM Timeout Error Injection is enabled" "Tx FSM Timeout Error Injection is disabled,Tx FSM Timeout Error Injection is enabled" newline hexmask.long.byte 0x0 2.--7. 1. "RESERVED_7_2," newline bitfld.long 0x0 1. "PRTYEN,This bit when set indicates that the FSM parity feature is enabled. 0x0: FSM Parity feature is disabled 0x1: FSM Parity feature is enabled" "FSM Parity feature is disabled,FSM Parity feature is enabled" newline bitfld.long 0x0 0. "TMOUTEN,This bit when set indicates that the FSM timeout feature is enabled. 0x0: FSM timeout feature is disabled 0x1: FSM timeout feature is enabled" "FSM timeout feature is disabled,FSM timeout feature is enabled" line.long 0x4 "MAC_FSM_ACT_TIMER,This register is used to select the FSM and Interface Timeout values." hexmask.long.byte 0x4 24.--31. 1. "RESERVED_31_24,Reserved." newline hexmask.long.byte 0x4 20.--23. 1. "LTMRMD,This field provides the mode value to be used for large mode FSM and other interface time outs. The timeout duration based on the mode value is given below 0x3: 16.384ms (~16ms) 0x8: 16.777sec (~16sec) 0x1: 1us 0x6: 1.048sec (~1sec) 0x5: 262.144ms.." newline hexmask.long.byte 0x4 16.--19. 1. "NTMRMD,This field provides the value to be used for normal mode FSM and other interface time outs. The timeout duration based on the mode value is given below 0x3: 16.384ms (~16ms) 0x8: 16.777sec (~16sec) 0x1: 1us 0x6: 1.048sec (~1sec) 0x5: 262.144ms.." newline hexmask.long.byte 0x4 10.--15. 1. "RESERVED_15_10,Reserved." newline hexmask.long.word 0x4 0.--9. 1. "TMR,This field indicates the number of CSR clocks required to generate 1us tic." line.long 0x8 "SNPS_SCS_REG1,Synopsys Reserved Register" hexmask.long 0x8 0.--31. 1. "MAC_SCS1,Synopsys Reserved All the bits must be set to '0'. This field is reserved for Synopsys Internal use and must always be set to '0' unless instructed by Synopsys. Setting any bit to '1' might cause unexpected behavior in the IP." group.long 0x200++0x7 line.long 0x0 "MAC_MDIO_ADDRESS,The MDIO Address register controls the management cycles to external PHY through a management interface." hexmask.long.byte 0x0 28.--31. 1. "RESERVED_31_28,Reserved." newline bitfld.long 0x0 27. "PSE,Preamble Suppression Enable When this bit is set the SMA suppresses the 32-bit preamble and transmits MDIO frames with only 1 preamble bit. When this bit is 0 the MDIO frame always has 32 bits of preamble as defined in the IEEE specifications. 0x0:.." "Preamble Suppression disabled,Preamble Suppression enabled" newline bitfld.long 0x0 26. "BTB,Back to Back transactions When this bit is set and the NTC has value greater than 0 then the MAC informs the completion of a read or write command at the end of frame transfer (before the trailing clocks are transmitted). The software can thus.." "Back to Back transactions disabled,Back to Back transactions enabled" newline hexmask.long.byte 0x0 21.--25. 1. "PA,Physical Layer Address This field indicates which Clause 22 PHY devices (out of 32 devices) the MAC is accessing. This field indicates which Clause 45 capable PHYs (out of 32 PHYs) the MAC is accessing." newline hexmask.long.byte 0x0 16.--20. 1. "RDA,Register/Device Address These bits select the PHY register in selected Clause 22 PHY device. These bits select the Device (MMD) in selected Clause 45 capable PHY." newline rbitfld.long 0x0 15. "RESERVED_15,Reserved." "0,1" newline bitfld.long 0x0 12.--14. "NTC,Number of Trailing Clocks This field controls the number of trailing clock cycles generated on gmii_mdc_o (MDC) after the end of transmission of MDIO frame. The valid values can be from 0 to 7. Programming the value to 3'h3 indicates that there are.." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x0 8.--11. 1. "CR,CSR Clock Range The CSR Clock Range selection determines the frequency of the MDC clock according to the CSR clock frequency used in your design: - 0000: CSR clock = 60-100 MHz; MDC clock = CSR clock/42 - 0001: CSR clock = 100-150 MHz; MDC clock = CSR.." newline rbitfld.long 0x0 5.--7. "RESERVED_7_5,Reserved." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 4. "SKAP,Skip Address Packet When this bit is set the SMA does not send the address packets before read write or post-read increment address packets. This bit is valid only when C45E is set. 0x0: Skip Address Packet is disabled 0x1: Skip Address Packet is.." "Skip Address Packet is disabled,Skip Address Packet is enabled" newline bitfld.long 0x0 3. "GOC_1,GMII Operation Command 1 This bit is higher bit of the operation command to the PHY GOC_1 and GOC_O is encoded as follows: - 00: Reserved - 01: Write - 10: Post Read Increment Address for Clause 45 PHY - 11: Read When Clause 22 PHY is enabled.." "GMII Operation Command 1 is disabled,GMII Operation Command 1 is enabled" newline bitfld.long 0x0 2. "GOC_0,GMII Operation Command 0 This is the lower bit of the operation command to the PHY. When in SMA mode (MDIO master) this bit along with GOC_1 determines the operation to be performed to the PHY. 0x0: GMII Operation Command 0 is disabled 0x1: GMII.." "GMII Operation Command 0 is disabled,GMII Operation Command 0 is enabled" newline bitfld.long 0x0 1. "C45E,Clause 45 PHY Enable When this bit is set Clause 45 capable PHY is connected to MDIO. When this bit is reset Clause 22 capable PHY is connected to MDIO. 0x0: Clause 45 PHY is disabled 0x1: Clause 45 PHY is enabled" "Clause 45 PHY is disabled,Clause 45 PHY is enabled" newline bitfld.long 0x0 0. "GB,GMII Busy The application sets this bit to instruct the SMA to initiate a Read or Write access to the MDIO slave. The MAC clears this bit after the MDIO frame transfer is completed. Hence the software must not write or change any of the fields in.." "GMII Busy is disabled,GMII Busy is enabled" line.long 0x4 "MAC_MDIO_DATA,The MDIO Data register stores the Write data to be written to the PHY register located at the address specified in MAC_MDIO_Address. This register also stores the Read data from the PHY register located at the address specified by MDIO.." hexmask.long.word 0x4 16.--31. 1. "RA,Register Address This field is valid only when C45E is set. It contains the Register Address in the PHY to which the MDIO frame is intended for." newline hexmask.long.word 0x4 0.--15. 1. "GD,GMII Data This field contains the 16-bit data value read from the PHY after a Management Read operation or the 16-bit data value to be written to the PHY before a Management Write operation." group.long 0x230++0x7 line.long 0x0 "MAC_CSR_SW_CTRL,This register contains SW programmable controls for changing the CSR access response and status bits clearing." hexmask.long.tbyte 0x0 9.--31. 1. "RESERVED_31_9,Reserved." newline bitfld.long 0x0 8. "SEEN,Slave Error Response Enable When this bit is set the MAC responds with Slave Error for accesses to reserved registers in CSR space. When this bit is reset the MAC responds with Okay response to any register accessed from CSR space. 0x0: Slave.." "Slave Error Response is disabled,Slave Error Response is enabled" newline hexmask.long.byte 0x0 1.--7. 1. "RESERVED_7_1,Reserved." newline bitfld.long 0x0 0. "RCWE,Register Clear on Write 1 Enable When this bit is set the access mode of some register fields changes to Clear on Write 1 the application needs to set that respective bit to 1 to clear it. When this bit is reset the access mode of these register.." "Register Clear on Write 1 is disabled,Register Clear on Write 1 is enabled" line.long 0x4 "MAC_FPE_CTRL_STS,This register controls the operation of Frame Preemption." hexmask.long.word 0x4 20.--31. 1. "RESERVED_31_20,Reserved." newline bitfld.long 0x4 19. "TRSP,Transmitted Respond Frame Set when a Respond mPacket is transmitted (triggered by setting SRSP field). An interrupt can be generated for this event if FPEIE bit of MAC_Interrupt_Enable is set. Access restriction applies. Clears on read (or write of.." "Not transmitted Respond Frame,transmitted Respond Frame" newline bitfld.long 0x4 18. "TVER,Transmitted Verify Frame Set when a Verify mPacket is transmitted (triggered by setting SVER field). An interrupt can be generated for this event if FPEIE bit of MAC_Interrupt_Enable is set. Access restriction applies. Clears on read (or write of 1.." "Not transmitted Verify Frame,transmitted Verify Frame" newline bitfld.long 0x4 17. "RRSP,Received Respond Frame Set when a Respond mPacket is received. An interrupt can be generated for this event if FPEIE bit of MAC_Interrupt_Enable is set. Access restriction applies. Clears on read (or write of 1 when RCWE bit in MAC_CSR_SW_Ctrl.." "Not received Respond Frame,Received Respond Frame" newline bitfld.long 0x4 16. "RVER,Received Verify Frame Set when a Verify mPacket is received. An interrupt can be generated for this event if FPEIE bit of MAC_Interrupt_Enable is set. Access restriction applies. Clears on read (or write of 1 when RCWE bit in MAC_CSR_SW_Ctrl.." "Not received Verify Frame,Received Verify Frame" newline hexmask.long.word 0x4 4.--15. 1. "RESERVED_15_4,Reserved." newline bitfld.long 0x4 3. "S1_SET_0,Synopsys Reserved Must be set to '0'. This field is reserved for Synopsys Internal use and must always be set to '0' unless instructed by Synopsys. Setting to '1' might cause unexpected behavior in the IP." "0,1" newline bitfld.long 0x4 2. "SRSP,Send Respond mPacket When set indicates hardware to send a Respond mPacket. Reset by hardware after sending the Respond mPacket. Access restriction applies. Setting 1 sets. Self-cleared. Setting 0 has no effect. 0x0: Send Respond mPacket is disabled.." "Send Respond mPacket is disabled,Send Respond mPacket is enabled" newline bitfld.long 0x4 1. "SVER,Send Verify mPacket When set indicates hardware to send a verify mPacket. Reset by hardware after sending the Verify mPacket. Access restriction applies. Setting 1 sets. Self-cleared. Setting 0 has no effect. 0x0: Send Verify mPacket is disabled.." "Send Verify mPacket is disabled,Send Verify mPacket is enabled" newline bitfld.long 0x4 0. "EFPE,Enable Tx Frame Preemption When set Frame Preemption Tx functionality is enabled. 0x0: Tx Frame Preemption is disabled 0x1: Tx Frame Preemption is enabled" "Tx Frame Preemption is disabled,Tx Frame Preemption is enabled" rgroup.long 0x240++0x3 line.long 0x0 "MAC_PRESN_TIME_NS,This register contains the 32-bit binary rollover equivalent time of the PTP System Time in ns Exists when DWC_EQOS_FLEXI_PPS_OUT_EN is configured" hexmask.long 0x0 0.--31. 1. "MPTN,MAC 1722 Presentation Time in ns These bits indicate the value of the 32-bit binary rollover equivalent time of the PTP System Time in ns" group.long 0x244++0x3 line.long 0x0 "MAC_PRESN_TIME_UPDT,This field holds the 32-bit value of MAC 1722 Presentation Time in ns. that should be added to the Current Presentation Time Counter value. Init happens when TSINIT is set. and update happens when the TSUPDT bit is set (TSINIT and.." hexmask.long 0x0 0.--31. 1. "MPTU,MAC 1722 Presentation Time Update This field holds the init value or the update value for the presentation time. When used for update this field holds the 32-bit value in ns that should be added to the Current Presentation Time Counter value. Init.." group.long 0x300++0x403 line.long 0x0 "MAC_ADDRESS0_HIGH,The MAC Address0 High register holds the upper 16 bits of the first 6-byte MAC address of the station. The first DA byte that is received on the (G)MII interface corresponds to the LS byte (Bits [7:0]) of the MAC Address Low register." rbitfld.long 0x0 31. "AE,Address Enable This bit is always set to 1. 0x0: INVALID : This bit must be always set to 1 0x1: This bit is always set to 1" "INVALID : This bit must be always set to 1,This bit is always set to 1" newline hexmask.long.word 0x0 21.--30. 1. "RESERVED_30_Y,Reserved." newline hexmask.long.byte 0x0 16.--20. 1. "DCS,DMA Channel Select If the PDC bit of MAC_Ext_Configuration register is not set: This field contains the binary representation of the DMA Channel number to which an Rx packet whose DA matches the MAC Address0 content is routed. If the PDC bit of.." newline hexmask.long.word 0x0 0.--15. 1. "ADDRHI,MAC Address0[47:32] This field contains the upper 16 bits [47:32] of the first 6-byte MAC address. The MAC uses this field for filtering the received packets and inserting the MAC address in the Transmit Flow Control (Pause) Packets." line.long 0x4 "MAC_ADDRESS0_LOW,The MAC Address0 Low register holds the lower 32 bits of the 6-byte first MAC address of the station." hexmask.long 0x4 0.--31. 1. "ADDRLO,MAC Address0[31:0] This field contains the lower 32 bits of the first 6-byte MAC address. The MAC uses this field for filtering the received packets and inserting the MAC address in the Transmit Flow Control (Pause) Packets." line.long 0x8 "MAC_ADDRESS1_HIGH,The MAC Address1 High register holds the upper 16 bits of the second 6-byte MAC address of the station. If the MAC address registers are configured to be double-synchronized to the (G)MII clock domains. the synchronization is triggered.." bitfld.long 0x8 31. "AE,Address Enable When this bit is set the address filter module uses the second MAC address for perfect filtering. When this bit is reset the address filter module ignores the address for filtering. 0x0: Address is ignored 0x1: Address is enabled" "Address is ignored,Address is enabled" newline bitfld.long 0x8 30. "SA,Source Address When this bit is set the MAC Address1[47:0] is used to compare with the SA fields of the received packet. When this bit is reset the MAC Address1[47:0] is used to compare with the DA fields of the received packet. 0x0: Compare with.." "Compare with Destination Address,Compare with Source Address" newline hexmask.long.byte 0x8 24.--29. 1. "MBC,Mask Byte Control These bits are mask control bits for comparing each of the MAC Address bytes. When set high the MAC does not compare the corresponding byte of received DA or SA with the contents of MAC Address1 registers. Each bit controls the.." newline rbitfld.long 0x8 21.--23. "RESERVED_23_Y,Reserved." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x8 16.--20. 1. "DCS,DMA Channel Select If the PDC bit of MAC_Ext_Configuration register is not set: This field contains the binary representation of the DMA Channel number to which an Rx packet whose DA matches the MAC Address(#i) content is routed. If the PDC bit of.." newline hexmask.long.word 0x8 0.--15. 1. "ADDRHI,MAC Address1 [47:32] This field contains the upper 16 bits[47:32] of the second 6-byte MAC address." line.long 0xC "MAC_ADDRESS1_LOW,The MAC Address1 Low register holds the lower 32 bits of the second 6-byte MAC address of the station." hexmask.long 0xC 0.--31. 1. "ADDRLO,MAC Address1 [31:0] This field contains the lower 32 bits of second 6-byte MAC address. The content of this field is undefined until loaded by the application after the initialization process." line.long 0x10 "MAC_ADDRESS2_HIGH,The MAC Address1 High register holds the upper 16 bits of the second 6-byte MAC address of the station. If the MAC address registers are configured to be double-synchronized to the (G)MII clock domains. the synchronization is triggered.." bitfld.long 0x10 31. "AE,Address Enable When this bit is set the address filter module uses the second MAC address for perfect filtering. When this bit is reset the address filter module ignores the address for filtering. 0x0: Address is ignored 0x1: Address is enabled" "Address is ignored,Address is enabled" newline bitfld.long 0x10 30. "SA,Source Address When this bit is set the MAC Address1[47:0] is used to compare with the SA fields of the received packet. When this bit is reset the MAC Address1[47:0] is used to compare with the DA fields of the received packet. 0x0: Compare with.." "Compare with Destination Address,Compare with Source Address" newline hexmask.long.byte 0x10 24.--29. 1. "MBC,Mask Byte Control These bits are mask control bits for comparing each of the MAC Address bytes. When set high the MAC does not compare the corresponding byte of received DA or SA with the contents of MAC Address1 registers. Each bit controls the.." newline rbitfld.long 0x10 21.--23. "RESERVED_23_Y,Reserved." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x10 16.--20. 1. "DCS,DMA Channel Select If the PDC bit of MAC_Ext_Configuration register is not set: This field contains the binary representation of the DMA Channel number to which an Rx packet whose DA matches the MAC Address(#i) content is routed. If the PDC bit of.." newline hexmask.long.word 0x10 0.--15. 1. "ADDRHI,MAC Address1 [47:32] This field contains the upper 16 bits[47:32] of the second 6-byte MAC address." line.long 0x14 "MAC_ADDRESS2_LOW,The MAC Address1 Low register holds the lower 32 bits of the second 6-byte MAC address of the station." hexmask.long 0x14 0.--31. 1. "ADDRLO,MAC Address1 [31:0] This field contains the lower 32 bits of second 6-byte MAC address. The content of this field is undefined until loaded by the application after the initialization process." line.long 0x18 "MAC_ADDRESS3_HIGH,The MAC Address1 High register holds the upper 16 bits of the second 6-byte MAC address of the station. If the MAC address registers are configured to be double-synchronized to the (G)MII clock domains. the synchronization is triggered.." bitfld.long 0x18 31. "AE,Address Enable When this bit is set the address filter module uses the second MAC address for perfect filtering. When this bit is reset the address filter module ignores the address for filtering. 0x0: Address is ignored 0x1: Address is enabled" "Address is ignored,Address is enabled" newline bitfld.long 0x18 30. "SA,Source Address When this bit is set the MAC Address1[47:0] is used to compare with the SA fields of the received packet. When this bit is reset the MAC Address1[47:0] is used to compare with the DA fields of the received packet. 0x0: Compare with.." "Compare with Destination Address,Compare with Source Address" newline hexmask.long.byte 0x18 24.--29. 1. "MBC,Mask Byte Control These bits are mask control bits for comparing each of the MAC Address bytes. When set high the MAC does not compare the corresponding byte of received DA or SA with the contents of MAC Address1 registers. Each bit controls the.." newline rbitfld.long 0x18 21.--23. "RESERVED_23_Y,Reserved." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x18 16.--20. 1. "DCS,DMA Channel Select If the PDC bit of MAC_Ext_Configuration register is not set: This field contains the binary representation of the DMA Channel number to which an Rx packet whose DA matches the MAC Address(#i) content is routed. If the PDC bit of.." newline hexmask.long.word 0x18 0.--15. 1. "ADDRHI,MAC Address1 [47:32] This field contains the upper 16 bits[47:32] of the second 6-byte MAC address." line.long 0x1C "MAC_ADDRESS3_LOW,The MAC Address1 Low register holds the lower 32 bits of the second 6-byte MAC address of the station." hexmask.long 0x1C 0.--31. 1. "ADDRLO,MAC Address1 [31:0] This field contains the lower 32 bits of second 6-byte MAC address. The content of this field is undefined until loaded by the application after the initialization process." line.long 0x20 "MAC_ADDRESS4_HIGH,The MAC Address1 High register holds the upper 16 bits of the second 6-byte MAC address of the station. If the MAC address registers are configured to be double-synchronized to the (G)MII clock domains. the synchronization is triggered.." bitfld.long 0x20 31. "AE,Address Enable When this bit is set the address filter module uses the second MAC address for perfect filtering. When this bit is reset the address filter module ignores the address for filtering. 0x0: Address is ignored 0x1: Address is enabled" "Address is ignored,Address is enabled" newline bitfld.long 0x20 30. "SA,Source Address When this bit is set the MAC Address1[47:0] is used to compare with the SA fields of the received packet. When this bit is reset the MAC Address1[47:0] is used to compare with the DA fields of the received packet. 0x0: Compare with.." "Compare with Destination Address,Compare with Source Address" newline hexmask.long.byte 0x20 24.--29. 1. "MBC,Mask Byte Control These bits are mask control bits for comparing each of the MAC Address bytes. When set high the MAC does not compare the corresponding byte of received DA or SA with the contents of MAC Address1 registers. Each bit controls the.." newline rbitfld.long 0x20 21.--23. "RESERVED_23_Y,Reserved." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x20 16.--20. 1. "DCS,DMA Channel Select If the PDC bit of MAC_Ext_Configuration register is not set: This field contains the binary representation of the DMA Channel number to which an Rx packet whose DA matches the MAC Address(#i) content is routed. If the PDC bit of.." newline hexmask.long.word 0x20 0.--15. 1. "ADDRHI,MAC Address1 [47:32] This field contains the upper 16 bits[47:32] of the second 6-byte MAC address." line.long 0x24 "MAC_ADDRESS4_LOW,The MAC Address1 Low register holds the lower 32 bits of the second 6-byte MAC address of the station." hexmask.long 0x24 0.--31. 1. "ADDRLO,MAC Address1 [31:0] This field contains the lower 32 bits of second 6-byte MAC address. The content of this field is undefined until loaded by the application after the initialization process." line.long 0x28 "MAC_ADDRESS5_HIGH,The MAC Address1 High register holds the upper 16 bits of the second 6-byte MAC address of the station. If the MAC address registers are configured to be double-synchronized to the (G)MII clock domains. the synchronization is triggered.." bitfld.long 0x28 31. "AE,Address Enable When this bit is set the address filter module uses the second MAC address for perfect filtering. When this bit is reset the address filter module ignores the address for filtering. 0x0: Address is ignored 0x1: Address is enabled" "Address is ignored,Address is enabled" newline bitfld.long 0x28 30. "SA,Source Address When this bit is set the MAC Address1[47:0] is used to compare with the SA fields of the received packet. When this bit is reset the MAC Address1[47:0] is used to compare with the DA fields of the received packet. 0x0: Compare with.." "Compare with Destination Address,Compare with Source Address" newline hexmask.long.byte 0x28 24.--29. 1. "MBC,Mask Byte Control These bits are mask control bits for comparing each of the MAC Address bytes. When set high the MAC does not compare the corresponding byte of received DA or SA with the contents of MAC Address1 registers. Each bit controls the.." newline rbitfld.long 0x28 21.--23. "RESERVED_23_Y,Reserved." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x28 16.--20. 1. "DCS,DMA Channel Select If the PDC bit of MAC_Ext_Configuration register is not set: This field contains the binary representation of the DMA Channel number to which an Rx packet whose DA matches the MAC Address(#i) content is routed. If the PDC bit of.." newline hexmask.long.word 0x28 0.--15. 1. "ADDRHI,MAC Address1 [47:32] This field contains the upper 16 bits[47:32] of the second 6-byte MAC address." line.long 0x2C "MAC_ADDRESS5_LOW,The MAC Address1 Low register holds the lower 32 bits of the second 6-byte MAC address of the station." hexmask.long 0x2C 0.--31. 1. "ADDRLO,MAC Address1 [31:0] This field contains the lower 32 bits of second 6-byte MAC address. The content of this field is undefined until loaded by the application after the initialization process." line.long 0x30 "MAC_ADDRESS6_HIGH,The MAC Address1 High register holds the upper 16 bits of the second 6-byte MAC address of the station. If the MAC address registers are configured to be double-synchronized to the (G)MII clock domains. the synchronization is triggered.." bitfld.long 0x30 31. "AE,Address Enable When this bit is set the address filter module uses the second MAC address for perfect filtering. When this bit is reset the address filter module ignores the address for filtering. 0x0: Address is ignored 0x1: Address is enabled" "Address is ignored,Address is enabled" newline bitfld.long 0x30 30. "SA,Source Address When this bit is set the MAC Address1[47:0] is used to compare with the SA fields of the received packet. When this bit is reset the MAC Address1[47:0] is used to compare with the DA fields of the received packet. 0x0: Compare with.." "Compare with Destination Address,Compare with Source Address" newline hexmask.long.byte 0x30 24.--29. 1. "MBC,Mask Byte Control These bits are mask control bits for comparing each of the MAC Address bytes. When set high the MAC does not compare the corresponding byte of received DA or SA with the contents of MAC Address1 registers. Each bit controls the.." newline rbitfld.long 0x30 21.--23. "RESERVED_23_Y,Reserved." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x30 16.--20. 1. "DCS,DMA Channel Select If the PDC bit of MAC_Ext_Configuration register is not set: This field contains the binary representation of the DMA Channel number to which an Rx packet whose DA matches the MAC Address(#i) content is routed. If the PDC bit of.." newline hexmask.long.word 0x30 0.--15. 1. "ADDRHI,MAC Address1 [47:32] This field contains the upper 16 bits[47:32] of the second 6-byte MAC address." line.long 0x34 "MAC_ADDRESS6_LOW,The MAC Address1 Low register holds the lower 32 bits of the second 6-byte MAC address of the station." hexmask.long 0x34 0.--31. 1. "ADDRLO,MAC Address1 [31:0] This field contains the lower 32 bits of second 6-byte MAC address. The content of this field is undefined until loaded by the application after the initialization process." line.long 0x38 "MAC_ADDRESS7_HIGH,The MAC Address1 High register holds the upper 16 bits of the second 6-byte MAC address of the station. If the MAC address registers are configured to be double-synchronized to the (G)MII clock domains. the synchronization is triggered.." bitfld.long 0x38 31. "AE,Address Enable When this bit is set the address filter module uses the second MAC address for perfect filtering. When this bit is reset the address filter module ignores the address for filtering. 0x0: Address is ignored 0x1: Address is enabled" "Address is ignored,Address is enabled" newline bitfld.long 0x38 30. "SA,Source Address When this bit is set the MAC Address1[47:0] is used to compare with the SA fields of the received packet. When this bit is reset the MAC Address1[47:0] is used to compare with the DA fields of the received packet. 0x0: Compare with.." "Compare with Destination Address,Compare with Source Address" newline hexmask.long.byte 0x38 24.--29. 1. "MBC,Mask Byte Control These bits are mask control bits for comparing each of the MAC Address bytes. When set high the MAC does not compare the corresponding byte of received DA or SA with the contents of MAC Address1 registers. Each bit controls the.." newline rbitfld.long 0x38 21.--23. "RESERVED_23_Y,Reserved." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x38 16.--20. 1. "DCS,DMA Channel Select If the PDC bit of MAC_Ext_Configuration register is not set: This field contains the binary representation of the DMA Channel number to which an Rx packet whose DA matches the MAC Address(#i) content is routed. If the PDC bit of.." newline hexmask.long.word 0x38 0.--15. 1. "ADDRHI,MAC Address1 [47:32] This field contains the upper 16 bits[47:32] of the second 6-byte MAC address." line.long 0x3C "MAC_ADDRESS7_LOW,The MAC Address1 Low register holds the lower 32 bits of the second 6-byte MAC address of the station." hexmask.long 0x3C 0.--31. 1. "ADDRLO,MAC Address1 [31:0] This field contains the lower 32 bits of second 6-byte MAC address. The content of this field is undefined until loaded by the application after the initialization process." line.long 0x40 "MAC_ADDRESS8_HIGH,The MAC Address1 High register holds the upper 16 bits of the second 6-byte MAC address of the station. If the MAC address registers are configured to be double-synchronized to the (G)MII clock domains. the synchronization is triggered.." bitfld.long 0x40 31. "AE,Address Enable When this bit is set the address filter module uses the second MAC address for perfect filtering. When this bit is reset the address filter module ignores the address for filtering. 0x0: Address is ignored 0x1: Address is enabled" "Address is ignored,Address is enabled" newline bitfld.long 0x40 30. "SA,Source Address When this bit is set the MAC Address1[47:0] is used to compare with the SA fields of the received packet. When this bit is reset the MAC Address1[47:0] is used to compare with the DA fields of the received packet. 0x0: Compare with.." "Compare with Destination Address,Compare with Source Address" newline hexmask.long.byte 0x40 24.--29. 1. "MBC,Mask Byte Control These bits are mask control bits for comparing each of the MAC Address bytes. When set high the MAC does not compare the corresponding byte of received DA or SA with the contents of MAC Address1 registers. Each bit controls the.." newline rbitfld.long 0x40 21.--23. "RESERVED_23_Y,Reserved." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x40 16.--20. 1. "DCS,DMA Channel Select If the PDC bit of MAC_Ext_Configuration register is not set: This field contains the binary representation of the DMA Channel number to which an Rx packet whose DA matches the MAC Address(#i) content is routed. If the PDC bit of.." newline hexmask.long.word 0x40 0.--15. 1. "ADDRHI,MAC Address1 [47:32] This field contains the upper 16 bits[47:32] of the second 6-byte MAC address." line.long 0x44 "MAC_ADDRESS8_LOW,The MAC Address1 Low register holds the lower 32 bits of the second 6-byte MAC address of the station." hexmask.long 0x44 0.--31. 1. "ADDRLO,MAC Address1 [31:0] This field contains the lower 32 bits of second 6-byte MAC address. The content of this field is undefined until loaded by the application after the initialization process." line.long 0x48 "MAC_ADDRESS9_HIGH,The MAC Address1 High register holds the upper 16 bits of the second 6-byte MAC address of the station. If the MAC address registers are configured to be double-synchronized to the (G)MII clock domains. the synchronization is triggered.." bitfld.long 0x48 31. "AE,Address Enable When this bit is set the address filter module uses the second MAC address for perfect filtering. When this bit is reset the address filter module ignores the address for filtering. 0x0: Address is ignored 0x1: Address is enabled" "Address is ignored,Address is enabled" newline bitfld.long 0x48 30. "SA,Source Address When this bit is set the MAC Address1[47:0] is used to compare with the SA fields of the received packet. When this bit is reset the MAC Address1[47:0] is used to compare with the DA fields of the received packet. 0x0: Compare with.." "Compare with Destination Address,Compare with Source Address" newline hexmask.long.byte 0x48 24.--29. 1. "MBC,Mask Byte Control These bits are mask control bits for comparing each of the MAC Address bytes. When set high the MAC does not compare the corresponding byte of received DA or SA with the contents of MAC Address1 registers. Each bit controls the.." newline rbitfld.long 0x48 21.--23. "RESERVED_23_Y,Reserved." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x48 16.--20. 1. "DCS,DMA Channel Select If the PDC bit of MAC_Ext_Configuration register is not set: This field contains the binary representation of the DMA Channel number to which an Rx packet whose DA matches the MAC Address(#i) content is routed. If the PDC bit of.." newline hexmask.long.word 0x48 0.--15. 1. "ADDRHI,MAC Address1 [47:32] This field contains the upper 16 bits[47:32] of the second 6-byte MAC address." line.long 0x4C "MAC_ADDRESS9_LOW,The MAC Address1 Low register holds the lower 32 bits of the second 6-byte MAC address of the station." hexmask.long 0x4C 0.--31. 1. "ADDRLO,MAC Address1 [31:0] This field contains the lower 32 bits of second 6-byte MAC address. The content of this field is undefined until loaded by the application after the initialization process." line.long 0x50 "MAC_ADDRESS10_HIGH,The MAC Address1 High register holds the upper 16 bits of the second 6-byte MAC address of the station. If the MAC address registers are configured to be double-synchronized to the (G)MII clock domains. the synchronization is triggered.." bitfld.long 0x50 31. "AE,Address Enable When this bit is set the address filter module uses the second MAC address for perfect filtering. When this bit is reset the address filter module ignores the address for filtering. 0x0: Address is ignored 0x1: Address is enabled" "Address is ignored,Address is enabled" newline bitfld.long 0x50 30. "SA,Source Address When this bit is set the MAC Address1[47:0] is used to compare with the SA fields of the received packet. When this bit is reset the MAC Address1[47:0] is used to compare with the DA fields of the received packet. 0x0: Compare with.." "Compare with Destination Address,Compare with Source Address" newline hexmask.long.byte 0x50 24.--29. 1. "MBC,Mask Byte Control These bits are mask control bits for comparing each of the MAC Address bytes. When set high the MAC does not compare the corresponding byte of received DA or SA with the contents of MAC Address1 registers. Each bit controls the.." newline rbitfld.long 0x50 21.--23. "RESERVED_23_Y,Reserved." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x50 16.--20. 1. "DCS,DMA Channel Select If the PDC bit of MAC_Ext_Configuration register is not set: This field contains the binary representation of the DMA Channel number to which an Rx packet whose DA matches the MAC Address(#i) content is routed. If the PDC bit of.." newline hexmask.long.word 0x50 0.--15. 1. "ADDRHI,MAC Address1 [47:32] This field contains the upper 16 bits[47:32] of the second 6-byte MAC address." line.long 0x54 "MAC_ADDRESS10_LOW,The MAC Address1 Low register holds the lower 32 bits of the second 6-byte MAC address of the station." hexmask.long 0x54 0.--31. 1. "ADDRLO,MAC Address1 [31:0] This field contains the lower 32 bits of second 6-byte MAC address. The content of this field is undefined until loaded by the application after the initialization process." line.long 0x58 "MAC_ADDRESS11_HIGH,The MAC Address1 High register holds the upper 16 bits of the second 6-byte MAC address of the station. If the MAC address registers are configured to be double-synchronized to the (G)MII clock domains. the synchronization is triggered.." bitfld.long 0x58 31. "AE,Address Enable When this bit is set the address filter module uses the second MAC address for perfect filtering. When this bit is reset the address filter module ignores the address for filtering. 0x0: Address is ignored 0x1: Address is enabled" "Address is ignored,Address is enabled" newline bitfld.long 0x58 30. "SA,Source Address When this bit is set the MAC Address1[47:0] is used to compare with the SA fields of the received packet. When this bit is reset the MAC Address1[47:0] is used to compare with the DA fields of the received packet. 0x0: Compare with.." "Compare with Destination Address,Compare with Source Address" newline hexmask.long.byte 0x58 24.--29. 1. "MBC,Mask Byte Control These bits are mask control bits for comparing each of the MAC Address bytes. When set high the MAC does not compare the corresponding byte of received DA or SA with the contents of MAC Address1 registers. Each bit controls the.." newline rbitfld.long 0x58 21.--23. "RESERVED_23_Y,Reserved." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x58 16.--20. 1. "DCS,DMA Channel Select If the PDC bit of MAC_Ext_Configuration register is not set: This field contains the binary representation of the DMA Channel number to which an Rx packet whose DA matches the MAC Address(#i) content is routed. If the PDC bit of.." newline hexmask.long.word 0x58 0.--15. 1. "ADDRHI,MAC Address1 [47:32] This field contains the upper 16 bits[47:32] of the second 6-byte MAC address." line.long 0x5C "MAC_ADDRESS11_LOW,The MAC Address1 Low register holds the lower 32 bits of the second 6-byte MAC address of the station." hexmask.long 0x5C 0.--31. 1. "ADDRLO,MAC Address1 [31:0] This field contains the lower 32 bits of second 6-byte MAC address. The content of this field is undefined until loaded by the application after the initialization process." line.long 0x60 "MAC_ADDRESS12_HIGH,The MAC Address1 High register holds the upper 16 bits of the second 6-byte MAC address of the station. If the MAC address registers are configured to be double-synchronized to the (G)MII clock domains. the synchronization is triggered.." bitfld.long 0x60 31. "AE,Address Enable When this bit is set the address filter module uses the second MAC address for perfect filtering. When this bit is reset the address filter module ignores the address for filtering. 0x0: Address is ignored 0x1: Address is enabled" "Address is ignored,Address is enabled" newline bitfld.long 0x60 30. "SA,Source Address When this bit is set the MAC Address1[47:0] is used to compare with the SA fields of the received packet. When this bit is reset the MAC Address1[47:0] is used to compare with the DA fields of the received packet. 0x0: Compare with.." "Compare with Destination Address,Compare with Source Address" newline hexmask.long.byte 0x60 24.--29. 1. "MBC,Mask Byte Control These bits are mask control bits for comparing each of the MAC Address bytes. When set high the MAC does not compare the corresponding byte of received DA or SA with the contents of MAC Address1 registers. Each bit controls the.." newline rbitfld.long 0x60 21.--23. "RESERVED_23_Y,Reserved." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x60 16.--20. 1. "DCS,DMA Channel Select If the PDC bit of MAC_Ext_Configuration register is not set: This field contains the binary representation of the DMA Channel number to which an Rx packet whose DA matches the MAC Address(#i) content is routed. If the PDC bit of.." newline hexmask.long.word 0x60 0.--15. 1. "ADDRHI,MAC Address1 [47:32] This field contains the upper 16 bits[47:32] of the second 6-byte MAC address." line.long 0x64 "MAC_ADDRESS12_LOW,The MAC Address1 Low register holds the lower 32 bits of the second 6-byte MAC address of the station." hexmask.long 0x64 0.--31. 1. "ADDRLO,MAC Address1 [31:0] This field contains the lower 32 bits of second 6-byte MAC address. The content of this field is undefined until loaded by the application after the initialization process." line.long 0x68 "MAC_ADDRESS13_HIGH,The MAC Address1 High register holds the upper 16 bits of the second 6-byte MAC address of the station. If the MAC address registers are configured to be double-synchronized to the (G)MII clock domains. the synchronization is triggered.." bitfld.long 0x68 31. "AE,Address Enable When this bit is set the address filter module uses the second MAC address for perfect filtering. When this bit is reset the address filter module ignores the address for filtering. 0x0: Address is ignored 0x1: Address is enabled" "Address is ignored,Address is enabled" newline bitfld.long 0x68 30. "SA,Source Address When this bit is set the MAC Address1[47:0] is used to compare with the SA fields of the received packet. When this bit is reset the MAC Address1[47:0] is used to compare with the DA fields of the received packet. 0x0: Compare with.." "Compare with Destination Address,Compare with Source Address" newline hexmask.long.byte 0x68 24.--29. 1. "MBC,Mask Byte Control These bits are mask control bits for comparing each of the MAC Address bytes. When set high the MAC does not compare the corresponding byte of received DA or SA with the contents of MAC Address1 registers. Each bit controls the.." newline rbitfld.long 0x68 21.--23. "RESERVED_23_Y,Reserved." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x68 16.--20. 1. "DCS,DMA Channel Select If the PDC bit of MAC_Ext_Configuration register is not set: This field contains the binary representation of the DMA Channel number to which an Rx packet whose DA matches the MAC Address(#i) content is routed. If the PDC bit of.." newline hexmask.long.word 0x68 0.--15. 1. "ADDRHI,MAC Address1 [47:32] This field contains the upper 16 bits[47:32] of the second 6-byte MAC address." line.long 0x6C "MAC_ADDRESS13_LOW,The MAC Address1 Low register holds the lower 32 bits of the second 6-byte MAC address of the station." hexmask.long 0x6C 0.--31. 1. "ADDRLO,MAC Address1 [31:0] This field contains the lower 32 bits of second 6-byte MAC address. The content of this field is undefined until loaded by the application after the initialization process." line.long 0x70 "MAC_ADDRESS14_HIGH,The MAC Address1 High register holds the upper 16 bits of the second 6-byte MAC address of the station. If the MAC address registers are configured to be double-synchronized to the (G)MII clock domains. the synchronization is triggered.." bitfld.long 0x70 31. "AE,Address Enable When this bit is set the address filter module uses the second MAC address for perfect filtering. When this bit is reset the address filter module ignores the address for filtering. 0x0: Address is ignored 0x1: Address is enabled" "Address is ignored,Address is enabled" newline bitfld.long 0x70 30. "SA,Source Address When this bit is set the MAC Address1[47:0] is used to compare with the SA fields of the received packet. When this bit is reset the MAC Address1[47:0] is used to compare with the DA fields of the received packet. 0x0: Compare with.." "Compare with Destination Address,Compare with Source Address" newline hexmask.long.byte 0x70 24.--29. 1. "MBC,Mask Byte Control These bits are mask control bits for comparing each of the MAC Address bytes. When set high the MAC does not compare the corresponding byte of received DA or SA with the contents of MAC Address1 registers. Each bit controls the.." newline rbitfld.long 0x70 21.--23. "RESERVED_23_Y,Reserved." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x70 16.--20. 1. "DCS,DMA Channel Select If the PDC bit of MAC_Ext_Configuration register is not set: This field contains the binary representation of the DMA Channel number to which an Rx packet whose DA matches the MAC Address(#i) content is routed. If the PDC bit of.." newline hexmask.long.word 0x70 0.--15. 1. "ADDRHI,MAC Address1 [47:32] This field contains the upper 16 bits[47:32] of the second 6-byte MAC address." line.long 0x74 "MAC_ADDRESS14_LOW,The MAC Address1 Low register holds the lower 32 bits of the second 6-byte MAC address of the station." hexmask.long 0x74 0.--31. 1. "ADDRLO,MAC Address1 [31:0] This field contains the lower 32 bits of second 6-byte MAC address. The content of this field is undefined until loaded by the application after the initialization process." line.long 0x78 "MAC_ADDRESS15_HIGH,The MAC Address1 High register holds the upper 16 bits of the second 6-byte MAC address of the station. If the MAC address registers are configured to be double-synchronized to the (G)MII clock domains. the synchronization is triggered.." bitfld.long 0x78 31. "AE,Address Enable When this bit is set the address filter module uses the second MAC address for perfect filtering. When this bit is reset the address filter module ignores the address for filtering. 0x0: Address is ignored 0x1: Address is enabled" "Address is ignored,Address is enabled" newline bitfld.long 0x78 30. "SA,Source Address When this bit is set the MAC Address1[47:0] is used to compare with the SA fields of the received packet. When this bit is reset the MAC Address1[47:0] is used to compare with the DA fields of the received packet. 0x0: Compare with.." "Compare with Destination Address,Compare with Source Address" newline hexmask.long.byte 0x78 24.--29. 1. "MBC,Mask Byte Control These bits are mask control bits for comparing each of the MAC Address bytes. When set high the MAC does not compare the corresponding byte of received DA or SA with the contents of MAC Address1 registers. Each bit controls the.." newline rbitfld.long 0x78 21.--23. "RESERVED_23_Y,Reserved." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x78 16.--20. 1. "DCS,DMA Channel Select If the PDC bit of MAC_Ext_Configuration register is not set: This field contains the binary representation of the DMA Channel number to which an Rx packet whose DA matches the MAC Address(#i) content is routed. If the PDC bit of.." newline hexmask.long.word 0x78 0.--15. 1. "ADDRHI,MAC Address1 [47:32] This field contains the upper 16 bits[47:32] of the second 6-byte MAC address." line.long 0x7C "MAC_ADDRESS15_LOW,The MAC Address1 Low register holds the lower 32 bits of the second 6-byte MAC address of the station." hexmask.long 0x7C 0.--31. 1. "ADDRLO,MAC Address1 [31:0] This field contains the lower 32 bits of second 6-byte MAC address. The content of this field is undefined until loaded by the application after the initialization process." line.long 0x80 "MAC_ADDRESS16_HIGH,The MAC Address1 High register holds the upper 16 bits of the second 6-byte MAC address of the station. If the MAC address registers are configured to be double-synchronized to the (G)MII clock domains. the synchronization is triggered.." bitfld.long 0x80 31. "AE,Address Enable When this bit is set the address filter module uses the second MAC address for perfect filtering. When this bit is reset the address filter module ignores the address for filtering. 0x0: Address is ignored 0x1: Address is enabled" "Address is ignored,Address is enabled" newline bitfld.long 0x80 30. "SA,Source Address When this bit is set the MAC Address1[47:0] is used to compare with the SA fields of the received packet. When this bit is reset the MAC Address1[47:0] is used to compare with the DA fields of the received packet. 0x0: Compare with.." "Compare with Destination Address,Compare with Source Address" newline hexmask.long.byte 0x80 24.--29. 1. "MBC,Mask Byte Control These bits are mask control bits for comparing each of the MAC Address bytes. When set high the MAC does not compare the corresponding byte of received DA or SA with the contents of MAC Address1 registers. Each bit controls the.." newline rbitfld.long 0x80 21.--23. "RESERVED_23_Y,Reserved." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x80 16.--20. 1. "DCS,DMA Channel Select If the PDC bit of MAC_Ext_Configuration register is not set: This field contains the binary representation of the DMA Channel number to which an Rx packet whose DA matches the MAC Address(#i) content is routed. If the PDC bit of.." newline hexmask.long.word 0x80 0.--15. 1. "ADDRHI,MAC Address1 [47:32] This field contains the upper 16 bits[47:32] of the second 6-byte MAC address." line.long 0x84 "MAC_ADDRESS16_LOW,The MAC Address1 Low register holds the lower 32 bits of the second 6-byte MAC address of the station." hexmask.long 0x84 0.--31. 1. "ADDRLO,MAC Address1 [31:0] This field contains the lower 32 bits of second 6-byte MAC address. The content of this field is undefined until loaded by the application after the initialization process." line.long 0x88 "MAC_ADDRESS17_HIGH,The MAC Address1 High register holds the upper 16 bits of the second 6-byte MAC address of the station. If the MAC address registers are configured to be double-synchronized to the (G)MII clock domains. the synchronization is triggered.." bitfld.long 0x88 31. "AE,Address Enable When this bit is set the address filter module uses the second MAC address for perfect filtering. When this bit is reset the address filter module ignores the address for filtering. 0x0: Address is ignored 0x1: Address is enabled" "Address is ignored,Address is enabled" newline bitfld.long 0x88 30. "SA,Source Address When this bit is set the MAC Address1[47:0] is used to compare with the SA fields of the received packet. When this bit is reset the MAC Address1[47:0] is used to compare with the DA fields of the received packet. 0x0: Compare with.." "Compare with Destination Address,Compare with Source Address" newline hexmask.long.byte 0x88 24.--29. 1. "MBC,Mask Byte Control These bits are mask control bits for comparing each of the MAC Address bytes. When set high the MAC does not compare the corresponding byte of received DA or SA with the contents of MAC Address1 registers. Each bit controls the.." newline rbitfld.long 0x88 21.--23. "RESERVED_23_Y,Reserved." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x88 16.--20. 1. "DCS,DMA Channel Select If the PDC bit of MAC_Ext_Configuration register is not set: This field contains the binary representation of the DMA Channel number to which an Rx packet whose DA matches the MAC Address(#i) content is routed. If the PDC bit of.." newline hexmask.long.word 0x88 0.--15. 1. "ADDRHI,MAC Address1 [47:32] This field contains the upper 16 bits[47:32] of the second 6-byte MAC address." line.long 0x8C "MAC_ADDRESS17_LOW,The MAC Address1 Low register holds the lower 32 bits of the second 6-byte MAC address of the station." hexmask.long 0x8C 0.--31. 1. "ADDRLO,MAC Address1 [31:0] This field contains the lower 32 bits of second 6-byte MAC address. The content of this field is undefined until loaded by the application after the initialization process." line.long 0x90 "MAC_ADDRESS18_HIGH,The MAC Address1 High register holds the upper 16 bits of the second 6-byte MAC address of the station. If the MAC address registers are configured to be double-synchronized to the (G)MII clock domains. the synchronization is triggered.." bitfld.long 0x90 31. "AE,Address Enable When this bit is set the address filter module uses the second MAC address for perfect filtering. When this bit is reset the address filter module ignores the address for filtering. 0x0: Address is ignored 0x1: Address is enabled" "Address is ignored,Address is enabled" newline bitfld.long 0x90 30. "SA,Source Address When this bit is set the MAC Address1[47:0] is used to compare with the SA fields of the received packet. When this bit is reset the MAC Address1[47:0] is used to compare with the DA fields of the received packet. 0x0: Compare with.." "Compare with Destination Address,Compare with Source Address" newline hexmask.long.byte 0x90 24.--29. 1. "MBC,Mask Byte Control These bits are mask control bits for comparing each of the MAC Address bytes. When set high the MAC does not compare the corresponding byte of received DA or SA with the contents of MAC Address1 registers. Each bit controls the.." newline rbitfld.long 0x90 21.--23. "RESERVED_23_Y,Reserved." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x90 16.--20. 1. "DCS,DMA Channel Select If the PDC bit of MAC_Ext_Configuration register is not set: This field contains the binary representation of the DMA Channel number to which an Rx packet whose DA matches the MAC Address(#i) content is routed. If the PDC bit of.." newline hexmask.long.word 0x90 0.--15. 1. "ADDRHI,MAC Address1 [47:32] This field contains the upper 16 bits[47:32] of the second 6-byte MAC address." line.long 0x94 "MAC_ADDRESS18_LOW,The MAC Address1 Low register holds the lower 32 bits of the second 6-byte MAC address of the station." hexmask.long 0x94 0.--31. 1. "ADDRLO,MAC Address1 [31:0] This field contains the lower 32 bits of second 6-byte MAC address. The content of this field is undefined until loaded by the application after the initialization process." line.long 0x98 "MAC_ADDRESS19_HIGH,The MAC Address1 High register holds the upper 16 bits of the second 6-byte MAC address of the station. If the MAC address registers are configured to be double-synchronized to the (G)MII clock domains. the synchronization is triggered.." bitfld.long 0x98 31. "AE,Address Enable When this bit is set the address filter module uses the second MAC address for perfect filtering. When this bit is reset the address filter module ignores the address for filtering. 0x0: Address is ignored 0x1: Address is enabled" "Address is ignored,Address is enabled" newline bitfld.long 0x98 30. "SA,Source Address When this bit is set the MAC Address1[47:0] is used to compare with the SA fields of the received packet. When this bit is reset the MAC Address1[47:0] is used to compare with the DA fields of the received packet. 0x0: Compare with.." "Compare with Destination Address,Compare with Source Address" newline hexmask.long.byte 0x98 24.--29. 1. "MBC,Mask Byte Control These bits are mask control bits for comparing each of the MAC Address bytes. When set high the MAC does not compare the corresponding byte of received DA or SA with the contents of MAC Address1 registers. Each bit controls the.." newline rbitfld.long 0x98 21.--23. "RESERVED_23_Y,Reserved." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x98 16.--20. 1. "DCS,DMA Channel Select If the PDC bit of MAC_Ext_Configuration register is not set: This field contains the binary representation of the DMA Channel number to which an Rx packet whose DA matches the MAC Address(#i) content is routed. If the PDC bit of.." newline hexmask.long.word 0x98 0.--15. 1. "ADDRHI,MAC Address1 [47:32] This field contains the upper 16 bits[47:32] of the second 6-byte MAC address." line.long 0x9C "MAC_ADDRESS19_LOW,The MAC Address1 Low register holds the lower 32 bits of the second 6-byte MAC address of the station." hexmask.long 0x9C 0.--31. 1. "ADDRLO,MAC Address1 [31:0] This field contains the lower 32 bits of second 6-byte MAC address. The content of this field is undefined until loaded by the application after the initialization process." line.long 0xA0 "MAC_ADDRESS20_HIGH,The MAC Address1 High register holds the upper 16 bits of the second 6-byte MAC address of the station. If the MAC address registers are configured to be double-synchronized to the (G)MII clock domains. the synchronization is triggered.." bitfld.long 0xA0 31. "AE,Address Enable When this bit is set the address filter module uses the second MAC address for perfect filtering. When this bit is reset the address filter module ignores the address for filtering. 0x0: Address is ignored 0x1: Address is enabled" "Address is ignored,Address is enabled" newline bitfld.long 0xA0 30. "SA,Source Address When this bit is set the MAC Address1[47:0] is used to compare with the SA fields of the received packet. When this bit is reset the MAC Address1[47:0] is used to compare with the DA fields of the received packet. 0x0: Compare with.." "Compare with Destination Address,Compare with Source Address" newline hexmask.long.byte 0xA0 24.--29. 1. "MBC,Mask Byte Control These bits are mask control bits for comparing each of the MAC Address bytes. When set high the MAC does not compare the corresponding byte of received DA or SA with the contents of MAC Address1 registers. Each bit controls the.." newline rbitfld.long 0xA0 21.--23. "RESERVED_23_Y,Reserved." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0xA0 16.--20. 1. "DCS,DMA Channel Select If the PDC bit of MAC_Ext_Configuration register is not set: This field contains the binary representation of the DMA Channel number to which an Rx packet whose DA matches the MAC Address(#i) content is routed. If the PDC bit of.." newline hexmask.long.word 0xA0 0.--15. 1. "ADDRHI,MAC Address1 [47:32] This field contains the upper 16 bits[47:32] of the second 6-byte MAC address." line.long 0xA4 "MAC_ADDRESS20_LOW,The MAC Address1 Low register holds the lower 32 bits of the second 6-byte MAC address of the station." hexmask.long 0xA4 0.--31. 1. "ADDRLO,MAC Address1 [31:0] This field contains the lower 32 bits of second 6-byte MAC address. The content of this field is undefined until loaded by the application after the initialization process." line.long 0xA8 "MAC_ADDRESS21_HIGH,The MAC Address1 High register holds the upper 16 bits of the second 6-byte MAC address of the station. If the MAC address registers are configured to be double-synchronized to the (G)MII clock domains. the synchronization is triggered.." bitfld.long 0xA8 31. "AE,Address Enable When this bit is set the address filter module uses the second MAC address for perfect filtering. When this bit is reset the address filter module ignores the address for filtering. 0x0: Address is ignored 0x1: Address is enabled" "Address is ignored,Address is enabled" newline bitfld.long 0xA8 30. "SA,Source Address When this bit is set the MAC Address1[47:0] is used to compare with the SA fields of the received packet. When this bit is reset the MAC Address1[47:0] is used to compare with the DA fields of the received packet. 0x0: Compare with.." "Compare with Destination Address,Compare with Source Address" newline hexmask.long.byte 0xA8 24.--29. 1. "MBC,Mask Byte Control These bits are mask control bits for comparing each of the MAC Address bytes. When set high the MAC does not compare the corresponding byte of received DA or SA with the contents of MAC Address1 registers. Each bit controls the.." newline rbitfld.long 0xA8 21.--23. "RESERVED_23_Y,Reserved." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0xA8 16.--20. 1. "DCS,DMA Channel Select If the PDC bit of MAC_Ext_Configuration register is not set: This field contains the binary representation of the DMA Channel number to which an Rx packet whose DA matches the MAC Address(#i) content is routed. If the PDC bit of.." newline hexmask.long.word 0xA8 0.--15. 1. "ADDRHI,MAC Address1 [47:32] This field contains the upper 16 bits[47:32] of the second 6-byte MAC address." line.long 0xAC "MAC_ADDRESS21_LOW,The MAC Address1 Low register holds the lower 32 bits of the second 6-byte MAC address of the station." hexmask.long 0xAC 0.--31. 1. "ADDRLO,MAC Address1 [31:0] This field contains the lower 32 bits of second 6-byte MAC address. The content of this field is undefined until loaded by the application after the initialization process." line.long 0xB0 "MAC_ADDRESS22_HIGH,The MAC Address1 High register holds the upper 16 bits of the second 6-byte MAC address of the station. If the MAC address registers are configured to be double-synchronized to the (G)MII clock domains. the synchronization is triggered.." bitfld.long 0xB0 31. "AE,Address Enable When this bit is set the address filter module uses the second MAC address for perfect filtering. When this bit is reset the address filter module ignores the address for filtering. 0x0: Address is ignored 0x1: Address is enabled" "Address is ignored,Address is enabled" newline bitfld.long 0xB0 30. "SA,Source Address When this bit is set the MAC Address1[47:0] is used to compare with the SA fields of the received packet. When this bit is reset the MAC Address1[47:0] is used to compare with the DA fields of the received packet. 0x0: Compare with.." "Compare with Destination Address,Compare with Source Address" newline hexmask.long.byte 0xB0 24.--29. 1. "MBC,Mask Byte Control These bits are mask control bits for comparing each of the MAC Address bytes. When set high the MAC does not compare the corresponding byte of received DA or SA with the contents of MAC Address1 registers. Each bit controls the.." newline rbitfld.long 0xB0 21.--23. "RESERVED_23_Y,Reserved." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0xB0 16.--20. 1. "DCS,DMA Channel Select If the PDC bit of MAC_Ext_Configuration register is not set: This field contains the binary representation of the DMA Channel number to which an Rx packet whose DA matches the MAC Address(#i) content is routed. If the PDC bit of.." newline hexmask.long.word 0xB0 0.--15. 1. "ADDRHI,MAC Address1 [47:32] This field contains the upper 16 bits[47:32] of the second 6-byte MAC address." line.long 0xB4 "MAC_ADDRESS22_LOW,The MAC Address1 Low register holds the lower 32 bits of the second 6-byte MAC address of the station." hexmask.long 0xB4 0.--31. 1. "ADDRLO,MAC Address1 [31:0] This field contains the lower 32 bits of second 6-byte MAC address. The content of this field is undefined until loaded by the application after the initialization process." line.long 0xB8 "MAC_ADDRESS23_HIGH,The MAC Address1 High register holds the upper 16 bits of the second 6-byte MAC address of the station. If the MAC address registers are configured to be double-synchronized to the (G)MII clock domains. the synchronization is triggered.." bitfld.long 0xB8 31. "AE,Address Enable When this bit is set the address filter module uses the second MAC address for perfect filtering. When this bit is reset the address filter module ignores the address for filtering. 0x0: Address is ignored 0x1: Address is enabled" "Address is ignored,Address is enabled" newline bitfld.long 0xB8 30. "SA,Source Address When this bit is set the MAC Address1[47:0] is used to compare with the SA fields of the received packet. When this bit is reset the MAC Address1[47:0] is used to compare with the DA fields of the received packet. 0x0: Compare with.." "Compare with Destination Address,Compare with Source Address" newline hexmask.long.byte 0xB8 24.--29. 1. "MBC,Mask Byte Control These bits are mask control bits for comparing each of the MAC Address bytes. When set high the MAC does not compare the corresponding byte of received DA or SA with the contents of MAC Address1 registers. Each bit controls the.." newline rbitfld.long 0xB8 21.--23. "RESERVED_23_Y,Reserved." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0xB8 16.--20. 1. "DCS,DMA Channel Select If the PDC bit of MAC_Ext_Configuration register is not set: This field contains the binary representation of the DMA Channel number to which an Rx packet whose DA matches the MAC Address(#i) content is routed. If the PDC bit of.." newline hexmask.long.word 0xB8 0.--15. 1. "ADDRHI,MAC Address1 [47:32] This field contains the upper 16 bits[47:32] of the second 6-byte MAC address." line.long 0xBC "MAC_ADDRESS23_LOW,The MAC Address1 Low register holds the lower 32 bits of the second 6-byte MAC address of the station." hexmask.long 0xBC 0.--31. 1. "ADDRLO,MAC Address1 [31:0] This field contains the lower 32 bits of second 6-byte MAC address. The content of this field is undefined until loaded by the application after the initialization process." line.long 0xC0 "MAC_ADDRESS24_HIGH,The MAC Address1 High register holds the upper 16 bits of the second 6-byte MAC address of the station. If the MAC address registers are configured to be double-synchronized to the (G)MII clock domains. the synchronization is triggered.." bitfld.long 0xC0 31. "AE,Address Enable When this bit is set the address filter module uses the second MAC address for perfect filtering. When this bit is reset the address filter module ignores the address for filtering. 0x0: Address is ignored 0x1: Address is enabled" "Address is ignored,Address is enabled" newline bitfld.long 0xC0 30. "SA,Source Address When this bit is set the MAC Address1[47:0] is used to compare with the SA fields of the received packet. When this bit is reset the MAC Address1[47:0] is used to compare with the DA fields of the received packet. 0x0: Compare with.." "Compare with Destination Address,Compare with Source Address" newline hexmask.long.byte 0xC0 24.--29. 1. "MBC,Mask Byte Control These bits are mask control bits for comparing each of the MAC Address bytes. When set high the MAC does not compare the corresponding byte of received DA or SA with the contents of MAC Address1 registers. Each bit controls the.." newline rbitfld.long 0xC0 21.--23. "RESERVED_23_Y,Reserved." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0xC0 16.--20. 1. "DCS,DMA Channel Select If the PDC bit of MAC_Ext_Configuration register is not set: This field contains the binary representation of the DMA Channel number to which an Rx packet whose DA matches the MAC Address(#i) content is routed. If the PDC bit of.." newline hexmask.long.word 0xC0 0.--15. 1. "ADDRHI,MAC Address1 [47:32] This field contains the upper 16 bits[47:32] of the second 6-byte MAC address." line.long 0xC4 "MAC_ADDRESS24_LOW,The MAC Address1 Low register holds the lower 32 bits of the second 6-byte MAC address of the station." hexmask.long 0xC4 0.--31. 1. "ADDRLO,MAC Address1 [31:0] This field contains the lower 32 bits of second 6-byte MAC address. The content of this field is undefined until loaded by the application after the initialization process." line.long 0xC8 "MAC_ADDRESS25_HIGH,The MAC Address1 High register holds the upper 16 bits of the second 6-byte MAC address of the station. If the MAC address registers are configured to be double-synchronized to the (G)MII clock domains. the synchronization is triggered.." bitfld.long 0xC8 31. "AE,Address Enable When this bit is set the address filter module uses the second MAC address for perfect filtering. When this bit is reset the address filter module ignores the address for filtering. 0x0: Address is ignored 0x1: Address is enabled" "Address is ignored,Address is enabled" newline bitfld.long 0xC8 30. "SA,Source Address When this bit is set the MAC Address1[47:0] is used to compare with the SA fields of the received packet. When this bit is reset the MAC Address1[47:0] is used to compare with the DA fields of the received packet. 0x0: Compare with.." "Compare with Destination Address,Compare with Source Address" newline hexmask.long.byte 0xC8 24.--29. 1. "MBC,Mask Byte Control These bits are mask control bits for comparing each of the MAC Address bytes. When set high the MAC does not compare the corresponding byte of received DA or SA with the contents of MAC Address1 registers. Each bit controls the.." newline rbitfld.long 0xC8 21.--23. "RESERVED_23_Y,Reserved." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0xC8 16.--20. 1. "DCS,DMA Channel Select If the PDC bit of MAC_Ext_Configuration register is not set: This field contains the binary representation of the DMA Channel number to which an Rx packet whose DA matches the MAC Address(#i) content is routed. If the PDC bit of.." newline hexmask.long.word 0xC8 0.--15. 1. "ADDRHI,MAC Address1 [47:32] This field contains the upper 16 bits[47:32] of the second 6-byte MAC address." line.long 0xCC "MAC_ADDRESS25_LOW,The MAC Address1 Low register holds the lower 32 bits of the second 6-byte MAC address of the station." hexmask.long 0xCC 0.--31. 1. "ADDRLO,MAC Address1 [31:0] This field contains the lower 32 bits of second 6-byte MAC address. The content of this field is undefined until loaded by the application after the initialization process." line.long 0xD0 "MAC_ADDRESS26_HIGH,The MAC Address1 High register holds the upper 16 bits of the second 6-byte MAC address of the station. If the MAC address registers are configured to be double-synchronized to the (G)MII clock domains. the synchronization is triggered.." bitfld.long 0xD0 31. "AE,Address Enable When this bit is set the address filter module uses the second MAC address for perfect filtering. When this bit is reset the address filter module ignores the address for filtering. 0x0: Address is ignored 0x1: Address is enabled" "Address is ignored,Address is enabled" newline bitfld.long 0xD0 30. "SA,Source Address When this bit is set the MAC Address1[47:0] is used to compare with the SA fields of the received packet. When this bit is reset the MAC Address1[47:0] is used to compare with the DA fields of the received packet. 0x0: Compare with.." "Compare with Destination Address,Compare with Source Address" newline hexmask.long.byte 0xD0 24.--29. 1. "MBC,Mask Byte Control These bits are mask control bits for comparing each of the MAC Address bytes. When set high the MAC does not compare the corresponding byte of received DA or SA with the contents of MAC Address1 registers. Each bit controls the.." newline rbitfld.long 0xD0 21.--23. "RESERVED_23_Y,Reserved." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0xD0 16.--20. 1. "DCS,DMA Channel Select If the PDC bit of MAC_Ext_Configuration register is not set: This field contains the binary representation of the DMA Channel number to which an Rx packet whose DA matches the MAC Address(#i) content is routed. If the PDC bit of.." newline hexmask.long.word 0xD0 0.--15. 1. "ADDRHI,MAC Address1 [47:32] This field contains the upper 16 bits[47:32] of the second 6-byte MAC address." line.long 0xD4 "MAC_ADDRESS26_LOW,The MAC Address1 Low register holds the lower 32 bits of the second 6-byte MAC address of the station." hexmask.long 0xD4 0.--31. 1. "ADDRLO,MAC Address1 [31:0] This field contains the lower 32 bits of second 6-byte MAC address. The content of this field is undefined until loaded by the application after the initialization process." line.long 0xD8 "MAC_ADDRESS27_HIGH,The MAC Address1 High register holds the upper 16 bits of the second 6-byte MAC address of the station. If the MAC address registers are configured to be double-synchronized to the (G)MII clock domains. the synchronization is triggered.." bitfld.long 0xD8 31. "AE,Address Enable When this bit is set the address filter module uses the second MAC address for perfect filtering. When this bit is reset the address filter module ignores the address for filtering. 0x0: Address is ignored 0x1: Address is enabled" "Address is ignored,Address is enabled" newline bitfld.long 0xD8 30. "SA,Source Address When this bit is set the MAC Address1[47:0] is used to compare with the SA fields of the received packet. When this bit is reset the MAC Address1[47:0] is used to compare with the DA fields of the received packet. 0x0: Compare with.." "Compare with Destination Address,Compare with Source Address" newline hexmask.long.byte 0xD8 24.--29. 1. "MBC,Mask Byte Control These bits are mask control bits for comparing each of the MAC Address bytes. When set high the MAC does not compare the corresponding byte of received DA or SA with the contents of MAC Address1 registers. Each bit controls the.." newline rbitfld.long 0xD8 21.--23. "RESERVED_23_Y,Reserved." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0xD8 16.--20. 1. "DCS,DMA Channel Select If the PDC bit of MAC_Ext_Configuration register is not set: This field contains the binary representation of the DMA Channel number to which an Rx packet whose DA matches the MAC Address(#i) content is routed. If the PDC bit of.." newline hexmask.long.word 0xD8 0.--15. 1. "ADDRHI,MAC Address1 [47:32] This field contains the upper 16 bits[47:32] of the second 6-byte MAC address." line.long 0xDC "MAC_ADDRESS27_LOW,The MAC Address1 Low register holds the lower 32 bits of the second 6-byte MAC address of the station." hexmask.long 0xDC 0.--31. 1. "ADDRLO,MAC Address1 [31:0] This field contains the lower 32 bits of second 6-byte MAC address. The content of this field is undefined until loaded by the application after the initialization process." line.long 0xE0 "MAC_ADDRESS28_HIGH,The MAC Address1 High register holds the upper 16 bits of the second 6-byte MAC address of the station. If the MAC address registers are configured to be double-synchronized to the (G)MII clock domains. the synchronization is triggered.." bitfld.long 0xE0 31. "AE,Address Enable When this bit is set the address filter module uses the second MAC address for perfect filtering. When this bit is reset the address filter module ignores the address for filtering. 0x0: Address is ignored 0x1: Address is enabled" "Address is ignored,Address is enabled" newline bitfld.long 0xE0 30. "SA,Source Address When this bit is set the MAC Address1[47:0] is used to compare with the SA fields of the received packet. When this bit is reset the MAC Address1[47:0] is used to compare with the DA fields of the received packet. 0x0: Compare with.." "Compare with Destination Address,Compare with Source Address" newline hexmask.long.byte 0xE0 24.--29. 1. "MBC,Mask Byte Control These bits are mask control bits for comparing each of the MAC Address bytes. When set high the MAC does not compare the corresponding byte of received DA or SA with the contents of MAC Address1 registers. Each bit controls the.." newline rbitfld.long 0xE0 21.--23. "RESERVED_23_Y,Reserved." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0xE0 16.--20. 1. "DCS,DMA Channel Select If the PDC bit of MAC_Ext_Configuration register is not set: This field contains the binary representation of the DMA Channel number to which an Rx packet whose DA matches the MAC Address(#i) content is routed. If the PDC bit of.." newline hexmask.long.word 0xE0 0.--15. 1. "ADDRHI,MAC Address1 [47:32] This field contains the upper 16 bits[47:32] of the second 6-byte MAC address." line.long 0xE4 "MAC_ADDRESS28_LOW,The MAC Address1 Low register holds the lower 32 bits of the second 6-byte MAC address of the station." hexmask.long 0xE4 0.--31. 1. "ADDRLO,MAC Address1 [31:0] This field contains the lower 32 bits of second 6-byte MAC address. The content of this field is undefined until loaded by the application after the initialization process." line.long 0xE8 "MAC_ADDRESS29_HIGH,The MAC Address1 High register holds the upper 16 bits of the second 6-byte MAC address of the station. If the MAC address registers are configured to be double-synchronized to the (G)MII clock domains. the synchronization is triggered.." bitfld.long 0xE8 31. "AE,Address Enable When this bit is set the address filter module uses the second MAC address for perfect filtering. When this bit is reset the address filter module ignores the address for filtering. 0x0: Address is ignored 0x1: Address is enabled" "Address is ignored,Address is enabled" newline bitfld.long 0xE8 30. "SA,Source Address When this bit is set the MAC Address1[47:0] is used to compare with the SA fields of the received packet. When this bit is reset the MAC Address1[47:0] is used to compare with the DA fields of the received packet. 0x0: Compare with.." "Compare with Destination Address,Compare with Source Address" newline hexmask.long.byte 0xE8 24.--29. 1. "MBC,Mask Byte Control These bits are mask control bits for comparing each of the MAC Address bytes. When set high the MAC does not compare the corresponding byte of received DA or SA with the contents of MAC Address1 registers. Each bit controls the.." newline rbitfld.long 0xE8 21.--23. "RESERVED_23_Y,Reserved." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0xE8 16.--20. 1. "DCS,DMA Channel Select If the PDC bit of MAC_Ext_Configuration register is not set: This field contains the binary representation of the DMA Channel number to which an Rx packet whose DA matches the MAC Address(#i) content is routed. If the PDC bit of.." newline hexmask.long.word 0xE8 0.--15. 1. "ADDRHI,MAC Address1 [47:32] This field contains the upper 16 bits[47:32] of the second 6-byte MAC address." line.long 0xEC "MAC_ADDRESS29_LOW,The MAC Address1 Low register holds the lower 32 bits of the second 6-byte MAC address of the station." hexmask.long 0xEC 0.--31. 1. "ADDRLO,MAC Address1 [31:0] This field contains the lower 32 bits of second 6-byte MAC address. The content of this field is undefined until loaded by the application after the initialization process." line.long 0xF0 "MAC_ADDRESS30_HIGH,The MAC Address1 High register holds the upper 16 bits of the second 6-byte MAC address of the station. If the MAC address registers are configured to be double-synchronized to the (G)MII clock domains. the synchronization is triggered.." bitfld.long 0xF0 31. "AE,Address Enable When this bit is set the address filter module uses the second MAC address for perfect filtering. When this bit is reset the address filter module ignores the address for filtering. 0x0: Address is ignored 0x1: Address is enabled" "Address is ignored,Address is enabled" newline bitfld.long 0xF0 30. "SA,Source Address When this bit is set the MAC Address1[47:0] is used to compare with the SA fields of the received packet. When this bit is reset the MAC Address1[47:0] is used to compare with the DA fields of the received packet. 0x0: Compare with.." "Compare with Destination Address,Compare with Source Address" newline hexmask.long.byte 0xF0 24.--29. 1. "MBC,Mask Byte Control These bits are mask control bits for comparing each of the MAC Address bytes. When set high the MAC does not compare the corresponding byte of received DA or SA with the contents of MAC Address1 registers. Each bit controls the.." newline rbitfld.long 0xF0 21.--23. "RESERVED_23_Y,Reserved." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0xF0 16.--20. 1. "DCS,DMA Channel Select If the PDC bit of MAC_Ext_Configuration register is not set: This field contains the binary representation of the DMA Channel number to which an Rx packet whose DA matches the MAC Address(#i) content is routed. If the PDC bit of.." newline hexmask.long.word 0xF0 0.--15. 1. "ADDRHI,MAC Address1 [47:32] This field contains the upper 16 bits[47:32] of the second 6-byte MAC address." line.long 0xF4 "MAC_ADDRESS30_LOW,The MAC Address1 Low register holds the lower 32 bits of the second 6-byte MAC address of the station." hexmask.long 0xF4 0.--31. 1. "ADDRLO,MAC Address1 [31:0] This field contains the lower 32 bits of second 6-byte MAC address. The content of this field is undefined until loaded by the application after the initialization process." line.long 0xF8 "MAC_ADDRESS31_HIGH,The MAC Address1 High register holds the upper 16 bits of the second 6-byte MAC address of the station. If the MAC address registers are configured to be double-synchronized to the (G)MII clock domains. the synchronization is triggered.." bitfld.long 0xF8 31. "AE,Address Enable When this bit is set the address filter module uses the second MAC address for perfect filtering. When this bit is reset the address filter module ignores the address for filtering. 0x0: Address is ignored 0x1: Address is enabled" "Address is ignored,Address is enabled" newline bitfld.long 0xF8 30. "SA,Source Address When this bit is set the MAC Address1[47:0] is used to compare with the SA fields of the received packet. When this bit is reset the MAC Address1[47:0] is used to compare with the DA fields of the received packet. 0x0: Compare with.." "Compare with Destination Address,Compare with Source Address" newline hexmask.long.byte 0xF8 24.--29. 1. "MBC,Mask Byte Control These bits are mask control bits for comparing each of the MAC Address bytes. When set high the MAC does not compare the corresponding byte of received DA or SA with the contents of MAC Address1 registers. Each bit controls the.." newline rbitfld.long 0xF8 21.--23. "RESERVED_23_Y,Reserved." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0xF8 16.--20. 1. "DCS,DMA Channel Select If the PDC bit of MAC_Ext_Configuration register is not set: This field contains the binary representation of the DMA Channel number to which an Rx packet whose DA matches the MAC Address(#i) content is routed. If the PDC bit of.." newline hexmask.long.word 0xF8 0.--15. 1. "ADDRHI,MAC Address1 [47:32] This field contains the upper 16 bits[47:32] of the second 6-byte MAC address." line.long 0xFC "MAC_ADDRESS31_LOW,The MAC Address1 Low register holds the lower 32 bits of the second 6-byte MAC address of the station." hexmask.long 0xFC 0.--31. 1. "ADDRLO,MAC Address1 [31:0] This field contains the lower 32 bits of second 6-byte MAC address. The content of this field is undefined until loaded by the application after the initialization process." line.long 0x100 "MAC_ADDRESS32_HIGH,The MAC Address32 High register holds the upper 16 bits of the 33rd 6-byte MAC address of the station. If the MAC address registers are configured to be double-synchronized to the (G)MII clock domains. the synchronization is triggered.." bitfld.long 0x100 31. "AE,Address Enable When this bit is set the Address filter module uses the 33rd MAC address for perfect filtering. When this bit is reset the address filter module ignores the address for filtering. 0x0: Address is ignored 0x1: Address is enabled" "Address is ignored,Address is enabled" newline hexmask.long.word 0x100 19.--30. 1. "RESERVED_30_Y,Reserved." newline bitfld.long 0x100 16.--18. "DCS,DMA Channel Select This field contains the DMA Channel number to which an Rx packet whose DA matches the MAC Address32 content is routed." "0,1,2,3,4,5,6,7" newline hexmask.long.word 0x100 0.--15. 1. "ADDRHI,MAC Address32 [47:32] This field contains the upper 16 bits (47:32) of the 33rd 6-byte MAC address." line.long 0x104 "MAC_ADDRESS32_LOW,The MAC Address32 Low register holds the lower 16 bits of the 33rd 6-byte MAC address of the station." hexmask.long 0x104 0.--31. 1. "ADDRLO,MAC Address32 [31:0] This field contains the lower 32 bits of the 33rd 6-byte MAC address. The content of this field is undefined until loaded by the Application after the initialization process." line.long 0x108 "MAC_ADDRESS33_HIGH,The MAC Address32 High register holds the upper 16 bits of the 33rd 6-byte MAC address of the station. If the MAC address registers are configured to be double-synchronized to the (G)MII clock domains. the synchronization is triggered.." bitfld.long 0x108 31. "AE,Address Enable When this bit is set the Address filter module uses the 33rd MAC address for perfect filtering. When this bit is reset the address filter module ignores the address for filtering. 0x0: Address is ignored 0x1: Address is enabled" "Address is ignored,Address is enabled" newline hexmask.long.word 0x108 19.--30. 1. "RESERVED_30_Y,Reserved." newline bitfld.long 0x108 16.--18. "DCS,DMA Channel Select This field contains the DMA Channel number to which an Rx packet whose DA matches the MAC Address32 content is routed." "0,1,2,3,4,5,6,7" newline hexmask.long.word 0x108 0.--15. 1. "ADDRHI,MAC Address32 [47:32] This field contains the upper 16 bits (47:32) of the 33rd 6-byte MAC address." line.long 0x10C "MAC_ADDRESS33_LOW,The MAC Address32 Low register holds the lower 16 bits of the 33rd 6-byte MAC address of the station." hexmask.long 0x10C 0.--31. 1. "ADDRLO,MAC Address32 [31:0] This field contains the lower 32 bits of the 33rd 6-byte MAC address. The content of this field is undefined until loaded by the Application after the initialization process." line.long 0x110 "MAC_ADDRESS34_HIGH,The MAC Address32 High register holds the upper 16 bits of the 33rd 6-byte MAC address of the station. If the MAC address registers are configured to be double-synchronized to the (G)MII clock domains. the synchronization is triggered.." bitfld.long 0x110 31. "AE,Address Enable When this bit is set the Address filter module uses the 33rd MAC address for perfect filtering. When this bit is reset the address filter module ignores the address for filtering. 0x0: Address is ignored 0x1: Address is enabled" "Address is ignored,Address is enabled" newline hexmask.long.word 0x110 19.--30. 1. "RESERVED_30_Y,Reserved." newline bitfld.long 0x110 16.--18. "DCS,DMA Channel Select This field contains the DMA Channel number to which an Rx packet whose DA matches the MAC Address32 content is routed." "0,1,2,3,4,5,6,7" newline hexmask.long.word 0x110 0.--15. 1. "ADDRHI,MAC Address32 [47:32] This field contains the upper 16 bits (47:32) of the 33rd 6-byte MAC address." line.long 0x114 "MAC_ADDRESS34_LOW,The MAC Address32 Low register holds the lower 16 bits of the 33rd 6-byte MAC address of the station." hexmask.long 0x114 0.--31. 1. "ADDRLO,MAC Address32 [31:0] This field contains the lower 32 bits of the 33rd 6-byte MAC address. The content of this field is undefined until loaded by the Application after the initialization process." line.long 0x118 "MAC_ADDRESS35_HIGH,The MAC Address32 High register holds the upper 16 bits of the 33rd 6-byte MAC address of the station. If the MAC address registers are configured to be double-synchronized to the (G)MII clock domains. the synchronization is triggered.." bitfld.long 0x118 31. "AE,Address Enable When this bit is set the Address filter module uses the 33rd MAC address for perfect filtering. When this bit is reset the address filter module ignores the address for filtering. 0x0: Address is ignored 0x1: Address is enabled" "Address is ignored,Address is enabled" newline hexmask.long.word 0x118 19.--30. 1. "RESERVED_30_Y,Reserved." newline bitfld.long 0x118 16.--18. "DCS,DMA Channel Select This field contains the DMA Channel number to which an Rx packet whose DA matches the MAC Address32 content is routed." "0,1,2,3,4,5,6,7" newline hexmask.long.word 0x118 0.--15. 1. "ADDRHI,MAC Address32 [47:32] This field contains the upper 16 bits (47:32) of the 33rd 6-byte MAC address." line.long 0x11C "MAC_ADDRESS35_LOW,The MAC Address32 Low register holds the lower 16 bits of the 33rd 6-byte MAC address of the station." hexmask.long 0x11C 0.--31. 1. "ADDRLO,MAC Address32 [31:0] This field contains the lower 32 bits of the 33rd 6-byte MAC address. The content of this field is undefined until loaded by the Application after the initialization process." line.long 0x120 "MAC_ADDRESS36_HIGH,The MAC Address32 High register holds the upper 16 bits of the 33rd 6-byte MAC address of the station. If the MAC address registers are configured to be double-synchronized to the (G)MII clock domains. the synchronization is triggered.." bitfld.long 0x120 31. "AE,Address Enable When this bit is set the Address filter module uses the 33rd MAC address for perfect filtering. When this bit is reset the address filter module ignores the address for filtering. 0x0: Address is ignored 0x1: Address is enabled" "Address is ignored,Address is enabled" newline hexmask.long.word 0x120 19.--30. 1. "RESERVED_30_Y,Reserved." newline bitfld.long 0x120 16.--18. "DCS,DMA Channel Select This field contains the DMA Channel number to which an Rx packet whose DA matches the MAC Address32 content is routed." "0,1,2,3,4,5,6,7" newline hexmask.long.word 0x120 0.--15. 1. "ADDRHI,MAC Address32 [47:32] This field contains the upper 16 bits (47:32) of the 33rd 6-byte MAC address." line.long 0x124 "MAC_ADDRESS36_LOW,The MAC Address32 Low register holds the lower 16 bits of the 33rd 6-byte MAC address of the station." hexmask.long 0x124 0.--31. 1. "ADDRLO,MAC Address32 [31:0] This field contains the lower 32 bits of the 33rd 6-byte MAC address. The content of this field is undefined until loaded by the Application after the initialization process." line.long 0x128 "MAC_ADDRESS37_HIGH,The MAC Address32 High register holds the upper 16 bits of the 33rd 6-byte MAC address of the station. If the MAC address registers are configured to be double-synchronized to the (G)MII clock domains. the synchronization is triggered.." bitfld.long 0x128 31. "AE,Address Enable When this bit is set the Address filter module uses the 33rd MAC address for perfect filtering. When this bit is reset the address filter module ignores the address for filtering. 0x0: Address is ignored 0x1: Address is enabled" "Address is ignored,Address is enabled" newline hexmask.long.word 0x128 19.--30. 1. "RESERVED_30_Y,Reserved." newline bitfld.long 0x128 16.--18. "DCS,DMA Channel Select This field contains the DMA Channel number to which an Rx packet whose DA matches the MAC Address32 content is routed." "0,1,2,3,4,5,6,7" newline hexmask.long.word 0x128 0.--15. 1. "ADDRHI,MAC Address32 [47:32] This field contains the upper 16 bits (47:32) of the 33rd 6-byte MAC address." line.long 0x12C "MAC_ADDRESS37_LOW,The MAC Address32 Low register holds the lower 16 bits of the 33rd 6-byte MAC address of the station." hexmask.long 0x12C 0.--31. 1. "ADDRLO,MAC Address32 [31:0] This field contains the lower 32 bits of the 33rd 6-byte MAC address. The content of this field is undefined until loaded by the Application after the initialization process." line.long 0x130 "MAC_ADDRESS38_HIGH,The MAC Address32 High register holds the upper 16 bits of the 33rd 6-byte MAC address of the station. If the MAC address registers are configured to be double-synchronized to the (G)MII clock domains. the synchronization is triggered.." bitfld.long 0x130 31. "AE,Address Enable When this bit is set the Address filter module uses the 33rd MAC address for perfect filtering. When this bit is reset the address filter module ignores the address for filtering. 0x0: Address is ignored 0x1: Address is enabled" "Address is ignored,Address is enabled" newline hexmask.long.word 0x130 19.--30. 1. "RESERVED_30_Y,Reserved." newline bitfld.long 0x130 16.--18. "DCS,DMA Channel Select This field contains the DMA Channel number to which an Rx packet whose DA matches the MAC Address32 content is routed." "0,1,2,3,4,5,6,7" newline hexmask.long.word 0x130 0.--15. 1. "ADDRHI,MAC Address32 [47:32] This field contains the upper 16 bits (47:32) of the 33rd 6-byte MAC address." line.long 0x134 "MAC_ADDRESS38_LOW,The MAC Address32 Low register holds the lower 16 bits of the 33rd 6-byte MAC address of the station." hexmask.long 0x134 0.--31. 1. "ADDRLO,MAC Address32 [31:0] This field contains the lower 32 bits of the 33rd 6-byte MAC address. The content of this field is undefined until loaded by the Application after the initialization process." line.long 0x138 "MAC_ADDRESS39_HIGH,The MAC Address32 High register holds the upper 16 bits of the 33rd 6-byte MAC address of the station. If the MAC address registers are configured to be double-synchronized to the (G)MII clock domains. the synchronization is triggered.." bitfld.long 0x138 31. "AE,Address Enable When this bit is set the Address filter module uses the 33rd MAC address for perfect filtering. When this bit is reset the address filter module ignores the address for filtering. 0x0: Address is ignored 0x1: Address is enabled" "Address is ignored,Address is enabled" newline hexmask.long.word 0x138 19.--30. 1. "RESERVED_30_Y,Reserved." newline bitfld.long 0x138 16.--18. "DCS,DMA Channel Select This field contains the DMA Channel number to which an Rx packet whose DA matches the MAC Address32 content is routed." "0,1,2,3,4,5,6,7" newline hexmask.long.word 0x138 0.--15. 1. "ADDRHI,MAC Address32 [47:32] This field contains the upper 16 bits (47:32) of the 33rd 6-byte MAC address." line.long 0x13C "MAC_ADDRESS39_LOW,The MAC Address32 Low register holds the lower 16 bits of the 33rd 6-byte MAC address of the station." hexmask.long 0x13C 0.--31. 1. "ADDRLO,MAC Address32 [31:0] This field contains the lower 32 bits of the 33rd 6-byte MAC address. The content of this field is undefined until loaded by the Application after the initialization process." line.long 0x140 "MAC_ADDRESS40_HIGH,The MAC Address32 High register holds the upper 16 bits of the 33rd 6-byte MAC address of the station. If the MAC address registers are configured to be double-synchronized to the (G)MII clock domains. the synchronization is triggered.." bitfld.long 0x140 31. "AE,Address Enable When this bit is set the Address filter module uses the 33rd MAC address for perfect filtering. When this bit is reset the address filter module ignores the address for filtering. 0x0: Address is ignored 0x1: Address is enabled" "Address is ignored,Address is enabled" newline hexmask.long.word 0x140 19.--30. 1. "RESERVED_30_Y,Reserved." newline bitfld.long 0x140 16.--18. "DCS,DMA Channel Select This field contains the DMA Channel number to which an Rx packet whose DA matches the MAC Address32 content is routed." "0,1,2,3,4,5,6,7" newline hexmask.long.word 0x140 0.--15. 1. "ADDRHI,MAC Address32 [47:32] This field contains the upper 16 bits (47:32) of the 33rd 6-byte MAC address." line.long 0x144 "MAC_ADDRESS40_LOW,The MAC Address32 Low register holds the lower 16 bits of the 33rd 6-byte MAC address of the station." hexmask.long 0x144 0.--31. 1. "ADDRLO,MAC Address32 [31:0] This field contains the lower 32 bits of the 33rd 6-byte MAC address. The content of this field is undefined until loaded by the Application after the initialization process." line.long 0x148 "MAC_ADDRESS41_HIGH,The MAC Address32 High register holds the upper 16 bits of the 33rd 6-byte MAC address of the station. If the MAC address registers are configured to be double-synchronized to the (G)MII clock domains. the synchronization is triggered.." bitfld.long 0x148 31. "AE,Address Enable When this bit is set the Address filter module uses the 33rd MAC address for perfect filtering. When this bit is reset the address filter module ignores the address for filtering. 0x0: Address is ignored 0x1: Address is enabled" "Address is ignored,Address is enabled" newline hexmask.long.word 0x148 19.--30. 1. "RESERVED_30_Y,Reserved." newline bitfld.long 0x148 16.--18. "DCS,DMA Channel Select This field contains the DMA Channel number to which an Rx packet whose DA matches the MAC Address32 content is routed." "0,1,2,3,4,5,6,7" newline hexmask.long.word 0x148 0.--15. 1. "ADDRHI,MAC Address32 [47:32] This field contains the upper 16 bits (47:32) of the 33rd 6-byte MAC address." line.long 0x14C "MAC_ADDRESS41_LOW,The MAC Address32 Low register holds the lower 16 bits of the 33rd 6-byte MAC address of the station." hexmask.long 0x14C 0.--31. 1. "ADDRLO,MAC Address32 [31:0] This field contains the lower 32 bits of the 33rd 6-byte MAC address. The content of this field is undefined until loaded by the Application after the initialization process." line.long 0x150 "MAC_ADDRESS42_HIGH,The MAC Address32 High register holds the upper 16 bits of the 33rd 6-byte MAC address of the station. If the MAC address registers are configured to be double-synchronized to the (G)MII clock domains. the synchronization is triggered.." bitfld.long 0x150 31. "AE,Address Enable When this bit is set the Address filter module uses the 33rd MAC address for perfect filtering. When this bit is reset the address filter module ignores the address for filtering. 0x0: Address is ignored 0x1: Address is enabled" "Address is ignored,Address is enabled" newline hexmask.long.word 0x150 19.--30. 1. "RESERVED_30_Y,Reserved." newline bitfld.long 0x150 16.--18. "DCS,DMA Channel Select This field contains the DMA Channel number to which an Rx packet whose DA matches the MAC Address32 content is routed." "0,1,2,3,4,5,6,7" newline hexmask.long.word 0x150 0.--15. 1. "ADDRHI,MAC Address32 [47:32] This field contains the upper 16 bits (47:32) of the 33rd 6-byte MAC address." line.long 0x154 "MAC_ADDRESS42_LOW,The MAC Address32 Low register holds the lower 16 bits of the 33rd 6-byte MAC address of the station." hexmask.long 0x154 0.--31. 1. "ADDRLO,MAC Address32 [31:0] This field contains the lower 32 bits of the 33rd 6-byte MAC address. The content of this field is undefined until loaded by the Application after the initialization process." line.long 0x158 "MAC_ADDRESS43_HIGH,The MAC Address32 High register holds the upper 16 bits of the 33rd 6-byte MAC address of the station. If the MAC address registers are configured to be double-synchronized to the (G)MII clock domains. the synchronization is triggered.." bitfld.long 0x158 31. "AE,Address Enable When this bit is set the Address filter module uses the 33rd MAC address for perfect filtering. When this bit is reset the address filter module ignores the address for filtering. 0x0: Address is ignored 0x1: Address is enabled" "Address is ignored,Address is enabled" newline hexmask.long.word 0x158 19.--30. 1. "RESERVED_30_Y,Reserved." newline bitfld.long 0x158 16.--18. "DCS,DMA Channel Select This field contains the DMA Channel number to which an Rx packet whose DA matches the MAC Address32 content is routed." "0,1,2,3,4,5,6,7" newline hexmask.long.word 0x158 0.--15. 1. "ADDRHI,MAC Address32 [47:32] This field contains the upper 16 bits (47:32) of the 33rd 6-byte MAC address." line.long 0x15C "MAC_ADDRESS43_LOW,The MAC Address32 Low register holds the lower 16 bits of the 33rd 6-byte MAC address of the station." hexmask.long 0x15C 0.--31. 1. "ADDRLO,MAC Address32 [31:0] This field contains the lower 32 bits of the 33rd 6-byte MAC address. The content of this field is undefined until loaded by the Application after the initialization process." line.long 0x160 "MAC_ADDRESS44_HIGH,The MAC Address32 High register holds the upper 16 bits of the 33rd 6-byte MAC address of the station. If the MAC address registers are configured to be double-synchronized to the (G)MII clock domains. the synchronization is triggered.." bitfld.long 0x160 31. "AE,Address Enable When this bit is set the Address filter module uses the 33rd MAC address for perfect filtering. When this bit is reset the address filter module ignores the address for filtering. 0x0: Address is ignored 0x1: Address is enabled" "Address is ignored,Address is enabled" newline hexmask.long.word 0x160 19.--30. 1. "RESERVED_30_Y,Reserved." newline bitfld.long 0x160 16.--18. "DCS,DMA Channel Select This field contains the DMA Channel number to which an Rx packet whose DA matches the MAC Address32 content is routed." "0,1,2,3,4,5,6,7" newline hexmask.long.word 0x160 0.--15. 1. "ADDRHI,MAC Address32 [47:32] This field contains the upper 16 bits (47:32) of the 33rd 6-byte MAC address." line.long 0x164 "MAC_ADDRESS44_LOW,The MAC Address32 Low register holds the lower 16 bits of the 33rd 6-byte MAC address of the station." hexmask.long 0x164 0.--31. 1. "ADDRLO,MAC Address32 [31:0] This field contains the lower 32 bits of the 33rd 6-byte MAC address. The content of this field is undefined until loaded by the Application after the initialization process." line.long 0x168 "MAC_ADDRESS45_HIGH,The MAC Address32 High register holds the upper 16 bits of the 33rd 6-byte MAC address of the station. If the MAC address registers are configured to be double-synchronized to the (G)MII clock domains. the synchronization is triggered.." bitfld.long 0x168 31. "AE,Address Enable When this bit is set the Address filter module uses the 33rd MAC address for perfect filtering. When this bit is reset the address filter module ignores the address for filtering. 0x0: Address is ignored 0x1: Address is enabled" "Address is ignored,Address is enabled" newline hexmask.long.word 0x168 19.--30. 1. "RESERVED_30_Y,Reserved." newline bitfld.long 0x168 16.--18. "DCS,DMA Channel Select This field contains the DMA Channel number to which an Rx packet whose DA matches the MAC Address32 content is routed." "0,1,2,3,4,5,6,7" newline hexmask.long.word 0x168 0.--15. 1. "ADDRHI,MAC Address32 [47:32] This field contains the upper 16 bits (47:32) of the 33rd 6-byte MAC address." line.long 0x16C "MAC_ADDRESS45_LOW,The MAC Address32 Low register holds the lower 16 bits of the 33rd 6-byte MAC address of the station." hexmask.long 0x16C 0.--31. 1. "ADDRLO,MAC Address32 [31:0] This field contains the lower 32 bits of the 33rd 6-byte MAC address. The content of this field is undefined until loaded by the Application after the initialization process." line.long 0x170 "MAC_ADDRESS46_HIGH,The MAC Address32 High register holds the upper 16 bits of the 33rd 6-byte MAC address of the station. If the MAC address registers are configured to be double-synchronized to the (G)MII clock domains. the synchronization is triggered.." bitfld.long 0x170 31. "AE,Address Enable When this bit is set the Address filter module uses the 33rd MAC address for perfect filtering. When this bit is reset the address filter module ignores the address for filtering. 0x0: Address is ignored 0x1: Address is enabled" "Address is ignored,Address is enabled" newline hexmask.long.word 0x170 19.--30. 1. "RESERVED_30_Y,Reserved." newline bitfld.long 0x170 16.--18. "DCS,DMA Channel Select This field contains the DMA Channel number to which an Rx packet whose DA matches the MAC Address32 content is routed." "0,1,2,3,4,5,6,7" newline hexmask.long.word 0x170 0.--15. 1. "ADDRHI,MAC Address32 [47:32] This field contains the upper 16 bits (47:32) of the 33rd 6-byte MAC address." line.long 0x174 "MAC_ADDRESS46_LOW,The MAC Address32 Low register holds the lower 16 bits of the 33rd 6-byte MAC address of the station." hexmask.long 0x174 0.--31. 1. "ADDRLO,MAC Address32 [31:0] This field contains the lower 32 bits of the 33rd 6-byte MAC address. The content of this field is undefined until loaded by the Application after the initialization process." line.long 0x178 "MAC_ADDRESS47_HIGH,The MAC Address32 High register holds the upper 16 bits of the 33rd 6-byte MAC address of the station. If the MAC address registers are configured to be double-synchronized to the (G)MII clock domains. the synchronization is triggered.." bitfld.long 0x178 31. "AE,Address Enable When this bit is set the Address filter module uses the 33rd MAC address for perfect filtering. When this bit is reset the address filter module ignores the address for filtering. 0x0: Address is ignored 0x1: Address is enabled" "Address is ignored,Address is enabled" newline hexmask.long.word 0x178 19.--30. 1. "RESERVED_30_Y,Reserved." newline bitfld.long 0x178 16.--18. "DCS,DMA Channel Select This field contains the DMA Channel number to which an Rx packet whose DA matches the MAC Address32 content is routed." "0,1,2,3,4,5,6,7" newline hexmask.long.word 0x178 0.--15. 1. "ADDRHI,MAC Address32 [47:32] This field contains the upper 16 bits (47:32) of the 33rd 6-byte MAC address." line.long 0x17C "MAC_ADDRESS47_LOW,The MAC Address32 Low register holds the lower 16 bits of the 33rd 6-byte MAC address of the station." hexmask.long 0x17C 0.--31. 1. "ADDRLO,MAC Address32 [31:0] This field contains the lower 32 bits of the 33rd 6-byte MAC address. The content of this field is undefined until loaded by the Application after the initialization process." line.long 0x180 "MAC_ADDRESS48_HIGH,The MAC Address32 High register holds the upper 16 bits of the 33rd 6-byte MAC address of the station. If the MAC address registers are configured to be double-synchronized to the (G)MII clock domains. the synchronization is triggered.." bitfld.long 0x180 31. "AE,Address Enable When this bit is set the Address filter module uses the 33rd MAC address for perfect filtering. When this bit is reset the address filter module ignores the address for filtering. 0x0: Address is ignored 0x1: Address is enabled" "Address is ignored,Address is enabled" newline hexmask.long.word 0x180 19.--30. 1. "RESERVED_30_Y,Reserved." newline bitfld.long 0x180 16.--18. "DCS,DMA Channel Select This field contains the DMA Channel number to which an Rx packet whose DA matches the MAC Address32 content is routed." "0,1,2,3,4,5,6,7" newline hexmask.long.word 0x180 0.--15. 1. "ADDRHI,MAC Address32 [47:32] This field contains the upper 16 bits (47:32) of the 33rd 6-byte MAC address." line.long 0x184 "MAC_ADDRESS48_LOW,The MAC Address32 Low register holds the lower 16 bits of the 33rd 6-byte MAC address of the station." hexmask.long 0x184 0.--31. 1. "ADDRLO,MAC Address32 [31:0] This field contains the lower 32 bits of the 33rd 6-byte MAC address. The content of this field is undefined until loaded by the Application after the initialization process." line.long 0x188 "MAC_ADDRESS49_HIGH,The MAC Address32 High register holds the upper 16 bits of the 33rd 6-byte MAC address of the station. If the MAC address registers are configured to be double-synchronized to the (G)MII clock domains. the synchronization is triggered.." bitfld.long 0x188 31. "AE,Address Enable When this bit is set the Address filter module uses the 33rd MAC address for perfect filtering. When this bit is reset the address filter module ignores the address for filtering. 0x0: Address is ignored 0x1: Address is enabled" "Address is ignored,Address is enabled" newline hexmask.long.word 0x188 19.--30. 1. "RESERVED_30_Y,Reserved." newline bitfld.long 0x188 16.--18. "DCS,DMA Channel Select This field contains the DMA Channel number to which an Rx packet whose DA matches the MAC Address32 content is routed." "0,1,2,3,4,5,6,7" newline hexmask.long.word 0x188 0.--15. 1. "ADDRHI,MAC Address32 [47:32] This field contains the upper 16 bits (47:32) of the 33rd 6-byte MAC address." line.long 0x18C "MAC_ADDRESS49_LOW,The MAC Address32 Low register holds the lower 16 bits of the 33rd 6-byte MAC address of the station." hexmask.long 0x18C 0.--31. 1. "ADDRLO,MAC Address32 [31:0] This field contains the lower 32 bits of the 33rd 6-byte MAC address. The content of this field is undefined until loaded by the Application after the initialization process." line.long 0x190 "MAC_ADDRESS50_HIGH,The MAC Address32 High register holds the upper 16 bits of the 33rd 6-byte MAC address of the station. If the MAC address registers are configured to be double-synchronized to the (G)MII clock domains. the synchronization is triggered.." bitfld.long 0x190 31. "AE,Address Enable When this bit is set the Address filter module uses the 33rd MAC address for perfect filtering. When this bit is reset the address filter module ignores the address for filtering. 0x0: Address is ignored 0x1: Address is enabled" "Address is ignored,Address is enabled" newline hexmask.long.word 0x190 19.--30. 1. "RESERVED_30_Y,Reserved." newline bitfld.long 0x190 16.--18. "DCS,DMA Channel Select This field contains the DMA Channel number to which an Rx packet whose DA matches the MAC Address32 content is routed." "0,1,2,3,4,5,6,7" newline hexmask.long.word 0x190 0.--15. 1. "ADDRHI,MAC Address32 [47:32] This field contains the upper 16 bits (47:32) of the 33rd 6-byte MAC address." line.long 0x194 "MAC_ADDRESS50_LOW,The MAC Address32 Low register holds the lower 16 bits of the 33rd 6-byte MAC address of the station." hexmask.long 0x194 0.--31. 1. "ADDRLO,MAC Address32 [31:0] This field contains the lower 32 bits of the 33rd 6-byte MAC address. The content of this field is undefined until loaded by the Application after the initialization process." line.long 0x198 "MAC_ADDRESS51_HIGH,The MAC Address32 High register holds the upper 16 bits of the 33rd 6-byte MAC address of the station. If the MAC address registers are configured to be double-synchronized to the (G)MII clock domains. the synchronization is triggered.." bitfld.long 0x198 31. "AE,Address Enable When this bit is set the Address filter module uses the 33rd MAC address for perfect filtering. When this bit is reset the address filter module ignores the address for filtering. 0x0: Address is ignored 0x1: Address is enabled" "Address is ignored,Address is enabled" newline hexmask.long.word 0x198 19.--30. 1. "RESERVED_30_Y,Reserved." newline bitfld.long 0x198 16.--18. "DCS,DMA Channel Select This field contains the DMA Channel number to which an Rx packet whose DA matches the MAC Address32 content is routed." "0,1,2,3,4,5,6,7" newline hexmask.long.word 0x198 0.--15. 1. "ADDRHI,MAC Address32 [47:32] This field contains the upper 16 bits (47:32) of the 33rd 6-byte MAC address." line.long 0x19C "MAC_ADDRESS51_LOW,The MAC Address32 Low register holds the lower 16 bits of the 33rd 6-byte MAC address of the station." hexmask.long 0x19C 0.--31. 1. "ADDRLO,MAC Address32 [31:0] This field contains the lower 32 bits of the 33rd 6-byte MAC address. The content of this field is undefined until loaded by the Application after the initialization process." line.long 0x1A0 "MAC_ADDRESS52_HIGH,The MAC Address32 High register holds the upper 16 bits of the 33rd 6-byte MAC address of the station. If the MAC address registers are configured to be double-synchronized to the (G)MII clock domains. the synchronization is triggered.." bitfld.long 0x1A0 31. "AE,Address Enable When this bit is set the Address filter module uses the 33rd MAC address for perfect filtering. When this bit is reset the address filter module ignores the address for filtering. 0x0: Address is ignored 0x1: Address is enabled" "Address is ignored,Address is enabled" newline hexmask.long.word 0x1A0 19.--30. 1. "RESERVED_30_Y,Reserved." newline bitfld.long 0x1A0 16.--18. "DCS,DMA Channel Select This field contains the DMA Channel number to which an Rx packet whose DA matches the MAC Address32 content is routed." "0,1,2,3,4,5,6,7" newline hexmask.long.word 0x1A0 0.--15. 1. "ADDRHI,MAC Address32 [47:32] This field contains the upper 16 bits (47:32) of the 33rd 6-byte MAC address." line.long 0x1A4 "MAC_ADDRESS52_LOW,The MAC Address32 Low register holds the lower 16 bits of the 33rd 6-byte MAC address of the station." hexmask.long 0x1A4 0.--31. 1. "ADDRLO,MAC Address32 [31:0] This field contains the lower 32 bits of the 33rd 6-byte MAC address. The content of this field is undefined until loaded by the Application after the initialization process." line.long 0x1A8 "MAC_ADDRESS53_HIGH,The MAC Address32 High register holds the upper 16 bits of the 33rd 6-byte MAC address of the station. If the MAC address registers are configured to be double-synchronized to the (G)MII clock domains. the synchronization is triggered.." bitfld.long 0x1A8 31. "AE,Address Enable When this bit is set the Address filter module uses the 33rd MAC address for perfect filtering. When this bit is reset the address filter module ignores the address for filtering. 0x0: Address is ignored 0x1: Address is enabled" "Address is ignored,Address is enabled" newline hexmask.long.word 0x1A8 19.--30. 1. "RESERVED_30_Y,Reserved." newline bitfld.long 0x1A8 16.--18. "DCS,DMA Channel Select This field contains the DMA Channel number to which an Rx packet whose DA matches the MAC Address32 content is routed." "0,1,2,3,4,5,6,7" newline hexmask.long.word 0x1A8 0.--15. 1. "ADDRHI,MAC Address32 [47:32] This field contains the upper 16 bits (47:32) of the 33rd 6-byte MAC address." line.long 0x1AC "MAC_ADDRESS53_LOW,The MAC Address32 Low register holds the lower 16 bits of the 33rd 6-byte MAC address of the station." hexmask.long 0x1AC 0.--31. 1. "ADDRLO,MAC Address32 [31:0] This field contains the lower 32 bits of the 33rd 6-byte MAC address. The content of this field is undefined until loaded by the Application after the initialization process." line.long 0x1B0 "MAC_ADDRESS54_HIGH,The MAC Address32 High register holds the upper 16 bits of the 33rd 6-byte MAC address of the station. If the MAC address registers are configured to be double-synchronized to the (G)MII clock domains. the synchronization is triggered.." bitfld.long 0x1B0 31. "AE,Address Enable When this bit is set the Address filter module uses the 33rd MAC address for perfect filtering. When this bit is reset the address filter module ignores the address for filtering. 0x0: Address is ignored 0x1: Address is enabled" "Address is ignored,Address is enabled" newline hexmask.long.word 0x1B0 19.--30. 1. "RESERVED_30_Y,Reserved." newline bitfld.long 0x1B0 16.--18. "DCS,DMA Channel Select This field contains the DMA Channel number to which an Rx packet whose DA matches the MAC Address32 content is routed." "0,1,2,3,4,5,6,7" newline hexmask.long.word 0x1B0 0.--15. 1. "ADDRHI,MAC Address32 [47:32] This field contains the upper 16 bits (47:32) of the 33rd 6-byte MAC address." line.long 0x1B4 "MAC_ADDRESS54_LOW,The MAC Address32 Low register holds the lower 16 bits of the 33rd 6-byte MAC address of the station." hexmask.long 0x1B4 0.--31. 1. "ADDRLO,MAC Address32 [31:0] This field contains the lower 32 bits of the 33rd 6-byte MAC address. The content of this field is undefined until loaded by the Application after the initialization process." line.long 0x1B8 "MAC_ADDRESS55_HIGH,The MAC Address32 High register holds the upper 16 bits of the 33rd 6-byte MAC address of the station. If the MAC address registers are configured to be double-synchronized to the (G)MII clock domains. the synchronization is triggered.." bitfld.long 0x1B8 31. "AE,Address Enable When this bit is set the Address filter module uses the 33rd MAC address for perfect filtering. When this bit is reset the address filter module ignores the address for filtering. 0x0: Address is ignored 0x1: Address is enabled" "Address is ignored,Address is enabled" newline hexmask.long.word 0x1B8 19.--30. 1. "RESERVED_30_Y,Reserved." newline bitfld.long 0x1B8 16.--18. "DCS,DMA Channel Select This field contains the DMA Channel number to which an Rx packet whose DA matches the MAC Address32 content is routed." "0,1,2,3,4,5,6,7" newline hexmask.long.word 0x1B8 0.--15. 1. "ADDRHI,MAC Address32 [47:32] This field contains the upper 16 bits (47:32) of the 33rd 6-byte MAC address." line.long 0x1BC "MAC_ADDRESS55_LOW,The MAC Address32 Low register holds the lower 16 bits of the 33rd 6-byte MAC address of the station." hexmask.long 0x1BC 0.--31. 1. "ADDRLO,MAC Address32 [31:0] This field contains the lower 32 bits of the 33rd 6-byte MAC address. The content of this field is undefined until loaded by the Application after the initialization process." line.long 0x1C0 "MAC_ADDRESS56_HIGH,The MAC Address32 High register holds the upper 16 bits of the 33rd 6-byte MAC address of the station. If the MAC address registers are configured to be double-synchronized to the (G)MII clock domains. the synchronization is triggered.." bitfld.long 0x1C0 31. "AE,Address Enable When this bit is set the Address filter module uses the 33rd MAC address for perfect filtering. When this bit is reset the address filter module ignores the address for filtering. 0x0: Address is ignored 0x1: Address is enabled" "Address is ignored,Address is enabled" newline hexmask.long.word 0x1C0 19.--30. 1. "RESERVED_30_Y,Reserved." newline bitfld.long 0x1C0 16.--18. "DCS,DMA Channel Select This field contains the DMA Channel number to which an Rx packet whose DA matches the MAC Address32 content is routed." "0,1,2,3,4,5,6,7" newline hexmask.long.word 0x1C0 0.--15. 1. "ADDRHI,MAC Address32 [47:32] This field contains the upper 16 bits (47:32) of the 33rd 6-byte MAC address." line.long 0x1C4 "MAC_ADDRESS56_LOW,The MAC Address32 Low register holds the lower 16 bits of the 33rd 6-byte MAC address of the station." hexmask.long 0x1C4 0.--31. 1. "ADDRLO,MAC Address32 [31:0] This field contains the lower 32 bits of the 33rd 6-byte MAC address. The content of this field is undefined until loaded by the Application after the initialization process." line.long 0x1C8 "MAC_ADDRESS57_HIGH,The MAC Address32 High register holds the upper 16 bits of the 33rd 6-byte MAC address of the station. If the MAC address registers are configured to be double-synchronized to the (G)MII clock domains. the synchronization is triggered.." bitfld.long 0x1C8 31. "AE,Address Enable When this bit is set the Address filter module uses the 33rd MAC address for perfect filtering. When this bit is reset the address filter module ignores the address for filtering. 0x0: Address is ignored 0x1: Address is enabled" "Address is ignored,Address is enabled" newline hexmask.long.word 0x1C8 19.--30. 1. "RESERVED_30_Y,Reserved." newline bitfld.long 0x1C8 16.--18. "DCS,DMA Channel Select This field contains the DMA Channel number to which an Rx packet whose DA matches the MAC Address32 content is routed." "0,1,2,3,4,5,6,7" newline hexmask.long.word 0x1C8 0.--15. 1. "ADDRHI,MAC Address32 [47:32] This field contains the upper 16 bits (47:32) of the 33rd 6-byte MAC address." line.long 0x1CC "MAC_ADDRESS57_LOW,The MAC Address32 Low register holds the lower 16 bits of the 33rd 6-byte MAC address of the station." hexmask.long 0x1CC 0.--31. 1. "ADDRLO,MAC Address32 [31:0] This field contains the lower 32 bits of the 33rd 6-byte MAC address. The content of this field is undefined until loaded by the Application after the initialization process." line.long 0x1D0 "MAC_ADDRESS58_HIGH,The MAC Address32 High register holds the upper 16 bits of the 33rd 6-byte MAC address of the station. If the MAC address registers are configured to be double-synchronized to the (G)MII clock domains. the synchronization is triggered.." bitfld.long 0x1D0 31. "AE,Address Enable When this bit is set the Address filter module uses the 33rd MAC address for perfect filtering. When this bit is reset the address filter module ignores the address for filtering. 0x0: Address is ignored 0x1: Address is enabled" "Address is ignored,Address is enabled" newline hexmask.long.word 0x1D0 19.--30. 1. "RESERVED_30_Y,Reserved." newline bitfld.long 0x1D0 16.--18. "DCS,DMA Channel Select This field contains the DMA Channel number to which an Rx packet whose DA matches the MAC Address32 content is routed." "0,1,2,3,4,5,6,7" newline hexmask.long.word 0x1D0 0.--15. 1. "ADDRHI,MAC Address32 [47:32] This field contains the upper 16 bits (47:32) of the 33rd 6-byte MAC address." line.long 0x1D4 "MAC_ADDRESS58_LOW,The MAC Address32 Low register holds the lower 16 bits of the 33rd 6-byte MAC address of the station." hexmask.long 0x1D4 0.--31. 1. "ADDRLO,MAC Address32 [31:0] This field contains the lower 32 bits of the 33rd 6-byte MAC address. The content of this field is undefined until loaded by the Application after the initialization process." line.long 0x1D8 "MAC_ADDRESS59_HIGH,The MAC Address32 High register holds the upper 16 bits of the 33rd 6-byte MAC address of the station. If the MAC address registers are configured to be double-synchronized to the (G)MII clock domains. the synchronization is triggered.." bitfld.long 0x1D8 31. "AE,Address Enable When this bit is set the Address filter module uses the 33rd MAC address for perfect filtering. When this bit is reset the address filter module ignores the address for filtering. 0x0: Address is ignored 0x1: Address is enabled" "Address is ignored,Address is enabled" newline hexmask.long.word 0x1D8 19.--30. 1. "RESERVED_30_Y,Reserved." newline bitfld.long 0x1D8 16.--18. "DCS,DMA Channel Select This field contains the DMA Channel number to which an Rx packet whose DA matches the MAC Address32 content is routed." "0,1,2,3,4,5,6,7" newline hexmask.long.word 0x1D8 0.--15. 1. "ADDRHI,MAC Address32 [47:32] This field contains the upper 16 bits (47:32) of the 33rd 6-byte MAC address." line.long 0x1DC "MAC_ADDRESS59_LOW,The MAC Address32 Low register holds the lower 16 bits of the 33rd 6-byte MAC address of the station." hexmask.long 0x1DC 0.--31. 1. "ADDRLO,MAC Address32 [31:0] This field contains the lower 32 bits of the 33rd 6-byte MAC address. The content of this field is undefined until loaded by the Application after the initialization process." line.long 0x1E0 "MAC_ADDRESS60_HIGH,The MAC Address32 High register holds the upper 16 bits of the 33rd 6-byte MAC address of the station. If the MAC address registers are configured to be double-synchronized to the (G)MII clock domains. the synchronization is triggered.." bitfld.long 0x1E0 31. "AE,Address Enable When this bit is set the Address filter module uses the 33rd MAC address for perfect filtering. When this bit is reset the address filter module ignores the address for filtering. 0x0: Address is ignored 0x1: Address is enabled" "Address is ignored,Address is enabled" newline hexmask.long.word 0x1E0 19.--30. 1. "RESERVED_30_Y,Reserved." newline bitfld.long 0x1E0 16.--18. "DCS,DMA Channel Select This field contains the DMA Channel number to which an Rx packet whose DA matches the MAC Address32 content is routed." "0,1,2,3,4,5,6,7" newline hexmask.long.word 0x1E0 0.--15. 1. "ADDRHI,MAC Address32 [47:32] This field contains the upper 16 bits (47:32) of the 33rd 6-byte MAC address." line.long 0x1E4 "MAC_ADDRESS60_LOW,The MAC Address32 Low register holds the lower 16 bits of the 33rd 6-byte MAC address of the station." hexmask.long 0x1E4 0.--31. 1. "ADDRLO,MAC Address32 [31:0] This field contains the lower 32 bits of the 33rd 6-byte MAC address. The content of this field is undefined until loaded by the Application after the initialization process." line.long 0x1E8 "MAC_ADDRESS61_HIGH,The MAC Address32 High register holds the upper 16 bits of the 33rd 6-byte MAC address of the station. If the MAC address registers are configured to be double-synchronized to the (G)MII clock domains. the synchronization is triggered.." bitfld.long 0x1E8 31. "AE,Address Enable When this bit is set the Address filter module uses the 33rd MAC address for perfect filtering. When this bit is reset the address filter module ignores the address for filtering. 0x0: Address is ignored 0x1: Address is enabled" "Address is ignored,Address is enabled" newline hexmask.long.word 0x1E8 19.--30. 1. "RESERVED_30_Y,Reserved." newline bitfld.long 0x1E8 16.--18. "DCS,DMA Channel Select This field contains the DMA Channel number to which an Rx packet whose DA matches the MAC Address32 content is routed." "0,1,2,3,4,5,6,7" newline hexmask.long.word 0x1E8 0.--15. 1. "ADDRHI,MAC Address32 [47:32] This field contains the upper 16 bits (47:32) of the 33rd 6-byte MAC address." line.long 0x1EC "MAC_ADDRESS61_LOW,The MAC Address32 Low register holds the lower 16 bits of the 33rd 6-byte MAC address of the station." hexmask.long 0x1EC 0.--31. 1. "ADDRLO,MAC Address32 [31:0] This field contains the lower 32 bits of the 33rd 6-byte MAC address. The content of this field is undefined until loaded by the Application after the initialization process." line.long 0x1F0 "MAC_ADDRESS62_HIGH,The MAC Address32 High register holds the upper 16 bits of the 33rd 6-byte MAC address of the station. If the MAC address registers are configured to be double-synchronized to the (G)MII clock domains. the synchronization is triggered.." bitfld.long 0x1F0 31. "AE,Address Enable When this bit is set the Address filter module uses the 33rd MAC address for perfect filtering. When this bit is reset the address filter module ignores the address for filtering. 0x0: Address is ignored 0x1: Address is enabled" "Address is ignored,Address is enabled" newline hexmask.long.word 0x1F0 19.--30. 1. "RESERVED_30_Y,Reserved." newline bitfld.long 0x1F0 16.--18. "DCS,DMA Channel Select This field contains the DMA Channel number to which an Rx packet whose DA matches the MAC Address32 content is routed." "0,1,2,3,4,5,6,7" newline hexmask.long.word 0x1F0 0.--15. 1. "ADDRHI,MAC Address32 [47:32] This field contains the upper 16 bits (47:32) of the 33rd 6-byte MAC address." line.long 0x1F4 "MAC_ADDRESS62_LOW,The MAC Address32 Low register holds the lower 16 bits of the 33rd 6-byte MAC address of the station." hexmask.long 0x1F4 0.--31. 1. "ADDRLO,MAC Address32 [31:0] This field contains the lower 32 bits of the 33rd 6-byte MAC address. The content of this field is undefined until loaded by the Application after the initialization process." line.long 0x1F8 "MAC_ADDRESS63_HIGH,The MAC Address32 High register holds the upper 16 bits of the 33rd 6-byte MAC address of the station. If the MAC address registers are configured to be double-synchronized to the (G)MII clock domains. the synchronization is triggered.." bitfld.long 0x1F8 31. "AE,Address Enable When this bit is set the Address filter module uses the 33rd MAC address for perfect filtering. When this bit is reset the address filter module ignores the address for filtering. 0x0: Address is ignored 0x1: Address is enabled" "Address is ignored,Address is enabled" newline hexmask.long.word 0x1F8 19.--30. 1. "RESERVED_30_Y,Reserved." newline bitfld.long 0x1F8 16.--18. "DCS,DMA Channel Select This field contains the DMA Channel number to which an Rx packet whose DA matches the MAC Address32 content is routed." "0,1,2,3,4,5,6,7" newline hexmask.long.word 0x1F8 0.--15. 1. "ADDRHI,MAC Address32 [47:32] This field contains the upper 16 bits (47:32) of the 33rd 6-byte MAC address." line.long 0x1FC "MAC_ADDRESS63_LOW,The MAC Address32 Low register holds the lower 16 bits of the 33rd 6-byte MAC address of the station." hexmask.long 0x1FC 0.--31. 1. "ADDRLO,MAC Address32 [31:0] This field contains the lower 32 bits of the 33rd 6-byte MAC address. The content of this field is undefined until loaded by the Application after the initialization process." line.long 0x200 "MAC_ADDRESS64_HIGH,The MAC Address32 High register holds the upper 16 bits of the 33rd 6-byte MAC address of the station. If the MAC address registers are configured to be double-synchronized to the (G)MII clock domains. the synchronization is triggered.." bitfld.long 0x200 31. "AE,Address Enable When this bit is set the Address filter module uses the 33rd MAC address for perfect filtering. When this bit is reset the address filter module ignores the address for filtering. 0x0: Address is ignored 0x1: Address is enabled" "Address is ignored,Address is enabled" newline hexmask.long.word 0x200 19.--30. 1. "RESERVED_30_Y,Reserved." newline bitfld.long 0x200 16.--18. "DCS,DMA Channel Select This field contains the DMA Channel number to which an Rx packet whose DA matches the MAC Address32 content is routed." "0,1,2,3,4,5,6,7" newline hexmask.long.word 0x200 0.--15. 1. "ADDRHI,MAC Address32 [47:32] This field contains the upper 16 bits (47:32) of the 33rd 6-byte MAC address." line.long 0x204 "MAC_ADDRESS64_LOW,The MAC Address32 Low register holds the lower 16 bits of the 33rd 6-byte MAC address of the station." hexmask.long 0x204 0.--31. 1. "ADDRLO,MAC Address32 [31:0] This field contains the lower 32 bits of the 33rd 6-byte MAC address. The content of this field is undefined until loaded by the Application after the initialization process." line.long 0x208 "MAC_ADDRESS65_HIGH,The MAC Address32 High register holds the upper 16 bits of the 33rd 6-byte MAC address of the station. If the MAC address registers are configured to be double-synchronized to the (G)MII clock domains. the synchronization is triggered.." bitfld.long 0x208 31. "AE,Address Enable When this bit is set the Address filter module uses the 33rd MAC address for perfect filtering. When this bit is reset the address filter module ignores the address for filtering. 0x0: Address is ignored 0x1: Address is enabled" "Address is ignored,Address is enabled" newline hexmask.long.word 0x208 19.--30. 1. "RESERVED_30_Y,Reserved." newline bitfld.long 0x208 16.--18. "DCS,DMA Channel Select This field contains the DMA Channel number to which an Rx packet whose DA matches the MAC Address32 content is routed." "0,1,2,3,4,5,6,7" newline hexmask.long.word 0x208 0.--15. 1. "ADDRHI,MAC Address32 [47:32] This field contains the upper 16 bits (47:32) of the 33rd 6-byte MAC address." line.long 0x20C "MAC_ADDRESS65_LOW,The MAC Address32 Low register holds the lower 16 bits of the 33rd 6-byte MAC address of the station." hexmask.long 0x20C 0.--31. 1. "ADDRLO,MAC Address32 [31:0] This field contains the lower 32 bits of the 33rd 6-byte MAC address. The content of this field is undefined until loaded by the Application after the initialization process." line.long 0x210 "MAC_ADDRESS66_HIGH,The MAC Address32 High register holds the upper 16 bits of the 33rd 6-byte MAC address of the station. If the MAC address registers are configured to be double-synchronized to the (G)MII clock domains. the synchronization is triggered.." bitfld.long 0x210 31. "AE,Address Enable When this bit is set the Address filter module uses the 33rd MAC address for perfect filtering. When this bit is reset the address filter module ignores the address for filtering. 0x0: Address is ignored 0x1: Address is enabled" "Address is ignored,Address is enabled" newline hexmask.long.word 0x210 19.--30. 1. "RESERVED_30_Y,Reserved." newline bitfld.long 0x210 16.--18. "DCS,DMA Channel Select This field contains the DMA Channel number to which an Rx packet whose DA matches the MAC Address32 content is routed." "0,1,2,3,4,5,6,7" newline hexmask.long.word 0x210 0.--15. 1. "ADDRHI,MAC Address32 [47:32] This field contains the upper 16 bits (47:32) of the 33rd 6-byte MAC address." line.long 0x214 "MAC_ADDRESS66_LOW,The MAC Address32 Low register holds the lower 16 bits of the 33rd 6-byte MAC address of the station." hexmask.long 0x214 0.--31. 1. "ADDRLO,MAC Address32 [31:0] This field contains the lower 32 bits of the 33rd 6-byte MAC address. The content of this field is undefined until loaded by the Application after the initialization process." line.long 0x218 "MAC_ADDRESS67_HIGH,The MAC Address32 High register holds the upper 16 bits of the 33rd 6-byte MAC address of the station. If the MAC address registers are configured to be double-synchronized to the (G)MII clock domains. the synchronization is triggered.." bitfld.long 0x218 31. "AE,Address Enable When this bit is set the Address filter module uses the 33rd MAC address for perfect filtering. When this bit is reset the address filter module ignores the address for filtering. 0x0: Address is ignored 0x1: Address is enabled" "Address is ignored,Address is enabled" newline hexmask.long.word 0x218 19.--30. 1. "RESERVED_30_Y,Reserved." newline bitfld.long 0x218 16.--18. "DCS,DMA Channel Select This field contains the DMA Channel number to which an Rx packet whose DA matches the MAC Address32 content is routed." "0,1,2,3,4,5,6,7" newline hexmask.long.word 0x218 0.--15. 1. "ADDRHI,MAC Address32 [47:32] This field contains the upper 16 bits (47:32) of the 33rd 6-byte MAC address." line.long 0x21C "MAC_ADDRESS67_LOW,The MAC Address32 Low register holds the lower 16 bits of the 33rd 6-byte MAC address of the station." hexmask.long 0x21C 0.--31. 1. "ADDRLO,MAC Address32 [31:0] This field contains the lower 32 bits of the 33rd 6-byte MAC address. The content of this field is undefined until loaded by the Application after the initialization process." line.long 0x220 "MAC_ADDRESS68_HIGH,The MAC Address32 High register holds the upper 16 bits of the 33rd 6-byte MAC address of the station. If the MAC address registers are configured to be double-synchronized to the (G)MII clock domains. the synchronization is triggered.." bitfld.long 0x220 31. "AE,Address Enable When this bit is set the Address filter module uses the 33rd MAC address for perfect filtering. When this bit is reset the address filter module ignores the address for filtering. 0x0: Address is ignored 0x1: Address is enabled" "Address is ignored,Address is enabled" newline hexmask.long.word 0x220 19.--30. 1. "RESERVED_30_Y,Reserved." newline bitfld.long 0x220 16.--18. "DCS,DMA Channel Select This field contains the DMA Channel number to which an Rx packet whose DA matches the MAC Address32 content is routed." "0,1,2,3,4,5,6,7" newline hexmask.long.word 0x220 0.--15. 1. "ADDRHI,MAC Address32 [47:32] This field contains the upper 16 bits (47:32) of the 33rd 6-byte MAC address." line.long 0x224 "MAC_ADDRESS68_LOW,The MAC Address32 Low register holds the lower 16 bits of the 33rd 6-byte MAC address of the station." hexmask.long 0x224 0.--31. 1. "ADDRLO,MAC Address32 [31:0] This field contains the lower 32 bits of the 33rd 6-byte MAC address. The content of this field is undefined until loaded by the Application after the initialization process." line.long 0x228 "MAC_ADDRESS69_HIGH,The MAC Address32 High register holds the upper 16 bits of the 33rd 6-byte MAC address of the station. If the MAC address registers are configured to be double-synchronized to the (G)MII clock domains. the synchronization is triggered.." bitfld.long 0x228 31. "AE,Address Enable When this bit is set the Address filter module uses the 33rd MAC address for perfect filtering. When this bit is reset the address filter module ignores the address for filtering. 0x0: Address is ignored 0x1: Address is enabled" "Address is ignored,Address is enabled" newline hexmask.long.word 0x228 19.--30. 1. "RESERVED_30_Y,Reserved." newline bitfld.long 0x228 16.--18. "DCS,DMA Channel Select This field contains the DMA Channel number to which an Rx packet whose DA matches the MAC Address32 content is routed." "0,1,2,3,4,5,6,7" newline hexmask.long.word 0x228 0.--15. 1. "ADDRHI,MAC Address32 [47:32] This field contains the upper 16 bits (47:32) of the 33rd 6-byte MAC address." line.long 0x22C "MAC_ADDRESS69_LOW,The MAC Address32 Low register holds the lower 16 bits of the 33rd 6-byte MAC address of the station." hexmask.long 0x22C 0.--31. 1. "ADDRLO,MAC Address32 [31:0] This field contains the lower 32 bits of the 33rd 6-byte MAC address. The content of this field is undefined until loaded by the Application after the initialization process." line.long 0x230 "MAC_ADDRESS70_HIGH,The MAC Address32 High register holds the upper 16 bits of the 33rd 6-byte MAC address of the station. If the MAC address registers are configured to be double-synchronized to the (G)MII clock domains. the synchronization is triggered.." bitfld.long 0x230 31. "AE,Address Enable When this bit is set the Address filter module uses the 33rd MAC address for perfect filtering. When this bit is reset the address filter module ignores the address for filtering. 0x0: Address is ignored 0x1: Address is enabled" "Address is ignored,Address is enabled" newline hexmask.long.word 0x230 19.--30. 1. "RESERVED_30_Y,Reserved." newline bitfld.long 0x230 16.--18. "DCS,DMA Channel Select This field contains the DMA Channel number to which an Rx packet whose DA matches the MAC Address32 content is routed." "0,1,2,3,4,5,6,7" newline hexmask.long.word 0x230 0.--15. 1. "ADDRHI,MAC Address32 [47:32] This field contains the upper 16 bits (47:32) of the 33rd 6-byte MAC address." line.long 0x234 "MAC_ADDRESS70_LOW,The MAC Address32 Low register holds the lower 16 bits of the 33rd 6-byte MAC address of the station." hexmask.long 0x234 0.--31. 1. "ADDRLO,MAC Address32 [31:0] This field contains the lower 32 bits of the 33rd 6-byte MAC address. The content of this field is undefined until loaded by the Application after the initialization process." line.long 0x238 "MAC_ADDRESS71_HIGH,The MAC Address32 High register holds the upper 16 bits of the 33rd 6-byte MAC address of the station. If the MAC address registers are configured to be double-synchronized to the (G)MII clock domains. the synchronization is triggered.." bitfld.long 0x238 31. "AE,Address Enable When this bit is set the Address filter module uses the 33rd MAC address for perfect filtering. When this bit is reset the address filter module ignores the address for filtering. 0x0: Address is ignored 0x1: Address is enabled" "Address is ignored,Address is enabled" newline hexmask.long.word 0x238 19.--30. 1. "RESERVED_30_Y,Reserved." newline bitfld.long 0x238 16.--18. "DCS,DMA Channel Select This field contains the DMA Channel number to which an Rx packet whose DA matches the MAC Address32 content is routed." "0,1,2,3,4,5,6,7" newline hexmask.long.word 0x238 0.--15. 1. "ADDRHI,MAC Address32 [47:32] This field contains the upper 16 bits (47:32) of the 33rd 6-byte MAC address." line.long 0x23C "MAC_ADDRESS71_LOW,The MAC Address32 Low register holds the lower 16 bits of the 33rd 6-byte MAC address of the station." hexmask.long 0x23C 0.--31. 1. "ADDRLO,MAC Address32 [31:0] This field contains the lower 32 bits of the 33rd 6-byte MAC address. The content of this field is undefined until loaded by the Application after the initialization process." line.long 0x240 "MAC_ADDRESS72_HIGH,The MAC Address32 High register holds the upper 16 bits of the 33rd 6-byte MAC address of the station. If the MAC address registers are configured to be double-synchronized to the (G)MII clock domains. the synchronization is triggered.." bitfld.long 0x240 31. "AE,Address Enable When this bit is set the Address filter module uses the 33rd MAC address for perfect filtering. When this bit is reset the address filter module ignores the address for filtering. 0x0: Address is ignored 0x1: Address is enabled" "Address is ignored,Address is enabled" newline hexmask.long.word 0x240 19.--30. 1. "RESERVED_30_Y,Reserved." newline bitfld.long 0x240 16.--18. "DCS,DMA Channel Select This field contains the DMA Channel number to which an Rx packet whose DA matches the MAC Address32 content is routed." "0,1,2,3,4,5,6,7" newline hexmask.long.word 0x240 0.--15. 1. "ADDRHI,MAC Address32 [47:32] This field contains the upper 16 bits (47:32) of the 33rd 6-byte MAC address." line.long 0x244 "MAC_ADDRESS72_LOW,The MAC Address32 Low register holds the lower 16 bits of the 33rd 6-byte MAC address of the station." hexmask.long 0x244 0.--31. 1. "ADDRLO,MAC Address32 [31:0] This field contains the lower 32 bits of the 33rd 6-byte MAC address. The content of this field is undefined until loaded by the Application after the initialization process." line.long 0x248 "MAC_ADDRESS73_HIGH,The MAC Address32 High register holds the upper 16 bits of the 33rd 6-byte MAC address of the station. If the MAC address registers are configured to be double-synchronized to the (G)MII clock domains. the synchronization is triggered.." bitfld.long 0x248 31. "AE,Address Enable When this bit is set the Address filter module uses the 33rd MAC address for perfect filtering. When this bit is reset the address filter module ignores the address for filtering. 0x0: Address is ignored 0x1: Address is enabled" "Address is ignored,Address is enabled" newline hexmask.long.word 0x248 19.--30. 1. "RESERVED_30_Y,Reserved." newline bitfld.long 0x248 16.--18. "DCS,DMA Channel Select This field contains the DMA Channel number to which an Rx packet whose DA matches the MAC Address32 content is routed." "0,1,2,3,4,5,6,7" newline hexmask.long.word 0x248 0.--15. 1. "ADDRHI,MAC Address32 [47:32] This field contains the upper 16 bits (47:32) of the 33rd 6-byte MAC address." line.long 0x24C "MAC_ADDRESS73_LOW,The MAC Address32 Low register holds the lower 16 bits of the 33rd 6-byte MAC address of the station." hexmask.long 0x24C 0.--31. 1. "ADDRLO,MAC Address32 [31:0] This field contains the lower 32 bits of the 33rd 6-byte MAC address. The content of this field is undefined until loaded by the Application after the initialization process." line.long 0x250 "MAC_ADDRESS74_HIGH,The MAC Address32 High register holds the upper 16 bits of the 33rd 6-byte MAC address of the station. If the MAC address registers are configured to be double-synchronized to the (G)MII clock domains. the synchronization is triggered.." bitfld.long 0x250 31. "AE,Address Enable When this bit is set the Address filter module uses the 33rd MAC address for perfect filtering. When this bit is reset the address filter module ignores the address for filtering. 0x0: Address is ignored 0x1: Address is enabled" "Address is ignored,Address is enabled" newline hexmask.long.word 0x250 19.--30. 1. "RESERVED_30_Y,Reserved." newline bitfld.long 0x250 16.--18. "DCS,DMA Channel Select This field contains the DMA Channel number to which an Rx packet whose DA matches the MAC Address32 content is routed." "0,1,2,3,4,5,6,7" newline hexmask.long.word 0x250 0.--15. 1. "ADDRHI,MAC Address32 [47:32] This field contains the upper 16 bits (47:32) of the 33rd 6-byte MAC address." line.long 0x254 "MAC_ADDRESS74_LOW,The MAC Address32 Low register holds the lower 16 bits of the 33rd 6-byte MAC address of the station." hexmask.long 0x254 0.--31. 1. "ADDRLO,MAC Address32 [31:0] This field contains the lower 32 bits of the 33rd 6-byte MAC address. The content of this field is undefined until loaded by the Application after the initialization process." line.long 0x258 "MAC_ADDRESS75_HIGH,The MAC Address32 High register holds the upper 16 bits of the 33rd 6-byte MAC address of the station. If the MAC address registers are configured to be double-synchronized to the (G)MII clock domains. the synchronization is triggered.." bitfld.long 0x258 31. "AE,Address Enable When this bit is set the Address filter module uses the 33rd MAC address for perfect filtering. When this bit is reset the address filter module ignores the address for filtering. 0x0: Address is ignored 0x1: Address is enabled" "Address is ignored,Address is enabled" newline hexmask.long.word 0x258 19.--30. 1. "RESERVED_30_Y,Reserved." newline bitfld.long 0x258 16.--18. "DCS,DMA Channel Select This field contains the DMA Channel number to which an Rx packet whose DA matches the MAC Address32 content is routed." "0,1,2,3,4,5,6,7" newline hexmask.long.word 0x258 0.--15. 1. "ADDRHI,MAC Address32 [47:32] This field contains the upper 16 bits (47:32) of the 33rd 6-byte MAC address." line.long 0x25C "MAC_ADDRESS75_LOW,The MAC Address32 Low register holds the lower 16 bits of the 33rd 6-byte MAC address of the station." hexmask.long 0x25C 0.--31. 1. "ADDRLO,MAC Address32 [31:0] This field contains the lower 32 bits of the 33rd 6-byte MAC address. The content of this field is undefined until loaded by the Application after the initialization process." line.long 0x260 "MAC_ADDRESS76_HIGH,The MAC Address32 High register holds the upper 16 bits of the 33rd 6-byte MAC address of the station. If the MAC address registers are configured to be double-synchronized to the (G)MII clock domains. the synchronization is triggered.." bitfld.long 0x260 31. "AE,Address Enable When this bit is set the Address filter module uses the 33rd MAC address for perfect filtering. When this bit is reset the address filter module ignores the address for filtering. 0x0: Address is ignored 0x1: Address is enabled" "Address is ignored,Address is enabled" newline hexmask.long.word 0x260 19.--30. 1. "RESERVED_30_Y,Reserved." newline bitfld.long 0x260 16.--18. "DCS,DMA Channel Select This field contains the DMA Channel number to which an Rx packet whose DA matches the MAC Address32 content is routed." "0,1,2,3,4,5,6,7" newline hexmask.long.word 0x260 0.--15. 1. "ADDRHI,MAC Address32 [47:32] This field contains the upper 16 bits (47:32) of the 33rd 6-byte MAC address." line.long 0x264 "MAC_ADDRESS76_LOW,The MAC Address32 Low register holds the lower 16 bits of the 33rd 6-byte MAC address of the station." hexmask.long 0x264 0.--31. 1. "ADDRLO,MAC Address32 [31:0] This field contains the lower 32 bits of the 33rd 6-byte MAC address. The content of this field is undefined until loaded by the Application after the initialization process." line.long 0x268 "MAC_ADDRESS77_HIGH,The MAC Address32 High register holds the upper 16 bits of the 33rd 6-byte MAC address of the station. If the MAC address registers are configured to be double-synchronized to the (G)MII clock domains. the synchronization is triggered.." bitfld.long 0x268 31. "AE,Address Enable When this bit is set the Address filter module uses the 33rd MAC address for perfect filtering. When this bit is reset the address filter module ignores the address for filtering. 0x0: Address is ignored 0x1: Address is enabled" "Address is ignored,Address is enabled" newline hexmask.long.word 0x268 19.--30. 1. "RESERVED_30_Y,Reserved." newline bitfld.long 0x268 16.--18. "DCS,DMA Channel Select This field contains the DMA Channel number to which an Rx packet whose DA matches the MAC Address32 content is routed." "0,1,2,3,4,5,6,7" newline hexmask.long.word 0x268 0.--15. 1. "ADDRHI,MAC Address32 [47:32] This field contains the upper 16 bits (47:32) of the 33rd 6-byte MAC address." line.long 0x26C "MAC_ADDRESS77_LOW,The MAC Address32 Low register holds the lower 16 bits of the 33rd 6-byte MAC address of the station." hexmask.long 0x26C 0.--31. 1. "ADDRLO,MAC Address32 [31:0] This field contains the lower 32 bits of the 33rd 6-byte MAC address. The content of this field is undefined until loaded by the Application after the initialization process." line.long 0x270 "MAC_ADDRESS78_HIGH,The MAC Address32 High register holds the upper 16 bits of the 33rd 6-byte MAC address of the station. If the MAC address registers are configured to be double-synchronized to the (G)MII clock domains. the synchronization is triggered.." bitfld.long 0x270 31. "AE,Address Enable When this bit is set the Address filter module uses the 33rd MAC address for perfect filtering. When this bit is reset the address filter module ignores the address for filtering. 0x0: Address is ignored 0x1: Address is enabled" "Address is ignored,Address is enabled" newline hexmask.long.word 0x270 19.--30. 1. "RESERVED_30_Y,Reserved." newline bitfld.long 0x270 16.--18. "DCS,DMA Channel Select This field contains the DMA Channel number to which an Rx packet whose DA matches the MAC Address32 content is routed." "0,1,2,3,4,5,6,7" newline hexmask.long.word 0x270 0.--15. 1. "ADDRHI,MAC Address32 [47:32] This field contains the upper 16 bits (47:32) of the 33rd 6-byte MAC address." line.long 0x274 "MAC_ADDRESS78_LOW,The MAC Address32 Low register holds the lower 16 bits of the 33rd 6-byte MAC address of the station." hexmask.long 0x274 0.--31. 1. "ADDRLO,MAC Address32 [31:0] This field contains the lower 32 bits of the 33rd 6-byte MAC address. The content of this field is undefined until loaded by the Application after the initialization process." line.long 0x278 "MAC_ADDRESS79_HIGH,The MAC Address32 High register holds the upper 16 bits of the 33rd 6-byte MAC address of the station. If the MAC address registers are configured to be double-synchronized to the (G)MII clock domains. the synchronization is triggered.." bitfld.long 0x278 31. "AE,Address Enable When this bit is set the Address filter module uses the 33rd MAC address for perfect filtering. When this bit is reset the address filter module ignores the address for filtering. 0x0: Address is ignored 0x1: Address is enabled" "Address is ignored,Address is enabled" newline hexmask.long.word 0x278 19.--30. 1. "RESERVED_30_Y,Reserved." newline bitfld.long 0x278 16.--18. "DCS,DMA Channel Select This field contains the DMA Channel number to which an Rx packet whose DA matches the MAC Address32 content is routed." "0,1,2,3,4,5,6,7" newline hexmask.long.word 0x278 0.--15. 1. "ADDRHI,MAC Address32 [47:32] This field contains the upper 16 bits (47:32) of the 33rd 6-byte MAC address." line.long 0x27C "MAC_ADDRESS79_LOW,The MAC Address32 Low register holds the lower 16 bits of the 33rd 6-byte MAC address of the station." hexmask.long 0x27C 0.--31. 1. "ADDRLO,MAC Address32 [31:0] This field contains the lower 32 bits of the 33rd 6-byte MAC address. The content of this field is undefined until loaded by the Application after the initialization process." line.long 0x280 "MAC_ADDRESS80_HIGH,The MAC Address32 High register holds the upper 16 bits of the 33rd 6-byte MAC address of the station. If the MAC address registers are configured to be double-synchronized to the (G)MII clock domains. the synchronization is triggered.." bitfld.long 0x280 31. "AE,Address Enable When this bit is set the Address filter module uses the 33rd MAC address for perfect filtering. When this bit is reset the address filter module ignores the address for filtering. 0x0: Address is ignored 0x1: Address is enabled" "Address is ignored,Address is enabled" newline hexmask.long.word 0x280 19.--30. 1. "RESERVED_30_Y,Reserved." newline bitfld.long 0x280 16.--18. "DCS,DMA Channel Select This field contains the DMA Channel number to which an Rx packet whose DA matches the MAC Address32 content is routed." "0,1,2,3,4,5,6,7" newline hexmask.long.word 0x280 0.--15. 1. "ADDRHI,MAC Address32 [47:32] This field contains the upper 16 bits (47:32) of the 33rd 6-byte MAC address." line.long 0x284 "MAC_ADDRESS80_LOW,The MAC Address32 Low register holds the lower 16 bits of the 33rd 6-byte MAC address of the station." hexmask.long 0x284 0.--31. 1. "ADDRLO,MAC Address32 [31:0] This field contains the lower 32 bits of the 33rd 6-byte MAC address. The content of this field is undefined until loaded by the Application after the initialization process." line.long 0x288 "MAC_ADDRESS81_HIGH,The MAC Address32 High register holds the upper 16 bits of the 33rd 6-byte MAC address of the station. If the MAC address registers are configured to be double-synchronized to the (G)MII clock domains. the synchronization is triggered.." bitfld.long 0x288 31. "AE,Address Enable When this bit is set the Address filter module uses the 33rd MAC address for perfect filtering. When this bit is reset the address filter module ignores the address for filtering. 0x0: Address is ignored 0x1: Address is enabled" "Address is ignored,Address is enabled" newline hexmask.long.word 0x288 19.--30. 1. "RESERVED_30_Y,Reserved." newline bitfld.long 0x288 16.--18. "DCS,DMA Channel Select This field contains the DMA Channel number to which an Rx packet whose DA matches the MAC Address32 content is routed." "0,1,2,3,4,5,6,7" newline hexmask.long.word 0x288 0.--15. 1. "ADDRHI,MAC Address32 [47:32] This field contains the upper 16 bits (47:32) of the 33rd 6-byte MAC address." line.long 0x28C "MAC_ADDRESS81_LOW,The MAC Address32 Low register holds the lower 16 bits of the 33rd 6-byte MAC address of the station." hexmask.long 0x28C 0.--31. 1. "ADDRLO,MAC Address32 [31:0] This field contains the lower 32 bits of the 33rd 6-byte MAC address. The content of this field is undefined until loaded by the Application after the initialization process." line.long 0x290 "MAC_ADDRESS82_HIGH,The MAC Address32 High register holds the upper 16 bits of the 33rd 6-byte MAC address of the station. If the MAC address registers are configured to be double-synchronized to the (G)MII clock domains. the synchronization is triggered.." bitfld.long 0x290 31. "AE,Address Enable When this bit is set the Address filter module uses the 33rd MAC address for perfect filtering. When this bit is reset the address filter module ignores the address for filtering. 0x0: Address is ignored 0x1: Address is enabled" "Address is ignored,Address is enabled" newline hexmask.long.word 0x290 19.--30. 1. "RESERVED_30_Y,Reserved." newline bitfld.long 0x290 16.--18. "DCS,DMA Channel Select This field contains the DMA Channel number to which an Rx packet whose DA matches the MAC Address32 content is routed." "0,1,2,3,4,5,6,7" newline hexmask.long.word 0x290 0.--15. 1. "ADDRHI,MAC Address32 [47:32] This field contains the upper 16 bits (47:32) of the 33rd 6-byte MAC address." line.long 0x294 "MAC_ADDRESS82_LOW,The MAC Address32 Low register holds the lower 16 bits of the 33rd 6-byte MAC address of the station." hexmask.long 0x294 0.--31. 1. "ADDRLO,MAC Address32 [31:0] This field contains the lower 32 bits of the 33rd 6-byte MAC address. The content of this field is undefined until loaded by the Application after the initialization process." line.long 0x298 "MAC_ADDRESS83_HIGH,The MAC Address32 High register holds the upper 16 bits of the 33rd 6-byte MAC address of the station. If the MAC address registers are configured to be double-synchronized to the (G)MII clock domains. the synchronization is triggered.." bitfld.long 0x298 31. "AE,Address Enable When this bit is set the Address filter module uses the 33rd MAC address for perfect filtering. When this bit is reset the address filter module ignores the address for filtering. 0x0: Address is ignored 0x1: Address is enabled" "Address is ignored,Address is enabled" newline hexmask.long.word 0x298 19.--30. 1. "RESERVED_30_Y,Reserved." newline bitfld.long 0x298 16.--18. "DCS,DMA Channel Select This field contains the DMA Channel number to which an Rx packet whose DA matches the MAC Address32 content is routed." "0,1,2,3,4,5,6,7" newline hexmask.long.word 0x298 0.--15. 1. "ADDRHI,MAC Address32 [47:32] This field contains the upper 16 bits (47:32) of the 33rd 6-byte MAC address." line.long 0x29C "MAC_ADDRESS83_LOW,The MAC Address32 Low register holds the lower 16 bits of the 33rd 6-byte MAC address of the station." hexmask.long 0x29C 0.--31. 1. "ADDRLO,MAC Address32 [31:0] This field contains the lower 32 bits of the 33rd 6-byte MAC address. The content of this field is undefined until loaded by the Application after the initialization process." line.long 0x2A0 "MAC_ADDRESS84_HIGH,The MAC Address32 High register holds the upper 16 bits of the 33rd 6-byte MAC address of the station. If the MAC address registers are configured to be double-synchronized to the (G)MII clock domains. the synchronization is triggered.." bitfld.long 0x2A0 31. "AE,Address Enable When this bit is set the Address filter module uses the 33rd MAC address for perfect filtering. When this bit is reset the address filter module ignores the address for filtering. 0x0: Address is ignored 0x1: Address is enabled" "Address is ignored,Address is enabled" newline hexmask.long.word 0x2A0 19.--30. 1. "RESERVED_30_Y,Reserved." newline bitfld.long 0x2A0 16.--18. "DCS,DMA Channel Select This field contains the DMA Channel number to which an Rx packet whose DA matches the MAC Address32 content is routed." "0,1,2,3,4,5,6,7" newline hexmask.long.word 0x2A0 0.--15. 1. "ADDRHI,MAC Address32 [47:32] This field contains the upper 16 bits (47:32) of the 33rd 6-byte MAC address." line.long 0x2A4 "MAC_ADDRESS84_LOW,The MAC Address32 Low register holds the lower 16 bits of the 33rd 6-byte MAC address of the station." hexmask.long 0x2A4 0.--31. 1. "ADDRLO,MAC Address32 [31:0] This field contains the lower 32 bits of the 33rd 6-byte MAC address. The content of this field is undefined until loaded by the Application after the initialization process." line.long 0x2A8 "MAC_ADDRESS85_HIGH,The MAC Address32 High register holds the upper 16 bits of the 33rd 6-byte MAC address of the station. If the MAC address registers are configured to be double-synchronized to the (G)MII clock domains. the synchronization is triggered.." bitfld.long 0x2A8 31. "AE,Address Enable When this bit is set the Address filter module uses the 33rd MAC address for perfect filtering. When this bit is reset the address filter module ignores the address for filtering. 0x0: Address is ignored 0x1: Address is enabled" "Address is ignored,Address is enabled" newline hexmask.long.word 0x2A8 19.--30. 1. "RESERVED_30_Y,Reserved." newline bitfld.long 0x2A8 16.--18. "DCS,DMA Channel Select This field contains the DMA Channel number to which an Rx packet whose DA matches the MAC Address32 content is routed." "0,1,2,3,4,5,6,7" newline hexmask.long.word 0x2A8 0.--15. 1. "ADDRHI,MAC Address32 [47:32] This field contains the upper 16 bits (47:32) of the 33rd 6-byte MAC address." line.long 0x2AC "MAC_ADDRESS85_LOW,The MAC Address32 Low register holds the lower 16 bits of the 33rd 6-byte MAC address of the station." hexmask.long 0x2AC 0.--31. 1. "ADDRLO,MAC Address32 [31:0] This field contains the lower 32 bits of the 33rd 6-byte MAC address. The content of this field is undefined until loaded by the Application after the initialization process." line.long 0x2B0 "MAC_ADDRESS86_HIGH,The MAC Address32 High register holds the upper 16 bits of the 33rd 6-byte MAC address of the station. If the MAC address registers are configured to be double-synchronized to the (G)MII clock domains. the synchronization is triggered.." bitfld.long 0x2B0 31. "AE,Address Enable When this bit is set the Address filter module uses the 33rd MAC address for perfect filtering. When this bit is reset the address filter module ignores the address for filtering. 0x0: Address is ignored 0x1: Address is enabled" "Address is ignored,Address is enabled" newline hexmask.long.word 0x2B0 19.--30. 1. "RESERVED_30_Y,Reserved." newline bitfld.long 0x2B0 16.--18. "DCS,DMA Channel Select This field contains the DMA Channel number to which an Rx packet whose DA matches the MAC Address32 content is routed." "0,1,2,3,4,5,6,7" newline hexmask.long.word 0x2B0 0.--15. 1. "ADDRHI,MAC Address32 [47:32] This field contains the upper 16 bits (47:32) of the 33rd 6-byte MAC address." line.long 0x2B4 "MAC_ADDRESS86_LOW,The MAC Address32 Low register holds the lower 16 bits of the 33rd 6-byte MAC address of the station." hexmask.long 0x2B4 0.--31. 1. "ADDRLO,MAC Address32 [31:0] This field contains the lower 32 bits of the 33rd 6-byte MAC address. The content of this field is undefined until loaded by the Application after the initialization process." line.long 0x2B8 "MAC_ADDRESS87_HIGH,The MAC Address32 High register holds the upper 16 bits of the 33rd 6-byte MAC address of the station. If the MAC address registers are configured to be double-synchronized to the (G)MII clock domains. the synchronization is triggered.." bitfld.long 0x2B8 31. "AE,Address Enable When this bit is set the Address filter module uses the 33rd MAC address for perfect filtering. When this bit is reset the address filter module ignores the address for filtering. 0x0: Address is ignored 0x1: Address is enabled" "Address is ignored,Address is enabled" newline hexmask.long.word 0x2B8 19.--30. 1. "RESERVED_30_Y,Reserved." newline bitfld.long 0x2B8 16.--18. "DCS,DMA Channel Select This field contains the DMA Channel number to which an Rx packet whose DA matches the MAC Address32 content is routed." "0,1,2,3,4,5,6,7" newline hexmask.long.word 0x2B8 0.--15. 1. "ADDRHI,MAC Address32 [47:32] This field contains the upper 16 bits (47:32) of the 33rd 6-byte MAC address." line.long 0x2BC "MAC_ADDRESS87_LOW,The MAC Address32 Low register holds the lower 16 bits of the 33rd 6-byte MAC address of the station." hexmask.long 0x2BC 0.--31. 1. "ADDRLO,MAC Address32 [31:0] This field contains the lower 32 bits of the 33rd 6-byte MAC address. The content of this field is undefined until loaded by the Application after the initialization process." line.long 0x2C0 "MAC_ADDRESS88_HIGH,The MAC Address32 High register holds the upper 16 bits of the 33rd 6-byte MAC address of the station. If the MAC address registers are configured to be double-synchronized to the (G)MII clock domains. the synchronization is triggered.." bitfld.long 0x2C0 31. "AE,Address Enable When this bit is set the Address filter module uses the 33rd MAC address for perfect filtering. When this bit is reset the address filter module ignores the address for filtering. 0x0: Address is ignored 0x1: Address is enabled" "Address is ignored,Address is enabled" newline hexmask.long.word 0x2C0 19.--30. 1. "RESERVED_30_Y,Reserved." newline bitfld.long 0x2C0 16.--18. "DCS,DMA Channel Select This field contains the DMA Channel number to which an Rx packet whose DA matches the MAC Address32 content is routed." "0,1,2,3,4,5,6,7" newline hexmask.long.word 0x2C0 0.--15. 1. "ADDRHI,MAC Address32 [47:32] This field contains the upper 16 bits (47:32) of the 33rd 6-byte MAC address." line.long 0x2C4 "MAC_ADDRESS88_LOW,The MAC Address32 Low register holds the lower 16 bits of the 33rd 6-byte MAC address of the station." hexmask.long 0x2C4 0.--31. 1. "ADDRLO,MAC Address32 [31:0] This field contains the lower 32 bits of the 33rd 6-byte MAC address. The content of this field is undefined until loaded by the Application after the initialization process." line.long 0x2C8 "MAC_ADDRESS89_HIGH,The MAC Address32 High register holds the upper 16 bits of the 33rd 6-byte MAC address of the station. If the MAC address registers are configured to be double-synchronized to the (G)MII clock domains. the synchronization is triggered.." bitfld.long 0x2C8 31. "AE,Address Enable When this bit is set the Address filter module uses the 33rd MAC address for perfect filtering. When this bit is reset the address filter module ignores the address for filtering. 0x0: Address is ignored 0x1: Address is enabled" "Address is ignored,Address is enabled" newline hexmask.long.word 0x2C8 19.--30. 1. "RESERVED_30_Y,Reserved." newline bitfld.long 0x2C8 16.--18. "DCS,DMA Channel Select This field contains the DMA Channel number to which an Rx packet whose DA matches the MAC Address32 content is routed." "0,1,2,3,4,5,6,7" newline hexmask.long.word 0x2C8 0.--15. 1. "ADDRHI,MAC Address32 [47:32] This field contains the upper 16 bits (47:32) of the 33rd 6-byte MAC address." line.long 0x2CC "MAC_ADDRESS89_LOW,The MAC Address32 Low register holds the lower 16 bits of the 33rd 6-byte MAC address of the station." hexmask.long 0x2CC 0.--31. 1. "ADDRLO,MAC Address32 [31:0] This field contains the lower 32 bits of the 33rd 6-byte MAC address. The content of this field is undefined until loaded by the Application after the initialization process." line.long 0x2D0 "MAC_ADDRESS90_HIGH,The MAC Address32 High register holds the upper 16 bits of the 33rd 6-byte MAC address of the station. If the MAC address registers are configured to be double-synchronized to the (G)MII clock domains. the synchronization is triggered.." bitfld.long 0x2D0 31. "AE,Address Enable When this bit is set the Address filter module uses the 33rd MAC address for perfect filtering. When this bit is reset the address filter module ignores the address for filtering. 0x0: Address is ignored 0x1: Address is enabled" "Address is ignored,Address is enabled" newline hexmask.long.word 0x2D0 19.--30. 1. "RESERVED_30_Y,Reserved." newline bitfld.long 0x2D0 16.--18. "DCS,DMA Channel Select This field contains the DMA Channel number to which an Rx packet whose DA matches the MAC Address32 content is routed." "0,1,2,3,4,5,6,7" newline hexmask.long.word 0x2D0 0.--15. 1. "ADDRHI,MAC Address32 [47:32] This field contains the upper 16 bits (47:32) of the 33rd 6-byte MAC address." line.long 0x2D4 "MAC_ADDRESS90_LOW,The MAC Address32 Low register holds the lower 16 bits of the 33rd 6-byte MAC address of the station." hexmask.long 0x2D4 0.--31. 1. "ADDRLO,MAC Address32 [31:0] This field contains the lower 32 bits of the 33rd 6-byte MAC address. The content of this field is undefined until loaded by the Application after the initialization process." line.long 0x2D8 "MAC_ADDRESS91_HIGH,The MAC Address32 High register holds the upper 16 bits of the 33rd 6-byte MAC address of the station. If the MAC address registers are configured to be double-synchronized to the (G)MII clock domains. the synchronization is triggered.." bitfld.long 0x2D8 31. "AE,Address Enable When this bit is set the Address filter module uses the 33rd MAC address for perfect filtering. When this bit is reset the address filter module ignores the address for filtering. 0x0: Address is ignored 0x1: Address is enabled" "Address is ignored,Address is enabled" newline hexmask.long.word 0x2D8 19.--30. 1. "RESERVED_30_Y,Reserved." newline bitfld.long 0x2D8 16.--18. "DCS,DMA Channel Select This field contains the DMA Channel number to which an Rx packet whose DA matches the MAC Address32 content is routed." "0,1,2,3,4,5,6,7" newline hexmask.long.word 0x2D8 0.--15. 1. "ADDRHI,MAC Address32 [47:32] This field contains the upper 16 bits (47:32) of the 33rd 6-byte MAC address." line.long 0x2DC "MAC_ADDRESS91_LOW,The MAC Address32 Low register holds the lower 16 bits of the 33rd 6-byte MAC address of the station." hexmask.long 0x2DC 0.--31. 1. "ADDRLO,MAC Address32 [31:0] This field contains the lower 32 bits of the 33rd 6-byte MAC address. The content of this field is undefined until loaded by the Application after the initialization process." line.long 0x2E0 "MAC_ADDRESS92_HIGH,The MAC Address32 High register holds the upper 16 bits of the 33rd 6-byte MAC address of the station. If the MAC address registers are configured to be double-synchronized to the (G)MII clock domains. the synchronization is triggered.." bitfld.long 0x2E0 31. "AE,Address Enable When this bit is set the Address filter module uses the 33rd MAC address for perfect filtering. When this bit is reset the address filter module ignores the address for filtering. 0x0: Address is ignored 0x1: Address is enabled" "Address is ignored,Address is enabled" newline hexmask.long.word 0x2E0 19.--30. 1. "RESERVED_30_Y,Reserved." newline bitfld.long 0x2E0 16.--18. "DCS,DMA Channel Select This field contains the DMA Channel number to which an Rx packet whose DA matches the MAC Address32 content is routed." "0,1,2,3,4,5,6,7" newline hexmask.long.word 0x2E0 0.--15. 1. "ADDRHI,MAC Address32 [47:32] This field contains the upper 16 bits (47:32) of the 33rd 6-byte MAC address." line.long 0x2E4 "MAC_ADDRESS92_LOW,The MAC Address32 Low register holds the lower 16 bits of the 33rd 6-byte MAC address of the station." hexmask.long 0x2E4 0.--31. 1. "ADDRLO,MAC Address32 [31:0] This field contains the lower 32 bits of the 33rd 6-byte MAC address. The content of this field is undefined until loaded by the Application after the initialization process." line.long 0x2E8 "MAC_ADDRESS93_HIGH,The MAC Address32 High register holds the upper 16 bits of the 33rd 6-byte MAC address of the station. If the MAC address registers are configured to be double-synchronized to the (G)MII clock domains. the synchronization is triggered.." bitfld.long 0x2E8 31. "AE,Address Enable When this bit is set the Address filter module uses the 33rd MAC address for perfect filtering. When this bit is reset the address filter module ignores the address for filtering. 0x0: Address is ignored 0x1: Address is enabled" "Address is ignored,Address is enabled" newline hexmask.long.word 0x2E8 19.--30. 1. "RESERVED_30_Y,Reserved." newline bitfld.long 0x2E8 16.--18. "DCS,DMA Channel Select This field contains the DMA Channel number to which an Rx packet whose DA matches the MAC Address32 content is routed." "0,1,2,3,4,5,6,7" newline hexmask.long.word 0x2E8 0.--15. 1. "ADDRHI,MAC Address32 [47:32] This field contains the upper 16 bits (47:32) of the 33rd 6-byte MAC address." line.long 0x2EC "MAC_ADDRESS93_LOW,The MAC Address32 Low register holds the lower 16 bits of the 33rd 6-byte MAC address of the station." hexmask.long 0x2EC 0.--31. 1. "ADDRLO,MAC Address32 [31:0] This field contains the lower 32 bits of the 33rd 6-byte MAC address. The content of this field is undefined until loaded by the Application after the initialization process." line.long 0x2F0 "MAC_ADDRESS94_HIGH,The MAC Address32 High register holds the upper 16 bits of the 33rd 6-byte MAC address of the station. If the MAC address registers are configured to be double-synchronized to the (G)MII clock domains. the synchronization is triggered.." bitfld.long 0x2F0 31. "AE,Address Enable When this bit is set the Address filter module uses the 33rd MAC address for perfect filtering. When this bit is reset the address filter module ignores the address for filtering. 0x0: Address is ignored 0x1: Address is enabled" "Address is ignored,Address is enabled" newline hexmask.long.word 0x2F0 19.--30. 1. "RESERVED_30_Y,Reserved." newline bitfld.long 0x2F0 16.--18. "DCS,DMA Channel Select This field contains the DMA Channel number to which an Rx packet whose DA matches the MAC Address32 content is routed." "0,1,2,3,4,5,6,7" newline hexmask.long.word 0x2F0 0.--15. 1. "ADDRHI,MAC Address32 [47:32] This field contains the upper 16 bits (47:32) of the 33rd 6-byte MAC address." line.long 0x2F4 "MAC_ADDRESS94_LOW,The MAC Address32 Low register holds the lower 16 bits of the 33rd 6-byte MAC address of the station." hexmask.long 0x2F4 0.--31. 1. "ADDRLO,MAC Address32 [31:0] This field contains the lower 32 bits of the 33rd 6-byte MAC address. The content of this field is undefined until loaded by the Application after the initialization process." line.long 0x2F8 "MAC_ADDRESS95_HIGH,The MAC Address32 High register holds the upper 16 bits of the 33rd 6-byte MAC address of the station. If the MAC address registers are configured to be double-synchronized to the (G)MII clock domains. the synchronization is triggered.." bitfld.long 0x2F8 31. "AE,Address Enable When this bit is set the Address filter module uses the 33rd MAC address for perfect filtering. When this bit is reset the address filter module ignores the address for filtering. 0x0: Address is ignored 0x1: Address is enabled" "Address is ignored,Address is enabled" newline hexmask.long.word 0x2F8 19.--30. 1. "RESERVED_30_Y,Reserved." newline bitfld.long 0x2F8 16.--18. "DCS,DMA Channel Select This field contains the DMA Channel number to which an Rx packet whose DA matches the MAC Address32 content is routed." "0,1,2,3,4,5,6,7" newline hexmask.long.word 0x2F8 0.--15. 1. "ADDRHI,MAC Address32 [47:32] This field contains the upper 16 bits (47:32) of the 33rd 6-byte MAC address." line.long 0x2FC "MAC_ADDRESS95_LOW,The MAC Address32 Low register holds the lower 16 bits of the 33rd 6-byte MAC address of the station." hexmask.long 0x2FC 0.--31. 1. "ADDRLO,MAC Address32 [31:0] This field contains the lower 32 bits of the 33rd 6-byte MAC address. The content of this field is undefined until loaded by the Application after the initialization process." line.long 0x300 "MAC_ADDRESS96_HIGH,The MAC Address32 High register holds the upper 16 bits of the 33rd 6-byte MAC address of the station. If the MAC address registers are configured to be double-synchronized to the (G)MII clock domains. the synchronization is triggered.." bitfld.long 0x300 31. "AE,Address Enable When this bit is set the Address filter module uses the 33rd MAC address for perfect filtering. When this bit is reset the address filter module ignores the address for filtering. 0x0: Address is ignored 0x1: Address is enabled" "Address is ignored,Address is enabled" newline hexmask.long.word 0x300 19.--30. 1. "RESERVED_30_Y,Reserved." newline bitfld.long 0x300 16.--18. "DCS,DMA Channel Select This field contains the DMA Channel number to which an Rx packet whose DA matches the MAC Address32 content is routed." "0,1,2,3,4,5,6,7" newline hexmask.long.word 0x300 0.--15. 1. "ADDRHI,MAC Address32 [47:32] This field contains the upper 16 bits (47:32) of the 33rd 6-byte MAC address." line.long 0x304 "MAC_ADDRESS96_LOW,The MAC Address32 Low register holds the lower 16 bits of the 33rd 6-byte MAC address of the station." hexmask.long 0x304 0.--31. 1. "ADDRLO,MAC Address32 [31:0] This field contains the lower 32 bits of the 33rd 6-byte MAC address. The content of this field is undefined until loaded by the Application after the initialization process." line.long 0x308 "MAC_ADDRESS97_HIGH,The MAC Address32 High register holds the upper 16 bits of the 33rd 6-byte MAC address of the station. If the MAC address registers are configured to be double-synchronized to the (G)MII clock domains. the synchronization is triggered.." bitfld.long 0x308 31. "AE,Address Enable When this bit is set the Address filter module uses the 33rd MAC address for perfect filtering. When this bit is reset the address filter module ignores the address for filtering. 0x0: Address is ignored 0x1: Address is enabled" "Address is ignored,Address is enabled" newline hexmask.long.word 0x308 19.--30. 1. "RESERVED_30_Y,Reserved." newline bitfld.long 0x308 16.--18. "DCS,DMA Channel Select This field contains the DMA Channel number to which an Rx packet whose DA matches the MAC Address32 content is routed." "0,1,2,3,4,5,6,7" newline hexmask.long.word 0x308 0.--15. 1. "ADDRHI,MAC Address32 [47:32] This field contains the upper 16 bits (47:32) of the 33rd 6-byte MAC address." line.long 0x30C "MAC_ADDRESS97_LOW,The MAC Address32 Low register holds the lower 16 bits of the 33rd 6-byte MAC address of the station." hexmask.long 0x30C 0.--31. 1. "ADDRLO,MAC Address32 [31:0] This field contains the lower 32 bits of the 33rd 6-byte MAC address. The content of this field is undefined until loaded by the Application after the initialization process." line.long 0x310 "MAC_ADDRESS98_HIGH,The MAC Address32 High register holds the upper 16 bits of the 33rd 6-byte MAC address of the station. If the MAC address registers are configured to be double-synchronized to the (G)MII clock domains. the synchronization is triggered.." bitfld.long 0x310 31. "AE,Address Enable When this bit is set the Address filter module uses the 33rd MAC address for perfect filtering. When this bit is reset the address filter module ignores the address for filtering. 0x0: Address is ignored 0x1: Address is enabled" "Address is ignored,Address is enabled" newline hexmask.long.word 0x310 19.--30. 1. "RESERVED_30_Y,Reserved." newline bitfld.long 0x310 16.--18. "DCS,DMA Channel Select This field contains the DMA Channel number to which an Rx packet whose DA matches the MAC Address32 content is routed." "0,1,2,3,4,5,6,7" newline hexmask.long.word 0x310 0.--15. 1. "ADDRHI,MAC Address32 [47:32] This field contains the upper 16 bits (47:32) of the 33rd 6-byte MAC address." line.long 0x314 "MAC_ADDRESS98_LOW,The MAC Address32 Low register holds the lower 16 bits of the 33rd 6-byte MAC address of the station." hexmask.long 0x314 0.--31. 1. "ADDRLO,MAC Address32 [31:0] This field contains the lower 32 bits of the 33rd 6-byte MAC address. The content of this field is undefined until loaded by the Application after the initialization process." line.long 0x318 "MAC_ADDRESS99_HIGH,The MAC Address32 High register holds the upper 16 bits of the 33rd 6-byte MAC address of the station. If the MAC address registers are configured to be double-synchronized to the (G)MII clock domains. the synchronization is triggered.." bitfld.long 0x318 31. "AE,Address Enable When this bit is set the Address filter module uses the 33rd MAC address for perfect filtering. When this bit is reset the address filter module ignores the address for filtering. 0x0: Address is ignored 0x1: Address is enabled" "Address is ignored,Address is enabled" newline hexmask.long.word 0x318 19.--30. 1. "RESERVED_30_Y,Reserved." newline bitfld.long 0x318 16.--18. "DCS,DMA Channel Select This field contains the DMA Channel number to which an Rx packet whose DA matches the MAC Address32 content is routed." "0,1,2,3,4,5,6,7" newline hexmask.long.word 0x318 0.--15. 1. "ADDRHI,MAC Address32 [47:32] This field contains the upper 16 bits (47:32) of the 33rd 6-byte MAC address." line.long 0x31C "MAC_ADDRESS99_LOW,The MAC Address32 Low register holds the lower 16 bits of the 33rd 6-byte MAC address of the station." hexmask.long 0x31C 0.--31. 1. "ADDRLO,MAC Address32 [31:0] This field contains the lower 32 bits of the 33rd 6-byte MAC address. The content of this field is undefined until loaded by the Application after the initialization process." line.long 0x320 "MAC_ADDRESS100_HIGH,The MAC Address32 High register holds the upper 16 bits of the 33rd 6-byte MAC address of the station. If the MAC address registers are configured to be double-synchronized to the (G)MII clock domains. the synchronization is triggered.." bitfld.long 0x320 31. "AE,Address Enable When this bit is set the Address filter module uses the 33rd MAC address for perfect filtering. When this bit is reset the address filter module ignores the address for filtering. 0x0: Address is ignored 0x1: Address is enabled" "Address is ignored,Address is enabled" newline hexmask.long.word 0x320 19.--30. 1. "RESERVED_30_Y,Reserved." newline bitfld.long 0x320 16.--18. "DCS,DMA Channel Select This field contains the DMA Channel number to which an Rx packet whose DA matches the MAC Address32 content is routed." "0,1,2,3,4,5,6,7" newline hexmask.long.word 0x320 0.--15. 1. "ADDRHI,MAC Address32 [47:32] This field contains the upper 16 bits (47:32) of the 33rd 6-byte MAC address." line.long 0x324 "MAC_ADDRESS100_LOW,The MAC Address32 Low register holds the lower 16 bits of the 33rd 6-byte MAC address of the station." hexmask.long 0x324 0.--31. 1. "ADDRLO,MAC Address32 [31:0] This field contains the lower 32 bits of the 33rd 6-byte MAC address. The content of this field is undefined until loaded by the Application after the initialization process." line.long 0x328 "MAC_ADDRESS101_HIGH,The MAC Address32 High register holds the upper 16 bits of the 33rd 6-byte MAC address of the station. If the MAC address registers are configured to be double-synchronized to the (G)MII clock domains. the synchronization is triggered.." bitfld.long 0x328 31. "AE,Address Enable When this bit is set the Address filter module uses the 33rd MAC address for perfect filtering. When this bit is reset the address filter module ignores the address for filtering. 0x0: Address is ignored 0x1: Address is enabled" "Address is ignored,Address is enabled" newline hexmask.long.word 0x328 19.--30. 1. "RESERVED_30_Y,Reserved." newline bitfld.long 0x328 16.--18. "DCS,DMA Channel Select This field contains the DMA Channel number to which an Rx packet whose DA matches the MAC Address32 content is routed." "0,1,2,3,4,5,6,7" newline hexmask.long.word 0x328 0.--15. 1. "ADDRHI,MAC Address32 [47:32] This field contains the upper 16 bits (47:32) of the 33rd 6-byte MAC address." line.long 0x32C "MAC_ADDRESS101_LOW,The MAC Address32 Low register holds the lower 16 bits of the 33rd 6-byte MAC address of the station." hexmask.long 0x32C 0.--31. 1. "ADDRLO,MAC Address32 [31:0] This field contains the lower 32 bits of the 33rd 6-byte MAC address. The content of this field is undefined until loaded by the Application after the initialization process." line.long 0x330 "MAC_ADDRESS102_HIGH,The MAC Address32 High register holds the upper 16 bits of the 33rd 6-byte MAC address of the station. If the MAC address registers are configured to be double-synchronized to the (G)MII clock domains. the synchronization is triggered.." bitfld.long 0x330 31. "AE,Address Enable When this bit is set the Address filter module uses the 33rd MAC address for perfect filtering. When this bit is reset the address filter module ignores the address for filtering. 0x0: Address is ignored 0x1: Address is enabled" "Address is ignored,Address is enabled" newline hexmask.long.word 0x330 19.--30. 1. "RESERVED_30_Y,Reserved." newline bitfld.long 0x330 16.--18. "DCS,DMA Channel Select This field contains the DMA Channel number to which an Rx packet whose DA matches the MAC Address32 content is routed." "0,1,2,3,4,5,6,7" newline hexmask.long.word 0x330 0.--15. 1. "ADDRHI,MAC Address32 [47:32] This field contains the upper 16 bits (47:32) of the 33rd 6-byte MAC address." line.long 0x334 "MAC_ADDRESS102_LOW,The MAC Address32 Low register holds the lower 16 bits of the 33rd 6-byte MAC address of the station." hexmask.long 0x334 0.--31. 1. "ADDRLO,MAC Address32 [31:0] This field contains the lower 32 bits of the 33rd 6-byte MAC address. The content of this field is undefined until loaded by the Application after the initialization process." line.long 0x338 "MAC_ADDRESS103_HIGH,The MAC Address32 High register holds the upper 16 bits of the 33rd 6-byte MAC address of the station. If the MAC address registers are configured to be double-synchronized to the (G)MII clock domains. the synchronization is triggered.." bitfld.long 0x338 31. "AE,Address Enable When this bit is set the Address filter module uses the 33rd MAC address for perfect filtering. When this bit is reset the address filter module ignores the address for filtering. 0x0: Address is ignored 0x1: Address is enabled" "Address is ignored,Address is enabled" newline hexmask.long.word 0x338 19.--30. 1. "RESERVED_30_Y,Reserved." newline bitfld.long 0x338 16.--18. "DCS,DMA Channel Select This field contains the DMA Channel number to which an Rx packet whose DA matches the MAC Address32 content is routed." "0,1,2,3,4,5,6,7" newline hexmask.long.word 0x338 0.--15. 1. "ADDRHI,MAC Address32 [47:32] This field contains the upper 16 bits (47:32) of the 33rd 6-byte MAC address." line.long 0x33C "MAC_ADDRESS103_LOW,The MAC Address32 Low register holds the lower 16 bits of the 33rd 6-byte MAC address of the station." hexmask.long 0x33C 0.--31. 1. "ADDRLO,MAC Address32 [31:0] This field contains the lower 32 bits of the 33rd 6-byte MAC address. The content of this field is undefined until loaded by the Application after the initialization process." line.long 0x340 "MAC_ADDRESS104_HIGH,The MAC Address32 High register holds the upper 16 bits of the 33rd 6-byte MAC address of the station. If the MAC address registers are configured to be double-synchronized to the (G)MII clock domains. the synchronization is triggered.." bitfld.long 0x340 31. "AE,Address Enable When this bit is set the Address filter module uses the 33rd MAC address for perfect filtering. When this bit is reset the address filter module ignores the address for filtering. 0x0: Address is ignored 0x1: Address is enabled" "Address is ignored,Address is enabled" newline hexmask.long.word 0x340 19.--30. 1. "RESERVED_30_Y,Reserved." newline bitfld.long 0x340 16.--18. "DCS,DMA Channel Select This field contains the DMA Channel number to which an Rx packet whose DA matches the MAC Address32 content is routed." "0,1,2,3,4,5,6,7" newline hexmask.long.word 0x340 0.--15. 1. "ADDRHI,MAC Address32 [47:32] This field contains the upper 16 bits (47:32) of the 33rd 6-byte MAC address." line.long 0x344 "MAC_ADDRESS104_LOW,The MAC Address32 Low register holds the lower 16 bits of the 33rd 6-byte MAC address of the station." hexmask.long 0x344 0.--31. 1. "ADDRLO,MAC Address32 [31:0] This field contains the lower 32 bits of the 33rd 6-byte MAC address. The content of this field is undefined until loaded by the Application after the initialization process." line.long 0x348 "MAC_ADDRESS105_HIGH,The MAC Address32 High register holds the upper 16 bits of the 33rd 6-byte MAC address of the station. If the MAC address registers are configured to be double-synchronized to the (G)MII clock domains. the synchronization is triggered.." bitfld.long 0x348 31. "AE,Address Enable When this bit is set the Address filter module uses the 33rd MAC address for perfect filtering. When this bit is reset the address filter module ignores the address for filtering. 0x0: Address is ignored 0x1: Address is enabled" "Address is ignored,Address is enabled" newline hexmask.long.word 0x348 19.--30. 1. "RESERVED_30_Y,Reserved." newline bitfld.long 0x348 16.--18. "DCS,DMA Channel Select This field contains the DMA Channel number to which an Rx packet whose DA matches the MAC Address32 content is routed." "0,1,2,3,4,5,6,7" newline hexmask.long.word 0x348 0.--15. 1. "ADDRHI,MAC Address32 [47:32] This field contains the upper 16 bits (47:32) of the 33rd 6-byte MAC address." line.long 0x34C "MAC_ADDRESS105_LOW,The MAC Address32 Low register holds the lower 16 bits of the 33rd 6-byte MAC address of the station." hexmask.long 0x34C 0.--31. 1. "ADDRLO,MAC Address32 [31:0] This field contains the lower 32 bits of the 33rd 6-byte MAC address. The content of this field is undefined until loaded by the Application after the initialization process." line.long 0x350 "MAC_ADDRESS106_HIGH,The MAC Address32 High register holds the upper 16 bits of the 33rd 6-byte MAC address of the station. If the MAC address registers are configured to be double-synchronized to the (G)MII clock domains. the synchronization is triggered.." bitfld.long 0x350 31. "AE,Address Enable When this bit is set the Address filter module uses the 33rd MAC address for perfect filtering. When this bit is reset the address filter module ignores the address for filtering. 0x0: Address is ignored 0x1: Address is enabled" "Address is ignored,Address is enabled" newline hexmask.long.word 0x350 19.--30. 1. "RESERVED_30_Y,Reserved." newline bitfld.long 0x350 16.--18. "DCS,DMA Channel Select This field contains the DMA Channel number to which an Rx packet whose DA matches the MAC Address32 content is routed." "0,1,2,3,4,5,6,7" newline hexmask.long.word 0x350 0.--15. 1. "ADDRHI,MAC Address32 [47:32] This field contains the upper 16 bits (47:32) of the 33rd 6-byte MAC address." line.long 0x354 "MAC_ADDRESS106_LOW,The MAC Address32 Low register holds the lower 16 bits of the 33rd 6-byte MAC address of the station." hexmask.long 0x354 0.--31. 1. "ADDRLO,MAC Address32 [31:0] This field contains the lower 32 bits of the 33rd 6-byte MAC address. The content of this field is undefined until loaded by the Application after the initialization process." line.long 0x358 "MAC_ADDRESS107_HIGH,The MAC Address32 High register holds the upper 16 bits of the 33rd 6-byte MAC address of the station. If the MAC address registers are configured to be double-synchronized to the (G)MII clock domains. the synchronization is triggered.." bitfld.long 0x358 31. "AE,Address Enable When this bit is set the Address filter module uses the 33rd MAC address for perfect filtering. When this bit is reset the address filter module ignores the address for filtering. 0x0: Address is ignored 0x1: Address is enabled" "Address is ignored,Address is enabled" newline hexmask.long.word 0x358 19.--30. 1. "RESERVED_30_Y,Reserved." newline bitfld.long 0x358 16.--18. "DCS,DMA Channel Select This field contains the DMA Channel number to which an Rx packet whose DA matches the MAC Address32 content is routed." "0,1,2,3,4,5,6,7" newline hexmask.long.word 0x358 0.--15. 1. "ADDRHI,MAC Address32 [47:32] This field contains the upper 16 bits (47:32) of the 33rd 6-byte MAC address." line.long 0x35C "MAC_ADDRESS107_LOW,The MAC Address32 Low register holds the lower 16 bits of the 33rd 6-byte MAC address of the station." hexmask.long 0x35C 0.--31. 1. "ADDRLO,MAC Address32 [31:0] This field contains the lower 32 bits of the 33rd 6-byte MAC address. The content of this field is undefined until loaded by the Application after the initialization process." line.long 0x360 "MAC_ADDRESS108_HIGH,The MAC Address32 High register holds the upper 16 bits of the 33rd 6-byte MAC address of the station. If the MAC address registers are configured to be double-synchronized to the (G)MII clock domains. the synchronization is triggered.." bitfld.long 0x360 31. "AE,Address Enable When this bit is set the Address filter module uses the 33rd MAC address for perfect filtering. When this bit is reset the address filter module ignores the address for filtering. 0x0: Address is ignored 0x1: Address is enabled" "Address is ignored,Address is enabled" newline hexmask.long.word 0x360 19.--30. 1. "RESERVED_30_Y,Reserved." newline bitfld.long 0x360 16.--18. "DCS,DMA Channel Select This field contains the DMA Channel number to which an Rx packet whose DA matches the MAC Address32 content is routed." "0,1,2,3,4,5,6,7" newline hexmask.long.word 0x360 0.--15. 1. "ADDRHI,MAC Address32 [47:32] This field contains the upper 16 bits (47:32) of the 33rd 6-byte MAC address." line.long 0x364 "MAC_ADDRESS108_LOW,The MAC Address32 Low register holds the lower 16 bits of the 33rd 6-byte MAC address of the station." hexmask.long 0x364 0.--31. 1. "ADDRLO,MAC Address32 [31:0] This field contains the lower 32 bits of the 33rd 6-byte MAC address. The content of this field is undefined until loaded by the Application after the initialization process." line.long 0x368 "MAC_ADDRESS109_HIGH,The MAC Address32 High register holds the upper 16 bits of the 33rd 6-byte MAC address of the station. If the MAC address registers are configured to be double-synchronized to the (G)MII clock domains. the synchronization is triggered.." bitfld.long 0x368 31. "AE,Address Enable When this bit is set the Address filter module uses the 33rd MAC address for perfect filtering. When this bit is reset the address filter module ignores the address for filtering. 0x0: Address is ignored 0x1: Address is enabled" "Address is ignored,Address is enabled" newline hexmask.long.word 0x368 19.--30. 1. "RESERVED_30_Y,Reserved." newline bitfld.long 0x368 16.--18. "DCS,DMA Channel Select This field contains the DMA Channel number to which an Rx packet whose DA matches the MAC Address32 content is routed." "0,1,2,3,4,5,6,7" newline hexmask.long.word 0x368 0.--15. 1. "ADDRHI,MAC Address32 [47:32] This field contains the upper 16 bits (47:32) of the 33rd 6-byte MAC address." line.long 0x36C "MAC_ADDRESS109_LOW,The MAC Address32 Low register holds the lower 16 bits of the 33rd 6-byte MAC address of the station." hexmask.long 0x36C 0.--31. 1. "ADDRLO,MAC Address32 [31:0] This field contains the lower 32 bits of the 33rd 6-byte MAC address. The content of this field is undefined until loaded by the Application after the initialization process." line.long 0x370 "MAC_ADDRESS110_HIGH,The MAC Address32 High register holds the upper 16 bits of the 33rd 6-byte MAC address of the station. If the MAC address registers are configured to be double-synchronized to the (G)MII clock domains. the synchronization is triggered.." bitfld.long 0x370 31. "AE,Address Enable When this bit is set the Address filter module uses the 33rd MAC address for perfect filtering. When this bit is reset the address filter module ignores the address for filtering. 0x0: Address is ignored 0x1: Address is enabled" "Address is ignored,Address is enabled" newline hexmask.long.word 0x370 19.--30. 1. "RESERVED_30_Y,Reserved." newline bitfld.long 0x370 16.--18. "DCS,DMA Channel Select This field contains the DMA Channel number to which an Rx packet whose DA matches the MAC Address32 content is routed." "0,1,2,3,4,5,6,7" newline hexmask.long.word 0x370 0.--15. 1. "ADDRHI,MAC Address32 [47:32] This field contains the upper 16 bits (47:32) of the 33rd 6-byte MAC address." line.long 0x374 "MAC_ADDRESS110_LOW,The MAC Address32 Low register holds the lower 16 bits of the 33rd 6-byte MAC address of the station." hexmask.long 0x374 0.--31. 1. "ADDRLO,MAC Address32 [31:0] This field contains the lower 32 bits of the 33rd 6-byte MAC address. The content of this field is undefined until loaded by the Application after the initialization process." line.long 0x378 "MAC_ADDRESS111_HIGH,The MAC Address32 High register holds the upper 16 bits of the 33rd 6-byte MAC address of the station. If the MAC address registers are configured to be double-synchronized to the (G)MII clock domains. the synchronization is triggered.." bitfld.long 0x378 31. "AE,Address Enable When this bit is set the Address filter module uses the 33rd MAC address for perfect filtering. When this bit is reset the address filter module ignores the address for filtering. 0x0: Address is ignored 0x1: Address is enabled" "Address is ignored,Address is enabled" newline hexmask.long.word 0x378 19.--30. 1. "RESERVED_30_Y,Reserved." newline bitfld.long 0x378 16.--18. "DCS,DMA Channel Select This field contains the DMA Channel number to which an Rx packet whose DA matches the MAC Address32 content is routed." "0,1,2,3,4,5,6,7" newline hexmask.long.word 0x378 0.--15. 1. "ADDRHI,MAC Address32 [47:32] This field contains the upper 16 bits (47:32) of the 33rd 6-byte MAC address." line.long 0x37C "MAC_ADDRESS111_LOW,The MAC Address32 Low register holds the lower 16 bits of the 33rd 6-byte MAC address of the station." hexmask.long 0x37C 0.--31. 1. "ADDRLO,MAC Address32 [31:0] This field contains the lower 32 bits of the 33rd 6-byte MAC address. The content of this field is undefined until loaded by the Application after the initialization process." line.long 0x380 "MAC_ADDRESS112_HIGH,The MAC Address32 High register holds the upper 16 bits of the 33rd 6-byte MAC address of the station. If the MAC address registers are configured to be double-synchronized to the (G)MII clock domains. the synchronization is triggered.." bitfld.long 0x380 31. "AE,Address Enable When this bit is set the Address filter module uses the 33rd MAC address for perfect filtering. When this bit is reset the address filter module ignores the address for filtering. 0x0: Address is ignored 0x1: Address is enabled" "Address is ignored,Address is enabled" newline hexmask.long.word 0x380 19.--30. 1. "RESERVED_30_Y,Reserved." newline bitfld.long 0x380 16.--18. "DCS,DMA Channel Select This field contains the DMA Channel number to which an Rx packet whose DA matches the MAC Address32 content is routed." "0,1,2,3,4,5,6,7" newline hexmask.long.word 0x380 0.--15. 1. "ADDRHI,MAC Address32 [47:32] This field contains the upper 16 bits (47:32) of the 33rd 6-byte MAC address." line.long 0x384 "MAC_ADDRESS112_LOW,The MAC Address32 Low register holds the lower 16 bits of the 33rd 6-byte MAC address of the station." hexmask.long 0x384 0.--31. 1. "ADDRLO,MAC Address32 [31:0] This field contains the lower 32 bits of the 33rd 6-byte MAC address. The content of this field is undefined until loaded by the Application after the initialization process." line.long 0x388 "MAC_ADDRESS113_HIGH,The MAC Address32 High register holds the upper 16 bits of the 33rd 6-byte MAC address of the station. If the MAC address registers are configured to be double-synchronized to the (G)MII clock domains. the synchronization is triggered.." bitfld.long 0x388 31. "AE,Address Enable When this bit is set the Address filter module uses the 33rd MAC address for perfect filtering. When this bit is reset the address filter module ignores the address for filtering. 0x0: Address is ignored 0x1: Address is enabled" "Address is ignored,Address is enabled" newline hexmask.long.word 0x388 19.--30. 1. "RESERVED_30_Y,Reserved." newline bitfld.long 0x388 16.--18. "DCS,DMA Channel Select This field contains the DMA Channel number to which an Rx packet whose DA matches the MAC Address32 content is routed." "0,1,2,3,4,5,6,7" newline hexmask.long.word 0x388 0.--15. 1. "ADDRHI,MAC Address32 [47:32] This field contains the upper 16 bits (47:32) of the 33rd 6-byte MAC address." line.long 0x38C "MAC_ADDRESS113_LOW,The MAC Address32 Low register holds the lower 16 bits of the 33rd 6-byte MAC address of the station." hexmask.long 0x38C 0.--31. 1. "ADDRLO,MAC Address32 [31:0] This field contains the lower 32 bits of the 33rd 6-byte MAC address. The content of this field is undefined until loaded by the Application after the initialization process." line.long 0x390 "MAC_ADDRESS114_HIGH,The MAC Address32 High register holds the upper 16 bits of the 33rd 6-byte MAC address of the station. If the MAC address registers are configured to be double-synchronized to the (G)MII clock domains. the synchronization is triggered.." bitfld.long 0x390 31. "AE,Address Enable When this bit is set the Address filter module uses the 33rd MAC address for perfect filtering. When this bit is reset the address filter module ignores the address for filtering. 0x0: Address is ignored 0x1: Address is enabled" "Address is ignored,Address is enabled" newline hexmask.long.word 0x390 19.--30. 1. "RESERVED_30_Y,Reserved." newline bitfld.long 0x390 16.--18. "DCS,DMA Channel Select This field contains the DMA Channel number to which an Rx packet whose DA matches the MAC Address32 content is routed." "0,1,2,3,4,5,6,7" newline hexmask.long.word 0x390 0.--15. 1. "ADDRHI,MAC Address32 [47:32] This field contains the upper 16 bits (47:32) of the 33rd 6-byte MAC address." line.long 0x394 "MAC_ADDRESS114_LOW,The MAC Address32 Low register holds the lower 16 bits of the 33rd 6-byte MAC address of the station." hexmask.long 0x394 0.--31. 1. "ADDRLO,MAC Address32 [31:0] This field contains the lower 32 bits of the 33rd 6-byte MAC address. The content of this field is undefined until loaded by the Application after the initialization process." line.long 0x398 "MAC_ADDRESS115_HIGH,The MAC Address32 High register holds the upper 16 bits of the 33rd 6-byte MAC address of the station. If the MAC address registers are configured to be double-synchronized to the (G)MII clock domains. the synchronization is triggered.." bitfld.long 0x398 31. "AE,Address Enable When this bit is set the Address filter module uses the 33rd MAC address for perfect filtering. When this bit is reset the address filter module ignores the address for filtering. 0x0: Address is ignored 0x1: Address is enabled" "Address is ignored,Address is enabled" newline hexmask.long.word 0x398 19.--30. 1. "RESERVED_30_Y,Reserved." newline bitfld.long 0x398 16.--18. "DCS,DMA Channel Select This field contains the DMA Channel number to which an Rx packet whose DA matches the MAC Address32 content is routed." "0,1,2,3,4,5,6,7" newline hexmask.long.word 0x398 0.--15. 1. "ADDRHI,MAC Address32 [47:32] This field contains the upper 16 bits (47:32) of the 33rd 6-byte MAC address." line.long 0x39C "MAC_ADDRESS115_LOW,The MAC Address32 Low register holds the lower 16 bits of the 33rd 6-byte MAC address of the station." hexmask.long 0x39C 0.--31. 1. "ADDRLO,MAC Address32 [31:0] This field contains the lower 32 bits of the 33rd 6-byte MAC address. The content of this field is undefined until loaded by the Application after the initialization process." line.long 0x3A0 "MAC_ADDRESS116_HIGH,The MAC Address32 High register holds the upper 16 bits of the 33rd 6-byte MAC address of the station. If the MAC address registers are configured to be double-synchronized to the (G)MII clock domains. the synchronization is triggered.." bitfld.long 0x3A0 31. "AE,Address Enable When this bit is set the Address filter module uses the 33rd MAC address for perfect filtering. When this bit is reset the address filter module ignores the address for filtering. 0x0: Address is ignored 0x1: Address is enabled" "Address is ignored,Address is enabled" newline hexmask.long.word 0x3A0 19.--30. 1. "RESERVED_30_Y,Reserved." newline bitfld.long 0x3A0 16.--18. "DCS,DMA Channel Select This field contains the DMA Channel number to which an Rx packet whose DA matches the MAC Address32 content is routed." "0,1,2,3,4,5,6,7" newline hexmask.long.word 0x3A0 0.--15. 1. "ADDRHI,MAC Address32 [47:32] This field contains the upper 16 bits (47:32) of the 33rd 6-byte MAC address." line.long 0x3A4 "MAC_ADDRESS116_LOW,The MAC Address32 Low register holds the lower 16 bits of the 33rd 6-byte MAC address of the station." hexmask.long 0x3A4 0.--31. 1. "ADDRLO,MAC Address32 [31:0] This field contains the lower 32 bits of the 33rd 6-byte MAC address. The content of this field is undefined until loaded by the Application after the initialization process." line.long 0x3A8 "MAC_ADDRESS117_HIGH,The MAC Address32 High register holds the upper 16 bits of the 33rd 6-byte MAC address of the station. If the MAC address registers are configured to be double-synchronized to the (G)MII clock domains. the synchronization is triggered.." bitfld.long 0x3A8 31. "AE,Address Enable When this bit is set the Address filter module uses the 33rd MAC address for perfect filtering. When this bit is reset the address filter module ignores the address for filtering. 0x0: Address is ignored 0x1: Address is enabled" "Address is ignored,Address is enabled" newline hexmask.long.word 0x3A8 19.--30. 1. "RESERVED_30_Y,Reserved." newline bitfld.long 0x3A8 16.--18. "DCS,DMA Channel Select This field contains the DMA Channel number to which an Rx packet whose DA matches the MAC Address32 content is routed." "0,1,2,3,4,5,6,7" newline hexmask.long.word 0x3A8 0.--15. 1. "ADDRHI,MAC Address32 [47:32] This field contains the upper 16 bits (47:32) of the 33rd 6-byte MAC address." line.long 0x3AC "MAC_ADDRESS117_LOW,The MAC Address32 Low register holds the lower 16 bits of the 33rd 6-byte MAC address of the station." hexmask.long 0x3AC 0.--31. 1. "ADDRLO,MAC Address32 [31:0] This field contains the lower 32 bits of the 33rd 6-byte MAC address. The content of this field is undefined until loaded by the Application after the initialization process." line.long 0x3B0 "MAC_ADDRESS118_HIGH,The MAC Address32 High register holds the upper 16 bits of the 33rd 6-byte MAC address of the station. If the MAC address registers are configured to be double-synchronized to the (G)MII clock domains. the synchronization is triggered.." bitfld.long 0x3B0 31. "AE,Address Enable When this bit is set the Address filter module uses the 33rd MAC address for perfect filtering. When this bit is reset the address filter module ignores the address for filtering. 0x0: Address is ignored 0x1: Address is enabled" "Address is ignored,Address is enabled" newline hexmask.long.word 0x3B0 19.--30. 1. "RESERVED_30_Y,Reserved." newline bitfld.long 0x3B0 16.--18. "DCS,DMA Channel Select This field contains the DMA Channel number to which an Rx packet whose DA matches the MAC Address32 content is routed." "0,1,2,3,4,5,6,7" newline hexmask.long.word 0x3B0 0.--15. 1. "ADDRHI,MAC Address32 [47:32] This field contains the upper 16 bits (47:32) of the 33rd 6-byte MAC address." line.long 0x3B4 "MAC_ADDRESS118_LOW,The MAC Address32 Low register holds the lower 16 bits of the 33rd 6-byte MAC address of the station." hexmask.long 0x3B4 0.--31. 1. "ADDRLO,MAC Address32 [31:0] This field contains the lower 32 bits of the 33rd 6-byte MAC address. The content of this field is undefined until loaded by the Application after the initialization process." line.long 0x3B8 "MAC_ADDRESS119_HIGH,The MAC Address32 High register holds the upper 16 bits of the 33rd 6-byte MAC address of the station. If the MAC address registers are configured to be double-synchronized to the (G)MII clock domains. the synchronization is triggered.." bitfld.long 0x3B8 31. "AE,Address Enable When this bit is set the Address filter module uses the 33rd MAC address for perfect filtering. When this bit is reset the address filter module ignores the address for filtering. 0x0: Address is ignored 0x1: Address is enabled" "Address is ignored,Address is enabled" newline hexmask.long.word 0x3B8 19.--30. 1. "RESERVED_30_Y,Reserved." newline bitfld.long 0x3B8 16.--18. "DCS,DMA Channel Select This field contains the DMA Channel number to which an Rx packet whose DA matches the MAC Address32 content is routed." "0,1,2,3,4,5,6,7" newline hexmask.long.word 0x3B8 0.--15. 1. "ADDRHI,MAC Address32 [47:32] This field contains the upper 16 bits (47:32) of the 33rd 6-byte MAC address." line.long 0x3BC "MAC_ADDRESS119_LOW,The MAC Address32 Low register holds the lower 16 bits of the 33rd 6-byte MAC address of the station." hexmask.long 0x3BC 0.--31. 1. "ADDRLO,MAC Address32 [31:0] This field contains the lower 32 bits of the 33rd 6-byte MAC address. The content of this field is undefined until loaded by the Application after the initialization process." line.long 0x3C0 "MAC_ADDRESS120_HIGH,The MAC Address32 High register holds the upper 16 bits of the 33rd 6-byte MAC address of the station. If the MAC address registers are configured to be double-synchronized to the (G)MII clock domains. the synchronization is triggered.." bitfld.long 0x3C0 31. "AE,Address Enable When this bit is set the Address filter module uses the 33rd MAC address for perfect filtering. When this bit is reset the address filter module ignores the address for filtering. 0x0: Address is ignored 0x1: Address is enabled" "Address is ignored,Address is enabled" newline hexmask.long.word 0x3C0 19.--30. 1. "RESERVED_30_Y,Reserved." newline bitfld.long 0x3C0 16.--18. "DCS,DMA Channel Select This field contains the DMA Channel number to which an Rx packet whose DA matches the MAC Address32 content is routed." "0,1,2,3,4,5,6,7" newline hexmask.long.word 0x3C0 0.--15. 1. "ADDRHI,MAC Address32 [47:32] This field contains the upper 16 bits (47:32) of the 33rd 6-byte MAC address." line.long 0x3C4 "MAC_ADDRESS120_LOW,The MAC Address32 Low register holds the lower 16 bits of the 33rd 6-byte MAC address of the station." hexmask.long 0x3C4 0.--31. 1. "ADDRLO,MAC Address32 [31:0] This field contains the lower 32 bits of the 33rd 6-byte MAC address. The content of this field is undefined until loaded by the Application after the initialization process." line.long 0x3C8 "MAC_ADDRESS121_HIGH,The MAC Address32 High register holds the upper 16 bits of the 33rd 6-byte MAC address of the station. If the MAC address registers are configured to be double-synchronized to the (G)MII clock domains. the synchronization is triggered.." bitfld.long 0x3C8 31. "AE,Address Enable When this bit is set the Address filter module uses the 33rd MAC address for perfect filtering. When this bit is reset the address filter module ignores the address for filtering. 0x0: Address is ignored 0x1: Address is enabled" "Address is ignored,Address is enabled" newline hexmask.long.word 0x3C8 19.--30. 1. "RESERVED_30_Y,Reserved." newline bitfld.long 0x3C8 16.--18. "DCS,DMA Channel Select This field contains the DMA Channel number to which an Rx packet whose DA matches the MAC Address32 content is routed." "0,1,2,3,4,5,6,7" newline hexmask.long.word 0x3C8 0.--15. 1. "ADDRHI,MAC Address32 [47:32] This field contains the upper 16 bits (47:32) of the 33rd 6-byte MAC address." line.long 0x3CC "MAC_ADDRESS121_LOW,The MAC Address32 Low register holds the lower 16 bits of the 33rd 6-byte MAC address of the station." hexmask.long 0x3CC 0.--31. 1. "ADDRLO,MAC Address32 [31:0] This field contains the lower 32 bits of the 33rd 6-byte MAC address. The content of this field is undefined until loaded by the Application after the initialization process." line.long 0x3D0 "MAC_ADDRESS122_HIGH,The MAC Address32 High register holds the upper 16 bits of the 33rd 6-byte MAC address of the station. If the MAC address registers are configured to be double-synchronized to the (G)MII clock domains. the synchronization is triggered.." bitfld.long 0x3D0 31. "AE,Address Enable When this bit is set the Address filter module uses the 33rd MAC address for perfect filtering. When this bit is reset the address filter module ignores the address for filtering. 0x0: Address is ignored 0x1: Address is enabled" "Address is ignored,Address is enabled" newline hexmask.long.word 0x3D0 19.--30. 1. "RESERVED_30_Y,Reserved." newline bitfld.long 0x3D0 16.--18. "DCS,DMA Channel Select This field contains the DMA Channel number to which an Rx packet whose DA matches the MAC Address32 content is routed." "0,1,2,3,4,5,6,7" newline hexmask.long.word 0x3D0 0.--15. 1. "ADDRHI,MAC Address32 [47:32] This field contains the upper 16 bits (47:32) of the 33rd 6-byte MAC address." line.long 0x3D4 "MAC_ADDRESS122_LOW,The MAC Address32 Low register holds the lower 16 bits of the 33rd 6-byte MAC address of the station." hexmask.long 0x3D4 0.--31. 1. "ADDRLO,MAC Address32 [31:0] This field contains the lower 32 bits of the 33rd 6-byte MAC address. The content of this field is undefined until loaded by the Application after the initialization process." line.long 0x3D8 "MAC_ADDRESS123_HIGH,The MAC Address32 High register holds the upper 16 bits of the 33rd 6-byte MAC address of the station. If the MAC address registers are configured to be double-synchronized to the (G)MII clock domains. the synchronization is triggered.." bitfld.long 0x3D8 31. "AE,Address Enable When this bit is set the Address filter module uses the 33rd MAC address for perfect filtering. When this bit is reset the address filter module ignores the address for filtering. 0x0: Address is ignored 0x1: Address is enabled" "Address is ignored,Address is enabled" newline hexmask.long.word 0x3D8 19.--30. 1. "RESERVED_30_Y,Reserved." newline bitfld.long 0x3D8 16.--18. "DCS,DMA Channel Select This field contains the DMA Channel number to which an Rx packet whose DA matches the MAC Address32 content is routed." "0,1,2,3,4,5,6,7" newline hexmask.long.word 0x3D8 0.--15. 1. "ADDRHI,MAC Address32 [47:32] This field contains the upper 16 bits (47:32) of the 33rd 6-byte MAC address." line.long 0x3DC "MAC_ADDRESS123_LOW,The MAC Address32 Low register holds the lower 16 bits of the 33rd 6-byte MAC address of the station." hexmask.long 0x3DC 0.--31. 1. "ADDRLO,MAC Address32 [31:0] This field contains the lower 32 bits of the 33rd 6-byte MAC address. The content of this field is undefined until loaded by the Application after the initialization process." line.long 0x3E0 "MAC_ADDRESS124_HIGH,The MAC Address32 High register holds the upper 16 bits of the 33rd 6-byte MAC address of the station. If the MAC address registers are configured to be double-synchronized to the (G)MII clock domains. the synchronization is triggered.." bitfld.long 0x3E0 31. "AE,Address Enable When this bit is set the Address filter module uses the 33rd MAC address for perfect filtering. When this bit is reset the address filter module ignores the address for filtering. 0x0: Address is ignored 0x1: Address is enabled" "Address is ignored,Address is enabled" newline hexmask.long.word 0x3E0 19.--30. 1. "RESERVED_30_Y,Reserved." newline bitfld.long 0x3E0 16.--18. "DCS,DMA Channel Select This field contains the DMA Channel number to which an Rx packet whose DA matches the MAC Address32 content is routed." "0,1,2,3,4,5,6,7" newline hexmask.long.word 0x3E0 0.--15. 1. "ADDRHI,MAC Address32 [47:32] This field contains the upper 16 bits (47:32) of the 33rd 6-byte MAC address." line.long 0x3E4 "MAC_ADDRESS124_LOW,The MAC Address32 Low register holds the lower 16 bits of the 33rd 6-byte MAC address of the station." hexmask.long 0x3E4 0.--31. 1. "ADDRLO,MAC Address32 [31:0] This field contains the lower 32 bits of the 33rd 6-byte MAC address. The content of this field is undefined until loaded by the Application after the initialization process." line.long 0x3E8 "MAC_ADDRESS125_HIGH,The MAC Address32 High register holds the upper 16 bits of the 33rd 6-byte MAC address of the station. If the MAC address registers are configured to be double-synchronized to the (G)MII clock domains. the synchronization is triggered.." bitfld.long 0x3E8 31. "AE,Address Enable When this bit is set the Address filter module uses the 33rd MAC address for perfect filtering. When this bit is reset the address filter module ignores the address for filtering. 0x0: Address is ignored 0x1: Address is enabled" "Address is ignored,Address is enabled" newline hexmask.long.word 0x3E8 19.--30. 1. "RESERVED_30_Y,Reserved." newline bitfld.long 0x3E8 16.--18. "DCS,DMA Channel Select This field contains the DMA Channel number to which an Rx packet whose DA matches the MAC Address32 content is routed." "0,1,2,3,4,5,6,7" newline hexmask.long.word 0x3E8 0.--15. 1. "ADDRHI,MAC Address32 [47:32] This field contains the upper 16 bits (47:32) of the 33rd 6-byte MAC address." line.long 0x3EC "MAC_ADDRESS125_LOW,The MAC Address32 Low register holds the lower 16 bits of the 33rd 6-byte MAC address of the station." hexmask.long 0x3EC 0.--31. 1. "ADDRLO,MAC Address32 [31:0] This field contains the lower 32 bits of the 33rd 6-byte MAC address. The content of this field is undefined until loaded by the Application after the initialization process." line.long 0x3F0 "MAC_ADDRESS126_HIGH,The MAC Address32 High register holds the upper 16 bits of the 33rd 6-byte MAC address of the station. If the MAC address registers are configured to be double-synchronized to the (G)MII clock domains. the synchronization is triggered.." bitfld.long 0x3F0 31. "AE,Address Enable When this bit is set the Address filter module uses the 33rd MAC address for perfect filtering. When this bit is reset the address filter module ignores the address for filtering. 0x0: Address is ignored 0x1: Address is enabled" "Address is ignored,Address is enabled" newline hexmask.long.word 0x3F0 19.--30. 1. "RESERVED_30_Y,Reserved." newline bitfld.long 0x3F0 16.--18. "DCS,DMA Channel Select This field contains the DMA Channel number to which an Rx packet whose DA matches the MAC Address32 content is routed." "0,1,2,3,4,5,6,7" newline hexmask.long.word 0x3F0 0.--15. 1. "ADDRHI,MAC Address32 [47:32] This field contains the upper 16 bits (47:32) of the 33rd 6-byte MAC address." line.long 0x3F4 "MAC_ADDRESS126_LOW,The MAC Address32 Low register holds the lower 16 bits of the 33rd 6-byte MAC address of the station." hexmask.long 0x3F4 0.--31. 1. "ADDRLO,MAC Address32 [31:0] This field contains the lower 32 bits of the 33rd 6-byte MAC address. The content of this field is undefined until loaded by the Application after the initialization process." line.long 0x3F8 "MAC_ADDRESS127_HIGH,The MAC Address32 High register holds the upper 16 bits of the 33rd 6-byte MAC address of the station. If the MAC address registers are configured to be double-synchronized to the (G)MII clock domains. the synchronization is triggered.." bitfld.long 0x3F8 31. "AE,Address Enable When this bit is set the Address filter module uses the 33rd MAC address for perfect filtering. When this bit is reset the address filter module ignores the address for filtering. 0x0: Address is ignored 0x1: Address is enabled" "Address is ignored,Address is enabled" newline hexmask.long.word 0x3F8 19.--30. 1. "RESERVED_30_Y,Reserved." newline bitfld.long 0x3F8 16.--18. "DCS,DMA Channel Select This field contains the DMA Channel number to which an Rx packet whose DA matches the MAC Address32 content is routed." "0,1,2,3,4,5,6,7" newline hexmask.long.word 0x3F8 0.--15. 1. "ADDRHI,MAC Address32 [47:32] This field contains the upper 16 bits (47:32) of the 33rd 6-byte MAC address." line.long 0x3FC "MAC_ADDRESS127_LOW,The MAC Address32 Low register holds the lower 16 bits of the 33rd 6-byte MAC address of the station." hexmask.long 0x3FC 0.--31. 1. "ADDRLO,MAC Address32 [31:0] This field contains the lower 32 bits of the 33rd 6-byte MAC address. The content of this field is undefined until loaded by the Application after the initialization process." line.long 0x400 "MMC_CONTROL,This register establishes the operating mode of MMC." hexmask.long.tbyte 0x400 9.--31. 1. "RESERVED_31_9,Reserved." newline bitfld.long 0x400 8. "UCDBC,Update MMC Counters for Dropped Broadcast Packets Note: The CNTRST bit has a higher priority than the CNTPRST bit. Therefore when the software tries to set both bits in the same write cycle all counters are cleared and the CNTPRST bit is not set." "Update MMC Counters for Dropped Broadcast..,Update MMC Counters for Dropped Broadcast.." newline rbitfld.long 0x400 6.--7. "RESERVED_7_6,Reserved." "0,1,2,3" newline bitfld.long 0x400 5. "CNTPRSTLVL,Full-Half Preset When this bit is low and the CNTPRST bit is set all MMC counters get preset to almost-half value. All octet counters get preset to 0x7FFF_F800 (Half 2KBytes) and all packet-counters gets preset to 0x7FFF_FFF0 (Half 16). When.." "Full-Half Preset is disabled,Full-Half Preset is enabled" newline bitfld.long 0x400 4. "CNTPRST,Counters Preset When this bit is set all counters are initialized or preset to almost full or almost half according to the CNTPRSTLVL bit. This bit is cleared automatically after 1 clock cycle. This bit along with the CNTPRSTLVL bit is useful.." "Counters Preset is disabled,Counters Preset is enabled" newline bitfld.long 0x400 3. "CNTFREEZ,MMC Counter Freeze When this bit is set it freezes all MMC counters to their current value. Until this bit is reset to 0 no MMC counter is updated because of any transmitted or received packet. If any MMC counter is read with the Reset on Read.." "MMC Counter Freeze is disabled,MMC Counter Freeze is enabled" newline bitfld.long 0x400 2. "RSTONRD,Reset on Read When this bit is set the MMC counters are reset to zero after Read (self-clearing after reset). The counters are cleared when the least significant byte lane (Bits[7:0]) is read. 0x0: Reset on Read is disabled 0x1: Reset on Read is.." "Reset on Read is disabled,Reset on Read is enabled" newline bitfld.long 0x400 1. "CNTSTOPRO,Counter Stop Rollover When this bit is set the counter does not roll over to zero after reaching the maximum value. 0x0: Counter Stop Rollover is disabled 0x1: Counter Stop Rollover is enabled" "Counter Stop Rollover is disabled,Counter Stop Rollover is enabled" newline bitfld.long 0x400 0. "CNTRST,Counters Reset When this bit is set all counters are reset. This bit is cleared automatically after 1 clock cycle. Access restriction applies. Self-cleared. Setting 0 clears. Setting 1 sets. 0x0: Counters are not reset 0x1: All counters are reset" "Counters are not reset,All counters are reset" rgroup.long 0x704++0x7 line.long 0x0 "MMC_RX_INTERRUPT,This register maintains the interrupts generated from all Receive statistics counters. The MMC Receive Interrupt register maintains the interrupts that are generated when the following occur: - Receive statistic counters reach half of.." hexmask.long.byte 0x0 28.--31. 1. "RESERVED_31_28,Reserved." newline bitfld.long 0x0 27. "RXLPITRCIS,MMC Receive LPI transition counter interrupt status This bit is set when the Rx_LPI_Tran_Cntr counter reaches half of the maximum value or the maximum value. Access restriction applies. Clears on read. Self-set to 1 on internal event. 0x1: MMC.." "MMC Receive LPI transition Counter Interrupt..,MMC Receive LPI transition Counter Interrupt.." newline bitfld.long 0x0 26. "RXLPIUSCIS,MMC Receive LPI microsecond counter interrupt status This bit is set when the Rx_LPI_USEC_Cntr counter reaches half of the maximum value or the maximum value. Access restriction applies. Clears on read. Self-set to 1 on internal event. 0x1:.." "MMC Receive LPI microsecond Counter Interrupt..,MMC Receive LPI microsecond Counter Interrupt.." newline bitfld.long 0x0 25. "RXCTRLPIS,MMC Receive Control Packet Counter Interrupt Status This bit is set when the rxctrlpackets_g counter reaches half of the maximum value or the maximum value. Access restriction applies. Clears on read. Self-set to 1 on internal event. 0x1: MMC.." "MMC Receive Control Packet Counter Interrupt..,MMC Receive Control Packet Counter Interrupt.." newline bitfld.long 0x0 24. "RXRCVERRPIS,MMC Receive Error Packet Counter Interrupt Status This bit is set when the rxrcverror counter reaches half of the maximum value or the maximum value. Access restriction applies. Clears on read. Self-set to 1 on internal event. 0x1: MMC.." "MMC Receive Error Packet Counter Interrupt..,MMC Receive Error Packet Counter Interrupt.." newline bitfld.long 0x0 23. "RXWDOGPIS,MMC Receive Watchdog Error Packet Counter Interrupt Status This bit is set when the rxwatchdog error counter reaches half of the maximum value or the maximum value. Access restriction applies. Clears on read. Self-set to 1 on internal event." "MMC Receive Watchdog Error Packet Counter..,MMC Receive Watchdog Error Packet Counter.." newline bitfld.long 0x0 22. "RXVLANGBPIS,MMC Receive VLAN Good Bad Packet Counter Interrupt Status This bit is set when the rxvlanpackets_gb counter reaches half of the maximum value or the maximum value. Access restriction applies. Clears on read. Self-set to 1 on internal event." "MMC Receive VLAN Good Bad Packet Counter..,MMC Receive VLAN Good Bad Packet Counter.." newline bitfld.long 0x0 21. "RXFOVPIS,MMC Receive FIFO Overflow Packet Counter Interrupt Status This bit is set when the rxfifooverflow counter reaches half of the maximum value or the maximum value. Access restriction applies. Clears on read. Self-set to 1 on internal event. 0x1:.." "MMC Receive FIFO Overflow Packet Counter..,MMC Receive FIFO Overflow Packet Counter.." newline bitfld.long 0x0 20. "RXPAUSPIS,MMC Receive Pause Packet Counter Interrupt Status This bit is set when the rxpausepackets counter reaches half of the maximum value or the maximum value. Access restriction applies. Clears on read. Self-set to 1 on internal event. 0x1: MMC.." "MMC Receive Pause Packet Counter Interrupt..,MMC Receive Pause Packet Counter Interrupt.." newline bitfld.long 0x0 19. "RXORANGEPIS,MMC Receive Out Of Range Error Packet Counter Interrupt Status. This bit is set when the rxoutofrangetype counter reaches half of the maximum value or the maximum value. Access restriction applies. Clears on read. Self-set to 1 on internal.." "MMC Receive Out Of Range Error Packet Counter..,MMC Receive Out Of Range Error Packet Counter.." newline bitfld.long 0x0 18. "RXLENERPIS,MMC Receive Length Error Packet Counter Interrupt Status This bit is set when the rxlengtherror counter reaches half of the maximum value or the maximum value. Access restriction applies. Clears on read. Self-set to 1 on internal event. 0x1:.." "MMC Receive Length Error Packet Counter..,MMC Receive Length Error Packet Counter.." newline bitfld.long 0x0 17. "RXUCGPIS,MMC Receive Unicast Good Packet Counter Interrupt Status This bit is set when the rxunicastpackets_g counter reaches half of the maximum value or the maximum value. Access restriction applies. Clears on read. Self-set to 1 on internal event." "MMC Receive Unicast Good Packet Counter..,MMC Receive Unicast Good Packet Counter.." newline bitfld.long 0x0 16. "RX1024TMAXOCTGBPIS,MMC Receive 1024 to Maximum Octet Good Bad Packet Counter Interrupt Status This bit is set when the rx1024tomaxoctets_gb counter reaches half of the maximum value or the maximum value. Access restriction applies. Clears on read." "MMC Receive 1024 to Maximum Octet Good Bad..,MMC Receive 1024 to Maximum Octet Good Bad.." newline bitfld.long 0x0 15. "RX512T1023OCTGBPIS,MMC Receive 512 to 1023 Octet Good Bad Packet Counter Interrupt Status This bit is set when the rx512to1023octets_gb counter reaches half of the maximum value or the maximum value. Access restriction applies. Clears on read. Self-set.." "MMC Receive 512 to 1023 Octet Good Bad Packet..,MMC Receive 512 to 1023 Octet Good Bad Packet.." newline bitfld.long 0x0 14. "RX256T511OCTGBPIS,MMC Receive 256 to 511 Octet Good Bad Packet Counter Interrupt Status This bit is set when the rx256to511octets_gb counter reaches half of the maximum value or the maximum value. Access restriction applies. Clears on read. Self-set to 1.." "MMC Receive 256 to 511 Octet Good Bad Packet..,MMC Receive 256 to 511 Octet Good Bad Packet.." newline bitfld.long 0x0 13. "RX128T255OCTGBPIS,MMC Receive 128 to 255 Octet Good Bad Packet Counter Interrupt Status This bit is set when the rx128to255octets_gb counter reaches half of the maximum value or the maximum value. Access restriction applies. Clears on read. Self-set to 1.." "MMC Receive 128 to 255 Octet Good Bad Packet..,MMC Receive 128 to 255 Octet Good Bad Packet.." newline bitfld.long 0x0 12. "RX65T127OCTGBPIS,MMC Receive 65 to 127 Octet Good Bad Packet Counter Interrupt Status This bit is set when the rx65to127octets_gb counter reaches half of the maximum value or the maximum value. Access restriction applies. Clears on read. Self-set to 1 on.." "MMC Receive 65 to 127 Octet Good Bad Packet..,MMC Receive 65 to 127 Octet Good Bad Packet.." newline bitfld.long 0x0 11. "RX64OCTGBPIS,MMC Receive 64 Octet Good Bad Packet Counter Interrupt Status This bit is set when the rx64octets_gb counter reaches half of the maximum value or the maximum value. Access restriction applies. Clears on read. Self-set to 1 on internal event." "MMC Receive 64 Octet Good Bad Packet Counter..,MMC Receive 64 Octet Good Bad Packet Counter.." newline bitfld.long 0x0 10. "RXOSIZEGPIS,MMC Receive Oversize Good Packet Counter Interrupt Status This bit is set when the rxoversize_g counter reaches half of the maximum value or the maximum value. Access restriction applies. Clears on read. Self-set to 1 on internal event. 0x1:.." "MMC Receive Oversize Good Packet Counter..,MMC Receive Oversize Good Packet Counter.." newline bitfld.long 0x0 9. "RXUSIZEGPIS,MMC Receive Undersize Good Packet Counter Interrupt Status This bit is set when the rxundersize_g counter reaches half of the maximum value or the maximum value. Access restriction applies. Clears on read. Self-set to 1 on internal event." "MMC Receive Undersize Good Packet Counter..,MMC Receive Undersize Good Packet Counter.." newline bitfld.long 0x0 8. "RXJABERPIS,MMC Receive Jabber Error Packet Counter Interrupt Status This bit is set when the rxjabbererror counter reaches half of the maximum value or the maximum value. Access restriction applies. Clears on read. Self-set to 1 on internal event. 0x1:.." "MMC Receive Jabber Error Packet Counter..,MMC Receive Jabber Error Packet Counter.." newline bitfld.long 0x0 7. "RXRUNTPIS,MMC Receive Runt Packet Counter Interrupt Status This bit is set when the rxrunterror counter reaches half of the maximum value or the maximum value. Access restriction applies. Clears on read. Self-set to 1 on internal event. 0x1: MMC Receive.." "MMC Receive Runt Packet Counter Interrupt Status..,MMC Receive Runt Packet Counter Interrupt Status.." newline bitfld.long 0x0 6. "RXALGNERPIS,MMC Receive Alignment Error Packet Counter Interrupt Status This bit is set when the rxalignmenterror counter reaches half of the maximum value or the maximum value. Access restriction applies. Clears on read. Self-set to 1 on internal event." "MMC Receive Alignment Error Packet Counter..,MMC Receive Alignment Error Packet Counter.." newline bitfld.long 0x0 5. "RXCRCERPIS,MMC Receive CRC Error Packet Counter Interrupt Status This bit is set when the rxcrcerror counter reaches half of the maximum value or the maximum value. Access restriction applies. Clears on read. Self-set to 1 on internal event. 0x1: MMC.." "MMC Receive CRC Error Packet Counter Interrupt..,MMC Receive CRC Error Packet Counter Interrupt.." newline bitfld.long 0x0 4. "RXMCGPIS,MMC Receive Multicast Good Packet Counter Interrupt Status This bit is set when the rxmulticastpackets_g counter reaches half of the maximum value or the maximum value. Access restriction applies. Clears on read. Self-set to 1 on internal event." "MMC Receive Multicast Good Packet Counter..,MMC Receive Multicast Good Packet Counter.." newline bitfld.long 0x0 3. "RXBCGPIS,MMC Receive Broadcast Good Packet Counter Interrupt Status This bit is set when the rxbroadcastpackets_g counter reaches half of the maximum value or the maximum value. Access restriction applies. Clears on read. Self-set to 1 on internal event." "MMC Receive Broadcast Good Packet Counter..,MMC Receive Broadcast Good Packet Counter.." newline bitfld.long 0x0 2. "RXGOCTIS,MMC Receive Good Octet Counter Interrupt Status This bit is set when the rxoctetcount_g counter reaches half of the maximum value or the maximum value. Access restriction applies. Clears on read. Self-set to 1 on internal event. 0x1: MMC Receive.." "MMC Receive Good Octet Counter Interrupt Status..,MMC Receive Good Octet Counter Interrupt Status.." newline bitfld.long 0x0 1. "RXGBOCTIS,MMC Receive Good Bad Octet Counter Interrupt Status This bit is set when the rxoctetcount_gb counter reaches half of the maximum value or the maximum value. Access restriction applies. Clears on read. Self-set to 1 on internal event. 0x1: MMC.." "MMC Receive Good Bad Octet Counter Interrupt..,MMC Receive Good Bad Octet Counter Interrupt.." newline bitfld.long 0x0 0. "RXGBPKTIS,MMC Receive Good Bad Packet Counter Interrupt Status This bit is set when the rxpacketcount_gb counter reaches half of the maximum value or the maximum value. Access restriction applies. Clears on read. Self-set to 1 on internal event. 0x1: MMC.." "MMC Receive Good Bad Packet Counter Interrupt..,MMC Receive Good Bad Packet Counter Interrupt.." line.long 0x4 "MMC_TX_INTERRUPT,This register maintains the interrupts generated from all Transmit statistics counters. The MMC Transmit Interrupt register maintains the interrupts generated when transmit statistic counters reach half their maximum values (0x8000_0000.." hexmask.long.byte 0x4 28.--31. 1. "RESERVED_31_28,Reserved." newline bitfld.long 0x4 27. "TXLPITRCIS,MMC Transmit LPI transition counter interrupt status This bit is set when the Tx_LPI_Tran_Cntr counter reaches half of the maximum value or the maximum value. Access restriction applies. Clears on read. Self-set to 1 on internal event. 0x1:.." "MMC Transmit LPI transition Counter Interrupt..,MMC Transmit LPI transition Counter Interrupt.." newline bitfld.long 0x4 26. "TXLPIUSCIS,MMC Transmit LPI microsecond counter interrupt status This bit is set when the Tx_LPI_USEC_Cntr counter reaches half of the maximum value or the maximum value. Access restriction applies. Clears on read. Self-set to 1 on internal event. 0x1:.." "MMC Transmit LPI microsecond Counter Interrupt..,MMC Transmit LPI microsecond Counter Interrupt.." newline bitfld.long 0x4 25. "TXOSIZEGPIS,MMC Transmit Oversize Good Packet Counter Interrupt Status This bit is set when the txoversize_g counter reaches half of the maximum value or the maximum value. Access restriction applies. Clears on read. Self-set to 1 on internal event. 0x1:.." "MMC Transmit Oversize Good Packet Counter..,MMC Transmit Oversize Good Packet Counter.." newline bitfld.long 0x4 24. "TXVLANGPIS,MMC Transmit VLAN Good Packet Counter Interrupt Status This bit is set when the txvlanpackets_g counter reaches half of the maximum value or the maximum value. Access restriction applies. Clears on read. Self-set to 1 on internal event. 0x1:.." "MMC Transmit VLAN Good Packet Counter Interrupt..,MMC Transmit VLAN Good Packet Counter Interrupt.." newline bitfld.long 0x4 23. "TXPAUSPIS,MMC Transmit Pause Packet Counter Interrupt Status This bit is set when the txpausepacketserror counter reaches half of the maximum value or the maximum value. Access restriction applies. Clears on read. Self-set to 1 on internal event. 0x1:.." "MMC Transmit Pause Packet Counter Interrupt..,MMC Transmit Pause Packet Counter Interrupt.." newline bitfld.long 0x4 22. "TXEXDEFPIS,MMC Transmit Excessive Deferral Packet Counter Interrupt Status This bit is set when the txexcessdef counter reaches half of the maximum value or the maximum value. Access restriction applies. Clears on read. Self-set to 1 on internal event." "MMC Transmit Excessive Deferral Packet Counter..,MMC Transmit Excessive Deferral Packet Counter.." newline bitfld.long 0x4 21. "TXGPKTIS,MMC Transmit Good Packet Counter Interrupt Status This bit is set when the txpacketcount_g counter reaches half of the maximum value or the maximum value. Access restriction applies. Clears on read. Self-set to 1 on internal event. 0x1: MMC.." "MMC Transmit Good Packet Counter Interrupt..,MMC Transmit Good Packet Counter Interrupt.." newline bitfld.long 0x4 20. "TXGOCTIS,MMC Transmit Good Octet Counter Interrupt Status This bit is set when the txoctetcount_g counter reaches half of the maximum value or the maximum value. Access restriction applies. Clears on read. Self-set to 1 on internal event. 0x1: MMC.." "MMC Transmit Good Octet Counter Interrupt Status..,MMC Transmit Good Octet Counter Interrupt Status.." newline bitfld.long 0x4 19. "TXCARERPIS,MMC Transmit Carrier Error Packet Counter Interrupt Status This bit is set when the txcarriererror counter reaches half of the maximum value or the maximum value. Access restriction applies. Clears on read. Self-set to 1 on internal event." "MMC Transmit Carrier Error Packet Counter..,MMC Transmit Carrier Error Packet Counter.." newline bitfld.long 0x4 18. "TXEXCOLPIS,MMC Transmit Excessive Collision Packet Counter Interrupt Status This bit is set when the txexesscol counter reaches half of the maximum value or the maximum value. Access restriction applies. Clears on read. Self-set to 1 on internal event." "MMC Transmit Excessive Collision Packet Counter..,MMC Transmit Excessive Collision Packet Counter.." newline bitfld.long 0x4 17. "TXLATCOLPIS,MMC Transmit Late Collision Packet Counter Interrupt Status This bit is set when the txlatecol counter reaches half of the maximum value or the maximum value. Access restriction applies. Clears on read. Self-set to 1 on internal event. 0x1:.." "MMC Transmit Late Collision Packet Counter..,MMC Transmit Late Collision Packet Counter.." newline bitfld.long 0x4 16. "TXDEFPIS,MMC Transmit Deferred Packet Counter Interrupt Status This bit is set when the txdeferred counter reaches half of the maximum value or the maximum value. Access restriction applies. Clears on read. Self-set to 1 on internal event. 0x1: MMC.." "MMC Transmit Deferred Packet Counter Interrupt..,MMC Transmit Deferred Packet Counter Interrupt.." newline bitfld.long 0x4 15. "TXMCOLGPIS,MMC Transmit Multiple Collision Good Packet Counter Interrupt Status This bit is set when the txmulticol_g counter reaches half of the maximum value or the maximum value. Access restriction applies. Clears on read. Self-set to 1 on internal.." "MMC Transmit Multiple Collision Good Packet..,MMC Transmit Multiple Collision Good Packet.." newline bitfld.long 0x4 14. "TXSCOLGPIS,MMC Transmit Single Collision Good Packet Counter Interrupt Status This bit is set when the txsinglecol_g counter reaches half of the maximum value or the maximum value. Access restriction applies. Clears on read. Self-set to 1 on internal.." "MMC Transmit Single Collision Good Packet..,MMC Transmit Single Collision Good Packet.." newline bitfld.long 0x4 13. "TXUFLOWERPIS,MMC Transmit Underflow Error Packet Counter Interrupt Status This bit is set when the txunderflowerror counter reaches half of the maximum value or the maximum value. Access restriction applies. Clears on read. Self-set to 1 on internal.." "MMC Transmit Underflow Error Packet Counter..,MMC Transmit Underflow Error Packet Counter.." newline bitfld.long 0x4 12. "TXBCGBPIS,MMC Transmit Broadcast Good Bad Packet Counter Interrupt Status This bit is set when the txbroadcastpackets_gb counter reaches half of the maximum value or the maximum value. Access restriction applies. Clears on read. Self-set to 1 on internal.." "MMC Transmit Broadcast Good Bad Packet Counter..,MMC Transmit Broadcast Good Bad Packet Counter.." newline bitfld.long 0x4 11. "TXMCGBPIS,MMC Transmit Multicast Good Bad Packet Counter Interrupt Status The bit is set when the txmulticastpackets_gb counter reaches half of the maximum value or the maximum value. Access restriction applies. Clears on read. Self-set to 1 on internal.." "MMC Transmit Multicast Good Bad Packet Counter..,MMC Transmit Multicast Good Bad Packet Counter.." newline bitfld.long 0x4 10. "TXUCGBPIS,MMC Transmit Unicast Good Bad Packet Counter Interrupt Status This bit is set when the txunicastpackets_gb counter reaches half of the maximum value or the maximum value. Access restriction applies. Clears on read. Self-set to 1 on internal.." "MMC Transmit Unicast Good Bad Packet Counter..,MMC Transmit Unicast Good Bad Packet Counter.." newline bitfld.long 0x4 9. "TX1024TMAXOCTGBPIS,MMC Transmit 1024 to Maximum Octet Good Bad Packet Counter Interrupt Status This bit is set when the tx1024tomaxoctets_gb counter reaches half of the maximum value or the maximum value. Access restriction applies. Clears on read." "MMC Transmit 1024 to Maximum Octet Good Bad..,MMC Transmit 1024 to Maximum Octet Good Bad.." newline bitfld.long 0x4 8. "TX512T1023OCTGBPIS,MMC Transmit 512 to 1023 Octet Good Bad Packet Counter Interrupt Status This bit is set when the tx512to1023octets_gb counter reaches half of the maximum value or the maximum value. Access restriction applies. Clears on read. Self-set.." "MMC Transmit 512 to 1023 Octet Good Bad Packet..,MMC Transmit 512 to 1023 Octet Good Bad Packet.." newline bitfld.long 0x4 7. "TX256T511OCTGBPIS,MMC Transmit 256 to 511 Octet Good Bad Packet Counter Interrupt Status This bit is set when the tx256to511octets_gb counter reaches half of the maximum value or the maximum value. Access restriction applies. Clears on read. Self-set to.." "MMC Transmit 256 to 511 Octet Good Bad Packet..,MMC Transmit 256 to 511 Octet Good Bad Packet.." newline bitfld.long 0x4 6. "TX128T255OCTGBPIS,MMC Transmit 128 to 255 Octet Good Bad Packet Counter Interrupt Status This bit is set when the tx128to255octets_gb counter reaches half of the maximum value or the maximum value. Access restriction applies. Clears on read. Self-set to.." "MMC Transmit 128 to 255 Octet Good Bad Packet..,MMC Transmit 128 to 255 Octet Good Bad Packet.." newline bitfld.long 0x4 5. "TX65T127OCTGBPIS,MMC Transmit 65 to 127 Octet Good Bad Packet Counter Interrupt Status This bit is set when the tx65to127octets_gb counter reaches half the maximum value and also when it reaches the maximum value. Access restriction applies. Clears on.." "MMC Transmit 65 to 127 Octet Good Bad Packet..,MMC Transmit 65 to 127 Octet Good Bad Packet.." newline bitfld.long 0x4 4. "TX64OCTGBPIS,MMC Transmit 64 Octet Good Bad Packet Counter Interrupt Status This bit is set when the tx64octets_gb counter reaches half of the maximum value or the maximum value. Access restriction applies. Clears on read. Self-set to 1 on internal.." "MMC Transmit 64 Octet Good Bad Packet Counter..,MMC Transmit 64 Octet Good Bad Packet Counter.." newline bitfld.long 0x4 3. "TXMCGPIS,MMC Transmit Multicast Good Packet Counter Interrupt Status This bit is set when the txmulticastpackets_g counter reaches half of the maximum value or the maximum value. Access restriction applies. Clears on read. Self-set to 1 on internal.." "MMC Transmit Multicast Good Packet Counter..,MMC Transmit Multicast Good Packet Counter.." newline bitfld.long 0x4 2. "TXBCGPIS,MMC Transmit Broadcast Good Packet Counter Interrupt Status This bit is set when the txbroadcastpackets_g counter reaches half of the maximum value or the maximum value. Access restriction applies. Clears on read. Self-set to 1 on internal.." "MMC Transmit Broadcast Good Packet Counter..,MMC Transmit Broadcast Good Packet Counter.." newline bitfld.long 0x4 1. "TXGBPKTIS,MMC Transmit Good Bad Packet Counter Interrupt Status This bit is set when the txpacketcount_gb counter reaches half of the maximum value or the maximum value. Access restriction applies. Clears on read. Self-set to 1 on internal event. 0x1:.." "MMC Transmit Good Bad Packet Counter Interrupt..,MMC Transmit Good Bad Packet Counter Interrupt.." newline bitfld.long 0x4 0. "TXGBOCTIS,MMC Transmit Good Bad Octet Counter Interrupt Status This bit is set when the txoctetcount_gb counter reaches half of the maximum value or the maximum value. Access restriction applies. Clears on read. Self-set to 1 on internal event. 0x1: MMC.." "MMC Transmit Good Bad Octet Counter Interrupt..,MMC Transmit Good Bad Octet Counter Interrupt.." group.long 0x70C++0x7 line.long 0x0 "MMC_RX_INTERRUPT_MASK,This register maintains the masks for interrupts generated from all Receive statistics counters. The MMC Receive Interrupt Mask register maintains the masks for the interrupts generated when receive statistic counters reach half of.." hexmask.long.byte 0x0 28.--31. 1. "RESERVED_31_28,Reserved." newline bitfld.long 0x0 27. "RXLPITRCIM,MMC Receive LPI transition counter interrupt Mask Setting this bit masks the interrupt when the Rx_LPI_Tran_Cntr counter reaches half of the maximum value or the maximum value. 0x0: MMC Receive LPI transition counter interrupt Mask is disabled.." "MMC Receive LPI transition counter interrupt..,MMC Receive LPI transition counter interrupt.." newline bitfld.long 0x0 26. "RXLPIUSCIM,MMC Receive LPI microsecond counter interrupt Mask Setting this bit masks the interrupt when the Rx_LPI_USEC_Cntr counter reaches half of the maximum value or the maximum value. 0x0: MMC Receive LPI microsecond counter interrupt Mask is.." "MMC Receive LPI microsecond counter interrupt..,MMC Receive LPI microsecond counter interrupt.." newline bitfld.long 0x0 25. "RXCTRLPIM,MMC Receive Control Packet Counter Interrupt Mask Setting this bit masks the interrupt when the rxctrlpackets_g counter reaches half of the maximum value or the maximum value. 0x0: MMC Receive Control Packet Counter Interrupt Mask is disabled.." "MMC Receive Control Packet Counter Interrupt..,MMC Receive Control Packet Counter Interrupt.." newline bitfld.long 0x0 24. "RXRCVERRPIM,MMC Receive Error Packet Counter Interrupt Mask Setting this bit masks the interrupt when the rxrcverror counter reaches half of the maximum value or the maximum value. 0x0: MMC Receive Error Packet Counter Interrupt Mask is disabled 0x1: MMC.." "MMC Receive Error Packet Counter Interrupt Mask..,MMC Receive Error Packet Counter Interrupt Mask.." newline bitfld.long 0x0 23. "RXWDOGPIM,MMC Receive Watchdog Error Packet Counter Interrupt Mask Setting this bit masks the interrupt when the rxwatchdog counter reaches half of the maximum value or the maximum value. 0x0: MMC Receive Watchdog Error Packet Counter Interrupt Mask is.." "MMC Receive Watchdog Error Packet Counter..,MMC Receive Watchdog Error Packet Counter.." newline bitfld.long 0x0 22. "RXVLANGBPIM,MMC Receive VLAN Good Bad Packet Counter Interrupt Mask Setting this bit masks the interrupt when the rxvlanpackets_gb counter reaches half of the maximum value or the maximum value. 0x0: MMC Receive VLAN Good Bad Packet Counter Interrupt.." "MMC Receive VLAN Good Bad Packet Counter..,MMC Receive VLAN Good Bad Packet Counter.." newline bitfld.long 0x0 21. "RXFOVPIM,MMC Receive FIFO Overflow Packet Counter Interrupt Mask Setting this bit masks the interrupt when the rxfifooverflow counter reaches half of the maximum value or the maximum value. 0x0: MMC Receive FIFO Overflow Packet Counter Interrupt Mask is.." "MMC Receive FIFO Overflow Packet Counter..,MMC Receive FIFO Overflow Packet Counter.." newline bitfld.long 0x0 20. "RXPAUSPIM,MMC Receive Pause Packet Counter Interrupt Mask Setting this bit masks the interrupt when the rxpausepackets counter reaches half of the maximum value or the maximum value. 0x0: MMC Receive Pause Packet Counter Interrupt Mask is disabled 0x1:.." "MMC Receive Pause Packet Counter Interrupt Mask..,MMC Receive Pause Packet Counter Interrupt Mask.." newline bitfld.long 0x0 19. "RXORANGEPIM,MMC Receive Out Of Range Error Packet Counter Interrupt Mask Setting this bit masks the interrupt when the rxoutofrangetype counter reaches half of the maximum value or the maximum value. 0x0: MMC Receive Out Of Range Error Packet Counter.." "MMC Receive Out Of Range Error Packet Counter..,MMC Receive Out Of Range Error Packet Counter.." newline bitfld.long 0x0 18. "RXLENERPIM,MMC Receive Length Error Packet Counter Interrupt Mask Setting this bit masks the interrupt when the rxlengtherror counter reaches half of the maximum value or the maximum value. 0x0: MMC Receive Length Error Packet Counter Interrupt Mask is.." "MMC Receive Length Error Packet Counter..,MMC Receive Length Error Packet Counter.." newline bitfld.long 0x0 17. "RXUCGPIM,MMC Receive Unicast Good Packet Counter Interrupt Mask Setting this bit masks the interrupt when the rxunicastpackets_g counter reaches half of the maximum value or the maximum value. 0x0: MMC Receive Unicast Good Packet Counter Interrupt Mask.." "MMC Receive Unicast Good Packet Counter..,MMC Receive Unicast Good Packet Counter.." newline bitfld.long 0x0 16. "RX1024TMAXOCTGBPIM,MMC Receive 1024 to Maximum Octet Good Bad Packet Counter Interrupt Mask. Setting this bit masks the interrupt when the rx1024tomaxoctets_gb counter reaches half of the maximum value or the maximum value. 0x0: MMC Receive 1024 to.." "MMC Receive 1024 to Maximum Octet Good Bad..,MMC Receive 1024 to Maximum Octet Good Bad.." newline bitfld.long 0x0 15. "RX512T1023OCTGBPIM,MMC Receive 512 to 1023 Octet Good Bad Packet Counter Interrupt Mask Setting this bit masks the interrupt when the rx512to1023octets_gb counter reaches half of the maximum value or the maximum value. 0x0: MMC Receive 512 to 1023 Octet.." "MMC Receive 512 to 1023 Octet Good Bad Packet..,MMC Receive 512 to 1023 Octet Good Bad Packet.." newline bitfld.long 0x0 14. "RX256T511OCTGBPIM,MMC Receive 256 to 511 Octet Good Bad Packet Counter Interrupt Mask Setting this bit masks the interrupt when the rx256to511octets_gb counter reaches half of the maximum value or the maximum value. 0x0: MMC Receive 256 to 511 Octet Good.." "MMC Receive 256 to 511 Octet Good Bad Packet..,MMC Receive 256 to 511 Octet Good Bad Packet.." newline bitfld.long 0x0 13. "RX128T255OCTGBPIM,MMC Receive 128 to 255 Octet Good Bad Packet Counter Interrupt Mask Setting this bit masks the interrupt when the rx128to255octets_gb counter reaches half of the maximum value or the maximum value. 0x0: MMC Receive 128 to 255 Octet Good.." "MMC Receive 128 to 255 Octet Good Bad Packet..,MMC Receive 128 to 255 Octet Good Bad Packet.." newline bitfld.long 0x0 12. "RX65T127OCTGBPIM,MMC Receive 65 to 127 Octet Good Bad Packet Counter Interrupt Mask Setting this bit masks the interrupt when the rx65to127octets_gb counter reaches half of the maximum value or the maximum value. 0x0: MMC Receive 65 to 127 Octet Good Bad.." "MMC Receive 65 to 127 Octet Good Bad Packet..,MMC Receive 65 to 127 Octet Good Bad Packet.." newline bitfld.long 0x0 11. "RX64OCTGBPIM,MMC Receive 64 Octet Good Bad Packet Counter Interrupt Mask Setting this bit masks the interrupt when the rx64octets_gb counter reaches half of the maximum value or the maximum value. 0x0: MMC Receive 64 Octet Good Bad Packet Counter.." "MMC Receive 64 Octet Good Bad Packet Counter..,MMC Receive 64 Octet Good Bad Packet Counter.." newline bitfld.long 0x0 10. "RXOSIZEGPIM,MMC Receive Oversize Good Packet Counter Interrupt Mask Setting this bit masks the interrupt when the rxoversize_g counter reaches half of the maximum value or the maximum value. 0x0: MMC Receive Oversize Good Packet Counter Interrupt Mask is.." "MMC Receive Oversize Good Packet Counter..,MMC Receive Oversize Good Packet Counter.." newline bitfld.long 0x0 9. "RXUSIZEGPIM,MMC Receive Undersize Good Packet Counter Interrupt Mask Setting this bit masks the interrupt when the rxundersize_g counter reaches half of the maximum value or the maximum value. 0x0: MMC Receive Undersize Good Packet Counter Interrupt Mask.." "MMC Receive Undersize Good Packet Counter..,MMC Receive Undersize Good Packet Counter.." newline bitfld.long 0x0 8. "RXJABERPIM,MMC Receive Jabber Error Packet Counter Interrupt Mask Setting this bit masks the interrupt when the rxjabbererror counter reaches half of the maximum value or the maximum value. 0x0: MMC Receive Jabber Error Packet Counter Interrupt Mask is.." "MMC Receive Jabber Error Packet Counter..,MMC Receive Jabber Error Packet Counter.." newline bitfld.long 0x0 7. "RXRUNTPIM,MMC Receive Runt Packet Counter Interrupt Mask Setting this bit masks the interrupt when the rxrunterror counter reaches half of the maximum value or the maximum value. 0x0: MMC Receive Runt Packet Counter Interrupt Mask is disabled 0x1: MMC.." "MMC Receive Runt Packet Counter Interrupt Mask..,MMC Receive Runt Packet Counter Interrupt Mask.." newline bitfld.long 0x0 6. "RXALGNERPIM,MMC Receive Alignment Error Packet Counter Interrupt Mask Setting this bit masks the interrupt when the rxalignmenterror counter reaches half of the maximum value or the maximum value. 0x0: MMC Receive Alignment Error Packet Counter Interrupt.." "MMC Receive Alignment Error Packet Counter..,MMC Receive Alignment Error Packet Counter.." newline bitfld.long 0x0 5. "RXCRCERPIM,MMC Receive CRC Error Packet Counter Interrupt Mask Setting this bit masks the interrupt when the rxcrcerror counter reaches half of the maximum value or the maximum value. 0x0: MMC Receive CRC Error Packet Counter Interrupt Mask is disabled.." "MMC Receive CRC Error Packet Counter Interrupt..,MMC Receive CRC Error Packet Counter Interrupt.." newline bitfld.long 0x0 4. "RXMCGPIM,MMC Receive Multicast Good Packet Counter Interrupt Mask Setting this bit masks the interrupt when the rxmulticastpackets_g counter reaches half of the maximum value or the maximum value. 0x0: MMC Receive Multicast Good Packet Counter Interrupt.." "MMC Receive Multicast Good Packet Counter..,MMC Receive Multicast Good Packet Counter.." newline bitfld.long 0x0 3. "RXBCGPIM,MMC Receive Broadcast Good Packet Counter Interrupt Mask Setting this bit masks the interrupt when the rxbroadcastpackets_g counter reaches half of the maximum value or the maximum value. 0x0: MMC Receive Broadcast Good Packet Counter Interrupt.." "MMC Receive Broadcast Good Packet Counter..,MMC Receive Broadcast Good Packet Counter.." newline bitfld.long 0x0 2. "RXGOCTIM,MMC Receive Good Octet Counter Interrupt Mask Setting this bit masks the interrupt when the rxoctetcount_g counter reaches half of the maximum value or the maximum value. 0x0: MMC Receive Good Octet Counter Interrupt Mask is disabled 0x1: MMC.." "MMC Receive Good Octet Counter Interrupt Mask is..,MMC Receive Good Octet Counter Interrupt Mask is.." newline bitfld.long 0x0 1. "RXGBOCTIM,MMC Receive Good Bad Octet Counter Interrupt Mask Setting this bit masks the interrupt when the rxoctetcount_gb counter reaches half of the maximum value or the maximum value. 0x0: MMC Receive Good Bad Octet Counter Interrupt Mask is disabled.." "MMC Receive Good Bad Octet Counter Interrupt..,MMC Receive Good Bad Octet Counter Interrupt.." newline bitfld.long 0x0 0. "RXGBPKTIM,MMC Receive Good Bad Packet Counter Interrupt Mask Setting this bit masks the interrupt when the rxpacketcount_gb counter reaches half of the maximum value or the maximum value. 0x0: MMC Receive Good Bad Packet Counter Interrupt Mask is.." "MMC Receive Good Bad Packet Counter Interrupt..,MMC Receive Good Bad Packet Counter Interrupt.." line.long 0x4 "MMC_TX_INTERRUPT_MASK,This register maintains the masks for interrupts generated from all Transmit statistics counters. The MMC Transmit Interrupt Mask register maintains the masks for the interrupts generated when the transmit statistic counters reach.." hexmask.long.byte 0x4 28.--31. 1. "RESERVED_31_28,Reserved." newline bitfld.long 0x4 27. "TXLPITRCIM,MMC Transmit LPI transition counter interrupt Mask Setting this bit masks the interrupt when the Tx_LPI_Tran_Cntr counter reaches half of the maximum value or the maximum value. 0x0: MMC Transmit LPI transition counter interrupt Mask is.." "MMC Transmit LPI transition counter interrupt..,MMC Transmit LPI transition counter interrupt.." newline bitfld.long 0x4 26. "TXLPIUSCIM,MMC Transmit LPI microsecond counter interrupt Mask Setting this bit masks the interrupt when the Tx_LPI_USEC_Cntr counter reaches half of the maximum value or the maximum value. 0x0: MMC Transmit LPI microsecond counter interrupt Mask is.." "MMC Transmit LPI microsecond counter interrupt..,MMC Transmit LPI microsecond counter interrupt.." newline bitfld.long 0x4 25. "TXOSIZEGPIM,MMC Transmit Oversize Good Packet Counter Interrupt Mask Setting this bit masks the interrupt when the txoversize_g counter reaches half of the maximum value or the maximum value. 0x0: MMC Transmit Oversize Good Packet Counter Interrupt Mask.." "MMC Transmit Oversize Good Packet Counter..,MMC Transmit Oversize Good Packet Counter.." newline bitfld.long 0x4 24. "TXVLANGPIM,MMC Transmit VLAN Good Packet Counter Interrupt Mask Setting this bit masks the interrupt when the txvlanpackets_g counter reaches half of the maximum value or the maximum value. 0x0: MMC Transmit VLAN Good Packet Counter Interrupt Mask is.." "MMC Transmit VLAN Good Packet Counter Interrupt..,MMC Transmit VLAN Good Packet Counter Interrupt.." newline bitfld.long 0x4 23. "TXPAUSPIM,MMC Transmit Pause Packet Counter Interrupt Mask Setting this bit masks the interrupt when the txpausepackets counter reaches half of the maximum value or the maximum value. 0x0: MMC Transmit Pause Packet Counter Interrupt Mask is disabled 0x1:.." "MMC Transmit Pause Packet Counter Interrupt Mask..,MMC Transmit Pause Packet Counter Interrupt Mask.." newline bitfld.long 0x4 22. "TXEXDEFPIM,MMC Transmit Excessive Deferral Packet Counter Interrupt Mask Setting this bit masks the interrupt when the txexcessdef counter reaches half of the maximum value or the maximum value. 0x0: MMC Transmit Excessive Deferral Packet Counter.." "MMC Transmit Excessive Deferral Packet Counter..,MMC Transmit Excessive Deferral Packet Counter.." newline bitfld.long 0x4 21. "TXGPKTIM,MMC Transmit Good Packet Counter Interrupt Mask Setting this bit masks the interrupt when the txpacketcount_g counter reaches half of the maximum value or the maximum value. 0x0: MMC Transmit Good Packet Counter Interrupt Mask is disabled 0x1:.." "MMC Transmit Good Packet Counter Interrupt Mask..,MMC Transmit Good Packet Counter Interrupt Mask.." newline bitfld.long 0x4 20. "TXGOCTIM,MMC Transmit Good Octet Counter Interrupt Mask Setting this bit masks the interrupt when the txoctetcount_g counter reaches half of the maximum value or the maximum value. 0x0: MMC Transmit Good Octet Counter Interrupt Mask is disabled 0x1: MMC.." "MMC Transmit Good Octet Counter Interrupt Mask..,MMC Transmit Good Octet Counter Interrupt Mask.." newline bitfld.long 0x4 19. "TXCARERPIM,MMC Transmit Carrier Error Packet Counter Interrupt Mask Setting this bit masks the interrupt when the txcarriererror counter reaches half of the maximum value or the maximum value. 0x0: MMC Transmit Carrier Error Packet Counter Interrupt Mask.." "MMC Transmit Carrier Error Packet Counter..,MMC Transmit Carrier Error Packet Counter.." newline bitfld.long 0x4 18. "TXEXCOLPIM,MMC Transmit Excessive Collision Packet Counter Interrupt Mask Setting this bit masks the interrupt when the txexcesscol counter reaches half of the maximum value or the maximum value. 0x0: MMC Transmit Excessive Collision Packet Counter.." "MMC Transmit Excessive Collision Packet Counter..,MMC Transmit Excessive Collision Packet Counter.." newline bitfld.long 0x4 17. "TXLATCOLPIM,MMC Transmit Late Collision Packet Counter Interrupt Mask Setting this bit masks the interrupt when the txlatecol counter reaches half of the maximum value or the maximum value. 0x0: MMC Transmit Late Collision Packet Counter Interrupt Mask.." "MMC Transmit Late Collision Packet Counter..,MMC Transmit Late Collision Packet Counter.." newline bitfld.long 0x4 16. "TXDEFPIM,MMC Transmit Deferred Packet Counter Interrupt Mask Setting this bit masks the interrupt when the txdeferred counter reaches half of the maximum value or the maximum value. 0x0: MMC Transmit Deferred Packet Counter Interrupt Mask is disabled.." "MMC Transmit Deferred Packet Counter Interrupt..,MMC Transmit Deferred Packet Counter Interrupt.." newline bitfld.long 0x4 15. "TXMCOLGPIM,MMC Transmit Multiple Collision Good Packet Counter Interrupt Mask Setting this bit masks the interrupt when the txmulticol_g counter reaches half of the maximum value or the maximum value. 0x0: MMC Transmit Multiple Collision Good Packet.." "MMC Transmit Multiple Collision Good Packet..,MMC Transmit Multiple Collision Good Packet.." newline bitfld.long 0x4 14. "TXSCOLGPIM,MMC Transmit Single Collision Good Packet Counter Interrupt Mask Setting this bit masks the interrupt when the txsinglecol_g counter reaches half of the maximum value or the maximum value. 0x0: MMC Transmit Single Collision Good Packet Counter.." "MMC Transmit Single Collision Good Packet..,MMC Transmit Single Collision Good Packet.." newline bitfld.long 0x4 13. "TXUFLOWERPIM,MMC Transmit Underflow Error Packet Counter Interrupt Mask Setting this bit masks the interrupt when the txunderflowerror counter reaches half of the maximum value or the maximum value. 0x0: MMC Transmit Underflow Error Packet Counter.." "MMC Transmit Underflow Error Packet Counter..,MMC Transmit Underflow Error Packet Counter.." newline bitfld.long 0x4 12. "TXBCGBPIM,MMC Transmit Broadcast Good Bad Packet Counter Interrupt Mask Setting this bit masks the interrupt when the txbroadcastpackets_gb counter reaches half of the maximum value or the maximum value. 0x0: MMC Transmit Broadcast Good Bad Packet.." "MMC Transmit Broadcast Good Bad Packet Counter..,MMC Transmit Broadcast Good Bad Packet Counter.." newline bitfld.long 0x4 11. "TXMCGBPIM,MMC Transmit Multicast Good Bad Packet Counter Interrupt Mask Setting this bit masks the interrupt when the txmulticastpackets_gb counter reaches half of the maximum value or the maximum value. 0x0: MMC Transmit Multicast Good Bad Packet.." "MMC Transmit Multicast Good Bad Packet Counter..,MMC Transmit Multicast Good Bad Packet Counter.." newline bitfld.long 0x4 10. "TXUCGBPIM,MMC Transmit Unicast Good Bad Packet Counter Interrupt Mask Setting this bit masks the interrupt when the txunicastpackets_gb counter reaches half of the maximum value or the maximum value. 0x0: MMC Transmit Unicast Good Bad Packet Counter.." "MMC Transmit Unicast Good Bad Packet Counter..,MMC Transmit Unicast Good Bad Packet Counter.." newline bitfld.long 0x4 9. "TX1024TMAXOCTGBPIM,MMC Transmit 1024 to Maximum Octet Good Bad Packet Counter Interrupt Mask Setting this bit masks the interrupt when the tx1024tomaxoctets_gb counter reaches half of the maximum value or the maximum value. 0x0: MMC Transmit 1024 to.." "MMC Transmit 1024 to Maximum Octet Good Bad..,MMC Transmit 1024 to Maximum Octet Good Bad.." newline bitfld.long 0x4 8. "TX512T1023OCTGBPIM,MMC Transmit 512 to 1023 Octet Good Bad Packet Counter Interrupt Mask Setting this bit masks the interrupt when the tx512to1023octets_gb counter reaches half of the maximum value or the maximum value. 0x0: MMC Transmit 512 to 1023.." "MMC Transmit 512 to 1023 Octet Good Bad Packet..,MMC Transmit 512 to 1023 Octet Good Bad Packet.." newline bitfld.long 0x4 7. "TX256T511OCTGBPIM,MMC Transmit 256 to 511 Octet Good Bad Packet Counter Interrupt Mask Setting this bit masks the interrupt when the tx256to511octets_gb counter reaches half of the maximum value or the maximum value. 0x0: MMC Transmit 256 to 511 Octet.." "MMC Transmit 256 to 511 Octet Good Bad Packet..,MMC Transmit 256 to 511 Octet Good Bad Packet.." newline bitfld.long 0x4 6. "TX128T255OCTGBPIM,MMC Transmit 128 to 255 Octet Good Bad Packet Counter Interrupt Mask Setting this bit masks the interrupt when the tx128to255octets_gb counter reaches half of the maximum value or the maximum value. 0x0: MMC Transmit 128 to 255 Octet.." "MMC Transmit 128 to 255 Octet Good Bad Packet..,MMC Transmit 128 to 255 Octet Good Bad Packet.." newline bitfld.long 0x4 5. "TX65T127OCTGBPIM,MMC Transmit 65 to 127 Octet Good Bad Packet Counter Interrupt Mask Setting this bit masks the interrupt when the tx65to127octets_gb counter reaches half of the maximum value or the maximum value. 0x0: MMC Transmit 65 to 127 Octet Good.." "MMC Transmit 65 to 127 Octet Good Bad Packet..,MMC Transmit 65 to 127 Octet Good Bad Packet.." newline bitfld.long 0x4 4. "TX64OCTGBPIM,MMC Transmit 64 Octet Good Bad Packet Counter Interrupt Mask Setting this bit masks the interrupt when the tx64octets_gb counter reaches half of the maximum value or the maximum value. 0x0: MMC Transmit 64 Octet Good Bad Packet Counter.." "MMC Transmit 64 Octet Good Bad Packet Counter..,MMC Transmit 64 Octet Good Bad Packet Counter.." newline bitfld.long 0x4 3. "TXMCGPIM,MMC Transmit Multicast Good Packet Counter Interrupt Mask Setting this bit masks the interrupt when the txmulticastpackets_g counter reaches half of the maximum value or the maximum value. 0x0: MMC Transmit Multicast Good Packet Counter.." "MMC Transmit Multicast Good Packet Counter..,MMC Transmit Multicast Good Packet Counter.." newline bitfld.long 0x4 2. "TXBCGPIM,MMC Transmit Broadcast Good Packet Counter Interrupt Mask Setting this bit masks the interrupt when the txbroadcastpackets_g counter reaches half of the maximum value or the maximum value. 0x0: MMC Transmit Broadcast Good Packet Counter.." "MMC Transmit Broadcast Good Packet Counter..,MMC Transmit Broadcast Good Packet Counter.." newline bitfld.long 0x4 1. "TXGBPKTIM,MMC Transmit Good Bad Packet Counter Interrupt Mask Setting this bit masks the interrupt when the txpacketcount_gb counter reaches half of the maximum value or the maximum value. 0x0: MMC Transmit Good Bad Packet Counter Interrupt Mask is.." "MMC Transmit Good Bad Packet Counter Interrupt..,MMC Transmit Good Bad Packet Counter Interrupt.." newline bitfld.long 0x4 0. "TXGBOCTIM,MMC Transmit Good Bad Octet Counter Interrupt Mask Setting this bit masks the interrupt when the txoctetcount_gb counter reaches half of the maximum value or the maximum value. 0x0: MMC Transmit Good Bad Octet Counter Interrupt Mask is disabled.." "MMC Transmit Good Bad Octet Counter Interrupt..,MMC Transmit Good Bad Octet Counter Interrupt.." rgroup.long 0x714++0x67 line.long 0x0 "TX_OCTET_COUNT_GOOD_BAD,This register provides the number of bytes transmitted by the DWC_ether_qos. exclusive of preamble and retried bytes. in good and bad packets." hexmask.long 0x0 0.--31. 1. "TXOCTGB,Tx Octet Count Good Bad This field indicates the number of bytes transmitted exclusive of preamble and retried bytes in good and bad packets." line.long 0x4 "TX_PACKET_COUNT_GOOD_BAD,This register provides the number of good and bad packets transmitted by DWC_ether_qos. exclusive of retried packets." hexmask.long 0x4 0.--31. 1. "TXPKTGB,Tx Packet Count Good Bad This field indicates the number of good and bad packets transmitted exclusive of retried packets." line.long 0x8 "TX_BROADCAST_PACKETS_GOOD,This register provides the number of good broadcast packets transmitted by DWC_ether_qos." hexmask.long 0x8 0.--31. 1. "TXBCASTG,Tx Broadcast Packets Good This field indicates the number of good broadcast packets transmitted." line.long 0xC "TX_MULTICAST_PACKETS_GOOD,This register provides the number of good multicast packets transmitted by DWC_ether_qos." hexmask.long 0xC 0.--31. 1. "TXMCASTG,Tx Multicast Packets Good This field indicates the number of good multicast packets transmitted." line.long 0x10 "TX_64OCTETS_PACKETS_GOOD_BAD,This register provides the number of good and bad packets transmitted by DWC_ether_qos with length 64 bytes. exclusive of preamble and retried packets." hexmask.long 0x10 0.--31. 1. "TX64OCTGB,Tx 64Octets Packets Good_Bad This field indicates the number of good and bad packets transmitted with length 64 bytes exclusive of preamble and retried packets." line.long 0x14 "TX_65TO127OCTETS_PACKETS_GOOD_BAD,This register provides the number of good and bad packets transmitted by DWC_ether_qos with length between 65 and 127 (inclusive) bytes. exclusive of preamble and retried packets." hexmask.long 0x14 0.--31. 1. "TX65_127OCTGB,Tx 65To127Octets Packets Good Bad This field indicates the number of good and bad packets transmitted with length between 65 and 127 (inclusive) bytes exclusive of preamble and retried packets." line.long 0x18 "TX_128TO255OCTETS_PACKETS_GOOD_BAD,This register provides the number of good and bad packets transmitted by DWC_ether_qos with length between 128 to 255 (inclusive) bytes. exclusive of preamble and retried packets." hexmask.long 0x18 0.--31. 1. "TX128_255OCTGB,Tx 128To255Octets Packets Good Bad This field indicates the number of good and bad packets transmitted with length between 128 and 255 (inclusive) bytes exclusive of preamble and retried packets." line.long 0x1C "TX_256TO511OCTETS_PACKETS_GOOD_BAD,This register provides the number of good and bad packets transmitted by DWC_ether_qos with length between 256 to 511 (inclusive) bytes. exclusive of preamble and retried packets." hexmask.long 0x1C 0.--31. 1. "TX256_511OCTGB,Tx 256To511Octets Packets Good Bad This field indicates the number of good and bad packets transmitted with length between 256 and 511 (inclusive) bytes exclusive of preamble and retried packets." line.long 0x20 "TX_512TO1023OCTETS_PACKETS_GOOD_BAD,This register provides the number of good and bad packets transmitted by DWC_ether_qos with length 512 to 1023 (inclusive) bytes. exclusive of preamble and retried packets." hexmask.long 0x20 0.--31. 1. "TX512_1023OCTGB,Tx 512To1023Octets Packets Good Bad This field indicates the number of good and bad packets transmitted with length between 512 and 1023 (inclusive) bytes exclusive of preamble and retried packets." line.long 0x24 "TX_1024TOMAXOCTETS_PACKETS_GOOD_BAD,This register provides the number of good and bad packets transmitted by DWC_ether_qos with length 1024 to maxsize (inclusive) bytes. exclusive of preamble and retried packets." hexmask.long 0x24 0.--31. 1. "TX1024_MAXOCTGB,Tx 1024ToMaxOctets Packets Good Bad This field indicates the number of good and bad packets transmitted with length between 1024 and maxsize (inclusive) bytes exclusive of preamble and retried packets." line.long 0x28 "TX_UNICAST_PACKETS_GOOD_BAD,This register provides the number of good and bad unicast packets transmitted by DWC_ether_qos." hexmask.long 0x28 0.--31. 1. "TXUCASTGB,Tx Unicast Packets Good Bad This field indicates the number of good and bad unicast packets transmitted." line.long 0x2C "TX_MULTICAST_PACKETS_GOOD_BAD,This register provides the number of good and bad multicast packets transmitted by DWC_ether_qos." hexmask.long 0x2C 0.--31. 1. "TXMCASTGB,Tx Multicast Packets Good Bad This field indicates the number of good and bad multicast packets transmitted." line.long 0x30 "TX_BROADCAST_PACKETS_GOOD_BAD,This register provides the number of good and bad broadcast packets transmitted by DWC_ether_qos." hexmask.long 0x30 0.--31. 1. "TXBCASTGB,Tx Broadcast Packets Good Bad This field indicates the number of good and bad broadcast packets transmitted." line.long 0x34 "TX_UNDERFLOW_ERROR_PACKETS,This register provides the number of packets aborted by DWC_ether_qos because of packets underflow error." hexmask.long 0x34 0.--31. 1. "TXUNDRFLW,Tx Underflow Error Packets This field indicates the number of packets aborted because of packets underflow error." line.long 0x38 "TX_SINGLE_COLLISION_GOOD_PACKETS,This register provides the number of successfully transmitted packets by DWC_ether_qos after a single collision in the half-duplex mode." hexmask.long 0x38 0.--31. 1. "TXSNGLCOLG,Tx Single Collision Good Packets This field indicates the number of successfully transmitted packets after a single collision in the half-duplex mode." line.long 0x3C "TX_MULTIPLE_COLLISION_GOOD_PACKETS,This register provides the number of successfully transmitted packets by DWC_ether_qos after multiple collisions in the half-duplex mode." hexmask.long 0x3C 0.--31. 1. "TXMULTCOLG,Tx Multiple Collision Good Packets This field indicates the number of successfully transmitted packets after multiple collisions in the half-duplex mode." line.long 0x40 "TX_DEFERRED_PACKETS,This register provides the number of successfully transmitted by DWC_ether_qos after a deferral in the half-duplex mode." hexmask.long 0x40 0.--31. 1. "TXDEFRD,Tx Deferred Packets This field indicates the number of successfully transmitted after a deferral in the half-duplex mode." line.long 0x44 "TX_LATE_COLLISION_PACKETS,This register provides the number of packets aborted by DWC_ether_qos because of late collision error." hexmask.long 0x44 0.--31. 1. "TXLATECOL,Tx Late Collision Packets This field indicates the number of packets aborted because of late collision error." line.long 0x48 "TX_EXCESSIVE_COLLISION_PACKETS,This register provides the number of packets aborted by DWC_ether_qos because of excessive (16) collision errors." hexmask.long 0x48 0.--31. 1. "TXEXSCOL,Tx Excessive Collision Packets This field indicates the number of packets aborted because of excessive (16) collision errors." line.long 0x4C "TX_CARRIER_ERROR_PACKETS,This register provides the number of packets aborted by DWC_ether_qos because of carrier sense error (no carrier or loss of carrier)." hexmask.long 0x4C 0.--31. 1. "TXCARR,Tx Carrier Error Packets This field indicates the number of packets aborted because of carrier sense error (no carrier or loss of carrier)." line.long 0x50 "TX_OCTET_COUNT_GOOD,This register provides the number of bytes transmitted by DWC_ether_qos. exclusive of preamble. only in good packets." hexmask.long 0x50 0.--31. 1. "TXOCTG,Tx Octet Count Good This field indicates the number of bytes transmitted exclusive of preamble only in good packets." line.long 0x54 "TX_PACKET_COUNT_GOOD,This register provides the number of good packets transmitted by DWC_ether_qos." hexmask.long 0x54 0.--31. 1. "TXPKTG,Tx Packet Count Good This field indicates the number of good packets transmitted." line.long 0x58 "TX_EXCESSIVE_DEFERRAL_ERROR,This register provides the number of packets aborted by DWC_ether_qos because of excessive deferral error (deferred for more than two max-sized packet times)." hexmask.long 0x58 0.--31. 1. "TXEXSDEF,Tx Excessive Deferral Error This field indicates the number of packets aborted because of excessive deferral error (deferred for more than two max-sized packet times)." line.long 0x5C "TX_PAUSE_PACKETS,This register provides the number of good Pause packets transmitted by DWC_ether_qos." hexmask.long 0x5C 0.--31. 1. "TXPAUSE,Tx Pause Packets This field indicates the number of good Pause packets transmitted." line.long 0x60 "TX_VLAN_PACKETS_GOOD,This register provides the number of good VLAN packets transmitted by DWC_ether_qos." hexmask.long 0x60 0.--31. 1. "TXVLANG,Tx VLAN Packets Good This field provides the number of good VLAN packets transmitted." line.long 0x64 "TX_OSIZE_PACKETS_GOOD,This register provides the number of packets transmitted by DWC_ether_qos without errors and with length greater than the maxsize (1.518 or 1.522 bytes for VLAN tagged packets; 2000 bytes if enabled in S2KP bit of the.." hexmask.long 0x64 0.--31. 1. "TXOSIZG,Tx OSize Packets Good This field indicates the number of packets transmitted without errors and with length greater than the maxsize (1 518 or 1 522 bytes for VLAN tagged packets; 2000 bytes if enabled in S2KP bit of the MAC_Configuration.." rgroup.long 0x780++0x67 line.long 0x0 "RX_PACKETS_COUNT_GOOD_BAD,This register provides the number of good and bad packets received by DWC_ether_qos." hexmask.long 0x0 0.--31. 1. "RXPKTGB,Rx Packets Count Good Bad This field indicates the number of good and bad packets received." line.long 0x4 "RX_OCTET_COUNT_GOOD_BAD,This register provides the number of bytes received by DWC_ther_qos. exclusive of preamble. in good and bad packets." hexmask.long 0x4 0.--31. 1. "RXOCTGB,Rx Octet Count Good Bad This field indicates the number of bytes received exclusive of preamble in good and bad packets." line.long 0x8 "RX_OCTET_COUNT_GOOD,This register provides the number of bytes received by DWC_ether_qos. exclusive of preamble. only in good packets." hexmask.long 0x8 0.--31. 1. "RXOCTG,Rx Octet Count Good This field indicates the number of bytes received exclusive of preamble only in good packets." line.long 0xC "RX_BROADCAST_PACKETS_GOOD,This register provides the number of good broadcast packets received by DWC_ether_qos." hexmask.long 0xC 0.--31. 1. "RXBCASTG,Rx Broadcast Packets Good This field indicates the number of good broadcast packets received." line.long 0x10 "RX_MULTICAST_PACKETS_GOOD,This register provides the number of good multicast packets received by DWC_ether_qos." hexmask.long 0x10 0.--31. 1. "RXMCASTG,Rx Multicast Packets Good This field indicates the number of good multicast packets received." line.long 0x14 "RX_CRC_ERROR_PACKETS,This register provides the number of packets received by DWC_ether_qos with CRC error." hexmask.long 0x14 0.--31. 1. "RXCRCERR,Rx CRC Error Packets This field indicates the number of packets received with CRC error." line.long 0x18 "RX_ALIGNMENT_ERROR_PACKETS,This register provides the number of packets received by DWC_ether_qos with alignment (dribble) error. It is valid only in 10/100 mode." hexmask.long 0x18 0.--31. 1. "RXALGNERR,Rx Alignment Error Packets This field indicates the number of packets received with alignment (dribble) error. It is valid only in 10/100 mode." line.long 0x1C "RX_RUNT_ERROR_PACKETS,This register provides the number of packets received by DWC_ether_qos with runt (length less than 64 bytes and CRC error) error." hexmask.long 0x1C 0.--31. 1. "RXRUNTERR,Rx Runt Error Packets This field indicates the number of packets received with runt (length less than 64 bytes and CRC error) error." line.long 0x20 "RX_JABBER_ERROR_PACKETS,This register provides the number of giant packets received by DWC_ether_qos with length (including CRC) greater than 1.518 bytes (1.522 bytes for VLAN tagged) and with CRC error. If Jumbo Packet mode is enabled. packets of length.." hexmask.long 0x20 0.--31. 1. "RXJABERR,Rx Jabber Error Packets This field indicates the number of giant packets received with length (including CRC) greater than 1 518 bytes (1 522 bytes for VLAN tagged) and with CRC error. If Jumbo Packet mode is enabled packets of length greater.." line.long 0x24 "RX_UNDERSIZE_PACKETS_GOOD,This register provides the number of packets received by DWC_ether_qos with length less than 64 bytes. without any errors." hexmask.long 0x24 0.--31. 1. "RXUNDERSZG,Rx Undersize Packets Good This field indicates the number of packets received with length less than 64 bytes without any errors." line.long 0x28 "RX_OVERSIZE_PACKETS_GOOD,This register provides the number of packets received by DWC_ether_qos without errors. with length greater than the maxsize (1.518 bytes or 1.522 bytes for VLAN tagged packets; 2000 bytes if enabled in the S2KP bit of the.." hexmask.long 0x28 0.--31. 1. "RXOVERSZG,Rx Oversize Packets Good This field indicates the number of packets received without errors with length greater than the maxsize (1 518 bytes or 1 522 bytes for VLAN tagged packets; 2000 bytes if enabled in the S2KP bit of the.." line.long 0x2C "RX_64OCTETS_PACKETS_GOOD_BAD,This register provides the number of good and bad packets received by DWC_ether_qos with length 64 bytes. exclusive of the preamble." hexmask.long 0x2C 0.--31. 1. "RX64OCTGB,Rx 64 Octets Packets Good Bad This field indicates the number of good and bad packets received with length 64 bytes exclusive of the preamble." line.long 0x30 "RX_65TO127OCTETS_PACKETS_GOOD_BAD,This register provides the number of good and bad packets received by DWC_ether_qos with length between 65 and 127 (inclusive) bytes. exclusive of the preamble." hexmask.long 0x30 0.--31. 1. "RX65_127OCTGB,Rx 65-127 Octets Packets Good Bad This field indicates the number of good and bad packets received with length between 65 and 127 (inclusive) bytes exclusive of the preamble." line.long 0x34 "RX_128TO255OCTETS_PACKETS_GOOD_BAD,This register provides the number of good and bad packets received by DWC_ether_qos with length between 128 and 255 (inclusive) bytes. exclusive of the preamble." hexmask.long 0x34 0.--31. 1. "RX128_255OCTGB,Rx 128-255 Octets Packets Good Bad This field indicates the number of good and bad packets received with length between 128 and 255 (inclusive) bytes exclusive of the preamble." line.long 0x38 "RX_256TO511OCTETS_PACKETS_GOOD_BAD,This register provides the number of good and bad packets received by DWC_ether_qos with length between 256 and 511 (inclusive) bytes. exclusive of the preamble." hexmask.long 0x38 0.--31. 1. "RX256_511OCTGB,Rx 256-511 Octets Packets Good Bad This field indicates the number of good and bad packets received with length between 256 and 511 (inclusive) bytes exclusive of the preamble." line.long 0x3C "RX_512TO1023OCTETS_PACKETS_GOOD_BAD,This register provides the number of good and bad packets received by DWC_ether_qos with length between 512 and 1023 (inclusive) bytes. exclusive of the preamble." hexmask.long 0x3C 0.--31. 1. "RX512_1023OCTGB,RX 512-1023 Octets Packets Good Bad This field indicates the number of good and bad packets received with length between 512 and 1023 (inclusive) bytes exclusive of the preamble." line.long 0x40 "RX_1024TOMAXOCTETS_PACKETS_GOOD_BAD,This register provides the number of good and bad packets received by DWC_ether_qos with length between 1024 and maxsize (inclusive) bytes. exclusive of the preamble." hexmask.long 0x40 0.--31. 1. "RX1024_MAXOCTGB,Rx 1024-Max Octets Good Bad This field indicates the number of good and bad packets received with length between 1024 and maxsize (inclusive) bytes exclusive of the preamble." line.long 0x44 "RX_UNICAST_PACKETS_GOOD,This register provides the number of good unicast packets received by DWC_ether_qos." hexmask.long 0x44 0.--31. 1. "RXUCASTG,Rx Unicast Packets Good This field indicates the number of good unicast packets received." line.long 0x48 "RX_LENGTH_ERROR_PACKETS,This register provides the number of packets received by DWC_ether_qos with length error (Length Type field not equal to packet size). for all packets with valid length field." hexmask.long 0x48 0.--31. 1. "RXLENERR,Rx Length Error Packets This field indicates the number of packets received with length error (Length Type field not equal to packet size) for all packets with valid length field." line.long 0x4C "RX_OUT_OF_RANGE_TYPE_PACKETS,This register provides the number of packets received by DWC_ether_qos with length field not equal to the valid packet size (greater than 1.500 but less than 1.536)." hexmask.long 0x4C 0.--31. 1. "RXOUTOFRNG,Rx Out of Range Type Packet This field indicates the number of packets received with length field not equal to the valid packet size (greater than 1 500 but less than 1 536)." line.long 0x50 "RX_PAUSE_PACKETS,This register provides the number of good and valid Pause packets received by DWC_ether_qos." hexmask.long 0x50 0.--31. 1. "RXPAUSEPKT,Rx Pause Packets This field indicates the number of good and valid Pause packets received." line.long 0x54 "RX_FIFO_OVERFLOW_PACKETS,This register provides the number of missed received packets because of FIFO overflow in DWC_ether_qos." hexmask.long 0x54 0.--31. 1. "RXFIFOOVFL,Rx FIFO Overflow Packets This field indicates the number of missed received packets because of FIFO overflow." line.long 0x58 "RX_VLAN_PACKETS_GOOD_BAD,This register provides the number of good and bad VLAN packets received by DWC_ether_qos." hexmask.long 0x58 0.--31. 1. "RXVLANPKTGB,Rx VLAN Packets Good Bad This field indicates the number of good and bad VLAN packets received." line.long 0x5C "RX_WATCHDOG_ERROR_PACKETS,This register provides the number of packets received by DWC_ether_qos with error because of watchdog timeout error (packets with a data load larger than 2.048 bytes (when JE and WD bits are reset in MAC_Configuration register)." hexmask.long 0x5C 0.--31. 1. "RXWDGERR,Rx Watchdog Error Packets This field indicates the number of packets received with error because of watchdog timeout error (packets with a data load larger than 2 048 bytes (when JE and WD bits are reset in MAC_Configuration register) 10 240.." line.long 0x60 "RX_RECEIVE_ERROR_PACKETS,This register provides the number of packets received by DWC_ether_qos with Receive error or Packet Extension error on the GMII or MII interface." hexmask.long 0x60 0.--31. 1. "RXRCVERR,Rx Receive Error Packets This field indicates the number of packets received with Receive error or Packet Extension error on the GMII or MII interface." line.long 0x64 "RX_CONTROL_PACKETS_GOOD,This register provides the number of good control packets received by DWC_ether_qos." hexmask.long 0x64 0.--31. 1. "RXCTRLG,Rx Control Packets Good This field indicates the number of good control packets received." rgroup.long 0x7EC++0xF line.long 0x0 "TX_LPI_USEC_CNTR,This register provides the number of microseconds Tx LPI is asserted by DWC_ether_qos." hexmask.long 0x0 0.--31. 1. "TXLPIUSC,Tx LPI Microseconds Counter This field indicates the number of microseconds Tx LPI is asserted. For every Tx LPI Entry and Exit the Timer value can have an error of +/- 1 microsecond." line.long 0x4 "TX_LPI_TRAN_CNTR,This register provides the number of times DWC_ether_qos has entered Tx LPI." hexmask.long 0x4 0.--31. 1. "TXLPITRC,Tx LPI Transition counter This field indicates the number of times Tx LPI Entry has occurred. Even if Tx LPI Entry occurs in Automate Mode (because of LPITXA bit set in the LPI Control and Status register) the counter will increment." line.long 0x8 "RX_LPI_USEC_CNTR,This register provides the number of microseconds Rx LPI is sampled by DWC_ether_qos." hexmask.long 0x8 0.--31. 1. "RXLPIUSC,Rx LPI Microseconds Counter This field indicates the number of microseconds Rx LPI is asserted. For every Rx LPI Entry and Exit the Timer value can have an error of +/- 1 microsecond." line.long 0xC "RX_LPI_TRAN_CNTR,This register provides the number of times DWC_ether_qos has entered Rx LPI." hexmask.long 0xC 0.--31. 1. "RXLPITRC,Rx LPI Transition counter This field indicates the number of times Rx LPI Entry has occurred." group.long 0x800++0x3 line.long 0x0 "MMC_IPC_RX_INTERRUPT_MASK,This register maintains the mask for the interrupt generated from the receive IPC statistic counters. The MMC Receive Checksum Off load Interrupt Mask register maintains the masks for the interrupts generated when the receive.." rbitfld.long 0x0 30.--31. "RESERVED_31_30,Reserved." "0,1,2,3" newline bitfld.long 0x0 29. "RXICMPEROIM,MMC Receive ICMP Error Octet Counter Interrupt Mask Setting this bit masks the interrupt when the rxicmp_err_octets counter reaches half of the maximum value or the maximum value. 0x0: MMC Receive ICMP Error Octet Counter Interrupt Mask is.." "MMC Receive ICMP Error Octet Counter Interrupt..,MMC Receive ICMP Error Octet Counter Interrupt.." newline bitfld.long 0x0 28. "RXICMPGOIM,MMC Receive ICMP Good Octet Counter Interrupt Mask Setting this bit masks the interrupt when the rxicmp_gd_octets counter reaches half of the maximum value or the maximum value. 0x0: MMC Receive ICMP Good Octet Counter Interrupt Mask is.." "MMC Receive ICMP Good Octet Counter Interrupt..,MMC Receive ICMP Good Octet Counter Interrupt.." newline bitfld.long 0x0 27. "RXTCPEROIM,MMC Receive TCP Error Octet Counter Interrupt Mask Setting this bit masks the interrupt when the rxtcp_err_octets counter reaches half of the maximum value or the maximum value. 0x0: MMC Receive TCP Error Octet Counter Interrupt Mask is.." "MMC Receive TCP Error Octet Counter Interrupt..,MMC Receive TCP Error Octet Counter Interrupt.." newline bitfld.long 0x0 26. "RXTCPGOIM,MMC Receive TCP Good Octet Counter Interrupt Mask Setting this bit masks the interrupt when the rxtcp_gd_octets counter reaches half of the maximum value or the maximum value. 0x0: MMC Receive TCP Good Octet Counter Interrupt Mask is disabled.." "MMC Receive TCP Good Octet Counter Interrupt..,MMC Receive TCP Good Octet Counter Interrupt.." newline bitfld.long 0x0 25. "RXUDPEROIM,MMC Receive UDP Good Octet Counter Interrupt Mask Setting this bit masks the interrupt when the rxudp_err_octets counter reaches half of the maximum value or the maximum value. 0x0: MMC Receive UDP Good Octet Counter Interrupt Mask is disabled.." "MMC Receive UDP Good Octet Counter Interrupt..,MMC Receive UDP Good Octet Counter Interrupt.." newline bitfld.long 0x0 24. "RXUDPGOIM,MMC Receive IPV6 No Payload Octet Counter Interrupt Mask Setting this bit masks the interrupt when the rxudp_gd_octets counter reaches half of the maximum value or the maximum value. 0x0: MMC Receive IPV6 No Payload Octet Counter Interrupt Mask.." "MMC Receive IPV6 No Payload Octet Counter..,MMC Receive IPV6 No Payload Octet Counter.." newline bitfld.long 0x0 23. "RXIPV6NOPAYOIM,MMC Receive IPV6 Header Error Octet Counter Interrupt Mask Setting this bit masks the interrupt when the rxipv6_nopay_octets counter reaches half of the maximum value or the maximum value. 0x0: MMC Receive IPV6 Header Error Octet Counter.." "MMC Receive IPV6 Header Error Octet Counter..,MMC Receive IPV6 Header Error Octet Counter.." newline bitfld.long 0x0 22. "RXIPV6HEROIM,MMC Receive IPV6 Good Octet Counter Interrupt Mask Setting this bit masks the interrupt when the rxipv6_hdrerr_octets counter reaches half of the maximum value or the maximum value. 0x0: MMC Receive IPV6 Good Octet Counter Interrupt Mask is.." "MMC Receive IPV6 Good Octet Counter Interrupt..,MMC Receive IPV6 Good Octet Counter Interrupt.." newline bitfld.long 0x0 21. "RXIPV6GOIM,MMC Receive IPV6 Good Octet Counter Interrupt Mask Setting this bit masks the interrupt when the rxipv6_gd_octets counter reaches half of the maximum value or the maximum value. 0x0: MMC Receive IPV6 Good Octet Counter Interrupt Mask is.." "MMC Receive IPV6 Good Octet Counter Interrupt..,MMC Receive IPV6 Good Octet Counter Interrupt.." newline bitfld.long 0x0 20. "RXIPV4UDSBLOIM,MMC Receive IPV4 UDP Checksum Disabled Octet Counter Interrupt Mask Setting this bit masks the interrupt when the rxipv4_udsbl_octets counter reaches half of the maximum value or the maximum value. 0x0: MMC Receive IPV4 UDP Checksum.." "MMC Receive IPV4 UDP Checksum Disabled Octet..,MMC Receive IPV4 UDP Checksum Disabled Octet.." newline bitfld.long 0x0 19. "RXIPV4FRAGOIM,MMC Receive IPV4 Fragmented Octet Counter Interrupt Mask Setting this bit masks the interrupt when the rxipv4_frag_octets counter reaches half of the maximum value or the maximum value. 0x0: MMC Receive IPV4 Fragmented Octet Counter.." "MMC Receive IPV4 Fragmented Octet Counter..,MMC Receive IPV4 Fragmented Octet Counter.." newline bitfld.long 0x0 18. "RXIPV4NOPAYOIM,MMC Receive IPV4 No Payload Octet Counter Interrupt Mask Setting this bit masks the interrupt when the rxipv4_nopay_octets counter reaches half of the maximum value or the maximum value. 0x0: MMC Receive IPV4 No Payload Octet Counter.." "MMC Receive IPV4 No Payload Octet Counter..,MMC Receive IPV4 No Payload Octet Counter.." newline bitfld.long 0x0 17. "RXIPV4HEROIM,MMC Receive IPV4 Header Error Octet Counter Interrupt Mask Setting this bit masks the interrupt when the rxipv4_hdrerr_octets counter reaches half of the maximum value or the maximum value. 0x0: MMC Receive IPV4 Header Error Octet Counter.." "MMC Receive IPV4 Header Error Octet Counter..,MMC Receive IPV4 Header Error Octet Counter.." newline bitfld.long 0x0 16. "RXIPV4GOIM,MMC Receive IPV4 Good Octet Counter Interrupt Mask Setting this bit masks the interrupt when the rxipv4_gd_octets counter reaches half of the maximum value or the maximum value. 0x0: MMC Receive IPV4 Good Octet Counter Interrupt Mask is.." "MMC Receive IPV4 Good Octet Counter Interrupt..,MMC Receive IPV4 Good Octet Counter Interrupt.." newline rbitfld.long 0x0 14.--15. "RESERVED_15_14,Reserved." "0,1,2,3" newline bitfld.long 0x0 13. "RXICMPERPIM,MMC Receive ICMP Error Packet Counter Interrupt Mask Setting this bit masks the interrupt when the rxicmp_err_pkts counter reaches half of the maximum value or the maximum value. 0x0: MMC Receive ICMP Error Packet Counter Interrupt Mask is.." "MMC Receive ICMP Error Packet Counter Interrupt..,MMC Receive ICMP Error Packet Counter Interrupt.." newline bitfld.long 0x0 12. "RXICMPGPIM,MMC Receive ICMP Good Packet Counter Interrupt Mask Setting this bit masks the interrupt when the rxicmp_gd_pkts counter reaches half of the maximum value or the maximum value. 0x0: MMC Receive ICMP Good Packet Counter Interrupt Mask is.." "MMC Receive ICMP Good Packet Counter Interrupt..,MMC Receive ICMP Good Packet Counter Interrupt.." newline bitfld.long 0x0 11. "RXTCPERPIM,MMC Receive TCP Error Packet Counter Interrupt Mask Setting this bit masks the interrupt when the rxtcp_err_pkts counter reaches half of the maximum value or the maximum value. 0x0: MMC Receive TCP Error Packet Counter Interrupt Mask is.." "MMC Receive TCP Error Packet Counter Interrupt..,MMC Receive TCP Error Packet Counter Interrupt.." newline bitfld.long 0x0 10. "RXTCPGPIM,MMC Receive TCP Good Packet Counter Interrupt Mask Setting this bit masks the interrupt when the rxtcp_gd_pkts counter reaches half of the maximum value or the maximum value. 0x0: MMC Receive TCP Good Packet Counter Interrupt Mask is disabled.." "MMC Receive TCP Good Packet Counter Interrupt..,MMC Receive TCP Good Packet Counter Interrupt.." newline bitfld.long 0x0 9. "RXUDPERPIM,MMC Receive UDP Error Packet Counter Interrupt Mask Setting this bit masks the interrupt when the rxudp_err_pkts counter reaches half of the maximum value or the maximum value. 0x0: MMC Receive UDP Error Packet Counter Interrupt Mask is.." "MMC Receive UDP Error Packet Counter Interrupt..,MMC Receive UDP Error Packet Counter Interrupt.." newline bitfld.long 0x0 8. "RXUDPGPIM,MMC Receive UDP Good Packet Counter Interrupt Mask Setting this bit masks the interrupt when the rxudp_gd_pkts counter reaches half of the maximum value or the maximum value. 0x0: MMC Receive UDP Good Packet Counter Interrupt Mask is disabled.." "MMC Receive UDP Good Packet Counter Interrupt..,MMC Receive UDP Good Packet Counter Interrupt.." newline bitfld.long 0x0 7. "RXIPV6NOPAYPIM,MMC Receive IPV6 No Payload Packet Counter Interrupt Mask Setting this bit masks the interrupt when the rxipv6_nopay_pkts counter reaches half of the maximum value or the maximum value. 0x0: MMC Receive IPV6 No Payload Packet Counter.." "MMC Receive IPV6 No Payload Packet Counter..,MMC Receive IPV6 No Payload Packet Counter.." newline bitfld.long 0x0 6. "RXIPV6HERPIM,MMC Receive IPV6 Header Error Packet Counter Interrupt Mask Setting this bit masks the interrupt when the rxipv6_hdrerr_pkts counter reaches half of the maximum value or the maximum value. 0x0: MMC Receive IPV6 Header Error Packet Counter.." "MMC Receive IPV6 Header Error Packet Counter..,MMC Receive IPV6 Header Error Packet Counter.." newline bitfld.long 0x0 5. "RXIPV6GPIM,MMC Receive IPV6 Good Packet Counter Interrupt Mask Setting this bit masks the interrupt when the rxipv6_gd_pkts counter reaches half of the maximum value or the maximum value. 0x0: MMC Receive IPV6 Good Packet Counter Interrupt Mask is.." "MMC Receive IPV6 Good Packet Counter Interrupt..,MMC Receive IPV6 Good Packet Counter Interrupt.." newline bitfld.long 0x0 4. "RXIPV4UDSBLPIM,MMC Receive IPV4 UDP Checksum Disabled Packet Counter Interrupt Mask Setting this bit masks the interrupt when the rxipv4_udsbl_pkts counter reaches half of the maximum value or the maximum value. 0x0: MMC Receive IPV4 UDP Checksum.." "MMC Receive IPV4 UDP Checksum Disabled Packet..,MMC Receive IPV4 UDP Checksum Disabled Packet.." newline bitfld.long 0x0 3. "RXIPV4FRAGPIM,MMC Receive IPV4 Fragmented Packet Counter Interrupt Mask Setting this bit masks the interrupt when the rxipv4_frag_pkts counter reaches half of the maximum value or the maximum value. 0x0: MMC Receive IPV4 Fragmented Packet Counter.." "MMC Receive IPV4 Fragmented Packet Counter..,MMC Receive IPV4 Fragmented Packet Counter.." newline bitfld.long 0x0 2. "RXIPV4NOPAYPIM,MMC Receive IPV4 No Payload Packet Counter Interrupt Mask Setting this bit masks the interrupt when the rxipv4_nopay_pkts counter reaches half of the maximum value or the maximum value. 0x0: MMC Receive IPV4 No Payload Packet Counter.." "MMC Receive IPV4 No Payload Packet Counter..,MMC Receive IPV4 No Payload Packet Counter.." newline bitfld.long 0x0 1. "RXIPV4HERPIM,MMC Receive IPV4 Header Error Packet Counter Interrupt Mask Setting this bit masks the interrupt when the rxipv4_hdrerr_pkts counter reaches half of the maximum value or the maximum value. 0x0: MMC Receive IPV4 Header Error Packet Counter.." "MMC Receive IPV4 Header Error Packet Counter..,MMC Receive IPV4 Header Error Packet Counter.." newline bitfld.long 0x0 0. "RXIPV4GPIM,MMC Receive IPV4 Good Packet Counter Interrupt Mask Setting this bit masks the interrupt when the rxipv4_gd_pkts counter reaches half of the maximum value or the maximum value. 0x0: MMC Receive IPV4 Good Packet Counter Interrupt Mask is.." "MMC Receive IPV4 Good Packet Counter Interrupt..,MMC Receive IPV4 Good Packet Counter Interrupt.." rgroup.long 0x808++0x3 line.long 0x0 "MMC_IPC_RX_INTERRUPT,This register maintains the interrupt that the receive IPC statistic counters generate. The MMC Receive Checksum Offload Interrupt register maintains the interrupts generated when receive IPC statistic counters reach half their.." bitfld.long 0x0 30.--31. "RESERVED_31_30,Reserved." "0,1,2,3" newline bitfld.long 0x0 29. "RXICMPEROIS,MMC Receive ICMP Error Octet Counter Interrupt Status This bit is set when the rxicmp_err_octets counter reaches half of the maximum value or the maximum value. Access restriction applies. Clears on read. Self-set to 1 on internal event. 0x1:.." "MMC Receive ICMP Error Octet Counter Interrupt..,MMC Receive ICMP Error Octet Counter Interrupt.." newline bitfld.long 0x0 28. "RXICMPGOIS,MMC Receive ICMP Good Octet Counter Interrupt Status This bit is set when the rxicmp_gd_octets counter reaches half of the maximum value or the maximum value. Access restriction applies. Clears on read. Self-set to 1 on internal event. 0x1:.." "MMC Receive ICMP Good Octet Counter Interrupt..,MMC Receive ICMP Good Octet Counter Interrupt.." newline bitfld.long 0x0 27. "RXTCPEROIS,MMC Receive TCP Error Octet Counter Interrupt Status This bit is set when the rxtcp_err_octets counter reaches half of the maximum value or the maximum value. Access restriction applies. Clears on read. Self-set to 1 on internal event. 0x1:.." "MMC Receive TCP Error Octet Counter Interrupt..,MMC Receive TCP Error Octet Counter Interrupt.." newline bitfld.long 0x0 26. "RXTCPGOIS,MMC Receive TCP Good Octet Counter Interrupt Status This bit is set when the rxtcp_gd_octets counter reaches half of the maximum value or the maximum value. Access restriction applies. Clears on read. Self-set to 1 on internal event. 0x1: MMC.." "MMC Receive TCP Good Octet Counter Interrupt..,MMC Receive TCP Good Octet Counter Interrupt.." newline bitfld.long 0x0 25. "RXUDPEROIS,MMC Receive UDP Error Octet Counter Interrupt Status This bit is set when the rxudp_err_octets counter reaches half of the maximum value or the maximum value. Access restriction applies. Clears on read. Self-set to 1 on internal event. 0x1:.." "MMC Receive UDP Error Octet Counter Interrupt..,MMC Receive UDP Error Octet Counter Interrupt.." newline bitfld.long 0x0 24. "RXUDPGOIS,MMC Receive UDP Good Octet Counter Interrupt Status This bit is set when the rxudp_gd_octets counter reaches half of the maximum value or the maximum value. Access restriction applies. Clears on read. Self-set to 1 on internal event. 0x1: MMC.." "MMC Receive UDP Good Octet Counter Interrupt..,MMC Receive UDP Good Octet Counter Interrupt.." newline bitfld.long 0x0 23. "RXIPV6NOPAYOIS,MMC Receive IPV6 No Payload Octet Counter Interrupt Status This bit is set when the rxipv6_nopay_octets counter reaches half of the maximum value or the maximum value. Access restriction applies. Clears on read. Self-set to 1 on internal.." "MMC Receive IPV6 No Payload Octet Counter..,MMC Receive IPV6 No Payload Octet Counter.." newline bitfld.long 0x0 22. "RXIPV6HEROIS,MMC Receive IPV6 Header Error Octet Counter Interrupt Status This bit is set when the rxipv6_hdrerr_octets counter reaches half of the maximum value or the maximum value. Access restriction applies. Clears on read. Self-set to 1 on internal.." "MMC Receive IPV6 Header Error Octet Counter..,MMC Receive IPV6 Header Error Octet Counter.." newline bitfld.long 0x0 21. "RXIPV6GOIS,MMC Receive IPV6 Good Octet Counter Interrupt Status This bit is set when the rxipv6_gd_octets counter reaches half of the maximum value or the maximum value. Access restriction applies. Clears on read. Self-set to 1 on internal event. 0x1:.." "MMC Receive IPV6 Good Octet Counter Interrupt..,MMC Receive IPV6 Good Octet Counter Interrupt.." newline bitfld.long 0x0 20. "RXIPV4UDSBLOIS,MMC Receive IPV4 UDP Checksum Disabled Octet Counter Interrupt Status This bit is set when the rxipv4_udsbl_octets counter reaches half of the maximum value or the maximum value. Access restriction applies. Clears on read. Self-set to 1 on.." "MMC Receive IPV4 UDP Checksum Disabled Octet..,MMC Receive IPV4 UDP Checksum Disabled Octet.." newline bitfld.long 0x0 19. "RXIPV4FRAGOIS,MMC Receive IPV4 Fragmented Octet Counter Interrupt Status This bit is set when the rxipv4_frag_octets counter reaches half of the maximum value or the maximum value. Access restriction applies. Clears on read. Self-set to 1 on internal.." "MMC Receive IPV4 Fragmented Octet Counter..,MMC Receive IPV4 Fragmented Octet Counter.." newline bitfld.long 0x0 18. "RXIPV4NOPAYOIS,MMC Receive IPV4 No Payload Octet Counter Interrupt Status This bit is set when the rxipv4_nopay_octets counter reaches half of the maximum value or the maximum value. Access restriction applies. Clears on read. Self-set to 1 on internal.." "MMC Receive IPV4 No Payload Octet Counter..,MMC Receive IPV4 No Payload Octet Counter.." newline bitfld.long 0x0 17. "RXIPV4HEROIS,MMC Receive IPV4 Header Error Octet Counter Interrupt Status This bit is set when the rxipv4_hdrerr_octets counter reaches half of the maximum value or the maximum value. Access restriction applies. Clears on read. Self-set to 1 on internal.." "MMC Receive IPV4 Header Error Octet Counter..,MMC Receive IPV4 Header Error Octet Counter.." newline bitfld.long 0x0 16. "RXIPV4GOIS,MMC Receive IPV4 Good Octet Counter Interrupt Status This bit is set when the rxipv4_gd_octets counter reaches half of the maximum value or the maximum value. Access restriction applies. Clears on read. Self-set to 1 on internal event. 0x1:.." "MMC Receive IPV4 Good Octet Counter Interrupt..,MMC Receive IPV4 Good Octet Counter Interrupt.." newline bitfld.long 0x0 14.--15. "RESERVED_15_14,Reserved." "0,1,2,3" newline bitfld.long 0x0 13. "RXICMPERPIS,MMC Receive ICMP Error Packet Counter Interrupt Status This bit is set when the rxicmp_err_pkts counter reaches half of the maximum value or the maximum value. Access restriction applies. Clears on read. Self-set to 1 on internal event. 0x1:.." "MMC Receive ICMP Error Packet Counter Interrupt..,MMC Receive ICMP Error Packet Counter Interrupt.." newline bitfld.long 0x0 12. "RXICMPGPIS,MMC Receive ICMP Good Packet Counter Interrupt Status This bit is set when the rxicmp_gd_pkts counter reaches half of the maximum value or the maximum value. Access restriction applies. Clears on read. Self-set to 1 on internal event. 0x1: MMC.." "MMC Receive ICMP Good Packet Counter Interrupt..,MMC Receive ICMP Good Packet Counter Interrupt.." newline bitfld.long 0x0 11. "RXTCPERPIS,MMC Receive TCP Error Packet Counter Interrupt Status This bit is set when the rxtcp_err_pkts counter reaches half of the maximum value or the maximum value. Access restriction applies. Clears on read. Self-set to 1 on internal event. 0x1: MMC.." "MMC Receive TCP Error Packet Counter Interrupt..,MMC Receive TCP Error Packet Counter Interrupt.." newline bitfld.long 0x0 10. "RXTCPGPIS,MMC Receive TCP Good Packet Counter Interrupt Status This bit is set when the rxtcp_gd_pkts counter reaches half of the maximum value or the maximum value. Access restriction applies. Clears on read. Self-set to 1 on internal event. 0x1: MMC.." "MMC Receive TCP Good Packet Counter Interrupt..,MMC Receive TCP Good Packet Counter Interrupt.." newline bitfld.long 0x0 9. "RXUDPERPIS,MMC Receive UDP Error Packet Counter Interrupt Status This bit is set when the rxudp_err_pkts counter reaches half of the maximum value or the maximum value. Access restriction applies. Clears on read. Self-set to 1 on internal event. 0x1: MMC.." "MMC Receive UDP Error Packet Counter Interrupt..,MMC Receive UDP Error Packet Counter Interrupt.." newline bitfld.long 0x0 8. "RXUDPGPIS,MC Receive UDP Good Packet Counter Interrupt Status This bit is set when the rxudp_gd_pkts counter reaches half of the maximum value or the maximum value. Access restriction applies. Clears on read. Self-set to 1 on internal event. 0x1: MMC.." "MMC Receive UDP Good Packet Counter Interrupt..,MMC Receive UDP Good Packet Counter Interrupt.." newline bitfld.long 0x0 7. "RXIPV6NOPAYPIS,MMC Receive IPV6 No Payload Packet Counter Interrupt Status This bit is set when the rxipv6_nopay_pkts counter reaches half of the maximum value or the maximum value. Access restriction applies. Clears on read. Self-set to 1 on internal.." "MMC Receive IPV6 No Payload Packet Counter..,MMC Receive IPV6 No Payload Packet Counter.." newline bitfld.long 0x0 6. "RXIPV6HERPIS,MMC Receive IPV6 Header Error Packet Counter Interrupt Status This bit is set when the rxipv6_hdrerr_pkts counter reaches half of the maximum value or the maximum value. Access restriction applies. Clears on read. Self-set to 1 on internal.." "MMC Receive IPV6 Header Error Packet Counter..,MMC Receive IPV6 Header Error Packet Counter.." newline bitfld.long 0x0 5. "RXIPV6GPIS,MMC Receive IPV6 Good Packet Counter Interrupt Status This bit is set when the rxipv6_gd_pkts counter reaches half of the maximum value or the maximum value. Access restriction applies. Clears on read. Self-set to 1 on internal event. 0x1: MMC.." "MMC Receive IPV6 Good Packet Counter Interrupt..,MMC Receive IPV6 Good Packet Counter Interrupt.." newline bitfld.long 0x0 4. "RXIPV4UDSBLPIS,MMC Receive IPV4 UDP Checksum Disabled Packet Counter Interrupt Status This bit is set when the rxipv4_udsbl_pkts counter reaches half of the maximum value or the maximum value. 0x1: MMC Receive IPV4 UDP Checksum Disabled Packet Counter.." "MMC Receive IPV4 UDP Checksum Disabled Packet..,MMC Receive IPV4 UDP Checksum Disabled Packet.." newline bitfld.long 0x0 3. "RXIPV4FRAGPIS,MMC Receive IPV4 Fragmented Packet Counter Interrupt Status This bit is set when the rxipv4_frag_pkts counter reaches half of the maximum value or the maximum value. Access restriction applies. Clears on read. Self-set to 1 on internal.." "MMC Receive IPV4 Fragmented Packet Counter..,MMC Receive IPV4 Fragmented Packet Counter.." newline bitfld.long 0x0 2. "RXIPV4NOPAYPIS,MMC Receive IPV4 No Payload Packet Counter Interrupt Status This bit is set when the rxipv4_nopay_pkts counter reaches half of the maximum value or the maximum value. Access restriction applies. Clears on read. Self-set to 1 on internal.." "MMC Receive IPV4 No Payload Packet Counter..,MMC Receive IPV4 No Payload Packet Counter.." newline bitfld.long 0x0 1. "RXIPV4HERPIS,MMC Receive IPV4 Header Error Packet Counter Interrupt Status This bit is set when the rxipv4_hdrerr_pkts counter reaches half of the maximum value or the maximum value. Access restriction applies. Clears on read. Self-set to 1 on internal.." "MMC Receive IPV4 Header Error Packet Counter..,MMC Receive IPV4 Header Error Packet Counter.." newline bitfld.long 0x0 0. "RXIPV4GPIS,MMC Receive IPV4 Good Packet Counter Interrupt Status This bit is set when the rxipv4_gd_pkts counter reaches half of the maximum value or the maximum value. Access restriction applies. Clears on read. Self-set to 1 on internal event. 0x1: MMC.." "MMC Receive IPV4 Good Packet Counter Interrupt..,MMC Receive IPV4 Good Packet Counter Interrupt.." rgroup.long 0x810++0x37 line.long 0x0 "RXIPV4_GOOD_PACKETS,This register provides the number of good IPv4 datagrams received by DWC_ether_qos with the TCP. UDP. or ICMP payload." hexmask.long 0x0 0.--31. 1. "RXIPV4GDPKT,RxIPv4 Good Packets This field indicates the number of good IPv4 datagrams received with the TCP UDP or ICMP payload." line.long 0x4 "RXIPV4_HEADER_ERROR_PACKETS,RxIPv4 Header Error Packets This register provides the number of IPv4 datagrams received by DWC_ether_qos with header (checksum. length. or version mismatch) errors." hexmask.long 0x4 0.--31. 1. "RXIPV4HDRERRPKT,RxIPv4 Header Error Packets This field indicates the number of IPv4 datagrams received with header (checksum length or version mismatch) errors." line.long 0x8 "RXIPV4_NO_PAYLOAD_PACKETS,This register provides the number of IPv4 datagram packets received by DWC_ether_qos that did not have a TCP. UDP. or ICMP payload." hexmask.long 0x8 0.--31. 1. "RXIPV4NOPAYPKT,RxIPv4 Payload Packets This field indicates the number of IPv4 datagram packets received that did not have a TCP UDP or ICMP payload." line.long 0xC "RXIPV4_FRAGMENTED_PACKETS,This register provides the number of good IPv4 datagrams received by DWC_ether_qos with fragmentation." hexmask.long 0xC 0.--31. 1. "RXIPV4FRAGPKT,RxIPv4 Fragmented Packets This field indicates the number of good IPv4 datagrams received with fragmentation." line.long 0x10 "RXIPV4_UDP_CHECKSUM_DISABLED_PACKETS,This register provides the number of good IPv4 datagrams received by DWC_ether_qos that had a UDP payload with checksum disabled." hexmask.long 0x10 0.--31. 1. "RXIPV4UDSBLPKT,RxIPv4 UDP Checksum Disabled Packets This field indicates the number of good IPv4 datagrams received that had a UDP payload with checksum disabled." line.long 0x14 "RXIPV6_GOOD_PACKETS,This register provides the number of good IPv6 datagrams received by DWC_ether_qos with the TCP. UDP. or ICMP payload." hexmask.long 0x14 0.--31. 1. "RXIPV6GDPKT,RxIPv6 Good Packets This field indicates the number of good IPv6 datagrams received with the TCP UDP or ICMP payload." line.long 0x18 "RXIPV6_HEADER_ERROR_PACKETS,This register provides the number of IPv6 datagrams received by DWC_ether_qos with header (length or version mismatch) errors." hexmask.long 0x18 0.--31. 1. "RXIPV6HDRERRPKT,RxIPv6 Header Error Packets This field indicates the number of IPv6 datagrams received with header (length or version mismatch) errors." line.long 0x1C "RXIPV6_NO_PAYLOAD_PACKETS,This register provides the number of IPv6 datagram packets received by DWC_ether_qos that did not have a TCP. UDP. or ICMP payload. This includes all IPv6 datagrams with fragmentation or security extension headers." hexmask.long 0x1C 0.--31. 1. "RXIPV6NOPAYPKT,RxIPv6 Payload Packets This field indicates the number of IPv6 datagram packets received that did not have a TCP UDP or ICMP payload. This includes all IPv6 datagrams with fragmentation or security extension headers." line.long 0x20 "RXUDP_GOOD_PACKETS,This register provides the number of good IP datagrams received by DWC_ether_qos with a good UDP payload. This counter is not updated when the RxIPv4_UDP_Checksum_Disabled_Packets counter is incremented." hexmask.long 0x20 0.--31. 1. "RXUDPGDPKT,RxUDP Good Packets This field indicates the number of good IP datagrams received with a good UDP payload. This counter is not updated when the RxIPv4_UDP_Checksum_Disabled_Packets counter is incremented." line.long 0x24 "RXUDP_ERROR_PACKETS,This register provides the number of good IP datagrams received by DWC_ether_qos whose UDP payload has a checksum error." hexmask.long 0x24 0.--31. 1. "RXUDPERRPKT,RxUDP Error Packets This field indicates the number of good IP datagrams received whose UDP payload has a checksum error." line.long 0x28 "RXTCP_GOOD_PACKETS,This register provides the number of good IP datagrams received by DWC_ether_qos with a good TCP payload." hexmask.long 0x28 0.--31. 1. "RXTCPGDPKT,RxTCP Good Packets This field indicates the number of good IP datagrams received with a good TCP payload." line.long 0x2C "RXTCP_ERROR_PACKETS,This register provides the number of good IP datagrams received by DWC_ether_qos whose TCP payload has a checksum error." hexmask.long 0x2C 0.--31. 1. "RXTCPERRPKT,RxTCP Error Packets This field indicates the number of good IP datagrams received whose TCP payload has a checksum error." line.long 0x30 "RXICMP_GOOD_PACKETS,This register provides the number of good IP datagrams received by DWC_ether_qos with a good ICMP payload." hexmask.long 0x30 0.--31. 1. "RXICMPGDPKT,RxICMP Good Packets This field indicates the number of good IP datagrams received with a good ICMP payload." line.long 0x34 "RXICMP_ERROR_PACKETS,This register provides the number of good IP datagrams received by DWC_ether_qos whose ICMP payload has a checksum error." hexmask.long 0x34 0.--31. 1. "RXICMPERRPKT,RxICMP Error Packets This field indicates the number of good IP datagrams received whose ICMP payload has a checksum error." rgroup.long 0x850++0x37 line.long 0x0 "RXIPV4_GOOD_OCTETS,This register provides the number of bytes received by DWC_ether_qos in good IPv4 datagrams encapsulating TCP. UDP. or ICMP data. (Ethernet header. FCS. pad. or IP pad bytes are not included in this counter." hexmask.long 0x0 0.--31. 1. "RXIPV4GDOCT,RxIPv4 Good Octets This field indicates the number of bytes received in good IPv4 datagrams encapsulating TCP UDP or ICMP data. (Ethernet header FCS pad or IP pad bytes are not included in this counter." line.long 0x4 "RXIPV4_HEADER_ERROR_OCTETS,This register provides the number of bytes received by DWC_ether_qos in IPv4 datagrams with header errors (checksum. length. version mismatch). The value in the Length field of IPv4 header is used to update this counter." hexmask.long 0x4 0.--31. 1. "RXIPV4HDRERROCT,RxIPv4 Header Error Octets This field indicates the number of bytes received in IPv4 datagrams with header errors (checksum length version mismatch). The value in the Length field of IPv4 header is used to update this counter. (Ethernet.." line.long 0x8 "RXIPV4_NO_PAYLOAD_OCTETS,This register provides the number of bytes received by DWC_ether_qos in IPv4 datagrams that did not have a TCP. UDP. or ICMP payload. The value in the Length field of IPv4 header is used to update this counter. (Ethernet header." hexmask.long 0x8 0.--31. 1. "RXIPV4NOPAYOCT,RxIPv4 Payload Octets This field indicates the number of bytes received in IPv4 datagrams that did not have a TCP UDP or ICMP payload. The value in the Length field of IPv4 header is used to update this counter. (Ethernet header FCS.." line.long 0xC "RXIPV4_FRAGMENTED_OCTETS,This register provides the number of bytes received by DWC_ether_qos in fragmented IPv4 datagrams. The value in the Length field of IPv4 header is used to update this counter. (Ethernet header. FCS. pad. or IP pad bytes are not.." hexmask.long 0xC 0.--31. 1. "RXIPV4FRAGOCT,RxIPv4 Fragmented Octets This field indicates the number of bytes received in fragmented IPv4 datagrams. The value in the Length field of IPv4 header is used to update this counter. (Ethernet header FCS pad or IP pad bytes are not.." line.long 0x10 "RXIPV4_UDP_CHECKSUM_DISABLE_OCTETS,This register provides the number of bytes received by DWC_ether_qos in a UDP segment that had the UDP checksum disabled. This counter does not count IP Header bytes. (Ethernet header. FCS. pad. or IP pad bytes are not.." hexmask.long 0x10 0.--31. 1. "RXIPV4UDSBLOCT,RxIPv4 UDP Checksum Disable Octets This field indicates the number of bytes received in a UDP segment that had the UDP checksum disabled. This counter does not count IP Header bytes. (Ethernet header FCS pad or IP pad bytes are not.." line.long 0x14 "RXIPV6_GOOD_OCTETS,This register provides the number of bytes received by DWC_ether_qos in good IPv6 datagrams encapsulating TCP. UDP. or ICMP data. (Ethernet header. FCS. pad. or IP pad bytes are not included in this counter." hexmask.long 0x14 0.--31. 1. "RXIPV6GDOCT,RxIPv6 Good Octets This field indicates the number of bytes received in good IPv6 datagrams encapsulating TCP UDP or ICMP data. (Ethernet header FCS pad or IP pad bytes are not included in this counter." line.long 0x18 "RXIPV6_HEADER_ERROR_OCTETS,This register provides the number of bytes received by DWC_ether_qos in IPv6 datagrams with header errors (length. version mismatch). The value in the Length field of IPv6 header is used to update this counter. (Ethernet.." hexmask.long 0x18 0.--31. 1. "RXIPV6HDRERROCT,RxIPv6 Header Error Octets This field indicates the number of bytes received in IPv6 datagrams with header errors (length version mismatch). The value in the Length field of IPv6 header is used to update this counter. (Ethernet header.." line.long 0x1C "RXIPV6_NO_PAYLOAD_OCTETS,This register provides the number of bytes received by DWC_ether_qos in IPv6 datagrams that did not have a TCP. UDP. or ICMP payload. The value in the Length field of IPv6 header is used to update this counter. (Ethernet header." hexmask.long 0x1C 0.--31. 1. "RXIPV6NOPAYOCT,RxIPv6 Payload Octets This field indicates the number of bytes received in IPv6 datagrams that did not have a TCP UDP or ICMP payload. The value in the Length field of IPv6 header is used to update this counter. (Ethernet header FCS.." line.long 0x20 "RXUDP_GOOD_OCTETS,This register provides the number of bytes received by DWC_ether_qos in a good UDP segment. This counter does not count IP header bytes." hexmask.long 0x20 0.--31. 1. "RXUDPGDOCT,RxUDP Good Octets This field indicates the number of bytes received in a good UDP segment. This counter does not count IP header bytes." line.long 0x24 "RXUDP_ERROR_OCTETS,This register provides the number of bytes received by DWC_ether_qos in a UDP segment that had checksum errors. This counter does not count IP header bytes." hexmask.long 0x24 0.--31. 1. "RXUDPERROCT,RxUDP Error Octets This field indicates the number of bytes received in a UDP segment that had checksum errors. This counter does not count IP header bytes." line.long 0x28 "RXTCP_GOOD_OCTETS,This register provides the number of bytes received by DWC_ether_qos in a good TCP segment. This counter does not count IP header bytes." hexmask.long 0x28 0.--31. 1. "RXTCPGDOCT,RxTCP Good Octets This field indicates the number of bytes received in a good TCP segment. This counter does not count IP header bytes." line.long 0x2C "RXTCP_ERROR_OCTETS,This register provides the number of bytes received by DWC_ether_qos in a TCP segment that had checksum errors. This counter does not count IP header bytes." hexmask.long 0x2C 0.--31. 1. "RXTCPERROCT,RxTCP Error Octets This field indicates the number of bytes received in a TCP segment that had checksum errors. This counter does not count IP header bytes." line.long 0x30 "RXICMP_GOOD_OCTETS,This register provides the number of bytes received by DWC_ether_qos in a good ICMP segment. This counter does not count IP header bytes." hexmask.long 0x30 0.--31. 1. "RXICMPGDOCT,RxICMP Good Octets This field indicates the number of bytes received in a good ICMP segment. This counter does not count IP header bytes." line.long 0x34 "RXICMP_ERROR_OCTETS,This register provides the number of bytes received by DWC_ether_qos in a ICMP segment that had checksum errors. This counter does not count IP header bytes." hexmask.long 0x34 0.--31. 1. "RXICMPERROCT,RxICMP Error Octets This field indicates the number of bytes received in a ICMP segment that had checksum errors. This counter does not count IP header bytes." rgroup.long 0x8A0++0x3 line.long 0x0 "MMC_FPE_TX_INTERRUPT,This register maintains the interrupts generated from all FPE related Transmit statistics counters. The MMC FPE Transmit Interrupt register maintains the interrupts generated when transmit statistic counters reach half their maximum.." hexmask.long 0x0 2.--31. 1. "RESERVED_31_2,Reserved." newline bitfld.long 0x0 1. "HRCIS,MMC Tx Hold Request Counter Interrupt Status This bit is set when the Tx_Hold_Req_Cntr counter reaches half of the maximum value or the maximum value. Access restriction applies. Clears on read. Self-set to 1 on internal event. Exists when any one.." "MMC Tx Hold Request Counter Interrupt Status not..,MMC Tx Hold Request Counter Interrupt Status.." newline bitfld.long 0x0 0. "FCIS,MMC Tx FPE Fragment Counter Interrupt status This bit is set when the Tx_FPE_Fragment_Cntr counter reaches half of the maximum value or the maximum value. Access restriction applies. Clears on read. Self-set to 1 on internal event. Exists when any.." "MMC Tx FPE Fragment Counter Interrupt status not..,MMC Tx FPE Fragment Counter Interrupt status.." group.long 0x8A4++0x3 line.long 0x0 "MMC_FPE_TX_INTERRUPT_MASK,This register maintains the masks for interrupts generated from all FPE related Transmit statistics counters. The MMC Receive Interrupt Mask register maintains the masks for the interrupts generated when FPE related receive.." hexmask.long 0x0 2.--31. 1. "RESERVED_31_2,Reserved." newline bitfld.long 0x0 1. "HRCIM,MMC Transmit Hold Request Counter Interrupt Mask Setting this bit masks the interrupt when the Tx_Hold_Req_Cntr counter reaches half of the maximum value or the maximum value. Exists when any one of the RX/TX MMC counters are enabled during FPE.." "MMC Transmit Hold Request Counter Interrupt Mask..,MMC Transmit Hold Request Counter Interrupt Mask.." newline bitfld.long 0x0 0. "FCIM,MMC Transmit Fragment Counter Interrupt Mask Setting this bit masks the interrupt when the Tx_FPE_Fragment_Cntr counter reaches half of the maximum value or the maximum value. Exists when any one of the RX/TX MMC counters are enabled during FPE.." "MMC Transmit Fragment Counter Interrupt Mask is..,MMC Transmit Fragment Counter Interrupt Mask is.." rgroup.long 0x8A8++0x7 line.long 0x0 "MMC_TX_FPE_FRAGMENT_CNTR,This register provides the number of additional mPackets transmitted due to preemption." hexmask.long 0x0 0.--31. 1. "TXFFC,Tx FPE Fragment counter This field indicates the number of additional mPackets that has been transmitted due to preemption Exists when any one of the RX/TX MMC counters are enabled during FPE Enabled configuration." line.long 0x4 "MMC_TX_HOLD_REQ_CNTR,This register provides the count of number of times a hold request is given to MAC" hexmask.long 0x4 0.--31. 1. "TXHRC,Tx Hold Request Counter This field indicates count of number of a hold request is given to MAC. Exists when any one of the RX/TX MMC counters are enabled during FPE with AV_EST Enabled configuration." rgroup.long 0x8C0++0x3 line.long 0x0 "MMC_FPE_RX_INTERRUPT,This register maintains the interrupts generated from all FPE related Receive statistics counters. The MMC FPE Receive Interrupt register maintains the interrupts generated when transmit statistic counters reach half their maximum.." hexmask.long 0x0 4.--31. 1. "RESERVED_31_4,Reserved." newline bitfld.long 0x0 3. "FCIS,MMC Rx FPE Fragment Counter Interrupt Status This bit is set when the Rx_FPE_Fragment_Cntr counter reaches half of the maximum value or the maximum value. Access restriction applies. Clears on read. Self-set to 1 on internal event. Exists when any.." "MMC Rx FPE Fragment Counter Interrupt Status not..,MMC Rx FPE Fragment Counter Interrupt Status.." newline bitfld.long 0x0 2. "PAOCIS,MMC Rx Packet Assembly OK Counter Interrupt Status This bit is set when the Rx_Packet_Assemble_Ok_Cntr counter reaches half of the maximum value or the maximum value. Access restriction applies. Clears on read. Self-set to 1 on internal event." "MMC Rx Packet Assembly OK Counter Interrupt..,MMC Rx Packet Assembly OK Counter Interrupt.." newline bitfld.long 0x0 1. "PSECIS,MMC Rx Packet SMD Error Counter Interrupt Status This bit is set when the Rx_Packet_SMD_Err_Cntr counter reaches half of the maximum value or the maximum value. Access restriction applies. Clears on read. Self-set to 1 on internal event. Exists.." "MMC Rx Packet SMD Error Counter Interrupt Status..,MMC Rx Packet SMD Error Counter Interrupt Status.." newline bitfld.long 0x0 0. "PAECIS,MMC Rx Packet Assembly Error Counter Interrupt Status This bit is set when the Rx_Packet_Assemble_Err_Cntr counter reaches half of the maximum value or the maximum value. Access restriction applies. Clears on read. Self-set to 1 on internal event." "MMC Rx Packet Assembly Error Counter Interrupt..,MMC Rx Packet Assembly Error Counter Interrupt.." group.long 0x8C4++0x3 line.long 0x0 "MMC_FPE_RX_INTERRUPT_MASK,This register maintains the masks for interrupts generated from all FPE related Receive statistics counters. The MMC Receive Interrupt Mask register maintains the masks for the interrupts generated when FPE related receive.." hexmask.long 0x0 4.--31. 1. "RESERVED_31_4,Reserved." newline bitfld.long 0x0 3. "FCIM,MMC Rx FPE Fragment Counter Interrupt Mask Setting this bit masks the interrupt when the Tx_FPE_Fragment_Cntr counter reaches half of the maximum value or the maximum value. Exists when any one of the RX/TX MMC counters are enabled during FPE.." "MMC Rx FPE Fragment Counter Interrupt Mask is..,MMC Rx FPE Fragment Counter Interrupt Mask is.." newline bitfld.long 0x0 2. "PAOCIM,MMC Rx Packet Assembly OK Counter Interrupt Mask Setting this bit masks the interrupt when the Rx_Packet_Assemble_Ok_Cntr counter reaches half of the maximum value or the maximum value. Exists when any one of the RX/TX MMC counters are enabled.." "MMC Rx Packet Assembly OK Counter Interrupt Mask..,MMC Rx Packet Assembly OK Counter Interrupt Mask.." newline bitfld.long 0x0 1. "PSECIM,MMC Rx Packet SMD Error Counter Interrupt Mask Setting this bit masks the interrupt when the R Rx_Packet_SMD_Err_Cntr counter reaches half of the maximum value or the maximum value. Exists when any one of the RX/TX MMC counters are enabled during.." "MMC Rx Packet SMD Error Counter Interrupt Mask..,MMC Rx Packet SMD Error Counter Interrupt Mask.." newline bitfld.long 0x0 0. "PAECIM,MMC Rx Packet Assembly Error Counter Interrupt Mask Setting this bit masks the interrupt when the R Rx_Packet_Assemble_Err_Cntr counter reaches half of the maximum value or the maximum value. Exists when any one of the RX/TX MMC counters are.." "MMC Rx Packet Assembly Error Counter Interrupt..,MMC Rx Packet Assembly Error Counter Interrupt.." rgroup.long 0x8C8++0xF line.long 0x0 "MMC_RX_PACKET_ASSEMBLY_ERR_CNTR,This register provides the number of MAC frames with reassembly errors on the Receiver. due to mismatch in the Fragment Count value." hexmask.long 0x0 0.--31. 1. "PAEC,Rx Packet Assembly Error Counter This field indicates the number of MAC frames with reassembly errors on the Receiver due to mismatch in the Fragment Count value. Exists when any one of the RX/TX MMC counters are enabled during FPE Enabled.." line.long 0x4 "MMC_RX_PACKET_SMD_ERR_CNTR,This register provides the number of received MAC frames rejected due to unknown SMD value and MAC frame fragments rejected due to arriving with an SMD-C when there was no preceding preempted frame." hexmask.long 0x4 0.--31. 1. "PSEC,Rx Packet SMD Error Counter This field indicates the number of MAC frames rejected due to unknown SMD value and MAC frame fragments rejected due to arriving with an SMD-C when there was no preceding preempted frame. Exists when at least one of the.." line.long 0x8 "MMC_RX_PACKET_ASSEMBLY_OK_CNTR,This register provides the number of MAC frames that were successfully reassembled and delivered to MAC." hexmask.long 0x8 0.--31. 1. "PAOC,Rx Packet Assembly OK Counter This field indicates the number of MAC frames that were successfully reassembled and delivered to MAC. Exists when at least one of the RX/TX MMC counters are enabled during FPE Enabled configuration." line.long 0xC "MMC_RX_FPE_FRAGMENT_CNTR,This register provides the number of additional mPackets received due to preemption." hexmask.long 0xC 0.--31. 1. "FFC,Rx FPE Fragment Counter This field indicates the number of additional mPackets received due to preemption Exists when at least one of the RX/TX MMC counters are enabled during FPE Enabled configuration." repeat 4. (list 0x0 0x1 0x2 0x3 )(list 0x0 0x30 0x60 0x90 ) group.long ($2+0x900)++0x3 line.long 0x0 "MAC_L3_L4_CONTROL$1,The Layer 3 and Layer 4 Control register controls the operations of filter 0 of Layer 3 and Layer 4." rbitfld.long 0x0 29.--31. "RESERVED_31_29,Reserved." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 28. "DMCHEN0,DMA Channel Select Enable When set this bit enables the selection of the DMA channel number for the packet that is passed by this L3_L4 filter. The DMA channel is indicated by the DMCHN bits. When this bit is reset the DMA channel is not.." "DMA Channel Select is disabled,DMA Channel Select is enabled" newline rbitfld.long 0x0 27. "RESERVED_27_Y,Reserved." "0,1" newline bitfld.long 0x0 24.--26. "DMCHN0,DMA Channel Number When DMCHEN is set high this field selects the DMA Channel number to which the packet passed by this filter is routed. The width of this field depends on the number of the DMA channels present in your configuration." "0,1,2,3,4,5,6,7" newline rbitfld.long 0x0 22.--23. "RESERVED_23_22,Reserved." "0,1,2,3" newline bitfld.long 0x0 21. "L4DPIM0,Layer 4 Destination Port Inverse Match Enable When this bit is set the Layer 4 Destination Port number field is enabled for inverse matching. When this bit is reset the Layer 4 Destination Port number field is enabled for perfect matching. This.." "Layer 4 Destination Port Inverse Match is disabled,Layer 4 Destination Port Inverse Match is enabled" newline bitfld.long 0x0 20. "L4DPM0,Layer 4 Destination Port Match Enable When this bit is set the Layer 4 Destination Port number field is enabled for matching. When this bit is reset the MAC ignores the Layer 4 Destination Port number field for matching. 0x0: Layer 4 Destination.." "Layer 4 Destination Port Match is disabled,Layer 4 Destination Port Match is enabled" newline bitfld.long 0x0 19. "L4SPIM0,Layer 4 Source Port Inverse Match Enable When this bit is set the Layer 4 Source Port number field is enabled for inverse matching. When this bit is reset the Layer 4 Source Port number field is enabled for perfect matching. This bit is valid.." "Layer 4 Source Port Inverse Match is disabled,Layer 4 Source Port Inverse Match is enabled" newline bitfld.long 0x0 18. "L4SPM0,Layer 4 Source Port Match Enable When this bit is set the Layer 4 Source Port number field is enabled for matching. When this bit is reset the MAC ignores the Layer 4 Source Port number field for matching. 0x0: Layer 4 Source Port Match is.." "Layer 4 Source Port Match is disabled,Layer 4 Source Port Match is enabled" newline rbitfld.long 0x0 17. "RESERVED_17,Reserved." "0,1" newline bitfld.long 0x0 16. "L4PEN0,Layer 4 Protocol Enable When this bit is set the Source and Destination Port number fields of UDP packets are used for matching. When this bit is reset the Source and Destination Port number fields of TCP packets are used for matching. The Layer.." "Layer 4 Protocol is disabled,Layer 4 Protocol is enabled" newline hexmask.long.byte 0x0 11.--15. 1. "L3HDBM0,Layer 3 IP DA Higher Bits Match IPv4 Packets: This field contains the number of higher bits of IP Destination Address that are matched in the IPv4 packets. The following list describes the values of this field: - 0: No bits are masked. - 1:.." newline hexmask.long.byte 0x0 6.--10. 1. "L3HSBM0,Layer 3 IP SA Higher Bits Match IPv4 Packets: This field contains the number of lower bits of IP Source Address that are masked for matching in the IPv4 packets. The following list describes the values of this field: - 0: No bits are masked. - 1:.." newline bitfld.long 0x0 5. "L3DAIM0,Layer 3 IP DA Inverse Match Enable When this bit is set the Layer 3 IP Destination Address field is enabled for inverse matching. When this bit is reset the Layer 3 IP Destination Address field is enabled for perfect matching. This bit is valid.." "Layer 3 IP DA Inverse Match is disabled,Layer 3 IP DA Inverse Match is enabled" newline bitfld.long 0x0 4. "L3DAM0,Layer 3 IP DA Match Enable When this bit is set the Layer 3 IP Destination Address field is enabled for matching. When this bit is reset the MAC ignores the Layer 3 IP Destination Address field for matching. Note: When the L3PEN0 bit is set you.." "Layer 3 IP DA Match is disabled,Layer 3 IP DA Match is enabled" newline bitfld.long 0x0 3. "L3SAIM0,Layer 3 IP SA Inverse Match Enable When this bit is set the Layer 3 IP Source Address field is enabled for inverse matching. When this bit reset the Layer 3 IP Source Address field is enabled for perfect matching. This bit is valid and.." "Layer 3 IP SA Inverse Match is disabled,Layer 3 IP SA Inverse Match is enabled" newline bitfld.long 0x0 2. "L3SAM0,Layer 3 IP SA Match Enable When this bit is set the Layer 3 IP Source Address field is enabled for matching. When this bit is reset the MAC ignores the Layer 3 IP Source Address field for matching. Note: When the L3PEN0 bit is set you should.." "Layer 3 IP SA Match is disabled,Layer 3 IP SA Match is enabled" newline rbitfld.long 0x0 1. "RESERVED_1,Reserved." "0,1" newline bitfld.long 0x0 0. "L3PEN0,Layer 3 Protocol Enable When this bit is set the Layer 3 IP Source or Destination Address matching is enabled for IPv6 packets. When this bit is reset the Layer 3 IP Source or Destination Address matching is enabled for IPv4 packets. The Layer 3.." "Layer 3 Protocol is disabled,Layer 3 Protocol is enabled" repeat.end repeat 4. (list 0x0 0x1 0x2 0x3 )(list 0x0 0x30 0x60 0x90 ) group.long ($2+0x904)++0x3 line.long 0x0 "MAC_LAYER4_ADDRESS$1,The MAC_Layer4_Address(#i). MAC_L3_L4_Control(#i). MAC_Layer3_Addr0_Reg(#i). MAC_Layer3_Addr1_Reg(#i). MAC_Layer3_Addr2_Reg(#i) and MAC_Layer3_Addr3_Reg(#i) registers are reserved (RO with default value) if Enable Layer 3 and Layer 4.." hexmask.long.word 0x0 16.--31. 1. "L4DP0,Layer 4 Destination Port Number Field When the L4PEN0 bit is reset and the L4DPM0 bit is set in the MAC_L3_L4_Control0 register this field contains the value to be matched with the TCP Destination Port Number field in the IPv4 or IPv6 packets." newline hexmask.long.word 0x0 0.--15. 1. "L4SP0,Layer 4 Source Port Number Field When the L4PEN0 bit is reset and the L4SPM0 bit is set in the MAC_L3_L4_Control0 register this field contains the value to be matched with the TCP Source Port Number field in the IPv4 or IPv6 packets. When the.." repeat.end repeat 4. (list 0x0 0x1 0x2 0x3 )(list 0x0 0x30 0x60 0x90 ) group.long ($2+0x910)++0x3 line.long 0x0 "MAC_LAYER3_ADDR0_REG$1,For IPv4 packets. the Layer 3 Address 0 Register 0 register contains the 32-bit IP Source Address field. For IPv6 packets. it contains Bits[31:0] of the 128-bit IP Source Address or Destination Address field." hexmask.long 0x0 0.--31. 1. "L3A00,Layer 3 Address 0 Field When the L3PEN0 and L3SAM0 bits are set in the MAC_L3_L4_Control0 register this field contains the value to be matched with Bits[31:0] of the IP Source Address field in the IPv6 packets. When the L3PEN0 and L3DAM0 bits are.." repeat.end repeat 4. (list 0x0 0x1 0x2 0x3 )(list 0x0 0x30 0x60 0x90 ) group.long ($2+0x914)++0x3 line.long 0x0 "MAC_LAYER3_ADDR1_REG$1,For IPv4 packets. the Layer 3 Address 1 Register 0 register contains the 32-bit IP Destination Address field. For IPv6 packets. it contains Bits[63:32] of the 128-bit IP Source Address or Destination Address field." hexmask.long 0x0 0.--31. 1. "L3A10,Layer 3 Address 1 Field When the L3PEN0 and L3SAM0 bits are set in the MAC_L3_L4_Control0 register this field contains the value to be matched with Bits[63:32] of the IP Source Address field in the IPv6 packets. When the L3PEN0 and L3DAM0 bits are.." repeat.end repeat 4. (list 0x0 0x1 0x2 0x3 )(list 0x0 0x30 0x60 0x90 ) group.long ($2+0x918)++0x3 line.long 0x0 "MAC_LAYER3_ADDR2_REG$1,The Layer 3 Address 2 Register 0 register is reserved for IPv4 packets. For IPv6 packets. it contains Bits[95:64] of 128-bit IP Source Address or Destination Address field." hexmask.long 0x0 0.--31. 1. "L3A20,Layer 3 Address 2 Field When the L3PEN0 and L3SAM0 bits are set in the MAC_L3_L4_Control0 register this field contains the value to be matched with Bits[95:64] of the IP Source Address field in the IPv6 packets. When the L3PEN0 and L3DAM0 bits are.." repeat.end repeat 4. (list 0x0 0x1 0x2 0x3 )(list 0x0 0x30 0x60 0x90 ) group.long ($2+0x91C)++0x3 line.long 0x0 "MAC_LAYER3_ADDR3_REG$1,The Layer 3 Address 3 Register 0 register is reserved for IPv4 packets. For IPv6 packets. it contains Bits[127:96] of 128-bit IP Source Address or Destination Address field." hexmask.long 0x0 0.--31. 1. "L3A30,Layer 3 Address 3 Field When the L3PEN0 and L3SAM0 bits are set in the MAC_L3_L4_Control0 register this field contains the value to be matched with Bits[127:96] of the IP Source Address field in the IPv6 packets. When the L3PEN0 and L3DAM0 bits.." repeat.end group.long 0xB00++0x7 line.long 0x0 "MAC_TIMESTAMP_CONTROL,This register controls the operation of the System Time generator and processing of PTP packets for timestamping in the Receiver." rbitfld.long 0x0 29.--31. "RESERVED_31_29,Reserved." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 28. "AV8021ASMEN,AV 802.1AS Mode Enable When this bit is set the MAC processes only untagged PTP over Ethernet packets for providing PTP status and capturing timestamp snapshots that is IEEE 802.1AS mode of operation. When PTP offload feature is enabled.." "AV 802,AV 802" newline rbitfld.long 0x0 25.--27. "RESERVED_27_25,Reserved." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 24. "TXTSSTSM,Transmit Timestamp Status Mode When this bit is set the MAC overwrites the earlier transmit timestamp status even if it is not read by the software. The MAC indicates this by setting the TXTSSMIS bit of the MAC_Tx_Timestamp_Status_Nanoseconds.." "Transmit Timestamp Status Mode is disabled,Transmit Timestamp Status Mode is enabled" newline rbitfld.long 0x0 21.--23. "RESERVED_23_21,Reserved." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 20. "ESTI,External System Time Input When this bit is set the MAC uses the external 64-bit reference System Time input for the following: - To take the timestamp provided as status - To insert the timestamp in transmit PTP packets when One-step Timestamp or.." "External System Time Input is disabled,External System Time Input is enabled" newline bitfld.long 0x0 19. "CSC,Enable checksum correction during OST for PTP over UDP/IPv4 packets When this bit is set the last two bytes of PTP message sent over UDP/IPv4 is updated to keep the UDP checksum correct for changes made to origin timestamp and/or correction field.." "checksum correction during OST for PTP over..,checksum correction during OST for PTP over.." newline bitfld.long 0x0 18. "TSENMACADDR,Enable MAC Address for PTP Packet Filtering When this bit is set the DA MAC address (that matches any MAC Address register) is used to filter the PTP packets when PTP is directly sent over Ethernet. When this bit is set received PTP packets.." "MAC Address for PTP Packet Filtering is disabled,MAC Address for PTP Packet Filtering is enabled" newline bitfld.long 0x0 16.--17. "SNAPTYPSEL,Select PTP packets for Taking Snapshots These bits along with Bits 15 and 14 decide the set of PTP packet types for which snapshot needs to be taken. The encoding is given in Timestamp Snapshot Dependency on Register Bits Table." "0,1,2,3" newline bitfld.long 0x0 15. "TSMSTRENA,Enable Snapshot for Messages Relevant to Master When this bit is set the snapshot is taken only for the messages that are relevant to the master node. Otherwise the snapshot is taken for the messages relevant to the slave node. 0x0: Snapshot.." "Snapshot for Messages Relevant to Master is..,Snapshot for Messages Relevant to Master is.." newline bitfld.long 0x0 14. "TSEVNTENA,Enable Timestamp Snapshot for Event Messages When this bit is set the timestamp snapshot is taken only for event messages (SYNC Delay_Req Pdelay_Req or Pdelay_Resp). When this bit is reset the snapshot is taken for all messages except.." "Timestamp Snapshot for Event Messages is disabled,Timestamp Snapshot for Event Messages is enabled" newline bitfld.long 0x0 13. "TSIPV4ENA,Enable Processing of PTP Packets Sent over IPv4-UDP When this bit is set the MAC receiver processes the PTP packets encapsulated in IPv4-UDP packets. When this bit is reset the MAC ignores the PTP transported over IPv4-UDP packets. This bit.." "Processing of PTP Packets Sent over IPv4-UDP is..,Processing of PTP Packets Sent over IPv4-UDP is.." newline bitfld.long 0x0 12. "TSIPV6ENA,Enable Processing of PTP Packets Sent over IPv6-UDP When this bit is set the MAC receiver processes the PTP packets encapsulated in IPv6-UDP packets. When this bit is clear the MAC ignores the PTP transported over IPv6-UDP packets. 0x0:.." "Processing of PTP Packets Sent over IPv6-UDP is..,Processing of PTP Packets Sent over IPv6-UDP is.." newline bitfld.long 0x0 11. "TSIPENA,Enable Processing of PTP over Ethernet Packets When this bit is set the MAC receiver processes the PTP packets encapsulated directly in the Ethernet packets. When this bit is reset the MAC ignores the PTP over Ethernet packets. 0x0: Processing.." "Processing of PTP over Ethernet Packets is..,Processing of PTP over Ethernet Packets is enabled" newline bitfld.long 0x0 10. "TSVER2ENA,Enable PTP Packet Processing for Version 2 Format When this bit is set the IEEE 1588 version 2 format is used to process the PTP packets. When this bit is reset the IEEE 1588 version 1 format is used to process the PTP packets. The IEEE 1588.." "PTP Packet Processing for Version 2 Format is..,PTP Packet Processing for Version 2 Format is.." newline bitfld.long 0x0 9. "TSCTRLSSR,Timestamp Digital or Binary Rollover Control When this bit is set the Timestamp Low register rolls over after 0x3B9A_C9FF value (that is 1 nanosecond accuracy) and increments the timestamp (High) seconds. When this bit is reset the rollover.." "Timestamp Digital or Binary Rollover Control is..,Timestamp Digital or Binary Rollover Control is.." newline bitfld.long 0x0 8. "TSENALL,Enable Timestamp for All Packets When this bit is set the timestamp snapshot is enabled for all packets received by the MAC. 0x0: Timestamp for All Packets disabled 0x1: Timestamp for All Packets enabled" "Timestamp for All Packets disabled,Timestamp for All Packets enabled" newline rbitfld.long 0x0 7. "RESERVED_7,Reserved." "0,1" newline bitfld.long 0x0 6. "PTGE,Presentation Time Generation Enable When this bit is set the Presentation Time generation will be enabled. 0x0: Presentation Time Generation is disabled 0x1: Presentation Time Generation is enabled" "Presentation Time Generation is disabled,Presentation Time Generation is enabled" newline bitfld.long 0x0 5. "TSADDREG,Update Addend Register When this bit is set the content of the Timestamp Addend register is updated in the PTP block for fine correction. This bit is cleared when the update is complete. This bit should be zero before it is set. Access.." "Addend Register is not updated,Addend Register is updated" newline rbitfld.long 0x0 4. "RESERVED_TSTRIG,Reserved." "0,1" newline bitfld.long 0x0 3. "TSUPDT,Update Timestamp When this bit is set the system time is updated (added or subtracted) with the value specified in MAC_System_Time_Seconds_Update and MAC_System_Time_Nanoseconds_Update registers. This bit should be zero before updating it. This.." "Timestamp is not updated,Timestamp is updated" newline bitfld.long 0x0 2. "TSINIT,Initialize Timestamp When this bit is set the system time is initialized (overwritten) with the value specified in the MAC_System_Time_Seconds_Update and MAC_System_Time_Nanoseconds_Update registers. This bit should be zero before it is updated." "Timestamp is not initialized,Timestamp is initialized" newline bitfld.long 0x0 1. "TSCFUPDT,Fine or Coarse Timestamp Update When this bit is set the Fine method is used to update system timestamp. When this bit is reset Coarse method is used to update the system timestamp. 0x0: Coarse method is used to update system timestamp 0x1:.." "Coarse method is used to update system timestamp,Fine method is used to update system timestamp" line.long 0x4 "MAC_SUB_SECOND_INCREMENT,This register specifies the value to be added to the internal system time register every cycle of clk_ptp_ref_i clock." hexmask.long.byte 0x4 24.--31. 1. "RESERVED_31_24,Reserved." newline hexmask.long.byte 0x4 16.--23. 1. "SSINC,Sub-second Increment Value The value programmed in this field is accumulated every clock cycle (of clk_ptp_i) with the contents of the sub-second register. For example when the PTP clock is 50 MHz (period is 20 ns) you should program 20 (0x14).." newline hexmask.long.byte 0x4 8.--15. 1. "SNSINC,Sub-nanosecond Increment Value This field contains the sub-nanosecond increment value represented in nanoseconds multiplied by 2^8. This value is accumulated with the sub-nanoseconds field of the subsecond register. For example when TSCTRLSSR.." newline hexmask.long.byte 0x4 0.--7. 1. "RESERVED_7_0,Reserved." rgroup.long 0xB08++0x7 line.long 0x0 "MAC_SYSTEM_TIME_SECONDS,The System Time Seconds register. along with System Time Nanoseconds register. indicates the current value of the system time maintained by the MAC. Though it is updated on a continuous basis. there is some delay from the actual.." hexmask.long 0x0 0.--31. 1. "TSS,Timestamp Second The value in this field indicates the current value in seconds of the System Time maintained by the MAC." line.long 0x4 "MAC_SYSTEM_TIME_NANOSECONDS,The System Time Nanoseconds register. along with System Time Seconds register. indicates the current value of the system time maintained by the MAC." bitfld.long 0x4 31. "RESERVED_31,Reserved." "0,1" newline hexmask.long 0x4 0.--30. 1. "TSSS,Timestamp Sub Seconds The value in this field has the sub-second representation of time with an accuracy of 0.46 ns. When Bit 9 is set in MAC_Timestamp_Control each bit represents 1 ns. The maximum value is 0x3B9A_C9FF after which it rolls-over to.." group.long 0xB10++0xF line.long 0x0 "MAC_SYSTEM_TIME_SECONDS_UPDATE,The System Time Seconds Update register. along with the System Time Nanoseconds Update register. initializes or updates the system time maintained by the MAC. You must write both registers before setting the TSINIT or.." hexmask.long 0x0 0.--31. 1. "TSS,Timestamp Seconds The value in this field is the seconds part of the update. When ADDSUB is reset this field must be programmed with the seconds part of the update value. When ADDSUB is set this field must be programmed with the complement of the.." line.long 0x4 "MAC_SYSTEM_TIME_NANOSECONDS_UPDATE,MAC System Time Nanoseconds Update register." bitfld.long 0x4 31. "ADDSUB,Add or Subtract Time When this bit is set the time value is subtracted with the contents of the update register. When this bit is reset the time value is added with the contents of the update register. 0x0: Add time 0x1: Subtract time" "Add time,Subtract time" newline hexmask.long 0x4 0.--30. 1. "TSSS,Timestamp Sub Seconds The value in this field is the sub-seconds part of the update. When ADDSUB is reset this field must be programmed with the sub-seconds part of the update value with an accuracy based on the TSCTRLSSR bit of the.." line.long 0x8 "MAC_TIMESTAMP_ADDEND,Timestamp Addend register. This register value is used only when the system time is configured for Fine Update mode (TSCFUPDT bit in the MAC_Timestamp_Control register). The content of this register is added to a 32-bit accumulator.." hexmask.long 0x8 0.--31. 1. "TSAR,Timestamp Addend Register This field indicates the 32-bit time value to be added to the Accumulator register to achieve time synchronization." line.long 0xC "MAC_SYSTEM_TIME_HIGHER_WORD_SECONDS,System Time - Higher Word Seconds register." hexmask.long.word 0xC 16.--31. 1. "RESERVED_31_16,Reserved." newline hexmask.long.word 0xC 0.--15. 1. "TSHWR,Timestamp Higher Word Register This field contains the most-significant 16-bits of timestamp seconds value. This register is optional. You can add this register by selecting the Add IEEE 1588 Higher Word Register option. This register is directly.." rgroup.long 0xB20++0x3 line.long 0x0 "MAC_TIMESTAMP_STATUS,Timestamp Status register. All bits except Bits[27:25] gets cleared when the application reads this register." bitfld.long 0x0 30.--31. "RESERVED_31_30,Reserved." "0,1,2,3" newline hexmask.long.byte 0x0 25.--29. 1. "ATSNS,Number of Auxiliary Timestamp Snapshots This field indicates the number of Snapshots available in the FIFO. A value equal to the selected depth of FIFO (4 8 or 16) indicates that the Auxiliary Snapshot FIFO is full. These bits are cleared (to.." newline bitfld.long 0x0 24. "ATSSTM,Auxiliary Timestamp Snapshot Trigger Missed This bit is set when the Auxiliary timestamp snapshot FIFO is full and external trigger was set. This indicates that the latest snapshot is not stored in the FIFO. This bit is valid only if the Add IEEE.." "Auxiliary Timestamp Snapshot Trigger Missed..,Auxiliary Timestamp Snapshot Trigger Missed.." newline hexmask.long.byte 0x0 20.--23. 1. "RESERVED_23_20,Reserved." newline hexmask.long.byte 0x0 16.--19. 1. "ATSSTN,Auxiliary Timestamp Snapshot Trigger Identifier These bits identify the Auxiliary trigger inputs for which the timestamp available in the Auxiliary Snapshot Register is applicable. When more than one bit is set at the same time it means that.." newline bitfld.long 0x0 15. "TXTSSIS,Tx Timestamp Status Interrupt Status In non-EQOS_CORE configurations when drop transmit status is enabled in MTL this bit is set when the captured transmit timestamp is updated in the MAC_Tx_Timestamp_Status_Nanoseconds and.." "Tx Timestamp Status Interrupt status not detected,Tx Timestamp Status Interrupt status detected" newline hexmask.long.byte 0x0 10.--14. 1. "RESERVED_14_10,Reserved." newline bitfld.long 0x0 9. "TSTRGTERR3,Timestamp Target Time Error This bit is set when the latest target time programmed in the MAC_PPS3_Target_Time_Seconds and MAC_PPS3_Target_Time_Nanoseconds registers elapses. This bit is cleared when the application reads this bit. Access.." "Timestamp Target Time Error status not detected,Timestamp Target Time Error status detected" newline bitfld.long 0x0 8. "TSTARGT3,Timestamp Target Time Reached for Target Time PPS3 When this bit is set it indicates that the value of system time is greater than or equal to the value specified in the MAC_PPS3_Target_Time_Seconds and MAC_PPS3_Target_Time_Nanoseconds.." "Timestamp Target Time Reached for Target Time..,Timestamp Target Time Reached for Target Time.." newline bitfld.long 0x0 7. "TSTRGTERR2,Timestamp Target Time Error This bit is set when the latest target time programmed in the MAC_PPS2_Target_Time_Seconds and MAC_PPS2_Target_Time_Nanoseconds registers elapses. This bit is cleared when the application reads this bit. Access.." "Timestamp Target Time Error status not detected,Timestamp Target Time Error status detected" newline bitfld.long 0x0 6. "TSTARGT2,Timestamp Target Time Reached for Target Time PPS2 When set this bit indicates that the value of system time is greater than or equal to the value specified in the MAC_PPS2_Target_Time_Seconds and MAC_PPS2_Target_Time_Nanoseconds registers." "Timestamp Target Time Reached for Target Time..,Timestamp Target Time Reached for Target Time.." newline bitfld.long 0x0 5. "TSTRGTERR1,Timestamp Target Time Error This bit is set when the latest target time programmed in the MAC_PPS1_Target_Time_Seconds and MAC_PPS1_Target_Time_Nanoseconds registers elapses. This bit is cleared when the application reads this bit. Access.." "Timestamp Target Time Error status not detected,Timestamp Target Time Error status detected" newline bitfld.long 0x0 4. "TSTARGT1,Timestamp Target Time Reached for Target Time PPS1 When set this bit indicates that the value of system time is greater than or equal to the value specified in the MAC_PPS1_Target_Time_Seconds and MAC_PPS1_Target_Time_Nanoseconds registers." "Timestamp Target Time Reached for Target Time..,Timestamp Target Time Reached for Target Time.." newline bitfld.long 0x0 3. "TSTRGTERR0,Timestamp Target Time Error This bit is set when the latest target time programmed in the MAC_PPS0_Target_Time_Seconds and MAC_PPS0_Target_Time_Nanoseconds registers elapses. This bit is cleared when the application reads this bit. Access.." "Timestamp Target Time Error status not detected,Timestamp Target Time Error status detected" newline bitfld.long 0x0 2. "AUXTSTRIG,Auxiliary Timestamp Trigger Snapshot This bit is set high when the auxiliary snapshot is written to the FIFO. This bit is valid only if the Add IEEE 1588 Auxiliary Snapshot option is selected. Access restriction applies. Clears on read (or this.." "Auxiliary Timestamp Trigger Snapshot status not..,Auxiliary Timestamp Trigger Snapshot status.." newline bitfld.long 0x0 1. "TSTARGT0,Timestamp Target Time Reached When set this bit indicates that the value of system time is greater than or equal to the value specified in the MAC_PPS0_Target_Time_Seconds and MAC_PPS0_Target_Time_Nanoseconds registers. Access restriction.." "Timestamp Target Time Reached status not detected,Timestamp Target Time Reached status detected" newline bitfld.long 0x0 0. "TSSOVF,Timestamp Seconds Overflow When this bit is set it indicates that the seconds value of the timestamp (when supporting version 2 format) has overflowed beyond 32'hFFFF_FFFF. Access restriction applies. Clears on read (or this bit is written to 1.." "Timestamp Seconds Overflow status not detected,Timestamp Seconds Overflow status detected" rgroup.long 0xB30++0x7 line.long 0x0 "MAC_TX_TIMESTAMP_STATUS_NANOSECONDS,This register contains the nanosecond part of timestamp captured for Transmit packets when Tx status is disabled. The MAC_Tx_Timestamp_Status_Nanoseconds register. along with MAC_Tx_Timestamp_Status_Seconds. gives the.." bitfld.long 0x0 31. "TXTSSMIS,Transmit Timestamp Status Missed When this bit is set it indicates one of the following: - The timestamp of the current packet is ignored if TXTSSTSM bit of the MAC_Timestamp_Control register is reset - The timestamp of the previous packet is.." "Transmit Timestamp Status Missed status not..,Transmit Timestamp Status Missed status detected" newline hexmask.long 0x0 0.--30. 1. "TXTSSLO,Transmit Timestamp Status Low This field contains the 31 bits of the Nanoseconds field of the Transmit packet's captured timestamp." line.long 0x4 "MAC_TX_TIMESTAMP_STATUS_SECONDS,The register contains the higher 32 bits of the timestamp (in seconds) captured when a PTP packet is transmitted." hexmask.long 0x4 0.--31. 1. "TXTSSHI,Transmit Timestamp Status High This field contains the lower 32 bits of the Seconds field of Transmit packet's captured timestamp." group.long 0xB40++0x3 line.long 0x0 "MAC_AUXILIARY_CONTROL,The Auxiliary Timestamp Control register controls the Auxiliary Timestamp snapshot." hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED_31_8,Reserved." newline bitfld.long 0x0 7. "ATSEN3,Auxiliary Snapshot 3 Enable This bit controls the capturing of Auxiliary Snapshot Trigger 3. When this bit is set the auxiliary snapshot of the event on ptp_aux_trig_i[3] input is enabled. When this bit is reset the events on this input are.." "Auxiliary Snapshot i is disabled,Auxiliary Snapshot i is enabled" newline bitfld.long 0x0 6. "ATSEN2,Auxiliary Snapshot 2 Enable This bit controls the capturing of Auxiliary Snapshot Trigger 2. When this bit is set the auxiliary snapshot of the event on ptp_aux_trig_i[2] input is enabled. When this bit is reset the events on this input are.." "Auxiliary Snapshot i is disabled,Auxiliary Snapshot i is enabled" newline bitfld.long 0x0 5. "ATSEN1,Auxiliary Snapshot 1 Enable This bit controls the capturing of Auxiliary Snapshot Trigger 1. When this bit is set the auxiliary snapshot of the event on ptp_aux_trig_i[1] input is enabled. When this bit is reset the events on this input are.." "Auxiliary Snapshot i is disabled,Auxiliary Snapshot i is enabled" newline bitfld.long 0x0 4. "ATSEN0,Auxiliary Snapshot 0 Enable This bit controls the capturing of Auxiliary Snapshot Trigger 0. When this bit is set the auxiliary snapshot of the event on ptp_aux_trig_i[0] input is enabled. When this bit is reset the events on this input are.." "Auxiliary Snapshot i is disabled,Auxiliary Snapshot i is enabled" newline rbitfld.long 0x0 1.--3. "RESERVED_3_1,Reserved." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 0. "ATSFC,Auxiliary Snapshot FIFO Clear When set this bit resets the pointers of the Auxiliary Snapshot FIFO. This bit is cleared when the pointers are reset and the FIFO is empty. When this bit is high the auxiliary snapshots are stored in the FIFO." "Auxiliary Snapshot FIFO Clear is disabled,Auxiliary Snapshot FIFO Clear is enabled" rgroup.long 0xB48++0x7 line.long 0x0 "MAC_AUXILIARY_TIMESTAMP_NANOSECONDS,The Auxiliary Timestamp Nanoseconds register. along with MAC_Auxiliary_Timestamp_Seconds. gives the 64-bit timestamp stored as auxiliary snapshot. These two registers form the read port of a 64-bit wide FIFO with a.." bitfld.long 0x0 31. "RESERVED_31,Reserved." "0,1" newline hexmask.long 0x0 0.--30. 1. "AUXTSLO,Auxiliary Timestamp Contains the lower 31 bits (nanoseconds field) of the auxiliary timestamp." line.long 0x4 "MAC_AUXILIARY_TIMESTAMP_SECONDS,The Auxiliary Timestamp - Seconds register contains the lower 32 bits of the Seconds field of the auxiliary timestamp register." hexmask.long 0x4 0.--31. 1. "AUXTSHI,Auxiliary Timestamp Contains the lower 32 bits of the Seconds field of the auxiliary timestamp." group.long 0xB50++0x17 line.long 0x0 "MAC_TIMESTAMP_INGRESS_ASYM_CORR,The MAC Timestamp Ingress Asymmetry Correction register contains the Ingress Asymmetry Correction value to be used while updating correction field in PDelay_Resp PTP messages." hexmask.long 0x0 0.--31. 1. "OSTIAC,One-Step Timestamp Ingress Asymmetry Correction This field contains the ingress path asymmetry value to be added to correctionField of Pdelay_Resp PTP packet. The programmed value should be in units of nanoseconds and multiplied by 2^16. For.." line.long 0x4 "MAC_TIMESTAMP_EGRESS_ASYM_CORR,The MAC Timestamp Egress Asymmetry Correction register contains the Egress Asymmetry Correction value to be used while updating the correction field in PDelay_Req PTP messages." hexmask.long 0x4 0.--31. 1. "OSTEAC,One-Step Timestamp Egress Asymmetry Correction This field contains the egress path asymmetry value to be subtracted from correctionField of Pdelay_Resp PTP packet. The programmed value must be the negated value in units of nanoseconds multiplied.." line.long 0x8 "MAC_TIMESTAMP_INGRESS_CORR_NANOSECOND,This register contains the correction value in nanoseconds to be used with the captured timestamp value in the ingress path." hexmask.long 0x8 0.--31. 1. "TSIC,Timestamp Ingress Correction This field contains the ingress path correction value as defined by the Ingress Correction expression." line.long 0xC "MAC_TIMESTAMP_EGRESS_CORR_NANOSECOND,This register contains the correction value in nanoseconds to be used with the captured timestamp value in the egress path." hexmask.long 0xC 0.--31. 1. "TSEC,Timestamp Egress Correction This field contains the nanoseconds part of the egress path correction value as defined by the Egress Correction expression." line.long 0x10 "MAC_TIMESTAMP_INGRESS_CORR_SUBNANOSEC,This register contains the sub-nanosecond part of the correction value to be used with the captured timestamp value. for ingress direction." hexmask.long.word 0x10 16.--31. 1. "RESERVED_31_16,Reserved." newline hexmask.long.byte 0x10 8.--15. 1. "TSICSNS,Timestamp Ingress Correction sub-nanoseconds This field contains the sub-nanoseconds part of the ingress path correction value as defined by the 'Ingress Correction' expression." newline hexmask.long.byte 0x10 0.--7. 1. "RESERVED_7_0,Reserved." line.long 0x14 "MAC_TIMESTAMP_EGRESS_CORR_SUBNANOSEC,This register contains the sub-nanosecond part of the correction value to be used with the captured timestamp value. for egress direction." hexmask.long.word 0x14 16.--31. 1. "RESERVED_31_16,Reserved." newline hexmask.long.byte 0x14 8.--15. 1. "TSECSNS,Timestamp Egress Correction sub-nanoseconds This field contains the sub-nanoseconds part of the egress path correction value as defined by the 'Egress Correction' expression." newline hexmask.long.byte 0x14 0.--7. 1. "RESERVED_7_0,Reserved." rgroup.long 0xB68++0x7 line.long 0x0 "MAC_TIMESTAMP_INGRESS_LATENCY,This register holds the Ingress MAC latency." hexmask.long.byte 0x0 28.--31. 1. "RESERVED_31_28,Reserved." newline hexmask.long.word 0x0 16.--27. 1. "ITLNS,Ingress Timestamp Latency in sub-nanoseconds This register holds the average latency in sub-nanoseconds between the input ports (phy_rxd_i) of MAC and the actual point (GMII/MII) where the ingress timestamp is taken. Ingress correction value is.." newline hexmask.long.byte 0x0 8.--15. 1. "ITLSNS,Ingress Timestamp Latency in nanoseconds This register holds the average latency in nanoseconds between the input ports (phy_rxd_i) of MAC and the actual point (GMII/MII) where the ingress timestamp is taken. Ingress correction value is computed.." newline hexmask.long.byte 0x0 0.--7. 1. "RESERVED_7_0,Reserved." line.long 0x4 "MAC_TIMESTAMP_EGRESS_LATENCY,This register holds the Egress MAC latency." hexmask.long.byte 0x4 28.--31. 1. "RESERVED_31_28,Reserved." newline hexmask.long.word 0x4 16.--27. 1. "ETLNS,Egress Timestamp Latency in nanoseconds This register holds the average latency in nanoseconds between the actual point (GMII/MII) where the egress timestamp is taken and the output ports (phy_txd_o) of the MAC. Ingress correction value is.." newline hexmask.long.byte 0x4 8.--15. 1. "ETLSNS,Egress Timestamp Latency in sub-nanoseconds This register holds the average latency in sub-nanoseconds between the actual point (GMII/MII) where the egress timestamp is taken and the output ports (phy_txd_o) of the MAC. Ingress correction value.." newline hexmask.long.byte 0x4 0.--7. 1. "RESERVED_7_0,Reserved." group.long 0xB70++0x3 line.long 0x0 "MAC_PPS_CONTROL,PPS Control register. Bits[30:24] of this register are valid only when four Flexible PPS outputs are selected. Bits[22:16] are valid only when three or more Flexible PPS outputs are selected. Bits[14:8] are valid only when two or more.." bitfld.long 0x0 31. "MCGREN3,MCGR Mode Enable for PPS3 Output This field enables the 3rd PPS instance to operate in PPS or MCGR mode. When set it operates in MCGR mode and on reset it operates in PPS mode." "0,1" newline bitfld.long 0x0 29.--30. "TRGTMODSEL3,Target Time Register Mode for PPS3 Output This field indicates the Target Time registers (MAC_PPS3_Target_Time_Seconds and MAC_PPS3_Target_Time_Nanoseconds) mode for PPS3 output signal. 0x2: Target Time registers are programmed for generating.." "Target Time registers are programmed only for..,Reserved,Target Time registers are programmed for..,Target Time registers are programmed only for.." newline rbitfld.long 0x0 28. "RESERVED_28,Reserved." "0,1" newline hexmask.long.byte 0x0 24.--27. 1. "PPSCMD3,Flexible PPS3 Output Control This field controls the flexible PPS3 output (ptp_pps_o[3]) signal. This field is similar to the PPSCMD0[2:0] field. If MCGREN3 is set then PPSCMD3 indicated by these 4 bits [27:24] are taken as Presentation Time.." newline bitfld.long 0x0 23. "MCGREN2,MCGR Mode Enable for PPS2 Output This field enables the 2nd PPS instance to operate in PPS or MCGR mode. When set it operates in MCGR mode and on reset it operates in PPS mode. 0x0: 2nd PPS instance is disabled to operate in PPS or MCGR mode 0x1:.." "0,1" newline bitfld.long 0x0 21.--22. "TRGTMODSEL2,Target Time Register Mode for PPS2 Output This field indicates the Target Time registers (MAC_PPS2_Target_Time_Seconds and MAC_PPS2_Target_Time_Nanoseconds) mode for PPS2 output signal. 0x2: Target Time registers are programmed for generating.." "Target Time registers are programmed only for..,Reserved,Target Time registers are programmed for..,Target Time registers are programmed only for.." newline rbitfld.long 0x0 20. "RESERVED_20,Reserved." "0,1" newline hexmask.long.byte 0x0 16.--19. 1. "PPSCMD2,Flexible PPS2 Output Control This field controls the flexible PPS2 output (ptp_pps_o[2]) signal. This field is similar to the PPSCMD0 field. If MCGREN2 is set then PPSCMD2 indicated by these 4 bits [19:16] are taken as Presentation Time Control.." newline bitfld.long 0x0 15. "MCGREN1,MCGR Mode Enable for PPS1 Output This field enables the 1st PPS instance to operate in PPS or MCGR mode. When set it operates in MCGR mode and on reset it operates in PPS mode. 0x0: 1st PPS instance is disabled to operate in PPS or MCGR mode 0x1:.." "0,1" newline bitfld.long 0x0 13.--14. "TRGTMODSEL1,Target Time Register Mode for PPS1 Output This field indicates the Target Time registers (MAC_PPS1_Target_Time_Seconds and MAC_PPS1_Target_Time_Nanoseconds) mode for PPS1 output signal. 0x2: Target Time registers are programmed for generating.." "Target Time registers are programmed only for..,Reserved,Target Time registers are programmed for..,Target Time registers are programmed only for.." newline rbitfld.long 0x0 12. "RESERVED_12,Reserved." "0,1" newline hexmask.long.byte 0x0 8.--11. 1. "PPSCMD1,Flexible PPS1 Output Control This field controls the flexible PPS1 output (ptp_pps_o[1]) signal. This field is similar to the PPSCMD0 field. If MCGREN1 is set then PPSCMD1 indicated by these 4 bits [11:8] are taken as Presentation Time Control.." newline bitfld.long 0x0 7. "MCGREN0,MCGR Mode Enable for PPS0 Output This field enables the 0th PPS instance to operate in PPS or MCGR mode. When set it operates in MCGR mode and on reset it operates in PPS mode. 0x1: 0th PPS instance is enabled to operate in MCGR mode 0x0: 0th PPS.." "0,1" newline bitfld.long 0x0 5.--6. "TRGTMODSEL0,Target Time Register Mode for PPS0 Output This field indicates the Target Time registers (MAC_PPS0_Target_Time_Seconds and MAC_PPS0_Target_Time_Nanoseconds) mode for PPS0 output signal: 0x2: Target Time registers are programmed for generating.." "Target Time registers are programmed only for..,Reserved,Target Time registers are programmed for..,Target Time registers are programmed only for.." newline bitfld.long 0x0 4. "PPSEN0,Flexible PPS Output Mode Enable When this bit is set Bits[3:0] function as PPSCMD. When this bit is reset Bits[3:0] function as PPSCTRL (Fixed PPS mode). 0x0: Flexible PPS Output Mode is disabled 0x1: Flexible PPS Output Mode is enabled" "Flexible PPS Output Mode is disabled,Flexible PPS Output Mode is enabled" newline hexmask.long.byte 0x0 0.--3. 1. "PPSCTRL_PPSCMD,PPS Output Frequency Control This field controls the frequency of the PPS0 output (ptp_pps_o[0]) signal. The default value of PPSCTRL is 0000 and the PPS output is 1 pulse (of width clk_ptp_i) every second. For other values of PPSCTRL.." group.long 0xB80++0x53 line.long 0x0 "MAC_PPS0_TARGET_TIME_SECONDS,The PPS Target Time Seconds register. along with PPS Target Time Nanoseconds register. is used to schedule an interrupt event [Bit 1 of MAC_Timestamp_Status] when the system time exceeds the value programmed in these registers." hexmask.long 0x0 0.--31. 1. "TSTRH0,PPS Target Time Seconds Register This field stores the time in seconds. When the timestamp value matches or exceeds both Target Timestamp registers the MAC starts or stops the PPS signal output and generates an interrupt (if enabled) based on.." line.long 0x4 "MAC_PPS0_TARGET_TIME_NANOSECONDS,PPS0 Target Time Nanoseconds register." bitfld.long 0x4 31. "TRGTBUSY0,PPS Target Time Register Busy The MAC sets this bit when the PPSCMD0 field in the MAC_PPS_Control register is programmed to 010 or 011. Programming the PPSCMD0 field to 010 or 011 instructs the MAC to synchronize the Target Time Registers to.." "PPS Target Time Register Busy status is not..,PPS Target Time Register Busy is detected" newline hexmask.long 0x4 0.--30. 1. "TTSL0,Target Time Low for PPS Register This register stores the time in (signed) nanoseconds. When the value of the timestamp matches the value in both Target Timestamp registers the MAC starts or stops the PPS signal output and generates an interrupt.." line.long 0x8 "MAC_PPS0_INTERVAL,The PPS0 Interval register contains the number of units of sub-second increment value between the rising edges of PPS0 signal output (ptp_pps_o[0])." hexmask.long 0x8 0.--31. 1. "PPSINT0,PPS Output Signal Interval These bits store the interval between the rising edges of PPS0 signal output. The interval is stored in terms of number of units of sub-second increment value. You need to program one value less than the required.." line.long 0xC "MAC_PPS0_WIDTH,The PPS0 Width register contains the number of units of sub-second increment value between the rising and corresponding falling edges of PPS0 signal output (ptp_pps_o[0])." hexmask.long 0xC 0.--31. 1. "PPSWIDTH0,PPS Output Signal Width These bits store the width between the rising edge and corresponding falling edge of PPS0 signal output. The width is stored in terms of number of units of sub-second increment value. You need to program one value less.." line.long 0x10 "MAC_PPS1_TARGET_TIME_SECONDS,The PPS Target Time Seconds register. along with PPS Target Time Nanoseconds register. is used to schedule an interrupt event [Bit 1 of MAC_Timestamp_Status] when the system time exceeds the value programmed in these registers." hexmask.long 0x10 0.--31. 1. "TSTRH1,PPS Target Time Seconds Register This field stores the time in seconds. When the timestamp value matches or exceeds both Target Timestamp registers the MAC starts or stops the PPS signal output and generates an interrupt (if enabled) based on.." line.long 0x14 "MAC_PPS1_TARGET_TIME_NANOSECONDS,PPS0 Target Time Nanoseconds register." bitfld.long 0x14 31. "TRGTBUSY1,PPS Target Time Register Busy The MAC sets this bit when the PPSCMD0 field in the MAC_PPS_Control register is programmed to 010 or 011. Programming the PPSCMD0 field to 010 or 011 instructs the MAC to synchronize the Target Time Registers to.." "PPS Target Time Register Busy status is not..,PPS Target Time Register Busy is detected" newline hexmask.long 0x14 0.--30. 1. "TTSL1,Target Time Low for PPS Register This register stores the time in (signed) nanoseconds. When the value of the timestamp matches the value in both Target Timestamp registers the MAC starts or stops the PPS signal output and generates an interrupt.." line.long 0x18 "MAC_PPS1_INTERVAL,The PPS0 Interval register contains the number of units of sub-second increment value between the rising edges of PPS0 signal output (ptp_pps_o[0])." hexmask.long 0x18 0.--31. 1. "PPSINT1,PPS Output Signal Interval These bits store the interval between the rising edges of PPS0 signal output. The interval is stored in terms of number of units of sub-second increment value. You need to program one value less than the required.." line.long 0x1C "MAC_PPS1_WIDTH,The PPS0 Width register contains the number of units of sub-second increment value between the rising and corresponding falling edges of PPS0 signal output (ptp_pps_o[0])." hexmask.long 0x1C 0.--31. 1. "PPSWIDTH1,PPS Output Signal Width These bits store the width between the rising edge and corresponding falling edge of PPS0 signal output. The width is stored in terms of number of units of sub-second increment value. You need to program one value less.." line.long 0x20 "MAC_PPS2_TARGET_TIME_SECONDS,The PPS Target Time Seconds register. along with PPS Target Time Nanoseconds register. is used to schedule an interrupt event [Bit 1 of MAC_Timestamp_Status] when the system time exceeds the value programmed in these registers." hexmask.long 0x20 0.--31. 1. "TSTRH2,PPS Target Time Seconds Register This field stores the time in seconds. When the timestamp value matches or exceeds both Target Timestamp registers the MAC starts or stops the PPS signal output and generates an interrupt (if enabled) based on.." line.long 0x24 "MAC_PPS2_TARGET_TIME_NANOSECONDS,PPS0 Target Time Nanoseconds register." bitfld.long 0x24 31. "TRGTBUSY2,PPS Target Time Register Busy The MAC sets this bit when the PPSCMD0 field in the MAC_PPS_Control register is programmed to 010 or 011. Programming the PPSCMD0 field to 010 or 011 instructs the MAC to synchronize the Target Time Registers to.." "PPS Target Time Register Busy status is not..,PPS Target Time Register Busy is detected" newline hexmask.long 0x24 0.--30. 1. "TTSL2,Target Time Low for PPS Register This register stores the time in (signed) nanoseconds. When the value of the timestamp matches the value in both Target Timestamp registers the MAC starts or stops the PPS signal output and generates an interrupt.." line.long 0x28 "MAC_PPS2_INTERVAL,The PPS0 Interval register contains the number of units of sub-second increment value between the rising edges of PPS0 signal output (ptp_pps_o[0])." hexmask.long 0x28 0.--31. 1. "PPSINT2,PPS Output Signal Interval These bits store the interval between the rising edges of PPS0 signal output. The interval is stored in terms of number of units of sub-second increment value. You need to program one value less than the required.." line.long 0x2C "MAC_PPS2_WIDTH,The PPS0 Width register contains the number of units of sub-second increment value between the rising and corresponding falling edges of PPS0 signal output (ptp_pps_o[0])." hexmask.long 0x2C 0.--31. 1. "PPSWIDTH2,PPS Output Signal Width These bits store the width between the rising edge and corresponding falling edge of PPS0 signal output. The width is stored in terms of number of units of sub-second increment value. You need to program one value less.." line.long 0x30 "MAC_PPS3_TARGET_TIME_SECONDS,The PPS Target Time Seconds register. along with PPS Target Time Nanoseconds register. is used to schedule an interrupt event [Bit 1 of MAC_Timestamp_Status] when the system time exceeds the value programmed in these registers." hexmask.long 0x30 0.--31. 1. "TSTRH3,PPS Target Time Seconds Register This field stores the time in seconds. When the timestamp value matches or exceeds both Target Timestamp registers the MAC starts or stops the PPS signal output and generates an interrupt (if enabled) based on.." line.long 0x34 "MAC_PPS3_TARGET_TIME_NANOSECONDS,PPS0 Target Time Nanoseconds register." bitfld.long 0x34 31. "TRGTBUSY3,PPS Target Time Register Busy The MAC sets this bit when the PPSCMD0 field in the MAC_PPS_Control register is programmed to 010 or 011. Programming the PPSCMD0 field to 010 or 011 instructs the MAC to synchronize the Target Time Registers to.." "PPS Target Time Register Busy status is not..,PPS Target Time Register Busy is detected" newline hexmask.long 0x34 0.--30. 1. "TTSL3,Target Time Low for PPS Register This register stores the time in (signed) nanoseconds. When the value of the timestamp matches the value in both Target Timestamp registers the MAC starts or stops the PPS signal output and generates an interrupt.." line.long 0x38 "MAC_PPS3_INTERVAL,The PPS0 Interval register contains the number of units of sub-second increment value between the rising edges of PPS0 signal output (ptp_pps_o[0])." hexmask.long 0x38 0.--31. 1. "PPSINT3,PPS Output Signal Interval These bits store the interval between the rising edges of PPS0 signal output. The interval is stored in terms of number of units of sub-second increment value. You need to program one value less than the required.." line.long 0x3C "MAC_PPS3_WIDTH,The PPS0 Width register contains the number of units of sub-second increment value between the rising and corresponding falling edges of PPS0 signal output (ptp_pps_o[0])." hexmask.long 0x3C 0.--31. 1. "PPSWIDTH3,PPS Output Signal Width These bits store the width between the rising edge and corresponding falling edge of PPS0 signal output. The width is stored in terms of number of units of sub-second increment value. You need to program one value less.." line.long 0x40 "MAC_PTO_CONTROL,This register controls the PTP Offload Engine operation. This register is available only when the Enable PTP Timestamp Offload feature is selected." hexmask.long.word 0x40 16.--31. 1. "RESERVED_31_16,Reserved." newline hexmask.long.byte 0x40 8.--15. 1. "DN,Domain Number This field indicates the domain Number in which the PTP node is operating." newline bitfld.long 0x40 7. "PDRDIS,Disable Peer Delay Response response generation When this bit is set the Peer Delay Response (Pdelay_Resp) response is not be generated for received Peer Delay Request (Pdelay_Req) request packet as required by the programmed mode. Note: Setting.." "Peer Delay Response response generation is enabled,Peer Delay Response response generation is.." newline bitfld.long 0x40 6. "DRRDIS,Disable PTO Delay Request/Response response generation When this bit is set the Delay Request and Delay response is not generated for received SYNC and Delay request packet respectively as required by the programmed mode. 0x1: PTO Delay.." "PTO Delay Request/Response response generation..,PTO Delay Request/Response response generation.." newline bitfld.long 0x40 5. "APDREQTRIG,Automatic PTP Pdelay_Req message Trigger When this bit is set one PTP Pdelay_Req message is transmitted. This bit is automatically cleared after the PTP Pdelay_Req message is transmitted. The application should set the APDREQEN bit for this.." "Automatic PTP Pdelay_Req message Trigger is..,Automatic PTP Pdelay_Req message Trigger is.." newline bitfld.long 0x40 4. "ASYNCTRIG,Automatic PTP SYNC message Trigger When this bit is set one PTP SYNC message is transmitted. This bit is automatically cleared after the PTP SYNC message is transmitted. The application should set the ASYNCEN bit for this operation. Access.." "Automatic PTP SYNC message Trigger is disabled,Automatic PTP SYNC message Trigger is enabled" newline rbitfld.long 0x40 3. "RESERVED_3,Reserved." "0,1" newline bitfld.long 0x40 2. "APDREQEN,Automatic PTP Pdelay_Req message Enable When this bit is set PTP Pdelay_Req message is generated periodically based on interval programmed or trigger from application when the MAC is programmed to be in Peer-to-Peer Transparent mode. 0x0:.." "Automatic PTP Pdelay_Req message is disabled,Automatic PTP Pdelay_Req message is enabled" newline bitfld.long 0x40 1. "ASYNCEN,Automatic PTP SYNC message Enable When this bit is set PTP SYNC message is generated periodically based on interval programmed or trigger from application when the MAC is programmed to be in Clock Master mode. 0x0: Automatic PTP SYNC message is.." "Automatic PTP SYNC message is disabled,Automatic PTP SYNC message is enabled" newline bitfld.long 0x40 0. "PTOEN,PTP Offload Enable When this bit is set the PTP Offload feature is enabled. 0x0: PTP Offload feature is disabled 0x1: PTP Offload feature is enabled" "PTP Offload feature is disabled,PTP Offload feature is enabled" line.long 0x44 "MAC_SOURCE_PORT_IDENTITY0,This register contains Bits[31:0] of the 80-bit Source Port Identity of the PTP node. This register is available only when the Enable PTP Timestamp Offload feature is selected." hexmask.long 0x44 0.--31. 1. "SPI0,Source Port Identity 0 This field indicates bits [31:0] of sourcePortIdentity of PTP node." line.long 0x48 "MAC_SOURCE_PORT_IDENTITY1,This register contains Bits[63:32] of the 80-bit Source Port Identity of the PTP node. This register is available only when the Enable PTP Timestamp Offload feature is selected." hexmask.long 0x48 0.--31. 1. "SPI1,Source Port Identity 1 This field indicates bits [63:32] of sourcePortIdentity of PTP node." line.long 0x4C "MAC_SOURCE_PORT_IDENTITY2,This register contains Bits[79:64] of the 80-bit Source Port Identity of the PTP node. This register is available only when the Enable PTP Timestamp Offload feature is selected." hexmask.long.word 0x4C 16.--31. 1. "RESERVED_31_16,Reserved." newline hexmask.long.word 0x4C 0.--15. 1. "SPI2,Source Port Identity 2 This field indicates bits [79:64] of sourcePortIdentity of PTP node." line.long 0x50 "MAC_LOG_MESSAGE_INTERVAL,This register contains the periodic intervals for automatic PTP packet generation. This register is available only when the Enable PTP Timestamp Offload feature is selected." hexmask.long.byte 0x50 24.--31. 1. "LMPDRI,Log Min Pdelay_Req Interval This field indicates logMinPdelayReqInterval of PTP node. This is used to schedule the periodic Pdelay request packet transmission. Allowed values are -15 to 15.Negative value must be represented in 2's-complement form." newline hexmask.long.word 0x50 11.--23. 1. "RESERVED_23_11,Reserved." newline bitfld.long 0x50 8.--10. "DRSYNCR,Delay_Req to SYNC Ratio In Slave mode it is used for controlling frequency of Delay_Req messages transmitted. - 0: DelayReq generated for every received SYNC - 1: DelayReq generated every alternate reception of SYNC - 2: for every 4 SYNC.." "DelayReq generated for every received SYNC,DelayReq generated every alternate reception of..,for every 4 SYNC messages,for every 8 SYNC messages,for every 16 SYNC messages,for every 32 SYNC messages,Reserved,Reserved" newline hexmask.long.byte 0x50 0.--7. 1. "LSI,Log Sync Interval This field indicates the periodicity of the automatically generated SYNC message when the PTP node is Master. Allowed values are -15 to 15. Negative value must be represented in 2's-complement form. For example if the required.." tree.end tree "EQOS_MTL" group.long 0x0++0x3 line.long 0x0 "MTL_OPERATION_MODE,The Operation Mode register establishes the Transmit and Receive operating modes and commands." hexmask.long.word 0x0 16.--31. 1. "RESERVED_31_16,Reserved." newline bitfld.long 0x0 15. "FRPE,Flexible Rx parser Enable When this bit is set to 1 the Programmable Rx Parser functionality is enabled. When the Rx parser is disabled and if the Rx parser is in the middle of the parsing then it gets disabled only after completing the current.." "Flexible Rx parser is disabled,Flexible Rx parser is enabled" newline hexmask.long.byte 0x0 10.--14. 1. "RESERVED_14_10,Reserved." newline bitfld.long 0x0 9. "CNTCLR,Counters Reset When this bit is set all counters are reset. This bit is cleared automatically after 1 clock cycle. If this bit is set along with CNT_PRESET bit CNT_PRESET has precedence. Access restriction applies. Setting 1 sets. Self-cleared." "Counters are not reset,All counters are reset" newline bitfld.long 0x0 8. "CNTPRST,Counters Preset When this bit is set - MTL_TxQ[0-7]_Underflow register is initialized/preset to 12'h7F0. - Missed Packet and Overflow Packet counters in MTL_RxQ[0-7]_Missed_Packet_Overflow_Cnt register is initialized/preset to 12'h7F0. Access.." "Counters Preset is disabled,Counters Preset is enabled" newline rbitfld.long 0x0 7. "RESERVED_7,Reserved." "0,1" newline bitfld.long 0x0 5.--6. "SCHALG,Tx Scheduling Algorithm This field indicates the algorithm for Tx scheduling: 0x2: DWRR algorithm when DCB feature is selected.Otherwise Reserved 0x3: Strict priority algorithm 0x1: WFQ algorithm when DCB feature is selected.Otherwise Reserved.." "WRR algorithm,WFQ algorithm when DCB feature is selected,DWRR algorithm when DCB feature is selected,Strict priority algorithm" newline rbitfld.long 0x0 3.--4. "RESERVED_4_3,Reserved." "0,1,2,3" newline bitfld.long 0x0 2. "RAA,Receive Arbitration Algorithm This field is used to select the arbitration algorithm for the Rx side. - 0: Strict priority (SP) Queue 0 has the lowest priority and the last queue has the highest priority. - 1: Weighted Strict Priority (WSP) 0x0:.." "Strict priority,Weighted Strict Priority" newline bitfld.long 0x0 1. "DTXSTS,Drop Transmit Status When this bit is set the Tx packet status received from the MAC is dropped in the MTL. When this bit is reset the Tx packet status received from the MAC is forwarded to the application. 0x0: Drop Transmit Status is disabled.." "Drop Transmit Status is disabled,Drop Transmit Status is enabled" newline rbitfld.long 0x0 0. "RESERVED_0,Reserved." "0,1" group.long 0x8++0xB line.long 0x0 "MTL_DBG_CTL,The FIFO Debug Access Control and Status register controls the operation mode of FIFO debug access." hexmask.long.word 0x0 19.--31. 1. "RESERVED_31_19,Reserved." newline bitfld.long 0x0 17.--18. "EIEC,ECC Inject Error Control for Tx Rx and TSO memories When EIEE bit of this register is set following are the errors inserted based on the value encoded in this field. 0x0: Insert 1 bit error 0x3: Insert 1 bit error in address field 0x1: Insert 2.." "Insert 1 bit error,Insert 2 bit errors,Insert 3 bit errors,Insert 1 bit error in address field" newline bitfld.long 0x0 16. "EIEE,ECC Inject Error Enable for Tx Rx and TSO memories When set enables the ECC error injection feature. When reset disables the ECC error injection feature. 0x0: ECC Inject Error for Tx Rx and TSO memories is disabled 0x1: ECC Inject Error for Tx.." "ECC Inject Error for Tx,ECC Inject Error for Tx" newline bitfld.long 0x0 15. "STSIE,Transmit Status Available Interrupt Status Enable When this bit is set an interrupt is generated when Transmit status is available in slave mode. 0x0: Transmit Packet Available Interrupt Status is disabled 0x1: Transmit Packet Available Interrupt.." "Transmit Packet Available Interrupt Status is..,Transmit Packet Available Interrupt Status is.." newline bitfld.long 0x0 14. "PKTIE,Receive Packet Available Interrupt Status Enable When this bit is set an interrupt is generated when EOP of received packet is written to the Rx FIFO. 0x0: Receive Packet Available Interrupt Status is disabled 0x1: Receive Packet Available.." "Receive Packet Available Interrupt Status is..,Receive Packet Available Interrupt Status is.." newline bitfld.long 0x0 12.--13. "FIFOSEL,FIFO Selected for Access This field indicates the FIFO selected for debug access: 0x3: Rx FIFO 0x2: TSO FIFO (cannot be accessed when SLVMOD is set) 0x0: Tx FIFO 0x1: Tx Status FIFO (only read access when SLVMOD is set)" "Tx FIFO,Tx Status FIFO,TSO FIFO,Rx FIFO" newline bitfld.long 0x0 11. "FIFOWREN,FIFO Write Enable When this bit is set it enables the Write operation on selected FIFO when FIFO Debug Access is enabled. This bit must not be written to 1 when FIFO Debug Access is not enabled that is FDBGEN bit is 0. Access restriction.." "FIFO Write is disabled,FIFO Write is enabled" newline bitfld.long 0x0 10. "FIFORDEN,FIFO Read Enable When this bit is set it enables the Read operation on selected FIFO when FIFO Debug Access is enabled. This bit must not be written to 1 when FIFO Debug Access is not enabled that is FDBGEN bit is 0. Access restriction.." "FIFO Read is disabled,FIFO Read is enabled" newline bitfld.long 0x0 9. "RSTSEL,Reset Pointers of Selected FIFO When this bit is set the pointers of the currently-selected FIFO are reset when FIFO Debug Access is enabled. This bit must not be written to 1 when FIFO Debug Access is not enabled that is FDBGEN bit is 0. Access.." "Reset Pointers of Selected FIFO is disabled,Reset Pointers of Selected FIFO is enabled" newline bitfld.long 0x0 8. "RSTALL,Reset All Pointers When this bit is set the pointers of all FIFOs are reset when FIFO Debug Access is enabled. This bit must not be written to 1 when FIFO Debug Access is not enabled that is FDBGEN bit is 0. Access restriction applies." "Reset All Pointers is disabled,Reset All Pointers is enabled" newline rbitfld.long 0x0 7. "RESERVED_7,Reserved." "0,1" newline bitfld.long 0x0 5.--6. "PKTSTATE,Encoded Packet State This field is used to write the control information to the Tx FIFO or Rx FIFO. Tx FIFO: - 00: Packet Data - 01: Control Word - 10: SOP Data - 11: EOP Data Rx FIFO: - 00: Packet Data - 01: Normal Status - 10: Last Status -.." "Packet Data,Control Word/Normal Status,SOP Data/Last Status,EOP Data/EOP" newline rbitfld.long 0x0 4. "RESERVED_4,Reserved." "0,1" newline bitfld.long 0x0 2.--3. "BYTEEN,Byte Enables This field indicates the number of data bytes valid in the data register during Write operation. This is valid only when PKTSTATE is 2'b10 (EOP) and Tx FIFO or Rx FIFO is selected. 0x3: All four bytes are valid 0x2: Byte 0 Byte 1.." "Byte 0 valid,Byte 0 and Byte 1 are valid,Byte 0,All four bytes are valid" newline bitfld.long 0x0 1. "DBGMOD,Debug Mode Access to FIFO When this bit is set it indicates that the current access to the FIFO is read write and debug access. In this mode the following access types are allowed: - Read and Write access to Tx FIFO TSO FIFO and Rx FIFO -.." "Debug Mode Access to FIFO is disabled,Debug Mode Access to FIFO is enabled" newline bitfld.long 0x0 0. "FDBGEN,FIFO Debug Access Enable When this bit is set it indicates that the debug mode access to the FIFO is enabled. When this bit is reset it indicates that the FIFO can be accessed only through a master interface. 0x0: FIFO Debug Access is disabled.." "FIFO Debug Access is disabled,FIFO Debug Access is enabled" line.long 0x4 "MTL_DBG_STS,The FIFO Debug Status register contains the status of FIFO debug access." hexmask.long.tbyte 0x4 15.--31. 1. "LOCR,Remaining Locations in the FIFO Slave Access Mode: This field indicates the space available in selected FIFO. Debug Access Mode: This field contains the Write or Read pointer value of the selected FIFO during Write or Read operation respectively." newline hexmask.long.byte 0x4 10.--14. 1. "RESERVED_14_10,Reserved." newline bitfld.long 0x4 9. "STSI,Transmit Status Available Interrupt Status When set this bit indicates that the Slave mode Tx packet is transmitted and the status is available in Tx Status FIFO. This bit is reset when 1 is written to this bit. 0x1: Transmit Status Available.." "Transmit Status Available Interrupt Status not..,Transmit Status Available Interrupt Status.." newline bitfld.long 0x4 8. "PKTI,Receive Packet Available Interrupt Status When set this bit indicates that MAC layer has written the EOP of received packet to the Rx FIFO. This bit is reset when 1 is written to this bit. 0x1: Receive Packet Available Interrupt Status detected.." "Receive Packet Available Interrupt Status not..,Receive Packet Available Interrupt Status detected" newline rbitfld.long 0x4 5.--7. "RESERVED_7_5,Reserved." "0,1,2,3,4,5,6,7" newline rbitfld.long 0x4 3.--4. "BYTEEN,Byte Enables This field indicates the number of data bytes valid in the data register during Read operation. This is valid only when PKTSTATE is 2'b10 (EOP) and Tx FIFO or Rx FIFO is selected. 0x3: All four bytes are valid 0x2: Byte 0 Byte 1 and.." "Byte 0 valid,Byte 0 and Byte 1 are valid,Byte 0,All four bytes are valid" newline rbitfld.long 0x4 1.--2. "PKTSTATE,Encoded Packet State This field is used to get the control or status information of the selected FIFO. Tx FIFO: - 00: Packet Data - 01: Control Word - 10: SOP Data - 11: EOP Data Rx FIFO: - 00: Packet Data - 01: Normal Status - 10: Last Status -.." "Packet Data,Control Word/Normal Status,SOP Data/Last Status,EOP Data/EOP" newline rbitfld.long 0x4 0. "FIFOBUSY,FIFO Busy When set this bit indicates that a FIFO operation is in progress in the MAC and content of the following fields is not valid: - All other fields of this register - All fields of the MTL_FIFO_Debug_Data register 0x1: FIFO Busy detected.." "FIFO Busy not detected,FIFO Busy detected" line.long 0x8 "MTL_FIFO_DEBUG_DATA,The FIFO Debug Data register contains the data to be written to or read from the FIFOs." hexmask.long 0x8 0.--31. 1. "FDBGDATA,FIFO Debug Data During debug or slave access write operation this field contains the data to be written to the Tx FIFO Rx FIFO or TSO FIFO. During debug or slave access read operation this field contains the data read from the Tx FIFO Rx.." rgroup.long 0x20++0x3 line.long 0x0 "MTL_INTERRUPT_STATUS,The software driver (application) reads this register during interrupt service routine or polling to determine the interrupt status of MTL queues and the MAC." hexmask.long.byte 0x0 24.--31. 1. "RESERVED_31_24,Reserved." newline bitfld.long 0x0 23. "MTLPIS,MTL Rx Parser Interrupt Status This bit indicates that there is an interrupt from Rx Parser Block. To reset this bit the application must read the MTL_ Rxp_Interrupt_Status register to get the exact cause of the interrupt and clear its source." "MTL Rx Parser Interrupt status not detected,MTL Rx Parser Interrupt status detected" newline hexmask.long.byte 0x0 19.--22. 1. "RESERVED_22_19,Reserved." newline bitfld.long 0x0 18. "ESTIS,EST (TAS- 802.1Qbv) Interrupt Status This bit indicates an interrupt event during the operation of 802.1Qbv. To reset this bit the application must clear the error/event that has caused the Interrupt. 0x1: EST (TAS- 802.1Qbv) Interrupt status.." "EST,EST" newline bitfld.long 0x0 17. "DBGIS,Debug Interrupt status This bit indicates an interrupt event during the slave access. To reset this bit the application must read the FIFO Debug Access Status register to get the exact cause of the interrupt and clear its source. 0x1: Debug.." "Debug Interrupt status not detected,Debug Interrupt status detected" newline bitfld.long 0x0 16. "RESERVED_MACIS,Reserved." "0,1" newline hexmask.long.byte 0x0 8.--15. 1. "RESERVED_15_8,Reserved." newline bitfld.long 0x0 7. "RESERVED_Q7IS,Reserved." "0,1" newline bitfld.long 0x0 6. "RESERVED_Q6IS,Reserved." "0,1" newline bitfld.long 0x0 5. "RESERVED_Q5IS,Reserved." "0,1" newline bitfld.long 0x0 4. "Q4IS,Queue 4 Interrupt status This bit indicates that there is an interrupt from Queue 4. To reset this bit the application must read the MTL_Q4_Interrupt_Control_Status register to get the exact cause of the interrupt and clear its source. 0x1: Queue 4.." "Queue 4 Interrupt status not detected,Queue 4 Interrupt status detected" newline bitfld.long 0x0 3. "Q3IS,Queue 3 Interrupt status This bit indicates that there is an interrupt from Queue 3. To reset this bit the application must read the MTL_Q3_Interrupt_Control_Status register to get the exact cause of the interrupt and clear its source. 0x1: Queue 3.." "Queue 3 Interrupt status not detected,Queue 3 Interrupt status detected" newline bitfld.long 0x0 2. "Q2IS,Queue 2 Interrupt status This bit indicates that there is an interrupt from Queue 2. To reset this bit the application must read the MTL_Q2_Interrupt_Control_Status register to get the exact cause of the interrupt and clear its source. 0x1: Queue 2.." "Queue 2 Interrupt status not detected,Queue 2 Interrupt status detected" newline bitfld.long 0x0 1. "Q1IS,Queue 1 Interrupt status This bit indicates that there is an interrupt from Queue 1. To reset this bit the application must read the MTL_Q1_Interrupt_Control_Status register to get the exact cause of the interrupt and clear its source. 0x1: Queue 1.." "Queue 1 Interrupt status not detected,Queue 1 Interrupt status detected" newline bitfld.long 0x0 0. "Q0IS,Queue 0 Interrupt status This bit indicates that there is an interrupt from Queue 0. To reset this bit the application must read Queue 0 Interrupt Control and Status register to get the exact cause of the interrupt and clear its source. 0x1: Queue.." "Queue 0 Interrupt status not detected,Queue 0 Interrupt status detected" group.long 0x30++0x7 line.long 0x0 "MTL_RXQ_DMA_MAP0,The Receive Queue and DMA Channel Mapping 0 register is reserved in EQOS-CORE and EQOS-MTL configurations." rbitfld.long 0x0 29.--31. "RESERVED_31_29,Reserved." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 28. "Q3DDMACH,Queue 3 Enabled for Dynamic (per packet) DMA Channel Selection When set this bit indicates that the packets received in Queue 3 are routed to a particular DMA channel as decided in the MAC Receiver based on the DMA channel number programmed in.." "Queue 3 disabled for DA-based DMA Channel..,Queue 3 enabled for DA-based DMA Channel Selection" newline rbitfld.long 0x0 27. "RESERVED_27_Y,Reserved." "0,1" newline bitfld.long 0x0 24.--26. "Q3MDMACH,Queue 3 Mapped to DMA Channel This field controls the routing of the received packet in Queue 3 to the DMA channel: - 000: DMA Channel 0 - 001: DMA Channel 1 - 010: DMA Channel 2 - 011: DMA Channel 3 - 100: DMA Channel 4 - 101: DMA Channel 5 -.." "DMA Channel 0,DMA Channel 1,?,?,?,?,?,?" newline rbitfld.long 0x0 21.--23. "RESERVED_23_21,Reserved." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 20. "Q2DDMACH,Queue 2 Enabled for DA-based DMA Channel Selection When set this bit indicates that the packets received in Queue 2 are routed to a particular DMA channel as decided in the MAC Receiver based on the DMA channel number programmed in the L3-L4.." "Queue 2 disabled for DA-based DMA Channel..,Queue 2 enabled for DA-based DMA Channel Selection" newline rbitfld.long 0x0 19. "RESERVED_19_Y,Reserved." "0,1" newline bitfld.long 0x0 16.--18. "Q2MDMACH,Queue 2 Mapped to DMA Channel This field controls the routing of the received packet in Queue 2 to the DMA channel: - 000: DMA Channel 0 - 001: DMA Channel 1 - 010: DMA Channel 2 - 011: DMA Channel 3 - 100: DMA Channel 4 - 101: DMA Channel 5 -.." "DMA Channel 0,DMA Channel 1,?,?,?,?,?,?" newline rbitfld.long 0x0 13.--15. "RESERVED_15_13,Reserved." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 12. "Q1DDMACH,Queue 1 Enabled for DA-based DMA Channel Selection When set this bit indicates that the packets received in Queue 1 are routed to a particular DMA channel as decided in the MAC Receiver based on the DMA channel number programmed in the L3-L4.." "Queue 1 disabled for DA-based DMA Channel..,Queue 1 enabled for DA-based DMA Channel Selection" newline rbitfld.long 0x0 11. "RESERVED_11_Y,Reserved." "0,1" newline bitfld.long 0x0 8.--10. "Q1MDMACH,Queue 1 Mapped to DMA Channel This field controls the routing of the received packet in Queue 1 to the DMA channel: - 000: DMA Channel 0 - 001: DMA Channel 1 - 010: DMA Channel 2 - 011: DMA Channel 3 - 100: DMA Channel 4 - 101: DMA Channel 5 -.." "DMA Channel 0,DMA Channel 1,?,?,?,?,?,?" newline rbitfld.long 0x0 5.--7. "RESERVED_7_5,Reserved." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 4. "Q0DDMACH,Queue 0 Enabled for DA-based DMA Channel Selection When set this bit indicates that the packets received in Queue 0 are routed to a particular DMA channel as decided in the MAC Receiver based on the DMA channel number programmed in the L3-L4.." "Queue 0 disabled for DA-based DMA Channel..,Queue 0 enabled for DA-based DMA Channel Selection" newline rbitfld.long 0x0 3. "RESERVED_3_Y,Reserved." "0,1" newline bitfld.long 0x0 0.--2. "Q0MDMACH,Queue 0 Mapped to DMA Channel This field controls the routing of the packet received in Queue 0 to the DMA channel: - 000: DMA Channel 0 - 001: DMA Channel 1 - 010: DMA Channel 2 - 011: DMA Channel 3 - 100: DMA Channel 4 - 101: DMA Channel 5 -.." "DMA Channel 0,DMA Channel 1,?,?,?,?,?,?" line.long 0x4 "MTL_RXQ_DMA_MAP1,The Receive Queue and DMA Channel Mapping 1 register is reserved in EQOS-CORE and EQOS-MTL configurations." rbitfld.long 0x4 29.--31. "RESERVED_31_29,Reserved." "0,1,2,3,4,5,6,7" newline rbitfld.long 0x4 28. "RESERVED_Q7DDMACH,Reserved." "0,1" newline rbitfld.long 0x4 27. "RESERVED_27_Y,Reserved." "0,1" newline rbitfld.long 0x4 24.--26. "RESERVED_Q7MDMACH,Reserved." "0,1,2,3,4,5,6,7" newline rbitfld.long 0x4 21.--23. "RESERVED_23_21,Reserved." "0,1,2,3,4,5,6,7" newline rbitfld.long 0x4 20. "RESERVED_Q6DDMACH,Reserved." "0,1" newline rbitfld.long 0x4 19. "RESERVED_19_Y,Reserved." "0,1" newline rbitfld.long 0x4 16.--18. "RESERVED_Q6MDMACH,Reserved." "0,1,2,3,4,5,6,7" newline rbitfld.long 0x4 13.--15. "RESERVED_15_13,Reserved." "0,1,2,3,4,5,6,7" newline rbitfld.long 0x4 12. "RESERVED_Q5DDMACH,Reserved." "0,1" newline rbitfld.long 0x4 11. "RESERVED_11_Y,Reserved." "0,1" newline rbitfld.long 0x4 8.--10. "RESERVED_Q5MDMACH,Reserved." "0,1,2,3,4,5,6,7" newline rbitfld.long 0x4 5.--7. "RESERVED_7_5,Reserved." "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 4. "Q4DDMACH,Queue 4 Enabled for DA-based DMA Channel Selection When set this bit indicates that the packets received in Queue 4 are routed to a particular DMA channel as decided in the MAC Receiver based on the DMA channel number programmed in the L3-L4.." "Queue 4 disabled for DA-based DMA Channel..,Queue 4 enabled for DA-based DMA Channel Selection" newline rbitfld.long 0x4 3. "RESERVED_3_Y,Reserved." "0,1" newline bitfld.long 0x4 0.--2. "Q4MDMACH,Queue 4 Mapped to DMA Channel This field controls the routing of the packet received in Queue 4 to the DMA channel: - 000: DMA Channel 0 - 001: DMA Channel 1 - 010: DMA Channel 2 - 011: DMA Channel 3 - 100: DMA Channel 4 - 101: DMA Channel 5 -.." "DMA Channel 0,DMA Channel 1,?,?,?,?,?,?" group.long 0x40++0x3 line.long 0x0 "MTL_TBS_CTRL,This register controls the operation of Time Based Scheduling." hexmask.long.tbyte 0x0 8.--31. 1. "LEOS,Launch Expiry Offset The value in units of 256 nanoseconds that has to be added to the Launch time to compute the Launch Expiry time. Value valid only when LEOV is set. Max value: 999 999 999 ns additionally should be smaller than CTR-1 value when.." newline rbitfld.long 0x0 7. "RESERVED_7,Reserved." "0,1" newline bitfld.long 0x0 4.--6. "LEGOS,Launch Expiry GSN Offset The number GSN slots that has to be added to the Launch GSN to compute the Launch Expiry time. Value valid only when LEOV is set." "0,1,2,3,4,5,6,7" newline rbitfld.long 0x0 2.--3. "RESERVED_3_2,Reserved." "0,1,2,3" newline bitfld.long 0x0 1. "LEOV,Launch Expiry Offset Valid When set indicates the LEOS field is valid. When not set indicates the Launch Expiry Offset is not valid and the MTL must not check for Launch expiry time. 0x0: LEOS field is invalid 0x1: LEOS field is valid" "LEOS field is invalid,LEOS field is valid" newline bitfld.long 0x0 0. "ESTM,EST offset Mode When this bit is set the Launch Time value used in Time Based Scheduling is interpreted as an EST offset value and is added to the Base Time Register (BTR) of the current list. When reset the Launch Time value is used as an.." "EST offset Mode is disabled,EST offset Mode is enabled" group.long 0x50++0x3 line.long 0x0 "MTL_EST_CONTROL,This register controls the operation of Enhancements to Scheduled Transmission (IEEE802.1Qbv)." hexmask.long.byte 0x0 24.--31. 1. "PTOV,PTP Time Offset Value The value of PTP Clock period multiplied by 6 in nanoseconds. This value is needed to avoid transmission overruns at the beginning of the installation of a new GCL." newline hexmask.long.word 0x0 12.--23. 1. "CTOV,Current Time Offset Value Provides a 12 bit time offset value in nano second that is added to the current time to compensate for all the implementation pipeline delays such as the CDC sync delay buffering delays data path delays etc. This offset.." newline rbitfld.long 0x0 11. "RESERVED_11,Reserved." "0,1" newline bitfld.long 0x0 8.--10. "TILS,Time Interval Left Shift Amount This field provides the left shift amount for the programmed Time Interval values used in the Gate Control Lists. - 000: No left shift needed (equal to x1ns) - 001: Left shift TI by 1 bit (equal to x2ns) - 010: Left.." "No left shift needed,Left shift TI by 1 bit,?,?,?,?,?,?" newline bitfld.long 0x0 6.--7. "LCSE,Loop Count to report Scheduling Error Programmable number of GCL list iterations before reporting an HLBS error defined in EST_Status register. 0x2: 16 iterations 0x3: 32 iterations 0x0: 4 iterations 0x1: 8 iterations" "0,1,2,3" newline bitfld.long 0x0 5. "DFBS,Drop Frames causing Scheduling Error When set frames reported to cause HOL Blocking due to not getting scheduled (HLBS field of EST_Status register) after 4 8 16 32 (based on LCSE field of this register) GCL iterations are dropped. 0x0: Do not Drop.." "Do not Drop Frames causing Scheduling Error,Drop Frames causing Scheduling Error" newline bitfld.long 0x0 4. "DDBF,Do not Drop frames during Frame Size Error When set frames are not be dropped during Head-of-Line blocking due to Frame Size Error (HLBF field of EST_Status register). 0x1: Do not Drop frames during Frame Size Error 0x0: Drop frames during Frame.." "Drop frames during Frame Size Error,Do not Drop frames during Frame Size Error" newline rbitfld.long 0x0 2.--3. "RESERVED_2_3,Reserved." "0,1,2,3" newline bitfld.long 0x0 1. "SSWL,Switch to S/W owned list When set indicates that the software has programmed that list that it currently owns (SWOL) and the hardware should switch to the new list based on the new BTR. Hardware clears this bit when the switch to the SWOL happens to.." "Switch to S/W owned list is disabled,Switch to S/W owned list is enabled" newline bitfld.long 0x0 0. "EEST,Enable EST When reset the gate control list processing is halted and all gates are assumed to be in Open state. Should be set for the hardware to start processing the gate control lists. During the toggle from 0 to 1 the gate control list.." "EST is disabled,EST is enabled" group.long 0x58++0x3 line.long 0x0 "MTL_EST_STATUS,This register provides Status related to Enhancements to Scheduled Transmission (IEEE802.1Qbv)." hexmask.long.word 0x0 20.--31. 1. "RESERVED_31_20,Reserved." newline hexmask.long.byte 0x0 16.--19. 1. "CGSN,Current GCL Slot Number Indicates the slot number of the GCL list. Slot number is a modulo 16 count of the GCL List loops executed so far. Even if a new GCL list is installed the count is incremental." newline hexmask.long.byte 0x0 12.--15. 1. "RESERVED_15_12,Reserved." newline hexmask.long.byte 0x0 8.--11. 1. "BTRL,BTR Error Loop Count Provides the minimum count (N) for which the equation Current Time =< New BTR + (N * New Cycle Time) becomes true. N = '1111' indicates the iterations exceeded the value of 8 and the hardware was not able to update New BTR to be.." newline rbitfld.long 0x0 7. "SWOL,S/W owned list When '0' indicates Gate control list number '0' is owned by software and when '1' indicates the Gate Control list '1' is owned by the software. Any reads/writes by the software (using indirect access via GCL_Control) is directed to.." "Gate control list number '0' is owned by software,Gate control list number '1' is owned by software" newline rbitfld.long 0x0 5.--6. "RESERVED_6_5,Reserved." "0,1,2,3" newline bitfld.long 0x0 4. "CGCE,Constant Gate Control Error This error occurs when the list length (LLR) is 1 and the programmed Time Interval (TI) value after the optional Left Shifting is less than or equal to the Cycle Time (CTR). The above programming implies Gates are either.." "Constant Gate Control Error not detected,Constant Gate Control Error detected" newline rbitfld.long 0x0 3. "HLBS,Head-Of-Line Blocking due to Scheduling Set when the frame is not able to win arbitration and get scheduled even after 4 iterations of the GCL. Indicates to software a potential programming error. The one hot encoded values of the Queue Numbers that.." "Head-Of-Line Blocking due to Scheduling not..,Head-Of-Line Blocking due to Scheduling detected" newline rbitfld.long 0x0 2. "HLBF,Head-Of-Line Blocking due to Frame Size Set when HOL Blocking is noticed on one or more Queues as a result of none of the Time Intervals of gate open in the GCL being greater than or equal to the duration needed for frame size (or frame fragment.." "Head-Of-Line Blocking due to Frame Size not..,Head-Of-Line Blocking due to Frame Size detected" newline bitfld.long 0x0 1. "BTRE,BTR Error When '1' indicates a programming error in the BTR of SWOL where the programmed value is less than current time. If the BTRL = '1111' SWOL is not updated and Software should reprogram the BTR to a value greater than current time and then.." "BTR Error not detected,BTR Error detected" newline bitfld.long 0x0 0. "SWLC,Switch to S/W owned list Complete When '1' indicates the hardware has successfully switched to the SWOL and the SWOL bit has been updated to that effect. Cleared when the SSWL of EST_Control register transitions from 0 to 1 or on a software write." "Switch to S/W owned list Complete not detected,Switch to S/W owned list Complete detected" group.long 0x60++0x7 line.long 0x0 "MTL_EST_SCH_ERROR,This register provides the One Hot encoded Queue Numbers that are having the Scheduling related error (timeout)." hexmask.long 0x0 5.--31. 1. "RESERVED_31_X,Reserved." newline hexmask.long.byte 0x0 0.--4. 1. "SEQN,Schedule Error Queue Number The One Hot Encoded Queue Numbers that have experienced error/timeout described in HLBS field of status register. Access restriction applies. Self-set to 1 on internal event. Setting 1 clears. Setting 0 has no effect." line.long 0x4 "MTL_EST_FRM_SIZE_ERROR,This register provides the One Hot encoded Queue Numbers that are having the Frame Size related error." hexmask.long 0x4 5.--31. 1. "RESERVED_31_X,Reserved." newline hexmask.long.byte 0x4 0.--4. 1. "FEQN,Frame Size Error Queue Number The One Hot Encoded Queue Numbers that have experienced error described in HLBF field of status register. Access restriction applies. Self-set to 1 on internal event. Setting 1 clears. Setting 0 has no effect." rgroup.long 0x68++0x3 line.long 0x0 "MTL_EST_FRM_SIZE_CAPTURE,This register captures the Frame Size and Queue Number of the first occurrence of the Frame Size related error. Up on clearing it captures the data of immediate next occurrence of a similar error." hexmask.long.word 0x0 19.--31. 1. "RESERVED_31_X,Reserved." newline bitfld.long 0x0 16.--18. "HBFQ,Queue Number of HLBF Captures the binary value of the of the first Queue (number) experiencing HLBF error (see HLBF field of status register). Value once written is not altered by any subsequent queue errors of similar nature. Once cleared the queue.." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 15. "RESERVED_15,Reserved." "0,1" newline hexmask.long.word 0x0 0.--14. 1. "HBFS,Frame Size of HLBF Captures the Frame Size of the dropped frame related to queue number indicated in HBFQ field of this register. Contents of this register should be considered invalid if this field is zero. Cleared when MTL_EST_Frm_Size_Error.." group.long 0x70++0x3 line.long 0x0 "MTL_EST_INTR_ENABLE,This register implements the Interrupt Enable bits for the various events that generate an interrupt. Bit positions have a 1 to 1 correlation with the status bit positions in MTL_ETS_Status register." hexmask.long 0x0 5.--31. 1. "RESERVED_31_5,Reserved." newline bitfld.long 0x0 4. "CGCE,Interrupt Enable for CGCE When set generates interrupt when the Constant Gate Control Error occurs and is indicated in the status. When reset this event does not generate an interrupt 0x0: Interrupt for CGCE is disabled 0x1: Interrupt for CGCE is.." "Interrupt for CGCE is disabled,Interrupt for CGCE is enabled" newline bitfld.long 0x0 3. "IEHS,Interrupt Enable for HLBS When set generates interrupt when the Head-of-Line Blocking due to Scheduling issue and is indicated in the status. When reset this event does not generate an interrupt. 0x0: Interrupt for HLBS is disabled 0x1: Interrupt.." "Interrupt for HLBS is disabled,Interrupt for HLBS is enabled" newline bitfld.long 0x0 2. "IEHF,Interrupt Enable for HLBF When set generates interrupt when the Head-of-Line Blocking due to Frame Size error occurs and is indicated in the status. When reset this event does not generate an interrupt. 0x0: Interrupt for HLBF is disabled 0x1:.." "Interrupt for HLBF is disabled,Interrupt for HLBF is enabled" newline bitfld.long 0x0 1. "IEBE,Interrupt Enable for BTR Error When set generates interrupt when the BTR Error occurs and is indicated in the status. When reset this event does not generate an interrupt. 0x0: Interrupt for BTR Error is disabled 0x1: Interrupt for BTR Error is.." "Interrupt for BTR Error is disabled,Interrupt for BTR Error is enabled" newline bitfld.long 0x0 0. "IECC,Interrupt Enable for Switch List When set generates interrupt when the configuration change is successful and the hardware has switched to the new list. When reset this event does not generate an interrupt. 0x0: Interrupt for Switch List is.." "Interrupt for Switch List is disabled,Interrupt for Switch List is enabled" group.long 0x80++0x7 line.long 0x0 "MTL_EST_GCL_CONTROL,This register provides the control information for reading/writing to the Gate Control lists." hexmask.long.byte 0x0 24.--31. 1. "RESERVED_31_24,Reserved." newline bitfld.long 0x0 22.--23. "ESTEIEC,ECC Inject Error Control for EST Memory When EIEE bit of this register is set following are the errors inserted based on the value encoded in this field. This filed will be valid only if DWC_EQOS_ASP_ECC feature is selected during the.." "Insert 1 bit error,Insert 2 bit errors,Insert 3 bit errors,Insert 1 bit error in address field" newline bitfld.long 0x0 21. "ESTEIEE,EST ECC Inject Error Enable When set along with EEST bit of MTL_EST_Control register enables the ECC error injection feature. When reset disables the ECC error injection feature. 0x0: EST ECC Inject Error is disabled 0x1: EST ECC Inject Error.." "EST ECC Inject Error is disabled,EST ECC Inject Error is enabled" newline bitfld.long 0x0 20. "ERR0,When set indicates the last write operation was aborted as software writes to GCL and GCL registers is prohibited when SSWL bit of MTL_EST_Control Register is set. Access restriction applies. Self-set to 1 on internal event. Setting 1 clears." "ERR0 is disabled,ERR1 is enabled" newline rbitfld.long 0x0 18.--19. "RESERVED_19_Y,Reserved." "0,1,2,3" newline hexmask.long.word 0x0 8.--17. 1. "ADDR,Gate Control List Address: (GCLA when GCRR is '0'). Provides the address (row number) of the Gate Control List at which the R/W operation has to be performed. By default the Gate Control List pointed by SWOL of MTL_EST_Status is selected for R/W.." newline bitfld.long 0x0 6.--7. "RESERVED_7_6,Reserved." "0,1,2,3" newline bitfld.long 0x0 5. "DBGB,Debug Mode Bank Select When set to '0' indicates R/W in debug mode should be directed to Bank 0 (GCL0 and corresponding Time related registers). When set to '1' indicates R/W in debug mode should be directed to Bank 1 (GCL1 and corresponding Time.." "R/W in debug mode should be directed to Bank 0,R/W in debug mode should be directed to Bank 1" newline bitfld.long 0x0 4. "DBGM,Debug Mode When set to '1' indicates R/W in debug mode where the memory bank (for GCL and Time related registers) is explicitly provided by DBGB value when set to '0' SWOL bit is used to determine which bank to use. 0x0: Debug Mode is disabled 0x1:.." "Debug Mode is disabled,Debug Mode is enabled" newline bitfld.long 0x0 3. "RESERVED_3,Reserved." "0,1" newline bitfld.long 0x0 2. "GCRR,Gate Control Related Registers When set to '1' indicates the R/W access is for the GCL related registers (BTR CTR TER LLR) whose address is provided by GCRA. When '0' indicates R/W should be directed to GCL from the address provided by GCLA. 0x0:.." "Gate Control Related Registers are disabled,Gate Control Related Registers are enabled" newline bitfld.long 0x0 1. "R1W0,Read '1' Write '0': When set to '1': Read Operation When set to '0': Write Operation. 0x1: Read Operation 0x0: Write Operation" "Write Operation,Read Operation" newline bitfld.long 0x0 0. "SRWO,Start Read/Write Op When set indicates a Read/Write Op has started and is in progress. When reset by hardware indicates the R/W Op has completed or an error has occurred (when bit 20 is set) Reads: Data can be read from MTL_EST_GCL_Data register.." "Start Read/Write Op disabled,Start Read/Write Op enabled" line.long 0x4 "MTL_EST_GCL_DATA,This register holds the read data or write data in case of reads and writes respectively." hexmask.long 0x4 0.--31. 1. "GCD,Gate Control Data The data corresponding to the address selected in the GCL_Control register. Used for both Read and Write operations." group.long 0x90++0x7 line.long 0x0 "MTL_FPE_CTRL_STS,This register controls the operation of. and provides status for Frame Preemption (IEEE802.1Qbu/802.3br)." rbitfld.long 0x0 29.--31. "RESERVED_31_29,Reserved." "0,1,2,3,4,5,6,7" newline rbitfld.long 0x0 28. "HRS,Hold/Release Status - 1: Indicates a Set-and-Hold-MAC operation was last executed and the pMAC is in Hold State. - 0: Indicates a Set-and-Release-MAC operation was last executed and the pMAC is in Release State. 0x1: Indicates a Set-and-Hold-MAC.." "Indicates a Set-and-Release-MAC operation was..,Indicates a Set-and-Hold-MAC operation was last.." newline hexmask.long.word 0x0 16.--27. 1. "RESERVED_27_16,Reserved." newline rbitfld.long 0x0 13.--15. "RESERVED_15_Y,Reserved." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x0 8.--12. 1. "PEC,Preemption Classification When set indicates the corresponding Queue must be classified as preemptable when '0' Queue is classified as express. When both EST (Qbv) and Preemption are enabled Queue-0 is always assumed to be preemptable. When EST.." newline hexmask.long.byte 0x0 2.--7. 1. "RESERVED_7_2,Reserved." newline bitfld.long 0x0 0.--1. "AFSZ,Additional Fragment Size used to indicate in units of 64 bytes the minimum number of bytes over 64 bytes required in non-final fragments of preempted frames. The minimum non-final fragment size is (AFSZ +1) * 64 bytes" "0,1,2,3" line.long 0x4 "MTL_FPE_ADVANCE,This register holds the Hold and Release Advance time." hexmask.long.word 0x4 16.--31. 1. "RADV,Release Advance The maximum time in nanoseconds that can elapse between issuing a RELEASE to the MAC and the MAC being ready to resume transmission of preemptable frames in the absence of there being any express frames available for transmission." newline hexmask.long.word 0x4 0.--15. 1. "HADV,Hold Advance The maximum time in nanoseconds that can elapse between issuing a HOLD to the MAC and the MAC ceasing to transmit any preemptable frame that is in the process of transmission or any preemptable frames that are queued for transmission." group.long 0xA0++0x7 line.long 0x0 "MTL_RXP_CONTROL_STATUS,The MTL_RXP_Control_Status register establishes the operating mode of Rx Parser and provides some status." rbitfld.long 0x0 31. "RXPI,RX Parser in Idle state This status bit is set to 1 when the Rx parser is in Idle State and waiting for a new packet for processing. This bit is used as a handshake with software when parser gets disables. After disabling when bit is set then.." "RX Parser not in Idle state,RX Parser in Idle state" newline hexmask.long.byte 0x0 24.--30. 1. "RESERVED_30_X,Reserved." newline hexmask.long.byte 0x0 16.--23. 1. "NPE,Number of parsable entries in the Instruction table This control indicates the number of parsable entries in the Instruction Memory. This is used in Rx parser logic to detect programming Error. In case number of parsed entries for a packet is more.." newline hexmask.long.byte 0x0 8.--15. 1. "RESERVED_15_X,Reserved." newline hexmask.long.byte 0x0 0.--7. 1. "NVE,Number of valid entries in the Instruction table This control indicates the number of valid entries in the Instruction Memory. This is used in Rx parser logic to detect any programming Error. In case while parsing Table address (memory address) found.." line.long 0x4 "MTL_RXP_INTERRUPT_CONTROL_STATUS,The MTL_RXP_Interrupt_Control_Status registers provides enable control for the interrupts and provides interrupt status." hexmask.long.word 0x4 20.--31. 1. "RESERVED_31_20,Reserved." newline bitfld.long 0x4 19. "PDRFIE,Packet Drop due to RF Interrupt Enable When this bit is set the PDRFIS interrupt is enabled. When this bit is reset the PDRFIS interrupt is disabled. 0x0: Packet Drop due to RF Interrupt is disabled 0x1: Packet Drop due to RF Interrupt is enabled" "Packet Drop due to RF Interrupt is disabled,Packet Drop due to RF Interrupt is enabled" newline bitfld.long 0x4 18. "FOOVIE,Frame Offset Overflow Interrupt Enable When this bit is set the FOOVIS interrupt is enabled. When this bit is reset the FOOVIS interrupt is disabled. 0x0: Frame Offset Overflow Interrupt is disabled 0x1: Frame Offset Overflow Interrupt is enabled" "Frame Offset Overflow Interrupt is disabled,Frame Offset Overflow Interrupt is enabled" newline rbitfld.long 0x4 17. "RESERVED,Reserved" "0,1" newline bitfld.long 0x4 16. "NVEOVIE,Number of Valid Entries Overflow Interrupt Enable When this bit is set the NVEOVIS interrupt is enabled. When this bit is reset the NVEOVIS interrupt is disabled. 0x0: Number of Valid Entries Overflow Interrupt is disabled 0x1: Number of Valid.." "Number of Valid Entries Overflow Interrupt is..,Number of Valid Entries Overflow Interrupt is.." newline hexmask.long.word 0x4 4.--15. 1. "RESERVED_15_4,Reserved." newline bitfld.long 0x4 3. "PDRFIS,Packet Dropped due to RF Interrupt Status If the Rx Parser result says to drop the packet by setting RF=1 in the instruction memory then this bit is set to 1. This bit is cleared when the application writes 1 to this bit. Access restriction.." "Packet Dropped due to RF Interrupt Status not..,Packet Dropped due to RF Interrupt Status detected" newline bitfld.long 0x4 2. "FOOVIS,Frame Offset Overflow Interrupt Status While parsing if the Instruction table entry's 'Frame Offset' found to be more than EOF offset then then this bit is set. This bit is cleared when the application writes 1 to this bit. Access restriction.." "Frame Offset Overflow Interrupt Status not..,Frame Offset Overflow Interrupt Status detected" newline bitfld.long 0x4 1. "NPEOVIS,Number of Parsable Entries Overflow Interrupt Status While parsing a packet if the number of parsed entries found to be more than NPE[] (Number of Parseable Entries in MTL_RXP_Control register) then this bit is set to 1. This bit is cleared when.." "Number of Parsable Entries Overflow Interrupt..,Number of Parsable Entries Overflow Interrupt.." newline bitfld.long 0x4 0. "NVEOVIS,Number of Valid Entries Overflow Interrupt Status While parsing if the Instruction address found to be more than NVE (Number of Valid Entries in MTL_RXP_Control register) then this bit is set to 1. This bit is cleared when the application writes.." "Number of Valid Entries Overflow Interrupt..,Number of Valid Entries Overflow Interrupt.." rgroup.long 0xA8++0x7 line.long 0x0 "MTL_RXP_DROP_CNT,The MTL_RXP_Drop_Cnt register provides the drop count of Rx Parser initiated drops." bitfld.long 0x0 31. "RXPDCOVF,Rx Parser Drop Counter Overflow Bit When set this bit indicates that the MTL_RXP_Drop_cnt (RXPDC) Counter field crossed the maximum limit. Access restriction applies. Clears on read. Self-set to 1 on internal event. 0x1: Rx Parser Drop count.." "Rx Parser Drop count overflow not occurred,Rx Parser Drop count overflow occurred" newline hexmask.long 0x0 0.--30. 1. "RXPDC,Rx Parser Drop count This 31-bit counter is implemented whenever a Rx Parser Drops a packet due to RF =1. The counter is cleared when the register is read." line.long 0x4 "MTL_RXP_ERROR_CNT,The MTL_RXP_Error_Cnt register provides the Rx Parser related error occurrence count." bitfld.long 0x4 31. "RXPECOVF,Rx Parser Error Counter Overflow Bit When set this bit indicates that the MTL_RXP_Error_cnt (RXPEC) Counter field crossed the maximum limit. Access restriction applies. Clears on read. Self-set to 1 on internal event. 0x1: Rx Parser Error count.." "Rx Parser Error count overflow not occurred,Rx Parser Error count overflow occurred" newline hexmask.long 0x4 0.--30. 1. "RXPEC,Rx Parser Error count This 31-bit counter is implemented whenever a Rx Parser encounters following Error scenarios - Entry address >= NVE[] - Number Parsed Entries >= NPE[] - Entry address > EOF data entry address The counter is cleared when the.." group.long 0xB0++0x3 line.long 0x0 "MTL_RXP_INDIRECT_ACC_CONTROL_STATUS,The MTL_RXP_Indirect_Acc_Control_Status register provides the Indirect Access control and status for Rx Parser memory." bitfld.long 0x0 31. "STARTBUSY,FRP Instruction Table Access Busy When this bit is set to 1 by the software then it indicates to start the Read/Write operation from/to the Rx Parser Memory. Software should read this bit as 0 before issuing read or write request to access the.." "hardware not busy,hardware is busy" newline hexmask.long.byte 0x0 23.--30. 1. "RESERVED_30_23,Reserved." newline bitfld.long 0x0 21.--22. "RXPEIEC,ECC Inject Error Control for Rx Parser Memory When EIEE bit of this register is set following are the errors inserted based on the value encoded in this field. 0x0: Insert 1 bit error 0x3: Insert 1 bit error in address field 0x1: Insert 2 bit.." "Insert 1 bit error,Insert 2 bit errors,Insert 3 bit errors,Insert 1 bit error in address field" newline bitfld.long 0x0 20. "RXPEIEE,ECC Inject Error Enable for Rx Parser Memory When set enables the ECC error injection feature. When reset disables the ECC error injection feature. 0x0: ECC Inject Error for Rx Parser Memory is disabled 0x1: ECC Inject Error for Rx Parser.." "ECC Inject Error for Rx Parser Memory is disabled,ECC Inject Error for Rx Parser Memory is enabled" newline rbitfld.long 0x0 17.--19. "RESERVED_19_17,Reserved." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 16. "WRRDN,Read Write Control When this bit is set to 1 indicates the write operation to the Rx Parser Memory. When this bit is set to 0 indicates the read operation to the Rx Parser Memory. 0x0: Read operation to the Rx Parser Memory 0x1: Write operation to.." "Read operation to the Rx Parser Memory,Write operation to the Rx Parser Memory" newline hexmask.long.byte 0x0 10.--15. 1. "RESERVED_15_X,Reserved." newline hexmask.long.word 0x0 0.--9. 1. "ADDR,FRP Instruction Table Offset Address This field indicates the ADDR of the 32-bit entry in Rx parser instruction table. Each entry has 128-bit (4x32-bit words). The X depends on the configurable DWC_EQOS_FRP_ENTRIES If DWC_EQOS_FRP_ENTRIES == 256.." rgroup.long 0xB4++0x3 line.long 0x0 "MTL_RXP_INDIRECT_ACC_DATA,The MTL_RXP_Indirect_Acc_Data registers holds the data associated to Indirect Access to Rx Parser memory." hexmask.long 0x0 0.--31. 1. "DATA,FRP Instruction Table Write/Read Data Software should write this register before issuing any write command. The hardware provides the read data from the Rx Parser Memory for read operation when STARTBUSY =0 after read command." group.long 0xC0++0x3 line.long 0x0 "MTL_ECC_CONTROL,The MTL_ECC_Control register establishes the operating mode of ECC related to MTL memories." hexmask.long.tbyte 0x0 9.--31. 1. "RESERVED_31_9,Reserved." newline bitfld.long 0x0 8. "MEEAO,MTL ECC Error Address Status Over-ride When set the following error address fields will hold the last valid address where the error is detected. When reset the following error address fields will hold the first address where the error is.." "MTL ECC Error Address Status Over-ride is disabled,MTL ECC Error Address Status Over-ride is enabled" newline rbitfld.long 0x0 5.--7. "RESERVED_7_5,Reserved." "0,1,2,3,4,5,6,7" newline rbitfld.long 0x0 4. "RESERVED_TSOEE,Reserved." "0,1" newline bitfld.long 0x0 3. "MRXPEE,MTL Rx Parser ECC Enable When set to 1 enables the ECC feature for Rx Parser memory. When set to zero disables the ECC feature for Rx Parser memory. 0x0: MTL Rx Parser ECC is disabled 0x1: MTL Rx Parser ECC is enabled" "MTL Rx Parser ECC is disabled,MTL Rx Parser ECC is enabled" newline bitfld.long 0x0 2. "MESTEE,MTL EST ECC Enable When set to 1 enables the ECC feature for EST memory. When set to zero disables the ECC feature for EST memory. 0x0: MTL EST ECC is disabled 0x1: MTL EST ECC is enabled" "MTL EST ECC is disabled,MTL EST ECC is enabled" newline bitfld.long 0x0 1. "MRXEE,MTL Rx FIFO ECC Enable When set to 1 enables the ECC feature for MTL Rx FIFO memory. When set to zero disables the ECC feature for MTL Rx FIFO memory. 0x0: MTL Rx FIFO ECC is disabled 0x1: MTL Rx FIFO ECC is enabled" "MTL Rx FIFO ECC is disabled,MTL Rx FIFO ECC is enabled" newline bitfld.long 0x0 0. "MTXEE,MTL Tx FIFO ECC Enable When set to 1 enables the ECC feature for MTL Tx FIFO memory. When set to zero disables the ECC feature for MTL Tx FIFO memory. 0x0: MTL Tx FIFO ECC is disabled 0x1: MTL Tx FIFO ECC is enabled" "MTL Tx FIFO ECC is disabled,MTL Tx FIFO ECC is enabled" rgroup.long 0xC4++0x3 line.long 0x0 "MTL_SAFETY_INTERRUPT_STATUS,The MTL_Safety_Interrupt_Status registers provides Safety interrupt status." bitfld.long 0x0 31. "MCSIS,MAC Safety Uncorrectable Interrupt Status Indicates an uncorrectable Safety-related Interrupt is set in the MAC module. MAC_DPP_FSM_Interrupt_Status register should be read when this bit is set to get the cause of the Safety Interrupt in MAC. 0x1:.." "MAC Safety Uncorrectable Interrupt Status not..,MAC Safety Uncorrectable Interrupt Status detected" newline hexmask.long 0x0 2.--30. 1. "RESERVED_30_2,Reserved." newline bitfld.long 0x0 1. "MEUIS,MTL ECC Uncorrectable error Interrupt Status This bit indicates that an uncorrectable error interrupt event in the MTL ECC safety feature. To get the exact cause of the interrupt the application should read the MTL_ECC_Interrupt_Status register." "MTL ECC Uncorrectable error Interrupt Status not..,MTL ECC Uncorrectable error Interrupt Status.." newline bitfld.long 0x0 0. "MECIS,MTL ECC Correctable error Interrupt Status This bit indicates that a correctable error interrupt event in the MTL ECC safety feature. To get the exact cause of the interrupt the application should read the MTL_ECC_Interrupt_Status register. 0x1:.." "MTL ECC Correctable error Interrupt Status not..,MTL ECC Correctable error Interrupt Status.." group.long 0xC8++0xB line.long 0x0 "MTL_ECC_INTERRUPT_ENABLE,The MTL_ECC_Interrupt_Enable register provides enable bits for the ECC interrupts." hexmask.long.tbyte 0x0 13.--31. 1. "RESERVED_31_13,Reserved." newline bitfld.long 0x0 12. "RPCEIE,Rx Parser memory Correctable Error Interrupt Enable When set generates an interrupt when an uncorrectable error is detected at the Rx Parser memory interface. It is indicated in RPCES status bit of MTL_ECC_Interrupt_Status register. When reset.." "Rx Parser memory Correctable Error Interrupt is..,Rx Parser memory Correctable Error Interrupt is.." newline rbitfld.long 0x0 9.--11. "RESERVED_11_9,Reserved." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 8. "ECEIE,EST memory Correctable Error Interrupt Enable When set generates an interrupt when a correctable error is detected at the MTL EST memory interface. It is indicated in the ECES bit of MTL_ECC_Interrupt_Status register. When reset this event does.." "EST memory Correctable Error Interrupt is disabled,EST memory Correctable Error Interrupt is enabled" newline rbitfld.long 0x0 5.--7. "RESERVED_7_5,Reserved." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 4. "RXCEIE,Rx memory Correctable Error Interrupt Enable When set generates an interrupt when a correctable error is detected at the MTL Rx memory interface. It is indicated in the RXCES bit of MTL_ECC_Interrupt_Status register. When reset this event does.." "Rx memory Correctable Error Interrupt is disabled,Rx memory Correctable Error Interrupt is enabled" newline rbitfld.long 0x0 1.--3. "RESERVED_3_1,Reserved." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 0. "TXCEIE,Tx memory Correctable Error Interrupt Enable When set generates an interrupt when a correctable error is detected at the MTL Tx memory interface. It is indicated in the TXCES bit of MTL_ECC_Interrupt_Status register. When reset this event does.." "Tx memory Correctable Error Interrupt is disabled,Tx memory Correctable Error Interrupt is enabled" line.long 0x4 "MTL_ECC_INTERRUPT_STATUS,The MTL_ECC_Interrupt_Status register provides MTL ECC Interrupt Status." hexmask.long.tbyte 0x4 15.--31. 1. "RESERVED_31_15,Reserved." newline bitfld.long 0x4 14. "RPUES,Rx Parser memory Uncorrectable Error Status When set indicates that an uncorrectable error is detected at Rx Parser memory interface. 0x1: Rx Parser memory Uncorrectable Error Status detected 0x0: Rx Parser memory Uncorrectable Error Status not.." "Rx Parser memory Uncorrectable Error Status not..,Rx Parser memory Uncorrectable Error Status.." newline bitfld.long 0x4 13. "RPAMS,MTL Rx Parser memory Address Mismatch Status This bit when set indicates that address mismatch is found for address bus of Rx Parser memory. 0x1: MTL Rx Parser memory Address Mismatch Status detected 0x0: MTL Rx Parser memory Address Mismatch.." "MTL Rx Parser memory Address Mismatch Status not..,MTL Rx Parser memory Address Mismatch Status.." newline bitfld.long 0x4 12. "RPCES,MTL Rx Parser memory Correctable Error Status This bit when set indicates that correctable error is detected at RX Parser memory interface. 0x1: MTL Rx Parser memory Correctable Error Status detected 0x0: MTL Rx Parser memory Correctable Error.." "MTL Rx Parser memory Correctable Error Status..,MTL Rx Parser memory Correctable Error Status.." newline rbitfld.long 0x4 11. "RESERVED_11,Reserved." "0,1" newline bitfld.long 0x4 10. "EUES,MTL EST memory Uncorrectable Error Status When set indicates that an uncorrectable error is detected at MTL EST memory interface. 0x1: MTL EST memory Uncorrectable Error Status detected 0x0: MTL EST memory Uncorrectable Error Status not detected" "MTL EST memory Uncorrectable Error Status not..,MTL EST memory Uncorrectable Error Status detected" newline bitfld.long 0x4 9. "EAMS,MTL EST memory Address Mismatch Status This bit when set indicates that address mismatch is found for address bus of MTL EST memory. 0x1: MTL EST memory Address Mismatch Status detected 0x0: MTL EST memory Address Mismatch Status not detected" "MTL EST memory Address Mismatch Status not..,MTL EST memory Address Mismatch Status detected" newline bitfld.long 0x4 8. "ECES,MTL EST memory Correctable Error Status This bit when set indicates that correctable error is detected at the MTL EST memory. 0x1: MTL EST memory Correctable Error Status detected 0x0: MTL EST memory Correctable Error Status not detected" "MTL EST memory Correctable Error Status not..,MTL EST memory Correctable Error Status detected" newline rbitfld.long 0x4 7. "RESERVED_7,Reserved." "0,1" newline bitfld.long 0x4 6. "RXUES,MTL Rx memory Uncorrectable Error Status When set indicates that an uncorrectable error is detected at the MTL Rx memory interface. 0x1: MTL Rx memory Uncorrectable Error Status detected 0x0: MTL Rx memory Uncorrectable Error Status not detected" "MTL Rx memory Uncorrectable Error Status not..,MTL Rx memory Uncorrectable Error Status detected" newline bitfld.long 0x4 5. "RXAMS,MTL Rx memory Address Mismatch Status This bit when set indicates that address mismatch is found for address bus of the MTL Rx memory. 0x1: MTL Rx memory Address Mismatch Status detected 0x0: MTL Rx memory Address Mismatch Status not detected" "MTL Rx memory Address Mismatch Status not detected,MTL Rx memory Address Mismatch Status detected" newline bitfld.long 0x4 4. "RXCES,MTL Rx memory Correctable Error Status This bit when set indicates that correctable error is detected at the MTL Rx memory. 0x1: MTL Rx memory correctable Error Status detected 0x0: MTL Rx memory correctable Error Status not detected" "MTL Rx memory correctable Error Status not..,MTL Rx memory correctable Error Status detected" newline rbitfld.long 0x4 3. "RESERVED_3,Reserved." "0,1" newline bitfld.long 0x4 2. "TXUES,MTL Tx memory Uncorrectable Error Status When set indicates that an uncorrectable error is detected at the MTL TX memory interface. 0x1: MTL Tx memory Uncorrectable Error Status detected 0x0: MTL Tx memory Uncorrectable Error Status not detected" "MTL Tx memory Uncorrectable Error Status not..,MTL Tx memory Uncorrectable Error Status detected" newline bitfld.long 0x4 1. "TXAMS,MTL Tx memory Address Mismatch Status This bit when set indicates that address mismatch is found for address bus of the MTL Tx memory. 0x1: MTL Tx memory Address Mismatch Status detected 0x0: MTL Tx memory Address Mismatch Status not detected" "MTL Tx memory Address Mismatch Status not detected,MTL Tx memory Address Mismatch Status detected" newline bitfld.long 0x4 0. "TXCES,MTL Tx memory Correctable Error Status This bit when set indicates that a correctable error is detected at the MTL Tx memory. 0x1: MTL Tx memory Correctable Error Status detected 0x0: MTL Tx memory Correctable Error Status not detected" "MTL Tx memory Correctable Error Status not..,MTL Tx memory Correctable Error Status detected" line.long 0x8 "MTL_ECC_ERR_STS_RCTL,The MTL_ECC_Err_Sts_Rctl register establishes the control for ECC Error status capture." hexmask.long 0x8 6.--31. 1. "RESERVED_31_6,Reserved." newline bitfld.long 0x8 5. "CUES,Clear Uncorrectable Error Status When this bit is set along with EESRE bit of this register based on the EMS field of this register the respective memory's uncorrectable error address and uncorrectable error count values will be cleared upon.." "Clear Uncorrectable Error Status not detected,Clear Uncorrectable Error Status detected" newline bitfld.long 0x8 4. "CCES,Clear Correctable Error Status When this bit is set along with EESRE bit of this register based on the EMS field of this register the respective memory's correctable error address and correctable error count values will be cleared upon reading." "Clear Correctable Error Status not detected,Clear Correctable Error Status detected" newline bitfld.long 0x8 1.--3. "EMS,MTL ECC Memory Selection When EESRE bit of this register is set this field indicates which memory's error status value to be read. The memory selection encoding is as described below. 0x2: MTL EST memory 0x3: MTL Rx Parser memory 0x1: MTL Rx memory.." "MTL Tx memory,MTL Rx memory,MTL EST memory,MTL Rx Parser memory,DMA TSO memory,?,?,?" newline bitfld.long 0x8 0. "EESRE,MTL ECC Error Status Read Enable When this bit is set based on the EMS field of this register the respective memory's error status values will be captured as described below - The correctable and uncorrectable error count values will be captured.." "MTL ECC Error Status Read is disabled,MTL ECC Error Status Read is enabled" rgroup.long 0xD4++0x7 line.long 0x0 "MTL_ECC_ERR_ADDR_STATUS,The MTL_ECC_Err_Addr_Status register provides the memory addresses for the correctable and uncorrectable errors." hexmask.long.word 0x0 16.--31. 1. "EUEAS,MTL ECC Uncorrectable Error Address Status Based on the EMS field of MTL_ECC_Err_Sts_Rctl register this field holds the respective memory's address locations for which an uncorrectable error or address mismatch is detected. When MEEAO bit of.." newline hexmask.long.word 0x0 0.--15. 1. "ECEAS,MTL ECC Correctable Error Address Status Based on the EMS field of MTL_ECC_Err_Sts_Rctl register this field holds the respective memory's address locations for which a correctable error is detected. When MEEAO bit of MTL_ECC_Control register is.." line.long 0x4 "MTL_ECC_ERR_CNTR_STATUS,The MTL_ECC_Err_Cntr_Status register provides ECC Error count for Correctable and uncorrectable errors." hexmask.long.word 0x4 20.--31. 1. "RESERVED_31_20,Reserved." newline hexmask.long.byte 0x4 16.--19. 1. "EUECS,MTL ECC Uncorrectable Error Counter Status Based on the EMS field of MTL_ECC_Err_Cntr_Rctl register this field holds the respective memory's uncorrectable error count value." newline hexmask.long.byte 0x4 8.--15. 1. "RESERVED_15_8,Reserved." newline hexmask.long.byte 0x4 0.--7. 1. "ECECS,MTL ECC Correctable Error Counter Status Based on the EMS field of MTL_ECC_Err_Cntr_Rctl register this field holds the respective memory's correctable error count value." group.long 0xE0++0x3 line.long 0x0 "MTL_DPP_CONTROL,The MTL_DPP_Control establishes the operating mode of Data Parity protection and error injection." hexmask.long.tbyte 0x0 14.--31. 1. "RESERVED_31_14,Reserved." newline bitfld.long 0x0 13. "IPECW,Insert Parity error in CSR Read data parity generator When set to 1 parity bit of first valid data generated by the CSR parity generator (or at PG10 as shown in Fig.AXI slave Interface Data path parity protection) is flipped. Hardware will clear.." "Insert Parity error in CSR Read data parity..,Insert Parity error in CSR Read data parity.." newline rbitfld.long 0x0 12. "RESERVED_IPEASW,Reserved." "0,1" newline bitfld.long 0x0 11. "IPERD,Insert Parity error in Rx write-back Descriptor parity generator When set to 1 parity bit of first valid data generated by the DMA Rx write-back descriptor parity generator(or at PG8 as shown in Fig.Receive data path parity protection) is flipped." "Insert Parity error in Rx write-back Descriptor..,Insert Parity error in Rx write-back Descriptor.." newline bitfld.long 0x0 10. "IPETD,Insert Parity error in Tx write-back Descriptor parity generator When set to 1 parity bit of first valid data generated by the DMA Tx write-back descriptor parity generator(or at PG4 as shown in Fig.Transmit data path parity protection) is.." "Insert Parity error in Tx write-back Descriptor..,Insert Parity error in Tx write-back Descriptor.." newline rbitfld.long 0x0 9. "RESERVED_IPETSO,Reserved." "0,1" newline bitfld.long 0x0 8. "IPEDDC,Insert Parity Error in DMA DTX Control word parity generator When set to 1 parity bit of first valid data generated by the DMA DTX Control word parity generator (or at PG2 as shown in Fig.Transmit data path parity protection) is flipped. Hardware.." "Insert Parity Error in DMA DTX Control word..,Insert Parity Error in DMA DTX Control word.." newline bitfld.long 0x0 7. "IPEMRF,Insert Parity Error in MTL Rx FIFO read control parity generator When set to 1 parity bit of first valid data generated by the MTL Rx FIFO read control parity generator (or at PG7 as shown in Fig.Receive data path parity protection) is flipped." "Insert Parity Error in MTL Rx FIFO read control..,Insert Parity Error in MTL Rx FIFO read control.." newline bitfld.long 0x0 6. "IPEMTS,Insert Parity Error in MTL Tx Status parity generator When set to 1 parity bit of first valid data generated by the MTL Tx Status parity generator (or at PG6 as shown in Fig.Transmit data path parity protection) is flipped. Hardware will clear.." "Insert Parity Error in MTL Tx Status parity..,Insert Parity Error in MTL Tx Status parity.." newline bitfld.long 0x0 5. "IPEMC,Insert Parity Error in MTL checksum parity generator When set to 1 parity bit of first valid data generated by the MTL checksum parity generator (or at PG5 as shown in Fig.Transmit data path parity protection) is flipped. Hardware will clear this.." "Insert Parity Error in MTL checksum parity..,Insert Parity Error in MTL checksum parity.." newline rbitfld.long 0x0 4. "RESERVED_IPEID,Reserved." "0,1" newline rbitfld.long 0x0 3. "RESERVED_3,Reserved." "0,1" newline bitfld.long 0x0 2. "EPSI,Enable Parity on Slave Interface port When set to 1 enables the parity check for the slave interface ports and disables the internal generation of parity for the input slave data port. When set to 0 disables the parity check for the slave.." "Parity on Slave Interface port is disabled,Parity on Slave Interface port is enabled" newline bitfld.long 0x0 1. "OPE,Odd Parity Enable When set to 1 enables odd parity protection on all the external interfaces and when set to 0 enables even parity protection on all the external interfaces. 0x0: Odd Parity is disabled 0x1: Odd Parity is enabled" "Odd Parity is disabled,Odd Parity is enabled" newline bitfld.long 0x0 0. "EDPP,Enable Data path Parity Protection When set to 1 enables the parity protection for EQOS datapath by generating and checking the parity on EQOS datapath. When set to 0 disables the parity protection for EQOS datapath. 0x0: Data path Parity.." "Data path Parity Protection is disabled,Data path Parity Protection is enabled" tree.end tree "EQOS_MTL_Q0" group.long 0x0++0x3 line.long 0x0 "MTL_TXQ0_OPERATION_MODE,The Queue 0 Transmit Operation Mode register establishes the Transmit queue operating modes and commands." hexmask.long.word 0x0 21.--31. 1. "RESERVED_31_Y,Reserved." newline hexmask.long.byte 0x0 16.--20. 1. "TQS,Transmit Queue Size This field indicates the size of the allocated Transmit queues in blocks of 256 bytes. The TQS field is read-write only if the number of Tx Queues more than one the reset value is 0x0 and indicates size of 256 bytes. When the.." newline hexmask.long.word 0x0 7.--15. 1. "RESERVED_15_7,Reserved." newline bitfld.long 0x0 4.--6. "TTC,Transmit Threshold Control These bits control the threshold level of the MTL Tx Queue. The transmission starts when the packet size within the MTL Tx Queue is larger than the threshold. In addition full packets with length less than the threshold.." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 2.--3. "TXQEN,Transmit Queue Enable This field is used to enable/disable the transmit queue 0. - 2'b00: Not enabled - 2'b01: Reserved - 2'b10: Enabled - 2'b11: Reserved This field is Read Only in Single Queue configurations and Read Write in Multiple Queue.." "Not enabled,Enable in AV mode,Enabled,Reserved" newline bitfld.long 0x0 1. "TSF,Transmit Store and Forward When this bit is set the transmission starts when a full packet resides in the MTL Tx queue. When this bit is set the TTC values specified in Bits[6:4] of this register are ignored. This bit should be changed only when.." "Transmit Store and Forward is disabled,Transmit Store and Forward is enabled" newline bitfld.long 0x0 0. "FTQ,Flush Transmit Queue When this bit is set the Tx queue controller logic is reset to its default values. Therefore all the data in the Tx queue is lost or flushed. This bit is internally reset when the flushing operation is complete. Until this bit.." "Flush Transmit Queue is disabled,Flush Transmit Queue is enabled" rgroup.long 0x4++0x7 line.long 0x0 "MTL_TXQ0_UNDERFLOW,The Queue 0 Underflow Counter register contains the counter for packets aborted because of Transmit queue underflow and packets missed because of Receive queue packet flush" hexmask.long.tbyte 0x0 12.--31. 1. "RESERVED_31_12,Reserved." newline bitfld.long 0x0 11. "UFCNTOVF,Overflow Bit for Underflow Packet Counter This bit is set every time the Tx queue Underflow Packet Counter field overflows that is it has crossed the maximum count. In such a scenario the overflow packet counter is reset to all-zeros and this.." "Overflow not detected for Underflow Packet Counter,Overflow detected for Underflow Packet Counter" newline hexmask.long.word 0x0 0.--10. 1. "UFFRMCNT,Underflow Packet Counter This field indicates the number of packets aborted by the controller because of Tx Queue Underflow. This counter is incremented each time the MAC aborts outgoing packet because of underflow. The counter is cleared when.." line.long 0x4 "MTL_TXQ0_DEBUG,The Queue 0 Transmit Debug register gives the debug status of various blocks related to the Transmit queue." hexmask.long.word 0x4 23.--31. 1. "RESERVED_31_23,Reserved." newline bitfld.long 0x4 20.--22. "STXSTSF,Number of Status Words in Tx Status FIFO of Queue This field indicates the current number of status in the Tx Status FIFO of this queue. When the DTXSTS bit of MTL_Operation_Mode register is set to 1 this field does not reflect the number of.." "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 19. "RESERVED_19,Reserved." "0,1" newline bitfld.long 0x4 16.--18. "PTXQ,Number of Packets in the Transmit Queue This field indicates the current number of packets in the Tx Queue. When the DTXSTS bit of MTL_Operation_Mode register is set to 1 this field does not reflect the number of packets in the Transmit queue." "0,1,2,3,4,5,6,7" newline hexmask.long.word 0x4 6.--15. 1. "RESERVED_15_6,Reserved." newline bitfld.long 0x4 5. "TXSTSFSTS,MTL Tx Status FIFO Full Status When high this bit indicates that the MTL Tx Status FIFO is full. Therefore the MTL cannot accept any more packets for transmission. 0x1: MTL Tx Status FIFO Full status is detected 0x0: MTL Tx Status FIFO Full.." "MTL Tx Status FIFO Full status is not detected,MTL Tx Status FIFO Full status is detected" newline bitfld.long 0x4 4. "TXQSTS,MTL Tx Queue Not Empty Status When this bit is high it indicates that the MTL Tx Queue is not empty and some data is left for transmission. 0x1: MTL Tx Queue Not Empty status is detected 0x0: MTL Tx Queue Not Empty status is not detected" "MTL Tx Queue Not Empty status is not detected,MTL Tx Queue Not Empty status is detected" newline bitfld.long 0x4 3. "TWCSTS,MTL Tx Queue Write Controller Status When high this bit indicates that the MTL Tx Queue Write Controller is active and it is transferring the data to the Tx Queue. 0x1: MTL Tx Queue Write Controller status is detected 0x0: MTL Tx Queue Write.." "MTL Tx Queue Write Controller status is not..,MTL Tx Queue Write Controller status is detected" newline bitfld.long 0x4 1.--2. "TRCSTS,MTL Tx Queue Read Controller Status This field indicates the state of the Tx Queue Read Controller: 0x3: Flushing the Tx queue because of the Packet Abort request from the MAC 0x0: Idle state 0x1: Read state (transferring data to the MAC.." "Idle state,Read state,Waiting for pending Tx Status from the MAC..,Flushing the Tx queue because of the Packet.." newline bitfld.long 0x4 0. "TXQPAUSED,Transmit Queue in Pause When this bit is high and the Rx flow control is enabled it indicates that the Tx Queue is in the Pause condition (in the full-duplex only mode) because of the following: - Reception of the PFC packet for the priorities.." "Transmit Queue in Pause status is not detected,Transmit Queue in Pause status is detected" rgroup.long 0x14++0x3 line.long 0x0 "MTL_TXQ0_ETS_STATUS,The Queue 0 ETS Status register provides the average traffic transmitted in Queue 0." hexmask.long.byte 0x0 24.--31. 1. "RESERVED_31_24,Reserved." newline hexmask.long.tbyte 0x0 0.--23. 1. "ABS,Average Bits per Slot This field contains the average transmitted bits per slot. When the DCB operation is enabled for Queue 0 this field is computed over every 10 million bit times slot (4 ms in 2500 Mbps; 10 ms in 1000 Mbps; 100 ms in 100 Mbps)." group.long 0x18++0x3 line.long 0x0 "MTL_TXQ0_QUANTUM_WEIGHT,The Queue 0 Quantum or Weights register contains the quantum value for Deficit Weighted Round Robin (DWRR). weights for the Weighted Round Robin (WRR). and Weighted Fair Queuing (WFQ) for Queue 0." hexmask.long.word 0x0 21.--31. 1. "RESERVED_31_21,Reserved." newline hexmask.long.tbyte 0x0 0.--20. 1. "ISCQW,Quantum or Weights When the DCB operation is enabled with DWRR algorithm for Queue 0 traffic this field contains the quantum value in bytes to be added to credit during every queue scanning cycle. The maximum value is 0x1312D0 bytes. When DCB.." group.long 0x2C++0x7 line.long 0x0 "MTL_Q0_INTERRUPT_CONTROL_STATUS,This register contains the interrupt enable and status bits for the queue 0 interrupts." hexmask.long.byte 0x0 25.--31. 1. "RESERVED_31_25,Reserved." newline bitfld.long 0x0 24. "RXOIE,Receive Queue Overflow Interrupt Enable When this bit is set the Receive Queue Overflow interrupt is enabled. When this bit is reset the Receive Queue Overflow interrupt is disabled. 0x0: Receive Queue Overflow Interrupt is disabled 0x1: Receive.." "Receive Queue Overflow Interrupt is disabled,Receive Queue Overflow Interrupt is enabled" newline hexmask.long.byte 0x0 17.--23. 1. "RESERVED_23_17,Reserved." newline bitfld.long 0x0 16. "RXOVFIS,Receive Queue Overflow Interrupt Status This bit indicates that the Receive Queue had an overflow while receiving the packet. If a partial packet is transferred to the application the overflow status is set in RDES3[21]. This bit is cleared when.." "Receive Queue Overflow Interrupt Status not..,Receive Queue Overflow Interrupt Status detected" newline hexmask.long.byte 0x0 10.--15. 1. "RESERVED_15_10,Reserved." newline bitfld.long 0x0 9. "ABPSIE,Average Bits Per Slot Interrupt Enable When this bit is set the MAC asserts the sbd_intr_o or mci_intr_o interrupt when the average bits per slot status is updated. When this bit is cleared the interrupt is not asserted for such an event. 0x0:.." "Average Bits Per Slot Interrupt is disabled,Average Bits Per Slot Interrupt is enabled" newline bitfld.long 0x0 8. "TXUIE,Transmit Queue Underflow Interrupt Enable When this bit is set the Transmit Queue Underflow interrupt is enabled. When this bit is reset the Transmit Queue Underflow interrupt is disabled. 0x0: Transmit Queue Underflow Interrupt Status is.." "Transmit Queue Underflow Interrupt Status is..,Transmit Queue Underflow Interrupt Status is.." newline hexmask.long.byte 0x0 2.--7. 1. "RESERVED_7_2,Reserved." newline bitfld.long 0x0 1. "ABPSIS,Average Bits Per Slot Interrupt Status When set this bit indicates that the MAC has updated the ABS value. This bit is cleared when the application writes 1 to this bit. Access restriction applies. Self-set to 1 on internal event. Setting 1.." "Average Bits Per Slot Interrupt Status not..,Average Bits Per Slot Interrupt Status detected" newline bitfld.long 0x0 0. "TXUNFIS,Transmit Queue Underflow Interrupt Status This bit indicates that the Transmit Queue had an underflow while transmitting the packet. Transmission is suspended and an Underflow Error TDES3[2] is set. This bit is cleared when the application writes.." "Transmit Queue Underflow Interrupt Status not..,Transmit Queue Underflow Interrupt Status detected" line.long 0x4 "MTL_RXQ0_OPERATION_MODE,The Queue 0 Receive Operation Mode register establishes the Receive queue operating modes and command. The RFA and RFD fields are not backward compatible with the RFA and RFD fields of 4.00a release" hexmask.long.byte 0x4 25.--31. 1. "RESERVED_31_Y,Reserved." newline hexmask.long.byte 0x4 20.--24. 1. "RQS,Receive Queue Size This field indicates the size of the allocated Receive queues in blocks of 256 bytes. The RQS field is read-write only if the number of Rx Queues more than one the reset value is 0x0 and indicates size of 256 bytes. When the.." newline rbitfld.long 0x4 18.--19. "RESERVED_19_Y,Reserved." "0,1,2,3" newline hexmask.long.byte 0x4 14.--17. 1. "RFD,Threshold for Deactivating Flow Control (in half-duplex and full-duplex modes) These bits control the threshold (fill-level of Rx queue) at which the flow control is de-asserted after activation: - 0: Full minus 1 KB that is FULL 1 KB - 1: Full.." newline rbitfld.long 0x4 12.--13. "RESERVED_13_Y,Reserved." "0,1,2,3" newline hexmask.long.byte 0x4 8.--11. 1. "RFA,Threshold for Activating Flow Control (in half-duplex and full-duplex These bits control the threshold (fill-level of Rx queue) at which the flow control is activated: For more information on encoding for this field see RFD." newline bitfld.long 0x4 7. "EHFC,Enable Hardware Flow Control When this bit is set the flow control signal operation based on the fill-level of Rx queue is enabled. When reset the flow control operation is disabled. 0x0: Hardware Flow Control is disabled 0x1: Hardware Flow.." "Hardware Flow Control is disabled,Hardware Flow Control is enabled" newline bitfld.long 0x4 6. "DIS_TCP_EF,Disable Dropping of TCP/IP Checksum Error Packets When this bit is set the MAC does not drop the packets which only have the errors detected by the Receive Checksum Offload engine. Such packets have errors only in the encapsulated payload." "Dropping of TCP/IP Checksum Error Packets is..,Dropping of TCP/IP Checksum Error Packets is.." newline bitfld.long 0x4 5. "RSF,Receive Queue Store and Forward When this bit is set the DWC_ether_qos reads a packet from the Rx queue only after the complete packet has been written to it ignoring the RTC field of this register. When this bit is reset the Rx queue operates in.." "Receive Queue Store and Forward is disabled,Receive Queue Store and Forward is enabled" newline bitfld.long 0x4 4. "FEP,Forward Error Packets When this bit is reset the Rx queue drops packets with error status (CRC error GMII_ER watchdog timeout or overflow). However if the start byte (write) pointer of a packet is already transferred to the read controller side.." "Forward Error Packets is disabled,Forward Error Packets is enabled" newline bitfld.long 0x4 3. "FUP,Forward Undersized Good Packets When this bit is set the Rx queue forwards the undersized good packets (packets with no error and length less than 64 bytes) including pad-bytes and CRC. When this bit is reset the Rx queue drops all packets of less.." "Forward Undersized Good Packets is disabled,Forward Undersized Good Packets is enabled" newline rbitfld.long 0x4 2. "RESERVED_2,Reserved." "0,1" newline bitfld.long 0x4 0.--1. "RTC,Receive Queue Threshold Control These bits control the threshold level of the MTL Rx queue (in bytes): The received packet is transferred to the application or DMA when the packet size within the MTL Rx queue is larger than the threshold. In addition.." "0,1,2,3" rgroup.long 0x34++0x7 line.long 0x0 "MTL_RXQ0_MISSED_PACKET_OVERFLOW_CNT,The Queue 0 Missed Packet and Overflow Counter register contains the counter for packets missed because of Receive queue packet flush and packets discarded because of Receive queue overflow." hexmask.long.byte 0x0 28.--31. 1. "RESERVED_31_28,Reserved." newline bitfld.long 0x0 27. "MISCNTOVF,Missed Packet Counter Overflow Bit When set this bit indicates that the Rx Queue Missed Packet Counter crossed the maximum limit. Access restriction applies. Clears on read. Self-set to 1 on internal event. 0x1: Missed Packet Counter overflow.." "Missed Packet Counter overflow not detected,Missed Packet Counter overflow detected" newline hexmask.long.word 0x0 16.--26. 1. "MISPKTCNT,Missed Packet Counter This field indicates the number of packets missed by the DWC_ether_qos because the application asserted ari_pkt_flush_i[] for this queue. This counter is reset when this register is read with mci_be_i[0] at 1b1. This.." newline hexmask.long.byte 0x0 12.--15. 1. "RESERVED_15_12,Reserved." newline bitfld.long 0x0 11. "OVFCNTOVF,Overflow Counter Overflow Bit When set this bit indicates that the Rx Queue Overflow Packet Counter field crossed the maximum limit. Access restriction applies. Clears on read. Self-set to 1 on internal event. 0x1: Overflow Counter overflow.." "Overflow Counter overflow not detected,Overflow Counter overflow detected" newline hexmask.long.word 0x0 0.--10. 1. "OVFPKTCNT,Overflow Packet Counter This field indicates the number of packets discarded by the DWC_ether_qos because of Receive queue overflow. This counter is incremented each time the DWC_ether_qos discards an incoming packet because of overflow. This.." line.long 0x4 "MTL_RXQ0_DEBUG,The Queue 0 Receive Debug register gives the debug status of various blocks related to the Receive queue." bitfld.long 0x4 30.--31. "RESERVED_31_30,Reserved." "0,1,2,3" newline hexmask.long.word 0x4 16.--29. 1. "PRXQ,Number of Packets in Receive Queue This field indicates the current number of packets in the Rx Queue. The theoretical maximum value for this field is 256KB/16B = 16K Packets that is Max_Queue_Size/Min_Packet_Size." newline hexmask.long.word 0x4 6.--15. 1. "RESERVED_15_6,Reserved." newline bitfld.long 0x4 4.--5. "RXQSTS,MTL Rx Queue Fill-Level Status This field gives the status of the fill-level of the Rx Queue: 0x2: Rx Queue fill-level above flow-control activate threshold 0x1: Rx Queue fill-level below flow-control deactivate threshold 0x0: Rx Queue empty 0x3:.." "Rx Queue empty,Rx Queue fill-level below flow-control..,Rx Queue fill-level above flow-control activate..,Rx Queue full" newline bitfld.long 0x4 3. "RESERVED_3,Reserved." "0,1" newline bitfld.long 0x4 1.--2. "RRCSTS,MTL Rx Queue Read Controller State This field gives the state of the Rx queue Read controller: 0x3: Flushing the packet data and status 0x0: Idle state 0x1: Reading packet data 0x2: Reading packet status (or timestamp)" "Idle state,Reading packet data,Reading packet status,Flushing the packet data and status" newline bitfld.long 0x4 0. "RWCSTS,MTL Rx Queue Write Controller Active Status When high this bit indicates that the MTL Rx queue Write controller is active and it is transferring a received packet to the Rx Queue. 0x1: MTL Rx Queue Write Controller Active Status detected 0x0:.." "MTL Rx Queue Write Controller Active Status not..,MTL Rx Queue Write Controller Active Status.." group.long 0x3C++0x3 line.long 0x0 "MTL_RXQ0_CONTROL,The Queue Receive Control register controls the receive arbitration and passing of received packets to the application." hexmask.long 0x0 4.--31. 1. "RESERVED_31_4,Reserved." newline bitfld.long 0x0 3. "RXQ_FRM_ARBIT,Receive Queue Packet Arbitration When this bit is set the DWC_ether_qos drives the packet data to the ARI interface such that the entire packet data of currently-selected queue is transmitted before switching to other queue. When this bit.." "Receive Queue Packet Arbitration is disabled,Receive Queue Packet Arbitration is enabled" newline bitfld.long 0x0 0.--2. "RXQ_WEGT,Receive Queue Weight This field indicates the weight assigned to the Rx Queue 0. The weight is used as the number of continuous PBL or packets requests (depending on the RXQ_FRM_ARBIT) allocated to the queue in one arbitration cycle." "0,1,2,3,4,5,6,7" tree.end tree "EQOS_MTL_Q1" group.long 0x0++0x3 line.long 0x0 "MTL_TXQ1_OPERATION_MODE,The Queue 1 Transmit Operation Mode register establishes the Transmit queue operating modes and commands." hexmask.long.word 0x0 21.--31. 1. "RESERVED_31_Y,Reserved." newline hexmask.long.byte 0x0 16.--20. 1. "TQS,Transmit Queue Size This field indicates the size of the allocated Transmit queues in blocks of 256 bytes. The TQS field is read-write only if the number of Tx Queues more than one the reset value is 0x0 and indicates size of 256 bytes. When the.." newline hexmask.long.word 0x0 7.--15. 1. "RESERVED_15_7,Reserved." newline bitfld.long 0x0 4.--6. "TTC,Transmit Threshold Control These bits control the threshold level of the MTL Tx Queue. The transmission starts when the packet size within the MTL Tx Queue is larger than the threshold. In addition full packets with length less than the threshold.." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 2.--3. "TXQEN,Transmit Queue Enable This field is used to enable/disable the transmit queue 0. - 2'b00: Not enabled - 2'b01: Enable in AV mode - 2'b10: Enabled - 2'b11: Reserved Note: In multiple Tx queues configuration all the queues are disabled by default." "Not enabled,Enable in AV mode,Enabled,Reserved" newline bitfld.long 0x0 1. "TSF,Transmit Store and Forward When this bit is set the transmission starts when a full packet resides in the MTL Tx queue. When this bit is set the TTC values specified in Bits[6:4] of this register are ignored. This bit should be changed only when.." "Transmit Store and Forward is disabled,Transmit Store and Forward is enabled" newline bitfld.long 0x0 0. "FTQ,Flush Transmit Queue When this bit is set the Tx queue controller logic is reset to its default values. Therefore all the data in the Tx queue is lost or flushed. This bit is internally reset when the flushing operation is complete. Until this bit.." "Flush Transmit Queue is disabled,Flush Transmit Queue is enabled" rgroup.long 0x4++0x7 line.long 0x0 "MTL_TXQ1_UNDERFLOW,The Queue 1 Underflow Counter register contains the counter for packets aborted because of Transmit queue underflow and packets missed because of Receive queue packet flush" hexmask.long.tbyte 0x0 12.--31. 1. "RESERVED_31_12,Reserved." newline bitfld.long 0x0 11. "UFCNTOVF,Overflow Bit for Underflow Packet Counter This bit is set every time the Tx queue Underflow Packet Counter field overflows that is it has crossed the maximum count. In such a scenario the overflow packet counter is reset to all-zeros and this.." "Overflow not detected for Underflow Packet Counter,Overflow detected for Underflow Packet Counter" newline hexmask.long.word 0x0 0.--10. 1. "UFFRMCNT,Underflow Packet Counter This field indicates the number of packets aborted by the controller because of Tx Queue Underflow. This counter is incremented each time the MAC aborts outgoing packet because of underflow. The counter is cleared when.." line.long 0x4 "MTL_TXQ1_DEBUG,The Queue 1 Transmit Debug register gives the debug status of various blocks related to the Transmit queue." hexmask.long.word 0x4 23.--31. 1. "RESERVED_31_23,Reserved." newline bitfld.long 0x4 20.--22. "STXSTSF,Number of Status Words in Tx Status FIFO of Queue This field indicates the current number of status in the Tx Status FIFO of this queue. When the DTXSTS bit of MTL_Operation_Mode register is set to 1 this field does not reflect the number of.." "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 19. "RESERVED_19,Reserved." "0,1" newline bitfld.long 0x4 16.--18. "PTXQ,Number of Packets in the Transmit Queue This field indicates the current number of packets in the Tx Queue. When the DTXSTS bit of MTL_Operation_Mode register is set to 1 this field does not reflect the number of packets in the Transmit queue." "0,1,2,3,4,5,6,7" newline hexmask.long.word 0x4 6.--15. 1. "RESERVED_15_6,Reserved." newline bitfld.long 0x4 5. "TXSTSFSTS,MTL Tx Status FIFO Full Status When high this bit indicates that the MTL Tx Status FIFO is full. Therefore the MTL cannot accept any more packets for transmission. 0x1: MTL Tx Status FIFO Full status is detected 0x0: MTL Tx Status FIFO Full.." "MTL Tx Status FIFO Full status is not detected,MTL Tx Status FIFO Full status is detected" newline bitfld.long 0x4 4. "TXQSTS,MTL Tx Queue Not Empty Status When this bit is high it indicates that the MTL Tx Queue is not empty and some data is left for transmission. 0x1: MTL Tx Queue Not Empty status is detected 0x0: MTL Tx Queue Not Empty status is not detected" "MTL Tx Queue Not Empty status is not detected,MTL Tx Queue Not Empty status is detected" newline bitfld.long 0x4 3. "TWCSTS,MTL Tx Queue Write Controller Status When high this bit indicates that the MTL Tx Queue Write Controller is active and it is transferring the data to the Tx Queue. 0x1: MTL Tx Queue Write Controller status is detected 0x0: MTL Tx Queue Write.." "MTL Tx Queue Write Controller status is not..,MTL Tx Queue Write Controller status is detected" newline bitfld.long 0x4 1.--2. "TRCSTS,MTL Tx Queue Read Controller Status This field indicates the state of the Tx Queue Read Controller: 0x3: Flushing the Tx queue because of the Packet Abort request from the MAC 0x0: Idle state 0x1: Read state (transferring data to the MAC.." "Idle state,Read state,Waiting for pending Tx Status from the MAC..,Flushing the Tx queue because of the Packet.." newline bitfld.long 0x4 0. "TXQPAUSED,Transmit Queue in Pause When this bit is high and the Rx flow control is enabled it indicates that the Tx Queue is in the Pause condition (in the full-duplex only mode) because of the following: - Reception of the PFC packet for the priorities.." "Transmit Queue in Pause status is not detected,Transmit Queue in Pause status is detected" group.long 0x10++0x3 line.long 0x0 "MTL_TXQ1_ETS_CONTROL,The Queue ETS Control register controls the enhanced transmission selection operation." hexmask.long 0x0 7.--31. 1. "RESERVED_31_7,Reserved." newline bitfld.long 0x0 4.--6. "SLC,Slot Count If the credit-based shaper algorithm is enabled the software can program the number of slots (of duration programmed in DMA_CH[n]_Slot_Interval register) over which the average transmitted bits per slot provided in the.." "?,?,?,?,?,Reserved,?,?" newline bitfld.long 0x0 3. "CC,Credit Control When this bit is set the accumulated credit parameter in the credit-based shaper algorithm logic is not reset to zero when there is positive credit and no packet to transmit in Channel 1. The credit accumulates even when there is no.." "Credit Control is disabled,Credit Control is enabled" newline bitfld.long 0x0 2. "AVALG,AV Algorithm When Queue 1 is programmed for AV this field configures the scheduling algorithm for this queue: This bit when set indicates credit based shaper algorithm (CBS) is selected for Queue 1 traffic. When reset strict priority is.." "CBS Algorithm is disabled,CBS Algorithm is enabled" newline rbitfld.long 0x0 0.--1. "RESERVED_1_0,Reserved." "0,1,2,3" rgroup.long 0x14++0x3 line.long 0x0 "MTL_TXQ1_ETS_STATUS,The Queue 1 ETS Status register provides the average traffic transmitted in Queue 1." hexmask.long.byte 0x0 24.--31. 1. "RESERVED_31_24,Reserved." newline hexmask.long.tbyte 0x0 0.--23. 1. "ABS,Average Bits per Slot This field contains the average transmitted bits per slot. If AV operation is enabled this field is computed over number of slots programmed in the SLC field of MTL_TxQ[n]_ETS_CONTROL register. The maximum value of this field.." group.long 0x18++0xF line.long 0x0 "MTL_TXQ1_QUANTUM_WEIGHT,The Queue 1 idleSlopeCredit. Quantum or Weights register provides the average traffic transmitted in Queue 1." hexmask.long.word 0x0 21.--31. 1. "RESERVED_31_21,Reserved." newline hexmask.long.tbyte 0x0 0.--20. 1. "ISCQW,idleSlopeCredit Quantum or Weights - idleSlopeCredit When AV feature is enabled this field contains the idleSlopeCredit value required for the credit-based shaper algorithm for Queue 1. This is the rate of change of credit in bits per cycle (40.." line.long 0x4 "MTL_TXQ1_SENDSLOPECREDIT,The sendSlopeCredit register contains the sendSlope credit value required for the credit-based shaper algorithm for the Queue." hexmask.long.tbyte 0x4 14.--31. 1. "RESERVED_31_14,Reserved." newline hexmask.long.word 0x4 0.--13. 1. "SSC,sendSlopeCredit Value When AV operation is enabled this field contains the sendSlopeCredit value required for credit-based shaper algorithm for Queue 1. This is the rate of change of credit in bits per cycle (40 ns 8 ns and 3.2 ns for 100 Mbps.." line.long 0x8 "MTL_TXQ1_HICREDIT,The hiCredit register contains the hiCredit value required for the credit-based shaper algorithm for the Queue." rbitfld.long 0x8 29.--31. "RESERVED_31_29,Reserved." "0,1,2,3,4,5,6,7" newline hexmask.long 0x8 0.--28. 1. "HC,hiCredit Value When the AV feature is enabled this field contains the hiCredit value required for the credit-based shaper algorithm. This is the maximum value that can be accumulated in the credit parameter. This is specified in bits scaled by 1 024." line.long 0xC "MTL_TXQ1_LOCREDIT,The loCredit register contains the loCredit value required for the credit-based shaper algorithm for the Queue." rbitfld.long 0xC 29.--31. "RESERVED_31_29,Reserved." "0,1,2,3,4,5,6,7" newline hexmask.long 0xC 0.--28. 1. "LC,loCredit Value When AV operation is enabled this field contains the loCredit value required for the credit-based shaper algorithm. This is the minimum value that can be accumulated in the credit parameter. This is specified in bits scaled by 1 024." group.long 0x2C++0x7 line.long 0x0 "MTL_Q1_INTERRUPT_CONTROL_STATUS,This register contains the interrupt enable and status bits for the queue 1 interrupts." hexmask.long.byte 0x0 25.--31. 1. "RESERVED_31_25,Reserved." newline bitfld.long 0x0 24. "RXOIE,Receive Queue Overflow Interrupt Enable When this bit is set the Receive Queue Overflow interrupt is enabled. When this bit is reset the Receive Queue Overflow interrupt is disabled. 0x0: Receive Queue Overflow Interrupt is disabled 0x1: Receive.." "Receive Queue Overflow Interrupt is disabled,Receive Queue Overflow Interrupt is enabled" newline hexmask.long.byte 0x0 17.--23. 1. "RESERVED_23_17,Reserved." newline bitfld.long 0x0 16. "RXOVFIS,Receive Queue Overflow Interrupt Status This bit indicates that the Receive Queue had an overflow while receiving the packet. If a partial packet is transferred to the application the overflow status is set in RDES3[21]. This bit is cleared when.." "Receive Queue Overflow Interrupt Status not..,Receive Queue Overflow Interrupt Status detected" newline hexmask.long.byte 0x0 10.--15. 1. "RESERVED_15_10,Reserved." newline bitfld.long 0x0 9. "ABPSIE,Average Bits Per Slot Interrupt Enable When this bit is set the MAC asserts the sbd_intr_o or mci_intr_o interrupt when the average bits per slot status is updated. When this bit is cleared the interrupt is not asserted for such an event. 0x0:.." "Average Bits Per Slot Interrupt is disabled,Average Bits Per Slot Interrupt is enabled" newline bitfld.long 0x0 8. "TXUIE,Transmit Queue Underflow Interrupt Enable When this bit is set the Transmit Queue Underflow interrupt is enabled. When this bit is reset the Transmit Queue Underflow interrupt is disabled. 0x0: Transmit Queue Underflow Interrupt Status is.." "Transmit Queue Underflow Interrupt Status is..,Transmit Queue Underflow Interrupt Status is.." newline hexmask.long.byte 0x0 2.--7. 1. "RESERVED_7_2,Reserved." newline bitfld.long 0x0 1. "ABPSIS,Average Bits Per Slot Interrupt Status When set this bit indicates that the MAC has updated the ABS value. This bit is cleared when the application writes 1 to this bit. Access restriction applies. Self-set to 1 on internal event. Setting 1.." "Average Bits Per Slot Interrupt Status not..,Average Bits Per Slot Interrupt Status detected" newline bitfld.long 0x0 0. "TXUNFIS,Transmit Queue Underflow Interrupt Status This bit indicates that the Transmit Queue had an underflow while transmitting the packet. Transmission is suspended and an Underflow Error TDES3[2] is set. This bit is cleared when the application writes.." "Transmit Queue Underflow Interrupt Status not..,Transmit Queue Underflow Interrupt Status detected" line.long 0x4 "MTL_RXQ1_OPERATION_MODE,The Queue 1 Receive Operation Mode register establishes the Receive queue operating modes and command. The RFA and RFD fields are not backward compatible with the RFA and RFD fields of 4.00a release" hexmask.long.byte 0x4 25.--31. 1. "RESERVED_31_Y,Reserved." newline hexmask.long.byte 0x4 20.--24. 1. "RQS,Receive Queue Size This field indicates the size of the allocated Receive queues in blocks of 256 bytes. The RQS field is read-write only if the number of Rx Queues more than one the reset value is 0x0 and indicates size of 256 bytes. When the.." newline rbitfld.long 0x4 18.--19. "RESERVED_19_Y,Reserved." "0,1,2,3" newline hexmask.long.byte 0x4 14.--17. 1. "RFD,Threshold for Deactivating Flow Control (in half-duplex and full-duplex modes) These bits control the threshold (fill-level of Rx queue) at which the flow control is de-asserted after activation: - 0: Full minus 1 KB that is FULL 1 KB - 1: Full.." newline rbitfld.long 0x4 12.--13. "RESERVED_13_Y,Reserved." "0,1,2,3" newline hexmask.long.byte 0x4 8.--11. 1. "RFA,Threshold for Activating Flow Control (in half-duplex and full-duplex These bits control the threshold (fill-level of Rx queue) at which the flow control is activated: For more information on encoding for this field see RFD." newline bitfld.long 0x4 7. "EHFC,Enable Hardware Flow Control When this bit is set the flow control signal operation based on the fill-level of Rx queue is enabled. When reset the flow control operation is disabled. 0x0: Hardware Flow Control is disabled 0x1: Hardware Flow.." "Hardware Flow Control is disabled,Hardware Flow Control is enabled" newline bitfld.long 0x4 6. "DIS_TCP_EF,Disable Dropping of TCP/IP Checksum Error Packets When this bit is set the MAC does not drop the packets which only have the errors detected by the Receive Checksum Offload engine. Such packets have errors only in the encapsulated payload." "Dropping of TCP/IP Checksum Error Packets is..,Dropping of TCP/IP Checksum Error Packets is.." newline bitfld.long 0x4 5. "RSF,Receive Queue Store and Forward When this bit is set the DWC_ether_qos reads a packet from the Rx queue only after the complete packet has been written to it ignoring the RTC field of this register. When this bit is reset the Rx queue operates in.." "Receive Queue Store and Forward is disabled,Receive Queue Store and Forward is enabled" newline bitfld.long 0x4 4. "FEP,Forward Error Packets When this bit is reset the Rx queue drops packets with error status (CRC error GMII_ER watchdog timeout or overflow). However if the start byte (write) pointer of a packet is already transferred to the read controller side.." "Forward Error Packets is disabled,Forward Error Packets is enabled" newline bitfld.long 0x4 3. "FUP,Forward Undersized Good Packets When this bit is set the Rx queue forwards the undersized good packets (packets with no error and length less than 64 bytes) including pad-bytes and CRC. When this bit is reset the Rx queue drops all packets of less.." "Forward Undersized Good Packets is disabled,Forward Undersized Good Packets is enabled" newline rbitfld.long 0x4 2. "RESERVED_2,Reserved." "0,1" newline bitfld.long 0x4 0.--1. "RTC,Receive Queue Threshold Control These bits control the threshold level of the MTL Rx queue (in bytes): The received packet is transferred to the application or DMA when the packet size within the MTL Rx queue is larger than the threshold. In addition.." "0,1,2,3" rgroup.long 0x34++0x7 line.long 0x0 "MTL_RXQ1_MISSED_PACKET_OVERFLOW_CNT,The Queue 1 Missed Packet and Overflow Counter register contains the counter for packets missed because of Receive queue packet flush and packets discarded because of Receive queue overflow." hexmask.long.byte 0x0 28.--31. 1. "RESERVED_31_28,Reserved." newline bitfld.long 0x0 27. "MISCNTOVF,Missed Packet Counter Overflow Bit When set this bit indicates that the Rx Queue Missed Packet Counter crossed the maximum limit. Access restriction applies. Clears on read. Self-set to 1 on internal event. 0x1: Missed Packet Counter overflow.." "Missed Packet Counter overflow not detected,Missed Packet Counter overflow detected" newline hexmask.long.word 0x0 16.--26. 1. "MISPKTCNT,Missed Packet Counter This field indicates the number of packets missed by the DWC_ether_qos because the application asserted ari_pkt_flush_i[] for this queue. This counter is reset when this register is read with mci_be_i[0] at 1b1. This.." newline hexmask.long.byte 0x0 12.--15. 1. "RESERVED_15_12,Reserved." newline bitfld.long 0x0 11. "OVFCNTOVF,Overflow Counter Overflow Bit When set this bit indicates that the Rx Queue Overflow Packet Counter field crossed the maximum limit. Access restriction applies. Clears on read. Self-set to 1 on internal event. 0x1: Overflow Counter overflow.." "Overflow Counter overflow not detected,Overflow Counter overflow detected" newline hexmask.long.word 0x0 0.--10. 1. "OVFPKTCNT,Overflow Packet Counter This field indicates the number of packets discarded by the DWC_ether_qos because of Receive queue overflow. This counter is incremented each time the DWC_ether_qos discards an incoming packet because of overflow. This.." line.long 0x4 "MTL_RXQ1_DEBUG,The Queue 1 Receive Debug register gives the debug status of various blocks related to the Receive queue." bitfld.long 0x4 30.--31. "RESERVED_31_30,Reserved." "0,1,2,3" newline hexmask.long.word 0x4 16.--29. 1. "PRXQ,Number of Packets in Receive Queue This field indicates the current number of packets in the Rx Queue. The theoretical maximum value for this field is 256KB/16B = 16K Packets that is Max_Queue_Size/Min_Packet_Size." newline hexmask.long.word 0x4 6.--15. 1. "RESERVED_15_6,Reserved." newline bitfld.long 0x4 4.--5. "RXQSTS,MTL Rx Queue Fill-Level Status This field gives the status of the fill-level of the Rx Queue: 0x2: Rx Queue fill-level above flow-control activate threshold 0x1: Rx Queue fill-level below flow-control deactivate threshold 0x0: Rx Queue empty 0x3:.." "Rx Queue empty,Rx Queue fill-level below flow-control..,Rx Queue fill-level above flow-control activate..,Rx Queue full" newline bitfld.long 0x4 3. "RESERVED_3,Reserved." "0,1" newline bitfld.long 0x4 1.--2. "RRCSTS,MTL Rx Queue Read Controller State This field gives the state of the Rx queue Read controller: 0x3: Flushing the packet data and status 0x0: Idle state 0x1: Reading packet data 0x2: Reading packet status (or timestamp)" "Idle state,Reading packet data,Reading packet status,Flushing the packet data and status" newline bitfld.long 0x4 0. "RWCSTS,MTL Rx Queue Write Controller Active Status When high this bit indicates that the MTL Rx queue Write controller is active and it is transferring a received packet to the Rx Queue. 0x1: MTL Rx Queue Write Controller Active Status detected 0x0:.." "MTL Rx Queue Write Controller Active Status not..,MTL Rx Queue Write Controller Active Status.." group.long 0x3C++0x3 line.long 0x0 "MTL_RXQ1_CONTROL,The Queue Receive Control register controls the receive arbitration and passing of received packets to the application." hexmask.long 0x0 4.--31. 1. "RESERVED_31_4,Reserved." newline bitfld.long 0x0 3. "RXQ_FRM_ARBIT,Receive Queue Packet Arbitration When this bit is set the DWC_ether_qos drives the packet data to the ARI interface such that the entire packet data of currently-selected queue is transmitted before switching to other queue. When this bit.." "Receive Queue Packet Arbitration is disabled,Receive Queue Packet Arbitration is enabled" newline bitfld.long 0x0 0.--2. "RXQ_WEGT,Receive Queue Weight This field indicates the weight assigned to the Rx Queue 0. The weight is used as the number of continuous PBL or packets requests (depending on the RXQ_FRM_ARBIT) allocated to the queue in one arbitration cycle." "0,1,2,3,4,5,6,7" tree.end tree "EQOS_MTL_Q2" group.long 0x0++0x3 line.long 0x0 "MTL_TXQ2_OPERATION_MODE,The Queue 2 Transmit Operation Mode register establishes the Transmit queue operating modes and commands." hexmask.long.word 0x0 21.--31. 1. "RESERVED_31_Y,Reserved." newline hexmask.long.byte 0x0 16.--20. 1. "TQS,Transmit Queue Size This field indicates the size of the allocated Transmit queues in blocks of 256 bytes. The TQS field is read-write only if the number of Tx Queues more than one the reset value is 0x0 and indicates size of 256 bytes. When the.." newline hexmask.long.word 0x0 7.--15. 1. "RESERVED_15_7,Reserved." newline bitfld.long 0x0 4.--6. "TTC,Transmit Threshold Control These bits control the threshold level of the MTL Tx Queue. The transmission starts when the packet size within the MTL Tx Queue is larger than the threshold. In addition full packets with length less than the threshold.." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 2.--3. "TXQEN,Transmit Queue Enable This field is used to enable/disable the transmit queue 0. - 2'b00: Not enabled - 2'b01: Enable in AV mode - 2'b10: Enabled - 2'b11: Reserved Note: In multiple Tx queues configuration all the queues are disabled by default." "Not enabled,Enable in AV mode,Enabled,Reserved" newline bitfld.long 0x0 1. "TSF,Transmit Store and Forward When this bit is set the transmission starts when a full packet resides in the MTL Tx queue. When this bit is set the TTC values specified in Bits[6:4] of this register are ignored. This bit should be changed only when.." "Transmit Store and Forward is disabled,Transmit Store and Forward is enabled" newline bitfld.long 0x0 0. "FTQ,Flush Transmit Queue When this bit is set the Tx queue controller logic is reset to its default values. Therefore all the data in the Tx queue is lost or flushed. This bit is internally reset when the flushing operation is complete. Until this bit.." "Flush Transmit Queue is disabled,Flush Transmit Queue is enabled" rgroup.long 0x4++0x7 line.long 0x0 "MTL_TXQ2_UNDERFLOW,The Queue 2 Underflow Counter register contains the counter for packets aborted because of Transmit queue underflow and packets missed because of Receive queue packet flush" hexmask.long.tbyte 0x0 12.--31. 1. "RESERVED_31_12,Reserved." newline bitfld.long 0x0 11. "UFCNTOVF,Overflow Bit for Underflow Packet Counter This bit is set every time the Tx queue Underflow Packet Counter field overflows that is it has crossed the maximum count. In such a scenario the overflow packet counter is reset to all-zeros and this.." "Overflow not detected for Underflow Packet Counter,Overflow detected for Underflow Packet Counter" newline hexmask.long.word 0x0 0.--10. 1. "UFFRMCNT,Underflow Packet Counter This field indicates the number of packets aborted by the controller because of Tx Queue Underflow. This counter is incremented each time the MAC aborts outgoing packet because of underflow. The counter is cleared when.." line.long 0x4 "MTL_TXQ2_DEBUG,The Queue 2 Transmit Debug register gives the debug status of various blocks related to the Transmit queue." hexmask.long.word 0x4 23.--31. 1. "RESERVED_31_23,Reserved." newline bitfld.long 0x4 20.--22. "STXSTSF,Number of Status Words in Tx Status FIFO of Queue This field indicates the current number of status in the Tx Status FIFO of this queue. When the DTXSTS bit of MTL_Operation_Mode register is set to 1 this field does not reflect the number of.." "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 19. "RESERVED_19,Reserved." "0,1" newline bitfld.long 0x4 16.--18. "PTXQ,Number of Packets in the Transmit Queue This field indicates the current number of packets in the Tx Queue. When the DTXSTS bit of MTL_Operation_Mode register is set to 1 this field does not reflect the number of packets in the Transmit queue." "0,1,2,3,4,5,6,7" newline hexmask.long.word 0x4 6.--15. 1. "RESERVED_15_6,Reserved." newline bitfld.long 0x4 5. "TXSTSFSTS,MTL Tx Status FIFO Full Status When high this bit indicates that the MTL Tx Status FIFO is full. Therefore the MTL cannot accept any more packets for transmission. 0x1: MTL Tx Status FIFO Full status is detected 0x0: MTL Tx Status FIFO Full.." "MTL Tx Status FIFO Full status is not detected,MTL Tx Status FIFO Full status is detected" newline bitfld.long 0x4 4. "TXQSTS,MTL Tx Queue Not Empty Status When this bit is high it indicates that the MTL Tx Queue is not empty and some data is left for transmission. 0x1: MTL Tx Queue Not Empty status is detected 0x0: MTL Tx Queue Not Empty status is not detected" "MTL Tx Queue Not Empty status is not detected,MTL Tx Queue Not Empty status is detected" newline bitfld.long 0x4 3. "TWCSTS,MTL Tx Queue Write Controller Status When high this bit indicates that the MTL Tx Queue Write Controller is active and it is transferring the data to the Tx Queue. 0x1: MTL Tx Queue Write Controller status is detected 0x0: MTL Tx Queue Write.." "MTL Tx Queue Write Controller status is not..,MTL Tx Queue Write Controller status is detected" newline bitfld.long 0x4 1.--2. "TRCSTS,MTL Tx Queue Read Controller Status This field indicates the state of the Tx Queue Read Controller: 0x3: Flushing the Tx queue because of the Packet Abort request from the MAC 0x0: Idle state 0x1: Read state (transferring data to the MAC.." "Idle state,Read state,Waiting for pending Tx Status from the MAC..,Flushing the Tx queue because of the Packet.." newline bitfld.long 0x4 0. "TXQPAUSED,Transmit Queue in Pause When this bit is high and the Rx flow control is enabled it indicates that the Tx Queue is in the Pause condition (in the full-duplex only mode) because of the following: - Reception of the PFC packet for the priorities.." "Transmit Queue in Pause status is not detected,Transmit Queue in Pause status is detected" group.long 0x10++0x3 line.long 0x0 "MTL_TXQ2_ETS_CONTROL,The Queue ETS Control register controls the enhanced transmission selection operation." hexmask.long 0x0 7.--31. 1. "RESERVED_31_7,Reserved." newline bitfld.long 0x0 4.--6. "SLC,Slot Count If the credit-based shaper algorithm is enabled the software can program the number of slots (of duration programmed in DMA_CH[n]_Slot_Interval register) over which the average transmitted bits per slot provided in the.." "?,?,?,?,?,Reserved,?,?" newline bitfld.long 0x0 3. "CC,Credit Control When this bit is set the accumulated credit parameter in the credit-based shaper algorithm logic is not reset to zero when there is positive credit and no packet to transmit in Channel 1. The credit accumulates even when there is no.." "Credit Control is disabled,Credit Control is enabled" newline bitfld.long 0x0 2. "AVALG,AV Algorithm When Queue 1 is programmed for AV this field configures the scheduling algorithm for this queue: This bit when set indicates credit based shaper algorithm (CBS) is selected for Queue 1 traffic. When reset strict priority is.." "CBS Algorithm is disabled,CBS Algorithm is enabled" newline rbitfld.long 0x0 0.--1. "RESERVED_1_0,Reserved." "0,1,2,3" rgroup.long 0x14++0x3 line.long 0x0 "MTL_TXQ2_ETS_STATUS,The Queue 2 ETS Status register provides the average traffic transmitted in Queue 2." hexmask.long.byte 0x0 24.--31. 1. "RESERVED_31_24,Reserved." newline hexmask.long.tbyte 0x0 0.--23. 1. "ABS,Average Bits per Slot This field contains the average transmitted bits per slot. If AV operation is enabled this field is computed over number of slots programmed in the SLC field of MTL_TxQ[n]_ETS_CONTROL register. The maximum value of this field.." group.long 0x18++0xF line.long 0x0 "MTL_TXQ2_QUANTUM_WEIGHT,The Queue 2 idleSlopeCredit. Quantum or Weights register provides the average traffic transmitted in Queue 2." hexmask.long.word 0x0 21.--31. 1. "RESERVED_31_21,Reserved." newline hexmask.long.tbyte 0x0 0.--20. 1. "ISCQW,idleSlopeCredit Quantum or Weights - idleSlopeCredit When AV feature is enabled this field contains the idleSlopeCredit value required for the credit-based shaper algorithm for Queue 1. This is the rate of change of credit in bits per cycle (40.." line.long 0x4 "MTL_TXQ2_SENDSLOPECREDIT,The sendSlopeCredit register contains the sendSlope credit value required for the credit-based shaper algorithm for the Queue." hexmask.long.tbyte 0x4 14.--31. 1. "RESERVED_31_14,Reserved." newline hexmask.long.word 0x4 0.--13. 1. "SSC,sendSlopeCredit Value When AV operation is enabled this field contains the sendSlopeCredit value required for credit-based shaper algorithm for Queue 1. This is the rate of change of credit in bits per cycle (40 ns 8 ns and 3.2 ns for 100 Mbps.." line.long 0x8 "MTL_TXQ2_HICREDIT,The hiCredit register contains the hiCredit value required for the credit-based shaper algorithm for the Queue." rbitfld.long 0x8 29.--31. "RESERVED_31_29,Reserved." "0,1,2,3,4,5,6,7" newline hexmask.long 0x8 0.--28. 1. "HC,hiCredit Value When the AV feature is enabled this field contains the hiCredit value required for the credit-based shaper algorithm. This is the maximum value that can be accumulated in the credit parameter. This is specified in bits scaled by 1 024." line.long 0xC "MTL_TXQ2_LOCREDIT,The loCredit register contains the loCredit value required for the credit-based shaper algorithm for the Queue." rbitfld.long 0xC 29.--31. "RESERVED_31_29,Reserved." "0,1,2,3,4,5,6,7" newline hexmask.long 0xC 0.--28. 1. "LC,loCredit Value When AV operation is enabled this field contains the loCredit value required for the credit-based shaper algorithm. This is the minimum value that can be accumulated in the credit parameter. This is specified in bits scaled by 1 024." group.long 0x2C++0x7 line.long 0x0 "MTL_Q2_INTERRUPT_CONTROL_STATUS,This register contains the interrupt enable and status bits for the queue 2 interrupts." hexmask.long.byte 0x0 25.--31. 1. "RESERVED_31_25,Reserved." newline bitfld.long 0x0 24. "RXOIE,Receive Queue Overflow Interrupt Enable When this bit is set the Receive Queue Overflow interrupt is enabled. When this bit is reset the Receive Queue Overflow interrupt is disabled. 0x0: Receive Queue Overflow Interrupt is disabled 0x1: Receive.." "Receive Queue Overflow Interrupt is disabled,Receive Queue Overflow Interrupt is enabled" newline hexmask.long.byte 0x0 17.--23. 1. "RESERVED_23_17,Reserved." newline bitfld.long 0x0 16. "RXOVFIS,Receive Queue Overflow Interrupt Status This bit indicates that the Receive Queue had an overflow while receiving the packet. If a partial packet is transferred to the application the overflow status is set in RDES3[21]. This bit is cleared when.." "Receive Queue Overflow Interrupt Status not..,Receive Queue Overflow Interrupt Status detected" newline hexmask.long.byte 0x0 10.--15. 1. "RESERVED_15_10,Reserved." newline bitfld.long 0x0 9. "ABPSIE,Average Bits Per Slot Interrupt Enable When this bit is set the MAC asserts the sbd_intr_o or mci_intr_o interrupt when the average bits per slot status is updated. When this bit is cleared the interrupt is not asserted for such an event. 0x0:.." "Average Bits Per Slot Interrupt is disabled,Average Bits Per Slot Interrupt is enabled" newline bitfld.long 0x0 8. "TXUIE,Transmit Queue Underflow Interrupt Enable When this bit is set the Transmit Queue Underflow interrupt is enabled. When this bit is reset the Transmit Queue Underflow interrupt is disabled. 0x0: Transmit Queue Underflow Interrupt Status is.." "Transmit Queue Underflow Interrupt Status is..,Transmit Queue Underflow Interrupt Status is.." newline hexmask.long.byte 0x0 2.--7. 1. "RESERVED_7_2,Reserved." newline bitfld.long 0x0 1. "ABPSIS,Average Bits Per Slot Interrupt Status When set this bit indicates that the MAC has updated the ABS value. This bit is cleared when the application writes 1 to this bit. Access restriction applies. Self-set to 1 on internal event. Setting 1.." "Average Bits Per Slot Interrupt Status not..,Average Bits Per Slot Interrupt Status detected" newline bitfld.long 0x0 0. "TXUNFIS,Transmit Queue Underflow Interrupt Status This bit indicates that the Transmit Queue had an underflow while transmitting the packet. Transmission is suspended and an Underflow Error TDES3[2] is set. This bit is cleared when the application writes.." "Transmit Queue Underflow Interrupt Status not..,Transmit Queue Underflow Interrupt Status detected" line.long 0x4 "MTL_RXQ2_OPERATION_MODE,The Queue 2 Receive Operation Mode register establishes the Receive queue operating modes and command. The RFA and RFD fields are not backward compatible with the RFA and RFD fields of 4.00a release" hexmask.long.byte 0x4 25.--31. 1. "RESERVED_31_Y,Reserved." newline hexmask.long.byte 0x4 20.--24. 1. "RQS,Receive Queue Size This field indicates the size of the allocated Receive queues in blocks of 256 bytes. The RQS field is read-write only if the number of Rx Queues more than one the reset value is 0x0 and indicates size of 256 bytes. When the.." newline rbitfld.long 0x4 18.--19. "RESERVED_19_Y,Reserved." "0,1,2,3" newline hexmask.long.byte 0x4 14.--17. 1. "RFD,Threshold for Deactivating Flow Control (in half-duplex and full-duplex modes) These bits control the threshold (fill-level of Rx queue) at which the flow control is de-asserted after activation: - 0: Full minus 1 KB that is FULL 1 KB - 1: Full.." newline rbitfld.long 0x4 12.--13. "RESERVED_13_Y,Reserved." "0,1,2,3" newline hexmask.long.byte 0x4 8.--11. 1. "RFA,Threshold for Activating Flow Control (in half-duplex and full-duplex These bits control the threshold (fill-level of Rx queue) at which the flow control is activated: For more information on encoding for this field see RFD." newline bitfld.long 0x4 7. "EHFC,Enable Hardware Flow Control When this bit is set the flow control signal operation based on the fill-level of Rx queue is enabled. When reset the flow control operation is disabled. 0x0: Hardware Flow Control is disabled 0x1: Hardware Flow.." "Hardware Flow Control is disabled,Hardware Flow Control is enabled" newline bitfld.long 0x4 6. "DIS_TCP_EF,Disable Dropping of TCP/IP Checksum Error Packets When this bit is set the MAC does not drop the packets which only have the errors detected by the Receive Checksum Offload engine. Such packets have errors only in the encapsulated payload." "Dropping of TCP/IP Checksum Error Packets is..,Dropping of TCP/IP Checksum Error Packets is.." newline bitfld.long 0x4 5. "RSF,Receive Queue Store and Forward When this bit is set the DWC_ether_qos reads a packet from the Rx queue only after the complete packet has been written to it ignoring the RTC field of this register. When this bit is reset the Rx queue operates in.." "Receive Queue Store and Forward is disabled,Receive Queue Store and Forward is enabled" newline bitfld.long 0x4 4. "FEP,Forward Error Packets When this bit is reset the Rx queue drops packets with error status (CRC error GMII_ER watchdog timeout or overflow). However if the start byte (write) pointer of a packet is already transferred to the read controller side.." "Forward Error Packets is disabled,Forward Error Packets is enabled" newline bitfld.long 0x4 3. "FUP,Forward Undersized Good Packets When this bit is set the Rx queue forwards the undersized good packets (packets with no error and length less than 64 bytes) including pad-bytes and CRC. When this bit is reset the Rx queue drops all packets of less.." "Forward Undersized Good Packets is disabled,Forward Undersized Good Packets is enabled" newline rbitfld.long 0x4 2. "RESERVED_2,Reserved." "0,1" newline bitfld.long 0x4 0.--1. "RTC,Receive Queue Threshold Control These bits control the threshold level of the MTL Rx queue (in bytes): The received packet is transferred to the application or DMA when the packet size within the MTL Rx queue is larger than the threshold. In addition.." "0,1,2,3" rgroup.long 0x34++0x7 line.long 0x0 "MTL_RXQ2_MISSED_PACKET_OVERFLOW_CNT,The Queue 2 Missed Packet and Overflow Counter register contains the counter for packets missed because of Receive queue packet flush and packets discarded because of Receive queue overflow." hexmask.long.byte 0x0 28.--31. 1. "RESERVED_31_28,Reserved." newline bitfld.long 0x0 27. "MISCNTOVF,Missed Packet Counter Overflow Bit When set this bit indicates that the Rx Queue Missed Packet Counter crossed the maximum limit. Access restriction applies. Clears on read. Self-set to 1 on internal event. 0x1: Missed Packet Counter overflow.." "Missed Packet Counter overflow not detected,Missed Packet Counter overflow detected" newline hexmask.long.word 0x0 16.--26. 1. "MISPKTCNT,Missed Packet Counter This field indicates the number of packets missed by the DWC_ether_qos because the application asserted ari_pkt_flush_i[] for this queue. This counter is reset when this register is read with mci_be_i[0] at 1b1. This.." newline hexmask.long.byte 0x0 12.--15. 1. "RESERVED_15_12,Reserved." newline bitfld.long 0x0 11. "OVFCNTOVF,Overflow Counter Overflow Bit When set this bit indicates that the Rx Queue Overflow Packet Counter field crossed the maximum limit. Access restriction applies. Clears on read. Self-set to 1 on internal event. 0x1: Overflow Counter overflow.." "Overflow Counter overflow not detected,Overflow Counter overflow detected" newline hexmask.long.word 0x0 0.--10. 1. "OVFPKTCNT,Overflow Packet Counter This field indicates the number of packets discarded by the DWC_ether_qos because of Receive queue overflow. This counter is incremented each time the DWC_ether_qos discards an incoming packet because of overflow. This.." line.long 0x4 "MTL_RXQ2_DEBUG,The Queue 2 Receive Debug register gives the debug status of various blocks related to the Receive queue." bitfld.long 0x4 30.--31. "RESERVED_31_30,Reserved." "0,1,2,3" newline hexmask.long.word 0x4 16.--29. 1. "PRXQ,Number of Packets in Receive Queue This field indicates the current number of packets in the Rx Queue. The theoretical maximum value for this field is 256KB/16B = 16K Packets that is Max_Queue_Size/Min_Packet_Size." newline hexmask.long.word 0x4 6.--15. 1. "RESERVED_15_6,Reserved." newline bitfld.long 0x4 4.--5. "RXQSTS,MTL Rx Queue Fill-Level Status This field gives the status of the fill-level of the Rx Queue: 0x2: Rx Queue fill-level above flow-control activate threshold 0x1: Rx Queue fill-level below flow-control deactivate threshold 0x0: Rx Queue empty 0x3:.." "Rx Queue empty,Rx Queue fill-level below flow-control..,Rx Queue fill-level above flow-control activate..,Rx Queue full" newline bitfld.long 0x4 3. "RESERVED_3,Reserved." "0,1" newline bitfld.long 0x4 1.--2. "RRCSTS,MTL Rx Queue Read Controller State This field gives the state of the Rx queue Read controller: 0x3: Flushing the packet data and status 0x0: Idle state 0x1: Reading packet data 0x2: Reading packet status (or timestamp)" "Idle state,Reading packet data,Reading packet status,Flushing the packet data and status" newline bitfld.long 0x4 0. "RWCSTS,MTL Rx Queue Write Controller Active Status When high this bit indicates that the MTL Rx queue Write controller is active and it is transferring a received packet to the Rx Queue. 0x1: MTL Rx Queue Write Controller Active Status detected 0x0:.." "MTL Rx Queue Write Controller Active Status not..,MTL Rx Queue Write Controller Active Status.." group.long 0x3C++0x3 line.long 0x0 "MTL_RXQ2_CONTROL,The Queue Receive Control register controls the receive arbitration and passing of received packets to the application." hexmask.long 0x0 4.--31. 1. "RESERVED_31_4,Reserved." newline bitfld.long 0x0 3. "RXQ_FRM_ARBIT,Receive Queue Packet Arbitration When this bit is set the DWC_ether_qos drives the packet data to the ARI interface such that the entire packet data of currently-selected queue is transmitted before switching to other queue. When this bit.." "Receive Queue Packet Arbitration is disabled,Receive Queue Packet Arbitration is enabled" newline bitfld.long 0x0 0.--2. "RXQ_WEGT,Receive Queue Weight This field indicates the weight assigned to the Rx Queue 0. The weight is used as the number of continuous PBL or packets requests (depending on the RXQ_FRM_ARBIT) allocated to the queue in one arbitration cycle." "0,1,2,3,4,5,6,7" tree.end tree "EQOS_MTL_Q3" group.long 0x0++0x3 line.long 0x0 "MTL_TXQ3_OPERATION_MODE,The Queue 3 Transmit Operation Mode register establishes the Transmit queue operating modes and commands." hexmask.long.word 0x0 21.--31. 1. "RESERVED_31_Y,Reserved." newline hexmask.long.byte 0x0 16.--20. 1. "TQS,Transmit Queue Size This field indicates the size of the allocated Transmit queues in blocks of 256 bytes. The TQS field is read-write only if the number of Tx Queues more than one the reset value is 0x0 and indicates size of 256 bytes. When the.." newline hexmask.long.word 0x0 7.--15. 1. "RESERVED_15_7,Reserved." newline bitfld.long 0x0 4.--6. "TTC,Transmit Threshold Control These bits control the threshold level of the MTL Tx Queue. The transmission starts when the packet size within the MTL Tx Queue is larger than the threshold. In addition full packets with length less than the threshold.." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 2.--3. "TXQEN,Transmit Queue Enable This field is used to enable/disable the transmit queue 0. - 2'b00: Not enabled - 2'b01: Enable in AV mode - 2'b10: Enabled - 2'b11: Reserved Note: In multiple Tx queues configuration all the queues are disabled by default." "Not enabled,Enable in AV mode,Enabled,Reserved" newline bitfld.long 0x0 1. "TSF,Transmit Store and Forward When this bit is set the transmission starts when a full packet resides in the MTL Tx queue. When this bit is set the TTC values specified in Bits[6:4] of this register are ignored. This bit should be changed only when.." "Transmit Store and Forward is disabled,Transmit Store and Forward is enabled" newline bitfld.long 0x0 0. "FTQ,Flush Transmit Queue When this bit is set the Tx queue controller logic is reset to its default values. Therefore all the data in the Tx queue is lost or flushed. This bit is internally reset when the flushing operation is complete. Until this bit.." "Flush Transmit Queue is disabled,Flush Transmit Queue is enabled" rgroup.long 0x4++0x7 line.long 0x0 "MTL_TXQ3_UNDERFLOW,The Queue 3 Underflow Counter register contains the counter for packets aborted because of Transmit queue underflow and packets missed because of Receive queue packet flush" hexmask.long.tbyte 0x0 12.--31. 1. "RESERVED_31_12,Reserved." newline bitfld.long 0x0 11. "UFCNTOVF,Overflow Bit for Underflow Packet Counter This bit is set every time the Tx queue Underflow Packet Counter field overflows that is it has crossed the maximum count. In such a scenario the overflow packet counter is reset to all-zeros and this.." "Overflow not detected for Underflow Packet Counter,Overflow detected for Underflow Packet Counter" newline hexmask.long.word 0x0 0.--10. 1. "UFFRMCNT,Underflow Packet Counter This field indicates the number of packets aborted by the controller because of Tx Queue Underflow. This counter is incremented each time the MAC aborts outgoing packet because of underflow. The counter is cleared when.." line.long 0x4 "MTL_TXQ3_DEBUG,The Queue 3 Transmit Debug register gives the debug status of various blocks related to the Transmit queue." hexmask.long.word 0x4 23.--31. 1. "RESERVED_31_23,Reserved." newline bitfld.long 0x4 20.--22. "STXSTSF,Number of Status Words in Tx Status FIFO of Queue This field indicates the current number of status in the Tx Status FIFO of this queue. When the DTXSTS bit of MTL_Operation_Mode register is set to 1 this field does not reflect the number of.." "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 19. "RESERVED_19,Reserved." "0,1" newline bitfld.long 0x4 16.--18. "PTXQ,Number of Packets in the Transmit Queue This field indicates the current number of packets in the Tx Queue. When the DTXSTS bit of MTL_Operation_Mode register is set to 1 this field does not reflect the number of packets in the Transmit queue." "0,1,2,3,4,5,6,7" newline hexmask.long.word 0x4 6.--15. 1. "RESERVED_15_6,Reserved." newline bitfld.long 0x4 5. "TXSTSFSTS,MTL Tx Status FIFO Full Status When high this bit indicates that the MTL Tx Status FIFO is full. Therefore the MTL cannot accept any more packets for transmission. 0x1: MTL Tx Status FIFO Full status is detected 0x0: MTL Tx Status FIFO Full.." "MTL Tx Status FIFO Full status is not detected,MTL Tx Status FIFO Full status is detected" newline bitfld.long 0x4 4. "TXQSTS,MTL Tx Queue Not Empty Status When this bit is high it indicates that the MTL Tx Queue is not empty and some data is left for transmission. 0x1: MTL Tx Queue Not Empty status is detected 0x0: MTL Tx Queue Not Empty status is not detected" "MTL Tx Queue Not Empty status is not detected,MTL Tx Queue Not Empty status is detected" newline bitfld.long 0x4 3. "TWCSTS,MTL Tx Queue Write Controller Status When high this bit indicates that the MTL Tx Queue Write Controller is active and it is transferring the data to the Tx Queue. 0x1: MTL Tx Queue Write Controller status is detected 0x0: MTL Tx Queue Write.." "MTL Tx Queue Write Controller status is not..,MTL Tx Queue Write Controller status is detected" newline bitfld.long 0x4 1.--2. "TRCSTS,MTL Tx Queue Read Controller Status This field indicates the state of the Tx Queue Read Controller: 0x3: Flushing the Tx queue because of the Packet Abort request from the MAC 0x0: Idle state 0x1: Read state (transferring data to the MAC.." "Idle state,Read state,Waiting for pending Tx Status from the MAC..,Flushing the Tx queue because of the Packet.." newline bitfld.long 0x4 0. "TXQPAUSED,Transmit Queue in Pause When this bit is high and the Rx flow control is enabled it indicates that the Tx Queue is in the Pause condition (in the full-duplex only mode) because of the following: - Reception of the PFC packet for the priorities.." "Transmit Queue in Pause status is not detected,Transmit Queue in Pause status is detected" group.long 0x10++0x3 line.long 0x0 "MTL_TXQ3_ETS_CONTROL,The Queue ETS Control register controls the enhanced transmission selection operation." hexmask.long 0x0 7.--31. 1. "RESERVED_31_7,Reserved." newline bitfld.long 0x0 4.--6. "SLC,Slot Count If the credit-based shaper algorithm is enabled the software can program the number of slots (of duration programmed in DMA_CH[n]_Slot_Interval register) over which the average transmitted bits per slot provided in the.." "?,?,?,?,?,Reserved,?,?" newline bitfld.long 0x0 3. "CC,Credit Control When this bit is set the accumulated credit parameter in the credit-based shaper algorithm logic is not reset to zero when there is positive credit and no packet to transmit in Channel 1. The credit accumulates even when there is no.." "Credit Control is disabled,Credit Control is enabled" newline bitfld.long 0x0 2. "AVALG,AV Algorithm When Queue 1 is programmed for AV this field configures the scheduling algorithm for this queue: This bit when set indicates credit based shaper algorithm (CBS) is selected for Queue 1 traffic. When reset strict priority is.." "CBS Algorithm is disabled,CBS Algorithm is enabled" newline rbitfld.long 0x0 0.--1. "RESERVED_1_0,Reserved." "0,1,2,3" rgroup.long 0x14++0x3 line.long 0x0 "MTL_TXQ3_ETS_STATUS,The Queue 3 ETS Status register provides the average traffic transmitted in Queue 3." hexmask.long.byte 0x0 24.--31. 1. "RESERVED_31_24,Reserved." newline hexmask.long.tbyte 0x0 0.--23. 1. "ABS,Average Bits per Slot This field contains the average transmitted bits per slot. If AV operation is enabled this field is computed over number of slots programmed in the SLC field of MTL_TxQ[n]_ETS_CONTROL register. The maximum value of this field.." group.long 0x18++0xF line.long 0x0 "MTL_TXQ3_QUANTUM_WEIGHT,The Queue 3 idleSlopeCredit. Quantum or Weights register provides the average traffic transmitted in Queue 3." hexmask.long.word 0x0 21.--31. 1. "RESERVED_31_21,Reserved." newline hexmask.long.tbyte 0x0 0.--20. 1. "ISCQW,idleSlopeCredit Quantum or Weights - idleSlopeCredit When AV feature is enabled this field contains the idleSlopeCredit value required for the credit-based shaper algorithm for Queue 1. This is the rate of change of credit in bits per cycle (40.." line.long 0x4 "MTL_TXQ3_SENDSLOPECREDIT,The sendSlopeCredit register contains the sendSlope credit value required for the credit-based shaper algorithm for the Queue." hexmask.long.tbyte 0x4 14.--31. 1. "RESERVED_31_14,Reserved." newline hexmask.long.word 0x4 0.--13. 1. "SSC,sendSlopeCredit Value When AV operation is enabled this field contains the sendSlopeCredit value required for credit-based shaper algorithm for Queue 1. This is the rate of change of credit in bits per cycle (40 ns 8 ns and 3.2 ns for 100 Mbps.." line.long 0x8 "MTL_TXQ3_HICREDIT,The hiCredit register contains the hiCredit value required for the credit-based shaper algorithm for the Queue." rbitfld.long 0x8 29.--31. "RESERVED_31_29,Reserved." "0,1,2,3,4,5,6,7" newline hexmask.long 0x8 0.--28. 1. "HC,hiCredit Value When the AV feature is enabled this field contains the hiCredit value required for the credit-based shaper algorithm. This is the maximum value that can be accumulated in the credit parameter. This is specified in bits scaled by 1 024." line.long 0xC "MTL_TXQ3_LOCREDIT,The loCredit register contains the loCredit value required for the credit-based shaper algorithm for the Queue." rbitfld.long 0xC 29.--31. "RESERVED_31_29,Reserved." "0,1,2,3,4,5,6,7" newline hexmask.long 0xC 0.--28. 1. "LC,loCredit Value When AV operation is enabled this field contains the loCredit value required for the credit-based shaper algorithm. This is the minimum value that can be accumulated in the credit parameter. This is specified in bits scaled by 1 024." group.long 0x2C++0x7 line.long 0x0 "MTL_Q3_INTERRUPT_CONTROL_STATUS,This register contains the interrupt enable and status bits for the queue 3 interrupts." hexmask.long.byte 0x0 25.--31. 1. "RESERVED_31_25,Reserved." newline bitfld.long 0x0 24. "RXOIE,Receive Queue Overflow Interrupt Enable When this bit is set the Receive Queue Overflow interrupt is enabled. When this bit is reset the Receive Queue Overflow interrupt is disabled. 0x0: Receive Queue Overflow Interrupt is disabled 0x1: Receive.." "Receive Queue Overflow Interrupt is disabled,Receive Queue Overflow Interrupt is enabled" newline hexmask.long.byte 0x0 17.--23. 1. "RESERVED_23_17,Reserved." newline bitfld.long 0x0 16. "RXOVFIS,Receive Queue Overflow Interrupt Status This bit indicates that the Receive Queue had an overflow while receiving the packet. If a partial packet is transferred to the application the overflow status is set in RDES3[21]. This bit is cleared when.." "Receive Queue Overflow Interrupt Status not..,Receive Queue Overflow Interrupt Status detected" newline hexmask.long.byte 0x0 10.--15. 1. "RESERVED_15_10,Reserved." newline bitfld.long 0x0 9. "ABPSIE,Average Bits Per Slot Interrupt Enable When this bit is set the MAC asserts the sbd_intr_o or mci_intr_o interrupt when the average bits per slot status is updated. When this bit is cleared the interrupt is not asserted for such an event. 0x0:.." "Average Bits Per Slot Interrupt is disabled,Average Bits Per Slot Interrupt is enabled" newline bitfld.long 0x0 8. "TXUIE,Transmit Queue Underflow Interrupt Enable When this bit is set the Transmit Queue Underflow interrupt is enabled. When this bit is reset the Transmit Queue Underflow interrupt is disabled. 0x0: Transmit Queue Underflow Interrupt Status is.." "Transmit Queue Underflow Interrupt Status is..,Transmit Queue Underflow Interrupt Status is.." newline hexmask.long.byte 0x0 2.--7. 1. "RESERVED_7_2,Reserved." newline bitfld.long 0x0 1. "ABPSIS,Average Bits Per Slot Interrupt Status When set this bit indicates that the MAC has updated the ABS value. This bit is cleared when the application writes 1 to this bit. Access restriction applies. Self-set to 1 on internal event. Setting 1.." "Average Bits Per Slot Interrupt Status not..,Average Bits Per Slot Interrupt Status detected" newline bitfld.long 0x0 0. "TXUNFIS,Transmit Queue Underflow Interrupt Status This bit indicates that the Transmit Queue had an underflow while transmitting the packet. Transmission is suspended and an Underflow Error TDES3[2] is set. This bit is cleared when the application writes.." "Transmit Queue Underflow Interrupt Status not..,Transmit Queue Underflow Interrupt Status detected" line.long 0x4 "MTL_RXQ3_OPERATION_MODE,The Queue 3 Receive Operation Mode register establishes the Receive queue operating modes and command. The RFA and RFD fields are not backward compatible with the RFA and RFD fields of 4.00a release" hexmask.long.byte 0x4 25.--31. 1. "RESERVED_31_Y,Reserved." newline hexmask.long.byte 0x4 20.--24. 1. "RQS,Receive Queue Size This field indicates the size of the allocated Receive queues in blocks of 256 bytes. The RQS field is read-write only if the number of Rx Queues more than one the reset value is 0x0 and indicates size of 256 bytes. When the.." newline rbitfld.long 0x4 18.--19. "RESERVED_19_Y,Reserved." "0,1,2,3" newline hexmask.long.byte 0x4 14.--17. 1. "RFD,Threshold for Deactivating Flow Control (in half-duplex and full-duplex modes) These bits control the threshold (fill-level of Rx queue) at which the flow control is de-asserted after activation: - 0: Full minus 1 KB that is FULL 1 KB - 1: Full.." newline rbitfld.long 0x4 12.--13. "RESERVED_13_Y,Reserved." "0,1,2,3" newline hexmask.long.byte 0x4 8.--11. 1. "RFA,Threshold for Activating Flow Control (in half-duplex and full-duplex These bits control the threshold (fill-level of Rx queue) at which the flow control is activated: For more information on encoding for this field see RFD." newline bitfld.long 0x4 7. "EHFC,Enable Hardware Flow Control When this bit is set the flow control signal operation based on the fill-level of Rx queue is enabled. When reset the flow control operation is disabled. 0x0: Hardware Flow Control is disabled 0x1: Hardware Flow.." "Hardware Flow Control is disabled,Hardware Flow Control is enabled" newline bitfld.long 0x4 6. "DIS_TCP_EF,Disable Dropping of TCP/IP Checksum Error Packets When this bit is set the MAC does not drop the packets which only have the errors detected by the Receive Checksum Offload engine. Such packets have errors only in the encapsulated payload." "Dropping of TCP/IP Checksum Error Packets is..,Dropping of TCP/IP Checksum Error Packets is.." newline bitfld.long 0x4 5. "RSF,Receive Queue Store and Forward When this bit is set the DWC_ether_qos reads a packet from the Rx queue only after the complete packet has been written to it ignoring the RTC field of this register. When this bit is reset the Rx queue operates in.." "Receive Queue Store and Forward is disabled,Receive Queue Store and Forward is enabled" newline bitfld.long 0x4 4. "FEP,Forward Error Packets When this bit is reset the Rx queue drops packets with error status (CRC error GMII_ER watchdog timeout or overflow). However if the start byte (write) pointer of a packet is already transferred to the read controller side.." "Forward Error Packets is disabled,Forward Error Packets is enabled" newline bitfld.long 0x4 3. "FUP,Forward Undersized Good Packets When this bit is set the Rx queue forwards the undersized good packets (packets with no error and length less than 64 bytes) including pad-bytes and CRC. When this bit is reset the Rx queue drops all packets of less.." "Forward Undersized Good Packets is disabled,Forward Undersized Good Packets is enabled" newline rbitfld.long 0x4 2. "RESERVED_2,Reserved." "0,1" newline bitfld.long 0x4 0.--1. "RTC,Receive Queue Threshold Control These bits control the threshold level of the MTL Rx queue (in bytes): The received packet is transferred to the application or DMA when the packet size within the MTL Rx queue is larger than the threshold. In addition.." "0,1,2,3" rgroup.long 0x34++0x7 line.long 0x0 "MTL_RXQ3_MISSED_PACKET_OVERFLOW_CNT,The Queue 3 Missed Packet and Overflow Counter register contains the counter for packets missed because of Receive queue packet flush and packets discarded because of Receive queue overflow." hexmask.long.byte 0x0 28.--31. 1. "RESERVED_31_28,Reserved." newline bitfld.long 0x0 27. "MISCNTOVF,Missed Packet Counter Overflow Bit When set this bit indicates that the Rx Queue Missed Packet Counter crossed the maximum limit. Access restriction applies. Clears on read. Self-set to 1 on internal event. 0x1: Missed Packet Counter overflow.." "Missed Packet Counter overflow not detected,Missed Packet Counter overflow detected" newline hexmask.long.word 0x0 16.--26. 1. "MISPKTCNT,Missed Packet Counter This field indicates the number of packets missed by the DWC_ether_qos because the application asserted ari_pkt_flush_i[] for this queue. This counter is reset when this register is read with mci_be_i[0] at 1b1. This.." newline hexmask.long.byte 0x0 12.--15. 1. "RESERVED_15_12,Reserved." newline bitfld.long 0x0 11. "OVFCNTOVF,Overflow Counter Overflow Bit When set this bit indicates that the Rx Queue Overflow Packet Counter field crossed the maximum limit. Access restriction applies. Clears on read. Self-set to 1 on internal event. 0x1: Overflow Counter overflow.." "Overflow Counter overflow not detected,Overflow Counter overflow detected" newline hexmask.long.word 0x0 0.--10. 1. "OVFPKTCNT,Overflow Packet Counter This field indicates the number of packets discarded by the DWC_ether_qos because of Receive queue overflow. This counter is incremented each time the DWC_ether_qos discards an incoming packet because of overflow. This.." line.long 0x4 "MTL_RXQ3_DEBUG,The Queue 3 Receive Debug register gives the debug status of various blocks related to the Receive queue." bitfld.long 0x4 30.--31. "RESERVED_31_30,Reserved." "0,1,2,3" newline hexmask.long.word 0x4 16.--29. 1. "PRXQ,Number of Packets in Receive Queue This field indicates the current number of packets in the Rx Queue. The theoretical maximum value for this field is 256KB/16B = 16K Packets that is Max_Queue_Size/Min_Packet_Size." newline hexmask.long.word 0x4 6.--15. 1. "RESERVED_15_6,Reserved." newline bitfld.long 0x4 4.--5. "RXQSTS,MTL Rx Queue Fill-Level Status This field gives the status of the fill-level of the Rx Queue: 0x2: Rx Queue fill-level above flow-control activate threshold 0x1: Rx Queue fill-level below flow-control deactivate threshold 0x0: Rx Queue empty 0x3:.." "Rx Queue empty,Rx Queue fill-level below flow-control..,Rx Queue fill-level above flow-control activate..,Rx Queue full" newline bitfld.long 0x4 3. "RESERVED_3,Reserved." "0,1" newline bitfld.long 0x4 1.--2. "RRCSTS,MTL Rx Queue Read Controller State This field gives the state of the Rx queue Read controller: 0x3: Flushing the packet data and status 0x0: Idle state 0x1: Reading packet data 0x2: Reading packet status (or timestamp)" "Idle state,Reading packet data,Reading packet status,Flushing the packet data and status" newline bitfld.long 0x4 0. "RWCSTS,MTL Rx Queue Write Controller Active Status When high this bit indicates that the MTL Rx queue Write controller is active and it is transferring a received packet to the Rx Queue. 0x1: MTL Rx Queue Write Controller Active Status detected 0x0:.." "MTL Rx Queue Write Controller Active Status not..,MTL Rx Queue Write Controller Active Status.." group.long 0x3C++0x3 line.long 0x0 "MTL_RXQ3_CONTROL,The Queue Receive Control register controls the receive arbitration and passing of received packets to the application." hexmask.long 0x0 4.--31. 1. "RESERVED_31_4,Reserved." newline bitfld.long 0x0 3. "RXQ_FRM_ARBIT,Receive Queue Packet Arbitration When this bit is set the DWC_ether_qos drives the packet data to the ARI interface such that the entire packet data of currently-selected queue is transmitted before switching to other queue. When this bit.." "Receive Queue Packet Arbitration is disabled,Receive Queue Packet Arbitration is enabled" newline bitfld.long 0x0 0.--2. "RXQ_WEGT,Receive Queue Weight This field indicates the weight assigned to the Rx Queue 0. The weight is used as the number of continuous PBL or packets requests (depending on the RXQ_FRM_ARBIT) allocated to the queue in one arbitration cycle." "0,1,2,3,4,5,6,7" tree.end tree "EQOS_MTL_Q4" group.long 0x0++0x3 line.long 0x0 "MTL_TXQ4_OPERATION_MODE,The Queue 4 Transmit Operation Mode register establishes the Transmit queue operating modes and commands." hexmask.long.word 0x0 21.--31. 1. "RESERVED_31_Y,Reserved." newline hexmask.long.byte 0x0 16.--20. 1. "TQS,Transmit Queue Size This field indicates the size of the allocated Transmit queues in blocks of 256 bytes. The TQS field is read-write only if the number of Tx Queues more than one the reset value is 0x0 and indicates size of 256 bytes. When the.." newline hexmask.long.word 0x0 7.--15. 1. "RESERVED_15_7,Reserved." newline bitfld.long 0x0 4.--6. "TTC,Transmit Threshold Control These bits control the threshold level of the MTL Tx Queue. The transmission starts when the packet size within the MTL Tx Queue is larger than the threshold. In addition full packets with length less than the threshold.." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 2.--3. "TXQEN,Transmit Queue Enable This field is used to enable/disable the transmit queue 0. - 2'b00: Not enabled - 2'b01: Enable in AV mode - 2'b10: Enabled - 2'b11: Reserved Note: In multiple Tx queues configuration all the queues are disabled by default." "Not enabled,Enable in AV mode,Enabled,Reserved" newline bitfld.long 0x0 1. "TSF,Transmit Store and Forward When this bit is set the transmission starts when a full packet resides in the MTL Tx queue. When this bit is set the TTC values specified in Bits[6:4] of this register are ignored. This bit should be changed only when.." "Transmit Store and Forward is disabled,Transmit Store and Forward is enabled" newline bitfld.long 0x0 0. "FTQ,Flush Transmit Queue When this bit is set the Tx queue controller logic is reset to its default values. Therefore all the data in the Tx queue is lost or flushed. This bit is internally reset when the flushing operation is complete. Until this bit.." "Flush Transmit Queue is disabled,Flush Transmit Queue is enabled" rgroup.long 0x4++0x7 line.long 0x0 "MTL_TXQ4_UNDERFLOW,The Queue 4 Underflow Counter register contains the counter for packets aborted because of Transmit queue underflow and packets missed because of Receive queue packet flush" hexmask.long.tbyte 0x0 12.--31. 1. "RESERVED_31_12,Reserved." newline bitfld.long 0x0 11. "UFCNTOVF,Overflow Bit for Underflow Packet Counter This bit is set every time the Tx queue Underflow Packet Counter field overflows that is it has crossed the maximum count. In such a scenario the overflow packet counter is reset to all-zeros and this.." "Overflow not detected for Underflow Packet Counter,Overflow detected for Underflow Packet Counter" newline hexmask.long.word 0x0 0.--10. 1. "UFFRMCNT,Underflow Packet Counter This field indicates the number of packets aborted by the controller because of Tx Queue Underflow. This counter is incremented each time the MAC aborts outgoing packet because of underflow. The counter is cleared when.." line.long 0x4 "MTL_TXQ4_DEBUG,The Queue 4 Transmit Debug register gives the debug status of various blocks related to the Transmit queue." hexmask.long.word 0x4 23.--31. 1. "RESERVED_31_23,Reserved." newline bitfld.long 0x4 20.--22. "STXSTSF,Number of Status Words in Tx Status FIFO of Queue This field indicates the current number of status in the Tx Status FIFO of this queue. When the DTXSTS bit of MTL_Operation_Mode register is set to 1 this field does not reflect the number of.." "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 19. "RESERVED_19,Reserved." "0,1" newline bitfld.long 0x4 16.--18. "PTXQ,Number of Packets in the Transmit Queue This field indicates the current number of packets in the Tx Queue. When the DTXSTS bit of MTL_Operation_Mode register is set to 1 this field does not reflect the number of packets in the Transmit queue." "0,1,2,3,4,5,6,7" newline hexmask.long.word 0x4 6.--15. 1. "RESERVED_15_6,Reserved." newline bitfld.long 0x4 5. "TXSTSFSTS,MTL Tx Status FIFO Full Status When high this bit indicates that the MTL Tx Status FIFO is full. Therefore the MTL cannot accept any more packets for transmission. 0x1: MTL Tx Status FIFO Full status is detected 0x0: MTL Tx Status FIFO Full.." "MTL Tx Status FIFO Full status is not detected,MTL Tx Status FIFO Full status is detected" newline bitfld.long 0x4 4. "TXQSTS,MTL Tx Queue Not Empty Status When this bit is high it indicates that the MTL Tx Queue is not empty and some data is left for transmission. 0x1: MTL Tx Queue Not Empty status is detected 0x0: MTL Tx Queue Not Empty status is not detected" "MTL Tx Queue Not Empty status is not detected,MTL Tx Queue Not Empty status is detected" newline bitfld.long 0x4 3. "TWCSTS,MTL Tx Queue Write Controller Status When high this bit indicates that the MTL Tx Queue Write Controller is active and it is transferring the data to the Tx Queue. 0x1: MTL Tx Queue Write Controller status is detected 0x0: MTL Tx Queue Write.." "MTL Tx Queue Write Controller status is not..,MTL Tx Queue Write Controller status is detected" newline bitfld.long 0x4 1.--2. "TRCSTS,MTL Tx Queue Read Controller Status This field indicates the state of the Tx Queue Read Controller: 0x3: Flushing the Tx queue because of the Packet Abort request from the MAC 0x0: Idle state 0x1: Read state (transferring data to the MAC.." "Idle state,Read state,Waiting for pending Tx Status from the MAC..,Flushing the Tx queue because of the Packet.." newline bitfld.long 0x4 0. "TXQPAUSED,Transmit Queue in Pause When this bit is high and the Rx flow control is enabled it indicates that the Tx Queue is in the Pause condition (in the full-duplex only mode) because of the following: - Reception of the PFC packet for the priorities.." "Transmit Queue in Pause status is not detected,Transmit Queue in Pause status is detected" group.long 0x10++0x3 line.long 0x0 "MTL_TXQ4_ETS_CONTROL,The Queue ETS Control register controls the enhanced transmission selection operation." hexmask.long 0x0 7.--31. 1. "RESERVED_31_7,Reserved." newline bitfld.long 0x0 4.--6. "SLC,Slot Count If the credit-based shaper algorithm is enabled the software can program the number of slots (of duration programmed in DMA_CH[n]_Slot_Interval register) over which the average transmitted bits per slot provided in the.." "?,?,?,?,?,Reserved,?,?" newline bitfld.long 0x0 3. "CC,Credit Control When this bit is set the accumulated credit parameter in the credit-based shaper algorithm logic is not reset to zero when there is positive credit and no packet to transmit in Channel 1. The credit accumulates even when there is no.." "Credit Control is disabled,Credit Control is enabled" newline bitfld.long 0x0 2. "AVALG,AV Algorithm When Queue 1 is programmed for AV this field configures the scheduling algorithm for this queue: This bit when set indicates credit based shaper algorithm (CBS) is selected for Queue 1 traffic. When reset strict priority is.." "CBS Algorithm is disabled,CBS Algorithm is enabled" newline rbitfld.long 0x0 0.--1. "RESERVED_1_0,Reserved." "0,1,2,3" rgroup.long 0x14++0x3 line.long 0x0 "MTL_TXQ4_ETS_STATUS,The Queue 4 ETS Status register provides the average traffic transmitted in Queue 4." hexmask.long.byte 0x0 24.--31. 1. "RESERVED_31_24,Reserved." newline hexmask.long.tbyte 0x0 0.--23. 1. "ABS,Average Bits per Slot This field contains the average transmitted bits per slot. If AV operation is enabled this field is computed over number of slots programmed in the SLC field of MTL_TxQ[n]_ETS_CONTROL register. The maximum value of this field.." group.long 0x18++0xF line.long 0x0 "MTL_TXQ4_QUANTUM_WEIGHT,The Queue 4 idleSlopeCredit. Quantum or Weights register provides the average traffic transmitted in Queue 4." hexmask.long.word 0x0 21.--31. 1. "RESERVED_31_21,Reserved." newline hexmask.long.tbyte 0x0 0.--20. 1. "ISCQW,idleSlopeCredit Quantum or Weights - idleSlopeCredit When AV feature is enabled this field contains the idleSlopeCredit value required for the credit-based shaper algorithm for Queue 1. This is the rate of change of credit in bits per cycle (40.." line.long 0x4 "MTL_TXQ4_SENDSLOPECREDIT,The sendSlopeCredit register contains the sendSlope credit value required for the credit-based shaper algorithm for the Queue." hexmask.long.tbyte 0x4 14.--31. 1. "RESERVED_31_14,Reserved." newline hexmask.long.word 0x4 0.--13. 1. "SSC,sendSlopeCredit Value When AV operation is enabled this field contains the sendSlopeCredit value required for credit-based shaper algorithm for Queue 1. This is the rate of change of credit in bits per cycle (40 ns 8 ns and 3.2 ns for 100 Mbps.." line.long 0x8 "MTL_TXQ4_HICREDIT,The hiCredit register contains the hiCredit value required for the credit-based shaper algorithm for the Queue." rbitfld.long 0x8 29.--31. "RESERVED_31_29,Reserved." "0,1,2,3,4,5,6,7" newline hexmask.long 0x8 0.--28. 1. "HC,hiCredit Value When the AV feature is enabled this field contains the hiCredit value required for the credit-based shaper algorithm. This is the maximum value that can be accumulated in the credit parameter. This is specified in bits scaled by 1 024." line.long 0xC "MTL_TXQ4_LOCREDIT,The loCredit register contains the loCredit value required for the credit-based shaper algorithm for the Queue." rbitfld.long 0xC 29.--31. "RESERVED_31_29,Reserved." "0,1,2,3,4,5,6,7" newline hexmask.long 0xC 0.--28. 1. "LC,loCredit Value When AV operation is enabled this field contains the loCredit value required for the credit-based shaper algorithm. This is the minimum value that can be accumulated in the credit parameter. This is specified in bits scaled by 1 024." group.long 0x2C++0x7 line.long 0x0 "MTL_Q4_INTERRUPT_CONTROL_STATUS,This register contains the interrupt enable and status bits for the queue 4 interrupts." hexmask.long.byte 0x0 25.--31. 1. "RESERVED_31_25,Reserved." newline bitfld.long 0x0 24. "RXOIE,Receive Queue Overflow Interrupt Enable When this bit is set the Receive Queue Overflow interrupt is enabled. When this bit is reset the Receive Queue Overflow interrupt is disabled. 0x0: Receive Queue Overflow Interrupt is disabled 0x1: Receive.." "Receive Queue Overflow Interrupt is disabled,Receive Queue Overflow Interrupt is enabled" newline hexmask.long.byte 0x0 17.--23. 1. "RESERVED_23_17,Reserved." newline bitfld.long 0x0 16. "RXOVFIS,Receive Queue Overflow Interrupt Status This bit indicates that the Receive Queue had an overflow while receiving the packet. If a partial packet is transferred to the application the overflow status is set in RDES3[21]. This bit is cleared when.." "Receive Queue Overflow Interrupt Status not..,Receive Queue Overflow Interrupt Status detected" newline hexmask.long.byte 0x0 10.--15. 1. "RESERVED_15_10,Reserved." newline bitfld.long 0x0 9. "ABPSIE,Average Bits Per Slot Interrupt Enable When this bit is set the MAC asserts the sbd_intr_o or mci_intr_o interrupt when the average bits per slot status is updated. When this bit is cleared the interrupt is not asserted for such an event. 0x0:.." "Average Bits Per Slot Interrupt is disabled,Average Bits Per Slot Interrupt is enabled" newline bitfld.long 0x0 8. "TXUIE,Transmit Queue Underflow Interrupt Enable When this bit is set the Transmit Queue Underflow interrupt is enabled. When this bit is reset the Transmit Queue Underflow interrupt is disabled. 0x0: Transmit Queue Underflow Interrupt Status is.." "Transmit Queue Underflow Interrupt Status is..,Transmit Queue Underflow Interrupt Status is.." newline hexmask.long.byte 0x0 2.--7. 1. "RESERVED_7_2,Reserved." newline bitfld.long 0x0 1. "ABPSIS,Average Bits Per Slot Interrupt Status When set this bit indicates that the MAC has updated the ABS value. This bit is cleared when the application writes 1 to this bit. Access restriction applies. Self-set to 1 on internal event. Setting 1.." "Average Bits Per Slot Interrupt Status not..,Average Bits Per Slot Interrupt Status detected" newline bitfld.long 0x0 0. "TXUNFIS,Transmit Queue Underflow Interrupt Status This bit indicates that the Transmit Queue had an underflow while transmitting the packet. Transmission is suspended and an Underflow Error TDES3[2] is set. This bit is cleared when the application writes.." "Transmit Queue Underflow Interrupt Status not..,Transmit Queue Underflow Interrupt Status detected" line.long 0x4 "MTL_RXQ4_OPERATION_MODE,The Queue 4 Receive Operation Mode register establishes the Receive queue operating modes and command. The RFA and RFD fields are not backward compatible with the RFA and RFD fields of 4.00a release" hexmask.long.byte 0x4 25.--31. 1. "RESERVED_31_Y,Reserved." newline hexmask.long.byte 0x4 20.--24. 1. "RQS,Receive Queue Size This field indicates the size of the allocated Receive queues in blocks of 256 bytes. The RQS field is read-write only if the number of Rx Queues more than one the reset value is 0x0 and indicates size of 256 bytes. When the.." newline rbitfld.long 0x4 18.--19. "RESERVED_19_Y,Reserved." "0,1,2,3" newline hexmask.long.byte 0x4 14.--17. 1. "RFD,Threshold for Deactivating Flow Control (in half-duplex and full-duplex modes) These bits control the threshold (fill-level of Rx queue) at which the flow control is de-asserted after activation: - 0: Full minus 1 KB that is FULL 1 KB - 1: Full.." newline rbitfld.long 0x4 12.--13. "RESERVED_13_Y,Reserved." "0,1,2,3" newline hexmask.long.byte 0x4 8.--11. 1. "RFA,Threshold for Activating Flow Control (in half-duplex and full-duplex These bits control the threshold (fill-level of Rx queue) at which the flow control is activated: For more information on encoding for this field see RFD." newline bitfld.long 0x4 7. "EHFC,Enable Hardware Flow Control When this bit is set the flow control signal operation based on the fill-level of Rx queue is enabled. When reset the flow control operation is disabled. 0x0: Hardware Flow Control is disabled 0x1: Hardware Flow.." "Hardware Flow Control is disabled,Hardware Flow Control is enabled" newline bitfld.long 0x4 6. "DIS_TCP_EF,Disable Dropping of TCP/IP Checksum Error Packets When this bit is set the MAC does not drop the packets which only have the errors detected by the Receive Checksum Offload engine. Such packets have errors only in the encapsulated payload." "Dropping of TCP/IP Checksum Error Packets is..,Dropping of TCP/IP Checksum Error Packets is.." newline bitfld.long 0x4 5. "RSF,Receive Queue Store and Forward When this bit is set the DWC_ether_qos reads a packet from the Rx queue only after the complete packet has been written to it ignoring the RTC field of this register. When this bit is reset the Rx queue operates in.." "Receive Queue Store and Forward is disabled,Receive Queue Store and Forward is enabled" newline bitfld.long 0x4 4. "FEP,Forward Error Packets When this bit is reset the Rx queue drops packets with error status (CRC error GMII_ER watchdog timeout or overflow). However if the start byte (write) pointer of a packet is already transferred to the read controller side.." "Forward Error Packets is disabled,Forward Error Packets is enabled" newline bitfld.long 0x4 3. "FUP,Forward Undersized Good Packets When this bit is set the Rx queue forwards the undersized good packets (packets with no error and length less than 64 bytes) including pad-bytes and CRC. When this bit is reset the Rx queue drops all packets of less.." "Forward Undersized Good Packets is disabled,Forward Undersized Good Packets is enabled" newline rbitfld.long 0x4 2. "RESERVED_2,Reserved." "0,1" newline bitfld.long 0x4 0.--1. "RTC,Receive Queue Threshold Control These bits control the threshold level of the MTL Rx queue (in bytes): The received packet is transferred to the application or DMA when the packet size within the MTL Rx queue is larger than the threshold. In addition.." "0,1,2,3" rgroup.long 0x34++0x7 line.long 0x0 "MTL_RXQ4_MISSED_PACKET_OVERFLOW_CNT,The Queue 4 Missed Packet and Overflow Counter register contains the counter for packets missed because of Receive queue packet flush and packets discarded because of Receive queue overflow." hexmask.long.byte 0x0 28.--31. 1. "RESERVED_31_28,Reserved." newline bitfld.long 0x0 27. "MISCNTOVF,Missed Packet Counter Overflow Bit When set this bit indicates that the Rx Queue Missed Packet Counter crossed the maximum limit. Access restriction applies. Clears on read. Self-set to 1 on internal event. 0x1: Missed Packet Counter overflow.." "Missed Packet Counter overflow not detected,Missed Packet Counter overflow detected" newline hexmask.long.word 0x0 16.--26. 1. "MISPKTCNT,Missed Packet Counter This field indicates the number of packets missed by the DWC_ether_qos because the application asserted ari_pkt_flush_i[] for this queue. This counter is reset when this register is read with mci_be_i[0] at 1b1. This.." newline hexmask.long.byte 0x0 12.--15. 1. "RESERVED_15_12,Reserved." newline bitfld.long 0x0 11. "OVFCNTOVF,Overflow Counter Overflow Bit When set this bit indicates that the Rx Queue Overflow Packet Counter field crossed the maximum limit. Access restriction applies. Clears on read. Self-set to 1 on internal event. 0x1: Overflow Counter overflow.." "Overflow Counter overflow not detected,Overflow Counter overflow detected" newline hexmask.long.word 0x0 0.--10. 1. "OVFPKTCNT,Overflow Packet Counter This field indicates the number of packets discarded by the DWC_ether_qos because of Receive queue overflow. This counter is incremented each time the DWC_ether_qos discards an incoming packet because of overflow. This.." line.long 0x4 "MTL_RXQ4_DEBUG,The Queue 4 Receive Debug register gives the debug status of various blocks related to the Receive queue." bitfld.long 0x4 30.--31. "RESERVED_31_30,Reserved." "0,1,2,3" newline hexmask.long.word 0x4 16.--29. 1. "PRXQ,Number of Packets in Receive Queue This field indicates the current number of packets in the Rx Queue. The theoretical maximum value for this field is 256KB/16B = 16K Packets that is Max_Queue_Size/Min_Packet_Size." newline hexmask.long.word 0x4 6.--15. 1. "RESERVED_15_6,Reserved." newline bitfld.long 0x4 4.--5. "RXQSTS,MTL Rx Queue Fill-Level Status This field gives the status of the fill-level of the Rx Queue: 0x2: Rx Queue fill-level above flow-control activate threshold 0x1: Rx Queue fill-level below flow-control deactivate threshold 0x0: Rx Queue empty 0x3:.." "Rx Queue empty,Rx Queue fill-level below flow-control..,Rx Queue fill-level above flow-control activate..,Rx Queue full" newline bitfld.long 0x4 3. "RESERVED_3,Reserved." "0,1" newline bitfld.long 0x4 1.--2. "RRCSTS,MTL Rx Queue Read Controller State This field gives the state of the Rx queue Read controller: 0x3: Flushing the packet data and status 0x0: Idle state 0x1: Reading packet data 0x2: Reading packet status (or timestamp)" "Idle state,Reading packet data,Reading packet status,Flushing the packet data and status" newline bitfld.long 0x4 0. "RWCSTS,MTL Rx Queue Write Controller Active Status When high this bit indicates that the MTL Rx queue Write controller is active and it is transferring a received packet to the Rx Queue. 0x1: MTL Rx Queue Write Controller Active Status detected 0x0:.." "MTL Rx Queue Write Controller Active Status not..,MTL Rx Queue Write Controller Active Status.." group.long 0x3C++0x3 line.long 0x0 "MTL_RXQ4_CONTROL,The Queue Receive Control register controls the receive arbitration and passing of received packets to the application." hexmask.long 0x0 4.--31. 1. "RESERVED_31_4,Reserved." newline bitfld.long 0x0 3. "RXQ_FRM_ARBIT,Receive Queue Packet Arbitration When this bit is set the DWC_ether_qos drives the packet data to the ARI interface such that the entire packet data of currently-selected queue is transmitted before switching to other queue. When this bit.." "Receive Queue Packet Arbitration is disabled,Receive Queue Packet Arbitration is enabled" newline bitfld.long 0x0 0.--2. "RXQ_WEGT,Receive Queue Weight This field indicates the weight assigned to the Rx Queue 0. The weight is used as the number of continuous PBL or packets requests (depending on the RXQ_FRM_ARBIT) allocated to the queue in one arbitration cycle." "0,1,2,3,4,5,6,7" tree.end tree "EQOS_DMA" group.long 0x0++0x7 line.long 0x0 "DMA_MODE,The Bus Mode register establishes the bus operating modes for the DMA." hexmask.long.word 0x0 18.--31. 1. "RESERVED_31_18,Reserved." newline bitfld.long 0x0 16.--17. "INTM,Interrupt Mode This field defines the interrupt mode of DWC_ether_qos. The behavior of the following outputs changes depending on the following settings: - sbd_perch_tx_intr_o[] (Transmit Per Channel Interrupt) - sbd_perch_rx_intr_o[] (Receive Per.." "See above description,See above description,See above description,Reserved" newline rbitfld.long 0x0 15. "RESERVED_15,Reserved." "0,1" newline rbitfld.long 0x0 12.--14. "RESERVED_PR,Reserved." "0,1,2,3,4,5,6,7" newline rbitfld.long 0x0 11. "RESERVED_TXPR,Reserved." "0,1" newline rbitfld.long 0x0 10. "RESERVED_SCSW,Reserved." "0,1" newline rbitfld.long 0x0 9. "RESERVED_ARBC,Reserved." "0,1" newline bitfld.long 0x0 8. "DSPW,Descriptor Posted Write When this bit is set to 0 the descriptor writes are always non-posted. When this bit is set to 1 the descriptor writes are non-posted only when IOC (Interrupt on completion) is set in last descriptor otherwise the.." "Descriptor Posted Write is disabled,Descriptor Posted Write is enabled" newline rbitfld.long 0x0 5.--7. "RESERVED_7_5,Reserved." "0,1,2,3,4,5,6,7" newline rbitfld.long 0x0 2.--4. "RESERVED_TAA,Reserved." "0,1,2,3,4,5,6,7" newline rbitfld.long 0x0 1. "RESERVED_DA,Reserved." "0,1" newline bitfld.long 0x0 0. "SWR,Software Reset When this bit is set the MAC and the DMA controller reset the logic and all internal registers of the DMA MTL and MAC. This bit is automatically cleared after the reset operation is complete in all DWC_ether_qos clock domains." "Software Reset is disabled,Software Reset is enabled" line.long 0x4 "DMA_SYSBUS_MODE,The System Bus mode register controls the behavior of the AHB or AXI master. It mainly controls burst splitting and number of outstanding requests." bitfld.long 0x4 31. "EN_LPI,Enable Low Power Interface (LPI) When set to 1 this bit enables the LPI mode supported by the EQOS-AXI configuration and accepts the LPI request from the AXI System Clock controller. When set to 0 this bit disables the LPI mode and always denies.." "Low Power Interface,Low Power Interface" newline bitfld.long 0x4 30. "LPI_XIT_PKT,Unlock on Magic Packet or Remote Wake-Up Packet When set to 1 this bit enables the AXI master to come out of the LPI mode only when the magic packet or remote wake-up packet is received. When set to 0 this bit enables the AXI master to come.." "Unlock on Magic Packet or Remote Wake-Up Packet..,Unlock on Magic Packet or Remote Wake-Up Packet.." newline rbitfld.long 0x4 28.--29. "RESERVED_29_Y,Reserved." "0,1,2,3" newline hexmask.long.byte 0x4 24.--27. 1. "WR_OSR_LMT,AXI Maximum Write Outstanding Request Limit This value limits the maximum outstanding request on the AXI write interface. Maximum outstanding requests = WR_OSR_LMT + 1 Note: - Bit 26 is reserved if DWC_ETHER_QOS_AXI_MAX_WR_REQ = 4 - Bit 27 is.." newline hexmask.long.byte 0x4 20.--23. 1. "RESERVED_23_Y,Reserved." newline hexmask.long.byte 0x4 16.--19. 1. "RD_OSR_LMT,AXI Maximum Read Outstanding Request Limit This value limits the maximum outstanding request on the AXI read interface. Maximum outstanding requests = RD_OSR_LMT + 1 Note: - Bit 18 is reserved if parameter DWC_ETHER_QOS_AXI_MAX_RD_REQ = 4 -.." newline rbitfld.long 0x4 15. "RESERVED_RB,Reserved." "0,1" newline rbitfld.long 0x4 14. "RESERVED_MB,Reserved." "0,1" newline bitfld.long 0x4 13. "ONEKBBE,1 KB Boundary Crossing Enable for the EQOS-AXI Master When set the burst transfers performed by the EQOS-AXI master do not cross 1 KB boundary. When reset the burst transfers performed by the EQOS-AXI master do not cross 4 KB boundary. 0x0: 1.." "0,1" newline bitfld.long 0x4 12. "AAL,Address-Aligned Beats When this bit is set to 1 the EQOS-AXI or EQOS-AHB master performs address-aligned burst transfers on Read and Write channels. 0x0: Address-Aligned Beats is disabled 0x1: Address-Aligned Beats is enabled" "Address-Aligned Beats is disabled,Address-Aligned Beats is enabled" newline bitfld.long 0x4 11. "EAME,Enhanced Address Mode Enable. When this bit is set to 1 the DMA master enables the enhanced address mode (40-bit or 48-bit addressing mode). In this mode the DMA engine uses either the 40- or 48-bit address depending on the configuration. 0x0:.." "Enhanced Address Mode is disabled,Enhanced Address Mode is enabled" newline bitfld.long 0x4 10. "AALE,Automatic AXI LPI enable When set to 1 enables the AXI master to enter into LPI state when there is no activity in the DWC_ether_qos for number of system clock cycles programmed in the LPIEI field of AXI_LPI_Entry_Interval register. 0x0: Automatic.." "Automatic AXI LPI is disabled,Automatic AXI LPI is enabled" newline rbitfld.long 0x4 8.--9. "RESERVED_9_8,Reserved." "0,1,2,3" newline bitfld.long 0x4 7. "BLEN256,AXI Burst Length 256 When this bit is set to 1 the EQOS-AXI master can select a burst length of 256 on the AXI interface. 0x0: No effect 0x1: AXI Burst Length 256" "No effect,AXI Burst Length 256" newline bitfld.long 0x4 6. "BLEN128,AXI Burst Length 128 When this bit is set to 1 the EQOS-AXI master can select a burst length of 128 on the AXI interface. 0x0: No effect 0x1: AXI Burst Length 128" "No effect,AXI Burst Length 128" newline bitfld.long 0x4 5. "BLEN64,AXI Burst Length 64 When this bit is set to 1 the EQOS-AXI master can select a burst length of 64 on the AXI interface. 0x0: No effect 0x1: AXI Burst Length 64" "No effect,AXI Burst Length 64" newline bitfld.long 0x4 4. "BLEN32,AXI Burst Length 32 When this bit is set to 1 the EQOS-AXI master can select a burst length of 32 on the AXI interface. 0x0: No effect 0x1: AXI Burst Length 32" "No effect,AXI Burst Length 32" newline bitfld.long 0x4 3. "BLEN16,AXI Burst Length 16 When this bit is set to 1 or the FB bit is set to 0 the EQOS-AXI master can select a burst length of 16 on the AXI interface. When the FB bit is set to 0 setting this bit has no effect. 0x0: No effect 0x1: AXI Burst Length 16" "No effect,AXI Burst Length 16" newline bitfld.long 0x4 2. "BLEN8,AXI Burst Length 8 When this bit is set to 1 or the FB bit is set to 0 the EQOS-AXI master can select a burst length of 8 on the AXI interface. When the FB bit is set to 0 setting this bit has no effect. 0x0: No effect 0x1: AXI Burst Length 8" "No effect,AXI Burst Length 8" newline bitfld.long 0x4 1. "BLEN4,AXI Burst Length 4 When this bit is set to 1 or the FB bit is set to 0 the EQOS-AXI master can select a burst length of 4 on the AXI interface. When the FB bit is set to 0 setting this bit has no effect. 0x0: No effect 0x1: AXI Burst Length 4" "No effect,AXI Burst Length 4" newline bitfld.long 0x4 0. "FB,Fixed Burst Length When this bit is set to 1 the EQOS-AXI master initiates burst transfers of specified lengths as given below. - Burst transfers of fixed burst lengths as indicated by the BLEN256 BLEN128 BLEN64 BLEN32 BLEN16 BLEN8 or BLEN4.." "Fixed Burst Length is disabled,Fixed Burst Length is enabled" rgroup.long 0x8++0xB line.long 0x0 "DMA_INTERRUPT_STATUS,The application reads this Interrupt Status register during interrupt service routine or polling to determine the interrupt status of DMA channels. MTL queues. and the MAC." hexmask.long.word 0x0 18.--31. 1. "RESERVED_31_18,Reserved." newline bitfld.long 0x0 17. "MACIS,MAC Interrupt Status This bit indicates an interrupt event in the MAC. To reset this bit to 1'b0 the software must read the corresponding register in the MAC to get the exact cause of the interrupt and clear its source. 0x1: MAC Interrupt Status.." "MAC Interrupt Status not detected,MAC Interrupt Status detected" newline bitfld.long 0x0 16. "MTLIS,MTL Interrupt Status This bit indicates an interrupt event in the MTL. To reset this bit to 1'b0 the software must read the corresponding register in the MTL to get the exact cause of the interrupt and clear its source. 0x1: MTL Interrupt Status.." "MTL Interrupt Status not detected,MTL Interrupt Status detected" newline hexmask.long.byte 0x0 8.--15. 1. "RESERVED_15_8,Reserved." newline bitfld.long 0x0 7. "RESERVED_DC7IS,Reserved." "0,1" newline bitfld.long 0x0 6. "RESERVED_DC6IS,Reserved." "0,1" newline bitfld.long 0x0 5. "RESERVED_DC5IS,Reserved." "0,1" newline bitfld.long 0x0 4. "DC4IS,DMA Channel 4 Interrupt Status This bit indicates an interrupt event in DMA Channel 4. To reset this bit to 1'b0 the software must read the corresponding register in DMA Channel 4 to get the exact cause of the interrupt and clear its source. 0x1:.." "DMA Channel 4 Interrupt Status not detected,DMA Channel 4 Interrupt Status detected" newline bitfld.long 0x0 3. "DC3IS,DMA Channel 3 Interrupt Status This bit indicates an interrupt event in DMA Channel 3. To reset this bit to 1'b0 the software must read the corresponding register in DMA Channel 3 to get the exact cause of the interrupt and clear its source. 0x1:.." "DMA Channel 3 Interrupt Status not detected,DMA Channel 3 Interrupt Status detected" newline bitfld.long 0x0 2. "DC2IS,DMA Channel 2 Interrupt Status This bit indicates an interrupt event in DMA Channel 2. To reset this bit to 1'b0 the software must read the corresponding register in DMA Channel 2 to get the exact cause of the interrupt and clear its source. 0x1:.." "DMA Channel 2 Interrupt Status not detected,DMA Channel 2 Interrupt Status detected" newline bitfld.long 0x0 1. "DC1IS,DMA Channel 1 Interrupt Status This bit indicates an interrupt event in DMA Channel 1. To reset this bit to 1'b0 the software must read the corresponding register in DMA Channel 1 to get the exact cause of the interrupt and clear its source. 0x1:.." "DMA Channel 1 Interrupt Status not detected,DMA Channel 1 Interrupt Status detected" newline bitfld.long 0x0 0. "DC0IS,DMA Channel 0 Interrupt Status This bit indicates an interrupt event in DMA Channel 0. To reset this bit to 1'b0 the software must read the corresponding register in DMA Channel 0 to get the exact cause of the interrupt and clear its source. 0x1:.." "DMA Channel 0 Interrupt Status not detected,DMA Channel 0 Interrupt Status detected" line.long 0x4 "DMA_DEBUG_STATUS0,The Debug Status 0 register gives the Receive and Transmit process status for DMA Channel 0-Channel 2 for debugging purpose." hexmask.long.byte 0x4 28.--31. 1. "TPS2,DMA Channel 2 Transmit Process State This field indicates the Tx DMA FSM state for Channel 2. The MSB of this field always returns 0. This field does not generate an interrupt. 0x5: Reserved for future use 0x7: Running (Closing Tx Descriptor) 0x1:.." newline hexmask.long.byte 0x4 24.--27. 1. "RPS2,DMA Channel 2 Receive Process State This field indicates the Rx DMA FSM state for Channel 2. The MSB of this field always returns 0. This field does not generate an interrupt. 0x2: Reserved for future use 0x5: Running (Closing the Rx Descriptor).." newline hexmask.long.byte 0x4 20.--23. 1. "TPS1,DMA Channel 1 Transmit Process State This field indicates the Tx DMA FSM state for Channel 1. The MSB of this field always returns 0. This field does not generate an interrupt. 0x5: Reserved for future use 0x7: Running (Closing Tx Descriptor) 0x1:.." newline hexmask.long.byte 0x4 16.--19. 1. "RPS1,DMA Channel 1 Receive Process State This field indicates the Rx DMA FSM state for Channel 1. The MSB of this field always returns 0. This field does not generate an interrupt. 0x2: Reserved for future use 0x5: Running (Closing the Rx Descriptor).." newline hexmask.long.byte 0x4 12.--15. 1. "TPS0,DMA Channel 0 Transmit Process State This field indicates the Tx DMA FSM state for Channel 0. The MSB of this field always returns 0. This field does not generate an interrupt. 0x5: Reserved for future use 0x7: Running (Closing Tx Descriptor) 0x1:.." newline hexmask.long.byte 0x4 8.--11. 1. "RPS0,DMA Channel 0 Receive Process State This field indicates the Rx DMA FSM state for Channel 0. The MSB of this field always returns 0. This field does not generate an interrupt. 0x2: Reserved for future use 0x5: Running (Closing the Rx Descriptor).." newline hexmask.long.byte 0x4 2.--7. 1. "RESERVED_7_2,Reserved." newline bitfld.long 0x4 1. "AXRHSTS,AXI Master Read Channel Status When high this bit indicates that the read channel of the AXI master is active and it is transferring the data. 0x1: AXI Master Read Channel Status detected 0x0: AXI Master Read Channel Status not detected" "AXI Master Read Channel Status not detected,AXI Master Read Channel Status detected" newline bitfld.long 0x4 0. "AXWHSTS,AXI Master Write Channel When high this bit indicates that the write channel of the AXI master is active and it is transferring data. 0x1: AXI Master Write Channel or AHB Master Status detected 0x0: AXI Master Write Channel or AHB Master Status.." "AXI Master Write Channel or AHB Master Status..,AXI Master Write Channel or AHB Master Status.." line.long 0x8 "DMA_DEBUG_STATUS1,The Debug Status1 register gives the Receive and Transmit process status for DMA Channel 3-Channel 6." hexmask.long.byte 0x8 28.--31. 1. "RESERVED_TPS6,Reserved." newline hexmask.long.byte 0x8 24.--27. 1. "RESERVED_RPS6,Reserved." newline hexmask.long.byte 0x8 20.--23. 1. "RESERVED_TPS5,Reserved." newline hexmask.long.byte 0x8 16.--19. 1. "RESERVED_RPS5,Reserved." newline hexmask.long.byte 0x8 12.--15. 1. "TPS4,DMA Channel 4 Transmit Process State This field indicates the Tx DMA FSM state for Channel 4. The MSB of this field always returns 0. This field does not generate an interrupt. 0x5: Reserved for future use 0x7: Running (Closing Tx Descriptor) 0x1:.." newline hexmask.long.byte 0x8 8.--11. 1. "RPS4,DMA Channel 4 Receive Process State This field indicates the Rx DMA FSM state for Channel 4. The MSB of this field always returns 0. This field does not generate an interrupt. 0x2: Reserved for future use 0x5: Running (Closing the Rx Descriptor).." newline hexmask.long.byte 0x8 4.--7. 1. "TPS3,DMA Channel 3 Transmit Process State This field indicates the Tx DMA FSM state for Channel 3. The MSB of this field always returns 0. This field does not generate an interrupt. 0x5: Reserved for future use 0x7: Running (Closing Tx Descriptor) 0x1:.." newline hexmask.long.byte 0x8 0.--3. 1. "RPS3,DMA Channel 3 Receive Process State This field indicates the Rx DMA FSM state for Channel 3. The MSB of this field always returns 0. This field does not generate an interrupt. 0x2: Reserved for future use 0x5: Running (Closing the Rx Descriptor).." group.long 0x20++0xB line.long 0x0 "AXI4_TX_AR_ACE_CONTROL,This register is used to control the AXI4 Cache Coherency Signals for read transactions by all the Transmit DMA channels. The following signals of the AXI4 interface are driven with different values as programmed for corresponding.." hexmask.long.word 0x0 22.--31. 1. "RESERVED_31_22,Reserved." newline bitfld.long 0x0 20.--21. "THD,Transmit DMA First Packet Buffer This field is used to drive ardomain_o[1:0] signal when Transmit DMA is accessing First Buffer of the Packet (First valid buffer with FD being set in the TDES3 of the Descriptor)." "0,1,2,3" newline hexmask.long.byte 0x0 16.--19. 1. "THC,Transmit DMA First Packet Buffer This field is used to drive arcache_o[3:0] signal when Transmit DMA is accessing First Buffer of the Packet (First valid buffer with FD being set in the TDES3 of the Descriptor).." newline rbitfld.long 0x0 14.--15. "RESERVED_15_14,Reserved." "0,1,2,3" newline bitfld.long 0x0 12.--13. "TED,Transmit DMA Extended Packet Buffer This field is used to drive ardomain_o[1:0] signal when Transmit DMA is accessing the extended buffers (when packet is distributed across multiple buffers)." "0,1,2,3" newline hexmask.long.byte 0x0 8.--11. 1. "TEC,Transmit DMA Extended Packet Buffer This field is used to drive arcache_o[3:0] signal when Transmit DMA is accessing the extended buffers (when packet is distributed across multiple buffers)." newline rbitfld.long 0x0 6.--7. "RESERVED_7_6,Reserved." "0,1,2,3" newline bitfld.long 0x0 4.--5. "TDRD,Transmit DMA Read Descriptor Domain Control This field is used to drive ardomain_o[1:0] signal when Transmit DMA engines access the Descriptor." "0,1,2,3" newline hexmask.long.byte 0x0 0.--3. 1. "TDRC,Transmit DMA Read Descriptor Cache Control This field is used to drive arcache_o[3:0] signal when Transmit DMA engines access the Descriptor." line.long 0x4 "AXI4_RX_AW_ACE_CONTROL,This register is used to control the AXI4 Cache Coherency Signals for write transactions by all the Receive DMA channels. The following signals of the AXI4 interface are driven with different values as programmed for corresponding.." rbitfld.long 0x4 30.--31. "RESERVED_31_30,Reserved." "0,1,2,3" newline bitfld.long 0x4 28.--29. "RDD,Receive DMA Buffer Domain Control This field is used to drive the awdomain_o[1:0] signal when Receive DMA is accessing the Buffer when Header and payload are NOT separated." "0,1,2,3" newline hexmask.long.byte 0x4 24.--27. 1. "RDC,Receive DMA Buffer Cache Control This field is used to drive awcache_o[3:0] signal when Receive DMA is accessing the Buffer when Header and payload are NOT separated." newline rbitfld.long 0x4 22.--23. "RESERVED_23_22,Reserved." "0,1,2,3" newline bitfld.long 0x4 20.--21. "RHD,Receive DMA Header Domain Control This field is used to drive awdomain_o[1:0] and signal when Receive DMA is accessing the header Buffer when Header and payload are separated." "0,1,2,3" newline hexmask.long.byte 0x4 16.--19. 1. "RHC,Receive DMA Header Cache Control This field is used to drive awcache_o[3:0] and signal when Receive DMA is accessing the header Buffer when Header and payload are separated." newline rbitfld.long 0x4 14.--15. "RESERVED_15_14,Reserved." "0,1,2,3" newline bitfld.long 0x4 12.--13. "RPD,Receive DMA Payload Domain Control This field is used to drive awdomain_o[1:0] signal when Receive DMA is accessing the Payload Buffer when Header and payload are separated." "0,1,2,3" newline hexmask.long.byte 0x4 8.--11. 1. "RPC,Receive DMA Payload Cache Control This field is used to drive awcache_o[3:0] signal when Receive DMA is accessing the Payload Buffer when Header and payload are separated." newline rbitfld.long 0x4 6.--7. "RESERVED_7_6,Reserved." "0,1,2,3" newline bitfld.long 0x4 4.--5. "RDWD,Receive DMA Write Descriptor Domain Control This field is used to drive awdomain_o[1:0] signal when Receive DMA accesses the Descriptor." "0,1,2,3" newline hexmask.long.byte 0x4 0.--3. 1. "RDWC,Receive DMA Write Descriptor Cache Control This field is used to drive awcache_o[3:0] signal when Receive DMA accesses the Descriptor." line.long 0x8 "AXI4_TXRX_AWAR_ACE_CONTROL,This register is used to control the AXI4 Cache Coherency Signals for Descriptor write transactions by all the TxDMA channels and Descriptor read transactions by all the RxDMA channels. It also controls the values to be driven.." hexmask.long.word 0x8 23.--31. 1. "RESERVED_31_23,Reserved." newline bitfld.long 0x8 20.--22. "WRP,DMA Write Protection control This field is used to drive awprot_m_o[2:0] signal on the AXI Write Channel." "0,1,2,3,4,5,6,7" newline rbitfld.long 0x8 19. "RESERVED_19,Reserved." "0,1" newline bitfld.long 0x8 16.--18. "RDP,DMA Read Protection control This field is used to drive arprot_m_o[2:0] signal during all read requests." "0,1,2,3,4,5,6,7" newline rbitfld.long 0x8 14.--15. "RESERVED_15_14,Reserved." "0,1,2,3" newline bitfld.long 0x8 12.--13. "RDRD,Receive DMA Read Descriptor Domain control This field is used to drive ardomain_o[1:0] signal when Receive DMA engines read the Descriptor." "0,1,2,3" newline hexmask.long.byte 0x8 8.--11. 1. "RDRC,Receive DMA Read Descriptor Cache control This field is used to drive arcache_o[3:0] signal when Receive DMA engines read the Descriptor." newline rbitfld.long 0x8 6.--7. "RESERVED_7_6,Reserved." "0,1,2,3" newline bitfld.long 0x8 4.--5. "TDWD,Transmit DMA Write Descriptor Domain control This field is used to drive awdomain_o[1:0] signal when Transmit DMA write to the Descriptor." "0,1,2,3" newline hexmask.long.byte 0x8 0.--3. 1. "TDWC,Transmit DMA Write Descriptor Cache control This field is used to drive awcache_o[3:0] signal when Transmit DMA writes to the Descriptor." group.long 0x40++0x3 line.long 0x0 "AXI_LPI_ENTRY_INTERVAL,This register is used to control the AXI LPI entry interval." hexmask.long 0x0 4.--31. 1. "RESERVED_31_4,Reserved." newline hexmask.long.byte 0x0 0.--3. 1. "LPIEI,LPI Entry Interval Contains the number of system clock cycles multiplied by 64 to wait for an activity in the DWC_ether_qos to enter into the AXI low power state 0 indicates 64 clock cycles" group.long 0x50++0x3 line.long 0x0 "DMA_TBS_CTRL,This register is used to control the TBS attributes." hexmask.long.tbyte 0x0 8.--31. 1. "FTOS,Fetch Time Offset The value in units of 256 nanoseconds that has to be deducted from the Launch time to compute the Fetch Time. Max value: 999 999 999 ns additionally should be smaller than CTR-1 value when ESTM mode is set since this value is a.." newline rbitfld.long 0x0 7. "RESERVED_7,Reserved." "0,1" newline bitfld.long 0x0 4.--6. "FGOS,Fetch GSN Offset The number GSN slots that must be deducted from the Launch GSN to compute the Fetch GSN. Value valid only when FTOV is set." "0,1,2,3,4,5,6,7" newline rbitfld.long 0x0 1.--3. "RESERVED_3_1,Reserved." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 0. "FTOV,Fetch Time Offset Valid When set indicates the FTOS field is valid. When not set indicates the Fetch Offset is not valid and the DMA engine can fetch the frames from host memory without any time restrictions. 0x0: Fetch Time Offset is invalid 0x1:.." "Fetch Time Offset is invalid,Fetch Time Offset is valid" rgroup.long 0x80++0x3 line.long 0x0 "DMA_SAFETY_INTERRUPT_STATUS,This register indicates summary (whether error occured in DMA/MTL/MAC and correctable/uncorrectable) of the Automotive Safety related error interrupts." bitfld.long 0x0 31. "MCSIS,MAC Safety Uncorrectable Interrupt Status Indicates a uncorrectable Safety related Interrupt is set in the MAC module. MAC_DPP_FSM_Interrupt_Status register should be read when this bit is set to get the cause of the Safety Interrupt in MAC. 0x1:.." "MAC Safety Uncorrectable Interrupt Status not..,MAC Safety Uncorrectable Interrupt Status detected" newline bitfld.long 0x0 30. "RESERVED_30,Reserved." "0,1" newline bitfld.long 0x0 29. "MSUIS,MTL Safety Uncorrectable error Interrupt Status This bit indicates an uncorrectable error interrupt event in MTL. To get exact cause of the interrupt the software should read the MTL_Safety_Interrupt_Status register. 0x1: MTL Safety Uncorrectable.." "MTL Safety Uncorrectable error Interrupt Status..,MTL Safety Uncorrectable error Interrupt Status.." newline bitfld.long 0x0 28. "MSCIS,MTL Safety Correctable error Interrupt Status This bit indicates a correctable error interrupt event in MTL. To get exact cause of the interrupt the software should read the MTL_Safety_Interrupt_Status register. 0x1: MTL Safety Correctable error.." "MTL Safety Correctable error Interrupt Status..,MTL Safety Correctable error Interrupt Status.." newline hexmask.long 0x0 2.--27. 1. "RESERVED_27_2,Reserved." newline bitfld.long 0x0 1. "DEUIS,DMA ECC Uncorrectable error Interrupt Status This bit indicates an interrupt event in the DMA ECC safety feature. To get the exact cause of the interrupt the application should read the DMA_ECC_Interrupt_Status register. 0x1: DMA ECC Uncorrectable.." "DMA ECC Uncorrectable error Interrupt Status not..,DMA ECC Uncorrectable error Interrupt Status.." newline bitfld.long 0x0 0. "DECIS,DMA ECC Correctable error Interrupt Status This bit indicates an interrupt event in the DMA ECC safety feature. To get the exact cause of the interrupt the application should read the DMA_ECC_Interrupt_Status register. 0x1: DMA ECC Correctable.." "DMA ECC Correctable error Interrupt Status not..,DMA ECC Correctable error Interrupt Status.." tree.end tree "EQOS_DMA_CH0" group.long 0x0++0xB line.long 0x0 "DMA_CH0_CONTROL,The DMA Channeli Control register specifies the MSS value for segmentation. length to skip between two descriptors. and also the features such as header splitting and 8xPBL mode." hexmask.long.byte 0x0 25.--31. 1. "RESERVED_31_25,Reserved." newline rbitfld.long 0x0 24. "RESERVED_SPH,Reserved." "0,1" newline rbitfld.long 0x0 21.--23. "RESERVED_23_21,Reserved." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 18.--20. "DSL,Descriptor Skip Length This bit specifies the Word Dword or Lword number (depending on the 32-bit 64-bit or 128-bit bus) to skip between two unchained descriptors. The address skipping starts from the end of the current descriptor to the start of.." "0,1,2,3,4,5,6,7" newline rbitfld.long 0x0 17. "RESERVED_17,Reserved." "0,1" newline bitfld.long 0x0 16. "PBLX8,8xPBL mode When this bit is set the PBL value programmed in Bits[21:16] in DMA_CH0_Tx_Control and Bits[21:16] in DMA_CH0_Rx_Control is multiplied by eight times. Therefore the DMA transfers the data in 8 16 32 64 128 and 256 beats depending.." "0,1" newline rbitfld.long 0x0 14.--15. "RESERVED_15_14,Reserved." "0,1,2,3" newline hexmask.long.word 0x0 0.--13. 1. "RESERVED_MSS,Reserved." line.long 0x4 "DMA_CH0_TX_CONTROL,The DMA Channeli Transmit Control register controls the Tx features such as PBL. TCP segmentation. and Tx Channel weights." rbitfld.long 0x4 29.--31. "RESERVED_31_29,Reserved." "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 28. "EDSE,Enhanced Descriptor Enable When this bit is set the corresponding channel uses Enhanced Descriptors that are 32 Bytes for both Normal and Context Descriptors. When reset the corresponding channel uses the descriptors that are 16 Bytes. 0x0:.." "Enhanced Descriptor is disabled,Enhanced Descriptor is enabled" newline hexmask.long.byte 0x4 24.--27. 1. "TQOS,Transmit QOS. This field is used to drive arqos_m_o[3:0] or awqos_m_o[3:0] output signals for all transactions of DMA Tx Channel0." newline rbitfld.long 0x4 23. "RESERVED_23,Reserved." "0,1" newline rbitfld.long 0x4 22. "RESERVED_ETIC,Reserved." "0,1" newline hexmask.long.byte 0x4 16.--21. 1. "TXPBL,Transmit Programmable Burst Length These bits indicate the maximum number of beats to be transferred in one DMA block data transfer. The DMA always attempts max burst as specified in PBL each time it starts a burst transfer on the application bus." newline bitfld.long 0x4 15. "IPBL,Ignore PBL Requirement When this bit is set the DMA does not check for PBL number of locations in the MTL before initiating a transfer. If space is not available the MTL may use handshaking to slow the DMA. Note: This bit/mode must not be used.." "Ignore PBL Requirement is disabled,Ignore PBL Requirement is enabled" newline rbitfld.long 0x4 13.--14. "RESERVED_TSE_MODE,Reserved." "0,1,2,3" newline rbitfld.long 0x4 12. "RESERVED_TSE,Reserved." "0,1" newline hexmask.long.byte 0x4 5.--11. 1. "RESERVED_11_5,Reserved." newline bitfld.long 0x4 4. "OSF,Operate on Second Packet When this bit is set it instructs the DMA to process the second packet of the Transmit data even before the status for the first packet is obtained. 0x0: Operate on Second Packet disabled 0x1: Operate on Second Packet enabled" "Operate on Second Packet disabled,Operate on Second Packet enabled" newline rbitfld.long 0x4 1.--3. "RESERVED_TCW,Reserved." "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 0. "ST,Start or Stop Transmission Command When this bit is set transmission is placed in the Running state. The DMA checks the Transmit list at the current position for a packet to be transmitted. The DMA tries to acquire descriptor from either of the.." "Stop Transmission Command,Start Transmission Command" line.long 0x8 "DMA_CH0_RX_CONTROL,The DMA Channeli Receive Control register controls the Rx features such as PBL. buffer size. and extended status." bitfld.long 0x8 31. "RPF,Rx Packet Flush. When this bit is set to 1 then DWC_ether_qos automatically flushes the packet from the Rx Queues destined to this DMA Rx Channel when it is stopped. When this bit remains set and the DMA is re-started by the software driver the.." "Rx Packet Flush is disabled,Rx Packet Flush is enabled" newline rbitfld.long 0x8 28.--30. "RESERVED_30_28,Reserved." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x8 24.--27. 1. "RQOS,Rx AXI4 QOS. This field is used to drive arqos_m_o[3:0] or awqos_m_o[3:0] output signals for all transactions of DMA Rx Channel0." newline rbitfld.long 0x8 23. "RESERVED_23,Reserved." "0,1" newline rbitfld.long 0x8 22. "RESERVED_ERIC,Reserved." "0,1" newline hexmask.long.byte 0x8 16.--21. 1. "RXPBL,Receive Programmable Burst Length These bits indicate the maximum number of beats to be transferred in one DMA block data transfer. The DMA always attempts max burst as specified in PBL each time it starts a burst transfer on the application bus." newline rbitfld.long 0x8 15. "RESERVED_15,Reserved." "0,1" newline hexmask.long.word 0x8 5.--14. 1. "RBSZ_13_Y,Receive Buffer size High RBSZ[13:0] is split into two fields higher RBSZ_13_y and lower RBSZ_x_0. The RBSZ[13:0] field indicates the size of the Rx buffers specified in bytes. The maximum buffer size is limited to 16K bytes. The buffer size is.." newline hexmask.long.byte 0x8 1.--4. 1. "RBSZ_X_0,Receive Buffer size Low RBSZ[13:0] is split into two fields RBSZ_13_y and RBSZ_x_0. The RBSZ_x_0 is the lower field whose width is based on data bus width of the configuration. This field is of width 2 3 or 4 bits for 32-bit 64-bit or.." newline bitfld.long 0x8 0. "SR,Start or Stop Receive When this bit is set the DMA tries to acquire the descriptor from the Receive list and processes the incoming packets. The DMA tries to acquire descriptor from either of the following positions: - The current position in the.." "Stop Receive,Start Receive" group.long 0x10++0x13 line.long 0x0 "DMA_CH0_TXDESC_LIST_HADDRESS,The Channeli Tx Descriptor List HAddress register has the higher 8 or 16 bits of the start address of the Transmit descriptor list. You can write to this register only when the Tx DMA has stopped. that is. the ST bit is set.." hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED_31_Y,Reserved." newline hexmask.long.byte 0x0 0.--7. 1. "TDESHA,Start of Transmit List This field contains the most-significant 8 or 16 bits of the 40- or 48-bit base address of the first descriptor in the Transmit descriptor list." line.long 0x4 "DMA_CH0_TXDESC_LIST_ADDRESS,The Channeli Tx Descriptor List Address register points the DMA to the start of Transmit descriptor list. The descriptor lists reside in the physical memory space of the application and must be Word. Dword. or Lword-aligned.." hexmask.long 0x4 4.--31. 1. "TDESLA,Start of Transmit List This field contains the base address of the first descriptor in the Transmit descriptor list. The DMA ignores the LSB bits (1:0 2:0 or 3:0) for 32-bit 64-bit or 128-bit bus width and internally takes these bits as.." newline hexmask.long.byte 0x4 0.--3. 1. "RESERVED_LSB," line.long 0x8 "DMA_CH0_RXDESC_LIST_HADDRESS,The Channeli Rx Descriptor List HAddress register has the higher 8 or 16 bits of the start address of the Receive descriptor list. Writing to this register is permitted only when reception is stopped. When stopped. this.." hexmask.long.tbyte 0x8 8.--31. 1. "RESERVED_31_Y,Reserved." newline hexmask.long.byte 0x8 0.--7. 1. "RDESHA,Start of Receive List This field contains the most-significant 8 or 16 bits of the 40-bit or 48-bit base address of the first descriptor in the Rx Descriptor list." line.long 0xC "DMA_CH0_RXDESC_LIST_ADDRESS,The Channeli Rx Descriptor List Address register points the DMA to the start of Receive descriptor list. This register points to the start of the Receive Descriptor List. The descriptor lists reside in the physical memory.." hexmask.long 0xC 4.--31. 1. "RDESLA,Start of Receive List This field contains the base address of the first descriptor in the Rx Descriptor list. The DMA ignores the LSB bits (1:0 2:0 or 3:0) for 32-bit 64-bit or 128-bit bus width and internally takes these bits as all-zero." newline hexmask.long.byte 0xC 0.--3. 1. "RESERVED_LSB," line.long 0x10 "DMA_CH0_TXDESC_TAIL_POINTER,The Channeli Tx Descriptor Tail Pointer register points to an offset from the base and indicates the location of the last valid descriptor." hexmask.long 0x10 4.--31. 1. "TDTP,Transmit Descriptor Tail Pointer This field contains the tail pointer for the Tx descriptor ring. The software writes the tail pointer to add more descriptors to the Tx channel. The hardware tries to transmit all packets referenced by the.." newline hexmask.long.byte 0x10 0.--3. 1. "RESERVED_LSB," group.long 0x28++0x17 line.long 0x0 "DMA_CH0_RXDESC_TAIL_POINTER,The Channeli Rx Descriptor Tail Pointer Points to an offset from the base and indicates the location of the last valid descriptor." hexmask.long 0x0 4.--31. 1. "RDTP,Receive Descriptor Tail Pointer This field contains the tail pointer for the Rx descriptor ring. The software writes the tail pointer to add more descriptors to the Rx channel. The hardware tries to write all received packets to the descriptors.." newline hexmask.long.byte 0x0 0.--3. 1. "RESERVED_LSB," line.long 0x4 "DMA_CH0_TXDESC_RING_LENGTH,The Tx Descriptor Ring Length register contains the length of the Transmit descriptor ring." hexmask.long.tbyte 0x4 10.--31. 1. "RESERVED_31_10,Reserved." newline hexmask.long.word 0x4 0.--9. 1. "TDRL,Transmit Descriptor Ring Length This field sets the maximum number of Tx descriptors in the circular descriptor ring. The maximum number of descriptors is limited to 1K descriptors. Synopsys recommends a minimum ring descriptor length of 4. For.." line.long 0x8 "DMA_CH0_RXDESC_RING_LENGTH,The Channeli Rx Descriptor Ring Length register contains the length of the Receive descriptor circular ring." hexmask.long.tbyte 0x8 10.--31. 1. "RESERVED_31_10,Reserved." newline hexmask.long.word 0x8 0.--9. 1. "RDRL,Receive Descriptor Ring Length This register sets the maximum number of Rx descriptors in the circular descriptor ring. The maximum number of descriptors is limited to 1K descriptors. For example You can program any value up to 0x3FF in this field." line.long 0xC "DMA_CH0_INTERRUPT_ENABLE,The Channeli Interrupt Enable register enables the interrupts reported by the Status register." hexmask.long.word 0xC 16.--31. 1. "RESERVED_31_16,Reserved." newline bitfld.long 0xC 15. "NIE,Normal Interrupt Summary Enable When this bit is set the normal interrupt summary is enabled. This bit enables the following interrupts in the DMA_CH0_Status register: - Bit 0: Transmit Interrupt - Bit 2: Transmit Buffer Unavailable - Bit 6: Receive.." "Normal Interrupt Summary is disabled,Normal Interrupt Summary is enabled" newline bitfld.long 0xC 14. "AIE,Abnormal Interrupt Summary Enable When this bit is set the abnormal interrupt summary is enabled. This bit enables the following interrupts in the DMA_CH0_Status register: - Bit 1: Transmit Process Stopped - Bit 7: Rx Buffer Unavailable - Bit 8:.." "Abnormal Interrupt Summary is disabled,Abnormal Interrupt Summary is enabled" newline bitfld.long 0xC 13. "CDEE,Context Descriptor Error Enable When this bit is set along with the AIE bit the Descriptor error interrupt is enabled. When this bit is reset the Descriptor error interrupt is disabled. 0x0: Context Descriptor Error is disabled 0x1: Context.." "Context Descriptor Error is disabled,Context Descriptor Error is enabled" newline bitfld.long 0xC 12. "FBEE,Fatal Bus Error Enable When this bit is set along with the AIE bit the Fatal Bus error interrupt is enabled. When this bit is reset the Fatal Bus Error error interrupt is disabled. 0x0: Fatal Bus Error is disabled 0x1: Fatal Bus Error is enabled" "Fatal Bus Error is disabled,Fatal Bus Error is enabled" newline bitfld.long 0xC 11. "ERIE,Early Receive Interrupt Enable When this bit is set along with the NIE bit the Early Receive interrupt is enabled. When this bit is reset the Early Receive interrupt is disabled. 0x0: Early Receive Interrupt is disabled 0x1: Early Receive.." "Early Receive Interrupt is disabled,Early Receive Interrupt is enabled" newline bitfld.long 0xC 10. "ETIE,Early Transmit Interrupt Enable When this bit is set along with the AIE bit the Early Transmit interrupt is enabled. When this bit is reset the Early Transmit interrupt is disabled. 0x0: Early Transmit Interrupt is disabled 0x1: Early Transmit.." "Early Transmit Interrupt is disabled,Early Transmit Interrupt is enabled" newline bitfld.long 0xC 9. "RWTE,Receive Watchdog Timeout Enable When this bit is set along with the AIE bit the Receive Watchdog Timeout interrupt is enabled. When this bit is reset the Receive Watchdog Timeout interrupt is disabled. 0x0: Receive Watchdog Timeout is disabled.." "Receive Watchdog Timeout is disabled,Receive Watchdog Timeout is enabled" newline bitfld.long 0xC 8. "RSE,Receive Stopped Enable When this bit is set along with the AIE bit the Receive Stopped Interrupt is enabled. When this bit is reset the Receive Stopped interrupt is disabled. 0x0: Receive Stopped is disabled 0x1: Receive Stopped is enabled" "Receive Stopped is disabled,Receive Stopped is enabled" newline bitfld.long 0xC 7. "RBUE,Receive Buffer Unavailable Enable When this bit is set along with the AIE bit the Receive Buffer Unavailable interrupt is enabled. When this bit is reset the Receive Buffer Unavailable interrupt is disabled. 0x0: Receive Buffer Unavailable is.." "Receive Buffer Unavailable is disabled,Receive Buffer Unavailable is enabled" newline bitfld.long 0xC 6. "RIE,Receive Interrupt Enable When this bit is set along with the NIE bit the Receive Interrupt is enabled. When this bit is reset the Receive Interrupt is disabled. 0x0: Receive Interrupt is disabled 0x1: Receive Interrupt is enabled" "Receive Interrupt is disabled,Receive Interrupt is enabled" newline rbitfld.long 0xC 3.--5. "RESERVED_5_3,Reserved." "0,1,2,3,4,5,6,7" newline bitfld.long 0xC 2. "TBUE,Transmit Buffer Unavailable Enable When this bit is set along with the NIE bit the Transmit Buffer Unavailable interrupt is enabled. When this bit is reset the Transmit Buffer Unavailable interrupt is disabled. 0x0: Transmit Buffer Unavailable is.." "Transmit Buffer Unavailable is disabled,Transmit Buffer Unavailable is enabled" newline bitfld.long 0xC 1. "TXSE,Transmit Stopped Enable When this bit is set along with the AIE bit the Transmission Stopped interrupt is enabled. When this bit is reset the Transmission Stopped interrupt is disabled. 0x0: Transmit Stopped is disabled 0x1: Transmit Stopped is.." "Transmit Stopped is disabled,Transmit Stopped is enabled" newline bitfld.long 0xC 0. "TIE,Transmit Interrupt Enable When this bit is set along with the NIE bit the Transmit Interrupt is enabled. When this bit is reset the Transmit Interrupt is disabled. 0x0: Transmit Interrupt is disabled 0x1: Transmit Interrupt is enabled" "Transmit Interrupt is disabled,Transmit Interrupt is enabled" line.long 0x10 "DMA_CH0_RX_INTERRUPT_WATCHDOG_TIMER,The Receive Interrupt Watchdog Timer register indicates the watchdog timeout for Receive Interrupt (RI) from the DMA. When this register is written with a non-zero value. it enables the watchdog timer for the RI bit of.." hexmask.long.word 0x10 18.--31. 1. "RESERVED_31_18,Reserved." newline bitfld.long 0x10 16.--17. "RWTU,Receive Interrupt Watchdog Timer Count Units This fields indicates the number of system clock cycles corresponding to one unit in RWT field. - 2'b00: 256 - 2'b01: 512 - 2'b10: 1024 - 2'b11: 2048 For example when RWT=2 and RWTU=1 the watchdog timer.." "0,1,2,3" newline hexmask.long.byte 0x10 8.--15. 1. "RESERVED_15_8,Reserved." newline hexmask.long.byte 0x10 0.--7. 1. "RWT,Receive Interrupt Watchdog Timer Count This field indicates the number of system clock cycles multiplied by factor indicated in RWTU field for which the watchdog timer is set. The watchdog timer is triggered with the programmed value after the Rx.." line.long 0x14 "DMA_CH0_SLOT_FUNCTION_CONTROL_STATUS,The Slot Function Control and Status register contains the control bits for slot function and the status for Transmit path." hexmask.long.word 0x14 20.--31. 1. "RESERVED_31_20,Reserved." newline hexmask.long.byte 0x14 16.--19. 1. "RSN,Reference Slot Number This field gives the current value of the reference slot number in the DMA. It is used for slot comparison." newline hexmask.long.word 0x14 4.--15. 1. "SIV,Slot Interval Value This field controls the period of the slot interval in which the TxDMA fetches the scheduled packets. A value of 0 specifies the slot interval of 1 us while the maximum value 4095 specifies the slot interval of 4096us. The.." newline rbitfld.long 0x14 2.--3. "RESERVED_3_2,Reserved." "0,1,2,3" newline bitfld.long 0x14 1. "ASC,Advance Slot Check When set this bit enables the DMA to fetch the data from the buffer when the slot number (SLOTNUM) programmed in the Tx descriptor is - equal to the reference slot number given in the RSN field or - ahead of the reference slot.." "Advance Slot Check is disabled,Advance Slot Check is enabled" newline bitfld.long 0x14 0. "ESC,Enable Slot Comparison When set this bit enables the checking of the slot numbers programmed in the Tx descriptor with the current reference given in the RSN field. The DMA fetches the data from the corresponding buffer only when the slot number is.." "Slot Comparison is disabled,Slot Comparison is enabled" rgroup.long 0x44++0x3 line.long 0x0 "DMA_CH0_CURRENT_APP_TXDESC,The Channeli Current Application Transmit Descriptor register points to the current Transmit descriptor read by the DMA." hexmask.long 0x0 0.--31. 1. "CURTDESAPTR,Application Transmit Descriptor Address Pointer The DMA updates this pointer during Tx operation. This pointer is cleared on reset." rgroup.long 0x4C++0x13 line.long 0x0 "DMA_CH0_CURRENT_APP_RXDESC,The Channeli Current Application Receive Descriptor register points to the current Receive descriptor read by the DMA." hexmask.long 0x0 0.--31. 1. "CURRDESAPTR,Application Receive Descriptor Address Pointer The DMA updates this pointer during Rx operation. This pointer is cleared on reset." line.long 0x4 "DMA_CH0_CURRENT_APP_TXBUFFER_H,The Channeli Current Application Transmit Buffer Address High register has the higher 8 or 16 bits of the current address of the Transmit buffer address read by the DMA." hexmask.long.tbyte 0x4 8.--31. 1. "RESERVED_31_Y,Reserved." newline hexmask.long.byte 0x4 0.--7. 1. "CURTBUFAPTRH,Application Transmit Buffer Address Pointer The DMA updates this pointer during Tx operation. This pointer is cleared on reset." line.long 0x8 "DMA_CH0_CURRENT_APP_TXBUFFER,The Channeli Current Application Transmit Buffer Address register points to the current Tx buffer address read by the DMA." hexmask.long 0x8 0.--31. 1. "CURTBUFAPTR,Application Transmit Buffer Address Pointer The DMA updates this pointer during Tx operation. This pointer is cleared on reset." line.long 0xC "DMA_CH0_CURRENT_APP_RXBUFFER_H,The Channeli Current Application Receive Buffer Address High register has the higher 8 or 16 bits of the current address of the Receive buffer address read by the DMA." hexmask.long.tbyte 0xC 8.--31. 1. "RESERVED_31_Y,Reserved." newline hexmask.long.byte 0xC 0.--7. 1. "CURRBUFAPTRH,Application Receive Buffer Address Pointer The DMA updates this pointer during Rx operation. This pointer is cleared on reset." line.long 0x10 "DMA_CH0_CURRENT_APP_RXBUFFER,The Channel 0 Current Application Receive Buffer Address register points to the current Rx buffer address read by the DMA." hexmask.long 0x10 0.--31. 1. "CURRBUFAPTR,Application Receive Buffer Address Pointer The DMA updates this pointer during Rx operation. This pointer is cleared on reset." group.long 0x60++0x3 line.long 0x0 "DMA_CH0_STATUS,The software driver (application) reads the Status register during interrupt service routine or polling to determine the status of the DMA. Note: The number of DMA_CH[n]_Status register in the configuration is the higher of number of Rx.." hexmask.long.word 0x0 22.--31. 1. "RESERVED_31_22,Reserved." newline rbitfld.long 0x0 19.--21. "REB,Rx DMA Error Bits This field indicates the type of error that caused a Bus Error. For example error response on the AHB or AXI interface. - Bit 21 -- 1'b1: Error during data transfer by Rx DMA -- 1'b0: No Error during data transfer by Rx DMA - Bit.." "Error during write transfer,Error during read transfer,?,?,?,?,?,?" newline rbitfld.long 0x0 16.--18. "TEB,Tx DMA Error Bits This field indicates the type of error that caused a Bus Error. For example error response on the AHB or AXI interface. - Bit 18 -- 1'b1: Error during data transfer by Tx DMA -- 1'b0: No Error during data transfer by Tx DMA - Bit.." "Error during write transfer,Error during read transfer,?,?,?,?,?,?" newline bitfld.long 0x0 15. "NIS,Normal Interrupt Summary Normal Interrupt Summary bit value is the logical OR of the following bits when the corresponding interrupt bits are enabled in the DMA_CH0_Interrupt_Enable register: - Bit 0: Transmit Interrupt - Bit 2: Transmit Buffer.." "Normal Interrupt Summary status not detected,Normal Interrupt Summary status detected" newline bitfld.long 0x0 14. "AIS,Abnormal Interrupt Summary Abnormal Interrupt Summary bit value is the logical OR of the following when the corresponding interrupt bits are enabled in the DMA_CH0_Interrupt_Enable register: - Bit 1: Transmit Process Stopped - Bit 7: Receive Buffer.." "Abnormal Interrupt Summary status not detected,Abnormal Interrupt Summary status detected" newline bitfld.long 0x0 13. "CDE,Context Descriptor Error This bit indicates that the DMA Tx/Rx engine received a descriptor error which indicates invalid context in the middle of packet flow ( intermediate descriptor) or all one's descriptor in Tx case and on Rx side it indicates.." "Context Descriptor Error status not detected,Context Descriptor Error status detected" newline bitfld.long 0x0 12. "FBE,Fatal Bus Error This bit indicates that a bus error occurred (as described in the EB field). When this bit is set the corresponding DMA channel engine disables all bus accesses. Access restriction applies. Self-set to 1 on internal event. Setting 1.." "Fatal Bus Error status not detected,Fatal Bus Error status detected" newline bitfld.long 0x0 11. "ERI,Early Receive Interrupt This bit when set indicates that the RxDMA has completed the transfer of packet data to the memory. In configs supporting ERIC When ERIC=0 this bit is set only after the Rx DMA has filled up a complete receive buffer with.." "Early Receive Interrupt status not detected,Early Receive Interrupt status detected" newline bitfld.long 0x0 10. "ETI,Early Transmit Interrupt This bit when set indicates that the TxDMA has completed the transfer of packet data to the MTL TXFIFO memory. In configs supporting ERIC: When ETIC=0 this bit is set only after the Tx DMA has transferred a complete packet.." "Early Transmit Interrupt status not detected,Early Transmit Interrupt status detected" newline bitfld.long 0x0 9. "RWT,Receive Watchdog Timeout This bit is asserted when a packet with length greater than 2 048 bytes (10 240 bytes when Jumbo Packet mode is enabled) is received. 0x1: Receive Watchdog Timeout status detected 0x0: Receive Watchdog Timeout status not.." "Receive Watchdog Timeout status not detected,Receive Watchdog Timeout status detected" newline bitfld.long 0x0 8. "RPS,Receive Process Stopped This bit is asserted when the Rx process enters the Stopped state. Access restriction applies. Self-set to 1 on internal event. Setting 1 clears. Setting 0 has no effect. 0x1: Receive Process Stopped status detected 0x0:.." "Receive Process Stopped status not detected,Receive Process Stopped status detected" newline bitfld.long 0x0 7. "RBU,Receive Buffer Unavailable This bit indicates that the application owns the next descriptor in the Receive list and the DMA cannot acquire it. The Rx process is suspended. To resume processing Rx descriptors the application should change the.." "Receive Buffer Unavailable status not detected,Receive Buffer Unavailable status detected" newline bitfld.long 0x0 6. "RI,Receive Interrupt This bit indicates that the packet reception is complete. When packet reception is complete Bit 31 of RDES3 is reset in the last descriptor and the specific packet status information is updated in the descriptor. The reception.." "Receive Interrupt status not detected,Receive Interrupt status detected" newline rbitfld.long 0x0 3.--5. "RESERVED_5_3,Reserved." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 2. "TBU,Transmit Buffer Unavailable This bit indicates that the application owns the next descriptor in the Transmit list and the DMA cannot acquire it. Transmission is suspended. The TPS0 field of the DMA_Debug_Status0 register explains the Transmit.." "Transmit Buffer Unavailable status not detected,Transmit Buffer Unavailable status detected" newline bitfld.long 0x0 1. "TPS,Transmit Process Stopped This bit is set when the transmission is stopped. Access restriction applies. Self-set to 1 on internal event. Setting 1 clears. Setting 0 has no effect. 0x1: Transmit Process Stopped status detected 0x0: Transmit Process.." "Transmit Process Stopped status not detected,Transmit Process Stopped status detected" newline bitfld.long 0x0 0. "TI,Transmit Interrupt This bit indicates that the packet transmission is complete. When transmission is complete Bit 31 of TDES3 is reset in the last descriptor and the specific packet status information is updated in the descriptor. Access restriction.." "Transmit Interrupt status not detected,Transmit Interrupt status detected" rgroup.long 0x64++0xB line.long 0x0 "DMA_CH0_MISS_FRAME_CNT,This register has the number of packet counter that got dropped by the DMA either due to Bus Error or due to programming RPF field in DMA_CH{i}_Rx_Control register." hexmask.long.word 0x0 16.--31. 1. "RESERVED_31_16,Reserved." newline bitfld.long 0x0 15. "MFCO,Overflow status of the MFC Counter When this bit is set then the MFC counter does not get incremented further. The bit gets cleared when this register is read. Access restriction applies. Clears on read. Self-set to 1 on internal event. 0x1: Miss.." "Miss Frame Counter overflow not occurred,Miss Frame Counter overflow occurred" newline hexmask.long.byte 0x0 11.--14. 1. "RESERVED_14_11,Reserved." newline hexmask.long.word 0x0 0.--10. 1. "MFC,Dropped Packet Counters This counter indicates the number of packet counters that are dropped by the DMA either because of bus error or because of programing RPF field in DMA_CH{i}_Rx_Control register. The counter gets cleared when this register is.." line.long 0x4 "DMA_CH0_RXP_ACCEPT_CNT,The DMA_CH(#i)_RXP_Accept_Cnt registers provides the count of the number of frames accepted by Rx Parser." bitfld.long 0x4 31. "RXPACOF,Rx Parser Accept Counter Overflow Bit When set this bit indicates that the RXPAC Counter field crossed the maximum limit. Access restriction applies. Clears on read. Self-set to 1 on internal event. 0x1: Rx Parser Accept Counter overflow.." "Rx Parser Accept Counter overflow not occurred,Rx Parser Accept Counter overflow occurred" newline hexmask.long 0x4 0.--30. 1. "RXPAC,Rx Parser Accept Counter This 31-bit counter is implemented whenever a Rx Parser Accept a packet due to AF =1. The counter is cleared when the register is read." line.long 0x8 "DMA_CH0_RX_ERI_CNT,The DMA_CH(#i)_RX_ERI_Cnt registers provides the count of the number of times ERI was asserted." hexmask.long.tbyte 0x8 12.--31. 1. "RESERVED_31_12," newline hexmask.long.word 0x8 0.--11. 1. "ECNT,ERI Counter When ERIC bit of DMA_CH(#i)_RX_Control register is set this counter increments for burst transfer completed by the Rx DMA from the start of packet transfer. This counter will get reset at the start of new packet." tree.end tree "EQOS_DMA_CH1" group.long 0x0++0xB line.long 0x0 "DMA_CH1_CONTROL,The DMA Channeli Control register specifies the MSS value for segmentation. length to skip between two descriptors. and also the features such as header splitting and 8xPBL mode." hexmask.long.byte 0x0 25.--31. 1. "RESERVED_31_25,Reserved." newline rbitfld.long 0x0 24. "RESERVED_SPH,Reserved." "0,1" newline rbitfld.long 0x0 21.--23. "RESERVED_23_21,Reserved." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 18.--20. "DSL,Descriptor Skip Length This bit specifies the Word Dword or Lword number (depending on the 32-bit 64-bit or 128-bit bus) to skip between two unchained descriptors. The address skipping starts from the end of the current descriptor to the start of.." "0,1,2,3,4,5,6,7" newline rbitfld.long 0x0 17. "RESERVED_17,Reserved." "0,1" newline bitfld.long 0x0 16. "PBLX8,8xPBL mode When this bit is set the PBL value programmed in Bits[21:16] in DMA_CH0_Tx_Control and Bits[21:16] in DMA_CH0_Rx_Control is multiplied by eight times. Therefore the DMA transfers the data in 8 16 32 64 128 and 256 beats depending.." "0,1" newline rbitfld.long 0x0 14.--15. "RESERVED_15_14,Reserved." "0,1,2,3" newline hexmask.long.word 0x0 0.--13. 1. "RESERVED_MSS,Reserved." line.long 0x4 "DMA_CH1_TX_CONTROL,The DMA Channeli Transmit Control register controls the Tx features such as PBL. TCP segmentation. and Tx Channel weights." rbitfld.long 0x4 29.--31. "RESERVED_31_29,Reserved." "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 28. "EDSE,Enhanced Descriptor Enable When this bit is set the corresponding channel uses Enhanced Descriptors that are 32 Bytes for both Normal and Context Descriptors. When reset the corresponding channel uses the descriptors that are 16 Bytes. 0x0:.." "Enhanced Descriptor is disabled,Enhanced Descriptor is enabled" newline hexmask.long.byte 0x4 24.--27. 1. "TQOS,Transmit QOS. This field is used to drive arqos_m_o[3:0] or awqos_m_o[3:0] output signals for all transactions of DMA Tx Channel0." newline rbitfld.long 0x4 23. "RESERVED_23,Reserved." "0,1" newline rbitfld.long 0x4 22. "RESERVED_ETIC,Reserved." "0,1" newline hexmask.long.byte 0x4 16.--21. 1. "TXPBL,Transmit Programmable Burst Length These bits indicate the maximum number of beats to be transferred in one DMA block data transfer. The DMA always attempts max burst as specified in PBL each time it starts a burst transfer on the application bus." newline bitfld.long 0x4 15. "IPBL,Ignore PBL Requirement When this bit is set the DMA does not check for PBL number of locations in the MTL before initiating a transfer. If space is not available the MTL may use handshaking to slow the DMA. Note: This bit/mode must not be used.." "Ignore PBL Requirement is disabled,Ignore PBL Requirement is enabled" newline rbitfld.long 0x4 13.--14. "RESERVED_TSE_MODE,Reserved." "0,1,2,3" newline rbitfld.long 0x4 12. "RESERVED_TSE,Reserved." "0,1" newline hexmask.long.byte 0x4 5.--11. 1. "RESERVED_11_5,Reserved." newline bitfld.long 0x4 4. "OSF,Operate on Second Packet When this bit is set it instructs the DMA to process the second packet of the Transmit data even before the status for the first packet is obtained. 0x0: Operate on Second Packet disabled 0x1: Operate on Second Packet enabled" "Operate on Second Packet disabled,Operate on Second Packet enabled" newline rbitfld.long 0x4 1.--3. "RESERVED_TCW,Reserved." "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 0. "ST,Start or Stop Transmission Command When this bit is set transmission is placed in the Running state. The DMA checks the Transmit list at the current position for a packet to be transmitted. The DMA tries to acquire descriptor from either of the.." "Stop Transmission Command,Start Transmission Command" line.long 0x8 "DMA_CH1_RX_CONTROL,The DMA Channeli Receive Control register controls the Rx features such as PBL. buffer size. and extended status." bitfld.long 0x8 31. "RPF,Rx Packet Flush. When this bit is set to 1 then DWC_ether_qos automatically flushes the packet from the Rx Queues destined to this DMA Rx Channel when it is stopped. When this bit remains set and the DMA is re-started by the software driver the.." "Rx Packet Flush is disabled,Rx Packet Flush is enabled" newline rbitfld.long 0x8 28.--30. "RESERVED_30_28,Reserved." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x8 24.--27. 1. "RQOS,Rx AXI4 QOS. This field is used to drive arqos_m_o[3:0] or awqos_m_o[3:0] output signals for all transactions of DMA Rx Channel0." newline rbitfld.long 0x8 23. "RESERVED_23,Reserved." "0,1" newline rbitfld.long 0x8 22. "RESERVED_ERIC,Reserved." "0,1" newline hexmask.long.byte 0x8 16.--21. 1. "RXPBL,Receive Programmable Burst Length These bits indicate the maximum number of beats to be transferred in one DMA block data transfer. The DMA always attempts max burst as specified in PBL each time it starts a burst transfer on the application bus." newline rbitfld.long 0x8 15. "RESERVED_15,Reserved." "0,1" newline hexmask.long.word 0x8 5.--14. 1. "RBSZ_13_Y,Receive Buffer size High RBSZ[13:0] is split into two fields higher RBSZ_13_y and lower RBSZ_x_0. The RBSZ[13:0] field indicates the size of the Rx buffers specified in bytes. The maximum buffer size is limited to 16K bytes. The buffer size is.." newline hexmask.long.byte 0x8 1.--4. 1. "RBSZ_X_0,Receive Buffer size Low RBSZ[13:0] is split into two fields RBSZ_13_y and RBSZ_x_0. The RBSZ_x_0 is the lower field whose width is based on data bus width of the configuration. This field is of width 2 3 or 4 bits for 32-bit 64-bit or.." newline bitfld.long 0x8 0. "SR,Start or Stop Receive When this bit is set the DMA tries to acquire the descriptor from the Receive list and processes the incoming packets. The DMA tries to acquire descriptor from either of the following positions: - The current position in the.." "Stop Receive,Start Receive" group.long 0x10++0x13 line.long 0x0 "DMA_CH1_TXDESC_LIST_HADDRESS,The Channeli Tx Descriptor List HAddress register has the higher 8 or 16 bits of the start address of the Transmit descriptor list. You can write to this register only when the Tx DMA has stopped. that is. the ST bit is set.." hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED_31_Y,Reserved." newline hexmask.long.byte 0x0 0.--7. 1. "TDESHA,Start of Transmit List This field contains the most-significant 8 or 16 bits of the 40- or 48-bit base address of the first descriptor in the Transmit descriptor list." line.long 0x4 "DMA_CH1_TXDESC_LIST_ADDRESS,The Channeli Tx Descriptor List Address register points the DMA to the start of Transmit descriptor list. The descriptor lists reside in the physical memory space of the application and must be Word. Dword. or Lword-aligned.." hexmask.long 0x4 4.--31. 1. "TDESLA,Start of Transmit List This field contains the base address of the first descriptor in the Transmit descriptor list. The DMA ignores the LSB bits (1:0 2:0 or 3:0) for 32-bit 64-bit or 128-bit bus width and internally takes these bits as.." newline hexmask.long.byte 0x4 0.--3. 1. "RESERVED_LSB," line.long 0x8 "DMA_CH1_RXDESC_LIST_HADDRESS,The Channeli Rx Descriptor List HAddress register has the higher 8 or 16 bits of the start address of the Receive descriptor list. Writing to this register is permitted only when reception is stopped. When stopped. this.." hexmask.long.tbyte 0x8 8.--31. 1. "RESERVED_31_Y,Reserved." newline hexmask.long.byte 0x8 0.--7. 1. "RDESHA,Start of Receive List This field contains the most-significant 8 or 16 bits of the 40-bit or 48-bit base address of the first descriptor in the Rx Descriptor list." line.long 0xC "DMA_CH1_RXDESC_LIST_ADDRESS,The Channeli Rx Descriptor List Address register points the DMA to the start of Receive descriptor list. This register points to the start of the Receive Descriptor List. The descriptor lists reside in the physical memory.." hexmask.long 0xC 4.--31. 1. "RDESLA,Start of Receive List This field contains the base address of the first descriptor in the Rx Descriptor list. The DMA ignores the LSB bits (1:0 2:0 or 3:0) for 32-bit 64-bit or 128-bit bus width and internally takes these bits as all-zero." newline hexmask.long.byte 0xC 0.--3. 1. "RESERVED_LSB," line.long 0x10 "DMA_CH1_TXDESC_TAIL_POINTER,The Channeli Tx Descriptor Tail Pointer register points to an offset from the base and indicates the location of the last valid descriptor." hexmask.long 0x10 4.--31. 1. "TDTP,Transmit Descriptor Tail Pointer This field contains the tail pointer for the Tx descriptor ring. The software writes the tail pointer to add more descriptors to the Tx channel. The hardware tries to transmit all packets referenced by the.." newline hexmask.long.byte 0x10 0.--3. 1. "RESERVED_LSB," group.long 0x28++0x17 line.long 0x0 "DMA_CH1_RXDESC_TAIL_POINTER,The Channeli Rx Descriptor Tail Pointer Points to an offset from the base and indicates the location of the last valid descriptor." hexmask.long 0x0 4.--31. 1. "RDTP,Receive Descriptor Tail Pointer This field contains the tail pointer for the Rx descriptor ring. The software writes the tail pointer to add more descriptors to the Rx channel. The hardware tries to write all received packets to the descriptors.." newline hexmask.long.byte 0x0 0.--3. 1. "RESERVED_LSB," line.long 0x4 "DMA_CH1_TXDESC_RING_LENGTH,The Tx Descriptor Ring Length register contains the length of the Transmit descriptor ring." hexmask.long.tbyte 0x4 10.--31. 1. "RESERVED_31_10,Reserved." newline hexmask.long.word 0x4 0.--9. 1. "TDRL,Transmit Descriptor Ring Length This field sets the maximum number of Tx descriptors in the circular descriptor ring. The maximum number of descriptors is limited to 1K descriptors. Synopsys recommends a minimum ring descriptor length of 4. For.." line.long 0x8 "DMA_CH1_RXDESC_RING_LENGTH,The Channeli Rx Descriptor Ring Length register contains the length of the Receive descriptor circular ring." hexmask.long.tbyte 0x8 10.--31. 1. "RESERVED_31_10,Reserved." newline hexmask.long.word 0x8 0.--9. 1. "RDRL,Receive Descriptor Ring Length This register sets the maximum number of Rx descriptors in the circular descriptor ring. The maximum number of descriptors is limited to 1K descriptors. For example You can program any value up to 0x3FF in this field." line.long 0xC "DMA_CH1_INTERRUPT_ENABLE,The Channeli Interrupt Enable register enables the interrupts reported by the Status register." hexmask.long.word 0xC 16.--31. 1. "RESERVED_31_16,Reserved." newline bitfld.long 0xC 15. "NIE,Normal Interrupt Summary Enable When this bit is set the normal interrupt summary is enabled. This bit enables the following interrupts in the DMA_CH0_Status register: - Bit 0: Transmit Interrupt - Bit 2: Transmit Buffer Unavailable - Bit 6: Receive.." "Normal Interrupt Summary is disabled,Normal Interrupt Summary is enabled" newline bitfld.long 0xC 14. "AIE,Abnormal Interrupt Summary Enable When this bit is set the abnormal interrupt summary is enabled. This bit enables the following interrupts in the DMA_CH0_Status register: - Bit 1: Transmit Process Stopped - Bit 7: Rx Buffer Unavailable - Bit 8:.." "Abnormal Interrupt Summary is disabled,Abnormal Interrupt Summary is enabled" newline bitfld.long 0xC 13. "CDEE,Context Descriptor Error Enable When this bit is set along with the AIE bit the Descriptor error interrupt is enabled. When this bit is reset the Descriptor error interrupt is disabled. 0x0: Context Descriptor Error is disabled 0x1: Context.." "Context Descriptor Error is disabled,Context Descriptor Error is enabled" newline bitfld.long 0xC 12. "FBEE,Fatal Bus Error Enable When this bit is set along with the AIE bit the Fatal Bus error interrupt is enabled. When this bit is reset the Fatal Bus Error error interrupt is disabled. 0x0: Fatal Bus Error is disabled 0x1: Fatal Bus Error is enabled" "Fatal Bus Error is disabled,Fatal Bus Error is enabled" newline bitfld.long 0xC 11. "ERIE,Early Receive Interrupt Enable When this bit is set along with the NIE bit the Early Receive interrupt is enabled. When this bit is reset the Early Receive interrupt is disabled. 0x0: Early Receive Interrupt is disabled 0x1: Early Receive.." "Early Receive Interrupt is disabled,Early Receive Interrupt is enabled" newline bitfld.long 0xC 10. "ETIE,Early Transmit Interrupt Enable When this bit is set along with the AIE bit the Early Transmit interrupt is enabled. When this bit is reset the Early Transmit interrupt is disabled. 0x0: Early Transmit Interrupt is disabled 0x1: Early Transmit.." "Early Transmit Interrupt is disabled,Early Transmit Interrupt is enabled" newline bitfld.long 0xC 9. "RWTE,Receive Watchdog Timeout Enable When this bit is set along with the AIE bit the Receive Watchdog Timeout interrupt is enabled. When this bit is reset the Receive Watchdog Timeout interrupt is disabled. 0x0: Receive Watchdog Timeout is disabled.." "Receive Watchdog Timeout is disabled,Receive Watchdog Timeout is enabled" newline bitfld.long 0xC 8. "RSE,Receive Stopped Enable When this bit is set along with the AIE bit the Receive Stopped Interrupt is enabled. When this bit is reset the Receive Stopped interrupt is disabled. 0x0: Receive Stopped is disabled 0x1: Receive Stopped is enabled" "Receive Stopped is disabled,Receive Stopped is enabled" newline bitfld.long 0xC 7. "RBUE,Receive Buffer Unavailable Enable When this bit is set along with the AIE bit the Receive Buffer Unavailable interrupt is enabled. When this bit is reset the Receive Buffer Unavailable interrupt is disabled. 0x0: Receive Buffer Unavailable is.." "Receive Buffer Unavailable is disabled,Receive Buffer Unavailable is enabled" newline bitfld.long 0xC 6. "RIE,Receive Interrupt Enable When this bit is set along with the NIE bit the Receive Interrupt is enabled. When this bit is reset the Receive Interrupt is disabled. 0x0: Receive Interrupt is disabled 0x1: Receive Interrupt is enabled" "Receive Interrupt is disabled,Receive Interrupt is enabled" newline rbitfld.long 0xC 3.--5. "RESERVED_5_3,Reserved." "0,1,2,3,4,5,6,7" newline bitfld.long 0xC 2. "TBUE,Transmit Buffer Unavailable Enable When this bit is set along with the NIE bit the Transmit Buffer Unavailable interrupt is enabled. When this bit is reset the Transmit Buffer Unavailable interrupt is disabled. 0x0: Transmit Buffer Unavailable is.." "Transmit Buffer Unavailable is disabled,Transmit Buffer Unavailable is enabled" newline bitfld.long 0xC 1. "TXSE,Transmit Stopped Enable When this bit is set along with the AIE bit the Transmission Stopped interrupt is enabled. When this bit is reset the Transmission Stopped interrupt is disabled. 0x0: Transmit Stopped is disabled 0x1: Transmit Stopped is.." "Transmit Stopped is disabled,Transmit Stopped is enabled" newline bitfld.long 0xC 0. "TIE,Transmit Interrupt Enable When this bit is set along with the NIE bit the Transmit Interrupt is enabled. When this bit is reset the Transmit Interrupt is disabled. 0x0: Transmit Interrupt is disabled 0x1: Transmit Interrupt is enabled" "Transmit Interrupt is disabled,Transmit Interrupt is enabled" line.long 0x10 "DMA_CH1_RX_INTERRUPT_WATCHDOG_TIMER,The Receive Interrupt Watchdog Timer register indicates the watchdog timeout for Receive Interrupt (RI) from the DMA. When this register is written with a non-zero value. it enables the watchdog timer for the RI bit of.." hexmask.long.word 0x10 18.--31. 1. "RESERVED_31_18,Reserved." newline bitfld.long 0x10 16.--17. "RWTU,Receive Interrupt Watchdog Timer Count Units This fields indicates the number of system clock cycles corresponding to one unit in RWT field. - 2'b00: 256 - 2'b01: 512 - 2'b10: 1024 - 2'b11: 2048 For example when RWT=2 and RWTU=1 the watchdog timer.." "0,1,2,3" newline hexmask.long.byte 0x10 8.--15. 1. "RESERVED_15_8,Reserved." newline hexmask.long.byte 0x10 0.--7. 1. "RWT,Receive Interrupt Watchdog Timer Count This field indicates the number of system clock cycles multiplied by factor indicated in RWTU field for which the watchdog timer is set. The watchdog timer is triggered with the programmed value after the Rx.." line.long 0x14 "DMA_CH1_SLOT_FUNCTION_CONTROL_STATUS,The Slot Function Control and Status register contains the control bits for slot function and the status for Transmit path." hexmask.long.word 0x14 20.--31. 1. "RESERVED_31_20,Reserved." newline hexmask.long.byte 0x14 16.--19. 1. "RSN,Reference Slot Number This field gives the current value of the reference slot number in the DMA. It is used for slot comparison." newline hexmask.long.word 0x14 4.--15. 1. "SIV,Slot Interval Value This field controls the period of the slot interval in which the TxDMA fetches the scheduled packets. A value of 0 specifies the slot interval of 1 us while the maximum value 4095 specifies the slot interval of 4096us. The.." newline rbitfld.long 0x14 2.--3. "RESERVED_3_2,Reserved." "0,1,2,3" newline bitfld.long 0x14 1. "ASC,Advance Slot Check When set this bit enables the DMA to fetch the data from the buffer when the slot number (SLOTNUM) programmed in the Tx descriptor is - equal to the reference slot number given in the RSN field or - ahead of the reference slot.." "Advance Slot Check is disabled,Advance Slot Check is enabled" newline bitfld.long 0x14 0. "ESC,Enable Slot Comparison When set this bit enables the checking of the slot numbers programmed in the Tx descriptor with the current reference given in the RSN field. The DMA fetches the data from the corresponding buffer only when the slot number is.." "Slot Comparison is disabled,Slot Comparison is enabled" rgroup.long 0x44++0x3 line.long 0x0 "DMA_CH1_CURRENT_APP_TXDESC,The Channeli Current Application Transmit Descriptor register points to the current Transmit descriptor read by the DMA." hexmask.long 0x0 0.--31. 1. "CURTDESAPTR,Application Transmit Descriptor Address Pointer The DMA updates this pointer during Tx operation. This pointer is cleared on reset." rgroup.long 0x4C++0x13 line.long 0x0 "DMA_CH1_CURRENT_APP_RXDESC,The Channeli Current Application Receive Descriptor register points to the current Receive descriptor read by the DMA." hexmask.long 0x0 0.--31. 1. "CURRDESAPTR,Application Receive Descriptor Address Pointer The DMA updates this pointer during Rx operation. This pointer is cleared on reset." line.long 0x4 "DMA_CH1_CURRENT_APP_TXBUFFER_H,The Channeli Current Application Transmit Buffer Address High register has the higher 8 or 16 bits of the current address of the Transmit buffer address read by the DMA." hexmask.long.tbyte 0x4 8.--31. 1. "RESERVED_31_Y,Reserved." newline hexmask.long.byte 0x4 0.--7. 1. "CURTBUFAPTRH,Application Transmit Buffer Address Pointer The DMA updates this pointer during Tx operation. This pointer is cleared on reset." line.long 0x8 "DMA_CH1_CURRENT_APP_TXBUFFER,The Channeli Current Application Transmit Buffer Address register points to the current Tx buffer address read by the DMA." hexmask.long 0x8 0.--31. 1. "CURTBUFAPTR,Application Transmit Buffer Address Pointer The DMA updates this pointer during Tx operation. This pointer is cleared on reset." line.long 0xC "DMA_CH1_CURRENT_APP_RXBUFFER_H,The Channeli Current Application Receive Buffer Address High register has the higher 8 or 16 bits of the current address of the Receive buffer address read by the DMA." hexmask.long.tbyte 0xC 8.--31. 1. "RESERVED_31_Y,Reserved." newline hexmask.long.byte 0xC 0.--7. 1. "CURRBUFAPTRH,Application Receive Buffer Address Pointer The DMA updates this pointer during Rx operation. This pointer is cleared on reset." line.long 0x10 "DMA_CH1_CURRENT_APP_RXBUFFER,The Channel 0 Current Application Receive Buffer Address register points to the current Rx buffer address read by the DMA." hexmask.long 0x10 0.--31. 1. "CURRBUFAPTR,Application Receive Buffer Address Pointer The DMA updates this pointer during Rx operation. This pointer is cleared on reset." group.long 0x60++0x3 line.long 0x0 "DMA_CH1_STATUS,The software driver (application) reads the Status register during interrupt service routine or polling to determine the status of the DMA. Note: The number of DMA_CH[n]_Status register in the configuration is the higher of number of Rx.." hexmask.long.word 0x0 22.--31. 1. "RESERVED_31_22,Reserved." newline rbitfld.long 0x0 19.--21. "REB,Rx DMA Error Bits This field indicates the type of error that caused a Bus Error. For example error response on the AHB or AXI interface. - Bit 21 -- 1'b1: Error during data transfer by Rx DMA -- 1'b0: No Error during data transfer by Rx DMA - Bit.." "Error during write transfer,Error during read transfer,?,?,?,?,?,?" newline rbitfld.long 0x0 16.--18. "TEB,Tx DMA Error Bits This field indicates the type of error that caused a Bus Error. For example error response on the AHB or AXI interface. - Bit 18 -- 1'b1: Error during data transfer by Tx DMA -- 1'b0: No Error during data transfer by Tx DMA - Bit.." "Error during write transfer,Error during read transfer,?,?,?,?,?,?" newline bitfld.long 0x0 15. "NIS,Normal Interrupt Summary Normal Interrupt Summary bit value is the logical OR of the following bits when the corresponding interrupt bits are enabled in the DMA_CH0_Interrupt_Enable register: - Bit 0: Transmit Interrupt - Bit 2: Transmit Buffer.." "Normal Interrupt Summary status not detected,Normal Interrupt Summary status detected" newline bitfld.long 0x0 14. "AIS,Abnormal Interrupt Summary Abnormal Interrupt Summary bit value is the logical OR of the following when the corresponding interrupt bits are enabled in the DMA_CH0_Interrupt_Enable register: - Bit 1: Transmit Process Stopped - Bit 7: Receive Buffer.." "Abnormal Interrupt Summary status not detected,Abnormal Interrupt Summary status detected" newline bitfld.long 0x0 13. "CDE,Context Descriptor Error This bit indicates that the DMA Tx/Rx engine received a descriptor error which indicates invalid context in the middle of packet flow ( intermediate descriptor) or all one's descriptor in Tx case and on Rx side it indicates.." "Context Descriptor Error status not detected,Context Descriptor Error status detected" newline bitfld.long 0x0 12. "FBE,Fatal Bus Error This bit indicates that a bus error occurred (as described in the EB field). When this bit is set the corresponding DMA channel engine disables all bus accesses. Access restriction applies. Self-set to 1 on internal event. Setting 1.." "Fatal Bus Error status not detected,Fatal Bus Error status detected" newline bitfld.long 0x0 11. "ERI,Early Receive Interrupt This bit when set indicates that the RxDMA has completed the transfer of packet data to the memory. In configs supporting ERIC When ERIC=0 this bit is set only after the Rx DMA has filled up a complete receive buffer with.." "Early Receive Interrupt status not detected,Early Receive Interrupt status detected" newline bitfld.long 0x0 10. "ETI,Early Transmit Interrupt This bit when set indicates that the TxDMA has completed the transfer of packet data to the MTL TXFIFO memory. In configs supporting ERIC: When ETIC=0 this bit is set only after the Tx DMA has transferred a complete packet.." "Early Transmit Interrupt status not detected,Early Transmit Interrupt status detected" newline bitfld.long 0x0 9. "RWT,Receive Watchdog Timeout This bit is asserted when a packet with length greater than 2 048 bytes (10 240 bytes when Jumbo Packet mode is enabled) is received. 0x1: Receive Watchdog Timeout status detected 0x0: Receive Watchdog Timeout status not.." "Receive Watchdog Timeout status not detected,Receive Watchdog Timeout status detected" newline bitfld.long 0x0 8. "RPS,Receive Process Stopped This bit is asserted when the Rx process enters the Stopped state. Access restriction applies. Self-set to 1 on internal event. Setting 1 clears. Setting 0 has no effect. 0x1: Receive Process Stopped status detected 0x0:.." "Receive Process Stopped status not detected,Receive Process Stopped status detected" newline bitfld.long 0x0 7. "RBU,Receive Buffer Unavailable This bit indicates that the application owns the next descriptor in the Receive list and the DMA cannot acquire it. The Rx process is suspended. To resume processing Rx descriptors the application should change the.." "Receive Buffer Unavailable status not detected,Receive Buffer Unavailable status detected" newline bitfld.long 0x0 6. "RI,Receive Interrupt This bit indicates that the packet reception is complete. When packet reception is complete Bit 31 of RDES3 is reset in the last descriptor and the specific packet status information is updated in the descriptor. The reception.." "Receive Interrupt status not detected,Receive Interrupt status detected" newline rbitfld.long 0x0 3.--5. "RESERVED_5_3,Reserved." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 2. "TBU,Transmit Buffer Unavailable This bit indicates that the application owns the next descriptor in the Transmit list and the DMA cannot acquire it. Transmission is suspended. The TPS0 field of the DMA_Debug_Status0 register explains the Transmit.." "Transmit Buffer Unavailable status not detected,Transmit Buffer Unavailable status detected" newline bitfld.long 0x0 1. "TPS,Transmit Process Stopped This bit is set when the transmission is stopped. Access restriction applies. Self-set to 1 on internal event. Setting 1 clears. Setting 0 has no effect. 0x1: Transmit Process Stopped status detected 0x0: Transmit Process.." "Transmit Process Stopped status not detected,Transmit Process Stopped status detected" newline bitfld.long 0x0 0. "TI,Transmit Interrupt This bit indicates that the packet transmission is complete. When transmission is complete Bit 31 of TDES3 is reset in the last descriptor and the specific packet status information is updated in the descriptor. Access restriction.." "Transmit Interrupt status not detected,Transmit Interrupt status detected" rgroup.long 0x64++0xB line.long 0x0 "DMA_CH1_MISS_FRAME_CNT,This register has the number of packet counter that got dropped by the DMA either due to Bus Error or due to programming RPF field in DMA_CH{i}_Rx_Control register." hexmask.long.word 0x0 16.--31. 1. "RESERVED_31_16,Reserved." newline bitfld.long 0x0 15. "MFCO,Overflow status of the MFC Counter When this bit is set then the MFC counter does not get incremented further. The bit gets cleared when this register is read. Access restriction applies. Clears on read. Self-set to 1 on internal event. 0x1: Miss.." "Miss Frame Counter overflow not occurred,Miss Frame Counter overflow occurred" newline hexmask.long.byte 0x0 11.--14. 1. "RESERVED_14_11,Reserved." newline hexmask.long.word 0x0 0.--10. 1. "MFC,Dropped Packet Counters This counter indicates the number of packet counters that are dropped by the DMA either because of bus error or because of programing RPF field in DMA_CH{i}_Rx_Control register. The counter gets cleared when this register is.." line.long 0x4 "DMA_CH1_RXP_ACCEPT_CNT,The DMA_CH(#i)_RXP_Accept_Cnt registers provides the count of the number of frames accepted by Rx Parser." bitfld.long 0x4 31. "RXPACOF,Rx Parser Accept Counter Overflow Bit When set this bit indicates that the RXPAC Counter field crossed the maximum limit. Access restriction applies. Clears on read. Self-set to 1 on internal event. 0x1: Rx Parser Accept Counter overflow.." "Rx Parser Accept Counter overflow not occurred,Rx Parser Accept Counter overflow occurred" newline hexmask.long 0x4 0.--30. 1. "RXPAC,Rx Parser Accept Counter This 31-bit counter is implemented whenever a Rx Parser Accept a packet due to AF =1. The counter is cleared when the register is read." line.long 0x8 "DMA_CH1_RX_ERI_CNT,The DMA_CH(#i)_RX_ERI_Cnt registers provides the count of the number of times ERI was asserted." hexmask.long.tbyte 0x8 12.--31. 1. "RESERVED_31_12," newline hexmask.long.word 0x8 0.--11. 1. "ECNT,ERI Counter When ERIC bit of DMA_CH(#i)_RX_Control register is set this counter increments for burst transfer completed by the Rx DMA from the start of packet transfer. This counter will get reset at the start of new packet." tree.end tree "EQOS_DMA_CH2" group.long 0x0++0xB line.long 0x0 "DMA_CH2_CONTROL,The DMA Channeli Control register specifies the MSS value for segmentation. length to skip between two descriptors. and also the features such as header splitting and 8xPBL mode." hexmask.long.byte 0x0 25.--31. 1. "RESERVED_31_25,Reserved." newline rbitfld.long 0x0 24. "RESERVED_SPH,Reserved." "0,1" newline rbitfld.long 0x0 21.--23. "RESERVED_23_21,Reserved." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 18.--20. "DSL,Descriptor Skip Length This bit specifies the Word Dword or Lword number (depending on the 32-bit 64-bit or 128-bit bus) to skip between two unchained descriptors. The address skipping starts from the end of the current descriptor to the start of.." "0,1,2,3,4,5,6,7" newline rbitfld.long 0x0 17. "RESERVED_17,Reserved." "0,1" newline bitfld.long 0x0 16. "PBLX8,8xPBL mode When this bit is set the PBL value programmed in Bits[21:16] in DMA_CH0_Tx_Control and Bits[21:16] in DMA_CH0_Rx_Control is multiplied by eight times. Therefore the DMA transfers the data in 8 16 32 64 128 and 256 beats depending.." "0,1" newline rbitfld.long 0x0 14.--15. "RESERVED_15_14,Reserved." "0,1,2,3" newline hexmask.long.word 0x0 0.--13. 1. "RESERVED_MSS,Reserved." line.long 0x4 "DMA_CH2_TX_CONTROL,The DMA Channeli Transmit Control register controls the Tx features such as PBL. TCP segmentation. and Tx Channel weights." rbitfld.long 0x4 29.--31. "RESERVED_31_29,Reserved." "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 28. "EDSE,Enhanced Descriptor Enable When this bit is set the corresponding channel uses Enhanced Descriptors that are 32 Bytes for both Normal and Context Descriptors. When reset the corresponding channel uses the descriptors that are 16 Bytes. 0x0:.." "Enhanced Descriptor is disabled,Enhanced Descriptor is enabled" newline hexmask.long.byte 0x4 24.--27. 1. "TQOS,Transmit QOS. This field is used to drive arqos_m_o[3:0] or awqos_m_o[3:0] output signals for all transactions of DMA Tx Channel0." newline rbitfld.long 0x4 23. "RESERVED_23,Reserved." "0,1" newline rbitfld.long 0x4 22. "RESERVED_ETIC,Reserved." "0,1" newline hexmask.long.byte 0x4 16.--21. 1. "TXPBL,Transmit Programmable Burst Length These bits indicate the maximum number of beats to be transferred in one DMA block data transfer. The DMA always attempts max burst as specified in PBL each time it starts a burst transfer on the application bus." newline bitfld.long 0x4 15. "IPBL,Ignore PBL Requirement When this bit is set the DMA does not check for PBL number of locations in the MTL before initiating a transfer. If space is not available the MTL may use handshaking to slow the DMA. Note: This bit/mode must not be used.." "Ignore PBL Requirement is disabled,Ignore PBL Requirement is enabled" newline rbitfld.long 0x4 13.--14. "RESERVED_TSE_MODE,Reserved." "0,1,2,3" newline rbitfld.long 0x4 12. "RESERVED_TSE,Reserved." "0,1" newline hexmask.long.byte 0x4 5.--11. 1. "RESERVED_11_5,Reserved." newline bitfld.long 0x4 4. "OSF,Operate on Second Packet When this bit is set it instructs the DMA to process the second packet of the Transmit data even before the status for the first packet is obtained. 0x0: Operate on Second Packet disabled 0x1: Operate on Second Packet enabled" "Operate on Second Packet disabled,Operate on Second Packet enabled" newline rbitfld.long 0x4 1.--3. "RESERVED_TCW,Reserved." "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 0. "ST,Start or Stop Transmission Command When this bit is set transmission is placed in the Running state. The DMA checks the Transmit list at the current position for a packet to be transmitted. The DMA tries to acquire descriptor from either of the.." "Stop Transmission Command,Start Transmission Command" line.long 0x8 "DMA_CH2_RX_CONTROL,The DMA Channeli Receive Control register controls the Rx features such as PBL. buffer size. and extended status." bitfld.long 0x8 31. "RPF,Rx Packet Flush. When this bit is set to 1 then DWC_ether_qos automatically flushes the packet from the Rx Queues destined to this DMA Rx Channel when it is stopped. When this bit remains set and the DMA is re-started by the software driver the.." "Rx Packet Flush is disabled,Rx Packet Flush is enabled" newline rbitfld.long 0x8 28.--30. "RESERVED_30_28,Reserved." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x8 24.--27. 1. "RQOS,Rx AXI4 QOS. This field is used to drive arqos_m_o[3:0] or awqos_m_o[3:0] output signals for all transactions of DMA Rx Channel0." newline rbitfld.long 0x8 23. "RESERVED_23,Reserved." "0,1" newline rbitfld.long 0x8 22. "RESERVED_ERIC,Reserved." "0,1" newline hexmask.long.byte 0x8 16.--21. 1. "RXPBL,Receive Programmable Burst Length These bits indicate the maximum number of beats to be transferred in one DMA block data transfer. The DMA always attempts max burst as specified in PBL each time it starts a burst transfer on the application bus." newline rbitfld.long 0x8 15. "RESERVED_15,Reserved." "0,1" newline hexmask.long.word 0x8 5.--14. 1. "RBSZ_13_Y,Receive Buffer size High RBSZ[13:0] is split into two fields higher RBSZ_13_y and lower RBSZ_x_0. The RBSZ[13:0] field indicates the size of the Rx buffers specified in bytes. The maximum buffer size is limited to 16K bytes. The buffer size is.." newline hexmask.long.byte 0x8 1.--4. 1. "RBSZ_X_0,Receive Buffer size Low RBSZ[13:0] is split into two fields RBSZ_13_y and RBSZ_x_0. The RBSZ_x_0 is the lower field whose width is based on data bus width of the configuration. This field is of width 2 3 or 4 bits for 32-bit 64-bit or.." newline bitfld.long 0x8 0. "SR,Start or Stop Receive When this bit is set the DMA tries to acquire the descriptor from the Receive list and processes the incoming packets. The DMA tries to acquire descriptor from either of the following positions: - The current position in the.." "Stop Receive,Start Receive" group.long 0x10++0x13 line.long 0x0 "DMA_CH2_TXDESC_LIST_HADDRESS,The Channeli Tx Descriptor List HAddress register has the higher 8 or 16 bits of the start address of the Transmit descriptor list. You can write to this register only when the Tx DMA has stopped. that is. the ST bit is set.." hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED_31_Y,Reserved." newline hexmask.long.byte 0x0 0.--7. 1. "TDESHA,Start of Transmit List This field contains the most-significant 8 or 16 bits of the 40- or 48-bit base address of the first descriptor in the Transmit descriptor list." line.long 0x4 "DMA_CH2_TXDESC_LIST_ADDRESS,The Channeli Tx Descriptor List Address register points the DMA to the start of Transmit descriptor list. The descriptor lists reside in the physical memory space of the application and must be Word. Dword. or Lword-aligned.." hexmask.long 0x4 4.--31. 1. "TDESLA,Start of Transmit List This field contains the base address of the first descriptor in the Transmit descriptor list. The DMA ignores the LSB bits (1:0 2:0 or 3:0) for 32-bit 64-bit or 128-bit bus width and internally takes these bits as.." newline hexmask.long.byte 0x4 0.--3. 1. "RESERVED_LSB," line.long 0x8 "DMA_CH2_RXDESC_LIST_HADDRESS,The Channeli Rx Descriptor List HAddress register has the higher 8 or 16 bits of the start address of the Receive descriptor list. Writing to this register is permitted only when reception is stopped. When stopped. this.." hexmask.long.tbyte 0x8 8.--31. 1. "RESERVED_31_Y,Reserved." newline hexmask.long.byte 0x8 0.--7. 1. "RDESHA,Start of Receive List This field contains the most-significant 8 or 16 bits of the 40-bit or 48-bit base address of the first descriptor in the Rx Descriptor list." line.long 0xC "DMA_CH2_RXDESC_LIST_ADDRESS,The Channeli Rx Descriptor List Address register points the DMA to the start of Receive descriptor list. This register points to the start of the Receive Descriptor List. The descriptor lists reside in the physical memory.." hexmask.long 0xC 4.--31. 1. "RDESLA,Start of Receive List This field contains the base address of the first descriptor in the Rx Descriptor list. The DMA ignores the LSB bits (1:0 2:0 or 3:0) for 32-bit 64-bit or 128-bit bus width and internally takes these bits as all-zero." newline hexmask.long.byte 0xC 0.--3. 1. "RESERVED_LSB," line.long 0x10 "DMA_CH2_TXDESC_TAIL_POINTER,The Channeli Tx Descriptor Tail Pointer register points to an offset from the base and indicates the location of the last valid descriptor." hexmask.long 0x10 4.--31. 1. "TDTP,Transmit Descriptor Tail Pointer This field contains the tail pointer for the Tx descriptor ring. The software writes the tail pointer to add more descriptors to the Tx channel. The hardware tries to transmit all packets referenced by the.." newline hexmask.long.byte 0x10 0.--3. 1. "RESERVED_LSB," group.long 0x28++0x17 line.long 0x0 "DMA_CH2_RXDESC_TAIL_POINTER,The Channeli Rx Descriptor Tail Pointer Points to an offset from the base and indicates the location of the last valid descriptor." hexmask.long 0x0 4.--31. 1. "RDTP,Receive Descriptor Tail Pointer This field contains the tail pointer for the Rx descriptor ring. The software writes the tail pointer to add more descriptors to the Rx channel. The hardware tries to write all received packets to the descriptors.." newline hexmask.long.byte 0x0 0.--3. 1. "RESERVED_LSB," line.long 0x4 "DMA_CH2_TXDESC_RING_LENGTH,The Tx Descriptor Ring Length register contains the length of the Transmit descriptor ring." hexmask.long.tbyte 0x4 10.--31. 1. "RESERVED_31_10,Reserved." newline hexmask.long.word 0x4 0.--9. 1. "TDRL,Transmit Descriptor Ring Length This field sets the maximum number of Tx descriptors in the circular descriptor ring. The maximum number of descriptors is limited to 1K descriptors. Synopsys recommends a minimum ring descriptor length of 4. For.." line.long 0x8 "DMA_CH2_RXDESC_RING_LENGTH,The Channeli Rx Descriptor Ring Length register contains the length of the Receive descriptor circular ring." hexmask.long.tbyte 0x8 10.--31. 1. "RESERVED_31_10,Reserved." newline hexmask.long.word 0x8 0.--9. 1. "RDRL,Receive Descriptor Ring Length This register sets the maximum number of Rx descriptors in the circular descriptor ring. The maximum number of descriptors is limited to 1K descriptors. For example You can program any value up to 0x3FF in this field." line.long 0xC "DMA_CH2_INTERRUPT_ENABLE,The Channeli Interrupt Enable register enables the interrupts reported by the Status register." hexmask.long.word 0xC 16.--31. 1. "RESERVED_31_16,Reserved." newline bitfld.long 0xC 15. "NIE,Normal Interrupt Summary Enable When this bit is set the normal interrupt summary is enabled. This bit enables the following interrupts in the DMA_CH0_Status register: - Bit 0: Transmit Interrupt - Bit 2: Transmit Buffer Unavailable - Bit 6: Receive.." "Normal Interrupt Summary is disabled,Normal Interrupt Summary is enabled" newline bitfld.long 0xC 14. "AIE,Abnormal Interrupt Summary Enable When this bit is set the abnormal interrupt summary is enabled. This bit enables the following interrupts in the DMA_CH0_Status register: - Bit 1: Transmit Process Stopped - Bit 7: Rx Buffer Unavailable - Bit 8:.." "Abnormal Interrupt Summary is disabled,Abnormal Interrupt Summary is enabled" newline bitfld.long 0xC 13. "CDEE,Context Descriptor Error Enable When this bit is set along with the AIE bit the Descriptor error interrupt is enabled. When this bit is reset the Descriptor error interrupt is disabled. 0x0: Context Descriptor Error is disabled 0x1: Context.." "Context Descriptor Error is disabled,Context Descriptor Error is enabled" newline bitfld.long 0xC 12. "FBEE,Fatal Bus Error Enable When this bit is set along with the AIE bit the Fatal Bus error interrupt is enabled. When this bit is reset the Fatal Bus Error error interrupt is disabled. 0x0: Fatal Bus Error is disabled 0x1: Fatal Bus Error is enabled" "Fatal Bus Error is disabled,Fatal Bus Error is enabled" newline bitfld.long 0xC 11. "ERIE,Early Receive Interrupt Enable When this bit is set along with the NIE bit the Early Receive interrupt is enabled. When this bit is reset the Early Receive interrupt is disabled. 0x0: Early Receive Interrupt is disabled 0x1: Early Receive.." "Early Receive Interrupt is disabled,Early Receive Interrupt is enabled" newline bitfld.long 0xC 10. "ETIE,Early Transmit Interrupt Enable When this bit is set along with the AIE bit the Early Transmit interrupt is enabled. When this bit is reset the Early Transmit interrupt is disabled. 0x0: Early Transmit Interrupt is disabled 0x1: Early Transmit.." "Early Transmit Interrupt is disabled,Early Transmit Interrupt is enabled" newline bitfld.long 0xC 9. "RWTE,Receive Watchdog Timeout Enable When this bit is set along with the AIE bit the Receive Watchdog Timeout interrupt is enabled. When this bit is reset the Receive Watchdog Timeout interrupt is disabled. 0x0: Receive Watchdog Timeout is disabled.." "Receive Watchdog Timeout is disabled,Receive Watchdog Timeout is enabled" newline bitfld.long 0xC 8. "RSE,Receive Stopped Enable When this bit is set along with the AIE bit the Receive Stopped Interrupt is enabled. When this bit is reset the Receive Stopped interrupt is disabled. 0x0: Receive Stopped is disabled 0x1: Receive Stopped is enabled" "Receive Stopped is disabled,Receive Stopped is enabled" newline bitfld.long 0xC 7. "RBUE,Receive Buffer Unavailable Enable When this bit is set along with the AIE bit the Receive Buffer Unavailable interrupt is enabled. When this bit is reset the Receive Buffer Unavailable interrupt is disabled. 0x0: Receive Buffer Unavailable is.." "Receive Buffer Unavailable is disabled,Receive Buffer Unavailable is enabled" newline bitfld.long 0xC 6. "RIE,Receive Interrupt Enable When this bit is set along with the NIE bit the Receive Interrupt is enabled. When this bit is reset the Receive Interrupt is disabled. 0x0: Receive Interrupt is disabled 0x1: Receive Interrupt is enabled" "Receive Interrupt is disabled,Receive Interrupt is enabled" newline rbitfld.long 0xC 3.--5. "RESERVED_5_3,Reserved." "0,1,2,3,4,5,6,7" newline bitfld.long 0xC 2. "TBUE,Transmit Buffer Unavailable Enable When this bit is set along with the NIE bit the Transmit Buffer Unavailable interrupt is enabled. When this bit is reset the Transmit Buffer Unavailable interrupt is disabled. 0x0: Transmit Buffer Unavailable is.." "Transmit Buffer Unavailable is disabled,Transmit Buffer Unavailable is enabled" newline bitfld.long 0xC 1. "TXSE,Transmit Stopped Enable When this bit is set along with the AIE bit the Transmission Stopped interrupt is enabled. When this bit is reset the Transmission Stopped interrupt is disabled. 0x0: Transmit Stopped is disabled 0x1: Transmit Stopped is.." "Transmit Stopped is disabled,Transmit Stopped is enabled" newline bitfld.long 0xC 0. "TIE,Transmit Interrupt Enable When this bit is set along with the NIE bit the Transmit Interrupt is enabled. When this bit is reset the Transmit Interrupt is disabled. 0x0: Transmit Interrupt is disabled 0x1: Transmit Interrupt is enabled" "Transmit Interrupt is disabled,Transmit Interrupt is enabled" line.long 0x10 "DMA_CH2_RX_INTERRUPT_WATCHDOG_TIMER,The Receive Interrupt Watchdog Timer register indicates the watchdog timeout for Receive Interrupt (RI) from the DMA. When this register is written with a non-zero value. it enables the watchdog timer for the RI bit of.." hexmask.long.word 0x10 18.--31. 1. "RESERVED_31_18,Reserved." newline bitfld.long 0x10 16.--17. "RWTU,Receive Interrupt Watchdog Timer Count Units This fields indicates the number of system clock cycles corresponding to one unit in RWT field. - 2'b00: 256 - 2'b01: 512 - 2'b10: 1024 - 2'b11: 2048 For example when RWT=2 and RWTU=1 the watchdog timer.." "0,1,2,3" newline hexmask.long.byte 0x10 8.--15. 1. "RESERVED_15_8,Reserved." newline hexmask.long.byte 0x10 0.--7. 1. "RWT,Receive Interrupt Watchdog Timer Count This field indicates the number of system clock cycles multiplied by factor indicated in RWTU field for which the watchdog timer is set. The watchdog timer is triggered with the programmed value after the Rx.." line.long 0x14 "DMA_CH2_SLOT_FUNCTION_CONTROL_STATUS,The Slot Function Control and Status register contains the control bits for slot function and the status for Transmit path." hexmask.long.word 0x14 20.--31. 1. "RESERVED_31_20,Reserved." newline hexmask.long.byte 0x14 16.--19. 1. "RSN,Reference Slot Number This field gives the current value of the reference slot number in the DMA. It is used for slot comparison." newline hexmask.long.word 0x14 4.--15. 1. "SIV,Slot Interval Value This field controls the period of the slot interval in which the TxDMA fetches the scheduled packets. A value of 0 specifies the slot interval of 1 us while the maximum value 4095 specifies the slot interval of 4096us. The.." newline rbitfld.long 0x14 2.--3. "RESERVED_3_2,Reserved." "0,1,2,3" newline bitfld.long 0x14 1. "ASC,Advance Slot Check When set this bit enables the DMA to fetch the data from the buffer when the slot number (SLOTNUM) programmed in the Tx descriptor is - equal to the reference slot number given in the RSN field or - ahead of the reference slot.." "Advance Slot Check is disabled,Advance Slot Check is enabled" newline bitfld.long 0x14 0. "ESC,Enable Slot Comparison When set this bit enables the checking of the slot numbers programmed in the Tx descriptor with the current reference given in the RSN field. The DMA fetches the data from the corresponding buffer only when the slot number is.." "Slot Comparison is disabled,Slot Comparison is enabled" rgroup.long 0x44++0x3 line.long 0x0 "DMA_CH2_CURRENT_APP_TXDESC,The Channeli Current Application Transmit Descriptor register points to the current Transmit descriptor read by the DMA." hexmask.long 0x0 0.--31. 1. "CURTDESAPTR,Application Transmit Descriptor Address Pointer The DMA updates this pointer during Tx operation. This pointer is cleared on reset." rgroup.long 0x4C++0x13 line.long 0x0 "DMA_CH2_CURRENT_APP_RXDESC,The Channeli Current Application Receive Descriptor register points to the current Receive descriptor read by the DMA." hexmask.long 0x0 0.--31. 1. "CURRDESAPTR,Application Receive Descriptor Address Pointer The DMA updates this pointer during Rx operation. This pointer is cleared on reset." line.long 0x4 "DMA_CH2_CURRENT_APP_TXBUFFER_H,The Channeli Current Application Transmit Buffer Address High register has the higher 8 or 16 bits of the current address of the Transmit buffer address read by the DMA." hexmask.long.tbyte 0x4 8.--31. 1. "RESERVED_31_Y,Reserved." newline hexmask.long.byte 0x4 0.--7. 1. "CURTBUFAPTRH,Application Transmit Buffer Address Pointer The DMA updates this pointer during Tx operation. This pointer is cleared on reset." line.long 0x8 "DMA_CH2_CURRENT_APP_TXBUFFER,The Channeli Current Application Transmit Buffer Address register points to the current Tx buffer address read by the DMA." hexmask.long 0x8 0.--31. 1. "CURTBUFAPTR,Application Transmit Buffer Address Pointer The DMA updates this pointer during Tx operation. This pointer is cleared on reset." line.long 0xC "DMA_CH2_CURRENT_APP_RXBUFFER_H,The Channeli Current Application Receive Buffer Address High register has the higher 8 or 16 bits of the current address of the Receive buffer address read by the DMA." hexmask.long.tbyte 0xC 8.--31. 1. "RESERVED_31_Y,Reserved." newline hexmask.long.byte 0xC 0.--7. 1. "CURRBUFAPTRH,Application Receive Buffer Address Pointer The DMA updates this pointer during Rx operation. This pointer is cleared on reset." line.long 0x10 "DMA_CH2_CURRENT_APP_RXBUFFER,The Channel 0 Current Application Receive Buffer Address register points to the current Rx buffer address read by the DMA." hexmask.long 0x10 0.--31. 1. "CURRBUFAPTR,Application Receive Buffer Address Pointer The DMA updates this pointer during Rx operation. This pointer is cleared on reset." group.long 0x60++0x3 line.long 0x0 "DMA_CH2_STATUS,The software driver (application) reads the Status register during interrupt service routine or polling to determine the status of the DMA. Note: The number of DMA_CH[n]_Status register in the configuration is the higher of number of Rx.." hexmask.long.word 0x0 22.--31. 1. "RESERVED_31_22,Reserved." newline rbitfld.long 0x0 19.--21. "REB,Rx DMA Error Bits This field indicates the type of error that caused a Bus Error. For example error response on the AHB or AXI interface. - Bit 21 -- 1'b1: Error during data transfer by Rx DMA -- 1'b0: No Error during data transfer by Rx DMA - Bit.." "Error during write transfer,Error during read transfer,?,?,?,?,?,?" newline rbitfld.long 0x0 16.--18. "TEB,Tx DMA Error Bits This field indicates the type of error that caused a Bus Error. For example error response on the AHB or AXI interface. - Bit 18 -- 1'b1: Error during data transfer by Tx DMA -- 1'b0: No Error during data transfer by Tx DMA - Bit.." "Error during write transfer,Error during read transfer,?,?,?,?,?,?" newline bitfld.long 0x0 15. "NIS,Normal Interrupt Summary Normal Interrupt Summary bit value is the logical OR of the following bits when the corresponding interrupt bits are enabled in the DMA_CH0_Interrupt_Enable register: - Bit 0: Transmit Interrupt - Bit 2: Transmit Buffer.." "Normal Interrupt Summary status not detected,Normal Interrupt Summary status detected" newline bitfld.long 0x0 14. "AIS,Abnormal Interrupt Summary Abnormal Interrupt Summary bit value is the logical OR of the following when the corresponding interrupt bits are enabled in the DMA_CH0_Interrupt_Enable register: - Bit 1: Transmit Process Stopped - Bit 7: Receive Buffer.." "Abnormal Interrupt Summary status not detected,Abnormal Interrupt Summary status detected" newline bitfld.long 0x0 13. "CDE,Context Descriptor Error This bit indicates that the DMA Tx/Rx engine received a descriptor error which indicates invalid context in the middle of packet flow ( intermediate descriptor) or all one's descriptor in Tx case and on Rx side it indicates.." "Context Descriptor Error status not detected,Context Descriptor Error status detected" newline bitfld.long 0x0 12. "FBE,Fatal Bus Error This bit indicates that a bus error occurred (as described in the EB field). When this bit is set the corresponding DMA channel engine disables all bus accesses. Access restriction applies. Self-set to 1 on internal event. Setting 1.." "Fatal Bus Error status not detected,Fatal Bus Error status detected" newline bitfld.long 0x0 11. "ERI,Early Receive Interrupt This bit when set indicates that the RxDMA has completed the transfer of packet data to the memory. In configs supporting ERIC When ERIC=0 this bit is set only after the Rx DMA has filled up a complete receive buffer with.." "Early Receive Interrupt status not detected,Early Receive Interrupt status detected" newline bitfld.long 0x0 10. "ETI,Early Transmit Interrupt This bit when set indicates that the TxDMA has completed the transfer of packet data to the MTL TXFIFO memory. In configs supporting ERIC: When ETIC=0 this bit is set only after the Tx DMA has transferred a complete packet.." "Early Transmit Interrupt status not detected,Early Transmit Interrupt status detected" newline bitfld.long 0x0 9. "RWT,Receive Watchdog Timeout This bit is asserted when a packet with length greater than 2 048 bytes (10 240 bytes when Jumbo Packet mode is enabled) is received. 0x1: Receive Watchdog Timeout status detected 0x0: Receive Watchdog Timeout status not.." "Receive Watchdog Timeout status not detected,Receive Watchdog Timeout status detected" newline bitfld.long 0x0 8. "RPS,Receive Process Stopped This bit is asserted when the Rx process enters the Stopped state. Access restriction applies. Self-set to 1 on internal event. Setting 1 clears. Setting 0 has no effect. 0x1: Receive Process Stopped status detected 0x0:.." "Receive Process Stopped status not detected,Receive Process Stopped status detected" newline bitfld.long 0x0 7. "RBU,Receive Buffer Unavailable This bit indicates that the application owns the next descriptor in the Receive list and the DMA cannot acquire it. The Rx process is suspended. To resume processing Rx descriptors the application should change the.." "Receive Buffer Unavailable status not detected,Receive Buffer Unavailable status detected" newline bitfld.long 0x0 6. "RI,Receive Interrupt This bit indicates that the packet reception is complete. When packet reception is complete Bit 31 of RDES3 is reset in the last descriptor and the specific packet status information is updated in the descriptor. The reception.." "Receive Interrupt status not detected,Receive Interrupt status detected" newline rbitfld.long 0x0 3.--5. "RESERVED_5_3,Reserved." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 2. "TBU,Transmit Buffer Unavailable This bit indicates that the application owns the next descriptor in the Transmit list and the DMA cannot acquire it. Transmission is suspended. The TPS0 field of the DMA_Debug_Status0 register explains the Transmit.." "Transmit Buffer Unavailable status not detected,Transmit Buffer Unavailable status detected" newline bitfld.long 0x0 1. "TPS,Transmit Process Stopped This bit is set when the transmission is stopped. Access restriction applies. Self-set to 1 on internal event. Setting 1 clears. Setting 0 has no effect. 0x1: Transmit Process Stopped status detected 0x0: Transmit Process.." "Transmit Process Stopped status not detected,Transmit Process Stopped status detected" newline bitfld.long 0x0 0. "TI,Transmit Interrupt This bit indicates that the packet transmission is complete. When transmission is complete Bit 31 of TDES3 is reset in the last descriptor and the specific packet status information is updated in the descriptor. Access restriction.." "Transmit Interrupt status not detected,Transmit Interrupt status detected" rgroup.long 0x64++0xB line.long 0x0 "DMA_CH2_MISS_FRAME_CNT,This register has the number of packet counter that got dropped by the DMA either due to Bus Error or due to programming RPF field in DMA_CH{i}_Rx_Control register." hexmask.long.word 0x0 16.--31. 1. "RESERVED_31_16,Reserved." newline bitfld.long 0x0 15. "MFCO,Overflow status of the MFC Counter When this bit is set then the MFC counter does not get incremented further. The bit gets cleared when this register is read. Access restriction applies. Clears on read. Self-set to 1 on internal event. 0x1: Miss.." "Miss Frame Counter overflow not occurred,Miss Frame Counter overflow occurred" newline hexmask.long.byte 0x0 11.--14. 1. "RESERVED_14_11,Reserved." newline hexmask.long.word 0x0 0.--10. 1. "MFC,Dropped Packet Counters This counter indicates the number of packet counters that are dropped by the DMA either because of bus error or because of programing RPF field in DMA_CH{i}_Rx_Control register. The counter gets cleared when this register is.." line.long 0x4 "DMA_CH2_RXP_ACCEPT_CNT,The DMA_CH(#i)_RXP_Accept_Cnt registers provides the count of the number of frames accepted by Rx Parser." bitfld.long 0x4 31. "RXPACOF,Rx Parser Accept Counter Overflow Bit When set this bit indicates that the RXPAC Counter field crossed the maximum limit. Access restriction applies. Clears on read. Self-set to 1 on internal event. 0x1: Rx Parser Accept Counter overflow.." "Rx Parser Accept Counter overflow not occurred,Rx Parser Accept Counter overflow occurred" newline hexmask.long 0x4 0.--30. 1. "RXPAC,Rx Parser Accept Counter This 31-bit counter is implemented whenever a Rx Parser Accept a packet due to AF =1. The counter is cleared when the register is read." line.long 0x8 "DMA_CH2_RX_ERI_CNT,The DMA_CH(#i)_RX_ERI_Cnt registers provides the count of the number of times ERI was asserted." hexmask.long.tbyte 0x8 12.--31. 1. "RESERVED_31_12," newline hexmask.long.word 0x8 0.--11. 1. "ECNT,ERI Counter When ERIC bit of DMA_CH(#i)_RX_Control register is set this counter increments for burst transfer completed by the Rx DMA from the start of packet transfer. This counter will get reset at the start of new packet." tree.end tree "EQOS_DMA_CH3" group.long 0x0++0xB line.long 0x0 "DMA_CH3_CONTROL,The DMA Channeli Control register specifies the MSS value for segmentation. length to skip between two descriptors. and also the features such as header splitting and 8xPBL mode." hexmask.long.byte 0x0 25.--31. 1. "RESERVED_31_25,Reserved." newline rbitfld.long 0x0 24. "RESERVED_SPH,Reserved." "0,1" newline rbitfld.long 0x0 21.--23. "RESERVED_23_21,Reserved." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 18.--20. "DSL,Descriptor Skip Length This bit specifies the Word Dword or Lword number (depending on the 32-bit 64-bit or 128-bit bus) to skip between two unchained descriptors. The address skipping starts from the end of the current descriptor to the start of.." "0,1,2,3,4,5,6,7" newline rbitfld.long 0x0 17. "RESERVED_17,Reserved." "0,1" newline bitfld.long 0x0 16. "PBLX8,8xPBL mode When this bit is set the PBL value programmed in Bits[21:16] in DMA_CH0_Tx_Control and Bits[21:16] in DMA_CH0_Rx_Control is multiplied by eight times. Therefore the DMA transfers the data in 8 16 32 64 128 and 256 beats depending.." "0,1" newline rbitfld.long 0x0 14.--15. "RESERVED_15_14,Reserved." "0,1,2,3" newline hexmask.long.word 0x0 0.--13. 1. "RESERVED_MSS,Reserved." line.long 0x4 "DMA_CH3_TX_CONTROL,The DMA Channeli Transmit Control register controls the Tx features such as PBL. TCP segmentation. and Tx Channel weights." rbitfld.long 0x4 29.--31. "RESERVED_31_29,Reserved." "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 28. "EDSE,Enhanced Descriptor Enable When this bit is set the corresponding channel uses Enhanced Descriptors that are 32 Bytes for both Normal and Context Descriptors. When reset the corresponding channel uses the descriptors that are 16 Bytes. 0x0:.." "Enhanced Descriptor is disabled,Enhanced Descriptor is enabled" newline hexmask.long.byte 0x4 24.--27. 1. "TQOS,Transmit QOS. This field is used to drive arqos_m_o[3:0] or awqos_m_o[3:0] output signals for all transactions of DMA Tx Channel0." newline rbitfld.long 0x4 23. "RESERVED_23,Reserved." "0,1" newline rbitfld.long 0x4 22. "RESERVED_ETIC,Reserved." "0,1" newline hexmask.long.byte 0x4 16.--21. 1. "TXPBL,Transmit Programmable Burst Length These bits indicate the maximum number of beats to be transferred in one DMA block data transfer. The DMA always attempts max burst as specified in PBL each time it starts a burst transfer on the application bus." newline bitfld.long 0x4 15. "IPBL,Ignore PBL Requirement When this bit is set the DMA does not check for PBL number of locations in the MTL before initiating a transfer. If space is not available the MTL may use handshaking to slow the DMA. Note: This bit/mode must not be used.." "Ignore PBL Requirement is disabled,Ignore PBL Requirement is enabled" newline rbitfld.long 0x4 13.--14. "RESERVED_TSE_MODE,Reserved." "0,1,2,3" newline rbitfld.long 0x4 12. "RESERVED_TSE,Reserved." "0,1" newline hexmask.long.byte 0x4 5.--11. 1. "RESERVED_11_5,Reserved." newline bitfld.long 0x4 4. "OSF,Operate on Second Packet When this bit is set it instructs the DMA to process the second packet of the Transmit data even before the status for the first packet is obtained. 0x0: Operate on Second Packet disabled 0x1: Operate on Second Packet enabled" "Operate on Second Packet disabled,Operate on Second Packet enabled" newline rbitfld.long 0x4 1.--3. "RESERVED_TCW,Reserved." "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 0. "ST,Start or Stop Transmission Command When this bit is set transmission is placed in the Running state. The DMA checks the Transmit list at the current position for a packet to be transmitted. The DMA tries to acquire descriptor from either of the.." "Stop Transmission Command,Start Transmission Command" line.long 0x8 "DMA_CH3_RX_CONTROL,The DMA Channeli Receive Control register controls the Rx features such as PBL. buffer size. and extended status." bitfld.long 0x8 31. "RPF,Rx Packet Flush. When this bit is set to 1 then DWC_ether_qos automatically flushes the packet from the Rx Queues destined to this DMA Rx Channel when it is stopped. When this bit remains set and the DMA is re-started by the software driver the.." "Rx Packet Flush is disabled,Rx Packet Flush is enabled" newline rbitfld.long 0x8 28.--30. "RESERVED_30_28,Reserved." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x8 24.--27. 1. "RQOS,Rx AXI4 QOS. This field is used to drive arqos_m_o[3:0] or awqos_m_o[3:0] output signals for all transactions of DMA Rx Channel0." newline rbitfld.long 0x8 23. "RESERVED_23,Reserved." "0,1" newline rbitfld.long 0x8 22. "RESERVED_ERIC,Reserved." "0,1" newline hexmask.long.byte 0x8 16.--21. 1. "RXPBL,Receive Programmable Burst Length These bits indicate the maximum number of beats to be transferred in one DMA block data transfer. The DMA always attempts max burst as specified in PBL each time it starts a burst transfer on the application bus." newline rbitfld.long 0x8 15. "RESERVED_15,Reserved." "0,1" newline hexmask.long.word 0x8 5.--14. 1. "RBSZ_13_Y,Receive Buffer size High RBSZ[13:0] is split into two fields higher RBSZ_13_y and lower RBSZ_x_0. The RBSZ[13:0] field indicates the size of the Rx buffers specified in bytes. The maximum buffer size is limited to 16K bytes. The buffer size is.." newline hexmask.long.byte 0x8 1.--4. 1. "RBSZ_X_0,Receive Buffer size Low RBSZ[13:0] is split into two fields RBSZ_13_y and RBSZ_x_0. The RBSZ_x_0 is the lower field whose width is based on data bus width of the configuration. This field is of width 2 3 or 4 bits for 32-bit 64-bit or.." newline bitfld.long 0x8 0. "SR,Start or Stop Receive When this bit is set the DMA tries to acquire the descriptor from the Receive list and processes the incoming packets. The DMA tries to acquire descriptor from either of the following positions: - The current position in the.." "Stop Receive,Start Receive" group.long 0x10++0x13 line.long 0x0 "DMA_CH3_TXDESC_LIST_HADDRESS,The Channeli Tx Descriptor List HAddress register has the higher 8 or 16 bits of the start address of the Transmit descriptor list. You can write to this register only when the Tx DMA has stopped. that is. the ST bit is set.." hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED_31_Y,Reserved." newline hexmask.long.byte 0x0 0.--7. 1. "TDESHA,Start of Transmit List This field contains the most-significant 8 or 16 bits of the 40- or 48-bit base address of the first descriptor in the Transmit descriptor list." line.long 0x4 "DMA_CH3_TXDESC_LIST_ADDRESS,The Channeli Tx Descriptor List Address register points the DMA to the start of Transmit descriptor list. The descriptor lists reside in the physical memory space of the application and must be Word. Dword. or Lword-aligned.." hexmask.long 0x4 4.--31. 1. "TDESLA,Start of Transmit List This field contains the base address of the first descriptor in the Transmit descriptor list. The DMA ignores the LSB bits (1:0 2:0 or 3:0) for 32-bit 64-bit or 128-bit bus width and internally takes these bits as.." newline hexmask.long.byte 0x4 0.--3. 1. "RESERVED_LSB," line.long 0x8 "DMA_CH3_RXDESC_LIST_HADDRESS,The Channeli Rx Descriptor List HAddress register has the higher 8 or 16 bits of the start address of the Receive descriptor list. Writing to this register is permitted only when reception is stopped. When stopped. this.." hexmask.long.tbyte 0x8 8.--31. 1. "RESERVED_31_Y,Reserved." newline hexmask.long.byte 0x8 0.--7. 1. "RDESHA,Start of Receive List This field contains the most-significant 8 or 16 bits of the 40-bit or 48-bit base address of the first descriptor in the Rx Descriptor list." line.long 0xC "DMA_CH3_RXDESC_LIST_ADDRESS,The Channeli Rx Descriptor List Address register points the DMA to the start of Receive descriptor list. This register points to the start of the Receive Descriptor List. The descriptor lists reside in the physical memory.." hexmask.long 0xC 4.--31. 1. "RDESLA,Start of Receive List This field contains the base address of the first descriptor in the Rx Descriptor list. The DMA ignores the LSB bits (1:0 2:0 or 3:0) for 32-bit 64-bit or 128-bit bus width and internally takes these bits as all-zero." newline hexmask.long.byte 0xC 0.--3. 1. "RESERVED_LSB," line.long 0x10 "DMA_CH3_TXDESC_TAIL_POINTER,The Channeli Tx Descriptor Tail Pointer register points to an offset from the base and indicates the location of the last valid descriptor." hexmask.long 0x10 4.--31. 1. "TDTP,Transmit Descriptor Tail Pointer This field contains the tail pointer for the Tx descriptor ring. The software writes the tail pointer to add more descriptors to the Tx channel. The hardware tries to transmit all packets referenced by the.." newline hexmask.long.byte 0x10 0.--3. 1. "RESERVED_LSB," group.long 0x28++0x17 line.long 0x0 "DMA_CH3_RXDESC_TAIL_POINTER,The Channeli Rx Descriptor Tail Pointer Points to an offset from the base and indicates the location of the last valid descriptor." hexmask.long 0x0 4.--31. 1. "RDTP,Receive Descriptor Tail Pointer This field contains the tail pointer for the Rx descriptor ring. The software writes the tail pointer to add more descriptors to the Rx channel. The hardware tries to write all received packets to the descriptors.." newline hexmask.long.byte 0x0 0.--3. 1. "RESERVED_LSB," line.long 0x4 "DMA_CH3_TXDESC_RING_LENGTH,The Tx Descriptor Ring Length register contains the length of the Transmit descriptor ring." hexmask.long.tbyte 0x4 10.--31. 1. "RESERVED_31_10,Reserved." newline hexmask.long.word 0x4 0.--9. 1. "TDRL,Transmit Descriptor Ring Length This field sets the maximum number of Tx descriptors in the circular descriptor ring. The maximum number of descriptors is limited to 1K descriptors. Synopsys recommends a minimum ring descriptor length of 4. For.." line.long 0x8 "DMA_CH3_RXDESC_RING_LENGTH,The Channeli Rx Descriptor Ring Length register contains the length of the Receive descriptor circular ring." hexmask.long.tbyte 0x8 10.--31. 1. "RESERVED_31_10,Reserved." newline hexmask.long.word 0x8 0.--9. 1. "RDRL,Receive Descriptor Ring Length This register sets the maximum number of Rx descriptors in the circular descriptor ring. The maximum number of descriptors is limited to 1K descriptors. For example You can program any value up to 0x3FF in this field." line.long 0xC "DMA_CH3_INTERRUPT_ENABLE,The Channeli Interrupt Enable register enables the interrupts reported by the Status register." hexmask.long.word 0xC 16.--31. 1. "RESERVED_31_16,Reserved." newline bitfld.long 0xC 15. "NIE,Normal Interrupt Summary Enable When this bit is set the normal interrupt summary is enabled. This bit enables the following interrupts in the DMA_CH0_Status register: - Bit 0: Transmit Interrupt - Bit 2: Transmit Buffer Unavailable - Bit 6: Receive.." "Normal Interrupt Summary is disabled,Normal Interrupt Summary is enabled" newline bitfld.long 0xC 14. "AIE,Abnormal Interrupt Summary Enable When this bit is set the abnormal interrupt summary is enabled. This bit enables the following interrupts in the DMA_CH0_Status register: - Bit 1: Transmit Process Stopped - Bit 7: Rx Buffer Unavailable - Bit 8:.." "Abnormal Interrupt Summary is disabled,Abnormal Interrupt Summary is enabled" newline bitfld.long 0xC 13. "CDEE,Context Descriptor Error Enable When this bit is set along with the AIE bit the Descriptor error interrupt is enabled. When this bit is reset the Descriptor error interrupt is disabled. 0x0: Context Descriptor Error is disabled 0x1: Context.." "Context Descriptor Error is disabled,Context Descriptor Error is enabled" newline bitfld.long 0xC 12. "FBEE,Fatal Bus Error Enable When this bit is set along with the AIE bit the Fatal Bus error interrupt is enabled. When this bit is reset the Fatal Bus Error error interrupt is disabled. 0x0: Fatal Bus Error is disabled 0x1: Fatal Bus Error is enabled" "Fatal Bus Error is disabled,Fatal Bus Error is enabled" newline bitfld.long 0xC 11. "ERIE,Early Receive Interrupt Enable When this bit is set along with the NIE bit the Early Receive interrupt is enabled. When this bit is reset the Early Receive interrupt is disabled. 0x0: Early Receive Interrupt is disabled 0x1: Early Receive.." "Early Receive Interrupt is disabled,Early Receive Interrupt is enabled" newline bitfld.long 0xC 10. "ETIE,Early Transmit Interrupt Enable When this bit is set along with the AIE bit the Early Transmit interrupt is enabled. When this bit is reset the Early Transmit interrupt is disabled. 0x0: Early Transmit Interrupt is disabled 0x1: Early Transmit.." "Early Transmit Interrupt is disabled,Early Transmit Interrupt is enabled" newline bitfld.long 0xC 9. "RWTE,Receive Watchdog Timeout Enable When this bit is set along with the AIE bit the Receive Watchdog Timeout interrupt is enabled. When this bit is reset the Receive Watchdog Timeout interrupt is disabled. 0x0: Receive Watchdog Timeout is disabled.." "Receive Watchdog Timeout is disabled,Receive Watchdog Timeout is enabled" newline bitfld.long 0xC 8. "RSE,Receive Stopped Enable When this bit is set along with the AIE bit the Receive Stopped Interrupt is enabled. When this bit is reset the Receive Stopped interrupt is disabled. 0x0: Receive Stopped is disabled 0x1: Receive Stopped is enabled" "Receive Stopped is disabled,Receive Stopped is enabled" newline bitfld.long 0xC 7. "RBUE,Receive Buffer Unavailable Enable When this bit is set along with the AIE bit the Receive Buffer Unavailable interrupt is enabled. When this bit is reset the Receive Buffer Unavailable interrupt is disabled. 0x0: Receive Buffer Unavailable is.." "Receive Buffer Unavailable is disabled,Receive Buffer Unavailable is enabled" newline bitfld.long 0xC 6. "RIE,Receive Interrupt Enable When this bit is set along with the NIE bit the Receive Interrupt is enabled. When this bit is reset the Receive Interrupt is disabled. 0x0: Receive Interrupt is disabled 0x1: Receive Interrupt is enabled" "Receive Interrupt is disabled,Receive Interrupt is enabled" newline rbitfld.long 0xC 3.--5. "RESERVED_5_3,Reserved." "0,1,2,3,4,5,6,7" newline bitfld.long 0xC 2. "TBUE,Transmit Buffer Unavailable Enable When this bit is set along with the NIE bit the Transmit Buffer Unavailable interrupt is enabled. When this bit is reset the Transmit Buffer Unavailable interrupt is disabled. 0x0: Transmit Buffer Unavailable is.." "Transmit Buffer Unavailable is disabled,Transmit Buffer Unavailable is enabled" newline bitfld.long 0xC 1. "TXSE,Transmit Stopped Enable When this bit is set along with the AIE bit the Transmission Stopped interrupt is enabled. When this bit is reset the Transmission Stopped interrupt is disabled. 0x0: Transmit Stopped is disabled 0x1: Transmit Stopped is.." "Transmit Stopped is disabled,Transmit Stopped is enabled" newline bitfld.long 0xC 0. "TIE,Transmit Interrupt Enable When this bit is set along with the NIE bit the Transmit Interrupt is enabled. When this bit is reset the Transmit Interrupt is disabled. 0x0: Transmit Interrupt is disabled 0x1: Transmit Interrupt is enabled" "Transmit Interrupt is disabled,Transmit Interrupt is enabled" line.long 0x10 "DMA_CH3_RX_INTERRUPT_WATCHDOG_TIMER,The Receive Interrupt Watchdog Timer register indicates the watchdog timeout for Receive Interrupt (RI) from the DMA. When this register is written with a non-zero value. it enables the watchdog timer for the RI bit of.." hexmask.long.word 0x10 18.--31. 1. "RESERVED_31_18,Reserved." newline bitfld.long 0x10 16.--17. "RWTU,Receive Interrupt Watchdog Timer Count Units This fields indicates the number of system clock cycles corresponding to one unit in RWT field. - 2'b00: 256 - 2'b01: 512 - 2'b10: 1024 - 2'b11: 2048 For example when RWT=2 and RWTU=1 the watchdog timer.." "0,1,2,3" newline hexmask.long.byte 0x10 8.--15. 1. "RESERVED_15_8,Reserved." newline hexmask.long.byte 0x10 0.--7. 1. "RWT,Receive Interrupt Watchdog Timer Count This field indicates the number of system clock cycles multiplied by factor indicated in RWTU field for which the watchdog timer is set. The watchdog timer is triggered with the programmed value after the Rx.." line.long 0x14 "DMA_CH3_SLOT_FUNCTION_CONTROL_STATUS,The Slot Function Control and Status register contains the control bits for slot function and the status for Transmit path." hexmask.long.word 0x14 20.--31. 1. "RESERVED_31_20,Reserved." newline hexmask.long.byte 0x14 16.--19. 1. "RSN,Reference Slot Number This field gives the current value of the reference slot number in the DMA. It is used for slot comparison." newline hexmask.long.word 0x14 4.--15. 1. "SIV,Slot Interval Value This field controls the period of the slot interval in which the TxDMA fetches the scheduled packets. A value of 0 specifies the slot interval of 1 us while the maximum value 4095 specifies the slot interval of 4096us. The.." newline rbitfld.long 0x14 2.--3. "RESERVED_3_2,Reserved." "0,1,2,3" newline bitfld.long 0x14 1. "ASC,Advance Slot Check When set this bit enables the DMA to fetch the data from the buffer when the slot number (SLOTNUM) programmed in the Tx descriptor is - equal to the reference slot number given in the RSN field or - ahead of the reference slot.." "Advance Slot Check is disabled,Advance Slot Check is enabled" newline bitfld.long 0x14 0. "ESC,Enable Slot Comparison When set this bit enables the checking of the slot numbers programmed in the Tx descriptor with the current reference given in the RSN field. The DMA fetches the data from the corresponding buffer only when the slot number is.." "Slot Comparison is disabled,Slot Comparison is enabled" rgroup.long 0x44++0x3 line.long 0x0 "DMA_CH3_CURRENT_APP_TXDESC,The Channeli Current Application Transmit Descriptor register points to the current Transmit descriptor read by the DMA." hexmask.long 0x0 0.--31. 1. "CURTDESAPTR,Application Transmit Descriptor Address Pointer The DMA updates this pointer during Tx operation. This pointer is cleared on reset." rgroup.long 0x4C++0x13 line.long 0x0 "DMA_CH3_CURRENT_APP_RXDESC,The Channeli Current Application Receive Descriptor register points to the current Receive descriptor read by the DMA." hexmask.long 0x0 0.--31. 1. "CURRDESAPTR,Application Receive Descriptor Address Pointer The DMA updates this pointer during Rx operation. This pointer is cleared on reset." line.long 0x4 "DMA_CH3_CURRENT_APP_TXBUFFER_H,The Channeli Current Application Transmit Buffer Address High register has the higher 8 or 16 bits of the current address of the Transmit buffer address read by the DMA." hexmask.long.tbyte 0x4 8.--31. 1. "RESERVED_31_Y,Reserved." newline hexmask.long.byte 0x4 0.--7. 1. "CURTBUFAPTRH,Application Transmit Buffer Address Pointer The DMA updates this pointer during Tx operation. This pointer is cleared on reset." line.long 0x8 "DMA_CH3_CURRENT_APP_TXBUFFER,The Channeli Current Application Transmit Buffer Address register points to the current Tx buffer address read by the DMA." hexmask.long 0x8 0.--31. 1. "CURTBUFAPTR,Application Transmit Buffer Address Pointer The DMA updates this pointer during Tx operation. This pointer is cleared on reset." line.long 0xC "DMA_CH3_CURRENT_APP_RXBUFFER_H,The Channeli Current Application Receive Buffer Address High register has the higher 8 or 16 bits of the current address of the Receive buffer address read by the DMA." hexmask.long.tbyte 0xC 8.--31. 1. "RESERVED_31_Y,Reserved." newline hexmask.long.byte 0xC 0.--7. 1. "CURRBUFAPTRH,Application Receive Buffer Address Pointer The DMA updates this pointer during Rx operation. This pointer is cleared on reset." line.long 0x10 "DMA_CH3_CURRENT_APP_RXBUFFER,The Channel 0 Current Application Receive Buffer Address register points to the current Rx buffer address read by the DMA." hexmask.long 0x10 0.--31. 1. "CURRBUFAPTR,Application Receive Buffer Address Pointer The DMA updates this pointer during Rx operation. This pointer is cleared on reset." group.long 0x60++0x3 line.long 0x0 "DMA_CH3_STATUS,The software driver (application) reads the Status register during interrupt service routine or polling to determine the status of the DMA. Note: The number of DMA_CH[n]_Status register in the configuration is the higher of number of Rx.." hexmask.long.word 0x0 22.--31. 1. "RESERVED_31_22,Reserved." newline rbitfld.long 0x0 19.--21. "REB,Rx DMA Error Bits This field indicates the type of error that caused a Bus Error. For example error response on the AHB or AXI interface. - Bit 21 -- 1'b1: Error during data transfer by Rx DMA -- 1'b0: No Error during data transfer by Rx DMA - Bit.." "Error during write transfer,Error during read transfer,?,?,?,?,?,?" newline rbitfld.long 0x0 16.--18. "TEB,Tx DMA Error Bits This field indicates the type of error that caused a Bus Error. For example error response on the AHB or AXI interface. - Bit 18 -- 1'b1: Error during data transfer by Tx DMA -- 1'b0: No Error during data transfer by Tx DMA - Bit.." "Error during write transfer,Error during read transfer,?,?,?,?,?,?" newline bitfld.long 0x0 15. "NIS,Normal Interrupt Summary Normal Interrupt Summary bit value is the logical OR of the following bits when the corresponding interrupt bits are enabled in the DMA_CH0_Interrupt_Enable register: - Bit 0: Transmit Interrupt - Bit 2: Transmit Buffer.." "Normal Interrupt Summary status not detected,Normal Interrupt Summary status detected" newline bitfld.long 0x0 14. "AIS,Abnormal Interrupt Summary Abnormal Interrupt Summary bit value is the logical OR of the following when the corresponding interrupt bits are enabled in the DMA_CH0_Interrupt_Enable register: - Bit 1: Transmit Process Stopped - Bit 7: Receive Buffer.." "Abnormal Interrupt Summary status not detected,Abnormal Interrupt Summary status detected" newline bitfld.long 0x0 13. "CDE,Context Descriptor Error This bit indicates that the DMA Tx/Rx engine received a descriptor error which indicates invalid context in the middle of packet flow ( intermediate descriptor) or all one's descriptor in Tx case and on Rx side it indicates.." "Context Descriptor Error status not detected,Context Descriptor Error status detected" newline bitfld.long 0x0 12. "FBE,Fatal Bus Error This bit indicates that a bus error occurred (as described in the EB field). When this bit is set the corresponding DMA channel engine disables all bus accesses. Access restriction applies. Self-set to 1 on internal event. Setting 1.." "Fatal Bus Error status not detected,Fatal Bus Error status detected" newline bitfld.long 0x0 11. "ERI,Early Receive Interrupt This bit when set indicates that the RxDMA has completed the transfer of packet data to the memory. In configs supporting ERIC When ERIC=0 this bit is set only after the Rx DMA has filled up a complete receive buffer with.." "Early Receive Interrupt status not detected,Early Receive Interrupt status detected" newline bitfld.long 0x0 10. "ETI,Early Transmit Interrupt This bit when set indicates that the TxDMA has completed the transfer of packet data to the MTL TXFIFO memory. In configs supporting ERIC: When ETIC=0 this bit is set only after the Tx DMA has transferred a complete packet.." "Early Transmit Interrupt status not detected,Early Transmit Interrupt status detected" newline bitfld.long 0x0 9. "RWT,Receive Watchdog Timeout This bit is asserted when a packet with length greater than 2 048 bytes (10 240 bytes when Jumbo Packet mode is enabled) is received. 0x1: Receive Watchdog Timeout status detected 0x0: Receive Watchdog Timeout status not.." "Receive Watchdog Timeout status not detected,Receive Watchdog Timeout status detected" newline bitfld.long 0x0 8. "RPS,Receive Process Stopped This bit is asserted when the Rx process enters the Stopped state. Access restriction applies. Self-set to 1 on internal event. Setting 1 clears. Setting 0 has no effect. 0x1: Receive Process Stopped status detected 0x0:.." "Receive Process Stopped status not detected,Receive Process Stopped status detected" newline bitfld.long 0x0 7. "RBU,Receive Buffer Unavailable This bit indicates that the application owns the next descriptor in the Receive list and the DMA cannot acquire it. The Rx process is suspended. To resume processing Rx descriptors the application should change the.." "Receive Buffer Unavailable status not detected,Receive Buffer Unavailable status detected" newline bitfld.long 0x0 6. "RI,Receive Interrupt This bit indicates that the packet reception is complete. When packet reception is complete Bit 31 of RDES3 is reset in the last descriptor and the specific packet status information is updated in the descriptor. The reception.." "Receive Interrupt status not detected,Receive Interrupt status detected" newline rbitfld.long 0x0 3.--5. "RESERVED_5_3,Reserved." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 2. "TBU,Transmit Buffer Unavailable This bit indicates that the application owns the next descriptor in the Transmit list and the DMA cannot acquire it. Transmission is suspended. The TPS0 field of the DMA_Debug_Status0 register explains the Transmit.." "Transmit Buffer Unavailable status not detected,Transmit Buffer Unavailable status detected" newline bitfld.long 0x0 1. "TPS,Transmit Process Stopped This bit is set when the transmission is stopped. Access restriction applies. Self-set to 1 on internal event. Setting 1 clears. Setting 0 has no effect. 0x1: Transmit Process Stopped status detected 0x0: Transmit Process.." "Transmit Process Stopped status not detected,Transmit Process Stopped status detected" newline bitfld.long 0x0 0. "TI,Transmit Interrupt This bit indicates that the packet transmission is complete. When transmission is complete Bit 31 of TDES3 is reset in the last descriptor and the specific packet status information is updated in the descriptor. Access restriction.." "Transmit Interrupt status not detected,Transmit Interrupt status detected" rgroup.long 0x64++0xB line.long 0x0 "DMA_CH3_MISS_FRAME_CNT,This register has the number of packet counter that got dropped by the DMA either due to Bus Error or due to programming RPF field in DMA_CH{i}_Rx_Control register." hexmask.long.word 0x0 16.--31. 1. "RESERVED_31_16,Reserved." newline bitfld.long 0x0 15. "MFCO,Overflow status of the MFC Counter When this bit is set then the MFC counter does not get incremented further. The bit gets cleared when this register is read. Access restriction applies. Clears on read. Self-set to 1 on internal event. 0x1: Miss.." "Miss Frame Counter overflow not occurred,Miss Frame Counter overflow occurred" newline hexmask.long.byte 0x0 11.--14. 1. "RESERVED_14_11,Reserved." newline hexmask.long.word 0x0 0.--10. 1. "MFC,Dropped Packet Counters This counter indicates the number of packet counters that are dropped by the DMA either because of bus error or because of programing RPF field in DMA_CH{i}_Rx_Control register. The counter gets cleared when this register is.." line.long 0x4 "DMA_CH3_RXP_ACCEPT_CNT,The DMA_CH(#i)_RXP_Accept_Cnt registers provides the count of the number of frames accepted by Rx Parser." bitfld.long 0x4 31. "RXPACOF,Rx Parser Accept Counter Overflow Bit When set this bit indicates that the RXPAC Counter field crossed the maximum limit. Access restriction applies. Clears on read. Self-set to 1 on internal event. 0x1: Rx Parser Accept Counter overflow.." "Rx Parser Accept Counter overflow not occurred,Rx Parser Accept Counter overflow occurred" newline hexmask.long 0x4 0.--30. 1. "RXPAC,Rx Parser Accept Counter This 31-bit counter is implemented whenever a Rx Parser Accept a packet due to AF =1. The counter is cleared when the register is read." line.long 0x8 "DMA_CH3_RX_ERI_CNT,The DMA_CH(#i)_RX_ERI_Cnt registers provides the count of the number of times ERI was asserted." hexmask.long.tbyte 0x8 12.--31. 1. "RESERVED_31_12," newline hexmask.long.word 0x8 0.--11. 1. "ECNT,ERI Counter When ERIC bit of DMA_CH(#i)_RX_Control register is set this counter increments for burst transfer completed by the Rx DMA from the start of packet transfer. This counter will get reset at the start of new packet." tree.end tree "EQOS_DMA_CH4" group.long 0x0++0xB line.long 0x0 "DMA_CH4_CONTROL,The DMA Channeli Control register specifies the MSS value for segmentation. length to skip between two descriptors. and also the features such as header splitting and 8xPBL mode." hexmask.long.byte 0x0 25.--31. 1. "RESERVED_31_25,Reserved." newline rbitfld.long 0x0 24. "RESERVED_SPH,Reserved." "0,1" newline rbitfld.long 0x0 21.--23. "RESERVED_23_21,Reserved." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 18.--20. "DSL,Descriptor Skip Length This bit specifies the Word Dword or Lword number (depending on the 32-bit 64-bit or 128-bit bus) to skip between two unchained descriptors. The address skipping starts from the end of the current descriptor to the start of.." "0,1,2,3,4,5,6,7" newline rbitfld.long 0x0 17. "RESERVED_17,Reserved." "0,1" newline bitfld.long 0x0 16. "PBLX8,8xPBL mode When this bit is set the PBL value programmed in Bits[21:16] in DMA_CH0_Tx_Control and Bits[21:16] in DMA_CH0_Rx_Control is multiplied by eight times. Therefore the DMA transfers the data in 8 16 32 64 128 and 256 beats depending.." "0,1" newline rbitfld.long 0x0 14.--15. "RESERVED_15_14,Reserved." "0,1,2,3" newline hexmask.long.word 0x0 0.--13. 1. "RESERVED_MSS,Reserved." line.long 0x4 "DMA_CH4_TX_CONTROL,The DMA Channeli Transmit Control register controls the Tx features such as PBL. TCP segmentation. and Tx Channel weights." rbitfld.long 0x4 29.--31. "RESERVED_31_29,Reserved." "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 28. "EDSE,Enhanced Descriptor Enable When this bit is set the corresponding channel uses Enhanced Descriptors that are 32 Bytes for both Normal and Context Descriptors. When reset the corresponding channel uses the descriptors that are 16 Bytes. 0x0:.." "Enhanced Descriptor is disabled,Enhanced Descriptor is enabled" newline hexmask.long.byte 0x4 24.--27. 1. "TQOS,Transmit QOS. This field is used to drive arqos_m_o[3:0] or awqos_m_o[3:0] output signals for all transactions of DMA Tx Channel0." newline rbitfld.long 0x4 23. "RESERVED_23,Reserved." "0,1" newline rbitfld.long 0x4 22. "RESERVED_ETIC,Reserved." "0,1" newline hexmask.long.byte 0x4 16.--21. 1. "TXPBL,Transmit Programmable Burst Length These bits indicate the maximum number of beats to be transferred in one DMA block data transfer. The DMA always attempts max burst as specified in PBL each time it starts a burst transfer on the application bus." newline bitfld.long 0x4 15. "IPBL,Ignore PBL Requirement When this bit is set the DMA does not check for PBL number of locations in the MTL before initiating a transfer. If space is not available the MTL may use handshaking to slow the DMA. Note: This bit/mode must not be used.." "Ignore PBL Requirement is disabled,Ignore PBL Requirement is enabled" newline rbitfld.long 0x4 13.--14. "RESERVED_TSE_MODE,Reserved." "0,1,2,3" newline rbitfld.long 0x4 12. "RESERVED_TSE,Reserved." "0,1" newline hexmask.long.byte 0x4 5.--11. 1. "RESERVED_11_5,Reserved." newline bitfld.long 0x4 4. "OSF,Operate on Second Packet When this bit is set it instructs the DMA to process the second packet of the Transmit data even before the status for the first packet is obtained. 0x0: Operate on Second Packet disabled 0x1: Operate on Second Packet enabled" "Operate on Second Packet disabled,Operate on Second Packet enabled" newline rbitfld.long 0x4 1.--3. "RESERVED_TCW,Reserved." "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 0. "ST,Start or Stop Transmission Command When this bit is set transmission is placed in the Running state. The DMA checks the Transmit list at the current position for a packet to be transmitted. The DMA tries to acquire descriptor from either of the.." "Stop Transmission Command,Start Transmission Command" line.long 0x8 "DMA_CH4_RX_CONTROL,The DMA Channeli Receive Control register controls the Rx features such as PBL. buffer size. and extended status." bitfld.long 0x8 31. "RPF,Rx Packet Flush. When this bit is set to 1 then DWC_ether_qos automatically flushes the packet from the Rx Queues destined to this DMA Rx Channel when it is stopped. When this bit remains set and the DMA is re-started by the software driver the.." "Rx Packet Flush is disabled,Rx Packet Flush is enabled" newline rbitfld.long 0x8 28.--30. "RESERVED_30_28,Reserved." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x8 24.--27. 1. "RQOS,Rx AXI4 QOS. This field is used to drive arqos_m_o[3:0] or awqos_m_o[3:0] output signals for all transactions of DMA Rx Channel0." newline rbitfld.long 0x8 23. "RESERVED_23,Reserved." "0,1" newline rbitfld.long 0x8 22. "RESERVED_ERIC,Reserved." "0,1" newline hexmask.long.byte 0x8 16.--21. 1. "RXPBL,Receive Programmable Burst Length These bits indicate the maximum number of beats to be transferred in one DMA block data transfer. The DMA always attempts max burst as specified in PBL each time it starts a burst transfer on the application bus." newline rbitfld.long 0x8 15. "RESERVED_15,Reserved." "0,1" newline hexmask.long.word 0x8 5.--14. 1. "RBSZ_13_Y,Receive Buffer size High RBSZ[13:0] is split into two fields higher RBSZ_13_y and lower RBSZ_x_0. The RBSZ[13:0] field indicates the size of the Rx buffers specified in bytes. The maximum buffer size is limited to 16K bytes. The buffer size is.." newline hexmask.long.byte 0x8 1.--4. 1. "RBSZ_X_0,Receive Buffer size Low RBSZ[13:0] is split into two fields RBSZ_13_y and RBSZ_x_0. The RBSZ_x_0 is the lower field whose width is based on data bus width of the configuration. This field is of width 2 3 or 4 bits for 32-bit 64-bit or.." newline bitfld.long 0x8 0. "SR,Start or Stop Receive When this bit is set the DMA tries to acquire the descriptor from the Receive list and processes the incoming packets. The DMA tries to acquire descriptor from either of the following positions: - The current position in the.." "Stop Receive,Start Receive" group.long 0x10++0x13 line.long 0x0 "DMA_CH4_TXDESC_LIST_HADDRESS,The Channeli Tx Descriptor List HAddress register has the higher 8 or 16 bits of the start address of the Transmit descriptor list. You can write to this register only when the Tx DMA has stopped. that is. the ST bit is set.." hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED_31_Y,Reserved." newline hexmask.long.byte 0x0 0.--7. 1. "TDESHA,Start of Transmit List This field contains the most-significant 8 or 16 bits of the 40- or 48-bit base address of the first descriptor in the Transmit descriptor list." line.long 0x4 "DMA_CH4_TXDESC_LIST_ADDRESS,The Channeli Tx Descriptor List Address register points the DMA to the start of Transmit descriptor list. The descriptor lists reside in the physical memory space of the application and must be Word. Dword. or Lword-aligned.." hexmask.long 0x4 4.--31. 1. "TDESLA,Start of Transmit List This field contains the base address of the first descriptor in the Transmit descriptor list. The DMA ignores the LSB bits (1:0 2:0 or 3:0) for 32-bit 64-bit or 128-bit bus width and internally takes these bits as.." newline hexmask.long.byte 0x4 0.--3. 1. "RESERVED_LSB," line.long 0x8 "DMA_CH4_RXDESC_LIST_HADDRESS,The Channeli Rx Descriptor List HAddress register has the higher 8 or 16 bits of the start address of the Receive descriptor list. Writing to this register is permitted only when reception is stopped. When stopped. this.." hexmask.long.tbyte 0x8 8.--31. 1. "RESERVED_31_Y,Reserved." newline hexmask.long.byte 0x8 0.--7. 1. "RDESHA,Start of Receive List This field contains the most-significant 8 or 16 bits of the 40-bit or 48-bit base address of the first descriptor in the Rx Descriptor list." line.long 0xC "DMA_CH4_RXDESC_LIST_ADDRESS,The Channeli Rx Descriptor List Address register points the DMA to the start of Receive descriptor list. This register points to the start of the Receive Descriptor List. The descriptor lists reside in the physical memory.." hexmask.long 0xC 4.--31. 1. "RDESLA,Start of Receive List This field contains the base address of the first descriptor in the Rx Descriptor list. The DMA ignores the LSB bits (1:0 2:0 or 3:0) for 32-bit 64-bit or 128-bit bus width and internally takes these bits as all-zero." newline hexmask.long.byte 0xC 0.--3. 1. "RESERVED_LSB," line.long 0x10 "DMA_CH4_TXDESC_TAIL_POINTER,The Channeli Tx Descriptor Tail Pointer register points to an offset from the base and indicates the location of the last valid descriptor." hexmask.long 0x10 4.--31. 1. "TDTP,Transmit Descriptor Tail Pointer This field contains the tail pointer for the Tx descriptor ring. The software writes the tail pointer to add more descriptors to the Tx channel. The hardware tries to transmit all packets referenced by the.." newline hexmask.long.byte 0x10 0.--3. 1. "RESERVED_LSB," group.long 0x28++0x17 line.long 0x0 "DMA_CH4_RXDESC_TAIL_POINTER,The Channeli Rx Descriptor Tail Pointer Points to an offset from the base and indicates the location of the last valid descriptor." hexmask.long 0x0 4.--31. 1. "RDTP,Receive Descriptor Tail Pointer This field contains the tail pointer for the Rx descriptor ring. The software writes the tail pointer to add more descriptors to the Rx channel. The hardware tries to write all received packets to the descriptors.." newline hexmask.long.byte 0x0 0.--3. 1. "RESERVED_LSB," line.long 0x4 "DMA_CH4_TXDESC_RING_LENGTH,The Tx Descriptor Ring Length register contains the length of the Transmit descriptor ring." hexmask.long.tbyte 0x4 10.--31. 1. "RESERVED_31_10,Reserved." newline hexmask.long.word 0x4 0.--9. 1. "TDRL,Transmit Descriptor Ring Length This field sets the maximum number of Tx descriptors in the circular descriptor ring. The maximum number of descriptors is limited to 1K descriptors. Synopsys recommends a minimum ring descriptor length of 4. For.." line.long 0x8 "DMA_CH4_RXDESC_RING_LENGTH,The Channeli Rx Descriptor Ring Length register contains the length of the Receive descriptor circular ring." hexmask.long.tbyte 0x8 10.--31. 1. "RESERVED_31_10,Reserved." newline hexmask.long.word 0x8 0.--9. 1. "RDRL,Receive Descriptor Ring Length This register sets the maximum number of Rx descriptors in the circular descriptor ring. The maximum number of descriptors is limited to 1K descriptors. For example You can program any value up to 0x3FF in this field." line.long 0xC "DMA_CH4_INTERRUPT_ENABLE,The Channeli Interrupt Enable register enables the interrupts reported by the Status register." hexmask.long.word 0xC 16.--31. 1. "RESERVED_31_16,Reserved." newline bitfld.long 0xC 15. "NIE,Normal Interrupt Summary Enable When this bit is set the normal interrupt summary is enabled. This bit enables the following interrupts in the DMA_CH0_Status register: - Bit 0: Transmit Interrupt - Bit 2: Transmit Buffer Unavailable - Bit 6: Receive.." "Normal Interrupt Summary is disabled,Normal Interrupt Summary is enabled" newline bitfld.long 0xC 14. "AIE,Abnormal Interrupt Summary Enable When this bit is set the abnormal interrupt summary is enabled. This bit enables the following interrupts in the DMA_CH0_Status register: - Bit 1: Transmit Process Stopped - Bit 7: Rx Buffer Unavailable - Bit 8:.." "Abnormal Interrupt Summary is disabled,Abnormal Interrupt Summary is enabled" newline bitfld.long 0xC 13. "CDEE,Context Descriptor Error Enable When this bit is set along with the AIE bit the Descriptor error interrupt is enabled. When this bit is reset the Descriptor error interrupt is disabled. 0x0: Context Descriptor Error is disabled 0x1: Context.." "Context Descriptor Error is disabled,Context Descriptor Error is enabled" newline bitfld.long 0xC 12. "FBEE,Fatal Bus Error Enable When this bit is set along with the AIE bit the Fatal Bus error interrupt is enabled. When this bit is reset the Fatal Bus Error error interrupt is disabled. 0x0: Fatal Bus Error is disabled 0x1: Fatal Bus Error is enabled" "Fatal Bus Error is disabled,Fatal Bus Error is enabled" newline bitfld.long 0xC 11. "ERIE,Early Receive Interrupt Enable When this bit is set along with the NIE bit the Early Receive interrupt is enabled. When this bit is reset the Early Receive interrupt is disabled. 0x0: Early Receive Interrupt is disabled 0x1: Early Receive.." "Early Receive Interrupt is disabled,Early Receive Interrupt is enabled" newline bitfld.long 0xC 10. "ETIE,Early Transmit Interrupt Enable When this bit is set along with the AIE bit the Early Transmit interrupt is enabled. When this bit is reset the Early Transmit interrupt is disabled. 0x0: Early Transmit Interrupt is disabled 0x1: Early Transmit.." "Early Transmit Interrupt is disabled,Early Transmit Interrupt is enabled" newline bitfld.long 0xC 9. "RWTE,Receive Watchdog Timeout Enable When this bit is set along with the AIE bit the Receive Watchdog Timeout interrupt is enabled. When this bit is reset the Receive Watchdog Timeout interrupt is disabled. 0x0: Receive Watchdog Timeout is disabled.." "Receive Watchdog Timeout is disabled,Receive Watchdog Timeout is enabled" newline bitfld.long 0xC 8. "RSE,Receive Stopped Enable When this bit is set along with the AIE bit the Receive Stopped Interrupt is enabled. When this bit is reset the Receive Stopped interrupt is disabled. 0x0: Receive Stopped is disabled 0x1: Receive Stopped is enabled" "Receive Stopped is disabled,Receive Stopped is enabled" newline bitfld.long 0xC 7. "RBUE,Receive Buffer Unavailable Enable When this bit is set along with the AIE bit the Receive Buffer Unavailable interrupt is enabled. When this bit is reset the Receive Buffer Unavailable interrupt is disabled. 0x0: Receive Buffer Unavailable is.." "Receive Buffer Unavailable is disabled,Receive Buffer Unavailable is enabled" newline bitfld.long 0xC 6. "RIE,Receive Interrupt Enable When this bit is set along with the NIE bit the Receive Interrupt is enabled. When this bit is reset the Receive Interrupt is disabled. 0x0: Receive Interrupt is disabled 0x1: Receive Interrupt is enabled" "Receive Interrupt is disabled,Receive Interrupt is enabled" newline rbitfld.long 0xC 3.--5. "RESERVED_5_3,Reserved." "0,1,2,3,4,5,6,7" newline bitfld.long 0xC 2. "TBUE,Transmit Buffer Unavailable Enable When this bit is set along with the NIE bit the Transmit Buffer Unavailable interrupt is enabled. When this bit is reset the Transmit Buffer Unavailable interrupt is disabled. 0x0: Transmit Buffer Unavailable is.." "Transmit Buffer Unavailable is disabled,Transmit Buffer Unavailable is enabled" newline bitfld.long 0xC 1. "TXSE,Transmit Stopped Enable When this bit is set along with the AIE bit the Transmission Stopped interrupt is enabled. When this bit is reset the Transmission Stopped interrupt is disabled. 0x0: Transmit Stopped is disabled 0x1: Transmit Stopped is.." "Transmit Stopped is disabled,Transmit Stopped is enabled" newline bitfld.long 0xC 0. "TIE,Transmit Interrupt Enable When this bit is set along with the NIE bit the Transmit Interrupt is enabled. When this bit is reset the Transmit Interrupt is disabled. 0x0: Transmit Interrupt is disabled 0x1: Transmit Interrupt is enabled" "Transmit Interrupt is disabled,Transmit Interrupt is enabled" line.long 0x10 "DMA_CH4_RX_INTERRUPT_WATCHDOG_TIMER,The Receive Interrupt Watchdog Timer register indicates the watchdog timeout for Receive Interrupt (RI) from the DMA. When this register is written with a non-zero value. it enables the watchdog timer for the RI bit of.." hexmask.long.word 0x10 18.--31. 1. "RESERVED_31_18,Reserved." newline bitfld.long 0x10 16.--17. "RWTU,Receive Interrupt Watchdog Timer Count Units This fields indicates the number of system clock cycles corresponding to one unit in RWT field. - 2'b00: 256 - 2'b01: 512 - 2'b10: 1024 - 2'b11: 2048 For example when RWT=2 and RWTU=1 the watchdog timer.." "0,1,2,3" newline hexmask.long.byte 0x10 8.--15. 1. "RESERVED_15_8,Reserved." newline hexmask.long.byte 0x10 0.--7. 1. "RWT,Receive Interrupt Watchdog Timer Count This field indicates the number of system clock cycles multiplied by factor indicated in RWTU field for which the watchdog timer is set. The watchdog timer is triggered with the programmed value after the Rx.." line.long 0x14 "DMA_CH4_SLOT_FUNCTION_CONTROL_STATUS,The Slot Function Control and Status register contains the control bits for slot function and the status for Transmit path." hexmask.long.word 0x14 20.--31. 1. "RESERVED_31_20,Reserved." newline hexmask.long.byte 0x14 16.--19. 1. "RSN,Reference Slot Number This field gives the current value of the reference slot number in the DMA. It is used for slot comparison." newline hexmask.long.word 0x14 4.--15. 1. "SIV,Slot Interval Value This field controls the period of the slot interval in which the TxDMA fetches the scheduled packets. A value of 0 specifies the slot interval of 1 us while the maximum value 4095 specifies the slot interval of 4096us. The.." newline rbitfld.long 0x14 2.--3. "RESERVED_3_2,Reserved." "0,1,2,3" newline bitfld.long 0x14 1. "ASC,Advance Slot Check When set this bit enables the DMA to fetch the data from the buffer when the slot number (SLOTNUM) programmed in the Tx descriptor is - equal to the reference slot number given in the RSN field or - ahead of the reference slot.." "Advance Slot Check is disabled,Advance Slot Check is enabled" newline bitfld.long 0x14 0. "ESC,Enable Slot Comparison When set this bit enables the checking of the slot numbers programmed in the Tx descriptor with the current reference given in the RSN field. The DMA fetches the data from the corresponding buffer only when the slot number is.." "Slot Comparison is disabled,Slot Comparison is enabled" rgroup.long 0x44++0x3 line.long 0x0 "DMA_CH4_CURRENT_APP_TXDESC,The Channeli Current Application Transmit Descriptor register points to the current Transmit descriptor read by the DMA." hexmask.long 0x0 0.--31. 1. "CURTDESAPTR,Application Transmit Descriptor Address Pointer The DMA updates this pointer during Tx operation. This pointer is cleared on reset." rgroup.long 0x4C++0x13 line.long 0x0 "DMA_CH4_CURRENT_APP_RXDESC,The Channeli Current Application Receive Descriptor register points to the current Receive descriptor read by the DMA." hexmask.long 0x0 0.--31. 1. "CURRDESAPTR,Application Receive Descriptor Address Pointer The DMA updates this pointer during Rx operation. This pointer is cleared on reset." line.long 0x4 "DMA_CH4_CURRENT_APP_TXBUFFER_H,The Channeli Current Application Transmit Buffer Address High register has the higher 8 or 16 bits of the current address of the Transmit buffer address read by the DMA." hexmask.long.tbyte 0x4 8.--31. 1. "RESERVED_31_Y,Reserved." newline hexmask.long.byte 0x4 0.--7. 1. "CURTBUFAPTRH,Application Transmit Buffer Address Pointer The DMA updates this pointer during Tx operation. This pointer is cleared on reset." line.long 0x8 "DMA_CH4_CURRENT_APP_TXBUFFER,The Channeli Current Application Transmit Buffer Address register points to the current Tx buffer address read by the DMA." hexmask.long 0x8 0.--31. 1. "CURTBUFAPTR,Application Transmit Buffer Address Pointer The DMA updates this pointer during Tx operation. This pointer is cleared on reset." line.long 0xC "DMA_CH4_CURRENT_APP_RXBUFFER_H,The Channeli Current Application Receive Buffer Address High register has the higher 8 or 16 bits of the current address of the Receive buffer address read by the DMA." hexmask.long.tbyte 0xC 8.--31. 1. "RESERVED_31_Y,Reserved." newline hexmask.long.byte 0xC 0.--7. 1. "CURRBUFAPTRH,Application Receive Buffer Address Pointer The DMA updates this pointer during Rx operation. This pointer is cleared on reset." line.long 0x10 "DMA_CH4_CURRENT_APP_RXBUFFER,The Channel 0 Current Application Receive Buffer Address register points to the current Rx buffer address read by the DMA." hexmask.long 0x10 0.--31. 1. "CURRBUFAPTR,Application Receive Buffer Address Pointer The DMA updates this pointer during Rx operation. This pointer is cleared on reset." group.long 0x60++0x3 line.long 0x0 "DMA_CH4_STATUS,The software driver (application) reads the Status register during interrupt service routine or polling to determine the status of the DMA. Note: The number of DMA_CH[n]_Status register in the configuration is the higher of number of Rx.." hexmask.long.word 0x0 22.--31. 1. "RESERVED_31_22,Reserved." newline rbitfld.long 0x0 19.--21. "REB,Rx DMA Error Bits This field indicates the type of error that caused a Bus Error. For example error response on the AHB or AXI interface. - Bit 21 -- 1'b1: Error during data transfer by Rx DMA -- 1'b0: No Error during data transfer by Rx DMA - Bit.." "Error during write transfer,Error during read transfer,?,?,?,?,?,?" newline rbitfld.long 0x0 16.--18. "TEB,Tx DMA Error Bits This field indicates the type of error that caused a Bus Error. For example error response on the AHB or AXI interface. - Bit 18 -- 1'b1: Error during data transfer by Tx DMA -- 1'b0: No Error during data transfer by Tx DMA - Bit.." "Error during write transfer,Error during read transfer,?,?,?,?,?,?" newline bitfld.long 0x0 15. "NIS,Normal Interrupt Summary Normal Interrupt Summary bit value is the logical OR of the following bits when the corresponding interrupt bits are enabled in the DMA_CH0_Interrupt_Enable register: - Bit 0: Transmit Interrupt - Bit 2: Transmit Buffer.." "Normal Interrupt Summary status not detected,Normal Interrupt Summary status detected" newline bitfld.long 0x0 14. "AIS,Abnormal Interrupt Summary Abnormal Interrupt Summary bit value is the logical OR of the following when the corresponding interrupt bits are enabled in the DMA_CH0_Interrupt_Enable register: - Bit 1: Transmit Process Stopped - Bit 7: Receive Buffer.." "Abnormal Interrupt Summary status not detected,Abnormal Interrupt Summary status detected" newline bitfld.long 0x0 13. "CDE,Context Descriptor Error This bit indicates that the DMA Tx/Rx engine received a descriptor error which indicates invalid context in the middle of packet flow ( intermediate descriptor) or all one's descriptor in Tx case and on Rx side it indicates.." "Context Descriptor Error status not detected,Context Descriptor Error status detected" newline bitfld.long 0x0 12. "FBE,Fatal Bus Error This bit indicates that a bus error occurred (as described in the EB field). When this bit is set the corresponding DMA channel engine disables all bus accesses. Access restriction applies. Self-set to 1 on internal event. Setting 1.." "Fatal Bus Error status not detected,Fatal Bus Error status detected" newline bitfld.long 0x0 11. "ERI,Early Receive Interrupt This bit when set indicates that the RxDMA has completed the transfer of packet data to the memory. In configs supporting ERIC When ERIC=0 this bit is set only after the Rx DMA has filled up a complete receive buffer with.." "Early Receive Interrupt status not detected,Early Receive Interrupt status detected" newline bitfld.long 0x0 10. "ETI,Early Transmit Interrupt This bit when set indicates that the TxDMA has completed the transfer of packet data to the MTL TXFIFO memory. In configs supporting ERIC: When ETIC=0 this bit is set only after the Tx DMA has transferred a complete packet.." "Early Transmit Interrupt status not detected,Early Transmit Interrupt status detected" newline bitfld.long 0x0 9. "RWT,Receive Watchdog Timeout This bit is asserted when a packet with length greater than 2 048 bytes (10 240 bytes when Jumbo Packet mode is enabled) is received. 0x1: Receive Watchdog Timeout status detected 0x0: Receive Watchdog Timeout status not.." "Receive Watchdog Timeout status not detected,Receive Watchdog Timeout status detected" newline bitfld.long 0x0 8. "RPS,Receive Process Stopped This bit is asserted when the Rx process enters the Stopped state. Access restriction applies. Self-set to 1 on internal event. Setting 1 clears. Setting 0 has no effect. 0x1: Receive Process Stopped status detected 0x0:.." "Receive Process Stopped status not detected,Receive Process Stopped status detected" newline bitfld.long 0x0 7. "RBU,Receive Buffer Unavailable This bit indicates that the application owns the next descriptor in the Receive list and the DMA cannot acquire it. The Rx process is suspended. To resume processing Rx descriptors the application should change the.." "Receive Buffer Unavailable status not detected,Receive Buffer Unavailable status detected" newline bitfld.long 0x0 6. "RI,Receive Interrupt This bit indicates that the packet reception is complete. When packet reception is complete Bit 31 of RDES3 is reset in the last descriptor and the specific packet status information is updated in the descriptor. The reception.." "Receive Interrupt status not detected,Receive Interrupt status detected" newline rbitfld.long 0x0 3.--5. "RESERVED_5_3,Reserved." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 2. "TBU,Transmit Buffer Unavailable This bit indicates that the application owns the next descriptor in the Transmit list and the DMA cannot acquire it. Transmission is suspended. The TPS0 field of the DMA_Debug_Status0 register explains the Transmit.." "Transmit Buffer Unavailable status not detected,Transmit Buffer Unavailable status detected" newline bitfld.long 0x0 1. "TPS,Transmit Process Stopped This bit is set when the transmission is stopped. Access restriction applies. Self-set to 1 on internal event. Setting 1 clears. Setting 0 has no effect. 0x1: Transmit Process Stopped status detected 0x0: Transmit Process.." "Transmit Process Stopped status not detected,Transmit Process Stopped status detected" newline bitfld.long 0x0 0. "TI,Transmit Interrupt This bit indicates that the packet transmission is complete. When transmission is complete Bit 31 of TDES3 is reset in the last descriptor and the specific packet status information is updated in the descriptor. Access restriction.." "Transmit Interrupt status not detected,Transmit Interrupt status detected" rgroup.long 0x64++0xB line.long 0x0 "DMA_CH4_MISS_FRAME_CNT,This register has the number of packet counter that got dropped by the DMA either due to Bus Error or due to programming RPF field in DMA_CH{i}_Rx_Control register." hexmask.long.word 0x0 16.--31. 1. "RESERVED_31_16,Reserved." newline bitfld.long 0x0 15. "MFCO,Overflow status of the MFC Counter When this bit is set then the MFC counter does not get incremented further. The bit gets cleared when this register is read. Access restriction applies. Clears on read. Self-set to 1 on internal event. 0x1: Miss.." "Miss Frame Counter overflow not occurred,Miss Frame Counter overflow occurred" newline hexmask.long.byte 0x0 11.--14. 1. "RESERVED_14_11,Reserved." newline hexmask.long.word 0x0 0.--10. 1. "MFC,Dropped Packet Counters This counter indicates the number of packet counters that are dropped by the DMA either because of bus error or because of programing RPF field in DMA_CH{i}_Rx_Control register. The counter gets cleared when this register is.." line.long 0x4 "DMA_CH4_RXP_ACCEPT_CNT,The DMA_CH(#i)_RXP_Accept_Cnt registers provides the count of the number of frames accepted by Rx Parser." bitfld.long 0x4 31. "RXPACOF,Rx Parser Accept Counter Overflow Bit When set this bit indicates that the RXPAC Counter field crossed the maximum limit. Access restriction applies. Clears on read. Self-set to 1 on internal event. 0x1: Rx Parser Accept Counter overflow.." "Rx Parser Accept Counter overflow not occurred,Rx Parser Accept Counter overflow occurred" newline hexmask.long 0x4 0.--30. 1. "RXPAC,Rx Parser Accept Counter This 31-bit counter is implemented whenever a Rx Parser Accept a packet due to AF =1. The counter is cleared when the register is read." line.long 0x8 "DMA_CH4_RX_ERI_CNT,The DMA_CH(#i)_RX_ERI_Cnt registers provides the count of the number of times ERI was asserted." hexmask.long.tbyte 0x8 12.--31. 1. "RESERVED_31_12," newline hexmask.long.word 0x8 0.--11. 1. "ECNT,ERI Counter When ERIC bit of DMA_CH(#i)_RX_Control register is set this counter increments for burst transfer completed by the Rx DMA from the start of packet transfer. This counter will get reset at the start of new packet." tree.end tree.end repeat.end elif (CORENAME()=="CORTEXA55") repeat 2. (increment 1. 1.) (list ad:0x30170000 ad:0x306A0000) tree "ETHERNET$1" base $2 tree "EQOS_MAC" group.long 0x0++0x1F line.long 0x0 "MAC_CONFIGURATION,The MAC Configuration Register establishes the operating mode of the MAC." rbitfld.long 0x0 31. "RESERVED_ARPEN,Reserved." "0,1" newline bitfld.long 0x0 28.--30. "SARC,Source Address Insertion or Replacement Control This field controls the source address insertion or replacement for all transmitted packets. Bit 30 specifies which MAC Address register (0 or 1) is used for source address insertion or replacement.." "mti_sa_ctrl_i and ati_sa_ctrl_i input signals..,?,Contents of MAC Addr-0 inserted in SA field,Contents of MAC Addr-0 replaces SA field,?,?,Contents of MAC Addr-1 inserted in SA field,Contents of MAC Addr-1 replaces SA field" newline bitfld.long 0x0 27. "IPC,Checksum Offload When set this bit enables the IPv4 header checksum checking and IPv4 or IPv6 TCP UDP or ICMP payload checksum checking. When this bit is reset the COE function in the receiver is disabled. The Layer 3 and Layer 4 Packet Filter.." "IP header/payload checksum checking is disabled,IP header/payload checksum checking is enabled" newline bitfld.long 0x0 24.--26. "IPG,Inter-Packet Gap These bits control the minimum IPG between packets during transmission. This range of minimum IPG is valid in full-duplex mode. In the half-duplex mode the minimum IPG can be configured only for 64-bit times (IPG = 100). Lower.." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 23. "GPSLCE,Giant Packet Size Limit Control Enable When this bit is set the MAC considers the value in GPSL field in MAC_Ext_Configuration register to declare a received packet as Giant packet. This field must be programmed to more than 1 518 bytes." "Giant Packet Size Limit Control is disabled,Giant Packet Size Limit Control is enabled" newline bitfld.long 0x0 22. "S2KP,IEEE 802.3as Support for 2K Packets When this bit is set the MAC considers all packets with up to 2 000 bytes length as normal packets. When the JE bit is not set the MAC considers all received packets of size more than 2K bytes as Giant packets." "Support upto 2K packet is disabled,Support upto 2K packet is Enabled" newline bitfld.long 0x0 21. "CST,CRC stripping for Type packets When this bit is set the last four bytes (FCS) of all packets of Ether type (type field greater than 1 536) are stripped and dropped before forwarding the packet to the application. Note: For information about how the.." "CRC stripping for Type packets is disabled,CRC stripping for Type packets is enabled" newline bitfld.long 0x0 20. "ACS,Automatic Pad or CRC Stripping When this bit is set the MAC strips the Pad or FCS field on the incoming packets only if the value of the length field is less than 1 536 bytes. All received packets with length field greater than or equal to 1 536.." "Automatic Pad or CRC Stripping is disabled,Automatic Pad or CRC Stripping is enabled" newline bitfld.long 0x0 19. "WD,Watchdog Disable When this bit is set the MAC disables the watchdog timer on the receiver. The MAC can receive packets of up to 16 383 bytes. When this bit is reset the MAC does not allow more than 2 048 bytes (10 240 if JE is set high) of the.." "Watchdog is enabled,Watchdog is disabled" newline bitfld.long 0x0 18. "BE,Packet Burst Enable When this bit is set the MAC allows packet bursting during transmission in the GMII half-duplex mode. 0x0: Packet Burst is disabled 0x1: Packet Burst is enabled" "Packet Burst is disabled,Packet Burst is enabled" newline bitfld.long 0x0 17. "JD,Jabber Disable When this bit is set the MAC disables the jabber timer on the transmitter. The MAC can transfer packets of up to 16 383 bytes. When this bit is reset if the application sends more than 2 048 bytes of data (10 240 if JE is set high).." "Jabber is enabled,Jabber is disabled" newline bitfld.long 0x0 16. "JE,Jumbo Packet Enable When this bit is set the MAC allows jumbo packets of 9 018 bytes (9 022 bytes for VLAN tagged packets) without reporting a giant packet error in the Rx packet status. 0x0: Jumbo packet is disabled 0x1: Jumbo packet is enabled" "Jumbo packet is disabled,Jumbo packet is enabled" newline bitfld.long 0x0 15. "PS,Port Select This bit selects the Ethernet line speed. This bit along with Bit 14 selects the exact line speed. In the 10/100 Mbps-only (always 1) or 1000 Mbps-only (always 0) configurations this bit is read-only (RO) with appropriate value. In.." "For 1000 or 2500 Mbps operations,For 10 or 100 Mbps operations" newline bitfld.long 0x0 14. "FES,Speed This bit selects the speed mode. The mac_speed_o[0] signal reflects the value of this bit. 0x1: 100 Mbps when PS bit is 1 and 2.5 Gbps when PS bit is 0 0x0: 10 Mbps when PS bit is 1 and 1 Gbps when PS bit is 0" "0,1" newline bitfld.long 0x0 13. "DM,Duplex Mode When this bit is set the MAC operates in the full-duplex mode in which it can transmit and receive simultaneously. This bit is RO with default value of 1'b1 in the full-duplex-only configurations. 0x1: Full-duplex mode 0x0: Half-duplex mode" "Half-duplex mode,Full-duplex mode" newline bitfld.long 0x0 12. "LM,Loopback Mode When this bit is set the MAC operates in the loopback mode at GMII or MII. The (G)MII Rx clock input (clk_rx_i) is required for the loopback to work properly. This is because the Tx clock is not internally looped back. 0x0: Loopback is.." "Loopback is disabled,Loopback is enabled" newline bitfld.long 0x0 11. "ECRSFD,Enable Carrier Sense Before Transmission in Full-Duplex Mode When this bit is set the MAC transmitter checks the CRS signal before packet transmission in the full-duplex mode. The MAC starts the transmission only when the CRS signal is low. When.." "ECRSFD is disabled,ECRSFD is enabled" newline bitfld.long 0x0 10. "DO,Disable Receive Own When this bit is set the MAC disables the reception of packets when the gmii_txen_o is asserted in the half-duplex mode. When this bit is reset the MAC receives all packets given by the PHY. This bit is not applicable in the.." "Enable Receive Own,Disable Receive Own" newline bitfld.long 0x0 9. "DCRS,Disable Carrier Sense During Transmission When this bit is set the MAC transmitter ignores the (G)MII CRS signal during packet transmission in the half-duplex mode. As a result no errors are generated because of Loss of Carrier or No Carrier.." "Enable Carrier Sense During Transmission,Disable Carrier Sense During Transmission" newline bitfld.long 0x0 8. "DR,Disable Retry When this bit is set the MAC attempts only one transmission. When a collision occurs on the GMII or MII interface the MAC ignores the current packet transmission and reports a Packet Abort with excessive collision error in the Tx.." "Enable Retry,Disable Retry" newline rbitfld.long 0x0 7. "RESERVED_7,Reserved." "0,1" newline bitfld.long 0x0 5.--6. "BL,Back-Off Limit The back-off limit determines the random integer number (r) of slot time delays (4 096 bit times for 1000/2500 Mbps; 512 bit times for 10/100 Mbps) for which the MAC waits before rescheduling a transmission attempt during retries after.." "k = min,k = min,k = min,k = min" newline bitfld.long 0x0 4. "DC,Deferral Check When this bit is set the deferral check function is enabled in the MAC. The MAC issues a Packet Abort status along with the excessive deferral error bit set in the Tx packet status when the Tx state machine is deferred for more than.." "Deferral check function is disabled,Deferral check function is enabled" newline bitfld.long 0x0 2.--3. "PRELEN,Preamble Length for Transmit packets These bits control the number of preamble bytes that are added to the beginning of every Tx packet. The preamble reduction occurs only when the MAC is operating in the full-duplex mode. 0x2: 3 bytes of preamble.." "?,?,?,Reserved" newline bitfld.long 0x0 1. "TE,Transmitter Enable When this bit is set the Tx state machine of the MAC is enabled for transmission on the GMII or MII interface. When this bit is reset the MAC Tx state machine is disabled after it completes the transmission of the current packet." "Transmitter is disabled,Transmitter is enabled" newline bitfld.long 0x0 0. "RE,Receiver Enable When this bit is set the Rx state machine of the MAC is enabled for receiving packets from the GMII or MII interface. When this bit is reset the MAC Rx state machine is disabled after it completes the reception of the current packet." "Receiver is disabled,Receiver is enabled" line.long 0x4 "MAC_EXT_CONFIGURATION,The MAC Extended Configuration Register establishes the operating mode of the MAC." rbitfld.long 0x4 31. "RESERVED_FHE,Reserved." "0,1" newline rbitfld.long 0x4 30. "RESERVED_30,Reserved." "0,1" newline hexmask.long.byte 0x4 25.--29. 1. "EIPG,Extended Inter-Packet Gap The value in this field is applicable when the EIPGEN bit is set. This field (as Most Significant bits) along with IPG field in MAC_Configuration register gives the minimum IPG greater than 96 bit times in steps of 8 bit.." newline bitfld.long 0x4 24. "EIPGEN,Extended Inter-Packet Gap Enable When this bit is set the MAC interprets EIPG field and IPG field in MAC_Configuration register together as minimum IPG greater than 96 bit times in steps of 8 bit times. When this bit is reset the MAC ignores.." "Extended Inter-Packet Gap is disabled,Extended Inter-Packet Gap is enabled" newline rbitfld.long 0x4 23. "RESERVED_23,Reserved." "0,1" newline rbitfld.long 0x4 20.--22. "RESERVED_HDSMS,Reserved." "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 19. "PDC,Packet Duplication Control When this bit is set the received packet with Multicast/Broadcast Destination address is routed to multiple Receive DMA Channels. The Receive DMA Channels is identified by the DCS field of MAC_Address(#i)_High register.." "Packet Duplication Control is disabled,Packet Duplication Control is enabled" newline bitfld.long 0x4 18. "USP,Unicast Slow Protocol Packet Detect When this bit is set the MAC detects the Slow Protocol packets with unicast address of the station specified in the MAC_Address0_High and MAC_Address0_Low registers. The MAC also detects the Slow Protocol packets.." "Unicast Slow Protocol Packet Detection is disabled,Unicast Slow Protocol Packet Detection is enabled" newline bitfld.long 0x4 17. "SPEN,Slow Protocol Detection Enable When this bit is set MAC processes the Slow Protocol packets (Ether Type 0x8809) and provides the Rx status. The MAC discards the Slow Protocol packets with invalid sub-types. When this bit is reset the MAC forwards.." "Slow Protocol Detection is disabled,Slow Protocol Detection is enabled" newline bitfld.long 0x4 16. "DCRCC,Disable CRC Checking for Received Packets When this bit is set the MAC receiver does not check the CRC field in the received packets. When this bit is reset the MAC receiver always checks the CRC field in the received packets. 0x1: CRC Checking.." "CRC Checking is enabled,CRC Checking is disabled" newline rbitfld.long 0x4 14.--15. "RESERVED_15_14,Reserved." "0,1,2,3" newline hexmask.long.word 0x4 0.--13. 1. "GPSL,Giant Packet Size Limit If the received packet size is greater than the value programmed in this field in units of bytes the MAC declares the received packet as Giant packet. The value programmed in this field must be greater than or equal to 1 518.." line.long 0x8 "MAC_PACKET_FILTER,The MAC Packet Filter register contains the filter controls for receiving packets. Some of the controls from this register go to the address check block of the MAC which performs the first level of address filtering. The second level of.." bitfld.long 0x8 31. "RA,Receive All When this bit is set the MAC Receiver module passes all received packets to the application irrespective of whether they pass the address filter or not. The result of the SA or DA filtering is updated (pass or fail) in the corresponding.." "Receive All is disabled,Receive All is enabled" newline hexmask.long.word 0x8 22.--30. 1. "RESERVED_30_22,Reserved." newline bitfld.long 0x8 21. "DNTU,Drop Non-TCP/UDP over IP Packets When this bit is set the MAC drops the non-TCP or UDP over IP packets. The MAC forward only those packets that are processed by the Layer 4 filter. When this bit is reset the MAC forwards all non-TCP or UDP over IP.." "Forward Non-TCP/UDP over IP Packets,Drop Non-TCP/UDP over IP Packets" newline bitfld.long 0x8 20. "IPFE,Layer 3 and Layer 4 Filter Enable When this bit is set the MAC drops packets that do not match the enabled Layer 3 and Layer 4 filters. If Layer 3 or Layer 4 filters are not enabled for matching this bit does not have any effect. When this bit is.." "Layer 3 and Layer 4 Filters are disabled,Layer 3 and Layer 4 Filters are enabled" newline rbitfld.long 0x8 17.--19. "RESERVED_19_17,Reserved." "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 16. "VTFE,VLAN Tag Filter Enable When this bit is set the MAC drops the VLAN tagged packets that do not match the VLAN Tag. When this bit is reset the MAC forwards all packets irrespective of the match status of the VLAN Tag. 0x0: VLAN Tag Filter is.." "VLAN Tag Filter is disabled,VLAN Tag Filter is enabled" newline hexmask.long.byte 0x8 11.--15. 1. "RESERVED_15_11,Reserved." newline bitfld.long 0x8 10. "HPF,Hash or Perfect Filter When this bit is set the address filter passes a packet if it matches either the perfect filtering or hash filtering as set by the HMC or HUC bit. When this bit is reset and the HUC or HMC bit is set the packet is passed only.." "Hash or Perfect Filter is disabled,Hash or Perfect Filter is enabled" newline bitfld.long 0x8 9. "SAF,Source Address Filter Enable When this bit is set the MAC compares the SA field of the received packets with the values programmed in the enabled SA registers. If the comparison fails the MAC drops the packet. When this bit is reset the MAC.." "SA Filtering is disabled,SA Filtering is enabled" newline bitfld.long 0x8 8. "SAIF,SA Inverse Filtering When this bit is set the Address Check block operates in the inverse filtering mode for SA address comparison. If the SA of a packet matches the values programmed in the SA registers it is marked as failing the SA Address.." "SA Inverse Filtering is disabled,SA Inverse Filtering is enabled" newline bitfld.long 0x8 6.--7. "PCF,Pass Control Packets These bits control the forwarding of all control packets (including unicast and multicast Pause packets). 0x0: MAC filters all control packets from reaching the application 0x2: MAC forwards all control packets to the application.." "MAC filters all control packets from reaching..,MAC forwards all control packets except Pause..,MAC forwards all control packets to the..,MAC forwards the control packets that pass the.." newline bitfld.long 0x8 5. "DBF,Disable Broadcast Packets When this bit is set the AFM module blocks all incoming broadcast packets. In addition it overrides all other filter settings. When this bit is reset the AFM module passes all received broadcast packets. 0x1: Disable.." "Enable Broadcast Packets,Disable Broadcast Packets" newline bitfld.long 0x8 4. "PM,Pass All Multicast When this bit is set it indicates that all received packets with a multicast destination address (first bit in the destination address field is '1') are passed. When this bit is reset filtering of multicast packet depends on HMC.." "Pass All Multicast is disabled,Pass All Multicast is enabled" newline bitfld.long 0x8 3. "DAIF,DA Inverse Filtering When this bit is set the Address Check block operates in inverse filtering mode for the DA address comparison for both unicast and multicast packets. When this bit is reset normal filtering of packets is performed. 0x0: DA.." "DA Inverse Filtering is disabled,DA Inverse Filtering is enabled" newline bitfld.long 0x8 2. "HMC,Hash Multicast When this bit is set the MAC performs the destination address filtering of received multicast packets according to the hash table. When this bit is reset the MAC performs the perfect destination address filtering for multicast.." "Hash Multicast is disabled,Hash Multicast is enabled" newline bitfld.long 0x8 1. "HUC,Hash Unicast When this bit is set the MAC performs the destination address filtering of unicast packets according to the hash table. When this bit is reset the MAC performs a perfect destination address filtering for unicast packets that is it.." "Hash Unicast is disabled,Hash Unicast is enabled" newline bitfld.long 0x8 0. "PR,Promiscuous Mode When this bit is set the Address Filtering module passes all incoming packets irrespective of the destination or source address. The SA or DA Filter Fails status bits of the Rx Status Word are always cleared when PR is set. 0x0:.." "Promiscuous Mode is disabled,Promiscuous Mode is enabled" line.long 0xC "MAC_WATCHDOG_TIMEOUT,The Watchdog Timeout register controls the watchdog timeout for received packets." hexmask.long.tbyte 0xC 9.--31. 1. "RESERVED_31_9,Reserved." newline bitfld.long 0xC 8. "PWE,Programmable Watchdog Enable When this bit is set and the WD bit of the MAC_Configuration register is reset the WTO field is used as watchdog timeout for a received packet. When this bit is cleared the watchdog timeout for a received packet is.." "Programmable Watchdog is disabled,Programmable Watchdog is enabled" newline hexmask.long.byte 0xC 4.--7. 1. "RESERVED_7_4,Reserved." newline hexmask.long.byte 0xC 0.--3. 1. "WTO,Watchdog Timeout When the PWE bit is set and the WD bit of the MAC_Configuration register is reset this field is used as watchdog timeout for a received packet. If the length of a received packet exceeds the value of this field such packet is.." line.long 0x10 "MAC_HASH_TABLE_REG0,The Hash Table Register 0 contains the first 32 bits of the hash table. when the width of the hash table is 128 or 256 bits. You can specify the width of the hash table by using the Hash Table Size option in coreConsultant. The Hash.." hexmask.long 0x10 0.--31. 1. "HT31T0,MAC Hash Table First 32 Bits This field contains the first 32 Bits [31:0] of the Hash table." line.long 0x14 "MAC_HASH_TABLE_REG1,The Hash Table Register 1 contains the second 32 bits of the hash table. You can specify the width of the hash table by using the Hash Table Size option in coreConsultant. The Hash table is used for group address filtering. For hash.." hexmask.long 0x14 0.--31. 1. "HT63T32,MAC Hash Table Second 32 Bits This field contains the second 32 Bits [63:32] of the Hash table." line.long 0x18 "MAC_HASH_TABLE_REG2,The Hash Table Register 2 contains the third 32 bits of the hash table. You can specify the width of the hash table by using the Hash Table Size option in coreConsultant. The Hash table is used for group address filtering. For hash.." hexmask.long 0x18 0.--31. 1. "HT95T64,MAC Hash Table Third 32 Bits This field contains the third 32 Bits [95:64] of the Hash table." line.long 0x1C "MAC_HASH_TABLE_REG3,The Hash Table Register 3 contains the fourth 32 bits of the hash table. You can specify the width of the hash table by using the Hash Table Size option in coreConsultant. The Hash table is used for group address filtering. For hash.." hexmask.long 0x1C 0.--31. 1. "HT127T96,MAC Hash Table Fourth 32 Bits This field contains the fourth 32 Bits [127:96] of the Hash table." group.long 0x50++0xB line.long 0x0 "MAC_VLAN_TAG_CTRL,This register is the redefined format of the MAC VLAN Tag Register. It is used for indirect addressing. It contains the address offset. command type and Busy Bit for CSR access of the Per VLAN Tag registers." bitfld.long 0x0 31. "EIVLRXS,Enable Inner VLAN Tag in Rx Status When this bit is set the MAC provides the inner VLAN Tag in the Rx status. When this bit is reset the MAC does not provide the inner VLAN Tag in Rx status. 0x0: Inner VLAN Tag in Rx status is disabled 0x1:.." "Inner VLAN Tag in Rx status is disabled,Inner VLAN Tag in Rx status is enabled" newline rbitfld.long 0x0 30. "RESERVED_30,Reserved." "0,1" newline bitfld.long 0x0 28.--29. "EIVLS,Enable Inner VLAN Tag Stripping on Receive This field indicates the stripping operation on inner VLAN Tag in received packet. 0x3: Always strip 0x0: Do not strip 0x2: Strip if VLAN filter fails 0x1: Strip if VLAN filter passes" "Do not strip,Strip if VLAN filter passes,Strip if VLAN filter fails,Always strip" newline bitfld.long 0x0 27. "ERIVLT,null 0x0: Inner VLAN tag is disabled 0x1: Inner VLAN tag is enabled" "Inner VLAN tag is disabled,Inner VLAN tag is enabled" newline bitfld.long 0x0 26. "EDVLP,Enable Double VLAN Processing When this bit is set the MAC enables processing of up to two VLAN Tags on Tx and Rx (if present). When this bit is reset the MAC enables processing of up to one VLAN Tag on Tx and Rx (if present). 0x0: Double VLAN.." "Double VLAN Processing is disabled,Double VLAN Processing is enabled" newline bitfld.long 0x0 25. "VTHM,VLAN Tag Hash Table Match Enable When this bit is set the most significant four bits of CRC of VLAN Tag (ones-complement of most significant four bits of CRC of VLAN Tag when ETV bit is reset) are used to index the content of the.." "VLAN Tag Hash Table Match is disabled,VLAN Tag Hash Table Match is enabled" newline bitfld.long 0x0 24. "EVLRXS,Enable VLAN Tag in Rx status When this bit is set MAC provides the outer VLAN Tag in the Rx status. When this bit is reset the MAC does not provide the outer VLAN Tag in Rx status. 0x0: VLAN Tag in Rx status is disabled 0x1: VLAN Tag in Rx.." "VLAN Tag in Rx status is disabled,VLAN Tag in Rx status is enabled" newline rbitfld.long 0x0 23. "RESERVED_23,Reserved." "0,1" newline bitfld.long 0x0 21.--22. "EVLS,Enable VLAN Tag Stripping on Receive This field indicates the stripping operation on the outer VLAN Tag in received packet. 0x3: Always strip 0x0: Do not strip 0x2: Strip if VLAN filter fails 0x1: Strip if VLAN filter passes" "Do not strip,Strip if VLAN filter passes,Strip if VLAN filter fails,Always strip" newline rbitfld.long 0x0 19.--20. "RESERVED_20_19,Reserved." "0,1,2,3" newline bitfld.long 0x0 18. "ESVL,Enable S-VLAN When this bit is set the MAC transmitter and receiver consider the S-VLAN packets (Type = 0x88A8) as valid VLAN tagged packets. 0x0: S-VLAN is disabled 0x1: S-VLAN is enabled" "S-VLAN is disabled,S-VLAN is enabled" newline bitfld.long 0x0 17. "VTIM,VLAN Tag Inverse Match Enable When this bit is set this bit enables the VLAN Tag inverse matching. The packets without matching VLAN Tag are marked as matched. When reset this bit enables the VLAN Tag perfect matching. The packets with matched.." "VLAN Tag Inverse Match is disabled,VLAN Tag Inverse Match is enabled" newline hexmask.long.word 0x0 7.--16. 1. "RESERVED_16_7,Reserved." newline hexmask.long.byte 0x0 2.--6. 1. "OFS,Offset This field holds the address offset of the MAC VLAN Tag Filter Register which the application is trying to access. The width of the field depends on the number of MAC VLAN Tag Registers enabled." newline bitfld.long 0x0 1. "CT,Command Type This bit indicates if the current register access is a read or a write. When set it indicate a read operation. When reset it indicates a write operation. 0x1: Read operation 0x0: Write operation" "Write operation,Read operation" newline bitfld.long 0x0 0. "OB,Operation Busy This bit is set along with a read or write command for initiating the indirect access to per VLAN Tag Filter register. This bit is reset when the read or write command to per VLAN Tag Filter indirect access register is complete. The.." "Operation Busy is disabled,Operation Busy is enabled" line.long 0x4 "MAC_VLAN_TAG_DATA,This register holds the read/write data for Indirect Access of the Per VLAN Tag registers. During the read access. this field contains valid read data only after the OB bit is reset. During the write access. this field should be valid.." hexmask.long.byte 0x4 28.--31. 1. "RESERVED_31_Y,Reserved." newline bitfld.long 0x4 25.--27. "DMACHN,DMA Channel Number The DMA Channel number to which the VLAN Tagged Frame is to be routed if it passes this VLAN Tag Filter is programmed in this field. If the Routing based on VLAN Tag Filter is not necessary this field need not be programmed." "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 24. "DMACHEN,DMA Channel Number Enable This bit is the Enable for the DMA Channel Number value programmed in the field DMACH. When this bit is reset the Routing does not occur based on VLAN Filter result. The frame is routed based on DA Based DMA Channel.." "DMA Channel Number is disabled,DMA Channel Number is enabled" newline rbitfld.long 0x4 21.--23. "RESERVED_23_21,Reserved." "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 20. "ERIVLT,Enable Inner VLAN Tag Comparison This bit is valid only when VLAN Tag Enable of the Filter is set. When this bit and the EDVLP field are set the MAC receiver enables operation on the inner VLAN Tag (if present). When this bit is reset the MAC.." "Inner VLAN tag comparison is disabled,Inner VLAN tag comparison is enabled" newline bitfld.long 0x4 19. "ERSVLM,Enable S-VLAN Match for received Frames This bit is valid only when VLAN Tag Enable of the Filter is set. When this bit is set the MAC receiver enables filtering or matching for S-VLAN (Type = 0x88A8) packets. When this bit is reset the MAC.." "Receive S-VLAN Match is disabled,Receive S-VLAN Match is enabled" newline bitfld.long 0x4 18. "DOVLTC,Disable VLAN Type Comparison This bit is valid only when VLAN Tag Enable of the Filter is set. When this bit is set the MAC does not check whether the VLAN Tag specified by the Enable Inner VLAN Tag Comparison bit is of type S-VLAN or C-VLAN." "VLAN type comparison is enabled,VLAN type comparison is disabled" newline bitfld.long 0x4 17. "ETV,12bits or 16bits VLAN comparison This bit is valid only when VEN of the Filter is set. When this bit is set a 12-bit VLAN identifier is used for comparing and filtering instead of the complete 16-bit VLAN tag. Bits [11:0] of VLAN tag are compared.." "0,1" newline bitfld.long 0x4 16. "VEN,VLAN Tag Enable This bit is used to enable or disable the VLAN Tag. When this bit is set the MAC compares the VLAN Tag of received packet with the VLAN Tag ID. When this bit is reset no comparison is performed irrespective of the programming of the.." "VLAN Tag is disabled,VLAN Tag is enabled" newline hexmask.long.word 0x4 0.--15. 1. "VID,VLAN Tag ID This field holds the VLAN Tag value which is used by the MAC for perfect comparison. It is valid when VLAN Tag Enable is set." line.long 0x8 "MAC_VLAN_HASH_TABLE,When VTHM bit of the MAC_VLAN_Tag register is set. the 16-bit VLAN Hash Table register is used for group address filtering based on the VLAN tag. For hash filtering. the content of the 16-bit VLAN tag or 12-bit VLAN ID (based on the.." hexmask.long.word 0x8 16.--31. 1. "RESERVED_31_16,Reserved." newline hexmask.long.word 0x8 0.--15. 1. "VLHT,VLAN Hash Table This field contains the 16-bit VLAN Hash Table." group.long 0x60++0x7 line.long 0x0 "MAC_VLAN_INCL,The VLAN Tag Inclusion or Replacement register contains the VLAN tag for insertion or replacement in the Transmit packets. It also contains the VLAN tag insertion controls." rbitfld.long 0x0 31. "BUSY,Busy This bit indicates the status of the read/write operation of indirect access to the queue/channel specific VLAN inclusion register. For write operation write to a register is complete when this bit is reset. For read operation the read data is.." "Busy status not detected,Busy status detected" newline bitfld.long 0x0 30. "RDWR,Read write control This bit controls the read or write operation for indirectly accessing the queue/channel specific VLAN Inclusion register. When set indicates write operation and when reset indicates read operation. This does not have any effect.." "Read operation of indirect access,Write operation of indirect access" newline rbitfld.long 0x0 27.--29. "RESERVED_29_Y,Reserved." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 24.--26. "ADDR,Address This field selects one of the queue/channel specific VLAN Inclusion register for read/write access. This does not have any effect when CBTI is reset." "0,1,2,3,4,5,6,7" newline rbitfld.long 0x0 22.--23. "RESERVED_23_22,Reserved." "0,1,2,3" newline bitfld.long 0x0 21. "CBTI,Channel based tag insertion When this bit is set outer VLAN tag is inserted for every packets transmitted by the MAC. The tag value is taken from the queue/channel specific VLAN tag register. The VLTI VLP VLC and VLT fields of this register are.." "Channel based tag insertion is disabled,Channel based tag insertion is enabled" newline bitfld.long 0x0 20. "VLTI,VLAN Tag Input When this bit is set it indicates that the VLAN tag to be inserted or replaced in Tx packet should be taken from: - The Tx descriptor 0x0: VLAN Tag Input is disabled 0x1: VLAN Tag Input is enabled" "VLAN Tag Input is disabled,VLAN Tag Input is enabled" newline bitfld.long 0x0 19. "CSVL,C-VLAN or S-VLAN When this bit is set S-VLAN type (0x88A8) is inserted or replaced in the 13th and 14th bytes of transmitted packets. When this bit is reset C-VLAN type (0x8100) is inserted or replaced in the 13th and 14th bytes of transmitted.." "C-VLAN type,S-VLAN type" newline bitfld.long 0x0 18. "VLP,VLAN Priority Control When this bit is set the control bits[17:16] are used for VLAN deletion insertion or replacement. When this bit is reset the mti_vlan_ctrl_i control input is used and bits[17:16] are ignored. 0x0: VLAN Priority Control is.." "VLAN Priority Control is disabled,VLAN Priority Control is enabled" newline bitfld.long 0x0 16.--17. "VLC,VLAN Tag Control in Transmit Packets - 2'b00: No VLAN tag deletion insertion or replacement - 2'b01: VLAN tag deletion The MAC removes the VLAN type (bytes 13 and 14) and VLAN tag (bytes 15 and 16) of all transmitted packets with VLAN tags. -.." "No VLAN tag deletion,VLAN tag deletion,VLAN tag insertion,VLAN tag replacement" newline hexmask.long.word 0x0 0.--15. 1. "VLT,VLAN Tag for Transmit Packets This field contains the value of the VLAN tag to be inserted or replaced. The value must only be changed when the transmit lines are inactive or during the initialization phase. Bits[15:13] are the User Priority field.." line.long 0x4 "MAC_INNER_VLAN_INCL,The Inner VLAN Tag Inclusion or Replacement register contains the inner VLAN tag to be inserted or replaced in the Transmit packet. It also contains the inner VLAN tag insertion controls." hexmask.long.word 0x4 21.--31. 1. "RESERVED_31_21,Reserved." newline bitfld.long 0x4 20. "VLTI,VLAN Tag Input When this bit is set it indicates that the VLAN tag to be inserted or replaced in Tx packet should be taken from: - The Tx descriptor 0x0: VLAN Tag Input is disabled 0x1: VLAN Tag Input is enabled" "VLAN Tag Input is disabled,VLAN Tag Input is enabled" newline bitfld.long 0x4 19. "CSVL,C-VLAN or S-VLAN When this bit is set S-VLAN type (0x88A8) is inserted or replaced in the 13th and 14th bytes of transmitted packets. When this bit is reset C-VLAN type (0x8100) is inserted or replaced in the 13th and 14th bytes of transmitted.." "C-VLAN type,S-VLAN type" newline bitfld.long 0x4 18. "VLP,VLAN Priority Control When this bit is set the VLC field is used for VLAN deletion insertion or replacement. When this bit is reset the mti_vlan_ctrl_i control input is used and the VLC field is ignored. 0x0: VLAN Priority Control is disabled.." "VLAN Priority Control is disabled,VLAN Priority Control is enabled" newline bitfld.long 0x4 16.--17. "VLC,VLAN Tag Control in Transmit Packets - 2'b00: No VLAN tag deletion insertion or replacement - 2'b01: VLAN tag deletion The MAC removes the VLAN type (bytes 17 and 18) and VLAN tag (bytes 19 and 20) of all transmitted packets with VLAN tags. -.." "No VLAN tag deletion,VLAN tag deletion,VLAN tag insertion,VLAN tag replacement" newline hexmask.long.word 0x4 0.--15. 1. "VLT,VLAN Tag for Transmit Packets This field contains the value of the VLAN tag to be inserted or replaced. The value must only be changed when the transmit lines are inactive or during the initialization phase. Bits[15:13] are the User Priority field.." group.long 0x70++0x13 line.long 0x0 "MAC_Q0_TX_FLOW_CTRL,The Flow Control register controls the generation and reception of the Control (Pause Command) packets by the Flow control module of the MAC. A Write to a register with the Busy bit set to 1 triggers the Flow Control block to generate.." hexmask.long.word 0x0 16.--31. 1. "PT,Pause Time This field holds the value to be used in the Pause Time field in the Tx control packet. If the Pause Time bits are configured to be double-synchronized to the (G)MII clock domain consecutive writes to this register should be performed only.." newline hexmask.long.byte 0x0 8.--15. 1. "RESERVED_15_8,Reserved." newline bitfld.long 0x0 7. "DZPQ,Disable Zero-Quanta Pause When this bit is set it disables the automatic generation of the zero-quanta Pause packets on de-assertion of the flow-control signal from the FIFO layer (MTL or external sideband flow control signal sbd_flowctrl_i or.." "Zero-Quanta Pause packet generation is enabled,Zero-Quanta Pause packet generation is disabled" newline bitfld.long 0x0 4.--6. "PLT,Pause Low Threshold This field configures the threshold of the Pause timer at which the input flow control signal mti_flowctrl_i (or sbd_flowctrl_i) is checked for automatic retransmission of the Pause packet. The threshold values should be always.." "Pause Time minus 4 Slot Times,Pause Time minus 28 Slot Times,Pause Time minus 36 Slot Times,Pause Time minus 144 Slot Times,Pause Time minus 256 Slot Times,Pause Time minus 512 Slot Times,Reserved,?" newline rbitfld.long 0x0 2.--3. "RESERVED_3_2,Reserved." "0,1,2,3" newline bitfld.long 0x0 1. "TFE,Transmit Flow Control Enable Full-Duplex Mode: In the full-duplex mode when this bit is set the MAC enables the flow control operation to Tx Pause packets. When this bit is reset the flow control operation in the MAC is disabled and the MAC does.." "Transmit Flow Control is disabled,Transmit Flow Control is enabled" newline bitfld.long 0x0 0. "FCB_BPA,Flow Control Busy or Backpressure Activate This bit initiates a Pause packet in the full-duplex mode and activates the backpressure function in the half-duplex mode if the TFE bit is set. Full-Duplex Mode: In the full-duplex mode this bit should.." "Flow Control Busy or Backpressure Activate is..,Flow Control Busy or Backpressure Activate is.." line.long 0x4 "MAC_Q1_TX_FLOW_CTRL,This register controls the generation of PFC Control packets of priorities mapped as per the PSRQi field in the MAC_RxQ_Ctrl2/MAC_RxQ_Ctrl3 registers." hexmask.long.word 0x4 16.--31. 1. "PT,Pause Time This field holds the value to be used in the Pause Time field in the Tx control packet. If the Pause Time bits are configured to be double-synchronized to the (G)MII clock domain consecutive writes to this register should be performed only.." newline hexmask.long.byte 0x4 8.--15. 1. "RESERVED_15_8,Reserved." newline bitfld.long 0x4 7. "DZPQ,Disable Zero-Quanta Pause When this bit is set it disables the automatic generation of the zero-quanta Pause packets on de-assertion of the flow-control signal from the FIFO layer (MTL or external sideband flow control signal sbd_flowctrl_i or.." "Zero-Quanta Pause packet generation is enabled,Zero-Quanta Pause packet generation is disabled" newline bitfld.long 0x4 4.--6. "PLT,Pause Low Threshold This field configures the threshold of the Pause timer at which the input flow control signal mti_flowctrl_i (or sbd_flowctrl_i) is checked for automatic retransmission of the Pause packet. The threshold values should be always.." "Pause Time minus 4 Slot Times,Pause Time minus 28 Slot Times,Pause Time minus 36 Slot Times,Pause Time minus 144 Slot Times,Pause Time minus 256 Slot Times,Pause Time minus 512 Slot Times,Reserved,?" newline rbitfld.long 0x4 2.--3. "RESERVED_3_2,Reserved." "0,1,2,3" newline bitfld.long 0x4 1. "TFE,Transmit Flow Control Enable When this bit is set in full-duplex mode the MAC enables the flow control operation to Tx Pause packets. When this bit is reset the flow control operation in the MAC is disabled and the MAC does not transmit any Pause.." "Transmit Flow Control is disabled,Transmit Flow Control is enabled" newline bitfld.long 0x4 0. "FCB_BPA,Flow Control Busy This bit initiates a PFC packet if the TFE bit is set. To initiate a PFC packet the application must set this bit to 1'b1. During Control packet transfer this bit continues to be set to indicate that a packet transmission is.." "Flow Control Busy or Backpressure Activate is..,Flow Control Busy or Backpressure Activate is.." line.long 0x8 "MAC_Q2_TX_FLOW_CTRL,This register controls the generation of PFC Control packets of priorities mapped as per the PSRQi field in the MAC_RxQ_Ctrl2/MAC_RxQ_Ctrl3 registers." hexmask.long.word 0x8 16.--31. 1. "PT,Pause Time This field holds the value to be used in the Pause Time field in the Tx control packet. If the Pause Time bits are configured to be double-synchronized to the (G)MII clock domain consecutive writes to this register should be performed only.." newline hexmask.long.byte 0x8 8.--15. 1. "RESERVED_15_8,Reserved." newline bitfld.long 0x8 7. "DZPQ,Disable Zero-Quanta Pause When this bit is set it disables the automatic generation of the zero-quanta Pause packets on de-assertion of the flow-control signal from the FIFO layer (MTL or external sideband flow control signal sbd_flowctrl_i or.." "Zero-Quanta Pause packet generation is enabled,Zero-Quanta Pause packet generation is disabled" newline bitfld.long 0x8 4.--6. "PLT,Pause Low Threshold This field configures the threshold of the Pause timer at which the input flow control signal mti_flowctrl_i (or sbd_flowctrl_i) is checked for automatic retransmission of the Pause packet. The threshold values should be always.." "Pause Time minus 4 Slot Times,Pause Time minus 28 Slot Times,Pause Time minus 36 Slot Times,Pause Time minus 144 Slot Times,Pause Time minus 256 Slot Times,Pause Time minus 512 Slot Times,Reserved,?" newline rbitfld.long 0x8 2.--3. "RESERVED_3_2,Reserved." "0,1,2,3" newline bitfld.long 0x8 1. "TFE,Transmit Flow Control Enable When this bit is set in full-duplex mode the MAC enables the flow control operation to Tx Pause packets. When this bit is reset the flow control operation in the MAC is disabled and the MAC does not transmit any Pause.." "Transmit Flow Control is disabled,Transmit Flow Control is enabled" newline bitfld.long 0x8 0. "FCB_BPA,Flow Control Busy This bit initiates a PFC packet if the TFE bit is set. To initiate a PFC packet the application must set this bit to 1'b1. During Control packet transfer this bit continues to be set to indicate that a packet transmission is.." "Flow Control Busy or Backpressure Activate is..,Flow Control Busy or Backpressure Activate is.." line.long 0xC "MAC_Q3_TX_FLOW_CTRL,This register controls the generation of PFC Control packets of priorities mapped as per the PSRQi field in the MAC_RxQ_Ctrl2/MAC_RxQ_Ctrl3 registers." hexmask.long.word 0xC 16.--31. 1. "PT,Pause Time This field holds the value to be used in the Pause Time field in the Tx control packet. If the Pause Time bits are configured to be double-synchronized to the (G)MII clock domain consecutive writes to this register should be performed only.." newline hexmask.long.byte 0xC 8.--15. 1. "RESERVED_15_8,Reserved." newline bitfld.long 0xC 7. "DZPQ,Disable Zero-Quanta Pause When this bit is set it disables the automatic generation of the zero-quanta Pause packets on de-assertion of the flow-control signal from the FIFO layer (MTL or external sideband flow control signal sbd_flowctrl_i or.." "Zero-Quanta Pause packet generation is enabled,Zero-Quanta Pause packet generation is disabled" newline bitfld.long 0xC 4.--6. "PLT,Pause Low Threshold This field configures the threshold of the Pause timer at which the input flow control signal mti_flowctrl_i (or sbd_flowctrl_i) is checked for automatic retransmission of the Pause packet. The threshold values should be always.." "Pause Time minus 4 Slot Times,Pause Time minus 28 Slot Times,Pause Time minus 36 Slot Times,Pause Time minus 144 Slot Times,Pause Time minus 256 Slot Times,Pause Time minus 512 Slot Times,Reserved,?" newline rbitfld.long 0xC 2.--3. "RESERVED_3_2,Reserved." "0,1,2,3" newline bitfld.long 0xC 1. "TFE,Transmit Flow Control Enable When this bit is set in full-duplex mode the MAC enables the flow control operation to Tx Pause packets. When this bit is reset the flow control operation in the MAC is disabled and the MAC does not transmit any Pause.." "Transmit Flow Control is disabled,Transmit Flow Control is enabled" newline bitfld.long 0xC 0. "FCB_BPA,Flow Control Busy This bit initiates a PFC packet if the TFE bit is set. To initiate a PFC packet the application must set this bit to 1'b1. During Control packet transfer this bit continues to be set to indicate that a packet transmission is.." "Flow Control Busy or Backpressure Activate is..,Flow Control Busy or Backpressure Activate is.." line.long 0x10 "MAC_Q4_TX_FLOW_CTRL,This register controls the generation of PFC Control packets of priorities mapped as per the PSRQi field in the MAC_RxQ_Ctrl2/MAC_RxQ_Ctrl3 registers." hexmask.long.word 0x10 16.--31. 1. "PT,Pause Time This field holds the value to be used in the Pause Time field in the Tx control packet. If the Pause Time bits are configured to be double-synchronized to the (G)MII clock domain consecutive writes to this register should be performed only.." newline hexmask.long.byte 0x10 8.--15. 1. "RESERVED_15_8,Reserved." newline bitfld.long 0x10 7. "DZPQ,Disable Zero-Quanta Pause When this bit is set it disables the automatic generation of the zero-quanta Pause packets on de-assertion of the flow-control signal from the FIFO layer (MTL or external sideband flow control signal sbd_flowctrl_i or.." "Zero-Quanta Pause packet generation is enabled,Zero-Quanta Pause packet generation is disabled" newline bitfld.long 0x10 4.--6. "PLT,Pause Low Threshold This field configures the threshold of the Pause timer at which the input flow control signal mti_flowctrl_i (or sbd_flowctrl_i) is checked for automatic retransmission of the Pause packet. The threshold values should be always.." "Pause Time minus 4 Slot Times,Pause Time minus 28 Slot Times,Pause Time minus 36 Slot Times,Pause Time minus 144 Slot Times,Pause Time minus 256 Slot Times,Pause Time minus 512 Slot Times,Reserved,?" newline rbitfld.long 0x10 2.--3. "RESERVED_3_2,Reserved." "0,1,2,3" newline bitfld.long 0x10 1. "TFE,Transmit Flow Control Enable When this bit is set in full-duplex mode the MAC enables the flow control operation to Tx Pause packets. When this bit is reset the flow control operation in the MAC is disabled and the MAC does not transmit any Pause.." "Transmit Flow Control is disabled,Transmit Flow Control is enabled" newline bitfld.long 0x10 0. "FCB_BPA,Flow Control Busy This bit initiates a PFC packet if the TFE bit is set. To initiate a PFC packet the application must set this bit to 1'b1. During Control packet transfer this bit continues to be set to indicate that a packet transmission is.." "Flow Control Busy or Backpressure Activate is..,Flow Control Busy or Backpressure Activate is.." group.long 0x90++0x1F line.long 0x0 "MAC_RX_FLOW_CTRL,The Receive Flow Control register controls the pausing of MAC Transmit based on the received Pause packet." hexmask.long.tbyte 0x0 9.--31. 1. "RESERVED_31_9,Reserved." newline bitfld.long 0x0 8. "PFCE,Priority Based Flow Control Enable When this bit is set it enables generation and reception of priority-based flow control (PFC) packets. When this bit is reset it enables generation and reception of 802.3x Pause control packets. 0x0: Priority.." "Priority Based Flow Control is disabled,Priority Based Flow Control is enabled" newline hexmask.long.byte 0x0 2.--7. 1. "RESERVED_7_2,Reserved." newline bitfld.long 0x0 1. "UP,Unicast Pause Packet Detect A pause packet is processed when it has the unique multicast address specified in the IEEE 802.3. When this bit is set the MAC can also detect Pause packets with unicast address of the station. This unicast address should.." "Unicast Pause Packet Detect disabled,Unicast Pause Packet Detect enabled" newline bitfld.long 0x0 0. "RFE,Receive Flow Control Enable When this bit is set and the MAC is operating in full-duplex mode the MAC decodes the received Pause packet and disables its transmitter for a specified (Pause) time. When this bit is reset or the MAC is operating in.." "Receive Flow Control is disabled,Receive Flow Control is enabled" line.long 0x4 "MAC_RXQ_CTRL4,The Receive Queue Control 4 register controls the routing of unicast and multicast packets that fail the Destination or Source address filter to the Rx queues." hexmask.long.word 0x4 20.--31. 1. "RESERVED_31_Y,Reserved." newline bitfld.long 0x4 17.--19. "VFFQ,VLAN Tag Filter Fail Packets Queue This field holds the Rx queue number to which the tagged packets failing the Destination or Source Address filter (and UFFQE/MFFQE not enabled) or failing the VLAN tag filter must be routed to. This field is valid.." "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 16. "VFFQE,VLAN Tag Filter Fail Packets Queuing Enable When this bit is set the tagged packets which fail the Destination or Source address filter or fail the VLAN tag filter are routed to the Rx Queue Number programmed in the VFFQ. When this bit is reset.." "VLAN tag Filter Fail Packets Queuing is disabled,VLAN tag Filter Fail Packets Queuing is enabled" newline hexmask.long.byte 0x4 12.--15. 1. "RESERVED_15_Y,Reserved." newline bitfld.long 0x4 9.--11. "MFFQ,Multicast Address Filter Fail Packets Queue. This field holds the Rx queue number to which the Multicast packets failing the Destination or Source Address filter are routed to. This field is valid only when the MFFQE bit is set." "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 8. "MFFQE,Multicast Address Filter Fail Packets Queuing Enable. When this bit is set the Multicast packets which fail the Destination or Source address filter is routed to the Rx Queue Number programmed in the MFFQ. When this bit is reset the Multicast.." "Multicast Address Filter Fail Packets Queuing is..,Multicast Address Filter Fail Packets Queuing is.." newline hexmask.long.byte 0x4 4.--7. 1. "RESERVED_7_Y,Reserved." newline bitfld.long 0x4 1.--3. "UFFQ,Unicast Address Filter Fail Packets Queue. This field holds the Rx queue number to which the Unicast packets failing the Destination or Source Address filter are routed to. This field is valid only when the UFFQE bit is set." "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 0. "UFFQE,Unicast Address Filter Fail Packets Queuing Enable. When this bit is set the Unicast packets which fail the Destination or Source address filter is routed to the Rx Queue Number programmed in the UFFQ. When this bit is reset the Unicast packets.." "Unicast Address Filter Fail Packets Queuing is..,Unicast Address Filter Fail Packets Queuing is.." line.long 0x8 "MAC_TXQ_PRTY_MAP0,The Transmit Queue Priority Mapping 0 register contains the priority values assigned to Tx Queue 0 through Tx Queue 3." hexmask.long.byte 0x8 24.--31. 1. "PSTQ3,Priorities Selected in Transmit Queue 3 This bit is similar to the PSTQ0 bit." newline hexmask.long.byte 0x8 16.--23. 1. "PSTQ2,Priorities Selected in Transmit Queue 2 This bit is similar to the PSTQ0 bit." newline hexmask.long.byte 0x8 8.--15. 1. "PSTQ1,Priorities Selected in Transmit Queue 1 This bit is similar to the PSTQ0 bit." newline hexmask.long.byte 0x8 0.--7. 1. "PSTQ0,Priorities Selected in Transmit Queue 0 This field holds the priorities assigned to Tx Queue 0 by the software. This field determines if Tx Queue 0 should be blocked from transmitting specified pause time when a PFC packet is received with.." line.long 0xC "MAC_TXQ_PRTY_MAP1,The Transmit Queue Priority Mapping 1 register contains the priority values assigned to Tx Queue 4 through Tx Queue 7." hexmask.long.byte 0xC 24.--31. 1. "RESERVED_PSTQ7,Reserved." newline hexmask.long.byte 0xC 16.--23. 1. "RESERVED_PSTQ6,Reserved." newline hexmask.long.byte 0xC 8.--15. 1. "RESERVED_PSTQ5,Reserved." newline hexmask.long.byte 0xC 0.--7. 1. "PSTQ4,Priorities Selected in Transmit Queue 4 This field holds the priorities assigned to Tx Queue 4 by the software. This field determines if Tx Queue 4 should be blocked from transmitting specified pause time when a PFC packet is received with.." line.long 0x10 "MAC_RXQ_CTRL0,The Receive Queue Control 0 register controls the queue management in the MAC Receiver. Note: In multiple Rx queues configuration. all the queues are disabled by default. Enable the Rx queue by programming the corresponding field in this.." hexmask.long.word 0x10 16.--31. 1. "RESERVED_31_16,Reserved." newline rbitfld.long 0x10 14.--15. "RESERVED_RXQ7EN,Reserved." "0,1,2,3" newline rbitfld.long 0x10 12.--13. "RESERVED_RXQ6EN,Reserved." "0,1,2,3" newline rbitfld.long 0x10 10.--11. "RESERVED_RXQ5EN,Reserved." "0,1,2,3" newline bitfld.long 0x10 8.--9. "RXQ4EN,Receive Queue 4 Enable This field is similar to the RXQ0EN field. 0x0: Queue not enabled 0x1: Queue enabled for AV 0x2: Queue enabled for DCB/Generic 0x3: Reserved" "Queue not enabled,Queue enabled for AV,Queue enabled for DCB/Generic,Reserved" newline bitfld.long 0x10 6.--7. "RXQ3EN,Receive Queue 3 Enable This field is similar to the RXQ0EN field. 0x0: Queue not enabled 0x1: Queue enabled for AV 0x2: Queue enabled for DCB/Generic 0x3: Reserved" "Queue not enabled,Queue enabled for AV,Queue enabled for DCB/Generic,Reserved" newline bitfld.long 0x10 4.--5. "RXQ2EN,Receive Queue 2 Enable This field is similar to the RXQ0EN field. 0x0: Queue not enabled 0x1: Queue enabled for AV 0x2: Queue enabled for DCB/Generic 0x3: Reserved" "Queue not enabled,Queue enabled for AV,Queue enabled for DCB/Generic,Reserved" newline bitfld.long 0x10 2.--3. "RXQ1EN,Receive Queue 1 Enable This field is similar to the RXQ0EN field. 0x0: Queue not enabled 0x1: Queue enabled for AV 0x2: Queue enabled for DCB/Generic 0x3: Reserved" "Queue not enabled,Queue enabled for AV,Queue enabled for DCB/Generic,Reserved" newline bitfld.long 0x10 0.--1. "RXQ0EN,Receive Queue 0 Enable This field indicates whether Rx Queue 0 is enabled for AV or DCB. 0x0: Queue not enabled 0x1: Queue enabled for AV 0x2: Queue enabled for DCB/Generic 0x3: Reserved" "Queue not enabled,Queue enabled for AV,Queue enabled for DCB/Generic,Reserved" line.long 0x14 "MAC_RXQ_CTRL1,The Receive Queue Control 1 register controls the routing of multicast. broadcast. AV. DCB. and untagged packets to the Rx queues." hexmask.long.byte 0x14 27.--31. 1. "RESERVED_31_Y,Reserved." newline bitfld.long 0x14 24.--26. "FPRQ,Frame Preemption Residue Queue This field holds the Rx queue number to which the residual preemption frames must be forwarded. Preemption frames that are tagged and pass the SA/DA/VLAN filtering are routed based on PSRQ and all other frames are.." "0,1,2,3,4,5,6,7" newline bitfld.long 0x14 22.--23. "TPQC,Tagged PTP over Ethernet Packets Queuing Control. This field controls the routing of the VLAN Tagged PTPoE packets. If DWC_EQOS_AV_ENABLE is selected in the configuration the following programmable options are allowed. - 2'b00: VLAN Tagged PTPoE.." "VLAN Tagged PTPoE packets are routed as generic..,VLAN Tagged PTPoE packets are routed to Rx..,VLAN Tagged PTPoE packets are routed to only AV..,Reserved" newline bitfld.long 0x14 21. "TACPQE,Tagged AV Control Packets Queuing Enable. When set the MAC routes the received Tagged AV Control packets to the Rx queue specified by AVCPQ field. When reset the MAC routes the received Tagged AV Control packets based on the tag priority.." "Tagged AV Control Packets Queuing is disabled,Tagged AV Control Packets Queuing is enabled" newline bitfld.long 0x14 20. "MCBCQEN,Multicast and Broadcast Queue Enable This bit specifies that Multicast or Broadcast packets routing to the Rx Queue is enabled and the Multicast or Broadcast packets must be routed to Rx Queue specified in MCBCQ field. 0x0: Multicast and.." "Multicast and Broadcast Queue is disabled,Multicast and Broadcast Queue is enabled" newline rbitfld.long 0x14 19. "RESERVED_19,Reserved." "0,1" newline bitfld.long 0x14 16.--18. "MCBCQ,Multicast and Broadcast Queue This field specifies the Rx Queue onto which Multicast or Broadcast Packets are routed. Any Rx Queue enabled for Generic/DCB/AV traffic can be used to route the Multicast or Broadcast Packets. 0x0: Receive Queue 0 0x1:.." "Receive Queue 0,Receive Queue 1,Receive Queue 2,Receive Queue 3,Receive Queue 4,Receive Queue 5,Receive Queue 6,Receive Queue 7" newline rbitfld.long 0x14 15. "RESERVED_15,Reserved." "0,1" newline bitfld.long 0x14 12.--14. "UPQ,Untagged Packet Queue This field indicates the Rx Queue to which Untagged Packets are to be routed. Any Rx Queue enabled for Generic/DCB/AV traffic can be used to route the Untagged Packets. 0x0: Receive Queue 0 0x1: Receive Queue 1 0x2: Receive.." "Receive Queue 0,Receive Queue 1,Receive Queue 2,Receive Queue 3,Receive Queue 4,Receive Queue 5,Receive Queue 6,Receive Queue 7" newline rbitfld.long 0x14 11. "RESERVED_11,Reserved." "0,1" newline bitfld.long 0x14 8.--10. "DCBCPQ,DCB Control Packets Queue This field specifies the Rx queue on which the received DCB control packets are routed. The DCB data packets are routed based on the PSRQ field of the Transmit Flow Control Register of corresponding queue. 0x0: Receive.." "Receive Queue 0,Receive Queue 1,Receive Queue 2,Receive Queue 3,Receive Queue 4,Receive Queue 5,Receive Queue 6,Receive Queue 7" newline rbitfld.long 0x14 7. "RESERVED_7,Reserved." "0,1" newline bitfld.long 0x14 4.--6. "PTPQ,PTP Packets Queue This field specifies the Rx queue on which the PTP packets sent over the Ethernet payload (not over IPv4 or IPv6) are routed. When the AV8021ASMEN bit of MAC_Timestamp_Control register is set only untagged PTP over Ethernet.." "Receive Queue 0,Receive Queue 1,Receive Queue 2,Receive Queue 3,Receive Queue 4,Receive Queue 5,Receive Queue 6,Receive Queue 7" newline rbitfld.long 0x14 3. "RESERVED_3,Reserved." "0,1" newline bitfld.long 0x14 0.--2. "AVCPQ,AV Untagged Control Packets Queue This field specifies the Receive queue on which the received AV tagged and untagged control packets are routed. The AV tagged (when TACPQE bit is set) and untagged control packets are routed to Receive queue.." "Receive Queue 0,Receive Queue 1,Receive Queue 2,Receive Queue 3,Receive Queue 4,Receive Queue 5,Receive Queue 6,Receive Queue 7" line.long 0x18 "MAC_RXQ_CTRL2,This register controls the routing of tagged packets based on the USP (user Priority) field of the received packets to the RxQueues 0 to 3." hexmask.long.byte 0x18 24.--31. 1. "PSRQ3,Priorities Selected in the Receive Queue 3 This field decides the priorities assigned to Rx Queue 3. All packets with priorities that match the values set in this field are routed to Rx Queue 3. For example if PSRQ3[6 3] are set packets with USP.." newline hexmask.long.byte 0x18 16.--23. 1. "PSRQ2,Priorities Selected in the Receive Queue 2 This field decides the priorities assigned to Rx Queue 2. All packets with priorities that match the values set in this field are routed to Rx Queue 2. For example if PSRQ2[1 0] are set packets with USP.." newline hexmask.long.byte 0x18 8.--15. 1. "PSRQ1,Priorities Selected in the Receive Queue 1 This field decides the priorities assigned to Rx Queue 1. All packets with priorities that match the values set in this field are routed to Rx Queue 1. For example if PSRQ1[4] is set packets with USP.." newline hexmask.long.byte 0x18 0.--7. 1. "PSRQ0,Priorities Selected in the Receive Queue 0 This field decides the priorities assigned to Rx Queue 0. All packets with priorities that match the values set in this field are routed to Rx Queue 0. For example if PSRQ0[5] is set packets with USP.." line.long 0x1C "MAC_RXQ_CTRL3,This register controls the routing of tagged packets based on the USP (user Priority) field of the received packets to the RxQueues 4 to 7." hexmask.long.byte 0x1C 24.--31. 1. "RESERVED_PSRQ7,Reserved." newline hexmask.long.byte 0x1C 16.--23. 1. "RESERVED_PSRQ6,Reserved." newline hexmask.long.byte 0x1C 8.--15. 1. "RESERVED_PSRQ5,Reserved." newline hexmask.long.byte 0x1C 0.--7. 1. "PSRQ4,Priorities Selected in the Receive Queue 4 This field decides the priorities assigned to Rx Queue 4. All packets with priorities that match the values set in this field are routed to Rx Queue 4. For example if PSRQ4[7:4] is set packets with USP.." rgroup.long 0xB0++0x3 line.long 0x0 "MAC_INTERRUPT_STATUS,The Interrupt Status register contains the status of interrupts." hexmask.long.word 0x0 21.--31. 1. "RESERVED_31_21,Reserved." newline bitfld.long 0x0 20. "MFRIS,MMC FPE Receive Interrupt Status This bit is set high when an interrupt is generated in the MMC FPE Receive Interrupt Register. This bit is cleared when all bits in this interrupt register are cleared. This bit is valid only when you select the.." "MMC FPE Receive Interrupt status not active,MMC FPE Receive Interrupt status active" newline bitfld.long 0x0 19. "MFTIS,MMC FPE Transmit Interrupt Status This bit is set high when an interrupt is generated in the MMC FPE Transmit Interrupt Register. This bit is cleared when all bits in this interrupt register are cleared. This bit is valid only when you select the.." "MMC FPE Transmit Interrupt status not active,MMC FPE Transmit Interrupt status active" newline bitfld.long 0x0 18. "MDIOIS,MDIO Interrupt Status This bit indicates an interrupt event after the completion of MDIO operation. To reset this bit the application has to read this bit/Write 1 to this bit when RCWE bit of MAC_CSR_SW_Ctrl register is set. Access restriction.." "MDIO Interrupt status not active,MDIO Interrupt status active" newline bitfld.long 0x0 17. "FPEIS,Frame Preemption Interrupt Status This bit indicates an interrupt event during the operation of Frame Preemption (Bits[19:16] of MAC_FPE_CTRL_STS register is set). To reset this bit the application must clear the event in MAC_FPE_CTRL_STS that has.." "Frame Preemption Interrupt status not active,Frame Preemption Interrupt status active" newline bitfld.long 0x0 16. "RESERVED_16,Reserved." "0,1" newline bitfld.long 0x0 15. "RESERVED_GPIIS,Reserved." "0,1" newline bitfld.long 0x0 14. "RXSTSIS,Receive Status Interrupt This bit indicates the status of received packets. This bit is set when the RWT bit is set in the MAC_Rx_Tx_Status register. This bit is cleared when the corresponding interrupt source bit is read (or corresponding.." "Receive Interrupt status not active,Receive Interrupt status active" newline bitfld.long 0x0 13. "TXSTSIS,Transmit Status Interrupt This bit indicates the status of transmitted packets. This bit is set when any of the following bits is set in the MAC_Rx_Tx_Status register: - Excessive Collision (EXCOL) - Late Collision (LCOL) - Excessive Deferral.." "Transmit Interrupt status not active,Transmit Interrupt status active" newline bitfld.long 0x0 12. "TSIS,Timestamp Interrupt Status If the Timestamp feature is enabled this bit is set when any of the following conditions is true: - The system time value is equal to or exceeds the value specified in the Target Time High and Low registers. - There is an.." "Timestamp Interrupt status not active,Timestamp Interrupt status active" newline bitfld.long 0x0 11. "MMCRXIPIS,MMC Receive Checksum Offload Interrupt Status This bit is set high when an interrupt is generated in the MMC Receive Checksum Offload Interrupt Register. This bit is cleared when all bits in this interrupt register are cleared. This bit is.." "MMC Receive Checksum Offload Interrupt status..,MMC Receive Checksum Offload Interrupt status.." newline bitfld.long 0x0 10. "MMCTXIS,MMC Transmit Interrupt Status This bit is set high when an interrupt is generated in the MMC Transmit Interrupt Register. This bit is cleared when all bits in this interrupt register are cleared. This bit is valid only when you select the Enable.." "MMC Transmit Interrupt status not active,MMC Transmit Interrupt status active" newline bitfld.long 0x0 9. "MMCRXIS,MMC Receive Interrupt Status This bit is set high when an interrupt is generated in the MMC Receive Interrupt Register. This bit is cleared when all bits in this interrupt register are cleared. This bit is valid only when you select the Enable.." "MMC Receive Interrupt status not active,MMC Receive Interrupt status active" newline bitfld.long 0x0 8. "MMCIS,MMC Interrupt Status This bit is set high when Bit 11 Bit 10 or Bit 9 is set high. This bit is cleared only when all these bits are low. This bit is valid only when you select the Enable MAC Management Counters (MMC) option. 0x1: MMC Interrupt.." "MMC Interrupt status not active,MMC Interrupt status active" newline bitfld.long 0x0 6.--7. "RESERVED_7_6,Reserved." "0,1,2,3" newline bitfld.long 0x0 5. "LPIIS,LPI Interrupt Status When the Energy Efficient Ethernet feature is enabled this bit is set for any LPI state entry or exit in the MAC Transmitter or Receiver. This bit is cleared when the corresponding interrupt source bit of.." "LPI Interrupt status not active,LPI Interrupt status active" newline bitfld.long 0x0 4. "PMTIS,PMT Interrupt Status This bit is set when a Magic packet or Wake-on-LAN packet is received in the power-down mode (RWKPRCVD and MGKPRCVD bits in MAC_PMT_Control_Status register). This bit is cleared when corresponding interrupt source bit are.." "PMT Interrupt status not active,PMT Interrupt status active" newline bitfld.long 0x0 3. "PHYIS,PHY Interrupt This bit is set when rising edge is detected on the phy_intr_i input. This bit is cleared when this register is read (or this bit is written to 1 when RCWE bit of MAC_CSR_SW_Ctrl register is set). 0x1: PHY Interrupt detected 0x0: PHY.." "PHY Interrupt not detected,PHY Interrupt detected" newline bitfld.long 0x0 2. "RESERVED_PCSANCIS,Reserved." "0,1" newline bitfld.long 0x0 1. "RESERVED_PCSLCHGIS,Reserved." "0,1" newline bitfld.long 0x0 0. "RGSMIIIS,RGMII or SMII Interrupt Status This bit is set because of any change in value of the Link Status of RGMII or SMII interface (LNKSTS bit in MAC_PHYIF_Control_Status register). This bit is cleared when the MAC_PHYIF_Control_Status register is read.." "RGMII or SMII Interrupt Status is not active,RGMII or SMII Interrupt Status is active" group.long 0xB4++0x3 line.long 0x0 "MAC_INTERRUPT_ENABLE,The Interrupt Enable register contains the masks for generating the interrupts." hexmask.long.word 0x0 19.--31. 1. "RESERVED_31_19,Reserved." newline bitfld.long 0x0 18. "MDIOIE,MDIO Interrupt Enable When this bit is set it enables the assertion of the interrupt when MDIOIS field is set in the MAC_Interrupt_Status register. 0x0: MDIO Interrupt is disabled 0x1: MDIO Interrupt is enabled" "MDIO Interrupt is disabled,MDIO Interrupt is enabled" newline bitfld.long 0x0 17. "FPEIE,Frame Preemption Interrupt Enable When this bit is set it enables the assertion of the interrupt when FPEIS field is set in the MAC_Interrupt_Status register. 0x0: Frame Preemption Interrupt is disabled 0x1: Frame Preemption Interrupt is enabled" "Frame Preemption Interrupt is disabled,Frame Preemption Interrupt is enabled" newline rbitfld.long 0x0 16. "RESERVED_16,Reserved." "0,1" newline rbitfld.long 0x0 15. "RESERVED_15,Reserved." "0,1" newline bitfld.long 0x0 14. "RXSTSIE,Receive Status Interrupt Enable When this bit is set it enables the assertion of the interrupt signal because of the setting of RXSTSIS bit in the MAC_Interrupt_Status register. 0x0: Receive Status Interrupt is disabled 0x1: Receive Status.." "Receive Status Interrupt is disabled,Receive Status Interrupt is enabled" newline bitfld.long 0x0 13. "TXSTSIE,Transmit Status Interrupt Enable When this bit is set it enables the assertion of the interrupt signal because of the setting of TXSTSIS bit in the MAC_Interrupt_Status register. 0x0: Timestamp Status Interrupt is disabled 0x1: Timestamp Status.." "Timestamp Status Interrupt is disabled,Timestamp Status Interrupt is enabled" newline bitfld.long 0x0 12. "TSIE,Timestamp Interrupt Enable When this bit is set it enables the assertion of the interrupt signal because of the setting of TSIS bit in MAC_Interrupt_Status register. 0x0: Timestamp Interrupt is disabled 0x1: Timestamp Interrupt is enabled" "Timestamp Interrupt is disabled,Timestamp Interrupt is enabled" newline hexmask.long.byte 0x0 6.--11. 1. "RESERVED_11_6,Reserved." newline bitfld.long 0x0 5. "LPIIE,LPI Interrupt Enable When this bit is set it enables the assertion of the interrupt signal because of the setting of LPIIS bit in MAC_Interrupt_Status register. 0x0: LPI Interrupt is disabled 0x1: LPI Interrupt is enabled" "LPI Interrupt is disabled,LPI Interrupt is enabled" newline bitfld.long 0x0 4. "PMTIE,PMT Interrupt Enable When this bit is set it enables the assertion of the interrupt signal because of the setting of PMTIS bit in MAC_Interrupt_Status register. 0x0: PMT Interrupt is disabled 0x1: PMT Interrupt is enabled" "PMT Interrupt is disabled,PMT Interrupt is enabled" newline bitfld.long 0x0 3. "PHYIE,PHY Interrupt Enable When this bit is set it enables the assertion of the interrupt signal because of the setting of PHYIS bit in MAC_Interrupt_Status register. 0x0: PHY Interrupt is disabled 0x1: PHY Interrupt is enabled" "PHY Interrupt is disabled,PHY Interrupt is enabled" newline rbitfld.long 0x0 2. "RESERVED_PCSANCIE,Reserved." "0,1" newline rbitfld.long 0x0 1. "RESERVED_PCSLCHGIE,Reserved." "0,1" newline bitfld.long 0x0 0. "RGSMIIIE,RGMII or SMII Interrupt Enable When this bit is set it enables the assertion of the interrupt signal because of the setting of RGSMIIIS bit in MAC_Interrupt_Status register. 0x0: RGMII or SMII Interrupt is disabled 0x1: RGMII or SMII Interrupt.." "RGMII or SMII Interrupt is disabled,RGMII or SMII Interrupt is enabled" rgroup.long 0xB8++0x3 line.long 0x0 "MAC_RX_TX_STATUS,The Receive Transmit Status register contains the Receive and Transmit Error status." hexmask.long.tbyte 0x0 9.--31. 1. "RESERVED_31_9,Reserved." newline bitfld.long 0x0 8. "RWT,Receive Watchdog Timeout This bit is set when a packet with length greater than 2 048 bytes is received (10 240 bytes when Jumbo Packet mode is enabled) and the WD bit is reset in the MAC_Configuration register. This bit is set when a packet with.." "No receive watchdog timeout,Receive watchdog timed out" newline bitfld.long 0x0 6.--7. "RESERVED_7_6,Reserved." "0,1,2,3" newline bitfld.long 0x0 5. "EXCOL,Excessive Collisions When the DTXSTS bit is set in the MTL_Operation_Mode register this bit indicates that the transmission aborted after 16 successive collisions while attempting to transmit the current packet. If the DR bit is set in the.." "No collision,Excessive collision is sensed" newline bitfld.long 0x0 4. "LCOL,Late Collision When the DTXSTS bit is set in the MTL_Operation_Mode register this bit indicates that the packet transmission aborted because a collision occurred after the collision window (64 bytes including Preamble in MII mode; 512 bytes.." "No collision,Late collision is sensed" newline bitfld.long 0x0 3. "EXDEF,Excessive Deferral When the DTXSTS bit is set in the MTL_Operation_Mode register and the DC bit is set in the MAC_Configuration register this bit indicates that the transmission ended because of excessive deferral of over 24 288 bit times (155 680.." "No Excessive deferral,Excessive deferral" newline bitfld.long 0x0 2. "LCARR,Loss of Carrier When the DTXSTS bit is set in the MTL_Operation_Mode register this bit indicates that the loss of carrier occurred during packet transmission that is the phy_crs_i signal was inactive for one or more transmission clock periods.." "Carrier is present,Loss of carrier" newline bitfld.long 0x0 1. "NCARR,No Carrier When the DTXSTS bit is set in the MTL_Operation_Mode register this bit indicates that the carrier signal from the PHY is not present at the end of preamble transmission. Access restriction applies. Clears on read (or write of 1 when.." "Carrier is present,No carrier" newline bitfld.long 0x0 0. "TJT,Transmit Jabber Timeout This bit indicates that the Transmit Jabber Timer expired which happens when the packet size exceeds 2 048 bytes (10 240 bytes when the Jumbo packet is enabled) and JD bit is reset in the MAC_Configuration register. This bit.." "No Transmit Jabber Timeout,Transmit Jabber Timeout occurred" group.long 0xC0++0x7 line.long 0x0 "MAC_PMT_CONTROL_STATUS,The PMT Control and Status Register." bitfld.long 0x0 31. "RWKFILTRST,Remote Wake-Up Packet Filter Register Pointer Reset When this bit is set the remote wake-up packet filter register pointer is reset to 3'b000. It is automatically cleared after 1 clock cycle. Access restriction applies. Setting 1 sets." "Remote Wake-Up Packet Filter Register Pointer is..,Remote Wake-Up Packet Filter Register Pointer is.." newline rbitfld.long 0x0 29.--30. "RESERVED_30_29,Reserved." "0,1,2,3" newline hexmask.long.byte 0x0 24.--28. 1. "RWKPTR,Remote Wake-up FIFO Pointer This field gives the current value (0 to 7 15 or 31 when 4 8 or 16 Remote Wake-up Packet Filters are selected) of the Remote Wake-up Packet Filter register pointer. When the value of this pointer is equal to maximum.." newline hexmask.long.word 0x0 11.--23. 1. "RESERVED_23_11,Reserved." newline bitfld.long 0x0 10. "RWKPFE,Remote Wake-up Packet Forwarding Enable When this bit is set along with RWKPKTEN the MAC receiver drops all received frames until it receives the expected Wake-up frame. All frames after that event including the received wake-up frame are.." "Remote Wake-up Packet Forwarding is disabled,Remote Wake-up Packet Forwarding is enabled" newline bitfld.long 0x0 9. "GLBLUCAST,Global Unicast When this bit set any unicast packet filtered by the MAC (DAF) address recognition is detected as a remote wake-up packet. 0x0: Global unicast is disabled 0x1: Global unicast is enabled" "Global unicast is disabled,Global unicast is enabled" newline rbitfld.long 0x0 7.--8. "RESERVED_8_7,Reserved." "0,1,2,3" newline rbitfld.long 0x0 6. "RWKPRCVD,Remote Wake-Up Packet Received When this bit is set it indicates that the power management event is generated because of the reception of a remote wake-up packet. This bit is cleared when this register is read. Access restriction applies." "Remote wake-up packet is received,Remote wake-up packet is received" newline rbitfld.long 0x0 5. "MGKPRCVD,Magic Packet Received When this bit is set it indicates that the power management event is generated because of the reception of a magic packet. This bit is cleared when this register is read. Access restriction applies. Clears on read (or.." "No Magic packet is received,Magic packet is received" newline rbitfld.long 0x0 3.--4. "RESERVED_4_3,Reserved." "0,1,2,3" newline bitfld.long 0x0 2. "RWKPKTEN,Remote Wake-Up Packet Enable When this bit is set a power management event is generated when the MAC receives a remote wake-up packet. 0x0: Remote wake-up packet is disabled 0x1: Remote wake-up packet is enabled" "Remote wake-up packet is disabled,Remote wake-up packet is enabled" newline bitfld.long 0x0 1. "MGKPKTEN,Magic Packet Enable When this bit is set a power management event is generated when the MAC receives a magic packet. 0x0: Magic Packet is disabled 0x1: Magic Packet is enabled" "Magic Packet is disabled,Magic Packet is enabled" newline bitfld.long 0x0 0. "PWRDWN,Power Down When this bit is set the MAC receiver drops all received packets until it receives the expected magic packet or remote wake-up packet. This bit is then self-cleared and the power-down mode is disabled. The software can clear this bit.." "Power down is disabled,Power down is enabled" line.long 0x4 "MAC_RWK_PACKET_FILTER,The Remote Wakeup Filter registers are implemented as 8. 16. or 32 indirect access registers (wkuppktfilter_reg#i) based on whether 4. 8. or 16 Remote Wakeup Filters are selected in the configuration and accessed by application.." hexmask.long 0x4 0.--31. 1. "WKUPFRMFTR,RWK Packet Filter This field contains the various controls of RWK Packet filter." group.long 0xD0++0xF line.long 0x0 "MAC_LPI_CONTROL_STATUS,The LPI Control and Status Register controls the LPI functions and provides the LPI interrupt status. The status bits are cleared when this register is read." hexmask.long.word 0x0 22.--31. 1. "RESERVED_31_22,Reserved." newline bitfld.long 0x0 21. "LPITCSE,LPI Tx Clock Stop Enable When this bit is set the MAC asserts sbd_tx_clk_gating_ctrl_o signal high after it enters Tx LPI mode to indicate that the Tx clock to MAC can be stopped. When this bit is reset the MAC does not assert.." "LPI Tx Clock Stop is disabled,LPI Tx Clock Stop is enabled" newline bitfld.long 0x0 20. "LPIATE,LPI Timer Enable This bit controls the automatic entry of the MAC Transmitter into and exit out of the LPI state. When LPIATE LPITXA and LPIEN bits are set the MAC Transmitter enters LPI state only when the complete MAC TX data path is IDLE for.." "LPI Timer is disabled,LPI Timer is enabled" newline bitfld.long 0x0 19. "LPITXA,LPI Tx Automate This bit controls the behavior of the MAC when it is entering or coming out of the LPI mode on the Transmit side. This bit is not functional in the EQOS-CORE configurations in which the Tx clock gating is done during the LPI mode." "LPI Tx Automate is disabled,LPI Tx Automate is enabled" newline bitfld.long 0x0 18. "PLSEN,PHY Link Status Enable This bit enables the link status received on the RGMII Receive paths to be used for activating the LPI LS TIMER. When this bit is set the MAC uses the link-status bits of the MAC_PHYIF_Control_Status register and the PLS bit.." "PHY Link Status is disabled,PHY Link Status is enabled" newline bitfld.long 0x0 17. "PLS,PHY Link Status This bit indicates the link status of the PHY. The MAC Transmitter asserts the LPI pattern only when the link status is up (OKAY) at least for the time indicated by the LPI LS TIMER. When this bit is set the link is considered to be.." "link is down,link is okay" newline bitfld.long 0x0 16. "LPIEN,LPI Enable When this bit is set it instructs the MAC Transmitter to enter the LPI state. When this bit is reset it instructs the MAC to exit the LPI state and resume normal transmission. This bit is cleared when the LPITXA bit is set and the MAC.." "LPI state is disabled,LPI state is enabled" newline hexmask.long.byte 0x0 10.--15. 1. "RESERVED_15_10,Reserved." newline rbitfld.long 0x0 9. "RLPIST,Receive LPI State When this bit is set it indicates that the MAC is receiving the LPI pattern on the GMII or MII interface. 0x1: Receive LPI state detected 0x0: Receive LPI state not detected" "Receive LPI state not detected,Receive LPI state detected" newline rbitfld.long 0x0 8. "TLPIST,Transmit LPI State When this bit is set it indicates that the MAC is transmitting the LPI pattern on the GMII or MII interface. 0x1: Transmit LPI state detected 0x0: Transmit LPI state not detected" "Transmit LPI state not detected,Transmit LPI state detected" newline hexmask.long.byte 0x0 4.--7. 1. "RESERVED_7_4,Reserved." newline rbitfld.long 0x0 3. "RLPIEX,Receive LPI Exit When this bit is set it indicates that the MAC Receiver has stopped receiving the LPI pattern on the GMII or MII interface exited the LPI state and resumed the normal reception. This bit is cleared by a read into this register.." "Receive LPI exit not detected,Receive LPI exit detected" newline rbitfld.long 0x0 2. "RLPIEN,Receive LPI Entry When this bit is set it indicates that the MAC Receiver has received an LPI pattern and entered the LPI state. This bit is cleared by a read into this register (or this bit is written to 1 when RCWE bit in MAC_CSR_SW_Ctrl.." "Receive LPI entry not detected,Receive LPI entry detected" newline rbitfld.long 0x0 1. "TLPIEX,Transmit LPI Exit When this bit is set it indicates that the MAC transmitter exited the LPI state after the application cleared the LPIEN bit and the LPI TW Timer has expired. This bit is cleared by a read into this register (or this bit is.." "Transmit LPI exit not detected,Transmit LPI exit detected" newline rbitfld.long 0x0 0. "TLPIEN,Transmit LPI Entry When this bit is set it indicates that the MAC Transmitter has entered the LPI state because of the setting of the LPIEN bit. This bit is cleared by a read into this register (or this bit is written to 1 when RCWE bit in.." "Transmit LPI entry not detected,Transmit LPI entry detected" line.long 0x4 "MAC_LPI_TIMERS_CONTROL,The LPI Timers Control register controls the timeout values in the LPI states. It specifies the time for which the MAC transmits the LPI pattern and also the time for which the MAC waits before resuming the normal transmission." hexmask.long.byte 0x4 26.--31. 1. "RESERVED_31_26,Reserved." newline hexmask.long.word 0x4 16.--25. 1. "LST,LPI LS Timer This field specifies the minimum time (in milliseconds) for which the link status from the PHY should be up (OKAY) before the LPI pattern can be transmitted to the PHY. The MAC does not transmit the LPI pattern even when the LPIEN bit is.." newline hexmask.long.word 0x4 0.--15. 1. "TWT,LPI TW Timer This field specifies the minimum time (in microseconds) for which the MAC waits after it stops transmitting the LPI pattern to the PHY and before it resumes the normal transmission. The TLPIEX status bit is set after the expiry of this.." line.long 0x8 "MAC_LPI_ENTRY_TIMER,This register controls the Tx LPI entry timer. This counter is enabled only when bit[20](LPITE) bit of MAC_LPI_Control_Status is set to 1." hexmask.long.word 0x8 20.--31. 1. "RESERVED_31_20,Reserved." newline hexmask.long.tbyte 0x8 3.--19. 1. "LPIET,LPI Entry Timer This field specifies the time in microseconds the MAC waits to enter LPI mode after it has transmitted all the frames. This field is valid and used only when LPITE and LPITXA are set to 1. Bits [2:0] are read-only so that the.." newline rbitfld.long 0x8 0.--2. "RESERVED_2_0,Reserved." "0,1,2,3,4,5,6,7" line.long 0xC "MAC_1US_TIC_COUNTER,This register controls the generation of the Reference time (1 microsecond tic) for all the LPI timers. This timer has to be programmed by the software initially." hexmask.long.tbyte 0xC 12.--31. 1. "RESERVED_31_12,Reserved." newline hexmask.long.word 0xC 0.--11. 1. "TIC_1US_CNTR,1US TIC Counter The application must program this counter so that the number of clock cycles of CSR clock is 1us. (Subtract 1 from the value before programming). For example if the CSR clock is 100MHz then this field needs to be programmed.." group.long 0xF8++0x3 line.long 0x0 "MAC_PHYIF_CONTROL_STATUS,The PHY Interface Control and Status register indicates the status signals received by the SGMII. RGMII. or SMII interface (selected at reset) from the PHY. This register is optional." hexmask.long.word 0x0 22.--31. 1. "RESERVED_31_22,Reserved." newline rbitfld.long 0x0 21. "RESERVED_FALSCARDET,Reserved." "0,1" newline rbitfld.long 0x0 20. "RESERVED_JABTO,Reserved." "0,1" newline rbitfld.long 0x0 19. "LNKSTS,Link Status This bit indicates whether the link is up (1'b1) or down (1'b0). 0x1: Link up 0x0: Link down" "Link down,Link up" newline rbitfld.long 0x0 17.--18. "LNKSPEED,Link Speed This bit indicates the current speed of the link. 0x2: 125 MHz 0x0: 2.5 MHz 0x1: 25 MHz 0x3: Reserved" "?,?,?,Reserved" newline rbitfld.long 0x0 16. "LNKMOD,Link Mode This bit indicates the current mode of operation of the link. 0x1: Full-duplex mode 0x0: Half-duplex mode" "Half-duplex mode,Full-duplex mode" newline hexmask.long.word 0x0 5.--15. 1. "RESERVED_15_5,Reserved." newline rbitfld.long 0x0 4. "RESERVED_SMIDRXS,Reserved." "0,1" newline rbitfld.long 0x0 3. "RESERVED_3,Reserved." "0,1" newline rbitfld.long 0x0 2. "RESERVED_SFTERR,Reserved." "0,1" newline bitfld.long 0x0 1. "LUD,Link Up or Down This bit indicates whether the link is up or down during transmission of configuration in the RGMII interface. 0x0: Link down 0x1: Link up" "Link down,Link up" newline bitfld.long 0x0 0. "TC,Transmit Configuration in RGMII. When set this bit enables the transmission of duplex mode link speed and link up or down information to the PHY in the RGMII port. When this bit is reset no such information is driven to the PHY. The details of.." "Disable Transmit Configuration in RGMII,Enable Transmit Configuration in RGMII" rgroup.long 0x110++0x7 line.long 0x0 "MAC_VERSION,The version register identifies the version of the DWC_ether_qos. This register contains two bytes: one that Synopsys uses to identify the core release number. and the other that you set while configuring the core." hexmask.long.word 0x0 16.--31. 1. "RESERVED_31_16,Reserved." newline hexmask.long.byte 0x0 8.--15. 1. "USERVER,User-defined Version (configured with coreConsultant)" newline hexmask.long.byte 0x0 0.--7. 1. "SNPSVER,Synopsys-defined Version" line.long 0x4 "MAC_DEBUG,The Debug register provides the debug status of various MAC blocks." hexmask.long.word 0x4 19.--31. 1. "RESERVED_31_19,Reserved." newline bitfld.long 0x4 17.--18. "TFCSTS,MAC Transmit Packet Controller Status This field indicates the state of the MAC Transmit Packet Controller module. 0x2: Generating and transmitting a Pause control packet (in full-duplex mode) 0x0: Idle state 0x3: Transferring input packet for.." "Idle state,Waiting for one of the following: Status of the..,Generating and transmitting a Pause control..,Transferring input packet for transmission" newline bitfld.long 0x4 16. "TPESTS,MAC GMII or MII Transmit Protocol Engine Status When this bit is set it indicates that the MAC GMII or MII transmit protocol engine is actively transmitting data and it is not in the Idle state. 0x1: MAC GMII or MII Transmit Protocol Engine.." "MAC GMII or MII Transmit Protocol Engine Status..,MAC GMII or MII Transmit Protocol Engine Status.." newline hexmask.long.word 0x4 3.--15. 1. "RESERVED_15_3,Reserved." newline bitfld.long 0x4 1.--2. "RFCFCSTS,MAC Receive Packet Controller FIFO Status When this bit is set this field indicates the active state of the small FIFO Read and Write controllers of the MAC Receive Packet Controller module." "0,1,2,3" newline bitfld.long 0x4 0. "RPESTS,MAC GMII or MII Receive Protocol Engine Status When this bit is set it indicates that the MAC GMII or MII receive protocol engine is actively receiving data and it is not in the Idle state. 0x1: MAC GMII or MII Receive Protocol Engine Status.." "MAC GMII or MII Receive Protocol Engine Status..,MAC GMII or MII Receive Protocol Engine Status.." rgroup.long 0x11C++0xF line.long 0x0 "MAC_HW_FEATURE0,This register indicates the presence of first set of the optional features or functions of the DWC_ether_qos. The software driver can use this register to dynamically enable or disable the programs related to the optional blocks. Note:.." bitfld.long 0x0 31. "RESERVED_31,Reserved." "0,1" newline bitfld.long 0x0 28.--30. "ACTPHYSEL,Active PHY Selected When you have multiple PHY interfaces in your configuration this field indicates the sampled value of phy_intf_sel_i during reset de-assertion. 0x0: Reserved 0x7: Reserved 0x1: RGMII 0x4: RMII 0x5: Reserved 0x2: Reserved.." "Reserved,RGMII,Reserved,Reserved,RMII,Reserved,Reserved,Reserved" newline bitfld.long 0x0 27. "SAVLANINS,Source Address or VLAN Insertion Enable This bit is set to 1 when the Enable SA and VLAN Insertion on Tx option is selected 0x1: Source Address or VLAN Insertion Enable option is selected 0x0: Source Address or VLAN Insertion Enable option is.." "Source Address or VLAN Insertion Enable option..,Source Address or VLAN Insertion Enable option.." newline bitfld.long 0x0 25.--26. "TSSTSSEL,Timestamp System Time Source This bit indicates the source of the Timestamp system time: This bit is set to 1 when the Enable IEEE 1588 Timestamp Support option is selected 0x2: Both 0x1: External 0x0: Internal 0x3: Reserved" "Internal,External,Both,Reserved" newline bitfld.long 0x0 24. "MACADR64SEL,MAC Addresses 64-127 Selected This bit is set to 1 when the Enable Additional 64 MAC Address Registers (64-127) option is selected 0x1: MAC Addresses 64-127 Select option is selected 0x0: MAC Addresses 64-127 Select option is not selected" "MAC Addresses 64-127 Select option is not selected,MAC Addresses 64-127 Select option is selected" newline bitfld.long 0x0 23. "MACADR32SEL,MAC Addresses 32-63 Selected This bit is set to 1 when the Enable Additional 32 MAC Address Registers (32-63) option is selected 0x1: MAC Addresses 32-63 Select option is selected 0x0: MAC Addresses 32-63 Select option is not selected" "MAC Addresses 32-63 Select option is not selected,MAC Addresses 32-63 Select option is selected" newline hexmask.long.byte 0x0 18.--22. 1. "ADDMACADRSEL,MAC Addresses 1-31 Selected This bit is set to 1 when the non-zero value is selected for Enable Additional 1-31 MAC Address Registers option" newline bitfld.long 0x0 17. "RESERVED_17,Reserved." "0,1" newline bitfld.long 0x0 16. "RXCOESEL,Receive Checksum Offload Enabled This bit is set to 1 when the Enable Receive TCP/IP Checksum Check option is selected 0x1: Receive Checksum Offload Enable option is selected 0x0: Receive Checksum Offload Enable option is not selected" "Receive Checksum Offload Enable option is not..,Receive Checksum Offload Enable option is selected" newline bitfld.long 0x0 15. "RESERVED_15,Reserved." "0,1" newline bitfld.long 0x0 14. "TXCOESEL,Transmit Checksum Offload Enabled This bit is set to 1 when the Enable Transmit TCP/IP Checksum Insertion option is selected 0x1: Transmit Checksum Offload Enable option is selected 0x0: Transmit Checksum Offload Enable option is not selected" "Transmit Checksum Offload Enable option is not..,Transmit Checksum Offload Enable option is.." newline bitfld.long 0x0 13. "EEESEL,Energy Efficient Ethernet Enabled This bit is set to 1 when the Enable Energy Efficient Ethernet (EEE) option is selected 0x1: Energy Efficient Ethernet Enable option is selected 0x0: Energy Efficient Ethernet Enable option is not selected" "Energy Efficient Ethernet Enable option is not..,Energy Efficient Ethernet Enable option is.." newline bitfld.long 0x0 12. "TSSEL,IEEE 1588-2008 Timestamp Enabled This bit is set to 1 when the Enable IEEE 1588 Timestamp Support option is selected 0x1: IEEE 1588-2008 Timestamp Enable option is selected 0x0: IEEE 1588-2008 Timestamp Enable option is not selected" "IEEE 1588-2008 Timestamp Enable option is not..,IEEE 1588-2008 Timestamp Enable option is selected" newline bitfld.long 0x0 10.--11. "RESERVED_11_10,Reserved." "0,1,2,3" newline bitfld.long 0x0 9. "ARPOFFSEL,ARP Offload Enabled This bit is set to 1 when the Enable IPv4 ARP Offload option is selected 0x1: ARP Offload Enable option is selected 0x0: ARP Offload Enable option is not selected" "ARP Offload Enable option is not selected,ARP Offload Enable option is selected" newline bitfld.long 0x0 8. "MMCSEL,RMON Module Enable This bit is set to 1 when the Enable MAC Management Counters (MMC) option is selected 0x1: RMON Module Enable option is selected 0x0: RMON Module Enable option is not selected" "RMON Module Enable option is not selected,RMON Module Enable option is selected" newline bitfld.long 0x0 7. "MGKSEL,PMT Magic Packet Enable This bit is set to 1 when the Enable Magic Packet Detection option is selected 0x1: PMT Magic Packet Enable option is selected 0x0: PMT Magic Packet Enable option is not selected" "PMT Magic Packet Enable option is not selected,PMT Magic Packet Enable option is selected" newline bitfld.long 0x0 6. "RWKSEL,PMT Remote Wake-up Packet Enable This bit is set to 1 when the Enable Remote Wake-Up Packet Detection option is selected 0x1: PMT Remote Wake-up Packet Enable option is selected 0x0: PMT Remote Wake-up Packet Enable option is not selected" "PMT Remote Wake-up Packet Enable option is not..,PMT Remote Wake-up Packet Enable option is.." newline bitfld.long 0x0 5. "SMASEL,SMA (MDIO) Interface This bit is set to 1 when the Enable Station Management (MDIO Interface) option is selected 0x1: SMA (MDIO) Interface selected 0x0: SMA (MDIO) Interface not selected" "SMA,SMA" newline bitfld.long 0x0 4. "VLHASH,VLAN Hash Filter Selected This bit is set to 1 when the Enable VLAN Hash Table Based Filtering option is selected 0x1: VLAN Hash Filter selected 0x0: VLAN Hash Filter not selected" "VLAN Hash Filter not selected,VLAN Hash Filter selected" newline bitfld.long 0x0 3. "PCSSEL,Reserved" "0,1" newline bitfld.long 0x0 2. "HDSEL,Half-duplex Support This bit is set to 1 when the half-duplex mode is selected 0x1: Half-duplex support 0x0: No Half-duplex support" "No Half-duplex support,Half-duplex support" newline bitfld.long 0x0 1. "GMIISEL,1000 Mbps Support This bit is set to 1 when 1000 Mbps is selected as the Mode of Operation 0x1: 1000 Mbps support 0x0: No 1000 Mbps support" "No 1000 Mbps support,?" newline bitfld.long 0x0 0. "MIISEL,10 or 100 Mbps Support This bit is set to 1 when 10/100 Mbps is selected as the Mode of Operation 0x1: 10 or 100 Mbps support 0x0: No 10 or 100 Mbps support" "No 10 or 100 Mbps support,?" line.long 0x4 "MAC_HW_FEATURE1,This register indicates the presence of second set of the optional features or functions of the DWC_ether_qos. The software driver can use this register to dynamically enable or disable the programs related to the optional blocks. Note:.." bitfld.long 0x4 31. "RESERVED_31,Reserved." "0,1" newline hexmask.long.byte 0x4 27.--30. 1. "L3L4FNUM,Total number of L3 or L4 Filters This field indicates the total number of L3 or L4 filters: 0x1: 1 L3 or L4 Filter 0x2: 2 L3 or L4 Filters 0x3: 3 L3 or L4 Filters 0x4: 4 L3 or L4 Filters 0x5: 5 L3 or L4 Filters 0x6: 6 L3 or L4 Filters 0x7: 7 L3.." newline bitfld.long 0x4 26. "RESERVED_26,Reserved." "0,1" newline bitfld.long 0x4 24.--25. "HASHTBLSZ,Hash Table Size This field indicates the size of the hash table: 0x2: 128 0x3: 256 0x1: 64 0x0: No hash table" "No hash table,?,?,?" newline bitfld.long 0x4 23. "POUOST,One Step for PTP over UDP/IP Feature Enable This bit is set to 1 when the Enable One step timestamp for PTP over UDP/IP feature is selected. 0x1: One Step for PTP over UDP/IP Feature is selected 0x0: One Step for PTP over UDP/IP Feature is not.." "One Step for PTP over UDP/IP Feature is not..,One Step for PTP over UDP/IP Feature is selected" newline bitfld.long 0x4 22. "RESERVED_22,Reserved." "0,1" newline bitfld.long 0x4 21. "RAVSEL,Rx Side Only AV Feature Enable This bit is set to 1 when the Enable Audio Video Bridging option on Rx Side Only is selected. 0x1: Rx Side Only AV Feature is selected 0x0: Rx Side Only AV Feature is not selected" "Rx Side Only AV Feature is not selected,Rx Side Only AV Feature is selected" newline bitfld.long 0x4 20. "AVSEL,AV Feature Enable This bit is set to 1 when the Enable Audio Video Bridging option is selected. 0x1: AV Feature is selected 0x0: AV Feature is not selected" "AV Feature is not selected,AV Feature is selected" newline bitfld.long 0x4 19. "DBGMEMA,DMA Debug Registers Enable This bit is set to 1 when the Debug Mode Enable option is selected 0x1: DMA Debug Registers option is selected 0x0: DMA Debug Registers option is not selected" "DMA Debug Registers option is not selected,DMA Debug Registers option is selected" newline bitfld.long 0x4 18. "TSOEN,TCP Segmentation Offload Enable This bit is set to 1 when the Enable TCP Segmentation Offloading for TCP/IP Packets option is selected 0x1: TCP Segmentation Offload Feature is selected 0x0: TCP Segmentation Offload Feature is not selected" "TCP Segmentation Offload Feature is not selected,TCP Segmentation Offload Feature is selected" newline bitfld.long 0x4 17. "SPHEN,Split Header Feature Enable This bit is set to 1 when the Enable Split Header Structure option is selected 0x1: Split Header Feature is selected 0x0: Split Header Feature is not selected" "Split Header Feature is not selected,Split Header Feature is selected" newline bitfld.long 0x4 16. "DCBEN,DCB Feature Enable This bit is set to 1 when the Enable Data Center Bridging option is selected 0x1: DCB Feature is selected 0x0: DCB Feature is not selected" "DCB Feature is not selected,DCB Feature is selected" newline bitfld.long 0x4 14.--15. "ADDR64,Address Width. This field indicates the configured address width: 0x0: 32 0x1: 40 0x2: 48 0x3: Reserved" "?,?,?,Reserved" newline bitfld.long 0x4 13. "ADVTHWORD,IEEE 1588 High Word Register Enable This bit is set to 1 when the Add IEEE 1588 Higher Word Register option is selected 0x1: IEEE 1588 High Word Register option is selected 0x0: IEEE 1588 High Word Register option is not selected" "IEEE 1588 High Word Register option is not..,IEEE 1588 High Word Register option is selected" newline bitfld.long 0x4 12. "PTOEN,PTP Offload Enable This bit is set to 1 when the Enable PTP Timestamp Offload Feature is selected. 0x1: PTP Offload feature is selected 0x0: PTP Offload feature is not selected" "PTP Offload feature is not selected,PTP Offload feature is selected" newline bitfld.long 0x4 11. "OSTEN,One-Step Timestamping Enable This bit is set to 1 when the Enable One-Step Timestamp Feature is selected. 0x1: One-Step Timestamping feature is selected 0x0: One-Step Timestamping feature is not selected" "One-Step Timestamping feature is not selected,One-Step Timestamping feature is selected" newline hexmask.long.byte 0x4 6.--10. 1. "TXFIFOSIZE,MTL Transmit FIFO Size This field contains the configured value of MTL Tx FIFO in bytes expressed as Log to base 2 minus 7 that is Log2(TXFIFO_SIZE) -7: 0x3: 1024 bytes 0x0: 128 bytes 0xa: 128 KB 0x7: 16384 bytes 0x4: 2048 bytes 0x1: 256.." newline bitfld.long 0x4 5. "SPRAM,Single Port RAM Enable This bit is set to 1 when the Use single port RAM Feature is selected. 0x1: Single Port RAM feature is selected 0x0: Single Port RAM feature is not selected" "Single Port RAM feature is not selected,Single Port RAM feature is selected" newline hexmask.long.byte 0x4 0.--4. 1. "RXFIFOSIZE,MTL Receive FIFO Size This field contains the configured value of MTL Rx FIFO in bytes expressed as Log to base 2 minus 7 that is Log2(RXFIFO_SIZE) -7: 0x3: 1024 bytes 0x0: 128 bytes 0xa: 128 KB 0x7: 16384 bytes 0x4: 2048 bytes 0x1: 256.." line.long 0x8 "MAC_HW_FEATURE2,This register indicates the presence of third set of the optional features or functions of the DWC_ether_qos. The software driver can use this register to dynamically enable or disable the programs related to the optional blocks." bitfld.long 0x8 31. "RESERVED_31,Reserved." "0,1" newline bitfld.long 0x8 28.--30. "AUXSNAPNUM,Number of Auxiliary Snapshot Inputs This field indicates the number of auxiliary snapshot inputs: 0x1: 1 auxiliary input 0x2: 2 auxiliary input 0x3: 3 auxiliary input 0x4: 4 auxiliary input 0x0: No auxiliary input 0x5: Reserved" "No auxiliary input,?,?,?,?,Reserved,?,?" newline bitfld.long 0x8 27. "RESERVED_27,Reserved." "0,1" newline bitfld.long 0x8 24.--26. "PPSOUTNUM,Number of PPS Outputs This field indicates the number of PPS outputs: 0x1: 1 PPS output 0x2: 2 PPS output 0x3: 3 PPS output 0x4: 4 PPS output 0x0: No PPS output 0x5: Reserved" "No PPS output,?,?,?,?,Reserved,?,?" newline bitfld.long 0x8 22.--23. "RESERVED_23_22,Reserved." "0,1,2,3" newline hexmask.long.byte 0x8 18.--21. 1. "TXCHCNT,Number of DMA Transmit Channels This field indicates the number of DMA Transmit channels: 0x0: 1 MTL Tx Channel 0x1: 2 MTL Tx Channels 0x2: 3 MTL Tx Channels 0x3: 4 MTL Tx Channels 0x4: 5 MTL Tx Channels 0x5: 6 MTL Tx Channels 0x6: 7 MTL Tx.." newline bitfld.long 0x8 16.--17. "RESERVED_17_16,Reserved." "0,1,2,3" newline hexmask.long.byte 0x8 12.--15. 1. "RXCHCNT,Number of DMA Receive Channels This field indicates the number of DMA Receive channels: 0x0: 1 MTL Rx Channel 0x1: 2 MTL Rx Channels 0x2: 3 MTL Rx Channels 0x3: 4 MTL Rx Channels 0x4: 5 MTL Rx Channels 0x5: 6 MTL Rx Channels 0x6: 7 MTL Rx.." newline bitfld.long 0x8 10.--11. "RESERVED_11_10,Reserved." "0,1,2,3" newline hexmask.long.byte 0x8 6.--9. 1. "TXQCNT,Number of MTL Transmit Queues This field indicates the number of MTL Transmit queues: 0x0: 1 MTL Tx Queue 0x1: 2 MTL Tx Queues 0x2: 3 MTL Tx Queues 0x3: 4 MTL Tx Queues 0x4: 5 MTL Tx Queues 0x5: 6 MTL Tx Queues 0x6: 7 MTL Tx Queues 0x7: 8 MTL Tx.." newline bitfld.long 0x8 4.--5. "RESERVED_5_4,Reserved." "0,1,2,3" newline hexmask.long.byte 0x8 0.--3. 1. "RXQCNT,Number of MTL Receive Queues This field indicates the number of MTL Receive queues: 0x0: 1 MTL Rx Queue 0x1: 2 MTL Rx Queues 0x2: 3 MTL Rx Queues 0x3: 4 MTL Rx Queues 0x4: 5 MTL Rx Queues 0x5: 6 MTL Rx Queues 0x6: 7 MTL Rx Queues 0x7: 8 MTL Rx.." line.long 0xC "MAC_HW_FEATURE3,This register indicates the presence of fourth set the optional features or functions of the DWC_ether_qos. The software driver can use this register to dynamically enable or disable the programs related to the optional blocks." bitfld.long 0xC 30.--31. "RESERVED_31_30,Reserved." "0,1,2,3" newline bitfld.long 0xC 28.--29. "ASP,Automotive Safety Package Following are the encoding for the different Safety features 0x2: All the Automotive Safety features are selected without the 'Parity Port Enable for external interface' feature 0x3: All the Automotive Safety features are.." "No Safety features selected,Only 'ECC protection for external memory'..,All the Automotive Safety features are selected..,All the Automotive Safety features are selected.." newline bitfld.long 0xC 27. "TBSSEL,Time Based Scheduling Enable This bit is set to 1 when the Time Based Scheduling feature is selected. 0x1: Time Based Scheduling Enable feature is selected 0x0: Time Based Scheduling Enable feature is not selected" "Time Based Scheduling Enable feature is not..,Time Based Scheduling Enable feature is selected" newline bitfld.long 0xC 26. "FPESEL,Frame Preemption Enable This bit is set to 1 when the Enable Frame preemption feature is selected. 0x1: Frame Preemption Enable feature is selected 0x0: Frame Preemption Enable feature is not selected" "Frame Preemption Enable feature is not selected,Frame Preemption Enable feature is selected" newline hexmask.long.byte 0xC 22.--25. 1. "RESERVED_25_22,Reserved." newline bitfld.long 0xC 20.--21. "ESTWID,Width of the Time Interval field in the Gate Control List This field indicates the width of the Configured Time Interval Field 0x0: Width not configured 0x1: 16 0x2: 20 0x3: 24" "Width not configured,?,?,?" newline bitfld.long 0xC 17.--19. "ESTDEP,Depth of the Gate Control List This field indicates the depth of Gate Control list expressed as Log2(DWC_EQOS_EST_DEP)-5 0x5: 1024 0x2: 128 0x3: 256 0x4: 512 0x1: 64 0x0: No Depth configured 0x6: Reserved" "No Depth configured,?,?,?,?,?,Reserved,?" newline bitfld.long 0xC 16. "ESTSEL,Enhancements to Scheduling Traffic Enable This bit is set to 1 when the Enable Enhancements to Scheduling Traffic feature is selected. 0x1: Enable Enhancements to Scheduling Traffic feature is selected 0x0: Enable Enhancements to Scheduling.." "Enable Enhancements to Scheduling Traffic..,Enable Enhancements to Scheduling Traffic.." newline bitfld.long 0xC 15. "RESERVED_15,Reserved." "0,1" newline bitfld.long 0xC 13.--14. "FRPES,Flexible Receive Parser Table Entries size This field indicates the Max Number of Parser Entries supported by Flexible Receive Parser. 0x1: 128 Entries 0x2: 256 Entries 0x0: 64 Entries 0x3: Reserved" "?,?,?,Reserved" newline bitfld.long 0xC 11.--12. "FRPBS,Flexible Receive Parser Buffer size This field indicates the supported Max Number of bytes of the packet data to be Parsed by Flexible Receive Parser. 0x1: 128 Bytes 0x2: 256 Bytes 0x0: 64 Bytes 0x3: Reserved" "?,?,?,Reserved" newline bitfld.long 0xC 10. "FRPSEL,Flexible Receive Parser Selected This bit is set to 1 when the Enable Flexible Programmable Receive Parser option is selected. 0x1: Flexible Receive Parser feature is selected 0x0: Flexible Receive Parser feature is not selected" "Flexible Receive Parser feature is not selected,Flexible Receive Parser feature is selected" newline bitfld.long 0xC 9. "PDUPSEL,Broadcast/Multicast Packet Duplication This bit is set to 1 when the Broadcast/Multicast Packet Duplication feature is selected. 0x1: Broadcast/Multicast Packet Duplication feature is selected 0x0: Broadcast/Multicast Packet Duplication feature.." "Broadcast/Multicast Packet Duplication feature..,Broadcast/Multicast Packet Duplication feature.." newline bitfld.long 0xC 6.--8. "RESERVED_7_6,Reserved." "0,1,2,3,4,5,6,7" newline bitfld.long 0xC 5. "DVLAN,Double VLAN Tag Processing Selected This bit is set to 1 when the Enable Double VLAN Processing Feature is selected. 0x1: Double VLAN option is selected 0x0: Double VLAN option is not selected" "Double VLAN option is not selected,Double VLAN option is selected" newline bitfld.long 0xC 4. "CBTISEL,Queue/Channel based VLAN tag insertion on Tx Enable This bit is set to 1 when the Enable Queue/Channel based VLAN tag insertion on Tx Feature is selected. 0x1: Enable Queue/Channel based VLAN tag insertion on Tx feature is selected 0x0: Enable.." "Enable Queue/Channel based VLAN tag insertion on..,Enable Queue/Channel based VLAN tag insertion on.." newline bitfld.long 0xC 3. "RESERVED_3,Reserved." "0,1" newline bitfld.long 0xC 0.--2. "NRVF,Number of Extended VLAN Tag Filters Enabled This field indicates the Number of Extended VLAN Tag Filters selected: 0x3: 16 Extended Rx VLAN Filters 0x4: 24 Extended Rx VLAN Filters 0x5: 32 Extended Rx VLAN Filters 0x1: 4 Extended Rx VLAN Filters.." "No Extended Rx VLAN Filters,?,?,?,?,?,Reserved,?" group.long 0x140++0x3 line.long 0x0 "MAC_DPP_FSM_INTERRUPT_STATUS,This register contains the status of Automotive Safety related Data Path Parity Errors. Interface Timeout Errors. FSM State Parity Errors and FSM State Timeout Errors." hexmask.long.byte 0x0 25.--31. 1. "RESERVED_31_25,Reserved." newline bitfld.long 0x0 24. "FSMPES,FSM State Parity Error Status This field when set indicates one of the FSMs State registers has a parity error detected. 0x1: FSM State Parity Error Status detected 0x0: FSM State Parity Error Status not detected" "FSM State Parity Error Status not detected,FSM State Parity Error Status detected" newline hexmask.long.byte 0x0 18.--23. 1. "RESERVED_23_18,Reserved." newline rbitfld.long 0x0 17. "RESERVED_SLVTES,Reserved." "0,1" newline bitfld.long 0x0 16. "MSTTES,Master Read/Write Timeout Error Status This field when set indicates that an Application/CSR Timeout has occurred on the master (AXI/AHB/ARI/ATI) interface. 0x1: Master Read/Write Timeout Error Status detected 0x0: Master Read/Write Timeout Error.." "Master Read/Write Timeout Error Status not..,Master Read/Write Timeout Error Status detected" newline rbitfld.long 0x0 15. "RESERVED_RVCTES,Reserved." "0,1" newline rbitfld.long 0x0 14. "RESERVED_R125ES,Reserved." "0,1" newline rbitfld.long 0x0 13. "RESERVED_T125ES,Reserved." "0,1" newline bitfld.long 0x0 12. "PTES,PTP FSM Timeout Error Status This field when set indicates that one of the PTP FSM Timeout has occurred. 0x1: PTP FSM Timeout Error Status detected 0x0: PTP FSM Timeout Error Status not detected" "PTP FSM Timeout Error Status not detected,PTP FSM Timeout Error Status detected" newline bitfld.long 0x0 11. "ATES,APP FSM Timeout Error Status This field when set indicates that one of the APP FSM Timeout has occurred. 0x1: APP FSM Timeout Error Status detected 0x0: APP FSM Timeout Error Status not detected" "APP FSM Timeout Error Status not detected,APP FSM Timeout Error Status detected" newline bitfld.long 0x0 10. "CTES,CSR FSM Timeout Error Status This field when set indicates that one of the CSR FSM Timeout has occurred. 0x1: CSR FSM Timeout Error Status detected 0x0: CSR FSM Timeout Error Status not detected" "CSR FSM Timeout Error Status not detected,CSR FSM Timeout Error Status detected" newline bitfld.long 0x0 9. "RTES,Rx FSM Timeout Error Status This field when set indicates that one of the Rx FSM Timeout has occurred. 0x1: Rx FSM Timeout Error Status detected 0x0: Rx FSM Timeout Error Status not detected" "Rx FSM Timeout Error Status not detected,Rx FSM Timeout Error Status detected" newline bitfld.long 0x0 8. "TTES,Tx FSM Timeout Error Status This field when set indicates that one of the Tx FSM Timeout has occurred. 0x1: Tx FSM Timeout Error Status detected 0x0: Tx FSM Timeout Error Status not detected" "Tx FSM Timeout Error Status not detected,Tx FSM Timeout Error Status detected" newline rbitfld.long 0x0 7. "RESERVED_ASRPES,Reserved." "0,1" newline rbitfld.long 0x0 6. "RESERVED_CWPES,Reserved." "0,1" newline bitfld.long 0x0 5. "ARPES,Application Receive interface data path Parity Error Status This bit when set indicates that a parity error is detected at following checkers based on the system configuration as described below - In MTL configuration (DWC_EQOS_SYS=1) parity.." "Application Receive interface data path Parity..,Application Receive interface data path Parity.." newline bitfld.long 0x0 4. "MTSPES,MTL TX Status data path Parity checker Error Status This filed when set indicates that parity error is detected on the MTL TX Status data on ati interface (or at PC5 as shown in Fig.Transmit data path parity protection). 0x1: MTL TX Status data.." "MTL TX Status data path Parity checker Error..,MTL TX Status data path Parity checker Error.." newline bitfld.long 0x0 3. "MPES,MTL data path Parity checker Error Status This bit when set indicates that a parity error is detected at the MTL transmit write controller parity checker (or at PC4 as shown in Fig.Transmit data path parity protection). 0x1: MTL data path Parity.." "MTL data path Parity checker Error Status not..,MTL data path Parity checker Error Status detected" newline bitfld.long 0x0 2. "RDPES,Read Descriptor Parity checker Error Status This bit when set indicates that a parity error is detected at the DMA Read descriptor parity checker (or at PC3 as shown in Fig.Transmit data path parity protection). 0x1: Read Descriptor Parity checker.." "Read Descriptor Parity checker Error Status not..,Read Descriptor Parity checker Error Status.." newline rbitfld.long 0x0 1. "RESERVED_TPES,Reserved." "0,1" newline bitfld.long 0x0 0. "ATPES,Application Transmit Interface Parity checker Error Status This bit when set indicates that a parity error is detected on the AXI/AHB Master read data parity checker. This bit when set indicates that a parity error is detected on the interface port.." "Application Transmit Interface Parity checker..,Application Transmit Interface Parity checker.." group.long 0x148++0xB line.long 0x0 "MAC_FSM_CONTROL,This register is used to control the FSM State parity and timeout error injection in Debug mode." rbitfld.long 0x0 31. "RESERVED_RVCLGRNML,Reserved." "0,1" newline rbitfld.long 0x0 30. "RESERVED_R125LGRNML,Reserved." "0,1" newline rbitfld.long 0x0 29. "RESERVED_T125LGRNML,Reserved." "0,1" newline bitfld.long 0x0 28. "PLGRNML,PTP Large/Normal Mode Select This field when set indicates that large mode tic generation is used for PTP domain else normal mode tic generation is used. 0x0: normal mode tic generation is used for PTP domain 0x1: large mode tic generation is.." "normal mode tic generation is used for PTP domain,large mode tic generation is used for PTP domain" newline bitfld.long 0x0 27. "ALGRNML,APP Large/Normal Mode Select This field when set indicates that large mode tic generation is used for APP domain else normal mode tic generation is used. 0x0: normal mode tic generation is used for APP domain 0x1: large mode tic generation is.." "normal mode tic generation is used for APP domain,large mode tic generation is used for APP domain" newline bitfld.long 0x0 26. "CLGRNML,CSR Large/Normal Mode Select This field when set indicates that large mode tic generation is used for CSR domain else normal mode tic generation is used. 0x0: normal mode tic generation is used for CSR domain 0x1: large mode tic generation is.." "normal mode tic generation is used for CSR domain,large mode tic generation is used for CSR domain" newline bitfld.long 0x0 25. "RLGRNML,Rx Large/Normal Mode Select This field when set indicates that large mode tic generation is used for Rx domain else normal mode tic generation is used. 0x0: normal mode tic generation is used for Rx domain 0x1: large mode tic generation is used.." "normal mode tic generation is used for Rx domain,large mode tic generation is used for Rx domain" newline bitfld.long 0x0 24. "TLGRNML,Tx Large/Normal Mode Select This field when set indicates that large mode tic generation is used for Tx domain else normal mode tic generation is used. 0x0: normal mode tic generation is used for Tx domain 0x1: large mode tic generation is used.." "normal mode tic generation is used for Tx domain,large mode tic generation is used for Tx domain" newline rbitfld.long 0x0 23. "RESERVED_RVCPEIN,Reserved." "0,1" newline rbitfld.long 0x0 22. "RESERVED_R125PEIN,Reserved." "0,1" newline rbitfld.long 0x0 21. "RESERVED_T125PEIN,Reserved." "0,1" newline bitfld.long 0x0 20. "PPEIN,PTP FSM Parity Error Injection This field when set indicates that Error Injection for PTP FSM Parity is enabled. 0x0: PTP FSM Parity Error Injection is disabled 0x1: PTP FSM Parity Error Injection is enabled" "PTP FSM Parity Error Injection is disabled,PTP FSM Parity Error Injection is enabled" newline bitfld.long 0x0 19. "APEIN,APP FSM Parity Error Injection This field when set indicates that Error Injection for APP FSM Parity is enabled. 0x0: APP FSM Parity Error Injection is disabled 0x1: APP FSM Parity Error Injection is enabled" "APP FSM Parity Error Injection is disabled,APP FSM Parity Error Injection is enabled" newline bitfld.long 0x0 18. "CPEIN,CSR FSM Parity Error Injection This field when set indicates that Error Injection for CSR Parity is enabled. 0x0: CSR FSM Parity Error Injection is disabled 0x1: CSR FSM Parity Error Injection is enabled" "CSR FSM Parity Error Injection is disabled,CSR FSM Parity Error Injection is enabled" newline bitfld.long 0x0 17. "RPEIN,Rx FSM Parity Error Injection This field when set indicates that Error Injection for RX FSM Parity is enabled. 0x0: Rx FSM Parity Error Injection is disabled 0x1: Rx FSM Parity Error Injection is enabled" "Rx FSM Parity Error Injection is disabled,Rx FSM Parity Error Injection is enabled" newline bitfld.long 0x0 16. "TPEIN,Tx FSM Parity Error Injection This field when set indicates that Error Injection for TX FSM Parity is enabled. 0x0: Tx FSM Parity Error Injection is disabled 0x1: Tx FSM Parity Error Injection is enabled" "Tx FSM Parity Error Injection is disabled,Tx FSM Parity Error Injection is enabled" newline rbitfld.long 0x0 15. "RESERVED_RVCTEIN,Reserved." "0,1" newline rbitfld.long 0x0 14. "RESERVED_R125TEIN,Reserved." "0,1" newline rbitfld.long 0x0 13. "RESERVED_T125TEIN,Reserved." "0,1" newline bitfld.long 0x0 12. "PTEIN,PTP FSM Timeout Error Injection This field when set indicates that Error Injection for PTP FSM timeout is enabled. 0x0: PTP FSM Timeout Error Injection is disabled 0x1: PTP FSM Timeout Error Injection is enabled" "PTP FSM Timeout Error Injection is disabled,PTP FSM Timeout Error Injection is enabled" newline bitfld.long 0x0 11. "ATEIN,APP FSM Timeout Error Injection This field when set indicates that Error Injection for APP FSM timeout is enabled. 0x0: APP FSM Timeout Error Injection is disabled 0x1: APP FSM Timeout Error Injection is enabled" "APP FSM Timeout Error Injection is disabled,APP FSM Timeout Error Injection is enabled" newline bitfld.long 0x0 10. "CTEIN,CSR FSM Timeout Error Injection This field when set indicates that Error Injection for CSR timeout is enabled. 0x0: CSR FSM Timeout Error Injection is disabled 0x1: CSR FSM Timeout Error Injection is enabled" "CSR FSM Timeout Error Injection is disabled,CSR FSM Timeout Error Injection is enabled" newline bitfld.long 0x0 9. "RTEIN,Rx FSM Timeout Error Injection This field when set indicates that Error Injection for RX FSM timeout is enabled. 0x0: Rx FSM Timeout Error Injection is disabled 0x1: Rx FSM Timeout Error Injection is enabled" "Rx FSM Timeout Error Injection is disabled,Rx FSM Timeout Error Injection is enabled" newline bitfld.long 0x0 8. "TTEIN,Tx FSM Timeout Error Injection This field when set indicates that Error Injection for TX FSM timeout is enabled. 0x0: Tx FSM Timeout Error Injection is disabled 0x1: Tx FSM Timeout Error Injection is enabled" "Tx FSM Timeout Error Injection is disabled,Tx FSM Timeout Error Injection is enabled" newline hexmask.long.byte 0x0 2.--7. 1. "RESERVED_7_2," newline bitfld.long 0x0 1. "PRTYEN,This bit when set indicates that the FSM parity feature is enabled. 0x0: FSM Parity feature is disabled 0x1: FSM Parity feature is enabled" "FSM Parity feature is disabled,FSM Parity feature is enabled" newline bitfld.long 0x0 0. "TMOUTEN,This bit when set indicates that the FSM timeout feature is enabled. 0x0: FSM timeout feature is disabled 0x1: FSM timeout feature is enabled" "FSM timeout feature is disabled,FSM timeout feature is enabled" line.long 0x4 "MAC_FSM_ACT_TIMER,This register is used to select the FSM and Interface Timeout values." hexmask.long.byte 0x4 24.--31. 1. "RESERVED_31_24,Reserved." newline hexmask.long.byte 0x4 20.--23. 1. "LTMRMD,This field provides the mode value to be used for large mode FSM and other interface time outs. The timeout duration based on the mode value is given below 0x3: 16.384ms (~16ms) 0x8: 16.777sec (~16sec) 0x1: 1us 0x6: 1.048sec (~1sec) 0x5: 262.144ms.." newline hexmask.long.byte 0x4 16.--19. 1. "NTMRMD,This field provides the value to be used for normal mode FSM and other interface time outs. The timeout duration based on the mode value is given below 0x3: 16.384ms (~16ms) 0x8: 16.777sec (~16sec) 0x1: 1us 0x6: 1.048sec (~1sec) 0x5: 262.144ms.." newline hexmask.long.byte 0x4 10.--15. 1. "RESERVED_15_10,Reserved." newline hexmask.long.word 0x4 0.--9. 1. "TMR,This field indicates the number of CSR clocks required to generate 1us tic." line.long 0x8 "SNPS_SCS_REG1,Synopsys Reserved Register" hexmask.long 0x8 0.--31. 1. "MAC_SCS1,Synopsys Reserved All the bits must be set to '0'. This field is reserved for Synopsys Internal use and must always be set to '0' unless instructed by Synopsys. Setting any bit to '1' might cause unexpected behavior in the IP." group.long 0x200++0x7 line.long 0x0 "MAC_MDIO_ADDRESS,The MDIO Address register controls the management cycles to external PHY through a management interface." hexmask.long.byte 0x0 28.--31. 1. "RESERVED_31_28,Reserved." newline bitfld.long 0x0 27. "PSE,Preamble Suppression Enable When this bit is set the SMA suppresses the 32-bit preamble and transmits MDIO frames with only 1 preamble bit. When this bit is 0 the MDIO frame always has 32 bits of preamble as defined in the IEEE specifications. 0x0:.." "Preamble Suppression disabled,Preamble Suppression enabled" newline bitfld.long 0x0 26. "BTB,Back to Back transactions When this bit is set and the NTC has value greater than 0 then the MAC informs the completion of a read or write command at the end of frame transfer (before the trailing clocks are transmitted). The software can thus.." "Back to Back transactions disabled,Back to Back transactions enabled" newline hexmask.long.byte 0x0 21.--25. 1. "PA,Physical Layer Address This field indicates which Clause 22 PHY devices (out of 32 devices) the MAC is accessing. This field indicates which Clause 45 capable PHYs (out of 32 PHYs) the MAC is accessing." newline hexmask.long.byte 0x0 16.--20. 1. "RDA,Register/Device Address These bits select the PHY register in selected Clause 22 PHY device. These bits select the Device (MMD) in selected Clause 45 capable PHY." newline rbitfld.long 0x0 15. "RESERVED_15,Reserved." "0,1" newline bitfld.long 0x0 12.--14. "NTC,Number of Trailing Clocks This field controls the number of trailing clock cycles generated on gmii_mdc_o (MDC) after the end of transmission of MDIO frame. The valid values can be from 0 to 7. Programming the value to 3'h3 indicates that there are.." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x0 8.--11. 1. "CR,CSR Clock Range The CSR Clock Range selection determines the frequency of the MDC clock according to the CSR clock frequency used in your design: - 0000: CSR clock = 60-100 MHz; MDC clock = CSR clock/42 - 0001: CSR clock = 100-150 MHz; MDC clock = CSR.." newline rbitfld.long 0x0 5.--7. "RESERVED_7_5,Reserved." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 4. "SKAP,Skip Address Packet When this bit is set the SMA does not send the address packets before read write or post-read increment address packets. This bit is valid only when C45E is set. 0x0: Skip Address Packet is disabled 0x1: Skip Address Packet is.." "Skip Address Packet is disabled,Skip Address Packet is enabled" newline bitfld.long 0x0 3. "GOC_1,GMII Operation Command 1 This bit is higher bit of the operation command to the PHY GOC_1 and GOC_O is encoded as follows: - 00: Reserved - 01: Write - 10: Post Read Increment Address for Clause 45 PHY - 11: Read When Clause 22 PHY is enabled.." "GMII Operation Command 1 is disabled,GMII Operation Command 1 is enabled" newline bitfld.long 0x0 2. "GOC_0,GMII Operation Command 0 This is the lower bit of the operation command to the PHY. When in SMA mode (MDIO master) this bit along with GOC_1 determines the operation to be performed to the PHY. 0x0: GMII Operation Command 0 is disabled 0x1: GMII.." "GMII Operation Command 0 is disabled,GMII Operation Command 0 is enabled" newline bitfld.long 0x0 1. "C45E,Clause 45 PHY Enable When this bit is set Clause 45 capable PHY is connected to MDIO. When this bit is reset Clause 22 capable PHY is connected to MDIO. 0x0: Clause 45 PHY is disabled 0x1: Clause 45 PHY is enabled" "Clause 45 PHY is disabled,Clause 45 PHY is enabled" newline bitfld.long 0x0 0. "GB,GMII Busy The application sets this bit to instruct the SMA to initiate a Read or Write access to the MDIO slave. The MAC clears this bit after the MDIO frame transfer is completed. Hence the software must not write or change any of the fields in.." "GMII Busy is disabled,GMII Busy is enabled" line.long 0x4 "MAC_MDIO_DATA,The MDIO Data register stores the Write data to be written to the PHY register located at the address specified in MAC_MDIO_Address. This register also stores the Read data from the PHY register located at the address specified by MDIO.." hexmask.long.word 0x4 16.--31. 1. "RA,Register Address This field is valid only when C45E is set. It contains the Register Address in the PHY to which the MDIO frame is intended for." newline hexmask.long.word 0x4 0.--15. 1. "GD,GMII Data This field contains the 16-bit data value read from the PHY after a Management Read operation or the 16-bit data value to be written to the PHY before a Management Write operation." group.long 0x230++0x7 line.long 0x0 "MAC_CSR_SW_CTRL,This register contains SW programmable controls for changing the CSR access response and status bits clearing." hexmask.long.tbyte 0x0 9.--31. 1. "RESERVED_31_9,Reserved." newline bitfld.long 0x0 8. "SEEN,Slave Error Response Enable When this bit is set the MAC responds with Slave Error for accesses to reserved registers in CSR space. When this bit is reset the MAC responds with Okay response to any register accessed from CSR space. 0x0: Slave.." "Slave Error Response is disabled,Slave Error Response is enabled" newline hexmask.long.byte 0x0 1.--7. 1. "RESERVED_7_1,Reserved." newline bitfld.long 0x0 0. "RCWE,Register Clear on Write 1 Enable When this bit is set the access mode of some register fields changes to Clear on Write 1 the application needs to set that respective bit to 1 to clear it. When this bit is reset the access mode of these register.." "Register Clear on Write 1 is disabled,Register Clear on Write 1 is enabled" line.long 0x4 "MAC_FPE_CTRL_STS,This register controls the operation of Frame Preemption." hexmask.long.word 0x4 20.--31. 1. "RESERVED_31_20,Reserved." newline bitfld.long 0x4 19. "TRSP,Transmitted Respond Frame Set when a Respond mPacket is transmitted (triggered by setting SRSP field). An interrupt can be generated for this event if FPEIE bit of MAC_Interrupt_Enable is set. Access restriction applies. Clears on read (or write of.." "Not transmitted Respond Frame,transmitted Respond Frame" newline bitfld.long 0x4 18. "TVER,Transmitted Verify Frame Set when a Verify mPacket is transmitted (triggered by setting SVER field). An interrupt can be generated for this event if FPEIE bit of MAC_Interrupt_Enable is set. Access restriction applies. Clears on read (or write of 1.." "Not transmitted Verify Frame,transmitted Verify Frame" newline bitfld.long 0x4 17. "RRSP,Received Respond Frame Set when a Respond mPacket is received. An interrupt can be generated for this event if FPEIE bit of MAC_Interrupt_Enable is set. Access restriction applies. Clears on read (or write of 1 when RCWE bit in MAC_CSR_SW_Ctrl.." "Not received Respond Frame,Received Respond Frame" newline bitfld.long 0x4 16. "RVER,Received Verify Frame Set when a Verify mPacket is received. An interrupt can be generated for this event if FPEIE bit of MAC_Interrupt_Enable is set. Access restriction applies. Clears on read (or write of 1 when RCWE bit in MAC_CSR_SW_Ctrl.." "Not received Verify Frame,Received Verify Frame" newline hexmask.long.word 0x4 4.--15. 1. "RESERVED_15_4,Reserved." newline bitfld.long 0x4 3. "S1_SET_0,Synopsys Reserved Must be set to '0'. This field is reserved for Synopsys Internal use and must always be set to '0' unless instructed by Synopsys. Setting to '1' might cause unexpected behavior in the IP." "0,1" newline bitfld.long 0x4 2. "SRSP,Send Respond mPacket When set indicates hardware to send a Respond mPacket. Reset by hardware after sending the Respond mPacket. Access restriction applies. Setting 1 sets. Self-cleared. Setting 0 has no effect. 0x0: Send Respond mPacket is disabled.." "Send Respond mPacket is disabled,Send Respond mPacket is enabled" newline bitfld.long 0x4 1. "SVER,Send Verify mPacket When set indicates hardware to send a verify mPacket. Reset by hardware after sending the Verify mPacket. Access restriction applies. Setting 1 sets. Self-cleared. Setting 0 has no effect. 0x0: Send Verify mPacket is disabled.." "Send Verify mPacket is disabled,Send Verify mPacket is enabled" newline bitfld.long 0x4 0. "EFPE,Enable Tx Frame Preemption When set Frame Preemption Tx functionality is enabled. 0x0: Tx Frame Preemption is disabled 0x1: Tx Frame Preemption is enabled" "Tx Frame Preemption is disabled,Tx Frame Preemption is enabled" rgroup.long 0x240++0x3 line.long 0x0 "MAC_PRESN_TIME_NS,This register contains the 32-bit binary rollover equivalent time of the PTP System Time in ns Exists when DWC_EQOS_FLEXI_PPS_OUT_EN is configured" hexmask.long 0x0 0.--31. 1. "MPTN,MAC 1722 Presentation Time in ns These bits indicate the value of the 32-bit binary rollover equivalent time of the PTP System Time in ns" group.long 0x244++0x3 line.long 0x0 "MAC_PRESN_TIME_UPDT,This field holds the 32-bit value of MAC 1722 Presentation Time in ns. that should be added to the Current Presentation Time Counter value. Init happens when TSINIT is set. and update happens when the TSUPDT bit is set (TSINIT and.." hexmask.long 0x0 0.--31. 1. "MPTU,MAC 1722 Presentation Time Update This field holds the init value or the update value for the presentation time. When used for update this field holds the 32-bit value in ns that should be added to the Current Presentation Time Counter value. Init.." group.long 0x300++0x403 line.long 0x0 "MAC_ADDRESS0_HIGH,The MAC Address0 High register holds the upper 16 bits of the first 6-byte MAC address of the station. The first DA byte that is received on the (G)MII interface corresponds to the LS byte (Bits [7:0]) of the MAC Address Low register." rbitfld.long 0x0 31. "AE,Address Enable This bit is always set to 1. 0x0: INVALID : This bit must be always set to 1 0x1: This bit is always set to 1" "INVALID : This bit must be always set to 1,This bit is always set to 1" newline hexmask.long.word 0x0 21.--30. 1. "RESERVED_30_Y,Reserved." newline hexmask.long.byte 0x0 16.--20. 1. "DCS,DMA Channel Select If the PDC bit of MAC_Ext_Configuration register is not set: This field contains the binary representation of the DMA Channel number to which an Rx packet whose DA matches the MAC Address0 content is routed. If the PDC bit of.." newline hexmask.long.word 0x0 0.--15. 1. "ADDRHI,MAC Address0[47:32] This field contains the upper 16 bits [47:32] of the first 6-byte MAC address. The MAC uses this field for filtering the received packets and inserting the MAC address in the Transmit Flow Control (Pause) Packets." line.long 0x4 "MAC_ADDRESS0_LOW,The MAC Address0 Low register holds the lower 32 bits of the 6-byte first MAC address of the station." hexmask.long 0x4 0.--31. 1. "ADDRLO,MAC Address0[31:0] This field contains the lower 32 bits of the first 6-byte MAC address. The MAC uses this field for filtering the received packets and inserting the MAC address in the Transmit Flow Control (Pause) Packets." line.long 0x8 "MAC_ADDRESS1_HIGH,The MAC Address1 High register holds the upper 16 bits of the second 6-byte MAC address of the station. If the MAC address registers are configured to be double-synchronized to the (G)MII clock domains. the synchronization is triggered.." bitfld.long 0x8 31. "AE,Address Enable When this bit is set the address filter module uses the second MAC address for perfect filtering. When this bit is reset the address filter module ignores the address for filtering. 0x0: Address is ignored 0x1: Address is enabled" "Address is ignored,Address is enabled" newline bitfld.long 0x8 30. "SA,Source Address When this bit is set the MAC Address1[47:0] is used to compare with the SA fields of the received packet. When this bit is reset the MAC Address1[47:0] is used to compare with the DA fields of the received packet. 0x0: Compare with.." "Compare with Destination Address,Compare with Source Address" newline hexmask.long.byte 0x8 24.--29. 1. "MBC,Mask Byte Control These bits are mask control bits for comparing each of the MAC Address bytes. When set high the MAC does not compare the corresponding byte of received DA or SA with the contents of MAC Address1 registers. Each bit controls the.." newline rbitfld.long 0x8 21.--23. "RESERVED_23_Y,Reserved." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x8 16.--20. 1. "DCS,DMA Channel Select If the PDC bit of MAC_Ext_Configuration register is not set: This field contains the binary representation of the DMA Channel number to which an Rx packet whose DA matches the MAC Address(#i) content is routed. If the PDC bit of.." newline hexmask.long.word 0x8 0.--15. 1. "ADDRHI,MAC Address1 [47:32] This field contains the upper 16 bits[47:32] of the second 6-byte MAC address." line.long 0xC "MAC_ADDRESS1_LOW,The MAC Address1 Low register holds the lower 32 bits of the second 6-byte MAC address of the station." hexmask.long 0xC 0.--31. 1. "ADDRLO,MAC Address1 [31:0] This field contains the lower 32 bits of second 6-byte MAC address. The content of this field is undefined until loaded by the application after the initialization process." line.long 0x10 "MAC_ADDRESS2_HIGH,The MAC Address1 High register holds the upper 16 bits of the second 6-byte MAC address of the station. If the MAC address registers are configured to be double-synchronized to the (G)MII clock domains. the synchronization is triggered.." bitfld.long 0x10 31. "AE,Address Enable When this bit is set the address filter module uses the second MAC address for perfect filtering. When this bit is reset the address filter module ignores the address for filtering. 0x0: Address is ignored 0x1: Address is enabled" "Address is ignored,Address is enabled" newline bitfld.long 0x10 30. "SA,Source Address When this bit is set the MAC Address1[47:0] is used to compare with the SA fields of the received packet. When this bit is reset the MAC Address1[47:0] is used to compare with the DA fields of the received packet. 0x0: Compare with.." "Compare with Destination Address,Compare with Source Address" newline hexmask.long.byte 0x10 24.--29. 1. "MBC,Mask Byte Control These bits are mask control bits for comparing each of the MAC Address bytes. When set high the MAC does not compare the corresponding byte of received DA or SA with the contents of MAC Address1 registers. Each bit controls the.." newline rbitfld.long 0x10 21.--23. "RESERVED_23_Y,Reserved." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x10 16.--20. 1. "DCS,DMA Channel Select If the PDC bit of MAC_Ext_Configuration register is not set: This field contains the binary representation of the DMA Channel number to which an Rx packet whose DA matches the MAC Address(#i) content is routed. If the PDC bit of.." newline hexmask.long.word 0x10 0.--15. 1. "ADDRHI,MAC Address1 [47:32] This field contains the upper 16 bits[47:32] of the second 6-byte MAC address." line.long 0x14 "MAC_ADDRESS2_LOW,The MAC Address1 Low register holds the lower 32 bits of the second 6-byte MAC address of the station." hexmask.long 0x14 0.--31. 1. "ADDRLO,MAC Address1 [31:0] This field contains the lower 32 bits of second 6-byte MAC address. The content of this field is undefined until loaded by the application after the initialization process." line.long 0x18 "MAC_ADDRESS3_HIGH,The MAC Address1 High register holds the upper 16 bits of the second 6-byte MAC address of the station. If the MAC address registers are configured to be double-synchronized to the (G)MII clock domains. the synchronization is triggered.." bitfld.long 0x18 31. "AE,Address Enable When this bit is set the address filter module uses the second MAC address for perfect filtering. When this bit is reset the address filter module ignores the address for filtering. 0x0: Address is ignored 0x1: Address is enabled" "Address is ignored,Address is enabled" newline bitfld.long 0x18 30. "SA,Source Address When this bit is set the MAC Address1[47:0] is used to compare with the SA fields of the received packet. When this bit is reset the MAC Address1[47:0] is used to compare with the DA fields of the received packet. 0x0: Compare with.." "Compare with Destination Address,Compare with Source Address" newline hexmask.long.byte 0x18 24.--29. 1. "MBC,Mask Byte Control These bits are mask control bits for comparing each of the MAC Address bytes. When set high the MAC does not compare the corresponding byte of received DA or SA with the contents of MAC Address1 registers. Each bit controls the.." newline rbitfld.long 0x18 21.--23. "RESERVED_23_Y,Reserved." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x18 16.--20. 1. "DCS,DMA Channel Select If the PDC bit of MAC_Ext_Configuration register is not set: This field contains the binary representation of the DMA Channel number to which an Rx packet whose DA matches the MAC Address(#i) content is routed. If the PDC bit of.." newline hexmask.long.word 0x18 0.--15. 1. "ADDRHI,MAC Address1 [47:32] This field contains the upper 16 bits[47:32] of the second 6-byte MAC address." line.long 0x1C "MAC_ADDRESS3_LOW,The MAC Address1 Low register holds the lower 32 bits of the second 6-byte MAC address of the station." hexmask.long 0x1C 0.--31. 1. "ADDRLO,MAC Address1 [31:0] This field contains the lower 32 bits of second 6-byte MAC address. The content of this field is undefined until loaded by the application after the initialization process." line.long 0x20 "MAC_ADDRESS4_HIGH,The MAC Address1 High register holds the upper 16 bits of the second 6-byte MAC address of the station. If the MAC address registers are configured to be double-synchronized to the (G)MII clock domains. the synchronization is triggered.." bitfld.long 0x20 31. "AE,Address Enable When this bit is set the address filter module uses the second MAC address for perfect filtering. When this bit is reset the address filter module ignores the address for filtering. 0x0: Address is ignored 0x1: Address is enabled" "Address is ignored,Address is enabled" newline bitfld.long 0x20 30. "SA,Source Address When this bit is set the MAC Address1[47:0] is used to compare with the SA fields of the received packet. When this bit is reset the MAC Address1[47:0] is used to compare with the DA fields of the received packet. 0x0: Compare with.." "Compare with Destination Address,Compare with Source Address" newline hexmask.long.byte 0x20 24.--29. 1. "MBC,Mask Byte Control These bits are mask control bits for comparing each of the MAC Address bytes. When set high the MAC does not compare the corresponding byte of received DA or SA with the contents of MAC Address1 registers. Each bit controls the.." newline rbitfld.long 0x20 21.--23. "RESERVED_23_Y,Reserved." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x20 16.--20. 1. "DCS,DMA Channel Select If the PDC bit of MAC_Ext_Configuration register is not set: This field contains the binary representation of the DMA Channel number to which an Rx packet whose DA matches the MAC Address(#i) content is routed. If the PDC bit of.." newline hexmask.long.word 0x20 0.--15. 1. "ADDRHI,MAC Address1 [47:32] This field contains the upper 16 bits[47:32] of the second 6-byte MAC address." line.long 0x24 "MAC_ADDRESS4_LOW,The MAC Address1 Low register holds the lower 32 bits of the second 6-byte MAC address of the station." hexmask.long 0x24 0.--31. 1. "ADDRLO,MAC Address1 [31:0] This field contains the lower 32 bits of second 6-byte MAC address. The content of this field is undefined until loaded by the application after the initialization process." line.long 0x28 "MAC_ADDRESS5_HIGH,The MAC Address1 High register holds the upper 16 bits of the second 6-byte MAC address of the station. If the MAC address registers are configured to be double-synchronized to the (G)MII clock domains. the synchronization is triggered.." bitfld.long 0x28 31. "AE,Address Enable When this bit is set the address filter module uses the second MAC address for perfect filtering. When this bit is reset the address filter module ignores the address for filtering. 0x0: Address is ignored 0x1: Address is enabled" "Address is ignored,Address is enabled" newline bitfld.long 0x28 30. "SA,Source Address When this bit is set the MAC Address1[47:0] is used to compare with the SA fields of the received packet. When this bit is reset the MAC Address1[47:0] is used to compare with the DA fields of the received packet. 0x0: Compare with.." "Compare with Destination Address,Compare with Source Address" newline hexmask.long.byte 0x28 24.--29. 1. "MBC,Mask Byte Control These bits are mask control bits for comparing each of the MAC Address bytes. When set high the MAC does not compare the corresponding byte of received DA or SA with the contents of MAC Address1 registers. Each bit controls the.." newline rbitfld.long 0x28 21.--23. "RESERVED_23_Y,Reserved." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x28 16.--20. 1. "DCS,DMA Channel Select If the PDC bit of MAC_Ext_Configuration register is not set: This field contains the binary representation of the DMA Channel number to which an Rx packet whose DA matches the MAC Address(#i) content is routed. If the PDC bit of.." newline hexmask.long.word 0x28 0.--15. 1. "ADDRHI,MAC Address1 [47:32] This field contains the upper 16 bits[47:32] of the second 6-byte MAC address." line.long 0x2C "MAC_ADDRESS5_LOW,The MAC Address1 Low register holds the lower 32 bits of the second 6-byte MAC address of the station." hexmask.long 0x2C 0.--31. 1. "ADDRLO,MAC Address1 [31:0] This field contains the lower 32 bits of second 6-byte MAC address. The content of this field is undefined until loaded by the application after the initialization process." line.long 0x30 "MAC_ADDRESS6_HIGH,The MAC Address1 High register holds the upper 16 bits of the second 6-byte MAC address of the station. If the MAC address registers are configured to be double-synchronized to the (G)MII clock domains. the synchronization is triggered.." bitfld.long 0x30 31. "AE,Address Enable When this bit is set the address filter module uses the second MAC address for perfect filtering. When this bit is reset the address filter module ignores the address for filtering. 0x0: Address is ignored 0x1: Address is enabled" "Address is ignored,Address is enabled" newline bitfld.long 0x30 30. "SA,Source Address When this bit is set the MAC Address1[47:0] is used to compare with the SA fields of the received packet. When this bit is reset the MAC Address1[47:0] is used to compare with the DA fields of the received packet. 0x0: Compare with.." "Compare with Destination Address,Compare with Source Address" newline hexmask.long.byte 0x30 24.--29. 1. "MBC,Mask Byte Control These bits are mask control bits for comparing each of the MAC Address bytes. When set high the MAC does not compare the corresponding byte of received DA or SA with the contents of MAC Address1 registers. Each bit controls the.." newline rbitfld.long 0x30 21.--23. "RESERVED_23_Y,Reserved." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x30 16.--20. 1. "DCS,DMA Channel Select If the PDC bit of MAC_Ext_Configuration register is not set: This field contains the binary representation of the DMA Channel number to which an Rx packet whose DA matches the MAC Address(#i) content is routed. If the PDC bit of.." newline hexmask.long.word 0x30 0.--15. 1. "ADDRHI,MAC Address1 [47:32] This field contains the upper 16 bits[47:32] of the second 6-byte MAC address." line.long 0x34 "MAC_ADDRESS6_LOW,The MAC Address1 Low register holds the lower 32 bits of the second 6-byte MAC address of the station." hexmask.long 0x34 0.--31. 1. "ADDRLO,MAC Address1 [31:0] This field contains the lower 32 bits of second 6-byte MAC address. The content of this field is undefined until loaded by the application after the initialization process." line.long 0x38 "MAC_ADDRESS7_HIGH,The MAC Address1 High register holds the upper 16 bits of the second 6-byte MAC address of the station. If the MAC address registers are configured to be double-synchronized to the (G)MII clock domains. the synchronization is triggered.." bitfld.long 0x38 31. "AE,Address Enable When this bit is set the address filter module uses the second MAC address for perfect filtering. When this bit is reset the address filter module ignores the address for filtering. 0x0: Address is ignored 0x1: Address is enabled" "Address is ignored,Address is enabled" newline bitfld.long 0x38 30. "SA,Source Address When this bit is set the MAC Address1[47:0] is used to compare with the SA fields of the received packet. When this bit is reset the MAC Address1[47:0] is used to compare with the DA fields of the received packet. 0x0: Compare with.." "Compare with Destination Address,Compare with Source Address" newline hexmask.long.byte 0x38 24.--29. 1. "MBC,Mask Byte Control These bits are mask control bits for comparing each of the MAC Address bytes. When set high the MAC does not compare the corresponding byte of received DA or SA with the contents of MAC Address1 registers. Each bit controls the.." newline rbitfld.long 0x38 21.--23. "RESERVED_23_Y,Reserved." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x38 16.--20. 1. "DCS,DMA Channel Select If the PDC bit of MAC_Ext_Configuration register is not set: This field contains the binary representation of the DMA Channel number to which an Rx packet whose DA matches the MAC Address(#i) content is routed. If the PDC bit of.." newline hexmask.long.word 0x38 0.--15. 1. "ADDRHI,MAC Address1 [47:32] This field contains the upper 16 bits[47:32] of the second 6-byte MAC address." line.long 0x3C "MAC_ADDRESS7_LOW,The MAC Address1 Low register holds the lower 32 bits of the second 6-byte MAC address of the station." hexmask.long 0x3C 0.--31. 1. "ADDRLO,MAC Address1 [31:0] This field contains the lower 32 bits of second 6-byte MAC address. The content of this field is undefined until loaded by the application after the initialization process." line.long 0x40 "MAC_ADDRESS8_HIGH,The MAC Address1 High register holds the upper 16 bits of the second 6-byte MAC address of the station. If the MAC address registers are configured to be double-synchronized to the (G)MII clock domains. the synchronization is triggered.." bitfld.long 0x40 31. "AE,Address Enable When this bit is set the address filter module uses the second MAC address for perfect filtering. When this bit is reset the address filter module ignores the address for filtering. 0x0: Address is ignored 0x1: Address is enabled" "Address is ignored,Address is enabled" newline bitfld.long 0x40 30. "SA,Source Address When this bit is set the MAC Address1[47:0] is used to compare with the SA fields of the received packet. When this bit is reset the MAC Address1[47:0] is used to compare with the DA fields of the received packet. 0x0: Compare with.." "Compare with Destination Address,Compare with Source Address" newline hexmask.long.byte 0x40 24.--29. 1. "MBC,Mask Byte Control These bits are mask control bits for comparing each of the MAC Address bytes. When set high the MAC does not compare the corresponding byte of received DA or SA with the contents of MAC Address1 registers. Each bit controls the.." newline rbitfld.long 0x40 21.--23. "RESERVED_23_Y,Reserved." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x40 16.--20. 1. "DCS,DMA Channel Select If the PDC bit of MAC_Ext_Configuration register is not set: This field contains the binary representation of the DMA Channel number to which an Rx packet whose DA matches the MAC Address(#i) content is routed. If the PDC bit of.." newline hexmask.long.word 0x40 0.--15. 1. "ADDRHI,MAC Address1 [47:32] This field contains the upper 16 bits[47:32] of the second 6-byte MAC address." line.long 0x44 "MAC_ADDRESS8_LOW,The MAC Address1 Low register holds the lower 32 bits of the second 6-byte MAC address of the station." hexmask.long 0x44 0.--31. 1. "ADDRLO,MAC Address1 [31:0] This field contains the lower 32 bits of second 6-byte MAC address. The content of this field is undefined until loaded by the application after the initialization process." line.long 0x48 "MAC_ADDRESS9_HIGH,The MAC Address1 High register holds the upper 16 bits of the second 6-byte MAC address of the station. If the MAC address registers are configured to be double-synchronized to the (G)MII clock domains. the synchronization is triggered.." bitfld.long 0x48 31. "AE,Address Enable When this bit is set the address filter module uses the second MAC address for perfect filtering. When this bit is reset the address filter module ignores the address for filtering. 0x0: Address is ignored 0x1: Address is enabled" "Address is ignored,Address is enabled" newline bitfld.long 0x48 30. "SA,Source Address When this bit is set the MAC Address1[47:0] is used to compare with the SA fields of the received packet. When this bit is reset the MAC Address1[47:0] is used to compare with the DA fields of the received packet. 0x0: Compare with.." "Compare with Destination Address,Compare with Source Address" newline hexmask.long.byte 0x48 24.--29. 1. "MBC,Mask Byte Control These bits are mask control bits for comparing each of the MAC Address bytes. When set high the MAC does not compare the corresponding byte of received DA or SA with the contents of MAC Address1 registers. Each bit controls the.." newline rbitfld.long 0x48 21.--23. "RESERVED_23_Y,Reserved." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x48 16.--20. 1. "DCS,DMA Channel Select If the PDC bit of MAC_Ext_Configuration register is not set: This field contains the binary representation of the DMA Channel number to which an Rx packet whose DA matches the MAC Address(#i) content is routed. If the PDC bit of.." newline hexmask.long.word 0x48 0.--15. 1. "ADDRHI,MAC Address1 [47:32] This field contains the upper 16 bits[47:32] of the second 6-byte MAC address." line.long 0x4C "MAC_ADDRESS9_LOW,The MAC Address1 Low register holds the lower 32 bits of the second 6-byte MAC address of the station." hexmask.long 0x4C 0.--31. 1. "ADDRLO,MAC Address1 [31:0] This field contains the lower 32 bits of second 6-byte MAC address. The content of this field is undefined until loaded by the application after the initialization process." line.long 0x50 "MAC_ADDRESS10_HIGH,The MAC Address1 High register holds the upper 16 bits of the second 6-byte MAC address of the station. If the MAC address registers are configured to be double-synchronized to the (G)MII clock domains. the synchronization is triggered.." bitfld.long 0x50 31. "AE,Address Enable When this bit is set the address filter module uses the second MAC address for perfect filtering. When this bit is reset the address filter module ignores the address for filtering. 0x0: Address is ignored 0x1: Address is enabled" "Address is ignored,Address is enabled" newline bitfld.long 0x50 30. "SA,Source Address When this bit is set the MAC Address1[47:0] is used to compare with the SA fields of the received packet. When this bit is reset the MAC Address1[47:0] is used to compare with the DA fields of the received packet. 0x0: Compare with.." "Compare with Destination Address,Compare with Source Address" newline hexmask.long.byte 0x50 24.--29. 1. "MBC,Mask Byte Control These bits are mask control bits for comparing each of the MAC Address bytes. When set high the MAC does not compare the corresponding byte of received DA or SA with the contents of MAC Address1 registers. Each bit controls the.." newline rbitfld.long 0x50 21.--23. "RESERVED_23_Y,Reserved." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x50 16.--20. 1. "DCS,DMA Channel Select If the PDC bit of MAC_Ext_Configuration register is not set: This field contains the binary representation of the DMA Channel number to which an Rx packet whose DA matches the MAC Address(#i) content is routed. If the PDC bit of.." newline hexmask.long.word 0x50 0.--15. 1. "ADDRHI,MAC Address1 [47:32] This field contains the upper 16 bits[47:32] of the second 6-byte MAC address." line.long 0x54 "MAC_ADDRESS10_LOW,The MAC Address1 Low register holds the lower 32 bits of the second 6-byte MAC address of the station." hexmask.long 0x54 0.--31. 1. "ADDRLO,MAC Address1 [31:0] This field contains the lower 32 bits of second 6-byte MAC address. The content of this field is undefined until loaded by the application after the initialization process." line.long 0x58 "MAC_ADDRESS11_HIGH,The MAC Address1 High register holds the upper 16 bits of the second 6-byte MAC address of the station. If the MAC address registers are configured to be double-synchronized to the (G)MII clock domains. the synchronization is triggered.." bitfld.long 0x58 31. "AE,Address Enable When this bit is set the address filter module uses the second MAC address for perfect filtering. When this bit is reset the address filter module ignores the address for filtering. 0x0: Address is ignored 0x1: Address is enabled" "Address is ignored,Address is enabled" newline bitfld.long 0x58 30. "SA,Source Address When this bit is set the MAC Address1[47:0] is used to compare with the SA fields of the received packet. When this bit is reset the MAC Address1[47:0] is used to compare with the DA fields of the received packet. 0x0: Compare with.." "Compare with Destination Address,Compare with Source Address" newline hexmask.long.byte 0x58 24.--29. 1. "MBC,Mask Byte Control These bits are mask control bits for comparing each of the MAC Address bytes. When set high the MAC does not compare the corresponding byte of received DA or SA with the contents of MAC Address1 registers. Each bit controls the.." newline rbitfld.long 0x58 21.--23. "RESERVED_23_Y,Reserved." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x58 16.--20. 1. "DCS,DMA Channel Select If the PDC bit of MAC_Ext_Configuration register is not set: This field contains the binary representation of the DMA Channel number to which an Rx packet whose DA matches the MAC Address(#i) content is routed. If the PDC bit of.." newline hexmask.long.word 0x58 0.--15. 1. "ADDRHI,MAC Address1 [47:32] This field contains the upper 16 bits[47:32] of the second 6-byte MAC address." line.long 0x5C "MAC_ADDRESS11_LOW,The MAC Address1 Low register holds the lower 32 bits of the second 6-byte MAC address of the station." hexmask.long 0x5C 0.--31. 1. "ADDRLO,MAC Address1 [31:0] This field contains the lower 32 bits of second 6-byte MAC address. The content of this field is undefined until loaded by the application after the initialization process." line.long 0x60 "MAC_ADDRESS12_HIGH,The MAC Address1 High register holds the upper 16 bits of the second 6-byte MAC address of the station. If the MAC address registers are configured to be double-synchronized to the (G)MII clock domains. the synchronization is triggered.." bitfld.long 0x60 31. "AE,Address Enable When this bit is set the address filter module uses the second MAC address for perfect filtering. When this bit is reset the address filter module ignores the address for filtering. 0x0: Address is ignored 0x1: Address is enabled" "Address is ignored,Address is enabled" newline bitfld.long 0x60 30. "SA,Source Address When this bit is set the MAC Address1[47:0] is used to compare with the SA fields of the received packet. When this bit is reset the MAC Address1[47:0] is used to compare with the DA fields of the received packet. 0x0: Compare with.." "Compare with Destination Address,Compare with Source Address" newline hexmask.long.byte 0x60 24.--29. 1. "MBC,Mask Byte Control These bits are mask control bits for comparing each of the MAC Address bytes. When set high the MAC does not compare the corresponding byte of received DA or SA with the contents of MAC Address1 registers. Each bit controls the.." newline rbitfld.long 0x60 21.--23. "RESERVED_23_Y,Reserved." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x60 16.--20. 1. "DCS,DMA Channel Select If the PDC bit of MAC_Ext_Configuration register is not set: This field contains the binary representation of the DMA Channel number to which an Rx packet whose DA matches the MAC Address(#i) content is routed. If the PDC bit of.." newline hexmask.long.word 0x60 0.--15. 1. "ADDRHI,MAC Address1 [47:32] This field contains the upper 16 bits[47:32] of the second 6-byte MAC address." line.long 0x64 "MAC_ADDRESS12_LOW,The MAC Address1 Low register holds the lower 32 bits of the second 6-byte MAC address of the station." hexmask.long 0x64 0.--31. 1. "ADDRLO,MAC Address1 [31:0] This field contains the lower 32 bits of second 6-byte MAC address. The content of this field is undefined until loaded by the application after the initialization process." line.long 0x68 "MAC_ADDRESS13_HIGH,The MAC Address1 High register holds the upper 16 bits of the second 6-byte MAC address of the station. If the MAC address registers are configured to be double-synchronized to the (G)MII clock domains. the synchronization is triggered.." bitfld.long 0x68 31. "AE,Address Enable When this bit is set the address filter module uses the second MAC address for perfect filtering. When this bit is reset the address filter module ignores the address for filtering. 0x0: Address is ignored 0x1: Address is enabled" "Address is ignored,Address is enabled" newline bitfld.long 0x68 30. "SA,Source Address When this bit is set the MAC Address1[47:0] is used to compare with the SA fields of the received packet. When this bit is reset the MAC Address1[47:0] is used to compare with the DA fields of the received packet. 0x0: Compare with.." "Compare with Destination Address,Compare with Source Address" newline hexmask.long.byte 0x68 24.--29. 1. "MBC,Mask Byte Control These bits are mask control bits for comparing each of the MAC Address bytes. When set high the MAC does not compare the corresponding byte of received DA or SA with the contents of MAC Address1 registers. Each bit controls the.." newline rbitfld.long 0x68 21.--23. "RESERVED_23_Y,Reserved." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x68 16.--20. 1. "DCS,DMA Channel Select If the PDC bit of MAC_Ext_Configuration register is not set: This field contains the binary representation of the DMA Channel number to which an Rx packet whose DA matches the MAC Address(#i) content is routed. If the PDC bit of.." newline hexmask.long.word 0x68 0.--15. 1. "ADDRHI,MAC Address1 [47:32] This field contains the upper 16 bits[47:32] of the second 6-byte MAC address." line.long 0x6C "MAC_ADDRESS13_LOW,The MAC Address1 Low register holds the lower 32 bits of the second 6-byte MAC address of the station." hexmask.long 0x6C 0.--31. 1. "ADDRLO,MAC Address1 [31:0] This field contains the lower 32 bits of second 6-byte MAC address. The content of this field is undefined until loaded by the application after the initialization process." line.long 0x70 "MAC_ADDRESS14_HIGH,The MAC Address1 High register holds the upper 16 bits of the second 6-byte MAC address of the station. If the MAC address registers are configured to be double-synchronized to the (G)MII clock domains. the synchronization is triggered.." bitfld.long 0x70 31. "AE,Address Enable When this bit is set the address filter module uses the second MAC address for perfect filtering. When this bit is reset the address filter module ignores the address for filtering. 0x0: Address is ignored 0x1: Address is enabled" "Address is ignored,Address is enabled" newline bitfld.long 0x70 30. "SA,Source Address When this bit is set the MAC Address1[47:0] is used to compare with the SA fields of the received packet. When this bit is reset the MAC Address1[47:0] is used to compare with the DA fields of the received packet. 0x0: Compare with.." "Compare with Destination Address,Compare with Source Address" newline hexmask.long.byte 0x70 24.--29. 1. "MBC,Mask Byte Control These bits are mask control bits for comparing each of the MAC Address bytes. When set high the MAC does not compare the corresponding byte of received DA or SA with the contents of MAC Address1 registers. Each bit controls the.." newline rbitfld.long 0x70 21.--23. "RESERVED_23_Y,Reserved." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x70 16.--20. 1. "DCS,DMA Channel Select If the PDC bit of MAC_Ext_Configuration register is not set: This field contains the binary representation of the DMA Channel number to which an Rx packet whose DA matches the MAC Address(#i) content is routed. If the PDC bit of.." newline hexmask.long.word 0x70 0.--15. 1. "ADDRHI,MAC Address1 [47:32] This field contains the upper 16 bits[47:32] of the second 6-byte MAC address." line.long 0x74 "MAC_ADDRESS14_LOW,The MAC Address1 Low register holds the lower 32 bits of the second 6-byte MAC address of the station." hexmask.long 0x74 0.--31. 1. "ADDRLO,MAC Address1 [31:0] This field contains the lower 32 bits of second 6-byte MAC address. The content of this field is undefined until loaded by the application after the initialization process." line.long 0x78 "MAC_ADDRESS15_HIGH,The MAC Address1 High register holds the upper 16 bits of the second 6-byte MAC address of the station. If the MAC address registers are configured to be double-synchronized to the (G)MII clock domains. the synchronization is triggered.." bitfld.long 0x78 31. "AE,Address Enable When this bit is set the address filter module uses the second MAC address for perfect filtering. When this bit is reset the address filter module ignores the address for filtering. 0x0: Address is ignored 0x1: Address is enabled" "Address is ignored,Address is enabled" newline bitfld.long 0x78 30. "SA,Source Address When this bit is set the MAC Address1[47:0] is used to compare with the SA fields of the received packet. When this bit is reset the MAC Address1[47:0] is used to compare with the DA fields of the received packet. 0x0: Compare with.." "Compare with Destination Address,Compare with Source Address" newline hexmask.long.byte 0x78 24.--29. 1. "MBC,Mask Byte Control These bits are mask control bits for comparing each of the MAC Address bytes. When set high the MAC does not compare the corresponding byte of received DA or SA with the contents of MAC Address1 registers. Each bit controls the.." newline rbitfld.long 0x78 21.--23. "RESERVED_23_Y,Reserved." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x78 16.--20. 1. "DCS,DMA Channel Select If the PDC bit of MAC_Ext_Configuration register is not set: This field contains the binary representation of the DMA Channel number to which an Rx packet whose DA matches the MAC Address(#i) content is routed. If the PDC bit of.." newline hexmask.long.word 0x78 0.--15. 1. "ADDRHI,MAC Address1 [47:32] This field contains the upper 16 bits[47:32] of the second 6-byte MAC address." line.long 0x7C "MAC_ADDRESS15_LOW,The MAC Address1 Low register holds the lower 32 bits of the second 6-byte MAC address of the station." hexmask.long 0x7C 0.--31. 1. "ADDRLO,MAC Address1 [31:0] This field contains the lower 32 bits of second 6-byte MAC address. The content of this field is undefined until loaded by the application after the initialization process." line.long 0x80 "MAC_ADDRESS16_HIGH,The MAC Address1 High register holds the upper 16 bits of the second 6-byte MAC address of the station. If the MAC address registers are configured to be double-synchronized to the (G)MII clock domains. the synchronization is triggered.." bitfld.long 0x80 31. "AE,Address Enable When this bit is set the address filter module uses the second MAC address for perfect filtering. When this bit is reset the address filter module ignores the address for filtering. 0x0: Address is ignored 0x1: Address is enabled" "Address is ignored,Address is enabled" newline bitfld.long 0x80 30. "SA,Source Address When this bit is set the MAC Address1[47:0] is used to compare with the SA fields of the received packet. When this bit is reset the MAC Address1[47:0] is used to compare with the DA fields of the received packet. 0x0: Compare with.." "Compare with Destination Address,Compare with Source Address" newline hexmask.long.byte 0x80 24.--29. 1. "MBC,Mask Byte Control These bits are mask control bits for comparing each of the MAC Address bytes. When set high the MAC does not compare the corresponding byte of received DA or SA with the contents of MAC Address1 registers. Each bit controls the.." newline rbitfld.long 0x80 21.--23. "RESERVED_23_Y,Reserved." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x80 16.--20. 1. "DCS,DMA Channel Select If the PDC bit of MAC_Ext_Configuration register is not set: This field contains the binary representation of the DMA Channel number to which an Rx packet whose DA matches the MAC Address(#i) content is routed. If the PDC bit of.." newline hexmask.long.word 0x80 0.--15. 1. "ADDRHI,MAC Address1 [47:32] This field contains the upper 16 bits[47:32] of the second 6-byte MAC address." line.long 0x84 "MAC_ADDRESS16_LOW,The MAC Address1 Low register holds the lower 32 bits of the second 6-byte MAC address of the station." hexmask.long 0x84 0.--31. 1. "ADDRLO,MAC Address1 [31:0] This field contains the lower 32 bits of second 6-byte MAC address. The content of this field is undefined until loaded by the application after the initialization process." line.long 0x88 "MAC_ADDRESS17_HIGH,The MAC Address1 High register holds the upper 16 bits of the second 6-byte MAC address of the station. If the MAC address registers are configured to be double-synchronized to the (G)MII clock domains. the synchronization is triggered.." bitfld.long 0x88 31. "AE,Address Enable When this bit is set the address filter module uses the second MAC address for perfect filtering. When this bit is reset the address filter module ignores the address for filtering. 0x0: Address is ignored 0x1: Address is enabled" "Address is ignored,Address is enabled" newline bitfld.long 0x88 30. "SA,Source Address When this bit is set the MAC Address1[47:0] is used to compare with the SA fields of the received packet. When this bit is reset the MAC Address1[47:0] is used to compare with the DA fields of the received packet. 0x0: Compare with.." "Compare with Destination Address,Compare with Source Address" newline hexmask.long.byte 0x88 24.--29. 1. "MBC,Mask Byte Control These bits are mask control bits for comparing each of the MAC Address bytes. When set high the MAC does not compare the corresponding byte of received DA or SA with the contents of MAC Address1 registers. Each bit controls the.." newline rbitfld.long 0x88 21.--23. "RESERVED_23_Y,Reserved." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x88 16.--20. 1. "DCS,DMA Channel Select If the PDC bit of MAC_Ext_Configuration register is not set: This field contains the binary representation of the DMA Channel number to which an Rx packet whose DA matches the MAC Address(#i) content is routed. If the PDC bit of.." newline hexmask.long.word 0x88 0.--15. 1. "ADDRHI,MAC Address1 [47:32] This field contains the upper 16 bits[47:32] of the second 6-byte MAC address." line.long 0x8C "MAC_ADDRESS17_LOW,The MAC Address1 Low register holds the lower 32 bits of the second 6-byte MAC address of the station." hexmask.long 0x8C 0.--31. 1. "ADDRLO,MAC Address1 [31:0] This field contains the lower 32 bits of second 6-byte MAC address. The content of this field is undefined until loaded by the application after the initialization process." line.long 0x90 "MAC_ADDRESS18_HIGH,The MAC Address1 High register holds the upper 16 bits of the second 6-byte MAC address of the station. If the MAC address registers are configured to be double-synchronized to the (G)MII clock domains. the synchronization is triggered.." bitfld.long 0x90 31. "AE,Address Enable When this bit is set the address filter module uses the second MAC address for perfect filtering. When this bit is reset the address filter module ignores the address for filtering. 0x0: Address is ignored 0x1: Address is enabled" "Address is ignored,Address is enabled" newline bitfld.long 0x90 30. "SA,Source Address When this bit is set the MAC Address1[47:0] is used to compare with the SA fields of the received packet. When this bit is reset the MAC Address1[47:0] is used to compare with the DA fields of the received packet. 0x0: Compare with.." "Compare with Destination Address,Compare with Source Address" newline hexmask.long.byte 0x90 24.--29. 1. "MBC,Mask Byte Control These bits are mask control bits for comparing each of the MAC Address bytes. When set high the MAC does not compare the corresponding byte of received DA or SA with the contents of MAC Address1 registers. Each bit controls the.." newline rbitfld.long 0x90 21.--23. "RESERVED_23_Y,Reserved." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x90 16.--20. 1. "DCS,DMA Channel Select If the PDC bit of MAC_Ext_Configuration register is not set: This field contains the binary representation of the DMA Channel number to which an Rx packet whose DA matches the MAC Address(#i) content is routed. If the PDC bit of.." newline hexmask.long.word 0x90 0.--15. 1. "ADDRHI,MAC Address1 [47:32] This field contains the upper 16 bits[47:32] of the second 6-byte MAC address." line.long 0x94 "MAC_ADDRESS18_LOW,The MAC Address1 Low register holds the lower 32 bits of the second 6-byte MAC address of the station." hexmask.long 0x94 0.--31. 1. "ADDRLO,MAC Address1 [31:0] This field contains the lower 32 bits of second 6-byte MAC address. The content of this field is undefined until loaded by the application after the initialization process." line.long 0x98 "MAC_ADDRESS19_HIGH,The MAC Address1 High register holds the upper 16 bits of the second 6-byte MAC address of the station. If the MAC address registers are configured to be double-synchronized to the (G)MII clock domains. the synchronization is triggered.." bitfld.long 0x98 31. "AE,Address Enable When this bit is set the address filter module uses the second MAC address for perfect filtering. When this bit is reset the address filter module ignores the address for filtering. 0x0: Address is ignored 0x1: Address is enabled" "Address is ignored,Address is enabled" newline bitfld.long 0x98 30. "SA,Source Address When this bit is set the MAC Address1[47:0] is used to compare with the SA fields of the received packet. When this bit is reset the MAC Address1[47:0] is used to compare with the DA fields of the received packet. 0x0: Compare with.." "Compare with Destination Address,Compare with Source Address" newline hexmask.long.byte 0x98 24.--29. 1. "MBC,Mask Byte Control These bits are mask control bits for comparing each of the MAC Address bytes. When set high the MAC does not compare the corresponding byte of received DA or SA with the contents of MAC Address1 registers. Each bit controls the.." newline rbitfld.long 0x98 21.--23. "RESERVED_23_Y,Reserved." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x98 16.--20. 1. "DCS,DMA Channel Select If the PDC bit of MAC_Ext_Configuration register is not set: This field contains the binary representation of the DMA Channel number to which an Rx packet whose DA matches the MAC Address(#i) content is routed. If the PDC bit of.." newline hexmask.long.word 0x98 0.--15. 1. "ADDRHI,MAC Address1 [47:32] This field contains the upper 16 bits[47:32] of the second 6-byte MAC address." line.long 0x9C "MAC_ADDRESS19_LOW,The MAC Address1 Low register holds the lower 32 bits of the second 6-byte MAC address of the station." hexmask.long 0x9C 0.--31. 1. "ADDRLO,MAC Address1 [31:0] This field contains the lower 32 bits of second 6-byte MAC address. The content of this field is undefined until loaded by the application after the initialization process." line.long 0xA0 "MAC_ADDRESS20_HIGH,The MAC Address1 High register holds the upper 16 bits of the second 6-byte MAC address of the station. If the MAC address registers are configured to be double-synchronized to the (G)MII clock domains. the synchronization is triggered.." bitfld.long 0xA0 31. "AE,Address Enable When this bit is set the address filter module uses the second MAC address for perfect filtering. When this bit is reset the address filter module ignores the address for filtering. 0x0: Address is ignored 0x1: Address is enabled" "Address is ignored,Address is enabled" newline bitfld.long 0xA0 30. "SA,Source Address When this bit is set the MAC Address1[47:0] is used to compare with the SA fields of the received packet. When this bit is reset the MAC Address1[47:0] is used to compare with the DA fields of the received packet. 0x0: Compare with.." "Compare with Destination Address,Compare with Source Address" newline hexmask.long.byte 0xA0 24.--29. 1. "MBC,Mask Byte Control These bits are mask control bits for comparing each of the MAC Address bytes. When set high the MAC does not compare the corresponding byte of received DA or SA with the contents of MAC Address1 registers. Each bit controls the.." newline rbitfld.long 0xA0 21.--23. "RESERVED_23_Y,Reserved." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0xA0 16.--20. 1. "DCS,DMA Channel Select If the PDC bit of MAC_Ext_Configuration register is not set: This field contains the binary representation of the DMA Channel number to which an Rx packet whose DA matches the MAC Address(#i) content is routed. If the PDC bit of.." newline hexmask.long.word 0xA0 0.--15. 1. "ADDRHI,MAC Address1 [47:32] This field contains the upper 16 bits[47:32] of the second 6-byte MAC address." line.long 0xA4 "MAC_ADDRESS20_LOW,The MAC Address1 Low register holds the lower 32 bits of the second 6-byte MAC address of the station." hexmask.long 0xA4 0.--31. 1. "ADDRLO,MAC Address1 [31:0] This field contains the lower 32 bits of second 6-byte MAC address. The content of this field is undefined until loaded by the application after the initialization process." line.long 0xA8 "MAC_ADDRESS21_HIGH,The MAC Address1 High register holds the upper 16 bits of the second 6-byte MAC address of the station. If the MAC address registers are configured to be double-synchronized to the (G)MII clock domains. the synchronization is triggered.." bitfld.long 0xA8 31. "AE,Address Enable When this bit is set the address filter module uses the second MAC address for perfect filtering. When this bit is reset the address filter module ignores the address for filtering. 0x0: Address is ignored 0x1: Address is enabled" "Address is ignored,Address is enabled" newline bitfld.long 0xA8 30. "SA,Source Address When this bit is set the MAC Address1[47:0] is used to compare with the SA fields of the received packet. When this bit is reset the MAC Address1[47:0] is used to compare with the DA fields of the received packet. 0x0: Compare with.." "Compare with Destination Address,Compare with Source Address" newline hexmask.long.byte 0xA8 24.--29. 1. "MBC,Mask Byte Control These bits are mask control bits for comparing each of the MAC Address bytes. When set high the MAC does not compare the corresponding byte of received DA or SA with the contents of MAC Address1 registers. Each bit controls the.." newline rbitfld.long 0xA8 21.--23. "RESERVED_23_Y,Reserved." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0xA8 16.--20. 1. "DCS,DMA Channel Select If the PDC bit of MAC_Ext_Configuration register is not set: This field contains the binary representation of the DMA Channel number to which an Rx packet whose DA matches the MAC Address(#i) content is routed. If the PDC bit of.." newline hexmask.long.word 0xA8 0.--15. 1. "ADDRHI,MAC Address1 [47:32] This field contains the upper 16 bits[47:32] of the second 6-byte MAC address." line.long 0xAC "MAC_ADDRESS21_LOW,The MAC Address1 Low register holds the lower 32 bits of the second 6-byte MAC address of the station." hexmask.long 0xAC 0.--31. 1. "ADDRLO,MAC Address1 [31:0] This field contains the lower 32 bits of second 6-byte MAC address. The content of this field is undefined until loaded by the application after the initialization process." line.long 0xB0 "MAC_ADDRESS22_HIGH,The MAC Address1 High register holds the upper 16 bits of the second 6-byte MAC address of the station. If the MAC address registers are configured to be double-synchronized to the (G)MII clock domains. the synchronization is triggered.." bitfld.long 0xB0 31. "AE,Address Enable When this bit is set the address filter module uses the second MAC address for perfect filtering. When this bit is reset the address filter module ignores the address for filtering. 0x0: Address is ignored 0x1: Address is enabled" "Address is ignored,Address is enabled" newline bitfld.long 0xB0 30. "SA,Source Address When this bit is set the MAC Address1[47:0] is used to compare with the SA fields of the received packet. When this bit is reset the MAC Address1[47:0] is used to compare with the DA fields of the received packet. 0x0: Compare with.." "Compare with Destination Address,Compare with Source Address" newline hexmask.long.byte 0xB0 24.--29. 1. "MBC,Mask Byte Control These bits are mask control bits for comparing each of the MAC Address bytes. When set high the MAC does not compare the corresponding byte of received DA or SA with the contents of MAC Address1 registers. Each bit controls the.." newline rbitfld.long 0xB0 21.--23. "RESERVED_23_Y,Reserved." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0xB0 16.--20. 1. "DCS,DMA Channel Select If the PDC bit of MAC_Ext_Configuration register is not set: This field contains the binary representation of the DMA Channel number to which an Rx packet whose DA matches the MAC Address(#i) content is routed. If the PDC bit of.." newline hexmask.long.word 0xB0 0.--15. 1. "ADDRHI,MAC Address1 [47:32] This field contains the upper 16 bits[47:32] of the second 6-byte MAC address." line.long 0xB4 "MAC_ADDRESS22_LOW,The MAC Address1 Low register holds the lower 32 bits of the second 6-byte MAC address of the station." hexmask.long 0xB4 0.--31. 1. "ADDRLO,MAC Address1 [31:0] This field contains the lower 32 bits of second 6-byte MAC address. The content of this field is undefined until loaded by the application after the initialization process." line.long 0xB8 "MAC_ADDRESS23_HIGH,The MAC Address1 High register holds the upper 16 bits of the second 6-byte MAC address of the station. If the MAC address registers are configured to be double-synchronized to the (G)MII clock domains. the synchronization is triggered.." bitfld.long 0xB8 31. "AE,Address Enable When this bit is set the address filter module uses the second MAC address for perfect filtering. When this bit is reset the address filter module ignores the address for filtering. 0x0: Address is ignored 0x1: Address is enabled" "Address is ignored,Address is enabled" newline bitfld.long 0xB8 30. "SA,Source Address When this bit is set the MAC Address1[47:0] is used to compare with the SA fields of the received packet. When this bit is reset the MAC Address1[47:0] is used to compare with the DA fields of the received packet. 0x0: Compare with.." "Compare with Destination Address,Compare with Source Address" newline hexmask.long.byte 0xB8 24.--29. 1. "MBC,Mask Byte Control These bits are mask control bits for comparing each of the MAC Address bytes. When set high the MAC does not compare the corresponding byte of received DA or SA with the contents of MAC Address1 registers. Each bit controls the.." newline rbitfld.long 0xB8 21.--23. "RESERVED_23_Y,Reserved." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0xB8 16.--20. 1. "DCS,DMA Channel Select If the PDC bit of MAC_Ext_Configuration register is not set: This field contains the binary representation of the DMA Channel number to which an Rx packet whose DA matches the MAC Address(#i) content is routed. If the PDC bit of.." newline hexmask.long.word 0xB8 0.--15. 1. "ADDRHI,MAC Address1 [47:32] This field contains the upper 16 bits[47:32] of the second 6-byte MAC address." line.long 0xBC "MAC_ADDRESS23_LOW,The MAC Address1 Low register holds the lower 32 bits of the second 6-byte MAC address of the station." hexmask.long 0xBC 0.--31. 1. "ADDRLO,MAC Address1 [31:0] This field contains the lower 32 bits of second 6-byte MAC address. The content of this field is undefined until loaded by the application after the initialization process." line.long 0xC0 "MAC_ADDRESS24_HIGH,The MAC Address1 High register holds the upper 16 bits of the second 6-byte MAC address of the station. If the MAC address registers are configured to be double-synchronized to the (G)MII clock domains. the synchronization is triggered.." bitfld.long 0xC0 31. "AE,Address Enable When this bit is set the address filter module uses the second MAC address for perfect filtering. When this bit is reset the address filter module ignores the address for filtering. 0x0: Address is ignored 0x1: Address is enabled" "Address is ignored,Address is enabled" newline bitfld.long 0xC0 30. "SA,Source Address When this bit is set the MAC Address1[47:0] is used to compare with the SA fields of the received packet. When this bit is reset the MAC Address1[47:0] is used to compare with the DA fields of the received packet. 0x0: Compare with.." "Compare with Destination Address,Compare with Source Address" newline hexmask.long.byte 0xC0 24.--29. 1. "MBC,Mask Byte Control These bits are mask control bits for comparing each of the MAC Address bytes. When set high the MAC does not compare the corresponding byte of received DA or SA with the contents of MAC Address1 registers. Each bit controls the.." newline rbitfld.long 0xC0 21.--23. "RESERVED_23_Y,Reserved." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0xC0 16.--20. 1. "DCS,DMA Channel Select If the PDC bit of MAC_Ext_Configuration register is not set: This field contains the binary representation of the DMA Channel number to which an Rx packet whose DA matches the MAC Address(#i) content is routed. If the PDC bit of.." newline hexmask.long.word 0xC0 0.--15. 1. "ADDRHI,MAC Address1 [47:32] This field contains the upper 16 bits[47:32] of the second 6-byte MAC address." line.long 0xC4 "MAC_ADDRESS24_LOW,The MAC Address1 Low register holds the lower 32 bits of the second 6-byte MAC address of the station." hexmask.long 0xC4 0.--31. 1. "ADDRLO,MAC Address1 [31:0] This field contains the lower 32 bits of second 6-byte MAC address. The content of this field is undefined until loaded by the application after the initialization process." line.long 0xC8 "MAC_ADDRESS25_HIGH,The MAC Address1 High register holds the upper 16 bits of the second 6-byte MAC address of the station. If the MAC address registers are configured to be double-synchronized to the (G)MII clock domains. the synchronization is triggered.." bitfld.long 0xC8 31. "AE,Address Enable When this bit is set the address filter module uses the second MAC address for perfect filtering. When this bit is reset the address filter module ignores the address for filtering. 0x0: Address is ignored 0x1: Address is enabled" "Address is ignored,Address is enabled" newline bitfld.long 0xC8 30. "SA,Source Address When this bit is set the MAC Address1[47:0] is used to compare with the SA fields of the received packet. When this bit is reset the MAC Address1[47:0] is used to compare with the DA fields of the received packet. 0x0: Compare with.." "Compare with Destination Address,Compare with Source Address" newline hexmask.long.byte 0xC8 24.--29. 1. "MBC,Mask Byte Control These bits are mask control bits for comparing each of the MAC Address bytes. When set high the MAC does not compare the corresponding byte of received DA or SA with the contents of MAC Address1 registers. Each bit controls the.." newline rbitfld.long 0xC8 21.--23. "RESERVED_23_Y,Reserved." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0xC8 16.--20. 1. "DCS,DMA Channel Select If the PDC bit of MAC_Ext_Configuration register is not set: This field contains the binary representation of the DMA Channel number to which an Rx packet whose DA matches the MAC Address(#i) content is routed. If the PDC bit of.." newline hexmask.long.word 0xC8 0.--15. 1. "ADDRHI,MAC Address1 [47:32] This field contains the upper 16 bits[47:32] of the second 6-byte MAC address." line.long 0xCC "MAC_ADDRESS25_LOW,The MAC Address1 Low register holds the lower 32 bits of the second 6-byte MAC address of the station." hexmask.long 0xCC 0.--31. 1. "ADDRLO,MAC Address1 [31:0] This field contains the lower 32 bits of second 6-byte MAC address. The content of this field is undefined until loaded by the application after the initialization process." line.long 0xD0 "MAC_ADDRESS26_HIGH,The MAC Address1 High register holds the upper 16 bits of the second 6-byte MAC address of the station. If the MAC address registers are configured to be double-synchronized to the (G)MII clock domains. the synchronization is triggered.." bitfld.long 0xD0 31. "AE,Address Enable When this bit is set the address filter module uses the second MAC address for perfect filtering. When this bit is reset the address filter module ignores the address for filtering. 0x0: Address is ignored 0x1: Address is enabled" "Address is ignored,Address is enabled" newline bitfld.long 0xD0 30. "SA,Source Address When this bit is set the MAC Address1[47:0] is used to compare with the SA fields of the received packet. When this bit is reset the MAC Address1[47:0] is used to compare with the DA fields of the received packet. 0x0: Compare with.." "Compare with Destination Address,Compare with Source Address" newline hexmask.long.byte 0xD0 24.--29. 1. "MBC,Mask Byte Control These bits are mask control bits for comparing each of the MAC Address bytes. When set high the MAC does not compare the corresponding byte of received DA or SA with the contents of MAC Address1 registers. Each bit controls the.." newline rbitfld.long 0xD0 21.--23. "RESERVED_23_Y,Reserved." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0xD0 16.--20. 1. "DCS,DMA Channel Select If the PDC bit of MAC_Ext_Configuration register is not set: This field contains the binary representation of the DMA Channel number to which an Rx packet whose DA matches the MAC Address(#i) content is routed. If the PDC bit of.." newline hexmask.long.word 0xD0 0.--15. 1. "ADDRHI,MAC Address1 [47:32] This field contains the upper 16 bits[47:32] of the second 6-byte MAC address." line.long 0xD4 "MAC_ADDRESS26_LOW,The MAC Address1 Low register holds the lower 32 bits of the second 6-byte MAC address of the station." hexmask.long 0xD4 0.--31. 1. "ADDRLO,MAC Address1 [31:0] This field contains the lower 32 bits of second 6-byte MAC address. The content of this field is undefined until loaded by the application after the initialization process." line.long 0xD8 "MAC_ADDRESS27_HIGH,The MAC Address1 High register holds the upper 16 bits of the second 6-byte MAC address of the station. If the MAC address registers are configured to be double-synchronized to the (G)MII clock domains. the synchronization is triggered.." bitfld.long 0xD8 31. "AE,Address Enable When this bit is set the address filter module uses the second MAC address for perfect filtering. When this bit is reset the address filter module ignores the address for filtering. 0x0: Address is ignored 0x1: Address is enabled" "Address is ignored,Address is enabled" newline bitfld.long 0xD8 30. "SA,Source Address When this bit is set the MAC Address1[47:0] is used to compare with the SA fields of the received packet. When this bit is reset the MAC Address1[47:0] is used to compare with the DA fields of the received packet. 0x0: Compare with.." "Compare with Destination Address,Compare with Source Address" newline hexmask.long.byte 0xD8 24.--29. 1. "MBC,Mask Byte Control These bits are mask control bits for comparing each of the MAC Address bytes. When set high the MAC does not compare the corresponding byte of received DA or SA with the contents of MAC Address1 registers. Each bit controls the.." newline rbitfld.long 0xD8 21.--23. "RESERVED_23_Y,Reserved." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0xD8 16.--20. 1. "DCS,DMA Channel Select If the PDC bit of MAC_Ext_Configuration register is not set: This field contains the binary representation of the DMA Channel number to which an Rx packet whose DA matches the MAC Address(#i) content is routed. If the PDC bit of.." newline hexmask.long.word 0xD8 0.--15. 1. "ADDRHI,MAC Address1 [47:32] This field contains the upper 16 bits[47:32] of the second 6-byte MAC address." line.long 0xDC "MAC_ADDRESS27_LOW,The MAC Address1 Low register holds the lower 32 bits of the second 6-byte MAC address of the station." hexmask.long 0xDC 0.--31. 1. "ADDRLO,MAC Address1 [31:0] This field contains the lower 32 bits of second 6-byte MAC address. The content of this field is undefined until loaded by the application after the initialization process." line.long 0xE0 "MAC_ADDRESS28_HIGH,The MAC Address1 High register holds the upper 16 bits of the second 6-byte MAC address of the station. If the MAC address registers are configured to be double-synchronized to the (G)MII clock domains. the synchronization is triggered.." bitfld.long 0xE0 31. "AE,Address Enable When this bit is set the address filter module uses the second MAC address for perfect filtering. When this bit is reset the address filter module ignores the address for filtering. 0x0: Address is ignored 0x1: Address is enabled" "Address is ignored,Address is enabled" newline bitfld.long 0xE0 30. "SA,Source Address When this bit is set the MAC Address1[47:0] is used to compare with the SA fields of the received packet. When this bit is reset the MAC Address1[47:0] is used to compare with the DA fields of the received packet. 0x0: Compare with.." "Compare with Destination Address,Compare with Source Address" newline hexmask.long.byte 0xE0 24.--29. 1. "MBC,Mask Byte Control These bits are mask control bits for comparing each of the MAC Address bytes. When set high the MAC does not compare the corresponding byte of received DA or SA with the contents of MAC Address1 registers. Each bit controls the.." newline rbitfld.long 0xE0 21.--23. "RESERVED_23_Y,Reserved." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0xE0 16.--20. 1. "DCS,DMA Channel Select If the PDC bit of MAC_Ext_Configuration register is not set: This field contains the binary representation of the DMA Channel number to which an Rx packet whose DA matches the MAC Address(#i) content is routed. If the PDC bit of.." newline hexmask.long.word 0xE0 0.--15. 1. "ADDRHI,MAC Address1 [47:32] This field contains the upper 16 bits[47:32] of the second 6-byte MAC address." line.long 0xE4 "MAC_ADDRESS28_LOW,The MAC Address1 Low register holds the lower 32 bits of the second 6-byte MAC address of the station." hexmask.long 0xE4 0.--31. 1. "ADDRLO,MAC Address1 [31:0] This field contains the lower 32 bits of second 6-byte MAC address. The content of this field is undefined until loaded by the application after the initialization process." line.long 0xE8 "MAC_ADDRESS29_HIGH,The MAC Address1 High register holds the upper 16 bits of the second 6-byte MAC address of the station. If the MAC address registers are configured to be double-synchronized to the (G)MII clock domains. the synchronization is triggered.." bitfld.long 0xE8 31. "AE,Address Enable When this bit is set the address filter module uses the second MAC address for perfect filtering. When this bit is reset the address filter module ignores the address for filtering. 0x0: Address is ignored 0x1: Address is enabled" "Address is ignored,Address is enabled" newline bitfld.long 0xE8 30. "SA,Source Address When this bit is set the MAC Address1[47:0] is used to compare with the SA fields of the received packet. When this bit is reset the MAC Address1[47:0] is used to compare with the DA fields of the received packet. 0x0: Compare with.." "Compare with Destination Address,Compare with Source Address" newline hexmask.long.byte 0xE8 24.--29. 1. "MBC,Mask Byte Control These bits are mask control bits for comparing each of the MAC Address bytes. When set high the MAC does not compare the corresponding byte of received DA or SA with the contents of MAC Address1 registers. Each bit controls the.." newline rbitfld.long 0xE8 21.--23. "RESERVED_23_Y,Reserved." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0xE8 16.--20. 1. "DCS,DMA Channel Select If the PDC bit of MAC_Ext_Configuration register is not set: This field contains the binary representation of the DMA Channel number to which an Rx packet whose DA matches the MAC Address(#i) content is routed. If the PDC bit of.." newline hexmask.long.word 0xE8 0.--15. 1. "ADDRHI,MAC Address1 [47:32] This field contains the upper 16 bits[47:32] of the second 6-byte MAC address." line.long 0xEC "MAC_ADDRESS29_LOW,The MAC Address1 Low register holds the lower 32 bits of the second 6-byte MAC address of the station." hexmask.long 0xEC 0.--31. 1. "ADDRLO,MAC Address1 [31:0] This field contains the lower 32 bits of second 6-byte MAC address. The content of this field is undefined until loaded by the application after the initialization process." line.long 0xF0 "MAC_ADDRESS30_HIGH,The MAC Address1 High register holds the upper 16 bits of the second 6-byte MAC address of the station. If the MAC address registers are configured to be double-synchronized to the (G)MII clock domains. the synchronization is triggered.." bitfld.long 0xF0 31. "AE,Address Enable When this bit is set the address filter module uses the second MAC address for perfect filtering. When this bit is reset the address filter module ignores the address for filtering. 0x0: Address is ignored 0x1: Address is enabled" "Address is ignored,Address is enabled" newline bitfld.long 0xF0 30. "SA,Source Address When this bit is set the MAC Address1[47:0] is used to compare with the SA fields of the received packet. When this bit is reset the MAC Address1[47:0] is used to compare with the DA fields of the received packet. 0x0: Compare with.." "Compare with Destination Address,Compare with Source Address" newline hexmask.long.byte 0xF0 24.--29. 1. "MBC,Mask Byte Control These bits are mask control bits for comparing each of the MAC Address bytes. When set high the MAC does not compare the corresponding byte of received DA or SA with the contents of MAC Address1 registers. Each bit controls the.." newline rbitfld.long 0xF0 21.--23. "RESERVED_23_Y,Reserved." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0xF0 16.--20. 1. "DCS,DMA Channel Select If the PDC bit of MAC_Ext_Configuration register is not set: This field contains the binary representation of the DMA Channel number to which an Rx packet whose DA matches the MAC Address(#i) content is routed. If the PDC bit of.." newline hexmask.long.word 0xF0 0.--15. 1. "ADDRHI,MAC Address1 [47:32] This field contains the upper 16 bits[47:32] of the second 6-byte MAC address." line.long 0xF4 "MAC_ADDRESS30_LOW,The MAC Address1 Low register holds the lower 32 bits of the second 6-byte MAC address of the station." hexmask.long 0xF4 0.--31. 1. "ADDRLO,MAC Address1 [31:0] This field contains the lower 32 bits of second 6-byte MAC address. The content of this field is undefined until loaded by the application after the initialization process." line.long 0xF8 "MAC_ADDRESS31_HIGH,The MAC Address1 High register holds the upper 16 bits of the second 6-byte MAC address of the station. If the MAC address registers are configured to be double-synchronized to the (G)MII clock domains. the synchronization is triggered.." bitfld.long 0xF8 31. "AE,Address Enable When this bit is set the address filter module uses the second MAC address for perfect filtering. When this bit is reset the address filter module ignores the address for filtering. 0x0: Address is ignored 0x1: Address is enabled" "Address is ignored,Address is enabled" newline bitfld.long 0xF8 30. "SA,Source Address When this bit is set the MAC Address1[47:0] is used to compare with the SA fields of the received packet. When this bit is reset the MAC Address1[47:0] is used to compare with the DA fields of the received packet. 0x0: Compare with.." "Compare with Destination Address,Compare with Source Address" newline hexmask.long.byte 0xF8 24.--29. 1. "MBC,Mask Byte Control These bits are mask control bits for comparing each of the MAC Address bytes. When set high the MAC does not compare the corresponding byte of received DA or SA with the contents of MAC Address1 registers. Each bit controls the.." newline rbitfld.long 0xF8 21.--23. "RESERVED_23_Y,Reserved." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0xF8 16.--20. 1. "DCS,DMA Channel Select If the PDC bit of MAC_Ext_Configuration register is not set: This field contains the binary representation of the DMA Channel number to which an Rx packet whose DA matches the MAC Address(#i) content is routed. If the PDC bit of.." newline hexmask.long.word 0xF8 0.--15. 1. "ADDRHI,MAC Address1 [47:32] This field contains the upper 16 bits[47:32] of the second 6-byte MAC address." line.long 0xFC "MAC_ADDRESS31_LOW,The MAC Address1 Low register holds the lower 32 bits of the second 6-byte MAC address of the station." hexmask.long 0xFC 0.--31. 1. "ADDRLO,MAC Address1 [31:0] This field contains the lower 32 bits of second 6-byte MAC address. The content of this field is undefined until loaded by the application after the initialization process." line.long 0x100 "MAC_ADDRESS32_HIGH,The MAC Address32 High register holds the upper 16 bits of the 33rd 6-byte MAC address of the station. If the MAC address registers are configured to be double-synchronized to the (G)MII clock domains. the synchronization is triggered.." bitfld.long 0x100 31. "AE,Address Enable When this bit is set the Address filter module uses the 33rd MAC address for perfect filtering. When this bit is reset the address filter module ignores the address for filtering. 0x0: Address is ignored 0x1: Address is enabled" "Address is ignored,Address is enabled" newline hexmask.long.word 0x100 19.--30. 1. "RESERVED_30_Y,Reserved." newline bitfld.long 0x100 16.--18. "DCS,DMA Channel Select This field contains the DMA Channel number to which an Rx packet whose DA matches the MAC Address32 content is routed." "0,1,2,3,4,5,6,7" newline hexmask.long.word 0x100 0.--15. 1. "ADDRHI,MAC Address32 [47:32] This field contains the upper 16 bits (47:32) of the 33rd 6-byte MAC address." line.long 0x104 "MAC_ADDRESS32_LOW,The MAC Address32 Low register holds the lower 16 bits of the 33rd 6-byte MAC address of the station." hexmask.long 0x104 0.--31. 1. "ADDRLO,MAC Address32 [31:0] This field contains the lower 32 bits of the 33rd 6-byte MAC address. The content of this field is undefined until loaded by the Application after the initialization process." line.long 0x108 "MAC_ADDRESS33_HIGH,The MAC Address32 High register holds the upper 16 bits of the 33rd 6-byte MAC address of the station. If the MAC address registers are configured to be double-synchronized to the (G)MII clock domains. the synchronization is triggered.." bitfld.long 0x108 31. "AE,Address Enable When this bit is set the Address filter module uses the 33rd MAC address for perfect filtering. When this bit is reset the address filter module ignores the address for filtering. 0x0: Address is ignored 0x1: Address is enabled" "Address is ignored,Address is enabled" newline hexmask.long.word 0x108 19.--30. 1. "RESERVED_30_Y,Reserved." newline bitfld.long 0x108 16.--18. "DCS,DMA Channel Select This field contains the DMA Channel number to which an Rx packet whose DA matches the MAC Address32 content is routed." "0,1,2,3,4,5,6,7" newline hexmask.long.word 0x108 0.--15. 1. "ADDRHI,MAC Address32 [47:32] This field contains the upper 16 bits (47:32) of the 33rd 6-byte MAC address." line.long 0x10C "MAC_ADDRESS33_LOW,The MAC Address32 Low register holds the lower 16 bits of the 33rd 6-byte MAC address of the station." hexmask.long 0x10C 0.--31. 1. "ADDRLO,MAC Address32 [31:0] This field contains the lower 32 bits of the 33rd 6-byte MAC address. The content of this field is undefined until loaded by the Application after the initialization process." line.long 0x110 "MAC_ADDRESS34_HIGH,The MAC Address32 High register holds the upper 16 bits of the 33rd 6-byte MAC address of the station. If the MAC address registers are configured to be double-synchronized to the (G)MII clock domains. the synchronization is triggered.." bitfld.long 0x110 31. "AE,Address Enable When this bit is set the Address filter module uses the 33rd MAC address for perfect filtering. When this bit is reset the address filter module ignores the address for filtering. 0x0: Address is ignored 0x1: Address is enabled" "Address is ignored,Address is enabled" newline hexmask.long.word 0x110 19.--30. 1. "RESERVED_30_Y,Reserved." newline bitfld.long 0x110 16.--18. "DCS,DMA Channel Select This field contains the DMA Channel number to which an Rx packet whose DA matches the MAC Address32 content is routed." "0,1,2,3,4,5,6,7" newline hexmask.long.word 0x110 0.--15. 1. "ADDRHI,MAC Address32 [47:32] This field contains the upper 16 bits (47:32) of the 33rd 6-byte MAC address." line.long 0x114 "MAC_ADDRESS34_LOW,The MAC Address32 Low register holds the lower 16 bits of the 33rd 6-byte MAC address of the station." hexmask.long 0x114 0.--31. 1. "ADDRLO,MAC Address32 [31:0] This field contains the lower 32 bits of the 33rd 6-byte MAC address. The content of this field is undefined until loaded by the Application after the initialization process." line.long 0x118 "MAC_ADDRESS35_HIGH,The MAC Address32 High register holds the upper 16 bits of the 33rd 6-byte MAC address of the station. If the MAC address registers are configured to be double-synchronized to the (G)MII clock domains. the synchronization is triggered.." bitfld.long 0x118 31. "AE,Address Enable When this bit is set the Address filter module uses the 33rd MAC address for perfect filtering. When this bit is reset the address filter module ignores the address for filtering. 0x0: Address is ignored 0x1: Address is enabled" "Address is ignored,Address is enabled" newline hexmask.long.word 0x118 19.--30. 1. "RESERVED_30_Y,Reserved." newline bitfld.long 0x118 16.--18. "DCS,DMA Channel Select This field contains the DMA Channel number to which an Rx packet whose DA matches the MAC Address32 content is routed." "0,1,2,3,4,5,6,7" newline hexmask.long.word 0x118 0.--15. 1. "ADDRHI,MAC Address32 [47:32] This field contains the upper 16 bits (47:32) of the 33rd 6-byte MAC address." line.long 0x11C "MAC_ADDRESS35_LOW,The MAC Address32 Low register holds the lower 16 bits of the 33rd 6-byte MAC address of the station." hexmask.long 0x11C 0.--31. 1. "ADDRLO,MAC Address32 [31:0] This field contains the lower 32 bits of the 33rd 6-byte MAC address. The content of this field is undefined until loaded by the Application after the initialization process." line.long 0x120 "MAC_ADDRESS36_HIGH,The MAC Address32 High register holds the upper 16 bits of the 33rd 6-byte MAC address of the station. If the MAC address registers are configured to be double-synchronized to the (G)MII clock domains. the synchronization is triggered.." bitfld.long 0x120 31. "AE,Address Enable When this bit is set the Address filter module uses the 33rd MAC address for perfect filtering. When this bit is reset the address filter module ignores the address for filtering. 0x0: Address is ignored 0x1: Address is enabled" "Address is ignored,Address is enabled" newline hexmask.long.word 0x120 19.--30. 1. "RESERVED_30_Y,Reserved." newline bitfld.long 0x120 16.--18. "DCS,DMA Channel Select This field contains the DMA Channel number to which an Rx packet whose DA matches the MAC Address32 content is routed." "0,1,2,3,4,5,6,7" newline hexmask.long.word 0x120 0.--15. 1. "ADDRHI,MAC Address32 [47:32] This field contains the upper 16 bits (47:32) of the 33rd 6-byte MAC address." line.long 0x124 "MAC_ADDRESS36_LOW,The MAC Address32 Low register holds the lower 16 bits of the 33rd 6-byte MAC address of the station." hexmask.long 0x124 0.--31. 1. "ADDRLO,MAC Address32 [31:0] This field contains the lower 32 bits of the 33rd 6-byte MAC address. The content of this field is undefined until loaded by the Application after the initialization process." line.long 0x128 "MAC_ADDRESS37_HIGH,The MAC Address32 High register holds the upper 16 bits of the 33rd 6-byte MAC address of the station. If the MAC address registers are configured to be double-synchronized to the (G)MII clock domains. the synchronization is triggered.." bitfld.long 0x128 31. "AE,Address Enable When this bit is set the Address filter module uses the 33rd MAC address for perfect filtering. When this bit is reset the address filter module ignores the address for filtering. 0x0: Address is ignored 0x1: Address is enabled" "Address is ignored,Address is enabled" newline hexmask.long.word 0x128 19.--30. 1. "RESERVED_30_Y,Reserved." newline bitfld.long 0x128 16.--18. "DCS,DMA Channel Select This field contains the DMA Channel number to which an Rx packet whose DA matches the MAC Address32 content is routed." "0,1,2,3,4,5,6,7" newline hexmask.long.word 0x128 0.--15. 1. "ADDRHI,MAC Address32 [47:32] This field contains the upper 16 bits (47:32) of the 33rd 6-byte MAC address." line.long 0x12C "MAC_ADDRESS37_LOW,The MAC Address32 Low register holds the lower 16 bits of the 33rd 6-byte MAC address of the station." hexmask.long 0x12C 0.--31. 1. "ADDRLO,MAC Address32 [31:0] This field contains the lower 32 bits of the 33rd 6-byte MAC address. The content of this field is undefined until loaded by the Application after the initialization process." line.long 0x130 "MAC_ADDRESS38_HIGH,The MAC Address32 High register holds the upper 16 bits of the 33rd 6-byte MAC address of the station. If the MAC address registers are configured to be double-synchronized to the (G)MII clock domains. the synchronization is triggered.." bitfld.long 0x130 31. "AE,Address Enable When this bit is set the Address filter module uses the 33rd MAC address for perfect filtering. When this bit is reset the address filter module ignores the address for filtering. 0x0: Address is ignored 0x1: Address is enabled" "Address is ignored,Address is enabled" newline hexmask.long.word 0x130 19.--30. 1. "RESERVED_30_Y,Reserved." newline bitfld.long 0x130 16.--18. "DCS,DMA Channel Select This field contains the DMA Channel number to which an Rx packet whose DA matches the MAC Address32 content is routed." "0,1,2,3,4,5,6,7" newline hexmask.long.word 0x130 0.--15. 1. "ADDRHI,MAC Address32 [47:32] This field contains the upper 16 bits (47:32) of the 33rd 6-byte MAC address." line.long 0x134 "MAC_ADDRESS38_LOW,The MAC Address32 Low register holds the lower 16 bits of the 33rd 6-byte MAC address of the station." hexmask.long 0x134 0.--31. 1. "ADDRLO,MAC Address32 [31:0] This field contains the lower 32 bits of the 33rd 6-byte MAC address. The content of this field is undefined until loaded by the Application after the initialization process." line.long 0x138 "MAC_ADDRESS39_HIGH,The MAC Address32 High register holds the upper 16 bits of the 33rd 6-byte MAC address of the station. If the MAC address registers are configured to be double-synchronized to the (G)MII clock domains. the synchronization is triggered.." bitfld.long 0x138 31. "AE,Address Enable When this bit is set the Address filter module uses the 33rd MAC address for perfect filtering. When this bit is reset the address filter module ignores the address for filtering. 0x0: Address is ignored 0x1: Address is enabled" "Address is ignored,Address is enabled" newline hexmask.long.word 0x138 19.--30. 1. "RESERVED_30_Y,Reserved." newline bitfld.long 0x138 16.--18. "DCS,DMA Channel Select This field contains the DMA Channel number to which an Rx packet whose DA matches the MAC Address32 content is routed." "0,1,2,3,4,5,6,7" newline hexmask.long.word 0x138 0.--15. 1. "ADDRHI,MAC Address32 [47:32] This field contains the upper 16 bits (47:32) of the 33rd 6-byte MAC address." line.long 0x13C "MAC_ADDRESS39_LOW,The MAC Address32 Low register holds the lower 16 bits of the 33rd 6-byte MAC address of the station." hexmask.long 0x13C 0.--31. 1. "ADDRLO,MAC Address32 [31:0] This field contains the lower 32 bits of the 33rd 6-byte MAC address. The content of this field is undefined until loaded by the Application after the initialization process." line.long 0x140 "MAC_ADDRESS40_HIGH,The MAC Address32 High register holds the upper 16 bits of the 33rd 6-byte MAC address of the station. If the MAC address registers are configured to be double-synchronized to the (G)MII clock domains. the synchronization is triggered.." bitfld.long 0x140 31. "AE,Address Enable When this bit is set the Address filter module uses the 33rd MAC address for perfect filtering. When this bit is reset the address filter module ignores the address for filtering. 0x0: Address is ignored 0x1: Address is enabled" "Address is ignored,Address is enabled" newline hexmask.long.word 0x140 19.--30. 1. "RESERVED_30_Y,Reserved." newline bitfld.long 0x140 16.--18. "DCS,DMA Channel Select This field contains the DMA Channel number to which an Rx packet whose DA matches the MAC Address32 content is routed." "0,1,2,3,4,5,6,7" newline hexmask.long.word 0x140 0.--15. 1. "ADDRHI,MAC Address32 [47:32] This field contains the upper 16 bits (47:32) of the 33rd 6-byte MAC address." line.long 0x144 "MAC_ADDRESS40_LOW,The MAC Address32 Low register holds the lower 16 bits of the 33rd 6-byte MAC address of the station." hexmask.long 0x144 0.--31. 1. "ADDRLO,MAC Address32 [31:0] This field contains the lower 32 bits of the 33rd 6-byte MAC address. The content of this field is undefined until loaded by the Application after the initialization process." line.long 0x148 "MAC_ADDRESS41_HIGH,The MAC Address32 High register holds the upper 16 bits of the 33rd 6-byte MAC address of the station. If the MAC address registers are configured to be double-synchronized to the (G)MII clock domains. the synchronization is triggered.." bitfld.long 0x148 31. "AE,Address Enable When this bit is set the Address filter module uses the 33rd MAC address for perfect filtering. When this bit is reset the address filter module ignores the address for filtering. 0x0: Address is ignored 0x1: Address is enabled" "Address is ignored,Address is enabled" newline hexmask.long.word 0x148 19.--30. 1. "RESERVED_30_Y,Reserved." newline bitfld.long 0x148 16.--18. "DCS,DMA Channel Select This field contains the DMA Channel number to which an Rx packet whose DA matches the MAC Address32 content is routed." "0,1,2,3,4,5,6,7" newline hexmask.long.word 0x148 0.--15. 1. "ADDRHI,MAC Address32 [47:32] This field contains the upper 16 bits (47:32) of the 33rd 6-byte MAC address." line.long 0x14C "MAC_ADDRESS41_LOW,The MAC Address32 Low register holds the lower 16 bits of the 33rd 6-byte MAC address of the station." hexmask.long 0x14C 0.--31. 1. "ADDRLO,MAC Address32 [31:0] This field contains the lower 32 bits of the 33rd 6-byte MAC address. The content of this field is undefined until loaded by the Application after the initialization process." line.long 0x150 "MAC_ADDRESS42_HIGH,The MAC Address32 High register holds the upper 16 bits of the 33rd 6-byte MAC address of the station. If the MAC address registers are configured to be double-synchronized to the (G)MII clock domains. the synchronization is triggered.." bitfld.long 0x150 31. "AE,Address Enable When this bit is set the Address filter module uses the 33rd MAC address for perfect filtering. When this bit is reset the address filter module ignores the address for filtering. 0x0: Address is ignored 0x1: Address is enabled" "Address is ignored,Address is enabled" newline hexmask.long.word 0x150 19.--30. 1. "RESERVED_30_Y,Reserved." newline bitfld.long 0x150 16.--18. "DCS,DMA Channel Select This field contains the DMA Channel number to which an Rx packet whose DA matches the MAC Address32 content is routed." "0,1,2,3,4,5,6,7" newline hexmask.long.word 0x150 0.--15. 1. "ADDRHI,MAC Address32 [47:32] This field contains the upper 16 bits (47:32) of the 33rd 6-byte MAC address." line.long 0x154 "MAC_ADDRESS42_LOW,The MAC Address32 Low register holds the lower 16 bits of the 33rd 6-byte MAC address of the station." hexmask.long 0x154 0.--31. 1. "ADDRLO,MAC Address32 [31:0] This field contains the lower 32 bits of the 33rd 6-byte MAC address. The content of this field is undefined until loaded by the Application after the initialization process." line.long 0x158 "MAC_ADDRESS43_HIGH,The MAC Address32 High register holds the upper 16 bits of the 33rd 6-byte MAC address of the station. If the MAC address registers are configured to be double-synchronized to the (G)MII clock domains. the synchronization is triggered.." bitfld.long 0x158 31. "AE,Address Enable When this bit is set the Address filter module uses the 33rd MAC address for perfect filtering. When this bit is reset the address filter module ignores the address for filtering. 0x0: Address is ignored 0x1: Address is enabled" "Address is ignored,Address is enabled" newline hexmask.long.word 0x158 19.--30. 1. "RESERVED_30_Y,Reserved." newline bitfld.long 0x158 16.--18. "DCS,DMA Channel Select This field contains the DMA Channel number to which an Rx packet whose DA matches the MAC Address32 content is routed." "0,1,2,3,4,5,6,7" newline hexmask.long.word 0x158 0.--15. 1. "ADDRHI,MAC Address32 [47:32] This field contains the upper 16 bits (47:32) of the 33rd 6-byte MAC address." line.long 0x15C "MAC_ADDRESS43_LOW,The MAC Address32 Low register holds the lower 16 bits of the 33rd 6-byte MAC address of the station." hexmask.long 0x15C 0.--31. 1. "ADDRLO,MAC Address32 [31:0] This field contains the lower 32 bits of the 33rd 6-byte MAC address. The content of this field is undefined until loaded by the Application after the initialization process." line.long 0x160 "MAC_ADDRESS44_HIGH,The MAC Address32 High register holds the upper 16 bits of the 33rd 6-byte MAC address of the station. If the MAC address registers are configured to be double-synchronized to the (G)MII clock domains. the synchronization is triggered.." bitfld.long 0x160 31. "AE,Address Enable When this bit is set the Address filter module uses the 33rd MAC address for perfect filtering. When this bit is reset the address filter module ignores the address for filtering. 0x0: Address is ignored 0x1: Address is enabled" "Address is ignored,Address is enabled" newline hexmask.long.word 0x160 19.--30. 1. "RESERVED_30_Y,Reserved." newline bitfld.long 0x160 16.--18. "DCS,DMA Channel Select This field contains the DMA Channel number to which an Rx packet whose DA matches the MAC Address32 content is routed." "0,1,2,3,4,5,6,7" newline hexmask.long.word 0x160 0.--15. 1. "ADDRHI,MAC Address32 [47:32] This field contains the upper 16 bits (47:32) of the 33rd 6-byte MAC address." line.long 0x164 "MAC_ADDRESS44_LOW,The MAC Address32 Low register holds the lower 16 bits of the 33rd 6-byte MAC address of the station." hexmask.long 0x164 0.--31. 1. "ADDRLO,MAC Address32 [31:0] This field contains the lower 32 bits of the 33rd 6-byte MAC address. The content of this field is undefined until loaded by the Application after the initialization process." line.long 0x168 "MAC_ADDRESS45_HIGH,The MAC Address32 High register holds the upper 16 bits of the 33rd 6-byte MAC address of the station. If the MAC address registers are configured to be double-synchronized to the (G)MII clock domains. the synchronization is triggered.." bitfld.long 0x168 31. "AE,Address Enable When this bit is set the Address filter module uses the 33rd MAC address for perfect filtering. When this bit is reset the address filter module ignores the address for filtering. 0x0: Address is ignored 0x1: Address is enabled" "Address is ignored,Address is enabled" newline hexmask.long.word 0x168 19.--30. 1. "RESERVED_30_Y,Reserved." newline bitfld.long 0x168 16.--18. "DCS,DMA Channel Select This field contains the DMA Channel number to which an Rx packet whose DA matches the MAC Address32 content is routed." "0,1,2,3,4,5,6,7" newline hexmask.long.word 0x168 0.--15. 1. "ADDRHI,MAC Address32 [47:32] This field contains the upper 16 bits (47:32) of the 33rd 6-byte MAC address." line.long 0x16C "MAC_ADDRESS45_LOW,The MAC Address32 Low register holds the lower 16 bits of the 33rd 6-byte MAC address of the station." hexmask.long 0x16C 0.--31. 1. "ADDRLO,MAC Address32 [31:0] This field contains the lower 32 bits of the 33rd 6-byte MAC address. The content of this field is undefined until loaded by the Application after the initialization process." line.long 0x170 "MAC_ADDRESS46_HIGH,The MAC Address32 High register holds the upper 16 bits of the 33rd 6-byte MAC address of the station. If the MAC address registers are configured to be double-synchronized to the (G)MII clock domains. the synchronization is triggered.." bitfld.long 0x170 31. "AE,Address Enable When this bit is set the Address filter module uses the 33rd MAC address for perfect filtering. When this bit is reset the address filter module ignores the address for filtering. 0x0: Address is ignored 0x1: Address is enabled" "Address is ignored,Address is enabled" newline hexmask.long.word 0x170 19.--30. 1. "RESERVED_30_Y,Reserved." newline bitfld.long 0x170 16.--18. "DCS,DMA Channel Select This field contains the DMA Channel number to which an Rx packet whose DA matches the MAC Address32 content is routed." "0,1,2,3,4,5,6,7" newline hexmask.long.word 0x170 0.--15. 1. "ADDRHI,MAC Address32 [47:32] This field contains the upper 16 bits (47:32) of the 33rd 6-byte MAC address." line.long 0x174 "MAC_ADDRESS46_LOW,The MAC Address32 Low register holds the lower 16 bits of the 33rd 6-byte MAC address of the station." hexmask.long 0x174 0.--31. 1. "ADDRLO,MAC Address32 [31:0] This field contains the lower 32 bits of the 33rd 6-byte MAC address. The content of this field is undefined until loaded by the Application after the initialization process." line.long 0x178 "MAC_ADDRESS47_HIGH,The MAC Address32 High register holds the upper 16 bits of the 33rd 6-byte MAC address of the station. If the MAC address registers are configured to be double-synchronized to the (G)MII clock domains. the synchronization is triggered.." bitfld.long 0x178 31. "AE,Address Enable When this bit is set the Address filter module uses the 33rd MAC address for perfect filtering. When this bit is reset the address filter module ignores the address for filtering. 0x0: Address is ignored 0x1: Address is enabled" "Address is ignored,Address is enabled" newline hexmask.long.word 0x178 19.--30. 1. "RESERVED_30_Y,Reserved." newline bitfld.long 0x178 16.--18. "DCS,DMA Channel Select This field contains the DMA Channel number to which an Rx packet whose DA matches the MAC Address32 content is routed." "0,1,2,3,4,5,6,7" newline hexmask.long.word 0x178 0.--15. 1. "ADDRHI,MAC Address32 [47:32] This field contains the upper 16 bits (47:32) of the 33rd 6-byte MAC address." line.long 0x17C "MAC_ADDRESS47_LOW,The MAC Address32 Low register holds the lower 16 bits of the 33rd 6-byte MAC address of the station." hexmask.long 0x17C 0.--31. 1. "ADDRLO,MAC Address32 [31:0] This field contains the lower 32 bits of the 33rd 6-byte MAC address. The content of this field is undefined until loaded by the Application after the initialization process." line.long 0x180 "MAC_ADDRESS48_HIGH,The MAC Address32 High register holds the upper 16 bits of the 33rd 6-byte MAC address of the station. If the MAC address registers are configured to be double-synchronized to the (G)MII clock domains. the synchronization is triggered.." bitfld.long 0x180 31. "AE,Address Enable When this bit is set the Address filter module uses the 33rd MAC address for perfect filtering. When this bit is reset the address filter module ignores the address for filtering. 0x0: Address is ignored 0x1: Address is enabled" "Address is ignored,Address is enabled" newline hexmask.long.word 0x180 19.--30. 1. "RESERVED_30_Y,Reserved." newline bitfld.long 0x180 16.--18. "DCS,DMA Channel Select This field contains the DMA Channel number to which an Rx packet whose DA matches the MAC Address32 content is routed." "0,1,2,3,4,5,6,7" newline hexmask.long.word 0x180 0.--15. 1. "ADDRHI,MAC Address32 [47:32] This field contains the upper 16 bits (47:32) of the 33rd 6-byte MAC address." line.long 0x184 "MAC_ADDRESS48_LOW,The MAC Address32 Low register holds the lower 16 bits of the 33rd 6-byte MAC address of the station." hexmask.long 0x184 0.--31. 1. "ADDRLO,MAC Address32 [31:0] This field contains the lower 32 bits of the 33rd 6-byte MAC address. The content of this field is undefined until loaded by the Application after the initialization process." line.long 0x188 "MAC_ADDRESS49_HIGH,The MAC Address32 High register holds the upper 16 bits of the 33rd 6-byte MAC address of the station. If the MAC address registers are configured to be double-synchronized to the (G)MII clock domains. the synchronization is triggered.." bitfld.long 0x188 31. "AE,Address Enable When this bit is set the Address filter module uses the 33rd MAC address for perfect filtering. When this bit is reset the address filter module ignores the address for filtering. 0x0: Address is ignored 0x1: Address is enabled" "Address is ignored,Address is enabled" newline hexmask.long.word 0x188 19.--30. 1. "RESERVED_30_Y,Reserved." newline bitfld.long 0x188 16.--18. "DCS,DMA Channel Select This field contains the DMA Channel number to which an Rx packet whose DA matches the MAC Address32 content is routed." "0,1,2,3,4,5,6,7" newline hexmask.long.word 0x188 0.--15. 1. "ADDRHI,MAC Address32 [47:32] This field contains the upper 16 bits (47:32) of the 33rd 6-byte MAC address." line.long 0x18C "MAC_ADDRESS49_LOW,The MAC Address32 Low register holds the lower 16 bits of the 33rd 6-byte MAC address of the station." hexmask.long 0x18C 0.--31. 1. "ADDRLO,MAC Address32 [31:0] This field contains the lower 32 bits of the 33rd 6-byte MAC address. The content of this field is undefined until loaded by the Application after the initialization process." line.long 0x190 "MAC_ADDRESS50_HIGH,The MAC Address32 High register holds the upper 16 bits of the 33rd 6-byte MAC address of the station. If the MAC address registers are configured to be double-synchronized to the (G)MII clock domains. the synchronization is triggered.." bitfld.long 0x190 31. "AE,Address Enable When this bit is set the Address filter module uses the 33rd MAC address for perfect filtering. When this bit is reset the address filter module ignores the address for filtering. 0x0: Address is ignored 0x1: Address is enabled" "Address is ignored,Address is enabled" newline hexmask.long.word 0x190 19.--30. 1. "RESERVED_30_Y,Reserved." newline bitfld.long 0x190 16.--18. "DCS,DMA Channel Select This field contains the DMA Channel number to which an Rx packet whose DA matches the MAC Address32 content is routed." "0,1,2,3,4,5,6,7" newline hexmask.long.word 0x190 0.--15. 1. "ADDRHI,MAC Address32 [47:32] This field contains the upper 16 bits (47:32) of the 33rd 6-byte MAC address." line.long 0x194 "MAC_ADDRESS50_LOW,The MAC Address32 Low register holds the lower 16 bits of the 33rd 6-byte MAC address of the station." hexmask.long 0x194 0.--31. 1. "ADDRLO,MAC Address32 [31:0] This field contains the lower 32 bits of the 33rd 6-byte MAC address. The content of this field is undefined until loaded by the Application after the initialization process." line.long 0x198 "MAC_ADDRESS51_HIGH,The MAC Address32 High register holds the upper 16 bits of the 33rd 6-byte MAC address of the station. If the MAC address registers are configured to be double-synchronized to the (G)MII clock domains. the synchronization is triggered.." bitfld.long 0x198 31. "AE,Address Enable When this bit is set the Address filter module uses the 33rd MAC address for perfect filtering. When this bit is reset the address filter module ignores the address for filtering. 0x0: Address is ignored 0x1: Address is enabled" "Address is ignored,Address is enabled" newline hexmask.long.word 0x198 19.--30. 1. "RESERVED_30_Y,Reserved." newline bitfld.long 0x198 16.--18. "DCS,DMA Channel Select This field contains the DMA Channel number to which an Rx packet whose DA matches the MAC Address32 content is routed." "0,1,2,3,4,5,6,7" newline hexmask.long.word 0x198 0.--15. 1. "ADDRHI,MAC Address32 [47:32] This field contains the upper 16 bits (47:32) of the 33rd 6-byte MAC address." line.long 0x19C "MAC_ADDRESS51_LOW,The MAC Address32 Low register holds the lower 16 bits of the 33rd 6-byte MAC address of the station." hexmask.long 0x19C 0.--31. 1. "ADDRLO,MAC Address32 [31:0] This field contains the lower 32 bits of the 33rd 6-byte MAC address. The content of this field is undefined until loaded by the Application after the initialization process." line.long 0x1A0 "MAC_ADDRESS52_HIGH,The MAC Address32 High register holds the upper 16 bits of the 33rd 6-byte MAC address of the station. If the MAC address registers are configured to be double-synchronized to the (G)MII clock domains. the synchronization is triggered.." bitfld.long 0x1A0 31. "AE,Address Enable When this bit is set the Address filter module uses the 33rd MAC address for perfect filtering. When this bit is reset the address filter module ignores the address for filtering. 0x0: Address is ignored 0x1: Address is enabled" "Address is ignored,Address is enabled" newline hexmask.long.word 0x1A0 19.--30. 1. "RESERVED_30_Y,Reserved." newline bitfld.long 0x1A0 16.--18. "DCS,DMA Channel Select This field contains the DMA Channel number to which an Rx packet whose DA matches the MAC Address32 content is routed." "0,1,2,3,4,5,6,7" newline hexmask.long.word 0x1A0 0.--15. 1. "ADDRHI,MAC Address32 [47:32] This field contains the upper 16 bits (47:32) of the 33rd 6-byte MAC address." line.long 0x1A4 "MAC_ADDRESS52_LOW,The MAC Address32 Low register holds the lower 16 bits of the 33rd 6-byte MAC address of the station." hexmask.long 0x1A4 0.--31. 1. "ADDRLO,MAC Address32 [31:0] This field contains the lower 32 bits of the 33rd 6-byte MAC address. The content of this field is undefined until loaded by the Application after the initialization process." line.long 0x1A8 "MAC_ADDRESS53_HIGH,The MAC Address32 High register holds the upper 16 bits of the 33rd 6-byte MAC address of the station. If the MAC address registers are configured to be double-synchronized to the (G)MII clock domains. the synchronization is triggered.." bitfld.long 0x1A8 31. "AE,Address Enable When this bit is set the Address filter module uses the 33rd MAC address for perfect filtering. When this bit is reset the address filter module ignores the address for filtering. 0x0: Address is ignored 0x1: Address is enabled" "Address is ignored,Address is enabled" newline hexmask.long.word 0x1A8 19.--30. 1. "RESERVED_30_Y,Reserved." newline bitfld.long 0x1A8 16.--18. "DCS,DMA Channel Select This field contains the DMA Channel number to which an Rx packet whose DA matches the MAC Address32 content is routed." "0,1,2,3,4,5,6,7" newline hexmask.long.word 0x1A8 0.--15. 1. "ADDRHI,MAC Address32 [47:32] This field contains the upper 16 bits (47:32) of the 33rd 6-byte MAC address." line.long 0x1AC "MAC_ADDRESS53_LOW,The MAC Address32 Low register holds the lower 16 bits of the 33rd 6-byte MAC address of the station." hexmask.long 0x1AC 0.--31. 1. "ADDRLO,MAC Address32 [31:0] This field contains the lower 32 bits of the 33rd 6-byte MAC address. The content of this field is undefined until loaded by the Application after the initialization process." line.long 0x1B0 "MAC_ADDRESS54_HIGH,The MAC Address32 High register holds the upper 16 bits of the 33rd 6-byte MAC address of the station. If the MAC address registers are configured to be double-synchronized to the (G)MII clock domains. the synchronization is triggered.." bitfld.long 0x1B0 31. "AE,Address Enable When this bit is set the Address filter module uses the 33rd MAC address for perfect filtering. When this bit is reset the address filter module ignores the address for filtering. 0x0: Address is ignored 0x1: Address is enabled" "Address is ignored,Address is enabled" newline hexmask.long.word 0x1B0 19.--30. 1. "RESERVED_30_Y,Reserved." newline bitfld.long 0x1B0 16.--18. "DCS,DMA Channel Select This field contains the DMA Channel number to which an Rx packet whose DA matches the MAC Address32 content is routed." "0,1,2,3,4,5,6,7" newline hexmask.long.word 0x1B0 0.--15. 1. "ADDRHI,MAC Address32 [47:32] This field contains the upper 16 bits (47:32) of the 33rd 6-byte MAC address." line.long 0x1B4 "MAC_ADDRESS54_LOW,The MAC Address32 Low register holds the lower 16 bits of the 33rd 6-byte MAC address of the station." hexmask.long 0x1B4 0.--31. 1. "ADDRLO,MAC Address32 [31:0] This field contains the lower 32 bits of the 33rd 6-byte MAC address. The content of this field is undefined until loaded by the Application after the initialization process." line.long 0x1B8 "MAC_ADDRESS55_HIGH,The MAC Address32 High register holds the upper 16 bits of the 33rd 6-byte MAC address of the station. If the MAC address registers are configured to be double-synchronized to the (G)MII clock domains. the synchronization is triggered.." bitfld.long 0x1B8 31. "AE,Address Enable When this bit is set the Address filter module uses the 33rd MAC address for perfect filtering. When this bit is reset the address filter module ignores the address for filtering. 0x0: Address is ignored 0x1: Address is enabled" "Address is ignored,Address is enabled" newline hexmask.long.word 0x1B8 19.--30. 1. "RESERVED_30_Y,Reserved." newline bitfld.long 0x1B8 16.--18. "DCS,DMA Channel Select This field contains the DMA Channel number to which an Rx packet whose DA matches the MAC Address32 content is routed." "0,1,2,3,4,5,6,7" newline hexmask.long.word 0x1B8 0.--15. 1. "ADDRHI,MAC Address32 [47:32] This field contains the upper 16 bits (47:32) of the 33rd 6-byte MAC address." line.long 0x1BC "MAC_ADDRESS55_LOW,The MAC Address32 Low register holds the lower 16 bits of the 33rd 6-byte MAC address of the station." hexmask.long 0x1BC 0.--31. 1. "ADDRLO,MAC Address32 [31:0] This field contains the lower 32 bits of the 33rd 6-byte MAC address. The content of this field is undefined until loaded by the Application after the initialization process." line.long 0x1C0 "MAC_ADDRESS56_HIGH,The MAC Address32 High register holds the upper 16 bits of the 33rd 6-byte MAC address of the station. If the MAC address registers are configured to be double-synchronized to the (G)MII clock domains. the synchronization is triggered.." bitfld.long 0x1C0 31. "AE,Address Enable When this bit is set the Address filter module uses the 33rd MAC address for perfect filtering. When this bit is reset the address filter module ignores the address for filtering. 0x0: Address is ignored 0x1: Address is enabled" "Address is ignored,Address is enabled" newline hexmask.long.word 0x1C0 19.--30. 1. "RESERVED_30_Y,Reserved." newline bitfld.long 0x1C0 16.--18. "DCS,DMA Channel Select This field contains the DMA Channel number to which an Rx packet whose DA matches the MAC Address32 content is routed." "0,1,2,3,4,5,6,7" newline hexmask.long.word 0x1C0 0.--15. 1. "ADDRHI,MAC Address32 [47:32] This field contains the upper 16 bits (47:32) of the 33rd 6-byte MAC address." line.long 0x1C4 "MAC_ADDRESS56_LOW,The MAC Address32 Low register holds the lower 16 bits of the 33rd 6-byte MAC address of the station." hexmask.long 0x1C4 0.--31. 1. "ADDRLO,MAC Address32 [31:0] This field contains the lower 32 bits of the 33rd 6-byte MAC address. The content of this field is undefined until loaded by the Application after the initialization process." line.long 0x1C8 "MAC_ADDRESS57_HIGH,The MAC Address32 High register holds the upper 16 bits of the 33rd 6-byte MAC address of the station. If the MAC address registers are configured to be double-synchronized to the (G)MII clock domains. the synchronization is triggered.." bitfld.long 0x1C8 31. "AE,Address Enable When this bit is set the Address filter module uses the 33rd MAC address for perfect filtering. When this bit is reset the address filter module ignores the address for filtering. 0x0: Address is ignored 0x1: Address is enabled" "Address is ignored,Address is enabled" newline hexmask.long.word 0x1C8 19.--30. 1. "RESERVED_30_Y,Reserved." newline bitfld.long 0x1C8 16.--18. "DCS,DMA Channel Select This field contains the DMA Channel number to which an Rx packet whose DA matches the MAC Address32 content is routed." "0,1,2,3,4,5,6,7" newline hexmask.long.word 0x1C8 0.--15. 1. "ADDRHI,MAC Address32 [47:32] This field contains the upper 16 bits (47:32) of the 33rd 6-byte MAC address." line.long 0x1CC "MAC_ADDRESS57_LOW,The MAC Address32 Low register holds the lower 16 bits of the 33rd 6-byte MAC address of the station." hexmask.long 0x1CC 0.--31. 1. "ADDRLO,MAC Address32 [31:0] This field contains the lower 32 bits of the 33rd 6-byte MAC address. The content of this field is undefined until loaded by the Application after the initialization process." line.long 0x1D0 "MAC_ADDRESS58_HIGH,The MAC Address32 High register holds the upper 16 bits of the 33rd 6-byte MAC address of the station. If the MAC address registers are configured to be double-synchronized to the (G)MII clock domains. the synchronization is triggered.." bitfld.long 0x1D0 31. "AE,Address Enable When this bit is set the Address filter module uses the 33rd MAC address for perfect filtering. When this bit is reset the address filter module ignores the address for filtering. 0x0: Address is ignored 0x1: Address is enabled" "Address is ignored,Address is enabled" newline hexmask.long.word 0x1D0 19.--30. 1. "RESERVED_30_Y,Reserved." newline bitfld.long 0x1D0 16.--18. "DCS,DMA Channel Select This field contains the DMA Channel number to which an Rx packet whose DA matches the MAC Address32 content is routed." "0,1,2,3,4,5,6,7" newline hexmask.long.word 0x1D0 0.--15. 1. "ADDRHI,MAC Address32 [47:32] This field contains the upper 16 bits (47:32) of the 33rd 6-byte MAC address." line.long 0x1D4 "MAC_ADDRESS58_LOW,The MAC Address32 Low register holds the lower 16 bits of the 33rd 6-byte MAC address of the station." hexmask.long 0x1D4 0.--31. 1. "ADDRLO,MAC Address32 [31:0] This field contains the lower 32 bits of the 33rd 6-byte MAC address. The content of this field is undefined until loaded by the Application after the initialization process." line.long 0x1D8 "MAC_ADDRESS59_HIGH,The MAC Address32 High register holds the upper 16 bits of the 33rd 6-byte MAC address of the station. If the MAC address registers are configured to be double-synchronized to the (G)MII clock domains. the synchronization is triggered.." bitfld.long 0x1D8 31. "AE,Address Enable When this bit is set the Address filter module uses the 33rd MAC address for perfect filtering. When this bit is reset the address filter module ignores the address for filtering. 0x0: Address is ignored 0x1: Address is enabled" "Address is ignored,Address is enabled" newline hexmask.long.word 0x1D8 19.--30. 1. "RESERVED_30_Y,Reserved." newline bitfld.long 0x1D8 16.--18. "DCS,DMA Channel Select This field contains the DMA Channel number to which an Rx packet whose DA matches the MAC Address32 content is routed." "0,1,2,3,4,5,6,7" newline hexmask.long.word 0x1D8 0.--15. 1. "ADDRHI,MAC Address32 [47:32] This field contains the upper 16 bits (47:32) of the 33rd 6-byte MAC address." line.long 0x1DC "MAC_ADDRESS59_LOW,The MAC Address32 Low register holds the lower 16 bits of the 33rd 6-byte MAC address of the station." hexmask.long 0x1DC 0.--31. 1. "ADDRLO,MAC Address32 [31:0] This field contains the lower 32 bits of the 33rd 6-byte MAC address. The content of this field is undefined until loaded by the Application after the initialization process." line.long 0x1E0 "MAC_ADDRESS60_HIGH,The MAC Address32 High register holds the upper 16 bits of the 33rd 6-byte MAC address of the station. If the MAC address registers are configured to be double-synchronized to the (G)MII clock domains. the synchronization is triggered.." bitfld.long 0x1E0 31. "AE,Address Enable When this bit is set the Address filter module uses the 33rd MAC address for perfect filtering. When this bit is reset the address filter module ignores the address for filtering. 0x0: Address is ignored 0x1: Address is enabled" "Address is ignored,Address is enabled" newline hexmask.long.word 0x1E0 19.--30. 1. "RESERVED_30_Y,Reserved." newline bitfld.long 0x1E0 16.--18. "DCS,DMA Channel Select This field contains the DMA Channel number to which an Rx packet whose DA matches the MAC Address32 content is routed." "0,1,2,3,4,5,6,7" newline hexmask.long.word 0x1E0 0.--15. 1. "ADDRHI,MAC Address32 [47:32] This field contains the upper 16 bits (47:32) of the 33rd 6-byte MAC address." line.long 0x1E4 "MAC_ADDRESS60_LOW,The MAC Address32 Low register holds the lower 16 bits of the 33rd 6-byte MAC address of the station." hexmask.long 0x1E4 0.--31. 1. "ADDRLO,MAC Address32 [31:0] This field contains the lower 32 bits of the 33rd 6-byte MAC address. The content of this field is undefined until loaded by the Application after the initialization process." line.long 0x1E8 "MAC_ADDRESS61_HIGH,The MAC Address32 High register holds the upper 16 bits of the 33rd 6-byte MAC address of the station. If the MAC address registers are configured to be double-synchronized to the (G)MII clock domains. the synchronization is triggered.." bitfld.long 0x1E8 31. "AE,Address Enable When this bit is set the Address filter module uses the 33rd MAC address for perfect filtering. When this bit is reset the address filter module ignores the address for filtering. 0x0: Address is ignored 0x1: Address is enabled" "Address is ignored,Address is enabled" newline hexmask.long.word 0x1E8 19.--30. 1. "RESERVED_30_Y,Reserved." newline bitfld.long 0x1E8 16.--18. "DCS,DMA Channel Select This field contains the DMA Channel number to which an Rx packet whose DA matches the MAC Address32 content is routed." "0,1,2,3,4,5,6,7" newline hexmask.long.word 0x1E8 0.--15. 1. "ADDRHI,MAC Address32 [47:32] This field contains the upper 16 bits (47:32) of the 33rd 6-byte MAC address." line.long 0x1EC "MAC_ADDRESS61_LOW,The MAC Address32 Low register holds the lower 16 bits of the 33rd 6-byte MAC address of the station." hexmask.long 0x1EC 0.--31. 1. "ADDRLO,MAC Address32 [31:0] This field contains the lower 32 bits of the 33rd 6-byte MAC address. The content of this field is undefined until loaded by the Application after the initialization process." line.long 0x1F0 "MAC_ADDRESS62_HIGH,The MAC Address32 High register holds the upper 16 bits of the 33rd 6-byte MAC address of the station. If the MAC address registers are configured to be double-synchronized to the (G)MII clock domains. the synchronization is triggered.." bitfld.long 0x1F0 31. "AE,Address Enable When this bit is set the Address filter module uses the 33rd MAC address for perfect filtering. When this bit is reset the address filter module ignores the address for filtering. 0x0: Address is ignored 0x1: Address is enabled" "Address is ignored,Address is enabled" newline hexmask.long.word 0x1F0 19.--30. 1. "RESERVED_30_Y,Reserved." newline bitfld.long 0x1F0 16.--18. "DCS,DMA Channel Select This field contains the DMA Channel number to which an Rx packet whose DA matches the MAC Address32 content is routed." "0,1,2,3,4,5,6,7" newline hexmask.long.word 0x1F0 0.--15. 1. "ADDRHI,MAC Address32 [47:32] This field contains the upper 16 bits (47:32) of the 33rd 6-byte MAC address." line.long 0x1F4 "MAC_ADDRESS62_LOW,The MAC Address32 Low register holds the lower 16 bits of the 33rd 6-byte MAC address of the station." hexmask.long 0x1F4 0.--31. 1. "ADDRLO,MAC Address32 [31:0] This field contains the lower 32 bits of the 33rd 6-byte MAC address. The content of this field is undefined until loaded by the Application after the initialization process." line.long 0x1F8 "MAC_ADDRESS63_HIGH,The MAC Address32 High register holds the upper 16 bits of the 33rd 6-byte MAC address of the station. If the MAC address registers are configured to be double-synchronized to the (G)MII clock domains. the synchronization is triggered.." bitfld.long 0x1F8 31. "AE,Address Enable When this bit is set the Address filter module uses the 33rd MAC address for perfect filtering. When this bit is reset the address filter module ignores the address for filtering. 0x0: Address is ignored 0x1: Address is enabled" "Address is ignored,Address is enabled" newline hexmask.long.word 0x1F8 19.--30. 1. "RESERVED_30_Y,Reserved." newline bitfld.long 0x1F8 16.--18. "DCS,DMA Channel Select This field contains the DMA Channel number to which an Rx packet whose DA matches the MAC Address32 content is routed." "0,1,2,3,4,5,6,7" newline hexmask.long.word 0x1F8 0.--15. 1. "ADDRHI,MAC Address32 [47:32] This field contains the upper 16 bits (47:32) of the 33rd 6-byte MAC address." line.long 0x1FC "MAC_ADDRESS63_LOW,The MAC Address32 Low register holds the lower 16 bits of the 33rd 6-byte MAC address of the station." hexmask.long 0x1FC 0.--31. 1. "ADDRLO,MAC Address32 [31:0] This field contains the lower 32 bits of the 33rd 6-byte MAC address. The content of this field is undefined until loaded by the Application after the initialization process." line.long 0x200 "MAC_ADDRESS64_HIGH,The MAC Address32 High register holds the upper 16 bits of the 33rd 6-byte MAC address of the station. If the MAC address registers are configured to be double-synchronized to the (G)MII clock domains. the synchronization is triggered.." bitfld.long 0x200 31. "AE,Address Enable When this bit is set the Address filter module uses the 33rd MAC address for perfect filtering. When this bit is reset the address filter module ignores the address for filtering. 0x0: Address is ignored 0x1: Address is enabled" "Address is ignored,Address is enabled" newline hexmask.long.word 0x200 19.--30. 1. "RESERVED_30_Y,Reserved." newline bitfld.long 0x200 16.--18. "DCS,DMA Channel Select This field contains the DMA Channel number to which an Rx packet whose DA matches the MAC Address32 content is routed." "0,1,2,3,4,5,6,7" newline hexmask.long.word 0x200 0.--15. 1. "ADDRHI,MAC Address32 [47:32] This field contains the upper 16 bits (47:32) of the 33rd 6-byte MAC address." line.long 0x204 "MAC_ADDRESS64_LOW,The MAC Address32 Low register holds the lower 16 bits of the 33rd 6-byte MAC address of the station." hexmask.long 0x204 0.--31. 1. "ADDRLO,MAC Address32 [31:0] This field contains the lower 32 bits of the 33rd 6-byte MAC address. The content of this field is undefined until loaded by the Application after the initialization process." line.long 0x208 "MAC_ADDRESS65_HIGH,The MAC Address32 High register holds the upper 16 bits of the 33rd 6-byte MAC address of the station. If the MAC address registers are configured to be double-synchronized to the (G)MII clock domains. the synchronization is triggered.." bitfld.long 0x208 31. "AE,Address Enable When this bit is set the Address filter module uses the 33rd MAC address for perfect filtering. When this bit is reset the address filter module ignores the address for filtering. 0x0: Address is ignored 0x1: Address is enabled" "Address is ignored,Address is enabled" newline hexmask.long.word 0x208 19.--30. 1. "RESERVED_30_Y,Reserved." newline bitfld.long 0x208 16.--18. "DCS,DMA Channel Select This field contains the DMA Channel number to which an Rx packet whose DA matches the MAC Address32 content is routed." "0,1,2,3,4,5,6,7" newline hexmask.long.word 0x208 0.--15. 1. "ADDRHI,MAC Address32 [47:32] This field contains the upper 16 bits (47:32) of the 33rd 6-byte MAC address." line.long 0x20C "MAC_ADDRESS65_LOW,The MAC Address32 Low register holds the lower 16 bits of the 33rd 6-byte MAC address of the station." hexmask.long 0x20C 0.--31. 1. "ADDRLO,MAC Address32 [31:0] This field contains the lower 32 bits of the 33rd 6-byte MAC address. The content of this field is undefined until loaded by the Application after the initialization process." line.long 0x210 "MAC_ADDRESS66_HIGH,The MAC Address32 High register holds the upper 16 bits of the 33rd 6-byte MAC address of the station. If the MAC address registers are configured to be double-synchronized to the (G)MII clock domains. the synchronization is triggered.." bitfld.long 0x210 31. "AE,Address Enable When this bit is set the Address filter module uses the 33rd MAC address for perfect filtering. When this bit is reset the address filter module ignores the address for filtering. 0x0: Address is ignored 0x1: Address is enabled" "Address is ignored,Address is enabled" newline hexmask.long.word 0x210 19.--30. 1. "RESERVED_30_Y,Reserved." newline bitfld.long 0x210 16.--18. "DCS,DMA Channel Select This field contains the DMA Channel number to which an Rx packet whose DA matches the MAC Address32 content is routed." "0,1,2,3,4,5,6,7" newline hexmask.long.word 0x210 0.--15. 1. "ADDRHI,MAC Address32 [47:32] This field contains the upper 16 bits (47:32) of the 33rd 6-byte MAC address." line.long 0x214 "MAC_ADDRESS66_LOW,The MAC Address32 Low register holds the lower 16 bits of the 33rd 6-byte MAC address of the station." hexmask.long 0x214 0.--31. 1. "ADDRLO,MAC Address32 [31:0] This field contains the lower 32 bits of the 33rd 6-byte MAC address. The content of this field is undefined until loaded by the Application after the initialization process." line.long 0x218 "MAC_ADDRESS67_HIGH,The MAC Address32 High register holds the upper 16 bits of the 33rd 6-byte MAC address of the station. If the MAC address registers are configured to be double-synchronized to the (G)MII clock domains. the synchronization is triggered.." bitfld.long 0x218 31. "AE,Address Enable When this bit is set the Address filter module uses the 33rd MAC address for perfect filtering. When this bit is reset the address filter module ignores the address for filtering. 0x0: Address is ignored 0x1: Address is enabled" "Address is ignored,Address is enabled" newline hexmask.long.word 0x218 19.--30. 1. "RESERVED_30_Y,Reserved." newline bitfld.long 0x218 16.--18. "DCS,DMA Channel Select This field contains the DMA Channel number to which an Rx packet whose DA matches the MAC Address32 content is routed." "0,1,2,3,4,5,6,7" newline hexmask.long.word 0x218 0.--15. 1. "ADDRHI,MAC Address32 [47:32] This field contains the upper 16 bits (47:32) of the 33rd 6-byte MAC address." line.long 0x21C "MAC_ADDRESS67_LOW,The MAC Address32 Low register holds the lower 16 bits of the 33rd 6-byte MAC address of the station." hexmask.long 0x21C 0.--31. 1. "ADDRLO,MAC Address32 [31:0] This field contains the lower 32 bits of the 33rd 6-byte MAC address. The content of this field is undefined until loaded by the Application after the initialization process." line.long 0x220 "MAC_ADDRESS68_HIGH,The MAC Address32 High register holds the upper 16 bits of the 33rd 6-byte MAC address of the station. If the MAC address registers are configured to be double-synchronized to the (G)MII clock domains. the synchronization is triggered.." bitfld.long 0x220 31. "AE,Address Enable When this bit is set the Address filter module uses the 33rd MAC address for perfect filtering. When this bit is reset the address filter module ignores the address for filtering. 0x0: Address is ignored 0x1: Address is enabled" "Address is ignored,Address is enabled" newline hexmask.long.word 0x220 19.--30. 1. "RESERVED_30_Y,Reserved." newline bitfld.long 0x220 16.--18. "DCS,DMA Channel Select This field contains the DMA Channel number to which an Rx packet whose DA matches the MAC Address32 content is routed." "0,1,2,3,4,5,6,7" newline hexmask.long.word 0x220 0.--15. 1. "ADDRHI,MAC Address32 [47:32] This field contains the upper 16 bits (47:32) of the 33rd 6-byte MAC address." line.long 0x224 "MAC_ADDRESS68_LOW,The MAC Address32 Low register holds the lower 16 bits of the 33rd 6-byte MAC address of the station." hexmask.long 0x224 0.--31. 1. "ADDRLO,MAC Address32 [31:0] This field contains the lower 32 bits of the 33rd 6-byte MAC address. The content of this field is undefined until loaded by the Application after the initialization process." line.long 0x228 "MAC_ADDRESS69_HIGH,The MAC Address32 High register holds the upper 16 bits of the 33rd 6-byte MAC address of the station. If the MAC address registers are configured to be double-synchronized to the (G)MII clock domains. the synchronization is triggered.." bitfld.long 0x228 31. "AE,Address Enable When this bit is set the Address filter module uses the 33rd MAC address for perfect filtering. When this bit is reset the address filter module ignores the address for filtering. 0x0: Address is ignored 0x1: Address is enabled" "Address is ignored,Address is enabled" newline hexmask.long.word 0x228 19.--30. 1. "RESERVED_30_Y,Reserved." newline bitfld.long 0x228 16.--18. "DCS,DMA Channel Select This field contains the DMA Channel number to which an Rx packet whose DA matches the MAC Address32 content is routed." "0,1,2,3,4,5,6,7" newline hexmask.long.word 0x228 0.--15. 1. "ADDRHI,MAC Address32 [47:32] This field contains the upper 16 bits (47:32) of the 33rd 6-byte MAC address." line.long 0x22C "MAC_ADDRESS69_LOW,The MAC Address32 Low register holds the lower 16 bits of the 33rd 6-byte MAC address of the station." hexmask.long 0x22C 0.--31. 1. "ADDRLO,MAC Address32 [31:0] This field contains the lower 32 bits of the 33rd 6-byte MAC address. The content of this field is undefined until loaded by the Application after the initialization process." line.long 0x230 "MAC_ADDRESS70_HIGH,The MAC Address32 High register holds the upper 16 bits of the 33rd 6-byte MAC address of the station. If the MAC address registers are configured to be double-synchronized to the (G)MII clock domains. the synchronization is triggered.." bitfld.long 0x230 31. "AE,Address Enable When this bit is set the Address filter module uses the 33rd MAC address for perfect filtering. When this bit is reset the address filter module ignores the address for filtering. 0x0: Address is ignored 0x1: Address is enabled" "Address is ignored,Address is enabled" newline hexmask.long.word 0x230 19.--30. 1. "RESERVED_30_Y,Reserved." newline bitfld.long 0x230 16.--18. "DCS,DMA Channel Select This field contains the DMA Channel number to which an Rx packet whose DA matches the MAC Address32 content is routed." "0,1,2,3,4,5,6,7" newline hexmask.long.word 0x230 0.--15. 1. "ADDRHI,MAC Address32 [47:32] This field contains the upper 16 bits (47:32) of the 33rd 6-byte MAC address." line.long 0x234 "MAC_ADDRESS70_LOW,The MAC Address32 Low register holds the lower 16 bits of the 33rd 6-byte MAC address of the station." hexmask.long 0x234 0.--31. 1. "ADDRLO,MAC Address32 [31:0] This field contains the lower 32 bits of the 33rd 6-byte MAC address. The content of this field is undefined until loaded by the Application after the initialization process." line.long 0x238 "MAC_ADDRESS71_HIGH,The MAC Address32 High register holds the upper 16 bits of the 33rd 6-byte MAC address of the station. If the MAC address registers are configured to be double-synchronized to the (G)MII clock domains. the synchronization is triggered.." bitfld.long 0x238 31. "AE,Address Enable When this bit is set the Address filter module uses the 33rd MAC address for perfect filtering. When this bit is reset the address filter module ignores the address for filtering. 0x0: Address is ignored 0x1: Address is enabled" "Address is ignored,Address is enabled" newline hexmask.long.word 0x238 19.--30. 1. "RESERVED_30_Y,Reserved." newline bitfld.long 0x238 16.--18. "DCS,DMA Channel Select This field contains the DMA Channel number to which an Rx packet whose DA matches the MAC Address32 content is routed." "0,1,2,3,4,5,6,7" newline hexmask.long.word 0x238 0.--15. 1. "ADDRHI,MAC Address32 [47:32] This field contains the upper 16 bits (47:32) of the 33rd 6-byte MAC address." line.long 0x23C "MAC_ADDRESS71_LOW,The MAC Address32 Low register holds the lower 16 bits of the 33rd 6-byte MAC address of the station." hexmask.long 0x23C 0.--31. 1. "ADDRLO,MAC Address32 [31:0] This field contains the lower 32 bits of the 33rd 6-byte MAC address. The content of this field is undefined until loaded by the Application after the initialization process." line.long 0x240 "MAC_ADDRESS72_HIGH,The MAC Address32 High register holds the upper 16 bits of the 33rd 6-byte MAC address of the station. If the MAC address registers are configured to be double-synchronized to the (G)MII clock domains. the synchronization is triggered.." bitfld.long 0x240 31. "AE,Address Enable When this bit is set the Address filter module uses the 33rd MAC address for perfect filtering. When this bit is reset the address filter module ignores the address for filtering. 0x0: Address is ignored 0x1: Address is enabled" "Address is ignored,Address is enabled" newline hexmask.long.word 0x240 19.--30. 1. "RESERVED_30_Y,Reserved." newline bitfld.long 0x240 16.--18. "DCS,DMA Channel Select This field contains the DMA Channel number to which an Rx packet whose DA matches the MAC Address32 content is routed." "0,1,2,3,4,5,6,7" newline hexmask.long.word 0x240 0.--15. 1. "ADDRHI,MAC Address32 [47:32] This field contains the upper 16 bits (47:32) of the 33rd 6-byte MAC address." line.long 0x244 "MAC_ADDRESS72_LOW,The MAC Address32 Low register holds the lower 16 bits of the 33rd 6-byte MAC address of the station." hexmask.long 0x244 0.--31. 1. "ADDRLO,MAC Address32 [31:0] This field contains the lower 32 bits of the 33rd 6-byte MAC address. The content of this field is undefined until loaded by the Application after the initialization process." line.long 0x248 "MAC_ADDRESS73_HIGH,The MAC Address32 High register holds the upper 16 bits of the 33rd 6-byte MAC address of the station. If the MAC address registers are configured to be double-synchronized to the (G)MII clock domains. the synchronization is triggered.." bitfld.long 0x248 31. "AE,Address Enable When this bit is set the Address filter module uses the 33rd MAC address for perfect filtering. When this bit is reset the address filter module ignores the address for filtering. 0x0: Address is ignored 0x1: Address is enabled" "Address is ignored,Address is enabled" newline hexmask.long.word 0x248 19.--30. 1. "RESERVED_30_Y,Reserved." newline bitfld.long 0x248 16.--18. "DCS,DMA Channel Select This field contains the DMA Channel number to which an Rx packet whose DA matches the MAC Address32 content is routed." "0,1,2,3,4,5,6,7" newline hexmask.long.word 0x248 0.--15. 1. "ADDRHI,MAC Address32 [47:32] This field contains the upper 16 bits (47:32) of the 33rd 6-byte MAC address." line.long 0x24C "MAC_ADDRESS73_LOW,The MAC Address32 Low register holds the lower 16 bits of the 33rd 6-byte MAC address of the station." hexmask.long 0x24C 0.--31. 1. "ADDRLO,MAC Address32 [31:0] This field contains the lower 32 bits of the 33rd 6-byte MAC address. The content of this field is undefined until loaded by the Application after the initialization process." line.long 0x250 "MAC_ADDRESS74_HIGH,The MAC Address32 High register holds the upper 16 bits of the 33rd 6-byte MAC address of the station. If the MAC address registers are configured to be double-synchronized to the (G)MII clock domains. the synchronization is triggered.." bitfld.long 0x250 31. "AE,Address Enable When this bit is set the Address filter module uses the 33rd MAC address for perfect filtering. When this bit is reset the address filter module ignores the address for filtering. 0x0: Address is ignored 0x1: Address is enabled" "Address is ignored,Address is enabled" newline hexmask.long.word 0x250 19.--30. 1. "RESERVED_30_Y,Reserved." newline bitfld.long 0x250 16.--18. "DCS,DMA Channel Select This field contains the DMA Channel number to which an Rx packet whose DA matches the MAC Address32 content is routed." "0,1,2,3,4,5,6,7" newline hexmask.long.word 0x250 0.--15. 1. "ADDRHI,MAC Address32 [47:32] This field contains the upper 16 bits (47:32) of the 33rd 6-byte MAC address." line.long 0x254 "MAC_ADDRESS74_LOW,The MAC Address32 Low register holds the lower 16 bits of the 33rd 6-byte MAC address of the station." hexmask.long 0x254 0.--31. 1. "ADDRLO,MAC Address32 [31:0] This field contains the lower 32 bits of the 33rd 6-byte MAC address. The content of this field is undefined until loaded by the Application after the initialization process." line.long 0x258 "MAC_ADDRESS75_HIGH,The MAC Address32 High register holds the upper 16 bits of the 33rd 6-byte MAC address of the station. If the MAC address registers are configured to be double-synchronized to the (G)MII clock domains. the synchronization is triggered.." bitfld.long 0x258 31. "AE,Address Enable When this bit is set the Address filter module uses the 33rd MAC address for perfect filtering. When this bit is reset the address filter module ignores the address for filtering. 0x0: Address is ignored 0x1: Address is enabled" "Address is ignored,Address is enabled" newline hexmask.long.word 0x258 19.--30. 1. "RESERVED_30_Y,Reserved." newline bitfld.long 0x258 16.--18. "DCS,DMA Channel Select This field contains the DMA Channel number to which an Rx packet whose DA matches the MAC Address32 content is routed." "0,1,2,3,4,5,6,7" newline hexmask.long.word 0x258 0.--15. 1. "ADDRHI,MAC Address32 [47:32] This field contains the upper 16 bits (47:32) of the 33rd 6-byte MAC address." line.long 0x25C "MAC_ADDRESS75_LOW,The MAC Address32 Low register holds the lower 16 bits of the 33rd 6-byte MAC address of the station." hexmask.long 0x25C 0.--31. 1. "ADDRLO,MAC Address32 [31:0] This field contains the lower 32 bits of the 33rd 6-byte MAC address. The content of this field is undefined until loaded by the Application after the initialization process." line.long 0x260 "MAC_ADDRESS76_HIGH,The MAC Address32 High register holds the upper 16 bits of the 33rd 6-byte MAC address of the station. If the MAC address registers are configured to be double-synchronized to the (G)MII clock domains. the synchronization is triggered.." bitfld.long 0x260 31. "AE,Address Enable When this bit is set the Address filter module uses the 33rd MAC address for perfect filtering. When this bit is reset the address filter module ignores the address for filtering. 0x0: Address is ignored 0x1: Address is enabled" "Address is ignored,Address is enabled" newline hexmask.long.word 0x260 19.--30. 1. "RESERVED_30_Y,Reserved." newline bitfld.long 0x260 16.--18. "DCS,DMA Channel Select This field contains the DMA Channel number to which an Rx packet whose DA matches the MAC Address32 content is routed." "0,1,2,3,4,5,6,7" newline hexmask.long.word 0x260 0.--15. 1. "ADDRHI,MAC Address32 [47:32] This field contains the upper 16 bits (47:32) of the 33rd 6-byte MAC address." line.long 0x264 "MAC_ADDRESS76_LOW,The MAC Address32 Low register holds the lower 16 bits of the 33rd 6-byte MAC address of the station." hexmask.long 0x264 0.--31. 1. "ADDRLO,MAC Address32 [31:0] This field contains the lower 32 bits of the 33rd 6-byte MAC address. The content of this field is undefined until loaded by the Application after the initialization process." line.long 0x268 "MAC_ADDRESS77_HIGH,The MAC Address32 High register holds the upper 16 bits of the 33rd 6-byte MAC address of the station. If the MAC address registers are configured to be double-synchronized to the (G)MII clock domains. the synchronization is triggered.." bitfld.long 0x268 31. "AE,Address Enable When this bit is set the Address filter module uses the 33rd MAC address for perfect filtering. When this bit is reset the address filter module ignores the address for filtering. 0x0: Address is ignored 0x1: Address is enabled" "Address is ignored,Address is enabled" newline hexmask.long.word 0x268 19.--30. 1. "RESERVED_30_Y,Reserved." newline bitfld.long 0x268 16.--18. "DCS,DMA Channel Select This field contains the DMA Channel number to which an Rx packet whose DA matches the MAC Address32 content is routed." "0,1,2,3,4,5,6,7" newline hexmask.long.word 0x268 0.--15. 1. "ADDRHI,MAC Address32 [47:32] This field contains the upper 16 bits (47:32) of the 33rd 6-byte MAC address." line.long 0x26C "MAC_ADDRESS77_LOW,The MAC Address32 Low register holds the lower 16 bits of the 33rd 6-byte MAC address of the station." hexmask.long 0x26C 0.--31. 1. "ADDRLO,MAC Address32 [31:0] This field contains the lower 32 bits of the 33rd 6-byte MAC address. The content of this field is undefined until loaded by the Application after the initialization process." line.long 0x270 "MAC_ADDRESS78_HIGH,The MAC Address32 High register holds the upper 16 bits of the 33rd 6-byte MAC address of the station. If the MAC address registers are configured to be double-synchronized to the (G)MII clock domains. the synchronization is triggered.." bitfld.long 0x270 31. "AE,Address Enable When this bit is set the Address filter module uses the 33rd MAC address for perfect filtering. When this bit is reset the address filter module ignores the address for filtering. 0x0: Address is ignored 0x1: Address is enabled" "Address is ignored,Address is enabled" newline hexmask.long.word 0x270 19.--30. 1. "RESERVED_30_Y,Reserved." newline bitfld.long 0x270 16.--18. "DCS,DMA Channel Select This field contains the DMA Channel number to which an Rx packet whose DA matches the MAC Address32 content is routed." "0,1,2,3,4,5,6,7" newline hexmask.long.word 0x270 0.--15. 1. "ADDRHI,MAC Address32 [47:32] This field contains the upper 16 bits (47:32) of the 33rd 6-byte MAC address." line.long 0x274 "MAC_ADDRESS78_LOW,The MAC Address32 Low register holds the lower 16 bits of the 33rd 6-byte MAC address of the station." hexmask.long 0x274 0.--31. 1. "ADDRLO,MAC Address32 [31:0] This field contains the lower 32 bits of the 33rd 6-byte MAC address. The content of this field is undefined until loaded by the Application after the initialization process." line.long 0x278 "MAC_ADDRESS79_HIGH,The MAC Address32 High register holds the upper 16 bits of the 33rd 6-byte MAC address of the station. If the MAC address registers are configured to be double-synchronized to the (G)MII clock domains. the synchronization is triggered.." bitfld.long 0x278 31. "AE,Address Enable When this bit is set the Address filter module uses the 33rd MAC address for perfect filtering. When this bit is reset the address filter module ignores the address for filtering. 0x0: Address is ignored 0x1: Address is enabled" "Address is ignored,Address is enabled" newline hexmask.long.word 0x278 19.--30. 1. "RESERVED_30_Y,Reserved." newline bitfld.long 0x278 16.--18. "DCS,DMA Channel Select This field contains the DMA Channel number to which an Rx packet whose DA matches the MAC Address32 content is routed." "0,1,2,3,4,5,6,7" newline hexmask.long.word 0x278 0.--15. 1. "ADDRHI,MAC Address32 [47:32] This field contains the upper 16 bits (47:32) of the 33rd 6-byte MAC address." line.long 0x27C "MAC_ADDRESS79_LOW,The MAC Address32 Low register holds the lower 16 bits of the 33rd 6-byte MAC address of the station." hexmask.long 0x27C 0.--31. 1. "ADDRLO,MAC Address32 [31:0] This field contains the lower 32 bits of the 33rd 6-byte MAC address. The content of this field is undefined until loaded by the Application after the initialization process." line.long 0x280 "MAC_ADDRESS80_HIGH,The MAC Address32 High register holds the upper 16 bits of the 33rd 6-byte MAC address of the station. If the MAC address registers are configured to be double-synchronized to the (G)MII clock domains. the synchronization is triggered.." bitfld.long 0x280 31. "AE,Address Enable When this bit is set the Address filter module uses the 33rd MAC address for perfect filtering. When this bit is reset the address filter module ignores the address for filtering. 0x0: Address is ignored 0x1: Address is enabled" "Address is ignored,Address is enabled" newline hexmask.long.word 0x280 19.--30. 1. "RESERVED_30_Y,Reserved." newline bitfld.long 0x280 16.--18. "DCS,DMA Channel Select This field contains the DMA Channel number to which an Rx packet whose DA matches the MAC Address32 content is routed." "0,1,2,3,4,5,6,7" newline hexmask.long.word 0x280 0.--15. 1. "ADDRHI,MAC Address32 [47:32] This field contains the upper 16 bits (47:32) of the 33rd 6-byte MAC address." line.long 0x284 "MAC_ADDRESS80_LOW,The MAC Address32 Low register holds the lower 16 bits of the 33rd 6-byte MAC address of the station." hexmask.long 0x284 0.--31. 1. "ADDRLO,MAC Address32 [31:0] This field contains the lower 32 bits of the 33rd 6-byte MAC address. The content of this field is undefined until loaded by the Application after the initialization process." line.long 0x288 "MAC_ADDRESS81_HIGH,The MAC Address32 High register holds the upper 16 bits of the 33rd 6-byte MAC address of the station. If the MAC address registers are configured to be double-synchronized to the (G)MII clock domains. the synchronization is triggered.." bitfld.long 0x288 31. "AE,Address Enable When this bit is set the Address filter module uses the 33rd MAC address for perfect filtering. When this bit is reset the address filter module ignores the address for filtering. 0x0: Address is ignored 0x1: Address is enabled" "Address is ignored,Address is enabled" newline hexmask.long.word 0x288 19.--30. 1. "RESERVED_30_Y,Reserved." newline bitfld.long 0x288 16.--18. "DCS,DMA Channel Select This field contains the DMA Channel number to which an Rx packet whose DA matches the MAC Address32 content is routed." "0,1,2,3,4,5,6,7" newline hexmask.long.word 0x288 0.--15. 1. "ADDRHI,MAC Address32 [47:32] This field contains the upper 16 bits (47:32) of the 33rd 6-byte MAC address." line.long 0x28C "MAC_ADDRESS81_LOW,The MAC Address32 Low register holds the lower 16 bits of the 33rd 6-byte MAC address of the station." hexmask.long 0x28C 0.--31. 1. "ADDRLO,MAC Address32 [31:0] This field contains the lower 32 bits of the 33rd 6-byte MAC address. The content of this field is undefined until loaded by the Application after the initialization process." line.long 0x290 "MAC_ADDRESS82_HIGH,The MAC Address32 High register holds the upper 16 bits of the 33rd 6-byte MAC address of the station. If the MAC address registers are configured to be double-synchronized to the (G)MII clock domains. the synchronization is triggered.." bitfld.long 0x290 31. "AE,Address Enable When this bit is set the Address filter module uses the 33rd MAC address for perfect filtering. When this bit is reset the address filter module ignores the address for filtering. 0x0: Address is ignored 0x1: Address is enabled" "Address is ignored,Address is enabled" newline hexmask.long.word 0x290 19.--30. 1. "RESERVED_30_Y,Reserved." newline bitfld.long 0x290 16.--18. "DCS,DMA Channel Select This field contains the DMA Channel number to which an Rx packet whose DA matches the MAC Address32 content is routed." "0,1,2,3,4,5,6,7" newline hexmask.long.word 0x290 0.--15. 1. "ADDRHI,MAC Address32 [47:32] This field contains the upper 16 bits (47:32) of the 33rd 6-byte MAC address." line.long 0x294 "MAC_ADDRESS82_LOW,The MAC Address32 Low register holds the lower 16 bits of the 33rd 6-byte MAC address of the station." hexmask.long 0x294 0.--31. 1. "ADDRLO,MAC Address32 [31:0] This field contains the lower 32 bits of the 33rd 6-byte MAC address. The content of this field is undefined until loaded by the Application after the initialization process." line.long 0x298 "MAC_ADDRESS83_HIGH,The MAC Address32 High register holds the upper 16 bits of the 33rd 6-byte MAC address of the station. If the MAC address registers are configured to be double-synchronized to the (G)MII clock domains. the synchronization is triggered.." bitfld.long 0x298 31. "AE,Address Enable When this bit is set the Address filter module uses the 33rd MAC address for perfect filtering. When this bit is reset the address filter module ignores the address for filtering. 0x0: Address is ignored 0x1: Address is enabled" "Address is ignored,Address is enabled" newline hexmask.long.word 0x298 19.--30. 1. "RESERVED_30_Y,Reserved." newline bitfld.long 0x298 16.--18. "DCS,DMA Channel Select This field contains the DMA Channel number to which an Rx packet whose DA matches the MAC Address32 content is routed." "0,1,2,3,4,5,6,7" newline hexmask.long.word 0x298 0.--15. 1. "ADDRHI,MAC Address32 [47:32] This field contains the upper 16 bits (47:32) of the 33rd 6-byte MAC address." line.long 0x29C "MAC_ADDRESS83_LOW,The MAC Address32 Low register holds the lower 16 bits of the 33rd 6-byte MAC address of the station." hexmask.long 0x29C 0.--31. 1. "ADDRLO,MAC Address32 [31:0] This field contains the lower 32 bits of the 33rd 6-byte MAC address. The content of this field is undefined until loaded by the Application after the initialization process." line.long 0x2A0 "MAC_ADDRESS84_HIGH,The MAC Address32 High register holds the upper 16 bits of the 33rd 6-byte MAC address of the station. If the MAC address registers are configured to be double-synchronized to the (G)MII clock domains. the synchronization is triggered.." bitfld.long 0x2A0 31. "AE,Address Enable When this bit is set the Address filter module uses the 33rd MAC address for perfect filtering. When this bit is reset the address filter module ignores the address for filtering. 0x0: Address is ignored 0x1: Address is enabled" "Address is ignored,Address is enabled" newline hexmask.long.word 0x2A0 19.--30. 1. "RESERVED_30_Y,Reserved." newline bitfld.long 0x2A0 16.--18. "DCS,DMA Channel Select This field contains the DMA Channel number to which an Rx packet whose DA matches the MAC Address32 content is routed." "0,1,2,3,4,5,6,7" newline hexmask.long.word 0x2A0 0.--15. 1. "ADDRHI,MAC Address32 [47:32] This field contains the upper 16 bits (47:32) of the 33rd 6-byte MAC address." line.long 0x2A4 "MAC_ADDRESS84_LOW,The MAC Address32 Low register holds the lower 16 bits of the 33rd 6-byte MAC address of the station." hexmask.long 0x2A4 0.--31. 1. "ADDRLO,MAC Address32 [31:0] This field contains the lower 32 bits of the 33rd 6-byte MAC address. The content of this field is undefined until loaded by the Application after the initialization process." line.long 0x2A8 "MAC_ADDRESS85_HIGH,The MAC Address32 High register holds the upper 16 bits of the 33rd 6-byte MAC address of the station. If the MAC address registers are configured to be double-synchronized to the (G)MII clock domains. the synchronization is triggered.." bitfld.long 0x2A8 31. "AE,Address Enable When this bit is set the Address filter module uses the 33rd MAC address for perfect filtering. When this bit is reset the address filter module ignores the address for filtering. 0x0: Address is ignored 0x1: Address is enabled" "Address is ignored,Address is enabled" newline hexmask.long.word 0x2A8 19.--30. 1. "RESERVED_30_Y,Reserved." newline bitfld.long 0x2A8 16.--18. "DCS,DMA Channel Select This field contains the DMA Channel number to which an Rx packet whose DA matches the MAC Address32 content is routed." "0,1,2,3,4,5,6,7" newline hexmask.long.word 0x2A8 0.--15. 1. "ADDRHI,MAC Address32 [47:32] This field contains the upper 16 bits (47:32) of the 33rd 6-byte MAC address." line.long 0x2AC "MAC_ADDRESS85_LOW,The MAC Address32 Low register holds the lower 16 bits of the 33rd 6-byte MAC address of the station." hexmask.long 0x2AC 0.--31. 1. "ADDRLO,MAC Address32 [31:0] This field contains the lower 32 bits of the 33rd 6-byte MAC address. The content of this field is undefined until loaded by the Application after the initialization process." line.long 0x2B0 "MAC_ADDRESS86_HIGH,The MAC Address32 High register holds the upper 16 bits of the 33rd 6-byte MAC address of the station. If the MAC address registers are configured to be double-synchronized to the (G)MII clock domains. the synchronization is triggered.." bitfld.long 0x2B0 31. "AE,Address Enable When this bit is set the Address filter module uses the 33rd MAC address for perfect filtering. When this bit is reset the address filter module ignores the address for filtering. 0x0: Address is ignored 0x1: Address is enabled" "Address is ignored,Address is enabled" newline hexmask.long.word 0x2B0 19.--30. 1. "RESERVED_30_Y,Reserved." newline bitfld.long 0x2B0 16.--18. "DCS,DMA Channel Select This field contains the DMA Channel number to which an Rx packet whose DA matches the MAC Address32 content is routed." "0,1,2,3,4,5,6,7" newline hexmask.long.word 0x2B0 0.--15. 1. "ADDRHI,MAC Address32 [47:32] This field contains the upper 16 bits (47:32) of the 33rd 6-byte MAC address." line.long 0x2B4 "MAC_ADDRESS86_LOW,The MAC Address32 Low register holds the lower 16 bits of the 33rd 6-byte MAC address of the station." hexmask.long 0x2B4 0.--31. 1. "ADDRLO,MAC Address32 [31:0] This field contains the lower 32 bits of the 33rd 6-byte MAC address. The content of this field is undefined until loaded by the Application after the initialization process." line.long 0x2B8 "MAC_ADDRESS87_HIGH,The MAC Address32 High register holds the upper 16 bits of the 33rd 6-byte MAC address of the station. If the MAC address registers are configured to be double-synchronized to the (G)MII clock domains. the synchronization is triggered.." bitfld.long 0x2B8 31. "AE,Address Enable When this bit is set the Address filter module uses the 33rd MAC address for perfect filtering. When this bit is reset the address filter module ignores the address for filtering. 0x0: Address is ignored 0x1: Address is enabled" "Address is ignored,Address is enabled" newline hexmask.long.word 0x2B8 19.--30. 1. "RESERVED_30_Y,Reserved." newline bitfld.long 0x2B8 16.--18. "DCS,DMA Channel Select This field contains the DMA Channel number to which an Rx packet whose DA matches the MAC Address32 content is routed." "0,1,2,3,4,5,6,7" newline hexmask.long.word 0x2B8 0.--15. 1. "ADDRHI,MAC Address32 [47:32] This field contains the upper 16 bits (47:32) of the 33rd 6-byte MAC address." line.long 0x2BC "MAC_ADDRESS87_LOW,The MAC Address32 Low register holds the lower 16 bits of the 33rd 6-byte MAC address of the station." hexmask.long 0x2BC 0.--31. 1. "ADDRLO,MAC Address32 [31:0] This field contains the lower 32 bits of the 33rd 6-byte MAC address. The content of this field is undefined until loaded by the Application after the initialization process." line.long 0x2C0 "MAC_ADDRESS88_HIGH,The MAC Address32 High register holds the upper 16 bits of the 33rd 6-byte MAC address of the station. If the MAC address registers are configured to be double-synchronized to the (G)MII clock domains. the synchronization is triggered.." bitfld.long 0x2C0 31. "AE,Address Enable When this bit is set the Address filter module uses the 33rd MAC address for perfect filtering. When this bit is reset the address filter module ignores the address for filtering. 0x0: Address is ignored 0x1: Address is enabled" "Address is ignored,Address is enabled" newline hexmask.long.word 0x2C0 19.--30. 1. "RESERVED_30_Y,Reserved." newline bitfld.long 0x2C0 16.--18. "DCS,DMA Channel Select This field contains the DMA Channel number to which an Rx packet whose DA matches the MAC Address32 content is routed." "0,1,2,3,4,5,6,7" newline hexmask.long.word 0x2C0 0.--15. 1. "ADDRHI,MAC Address32 [47:32] This field contains the upper 16 bits (47:32) of the 33rd 6-byte MAC address." line.long 0x2C4 "MAC_ADDRESS88_LOW,The MAC Address32 Low register holds the lower 16 bits of the 33rd 6-byte MAC address of the station." hexmask.long 0x2C4 0.--31. 1. "ADDRLO,MAC Address32 [31:0] This field contains the lower 32 bits of the 33rd 6-byte MAC address. The content of this field is undefined until loaded by the Application after the initialization process." line.long 0x2C8 "MAC_ADDRESS89_HIGH,The MAC Address32 High register holds the upper 16 bits of the 33rd 6-byte MAC address of the station. If the MAC address registers are configured to be double-synchronized to the (G)MII clock domains. the synchronization is triggered.." bitfld.long 0x2C8 31. "AE,Address Enable When this bit is set the Address filter module uses the 33rd MAC address for perfect filtering. When this bit is reset the address filter module ignores the address for filtering. 0x0: Address is ignored 0x1: Address is enabled" "Address is ignored,Address is enabled" newline hexmask.long.word 0x2C8 19.--30. 1. "RESERVED_30_Y,Reserved." newline bitfld.long 0x2C8 16.--18. "DCS,DMA Channel Select This field contains the DMA Channel number to which an Rx packet whose DA matches the MAC Address32 content is routed." "0,1,2,3,4,5,6,7" newline hexmask.long.word 0x2C8 0.--15. 1. "ADDRHI,MAC Address32 [47:32] This field contains the upper 16 bits (47:32) of the 33rd 6-byte MAC address." line.long 0x2CC "MAC_ADDRESS89_LOW,The MAC Address32 Low register holds the lower 16 bits of the 33rd 6-byte MAC address of the station." hexmask.long 0x2CC 0.--31. 1. "ADDRLO,MAC Address32 [31:0] This field contains the lower 32 bits of the 33rd 6-byte MAC address. The content of this field is undefined until loaded by the Application after the initialization process." line.long 0x2D0 "MAC_ADDRESS90_HIGH,The MAC Address32 High register holds the upper 16 bits of the 33rd 6-byte MAC address of the station. If the MAC address registers are configured to be double-synchronized to the (G)MII clock domains. the synchronization is triggered.." bitfld.long 0x2D0 31. "AE,Address Enable When this bit is set the Address filter module uses the 33rd MAC address for perfect filtering. When this bit is reset the address filter module ignores the address for filtering. 0x0: Address is ignored 0x1: Address is enabled" "Address is ignored,Address is enabled" newline hexmask.long.word 0x2D0 19.--30. 1. "RESERVED_30_Y,Reserved." newline bitfld.long 0x2D0 16.--18. "DCS,DMA Channel Select This field contains the DMA Channel number to which an Rx packet whose DA matches the MAC Address32 content is routed." "0,1,2,3,4,5,6,7" newline hexmask.long.word 0x2D0 0.--15. 1. "ADDRHI,MAC Address32 [47:32] This field contains the upper 16 bits (47:32) of the 33rd 6-byte MAC address." line.long 0x2D4 "MAC_ADDRESS90_LOW,The MAC Address32 Low register holds the lower 16 bits of the 33rd 6-byte MAC address of the station." hexmask.long 0x2D4 0.--31. 1. "ADDRLO,MAC Address32 [31:0] This field contains the lower 32 bits of the 33rd 6-byte MAC address. The content of this field is undefined until loaded by the Application after the initialization process." line.long 0x2D8 "MAC_ADDRESS91_HIGH,The MAC Address32 High register holds the upper 16 bits of the 33rd 6-byte MAC address of the station. If the MAC address registers are configured to be double-synchronized to the (G)MII clock domains. the synchronization is triggered.." bitfld.long 0x2D8 31. "AE,Address Enable When this bit is set the Address filter module uses the 33rd MAC address for perfect filtering. When this bit is reset the address filter module ignores the address for filtering. 0x0: Address is ignored 0x1: Address is enabled" "Address is ignored,Address is enabled" newline hexmask.long.word 0x2D8 19.--30. 1. "RESERVED_30_Y,Reserved." newline bitfld.long 0x2D8 16.--18. "DCS,DMA Channel Select This field contains the DMA Channel number to which an Rx packet whose DA matches the MAC Address32 content is routed." "0,1,2,3,4,5,6,7" newline hexmask.long.word 0x2D8 0.--15. 1. "ADDRHI,MAC Address32 [47:32] This field contains the upper 16 bits (47:32) of the 33rd 6-byte MAC address." line.long 0x2DC "MAC_ADDRESS91_LOW,The MAC Address32 Low register holds the lower 16 bits of the 33rd 6-byte MAC address of the station." hexmask.long 0x2DC 0.--31. 1. "ADDRLO,MAC Address32 [31:0] This field contains the lower 32 bits of the 33rd 6-byte MAC address. The content of this field is undefined until loaded by the Application after the initialization process." line.long 0x2E0 "MAC_ADDRESS92_HIGH,The MAC Address32 High register holds the upper 16 bits of the 33rd 6-byte MAC address of the station. If the MAC address registers are configured to be double-synchronized to the (G)MII clock domains. the synchronization is triggered.." bitfld.long 0x2E0 31. "AE,Address Enable When this bit is set the Address filter module uses the 33rd MAC address for perfect filtering. When this bit is reset the address filter module ignores the address for filtering. 0x0: Address is ignored 0x1: Address is enabled" "Address is ignored,Address is enabled" newline hexmask.long.word 0x2E0 19.--30. 1. "RESERVED_30_Y,Reserved." newline bitfld.long 0x2E0 16.--18. "DCS,DMA Channel Select This field contains the DMA Channel number to which an Rx packet whose DA matches the MAC Address32 content is routed." "0,1,2,3,4,5,6,7" newline hexmask.long.word 0x2E0 0.--15. 1. "ADDRHI,MAC Address32 [47:32] This field contains the upper 16 bits (47:32) of the 33rd 6-byte MAC address." line.long 0x2E4 "MAC_ADDRESS92_LOW,The MAC Address32 Low register holds the lower 16 bits of the 33rd 6-byte MAC address of the station." hexmask.long 0x2E4 0.--31. 1. "ADDRLO,MAC Address32 [31:0] This field contains the lower 32 bits of the 33rd 6-byte MAC address. The content of this field is undefined until loaded by the Application after the initialization process." line.long 0x2E8 "MAC_ADDRESS93_HIGH,The MAC Address32 High register holds the upper 16 bits of the 33rd 6-byte MAC address of the station. If the MAC address registers are configured to be double-synchronized to the (G)MII clock domains. the synchronization is triggered.." bitfld.long 0x2E8 31. "AE,Address Enable When this bit is set the Address filter module uses the 33rd MAC address for perfect filtering. When this bit is reset the address filter module ignores the address for filtering. 0x0: Address is ignored 0x1: Address is enabled" "Address is ignored,Address is enabled" newline hexmask.long.word 0x2E8 19.--30. 1. "RESERVED_30_Y,Reserved." newline bitfld.long 0x2E8 16.--18. "DCS,DMA Channel Select This field contains the DMA Channel number to which an Rx packet whose DA matches the MAC Address32 content is routed." "0,1,2,3,4,5,6,7" newline hexmask.long.word 0x2E8 0.--15. 1. "ADDRHI,MAC Address32 [47:32] This field contains the upper 16 bits (47:32) of the 33rd 6-byte MAC address." line.long 0x2EC "MAC_ADDRESS93_LOW,The MAC Address32 Low register holds the lower 16 bits of the 33rd 6-byte MAC address of the station." hexmask.long 0x2EC 0.--31. 1. "ADDRLO,MAC Address32 [31:0] This field contains the lower 32 bits of the 33rd 6-byte MAC address. The content of this field is undefined until loaded by the Application after the initialization process." line.long 0x2F0 "MAC_ADDRESS94_HIGH,The MAC Address32 High register holds the upper 16 bits of the 33rd 6-byte MAC address of the station. If the MAC address registers are configured to be double-synchronized to the (G)MII clock domains. the synchronization is triggered.." bitfld.long 0x2F0 31. "AE,Address Enable When this bit is set the Address filter module uses the 33rd MAC address for perfect filtering. When this bit is reset the address filter module ignores the address for filtering. 0x0: Address is ignored 0x1: Address is enabled" "Address is ignored,Address is enabled" newline hexmask.long.word 0x2F0 19.--30. 1. "RESERVED_30_Y,Reserved." newline bitfld.long 0x2F0 16.--18. "DCS,DMA Channel Select This field contains the DMA Channel number to which an Rx packet whose DA matches the MAC Address32 content is routed." "0,1,2,3,4,5,6,7" newline hexmask.long.word 0x2F0 0.--15. 1. "ADDRHI,MAC Address32 [47:32] This field contains the upper 16 bits (47:32) of the 33rd 6-byte MAC address." line.long 0x2F4 "MAC_ADDRESS94_LOW,The MAC Address32 Low register holds the lower 16 bits of the 33rd 6-byte MAC address of the station." hexmask.long 0x2F4 0.--31. 1. "ADDRLO,MAC Address32 [31:0] This field contains the lower 32 bits of the 33rd 6-byte MAC address. The content of this field is undefined until loaded by the Application after the initialization process." line.long 0x2F8 "MAC_ADDRESS95_HIGH,The MAC Address32 High register holds the upper 16 bits of the 33rd 6-byte MAC address of the station. If the MAC address registers are configured to be double-synchronized to the (G)MII clock domains. the synchronization is triggered.." bitfld.long 0x2F8 31. "AE,Address Enable When this bit is set the Address filter module uses the 33rd MAC address for perfect filtering. When this bit is reset the address filter module ignores the address for filtering. 0x0: Address is ignored 0x1: Address is enabled" "Address is ignored,Address is enabled" newline hexmask.long.word 0x2F8 19.--30. 1. "RESERVED_30_Y,Reserved." newline bitfld.long 0x2F8 16.--18. "DCS,DMA Channel Select This field contains the DMA Channel number to which an Rx packet whose DA matches the MAC Address32 content is routed." "0,1,2,3,4,5,6,7" newline hexmask.long.word 0x2F8 0.--15. 1. "ADDRHI,MAC Address32 [47:32] This field contains the upper 16 bits (47:32) of the 33rd 6-byte MAC address." line.long 0x2FC "MAC_ADDRESS95_LOW,The MAC Address32 Low register holds the lower 16 bits of the 33rd 6-byte MAC address of the station." hexmask.long 0x2FC 0.--31. 1. "ADDRLO,MAC Address32 [31:0] This field contains the lower 32 bits of the 33rd 6-byte MAC address. The content of this field is undefined until loaded by the Application after the initialization process." line.long 0x300 "MAC_ADDRESS96_HIGH,The MAC Address32 High register holds the upper 16 bits of the 33rd 6-byte MAC address of the station. If the MAC address registers are configured to be double-synchronized to the (G)MII clock domains. the synchronization is triggered.." bitfld.long 0x300 31. "AE,Address Enable When this bit is set the Address filter module uses the 33rd MAC address for perfect filtering. When this bit is reset the address filter module ignores the address for filtering. 0x0: Address is ignored 0x1: Address is enabled" "Address is ignored,Address is enabled" newline hexmask.long.word 0x300 19.--30. 1. "RESERVED_30_Y,Reserved." newline bitfld.long 0x300 16.--18. "DCS,DMA Channel Select This field contains the DMA Channel number to which an Rx packet whose DA matches the MAC Address32 content is routed." "0,1,2,3,4,5,6,7" newline hexmask.long.word 0x300 0.--15. 1. "ADDRHI,MAC Address32 [47:32] This field contains the upper 16 bits (47:32) of the 33rd 6-byte MAC address." line.long 0x304 "MAC_ADDRESS96_LOW,The MAC Address32 Low register holds the lower 16 bits of the 33rd 6-byte MAC address of the station." hexmask.long 0x304 0.--31. 1. "ADDRLO,MAC Address32 [31:0] This field contains the lower 32 bits of the 33rd 6-byte MAC address. The content of this field is undefined until loaded by the Application after the initialization process." line.long 0x308 "MAC_ADDRESS97_HIGH,The MAC Address32 High register holds the upper 16 bits of the 33rd 6-byte MAC address of the station. If the MAC address registers are configured to be double-synchronized to the (G)MII clock domains. the synchronization is triggered.." bitfld.long 0x308 31. "AE,Address Enable When this bit is set the Address filter module uses the 33rd MAC address for perfect filtering. When this bit is reset the address filter module ignores the address for filtering. 0x0: Address is ignored 0x1: Address is enabled" "Address is ignored,Address is enabled" newline hexmask.long.word 0x308 19.--30. 1. "RESERVED_30_Y,Reserved." newline bitfld.long 0x308 16.--18. "DCS,DMA Channel Select This field contains the DMA Channel number to which an Rx packet whose DA matches the MAC Address32 content is routed." "0,1,2,3,4,5,6,7" newline hexmask.long.word 0x308 0.--15. 1. "ADDRHI,MAC Address32 [47:32] This field contains the upper 16 bits (47:32) of the 33rd 6-byte MAC address." line.long 0x30C "MAC_ADDRESS97_LOW,The MAC Address32 Low register holds the lower 16 bits of the 33rd 6-byte MAC address of the station." hexmask.long 0x30C 0.--31. 1. "ADDRLO,MAC Address32 [31:0] This field contains the lower 32 bits of the 33rd 6-byte MAC address. The content of this field is undefined until loaded by the Application after the initialization process." line.long 0x310 "MAC_ADDRESS98_HIGH,The MAC Address32 High register holds the upper 16 bits of the 33rd 6-byte MAC address of the station. If the MAC address registers are configured to be double-synchronized to the (G)MII clock domains. the synchronization is triggered.." bitfld.long 0x310 31. "AE,Address Enable When this bit is set the Address filter module uses the 33rd MAC address for perfect filtering. When this bit is reset the address filter module ignores the address for filtering. 0x0: Address is ignored 0x1: Address is enabled" "Address is ignored,Address is enabled" newline hexmask.long.word 0x310 19.--30. 1. "RESERVED_30_Y,Reserved." newline bitfld.long 0x310 16.--18. "DCS,DMA Channel Select This field contains the DMA Channel number to which an Rx packet whose DA matches the MAC Address32 content is routed." "0,1,2,3,4,5,6,7" newline hexmask.long.word 0x310 0.--15. 1. "ADDRHI,MAC Address32 [47:32] This field contains the upper 16 bits (47:32) of the 33rd 6-byte MAC address." line.long 0x314 "MAC_ADDRESS98_LOW,The MAC Address32 Low register holds the lower 16 bits of the 33rd 6-byte MAC address of the station." hexmask.long 0x314 0.--31. 1. "ADDRLO,MAC Address32 [31:0] This field contains the lower 32 bits of the 33rd 6-byte MAC address. The content of this field is undefined until loaded by the Application after the initialization process." line.long 0x318 "MAC_ADDRESS99_HIGH,The MAC Address32 High register holds the upper 16 bits of the 33rd 6-byte MAC address of the station. If the MAC address registers are configured to be double-synchronized to the (G)MII clock domains. the synchronization is triggered.." bitfld.long 0x318 31. "AE,Address Enable When this bit is set the Address filter module uses the 33rd MAC address for perfect filtering. When this bit is reset the address filter module ignores the address for filtering. 0x0: Address is ignored 0x1: Address is enabled" "Address is ignored,Address is enabled" newline hexmask.long.word 0x318 19.--30. 1. "RESERVED_30_Y,Reserved." newline bitfld.long 0x318 16.--18. "DCS,DMA Channel Select This field contains the DMA Channel number to which an Rx packet whose DA matches the MAC Address32 content is routed." "0,1,2,3,4,5,6,7" newline hexmask.long.word 0x318 0.--15. 1. "ADDRHI,MAC Address32 [47:32] This field contains the upper 16 bits (47:32) of the 33rd 6-byte MAC address." line.long 0x31C "MAC_ADDRESS99_LOW,The MAC Address32 Low register holds the lower 16 bits of the 33rd 6-byte MAC address of the station." hexmask.long 0x31C 0.--31. 1. "ADDRLO,MAC Address32 [31:0] This field contains the lower 32 bits of the 33rd 6-byte MAC address. The content of this field is undefined until loaded by the Application after the initialization process." line.long 0x320 "MAC_ADDRESS100_HIGH,The MAC Address32 High register holds the upper 16 bits of the 33rd 6-byte MAC address of the station. If the MAC address registers are configured to be double-synchronized to the (G)MII clock domains. the synchronization is triggered.." bitfld.long 0x320 31. "AE,Address Enable When this bit is set the Address filter module uses the 33rd MAC address for perfect filtering. When this bit is reset the address filter module ignores the address for filtering. 0x0: Address is ignored 0x1: Address is enabled" "Address is ignored,Address is enabled" newline hexmask.long.word 0x320 19.--30. 1. "RESERVED_30_Y,Reserved." newline bitfld.long 0x320 16.--18. "DCS,DMA Channel Select This field contains the DMA Channel number to which an Rx packet whose DA matches the MAC Address32 content is routed." "0,1,2,3,4,5,6,7" newline hexmask.long.word 0x320 0.--15. 1. "ADDRHI,MAC Address32 [47:32] This field contains the upper 16 bits (47:32) of the 33rd 6-byte MAC address." line.long 0x324 "MAC_ADDRESS100_LOW,The MAC Address32 Low register holds the lower 16 bits of the 33rd 6-byte MAC address of the station." hexmask.long 0x324 0.--31. 1. "ADDRLO,MAC Address32 [31:0] This field contains the lower 32 bits of the 33rd 6-byte MAC address. The content of this field is undefined until loaded by the Application after the initialization process." line.long 0x328 "MAC_ADDRESS101_HIGH,The MAC Address32 High register holds the upper 16 bits of the 33rd 6-byte MAC address of the station. If the MAC address registers are configured to be double-synchronized to the (G)MII clock domains. the synchronization is triggered.." bitfld.long 0x328 31. "AE,Address Enable When this bit is set the Address filter module uses the 33rd MAC address for perfect filtering. When this bit is reset the address filter module ignores the address for filtering. 0x0: Address is ignored 0x1: Address is enabled" "Address is ignored,Address is enabled" newline hexmask.long.word 0x328 19.--30. 1. "RESERVED_30_Y,Reserved." newline bitfld.long 0x328 16.--18. "DCS,DMA Channel Select This field contains the DMA Channel number to which an Rx packet whose DA matches the MAC Address32 content is routed." "0,1,2,3,4,5,6,7" newline hexmask.long.word 0x328 0.--15. 1. "ADDRHI,MAC Address32 [47:32] This field contains the upper 16 bits (47:32) of the 33rd 6-byte MAC address." line.long 0x32C "MAC_ADDRESS101_LOW,The MAC Address32 Low register holds the lower 16 bits of the 33rd 6-byte MAC address of the station." hexmask.long 0x32C 0.--31. 1. "ADDRLO,MAC Address32 [31:0] This field contains the lower 32 bits of the 33rd 6-byte MAC address. The content of this field is undefined until loaded by the Application after the initialization process." line.long 0x330 "MAC_ADDRESS102_HIGH,The MAC Address32 High register holds the upper 16 bits of the 33rd 6-byte MAC address of the station. If the MAC address registers are configured to be double-synchronized to the (G)MII clock domains. the synchronization is triggered.." bitfld.long 0x330 31. "AE,Address Enable When this bit is set the Address filter module uses the 33rd MAC address for perfect filtering. When this bit is reset the address filter module ignores the address for filtering. 0x0: Address is ignored 0x1: Address is enabled" "Address is ignored,Address is enabled" newline hexmask.long.word 0x330 19.--30. 1. "RESERVED_30_Y,Reserved." newline bitfld.long 0x330 16.--18. "DCS,DMA Channel Select This field contains the DMA Channel number to which an Rx packet whose DA matches the MAC Address32 content is routed." "0,1,2,3,4,5,6,7" newline hexmask.long.word 0x330 0.--15. 1. "ADDRHI,MAC Address32 [47:32] This field contains the upper 16 bits (47:32) of the 33rd 6-byte MAC address." line.long 0x334 "MAC_ADDRESS102_LOW,The MAC Address32 Low register holds the lower 16 bits of the 33rd 6-byte MAC address of the station." hexmask.long 0x334 0.--31. 1. "ADDRLO,MAC Address32 [31:0] This field contains the lower 32 bits of the 33rd 6-byte MAC address. The content of this field is undefined until loaded by the Application after the initialization process." line.long 0x338 "MAC_ADDRESS103_HIGH,The MAC Address32 High register holds the upper 16 bits of the 33rd 6-byte MAC address of the station. If the MAC address registers are configured to be double-synchronized to the (G)MII clock domains. the synchronization is triggered.." bitfld.long 0x338 31. "AE,Address Enable When this bit is set the Address filter module uses the 33rd MAC address for perfect filtering. When this bit is reset the address filter module ignores the address for filtering. 0x0: Address is ignored 0x1: Address is enabled" "Address is ignored,Address is enabled" newline hexmask.long.word 0x338 19.--30. 1. "RESERVED_30_Y,Reserved." newline bitfld.long 0x338 16.--18. "DCS,DMA Channel Select This field contains the DMA Channel number to which an Rx packet whose DA matches the MAC Address32 content is routed." "0,1,2,3,4,5,6,7" newline hexmask.long.word 0x338 0.--15. 1. "ADDRHI,MAC Address32 [47:32] This field contains the upper 16 bits (47:32) of the 33rd 6-byte MAC address." line.long 0x33C "MAC_ADDRESS103_LOW,The MAC Address32 Low register holds the lower 16 bits of the 33rd 6-byte MAC address of the station." hexmask.long 0x33C 0.--31. 1. "ADDRLO,MAC Address32 [31:0] This field contains the lower 32 bits of the 33rd 6-byte MAC address. The content of this field is undefined until loaded by the Application after the initialization process." line.long 0x340 "MAC_ADDRESS104_HIGH,The MAC Address32 High register holds the upper 16 bits of the 33rd 6-byte MAC address of the station. If the MAC address registers are configured to be double-synchronized to the (G)MII clock domains. the synchronization is triggered.." bitfld.long 0x340 31. "AE,Address Enable When this bit is set the Address filter module uses the 33rd MAC address for perfect filtering. When this bit is reset the address filter module ignores the address for filtering. 0x0: Address is ignored 0x1: Address is enabled" "Address is ignored,Address is enabled" newline hexmask.long.word 0x340 19.--30. 1. "RESERVED_30_Y,Reserved." newline bitfld.long 0x340 16.--18. "DCS,DMA Channel Select This field contains the DMA Channel number to which an Rx packet whose DA matches the MAC Address32 content is routed." "0,1,2,3,4,5,6,7" newline hexmask.long.word 0x340 0.--15. 1. "ADDRHI,MAC Address32 [47:32] This field contains the upper 16 bits (47:32) of the 33rd 6-byte MAC address." line.long 0x344 "MAC_ADDRESS104_LOW,The MAC Address32 Low register holds the lower 16 bits of the 33rd 6-byte MAC address of the station." hexmask.long 0x344 0.--31. 1. "ADDRLO,MAC Address32 [31:0] This field contains the lower 32 bits of the 33rd 6-byte MAC address. The content of this field is undefined until loaded by the Application after the initialization process." line.long 0x348 "MAC_ADDRESS105_HIGH,The MAC Address32 High register holds the upper 16 bits of the 33rd 6-byte MAC address of the station. If the MAC address registers are configured to be double-synchronized to the (G)MII clock domains. the synchronization is triggered.." bitfld.long 0x348 31. "AE,Address Enable When this bit is set the Address filter module uses the 33rd MAC address for perfect filtering. When this bit is reset the address filter module ignores the address for filtering. 0x0: Address is ignored 0x1: Address is enabled" "Address is ignored,Address is enabled" newline hexmask.long.word 0x348 19.--30. 1. "RESERVED_30_Y,Reserved." newline bitfld.long 0x348 16.--18. "DCS,DMA Channel Select This field contains the DMA Channel number to which an Rx packet whose DA matches the MAC Address32 content is routed." "0,1,2,3,4,5,6,7" newline hexmask.long.word 0x348 0.--15. 1. "ADDRHI,MAC Address32 [47:32] This field contains the upper 16 bits (47:32) of the 33rd 6-byte MAC address." line.long 0x34C "MAC_ADDRESS105_LOW,The MAC Address32 Low register holds the lower 16 bits of the 33rd 6-byte MAC address of the station." hexmask.long 0x34C 0.--31. 1. "ADDRLO,MAC Address32 [31:0] This field contains the lower 32 bits of the 33rd 6-byte MAC address. The content of this field is undefined until loaded by the Application after the initialization process." line.long 0x350 "MAC_ADDRESS106_HIGH,The MAC Address32 High register holds the upper 16 bits of the 33rd 6-byte MAC address of the station. If the MAC address registers are configured to be double-synchronized to the (G)MII clock domains. the synchronization is triggered.." bitfld.long 0x350 31. "AE,Address Enable When this bit is set the Address filter module uses the 33rd MAC address for perfect filtering. When this bit is reset the address filter module ignores the address for filtering. 0x0: Address is ignored 0x1: Address is enabled" "Address is ignored,Address is enabled" newline hexmask.long.word 0x350 19.--30. 1. "RESERVED_30_Y,Reserved." newline bitfld.long 0x350 16.--18. "DCS,DMA Channel Select This field contains the DMA Channel number to which an Rx packet whose DA matches the MAC Address32 content is routed." "0,1,2,3,4,5,6,7" newline hexmask.long.word 0x350 0.--15. 1. "ADDRHI,MAC Address32 [47:32] This field contains the upper 16 bits (47:32) of the 33rd 6-byte MAC address." line.long 0x354 "MAC_ADDRESS106_LOW,The MAC Address32 Low register holds the lower 16 bits of the 33rd 6-byte MAC address of the station." hexmask.long 0x354 0.--31. 1. "ADDRLO,MAC Address32 [31:0] This field contains the lower 32 bits of the 33rd 6-byte MAC address. The content of this field is undefined until loaded by the Application after the initialization process." line.long 0x358 "MAC_ADDRESS107_HIGH,The MAC Address32 High register holds the upper 16 bits of the 33rd 6-byte MAC address of the station. If the MAC address registers are configured to be double-synchronized to the (G)MII clock domains. the synchronization is triggered.." bitfld.long 0x358 31. "AE,Address Enable When this bit is set the Address filter module uses the 33rd MAC address for perfect filtering. When this bit is reset the address filter module ignores the address for filtering. 0x0: Address is ignored 0x1: Address is enabled" "Address is ignored,Address is enabled" newline hexmask.long.word 0x358 19.--30. 1. "RESERVED_30_Y,Reserved." newline bitfld.long 0x358 16.--18. "DCS,DMA Channel Select This field contains the DMA Channel number to which an Rx packet whose DA matches the MAC Address32 content is routed." "0,1,2,3,4,5,6,7" newline hexmask.long.word 0x358 0.--15. 1. "ADDRHI,MAC Address32 [47:32] This field contains the upper 16 bits (47:32) of the 33rd 6-byte MAC address." line.long 0x35C "MAC_ADDRESS107_LOW,The MAC Address32 Low register holds the lower 16 bits of the 33rd 6-byte MAC address of the station." hexmask.long 0x35C 0.--31. 1. "ADDRLO,MAC Address32 [31:0] This field contains the lower 32 bits of the 33rd 6-byte MAC address. The content of this field is undefined until loaded by the Application after the initialization process." line.long 0x360 "MAC_ADDRESS108_HIGH,The MAC Address32 High register holds the upper 16 bits of the 33rd 6-byte MAC address of the station. If the MAC address registers are configured to be double-synchronized to the (G)MII clock domains. the synchronization is triggered.." bitfld.long 0x360 31. "AE,Address Enable When this bit is set the Address filter module uses the 33rd MAC address for perfect filtering. When this bit is reset the address filter module ignores the address for filtering. 0x0: Address is ignored 0x1: Address is enabled" "Address is ignored,Address is enabled" newline hexmask.long.word 0x360 19.--30. 1. "RESERVED_30_Y,Reserved." newline bitfld.long 0x360 16.--18. "DCS,DMA Channel Select This field contains the DMA Channel number to which an Rx packet whose DA matches the MAC Address32 content is routed." "0,1,2,3,4,5,6,7" newline hexmask.long.word 0x360 0.--15. 1. "ADDRHI,MAC Address32 [47:32] This field contains the upper 16 bits (47:32) of the 33rd 6-byte MAC address." line.long 0x364 "MAC_ADDRESS108_LOW,The MAC Address32 Low register holds the lower 16 bits of the 33rd 6-byte MAC address of the station." hexmask.long 0x364 0.--31. 1. "ADDRLO,MAC Address32 [31:0] This field contains the lower 32 bits of the 33rd 6-byte MAC address. The content of this field is undefined until loaded by the Application after the initialization process." line.long 0x368 "MAC_ADDRESS109_HIGH,The MAC Address32 High register holds the upper 16 bits of the 33rd 6-byte MAC address of the station. If the MAC address registers are configured to be double-synchronized to the (G)MII clock domains. the synchronization is triggered.." bitfld.long 0x368 31. "AE,Address Enable When this bit is set the Address filter module uses the 33rd MAC address for perfect filtering. When this bit is reset the address filter module ignores the address for filtering. 0x0: Address is ignored 0x1: Address is enabled" "Address is ignored,Address is enabled" newline hexmask.long.word 0x368 19.--30. 1. "RESERVED_30_Y,Reserved." newline bitfld.long 0x368 16.--18. "DCS,DMA Channel Select This field contains the DMA Channel number to which an Rx packet whose DA matches the MAC Address32 content is routed." "0,1,2,3,4,5,6,7" newline hexmask.long.word 0x368 0.--15. 1. "ADDRHI,MAC Address32 [47:32] This field contains the upper 16 bits (47:32) of the 33rd 6-byte MAC address." line.long 0x36C "MAC_ADDRESS109_LOW,The MAC Address32 Low register holds the lower 16 bits of the 33rd 6-byte MAC address of the station." hexmask.long 0x36C 0.--31. 1. "ADDRLO,MAC Address32 [31:0] This field contains the lower 32 bits of the 33rd 6-byte MAC address. The content of this field is undefined until loaded by the Application after the initialization process." line.long 0x370 "MAC_ADDRESS110_HIGH,The MAC Address32 High register holds the upper 16 bits of the 33rd 6-byte MAC address of the station. If the MAC address registers are configured to be double-synchronized to the (G)MII clock domains. the synchronization is triggered.." bitfld.long 0x370 31. "AE,Address Enable When this bit is set the Address filter module uses the 33rd MAC address for perfect filtering. When this bit is reset the address filter module ignores the address for filtering. 0x0: Address is ignored 0x1: Address is enabled" "Address is ignored,Address is enabled" newline hexmask.long.word 0x370 19.--30. 1. "RESERVED_30_Y,Reserved." newline bitfld.long 0x370 16.--18. "DCS,DMA Channel Select This field contains the DMA Channel number to which an Rx packet whose DA matches the MAC Address32 content is routed." "0,1,2,3,4,5,6,7" newline hexmask.long.word 0x370 0.--15. 1. "ADDRHI,MAC Address32 [47:32] This field contains the upper 16 bits (47:32) of the 33rd 6-byte MAC address." line.long 0x374 "MAC_ADDRESS110_LOW,The MAC Address32 Low register holds the lower 16 bits of the 33rd 6-byte MAC address of the station." hexmask.long 0x374 0.--31. 1. "ADDRLO,MAC Address32 [31:0] This field contains the lower 32 bits of the 33rd 6-byte MAC address. The content of this field is undefined until loaded by the Application after the initialization process." line.long 0x378 "MAC_ADDRESS111_HIGH,The MAC Address32 High register holds the upper 16 bits of the 33rd 6-byte MAC address of the station. If the MAC address registers are configured to be double-synchronized to the (G)MII clock domains. the synchronization is triggered.." bitfld.long 0x378 31. "AE,Address Enable When this bit is set the Address filter module uses the 33rd MAC address for perfect filtering. When this bit is reset the address filter module ignores the address for filtering. 0x0: Address is ignored 0x1: Address is enabled" "Address is ignored,Address is enabled" newline hexmask.long.word 0x378 19.--30. 1. "RESERVED_30_Y,Reserved." newline bitfld.long 0x378 16.--18. "DCS,DMA Channel Select This field contains the DMA Channel number to which an Rx packet whose DA matches the MAC Address32 content is routed." "0,1,2,3,4,5,6,7" newline hexmask.long.word 0x378 0.--15. 1. "ADDRHI,MAC Address32 [47:32] This field contains the upper 16 bits (47:32) of the 33rd 6-byte MAC address." line.long 0x37C "MAC_ADDRESS111_LOW,The MAC Address32 Low register holds the lower 16 bits of the 33rd 6-byte MAC address of the station." hexmask.long 0x37C 0.--31. 1. "ADDRLO,MAC Address32 [31:0] This field contains the lower 32 bits of the 33rd 6-byte MAC address. The content of this field is undefined until loaded by the Application after the initialization process." line.long 0x380 "MAC_ADDRESS112_HIGH,The MAC Address32 High register holds the upper 16 bits of the 33rd 6-byte MAC address of the station. If the MAC address registers are configured to be double-synchronized to the (G)MII clock domains. the synchronization is triggered.." bitfld.long 0x380 31. "AE,Address Enable When this bit is set the Address filter module uses the 33rd MAC address for perfect filtering. When this bit is reset the address filter module ignores the address for filtering. 0x0: Address is ignored 0x1: Address is enabled" "Address is ignored,Address is enabled" newline hexmask.long.word 0x380 19.--30. 1. "RESERVED_30_Y,Reserved." newline bitfld.long 0x380 16.--18. "DCS,DMA Channel Select This field contains the DMA Channel number to which an Rx packet whose DA matches the MAC Address32 content is routed." "0,1,2,3,4,5,6,7" newline hexmask.long.word 0x380 0.--15. 1. "ADDRHI,MAC Address32 [47:32] This field contains the upper 16 bits (47:32) of the 33rd 6-byte MAC address." line.long 0x384 "MAC_ADDRESS112_LOW,The MAC Address32 Low register holds the lower 16 bits of the 33rd 6-byte MAC address of the station." hexmask.long 0x384 0.--31. 1. "ADDRLO,MAC Address32 [31:0] This field contains the lower 32 bits of the 33rd 6-byte MAC address. The content of this field is undefined until loaded by the Application after the initialization process." line.long 0x388 "MAC_ADDRESS113_HIGH,The MAC Address32 High register holds the upper 16 bits of the 33rd 6-byte MAC address of the station. If the MAC address registers are configured to be double-synchronized to the (G)MII clock domains. the synchronization is triggered.." bitfld.long 0x388 31. "AE,Address Enable When this bit is set the Address filter module uses the 33rd MAC address for perfect filtering. When this bit is reset the address filter module ignores the address for filtering. 0x0: Address is ignored 0x1: Address is enabled" "Address is ignored,Address is enabled" newline hexmask.long.word 0x388 19.--30. 1. "RESERVED_30_Y,Reserved." newline bitfld.long 0x388 16.--18. "DCS,DMA Channel Select This field contains the DMA Channel number to which an Rx packet whose DA matches the MAC Address32 content is routed." "0,1,2,3,4,5,6,7" newline hexmask.long.word 0x388 0.--15. 1. "ADDRHI,MAC Address32 [47:32] This field contains the upper 16 bits (47:32) of the 33rd 6-byte MAC address." line.long 0x38C "MAC_ADDRESS113_LOW,The MAC Address32 Low register holds the lower 16 bits of the 33rd 6-byte MAC address of the station." hexmask.long 0x38C 0.--31. 1. "ADDRLO,MAC Address32 [31:0] This field contains the lower 32 bits of the 33rd 6-byte MAC address. The content of this field is undefined until loaded by the Application after the initialization process." line.long 0x390 "MAC_ADDRESS114_HIGH,The MAC Address32 High register holds the upper 16 bits of the 33rd 6-byte MAC address of the station. If the MAC address registers are configured to be double-synchronized to the (G)MII clock domains. the synchronization is triggered.." bitfld.long 0x390 31. "AE,Address Enable When this bit is set the Address filter module uses the 33rd MAC address for perfect filtering. When this bit is reset the address filter module ignores the address for filtering. 0x0: Address is ignored 0x1: Address is enabled" "Address is ignored,Address is enabled" newline hexmask.long.word 0x390 19.--30. 1. "RESERVED_30_Y,Reserved." newline bitfld.long 0x390 16.--18. "DCS,DMA Channel Select This field contains the DMA Channel number to which an Rx packet whose DA matches the MAC Address32 content is routed." "0,1,2,3,4,5,6,7" newline hexmask.long.word 0x390 0.--15. 1. "ADDRHI,MAC Address32 [47:32] This field contains the upper 16 bits (47:32) of the 33rd 6-byte MAC address." line.long 0x394 "MAC_ADDRESS114_LOW,The MAC Address32 Low register holds the lower 16 bits of the 33rd 6-byte MAC address of the station." hexmask.long 0x394 0.--31. 1. "ADDRLO,MAC Address32 [31:0] This field contains the lower 32 bits of the 33rd 6-byte MAC address. The content of this field is undefined until loaded by the Application after the initialization process." line.long 0x398 "MAC_ADDRESS115_HIGH,The MAC Address32 High register holds the upper 16 bits of the 33rd 6-byte MAC address of the station. If the MAC address registers are configured to be double-synchronized to the (G)MII clock domains. the synchronization is triggered.." bitfld.long 0x398 31. "AE,Address Enable When this bit is set the Address filter module uses the 33rd MAC address for perfect filtering. When this bit is reset the address filter module ignores the address for filtering. 0x0: Address is ignored 0x1: Address is enabled" "Address is ignored,Address is enabled" newline hexmask.long.word 0x398 19.--30. 1. "RESERVED_30_Y,Reserved." newline bitfld.long 0x398 16.--18. "DCS,DMA Channel Select This field contains the DMA Channel number to which an Rx packet whose DA matches the MAC Address32 content is routed." "0,1,2,3,4,5,6,7" newline hexmask.long.word 0x398 0.--15. 1. "ADDRHI,MAC Address32 [47:32] This field contains the upper 16 bits (47:32) of the 33rd 6-byte MAC address." line.long 0x39C "MAC_ADDRESS115_LOW,The MAC Address32 Low register holds the lower 16 bits of the 33rd 6-byte MAC address of the station." hexmask.long 0x39C 0.--31. 1. "ADDRLO,MAC Address32 [31:0] This field contains the lower 32 bits of the 33rd 6-byte MAC address. The content of this field is undefined until loaded by the Application after the initialization process." line.long 0x3A0 "MAC_ADDRESS116_HIGH,The MAC Address32 High register holds the upper 16 bits of the 33rd 6-byte MAC address of the station. If the MAC address registers are configured to be double-synchronized to the (G)MII clock domains. the synchronization is triggered.." bitfld.long 0x3A0 31. "AE,Address Enable When this bit is set the Address filter module uses the 33rd MAC address for perfect filtering. When this bit is reset the address filter module ignores the address for filtering. 0x0: Address is ignored 0x1: Address is enabled" "Address is ignored,Address is enabled" newline hexmask.long.word 0x3A0 19.--30. 1. "RESERVED_30_Y,Reserved." newline bitfld.long 0x3A0 16.--18. "DCS,DMA Channel Select This field contains the DMA Channel number to which an Rx packet whose DA matches the MAC Address32 content is routed." "0,1,2,3,4,5,6,7" newline hexmask.long.word 0x3A0 0.--15. 1. "ADDRHI,MAC Address32 [47:32] This field contains the upper 16 bits (47:32) of the 33rd 6-byte MAC address." line.long 0x3A4 "MAC_ADDRESS116_LOW,The MAC Address32 Low register holds the lower 16 bits of the 33rd 6-byte MAC address of the station." hexmask.long 0x3A4 0.--31. 1. "ADDRLO,MAC Address32 [31:0] This field contains the lower 32 bits of the 33rd 6-byte MAC address. The content of this field is undefined until loaded by the Application after the initialization process." line.long 0x3A8 "MAC_ADDRESS117_HIGH,The MAC Address32 High register holds the upper 16 bits of the 33rd 6-byte MAC address of the station. If the MAC address registers are configured to be double-synchronized to the (G)MII clock domains. the synchronization is triggered.." bitfld.long 0x3A8 31. "AE,Address Enable When this bit is set the Address filter module uses the 33rd MAC address for perfect filtering. When this bit is reset the address filter module ignores the address for filtering. 0x0: Address is ignored 0x1: Address is enabled" "Address is ignored,Address is enabled" newline hexmask.long.word 0x3A8 19.--30. 1. "RESERVED_30_Y,Reserved." newline bitfld.long 0x3A8 16.--18. "DCS,DMA Channel Select This field contains the DMA Channel number to which an Rx packet whose DA matches the MAC Address32 content is routed." "0,1,2,3,4,5,6,7" newline hexmask.long.word 0x3A8 0.--15. 1. "ADDRHI,MAC Address32 [47:32] This field contains the upper 16 bits (47:32) of the 33rd 6-byte MAC address." line.long 0x3AC "MAC_ADDRESS117_LOW,The MAC Address32 Low register holds the lower 16 bits of the 33rd 6-byte MAC address of the station." hexmask.long 0x3AC 0.--31. 1. "ADDRLO,MAC Address32 [31:0] This field contains the lower 32 bits of the 33rd 6-byte MAC address. The content of this field is undefined until loaded by the Application after the initialization process." line.long 0x3B0 "MAC_ADDRESS118_HIGH,The MAC Address32 High register holds the upper 16 bits of the 33rd 6-byte MAC address of the station. If the MAC address registers are configured to be double-synchronized to the (G)MII clock domains. the synchronization is triggered.." bitfld.long 0x3B0 31. "AE,Address Enable When this bit is set the Address filter module uses the 33rd MAC address for perfect filtering. When this bit is reset the address filter module ignores the address for filtering. 0x0: Address is ignored 0x1: Address is enabled" "Address is ignored,Address is enabled" newline hexmask.long.word 0x3B0 19.--30. 1. "RESERVED_30_Y,Reserved." newline bitfld.long 0x3B0 16.--18. "DCS,DMA Channel Select This field contains the DMA Channel number to which an Rx packet whose DA matches the MAC Address32 content is routed." "0,1,2,3,4,5,6,7" newline hexmask.long.word 0x3B0 0.--15. 1. "ADDRHI,MAC Address32 [47:32] This field contains the upper 16 bits (47:32) of the 33rd 6-byte MAC address." line.long 0x3B4 "MAC_ADDRESS118_LOW,The MAC Address32 Low register holds the lower 16 bits of the 33rd 6-byte MAC address of the station." hexmask.long 0x3B4 0.--31. 1. "ADDRLO,MAC Address32 [31:0] This field contains the lower 32 bits of the 33rd 6-byte MAC address. The content of this field is undefined until loaded by the Application after the initialization process." line.long 0x3B8 "MAC_ADDRESS119_HIGH,The MAC Address32 High register holds the upper 16 bits of the 33rd 6-byte MAC address of the station. If the MAC address registers are configured to be double-synchronized to the (G)MII clock domains. the synchronization is triggered.." bitfld.long 0x3B8 31. "AE,Address Enable When this bit is set the Address filter module uses the 33rd MAC address for perfect filtering. When this bit is reset the address filter module ignores the address for filtering. 0x0: Address is ignored 0x1: Address is enabled" "Address is ignored,Address is enabled" newline hexmask.long.word 0x3B8 19.--30. 1. "RESERVED_30_Y,Reserved." newline bitfld.long 0x3B8 16.--18. "DCS,DMA Channel Select This field contains the DMA Channel number to which an Rx packet whose DA matches the MAC Address32 content is routed." "0,1,2,3,4,5,6,7" newline hexmask.long.word 0x3B8 0.--15. 1. "ADDRHI,MAC Address32 [47:32] This field contains the upper 16 bits (47:32) of the 33rd 6-byte MAC address." line.long 0x3BC "MAC_ADDRESS119_LOW,The MAC Address32 Low register holds the lower 16 bits of the 33rd 6-byte MAC address of the station." hexmask.long 0x3BC 0.--31. 1. "ADDRLO,MAC Address32 [31:0] This field contains the lower 32 bits of the 33rd 6-byte MAC address. The content of this field is undefined until loaded by the Application after the initialization process." line.long 0x3C0 "MAC_ADDRESS120_HIGH,The MAC Address32 High register holds the upper 16 bits of the 33rd 6-byte MAC address of the station. If the MAC address registers are configured to be double-synchronized to the (G)MII clock domains. the synchronization is triggered.." bitfld.long 0x3C0 31. "AE,Address Enable When this bit is set the Address filter module uses the 33rd MAC address for perfect filtering. When this bit is reset the address filter module ignores the address for filtering. 0x0: Address is ignored 0x1: Address is enabled" "Address is ignored,Address is enabled" newline hexmask.long.word 0x3C0 19.--30. 1. "RESERVED_30_Y,Reserved." newline bitfld.long 0x3C0 16.--18. "DCS,DMA Channel Select This field contains the DMA Channel number to which an Rx packet whose DA matches the MAC Address32 content is routed." "0,1,2,3,4,5,6,7" newline hexmask.long.word 0x3C0 0.--15. 1. "ADDRHI,MAC Address32 [47:32] This field contains the upper 16 bits (47:32) of the 33rd 6-byte MAC address." line.long 0x3C4 "MAC_ADDRESS120_LOW,The MAC Address32 Low register holds the lower 16 bits of the 33rd 6-byte MAC address of the station." hexmask.long 0x3C4 0.--31. 1. "ADDRLO,MAC Address32 [31:0] This field contains the lower 32 bits of the 33rd 6-byte MAC address. The content of this field is undefined until loaded by the Application after the initialization process." line.long 0x3C8 "MAC_ADDRESS121_HIGH,The MAC Address32 High register holds the upper 16 bits of the 33rd 6-byte MAC address of the station. If the MAC address registers are configured to be double-synchronized to the (G)MII clock domains. the synchronization is triggered.." bitfld.long 0x3C8 31. "AE,Address Enable When this bit is set the Address filter module uses the 33rd MAC address for perfect filtering. When this bit is reset the address filter module ignores the address for filtering. 0x0: Address is ignored 0x1: Address is enabled" "Address is ignored,Address is enabled" newline hexmask.long.word 0x3C8 19.--30. 1. "RESERVED_30_Y,Reserved." newline bitfld.long 0x3C8 16.--18. "DCS,DMA Channel Select This field contains the DMA Channel number to which an Rx packet whose DA matches the MAC Address32 content is routed." "0,1,2,3,4,5,6,7" newline hexmask.long.word 0x3C8 0.--15. 1. "ADDRHI,MAC Address32 [47:32] This field contains the upper 16 bits (47:32) of the 33rd 6-byte MAC address." line.long 0x3CC "MAC_ADDRESS121_LOW,The MAC Address32 Low register holds the lower 16 bits of the 33rd 6-byte MAC address of the station." hexmask.long 0x3CC 0.--31. 1. "ADDRLO,MAC Address32 [31:0] This field contains the lower 32 bits of the 33rd 6-byte MAC address. The content of this field is undefined until loaded by the Application after the initialization process." line.long 0x3D0 "MAC_ADDRESS122_HIGH,The MAC Address32 High register holds the upper 16 bits of the 33rd 6-byte MAC address of the station. If the MAC address registers are configured to be double-synchronized to the (G)MII clock domains. the synchronization is triggered.." bitfld.long 0x3D0 31. "AE,Address Enable When this bit is set the Address filter module uses the 33rd MAC address for perfect filtering. When this bit is reset the address filter module ignores the address for filtering. 0x0: Address is ignored 0x1: Address is enabled" "Address is ignored,Address is enabled" newline hexmask.long.word 0x3D0 19.--30. 1. "RESERVED_30_Y,Reserved." newline bitfld.long 0x3D0 16.--18. "DCS,DMA Channel Select This field contains the DMA Channel number to which an Rx packet whose DA matches the MAC Address32 content is routed." "0,1,2,3,4,5,6,7" newline hexmask.long.word 0x3D0 0.--15. 1. "ADDRHI,MAC Address32 [47:32] This field contains the upper 16 bits (47:32) of the 33rd 6-byte MAC address." line.long 0x3D4 "MAC_ADDRESS122_LOW,The MAC Address32 Low register holds the lower 16 bits of the 33rd 6-byte MAC address of the station." hexmask.long 0x3D4 0.--31. 1. "ADDRLO,MAC Address32 [31:0] This field contains the lower 32 bits of the 33rd 6-byte MAC address. The content of this field is undefined until loaded by the Application after the initialization process." line.long 0x3D8 "MAC_ADDRESS123_HIGH,The MAC Address32 High register holds the upper 16 bits of the 33rd 6-byte MAC address of the station. If the MAC address registers are configured to be double-synchronized to the (G)MII clock domains. the synchronization is triggered.." bitfld.long 0x3D8 31. "AE,Address Enable When this bit is set the Address filter module uses the 33rd MAC address for perfect filtering. When this bit is reset the address filter module ignores the address for filtering. 0x0: Address is ignored 0x1: Address is enabled" "Address is ignored,Address is enabled" newline hexmask.long.word 0x3D8 19.--30. 1. "RESERVED_30_Y,Reserved." newline bitfld.long 0x3D8 16.--18. "DCS,DMA Channel Select This field contains the DMA Channel number to which an Rx packet whose DA matches the MAC Address32 content is routed." "0,1,2,3,4,5,6,7" newline hexmask.long.word 0x3D8 0.--15. 1. "ADDRHI,MAC Address32 [47:32] This field contains the upper 16 bits (47:32) of the 33rd 6-byte MAC address." line.long 0x3DC "MAC_ADDRESS123_LOW,The MAC Address32 Low register holds the lower 16 bits of the 33rd 6-byte MAC address of the station." hexmask.long 0x3DC 0.--31. 1. "ADDRLO,MAC Address32 [31:0] This field contains the lower 32 bits of the 33rd 6-byte MAC address. The content of this field is undefined until loaded by the Application after the initialization process." line.long 0x3E0 "MAC_ADDRESS124_HIGH,The MAC Address32 High register holds the upper 16 bits of the 33rd 6-byte MAC address of the station. If the MAC address registers are configured to be double-synchronized to the (G)MII clock domains. the synchronization is triggered.." bitfld.long 0x3E0 31. "AE,Address Enable When this bit is set the Address filter module uses the 33rd MAC address for perfect filtering. When this bit is reset the address filter module ignores the address for filtering. 0x0: Address is ignored 0x1: Address is enabled" "Address is ignored,Address is enabled" newline hexmask.long.word 0x3E0 19.--30. 1. "RESERVED_30_Y,Reserved." newline bitfld.long 0x3E0 16.--18. "DCS,DMA Channel Select This field contains the DMA Channel number to which an Rx packet whose DA matches the MAC Address32 content is routed." "0,1,2,3,4,5,6,7" newline hexmask.long.word 0x3E0 0.--15. 1. "ADDRHI,MAC Address32 [47:32] This field contains the upper 16 bits (47:32) of the 33rd 6-byte MAC address." line.long 0x3E4 "MAC_ADDRESS124_LOW,The MAC Address32 Low register holds the lower 16 bits of the 33rd 6-byte MAC address of the station." hexmask.long 0x3E4 0.--31. 1. "ADDRLO,MAC Address32 [31:0] This field contains the lower 32 bits of the 33rd 6-byte MAC address. The content of this field is undefined until loaded by the Application after the initialization process." line.long 0x3E8 "MAC_ADDRESS125_HIGH,The MAC Address32 High register holds the upper 16 bits of the 33rd 6-byte MAC address of the station. If the MAC address registers are configured to be double-synchronized to the (G)MII clock domains. the synchronization is triggered.." bitfld.long 0x3E8 31. "AE,Address Enable When this bit is set the Address filter module uses the 33rd MAC address for perfect filtering. When this bit is reset the address filter module ignores the address for filtering. 0x0: Address is ignored 0x1: Address is enabled" "Address is ignored,Address is enabled" newline hexmask.long.word 0x3E8 19.--30. 1. "RESERVED_30_Y,Reserved." newline bitfld.long 0x3E8 16.--18. "DCS,DMA Channel Select This field contains the DMA Channel number to which an Rx packet whose DA matches the MAC Address32 content is routed." "0,1,2,3,4,5,6,7" newline hexmask.long.word 0x3E8 0.--15. 1. "ADDRHI,MAC Address32 [47:32] This field contains the upper 16 bits (47:32) of the 33rd 6-byte MAC address." line.long 0x3EC "MAC_ADDRESS125_LOW,The MAC Address32 Low register holds the lower 16 bits of the 33rd 6-byte MAC address of the station." hexmask.long 0x3EC 0.--31. 1. "ADDRLO,MAC Address32 [31:0] This field contains the lower 32 bits of the 33rd 6-byte MAC address. The content of this field is undefined until loaded by the Application after the initialization process." line.long 0x3F0 "MAC_ADDRESS126_HIGH,The MAC Address32 High register holds the upper 16 bits of the 33rd 6-byte MAC address of the station. If the MAC address registers are configured to be double-synchronized to the (G)MII clock domains. the synchronization is triggered.." bitfld.long 0x3F0 31. "AE,Address Enable When this bit is set the Address filter module uses the 33rd MAC address for perfect filtering. When this bit is reset the address filter module ignores the address for filtering. 0x0: Address is ignored 0x1: Address is enabled" "Address is ignored,Address is enabled" newline hexmask.long.word 0x3F0 19.--30. 1. "RESERVED_30_Y,Reserved." newline bitfld.long 0x3F0 16.--18. "DCS,DMA Channel Select This field contains the DMA Channel number to which an Rx packet whose DA matches the MAC Address32 content is routed." "0,1,2,3,4,5,6,7" newline hexmask.long.word 0x3F0 0.--15. 1. "ADDRHI,MAC Address32 [47:32] This field contains the upper 16 bits (47:32) of the 33rd 6-byte MAC address." line.long 0x3F4 "MAC_ADDRESS126_LOW,The MAC Address32 Low register holds the lower 16 bits of the 33rd 6-byte MAC address of the station." hexmask.long 0x3F4 0.--31. 1. "ADDRLO,MAC Address32 [31:0] This field contains the lower 32 bits of the 33rd 6-byte MAC address. The content of this field is undefined until loaded by the Application after the initialization process." line.long 0x3F8 "MAC_ADDRESS127_HIGH,The MAC Address32 High register holds the upper 16 bits of the 33rd 6-byte MAC address of the station. If the MAC address registers are configured to be double-synchronized to the (G)MII clock domains. the synchronization is triggered.." bitfld.long 0x3F8 31. "AE,Address Enable When this bit is set the Address filter module uses the 33rd MAC address for perfect filtering. When this bit is reset the address filter module ignores the address for filtering. 0x0: Address is ignored 0x1: Address is enabled" "Address is ignored,Address is enabled" newline hexmask.long.word 0x3F8 19.--30. 1. "RESERVED_30_Y,Reserved." newline bitfld.long 0x3F8 16.--18. "DCS,DMA Channel Select This field contains the DMA Channel number to which an Rx packet whose DA matches the MAC Address32 content is routed." "0,1,2,3,4,5,6,7" newline hexmask.long.word 0x3F8 0.--15. 1. "ADDRHI,MAC Address32 [47:32] This field contains the upper 16 bits (47:32) of the 33rd 6-byte MAC address." line.long 0x3FC "MAC_ADDRESS127_LOW,The MAC Address32 Low register holds the lower 16 bits of the 33rd 6-byte MAC address of the station." hexmask.long 0x3FC 0.--31. 1. "ADDRLO,MAC Address32 [31:0] This field contains the lower 32 bits of the 33rd 6-byte MAC address. The content of this field is undefined until loaded by the Application after the initialization process." line.long 0x400 "MMC_CONTROL,This register establishes the operating mode of MMC." hexmask.long.tbyte 0x400 9.--31. 1. "RESERVED_31_9,Reserved." newline bitfld.long 0x400 8. "UCDBC,Update MMC Counters for Dropped Broadcast Packets Note: The CNTRST bit has a higher priority than the CNTPRST bit. Therefore when the software tries to set both bits in the same write cycle all counters are cleared and the CNTPRST bit is not set." "Update MMC Counters for Dropped Broadcast..,Update MMC Counters for Dropped Broadcast.." newline rbitfld.long 0x400 6.--7. "RESERVED_7_6,Reserved." "0,1,2,3" newline bitfld.long 0x400 5. "CNTPRSTLVL,Full-Half Preset When this bit is low and the CNTPRST bit is set all MMC counters get preset to almost-half value. All octet counters get preset to 0x7FFF_F800 (Half 2KBytes) and all packet-counters gets preset to 0x7FFF_FFF0 (Half 16). When.." "Full-Half Preset is disabled,Full-Half Preset is enabled" newline bitfld.long 0x400 4. "CNTPRST,Counters Preset When this bit is set all counters are initialized or preset to almost full or almost half according to the CNTPRSTLVL bit. This bit is cleared automatically after 1 clock cycle. This bit along with the CNTPRSTLVL bit is useful.." "Counters Preset is disabled,Counters Preset is enabled" newline bitfld.long 0x400 3. "CNTFREEZ,MMC Counter Freeze When this bit is set it freezes all MMC counters to their current value. Until this bit is reset to 0 no MMC counter is updated because of any transmitted or received packet. If any MMC counter is read with the Reset on Read.." "MMC Counter Freeze is disabled,MMC Counter Freeze is enabled" newline bitfld.long 0x400 2. "RSTONRD,Reset on Read When this bit is set the MMC counters are reset to zero after Read (self-clearing after reset). The counters are cleared when the least significant byte lane (Bits[7:0]) is read. 0x0: Reset on Read is disabled 0x1: Reset on Read is.." "Reset on Read is disabled,Reset on Read is enabled" newline bitfld.long 0x400 1. "CNTSTOPRO,Counter Stop Rollover When this bit is set the counter does not roll over to zero after reaching the maximum value. 0x0: Counter Stop Rollover is disabled 0x1: Counter Stop Rollover is enabled" "Counter Stop Rollover is disabled,Counter Stop Rollover is enabled" newline bitfld.long 0x400 0. "CNTRST,Counters Reset When this bit is set all counters are reset. This bit is cleared automatically after 1 clock cycle. Access restriction applies. Self-cleared. Setting 0 clears. Setting 1 sets. 0x0: Counters are not reset 0x1: All counters are reset" "Counters are not reset,All counters are reset" rgroup.long 0x704++0x7 line.long 0x0 "MMC_RX_INTERRUPT,This register maintains the interrupts generated from all Receive statistics counters. The MMC Receive Interrupt register maintains the interrupts that are generated when the following occur: - Receive statistic counters reach half of.." hexmask.long.byte 0x0 28.--31. 1. "RESERVED_31_28,Reserved." newline bitfld.long 0x0 27. "RXLPITRCIS,MMC Receive LPI transition counter interrupt status This bit is set when the Rx_LPI_Tran_Cntr counter reaches half of the maximum value or the maximum value. Access restriction applies. Clears on read. Self-set to 1 on internal event. 0x1: MMC.." "MMC Receive LPI transition Counter Interrupt..,MMC Receive LPI transition Counter Interrupt.." newline bitfld.long 0x0 26. "RXLPIUSCIS,MMC Receive LPI microsecond counter interrupt status This bit is set when the Rx_LPI_USEC_Cntr counter reaches half of the maximum value or the maximum value. Access restriction applies. Clears on read. Self-set to 1 on internal event. 0x1:.." "MMC Receive LPI microsecond Counter Interrupt..,MMC Receive LPI microsecond Counter Interrupt.." newline bitfld.long 0x0 25. "RXCTRLPIS,MMC Receive Control Packet Counter Interrupt Status This bit is set when the rxctrlpackets_g counter reaches half of the maximum value or the maximum value. Access restriction applies. Clears on read. Self-set to 1 on internal event. 0x1: MMC.." "MMC Receive Control Packet Counter Interrupt..,MMC Receive Control Packet Counter Interrupt.." newline bitfld.long 0x0 24. "RXRCVERRPIS,MMC Receive Error Packet Counter Interrupt Status This bit is set when the rxrcverror counter reaches half of the maximum value or the maximum value. Access restriction applies. Clears on read. Self-set to 1 on internal event. 0x1: MMC.." "MMC Receive Error Packet Counter Interrupt..,MMC Receive Error Packet Counter Interrupt.." newline bitfld.long 0x0 23. "RXWDOGPIS,MMC Receive Watchdog Error Packet Counter Interrupt Status This bit is set when the rxwatchdog error counter reaches half of the maximum value or the maximum value. Access restriction applies. Clears on read. Self-set to 1 on internal event." "MMC Receive Watchdog Error Packet Counter..,MMC Receive Watchdog Error Packet Counter.." newline bitfld.long 0x0 22. "RXVLANGBPIS,MMC Receive VLAN Good Bad Packet Counter Interrupt Status This bit is set when the rxvlanpackets_gb counter reaches half of the maximum value or the maximum value. Access restriction applies. Clears on read. Self-set to 1 on internal event." "MMC Receive VLAN Good Bad Packet Counter..,MMC Receive VLAN Good Bad Packet Counter.." newline bitfld.long 0x0 21. "RXFOVPIS,MMC Receive FIFO Overflow Packet Counter Interrupt Status This bit is set when the rxfifooverflow counter reaches half of the maximum value or the maximum value. Access restriction applies. Clears on read. Self-set to 1 on internal event. 0x1:.." "MMC Receive FIFO Overflow Packet Counter..,MMC Receive FIFO Overflow Packet Counter.." newline bitfld.long 0x0 20. "RXPAUSPIS,MMC Receive Pause Packet Counter Interrupt Status This bit is set when the rxpausepackets counter reaches half of the maximum value or the maximum value. Access restriction applies. Clears on read. Self-set to 1 on internal event. 0x1: MMC.." "MMC Receive Pause Packet Counter Interrupt..,MMC Receive Pause Packet Counter Interrupt.." newline bitfld.long 0x0 19. "RXORANGEPIS,MMC Receive Out Of Range Error Packet Counter Interrupt Status. This bit is set when the rxoutofrangetype counter reaches half of the maximum value or the maximum value. Access restriction applies. Clears on read. Self-set to 1 on internal.." "MMC Receive Out Of Range Error Packet Counter..,MMC Receive Out Of Range Error Packet Counter.." newline bitfld.long 0x0 18. "RXLENERPIS,MMC Receive Length Error Packet Counter Interrupt Status This bit is set when the rxlengtherror counter reaches half of the maximum value or the maximum value. Access restriction applies. Clears on read. Self-set to 1 on internal event. 0x1:.." "MMC Receive Length Error Packet Counter..,MMC Receive Length Error Packet Counter.." newline bitfld.long 0x0 17. "RXUCGPIS,MMC Receive Unicast Good Packet Counter Interrupt Status This bit is set when the rxunicastpackets_g counter reaches half of the maximum value or the maximum value. Access restriction applies. Clears on read. Self-set to 1 on internal event." "MMC Receive Unicast Good Packet Counter..,MMC Receive Unicast Good Packet Counter.." newline bitfld.long 0x0 16. "RX1024TMAXOCTGBPIS,MMC Receive 1024 to Maximum Octet Good Bad Packet Counter Interrupt Status This bit is set when the rx1024tomaxoctets_gb counter reaches half of the maximum value or the maximum value. Access restriction applies. Clears on read." "MMC Receive 1024 to Maximum Octet Good Bad..,MMC Receive 1024 to Maximum Octet Good Bad.." newline bitfld.long 0x0 15. "RX512T1023OCTGBPIS,MMC Receive 512 to 1023 Octet Good Bad Packet Counter Interrupt Status This bit is set when the rx512to1023octets_gb counter reaches half of the maximum value or the maximum value. Access restriction applies. Clears on read. Self-set.." "MMC Receive 512 to 1023 Octet Good Bad Packet..,MMC Receive 512 to 1023 Octet Good Bad Packet.." newline bitfld.long 0x0 14. "RX256T511OCTGBPIS,MMC Receive 256 to 511 Octet Good Bad Packet Counter Interrupt Status This bit is set when the rx256to511octets_gb counter reaches half of the maximum value or the maximum value. Access restriction applies. Clears on read. Self-set to 1.." "MMC Receive 256 to 511 Octet Good Bad Packet..,MMC Receive 256 to 511 Octet Good Bad Packet.." newline bitfld.long 0x0 13. "RX128T255OCTGBPIS,MMC Receive 128 to 255 Octet Good Bad Packet Counter Interrupt Status This bit is set when the rx128to255octets_gb counter reaches half of the maximum value or the maximum value. Access restriction applies. Clears on read. Self-set to 1.." "MMC Receive 128 to 255 Octet Good Bad Packet..,MMC Receive 128 to 255 Octet Good Bad Packet.." newline bitfld.long 0x0 12. "RX65T127OCTGBPIS,MMC Receive 65 to 127 Octet Good Bad Packet Counter Interrupt Status This bit is set when the rx65to127octets_gb counter reaches half of the maximum value or the maximum value. Access restriction applies. Clears on read. Self-set to 1 on.." "MMC Receive 65 to 127 Octet Good Bad Packet..,MMC Receive 65 to 127 Octet Good Bad Packet.." newline bitfld.long 0x0 11. "RX64OCTGBPIS,MMC Receive 64 Octet Good Bad Packet Counter Interrupt Status This bit is set when the rx64octets_gb counter reaches half of the maximum value or the maximum value. Access restriction applies. Clears on read. Self-set to 1 on internal event." "MMC Receive 64 Octet Good Bad Packet Counter..,MMC Receive 64 Octet Good Bad Packet Counter.." newline bitfld.long 0x0 10. "RXOSIZEGPIS,MMC Receive Oversize Good Packet Counter Interrupt Status This bit is set when the rxoversize_g counter reaches half of the maximum value or the maximum value. Access restriction applies. Clears on read. Self-set to 1 on internal event. 0x1:.." "MMC Receive Oversize Good Packet Counter..,MMC Receive Oversize Good Packet Counter.." newline bitfld.long 0x0 9. "RXUSIZEGPIS,MMC Receive Undersize Good Packet Counter Interrupt Status This bit is set when the rxundersize_g counter reaches half of the maximum value or the maximum value. Access restriction applies. Clears on read. Self-set to 1 on internal event." "MMC Receive Undersize Good Packet Counter..,MMC Receive Undersize Good Packet Counter.." newline bitfld.long 0x0 8. "RXJABERPIS,MMC Receive Jabber Error Packet Counter Interrupt Status This bit is set when the rxjabbererror counter reaches half of the maximum value or the maximum value. Access restriction applies. Clears on read. Self-set to 1 on internal event. 0x1:.." "MMC Receive Jabber Error Packet Counter..,MMC Receive Jabber Error Packet Counter.." newline bitfld.long 0x0 7. "RXRUNTPIS,MMC Receive Runt Packet Counter Interrupt Status This bit is set when the rxrunterror counter reaches half of the maximum value or the maximum value. Access restriction applies. Clears on read. Self-set to 1 on internal event. 0x1: MMC Receive.." "MMC Receive Runt Packet Counter Interrupt Status..,MMC Receive Runt Packet Counter Interrupt Status.." newline bitfld.long 0x0 6. "RXALGNERPIS,MMC Receive Alignment Error Packet Counter Interrupt Status This bit is set when the rxalignmenterror counter reaches half of the maximum value or the maximum value. Access restriction applies. Clears on read. Self-set to 1 on internal event." "MMC Receive Alignment Error Packet Counter..,MMC Receive Alignment Error Packet Counter.." newline bitfld.long 0x0 5. "RXCRCERPIS,MMC Receive CRC Error Packet Counter Interrupt Status This bit is set when the rxcrcerror counter reaches half of the maximum value or the maximum value. Access restriction applies. Clears on read. Self-set to 1 on internal event. 0x1: MMC.." "MMC Receive CRC Error Packet Counter Interrupt..,MMC Receive CRC Error Packet Counter Interrupt.." newline bitfld.long 0x0 4. "RXMCGPIS,MMC Receive Multicast Good Packet Counter Interrupt Status This bit is set when the rxmulticastpackets_g counter reaches half of the maximum value or the maximum value. Access restriction applies. Clears on read. Self-set to 1 on internal event." "MMC Receive Multicast Good Packet Counter..,MMC Receive Multicast Good Packet Counter.." newline bitfld.long 0x0 3. "RXBCGPIS,MMC Receive Broadcast Good Packet Counter Interrupt Status This bit is set when the rxbroadcastpackets_g counter reaches half of the maximum value or the maximum value. Access restriction applies. Clears on read. Self-set to 1 on internal event." "MMC Receive Broadcast Good Packet Counter..,MMC Receive Broadcast Good Packet Counter.." newline bitfld.long 0x0 2. "RXGOCTIS,MMC Receive Good Octet Counter Interrupt Status This bit is set when the rxoctetcount_g counter reaches half of the maximum value or the maximum value. Access restriction applies. Clears on read. Self-set to 1 on internal event. 0x1: MMC Receive.." "MMC Receive Good Octet Counter Interrupt Status..,MMC Receive Good Octet Counter Interrupt Status.." newline bitfld.long 0x0 1. "RXGBOCTIS,MMC Receive Good Bad Octet Counter Interrupt Status This bit is set when the rxoctetcount_gb counter reaches half of the maximum value or the maximum value. Access restriction applies. Clears on read. Self-set to 1 on internal event. 0x1: MMC.." "MMC Receive Good Bad Octet Counter Interrupt..,MMC Receive Good Bad Octet Counter Interrupt.." newline bitfld.long 0x0 0. "RXGBPKTIS,MMC Receive Good Bad Packet Counter Interrupt Status This bit is set when the rxpacketcount_gb counter reaches half of the maximum value or the maximum value. Access restriction applies. Clears on read. Self-set to 1 on internal event. 0x1: MMC.." "MMC Receive Good Bad Packet Counter Interrupt..,MMC Receive Good Bad Packet Counter Interrupt.." line.long 0x4 "MMC_TX_INTERRUPT,This register maintains the interrupts generated from all Transmit statistics counters. The MMC Transmit Interrupt register maintains the interrupts generated when transmit statistic counters reach half their maximum values (0x8000_0000.." hexmask.long.byte 0x4 28.--31. 1. "RESERVED_31_28,Reserved." newline bitfld.long 0x4 27. "TXLPITRCIS,MMC Transmit LPI transition counter interrupt status This bit is set when the Tx_LPI_Tran_Cntr counter reaches half of the maximum value or the maximum value. Access restriction applies. Clears on read. Self-set to 1 on internal event. 0x1:.." "MMC Transmit LPI transition Counter Interrupt..,MMC Transmit LPI transition Counter Interrupt.." newline bitfld.long 0x4 26. "TXLPIUSCIS,MMC Transmit LPI microsecond counter interrupt status This bit is set when the Tx_LPI_USEC_Cntr counter reaches half of the maximum value or the maximum value. Access restriction applies. Clears on read. Self-set to 1 on internal event. 0x1:.." "MMC Transmit LPI microsecond Counter Interrupt..,MMC Transmit LPI microsecond Counter Interrupt.." newline bitfld.long 0x4 25. "TXOSIZEGPIS,MMC Transmit Oversize Good Packet Counter Interrupt Status This bit is set when the txoversize_g counter reaches half of the maximum value or the maximum value. Access restriction applies. Clears on read. Self-set to 1 on internal event. 0x1:.." "MMC Transmit Oversize Good Packet Counter..,MMC Transmit Oversize Good Packet Counter.." newline bitfld.long 0x4 24. "TXVLANGPIS,MMC Transmit VLAN Good Packet Counter Interrupt Status This bit is set when the txvlanpackets_g counter reaches half of the maximum value or the maximum value. Access restriction applies. Clears on read. Self-set to 1 on internal event. 0x1:.." "MMC Transmit VLAN Good Packet Counter Interrupt..,MMC Transmit VLAN Good Packet Counter Interrupt.." newline bitfld.long 0x4 23. "TXPAUSPIS,MMC Transmit Pause Packet Counter Interrupt Status This bit is set when the txpausepacketserror counter reaches half of the maximum value or the maximum value. Access restriction applies. Clears on read. Self-set to 1 on internal event. 0x1:.." "MMC Transmit Pause Packet Counter Interrupt..,MMC Transmit Pause Packet Counter Interrupt.." newline bitfld.long 0x4 22. "TXEXDEFPIS,MMC Transmit Excessive Deferral Packet Counter Interrupt Status This bit is set when the txexcessdef counter reaches half of the maximum value or the maximum value. Access restriction applies. Clears on read. Self-set to 1 on internal event." "MMC Transmit Excessive Deferral Packet Counter..,MMC Transmit Excessive Deferral Packet Counter.." newline bitfld.long 0x4 21. "TXGPKTIS,MMC Transmit Good Packet Counter Interrupt Status This bit is set when the txpacketcount_g counter reaches half of the maximum value or the maximum value. Access restriction applies. Clears on read. Self-set to 1 on internal event. 0x1: MMC.." "MMC Transmit Good Packet Counter Interrupt..,MMC Transmit Good Packet Counter Interrupt.." newline bitfld.long 0x4 20. "TXGOCTIS,MMC Transmit Good Octet Counter Interrupt Status This bit is set when the txoctetcount_g counter reaches half of the maximum value or the maximum value. Access restriction applies. Clears on read. Self-set to 1 on internal event. 0x1: MMC.." "MMC Transmit Good Octet Counter Interrupt Status..,MMC Transmit Good Octet Counter Interrupt Status.." newline bitfld.long 0x4 19. "TXCARERPIS,MMC Transmit Carrier Error Packet Counter Interrupt Status This bit is set when the txcarriererror counter reaches half of the maximum value or the maximum value. Access restriction applies. Clears on read. Self-set to 1 on internal event." "MMC Transmit Carrier Error Packet Counter..,MMC Transmit Carrier Error Packet Counter.." newline bitfld.long 0x4 18. "TXEXCOLPIS,MMC Transmit Excessive Collision Packet Counter Interrupt Status This bit is set when the txexesscol counter reaches half of the maximum value or the maximum value. Access restriction applies. Clears on read. Self-set to 1 on internal event." "MMC Transmit Excessive Collision Packet Counter..,MMC Transmit Excessive Collision Packet Counter.." newline bitfld.long 0x4 17. "TXLATCOLPIS,MMC Transmit Late Collision Packet Counter Interrupt Status This bit is set when the txlatecol counter reaches half of the maximum value or the maximum value. Access restriction applies. Clears on read. Self-set to 1 on internal event. 0x1:.." "MMC Transmit Late Collision Packet Counter..,MMC Transmit Late Collision Packet Counter.." newline bitfld.long 0x4 16. "TXDEFPIS,MMC Transmit Deferred Packet Counter Interrupt Status This bit is set when the txdeferred counter reaches half of the maximum value or the maximum value. Access restriction applies. Clears on read. Self-set to 1 on internal event. 0x1: MMC.." "MMC Transmit Deferred Packet Counter Interrupt..,MMC Transmit Deferred Packet Counter Interrupt.." newline bitfld.long 0x4 15. "TXMCOLGPIS,MMC Transmit Multiple Collision Good Packet Counter Interrupt Status This bit is set when the txmulticol_g counter reaches half of the maximum value or the maximum value. Access restriction applies. Clears on read. Self-set to 1 on internal.." "MMC Transmit Multiple Collision Good Packet..,MMC Transmit Multiple Collision Good Packet.." newline bitfld.long 0x4 14. "TXSCOLGPIS,MMC Transmit Single Collision Good Packet Counter Interrupt Status This bit is set when the txsinglecol_g counter reaches half of the maximum value or the maximum value. Access restriction applies. Clears on read. Self-set to 1 on internal.." "MMC Transmit Single Collision Good Packet..,MMC Transmit Single Collision Good Packet.." newline bitfld.long 0x4 13. "TXUFLOWERPIS,MMC Transmit Underflow Error Packet Counter Interrupt Status This bit is set when the txunderflowerror counter reaches half of the maximum value or the maximum value. Access restriction applies. Clears on read. Self-set to 1 on internal.." "MMC Transmit Underflow Error Packet Counter..,MMC Transmit Underflow Error Packet Counter.." newline bitfld.long 0x4 12. "TXBCGBPIS,MMC Transmit Broadcast Good Bad Packet Counter Interrupt Status This bit is set when the txbroadcastpackets_gb counter reaches half of the maximum value or the maximum value. Access restriction applies. Clears on read. Self-set to 1 on internal.." "MMC Transmit Broadcast Good Bad Packet Counter..,MMC Transmit Broadcast Good Bad Packet Counter.." newline bitfld.long 0x4 11. "TXMCGBPIS,MMC Transmit Multicast Good Bad Packet Counter Interrupt Status The bit is set when the txmulticastpackets_gb counter reaches half of the maximum value or the maximum value. Access restriction applies. Clears on read. Self-set to 1 on internal.." "MMC Transmit Multicast Good Bad Packet Counter..,MMC Transmit Multicast Good Bad Packet Counter.." newline bitfld.long 0x4 10. "TXUCGBPIS,MMC Transmit Unicast Good Bad Packet Counter Interrupt Status This bit is set when the txunicastpackets_gb counter reaches half of the maximum value or the maximum value. Access restriction applies. Clears on read. Self-set to 1 on internal.." "MMC Transmit Unicast Good Bad Packet Counter..,MMC Transmit Unicast Good Bad Packet Counter.." newline bitfld.long 0x4 9. "TX1024TMAXOCTGBPIS,MMC Transmit 1024 to Maximum Octet Good Bad Packet Counter Interrupt Status This bit is set when the tx1024tomaxoctets_gb counter reaches half of the maximum value or the maximum value. Access restriction applies. Clears on read." "MMC Transmit 1024 to Maximum Octet Good Bad..,MMC Transmit 1024 to Maximum Octet Good Bad.." newline bitfld.long 0x4 8. "TX512T1023OCTGBPIS,MMC Transmit 512 to 1023 Octet Good Bad Packet Counter Interrupt Status This bit is set when the tx512to1023octets_gb counter reaches half of the maximum value or the maximum value. Access restriction applies. Clears on read. Self-set.." "MMC Transmit 512 to 1023 Octet Good Bad Packet..,MMC Transmit 512 to 1023 Octet Good Bad Packet.." newline bitfld.long 0x4 7. "TX256T511OCTGBPIS,MMC Transmit 256 to 511 Octet Good Bad Packet Counter Interrupt Status This bit is set when the tx256to511octets_gb counter reaches half of the maximum value or the maximum value. Access restriction applies. Clears on read. Self-set to.." "MMC Transmit 256 to 511 Octet Good Bad Packet..,MMC Transmit 256 to 511 Octet Good Bad Packet.." newline bitfld.long 0x4 6. "TX128T255OCTGBPIS,MMC Transmit 128 to 255 Octet Good Bad Packet Counter Interrupt Status This bit is set when the tx128to255octets_gb counter reaches half of the maximum value or the maximum value. Access restriction applies. Clears on read. Self-set to.." "MMC Transmit 128 to 255 Octet Good Bad Packet..,MMC Transmit 128 to 255 Octet Good Bad Packet.." newline bitfld.long 0x4 5. "TX65T127OCTGBPIS,MMC Transmit 65 to 127 Octet Good Bad Packet Counter Interrupt Status This bit is set when the tx65to127octets_gb counter reaches half the maximum value and also when it reaches the maximum value. Access restriction applies. Clears on.." "MMC Transmit 65 to 127 Octet Good Bad Packet..,MMC Transmit 65 to 127 Octet Good Bad Packet.." newline bitfld.long 0x4 4. "TX64OCTGBPIS,MMC Transmit 64 Octet Good Bad Packet Counter Interrupt Status This bit is set when the tx64octets_gb counter reaches half of the maximum value or the maximum value. Access restriction applies. Clears on read. Self-set to 1 on internal.." "MMC Transmit 64 Octet Good Bad Packet Counter..,MMC Transmit 64 Octet Good Bad Packet Counter.." newline bitfld.long 0x4 3. "TXMCGPIS,MMC Transmit Multicast Good Packet Counter Interrupt Status This bit is set when the txmulticastpackets_g counter reaches half of the maximum value or the maximum value. Access restriction applies. Clears on read. Self-set to 1 on internal.." "MMC Transmit Multicast Good Packet Counter..,MMC Transmit Multicast Good Packet Counter.." newline bitfld.long 0x4 2. "TXBCGPIS,MMC Transmit Broadcast Good Packet Counter Interrupt Status This bit is set when the txbroadcastpackets_g counter reaches half of the maximum value or the maximum value. Access restriction applies. Clears on read. Self-set to 1 on internal.." "MMC Transmit Broadcast Good Packet Counter..,MMC Transmit Broadcast Good Packet Counter.." newline bitfld.long 0x4 1. "TXGBPKTIS,MMC Transmit Good Bad Packet Counter Interrupt Status This bit is set when the txpacketcount_gb counter reaches half of the maximum value or the maximum value. Access restriction applies. Clears on read. Self-set to 1 on internal event. 0x1:.." "MMC Transmit Good Bad Packet Counter Interrupt..,MMC Transmit Good Bad Packet Counter Interrupt.." newline bitfld.long 0x4 0. "TXGBOCTIS,MMC Transmit Good Bad Octet Counter Interrupt Status This bit is set when the txoctetcount_gb counter reaches half of the maximum value or the maximum value. Access restriction applies. Clears on read. Self-set to 1 on internal event. 0x1: MMC.." "MMC Transmit Good Bad Octet Counter Interrupt..,MMC Transmit Good Bad Octet Counter Interrupt.." group.long 0x70C++0x7 line.long 0x0 "MMC_RX_INTERRUPT_MASK,This register maintains the masks for interrupts generated from all Receive statistics counters. The MMC Receive Interrupt Mask register maintains the masks for the interrupts generated when receive statistic counters reach half of.." hexmask.long.byte 0x0 28.--31. 1. "RESERVED_31_28,Reserved." newline bitfld.long 0x0 27. "RXLPITRCIM,MMC Receive LPI transition counter interrupt Mask Setting this bit masks the interrupt when the Rx_LPI_Tran_Cntr counter reaches half of the maximum value or the maximum value. 0x0: MMC Receive LPI transition counter interrupt Mask is disabled.." "MMC Receive LPI transition counter interrupt..,MMC Receive LPI transition counter interrupt.." newline bitfld.long 0x0 26. "RXLPIUSCIM,MMC Receive LPI microsecond counter interrupt Mask Setting this bit masks the interrupt when the Rx_LPI_USEC_Cntr counter reaches half of the maximum value or the maximum value. 0x0: MMC Receive LPI microsecond counter interrupt Mask is.." "MMC Receive LPI microsecond counter interrupt..,MMC Receive LPI microsecond counter interrupt.." newline bitfld.long 0x0 25. "RXCTRLPIM,MMC Receive Control Packet Counter Interrupt Mask Setting this bit masks the interrupt when the rxctrlpackets_g counter reaches half of the maximum value or the maximum value. 0x0: MMC Receive Control Packet Counter Interrupt Mask is disabled.." "MMC Receive Control Packet Counter Interrupt..,MMC Receive Control Packet Counter Interrupt.." newline bitfld.long 0x0 24. "RXRCVERRPIM,MMC Receive Error Packet Counter Interrupt Mask Setting this bit masks the interrupt when the rxrcverror counter reaches half of the maximum value or the maximum value. 0x0: MMC Receive Error Packet Counter Interrupt Mask is disabled 0x1: MMC.." "MMC Receive Error Packet Counter Interrupt Mask..,MMC Receive Error Packet Counter Interrupt Mask.." newline bitfld.long 0x0 23. "RXWDOGPIM,MMC Receive Watchdog Error Packet Counter Interrupt Mask Setting this bit masks the interrupt when the rxwatchdog counter reaches half of the maximum value or the maximum value. 0x0: MMC Receive Watchdog Error Packet Counter Interrupt Mask is.." "MMC Receive Watchdog Error Packet Counter..,MMC Receive Watchdog Error Packet Counter.." newline bitfld.long 0x0 22. "RXVLANGBPIM,MMC Receive VLAN Good Bad Packet Counter Interrupt Mask Setting this bit masks the interrupt when the rxvlanpackets_gb counter reaches half of the maximum value or the maximum value. 0x0: MMC Receive VLAN Good Bad Packet Counter Interrupt.." "MMC Receive VLAN Good Bad Packet Counter..,MMC Receive VLAN Good Bad Packet Counter.." newline bitfld.long 0x0 21. "RXFOVPIM,MMC Receive FIFO Overflow Packet Counter Interrupt Mask Setting this bit masks the interrupt when the rxfifooverflow counter reaches half of the maximum value or the maximum value. 0x0: MMC Receive FIFO Overflow Packet Counter Interrupt Mask is.." "MMC Receive FIFO Overflow Packet Counter..,MMC Receive FIFO Overflow Packet Counter.." newline bitfld.long 0x0 20. "RXPAUSPIM,MMC Receive Pause Packet Counter Interrupt Mask Setting this bit masks the interrupt when the rxpausepackets counter reaches half of the maximum value or the maximum value. 0x0: MMC Receive Pause Packet Counter Interrupt Mask is disabled 0x1:.." "MMC Receive Pause Packet Counter Interrupt Mask..,MMC Receive Pause Packet Counter Interrupt Mask.." newline bitfld.long 0x0 19. "RXORANGEPIM,MMC Receive Out Of Range Error Packet Counter Interrupt Mask Setting this bit masks the interrupt when the rxoutofrangetype counter reaches half of the maximum value or the maximum value. 0x0: MMC Receive Out Of Range Error Packet Counter.." "MMC Receive Out Of Range Error Packet Counter..,MMC Receive Out Of Range Error Packet Counter.." newline bitfld.long 0x0 18. "RXLENERPIM,MMC Receive Length Error Packet Counter Interrupt Mask Setting this bit masks the interrupt when the rxlengtherror counter reaches half of the maximum value or the maximum value. 0x0: MMC Receive Length Error Packet Counter Interrupt Mask is.." "MMC Receive Length Error Packet Counter..,MMC Receive Length Error Packet Counter.." newline bitfld.long 0x0 17. "RXUCGPIM,MMC Receive Unicast Good Packet Counter Interrupt Mask Setting this bit masks the interrupt when the rxunicastpackets_g counter reaches half of the maximum value or the maximum value. 0x0: MMC Receive Unicast Good Packet Counter Interrupt Mask.." "MMC Receive Unicast Good Packet Counter..,MMC Receive Unicast Good Packet Counter.." newline bitfld.long 0x0 16. "RX1024TMAXOCTGBPIM,MMC Receive 1024 to Maximum Octet Good Bad Packet Counter Interrupt Mask. Setting this bit masks the interrupt when the rx1024tomaxoctets_gb counter reaches half of the maximum value or the maximum value. 0x0: MMC Receive 1024 to.." "MMC Receive 1024 to Maximum Octet Good Bad..,MMC Receive 1024 to Maximum Octet Good Bad.." newline bitfld.long 0x0 15. "RX512T1023OCTGBPIM,MMC Receive 512 to 1023 Octet Good Bad Packet Counter Interrupt Mask Setting this bit masks the interrupt when the rx512to1023octets_gb counter reaches half of the maximum value or the maximum value. 0x0: MMC Receive 512 to 1023 Octet.." "MMC Receive 512 to 1023 Octet Good Bad Packet..,MMC Receive 512 to 1023 Octet Good Bad Packet.." newline bitfld.long 0x0 14. "RX256T511OCTGBPIM,MMC Receive 256 to 511 Octet Good Bad Packet Counter Interrupt Mask Setting this bit masks the interrupt when the rx256to511octets_gb counter reaches half of the maximum value or the maximum value. 0x0: MMC Receive 256 to 511 Octet Good.." "MMC Receive 256 to 511 Octet Good Bad Packet..,MMC Receive 256 to 511 Octet Good Bad Packet.." newline bitfld.long 0x0 13. "RX128T255OCTGBPIM,MMC Receive 128 to 255 Octet Good Bad Packet Counter Interrupt Mask Setting this bit masks the interrupt when the rx128to255octets_gb counter reaches half of the maximum value or the maximum value. 0x0: MMC Receive 128 to 255 Octet Good.." "MMC Receive 128 to 255 Octet Good Bad Packet..,MMC Receive 128 to 255 Octet Good Bad Packet.." newline bitfld.long 0x0 12. "RX65T127OCTGBPIM,MMC Receive 65 to 127 Octet Good Bad Packet Counter Interrupt Mask Setting this bit masks the interrupt when the rx65to127octets_gb counter reaches half of the maximum value or the maximum value. 0x0: MMC Receive 65 to 127 Octet Good Bad.." "MMC Receive 65 to 127 Octet Good Bad Packet..,MMC Receive 65 to 127 Octet Good Bad Packet.." newline bitfld.long 0x0 11. "RX64OCTGBPIM,MMC Receive 64 Octet Good Bad Packet Counter Interrupt Mask Setting this bit masks the interrupt when the rx64octets_gb counter reaches half of the maximum value or the maximum value. 0x0: MMC Receive 64 Octet Good Bad Packet Counter.." "MMC Receive 64 Octet Good Bad Packet Counter..,MMC Receive 64 Octet Good Bad Packet Counter.." newline bitfld.long 0x0 10. "RXOSIZEGPIM,MMC Receive Oversize Good Packet Counter Interrupt Mask Setting this bit masks the interrupt when the rxoversize_g counter reaches half of the maximum value or the maximum value. 0x0: MMC Receive Oversize Good Packet Counter Interrupt Mask is.." "MMC Receive Oversize Good Packet Counter..,MMC Receive Oversize Good Packet Counter.." newline bitfld.long 0x0 9. "RXUSIZEGPIM,MMC Receive Undersize Good Packet Counter Interrupt Mask Setting this bit masks the interrupt when the rxundersize_g counter reaches half of the maximum value or the maximum value. 0x0: MMC Receive Undersize Good Packet Counter Interrupt Mask.." "MMC Receive Undersize Good Packet Counter..,MMC Receive Undersize Good Packet Counter.." newline bitfld.long 0x0 8. "RXJABERPIM,MMC Receive Jabber Error Packet Counter Interrupt Mask Setting this bit masks the interrupt when the rxjabbererror counter reaches half of the maximum value or the maximum value. 0x0: MMC Receive Jabber Error Packet Counter Interrupt Mask is.." "MMC Receive Jabber Error Packet Counter..,MMC Receive Jabber Error Packet Counter.." newline bitfld.long 0x0 7. "RXRUNTPIM,MMC Receive Runt Packet Counter Interrupt Mask Setting this bit masks the interrupt when the rxrunterror counter reaches half of the maximum value or the maximum value. 0x0: MMC Receive Runt Packet Counter Interrupt Mask is disabled 0x1: MMC.." "MMC Receive Runt Packet Counter Interrupt Mask..,MMC Receive Runt Packet Counter Interrupt Mask.." newline bitfld.long 0x0 6. "RXALGNERPIM,MMC Receive Alignment Error Packet Counter Interrupt Mask Setting this bit masks the interrupt when the rxalignmenterror counter reaches half of the maximum value or the maximum value. 0x0: MMC Receive Alignment Error Packet Counter Interrupt.." "MMC Receive Alignment Error Packet Counter..,MMC Receive Alignment Error Packet Counter.." newline bitfld.long 0x0 5. "RXCRCERPIM,MMC Receive CRC Error Packet Counter Interrupt Mask Setting this bit masks the interrupt when the rxcrcerror counter reaches half of the maximum value or the maximum value. 0x0: MMC Receive CRC Error Packet Counter Interrupt Mask is disabled.." "MMC Receive CRC Error Packet Counter Interrupt..,MMC Receive CRC Error Packet Counter Interrupt.." newline bitfld.long 0x0 4. "RXMCGPIM,MMC Receive Multicast Good Packet Counter Interrupt Mask Setting this bit masks the interrupt when the rxmulticastpackets_g counter reaches half of the maximum value or the maximum value. 0x0: MMC Receive Multicast Good Packet Counter Interrupt.." "MMC Receive Multicast Good Packet Counter..,MMC Receive Multicast Good Packet Counter.." newline bitfld.long 0x0 3. "RXBCGPIM,MMC Receive Broadcast Good Packet Counter Interrupt Mask Setting this bit masks the interrupt when the rxbroadcastpackets_g counter reaches half of the maximum value or the maximum value. 0x0: MMC Receive Broadcast Good Packet Counter Interrupt.." "MMC Receive Broadcast Good Packet Counter..,MMC Receive Broadcast Good Packet Counter.." newline bitfld.long 0x0 2. "RXGOCTIM,MMC Receive Good Octet Counter Interrupt Mask Setting this bit masks the interrupt when the rxoctetcount_g counter reaches half of the maximum value or the maximum value. 0x0: MMC Receive Good Octet Counter Interrupt Mask is disabled 0x1: MMC.." "MMC Receive Good Octet Counter Interrupt Mask is..,MMC Receive Good Octet Counter Interrupt Mask is.." newline bitfld.long 0x0 1. "RXGBOCTIM,MMC Receive Good Bad Octet Counter Interrupt Mask Setting this bit masks the interrupt when the rxoctetcount_gb counter reaches half of the maximum value or the maximum value. 0x0: MMC Receive Good Bad Octet Counter Interrupt Mask is disabled.." "MMC Receive Good Bad Octet Counter Interrupt..,MMC Receive Good Bad Octet Counter Interrupt.." newline bitfld.long 0x0 0. "RXGBPKTIM,MMC Receive Good Bad Packet Counter Interrupt Mask Setting this bit masks the interrupt when the rxpacketcount_gb counter reaches half of the maximum value or the maximum value. 0x0: MMC Receive Good Bad Packet Counter Interrupt Mask is.." "MMC Receive Good Bad Packet Counter Interrupt..,MMC Receive Good Bad Packet Counter Interrupt.." line.long 0x4 "MMC_TX_INTERRUPT_MASK,This register maintains the masks for interrupts generated from all Transmit statistics counters. The MMC Transmit Interrupt Mask register maintains the masks for the interrupts generated when the transmit statistic counters reach.." hexmask.long.byte 0x4 28.--31. 1. "RESERVED_31_28,Reserved." newline bitfld.long 0x4 27. "TXLPITRCIM,MMC Transmit LPI transition counter interrupt Mask Setting this bit masks the interrupt when the Tx_LPI_Tran_Cntr counter reaches half of the maximum value or the maximum value. 0x0: MMC Transmit LPI transition counter interrupt Mask is.." "MMC Transmit LPI transition counter interrupt..,MMC Transmit LPI transition counter interrupt.." newline bitfld.long 0x4 26. "TXLPIUSCIM,MMC Transmit LPI microsecond counter interrupt Mask Setting this bit masks the interrupt when the Tx_LPI_USEC_Cntr counter reaches half of the maximum value or the maximum value. 0x0: MMC Transmit LPI microsecond counter interrupt Mask is.." "MMC Transmit LPI microsecond counter interrupt..,MMC Transmit LPI microsecond counter interrupt.." newline bitfld.long 0x4 25. "TXOSIZEGPIM,MMC Transmit Oversize Good Packet Counter Interrupt Mask Setting this bit masks the interrupt when the txoversize_g counter reaches half of the maximum value or the maximum value. 0x0: MMC Transmit Oversize Good Packet Counter Interrupt Mask.." "MMC Transmit Oversize Good Packet Counter..,MMC Transmit Oversize Good Packet Counter.." newline bitfld.long 0x4 24. "TXVLANGPIM,MMC Transmit VLAN Good Packet Counter Interrupt Mask Setting this bit masks the interrupt when the txvlanpackets_g counter reaches half of the maximum value or the maximum value. 0x0: MMC Transmit VLAN Good Packet Counter Interrupt Mask is.." "MMC Transmit VLAN Good Packet Counter Interrupt..,MMC Transmit VLAN Good Packet Counter Interrupt.." newline bitfld.long 0x4 23. "TXPAUSPIM,MMC Transmit Pause Packet Counter Interrupt Mask Setting this bit masks the interrupt when the txpausepackets counter reaches half of the maximum value or the maximum value. 0x0: MMC Transmit Pause Packet Counter Interrupt Mask is disabled 0x1:.." "MMC Transmit Pause Packet Counter Interrupt Mask..,MMC Transmit Pause Packet Counter Interrupt Mask.." newline bitfld.long 0x4 22. "TXEXDEFPIM,MMC Transmit Excessive Deferral Packet Counter Interrupt Mask Setting this bit masks the interrupt when the txexcessdef counter reaches half of the maximum value or the maximum value. 0x0: MMC Transmit Excessive Deferral Packet Counter.." "MMC Transmit Excessive Deferral Packet Counter..,MMC Transmit Excessive Deferral Packet Counter.." newline bitfld.long 0x4 21. "TXGPKTIM,MMC Transmit Good Packet Counter Interrupt Mask Setting this bit masks the interrupt when the txpacketcount_g counter reaches half of the maximum value or the maximum value. 0x0: MMC Transmit Good Packet Counter Interrupt Mask is disabled 0x1:.." "MMC Transmit Good Packet Counter Interrupt Mask..,MMC Transmit Good Packet Counter Interrupt Mask.." newline bitfld.long 0x4 20. "TXGOCTIM,MMC Transmit Good Octet Counter Interrupt Mask Setting this bit masks the interrupt when the txoctetcount_g counter reaches half of the maximum value or the maximum value. 0x0: MMC Transmit Good Octet Counter Interrupt Mask is disabled 0x1: MMC.." "MMC Transmit Good Octet Counter Interrupt Mask..,MMC Transmit Good Octet Counter Interrupt Mask.." newline bitfld.long 0x4 19. "TXCARERPIM,MMC Transmit Carrier Error Packet Counter Interrupt Mask Setting this bit masks the interrupt when the txcarriererror counter reaches half of the maximum value or the maximum value. 0x0: MMC Transmit Carrier Error Packet Counter Interrupt Mask.." "MMC Transmit Carrier Error Packet Counter..,MMC Transmit Carrier Error Packet Counter.." newline bitfld.long 0x4 18. "TXEXCOLPIM,MMC Transmit Excessive Collision Packet Counter Interrupt Mask Setting this bit masks the interrupt when the txexcesscol counter reaches half of the maximum value or the maximum value. 0x0: MMC Transmit Excessive Collision Packet Counter.." "MMC Transmit Excessive Collision Packet Counter..,MMC Transmit Excessive Collision Packet Counter.." newline bitfld.long 0x4 17. "TXLATCOLPIM,MMC Transmit Late Collision Packet Counter Interrupt Mask Setting this bit masks the interrupt when the txlatecol counter reaches half of the maximum value or the maximum value. 0x0: MMC Transmit Late Collision Packet Counter Interrupt Mask.." "MMC Transmit Late Collision Packet Counter..,MMC Transmit Late Collision Packet Counter.." newline bitfld.long 0x4 16. "TXDEFPIM,MMC Transmit Deferred Packet Counter Interrupt Mask Setting this bit masks the interrupt when the txdeferred counter reaches half of the maximum value or the maximum value. 0x0: MMC Transmit Deferred Packet Counter Interrupt Mask is disabled.." "MMC Transmit Deferred Packet Counter Interrupt..,MMC Transmit Deferred Packet Counter Interrupt.." newline bitfld.long 0x4 15. "TXMCOLGPIM,MMC Transmit Multiple Collision Good Packet Counter Interrupt Mask Setting this bit masks the interrupt when the txmulticol_g counter reaches half of the maximum value or the maximum value. 0x0: MMC Transmit Multiple Collision Good Packet.." "MMC Transmit Multiple Collision Good Packet..,MMC Transmit Multiple Collision Good Packet.." newline bitfld.long 0x4 14. "TXSCOLGPIM,MMC Transmit Single Collision Good Packet Counter Interrupt Mask Setting this bit masks the interrupt when the txsinglecol_g counter reaches half of the maximum value or the maximum value. 0x0: MMC Transmit Single Collision Good Packet Counter.." "MMC Transmit Single Collision Good Packet..,MMC Transmit Single Collision Good Packet.." newline bitfld.long 0x4 13. "TXUFLOWERPIM,MMC Transmit Underflow Error Packet Counter Interrupt Mask Setting this bit masks the interrupt when the txunderflowerror counter reaches half of the maximum value or the maximum value. 0x0: MMC Transmit Underflow Error Packet Counter.." "MMC Transmit Underflow Error Packet Counter..,MMC Transmit Underflow Error Packet Counter.." newline bitfld.long 0x4 12. "TXBCGBPIM,MMC Transmit Broadcast Good Bad Packet Counter Interrupt Mask Setting this bit masks the interrupt when the txbroadcastpackets_gb counter reaches half of the maximum value or the maximum value. 0x0: MMC Transmit Broadcast Good Bad Packet.." "MMC Transmit Broadcast Good Bad Packet Counter..,MMC Transmit Broadcast Good Bad Packet Counter.." newline bitfld.long 0x4 11. "TXMCGBPIM,MMC Transmit Multicast Good Bad Packet Counter Interrupt Mask Setting this bit masks the interrupt when the txmulticastpackets_gb counter reaches half of the maximum value or the maximum value. 0x0: MMC Transmit Multicast Good Bad Packet.." "MMC Transmit Multicast Good Bad Packet Counter..,MMC Transmit Multicast Good Bad Packet Counter.." newline bitfld.long 0x4 10. "TXUCGBPIM,MMC Transmit Unicast Good Bad Packet Counter Interrupt Mask Setting this bit masks the interrupt when the txunicastpackets_gb counter reaches half of the maximum value or the maximum value. 0x0: MMC Transmit Unicast Good Bad Packet Counter.." "MMC Transmit Unicast Good Bad Packet Counter..,MMC Transmit Unicast Good Bad Packet Counter.." newline bitfld.long 0x4 9. "TX1024TMAXOCTGBPIM,MMC Transmit 1024 to Maximum Octet Good Bad Packet Counter Interrupt Mask Setting this bit masks the interrupt when the tx1024tomaxoctets_gb counter reaches half of the maximum value or the maximum value. 0x0: MMC Transmit 1024 to.." "MMC Transmit 1024 to Maximum Octet Good Bad..,MMC Transmit 1024 to Maximum Octet Good Bad.." newline bitfld.long 0x4 8. "TX512T1023OCTGBPIM,MMC Transmit 512 to 1023 Octet Good Bad Packet Counter Interrupt Mask Setting this bit masks the interrupt when the tx512to1023octets_gb counter reaches half of the maximum value or the maximum value. 0x0: MMC Transmit 512 to 1023.." "MMC Transmit 512 to 1023 Octet Good Bad Packet..,MMC Transmit 512 to 1023 Octet Good Bad Packet.." newline bitfld.long 0x4 7. "TX256T511OCTGBPIM,MMC Transmit 256 to 511 Octet Good Bad Packet Counter Interrupt Mask Setting this bit masks the interrupt when the tx256to511octets_gb counter reaches half of the maximum value or the maximum value. 0x0: MMC Transmit 256 to 511 Octet.." "MMC Transmit 256 to 511 Octet Good Bad Packet..,MMC Transmit 256 to 511 Octet Good Bad Packet.." newline bitfld.long 0x4 6. "TX128T255OCTGBPIM,MMC Transmit 128 to 255 Octet Good Bad Packet Counter Interrupt Mask Setting this bit masks the interrupt when the tx128to255octets_gb counter reaches half of the maximum value or the maximum value. 0x0: MMC Transmit 128 to 255 Octet.." "MMC Transmit 128 to 255 Octet Good Bad Packet..,MMC Transmit 128 to 255 Octet Good Bad Packet.." newline bitfld.long 0x4 5. "TX65T127OCTGBPIM,MMC Transmit 65 to 127 Octet Good Bad Packet Counter Interrupt Mask Setting this bit masks the interrupt when the tx65to127octets_gb counter reaches half of the maximum value or the maximum value. 0x0: MMC Transmit 65 to 127 Octet Good.." "MMC Transmit 65 to 127 Octet Good Bad Packet..,MMC Transmit 65 to 127 Octet Good Bad Packet.." newline bitfld.long 0x4 4. "TX64OCTGBPIM,MMC Transmit 64 Octet Good Bad Packet Counter Interrupt Mask Setting this bit masks the interrupt when the tx64octets_gb counter reaches half of the maximum value or the maximum value. 0x0: MMC Transmit 64 Octet Good Bad Packet Counter.." "MMC Transmit 64 Octet Good Bad Packet Counter..,MMC Transmit 64 Octet Good Bad Packet Counter.." newline bitfld.long 0x4 3. "TXMCGPIM,MMC Transmit Multicast Good Packet Counter Interrupt Mask Setting this bit masks the interrupt when the txmulticastpackets_g counter reaches half of the maximum value or the maximum value. 0x0: MMC Transmit Multicast Good Packet Counter.." "MMC Transmit Multicast Good Packet Counter..,MMC Transmit Multicast Good Packet Counter.." newline bitfld.long 0x4 2. "TXBCGPIM,MMC Transmit Broadcast Good Packet Counter Interrupt Mask Setting this bit masks the interrupt when the txbroadcastpackets_g counter reaches half of the maximum value or the maximum value. 0x0: MMC Transmit Broadcast Good Packet Counter.." "MMC Transmit Broadcast Good Packet Counter..,MMC Transmit Broadcast Good Packet Counter.." newline bitfld.long 0x4 1. "TXGBPKTIM,MMC Transmit Good Bad Packet Counter Interrupt Mask Setting this bit masks the interrupt when the txpacketcount_gb counter reaches half of the maximum value or the maximum value. 0x0: MMC Transmit Good Bad Packet Counter Interrupt Mask is.." "MMC Transmit Good Bad Packet Counter Interrupt..,MMC Transmit Good Bad Packet Counter Interrupt.." newline bitfld.long 0x4 0. "TXGBOCTIM,MMC Transmit Good Bad Octet Counter Interrupt Mask Setting this bit masks the interrupt when the txoctetcount_gb counter reaches half of the maximum value or the maximum value. 0x0: MMC Transmit Good Bad Octet Counter Interrupt Mask is disabled.." "MMC Transmit Good Bad Octet Counter Interrupt..,MMC Transmit Good Bad Octet Counter Interrupt.." rgroup.long 0x714++0x67 line.long 0x0 "TX_OCTET_COUNT_GOOD_BAD,This register provides the number of bytes transmitted by the DWC_ether_qos. exclusive of preamble and retried bytes. in good and bad packets." hexmask.long 0x0 0.--31. 1. "TXOCTGB,Tx Octet Count Good Bad This field indicates the number of bytes transmitted exclusive of preamble and retried bytes in good and bad packets." line.long 0x4 "TX_PACKET_COUNT_GOOD_BAD,This register provides the number of good and bad packets transmitted by DWC_ether_qos. exclusive of retried packets." hexmask.long 0x4 0.--31. 1. "TXPKTGB,Tx Packet Count Good Bad This field indicates the number of good and bad packets transmitted exclusive of retried packets." line.long 0x8 "TX_BROADCAST_PACKETS_GOOD,This register provides the number of good broadcast packets transmitted by DWC_ether_qos." hexmask.long 0x8 0.--31. 1. "TXBCASTG,Tx Broadcast Packets Good This field indicates the number of good broadcast packets transmitted." line.long 0xC "TX_MULTICAST_PACKETS_GOOD,This register provides the number of good multicast packets transmitted by DWC_ether_qos." hexmask.long 0xC 0.--31. 1. "TXMCASTG,Tx Multicast Packets Good This field indicates the number of good multicast packets transmitted." line.long 0x10 "TX_64OCTETS_PACKETS_GOOD_BAD,This register provides the number of good and bad packets transmitted by DWC_ether_qos with length 64 bytes. exclusive of preamble and retried packets." hexmask.long 0x10 0.--31. 1. "TX64OCTGB,Tx 64Octets Packets Good_Bad This field indicates the number of good and bad packets transmitted with length 64 bytes exclusive of preamble and retried packets." line.long 0x14 "TX_65TO127OCTETS_PACKETS_GOOD_BAD,This register provides the number of good and bad packets transmitted by DWC_ether_qos with length between 65 and 127 (inclusive) bytes. exclusive of preamble and retried packets." hexmask.long 0x14 0.--31. 1. "TX65_127OCTGB,Tx 65To127Octets Packets Good Bad This field indicates the number of good and bad packets transmitted with length between 65 and 127 (inclusive) bytes exclusive of preamble and retried packets." line.long 0x18 "TX_128TO255OCTETS_PACKETS_GOOD_BAD,This register provides the number of good and bad packets transmitted by DWC_ether_qos with length between 128 to 255 (inclusive) bytes. exclusive of preamble and retried packets." hexmask.long 0x18 0.--31. 1. "TX128_255OCTGB,Tx 128To255Octets Packets Good Bad This field indicates the number of good and bad packets transmitted with length between 128 and 255 (inclusive) bytes exclusive of preamble and retried packets." line.long 0x1C "TX_256TO511OCTETS_PACKETS_GOOD_BAD,This register provides the number of good and bad packets transmitted by DWC_ether_qos with length between 256 to 511 (inclusive) bytes. exclusive of preamble and retried packets." hexmask.long 0x1C 0.--31. 1. "TX256_511OCTGB,Tx 256To511Octets Packets Good Bad This field indicates the number of good and bad packets transmitted with length between 256 and 511 (inclusive) bytes exclusive of preamble and retried packets." line.long 0x20 "TX_512TO1023OCTETS_PACKETS_GOOD_BAD,This register provides the number of good and bad packets transmitted by DWC_ether_qos with length 512 to 1023 (inclusive) bytes. exclusive of preamble and retried packets." hexmask.long 0x20 0.--31. 1. "TX512_1023OCTGB,Tx 512To1023Octets Packets Good Bad This field indicates the number of good and bad packets transmitted with length between 512 and 1023 (inclusive) bytes exclusive of preamble and retried packets." line.long 0x24 "TX_1024TOMAXOCTETS_PACKETS_GOOD_BAD,This register provides the number of good and bad packets transmitted by DWC_ether_qos with length 1024 to maxsize (inclusive) bytes. exclusive of preamble and retried packets." hexmask.long 0x24 0.--31. 1. "TX1024_MAXOCTGB,Tx 1024ToMaxOctets Packets Good Bad This field indicates the number of good and bad packets transmitted with length between 1024 and maxsize (inclusive) bytes exclusive of preamble and retried packets." line.long 0x28 "TX_UNICAST_PACKETS_GOOD_BAD,This register provides the number of good and bad unicast packets transmitted by DWC_ether_qos." hexmask.long 0x28 0.--31. 1. "TXUCASTGB,Tx Unicast Packets Good Bad This field indicates the number of good and bad unicast packets transmitted." line.long 0x2C "TX_MULTICAST_PACKETS_GOOD_BAD,This register provides the number of good and bad multicast packets transmitted by DWC_ether_qos." hexmask.long 0x2C 0.--31. 1. "TXMCASTGB,Tx Multicast Packets Good Bad This field indicates the number of good and bad multicast packets transmitted." line.long 0x30 "TX_BROADCAST_PACKETS_GOOD_BAD,This register provides the number of good and bad broadcast packets transmitted by DWC_ether_qos." hexmask.long 0x30 0.--31. 1. "TXBCASTGB,Tx Broadcast Packets Good Bad This field indicates the number of good and bad broadcast packets transmitted." line.long 0x34 "TX_UNDERFLOW_ERROR_PACKETS,This register provides the number of packets aborted by DWC_ether_qos because of packets underflow error." hexmask.long 0x34 0.--31. 1. "TXUNDRFLW,Tx Underflow Error Packets This field indicates the number of packets aborted because of packets underflow error." line.long 0x38 "TX_SINGLE_COLLISION_GOOD_PACKETS,This register provides the number of successfully transmitted packets by DWC_ether_qos after a single collision in the half-duplex mode." hexmask.long 0x38 0.--31. 1. "TXSNGLCOLG,Tx Single Collision Good Packets This field indicates the number of successfully transmitted packets after a single collision in the half-duplex mode." line.long 0x3C "TX_MULTIPLE_COLLISION_GOOD_PACKETS,This register provides the number of successfully transmitted packets by DWC_ether_qos after multiple collisions in the half-duplex mode." hexmask.long 0x3C 0.--31. 1. "TXMULTCOLG,Tx Multiple Collision Good Packets This field indicates the number of successfully transmitted packets after multiple collisions in the half-duplex mode." line.long 0x40 "TX_DEFERRED_PACKETS,This register provides the number of successfully transmitted by DWC_ether_qos after a deferral in the half-duplex mode." hexmask.long 0x40 0.--31. 1. "TXDEFRD,Tx Deferred Packets This field indicates the number of successfully transmitted after a deferral in the half-duplex mode." line.long 0x44 "TX_LATE_COLLISION_PACKETS,This register provides the number of packets aborted by DWC_ether_qos because of late collision error." hexmask.long 0x44 0.--31. 1. "TXLATECOL,Tx Late Collision Packets This field indicates the number of packets aborted because of late collision error." line.long 0x48 "TX_EXCESSIVE_COLLISION_PACKETS,This register provides the number of packets aborted by DWC_ether_qos because of excessive (16) collision errors." hexmask.long 0x48 0.--31. 1. "TXEXSCOL,Tx Excessive Collision Packets This field indicates the number of packets aborted because of excessive (16) collision errors." line.long 0x4C "TX_CARRIER_ERROR_PACKETS,This register provides the number of packets aborted by DWC_ether_qos because of carrier sense error (no carrier or loss of carrier)." hexmask.long 0x4C 0.--31. 1. "TXCARR,Tx Carrier Error Packets This field indicates the number of packets aborted because of carrier sense error (no carrier or loss of carrier)." line.long 0x50 "TX_OCTET_COUNT_GOOD,This register provides the number of bytes transmitted by DWC_ether_qos. exclusive of preamble. only in good packets." hexmask.long 0x50 0.--31. 1. "TXOCTG,Tx Octet Count Good This field indicates the number of bytes transmitted exclusive of preamble only in good packets." line.long 0x54 "TX_PACKET_COUNT_GOOD,This register provides the number of good packets transmitted by DWC_ether_qos." hexmask.long 0x54 0.--31. 1. "TXPKTG,Tx Packet Count Good This field indicates the number of good packets transmitted." line.long 0x58 "TX_EXCESSIVE_DEFERRAL_ERROR,This register provides the number of packets aborted by DWC_ether_qos because of excessive deferral error (deferred for more than two max-sized packet times)." hexmask.long 0x58 0.--31. 1. "TXEXSDEF,Tx Excessive Deferral Error This field indicates the number of packets aborted because of excessive deferral error (deferred for more than two max-sized packet times)." line.long 0x5C "TX_PAUSE_PACKETS,This register provides the number of good Pause packets transmitted by DWC_ether_qos." hexmask.long 0x5C 0.--31. 1. "TXPAUSE,Tx Pause Packets This field indicates the number of good Pause packets transmitted." line.long 0x60 "TX_VLAN_PACKETS_GOOD,This register provides the number of good VLAN packets transmitted by DWC_ether_qos." hexmask.long 0x60 0.--31. 1. "TXVLANG,Tx VLAN Packets Good This field provides the number of good VLAN packets transmitted." line.long 0x64 "TX_OSIZE_PACKETS_GOOD,This register provides the number of packets transmitted by DWC_ether_qos without errors and with length greater than the maxsize (1.518 or 1.522 bytes for VLAN tagged packets; 2000 bytes if enabled in S2KP bit of the.." hexmask.long 0x64 0.--31. 1. "TXOSIZG,Tx OSize Packets Good This field indicates the number of packets transmitted without errors and with length greater than the maxsize (1 518 or 1 522 bytes for VLAN tagged packets; 2000 bytes if enabled in S2KP bit of the MAC_Configuration.." rgroup.long 0x780++0x67 line.long 0x0 "RX_PACKETS_COUNT_GOOD_BAD,This register provides the number of good and bad packets received by DWC_ether_qos." hexmask.long 0x0 0.--31. 1. "RXPKTGB,Rx Packets Count Good Bad This field indicates the number of good and bad packets received." line.long 0x4 "RX_OCTET_COUNT_GOOD_BAD,This register provides the number of bytes received by DWC_ther_qos. exclusive of preamble. in good and bad packets." hexmask.long 0x4 0.--31. 1. "RXOCTGB,Rx Octet Count Good Bad This field indicates the number of bytes received exclusive of preamble in good and bad packets." line.long 0x8 "RX_OCTET_COUNT_GOOD,This register provides the number of bytes received by DWC_ether_qos. exclusive of preamble. only in good packets." hexmask.long 0x8 0.--31. 1. "RXOCTG,Rx Octet Count Good This field indicates the number of bytes received exclusive of preamble only in good packets." line.long 0xC "RX_BROADCAST_PACKETS_GOOD,This register provides the number of good broadcast packets received by DWC_ether_qos." hexmask.long 0xC 0.--31. 1. "RXBCASTG,Rx Broadcast Packets Good This field indicates the number of good broadcast packets received." line.long 0x10 "RX_MULTICAST_PACKETS_GOOD,This register provides the number of good multicast packets received by DWC_ether_qos." hexmask.long 0x10 0.--31. 1. "RXMCASTG,Rx Multicast Packets Good This field indicates the number of good multicast packets received." line.long 0x14 "RX_CRC_ERROR_PACKETS,This register provides the number of packets received by DWC_ether_qos with CRC error." hexmask.long 0x14 0.--31. 1. "RXCRCERR,Rx CRC Error Packets This field indicates the number of packets received with CRC error." line.long 0x18 "RX_ALIGNMENT_ERROR_PACKETS,This register provides the number of packets received by DWC_ether_qos with alignment (dribble) error. It is valid only in 10/100 mode." hexmask.long 0x18 0.--31. 1. "RXALGNERR,Rx Alignment Error Packets This field indicates the number of packets received with alignment (dribble) error. It is valid only in 10/100 mode." line.long 0x1C "RX_RUNT_ERROR_PACKETS,This register provides the number of packets received by DWC_ether_qos with runt (length less than 64 bytes and CRC error) error." hexmask.long 0x1C 0.--31. 1. "RXRUNTERR,Rx Runt Error Packets This field indicates the number of packets received with runt (length less than 64 bytes and CRC error) error." line.long 0x20 "RX_JABBER_ERROR_PACKETS,This register provides the number of giant packets received by DWC_ether_qos with length (including CRC) greater than 1.518 bytes (1.522 bytes for VLAN tagged) and with CRC error. If Jumbo Packet mode is enabled. packets of length.." hexmask.long 0x20 0.--31. 1. "RXJABERR,Rx Jabber Error Packets This field indicates the number of giant packets received with length (including CRC) greater than 1 518 bytes (1 522 bytes for VLAN tagged) and with CRC error. If Jumbo Packet mode is enabled packets of length greater.." line.long 0x24 "RX_UNDERSIZE_PACKETS_GOOD,This register provides the number of packets received by DWC_ether_qos with length less than 64 bytes. without any errors." hexmask.long 0x24 0.--31. 1. "RXUNDERSZG,Rx Undersize Packets Good This field indicates the number of packets received with length less than 64 bytes without any errors." line.long 0x28 "RX_OVERSIZE_PACKETS_GOOD,This register provides the number of packets received by DWC_ether_qos without errors. with length greater than the maxsize (1.518 bytes or 1.522 bytes for VLAN tagged packets; 2000 bytes if enabled in the S2KP bit of the.." hexmask.long 0x28 0.--31. 1. "RXOVERSZG,Rx Oversize Packets Good This field indicates the number of packets received without errors with length greater than the maxsize (1 518 bytes or 1 522 bytes for VLAN tagged packets; 2000 bytes if enabled in the S2KP bit of the.." line.long 0x2C "RX_64OCTETS_PACKETS_GOOD_BAD,This register provides the number of good and bad packets received by DWC_ether_qos with length 64 bytes. exclusive of the preamble." hexmask.long 0x2C 0.--31. 1. "RX64OCTGB,Rx 64 Octets Packets Good Bad This field indicates the number of good and bad packets received with length 64 bytes exclusive of the preamble." line.long 0x30 "RX_65TO127OCTETS_PACKETS_GOOD_BAD,This register provides the number of good and bad packets received by DWC_ether_qos with length between 65 and 127 (inclusive) bytes. exclusive of the preamble." hexmask.long 0x30 0.--31. 1. "RX65_127OCTGB,Rx 65-127 Octets Packets Good Bad This field indicates the number of good and bad packets received with length between 65 and 127 (inclusive) bytes exclusive of the preamble." line.long 0x34 "RX_128TO255OCTETS_PACKETS_GOOD_BAD,This register provides the number of good and bad packets received by DWC_ether_qos with length between 128 and 255 (inclusive) bytes. exclusive of the preamble." hexmask.long 0x34 0.--31. 1. "RX128_255OCTGB,Rx 128-255 Octets Packets Good Bad This field indicates the number of good and bad packets received with length between 128 and 255 (inclusive) bytes exclusive of the preamble." line.long 0x38 "RX_256TO511OCTETS_PACKETS_GOOD_BAD,This register provides the number of good and bad packets received by DWC_ether_qos with length between 256 and 511 (inclusive) bytes. exclusive of the preamble." hexmask.long 0x38 0.--31. 1. "RX256_511OCTGB,Rx 256-511 Octets Packets Good Bad This field indicates the number of good and bad packets received with length between 256 and 511 (inclusive) bytes exclusive of the preamble." line.long 0x3C "RX_512TO1023OCTETS_PACKETS_GOOD_BAD,This register provides the number of good and bad packets received by DWC_ether_qos with length between 512 and 1023 (inclusive) bytes. exclusive of the preamble." hexmask.long 0x3C 0.--31. 1. "RX512_1023OCTGB,RX 512-1023 Octets Packets Good Bad This field indicates the number of good and bad packets received with length between 512 and 1023 (inclusive) bytes exclusive of the preamble." line.long 0x40 "RX_1024TOMAXOCTETS_PACKETS_GOOD_BAD,This register provides the number of good and bad packets received by DWC_ether_qos with length between 1024 and maxsize (inclusive) bytes. exclusive of the preamble." hexmask.long 0x40 0.--31. 1. "RX1024_MAXOCTGB,Rx 1024-Max Octets Good Bad This field indicates the number of good and bad packets received with length between 1024 and maxsize (inclusive) bytes exclusive of the preamble." line.long 0x44 "RX_UNICAST_PACKETS_GOOD,This register provides the number of good unicast packets received by DWC_ether_qos." hexmask.long 0x44 0.--31. 1. "RXUCASTG,Rx Unicast Packets Good This field indicates the number of good unicast packets received." line.long 0x48 "RX_LENGTH_ERROR_PACKETS,This register provides the number of packets received by DWC_ether_qos with length error (Length Type field not equal to packet size). for all packets with valid length field." hexmask.long 0x48 0.--31. 1. "RXLENERR,Rx Length Error Packets This field indicates the number of packets received with length error (Length Type field not equal to packet size) for all packets with valid length field." line.long 0x4C "RX_OUT_OF_RANGE_TYPE_PACKETS,This register provides the number of packets received by DWC_ether_qos with length field not equal to the valid packet size (greater than 1.500 but less than 1.536)." hexmask.long 0x4C 0.--31. 1. "RXOUTOFRNG,Rx Out of Range Type Packet This field indicates the number of packets received with length field not equal to the valid packet size (greater than 1 500 but less than 1 536)." line.long 0x50 "RX_PAUSE_PACKETS,This register provides the number of good and valid Pause packets received by DWC_ether_qos." hexmask.long 0x50 0.--31. 1. "RXPAUSEPKT,Rx Pause Packets This field indicates the number of good and valid Pause packets received." line.long 0x54 "RX_FIFO_OVERFLOW_PACKETS,This register provides the number of missed received packets because of FIFO overflow in DWC_ether_qos." hexmask.long 0x54 0.--31. 1. "RXFIFOOVFL,Rx FIFO Overflow Packets This field indicates the number of missed received packets because of FIFO overflow." line.long 0x58 "RX_VLAN_PACKETS_GOOD_BAD,This register provides the number of good and bad VLAN packets received by DWC_ether_qos." hexmask.long 0x58 0.--31. 1. "RXVLANPKTGB,Rx VLAN Packets Good Bad This field indicates the number of good and bad VLAN packets received." line.long 0x5C "RX_WATCHDOG_ERROR_PACKETS,This register provides the number of packets received by DWC_ether_qos with error because of watchdog timeout error (packets with a data load larger than 2.048 bytes (when JE and WD bits are reset in MAC_Configuration register)." hexmask.long 0x5C 0.--31. 1. "RXWDGERR,Rx Watchdog Error Packets This field indicates the number of packets received with error because of watchdog timeout error (packets with a data load larger than 2 048 bytes (when JE and WD bits are reset in MAC_Configuration register) 10 240.." line.long 0x60 "RX_RECEIVE_ERROR_PACKETS,This register provides the number of packets received by DWC_ether_qos with Receive error or Packet Extension error on the GMII or MII interface." hexmask.long 0x60 0.--31. 1. "RXRCVERR,Rx Receive Error Packets This field indicates the number of packets received with Receive error or Packet Extension error on the GMII or MII interface." line.long 0x64 "RX_CONTROL_PACKETS_GOOD,This register provides the number of good control packets received by DWC_ether_qos." hexmask.long 0x64 0.--31. 1. "RXCTRLG,Rx Control Packets Good This field indicates the number of good control packets received." rgroup.long 0x7EC++0xF line.long 0x0 "TX_LPI_USEC_CNTR,This register provides the number of microseconds Tx LPI is asserted by DWC_ether_qos." hexmask.long 0x0 0.--31. 1. "TXLPIUSC,Tx LPI Microseconds Counter This field indicates the number of microseconds Tx LPI is asserted. For every Tx LPI Entry and Exit the Timer value can have an error of +/- 1 microsecond." line.long 0x4 "TX_LPI_TRAN_CNTR,This register provides the number of times DWC_ether_qos has entered Tx LPI." hexmask.long 0x4 0.--31. 1. "TXLPITRC,Tx LPI Transition counter This field indicates the number of times Tx LPI Entry has occurred. Even if Tx LPI Entry occurs in Automate Mode (because of LPITXA bit set in the LPI Control and Status register) the counter will increment." line.long 0x8 "RX_LPI_USEC_CNTR,This register provides the number of microseconds Rx LPI is sampled by DWC_ether_qos." hexmask.long 0x8 0.--31. 1. "RXLPIUSC,Rx LPI Microseconds Counter This field indicates the number of microseconds Rx LPI is asserted. For every Rx LPI Entry and Exit the Timer value can have an error of +/- 1 microsecond." line.long 0xC "RX_LPI_TRAN_CNTR,This register provides the number of times DWC_ether_qos has entered Rx LPI." hexmask.long 0xC 0.--31. 1. "RXLPITRC,Rx LPI Transition counter This field indicates the number of times Rx LPI Entry has occurred." group.long 0x800++0x3 line.long 0x0 "MMC_IPC_RX_INTERRUPT_MASK,This register maintains the mask for the interrupt generated from the receive IPC statistic counters. The MMC Receive Checksum Off load Interrupt Mask register maintains the masks for the interrupts generated when the receive.." rbitfld.long 0x0 30.--31. "RESERVED_31_30,Reserved." "0,1,2,3" newline bitfld.long 0x0 29. "RXICMPEROIM,MMC Receive ICMP Error Octet Counter Interrupt Mask Setting this bit masks the interrupt when the rxicmp_err_octets counter reaches half of the maximum value or the maximum value. 0x0: MMC Receive ICMP Error Octet Counter Interrupt Mask is.." "MMC Receive ICMP Error Octet Counter Interrupt..,MMC Receive ICMP Error Octet Counter Interrupt.." newline bitfld.long 0x0 28. "RXICMPGOIM,MMC Receive ICMP Good Octet Counter Interrupt Mask Setting this bit masks the interrupt when the rxicmp_gd_octets counter reaches half of the maximum value or the maximum value. 0x0: MMC Receive ICMP Good Octet Counter Interrupt Mask is.." "MMC Receive ICMP Good Octet Counter Interrupt..,MMC Receive ICMP Good Octet Counter Interrupt.." newline bitfld.long 0x0 27. "RXTCPEROIM,MMC Receive TCP Error Octet Counter Interrupt Mask Setting this bit masks the interrupt when the rxtcp_err_octets counter reaches half of the maximum value or the maximum value. 0x0: MMC Receive TCP Error Octet Counter Interrupt Mask is.." "MMC Receive TCP Error Octet Counter Interrupt..,MMC Receive TCP Error Octet Counter Interrupt.." newline bitfld.long 0x0 26. "RXTCPGOIM,MMC Receive TCP Good Octet Counter Interrupt Mask Setting this bit masks the interrupt when the rxtcp_gd_octets counter reaches half of the maximum value or the maximum value. 0x0: MMC Receive TCP Good Octet Counter Interrupt Mask is disabled.." "MMC Receive TCP Good Octet Counter Interrupt..,MMC Receive TCP Good Octet Counter Interrupt.." newline bitfld.long 0x0 25. "RXUDPEROIM,MMC Receive UDP Good Octet Counter Interrupt Mask Setting this bit masks the interrupt when the rxudp_err_octets counter reaches half of the maximum value or the maximum value. 0x0: MMC Receive UDP Good Octet Counter Interrupt Mask is disabled.." "MMC Receive UDP Good Octet Counter Interrupt..,MMC Receive UDP Good Octet Counter Interrupt.." newline bitfld.long 0x0 24. "RXUDPGOIM,MMC Receive IPV6 No Payload Octet Counter Interrupt Mask Setting this bit masks the interrupt when the rxudp_gd_octets counter reaches half of the maximum value or the maximum value. 0x0: MMC Receive IPV6 No Payload Octet Counter Interrupt Mask.." "MMC Receive IPV6 No Payload Octet Counter..,MMC Receive IPV6 No Payload Octet Counter.." newline bitfld.long 0x0 23. "RXIPV6NOPAYOIM,MMC Receive IPV6 Header Error Octet Counter Interrupt Mask Setting this bit masks the interrupt when the rxipv6_nopay_octets counter reaches half of the maximum value or the maximum value. 0x0: MMC Receive IPV6 Header Error Octet Counter.." "MMC Receive IPV6 Header Error Octet Counter..,MMC Receive IPV6 Header Error Octet Counter.." newline bitfld.long 0x0 22. "RXIPV6HEROIM,MMC Receive IPV6 Good Octet Counter Interrupt Mask Setting this bit masks the interrupt when the rxipv6_hdrerr_octets counter reaches half of the maximum value or the maximum value. 0x0: MMC Receive IPV6 Good Octet Counter Interrupt Mask is.." "MMC Receive IPV6 Good Octet Counter Interrupt..,MMC Receive IPV6 Good Octet Counter Interrupt.." newline bitfld.long 0x0 21. "RXIPV6GOIM,MMC Receive IPV6 Good Octet Counter Interrupt Mask Setting this bit masks the interrupt when the rxipv6_gd_octets counter reaches half of the maximum value or the maximum value. 0x0: MMC Receive IPV6 Good Octet Counter Interrupt Mask is.." "MMC Receive IPV6 Good Octet Counter Interrupt..,MMC Receive IPV6 Good Octet Counter Interrupt.." newline bitfld.long 0x0 20. "RXIPV4UDSBLOIM,MMC Receive IPV4 UDP Checksum Disabled Octet Counter Interrupt Mask Setting this bit masks the interrupt when the rxipv4_udsbl_octets counter reaches half of the maximum value or the maximum value. 0x0: MMC Receive IPV4 UDP Checksum.." "MMC Receive IPV4 UDP Checksum Disabled Octet..,MMC Receive IPV4 UDP Checksum Disabled Octet.." newline bitfld.long 0x0 19. "RXIPV4FRAGOIM,MMC Receive IPV4 Fragmented Octet Counter Interrupt Mask Setting this bit masks the interrupt when the rxipv4_frag_octets counter reaches half of the maximum value or the maximum value. 0x0: MMC Receive IPV4 Fragmented Octet Counter.." "MMC Receive IPV4 Fragmented Octet Counter..,MMC Receive IPV4 Fragmented Octet Counter.." newline bitfld.long 0x0 18. "RXIPV4NOPAYOIM,MMC Receive IPV4 No Payload Octet Counter Interrupt Mask Setting this bit masks the interrupt when the rxipv4_nopay_octets counter reaches half of the maximum value or the maximum value. 0x0: MMC Receive IPV4 No Payload Octet Counter.." "MMC Receive IPV4 No Payload Octet Counter..,MMC Receive IPV4 No Payload Octet Counter.." newline bitfld.long 0x0 17. "RXIPV4HEROIM,MMC Receive IPV4 Header Error Octet Counter Interrupt Mask Setting this bit masks the interrupt when the rxipv4_hdrerr_octets counter reaches half of the maximum value or the maximum value. 0x0: MMC Receive IPV4 Header Error Octet Counter.." "MMC Receive IPV4 Header Error Octet Counter..,MMC Receive IPV4 Header Error Octet Counter.." newline bitfld.long 0x0 16. "RXIPV4GOIM,MMC Receive IPV4 Good Octet Counter Interrupt Mask Setting this bit masks the interrupt when the rxipv4_gd_octets counter reaches half of the maximum value or the maximum value. 0x0: MMC Receive IPV4 Good Octet Counter Interrupt Mask is.." "MMC Receive IPV4 Good Octet Counter Interrupt..,MMC Receive IPV4 Good Octet Counter Interrupt.." newline rbitfld.long 0x0 14.--15. "RESERVED_15_14,Reserved." "0,1,2,3" newline bitfld.long 0x0 13. "RXICMPERPIM,MMC Receive ICMP Error Packet Counter Interrupt Mask Setting this bit masks the interrupt when the rxicmp_err_pkts counter reaches half of the maximum value or the maximum value. 0x0: MMC Receive ICMP Error Packet Counter Interrupt Mask is.." "MMC Receive ICMP Error Packet Counter Interrupt..,MMC Receive ICMP Error Packet Counter Interrupt.." newline bitfld.long 0x0 12. "RXICMPGPIM,MMC Receive ICMP Good Packet Counter Interrupt Mask Setting this bit masks the interrupt when the rxicmp_gd_pkts counter reaches half of the maximum value or the maximum value. 0x0: MMC Receive ICMP Good Packet Counter Interrupt Mask is.." "MMC Receive ICMP Good Packet Counter Interrupt..,MMC Receive ICMP Good Packet Counter Interrupt.." newline bitfld.long 0x0 11. "RXTCPERPIM,MMC Receive TCP Error Packet Counter Interrupt Mask Setting this bit masks the interrupt when the rxtcp_err_pkts counter reaches half of the maximum value or the maximum value. 0x0: MMC Receive TCP Error Packet Counter Interrupt Mask is.." "MMC Receive TCP Error Packet Counter Interrupt..,MMC Receive TCP Error Packet Counter Interrupt.." newline bitfld.long 0x0 10. "RXTCPGPIM,MMC Receive TCP Good Packet Counter Interrupt Mask Setting this bit masks the interrupt when the rxtcp_gd_pkts counter reaches half of the maximum value or the maximum value. 0x0: MMC Receive TCP Good Packet Counter Interrupt Mask is disabled.." "MMC Receive TCP Good Packet Counter Interrupt..,MMC Receive TCP Good Packet Counter Interrupt.." newline bitfld.long 0x0 9. "RXUDPERPIM,MMC Receive UDP Error Packet Counter Interrupt Mask Setting this bit masks the interrupt when the rxudp_err_pkts counter reaches half of the maximum value or the maximum value. 0x0: MMC Receive UDP Error Packet Counter Interrupt Mask is.." "MMC Receive UDP Error Packet Counter Interrupt..,MMC Receive UDP Error Packet Counter Interrupt.." newline bitfld.long 0x0 8. "RXUDPGPIM,MMC Receive UDP Good Packet Counter Interrupt Mask Setting this bit masks the interrupt when the rxudp_gd_pkts counter reaches half of the maximum value or the maximum value. 0x0: MMC Receive UDP Good Packet Counter Interrupt Mask is disabled.." "MMC Receive UDP Good Packet Counter Interrupt..,MMC Receive UDP Good Packet Counter Interrupt.." newline bitfld.long 0x0 7. "RXIPV6NOPAYPIM,MMC Receive IPV6 No Payload Packet Counter Interrupt Mask Setting this bit masks the interrupt when the rxipv6_nopay_pkts counter reaches half of the maximum value or the maximum value. 0x0: MMC Receive IPV6 No Payload Packet Counter.." "MMC Receive IPV6 No Payload Packet Counter..,MMC Receive IPV6 No Payload Packet Counter.." newline bitfld.long 0x0 6. "RXIPV6HERPIM,MMC Receive IPV6 Header Error Packet Counter Interrupt Mask Setting this bit masks the interrupt when the rxipv6_hdrerr_pkts counter reaches half of the maximum value or the maximum value. 0x0: MMC Receive IPV6 Header Error Packet Counter.." "MMC Receive IPV6 Header Error Packet Counter..,MMC Receive IPV6 Header Error Packet Counter.." newline bitfld.long 0x0 5. "RXIPV6GPIM,MMC Receive IPV6 Good Packet Counter Interrupt Mask Setting this bit masks the interrupt when the rxipv6_gd_pkts counter reaches half of the maximum value or the maximum value. 0x0: MMC Receive IPV6 Good Packet Counter Interrupt Mask is.." "MMC Receive IPV6 Good Packet Counter Interrupt..,MMC Receive IPV6 Good Packet Counter Interrupt.." newline bitfld.long 0x0 4. "RXIPV4UDSBLPIM,MMC Receive IPV4 UDP Checksum Disabled Packet Counter Interrupt Mask Setting this bit masks the interrupt when the rxipv4_udsbl_pkts counter reaches half of the maximum value or the maximum value. 0x0: MMC Receive IPV4 UDP Checksum.." "MMC Receive IPV4 UDP Checksum Disabled Packet..,MMC Receive IPV4 UDP Checksum Disabled Packet.." newline bitfld.long 0x0 3. "RXIPV4FRAGPIM,MMC Receive IPV4 Fragmented Packet Counter Interrupt Mask Setting this bit masks the interrupt when the rxipv4_frag_pkts counter reaches half of the maximum value or the maximum value. 0x0: MMC Receive IPV4 Fragmented Packet Counter.." "MMC Receive IPV4 Fragmented Packet Counter..,MMC Receive IPV4 Fragmented Packet Counter.." newline bitfld.long 0x0 2. "RXIPV4NOPAYPIM,MMC Receive IPV4 No Payload Packet Counter Interrupt Mask Setting this bit masks the interrupt when the rxipv4_nopay_pkts counter reaches half of the maximum value or the maximum value. 0x0: MMC Receive IPV4 No Payload Packet Counter.." "MMC Receive IPV4 No Payload Packet Counter..,MMC Receive IPV4 No Payload Packet Counter.." newline bitfld.long 0x0 1. "RXIPV4HERPIM,MMC Receive IPV4 Header Error Packet Counter Interrupt Mask Setting this bit masks the interrupt when the rxipv4_hdrerr_pkts counter reaches half of the maximum value or the maximum value. 0x0: MMC Receive IPV4 Header Error Packet Counter.." "MMC Receive IPV4 Header Error Packet Counter..,MMC Receive IPV4 Header Error Packet Counter.." newline bitfld.long 0x0 0. "RXIPV4GPIM,MMC Receive IPV4 Good Packet Counter Interrupt Mask Setting this bit masks the interrupt when the rxipv4_gd_pkts counter reaches half of the maximum value or the maximum value. 0x0: MMC Receive IPV4 Good Packet Counter Interrupt Mask is.." "MMC Receive IPV4 Good Packet Counter Interrupt..,MMC Receive IPV4 Good Packet Counter Interrupt.." rgroup.long 0x808++0x3 line.long 0x0 "MMC_IPC_RX_INTERRUPT,This register maintains the interrupt that the receive IPC statistic counters generate. The MMC Receive Checksum Offload Interrupt register maintains the interrupts generated when receive IPC statistic counters reach half their.." bitfld.long 0x0 30.--31. "RESERVED_31_30,Reserved." "0,1,2,3" newline bitfld.long 0x0 29. "RXICMPEROIS,MMC Receive ICMP Error Octet Counter Interrupt Status This bit is set when the rxicmp_err_octets counter reaches half of the maximum value or the maximum value. Access restriction applies. Clears on read. Self-set to 1 on internal event. 0x1:.." "MMC Receive ICMP Error Octet Counter Interrupt..,MMC Receive ICMP Error Octet Counter Interrupt.." newline bitfld.long 0x0 28. "RXICMPGOIS,MMC Receive ICMP Good Octet Counter Interrupt Status This bit is set when the rxicmp_gd_octets counter reaches half of the maximum value or the maximum value. Access restriction applies. Clears on read. Self-set to 1 on internal event. 0x1:.." "MMC Receive ICMP Good Octet Counter Interrupt..,MMC Receive ICMP Good Octet Counter Interrupt.." newline bitfld.long 0x0 27. "RXTCPEROIS,MMC Receive TCP Error Octet Counter Interrupt Status This bit is set when the rxtcp_err_octets counter reaches half of the maximum value or the maximum value. Access restriction applies. Clears on read. Self-set to 1 on internal event. 0x1:.." "MMC Receive TCP Error Octet Counter Interrupt..,MMC Receive TCP Error Octet Counter Interrupt.." newline bitfld.long 0x0 26. "RXTCPGOIS,MMC Receive TCP Good Octet Counter Interrupt Status This bit is set when the rxtcp_gd_octets counter reaches half of the maximum value or the maximum value. Access restriction applies. Clears on read. Self-set to 1 on internal event. 0x1: MMC.." "MMC Receive TCP Good Octet Counter Interrupt..,MMC Receive TCP Good Octet Counter Interrupt.." newline bitfld.long 0x0 25. "RXUDPEROIS,MMC Receive UDP Error Octet Counter Interrupt Status This bit is set when the rxudp_err_octets counter reaches half of the maximum value or the maximum value. Access restriction applies. Clears on read. Self-set to 1 on internal event. 0x1:.." "MMC Receive UDP Error Octet Counter Interrupt..,MMC Receive UDP Error Octet Counter Interrupt.." newline bitfld.long 0x0 24. "RXUDPGOIS,MMC Receive UDP Good Octet Counter Interrupt Status This bit is set when the rxudp_gd_octets counter reaches half of the maximum value or the maximum value. Access restriction applies. Clears on read. Self-set to 1 on internal event. 0x1: MMC.." "MMC Receive UDP Good Octet Counter Interrupt..,MMC Receive UDP Good Octet Counter Interrupt.." newline bitfld.long 0x0 23. "RXIPV6NOPAYOIS,MMC Receive IPV6 No Payload Octet Counter Interrupt Status This bit is set when the rxipv6_nopay_octets counter reaches half of the maximum value or the maximum value. Access restriction applies. Clears on read. Self-set to 1 on internal.." "MMC Receive IPV6 No Payload Octet Counter..,MMC Receive IPV6 No Payload Octet Counter.." newline bitfld.long 0x0 22. "RXIPV6HEROIS,MMC Receive IPV6 Header Error Octet Counter Interrupt Status This bit is set when the rxipv6_hdrerr_octets counter reaches half of the maximum value or the maximum value. Access restriction applies. Clears on read. Self-set to 1 on internal.." "MMC Receive IPV6 Header Error Octet Counter..,MMC Receive IPV6 Header Error Octet Counter.." newline bitfld.long 0x0 21. "RXIPV6GOIS,MMC Receive IPV6 Good Octet Counter Interrupt Status This bit is set when the rxipv6_gd_octets counter reaches half of the maximum value or the maximum value. Access restriction applies. Clears on read. Self-set to 1 on internal event. 0x1:.." "MMC Receive IPV6 Good Octet Counter Interrupt..,MMC Receive IPV6 Good Octet Counter Interrupt.." newline bitfld.long 0x0 20. "RXIPV4UDSBLOIS,MMC Receive IPV4 UDP Checksum Disabled Octet Counter Interrupt Status This bit is set when the rxipv4_udsbl_octets counter reaches half of the maximum value or the maximum value. Access restriction applies. Clears on read. Self-set to 1 on.." "MMC Receive IPV4 UDP Checksum Disabled Octet..,MMC Receive IPV4 UDP Checksum Disabled Octet.." newline bitfld.long 0x0 19. "RXIPV4FRAGOIS,MMC Receive IPV4 Fragmented Octet Counter Interrupt Status This bit is set when the rxipv4_frag_octets counter reaches half of the maximum value or the maximum value. Access restriction applies. Clears on read. Self-set to 1 on internal.." "MMC Receive IPV4 Fragmented Octet Counter..,MMC Receive IPV4 Fragmented Octet Counter.." newline bitfld.long 0x0 18. "RXIPV4NOPAYOIS,MMC Receive IPV4 No Payload Octet Counter Interrupt Status This bit is set when the rxipv4_nopay_octets counter reaches half of the maximum value or the maximum value. Access restriction applies. Clears on read. Self-set to 1 on internal.." "MMC Receive IPV4 No Payload Octet Counter..,MMC Receive IPV4 No Payload Octet Counter.." newline bitfld.long 0x0 17. "RXIPV4HEROIS,MMC Receive IPV4 Header Error Octet Counter Interrupt Status This bit is set when the rxipv4_hdrerr_octets counter reaches half of the maximum value or the maximum value. Access restriction applies. Clears on read. Self-set to 1 on internal.." "MMC Receive IPV4 Header Error Octet Counter..,MMC Receive IPV4 Header Error Octet Counter.." newline bitfld.long 0x0 16. "RXIPV4GOIS,MMC Receive IPV4 Good Octet Counter Interrupt Status This bit is set when the rxipv4_gd_octets counter reaches half of the maximum value or the maximum value. Access restriction applies. Clears on read. Self-set to 1 on internal event. 0x1:.." "MMC Receive IPV4 Good Octet Counter Interrupt..,MMC Receive IPV4 Good Octet Counter Interrupt.." newline bitfld.long 0x0 14.--15. "RESERVED_15_14,Reserved." "0,1,2,3" newline bitfld.long 0x0 13. "RXICMPERPIS,MMC Receive ICMP Error Packet Counter Interrupt Status This bit is set when the rxicmp_err_pkts counter reaches half of the maximum value or the maximum value. Access restriction applies. Clears on read. Self-set to 1 on internal event. 0x1:.." "MMC Receive ICMP Error Packet Counter Interrupt..,MMC Receive ICMP Error Packet Counter Interrupt.." newline bitfld.long 0x0 12. "RXICMPGPIS,MMC Receive ICMP Good Packet Counter Interrupt Status This bit is set when the rxicmp_gd_pkts counter reaches half of the maximum value or the maximum value. Access restriction applies. Clears on read. Self-set to 1 on internal event. 0x1: MMC.." "MMC Receive ICMP Good Packet Counter Interrupt..,MMC Receive ICMP Good Packet Counter Interrupt.." newline bitfld.long 0x0 11. "RXTCPERPIS,MMC Receive TCP Error Packet Counter Interrupt Status This bit is set when the rxtcp_err_pkts counter reaches half of the maximum value or the maximum value. Access restriction applies. Clears on read. Self-set to 1 on internal event. 0x1: MMC.." "MMC Receive TCP Error Packet Counter Interrupt..,MMC Receive TCP Error Packet Counter Interrupt.." newline bitfld.long 0x0 10. "RXTCPGPIS,MMC Receive TCP Good Packet Counter Interrupt Status This bit is set when the rxtcp_gd_pkts counter reaches half of the maximum value or the maximum value. Access restriction applies. Clears on read. Self-set to 1 on internal event. 0x1: MMC.." "MMC Receive TCP Good Packet Counter Interrupt..,MMC Receive TCP Good Packet Counter Interrupt.." newline bitfld.long 0x0 9. "RXUDPERPIS,MMC Receive UDP Error Packet Counter Interrupt Status This bit is set when the rxudp_err_pkts counter reaches half of the maximum value or the maximum value. Access restriction applies. Clears on read. Self-set to 1 on internal event. 0x1: MMC.." "MMC Receive UDP Error Packet Counter Interrupt..,MMC Receive UDP Error Packet Counter Interrupt.." newline bitfld.long 0x0 8. "RXUDPGPIS,MC Receive UDP Good Packet Counter Interrupt Status This bit is set when the rxudp_gd_pkts counter reaches half of the maximum value or the maximum value. Access restriction applies. Clears on read. Self-set to 1 on internal event. 0x1: MMC.." "MMC Receive UDP Good Packet Counter Interrupt..,MMC Receive UDP Good Packet Counter Interrupt.." newline bitfld.long 0x0 7. "RXIPV6NOPAYPIS,MMC Receive IPV6 No Payload Packet Counter Interrupt Status This bit is set when the rxipv6_nopay_pkts counter reaches half of the maximum value or the maximum value. Access restriction applies. Clears on read. Self-set to 1 on internal.." "MMC Receive IPV6 No Payload Packet Counter..,MMC Receive IPV6 No Payload Packet Counter.." newline bitfld.long 0x0 6. "RXIPV6HERPIS,MMC Receive IPV6 Header Error Packet Counter Interrupt Status This bit is set when the rxipv6_hdrerr_pkts counter reaches half of the maximum value or the maximum value. Access restriction applies. Clears on read. Self-set to 1 on internal.." "MMC Receive IPV6 Header Error Packet Counter..,MMC Receive IPV6 Header Error Packet Counter.." newline bitfld.long 0x0 5. "RXIPV6GPIS,MMC Receive IPV6 Good Packet Counter Interrupt Status This bit is set when the rxipv6_gd_pkts counter reaches half of the maximum value or the maximum value. Access restriction applies. Clears on read. Self-set to 1 on internal event. 0x1: MMC.." "MMC Receive IPV6 Good Packet Counter Interrupt..,MMC Receive IPV6 Good Packet Counter Interrupt.." newline bitfld.long 0x0 4. "RXIPV4UDSBLPIS,MMC Receive IPV4 UDP Checksum Disabled Packet Counter Interrupt Status This bit is set when the rxipv4_udsbl_pkts counter reaches half of the maximum value or the maximum value. 0x1: MMC Receive IPV4 UDP Checksum Disabled Packet Counter.." "MMC Receive IPV4 UDP Checksum Disabled Packet..,MMC Receive IPV4 UDP Checksum Disabled Packet.." newline bitfld.long 0x0 3. "RXIPV4FRAGPIS,MMC Receive IPV4 Fragmented Packet Counter Interrupt Status This bit is set when the rxipv4_frag_pkts counter reaches half of the maximum value or the maximum value. Access restriction applies. Clears on read. Self-set to 1 on internal.." "MMC Receive IPV4 Fragmented Packet Counter..,MMC Receive IPV4 Fragmented Packet Counter.." newline bitfld.long 0x0 2. "RXIPV4NOPAYPIS,MMC Receive IPV4 No Payload Packet Counter Interrupt Status This bit is set when the rxipv4_nopay_pkts counter reaches half of the maximum value or the maximum value. Access restriction applies. Clears on read. Self-set to 1 on internal.." "MMC Receive IPV4 No Payload Packet Counter..,MMC Receive IPV4 No Payload Packet Counter.." newline bitfld.long 0x0 1. "RXIPV4HERPIS,MMC Receive IPV4 Header Error Packet Counter Interrupt Status This bit is set when the rxipv4_hdrerr_pkts counter reaches half of the maximum value or the maximum value. Access restriction applies. Clears on read. Self-set to 1 on internal.." "MMC Receive IPV4 Header Error Packet Counter..,MMC Receive IPV4 Header Error Packet Counter.." newline bitfld.long 0x0 0. "RXIPV4GPIS,MMC Receive IPV4 Good Packet Counter Interrupt Status This bit is set when the rxipv4_gd_pkts counter reaches half of the maximum value or the maximum value. Access restriction applies. Clears on read. Self-set to 1 on internal event. 0x1: MMC.." "MMC Receive IPV4 Good Packet Counter Interrupt..,MMC Receive IPV4 Good Packet Counter Interrupt.." rgroup.long 0x810++0x37 line.long 0x0 "RXIPV4_GOOD_PACKETS,This register provides the number of good IPv4 datagrams received by DWC_ether_qos with the TCP. UDP. or ICMP payload." hexmask.long 0x0 0.--31. 1. "RXIPV4GDPKT,RxIPv4 Good Packets This field indicates the number of good IPv4 datagrams received with the TCP UDP or ICMP payload." line.long 0x4 "RXIPV4_HEADER_ERROR_PACKETS,RxIPv4 Header Error Packets This register provides the number of IPv4 datagrams received by DWC_ether_qos with header (checksum. length. or version mismatch) errors." hexmask.long 0x4 0.--31. 1. "RXIPV4HDRERRPKT,RxIPv4 Header Error Packets This field indicates the number of IPv4 datagrams received with header (checksum length or version mismatch) errors." line.long 0x8 "RXIPV4_NO_PAYLOAD_PACKETS,This register provides the number of IPv4 datagram packets received by DWC_ether_qos that did not have a TCP. UDP. or ICMP payload." hexmask.long 0x8 0.--31. 1. "RXIPV4NOPAYPKT,RxIPv4 Payload Packets This field indicates the number of IPv4 datagram packets received that did not have a TCP UDP or ICMP payload." line.long 0xC "RXIPV4_FRAGMENTED_PACKETS,This register provides the number of good IPv4 datagrams received by DWC_ether_qos with fragmentation." hexmask.long 0xC 0.--31. 1. "RXIPV4FRAGPKT,RxIPv4 Fragmented Packets This field indicates the number of good IPv4 datagrams received with fragmentation." line.long 0x10 "RXIPV4_UDP_CHECKSUM_DISABLED_PACKETS,This register provides the number of good IPv4 datagrams received by DWC_ether_qos that had a UDP payload with checksum disabled." hexmask.long 0x10 0.--31. 1. "RXIPV4UDSBLPKT,RxIPv4 UDP Checksum Disabled Packets This field indicates the number of good IPv4 datagrams received that had a UDP payload with checksum disabled." line.long 0x14 "RXIPV6_GOOD_PACKETS,This register provides the number of good IPv6 datagrams received by DWC_ether_qos with the TCP. UDP. or ICMP payload." hexmask.long 0x14 0.--31. 1. "RXIPV6GDPKT,RxIPv6 Good Packets This field indicates the number of good IPv6 datagrams received with the TCP UDP or ICMP payload." line.long 0x18 "RXIPV6_HEADER_ERROR_PACKETS,This register provides the number of IPv6 datagrams received by DWC_ether_qos with header (length or version mismatch) errors." hexmask.long 0x18 0.--31. 1. "RXIPV6HDRERRPKT,RxIPv6 Header Error Packets This field indicates the number of IPv6 datagrams received with header (length or version mismatch) errors." line.long 0x1C "RXIPV6_NO_PAYLOAD_PACKETS,This register provides the number of IPv6 datagram packets received by DWC_ether_qos that did not have a TCP. UDP. or ICMP payload. This includes all IPv6 datagrams with fragmentation or security extension headers." hexmask.long 0x1C 0.--31. 1. "RXIPV6NOPAYPKT,RxIPv6 Payload Packets This field indicates the number of IPv6 datagram packets received that did not have a TCP UDP or ICMP payload. This includes all IPv6 datagrams with fragmentation or security extension headers." line.long 0x20 "RXUDP_GOOD_PACKETS,This register provides the number of good IP datagrams received by DWC_ether_qos with a good UDP payload. This counter is not updated when the RxIPv4_UDP_Checksum_Disabled_Packets counter is incremented." hexmask.long 0x20 0.--31. 1. "RXUDPGDPKT,RxUDP Good Packets This field indicates the number of good IP datagrams received with a good UDP payload. This counter is not updated when the RxIPv4_UDP_Checksum_Disabled_Packets counter is incremented." line.long 0x24 "RXUDP_ERROR_PACKETS,This register provides the number of good IP datagrams received by DWC_ether_qos whose UDP payload has a checksum error." hexmask.long 0x24 0.--31. 1. "RXUDPERRPKT,RxUDP Error Packets This field indicates the number of good IP datagrams received whose UDP payload has a checksum error." line.long 0x28 "RXTCP_GOOD_PACKETS,This register provides the number of good IP datagrams received by DWC_ether_qos with a good TCP payload." hexmask.long 0x28 0.--31. 1. "RXTCPGDPKT,RxTCP Good Packets This field indicates the number of good IP datagrams received with a good TCP payload." line.long 0x2C "RXTCP_ERROR_PACKETS,This register provides the number of good IP datagrams received by DWC_ether_qos whose TCP payload has a checksum error." hexmask.long 0x2C 0.--31. 1. "RXTCPERRPKT,RxTCP Error Packets This field indicates the number of good IP datagrams received whose TCP payload has a checksum error." line.long 0x30 "RXICMP_GOOD_PACKETS,This register provides the number of good IP datagrams received by DWC_ether_qos with a good ICMP payload." hexmask.long 0x30 0.--31. 1. "RXICMPGDPKT,RxICMP Good Packets This field indicates the number of good IP datagrams received with a good ICMP payload." line.long 0x34 "RXICMP_ERROR_PACKETS,This register provides the number of good IP datagrams received by DWC_ether_qos whose ICMP payload has a checksum error." hexmask.long 0x34 0.--31. 1. "RXICMPERRPKT,RxICMP Error Packets This field indicates the number of good IP datagrams received whose ICMP payload has a checksum error." rgroup.long 0x850++0x37 line.long 0x0 "RXIPV4_GOOD_OCTETS,This register provides the number of bytes received by DWC_ether_qos in good IPv4 datagrams encapsulating TCP. UDP. or ICMP data. (Ethernet header. FCS. pad. or IP pad bytes are not included in this counter." hexmask.long 0x0 0.--31. 1. "RXIPV4GDOCT,RxIPv4 Good Octets This field indicates the number of bytes received in good IPv4 datagrams encapsulating TCP UDP or ICMP data. (Ethernet header FCS pad or IP pad bytes are not included in this counter." line.long 0x4 "RXIPV4_HEADER_ERROR_OCTETS,This register provides the number of bytes received by DWC_ether_qos in IPv4 datagrams with header errors (checksum. length. version mismatch). The value in the Length field of IPv4 header is used to update this counter." hexmask.long 0x4 0.--31. 1. "RXIPV4HDRERROCT,RxIPv4 Header Error Octets This field indicates the number of bytes received in IPv4 datagrams with header errors (checksum length version mismatch). The value in the Length field of IPv4 header is used to update this counter. (Ethernet.." line.long 0x8 "RXIPV4_NO_PAYLOAD_OCTETS,This register provides the number of bytes received by DWC_ether_qos in IPv4 datagrams that did not have a TCP. UDP. or ICMP payload. The value in the Length field of IPv4 header is used to update this counter. (Ethernet header." hexmask.long 0x8 0.--31. 1. "RXIPV4NOPAYOCT,RxIPv4 Payload Octets This field indicates the number of bytes received in IPv4 datagrams that did not have a TCP UDP or ICMP payload. The value in the Length field of IPv4 header is used to update this counter. (Ethernet header FCS.." line.long 0xC "RXIPV4_FRAGMENTED_OCTETS,This register provides the number of bytes received by DWC_ether_qos in fragmented IPv4 datagrams. The value in the Length field of IPv4 header is used to update this counter. (Ethernet header. FCS. pad. or IP pad bytes are not.." hexmask.long 0xC 0.--31. 1. "RXIPV4FRAGOCT,RxIPv4 Fragmented Octets This field indicates the number of bytes received in fragmented IPv4 datagrams. The value in the Length field of IPv4 header is used to update this counter. (Ethernet header FCS pad or IP pad bytes are not.." line.long 0x10 "RXIPV4_UDP_CHECKSUM_DISABLE_OCTETS,This register provides the number of bytes received by DWC_ether_qos in a UDP segment that had the UDP checksum disabled. This counter does not count IP Header bytes. (Ethernet header. FCS. pad. or IP pad bytes are not.." hexmask.long 0x10 0.--31. 1. "RXIPV4UDSBLOCT,RxIPv4 UDP Checksum Disable Octets This field indicates the number of bytes received in a UDP segment that had the UDP checksum disabled. This counter does not count IP Header bytes. (Ethernet header FCS pad or IP pad bytes are not.." line.long 0x14 "RXIPV6_GOOD_OCTETS,This register provides the number of bytes received by DWC_ether_qos in good IPv6 datagrams encapsulating TCP. UDP. or ICMP data. (Ethernet header. FCS. pad. or IP pad bytes are not included in this counter." hexmask.long 0x14 0.--31. 1. "RXIPV6GDOCT,RxIPv6 Good Octets This field indicates the number of bytes received in good IPv6 datagrams encapsulating TCP UDP or ICMP data. (Ethernet header FCS pad or IP pad bytes are not included in this counter." line.long 0x18 "RXIPV6_HEADER_ERROR_OCTETS,This register provides the number of bytes received by DWC_ether_qos in IPv6 datagrams with header errors (length. version mismatch). The value in the Length field of IPv6 header is used to update this counter. (Ethernet.." hexmask.long 0x18 0.--31. 1. "RXIPV6HDRERROCT,RxIPv6 Header Error Octets This field indicates the number of bytes received in IPv6 datagrams with header errors (length version mismatch). The value in the Length field of IPv6 header is used to update this counter. (Ethernet header.." line.long 0x1C "RXIPV6_NO_PAYLOAD_OCTETS,This register provides the number of bytes received by DWC_ether_qos in IPv6 datagrams that did not have a TCP. UDP. or ICMP payload. The value in the Length field of IPv6 header is used to update this counter. (Ethernet header." hexmask.long 0x1C 0.--31. 1. "RXIPV6NOPAYOCT,RxIPv6 Payload Octets This field indicates the number of bytes received in IPv6 datagrams that did not have a TCP UDP or ICMP payload. The value in the Length field of IPv6 header is used to update this counter. (Ethernet header FCS.." line.long 0x20 "RXUDP_GOOD_OCTETS,This register provides the number of bytes received by DWC_ether_qos in a good UDP segment. This counter does not count IP header bytes." hexmask.long 0x20 0.--31. 1. "RXUDPGDOCT,RxUDP Good Octets This field indicates the number of bytes received in a good UDP segment. This counter does not count IP header bytes." line.long 0x24 "RXUDP_ERROR_OCTETS,This register provides the number of bytes received by DWC_ether_qos in a UDP segment that had checksum errors. This counter does not count IP header bytes." hexmask.long 0x24 0.--31. 1. "RXUDPERROCT,RxUDP Error Octets This field indicates the number of bytes received in a UDP segment that had checksum errors. This counter does not count IP header bytes." line.long 0x28 "RXTCP_GOOD_OCTETS,This register provides the number of bytes received by DWC_ether_qos in a good TCP segment. This counter does not count IP header bytes." hexmask.long 0x28 0.--31. 1. "RXTCPGDOCT,RxTCP Good Octets This field indicates the number of bytes received in a good TCP segment. This counter does not count IP header bytes." line.long 0x2C "RXTCP_ERROR_OCTETS,This register provides the number of bytes received by DWC_ether_qos in a TCP segment that had checksum errors. This counter does not count IP header bytes." hexmask.long 0x2C 0.--31. 1. "RXTCPERROCT,RxTCP Error Octets This field indicates the number of bytes received in a TCP segment that had checksum errors. This counter does not count IP header bytes." line.long 0x30 "RXICMP_GOOD_OCTETS,This register provides the number of bytes received by DWC_ether_qos in a good ICMP segment. This counter does not count IP header bytes." hexmask.long 0x30 0.--31. 1. "RXICMPGDOCT,RxICMP Good Octets This field indicates the number of bytes received in a good ICMP segment. This counter does not count IP header bytes." line.long 0x34 "RXICMP_ERROR_OCTETS,This register provides the number of bytes received by DWC_ether_qos in a ICMP segment that had checksum errors. This counter does not count IP header bytes." hexmask.long 0x34 0.--31. 1. "RXICMPERROCT,RxICMP Error Octets This field indicates the number of bytes received in a ICMP segment that had checksum errors. This counter does not count IP header bytes." rgroup.long 0x8A0++0x3 line.long 0x0 "MMC_FPE_TX_INTERRUPT,This register maintains the interrupts generated from all FPE related Transmit statistics counters. The MMC FPE Transmit Interrupt register maintains the interrupts generated when transmit statistic counters reach half their maximum.." hexmask.long 0x0 2.--31. 1. "RESERVED_31_2,Reserved." newline bitfld.long 0x0 1. "HRCIS,MMC Tx Hold Request Counter Interrupt Status This bit is set when the Tx_Hold_Req_Cntr counter reaches half of the maximum value or the maximum value. Access restriction applies. Clears on read. Self-set to 1 on internal event. Exists when any one.." "MMC Tx Hold Request Counter Interrupt Status not..,MMC Tx Hold Request Counter Interrupt Status.." newline bitfld.long 0x0 0. "FCIS,MMC Tx FPE Fragment Counter Interrupt status This bit is set when the Tx_FPE_Fragment_Cntr counter reaches half of the maximum value or the maximum value. Access restriction applies. Clears on read. Self-set to 1 on internal event. Exists when any.." "MMC Tx FPE Fragment Counter Interrupt status not..,MMC Tx FPE Fragment Counter Interrupt status.." group.long 0x8A4++0x3 line.long 0x0 "MMC_FPE_TX_INTERRUPT_MASK,This register maintains the masks for interrupts generated from all FPE related Transmit statistics counters. The MMC Receive Interrupt Mask register maintains the masks for the interrupts generated when FPE related receive.." hexmask.long 0x0 2.--31. 1. "RESERVED_31_2,Reserved." newline bitfld.long 0x0 1. "HRCIM,MMC Transmit Hold Request Counter Interrupt Mask Setting this bit masks the interrupt when the Tx_Hold_Req_Cntr counter reaches half of the maximum value or the maximum value. Exists when any one of the RX/TX MMC counters are enabled during FPE.." "MMC Transmit Hold Request Counter Interrupt Mask..,MMC Transmit Hold Request Counter Interrupt Mask.." newline bitfld.long 0x0 0. "FCIM,MMC Transmit Fragment Counter Interrupt Mask Setting this bit masks the interrupt when the Tx_FPE_Fragment_Cntr counter reaches half of the maximum value or the maximum value. Exists when any one of the RX/TX MMC counters are enabled during FPE.." "MMC Transmit Fragment Counter Interrupt Mask is..,MMC Transmit Fragment Counter Interrupt Mask is.." rgroup.long 0x8A8++0x7 line.long 0x0 "MMC_TX_FPE_FRAGMENT_CNTR,This register provides the number of additional mPackets transmitted due to preemption." hexmask.long 0x0 0.--31. 1. "TXFFC,Tx FPE Fragment counter This field indicates the number of additional mPackets that has been transmitted due to preemption Exists when any one of the RX/TX MMC counters are enabled during FPE Enabled configuration." line.long 0x4 "MMC_TX_HOLD_REQ_CNTR,This register provides the count of number of times a hold request is given to MAC" hexmask.long 0x4 0.--31. 1. "TXHRC,Tx Hold Request Counter This field indicates count of number of a hold request is given to MAC. Exists when any one of the RX/TX MMC counters are enabled during FPE with AV_EST Enabled configuration." rgroup.long 0x8C0++0x3 line.long 0x0 "MMC_FPE_RX_INTERRUPT,This register maintains the interrupts generated from all FPE related Receive statistics counters. The MMC FPE Receive Interrupt register maintains the interrupts generated when transmit statistic counters reach half their maximum.." hexmask.long 0x0 4.--31. 1. "RESERVED_31_4,Reserved." newline bitfld.long 0x0 3. "FCIS,MMC Rx FPE Fragment Counter Interrupt Status This bit is set when the Rx_FPE_Fragment_Cntr counter reaches half of the maximum value or the maximum value. Access restriction applies. Clears on read. Self-set to 1 on internal event. Exists when any.." "MMC Rx FPE Fragment Counter Interrupt Status not..,MMC Rx FPE Fragment Counter Interrupt Status.." newline bitfld.long 0x0 2. "PAOCIS,MMC Rx Packet Assembly OK Counter Interrupt Status This bit is set when the Rx_Packet_Assemble_Ok_Cntr counter reaches half of the maximum value or the maximum value. Access restriction applies. Clears on read. Self-set to 1 on internal event." "MMC Rx Packet Assembly OK Counter Interrupt..,MMC Rx Packet Assembly OK Counter Interrupt.." newline bitfld.long 0x0 1. "PSECIS,MMC Rx Packet SMD Error Counter Interrupt Status This bit is set when the Rx_Packet_SMD_Err_Cntr counter reaches half of the maximum value or the maximum value. Access restriction applies. Clears on read. Self-set to 1 on internal event. Exists.." "MMC Rx Packet SMD Error Counter Interrupt Status..,MMC Rx Packet SMD Error Counter Interrupt Status.." newline bitfld.long 0x0 0. "PAECIS,MMC Rx Packet Assembly Error Counter Interrupt Status This bit is set when the Rx_Packet_Assemble_Err_Cntr counter reaches half of the maximum value or the maximum value. Access restriction applies. Clears on read. Self-set to 1 on internal event." "MMC Rx Packet Assembly Error Counter Interrupt..,MMC Rx Packet Assembly Error Counter Interrupt.." group.long 0x8C4++0x3 line.long 0x0 "MMC_FPE_RX_INTERRUPT_MASK,This register maintains the masks for interrupts generated from all FPE related Receive statistics counters. The MMC Receive Interrupt Mask register maintains the masks for the interrupts generated when FPE related receive.." hexmask.long 0x0 4.--31. 1. "RESERVED_31_4,Reserved." newline bitfld.long 0x0 3. "FCIM,MMC Rx FPE Fragment Counter Interrupt Mask Setting this bit masks the interrupt when the Tx_FPE_Fragment_Cntr counter reaches half of the maximum value or the maximum value. Exists when any one of the RX/TX MMC counters are enabled during FPE.." "MMC Rx FPE Fragment Counter Interrupt Mask is..,MMC Rx FPE Fragment Counter Interrupt Mask is.." newline bitfld.long 0x0 2. "PAOCIM,MMC Rx Packet Assembly OK Counter Interrupt Mask Setting this bit masks the interrupt when the Rx_Packet_Assemble_Ok_Cntr counter reaches half of the maximum value or the maximum value. Exists when any one of the RX/TX MMC counters are enabled.." "MMC Rx Packet Assembly OK Counter Interrupt Mask..,MMC Rx Packet Assembly OK Counter Interrupt Mask.." newline bitfld.long 0x0 1. "PSECIM,MMC Rx Packet SMD Error Counter Interrupt Mask Setting this bit masks the interrupt when the R Rx_Packet_SMD_Err_Cntr counter reaches half of the maximum value or the maximum value. Exists when any one of the RX/TX MMC counters are enabled during.." "MMC Rx Packet SMD Error Counter Interrupt Mask..,MMC Rx Packet SMD Error Counter Interrupt Mask.." newline bitfld.long 0x0 0. "PAECIM,MMC Rx Packet Assembly Error Counter Interrupt Mask Setting this bit masks the interrupt when the R Rx_Packet_Assemble_Err_Cntr counter reaches half of the maximum value or the maximum value. Exists when any one of the RX/TX MMC counters are.." "MMC Rx Packet Assembly Error Counter Interrupt..,MMC Rx Packet Assembly Error Counter Interrupt.." rgroup.long 0x8C8++0xF line.long 0x0 "MMC_RX_PACKET_ASSEMBLY_ERR_CNTR,This register provides the number of MAC frames with reassembly errors on the Receiver. due to mismatch in the Fragment Count value." hexmask.long 0x0 0.--31. 1. "PAEC,Rx Packet Assembly Error Counter This field indicates the number of MAC frames with reassembly errors on the Receiver due to mismatch in the Fragment Count value. Exists when any one of the RX/TX MMC counters are enabled during FPE Enabled.." line.long 0x4 "MMC_RX_PACKET_SMD_ERR_CNTR,This register provides the number of received MAC frames rejected due to unknown SMD value and MAC frame fragments rejected due to arriving with an SMD-C when there was no preceding preempted frame." hexmask.long 0x4 0.--31. 1. "PSEC,Rx Packet SMD Error Counter This field indicates the number of MAC frames rejected due to unknown SMD value and MAC frame fragments rejected due to arriving with an SMD-C when there was no preceding preempted frame. Exists when at least one of the.." line.long 0x8 "MMC_RX_PACKET_ASSEMBLY_OK_CNTR,This register provides the number of MAC frames that were successfully reassembled and delivered to MAC." hexmask.long 0x8 0.--31. 1. "PAOC,Rx Packet Assembly OK Counter This field indicates the number of MAC frames that were successfully reassembled and delivered to MAC. Exists when at least one of the RX/TX MMC counters are enabled during FPE Enabled configuration." line.long 0xC "MMC_RX_FPE_FRAGMENT_CNTR,This register provides the number of additional mPackets received due to preemption." hexmask.long 0xC 0.--31. 1. "FFC,Rx FPE Fragment Counter This field indicates the number of additional mPackets received due to preemption Exists when at least one of the RX/TX MMC counters are enabled during FPE Enabled configuration." repeat 4. (list 0x0 0x1 0x2 0x3 )(list 0x0 0x30 0x60 0x90 ) group.long ($2+0x900)++0x3 line.long 0x0 "MAC_L3_L4_CONTROL$1,The Layer 3 and Layer 4 Control register controls the operations of filter 0 of Layer 3 and Layer 4." rbitfld.long 0x0 29.--31. "RESERVED_31_29,Reserved." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 28. "DMCHEN0,DMA Channel Select Enable When set this bit enables the selection of the DMA channel number for the packet that is passed by this L3_L4 filter. The DMA channel is indicated by the DMCHN bits. When this bit is reset the DMA channel is not.." "DMA Channel Select is disabled,DMA Channel Select is enabled" newline rbitfld.long 0x0 27. "RESERVED_27_Y,Reserved." "0,1" newline bitfld.long 0x0 24.--26. "DMCHN0,DMA Channel Number When DMCHEN is set high this field selects the DMA Channel number to which the packet passed by this filter is routed. The width of this field depends on the number of the DMA channels present in your configuration." "0,1,2,3,4,5,6,7" newline rbitfld.long 0x0 22.--23. "RESERVED_23_22,Reserved." "0,1,2,3" newline bitfld.long 0x0 21. "L4DPIM0,Layer 4 Destination Port Inverse Match Enable When this bit is set the Layer 4 Destination Port number field is enabled for inverse matching. When this bit is reset the Layer 4 Destination Port number field is enabled for perfect matching. This.." "Layer 4 Destination Port Inverse Match is disabled,Layer 4 Destination Port Inverse Match is enabled" newline bitfld.long 0x0 20. "L4DPM0,Layer 4 Destination Port Match Enable When this bit is set the Layer 4 Destination Port number field is enabled for matching. When this bit is reset the MAC ignores the Layer 4 Destination Port number field for matching. 0x0: Layer 4 Destination.." "Layer 4 Destination Port Match is disabled,Layer 4 Destination Port Match is enabled" newline bitfld.long 0x0 19. "L4SPIM0,Layer 4 Source Port Inverse Match Enable When this bit is set the Layer 4 Source Port number field is enabled for inverse matching. When this bit is reset the Layer 4 Source Port number field is enabled for perfect matching. This bit is valid.." "Layer 4 Source Port Inverse Match is disabled,Layer 4 Source Port Inverse Match is enabled" newline bitfld.long 0x0 18. "L4SPM0,Layer 4 Source Port Match Enable When this bit is set the Layer 4 Source Port number field is enabled for matching. When this bit is reset the MAC ignores the Layer 4 Source Port number field for matching. 0x0: Layer 4 Source Port Match is.." "Layer 4 Source Port Match is disabled,Layer 4 Source Port Match is enabled" newline rbitfld.long 0x0 17. "RESERVED_17,Reserved." "0,1" newline bitfld.long 0x0 16. "L4PEN0,Layer 4 Protocol Enable When this bit is set the Source and Destination Port number fields of UDP packets are used for matching. When this bit is reset the Source and Destination Port number fields of TCP packets are used for matching. The Layer.." "Layer 4 Protocol is disabled,Layer 4 Protocol is enabled" newline hexmask.long.byte 0x0 11.--15. 1. "L3HDBM0,Layer 3 IP DA Higher Bits Match IPv4 Packets: This field contains the number of higher bits of IP Destination Address that are matched in the IPv4 packets. The following list describes the values of this field: - 0: No bits are masked. - 1:.." newline hexmask.long.byte 0x0 6.--10. 1. "L3HSBM0,Layer 3 IP SA Higher Bits Match IPv4 Packets: This field contains the number of lower bits of IP Source Address that are masked for matching in the IPv4 packets. The following list describes the values of this field: - 0: No bits are masked. - 1:.." newline bitfld.long 0x0 5. "L3DAIM0,Layer 3 IP DA Inverse Match Enable When this bit is set the Layer 3 IP Destination Address field is enabled for inverse matching. When this bit is reset the Layer 3 IP Destination Address field is enabled for perfect matching. This bit is valid.." "Layer 3 IP DA Inverse Match is disabled,Layer 3 IP DA Inverse Match is enabled" newline bitfld.long 0x0 4. "L3DAM0,Layer 3 IP DA Match Enable When this bit is set the Layer 3 IP Destination Address field is enabled for matching. When this bit is reset the MAC ignores the Layer 3 IP Destination Address field for matching. Note: When the L3PEN0 bit is set you.." "Layer 3 IP DA Match is disabled,Layer 3 IP DA Match is enabled" newline bitfld.long 0x0 3. "L3SAIM0,Layer 3 IP SA Inverse Match Enable When this bit is set the Layer 3 IP Source Address field is enabled for inverse matching. When this bit reset the Layer 3 IP Source Address field is enabled for perfect matching. This bit is valid and.." "Layer 3 IP SA Inverse Match is disabled,Layer 3 IP SA Inverse Match is enabled" newline bitfld.long 0x0 2. "L3SAM0,Layer 3 IP SA Match Enable When this bit is set the Layer 3 IP Source Address field is enabled for matching. When this bit is reset the MAC ignores the Layer 3 IP Source Address field for matching. Note: When the L3PEN0 bit is set you should.." "Layer 3 IP SA Match is disabled,Layer 3 IP SA Match is enabled" newline rbitfld.long 0x0 1. "RESERVED_1,Reserved." "0,1" newline bitfld.long 0x0 0. "L3PEN0,Layer 3 Protocol Enable When this bit is set the Layer 3 IP Source or Destination Address matching is enabled for IPv6 packets. When this bit is reset the Layer 3 IP Source or Destination Address matching is enabled for IPv4 packets. The Layer 3.." "Layer 3 Protocol is disabled,Layer 3 Protocol is enabled" repeat.end repeat 4. (list 0x0 0x1 0x2 0x3 )(list 0x0 0x30 0x60 0x90 ) group.long ($2+0x904)++0x3 line.long 0x0 "MAC_LAYER4_ADDRESS$1,The MAC_Layer4_Address(#i). MAC_L3_L4_Control(#i). MAC_Layer3_Addr0_Reg(#i). MAC_Layer3_Addr1_Reg(#i). MAC_Layer3_Addr2_Reg(#i) and MAC_Layer3_Addr3_Reg(#i) registers are reserved (RO with default value) if Enable Layer 3 and Layer 4.." hexmask.long.word 0x0 16.--31. 1. "L4DP0,Layer 4 Destination Port Number Field When the L4PEN0 bit is reset and the L4DPM0 bit is set in the MAC_L3_L4_Control0 register this field contains the value to be matched with the TCP Destination Port Number field in the IPv4 or IPv6 packets." newline hexmask.long.word 0x0 0.--15. 1. "L4SP0,Layer 4 Source Port Number Field When the L4PEN0 bit is reset and the L4SPM0 bit is set in the MAC_L3_L4_Control0 register this field contains the value to be matched with the TCP Source Port Number field in the IPv4 or IPv6 packets. When the.." repeat.end repeat 4. (list 0x0 0x1 0x2 0x3 )(list 0x0 0x30 0x60 0x90 ) group.long ($2+0x910)++0x3 line.long 0x0 "MAC_LAYER3_ADDR0_REG$1,For IPv4 packets. the Layer 3 Address 0 Register 0 register contains the 32-bit IP Source Address field. For IPv6 packets. it contains Bits[31:0] of the 128-bit IP Source Address or Destination Address field." hexmask.long 0x0 0.--31. 1. "L3A00,Layer 3 Address 0 Field When the L3PEN0 and L3SAM0 bits are set in the MAC_L3_L4_Control0 register this field contains the value to be matched with Bits[31:0] of the IP Source Address field in the IPv6 packets. When the L3PEN0 and L3DAM0 bits are.." repeat.end repeat 4. (list 0x0 0x1 0x2 0x3 )(list 0x0 0x30 0x60 0x90 ) group.long ($2+0x914)++0x3 line.long 0x0 "MAC_LAYER3_ADDR1_REG$1,For IPv4 packets. the Layer 3 Address 1 Register 0 register contains the 32-bit IP Destination Address field. For IPv6 packets. it contains Bits[63:32] of the 128-bit IP Source Address or Destination Address field." hexmask.long 0x0 0.--31. 1. "L3A10,Layer 3 Address 1 Field When the L3PEN0 and L3SAM0 bits are set in the MAC_L3_L4_Control0 register this field contains the value to be matched with Bits[63:32] of the IP Source Address field in the IPv6 packets. When the L3PEN0 and L3DAM0 bits are.." repeat.end repeat 4. (list 0x0 0x1 0x2 0x3 )(list 0x0 0x30 0x60 0x90 ) group.long ($2+0x918)++0x3 line.long 0x0 "MAC_LAYER3_ADDR2_REG$1,The Layer 3 Address 2 Register 0 register is reserved for IPv4 packets. For IPv6 packets. it contains Bits[95:64] of 128-bit IP Source Address or Destination Address field." hexmask.long 0x0 0.--31. 1. "L3A20,Layer 3 Address 2 Field When the L3PEN0 and L3SAM0 bits are set in the MAC_L3_L4_Control0 register this field contains the value to be matched with Bits[95:64] of the IP Source Address field in the IPv6 packets. When the L3PEN0 and L3DAM0 bits are.." repeat.end repeat 4. (list 0x0 0x1 0x2 0x3 )(list 0x0 0x30 0x60 0x90 ) group.long ($2+0x91C)++0x3 line.long 0x0 "MAC_LAYER3_ADDR3_REG$1,The Layer 3 Address 3 Register 0 register is reserved for IPv4 packets. For IPv6 packets. it contains Bits[127:96] of 128-bit IP Source Address or Destination Address field." hexmask.long 0x0 0.--31. 1. "L3A30,Layer 3 Address 3 Field When the L3PEN0 and L3SAM0 bits are set in the MAC_L3_L4_Control0 register this field contains the value to be matched with Bits[127:96] of the IP Source Address field in the IPv6 packets. When the L3PEN0 and L3DAM0 bits.." repeat.end group.long 0xB00++0x7 line.long 0x0 "MAC_TIMESTAMP_CONTROL,This register controls the operation of the System Time generator and processing of PTP packets for timestamping in the Receiver." rbitfld.long 0x0 29.--31. "RESERVED_31_29,Reserved." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 28. "AV8021ASMEN,AV 802.1AS Mode Enable When this bit is set the MAC processes only untagged PTP over Ethernet packets for providing PTP status and capturing timestamp snapshots that is IEEE 802.1AS mode of operation. When PTP offload feature is enabled.." "AV 802,AV 802" newline rbitfld.long 0x0 25.--27. "RESERVED_27_25,Reserved." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 24. "TXTSSTSM,Transmit Timestamp Status Mode When this bit is set the MAC overwrites the earlier transmit timestamp status even if it is not read by the software. The MAC indicates this by setting the TXTSSMIS bit of the MAC_Tx_Timestamp_Status_Nanoseconds.." "Transmit Timestamp Status Mode is disabled,Transmit Timestamp Status Mode is enabled" newline rbitfld.long 0x0 21.--23. "RESERVED_23_21,Reserved." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 20. "ESTI,External System Time Input When this bit is set the MAC uses the external 64-bit reference System Time input for the following: - To take the timestamp provided as status - To insert the timestamp in transmit PTP packets when One-step Timestamp or.." "External System Time Input is disabled,External System Time Input is enabled" newline bitfld.long 0x0 19. "CSC,Enable checksum correction during OST for PTP over UDP/IPv4 packets When this bit is set the last two bytes of PTP message sent over UDP/IPv4 is updated to keep the UDP checksum correct for changes made to origin timestamp and/or correction field.." "checksum correction during OST for PTP over..,checksum correction during OST for PTP over.." newline bitfld.long 0x0 18. "TSENMACADDR,Enable MAC Address for PTP Packet Filtering When this bit is set the DA MAC address (that matches any MAC Address register) is used to filter the PTP packets when PTP is directly sent over Ethernet. When this bit is set received PTP packets.." "MAC Address for PTP Packet Filtering is disabled,MAC Address for PTP Packet Filtering is enabled" newline bitfld.long 0x0 16.--17. "SNAPTYPSEL,Select PTP packets for Taking Snapshots These bits along with Bits 15 and 14 decide the set of PTP packet types for which snapshot needs to be taken. The encoding is given in Timestamp Snapshot Dependency on Register Bits Table." "0,1,2,3" newline bitfld.long 0x0 15. "TSMSTRENA,Enable Snapshot for Messages Relevant to Master When this bit is set the snapshot is taken only for the messages that are relevant to the master node. Otherwise the snapshot is taken for the messages relevant to the slave node. 0x0: Snapshot.." "Snapshot for Messages Relevant to Master is..,Snapshot for Messages Relevant to Master is.." newline bitfld.long 0x0 14. "TSEVNTENA,Enable Timestamp Snapshot for Event Messages When this bit is set the timestamp snapshot is taken only for event messages (SYNC Delay_Req Pdelay_Req or Pdelay_Resp). When this bit is reset the snapshot is taken for all messages except.." "Timestamp Snapshot for Event Messages is disabled,Timestamp Snapshot for Event Messages is enabled" newline bitfld.long 0x0 13. "TSIPV4ENA,Enable Processing of PTP Packets Sent over IPv4-UDP When this bit is set the MAC receiver processes the PTP packets encapsulated in IPv4-UDP packets. When this bit is reset the MAC ignores the PTP transported over IPv4-UDP packets. This bit.." "Processing of PTP Packets Sent over IPv4-UDP is..,Processing of PTP Packets Sent over IPv4-UDP is.." newline bitfld.long 0x0 12. "TSIPV6ENA,Enable Processing of PTP Packets Sent over IPv6-UDP When this bit is set the MAC receiver processes the PTP packets encapsulated in IPv6-UDP packets. When this bit is clear the MAC ignores the PTP transported over IPv6-UDP packets. 0x0:.." "Processing of PTP Packets Sent over IPv6-UDP is..,Processing of PTP Packets Sent over IPv6-UDP is.." newline bitfld.long 0x0 11. "TSIPENA,Enable Processing of PTP over Ethernet Packets When this bit is set the MAC receiver processes the PTP packets encapsulated directly in the Ethernet packets. When this bit is reset the MAC ignores the PTP over Ethernet packets. 0x0: Processing.." "Processing of PTP over Ethernet Packets is..,Processing of PTP over Ethernet Packets is enabled" newline bitfld.long 0x0 10. "TSVER2ENA,Enable PTP Packet Processing for Version 2 Format When this bit is set the IEEE 1588 version 2 format is used to process the PTP packets. When this bit is reset the IEEE 1588 version 1 format is used to process the PTP packets. The IEEE 1588.." "PTP Packet Processing for Version 2 Format is..,PTP Packet Processing for Version 2 Format is.." newline bitfld.long 0x0 9. "TSCTRLSSR,Timestamp Digital or Binary Rollover Control When this bit is set the Timestamp Low register rolls over after 0x3B9A_C9FF value (that is 1 nanosecond accuracy) and increments the timestamp (High) seconds. When this bit is reset the rollover.." "Timestamp Digital or Binary Rollover Control is..,Timestamp Digital or Binary Rollover Control is.." newline bitfld.long 0x0 8. "TSENALL,Enable Timestamp for All Packets When this bit is set the timestamp snapshot is enabled for all packets received by the MAC. 0x0: Timestamp for All Packets disabled 0x1: Timestamp for All Packets enabled" "Timestamp for All Packets disabled,Timestamp for All Packets enabled" newline rbitfld.long 0x0 7. "RESERVED_7,Reserved." "0,1" newline bitfld.long 0x0 6. "PTGE,Presentation Time Generation Enable When this bit is set the Presentation Time generation will be enabled. 0x0: Presentation Time Generation is disabled 0x1: Presentation Time Generation is enabled" "Presentation Time Generation is disabled,Presentation Time Generation is enabled" newline bitfld.long 0x0 5. "TSADDREG,Update Addend Register When this bit is set the content of the Timestamp Addend register is updated in the PTP block for fine correction. This bit is cleared when the update is complete. This bit should be zero before it is set. Access.." "Addend Register is not updated,Addend Register is updated" newline rbitfld.long 0x0 4. "RESERVED_TSTRIG,Reserved." "0,1" newline bitfld.long 0x0 3. "TSUPDT,Update Timestamp When this bit is set the system time is updated (added or subtracted) with the value specified in MAC_System_Time_Seconds_Update and MAC_System_Time_Nanoseconds_Update registers. This bit should be zero before updating it. This.." "Timestamp is not updated,Timestamp is updated" newline bitfld.long 0x0 2. "TSINIT,Initialize Timestamp When this bit is set the system time is initialized (overwritten) with the value specified in the MAC_System_Time_Seconds_Update and MAC_System_Time_Nanoseconds_Update registers. This bit should be zero before it is updated." "Timestamp is not initialized,Timestamp is initialized" newline bitfld.long 0x0 1. "TSCFUPDT,Fine or Coarse Timestamp Update When this bit is set the Fine method is used to update system timestamp. When this bit is reset Coarse method is used to update the system timestamp. 0x0: Coarse method is used to update system timestamp 0x1:.." "Coarse method is used to update system timestamp,Fine method is used to update system timestamp" line.long 0x4 "MAC_SUB_SECOND_INCREMENT,This register specifies the value to be added to the internal system time register every cycle of clk_ptp_ref_i clock." hexmask.long.byte 0x4 24.--31. 1. "RESERVED_31_24,Reserved." newline hexmask.long.byte 0x4 16.--23. 1. "SSINC,Sub-second Increment Value The value programmed in this field is accumulated every clock cycle (of clk_ptp_i) with the contents of the sub-second register. For example when the PTP clock is 50 MHz (period is 20 ns) you should program 20 (0x14).." newline hexmask.long.byte 0x4 8.--15. 1. "SNSINC,Sub-nanosecond Increment Value This field contains the sub-nanosecond increment value represented in nanoseconds multiplied by 2^8. This value is accumulated with the sub-nanoseconds field of the subsecond register. For example when TSCTRLSSR.." newline hexmask.long.byte 0x4 0.--7. 1. "RESERVED_7_0,Reserved." rgroup.long 0xB08++0x7 line.long 0x0 "MAC_SYSTEM_TIME_SECONDS,The System Time Seconds register. along with System Time Nanoseconds register. indicates the current value of the system time maintained by the MAC. Though it is updated on a continuous basis. there is some delay from the actual.." hexmask.long 0x0 0.--31. 1. "TSS,Timestamp Second The value in this field indicates the current value in seconds of the System Time maintained by the MAC." line.long 0x4 "MAC_SYSTEM_TIME_NANOSECONDS,The System Time Nanoseconds register. along with System Time Seconds register. indicates the current value of the system time maintained by the MAC." bitfld.long 0x4 31. "RESERVED_31,Reserved." "0,1" newline hexmask.long 0x4 0.--30. 1. "TSSS,Timestamp Sub Seconds The value in this field has the sub-second representation of time with an accuracy of 0.46 ns. When Bit 9 is set in MAC_Timestamp_Control each bit represents 1 ns. The maximum value is 0x3B9A_C9FF after which it rolls-over to.." group.long 0xB10++0xF line.long 0x0 "MAC_SYSTEM_TIME_SECONDS_UPDATE,The System Time Seconds Update register. along with the System Time Nanoseconds Update register. initializes or updates the system time maintained by the MAC. You must write both registers before setting the TSINIT or.." hexmask.long 0x0 0.--31. 1. "TSS,Timestamp Seconds The value in this field is the seconds part of the update. When ADDSUB is reset this field must be programmed with the seconds part of the update value. When ADDSUB is set this field must be programmed with the complement of the.." line.long 0x4 "MAC_SYSTEM_TIME_NANOSECONDS_UPDATE,MAC System Time Nanoseconds Update register." bitfld.long 0x4 31. "ADDSUB,Add or Subtract Time When this bit is set the time value is subtracted with the contents of the update register. When this bit is reset the time value is added with the contents of the update register. 0x0: Add time 0x1: Subtract time" "Add time,Subtract time" newline hexmask.long 0x4 0.--30. 1. "TSSS,Timestamp Sub Seconds The value in this field is the sub-seconds part of the update. When ADDSUB is reset this field must be programmed with the sub-seconds part of the update value with an accuracy based on the TSCTRLSSR bit of the.." line.long 0x8 "MAC_TIMESTAMP_ADDEND,Timestamp Addend register. This register value is used only when the system time is configured for Fine Update mode (TSCFUPDT bit in the MAC_Timestamp_Control register). The content of this register is added to a 32-bit accumulator.." hexmask.long 0x8 0.--31. 1. "TSAR,Timestamp Addend Register This field indicates the 32-bit time value to be added to the Accumulator register to achieve time synchronization." line.long 0xC "MAC_SYSTEM_TIME_HIGHER_WORD_SECONDS,System Time - Higher Word Seconds register." hexmask.long.word 0xC 16.--31. 1. "RESERVED_31_16,Reserved." newline hexmask.long.word 0xC 0.--15. 1. "TSHWR,Timestamp Higher Word Register This field contains the most-significant 16-bits of timestamp seconds value. This register is optional. You can add this register by selecting the Add IEEE 1588 Higher Word Register option. This register is directly.." rgroup.long 0xB20++0x3 line.long 0x0 "MAC_TIMESTAMP_STATUS,Timestamp Status register. All bits except Bits[27:25] gets cleared when the application reads this register." bitfld.long 0x0 30.--31. "RESERVED_31_30,Reserved." "0,1,2,3" newline hexmask.long.byte 0x0 25.--29. 1. "ATSNS,Number of Auxiliary Timestamp Snapshots This field indicates the number of Snapshots available in the FIFO. A value equal to the selected depth of FIFO (4 8 or 16) indicates that the Auxiliary Snapshot FIFO is full. These bits are cleared (to.." newline bitfld.long 0x0 24. "ATSSTM,Auxiliary Timestamp Snapshot Trigger Missed This bit is set when the Auxiliary timestamp snapshot FIFO is full and external trigger was set. This indicates that the latest snapshot is not stored in the FIFO. This bit is valid only if the Add IEEE.." "Auxiliary Timestamp Snapshot Trigger Missed..,Auxiliary Timestamp Snapshot Trigger Missed.." newline hexmask.long.byte 0x0 20.--23. 1. "RESERVED_23_20,Reserved." newline hexmask.long.byte 0x0 16.--19. 1. "ATSSTN,Auxiliary Timestamp Snapshot Trigger Identifier These bits identify the Auxiliary trigger inputs for which the timestamp available in the Auxiliary Snapshot Register is applicable. When more than one bit is set at the same time it means that.." newline bitfld.long 0x0 15. "TXTSSIS,Tx Timestamp Status Interrupt Status In non-EQOS_CORE configurations when drop transmit status is enabled in MTL this bit is set when the captured transmit timestamp is updated in the MAC_Tx_Timestamp_Status_Nanoseconds and.." "Tx Timestamp Status Interrupt status not detected,Tx Timestamp Status Interrupt status detected" newline hexmask.long.byte 0x0 10.--14. 1. "RESERVED_14_10,Reserved." newline bitfld.long 0x0 9. "TSTRGTERR3,Timestamp Target Time Error This bit is set when the latest target time programmed in the MAC_PPS3_Target_Time_Seconds and MAC_PPS3_Target_Time_Nanoseconds registers elapses. This bit is cleared when the application reads this bit. Access.." "Timestamp Target Time Error status not detected,Timestamp Target Time Error status detected" newline bitfld.long 0x0 8. "TSTARGT3,Timestamp Target Time Reached for Target Time PPS3 When this bit is set it indicates that the value of system time is greater than or equal to the value specified in the MAC_PPS3_Target_Time_Seconds and MAC_PPS3_Target_Time_Nanoseconds.." "Timestamp Target Time Reached for Target Time..,Timestamp Target Time Reached for Target Time.." newline bitfld.long 0x0 7. "TSTRGTERR2,Timestamp Target Time Error This bit is set when the latest target time programmed in the MAC_PPS2_Target_Time_Seconds and MAC_PPS2_Target_Time_Nanoseconds registers elapses. This bit is cleared when the application reads this bit. Access.." "Timestamp Target Time Error status not detected,Timestamp Target Time Error status detected" newline bitfld.long 0x0 6. "TSTARGT2,Timestamp Target Time Reached for Target Time PPS2 When set this bit indicates that the value of system time is greater than or equal to the value specified in the MAC_PPS2_Target_Time_Seconds and MAC_PPS2_Target_Time_Nanoseconds registers." "Timestamp Target Time Reached for Target Time..,Timestamp Target Time Reached for Target Time.." newline bitfld.long 0x0 5. "TSTRGTERR1,Timestamp Target Time Error This bit is set when the latest target time programmed in the MAC_PPS1_Target_Time_Seconds and MAC_PPS1_Target_Time_Nanoseconds registers elapses. This bit is cleared when the application reads this bit. Access.." "Timestamp Target Time Error status not detected,Timestamp Target Time Error status detected" newline bitfld.long 0x0 4. "TSTARGT1,Timestamp Target Time Reached for Target Time PPS1 When set this bit indicates that the value of system time is greater than or equal to the value specified in the MAC_PPS1_Target_Time_Seconds and MAC_PPS1_Target_Time_Nanoseconds registers." "Timestamp Target Time Reached for Target Time..,Timestamp Target Time Reached for Target Time.." newline bitfld.long 0x0 3. "TSTRGTERR0,Timestamp Target Time Error This bit is set when the latest target time programmed in the MAC_PPS0_Target_Time_Seconds and MAC_PPS0_Target_Time_Nanoseconds registers elapses. This bit is cleared when the application reads this bit. Access.." "Timestamp Target Time Error status not detected,Timestamp Target Time Error status detected" newline bitfld.long 0x0 2. "AUXTSTRIG,Auxiliary Timestamp Trigger Snapshot This bit is set high when the auxiliary snapshot is written to the FIFO. This bit is valid only if the Add IEEE 1588 Auxiliary Snapshot option is selected. Access restriction applies. Clears on read (or this.." "Auxiliary Timestamp Trigger Snapshot status not..,Auxiliary Timestamp Trigger Snapshot status.." newline bitfld.long 0x0 1. "TSTARGT0,Timestamp Target Time Reached When set this bit indicates that the value of system time is greater than or equal to the value specified in the MAC_PPS0_Target_Time_Seconds and MAC_PPS0_Target_Time_Nanoseconds registers. Access restriction.." "Timestamp Target Time Reached status not detected,Timestamp Target Time Reached status detected" newline bitfld.long 0x0 0. "TSSOVF,Timestamp Seconds Overflow When this bit is set it indicates that the seconds value of the timestamp (when supporting version 2 format) has overflowed beyond 32'hFFFF_FFFF. Access restriction applies. Clears on read (or this bit is written to 1.." "Timestamp Seconds Overflow status not detected,Timestamp Seconds Overflow status detected" rgroup.long 0xB30++0x7 line.long 0x0 "MAC_TX_TIMESTAMP_STATUS_NANOSECONDS,This register contains the nanosecond part of timestamp captured for Transmit packets when Tx status is disabled. The MAC_Tx_Timestamp_Status_Nanoseconds register. along with MAC_Tx_Timestamp_Status_Seconds. gives the.." bitfld.long 0x0 31. "TXTSSMIS,Transmit Timestamp Status Missed When this bit is set it indicates one of the following: - The timestamp of the current packet is ignored if TXTSSTSM bit of the MAC_Timestamp_Control register is reset - The timestamp of the previous packet is.." "Transmit Timestamp Status Missed status not..,Transmit Timestamp Status Missed status detected" newline hexmask.long 0x0 0.--30. 1. "TXTSSLO,Transmit Timestamp Status Low This field contains the 31 bits of the Nanoseconds field of the Transmit packet's captured timestamp." line.long 0x4 "MAC_TX_TIMESTAMP_STATUS_SECONDS,The register contains the higher 32 bits of the timestamp (in seconds) captured when a PTP packet is transmitted." hexmask.long 0x4 0.--31. 1. "TXTSSHI,Transmit Timestamp Status High This field contains the lower 32 bits of the Seconds field of Transmit packet's captured timestamp." group.long 0xB40++0x3 line.long 0x0 "MAC_AUXILIARY_CONTROL,The Auxiliary Timestamp Control register controls the Auxiliary Timestamp snapshot." hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED_31_8,Reserved." newline bitfld.long 0x0 7. "ATSEN3,Auxiliary Snapshot 3 Enable This bit controls the capturing of Auxiliary Snapshot Trigger 3. When this bit is set the auxiliary snapshot of the event on ptp_aux_trig_i[3] input is enabled. When this bit is reset the events on this input are.." "Auxiliary Snapshot i is disabled,Auxiliary Snapshot i is enabled" newline bitfld.long 0x0 6. "ATSEN2,Auxiliary Snapshot 2 Enable This bit controls the capturing of Auxiliary Snapshot Trigger 2. When this bit is set the auxiliary snapshot of the event on ptp_aux_trig_i[2] input is enabled. When this bit is reset the events on this input are.." "Auxiliary Snapshot i is disabled,Auxiliary Snapshot i is enabled" newline bitfld.long 0x0 5. "ATSEN1,Auxiliary Snapshot 1 Enable This bit controls the capturing of Auxiliary Snapshot Trigger 1. When this bit is set the auxiliary snapshot of the event on ptp_aux_trig_i[1] input is enabled. When this bit is reset the events on this input are.." "Auxiliary Snapshot i is disabled,Auxiliary Snapshot i is enabled" newline bitfld.long 0x0 4. "ATSEN0,Auxiliary Snapshot 0 Enable This bit controls the capturing of Auxiliary Snapshot Trigger 0. When this bit is set the auxiliary snapshot of the event on ptp_aux_trig_i[0] input is enabled. When this bit is reset the events on this input are.." "Auxiliary Snapshot i is disabled,Auxiliary Snapshot i is enabled" newline rbitfld.long 0x0 1.--3. "RESERVED_3_1,Reserved." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 0. "ATSFC,Auxiliary Snapshot FIFO Clear When set this bit resets the pointers of the Auxiliary Snapshot FIFO. This bit is cleared when the pointers are reset and the FIFO is empty. When this bit is high the auxiliary snapshots are stored in the FIFO." "Auxiliary Snapshot FIFO Clear is disabled,Auxiliary Snapshot FIFO Clear is enabled" rgroup.long 0xB48++0x7 line.long 0x0 "MAC_AUXILIARY_TIMESTAMP_NANOSECONDS,The Auxiliary Timestamp Nanoseconds register. along with MAC_Auxiliary_Timestamp_Seconds. gives the 64-bit timestamp stored as auxiliary snapshot. These two registers form the read port of a 64-bit wide FIFO with a.." bitfld.long 0x0 31. "RESERVED_31,Reserved." "0,1" newline hexmask.long 0x0 0.--30. 1. "AUXTSLO,Auxiliary Timestamp Contains the lower 31 bits (nanoseconds field) of the auxiliary timestamp." line.long 0x4 "MAC_AUXILIARY_TIMESTAMP_SECONDS,The Auxiliary Timestamp - Seconds register contains the lower 32 bits of the Seconds field of the auxiliary timestamp register." hexmask.long 0x4 0.--31. 1. "AUXTSHI,Auxiliary Timestamp Contains the lower 32 bits of the Seconds field of the auxiliary timestamp." group.long 0xB50++0x17 line.long 0x0 "MAC_TIMESTAMP_INGRESS_ASYM_CORR,The MAC Timestamp Ingress Asymmetry Correction register contains the Ingress Asymmetry Correction value to be used while updating correction field in PDelay_Resp PTP messages." hexmask.long 0x0 0.--31. 1. "OSTIAC,One-Step Timestamp Ingress Asymmetry Correction This field contains the ingress path asymmetry value to be added to correctionField of Pdelay_Resp PTP packet. The programmed value should be in units of nanoseconds and multiplied by 2^16. For.." line.long 0x4 "MAC_TIMESTAMP_EGRESS_ASYM_CORR,The MAC Timestamp Egress Asymmetry Correction register contains the Egress Asymmetry Correction value to be used while updating the correction field in PDelay_Req PTP messages." hexmask.long 0x4 0.--31. 1. "OSTEAC,One-Step Timestamp Egress Asymmetry Correction This field contains the egress path asymmetry value to be subtracted from correctionField of Pdelay_Resp PTP packet. The programmed value must be the negated value in units of nanoseconds multiplied.." line.long 0x8 "MAC_TIMESTAMP_INGRESS_CORR_NANOSECOND,This register contains the correction value in nanoseconds to be used with the captured timestamp value in the ingress path." hexmask.long 0x8 0.--31. 1. "TSIC,Timestamp Ingress Correction This field contains the ingress path correction value as defined by the Ingress Correction expression." line.long 0xC "MAC_TIMESTAMP_EGRESS_CORR_NANOSECOND,This register contains the correction value in nanoseconds to be used with the captured timestamp value in the egress path." hexmask.long 0xC 0.--31. 1. "TSEC,Timestamp Egress Correction This field contains the nanoseconds part of the egress path correction value as defined by the Egress Correction expression." line.long 0x10 "MAC_TIMESTAMP_INGRESS_CORR_SUBNANOSEC,This register contains the sub-nanosecond part of the correction value to be used with the captured timestamp value. for ingress direction." hexmask.long.word 0x10 16.--31. 1. "RESERVED_31_16,Reserved." newline hexmask.long.byte 0x10 8.--15. 1. "TSICSNS,Timestamp Ingress Correction sub-nanoseconds This field contains the sub-nanoseconds part of the ingress path correction value as defined by the 'Ingress Correction' expression." newline hexmask.long.byte 0x10 0.--7. 1. "RESERVED_7_0,Reserved." line.long 0x14 "MAC_TIMESTAMP_EGRESS_CORR_SUBNANOSEC,This register contains the sub-nanosecond part of the correction value to be used with the captured timestamp value. for egress direction." hexmask.long.word 0x14 16.--31. 1. "RESERVED_31_16,Reserved." newline hexmask.long.byte 0x14 8.--15. 1. "TSECSNS,Timestamp Egress Correction sub-nanoseconds This field contains the sub-nanoseconds part of the egress path correction value as defined by the 'Egress Correction' expression." newline hexmask.long.byte 0x14 0.--7. 1. "RESERVED_7_0,Reserved." rgroup.long 0xB68++0x7 line.long 0x0 "MAC_TIMESTAMP_INGRESS_LATENCY,This register holds the Ingress MAC latency." hexmask.long.byte 0x0 28.--31. 1. "RESERVED_31_28,Reserved." newline hexmask.long.word 0x0 16.--27. 1. "ITLNS,Ingress Timestamp Latency in sub-nanoseconds This register holds the average latency in sub-nanoseconds between the input ports (phy_rxd_i) of MAC and the actual point (GMII/MII) where the ingress timestamp is taken. Ingress correction value is.." newline hexmask.long.byte 0x0 8.--15. 1. "ITLSNS,Ingress Timestamp Latency in nanoseconds This register holds the average latency in nanoseconds between the input ports (phy_rxd_i) of MAC and the actual point (GMII/MII) where the ingress timestamp is taken. Ingress correction value is computed.." newline hexmask.long.byte 0x0 0.--7. 1. "RESERVED_7_0,Reserved." line.long 0x4 "MAC_TIMESTAMP_EGRESS_LATENCY,This register holds the Egress MAC latency." hexmask.long.byte 0x4 28.--31. 1. "RESERVED_31_28,Reserved." newline hexmask.long.word 0x4 16.--27. 1. "ETLNS,Egress Timestamp Latency in nanoseconds This register holds the average latency in nanoseconds between the actual point (GMII/MII) where the egress timestamp is taken and the output ports (phy_txd_o) of the MAC. Ingress correction value is.." newline hexmask.long.byte 0x4 8.--15. 1. "ETLSNS,Egress Timestamp Latency in sub-nanoseconds This register holds the average latency in sub-nanoseconds between the actual point (GMII/MII) where the egress timestamp is taken and the output ports (phy_txd_o) of the MAC. Ingress correction value.." newline hexmask.long.byte 0x4 0.--7. 1. "RESERVED_7_0,Reserved." group.long 0xB70++0x3 line.long 0x0 "MAC_PPS_CONTROL,PPS Control register. Bits[30:24] of this register are valid only when four Flexible PPS outputs are selected. Bits[22:16] are valid only when three or more Flexible PPS outputs are selected. Bits[14:8] are valid only when two or more.." bitfld.long 0x0 31. "MCGREN3,MCGR Mode Enable for PPS3 Output This field enables the 3rd PPS instance to operate in PPS or MCGR mode. When set it operates in MCGR mode and on reset it operates in PPS mode." "0,1" newline bitfld.long 0x0 29.--30. "TRGTMODSEL3,Target Time Register Mode for PPS3 Output This field indicates the Target Time registers (MAC_PPS3_Target_Time_Seconds and MAC_PPS3_Target_Time_Nanoseconds) mode for PPS3 output signal. 0x2: Target Time registers are programmed for generating.." "Target Time registers are programmed only for..,Reserved,Target Time registers are programmed for..,Target Time registers are programmed only for.." newline rbitfld.long 0x0 28. "RESERVED_28,Reserved." "0,1" newline hexmask.long.byte 0x0 24.--27. 1. "PPSCMD3,Flexible PPS3 Output Control This field controls the flexible PPS3 output (ptp_pps_o[3]) signal. This field is similar to the PPSCMD0[2:0] field. If MCGREN3 is set then PPSCMD3 indicated by these 4 bits [27:24] are taken as Presentation Time.." newline bitfld.long 0x0 23. "MCGREN2,MCGR Mode Enable for PPS2 Output This field enables the 2nd PPS instance to operate in PPS or MCGR mode. When set it operates in MCGR mode and on reset it operates in PPS mode. 0x0: 2nd PPS instance is disabled to operate in PPS or MCGR mode 0x1:.." "0,1" newline bitfld.long 0x0 21.--22. "TRGTMODSEL2,Target Time Register Mode for PPS2 Output This field indicates the Target Time registers (MAC_PPS2_Target_Time_Seconds and MAC_PPS2_Target_Time_Nanoseconds) mode for PPS2 output signal. 0x2: Target Time registers are programmed for generating.." "Target Time registers are programmed only for..,Reserved,Target Time registers are programmed for..,Target Time registers are programmed only for.." newline rbitfld.long 0x0 20. "RESERVED_20,Reserved." "0,1" newline hexmask.long.byte 0x0 16.--19. 1. "PPSCMD2,Flexible PPS2 Output Control This field controls the flexible PPS2 output (ptp_pps_o[2]) signal. This field is similar to the PPSCMD0 field. If MCGREN2 is set then PPSCMD2 indicated by these 4 bits [19:16] are taken as Presentation Time Control.." newline bitfld.long 0x0 15. "MCGREN1,MCGR Mode Enable for PPS1 Output This field enables the 1st PPS instance to operate in PPS or MCGR mode. When set it operates in MCGR mode and on reset it operates in PPS mode. 0x0: 1st PPS instance is disabled to operate in PPS or MCGR mode 0x1:.." "0,1" newline bitfld.long 0x0 13.--14. "TRGTMODSEL1,Target Time Register Mode for PPS1 Output This field indicates the Target Time registers (MAC_PPS1_Target_Time_Seconds and MAC_PPS1_Target_Time_Nanoseconds) mode for PPS1 output signal. 0x2: Target Time registers are programmed for generating.." "Target Time registers are programmed only for..,Reserved,Target Time registers are programmed for..,Target Time registers are programmed only for.." newline rbitfld.long 0x0 12. "RESERVED_12,Reserved." "0,1" newline hexmask.long.byte 0x0 8.--11. 1. "PPSCMD1,Flexible PPS1 Output Control This field controls the flexible PPS1 output (ptp_pps_o[1]) signal. This field is similar to the PPSCMD0 field. If MCGREN1 is set then PPSCMD1 indicated by these 4 bits [11:8] are taken as Presentation Time Control.." newline bitfld.long 0x0 7. "MCGREN0,MCGR Mode Enable for PPS0 Output This field enables the 0th PPS instance to operate in PPS or MCGR mode. When set it operates in MCGR mode and on reset it operates in PPS mode. 0x1: 0th PPS instance is enabled to operate in MCGR mode 0x0: 0th PPS.." "0,1" newline bitfld.long 0x0 5.--6. "TRGTMODSEL0,Target Time Register Mode for PPS0 Output This field indicates the Target Time registers (MAC_PPS0_Target_Time_Seconds and MAC_PPS0_Target_Time_Nanoseconds) mode for PPS0 output signal: 0x2: Target Time registers are programmed for generating.." "Target Time registers are programmed only for..,Reserved,Target Time registers are programmed for..,Target Time registers are programmed only for.." newline bitfld.long 0x0 4. "PPSEN0,Flexible PPS Output Mode Enable When this bit is set Bits[3:0] function as PPSCMD. When this bit is reset Bits[3:0] function as PPSCTRL (Fixed PPS mode). 0x0: Flexible PPS Output Mode is disabled 0x1: Flexible PPS Output Mode is enabled" "Flexible PPS Output Mode is disabled,Flexible PPS Output Mode is enabled" newline hexmask.long.byte 0x0 0.--3. 1. "PPSCTRL_PPSCMD,PPS Output Frequency Control This field controls the frequency of the PPS0 output (ptp_pps_o[0]) signal. The default value of PPSCTRL is 0000 and the PPS output is 1 pulse (of width clk_ptp_i) every second. For other values of PPSCTRL.." group.long 0xB80++0x53 line.long 0x0 "MAC_PPS0_TARGET_TIME_SECONDS,The PPS Target Time Seconds register. along with PPS Target Time Nanoseconds register. is used to schedule an interrupt event [Bit 1 of MAC_Timestamp_Status] when the system time exceeds the value programmed in these registers." hexmask.long 0x0 0.--31. 1. "TSTRH0,PPS Target Time Seconds Register This field stores the time in seconds. When the timestamp value matches or exceeds both Target Timestamp registers the MAC starts or stops the PPS signal output and generates an interrupt (if enabled) based on.." line.long 0x4 "MAC_PPS0_TARGET_TIME_NANOSECONDS,PPS0 Target Time Nanoseconds register." bitfld.long 0x4 31. "TRGTBUSY0,PPS Target Time Register Busy The MAC sets this bit when the PPSCMD0 field in the MAC_PPS_Control register is programmed to 010 or 011. Programming the PPSCMD0 field to 010 or 011 instructs the MAC to synchronize the Target Time Registers to.." "PPS Target Time Register Busy status is not..,PPS Target Time Register Busy is detected" newline hexmask.long 0x4 0.--30. 1. "TTSL0,Target Time Low for PPS Register This register stores the time in (signed) nanoseconds. When the value of the timestamp matches the value in both Target Timestamp registers the MAC starts or stops the PPS signal output and generates an interrupt.." line.long 0x8 "MAC_PPS0_INTERVAL,The PPS0 Interval register contains the number of units of sub-second increment value between the rising edges of PPS0 signal output (ptp_pps_o[0])." hexmask.long 0x8 0.--31. 1. "PPSINT0,PPS Output Signal Interval These bits store the interval between the rising edges of PPS0 signal output. The interval is stored in terms of number of units of sub-second increment value. You need to program one value less than the required.." line.long 0xC "MAC_PPS0_WIDTH,The PPS0 Width register contains the number of units of sub-second increment value between the rising and corresponding falling edges of PPS0 signal output (ptp_pps_o[0])." hexmask.long 0xC 0.--31. 1. "PPSWIDTH0,PPS Output Signal Width These bits store the width between the rising edge and corresponding falling edge of PPS0 signal output. The width is stored in terms of number of units of sub-second increment value. You need to program one value less.." line.long 0x10 "MAC_PPS1_TARGET_TIME_SECONDS,The PPS Target Time Seconds register. along with PPS Target Time Nanoseconds register. is used to schedule an interrupt event [Bit 1 of MAC_Timestamp_Status] when the system time exceeds the value programmed in these registers." hexmask.long 0x10 0.--31. 1. "TSTRH1,PPS Target Time Seconds Register This field stores the time in seconds. When the timestamp value matches or exceeds both Target Timestamp registers the MAC starts or stops the PPS signal output and generates an interrupt (if enabled) based on.." line.long 0x14 "MAC_PPS1_TARGET_TIME_NANOSECONDS,PPS0 Target Time Nanoseconds register." bitfld.long 0x14 31. "TRGTBUSY1,PPS Target Time Register Busy The MAC sets this bit when the PPSCMD0 field in the MAC_PPS_Control register is programmed to 010 or 011. Programming the PPSCMD0 field to 010 or 011 instructs the MAC to synchronize the Target Time Registers to.." "PPS Target Time Register Busy status is not..,PPS Target Time Register Busy is detected" newline hexmask.long 0x14 0.--30. 1. "TTSL1,Target Time Low for PPS Register This register stores the time in (signed) nanoseconds. When the value of the timestamp matches the value in both Target Timestamp registers the MAC starts or stops the PPS signal output and generates an interrupt.." line.long 0x18 "MAC_PPS1_INTERVAL,The PPS0 Interval register contains the number of units of sub-second increment value between the rising edges of PPS0 signal output (ptp_pps_o[0])." hexmask.long 0x18 0.--31. 1. "PPSINT1,PPS Output Signal Interval These bits store the interval between the rising edges of PPS0 signal output. The interval is stored in terms of number of units of sub-second increment value. You need to program one value less than the required.." line.long 0x1C "MAC_PPS1_WIDTH,The PPS0 Width register contains the number of units of sub-second increment value between the rising and corresponding falling edges of PPS0 signal output (ptp_pps_o[0])." hexmask.long 0x1C 0.--31. 1. "PPSWIDTH1,PPS Output Signal Width These bits store the width between the rising edge and corresponding falling edge of PPS0 signal output. The width is stored in terms of number of units of sub-second increment value. You need to program one value less.." line.long 0x20 "MAC_PPS2_TARGET_TIME_SECONDS,The PPS Target Time Seconds register. along with PPS Target Time Nanoseconds register. is used to schedule an interrupt event [Bit 1 of MAC_Timestamp_Status] when the system time exceeds the value programmed in these registers." hexmask.long 0x20 0.--31. 1. "TSTRH2,PPS Target Time Seconds Register This field stores the time in seconds. When the timestamp value matches or exceeds both Target Timestamp registers the MAC starts or stops the PPS signal output and generates an interrupt (if enabled) based on.." line.long 0x24 "MAC_PPS2_TARGET_TIME_NANOSECONDS,PPS0 Target Time Nanoseconds register." bitfld.long 0x24 31. "TRGTBUSY2,PPS Target Time Register Busy The MAC sets this bit when the PPSCMD0 field in the MAC_PPS_Control register is programmed to 010 or 011. Programming the PPSCMD0 field to 010 or 011 instructs the MAC to synchronize the Target Time Registers to.." "PPS Target Time Register Busy status is not..,PPS Target Time Register Busy is detected" newline hexmask.long 0x24 0.--30. 1. "TTSL2,Target Time Low for PPS Register This register stores the time in (signed) nanoseconds. When the value of the timestamp matches the value in both Target Timestamp registers the MAC starts or stops the PPS signal output and generates an interrupt.." line.long 0x28 "MAC_PPS2_INTERVAL,The PPS0 Interval register contains the number of units of sub-second increment value between the rising edges of PPS0 signal output (ptp_pps_o[0])." hexmask.long 0x28 0.--31. 1. "PPSINT2,PPS Output Signal Interval These bits store the interval between the rising edges of PPS0 signal output. The interval is stored in terms of number of units of sub-second increment value. You need to program one value less than the required.." line.long 0x2C "MAC_PPS2_WIDTH,The PPS0 Width register contains the number of units of sub-second increment value between the rising and corresponding falling edges of PPS0 signal output (ptp_pps_o[0])." hexmask.long 0x2C 0.--31. 1. "PPSWIDTH2,PPS Output Signal Width These bits store the width between the rising edge and corresponding falling edge of PPS0 signal output. The width is stored in terms of number of units of sub-second increment value. You need to program one value less.." line.long 0x30 "MAC_PPS3_TARGET_TIME_SECONDS,The PPS Target Time Seconds register. along with PPS Target Time Nanoseconds register. is used to schedule an interrupt event [Bit 1 of MAC_Timestamp_Status] when the system time exceeds the value programmed in these registers." hexmask.long 0x30 0.--31. 1. "TSTRH3,PPS Target Time Seconds Register This field stores the time in seconds. When the timestamp value matches or exceeds both Target Timestamp registers the MAC starts or stops the PPS signal output and generates an interrupt (if enabled) based on.." line.long 0x34 "MAC_PPS3_TARGET_TIME_NANOSECONDS,PPS0 Target Time Nanoseconds register." bitfld.long 0x34 31. "TRGTBUSY3,PPS Target Time Register Busy The MAC sets this bit when the PPSCMD0 field in the MAC_PPS_Control register is programmed to 010 or 011. Programming the PPSCMD0 field to 010 or 011 instructs the MAC to synchronize the Target Time Registers to.." "PPS Target Time Register Busy status is not..,PPS Target Time Register Busy is detected" newline hexmask.long 0x34 0.--30. 1. "TTSL3,Target Time Low for PPS Register This register stores the time in (signed) nanoseconds. When the value of the timestamp matches the value in both Target Timestamp registers the MAC starts or stops the PPS signal output and generates an interrupt.." line.long 0x38 "MAC_PPS3_INTERVAL,The PPS0 Interval register contains the number of units of sub-second increment value between the rising edges of PPS0 signal output (ptp_pps_o[0])." hexmask.long 0x38 0.--31. 1. "PPSINT3,PPS Output Signal Interval These bits store the interval between the rising edges of PPS0 signal output. The interval is stored in terms of number of units of sub-second increment value. You need to program one value less than the required.." line.long 0x3C "MAC_PPS3_WIDTH,The PPS0 Width register contains the number of units of sub-second increment value between the rising and corresponding falling edges of PPS0 signal output (ptp_pps_o[0])." hexmask.long 0x3C 0.--31. 1. "PPSWIDTH3,PPS Output Signal Width These bits store the width between the rising edge and corresponding falling edge of PPS0 signal output. The width is stored in terms of number of units of sub-second increment value. You need to program one value less.." line.long 0x40 "MAC_PTO_CONTROL,This register controls the PTP Offload Engine operation. This register is available only when the Enable PTP Timestamp Offload feature is selected." hexmask.long.word 0x40 16.--31. 1. "RESERVED_31_16,Reserved." newline hexmask.long.byte 0x40 8.--15. 1. "DN,Domain Number This field indicates the domain Number in which the PTP node is operating." newline bitfld.long 0x40 7. "PDRDIS,Disable Peer Delay Response response generation When this bit is set the Peer Delay Response (Pdelay_Resp) response is not be generated for received Peer Delay Request (Pdelay_Req) request packet as required by the programmed mode. Note: Setting.." "Peer Delay Response response generation is enabled,Peer Delay Response response generation is.." newline bitfld.long 0x40 6. "DRRDIS,Disable PTO Delay Request/Response response generation When this bit is set the Delay Request and Delay response is not generated for received SYNC and Delay request packet respectively as required by the programmed mode. 0x1: PTO Delay.." "PTO Delay Request/Response response generation..,PTO Delay Request/Response response generation.." newline bitfld.long 0x40 5. "APDREQTRIG,Automatic PTP Pdelay_Req message Trigger When this bit is set one PTP Pdelay_Req message is transmitted. This bit is automatically cleared after the PTP Pdelay_Req message is transmitted. The application should set the APDREQEN bit for this.." "Automatic PTP Pdelay_Req message Trigger is..,Automatic PTP Pdelay_Req message Trigger is.." newline bitfld.long 0x40 4. "ASYNCTRIG,Automatic PTP SYNC message Trigger When this bit is set one PTP SYNC message is transmitted. This bit is automatically cleared after the PTP SYNC message is transmitted. The application should set the ASYNCEN bit for this operation. Access.." "Automatic PTP SYNC message Trigger is disabled,Automatic PTP SYNC message Trigger is enabled" newline rbitfld.long 0x40 3. "RESERVED_3,Reserved." "0,1" newline bitfld.long 0x40 2. "APDREQEN,Automatic PTP Pdelay_Req message Enable When this bit is set PTP Pdelay_Req message is generated periodically based on interval programmed or trigger from application when the MAC is programmed to be in Peer-to-Peer Transparent mode. 0x0:.." "Automatic PTP Pdelay_Req message is disabled,Automatic PTP Pdelay_Req message is enabled" newline bitfld.long 0x40 1. "ASYNCEN,Automatic PTP SYNC message Enable When this bit is set PTP SYNC message is generated periodically based on interval programmed or trigger from application when the MAC is programmed to be in Clock Master mode. 0x0: Automatic PTP SYNC message is.." "Automatic PTP SYNC message is disabled,Automatic PTP SYNC message is enabled" newline bitfld.long 0x40 0. "PTOEN,PTP Offload Enable When this bit is set the PTP Offload feature is enabled. 0x0: PTP Offload feature is disabled 0x1: PTP Offload feature is enabled" "PTP Offload feature is disabled,PTP Offload feature is enabled" line.long 0x44 "MAC_SOURCE_PORT_IDENTITY0,This register contains Bits[31:0] of the 80-bit Source Port Identity of the PTP node. This register is available only when the Enable PTP Timestamp Offload feature is selected." hexmask.long 0x44 0.--31. 1. "SPI0,Source Port Identity 0 This field indicates bits [31:0] of sourcePortIdentity of PTP node." line.long 0x48 "MAC_SOURCE_PORT_IDENTITY1,This register contains Bits[63:32] of the 80-bit Source Port Identity of the PTP node. This register is available only when the Enable PTP Timestamp Offload feature is selected." hexmask.long 0x48 0.--31. 1. "SPI1,Source Port Identity 1 This field indicates bits [63:32] of sourcePortIdentity of PTP node." line.long 0x4C "MAC_SOURCE_PORT_IDENTITY2,This register contains Bits[79:64] of the 80-bit Source Port Identity of the PTP node. This register is available only when the Enable PTP Timestamp Offload feature is selected." hexmask.long.word 0x4C 16.--31. 1. "RESERVED_31_16,Reserved." newline hexmask.long.word 0x4C 0.--15. 1. "SPI2,Source Port Identity 2 This field indicates bits [79:64] of sourcePortIdentity of PTP node." line.long 0x50 "MAC_LOG_MESSAGE_INTERVAL,This register contains the periodic intervals for automatic PTP packet generation. This register is available only when the Enable PTP Timestamp Offload feature is selected." hexmask.long.byte 0x50 24.--31. 1. "LMPDRI,Log Min Pdelay_Req Interval This field indicates logMinPdelayReqInterval of PTP node. This is used to schedule the periodic Pdelay request packet transmission. Allowed values are -15 to 15.Negative value must be represented in 2's-complement form." newline hexmask.long.word 0x50 11.--23. 1. "RESERVED_23_11,Reserved." newline bitfld.long 0x50 8.--10. "DRSYNCR,Delay_Req to SYNC Ratio In Slave mode it is used for controlling frequency of Delay_Req messages transmitted. - 0: DelayReq generated for every received SYNC - 1: DelayReq generated every alternate reception of SYNC - 2: for every 4 SYNC.." "DelayReq generated for every received SYNC,DelayReq generated every alternate reception of..,for every 4 SYNC messages,for every 8 SYNC messages,for every 16 SYNC messages,for every 32 SYNC messages,Reserved,Reserved" newline hexmask.long.byte 0x50 0.--7. 1. "LSI,Log Sync Interval This field indicates the periodicity of the automatically generated SYNC message when the PTP node is Master. Allowed values are -15 to 15. Negative value must be represented in 2's-complement form. For example if the required.." tree.end tree "EQOS_MTL" group.long 0x0++0x3 line.long 0x0 "MTL_OPERATION_MODE,The Operation Mode register establishes the Transmit and Receive operating modes and commands." hexmask.long.word 0x0 16.--31. 1. "RESERVED_31_16,Reserved." newline bitfld.long 0x0 15. "FRPE,Flexible Rx parser Enable When this bit is set to 1 the Programmable Rx Parser functionality is enabled. When the Rx parser is disabled and if the Rx parser is in the middle of the parsing then it gets disabled only after completing the current.." "Flexible Rx parser is disabled,Flexible Rx parser is enabled" newline hexmask.long.byte 0x0 10.--14. 1. "RESERVED_14_10,Reserved." newline bitfld.long 0x0 9. "CNTCLR,Counters Reset When this bit is set all counters are reset. This bit is cleared automatically after 1 clock cycle. If this bit is set along with CNT_PRESET bit CNT_PRESET has precedence. Access restriction applies. Setting 1 sets. Self-cleared." "Counters are not reset,All counters are reset" newline bitfld.long 0x0 8. "CNTPRST,Counters Preset When this bit is set - MTL_TxQ[0-7]_Underflow register is initialized/preset to 12'h7F0. - Missed Packet and Overflow Packet counters in MTL_RxQ[0-7]_Missed_Packet_Overflow_Cnt register is initialized/preset to 12'h7F0. Access.." "Counters Preset is disabled,Counters Preset is enabled" newline rbitfld.long 0x0 7. "RESERVED_7,Reserved." "0,1" newline bitfld.long 0x0 5.--6. "SCHALG,Tx Scheduling Algorithm This field indicates the algorithm for Tx scheduling: 0x2: DWRR algorithm when DCB feature is selected.Otherwise Reserved 0x3: Strict priority algorithm 0x1: WFQ algorithm when DCB feature is selected.Otherwise Reserved.." "WRR algorithm,WFQ algorithm when DCB feature is selected,DWRR algorithm when DCB feature is selected,Strict priority algorithm" newline rbitfld.long 0x0 3.--4. "RESERVED_4_3,Reserved." "0,1,2,3" newline bitfld.long 0x0 2. "RAA,Receive Arbitration Algorithm This field is used to select the arbitration algorithm for the Rx side. - 0: Strict priority (SP) Queue 0 has the lowest priority and the last queue has the highest priority. - 1: Weighted Strict Priority (WSP) 0x0:.." "Strict priority,Weighted Strict Priority" newline bitfld.long 0x0 1. "DTXSTS,Drop Transmit Status When this bit is set the Tx packet status received from the MAC is dropped in the MTL. When this bit is reset the Tx packet status received from the MAC is forwarded to the application. 0x0: Drop Transmit Status is disabled.." "Drop Transmit Status is disabled,Drop Transmit Status is enabled" newline rbitfld.long 0x0 0. "RESERVED_0,Reserved." "0,1" group.long 0x8++0xB line.long 0x0 "MTL_DBG_CTL,The FIFO Debug Access Control and Status register controls the operation mode of FIFO debug access." hexmask.long.word 0x0 19.--31. 1. "RESERVED_31_19,Reserved." newline bitfld.long 0x0 17.--18. "EIEC,ECC Inject Error Control for Tx Rx and TSO memories When EIEE bit of this register is set following are the errors inserted based on the value encoded in this field. 0x0: Insert 1 bit error 0x3: Insert 1 bit error in address field 0x1: Insert 2.." "Insert 1 bit error,Insert 2 bit errors,Insert 3 bit errors,Insert 1 bit error in address field" newline bitfld.long 0x0 16. "EIEE,ECC Inject Error Enable for Tx Rx and TSO memories When set enables the ECC error injection feature. When reset disables the ECC error injection feature. 0x0: ECC Inject Error for Tx Rx and TSO memories is disabled 0x1: ECC Inject Error for Tx.." "ECC Inject Error for Tx,ECC Inject Error for Tx" newline bitfld.long 0x0 15. "STSIE,Transmit Status Available Interrupt Status Enable When this bit is set an interrupt is generated when Transmit status is available in slave mode. 0x0: Transmit Packet Available Interrupt Status is disabled 0x1: Transmit Packet Available Interrupt.." "Transmit Packet Available Interrupt Status is..,Transmit Packet Available Interrupt Status is.." newline bitfld.long 0x0 14. "PKTIE,Receive Packet Available Interrupt Status Enable When this bit is set an interrupt is generated when EOP of received packet is written to the Rx FIFO. 0x0: Receive Packet Available Interrupt Status is disabled 0x1: Receive Packet Available.." "Receive Packet Available Interrupt Status is..,Receive Packet Available Interrupt Status is.." newline bitfld.long 0x0 12.--13. "FIFOSEL,FIFO Selected for Access This field indicates the FIFO selected for debug access: 0x3: Rx FIFO 0x2: TSO FIFO (cannot be accessed when SLVMOD is set) 0x0: Tx FIFO 0x1: Tx Status FIFO (only read access when SLVMOD is set)" "Tx FIFO,Tx Status FIFO,TSO FIFO,Rx FIFO" newline bitfld.long 0x0 11. "FIFOWREN,FIFO Write Enable When this bit is set it enables the Write operation on selected FIFO when FIFO Debug Access is enabled. This bit must not be written to 1 when FIFO Debug Access is not enabled that is FDBGEN bit is 0. Access restriction.." "FIFO Write is disabled,FIFO Write is enabled" newline bitfld.long 0x0 10. "FIFORDEN,FIFO Read Enable When this bit is set it enables the Read operation on selected FIFO when FIFO Debug Access is enabled. This bit must not be written to 1 when FIFO Debug Access is not enabled that is FDBGEN bit is 0. Access restriction.." "FIFO Read is disabled,FIFO Read is enabled" newline bitfld.long 0x0 9. "RSTSEL,Reset Pointers of Selected FIFO When this bit is set the pointers of the currently-selected FIFO are reset when FIFO Debug Access is enabled. This bit must not be written to 1 when FIFO Debug Access is not enabled that is FDBGEN bit is 0. Access.." "Reset Pointers of Selected FIFO is disabled,Reset Pointers of Selected FIFO is enabled" newline bitfld.long 0x0 8. "RSTALL,Reset All Pointers When this bit is set the pointers of all FIFOs are reset when FIFO Debug Access is enabled. This bit must not be written to 1 when FIFO Debug Access is not enabled that is FDBGEN bit is 0. Access restriction applies." "Reset All Pointers is disabled,Reset All Pointers is enabled" newline rbitfld.long 0x0 7. "RESERVED_7,Reserved." "0,1" newline bitfld.long 0x0 5.--6. "PKTSTATE,Encoded Packet State This field is used to write the control information to the Tx FIFO or Rx FIFO. Tx FIFO: - 00: Packet Data - 01: Control Word - 10: SOP Data - 11: EOP Data Rx FIFO: - 00: Packet Data - 01: Normal Status - 10: Last Status -.." "Packet Data,Control Word/Normal Status,SOP Data/Last Status,EOP Data/EOP" newline rbitfld.long 0x0 4. "RESERVED_4,Reserved." "0,1" newline bitfld.long 0x0 2.--3. "BYTEEN,Byte Enables This field indicates the number of data bytes valid in the data register during Write operation. This is valid only when PKTSTATE is 2'b10 (EOP) and Tx FIFO or Rx FIFO is selected. 0x3: All four bytes are valid 0x2: Byte 0 Byte 1.." "Byte 0 valid,Byte 0 and Byte 1 are valid,Byte 0,All four bytes are valid" newline bitfld.long 0x0 1. "DBGMOD,Debug Mode Access to FIFO When this bit is set it indicates that the current access to the FIFO is read write and debug access. In this mode the following access types are allowed: - Read and Write access to Tx FIFO TSO FIFO and Rx FIFO -.." "Debug Mode Access to FIFO is disabled,Debug Mode Access to FIFO is enabled" newline bitfld.long 0x0 0. "FDBGEN,FIFO Debug Access Enable When this bit is set it indicates that the debug mode access to the FIFO is enabled. When this bit is reset it indicates that the FIFO can be accessed only through a master interface. 0x0: FIFO Debug Access is disabled.." "FIFO Debug Access is disabled,FIFO Debug Access is enabled" line.long 0x4 "MTL_DBG_STS,The FIFO Debug Status register contains the status of FIFO debug access." hexmask.long.tbyte 0x4 15.--31. 1. "LOCR,Remaining Locations in the FIFO Slave Access Mode: This field indicates the space available in selected FIFO. Debug Access Mode: This field contains the Write or Read pointer value of the selected FIFO during Write or Read operation respectively." newline hexmask.long.byte 0x4 10.--14. 1. "RESERVED_14_10,Reserved." newline bitfld.long 0x4 9. "STSI,Transmit Status Available Interrupt Status When set this bit indicates that the Slave mode Tx packet is transmitted and the status is available in Tx Status FIFO. This bit is reset when 1 is written to this bit. 0x1: Transmit Status Available.." "Transmit Status Available Interrupt Status not..,Transmit Status Available Interrupt Status.." newline bitfld.long 0x4 8. "PKTI,Receive Packet Available Interrupt Status When set this bit indicates that MAC layer has written the EOP of received packet to the Rx FIFO. This bit is reset when 1 is written to this bit. 0x1: Receive Packet Available Interrupt Status detected.." "Receive Packet Available Interrupt Status not..,Receive Packet Available Interrupt Status detected" newline rbitfld.long 0x4 5.--7. "RESERVED_7_5,Reserved." "0,1,2,3,4,5,6,7" newline rbitfld.long 0x4 3.--4. "BYTEEN,Byte Enables This field indicates the number of data bytes valid in the data register during Read operation. This is valid only when PKTSTATE is 2'b10 (EOP) and Tx FIFO or Rx FIFO is selected. 0x3: All four bytes are valid 0x2: Byte 0 Byte 1 and.." "Byte 0 valid,Byte 0 and Byte 1 are valid,Byte 0,All four bytes are valid" newline rbitfld.long 0x4 1.--2. "PKTSTATE,Encoded Packet State This field is used to get the control or status information of the selected FIFO. Tx FIFO: - 00: Packet Data - 01: Control Word - 10: SOP Data - 11: EOP Data Rx FIFO: - 00: Packet Data - 01: Normal Status - 10: Last Status -.." "Packet Data,Control Word/Normal Status,SOP Data/Last Status,EOP Data/EOP" newline rbitfld.long 0x4 0. "FIFOBUSY,FIFO Busy When set this bit indicates that a FIFO operation is in progress in the MAC and content of the following fields is not valid: - All other fields of this register - All fields of the MTL_FIFO_Debug_Data register 0x1: FIFO Busy detected.." "FIFO Busy not detected,FIFO Busy detected" line.long 0x8 "MTL_FIFO_DEBUG_DATA,The FIFO Debug Data register contains the data to be written to or read from the FIFOs." hexmask.long 0x8 0.--31. 1. "FDBGDATA,FIFO Debug Data During debug or slave access write operation this field contains the data to be written to the Tx FIFO Rx FIFO or TSO FIFO. During debug or slave access read operation this field contains the data read from the Tx FIFO Rx.." rgroup.long 0x20++0x3 line.long 0x0 "MTL_INTERRUPT_STATUS,The software driver (application) reads this register during interrupt service routine or polling to determine the interrupt status of MTL queues and the MAC." hexmask.long.byte 0x0 24.--31. 1. "RESERVED_31_24,Reserved." newline bitfld.long 0x0 23. "MTLPIS,MTL Rx Parser Interrupt Status This bit indicates that there is an interrupt from Rx Parser Block. To reset this bit the application must read the MTL_ Rxp_Interrupt_Status register to get the exact cause of the interrupt and clear its source." "MTL Rx Parser Interrupt status not detected,MTL Rx Parser Interrupt status detected" newline hexmask.long.byte 0x0 19.--22. 1. "RESERVED_22_19,Reserved." newline bitfld.long 0x0 18. "ESTIS,EST (TAS- 802.1Qbv) Interrupt Status This bit indicates an interrupt event during the operation of 802.1Qbv. To reset this bit the application must clear the error/event that has caused the Interrupt. 0x1: EST (TAS- 802.1Qbv) Interrupt status.." "EST,EST" newline bitfld.long 0x0 17. "DBGIS,Debug Interrupt status This bit indicates an interrupt event during the slave access. To reset this bit the application must read the FIFO Debug Access Status register to get the exact cause of the interrupt and clear its source. 0x1: Debug.." "Debug Interrupt status not detected,Debug Interrupt status detected" newline bitfld.long 0x0 16. "RESERVED_MACIS,Reserved." "0,1" newline hexmask.long.byte 0x0 8.--15. 1. "RESERVED_15_8,Reserved." newline bitfld.long 0x0 7. "RESERVED_Q7IS,Reserved." "0,1" newline bitfld.long 0x0 6. "RESERVED_Q6IS,Reserved." "0,1" newline bitfld.long 0x0 5. "RESERVED_Q5IS,Reserved." "0,1" newline bitfld.long 0x0 4. "Q4IS,Queue 4 Interrupt status This bit indicates that there is an interrupt from Queue 4. To reset this bit the application must read the MTL_Q4_Interrupt_Control_Status register to get the exact cause of the interrupt and clear its source. 0x1: Queue 4.." "Queue 4 Interrupt status not detected,Queue 4 Interrupt status detected" newline bitfld.long 0x0 3. "Q3IS,Queue 3 Interrupt status This bit indicates that there is an interrupt from Queue 3. To reset this bit the application must read the MTL_Q3_Interrupt_Control_Status register to get the exact cause of the interrupt and clear its source. 0x1: Queue 3.." "Queue 3 Interrupt status not detected,Queue 3 Interrupt status detected" newline bitfld.long 0x0 2. "Q2IS,Queue 2 Interrupt status This bit indicates that there is an interrupt from Queue 2. To reset this bit the application must read the MTL_Q2_Interrupt_Control_Status register to get the exact cause of the interrupt and clear its source. 0x1: Queue 2.." "Queue 2 Interrupt status not detected,Queue 2 Interrupt status detected" newline bitfld.long 0x0 1. "Q1IS,Queue 1 Interrupt status This bit indicates that there is an interrupt from Queue 1. To reset this bit the application must read the MTL_Q1_Interrupt_Control_Status register to get the exact cause of the interrupt and clear its source. 0x1: Queue 1.." "Queue 1 Interrupt status not detected,Queue 1 Interrupt status detected" newline bitfld.long 0x0 0. "Q0IS,Queue 0 Interrupt status This bit indicates that there is an interrupt from Queue 0. To reset this bit the application must read Queue 0 Interrupt Control and Status register to get the exact cause of the interrupt and clear its source. 0x1: Queue.." "Queue 0 Interrupt status not detected,Queue 0 Interrupt status detected" group.long 0x30++0x7 line.long 0x0 "MTL_RXQ_DMA_MAP0,The Receive Queue and DMA Channel Mapping 0 register is reserved in EQOS-CORE and EQOS-MTL configurations." rbitfld.long 0x0 29.--31. "RESERVED_31_29,Reserved." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 28. "Q3DDMACH,Queue 3 Enabled for Dynamic (per packet) DMA Channel Selection When set this bit indicates that the packets received in Queue 3 are routed to a particular DMA channel as decided in the MAC Receiver based on the DMA channel number programmed in.." "Queue 3 disabled for DA-based DMA Channel..,Queue 3 enabled for DA-based DMA Channel Selection" newline rbitfld.long 0x0 27. "RESERVED_27_Y,Reserved." "0,1" newline bitfld.long 0x0 24.--26. "Q3MDMACH,Queue 3 Mapped to DMA Channel This field controls the routing of the received packet in Queue 3 to the DMA channel: - 000: DMA Channel 0 - 001: DMA Channel 1 - 010: DMA Channel 2 - 011: DMA Channel 3 - 100: DMA Channel 4 - 101: DMA Channel 5 -.." "DMA Channel 0,DMA Channel 1,?,?,?,?,?,?" newline rbitfld.long 0x0 21.--23. "RESERVED_23_21,Reserved." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 20. "Q2DDMACH,Queue 2 Enabled for DA-based DMA Channel Selection When set this bit indicates that the packets received in Queue 2 are routed to a particular DMA channel as decided in the MAC Receiver based on the DMA channel number programmed in the L3-L4.." "Queue 2 disabled for DA-based DMA Channel..,Queue 2 enabled for DA-based DMA Channel Selection" newline rbitfld.long 0x0 19. "RESERVED_19_Y,Reserved." "0,1" newline bitfld.long 0x0 16.--18. "Q2MDMACH,Queue 2 Mapped to DMA Channel This field controls the routing of the received packet in Queue 2 to the DMA channel: - 000: DMA Channel 0 - 001: DMA Channel 1 - 010: DMA Channel 2 - 011: DMA Channel 3 - 100: DMA Channel 4 - 101: DMA Channel 5 -.." "DMA Channel 0,DMA Channel 1,?,?,?,?,?,?" newline rbitfld.long 0x0 13.--15. "RESERVED_15_13,Reserved." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 12. "Q1DDMACH,Queue 1 Enabled for DA-based DMA Channel Selection When set this bit indicates that the packets received in Queue 1 are routed to a particular DMA channel as decided in the MAC Receiver based on the DMA channel number programmed in the L3-L4.." "Queue 1 disabled for DA-based DMA Channel..,Queue 1 enabled for DA-based DMA Channel Selection" newline rbitfld.long 0x0 11. "RESERVED_11_Y,Reserved." "0,1" newline bitfld.long 0x0 8.--10. "Q1MDMACH,Queue 1 Mapped to DMA Channel This field controls the routing of the received packet in Queue 1 to the DMA channel: - 000: DMA Channel 0 - 001: DMA Channel 1 - 010: DMA Channel 2 - 011: DMA Channel 3 - 100: DMA Channel 4 - 101: DMA Channel 5 -.." "DMA Channel 0,DMA Channel 1,?,?,?,?,?,?" newline rbitfld.long 0x0 5.--7. "RESERVED_7_5,Reserved." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 4. "Q0DDMACH,Queue 0 Enabled for DA-based DMA Channel Selection When set this bit indicates that the packets received in Queue 0 are routed to a particular DMA channel as decided in the MAC Receiver based on the DMA channel number programmed in the L3-L4.." "Queue 0 disabled for DA-based DMA Channel..,Queue 0 enabled for DA-based DMA Channel Selection" newline rbitfld.long 0x0 3. "RESERVED_3_Y,Reserved." "0,1" newline bitfld.long 0x0 0.--2. "Q0MDMACH,Queue 0 Mapped to DMA Channel This field controls the routing of the packet received in Queue 0 to the DMA channel: - 000: DMA Channel 0 - 001: DMA Channel 1 - 010: DMA Channel 2 - 011: DMA Channel 3 - 100: DMA Channel 4 - 101: DMA Channel 5 -.." "DMA Channel 0,DMA Channel 1,?,?,?,?,?,?" line.long 0x4 "MTL_RXQ_DMA_MAP1,The Receive Queue and DMA Channel Mapping 1 register is reserved in EQOS-CORE and EQOS-MTL configurations." rbitfld.long 0x4 29.--31. "RESERVED_31_29,Reserved." "0,1,2,3,4,5,6,7" newline rbitfld.long 0x4 28. "RESERVED_Q7DDMACH,Reserved." "0,1" newline rbitfld.long 0x4 27. "RESERVED_27_Y,Reserved." "0,1" newline rbitfld.long 0x4 24.--26. "RESERVED_Q7MDMACH,Reserved." "0,1,2,3,4,5,6,7" newline rbitfld.long 0x4 21.--23. "RESERVED_23_21,Reserved." "0,1,2,3,4,5,6,7" newline rbitfld.long 0x4 20. "RESERVED_Q6DDMACH,Reserved." "0,1" newline rbitfld.long 0x4 19. "RESERVED_19_Y,Reserved." "0,1" newline rbitfld.long 0x4 16.--18. "RESERVED_Q6MDMACH,Reserved." "0,1,2,3,4,5,6,7" newline rbitfld.long 0x4 13.--15. "RESERVED_15_13,Reserved." "0,1,2,3,4,5,6,7" newline rbitfld.long 0x4 12. "RESERVED_Q5DDMACH,Reserved." "0,1" newline rbitfld.long 0x4 11. "RESERVED_11_Y,Reserved." "0,1" newline rbitfld.long 0x4 8.--10. "RESERVED_Q5MDMACH,Reserved." "0,1,2,3,4,5,6,7" newline rbitfld.long 0x4 5.--7. "RESERVED_7_5,Reserved." "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 4. "Q4DDMACH,Queue 4 Enabled for DA-based DMA Channel Selection When set this bit indicates that the packets received in Queue 4 are routed to a particular DMA channel as decided in the MAC Receiver based on the DMA channel number programmed in the L3-L4.." "Queue 4 disabled for DA-based DMA Channel..,Queue 4 enabled for DA-based DMA Channel Selection" newline rbitfld.long 0x4 3. "RESERVED_3_Y,Reserved." "0,1" newline bitfld.long 0x4 0.--2. "Q4MDMACH,Queue 4 Mapped to DMA Channel This field controls the routing of the packet received in Queue 4 to the DMA channel: - 000: DMA Channel 0 - 001: DMA Channel 1 - 010: DMA Channel 2 - 011: DMA Channel 3 - 100: DMA Channel 4 - 101: DMA Channel 5 -.." "DMA Channel 0,DMA Channel 1,?,?,?,?,?,?" group.long 0x40++0x3 line.long 0x0 "MTL_TBS_CTRL,This register controls the operation of Time Based Scheduling." hexmask.long.tbyte 0x0 8.--31. 1. "LEOS,Launch Expiry Offset The value in units of 256 nanoseconds that has to be added to the Launch time to compute the Launch Expiry time. Value valid only when LEOV is set. Max value: 999 999 999 ns additionally should be smaller than CTR-1 value when.." newline rbitfld.long 0x0 7. "RESERVED_7,Reserved." "0,1" newline bitfld.long 0x0 4.--6. "LEGOS,Launch Expiry GSN Offset The number GSN slots that has to be added to the Launch GSN to compute the Launch Expiry time. Value valid only when LEOV is set." "0,1,2,3,4,5,6,7" newline rbitfld.long 0x0 2.--3. "RESERVED_3_2,Reserved." "0,1,2,3" newline bitfld.long 0x0 1. "LEOV,Launch Expiry Offset Valid When set indicates the LEOS field is valid. When not set indicates the Launch Expiry Offset is not valid and the MTL must not check for Launch expiry time. 0x0: LEOS field is invalid 0x1: LEOS field is valid" "LEOS field is invalid,LEOS field is valid" newline bitfld.long 0x0 0. "ESTM,EST offset Mode When this bit is set the Launch Time value used in Time Based Scheduling is interpreted as an EST offset value and is added to the Base Time Register (BTR) of the current list. When reset the Launch Time value is used as an.." "EST offset Mode is disabled,EST offset Mode is enabled" group.long 0x50++0x3 line.long 0x0 "MTL_EST_CONTROL,This register controls the operation of Enhancements to Scheduled Transmission (IEEE802.1Qbv)." hexmask.long.byte 0x0 24.--31. 1. "PTOV,PTP Time Offset Value The value of PTP Clock period multiplied by 6 in nanoseconds. This value is needed to avoid transmission overruns at the beginning of the installation of a new GCL." newline hexmask.long.word 0x0 12.--23. 1. "CTOV,Current Time Offset Value Provides a 12 bit time offset value in nano second that is added to the current time to compensate for all the implementation pipeline delays such as the CDC sync delay buffering delays data path delays etc. This offset.." newline rbitfld.long 0x0 11. "RESERVED_11,Reserved." "0,1" newline bitfld.long 0x0 8.--10. "TILS,Time Interval Left Shift Amount This field provides the left shift amount for the programmed Time Interval values used in the Gate Control Lists. - 000: No left shift needed (equal to x1ns) - 001: Left shift TI by 1 bit (equal to x2ns) - 010: Left.." "No left shift needed,Left shift TI by 1 bit,?,?,?,?,?,?" newline bitfld.long 0x0 6.--7. "LCSE,Loop Count to report Scheduling Error Programmable number of GCL list iterations before reporting an HLBS error defined in EST_Status register. 0x2: 16 iterations 0x3: 32 iterations 0x0: 4 iterations 0x1: 8 iterations" "0,1,2,3" newline bitfld.long 0x0 5. "DFBS,Drop Frames causing Scheduling Error When set frames reported to cause HOL Blocking due to not getting scheduled (HLBS field of EST_Status register) after 4 8 16 32 (based on LCSE field of this register) GCL iterations are dropped. 0x0: Do not Drop.." "Do not Drop Frames causing Scheduling Error,Drop Frames causing Scheduling Error" newline bitfld.long 0x0 4. "DDBF,Do not Drop frames during Frame Size Error When set frames are not be dropped during Head-of-Line blocking due to Frame Size Error (HLBF field of EST_Status register). 0x1: Do not Drop frames during Frame Size Error 0x0: Drop frames during Frame.." "Drop frames during Frame Size Error,Do not Drop frames during Frame Size Error" newline rbitfld.long 0x0 2.--3. "RESERVED_2_3,Reserved." "0,1,2,3" newline bitfld.long 0x0 1. "SSWL,Switch to S/W owned list When set indicates that the software has programmed that list that it currently owns (SWOL) and the hardware should switch to the new list based on the new BTR. Hardware clears this bit when the switch to the SWOL happens to.." "Switch to S/W owned list is disabled,Switch to S/W owned list is enabled" newline bitfld.long 0x0 0. "EEST,Enable EST When reset the gate control list processing is halted and all gates are assumed to be in Open state. Should be set for the hardware to start processing the gate control lists. During the toggle from 0 to 1 the gate control list.." "EST is disabled,EST is enabled" group.long 0x58++0x3 line.long 0x0 "MTL_EST_STATUS,This register provides Status related to Enhancements to Scheduled Transmission (IEEE802.1Qbv)." hexmask.long.word 0x0 20.--31. 1. "RESERVED_31_20,Reserved." newline hexmask.long.byte 0x0 16.--19. 1. "CGSN,Current GCL Slot Number Indicates the slot number of the GCL list. Slot number is a modulo 16 count of the GCL List loops executed so far. Even if a new GCL list is installed the count is incremental." newline hexmask.long.byte 0x0 12.--15. 1. "RESERVED_15_12,Reserved." newline hexmask.long.byte 0x0 8.--11. 1. "BTRL,BTR Error Loop Count Provides the minimum count (N) for which the equation Current Time =< New BTR + (N * New Cycle Time) becomes true. N = '1111' indicates the iterations exceeded the value of 8 and the hardware was not able to update New BTR to be.." newline rbitfld.long 0x0 7. "SWOL,S/W owned list When '0' indicates Gate control list number '0' is owned by software and when '1' indicates the Gate Control list '1' is owned by the software. Any reads/writes by the software (using indirect access via GCL_Control) is directed to.." "Gate control list number '0' is owned by software,Gate control list number '1' is owned by software" newline rbitfld.long 0x0 5.--6. "RESERVED_6_5,Reserved." "0,1,2,3" newline bitfld.long 0x0 4. "CGCE,Constant Gate Control Error This error occurs when the list length (LLR) is 1 and the programmed Time Interval (TI) value after the optional Left Shifting is less than or equal to the Cycle Time (CTR). The above programming implies Gates are either.." "Constant Gate Control Error not detected,Constant Gate Control Error detected" newline rbitfld.long 0x0 3. "HLBS,Head-Of-Line Blocking due to Scheduling Set when the frame is not able to win arbitration and get scheduled even after 4 iterations of the GCL. Indicates to software a potential programming error. The one hot encoded values of the Queue Numbers that.." "Head-Of-Line Blocking due to Scheduling not..,Head-Of-Line Blocking due to Scheduling detected" newline rbitfld.long 0x0 2. "HLBF,Head-Of-Line Blocking due to Frame Size Set when HOL Blocking is noticed on one or more Queues as a result of none of the Time Intervals of gate open in the GCL being greater than or equal to the duration needed for frame size (or frame fragment.." "Head-Of-Line Blocking due to Frame Size not..,Head-Of-Line Blocking due to Frame Size detected" newline bitfld.long 0x0 1. "BTRE,BTR Error When '1' indicates a programming error in the BTR of SWOL where the programmed value is less than current time. If the BTRL = '1111' SWOL is not updated and Software should reprogram the BTR to a value greater than current time and then.." "BTR Error not detected,BTR Error detected" newline bitfld.long 0x0 0. "SWLC,Switch to S/W owned list Complete When '1' indicates the hardware has successfully switched to the SWOL and the SWOL bit has been updated to that effect. Cleared when the SSWL of EST_Control register transitions from 0 to 1 or on a software write." "Switch to S/W owned list Complete not detected,Switch to S/W owned list Complete detected" group.long 0x60++0x7 line.long 0x0 "MTL_EST_SCH_ERROR,This register provides the One Hot encoded Queue Numbers that are having the Scheduling related error (timeout)." hexmask.long 0x0 5.--31. 1. "RESERVED_31_X,Reserved." newline hexmask.long.byte 0x0 0.--4. 1. "SEQN,Schedule Error Queue Number The One Hot Encoded Queue Numbers that have experienced error/timeout described in HLBS field of status register. Access restriction applies. Self-set to 1 on internal event. Setting 1 clears. Setting 0 has no effect." line.long 0x4 "MTL_EST_FRM_SIZE_ERROR,This register provides the One Hot encoded Queue Numbers that are having the Frame Size related error." hexmask.long 0x4 5.--31. 1. "RESERVED_31_X,Reserved." newline hexmask.long.byte 0x4 0.--4. 1. "FEQN,Frame Size Error Queue Number The One Hot Encoded Queue Numbers that have experienced error described in HLBF field of status register. Access restriction applies. Self-set to 1 on internal event. Setting 1 clears. Setting 0 has no effect." rgroup.long 0x68++0x3 line.long 0x0 "MTL_EST_FRM_SIZE_CAPTURE,This register captures the Frame Size and Queue Number of the first occurrence of the Frame Size related error. Up on clearing it captures the data of immediate next occurrence of a similar error." hexmask.long.word 0x0 19.--31. 1. "RESERVED_31_X,Reserved." newline bitfld.long 0x0 16.--18. "HBFQ,Queue Number of HLBF Captures the binary value of the of the first Queue (number) experiencing HLBF error (see HLBF field of status register). Value once written is not altered by any subsequent queue errors of similar nature. Once cleared the queue.." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 15. "RESERVED_15,Reserved." "0,1" newline hexmask.long.word 0x0 0.--14. 1. "HBFS,Frame Size of HLBF Captures the Frame Size of the dropped frame related to queue number indicated in HBFQ field of this register. Contents of this register should be considered invalid if this field is zero. Cleared when MTL_EST_Frm_Size_Error.." group.long 0x70++0x3 line.long 0x0 "MTL_EST_INTR_ENABLE,This register implements the Interrupt Enable bits for the various events that generate an interrupt. Bit positions have a 1 to 1 correlation with the status bit positions in MTL_ETS_Status register." hexmask.long 0x0 5.--31. 1. "RESERVED_31_5,Reserved." newline bitfld.long 0x0 4. "CGCE,Interrupt Enable for CGCE When set generates interrupt when the Constant Gate Control Error occurs and is indicated in the status. When reset this event does not generate an interrupt 0x0: Interrupt for CGCE is disabled 0x1: Interrupt for CGCE is.." "Interrupt for CGCE is disabled,Interrupt for CGCE is enabled" newline bitfld.long 0x0 3. "IEHS,Interrupt Enable for HLBS When set generates interrupt when the Head-of-Line Blocking due to Scheduling issue and is indicated in the status. When reset this event does not generate an interrupt. 0x0: Interrupt for HLBS is disabled 0x1: Interrupt.." "Interrupt for HLBS is disabled,Interrupt for HLBS is enabled" newline bitfld.long 0x0 2. "IEHF,Interrupt Enable for HLBF When set generates interrupt when the Head-of-Line Blocking due to Frame Size error occurs and is indicated in the status. When reset this event does not generate an interrupt. 0x0: Interrupt for HLBF is disabled 0x1:.." "Interrupt for HLBF is disabled,Interrupt for HLBF is enabled" newline bitfld.long 0x0 1. "IEBE,Interrupt Enable for BTR Error When set generates interrupt when the BTR Error occurs and is indicated in the status. When reset this event does not generate an interrupt. 0x0: Interrupt for BTR Error is disabled 0x1: Interrupt for BTR Error is.." "Interrupt for BTR Error is disabled,Interrupt for BTR Error is enabled" newline bitfld.long 0x0 0. "IECC,Interrupt Enable for Switch List When set generates interrupt when the configuration change is successful and the hardware has switched to the new list. When reset this event does not generate an interrupt. 0x0: Interrupt for Switch List is.." "Interrupt for Switch List is disabled,Interrupt for Switch List is enabled" group.long 0x80++0x7 line.long 0x0 "MTL_EST_GCL_CONTROL,This register provides the control information for reading/writing to the Gate Control lists." hexmask.long.byte 0x0 24.--31. 1. "RESERVED_31_24,Reserved." newline bitfld.long 0x0 22.--23. "ESTEIEC,ECC Inject Error Control for EST Memory When EIEE bit of this register is set following are the errors inserted based on the value encoded in this field. This filed will be valid only if DWC_EQOS_ASP_ECC feature is selected during the.." "Insert 1 bit error,Insert 2 bit errors,Insert 3 bit errors,Insert 1 bit error in address field" newline bitfld.long 0x0 21. "ESTEIEE,EST ECC Inject Error Enable When set along with EEST bit of MTL_EST_Control register enables the ECC error injection feature. When reset disables the ECC error injection feature. 0x0: EST ECC Inject Error is disabled 0x1: EST ECC Inject Error.." "EST ECC Inject Error is disabled,EST ECC Inject Error is enabled" newline bitfld.long 0x0 20. "ERR0,When set indicates the last write operation was aborted as software writes to GCL and GCL registers is prohibited when SSWL bit of MTL_EST_Control Register is set. Access restriction applies. Self-set to 1 on internal event. Setting 1 clears." "ERR0 is disabled,ERR1 is enabled" newline rbitfld.long 0x0 18.--19. "RESERVED_19_Y,Reserved." "0,1,2,3" newline hexmask.long.word 0x0 8.--17. 1. "ADDR,Gate Control List Address: (GCLA when GCRR is '0'). Provides the address (row number) of the Gate Control List at which the R/W operation has to be performed. By default the Gate Control List pointed by SWOL of MTL_EST_Status is selected for R/W.." newline bitfld.long 0x0 6.--7. "RESERVED_7_6,Reserved." "0,1,2,3" newline bitfld.long 0x0 5. "DBGB,Debug Mode Bank Select When set to '0' indicates R/W in debug mode should be directed to Bank 0 (GCL0 and corresponding Time related registers). When set to '1' indicates R/W in debug mode should be directed to Bank 1 (GCL1 and corresponding Time.." "R/W in debug mode should be directed to Bank 0,R/W in debug mode should be directed to Bank 1" newline bitfld.long 0x0 4. "DBGM,Debug Mode When set to '1' indicates R/W in debug mode where the memory bank (for GCL and Time related registers) is explicitly provided by DBGB value when set to '0' SWOL bit is used to determine which bank to use. 0x0: Debug Mode is disabled 0x1:.." "Debug Mode is disabled,Debug Mode is enabled" newline bitfld.long 0x0 3. "RESERVED_3,Reserved." "0,1" newline bitfld.long 0x0 2. "GCRR,Gate Control Related Registers When set to '1' indicates the R/W access is for the GCL related registers (BTR CTR TER LLR) whose address is provided by GCRA. When '0' indicates R/W should be directed to GCL from the address provided by GCLA. 0x0:.." "Gate Control Related Registers are disabled,Gate Control Related Registers are enabled" newline bitfld.long 0x0 1. "R1W0,Read '1' Write '0': When set to '1': Read Operation When set to '0': Write Operation. 0x1: Read Operation 0x0: Write Operation" "Write Operation,Read Operation" newline bitfld.long 0x0 0. "SRWO,Start Read/Write Op When set indicates a Read/Write Op has started and is in progress. When reset by hardware indicates the R/W Op has completed or an error has occurred (when bit 20 is set) Reads: Data can be read from MTL_EST_GCL_Data register.." "Start Read/Write Op disabled,Start Read/Write Op enabled" line.long 0x4 "MTL_EST_GCL_DATA,This register holds the read data or write data in case of reads and writes respectively." hexmask.long 0x4 0.--31. 1. "GCD,Gate Control Data The data corresponding to the address selected in the GCL_Control register. Used for both Read and Write operations." group.long 0x90++0x7 line.long 0x0 "MTL_FPE_CTRL_STS,This register controls the operation of. and provides status for Frame Preemption (IEEE802.1Qbu/802.3br)." rbitfld.long 0x0 29.--31. "RESERVED_31_29,Reserved." "0,1,2,3,4,5,6,7" newline rbitfld.long 0x0 28. "HRS,Hold/Release Status - 1: Indicates a Set-and-Hold-MAC operation was last executed and the pMAC is in Hold State. - 0: Indicates a Set-and-Release-MAC operation was last executed and the pMAC is in Release State. 0x1: Indicates a Set-and-Hold-MAC.." "Indicates a Set-and-Release-MAC operation was..,Indicates a Set-and-Hold-MAC operation was last.." newline hexmask.long.word 0x0 16.--27. 1. "RESERVED_27_16,Reserved." newline rbitfld.long 0x0 13.--15. "RESERVED_15_Y,Reserved." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x0 8.--12. 1. "PEC,Preemption Classification When set indicates the corresponding Queue must be classified as preemptable when '0' Queue is classified as express. When both EST (Qbv) and Preemption are enabled Queue-0 is always assumed to be preemptable. When EST.." newline hexmask.long.byte 0x0 2.--7. 1. "RESERVED_7_2,Reserved." newline bitfld.long 0x0 0.--1. "AFSZ,Additional Fragment Size used to indicate in units of 64 bytes the minimum number of bytes over 64 bytes required in non-final fragments of preempted frames. The minimum non-final fragment size is (AFSZ +1) * 64 bytes" "0,1,2,3" line.long 0x4 "MTL_FPE_ADVANCE,This register holds the Hold and Release Advance time." hexmask.long.word 0x4 16.--31. 1. "RADV,Release Advance The maximum time in nanoseconds that can elapse between issuing a RELEASE to the MAC and the MAC being ready to resume transmission of preemptable frames in the absence of there being any express frames available for transmission." newline hexmask.long.word 0x4 0.--15. 1. "HADV,Hold Advance The maximum time in nanoseconds that can elapse between issuing a HOLD to the MAC and the MAC ceasing to transmit any preemptable frame that is in the process of transmission or any preemptable frames that are queued for transmission." group.long 0xA0++0x7 line.long 0x0 "MTL_RXP_CONTROL_STATUS,The MTL_RXP_Control_Status register establishes the operating mode of Rx Parser and provides some status." rbitfld.long 0x0 31. "RXPI,RX Parser in Idle state This status bit is set to 1 when the Rx parser is in Idle State and waiting for a new packet for processing. This bit is used as a handshake with software when parser gets disables. After disabling when bit is set then.." "RX Parser not in Idle state,RX Parser in Idle state" newline hexmask.long.byte 0x0 24.--30. 1. "RESERVED_30_X,Reserved." newline hexmask.long.byte 0x0 16.--23. 1. "NPE,Number of parsable entries in the Instruction table This control indicates the number of parsable entries in the Instruction Memory. This is used in Rx parser logic to detect programming Error. In case number of parsed entries for a packet is more.." newline hexmask.long.byte 0x0 8.--15. 1. "RESERVED_15_X,Reserved." newline hexmask.long.byte 0x0 0.--7. 1. "NVE,Number of valid entries in the Instruction table This control indicates the number of valid entries in the Instruction Memory. This is used in Rx parser logic to detect any programming Error. In case while parsing Table address (memory address) found.." line.long 0x4 "MTL_RXP_INTERRUPT_CONTROL_STATUS,The MTL_RXP_Interrupt_Control_Status registers provides enable control for the interrupts and provides interrupt status." hexmask.long.word 0x4 20.--31. 1. "RESERVED_31_20,Reserved." newline bitfld.long 0x4 19. "PDRFIE,Packet Drop due to RF Interrupt Enable When this bit is set the PDRFIS interrupt is enabled. When this bit is reset the PDRFIS interrupt is disabled. 0x0: Packet Drop due to RF Interrupt is disabled 0x1: Packet Drop due to RF Interrupt is enabled" "Packet Drop due to RF Interrupt is disabled,Packet Drop due to RF Interrupt is enabled" newline bitfld.long 0x4 18. "FOOVIE,Frame Offset Overflow Interrupt Enable When this bit is set the FOOVIS interrupt is enabled. When this bit is reset the FOOVIS interrupt is disabled. 0x0: Frame Offset Overflow Interrupt is disabled 0x1: Frame Offset Overflow Interrupt is enabled" "Frame Offset Overflow Interrupt is disabled,Frame Offset Overflow Interrupt is enabled" newline rbitfld.long 0x4 17. "RESERVED,Reserved" "0,1" newline bitfld.long 0x4 16. "NVEOVIE,Number of Valid Entries Overflow Interrupt Enable When this bit is set the NVEOVIS interrupt is enabled. When this bit is reset the NVEOVIS interrupt is disabled. 0x0: Number of Valid Entries Overflow Interrupt is disabled 0x1: Number of Valid.." "Number of Valid Entries Overflow Interrupt is..,Number of Valid Entries Overflow Interrupt is.." newline hexmask.long.word 0x4 4.--15. 1. "RESERVED_15_4,Reserved." newline bitfld.long 0x4 3. "PDRFIS,Packet Dropped due to RF Interrupt Status If the Rx Parser result says to drop the packet by setting RF=1 in the instruction memory then this bit is set to 1. This bit is cleared when the application writes 1 to this bit. Access restriction.." "Packet Dropped due to RF Interrupt Status not..,Packet Dropped due to RF Interrupt Status detected" newline bitfld.long 0x4 2. "FOOVIS,Frame Offset Overflow Interrupt Status While parsing if the Instruction table entry's 'Frame Offset' found to be more than EOF offset then then this bit is set. This bit is cleared when the application writes 1 to this bit. Access restriction.." "Frame Offset Overflow Interrupt Status not..,Frame Offset Overflow Interrupt Status detected" newline bitfld.long 0x4 1. "NPEOVIS,Number of Parsable Entries Overflow Interrupt Status While parsing a packet if the number of parsed entries found to be more than NPE[] (Number of Parseable Entries in MTL_RXP_Control register) then this bit is set to 1. This bit is cleared when.." "Number of Parsable Entries Overflow Interrupt..,Number of Parsable Entries Overflow Interrupt.." newline bitfld.long 0x4 0. "NVEOVIS,Number of Valid Entries Overflow Interrupt Status While parsing if the Instruction address found to be more than NVE (Number of Valid Entries in MTL_RXP_Control register) then this bit is set to 1. This bit is cleared when the application writes.." "Number of Valid Entries Overflow Interrupt..,Number of Valid Entries Overflow Interrupt.." rgroup.long 0xA8++0x7 line.long 0x0 "MTL_RXP_DROP_CNT,The MTL_RXP_Drop_Cnt register provides the drop count of Rx Parser initiated drops." bitfld.long 0x0 31. "RXPDCOVF,Rx Parser Drop Counter Overflow Bit When set this bit indicates that the MTL_RXP_Drop_cnt (RXPDC) Counter field crossed the maximum limit. Access restriction applies. Clears on read. Self-set to 1 on internal event. 0x1: Rx Parser Drop count.." "Rx Parser Drop count overflow not occurred,Rx Parser Drop count overflow occurred" newline hexmask.long 0x0 0.--30. 1. "RXPDC,Rx Parser Drop count This 31-bit counter is implemented whenever a Rx Parser Drops a packet due to RF =1. The counter is cleared when the register is read." line.long 0x4 "MTL_RXP_ERROR_CNT,The MTL_RXP_Error_Cnt register provides the Rx Parser related error occurrence count." bitfld.long 0x4 31. "RXPECOVF,Rx Parser Error Counter Overflow Bit When set this bit indicates that the MTL_RXP_Error_cnt (RXPEC) Counter field crossed the maximum limit. Access restriction applies. Clears on read. Self-set to 1 on internal event. 0x1: Rx Parser Error count.." "Rx Parser Error count overflow not occurred,Rx Parser Error count overflow occurred" newline hexmask.long 0x4 0.--30. 1. "RXPEC,Rx Parser Error count This 31-bit counter is implemented whenever a Rx Parser encounters following Error scenarios - Entry address >= NVE[] - Number Parsed Entries >= NPE[] - Entry address > EOF data entry address The counter is cleared when the.." group.long 0xB0++0x3 line.long 0x0 "MTL_RXP_INDIRECT_ACC_CONTROL_STATUS,The MTL_RXP_Indirect_Acc_Control_Status register provides the Indirect Access control and status for Rx Parser memory." bitfld.long 0x0 31. "STARTBUSY,FRP Instruction Table Access Busy When this bit is set to 1 by the software then it indicates to start the Read/Write operation from/to the Rx Parser Memory. Software should read this bit as 0 before issuing read or write request to access the.." "hardware not busy,hardware is busy" newline hexmask.long.byte 0x0 23.--30. 1. "RESERVED_30_23,Reserved." newline bitfld.long 0x0 21.--22. "RXPEIEC,ECC Inject Error Control for Rx Parser Memory When EIEE bit of this register is set following are the errors inserted based on the value encoded in this field. 0x0: Insert 1 bit error 0x3: Insert 1 bit error in address field 0x1: Insert 2 bit.." "Insert 1 bit error,Insert 2 bit errors,Insert 3 bit errors,Insert 1 bit error in address field" newline bitfld.long 0x0 20. "RXPEIEE,ECC Inject Error Enable for Rx Parser Memory When set enables the ECC error injection feature. When reset disables the ECC error injection feature. 0x0: ECC Inject Error for Rx Parser Memory is disabled 0x1: ECC Inject Error for Rx Parser.." "ECC Inject Error for Rx Parser Memory is disabled,ECC Inject Error for Rx Parser Memory is enabled" newline rbitfld.long 0x0 17.--19. "RESERVED_19_17,Reserved." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 16. "WRRDN,Read Write Control When this bit is set to 1 indicates the write operation to the Rx Parser Memory. When this bit is set to 0 indicates the read operation to the Rx Parser Memory. 0x0: Read operation to the Rx Parser Memory 0x1: Write operation to.." "Read operation to the Rx Parser Memory,Write operation to the Rx Parser Memory" newline hexmask.long.byte 0x0 10.--15. 1. "RESERVED_15_X,Reserved." newline hexmask.long.word 0x0 0.--9. 1. "ADDR,FRP Instruction Table Offset Address This field indicates the ADDR of the 32-bit entry in Rx parser instruction table. Each entry has 128-bit (4x32-bit words). The X depends on the configurable DWC_EQOS_FRP_ENTRIES If DWC_EQOS_FRP_ENTRIES == 256.." rgroup.long 0xB4++0x3 line.long 0x0 "MTL_RXP_INDIRECT_ACC_DATA,The MTL_RXP_Indirect_Acc_Data registers holds the data associated to Indirect Access to Rx Parser memory." hexmask.long 0x0 0.--31. 1. "DATA,FRP Instruction Table Write/Read Data Software should write this register before issuing any write command. The hardware provides the read data from the Rx Parser Memory for read operation when STARTBUSY =0 after read command." group.long 0xC0++0x3 line.long 0x0 "MTL_ECC_CONTROL,The MTL_ECC_Control register establishes the operating mode of ECC related to MTL memories." hexmask.long.tbyte 0x0 9.--31. 1. "RESERVED_31_9,Reserved." newline bitfld.long 0x0 8. "MEEAO,MTL ECC Error Address Status Over-ride When set the following error address fields will hold the last valid address where the error is detected. When reset the following error address fields will hold the first address where the error is.." "MTL ECC Error Address Status Over-ride is disabled,MTL ECC Error Address Status Over-ride is enabled" newline rbitfld.long 0x0 5.--7. "RESERVED_7_5,Reserved." "0,1,2,3,4,5,6,7" newline rbitfld.long 0x0 4. "RESERVED_TSOEE,Reserved." "0,1" newline bitfld.long 0x0 3. "MRXPEE,MTL Rx Parser ECC Enable When set to 1 enables the ECC feature for Rx Parser memory. When set to zero disables the ECC feature for Rx Parser memory. 0x0: MTL Rx Parser ECC is disabled 0x1: MTL Rx Parser ECC is enabled" "MTL Rx Parser ECC is disabled,MTL Rx Parser ECC is enabled" newline bitfld.long 0x0 2. "MESTEE,MTL EST ECC Enable When set to 1 enables the ECC feature for EST memory. When set to zero disables the ECC feature for EST memory. 0x0: MTL EST ECC is disabled 0x1: MTL EST ECC is enabled" "MTL EST ECC is disabled,MTL EST ECC is enabled" newline bitfld.long 0x0 1. "MRXEE,MTL Rx FIFO ECC Enable When set to 1 enables the ECC feature for MTL Rx FIFO memory. When set to zero disables the ECC feature for MTL Rx FIFO memory. 0x0: MTL Rx FIFO ECC is disabled 0x1: MTL Rx FIFO ECC is enabled" "MTL Rx FIFO ECC is disabled,MTL Rx FIFO ECC is enabled" newline bitfld.long 0x0 0. "MTXEE,MTL Tx FIFO ECC Enable When set to 1 enables the ECC feature for MTL Tx FIFO memory. When set to zero disables the ECC feature for MTL Tx FIFO memory. 0x0: MTL Tx FIFO ECC is disabled 0x1: MTL Tx FIFO ECC is enabled" "MTL Tx FIFO ECC is disabled,MTL Tx FIFO ECC is enabled" rgroup.long 0xC4++0x3 line.long 0x0 "MTL_SAFETY_INTERRUPT_STATUS,The MTL_Safety_Interrupt_Status registers provides Safety interrupt status." bitfld.long 0x0 31. "MCSIS,MAC Safety Uncorrectable Interrupt Status Indicates an uncorrectable Safety-related Interrupt is set in the MAC module. MAC_DPP_FSM_Interrupt_Status register should be read when this bit is set to get the cause of the Safety Interrupt in MAC. 0x1:.." "MAC Safety Uncorrectable Interrupt Status not..,MAC Safety Uncorrectable Interrupt Status detected" newline hexmask.long 0x0 2.--30. 1. "RESERVED_30_2,Reserved." newline bitfld.long 0x0 1. "MEUIS,MTL ECC Uncorrectable error Interrupt Status This bit indicates that an uncorrectable error interrupt event in the MTL ECC safety feature. To get the exact cause of the interrupt the application should read the MTL_ECC_Interrupt_Status register." "MTL ECC Uncorrectable error Interrupt Status not..,MTL ECC Uncorrectable error Interrupt Status.." newline bitfld.long 0x0 0. "MECIS,MTL ECC Correctable error Interrupt Status This bit indicates that a correctable error interrupt event in the MTL ECC safety feature. To get the exact cause of the interrupt the application should read the MTL_ECC_Interrupt_Status register. 0x1:.." "MTL ECC Correctable error Interrupt Status not..,MTL ECC Correctable error Interrupt Status.." group.long 0xC8++0xB line.long 0x0 "MTL_ECC_INTERRUPT_ENABLE,The MTL_ECC_Interrupt_Enable register provides enable bits for the ECC interrupts." hexmask.long.tbyte 0x0 13.--31. 1. "RESERVED_31_13,Reserved." newline bitfld.long 0x0 12. "RPCEIE,Rx Parser memory Correctable Error Interrupt Enable When set generates an interrupt when an uncorrectable error is detected at the Rx Parser memory interface. It is indicated in RPCES status bit of MTL_ECC_Interrupt_Status register. When reset.." "Rx Parser memory Correctable Error Interrupt is..,Rx Parser memory Correctable Error Interrupt is.." newline rbitfld.long 0x0 9.--11. "RESERVED_11_9,Reserved." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 8. "ECEIE,EST memory Correctable Error Interrupt Enable When set generates an interrupt when a correctable error is detected at the MTL EST memory interface. It is indicated in the ECES bit of MTL_ECC_Interrupt_Status register. When reset this event does.." "EST memory Correctable Error Interrupt is disabled,EST memory Correctable Error Interrupt is enabled" newline rbitfld.long 0x0 5.--7. "RESERVED_7_5,Reserved." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 4. "RXCEIE,Rx memory Correctable Error Interrupt Enable When set generates an interrupt when a correctable error is detected at the MTL Rx memory interface. It is indicated in the RXCES bit of MTL_ECC_Interrupt_Status register. When reset this event does.." "Rx memory Correctable Error Interrupt is disabled,Rx memory Correctable Error Interrupt is enabled" newline rbitfld.long 0x0 1.--3. "RESERVED_3_1,Reserved." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 0. "TXCEIE,Tx memory Correctable Error Interrupt Enable When set generates an interrupt when a correctable error is detected at the MTL Tx memory interface. It is indicated in the TXCES bit of MTL_ECC_Interrupt_Status register. When reset this event does.." "Tx memory Correctable Error Interrupt is disabled,Tx memory Correctable Error Interrupt is enabled" line.long 0x4 "MTL_ECC_INTERRUPT_STATUS,The MTL_ECC_Interrupt_Status register provides MTL ECC Interrupt Status." hexmask.long.tbyte 0x4 15.--31. 1. "RESERVED_31_15,Reserved." newline bitfld.long 0x4 14. "RPUES,Rx Parser memory Uncorrectable Error Status When set indicates that an uncorrectable error is detected at Rx Parser memory interface. 0x1: Rx Parser memory Uncorrectable Error Status detected 0x0: Rx Parser memory Uncorrectable Error Status not.." "Rx Parser memory Uncorrectable Error Status not..,Rx Parser memory Uncorrectable Error Status.." newline bitfld.long 0x4 13. "RPAMS,MTL Rx Parser memory Address Mismatch Status This bit when set indicates that address mismatch is found for address bus of Rx Parser memory. 0x1: MTL Rx Parser memory Address Mismatch Status detected 0x0: MTL Rx Parser memory Address Mismatch.." "MTL Rx Parser memory Address Mismatch Status not..,MTL Rx Parser memory Address Mismatch Status.." newline bitfld.long 0x4 12. "RPCES,MTL Rx Parser memory Correctable Error Status This bit when set indicates that correctable error is detected at RX Parser memory interface. 0x1: MTL Rx Parser memory Correctable Error Status detected 0x0: MTL Rx Parser memory Correctable Error.." "MTL Rx Parser memory Correctable Error Status..,MTL Rx Parser memory Correctable Error Status.." newline rbitfld.long 0x4 11. "RESERVED_11,Reserved." "0,1" newline bitfld.long 0x4 10. "EUES,MTL EST memory Uncorrectable Error Status When set indicates that an uncorrectable error is detected at MTL EST memory interface. 0x1: MTL EST memory Uncorrectable Error Status detected 0x0: MTL EST memory Uncorrectable Error Status not detected" "MTL EST memory Uncorrectable Error Status not..,MTL EST memory Uncorrectable Error Status detected" newline bitfld.long 0x4 9. "EAMS,MTL EST memory Address Mismatch Status This bit when set indicates that address mismatch is found for address bus of MTL EST memory. 0x1: MTL EST memory Address Mismatch Status detected 0x0: MTL EST memory Address Mismatch Status not detected" "MTL EST memory Address Mismatch Status not..,MTL EST memory Address Mismatch Status detected" newline bitfld.long 0x4 8. "ECES,MTL EST memory Correctable Error Status This bit when set indicates that correctable error is detected at the MTL EST memory. 0x1: MTL EST memory Correctable Error Status detected 0x0: MTL EST memory Correctable Error Status not detected" "MTL EST memory Correctable Error Status not..,MTL EST memory Correctable Error Status detected" newline rbitfld.long 0x4 7. "RESERVED_7,Reserved." "0,1" newline bitfld.long 0x4 6. "RXUES,MTL Rx memory Uncorrectable Error Status When set indicates that an uncorrectable error is detected at the MTL Rx memory interface. 0x1: MTL Rx memory Uncorrectable Error Status detected 0x0: MTL Rx memory Uncorrectable Error Status not detected" "MTL Rx memory Uncorrectable Error Status not..,MTL Rx memory Uncorrectable Error Status detected" newline bitfld.long 0x4 5. "RXAMS,MTL Rx memory Address Mismatch Status This bit when set indicates that address mismatch is found for address bus of the MTL Rx memory. 0x1: MTL Rx memory Address Mismatch Status detected 0x0: MTL Rx memory Address Mismatch Status not detected" "MTL Rx memory Address Mismatch Status not detected,MTL Rx memory Address Mismatch Status detected" newline bitfld.long 0x4 4. "RXCES,MTL Rx memory Correctable Error Status This bit when set indicates that correctable error is detected at the MTL Rx memory. 0x1: MTL Rx memory correctable Error Status detected 0x0: MTL Rx memory correctable Error Status not detected" "MTL Rx memory correctable Error Status not..,MTL Rx memory correctable Error Status detected" newline rbitfld.long 0x4 3. "RESERVED_3,Reserved." "0,1" newline bitfld.long 0x4 2. "TXUES,MTL Tx memory Uncorrectable Error Status When set indicates that an uncorrectable error is detected at the MTL TX memory interface. 0x1: MTL Tx memory Uncorrectable Error Status detected 0x0: MTL Tx memory Uncorrectable Error Status not detected" "MTL Tx memory Uncorrectable Error Status not..,MTL Tx memory Uncorrectable Error Status detected" newline bitfld.long 0x4 1. "TXAMS,MTL Tx memory Address Mismatch Status This bit when set indicates that address mismatch is found for address bus of the MTL Tx memory. 0x1: MTL Tx memory Address Mismatch Status detected 0x0: MTL Tx memory Address Mismatch Status not detected" "MTL Tx memory Address Mismatch Status not detected,MTL Tx memory Address Mismatch Status detected" newline bitfld.long 0x4 0. "TXCES,MTL Tx memory Correctable Error Status This bit when set indicates that a correctable error is detected at the MTL Tx memory. 0x1: MTL Tx memory Correctable Error Status detected 0x0: MTL Tx memory Correctable Error Status not detected" "MTL Tx memory Correctable Error Status not..,MTL Tx memory Correctable Error Status detected" line.long 0x8 "MTL_ECC_ERR_STS_RCTL,The MTL_ECC_Err_Sts_Rctl register establishes the control for ECC Error status capture." hexmask.long 0x8 6.--31. 1. "RESERVED_31_6,Reserved." newline bitfld.long 0x8 5. "CUES,Clear Uncorrectable Error Status When this bit is set along with EESRE bit of this register based on the EMS field of this register the respective memory's uncorrectable error address and uncorrectable error count values will be cleared upon.." "Clear Uncorrectable Error Status not detected,Clear Uncorrectable Error Status detected" newline bitfld.long 0x8 4. "CCES,Clear Correctable Error Status When this bit is set along with EESRE bit of this register based on the EMS field of this register the respective memory's correctable error address and correctable error count values will be cleared upon reading." "Clear Correctable Error Status not detected,Clear Correctable Error Status detected" newline bitfld.long 0x8 1.--3. "EMS,MTL ECC Memory Selection When EESRE bit of this register is set this field indicates which memory's error status value to be read. The memory selection encoding is as described below. 0x2: MTL EST memory 0x3: MTL Rx Parser memory 0x1: MTL Rx memory.." "MTL Tx memory,MTL Rx memory,MTL EST memory,MTL Rx Parser memory,DMA TSO memory,?,?,?" newline bitfld.long 0x8 0. "EESRE,MTL ECC Error Status Read Enable When this bit is set based on the EMS field of this register the respective memory's error status values will be captured as described below - The correctable and uncorrectable error count values will be captured.." "MTL ECC Error Status Read is disabled,MTL ECC Error Status Read is enabled" rgroup.long 0xD4++0x7 line.long 0x0 "MTL_ECC_ERR_ADDR_STATUS,The MTL_ECC_Err_Addr_Status register provides the memory addresses for the correctable and uncorrectable errors." hexmask.long.word 0x0 16.--31. 1. "EUEAS,MTL ECC Uncorrectable Error Address Status Based on the EMS field of MTL_ECC_Err_Sts_Rctl register this field holds the respective memory's address locations for which an uncorrectable error or address mismatch is detected. When MEEAO bit of.." newline hexmask.long.word 0x0 0.--15. 1. "ECEAS,MTL ECC Correctable Error Address Status Based on the EMS field of MTL_ECC_Err_Sts_Rctl register this field holds the respective memory's address locations for which a correctable error is detected. When MEEAO bit of MTL_ECC_Control register is.." line.long 0x4 "MTL_ECC_ERR_CNTR_STATUS,The MTL_ECC_Err_Cntr_Status register provides ECC Error count for Correctable and uncorrectable errors." hexmask.long.word 0x4 20.--31. 1. "RESERVED_31_20,Reserved." newline hexmask.long.byte 0x4 16.--19. 1. "EUECS,MTL ECC Uncorrectable Error Counter Status Based on the EMS field of MTL_ECC_Err_Cntr_Rctl register this field holds the respective memory's uncorrectable error count value." newline hexmask.long.byte 0x4 8.--15. 1. "RESERVED_15_8,Reserved." newline hexmask.long.byte 0x4 0.--7. 1. "ECECS,MTL ECC Correctable Error Counter Status Based on the EMS field of MTL_ECC_Err_Cntr_Rctl register this field holds the respective memory's correctable error count value." group.long 0xE0++0x3 line.long 0x0 "MTL_DPP_CONTROL,The MTL_DPP_Control establishes the operating mode of Data Parity protection and error injection." hexmask.long.tbyte 0x0 14.--31. 1. "RESERVED_31_14,Reserved." newline bitfld.long 0x0 13. "IPECW,Insert Parity error in CSR Read data parity generator When set to 1 parity bit of first valid data generated by the CSR parity generator (or at PG10 as shown in Fig.AXI slave Interface Data path parity protection) is flipped. Hardware will clear.." "Insert Parity error in CSR Read data parity..,Insert Parity error in CSR Read data parity.." newline rbitfld.long 0x0 12. "RESERVED_IPEASW,Reserved." "0,1" newline bitfld.long 0x0 11. "IPERD,Insert Parity error in Rx write-back Descriptor parity generator When set to 1 parity bit of first valid data generated by the DMA Rx write-back descriptor parity generator(or at PG8 as shown in Fig.Receive data path parity protection) is flipped." "Insert Parity error in Rx write-back Descriptor..,Insert Parity error in Rx write-back Descriptor.." newline bitfld.long 0x0 10. "IPETD,Insert Parity error in Tx write-back Descriptor parity generator When set to 1 parity bit of first valid data generated by the DMA Tx write-back descriptor parity generator(or at PG4 as shown in Fig.Transmit data path parity protection) is.." "Insert Parity error in Tx write-back Descriptor..,Insert Parity error in Tx write-back Descriptor.." newline rbitfld.long 0x0 9. "RESERVED_IPETSO,Reserved." "0,1" newline bitfld.long 0x0 8. "IPEDDC,Insert Parity Error in DMA DTX Control word parity generator When set to 1 parity bit of first valid data generated by the DMA DTX Control word parity generator (or at PG2 as shown in Fig.Transmit data path parity protection) is flipped. Hardware.." "Insert Parity Error in DMA DTX Control word..,Insert Parity Error in DMA DTX Control word.." newline bitfld.long 0x0 7. "IPEMRF,Insert Parity Error in MTL Rx FIFO read control parity generator When set to 1 parity bit of first valid data generated by the MTL Rx FIFO read control parity generator (or at PG7 as shown in Fig.Receive data path parity protection) is flipped." "Insert Parity Error in MTL Rx FIFO read control..,Insert Parity Error in MTL Rx FIFO read control.." newline bitfld.long 0x0 6. "IPEMTS,Insert Parity Error in MTL Tx Status parity generator When set to 1 parity bit of first valid data generated by the MTL Tx Status parity generator (or at PG6 as shown in Fig.Transmit data path parity protection) is flipped. Hardware will clear.." "Insert Parity Error in MTL Tx Status parity..,Insert Parity Error in MTL Tx Status parity.." newline bitfld.long 0x0 5. "IPEMC,Insert Parity Error in MTL checksum parity generator When set to 1 parity bit of first valid data generated by the MTL checksum parity generator (or at PG5 as shown in Fig.Transmit data path parity protection) is flipped. Hardware will clear this.." "Insert Parity Error in MTL checksum parity..,Insert Parity Error in MTL checksum parity.." newline rbitfld.long 0x0 4. "RESERVED_IPEID,Reserved." "0,1" newline rbitfld.long 0x0 3. "RESERVED_3,Reserved." "0,1" newline bitfld.long 0x0 2. "EPSI,Enable Parity on Slave Interface port When set to 1 enables the parity check for the slave interface ports and disables the internal generation of parity for the input slave data port. When set to 0 disables the parity check for the slave.." "Parity on Slave Interface port is disabled,Parity on Slave Interface port is enabled" newline bitfld.long 0x0 1. "OPE,Odd Parity Enable When set to 1 enables odd parity protection on all the external interfaces and when set to 0 enables even parity protection on all the external interfaces. 0x0: Odd Parity is disabled 0x1: Odd Parity is enabled" "Odd Parity is disabled,Odd Parity is enabled" newline bitfld.long 0x0 0. "EDPP,Enable Data path Parity Protection When set to 1 enables the parity protection for EQOS datapath by generating and checking the parity on EQOS datapath. When set to 0 disables the parity protection for EQOS datapath. 0x0: Data path Parity.." "Data path Parity Protection is disabled,Data path Parity Protection is enabled" tree.end tree "EQOS_MTL_Q0" group.long 0x0++0x3 line.long 0x0 "MTL_TXQ0_OPERATION_MODE,The Queue 0 Transmit Operation Mode register establishes the Transmit queue operating modes and commands." hexmask.long.word 0x0 21.--31. 1. "RESERVED_31_Y,Reserved." newline hexmask.long.byte 0x0 16.--20. 1. "TQS,Transmit Queue Size This field indicates the size of the allocated Transmit queues in blocks of 256 bytes. The TQS field is read-write only if the number of Tx Queues more than one the reset value is 0x0 and indicates size of 256 bytes. When the.." newline hexmask.long.word 0x0 7.--15. 1. "RESERVED_15_7,Reserved." newline bitfld.long 0x0 4.--6. "TTC,Transmit Threshold Control These bits control the threshold level of the MTL Tx Queue. The transmission starts when the packet size within the MTL Tx Queue is larger than the threshold. In addition full packets with length less than the threshold.." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 2.--3. "TXQEN,Transmit Queue Enable This field is used to enable/disable the transmit queue 0. - 2'b00: Not enabled - 2'b01: Reserved - 2'b10: Enabled - 2'b11: Reserved This field is Read Only in Single Queue configurations and Read Write in Multiple Queue.." "Not enabled,Enable in AV mode,Enabled,Reserved" newline bitfld.long 0x0 1. "TSF,Transmit Store and Forward When this bit is set the transmission starts when a full packet resides in the MTL Tx queue. When this bit is set the TTC values specified in Bits[6:4] of this register are ignored. This bit should be changed only when.." "Transmit Store and Forward is disabled,Transmit Store and Forward is enabled" newline bitfld.long 0x0 0. "FTQ,Flush Transmit Queue When this bit is set the Tx queue controller logic is reset to its default values. Therefore all the data in the Tx queue is lost or flushed. This bit is internally reset when the flushing operation is complete. Until this bit.." "Flush Transmit Queue is disabled,Flush Transmit Queue is enabled" rgroup.long 0x4++0x7 line.long 0x0 "MTL_TXQ0_UNDERFLOW,The Queue 0 Underflow Counter register contains the counter for packets aborted because of Transmit queue underflow and packets missed because of Receive queue packet flush" hexmask.long.tbyte 0x0 12.--31. 1. "RESERVED_31_12,Reserved." newline bitfld.long 0x0 11. "UFCNTOVF,Overflow Bit for Underflow Packet Counter This bit is set every time the Tx queue Underflow Packet Counter field overflows that is it has crossed the maximum count. In such a scenario the overflow packet counter is reset to all-zeros and this.." "Overflow not detected for Underflow Packet Counter,Overflow detected for Underflow Packet Counter" newline hexmask.long.word 0x0 0.--10. 1. "UFFRMCNT,Underflow Packet Counter This field indicates the number of packets aborted by the controller because of Tx Queue Underflow. This counter is incremented each time the MAC aborts outgoing packet because of underflow. The counter is cleared when.." line.long 0x4 "MTL_TXQ0_DEBUG,The Queue 0 Transmit Debug register gives the debug status of various blocks related to the Transmit queue." hexmask.long.word 0x4 23.--31. 1. "RESERVED_31_23,Reserved." newline bitfld.long 0x4 20.--22. "STXSTSF,Number of Status Words in Tx Status FIFO of Queue This field indicates the current number of status in the Tx Status FIFO of this queue. When the DTXSTS bit of MTL_Operation_Mode register is set to 1 this field does not reflect the number of.." "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 19. "RESERVED_19,Reserved." "0,1" newline bitfld.long 0x4 16.--18. "PTXQ,Number of Packets in the Transmit Queue This field indicates the current number of packets in the Tx Queue. When the DTXSTS bit of MTL_Operation_Mode register is set to 1 this field does not reflect the number of packets in the Transmit queue." "0,1,2,3,4,5,6,7" newline hexmask.long.word 0x4 6.--15. 1. "RESERVED_15_6,Reserved." newline bitfld.long 0x4 5. "TXSTSFSTS,MTL Tx Status FIFO Full Status When high this bit indicates that the MTL Tx Status FIFO is full. Therefore the MTL cannot accept any more packets for transmission. 0x1: MTL Tx Status FIFO Full status is detected 0x0: MTL Tx Status FIFO Full.." "MTL Tx Status FIFO Full status is not detected,MTL Tx Status FIFO Full status is detected" newline bitfld.long 0x4 4. "TXQSTS,MTL Tx Queue Not Empty Status When this bit is high it indicates that the MTL Tx Queue is not empty and some data is left for transmission. 0x1: MTL Tx Queue Not Empty status is detected 0x0: MTL Tx Queue Not Empty status is not detected" "MTL Tx Queue Not Empty status is not detected,MTL Tx Queue Not Empty status is detected" newline bitfld.long 0x4 3. "TWCSTS,MTL Tx Queue Write Controller Status When high this bit indicates that the MTL Tx Queue Write Controller is active and it is transferring the data to the Tx Queue. 0x1: MTL Tx Queue Write Controller status is detected 0x0: MTL Tx Queue Write.." "MTL Tx Queue Write Controller status is not..,MTL Tx Queue Write Controller status is detected" newline bitfld.long 0x4 1.--2. "TRCSTS,MTL Tx Queue Read Controller Status This field indicates the state of the Tx Queue Read Controller: 0x3: Flushing the Tx queue because of the Packet Abort request from the MAC 0x0: Idle state 0x1: Read state (transferring data to the MAC.." "Idle state,Read state,Waiting for pending Tx Status from the MAC..,Flushing the Tx queue because of the Packet.." newline bitfld.long 0x4 0. "TXQPAUSED,Transmit Queue in Pause When this bit is high and the Rx flow control is enabled it indicates that the Tx Queue is in the Pause condition (in the full-duplex only mode) because of the following: - Reception of the PFC packet for the priorities.." "Transmit Queue in Pause status is not detected,Transmit Queue in Pause status is detected" rgroup.long 0x14++0x3 line.long 0x0 "MTL_TXQ0_ETS_STATUS,The Queue 0 ETS Status register provides the average traffic transmitted in Queue 0." hexmask.long.byte 0x0 24.--31. 1. "RESERVED_31_24,Reserved." newline hexmask.long.tbyte 0x0 0.--23. 1. "ABS,Average Bits per Slot This field contains the average transmitted bits per slot. When the DCB operation is enabled for Queue 0 this field is computed over every 10 million bit times slot (4 ms in 2500 Mbps; 10 ms in 1000 Mbps; 100 ms in 100 Mbps)." group.long 0x18++0x3 line.long 0x0 "MTL_TXQ0_QUANTUM_WEIGHT,The Queue 0 Quantum or Weights register contains the quantum value for Deficit Weighted Round Robin (DWRR). weights for the Weighted Round Robin (WRR). and Weighted Fair Queuing (WFQ) for Queue 0." hexmask.long.word 0x0 21.--31. 1. "RESERVED_31_21,Reserved." newline hexmask.long.tbyte 0x0 0.--20. 1. "ISCQW,Quantum or Weights When the DCB operation is enabled with DWRR algorithm for Queue 0 traffic this field contains the quantum value in bytes to be added to credit during every queue scanning cycle. The maximum value is 0x1312D0 bytes. When DCB.." group.long 0x2C++0x7 line.long 0x0 "MTL_Q0_INTERRUPT_CONTROL_STATUS,This register contains the interrupt enable and status bits for the queue 0 interrupts." hexmask.long.byte 0x0 25.--31. 1. "RESERVED_31_25,Reserved." newline bitfld.long 0x0 24. "RXOIE,Receive Queue Overflow Interrupt Enable When this bit is set the Receive Queue Overflow interrupt is enabled. When this bit is reset the Receive Queue Overflow interrupt is disabled. 0x0: Receive Queue Overflow Interrupt is disabled 0x1: Receive.." "Receive Queue Overflow Interrupt is disabled,Receive Queue Overflow Interrupt is enabled" newline hexmask.long.byte 0x0 17.--23. 1. "RESERVED_23_17,Reserved." newline bitfld.long 0x0 16. "RXOVFIS,Receive Queue Overflow Interrupt Status This bit indicates that the Receive Queue had an overflow while receiving the packet. If a partial packet is transferred to the application the overflow status is set in RDES3[21]. This bit is cleared when.." "Receive Queue Overflow Interrupt Status not..,Receive Queue Overflow Interrupt Status detected" newline hexmask.long.byte 0x0 10.--15. 1. "RESERVED_15_10,Reserved." newline bitfld.long 0x0 9. "ABPSIE,Average Bits Per Slot Interrupt Enable When this bit is set the MAC asserts the sbd_intr_o or mci_intr_o interrupt when the average bits per slot status is updated. When this bit is cleared the interrupt is not asserted for such an event. 0x0:.." "Average Bits Per Slot Interrupt is disabled,Average Bits Per Slot Interrupt is enabled" newline bitfld.long 0x0 8. "TXUIE,Transmit Queue Underflow Interrupt Enable When this bit is set the Transmit Queue Underflow interrupt is enabled. When this bit is reset the Transmit Queue Underflow interrupt is disabled. 0x0: Transmit Queue Underflow Interrupt Status is.." "Transmit Queue Underflow Interrupt Status is..,Transmit Queue Underflow Interrupt Status is.." newline hexmask.long.byte 0x0 2.--7. 1. "RESERVED_7_2,Reserved." newline bitfld.long 0x0 1. "ABPSIS,Average Bits Per Slot Interrupt Status When set this bit indicates that the MAC has updated the ABS value. This bit is cleared when the application writes 1 to this bit. Access restriction applies. Self-set to 1 on internal event. Setting 1.." "Average Bits Per Slot Interrupt Status not..,Average Bits Per Slot Interrupt Status detected" newline bitfld.long 0x0 0. "TXUNFIS,Transmit Queue Underflow Interrupt Status This bit indicates that the Transmit Queue had an underflow while transmitting the packet. Transmission is suspended and an Underflow Error TDES3[2] is set. This bit is cleared when the application writes.." "Transmit Queue Underflow Interrupt Status not..,Transmit Queue Underflow Interrupt Status detected" line.long 0x4 "MTL_RXQ0_OPERATION_MODE,The Queue 0 Receive Operation Mode register establishes the Receive queue operating modes and command. The RFA and RFD fields are not backward compatible with the RFA and RFD fields of 4.00a release" hexmask.long.byte 0x4 25.--31. 1. "RESERVED_31_Y,Reserved." newline hexmask.long.byte 0x4 20.--24. 1. "RQS,Receive Queue Size This field indicates the size of the allocated Receive queues in blocks of 256 bytes. The RQS field is read-write only if the number of Rx Queues more than one the reset value is 0x0 and indicates size of 256 bytes. When the.." newline rbitfld.long 0x4 18.--19. "RESERVED_19_Y,Reserved." "0,1,2,3" newline hexmask.long.byte 0x4 14.--17. 1. "RFD,Threshold for Deactivating Flow Control (in half-duplex and full-duplex modes) These bits control the threshold (fill-level of Rx queue) at which the flow control is de-asserted after activation: - 0: Full minus 1 KB that is FULL 1 KB - 1: Full.." newline rbitfld.long 0x4 12.--13. "RESERVED_13_Y,Reserved." "0,1,2,3" newline hexmask.long.byte 0x4 8.--11. 1. "RFA,Threshold for Activating Flow Control (in half-duplex and full-duplex These bits control the threshold (fill-level of Rx queue) at which the flow control is activated: For more information on encoding for this field see RFD." newline bitfld.long 0x4 7. "EHFC,Enable Hardware Flow Control When this bit is set the flow control signal operation based on the fill-level of Rx queue is enabled. When reset the flow control operation is disabled. 0x0: Hardware Flow Control is disabled 0x1: Hardware Flow.." "Hardware Flow Control is disabled,Hardware Flow Control is enabled" newline bitfld.long 0x4 6. "DIS_TCP_EF,Disable Dropping of TCP/IP Checksum Error Packets When this bit is set the MAC does not drop the packets which only have the errors detected by the Receive Checksum Offload engine. Such packets have errors only in the encapsulated payload." "Dropping of TCP/IP Checksum Error Packets is..,Dropping of TCP/IP Checksum Error Packets is.." newline bitfld.long 0x4 5. "RSF,Receive Queue Store and Forward When this bit is set the DWC_ether_qos reads a packet from the Rx queue only after the complete packet has been written to it ignoring the RTC field of this register. When this bit is reset the Rx queue operates in.." "Receive Queue Store and Forward is disabled,Receive Queue Store and Forward is enabled" newline bitfld.long 0x4 4. "FEP,Forward Error Packets When this bit is reset the Rx queue drops packets with error status (CRC error GMII_ER watchdog timeout or overflow). However if the start byte (write) pointer of a packet is already transferred to the read controller side.." "Forward Error Packets is disabled,Forward Error Packets is enabled" newline bitfld.long 0x4 3. "FUP,Forward Undersized Good Packets When this bit is set the Rx queue forwards the undersized good packets (packets with no error and length less than 64 bytes) including pad-bytes and CRC. When this bit is reset the Rx queue drops all packets of less.." "Forward Undersized Good Packets is disabled,Forward Undersized Good Packets is enabled" newline rbitfld.long 0x4 2. "RESERVED_2,Reserved." "0,1" newline bitfld.long 0x4 0.--1. "RTC,Receive Queue Threshold Control These bits control the threshold level of the MTL Rx queue (in bytes): The received packet is transferred to the application or DMA when the packet size within the MTL Rx queue is larger than the threshold. In addition.." "0,1,2,3" rgroup.long 0x34++0x7 line.long 0x0 "MTL_RXQ0_MISSED_PACKET_OVERFLOW_CNT,The Queue 0 Missed Packet and Overflow Counter register contains the counter for packets missed because of Receive queue packet flush and packets discarded because of Receive queue overflow." hexmask.long.byte 0x0 28.--31. 1. "RESERVED_31_28,Reserved." newline bitfld.long 0x0 27. "MISCNTOVF,Missed Packet Counter Overflow Bit When set this bit indicates that the Rx Queue Missed Packet Counter crossed the maximum limit. Access restriction applies. Clears on read. Self-set to 1 on internal event. 0x1: Missed Packet Counter overflow.." "Missed Packet Counter overflow not detected,Missed Packet Counter overflow detected" newline hexmask.long.word 0x0 16.--26. 1. "MISPKTCNT,Missed Packet Counter This field indicates the number of packets missed by the DWC_ether_qos because the application asserted ari_pkt_flush_i[] for this queue. This counter is reset when this register is read with mci_be_i[0] at 1b1. This.." newline hexmask.long.byte 0x0 12.--15. 1. "RESERVED_15_12,Reserved." newline bitfld.long 0x0 11. "OVFCNTOVF,Overflow Counter Overflow Bit When set this bit indicates that the Rx Queue Overflow Packet Counter field crossed the maximum limit. Access restriction applies. Clears on read. Self-set to 1 on internal event. 0x1: Overflow Counter overflow.." "Overflow Counter overflow not detected,Overflow Counter overflow detected" newline hexmask.long.word 0x0 0.--10. 1. "OVFPKTCNT,Overflow Packet Counter This field indicates the number of packets discarded by the DWC_ether_qos because of Receive queue overflow. This counter is incremented each time the DWC_ether_qos discards an incoming packet because of overflow. This.." line.long 0x4 "MTL_RXQ0_DEBUG,The Queue 0 Receive Debug register gives the debug status of various blocks related to the Receive queue." bitfld.long 0x4 30.--31. "RESERVED_31_30,Reserved." "0,1,2,3" newline hexmask.long.word 0x4 16.--29. 1. "PRXQ,Number of Packets in Receive Queue This field indicates the current number of packets in the Rx Queue. The theoretical maximum value for this field is 256KB/16B = 16K Packets that is Max_Queue_Size/Min_Packet_Size." newline hexmask.long.word 0x4 6.--15. 1. "RESERVED_15_6,Reserved." newline bitfld.long 0x4 4.--5. "RXQSTS,MTL Rx Queue Fill-Level Status This field gives the status of the fill-level of the Rx Queue: 0x2: Rx Queue fill-level above flow-control activate threshold 0x1: Rx Queue fill-level below flow-control deactivate threshold 0x0: Rx Queue empty 0x3:.." "Rx Queue empty,Rx Queue fill-level below flow-control..,Rx Queue fill-level above flow-control activate..,Rx Queue full" newline bitfld.long 0x4 3. "RESERVED_3,Reserved." "0,1" newline bitfld.long 0x4 1.--2. "RRCSTS,MTL Rx Queue Read Controller State This field gives the state of the Rx queue Read controller: 0x3: Flushing the packet data and status 0x0: Idle state 0x1: Reading packet data 0x2: Reading packet status (or timestamp)" "Idle state,Reading packet data,Reading packet status,Flushing the packet data and status" newline bitfld.long 0x4 0. "RWCSTS,MTL Rx Queue Write Controller Active Status When high this bit indicates that the MTL Rx queue Write controller is active and it is transferring a received packet to the Rx Queue. 0x1: MTL Rx Queue Write Controller Active Status detected 0x0:.." "MTL Rx Queue Write Controller Active Status not..,MTL Rx Queue Write Controller Active Status.." group.long 0x3C++0x3 line.long 0x0 "MTL_RXQ0_CONTROL,The Queue Receive Control register controls the receive arbitration and passing of received packets to the application." hexmask.long 0x0 4.--31. 1. "RESERVED_31_4,Reserved." newline bitfld.long 0x0 3. "RXQ_FRM_ARBIT,Receive Queue Packet Arbitration When this bit is set the DWC_ether_qos drives the packet data to the ARI interface such that the entire packet data of currently-selected queue is transmitted before switching to other queue. When this bit.." "Receive Queue Packet Arbitration is disabled,Receive Queue Packet Arbitration is enabled" newline bitfld.long 0x0 0.--2. "RXQ_WEGT,Receive Queue Weight This field indicates the weight assigned to the Rx Queue 0. The weight is used as the number of continuous PBL or packets requests (depending on the RXQ_FRM_ARBIT) allocated to the queue in one arbitration cycle." "0,1,2,3,4,5,6,7" tree.end tree "EQOS_MTL_Q1" group.long 0x0++0x3 line.long 0x0 "MTL_TXQ1_OPERATION_MODE,The Queue 1 Transmit Operation Mode register establishes the Transmit queue operating modes and commands." hexmask.long.word 0x0 21.--31. 1. "RESERVED_31_Y,Reserved." newline hexmask.long.byte 0x0 16.--20. 1. "TQS,Transmit Queue Size This field indicates the size of the allocated Transmit queues in blocks of 256 bytes. The TQS field is read-write only if the number of Tx Queues more than one the reset value is 0x0 and indicates size of 256 bytes. When the.." newline hexmask.long.word 0x0 7.--15. 1. "RESERVED_15_7,Reserved." newline bitfld.long 0x0 4.--6. "TTC,Transmit Threshold Control These bits control the threshold level of the MTL Tx Queue. The transmission starts when the packet size within the MTL Tx Queue is larger than the threshold. In addition full packets with length less than the threshold.." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 2.--3. "TXQEN,Transmit Queue Enable This field is used to enable/disable the transmit queue 0. - 2'b00: Not enabled - 2'b01: Enable in AV mode - 2'b10: Enabled - 2'b11: Reserved Note: In multiple Tx queues configuration all the queues are disabled by default." "Not enabled,Enable in AV mode,Enabled,Reserved" newline bitfld.long 0x0 1. "TSF,Transmit Store and Forward When this bit is set the transmission starts when a full packet resides in the MTL Tx queue. When this bit is set the TTC values specified in Bits[6:4] of this register are ignored. This bit should be changed only when.." "Transmit Store and Forward is disabled,Transmit Store and Forward is enabled" newline bitfld.long 0x0 0. "FTQ,Flush Transmit Queue When this bit is set the Tx queue controller logic is reset to its default values. Therefore all the data in the Tx queue is lost or flushed. This bit is internally reset when the flushing operation is complete. Until this bit.." "Flush Transmit Queue is disabled,Flush Transmit Queue is enabled" rgroup.long 0x4++0x7 line.long 0x0 "MTL_TXQ1_UNDERFLOW,The Queue 1 Underflow Counter register contains the counter for packets aborted because of Transmit queue underflow and packets missed because of Receive queue packet flush" hexmask.long.tbyte 0x0 12.--31. 1. "RESERVED_31_12,Reserved." newline bitfld.long 0x0 11. "UFCNTOVF,Overflow Bit for Underflow Packet Counter This bit is set every time the Tx queue Underflow Packet Counter field overflows that is it has crossed the maximum count. In such a scenario the overflow packet counter is reset to all-zeros and this.." "Overflow not detected for Underflow Packet Counter,Overflow detected for Underflow Packet Counter" newline hexmask.long.word 0x0 0.--10. 1. "UFFRMCNT,Underflow Packet Counter This field indicates the number of packets aborted by the controller because of Tx Queue Underflow. This counter is incremented each time the MAC aborts outgoing packet because of underflow. The counter is cleared when.." line.long 0x4 "MTL_TXQ1_DEBUG,The Queue 1 Transmit Debug register gives the debug status of various blocks related to the Transmit queue." hexmask.long.word 0x4 23.--31. 1. "RESERVED_31_23,Reserved." newline bitfld.long 0x4 20.--22. "STXSTSF,Number of Status Words in Tx Status FIFO of Queue This field indicates the current number of status in the Tx Status FIFO of this queue. When the DTXSTS bit of MTL_Operation_Mode register is set to 1 this field does not reflect the number of.." "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 19. "RESERVED_19,Reserved." "0,1" newline bitfld.long 0x4 16.--18. "PTXQ,Number of Packets in the Transmit Queue This field indicates the current number of packets in the Tx Queue. When the DTXSTS bit of MTL_Operation_Mode register is set to 1 this field does not reflect the number of packets in the Transmit queue." "0,1,2,3,4,5,6,7" newline hexmask.long.word 0x4 6.--15. 1. "RESERVED_15_6,Reserved." newline bitfld.long 0x4 5. "TXSTSFSTS,MTL Tx Status FIFO Full Status When high this bit indicates that the MTL Tx Status FIFO is full. Therefore the MTL cannot accept any more packets for transmission. 0x1: MTL Tx Status FIFO Full status is detected 0x0: MTL Tx Status FIFO Full.." "MTL Tx Status FIFO Full status is not detected,MTL Tx Status FIFO Full status is detected" newline bitfld.long 0x4 4. "TXQSTS,MTL Tx Queue Not Empty Status When this bit is high it indicates that the MTL Tx Queue is not empty and some data is left for transmission. 0x1: MTL Tx Queue Not Empty status is detected 0x0: MTL Tx Queue Not Empty status is not detected" "MTL Tx Queue Not Empty status is not detected,MTL Tx Queue Not Empty status is detected" newline bitfld.long 0x4 3. "TWCSTS,MTL Tx Queue Write Controller Status When high this bit indicates that the MTL Tx Queue Write Controller is active and it is transferring the data to the Tx Queue. 0x1: MTL Tx Queue Write Controller status is detected 0x0: MTL Tx Queue Write.." "MTL Tx Queue Write Controller status is not..,MTL Tx Queue Write Controller status is detected" newline bitfld.long 0x4 1.--2. "TRCSTS,MTL Tx Queue Read Controller Status This field indicates the state of the Tx Queue Read Controller: 0x3: Flushing the Tx queue because of the Packet Abort request from the MAC 0x0: Idle state 0x1: Read state (transferring data to the MAC.." "Idle state,Read state,Waiting for pending Tx Status from the MAC..,Flushing the Tx queue because of the Packet.." newline bitfld.long 0x4 0. "TXQPAUSED,Transmit Queue in Pause When this bit is high and the Rx flow control is enabled it indicates that the Tx Queue is in the Pause condition (in the full-duplex only mode) because of the following: - Reception of the PFC packet for the priorities.." "Transmit Queue in Pause status is not detected,Transmit Queue in Pause status is detected" group.long 0x10++0x3 line.long 0x0 "MTL_TXQ1_ETS_CONTROL,The Queue ETS Control register controls the enhanced transmission selection operation." hexmask.long 0x0 7.--31. 1. "RESERVED_31_7,Reserved." newline bitfld.long 0x0 4.--6. "SLC,Slot Count If the credit-based shaper algorithm is enabled the software can program the number of slots (of duration programmed in DMA_CH[n]_Slot_Interval register) over which the average transmitted bits per slot provided in the.." "?,?,?,?,?,Reserved,?,?" newline bitfld.long 0x0 3. "CC,Credit Control When this bit is set the accumulated credit parameter in the credit-based shaper algorithm logic is not reset to zero when there is positive credit and no packet to transmit in Channel 1. The credit accumulates even when there is no.." "Credit Control is disabled,Credit Control is enabled" newline bitfld.long 0x0 2. "AVALG,AV Algorithm When Queue 1 is programmed for AV this field configures the scheduling algorithm for this queue: This bit when set indicates credit based shaper algorithm (CBS) is selected for Queue 1 traffic. When reset strict priority is.." "CBS Algorithm is disabled,CBS Algorithm is enabled" newline rbitfld.long 0x0 0.--1. "RESERVED_1_0,Reserved." "0,1,2,3" rgroup.long 0x14++0x3 line.long 0x0 "MTL_TXQ1_ETS_STATUS,The Queue 1 ETS Status register provides the average traffic transmitted in Queue 1." hexmask.long.byte 0x0 24.--31. 1. "RESERVED_31_24,Reserved." newline hexmask.long.tbyte 0x0 0.--23. 1. "ABS,Average Bits per Slot This field contains the average transmitted bits per slot. If AV operation is enabled this field is computed over number of slots programmed in the SLC field of MTL_TxQ[n]_ETS_CONTROL register. The maximum value of this field.." group.long 0x18++0xF line.long 0x0 "MTL_TXQ1_QUANTUM_WEIGHT,The Queue 1 idleSlopeCredit. Quantum or Weights register provides the average traffic transmitted in Queue 1." hexmask.long.word 0x0 21.--31. 1. "RESERVED_31_21,Reserved." newline hexmask.long.tbyte 0x0 0.--20. 1. "ISCQW,idleSlopeCredit Quantum or Weights - idleSlopeCredit When AV feature is enabled this field contains the idleSlopeCredit value required for the credit-based shaper algorithm for Queue 1. This is the rate of change of credit in bits per cycle (40.." line.long 0x4 "MTL_TXQ1_SENDSLOPECREDIT,The sendSlopeCredit register contains the sendSlope credit value required for the credit-based shaper algorithm for the Queue." hexmask.long.tbyte 0x4 14.--31. 1. "RESERVED_31_14,Reserved." newline hexmask.long.word 0x4 0.--13. 1. "SSC,sendSlopeCredit Value When AV operation is enabled this field contains the sendSlopeCredit value required for credit-based shaper algorithm for Queue 1. This is the rate of change of credit in bits per cycle (40 ns 8 ns and 3.2 ns for 100 Mbps.." line.long 0x8 "MTL_TXQ1_HICREDIT,The hiCredit register contains the hiCredit value required for the credit-based shaper algorithm for the Queue." rbitfld.long 0x8 29.--31. "RESERVED_31_29,Reserved." "0,1,2,3,4,5,6,7" newline hexmask.long 0x8 0.--28. 1. "HC,hiCredit Value When the AV feature is enabled this field contains the hiCredit value required for the credit-based shaper algorithm. This is the maximum value that can be accumulated in the credit parameter. This is specified in bits scaled by 1 024." line.long 0xC "MTL_TXQ1_LOCREDIT,The loCredit register contains the loCredit value required for the credit-based shaper algorithm for the Queue." rbitfld.long 0xC 29.--31. "RESERVED_31_29,Reserved." "0,1,2,3,4,5,6,7" newline hexmask.long 0xC 0.--28. 1. "LC,loCredit Value When AV operation is enabled this field contains the loCredit value required for the credit-based shaper algorithm. This is the minimum value that can be accumulated in the credit parameter. This is specified in bits scaled by 1 024." group.long 0x2C++0x7 line.long 0x0 "MTL_Q1_INTERRUPT_CONTROL_STATUS,This register contains the interrupt enable and status bits for the queue 1 interrupts." hexmask.long.byte 0x0 25.--31. 1. "RESERVED_31_25,Reserved." newline bitfld.long 0x0 24. "RXOIE,Receive Queue Overflow Interrupt Enable When this bit is set the Receive Queue Overflow interrupt is enabled. When this bit is reset the Receive Queue Overflow interrupt is disabled. 0x0: Receive Queue Overflow Interrupt is disabled 0x1: Receive.." "Receive Queue Overflow Interrupt is disabled,Receive Queue Overflow Interrupt is enabled" newline hexmask.long.byte 0x0 17.--23. 1. "RESERVED_23_17,Reserved." newline bitfld.long 0x0 16. "RXOVFIS,Receive Queue Overflow Interrupt Status This bit indicates that the Receive Queue had an overflow while receiving the packet. If a partial packet is transferred to the application the overflow status is set in RDES3[21]. This bit is cleared when.." "Receive Queue Overflow Interrupt Status not..,Receive Queue Overflow Interrupt Status detected" newline hexmask.long.byte 0x0 10.--15. 1. "RESERVED_15_10,Reserved." newline bitfld.long 0x0 9. "ABPSIE,Average Bits Per Slot Interrupt Enable When this bit is set the MAC asserts the sbd_intr_o or mci_intr_o interrupt when the average bits per slot status is updated. When this bit is cleared the interrupt is not asserted for such an event. 0x0:.." "Average Bits Per Slot Interrupt is disabled,Average Bits Per Slot Interrupt is enabled" newline bitfld.long 0x0 8. "TXUIE,Transmit Queue Underflow Interrupt Enable When this bit is set the Transmit Queue Underflow interrupt is enabled. When this bit is reset the Transmit Queue Underflow interrupt is disabled. 0x0: Transmit Queue Underflow Interrupt Status is.." "Transmit Queue Underflow Interrupt Status is..,Transmit Queue Underflow Interrupt Status is.." newline hexmask.long.byte 0x0 2.--7. 1. "RESERVED_7_2,Reserved." newline bitfld.long 0x0 1. "ABPSIS,Average Bits Per Slot Interrupt Status When set this bit indicates that the MAC has updated the ABS value. This bit is cleared when the application writes 1 to this bit. Access restriction applies. Self-set to 1 on internal event. Setting 1.." "Average Bits Per Slot Interrupt Status not..,Average Bits Per Slot Interrupt Status detected" newline bitfld.long 0x0 0. "TXUNFIS,Transmit Queue Underflow Interrupt Status This bit indicates that the Transmit Queue had an underflow while transmitting the packet. Transmission is suspended and an Underflow Error TDES3[2] is set. This bit is cleared when the application writes.." "Transmit Queue Underflow Interrupt Status not..,Transmit Queue Underflow Interrupt Status detected" line.long 0x4 "MTL_RXQ1_OPERATION_MODE,The Queue 1 Receive Operation Mode register establishes the Receive queue operating modes and command. The RFA and RFD fields are not backward compatible with the RFA and RFD fields of 4.00a release" hexmask.long.byte 0x4 25.--31. 1. "RESERVED_31_Y,Reserved." newline hexmask.long.byte 0x4 20.--24. 1. "RQS,Receive Queue Size This field indicates the size of the allocated Receive queues in blocks of 256 bytes. The RQS field is read-write only if the number of Rx Queues more than one the reset value is 0x0 and indicates size of 256 bytes. When the.." newline rbitfld.long 0x4 18.--19. "RESERVED_19_Y,Reserved." "0,1,2,3" newline hexmask.long.byte 0x4 14.--17. 1. "RFD,Threshold for Deactivating Flow Control (in half-duplex and full-duplex modes) These bits control the threshold (fill-level of Rx queue) at which the flow control is de-asserted after activation: - 0: Full minus 1 KB that is FULL 1 KB - 1: Full.." newline rbitfld.long 0x4 12.--13. "RESERVED_13_Y,Reserved." "0,1,2,3" newline hexmask.long.byte 0x4 8.--11. 1. "RFA,Threshold for Activating Flow Control (in half-duplex and full-duplex These bits control the threshold (fill-level of Rx queue) at which the flow control is activated: For more information on encoding for this field see RFD." newline bitfld.long 0x4 7. "EHFC,Enable Hardware Flow Control When this bit is set the flow control signal operation based on the fill-level of Rx queue is enabled. When reset the flow control operation is disabled. 0x0: Hardware Flow Control is disabled 0x1: Hardware Flow.." "Hardware Flow Control is disabled,Hardware Flow Control is enabled" newline bitfld.long 0x4 6. "DIS_TCP_EF,Disable Dropping of TCP/IP Checksum Error Packets When this bit is set the MAC does not drop the packets which only have the errors detected by the Receive Checksum Offload engine. Such packets have errors only in the encapsulated payload." "Dropping of TCP/IP Checksum Error Packets is..,Dropping of TCP/IP Checksum Error Packets is.." newline bitfld.long 0x4 5. "RSF,Receive Queue Store and Forward When this bit is set the DWC_ether_qos reads a packet from the Rx queue only after the complete packet has been written to it ignoring the RTC field of this register. When this bit is reset the Rx queue operates in.." "Receive Queue Store and Forward is disabled,Receive Queue Store and Forward is enabled" newline bitfld.long 0x4 4. "FEP,Forward Error Packets When this bit is reset the Rx queue drops packets with error status (CRC error GMII_ER watchdog timeout or overflow). However if the start byte (write) pointer of a packet is already transferred to the read controller side.." "Forward Error Packets is disabled,Forward Error Packets is enabled" newline bitfld.long 0x4 3. "FUP,Forward Undersized Good Packets When this bit is set the Rx queue forwards the undersized good packets (packets with no error and length less than 64 bytes) including pad-bytes and CRC. When this bit is reset the Rx queue drops all packets of less.." "Forward Undersized Good Packets is disabled,Forward Undersized Good Packets is enabled" newline rbitfld.long 0x4 2. "RESERVED_2,Reserved." "0,1" newline bitfld.long 0x4 0.--1. "RTC,Receive Queue Threshold Control These bits control the threshold level of the MTL Rx queue (in bytes): The received packet is transferred to the application or DMA when the packet size within the MTL Rx queue is larger than the threshold. In addition.." "0,1,2,3" rgroup.long 0x34++0x7 line.long 0x0 "MTL_RXQ1_MISSED_PACKET_OVERFLOW_CNT,The Queue 1 Missed Packet and Overflow Counter register contains the counter for packets missed because of Receive queue packet flush and packets discarded because of Receive queue overflow." hexmask.long.byte 0x0 28.--31. 1. "RESERVED_31_28,Reserved." newline bitfld.long 0x0 27. "MISCNTOVF,Missed Packet Counter Overflow Bit When set this bit indicates that the Rx Queue Missed Packet Counter crossed the maximum limit. Access restriction applies. Clears on read. Self-set to 1 on internal event. 0x1: Missed Packet Counter overflow.." "Missed Packet Counter overflow not detected,Missed Packet Counter overflow detected" newline hexmask.long.word 0x0 16.--26. 1. "MISPKTCNT,Missed Packet Counter This field indicates the number of packets missed by the DWC_ether_qos because the application asserted ari_pkt_flush_i[] for this queue. This counter is reset when this register is read with mci_be_i[0] at 1b1. This.." newline hexmask.long.byte 0x0 12.--15. 1. "RESERVED_15_12,Reserved." newline bitfld.long 0x0 11. "OVFCNTOVF,Overflow Counter Overflow Bit When set this bit indicates that the Rx Queue Overflow Packet Counter field crossed the maximum limit. Access restriction applies. Clears on read. Self-set to 1 on internal event. 0x1: Overflow Counter overflow.." "Overflow Counter overflow not detected,Overflow Counter overflow detected" newline hexmask.long.word 0x0 0.--10. 1. "OVFPKTCNT,Overflow Packet Counter This field indicates the number of packets discarded by the DWC_ether_qos because of Receive queue overflow. This counter is incremented each time the DWC_ether_qos discards an incoming packet because of overflow. This.." line.long 0x4 "MTL_RXQ1_DEBUG,The Queue 1 Receive Debug register gives the debug status of various blocks related to the Receive queue." bitfld.long 0x4 30.--31. "RESERVED_31_30,Reserved." "0,1,2,3" newline hexmask.long.word 0x4 16.--29. 1. "PRXQ,Number of Packets in Receive Queue This field indicates the current number of packets in the Rx Queue. The theoretical maximum value for this field is 256KB/16B = 16K Packets that is Max_Queue_Size/Min_Packet_Size." newline hexmask.long.word 0x4 6.--15. 1. "RESERVED_15_6,Reserved." newline bitfld.long 0x4 4.--5. "RXQSTS,MTL Rx Queue Fill-Level Status This field gives the status of the fill-level of the Rx Queue: 0x2: Rx Queue fill-level above flow-control activate threshold 0x1: Rx Queue fill-level below flow-control deactivate threshold 0x0: Rx Queue empty 0x3:.." "Rx Queue empty,Rx Queue fill-level below flow-control..,Rx Queue fill-level above flow-control activate..,Rx Queue full" newline bitfld.long 0x4 3. "RESERVED_3,Reserved." "0,1" newline bitfld.long 0x4 1.--2. "RRCSTS,MTL Rx Queue Read Controller State This field gives the state of the Rx queue Read controller: 0x3: Flushing the packet data and status 0x0: Idle state 0x1: Reading packet data 0x2: Reading packet status (or timestamp)" "Idle state,Reading packet data,Reading packet status,Flushing the packet data and status" newline bitfld.long 0x4 0. "RWCSTS,MTL Rx Queue Write Controller Active Status When high this bit indicates that the MTL Rx queue Write controller is active and it is transferring a received packet to the Rx Queue. 0x1: MTL Rx Queue Write Controller Active Status detected 0x0:.." "MTL Rx Queue Write Controller Active Status not..,MTL Rx Queue Write Controller Active Status.." group.long 0x3C++0x3 line.long 0x0 "MTL_RXQ1_CONTROL,The Queue Receive Control register controls the receive arbitration and passing of received packets to the application." hexmask.long 0x0 4.--31. 1. "RESERVED_31_4,Reserved." newline bitfld.long 0x0 3. "RXQ_FRM_ARBIT,Receive Queue Packet Arbitration When this bit is set the DWC_ether_qos drives the packet data to the ARI interface such that the entire packet data of currently-selected queue is transmitted before switching to other queue. When this bit.." "Receive Queue Packet Arbitration is disabled,Receive Queue Packet Arbitration is enabled" newline bitfld.long 0x0 0.--2. "RXQ_WEGT,Receive Queue Weight This field indicates the weight assigned to the Rx Queue 0. The weight is used as the number of continuous PBL or packets requests (depending on the RXQ_FRM_ARBIT) allocated to the queue in one arbitration cycle." "0,1,2,3,4,5,6,7" tree.end tree "EQOS_MTL_Q2" group.long 0x0++0x3 line.long 0x0 "MTL_TXQ2_OPERATION_MODE,The Queue 2 Transmit Operation Mode register establishes the Transmit queue operating modes and commands." hexmask.long.word 0x0 21.--31. 1. "RESERVED_31_Y,Reserved." newline hexmask.long.byte 0x0 16.--20. 1. "TQS,Transmit Queue Size This field indicates the size of the allocated Transmit queues in blocks of 256 bytes. The TQS field is read-write only if the number of Tx Queues more than one the reset value is 0x0 and indicates size of 256 bytes. When the.." newline hexmask.long.word 0x0 7.--15. 1. "RESERVED_15_7,Reserved." newline bitfld.long 0x0 4.--6. "TTC,Transmit Threshold Control These bits control the threshold level of the MTL Tx Queue. The transmission starts when the packet size within the MTL Tx Queue is larger than the threshold. In addition full packets with length less than the threshold.." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 2.--3. "TXQEN,Transmit Queue Enable This field is used to enable/disable the transmit queue 0. - 2'b00: Not enabled - 2'b01: Enable in AV mode - 2'b10: Enabled - 2'b11: Reserved Note: In multiple Tx queues configuration all the queues are disabled by default." "Not enabled,Enable in AV mode,Enabled,Reserved" newline bitfld.long 0x0 1. "TSF,Transmit Store and Forward When this bit is set the transmission starts when a full packet resides in the MTL Tx queue. When this bit is set the TTC values specified in Bits[6:4] of this register are ignored. This bit should be changed only when.." "Transmit Store and Forward is disabled,Transmit Store and Forward is enabled" newline bitfld.long 0x0 0. "FTQ,Flush Transmit Queue When this bit is set the Tx queue controller logic is reset to its default values. Therefore all the data in the Tx queue is lost or flushed. This bit is internally reset when the flushing operation is complete. Until this bit.." "Flush Transmit Queue is disabled,Flush Transmit Queue is enabled" rgroup.long 0x4++0x7 line.long 0x0 "MTL_TXQ2_UNDERFLOW,The Queue 2 Underflow Counter register contains the counter for packets aborted because of Transmit queue underflow and packets missed because of Receive queue packet flush" hexmask.long.tbyte 0x0 12.--31. 1. "RESERVED_31_12,Reserved." newline bitfld.long 0x0 11. "UFCNTOVF,Overflow Bit for Underflow Packet Counter This bit is set every time the Tx queue Underflow Packet Counter field overflows that is it has crossed the maximum count. In such a scenario the overflow packet counter is reset to all-zeros and this.." "Overflow not detected for Underflow Packet Counter,Overflow detected for Underflow Packet Counter" newline hexmask.long.word 0x0 0.--10. 1. "UFFRMCNT,Underflow Packet Counter This field indicates the number of packets aborted by the controller because of Tx Queue Underflow. This counter is incremented each time the MAC aborts outgoing packet because of underflow. The counter is cleared when.." line.long 0x4 "MTL_TXQ2_DEBUG,The Queue 2 Transmit Debug register gives the debug status of various blocks related to the Transmit queue." hexmask.long.word 0x4 23.--31. 1. "RESERVED_31_23,Reserved." newline bitfld.long 0x4 20.--22. "STXSTSF,Number of Status Words in Tx Status FIFO of Queue This field indicates the current number of status in the Tx Status FIFO of this queue. When the DTXSTS bit of MTL_Operation_Mode register is set to 1 this field does not reflect the number of.." "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 19. "RESERVED_19,Reserved." "0,1" newline bitfld.long 0x4 16.--18. "PTXQ,Number of Packets in the Transmit Queue This field indicates the current number of packets in the Tx Queue. When the DTXSTS bit of MTL_Operation_Mode register is set to 1 this field does not reflect the number of packets in the Transmit queue." "0,1,2,3,4,5,6,7" newline hexmask.long.word 0x4 6.--15. 1. "RESERVED_15_6,Reserved." newline bitfld.long 0x4 5. "TXSTSFSTS,MTL Tx Status FIFO Full Status When high this bit indicates that the MTL Tx Status FIFO is full. Therefore the MTL cannot accept any more packets for transmission. 0x1: MTL Tx Status FIFO Full status is detected 0x0: MTL Tx Status FIFO Full.." "MTL Tx Status FIFO Full status is not detected,MTL Tx Status FIFO Full status is detected" newline bitfld.long 0x4 4. "TXQSTS,MTL Tx Queue Not Empty Status When this bit is high it indicates that the MTL Tx Queue is not empty and some data is left for transmission. 0x1: MTL Tx Queue Not Empty status is detected 0x0: MTL Tx Queue Not Empty status is not detected" "MTL Tx Queue Not Empty status is not detected,MTL Tx Queue Not Empty status is detected" newline bitfld.long 0x4 3. "TWCSTS,MTL Tx Queue Write Controller Status When high this bit indicates that the MTL Tx Queue Write Controller is active and it is transferring the data to the Tx Queue. 0x1: MTL Tx Queue Write Controller status is detected 0x0: MTL Tx Queue Write.." "MTL Tx Queue Write Controller status is not..,MTL Tx Queue Write Controller status is detected" newline bitfld.long 0x4 1.--2. "TRCSTS,MTL Tx Queue Read Controller Status This field indicates the state of the Tx Queue Read Controller: 0x3: Flushing the Tx queue because of the Packet Abort request from the MAC 0x0: Idle state 0x1: Read state (transferring data to the MAC.." "Idle state,Read state,Waiting for pending Tx Status from the MAC..,Flushing the Tx queue because of the Packet.." newline bitfld.long 0x4 0. "TXQPAUSED,Transmit Queue in Pause When this bit is high and the Rx flow control is enabled it indicates that the Tx Queue is in the Pause condition (in the full-duplex only mode) because of the following: - Reception of the PFC packet for the priorities.." "Transmit Queue in Pause status is not detected,Transmit Queue in Pause status is detected" group.long 0x10++0x3 line.long 0x0 "MTL_TXQ2_ETS_CONTROL,The Queue ETS Control register controls the enhanced transmission selection operation." hexmask.long 0x0 7.--31. 1. "RESERVED_31_7,Reserved." newline bitfld.long 0x0 4.--6. "SLC,Slot Count If the credit-based shaper algorithm is enabled the software can program the number of slots (of duration programmed in DMA_CH[n]_Slot_Interval register) over which the average transmitted bits per slot provided in the.." "?,?,?,?,?,Reserved,?,?" newline bitfld.long 0x0 3. "CC,Credit Control When this bit is set the accumulated credit parameter in the credit-based shaper algorithm logic is not reset to zero when there is positive credit and no packet to transmit in Channel 1. The credit accumulates even when there is no.." "Credit Control is disabled,Credit Control is enabled" newline bitfld.long 0x0 2. "AVALG,AV Algorithm When Queue 1 is programmed for AV this field configures the scheduling algorithm for this queue: This bit when set indicates credit based shaper algorithm (CBS) is selected for Queue 1 traffic. When reset strict priority is.." "CBS Algorithm is disabled,CBS Algorithm is enabled" newline rbitfld.long 0x0 0.--1. "RESERVED_1_0,Reserved." "0,1,2,3" rgroup.long 0x14++0x3 line.long 0x0 "MTL_TXQ2_ETS_STATUS,The Queue 2 ETS Status register provides the average traffic transmitted in Queue 2." hexmask.long.byte 0x0 24.--31. 1. "RESERVED_31_24,Reserved." newline hexmask.long.tbyte 0x0 0.--23. 1. "ABS,Average Bits per Slot This field contains the average transmitted bits per slot. If AV operation is enabled this field is computed over number of slots programmed in the SLC field of MTL_TxQ[n]_ETS_CONTROL register. The maximum value of this field.." group.long 0x18++0xF line.long 0x0 "MTL_TXQ2_QUANTUM_WEIGHT,The Queue 2 idleSlopeCredit. Quantum or Weights register provides the average traffic transmitted in Queue 2." hexmask.long.word 0x0 21.--31. 1. "RESERVED_31_21,Reserved." newline hexmask.long.tbyte 0x0 0.--20. 1. "ISCQW,idleSlopeCredit Quantum or Weights - idleSlopeCredit When AV feature is enabled this field contains the idleSlopeCredit value required for the credit-based shaper algorithm for Queue 1. This is the rate of change of credit in bits per cycle (40.." line.long 0x4 "MTL_TXQ2_SENDSLOPECREDIT,The sendSlopeCredit register contains the sendSlope credit value required for the credit-based shaper algorithm for the Queue." hexmask.long.tbyte 0x4 14.--31. 1. "RESERVED_31_14,Reserved." newline hexmask.long.word 0x4 0.--13. 1. "SSC,sendSlopeCredit Value When AV operation is enabled this field contains the sendSlopeCredit value required for credit-based shaper algorithm for Queue 1. This is the rate of change of credit in bits per cycle (40 ns 8 ns and 3.2 ns for 100 Mbps.." line.long 0x8 "MTL_TXQ2_HICREDIT,The hiCredit register contains the hiCredit value required for the credit-based shaper algorithm for the Queue." rbitfld.long 0x8 29.--31. "RESERVED_31_29,Reserved." "0,1,2,3,4,5,6,7" newline hexmask.long 0x8 0.--28. 1. "HC,hiCredit Value When the AV feature is enabled this field contains the hiCredit value required for the credit-based shaper algorithm. This is the maximum value that can be accumulated in the credit parameter. This is specified in bits scaled by 1 024." line.long 0xC "MTL_TXQ2_LOCREDIT,The loCredit register contains the loCredit value required for the credit-based shaper algorithm for the Queue." rbitfld.long 0xC 29.--31. "RESERVED_31_29,Reserved." "0,1,2,3,4,5,6,7" newline hexmask.long 0xC 0.--28. 1. "LC,loCredit Value When AV operation is enabled this field contains the loCredit value required for the credit-based shaper algorithm. This is the minimum value that can be accumulated in the credit parameter. This is specified in bits scaled by 1 024." group.long 0x2C++0x7 line.long 0x0 "MTL_Q2_INTERRUPT_CONTROL_STATUS,This register contains the interrupt enable and status bits for the queue 2 interrupts." hexmask.long.byte 0x0 25.--31. 1. "RESERVED_31_25,Reserved." newline bitfld.long 0x0 24. "RXOIE,Receive Queue Overflow Interrupt Enable When this bit is set the Receive Queue Overflow interrupt is enabled. When this bit is reset the Receive Queue Overflow interrupt is disabled. 0x0: Receive Queue Overflow Interrupt is disabled 0x1: Receive.." "Receive Queue Overflow Interrupt is disabled,Receive Queue Overflow Interrupt is enabled" newline hexmask.long.byte 0x0 17.--23. 1. "RESERVED_23_17,Reserved." newline bitfld.long 0x0 16. "RXOVFIS,Receive Queue Overflow Interrupt Status This bit indicates that the Receive Queue had an overflow while receiving the packet. If a partial packet is transferred to the application the overflow status is set in RDES3[21]. This bit is cleared when.." "Receive Queue Overflow Interrupt Status not..,Receive Queue Overflow Interrupt Status detected" newline hexmask.long.byte 0x0 10.--15. 1. "RESERVED_15_10,Reserved." newline bitfld.long 0x0 9. "ABPSIE,Average Bits Per Slot Interrupt Enable When this bit is set the MAC asserts the sbd_intr_o or mci_intr_o interrupt when the average bits per slot status is updated. When this bit is cleared the interrupt is not asserted for such an event. 0x0:.." "Average Bits Per Slot Interrupt is disabled,Average Bits Per Slot Interrupt is enabled" newline bitfld.long 0x0 8. "TXUIE,Transmit Queue Underflow Interrupt Enable When this bit is set the Transmit Queue Underflow interrupt is enabled. When this bit is reset the Transmit Queue Underflow interrupt is disabled. 0x0: Transmit Queue Underflow Interrupt Status is.." "Transmit Queue Underflow Interrupt Status is..,Transmit Queue Underflow Interrupt Status is.." newline hexmask.long.byte 0x0 2.--7. 1. "RESERVED_7_2,Reserved." newline bitfld.long 0x0 1. "ABPSIS,Average Bits Per Slot Interrupt Status When set this bit indicates that the MAC has updated the ABS value. This bit is cleared when the application writes 1 to this bit. Access restriction applies. Self-set to 1 on internal event. Setting 1.." "Average Bits Per Slot Interrupt Status not..,Average Bits Per Slot Interrupt Status detected" newline bitfld.long 0x0 0. "TXUNFIS,Transmit Queue Underflow Interrupt Status This bit indicates that the Transmit Queue had an underflow while transmitting the packet. Transmission is suspended and an Underflow Error TDES3[2] is set. This bit is cleared when the application writes.." "Transmit Queue Underflow Interrupt Status not..,Transmit Queue Underflow Interrupt Status detected" line.long 0x4 "MTL_RXQ2_OPERATION_MODE,The Queue 2 Receive Operation Mode register establishes the Receive queue operating modes and command. The RFA and RFD fields are not backward compatible with the RFA and RFD fields of 4.00a release" hexmask.long.byte 0x4 25.--31. 1. "RESERVED_31_Y,Reserved." newline hexmask.long.byte 0x4 20.--24. 1. "RQS,Receive Queue Size This field indicates the size of the allocated Receive queues in blocks of 256 bytes. The RQS field is read-write only if the number of Rx Queues more than one the reset value is 0x0 and indicates size of 256 bytes. When the.." newline rbitfld.long 0x4 18.--19. "RESERVED_19_Y,Reserved." "0,1,2,3" newline hexmask.long.byte 0x4 14.--17. 1. "RFD,Threshold for Deactivating Flow Control (in half-duplex and full-duplex modes) These bits control the threshold (fill-level of Rx queue) at which the flow control is de-asserted after activation: - 0: Full minus 1 KB that is FULL 1 KB - 1: Full.." newline rbitfld.long 0x4 12.--13. "RESERVED_13_Y,Reserved." "0,1,2,3" newline hexmask.long.byte 0x4 8.--11. 1. "RFA,Threshold for Activating Flow Control (in half-duplex and full-duplex These bits control the threshold (fill-level of Rx queue) at which the flow control is activated: For more information on encoding for this field see RFD." newline bitfld.long 0x4 7. "EHFC,Enable Hardware Flow Control When this bit is set the flow control signal operation based on the fill-level of Rx queue is enabled. When reset the flow control operation is disabled. 0x0: Hardware Flow Control is disabled 0x1: Hardware Flow.." "Hardware Flow Control is disabled,Hardware Flow Control is enabled" newline bitfld.long 0x4 6. "DIS_TCP_EF,Disable Dropping of TCP/IP Checksum Error Packets When this bit is set the MAC does not drop the packets which only have the errors detected by the Receive Checksum Offload engine. Such packets have errors only in the encapsulated payload." "Dropping of TCP/IP Checksum Error Packets is..,Dropping of TCP/IP Checksum Error Packets is.." newline bitfld.long 0x4 5. "RSF,Receive Queue Store and Forward When this bit is set the DWC_ether_qos reads a packet from the Rx queue only after the complete packet has been written to it ignoring the RTC field of this register. When this bit is reset the Rx queue operates in.." "Receive Queue Store and Forward is disabled,Receive Queue Store and Forward is enabled" newline bitfld.long 0x4 4. "FEP,Forward Error Packets When this bit is reset the Rx queue drops packets with error status (CRC error GMII_ER watchdog timeout or overflow). However if the start byte (write) pointer of a packet is already transferred to the read controller side.." "Forward Error Packets is disabled,Forward Error Packets is enabled" newline bitfld.long 0x4 3. "FUP,Forward Undersized Good Packets When this bit is set the Rx queue forwards the undersized good packets (packets with no error and length less than 64 bytes) including pad-bytes and CRC. When this bit is reset the Rx queue drops all packets of less.." "Forward Undersized Good Packets is disabled,Forward Undersized Good Packets is enabled" newline rbitfld.long 0x4 2. "RESERVED_2,Reserved." "0,1" newline bitfld.long 0x4 0.--1. "RTC,Receive Queue Threshold Control These bits control the threshold level of the MTL Rx queue (in bytes): The received packet is transferred to the application or DMA when the packet size within the MTL Rx queue is larger than the threshold. In addition.." "0,1,2,3" rgroup.long 0x34++0x7 line.long 0x0 "MTL_RXQ2_MISSED_PACKET_OVERFLOW_CNT,The Queue 2 Missed Packet and Overflow Counter register contains the counter for packets missed because of Receive queue packet flush and packets discarded because of Receive queue overflow." hexmask.long.byte 0x0 28.--31. 1. "RESERVED_31_28,Reserved." newline bitfld.long 0x0 27. "MISCNTOVF,Missed Packet Counter Overflow Bit When set this bit indicates that the Rx Queue Missed Packet Counter crossed the maximum limit. Access restriction applies. Clears on read. Self-set to 1 on internal event. 0x1: Missed Packet Counter overflow.." "Missed Packet Counter overflow not detected,Missed Packet Counter overflow detected" newline hexmask.long.word 0x0 16.--26. 1. "MISPKTCNT,Missed Packet Counter This field indicates the number of packets missed by the DWC_ether_qos because the application asserted ari_pkt_flush_i[] for this queue. This counter is reset when this register is read with mci_be_i[0] at 1b1. This.." newline hexmask.long.byte 0x0 12.--15. 1. "RESERVED_15_12,Reserved." newline bitfld.long 0x0 11. "OVFCNTOVF,Overflow Counter Overflow Bit When set this bit indicates that the Rx Queue Overflow Packet Counter field crossed the maximum limit. Access restriction applies. Clears on read. Self-set to 1 on internal event. 0x1: Overflow Counter overflow.." "Overflow Counter overflow not detected,Overflow Counter overflow detected" newline hexmask.long.word 0x0 0.--10. 1. "OVFPKTCNT,Overflow Packet Counter This field indicates the number of packets discarded by the DWC_ether_qos because of Receive queue overflow. This counter is incremented each time the DWC_ether_qos discards an incoming packet because of overflow. This.." line.long 0x4 "MTL_RXQ2_DEBUG,The Queue 2 Receive Debug register gives the debug status of various blocks related to the Receive queue." bitfld.long 0x4 30.--31. "RESERVED_31_30,Reserved." "0,1,2,3" newline hexmask.long.word 0x4 16.--29. 1. "PRXQ,Number of Packets in Receive Queue This field indicates the current number of packets in the Rx Queue. The theoretical maximum value for this field is 256KB/16B = 16K Packets that is Max_Queue_Size/Min_Packet_Size." newline hexmask.long.word 0x4 6.--15. 1. "RESERVED_15_6,Reserved." newline bitfld.long 0x4 4.--5. "RXQSTS,MTL Rx Queue Fill-Level Status This field gives the status of the fill-level of the Rx Queue: 0x2: Rx Queue fill-level above flow-control activate threshold 0x1: Rx Queue fill-level below flow-control deactivate threshold 0x0: Rx Queue empty 0x3:.." "Rx Queue empty,Rx Queue fill-level below flow-control..,Rx Queue fill-level above flow-control activate..,Rx Queue full" newline bitfld.long 0x4 3. "RESERVED_3,Reserved." "0,1" newline bitfld.long 0x4 1.--2. "RRCSTS,MTL Rx Queue Read Controller State This field gives the state of the Rx queue Read controller: 0x3: Flushing the packet data and status 0x0: Idle state 0x1: Reading packet data 0x2: Reading packet status (or timestamp)" "Idle state,Reading packet data,Reading packet status,Flushing the packet data and status" newline bitfld.long 0x4 0. "RWCSTS,MTL Rx Queue Write Controller Active Status When high this bit indicates that the MTL Rx queue Write controller is active and it is transferring a received packet to the Rx Queue. 0x1: MTL Rx Queue Write Controller Active Status detected 0x0:.." "MTL Rx Queue Write Controller Active Status not..,MTL Rx Queue Write Controller Active Status.." group.long 0x3C++0x3 line.long 0x0 "MTL_RXQ2_CONTROL,The Queue Receive Control register controls the receive arbitration and passing of received packets to the application." hexmask.long 0x0 4.--31. 1. "RESERVED_31_4,Reserved." newline bitfld.long 0x0 3. "RXQ_FRM_ARBIT,Receive Queue Packet Arbitration When this bit is set the DWC_ether_qos drives the packet data to the ARI interface such that the entire packet data of currently-selected queue is transmitted before switching to other queue. When this bit.." "Receive Queue Packet Arbitration is disabled,Receive Queue Packet Arbitration is enabled" newline bitfld.long 0x0 0.--2. "RXQ_WEGT,Receive Queue Weight This field indicates the weight assigned to the Rx Queue 0. The weight is used as the number of continuous PBL or packets requests (depending on the RXQ_FRM_ARBIT) allocated to the queue in one arbitration cycle." "0,1,2,3,4,5,6,7" tree.end tree "EQOS_MTL_Q3" group.long 0x0++0x3 line.long 0x0 "MTL_TXQ3_OPERATION_MODE,The Queue 3 Transmit Operation Mode register establishes the Transmit queue operating modes and commands." hexmask.long.word 0x0 21.--31. 1. "RESERVED_31_Y,Reserved." newline hexmask.long.byte 0x0 16.--20. 1. "TQS,Transmit Queue Size This field indicates the size of the allocated Transmit queues in blocks of 256 bytes. The TQS field is read-write only if the number of Tx Queues more than one the reset value is 0x0 and indicates size of 256 bytes. When the.." newline hexmask.long.word 0x0 7.--15. 1. "RESERVED_15_7,Reserved." newline bitfld.long 0x0 4.--6. "TTC,Transmit Threshold Control These bits control the threshold level of the MTL Tx Queue. The transmission starts when the packet size within the MTL Tx Queue is larger than the threshold. In addition full packets with length less than the threshold.." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 2.--3. "TXQEN,Transmit Queue Enable This field is used to enable/disable the transmit queue 0. - 2'b00: Not enabled - 2'b01: Enable in AV mode - 2'b10: Enabled - 2'b11: Reserved Note: In multiple Tx queues configuration all the queues are disabled by default." "Not enabled,Enable in AV mode,Enabled,Reserved" newline bitfld.long 0x0 1. "TSF,Transmit Store and Forward When this bit is set the transmission starts when a full packet resides in the MTL Tx queue. When this bit is set the TTC values specified in Bits[6:4] of this register are ignored. This bit should be changed only when.." "Transmit Store and Forward is disabled,Transmit Store and Forward is enabled" newline bitfld.long 0x0 0. "FTQ,Flush Transmit Queue When this bit is set the Tx queue controller logic is reset to its default values. Therefore all the data in the Tx queue is lost or flushed. This bit is internally reset when the flushing operation is complete. Until this bit.." "Flush Transmit Queue is disabled,Flush Transmit Queue is enabled" rgroup.long 0x4++0x7 line.long 0x0 "MTL_TXQ3_UNDERFLOW,The Queue 3 Underflow Counter register contains the counter for packets aborted because of Transmit queue underflow and packets missed because of Receive queue packet flush" hexmask.long.tbyte 0x0 12.--31. 1. "RESERVED_31_12,Reserved." newline bitfld.long 0x0 11. "UFCNTOVF,Overflow Bit for Underflow Packet Counter This bit is set every time the Tx queue Underflow Packet Counter field overflows that is it has crossed the maximum count. In such a scenario the overflow packet counter is reset to all-zeros and this.." "Overflow not detected for Underflow Packet Counter,Overflow detected for Underflow Packet Counter" newline hexmask.long.word 0x0 0.--10. 1. "UFFRMCNT,Underflow Packet Counter This field indicates the number of packets aborted by the controller because of Tx Queue Underflow. This counter is incremented each time the MAC aborts outgoing packet because of underflow. The counter is cleared when.." line.long 0x4 "MTL_TXQ3_DEBUG,The Queue 3 Transmit Debug register gives the debug status of various blocks related to the Transmit queue." hexmask.long.word 0x4 23.--31. 1. "RESERVED_31_23,Reserved." newline bitfld.long 0x4 20.--22. "STXSTSF,Number of Status Words in Tx Status FIFO of Queue This field indicates the current number of status in the Tx Status FIFO of this queue. When the DTXSTS bit of MTL_Operation_Mode register is set to 1 this field does not reflect the number of.." "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 19. "RESERVED_19,Reserved." "0,1" newline bitfld.long 0x4 16.--18. "PTXQ,Number of Packets in the Transmit Queue This field indicates the current number of packets in the Tx Queue. When the DTXSTS bit of MTL_Operation_Mode register is set to 1 this field does not reflect the number of packets in the Transmit queue." "0,1,2,3,4,5,6,7" newline hexmask.long.word 0x4 6.--15. 1. "RESERVED_15_6,Reserved." newline bitfld.long 0x4 5. "TXSTSFSTS,MTL Tx Status FIFO Full Status When high this bit indicates that the MTL Tx Status FIFO is full. Therefore the MTL cannot accept any more packets for transmission. 0x1: MTL Tx Status FIFO Full status is detected 0x0: MTL Tx Status FIFO Full.." "MTL Tx Status FIFO Full status is not detected,MTL Tx Status FIFO Full status is detected" newline bitfld.long 0x4 4. "TXQSTS,MTL Tx Queue Not Empty Status When this bit is high it indicates that the MTL Tx Queue is not empty and some data is left for transmission. 0x1: MTL Tx Queue Not Empty status is detected 0x0: MTL Tx Queue Not Empty status is not detected" "MTL Tx Queue Not Empty status is not detected,MTL Tx Queue Not Empty status is detected" newline bitfld.long 0x4 3. "TWCSTS,MTL Tx Queue Write Controller Status When high this bit indicates that the MTL Tx Queue Write Controller is active and it is transferring the data to the Tx Queue. 0x1: MTL Tx Queue Write Controller status is detected 0x0: MTL Tx Queue Write.." "MTL Tx Queue Write Controller status is not..,MTL Tx Queue Write Controller status is detected" newline bitfld.long 0x4 1.--2. "TRCSTS,MTL Tx Queue Read Controller Status This field indicates the state of the Tx Queue Read Controller: 0x3: Flushing the Tx queue because of the Packet Abort request from the MAC 0x0: Idle state 0x1: Read state (transferring data to the MAC.." "Idle state,Read state,Waiting for pending Tx Status from the MAC..,Flushing the Tx queue because of the Packet.." newline bitfld.long 0x4 0. "TXQPAUSED,Transmit Queue in Pause When this bit is high and the Rx flow control is enabled it indicates that the Tx Queue is in the Pause condition (in the full-duplex only mode) because of the following: - Reception of the PFC packet for the priorities.." "Transmit Queue in Pause status is not detected,Transmit Queue in Pause status is detected" group.long 0x10++0x3 line.long 0x0 "MTL_TXQ3_ETS_CONTROL,The Queue ETS Control register controls the enhanced transmission selection operation." hexmask.long 0x0 7.--31. 1. "RESERVED_31_7,Reserved." newline bitfld.long 0x0 4.--6. "SLC,Slot Count If the credit-based shaper algorithm is enabled the software can program the number of slots (of duration programmed in DMA_CH[n]_Slot_Interval register) over which the average transmitted bits per slot provided in the.." "?,?,?,?,?,Reserved,?,?" newline bitfld.long 0x0 3. "CC,Credit Control When this bit is set the accumulated credit parameter in the credit-based shaper algorithm logic is not reset to zero when there is positive credit and no packet to transmit in Channel 1. The credit accumulates even when there is no.." "Credit Control is disabled,Credit Control is enabled" newline bitfld.long 0x0 2. "AVALG,AV Algorithm When Queue 1 is programmed for AV this field configures the scheduling algorithm for this queue: This bit when set indicates credit based shaper algorithm (CBS) is selected for Queue 1 traffic. When reset strict priority is.." "CBS Algorithm is disabled,CBS Algorithm is enabled" newline rbitfld.long 0x0 0.--1. "RESERVED_1_0,Reserved." "0,1,2,3" rgroup.long 0x14++0x3 line.long 0x0 "MTL_TXQ3_ETS_STATUS,The Queue 3 ETS Status register provides the average traffic transmitted in Queue 3." hexmask.long.byte 0x0 24.--31. 1. "RESERVED_31_24,Reserved." newline hexmask.long.tbyte 0x0 0.--23. 1. "ABS,Average Bits per Slot This field contains the average transmitted bits per slot. If AV operation is enabled this field is computed over number of slots programmed in the SLC field of MTL_TxQ[n]_ETS_CONTROL register. The maximum value of this field.." group.long 0x18++0xF line.long 0x0 "MTL_TXQ3_QUANTUM_WEIGHT,The Queue 3 idleSlopeCredit. Quantum or Weights register provides the average traffic transmitted in Queue 3." hexmask.long.word 0x0 21.--31. 1. "RESERVED_31_21,Reserved." newline hexmask.long.tbyte 0x0 0.--20. 1. "ISCQW,idleSlopeCredit Quantum or Weights - idleSlopeCredit When AV feature is enabled this field contains the idleSlopeCredit value required for the credit-based shaper algorithm for Queue 1. This is the rate of change of credit in bits per cycle (40.." line.long 0x4 "MTL_TXQ3_SENDSLOPECREDIT,The sendSlopeCredit register contains the sendSlope credit value required for the credit-based shaper algorithm for the Queue." hexmask.long.tbyte 0x4 14.--31. 1. "RESERVED_31_14,Reserved." newline hexmask.long.word 0x4 0.--13. 1. "SSC,sendSlopeCredit Value When AV operation is enabled this field contains the sendSlopeCredit value required for credit-based shaper algorithm for Queue 1. This is the rate of change of credit in bits per cycle (40 ns 8 ns and 3.2 ns for 100 Mbps.." line.long 0x8 "MTL_TXQ3_HICREDIT,The hiCredit register contains the hiCredit value required for the credit-based shaper algorithm for the Queue." rbitfld.long 0x8 29.--31. "RESERVED_31_29,Reserved." "0,1,2,3,4,5,6,7" newline hexmask.long 0x8 0.--28. 1. "HC,hiCredit Value When the AV feature is enabled this field contains the hiCredit value required for the credit-based shaper algorithm. This is the maximum value that can be accumulated in the credit parameter. This is specified in bits scaled by 1 024." line.long 0xC "MTL_TXQ3_LOCREDIT,The loCredit register contains the loCredit value required for the credit-based shaper algorithm for the Queue." rbitfld.long 0xC 29.--31. "RESERVED_31_29,Reserved." "0,1,2,3,4,5,6,7" newline hexmask.long 0xC 0.--28. 1. "LC,loCredit Value When AV operation is enabled this field contains the loCredit value required for the credit-based shaper algorithm. This is the minimum value that can be accumulated in the credit parameter. This is specified in bits scaled by 1 024." group.long 0x2C++0x7 line.long 0x0 "MTL_Q3_INTERRUPT_CONTROL_STATUS,This register contains the interrupt enable and status bits for the queue 3 interrupts." hexmask.long.byte 0x0 25.--31. 1. "RESERVED_31_25,Reserved." newline bitfld.long 0x0 24. "RXOIE,Receive Queue Overflow Interrupt Enable When this bit is set the Receive Queue Overflow interrupt is enabled. When this bit is reset the Receive Queue Overflow interrupt is disabled. 0x0: Receive Queue Overflow Interrupt is disabled 0x1: Receive.." "Receive Queue Overflow Interrupt is disabled,Receive Queue Overflow Interrupt is enabled" newline hexmask.long.byte 0x0 17.--23. 1. "RESERVED_23_17,Reserved." newline bitfld.long 0x0 16. "RXOVFIS,Receive Queue Overflow Interrupt Status This bit indicates that the Receive Queue had an overflow while receiving the packet. If a partial packet is transferred to the application the overflow status is set in RDES3[21]. This bit is cleared when.." "Receive Queue Overflow Interrupt Status not..,Receive Queue Overflow Interrupt Status detected" newline hexmask.long.byte 0x0 10.--15. 1. "RESERVED_15_10,Reserved." newline bitfld.long 0x0 9. "ABPSIE,Average Bits Per Slot Interrupt Enable When this bit is set the MAC asserts the sbd_intr_o or mci_intr_o interrupt when the average bits per slot status is updated. When this bit is cleared the interrupt is not asserted for such an event. 0x0:.." "Average Bits Per Slot Interrupt is disabled,Average Bits Per Slot Interrupt is enabled" newline bitfld.long 0x0 8. "TXUIE,Transmit Queue Underflow Interrupt Enable When this bit is set the Transmit Queue Underflow interrupt is enabled. When this bit is reset the Transmit Queue Underflow interrupt is disabled. 0x0: Transmit Queue Underflow Interrupt Status is.." "Transmit Queue Underflow Interrupt Status is..,Transmit Queue Underflow Interrupt Status is.." newline hexmask.long.byte 0x0 2.--7. 1. "RESERVED_7_2,Reserved." newline bitfld.long 0x0 1. "ABPSIS,Average Bits Per Slot Interrupt Status When set this bit indicates that the MAC has updated the ABS value. This bit is cleared when the application writes 1 to this bit. Access restriction applies. Self-set to 1 on internal event. Setting 1.." "Average Bits Per Slot Interrupt Status not..,Average Bits Per Slot Interrupt Status detected" newline bitfld.long 0x0 0. "TXUNFIS,Transmit Queue Underflow Interrupt Status This bit indicates that the Transmit Queue had an underflow while transmitting the packet. Transmission is suspended and an Underflow Error TDES3[2] is set. This bit is cleared when the application writes.." "Transmit Queue Underflow Interrupt Status not..,Transmit Queue Underflow Interrupt Status detected" line.long 0x4 "MTL_RXQ3_OPERATION_MODE,The Queue 3 Receive Operation Mode register establishes the Receive queue operating modes and command. The RFA and RFD fields are not backward compatible with the RFA and RFD fields of 4.00a release" hexmask.long.byte 0x4 25.--31. 1. "RESERVED_31_Y,Reserved." newline hexmask.long.byte 0x4 20.--24. 1. "RQS,Receive Queue Size This field indicates the size of the allocated Receive queues in blocks of 256 bytes. The RQS field is read-write only if the number of Rx Queues more than one the reset value is 0x0 and indicates size of 256 bytes. When the.." newline rbitfld.long 0x4 18.--19. "RESERVED_19_Y,Reserved." "0,1,2,3" newline hexmask.long.byte 0x4 14.--17. 1. "RFD,Threshold for Deactivating Flow Control (in half-duplex and full-duplex modes) These bits control the threshold (fill-level of Rx queue) at which the flow control is de-asserted after activation: - 0: Full minus 1 KB that is FULL 1 KB - 1: Full.." newline rbitfld.long 0x4 12.--13. "RESERVED_13_Y,Reserved." "0,1,2,3" newline hexmask.long.byte 0x4 8.--11. 1. "RFA,Threshold for Activating Flow Control (in half-duplex and full-duplex These bits control the threshold (fill-level of Rx queue) at which the flow control is activated: For more information on encoding for this field see RFD." newline bitfld.long 0x4 7. "EHFC,Enable Hardware Flow Control When this bit is set the flow control signal operation based on the fill-level of Rx queue is enabled. When reset the flow control operation is disabled. 0x0: Hardware Flow Control is disabled 0x1: Hardware Flow.." "Hardware Flow Control is disabled,Hardware Flow Control is enabled" newline bitfld.long 0x4 6. "DIS_TCP_EF,Disable Dropping of TCP/IP Checksum Error Packets When this bit is set the MAC does not drop the packets which only have the errors detected by the Receive Checksum Offload engine. Such packets have errors only in the encapsulated payload." "Dropping of TCP/IP Checksum Error Packets is..,Dropping of TCP/IP Checksum Error Packets is.." newline bitfld.long 0x4 5. "RSF,Receive Queue Store and Forward When this bit is set the DWC_ether_qos reads a packet from the Rx queue only after the complete packet has been written to it ignoring the RTC field of this register. When this bit is reset the Rx queue operates in.." "Receive Queue Store and Forward is disabled,Receive Queue Store and Forward is enabled" newline bitfld.long 0x4 4. "FEP,Forward Error Packets When this bit is reset the Rx queue drops packets with error status (CRC error GMII_ER watchdog timeout or overflow). However if the start byte (write) pointer of a packet is already transferred to the read controller side.." "Forward Error Packets is disabled,Forward Error Packets is enabled" newline bitfld.long 0x4 3. "FUP,Forward Undersized Good Packets When this bit is set the Rx queue forwards the undersized good packets (packets with no error and length less than 64 bytes) including pad-bytes and CRC. When this bit is reset the Rx queue drops all packets of less.." "Forward Undersized Good Packets is disabled,Forward Undersized Good Packets is enabled" newline rbitfld.long 0x4 2. "RESERVED_2,Reserved." "0,1" newline bitfld.long 0x4 0.--1. "RTC,Receive Queue Threshold Control These bits control the threshold level of the MTL Rx queue (in bytes): The received packet is transferred to the application or DMA when the packet size within the MTL Rx queue is larger than the threshold. In addition.." "0,1,2,3" rgroup.long 0x34++0x7 line.long 0x0 "MTL_RXQ3_MISSED_PACKET_OVERFLOW_CNT,The Queue 3 Missed Packet and Overflow Counter register contains the counter for packets missed because of Receive queue packet flush and packets discarded because of Receive queue overflow." hexmask.long.byte 0x0 28.--31. 1. "RESERVED_31_28,Reserved." newline bitfld.long 0x0 27. "MISCNTOVF,Missed Packet Counter Overflow Bit When set this bit indicates that the Rx Queue Missed Packet Counter crossed the maximum limit. Access restriction applies. Clears on read. Self-set to 1 on internal event. 0x1: Missed Packet Counter overflow.." "Missed Packet Counter overflow not detected,Missed Packet Counter overflow detected" newline hexmask.long.word 0x0 16.--26. 1. "MISPKTCNT,Missed Packet Counter This field indicates the number of packets missed by the DWC_ether_qos because the application asserted ari_pkt_flush_i[] for this queue. This counter is reset when this register is read with mci_be_i[0] at 1b1. This.." newline hexmask.long.byte 0x0 12.--15. 1. "RESERVED_15_12,Reserved." newline bitfld.long 0x0 11. "OVFCNTOVF,Overflow Counter Overflow Bit When set this bit indicates that the Rx Queue Overflow Packet Counter field crossed the maximum limit. Access restriction applies. Clears on read. Self-set to 1 on internal event. 0x1: Overflow Counter overflow.." "Overflow Counter overflow not detected,Overflow Counter overflow detected" newline hexmask.long.word 0x0 0.--10. 1. "OVFPKTCNT,Overflow Packet Counter This field indicates the number of packets discarded by the DWC_ether_qos because of Receive queue overflow. This counter is incremented each time the DWC_ether_qos discards an incoming packet because of overflow. This.." line.long 0x4 "MTL_RXQ3_DEBUG,The Queue 3 Receive Debug register gives the debug status of various blocks related to the Receive queue." bitfld.long 0x4 30.--31. "RESERVED_31_30,Reserved." "0,1,2,3" newline hexmask.long.word 0x4 16.--29. 1. "PRXQ,Number of Packets in Receive Queue This field indicates the current number of packets in the Rx Queue. The theoretical maximum value for this field is 256KB/16B = 16K Packets that is Max_Queue_Size/Min_Packet_Size." newline hexmask.long.word 0x4 6.--15. 1. "RESERVED_15_6,Reserved." newline bitfld.long 0x4 4.--5. "RXQSTS,MTL Rx Queue Fill-Level Status This field gives the status of the fill-level of the Rx Queue: 0x2: Rx Queue fill-level above flow-control activate threshold 0x1: Rx Queue fill-level below flow-control deactivate threshold 0x0: Rx Queue empty 0x3:.." "Rx Queue empty,Rx Queue fill-level below flow-control..,Rx Queue fill-level above flow-control activate..,Rx Queue full" newline bitfld.long 0x4 3. "RESERVED_3,Reserved." "0,1" newline bitfld.long 0x4 1.--2. "RRCSTS,MTL Rx Queue Read Controller State This field gives the state of the Rx queue Read controller: 0x3: Flushing the packet data and status 0x0: Idle state 0x1: Reading packet data 0x2: Reading packet status (or timestamp)" "Idle state,Reading packet data,Reading packet status,Flushing the packet data and status" newline bitfld.long 0x4 0. "RWCSTS,MTL Rx Queue Write Controller Active Status When high this bit indicates that the MTL Rx queue Write controller is active and it is transferring a received packet to the Rx Queue. 0x1: MTL Rx Queue Write Controller Active Status detected 0x0:.." "MTL Rx Queue Write Controller Active Status not..,MTL Rx Queue Write Controller Active Status.." group.long 0x3C++0x3 line.long 0x0 "MTL_RXQ3_CONTROL,The Queue Receive Control register controls the receive arbitration and passing of received packets to the application." hexmask.long 0x0 4.--31. 1. "RESERVED_31_4,Reserved." newline bitfld.long 0x0 3. "RXQ_FRM_ARBIT,Receive Queue Packet Arbitration When this bit is set the DWC_ether_qos drives the packet data to the ARI interface such that the entire packet data of currently-selected queue is transmitted before switching to other queue. When this bit.." "Receive Queue Packet Arbitration is disabled,Receive Queue Packet Arbitration is enabled" newline bitfld.long 0x0 0.--2. "RXQ_WEGT,Receive Queue Weight This field indicates the weight assigned to the Rx Queue 0. The weight is used as the number of continuous PBL or packets requests (depending on the RXQ_FRM_ARBIT) allocated to the queue in one arbitration cycle." "0,1,2,3,4,5,6,7" tree.end tree "EQOS_MTL_Q4" group.long 0x0++0x3 line.long 0x0 "MTL_TXQ4_OPERATION_MODE,The Queue 4 Transmit Operation Mode register establishes the Transmit queue operating modes and commands." hexmask.long.word 0x0 21.--31. 1. "RESERVED_31_Y,Reserved." newline hexmask.long.byte 0x0 16.--20. 1. "TQS,Transmit Queue Size This field indicates the size of the allocated Transmit queues in blocks of 256 bytes. The TQS field is read-write only if the number of Tx Queues more than one the reset value is 0x0 and indicates size of 256 bytes. When the.." newline hexmask.long.word 0x0 7.--15. 1. "RESERVED_15_7,Reserved." newline bitfld.long 0x0 4.--6. "TTC,Transmit Threshold Control These bits control the threshold level of the MTL Tx Queue. The transmission starts when the packet size within the MTL Tx Queue is larger than the threshold. In addition full packets with length less than the threshold.." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 2.--3. "TXQEN,Transmit Queue Enable This field is used to enable/disable the transmit queue 0. - 2'b00: Not enabled - 2'b01: Enable in AV mode - 2'b10: Enabled - 2'b11: Reserved Note: In multiple Tx queues configuration all the queues are disabled by default." "Not enabled,Enable in AV mode,Enabled,Reserved" newline bitfld.long 0x0 1. "TSF,Transmit Store and Forward When this bit is set the transmission starts when a full packet resides in the MTL Tx queue. When this bit is set the TTC values specified in Bits[6:4] of this register are ignored. This bit should be changed only when.." "Transmit Store and Forward is disabled,Transmit Store and Forward is enabled" newline bitfld.long 0x0 0. "FTQ,Flush Transmit Queue When this bit is set the Tx queue controller logic is reset to its default values. Therefore all the data in the Tx queue is lost or flushed. This bit is internally reset when the flushing operation is complete. Until this bit.." "Flush Transmit Queue is disabled,Flush Transmit Queue is enabled" rgroup.long 0x4++0x7 line.long 0x0 "MTL_TXQ4_UNDERFLOW,The Queue 4 Underflow Counter register contains the counter for packets aborted because of Transmit queue underflow and packets missed because of Receive queue packet flush" hexmask.long.tbyte 0x0 12.--31. 1. "RESERVED_31_12,Reserved." newline bitfld.long 0x0 11. "UFCNTOVF,Overflow Bit for Underflow Packet Counter This bit is set every time the Tx queue Underflow Packet Counter field overflows that is it has crossed the maximum count. In such a scenario the overflow packet counter is reset to all-zeros and this.." "Overflow not detected for Underflow Packet Counter,Overflow detected for Underflow Packet Counter" newline hexmask.long.word 0x0 0.--10. 1. "UFFRMCNT,Underflow Packet Counter This field indicates the number of packets aborted by the controller because of Tx Queue Underflow. This counter is incremented each time the MAC aborts outgoing packet because of underflow. The counter is cleared when.." line.long 0x4 "MTL_TXQ4_DEBUG,The Queue 4 Transmit Debug register gives the debug status of various blocks related to the Transmit queue." hexmask.long.word 0x4 23.--31. 1. "RESERVED_31_23,Reserved." newline bitfld.long 0x4 20.--22. "STXSTSF,Number of Status Words in Tx Status FIFO of Queue This field indicates the current number of status in the Tx Status FIFO of this queue. When the DTXSTS bit of MTL_Operation_Mode register is set to 1 this field does not reflect the number of.." "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 19. "RESERVED_19,Reserved." "0,1" newline bitfld.long 0x4 16.--18. "PTXQ,Number of Packets in the Transmit Queue This field indicates the current number of packets in the Tx Queue. When the DTXSTS bit of MTL_Operation_Mode register is set to 1 this field does not reflect the number of packets in the Transmit queue." "0,1,2,3,4,5,6,7" newline hexmask.long.word 0x4 6.--15. 1. "RESERVED_15_6,Reserved." newline bitfld.long 0x4 5. "TXSTSFSTS,MTL Tx Status FIFO Full Status When high this bit indicates that the MTL Tx Status FIFO is full. Therefore the MTL cannot accept any more packets for transmission. 0x1: MTL Tx Status FIFO Full status is detected 0x0: MTL Tx Status FIFO Full.." "MTL Tx Status FIFO Full status is not detected,MTL Tx Status FIFO Full status is detected" newline bitfld.long 0x4 4. "TXQSTS,MTL Tx Queue Not Empty Status When this bit is high it indicates that the MTL Tx Queue is not empty and some data is left for transmission. 0x1: MTL Tx Queue Not Empty status is detected 0x0: MTL Tx Queue Not Empty status is not detected" "MTL Tx Queue Not Empty status is not detected,MTL Tx Queue Not Empty status is detected" newline bitfld.long 0x4 3. "TWCSTS,MTL Tx Queue Write Controller Status When high this bit indicates that the MTL Tx Queue Write Controller is active and it is transferring the data to the Tx Queue. 0x1: MTL Tx Queue Write Controller status is detected 0x0: MTL Tx Queue Write.." "MTL Tx Queue Write Controller status is not..,MTL Tx Queue Write Controller status is detected" newline bitfld.long 0x4 1.--2. "TRCSTS,MTL Tx Queue Read Controller Status This field indicates the state of the Tx Queue Read Controller: 0x3: Flushing the Tx queue because of the Packet Abort request from the MAC 0x0: Idle state 0x1: Read state (transferring data to the MAC.." "Idle state,Read state,Waiting for pending Tx Status from the MAC..,Flushing the Tx queue because of the Packet.." newline bitfld.long 0x4 0. "TXQPAUSED,Transmit Queue in Pause When this bit is high and the Rx flow control is enabled it indicates that the Tx Queue is in the Pause condition (in the full-duplex only mode) because of the following: - Reception of the PFC packet for the priorities.." "Transmit Queue in Pause status is not detected,Transmit Queue in Pause status is detected" group.long 0x10++0x3 line.long 0x0 "MTL_TXQ4_ETS_CONTROL,The Queue ETS Control register controls the enhanced transmission selection operation." hexmask.long 0x0 7.--31. 1. "RESERVED_31_7,Reserved." newline bitfld.long 0x0 4.--6. "SLC,Slot Count If the credit-based shaper algorithm is enabled the software can program the number of slots (of duration programmed in DMA_CH[n]_Slot_Interval register) over which the average transmitted bits per slot provided in the.." "?,?,?,?,?,Reserved,?,?" newline bitfld.long 0x0 3. "CC,Credit Control When this bit is set the accumulated credit parameter in the credit-based shaper algorithm logic is not reset to zero when there is positive credit and no packet to transmit in Channel 1. The credit accumulates even when there is no.." "Credit Control is disabled,Credit Control is enabled" newline bitfld.long 0x0 2. "AVALG,AV Algorithm When Queue 1 is programmed for AV this field configures the scheduling algorithm for this queue: This bit when set indicates credit based shaper algorithm (CBS) is selected for Queue 1 traffic. When reset strict priority is.." "CBS Algorithm is disabled,CBS Algorithm is enabled" newline rbitfld.long 0x0 0.--1. "RESERVED_1_0,Reserved." "0,1,2,3" rgroup.long 0x14++0x3 line.long 0x0 "MTL_TXQ4_ETS_STATUS,The Queue 4 ETS Status register provides the average traffic transmitted in Queue 4." hexmask.long.byte 0x0 24.--31. 1. "RESERVED_31_24,Reserved." newline hexmask.long.tbyte 0x0 0.--23. 1. "ABS,Average Bits per Slot This field contains the average transmitted bits per slot. If AV operation is enabled this field is computed over number of slots programmed in the SLC field of MTL_TxQ[n]_ETS_CONTROL register. The maximum value of this field.." group.long 0x18++0xF line.long 0x0 "MTL_TXQ4_QUANTUM_WEIGHT,The Queue 4 idleSlopeCredit. Quantum or Weights register provides the average traffic transmitted in Queue 4." hexmask.long.word 0x0 21.--31. 1. "RESERVED_31_21,Reserved." newline hexmask.long.tbyte 0x0 0.--20. 1. "ISCQW,idleSlopeCredit Quantum or Weights - idleSlopeCredit When AV feature is enabled this field contains the idleSlopeCredit value required for the credit-based shaper algorithm for Queue 1. This is the rate of change of credit in bits per cycle (40.." line.long 0x4 "MTL_TXQ4_SENDSLOPECREDIT,The sendSlopeCredit register contains the sendSlope credit value required for the credit-based shaper algorithm for the Queue." hexmask.long.tbyte 0x4 14.--31. 1. "RESERVED_31_14,Reserved." newline hexmask.long.word 0x4 0.--13. 1. "SSC,sendSlopeCredit Value When AV operation is enabled this field contains the sendSlopeCredit value required for credit-based shaper algorithm for Queue 1. This is the rate of change of credit in bits per cycle (40 ns 8 ns and 3.2 ns for 100 Mbps.." line.long 0x8 "MTL_TXQ4_HICREDIT,The hiCredit register contains the hiCredit value required for the credit-based shaper algorithm for the Queue." rbitfld.long 0x8 29.--31. "RESERVED_31_29,Reserved." "0,1,2,3,4,5,6,7" newline hexmask.long 0x8 0.--28. 1. "HC,hiCredit Value When the AV feature is enabled this field contains the hiCredit value required for the credit-based shaper algorithm. This is the maximum value that can be accumulated in the credit parameter. This is specified in bits scaled by 1 024." line.long 0xC "MTL_TXQ4_LOCREDIT,The loCredit register contains the loCredit value required for the credit-based shaper algorithm for the Queue." rbitfld.long 0xC 29.--31. "RESERVED_31_29,Reserved." "0,1,2,3,4,5,6,7" newline hexmask.long 0xC 0.--28. 1. "LC,loCredit Value When AV operation is enabled this field contains the loCredit value required for the credit-based shaper algorithm. This is the minimum value that can be accumulated in the credit parameter. This is specified in bits scaled by 1 024." group.long 0x2C++0x7 line.long 0x0 "MTL_Q4_INTERRUPT_CONTROL_STATUS,This register contains the interrupt enable and status bits for the queue 4 interrupts." hexmask.long.byte 0x0 25.--31. 1. "RESERVED_31_25,Reserved." newline bitfld.long 0x0 24. "RXOIE,Receive Queue Overflow Interrupt Enable When this bit is set the Receive Queue Overflow interrupt is enabled. When this bit is reset the Receive Queue Overflow interrupt is disabled. 0x0: Receive Queue Overflow Interrupt is disabled 0x1: Receive.." "Receive Queue Overflow Interrupt is disabled,Receive Queue Overflow Interrupt is enabled" newline hexmask.long.byte 0x0 17.--23. 1. "RESERVED_23_17,Reserved." newline bitfld.long 0x0 16. "RXOVFIS,Receive Queue Overflow Interrupt Status This bit indicates that the Receive Queue had an overflow while receiving the packet. If a partial packet is transferred to the application the overflow status is set in RDES3[21]. This bit is cleared when.." "Receive Queue Overflow Interrupt Status not..,Receive Queue Overflow Interrupt Status detected" newline hexmask.long.byte 0x0 10.--15. 1. "RESERVED_15_10,Reserved." newline bitfld.long 0x0 9. "ABPSIE,Average Bits Per Slot Interrupt Enable When this bit is set the MAC asserts the sbd_intr_o or mci_intr_o interrupt when the average bits per slot status is updated. When this bit is cleared the interrupt is not asserted for such an event. 0x0:.." "Average Bits Per Slot Interrupt is disabled,Average Bits Per Slot Interrupt is enabled" newline bitfld.long 0x0 8. "TXUIE,Transmit Queue Underflow Interrupt Enable When this bit is set the Transmit Queue Underflow interrupt is enabled. When this bit is reset the Transmit Queue Underflow interrupt is disabled. 0x0: Transmit Queue Underflow Interrupt Status is.." "Transmit Queue Underflow Interrupt Status is..,Transmit Queue Underflow Interrupt Status is.." newline hexmask.long.byte 0x0 2.--7. 1. "RESERVED_7_2,Reserved." newline bitfld.long 0x0 1. "ABPSIS,Average Bits Per Slot Interrupt Status When set this bit indicates that the MAC has updated the ABS value. This bit is cleared when the application writes 1 to this bit. Access restriction applies. Self-set to 1 on internal event. Setting 1.." "Average Bits Per Slot Interrupt Status not..,Average Bits Per Slot Interrupt Status detected" newline bitfld.long 0x0 0. "TXUNFIS,Transmit Queue Underflow Interrupt Status This bit indicates that the Transmit Queue had an underflow while transmitting the packet. Transmission is suspended and an Underflow Error TDES3[2] is set. This bit is cleared when the application writes.." "Transmit Queue Underflow Interrupt Status not..,Transmit Queue Underflow Interrupt Status detected" line.long 0x4 "MTL_RXQ4_OPERATION_MODE,The Queue 4 Receive Operation Mode register establishes the Receive queue operating modes and command. The RFA and RFD fields are not backward compatible with the RFA and RFD fields of 4.00a release" hexmask.long.byte 0x4 25.--31. 1. "RESERVED_31_Y,Reserved." newline hexmask.long.byte 0x4 20.--24. 1. "RQS,Receive Queue Size This field indicates the size of the allocated Receive queues in blocks of 256 bytes. The RQS field is read-write only if the number of Rx Queues more than one the reset value is 0x0 and indicates size of 256 bytes. When the.." newline rbitfld.long 0x4 18.--19. "RESERVED_19_Y,Reserved." "0,1,2,3" newline hexmask.long.byte 0x4 14.--17. 1. "RFD,Threshold for Deactivating Flow Control (in half-duplex and full-duplex modes) These bits control the threshold (fill-level of Rx queue) at which the flow control is de-asserted after activation: - 0: Full minus 1 KB that is FULL 1 KB - 1: Full.." newline rbitfld.long 0x4 12.--13. "RESERVED_13_Y,Reserved." "0,1,2,3" newline hexmask.long.byte 0x4 8.--11. 1. "RFA,Threshold for Activating Flow Control (in half-duplex and full-duplex These bits control the threshold (fill-level of Rx queue) at which the flow control is activated: For more information on encoding for this field see RFD." newline bitfld.long 0x4 7. "EHFC,Enable Hardware Flow Control When this bit is set the flow control signal operation based on the fill-level of Rx queue is enabled. When reset the flow control operation is disabled. 0x0: Hardware Flow Control is disabled 0x1: Hardware Flow.." "Hardware Flow Control is disabled,Hardware Flow Control is enabled" newline bitfld.long 0x4 6. "DIS_TCP_EF,Disable Dropping of TCP/IP Checksum Error Packets When this bit is set the MAC does not drop the packets which only have the errors detected by the Receive Checksum Offload engine. Such packets have errors only in the encapsulated payload." "Dropping of TCP/IP Checksum Error Packets is..,Dropping of TCP/IP Checksum Error Packets is.." newline bitfld.long 0x4 5. "RSF,Receive Queue Store and Forward When this bit is set the DWC_ether_qos reads a packet from the Rx queue only after the complete packet has been written to it ignoring the RTC field of this register. When this bit is reset the Rx queue operates in.." "Receive Queue Store and Forward is disabled,Receive Queue Store and Forward is enabled" newline bitfld.long 0x4 4. "FEP,Forward Error Packets When this bit is reset the Rx queue drops packets with error status (CRC error GMII_ER watchdog timeout or overflow). However if the start byte (write) pointer of a packet is already transferred to the read controller side.." "Forward Error Packets is disabled,Forward Error Packets is enabled" newline bitfld.long 0x4 3. "FUP,Forward Undersized Good Packets When this bit is set the Rx queue forwards the undersized good packets (packets with no error and length less than 64 bytes) including pad-bytes and CRC. When this bit is reset the Rx queue drops all packets of less.." "Forward Undersized Good Packets is disabled,Forward Undersized Good Packets is enabled" newline rbitfld.long 0x4 2. "RESERVED_2,Reserved." "0,1" newline bitfld.long 0x4 0.--1. "RTC,Receive Queue Threshold Control These bits control the threshold level of the MTL Rx queue (in bytes): The received packet is transferred to the application or DMA when the packet size within the MTL Rx queue is larger than the threshold. In addition.." "0,1,2,3" rgroup.long 0x34++0x7 line.long 0x0 "MTL_RXQ4_MISSED_PACKET_OVERFLOW_CNT,The Queue 4 Missed Packet and Overflow Counter register contains the counter for packets missed because of Receive queue packet flush and packets discarded because of Receive queue overflow." hexmask.long.byte 0x0 28.--31. 1. "RESERVED_31_28,Reserved." newline bitfld.long 0x0 27. "MISCNTOVF,Missed Packet Counter Overflow Bit When set this bit indicates that the Rx Queue Missed Packet Counter crossed the maximum limit. Access restriction applies. Clears on read. Self-set to 1 on internal event. 0x1: Missed Packet Counter overflow.." "Missed Packet Counter overflow not detected,Missed Packet Counter overflow detected" newline hexmask.long.word 0x0 16.--26. 1. "MISPKTCNT,Missed Packet Counter This field indicates the number of packets missed by the DWC_ether_qos because the application asserted ari_pkt_flush_i[] for this queue. This counter is reset when this register is read with mci_be_i[0] at 1b1. This.." newline hexmask.long.byte 0x0 12.--15. 1. "RESERVED_15_12,Reserved." newline bitfld.long 0x0 11. "OVFCNTOVF,Overflow Counter Overflow Bit When set this bit indicates that the Rx Queue Overflow Packet Counter field crossed the maximum limit. Access restriction applies. Clears on read. Self-set to 1 on internal event. 0x1: Overflow Counter overflow.." "Overflow Counter overflow not detected,Overflow Counter overflow detected" newline hexmask.long.word 0x0 0.--10. 1. "OVFPKTCNT,Overflow Packet Counter This field indicates the number of packets discarded by the DWC_ether_qos because of Receive queue overflow. This counter is incremented each time the DWC_ether_qos discards an incoming packet because of overflow. This.." line.long 0x4 "MTL_RXQ4_DEBUG,The Queue 4 Receive Debug register gives the debug status of various blocks related to the Receive queue." bitfld.long 0x4 30.--31. "RESERVED_31_30,Reserved." "0,1,2,3" newline hexmask.long.word 0x4 16.--29. 1. "PRXQ,Number of Packets in Receive Queue This field indicates the current number of packets in the Rx Queue. The theoretical maximum value for this field is 256KB/16B = 16K Packets that is Max_Queue_Size/Min_Packet_Size." newline hexmask.long.word 0x4 6.--15. 1. "RESERVED_15_6,Reserved." newline bitfld.long 0x4 4.--5. "RXQSTS,MTL Rx Queue Fill-Level Status This field gives the status of the fill-level of the Rx Queue: 0x2: Rx Queue fill-level above flow-control activate threshold 0x1: Rx Queue fill-level below flow-control deactivate threshold 0x0: Rx Queue empty 0x3:.." "Rx Queue empty,Rx Queue fill-level below flow-control..,Rx Queue fill-level above flow-control activate..,Rx Queue full" newline bitfld.long 0x4 3. "RESERVED_3,Reserved." "0,1" newline bitfld.long 0x4 1.--2. "RRCSTS,MTL Rx Queue Read Controller State This field gives the state of the Rx queue Read controller: 0x3: Flushing the packet data and status 0x0: Idle state 0x1: Reading packet data 0x2: Reading packet status (or timestamp)" "Idle state,Reading packet data,Reading packet status,Flushing the packet data and status" newline bitfld.long 0x4 0. "RWCSTS,MTL Rx Queue Write Controller Active Status When high this bit indicates that the MTL Rx queue Write controller is active and it is transferring a received packet to the Rx Queue. 0x1: MTL Rx Queue Write Controller Active Status detected 0x0:.." "MTL Rx Queue Write Controller Active Status not..,MTL Rx Queue Write Controller Active Status.." group.long 0x3C++0x3 line.long 0x0 "MTL_RXQ4_CONTROL,The Queue Receive Control register controls the receive arbitration and passing of received packets to the application." hexmask.long 0x0 4.--31. 1. "RESERVED_31_4,Reserved." newline bitfld.long 0x0 3. "RXQ_FRM_ARBIT,Receive Queue Packet Arbitration When this bit is set the DWC_ether_qos drives the packet data to the ARI interface such that the entire packet data of currently-selected queue is transmitted before switching to other queue. When this bit.." "Receive Queue Packet Arbitration is disabled,Receive Queue Packet Arbitration is enabled" newline bitfld.long 0x0 0.--2. "RXQ_WEGT,Receive Queue Weight This field indicates the weight assigned to the Rx Queue 0. The weight is used as the number of continuous PBL or packets requests (depending on the RXQ_FRM_ARBIT) allocated to the queue in one arbitration cycle." "0,1,2,3,4,5,6,7" tree.end tree "EQOS_DMA" group.long 0x0++0x7 line.long 0x0 "DMA_MODE,The Bus Mode register establishes the bus operating modes for the DMA." hexmask.long.word 0x0 18.--31. 1. "RESERVED_31_18,Reserved." newline bitfld.long 0x0 16.--17. "INTM,Interrupt Mode This field defines the interrupt mode of DWC_ether_qos. The behavior of the following outputs changes depending on the following settings: - sbd_perch_tx_intr_o[] (Transmit Per Channel Interrupt) - sbd_perch_rx_intr_o[] (Receive Per.." "See above description,See above description,See above description,Reserved" newline rbitfld.long 0x0 15. "RESERVED_15,Reserved." "0,1" newline rbitfld.long 0x0 12.--14. "RESERVED_PR,Reserved." "0,1,2,3,4,5,6,7" newline rbitfld.long 0x0 11. "RESERVED_TXPR,Reserved." "0,1" newline rbitfld.long 0x0 10. "RESERVED_SCSW,Reserved." "0,1" newline rbitfld.long 0x0 9. "RESERVED_ARBC,Reserved." "0,1" newline bitfld.long 0x0 8. "DSPW,Descriptor Posted Write When this bit is set to 0 the descriptor writes are always non-posted. When this bit is set to 1 the descriptor writes are non-posted only when IOC (Interrupt on completion) is set in last descriptor otherwise the.." "Descriptor Posted Write is disabled,Descriptor Posted Write is enabled" newline rbitfld.long 0x0 5.--7. "RESERVED_7_5,Reserved." "0,1,2,3,4,5,6,7" newline rbitfld.long 0x0 2.--4. "RESERVED_TAA,Reserved." "0,1,2,3,4,5,6,7" newline rbitfld.long 0x0 1. "RESERVED_DA,Reserved." "0,1" newline bitfld.long 0x0 0. "SWR,Software Reset When this bit is set the MAC and the DMA controller reset the logic and all internal registers of the DMA MTL and MAC. This bit is automatically cleared after the reset operation is complete in all DWC_ether_qos clock domains." "Software Reset is disabled,Software Reset is enabled" line.long 0x4 "DMA_SYSBUS_MODE,The System Bus mode register controls the behavior of the AHB or AXI master. It mainly controls burst splitting and number of outstanding requests." bitfld.long 0x4 31. "EN_LPI,Enable Low Power Interface (LPI) When set to 1 this bit enables the LPI mode supported by the EQOS-AXI configuration and accepts the LPI request from the AXI System Clock controller. When set to 0 this bit disables the LPI mode and always denies.." "Low Power Interface,Low Power Interface" newline bitfld.long 0x4 30. "LPI_XIT_PKT,Unlock on Magic Packet or Remote Wake-Up Packet When set to 1 this bit enables the AXI master to come out of the LPI mode only when the magic packet or remote wake-up packet is received. When set to 0 this bit enables the AXI master to come.." "Unlock on Magic Packet or Remote Wake-Up Packet..,Unlock on Magic Packet or Remote Wake-Up Packet.." newline rbitfld.long 0x4 28.--29. "RESERVED_29_Y,Reserved." "0,1,2,3" newline hexmask.long.byte 0x4 24.--27. 1. "WR_OSR_LMT,AXI Maximum Write Outstanding Request Limit This value limits the maximum outstanding request on the AXI write interface. Maximum outstanding requests = WR_OSR_LMT + 1 Note: - Bit 26 is reserved if DWC_ETHER_QOS_AXI_MAX_WR_REQ = 4 - Bit 27 is.." newline hexmask.long.byte 0x4 20.--23. 1. "RESERVED_23_Y,Reserved." newline hexmask.long.byte 0x4 16.--19. 1. "RD_OSR_LMT,AXI Maximum Read Outstanding Request Limit This value limits the maximum outstanding request on the AXI read interface. Maximum outstanding requests = RD_OSR_LMT + 1 Note: - Bit 18 is reserved if parameter DWC_ETHER_QOS_AXI_MAX_RD_REQ = 4 -.." newline rbitfld.long 0x4 15. "RESERVED_RB,Reserved." "0,1" newline rbitfld.long 0x4 14. "RESERVED_MB,Reserved." "0,1" newline bitfld.long 0x4 13. "ONEKBBE,1 KB Boundary Crossing Enable for the EQOS-AXI Master When set the burst transfers performed by the EQOS-AXI master do not cross 1 KB boundary. When reset the burst transfers performed by the EQOS-AXI master do not cross 4 KB boundary. 0x0: 1.." "0,1" newline bitfld.long 0x4 12. "AAL,Address-Aligned Beats When this bit is set to 1 the EQOS-AXI or EQOS-AHB master performs address-aligned burst transfers on Read and Write channels. 0x0: Address-Aligned Beats is disabled 0x1: Address-Aligned Beats is enabled" "Address-Aligned Beats is disabled,Address-Aligned Beats is enabled" newline bitfld.long 0x4 11. "EAME,Enhanced Address Mode Enable. When this bit is set to 1 the DMA master enables the enhanced address mode (40-bit or 48-bit addressing mode). In this mode the DMA engine uses either the 40- or 48-bit address depending on the configuration. 0x0:.." "Enhanced Address Mode is disabled,Enhanced Address Mode is enabled" newline bitfld.long 0x4 10. "AALE,Automatic AXI LPI enable When set to 1 enables the AXI master to enter into LPI state when there is no activity in the DWC_ether_qos for number of system clock cycles programmed in the LPIEI field of AXI_LPI_Entry_Interval register. 0x0: Automatic.." "Automatic AXI LPI is disabled,Automatic AXI LPI is enabled" newline rbitfld.long 0x4 8.--9. "RESERVED_9_8,Reserved." "0,1,2,3" newline bitfld.long 0x4 7. "BLEN256,AXI Burst Length 256 When this bit is set to 1 the EQOS-AXI master can select a burst length of 256 on the AXI interface. 0x0: No effect 0x1: AXI Burst Length 256" "No effect,AXI Burst Length 256" newline bitfld.long 0x4 6. "BLEN128,AXI Burst Length 128 When this bit is set to 1 the EQOS-AXI master can select a burst length of 128 on the AXI interface. 0x0: No effect 0x1: AXI Burst Length 128" "No effect,AXI Burst Length 128" newline bitfld.long 0x4 5. "BLEN64,AXI Burst Length 64 When this bit is set to 1 the EQOS-AXI master can select a burst length of 64 on the AXI interface. 0x0: No effect 0x1: AXI Burst Length 64" "No effect,AXI Burst Length 64" newline bitfld.long 0x4 4. "BLEN32,AXI Burst Length 32 When this bit is set to 1 the EQOS-AXI master can select a burst length of 32 on the AXI interface. 0x0: No effect 0x1: AXI Burst Length 32" "No effect,AXI Burst Length 32" newline bitfld.long 0x4 3. "BLEN16,AXI Burst Length 16 When this bit is set to 1 or the FB bit is set to 0 the EQOS-AXI master can select a burst length of 16 on the AXI interface. When the FB bit is set to 0 setting this bit has no effect. 0x0: No effect 0x1: AXI Burst Length 16" "No effect,AXI Burst Length 16" newline bitfld.long 0x4 2. "BLEN8,AXI Burst Length 8 When this bit is set to 1 or the FB bit is set to 0 the EQOS-AXI master can select a burst length of 8 on the AXI interface. When the FB bit is set to 0 setting this bit has no effect. 0x0: No effect 0x1: AXI Burst Length 8" "No effect,AXI Burst Length 8" newline bitfld.long 0x4 1. "BLEN4,AXI Burst Length 4 When this bit is set to 1 or the FB bit is set to 0 the EQOS-AXI master can select a burst length of 4 on the AXI interface. When the FB bit is set to 0 setting this bit has no effect. 0x0: No effect 0x1: AXI Burst Length 4" "No effect,AXI Burst Length 4" newline bitfld.long 0x4 0. "FB,Fixed Burst Length When this bit is set to 1 the EQOS-AXI master initiates burst transfers of specified lengths as given below. - Burst transfers of fixed burst lengths as indicated by the BLEN256 BLEN128 BLEN64 BLEN32 BLEN16 BLEN8 or BLEN4.." "Fixed Burst Length is disabled,Fixed Burst Length is enabled" rgroup.long 0x8++0xB line.long 0x0 "DMA_INTERRUPT_STATUS,The application reads this Interrupt Status register during interrupt service routine or polling to determine the interrupt status of DMA channels. MTL queues. and the MAC." hexmask.long.word 0x0 18.--31. 1. "RESERVED_31_18,Reserved." newline bitfld.long 0x0 17. "MACIS,MAC Interrupt Status This bit indicates an interrupt event in the MAC. To reset this bit to 1'b0 the software must read the corresponding register in the MAC to get the exact cause of the interrupt and clear its source. 0x1: MAC Interrupt Status.." "MAC Interrupt Status not detected,MAC Interrupt Status detected" newline bitfld.long 0x0 16. "MTLIS,MTL Interrupt Status This bit indicates an interrupt event in the MTL. To reset this bit to 1'b0 the software must read the corresponding register in the MTL to get the exact cause of the interrupt and clear its source. 0x1: MTL Interrupt Status.." "MTL Interrupt Status not detected,MTL Interrupt Status detected" newline hexmask.long.byte 0x0 8.--15. 1. "RESERVED_15_8,Reserved." newline bitfld.long 0x0 7. "RESERVED_DC7IS,Reserved." "0,1" newline bitfld.long 0x0 6. "RESERVED_DC6IS,Reserved." "0,1" newline bitfld.long 0x0 5. "RESERVED_DC5IS,Reserved." "0,1" newline bitfld.long 0x0 4. "DC4IS,DMA Channel 4 Interrupt Status This bit indicates an interrupt event in DMA Channel 4. To reset this bit to 1'b0 the software must read the corresponding register in DMA Channel 4 to get the exact cause of the interrupt and clear its source. 0x1:.." "DMA Channel 4 Interrupt Status not detected,DMA Channel 4 Interrupt Status detected" newline bitfld.long 0x0 3. "DC3IS,DMA Channel 3 Interrupt Status This bit indicates an interrupt event in DMA Channel 3. To reset this bit to 1'b0 the software must read the corresponding register in DMA Channel 3 to get the exact cause of the interrupt and clear its source. 0x1:.." "DMA Channel 3 Interrupt Status not detected,DMA Channel 3 Interrupt Status detected" newline bitfld.long 0x0 2. "DC2IS,DMA Channel 2 Interrupt Status This bit indicates an interrupt event in DMA Channel 2. To reset this bit to 1'b0 the software must read the corresponding register in DMA Channel 2 to get the exact cause of the interrupt and clear its source. 0x1:.." "DMA Channel 2 Interrupt Status not detected,DMA Channel 2 Interrupt Status detected" newline bitfld.long 0x0 1. "DC1IS,DMA Channel 1 Interrupt Status This bit indicates an interrupt event in DMA Channel 1. To reset this bit to 1'b0 the software must read the corresponding register in DMA Channel 1 to get the exact cause of the interrupt and clear its source. 0x1:.." "DMA Channel 1 Interrupt Status not detected,DMA Channel 1 Interrupt Status detected" newline bitfld.long 0x0 0. "DC0IS,DMA Channel 0 Interrupt Status This bit indicates an interrupt event in DMA Channel 0. To reset this bit to 1'b0 the software must read the corresponding register in DMA Channel 0 to get the exact cause of the interrupt and clear its source. 0x1:.." "DMA Channel 0 Interrupt Status not detected,DMA Channel 0 Interrupt Status detected" line.long 0x4 "DMA_DEBUG_STATUS0,The Debug Status 0 register gives the Receive and Transmit process status for DMA Channel 0-Channel 2 for debugging purpose." hexmask.long.byte 0x4 28.--31. 1. "TPS2,DMA Channel 2 Transmit Process State This field indicates the Tx DMA FSM state for Channel 2. The MSB of this field always returns 0. This field does not generate an interrupt. 0x5: Reserved for future use 0x7: Running (Closing Tx Descriptor) 0x1:.." newline hexmask.long.byte 0x4 24.--27. 1. "RPS2,DMA Channel 2 Receive Process State This field indicates the Rx DMA FSM state for Channel 2. The MSB of this field always returns 0. This field does not generate an interrupt. 0x2: Reserved for future use 0x5: Running (Closing the Rx Descriptor).." newline hexmask.long.byte 0x4 20.--23. 1. "TPS1,DMA Channel 1 Transmit Process State This field indicates the Tx DMA FSM state for Channel 1. The MSB of this field always returns 0. This field does not generate an interrupt. 0x5: Reserved for future use 0x7: Running (Closing Tx Descriptor) 0x1:.." newline hexmask.long.byte 0x4 16.--19. 1. "RPS1,DMA Channel 1 Receive Process State This field indicates the Rx DMA FSM state for Channel 1. The MSB of this field always returns 0. This field does not generate an interrupt. 0x2: Reserved for future use 0x5: Running (Closing the Rx Descriptor).." newline hexmask.long.byte 0x4 12.--15. 1. "TPS0,DMA Channel 0 Transmit Process State This field indicates the Tx DMA FSM state for Channel 0. The MSB of this field always returns 0. This field does not generate an interrupt. 0x5: Reserved for future use 0x7: Running (Closing Tx Descriptor) 0x1:.." newline hexmask.long.byte 0x4 8.--11. 1. "RPS0,DMA Channel 0 Receive Process State This field indicates the Rx DMA FSM state for Channel 0. The MSB of this field always returns 0. This field does not generate an interrupt. 0x2: Reserved for future use 0x5: Running (Closing the Rx Descriptor).." newline hexmask.long.byte 0x4 2.--7. 1. "RESERVED_7_2,Reserved." newline bitfld.long 0x4 1. "AXRHSTS,AXI Master Read Channel Status When high this bit indicates that the read channel of the AXI master is active and it is transferring the data. 0x1: AXI Master Read Channel Status detected 0x0: AXI Master Read Channel Status not detected" "AXI Master Read Channel Status not detected,AXI Master Read Channel Status detected" newline bitfld.long 0x4 0. "AXWHSTS,AXI Master Write Channel When high this bit indicates that the write channel of the AXI master is active and it is transferring data. 0x1: AXI Master Write Channel or AHB Master Status detected 0x0: AXI Master Write Channel or AHB Master Status.." "AXI Master Write Channel or AHB Master Status..,AXI Master Write Channel or AHB Master Status.." line.long 0x8 "DMA_DEBUG_STATUS1,The Debug Status1 register gives the Receive and Transmit process status for DMA Channel 3-Channel 6." hexmask.long.byte 0x8 28.--31. 1. "RESERVED_TPS6,Reserved." newline hexmask.long.byte 0x8 24.--27. 1. "RESERVED_RPS6,Reserved." newline hexmask.long.byte 0x8 20.--23. 1. "RESERVED_TPS5,Reserved." newline hexmask.long.byte 0x8 16.--19. 1. "RESERVED_RPS5,Reserved." newline hexmask.long.byte 0x8 12.--15. 1. "TPS4,DMA Channel 4 Transmit Process State This field indicates the Tx DMA FSM state for Channel 4. The MSB of this field always returns 0. This field does not generate an interrupt. 0x5: Reserved for future use 0x7: Running (Closing Tx Descriptor) 0x1:.." newline hexmask.long.byte 0x8 8.--11. 1. "RPS4,DMA Channel 4 Receive Process State This field indicates the Rx DMA FSM state for Channel 4. The MSB of this field always returns 0. This field does not generate an interrupt. 0x2: Reserved for future use 0x5: Running (Closing the Rx Descriptor).." newline hexmask.long.byte 0x8 4.--7. 1. "TPS3,DMA Channel 3 Transmit Process State This field indicates the Tx DMA FSM state for Channel 3. The MSB of this field always returns 0. This field does not generate an interrupt. 0x5: Reserved for future use 0x7: Running (Closing Tx Descriptor) 0x1:.." newline hexmask.long.byte 0x8 0.--3. 1. "RPS3,DMA Channel 3 Receive Process State This field indicates the Rx DMA FSM state for Channel 3. The MSB of this field always returns 0. This field does not generate an interrupt. 0x2: Reserved for future use 0x5: Running (Closing the Rx Descriptor).." group.long 0x20++0xB line.long 0x0 "AXI4_TX_AR_ACE_CONTROL,This register is used to control the AXI4 Cache Coherency Signals for read transactions by all the Transmit DMA channels. The following signals of the AXI4 interface are driven with different values as programmed for corresponding.." hexmask.long.word 0x0 22.--31. 1. "RESERVED_31_22,Reserved." newline bitfld.long 0x0 20.--21. "THD,Transmit DMA First Packet Buffer This field is used to drive ardomain_o[1:0] signal when Transmit DMA is accessing First Buffer of the Packet (First valid buffer with FD being set in the TDES3 of the Descriptor)." "0,1,2,3" newline hexmask.long.byte 0x0 16.--19. 1. "THC,Transmit DMA First Packet Buffer This field is used to drive arcache_o[3:0] signal when Transmit DMA is accessing First Buffer of the Packet (First valid buffer with FD being set in the TDES3 of the Descriptor).." newline rbitfld.long 0x0 14.--15. "RESERVED_15_14,Reserved." "0,1,2,3" newline bitfld.long 0x0 12.--13. "TED,Transmit DMA Extended Packet Buffer This field is used to drive ardomain_o[1:0] signal when Transmit DMA is accessing the extended buffers (when packet is distributed across multiple buffers)." "0,1,2,3" newline hexmask.long.byte 0x0 8.--11. 1. "TEC,Transmit DMA Extended Packet Buffer This field is used to drive arcache_o[3:0] signal when Transmit DMA is accessing the extended buffers (when packet is distributed across multiple buffers)." newline rbitfld.long 0x0 6.--7. "RESERVED_7_6,Reserved." "0,1,2,3" newline bitfld.long 0x0 4.--5. "TDRD,Transmit DMA Read Descriptor Domain Control This field is used to drive ardomain_o[1:0] signal when Transmit DMA engines access the Descriptor." "0,1,2,3" newline hexmask.long.byte 0x0 0.--3. 1. "TDRC,Transmit DMA Read Descriptor Cache Control This field is used to drive arcache_o[3:0] signal when Transmit DMA engines access the Descriptor." line.long 0x4 "AXI4_RX_AW_ACE_CONTROL,This register is used to control the AXI4 Cache Coherency Signals for write transactions by all the Receive DMA channels. The following signals of the AXI4 interface are driven with different values as programmed for corresponding.." rbitfld.long 0x4 30.--31. "RESERVED_31_30,Reserved." "0,1,2,3" newline bitfld.long 0x4 28.--29. "RDD,Receive DMA Buffer Domain Control This field is used to drive the awdomain_o[1:0] signal when Receive DMA is accessing the Buffer when Header and payload are NOT separated." "0,1,2,3" newline hexmask.long.byte 0x4 24.--27. 1. "RDC,Receive DMA Buffer Cache Control This field is used to drive awcache_o[3:0] signal when Receive DMA is accessing the Buffer when Header and payload are NOT separated." newline rbitfld.long 0x4 22.--23. "RESERVED_23_22,Reserved." "0,1,2,3" newline bitfld.long 0x4 20.--21. "RHD,Receive DMA Header Domain Control This field is used to drive awdomain_o[1:0] and signal when Receive DMA is accessing the header Buffer when Header and payload are separated." "0,1,2,3" newline hexmask.long.byte 0x4 16.--19. 1. "RHC,Receive DMA Header Cache Control This field is used to drive awcache_o[3:0] and signal when Receive DMA is accessing the header Buffer when Header and payload are separated." newline rbitfld.long 0x4 14.--15. "RESERVED_15_14,Reserved." "0,1,2,3" newline bitfld.long 0x4 12.--13. "RPD,Receive DMA Payload Domain Control This field is used to drive awdomain_o[1:0] signal when Receive DMA is accessing the Payload Buffer when Header and payload are separated." "0,1,2,3" newline hexmask.long.byte 0x4 8.--11. 1. "RPC,Receive DMA Payload Cache Control This field is used to drive awcache_o[3:0] signal when Receive DMA is accessing the Payload Buffer when Header and payload are separated." newline rbitfld.long 0x4 6.--7. "RESERVED_7_6,Reserved." "0,1,2,3" newline bitfld.long 0x4 4.--5. "RDWD,Receive DMA Write Descriptor Domain Control This field is used to drive awdomain_o[1:0] signal when Receive DMA accesses the Descriptor." "0,1,2,3" newline hexmask.long.byte 0x4 0.--3. 1. "RDWC,Receive DMA Write Descriptor Cache Control This field is used to drive awcache_o[3:0] signal when Receive DMA accesses the Descriptor." line.long 0x8 "AXI4_TXRX_AWAR_ACE_CONTROL,This register is used to control the AXI4 Cache Coherency Signals for Descriptor write transactions by all the TxDMA channels and Descriptor read transactions by all the RxDMA channels. It also controls the values to be driven.." hexmask.long.word 0x8 23.--31. 1. "RESERVED_31_23,Reserved." newline bitfld.long 0x8 20.--22. "WRP,DMA Write Protection control This field is used to drive awprot_m_o[2:0] signal on the AXI Write Channel." "0,1,2,3,4,5,6,7" newline rbitfld.long 0x8 19. "RESERVED_19,Reserved." "0,1" newline bitfld.long 0x8 16.--18. "RDP,DMA Read Protection control This field is used to drive arprot_m_o[2:0] signal during all read requests." "0,1,2,3,4,5,6,7" newline rbitfld.long 0x8 14.--15. "RESERVED_15_14,Reserved." "0,1,2,3" newline bitfld.long 0x8 12.--13. "RDRD,Receive DMA Read Descriptor Domain control This field is used to drive ardomain_o[1:0] signal when Receive DMA engines read the Descriptor." "0,1,2,3" newline hexmask.long.byte 0x8 8.--11. 1. "RDRC,Receive DMA Read Descriptor Cache control This field is used to drive arcache_o[3:0] signal when Receive DMA engines read the Descriptor." newline rbitfld.long 0x8 6.--7. "RESERVED_7_6,Reserved." "0,1,2,3" newline bitfld.long 0x8 4.--5. "TDWD,Transmit DMA Write Descriptor Domain control This field is used to drive awdomain_o[1:0] signal when Transmit DMA write to the Descriptor." "0,1,2,3" newline hexmask.long.byte 0x8 0.--3. 1. "TDWC,Transmit DMA Write Descriptor Cache control This field is used to drive awcache_o[3:0] signal when Transmit DMA writes to the Descriptor." group.long 0x40++0x3 line.long 0x0 "AXI_LPI_ENTRY_INTERVAL,This register is used to control the AXI LPI entry interval." hexmask.long 0x0 4.--31. 1. "RESERVED_31_4,Reserved." newline hexmask.long.byte 0x0 0.--3. 1. "LPIEI,LPI Entry Interval Contains the number of system clock cycles multiplied by 64 to wait for an activity in the DWC_ether_qos to enter into the AXI low power state 0 indicates 64 clock cycles" group.long 0x50++0x3 line.long 0x0 "DMA_TBS_CTRL,This register is used to control the TBS attributes." hexmask.long.tbyte 0x0 8.--31. 1. "FTOS,Fetch Time Offset The value in units of 256 nanoseconds that has to be deducted from the Launch time to compute the Fetch Time. Max value: 999 999 999 ns additionally should be smaller than CTR-1 value when ESTM mode is set since this value is a.." newline rbitfld.long 0x0 7. "RESERVED_7,Reserved." "0,1" newline bitfld.long 0x0 4.--6. "FGOS,Fetch GSN Offset The number GSN slots that must be deducted from the Launch GSN to compute the Fetch GSN. Value valid only when FTOV is set." "0,1,2,3,4,5,6,7" newline rbitfld.long 0x0 1.--3. "RESERVED_3_1,Reserved." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 0. "FTOV,Fetch Time Offset Valid When set indicates the FTOS field is valid. When not set indicates the Fetch Offset is not valid and the DMA engine can fetch the frames from host memory without any time restrictions. 0x0: Fetch Time Offset is invalid 0x1:.." "Fetch Time Offset is invalid,Fetch Time Offset is valid" rgroup.long 0x80++0x3 line.long 0x0 "DMA_SAFETY_INTERRUPT_STATUS,This register indicates summary (whether error occured in DMA/MTL/MAC and correctable/uncorrectable) of the Automotive Safety related error interrupts." bitfld.long 0x0 31. "MCSIS,MAC Safety Uncorrectable Interrupt Status Indicates a uncorrectable Safety related Interrupt is set in the MAC module. MAC_DPP_FSM_Interrupt_Status register should be read when this bit is set to get the cause of the Safety Interrupt in MAC. 0x1:.." "MAC Safety Uncorrectable Interrupt Status not..,MAC Safety Uncorrectable Interrupt Status detected" newline bitfld.long 0x0 30. "RESERVED_30,Reserved." "0,1" newline bitfld.long 0x0 29. "MSUIS,MTL Safety Uncorrectable error Interrupt Status This bit indicates an uncorrectable error interrupt event in MTL. To get exact cause of the interrupt the software should read the MTL_Safety_Interrupt_Status register. 0x1: MTL Safety Uncorrectable.." "MTL Safety Uncorrectable error Interrupt Status..,MTL Safety Uncorrectable error Interrupt Status.." newline bitfld.long 0x0 28. "MSCIS,MTL Safety Correctable error Interrupt Status This bit indicates a correctable error interrupt event in MTL. To get exact cause of the interrupt the software should read the MTL_Safety_Interrupt_Status register. 0x1: MTL Safety Correctable error.." "MTL Safety Correctable error Interrupt Status..,MTL Safety Correctable error Interrupt Status.." newline hexmask.long 0x0 2.--27. 1. "RESERVED_27_2,Reserved." newline bitfld.long 0x0 1. "DEUIS,DMA ECC Uncorrectable error Interrupt Status This bit indicates an interrupt event in the DMA ECC safety feature. To get the exact cause of the interrupt the application should read the DMA_ECC_Interrupt_Status register. 0x1: DMA ECC Uncorrectable.." "DMA ECC Uncorrectable error Interrupt Status not..,DMA ECC Uncorrectable error Interrupt Status.." newline bitfld.long 0x0 0. "DECIS,DMA ECC Correctable error Interrupt Status This bit indicates an interrupt event in the DMA ECC safety feature. To get the exact cause of the interrupt the application should read the DMA_ECC_Interrupt_Status register. 0x1: DMA ECC Correctable.." "DMA ECC Correctable error Interrupt Status not..,DMA ECC Correctable error Interrupt Status.." tree.end tree "EQOS_DMA_CH0" group.long 0x0++0xB line.long 0x0 "DMA_CH0_CONTROL,The DMA Channeli Control register specifies the MSS value for segmentation. length to skip between two descriptors. and also the features such as header splitting and 8xPBL mode." hexmask.long.byte 0x0 25.--31. 1. "RESERVED_31_25,Reserved." newline rbitfld.long 0x0 24. "RESERVED_SPH,Reserved." "0,1" newline rbitfld.long 0x0 21.--23. "RESERVED_23_21,Reserved." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 18.--20. "DSL,Descriptor Skip Length This bit specifies the Word Dword or Lword number (depending on the 32-bit 64-bit or 128-bit bus) to skip between two unchained descriptors. The address skipping starts from the end of the current descriptor to the start of.." "0,1,2,3,4,5,6,7" newline rbitfld.long 0x0 17. "RESERVED_17,Reserved." "0,1" newline bitfld.long 0x0 16. "PBLX8,8xPBL mode When this bit is set the PBL value programmed in Bits[21:16] in DMA_CH0_Tx_Control and Bits[21:16] in DMA_CH0_Rx_Control is multiplied by eight times. Therefore the DMA transfers the data in 8 16 32 64 128 and 256 beats depending.." "0,1" newline rbitfld.long 0x0 14.--15. "RESERVED_15_14,Reserved." "0,1,2,3" newline hexmask.long.word 0x0 0.--13. 1. "RESERVED_MSS,Reserved." line.long 0x4 "DMA_CH0_TX_CONTROL,The DMA Channeli Transmit Control register controls the Tx features such as PBL. TCP segmentation. and Tx Channel weights." rbitfld.long 0x4 29.--31. "RESERVED_31_29,Reserved." "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 28. "EDSE,Enhanced Descriptor Enable When this bit is set the corresponding channel uses Enhanced Descriptors that are 32 Bytes for both Normal and Context Descriptors. When reset the corresponding channel uses the descriptors that are 16 Bytes. 0x0:.." "Enhanced Descriptor is disabled,Enhanced Descriptor is enabled" newline hexmask.long.byte 0x4 24.--27. 1. "TQOS,Transmit QOS. This field is used to drive arqos_m_o[3:0] or awqos_m_o[3:0] output signals for all transactions of DMA Tx Channel0." newline rbitfld.long 0x4 23. "RESERVED_23,Reserved." "0,1" newline rbitfld.long 0x4 22. "RESERVED_ETIC,Reserved." "0,1" newline hexmask.long.byte 0x4 16.--21. 1. "TXPBL,Transmit Programmable Burst Length These bits indicate the maximum number of beats to be transferred in one DMA block data transfer. The DMA always attempts max burst as specified in PBL each time it starts a burst transfer on the application bus." newline bitfld.long 0x4 15. "IPBL,Ignore PBL Requirement When this bit is set the DMA does not check for PBL number of locations in the MTL before initiating a transfer. If space is not available the MTL may use handshaking to slow the DMA. Note: This bit/mode must not be used.." "Ignore PBL Requirement is disabled,Ignore PBL Requirement is enabled" newline rbitfld.long 0x4 13.--14. "RESERVED_TSE_MODE,Reserved." "0,1,2,3" newline rbitfld.long 0x4 12. "RESERVED_TSE,Reserved." "0,1" newline hexmask.long.byte 0x4 5.--11. 1. "RESERVED_11_5,Reserved." newline bitfld.long 0x4 4. "OSF,Operate on Second Packet When this bit is set it instructs the DMA to process the second packet of the Transmit data even before the status for the first packet is obtained. 0x0: Operate on Second Packet disabled 0x1: Operate on Second Packet enabled" "Operate on Second Packet disabled,Operate on Second Packet enabled" newline rbitfld.long 0x4 1.--3. "RESERVED_TCW,Reserved." "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 0. "ST,Start or Stop Transmission Command When this bit is set transmission is placed in the Running state. The DMA checks the Transmit list at the current position for a packet to be transmitted. The DMA tries to acquire descriptor from either of the.." "Stop Transmission Command,Start Transmission Command" line.long 0x8 "DMA_CH0_RX_CONTROL,The DMA Channeli Receive Control register controls the Rx features such as PBL. buffer size. and extended status." bitfld.long 0x8 31. "RPF,Rx Packet Flush. When this bit is set to 1 then DWC_ether_qos automatically flushes the packet from the Rx Queues destined to this DMA Rx Channel when it is stopped. When this bit remains set and the DMA is re-started by the software driver the.." "Rx Packet Flush is disabled,Rx Packet Flush is enabled" newline rbitfld.long 0x8 28.--30. "RESERVED_30_28,Reserved." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x8 24.--27. 1. "RQOS,Rx AXI4 QOS. This field is used to drive arqos_m_o[3:0] or awqos_m_o[3:0] output signals for all transactions of DMA Rx Channel0." newline rbitfld.long 0x8 23. "RESERVED_23,Reserved." "0,1" newline rbitfld.long 0x8 22. "RESERVED_ERIC,Reserved." "0,1" newline hexmask.long.byte 0x8 16.--21. 1. "RXPBL,Receive Programmable Burst Length These bits indicate the maximum number of beats to be transferred in one DMA block data transfer. The DMA always attempts max burst as specified in PBL each time it starts a burst transfer on the application bus." newline rbitfld.long 0x8 15. "RESERVED_15,Reserved." "0,1" newline hexmask.long.word 0x8 5.--14. 1. "RBSZ_13_Y,Receive Buffer size High RBSZ[13:0] is split into two fields higher RBSZ_13_y and lower RBSZ_x_0. The RBSZ[13:0] field indicates the size of the Rx buffers specified in bytes. The maximum buffer size is limited to 16K bytes. The buffer size is.." newline hexmask.long.byte 0x8 1.--4. 1. "RBSZ_X_0,Receive Buffer size Low RBSZ[13:0] is split into two fields RBSZ_13_y and RBSZ_x_0. The RBSZ_x_0 is the lower field whose width is based on data bus width of the configuration. This field is of width 2 3 or 4 bits for 32-bit 64-bit or.." newline bitfld.long 0x8 0. "SR,Start or Stop Receive When this bit is set the DMA tries to acquire the descriptor from the Receive list and processes the incoming packets. The DMA tries to acquire descriptor from either of the following positions: - The current position in the.." "Stop Receive,Start Receive" group.long 0x10++0x13 line.long 0x0 "DMA_CH0_TXDESC_LIST_HADDRESS,The Channeli Tx Descriptor List HAddress register has the higher 8 or 16 bits of the start address of the Transmit descriptor list. You can write to this register only when the Tx DMA has stopped. that is. the ST bit is set.." hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED_31_Y,Reserved." newline hexmask.long.byte 0x0 0.--7. 1. "TDESHA,Start of Transmit List This field contains the most-significant 8 or 16 bits of the 40- or 48-bit base address of the first descriptor in the Transmit descriptor list." line.long 0x4 "DMA_CH0_TXDESC_LIST_ADDRESS,The Channeli Tx Descriptor List Address register points the DMA to the start of Transmit descriptor list. The descriptor lists reside in the physical memory space of the application and must be Word. Dword. or Lword-aligned.." hexmask.long 0x4 4.--31. 1. "TDESLA,Start of Transmit List This field contains the base address of the first descriptor in the Transmit descriptor list. The DMA ignores the LSB bits (1:0 2:0 or 3:0) for 32-bit 64-bit or 128-bit bus width and internally takes these bits as.." newline hexmask.long.byte 0x4 0.--3. 1. "RESERVED_LSB," line.long 0x8 "DMA_CH0_RXDESC_LIST_HADDRESS,The Channeli Rx Descriptor List HAddress register has the higher 8 or 16 bits of the start address of the Receive descriptor list. Writing to this register is permitted only when reception is stopped. When stopped. this.." hexmask.long.tbyte 0x8 8.--31. 1. "RESERVED_31_Y,Reserved." newline hexmask.long.byte 0x8 0.--7. 1. "RDESHA,Start of Receive List This field contains the most-significant 8 or 16 bits of the 40-bit or 48-bit base address of the first descriptor in the Rx Descriptor list." line.long 0xC "DMA_CH0_RXDESC_LIST_ADDRESS,The Channeli Rx Descriptor List Address register points the DMA to the start of Receive descriptor list. This register points to the start of the Receive Descriptor List. The descriptor lists reside in the physical memory.." hexmask.long 0xC 4.--31. 1. "RDESLA,Start of Receive List This field contains the base address of the first descriptor in the Rx Descriptor list. The DMA ignores the LSB bits (1:0 2:0 or 3:0) for 32-bit 64-bit or 128-bit bus width and internally takes these bits as all-zero." newline hexmask.long.byte 0xC 0.--3. 1. "RESERVED_LSB," line.long 0x10 "DMA_CH0_TXDESC_TAIL_POINTER,The Channeli Tx Descriptor Tail Pointer register points to an offset from the base and indicates the location of the last valid descriptor." hexmask.long 0x10 4.--31. 1. "TDTP,Transmit Descriptor Tail Pointer This field contains the tail pointer for the Tx descriptor ring. The software writes the tail pointer to add more descriptors to the Tx channel. The hardware tries to transmit all packets referenced by the.." newline hexmask.long.byte 0x10 0.--3. 1. "RESERVED_LSB," group.long 0x28++0x17 line.long 0x0 "DMA_CH0_RXDESC_TAIL_POINTER,The Channeli Rx Descriptor Tail Pointer Points to an offset from the base and indicates the location of the last valid descriptor." hexmask.long 0x0 4.--31. 1. "RDTP,Receive Descriptor Tail Pointer This field contains the tail pointer for the Rx descriptor ring. The software writes the tail pointer to add more descriptors to the Rx channel. The hardware tries to write all received packets to the descriptors.." newline hexmask.long.byte 0x0 0.--3. 1. "RESERVED_LSB," line.long 0x4 "DMA_CH0_TXDESC_RING_LENGTH,The Tx Descriptor Ring Length register contains the length of the Transmit descriptor ring." hexmask.long.tbyte 0x4 10.--31. 1. "RESERVED_31_10,Reserved." newline hexmask.long.word 0x4 0.--9. 1. "TDRL,Transmit Descriptor Ring Length This field sets the maximum number of Tx descriptors in the circular descriptor ring. The maximum number of descriptors is limited to 1K descriptors. Synopsys recommends a minimum ring descriptor length of 4. For.." line.long 0x8 "DMA_CH0_RXDESC_RING_LENGTH,The Channeli Rx Descriptor Ring Length register contains the length of the Receive descriptor circular ring." hexmask.long.tbyte 0x8 10.--31. 1. "RESERVED_31_10,Reserved." newline hexmask.long.word 0x8 0.--9. 1. "RDRL,Receive Descriptor Ring Length This register sets the maximum number of Rx descriptors in the circular descriptor ring. The maximum number of descriptors is limited to 1K descriptors. For example You can program any value up to 0x3FF in this field." line.long 0xC "DMA_CH0_INTERRUPT_ENABLE,The Channeli Interrupt Enable register enables the interrupts reported by the Status register." hexmask.long.word 0xC 16.--31. 1. "RESERVED_31_16,Reserved." newline bitfld.long 0xC 15. "NIE,Normal Interrupt Summary Enable When this bit is set the normal interrupt summary is enabled. This bit enables the following interrupts in the DMA_CH0_Status register: - Bit 0: Transmit Interrupt - Bit 2: Transmit Buffer Unavailable - Bit 6: Receive.." "Normal Interrupt Summary is disabled,Normal Interrupt Summary is enabled" newline bitfld.long 0xC 14. "AIE,Abnormal Interrupt Summary Enable When this bit is set the abnormal interrupt summary is enabled. This bit enables the following interrupts in the DMA_CH0_Status register: - Bit 1: Transmit Process Stopped - Bit 7: Rx Buffer Unavailable - Bit 8:.." "Abnormal Interrupt Summary is disabled,Abnormal Interrupt Summary is enabled" newline bitfld.long 0xC 13. "CDEE,Context Descriptor Error Enable When this bit is set along with the AIE bit the Descriptor error interrupt is enabled. When this bit is reset the Descriptor error interrupt is disabled. 0x0: Context Descriptor Error is disabled 0x1: Context.." "Context Descriptor Error is disabled,Context Descriptor Error is enabled" newline bitfld.long 0xC 12. "FBEE,Fatal Bus Error Enable When this bit is set along with the AIE bit the Fatal Bus error interrupt is enabled. When this bit is reset the Fatal Bus Error error interrupt is disabled. 0x0: Fatal Bus Error is disabled 0x1: Fatal Bus Error is enabled" "Fatal Bus Error is disabled,Fatal Bus Error is enabled" newline bitfld.long 0xC 11. "ERIE,Early Receive Interrupt Enable When this bit is set along with the NIE bit the Early Receive interrupt is enabled. When this bit is reset the Early Receive interrupt is disabled. 0x0: Early Receive Interrupt is disabled 0x1: Early Receive.." "Early Receive Interrupt is disabled,Early Receive Interrupt is enabled" newline bitfld.long 0xC 10. "ETIE,Early Transmit Interrupt Enable When this bit is set along with the AIE bit the Early Transmit interrupt is enabled. When this bit is reset the Early Transmit interrupt is disabled. 0x0: Early Transmit Interrupt is disabled 0x1: Early Transmit.." "Early Transmit Interrupt is disabled,Early Transmit Interrupt is enabled" newline bitfld.long 0xC 9. "RWTE,Receive Watchdog Timeout Enable When this bit is set along with the AIE bit the Receive Watchdog Timeout interrupt is enabled. When this bit is reset the Receive Watchdog Timeout interrupt is disabled. 0x0: Receive Watchdog Timeout is disabled.." "Receive Watchdog Timeout is disabled,Receive Watchdog Timeout is enabled" newline bitfld.long 0xC 8. "RSE,Receive Stopped Enable When this bit is set along with the AIE bit the Receive Stopped Interrupt is enabled. When this bit is reset the Receive Stopped interrupt is disabled. 0x0: Receive Stopped is disabled 0x1: Receive Stopped is enabled" "Receive Stopped is disabled,Receive Stopped is enabled" newline bitfld.long 0xC 7. "RBUE,Receive Buffer Unavailable Enable When this bit is set along with the AIE bit the Receive Buffer Unavailable interrupt is enabled. When this bit is reset the Receive Buffer Unavailable interrupt is disabled. 0x0: Receive Buffer Unavailable is.." "Receive Buffer Unavailable is disabled,Receive Buffer Unavailable is enabled" newline bitfld.long 0xC 6. "RIE,Receive Interrupt Enable When this bit is set along with the NIE bit the Receive Interrupt is enabled. When this bit is reset the Receive Interrupt is disabled. 0x0: Receive Interrupt is disabled 0x1: Receive Interrupt is enabled" "Receive Interrupt is disabled,Receive Interrupt is enabled" newline rbitfld.long 0xC 3.--5. "RESERVED_5_3,Reserved." "0,1,2,3,4,5,6,7" newline bitfld.long 0xC 2. "TBUE,Transmit Buffer Unavailable Enable When this bit is set along with the NIE bit the Transmit Buffer Unavailable interrupt is enabled. When this bit is reset the Transmit Buffer Unavailable interrupt is disabled. 0x0: Transmit Buffer Unavailable is.." "Transmit Buffer Unavailable is disabled,Transmit Buffer Unavailable is enabled" newline bitfld.long 0xC 1. "TXSE,Transmit Stopped Enable When this bit is set along with the AIE bit the Transmission Stopped interrupt is enabled. When this bit is reset the Transmission Stopped interrupt is disabled. 0x0: Transmit Stopped is disabled 0x1: Transmit Stopped is.." "Transmit Stopped is disabled,Transmit Stopped is enabled" newline bitfld.long 0xC 0. "TIE,Transmit Interrupt Enable When this bit is set along with the NIE bit the Transmit Interrupt is enabled. When this bit is reset the Transmit Interrupt is disabled. 0x0: Transmit Interrupt is disabled 0x1: Transmit Interrupt is enabled" "Transmit Interrupt is disabled,Transmit Interrupt is enabled" line.long 0x10 "DMA_CH0_RX_INTERRUPT_WATCHDOG_TIMER,The Receive Interrupt Watchdog Timer register indicates the watchdog timeout for Receive Interrupt (RI) from the DMA. When this register is written with a non-zero value. it enables the watchdog timer for the RI bit of.." hexmask.long.word 0x10 18.--31. 1. "RESERVED_31_18,Reserved." newline bitfld.long 0x10 16.--17. "RWTU,Receive Interrupt Watchdog Timer Count Units This fields indicates the number of system clock cycles corresponding to one unit in RWT field. - 2'b00: 256 - 2'b01: 512 - 2'b10: 1024 - 2'b11: 2048 For example when RWT=2 and RWTU=1 the watchdog timer.." "0,1,2,3" newline hexmask.long.byte 0x10 8.--15. 1. "RESERVED_15_8,Reserved." newline hexmask.long.byte 0x10 0.--7. 1. "RWT,Receive Interrupt Watchdog Timer Count This field indicates the number of system clock cycles multiplied by factor indicated in RWTU field for which the watchdog timer is set. The watchdog timer is triggered with the programmed value after the Rx.." line.long 0x14 "DMA_CH0_SLOT_FUNCTION_CONTROL_STATUS,The Slot Function Control and Status register contains the control bits for slot function and the status for Transmit path." hexmask.long.word 0x14 20.--31. 1. "RESERVED_31_20,Reserved." newline hexmask.long.byte 0x14 16.--19. 1. "RSN,Reference Slot Number This field gives the current value of the reference slot number in the DMA. It is used for slot comparison." newline hexmask.long.word 0x14 4.--15. 1. "SIV,Slot Interval Value This field controls the period of the slot interval in which the TxDMA fetches the scheduled packets. A value of 0 specifies the slot interval of 1 us while the maximum value 4095 specifies the slot interval of 4096us. The.." newline rbitfld.long 0x14 2.--3. "RESERVED_3_2,Reserved." "0,1,2,3" newline bitfld.long 0x14 1. "ASC,Advance Slot Check When set this bit enables the DMA to fetch the data from the buffer when the slot number (SLOTNUM) programmed in the Tx descriptor is - equal to the reference slot number given in the RSN field or - ahead of the reference slot.." "Advance Slot Check is disabled,Advance Slot Check is enabled" newline bitfld.long 0x14 0. "ESC,Enable Slot Comparison When set this bit enables the checking of the slot numbers programmed in the Tx descriptor with the current reference given in the RSN field. The DMA fetches the data from the corresponding buffer only when the slot number is.." "Slot Comparison is disabled,Slot Comparison is enabled" rgroup.long 0x44++0x3 line.long 0x0 "DMA_CH0_CURRENT_APP_TXDESC,The Channeli Current Application Transmit Descriptor register points to the current Transmit descriptor read by the DMA." hexmask.long 0x0 0.--31. 1. "CURTDESAPTR,Application Transmit Descriptor Address Pointer The DMA updates this pointer during Tx operation. This pointer is cleared on reset." rgroup.long 0x4C++0x13 line.long 0x0 "DMA_CH0_CURRENT_APP_RXDESC,The Channeli Current Application Receive Descriptor register points to the current Receive descriptor read by the DMA." hexmask.long 0x0 0.--31. 1. "CURRDESAPTR,Application Receive Descriptor Address Pointer The DMA updates this pointer during Rx operation. This pointer is cleared on reset." line.long 0x4 "DMA_CH0_CURRENT_APP_TXBUFFER_H,The Channeli Current Application Transmit Buffer Address High register has the higher 8 or 16 bits of the current address of the Transmit buffer address read by the DMA." hexmask.long.tbyte 0x4 8.--31. 1. "RESERVED_31_Y,Reserved." newline hexmask.long.byte 0x4 0.--7. 1. "CURTBUFAPTRH,Application Transmit Buffer Address Pointer The DMA updates this pointer during Tx operation. This pointer is cleared on reset." line.long 0x8 "DMA_CH0_CURRENT_APP_TXBUFFER,The Channeli Current Application Transmit Buffer Address register points to the current Tx buffer address read by the DMA." hexmask.long 0x8 0.--31. 1. "CURTBUFAPTR,Application Transmit Buffer Address Pointer The DMA updates this pointer during Tx operation. This pointer is cleared on reset." line.long 0xC "DMA_CH0_CURRENT_APP_RXBUFFER_H,The Channeli Current Application Receive Buffer Address High register has the higher 8 or 16 bits of the current address of the Receive buffer address read by the DMA." hexmask.long.tbyte 0xC 8.--31. 1. "RESERVED_31_Y,Reserved." newline hexmask.long.byte 0xC 0.--7. 1. "CURRBUFAPTRH,Application Receive Buffer Address Pointer The DMA updates this pointer during Rx operation. This pointer is cleared on reset." line.long 0x10 "DMA_CH0_CURRENT_APP_RXBUFFER,The Channel 0 Current Application Receive Buffer Address register points to the current Rx buffer address read by the DMA." hexmask.long 0x10 0.--31. 1. "CURRBUFAPTR,Application Receive Buffer Address Pointer The DMA updates this pointer during Rx operation. This pointer is cleared on reset." group.long 0x60++0x3 line.long 0x0 "DMA_CH0_STATUS,The software driver (application) reads the Status register during interrupt service routine or polling to determine the status of the DMA. Note: The number of DMA_CH[n]_Status register in the configuration is the higher of number of Rx.." hexmask.long.word 0x0 22.--31. 1. "RESERVED_31_22,Reserved." newline rbitfld.long 0x0 19.--21. "REB,Rx DMA Error Bits This field indicates the type of error that caused a Bus Error. For example error response on the AHB or AXI interface. - Bit 21 -- 1'b1: Error during data transfer by Rx DMA -- 1'b0: No Error during data transfer by Rx DMA - Bit.." "Error during write transfer,Error during read transfer,?,?,?,?,?,?" newline rbitfld.long 0x0 16.--18. "TEB,Tx DMA Error Bits This field indicates the type of error that caused a Bus Error. For example error response on the AHB or AXI interface. - Bit 18 -- 1'b1: Error during data transfer by Tx DMA -- 1'b0: No Error during data transfer by Tx DMA - Bit.." "Error during write transfer,Error during read transfer,?,?,?,?,?,?" newline bitfld.long 0x0 15. "NIS,Normal Interrupt Summary Normal Interrupt Summary bit value is the logical OR of the following bits when the corresponding interrupt bits are enabled in the DMA_CH0_Interrupt_Enable register: - Bit 0: Transmit Interrupt - Bit 2: Transmit Buffer.." "Normal Interrupt Summary status not detected,Normal Interrupt Summary status detected" newline bitfld.long 0x0 14. "AIS,Abnormal Interrupt Summary Abnormal Interrupt Summary bit value is the logical OR of the following when the corresponding interrupt bits are enabled in the DMA_CH0_Interrupt_Enable register: - Bit 1: Transmit Process Stopped - Bit 7: Receive Buffer.." "Abnormal Interrupt Summary status not detected,Abnormal Interrupt Summary status detected" newline bitfld.long 0x0 13. "CDE,Context Descriptor Error This bit indicates that the DMA Tx/Rx engine received a descriptor error which indicates invalid context in the middle of packet flow ( intermediate descriptor) or all one's descriptor in Tx case and on Rx side it indicates.." "Context Descriptor Error status not detected,Context Descriptor Error status detected" newline bitfld.long 0x0 12. "FBE,Fatal Bus Error This bit indicates that a bus error occurred (as described in the EB field). When this bit is set the corresponding DMA channel engine disables all bus accesses. Access restriction applies. Self-set to 1 on internal event. Setting 1.." "Fatal Bus Error status not detected,Fatal Bus Error status detected" newline bitfld.long 0x0 11. "ERI,Early Receive Interrupt This bit when set indicates that the RxDMA has completed the transfer of packet data to the memory. In configs supporting ERIC When ERIC=0 this bit is set only after the Rx DMA has filled up a complete receive buffer with.." "Early Receive Interrupt status not detected,Early Receive Interrupt status detected" newline bitfld.long 0x0 10. "ETI,Early Transmit Interrupt This bit when set indicates that the TxDMA has completed the transfer of packet data to the MTL TXFIFO memory. In configs supporting ERIC: When ETIC=0 this bit is set only after the Tx DMA has transferred a complete packet.." "Early Transmit Interrupt status not detected,Early Transmit Interrupt status detected" newline bitfld.long 0x0 9. "RWT,Receive Watchdog Timeout This bit is asserted when a packet with length greater than 2 048 bytes (10 240 bytes when Jumbo Packet mode is enabled) is received. 0x1: Receive Watchdog Timeout status detected 0x0: Receive Watchdog Timeout status not.." "Receive Watchdog Timeout status not detected,Receive Watchdog Timeout status detected" newline bitfld.long 0x0 8. "RPS,Receive Process Stopped This bit is asserted when the Rx process enters the Stopped state. Access restriction applies. Self-set to 1 on internal event. Setting 1 clears. Setting 0 has no effect. 0x1: Receive Process Stopped status detected 0x0:.." "Receive Process Stopped status not detected,Receive Process Stopped status detected" newline bitfld.long 0x0 7. "RBU,Receive Buffer Unavailable This bit indicates that the application owns the next descriptor in the Receive list and the DMA cannot acquire it. The Rx process is suspended. To resume processing Rx descriptors the application should change the.." "Receive Buffer Unavailable status not detected,Receive Buffer Unavailable status detected" newline bitfld.long 0x0 6. "RI,Receive Interrupt This bit indicates that the packet reception is complete. When packet reception is complete Bit 31 of RDES3 is reset in the last descriptor and the specific packet status information is updated in the descriptor. The reception.." "Receive Interrupt status not detected,Receive Interrupt status detected" newline rbitfld.long 0x0 3.--5. "RESERVED_5_3,Reserved." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 2. "TBU,Transmit Buffer Unavailable This bit indicates that the application owns the next descriptor in the Transmit list and the DMA cannot acquire it. Transmission is suspended. The TPS0 field of the DMA_Debug_Status0 register explains the Transmit.." "Transmit Buffer Unavailable status not detected,Transmit Buffer Unavailable status detected" newline bitfld.long 0x0 1. "TPS,Transmit Process Stopped This bit is set when the transmission is stopped. Access restriction applies. Self-set to 1 on internal event. Setting 1 clears. Setting 0 has no effect. 0x1: Transmit Process Stopped status detected 0x0: Transmit Process.." "Transmit Process Stopped status not detected,Transmit Process Stopped status detected" newline bitfld.long 0x0 0. "TI,Transmit Interrupt This bit indicates that the packet transmission is complete. When transmission is complete Bit 31 of TDES3 is reset in the last descriptor and the specific packet status information is updated in the descriptor. Access restriction.." "Transmit Interrupt status not detected,Transmit Interrupt status detected" rgroup.long 0x64++0xB line.long 0x0 "DMA_CH0_MISS_FRAME_CNT,This register has the number of packet counter that got dropped by the DMA either due to Bus Error or due to programming RPF field in DMA_CH{i}_Rx_Control register." hexmask.long.word 0x0 16.--31. 1. "RESERVED_31_16,Reserved." newline bitfld.long 0x0 15. "MFCO,Overflow status of the MFC Counter When this bit is set then the MFC counter does not get incremented further. The bit gets cleared when this register is read. Access restriction applies. Clears on read. Self-set to 1 on internal event. 0x1: Miss.." "Miss Frame Counter overflow not occurred,Miss Frame Counter overflow occurred" newline hexmask.long.byte 0x0 11.--14. 1. "RESERVED_14_11,Reserved." newline hexmask.long.word 0x0 0.--10. 1. "MFC,Dropped Packet Counters This counter indicates the number of packet counters that are dropped by the DMA either because of bus error or because of programing RPF field in DMA_CH{i}_Rx_Control register. The counter gets cleared when this register is.." line.long 0x4 "DMA_CH0_RXP_ACCEPT_CNT,The DMA_CH(#i)_RXP_Accept_Cnt registers provides the count of the number of frames accepted by Rx Parser." bitfld.long 0x4 31. "RXPACOF,Rx Parser Accept Counter Overflow Bit When set this bit indicates that the RXPAC Counter field crossed the maximum limit. Access restriction applies. Clears on read. Self-set to 1 on internal event. 0x1: Rx Parser Accept Counter overflow.." "Rx Parser Accept Counter overflow not occurred,Rx Parser Accept Counter overflow occurred" newline hexmask.long 0x4 0.--30. 1. "RXPAC,Rx Parser Accept Counter This 31-bit counter is implemented whenever a Rx Parser Accept a packet due to AF =1. The counter is cleared when the register is read." line.long 0x8 "DMA_CH0_RX_ERI_CNT,The DMA_CH(#i)_RX_ERI_Cnt registers provides the count of the number of times ERI was asserted." hexmask.long.tbyte 0x8 12.--31. 1. "RESERVED_31_12," newline hexmask.long.word 0x8 0.--11. 1. "ECNT,ERI Counter When ERIC bit of DMA_CH(#i)_RX_Control register is set this counter increments for burst transfer completed by the Rx DMA from the start of packet transfer. This counter will get reset at the start of new packet." tree.end tree "EQOS_DMA_CH1" group.long 0x0++0xB line.long 0x0 "DMA_CH1_CONTROL,The DMA Channeli Control register specifies the MSS value for segmentation. length to skip between two descriptors. and also the features such as header splitting and 8xPBL mode." hexmask.long.byte 0x0 25.--31. 1. "RESERVED_31_25,Reserved." newline rbitfld.long 0x0 24. "RESERVED_SPH,Reserved." "0,1" newline rbitfld.long 0x0 21.--23. "RESERVED_23_21,Reserved." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 18.--20. "DSL,Descriptor Skip Length This bit specifies the Word Dword or Lword number (depending on the 32-bit 64-bit or 128-bit bus) to skip between two unchained descriptors. The address skipping starts from the end of the current descriptor to the start of.." "0,1,2,3,4,5,6,7" newline rbitfld.long 0x0 17. "RESERVED_17,Reserved." "0,1" newline bitfld.long 0x0 16. "PBLX8,8xPBL mode When this bit is set the PBL value programmed in Bits[21:16] in DMA_CH0_Tx_Control and Bits[21:16] in DMA_CH0_Rx_Control is multiplied by eight times. Therefore the DMA transfers the data in 8 16 32 64 128 and 256 beats depending.." "0,1" newline rbitfld.long 0x0 14.--15. "RESERVED_15_14,Reserved." "0,1,2,3" newline hexmask.long.word 0x0 0.--13. 1. "RESERVED_MSS,Reserved." line.long 0x4 "DMA_CH1_TX_CONTROL,The DMA Channeli Transmit Control register controls the Tx features such as PBL. TCP segmentation. and Tx Channel weights." rbitfld.long 0x4 29.--31. "RESERVED_31_29,Reserved." "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 28. "EDSE,Enhanced Descriptor Enable When this bit is set the corresponding channel uses Enhanced Descriptors that are 32 Bytes for both Normal and Context Descriptors. When reset the corresponding channel uses the descriptors that are 16 Bytes. 0x0:.." "Enhanced Descriptor is disabled,Enhanced Descriptor is enabled" newline hexmask.long.byte 0x4 24.--27. 1. "TQOS,Transmit QOS. This field is used to drive arqos_m_o[3:0] or awqos_m_o[3:0] output signals for all transactions of DMA Tx Channel0." newline rbitfld.long 0x4 23. "RESERVED_23,Reserved." "0,1" newline rbitfld.long 0x4 22. "RESERVED_ETIC,Reserved." "0,1" newline hexmask.long.byte 0x4 16.--21. 1. "TXPBL,Transmit Programmable Burst Length These bits indicate the maximum number of beats to be transferred in one DMA block data transfer. The DMA always attempts max burst as specified in PBL each time it starts a burst transfer on the application bus." newline bitfld.long 0x4 15. "IPBL,Ignore PBL Requirement When this bit is set the DMA does not check for PBL number of locations in the MTL before initiating a transfer. If space is not available the MTL may use handshaking to slow the DMA. Note: This bit/mode must not be used.." "Ignore PBL Requirement is disabled,Ignore PBL Requirement is enabled" newline rbitfld.long 0x4 13.--14. "RESERVED_TSE_MODE,Reserved." "0,1,2,3" newline rbitfld.long 0x4 12. "RESERVED_TSE,Reserved." "0,1" newline hexmask.long.byte 0x4 5.--11. 1. "RESERVED_11_5,Reserved." newline bitfld.long 0x4 4. "OSF,Operate on Second Packet When this bit is set it instructs the DMA to process the second packet of the Transmit data even before the status for the first packet is obtained. 0x0: Operate on Second Packet disabled 0x1: Operate on Second Packet enabled" "Operate on Second Packet disabled,Operate on Second Packet enabled" newline rbitfld.long 0x4 1.--3. "RESERVED_TCW,Reserved." "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 0. "ST,Start or Stop Transmission Command When this bit is set transmission is placed in the Running state. The DMA checks the Transmit list at the current position for a packet to be transmitted. The DMA tries to acquire descriptor from either of the.." "Stop Transmission Command,Start Transmission Command" line.long 0x8 "DMA_CH1_RX_CONTROL,The DMA Channeli Receive Control register controls the Rx features such as PBL. buffer size. and extended status." bitfld.long 0x8 31. "RPF,Rx Packet Flush. When this bit is set to 1 then DWC_ether_qos automatically flushes the packet from the Rx Queues destined to this DMA Rx Channel when it is stopped. When this bit remains set and the DMA is re-started by the software driver the.." "Rx Packet Flush is disabled,Rx Packet Flush is enabled" newline rbitfld.long 0x8 28.--30. "RESERVED_30_28,Reserved." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x8 24.--27. 1. "RQOS,Rx AXI4 QOS. This field is used to drive arqos_m_o[3:0] or awqos_m_o[3:0] output signals for all transactions of DMA Rx Channel0." newline rbitfld.long 0x8 23. "RESERVED_23,Reserved." "0,1" newline rbitfld.long 0x8 22. "RESERVED_ERIC,Reserved." "0,1" newline hexmask.long.byte 0x8 16.--21. 1. "RXPBL,Receive Programmable Burst Length These bits indicate the maximum number of beats to be transferred in one DMA block data transfer. The DMA always attempts max burst as specified in PBL each time it starts a burst transfer on the application bus." newline rbitfld.long 0x8 15. "RESERVED_15,Reserved." "0,1" newline hexmask.long.word 0x8 5.--14. 1. "RBSZ_13_Y,Receive Buffer size High RBSZ[13:0] is split into two fields higher RBSZ_13_y and lower RBSZ_x_0. The RBSZ[13:0] field indicates the size of the Rx buffers specified in bytes. The maximum buffer size is limited to 16K bytes. The buffer size is.." newline hexmask.long.byte 0x8 1.--4. 1. "RBSZ_X_0,Receive Buffer size Low RBSZ[13:0] is split into two fields RBSZ_13_y and RBSZ_x_0. The RBSZ_x_0 is the lower field whose width is based on data bus width of the configuration. This field is of width 2 3 or 4 bits for 32-bit 64-bit or.." newline bitfld.long 0x8 0. "SR,Start or Stop Receive When this bit is set the DMA tries to acquire the descriptor from the Receive list and processes the incoming packets. The DMA tries to acquire descriptor from either of the following positions: - The current position in the.." "Stop Receive,Start Receive" group.long 0x10++0x13 line.long 0x0 "DMA_CH1_TXDESC_LIST_HADDRESS,The Channeli Tx Descriptor List HAddress register has the higher 8 or 16 bits of the start address of the Transmit descriptor list. You can write to this register only when the Tx DMA has stopped. that is. the ST bit is set.." hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED_31_Y,Reserved." newline hexmask.long.byte 0x0 0.--7. 1. "TDESHA,Start of Transmit List This field contains the most-significant 8 or 16 bits of the 40- or 48-bit base address of the first descriptor in the Transmit descriptor list." line.long 0x4 "DMA_CH1_TXDESC_LIST_ADDRESS,The Channeli Tx Descriptor List Address register points the DMA to the start of Transmit descriptor list. The descriptor lists reside in the physical memory space of the application and must be Word. Dword. or Lword-aligned.." hexmask.long 0x4 4.--31. 1. "TDESLA,Start of Transmit List This field contains the base address of the first descriptor in the Transmit descriptor list. The DMA ignores the LSB bits (1:0 2:0 or 3:0) for 32-bit 64-bit or 128-bit bus width and internally takes these bits as.." newline hexmask.long.byte 0x4 0.--3. 1. "RESERVED_LSB," line.long 0x8 "DMA_CH1_RXDESC_LIST_HADDRESS,The Channeli Rx Descriptor List HAddress register has the higher 8 or 16 bits of the start address of the Receive descriptor list. Writing to this register is permitted only when reception is stopped. When stopped. this.." hexmask.long.tbyte 0x8 8.--31. 1. "RESERVED_31_Y,Reserved." newline hexmask.long.byte 0x8 0.--7. 1. "RDESHA,Start of Receive List This field contains the most-significant 8 or 16 bits of the 40-bit or 48-bit base address of the first descriptor in the Rx Descriptor list." line.long 0xC "DMA_CH1_RXDESC_LIST_ADDRESS,The Channeli Rx Descriptor List Address register points the DMA to the start of Receive descriptor list. This register points to the start of the Receive Descriptor List. The descriptor lists reside in the physical memory.." hexmask.long 0xC 4.--31. 1. "RDESLA,Start of Receive List This field contains the base address of the first descriptor in the Rx Descriptor list. The DMA ignores the LSB bits (1:0 2:0 or 3:0) for 32-bit 64-bit or 128-bit bus width and internally takes these bits as all-zero." newline hexmask.long.byte 0xC 0.--3. 1. "RESERVED_LSB," line.long 0x10 "DMA_CH1_TXDESC_TAIL_POINTER,The Channeli Tx Descriptor Tail Pointer register points to an offset from the base and indicates the location of the last valid descriptor." hexmask.long 0x10 4.--31. 1. "TDTP,Transmit Descriptor Tail Pointer This field contains the tail pointer for the Tx descriptor ring. The software writes the tail pointer to add more descriptors to the Tx channel. The hardware tries to transmit all packets referenced by the.." newline hexmask.long.byte 0x10 0.--3. 1. "RESERVED_LSB," group.long 0x28++0x17 line.long 0x0 "DMA_CH1_RXDESC_TAIL_POINTER,The Channeli Rx Descriptor Tail Pointer Points to an offset from the base and indicates the location of the last valid descriptor." hexmask.long 0x0 4.--31. 1. "RDTP,Receive Descriptor Tail Pointer This field contains the tail pointer for the Rx descriptor ring. The software writes the tail pointer to add more descriptors to the Rx channel. The hardware tries to write all received packets to the descriptors.." newline hexmask.long.byte 0x0 0.--3. 1. "RESERVED_LSB," line.long 0x4 "DMA_CH1_TXDESC_RING_LENGTH,The Tx Descriptor Ring Length register contains the length of the Transmit descriptor ring." hexmask.long.tbyte 0x4 10.--31. 1. "RESERVED_31_10,Reserved." newline hexmask.long.word 0x4 0.--9. 1. "TDRL,Transmit Descriptor Ring Length This field sets the maximum number of Tx descriptors in the circular descriptor ring. The maximum number of descriptors is limited to 1K descriptors. Synopsys recommends a minimum ring descriptor length of 4. For.." line.long 0x8 "DMA_CH1_RXDESC_RING_LENGTH,The Channeli Rx Descriptor Ring Length register contains the length of the Receive descriptor circular ring." hexmask.long.tbyte 0x8 10.--31. 1. "RESERVED_31_10,Reserved." newline hexmask.long.word 0x8 0.--9. 1. "RDRL,Receive Descriptor Ring Length This register sets the maximum number of Rx descriptors in the circular descriptor ring. The maximum number of descriptors is limited to 1K descriptors. For example You can program any value up to 0x3FF in this field." line.long 0xC "DMA_CH1_INTERRUPT_ENABLE,The Channeli Interrupt Enable register enables the interrupts reported by the Status register." hexmask.long.word 0xC 16.--31. 1. "RESERVED_31_16,Reserved." newline bitfld.long 0xC 15. "NIE,Normal Interrupt Summary Enable When this bit is set the normal interrupt summary is enabled. This bit enables the following interrupts in the DMA_CH0_Status register: - Bit 0: Transmit Interrupt - Bit 2: Transmit Buffer Unavailable - Bit 6: Receive.." "Normal Interrupt Summary is disabled,Normal Interrupt Summary is enabled" newline bitfld.long 0xC 14. "AIE,Abnormal Interrupt Summary Enable When this bit is set the abnormal interrupt summary is enabled. This bit enables the following interrupts in the DMA_CH0_Status register: - Bit 1: Transmit Process Stopped - Bit 7: Rx Buffer Unavailable - Bit 8:.." "Abnormal Interrupt Summary is disabled,Abnormal Interrupt Summary is enabled" newline bitfld.long 0xC 13. "CDEE,Context Descriptor Error Enable When this bit is set along with the AIE bit the Descriptor error interrupt is enabled. When this bit is reset the Descriptor error interrupt is disabled. 0x0: Context Descriptor Error is disabled 0x1: Context.." "Context Descriptor Error is disabled,Context Descriptor Error is enabled" newline bitfld.long 0xC 12. "FBEE,Fatal Bus Error Enable When this bit is set along with the AIE bit the Fatal Bus error interrupt is enabled. When this bit is reset the Fatal Bus Error error interrupt is disabled. 0x0: Fatal Bus Error is disabled 0x1: Fatal Bus Error is enabled" "Fatal Bus Error is disabled,Fatal Bus Error is enabled" newline bitfld.long 0xC 11. "ERIE,Early Receive Interrupt Enable When this bit is set along with the NIE bit the Early Receive interrupt is enabled. When this bit is reset the Early Receive interrupt is disabled. 0x0: Early Receive Interrupt is disabled 0x1: Early Receive.." "Early Receive Interrupt is disabled,Early Receive Interrupt is enabled" newline bitfld.long 0xC 10. "ETIE,Early Transmit Interrupt Enable When this bit is set along with the AIE bit the Early Transmit interrupt is enabled. When this bit is reset the Early Transmit interrupt is disabled. 0x0: Early Transmit Interrupt is disabled 0x1: Early Transmit.." "Early Transmit Interrupt is disabled,Early Transmit Interrupt is enabled" newline bitfld.long 0xC 9. "RWTE,Receive Watchdog Timeout Enable When this bit is set along with the AIE bit the Receive Watchdog Timeout interrupt is enabled. When this bit is reset the Receive Watchdog Timeout interrupt is disabled. 0x0: Receive Watchdog Timeout is disabled.." "Receive Watchdog Timeout is disabled,Receive Watchdog Timeout is enabled" newline bitfld.long 0xC 8. "RSE,Receive Stopped Enable When this bit is set along with the AIE bit the Receive Stopped Interrupt is enabled. When this bit is reset the Receive Stopped interrupt is disabled. 0x0: Receive Stopped is disabled 0x1: Receive Stopped is enabled" "Receive Stopped is disabled,Receive Stopped is enabled" newline bitfld.long 0xC 7. "RBUE,Receive Buffer Unavailable Enable When this bit is set along with the AIE bit the Receive Buffer Unavailable interrupt is enabled. When this bit is reset the Receive Buffer Unavailable interrupt is disabled. 0x0: Receive Buffer Unavailable is.." "Receive Buffer Unavailable is disabled,Receive Buffer Unavailable is enabled" newline bitfld.long 0xC 6. "RIE,Receive Interrupt Enable When this bit is set along with the NIE bit the Receive Interrupt is enabled. When this bit is reset the Receive Interrupt is disabled. 0x0: Receive Interrupt is disabled 0x1: Receive Interrupt is enabled" "Receive Interrupt is disabled,Receive Interrupt is enabled" newline rbitfld.long 0xC 3.--5. "RESERVED_5_3,Reserved." "0,1,2,3,4,5,6,7" newline bitfld.long 0xC 2. "TBUE,Transmit Buffer Unavailable Enable When this bit is set along with the NIE bit the Transmit Buffer Unavailable interrupt is enabled. When this bit is reset the Transmit Buffer Unavailable interrupt is disabled. 0x0: Transmit Buffer Unavailable is.." "Transmit Buffer Unavailable is disabled,Transmit Buffer Unavailable is enabled" newline bitfld.long 0xC 1. "TXSE,Transmit Stopped Enable When this bit is set along with the AIE bit the Transmission Stopped interrupt is enabled. When this bit is reset the Transmission Stopped interrupt is disabled. 0x0: Transmit Stopped is disabled 0x1: Transmit Stopped is.." "Transmit Stopped is disabled,Transmit Stopped is enabled" newline bitfld.long 0xC 0. "TIE,Transmit Interrupt Enable When this bit is set along with the NIE bit the Transmit Interrupt is enabled. When this bit is reset the Transmit Interrupt is disabled. 0x0: Transmit Interrupt is disabled 0x1: Transmit Interrupt is enabled" "Transmit Interrupt is disabled,Transmit Interrupt is enabled" line.long 0x10 "DMA_CH1_RX_INTERRUPT_WATCHDOG_TIMER,The Receive Interrupt Watchdog Timer register indicates the watchdog timeout for Receive Interrupt (RI) from the DMA. When this register is written with a non-zero value. it enables the watchdog timer for the RI bit of.." hexmask.long.word 0x10 18.--31. 1. "RESERVED_31_18,Reserved." newline bitfld.long 0x10 16.--17. "RWTU,Receive Interrupt Watchdog Timer Count Units This fields indicates the number of system clock cycles corresponding to one unit in RWT field. - 2'b00: 256 - 2'b01: 512 - 2'b10: 1024 - 2'b11: 2048 For example when RWT=2 and RWTU=1 the watchdog timer.." "0,1,2,3" newline hexmask.long.byte 0x10 8.--15. 1. "RESERVED_15_8,Reserved." newline hexmask.long.byte 0x10 0.--7. 1. "RWT,Receive Interrupt Watchdog Timer Count This field indicates the number of system clock cycles multiplied by factor indicated in RWTU field for which the watchdog timer is set. The watchdog timer is triggered with the programmed value after the Rx.." line.long 0x14 "DMA_CH1_SLOT_FUNCTION_CONTROL_STATUS,The Slot Function Control and Status register contains the control bits for slot function and the status for Transmit path." hexmask.long.word 0x14 20.--31. 1. "RESERVED_31_20,Reserved." newline hexmask.long.byte 0x14 16.--19. 1. "RSN,Reference Slot Number This field gives the current value of the reference slot number in the DMA. It is used for slot comparison." newline hexmask.long.word 0x14 4.--15. 1. "SIV,Slot Interval Value This field controls the period of the slot interval in which the TxDMA fetches the scheduled packets. A value of 0 specifies the slot interval of 1 us while the maximum value 4095 specifies the slot interval of 4096us. The.." newline rbitfld.long 0x14 2.--3. "RESERVED_3_2,Reserved." "0,1,2,3" newline bitfld.long 0x14 1. "ASC,Advance Slot Check When set this bit enables the DMA to fetch the data from the buffer when the slot number (SLOTNUM) programmed in the Tx descriptor is - equal to the reference slot number given in the RSN field or - ahead of the reference slot.." "Advance Slot Check is disabled,Advance Slot Check is enabled" newline bitfld.long 0x14 0. "ESC,Enable Slot Comparison When set this bit enables the checking of the slot numbers programmed in the Tx descriptor with the current reference given in the RSN field. The DMA fetches the data from the corresponding buffer only when the slot number is.." "Slot Comparison is disabled,Slot Comparison is enabled" rgroup.long 0x44++0x3 line.long 0x0 "DMA_CH1_CURRENT_APP_TXDESC,The Channeli Current Application Transmit Descriptor register points to the current Transmit descriptor read by the DMA." hexmask.long 0x0 0.--31. 1. "CURTDESAPTR,Application Transmit Descriptor Address Pointer The DMA updates this pointer during Tx operation. This pointer is cleared on reset." rgroup.long 0x4C++0x13 line.long 0x0 "DMA_CH1_CURRENT_APP_RXDESC,The Channeli Current Application Receive Descriptor register points to the current Receive descriptor read by the DMA." hexmask.long 0x0 0.--31. 1. "CURRDESAPTR,Application Receive Descriptor Address Pointer The DMA updates this pointer during Rx operation. This pointer is cleared on reset." line.long 0x4 "DMA_CH1_CURRENT_APP_TXBUFFER_H,The Channeli Current Application Transmit Buffer Address High register has the higher 8 or 16 bits of the current address of the Transmit buffer address read by the DMA." hexmask.long.tbyte 0x4 8.--31. 1. "RESERVED_31_Y,Reserved." newline hexmask.long.byte 0x4 0.--7. 1. "CURTBUFAPTRH,Application Transmit Buffer Address Pointer The DMA updates this pointer during Tx operation. This pointer is cleared on reset." line.long 0x8 "DMA_CH1_CURRENT_APP_TXBUFFER,The Channeli Current Application Transmit Buffer Address register points to the current Tx buffer address read by the DMA." hexmask.long 0x8 0.--31. 1. "CURTBUFAPTR,Application Transmit Buffer Address Pointer The DMA updates this pointer during Tx operation. This pointer is cleared on reset." line.long 0xC "DMA_CH1_CURRENT_APP_RXBUFFER_H,The Channeli Current Application Receive Buffer Address High register has the higher 8 or 16 bits of the current address of the Receive buffer address read by the DMA." hexmask.long.tbyte 0xC 8.--31. 1. "RESERVED_31_Y,Reserved." newline hexmask.long.byte 0xC 0.--7. 1. "CURRBUFAPTRH,Application Receive Buffer Address Pointer The DMA updates this pointer during Rx operation. This pointer is cleared on reset." line.long 0x10 "DMA_CH1_CURRENT_APP_RXBUFFER,The Channel 0 Current Application Receive Buffer Address register points to the current Rx buffer address read by the DMA." hexmask.long 0x10 0.--31. 1. "CURRBUFAPTR,Application Receive Buffer Address Pointer The DMA updates this pointer during Rx operation. This pointer is cleared on reset." group.long 0x60++0x3 line.long 0x0 "DMA_CH1_STATUS,The software driver (application) reads the Status register during interrupt service routine or polling to determine the status of the DMA. Note: The number of DMA_CH[n]_Status register in the configuration is the higher of number of Rx.." hexmask.long.word 0x0 22.--31. 1. "RESERVED_31_22,Reserved." newline rbitfld.long 0x0 19.--21. "REB,Rx DMA Error Bits This field indicates the type of error that caused a Bus Error. For example error response on the AHB or AXI interface. - Bit 21 -- 1'b1: Error during data transfer by Rx DMA -- 1'b0: No Error during data transfer by Rx DMA - Bit.." "Error during write transfer,Error during read transfer,?,?,?,?,?,?" newline rbitfld.long 0x0 16.--18. "TEB,Tx DMA Error Bits This field indicates the type of error that caused a Bus Error. For example error response on the AHB or AXI interface. - Bit 18 -- 1'b1: Error during data transfer by Tx DMA -- 1'b0: No Error during data transfer by Tx DMA - Bit.." "Error during write transfer,Error during read transfer,?,?,?,?,?,?" newline bitfld.long 0x0 15. "NIS,Normal Interrupt Summary Normal Interrupt Summary bit value is the logical OR of the following bits when the corresponding interrupt bits are enabled in the DMA_CH0_Interrupt_Enable register: - Bit 0: Transmit Interrupt - Bit 2: Transmit Buffer.." "Normal Interrupt Summary status not detected,Normal Interrupt Summary status detected" newline bitfld.long 0x0 14. "AIS,Abnormal Interrupt Summary Abnormal Interrupt Summary bit value is the logical OR of the following when the corresponding interrupt bits are enabled in the DMA_CH0_Interrupt_Enable register: - Bit 1: Transmit Process Stopped - Bit 7: Receive Buffer.." "Abnormal Interrupt Summary status not detected,Abnormal Interrupt Summary status detected" newline bitfld.long 0x0 13. "CDE,Context Descriptor Error This bit indicates that the DMA Tx/Rx engine received a descriptor error which indicates invalid context in the middle of packet flow ( intermediate descriptor) or all one's descriptor in Tx case and on Rx side it indicates.." "Context Descriptor Error status not detected,Context Descriptor Error status detected" newline bitfld.long 0x0 12. "FBE,Fatal Bus Error This bit indicates that a bus error occurred (as described in the EB field). When this bit is set the corresponding DMA channel engine disables all bus accesses. Access restriction applies. Self-set to 1 on internal event. Setting 1.." "Fatal Bus Error status not detected,Fatal Bus Error status detected" newline bitfld.long 0x0 11. "ERI,Early Receive Interrupt This bit when set indicates that the RxDMA has completed the transfer of packet data to the memory. In configs supporting ERIC When ERIC=0 this bit is set only after the Rx DMA has filled up a complete receive buffer with.." "Early Receive Interrupt status not detected,Early Receive Interrupt status detected" newline bitfld.long 0x0 10. "ETI,Early Transmit Interrupt This bit when set indicates that the TxDMA has completed the transfer of packet data to the MTL TXFIFO memory. In configs supporting ERIC: When ETIC=0 this bit is set only after the Tx DMA has transferred a complete packet.." "Early Transmit Interrupt status not detected,Early Transmit Interrupt status detected" newline bitfld.long 0x0 9. "RWT,Receive Watchdog Timeout This bit is asserted when a packet with length greater than 2 048 bytes (10 240 bytes when Jumbo Packet mode is enabled) is received. 0x1: Receive Watchdog Timeout status detected 0x0: Receive Watchdog Timeout status not.." "Receive Watchdog Timeout status not detected,Receive Watchdog Timeout status detected" newline bitfld.long 0x0 8. "RPS,Receive Process Stopped This bit is asserted when the Rx process enters the Stopped state. Access restriction applies. Self-set to 1 on internal event. Setting 1 clears. Setting 0 has no effect. 0x1: Receive Process Stopped status detected 0x0:.." "Receive Process Stopped status not detected,Receive Process Stopped status detected" newline bitfld.long 0x0 7. "RBU,Receive Buffer Unavailable This bit indicates that the application owns the next descriptor in the Receive list and the DMA cannot acquire it. The Rx process is suspended. To resume processing Rx descriptors the application should change the.." "Receive Buffer Unavailable status not detected,Receive Buffer Unavailable status detected" newline bitfld.long 0x0 6. "RI,Receive Interrupt This bit indicates that the packet reception is complete. When packet reception is complete Bit 31 of RDES3 is reset in the last descriptor and the specific packet status information is updated in the descriptor. The reception.." "Receive Interrupt status not detected,Receive Interrupt status detected" newline rbitfld.long 0x0 3.--5. "RESERVED_5_3,Reserved." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 2. "TBU,Transmit Buffer Unavailable This bit indicates that the application owns the next descriptor in the Transmit list and the DMA cannot acquire it. Transmission is suspended. The TPS0 field of the DMA_Debug_Status0 register explains the Transmit.." "Transmit Buffer Unavailable status not detected,Transmit Buffer Unavailable status detected" newline bitfld.long 0x0 1. "TPS,Transmit Process Stopped This bit is set when the transmission is stopped. Access restriction applies. Self-set to 1 on internal event. Setting 1 clears. Setting 0 has no effect. 0x1: Transmit Process Stopped status detected 0x0: Transmit Process.." "Transmit Process Stopped status not detected,Transmit Process Stopped status detected" newline bitfld.long 0x0 0. "TI,Transmit Interrupt This bit indicates that the packet transmission is complete. When transmission is complete Bit 31 of TDES3 is reset in the last descriptor and the specific packet status information is updated in the descriptor. Access restriction.." "Transmit Interrupt status not detected,Transmit Interrupt status detected" rgroup.long 0x64++0xB line.long 0x0 "DMA_CH1_MISS_FRAME_CNT,This register has the number of packet counter that got dropped by the DMA either due to Bus Error or due to programming RPF field in DMA_CH{i}_Rx_Control register." hexmask.long.word 0x0 16.--31. 1. "RESERVED_31_16,Reserved." newline bitfld.long 0x0 15. "MFCO,Overflow status of the MFC Counter When this bit is set then the MFC counter does not get incremented further. The bit gets cleared when this register is read. Access restriction applies. Clears on read. Self-set to 1 on internal event. 0x1: Miss.." "Miss Frame Counter overflow not occurred,Miss Frame Counter overflow occurred" newline hexmask.long.byte 0x0 11.--14. 1. "RESERVED_14_11,Reserved." newline hexmask.long.word 0x0 0.--10. 1. "MFC,Dropped Packet Counters This counter indicates the number of packet counters that are dropped by the DMA either because of bus error or because of programing RPF field in DMA_CH{i}_Rx_Control register. The counter gets cleared when this register is.." line.long 0x4 "DMA_CH1_RXP_ACCEPT_CNT,The DMA_CH(#i)_RXP_Accept_Cnt registers provides the count of the number of frames accepted by Rx Parser." bitfld.long 0x4 31. "RXPACOF,Rx Parser Accept Counter Overflow Bit When set this bit indicates that the RXPAC Counter field crossed the maximum limit. Access restriction applies. Clears on read. Self-set to 1 on internal event. 0x1: Rx Parser Accept Counter overflow.." "Rx Parser Accept Counter overflow not occurred,Rx Parser Accept Counter overflow occurred" newline hexmask.long 0x4 0.--30. 1. "RXPAC,Rx Parser Accept Counter This 31-bit counter is implemented whenever a Rx Parser Accept a packet due to AF =1. The counter is cleared when the register is read." line.long 0x8 "DMA_CH1_RX_ERI_CNT,The DMA_CH(#i)_RX_ERI_Cnt registers provides the count of the number of times ERI was asserted." hexmask.long.tbyte 0x8 12.--31. 1. "RESERVED_31_12," newline hexmask.long.word 0x8 0.--11. 1. "ECNT,ERI Counter When ERIC bit of DMA_CH(#i)_RX_Control register is set this counter increments for burst transfer completed by the Rx DMA from the start of packet transfer. This counter will get reset at the start of new packet." tree.end tree "EQOS_DMA_CH2" group.long 0x0++0xB line.long 0x0 "DMA_CH2_CONTROL,The DMA Channeli Control register specifies the MSS value for segmentation. length to skip between two descriptors. and also the features such as header splitting and 8xPBL mode." hexmask.long.byte 0x0 25.--31. 1. "RESERVED_31_25,Reserved." newline rbitfld.long 0x0 24. "RESERVED_SPH,Reserved." "0,1" newline rbitfld.long 0x0 21.--23. "RESERVED_23_21,Reserved." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 18.--20. "DSL,Descriptor Skip Length This bit specifies the Word Dword or Lword number (depending on the 32-bit 64-bit or 128-bit bus) to skip between two unchained descriptors. The address skipping starts from the end of the current descriptor to the start of.." "0,1,2,3,4,5,6,7" newline rbitfld.long 0x0 17. "RESERVED_17,Reserved." "0,1" newline bitfld.long 0x0 16. "PBLX8,8xPBL mode When this bit is set the PBL value programmed in Bits[21:16] in DMA_CH0_Tx_Control and Bits[21:16] in DMA_CH0_Rx_Control is multiplied by eight times. Therefore the DMA transfers the data in 8 16 32 64 128 and 256 beats depending.." "0,1" newline rbitfld.long 0x0 14.--15. "RESERVED_15_14,Reserved." "0,1,2,3" newline hexmask.long.word 0x0 0.--13. 1. "RESERVED_MSS,Reserved." line.long 0x4 "DMA_CH2_TX_CONTROL,The DMA Channeli Transmit Control register controls the Tx features such as PBL. TCP segmentation. and Tx Channel weights." rbitfld.long 0x4 29.--31. "RESERVED_31_29,Reserved." "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 28. "EDSE,Enhanced Descriptor Enable When this bit is set the corresponding channel uses Enhanced Descriptors that are 32 Bytes for both Normal and Context Descriptors. When reset the corresponding channel uses the descriptors that are 16 Bytes. 0x0:.." "Enhanced Descriptor is disabled,Enhanced Descriptor is enabled" newline hexmask.long.byte 0x4 24.--27. 1. "TQOS,Transmit QOS. This field is used to drive arqos_m_o[3:0] or awqos_m_o[3:0] output signals for all transactions of DMA Tx Channel0." newline rbitfld.long 0x4 23. "RESERVED_23,Reserved." "0,1" newline rbitfld.long 0x4 22. "RESERVED_ETIC,Reserved." "0,1" newline hexmask.long.byte 0x4 16.--21. 1. "TXPBL,Transmit Programmable Burst Length These bits indicate the maximum number of beats to be transferred in one DMA block data transfer. The DMA always attempts max burst as specified in PBL each time it starts a burst transfer on the application bus." newline bitfld.long 0x4 15. "IPBL,Ignore PBL Requirement When this bit is set the DMA does not check for PBL number of locations in the MTL before initiating a transfer. If space is not available the MTL may use handshaking to slow the DMA. Note: This bit/mode must not be used.." "Ignore PBL Requirement is disabled,Ignore PBL Requirement is enabled" newline rbitfld.long 0x4 13.--14. "RESERVED_TSE_MODE,Reserved." "0,1,2,3" newline rbitfld.long 0x4 12. "RESERVED_TSE,Reserved." "0,1" newline hexmask.long.byte 0x4 5.--11. 1. "RESERVED_11_5,Reserved." newline bitfld.long 0x4 4. "OSF,Operate on Second Packet When this bit is set it instructs the DMA to process the second packet of the Transmit data even before the status for the first packet is obtained. 0x0: Operate on Second Packet disabled 0x1: Operate on Second Packet enabled" "Operate on Second Packet disabled,Operate on Second Packet enabled" newline rbitfld.long 0x4 1.--3. "RESERVED_TCW,Reserved." "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 0. "ST,Start or Stop Transmission Command When this bit is set transmission is placed in the Running state. The DMA checks the Transmit list at the current position for a packet to be transmitted. The DMA tries to acquire descriptor from either of the.." "Stop Transmission Command,Start Transmission Command" line.long 0x8 "DMA_CH2_RX_CONTROL,The DMA Channeli Receive Control register controls the Rx features such as PBL. buffer size. and extended status." bitfld.long 0x8 31. "RPF,Rx Packet Flush. When this bit is set to 1 then DWC_ether_qos automatically flushes the packet from the Rx Queues destined to this DMA Rx Channel when it is stopped. When this bit remains set and the DMA is re-started by the software driver the.." "Rx Packet Flush is disabled,Rx Packet Flush is enabled" newline rbitfld.long 0x8 28.--30. "RESERVED_30_28,Reserved." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x8 24.--27. 1. "RQOS,Rx AXI4 QOS. This field is used to drive arqos_m_o[3:0] or awqos_m_o[3:0] output signals for all transactions of DMA Rx Channel0." newline rbitfld.long 0x8 23. "RESERVED_23,Reserved." "0,1" newline rbitfld.long 0x8 22. "RESERVED_ERIC,Reserved." "0,1" newline hexmask.long.byte 0x8 16.--21. 1. "RXPBL,Receive Programmable Burst Length These bits indicate the maximum number of beats to be transferred in one DMA block data transfer. The DMA always attempts max burst as specified in PBL each time it starts a burst transfer on the application bus." newline rbitfld.long 0x8 15. "RESERVED_15,Reserved." "0,1" newline hexmask.long.word 0x8 5.--14. 1. "RBSZ_13_Y,Receive Buffer size High RBSZ[13:0] is split into two fields higher RBSZ_13_y and lower RBSZ_x_0. The RBSZ[13:0] field indicates the size of the Rx buffers specified in bytes. The maximum buffer size is limited to 16K bytes. The buffer size is.." newline hexmask.long.byte 0x8 1.--4. 1. "RBSZ_X_0,Receive Buffer size Low RBSZ[13:0] is split into two fields RBSZ_13_y and RBSZ_x_0. The RBSZ_x_0 is the lower field whose width is based on data bus width of the configuration. This field is of width 2 3 or 4 bits for 32-bit 64-bit or.." newline bitfld.long 0x8 0. "SR,Start or Stop Receive When this bit is set the DMA tries to acquire the descriptor from the Receive list and processes the incoming packets. The DMA tries to acquire descriptor from either of the following positions: - The current position in the.." "Stop Receive,Start Receive" group.long 0x10++0x13 line.long 0x0 "DMA_CH2_TXDESC_LIST_HADDRESS,The Channeli Tx Descriptor List HAddress register has the higher 8 or 16 bits of the start address of the Transmit descriptor list. You can write to this register only when the Tx DMA has stopped. that is. the ST bit is set.." hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED_31_Y,Reserved." newline hexmask.long.byte 0x0 0.--7. 1. "TDESHA,Start of Transmit List This field contains the most-significant 8 or 16 bits of the 40- or 48-bit base address of the first descriptor in the Transmit descriptor list." line.long 0x4 "DMA_CH2_TXDESC_LIST_ADDRESS,The Channeli Tx Descriptor List Address register points the DMA to the start of Transmit descriptor list. The descriptor lists reside in the physical memory space of the application and must be Word. Dword. or Lword-aligned.." hexmask.long 0x4 4.--31. 1. "TDESLA,Start of Transmit List This field contains the base address of the first descriptor in the Transmit descriptor list. The DMA ignores the LSB bits (1:0 2:0 or 3:0) for 32-bit 64-bit or 128-bit bus width and internally takes these bits as.." newline hexmask.long.byte 0x4 0.--3. 1. "RESERVED_LSB," line.long 0x8 "DMA_CH2_RXDESC_LIST_HADDRESS,The Channeli Rx Descriptor List HAddress register has the higher 8 or 16 bits of the start address of the Receive descriptor list. Writing to this register is permitted only when reception is stopped. When stopped. this.." hexmask.long.tbyte 0x8 8.--31. 1. "RESERVED_31_Y,Reserved." newline hexmask.long.byte 0x8 0.--7. 1. "RDESHA,Start of Receive List This field contains the most-significant 8 or 16 bits of the 40-bit or 48-bit base address of the first descriptor in the Rx Descriptor list." line.long 0xC "DMA_CH2_RXDESC_LIST_ADDRESS,The Channeli Rx Descriptor List Address register points the DMA to the start of Receive descriptor list. This register points to the start of the Receive Descriptor List. The descriptor lists reside in the physical memory.." hexmask.long 0xC 4.--31. 1. "RDESLA,Start of Receive List This field contains the base address of the first descriptor in the Rx Descriptor list. The DMA ignores the LSB bits (1:0 2:0 or 3:0) for 32-bit 64-bit or 128-bit bus width and internally takes these bits as all-zero." newline hexmask.long.byte 0xC 0.--3. 1. "RESERVED_LSB," line.long 0x10 "DMA_CH2_TXDESC_TAIL_POINTER,The Channeli Tx Descriptor Tail Pointer register points to an offset from the base and indicates the location of the last valid descriptor." hexmask.long 0x10 4.--31. 1. "TDTP,Transmit Descriptor Tail Pointer This field contains the tail pointer for the Tx descriptor ring. The software writes the tail pointer to add more descriptors to the Tx channel. The hardware tries to transmit all packets referenced by the.." newline hexmask.long.byte 0x10 0.--3. 1. "RESERVED_LSB," group.long 0x28++0x17 line.long 0x0 "DMA_CH2_RXDESC_TAIL_POINTER,The Channeli Rx Descriptor Tail Pointer Points to an offset from the base and indicates the location of the last valid descriptor." hexmask.long 0x0 4.--31. 1. "RDTP,Receive Descriptor Tail Pointer This field contains the tail pointer for the Rx descriptor ring. The software writes the tail pointer to add more descriptors to the Rx channel. The hardware tries to write all received packets to the descriptors.." newline hexmask.long.byte 0x0 0.--3. 1. "RESERVED_LSB," line.long 0x4 "DMA_CH2_TXDESC_RING_LENGTH,The Tx Descriptor Ring Length register contains the length of the Transmit descriptor ring." hexmask.long.tbyte 0x4 10.--31. 1. "RESERVED_31_10,Reserved." newline hexmask.long.word 0x4 0.--9. 1. "TDRL,Transmit Descriptor Ring Length This field sets the maximum number of Tx descriptors in the circular descriptor ring. The maximum number of descriptors is limited to 1K descriptors. Synopsys recommends a minimum ring descriptor length of 4. For.." line.long 0x8 "DMA_CH2_RXDESC_RING_LENGTH,The Channeli Rx Descriptor Ring Length register contains the length of the Receive descriptor circular ring." hexmask.long.tbyte 0x8 10.--31. 1. "RESERVED_31_10,Reserved." newline hexmask.long.word 0x8 0.--9. 1. "RDRL,Receive Descriptor Ring Length This register sets the maximum number of Rx descriptors in the circular descriptor ring. The maximum number of descriptors is limited to 1K descriptors. For example You can program any value up to 0x3FF in this field." line.long 0xC "DMA_CH2_INTERRUPT_ENABLE,The Channeli Interrupt Enable register enables the interrupts reported by the Status register." hexmask.long.word 0xC 16.--31. 1. "RESERVED_31_16,Reserved." newline bitfld.long 0xC 15. "NIE,Normal Interrupt Summary Enable When this bit is set the normal interrupt summary is enabled. This bit enables the following interrupts in the DMA_CH0_Status register: - Bit 0: Transmit Interrupt - Bit 2: Transmit Buffer Unavailable - Bit 6: Receive.." "Normal Interrupt Summary is disabled,Normal Interrupt Summary is enabled" newline bitfld.long 0xC 14. "AIE,Abnormal Interrupt Summary Enable When this bit is set the abnormal interrupt summary is enabled. This bit enables the following interrupts in the DMA_CH0_Status register: - Bit 1: Transmit Process Stopped - Bit 7: Rx Buffer Unavailable - Bit 8:.." "Abnormal Interrupt Summary is disabled,Abnormal Interrupt Summary is enabled" newline bitfld.long 0xC 13. "CDEE,Context Descriptor Error Enable When this bit is set along with the AIE bit the Descriptor error interrupt is enabled. When this bit is reset the Descriptor error interrupt is disabled. 0x0: Context Descriptor Error is disabled 0x1: Context.." "Context Descriptor Error is disabled,Context Descriptor Error is enabled" newline bitfld.long 0xC 12. "FBEE,Fatal Bus Error Enable When this bit is set along with the AIE bit the Fatal Bus error interrupt is enabled. When this bit is reset the Fatal Bus Error error interrupt is disabled. 0x0: Fatal Bus Error is disabled 0x1: Fatal Bus Error is enabled" "Fatal Bus Error is disabled,Fatal Bus Error is enabled" newline bitfld.long 0xC 11. "ERIE,Early Receive Interrupt Enable When this bit is set along with the NIE bit the Early Receive interrupt is enabled. When this bit is reset the Early Receive interrupt is disabled. 0x0: Early Receive Interrupt is disabled 0x1: Early Receive.." "Early Receive Interrupt is disabled,Early Receive Interrupt is enabled" newline bitfld.long 0xC 10. "ETIE,Early Transmit Interrupt Enable When this bit is set along with the AIE bit the Early Transmit interrupt is enabled. When this bit is reset the Early Transmit interrupt is disabled. 0x0: Early Transmit Interrupt is disabled 0x1: Early Transmit.." "Early Transmit Interrupt is disabled,Early Transmit Interrupt is enabled" newline bitfld.long 0xC 9. "RWTE,Receive Watchdog Timeout Enable When this bit is set along with the AIE bit the Receive Watchdog Timeout interrupt is enabled. When this bit is reset the Receive Watchdog Timeout interrupt is disabled. 0x0: Receive Watchdog Timeout is disabled.." "Receive Watchdog Timeout is disabled,Receive Watchdog Timeout is enabled" newline bitfld.long 0xC 8. "RSE,Receive Stopped Enable When this bit is set along with the AIE bit the Receive Stopped Interrupt is enabled. When this bit is reset the Receive Stopped interrupt is disabled. 0x0: Receive Stopped is disabled 0x1: Receive Stopped is enabled" "Receive Stopped is disabled,Receive Stopped is enabled" newline bitfld.long 0xC 7. "RBUE,Receive Buffer Unavailable Enable When this bit is set along with the AIE bit the Receive Buffer Unavailable interrupt is enabled. When this bit is reset the Receive Buffer Unavailable interrupt is disabled. 0x0: Receive Buffer Unavailable is.." "Receive Buffer Unavailable is disabled,Receive Buffer Unavailable is enabled" newline bitfld.long 0xC 6. "RIE,Receive Interrupt Enable When this bit is set along with the NIE bit the Receive Interrupt is enabled. When this bit is reset the Receive Interrupt is disabled. 0x0: Receive Interrupt is disabled 0x1: Receive Interrupt is enabled" "Receive Interrupt is disabled,Receive Interrupt is enabled" newline rbitfld.long 0xC 3.--5. "RESERVED_5_3,Reserved." "0,1,2,3,4,5,6,7" newline bitfld.long 0xC 2. "TBUE,Transmit Buffer Unavailable Enable When this bit is set along with the NIE bit the Transmit Buffer Unavailable interrupt is enabled. When this bit is reset the Transmit Buffer Unavailable interrupt is disabled. 0x0: Transmit Buffer Unavailable is.." "Transmit Buffer Unavailable is disabled,Transmit Buffer Unavailable is enabled" newline bitfld.long 0xC 1. "TXSE,Transmit Stopped Enable When this bit is set along with the AIE bit the Transmission Stopped interrupt is enabled. When this bit is reset the Transmission Stopped interrupt is disabled. 0x0: Transmit Stopped is disabled 0x1: Transmit Stopped is.." "Transmit Stopped is disabled,Transmit Stopped is enabled" newline bitfld.long 0xC 0. "TIE,Transmit Interrupt Enable When this bit is set along with the NIE bit the Transmit Interrupt is enabled. When this bit is reset the Transmit Interrupt is disabled. 0x0: Transmit Interrupt is disabled 0x1: Transmit Interrupt is enabled" "Transmit Interrupt is disabled,Transmit Interrupt is enabled" line.long 0x10 "DMA_CH2_RX_INTERRUPT_WATCHDOG_TIMER,The Receive Interrupt Watchdog Timer register indicates the watchdog timeout for Receive Interrupt (RI) from the DMA. When this register is written with a non-zero value. it enables the watchdog timer for the RI bit of.." hexmask.long.word 0x10 18.--31. 1. "RESERVED_31_18,Reserved." newline bitfld.long 0x10 16.--17. "RWTU,Receive Interrupt Watchdog Timer Count Units This fields indicates the number of system clock cycles corresponding to one unit in RWT field. - 2'b00: 256 - 2'b01: 512 - 2'b10: 1024 - 2'b11: 2048 For example when RWT=2 and RWTU=1 the watchdog timer.." "0,1,2,3" newline hexmask.long.byte 0x10 8.--15. 1. "RESERVED_15_8,Reserved." newline hexmask.long.byte 0x10 0.--7. 1. "RWT,Receive Interrupt Watchdog Timer Count This field indicates the number of system clock cycles multiplied by factor indicated in RWTU field for which the watchdog timer is set. The watchdog timer is triggered with the programmed value after the Rx.." line.long 0x14 "DMA_CH2_SLOT_FUNCTION_CONTROL_STATUS,The Slot Function Control and Status register contains the control bits for slot function and the status for Transmit path." hexmask.long.word 0x14 20.--31. 1. "RESERVED_31_20,Reserved." newline hexmask.long.byte 0x14 16.--19. 1. "RSN,Reference Slot Number This field gives the current value of the reference slot number in the DMA. It is used for slot comparison." newline hexmask.long.word 0x14 4.--15. 1. "SIV,Slot Interval Value This field controls the period of the slot interval in which the TxDMA fetches the scheduled packets. A value of 0 specifies the slot interval of 1 us while the maximum value 4095 specifies the slot interval of 4096us. The.." newline rbitfld.long 0x14 2.--3. "RESERVED_3_2,Reserved." "0,1,2,3" newline bitfld.long 0x14 1. "ASC,Advance Slot Check When set this bit enables the DMA to fetch the data from the buffer when the slot number (SLOTNUM) programmed in the Tx descriptor is - equal to the reference slot number given in the RSN field or - ahead of the reference slot.." "Advance Slot Check is disabled,Advance Slot Check is enabled" newline bitfld.long 0x14 0. "ESC,Enable Slot Comparison When set this bit enables the checking of the slot numbers programmed in the Tx descriptor with the current reference given in the RSN field. The DMA fetches the data from the corresponding buffer only when the slot number is.." "Slot Comparison is disabled,Slot Comparison is enabled" rgroup.long 0x44++0x3 line.long 0x0 "DMA_CH2_CURRENT_APP_TXDESC,The Channeli Current Application Transmit Descriptor register points to the current Transmit descriptor read by the DMA." hexmask.long 0x0 0.--31. 1. "CURTDESAPTR,Application Transmit Descriptor Address Pointer The DMA updates this pointer during Tx operation. This pointer is cleared on reset." rgroup.long 0x4C++0x13 line.long 0x0 "DMA_CH2_CURRENT_APP_RXDESC,The Channeli Current Application Receive Descriptor register points to the current Receive descriptor read by the DMA." hexmask.long 0x0 0.--31. 1. "CURRDESAPTR,Application Receive Descriptor Address Pointer The DMA updates this pointer during Rx operation. This pointer is cleared on reset." line.long 0x4 "DMA_CH2_CURRENT_APP_TXBUFFER_H,The Channeli Current Application Transmit Buffer Address High register has the higher 8 or 16 bits of the current address of the Transmit buffer address read by the DMA." hexmask.long.tbyte 0x4 8.--31. 1. "RESERVED_31_Y,Reserved." newline hexmask.long.byte 0x4 0.--7. 1. "CURTBUFAPTRH,Application Transmit Buffer Address Pointer The DMA updates this pointer during Tx operation. This pointer is cleared on reset." line.long 0x8 "DMA_CH2_CURRENT_APP_TXBUFFER,The Channeli Current Application Transmit Buffer Address register points to the current Tx buffer address read by the DMA." hexmask.long 0x8 0.--31. 1. "CURTBUFAPTR,Application Transmit Buffer Address Pointer The DMA updates this pointer during Tx operation. This pointer is cleared on reset." line.long 0xC "DMA_CH2_CURRENT_APP_RXBUFFER_H,The Channeli Current Application Receive Buffer Address High register has the higher 8 or 16 bits of the current address of the Receive buffer address read by the DMA." hexmask.long.tbyte 0xC 8.--31. 1. "RESERVED_31_Y,Reserved." newline hexmask.long.byte 0xC 0.--7. 1. "CURRBUFAPTRH,Application Receive Buffer Address Pointer The DMA updates this pointer during Rx operation. This pointer is cleared on reset." line.long 0x10 "DMA_CH2_CURRENT_APP_RXBUFFER,The Channel 0 Current Application Receive Buffer Address register points to the current Rx buffer address read by the DMA." hexmask.long 0x10 0.--31. 1. "CURRBUFAPTR,Application Receive Buffer Address Pointer The DMA updates this pointer during Rx operation. This pointer is cleared on reset." group.long 0x60++0x3 line.long 0x0 "DMA_CH2_STATUS,The software driver (application) reads the Status register during interrupt service routine or polling to determine the status of the DMA. Note: The number of DMA_CH[n]_Status register in the configuration is the higher of number of Rx.." hexmask.long.word 0x0 22.--31. 1. "RESERVED_31_22,Reserved." newline rbitfld.long 0x0 19.--21. "REB,Rx DMA Error Bits This field indicates the type of error that caused a Bus Error. For example error response on the AHB or AXI interface. - Bit 21 -- 1'b1: Error during data transfer by Rx DMA -- 1'b0: No Error during data transfer by Rx DMA - Bit.." "Error during write transfer,Error during read transfer,?,?,?,?,?,?" newline rbitfld.long 0x0 16.--18. "TEB,Tx DMA Error Bits This field indicates the type of error that caused a Bus Error. For example error response on the AHB or AXI interface. - Bit 18 -- 1'b1: Error during data transfer by Tx DMA -- 1'b0: No Error during data transfer by Tx DMA - Bit.." "Error during write transfer,Error during read transfer,?,?,?,?,?,?" newline bitfld.long 0x0 15. "NIS,Normal Interrupt Summary Normal Interrupt Summary bit value is the logical OR of the following bits when the corresponding interrupt bits are enabled in the DMA_CH0_Interrupt_Enable register: - Bit 0: Transmit Interrupt - Bit 2: Transmit Buffer.." "Normal Interrupt Summary status not detected,Normal Interrupt Summary status detected" newline bitfld.long 0x0 14. "AIS,Abnormal Interrupt Summary Abnormal Interrupt Summary bit value is the logical OR of the following when the corresponding interrupt bits are enabled in the DMA_CH0_Interrupt_Enable register: - Bit 1: Transmit Process Stopped - Bit 7: Receive Buffer.." "Abnormal Interrupt Summary status not detected,Abnormal Interrupt Summary status detected" newline bitfld.long 0x0 13. "CDE,Context Descriptor Error This bit indicates that the DMA Tx/Rx engine received a descriptor error which indicates invalid context in the middle of packet flow ( intermediate descriptor) or all one's descriptor in Tx case and on Rx side it indicates.." "Context Descriptor Error status not detected,Context Descriptor Error status detected" newline bitfld.long 0x0 12. "FBE,Fatal Bus Error This bit indicates that a bus error occurred (as described in the EB field). When this bit is set the corresponding DMA channel engine disables all bus accesses. Access restriction applies. Self-set to 1 on internal event. Setting 1.." "Fatal Bus Error status not detected,Fatal Bus Error status detected" newline bitfld.long 0x0 11. "ERI,Early Receive Interrupt This bit when set indicates that the RxDMA has completed the transfer of packet data to the memory. In configs supporting ERIC When ERIC=0 this bit is set only after the Rx DMA has filled up a complete receive buffer with.." "Early Receive Interrupt status not detected,Early Receive Interrupt status detected" newline bitfld.long 0x0 10. "ETI,Early Transmit Interrupt This bit when set indicates that the TxDMA has completed the transfer of packet data to the MTL TXFIFO memory. In configs supporting ERIC: When ETIC=0 this bit is set only after the Tx DMA has transferred a complete packet.." "Early Transmit Interrupt status not detected,Early Transmit Interrupt status detected" newline bitfld.long 0x0 9. "RWT,Receive Watchdog Timeout This bit is asserted when a packet with length greater than 2 048 bytes (10 240 bytes when Jumbo Packet mode is enabled) is received. 0x1: Receive Watchdog Timeout status detected 0x0: Receive Watchdog Timeout status not.." "Receive Watchdog Timeout status not detected,Receive Watchdog Timeout status detected" newline bitfld.long 0x0 8. "RPS,Receive Process Stopped This bit is asserted when the Rx process enters the Stopped state. Access restriction applies. Self-set to 1 on internal event. Setting 1 clears. Setting 0 has no effect. 0x1: Receive Process Stopped status detected 0x0:.." "Receive Process Stopped status not detected,Receive Process Stopped status detected" newline bitfld.long 0x0 7. "RBU,Receive Buffer Unavailable This bit indicates that the application owns the next descriptor in the Receive list and the DMA cannot acquire it. The Rx process is suspended. To resume processing Rx descriptors the application should change the.." "Receive Buffer Unavailable status not detected,Receive Buffer Unavailable status detected" newline bitfld.long 0x0 6. "RI,Receive Interrupt This bit indicates that the packet reception is complete. When packet reception is complete Bit 31 of RDES3 is reset in the last descriptor and the specific packet status information is updated in the descriptor. The reception.." "Receive Interrupt status not detected,Receive Interrupt status detected" newline rbitfld.long 0x0 3.--5. "RESERVED_5_3,Reserved." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 2. "TBU,Transmit Buffer Unavailable This bit indicates that the application owns the next descriptor in the Transmit list and the DMA cannot acquire it. Transmission is suspended. The TPS0 field of the DMA_Debug_Status0 register explains the Transmit.." "Transmit Buffer Unavailable status not detected,Transmit Buffer Unavailable status detected" newline bitfld.long 0x0 1. "TPS,Transmit Process Stopped This bit is set when the transmission is stopped. Access restriction applies. Self-set to 1 on internal event. Setting 1 clears. Setting 0 has no effect. 0x1: Transmit Process Stopped status detected 0x0: Transmit Process.." "Transmit Process Stopped status not detected,Transmit Process Stopped status detected" newline bitfld.long 0x0 0. "TI,Transmit Interrupt This bit indicates that the packet transmission is complete. When transmission is complete Bit 31 of TDES3 is reset in the last descriptor and the specific packet status information is updated in the descriptor. Access restriction.." "Transmit Interrupt status not detected,Transmit Interrupt status detected" rgroup.long 0x64++0xB line.long 0x0 "DMA_CH2_MISS_FRAME_CNT,This register has the number of packet counter that got dropped by the DMA either due to Bus Error or due to programming RPF field in DMA_CH{i}_Rx_Control register." hexmask.long.word 0x0 16.--31. 1. "RESERVED_31_16,Reserved." newline bitfld.long 0x0 15. "MFCO,Overflow status of the MFC Counter When this bit is set then the MFC counter does not get incremented further. The bit gets cleared when this register is read. Access restriction applies. Clears on read. Self-set to 1 on internal event. 0x1: Miss.." "Miss Frame Counter overflow not occurred,Miss Frame Counter overflow occurred" newline hexmask.long.byte 0x0 11.--14. 1. "RESERVED_14_11,Reserved." newline hexmask.long.word 0x0 0.--10. 1. "MFC,Dropped Packet Counters This counter indicates the number of packet counters that are dropped by the DMA either because of bus error or because of programing RPF field in DMA_CH{i}_Rx_Control register. The counter gets cleared when this register is.." line.long 0x4 "DMA_CH2_RXP_ACCEPT_CNT,The DMA_CH(#i)_RXP_Accept_Cnt registers provides the count of the number of frames accepted by Rx Parser." bitfld.long 0x4 31. "RXPACOF,Rx Parser Accept Counter Overflow Bit When set this bit indicates that the RXPAC Counter field crossed the maximum limit. Access restriction applies. Clears on read. Self-set to 1 on internal event. 0x1: Rx Parser Accept Counter overflow.." "Rx Parser Accept Counter overflow not occurred,Rx Parser Accept Counter overflow occurred" newline hexmask.long 0x4 0.--30. 1. "RXPAC,Rx Parser Accept Counter This 31-bit counter is implemented whenever a Rx Parser Accept a packet due to AF =1. The counter is cleared when the register is read." line.long 0x8 "DMA_CH2_RX_ERI_CNT,The DMA_CH(#i)_RX_ERI_Cnt registers provides the count of the number of times ERI was asserted." hexmask.long.tbyte 0x8 12.--31. 1. "RESERVED_31_12," newline hexmask.long.word 0x8 0.--11. 1. "ECNT,ERI Counter When ERIC bit of DMA_CH(#i)_RX_Control register is set this counter increments for burst transfer completed by the Rx DMA from the start of packet transfer. This counter will get reset at the start of new packet." tree.end tree "EQOS_DMA_CH3" group.long 0x0++0xB line.long 0x0 "DMA_CH3_CONTROL,The DMA Channeli Control register specifies the MSS value for segmentation. length to skip between two descriptors. and also the features such as header splitting and 8xPBL mode." hexmask.long.byte 0x0 25.--31. 1. "RESERVED_31_25,Reserved." newline rbitfld.long 0x0 24. "RESERVED_SPH,Reserved." "0,1" newline rbitfld.long 0x0 21.--23. "RESERVED_23_21,Reserved." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 18.--20. "DSL,Descriptor Skip Length This bit specifies the Word Dword or Lword number (depending on the 32-bit 64-bit or 128-bit bus) to skip between two unchained descriptors. The address skipping starts from the end of the current descriptor to the start of.." "0,1,2,3,4,5,6,7" newline rbitfld.long 0x0 17. "RESERVED_17,Reserved." "0,1" newline bitfld.long 0x0 16. "PBLX8,8xPBL mode When this bit is set the PBL value programmed in Bits[21:16] in DMA_CH0_Tx_Control and Bits[21:16] in DMA_CH0_Rx_Control is multiplied by eight times. Therefore the DMA transfers the data in 8 16 32 64 128 and 256 beats depending.." "0,1" newline rbitfld.long 0x0 14.--15. "RESERVED_15_14,Reserved." "0,1,2,3" newline hexmask.long.word 0x0 0.--13. 1. "RESERVED_MSS,Reserved." line.long 0x4 "DMA_CH3_TX_CONTROL,The DMA Channeli Transmit Control register controls the Tx features such as PBL. TCP segmentation. and Tx Channel weights." rbitfld.long 0x4 29.--31. "RESERVED_31_29,Reserved." "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 28. "EDSE,Enhanced Descriptor Enable When this bit is set the corresponding channel uses Enhanced Descriptors that are 32 Bytes for both Normal and Context Descriptors. When reset the corresponding channel uses the descriptors that are 16 Bytes. 0x0:.." "Enhanced Descriptor is disabled,Enhanced Descriptor is enabled" newline hexmask.long.byte 0x4 24.--27. 1. "TQOS,Transmit QOS. This field is used to drive arqos_m_o[3:0] or awqos_m_o[3:0] output signals for all transactions of DMA Tx Channel0." newline rbitfld.long 0x4 23. "RESERVED_23,Reserved." "0,1" newline rbitfld.long 0x4 22. "RESERVED_ETIC,Reserved." "0,1" newline hexmask.long.byte 0x4 16.--21. 1. "TXPBL,Transmit Programmable Burst Length These bits indicate the maximum number of beats to be transferred in one DMA block data transfer. The DMA always attempts max burst as specified in PBL each time it starts a burst transfer on the application bus." newline bitfld.long 0x4 15. "IPBL,Ignore PBL Requirement When this bit is set the DMA does not check for PBL number of locations in the MTL before initiating a transfer. If space is not available the MTL may use handshaking to slow the DMA. Note: This bit/mode must not be used.." "Ignore PBL Requirement is disabled,Ignore PBL Requirement is enabled" newline rbitfld.long 0x4 13.--14. "RESERVED_TSE_MODE,Reserved." "0,1,2,3" newline rbitfld.long 0x4 12. "RESERVED_TSE,Reserved." "0,1" newline hexmask.long.byte 0x4 5.--11. 1. "RESERVED_11_5,Reserved." newline bitfld.long 0x4 4. "OSF,Operate on Second Packet When this bit is set it instructs the DMA to process the second packet of the Transmit data even before the status for the first packet is obtained. 0x0: Operate on Second Packet disabled 0x1: Operate on Second Packet enabled" "Operate on Second Packet disabled,Operate on Second Packet enabled" newline rbitfld.long 0x4 1.--3. "RESERVED_TCW,Reserved." "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 0. "ST,Start or Stop Transmission Command When this bit is set transmission is placed in the Running state. The DMA checks the Transmit list at the current position for a packet to be transmitted. The DMA tries to acquire descriptor from either of the.." "Stop Transmission Command,Start Transmission Command" line.long 0x8 "DMA_CH3_RX_CONTROL,The DMA Channeli Receive Control register controls the Rx features such as PBL. buffer size. and extended status." bitfld.long 0x8 31. "RPF,Rx Packet Flush. When this bit is set to 1 then DWC_ether_qos automatically flushes the packet from the Rx Queues destined to this DMA Rx Channel when it is stopped. When this bit remains set and the DMA is re-started by the software driver the.." "Rx Packet Flush is disabled,Rx Packet Flush is enabled" newline rbitfld.long 0x8 28.--30. "RESERVED_30_28,Reserved." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x8 24.--27. 1. "RQOS,Rx AXI4 QOS. This field is used to drive arqos_m_o[3:0] or awqos_m_o[3:0] output signals for all transactions of DMA Rx Channel0." newline rbitfld.long 0x8 23. "RESERVED_23,Reserved." "0,1" newline rbitfld.long 0x8 22. "RESERVED_ERIC,Reserved." "0,1" newline hexmask.long.byte 0x8 16.--21. 1. "RXPBL,Receive Programmable Burst Length These bits indicate the maximum number of beats to be transferred in one DMA block data transfer. The DMA always attempts max burst as specified in PBL each time it starts a burst transfer on the application bus." newline rbitfld.long 0x8 15. "RESERVED_15,Reserved." "0,1" newline hexmask.long.word 0x8 5.--14. 1. "RBSZ_13_Y,Receive Buffer size High RBSZ[13:0] is split into two fields higher RBSZ_13_y and lower RBSZ_x_0. The RBSZ[13:0] field indicates the size of the Rx buffers specified in bytes. The maximum buffer size is limited to 16K bytes. The buffer size is.." newline hexmask.long.byte 0x8 1.--4. 1. "RBSZ_X_0,Receive Buffer size Low RBSZ[13:0] is split into two fields RBSZ_13_y and RBSZ_x_0. The RBSZ_x_0 is the lower field whose width is based on data bus width of the configuration. This field is of width 2 3 or 4 bits for 32-bit 64-bit or.." newline bitfld.long 0x8 0. "SR,Start or Stop Receive When this bit is set the DMA tries to acquire the descriptor from the Receive list and processes the incoming packets. The DMA tries to acquire descriptor from either of the following positions: - The current position in the.." "Stop Receive,Start Receive" group.long 0x10++0x13 line.long 0x0 "DMA_CH3_TXDESC_LIST_HADDRESS,The Channeli Tx Descriptor List HAddress register has the higher 8 or 16 bits of the start address of the Transmit descriptor list. You can write to this register only when the Tx DMA has stopped. that is. the ST bit is set.." hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED_31_Y,Reserved." newline hexmask.long.byte 0x0 0.--7. 1. "TDESHA,Start of Transmit List This field contains the most-significant 8 or 16 bits of the 40- or 48-bit base address of the first descriptor in the Transmit descriptor list." line.long 0x4 "DMA_CH3_TXDESC_LIST_ADDRESS,The Channeli Tx Descriptor List Address register points the DMA to the start of Transmit descriptor list. The descriptor lists reside in the physical memory space of the application and must be Word. Dword. or Lword-aligned.." hexmask.long 0x4 4.--31. 1. "TDESLA,Start of Transmit List This field contains the base address of the first descriptor in the Transmit descriptor list. The DMA ignores the LSB bits (1:0 2:0 or 3:0) for 32-bit 64-bit or 128-bit bus width and internally takes these bits as.." newline hexmask.long.byte 0x4 0.--3. 1. "RESERVED_LSB," line.long 0x8 "DMA_CH3_RXDESC_LIST_HADDRESS,The Channeli Rx Descriptor List HAddress register has the higher 8 or 16 bits of the start address of the Receive descriptor list. Writing to this register is permitted only when reception is stopped. When stopped. this.." hexmask.long.tbyte 0x8 8.--31. 1. "RESERVED_31_Y,Reserved." newline hexmask.long.byte 0x8 0.--7. 1. "RDESHA,Start of Receive List This field contains the most-significant 8 or 16 bits of the 40-bit or 48-bit base address of the first descriptor in the Rx Descriptor list." line.long 0xC "DMA_CH3_RXDESC_LIST_ADDRESS,The Channeli Rx Descriptor List Address register points the DMA to the start of Receive descriptor list. This register points to the start of the Receive Descriptor List. The descriptor lists reside in the physical memory.." hexmask.long 0xC 4.--31. 1. "RDESLA,Start of Receive List This field contains the base address of the first descriptor in the Rx Descriptor list. The DMA ignores the LSB bits (1:0 2:0 or 3:0) for 32-bit 64-bit or 128-bit bus width and internally takes these bits as all-zero." newline hexmask.long.byte 0xC 0.--3. 1. "RESERVED_LSB," line.long 0x10 "DMA_CH3_TXDESC_TAIL_POINTER,The Channeli Tx Descriptor Tail Pointer register points to an offset from the base and indicates the location of the last valid descriptor." hexmask.long 0x10 4.--31. 1. "TDTP,Transmit Descriptor Tail Pointer This field contains the tail pointer for the Tx descriptor ring. The software writes the tail pointer to add more descriptors to the Tx channel. The hardware tries to transmit all packets referenced by the.." newline hexmask.long.byte 0x10 0.--3. 1. "RESERVED_LSB," group.long 0x28++0x17 line.long 0x0 "DMA_CH3_RXDESC_TAIL_POINTER,The Channeli Rx Descriptor Tail Pointer Points to an offset from the base and indicates the location of the last valid descriptor." hexmask.long 0x0 4.--31. 1. "RDTP,Receive Descriptor Tail Pointer This field contains the tail pointer for the Rx descriptor ring. The software writes the tail pointer to add more descriptors to the Rx channel. The hardware tries to write all received packets to the descriptors.." newline hexmask.long.byte 0x0 0.--3. 1. "RESERVED_LSB," line.long 0x4 "DMA_CH3_TXDESC_RING_LENGTH,The Tx Descriptor Ring Length register contains the length of the Transmit descriptor ring." hexmask.long.tbyte 0x4 10.--31. 1. "RESERVED_31_10,Reserved." newline hexmask.long.word 0x4 0.--9. 1. "TDRL,Transmit Descriptor Ring Length This field sets the maximum number of Tx descriptors in the circular descriptor ring. The maximum number of descriptors is limited to 1K descriptors. Synopsys recommends a minimum ring descriptor length of 4. For.." line.long 0x8 "DMA_CH3_RXDESC_RING_LENGTH,The Channeli Rx Descriptor Ring Length register contains the length of the Receive descriptor circular ring." hexmask.long.tbyte 0x8 10.--31. 1. "RESERVED_31_10,Reserved." newline hexmask.long.word 0x8 0.--9. 1. "RDRL,Receive Descriptor Ring Length This register sets the maximum number of Rx descriptors in the circular descriptor ring. The maximum number of descriptors is limited to 1K descriptors. For example You can program any value up to 0x3FF in this field." line.long 0xC "DMA_CH3_INTERRUPT_ENABLE,The Channeli Interrupt Enable register enables the interrupts reported by the Status register." hexmask.long.word 0xC 16.--31. 1. "RESERVED_31_16,Reserved." newline bitfld.long 0xC 15. "NIE,Normal Interrupt Summary Enable When this bit is set the normal interrupt summary is enabled. This bit enables the following interrupts in the DMA_CH0_Status register: - Bit 0: Transmit Interrupt - Bit 2: Transmit Buffer Unavailable - Bit 6: Receive.." "Normal Interrupt Summary is disabled,Normal Interrupt Summary is enabled" newline bitfld.long 0xC 14. "AIE,Abnormal Interrupt Summary Enable When this bit is set the abnormal interrupt summary is enabled. This bit enables the following interrupts in the DMA_CH0_Status register: - Bit 1: Transmit Process Stopped - Bit 7: Rx Buffer Unavailable - Bit 8:.." "Abnormal Interrupt Summary is disabled,Abnormal Interrupt Summary is enabled" newline bitfld.long 0xC 13. "CDEE,Context Descriptor Error Enable When this bit is set along with the AIE bit the Descriptor error interrupt is enabled. When this bit is reset the Descriptor error interrupt is disabled. 0x0: Context Descriptor Error is disabled 0x1: Context.." "Context Descriptor Error is disabled,Context Descriptor Error is enabled" newline bitfld.long 0xC 12. "FBEE,Fatal Bus Error Enable When this bit is set along with the AIE bit the Fatal Bus error interrupt is enabled. When this bit is reset the Fatal Bus Error error interrupt is disabled. 0x0: Fatal Bus Error is disabled 0x1: Fatal Bus Error is enabled" "Fatal Bus Error is disabled,Fatal Bus Error is enabled" newline bitfld.long 0xC 11. "ERIE,Early Receive Interrupt Enable When this bit is set along with the NIE bit the Early Receive interrupt is enabled. When this bit is reset the Early Receive interrupt is disabled. 0x0: Early Receive Interrupt is disabled 0x1: Early Receive.." "Early Receive Interrupt is disabled,Early Receive Interrupt is enabled" newline bitfld.long 0xC 10. "ETIE,Early Transmit Interrupt Enable When this bit is set along with the AIE bit the Early Transmit interrupt is enabled. When this bit is reset the Early Transmit interrupt is disabled. 0x0: Early Transmit Interrupt is disabled 0x1: Early Transmit.." "Early Transmit Interrupt is disabled,Early Transmit Interrupt is enabled" newline bitfld.long 0xC 9. "RWTE,Receive Watchdog Timeout Enable When this bit is set along with the AIE bit the Receive Watchdog Timeout interrupt is enabled. When this bit is reset the Receive Watchdog Timeout interrupt is disabled. 0x0: Receive Watchdog Timeout is disabled.." "Receive Watchdog Timeout is disabled,Receive Watchdog Timeout is enabled" newline bitfld.long 0xC 8. "RSE,Receive Stopped Enable When this bit is set along with the AIE bit the Receive Stopped Interrupt is enabled. When this bit is reset the Receive Stopped interrupt is disabled. 0x0: Receive Stopped is disabled 0x1: Receive Stopped is enabled" "Receive Stopped is disabled,Receive Stopped is enabled" newline bitfld.long 0xC 7. "RBUE,Receive Buffer Unavailable Enable When this bit is set along with the AIE bit the Receive Buffer Unavailable interrupt is enabled. When this bit is reset the Receive Buffer Unavailable interrupt is disabled. 0x0: Receive Buffer Unavailable is.." "Receive Buffer Unavailable is disabled,Receive Buffer Unavailable is enabled" newline bitfld.long 0xC 6. "RIE,Receive Interrupt Enable When this bit is set along with the NIE bit the Receive Interrupt is enabled. When this bit is reset the Receive Interrupt is disabled. 0x0: Receive Interrupt is disabled 0x1: Receive Interrupt is enabled" "Receive Interrupt is disabled,Receive Interrupt is enabled" newline rbitfld.long 0xC 3.--5. "RESERVED_5_3,Reserved." "0,1,2,3,4,5,6,7" newline bitfld.long 0xC 2. "TBUE,Transmit Buffer Unavailable Enable When this bit is set along with the NIE bit the Transmit Buffer Unavailable interrupt is enabled. When this bit is reset the Transmit Buffer Unavailable interrupt is disabled. 0x0: Transmit Buffer Unavailable is.." "Transmit Buffer Unavailable is disabled,Transmit Buffer Unavailable is enabled" newline bitfld.long 0xC 1. "TXSE,Transmit Stopped Enable When this bit is set along with the AIE bit the Transmission Stopped interrupt is enabled. When this bit is reset the Transmission Stopped interrupt is disabled. 0x0: Transmit Stopped is disabled 0x1: Transmit Stopped is.." "Transmit Stopped is disabled,Transmit Stopped is enabled" newline bitfld.long 0xC 0. "TIE,Transmit Interrupt Enable When this bit is set along with the NIE bit the Transmit Interrupt is enabled. When this bit is reset the Transmit Interrupt is disabled. 0x0: Transmit Interrupt is disabled 0x1: Transmit Interrupt is enabled" "Transmit Interrupt is disabled,Transmit Interrupt is enabled" line.long 0x10 "DMA_CH3_RX_INTERRUPT_WATCHDOG_TIMER,The Receive Interrupt Watchdog Timer register indicates the watchdog timeout for Receive Interrupt (RI) from the DMA. When this register is written with a non-zero value. it enables the watchdog timer for the RI bit of.." hexmask.long.word 0x10 18.--31. 1. "RESERVED_31_18,Reserved." newline bitfld.long 0x10 16.--17. "RWTU,Receive Interrupt Watchdog Timer Count Units This fields indicates the number of system clock cycles corresponding to one unit in RWT field. - 2'b00: 256 - 2'b01: 512 - 2'b10: 1024 - 2'b11: 2048 For example when RWT=2 and RWTU=1 the watchdog timer.." "0,1,2,3" newline hexmask.long.byte 0x10 8.--15. 1. "RESERVED_15_8,Reserved." newline hexmask.long.byte 0x10 0.--7. 1. "RWT,Receive Interrupt Watchdog Timer Count This field indicates the number of system clock cycles multiplied by factor indicated in RWTU field for which the watchdog timer is set. The watchdog timer is triggered with the programmed value after the Rx.." line.long 0x14 "DMA_CH3_SLOT_FUNCTION_CONTROL_STATUS,The Slot Function Control and Status register contains the control bits for slot function and the status for Transmit path." hexmask.long.word 0x14 20.--31. 1. "RESERVED_31_20,Reserved." newline hexmask.long.byte 0x14 16.--19. 1. "RSN,Reference Slot Number This field gives the current value of the reference slot number in the DMA. It is used for slot comparison." newline hexmask.long.word 0x14 4.--15. 1. "SIV,Slot Interval Value This field controls the period of the slot interval in which the TxDMA fetches the scheduled packets. A value of 0 specifies the slot interval of 1 us while the maximum value 4095 specifies the slot interval of 4096us. The.." newline rbitfld.long 0x14 2.--3. "RESERVED_3_2,Reserved." "0,1,2,3" newline bitfld.long 0x14 1. "ASC,Advance Slot Check When set this bit enables the DMA to fetch the data from the buffer when the slot number (SLOTNUM) programmed in the Tx descriptor is - equal to the reference slot number given in the RSN field or - ahead of the reference slot.." "Advance Slot Check is disabled,Advance Slot Check is enabled" newline bitfld.long 0x14 0. "ESC,Enable Slot Comparison When set this bit enables the checking of the slot numbers programmed in the Tx descriptor with the current reference given in the RSN field. The DMA fetches the data from the corresponding buffer only when the slot number is.." "Slot Comparison is disabled,Slot Comparison is enabled" rgroup.long 0x44++0x3 line.long 0x0 "DMA_CH3_CURRENT_APP_TXDESC,The Channeli Current Application Transmit Descriptor register points to the current Transmit descriptor read by the DMA." hexmask.long 0x0 0.--31. 1. "CURTDESAPTR,Application Transmit Descriptor Address Pointer The DMA updates this pointer during Tx operation. This pointer is cleared on reset." rgroup.long 0x4C++0x13 line.long 0x0 "DMA_CH3_CURRENT_APP_RXDESC,The Channeli Current Application Receive Descriptor register points to the current Receive descriptor read by the DMA." hexmask.long 0x0 0.--31. 1. "CURRDESAPTR,Application Receive Descriptor Address Pointer The DMA updates this pointer during Rx operation. This pointer is cleared on reset." line.long 0x4 "DMA_CH3_CURRENT_APP_TXBUFFER_H,The Channeli Current Application Transmit Buffer Address High register has the higher 8 or 16 bits of the current address of the Transmit buffer address read by the DMA." hexmask.long.tbyte 0x4 8.--31. 1. "RESERVED_31_Y,Reserved." newline hexmask.long.byte 0x4 0.--7. 1. "CURTBUFAPTRH,Application Transmit Buffer Address Pointer The DMA updates this pointer during Tx operation. This pointer is cleared on reset." line.long 0x8 "DMA_CH3_CURRENT_APP_TXBUFFER,The Channeli Current Application Transmit Buffer Address register points to the current Tx buffer address read by the DMA." hexmask.long 0x8 0.--31. 1. "CURTBUFAPTR,Application Transmit Buffer Address Pointer The DMA updates this pointer during Tx operation. This pointer is cleared on reset." line.long 0xC "DMA_CH3_CURRENT_APP_RXBUFFER_H,The Channeli Current Application Receive Buffer Address High register has the higher 8 or 16 bits of the current address of the Receive buffer address read by the DMA." hexmask.long.tbyte 0xC 8.--31. 1. "RESERVED_31_Y,Reserved." newline hexmask.long.byte 0xC 0.--7. 1. "CURRBUFAPTRH,Application Receive Buffer Address Pointer The DMA updates this pointer during Rx operation. This pointer is cleared on reset." line.long 0x10 "DMA_CH3_CURRENT_APP_RXBUFFER,The Channel 0 Current Application Receive Buffer Address register points to the current Rx buffer address read by the DMA." hexmask.long 0x10 0.--31. 1. "CURRBUFAPTR,Application Receive Buffer Address Pointer The DMA updates this pointer during Rx operation. This pointer is cleared on reset." group.long 0x60++0x3 line.long 0x0 "DMA_CH3_STATUS,The software driver (application) reads the Status register during interrupt service routine or polling to determine the status of the DMA. Note: The number of DMA_CH[n]_Status register in the configuration is the higher of number of Rx.." hexmask.long.word 0x0 22.--31. 1. "RESERVED_31_22,Reserved." newline rbitfld.long 0x0 19.--21. "REB,Rx DMA Error Bits This field indicates the type of error that caused a Bus Error. For example error response on the AHB or AXI interface. - Bit 21 -- 1'b1: Error during data transfer by Rx DMA -- 1'b0: No Error during data transfer by Rx DMA - Bit.." "Error during write transfer,Error during read transfer,?,?,?,?,?,?" newline rbitfld.long 0x0 16.--18. "TEB,Tx DMA Error Bits This field indicates the type of error that caused a Bus Error. For example error response on the AHB or AXI interface. - Bit 18 -- 1'b1: Error during data transfer by Tx DMA -- 1'b0: No Error during data transfer by Tx DMA - Bit.." "Error during write transfer,Error during read transfer,?,?,?,?,?,?" newline bitfld.long 0x0 15. "NIS,Normal Interrupt Summary Normal Interrupt Summary bit value is the logical OR of the following bits when the corresponding interrupt bits are enabled in the DMA_CH0_Interrupt_Enable register: - Bit 0: Transmit Interrupt - Bit 2: Transmit Buffer.." "Normal Interrupt Summary status not detected,Normal Interrupt Summary status detected" newline bitfld.long 0x0 14. "AIS,Abnormal Interrupt Summary Abnormal Interrupt Summary bit value is the logical OR of the following when the corresponding interrupt bits are enabled in the DMA_CH0_Interrupt_Enable register: - Bit 1: Transmit Process Stopped - Bit 7: Receive Buffer.." "Abnormal Interrupt Summary status not detected,Abnormal Interrupt Summary status detected" newline bitfld.long 0x0 13. "CDE,Context Descriptor Error This bit indicates that the DMA Tx/Rx engine received a descriptor error which indicates invalid context in the middle of packet flow ( intermediate descriptor) or all one's descriptor in Tx case and on Rx side it indicates.." "Context Descriptor Error status not detected,Context Descriptor Error status detected" newline bitfld.long 0x0 12. "FBE,Fatal Bus Error This bit indicates that a bus error occurred (as described in the EB field). When this bit is set the corresponding DMA channel engine disables all bus accesses. Access restriction applies. Self-set to 1 on internal event. Setting 1.." "Fatal Bus Error status not detected,Fatal Bus Error status detected" newline bitfld.long 0x0 11. "ERI,Early Receive Interrupt This bit when set indicates that the RxDMA has completed the transfer of packet data to the memory. In configs supporting ERIC When ERIC=0 this bit is set only after the Rx DMA has filled up a complete receive buffer with.." "Early Receive Interrupt status not detected,Early Receive Interrupt status detected" newline bitfld.long 0x0 10. "ETI,Early Transmit Interrupt This bit when set indicates that the TxDMA has completed the transfer of packet data to the MTL TXFIFO memory. In configs supporting ERIC: When ETIC=0 this bit is set only after the Tx DMA has transferred a complete packet.." "Early Transmit Interrupt status not detected,Early Transmit Interrupt status detected" newline bitfld.long 0x0 9. "RWT,Receive Watchdog Timeout This bit is asserted when a packet with length greater than 2 048 bytes (10 240 bytes when Jumbo Packet mode is enabled) is received. 0x1: Receive Watchdog Timeout status detected 0x0: Receive Watchdog Timeout status not.." "Receive Watchdog Timeout status not detected,Receive Watchdog Timeout status detected" newline bitfld.long 0x0 8. "RPS,Receive Process Stopped This bit is asserted when the Rx process enters the Stopped state. Access restriction applies. Self-set to 1 on internal event. Setting 1 clears. Setting 0 has no effect. 0x1: Receive Process Stopped status detected 0x0:.." "Receive Process Stopped status not detected,Receive Process Stopped status detected" newline bitfld.long 0x0 7. "RBU,Receive Buffer Unavailable This bit indicates that the application owns the next descriptor in the Receive list and the DMA cannot acquire it. The Rx process is suspended. To resume processing Rx descriptors the application should change the.." "Receive Buffer Unavailable status not detected,Receive Buffer Unavailable status detected" newline bitfld.long 0x0 6. "RI,Receive Interrupt This bit indicates that the packet reception is complete. When packet reception is complete Bit 31 of RDES3 is reset in the last descriptor and the specific packet status information is updated in the descriptor. The reception.." "Receive Interrupt status not detected,Receive Interrupt status detected" newline rbitfld.long 0x0 3.--5. "RESERVED_5_3,Reserved." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 2. "TBU,Transmit Buffer Unavailable This bit indicates that the application owns the next descriptor in the Transmit list and the DMA cannot acquire it. Transmission is suspended. The TPS0 field of the DMA_Debug_Status0 register explains the Transmit.." "Transmit Buffer Unavailable status not detected,Transmit Buffer Unavailable status detected" newline bitfld.long 0x0 1. "TPS,Transmit Process Stopped This bit is set when the transmission is stopped. Access restriction applies. Self-set to 1 on internal event. Setting 1 clears. Setting 0 has no effect. 0x1: Transmit Process Stopped status detected 0x0: Transmit Process.." "Transmit Process Stopped status not detected,Transmit Process Stopped status detected" newline bitfld.long 0x0 0. "TI,Transmit Interrupt This bit indicates that the packet transmission is complete. When transmission is complete Bit 31 of TDES3 is reset in the last descriptor and the specific packet status information is updated in the descriptor. Access restriction.." "Transmit Interrupt status not detected,Transmit Interrupt status detected" rgroup.long 0x64++0xB line.long 0x0 "DMA_CH3_MISS_FRAME_CNT,This register has the number of packet counter that got dropped by the DMA either due to Bus Error or due to programming RPF field in DMA_CH{i}_Rx_Control register." hexmask.long.word 0x0 16.--31. 1. "RESERVED_31_16,Reserved." newline bitfld.long 0x0 15. "MFCO,Overflow status of the MFC Counter When this bit is set then the MFC counter does not get incremented further. The bit gets cleared when this register is read. Access restriction applies. Clears on read. Self-set to 1 on internal event. 0x1: Miss.." "Miss Frame Counter overflow not occurred,Miss Frame Counter overflow occurred" newline hexmask.long.byte 0x0 11.--14. 1. "RESERVED_14_11,Reserved." newline hexmask.long.word 0x0 0.--10. 1. "MFC,Dropped Packet Counters This counter indicates the number of packet counters that are dropped by the DMA either because of bus error or because of programing RPF field in DMA_CH{i}_Rx_Control register. The counter gets cleared when this register is.." line.long 0x4 "DMA_CH3_RXP_ACCEPT_CNT,The DMA_CH(#i)_RXP_Accept_Cnt registers provides the count of the number of frames accepted by Rx Parser." bitfld.long 0x4 31. "RXPACOF,Rx Parser Accept Counter Overflow Bit When set this bit indicates that the RXPAC Counter field crossed the maximum limit. Access restriction applies. Clears on read. Self-set to 1 on internal event. 0x1: Rx Parser Accept Counter overflow.." "Rx Parser Accept Counter overflow not occurred,Rx Parser Accept Counter overflow occurred" newline hexmask.long 0x4 0.--30. 1. "RXPAC,Rx Parser Accept Counter This 31-bit counter is implemented whenever a Rx Parser Accept a packet due to AF =1. The counter is cleared when the register is read." line.long 0x8 "DMA_CH3_RX_ERI_CNT,The DMA_CH(#i)_RX_ERI_Cnt registers provides the count of the number of times ERI was asserted." hexmask.long.tbyte 0x8 12.--31. 1. "RESERVED_31_12," newline hexmask.long.word 0x8 0.--11. 1. "ECNT,ERI Counter When ERIC bit of DMA_CH(#i)_RX_Control register is set this counter increments for burst transfer completed by the Rx DMA from the start of packet transfer. This counter will get reset at the start of new packet." tree.end tree "EQOS_DMA_CH4" group.long 0x0++0xB line.long 0x0 "DMA_CH4_CONTROL,The DMA Channeli Control register specifies the MSS value for segmentation. length to skip between two descriptors. and also the features such as header splitting and 8xPBL mode." hexmask.long.byte 0x0 25.--31. 1. "RESERVED_31_25,Reserved." newline rbitfld.long 0x0 24. "RESERVED_SPH,Reserved." "0,1" newline rbitfld.long 0x0 21.--23. "RESERVED_23_21,Reserved." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 18.--20. "DSL,Descriptor Skip Length This bit specifies the Word Dword or Lword number (depending on the 32-bit 64-bit or 128-bit bus) to skip between two unchained descriptors. The address skipping starts from the end of the current descriptor to the start of.." "0,1,2,3,4,5,6,7" newline rbitfld.long 0x0 17. "RESERVED_17,Reserved." "0,1" newline bitfld.long 0x0 16. "PBLX8,8xPBL mode When this bit is set the PBL value programmed in Bits[21:16] in DMA_CH0_Tx_Control and Bits[21:16] in DMA_CH0_Rx_Control is multiplied by eight times. Therefore the DMA transfers the data in 8 16 32 64 128 and 256 beats depending.." "0,1" newline rbitfld.long 0x0 14.--15. "RESERVED_15_14,Reserved." "0,1,2,3" newline hexmask.long.word 0x0 0.--13. 1. "RESERVED_MSS,Reserved." line.long 0x4 "DMA_CH4_TX_CONTROL,The DMA Channeli Transmit Control register controls the Tx features such as PBL. TCP segmentation. and Tx Channel weights." rbitfld.long 0x4 29.--31. "RESERVED_31_29,Reserved." "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 28. "EDSE,Enhanced Descriptor Enable When this bit is set the corresponding channel uses Enhanced Descriptors that are 32 Bytes for both Normal and Context Descriptors. When reset the corresponding channel uses the descriptors that are 16 Bytes. 0x0:.." "Enhanced Descriptor is disabled,Enhanced Descriptor is enabled" newline hexmask.long.byte 0x4 24.--27. 1. "TQOS,Transmit QOS. This field is used to drive arqos_m_o[3:0] or awqos_m_o[3:0] output signals for all transactions of DMA Tx Channel0." newline rbitfld.long 0x4 23. "RESERVED_23,Reserved." "0,1" newline rbitfld.long 0x4 22. "RESERVED_ETIC,Reserved." "0,1" newline hexmask.long.byte 0x4 16.--21. 1. "TXPBL,Transmit Programmable Burst Length These bits indicate the maximum number of beats to be transferred in one DMA block data transfer. The DMA always attempts max burst as specified in PBL each time it starts a burst transfer on the application bus." newline bitfld.long 0x4 15. "IPBL,Ignore PBL Requirement When this bit is set the DMA does not check for PBL number of locations in the MTL before initiating a transfer. If space is not available the MTL may use handshaking to slow the DMA. Note: This bit/mode must not be used.." "Ignore PBL Requirement is disabled,Ignore PBL Requirement is enabled" newline rbitfld.long 0x4 13.--14. "RESERVED_TSE_MODE,Reserved." "0,1,2,3" newline rbitfld.long 0x4 12. "RESERVED_TSE,Reserved." "0,1" newline hexmask.long.byte 0x4 5.--11. 1. "RESERVED_11_5,Reserved." newline bitfld.long 0x4 4. "OSF,Operate on Second Packet When this bit is set it instructs the DMA to process the second packet of the Transmit data even before the status for the first packet is obtained. 0x0: Operate on Second Packet disabled 0x1: Operate on Second Packet enabled" "Operate on Second Packet disabled,Operate on Second Packet enabled" newline rbitfld.long 0x4 1.--3. "RESERVED_TCW,Reserved." "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 0. "ST,Start or Stop Transmission Command When this bit is set transmission is placed in the Running state. The DMA checks the Transmit list at the current position for a packet to be transmitted. The DMA tries to acquire descriptor from either of the.." "Stop Transmission Command,Start Transmission Command" line.long 0x8 "DMA_CH4_RX_CONTROL,The DMA Channeli Receive Control register controls the Rx features such as PBL. buffer size. and extended status." bitfld.long 0x8 31. "RPF,Rx Packet Flush. When this bit is set to 1 then DWC_ether_qos automatically flushes the packet from the Rx Queues destined to this DMA Rx Channel when it is stopped. When this bit remains set and the DMA is re-started by the software driver the.." "Rx Packet Flush is disabled,Rx Packet Flush is enabled" newline rbitfld.long 0x8 28.--30. "RESERVED_30_28,Reserved." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x8 24.--27. 1. "RQOS,Rx AXI4 QOS. This field is used to drive arqos_m_o[3:0] or awqos_m_o[3:0] output signals for all transactions of DMA Rx Channel0." newline rbitfld.long 0x8 23. "RESERVED_23,Reserved." "0,1" newline rbitfld.long 0x8 22. "RESERVED_ERIC,Reserved." "0,1" newline hexmask.long.byte 0x8 16.--21. 1. "RXPBL,Receive Programmable Burst Length These bits indicate the maximum number of beats to be transferred in one DMA block data transfer. The DMA always attempts max burst as specified in PBL each time it starts a burst transfer on the application bus." newline rbitfld.long 0x8 15. "RESERVED_15,Reserved." "0,1" newline hexmask.long.word 0x8 5.--14. 1. "RBSZ_13_Y,Receive Buffer size High RBSZ[13:0] is split into two fields higher RBSZ_13_y and lower RBSZ_x_0. The RBSZ[13:0] field indicates the size of the Rx buffers specified in bytes. The maximum buffer size is limited to 16K bytes. The buffer size is.." newline hexmask.long.byte 0x8 1.--4. 1. "RBSZ_X_0,Receive Buffer size Low RBSZ[13:0] is split into two fields RBSZ_13_y and RBSZ_x_0. The RBSZ_x_0 is the lower field whose width is based on data bus width of the configuration. This field is of width 2 3 or 4 bits for 32-bit 64-bit or.." newline bitfld.long 0x8 0. "SR,Start or Stop Receive When this bit is set the DMA tries to acquire the descriptor from the Receive list and processes the incoming packets. The DMA tries to acquire descriptor from either of the following positions: - The current position in the.." "Stop Receive,Start Receive" group.long 0x10++0x13 line.long 0x0 "DMA_CH4_TXDESC_LIST_HADDRESS,The Channeli Tx Descriptor List HAddress register has the higher 8 or 16 bits of the start address of the Transmit descriptor list. You can write to this register only when the Tx DMA has stopped. that is. the ST bit is set.." hexmask.long.tbyte 0x0 8.--31. 1. "RESERVED_31_Y,Reserved." newline hexmask.long.byte 0x0 0.--7. 1. "TDESHA,Start of Transmit List This field contains the most-significant 8 or 16 bits of the 40- or 48-bit base address of the first descriptor in the Transmit descriptor list." line.long 0x4 "DMA_CH4_TXDESC_LIST_ADDRESS,The Channeli Tx Descriptor List Address register points the DMA to the start of Transmit descriptor list. The descriptor lists reside in the physical memory space of the application and must be Word. Dword. or Lword-aligned.." hexmask.long 0x4 4.--31. 1. "TDESLA,Start of Transmit List This field contains the base address of the first descriptor in the Transmit descriptor list. The DMA ignores the LSB bits (1:0 2:0 or 3:0) for 32-bit 64-bit or 128-bit bus width and internally takes these bits as.." newline hexmask.long.byte 0x4 0.--3. 1. "RESERVED_LSB," line.long 0x8 "DMA_CH4_RXDESC_LIST_HADDRESS,The Channeli Rx Descriptor List HAddress register has the higher 8 or 16 bits of the start address of the Receive descriptor list. Writing to this register is permitted only when reception is stopped. When stopped. this.." hexmask.long.tbyte 0x8 8.--31. 1. "RESERVED_31_Y,Reserved." newline hexmask.long.byte 0x8 0.--7. 1. "RDESHA,Start of Receive List This field contains the most-significant 8 or 16 bits of the 40-bit or 48-bit base address of the first descriptor in the Rx Descriptor list." line.long 0xC "DMA_CH4_RXDESC_LIST_ADDRESS,The Channeli Rx Descriptor List Address register points the DMA to the start of Receive descriptor list. This register points to the start of the Receive Descriptor List. The descriptor lists reside in the physical memory.." hexmask.long 0xC 4.--31. 1. "RDESLA,Start of Receive List This field contains the base address of the first descriptor in the Rx Descriptor list. The DMA ignores the LSB bits (1:0 2:0 or 3:0) for 32-bit 64-bit or 128-bit bus width and internally takes these bits as all-zero." newline hexmask.long.byte 0xC 0.--3. 1. "RESERVED_LSB," line.long 0x10 "DMA_CH4_TXDESC_TAIL_POINTER,The Channeli Tx Descriptor Tail Pointer register points to an offset from the base and indicates the location of the last valid descriptor." hexmask.long 0x10 4.--31. 1. "TDTP,Transmit Descriptor Tail Pointer This field contains the tail pointer for the Tx descriptor ring. The software writes the tail pointer to add more descriptors to the Tx channel. The hardware tries to transmit all packets referenced by the.." newline hexmask.long.byte 0x10 0.--3. 1. "RESERVED_LSB," group.long 0x28++0x17 line.long 0x0 "DMA_CH4_RXDESC_TAIL_POINTER,The Channeli Rx Descriptor Tail Pointer Points to an offset from the base and indicates the location of the last valid descriptor." hexmask.long 0x0 4.--31. 1. "RDTP,Receive Descriptor Tail Pointer This field contains the tail pointer for the Rx descriptor ring. The software writes the tail pointer to add more descriptors to the Rx channel. The hardware tries to write all received packets to the descriptors.." newline hexmask.long.byte 0x0 0.--3. 1. "RESERVED_LSB," line.long 0x4 "DMA_CH4_TXDESC_RING_LENGTH,The Tx Descriptor Ring Length register contains the length of the Transmit descriptor ring." hexmask.long.tbyte 0x4 10.--31. 1. "RESERVED_31_10,Reserved." newline hexmask.long.word 0x4 0.--9. 1. "TDRL,Transmit Descriptor Ring Length This field sets the maximum number of Tx descriptors in the circular descriptor ring. The maximum number of descriptors is limited to 1K descriptors. Synopsys recommends a minimum ring descriptor length of 4. For.." line.long 0x8 "DMA_CH4_RXDESC_RING_LENGTH,The Channeli Rx Descriptor Ring Length register contains the length of the Receive descriptor circular ring." hexmask.long.tbyte 0x8 10.--31. 1. "RESERVED_31_10,Reserved." newline hexmask.long.word 0x8 0.--9. 1. "RDRL,Receive Descriptor Ring Length This register sets the maximum number of Rx descriptors in the circular descriptor ring. The maximum number of descriptors is limited to 1K descriptors. For example You can program any value up to 0x3FF in this field." line.long 0xC "DMA_CH4_INTERRUPT_ENABLE,The Channeli Interrupt Enable register enables the interrupts reported by the Status register." hexmask.long.word 0xC 16.--31. 1. "RESERVED_31_16,Reserved." newline bitfld.long 0xC 15. "NIE,Normal Interrupt Summary Enable When this bit is set the normal interrupt summary is enabled. This bit enables the following interrupts in the DMA_CH0_Status register: - Bit 0: Transmit Interrupt - Bit 2: Transmit Buffer Unavailable - Bit 6: Receive.." "Normal Interrupt Summary is disabled,Normal Interrupt Summary is enabled" newline bitfld.long 0xC 14. "AIE,Abnormal Interrupt Summary Enable When this bit is set the abnormal interrupt summary is enabled. This bit enables the following interrupts in the DMA_CH0_Status register: - Bit 1: Transmit Process Stopped - Bit 7: Rx Buffer Unavailable - Bit 8:.." "Abnormal Interrupt Summary is disabled,Abnormal Interrupt Summary is enabled" newline bitfld.long 0xC 13. "CDEE,Context Descriptor Error Enable When this bit is set along with the AIE bit the Descriptor error interrupt is enabled. When this bit is reset the Descriptor error interrupt is disabled. 0x0: Context Descriptor Error is disabled 0x1: Context.." "Context Descriptor Error is disabled,Context Descriptor Error is enabled" newline bitfld.long 0xC 12. "FBEE,Fatal Bus Error Enable When this bit is set along with the AIE bit the Fatal Bus error interrupt is enabled. When this bit is reset the Fatal Bus Error error interrupt is disabled. 0x0: Fatal Bus Error is disabled 0x1: Fatal Bus Error is enabled" "Fatal Bus Error is disabled,Fatal Bus Error is enabled" newline bitfld.long 0xC 11. "ERIE,Early Receive Interrupt Enable When this bit is set along with the NIE bit the Early Receive interrupt is enabled. When this bit is reset the Early Receive interrupt is disabled. 0x0: Early Receive Interrupt is disabled 0x1: Early Receive.." "Early Receive Interrupt is disabled,Early Receive Interrupt is enabled" newline bitfld.long 0xC 10. "ETIE,Early Transmit Interrupt Enable When this bit is set along with the AIE bit the Early Transmit interrupt is enabled. When this bit is reset the Early Transmit interrupt is disabled. 0x0: Early Transmit Interrupt is disabled 0x1: Early Transmit.." "Early Transmit Interrupt is disabled,Early Transmit Interrupt is enabled" newline bitfld.long 0xC 9. "RWTE,Receive Watchdog Timeout Enable When this bit is set along with the AIE bit the Receive Watchdog Timeout interrupt is enabled. When this bit is reset the Receive Watchdog Timeout interrupt is disabled. 0x0: Receive Watchdog Timeout is disabled.." "Receive Watchdog Timeout is disabled,Receive Watchdog Timeout is enabled" newline bitfld.long 0xC 8. "RSE,Receive Stopped Enable When this bit is set along with the AIE bit the Receive Stopped Interrupt is enabled. When this bit is reset the Receive Stopped interrupt is disabled. 0x0: Receive Stopped is disabled 0x1: Receive Stopped is enabled" "Receive Stopped is disabled,Receive Stopped is enabled" newline bitfld.long 0xC 7. "RBUE,Receive Buffer Unavailable Enable When this bit is set along with the AIE bit the Receive Buffer Unavailable interrupt is enabled. When this bit is reset the Receive Buffer Unavailable interrupt is disabled. 0x0: Receive Buffer Unavailable is.." "Receive Buffer Unavailable is disabled,Receive Buffer Unavailable is enabled" newline bitfld.long 0xC 6. "RIE,Receive Interrupt Enable When this bit is set along with the NIE bit the Receive Interrupt is enabled. When this bit is reset the Receive Interrupt is disabled. 0x0: Receive Interrupt is disabled 0x1: Receive Interrupt is enabled" "Receive Interrupt is disabled,Receive Interrupt is enabled" newline rbitfld.long 0xC 3.--5. "RESERVED_5_3,Reserved." "0,1,2,3,4,5,6,7" newline bitfld.long 0xC 2. "TBUE,Transmit Buffer Unavailable Enable When this bit is set along with the NIE bit the Transmit Buffer Unavailable interrupt is enabled. When this bit is reset the Transmit Buffer Unavailable interrupt is disabled. 0x0: Transmit Buffer Unavailable is.." "Transmit Buffer Unavailable is disabled,Transmit Buffer Unavailable is enabled" newline bitfld.long 0xC 1. "TXSE,Transmit Stopped Enable When this bit is set along with the AIE bit the Transmission Stopped interrupt is enabled. When this bit is reset the Transmission Stopped interrupt is disabled. 0x0: Transmit Stopped is disabled 0x1: Transmit Stopped is.." "Transmit Stopped is disabled,Transmit Stopped is enabled" newline bitfld.long 0xC 0. "TIE,Transmit Interrupt Enable When this bit is set along with the NIE bit the Transmit Interrupt is enabled. When this bit is reset the Transmit Interrupt is disabled. 0x0: Transmit Interrupt is disabled 0x1: Transmit Interrupt is enabled" "Transmit Interrupt is disabled,Transmit Interrupt is enabled" line.long 0x10 "DMA_CH4_RX_INTERRUPT_WATCHDOG_TIMER,The Receive Interrupt Watchdog Timer register indicates the watchdog timeout for Receive Interrupt (RI) from the DMA. When this register is written with a non-zero value. it enables the watchdog timer for the RI bit of.." hexmask.long.word 0x10 18.--31. 1. "RESERVED_31_18,Reserved." newline bitfld.long 0x10 16.--17. "RWTU,Receive Interrupt Watchdog Timer Count Units This fields indicates the number of system clock cycles corresponding to one unit in RWT field. - 2'b00: 256 - 2'b01: 512 - 2'b10: 1024 - 2'b11: 2048 For example when RWT=2 and RWTU=1 the watchdog timer.." "0,1,2,3" newline hexmask.long.byte 0x10 8.--15. 1. "RESERVED_15_8,Reserved." newline hexmask.long.byte 0x10 0.--7. 1. "RWT,Receive Interrupt Watchdog Timer Count This field indicates the number of system clock cycles multiplied by factor indicated in RWTU field for which the watchdog timer is set. The watchdog timer is triggered with the programmed value after the Rx.." line.long 0x14 "DMA_CH4_SLOT_FUNCTION_CONTROL_STATUS,The Slot Function Control and Status register contains the control bits for slot function and the status for Transmit path." hexmask.long.word 0x14 20.--31. 1. "RESERVED_31_20,Reserved." newline hexmask.long.byte 0x14 16.--19. 1. "RSN,Reference Slot Number This field gives the current value of the reference slot number in the DMA. It is used for slot comparison." newline hexmask.long.word 0x14 4.--15. 1. "SIV,Slot Interval Value This field controls the period of the slot interval in which the TxDMA fetches the scheduled packets. A value of 0 specifies the slot interval of 1 us while the maximum value 4095 specifies the slot interval of 4096us. The.." newline rbitfld.long 0x14 2.--3. "RESERVED_3_2,Reserved." "0,1,2,3" newline bitfld.long 0x14 1. "ASC,Advance Slot Check When set this bit enables the DMA to fetch the data from the buffer when the slot number (SLOTNUM) programmed in the Tx descriptor is - equal to the reference slot number given in the RSN field or - ahead of the reference slot.." "Advance Slot Check is disabled,Advance Slot Check is enabled" newline bitfld.long 0x14 0. "ESC,Enable Slot Comparison When set this bit enables the checking of the slot numbers programmed in the Tx descriptor with the current reference given in the RSN field. The DMA fetches the data from the corresponding buffer only when the slot number is.." "Slot Comparison is disabled,Slot Comparison is enabled" rgroup.long 0x44++0x3 line.long 0x0 "DMA_CH4_CURRENT_APP_TXDESC,The Channeli Current Application Transmit Descriptor register points to the current Transmit descriptor read by the DMA." hexmask.long 0x0 0.--31. 1. "CURTDESAPTR,Application Transmit Descriptor Address Pointer The DMA updates this pointer during Tx operation. This pointer is cleared on reset." rgroup.long 0x4C++0x13 line.long 0x0 "DMA_CH4_CURRENT_APP_RXDESC,The Channeli Current Application Receive Descriptor register points to the current Receive descriptor read by the DMA." hexmask.long 0x0 0.--31. 1. "CURRDESAPTR,Application Receive Descriptor Address Pointer The DMA updates this pointer during Rx operation. This pointer is cleared on reset." line.long 0x4 "DMA_CH4_CURRENT_APP_TXBUFFER_H,The Channeli Current Application Transmit Buffer Address High register has the higher 8 or 16 bits of the current address of the Transmit buffer address read by the DMA." hexmask.long.tbyte 0x4 8.--31. 1. "RESERVED_31_Y,Reserved." newline hexmask.long.byte 0x4 0.--7. 1. "CURTBUFAPTRH,Application Transmit Buffer Address Pointer The DMA updates this pointer during Tx operation. This pointer is cleared on reset." line.long 0x8 "DMA_CH4_CURRENT_APP_TXBUFFER,The Channeli Current Application Transmit Buffer Address register points to the current Tx buffer address read by the DMA." hexmask.long 0x8 0.--31. 1. "CURTBUFAPTR,Application Transmit Buffer Address Pointer The DMA updates this pointer during Tx operation. This pointer is cleared on reset." line.long 0xC "DMA_CH4_CURRENT_APP_RXBUFFER_H,The Channeli Current Application Receive Buffer Address High register has the higher 8 or 16 bits of the current address of the Receive buffer address read by the DMA." hexmask.long.tbyte 0xC 8.--31. 1. "RESERVED_31_Y,Reserved." newline hexmask.long.byte 0xC 0.--7. 1. "CURRBUFAPTRH,Application Receive Buffer Address Pointer The DMA updates this pointer during Rx operation. This pointer is cleared on reset." line.long 0x10 "DMA_CH4_CURRENT_APP_RXBUFFER,The Channel 0 Current Application Receive Buffer Address register points to the current Rx buffer address read by the DMA." hexmask.long 0x10 0.--31. 1. "CURRBUFAPTR,Application Receive Buffer Address Pointer The DMA updates this pointer during Rx operation. This pointer is cleared on reset." group.long 0x60++0x3 line.long 0x0 "DMA_CH4_STATUS,The software driver (application) reads the Status register during interrupt service routine or polling to determine the status of the DMA. Note: The number of DMA_CH[n]_Status register in the configuration is the higher of number of Rx.." hexmask.long.word 0x0 22.--31. 1. "RESERVED_31_22,Reserved." newline rbitfld.long 0x0 19.--21. "REB,Rx DMA Error Bits This field indicates the type of error that caused a Bus Error. For example error response on the AHB or AXI interface. - Bit 21 -- 1'b1: Error during data transfer by Rx DMA -- 1'b0: No Error during data transfer by Rx DMA - Bit.." "Error during write transfer,Error during read transfer,?,?,?,?,?,?" newline rbitfld.long 0x0 16.--18. "TEB,Tx DMA Error Bits This field indicates the type of error that caused a Bus Error. For example error response on the AHB or AXI interface. - Bit 18 -- 1'b1: Error during data transfer by Tx DMA -- 1'b0: No Error during data transfer by Tx DMA - Bit.." "Error during write transfer,Error during read transfer,?,?,?,?,?,?" newline bitfld.long 0x0 15. "NIS,Normal Interrupt Summary Normal Interrupt Summary bit value is the logical OR of the following bits when the corresponding interrupt bits are enabled in the DMA_CH0_Interrupt_Enable register: - Bit 0: Transmit Interrupt - Bit 2: Transmit Buffer.." "Normal Interrupt Summary status not detected,Normal Interrupt Summary status detected" newline bitfld.long 0x0 14. "AIS,Abnormal Interrupt Summary Abnormal Interrupt Summary bit value is the logical OR of the following when the corresponding interrupt bits are enabled in the DMA_CH0_Interrupt_Enable register: - Bit 1: Transmit Process Stopped - Bit 7: Receive Buffer.." "Abnormal Interrupt Summary status not detected,Abnormal Interrupt Summary status detected" newline bitfld.long 0x0 13. "CDE,Context Descriptor Error This bit indicates that the DMA Tx/Rx engine received a descriptor error which indicates invalid context in the middle of packet flow ( intermediate descriptor) or all one's descriptor in Tx case and on Rx side it indicates.." "Context Descriptor Error status not detected,Context Descriptor Error status detected" newline bitfld.long 0x0 12. "FBE,Fatal Bus Error This bit indicates that a bus error occurred (as described in the EB field). When this bit is set the corresponding DMA channel engine disables all bus accesses. Access restriction applies. Self-set to 1 on internal event. Setting 1.." "Fatal Bus Error status not detected,Fatal Bus Error status detected" newline bitfld.long 0x0 11. "ERI,Early Receive Interrupt This bit when set indicates that the RxDMA has completed the transfer of packet data to the memory. In configs supporting ERIC When ERIC=0 this bit is set only after the Rx DMA has filled up a complete receive buffer with.." "Early Receive Interrupt status not detected,Early Receive Interrupt status detected" newline bitfld.long 0x0 10. "ETI,Early Transmit Interrupt This bit when set indicates that the TxDMA has completed the transfer of packet data to the MTL TXFIFO memory. In configs supporting ERIC: When ETIC=0 this bit is set only after the Tx DMA has transferred a complete packet.." "Early Transmit Interrupt status not detected,Early Transmit Interrupt status detected" newline bitfld.long 0x0 9. "RWT,Receive Watchdog Timeout This bit is asserted when a packet with length greater than 2 048 bytes (10 240 bytes when Jumbo Packet mode is enabled) is received. 0x1: Receive Watchdog Timeout status detected 0x0: Receive Watchdog Timeout status not.." "Receive Watchdog Timeout status not detected,Receive Watchdog Timeout status detected" newline bitfld.long 0x0 8. "RPS,Receive Process Stopped This bit is asserted when the Rx process enters the Stopped state. Access restriction applies. Self-set to 1 on internal event. Setting 1 clears. Setting 0 has no effect. 0x1: Receive Process Stopped status detected 0x0:.." "Receive Process Stopped status not detected,Receive Process Stopped status detected" newline bitfld.long 0x0 7. "RBU,Receive Buffer Unavailable This bit indicates that the application owns the next descriptor in the Receive list and the DMA cannot acquire it. The Rx process is suspended. To resume processing Rx descriptors the application should change the.." "Receive Buffer Unavailable status not detected,Receive Buffer Unavailable status detected" newline bitfld.long 0x0 6. "RI,Receive Interrupt This bit indicates that the packet reception is complete. When packet reception is complete Bit 31 of RDES3 is reset in the last descriptor and the specific packet status information is updated in the descriptor. The reception.." "Receive Interrupt status not detected,Receive Interrupt status detected" newline rbitfld.long 0x0 3.--5. "RESERVED_5_3,Reserved." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 2. "TBU,Transmit Buffer Unavailable This bit indicates that the application owns the next descriptor in the Transmit list and the DMA cannot acquire it. Transmission is suspended. The TPS0 field of the DMA_Debug_Status0 register explains the Transmit.." "Transmit Buffer Unavailable status not detected,Transmit Buffer Unavailable status detected" newline bitfld.long 0x0 1. "TPS,Transmit Process Stopped This bit is set when the transmission is stopped. Access restriction applies. Self-set to 1 on internal event. Setting 1 clears. Setting 0 has no effect. 0x1: Transmit Process Stopped status detected 0x0: Transmit Process.." "Transmit Process Stopped status not detected,Transmit Process Stopped status detected" newline bitfld.long 0x0 0. "TI,Transmit Interrupt This bit indicates that the packet transmission is complete. When transmission is complete Bit 31 of TDES3 is reset in the last descriptor and the specific packet status information is updated in the descriptor. Access restriction.." "Transmit Interrupt status not detected,Transmit Interrupt status detected" rgroup.long 0x64++0xB line.long 0x0 "DMA_CH4_MISS_FRAME_CNT,This register has the number of packet counter that got dropped by the DMA either due to Bus Error or due to programming RPF field in DMA_CH{i}_Rx_Control register." hexmask.long.word 0x0 16.--31. 1. "RESERVED_31_16,Reserved." newline bitfld.long 0x0 15. "MFCO,Overflow status of the MFC Counter When this bit is set then the MFC counter does not get incremented further. The bit gets cleared when this register is read. Access restriction applies. Clears on read. Self-set to 1 on internal event. 0x1: Miss.." "Miss Frame Counter overflow not occurred,Miss Frame Counter overflow occurred" newline hexmask.long.byte 0x0 11.--14. 1. "RESERVED_14_11,Reserved." newline hexmask.long.word 0x0 0.--10. 1. "MFC,Dropped Packet Counters This counter indicates the number of packet counters that are dropped by the DMA either because of bus error or because of programing RPF field in DMA_CH{i}_Rx_Control register. The counter gets cleared when this register is.." line.long 0x4 "DMA_CH4_RXP_ACCEPT_CNT,The DMA_CH(#i)_RXP_Accept_Cnt registers provides the count of the number of frames accepted by Rx Parser." bitfld.long 0x4 31. "RXPACOF,Rx Parser Accept Counter Overflow Bit When set this bit indicates that the RXPAC Counter field crossed the maximum limit. Access restriction applies. Clears on read. Self-set to 1 on internal event. 0x1: Rx Parser Accept Counter overflow.." "Rx Parser Accept Counter overflow not occurred,Rx Parser Accept Counter overflow occurred" newline hexmask.long 0x4 0.--30. 1. "RXPAC,Rx Parser Accept Counter This 31-bit counter is implemented whenever a Rx Parser Accept a packet due to AF =1. The counter is cleared when the register is read." line.long 0x8 "DMA_CH4_RX_ERI_CNT,The DMA_CH(#i)_RX_ERI_Cnt registers provides the count of the number of times ERI was asserted." hexmask.long.tbyte 0x8 12.--31. 1. "RESERVED_31_12," newline hexmask.long.word 0x8 0.--11. 1. "ECNT,ERI Counter When ERIC bit of DMA_CH(#i)_RX_Control register is set this counter increments for burst transfer completed by the Rx DMA from the start of packet transfer. This counter will get reset at the start of new packet." tree.end tree.end repeat.end endif tree.end sif (CORENAME()=="CORTEXA55") tree "GIC (Generic Interrupt Controller)" tree "GIC_A55" base ad:0x35440000 tree "Distributor" rgroup.long (0x0+0x4096)++0xB line.long 0x0 "GICD_CTLR,Distributor Control Register" line.long 0x4 "GICD_TYPER,Interrupt Controller Type Register" line.long 0x8 "GICD_IIDR,Distributor Implementer Identification Register" repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x4 0x8 0xC 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C ) rgroup.long ($2+0x80+0x4096)++0x3 line.long 0x0 "GICD_IGROUPR$1,Interrupt Group Registers" repeat.end repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x4 0x8 0xC 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C ) rgroup.long ($2+0x100+0x4096)++0x3 line.long 0x0 "GICD_ISENABLER$1,Interrupt Set-Enable Registers" repeat.end repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x4 0x8 0xC 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C ) rgroup.long ($2+0x180+0x4096)++0x3 line.long 0x0 "GICD_ICENABLER$1,Interrupt Clear-Enable Registers" repeat.end repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x4 0x8 0xC 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C ) rgroup.long ($2+0x200+0x4096)++0x3 line.long 0x0 "GICD_ISPENDR$1,Interrupt Set-Pending Registers" repeat.end repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x4 0x8 0xC 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C ) rgroup.long ($2+0x280+0x4096)++0x3 line.long 0x0 "GICD_ICPENDR$1,Interrupt Clear-Pending Registers" repeat.end repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x4 0x8 0xC 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C ) rgroup.long ($2+0x300+0x4096)++0x3 line.long 0x0 "GICD_ISACTIVER$1,Interrupt Set-Active Registers" repeat.end repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x4 0x8 0xC 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C ) rgroup.long ($2+0x380+0x4096)++0x3 line.long 0x0 "GICD_ICACTIVER$1,Interrupt Clear-Active Registers" repeat.end repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x4 0x8 0xC 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C ) rgroup.long ($2+0x400+0x4096)++0x3 line.long 0x0 "GICD_IPRIORITYR$1,Interrupt Priority Registers" repeat.end repeat 16. (list 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1A 0x1B 0x1C 0x1D 0x1E 0x1F )(list 0x40 0x44 0x48 0x4C 0x50 0x54 0x58 0x5C 0x60 0x64 0x68 0x6C 0x70 0x74 0x78 0x7C ) rgroup.long ($2+0x400+0x4096)++0x3 line.long 0x0 "GICD_IPRIORITYR$1,Interrupt Priority Registers" repeat.end repeat 16. (list 0x20 0x21 0x22 0x23 0x24 0x25 0x26 0x27 0x28 0x29 0x2A 0x2B 0x2C 0x2D 0x2E 0x2F )(list 0x80 0x84 0x88 0x8C 0x90 0x94 0x98 0x9C 0xA0 0xA4 0xA8 0xAC 0xB0 0xB4 0xB8 0xBC ) rgroup.long ($2+0x400+0x4096)++0x3 line.long 0x0 "GICD_IPRIORITYR$1,Interrupt Priority Registers" repeat.end repeat 16. (list 0x30 0x31 0x32 0x33 0x34 0x35 0x36 0x37 0x38 0x39 0x3A 0x3B 0x3C 0x3D 0x3E 0x3F )(list 0xC0 0xC4 0xC8 0xCC 0xD0 0xD4 0xD8 0xDC 0xE0 0xE4 0xE8 0xEC 0xF0 0xF4 0xF8 0xFC ) rgroup.long ($2+0x400+0x4096)++0x3 line.long 0x0 "GICD_IPRIORITYR$1,Interrupt Priority Registers" repeat.end repeat 16. (list 0x40 0x41 0x42 0x43 0x44 0x45 0x46 0x47 0x48 0x49 0x4A 0x4B 0x4C 0x4D 0x4E 0x4F )(list 0x100 0x104 0x108 0x10C 0x110 0x114 0x118 0x11C 0x120 0x124 0x128 0x12C 0x130 0x134 0x138 0x13C ) rgroup.long ($2+0x400+0x4096)++0x3 line.long 0x0 "GICD_IPRIORITYR$1,Interrupt Priority Registers" repeat.end repeat 16. (list 0x50 0x51 0x52 0x53 0x54 0x55 0x56 0x57 0x58 0x59 0x5A 0x5B 0x5C 0x5D 0x5E 0x5F )(list 0x140 0x144 0x148 0x14C 0x150 0x154 0x158 0x15C 0x160 0x164 0x168 0x16C 0x170 0x174 0x178 0x17C ) rgroup.long ($2+0x400+0x4096)++0x3 line.long 0x0 "GICD_IPRIORITYR$1,Interrupt Priority Registers" repeat.end repeat 16. (list 0x60 0x61 0x62 0x63 0x64 0x65 0x66 0x67 0x68 0x69 0x6A 0x6B 0x6C 0x6D 0x6E 0x6F )(list 0x180 0x184 0x188 0x18C 0x190 0x194 0x198 0x19C 0x1A0 0x1A4 0x1A8 0x1AC 0x1B0 0x1B4 0x1B8 0x1BC ) rgroup.long ($2+0x400+0x4096)++0x3 line.long 0x0 "GICD_IPRIORITYR$1,Interrupt Priority Registers" repeat.end repeat 16. (list 0x70 0x71 0x72 0x73 0x74 0x75 0x76 0x77 0x78 0x79 0x7A 0x7B 0x7C 0x7D 0x7E 0x7F )(list 0x1C0 0x1C4 0x1C8 0x1CC 0x1D0 0x1D4 0x1D8 0x1DC 0x1E0 0x1E4 0x1E8 0x1EC 0x1F0 0x1F4 0x1F8 0x1FC ) rgroup.long ($2+0x400+0x4096)++0x3 line.long 0x0 "GICD_IPRIORITYR$1,Interrupt Priority Registers" repeat.end repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x4 0x8 0xC 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C ) rgroup.long ($2+0x800+0x4096)++0x3 line.long 0x0 "GICD_ITARGETSR$1,Interrupt Processor Targets Registers" repeat.end repeat 16. (list 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1A 0x1B 0x1C 0x1D 0x1E 0x1F )(list 0x40 0x44 0x48 0x4C 0x50 0x54 0x58 0x5C 0x60 0x64 0x68 0x6C 0x70 0x74 0x78 0x7C ) rgroup.long ($2+0x800+0x4096)++0x3 line.long 0x0 "GICD_ITARGETSR$1,Interrupt Processor Targets Registers" repeat.end repeat 16. (list 0x20 0x21 0x22 0x23 0x24 0x25 0x26 0x27 0x28 0x29 0x2A 0x2B 0x2C 0x2D 0x2E 0x2F )(list 0x80 0x84 0x88 0x8C 0x90 0x94 0x98 0x9C 0xA0 0xA4 0xA8 0xAC 0xB0 0xB4 0xB8 0xBC ) rgroup.long ($2+0x800+0x4096)++0x3 line.long 0x0 "GICD_ITARGETSR$1,Interrupt Processor Targets Registers" repeat.end repeat 16. (list 0x30 0x31 0x32 0x33 0x34 0x35 0x36 0x37 0x38 0x39 0x3A 0x3B 0x3C 0x3D 0x3E 0x3F )(list 0xC0 0xC4 0xC8 0xCC 0xD0 0xD4 0xD8 0xDC 0xE0 0xE4 0xE8 0xEC 0xF0 0xF4 0xF8 0xFC ) rgroup.long ($2+0x800+0x4096)++0x3 line.long 0x0 "GICD_ITARGETSR$1,Interrupt Processor Targets Registers" repeat.end repeat 16. (list 0x40 0x41 0x42 0x43 0x44 0x45 0x46 0x47 0x48 0x49 0x4A 0x4B 0x4C 0x4D 0x4E 0x4F )(list 0x100 0x104 0x108 0x10C 0x110 0x114 0x118 0x11C 0x120 0x124 0x128 0x12C 0x130 0x134 0x138 0x13C ) rgroup.long ($2+0x800+0x4096)++0x3 line.long 0x0 "GICD_ITARGETSR$1,Interrupt Processor Targets Registers" repeat.end repeat 16. (list 0x50 0x51 0x52 0x53 0x54 0x55 0x56 0x57 0x58 0x59 0x5A 0x5B 0x5C 0x5D 0x5E 0x5F )(list 0x140 0x144 0x148 0x14C 0x150 0x154 0x158 0x15C 0x160 0x164 0x168 0x16C 0x170 0x174 0x178 0x17C ) rgroup.long ($2+0x800+0x4096)++0x3 line.long 0x0 "GICD_ITARGETSR$1,Interrupt Processor Targets Registers" repeat.end repeat 16. (list 0x60 0x61 0x62 0x63 0x64 0x65 0x66 0x67 0x68 0x69 0x6A 0x6B 0x6C 0x6D 0x6E 0x6F )(list 0x180 0x184 0x188 0x18C 0x190 0x194 0x198 0x19C 0x1A0 0x1A4 0x1A8 0x1AC 0x1B0 0x1B4 0x1B8 0x1BC ) rgroup.long ($2+0x800+0x4096)++0x3 line.long 0x0 "GICD_ITARGETSR$1,Interrupt Processor Targets Registers" repeat.end repeat 16. (list 0x70 0x71 0x72 0x73 0x74 0x75 0x76 0x77 0x78 0x79 0x7A 0x7B 0x7C 0x7D 0x7E 0x7F )(list 0x1C0 0x1C4 0x1C8 0x1CC 0x1D0 0x1D4 0x1D8 0x1DC 0x1E0 0x1E4 0x1E8 0x1EC 0x1F0 0x1F4 0x1F8 0x1FC ) rgroup.long ($2+0x800+0x4096)++0x3 line.long 0x0 "GICD_ITARGETSR$1,Interrupt Processor Targets Registers" repeat.end repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x4 0x8 0xC 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C ) rgroup.long ($2+0xC00+0x4096)++0x3 line.long 0x0 "GICD_ICFGR$1,Interrupt Configuration Registers" repeat.end repeat 16. (list 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1A 0x1B 0x1C 0x1D 0x1E 0x1F )(list 0x40 0x44 0x48 0x4C 0x50 0x54 0x58 0x5C 0x60 0x64 0x68 0x6C 0x70 0x74 0x78 0x7C ) rgroup.long ($2+0xC00+0x4096)++0x3 line.long 0x0 "GICD_ICFGR$1,Interrupt Configuration Registers" repeat.end rgroup.long (0xD00+0x4096)++0x3 line.long 0x0 "GICD_PPISR,Private Peripheral Interrupt Status Register" repeat 15. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE )(list 0x0 0x4 0x8 0xC 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 ) rgroup.long ($2+0xD04+0x4096)++0x3 line.long 0x0 "GICD_SPISR$1,Shared Peripheral Interrupt Status Registers" repeat.end rgroup.long (0xF00+0x4096)++0x3 line.long 0x0 "GICD_SGIR,Software Generated Interrupt Register" repeat 4. (list 0x0 0x1 0x2 0x3 )(list 0x0 0x4 0x8 0xC ) rgroup.long ($2+0xF10+0x4096)++0x3 line.long 0x0 "GICD_CPENDSGIR$1,SGI Clear-Pending Registers" repeat.end repeat 4. (list 0x0 0x1 0x2 0x3 )(list 0x0 0x4 0x8 0xC ) rgroup.long ($2+0xF20+0x4096)++0x3 line.long 0x0 "GICD_SPENDSGIR$1,SGI Set-Pending Registers" repeat.end rgroup.long (0xFD0+0x4096)++0x2F line.long 0x0 "GICD_PIDR4,Peripheral ID4 Register" line.long 0x4 "GICD_PIDR5,Peripheral ID5 Register" line.long 0x8 "GICD_PIDR6,Peripheral ID6 Register" line.long 0xC "GICD_PIDR7,Peripheral ID7 Register" line.long 0x10 "GICD_PIDR0,Peripheral ID0 Register" line.long 0x14 "GICD_PIDR1,Peripheral ID1 Register" line.long 0x18 "GICD_PIDR2,Peripheral ID2 Register" line.long 0x1C "GICD_PIDR3,Peripheral ID3 Register" line.long 0x20 "GICD_CIDR0,Component ID0 Register" line.long 0x24 "GICD_CIDR1,Component ID1 Register" line.long 0x28 "GICD_CIDR2,Component ID2 Register" line.long 0x2C "GICD_CIDR3,Component ID3 Register" tree.end tree "CPUif" group.long (0x0+0x8192)++0x2B line.long 0x0 "GICC_CTLR,CPU Interface Control Register" line.long 0x4 "GICC_PMR,Interrupt Priority Mask Register" line.long 0x8 "GICC_BPR,Binary Point Register" line.long 0xC "GICC_IAR,Interrupt Acknowledge Register" line.long 0x10 "GICC_EOIR,End of Interrupt Register" line.long 0x14 "GICC_RPR,Running Priority Register" line.long 0x18 "GICC_HPPIR,Highest Priority Pending Interrupt Register" line.long 0x1C "GICC_ABPR,Aliased Binary Point Register" line.long 0x20 "GICC_AIAR,Aliased Interrupt Acknowledge Register" line.long 0x24 "GICC_AEOIR,Aliased End of Interrupt Register" line.long 0x28 "GICC_AHPPIR,Aliased Highest Priority Pending Interrupt Register" group.long (0xD0+0x8192)++0x3 line.long 0x0 "GICC_APR0,Active Priority Register" group.long (0xE0+0x8192)++0x3 line.long 0x0 "GICC_NSAPR0,Non-Secure Active Priority Register" group.long (0xFC+0x8192)++0x3 line.long 0x0 "GICC_IIDR,CPU Interface Identification Register" group.long (0x1000+0x8192)++0x3 line.long 0x0 "GICC_DIR,Deactivate Interrupt Register" tree.end tree "VCPUifHyp" group.long (0x0+0x16384)++0xB line.long 0x0 "GICH_HCR,Hypervisor Control Register" line.long 0x4 "GICH_VTR,VGIC Type Register" line.long 0x8 "GICH_VMCR,Virtual Machine Control Register" group.long (0x10+0x16384)++0x3 line.long 0x0 "GICH_MISR,Maintenance Interrupt Status Register" group.long (0x20+0x16384)++0x3 line.long 0x0 "GICH_EISR0,End of Interrupt Status Register" group.long (0x30+0x16384)++0x3 line.long 0x0 "GICH_ELSR0,Empty List register Status Register" group.long (0xF0+0x16384)++0x3 line.long 0x0 "GICH_APR0,Active Priority Register" repeat 4. (list 0x0 0x1 0x2 0x3 )(list 0x0 0x4 0x8 0xC ) group.long ($2+0x100+0x16384)++0x3 line.long 0x0 "GICH_LR$1,List Register 0" repeat.end tree.end tree "VCPUifHypAlias0" group.long (0x0+0x20480)++0xB line.long 0x0 "GICH_HCR,Hypervisor Control Register" line.long 0x4 "GICH_VTR,VGIC Type Register" line.long 0x8 "GICH_VMCR,Virtual Machine Control Register" group.long (0x10+0x20480)++0x3 line.long 0x0 "GICH_MISR,Maintenance Interrupt Status Register" group.long (0x20+0x20480)++0x3 line.long 0x0 "GICH_EISR0,End of Interrupt Status Register" group.long (0x30+0x20480)++0x3 line.long 0x0 "GICH_ELSR0,Empty List register Status Register" group.long (0xF0+0x20480)++0x3 line.long 0x0 "GICH_APR0,Active Priority Register" repeat 4. (list 0x0 0x1 0x2 0x3 )(list 0x0 0x4 0x8 0xC ) group.long ($2+0x100+0x20480)++0x3 line.long 0x0 "GICH_LR$1,List Register 0" repeat.end tree.end tree "VCPUifHypAlias1" group.long (0x0+0x20992)++0xB line.long 0x0 "GICH_HCR,Hypervisor Control Register" line.long 0x4 "GICH_VTR,VGIC Type Register" line.long 0x8 "GICH_VMCR,Virtual Machine Control Register" group.long (0x10+0x20992)++0x3 line.long 0x0 "GICH_MISR,Maintenance Interrupt Status Register" group.long (0x20+0x20992)++0x3 line.long 0x0 "GICH_EISR0,End of Interrupt Status Register" group.long (0x30+0x20992)++0x3 line.long 0x0 "GICH_ELSR0,Empty List register Status Register" group.long (0xF0+0x20992)++0x3 line.long 0x0 "GICH_APR0,Active Priority Register" repeat 4. (list 0x0 0x1 0x2 0x3 )(list 0x0 0x4 0x8 0xC ) group.long ($2+0x100+0x20992)++0x3 line.long 0x0 "GICH_LR$1,List Register 0" repeat.end tree.end tree "VCPUifHypAlias2" group.long (0x0+0x21504)++0xB line.long 0x0 "GICH_HCR,Hypervisor Control Register" line.long 0x4 "GICH_VTR,VGIC Type Register" line.long 0x8 "GICH_VMCR,Virtual Machine Control Register" group.long (0x10+0x21504)++0x3 line.long 0x0 "GICH_MISR,Maintenance Interrupt Status Register" group.long (0x20+0x21504)++0x3 line.long 0x0 "GICH_EISR0,End of Interrupt Status Register" group.long (0x30+0x21504)++0x3 line.long 0x0 "GICH_ELSR0,Empty List register Status Register" group.long (0xF0+0x21504)++0x3 line.long 0x0 "GICH_APR0,Active Priority Register" repeat 4. (list 0x0 0x1 0x2 0x3 )(list 0x0 0x4 0x8 0xC ) group.long ($2+0x100+0x21504)++0x3 line.long 0x0 "GICH_LR$1,List Register 0" repeat.end tree.end tree "VCPUifHypAlias3" group.long (0x0+0x22016)++0xB line.long 0x0 "GICH_HCR,Hypervisor Control Register" line.long 0x4 "GICH_VTR,VGIC Type Register" line.long 0x8 "GICH_VMCR,Virtual Machine Control Register" group.long (0x10+0x22016)++0x3 line.long 0x0 "GICH_MISR,Maintenance Interrupt Status Register" group.long (0x20+0x22016)++0x3 line.long 0x0 "GICH_EISR0,End of Interrupt Status Register" group.long (0x30+0x22016)++0x3 line.long 0x0 "GICH_ELSR0,Empty List register Status Register" group.long (0xF0+0x22016)++0x3 line.long 0x0 "GICH_APR0,Active Priority Register" repeat 4. (list 0x0 0x1 0x2 0x3 )(list 0x0 0x4 0x8 0xC ) group.long ($2+0x100+0x22016)++0x3 line.long 0x0 "GICH_LR$1,List Register 0" repeat.end tree.end tree "VCPUifHypAlias4" group.long (0x0+0x22528)++0xB line.long 0x0 "GICH_HCR,Hypervisor Control Register" line.long 0x4 "GICH_VTR,VGIC Type Register" line.long 0x8 "GICH_VMCR,Virtual Machine Control Register" group.long (0x10+0x22528)++0x3 line.long 0x0 "GICH_MISR,Maintenance Interrupt Status Register" group.long (0x20+0x22528)++0x3 line.long 0x0 "GICH_EISR0,End of Interrupt Status Register" group.long (0x30+0x22528)++0x3 line.long 0x0 "GICH_ELSR0,Empty List register Status Register" group.long (0xF0+0x22528)++0x3 line.long 0x0 "GICH_APR0,Active Priority Register" repeat 4. (list 0x0 0x1 0x2 0x3 )(list 0x0 0x4 0x8 0xC ) group.long ($2+0x100+0x22528)++0x3 line.long 0x0 "GICH_LR$1,List Register 0" repeat.end tree.end tree "VCPUifHypAlias5" group.long (0x0+0x23040)++0xB line.long 0x0 "GICH_HCR,Hypervisor Control Register" line.long 0x4 "GICH_VTR,VGIC Type Register" line.long 0x8 "GICH_VMCR,Virtual Machine Control Register" group.long (0x10+0x23040)++0x3 line.long 0x0 "GICH_MISR,Maintenance Interrupt Status Register" group.long (0x20+0x23040)++0x3 line.long 0x0 "GICH_EISR0,End of Interrupt Status Register" group.long (0x30+0x23040)++0x3 line.long 0x0 "GICH_ELSR0,Empty List register Status Register" group.long (0xF0+0x23040)++0x3 line.long 0x0 "GICH_APR0,Active Priority Register" repeat 4. (list 0x0 0x1 0x2 0x3 )(list 0x0 0x4 0x8 0xC ) group.long ($2+0x100+0x23040)++0x3 line.long 0x0 "GICH_LR$1,List Register 0" repeat.end tree.end tree "VCPUifHypAlias6" group.long (0x0+0x23552)++0xB line.long 0x0 "GICH_HCR,Hypervisor Control Register" line.long 0x4 "GICH_VTR,VGIC Type Register" line.long 0x8 "GICH_VMCR,Virtual Machine Control Register" group.long (0x10+0x23552)++0x3 line.long 0x0 "GICH_MISR,Maintenance Interrupt Status Register" group.long (0x20+0x23552)++0x3 line.long 0x0 "GICH_EISR0,End of Interrupt Status Register" group.long (0x30+0x23552)++0x3 line.long 0x0 "GICH_ELSR0,Empty List register Status Register" group.long (0xF0+0x23552)++0x3 line.long 0x0 "GICH_APR0,Active Priority Register" repeat 4. (list 0x0 0x1 0x2 0x3 )(list 0x0 0x4 0x8 0xC ) group.long ($2+0x100+0x23552)++0x3 line.long 0x0 "GICH_LR$1,List Register 0" repeat.end tree.end tree "VCPUifHypAlias7" group.long (0x0+0x24064)++0xB line.long 0x0 "GICH_HCR,Hypervisor Control Register" line.long 0x4 "GICH_VTR,VGIC Type Register" line.long 0x8 "GICH_VMCR,Virtual Machine Control Register" group.long (0x10+0x24064)++0x3 line.long 0x0 "GICH_MISR,Maintenance Interrupt Status Register" group.long (0x20+0x24064)++0x3 line.long 0x0 "GICH_EISR0,End of Interrupt Status Register" group.long (0x30+0x24064)++0x3 line.long 0x0 "GICH_ELSR0,Empty List register Status Register" group.long (0xF0+0x24064)++0x3 line.long 0x0 "GICH_APR0,Active Priority Register" repeat 4. (list 0x0 0x1 0x2 0x3 )(list 0x0 0x4 0x8 0xC ) group.long ($2+0x100+0x24064)++0x3 line.long 0x0 "GICH_LR$1,List Register 0" repeat.end tree.end tree "VCPUifVM " group.long (0x0+0x24576)++0x2B line.long 0x0 "GICV_CTLR,Virtual Machine Control Register" line.long 0x4 "GICV_PMR,VM Priority Mask Register" line.long 0x8 "GICV_BPR,VM Binary Point Register" line.long 0xC "GICV_IAR,VM Interrupt Acknowledge Register" line.long 0x10 "GICV_EOIR,VM End of Interrupt Register" line.long 0x14 "GICV_RPR,VM Running Priority Register" line.long 0x18 "GICV_HPPIR,VM Highest Priority Pending Interrupt Register" line.long 0x1C "GICV_ABPR,VM Aliased Binary Point Register" line.long 0x20 "GICV_AIAR,VM Aliased Interrupt Acknowledge Register" line.long 0x24 "GICV_AEOIR,VM Aliased End of Interrupt Register" line.long 0x28 "GICV_AHPPIR,VM Aliased Highest Priority Pending Interrupt Register" group.long (0xD0+0x24576)++0x3 line.long 0x0 "GICV_APR0,VM Active Priority Register" group.long (0xFC+0x24576)++0x3 line.long 0x0 "GICV_IIDR,VM CPU Interface Identification Register" group.long (0x1000+0x24576)++0x3 line.long 0x0 "GICV_DIR,VM Deactivate Interrupt Register" tree.end tree.end tree "GIC_A55_MP" base ad:0x35430000 tree "Distributor" rgroup.long (0x0+0x4096)++0xB line.long 0x0 "GICD_CTLR,Distributor Control Register" line.long 0x4 "GICD_TYPER,Interrupt Controller Type Register" line.long 0x8 "GICD_IIDR,Distributor Implementer Identification Register" repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x4 0x8 0xC 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C ) rgroup.long ($2+0x80+0x4096)++0x3 line.long 0x0 "GICD_IGROUPR$1,Interrupt Group Registers" repeat.end repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x4 0x8 0xC 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C ) rgroup.long ($2+0x100+0x4096)++0x3 line.long 0x0 "GICD_ISENABLER$1,Interrupt Set-Enable Registers" repeat.end repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x4 0x8 0xC 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C ) rgroup.long ($2+0x180+0x4096)++0x3 line.long 0x0 "GICD_ICENABLER$1,Interrupt Clear-Enable Registers" repeat.end repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x4 0x8 0xC 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C ) rgroup.long ($2+0x200+0x4096)++0x3 line.long 0x0 "GICD_ISPENDR$1,Interrupt Set-Pending Registers" repeat.end repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x4 0x8 0xC 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C ) rgroup.long ($2+0x280+0x4096)++0x3 line.long 0x0 "GICD_ICPENDR$1,Interrupt Clear-Pending Registers" repeat.end repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x4 0x8 0xC 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C ) rgroup.long ($2+0x300+0x4096)++0x3 line.long 0x0 "GICD_ISACTIVER$1,Interrupt Set-Active Registers" repeat.end repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x4 0x8 0xC 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C ) rgroup.long ($2+0x380+0x4096)++0x3 line.long 0x0 "GICD_ICACTIVER$1,Interrupt Clear-Active Registers" repeat.end repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x4 0x8 0xC 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C ) rgroup.long ($2+0x400+0x4096)++0x3 line.long 0x0 "GICD_IPRIORITYR$1,Interrupt Priority Registers" repeat.end repeat 16. (list 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1A 0x1B 0x1C 0x1D 0x1E 0x1F )(list 0x40 0x44 0x48 0x4C 0x50 0x54 0x58 0x5C 0x60 0x64 0x68 0x6C 0x70 0x74 0x78 0x7C ) rgroup.long ($2+0x400+0x4096)++0x3 line.long 0x0 "GICD_IPRIORITYR$1,Interrupt Priority Registers" repeat.end repeat 16. (list 0x20 0x21 0x22 0x23 0x24 0x25 0x26 0x27 0x28 0x29 0x2A 0x2B 0x2C 0x2D 0x2E 0x2F )(list 0x80 0x84 0x88 0x8C 0x90 0x94 0x98 0x9C 0xA0 0xA4 0xA8 0xAC 0xB0 0xB4 0xB8 0xBC ) rgroup.long ($2+0x400+0x4096)++0x3 line.long 0x0 "GICD_IPRIORITYR$1,Interrupt Priority Registers" repeat.end repeat 16. (list 0x30 0x31 0x32 0x33 0x34 0x35 0x36 0x37 0x38 0x39 0x3A 0x3B 0x3C 0x3D 0x3E 0x3F )(list 0xC0 0xC4 0xC8 0xCC 0xD0 0xD4 0xD8 0xDC 0xE0 0xE4 0xE8 0xEC 0xF0 0xF4 0xF8 0xFC ) rgroup.long ($2+0x400+0x4096)++0x3 line.long 0x0 "GICD_IPRIORITYR$1,Interrupt Priority Registers" repeat.end repeat 16. (list 0x40 0x41 0x42 0x43 0x44 0x45 0x46 0x47 0x48 0x49 0x4A 0x4B 0x4C 0x4D 0x4E 0x4F )(list 0x100 0x104 0x108 0x10C 0x110 0x114 0x118 0x11C 0x120 0x124 0x128 0x12C 0x130 0x134 0x138 0x13C ) rgroup.long ($2+0x400+0x4096)++0x3 line.long 0x0 "GICD_IPRIORITYR$1,Interrupt Priority Registers" repeat.end repeat 16. (list 0x50 0x51 0x52 0x53 0x54 0x55 0x56 0x57 0x58 0x59 0x5A 0x5B 0x5C 0x5D 0x5E 0x5F )(list 0x140 0x144 0x148 0x14C 0x150 0x154 0x158 0x15C 0x160 0x164 0x168 0x16C 0x170 0x174 0x178 0x17C ) rgroup.long ($2+0x400+0x4096)++0x3 line.long 0x0 "GICD_IPRIORITYR$1,Interrupt Priority Registers" repeat.end repeat 16. (list 0x60 0x61 0x62 0x63 0x64 0x65 0x66 0x67 0x68 0x69 0x6A 0x6B 0x6C 0x6D 0x6E 0x6F )(list 0x180 0x184 0x188 0x18C 0x190 0x194 0x198 0x19C 0x1A0 0x1A4 0x1A8 0x1AC 0x1B0 0x1B4 0x1B8 0x1BC ) rgroup.long ($2+0x400+0x4096)++0x3 line.long 0x0 "GICD_IPRIORITYR$1,Interrupt Priority Registers" repeat.end repeat 16. (list 0x70 0x71 0x72 0x73 0x74 0x75 0x76 0x77 0x78 0x79 0x7A 0x7B 0x7C 0x7D 0x7E 0x7F )(list 0x1C0 0x1C4 0x1C8 0x1CC 0x1D0 0x1D4 0x1D8 0x1DC 0x1E0 0x1E4 0x1E8 0x1EC 0x1F0 0x1F4 0x1F8 0x1FC ) rgroup.long ($2+0x400+0x4096)++0x3 line.long 0x0 "GICD_IPRIORITYR$1,Interrupt Priority Registers" repeat.end repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x4 0x8 0xC 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C ) rgroup.long ($2+0x800+0x4096)++0x3 line.long 0x0 "GICD_ITARGETSR$1,Interrupt Processor Targets Registers" repeat.end repeat 16. (list 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1A 0x1B 0x1C 0x1D 0x1E 0x1F )(list 0x40 0x44 0x48 0x4C 0x50 0x54 0x58 0x5C 0x60 0x64 0x68 0x6C 0x70 0x74 0x78 0x7C ) rgroup.long ($2+0x800+0x4096)++0x3 line.long 0x0 "GICD_ITARGETSR$1,Interrupt Processor Targets Registers" repeat.end repeat 16. (list 0x20 0x21 0x22 0x23 0x24 0x25 0x26 0x27 0x28 0x29 0x2A 0x2B 0x2C 0x2D 0x2E 0x2F )(list 0x80 0x84 0x88 0x8C 0x90 0x94 0x98 0x9C 0xA0 0xA4 0xA8 0xAC 0xB0 0xB4 0xB8 0xBC ) rgroup.long ($2+0x800+0x4096)++0x3 line.long 0x0 "GICD_ITARGETSR$1,Interrupt Processor Targets Registers" repeat.end repeat 16. (list 0x30 0x31 0x32 0x33 0x34 0x35 0x36 0x37 0x38 0x39 0x3A 0x3B 0x3C 0x3D 0x3E 0x3F )(list 0xC0 0xC4 0xC8 0xCC 0xD0 0xD4 0xD8 0xDC 0xE0 0xE4 0xE8 0xEC 0xF0 0xF4 0xF8 0xFC ) rgroup.long ($2+0x800+0x4096)++0x3 line.long 0x0 "GICD_ITARGETSR$1,Interrupt Processor Targets Registers" repeat.end repeat 16. (list 0x40 0x41 0x42 0x43 0x44 0x45 0x46 0x47 0x48 0x49 0x4A 0x4B 0x4C 0x4D 0x4E 0x4F )(list 0x100 0x104 0x108 0x10C 0x110 0x114 0x118 0x11C 0x120 0x124 0x128 0x12C 0x130 0x134 0x138 0x13C ) rgroup.long ($2+0x800+0x4096)++0x3 line.long 0x0 "GICD_ITARGETSR$1,Interrupt Processor Targets Registers" repeat.end repeat 16. (list 0x50 0x51 0x52 0x53 0x54 0x55 0x56 0x57 0x58 0x59 0x5A 0x5B 0x5C 0x5D 0x5E 0x5F )(list 0x140 0x144 0x148 0x14C 0x150 0x154 0x158 0x15C 0x160 0x164 0x168 0x16C 0x170 0x174 0x178 0x17C ) rgroup.long ($2+0x800+0x4096)++0x3 line.long 0x0 "GICD_ITARGETSR$1,Interrupt Processor Targets Registers" repeat.end repeat 16. (list 0x60 0x61 0x62 0x63 0x64 0x65 0x66 0x67 0x68 0x69 0x6A 0x6B 0x6C 0x6D 0x6E 0x6F )(list 0x180 0x184 0x188 0x18C 0x190 0x194 0x198 0x19C 0x1A0 0x1A4 0x1A8 0x1AC 0x1B0 0x1B4 0x1B8 0x1BC ) rgroup.long ($2+0x800+0x4096)++0x3 line.long 0x0 "GICD_ITARGETSR$1,Interrupt Processor Targets Registers" repeat.end repeat 16. (list 0x70 0x71 0x72 0x73 0x74 0x75 0x76 0x77 0x78 0x79 0x7A 0x7B 0x7C 0x7D 0x7E 0x7F )(list 0x1C0 0x1C4 0x1C8 0x1CC 0x1D0 0x1D4 0x1D8 0x1DC 0x1E0 0x1E4 0x1E8 0x1EC 0x1F0 0x1F4 0x1F8 0x1FC ) rgroup.long ($2+0x800+0x4096)++0x3 line.long 0x0 "GICD_ITARGETSR$1,Interrupt Processor Targets Registers" repeat.end repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x4 0x8 0xC 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C ) rgroup.long ($2+0xC00+0x4096)++0x3 line.long 0x0 "GICD_ICFGR$1,Interrupt Configuration Registers" repeat.end repeat 16. (list 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1A 0x1B 0x1C 0x1D 0x1E 0x1F )(list 0x40 0x44 0x48 0x4C 0x50 0x54 0x58 0x5C 0x60 0x64 0x68 0x6C 0x70 0x74 0x78 0x7C ) rgroup.long ($2+0xC00+0x4096)++0x3 line.long 0x0 "GICD_ICFGR$1,Interrupt Configuration Registers" repeat.end rgroup.long (0xD00+0x4096)++0x3 line.long 0x0 "GICD_PPISR,Private Peripheral Interrupt Status Register" repeat 15. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE )(list 0x0 0x4 0x8 0xC 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 ) rgroup.long ($2+0xD04+0x4096)++0x3 line.long 0x0 "GICD_SPISR$1,Shared Peripheral Interrupt Status Registers" repeat.end rgroup.long (0xF00+0x4096)++0x3 line.long 0x0 "GICD_SGIR,Software Generated Interrupt Register" repeat 4. (list 0x0 0x1 0x2 0x3 )(list 0x0 0x4 0x8 0xC ) rgroup.long ($2+0xF10+0x4096)++0x3 line.long 0x0 "GICD_CPENDSGIR$1,SGI Clear-Pending Registers" repeat.end repeat 4. (list 0x0 0x1 0x2 0x3 )(list 0x0 0x4 0x8 0xC ) rgroup.long ($2+0xF20+0x4096)++0x3 line.long 0x0 "GICD_SPENDSGIR$1,SGI Set-Pending Registers" repeat.end rgroup.long (0xFD0+0x4096)++0x2F line.long 0x0 "GICD_PIDR4,Peripheral ID4 Register" line.long 0x4 "GICD_PIDR5,Peripheral ID5 Register" line.long 0x8 "GICD_PIDR6,Peripheral ID6 Register" line.long 0xC "GICD_PIDR7,Peripheral ID7 Register" line.long 0x10 "GICD_PIDR0,Peripheral ID0 Register" line.long 0x14 "GICD_PIDR1,Peripheral ID1 Register" line.long 0x18 "GICD_PIDR2,Peripheral ID2 Register" line.long 0x1C "GICD_PIDR3,Peripheral ID3 Register" line.long 0x20 "GICD_CIDR0,Component ID0 Register" line.long 0x24 "GICD_CIDR1,Component ID1 Register" line.long 0x28 "GICD_CIDR2,Component ID2 Register" line.long 0x2C "GICD_CIDR3,Component ID3 Register" tree.end tree "CPUif" group.long (0x0+0x8192)++0x2B line.long 0x0 "GICC_CTLR,CPU Interface Control Register" line.long 0x4 "GICC_PMR,Interrupt Priority Mask Register" line.long 0x8 "GICC_BPR,Binary Point Register" line.long 0xC "GICC_IAR,Interrupt Acknowledge Register" line.long 0x10 "GICC_EOIR,End of Interrupt Register" line.long 0x14 "GICC_RPR,Running Priority Register" line.long 0x18 "GICC_HPPIR,Highest Priority Pending Interrupt Register" line.long 0x1C "GICC_ABPR,Aliased Binary Point Register" line.long 0x20 "GICC_AIAR,Aliased Interrupt Acknowledge Register" line.long 0x24 "GICC_AEOIR,Aliased End of Interrupt Register" line.long 0x28 "GICC_AHPPIR,Aliased Highest Priority Pending Interrupt Register" group.long (0xD0+0x8192)++0x3 line.long 0x0 "GICC_APR0,Active Priority Register" group.long (0xE0+0x8192)++0x3 line.long 0x0 "GICC_NSAPR0,Non-Secure Active Priority Register" group.long (0xFC+0x8192)++0x3 line.long 0x0 "GICC_IIDR,CPU Interface Identification Register" group.long (0x1000+0x8192)++0x3 line.long 0x0 "GICC_DIR,Deactivate Interrupt Register" tree.end tree "VCPUifHyp" group.long (0x0+0x16384)++0xB line.long 0x0 "GICH_HCR,Hypervisor Control Register" line.long 0x4 "GICH_VTR,VGIC Type Register" line.long 0x8 "GICH_VMCR,Virtual Machine Control Register" group.long (0x10+0x16384)++0x3 line.long 0x0 "GICH_MISR,Maintenance Interrupt Status Register" group.long (0x20+0x16384)++0x3 line.long 0x0 "GICH_EISR0,End of Interrupt Status Register" group.long (0x30+0x16384)++0x3 line.long 0x0 "GICH_ELSR0,Empty List register Status Register" group.long (0xF0+0x16384)++0x3 line.long 0x0 "GICH_APR0,Active Priority Register" repeat 4. (list 0x0 0x1 0x2 0x3 )(list 0x0 0x4 0x8 0xC ) group.long ($2+0x100+0x16384)++0x3 line.long 0x0 "GICH_LR$1,List Register 0" repeat.end tree.end tree "VCPUifHypAlias0" group.long (0x0+0x20480)++0xB line.long 0x0 "GICH_HCR,Hypervisor Control Register" line.long 0x4 "GICH_VTR,VGIC Type Register" line.long 0x8 "GICH_VMCR,Virtual Machine Control Register" group.long (0x10+0x20480)++0x3 line.long 0x0 "GICH_MISR,Maintenance Interrupt Status Register" group.long (0x20+0x20480)++0x3 line.long 0x0 "GICH_EISR0,End of Interrupt Status Register" group.long (0x30+0x20480)++0x3 line.long 0x0 "GICH_ELSR0,Empty List register Status Register" group.long (0xF0+0x20480)++0x3 line.long 0x0 "GICH_APR0,Active Priority Register" repeat 4. (list 0x0 0x1 0x2 0x3 )(list 0x0 0x4 0x8 0xC ) group.long ($2+0x100+0x20480)++0x3 line.long 0x0 "GICH_LR$1,List Register 0" repeat.end tree.end tree "VCPUifHypAlias1" group.long (0x0+0x20992)++0xB line.long 0x0 "GICH_HCR,Hypervisor Control Register" line.long 0x4 "GICH_VTR,VGIC Type Register" line.long 0x8 "GICH_VMCR,Virtual Machine Control Register" group.long (0x10+0x20992)++0x3 line.long 0x0 "GICH_MISR,Maintenance Interrupt Status Register" group.long (0x20+0x20992)++0x3 line.long 0x0 "GICH_EISR0,End of Interrupt Status Register" group.long (0x30+0x20992)++0x3 line.long 0x0 "GICH_ELSR0,Empty List register Status Register" group.long (0xF0+0x20992)++0x3 line.long 0x0 "GICH_APR0,Active Priority Register" repeat 4. (list 0x0 0x1 0x2 0x3 )(list 0x0 0x4 0x8 0xC ) group.long ($2+0x100+0x20992)++0x3 line.long 0x0 "GICH_LR$1,List Register 0" repeat.end tree.end tree "VCPUifHypAlias2" group.long (0x0+0x21504)++0xB line.long 0x0 "GICH_HCR,Hypervisor Control Register" line.long 0x4 "GICH_VTR,VGIC Type Register" line.long 0x8 "GICH_VMCR,Virtual Machine Control Register" group.long (0x10+0x21504)++0x3 line.long 0x0 "GICH_MISR,Maintenance Interrupt Status Register" group.long (0x20+0x21504)++0x3 line.long 0x0 "GICH_EISR0,End of Interrupt Status Register" group.long (0x30+0x21504)++0x3 line.long 0x0 "GICH_ELSR0,Empty List register Status Register" group.long (0xF0+0x21504)++0x3 line.long 0x0 "GICH_APR0,Active Priority Register" repeat 4. (list 0x0 0x1 0x2 0x3 )(list 0x0 0x4 0x8 0xC ) group.long ($2+0x100+0x21504)++0x3 line.long 0x0 "GICH_LR$1,List Register 0" repeat.end tree.end tree "VCPUifHypAlias3" group.long (0x0+0x22016)++0xB line.long 0x0 "GICH_HCR,Hypervisor Control Register" line.long 0x4 "GICH_VTR,VGIC Type Register" line.long 0x8 "GICH_VMCR,Virtual Machine Control Register" group.long (0x10+0x22016)++0x3 line.long 0x0 "GICH_MISR,Maintenance Interrupt Status Register" group.long (0x20+0x22016)++0x3 line.long 0x0 "GICH_EISR0,End of Interrupt Status Register" group.long (0x30+0x22016)++0x3 line.long 0x0 "GICH_ELSR0,Empty List register Status Register" group.long (0xF0+0x22016)++0x3 line.long 0x0 "GICH_APR0,Active Priority Register" repeat 4. (list 0x0 0x1 0x2 0x3 )(list 0x0 0x4 0x8 0xC ) group.long ($2+0x100+0x22016)++0x3 line.long 0x0 "GICH_LR$1,List Register 0" repeat.end tree.end tree "VCPUifHypAlias4" group.long (0x0+0x22528)++0xB line.long 0x0 "GICH_HCR,Hypervisor Control Register" line.long 0x4 "GICH_VTR,VGIC Type Register" line.long 0x8 "GICH_VMCR,Virtual Machine Control Register" group.long (0x10+0x22528)++0x3 line.long 0x0 "GICH_MISR,Maintenance Interrupt Status Register" group.long (0x20+0x22528)++0x3 line.long 0x0 "GICH_EISR0,End of Interrupt Status Register" group.long (0x30+0x22528)++0x3 line.long 0x0 "GICH_ELSR0,Empty List register Status Register" group.long (0xF0+0x22528)++0x3 line.long 0x0 "GICH_APR0,Active Priority Register" repeat 4. (list 0x0 0x1 0x2 0x3 )(list 0x0 0x4 0x8 0xC ) group.long ($2+0x100+0x22528)++0x3 line.long 0x0 "GICH_LR$1,List Register 0" repeat.end tree.end tree "VCPUifHypAlias5" group.long (0x0+0x23040)++0xB line.long 0x0 "GICH_HCR,Hypervisor Control Register" line.long 0x4 "GICH_VTR,VGIC Type Register" line.long 0x8 "GICH_VMCR,Virtual Machine Control Register" group.long (0x10+0x23040)++0x3 line.long 0x0 "GICH_MISR,Maintenance Interrupt Status Register" group.long (0x20+0x23040)++0x3 line.long 0x0 "GICH_EISR0,End of Interrupt Status Register" group.long (0x30+0x23040)++0x3 line.long 0x0 "GICH_ELSR0,Empty List register Status Register" group.long (0xF0+0x23040)++0x3 line.long 0x0 "GICH_APR0,Active Priority Register" repeat 4. (list 0x0 0x1 0x2 0x3 )(list 0x0 0x4 0x8 0xC ) group.long ($2+0x100+0x23040)++0x3 line.long 0x0 "GICH_LR$1,List Register 0" repeat.end tree.end tree "VCPUifHypAlias6" group.long (0x0+0x23552)++0xB line.long 0x0 "GICH_HCR,Hypervisor Control Register" line.long 0x4 "GICH_VTR,VGIC Type Register" line.long 0x8 "GICH_VMCR,Virtual Machine Control Register" group.long (0x10+0x23552)++0x3 line.long 0x0 "GICH_MISR,Maintenance Interrupt Status Register" group.long (0x20+0x23552)++0x3 line.long 0x0 "GICH_EISR0,End of Interrupt Status Register" group.long (0x30+0x23552)++0x3 line.long 0x0 "GICH_ELSR0,Empty List register Status Register" group.long (0xF0+0x23552)++0x3 line.long 0x0 "GICH_APR0,Active Priority Register" repeat 4. (list 0x0 0x1 0x2 0x3 )(list 0x0 0x4 0x8 0xC ) group.long ($2+0x100+0x23552)++0x3 line.long 0x0 "GICH_LR$1,List Register 0" repeat.end tree.end tree "VCPUifHypAlias7" group.long (0x0+0x24064)++0xB line.long 0x0 "GICH_HCR,Hypervisor Control Register" line.long 0x4 "GICH_VTR,VGIC Type Register" line.long 0x8 "GICH_VMCR,Virtual Machine Control Register" group.long (0x10+0x24064)++0x3 line.long 0x0 "GICH_MISR,Maintenance Interrupt Status Register" group.long (0x20+0x24064)++0x3 line.long 0x0 "GICH_EISR0,End of Interrupt Status Register" group.long (0x30+0x24064)++0x3 line.long 0x0 "GICH_ELSR0,Empty List register Status Register" group.long (0xF0+0x24064)++0x3 line.long 0x0 "GICH_APR0,Active Priority Register" repeat 4. (list 0x0 0x1 0x2 0x3 )(list 0x0 0x4 0x8 0xC ) group.long ($2+0x100+0x24064)++0x3 line.long 0x0 "GICH_LR$1,List Register 0" repeat.end tree.end tree "VCPUifVM " group.long (0x0+0x24576)++0x2B line.long 0x0 "GICV_CTLR,Virtual Machine Control Register" line.long 0x4 "GICV_PMR,VM Priority Mask Register" line.long 0x8 "GICV_BPR,VM Binary Point Register" line.long 0xC "GICV_IAR,VM Interrupt Acknowledge Register" line.long 0x10 "GICV_EOIR,VM End of Interrupt Register" line.long 0x14 "GICV_RPR,VM Running Priority Register" line.long 0x18 "GICV_HPPIR,VM Highest Priority Pending Interrupt Register" line.long 0x1C "GICV_ABPR,VM Aliased Binary Point Register" line.long 0x20 "GICV_AIAR,VM Aliased Interrupt Acknowledge Register" line.long 0x24 "GICV_AEOIR,VM Aliased End of Interrupt Register" line.long 0x28 "GICV_AHPPIR,VM Aliased Highest Priority Pending Interrupt Register" group.long (0xD0+0x24576)++0x3 line.long 0x0 "GICV_APR0,VM Active Priority Register" group.long (0xFC+0x24576)++0x3 line.long 0x0 "GICV_IIDR,VM CPU Interface Identification Register" group.long (0x1000+0x24576)++0x3 line.long 0x0 "GICV_DIR,VM Deactivate Interrupt Register" tree.end tree.end tree.end endif tree "GPIO (General-Purpose IO Controller)" sif (CORENAME()=="CORTEXR5F") repeat 5. (increment 1. 1.) (list ad:0xF0000000 ad:0xF0400000 ad:0xF0410000 ad:0xF0420000 ad:0xF0430000) tree "GPIO$1" base $2 repeat 4. (list 0x0 0x1 0x2 0x3 )(list 0x0 0x10 0x20 0x30 ) group.long ($2)++0x3 line.long 0x0 "GPIO_CTRL_$1,gpio overall control and status register" rbitfld.long 0x0 14. "PCLK_ACTIVE,status of pclk: 1: pclk is active 0: pclk is inactive" "pclk is inactive,pclk is active" newline bitfld.long 0x0 13. "INT_CLK_SEL,selection of gpio interrupt clock 0: pclk 1: 32kHz" "pclk,?" bitfld.long 0x0 12. "INT_DEB_EN,control of gpio interrupt debounce. 0: disable 1: enable" "disable,enable" newline bitfld.long 0x0 11. "INT_LEV_SYNC,gpio level sensitive sync enable 0: disable 1: enable" "disable,enable" bitfld.long 0x0 10. "INT_EDGE_CLR,gpio edge sensitive interrupt clear. this bit is auto cleared. no need to clear it to 0 after program to 1. 0: not clear 1: clear" "not clear,clear" newline rbitfld.long 0x0 9. "INT_STATUS_UNMASK,gpio interrupt unmasked status 0: interrupt not active 1: interrupt active" "interrupt not active,interrupt active" rbitfld.long 0x0 8. "INT_STATUS,gpio interrupt status. 0: interrupt not active 1: interrupt active" "interrupt not active,interrupt active" newline bitfld.long 0x0 7. "INT_BOTH_EDGE,gpio interrupt both sensitive type 0: single edge sensitive 1: both edge sensitive" "single edge sensitive,both edge sensitive" bitfld.long 0x0 6. "INT_POL,gpio interrupt polarity. 0: low active or negedge active 1: high active or posedge active" "low active or negedge active,high active or posedge active" newline bitfld.long 0x0 5. "INT_TYPE,gpio interrupt type 0: Interrupt is level sensitive 1: Interrupt is edge sensitive" "Interrupt is level sensitive,Interrupt is edge sensitive" bitfld.long 0x0 4. "INT_MASK,gpio interrupt mask 0: interrupt not mask 1: interrupt mask" "interrupt not mask,interrupt mask" newline bitfld.long 0x0 3. "INT_EN,gpio interrupt enable 0: disable 1: enable" "disable,enable" bitfld.long 0x0 2. "DATA_OUT,gpio output data" "0,1" newline rbitfld.long 0x0 1. "DATA_IN,gpio input data" "0,1" bitfld.long 0x0 0. "DIR,gpio direction. 0: input mode 1: output mode" "input mode,output mode" repeat.end group.long 0x2000++0x3 line.long 0x0 "GPIO_DIR_0,gpio direction control for 32 gpio at once" hexmask.long 0x0 0.--31. 1. "DIR,gpio direction control for 32 gpio at once" rgroup.long 0x2200++0x3 line.long 0x0 "GPIO_DATA_IN_0,gpio data input" hexmask.long 0x0 0.--31. 1. "DATA_IN,gpio data input" group.long 0x2400++0x3 line.long 0x0 "GPIO_DATA_OUT_0,gpio data output" hexmask.long 0x0 0.--31. 1. "DATA_OUT,gpio data output" group.long 0x2600++0x3 line.long 0x0 "GPIO_INT_EN_0,gpio interrupt enable" hexmask.long 0x0 0.--31. 1. "INT_EN,gpio interrupt enable" group.long 0x2800++0x3 line.long 0x0 "GPIO_INT_MASK_0,gpio interrupt mask" hexmask.long 0x0 0.--31. 1. "INT_MASK,gpio interrupt mask" group.long 0x2A00++0x3 line.long 0x0 "GPIO_INT_TYPE_0,gpio interrupt type" hexmask.long 0x0 0.--31. 1. "INT_TYPE,0: Interrupt is level sensitive 1: Interrupt is edge sensitive" group.long 0x2C00++0x3 line.long 0x0 "GPIO_INT_POL_0,gpio interrupt polarity" hexmask.long 0x0 0.--31. 1. "INT_POL,gpio interrupt polarity. 0: low active or negedge active 1: high active or posedge active" group.long 0x2E00++0x3 line.long 0x0 "GPIO_INT_BOTH_EDGE_0,gpio interrupt both edge sensitive enable" hexmask.long 0x0 0.--31. 1. "INT_BOTH_EDGE,gpio interrupt both sensitive type 0: single edge sensitive 1: both edge sensitive" rgroup.long 0x3000++0x3 line.long 0x0 "GPIO_INT_STATUS_0,gpio interrupt status" hexmask.long 0x0 0.--31. 1. "INT_STATUS,gpio interrupt status. 0: interrupt not active 1: interrupt active" rgroup.long 0x3200++0x3 line.long 0x0 "GPIO_INT_STATUS_UNMASK_0,gpio interrupt unmasked status" hexmask.long 0x0 0.--31. 1. "INT_STATUS_UNMASK,gpio interrupt unmasked status 0: interrupt not active 1: interrupt active" group.long 0x3400++0x3 line.long 0x0 "GPIO_INT_EDGE_CLR_0,gpio edge sensitive interrupt clear. this bit is auto cleared. no need to clear it to 0 after program to 1." hexmask.long 0x0 0.--31. 1. "INT_EDGE_CLR,gpio edge sensitive interrupt clear. this bit is auto cleared. no need to clear it to 0 after program to 1. 0: not clear 1: clear" group.long 0x3600++0x3 line.long 0x0 "GPIO_INT_LEV_SYNC_0,gpio level sensitive sync enable" hexmask.long 0x0 0.--31. 1. "INT_LEV_SYNC,pio level sensitive sync enable 0: disable 1: enable" group.long 0x3800++0x3 line.long 0x0 "GPIO_INT_DEB_EN_0,gpio interrupt debounce enable." hexmask.long 0x0 0.--31. 1. "INT_DEB_EN,gpio interrupt debounce enable. 0: disable 1: enable" group.long 0x3A00++0x3 line.long 0x0 "GPIO_INT_CLK_SEL_0,gpio interrupt clock source select" hexmask.long 0x0 0.--31. 1. "INT_CLK_SEL,gpio interrupt clock source select 0: pclk 1: 32kHz" rgroup.long 0x3C00++0x3 line.long 0x0 "GPIO_INT_PCLK_ACTIVE_0,gpio pclk active status" hexmask.long 0x0 0.--31. 1. "PCLK_ACTIVE,gpio pclk active status 1: pclk acvive 0: pclk not active for each bit" tree.end repeat.end elif (CORENAME()=="CORTEXA55") repeat 5. (increment 1. 1.) (list ad:0x30000000 ad:0x30400000 ad:0x30410000 ad:0x30420000 ad:0x30430000) tree "GPIO$1" base $2 repeat 4. (list 0x0 0x1 0x2 0x3 )(list 0x0 0x10 0x20 0x30 ) group.long ($2)++0x3 line.long 0x0 "GPIO_CTRL_$1,gpio overall control and status register" rbitfld.long 0x0 14. "PCLK_ACTIVE,status of pclk: 1: pclk is active 0: pclk is inactive" "pclk is inactive,pclk is active" newline bitfld.long 0x0 13. "INT_CLK_SEL,selection of gpio interrupt clock 0: pclk 1: 32kHz" "pclk,?" bitfld.long 0x0 12. "INT_DEB_EN,control of gpio interrupt debounce. 0: disable 1: enable" "disable,enable" newline bitfld.long 0x0 11. "INT_LEV_SYNC,gpio level sensitive sync enable 0: disable 1: enable" "disable,enable" bitfld.long 0x0 10. "INT_EDGE_CLR,gpio edge sensitive interrupt clear. this bit is auto cleared. no need to clear it to 0 after program to 1. 0: not clear 1: clear" "not clear,clear" newline rbitfld.long 0x0 9. "INT_STATUS_UNMASK,gpio interrupt unmasked status 0: interrupt not active 1: interrupt active" "interrupt not active,interrupt active" rbitfld.long 0x0 8. "INT_STATUS,gpio interrupt status. 0: interrupt not active 1: interrupt active" "interrupt not active,interrupt active" newline bitfld.long 0x0 7. "INT_BOTH_EDGE,gpio interrupt both sensitive type 0: single edge sensitive 1: both edge sensitive" "single edge sensitive,both edge sensitive" bitfld.long 0x0 6. "INT_POL,gpio interrupt polarity. 0: low active or negedge active 1: high active or posedge active" "low active or negedge active,high active or posedge active" newline bitfld.long 0x0 5. "INT_TYPE,gpio interrupt type 0: Interrupt is level sensitive 1: Interrupt is edge sensitive" "Interrupt is level sensitive,Interrupt is edge sensitive" bitfld.long 0x0 4. "INT_MASK,gpio interrupt mask 0: interrupt not mask 1: interrupt mask" "interrupt not mask,interrupt mask" newline bitfld.long 0x0 3. "INT_EN,gpio interrupt enable 0: disable 1: enable" "disable,enable" bitfld.long 0x0 2. "DATA_OUT,gpio output data" "0,1" newline rbitfld.long 0x0 1. "DATA_IN,gpio input data" "0,1" bitfld.long 0x0 0. "DIR,gpio direction. 0: input mode 1: output mode" "input mode,output mode" repeat.end group.long 0x2000++0x3 line.long 0x0 "GPIO_DIR_0,gpio direction control for 32 gpio at once" hexmask.long 0x0 0.--31. 1. "DIR,gpio direction control for 32 gpio at once" rgroup.long 0x2200++0x3 line.long 0x0 "GPIO_DATA_IN_0,gpio data input" hexmask.long 0x0 0.--31. 1. "DATA_IN,gpio data input" group.long 0x2400++0x3 line.long 0x0 "GPIO_DATA_OUT_0,gpio data output" hexmask.long 0x0 0.--31. 1. "DATA_OUT,gpio data output" group.long 0x2600++0x3 line.long 0x0 "GPIO_INT_EN_0,gpio interrupt enable" hexmask.long 0x0 0.--31. 1. "INT_EN,gpio interrupt enable" group.long 0x2800++0x3 line.long 0x0 "GPIO_INT_MASK_0,gpio interrupt mask" hexmask.long 0x0 0.--31. 1. "INT_MASK,gpio interrupt mask" group.long 0x2A00++0x3 line.long 0x0 "GPIO_INT_TYPE_0,gpio interrupt type" hexmask.long 0x0 0.--31. 1. "INT_TYPE,0: Interrupt is level sensitive 1: Interrupt is edge sensitive" group.long 0x2C00++0x3 line.long 0x0 "GPIO_INT_POL_0,gpio interrupt polarity" hexmask.long 0x0 0.--31. 1. "INT_POL,gpio interrupt polarity. 0: low active or negedge active 1: high active or posedge active" group.long 0x2E00++0x3 line.long 0x0 "GPIO_INT_BOTH_EDGE_0,gpio interrupt both edge sensitive enable" hexmask.long 0x0 0.--31. 1. "INT_BOTH_EDGE,gpio interrupt both sensitive type 0: single edge sensitive 1: both edge sensitive" rgroup.long 0x3000++0x3 line.long 0x0 "GPIO_INT_STATUS_0,gpio interrupt status" hexmask.long 0x0 0.--31. 1. "INT_STATUS,gpio interrupt status. 0: interrupt not active 1: interrupt active" rgroup.long 0x3200++0x3 line.long 0x0 "GPIO_INT_STATUS_UNMASK_0,gpio interrupt unmasked status" hexmask.long 0x0 0.--31. 1. "INT_STATUS_UNMASK,gpio interrupt unmasked status 0: interrupt not active 1: interrupt active" group.long 0x3400++0x3 line.long 0x0 "GPIO_INT_EDGE_CLR_0,gpio edge sensitive interrupt clear. this bit is auto cleared. no need to clear it to 0 after program to 1." hexmask.long 0x0 0.--31. 1. "INT_EDGE_CLR,gpio edge sensitive interrupt clear. this bit is auto cleared. no need to clear it to 0 after program to 1. 0: not clear 1: clear" group.long 0x3600++0x3 line.long 0x0 "GPIO_INT_LEV_SYNC_0,gpio level sensitive sync enable" hexmask.long 0x0 0.--31. 1. "INT_LEV_SYNC,pio level sensitive sync enable 0: disable 1: enable" group.long 0x3800++0x3 line.long 0x0 "GPIO_INT_DEB_EN_0,gpio interrupt debounce enable." hexmask.long 0x0 0.--31. 1. "INT_DEB_EN,gpio interrupt debounce enable. 0: disable 1: enable" group.long 0x3A00++0x3 line.long 0x0 "GPIO_INT_CLK_SEL_0,gpio interrupt clock source select" hexmask.long 0x0 0.--31. 1. "INT_CLK_SEL,gpio interrupt clock source select 0: pclk 1: 32kHz" rgroup.long 0x3C00++0x3 line.long 0x0 "GPIO_INT_PCLK_ACTIVE_0,gpio pclk active status" hexmask.long 0x0 0.--31. 1. "PCLK_ACTIVE,gpio pclk active status 1: pclk acvive 0: pclk not active for each bit" tree.end repeat.end endif tree.end tree "GPU (GPU Controller)" sif (CORENAME()=="CORTEXR5F") tree "GPU1" base ad:0xF4C00000 group.long 0x0++0x7 line.long 0x0 "RGX_CR_CLK_CTRL_0,Core Module Clock Control Modes. Allows individual domain clocks to be forced off. forced on or operate under automatic pipeline activity based clock gating. This register is generally controlled by the GPU firmware and should be set to.." bitfld.long 0x0 30.--31. "Reserved_30,Reserved_30" "0,1,2,3" newline bitfld.long 0x0 28.--29. "TPU_MCU_DEMUX,TPU_MCU_DEMUX" "0,1,2,3" newline bitfld.long 0x0 26.--27. "MCU_L0,MCU_L0" "0,1,2,3" newline bitfld.long 0x0 24.--25. "TPU,TPU" "0,1,2,3" newline bitfld.long 0x0 22.--23. "Reserved_22,Reserved_22" "0,1,2,3" newline bitfld.long 0x0 20.--21. "USC,USC" "0,1,2,3" newline bitfld.long 0x0 18.--19. "Reserved_18,Reserved_18" "0,1,2,3" newline bitfld.long 0x0 16.--17. "SLC,SLC" "0,1,2,3" newline bitfld.long 0x0 14.--15. "UVS,UVS" "0,1,2,3" newline bitfld.long 0x0 12.--13. "PDS,PDS" "0,1,2,3" newline bitfld.long 0x0 10.--11. "VDM,VDM" "0,1,2,3" newline bitfld.long 0x0 8.--9. "PM,PM" "0,1,2,3" newline bitfld.long 0x0 6.--7. "GPP,GPP" "0,1,2,3" newline bitfld.long 0x0 4.--5. "TE,TE" "0,1,2,3" newline bitfld.long 0x0 2.--3. "TSP,TSP" "0,1,2,3" newline bitfld.long 0x0 0.--1. "ISP,ISP" "0,1,2,3" line.long 0x4 "RGX_CR_CLK_CTRL_1,Core Module Clock Control Modes. Allows individual domain clocks to be forced off. forced on or operate under automatic pipeline activity based clock gating. This register is generally controlled by the GPU firmware and should be set to.." hexmask.long.byte 0x4 28.--31. 1. "Reserved_60,Reserved_60" newline bitfld.long 0x4 26.--27. "FBC,FBC" "0,1,2,3" newline bitfld.long 0x4 24.--25. "FBDC,FBDC" "0,1,2,3" newline bitfld.long 0x4 22.--23. "FB_TLCACHE,FB_TLCACHE" "0,1,2,3" newline bitfld.long 0x4 20.--21. "USCS,USCS" "0,1,2,3" newline bitfld.long 0x4 18.--19. "PBE,PBE" "0,1,2,3" newline bitfld.long 0x4 16.--17. "MCU_L1,MCU_L1" "0,1,2,3" newline bitfld.long 0x4 14.--15. "CDM,CDM" "0,1,2,3" newline bitfld.long 0x4 12.--13. "SIDEKICK,SIDEKICK" "0,1,2,3" newline bitfld.long 0x4 10.--11. "BIF_SIDEKICK,BIF_SIDEKICK" "0,1,2,3" newline bitfld.long 0x4 8.--9. "BIF,BIF" "0,1,2,3" newline hexmask.long.byte 0x4 0.--7. 1. "Reserved_30,Reserved_30" rgroup.long 0x8++0x7 line.long 0x0 "RGX_CR_CLK_STATUS_0,Reports the current module clock status Clock gating state reflects the condition of the clock for each module" bitfld.long 0x0 30.--31. "Reserved_30,Reserved_30" "0,1,2,3" newline bitfld.long 0x0 29. "FBC,FBC" "0,1" newline bitfld.long 0x0 28. "FBDC,FBDC" "0,1" newline bitfld.long 0x0 27. "FB_TLCACHE,FB_TLCACHE" "0,1" newline bitfld.long 0x0 26. "USCS,USCS" "0,1" newline bitfld.long 0x0 25. "PBE,PBE" "0,1" newline bitfld.long 0x0 24. "MCU_L1,MCU_L1" "0,1" newline bitfld.long 0x0 23. "CDM,CDM" "0,1" newline bitfld.long 0x0 22. "SIDEKICK,SIDEKICK" "0,1" newline bitfld.long 0x0 21. "BIF_SIDEKICK,BIF_SIDEKICK" "0,1" newline bitfld.long 0x0 20. "BIF,BIF" "0,1" newline hexmask.long.byte 0x0 15.--19. 1. "Reserved_15,Reserved_15" newline bitfld.long 0x0 14. "TPU_MCU_DEMUX,TPU_MCU_DEMUX" "0,1" newline bitfld.long 0x0 13. "MCU_L0,MCU_L0" "0,1" newline bitfld.long 0x0 12. "TPU,TPU" "0,1" newline bitfld.long 0x0 11. "Reserved_11,Reserved_11" "0,1" newline bitfld.long 0x0 10. "USC,USC" "0,1" newline bitfld.long 0x0 9. "Reserved_9,Reserved_9" "0,1" newline bitfld.long 0x0 8. "SLC,SLC" "0,1" newline bitfld.long 0x0 7. "UVS,UVS" "0,1" newline bitfld.long 0x0 6. "PDS,PDS" "0,1" newline bitfld.long 0x0 5. "VDM,VDM" "0,1" newline bitfld.long 0x0 4. "PM,PM" "0,1" newline bitfld.long 0x0 3. "GPP,GPP" "0,1" newline bitfld.long 0x0 2. "TE,TE" "0,1" newline bitfld.long 0x0 1. "TSP,TSP" "0,1" newline bitfld.long 0x0 0. "ISP,ISP" "0,1" line.long 0x4 "RGX_CR_CLK_STATUS_1,Reports the current module clock status Clock gating state reflects the condition of the clock for each module" hexmask.long 0x4 1.--31. 1. "Reserved_33,Reserved_33" newline bitfld.long 0x4 0. "MCU_FBTC,MCU_FBTC" "0,1" rgroup.long 0x18++0x7 line.long 0x0 "RGX_CR_PRODUCT_ID_0,Reports the product ID Product ID Register" hexmask.long.word 0x0 16.--31. 1. "IMG_PRODUCT_ID,IMG Product ID" newline hexmask.long.word 0x0 0.--15. 1. "Reserved_0,Reserved_0" line.long 0x4 "RGX_CR_PRODUCT_ID_1,Reports the product ID Product ID Register" hexmask.long 0x4 0.--31. 1. "Reserved_32,Reserved_32" repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) rgroup.long ($2+0x20)++0x3 line.long 0x0 "RGX_CR_CORE_ID_$1,Reports the product ID Core ID Register" hexmask.long.word 0x0 16.--31. 1. "NUMBER_OF_SCALABLE_UNITS,N - Number of scalable Units" newline hexmask.long.word 0x0 0.--15. 1. "CONFIG_ID,C - Config ID" repeat.end repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) rgroup.long ($2+0x28)++0x3 line.long 0x0 "RGX_CR_CORE_IP_INTEGRATOR_ID_$1,Reports the product ID Core IP Integrator ID Register" hexmask.long 0x0 0.--31. 1. "VALUE,IP company ID/Designer" repeat.end repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) rgroup.long ($2+0x30)++0x3 line.long 0x0 "RGX_CR_CORE_IP_CHANGELIST_$1,Reports the version control ID Core IP Changelist Register" hexmask.long 0x0 0.--31. 1. "VALUE,Version control ID" repeat.end group.long 0x38++0x7 line.long 0x0 "RGX_CR_POWER_EVENT_0,Allows the firmware to request a power-up or power-down operation to an external (to Rogue) power-management controller When the power event operation is accepted. the firmware will either receive an.." hexmask.long.byte 0x0 24.--31. 1. "Reserved_24,Reserved_24" newline hexmask.long.word 0x0 8.--23. 1. "DOMAIN,sets which power island is enabled for the current power event request; bit0:jones bit1-8:dusts bit9-12:blackpearls" newline hexmask.long.byte 0x0 2.--7. 1. "Reserved_2,Reserved_2" newline bitfld.long 0x0 1. "REQ,Set when a power event operation is requested" "0,1" newline bitfld.long 0x0 0. "TYPE,The requested power event operation" "0,1" line.long 0x4 "RGX_CR_POWER_EVENT_1,Allows the firmware to request a power-up or power-down operation to an external (to Rogue) power-management controller When the power event operation is accepted. the firmware will either receive an.." hexmask.long 0x4 0.--31. 1. "Reserved_24,Reserved_24" group.long 0x50++0x7 line.long 0x0 "RGX_CR_DUSTS_ENABLE_0,Controls how many Dual Unified Shading and Texturing Units (DUSTs) are enabled. Each DUST Contain 2 USCs and a TPU module. (Available on 2. X.X.X cores and above). Only applicable in cores with a B.V.N.C > 2.0.0.0 Controls how many.." hexmask.long.tbyte 0x0 8.--31. 1. "Reserved_8,Reserved_8" newline hexmask.long.byte 0x0 0.--7. 1. "ENABLE,Dusts enabled" line.long 0x4 "RGX_CR_DUSTS_ENABLE_1,Controls how many Dual Unified Shading and Texturing Units (DUSTs) are enabled. Each DUST Contain 2 USCs and a TPU module. (Available on 2. X.X.X cores and above). Only applicable in cores with a B.V.N.C > 2.0.0.0 Controls how many.." hexmask.long 0x4 0.--31. 1. "Reserved_8,Reserved_8" rgroup.long 0x58++0x7 line.long 0x0 "RGX_CR_DUSTS_FUSE_0,Indicates how many of the available DUST modules are enabled on the Silicon. (Available on 2.X.X.X cores and above). Shows the raw value of dusts_enable port." hexmask.long.tbyte 0x0 8.--31. 1. "Reserved_8,Reserved_8" newline hexmask.long.byte 0x0 0.--7. 1. "ENABLE,Dusts enabled" line.long 0x4 "RGX_CR_DUSTS_FUSE_1,Indicates how many of the available DUST modules are enabled on the Silicon. (Available on 2.X.X.X cores and above). Shows the raw value of dusts_enable port." hexmask.long 0x4 0.--31. 1. "Reserved_8,Reserved_8" group.long 0x80++0x7 line.long 0x0 "RGX_CR_CLK_XTPLUS_CTRL_0,Core Module Clock Control Modes. Allows individual domain clocks to be forced off. forced on or operate under automatic pipeline activity based clock gating. This register is generally controlled by the GPU firmware and should be.." hexmask.long 0x0 0.--31. 1. "Reserved_0,Reserved_0" line.long 0x4 "RGX_CR_CLK_XTPLUS_CTRL_1,Core Module Clock Control Modes. Allows individual domain clocks to be forced off. forced on or operate under automatic pipeline activity based clock gating. This register is generally controlled by the GPU firmware and should be.." hexmask.long 0x4 6.--31. 1. "Reserved_38,Reserved_38" newline bitfld.long 0x4 4.--5. "TDM,TDM" "0,1,2,3" newline bitfld.long 0x4 2.--3. "ASTC,ASTC" "0,1,2,3" newline bitfld.long 0x4 0.--1. "Reserved_0,Reserved_0" "0,1,2,3" rgroup.long 0x88++0x7 line.long 0x0 "RGX_CR_CLK_XTPLUS_STATUS_0,Reports the current module clock status Clock gating state reflects the condition of the clock for each module" hexmask.long.tbyte 0x0 11.--31. 1. "Reserved_11,Reserved_11" newline bitfld.long 0x0 10. "TDM,TDM" "0,1" newline bitfld.long 0x0 9. "IPF,IPF" "0,1" newline bitfld.long 0x0 8. "COMPUTE,COMPUTE" "0,1" newline bitfld.long 0x0 7. "ASTC,ASTC" "0,1" newline bitfld.long 0x0 6. "PIXEL,PIXEL" "0,1" newline bitfld.long 0x0 5. "VERTEX,VERTEX" "0,1" newline bitfld.long 0x0 4. "Reserved_4,Reserved_4" "0,1" newline bitfld.long 0x0 3. "PDS_SHARED,PDS_SHARED" "0,1" newline bitfld.long 0x0 2. "BIF_BLACKPEARL,BIF_BLACKPEARL" "0,1" newline bitfld.long 0x0 1. "USC_SHARED,USC_SHARED" "0,1" newline bitfld.long 0x0 0. "GEOMETRY,GEOMETRY" "0,1" line.long 0x4 "RGX_CR_CLK_XTPLUS_STATUS_1,Reports the current module clock status Clock gating state reflects the condition of the clock for each module" hexmask.long 0x4 0.--31. 1. "Reserved_11,Reserved_11" repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) rgroup.long ($2+0xE0)++0x3 line.long 0x0 "RGX_CR_SOC_TIMER_GRAY_$1,This register contains the value of a 64-bit external gray coded timer. (Available on 2.X.X.X cores and above)." hexmask.long 0x0 0.--31. 1. "VALUE,VALUE" repeat.end repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) rgroup.long ($2+0xE8)++0x3 line.long 0x0 "RGX_CR_SOC_TIMER_BINARY_$1,This register contains the value of a 64-bit external binary coded timer." hexmask.long 0x0 0.--31. 1. "VALUE,VALUE" repeat.end group.long 0x100++0xF line.long 0x0 "RGX_CR_SOFT_RESET_0,Core soft reset control register. Write a '1' to reset and a '0' to clear See the soft reset section in the TRM to understand how to use the soft reset register." bitfld.long 0x0 31. "RASCAL_CORE,Note that the RASL_CORE bit affects logic related to the reading and writing of registers. This soft reset should therefore be used with caution. Upon power down events it is necessary to reset every register so this bit should be used but.." "0,1" newline bitfld.long 0x0 30. "DUST_B_CORE,DUST_B_CORE" "0,1" newline bitfld.long 0x0 29. "DUST_A_CORE,DUST_A_CORE" "0,1" newline bitfld.long 0x0 28. "FB_TLCACHE,FB_TLCACHE" "0,1" newline bitfld.long 0x0 27. "SLC,SLC" "0,1" newline bitfld.long 0x0 26. "Reserved_26,Reserved_26" "0,1" newline bitfld.long 0x0 25. "UVS,UVS" "0,1" newline bitfld.long 0x0 24. "TE,TE" "0,1" newline bitfld.long 0x0 23. "GPP,GPP" "0,1" newline bitfld.long 0x0 22. "FBDC,FBDC" "0,1" newline bitfld.long 0x0 21. "FBC,FBC" "0,1" newline bitfld.long 0x0 20. "PM,PM" "0,1" newline bitfld.long 0x0 19. "PBE,PBE" "0,1" newline bitfld.long 0x0 18. "USC_SHARED,USC_SHARED" "0,1" newline bitfld.long 0x0 17. "MCU_L1,MCU_L1" "0,1" newline bitfld.long 0x0 16. "BIF,Bifpmcache BIF" "0,1" newline bitfld.long 0x0 15. "CDM,CDM" "0,1" newline bitfld.long 0x0 14. "VDM,VDM" "0,1" newline bitfld.long 0x0 13. "Reserved_13,Reserved_13" "0,1" newline bitfld.long 0x0 12. "PDS,PDS" "0,1" newline bitfld.long 0x0 11. "ISP,ISP" "0,1" newline bitfld.long 0x0 10. "TSP,TSP" "0,1" newline hexmask.long.byte 0x0 5.--9. 1. "Reserved_5,Reserved_5" newline bitfld.long 0x0 4. "TPU_MCU_DEMUX,TPU_MCU_DEMUX" "0,1" newline bitfld.long 0x0 3. "MCU_L0,MCU_L0" "0,1" newline bitfld.long 0x0 2. "TPU,TPU" "0,1" newline bitfld.long 0x0 1. "Reserved_1,Reserved_1" "0,1" newline bitfld.long 0x0 0. "USC,USC" "0,1" line.long 0x4 "RGX_CR_SOFT_RESET_1,Core soft reset control register. Write a '1' to reset and a '0' to clear See the soft reset section in the TRM to understand how to use the soft reset register." bitfld.long 0x4 29.--31. "Reserved_61,Reserved_61" "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 28. "JONES_CORE,JONES_CORE" "0,1" newline bitfld.long 0x4 27. "TILING_CORE,TILING_CORE" "0,1" newline bitfld.long 0x4 26. "TE3,TE3" "0,1" newline bitfld.long 0x4 25. "VCE,VCE" "0,1" newline bitfld.long 0x4 24. "VBS,VBS" "0,1" newline hexmask.long.byte 0x4 20.--23. 1. "Reserved_52,Reserved_52" newline bitfld.long 0x4 19. "FB_CDC,FB_CDC" "0,1" newline bitfld.long 0x4 17.--18. "Reserved_49,Reserved_49" "0,1,2,3" newline bitfld.long 0x4 16. "MCU_FBTC,MCU_FBTC" "0,1" newline hexmask.long.word 0x4 3.--15. 1. "Reserved_35,Reserved_35" newline bitfld.long 0x4 2. "MMU,MMU" "0,1" newline bitfld.long 0x4 1. "Reserved_33,Reserved_33" "0,1" newline bitfld.long 0x4 0. "GARTEN,Includes MTS and META or MIPS" "0,1" line.long 0x8 "RGX_CR_SOFT_RESET2_0,Core soft reset control register. Write a '1' to reset and a '0' to clear See the soft reset section in the TRM to understand how to use the soft reset register." hexmask.long.tbyte 0x8 12.--31. 1. "Reserved_12,Reserved_12" newline bitfld.long 0x8 11. "TDM,TDM" "0,1" newline bitfld.long 0x8 10. "ASTC,ASTC" "0,1" newline bitfld.long 0x8 9. "BLACKPEARL,BLACKPEARL" "0,1" newline bitfld.long 0x8 8. "Reserved_8,Reserved_8" "0,1" newline bitfld.long 0x8 7. "IPF,IPF" "0,1" newline bitfld.long 0x8 6. "GEOMETRY,GEOMETRY" "0,1" newline bitfld.long 0x8 5. "USC_SHARED,USC_SHARED" "0,1" newline bitfld.long 0x8 4. "PDS_SHARED,PDS_SHARED" "0,1" newline bitfld.long 0x8 3. "BIF_BLACKPEARL,BIF_BLACKPEARL" "0,1" newline bitfld.long 0x8 2. "PIXEL,PIXEL" "0,1" newline bitfld.long 0x8 1. "Reserved_1,Reserved_1" "0,1" newline bitfld.long 0x8 0. "VERTEX,VERTEX" "0,1" line.long 0xC "RGX_CR_SOFT_RESET2_1,Core soft reset control register. Write a '1' to reset and a '0' to clear See the soft reset section in the TRM to understand how to use the soft reset register." hexmask.long 0xC 0.--31. 1. "Reserved_12,Reserved_12" group.long 0x120++0x17 line.long 0x0 "RGX_CR_CONTEXT_SWITCH_ENABLE_0,The use of the this register has been deprecated." hexmask.long 0x0 4.--31. 1. "Reserved_4,Reserved_4" newline bitfld.long 0x0 3. "SOFT_RESET,SOFT_RESET" "0,1" newline bitfld.long 0x0 2. "IPF,IPF" "0,1" newline bitfld.long 0x0 1. "VDM,VDM" "0,1" newline bitfld.long 0x0 0. "CDM,CDM" "0,1" line.long 0x4 "RGX_CR_CONTEXT_SWITCH_ENABLE_1,The use of the this register has been deprecated." hexmask.long 0x4 0.--31. 1. "Reserved_4,Reserved_4" line.long 0x8 "RGX_CR_EVENT_ENABLE_0,This register is used to enable GPU interrupts directly to the host Writing a '1' to a bit field enables the relevant event This register should only be programmed when the META firmware is not used If the META firmware is used. the.." bitfld.long 0x8 31. "TDM_FENCE_FINISHED,Indicates a 2D fence has been processed" "0,1" newline bitfld.long 0x8 30. "TDM_BUFFER_STALL,The TDM has exhausted the current 2D circular buffer (read pointer = write_pointer)" "0,1" newline hexmask.long.word 0x8 19.--29. 1. "Reserved_19,Reserved_19" newline bitfld.long 0x8 18. "TDM_CONTEXT_STORE_FINISHED,The TDM has completed the requested context store operation." "0,1" newline bitfld.long 0x8 16.--17. "Reserved_16,Reserved_16" "0,1,2,3" newline bitfld.long 0x8 15. "USC_TRIGGER,One or more USC has executed a nop.trigger instruction" "0,1" newline bitfld.long 0x8 14. "ZLS_FINISHED,ZLS has finished all tiles in a Render" "0,1" newline bitfld.long 0x8 13. "GPIO_ACK,General Purpose ouput acknowledgement" "0,1" newline bitfld.long 0x8 12. "GPIO_REQ,General Purpose input request" "0,1" newline bitfld.long 0x8 11. "POWER_ABORT,The requested power operation has been denied." "0,1" newline bitfld.long 0x8 10. "POWER_COMPLETE,The requested power operation has completed" "0,1" newline bitfld.long 0x8 9. "MMU_PAGE_FAULT,An MMU page fault has occurred" "0,1" newline bitfld.long 0x8 8. "PM_3D_MEM_FREE,PM memory allocation completed for the current render" "0,1" newline bitfld.long 0x8 7. "PM_OUT_OF_MEMORY,PM memory allocation failed for a macro-tile" "0,1" newline bitfld.long 0x8 6. "TA_TERMINATE,The TE has aborted a macro tile after a failted PM allocation request" "0,1" newline bitfld.long 0x8 5. "TA_FINISHED,The TA phase has completed" "0,1" newline bitfld.long 0x8 4. "ISP_END_MACROTILE,ISP End-of-Macrotile" "0,1" newline bitfld.long 0x8 3. "PIXELBE_END_RENDER,The 3D phase has completed" "0,1" newline bitfld.long 0x8 2. "COMPUTE_FINISHED,The compute phase has completed" "0,1" newline bitfld.long 0x8 1. "KERNEL_FINISHED,A compute kernel has completed and updated the associated event object in external memory" "0,1" newline bitfld.long 0x8 0. "Reserved_0,Reserved_0" "0,1" line.long 0xC "RGX_CR_EVENT_ENABLE_1,This register is used to enable GPU interrupts directly to the host Writing a '1' to a bit field enables the relevant event This register should only be programmed when the META firmware is not used If the META firmware is used. the.." hexmask.long 0xC 0.--31. 1. "Reserved_32,Reserved_32" line.long 0x10 "RGX_CR_EVENT_STATUS_0,The event status register indicate the source of an interrupt generated by PowerVR RGX These events only schedule an interrupt context thread to run on META when the appropriate enables are set in RGX_CR_DMn_INTERRUPT_ENABLE" bitfld.long 0x10 31. "TDM_FENCE_FINISHED,Indicates a 2D fence has been processed" "0,1" newline bitfld.long 0x10 30. "TDM_BUFFER_STALL,The TDM has exhausted the current 2D circular buffer (read pointer = write_pointer)" "0,1" newline hexmask.long.word 0x10 19.--29. 1. "Reserved_19,Reserved_19" newline bitfld.long 0x10 18. "TDM_CONTEXT_STORE_FINISHED,The TDM has completed the requested context store operation." "0,1" newline bitfld.long 0x10 16.--17. "Reserved_16,Reserved_16" "0,1,2,3" newline bitfld.long 0x10 15. "USC_TRIGGER,One or more USC has executed a nop.trigger instruction" "0,1" newline bitfld.long 0x10 14. "ZLS_FINISHED,ZLS has finished all tiles in a Render" "0,1" newline bitfld.long 0x10 13. "GPIO_ACK,General Purpose ouput acknowledgement" "0,1" newline bitfld.long 0x10 12. "GPIO_REQ,General Purpose input request" "0,1" newline bitfld.long 0x10 11. "POWER_ABORT,The requested power operation has been denied." "0,1" newline bitfld.long 0x10 10. "POWER_COMPLETE,The requested power operation has completed" "0,1" newline bitfld.long 0x10 9. "MMU_PAGE_FAULT,An MMU page fault has occurred" "0,1" newline bitfld.long 0x10 8. "PM_3D_MEM_FREE,PM memory allocation completed for the current render" "0,1" newline bitfld.long 0x10 7. "PM_OUT_OF_MEMORY,PM memory allocation failed for a macro-tile" "0,1" newline bitfld.long 0x10 6. "TA_TERMINATE,The TE has aborted a macro tile after a failted PM allocation request" "0,1" newline bitfld.long 0x10 5. "TA_FINISHED,The TA phase has completed" "0,1" newline bitfld.long 0x10 4. "ISP_END_MACROTILE,ISP End-of-Macrotile" "0,1" newline bitfld.long 0x10 3. "PIXELBE_END_RENDER,The 3D phase has completed" "0,1" newline bitfld.long 0x10 2. "COMPUTE_FINISHED,The compute phase has completed" "0,1" newline bitfld.long 0x10 1. "KERNEL_FINISHED,A compute kernel has completed and updated the associated event object in external memory" "0,1" newline bitfld.long 0x10 0. "Reserved_0,Reserved_0" "0,1" line.long 0x14 "RGX_CR_EVENT_STATUS_1,The event status register indicate the source of an interrupt generated by PowerVR RGX These events only schedule an interrupt context thread to run on META when the appropriate enables are set in RGX_CR_DMn_INTERRUPT_ENABLE" hexmask.long 0x14 0.--31. 1. "Reserved_32,Reserved_32" wgroup.long 0x138++0x7 line.long 0x0 "RGX_CR_EVENT_CLEAR_0,This register is used to clear event interrupts. Writing a '1' to a bit field clears the relevant event." bitfld.long 0x0 31. "TDM_FENCE_FINISHED,Indicates a 2D fence has been processed" "0,1" newline bitfld.long 0x0 30. "TDM_BUFFER_STALL,The TDM has exhausted the current 2D circular buffer (read pointer = write_pointer)" "0,1" newline hexmask.long.word 0x0 19.--29. 1. "Reserved_19,Reserved_19" newline bitfld.long 0x0 18. "TDM_CONTEXT_STORE_FINISHED,The TDM has completed the requested context store operation." "0,1" newline bitfld.long 0x0 16.--17. "Reserved_16,Reserved_16" "0,1,2,3" newline bitfld.long 0x0 15. "USC_TRIGGER,One or more USC has executed a nop.trigger instruction" "0,1" newline bitfld.long 0x0 14. "ZLS_FINISHED,ZLS has finished all tiles in a Render" "0,1" newline bitfld.long 0x0 13. "GPIO_ACK,General Purpose ouput acknowledgement" "0,1" newline bitfld.long 0x0 12. "GPIO_REQ,General Purpose input request" "0,1" newline bitfld.long 0x0 11. "POWER_ABORT,The requested power operation has been denied." "0,1" newline bitfld.long 0x0 10. "POWER_COMPLETE,The requested power operation has completed" "0,1" newline bitfld.long 0x0 9. "MMU_PAGE_FAULT,An MMU page fault has occurred" "0,1" newline bitfld.long 0x0 8. "PM_3D_MEM_FREE,PM memory allocation completed for the current render" "0,1" newline bitfld.long 0x0 7. "PM_OUT_OF_MEMORY,PM memory allocation failed for a macro-tile" "0,1" newline bitfld.long 0x0 6. "TA_TERMINATE,The TE has aborted a macro tile after a failted PM allocation request" "0,1" newline bitfld.long 0x0 5. "TA_FINISHED,The TA phase has completed" "0,1" newline bitfld.long 0x0 4. "ISP_END_MACROTILE,ISP End-of-Macrotile" "0,1" newline bitfld.long 0x0 3. "PIXELBE_END_RENDER,The 3D phase has completed" "0,1" newline bitfld.long 0x0 2. "COMPUTE_FINISHED,The compute phase has completed" "0,1" newline bitfld.long 0x0 1. "KERNEL_FINISHED,A compute kernel has completed and updated the associated event object in external memory" "0,1" newline bitfld.long 0x0 0. "Reserved_0,Reserved_0" "0,1" line.long 0x4 "RGX_CR_EVENT_CLEAR_1,This register is used to clear event interrupts. Writing a '1' to a bit field clears the relevant event." hexmask.long 0x4 0.--31. 1. "Reserved_32,Reserved_32" group.long 0x140++0xF line.long 0x0 "RGX_CR_GPIO_OUTPUT_DATA_0,General Purpose Input/Output interface for implementing communication protocol between HW external to Rogue and the firmware These registers are connected to top-level pins These registers are driven by the firmware. When the.." hexmask.long.tbyte 0x0 8.--31. 1. "Reserved_8,Reserved_8" newline hexmask.long.byte 0x0 0.--7. 1. "DATA,The data the firmware wants to transfer" line.long 0x4 "RGX_CR_GPIO_OUTPUT_DATA_1,General Purpose Input/Output interface for implementing communication protocol between HW external to Rogue and the firmware These registers are connected to top-level pins These registers are driven by the firmware. When the.." hexmask.long 0x4 0.--31. 1. "Reserved_8,Reserved_8" line.long 0x8 "RGX_CR_GPIO_OUTPUT_REQ_0,General Purpose Input/Output interface for implementing communication protocol between HW external to Rogue and the firmware This register is connected to a top-level pin This register is driven by the firmware. When the request.." hexmask.long 0x8 1.--31. 1. "Reserved_1,Reserved_1" newline bitfld.long 0x8 0. "REQ,Set when the firmware wants to communicate with a external HW" "0,1" line.long 0xC "RGX_CR_GPIO_OUTPUT_REQ_1,General Purpose Input/Output interface for implementing communication protocol between HW external to Rogue and the firmware This register is connected to a top-level pin This register is driven by the firmware. When the request.." hexmask.long 0xC 0.--31. 1. "Reserved_1,Reserved_1" rgroup.long 0x150++0x7 line.long 0x0 "RGX_CR_GPIO_INPUT_DATA_0,General Purpose Input/Output interface for implementing communication protocol between HW external to Rogue and the firmware This register is connected to top-level pins This register is driven by HW external to rogue before.." hexmask.long.tbyte 0x0 8.--31. 1. "Reserved_8,Reserved_8" newline hexmask.long.byte 0x0 0.--7. 1. "DATA,The incoming data from HW external to Rogue" line.long 0x4 "RGX_CR_GPIO_INPUT_DATA_1,General Purpose Input/Output interface for implementing communication protocol between HW external to Rogue and the firmware This register is connected to top-level pins This register is driven by HW external to rogue before.." hexmask.long 0x4 0.--31. 1. "Reserved_8,Reserved_8" group.long 0x158++0x7 line.long 0x0 "RGX_CR_GPIO_INPUT_ACK_0,General Purpose Input/Output interface for implementing communication protocol between HW external to Rogue and the firmware This register is connected to a top-level pin This register is driven by external HW in response to an.." hexmask.long 0x0 1.--31. 1. "Reserved_1,Reserved_1" newline bitfld.long 0x0 0. "ACK,Set by the firmware when it has acknowledged the incoming request" "0,1" line.long 0x4 "RGX_CR_GPIO_INPUT_ACK_1,General Purpose Input/Output interface for implementing communication protocol between HW external to Rogue and the firmware This register is connected to a top-level pin This register is driven by external HW in response to an.." hexmask.long 0x4 0.--31. 1. "Reserved_1,Reserved_1" rgroup.long 0x160++0x7 line.long 0x0 "RGX_CR_TIMER_0,This register contains the value of a 48-bit internal timer. The timer runs continuously. and wraps at the top end. It counts 256 cycles at the core clock frequency. This means that at 100 MHz: 1 count value = 1/100MHz = 256 * 10 * 10^-9.." hexmask.long 0x0 0.--31. 1. "VALUE,VALUE" line.long 0x4 "RGX_CR_TIMER_1,This register contains the value of a 48-bit internal timer. The timer runs continuously. and wraps at the top end. It counts 256 cycles at the core clock frequency. This means that at 100 MHz: 1 count value = 1/100MHz = 256 * 10 * 10^-9.." bitfld.long 0x4 31. "BIT31,BIT31" "0,1" newline hexmask.long.word 0x4 16.--30. 1. "Reserved_48,Reserved_48" newline hexmask.long.word 0x4 0.--15. 1. "VALUE,VALUE" group.long 0x168++0x7 line.long 0x0 "RGX_CR_AXI_EXACCESS_0,AXI exclusive access enable register" hexmask.long 0x0 1.--31. 1. "Reserved_1,Reserved_1" newline bitfld.long 0x0 0. "SOCIF_ENABLE,enable the exclusive access logic in the socif img_axi2img. vhd module" "0,1" line.long 0x4 "RGX_CR_AXI_EXACCESS_1,AXI exclusive access enable register" hexmask.long 0x4 0.--31. 1. "Reserved_1,Reserved_1" group.long 0x190++0x17 line.long 0x0 "RGX_CR_PM_TASK_MLIST_LOAD_0,This register is part of the parameter management. which controls the allocation and de-allocation of memory for the 3D display list (parameters). The MLIST is the list of Pages which have been allocated to thew MMU. to map.." hexmask.long 0x0 1.--31. 1. "Reserved_1,Reserved_1" newline bitfld.long 0x0 0. "PENDING,A write to this register will cause the MLIST pointer to be loaded from either PM_MLIST0_START_OF or PM_MLIST1_START_OF depending upon the Context ID contained in PM_CONTEXT_ID_MLS_LS. A read to this register return '1' until this operation has.." "0,1" line.long 0x4 "RGX_CR_PM_TASK_MLIST_LOAD_1,This register is part of the parameter management. which controls the allocation and de-allocation of memory for the 3D display list (parameters). The MLIST is the list of Pages which have been allocated to thew MMU. to map.." hexmask.long 0x4 0.--31. 1. "Reserved_1,Reserved_1" line.long 0x8 "RGX_CR_PM_TASK_MLIST_CLEAR_0,This register is part of the parameter management. which controls the allocation and de-allocation of memory for the 3D display list (parameters). The MLIST is the list of Pages which have been allocated to thew MMU. to map.." hexmask.long 0x8 1.--31. 1. "Reserved_1,Reserved_1" newline bitfld.long 0x8 0. "PENDING,A write to this register will cause the MLIST pointer to be reset to 0. A read to this register return '1' until this operation has completed." "0,1" line.long 0xC "RGX_CR_PM_TASK_MLIST_CLEAR_1,This register is part of the parameter management. which controls the allocation and de-allocation of memory for the 3D display list (parameters). The MLIST is the list of Pages which have been allocated to thew MMU. to map.." hexmask.long 0xC 0.--31. 1. "Reserved_1,Reserved_1" line.long 0x10 "RGX_CR_PM_TA_MAX_RENDER_TARGET_0,This register is deprecated and has no function." hexmask.long.tbyte 0x10 11.--31. 1. "Reserved_11,Reserved_11" newline hexmask.long.word 0x10 0.--10. 1. "ID,If used the software should program this with the maximum render target array index used within the Scene" line.long 0x14 "RGX_CR_PM_TA_MAX_RENDER_TARGET_1,This register is deprecated and has no function." hexmask.long 0x14 0.--31. 1. "Reserved_11,Reserved_11" rgroup.long 0x1A8++0x7 line.long 0x0 "RGX_CR_PM_MTILE_ARRAY_REORDER_VALID_STATUS_0,This register is deprecated and has no function." hexmask.long 0x0 1.--31. 1. "Reserved_1,Reserved_1" newline bitfld.long 0x0 0. "OP,OP" "0,1" line.long 0x4 "RGX_CR_PM_MTILE_ARRAY_REORDER_VALID_STATUS_1,This register is deprecated and has no function." hexmask.long 0x4 0.--31. 1. "Reserved_1,Reserved_1" group.long 0x1B0++0x1F line.long 0x0 "RGX_CR_PM_EMPTY_PAGE_FAST_FREEING_0,This register is part of the parameter management. which controls the allocation and de-allocation of memory for the 3D display list (parameters). This register enables an optimisation which causes pages which have.." hexmask.long 0x0 1.--31. 1. "Reserved_1,Reserved_1" newline bitfld.long 0x0 0. "ID,When set enable freeing of unused pages during TA phase" "0,1" line.long 0x4 "RGX_CR_PM_EMPTY_PAGE_FAST_FREEING_1,This register is part of the parameter management. which controls the allocation and de-allocation of memory for the 3D display list (parameters). This register enables an optimisation which causes pages which have.." hexmask.long 0x4 0.--31. 1. "Reserved_1,Reserved_1" line.long 0x8 "RGX_CR_PM_MMU_REMAP_PENDING_0,This register is part of the parameter management. which controls the allocation and de-allocation of memory for the 3D display list (parameters). This register starts the process of remapping the remaining physical pages at.." hexmask.long 0x8 1.--31. 1. "Reserved_1,Reserved_1" newline bitfld.long 0x8 0. "OP,Pending status register corresponding to the MMU remapping operation it will become '1' when written and deassert when the operation complete." "0,1" line.long 0xC "RGX_CR_PM_MMU_REMAP_PENDING_1,This register is part of the parameter management. which controls the allocation and de-allocation of memory for the 3D display list (parameters). This register starts the process of remapping the remaining physical pages at.." hexmask.long 0xC 0.--31. 1. "Reserved_1,Reserved_1" line.long 0x10 "RGX_CR_PM_PBE_FORCE_FREEING_0,This register is part of the parameter management. which controls the allocation and de-allocation of memory for the 3D display list (parameters). Normally freeing of memory is associated with macrotiles (a portion of the.." hexmask.long 0x10 1.--31. 1. "Reserved_1,Reserved_1" newline bitfld.long 0x10 0. "ENABLE,When this bit is set PM will free all the 3D context Memory when a genuine pixelbe end of render is received." "0,1" line.long 0x14 "RGX_CR_PM_PBE_FORCE_FREEING_1,This register is part of the parameter management. which controls the allocation and de-allocation of memory for the 3D display list (parameters). Normally freeing of memory is associated with macrotiles (a portion of the.." hexmask.long 0x14 0.--31. 1. "Reserved_1,Reserved_1" line.long 0x18 "RGX_CR_PM_PDS_STARTOF_MTILEFREE_0,RGX_CR_PM_PDS_STARTOF_MTILEFREE_0" hexmask.long.word 0x18 17.--31. 1. "Reserved_17,Reserved_17" newline hexmask.long.tbyte 0x18 0.--16. 1. "OP,This startof register indicates the macrotile number of the PDSs current macrotile free request needs to be programmed by FW on a render start" line.long 0x1C "RGX_CR_PM_PDS_STARTOF_MTILEFREE_1,RGX_CR_PM_PDS_STARTOF_MTILEFREE_1" hexmask.long 0x1C 0.--31. 1. "Reserved_17,Reserved_17" group.long 0x200++0x1F line.long 0x0 "RGX_CR_PM_TASK_3D_FREE_LOAD_0,RGX_CR_PM_TASK_3D_FREE_LOAD_0" hexmask.long 0x0 1.--31. 1. "Reserved_1,Reserved_1" newline bitfld.long 0x0 0. "PENDING,A write into this register will cause the 3D free list context to be loaded from the relevant configuration registers" "0,1" line.long 0x4 "RGX_CR_PM_TASK_3D_FREE_LOAD_1,RGX_CR_PM_TASK_3D_FREE_LOAD_1" hexmask.long 0x4 0.--31. 1. "Reserved_1,Reserved_1" line.long 0x8 "RGX_CR_PM_TASK_TA_FREE_LOAD_0,RGX_CR_PM_TASK_TA_FREE_LOAD_0" hexmask.long 0x8 1.--31. 1. "Reserved_1,Reserved_1" newline bitfld.long 0x8 0. "PENDING,A write into this register will cause the TA free list context to be loaded from the relevant configuration registers" "0,1" line.long 0xC "RGX_CR_PM_TASK_TA_FREE_LOAD_1,RGX_CR_PM_TASK_TA_FREE_LOAD_1" hexmask.long 0xC 0.--31. 1. "Reserved_1,Reserved_1" line.long 0x10 "RGX_CR_PM_TA_FSTACK_BASE_0,Effective on load TA context. this register defines the base address of the free list stack being referenced during TA processing." hexmask.long 0x10 4.--31. 1. "ADDR,1TB Addressable 128 bits aligned Base Address for TA context page tables in the DPM module" newline hexmask.long.byte 0x10 0.--3. 1. "Reserved_0,Reserved_0" line.long 0x14 "RGX_CR_PM_TA_FSTACK_BASE_1,Effective on load TA context. this register defines the base address of the free list stack being referenced during TA processing." hexmask.long.tbyte 0x14 8.--31. 1. "Reserved_40,Reserved_40" newline hexmask.long.byte 0x14 0.--7. 1. "ADDR,1TB Addressable 128 bits aligned Base Address for TA context page tables in the DPM module" line.long 0x18 "RGX_CR_PM_3D_FSTACK_BASE_0,Effective on load 3D context. this register defines the base address of the free list table being referenced in the process of de-allocating pages during a 3D render." hexmask.long 0x18 4.--31. 1. "ADDR,1TB Addressable 128 bits aligned Base Address for 3D context page tables in the DPM module" newline hexmask.long.byte 0x18 0.--3. 1. "Reserved_0,Reserved_0" line.long 0x1C "RGX_CR_PM_3D_FSTACK_BASE_1,Effective on load 3D context. this register defines the base address of the free list table being referenced in the process of de-allocating pages during a 3D render." hexmask.long.tbyte 0x1C 8.--31. 1. "Reserved_40,Reserved_40" newline hexmask.long.byte 0x1C 0.--7. 1. "ADDR,1TB Addressable 128 bits aligned Base Address for 3D context page tables in the DPM module" repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) group.long ($2+0x220)++0x3 line.long 0x0 "RGX_CR_PM_TA_FSTACK_$1,Note: each 16GB 4KB addressable page (22 bits) is rounded to dword aligned" hexmask.long.word 0x0 22.--31. 1. "Reserved_22,Reserved_22" newline hexmask.long.tbyte 0x0 0.--21. 1. "SIZE,This register defines the number of 4K pages in the free list stack used for the TA page allocation effective on a load TA context." repeat.end group.long 0x230++0x7 line.long 0x0 "RGX_CR_PM_3D_FSTACK_0,Note: each 16GB 4KB addressable page (22 bits) is rounded to dword aligned" hexmask.long.word 0x0 22.--31. 1. "STARTOF_TOP,This register defines the head pointer of the free list in terms of 4K free pages in the free list stack effective on a load TA context." newline hexmask.long.tbyte 0x0 0.--21. 1. "SIZE,This register defines the number of 4K pages in the free list stack used for the TA page allocation effective on a load TA context." line.long 0x4 "RGX_CR_PM_3D_FSTACK_1,Note: each 16GB 4KB addressable page (22 bits) is rounded to dword aligned" hexmask.long.tbyte 0x4 12.--31. 1. "Reserved_44,Reserved_44" newline hexmask.long.word 0x4 0.--11. 1. "STARTOF_TOP,This register defines the head pointer of the free list in terms of 4K free pages in the free list stack effective on a load TA context." group.long 0x240++0x2F line.long 0x0 "RGX_CR_PM_MTILE_ARRAY_0,Effective Immediately." hexmask.long 0x0 4.--31. 1. "BASE_ADDR,1TB Addressable 128 bits aligned Base Address for Mtile Array Base" newline hexmask.long.byte 0x0 0.--3. 1. "Reserved_0,Reserved_0" line.long 0x4 "RGX_CR_PM_MTILE_ARRAY_1,Effective Immediately." hexmask.long.tbyte 0x4 8.--31. 1. "Reserved_40,Reserved_40" newline hexmask.long.byte 0x4 0.--7. 1. "BASE_ADDR,1TB Addressable 128 bits aligned Base Address for Mtile Array Base" line.long 0x8 "RGX_CR_PM_VHEAP_TABLE_0,Effective immediately. this register defines the base address of the virtual heap table information. The size of the Virtual Heap needs to be no smaller than PM_VHEAP_TABLE_SIZE Dwords." hexmask.long 0x8 4.--31. 1. "BASE_ADDR,1TB Addressable 128 bits aligned Base Address for Virtual Heap Table" newline hexmask.long.byte 0x8 0.--3. 1. "Reserved_0,Reserved_0" line.long 0xC "RGX_CR_PM_VHEAP_TABLE_1,Effective immediately. this register defines the base address of the virtual heap table information. The size of the Virtual Heap needs to be no smaller than PM_VHEAP_TABLE_SIZE Dwords." hexmask.long.tbyte 0xC 8.--31. 1. "Reserved_40,Reserved_40" newline hexmask.long.byte 0xC 0.--7. 1. "BASE_ADDR,1TB Addressable 128 bits aligned Base Address for Virtual Heap Table" line.long 0x10 "RGX_CR_PM_TASK_VHEAP_LOAD_0,RGX_CR_PM_TASK_VHEAP_LOAD_0" hexmask.long 0x10 1.--31. 1. "Reserved_1,Reserved_1" newline bitfld.long 0x10 0. "PENDING,Causes the vheap to be loaded as specified by the relevant configuration registers when it is done the hw will clear this bit" "0,1" line.long 0x14 "RGX_CR_PM_TASK_VHEAP_LOAD_1,RGX_CR_PM_TASK_VHEAP_LOAD_1" hexmask.long 0x14 0.--31. 1. "Reserved_1,Reserved_1" line.long 0x18 "RGX_CR_PM_TASK_VHEAP_CLEAR_0,RGX_CR_PM_TASK_VHEAP_CLEAR_0" hexmask.long 0x18 1.--31. 1. "Reserved_1,Reserved_1" newline bitfld.long 0x18 0. "PENDING,Causes the vheap to be cleared as specified by the relevant configuration registers. When it is done the hw will clear this bit" "0,1" line.long 0x1C "RGX_CR_PM_TASK_VHEAP_CLEAR_1,RGX_CR_PM_TASK_VHEAP_CLEAR_1" hexmask.long 0x1C 0.--31. 1. "Reserved_1,Reserved_1" line.long 0x20 "RGX_CR_PM_TASK_VHEAP_STORE_0,RGX_CR_PM_TASK_VHEAP_STORE_0" hexmask.long 0x20 1.--31. 1. "Reserved_1,Reserved_1" newline bitfld.long 0x20 0. "PENDING,Causes the vheap to be stored as specified by the relevant configuration registers. When it is done the hw will clear this bit" "0,1" line.long 0x24 "RGX_CR_PM_TASK_VHEAP_STORE_1,RGX_CR_PM_TASK_VHEAP_STORE_1" hexmask.long 0x24 0.--31. 1. "Reserved_1,Reserved_1" line.long 0x28 "RGX_CR_PM_ALIST0_START_OF_0,start pointer of the allocation list tail.in size of 8 bytes" hexmask.long 0x28 0.--31. 1. "TAIL,allocation List 0 tail pointer" line.long 0x2C "RGX_CR_PM_ALIST0_START_OF_1,start pointer of the allocation list tail.in size of 8 bytes" hexmask.long 0x2C 1.--31. 1. "Reserved_33,Reserved_33" newline bitfld.long 0x2C 0. "TAIL,allocation List 0 tail pointer" "0,1" rgroup.long 0x270++0x7 line.long 0x0 "RGX_CR_PM_ALIST0_STATUS_0,pointer of current allocation list.in size of 8 bytes" hexmask.long 0x0 0.--31. 1. "TAIL,allocation List tail pointer" line.long 0x4 "RGX_CR_PM_ALIST0_STATUS_1,pointer of current allocation list.in size of 8 bytes" hexmask.long 0x4 1.--31. 1. "Reserved_33,Reserved_33" newline bitfld.long 0x4 0. "TAIL,allocation List tail pointer" "0,1" group.long 0x278++0x7 line.long 0x0 "RGX_CR_PM_ALIST1_START_OF_0,start of the tail pointer of current allocation list.effecitve on an allocation_list_load" hexmask.long 0x0 0.--31. 1. "TAIL,start of the allocation list tail pointer" line.long 0x4 "RGX_CR_PM_ALIST1_START_OF_1,start of the tail pointer of current allocation list.effecitve on an allocation_list_load" hexmask.long 0x4 1.--31. 1. "Reserved_33,Reserved_33" newline bitfld.long 0x4 0. "TAIL,start of the allocation list tail pointer" "0,1" rgroup.long 0x280++0x7 line.long 0x0 "RGX_CR_PM_ALIST1_STATUS_0,pointer of current allocation list.in size of 8 bytes" hexmask.long 0x0 0.--31. 1. "TAIL,allocation List tail pointer" line.long 0x4 "RGX_CR_PM_ALIST1_STATUS_1,pointer of current allocation list.in size of 8 bytes" hexmask.long 0x4 1.--31. 1. "Reserved_33,Reserved_33" newline bitfld.long 0x4 0. "TAIL,allocation List tail pointer" "0,1" group.long 0x288++0x1F line.long 0x0 "RGX_CR_PM_TASK_ALIST_LOAD_0,RGX_CR_PM_TASK_ALIST_LOAD_0" hexmask.long 0x0 1.--31. 1. "Reserved_1,Reserved_1" newline bitfld.long 0x0 0. "PENDING,the write to this register will cause allocation list to be loaded from the relevant configuration registers" "0,1" line.long 0x4 "RGX_CR_PM_TASK_ALIST_LOAD_1,RGX_CR_PM_TASK_ALIST_LOAD_1" hexmask.long 0x4 0.--31. 1. "Reserved_1,Reserved_1" line.long 0x8 "RGX_CR_PM_TASK_ALIST_CLEAR_0,RGX_CR_PM_TASK_ALIST_CLEAR_0" hexmask.long 0x8 1.--31. 1. "Reserved_1,Reserved_1" newline bitfld.long 0x8 0. "PENDING,the write to this register will causes the allocation list to be cleard from the relevant configuration registers" "0,1" line.long 0xC "RGX_CR_PM_TASK_ALIST_CLEAR_1,RGX_CR_PM_TASK_ALIST_CLEAR_1" hexmask.long 0xC 0.--31. 1. "Reserved_1,Reserved_1" line.long 0x10 "RGX_CR_PM_DEALLOCATION_STARTOF_MASK_0,RGX_CR_PM_DEALLOCATION_STARTOF_MASK_0" hexmask.long.word 0x10 16.--31. 1. "Reserved_16,Reserved_16" newline hexmask.long.word 0x10 0.--15. 1. "OP,This is the start of the mask PM deallocation will be based on. Normally it is 0. However in ISP context resume or extra 3D timeout case the driver has to programme the value from the previous render." line.long 0x14 "RGX_CR_PM_DEALLOCATION_STARTOF_MASK_1,RGX_CR_PM_DEALLOCATION_STARTOF_MASK_1" hexmask.long 0x14 0.--31. 1. "Reserved_16,Reserved_16" line.long 0x18 "RGX_CR_PM_PAGE_MANAGEOP_0,RGX_CR_PM_PAGE_MANAGEOP_0" hexmask.long 0x18 3.--31. 1. "Reserved_3,Reserved_3" newline bitfld.long 0x18 2. "COMBINE_DALLOC,1 means the PM writes to the free stack will be burst combined" "0,1" newline bitfld.long 0x18 1. "DISABLE_DALLOC,1 means the PM page management deallocation operation will be disabled" "0,1" newline bitfld.long 0x18 0. "DISABLE_ALLOC,1 means the PM page management allocation operation will be disabled" "0,1" line.long 0x1C "RGX_CR_PM_PAGE_MANAGEOP_1,RGX_CR_PM_PAGE_MANAGEOP_1" hexmask.long 0x1C 0.--31. 1. "Reserved_3,Reserved_3" rgroup.long 0x2A8++0x7 line.long 0x0 "RGX_CR_PM_PAGE_MANAGEOP_STATUS_0,RGX_CR_PM_PAGE_MANAGEOP_STATUS_0" hexmask.long 0x0 2.--31. 1. "Reserved_2,Reserved_2" newline bitfld.long 0x0 1. "DALLOC_DISABLED,1 means the PM page management operation has been disabled" "0,1" newline bitfld.long 0x0 0. "ALLOC_DISABLED,1 means the PM page management operation has been disabled" "0,1" line.long 0x4 "RGX_CR_PM_PAGE_MANAGEOP_STATUS_1,RGX_CR_PM_PAGE_MANAGEOP_STATUS_1" hexmask.long 0x4 0.--31. 1. "Reserved_2,Reserved_2" group.long 0x2B0++0xF line.long 0x0 "RGX_CR_PM_CONTEXT_PB_BASE_0,RGX_CR_PM_CONTEXT_PB_BASE_0" hexmask.long 0x0 3.--31. 1. "Reserved_3,Reserved_3" newline bitfld.long 0x0 0.--2. "CMP,Defines whether the TA/3D/HOST contexts are using the same parameter buffer. Setting a bit to '1' indicates that the context is using a different parameter buffer. Bit 0 = 0 : Unified Free List 3D context Parameter buffer = Unified Free List TA.." "MMU Free List 3D context Parameter buffer = MMU..,?,?,?,?,?,?,?" line.long 0x4 "RGX_CR_PM_CONTEXT_PB_BASE_1,RGX_CR_PM_CONTEXT_PB_BASE_1" hexmask.long 0x4 0.--31. 1. "Reserved_3,Reserved_3" line.long 0x8 "RGX_CR_PM_MLIST0_START_OF_0,start value of the mlist tail @ the loading of the context. in size of 4 bytes. stride is 64KB" hexmask.long.word 0x8 22.--31. 1. "Reserved_22,Reserved_22" newline hexmask.long.tbyte 0x8 0.--21. 1. "TAIL,allocation List 0 tail pointer" line.long 0xC "RGX_CR_PM_MLIST0_START_OF_1,start value of the mlist tail @ the loading of the context. in size of 4 bytes. stride is 64KB" hexmask.long 0xC 0.--31. 1. "Reserved_22,Reserved_22" rgroup.long 0x2C0++0x7 line.long 0x0 "RGX_CR_PM_MLIST0_STATUS_0,pointer of current mmu allocation list.in size of 4 bytes. stride is 64KB" hexmask.long.word 0x0 22.--31. 1. "Reserved_22,Reserved_22" newline hexmask.long.tbyte 0x0 0.--21. 1. "TAIL,allocation List 1 tail pointer" line.long 0x4 "RGX_CR_PM_MLIST0_STATUS_1,pointer of current mmu allocation list.in size of 4 bytes. stride is 64KB" hexmask.long 0x4 0.--31. 1. "Reserved_22,Reserved_22" group.long 0x2C8++0x7 line.long 0x0 "RGX_CR_PM_MLIST1_START_OF_0,start of the tail pointer of mmu allocation list.effecitve on an allocation_list_load" hexmask.long.word 0x0 22.--31. 1. "Reserved_22,Reserved_22" newline hexmask.long.tbyte 0x0 0.--21. 1. "TAIL,start of the allocation list 1 tail pointer" line.long 0x4 "RGX_CR_PM_MLIST1_START_OF_1,start of the tail pointer of mmu allocation list.effecitve on an allocation_list_load" hexmask.long 0x4 0.--31. 1. "Reserved_22,Reserved_22" rgroup.long 0x2D0++0x7 line.long 0x0 "RGX_CR_PM_MLIST1_STATUS_0,pointer of mmu allocation list1 pointer.in size of 4 bytes" hexmask.long.word 0x0 22.--31. 1. "Reserved_22,Reserved_22" newline hexmask.long.tbyte 0x0 0.--21. 1. "TAIL,mmu allocation List 1 tail pointer" line.long 0x4 "RGX_CR_PM_MLIST1_STATUS_1,pointer of mmu allocation list1 pointer.in size of 4 bytes" hexmask.long 0x4 0.--31. 1. "Reserved_22,Reserved_22" group.long 0x2D8++0xF line.long 0x0 "RGX_CR_PM_MLIST0_BASE_0,This register defines the base address of the mmu list 0 for the mmu pages. the stride has to be 64KBytes" hexmask.long 0x0 4.--31. 1. "ADDR,1TB Addressable 128 bits aligned Base Address for mmu list0 module Effective Immediately" newline hexmask.long.byte 0x0 0.--3. 1. "Reserved_0,Reserved_0" line.long 0x4 "RGX_CR_PM_MLIST0_BASE_1,This register defines the base address of the mmu list 0 for the mmu pages. the stride has to be 64KBytes" hexmask.long.tbyte 0x4 8.--31. 1. "Reserved_40,Reserved_40" newline hexmask.long.byte 0x4 0.--7. 1. "ADDR,1TB Addressable 128 bits aligned Base Address for mmu list0 module Effective Immediately" line.long 0x8 "RGX_CR_PM_MLIST1_BASE_0,This register defines the base address of the mmu list 1 for the mmu pages. the stride has to be a 64KBytes" hexmask.long 0x8 4.--31. 1. "ADDR,1TB Addressable 128 bits aligned Base Address for mmu list1 module Effective Immediately" newline hexmask.long.byte 0x8 0.--3. 1. "Reserved_0,Reserved_0" line.long 0xC "RGX_CR_PM_MLIST1_BASE_1,This register defines the base address of the mmu list 1 for the mmu pages. the stride has to be a 64KBytes" hexmask.long.tbyte 0xC 8.--31. 1. "Reserved_40,Reserved_40" newline hexmask.long.byte 0xC 0.--7. 1. "ADDR,1TB Addressable 128 bits aligned Base Address for mmu list1 module Effective Immediately" rgroup.long 0x2F8++0x27 line.long 0x0 "RGX_CR_PM_VCE_VTOP_STATUS_0,RGX_CR_PM_VCE_VTOP_STATUS_0" hexmask.long.word 0x0 20.--31. 1. "Reserved_20,Reserved_20" newline hexmask.long.tbyte 0x0 0.--19. 1. "OP,Virtual Page Pointer for the VCE 16KB granauality" line.long 0x4 "RGX_CR_PM_VCE_VTOP_STATUS_1,RGX_CR_PM_VCE_VTOP_STATUS_1" hexmask.long 0x4 0.--31. 1. "Reserved_20,Reserved_20" line.long 0x8 "RGX_CR_PM_TE_VTOP_STATUS_0,RGX_CR_PM_TE_VTOP_STATUS_0" hexmask.long.word 0x8 20.--31. 1. "Reserved_20,Reserved_20" newline hexmask.long.tbyte 0x8 0.--19. 1. "OP,Virtual Page Pointer for the TE 16KB granauality" line.long 0xC "RGX_CR_PM_TE_VTOP_STATUS_1,RGX_CR_PM_TE_VTOP_STATUS_1" hexmask.long 0xC 0.--31. 1. "Reserved_20,Reserved_20" line.long 0x10 "RGX_CR_PM_OUTOF_MEM_SRC_0,RGX_CR_PM_OUTOF_MEM_SRC_0" hexmask.long 0x10 3.--31. 1. "Reserved_3,Reserved_3" newline bitfld.long 0x10 0.--2. "OP,one hot encoding indicating which part of resource runs out of memory bit 0: normal ta free list bit 1: unified ta free list bit 2: mmu free list" "normal ta free list,unified ta free list,mmu free list,?,?,?,?,?" line.long 0x14 "RGX_CR_PM_OUTOF_MEM_SRC_1,RGX_CR_PM_OUTOF_MEM_SRC_1" hexmask.long 0x14 0.--31. 1. "Reserved_3,Reserved_3" line.long 0x18 "RGX_CR_PM_ALIST_VTOP_STATUS_0,RGX_CR_PM_ALIST_VTOP_STATUS_0" hexmask.long.word 0x18 20.--31. 1. "Reserved_20,Reserved_20" newline hexmask.long.tbyte 0x18 0.--19. 1. "OP,Virtual Page Pointer for the allocation list 16KB granauality" line.long 0x1C "RGX_CR_PM_ALIST_VTOP_STATUS_1,RGX_CR_PM_ALIST_VTOP_STATUS_1" hexmask.long 0x1C 0.--31. 1. "Reserved_20,Reserved_20" line.long 0x20 "RGX_CR_PM_MMU_VTOP_STATUS_0,RGX_CR_PM_MMU_VTOP_STATUS_0" hexmask.long.word 0x20 20.--31. 1. "Reserved_20,Reserved_20" newline hexmask.long.tbyte 0x20 0.--19. 1. "OP,Virtual Page Pointer for the MMU 4KB granauality" line.long 0x24 "RGX_CR_PM_MMU_VTOP_STATUS_1,RGX_CR_PM_MMU_VTOP_STATUS_1" hexmask.long 0x24 0.--31. 1. "Reserved_20,Reserved_20" wgroup.long 0x320++0xF line.long 0x0 "RGX_CR_PM_OUTOFMEM_ABORTALL_0,RGX_CR_PM_OUTOFMEM_ABORTALL_0" hexmask.long 0x0 1.--31. 1. "Reserved_1,Reserved_1" newline bitfld.long 0x0 0. "OP,Instruct the PM to Deny the TE allocation outstanding on Out Of Memory" "0,1" line.long 0x4 "RGX_CR_PM_OUTOFMEM_ABORTALL_1,RGX_CR_PM_OUTOFMEM_ABORTALL_1" hexmask.long 0x4 0.--31. 1. "Reserved_1,Reserved_1" line.long 0x8 "RGX_CR_PM_OUTOFMEM_RESTART_0,RGX_CR_PM_OUTOFMEM_RESTART_0" hexmask.long 0x8 1.--31. 1. "Reserved_1,Reserved_1" newline bitfld.long 0x8 0. "OP,Restart the PM after an Out of Memory and Abort sequence" "0,1" line.long 0xC "RGX_CR_PM_OUTOFMEM_RESTART_1,RGX_CR_PM_OUTOFMEM_RESTART_1" hexmask.long 0xC 0.--31. 1. "Reserved_1,Reserved_1" rgroup.long 0x330++0x7 line.long 0x0 "RGX_CR_PM_REQUESTING_SOURCE_0,RGX_CR_PM_REQUESTING_SOURCE_0" hexmask.long 0x0 2.--31. 1. "Reserved_2,Reserved_2" newline bitfld.long 0x0 0.--1. "OP,Requesting source when out of memory. Bit 1 : VCE Bit 0 : TE" "TE,VCE,?,?" line.long 0x4 "RGX_CR_PM_REQUESTING_SOURCE_1,RGX_CR_PM_REQUESTING_SOURCE_1" hexmask.long 0x4 0.--31. 1. "Reserved_2,Reserved_2" group.long 0x338++0xF line.long 0x0 "RGX_CR_PM_PARTIAL_RENDER_ENABLE_0,RGX_CR_PM_PARTIAL_RENDER_ENABLE_0" hexmask.long 0x0 1.--31. 1. "Reserved_1,Reserved_1" newline bitfld.long 0x0 0. "OP,Partial Render Enable Bit" "0,1" line.long 0x4 "RGX_CR_PM_PARTIAL_RENDER_ENABLE_1,RGX_CR_PM_PARTIAL_RENDER_ENABLE_1" hexmask.long 0x4 0.--31. 1. "Reserved_1,Reserved_1" line.long 0x8 "RGX_CR_PM_3D_DEALLOCATE_SCANMODE_0,RGX_CR_PM_3D_DEALLOCATE_SCANMODE_0" hexmask.long 0x8 5.--31. 1. "Reserved_5,Reserved_5" newline hexmask.long.byte 0x8 0.--4. 1. "OP,This register defines the deallocation behaviour of the PM: value > 2 is only for debug on ZLS mode 0 it can only set less than 2 0: PM will free the macrotile memory as soon as it is possible 1: PM only free one mtile for each traverse 2: PM only.." line.long 0xC "RGX_CR_PM_3D_DEALLOCATE_SCANMODE_1,RGX_CR_PM_3D_DEALLOCATE_SCANMODE_1" hexmask.long 0xC 0.--31. 1. "Reserved_5,Reserved_5" rgroup.long 0x348++0xF line.long 0x0 "RGX_CR_PM_TA_FSTACK_STATUS_0,Note: this is the pointer pointing to the TA free stack top. (4KB page pointer)" hexmask.long.word 0x0 22.--31. 1. "Reserved_22,Reserved_22" newline hexmask.long.tbyte 0x0 0.--21. 1. "TOP,This status register indicated the ta context free list pointer status." line.long 0x4 "RGX_CR_PM_TA_FSTACK_STATUS_1,Note: this is the pointer pointing to the TA free stack top. (4KB page pointer)" hexmask.long 0x4 0.--31. 1. "Reserved_22,Reserved_22" line.long 0x8 "RGX_CR_PM_3D_FSTACK_STATUS_0,Note: this is the pointer pointing to the 3D free stack top. (4KB page pointer)" hexmask.long.word 0x8 22.--31. 1. "Reserved_22,Reserved_22" newline hexmask.long.tbyte 0x8 0.--21. 1. "TOP,This status register indicated the 3D context free list status" line.long 0xC "RGX_CR_PM_3D_FSTACK_STATUS_1,Note: this is the pointer pointing to the 3D free stack top. (4KB page pointer)" hexmask.long 0xC 0.--31. 1. "Reserved_22,Reserved_22" group.long 0x358++0x7 line.long 0x0 "RGX_CR_PM_RESERVE_PAGES_0,RGX_CR_PM_RESERVE_PAGES_0" hexmask.long.word 0x0 16.--31. 1. "Reserved_16,Reserved_16" newline hexmask.long.word 0x0 0.--15. 1. "OP,This register defines the guard page required for one VCE/TE allocation. The requirement is set by the number of ppages needed to create the ALIST nodes when a vpage is closed. The MMU requirement is fixed at 3 ppages max for creatig a new ALIST.." line.long 0x4 "RGX_CR_PM_RESERVE_PAGES_1,RGX_CR_PM_RESERVE_PAGES_1" hexmask.long 0x4 0.--31. 1. "Reserved_16,Reserved_16" rgroup.long 0x360++0x17 line.long 0x0 "RGX_CR_PM_DEALLOCATED_MASK_STATUS_0,RGX_CR_PM_DEALLOCATED_MASK_STATUS_0" hexmask.long.word 0x0 16.--31. 1. "Reserved_16,Reserved_16" newline hexmask.long.word 0x0 0.--15. 1. "TOP,This status register contains a bitmask of the macrotiles freed at this point in the render" line.long 0x4 "RGX_CR_PM_DEALLOCATED_MASK_STATUS_1,RGX_CR_PM_DEALLOCATED_MASK_STATUS_1" hexmask.long 0x4 0.--31. 1. "Reserved_16,Reserved_16" line.long 0x8 "RGX_CR_PM_DEALLOCATING_MASK_STATUS_0,RGX_CR_PM_DEALLOCATING_MASK_STATUS_0" hexmask.long.word 0x8 16.--31. 1. "Reserved_16,Reserved_16" newline hexmask.long.word 0x8 0.--15. 1. "TOP,This status register indicates the mtile mask being freed at the current traverse" line.long 0xC "RGX_CR_PM_DEALLOCATING_MASK_STATUS_1,RGX_CR_PM_DEALLOCATING_MASK_STATUS_1" hexmask.long 0xC 0.--31. 1. "Reserved_16,Reserved_16" line.long 0x10 "RGX_CR_PM_PDS_MTILEFREE_STATUS_0,RGX_CR_PM_PDS_MTILEFREE_STATUS_0" hexmask.long.word 0x10 17.--31. 1. "Reserved_17,Reserved_17" newline hexmask.long.tbyte 0x10 0.--16. 1. "OP,This status register indicates the macrotile number of the PDSs current macrotile free request" line.long 0x14 "RGX_CR_PM_PDS_MTILEFREE_STATUS_1,RGX_CR_PM_PDS_MTILEFREE_STATUS_1" hexmask.long 0x14 0.--31. 1. "Reserved_17,Reserved_17" group.long 0x378++0x7 line.long 0x0 "RGX_CR_PM_TA_FREE_CONTEXT_0,RGX_CR_PM_TA_FREE_CONTEXT_0" hexmask.long 0x0 1.--31. 1. "Reserved_1,Reserved_1" newline bitfld.long 0x0 0. "PENDING,free the ta context register operation" "0,1" line.long 0x4 "RGX_CR_PM_TA_FREE_CONTEXT_1,RGX_CR_PM_TA_FREE_CONTEXT_1" hexmask.long 0x4 0.--31. 1. "Reserved_1,Reserved_1" wgroup.long 0x380++0x7 line.long 0x0 "RGX_CR_PM_3D_TIMEOUT_NOW_0,RGX_CR_PM_3D_TIMEOUT_NOW_0" hexmask.long 0x0 1.--31. 1. "Reserved_1,Reserved_1" newline bitfld.long 0x0 0. "OP,free the 3D context" "0,1" line.long 0x4 "RGX_CR_PM_3D_TIMEOUT_NOW_1,RGX_CR_PM_3D_TIMEOUT_NOW_1" hexmask.long 0x4 0.--31. 1. "Reserved_1,Reserved_1" group.long 0x388++0x7 line.long 0x0 "RGX_CR_PM_3D_DEALLOCATE_ENABLE_0,RGX_CR_PM_3D_DEALLOCATE_ENABLE_0" hexmask.long 0x0 1.--31. 1. "Reserved_1,Reserved_1" newline bitfld.long 0x0 0. "OP,3D deallocate enable mode" "0,1" line.long 0x4 "RGX_CR_PM_3D_DEALLOCATE_ENABLE_1,RGX_CR_PM_3D_DEALLOCATE_ENABLE_1" hexmask.long 0x4 0.--31. 1. "Reserved_1,Reserved_1" repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) group.long ($2+0x390)++0x3 line.long 0x0 "RGX_CR_PM_START_OF_TACONTEXT_$1,RGX_CR_PM_START_OF_TACONTEXT_0" hexmask.long.word 0x0 22.--31. 1. "Reserved_22,Reserved_22" newline hexmask.long.tbyte 0x0 0.--21. 1. "ALLOCATED_PAGE,Start of TA pages(4KB) on loading of the TA context" repeat.end repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) group.long ($2+0x398)++0x3 line.long 0x0 "RGX_CR_PM_START_OF_3DCONTEXT_$1,RGX_CR_PM_START_OF_3DCONTEXT_0" hexmask.long.word 0x0 22.--31. 1. "Reserved_22,Reserved_22" newline hexmask.long.tbyte 0x0 0.--21. 1. "ALLOCATED_PAGE,Start of 3D pages(4KB) on loading of the TA context" repeat.end rgroup.long 0x3A0++0x2F line.long 0x0 "RGX_CR_PM_TA_PAGE_STATUS_0,RGX_CR_PM_TA_PAGE_STATUS_0" hexmask.long.word 0x0 22.--31. 1. "Reserved_22,Reserved_22" newline hexmask.long.tbyte 0x0 0.--21. 1. "OP,The number of TA pages currently allocated" line.long 0x4 "RGX_CR_PM_TA_PAGE_STATUS_1,RGX_CR_PM_TA_PAGE_STATUS_1" hexmask.long 0x4 0.--31. 1. "Reserved_22,Reserved_22" line.long 0x8 "RGX_CR_PM_3D_PAGE_STATUS_0,RGX_CR_PM_3D_PAGE_STATUS_0" hexmask.long.word 0x8 22.--31. 1. "Reserved_22,Reserved_22" newline hexmask.long.tbyte 0x8 0.--21. 1. "OP,The number of 3D pages currently allocated" line.long 0xC "RGX_CR_PM_3D_PAGE_STATUS_1,RGX_CR_PM_3D_PAGE_STATUS_1" hexmask.long 0xC 0.--31. 1. "Reserved_22,Reserved_22" line.long 0x10 "RGX_CR_PM_VCE_INFLIGHT_STATUS_0,RGX_CR_PM_VCE_INFLIGHT_STATUS_0" hexmask.long.word 0x10 20.--31. 1. "Reserved_20,Reserved_20" newline hexmask.long.tbyte 0x10 0.--19. 1. "OP,The Virtual Page Number in flight in the VCE Requestor" line.long 0x14 "RGX_CR_PM_VCE_INFLIGHT_STATUS_1,RGX_CR_PM_VCE_INFLIGHT_STATUS_1" hexmask.long 0x14 0.--31. 1. "Reserved_20,Reserved_20" line.long 0x18 "RGX_CR_PM_TE_INFLIGHT_STATUS_0,RGX_CR_PM_TE_INFLIGHT_STATUS_0" hexmask.long.word 0x18 20.--31. 1. "Reserved_20,Reserved_20" newline hexmask.long.tbyte 0x18 0.--19. 1. "OP,The Virtual Page Number in flight in the TE Requestor" line.long 0x1C "RGX_CR_PM_TE_INFLIGHT_STATUS_1,RGX_CR_PM_TE_INFLIGHT_STATUS_1" hexmask.long 0x1C 0.--31. 1. "Reserved_20,Reserved_20" line.long 0x20 "RGX_CR_BIFPM_IDLE_0,RGX_CR_BIFPM_IDLE_0" hexmask.long 0x20 7.--31. 1. "Reserved_7,Reserved_7" newline bitfld.long 0x20 6. "MCU_L0_MEMIF,MCU L0 MEMIF Module IDLE" "0,1" newline bitfld.long 0x20 5. "PBE,PBE Module IDLE" "0,1" newline bitfld.long 0x20 4. "MCU_L0_PDSRW,MCU L0 PDSRW Module IDLE" "0,1" newline bitfld.long 0x20 3. "MCU_L1,MCU L1 Module IDLE" "0,1" newline bitfld.long 0x20 2. "USCS,USC Shared Module IDLE" "0,1" newline bitfld.long 0x20 1. "PM,PM Module IDLE" "0,1" newline bitfld.long 0x20 0. "BIF256,BIF256 Module IDLE" "0,1" line.long 0x24 "RGX_CR_BIFPM_IDLE_1,RGX_CR_BIFPM_IDLE_1" hexmask.long 0x24 0.--31. 1. "Reserved_7,Reserved_7" line.long 0x28 "RGX_CR_SIDEKICK_IDLE_0,RGX_CR_SIDEKICK_IDLE_0" hexmask.long 0x28 7.--31. 1. "Reserved_7,Reserved_7" newline bitfld.long 0x28 6. "FB_CDC,FB CDC Module IDLE" "0,1" newline bitfld.long 0x28 5. "MMU,MMU Module IDLE" "0,1" newline bitfld.long 0x28 4. "BIF128,BIF128 Module IDLE" "0,1" newline bitfld.long 0x28 3. "TLA,TLA Module IDLE" "0,1" newline bitfld.long 0x28 2. "GARTEN,GARTEN Module IDLE" "0,1" newline bitfld.long 0x28 1. "HOSTIF,HOSTIF Module IDLE" "0,1" newline bitfld.long 0x28 0. "SOCIF,SOCIF Module IDLE" "0,1" line.long 0x2C "RGX_CR_SIDEKICK_IDLE_1,RGX_CR_SIDEKICK_IDLE_1" hexmask.long 0x2C 0.--31. 1. "Reserved_7,Reserved_7" group.long 0x3D0++0x17 line.long 0x0 "RGX_CR_PM_CONTEXT_ID_0,RGX_CR_PM_CONTEXT_ID_0" hexmask.long.byte 0x0 25.--31. 1. "Reserved_25,Reserved_25" newline bitfld.long 0x0 24. "MLIS_ALLOC,MMU page List (TE VCE aligned with this context )Allocation Context ID" "0,1" newline hexmask.long.byte 0x0 17.--23. 1. "Reserved_17,Reserved_17" newline bitfld.long 0x0 16. "LS,Load Store Context ID for the allocation list" "0,1" newline hexmask.long.byte 0x0 9.--15. 1. "Reserved_9,Reserved_9" newline bitfld.long 0x0 8. "DALLOC,DeAllocation Context ID for the allocation list" "0,1" newline hexmask.long.byte 0x0 1.--7. 1. "Reserved_1,Reserved_1" newline bitfld.long 0x0 0. "ALLOC,Allocation Context ID for the allocation list" "0,1" line.long 0x4 "RGX_CR_PM_CONTEXT_ID_1,RGX_CR_PM_CONTEXT_ID_1" hexmask.long.tbyte 0x4 9.--31. 1. "Reserved_41,Reserved_41" newline bitfld.long 0x4 8. "MLIS_LS,MMU page List (TE VCE aligned with this context )Load Store Context ID" "0,1" newline hexmask.long.byte 0x4 1.--7. 1. "Reserved_33,Reserved_33" newline bitfld.long 0x4 0. "MLIS_DALLOC,MMU page List (TE VCE aligned with this context )DeAllocation Context ID" "0,1" line.long 0x8 "RGX_CR_PM_3D_RENDER_TARGET_INDEX_0,RGX_CR_PM_3D_RENDER_TARGET_INDEX_0" hexmask.long.tbyte 0x8 11.--31. 1. "Reserved_11,Reserved_11" newline hexmask.long.word 0x8 0.--10. 1. "ID,Render Target ID which is being rendered" line.long 0xC "RGX_CR_PM_3D_RENDER_TARGET_INDEX_1,RGX_CR_PM_3D_RENDER_TARGET_INDEX_1" hexmask.long 0xC 0.--31. 1. "Reserved_11,Reserved_11" line.long 0x10 "RGX_CR_PM_3D_RENDER_TARGET_LAST_0,RGX_CR_PM_3D_RENDER_TARGET_LAST_0" hexmask.long 0x10 1.--31. 1. "Reserved_1,Reserved_1" newline bitfld.long 0x10 0. "ID,If this bit is set this means the render will be the last one in the whole render target array. If no multiple render target array is present this bit always needs set" "0,1" line.long 0x14 "RGX_CR_PM_3D_RENDER_TARGET_LAST_1,RGX_CR_PM_3D_RENDER_TARGET_LAST_1" hexmask.long 0x14 0.--31. 1. "Reserved_1,Reserved_1" rgroup.long 0x3E8++0x17 line.long 0x0 "RGX_CR_PM_LOCK_STATUS_0,RGX_CR_PM_LOCK_STATUS_0" hexmask.long 0x0 2.--31. 1. "Reserved_2,Reserved_2" newline bitfld.long 0x0 1. "TD,Bit 1: 3D free list Lock Status. 0 idle/ 1 used" "0,1" newline bitfld.long 0x0 0. "TA,Bit 0: TA free list Lock Status. 0 idle/ 1 used." "TA free list Lock Status,?" line.long 0x4 "RGX_CR_PM_LOCK_STATUS_1,RGX_CR_PM_LOCK_STATUS_1" hexmask.long 0x4 0.--31. 1. "Reserved_2,Reserved_2" line.long 0x8 "RGX_CR_PM_LOCK_OWNER_0,RGX_CR_PM_LOCK_OWNER_0" hexmask.long 0x8 2.--31. 1. "Reserved_2,Reserved_2" newline bitfld.long 0x8 1. "TD,Bit 1 :3D free list Lock owner. 0 PMA / 1 PMD" "0,1" newline bitfld.long 0x8 0. "TA,Bit 0: TA free list Lock Owner. 0 PMA / 1 PMD." "TA free list Lock Owner,?" line.long 0xC "RGX_CR_PM_LOCK_OWNER_1,RGX_CR_PM_LOCK_OWNER_1" hexmask.long 0xC 0.--31. 1. "Reserved_2,Reserved_2" line.long 0x10 "RGX_CR_PM_IDLE_STATUS_0,RGX_CR_PM_IDLE_STATUS_0" hexmask.long.tbyte 0x10 8.--31. 1. "Reserved_8,Reserved_8" newline bitfld.long 0x10 7. "PMD_BIF,Idle Status Register of the PMD module bif state machine" "0,1" newline bitfld.long 0x10 6. "PMD_FRE,Idle Status Register of the PMD module master state machine" "0,1" newline bitfld.long 0x10 5. "BIF,Idle Status Register of the BIF Interface default" "0,1" newline bitfld.long 0x10 4. "BARB,Idle Status Register of the BIF Arbiter state BAR" "0,1" newline bitfld.long 0x10 3. "AMAN,Idle Status Register of the Alist state machine" "0,1" newline bitfld.long 0x10 2. "STA,Idle Status Register of the Stack Manager Modul" "0,1" newline bitfld.long 0x10 1. "PMD,Idle Status Register of the PMD module" "0,1" newline bitfld.long 0x10 0. "PMA,Idle Status Register of the PMA module" "0,1" line.long 0x14 "RGX_CR_PM_IDLE_STATUS_1,RGX_CR_PM_IDLE_STATUS_1" hexmask.long 0x14 0.--31. 1. "Reserved_8,Reserved_8" wgroup.long 0x400++0x7 line.long 0x0 "RGX_CR_VDM_START_0,A write of '1' to this register starts the Vertex Data Master (TA) Reading the control stream pointed to by VDM_CTRL_STREAM_BASE" hexmask.long 0x0 1.--31. 1. "Reserved_1,Reserved_1" newline bitfld.long 0x0 0. "PULSE,Start VDM" "0,1" line.long 0x4 "RGX_CR_VDM_START_1,A write of '1' to this register starts the Vertex Data Master (TA) Reading the control stream pointed to by VDM_CTRL_STREAM_BASE" hexmask.long 0x4 0.--31. 1. "Reserved_1,Reserved_1" group.long 0x408++0x7 line.long 0x0 "RGX_CR_VDM_CTRL_STREAM_BASE_0,The base address of the Vertex Data Master's Input Parameter Control Stream in external memory" hexmask.long 0x0 2.--31. 1. "ADDR,1TB range 32-bit aligned base address" newline bitfld.long 0x0 0.--1. "Reserved_0,Reserved_0" "0,1,2,3" line.long 0x4 "RGX_CR_VDM_CTRL_STREAM_BASE_1,The base address of the Vertex Data Master's Input Parameter Control Stream in external memory" hexmask.long.tbyte 0x4 8.--31. 1. "Reserved_40,Reserved_40" newline hexmask.long.byte 0x4 0.--7. 1. "ADDR,1TB range 32-bit aligned base address" rgroup.long 0x410++0x7 line.long 0x0 "RGX_CR_VDM_CTRL_STREAM_CURRENT_0,This status register reports the current position in the input parameter format of the data being processed. This is a debug register. This is NOT the fetch address presented to the BIF. which is reading ahead Since the.." hexmask.long 0x0 2.--31. 1. "ADDR,1TB range 32-bit aligned address" newline bitfld.long 0x0 0.--1. "Reserved_0,Reserved_0" "0,1,2,3" line.long 0x4 "RGX_CR_VDM_CTRL_STREAM_CURRENT_1,This status register reports the current position in the input parameter format of the data being processed. This is a debug register. This is NOT the fetch address presented to the BIF. which is reading ahead Since the.." hexmask.long.tbyte 0x4 8.--31. 1. "Reserved_40,Reserved_40" newline hexmask.long.byte 0x4 0.--7. 1. "ADDR,1TB range 32-bit aligned address" group.long 0x418++0x17 line.long 0x0 "RGX_CR_VDM_CALL_STACK_POINTER_0,The pointer to the control stream call stack. The current pointer within the VDM's call stack in external memory. The call stack is used whenever a call is made to another control stream. to store the return address.." hexmask.long 0x0 3.--31. 1. "ADDR,1TB range 64-bit aligned base address" newline bitfld.long 0x0 0.--2. "Reserved_0,Reserved_0" "0,1,2,3,4,5,6,7" line.long 0x4 "RGX_CR_VDM_CALL_STACK_POINTER_1,The pointer to the control stream call stack. The current pointer within the VDM's call stack in external memory. The call stack is used whenever a call is made to another control stream. to store the return address.." hexmask.long.tbyte 0x4 8.--31. 1. "Reserved_40,Reserved_40" newline hexmask.long.byte 0x4 0.--7. 1. "ADDR,1TB range 64-bit aligned base address" line.long 0x8 "RGX_CR_VDM_BATCH_0,The Batch number is a index list block (draw call) ID which is passed through the GPU pipeline. This is helpful for debug and performance profiling. The starting batch number should be programmed before the first TA phase of every.." hexmask.long.tbyte 0x8 14.--31. 1. "Reserved_14,Reserved_14" newline hexmask.long.word 0x8 0.--13. 1. "NUMBER,NUMBER" line.long 0xC "RGX_CR_VDM_BATCH_1,The Batch number is a index list block (draw call) ID which is passed through the GPU pipeline. This is helpful for debug and performance profiling. The starting batch number should be programmed before the first TA phase of every.." hexmask.long 0xC 0.--31. 1. "Reserved_14,Reserved_14" line.long 0x10 "RGX_CR_VDM_CONTEXT_STATE_BASE_0,The base address in external memory of the VDM's context state buffer. On a context store the VDM will store its state to this address. and reload it on a context resume. The size and format of the data written is defined.." hexmask.long 0x10 4.--31. 1. "ADDR,1TB range 128-bit aligned base address" newline hexmask.long.byte 0x10 0.--3. 1. "Reserved_0,Reserved_0" line.long 0x14 "RGX_CR_VDM_CONTEXT_STATE_BASE_1,The base address in external memory of the VDM's context state buffer. On a context store the VDM will store its state to this address. and reload it on a context resume. The size and format of the data written is defined.." hexmask.long.tbyte 0x14 8.--31. 1. "Reserved_40,Reserved_40" newline hexmask.long.byte 0x14 0.--7. 1. "ADDR,1TB range 128-bit aligned base address" rgroup.long 0x430++0x7 line.long 0x0 "RGX_CR_VDM_CONTEXT_STORE_STATUS_0,This register indicates the status of a VDM context switch operation. If a context store has been requested. then this muist be sample on TA finished. The firmware must wait for the COMPLETE bit to be set. The.." hexmask.long.tbyte 0x0 8.--31. 1. "Reserved_8,Reserved_8" newline hexmask.long.byte 0x0 4.--7. 1. "LAST_PIPE,The TA pipe number to which the VDM last sent indices" newline bitfld.long 0x0 2.--3. "Reserved_2,Reserved_2" "0,1,2,3" newline bitfld.long 0x0 1. "NEED_RESUME,The VDM still has control stream left to process meaning this context must be resumed" "0,1" newline bitfld.long 0x0 0. "COMPLETE,The VDM has completed the context store operation and fenced its state to external memory" "0,1" line.long 0x4 "RGX_CR_VDM_CONTEXT_STORE_STATUS_1,This register indicates the status of a VDM context switch operation. If a context store has been requested. then this muist be sample on TA finished. The firmware must wait for the COMPLETE bit to be set. The.." hexmask.long 0x4 0.--31. 1. "Reserved_8,Reserved_8" repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) group.long ($2+0x438)++0x3 line.long 0x0 "RGX_CR_VDM_CONTEXT_STORE_TASK0_$1,These words define the PDS State Update task which will be inserted into the VDM pipeline on a context store operation. The function of this task is described in the Rogue Context Switching Hardware Specification. Their.." hexmask.long 0x0 0.--31. 1. "PDS_STATE0,PDS_STATE0" repeat.end repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) group.long ($2+0x440)++0x3 line.long 0x0 "RGX_CR_VDM_CONTEXT_STORE_TASK1_$1,This word defines the PDS State Update task which will be inserted into the VDM pipeline on a context store operation. The function of this task is described in the Rogue Context Switching Hardware Specification. Its.." hexmask.long 0x0 0.--31. 1. "PDS_STATE2,PDS_STATE2" repeat.end repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) group.long ($2+0x448)++0x3 line.long 0x0 "RGX_CR_VDM_CONTEXT_STORE_TASK2_$1,These words defines the Stream Out Sync program which will be inserted into the VDM pipeline as a PPP State Update on a context store operation. The function of this task is described in the Rogue Context Switching.." hexmask.long 0x0 0.--31. 1. "STREAM_OUT1,STREAM_OUT1" repeat.end repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) group.long ($2+0x450)++0x3 line.long 0x0 "RGX_CR_VDM_CONTEXT_RESUME_TASK0_$1,These words define the PDS State Update task which will be written by the VDM to its context resume control stream on a context store operation. The function of this task is described in the Rogue Context Switching.." hexmask.long 0x0 0.--31. 1. "PDS_STATE0,PDS_STATE0" repeat.end repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) group.long ($2+0x458)++0x3 line.long 0x0 "RGX_CR_VDM_CONTEXT_RESUME_TASK1_$1,This word defines the PDS State Update task which will be written by the VDM to its context resume control stream on a context store operation. The function of this task is described in the Rogue Context Switching.." hexmask.long 0x0 0.--31. 1. "PDS_STATE2,PDS_STATE2" repeat.end repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) group.long ($2+0x460)++0x3 line.long 0x0 "RGX_CR_VDM_CONTEXT_RESUME_TASK2_$1,These words defines the Stream Out Sync program which will be written. as a PPP State Update. by the VDM to its context resume control stream on a context store operation The function of this task is described in the.." hexmask.long 0x0 0.--31. 1. "STREAM_OUT1,STREAM_OUT1" repeat.end wgroup.long 0x468++0x7 line.long 0x0 "RGX_CR_VDM_CONTEXT_STORE_START_0,Writing '1' to this register starts the VDM context store operation. The function of this task is described in the Rogue Context Switching Hardware Specifiction" hexmask.long 0x0 1.--31. 1. "Reserved_1,Reserved_1" newline bitfld.long 0x0 0. "PULSE,PULSE" "0,1" line.long 0x4 "RGX_CR_VDM_CONTEXT_STORE_START_1,Writing '1' to this register starts the VDM context store operation. The function of this task is described in the Rogue Context Switching Hardware Specifiction" hexmask.long 0x4 0.--31. 1. "Reserved_1,Reserved_1" group.long 0x470++0x7 line.long 0x0 "RGX_CR_VDM_SYNC_PDS_DATA_BASE_0,The base address of the PDS data segment base for all TA state sync program 4GB range. 128-bit granularity The data segment size is always 256 bits The PDS code address for the TA state sync program is always 256 bits on.." hexmask.long 0x0 4.--31. 1. "ADDR,ADDR" newline hexmask.long.byte 0x0 0.--3. 1. "Reserved_0,Reserved_0" line.long 0x4 "RGX_CR_VDM_SYNC_PDS_DATA_BASE_1,The base address of the PDS data segment base for all TA state sync program 4GB range. 128-bit granularity The data segment size is always 256 bits The PDS code address for the TA state sync program is always 256 bits on.." hexmask.long 0x4 0.--31. 1. "Reserved_32,Reserved_32" wgroup.long 0x478++0x7 line.long 0x0 "RGX_CR_CDM_START_0,A write of '1' to this register starts the Compute Data Master reading it's control stream from memory." hexmask.long 0x0 1.--31. 1. "Reserved_1,Reserved_1" newline bitfld.long 0x0 0. "PULSE,Start CDM" "0,1" line.long 0x4 "RGX_CR_CDM_START_1,A write of '1' to this register starts the Compute Data Master reading it's control stream from memory." hexmask.long 0x4 0.--31. 1. "Reserved_1,Reserved_1" group.long 0x480++0x7 line.long 0x0 "RGX_CR_CDM_CTRL_STREAM_BASE_0,The base address of the Compute Data Master's Input Parameter Control Stream in external memory" hexmask.long 0x0 2.--31. 1. "ADDR,1TB range 32-bit aligned base address" newline bitfld.long 0x0 0.--1. "Reserved_0,Reserved_0" "0,1,2,3" line.long 0x4 "RGX_CR_CDM_CTRL_STREAM_BASE_1,The base address of the Compute Data Master's Input Parameter Control Stream in external memory" hexmask.long.tbyte 0x4 8.--31. 1. "Reserved_40,Reserved_40" newline hexmask.long.byte 0x4 0.--7. 1. "ADDR,1TB range 32-bit aligned base address" wgroup.long 0x488++0x7 line.long 0x0 "RGX_CR_CDM_CONTEXT_STORE_0,Writing '1' to this register starts the CDM context store operation." hexmask.long 0x0 1.--31. 1. "Reserved_1,Reserved_1" newline bitfld.long 0x0 0. "PULSE,PULSE" "0,1" line.long 0x4 "RGX_CR_CDM_CONTEXT_STORE_1,Writing '1' to this register starts the CDM context store operation." hexmask.long 0x4 0.--31. 1. "Reserved_1,Reserved_1" group.long 0x490++0xF line.long 0x0 "RGX_CR_CDM_CONTEXT_LOAD_0,The firmware writes a '1' to this register starts the CDM context load operation. The CDM will set this register to '0' when the context load operation is complete The firmware should poll on this register after writing to it" hexmask.long 0x0 1.--31. 1. "Reserved_1,Reserved_1" newline bitfld.long 0x0 0. "PENDING,PENDING" "0,1" line.long 0x4 "RGX_CR_CDM_CONTEXT_LOAD_1,The firmware writes a '1' to this register starts the CDM context load operation. The CDM will set this register to '0' when the context load operation is complete The firmware should poll on this register after writing to it" hexmask.long 0x4 0.--31. 1. "Reserved_1,Reserved_1" line.long 0x8 "RGX_CR_CDM_CONTEXT_STATE_BASE_0,The base address in external memory of the CDM's context state buffer. to which it will store its snapshot state on a context store and from which it will reload on a context resume" hexmask.long 0x8 4.--31. 1. "ADDR,1TB range 128-bit aligned base address" newline hexmask.long.byte 0x8 0.--3. 1. "Reserved_0,Reserved_0" line.long 0xC "RGX_CR_CDM_CONTEXT_STATE_BASE_1,The base address in external memory of the CDM's context state buffer. to which it will store its snapshot state on a context store and from which it will reload on a context resume" hexmask.long.tbyte 0xC 8.--31. 1. "Reserved_40,Reserved_40" newline hexmask.long.byte 0xC 0.--7. 1. "ADDR,1TB range 128-bit aligned base address" rgroup.long 0x4A0++0x7 line.long 0x0 "RGX_CR_CDM_CONTEXT_STORE_STATUS_0,This register indicates the status of a CDM context switch operation. If a context store is in progress. this register must be sampled on a context store compute finished event. The firmware must wait for the COMPLETE.." hexmask.long 0x0 2.--31. 1. "Reserved_2,Reserved_2" newline bitfld.long 0x0 1. "NEED_RESUME,The CDM still has control stream left to process meaning this context must be resumed" "0,1" newline bitfld.long 0x0 0. "COMPLETE,The CDM has completed the context store operation and fenced its state to external memory" "0,1" line.long 0x4 "RGX_CR_CDM_CONTEXT_STORE_STATUS_1,This register indicates the status of a CDM context switch operation. If a context store is in progress. this register must be sampled on a context store compute finished event. The firmware must wait for the COMPLETE.." hexmask.long 0x4 0.--31. 1. "Reserved_2,Reserved_2" repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) group.long ($2+0x4A8)++0x3 line.long 0x0 "RGX_CR_CDM_CONTEXT_PDS0_$1,This register contains the PDS Code and Data Addresses for the Store/Load Program. This program is sent to PDS on Context Store and Context Load." hexmask.long 0x0 4.--31. 1. "CODE_ADDR,PDS Code Address for Store/Load Program 128-bit aligned" newline hexmask.long.byte 0x0 0.--3. 1. "Reserved_0,Reserved_0" repeat.end group.long 0x4B0++0x7 line.long 0x0 "RGX_CR_CDM_CONTEXT_PDS1_0,This register contains the PDS Task Data necessary to produce the Store/Load PDS Program Task from CDM to PDS" bitfld.long 0x0 30.--31. "Reserved_30,Reserved_30" "0,1,2,3" newline bitfld.long 0x0 29. "PDS_SEQ_DEP,PDS Sequential Dependency" "0,1" newline bitfld.long 0x0 28. "USC_SEQ_DEP,USC Sequential Dependency" "0,1" newline bitfld.long 0x0 27. "TARGET,USC Target (0=All 1=Any)" "All,Any)" newline hexmask.long.byte 0x0 21.--26. 1. "UNIFIED_SIZE,Unified Size" newline bitfld.long 0x0 20. "COMMON_SHARED,PDS Common Store Allocation is Shared Registers" "0,1" newline hexmask.long.word 0x0 11.--19. 1. "COMMON_SIZE,PDS Common Size" newline hexmask.long.byte 0x0 7.--10. 1. "TEMP_SIZE,PDS Temp Size" newline hexmask.long.byte 0x0 1.--6. 1. "DATA_SIZE,PDS Data Size" newline bitfld.long 0x0 0. "FENCE,Fence the Task in the PDS/USC - Set on Store unset on Load" "0,1" line.long 0x4 "RGX_CR_CDM_CONTEXT_PDS1_1,This register contains the PDS Task Data necessary to produce the Store/Load PDS Program Task from CDM to PDS" hexmask.long 0x4 0.--31. 1. "Reserved_30,Reserved_30" repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) group.long ($2+0x4B8)++0x3 line.long 0x0 "RGX_CR_CDM_TERMINATE_PDS_$1,This register contains the PDS Code and Data Addresses for the Terminate Program. This program is sent to PDS on Context Store after the Context Store Program" hexmask.long 0x0 4.--31. 1. "CODE_ADDR,PDS Code Address for Terminate Program 128-bit aligned" newline hexmask.long.byte 0x0 0.--3. 1. "Reserved_0,Reserved_0" repeat.end group.long 0x4C0++0x7 line.long 0x0 "RGX_CR_CDM_TERMINATE_PDS1_0,This register contains the PDS Task Data necessary to produce the Context Store Terminate PDS Program Task from CDM to PDS" bitfld.long 0x0 30.--31. "Reserved_30,Reserved_30" "0,1,2,3" newline bitfld.long 0x0 29. "PDS_SEQ_DEP,PDS Sequential Dependency" "0,1" newline bitfld.long 0x0 28. "USC_SEQ_DEP,USC Sequential Dependency" "0,1" newline bitfld.long 0x0 27. "TARGET,USC Target (0=All 1=Any)" "All,Any)" newline hexmask.long.byte 0x0 21.--26. 1. "UNIFIED_SIZE,Unified Size" newline bitfld.long 0x0 20. "COMMON_SHARED,PDS Common Store Allocation is Shared Registers" "0,1" newline hexmask.long.word 0x0 11.--19. 1. "COMMON_SIZE,PDS Common Size" newline hexmask.long.byte 0x0 7.--10. 1. "TEMP_SIZE,PDS Temp Size" newline hexmask.long.byte 0x0 1.--6. 1. "DATA_SIZE,PDS Data Size" newline bitfld.long 0x0 0. "FENCE,Fence the Task in the PDS/USC - Set on Store Terminate" "0,1" line.long 0x4 "RGX_CR_CDM_TERMINATE_PDS1_1,This register contains the PDS Task Data necessary to produce the Context Store Terminate PDS Program Task from CDM to PDS" hexmask.long 0x4 0.--31. 1. "Reserved_30,Reserved_30" repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) group.long ($2+0x4D8)++0x3 line.long 0x0 "RGX_CR_CDM_CONTEXT_LOAD_PDS0_$1,This register contains the PDS Code and Data Addresses for the Store/Load Program. This program is sent to PDS on Context Store and Context Load." hexmask.long 0x0 4.--31. 1. "CODE_ADDR,PDS Code Address for Store/Load Program 128-bit aligned" newline hexmask.long.byte 0x0 0.--3. 1. "Reserved_0,Reserved_0" repeat.end group.long 0x4E0++0x7 line.long 0x0 "RGX_CR_CDM_CONTEXT_LOAD_PDS1_0,This register contains the PDS Task Data necessary to produce the Store/Load PDS Program Task from CDM to PDS" bitfld.long 0x0 30.--31. "Reserved_30,Reserved_30" "0,1,2,3" newline bitfld.long 0x0 29. "PDS_SEQ_DEP,PDS Sequential Dependency" "0,1" newline bitfld.long 0x0 28. "USC_SEQ_DEP,USC Sequential Dependency" "0,1" newline bitfld.long 0x0 27. "TARGET,USC Target (0=All 1=Any)" "All,Any)" newline hexmask.long.byte 0x0 21.--26. 1. "UNIFIED_SIZE,Unified Size" newline bitfld.long 0x0 20. "COMMON_SHARED,PDS Common Store Allocation is Shared Registers" "0,1" newline hexmask.long.word 0x0 11.--19. 1. "COMMON_SIZE,PDS Common Size" newline hexmask.long.byte 0x0 7.--10. 1. "TEMP_SIZE,PDS Temp Size" newline hexmask.long.byte 0x0 1.--6. 1. "DATA_SIZE,PDS Data Size" newline bitfld.long 0x0 0. "FENCE,Fence the Task in the PDS/USC - Set on Store unset on Load" "0,1" line.long 0x4 "RGX_CR_CDM_CONTEXT_LOAD_PDS1_1,This register contains the PDS Task Data necessary to produce the Store/Load PDS Program Task from CDM to PDS" hexmask.long 0x4 0.--31. 1. "Reserved_30,Reserved_30" group.long 0x600++0x7 line.long 0x0 "RGX_CR_PDS_CTRL_0,Controls the maximum number of tasks per data master (per USC). There are a maximum of 48 tasks in the system" hexmask.long.byte 0x0 24.--31. 1. "MAX_NUM_CDM_TASKS,The maximum number of compute tasks allowed on each USC range 0 to 48" newline hexmask.long.byte 0x0 16.--23. 1. "MAX_NUM_PDM_TASKS,The maximum number of pixel tasks allowed on each USC range 0 to 48" newline hexmask.long.byte 0x0 8.--15. 1. "MAX_NUM_VDM_TASKS,The maximum number of vertex tasks (VS HS GS when Tess not enabled) allowed on each USC range 0 to 39 (Note reduced range to prevent Pixel/VDM system deadlock)" newline hexmask.long.byte 0x0 0.--7. 1. "MAX_NUM_TDM_TASKS,The maximum number of fastrender tasks allowed on each USC range 0 to 48" line.long 0x4 "RGX_CR_PDS_CTRL_1,Controls the maximum number of tasks per data master (per USC). There are a maximum of 48 tasks in the system" hexmask.long 0x4 0.--31. 1. "Reserved_32,Reserved_32" wgroup.long 0x608++0x7 line.long 0x0 "RGX_CR_PDS_USC_COLLATOR_0,This register clear the internal resource tracking storage. It must be cleared after reste/power up. A write of '1' to this register clears the PDS Unified Clusters Resource Collator Contents. The PDS USC Resource Collator is a.." hexmask.long 0x0 1.--31. 1. "Reserved_1,Reserved_1" newline bitfld.long 0x0 0. "CLEAR,Clear PDS Unified Clusters Resource Collator" "0,1" line.long 0x4 "RGX_CR_PDS_USC_COLLATOR_1,This register clear the internal resource tracking storage. It must be cleared after reste/power up. A write of '1' to this register clears the PDS Unified Clusters Resource Collator Contents. The PDS USC Resource Collator is a.." hexmask.long 0x4 0.--31. 1. "Reserved_1,Reserved_1" group.long 0x610++0x1F line.long 0x0 "RGX_CR_PDS_EXEC_BASE_0,Base Address in memory where the PDS programs are located" hexmask.long.word 0x0 20.--31. 1. "ADDR,1TB addressable 1 MB aligned base address for PDS programs" newline hexmask.long.tbyte 0x0 0.--19. 1. "Reserved_0,Reserved_0" line.long 0x4 "RGX_CR_PDS_EXEC_BASE_1,Base Address in memory where the PDS programs are located" hexmask.long.tbyte 0x4 8.--31. 1. "Reserved_40,Reserved_40" newline hexmask.long.byte 0x4 0.--7. 1. "ADDR,1TB addressable 1 MB aligned base address for PDS programs" line.long 0x8 "RGX_CR_EVENT_PIXEL_PDS_CODE_0,RGX_CR_EVENT_PIXEL_PDS_CODE_0" hexmask.long 0x8 4.--31. 1. "ADDR,PDS Execution Address for pixel tasks (Positioned as a byte address 128 bit granularity) 4 GB Range" newline hexmask.long.byte 0x8 0.--3. 1. "Reserved_0,Reserved_0" line.long 0xC "RGX_CR_EVENT_PIXEL_PDS_CODE_1,RGX_CR_EVENT_PIXEL_PDS_CODE_1" hexmask.long 0xC 0.--31. 1. "Reserved_32,Reserved_32" line.long 0x10 "RGX_CR_EVENT_PIXEL_PDS_DATA_0,RGX_CR_EVENT_PIXEL_PDS_DATA_0" hexmask.long 0x10 4.--31. 1. "ADDR,PDS Execution Address for pixel tasks (Positioned as a byte address 128 bit granularity) 4 GB Range" newline hexmask.long.byte 0x10 0.--3. 1. "Reserved_0,Reserved_0" line.long 0x14 "RGX_CR_EVENT_PIXEL_PDS_DATA_1,RGX_CR_EVENT_PIXEL_PDS_DATA_1" hexmask.long 0x14 0.--31. 1. "Reserved_32,Reserved_32" line.long 0x18 "RGX_CR_EVENT_PIXEL_PDS_INFO_0,RGX_CR_EVENT_PIXEL_PDS_INFO_0" hexmask.long.tbyte 0x18 15.--31. 1. "Reserved_15,Reserved_15" newline hexmask.long.byte 0x18 9.--14. 1. "USC_SR_SIZE,USC Shared Register Data Size in 4x128 bit words (0=0) for pixel event task if zero pixel event task is skipped" newline hexmask.long.byte 0x18 5.--8. 1. "TEMP_STRIDE,PDS Temp Size in 128 bit words (0=0) for pixel event tasks" newline hexmask.long.byte 0x18 0.--4. 1. "CONST_SIZE,PDS Data Size in 128 bit words (0=0) for pixel event tasks if zero pixel event task is skipped" line.long 0x1C "RGX_CR_EVENT_PIXEL_PDS_INFO_1,RGX_CR_EVENT_PIXEL_PDS_INFO_1" hexmask.long 0x1C 0.--31. 1. "Reserved_15,Reserved_15" wgroup.long 0x630++0x7 line.long 0x0 "RGX_CR_PDS_CSRM_0,A write of '1' to this register clears the PDS Common Store Resource Manager Contents The PDS CSRM is a cross-DM controller. meaning this register must not be written during any active TA. 3D or Compute phase. This register must be.." hexmask.long 0x0 1.--31. 1. "Reserved_1,Reserved_1" newline bitfld.long 0x0 0. "CLEAR,Clear PDS Common Store Resource Manager a write to this register results in a one cycle pulse" "0,1" line.long 0x4 "RGX_CR_PDS_CSRM_1,A write of '1' to this register clears the PDS Common Store Resource Manager Contents The PDS CSRM is a cross-DM controller. meaning this register must not be written during any active TA. 3D or Compute phase. This register must be.." hexmask.long 0x4 0.--31. 1. "Reserved_1,Reserved_1" group.long 0x638++0xF line.long 0x0 "RGX_CR_PDS_MAX_CSRM_CHUNKS_0,Soft Limit Registers for Maximum Allocation Chunks in the Common Store on a Data Master basis. 1024 Allocation Regions exist in the Common Store. Each Allocation Region or Chunk represetns 4x128-bits of space in the Common.." hexmask.long.byte 0x0 27.--31. 1. "Reserved_27,Reserved_27" newline hexmask.long.word 0x0 18.--26. 1. "CDM,Max Number of Allocation Regions to Allocate to the Compute Data Master in Common Store" newline hexmask.long.word 0x0 9.--17. 1. "PDM,Max Number of Allocation Regions to Allocate to the Pixel Data Master in Common Store" newline hexmask.long.word 0x0 0.--8. 1. "VDM,Max Number of Allocation Regions to Allocate to the VDM Data Master in Common Store" line.long 0x4 "RGX_CR_PDS_MAX_CSRM_CHUNKS_1,Soft Limit Registers for Maximum Allocation Chunks in the Common Store on a Data Master basis. 1024 Allocation Regions exist in the Common Store. Each Allocation Region or Chunk represetns 4x128-bits of space in the Common.." hexmask.long 0x4 0.--31. 1. "Reserved_27,Reserved_27" line.long 0x8 "RGX_CR_PDS_CSRM_MAX_COEFF_0,The Common Store contains Coefficients and Shared Registers in a maximum of n Lines of 64 Allocation Chunks numbered 0-19. Allocated Dynamically. This Register sets a Soft Limit for the Maximum Line to Allocate for use as a.." hexmask.long 0x8 6.--31. 1. "Reserved_6,Reserved_6" newline hexmask.long.byte 0x8 1.--5. 1. "LINE,Coefficients are allocated from Line 0 upwards this is the maximum Line to use for Coefficients before wrapping" newline bitfld.long 0x8 0. "LINE_ENABLE,Enable Max Coefficient Line Limit" "0,1" line.long 0xC "RGX_CR_PDS_CSRM_MAX_COEFF_1,The Common Store contains Coefficients and Shared Registers in a maximum of n Lines of 64 Allocation Chunks numbered 0-19. Allocated Dynamically. This Register sets a Soft Limit for the Maximum Line to Allocate for use as a.." hexmask.long 0xC 0.--31. 1. "Reserved_6,Reserved_6" wgroup.long 0x648++0x7 line.long 0x0 "RGX_CR_PDS_USRM_0,A write of '1' to this register clears the PDS Unified Store Resource Manager Contents. The PDS Unified Store Resource Manager only applies to the vertex and compute data masters. This register must be written during the core.." hexmask.long 0x0 1.--31. 1. "Reserved_1,Reserved_1" newline bitfld.long 0x0 0. "CLEAR,Clear PDS Unified Store Resource Manager a write to this register results in a one cycle pulse" "0,1" line.long 0x4 "RGX_CR_PDS_USRM_1,A write of '1' to this register clears the PDS Unified Store Resource Manager Contents. The PDS Unified Store Resource Manager only applies to the vertex and compute data masters. This register must be written during the core.." hexmask.long 0x4 0.--31. 1. "Reserved_1,Reserved_1" group.long 0x650++0xF line.long 0x0 "RGX_CR_PDS_MAX_USRM_CHUNKS_0,Soft Limit Registers for Maximum Allocation Chunks in the Unified Store on a Data Master basis. 400 Allocation Regions exist in the Unified Store. Each Allocation Region represents 4x128-bits of space in the Unified Store." hexmask.long.word 0x0 18.--31. 1. "Reserved_18,Reserved_18" newline hexmask.long.word 0x0 9.--17. 1. "CDM,Max Number of Allocation Regions to Allocate to the Compute Data Master in Unified Store" newline hexmask.long.word 0x0 0.--8. 1. "VDM,Max Number of Allocation Regions to Allocate to the VDM Data Master in Unified Store" line.long 0x4 "RGX_CR_PDS_MAX_USRM_CHUNKS_1,Soft Limit Registers for Maximum Allocation Chunks in the Unified Store on a Data Master basis. 400 Allocation Regions exist in the Unified Store. Each Allocation Region represents 4x128-bits of space in the Unified Store." hexmask.long 0x4 0.--31. 1. "Reserved_18,Reserved_18" line.long 0x8 "RGX_CR_PDS_USRM_MAX_TEMP_0,The Unified Store contains Temporaries and Attributes in n Lines of 16 Allocation Chunks numbered 0- n-1. Allocated Dynamically. This Register sets a Soft Limit for the Maximum Line to Allocate for use as a Temporaries Line.." hexmask.long 0x8 5.--31. 1. "Reserved_5,Reserved_5" newline hexmask.long.byte 0x8 1.--4. 1. "LINE,Max Line for use as Temporaries" newline bitfld.long 0x8 0. "LINE_ENABLE,Enable Max Temporaries Line Limit" "0,1" line.long 0xC "RGX_CR_PDS_USRM_MAX_TEMP_1,The Unified Store contains Temporaries and Attributes in n Lines of 16 Allocation Chunks numbered 0- n-1. Allocated Dynamically. This Register sets a Soft Limit for the Maximum Line to Allocate for use as a Temporaries Line.." hexmask.long 0xC 0.--31. 1. "Reserved_5,Reserved_5" wgroup.long 0x660++0x7 line.long 0x0 "RGX_CR_PDS_UVSRM_0,A write of '1' to this register clears the PDS Unified Vertex Store Resource Manager Contents The UVS Resource Manager only applies to the vertex data master. This register must be written during the core initialisation sequence." hexmask.long 0x0 1.--31. 1. "Reserved_1,Reserved_1" newline bitfld.long 0x0 0. "CLEAR,Clear PDS Unified Vertex Store Resource Manager a write to this register results in a one cycle pulse" "0,1" line.long 0x4 "RGX_CR_PDS_UVSRM_1,A write of '1' to this register clears the PDS Unified Vertex Store Resource Manager Contents The UVS Resource Manager only applies to the vertex data master. This register must be written during the core initialisation sequence." hexmask.long 0x4 0.--31. 1. "Reserved_1,Reserved_1" group.long 0x668++0x7 line.long 0x0 "RGX_CR_MCU_FBTC_ICTRL_0,MCU Framebuffer Tile Cache Invalidate Control" hexmask.long 0x0 4.--31. 1. "Reserved_4,Reserved_4" newline bitfld.long 0x0 3. "COMP_DM,When set to 1 all entries in the tile cache that have been tagged as a compute data master will be invalidate when PENDING is set" "0,1" newline bitfld.long 0x0 2. "VERTEX_DM,When set to 1 all entries in the tile cache that have been tagged as a vertex data master will be invalidate when PENDING is set" "0,1" newline bitfld.long 0x0 1. "PIXEL_DM,When set to 1 all entries in the tile cache that have been tagged as a pixel data master will be invalidate when PENDING is set" "0,1" newline bitfld.long 0x0 0. "PENDING,When written to 1 will invalidate the header cache in the FBDC when read as 1 invalidate is in progress when read as 0 invalidate is complete" "0,1" line.long 0x4 "RGX_CR_MCU_FBTC_ICTRL_1,MCU Framebuffer Tile Cache Invalidate Control" hexmask.long 0x4 0.--31. 1. "Reserved_4,Reserved_4" wgroup.long 0x670++0x7 line.long 0x0 "RGX_CR_PDS_STORERM_0,A write of '1' to this register clears the PDS Store Resource Manager Contents. The PDS Store Resource Manager is a cross-DM controller. meaning this register must not be written during any active TA. 3D or Compute phase. This.." hexmask.long 0x0 1.--31. 1. "Reserved_1,Reserved_1" newline bitfld.long 0x0 0. "CLEAR,Clear PDS Store Resource Manager a write to this register results in a one cycle pulse" "0,1" line.long 0x4 "RGX_CR_PDS_STORERM_1,A write of '1' to this register clears the PDS Store Resource Manager Contents. The PDS Store Resource Manager is a cross-DM controller. meaning this register must not be written during any active TA. 3D or Compute phase. This.." hexmask.long 0x4 0.--31. 1. "Reserved_1,Reserved_1" group.long 0x678++0x27 line.long 0x0 "RGX_CR_PDS_MAX_STORERM_CHUNKS_0,Soft Limit Registers for Maximum Allocation Chunks in the PDS Store on a Data Master basis. 488 Allocation Regions exist in the PDS Store. Each Allocation Chunk/Region represents 8x64-bits of space in the PDS Store." hexmask.long.byte 0x0 27.--31. 1. "STM,Max Number of Allocation Regions to Allocate to the Stream Out Data Master in PDS Store" newline hexmask.long.word 0x0 18.--26. 1. "CDM,Max Number of Allocation Regions to Allocate to the Compute Data Master in PDS Store" newline hexmask.long.word 0x0 9.--17. 1. "PDM,Max Number of Allocation Regions to Allocate to the Pixel Data Master in PDS Store" newline hexmask.long.word 0x0 0.--8. 1. "VDM,Max Number of Allocation Regions to Allocate to the VDM Data Master in PDS Store" line.long 0x4 "RGX_CR_PDS_MAX_STORERM_CHUNKS_1,Soft Limit Registers for Maximum Allocation Chunks in the PDS Store on a Data Master basis. 488 Allocation Regions exist in the PDS Store. Each Allocation Chunk/Region represents 8x64-bits of space in the PDS Store." hexmask.long 0x4 4.--31. 1. "Reserved_36,Reserved_36" newline hexmask.long.byte 0x4 0.--3. 1. "STM,Max Number of Allocation Regions to Allocate to the Stream Out Data Master in PDS Store" line.long 0x8 "RGX_CR_PDS_STORERM_MAX_TEMP_0,The PDS Store Resource Manager contains Temporaries and Constants in 8 Lines of 64 Allocation Chunks each numbered 0-7. Allocated Dynamically. This Register sets a Soft Limit for the Maximum Line to Allocate for use as a.." hexmask.long 0x8 4.--31. 1. "Reserved_4,Reserved_4" newline bitfld.long 0x8 1.--3. "LINE,Temporaries are allocated from Line 0 upwards this is the maximum Line to use for Temporaries before wrapping" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 0. "LINE_ENABLE,Enable Max Temporaries Line Limit" "0,1" line.long 0xC "RGX_CR_PDS_STORERM_MAX_TEMP_1,The PDS Store Resource Manager contains Temporaries and Constants in 8 Lines of 64 Allocation Chunks each numbered 0-7. Allocated Dynamically. This Register sets a Soft Limit for the Maximum Line to Allocate for use as a.." hexmask.long 0xC 0.--31. 1. "Reserved_4,Reserved_4" line.long 0x10 "RGX_CR_PDS_ICC_INVAL_0,A write of '1' any bit to this register clears the PDS Instruction Cache for the selected DM The PDS HW will clear the bits when the operations complete" hexmask.long 0x10 6.--31. 1. "Reserved_6,Reserved_6" newline bitfld.long 0x10 5. "FASTRENDER_PENDING,PDS Instruction Cache Fastrender (DM 6) has been invalidated" "0,1" newline bitfld.long 0x10 3.--4. "Reserved_3,Reserved_3" "0,1,2,3" newline bitfld.long 0x10 2. "COMPUTE_PENDING,PDS Instruction Cache Compute (DM 2) has been invalidated" "0,1" newline bitfld.long 0x10 1. "PIXEL_PENDING,PDS Instruction Cache Pixel (DM 1) has been invalidated" "0,1" newline bitfld.long 0x10 0. "VERTEX_PENDING,PDS Instruction Cache Vertex (DM 0) has been invalidated" "0,1" line.long 0x14 "RGX_CR_PDS_ICC_INVAL_1,A write of '1' any bit to this register clears the PDS Instruction Cache for the selected DM The PDS HW will clear the bits when the operations complete" hexmask.long 0x14 0.--31. 1. "Reserved_6,Reserved_6" line.long 0x18 "RGX_CR_PDS_MCU_REQ_CTRL_0,The PDS makes requests to the MCU to DMA to the PDS store and write data to memory. This register defines the various cache modes that apply to those requests." hexmask.long 0x18 4.--31. 1. "Reserved_4,Reserved_4" newline bitfld.long 0x18 2.--3. "SMODE,SLC cache policy to use for requests from the VDM/PDM/CDM/STM resource requestors inside the PDS" "0,1,2,3" newline bitfld.long 0x18 0.--1. "CMODE,Cache Mode to use for requests from the VDM/PDM/CDM/STM resource requestors inside the PDS" "0,1,2,3" line.long 0x1C "RGX_CR_PDS_MCU_REQ_CTRL_1,The PDS makes requests to the MCU to DMA to the PDS store and write data to memory. This register defines the various cache modes that apply to those requests." hexmask.long 0x1C 0.--31. 1. "Reserved_4,Reserved_4" line.long 0x20 "RGX_CR_PDS_CSRM_MIN_SHARED_0,The Common Store contains Coefficients and Shared Registers in 14 Lines of 64 Allocation Chunks numbered 0-13. Allocated Dynamically. This Register sets a Soft Limit for the Minimum Line to Allocate for use as a Shared Line.." hexmask.long 0x20 6.--31. 1. "Reserved_6,Reserved_6" newline hexmask.long.byte 0x20 1.--5. 1. "LINE,Shared are allocated from top line downwards this is the minimum Line to use for Shared Registers before wrapping" newline bitfld.long 0x20 0. "LINE_ENABLE,Enable Min Shared Register Line Limit" "0,1" line.long 0x24 "RGX_CR_PDS_CSRM_MIN_SHARED_1,The Common Store contains Coefficients and Shared Registers in 14 Lines of 64 Allocation Chunks numbered 0-13. Allocated Dynamically. This Register sets a Soft Limit for the Minimum Line to Allocate for use as a Shared Line.." hexmask.long 0x24 0.--31. 1. "Reserved_6,Reserved_6" repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) group.long ($2+0x6A0)++0x3 line.long 0x0 "RGX_CR_PDS_BGRND0_BASE_$1,PDS Background Setup Word 0" hexmask.long 0x0 4.--31. 1. "SHADER_ADDR,The pixel shader base is the base address of the PDS Data Segment. The code segment is address is PDS_PIXEL_SHADERBASE + PDS_PIXELSHADERSIZE. The pixel shader program issues the DOUTU for the Fragment Shader only." newline hexmask.long.byte 0x0 0.--3. 1. "Reserved_0,Reserved_0" repeat.end repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) group.long ($2+0x6A8)++0x3 line.long 0x0 "RGX_CR_PDS_BGRND1_BASE_$1,PDS Background Setup Word 1" hexmask.long 0x0 4.--31. 1. "VARYING_ADDR,This is the base address of the PDS Data Segment. The code segment is address is PDS_VARYINGBASE + PDS_VARYINGSIZE (PDS_BGRND_SIZEINFO1)." newline hexmask.long.byte 0x0 0.--3. 1. "Reserved_0,Reserved_0" repeat.end group.long 0x6B0++0x37 line.long 0x0 "RGX_CR_PDS_BGRND2_BASE_0,PDS Background Setup Word 2" hexmask.long 0x0 4.--31. 1. "UNIFORMDATA_ADDR,This points to the DMAs to load the Uniforms (or contains the Uniforms with DOUTW commands)" newline hexmask.long.byte 0x0 0.--3. 1. "Reserved_0,Reserved_0" line.long 0x4 "RGX_CR_PDS_BGRND2_BASE_1,PDS Background Setup Word 2" hexmask.long 0x4 0.--31. 1. "Reserved_32,Reserved_32" line.long 0x8 "RGX_CR_PDS_BGRND3_SIZEINFO_0,If any of the size fields are 0. then that program will not be run. PDS_BGRND_PIXELSHADERSIZE is always 2 128 Bit Words" hexmask.long.word 0x8 23.--31. 1. "PDS_UNIFORMSIZE,The size of the Uniform PDS Data Segment in 128 bit words" newline hexmask.long.byte 0x8 16.--22. 1. "PDS_TEXTURESTATESIZE,The size of the Texture PDS Data Segment in 128 bit words" newline hexmask.long.byte 0x8 10.--15. 1. "PDS_VARYINGSIZE,The size of the Varying/Coefficient PDS Data Segment in 128 bit words" newline hexmask.long.byte 0x8 4.--9. 1. "USC_VARYINGSIZE,The size of the Varying/Coefficient USC Common Store Data in 4x128 bit words" newline hexmask.long.byte 0x8 0.--3. 1. "PDS_TEMPSIZE,0 = 0 128 bit words 1 = 1 128 bit word this applies to coefficient uniform and varying state" line.long 0xC "RGX_CR_PDS_BGRND3_SIZEINFO_1,If any of the size fields are 0. then that program will not be run. PDS_BGRND_PIXELSHADERSIZE is always 2 128 Bit Words" hexmask.long.word 0xC 23.--31. 1. "USC_SHAREDSIZE,The common store allocation size for the shared registers (texture and uniform data commbined)" newline hexmask.long.word 0xC 14.--22. 1. "Reserved_46,Reserved_46" newline hexmask.long.word 0xC 0.--13. 1. "PDS_BATCHNUM,The batch ID to be associated with the background" line.long 0x10 "RGX_CR_PDS_USRM_MIN_ATTR_0,The Unified Store contains Temporaries and Attributes in n Lines of 16 Allocation Chunks numbered 0 - n-1. Allocated Dynamically. This Register sets a Soft Limit for the Minimum Line to Allocate for use as an Attribute Line.." hexmask.long 0x10 5.--31. 1. "Reserved_5,Reserved_5" newline hexmask.long.byte 0x10 1.--4. 1. "LINE,Min Line for use for Attributes" newline bitfld.long 0x10 0. "LINE_ENABLE,Enable Min Attributes Line Limit" "0,1" line.long 0x14 "RGX_CR_PDS_USRM_MIN_ATTR_1,The Unified Store contains Temporaries and Attributes in n Lines of 16 Allocation Chunks numbered 0 - n-1. Allocated Dynamically. This Register sets a Soft Limit for the Minimum Line to Allocate for use as an Attribute Line.." hexmask.long 0x14 0.--31. 1. "Reserved_5,Reserved_5" line.long 0x18 "RGX_CR_PDS_STORERM_MIN_CONST_0,The PDS Store Resource Manager contains Temporaries and Constants in 8 Lines of 64 Allocation Chunks each numbered 0-7. Allocated Dynamically. This Register sets a Soft Limit for the Minimum Line to Allocate for use as a.." hexmask.long 0x18 4.--31. 1. "Reserved_4,Reserved_4" newline bitfld.long 0x18 1.--3. "LINE,Constants are allocated from Line 7 down this is the minimum Line to use for Constants before wrapping" "0,1,2,3,4,5,6,7" newline bitfld.long 0x18 0. "LINE_ENABLE,Enable Min Constants Line Limit" "0,1" line.long 0x1C "RGX_CR_PDS_STORERM_MIN_CONST_1,The PDS Store Resource Manager contains Temporaries and Constants in 8 Lines of 64 Allocation Chunks each numbered 0-7. Allocated Dynamically. This Register sets a Soft Limit for the Minimum Line to Allocate for use as a.." hexmask.long 0x1C 0.--31. 1. "Reserved_4,Reserved_4" line.long 0x20 "RGX_CR_PDS_PIXELMERGE_0,RGX_CR_PDS_PIXELMERGE_0" hexmask.long 0x20 7.--31. 1. "Reserved_7,Reserved_7" newline bitfld.long 0x20 6. "TASK_DISABLE,Disable pixel merging within a whole pixel fragment task" "0,1" newline bitfld.long 0x20 5. "DISABLE,Disable pixel merging within each 2x2 pixel block of a pixel fragment task" "0,1" newline hexmask.long.byte 0x20 0.--4. 1. "GRADLIMIT,Gradient difference limit for PDS PP pixel merging" line.long 0x24 "RGX_CR_PDS_PIXELMERGE_1,RGX_CR_PDS_PIXELMERGE_1" hexmask.long 0x24 0.--31. 1. "Reserved_7,Reserved_7" line.long 0x28 "RGX_CR_PDS_CSRM_USC_DEBUG_0,When written a non zero value. this register assigns an extra degree of space to be allocated in the Common Store via the PDS CSRM for USC debugging on Shared Allocations. The SIZE field is Allocation Region Granular (i.e.." hexmask.long 0x28 5.--31. 1. "Reserved_5,Reserved_5" newline hexmask.long.byte 0x28 0.--4. 1. "SIZE,Amount of Space (in 512-bit Allocation Regions) to allocate to USC Debug Space on a Shared Allocation." line.long 0x2C "RGX_CR_PDS_CSRM_USC_DEBUG_1,When written a non zero value. this register assigns an extra degree of space to be allocated in the Common Store via the PDS CSRM for USC debugging on Shared Allocations. The SIZE field is Allocation Region Granular (i.e.." hexmask.long 0x2C 0.--31. 1. "Reserved_5,Reserved_5" line.long 0x30 "RGX_CR_PDS_CSRM_DISABLE_0,When this register is set. the CSRM will be configured on PDS CSRM CLEAR to not reserve any space for Partitions (this is normally governed by the AA MODE and PIXEL OUTPUT CTRL WIDTH register settings). to maximise space in the.." hexmask.long 0x30 3.--31. 1. "Reserved_3,Reserved_3" newline bitfld.long 0x30 2. "COEFF_SLIDE,Disable Slide of Coeff Allocations on Failure" "0,1" newline bitfld.long 0x30 1. "SHARED_SLIDE,Disable Slide of Shared Allocations on Failure" "0,1" newline bitfld.long 0x30 0. "PARTITIONS,Disable Partition Space Reservation in the CSRM" "0,1" line.long 0x34 "RGX_CR_PDS_CSRM_DISABLE_1,When this register is set. the CSRM will be configured on PDS CSRM CLEAR to not reserve any space for Partitions (this is normally governed by the AA MODE and PIXEL OUTPUT CTRL WIDTH register settings). to maximise space in the.." hexmask.long 0x34 0.--31. 1. "Reserved_3,Reserved_3" rgroup.long 0x6E8++0x7 line.long 0x0 "RGX_CR_HUB_IDLE_0,RGX_CR_HUB_IDLE_0" hexmask.long 0x0 4.--31. 1. "Reserved_4,Reserved_4" newline bitfld.long 0x0 3. "TDM,TDM Module IDLE" "0,1" newline bitfld.long 0x0 2. "CDM,CDM Module IDLE" "0,1" newline bitfld.long 0x0 1. "VDM,VDM Module IDLE" "0,1" newline bitfld.long 0x0 0. "PDS,PDS Module IDLE" "0,1" line.long 0x4 "RGX_CR_HUB_IDLE_1,RGX_CR_HUB_IDLE_1" hexmask.long 0x4 0.--31. 1. "Reserved_4,Reserved_4" repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) rgroup.long ($2+0x6F0)++0x3 line.long 0x0 "RGX_CR_HUB_PWR_$1,RGX_CR_HUB_PWR_0" hexmask.long 0x0 0.--31. 1. "NUM_PDS_INST,Number of PDS instructions" repeat.end group.long 0x700++0xF line.long 0x0 "RGX_CR_PDS_PASSGROUP_0,RGX_CR_PDS_PASSGROUP_0" hexmask.long 0x0 2.--31. 1. "Reserved_2,Reserved_2" newline bitfld.long 0x0 1. "FORCE_PT,Force the use of Hard SDs between punchthrough or depth feedback type passes" "0,1" newline bitfld.long 0x0 0. "ENABLE,Enable pass group optimisation within USC by replacing USC Hard SDs with USC Soft SDs for all pass groups in the PDS PP." "0,1" line.long 0x4 "RGX_CR_PDS_PASSGROUP_1,RGX_CR_PDS_PASSGROUP_1" hexmask.long 0x4 0.--31. 1. "Reserved_2,Reserved_2" line.long 0x8 "RGX_CR_PDS_COMPUTE_THREAD_BARRIER_0,RGX_CR_PDS_COMPUTE_THREAD_BARRIER_0" hexmask.long 0x8 1.--31. 1. "Reserved_1,Reserved_1" newline bitfld.long 0x8 0. "ENABLE,Enable thread barrier support in the PDS CDM_RR." "0,1" line.long 0xC "RGX_CR_PDS_COMPUTE_THREAD_BARRIER_1,RGX_CR_PDS_COMPUTE_THREAD_BARRIER_1" hexmask.long 0xC 0.--31. 1. "Reserved_1,Reserved_1" group.long 0x720++0x7 line.long 0x0 "RGX_CR_PDS_CSRM_SETUP_0,If the ENABLE field is set. then when the PDS CSRM is Cleared via the PDS_CSRM_CLEAR register. the value set in the MAX_LINE vector is used to define the maximum Line in the CSRM which is allocatable to Shared.." hexmask.long 0x0 6.--31. 1. "Reserved_6,Reserved_6" newline bitfld.long 0x0 5. "HALF,Top line is prefilled half full" "0,1" newline hexmask.long.byte 0x0 1.--4. 1. "MAX_LINE,(Lower 4 bits of) Maximum Line within the CSRM that can be allocated to Shared Registers/Coefficients" newline bitfld.long 0x0 0. "ENABLE,Enable use of this register to set the Maximum Line the CSRM can allocate on behalf of the USC Common Store" "0,1" line.long 0x4 "RGX_CR_PDS_CSRM_SETUP_1,If the ENABLE field is set. then when the PDS CSRM is Cleared via the PDS_CSRM_CLEAR register. the value set in the MAX_LINE vector is used to define the maximum Line in the CSRM which is allocatable to Shared.." hexmask.long 0x4 0.--31. 1. "Reserved_6,Reserved_6" group.long 0x738++0x7 line.long 0x0 "RGX_CR_PDS_USRM_DISABLE_0,When this register is set. the USRM will be configured on PDS USRM CLEAR to disable the Temp/Attribute slide functionality which allows a Temporaries or Attributes allocation which fails to slide the allocation window. The.." hexmask.long 0x0 1.--31. 1. "Reserved_1,Reserved_1" newline bitfld.long 0x0 0. "TEMP_SLIDE,Disable Slide of Temp Allocations on Failure" "0,1" line.long 0x4 "RGX_CR_PDS_USRM_DISABLE_1,When this register is set. the USRM will be configured on PDS USRM CLEAR to disable the Temp/Attribute slide functionality which allows a Temporaries or Attributes allocation which fails to slide the allocation window. The.." hexmask.long 0x4 0.--31. 1. "Reserved_1,Reserved_1" group.long 0x788++0xF line.long 0x0 "RGX_CR_PDS_CSRM_PIXEL_0,The Common Store contains Coefficients and Shared Registers in a maximum of n Lines of 64 Allocation Chunks numbered 0-31. Allocated Dynamically. This Register sets a Soft Limit for the Maximum Line of available Coefficient space." hexmask.long 0x0 6.--31. 1. "Reserved_6,Reserved_6" newline hexmask.long.byte 0x0 1.--5. 1. "MAX_LINE,Coefficients are allocated from Line 0 upwards this is the maximum Line to reserve for ONLY PDM Coefficients. The Max line of this region is set in the PDS_CSRM_MAX_COEFF register" newline bitfld.long 0x0 0. "MODE_ENABLE,Enable PIXEL RESERVE MODE in the PDS CSRM" "0,1" line.long 0x4 "RGX_CR_PDS_CSRM_PIXEL_1,The Common Store contains Coefficients and Shared Registers in a maximum of n Lines of 64 Allocation Chunks numbered 0-31. Allocated Dynamically. This Register sets a Soft Limit for the Maximum Line of available Coefficient space." hexmask.long 0x4 0.--31. 1. "Reserved_6,Reserved_6" line.long 0x8 "RGX_CR_PDS_MAX_STORERM_CHUNKS2_0,Soft Limit Registers for Maximum Allocation Chunks in the PDS Store on a Data Master basis. 488 Allocation Regions exist in the PDS Store. Each Allocation Chunk/Region represents 8x64-bits of space in the PDS Store." hexmask.long.tbyte 0x8 9.--31. 1. "Reserved_9,Reserved_9" newline hexmask.long.word 0x8 0.--8. 1. "TDM,Max Number of Allocation Regions to Allocate to the Fastrender Data Master in PDS Store" line.long 0xC "RGX_CR_PDS_MAX_STORERM_CHUNKS2_1,Soft Limit Registers for Maximum Allocation Chunks in the PDS Store on a Data Master basis. 488 Allocation Regions exist in the PDS Store. Each Allocation Chunk/Region represents 8x64-bits of space in the PDS Store." hexmask.long 0xC 0.--31. 1. "Reserved_9,Reserved_9" group.long 0x800++0x67 line.long 0x0 "RGX_CR_SIDEKICK_EXT_MEM_ARB_CONFIG_0,This register contains the configuration options for the Sidekick external memory arbiter." hexmask.long 0x0 2.--31. 1. "Reserved_2,Reserved_2" newline bitfld.long 0x0 0.--1. "ARB_PRIO_MODE,Priority mode for external memory access arbiter between GPU scheduler and SLC" "0,1,2,3" line.long 0x4 "RGX_CR_SIDEKICK_EXT_MEM_ARB_CONFIG_1,This register contains the configuration options for the Sidekick external memory arbiter." hexmask.long 0x4 0.--31. 1. "Reserved_2,Reserved_2" line.long 0x8 "RGX_CR_MIPS_WRAPPER_FENCE_0,When writing to this register. the MIPS wrapper holds further transaction from MIPS and emits a memory fence onto the bus" hexmask.long 0x8 1.--31. 1. "Reserved_1,Reserved_1" newline bitfld.long 0x8 0. "SYS_FENCE_ID,reserved address identifier for system fence events" "0,1" line.long 0xC "RGX_CR_MIPS_WRAPPER_FENCE_1,When writing to this register. the MIPS wrapper holds further transaction from MIPS and emits a memory fence onto the bus" hexmask.long 0xC 0.--31. 1. "Reserved_1,Reserved_1" line.long 0x10 "RGX_CR_MIPS_WRAPPER_CONFIG_0,This register contains the configuration options for the MIPS CPU wrapper." hexmask.long.byte 0x10 28.--31. 1. "Reserved_28,Reserved_28" newline bitfld.long 0x10 25.--27. "OS_ID,The default OS_ID of the firmware" "0,1,2,3,4,5,6,7" newline bitfld.long 0x10 24. "TRUSTED,Defines whether these accesses are trusted" "0,1" newline hexmask.long.byte 0x10 17.--23. 1. "Reserved_17,Reserved_17" newline bitfld.long 0x10 16. "BOOT_ISA_MODE,MIPS boot up mode. When set to 0 boot from MIPS32 mode or set to 1 to boot in microMIPS mode" "0,1" newline hexmask.long.word 0x10 0.--15. 1. "REGBANK_BASE_ADDR,16-bit aligned address that identifies rgx register bank transactions emitted from the MIPS core" line.long 0x14 "RGX_CR_MIPS_WRAPPER_CONFIG_1,This register contains the configuration options for the MIPS CPU wrapper." hexmask.long.tbyte 0x14 9.--31. 1. "Reserved_41,Reserved_41" newline bitfld.long 0x14 8. "FW_IDLE_ENABLE,Set to 0x0 overwrites the value of GPU_IDLE to 0x0 set to 0x1 makes GPU Idle dependent on top level idles" "0,1" newline hexmask.long.byte 0x14 2.--7. 1. "Reserved_34,Reserved_34" newline bitfld.long 0x14 1. "DISABLE_BOOT,Stop the MIPS from boot-up even after a soft reset is triggered" "0,1" newline bitfld.long 0x14 0. "L2_CACHE_OFF,Turn off the L2 cache within the MIPS wrapper" "0,1" line.long 0x18 "RGX_CR_MIPS_ADDR_REMAP1_CONFIG1_0,This register contains the address remapping options for the MIPS CPU physical address. e.g. during boot" hexmask.long.tbyte 0x18 12.--31. 1. "BASE_ADDR_IN,4K (12 bits) aligned address used as a input for the address remapping" newline hexmask.long.word 0x18 1.--11. 1. "Reserved_1,Reserved_1" newline bitfld.long 0x18 0. "MODE_ENABLE,Enable address remapping mode" "0,1" line.long 0x1C "RGX_CR_MIPS_ADDR_REMAP1_CONFIG1_1,This register contains the address remapping options for the MIPS CPU physical address. e.g. during boot" hexmask.long 0x1C 0.--31. 1. "Reserved_32,Reserved_32" line.long 0x20 "RGX_CR_MIPS_ADDR_REMAP1_CONFIG2_0,This register contains the address remapping options for the MIPS CPU physical address. e.g. during boot" hexmask.long.tbyte 0x20 12.--31. 1. "ADDR_OUT,4K (12 bits) aligned address used as output for the address remapping" newline bitfld.long 0x20 9.--11. "Reserved_9,Reserved_9" "0,1,2,3,4,5,6,7" newline bitfld.long 0x20 6.--8. "OS_ID,The OS_ID emitted for all address transactions from this region" "0,1,2,3,4,5,6,7" newline bitfld.long 0x20 5. "TRUSTED,Defines whether these accesses are trusted" "0,1" newline hexmask.long.byte 0x20 0.--4. 1. "REGION_SIZE_POW2,Remapped region size or offset size i.e. number of bits from the bottom of the base input address that survive onto the output address. Minimum value of 12" line.long 0x24 "RGX_CR_MIPS_ADDR_REMAP1_CONFIG2_1,This register contains the address remapping options for the MIPS CPU physical address. e.g. during boot" hexmask.long.tbyte 0x24 8.--31. 1. "Reserved_40,Reserved_40" newline hexmask.long.byte 0x24 0.--7. 1. "ADDR_OUT,4K (12 bits) aligned address used as output for the address remapping" line.long 0x28 "RGX_CR_MIPS_ADDR_REMAP2_CONFIG1_0,This register contains the address remapping options for the MIPS CPU physical address. e.g. during boot" hexmask.long.tbyte 0x28 12.--31. 1. "BASE_ADDR_IN,4K (12 bits) aligned address used as a input for the address remapping" newline hexmask.long.word 0x28 1.--11. 1. "Reserved_1,Reserved_1" newline bitfld.long 0x28 0. "MODE_ENABLE,Enable address remapping mode" "0,1" line.long 0x2C "RGX_CR_MIPS_ADDR_REMAP2_CONFIG1_1,This register contains the address remapping options for the MIPS CPU physical address. e.g. during boot" hexmask.long 0x2C 0.--31. 1. "Reserved_32,Reserved_32" line.long 0x30 "RGX_CR_MIPS_ADDR_REMAP2_CONFIG2_0,This register contains the address remapping options for the MIPS CPU physical address. e.g. during boot" hexmask.long.tbyte 0x30 12.--31. 1. "ADDR_OUT,4K (12 bits) aligned address used as output for the address remapping" newline bitfld.long 0x30 9.--11. "Reserved_9,Reserved_9" "0,1,2,3,4,5,6,7" newline bitfld.long 0x30 6.--8. "OS_ID,The OS_ID emitted for all address transactions from this region" "0,1,2,3,4,5,6,7" newline bitfld.long 0x30 5. "TRUSTED,Defines whether these accesses are trusted" "0,1" newline hexmask.long.byte 0x30 0.--4. 1. "REGION_SIZE_POW2,Remapped region size or offset size i.e. number of bits from the bottom of the base input address that survive onto the output address. Minimum value of 12" line.long 0x34 "RGX_CR_MIPS_ADDR_REMAP2_CONFIG2_1,This register contains the address remapping options for the MIPS CPU physical address. e.g. during boot" hexmask.long.tbyte 0x34 8.--31. 1. "Reserved_40,Reserved_40" newline hexmask.long.byte 0x34 0.--7. 1. "ADDR_OUT,4K (12 bits) aligned address used as output for the address remapping" line.long 0x38 "RGX_CR_MIPS_ADDR_REMAP3_CONFIG1_0,This register contains the address remapping options for the MIPS CPU physical address. e.g. during boot" hexmask.long.tbyte 0x38 12.--31. 1. "BASE_ADDR_IN,4K (12 bits) aligned address used as a input for the address remapping" newline hexmask.long.word 0x38 1.--11. 1. "Reserved_1,Reserved_1" newline bitfld.long 0x38 0. "MODE_ENABLE,Enable address remapping mode" "0,1" line.long 0x3C "RGX_CR_MIPS_ADDR_REMAP3_CONFIG1_1,This register contains the address remapping options for the MIPS CPU physical address. e.g. during boot" hexmask.long 0x3C 0.--31. 1. "Reserved_32,Reserved_32" line.long 0x40 "RGX_CR_MIPS_ADDR_REMAP3_CONFIG2_0,This register contains the address remapping options for the MIPS CPU physical address. e.g. during boot" hexmask.long.tbyte 0x40 12.--31. 1. "ADDR_OUT,4K (12 bits) aligned address used as output for the address remapping" newline bitfld.long 0x40 9.--11. "Reserved_9,Reserved_9" "0,1,2,3,4,5,6,7" newline bitfld.long 0x40 6.--8. "OS_ID,The OS_ID emitted for all address transactions from this region" "0,1,2,3,4,5,6,7" newline bitfld.long 0x40 5. "TRUSTED,Defines whether these accesses are trusted" "0,1" newline hexmask.long.byte 0x40 0.--4. 1. "REGION_SIZE_POW2,Remapped region size or offset size i.e. number of bits from the bottom of the base input address that survive onto the output address. Minimum value of 12" line.long 0x44 "RGX_CR_MIPS_ADDR_REMAP3_CONFIG2_1,This register contains the address remapping options for the MIPS CPU physical address. e.g. during boot" hexmask.long.tbyte 0x44 8.--31. 1. "Reserved_40,Reserved_40" newline hexmask.long.byte 0x44 0.--7. 1. "ADDR_OUT,4K (12 bits) aligned address used as output for the address remapping" line.long 0x48 "RGX_CR_MIPS_ADDR_REMAP4_CONFIG1_0,This register contains the address remapping options for the MIPS CPU physical address. e.g. during boot" hexmask.long.tbyte 0x48 12.--31. 1. "BASE_ADDR_IN,4K (12 bits) aligned address used as a input for the address remapping" newline hexmask.long.word 0x48 1.--11. 1. "Reserved_1,Reserved_1" newline bitfld.long 0x48 0. "MODE_ENABLE,Enable address remapping mode" "0,1" line.long 0x4C "RGX_CR_MIPS_ADDR_REMAP4_CONFIG1_1,This register contains the address remapping options for the MIPS CPU physical address. e.g. during boot" hexmask.long 0x4C 0.--31. 1. "Reserved_32,Reserved_32" line.long 0x50 "RGX_CR_MIPS_ADDR_REMAP4_CONFIG2_0,This register contains the address remapping options for the MIPS CPU physical address. e.g. during boot" hexmask.long.tbyte 0x50 12.--31. 1. "ADDR_OUT,4K (12 bits) aligned address used as output for the address remapping" newline bitfld.long 0x50 9.--11. "Reserved_9,Reserved_9" "0,1,2,3,4,5,6,7" newline bitfld.long 0x50 6.--8. "OS_ID,The OS_ID emitted for all address transactions from this region" "0,1,2,3,4,5,6,7" newline bitfld.long 0x50 5. "TRUSTED,Defines whether these accesses are trusted" "0,1" newline hexmask.long.byte 0x50 0.--4. 1. "REGION_SIZE_POW2,Remapped region size or offset size i.e. number of bits from the bottom of the base input address that survive onto the output address. Minimum value of 12" line.long 0x54 "RGX_CR_MIPS_ADDR_REMAP4_CONFIG2_1,This register contains the address remapping options for the MIPS CPU physical address. e.g. during boot" hexmask.long.tbyte 0x54 8.--31. 1. "Reserved_40,Reserved_40" newline hexmask.long.byte 0x54 0.--7. 1. "ADDR_OUT,4K (12 bits) aligned address used as output for the address remapping" line.long 0x58 "RGX_CR_MIPS_ADDR_REMAP5_CONFIG1_0,This register contains the address remapping options for the MIPS CPU physical address. e.g. during boot" hexmask.long.tbyte 0x58 12.--31. 1. "BASE_ADDR_IN,4K (12 bits) aligned address used as a input for the address remapping" newline hexmask.long.word 0x58 1.--11. 1. "Reserved_1,Reserved_1" newline bitfld.long 0x58 0. "MODE_ENABLE,Enable address remapping mode" "0,1" line.long 0x5C "RGX_CR_MIPS_ADDR_REMAP5_CONFIG1_1,This register contains the address remapping options for the MIPS CPU physical address. e.g. during boot" hexmask.long 0x5C 0.--31. 1. "Reserved_32,Reserved_32" line.long 0x60 "RGX_CR_MIPS_ADDR_REMAP5_CONFIG2_0,This register contains the address remapping options for the MIPS CPU physical address. e.g. during boot" hexmask.long.tbyte 0x60 12.--31. 1. "ADDR_OUT,4K (12 bits) aligned address used as output for the address remapping" newline bitfld.long 0x60 9.--11. "Reserved_9,Reserved_9" "0,1,2,3,4,5,6,7" newline bitfld.long 0x60 6.--8. "OS_ID,The OS_ID emitted for all address transactions from this region" "0,1,2,3,4,5,6,7" newline bitfld.long 0x60 5. "TRUSTED,Defines whether these accesses are trusted" "0,1" newline hexmask.long.byte 0x60 0.--4. 1. "REGION_SIZE_POW2,Remapped region size or offset size i.e. number of bits from the bottom of the base input address that survive onto the output address. Minimum value of 12" line.long 0x64 "RGX_CR_MIPS_ADDR_REMAP5_CONFIG2_1,This register contains the address remapping options for the MIPS CPU physical address. e.g. during boot" hexmask.long.tbyte 0x64 8.--31. 1. "Reserved_40,Reserved_40" newline hexmask.long.byte 0x64 0.--7. 1. "ADDR_OUT,4K (12 bits) aligned address used as output for the address remapping" rgroup.long 0x868++0x7 line.long 0x0 "RGX_CR_MIPS_ADDR_REMAP_UNMAPPED_STATUS_0,This register contains the unmapped exception status information of the MIPS GPU scheduler." hexmask.long 0x0 0.--31. 1. "ADDRESS,Unmapped MIPS physical address" line.long 0x4 "RGX_CR_MIPS_ADDR_REMAP_UNMAPPED_STATUS_1,This register contains the unmapped exception status information of the MIPS GPU scheduler." hexmask.long 0x4 1.--31. 1. "Reserved_33,Reserved_33" newline bitfld.long 0x4 0. "EVENT,An address from the MIPS was not remapped to a new range in the GPU" "0,1" wgroup.long 0x870++0x7 line.long 0x0 "RGX_CR_MIPS_ADDR_REMAP_UNMAPPED_CLEAR_0,This register contains the configuration options for the MIPS unmapped exception." hexmask.long 0x0 1.--31. 1. "Reserved_1,Reserved_1" newline bitfld.long 0x0 0. "EVENT,Clears the unmapped exception event" "0,1" line.long 0x4 "RGX_CR_MIPS_ADDR_REMAP_UNMAPPED_CLEAR_1,This register contains the configuration options for the MIPS unmapped exception." hexmask.long 0x4 0.--31. 1. "Reserved_1,Reserved_1" group.long 0x878++0x7 line.long 0x0 "RGX_CR_MIPS_ADDR_REMAP_RANGE_CONFIG_0,This register contains the address remapping options for the MIPS CPU physical address. e.g. during boot" hexmask.long.tbyte 0x0 12.--31. 1. "BASE_ADDR_IN,4K (12 bits) aligned address used as a input for the address remapping" newline bitfld.long 0x0 11. "TRUSTED,Defines whether these accesses are trusted" "0,1" newline hexmask.long.byte 0x0 7.--10. 1. "REGION_SIZE,Remapped region size" newline bitfld.long 0x0 6. "Reserved_6,Reserved_6" "0,1" newline hexmask.long.byte 0x0 1.--5. 1. "ENTRY,Select remap entry to configure. Valid range of Entry 0-31" newline bitfld.long 0x0 0. "MODE_ENABLE,When set configure the entry" "0,1" line.long 0x4 "RGX_CR_MIPS_ADDR_REMAP_RANGE_CONFIG_1,This register contains the address remapping options for the MIPS CPU physical address. e.g. during boot" hexmask.long 0x4 4.--31. 1. "ADDR_OUT,4K (12 bits) aligned address used as output for the address remapping" newline bitfld.long 0x4 3. "Reserved_35,Reserved_35" "0,1" newline bitfld.long 0x4 0.--2. "OS_ID,The OS_ID emitted for all address transactions from this region" "0,1,2,3,4,5,6,7" wgroup.long 0x880++0x7 line.long 0x0 "RGX_CR_MIPS_ADDR_REMAP_RANGE_READ_0,This register contains the configuration options for the MIPS remap register read interface." hexmask.long 0x0 6.--31. 1. "Reserved_6,Reserved_6" newline hexmask.long.byte 0x0 1.--5. 1. "ENTRY,MIPS address remap entry to read" newline bitfld.long 0x0 0. "REQUEST,Issue a read request to the MIPS address remap range entries" "0,1" line.long 0x4 "RGX_CR_MIPS_ADDR_REMAP_RANGE_READ_1,This register contains the configuration options for the MIPS remap register read interface." hexmask.long 0x4 0.--31. 1. "Reserved_6,Reserved_6" rgroup.long 0x888++0x7 line.long 0x0 "RGX_CR_MIPS_ADDR_REMAP_RANGE_DATA_0,This register contains the remapping entry information for the MIPS remap register read interface." hexmask.long.tbyte 0x0 12.--31. 1. "BASE_ADDR_IN,4K (12 bits) aligned address used as a input for the address remapping" newline bitfld.long 0x0 11. "TRUSTED,Defines whether these accesses are trusted" "0,1" newline hexmask.long.byte 0x0 7.--10. 1. "REGION_SIZE,Remapped region size" newline hexmask.long.byte 0x0 1.--6. 1. "Reserved_1,Reserved_1" newline bitfld.long 0x0 0. "MODE_ENABLE,When set configures the entry" "0,1" line.long 0x4 "RGX_CR_MIPS_ADDR_REMAP_RANGE_DATA_1,This register contains the remapping entry information for the MIPS remap register read interface." hexmask.long 0x4 4.--31. 1. "ADDR_OUT,4K (12 bits) aligned address used as output for the address remapping" newline bitfld.long 0x4 3. "Reserved_35,Reserved_35" "0,1" newline bitfld.long 0x4 0.--2. "OS_ID,The OS_ID emitted for all address transactions from this region" "0,1,2,3,4,5,6,7" group.long 0x8A0++0xF line.long 0x0 "RGX_CR_MIPS_WRAPPER_IRQ_ENABLE_0,This register contains the configuration options for the RGX firmware interrupts to HOST." hexmask.long 0x0 1.--31. 1. "Reserved_1,Reserved_1" newline bitfld.long 0x0 0. "EVENT,Allow RGX firmware to send interrupts to HOST" "0,1" line.long 0x4 "RGX_CR_MIPS_WRAPPER_IRQ_ENABLE_1,This register contains the configuration options for the RGX firmware interrupts to HOST." hexmask.long 0x4 0.--31. 1. "Reserved_1,Reserved_1" line.long 0x8 "RGX_CR_MIPS_WRAPPER_IRQ_STATUS_0,This register contains the configuration options for the RGX firmware interrupts to HOST." hexmask.long 0x8 1.--31. 1. "Reserved_1,Reserved_1" newline bitfld.long 0x8 0. "EVENT,Indicates an outstanding interrupt to HOST from RGX firmware" "0,1" line.long 0xC "RGX_CR_MIPS_WRAPPER_IRQ_STATUS_1,This register contains the configuration options for the RGX firmware interrupts to HOST." hexmask.long 0xC 0.--31. 1. "Reserved_1,Reserved_1" wgroup.long 0x8B0++0x7 line.long 0x0 "RGX_CR_MIPS_WRAPPER_IRQ_CLEAR_0,This register contains the configuration options for the RGX firmware interrupts to HOST." hexmask.long 0x0 1.--31. 1. "Reserved_1,Reserved_1" newline bitfld.long 0x0 0. "EVENT,Clears the interrupt event to HOST from RGX firmware" "0,1" line.long 0x4 "RGX_CR_MIPS_WRAPPER_IRQ_CLEAR_1,This register contains the configuration options for the RGX firmware interrupts to HOST." hexmask.long 0x4 0.--31. 1. "Reserved_1,Reserved_1" group.long 0x8B8++0x7 line.long 0x0 "RGX_CR_MIPS_WRAPPER_NMI_ENABLE_0,This register contains the configuration options for the RGX firmware non-maskable interrupts to MIPS." hexmask.long 0x0 1.--31. 1. "Reserved_1,Reserved_1" newline bitfld.long 0x0 0. "EVENT,Allow RGX firmware to send non-maskable interrupts to MIPS" "0,1" line.long 0x4 "RGX_CR_MIPS_WRAPPER_NMI_ENABLE_1,This register contains the configuration options for the RGX firmware non-maskable interrupts to MIPS." hexmask.long 0x4 0.--31. 1. "Reserved_1,Reserved_1" wgroup.long 0x8C0++0x7 line.long 0x0 "RGX_CR_MIPS_WRAPPER_NMI_EVENT_0,This register contains the configuration options for the RGX firmware non-maskable interrupts to MIPS." hexmask.long 0x0 1.--31. 1. "Reserved_1,Reserved_1" newline bitfld.long 0x0 0. "TRIGGER,Issue a non-maskable interrupt to the MIPS SI_NMI pin from RGX firmware" "0,1" line.long 0x4 "RGX_CR_MIPS_WRAPPER_NMI_EVENT_1,This register contains the configuration options for the RGX firmware non-maskable interrupts to MIPS." hexmask.long 0x4 0.--31. 1. "Reserved_1,Reserved_1" group.long 0x8C8++0x7 line.long 0x0 "RGX_CR_MIPS_DEBUG_CONFIG_0,This register contains the security and debug configuration options for the MIPS GPU scheduler." hexmask.long 0x0 1.--31. 1. "Reserved_1,Reserved_1" newline bitfld.long 0x0 0. "DISABLE_PROBE_DEBUG,Enable MIPS SecureDebug. Disables EJTAG access to the MIPS core and PC Sampling" "0,1" line.long 0x4 "RGX_CR_MIPS_DEBUG_CONFIG_1,This register contains the security and debug configuration options for the MIPS GPU scheduler." hexmask.long 0x4 0.--31. 1. "Reserved_1,Reserved_1" rgroup.long 0x8D0++0x7 line.long 0x0 "RGX_CR_MIPS_EXCEPTION_STATUS_0,This register contains the exception status information of the MIPS GPU scheduler." hexmask.long 0x0 6.--31. 1. "Reserved_6,Reserved_6" newline bitfld.long 0x0 5. "SI_SLEEP,Reflects the status of the MIPS SI_Sleep pin" "0,1" newline bitfld.long 0x0 4. "SI_NMI_TAKEN,Reflects the status of the MIPS SI_NMITaken pin" "0,1" newline bitfld.long 0x0 3. "SI_NEST_EXL,Reflects the status of the MIPS SI_NESTEXL pin" "0,1" newline bitfld.long 0x0 2. "SI_NEST_ERL,Reflects the status of the MIPS SI_NESTERL pin" "0,1" newline bitfld.long 0x0 1. "SI_EXL,Reflects the status of the MIPS SI_EXL pin" "0,1" newline bitfld.long 0x0 0. "SI_ERL,Reflects the status of the MIPS SI_ERL pin" "0,1" line.long 0x4 "RGX_CR_MIPS_EXCEPTION_STATUS_1,This register contains the exception status information of the MIPS GPU scheduler." hexmask.long 0x4 0.--31. 1. "Reserved_6,Reserved_6" group.long 0x8D8++0xF line.long 0x0 "RGX_CR_MIPS_WRAPPER_FENCE_CONFIG_0,This register contains the fence configuration options for when MIPS emits a memory fence onto the bus" hexmask.long.tbyte 0x0 12.--31. 1. "BASE_ADDR,4K (12 bits) aligned address that serves as the external memory fence base address" newline hexmask.long.byte 0x0 4.--11. 1. "Reserved_4,Reserved_4" newline bitfld.long 0x0 1.--3. "OS_ID,OS_ID of the emitted fence" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 0. "TRUSTED,Defines whether these accesses are trusted" "0,1" line.long 0x4 "RGX_CR_MIPS_WRAPPER_FENCE_CONFIG_1,This register contains the fence configuration options for when MIPS emits a memory fence onto the bus" hexmask.long.tbyte 0x4 8.--31. 1. "Reserved_40,Reserved_40" newline hexmask.long.byte 0x4 0.--7. 1. "BASE_ADDR,4K (12 bits) aligned address that serves as the external memory fence base address" line.long 0x8 "RGX_CR_MIPS_WRAPPER_CACHE_INVAL_0,A write of '1' to this register invalidates the MIPS wrapper L2 cache The cache hardware will clear this bit when the invalidation operation completes" hexmask.long 0x8 1.--31. 1. "Reserved_1,Reserved_1" newline bitfld.long 0x8 0. "PENDING,MIPS wrapper L2 cache is being invalidated" "0,1" line.long 0xC "RGX_CR_MIPS_WRAPPER_CACHE_INVAL_1,A write of '1' to this register invalidates the MIPS wrapper L2 cache The cache hardware will clear this bit when the invalidation operation completes" hexmask.long 0xC 0.--31. 1. "Reserved_1,Reserved_1" rgroup.long 0x8E8++0x7 line.long 0x0 "RGX_CR_MIPS_WRAPPER_STATUS_0,This register contains status information of the MIPS GPU scheduler." hexmask.long.tbyte 0x0 8.--31. 1. "Reserved_8,Reserved_8" newline hexmask.long.byte 0x0 0.--7. 1. "OUTSTANDING_REQUESTS,Outstanding requests by the MIPS" line.long 0x4 "RGX_CR_MIPS_WRAPPER_STATUS_1,This register contains status information of the MIPS GPU scheduler." hexmask.long 0x4 0.--31. 1. "Reserved_8,Reserved_8" group.long 0x900++0x17 line.long 0x0 "RGX_CR_EVENT_TDM_PDS_CODE_0,PDS code segment address for 2D End-of-Tile event shader." hexmask.long 0x0 4.--31. 1. "ADDR,PDS Execution Address for pixel tasks (Positioned as a byte address 128 bit granularity) 4 GB Range" newline hexmask.long.byte 0x0 0.--3. 1. "Reserved_0,Reserved_0" line.long 0x4 "RGX_CR_EVENT_TDM_PDS_CODE_1,PDS code segment address for 2D End-of-Tile event shader." hexmask.long 0x4 0.--31. 1. "Reserved_32,Reserved_32" line.long 0x8 "RGX_CR_EVENT_TDM_PDS_DATA_0,RGX_CR_EVENT_TDM_PDS_DATA_0" hexmask.long 0x8 4.--31. 1. "ADDR,PDS Execution Address for pixel tasks (Positioned as a byte address 128 bit granularity) 4 GB Range" newline hexmask.long.byte 0x8 0.--3. 1. "Reserved_0,Reserved_0" line.long 0xC "RGX_CR_EVENT_TDM_PDS_DATA_1,RGX_CR_EVENT_TDM_PDS_DATA_1" hexmask.long 0xC 0.--31. 1. "Reserved_32,Reserved_32" line.long 0x10 "RGX_CR_EVENT_TDM_PDS_INFO_0,RGX_CR_EVENT_TDM_PDS_INFO_0" hexmask.long.word 0x10 16.--31. 1. "Reserved_16,Reserved_16" newline hexmask.long.byte 0x10 10.--15. 1. "USC_SR_SIZE,USC Shared Register Data Size in 4x128 bit words (0=0) for pixel event task if zero pixel event task is skipped" newline hexmask.long.byte 0x10 5.--9. 1. "TEMP_STRIDE,PDS Temp Size in 64 bit words (0=0) for pixel event tasks" newline hexmask.long.byte 0x10 0.--4. 1. "CONST_SIZE,PDS Data Size in 128 bit words (0=0) for pixel event tasks if zero pixel event task is skipped" line.long 0x14 "RGX_CR_EVENT_TDM_PDS_INFO_1,RGX_CR_EVENT_TDM_PDS_INFO_1" hexmask.long 0x14 0.--31. 1. "Reserved_16,Reserved_16" repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) group.long ($2+0x918)++0x3 line.long 0x0 "RGX_CR_PDS_TDM_BGRND0_BASE_$1,PDS Background Setup Word 0" hexmask.long 0x0 4.--31. 1. "SHADER_ADDR,The pixel shader base is the base address of the PDS Data Segment. The code segment is address is PDS_PIXEL_SHADERBASE + PDS_PIXELSHADERSIZE. The pixel shader program issues the DOUTU for the Fragment Shader only." newline hexmask.long.byte 0x0 0.--3. 1. "Reserved_0,Reserved_0" repeat.end repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) group.long ($2+0x920)++0x3 line.long 0x0 "RGX_CR_PDS_TDM_BGRND1_BASE_$1,PDS Background Setup Word 1" hexmask.long 0x0 4.--31. 1. "VARYING_ADDR,This is the base address of the PDS Data Segment. The code segment is address is PDS_VARYINGBASE + PDS_VARYINGSIZE (PDS_BGRND_SIZEINFO1)." newline hexmask.long.byte 0x0 0.--3. 1. "Reserved_0,Reserved_0" repeat.end group.long 0x928++0xF line.long 0x0 "RGX_CR_PDS_TDM_BGRND2_BASE_0,PDS Background Setup Word 2" hexmask.long 0x0 4.--31. 1. "UNIFORMDATA_ADDR,This points to the DMAs to load the Uniforms (or contains the Uniforms with DOUTW commands)" newline hexmask.long.byte 0x0 0.--3. 1. "Reserved_0,Reserved_0" line.long 0x4 "RGX_CR_PDS_TDM_BGRND2_BASE_1,PDS Background Setup Word 2" hexmask.long 0x4 0.--31. 1. "Reserved_32,Reserved_32" line.long 0x8 "RGX_CR_PDS_TDM_BGRND3_SIZEINFO_0,If any of the size fields are 0. then that program will not be run. PDS_BGRND_PIXELSHADERSIZE is always 2 128 Bit Words" hexmask.long.byte 0x8 27.--31. 1. "PDS_BATCHNUM,The batch ID to be associated with the background" newline hexmask.long.byte 0x8 21.--26. 1. "PDS_UNIFORMSIZE,The size of the Uniform PDS Data Segment in 128 bit words 0=0. 32 max" newline hexmask.long.byte 0x8 15.--20. 1. "PDS_TEXTURESTATESIZE,The size of the Texture PDS Data Segment in 128 bit words 0=0 32 max" newline hexmask.long.byte 0x8 9.--14. 1. "PDS_VARYINGSIZE,The size of the Varying/Coefficient PDS Data Segment in 128 bit words 0=0 32 max" newline hexmask.long.word 0x8 0.--8. 1. "USC_VARYINGSIZE,The size of the Varying/Coefficient USC Common Store Data in 4x128 bit words 0=0. 256 max" line.long 0xC "RGX_CR_PDS_TDM_BGRND3_SIZEINFO_1,If any of the size fields are 0. then that program will not be run. PDS_BGRND_PIXELSHADERSIZE is always 2 128 Bit Words" hexmask.long.word 0xC 23.--31. 1. "Reserved_55,Reserved_55" newline hexmask.long.word 0xC 14.--22. 1. "USC_SHAREDSIZE,The common store allocation size for the shared registers (texture and uniform data commbined) 256 chunks max" newline hexmask.long.byte 0xC 9.--13. 1. "PDS_TEMPSIZE,0 = 0 64 bit words 1 = 1 64 bit word 248 bytes. This applies to coefficient uniform and texture state updates." newline hexmask.long.word 0xC 0.--8. 1. "PDS_BATCHNUM,The batch ID to be associated with the background" group.long 0xB00++0xF line.long 0x0 "RGX_CR_MTS_SCHEDULE_0,This register allows firmware tasks to be scheduled on the META (Garten) core." hexmask.long.tbyte 0x0 9.--31. 1. "Reserved_9,Reserved_9" newline bitfld.long 0x0 8. "HOST,Host Interrupte kick" "0,1" newline bitfld.long 0x0 6.--7. "PRIORITY,DataMaster Priority" "0,1,2,3" newline bitfld.long 0x0 5. "CONTEXT,CONTEXT" "0,1" newline bitfld.long 0x0 4. "TASK,TASK" "0,1" newline hexmask.long.byte 0x0 0.--3. 1. "DM,DataMaster Type" line.long 0x4 "RGX_CR_MTS_SCHEDULE_1,This register allows firmware tasks to be scheduled on the META (Garten) core." hexmask.long 0x4 0.--31. 1. "Reserved_9,Reserved_9" line.long 0x8 "RGX_CR_MTS_PROC_COMPLETE_0,This register allows firmware tasks to signal process completion." hexmask.long 0x8 2.--31. 1. "Reserved_2,Reserved_2" newline bitfld.long 0x8 1. "CONTEXT,CONTEXT" "0,1" newline bitfld.long 0x8 0. "THREAD,Thread number. This is filled in by hardware and can have any value" "0,1" line.long 0xC "RGX_CR_MTS_PROC_COMPLETE_1,This register allows firmware tasks to signal process completion." hexmask.long 0xC 0.--31. 1. "Reserved_2,Reserved_2" rgroup.long 0xB10++0x1F line.long 0x0 "RGX_CR_MTS_BGCTX_SBDATA0_0,This register contains the sideband data for the process running on the background context of thread 0. Reads of this register will be redirected to the correct. thread specific register by hardware." hexmask.long.tbyte 0x0 9.--31. 1. "Reserved_9,Reserved_9" newline bitfld.long 0x0 6.--8. "OS_ID,The OS_ID of the active thread" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 5. "THREAD_ACTIVE,Indicates the thread is active" "0,1" newline bitfld.long 0x0 4. "TASK,TASK" "0,1" newline hexmask.long.byte 0x0 0.--3. 1. "DM,DataMaster Type" line.long 0x4 "RGX_CR_MTS_BGCTX_SBDATA0_1,This register contains the sideband data for the process running on the background context of thread 0. Reads of this register will be redirected to the correct. thread specific register by hardware." hexmask.long 0x4 0.--31. 1. "Reserved_9,Reserved_9" line.long 0x8 "RGX_CR_MTS_BGCTX_SBDATA1_0,This register contains the sideband data for the process running on the background context of thread 1. Reads of this register will be redirected to the correct. thread specific register by hardware." hexmask.long.tbyte 0x8 9.--31. 1. "Reserved_9,Reserved_9" newline bitfld.long 0x8 6.--8. "OS_ID,The OS_ID of the active thread" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 5. "THREAD_ACTIVE,Indicates the thread is active" "0,1" newline bitfld.long 0x8 4. "TASK,TASK" "0,1" newline hexmask.long.byte 0x8 0.--3. 1. "DM,DataMaster Type" line.long 0xC "RGX_CR_MTS_BGCTX_SBDATA1_1,This register contains the sideband data for the process running on the background context of thread 1. Reads of this register will be redirected to the correct. thread specific register by hardware." hexmask.long 0xC 0.--31. 1. "Reserved_9,Reserved_9" line.long 0x10 "RGX_CR_MTS_INTCTX_SBDATA0_0,This register contains the sideband data for the process running on the interrupt context of thread 0. Reads of this register will be redirected to the correct. thread specific register by hardware." hexmask.long 0x10 6.--31. 1. "INT_STATUS,Interrupt Status for 32 event bus lines" newline hexmask.long.byte 0x10 2.--5. 1. "DM,DataMaster Type" newline bitfld.long 0x10 0.--1. "INT_TASK,Kick Request for timer/BG-request/host" "0,1,2,3" line.long 0x14 "RGX_CR_MTS_INTCTX_SBDATA0_1,This register contains the sideband data for the process running on the interrupt context of thread 0. Reads of this register will be redirected to the correct. thread specific register by hardware." hexmask.long.tbyte 0x14 10.--31. 1. "Reserved_42,Reserved_42" newline bitfld.long 0x14 7.--9. "OS_ID,The OS_ID of the active thread" "0,1,2,3,4,5,6,7" newline bitfld.long 0x14 6. "THREAD_ACTIVE,Indicates the thread is active" "0,1" newline hexmask.long.byte 0x14 0.--5. 1. "INT_STATUS,Interrupt Status for 32 event bus lines" line.long 0x18 "RGX_CR_MTS_INTCTX_SBDATA1_0,This register contains the sideband data for the process running on the interrupt context of thread 1. Reads of this register will be redirected to the correct. thread specific register by hardware." hexmask.long 0x18 6.--31. 1. "INT_STATUS,Interrupt Status for 32 event bus lines" newline hexmask.long.byte 0x18 2.--5. 1. "DM,DataMaster Type" newline bitfld.long 0x18 0.--1. "INT_TASK,Kick Request for timer/BG-request/host" "0,1,2,3" line.long 0x1C "RGX_CR_MTS_INTCTX_SBDATA1_1,This register contains the sideband data for the process running on the interrupt context of thread 1. Reads of this register will be redirected to the correct. thread specific register by hardware." hexmask.long.tbyte 0x1C 10.--31. 1. "Reserved_42,Reserved_42" newline bitfld.long 0x1C 7.--9. "OS_ID,The OS_ID of the active thread" "0,1,2,3,4,5,6,7" newline bitfld.long 0x1C 6. "THREAD_ACTIVE,Indicates the thread is active" "0,1" newline hexmask.long.byte 0x1C 0.--5. 1. "INT_STATUS,Interrupt Status for 32 event bus lines" group.long 0xB30++0x27 line.long 0x0 "RGX_CR_MTS_BGCTX_THREAD0_DM_ASSOC_0,This register is the DataMaster assocation for the background context of thread 0. Bit high represents DataMaster being permitted to run on the background context of thread 0." hexmask.long.word 0x0 16.--31. 1. "Reserved_16,Reserved_16" newline hexmask.long.word 0x0 0.--15. 1. "DM_ASSOC,DataMaster Association (Active High)" line.long 0x4 "RGX_CR_MTS_BGCTX_THREAD0_DM_ASSOC_1,This register is the DataMaster assocation for the background context of thread 0. Bit high represents DataMaster being permitted to run on the background context of thread 0." hexmask.long 0x4 0.--31. 1. "Reserved_16,Reserved_16" line.long 0x8 "RGX_CR_MTS_BGCTX_THREAD1_DM_ASSOC_0,This register is the DataMaster assocation for the background context of thread 1. Bit high represents DataMaster being permitted to run on the background context of thread 1." hexmask.long.word 0x8 16.--31. 1. "Reserved_16,Reserved_16" newline hexmask.long.word 0x8 0.--15. 1. "DM_ASSOC,DataMaster Association (Active High)" line.long 0xC "RGX_CR_MTS_BGCTX_THREAD1_DM_ASSOC_1,This register is the DataMaster assocation for the background context of thread 1. Bit high represents DataMaster being permitted to run on the background context of thread 1." hexmask.long 0xC 0.--31. 1. "Reserved_16,Reserved_16" line.long 0x10 "RGX_CR_MTS_INTCTX_THREAD0_DM_ASSOC_0,This register is the DataMaster assocation for the interrupt context of thread 0. Bit high represents DataMaster being permitted to run on the interrupt context of thread 0." hexmask.long.word 0x10 16.--31. 1. "Reserved_16,Reserved_16" newline hexmask.long.word 0x10 0.--15. 1. "DM_ASSOC,DataMaster Association (Active High)" line.long 0x14 "RGX_CR_MTS_INTCTX_THREAD0_DM_ASSOC_1,This register is the DataMaster assocation for the interrupt context of thread 0. Bit high represents DataMaster being permitted to run on the interrupt context of thread 0." hexmask.long 0x14 0.--31. 1. "Reserved_16,Reserved_16" line.long 0x18 "RGX_CR_MTS_INTCTX_THREAD1_DM_ASSOC_0,This register is the DataMaster assocation for the interrupt context of thread 1. Bit high represents DataMaster being permitted to run on the interrupt context of thread 1." hexmask.long.word 0x18 16.--31. 1. "Reserved_16,Reserved_16" newline hexmask.long.word 0x18 0.--15. 1. "DM_ASSOC,DataMaster Association (Active High)" line.long 0x1C "RGX_CR_MTS_INTCTX_THREAD1_DM_ASSOC_1,This register is the DataMaster assocation for the interrupt context of thread 1. Bit high represents DataMaster being permitted to run on the interrupt context of thread 1." hexmask.long 0x1C 0.--31. 1. "Reserved_16,Reserved_16" line.long 0x20 "RGX_CR_MTS_GARTEN_WRAPPER_CONFIG_0,This register contains the configuration options for the Garten wrapper." hexmask.long.tbyte 0x20 12.--31. 1. "FENCE_ADDR,4k page address to be used for fence requests" newline hexmask.long.word 0x20 1.--11. 1. "Reserved_1,Reserved_1" newline bitfld.long 0x20 0. "IDLE_CTRL,IDLE_CTRL" "0,1" line.long 0x24 "RGX_CR_MTS_GARTEN_WRAPPER_CONFIG_1,This register contains the configuration options for the Garten wrapper." hexmask.long.word 0x24 16.--31. 1. "Reserved_48,Reserved_48" newline hexmask.long.byte 0x24 12.--15. 1. "FENCE_PC_BASE,Page Catalogue base address number to be used for fence requests" newline hexmask.long.byte 0x24 8.--11. 1. "FENCE_DM,Data master value to be used for fence requests" newline hexmask.long.byte 0x24 0.--7. 1. "FENCE_ADDR,4k page address to be used for fence requests" repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) group.long ($2+0xB58)++0x3 line.long 0x0 "RGX_CR_MTS_DM0_INTERRUPT_ENABLE_$1,Interrupt enable status register for DataMaster 0" hexmask.long 0x0 0.--31. 1. "INT_ENABLE,Interrupt Enable" repeat.end repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) group.long ($2+0xB60)++0x3 line.long 0x0 "RGX_CR_MTS_DM1_INTERRUPT_ENABLE_$1,Interrupt enable status register for DataMaster 1" hexmask.long 0x0 0.--31. 1. "INT_ENABLE,Interrupt Enable" repeat.end repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) group.long ($2+0xB68)++0x3 line.long 0x0 "RGX_CR_MTS_DM2_INTERRUPT_ENABLE_$1,Interrupt enable status register for DataMaster 2" hexmask.long 0x0 0.--31. 1. "INT_ENABLE,Interrupt Enable" repeat.end repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) group.long ($2+0xB70)++0x3 line.long 0x0 "RGX_CR_MTS_DM3_INTERRUPT_ENABLE_$1,Interrupt enable status register for DataMaster 3" hexmask.long 0x0 0.--31. 1. "INT_ENABLE,Interrupt Enable" repeat.end repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) group.long ($2+0xB78)++0x3 line.long 0x0 "RGX_CR_MTS_DM4_INTERRUPT_ENABLE_$1,Interrupt enable status register for DataMaster 4" hexmask.long 0x0 0.--31. 1. "INT_ENABLE,Interrupt Enable" repeat.end repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) group.long ($2+0xB80)++0x3 line.long 0x0 "RGX_CR_MTS_DM5_INTERRUPT_ENABLE_$1,Interrupt enable status register for DataMaster 5" hexmask.long 0x0 0.--31. 1. "INT_ENABLE,Interrupt Enable" repeat.end repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) group.long ($2+0xB88)++0x3 line.long 0x0 "RGX_CR_MTS_EVENT_MASK_$1,Mask interrupt events" hexmask.long 0x0 0.--31. 1. "MASK,DESCRIPTION" repeat.end repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) wgroup.long ($2+0xB90)++0x3 line.long 0x0 "RGX_CR_MTS_EVENT_CLEAR_$1,Clear internal interrupt registers" hexmask.long 0x0 0.--31. 1. "CLEAR,DESCRIPTION" repeat.end rgroup.long 0xB98++0x17 line.long 0x0 "RGX_CR_MTS_INTCTX_0,This register contains the sideband data for the MTS internal interrupt context registers" bitfld.long 0x0 30.--31. "Reserved_30,Reserved_30" "0,1,2,3" newline hexmask.long.byte 0x0 22.--29. 1. "DM_HOST_SCHEDULE,A 1 bit counter per DM for host requests" newline hexmask.long.byte 0x0 16.--21. 1. "Reserved_16,Reserved_16" newline hexmask.long.byte 0x0 8.--15. 1. "DM_TIMER_SCHEDULE,A 1 bit counter per DM for timer requests" newline hexmask.long.byte 0x0 0.--7. 1. "DM_INTERRUPT_SCHEDULE,A 1 bit counter per DM for interrupt requests" line.long 0x4 "RGX_CR_MTS_INTCTX_1,This register contains the sideband data for the MTS internal interrupt context registers" hexmask.long 0x4 0.--31. 1. "Reserved_30,Reserved_30" line.long 0x8 "RGX_CR_MTS_BGCTX_0,This register contains the sideband data for the MTS internal background context registers" hexmask.long.tbyte 0x8 8.--31. 1. "Reserved_8,Reserved_8" newline hexmask.long.byte 0x8 0.--7. 1. "DM_NONCOUNTED_SCHEDULE,A 1 bit counter per DM for non-counted background request" line.long 0xC "RGX_CR_MTS_BGCTX_1,This register contains the sideband data for the MTS internal background context registers" hexmask.long 0xC 0.--31. 1. "Reserved_8,Reserved_8" line.long 0x10 "RGX_CR_MTS_BGCTX_COUNTED_SCHEDULE_0,This register contains the sideband data for the MTS internal counted background context counters" hexmask.long.byte 0x10 24.--31. 1. "DM3,A 8 bit counter for DM3" newline hexmask.long.byte 0x10 16.--23. 1. "DM2,A 8 bit counter for DM2" newline hexmask.long.byte 0x10 8.--15. 1. "DM1,A 8 bit counter for DM1" newline hexmask.long.byte 0x10 0.--7. 1. "DM0,A 8 bit counter for DM0" line.long 0x14 "RGX_CR_MTS_BGCTX_COUNTED_SCHEDULE_1,This register contains the sideband data for the MTS internal counted background context counters" hexmask.long.word 0x14 16.--31. 1. "Reserved_48,Reserved_48" newline hexmask.long.byte 0x14 8.--15. 1. "DM5,A 8 bit counter for DM5" newline hexmask.long.byte 0x14 0.--7. 1. "DM4,A 8 bit counter for DM4" repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) rgroup.long ($2+0xBB0)++0x3 line.long 0x0 "RGX_CR_MTS_GPU_INT_STATUS_$1,This register contains the sideband data for the MTS internal GPU interrupt status" hexmask.long 0x0 0.--31. 1. "STATUS,A 32 bit register for recored GPU events" repeat.end group.long 0xBC0++0xF line.long 0x0 "RGX_CR_MTS_OS_PRIORITY_0,Operating System Priority" hexmask.long.word 0x0 16.--31. 1. "Reserved_16,Reserved_16" newline bitfld.long 0x0 14.--15. "ID7,Scheduling priority for operating system 7" "0,1,2,3" newline bitfld.long 0x0 12.--13. "ID6,Scheduling priority for operating system 6" "0,1,2,3" newline bitfld.long 0x0 10.--11. "ID5,Scheduling priority for operating system 5" "0,1,2,3" newline bitfld.long 0x0 8.--9. "ID4,Scheduling priority for operating system 4" "0,1,2,3" newline bitfld.long 0x0 6.--7. "ID3,Scheduling priority for operating system 3" "0,1,2,3" newline bitfld.long 0x0 4.--5. "ID2,Scheduling priority for operating system 2" "0,1,2,3" newline bitfld.long 0x0 2.--3. "ID1,Scheduling priority for operating system 1" "0,1,2,3" newline bitfld.long 0x0 0.--1. "ID0,Scheduling priority for operating system 0" "0,1,2,3" line.long 0x4 "RGX_CR_MTS_OS_PRIORITY_1,Operating System Priority" hexmask.long 0x4 0.--31. 1. "Reserved_16,Reserved_16" line.long 0x8 "RGX_CR_MTS_SCHEDULE_ENABLE_0,This register is an active-high mask. When the bit is 0. the MTS_SCHEDULE kick from the corresponding Guest OS is silently discarded. This allows the FW to mask out a Guest OS in order to prevent denial-of-service style.." hexmask.long.tbyte 0x8 8.--31. 1. "Reserved_8,Reserved_8" newline hexmask.long.byte 0x8 0.--7. 1. "MASK,MASK" line.long 0xC "RGX_CR_MTS_SCHEDULE_ENABLE_1,This register is an active-high mask. When the bit is 0. the MTS_SCHEDULE kick from the corresponding Guest OS is silently discarded. This allows the FW to mask out a Guest OS in order to prevent denial-of-service style.." hexmask.long 0xC 0.--31. 1. "Reserved_8,Reserved_8" rgroup.long 0xBD8++0x7 line.long 0x0 "RGX_CR_IRQ_OS0_EVENT_STATUS_0,This register indicates the source of a per-OS host interrupt. This register is set by the firmware and cleared by the host." hexmask.long 0x0 1.--31. 1. "Reserved_1,Reserved_1" newline bitfld.long 0x0 0. "SOURCE,SOURCE" "0,1" line.long 0x4 "RGX_CR_IRQ_OS0_EVENT_STATUS_1,This register indicates the source of a per-OS host interrupt. This register is set by the firmware and cleared by the host." hexmask.long 0x4 0.--31. 1. "Reserved_1,Reserved_1" group.long 0xBE0++0xF line.long 0x0 "RGX_CR_HOST_IRQ_0,This register triggers a per-OS host interrupt. The hardware sets the corresponding RGX_CR_IRQ_OS_EVENT_STATUS register." hexmask.long 0x0 3.--31. 1. "Reserved_3,Reserved_3" newline bitfld.long 0x0 0.--2. "OSID,Indicates the Guest OS for the interrupt" "0,1,2,3,4,5,6,7" line.long 0x4 "RGX_CR_HOST_IRQ_1,This register triggers a per-OS host interrupt. The hardware sets the corresponding RGX_CR_IRQ_OS_EVENT_STATUS register." hexmask.long 0x4 0.--31. 1. "Reserved_3,Reserved_3" line.long 0x8 "RGX_CR_IRQ_OS0_EVENT_CLEAR_0,This register clears a per-OS host interrupt." hexmask.long 0x8 1.--31. 1. "Reserved_1,Reserved_1" newline bitfld.long 0x8 0. "SOURCE,SOURCE" "0,1" line.long 0xC "RGX_CR_IRQ_OS0_EVENT_CLEAR_1,This register clears a per-OS host interrupt." hexmask.long 0xC 0.--31. 1. "Reserved_1,Reserved_1" group.long 0xBF8++0x5F line.long 0x0 "RGX_CR_META_BOOT_0,RGX_CR_META_BOOT_0" hexmask.long 0x0 1.--31. 1. "Reserved_1,Reserved_1" newline bitfld.long 0x0 0. "MODE,0 = Don't boot 1 = Boot" "Don't boot,Boot" line.long 0x4 "RGX_CR_META_BOOT_1,RGX_CR_META_BOOT_1" hexmask.long 0x4 0.--31. 1. "Reserved_1,Reserved_1" line.long 0x8 "RGX_CR_TE_AA_0,This register controls the anti-aliasing mode of the Tiling Co-Processor. independent control is provided in both X & Y axis. 2xmsaa is achieved by enabling X2 - does not affect TE 4xmsaa is achieved by enabling Y and X2 - TE does AA on Y.." hexmask.long 0x8 3.--31. 1. "Reserved_3,Reserved_3" newline bitfld.long 0x8 2. "Y,Anti-Aliasing in Y Plane Enabled" "0,1" newline bitfld.long 0x8 1. "X,Anti-Aliasing in X Plane Enabled" "0,1" newline bitfld.long 0x8 0. "X2,2x Anti-Aliasing Enabled affects PPP only" "0,1" line.long 0xC "RGX_CR_TE_AA_1,This register controls the anti-aliasing mode of the Tiling Co-Processor. independent control is provided in both X & Y axis. 2xmsaa is achieved by enabling X2 - does not affect TE 4xmsaa is achieved by enabling Y and X2 - TE does AA on Y.." hexmask.long 0xC 0.--31. 1. "Reserved_3,Reserved_3" line.long 0x10 "RGX_CR_TE_MTILE1_0,MacroTile Boundaries X Plane" hexmask.long.byte 0x10 27.--31. 1. "Reserved_27,Reserved_27" newline hexmask.long.word 0x10 18.--26. 1. "X1,X1 MacroTile boundary left tile X for second column of macrotiles (16MT mode) - 32 pixels across tile" newline hexmask.long.word 0x10 9.--17. 1. "X2,X2 MacroTile boundary left tile X for third(16MT) column of macrotiles - 32 pixels across tile" newline hexmask.long.word 0x10 0.--8. 1. "X3,X3 MacroTile boundary left tile X for fourth column of macrotiles (16MT) - 32 pixels across tile" line.long 0x14 "RGX_CR_TE_MTILE1_1,MacroTile Boundaries X Plane" hexmask.long 0x14 0.--31. 1. "Reserved_27,Reserved_27" line.long 0x18 "RGX_CR_TE_MTILE2_0,MacroTile Boundaries Y Plane." hexmask.long.byte 0x18 27.--31. 1. "Reserved_27,Reserved_27" newline hexmask.long.word 0x18 18.--26. 1. "Y1,X1 MacroTile boundary ltop tile Y for second column of macrotiles (16MT mode) - 32 pixels tile height" newline hexmask.long.word 0x18 9.--17. 1. "Y2,X2 MacroTile boundary top tile Y for third(16MT) column of macrotiles - 32 pixels tile height" newline hexmask.long.word 0x18 0.--8. 1. "Y3,X3 MacroTile boundary top tile Y for fourth column of macrotiles (16MT) - 32 pixels tile height" line.long 0x1C "RGX_CR_TE_MTILE2_1,MacroTile Boundaries Y Plane." hexmask.long 0x1C 0.--31. 1. "Reserved_27,Reserved_27" line.long 0x20 "RGX_CR_TE_SCREEN_0,In order to perform the tiling operation and generate the display list the maximum screen size must be configured in terms of the number of tiles in X & Y axis." hexmask.long.word 0x20 21.--31. 1. "Reserved_21,Reserved_21" newline hexmask.long.word 0x20 12.--20. 1. "YMAX,Maximum Y tile address visible on screen 32 pixel tile height 16Kx16K max screen size" newline bitfld.long 0x20 9.--11. "Reserved_9,Reserved_9" "0,1,2,3,4,5,6,7" newline hexmask.long.word 0x20 0.--8. 1. "XMAX,Maximum X tile address visible on screen 32 pixel tile width 16Kx16K max screen size" line.long 0x24 "RGX_CR_TE_SCREEN_1,In order to perform the tiling operation and generate the display list the maximum screen size must be configured in terms of the number of tiles in X & Y axis." hexmask.long 0x24 0.--31. 1. "Reserved_21,Reserved_21" line.long 0x28 "RGX_CR_TE_MTILE_0,In order to perform the tiling operation and generate the display list the maximum screen size must be configured in terms of the number of tiles in X & Y axis." hexmask.long.word 0x28 19.--31. 1. "Reserved_19,Reserved_19" newline hexmask.long.tbyte 0x28 0.--18. 1. "STRIDE,Number of tiles in a Macrotile. Stride = (XTile * YTiles) tiles 32 pixels across by 32 pixels" line.long 0x2C "RGX_CR_TE_MTILE_1,In order to perform the tiling operation and generate the display list the maximum screen size must be configured in terms of the number of tiles in X & Y axis." hexmask.long 0x2C 0.--31. 1. "Reserved_19,Reserved_19" line.long 0x30 "RGX_CR_TE_PSG_0,This register defines the global control for the Parameter Stream Generator within the Tiling Co-Processor. This module formats the display list generated by the Tiling Co-Processor." hexmask.long.word 0x30 22.--31. 1. "Reserved_22,Reserved_22" newline bitfld.long 0x30 21. "CS_SIZE,Size of control stream chunk. 0x0 512 bit 0x1 1024 bit" "0,1" newline bitfld.long 0x30 20. "ENABLE_PWR_GATE_STATE,Enables TE PSG power gate state init. 0x0 Disable 0x1 Enable" "0,1" newline bitfld.long 0x30 19. "ENABLE_CONTEXT_STATE_RESTORE,Enables sampling of Driver TE_STATE_ISP_STATE_ID and TE_ACTIVE_MTILE registers on context switch/restore when set when reset current local value is preserved." "0,1" newline bitfld.long 0x30 18. "ZONLYRENDER,Don't invalidate Tail Pointer Cache entries on a Terminate command. Only effective when COMPLETEONTERMINATE is 0x0 0x0 Do Invalidate 0x1 Don't Invalidate" "0,1" newline bitfld.long 0x30 17. "COMPLETEONTERMINATE,0x1 Write region headers terminate streams and invalidate tail pointer cache entries on terminate. 0x0 If ZONLYRENDER = 0x0 then force an Interrupt however if ZONLYRENDER = 0x1 then write region headers and terminate streams." "0,1" newline bitfld.long 0x30 15.--16. "Reserved_15,Reserved_15" "0,1,2,3" newline bitfld.long 0x30 14. "CACHE_BYPASS,when set VCE sets its write only cache to bypass mode effectively disabling the cache" "0,1" newline bitfld.long 0x30 13. "FORCENEWSTATE,Always embed state information in control stream. Debug only." "0,1" newline bitfld.long 0x30 11.--12. "Reserved_11,Reserved_11" "0,1,2,3" newline hexmask.long.word 0x30 0.--10. 1. "REGION_STRIDE,Number of 4kB Pages devoted to region headers for each Render Target - max needed = 0x500" line.long 0x34 "RGX_CR_TE_PSG_1,This register defines the global control for the Parameter Stream Generator within the Tiling Co-Processor. This module formats the display list generated by the Tiling Co-Processor." hexmask.long 0x34 0.--31. 1. "Reserved_22,Reserved_22" line.long 0x38 "RGX_CR_TE_PSG_TERMINATE_0,This register can be written by the driver to define what the TA should terminate tile control streams with. Default value is 0x00000002. however this can be replaced with a link pointer to some driver defined control stream." hexmask.long 0x38 0.--31. 1. "DWORD,Double-word to terminate all tile control streams with." line.long 0x3C "RGX_CR_TE_PSG_TERMINATE_1,This register can be written by the driver to define what the TA should terminate tile control streams with. Default value is 0x00000002. however this can be replaced with a link pointer to some driver defined control stream." hexmask.long.tbyte 0x3C 8.--31. 1. "Reserved_40,Reserved_40" newline hexmask.long.byte 0x3C 0.--7. 1. "BYTE,Byte to terminate all tile control streams with." line.long 0x40 "RGX_CR_TE_PSGREGION_ADDR_0,This register defines the base address in memory of the Region Header writes by the TA. Region headers are the first part of the display list and contain an entry per tile with information on global setup and a link address to.." hexmask.long 0x40 6.--31. 1. "BASE,16GB Addressable 512-bit aligned Base Address for Region Header writes" newline hexmask.long.byte 0x40 0.--5. 1. "Reserved_0,Reserved_0" line.long 0x44 "RGX_CR_TE_PSGREGION_ADDR_1,This register defines the base address in memory of the Region Header writes by the TA. Region headers are the first part of the display list and contain an entry per tile with information on global setup and a link address to.." hexmask.long.tbyte 0x44 8.--31. 1. "Reserved_40,Reserved_40" newline hexmask.long.byte 0x44 2.--7. 1. "HEAP,1TB Addressable 16GB aligned Heap Address for Region Header writes" newline bitfld.long 0x44 0.--1. "BASE,16GB Addressable 512-bit aligned Base Address for Region Header writes" "0,1,2,3" line.long 0x48 "RGX_CR_TE_TPC_ADDR_0,This register defines the base address in memory of the Tail Pointer Cache. A tail pointer is the current last address written to for a tiles individual display list. an entry for active tiles is maintained as primitives are.." hexmask.long 0x48 6.--31. 1. "BASE,16GB Addressable 512-bit aligned Base Address for Tail Pointer Cache entries. The tail pointer is the current last address written to for a control stream for a tile." newline hexmask.long.byte 0x48 0.--5. 1. "Reserved_0,Reserved_0" line.long 0x4C "RGX_CR_TE_TPC_ADDR_1,This register defines the base address in memory of the Tail Pointer Cache. A tail pointer is the current last address written to for a tiles individual display list. an entry for active tiles is maintained as primitives are.." hexmask.long.tbyte 0x4C 8.--31. 1. "Reserved_40,Reserved_40" newline hexmask.long.byte 0x4C 2.--7. 1. "HEAP,1TB Addressable 16GB aligned Heap Address for Tail Pointer Cache." newline bitfld.long 0x4C 0.--1. "BASE,16GB Addressable 512-bit aligned Base Address for Tail Pointer Cache entries. The tail pointer is the current last address written to for a control stream for a tile." "0,1,2,3" line.long 0x50 "RGX_CR_TE_TPC_0,This register defines the TPC Memory footprint size per Render Target as a Stride of 4KB pages" hexmask.long.tbyte 0x50 12.--31. 1. "Reserved_12,Reserved_12" newline hexmask.long.word 0x50 0.--11. 1. "STRIDE,Number of 4KB pages per Render Target in each TPC footprint - max = 2048" line.long 0x54 "RGX_CR_TE_TPC_1,This register defines the TPC Memory footprint size per Render Target as a Stride of 4KB pages" hexmask.long 0x54 0.--31. 1. "Reserved_12,Reserved_12" line.long 0x58 "RGX_CR_TE_TPC_CONTEXT_0,The Tail Pointer Cache is used to keep track of the last address written to for a particular tile. this is stored in a mixture of on chip cache and external memory. Under certain circumstances it is neccesary to either reset the.." bitfld.long 0x58 31. "CLEAR_PENDING,Reset contents of Tail Pointer Cache" "0,1" newline bitfld.long 0x58 30. "FLUSH_PENDING,Flush contents of Tail Pointer Cache to Memory" "0,1" newline hexmask.long 0x58 0.--29. 1. "Reserved_0,Reserved_0" line.long 0x5C "RGX_CR_TE_TPC_CONTEXT_1,The Tail Pointer Cache is used to keep track of the last address written to for a particular tile. this is stored in a mixture of on chip cache and external memory. Under certain circumstances it is neccesary to either reset the.." hexmask.long 0x5C 0.--31. 1. "Reserved_32,Reserved_32" rgroup.long 0xC58++0xF line.long 0x0 "RGX_CR_TE_RGNBBOX_X_0,Reset or enabled by the PPP_RESETBBOX and PPP_UPDATEBBOX fields in the PPPControl word of the Input Parameter format. This is the maximum extent in X of the post transformed. clipped data before region clipping." hexmask.long.byte 0x0 26.--31. 1. "Reserved_26,Reserved_26" newline hexmask.long.word 0x0 16.--25. 1. "MAX,XMax value for maintained Region Generator Bounding Box tiles 32 pixels in width" newline hexmask.long.byte 0x0 10.--15. 1. "Reserved_10,Reserved_10" newline hexmask.long.word 0x0 0.--9. 1. "MIN,XMin value for maintained Region Generator Bounding Box tiles 32 pixels in width" line.long 0x4 "RGX_CR_TE_RGNBBOX_X_1,Reset or enabled by the PPP_RESETBBOX and PPP_UPDATEBBOX fields in the PPPControl word of the Input Parameter format. This is the maximum extent in X of the post transformed. clipped data before region clipping." hexmask.long 0x4 0.--31. 1. "Reserved_26,Reserved_26" line.long 0x8 "RGX_CR_TE_RGNBBOX_Y_0,Reset or enabled by the PPP_RESETBBOX and PPP_UPDATEBBOX fields in the PPP Control word of the Input Parameter format. This is the maximum extent in Y of the post transformed. clipped data before region clipping." hexmask.long.byte 0x8 26.--31. 1. "Reserved_26,Reserved_26" newline hexmask.long.word 0x8 16.--25. 1. "MAX,YMax value for maintained Region Generator Bounding Box tiles 16 pixels in height" newline hexmask.long.byte 0x8 10.--15. 1. "Reserved_10,Reserved_10" newline hexmask.long.word 0x8 0.--9. 1. "MIN,YMin value for maintained Region Generator Bounding Box tiles 16 pixels in height" line.long 0xC "RGX_CR_TE_RGNBBOX_Y_1,Reset or enabled by the PPP_RESETBBOX and PPP_UPDATEBBOX fields in the PPP Control word of the Input Parameter format. This is the maximum extent in Y of the post transformed. clipped data before region clipping." hexmask.long 0xC 0.--31. 1. "Reserved_26,Reserved_26" group.long 0xC68++0x7 line.long 0x0 "RGX_CR_TE_RGNHDR_INIT_0,A write of '1' to this register starts the TE Region Header Initialisation Sequence The TE HW will clear the PENDING bit once the operation is complete" hexmask.long 0x0 1.--31. 1. "Reserved_1,Reserved_1" newline bitfld.long 0x0 0. "PENDING,Start TE Region Header Initialisation" "0,1" line.long 0x4 "RGX_CR_TE_RGNHDR_INIT_1,A write of '1' to this register starts the TE Region Header Initialisation Sequence The TE HW will clear the PENDING bit once the operation is complete" hexmask.long 0x4 0.--31. 1. "Reserved_1,Reserved_1" group.long 0xC78++0x17 line.long 0x0 "RGX_CR_PPP_GRIDOFFSET_0,Sample position grid offset for use when MSAA/ODAA is DISABLED DX (0.0.0.0) OpenGL (0.5.0.5) Acts as the 9th multisample position when MSAA is ENABLED." hexmask.long.tbyte 0x0 8.--31. 1. "Reserved_8,Reserved_8" newline hexmask.long.byte 0x0 4.--7. 1. "GRID_Y,Unsigned sub-pixel offset" newline hexmask.long.byte 0x0 0.--3. 1. "GRID_X,Unsigned sub-pixel offset" line.long 0x4 "RGX_CR_PPP_GRIDOFFSET_1,Sample position grid offset for use when MSAA/ODAA is DISABLED DX (0.0.0.0) OpenGL (0.5.0.5) Acts as the 9th multisample position when MSAA is ENABLED." hexmask.long 0x4 0.--31. 1. "Reserved_8,Reserved_8" line.long 0x8 "RGX_CR_PPP_MULTISAMPLECTL_0,Sample position grid offset for use in 2x. 4x. 8xMSAA and ODAA modes." hexmask.long.byte 0x8 28.--31. 1. "MSAA_Y3,Unsigned sub-pixel offset for the 4th multisample Y position" newline hexmask.long.byte 0x8 24.--27. 1. "MSAA_X3,Unsigned sub-pixel offset for the 4th multisample X position" newline hexmask.long.byte 0x8 20.--23. 1. "MSAA_Y2,Unsigned sub-pixel offset for the 3rd multisample Y position" newline hexmask.long.byte 0x8 16.--19. 1. "MSAA_X2,Unsigned sub-pixel offset for the 3rd multisample X position" newline hexmask.long.byte 0x8 12.--15. 1. "MSAA_Y1,Unsigned sub-pixel offset for the 2nd multisample Y position" newline hexmask.long.byte 0x8 8.--11. 1. "MSAA_X1,Unsigned sub-pixel offset for the 2nd multisample X position" newline hexmask.long.byte 0x8 4.--7. 1. "MSAA_Y0,Unsigned sub-pixel offset for the 1st multisample Y position" newline hexmask.long.byte 0x8 0.--3. 1. "MSAA_X0,Unsigned sub-pixel offset for the 1st multisample X position" line.long 0xC "RGX_CR_PPP_MULTISAMPLECTL_1,Sample position grid offset for use in 2x. 4x. 8xMSAA and ODAA modes." hexmask.long 0xC 0.--31. 1. "Reserved_32,Reserved_32" line.long 0x10 "RGX_CR_PPP_CTRL_0,This register controls the global setup of the PPP." hexmask.long.tbyte 0x10 13.--31. 1. "Reserved_13,Reserved_13" newline bitfld.long 0x10 12. "VPT_SCISSOR,When 0 the PPP will insert state updates on change of VPT ID When 1 this feature is disabled" "0,1" newline bitfld.long 0x10 11. "FLUSH_MODE,when 0 PPP will supress end of draw call flushed from reaching the Clipper and TA pipeline This will break batch number funstionality but will give better primitive block utiliastion. when 1 PPP will not supress any flushes" "0,1" newline bitfld.long 0x10 10. "BFCULL_RESTRICT_CLIP,When set clipped primitives are only back-face culled after the clipper. 0 Enable early back face cull for clipped primitives 1 Disable early cull" "0,1" newline bitfld.long 0x10 9. "FIXED_POINT_FORMAT,When set the PPP will use a fixed point format of 16. 8 rather than 16.4. 0 16.4 fixed point format 1 16.8 fixed point format" "0,1" newline bitfld.long 0x10 8. "DEFAULT_POINT_SIZE,When set the PPP will use the default point size rather than reading it from the vertex. 0 Point size read from vertex 1 Default point size of 3F800000 used" "0,1" newline bitfld.long 0x10 7. "BFCULL1_DISABLE,Disable for fully clipped culling 0 First back face cull block enabled 1 First back face cull block disabled" "0,1" newline bitfld.long 0x10 6. "BFCULL2_DISABLE,Disable for fully clipped culling 0 Second back face cull block enabled 1 Second back face cull block disabled" "0,1" newline bitfld.long 0x10 5. "FCCULL_DISABLE,Disable for fully clipped culling 0 Fully clipped culling enabled 1 Fully clipped culling disabled" "0,1" newline bitfld.long 0x10 4. "OSCULL_DISABLE,Disable for off screen culling 0 Off screen culling enabled 1 Off screen culling disabled" "0,1" newline bitfld.long 0x10 3. "PSOCULL_DISABLE,Disable for perfect small object culling 0 Perfect small object culling enabled 1 Perfect small object culling disabled" "0,1" newline bitfld.long 0x10 2. "SOCULL_DISABLE,Disable for small object culling 0 Small object culling enabled 1 Small object culling disabled" "0,1" newline bitfld.long 0x10 1. "WCLAMPEN,Enable W clamping 0 W clamping disabled 1 W clamping enabled" "0,1" newline bitfld.long 0x10 0. "OPENGL,Select OpenGL or D3D mode 0 D3D 1 OpenGL" "0,1" line.long 0x14 "RGX_CR_PPP_CTRL_1,This register controls the global setup of the PPP." hexmask.long 0x14 0.--31. 1. "Reserved_13,Reserved_13" repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) group.long ($2+0xC90)++0x3 line.long 0x0 "RGX_CR_PPP_WCLAMP_$1,RGX_CR_PPP_WCLAMP_0" hexmask.long 0x0 0.--31. 1. "CLAMP_VALUE,Clamp value for W clamping. See the Input parameter format viewport transform for details. Clamp is applied post viewport transform if the w value is less than the WCOMPARE value. Note that this value cannot be negative." repeat.end group.long 0xC98++0xF line.long 0x0 "RGX_CR_PPP_SCREEN_0,In order to perform the tiling operation and generate the display list the maximum screen size must be configured in terms of the number of pixels in X & Y axis since this may not be the same as the number of tiles defined in the.." bitfld.long 0x0 31. "Reserved_31,Reserved_31" "0,1" newline hexmask.long.word 0x0 16.--30. 1. "PIXYMAX,Screen height in pixels. (16K x 16K max screen size)" newline bitfld.long 0x0 15. "Reserved_15,Reserved_15" "0,1" newline hexmask.long.word 0x0 0.--14. 1. "PIXXMAX,Screen width in pixels.(16K x 16K max screen size)" line.long 0x4 "RGX_CR_PPP_SCREEN_1,In order to perform the tiling operation and generate the display list the maximum screen size must be configured in terms of the number of pixels in X & Y axis since this may not be the same as the number of tiles defined in the.." hexmask.long 0x4 0.--31. 1. "Reserved_31,Reserved_31" line.long 0x8 "RGX_CR_VCE_CTRL_0,This register controls the global setup of the VCE." hexmask.long 0x8 4.--31. 1. "Reserved_4,Reserved_4" newline bitfld.long 0x8 3. "CACHE_BYPASS,when set VCE sets its write only cache to bypass mode effectively disabling the cache" "0,1" newline bitfld.long 0x8 2. "Reserved_2,Reserved_2" "0,1" newline bitfld.long 0x8 1. "TWO_ORIGIN_DISABLE,When set raw mode is selected in place of 2-origin delta stream compression mode" "0,1" newline bitfld.long 0x8 0. "COMPRESS_DISABLE,When set vertex compression is disabled. I.e. raw mode is forced for all vertices" "0,1" line.long 0xC "RGX_CR_VCE_CTRL_1,This register controls the global setup of the VCE." hexmask.long 0xC 0.--31. 1. "Reserved_4,Reserved_4" wgroup.long 0xCA8++0x7 line.long 0x0 "RGX_CR_TE_CLEAR_LISTS_AFTER_ABORT_0,A write of '1' to this register tells the TE we are resuming after an Abort and Partial Render Sequence" hexmask.long 0x0 1.--31. 1. "Reserved_1,Reserved_1" newline bitfld.long 0x0 0. "PULSE,TE Clears all references after Abort and Partial Render Sequence" "0,1" line.long 0x4 "RGX_CR_TE_CLEAR_LISTS_AFTER_ABORT_1,A write of '1' to this register tells the TE we are resuming after an Abort and Partial Render Sequence" hexmask.long 0x4 0.--31. 1. "Reserved_1,Reserved_1" group.long 0xCB0++0x17 line.long 0x0 "RGX_CR_TA_RTC_ADDR_0,This register defines the base address in memory of the TA Render Target Caches. for the VCE. TEAC and PSG" hexmask.long 0x0 6.--31. 1. "BASE,16GB Addressabreadonly le 512-bit aligned Base Address for TA Render Target Caches." newline hexmask.long.byte 0x0 0.--5. 1. "Reserved_0,Reserved_0" line.long 0x4 "RGX_CR_TA_RTC_ADDR_1,This register defines the base address in memory of the TA Render Target Caches. for the VCE. TEAC and PSG" hexmask.long.tbyte 0x4 8.--31. 1. "Reserved_40,Reserved_40" newline hexmask.long.byte 0x4 2.--7. 1. "HEAP,1TB Addressable 16GB aligned Heap Address for TA Render Target Caches" newline bitfld.long 0x4 0.--1. "BASE,16GB Addressabreadonly le 512-bit aligned Base Address for TA Render Target Caches." "0,1,2,3" line.long 0x8 "RGX_CR_TA_RTC_CTRL_0,A write of '1' to Bit 0 of this register Clears the RTC. A write of '1' to Bit 1 of this register Stores the RTC to memory (address specified in TA_RTC_ADDR register)" hexmask.long 0x8 2.--31. 1. "Reserved_2,Reserved_2" newline bitfld.long 0x8 1. "STORE_PENDING,Store RTC" "0,1" newline bitfld.long 0x8 0. "CLEAR_PENDING,Clear RTC" "0,1" line.long 0xC "RGX_CR_TA_RTC_CTRL_1,A write of '1' to Bit 0 of this register Clears the RTC. A write of '1' to Bit 1 of this register Stores the RTC to memory (address specified in TA_RTC_ADDR register)" hexmask.long 0xC 0.--31. 1. "Reserved_2,Reserved_2" line.long 0x10 "RGX_CR_TA_CONTEXT_STATE_BASE_0,The base address in external memory of the TA's context state buffer. to which the PPP will store the state on a context store and from which the VDM will reload on a context resume" hexmask.long 0x10 4.--31. 1. "ADDR,1TB range 128-bit aligned base address" newline hexmask.long.byte 0x10 0.--3. 1. "Reserved_0,Reserved_0" line.long 0x14 "RGX_CR_TA_CONTEXT_STATE_BASE_1,The base address in external memory of the TA's context state buffer. to which the PPP will store the state on a context store and from which the VDM will reload on a context resume" hexmask.long.tbyte 0x14 8.--31. 1. "Reserved_40,Reserved_40" newline hexmask.long.byte 0x14 0.--7. 1. "ADDR,1TB range 128-bit aligned base address" rgroup.long 0xCC8++0x7 line.long 0x0 "RGX_CR_PPP_DIAG_CULL_0,Diagnois register keeps a count of the number of primtives entering the PPP culling module" hexmask.long.byte 0x0 26.--31. 1. "OP_COUNT,count of primitives exiting the cull block" newline hexmask.long 0x0 0.--25. 1. "IP_COUNT,count of primitives entering the cull block" line.long 0x4 "RGX_CR_PPP_DIAG_CULL_1,Diagnois register keeps a count of the number of primtives entering the PPP culling module" hexmask.long.word 0x4 20.--31. 1. "Reserved_52,Reserved_52" newline hexmask.long.tbyte 0x4 0.--19. 1. "OP_COUNT,count of primitives exiting the cull block" repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) rgroup.long ($2+0xCD0)++0x3 line.long 0x0 "RGX_CR_PPP_$1,Checksum generated from the output of the PPP" hexmask.long 0x0 0.--31. 1. "CHECKSUM,checksum generated from the output of the PPP" repeat.end group.long 0xCD8++0x1F line.long 0x0 "RGX_CR_UVS_CLEAR_0,A write of '1' to this register starts the UVS Clear Operation This register must be written during the core initialisation sequence." hexmask.long 0x0 1.--31. 1. "Reserved_1,Reserved_1" newline bitfld.long 0x0 0. "PENDING,Start UVS Clear Operation a write to this register results in a one cycle pulse" "0,1" line.long 0x4 "RGX_CR_UVS_CLEAR_1,A write of '1' to this register starts the UVS Clear Operation This register must be written during the core initialisation sequence." hexmask.long 0x4 0.--31. 1. "Reserved_1,Reserved_1" line.long 0x8 "RGX_CR_TA_RTC_PRELOAD_0,When set. the RTC will be Preloaded with Zeros (or a nonRTA render target of 1) on a Clear Operation (used when Render Targets are not in use to remove the need for memory allocation)" hexmask.long 0x8 2.--31. 1. "Reserved_2,Reserved_2" newline bitfld.long 0x8 1. "ONE,Preload RTC with Render Target 0 set on a Clear. Used when resuming a TA phase after coarse grain context switch" "0,1" newline bitfld.long 0x8 0. "ZEROS,Preload RTC with Zeros on a Clear" "0,1" line.long 0xC "RGX_CR_TA_RTC_PRELOAD_1,When set. the RTC will be Preloaded with Zeros (or a nonRTA render target of 1) on a Clear Operation (used when Render Targets are not in use to remove the need for memory allocation)" hexmask.long 0xC 0.--31. 1. "Reserved_2,Reserved_2" line.long 0x10 "RGX_CR_TE_STATE_0,This register should be Sampled by the Driver on Context Switch and Restored before the Resume of the TA Context" hexmask.long 0x10 6.--31. 1. "Reserved_6,Reserved_6" newline hexmask.long.byte 0x10 1.--5. 1. "ISP_STATE_ID,ISP State ID" newline bitfld.long 0x10 0. "ABORTED,TA had been aborted in the past" "0,1" line.long 0x14 "RGX_CR_TE_STATE_1,This register should be Sampled by the Driver on Context Switch and Restored before the Resume of the TA Context" hexmask.long 0x14 0.--31. 1. "Reserved_6,Reserved_6" line.long 0x18 "RGX_CR_VCE_HALT_0,The MicroKernel must halt VCE processing (consumption of it's pages allocated by PM) before we can do a Partial Render in the Rogue Architecture. When it writes this register. the VCE will detect this on a notify pulse and assert the.." hexmask.long 0x18 1.--31. 1. "Reserved_1,Reserved_1" newline bitfld.long 0x18 0. "PENDING,VCE is Halting after Current Block" "0,1" line.long 0x1C "RGX_CR_VCE_HALT_1,The MicroKernel must halt VCE processing (consumption of it's pages allocated by PM) before we can do a Partial Render in the Rogue Architecture. When it writes this register. the VCE will detect this on a notify pulse and assert the.." hexmask.long 0x1C 0.--31. 1. "Reserved_1,Reserved_1" wgroup.long 0xCF8++0x7 line.long 0x0 "RGX_CR_TE_RESUME_AFTER_ABORT_0,A write of '1' to this register tells the TE we are resuming after an Abort but that no Partial Render took place" hexmask.long 0x0 1.--31. 1. "Reserved_1,Reserved_1" newline bitfld.long 0x0 0. "PULSE,TE is restarted and reattempts failing allocation after Out Of Memory event only" "0,1" line.long 0x4 "RGX_CR_TE_RESUME_AFTER_ABORT_1,A write of '1' to this register tells the TE we are resuming after an Abort but that no Partial Render took place" hexmask.long 0x4 0.--31. 1. "Reserved_1,Reserved_1" rgroup.long 0xD00++0x7 line.long 0x0 "RGX_CR_TA_IDLE_0,RGX_CR_TA_IDLE_0" hexmask.long 0x0 6.--31. 1. "Reserved_6,Reserved_6" newline bitfld.long 0x0 5. "TE,TE Module IDLE" "0,1" newline bitfld.long 0x0 4. "VCE,VCE Module IDLE" "0,1" newline bitfld.long 0x0 3. "VBG,VBG Module IDLE" "0,1" newline bitfld.long 0x0 2. "CLIP,CLIP Module IDLE" "0,1" newline bitfld.long 0x0 1. "PPP,PPP Module IDLE" "0,1" newline bitfld.long 0x0 0. "UVS,UVS Module IDLE" "0,1" line.long 0x4 "RGX_CR_TA_IDLE_1,RGX_CR_TA_IDLE_1" hexmask.long 0x4 0.--31. 1. "Reserved_6,Reserved_6" repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) rgroup.long ($2+0xD08)++0x3 line.long 0x0 "RGX_CR_STAT_NEW_PRIM_$1,RGX_CR_STAT_NEW_PRIM_0" hexmask.long 0x0 0.--31. 1. "PPP,Number of primitives into PPP" repeat.end repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) rgroup.long ($2+0xD10)++0x3 line.long 0x0 "RGX_CR_STAT_NEW_$1,RGX_CR_STAT_NEW_0" hexmask.long 0x0 0.--31. 1. "VERTEX,Number of vertices" repeat.end group.long 0xD18++0x27 line.long 0x0 "RGX_CR_FBC_MEM_POINTER_0,Framebuffer last memory address written in indirect mode" hexmask.long 0x0 0.--31. 1. "BASE_ADDRESS_REQ,Set to base address of compressed surface to find the last written address for that surface by reading the register when FBC_MEM_POINTER_READ_PENDING =0. BASE_ADDRESS=[33..0] DM=[36..34]" line.long 0x4 "RGX_CR_FBC_MEM_POINTER_1,Framebuffer last memory address written in indirect mode" hexmask.long 0x4 6.--31. 1. "Reserved_38,Reserved_38" newline bitfld.long 0x4 5. "READ_PENDING,Write 1 to perform a lookup for the last memory address written for that surface specified when this register is read as 0 then contents of FBC_MEM_POINTER_BASE_ADDRESS_REQ register contains the last memory address written for the.." "0,1" newline hexmask.long.byte 0x4 0.--4. 1. "BASE_ADDRESS_REQ,Set to base address of compressed surface to find the last written address for that surface by reading the register when FBC_MEM_POINTER_READ_PENDING =0. BASE_ADDRESS=[33..0] DM=[36..34]" line.long 0x8 "RGX_CR_TE_PSG_RTC_0,This register should be Sampled by the Driver on VDM Context Switch Terminate TA FINISHED event and Restored before the Resume of the TA Context" hexmask.long.tbyte 0x8 12.--31. 1. "Reserved_12,Reserved_12" newline hexmask.long.word 0x8 0.--11. 1. "ACTIVE_RTS,RTAs active at the point of the VDM Context SWitch" line.long 0xC "RGX_CR_TE_PSG_RTC_1,This register should be Sampled by the Driver on VDM Context Switch Terminate TA FINISHED event and Restored before the Resume of the TA Context" hexmask.long 0xC 0.--31. 1. "Reserved_12,Reserved_12" line.long 0x10 "RGX_CR_VCE_CACHE_FLUSH_0,The MicroKernel can use this to flush the VCE write only cache at the end of TA phase render. When it writes this register. the VCE will detect this on a notify pulse and assert the return signal until it has completed processing.." hexmask.long 0x10 1.--31. 1. "Reserved_1,Reserved_1" newline bitfld.long 0x10 0. "PENDING,VCE is Flushing its write only cache to memory" "0,1" line.long 0x14 "RGX_CR_VCE_CACHE_FLUSH_1,The MicroKernel can use this to flush the VCE write only cache at the end of TA phase render. When it writes this register. the VCE will detect this on a notify pulse and assert the return signal until it has completed processing.." hexmask.long 0x14 0.--31. 1. "Reserved_1,Reserved_1" line.long 0x18 "RGX_CR_TE_CACHE_FLUSH_0,The MicroKernel can use this to flush the TE write only cache at the end of TA phase render. When it writes this register. the TE will detect this on a notify pulse and assert the return signal until it has completed processing.." hexmask.long 0x18 1.--31. 1. "Reserved_1,Reserved_1" newline bitfld.long 0x18 0. "PENDING,TE is Flushing its write only cache to memory" "0,1" line.long 0x1C "RGX_CR_TE_CACHE_FLUSH_1,The MicroKernel can use this to flush the TE write only cache at the end of TA phase render. When it writes this register. the TE will detect this on a notify pulse and assert the return signal until it has completed processing.." hexmask.long 0x1C 0.--31. 1. "Reserved_1,Reserved_1" line.long 0x20 "RGX_CR_PM_CACHE_FLUSH_0,The MicroKernel can use this to flush the PM write only cache at the end of TA phase render. When it writes this register. the PM will detect this on a notify pulse and assert the return signal until it has completed processing.." hexmask.long 0x20 1.--31. 1. "Reserved_1,Reserved_1" newline bitfld.long 0x20 0. "PENDING,PM is Flushing its write only cache to memory" "0,1" line.long 0x24 "RGX_CR_PM_CACHE_FLUSH_1,The MicroKernel can use this to flush the PM write only cache at the end of TA phase render. When it writes this register. the PM will detect this on a notify pulse and assert the return signal until it has completed processing.." hexmask.long 0x24 0.--31. 1. "Reserved_1,Reserved_1" wgroup.long 0xF00++0x7 line.long 0x0 "RGX_CR_ISP_START_RENDER_0,Writing '1' to this register initiates a 3D render" hexmask.long 0x0 1.--31. 1. "Reserved_1,Reserved_1" newline bitfld.long 0x0 0. "PULSE,PULSE" "0,1" line.long 0x4 "RGX_CR_ISP_START_RENDER_1,Writing '1' to this register initiates a 3D render" hexmask.long 0x4 0.--31. 1. "Reserved_1,Reserved_1" group.long 0xF08++0x77 line.long 0x0 "RGX_CR_ISP_RENDER_0,Controls the render" hexmask.long 0x0 5.--31. 1. "Reserved_5,Reserved_5" newline bitfld.long 0x0 4. "RESUME,Render resume" "0,1" newline bitfld.long 0x0 2.--3. "DIR,Render direction" "0,1,2,3" newline bitfld.long 0x0 0.--1. "MODE,Render type" "0,1,2,3" line.long 0x4 "RGX_CR_ISP_RENDER_1,Controls the render" hexmask.long 0x4 0.--31. 1. "Reserved_5,Reserved_5" line.long 0x8 "RGX_CR_ISP_RENDER_ORIGIN_0,This register defines the top-left tile coordinate for the render." hexmask.long.byte 0x8 26.--31. 1. "Reserved_26,Reserved_26" newline hexmask.long.word 0x8 16.--25. 1. "X,X coordinate in tiles" newline hexmask.long.byte 0x8 10.--15. 1. "Reserved_10,Reserved_10" newline hexmask.long.word 0x8 0.--9. 1. "Y,Y coordinate in tiles" line.long 0xC "RGX_CR_ISP_RENDER_ORIGIN_1,This register defines the top-left tile coordinate for the render." hexmask.long 0xC 0.--31. 1. "Reserved_26,Reserved_26" line.long 0x10 "RGX_CR_ISP_MTILE_SIZE_0,RGX_CR_ISP_MTILE_SIZE_0" hexmask.long.byte 0x10 26.--31. 1. "Reserved_26,Reserved_26" newline hexmask.long.word 0x10 16.--25. 1. "X,Macrotile width in tiles. A value of zero corresponds to the maximum size" newline hexmask.long.byte 0x10 10.--15. 1. "Reserved_10,Reserved_10" newline hexmask.long.word 0x10 0.--9. 1. "Y,Macrotile height in tiles. A value of zero corresponds to the maximum size" line.long 0x14 "RGX_CR_ISP_MTILE_SIZE_1,RGX_CR_ISP_MTILE_SIZE_1" hexmask.long 0x14 0.--31. 1. "Reserved_26,Reserved_26" line.long 0x18 "RGX_CR_ISP_MTILE_BASE_0,RGX_CR_ISP_MTILE_BASE_0" hexmask.long 0x18 2.--31. 1. "ADDR,1TB range 32-bit aligned base address" newline bitfld.long 0x18 0.--1. "Reserved_0,Reserved_0" "0,1,2,3" line.long 0x1C "RGX_CR_ISP_MTILE_BASE_1,RGX_CR_ISP_MTILE_BASE_1" hexmask.long.tbyte 0x1C 8.--31. 1. "Reserved_40,Reserved_40" newline hexmask.long.byte 0x1C 0.--7. 1. "ADDR,1TB range 32-bit aligned base address" line.long 0x20 "RGX_CR_ISP_RGN_0,This register defines the sizes of the allocations of the simple internal parameter data." bitfld.long 0x20 29.--31. "Reserved_29,Reserved_29" "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x20 24.--28. 1. "CS_SIZE,Number of primitive headers in the control stream for a fast 2D render. If the number of primitive headers exceeds the maximum field size or the size of the control stream is unknown a value of all ones should be written" newline hexmask.long.tbyte 0x20 0.--23. 1. "SIZE,Number of Region Headers to fetch" line.long 0x24 "RGX_CR_ISP_RGN_1,This register defines the sizes of the allocations of the simple internal parameter data." hexmask.long 0x24 0.--31. 1. "Reserved_29,Reserved_29" line.long 0x28 "RGX_CR_ISP_AA_0,Controls whether anti-aliasing is enabled or disabled" hexmask.long 0x28 2.--31. 1. "Reserved_2,Reserved_2" newline bitfld.long 0x28 0.--1. "MODE,MODE" "0,1,2,3" line.long 0x2C "RGX_CR_ISP_AA_1,Controls whether anti-aliasing is enabled or disabled" hexmask.long 0x2C 0.--31. 1. "Reserved_2,Reserved_2" line.long 0x30 "RGX_CR_ISP_CTL_0,ISP control register. This register contains the PIPE_NUM field which controls the number of tiles in flight within the IPP and IPF. The values to which this register should be set are dependent on not only the number of tiles in flight.." bitfld.long 0x30 31. "Reserved_31,Reserved_31" "0,1" newline bitfld.long 0x30 30. "LINE_STYLE,Used to enable rendering widelines as rectangles. '0': render as parallelograms '1': render as retangles" "0,1" newline bitfld.long 0x30 29. "LINE_STYLE_PIX,Used to enable rendering single pixel widelines as rectangles. '0': render as parallelograms '1': render as retangles" "0,1" newline bitfld.long 0x30 28. "PAIR_TILES_VERT,If set causes IPF to pair tiles vertically within its pipeline." "0,1" newline bitfld.long 0x30 27. "PAIR_TILES,If set causes IPF to pair tiles within its pipeline." "0,1" newline hexmask.long.byte 0x30 21.--26. 1. "Reserved_21,Reserved_21" newline bitfld.long 0x30 20. "DBIAS_IS_INT,When set depth bias value is a signed integer" "0,1" newline bitfld.long 0x30 19. "OVERLAP_CHECK_MODE,0 - different samples for the same pixel will be sent to different pass groups for translucent objects (pixel to pixel overlap test) 1 - different samples for the same pixel will be sent as the same pass group (sample to sample overlap.." "different samples for the same pixel will be..,different samples for the same pixel will be.." newline bitfld.long 0x30 18. "PT_UPFRONT_DEPTH_DISABLE,When set disable UPFRONT depth test in the Depthsorter" "0,1" newline bitfld.long 0x30 17. "PROCESS_EMPTY_TILES,When set empty tiles are always processed rather than being suppressed" "0,1" newline bitfld.long 0x30 16. "SAMPLE_POS,Specifies the sampling rule to be used when calculating the endpoint adjustment for thin lines" "0,1" newline hexmask.long.byte 0x30 12.--15. 1. "PIPE_ENABLE,Tiles-in-flight" newline bitfld.long 0x30 10.--11. "Reserved_10,Reserved_10" "0,1,2,3" newline hexmask.long.byte 0x30 4.--9. 1. "VALID_ID,Triangle validation value" newline hexmask.long.byte 0x30 0.--3. 1. "UPASS_START,User pass start value" line.long 0x34 "RGX_CR_ISP_CTL_1,ISP control register. This register contains the PIPE_NUM field which controls the number of tiles in flight within the IPP and IPF. The values to which this register should be set are dependent on not only the number of tiles in flight.." hexmask.long 0x34 0.--31. 1. "Reserved_31,Reserved_31" line.long 0x38 "RGX_CR_ISP_SPLIT_RENDER_0,RGX_CR_ISP_SPLIT_RENDER_0" bitfld.long 0x38 30.--31. "Reserved_30,Reserved_30" "0,1,2,3" newline hexmask.long.word 0x38 16.--29. 1. "MAX,Render up to and including this value" newline bitfld.long 0x38 14.--15. "Reserved_14,Reserved_14" "0,1,2,3" newline hexmask.long.word 0x38 0.--13. 1. "MIN,Render up from and including this value" line.long 0x3C "RGX_CR_ISP_SPLIT_RENDER_1,RGX_CR_ISP_SPLIT_RENDER_1" hexmask.long 0x3C 1.--31. 1. "Reserved_33,Reserved_33" newline bitfld.long 0x3C 0. "ENABLE,ENABLE" "0,1" line.long 0x40 "RGX_CR_ISP_ZLSCTL_0,ISP Z Load/Store & format global control register" hexmask.long.byte 0x40 27.--31. 1. "ZLSEXTENT_Y_Z,For Depth buffer Display width of Y in tiles minus one: 0x000 1 tile 0x001 2 tiles .. 0x2FF 1024 tiles zlsextent_y = total_samples_y / 32 samples in non-msaa 4xmsaa mode = total_samples_y / 64 samples in 2xmsaa 8xmsaa mode. In.." newline bitfld.long 0x40 25.--26. "ZSTOREFORMAT,ZSTOREFORMAT" "0,1,2,3" newline bitfld.long 0x40 23.--24. "ZLOADFORMAT,ZLOADFORMAT" "0,1,2,3" newline bitfld.long 0x40 22. "FB_STOREEN,when set frame buffer compression store is enabled" "0,1" newline bitfld.long 0x40 21. "FB_LOADEN,when set frame buffer decompression load is enabled" "0,1" newline bitfld.long 0x40 20. "MSTOREEN,When set and ZSTOREFORMAT = 0x0 mask plane is stored within msb of IEEE format when set and ZSTOREFORMAT = 0x3 mask plane is stored at bit position 31 of IEEE format when set for other format if mask_store_base_enable = '1' background.." "0,1" newline bitfld.long 0x40 19. "ZSTOREEN,When set to 1 if the ZSTORE bit in the region header is also set then the depth buffer is stored to memory after each tile is processed" "0,1" newline bitfld.long 0x40 18. "SSTOREEN,When set to 1 if the ZSTORE bit in the region header is also set then the stencil buffer is stored to memory after each tile is processed" "0,1" newline bitfld.long 0x40 17. "STORETWIDDLED,When set to 1 depth and stencil data is written out in 'Twiddled' order." "0,1" newline bitfld.long 0x40 16. "MLOADEN,When set and ZLOADFORMAT = 0x0 mask plane is loaded from msb of IEEE format when set and ZLOADFORMAT = 0x3 mask plane is loaded from the bit position 31 of IEEE format when set for other format if mask_load_base_enable = '1' mask plane is.." "0,1" newline bitfld.long 0x40 15. "ZLOADEN,When set to 1 if the ZLOAD bit in the region header is also set then the depth buffer is read from memory prior to tile processing" "0,1" newline bitfld.long 0x40 14. "SLOADEN,When set to 1 if the ZLOAD bit in the region header is also set then the stencil buffer is read from memory prior to tile processing" "0,1" newline bitfld.long 0x40 13. "LOADTWIDDLED,When set to 1 depth stencil data is loaded in 'Twiddled' order" "0,1" newline hexmask.long.word 0x40 3.--12. 1. "ZLSEXTENT_X_Z,For depth buffer Display width of X in tiles minus one: 0x000 1 tile 0x001 2 tiles .. 0x2FF 1024 tiles. For different msaa mode 1xmsaa = 1 x (32 32) pixels = 32x1 x 32x1 = 1024 samples = 32 x 32 samples 2xmsaa = 2 x (32 32) pixels =.." newline bitfld.long 0x40 2. "FORCEZSTORE,If set to 1 the depth/stencil buffer is always stored at the end of each tile irrespective of the region header ZSTORE bit." "0,1" newline bitfld.long 0x40 1. "FORCEZLOAD,If set to 1 the depth/stencil buffer is always loaded at the start of each tile irrespective of the region header ZLOAD bit." "0,1" newline bitfld.long 0x40 0. "ZONLYRENDER,When set only the Z buffer is rendered. Opaque and translucent objects are stencil and depth tested as usual but no pixel spans are emitted to the PDS Pixel presenter. Pixels within punch through and depth feedback objects are emitted on.." "0,1" line.long 0x44 "RGX_CR_ISP_ZLSCTL_1,ISP Z Load/Store & format global control register" hexmask.long.byte 0x44 26.--31. 1. "Reserved_58,Reserved_58" newline hexmask.long.word 0x44 16.--25. 1. "ZLSEXTENT_Y_S,For stencil buffer the value calculation is the same as ZLSEXTENT_Y_Z" newline hexmask.long.word 0x44 6.--15. 1. "ZLSEXTENT_X_S,For stencil buffer the value calculation is the same as ZLSEXTENT_X_Z" newline bitfld.long 0x44 5. "STENCIL_EXTENT_ENABLE,When this bit is '1' stencil buffer will use zlsextent_x/y_s value to calculate zload/store address otherwise zlsextent_x/y_z value will be used. The default value is '0' which disables this new function." "0,1" newline hexmask.long.byte 0x44 0.--4. 1. "ZLSEXTENT_Y_Z,For Depth buffer Display width of Y in tiles minus one: 0x000 1 tile 0x001 2 tiles .. 0x2FF 1024 tiles zlsextent_y = total_samples_y / 32 samples in non-msaa 4xmsaa mode = total_samples_y / 64 samples in 2xmsaa 8xmsaa mode. In.." line.long 0x48 "RGX_CR_ISP_ZLOAD_BASE_0,Base address in memory of the Z Buffer base address to load into the ISP for non-compressed ZLS formats." hexmask.long 0x48 4.--31. 1. "ADDR,1TB Addressable 16byte aligned Base Address of the Z Buffer Load base address" newline hexmask.long.byte 0x48 0.--3. 1. "Reserved_0,Reserved_0" line.long 0x4C "RGX_CR_ISP_ZLOAD_BASE_1,Base address in memory of the Z Buffer base address to load into the ISP for non-compressed ZLS formats." hexmask.long.tbyte 0x4C 8.--31. 1. "Reserved_40,Reserved_40" newline hexmask.long.byte 0x4C 0.--7. 1. "ADDR,1TB Addressable 16byte aligned Base Address of the Z Buffer Load base address" line.long 0x50 "RGX_CR_ISP_ZSTORE_BASE_0,Base address in memory of the Z Buffer base address to store into the ISP for non-compressed ZLS formats." hexmask.long 0x50 4.--31. 1. "ADDR,1TB Addressable 16byte aligned Base Address of the Z Buffer Store base address" newline hexmask.long.byte 0x50 0.--3. 1. "Reserved_0,Reserved_0" line.long 0x54 "RGX_CR_ISP_ZSTORE_BASE_1,Base address in memory of the Z Buffer base address to store into the ISP for non-compressed ZLS formats." hexmask.long.tbyte 0x54 8.--31. 1. "Reserved_40,Reserved_40" newline hexmask.long.byte 0x54 0.--7. 1. "ADDR,1TB Addressable 16byte aligned Base Address of the Z Buffer Store base address" line.long 0x58 "RGX_CR_ISP_STENCIL_LOAD_BASE_0,Base address in memory of the Stencil Buffer base address to load into the ISP for non-compressed ZLS formats. This alternate stencil buffer base address is selectable based on the enable bit." hexmask.long 0x58 4.--31. 1. "ADDR,1TB Addressable 16byte aligned Base Address of the Z Buffer Load base address" newline bitfld.long 0x58 1.--3. "Reserved_1,Reserved_1" "0,1,2,3,4,5,6,7" newline bitfld.long 0x58 0. "ENABLE,When set to 1 enables fetching of stencil from a separate base address" "0,1" line.long 0x5C "RGX_CR_ISP_STENCIL_LOAD_BASE_1,Base address in memory of the Stencil Buffer base address to load into the ISP for non-compressed ZLS formats. This alternate stencil buffer base address is selectable based on the enable bit." hexmask.long.tbyte 0x5C 8.--31. 1. "Reserved_40,Reserved_40" newline hexmask.long.byte 0x5C 0.--7. 1. "ADDR,1TB Addressable 16byte aligned Base Address of the Z Buffer Load base address" line.long 0x60 "RGX_CR_ISP_STENCIL_STORE_BASE_0,Base address in memory of the Stencil Buffer base address to store into the ISP for non-compressed ZLS formats. This alternate stencil buffer base address is selectable based on the enable bit." hexmask.long 0x60 4.--31. 1. "ADDR,1TB Addressable 16byte aligned Base Address of the Z Buffer Load base address" newline bitfld.long 0x60 1.--3. "Reserved_1,Reserved_1" "0,1,2,3,4,5,6,7" newline bitfld.long 0x60 0. "ENABLE,When set to 1 enables fetching of stencil from a separate base address" "0,1" line.long 0x64 "RGX_CR_ISP_STENCIL_STORE_BASE_1,Base address in memory of the Stencil Buffer base address to store into the ISP for non-compressed ZLS formats. This alternate stencil buffer base address is selectable based on the enable bit." hexmask.long.tbyte 0x64 8.--31. 1. "Reserved_40,Reserved_40" newline hexmask.long.byte 0x64 0.--7. 1. "ADDR,1TB Addressable 16byte aligned Base Address of the Z Buffer Load base address" line.long 0x68 "RGX_CR_ISP_MASK_LOAD_BASE_0,Base address in memory of the Mask Buffer base address to load into the ISP for non-compressed ZLS formats. This alternate mask buffer base address is selectable based on the enable bit." hexmask.long 0x68 4.--31. 1. "ADDR,1TB Addressable 16byte aligned Base Address of the Z Buffer Load base address" newline bitfld.long 0x68 1.--3. "Reserved_1,Reserved_1" "0,1,2,3,4,5,6,7" newline bitfld.long 0x68 0. "ENABLE,When set to 1 enables fetching of mask from a separate base address" "0,1" line.long 0x6C "RGX_CR_ISP_MASK_LOAD_BASE_1,Base address in memory of the Mask Buffer base address to load into the ISP for non-compressed ZLS formats. This alternate mask buffer base address is selectable based on the enable bit." hexmask.long.tbyte 0x6C 8.--31. 1. "Reserved_40,Reserved_40" newline hexmask.long.byte 0x6C 0.--7. 1. "ADDR,1TB Addressable 16byte aligned Base Address of the Z Buffer Load base address" line.long 0x70 "RGX_CR_ISP_MASK_STORE_BASE_0,Base address in memory of the Mask Buffer base address to store into the ISP for non-compressed ZLS formats. This alternate mask buffer base address is selectable based on the enable bit." hexmask.long 0x70 4.--31. 1. "ADDR,1TB Addressable 16byte aligned Base Address of the Z Buffer Load base address" newline bitfld.long 0x70 1.--3. "Reserved_1,Reserved_1" "0,1,2,3,4,5,6,7" newline bitfld.long 0x70 0. "ENABLE,When set to 1 enables fetching of mask from a separate base address" "0,1" line.long 0x74 "RGX_CR_ISP_MASK_STORE_BASE_1,Base address in memory of the Mask Buffer base address to store into the ISP for non-compressed ZLS formats. This alternate mask buffer base address is selectable based on the enable bit." hexmask.long.tbyte 0x74 8.--31. 1. "Reserved_40,Reserved_40" newline hexmask.long.byte 0x74 0.--7. 1. "ADDR,1TB Addressable 16byte aligned Base Address of the Z Buffer Load base address" repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) group.long ($2+0xF80)++0x3 line.long 0x0 "RGX_CR_ISP_BGOBJDEPTH_$1,The ISP operates by comparing depth values of incoming objects with the results of previous depth compares. in order to make sure there are no unitialised values at the start of the tile or to cover pixels where there are no.." hexmask.long 0x0 0.--31. 1. "VALUE,Note the format in this register has to be consistent with the format defined by ZLS_STORE_FORMAT register. If depth buffer is F32 then the value here should be IEEE 754 single precisoin floating point If depth buffer is /INT16 then the value.." repeat.end group.long 0xF88++0x7 line.long 0x0 "RGX_CR_ISP_BGOBJVALS_0,This register provides enable. mask and stencil information for the hardware background object." hexmask.long.tbyte 0x0 10.--31. 1. "Reserved_10,Reserved_10" newline bitfld.long 0x0 9. "ENABLEBGTAG,When set to 1 at the start of each tile the ISP tag buffer is initialised with the background object tag (default = 1)" "0,1" newline bitfld.long 0x0 8. "MASK,Hardware background object mask plane" "0,1" newline hexmask.long.byte 0x0 0.--7. 1. "STENCIL,Hardware background object stencil" line.long 0x4 "RGX_CR_ISP_BGOBJVALS_1,This register provides enable. mask and stencil information for the hardware background object." hexmask.long 0x4 0.--31. 1. "Reserved_10,Reserved_10" group.long 0xFA0++0x7 line.long 0x0 "RGX_CR_ISP_GRIDOFFSET_0,Sample position grid offset for use when MSAA/ODAA is DISABLED DX (0.0.0.0) OpenGL (0.5.0.5) Acts as the 9th multisample position when MSAA is ENABLED." hexmask.long.tbyte 0x0 8.--31. 1. "Reserved_8,Reserved_8" newline hexmask.long.byte 0x0 4.--7. 1. "GRID_Y,Unsigned sub-pixel offset" newline hexmask.long.byte 0x0 0.--3. 1. "GRID_X,Unsigned sub-pixel offset" line.long 0x4 "RGX_CR_ISP_GRIDOFFSET_1,Sample position grid offset for use when MSAA/ODAA is DISABLED DX (0.0.0.0) OpenGL (0.5.0.5) Acts as the 9th multisample position when MSAA is ENABLED." hexmask.long 0x4 0.--31. 1. "Reserved_8,Reserved_8" repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) group.long ($2+0xFA8)++0x3 line.long 0x0 "RGX_CR_ISP_MULTISAMPLECTL_$1,Sample position grid offset for use in 2x. 4x. 8xMSAA and ODAA modes." hexmask.long.byte 0x0 28.--31. 1. "MSAA_Y3,Unsigned sub-pixel offset for the 4th multisample Y position" newline hexmask.long.byte 0x0 24.--27. 1. "MSAA_X3,Unsigned sub-pixel offset for the 4th multisample X position" newline hexmask.long.byte 0x0 20.--23. 1. "MSAA_Y2,Unsigned sub-pixel offset for the 3rd multisample Y position" newline hexmask.long.byte 0x0 16.--19. 1. "MSAA_X2,Unsigned sub-pixel offset for the 3rd multisample X position" newline hexmask.long.byte 0x0 12.--15. 1. "MSAA_Y1,Unsigned sub-pixel offset for the 2nd multisample Y position" newline hexmask.long.byte 0x0 8.--11. 1. "MSAA_X1,Unsigned sub-pixel offset for the 2nd multisample X position" newline hexmask.long.byte 0x0 4.--7. 1. "MSAA_Y0,Unsigned sub-pixel offset for the 1st multisample Y position" newline hexmask.long.byte 0x0 0.--3. 1. "MSAA_X0,Unsigned sub-pixel offset for the 1st multisample X position" repeat.end group.long 0xFB0++0x2F line.long 0x0 "RGX_CR_ISP_SCISSOR_BASE_0,RGX_CR_ISP_SCISSOR_BASE_0" hexmask.long 0x0 2.--31. 1. "ADDR,1TB range 32-bit aligned base address" newline bitfld.long 0x0 0.--1. "Reserved_0,Reserved_0" "0,1,2,3" line.long 0x4 "RGX_CR_ISP_SCISSOR_BASE_1,RGX_CR_ISP_SCISSOR_BASE_1" hexmask.long.tbyte 0x4 8.--31. 1. "Reserved_40,Reserved_40" newline hexmask.long.byte 0x4 0.--7. 1. "ADDR,1TB range 32-bit aligned base address" line.long 0x8 "RGX_CR_ISP_DBIAS_BASE_0,RGX_CR_ISP_DBIAS_BASE_0" hexmask.long 0x8 2.--31. 1. "ADDR,1TB range 32-bit aligned base address" newline bitfld.long 0x8 0.--1. "Reserved_0,Reserved_0" "0,1,2,3" line.long 0xC "RGX_CR_ISP_DBIAS_BASE_1,RGX_CR_ISP_DBIAS_BASE_1" hexmask.long.tbyte 0xC 8.--31. 1. "Reserved_40,Reserved_40" newline hexmask.long.byte 0xC 0.--7. 1. "ADDR,1TB range 32-bit aligned base address" line.long 0x10 "RGX_CR_ISP_OCLQRY_BASE_0,Base address for occlusion query counter values. For multiple phantom system. base address could be set differently and driver needs to sum up the result from different phantoms which have same occlusion query index." hexmask.long 0x10 4.--31. 1. "ADDR,1TB range 128-bit aligned base address" newline hexmask.long.byte 0x10 0.--3. 1. "Reserved_0,Reserved_0" line.long 0x14 "RGX_CR_ISP_OCLQRY_BASE_1,Base address for occlusion query counter values. For multiple phantom system. base address could be set differently and driver needs to sum up the result from different phantoms which have same occlusion query index." hexmask.long.tbyte 0x14 8.--31. 1. "Reserved_40,Reserved_40" newline hexmask.long.byte 0x14 0.--7. 1. "ADDR,1TB range 128-bit aligned base address" line.long 0x18 "RGX_CR_ISP_PIXEL_BASE_0,Base address for control stream and primitive blocks." hexmask.long 0x18 0.--31. 1. "Reserved_0,Reserved_0" line.long 0x1C "RGX_CR_ISP_PIXEL_BASE_1,Base address for control stream and primitive blocks." hexmask.long.tbyte 0x1C 8.--31. 1. "Reserved_40,Reserved_40" newline hexmask.long.byte 0x1C 2.--7. 1. "ADDR,1TB range 16GB granularity" newline bitfld.long 0x1C 0.--1. "Reserved_0,Reserved_0" "0,1,2,3" line.long 0x20 "RGX_CR_ISP_ZLS_PIXELS_0,screen size in pixel numbers for ZLS." bitfld.long 0x20 30.--31. "Reserved_30,Reserved_30" "0,1,2,3" newline hexmask.long.word 0x20 15.--29. 1. "Y,Display width of Y in pixels minus one. 0x000 1 pixel 0x001 2 pixels ... 0x7FFF 1024*32 pixels. Subtile only supports for non-msaa mode depth load/store so For non-msaa mode if framebuffer compression or separate mask or separate stencil is.." newline hexmask.long.word 0x20 0.--14. 1. "X,Display width of X in pixels minus one. 0x000 1 pixel 0x001 2 pixels ... 0x7FFF 1024*32 pixels. Subtile only supports for non-msaa mode depth load/store so For non-msaa mode if framebuffer compression or separate mask or separate stencil is.." line.long 0x24 "RGX_CR_ISP_ZLS_PIXELS_1,screen size in pixel numbers for ZLS." hexmask.long 0x24 0.--31. 1. "Reserved_30,Reserved_30" line.long 0x28 "RGX_CR_ISP_CTL2_0,RGX_CR_ISP_CTL2_0" hexmask.long 0x28 5.--31. 1. "Reserved_5,Reserved_5" newline hexmask.long.byte 0x28 0.--4. 1. "DEPTHBUFFERS_IN_USE,Specifies the number of depth buffers to use" line.long 0x2C "RGX_CR_ISP_CTL2_1,RGX_CR_ISP_CTL2_1" hexmask.long 0x2C 0.--31. 1. "Reserved_5,Reserved_5" wgroup.long 0x1000++0x7 line.long 0x0 "RGX_CR_ISP_START_CONTEXT_STORE_0,Writing '1' to this register initiates a 3D context store" hexmask.long 0x0 1.--31. 1. "Reserved_1,Reserved_1" newline bitfld.long 0x0 0. "PULSE,PULSE" "0,1" line.long 0x4 "RGX_CR_ISP_START_CONTEXT_STORE_1,Writing '1' to this register initiates a 3D context store" hexmask.long 0x4 0.--31. 1. "Reserved_1,Reserved_1" rgroup.long 0x1008++0xF line.long 0x0 "RGX_CR_ISP_STORE0_0,ISP context store register" bitfld.long 0x0 31. "Reserved_31,Reserved_31" "0,1" newline bitfld.long 0x0 30. "ACTIVE,ACTIVE" "0,1" newline bitfld.long 0x0 29. "EOR,EOR" "0,1" newline bitfld.long 0x0 28. "TILE_LAST,TILE_LAST" "0,1" newline hexmask.long.byte 0x0 24.--27. 1. "MT,MT" newline bitfld.long 0x0 22.--23. "Reserved_22,Reserved_22" "0,1,2,3" newline hexmask.long.word 0x0 12.--21. 1. "TILE_X,TILE_X" newline bitfld.long 0x0 10.--11. "Reserved_10,Reserved_10" "0,1,2,3" newline hexmask.long.word 0x0 0.--9. 1. "TILE_Y,TILE_Y" line.long 0x4 "RGX_CR_ISP_STORE0_1,ISP context store register" hexmask.long 0x4 0.--31. 1. "Reserved_31,Reserved_31" line.long 0x8 "RGX_CR_ISP_STORE1_0,ISP context store register" bitfld.long 0x8 31. "Reserved_31,Reserved_31" "0,1" newline bitfld.long 0x8 30. "ACTIVE,ACTIVE" "0,1" newline bitfld.long 0x8 29. "EOR,EOR" "0,1" newline bitfld.long 0x8 28. "TILE_LAST,TILE_LAST" "0,1" newline hexmask.long.byte 0x8 24.--27. 1. "MT,MT" newline bitfld.long 0x8 22.--23. "Reserved_22,Reserved_22" "0,1,2,3" newline hexmask.long.word 0x8 12.--21. 1. "TILE_X,TILE_X" newline bitfld.long 0x8 10.--11. "Reserved_10,Reserved_10" "0,1,2,3" newline hexmask.long.word 0x8 0.--9. 1. "TILE_Y,TILE_Y" line.long 0xC "RGX_CR_ISP_STORE1_1,ISP context store register" hexmask.long 0xC 0.--31. 1. "Reserved_31,Reserved_31" group.long 0x1020++0xF line.long 0x0 "RGX_CR_ISP_RESUME0_0,ISP context resume register" hexmask.long.word 0x0 22.--31. 1. "Reserved_22,Reserved_22" newline hexmask.long.word 0x0 12.--21. 1. "TILE_X,TILE_X" newline bitfld.long 0x0 10.--11. "Reserved_10,Reserved_10" "0,1,2,3" newline hexmask.long.word 0x0 0.--9. 1. "TILE_Y,TILE_Y" line.long 0x4 "RGX_CR_ISP_RESUME0_1,ISP context resume register" hexmask.long 0x4 0.--31. 1. "Reserved_22,Reserved_22" line.long 0x8 "RGX_CR_ISP_RESUME1_0,ISP context resume register" hexmask.long.word 0x8 22.--31. 1. "Reserved_22,Reserved_22" newline hexmask.long.word 0x8 12.--21. 1. "TILE_X,TILE_X" newline bitfld.long 0x8 10.--11. "Reserved_10,Reserved_10" "0,1,2,3" newline hexmask.long.word 0x8 0.--9. 1. "TILE_Y,TILE_Y" line.long 0xC "RGX_CR_ISP_RESUME1_1,ISP context resume register" hexmask.long 0xC 0.--31. 1. "Reserved_22,Reserved_22" rgroup.long 0x1038++0xF line.long 0x0 "RGX_CR_ISP_STATUS_0,ISP status registers" hexmask.long 0x0 3.--31. 1. "Reserved_3,Reserved_3" newline bitfld.long 0x0 2. "SPLIT_MAX,Split Render Maximum Threshold has been Exceeded" "0,1" newline bitfld.long 0x0 1. "ACTIVE,ISP is Active first tile in the render has been assigned" "0,1" newline bitfld.long 0x0 0. "EOR,ISP has assigned the last tile in the render" "0,1" line.long 0x4 "RGX_CR_ISP_STATUS_1,ISP status registers" hexmask.long 0x4 0.--31. 1. "Reserved_3,Reserved_3" line.long 0x8 "RGX_CR_RAST_IDLE_0,RGX_CR_RAST_IDLE_0" hexmask.long 0x8 5.--31. 1. "Reserved_5,Reserved_5" newline bitfld.long 0x8 4. "TFPU,TFPU Module IDLE" "0,1" newline bitfld.long 0x8 3. "TPF,TPF Module IDLE" "0,1" newline bitfld.long 0x8 2. "IFPU,IFPU Module IDLE" "0,1" newline bitfld.long 0x8 1. "ISP,ISP Module IDLE" "0,1" newline bitfld.long 0x8 0. "IPF,IPF Module IDLE" "0,1" line.long 0xC "RGX_CR_RAST_IDLE_1,RGX_CR_RAST_IDLE_1" hexmask.long 0xC 0.--31. 1. "Reserved_5,Reserved_5" repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) rgroup.long ($2+0x1048)++0x3 line.long 0x0 "RGX_CR_ISP_PWR_NUM_$1,RGX_CR_ISP_PWR_NUM_0" hexmask.long 0x0 0.--31. 1. "PIXELS_PROCESS,Number of depth tested pixels(non-MSAA) or samples(MSAA) processed" repeat.end repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) rgroup.long ($2+0x1058)++0x3 line.long 0x0 "RGX_CR_TFPU_PWR_NUM_$1,RGX_CR_TFPU_PWR_NUM_0" hexmask.long 0x0 0.--31. 1. "PRIMITIVES_PROCESSED,Number of primitives processed" repeat.end repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) group.long ($2+0x11D0)++0x3 line.long 0x0 "RGX_CR_ISP_MERGE_LOWER_X_$1,Used by the IFPU to generate the angle vectors used for triangle merging" hexmask.long 0x0 0.--31. 1. "VALUE,tan(15)/16k screen size" repeat.end repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) group.long ($2+0x11D8)++0x3 line.long 0x0 "RGX_CR_ISP_MERGE_LOWER_Y_$1,Used by the IFPU to generate the angle vectors used for triangle merging" hexmask.long 0x0 0.--31. 1. "VALUE,tan(15)/16k screen size" repeat.end repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) group.long ($2+0x11E0)++0x3 line.long 0x0 "RGX_CR_ISP_MERGE_UPPER_X_$1,RGX_CR_ISP_MERGE_UPPER_X_0" hexmask.long 0x0 0.--31. 1. "VALUE,tan(60)/16k screen size" repeat.end repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) group.long ($2+0x11E8)++0x3 line.long 0x0 "RGX_CR_ISP_MERGE_UPPER_Y_$1,Used by the IFPU to generate the angle vectors used for triangle merging" hexmask.long 0x0 0.--31. 1. "VALUE,tan(60)/16k screen size" repeat.end repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) group.long ($2+0x11F0)++0x3 line.long 0x0 "RGX_CR_ISP_MERGE_SCALE_X_$1,RGX_CR_ISP_MERGE_SCALE_X_0" hexmask.long 0x0 0.--31. 1. "VALUE,16 * default screen size of 16k" repeat.end repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) group.long ($2+0x11F8)++0x3 line.long 0x0 "RGX_CR_ISP_MERGE_SCALE_Y_$1,Used by the IFPU to generate the angle vectors used for triangle merging" hexmask.long 0x0 0.--31. 1. "VALUE,16 * default screen size of 16k" repeat.end group.long 0x1200++0x57 line.long 0x0 "RGX_CR_BIF_CAT_BASE0_0,RGX_CR_BIF_CAT_BASE0_0" hexmask.long.tbyte 0x0 12.--31. 1. "ADDR,ADDR" newline hexmask.long.word 0x0 0.--11. 1. "Reserved_0,Reserved_0" line.long 0x4 "RGX_CR_BIF_CAT_BASE0_1,RGX_CR_BIF_CAT_BASE0_1" hexmask.long.tbyte 0x4 8.--31. 1. "Reserved_40,Reserved_40" newline hexmask.long.byte 0x4 0.--7. 1. "ADDR,ADDR" line.long 0x8 "RGX_CR_BIF_CAT_BASE1_0,RGX_CR_BIF_CAT_BASE1_0" hexmask.long.tbyte 0x8 12.--31. 1. "ADDR,ADDR" newline hexmask.long.word 0x8 0.--11. 1. "Reserved_0,Reserved_0" line.long 0xC "RGX_CR_BIF_CAT_BASE1_1,RGX_CR_BIF_CAT_BASE1_1" hexmask.long.tbyte 0xC 8.--31. 1. "Reserved_40,Reserved_40" newline hexmask.long.byte 0xC 0.--7. 1. "ADDR,ADDR" line.long 0x10 "RGX_CR_BIF_CAT_BASE2_0,RGX_CR_BIF_CAT_BASE2_0" hexmask.long.tbyte 0x10 12.--31. 1. "ADDR,ADDR" newline hexmask.long.word 0x10 0.--11. 1. "Reserved_0,Reserved_0" line.long 0x14 "RGX_CR_BIF_CAT_BASE2_1,RGX_CR_BIF_CAT_BASE2_1" hexmask.long.tbyte 0x14 8.--31. 1. "Reserved_40,Reserved_40" newline hexmask.long.byte 0x14 0.--7. 1. "ADDR,ADDR" line.long 0x18 "RGX_CR_BIF_CAT_BASE3_0,RGX_CR_BIF_CAT_BASE3_0" hexmask.long.tbyte 0x18 12.--31. 1. "ADDR,ADDR" newline hexmask.long.word 0x18 0.--11. 1. "Reserved_0,Reserved_0" line.long 0x1C "RGX_CR_BIF_CAT_BASE3_1,RGX_CR_BIF_CAT_BASE3_1" hexmask.long.tbyte 0x1C 8.--31. 1. "Reserved_40,Reserved_40" newline hexmask.long.byte 0x1C 0.--7. 1. "ADDR,ADDR" line.long 0x20 "RGX_CR_BIF_CAT_BASE4_0,RGX_CR_BIF_CAT_BASE4_0" hexmask.long.tbyte 0x20 12.--31. 1. "ADDR,ADDR" newline hexmask.long.word 0x20 0.--11. 1. "Reserved_0,Reserved_0" line.long 0x24 "RGX_CR_BIF_CAT_BASE4_1,RGX_CR_BIF_CAT_BASE4_1" hexmask.long.tbyte 0x24 8.--31. 1. "Reserved_40,Reserved_40" newline hexmask.long.byte 0x24 0.--7. 1. "ADDR,ADDR" line.long 0x28 "RGX_CR_BIF_CAT_BASE5_0,RGX_CR_BIF_CAT_BASE5_0" hexmask.long.tbyte 0x28 12.--31. 1. "ADDR,ADDR" newline hexmask.long.word 0x28 0.--11. 1. "Reserved_0,Reserved_0" line.long 0x2C "RGX_CR_BIF_CAT_BASE5_1,RGX_CR_BIF_CAT_BASE5_1" hexmask.long.tbyte 0x2C 8.--31. 1. "Reserved_40,Reserved_40" newline hexmask.long.byte 0x2C 0.--7. 1. "ADDR,ADDR" line.long 0x30 "RGX_CR_BIF_CAT_BASE6_0,RGX_CR_BIF_CAT_BASE6_0" hexmask.long.tbyte 0x30 12.--31. 1. "ADDR,ADDR" newline hexmask.long.word 0x30 0.--11. 1. "Reserved_0,Reserved_0" line.long 0x34 "RGX_CR_BIF_CAT_BASE6_1,RGX_CR_BIF_CAT_BASE6_1" hexmask.long.tbyte 0x34 8.--31. 1. "Reserved_40,Reserved_40" newline hexmask.long.byte 0x34 0.--7. 1. "ADDR,ADDR" line.long 0x38 "RGX_CR_BIF_CAT_BASE7_0,RGX_CR_BIF_CAT_BASE7_0" hexmask.long.tbyte 0x38 12.--31. 1. "ADDR,ADDR" newline hexmask.long.word 0x38 0.--11. 1. "Reserved_0,Reserved_0" line.long 0x3C "RGX_CR_BIF_CAT_BASE7_1,RGX_CR_BIF_CAT_BASE7_1" hexmask.long.tbyte 0x3C 8.--31. 1. "Reserved_40,Reserved_40" newline hexmask.long.byte 0x3C 0.--7. 1. "ADDR,ADDR" line.long 0x40 "RGX_CR_BIF_CAT_BASE_INDEX_0,Index registers per data master. Byte aligned fields to allow byte-masked access" hexmask.long.word 0x40 22.--31. 1. "Reserved_22,Reserved_22" newline bitfld.long 0x40 19.--21. "TDM,Catalogue Base number for TDM data master" "0,1,2,3,4,5,6,7" newline bitfld.long 0x40 16.--18. "CDM,Catalogue Base number for CDM data master" "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x40 11.--15. 1. "Reserved_11,Reserved_11" newline bitfld.long 0x40 8.--10. "PIXEL,Catalogue Base number for PIXEL data master" "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x40 3.--7. 1. "Reserved_3,Reserved_3" newline bitfld.long 0x40 0.--2. "TA,Catalogue Base number for TA data master" "0,1,2,3,4,5,6,7" line.long 0x44 "RGX_CR_BIF_CAT_BASE_INDEX_1,Index registers per data master. Byte aligned fields to allow byte-masked access" hexmask.long 0x44 3.--31. 1. "Reserved_35,Reserved_35" newline bitfld.long 0x44 0.--2. "HOST,Catalogue Base number for HOST data master" "0,1,2,3,4,5,6,7" line.long 0x48 "RGX_CR_BIF_PM_CAT_BASE_VCE0_0,PM catalogue base address for VCE context 0" hexmask.long.tbyte 0x48 12.--31. 1. "ADDR,ADDR" newline hexmask.long.word 0x48 2.--11. 1. "Reserved_2,Reserved_2" newline bitfld.long 0x48 1. "WRAP,Indicates address space has been fully allocated" "0,1" newline bitfld.long 0x48 0. "VALID,VALID" "0,1" line.long 0x4C "RGX_CR_BIF_PM_CAT_BASE_VCE0_1,PM catalogue base address for VCE context 0" hexmask.long.byte 0x4C 28.--31. 1. "Reserved_60,Reserved_60" newline hexmask.long.tbyte 0x4C 8.--27. 1. "INIT_PAGE,INIT_PAGE" newline hexmask.long.byte 0x4C 0.--7. 1. "ADDR,ADDR" line.long 0x50 "RGX_CR_BIF_PM_CAT_BASE_TE0_0,PM catalogue base address for TE context 0" hexmask.long.tbyte 0x50 12.--31. 1. "ADDR,ADDR" newline hexmask.long.word 0x50 2.--11. 1. "Reserved_2,Reserved_2" newline bitfld.long 0x50 1. "WRAP,WRAP" "0,1" newline bitfld.long 0x50 0. "VALID,VALID" "0,1" line.long 0x54 "RGX_CR_BIF_PM_CAT_BASE_TE0_1,PM catalogue base address for TE context 0" hexmask.long.byte 0x54 28.--31. 1. "Reserved_60,Reserved_60" newline hexmask.long.tbyte 0x54 8.--27. 1. "INIT_PAGE,INIT_PAGE" newline hexmask.long.byte 0x54 0.--7. 1. "ADDR,ADDR" group.long 0x1260++0x17 line.long 0x0 "RGX_CR_BIF_PM_CAT_BASE_ALIST0_0,PM catalogue base address for ALIST context 0" hexmask.long.tbyte 0x0 12.--31. 1. "ADDR,ADDR" newline hexmask.long.word 0x0 2.--11. 1. "Reserved_2,Reserved_2" newline bitfld.long 0x0 1. "WRAP,WRAP" "0,1" newline bitfld.long 0x0 0. "VALID,VALID" "0,1" line.long 0x4 "RGX_CR_BIF_PM_CAT_BASE_ALIST0_1,PM catalogue base address for ALIST context 0" hexmask.long.byte 0x4 28.--31. 1. "Reserved_60,Reserved_60" newline hexmask.long.tbyte 0x4 8.--27. 1. "INIT_PAGE,INIT_PAGE" newline hexmask.long.byte 0x4 0.--7. 1. "ADDR,ADDR" line.long 0x8 "RGX_CR_BIF_PM_CAT_BASE_VCE1_0,PM catalogue base address for VCE context 1" hexmask.long.tbyte 0x8 12.--31. 1. "ADDR,ADDR" newline hexmask.long.word 0x8 2.--11. 1. "Reserved_2,Reserved_2" newline bitfld.long 0x8 1. "WRAP,WRAP" "0,1" newline bitfld.long 0x8 0. "VALID,VALID" "0,1" line.long 0xC "RGX_CR_BIF_PM_CAT_BASE_VCE1_1,PM catalogue base address for VCE context 1" hexmask.long.byte 0xC 28.--31. 1. "Reserved_60,Reserved_60" newline hexmask.long.tbyte 0xC 8.--27. 1. "INIT_PAGE,INIT_PAGE" newline hexmask.long.byte 0xC 0.--7. 1. "ADDR,ADDR" line.long 0x10 "RGX_CR_BIF_PM_CAT_BASE_TE1_0,PM catalogue base address for TE context 1" hexmask.long.tbyte 0x10 12.--31. 1. "ADDR,ADDR" newline hexmask.long.word 0x10 2.--11. 1. "Reserved_2,Reserved_2" newline bitfld.long 0x10 1. "WRAP,WRAP" "0,1" newline bitfld.long 0x10 0. "VALID,VALID" "0,1" line.long 0x14 "RGX_CR_BIF_PM_CAT_BASE_TE1_1,PM catalogue base address for TE context 1" hexmask.long.byte 0x14 28.--31. 1. "Reserved_60,Reserved_60" newline hexmask.long.tbyte 0x14 8.--27. 1. "INIT_PAGE,INIT_PAGE" newline hexmask.long.byte 0x14 0.--7. 1. "ADDR,ADDR" group.long 0x1280++0x7 line.long 0x0 "RGX_CR_BIF_PM_CAT_BASE_ALIST1_0,PM catalogue base address for ALIST context 1" hexmask.long.tbyte 0x0 12.--31. 1. "ADDR,ADDR" newline hexmask.long.word 0x0 2.--11. 1. "Reserved_2,Reserved_2" newline bitfld.long 0x0 1. "WRAP,WRAP" "0,1" newline bitfld.long 0x0 0. "VALID,VALID" "0,1" line.long 0x4 "RGX_CR_BIF_PM_CAT_BASE_ALIST1_1,PM catalogue base address for ALIST context 1" hexmask.long.byte 0x4 28.--31. 1. "Reserved_60,Reserved_60" newline hexmask.long.tbyte 0x4 8.--27. 1. "INIT_PAGE,INIT_PAGE" newline hexmask.long.byte 0x4 0.--7. 1. "ADDR,ADDR" rgroup.long 0x1288++0x7 line.long 0x0 "RGX_CR_BIF_MMU_ENTRY_STATUS_0,Status of pending entry" hexmask.long.tbyte 0x0 12.--31. 1. "ADDRESS,Virtual 4KB address" newline hexmask.long.byte 0x0 8.--11. 1. "Reserved_8,Reserved_8" newline hexmask.long.byte 0x0 4.--7. 1. "CAT_BASE,Catalogue base address number" newline bitfld.long 0x0 2.--3. "Reserved_2,Reserved_2" "0,1,2,3" newline bitfld.long 0x0 0.--1. "DATA_TYPE,MMU data type '00' = PT '01' = PD '10' = PC" "0,1,2,3" line.long 0x4 "RGX_CR_BIF_MMU_ENTRY_STATUS_1,Status of pending entry" hexmask.long.tbyte 0x4 8.--31. 1. "Reserved_40,Reserved_40" newline hexmask.long.byte 0x4 0.--7. 1. "ADDRESS,Virtual 4KB address" group.long 0x1290++0x7 line.long 0x0 "RGX_CR_BIF_MMU_ENTRY_0,Indicates MMU is waiting on the driver to map an entry" hexmask.long 0x0 2.--31. 1. "Reserved_2,Reserved_2" newline bitfld.long 0x0 1. "ENABLE,When set PENDING will trigger an interrupt back to the host CPU (bypassing the FW)" "0,1" newline bitfld.long 0x0 0. "PENDING,PENDING" "0,1" line.long 0x4 "RGX_CR_BIF_MMU_ENTRY_1,Indicates MMU is waiting on the driver to map an entry" hexmask.long 0x4 0.--31. 1. "Reserved_2,Reserved_2" group.long 0x12A0++0xF line.long 0x0 "RGX_CR_BIF_CTRL_INVAL_0,Invalidation bits allowing BIF/MMU to clear when invalidation complete" hexmask.long 0x0 4.--31. 1. "Reserved_4,Reserved_4" newline bitfld.long 0x0 3. "TLB1,TLB1" "0,1" newline bitfld.long 0x0 2. "PC,PC" "0,1" newline bitfld.long 0x0 1. "PD,PD" "0,1" newline bitfld.long 0x0 0. "PT,PT" "0,1" line.long 0x4 "RGX_CR_BIF_CTRL_INVAL_1,Invalidation bits allowing BIF/MMU to clear when invalidation complete" hexmask.long 0x4 0.--31. 1. "Reserved_4,Reserved_4" line.long 0x8 "RGX_CR_BIF_CTRL_0,Miscellaneous controls" hexmask.long.tbyte 0x8 9.--31. 1. "Reserved_9,Reserved_9" newline bitfld.long 0x8 8. "PAUSE_MMU_BIF4,Stalls BIF4 input to MMU" "0,1" newline bitfld.long 0x8 7. "ENABLE_MMU_QUEUE_BYPASS,Enables bypassing of the MMU queue for cache hits" "0,1" newline bitfld.long 0x8 6. "ENABLE_MMU_AUTO_PREFETCH,Enables automatic prefetching based on incoming requests" "0,1" newline bitfld.long 0x8 5. "PAUSE_MMU_BIF3,Stalls BIF3 input to MMU" "0,1" newline bitfld.long 0x8 4. "PAUSE_MMU_BIF2,Stalls BIF2 input to MMU" "0,1" newline bitfld.long 0x8 3. "PAUSE_BIF1,Stalls BIF1 pipeline" "0,1" newline bitfld.long 0x8 2. "PAUSE_MMU_PM,Stalls PM input to MMU" "0,1" newline bitfld.long 0x8 1. "PAUSE_MMU_BIF1,Stalls BIF1 input to MMU" "0,1" newline bitfld.long 0x8 0. "PAUSE_MMU_BIF0,Stalls BIF0 input to MMU" "0,1" line.long 0xC "RGX_CR_BIF_CTRL_1,Miscellaneous controls" hexmask.long 0xC 0.--31. 1. "Reserved_9,Reserved_9" rgroup.long 0x12B0++0x27 line.long 0x0 "RGX_CR_BIF_FAULT_BANK0_MMU_STATUS_0,Indicates a fault has occurred on bank 0 and provides details of fault" hexmask.long.word 0x0 16.--31. 1. "Reserved_16,Reserved_16" newline hexmask.long.byte 0x0 12.--15. 1. "CAT_BASE,Catalogue base address number" newline bitfld.long 0x0 11. "Reserved_11,Reserved_11" "0,1" newline bitfld.long 0x0 8.--10. "PAGE_SIZE,Page size" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 7. "Reserved_7,Reserved_7" "0,1" newline bitfld.long 0x0 5.--6. "DATA_TYPE,MMU data type that was invalid (on valid fault)" "0,1,2,3" newline bitfld.long 0x0 4. "FAULT_RO,Indicates read-only fault('1') or valid fault('0')" "0,1" newline bitfld.long 0x0 3. "Reserved_3,Reserved_3" "0,1" newline bitfld.long 0x0 2. "FAULT_PM_META_RO,Indicates pm/meta protected region fault" "0,1" newline bitfld.long 0x0 1. "Reserved_1,Reserved_1" "0,1" newline bitfld.long 0x0 0. "FAULT,Indicates a fault has occured" "0,1" line.long 0x4 "RGX_CR_BIF_FAULT_BANK0_MMU_STATUS_1,Indicates a fault has occurred on bank 0 and provides details of fault" hexmask.long 0x4 0.--31. 1. "Reserved_16,Reserved_16" line.long 0x8 "RGX_CR_BIF_FAULT_BANK0_REQ_STATUS_0,Provides details of the request that faulted on bank 0" hexmask.long 0x8 4.--31. 1. "ADDRESS,ADDRESS" newline hexmask.long.byte 0x8 0.--3. 1. "Reserved_0,Reserved_0" line.long 0xC "RGX_CR_BIF_FAULT_BANK0_REQ_STATUS_1,Provides details of the request that faulted on bank 0" hexmask.long.word 0xC 21.--31. 1. "Reserved_53,Reserved_53" newline bitfld.long 0xC 20. "RNW,RNW" "0,1" newline hexmask.long.byte 0xC 14.--19. 1. "TAG_SB,TAG_SB" newline hexmask.long.byte 0xC 8.--13. 1. "TAG_ID,TAG_ID" newline hexmask.long.byte 0xC 0.--7. 1. "ADDRESS,ADDRESS" line.long 0x10 "RGX_CR_BIF_FAULT_BANK1_MMU_STATUS_0,Indicates a fault has occurred on bank 1 and provides details of fault" hexmask.long.word 0x10 16.--31. 1. "Reserved_16,Reserved_16" newline hexmask.long.byte 0x10 12.--15. 1. "CAT_BASE,Catalogue base address number" newline bitfld.long 0x10 11. "Reserved_11,Reserved_11" "0,1" newline bitfld.long 0x10 8.--10. "PAGE_SIZE,Page size" "0,1,2,3,4,5,6,7" newline bitfld.long 0x10 7. "Reserved_7,Reserved_7" "0,1" newline bitfld.long 0x10 5.--6. "DATA_TYPE,MMU data type that was invalid (on valid fault)" "0,1,2,3" newline bitfld.long 0x10 4. "FAULT_RO,Indicates read-only fault('1') of valid fault('0')" "0,1" newline bitfld.long 0x10 3. "Reserved_3,Reserved_3" "0,1" newline bitfld.long 0x10 2. "FAULT_PM_META_RO,Indicates pm/meta protected region fault" "0,1" newline bitfld.long 0x10 1. "Reserved_1,Reserved_1" "0,1" newline bitfld.long 0x10 0. "FAULT,Indicates a fault has occured" "0,1" line.long 0x14 "RGX_CR_BIF_FAULT_BANK1_MMU_STATUS_1,Indicates a fault has occurred on bank 1 and provides details of fault" hexmask.long 0x14 0.--31. 1. "Reserved_16,Reserved_16" line.long 0x18 "RGX_CR_BIF_FAULT_BANK1_REQ_STATUS_0,Provides details of the request that faulted on bank 1" hexmask.long 0x18 4.--31. 1. "ADDRESS,ADDRESS" newline hexmask.long.byte 0x18 0.--3. 1. "Reserved_0,Reserved_0" line.long 0x1C "RGX_CR_BIF_FAULT_BANK1_REQ_STATUS_1,Provides details of the request that faulted on bank 1" hexmask.long.word 0x1C 19.--31. 1. "Reserved_51,Reserved_51" newline bitfld.long 0x1C 18. "RNW,RNW" "0,1" newline hexmask.long.byte 0x1C 12.--17. 1. "TAG_SB,TAG_SB" newline hexmask.long.byte 0x1C 8.--11. 1. "TAG_ID,TAG_ID" newline hexmask.long.byte 0x1C 0.--7. 1. "ADDRESS,ADDRESS" line.long 0x20 "RGX_CR_BIF_MMU_STATUS_0,General MMU status" bitfld.long 0x20 29.--31. "Reserved_29,Reserved_29" "0,1,2,3,4,5,6,7" newline bitfld.long 0x20 28. "PM_FAULT,PM_FAULT" "0,1" newline hexmask.long.byte 0x20 20.--27. 1. "PC_DATA,PC_DATA" newline hexmask.long.byte 0x20 12.--19. 1. "PD_DATA,PD_DATA" newline hexmask.long.byte 0x20 4.--11. 1. "PT_DATA,PT_DATA" newline bitfld.long 0x20 3. "Reserved_3,Reserved_3" "0,1" newline bitfld.long 0x20 2. "STALLED,STALLED" "0,1" newline bitfld.long 0x20 1. "PAUSED,PAUSED" "0,1" newline bitfld.long 0x20 0. "BUSY,BUSY" "0,1" line.long 0x24 "RGX_CR_BIF_MMU_STATUS_1,General MMU status" hexmask.long 0x24 0.--31. 1. "Reserved_29,Reserved_29" group.long 0x12D8++0x3F line.long 0x0 "RGX_CR_BIF_TILING_CFG0_0,This register defines 8 RANGEs in which BIF Tiling can be configured. Each RANGE is given a Stride and a MIN and MAX 4KB aligned address to define the region of Address Space to be tiled. The BIF_TILING_CAT_BASE_INDEX register is.." hexmask.long.byte 0x0 28.--31. 1. "Reserved_28,Reserved_28" newline hexmask.long 0x0 0.--27. 1. "MIN_ADDRESS,4KB aligned min address for tiling" line.long 0x4 "RGX_CR_BIF_TILING_CFG0_1,This register defines 8 RANGEs in which BIF Tiling can be configured. Each RANGE is given a Stride and a MIN and MAX 4KB aligned address to define the region of Address Space to be tiled. The BIF_TILING_CAT_BASE_INDEX register is.." bitfld.long 0x4 29.--31. "XSTRIDE,defines x tile stride. The value in the register is equal to log2(number of tiles in x)-1 e. g. a value of 0 gives 2 x-tiles and a value of 3 gives 16 x-tiles" "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 28. "ENABLE,enables tiling range" "0,1" newline hexmask.long 0x4 0.--27. 1. "MAX_ADDRESS,4KB aligned max address for tiling" line.long 0x8 "RGX_CR_BIF_TILING_CFG1_0,This register defines 8 RANGEs in which BIF Tiling can be configured. Each RANGE is given a Stride and a MIN and MAX 4KB aligned address to define the region of Address Space to be tiled. The BIF_TILING_CAT_BASE_INDEX register is.." hexmask.long.byte 0x8 28.--31. 1. "Reserved_28,Reserved_28" newline hexmask.long 0x8 0.--27. 1. "MIN_ADDRESS,4KB aligned min address for tiling" line.long 0xC "RGX_CR_BIF_TILING_CFG1_1,This register defines 8 RANGEs in which BIF Tiling can be configured. Each RANGE is given a Stride and a MIN and MAX 4KB aligned address to define the region of Address Space to be tiled. The BIF_TILING_CAT_BASE_INDEX register is.." bitfld.long 0xC 29.--31. "XSTRIDE,defines x tile stride. The value in the register is equal to log2(number of tiles in x)-1 e. g. a value of 0 gives 2 x-tiles and a value of 3 gives 16 x-tiles" "0,1,2,3,4,5,6,7" newline bitfld.long 0xC 28. "ENABLE,enables tiling range" "0,1" newline hexmask.long 0xC 0.--27. 1. "MAX_ADDRESS,4KB aligned max address for tiling" line.long 0x10 "RGX_CR_BIF_TILING_CFG2_0,This register defines 8 RANGEs in which BIF Tiling can be configured. Each RANGE is given a Stride and a MIN and MAX 4KB aligned address to define the region of Address Space to be tiled. The BIF_TILING_CAT_BASE_INDEX register is.." hexmask.long.byte 0x10 28.--31. 1. "Reserved_28,Reserved_28" newline hexmask.long 0x10 0.--27. 1. "MIN_ADDRESS,4KB aligned min address for tiling" line.long 0x14 "RGX_CR_BIF_TILING_CFG2_1,This register defines 8 RANGEs in which BIF Tiling can be configured. Each RANGE is given a Stride and a MIN and MAX 4KB aligned address to define the region of Address Space to be tiled. The BIF_TILING_CAT_BASE_INDEX register is.." bitfld.long 0x14 29.--31. "XSTRIDE,defines x tile stride. The value in the register is equal to log2(number of tiles in x)-1 e. g. a value of 0 gives 2 x-tiles and a value of 3 gives 16 x-tiles" "0,1,2,3,4,5,6,7" newline bitfld.long 0x14 28. "ENABLE,enables tiling range" "0,1" newline hexmask.long 0x14 0.--27. 1. "MAX_ADDRESS,4KB aligned max address for tiling" line.long 0x18 "RGX_CR_BIF_TILING_CFG3_0,This register defines 8 RANGEs in which BIF Tiling can be configured. Each RANGE is given a Stride and a MIN and MAX 4KB aligned address to define the region of Address Space to be tiled. The BIF_TILING_CAT_BASE_INDEX register is.." hexmask.long.byte 0x18 28.--31. 1. "Reserved_28,Reserved_28" newline hexmask.long 0x18 0.--27. 1. "MIN_ADDRESS,4KB aligned min address for tiling" line.long 0x1C "RGX_CR_BIF_TILING_CFG3_1,This register defines 8 RANGEs in which BIF Tiling can be configured. Each RANGE is given a Stride and a MIN and MAX 4KB aligned address to define the region of Address Space to be tiled. The BIF_TILING_CAT_BASE_INDEX register is.." bitfld.long 0x1C 29.--31. "XSTRIDE,defines x tile stride. The value in the register is equal to log2(number of tiles in x)-1 e. g. a value of 0 gives 2 x-tiles and a value of 3 gives 16 x-tiles" "0,1,2,3,4,5,6,7" newline bitfld.long 0x1C 28. "ENABLE,enables tiling range" "0,1" newline hexmask.long 0x1C 0.--27. 1. "MAX_ADDRESS,4KB aligned max address for tiling" line.long 0x20 "RGX_CR_BIF_TILING_CFG4_0,This register defines 8 RANGEs in which BIF Tiling can be configured. Each RANGE is given a Stride and a MIN and MAX 4KB aligned address to define the region of Address Space to be tiled. The BIF_TILING_CAT_BASE_INDEX register is.." hexmask.long.byte 0x20 28.--31. 1. "Reserved_28,Reserved_28" newline hexmask.long 0x20 0.--27. 1. "MIN_ADDRESS,4KB aligned min address for tiling" line.long 0x24 "RGX_CR_BIF_TILING_CFG4_1,This register defines 8 RANGEs in which BIF Tiling can be configured. Each RANGE is given a Stride and a MIN and MAX 4KB aligned address to define the region of Address Space to be tiled. The BIF_TILING_CAT_BASE_INDEX register is.." bitfld.long 0x24 29.--31. "XSTRIDE,defines x tile stride. The value in the register is equal to log2(number of tiles in x)-1 e. g. a value of 0 gives 2 x-tiles and a value of 3 gives 16 x-tiles" "0,1,2,3,4,5,6,7" newline bitfld.long 0x24 28. "ENABLE,enables tiling range" "0,1" newline hexmask.long 0x24 0.--27. 1. "MAX_ADDRESS,4KB aligned max address for tiling" line.long 0x28 "RGX_CR_BIF_TILING_CFG5_0,This register defines 8 RANGEs in which BIF Tiling can be configured. Each RANGE is given a Stride and a MIN and MAX 4KB aligned address to define the region of Address Space to be tiled. The BIF_TILING_CAT_BASE_INDEX register is.." hexmask.long.byte 0x28 28.--31. 1. "Reserved_28,Reserved_28" newline hexmask.long 0x28 0.--27. 1. "MIN_ADDRESS,4KB aligned min address for tiling" line.long 0x2C "RGX_CR_BIF_TILING_CFG5_1,This register defines 8 RANGEs in which BIF Tiling can be configured. Each RANGE is given a Stride and a MIN and MAX 4KB aligned address to define the region of Address Space to be tiled. The BIF_TILING_CAT_BASE_INDEX register is.." bitfld.long 0x2C 29.--31. "XSTRIDE,defines x tile stride. The value in the register is equal to log2(number of tiles in x)-1 e. g. a value of 0 gives 2 x-tiles and a value of 3 gives 16 x-tiles" "0,1,2,3,4,5,6,7" newline bitfld.long 0x2C 28. "ENABLE,enables tiling range" "0,1" newline hexmask.long 0x2C 0.--27. 1. "MAX_ADDRESS,4KB aligned max address for tiling" line.long 0x30 "RGX_CR_BIF_TILING_CFG6_0,This register defines 8 RANGEs in which BIF Tiling can be configured. Each RANGE is given a Stride and a MIN and MAX 4KB aligned address to define the region of Address Space to be tiled. The BIF_TILING_CAT_BASE_INDEX register is.." hexmask.long.byte 0x30 28.--31. 1. "Reserved_28,Reserved_28" newline hexmask.long 0x30 0.--27. 1. "MIN_ADDRESS,4KB aligned min address for tiling" line.long 0x34 "RGX_CR_BIF_TILING_CFG6_1,This register defines 8 RANGEs in which BIF Tiling can be configured. Each RANGE is given a Stride and a MIN and MAX 4KB aligned address to define the region of Address Space to be tiled. The BIF_TILING_CAT_BASE_INDEX register is.." bitfld.long 0x34 29.--31. "XSTRIDE,defines x tile stride. The value in the register is equal to log2(number of tiles in x)-1 e. g. a value of 0 gives 2 x-tiles and a value of 3 gives 16 x-tiles" "0,1,2,3,4,5,6,7" newline bitfld.long 0x34 28. "ENABLE,enables tiling range" "0,1" newline hexmask.long 0x34 0.--27. 1. "MAX_ADDRESS,4KB aligned max address for tiling" line.long 0x38 "RGX_CR_BIF_TILING_CFG7_0,This register defines 8 RANGEs in which BIF Tiling can be configured. Each RANGE is given a Stride and a MIN and MAX 4KB aligned address to define the region of Address Space to be tiled. The BIF_TILING_CAT_BASE_INDEX register is.." hexmask.long.byte 0x38 28.--31. 1. "Reserved_28,Reserved_28" newline hexmask.long 0x38 0.--27. 1. "MIN_ADDRESS,4KB aligned min address for tiling" line.long 0x3C "RGX_CR_BIF_TILING_CFG7_1,This register defines 8 RANGEs in which BIF Tiling can be configured. Each RANGE is given a Stride and a MIN and MAX 4KB aligned address to define the region of Address Space to be tiled. The BIF_TILING_CAT_BASE_INDEX register is.." bitfld.long 0x3C 29.--31. "XSTRIDE,defines x tile stride. The value in the register is equal to log2(number of tiles in x)-1 e. g. a value of 0 gives 2 x-tiles and a value of 3 gives 16 x-tiles" "0,1,2,3,4,5,6,7" newline bitfld.long 0x3C 28. "ENABLE,enables tiling range" "0,1" newline hexmask.long 0x3C 0.--27. 1. "MAX_ADDRESS,4KB aligned max address for tiling" repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) group.long ($2+0x1318)++0x3 line.long 0x0 "RGX_CR_BIF_TILING_CAT_BASE_INDEX_$1,This register defines the Catalogue Base Index applying to each tiling configuration register. An input address passing the RANGE test is also qualified against the RANGE INDEX before Tiling can proceed." hexmask.long.byte 0x0 27.--31. 1. "Reserved_27,Reserved_27" newline bitfld.long 0x0 24.--26. "RANGE3,RANGE3" "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x0 19.--23. 1. "Reserved_19,Reserved_19" newline bitfld.long 0x0 16.--18. "RANGE2,RANGE2" "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x0 11.--15. 1. "Reserved_11,Reserved_11" newline bitfld.long 0x0 8.--10. "RANGE1,RANGE1" "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x0 3.--7. 1. "Reserved_3,Reserved_3" newline bitfld.long 0x0 0.--2. "RANGE0,RANGE0" "0,1,2,3,4,5,6,7" repeat.end rgroup.long 0x1320++0x1F line.long 0x0 "RGX_CR_BIF_READS_EXT_STATUS_0,Outstanding read data external to BIF for BIF128 and MMU" hexmask.long.word 0x0 23.--31. 1. "Reserved_23,Reserved_23" newline hexmask.long.byte 0x0 16.--22. 1. "MMU,MMU" newline hexmask.long.word 0x0 0.--15. 1. "BANK1,BANK1" line.long 0x4 "RGX_CR_BIF_READS_EXT_STATUS_1,Outstanding read data external to BIF for BIF128 and MMU" hexmask.long 0x4 0.--31. 1. "Reserved_23,Reserved_23" line.long 0x8 "RGX_CR_BIF_READS_INT_STATUS_0,Outstanding 256-bit read data in return data FIFO for BIF128 and MMU" hexmask.long.word 0x8 23.--31. 1. "Reserved_23,Reserved_23" newline hexmask.long.byte 0x8 16.--22. 1. "MMU,MMU" newline hexmask.long.word 0x8 0.--15. 1. "BANK1,BANK1" line.long 0xC "RGX_CR_BIF_READS_INT_STATUS_1,Outstanding 256-bit read data in return data FIFO for BIF128 and MMU" hexmask.long 0xC 0.--31. 1. "Reserved_23,Reserved_23" line.long 0x10 "RGX_CR_BIFPM_READS_INT_STATUS_0,Outstanding 256-bit read data in return data FIFO for BIF256" hexmask.long.word 0x10 16.--31. 1. "Reserved_16,Reserved_16" newline hexmask.long.word 0x10 0.--15. 1. "BANK0,BANK0" line.long 0x14 "RGX_CR_BIFPM_READS_INT_STATUS_1,Outstanding 256-bit read data in return data FIFO for BIF256" hexmask.long 0x14 0.--31. 1. "Reserved_16,Reserved_16" line.long 0x18 "RGX_CR_BIFPM_READS_EXT_STATUS_0,Outstanding 256-bit read data external to BIF for BIF256" hexmask.long.word 0x18 16.--31. 1. "Reserved_16,Reserved_16" newline hexmask.long.word 0x18 0.--15. 1. "BANK0,BANK0" line.long 0x1C "RGX_CR_BIFPM_READS_EXT_STATUS_1,Outstanding 256-bit read data external to BIF for BIF256" hexmask.long 0x1C 0.--31. 1. "Reserved_16,Reserved_16" group.long 0x1340++0xF line.long 0x0 "RGX_CR_BIFPM_CTRL_0,Miscellaneous controls" hexmask.long 0x0 2.--31. 1. "Reserved_2,Reserved_2" newline bitfld.long 0x0 1. "ENABLE_SLC_STALLING,Enables BIF to stall returns from SLC so that requests can be made even when there is no space in the BIF return buffer (only when no chance of lockup)" "0,1" newline bitfld.long 0x0 0. "PAUSE_BIF0,Stalls BIF0 pipeline" "0,1" line.long 0x4 "RGX_CR_BIFPM_CTRL_1,Miscellaneous controls" hexmask.long 0x4 0.--31. 1. "Reserved_2,Reserved_2" line.long 0x8 "RGX_CR_BIFPM_CTRL_INVAL_0,Invalidation bits allowing BIF to clear when invalidation complete" hexmask.long 0x8 1.--31. 1. "Reserved_1,Reserved_1" newline bitfld.long 0x8 0. "TLB0,TLB0" "0,1" line.long 0xC "RGX_CR_BIFPM_CTRL_INVAL_1,Invalidation bits allowing BIF to clear when invalidation complete" hexmask.long 0xC 0.--31. 1. "Reserved_1,Reserved_1" rgroup.long 0x1350++0xF line.long 0x0 "RGX_CR_BIFPM_STATUS_MMU_0,Outstanding MMU requests from BIF0" hexmask.long.tbyte 0x0 8.--31. 1. "Reserved_8,Reserved_8" newline hexmask.long.byte 0x0 0.--7. 1. "REQUESTS,REQUESTS" line.long 0x4 "RGX_CR_BIFPM_STATUS_MMU_1,Outstanding MMU requests from BIF0" hexmask.long 0x4 0.--31. 1. "Reserved_8,Reserved_8" line.long 0x8 "RGX_CR_BIF_STATUS_MMU_0,Outstanding MMU requests from BIF1" hexmask.long.tbyte 0x8 8.--31. 1. "Reserved_8,Reserved_8" newline hexmask.long.byte 0x8 0.--7. 1. "REQUESTS,REQUESTS" line.long 0xC "RGX_CR_BIF_STATUS_MMU_1,Outstanding MMU requests from BIF1" hexmask.long 0xC 0.--31. 1. "Reserved_8,Reserved_8" group.long 0x1360++0x7 line.long 0x0 "RGX_CR_BIF_TILING_0,Sets tiling mode between 256byte x 16 rows (0) and 512byte x 8 rows (1)" hexmask.long 0x0 1.--31. 1. "Reserved_1,Reserved_1" newline bitfld.long 0x0 0. "MODE,MODE" "0,1" line.long 0x4 "RGX_CR_BIF_TILING_1,Sets tiling mode between 256byte x 16 rows (0) and 512byte x 8 rows (1)" hexmask.long 0x4 0.--31. 1. "Reserved_1,Reserved_1" repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) rgroup.long ($2+0x1370)++0x3 line.long 0x0 "RGX_CR_BIF_BLACKPEARL_PWR_$1,Power monitoring register" hexmask.long 0x0 0.--31. 1. "NUM_256BIT_TRANS,Number of 256-bit transactions" repeat.end repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) rgroup.long ($2+0x1378)++0x3 line.long 0x0 "RGX_CR_BIF_JONES_PWR_$1,Power monitoring register" hexmask.long 0x0 0.--31. 1. "NUM_256BIT_TRANS,Number of 256-bit transactions" repeat.end group.long 0x13E0++0x7 line.long 0x0 "RGX_CR_BIF_FAULT_READ_0,Specifies physical address to read from in the event of a faulting read request from BIF1" hexmask.long 0x0 4.--31. 1. "ADDRESS,ADDRESS" newline hexmask.long.byte 0x0 0.--3. 1. "Reserved_0,Reserved_0" line.long 0x4 "RGX_CR_BIF_FAULT_READ_1,Specifies physical address to read from in the event of a faulting read request from BIF1" hexmask.long.tbyte 0x4 8.--31. 1. "Reserved_40,Reserved_40" newline hexmask.long.byte 0x4 0.--7. 1. "ADDRESS,ADDRESS" repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) rgroup.long ($2+0x13E8)++0x3 line.long 0x0 "RGX_CR_BIF_PWR_$1,Power monitoring register" hexmask.long 0x0 0.--31. 1. "NUM_256BIT_TRANS,Number of 256-bit transactions" repeat.end group.long 0x13F8++0x7 line.long 0x0 "RGX_CR_BIF_MCU_RESERVED_0,Allows driver to change the amount of space in the return data FIFO reserved for the MCU" hexmask.long 0x0 5.--31. 1. "Reserved_5,Reserved_5" newline hexmask.long.byte 0x0 0.--4. 1. "SPACE,Granularity of 8 spaces minimum legal value 0x1" line.long 0x4 "RGX_CR_BIF_MCU_RESERVED_1,Allows driver to change the amount of space in the return data FIFO reserved for the MCU" hexmask.long 0x4 0.--31. 1. "Reserved_5,Reserved_5" rgroup.long 0x1430++0x27 line.long 0x0 "RGX_CR_TEXAS_BIF_FAULT_BANK0_MMU_STATUS_0,Indicates a fault has occurred on bank 0 and provides details of fault" hexmask.long.word 0x0 16.--31. 1. "Reserved_16,Reserved_16" newline hexmask.long.byte 0x0 12.--15. 1. "CAT_BASE,Catalogue base address number" newline bitfld.long 0x0 11. "Reserved_11,Reserved_11" "0,1" newline bitfld.long 0x0 8.--10. "PAGE_SIZE,Page size" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 7. "Reserved_7,Reserved_7" "0,1" newline bitfld.long 0x0 5.--6. "DATA_TYPE,MMU data type that was invalid (on valid fault)" "0,1,2,3" newline bitfld.long 0x0 4. "FAULT_RO,Indicates read-only fault('1') or valid fault('0')" "0,1" newline bitfld.long 0x0 3. "Reserved_3,Reserved_3" "0,1" newline bitfld.long 0x0 2. "FAULT_PM_META_RO,Indicates pm/meta protected region fault" "0,1" newline bitfld.long 0x0 1. "Reserved_1,Reserved_1" "0,1" newline bitfld.long 0x0 0. "FAULT,Indicates a fault has occured" "0,1" line.long 0x4 "RGX_CR_TEXAS_BIF_FAULT_BANK0_MMU_STATUS_1,Indicates a fault has occurred on bank 0 and provides details of fault" hexmask.long 0x4 0.--31. 1. "Reserved_16,Reserved_16" line.long 0x8 "RGX_CR_TEXAS_BIF_FAULT_BANK0_REQ_STATUS_0,Provides details of the request that faulted on bank 0" hexmask.long 0x8 4.--31. 1. "ADDRESS,ADDRESS" newline hexmask.long.byte 0x8 0.--3. 1. "Reserved_0,Reserved_0" line.long 0xC "RGX_CR_TEXAS_BIF_FAULT_BANK0_REQ_STATUS_1,Provides details of the request that faulted on bank 0" hexmask.long.word 0xC 19.--31. 1. "Reserved_51,Reserved_51" newline bitfld.long 0xC 18. "RNW,RNW" "0,1" newline hexmask.long.byte 0xC 12.--17. 1. "TAG_SB,TAG_SB" newline hexmask.long.byte 0xC 8.--11. 1. "TAG_ID,TAG_ID" newline hexmask.long.byte 0xC 0.--7. 1. "ADDRESS,ADDRESS" line.long 0x10 "RGX_CR_TEXAS_BIFPM_READS_INT_STATUS_0,Outstanding 256-bit read data in return data FIFO for BIF256" hexmask.long.word 0x10 16.--31. 1. "Reserved_16,Reserved_16" newline hexmask.long.word 0x10 0.--15. 1. "BANK0,BANK0" line.long 0x14 "RGX_CR_TEXAS_BIFPM_READS_INT_STATUS_1,Outstanding 256-bit read data in return data FIFO for BIF256" hexmask.long 0x14 0.--31. 1. "Reserved_16,Reserved_16" line.long 0x18 "RGX_CR_TEXAS_BIFPM_READS_EXT_STATUS_0,Outstanding 256-bit read data external to BIF for BIF256" hexmask.long.word 0x18 16.--31. 1. "Reserved_16,Reserved_16" newline hexmask.long.word 0x18 0.--15. 1. "BANK0,BANK0" line.long 0x1C "RGX_CR_TEXAS_BIFPM_READS_EXT_STATUS_1,Outstanding 256-bit read data external to BIF for BIF256" hexmask.long 0x1C 0.--31. 1. "Reserved_16,Reserved_16" line.long 0x20 "RGX_CR_TEXAS_BIFPM_STATUS_MMU_0,Outstanding MMU requests from BIF0" hexmask.long.tbyte 0x20 8.--31. 1. "Reserved_8,Reserved_8" newline hexmask.long.byte 0x20 0.--7. 1. "REQUESTS,REQUESTS" line.long 0x24 "RGX_CR_TEXAS_BIFPM_STATUS_MMU_1,Outstanding MMU requests from BIF0" hexmask.long 0x24 0.--31. 1. "Reserved_8,Reserved_8" repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) group.long ($2+0x1460)++0x3 line.long 0x0 "RGX_CR_BIF_OSID0_$1,Defines OSID for each CAT_BASE" hexmask.long.byte 0x0 27.--31. 1. "Reserved_27,Reserved_27" newline bitfld.long 0x0 24.--26. "CBASE3,OSID for CAT BASE 3" "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x0 19.--23. 1. "Reserved_19,Reserved_19" newline bitfld.long 0x0 16.--18. "CBASE2,OSID for CAT BASE 2" "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x0 11.--15. 1. "Reserved_11,Reserved_11" newline bitfld.long 0x0 8.--10. "CBASE1,OSID for CAT BASE 1" "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x0 3.--7. 1. "Reserved_3,Reserved_3" newline bitfld.long 0x0 0.--2. "CBASE0,OSID for CAT BASE 0" "0,1,2,3,4,5,6,7" repeat.end group.long 0x1468++0x7 line.long 0x0 "RGX_CR_BIF_OSID1_0,Defines OSID for each data master" hexmask.long.tbyte 0x0 11.--31. 1. "Reserved_11,Reserved_11" newline bitfld.long 0x0 8.--10. "PM_CTX1,OSID for VCE1 TE1 and ALIST1" "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x0 3.--7. 1. "Reserved_3,Reserved_3" newline bitfld.long 0x0 0.--2. "PM_CTX0,OSID for VCE0 TE0 and ALIST0" "0,1,2,3,4,5,6,7" line.long 0x4 "RGX_CR_BIF_OSID1_1,Defines OSID for each data master" hexmask.long 0x4 0.--31. 1. "Reserved_11,Reserved_11" group.long 0x1500++0x7 line.long 0x0 "RGX_CR_PBE_0,The PBE(Pixel back end) module scales and packs the pixel data before writing to memory. this register contains global control signals." hexmask.long.tbyte 0x0 9.--31. 1. "Reserved_9,Reserved_9" newline bitfld.long 0x0 8. "AA_EDGEOPT_OFF,Switches off the PBE-USE read optimisation during Anti aliasing mode. (This is typically for debug purposes only)" "0,1" newline hexmask.long.byte 0x0 0.--7. 1. "ALPHATHRESHOLD,Alpha threshold used when encoding 1555 format. If the internal 8bit Alpha value exceeds this value then a 1 is written to the top bit of the output otherwise a 0 is written" line.long 0x4 "RGX_CR_PBE_1,The PBE(Pixel back end) module scales and packs the pixel data before writing to memory. this register contains global control signals." hexmask.long 0x4 0.--31. 1. "Reserved_9,Reserved_9" rgroup.long 0x1508++0x7 line.long 0x0 "RGX_CR_PBE_EMIT_STATUS_0,This register indicates if the PixelBE would stall the USE if there were another emit. '0' indicates that the PixelBE would stall the USC. '1' indicates that the PixelBE would not stall the USE." hexmask.long.word 0x0 16.--31. 1. "Reserved_16,Reserved_16" newline bitfld.long 0x0 15. "USC15,Pipe 15 status" "0,1" newline bitfld.long 0x0 14. "USC14,Pipe 14 status" "0,1" newline bitfld.long 0x0 13. "USC13,Pipe 13 status" "0,1" newline bitfld.long 0x0 12. "USC12,Pipe 12 status" "0,1" newline bitfld.long 0x0 11. "USC11,Pipe 11 status" "0,1" newline bitfld.long 0x0 10. "USC10,Pipe 10 status" "0,1" newline bitfld.long 0x0 9. "USC9,Pipe 9 status" "0,1" newline bitfld.long 0x0 8. "USC8,Pipe 8 status" "0,1" newline bitfld.long 0x0 7. "USC7,Pipe 7 status" "0,1" newline bitfld.long 0x0 6. "USC6,Pipe 6 status" "0,1" newline bitfld.long 0x0 5. "USC5,Pipe 5 status" "0,1" newline bitfld.long 0x0 4. "USC4,Pipe 4 status" "0,1" newline bitfld.long 0x0 3. "USC3,Pipe 3 status" "0,1" newline bitfld.long 0x0 2. "USC2,Pipe 2 status" "0,1" newline bitfld.long 0x0 1. "USC1,Pipe 1 status" "0,1" newline bitfld.long 0x0 0. "USC0,Pipe 0 status" "0,1" line.long 0x4 "RGX_CR_PBE_EMIT_STATUS_1,This register indicates if the PixelBE would stall the USE if there were another emit. '0' indicates that the PixelBE would stall the USC. '1' indicates that the PixelBE would not stall the USE." hexmask.long 0x4 0.--31. 1. "Reserved_16,Reserved_16" group.long 0x1510++0x3F line.long 0x0 "RGX_CR_PBE_WORD0_MRT0_0,Pixel Back end State Word 0." bitfld.long 0x0 29.--31. "SWIZ_CHAN3,Swizzle for destination channel 3" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 26.--28. "SWIZ_CHAN2,Swizzle for destination channel 2" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 23.--25. "SWIZ_CHAN1,Swizzle for destination channel 1" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 20.--22. "SWIZ_CHAN0,Swizzle for destination channel 0" "0,1,2,3,4,5,6,7" newline hexmask.long.word 0x0 6.--19. 1. "MINCLIP_X,Min X Clip" newline bitfld.long 0x0 5. "TWOCOMP_GAMMA,Sets the gamma mode for 2 component targets" "0,1" newline bitfld.long 0x0 4. "GAMMA,Gamma enabled" "0,1" newline bitfld.long 0x0 3. "COMPRESSION,Frame buffer Compression enabled" "0,1" newline bitfld.long 0x0 2. "COMPRESS_SIZE,Block size for the compressor used with COMPRESS_SIZE_EXT register bit to define 8x8; 16x4 or 32x2 size COMPRESS_SIZE_EXT COMPRESS_SIZE SIZE 0 0 8x8 0 1 16x4 1 0 32x2 1 1 reserved" "0,1" newline bitfld.long 0x0 1. "COMP_INDIRECT_TABLE,If set indicates to the compressor that an indirect addressing is used otherwise direct addressing" "0,1" newline bitfld.long 0x0 0. "Y_FLIP,Y_FLIP" "0,1" line.long 0x4 "RGX_CR_PBE_WORD0_MRT0_1,Pixel Back end State Word 0." bitfld.long 0x4 30.--31. "X_RSRVD,Not used" "0,1,2,3" newline bitfld.long 0x4 29. "COMPRESS_SIZE_EXT,Extra bit to support 32x2 compression size used with COMPRESS_SIZE register bit to define 8x8; 16x4 or 32x2 size COMPRESS_SIZE_EXT COMPRESS_SIZE SIZE 0 0 8x8 0 1 16x4 1 0 32x2 1 1 reserved" "0,1" newline bitfld.long 0x4 28. "COMP_IADDR_MODE,FBC indirect addressing mode" "0,1" newline bitfld.long 0x4 27. "COMP_COR_ENABLE,Enable FBC correlation" "0,1" newline bitfld.long 0x4 26. "DITHER,Enable dither" "0,1" newline bitfld.long 0x4 25. "TILERELATIVE,Add tile offset" "0,1" newline bitfld.long 0x4 24. "DOWNSCALE,Perform box filter downscale" "0,1" newline hexmask.long.byte 0x4 20.--23. 1. "SIZE_Z,Z Size in pixels [log 2]" newline bitfld.long 0x4 18.--19. "ROTATION,Rotation angle" "0,1,2,3" newline hexmask.long.word 0x4 2.--17. 1. "LINESTRIDE,Linestride in 2 pixel units. 0 == 2. Supports 32KDWORD stride memory write" newline bitfld.long 0x4 0.--1. "MEMLAYOUT,Memory layout" "0,1,2,3" line.long 0x8 "RGX_CR_PBE_WORD0_MRT1_0,Pixel Back end State Word 0." bitfld.long 0x8 29.--31. "SWIZ_CHAN3,Swizzle for destination channel 3" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 26.--28. "SWIZ_CHAN2,Swizzle for destination channel 2" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 23.--25. "SWIZ_CHAN1,Swizzle for destination channel 1" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 20.--22. "SWIZ_CHAN0,Swizzle for destination channel 0" "0,1,2,3,4,5,6,7" newline hexmask.long.word 0x8 6.--19. 1. "MINCLIP_X,Min X Clip" newline bitfld.long 0x8 5. "TWOCOMP_GAMMA,Sets the gamma mode for 2 component targets" "0,1" newline bitfld.long 0x8 4. "GAMMA,Gamma enabled" "0,1" newline bitfld.long 0x8 3. "COMPRESSION,Frame buffer Compression enabled" "0,1" newline bitfld.long 0x8 2. "COMPRESS_SIZE,Block size for the compressor used with COMPRESS_SIZE_EXT register bit to define 8x8; 16x4 or 32x2 size COMPRESS_SIZE_EXT COMPRESS_SIZE SIZE 0 0 8x8 0 1 16x4 1 0 32x2 1 1 reserved" "0,1" newline bitfld.long 0x8 1. "COMP_INDIRECT_TABLE,If set indicates to the compressor that an indirect addressing is used otherwise direct addressing" "0,1" newline bitfld.long 0x8 0. "Y_FLIP,Y_FLIP" "0,1" line.long 0xC "RGX_CR_PBE_WORD0_MRT1_1,Pixel Back end State Word 0." bitfld.long 0xC 30.--31. "X_RSRVD,Not used" "0,1,2,3" newline bitfld.long 0xC 29. "COMPRESS_SIZE_EXT,Extra bit to support 32x2 compression size used with COMPRESS_SIZE register bit to define 8x8; 16x4 or 32x2 size COMPRESS_SIZE_EXT COMPRESS_SIZE SIZE 0 0 8x8 0 1 16x4 1 0 32x2 1 1 reserved" "0,1" newline bitfld.long 0xC 28. "COMP_IADDR_MODE,FBC indirect addressing mode" "0,1" newline bitfld.long 0xC 27. "COMP_COR_ENABLE,Enable FBC correlation" "0,1" newline bitfld.long 0xC 26. "DITHER,Enable dither" "0,1" newline bitfld.long 0xC 25. "TILERELATIVE,Add tile offset" "0,1" newline bitfld.long 0xC 24. "DOWNSCALE,Perform box filter downscale" "0,1" newline hexmask.long.byte 0xC 20.--23. 1. "SIZE_Z,Z Size in pixels [log 2]" newline bitfld.long 0xC 18.--19. "ROTATION,Rotation angle" "0,1,2,3" newline hexmask.long.word 0xC 2.--17. 1. "LINESTRIDE,Linestride in 2 pixel units. 0 == 2. Supports 32KDWORD stride memory write" newline bitfld.long 0xC 0.--1. "MEMLAYOUT,Memory layout" "0,1,2,3" line.long 0x10 "RGX_CR_PBE_WORD0_MRT2_0,Pixel Back end State Word 0." bitfld.long 0x10 29.--31. "SWIZ_CHAN3,Swizzle for destination channel 3" "0,1,2,3,4,5,6,7" newline bitfld.long 0x10 26.--28. "SWIZ_CHAN2,Swizzle for destination channel 2" "0,1,2,3,4,5,6,7" newline bitfld.long 0x10 23.--25. "SWIZ_CHAN1,Swizzle for destination channel 1" "0,1,2,3,4,5,6,7" newline bitfld.long 0x10 20.--22. "SWIZ_CHAN0,Swizzle for destination channel 0" "0,1,2,3,4,5,6,7" newline hexmask.long.word 0x10 6.--19. 1. "MINCLIP_X,Min X Clip" newline bitfld.long 0x10 5. "TWOCOMP_GAMMA,Sets the gamma mode for 2 component targets" "0,1" newline bitfld.long 0x10 4. "GAMMA,Gamma enabled" "0,1" newline bitfld.long 0x10 3. "COMPRESSION,Frame buffer Compression enabled" "0,1" newline bitfld.long 0x10 2. "COMPRESS_SIZE,Block size for the compressor used with COMPRESS_SIZE_EXT register bit to define 8x8; 16x4 or 32x2 size COMPRESS_SIZE_EXT COMPRESS_SIZE SIZE 0 0 8x8 0 1 16x4 1 0 32x2 1 1 reserved" "0,1" newline bitfld.long 0x10 1. "COMP_INDIRECT_TABLE,If set indicates to the compressor that an indirect addressing is used otherwise direct addressing" "0,1" newline bitfld.long 0x10 0. "Y_FLIP,Y_FLIP" "0,1" line.long 0x14 "RGX_CR_PBE_WORD0_MRT2_1,Pixel Back end State Word 0." bitfld.long 0x14 30.--31. "X_RSRVD,Not used" "0,1,2,3" newline bitfld.long 0x14 29. "COMPRESS_SIZE_EXT,Extra bit to support 32x2 compression size used with COMPRESS_SIZE register bit to define 8x8; 16x4 or 32x2 size COMPRESS_SIZE_EXT COMPRESS_SIZE SIZE 0 0 8x8 0 1 16x4 1 0 32x2 1 1 reserved" "0,1" newline bitfld.long 0x14 28. "COMP_IADDR_MODE,FBC indirect addressing mode" "0,1" newline bitfld.long 0x14 27. "COMP_COR_ENABLE,Enable FBC correlation" "0,1" newline bitfld.long 0x14 26. "DITHER,Enable dither" "0,1" newline bitfld.long 0x14 25. "TILERELATIVE,Add tile offset" "0,1" newline bitfld.long 0x14 24. "DOWNSCALE,Perform box filter downscale" "0,1" newline hexmask.long.byte 0x14 20.--23. 1. "SIZE_Z,Z Size in pixels [log 2]" newline bitfld.long 0x14 18.--19. "ROTATION,Rotation angle" "0,1,2,3" newline hexmask.long.word 0x14 2.--17. 1. "LINESTRIDE,Linestride in 2 pixel units. 0 == 2. Supports 32KDWORD stride memory write" newline bitfld.long 0x14 0.--1. "MEMLAYOUT,Memory layout" "0,1,2,3" line.long 0x18 "RGX_CR_PBE_WORD0_MRT3_0,Pixel Back end State Word 0." bitfld.long 0x18 29.--31. "SWIZ_CHAN3,Swizzle for destination channel 3" "0,1,2,3,4,5,6,7" newline bitfld.long 0x18 26.--28. "SWIZ_CHAN2,Swizzle for destination channel 2" "0,1,2,3,4,5,6,7" newline bitfld.long 0x18 23.--25. "SWIZ_CHAN1,Swizzle for destination channel 1" "0,1,2,3,4,5,6,7" newline bitfld.long 0x18 20.--22. "SWIZ_CHAN0,Swizzle for destination channel 0" "0,1,2,3,4,5,6,7" newline hexmask.long.word 0x18 6.--19. 1. "MINCLIP_X,Min X Clip" newline bitfld.long 0x18 5. "TWOCOMP_GAMMA,Sets the gamma mode for 2 component targets" "0,1" newline bitfld.long 0x18 4. "GAMMA,Gamma enabled" "0,1" newline bitfld.long 0x18 3. "COMPRESSION,Frame buffer Compression enabled" "0,1" newline bitfld.long 0x18 2. "COMPRESS_SIZE,Block size for the compressor used with COMPRESS_SIZE_EXT register bit to define 8x8; 16x4 or 32x2 size COMPRESS_SIZE_EXT COMPRESS_SIZE SIZE 0 0 8x8 0 1 16x4 1 0 32x2 1 1 reserved" "0,1" newline bitfld.long 0x18 1. "COMP_INDIRECT_TABLE,If set indicates to the compressor that an indirect addressing is used otherwise direct addressing" "0,1" newline bitfld.long 0x18 0. "Y_FLIP,Y_FLIP" "0,1" line.long 0x1C "RGX_CR_PBE_WORD0_MRT3_1,Pixel Back end State Word 0." bitfld.long 0x1C 30.--31. "X_RSRVD,Not used" "0,1,2,3" newline bitfld.long 0x1C 29. "COMPRESS_SIZE_EXT,Extra bit to support 32x2 compression size used with COMPRESS_SIZE register bit to define 8x8; 16x4 or 32x2 size COMPRESS_SIZE_EXT COMPRESS_SIZE SIZE 0 0 8x8 0 1 16x4 1 0 32x2 1 1 reserved" "0,1" newline bitfld.long 0x1C 28. "COMP_IADDR_MODE,FBC indirect addressing mode" "0,1" newline bitfld.long 0x1C 27. "COMP_COR_ENABLE,Enable FBC correlation" "0,1" newline bitfld.long 0x1C 26. "DITHER,Enable dither" "0,1" newline bitfld.long 0x1C 25. "TILERELATIVE,Add tile offset" "0,1" newline bitfld.long 0x1C 24. "DOWNSCALE,Perform box filter downscale" "0,1" newline hexmask.long.byte 0x1C 20.--23. 1. "SIZE_Z,Z Size in pixels [log 2]" newline bitfld.long 0x1C 18.--19. "ROTATION,Rotation angle" "0,1,2,3" newline hexmask.long.word 0x1C 2.--17. 1. "LINESTRIDE,Linestride in 2 pixel units. 0 == 2. Supports 32KDWORD stride memory write" newline bitfld.long 0x1C 0.--1. "MEMLAYOUT,Memory layout" "0,1,2,3" line.long 0x20 "RGX_CR_PBE_WORD0_MRT4_0,Pixel Back end State Word 0." bitfld.long 0x20 29.--31. "SWIZ_CHAN3,Swizzle for destination channel 3" "0,1,2,3,4,5,6,7" newline bitfld.long 0x20 26.--28. "SWIZ_CHAN2,Swizzle for destination channel 2" "0,1,2,3,4,5,6,7" newline bitfld.long 0x20 23.--25. "SWIZ_CHAN1,Swizzle for destination channel 1" "0,1,2,3,4,5,6,7" newline bitfld.long 0x20 20.--22. "SWIZ_CHAN0,Swizzle for destination channel 0" "0,1,2,3,4,5,6,7" newline hexmask.long.word 0x20 6.--19. 1. "MINCLIP_X,Min X Clip" newline bitfld.long 0x20 5. "TWOCOMP_GAMMA,Sets the gamma mode for 2 component targets" "0,1" newline bitfld.long 0x20 4. "GAMMA,Gamma enabled" "0,1" newline bitfld.long 0x20 3. "COMPRESSION,Frame buffer Compression enabled" "0,1" newline bitfld.long 0x20 2. "COMPRESS_SIZE,Block size for the compressor used with COMPRESS_SIZE_EXT register bit to define 8x8; 16x4 or 32x2 size COMPRESS_SIZE_EXT COMPRESS_SIZE SIZE 0 0 8x8 0 1 16x4 1 0 32x2 1 1 reserved" "0,1" newline bitfld.long 0x20 1. "COMP_INDIRECT_TABLE,If set indicates to the compressor that an indirect addressing is used otherwise direct addressing" "0,1" newline bitfld.long 0x20 0. "Y_FLIP,Y_FLIP" "0,1" line.long 0x24 "RGX_CR_PBE_WORD0_MRT4_1,Pixel Back end State Word 0." bitfld.long 0x24 30.--31. "X_RSRVD,Not used" "0,1,2,3" newline bitfld.long 0x24 29. "COMPRESS_SIZE_EXT,Extra bit to support 32x2 compression size used with COMPRESS_SIZE register bit to define 8x8; 16x4 or 32x2 size COMPRESS_SIZE_EXT COMPRESS_SIZE SIZE 0 0 8x8 0 1 16x4 1 0 32x2 1 1 reserved" "0,1" newline bitfld.long 0x24 28. "COMP_IADDR_MODE,FBC indirect addressing mode" "0,1" newline bitfld.long 0x24 27. "COMP_COR_ENABLE,Enable FBC correlation" "0,1" newline bitfld.long 0x24 26. "DITHER,Enable dither" "0,1" newline bitfld.long 0x24 25. "TILERELATIVE,Add tile offset" "0,1" newline bitfld.long 0x24 24. "DOWNSCALE,Perform box filter downscale" "0,1" newline hexmask.long.byte 0x24 20.--23. 1. "SIZE_Z,Z Size in pixels [log 2]" newline bitfld.long 0x24 18.--19. "ROTATION,Rotation angle" "0,1,2,3" newline hexmask.long.word 0x24 2.--17. 1. "LINESTRIDE,Linestride in 2 pixel units. 0 == 2. Supports 32KDWORD stride memory write" newline bitfld.long 0x24 0.--1. "MEMLAYOUT,Memory layout" "0,1,2,3" line.long 0x28 "RGX_CR_PBE_WORD0_MRT5_0,Pixel Back end State Word 0." bitfld.long 0x28 29.--31. "SWIZ_CHAN3,Swizzle for destination channel 3" "0,1,2,3,4,5,6,7" newline bitfld.long 0x28 26.--28. "SWIZ_CHAN2,Swizzle for destination channel 2" "0,1,2,3,4,5,6,7" newline bitfld.long 0x28 23.--25. "SWIZ_CHAN1,Swizzle for destination channel 1" "0,1,2,3,4,5,6,7" newline bitfld.long 0x28 20.--22. "SWIZ_CHAN0,Swizzle for destination channel 0" "0,1,2,3,4,5,6,7" newline hexmask.long.word 0x28 6.--19. 1. "MINCLIP_X,Min X Clip" newline bitfld.long 0x28 5. "TWOCOMP_GAMMA,Sets the gamma mode for 2 component targets" "0,1" newline bitfld.long 0x28 4. "GAMMA,Gamma enabled" "0,1" newline bitfld.long 0x28 3. "COMPRESSION,Frame buffer Compression enabled" "0,1" newline bitfld.long 0x28 2. "COMPRESS_SIZE,Block size for the compressor used with COMPRESS_SIZE_EXT register bit to define 8x8; 16x4 or 32x2 size COMPRESS_SIZE_EXT COMPRESS_SIZE SIZE 0 0 8x8 0 1 16x4 1 0 32x2 1 1 reserved" "0,1" newline bitfld.long 0x28 1. "COMP_INDIRECT_TABLE,If set indicates to the compressor that an indirect addressing is used otherwise direct addressing" "0,1" newline bitfld.long 0x28 0. "Y_FLIP,Y_FLIP" "0,1" line.long 0x2C "RGX_CR_PBE_WORD0_MRT5_1,Pixel Back end State Word 0." bitfld.long 0x2C 30.--31. "X_RSRVD,Not used" "0,1,2,3" newline bitfld.long 0x2C 29. "COMPRESS_SIZE_EXT,Extra bit to support 32x2 compression size used with COMPRESS_SIZE register bit to define 8x8; 16x4 or 32x2 size COMPRESS_SIZE_EXT COMPRESS_SIZE SIZE 0 0 8x8 0 1 16x4 1 0 32x2 1 1 reserved" "0,1" newline bitfld.long 0x2C 28. "COMP_IADDR_MODE,FBC indirect addressing mode" "0,1" newline bitfld.long 0x2C 27. "COMP_COR_ENABLE,Enable FBC correlation" "0,1" newline bitfld.long 0x2C 26. "DITHER,Enable dither" "0,1" newline bitfld.long 0x2C 25. "TILERELATIVE,Add tile offset" "0,1" newline bitfld.long 0x2C 24. "DOWNSCALE,Perform box filter downscale" "0,1" newline hexmask.long.byte 0x2C 20.--23. 1. "SIZE_Z,Z Size in pixels [log 2]" newline bitfld.long 0x2C 18.--19. "ROTATION,Rotation angle" "0,1,2,3" newline hexmask.long.word 0x2C 2.--17. 1. "LINESTRIDE,Linestride in 2 pixel units. 0 == 2. Supports 32KDWORD stride memory write" newline bitfld.long 0x2C 0.--1. "MEMLAYOUT,Memory layout" "0,1,2,3" line.long 0x30 "RGX_CR_PBE_WORD0_MRT6_0,Pixel Back end State Word 0." bitfld.long 0x30 29.--31. "SWIZ_CHAN3,Swizzle for destination channel 3" "0,1,2,3,4,5,6,7" newline bitfld.long 0x30 26.--28. "SWIZ_CHAN2,Swizzle for destination channel 2" "0,1,2,3,4,5,6,7" newline bitfld.long 0x30 23.--25. "SWIZ_CHAN1,Swizzle for destination channel 1" "0,1,2,3,4,5,6,7" newline bitfld.long 0x30 20.--22. "SWIZ_CHAN0,Swizzle for destination channel 0" "0,1,2,3,4,5,6,7" newline hexmask.long.word 0x30 6.--19. 1. "MINCLIP_X,Min X Clip" newline bitfld.long 0x30 5. "TWOCOMP_GAMMA,Sets the gamma mode for 2 component targets" "0,1" newline bitfld.long 0x30 4. "GAMMA,Gamma enabled" "0,1" newline bitfld.long 0x30 3. "COMPRESSION,Frame buffer Compression enabled" "0,1" newline bitfld.long 0x30 2. "COMPRESS_SIZE,Block size for the compressor used with COMPRESS_SIZE_EXT register bit to define 8x8; 16x4 or 32x2 size COMPRESS_SIZE_EXT COMPRESS_SIZE SIZE 0 0 8x8 0 1 16x4 1 0 32x2 1 1 reserved" "0,1" newline bitfld.long 0x30 1. "COMP_INDIRECT_TABLE,If set indicates to the compressor that an indirect addressing is used otherwise direct addressing" "0,1" newline bitfld.long 0x30 0. "Y_FLIP,Y_FLIP" "0,1" line.long 0x34 "RGX_CR_PBE_WORD0_MRT6_1,Pixel Back end State Word 0." bitfld.long 0x34 30.--31. "X_RSRVD,Not used" "0,1,2,3" newline bitfld.long 0x34 29. "COMPRESS_SIZE_EXT,Extra bit to support 32x2 compression size used with COMPRESS_SIZE register bit to define 8x8; 16x4 or 32x2 size COMPRESS_SIZE_EXT COMPRESS_SIZE SIZE 0 0 8x8 0 1 16x4 1 0 32x2 1 1 reserved" "0,1" newline bitfld.long 0x34 28. "COMP_IADDR_MODE,FBC indirect addressing mode" "0,1" newline bitfld.long 0x34 27. "COMP_COR_ENABLE,Enable FBC correlation" "0,1" newline bitfld.long 0x34 26. "DITHER,Enable dither" "0,1" newline bitfld.long 0x34 25. "TILERELATIVE,Add tile offset" "0,1" newline bitfld.long 0x34 24. "DOWNSCALE,Perform box filter downscale" "0,1" newline hexmask.long.byte 0x34 20.--23. 1. "SIZE_Z,Z Size in pixels [log 2]" newline bitfld.long 0x34 18.--19. "ROTATION,Rotation angle" "0,1,2,3" newline hexmask.long.word 0x34 2.--17. 1. "LINESTRIDE,Linestride in 2 pixel units. 0 == 2. Supports 32KDWORD stride memory write" newline bitfld.long 0x34 0.--1. "MEMLAYOUT,Memory layout" "0,1,2,3" line.long 0x38 "RGX_CR_PBE_WORD0_MRT7_0,Pixel Back end State Word 0." bitfld.long 0x38 29.--31. "SWIZ_CHAN3,Swizzle for destination channel 3" "0,1,2,3,4,5,6,7" newline bitfld.long 0x38 26.--28. "SWIZ_CHAN2,Swizzle for destination channel 2" "0,1,2,3,4,5,6,7" newline bitfld.long 0x38 23.--25. "SWIZ_CHAN1,Swizzle for destination channel 1" "0,1,2,3,4,5,6,7" newline bitfld.long 0x38 20.--22. "SWIZ_CHAN0,Swizzle for destination channel 0" "0,1,2,3,4,5,6,7" newline hexmask.long.word 0x38 6.--19. 1. "MINCLIP_X,Min X Clip" newline bitfld.long 0x38 5. "TWOCOMP_GAMMA,Sets the gamma mode for 2 component targets" "0,1" newline bitfld.long 0x38 4. "GAMMA,Gamma enabled" "0,1" newline bitfld.long 0x38 3. "COMPRESSION,Frame buffer Compression enabled" "0,1" newline bitfld.long 0x38 2. "COMPRESS_SIZE,Block size for the compressor used with COMPRESS_SIZE_EXT register bit to define 8x8; 16x4 or 32x2 size COMPRESS_SIZE_EXT COMPRESS_SIZE SIZE 0 0 8x8 0 1 16x4 1 0 32x2 1 1 reserved" "0,1" newline bitfld.long 0x38 1. "COMP_INDIRECT_TABLE,If set indicates to the compressor that an indirect addressing is used otherwise direct addressing" "0,1" newline bitfld.long 0x38 0. "Y_FLIP,Y_FLIP" "0,1" line.long 0x3C "RGX_CR_PBE_WORD0_MRT7_1,Pixel Back end State Word 0." bitfld.long 0x3C 30.--31. "X_RSRVD,Not used" "0,1,2,3" newline bitfld.long 0x3C 29. "COMPRESS_SIZE_EXT,Extra bit to support 32x2 compression size used with COMPRESS_SIZE register bit to define 8x8; 16x4 or 32x2 size COMPRESS_SIZE_EXT COMPRESS_SIZE SIZE 0 0 8x8 0 1 16x4 1 0 32x2 1 1 reserved" "0,1" newline bitfld.long 0x3C 28. "COMP_IADDR_MODE,FBC indirect addressing mode" "0,1" newline bitfld.long 0x3C 27. "COMP_COR_ENABLE,Enable FBC correlation" "0,1" newline bitfld.long 0x3C 26. "DITHER,Enable dither" "0,1" newline bitfld.long 0x3C 25. "TILERELATIVE,Add tile offset" "0,1" newline bitfld.long 0x3C 24. "DOWNSCALE,Perform box filter downscale" "0,1" newline hexmask.long.byte 0x3C 20.--23. 1. "SIZE_Z,Z Size in pixels [log 2]" newline bitfld.long 0x3C 18.--19. "ROTATION,Rotation angle" "0,1,2,3" newline hexmask.long.word 0x3C 2.--17. 1. "LINESTRIDE,Linestride in 2 pixel units. 0 == 2. Supports 32KDWORD stride memory write" newline bitfld.long 0x3C 0.--1. "MEMLAYOUT,Memory layout" "0,1,2,3" repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) group.long ($2+0x1550)++0x3 line.long 0x0 "RGX_CR_PBE_WORD1_MRT0_$1,Pixel Back end State Word 1." hexmask.long.byte 0x0 28.--31. 1. "SIZE_Y,Y Size in pixels [log 2]" newline hexmask.long.word 0x0 14.--27. 1. "ZSLICE,Slice number for render to 3D twiddle target" newline hexmask.long.word 0x0 0.--13. 1. "MAXCLIP_Y,Max Y clip" repeat.end repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) group.long ($2+0x1558)++0x3 line.long 0x0 "RGX_CR_PBE_WORD1_MRT1_$1,Pixel Back end State Word 1." hexmask.long.byte 0x0 28.--31. 1. "SIZE_Y,Y Size in pixels [log 2]" newline hexmask.long.word 0x0 14.--27. 1. "ZSLICE,Slice number for render to 3D twiddle target" newline hexmask.long.word 0x0 0.--13. 1. "MAXCLIP_Y,Max Y clip" repeat.end repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) group.long ($2+0x1560)++0x3 line.long 0x0 "RGX_CR_PBE_WORD1_MRT2_$1,Pixel Back end State Word 1." hexmask.long.byte 0x0 28.--31. 1. "SIZE_Y,Y Size in pixels [log 2]" newline hexmask.long.word 0x0 14.--27. 1. "ZSLICE,Slice number for render to 3D twiddle target" newline hexmask.long.word 0x0 0.--13. 1. "MAXCLIP_Y,Max Y clip" repeat.end repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) group.long ($2+0x1568)++0x3 line.long 0x0 "RGX_CR_PBE_WORD1_MRT3_$1,Pixel Back end State Word 1." hexmask.long.byte 0x0 28.--31. 1. "SIZE_Y,Y Size in pixels [log 2]" newline hexmask.long.word 0x0 14.--27. 1. "ZSLICE,Slice number for render to 3D twiddle target" newline hexmask.long.word 0x0 0.--13. 1. "MAXCLIP_Y,Max Y clip" repeat.end repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) group.long ($2+0x1570)++0x3 line.long 0x0 "RGX_CR_PBE_WORD1_MRT4_$1,Pixel Back end State Word 1." hexmask.long.byte 0x0 28.--31. 1. "SIZE_Y,Y Size in pixels [log 2]" newline hexmask.long.word 0x0 14.--27. 1. "ZSLICE,Slice number for render to 3D twiddle target" newline hexmask.long.word 0x0 0.--13. 1. "MAXCLIP_Y,Max Y clip" repeat.end repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) group.long ($2+0x1578)++0x3 line.long 0x0 "RGX_CR_PBE_WORD1_MRT5_$1,Pixel Back end State Word 1." hexmask.long.byte 0x0 28.--31. 1. "SIZE_Y,Y Size in pixels [log 2]" newline hexmask.long.word 0x0 14.--27. 1. "ZSLICE,Slice number for render to 3D twiddle target" newline hexmask.long.word 0x0 0.--13. 1. "MAXCLIP_Y,Max Y clip" repeat.end repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) group.long ($2+0x1580)++0x3 line.long 0x0 "RGX_CR_PBE_WORD1_MRT6_$1,Pixel Back end State Word 1." hexmask.long.byte 0x0 28.--31. 1. "SIZE_Y,Y Size in pixels [log 2]" newline hexmask.long.word 0x0 14.--27. 1. "ZSLICE,Slice number for render to 3D twiddle target" newline hexmask.long.word 0x0 0.--13. 1. "MAXCLIP_Y,Max Y clip" repeat.end repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) group.long ($2+0x1588)++0x3 line.long 0x0 "RGX_CR_PBE_WORD1_MRT7_$1,Pixel Back end State Word 1." hexmask.long.byte 0x0 28.--31. 1. "SIZE_Y,Y Size in pixels [log 2]" newline hexmask.long.word 0x0 14.--27. 1. "ZSLICE,Slice number for render to 3D twiddle target" newline hexmask.long.word 0x0 0.--13. 1. "MAXCLIP_Y,Max Y clip" repeat.end repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) rgroup.long ($2+0x1590)++0x3 line.long 0x0 "RGX_CR_PBE_PWR_$1,Power monitoring register" hexmask.long 0x0 0.--31. 1. "NUM_PIXELS_PROCESSED,Number of on-edge/off-edge pixels per tile." repeat.end group.long 0x15A0++0x3F line.long 0x0 "RGX_CR_PBE_WORD2_MRT0_0,Pixel Back end State Word 2." hexmask.long 0x0 0.--31. 1. "SW_BYTEMASK,SW driven mask" line.long 0x4 "RGX_CR_PBE_WORD2_MRT0_1,Pixel Back end State Word 2." hexmask.long.tbyte 0x4 15.--31. 1. "Reserved_47,Reserved_47" newline bitfld.long 0x4 14. "PAIR_TILES,If set then PBE will pair 16x16 tiles" "0,1" newline hexmask.long.word 0x4 0.--13. 1. "SURFACE_Y_SIZE,Y Size in pixels (only used for strided memory layout with FBC)" line.long 0x8 "RGX_CR_PBE_WORD2_MRT1_0,Pixel Back end State Word 2." hexmask.long 0x8 0.--31. 1. "SW_BYTEMASK,SW driven mask" line.long 0xC "RGX_CR_PBE_WORD2_MRT1_1,Pixel Back end State Word 2." hexmask.long.tbyte 0xC 15.--31. 1. "Reserved_47,Reserved_47" newline bitfld.long 0xC 14. "PAIR_TILES,If set then PBE will pair 16x16 tiles" "0,1" newline hexmask.long.word 0xC 0.--13. 1. "SURFACE_Y_SIZE,Y Size in pixels (only used for strided memory layout with FBC)" line.long 0x10 "RGX_CR_PBE_WORD2_MRT2_0,Pixel Back end State Word 2." hexmask.long 0x10 0.--31. 1. "SW_BYTEMASK,SW driven mask" line.long 0x14 "RGX_CR_PBE_WORD2_MRT2_1,Pixel Back end State Word 2." hexmask.long.tbyte 0x14 15.--31. 1. "Reserved_47,Reserved_47" newline bitfld.long 0x14 14. "PAIR_TILES,If set then PBE will pair 16x16 tiles" "0,1" newline hexmask.long.word 0x14 0.--13. 1. "SURFACE_Y_SIZE,Y Size in pixels (only used for strided memory layout with FBC)" line.long 0x18 "RGX_CR_PBE_WORD2_MRT3_0,Pixel Back end State Word 2." hexmask.long 0x18 0.--31. 1. "SW_BYTEMASK,SW driven mask" line.long 0x1C "RGX_CR_PBE_WORD2_MRT3_1,Pixel Back end State Word 2." hexmask.long.tbyte 0x1C 15.--31. 1. "Reserved_47,Reserved_47" newline bitfld.long 0x1C 14. "PAIR_TILES,If set then PBE will pair 16x16 tiles" "0,1" newline hexmask.long.word 0x1C 0.--13. 1. "SURFACE_Y_SIZE,Y Size in pixels (only used for strided memory layout with FBC)" line.long 0x20 "RGX_CR_PBE_WORD2_MRT4_0,Pixel Back end State Word 2." hexmask.long 0x20 0.--31. 1. "SW_BYTEMASK,SW driven mask" line.long 0x24 "RGX_CR_PBE_WORD2_MRT4_1,Pixel Back end State Word 2." hexmask.long.tbyte 0x24 15.--31. 1. "Reserved_47,Reserved_47" newline bitfld.long 0x24 14. "PAIR_TILES,If set then PBE will pair 16x16 tiles" "0,1" newline hexmask.long.word 0x24 0.--13. 1. "SURFACE_Y_SIZE,Y Size in pixels (only used for strided memory layout with FBC)" line.long 0x28 "RGX_CR_PBE_WORD2_MRT5_0,Pixel Back end State Word 2." hexmask.long 0x28 0.--31. 1. "SW_BYTEMASK,SW driven mask" line.long 0x2C "RGX_CR_PBE_WORD2_MRT5_1,Pixel Back end State Word 2." hexmask.long.tbyte 0x2C 15.--31. 1. "Reserved_47,Reserved_47" newline bitfld.long 0x2C 14. "PAIR_TILES,If set then PBE will pair 16x16 tiles" "0,1" newline hexmask.long.word 0x2C 0.--13. 1. "SURFACE_Y_SIZE,Y Size in pixels (only used for strided memory layout with FBC)" line.long 0x30 "RGX_CR_PBE_WORD2_MRT6_0,Pixel Back end State Word 2." hexmask.long 0x30 0.--31. 1. "SW_BYTEMASK,SW driven mask" line.long 0x34 "RGX_CR_PBE_WORD2_MRT6_1,Pixel Back end State Word 2." hexmask.long.tbyte 0x34 15.--31. 1. "Reserved_47,Reserved_47" newline bitfld.long 0x34 14. "PAIR_TILES,If set then PBE will pair 16x16 tiles" "0,1" newline hexmask.long.word 0x34 0.--13. 1. "SURFACE_Y_SIZE,Y Size in pixels (only used for strided memory layout with FBC)" line.long 0x38 "RGX_CR_PBE_WORD2_MRT7_0,Pixel Back end State Word 2." hexmask.long 0x38 0.--31. 1. "SW_BYTEMASK,SW driven mask" line.long 0x3C "RGX_CR_PBE_WORD2_MRT7_1,Pixel Back end State Word 2." hexmask.long.tbyte 0x3C 15.--31. 1. "Reserved_47,Reserved_47" newline bitfld.long 0x3C 14. "PAIR_TILES,If set then PBE will pair 16x16 tiles" "0,1" newline hexmask.long.word 0x3C 0.--13. 1. "SURFACE_Y_SIZE,Y Size in pixels (only used for strided memory layout with FBC)" group.long 0x1600++0x11F line.long 0x0 "RGX_CR_FB_CDC_0,Framebuffer Compression/Decompression arbiter modes" bitfld.long 0x0 30.--31. "FBDC_MCU_SLC_HDR_POLICY,SLC Cache policy for MCU requested FBDC header requests" "0,1,2,3" newline bitfld.long 0x0 28.--29. "FBDC_MCU_SLC_DATA_POLICY,SLC Cache policy for MCU requested FBDC tile data requests" "0,1,2,3" newline hexmask.long.word 0x0 12.--27. 1. "FBC_FBDC_COMPATIBILITY,The register defines the mode of operation to ensure that the GPU FBC/FBDC is compatible with any FBC/FBDC existing in the SoC (standalone FBC/FBDC). To be compatible the register needs to be programed with the version of the SoC.." newline bitfld.long 0x0 11. "FBC_FBDC_INVAL_OVERRIDE,When set then all FBDC header cache entries will be invalidate from the FBC otherwise only those associated with the request being processed by the FBC will be invalidated" "0,1" newline bitfld.long 0x0 10. "ZLS_SLC_NOLINEFILL,ZLS write SLC no line fill: 0=line fill on miss 1=no line fill on miss" "line fill on miss,no line fill on miss" newline bitfld.long 0x0 8.--9. "ZLS_SLC_POLICY,ZLS write SLC cache Policy" "0,1,2,3" newline bitfld.long 0x0 7. "PBE_SLC_NOLINEFILL,PBE write SLC no line fill: 0=line fill on miss 1=no line fill on miss" "line fill on miss,no line fill on miss" newline bitfld.long 0x0 5.--6. "PBE_SLC_POLICY,PBE write SLC cache Policy" "0,1,2,3" newline bitfld.long 0x0 4. "PBE_COR_COLOUR_ENABLE,PBE Enable correlation/decorrelation for PBE 0=disbaled 1=enabled" "disbaled,enabled" newline bitfld.long 0x0 3. "FBC_ARB_MODE,FBC Request Arbiter Mode 0 = Re-arbitrate after tile 1 = Re-arbitrate after valid drop and tile complete" "Re-arbitrate after tile,Re-arbitrate after valid drop and tile complete" newline bitfld.long 0x0 2. "Reserved_2,Reserved_2" "0,1" newline bitfld.long 0x0 1. "TLDECODE_ARB_MODE,TLCache Request Arbiter Mode Rearbitration:0 = valid dropped and burst complete 1 = After burst complete" "valid dropped and burst complete,After burst complete" newline bitfld.long 0x0 0. "BIF_ARB_MODE,FBC and FBDC BIF Arbiter Mode 0 = Re-arbitrate after burst 1 = Re-arbitrate after valid drop and burst complete" "Re-arbitrate after burst,Re-arbitrate after valid drop and burst complete" line.long 0x4 "RGX_CR_FB_CDC_1,Framebuffer Compression/Decompression arbiter modes" hexmask.long.tbyte 0x4 13.--31. 1. "Reserved_45,Reserved_45" newline bitfld.long 0x4 12. "FBCDC_COR_ENABLE,writing '0' the compression correlation/decorrelation is disable" "0,1" newline hexmask.long.byte 0x4 4.--11. 1. "Reserved_36,Reserved_36" newline bitfld.long 0x4 2.--3. "FBDC_ZLS_SLC_HDR_POLICY,SLC Cache policy for ZLS requested FBDC header requests" "0,1,2,3" newline bitfld.long 0x4 0.--1. "FBDC_ZLS_SLC_DATA_POLICY,SLC Cache policy for ZLS requested FBDC tile data requests" "0,1,2,3" line.long 0x8 "RGX_CR_FB_ICTRL_0,Framebuffer Invalidates" hexmask.long.word 0x8 23.--31. 1. "Reserved_23,Reserved_23" newline bitfld.long 0x8 22. "TLCACHE_INVALFLUSH_FASTRENDER_DM,When set to 1 all entries in the tile cache that have been tagged as a fastrender data master will be invalidate/flush when TLCACHE_INVALFLUSH_PENDING is set" "0,1" newline bitfld.long 0x8 19.--21. "Reserved_19,Reserved_19" "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x8 15.--18. 1. "FBDC_INVALIDATE_REQUESTER,Bit mask of requester to invalidate when FBDC_INVALIDATE_PENDING is set" newline bitfld.long 0x8 14. "TLCACHE_INVALFLUSH_TOMEM,When set to 1 all flushes will result in a flush fence being sent to memory after the tiles have been flushed. On return of this fence the TLCACHE_INVALFLUSH_PENDING will be cleared. When not set a flush fence is not sent and.." "0,1" newline hexmask.long.byte 0x8 10.--13. 1. "TLCACHE_INVALFLUSH_REQUESTER,Bit mask of requester to flush or invalidate when TLCACHE_INVALFUSH_PENDING is set These are also used in combination with the invalflush__DM mask bits" newline bitfld.long 0x8 8.--9. "Reserved_8,Reserved_8" "0,1,2,3" newline bitfld.long 0x8 7. "TLCACHE_INVALFLUSH_COMP_DM,When set to 1 all entries in the tile cache that have been tagged as a compute data master will be invalidate/flush when TLCACHE_INVALFLUSH_PENDING is set" "0,1" newline bitfld.long 0x8 6. "TLCACHE_INVALFLUSH_VERTEX_DM,When set to 1 all entries in the tile cache that have been tagged as a vertex data master will be invalidate/flush when TLCACHE_INVALFLUSH_PENDING is set" "0,1" newline bitfld.long 0x8 5. "TLCACHE_INVALFLUSH_PIXEL_DM,When set to 1 all entries in the tile cache that have been tagged as a pixel data master will be invalidate/flush when TLCACHE_INVALFLUSH_PENDING is set" "0,1" newline bitfld.long 0x8 3.--4. "TLCACHE_INVALFLUSH_PENDING,The cache may be requested to flush or invalidate or both in a single write access. Each bit when read returns the current status of the flush or invalidate request. Bit 0 = Invalidate Bit 1 = Flush If either bit is read back.." "Invalidate,Flush,?,?" newline bitfld.long 0x8 1.--2. "Reserved_1,Reserved_1" "0,1,2,3" newline bitfld.long 0x8 0. "FBDC_INVALIDATE_PENDING,When written to 1 will invalidate the header cache in the FBDC when read as 1 invalidate is in progress when read as 0 invalidate is complete" "0,1" line.long 0xC "RGX_CR_FB_ICTRL_1,Framebuffer Invalidates" hexmask.long 0xC 0.--31. 1. "Reserved_23,Reserved_23" line.long 0x10 "RGX_CR_FB_MEM_REGION0_0,Framebuffer Compression/Decompression memory regions for Host and TLA accesses" hexmask.long 0x10 0.--31. 1. "BASE_ADDRESS,Base address of this memory region in 512bit granularity" line.long 0x14 "RGX_CR_FB_MEM_REGION0_1,Framebuffer Compression/Decompression memory regions for Host and TLA accesses" hexmask.long.byte 0x14 25.--31. 1. "Reserved_57,Reserved_57" newline hexmask.long.tbyte 0x14 2.--24. 1. "NUM_TILES,The number of compressor tiles to be used in this memory region" newline bitfld.long 0x14 0.--1. "BASE_ADDRESS,Base address of this memory region in 512bit granularity" "0,1,2,3" line.long 0x18 "RGX_CR_FB_MEM_REGION1_0,Framebuffer Compression/Decompression memory regions for Host and TLA accesses" hexmask.long 0x18 0.--31. 1. "BASE_ADDRESS,Base address of this memory region in 512bit granularity" line.long 0x1C "RGX_CR_FB_MEM_REGION1_1,Framebuffer Compression/Decompression memory regions for Host and TLA accesses" hexmask.long.byte 0x1C 25.--31. 1. "Reserved_57,Reserved_57" newline hexmask.long.tbyte 0x1C 2.--24. 1. "NUM_TILES,The number of compressor tiles to be used in this memory region" newline bitfld.long 0x1C 0.--1. "BASE_ADDRESS,Base address of this memory region in 512bit granularity" "0,1,2,3" line.long 0x20 "RGX_CR_FB_MEM_REGION2_0,Framebuffer Compression/Decompression memory regions for Host and TLA accesses" hexmask.long 0x20 0.--31. 1. "BASE_ADDRESS,Base address of this memory region in 512bit granularity" line.long 0x24 "RGX_CR_FB_MEM_REGION2_1,Framebuffer Compression/Decompression memory regions for Host and TLA accesses" hexmask.long.byte 0x24 25.--31. 1. "Reserved_57,Reserved_57" newline hexmask.long.tbyte 0x24 2.--24. 1. "NUM_TILES,The number of compressor tiles to be used in this memory region" newline bitfld.long 0x24 0.--1. "BASE_ADDRESS,Base address of this memory region in 512bit granularity" "0,1,2,3" line.long 0x28 "RGX_CR_FB_MEM_REGION3_0,Framebuffer Compression/Decompression memory regions for Host and TLA accesses" hexmask.long 0x28 0.--31. 1. "BASE_ADDRESS,Base address of this memory region in 512bit granularity" line.long 0x2C "RGX_CR_FB_MEM_REGION3_1,Framebuffer Compression/Decompression memory regions for Host and TLA accesses" hexmask.long.byte 0x2C 25.--31. 1. "Reserved_57,Reserved_57" newline hexmask.long.tbyte 0x2C 2.--24. 1. "NUM_TILES,The number of compressor tiles to be used in this memory region" newline bitfld.long 0x2C 0.--1. "BASE_ADDRESS,Base address of this memory region in 512bit granularity" "0,1,2,3" line.long 0x30 "RGX_CR_FB_MEM_REGION4_0,Framebuffer Compression/Decompression memory regions for Host and TLA accesses" hexmask.long 0x30 0.--31. 1. "BASE_ADDRESS,Base address of this memory region in 512bit granularity" line.long 0x34 "RGX_CR_FB_MEM_REGION4_1,Framebuffer Compression/Decompression memory regions for Host and TLA accesses" hexmask.long.byte 0x34 25.--31. 1. "Reserved_57,Reserved_57" newline hexmask.long.tbyte 0x34 2.--24. 1. "NUM_TILES,The number of compressor tiles to be used in this memory region" newline bitfld.long 0x34 0.--1. "BASE_ADDRESS,Base address of this memory region in 512bit granularity" "0,1,2,3" line.long 0x38 "RGX_CR_FB_MEM_REGION5_0,Framebuffer Compression/Decompression memory regions for Host and TLA accesses" hexmask.long 0x38 0.--31. 1. "BASE_ADDRESS,Base address of this memory region in 512bit granularity" line.long 0x3C "RGX_CR_FB_MEM_REGION5_1,Framebuffer Compression/Decompression memory regions for Host and TLA accesses" hexmask.long.byte 0x3C 25.--31. 1. "Reserved_57,Reserved_57" newline hexmask.long.tbyte 0x3C 2.--24. 1. "NUM_TILES,The number of compressor tiles to be used in this memory region" newline bitfld.long 0x3C 0.--1. "BASE_ADDRESS,Base address of this memory region in 512bit granularity" "0,1,2,3" line.long 0x40 "RGX_CR_FB_MEM_REGION6_0,Framebuffer Compression/Decompression memory regions for Host and TLA accesses" hexmask.long 0x40 0.--31. 1. "BASE_ADDRESS,Base address of this memory region in 512bit granularity" line.long 0x44 "RGX_CR_FB_MEM_REGION6_1,Framebuffer Compression/Decompression memory regions for Host and TLA accesses" hexmask.long.byte 0x44 25.--31. 1. "Reserved_57,Reserved_57" newline hexmask.long.tbyte 0x44 2.--24. 1. "NUM_TILES,The number of compressor tiles to be used in this memory region" newline bitfld.long 0x44 0.--1. "BASE_ADDRESS,Base address of this memory region in 512bit granularity" "0,1,2,3" line.long 0x48 "RGX_CR_FB_MEM_REGION7_0,Framebuffer Compression/Decompression memory regions for Host and TLA accesses" hexmask.long 0x48 0.--31. 1. "BASE_ADDRESS,Base address of this memory region in 512bit granularity" line.long 0x4C "RGX_CR_FB_MEM_REGION7_1,Framebuffer Compression/Decompression memory regions for Host and TLA accesses" hexmask.long.byte 0x4C 25.--31. 1. "Reserved_57,Reserved_57" newline hexmask.long.tbyte 0x4C 2.--24. 1. "NUM_TILES,The number of compressor tiles to be used in this memory region" newline bitfld.long 0x4C 0.--1. "BASE_ADDRESS,Base address of this memory region in 512bit granularity" "0,1,2,3" line.long 0x50 "RGX_CR_FB_MEM_REGION8_0,Framebuffer Compression/Decompression memory regions for Host and TLA accesses" hexmask.long 0x50 0.--31. 1. "BASE_ADDRESS,Base address of this memory region in 512bit granularity" line.long 0x54 "RGX_CR_FB_MEM_REGION8_1,Framebuffer Compression/Decompression memory regions for Host and TLA accesses" hexmask.long.byte 0x54 25.--31. 1. "Reserved_57,Reserved_57" newline hexmask.long.tbyte 0x54 2.--24. 1. "NUM_TILES,The number of compressor tiles to be used in this memory region" newline bitfld.long 0x54 0.--1. "BASE_ADDRESS,Base address of this memory region in 512bit granularity" "0,1,2,3" line.long 0x58 "RGX_CR_FB_MEM_REGION9_0,Framebuffer Compression/Decompression memory regions for Host and TLA accesses" hexmask.long 0x58 0.--31. 1. "BASE_ADDRESS,Base address of this memory region in 512bit granularity" line.long 0x5C "RGX_CR_FB_MEM_REGION9_1,Framebuffer Compression/Decompression memory regions for Host and TLA accesses" hexmask.long.byte 0x5C 25.--31. 1. "Reserved_57,Reserved_57" newline hexmask.long.tbyte 0x5C 2.--24. 1. "NUM_TILES,The number of compressor tiles to be used in this memory region" newline bitfld.long 0x5C 0.--1. "BASE_ADDRESS,Base address of this memory region in 512bit granularity" "0,1,2,3" line.long 0x60 "RGX_CR_FB_MEM_REGION10_0,Framebuffer Compression/Decompression memory regions for Host and TLA accesses" hexmask.long 0x60 0.--31. 1. "BASE_ADDRESS,Base address of this memory region in 512bit granularity" line.long 0x64 "RGX_CR_FB_MEM_REGION10_1,Framebuffer Compression/Decompression memory regions for Host and TLA accesses" hexmask.long.byte 0x64 25.--31. 1. "Reserved_57,Reserved_57" newline hexmask.long.tbyte 0x64 2.--24. 1. "NUM_TILES,The number of compressor tiles to be used in this memory region" newline bitfld.long 0x64 0.--1. "BASE_ADDRESS,Base address of this memory region in 512bit granularity" "0,1,2,3" line.long 0x68 "RGX_CR_FB_MEM_REGION11_0,Framebuffer Compression/Decompression memory regions for Host and TLA accesses" hexmask.long 0x68 0.--31. 1. "BASE_ADDRESS,Base address of this memory region in 512bit granularity" line.long 0x6C "RGX_CR_FB_MEM_REGION11_1,Framebuffer Compression/Decompression memory regions for Host and TLA accesses" hexmask.long.byte 0x6C 25.--31. 1. "Reserved_57,Reserved_57" newline hexmask.long.tbyte 0x6C 2.--24. 1. "NUM_TILES,The number of compressor tiles to be used in this memory region" newline bitfld.long 0x6C 0.--1. "BASE_ADDRESS,Base address of this memory region in 512bit granularity" "0,1,2,3" line.long 0x70 "RGX_CR_FB_MEM_REGION12_0,Framebuffer Compression/Decompression memory regions for Host and TLA accesses" hexmask.long 0x70 0.--31. 1. "BASE_ADDRESS,Base address of this memory region in 512bit granularity" line.long 0x74 "RGX_CR_FB_MEM_REGION12_1,Framebuffer Compression/Decompression memory regions for Host and TLA accesses" hexmask.long.byte 0x74 25.--31. 1. "Reserved_57,Reserved_57" newline hexmask.long.tbyte 0x74 2.--24. 1. "NUM_TILES,The number of compressor tiles to be used in this memory region" newline bitfld.long 0x74 0.--1. "BASE_ADDRESS,Base address of this memory region in 512bit granularity" "0,1,2,3" line.long 0x78 "RGX_CR_FB_MEM_REGION13_0,Framebuffer Compression/Decompression memory regions for Host and TLA accesses" hexmask.long 0x78 0.--31. 1. "BASE_ADDRESS,Base address of this memory region in 512bit granularity" line.long 0x7C "RGX_CR_FB_MEM_REGION13_1,Framebuffer Compression/Decompression memory regions for Host and TLA accesses" hexmask.long.byte 0x7C 25.--31. 1. "Reserved_57,Reserved_57" newline hexmask.long.tbyte 0x7C 2.--24. 1. "NUM_TILES,The number of compressor tiles to be used in this memory region" newline bitfld.long 0x7C 0.--1. "BASE_ADDRESS,Base address of this memory region in 512bit granularity" "0,1,2,3" line.long 0x80 "RGX_CR_FB_MEM_REGION14_0,Framebuffer Compression/Decompression memory regions for Host and TLA accesses" hexmask.long 0x80 0.--31. 1. "BASE_ADDRESS,Base address of this memory region in 512bit granularity" line.long 0x84 "RGX_CR_FB_MEM_REGION14_1,Framebuffer Compression/Decompression memory regions for Host and TLA accesses" hexmask.long.byte 0x84 25.--31. 1. "Reserved_57,Reserved_57" newline hexmask.long.tbyte 0x84 2.--24. 1. "NUM_TILES,The number of compressor tiles to be used in this memory region" newline bitfld.long 0x84 0.--1. "BASE_ADDRESS,Base address of this memory region in 512bit granularity" "0,1,2,3" line.long 0x88 "RGX_CR_FB_MEM_REGION15_0,Framebuffer Compression/Decompression memory regions for Host and TLA accesses" hexmask.long 0x88 0.--31. 1. "BASE_ADDRESS,Base address of this memory region in 512bit granularity" line.long 0x8C "RGX_CR_FB_MEM_REGION15_1,Framebuffer Compression/Decompression memory regions for Host and TLA accesses" hexmask.long.byte 0x8C 25.--31. 1. "Reserved_57,Reserved_57" newline hexmask.long.tbyte 0x8C 2.--24. 1. "NUM_TILES,The number of compressor tiles to be used in this memory region" newline bitfld.long 0x8C 0.--1. "BASE_ADDRESS,Base address of this memory region in 512bit granularity" "0,1,2,3" line.long 0x90 "RGX_CR_FB_MEM_REGION_CTRL0_0,Framebuffer Compression/Decompression memory regions for Host and TLA accesses" hexmask.long.byte 0x90 25.--31. 1. "DIMY,Surface height in terms of TILE_TYPE for this memory region" newline hexmask.long.word 0x90 12.--24. 1. "DIMX,Surface width in terms of TILE_TYPE for this memory region" newline bitfld.long 0x90 11. "MEML,Surface Memory layout for this memory region 0=linear 1=twiddled" "linear,twiddled" newline bitfld.long 0x90 9.--10. "DM,Data master to be used for this memory region 00 = TA/Vertex 01 = 3D/Pixel 10 = Compute 11 = Data Master of Requester If the memory region is being accessed by the TLA the data master is set to the TLA data master If the memory region is being.." "TA/Vertex,?,?,?" newline bitfld.long 0x90 8. "TILE_TYPE,Compressor tile type 0 = 8x8 pixels 1 = 16x4 pixels" "0,1" newline hexmask.long.byte 0x90 1.--7. 1. "FMT,The pixel format to be used in this memory region" newline bitfld.long 0x90 0. "MODE,Defines if this memory region maps to BIF or FBC/FBDC access; 0 = BIF 1 = FBC/FBDC" "BIF,FBC/FBDC" line.long 0x94 "RGX_CR_FB_MEM_REGION_CTRL0_1,Framebuffer Compression/Decompression memory regions for Host and TLA accesses" hexmask.long.tbyte 0x94 15.--31. 1. "Reserved_47,Reserved_47" newline bitfld.long 0x94 14. "PORT,Defines if this memory region is to be used by the TLA or Host port. 0 = TLA Port 1 = Host Port" "TLA Port,Host Port" newline bitfld.long 0x94 13. "ACTIVE,Defines if this memory region is active or not default to INACTIVE. Used in conjuction with MODE field to define if a memory region maps to BIF or FBC/FBDC access. If active then this region base address is used to check if an access is for the.." "0,1" newline bitfld.long 0x94 12. "SLC_NOLINEFILL,SLC cache no line fill Policy: 0= line fill on miss 1=no line fill on miss" "line fill on miss,no line fill on miss" newline bitfld.long 0x94 10.--11. "SLC_POLICY,SLC cache Policy: 00=Bypass 01=Write Back 10 =Write Through 11=Cached Read" "Bypass,Write Back,?,?" newline bitfld.long 0x94 9. "TLCACHE_POLICY,Tile cache Policy: 1=no line fill on miss 0=line fill on miss" "line fill on miss,no line fill on miss" newline bitfld.long 0x94 8. "COR_COLOUR_ENABLE,Correlation Colour Enable 0=off 1=on" "off,on" newline bitfld.long 0x94 7. "IADDR,Direct/Indirect Addressing: 1=indirect 0=direct" "direct,indirect" newline hexmask.long.byte 0x94 0.--6. 1. "DIMY,Surface height in terms of TILE_TYPE for this memory region" line.long 0x98 "RGX_CR_FB_MEM_REGION_CTRL1_0,Framebuffer Compression/Decompression memory regions for Host and TLA accesses" hexmask.long.byte 0x98 25.--31. 1. "DIMY,Surface height in terms of TILE_TYPE for this memory region" newline hexmask.long.word 0x98 12.--24. 1. "DIMX,Surface width in terms of TILE_TYPE for this memory region" newline bitfld.long 0x98 11. "MEML,Surface Memory layout for this memory region 0=linear 1=twiddled" "linear,twiddled" newline bitfld.long 0x98 9.--10. "DM,Data master to be used for this memory region 00 = TA/Vertex 01 = 3D/Pixel 10 = Compute 11 = Data Master of Requester If the memory region is being accessed by the TLA the data master is set to the TLA data master If the memory region is being.." "TA/Vertex,?,?,?" newline bitfld.long 0x98 8. "TILE_TYPE,Compressor tile type 0 = 8x8 pixels 1 = 16x4 pixels" "0,1" newline hexmask.long.byte 0x98 1.--7. 1. "FMT,The pixel format to be used in this memory region" newline bitfld.long 0x98 0. "MODE,Defines if this memory region maps to BIF or FBC/FBDC access; 0 = BIF 1 = FBC/FBDC" "BIF,FBC/FBDC" line.long 0x9C "RGX_CR_FB_MEM_REGION_CTRL1_1,Framebuffer Compression/Decompression memory regions for Host and TLA accesses" hexmask.long.tbyte 0x9C 15.--31. 1. "Reserved_47,Reserved_47" newline bitfld.long 0x9C 14. "PORT,Defines if this memory region is to be used by the TLA or Host port. 0 = TLA Port 1 = Host Port" "TLA Port,Host Port" newline bitfld.long 0x9C 13. "ACTIVE,Defines if this memory region is active or not default to INACTIVE. Used in conjuction with MODE field to define if a memory region maps to BIF or FBC/FBDC access. If active then this region base address is used to check if an access is for the.." "0,1" newline bitfld.long 0x9C 12. "SLC_NOLINEFILL,SLC cache no line fill Policy: 0= line fill on miss 1=no line fill on miss" "line fill on miss,no line fill on miss" newline bitfld.long 0x9C 10.--11. "SLC_POLICY,SLC cache Policy: 00=Bypass 01=Write Back 10 =Write Through 11=Cached Read" "Bypass,Write Back,?,?" newline bitfld.long 0x9C 9. "TLCACHE_POLICY,Tile cache Policy: 1=no line fill on miss 0=line fill on miss" "line fill on miss,no line fill on miss" newline bitfld.long 0x9C 8. "COR_COLOUR_ENABLE,Correlation Colour Enable 0=off 1=on" "off,on" newline bitfld.long 0x9C 7. "IADDR,Direct/Indirect Addressing: 1=indirect 0=direct" "direct,indirect" newline hexmask.long.byte 0x9C 0.--6. 1. "DIMY,Surface height in terms of TILE_TYPE for this memory region" line.long 0xA0 "RGX_CR_FB_MEM_REGION_CTRL2_0,Framebuffer Compression/Decompression memory regions for Host and TLA accesses" hexmask.long.byte 0xA0 25.--31. 1. "DIMY,Surface height in terms of TILE_TYPE for this memory region" newline hexmask.long.word 0xA0 12.--24. 1. "DIMX,Surface width in terms of TILE_TYPE for this memory region" newline bitfld.long 0xA0 11. "MEML,Surface Memory layout for this memory region 0=linear 1=twiddled" "linear,twiddled" newline bitfld.long 0xA0 9.--10. "DM,Data master to be used for this memory region 00 = TA/Vertex 01 = 3D/Pixel 10 = Compute 11 = Data Master of Requester If the memory region is being accessed by the TLA the data master is set to the TLA data master If the memory region is being.." "TA/Vertex,?,?,?" newline bitfld.long 0xA0 8. "TILE_TYPE,Compressor tile type 0 = 8x8 pixels 1 = 16x4 pixels" "0,1" newline hexmask.long.byte 0xA0 1.--7. 1. "FMT,The pixel format to be used in this memory region" newline bitfld.long 0xA0 0. "MODE,Defines if this memory region maps to BIF or FBC/FBDC access; 0 = BIF 1 = FBC/FBDC" "BIF,FBC/FBDC" line.long 0xA4 "RGX_CR_FB_MEM_REGION_CTRL2_1,Framebuffer Compression/Decompression memory regions for Host and TLA accesses" hexmask.long.tbyte 0xA4 15.--31. 1. "Reserved_47,Reserved_47" newline bitfld.long 0xA4 14. "PORT,Defines if this memory region is to be used by the TLA or Host port. 0 = TLA Port 1 = Host Port" "TLA Port,Host Port" newline bitfld.long 0xA4 13. "ACTIVE,Defines if this memory region is active or not default to INACTIVE. Used in conjuction with MODE field to define if a memory region maps to BIF or FBC/FBDC access. If active then this region base address is used to check if an access is for the.." "0,1" newline bitfld.long 0xA4 12. "SLC_NOLINEFILL,SLC cache no line fill Policy: 0= line fill on miss 1=no line fill on miss" "line fill on miss,no line fill on miss" newline bitfld.long 0xA4 10.--11. "SLC_POLICY,SLC cache Policy: 00=Bypass 01=Write Back 10 =Write Through 11=Cached Read" "Bypass,Write Back,?,?" newline bitfld.long 0xA4 9. "TLCACHE_POLICY,Tile cache Policy: 1=no line fill on miss 0=line fill on miss" "line fill on miss,no line fill on miss" newline bitfld.long 0xA4 8. "COR_COLOUR_ENABLE,Correlation Colour Enable 0=off 1=on" "off,on" newline bitfld.long 0xA4 7. "IADDR,Direct/Indirect Addressing: 1=indirect 0=direct" "direct,indirect" newline hexmask.long.byte 0xA4 0.--6. 1. "DIMY,Surface height in terms of TILE_TYPE for this memory region" line.long 0xA8 "RGX_CR_FB_MEM_REGION_CTRL3_0,Framebuffer Compression/Decompression memory regions for Host and TLA accesses" hexmask.long.byte 0xA8 25.--31. 1. "DIMY,Surface height in terms of TILE_TYPE for this memory region" newline hexmask.long.word 0xA8 12.--24. 1. "DIMX,Surface width in terms of TILE_TYPE for this memory region" newline bitfld.long 0xA8 11. "MEML,Surface Memory layout for this memory region 0=linear 1=twiddled" "linear,twiddled" newline bitfld.long 0xA8 9.--10. "DM,Data master to be used for this memory region 00 = TA/Vertex 01 = 3D/Pixel 10 = Compute 11 = Data Master of Requester If the memory region is being accessed by the TLA the data master is set to the TLA data master If the memory region is being.." "TA/Vertex,?,?,?" newline bitfld.long 0xA8 8. "TILE_TYPE,Compressor tile type 0 = 8x8 pixels 1 = 16x4 pixels" "0,1" newline hexmask.long.byte 0xA8 1.--7. 1. "FMT,The pixel format to be used in this memory region" newline bitfld.long 0xA8 0. "MODE,Defines if this memory region maps to BIF or FBC/FBDC access; 0 = BIF 1 = FBC/FBDC" "BIF,FBC/FBDC" line.long 0xAC "RGX_CR_FB_MEM_REGION_CTRL3_1,Framebuffer Compression/Decompression memory regions for Host and TLA accesses" hexmask.long.tbyte 0xAC 15.--31. 1. "Reserved_47,Reserved_47" newline bitfld.long 0xAC 14. "PORT,Defines if this memory region is to be used by the TLA or Host port. 0 = TLA Port 1 = Host Port" "TLA Port,Host Port" newline bitfld.long 0xAC 13. "ACTIVE,Defines if this memory region is active or not default to INACTIVE. Used in conjuction with MODE field to define if a memory region maps to BIF or FBC/FBDC access. If active then this region base address is used to check if an access is for the.." "0,1" newline bitfld.long 0xAC 12. "SLC_NOLINEFILL,SLC cache no line fill Policy: 0= line fill on miss 1=no line fill on miss" "line fill on miss,no line fill on miss" newline bitfld.long 0xAC 10.--11. "SLC_POLICY,SLC cache Policy: 00=Bypass 01=Write Back 10 =Write Through 11=Cached Read" "Bypass,Write Back,?,?" newline bitfld.long 0xAC 9. "TLCACHE_POLICY,Tile cache Policy: 1=no line fill on miss 0=line fill on miss" "line fill on miss,no line fill on miss" newline bitfld.long 0xAC 8. "COR_COLOUR_ENABLE,Correlation Colour Enable 0=off 1=on" "off,on" newline bitfld.long 0xAC 7. "IADDR,Direct/Indirect Addressing: 1=indirect 0=direct" "direct,indirect" newline hexmask.long.byte 0xAC 0.--6. 1. "DIMY,Surface height in terms of TILE_TYPE for this memory region" line.long 0xB0 "RGX_CR_FB_MEM_REGION_CTRL4_0,Framebuffer Compression/Decompression memory regions for Host and TLA accesses" hexmask.long.byte 0xB0 25.--31. 1. "DIMY,Surface height in terms of TILE_TYPE for this memory region" newline hexmask.long.word 0xB0 12.--24. 1. "DIMX,Surface width in terms of TILE_TYPE for this memory region" newline bitfld.long 0xB0 11. "MEML,Surface Memory layout for this memory region 0=linear 1=twiddled" "linear,twiddled" newline bitfld.long 0xB0 9.--10. "DM,Data master to be used for this memory region 00 = TA/Vertex 01 = 3D/Pixel 10 = Compute 11 = Data Master of Requester If the memory region is being accessed by the TLA the data master is set to the TLA data master If the memory region is being.." "TA/Vertex,?,?,?" newline bitfld.long 0xB0 8. "TILE_TYPE,Compressor tile type 0 = 8x8 pixels 1 = 16x4 pixels" "0,1" newline hexmask.long.byte 0xB0 1.--7. 1. "FMT,The pixel format to be used in this memory region" newline bitfld.long 0xB0 0. "MODE,Defines if this memory region maps to BIF or FBC/FBDC access; 0 = BIF 1 = FBC/FBDC" "BIF,FBC/FBDC" line.long 0xB4 "RGX_CR_FB_MEM_REGION_CTRL4_1,Framebuffer Compression/Decompression memory regions for Host and TLA accesses" hexmask.long.tbyte 0xB4 15.--31. 1. "Reserved_47,Reserved_47" newline bitfld.long 0xB4 14. "PORT,Defines if this memory region is to be used by the TLA or Host port. 0 = TLA Port 1 = Host Port" "TLA Port,Host Port" newline bitfld.long 0xB4 13. "ACTIVE,Defines if this memory region is active or not default to INACTIVE. Used in conjuction with MODE field to define if a memory region maps to BIF or FBC/FBDC access. If active then this region base address is used to check if an access is for the.." "0,1" newline bitfld.long 0xB4 12. "SLC_NOLINEFILL,SLC cache no line fill Policy: 0= line fill on miss 1=no line fill on miss" "line fill on miss,no line fill on miss" newline bitfld.long 0xB4 10.--11. "SLC_POLICY,SLC cache Policy: 00=Bypass 01=Write Back 10 =Write Through 11=Cached Read" "Bypass,Write Back,?,?" newline bitfld.long 0xB4 9. "TLCACHE_POLICY,Tile cache Policy: 1=no line fill on miss 0=line fill on miss" "line fill on miss,no line fill on miss" newline bitfld.long 0xB4 8. "COR_COLOUR_ENABLE,Correlation Colour Enable 0=off 1=on" "off,on" newline bitfld.long 0xB4 7. "IADDR,Direct/Indirect Addressing: 1=indirect 0=direct" "direct,indirect" newline hexmask.long.byte 0xB4 0.--6. 1. "DIMY,Surface height in terms of TILE_TYPE for this memory region" line.long 0xB8 "RGX_CR_FB_MEM_REGION_CTRL5_0,Framebuffer Compression/Decompression memory regions for Host and TLA accesses" hexmask.long.byte 0xB8 25.--31. 1. "DIMY,Surface height in terms of TILE_TYPE for this memory region" newline hexmask.long.word 0xB8 12.--24. 1. "DIMX,Surface width in terms of TILE_TYPE for this memory region" newline bitfld.long 0xB8 11. "MEML,Surface Memory layout for this memory region 0=linear 1=twiddled" "linear,twiddled" newline bitfld.long 0xB8 9.--10. "DM,Data master to be used for this memory region 00 = TA/Vertex 01 = 3D/Pixel 10 = Compute 11 = Data Master of Requester If the memory region is being accessed by the TLA the data master is set to the TLA data master If the memory region is being.." "TA/Vertex,?,?,?" newline bitfld.long 0xB8 8. "TILE_TYPE,Compressor tile type 0 = 8x8 pixels 1 = 16x4 pixels" "0,1" newline hexmask.long.byte 0xB8 1.--7. 1. "FMT,The pixel format to be used in this memory region" newline bitfld.long 0xB8 0. "MODE,Defines if this memory region maps to BIF or FBC/FBDC access; 0 = BIF 1 = FBC/FBDC" "BIF,FBC/FBDC" line.long 0xBC "RGX_CR_FB_MEM_REGION_CTRL5_1,Framebuffer Compression/Decompression memory regions for Host and TLA accesses" hexmask.long.tbyte 0xBC 15.--31. 1. "Reserved_47,Reserved_47" newline bitfld.long 0xBC 14. "PORT,Defines if this memory region is to be used by the TLA or Host port. 0 = TLA Port 1 = Host Port" "TLA Port,Host Port" newline bitfld.long 0xBC 13. "ACTIVE,Defines if this memory region is active or not default to INACTIVE. Used in conjuction with MODE field to define if a memory region maps to BIF or FBC/FBDC access. If active then this region base address is used to check if an access is for the.." "0,1" newline bitfld.long 0xBC 12. "SLC_NOLINEFILL,SLC cache no line fill Policy: 0= line fill on miss 1=no line fill on miss" "line fill on miss,no line fill on miss" newline bitfld.long 0xBC 10.--11. "SLC_POLICY,SLC cache Policy: 00=Bypass 01=Write Back 10 =Write Through 11=Cached Read" "Bypass,Write Back,?,?" newline bitfld.long 0xBC 9. "TLCACHE_POLICY,Tile cache Policy: 1=no line fill on miss 0=line fill on miss" "line fill on miss,no line fill on miss" newline bitfld.long 0xBC 8. "COR_COLOUR_ENABLE,Correlation Colour Enable 0=off 1=on" "off,on" newline bitfld.long 0xBC 7. "IADDR,Direct/Indirect Addressing: 1=indirect 0=direct" "direct,indirect" newline hexmask.long.byte 0xBC 0.--6. 1. "DIMY,Surface height in terms of TILE_TYPE for this memory region" line.long 0xC0 "RGX_CR_FB_MEM_REGION_CTRL6_0,Framebuffer Compression/Decompression memory regions for Host and TLA accesses" hexmask.long.byte 0xC0 25.--31. 1. "DIMY,Surface height in terms of TILE_TYPE for this memory region" newline hexmask.long.word 0xC0 12.--24. 1. "DIMX,Surface width in terms of TILE_TYPE for this memory region" newline bitfld.long 0xC0 11. "MEML,Surface Memory layout for this memory region 0=linear 1=twiddled" "linear,twiddled" newline bitfld.long 0xC0 9.--10. "DM,Data master to be used for this memory region 00 = TA/Vertex 01 = 3D/Pixel 10 = Compute 11 = Data Master of Requester If the memory region is being accessed by the TLA the data master is set to the TLA data master If the memory region is being.." "TA/Vertex,?,?,?" newline bitfld.long 0xC0 8. "TILE_TYPE,Compressor tile type 0 = 8x8 pixels 1 = 16x4 pixels" "0,1" newline hexmask.long.byte 0xC0 1.--7. 1. "FMT,The pixel format to be used in this memory region" newline bitfld.long 0xC0 0. "MODE,Defines if this memory region maps to BIF or FBC/FBDC access; 0 = BIF 1 = FBC/FBDC" "BIF,FBC/FBDC" line.long 0xC4 "RGX_CR_FB_MEM_REGION_CTRL6_1,Framebuffer Compression/Decompression memory regions for Host and TLA accesses" hexmask.long.tbyte 0xC4 15.--31. 1. "Reserved_47,Reserved_47" newline bitfld.long 0xC4 14. "PORT,Defines if this memory region is to be used by the TLA or Host port. 0 = TLA Port 1 = Host Port" "TLA Port,Host Port" newline bitfld.long 0xC4 13. "ACTIVE,Defines if this memory region is active or not default to INACTIVE. Used in conjuction with MODE field to define if a memory region maps to BIF or FBC/FBDC access. If active then this region base address is used to check if an access is for the.." "0,1" newline bitfld.long 0xC4 12. "SLC_NOLINEFILL,SLC cache no line fill Policy: 0= line fill on miss 1=no line fill on miss" "line fill on miss,no line fill on miss" newline bitfld.long 0xC4 10.--11. "SLC_POLICY,SLC cache Policy: 00=Bypass 01=Write Back 10 =Write Through 11=Cached Read" "Bypass,Write Back,?,?" newline bitfld.long 0xC4 9. "TLCACHE_POLICY,Tile cache Policy: 1=no line fill on miss 0=line fill on miss" "line fill on miss,no line fill on miss" newline bitfld.long 0xC4 8. "COR_COLOUR_ENABLE,Correlation Colour Enable 0=off 1=on" "off,on" newline bitfld.long 0xC4 7. "IADDR,Direct/Indirect Addressing: 1=indirect 0=direct" "direct,indirect" newline hexmask.long.byte 0xC4 0.--6. 1. "DIMY,Surface height in terms of TILE_TYPE for this memory region" line.long 0xC8 "RGX_CR_FB_MEM_REGION_CTRL7_0,Framebuffer Compression/Decompression memory regions for Host and TLA accesses" hexmask.long.byte 0xC8 25.--31. 1. "DIMY,Surface height in terms of TILE_TYPE for this memory region" newline hexmask.long.word 0xC8 12.--24. 1. "DIMX,Surface width in terms of TILE_TYPE for this memory region" newline bitfld.long 0xC8 11. "MEML,Surface Memory layout for this memory region 0=linear 1=twiddled" "linear,twiddled" newline bitfld.long 0xC8 9.--10. "DM,Data master to be used for this memory region 00 = TA/Vertex 01 = 3D/Pixel 10 = Compute 11 = Data Master of Requester If the memory region is being accessed by the TLA the data master is set to the TLA data master If the memory region is being.." "TA/Vertex,?,?,?" newline bitfld.long 0xC8 8. "TILE_TYPE,Compressor tile type 0 = 8x8 pixels 1 = 16x4 pixels" "0,1" newline hexmask.long.byte 0xC8 1.--7. 1. "FMT,The pixel format to be used in this memory region" newline bitfld.long 0xC8 0. "MODE,Defines if this memory region maps to BIF or FBC/FBDC access; 0 = BIF 1 = FBC/FBDC" "BIF,FBC/FBDC" line.long 0xCC "RGX_CR_FB_MEM_REGION_CTRL7_1,Framebuffer Compression/Decompression memory regions for Host and TLA accesses" hexmask.long.tbyte 0xCC 15.--31. 1. "Reserved_47,Reserved_47" newline bitfld.long 0xCC 14. "PORT,Defines if this memory region is to be used by the TLA or Host port. 0 = TLA Port 1 = Host Port" "TLA Port,Host Port" newline bitfld.long 0xCC 13. "ACTIVE,Defines if this memory region is active or not default to INACTIVE. Used in conjuction with MODE field to define if a memory region maps to BIF or FBC/FBDC access. If active then this region base address is used to check if an access is for the.." "0,1" newline bitfld.long 0xCC 12. "SLC_NOLINEFILL,SLC cache no line fill Policy: 0= line fill on miss 1=no line fill on miss" "line fill on miss,no line fill on miss" newline bitfld.long 0xCC 10.--11. "SLC_POLICY,SLC cache Policy: 00=Bypass 01=Write Back 10 =Write Through 11=Cached Read" "Bypass,Write Back,?,?" newline bitfld.long 0xCC 9. "TLCACHE_POLICY,Tile cache Policy: 1=no line fill on miss 0=line fill on miss" "line fill on miss,no line fill on miss" newline bitfld.long 0xCC 8. "COR_COLOUR_ENABLE,Correlation Colour Enable 0=off 1=on" "off,on" newline bitfld.long 0xCC 7. "IADDR,Direct/Indirect Addressing: 1=indirect 0=direct" "direct,indirect" newline hexmask.long.byte 0xCC 0.--6. 1. "DIMY,Surface height in terms of TILE_TYPE for this memory region" line.long 0xD0 "RGX_CR_FB_MEM_REGION_CTRL8_0,Framebuffer Compression/Decompression memory regions for Host and TLA accesses" hexmask.long.byte 0xD0 25.--31. 1. "DIMY,Surface height in terms of TILE_TYPE for this memory region" newline hexmask.long.word 0xD0 12.--24. 1. "DIMX,Surface width in terms of TILE_TYPE for this memory region" newline bitfld.long 0xD0 11. "MEML,Surface Memory layout for this memory region 0=linear 1=twiddled" "linear,twiddled" newline bitfld.long 0xD0 9.--10. "DM,Data master to be used for this memory region 00 = TA/Vertex 01 = 3D/Pixel 10 = Compute 11 = Data Master of Requester If the memory region is being accessed by the TLA the data master is set to the TLA data master If the memory region is being.." "TA/Vertex,?,?,?" newline bitfld.long 0xD0 8. "TILE_TYPE,Compressor tile type 0 = 8x8 pixels 1 = 16x4 pixels" "0,1" newline hexmask.long.byte 0xD0 1.--7. 1. "FMT,The pixel format to be used in this memory region" newline bitfld.long 0xD0 0. "MODE,Defines if this memory region maps to BIF or FBC/FBDC access; 0 = BIF 1 = FBC/FBDC" "BIF,FBC/FBDC" line.long 0xD4 "RGX_CR_FB_MEM_REGION_CTRL8_1,Framebuffer Compression/Decompression memory regions for Host and TLA accesses" hexmask.long.tbyte 0xD4 15.--31. 1. "Reserved_47,Reserved_47" newline bitfld.long 0xD4 14. "PORT,Defines if this memory region is to be used by the TLA or Host port. 0 = TLA Port 1 = Host Port" "TLA Port,Host Port" newline bitfld.long 0xD4 13. "ACTIVE,Defines if this memory region is active or not default to INACTIVE. Used in conjuction with MODE field to define if a memory region maps to BIF or FBC/FBDC access. If active then this region base address is used to check if an access is for the.." "0,1" newline bitfld.long 0xD4 12. "SLC_NOLINEFILL,SLC cache no line fill Policy: 0= line fill on miss 1=no line fill on miss" "line fill on miss,no line fill on miss" newline bitfld.long 0xD4 10.--11. "SLC_POLICY,SLC cache Policy: 00=Bypass 01=Write Back 10 =Write Through 11=Cached Read" "Bypass,Write Back,?,?" newline bitfld.long 0xD4 9. "TLCACHE_POLICY,Tile cache Policy: 1=no line fill on miss 0=line fill on miss" "line fill on miss,no line fill on miss" newline bitfld.long 0xD4 8. "COR_COLOUR_ENABLE,Correlation Colour Enable 0=off 1=on" "off,on" newline bitfld.long 0xD4 7. "IADDR,Direct/Indirect Addressing: 1=indirect 0=direct" "direct,indirect" newline hexmask.long.byte 0xD4 0.--6. 1. "DIMY,Surface height in terms of TILE_TYPE for this memory region" line.long 0xD8 "RGX_CR_FB_MEM_REGION_CTRL9_0,Framebuffer Compression/Decompression memory regions for Host and TLA accesses" hexmask.long.byte 0xD8 25.--31. 1. "DIMY,Surface height in terms of TILE_TYPE for this memory region" newline hexmask.long.word 0xD8 12.--24. 1. "DIMX,Surface width in terms of TILE_TYPE for this memory region" newline bitfld.long 0xD8 11. "MEML,Surface Memory layout for this memory region 0=linear 1=twiddled" "linear,twiddled" newline bitfld.long 0xD8 9.--10. "DM,Data master to be used for this memory region 00 = TA/Vertex 01 = 3D/Pixel 10 = Compute 11 = Data Master of Requester If the memory region is being accessed by the TLA the data master is set to the TLA data master If the memory region is being.." "TA/Vertex,?,?,?" newline bitfld.long 0xD8 8. "TILE_TYPE,Compressor tile type 0 = 8x8 pixels 1 = 16x4 pixels" "0,1" newline hexmask.long.byte 0xD8 1.--7. 1. "FMT,The pixel format to be used in this memory region" newline bitfld.long 0xD8 0. "MODE,Defines if this memory region maps to BIF or FBC/FBDC access; 0 = BIF 1 = FBC/FBDC" "BIF,FBC/FBDC" line.long 0xDC "RGX_CR_FB_MEM_REGION_CTRL9_1,Framebuffer Compression/Decompression memory regions for Host and TLA accesses" hexmask.long.tbyte 0xDC 15.--31. 1. "Reserved_47,Reserved_47" newline bitfld.long 0xDC 14. "PORT,Defines if this memory region is to be used by the TLA or Host port. 0 = TLA Port 1 = Host Port" "TLA Port,Host Port" newline bitfld.long 0xDC 13. "ACTIVE,Defines if this memory region is active or not default to INACTIVE. Used in conjuction with MODE field to define if a memory region maps to BIF or FBC/FBDC access. If active then this region base address is used to check if an access is for the.." "0,1" newline bitfld.long 0xDC 12. "SLC_NOLINEFILL,SLC cache no line fill Policy: 0= line fill on miss 1=no line fill on miss" "line fill on miss,no line fill on miss" newline bitfld.long 0xDC 10.--11. "SLC_POLICY,SLC cache Policy: 00=Bypass 01=Write Back 10 =Write Through 11=Cached Read" "Bypass,Write Back,?,?" newline bitfld.long 0xDC 9. "TLCACHE_POLICY,Tile cache Policy: 1=no line fill on miss 0=line fill on miss" "line fill on miss,no line fill on miss" newline bitfld.long 0xDC 8. "COR_COLOUR_ENABLE,Correlation Colour Enable 0=off 1=on" "off,on" newline bitfld.long 0xDC 7. "IADDR,Direct/Indirect Addressing: 1=indirect 0=direct" "direct,indirect" newline hexmask.long.byte 0xDC 0.--6. 1. "DIMY,Surface height in terms of TILE_TYPE for this memory region" line.long 0xE0 "RGX_CR_FB_MEM_REGION_CTRL10_0,Framebuffer Compression/Decompression memory regions for Host and TLA accesses" hexmask.long.byte 0xE0 25.--31. 1. "DIMY,Surface height in terms of TILE_TYPE for this memory region" newline hexmask.long.word 0xE0 12.--24. 1. "DIMX,Surface width in terms of TILE_TYPE for this memory region" newline bitfld.long 0xE0 11. "MEML,Surface Memory layout for this memory region 0=linear 1=twiddled" "linear,twiddled" newline bitfld.long 0xE0 9.--10. "DM,Data master to be used for this memory region 00 = TA/Vertex 01 = 3D/Pixel 10 = Compute 11 = Data Master of Requester If the memory region is being accessed by the TLA the data master is set to the TLA data master If the memory region is being.." "TA/Vertex,?,?,?" newline bitfld.long 0xE0 8. "TILE_TYPE,Compressor tile type 0 = 8x8 pixels 1 = 16x4 pixels" "0,1" newline hexmask.long.byte 0xE0 1.--7. 1. "FMT,The pixel format to be used in this memory region" newline bitfld.long 0xE0 0. "MODE,Defines if this memory region maps to BIF or FBC/FBDC access; 0 = BIF 1 = FBC/FBDC" "BIF,FBC/FBDC" line.long 0xE4 "RGX_CR_FB_MEM_REGION_CTRL10_1,Framebuffer Compression/Decompression memory regions for Host and TLA accesses" hexmask.long.tbyte 0xE4 15.--31. 1. "Reserved_47,Reserved_47" newline bitfld.long 0xE4 14. "PORT,Defines if this memory region is to be used by the TLA or Host port. 0 = TLA Port 1 = Host Port" "TLA Port,Host Port" newline bitfld.long 0xE4 13. "ACTIVE,Defines if this memory region is active or not default to INACTIVE. Used in conjuction with MODE field to define if a memory region maps to BIF or FBC/FBDC access. If active then this region base address is used to check if an access is for the.." "0,1" newline bitfld.long 0xE4 12. "SLC_NOLINEFILL,SLC cache no line fill Policy: 0= line fill on miss 1=no line fill on miss" "line fill on miss,no line fill on miss" newline bitfld.long 0xE4 10.--11. "SLC_POLICY,SLC cache Policy: 00=Bypass 01=Write Back 10 =Write Through 11=Cached Read" "Bypass,Write Back,?,?" newline bitfld.long 0xE4 9. "TLCACHE_POLICY,Tile cache Policy: 1=no line fill on miss 0=line fill on miss" "line fill on miss,no line fill on miss" newline bitfld.long 0xE4 8. "COR_COLOUR_ENABLE,Correlation Colour Enable 0=off 1=on" "off,on" newline bitfld.long 0xE4 7. "IADDR,Direct/Indirect Addressing: 1=indirect 0=direct" "direct,indirect" newline hexmask.long.byte 0xE4 0.--6. 1. "DIMY,Surface height in terms of TILE_TYPE for this memory region" line.long 0xE8 "RGX_CR_FB_MEM_REGION_CTRL11_0,Framebuffer Compression/Decompression memory regions for Host and TLA accesses" hexmask.long.byte 0xE8 25.--31. 1. "DIMY,Surface height in terms of TILE_TYPE for this memory region" newline hexmask.long.word 0xE8 12.--24. 1. "DIMX,Surface width in terms of TILE_TYPE for this memory region" newline bitfld.long 0xE8 11. "MEML,Surface Memory layout for this memory region 0=linear 1=twiddled" "linear,twiddled" newline bitfld.long 0xE8 9.--10. "DM,Data master to be used for this memory region 00 = TA/Vertex 01 = 3D/Pixel 10 = Compute 11 = Data Master of Requester If the memory region is being accessed by the TLA the data master is set to the TLA data master If the memory region is being.." "TA/Vertex,?,?,?" newline bitfld.long 0xE8 8. "TILE_TYPE,Compressor tile type 0 = 8x8 pixels 1 = 16x4 pixels" "0,1" newline hexmask.long.byte 0xE8 1.--7. 1. "FMT,The pixel format to be used in this memory region" newline bitfld.long 0xE8 0. "MODE,Defines if this memory region maps to BIF or FBC/FBDC access; 0 = BIF 1 = FBC/FBDC" "BIF,FBC/FBDC" line.long 0xEC "RGX_CR_FB_MEM_REGION_CTRL11_1,Framebuffer Compression/Decompression memory regions for Host and TLA accesses" hexmask.long.tbyte 0xEC 15.--31. 1. "Reserved_47,Reserved_47" newline bitfld.long 0xEC 14. "PORT,Defines if this memory region is to be used by the TLA or Host port. 0 = TLA Port 1 = Host Port" "TLA Port,Host Port" newline bitfld.long 0xEC 13. "ACTIVE,Defines if this memory region is active or not default to INACTIVE. Used in conjuction with MODE field to define if a memory region maps to BIF or FBC/FBDC access. If active then this region base address is used to check if an access is for the.." "0,1" newline bitfld.long 0xEC 12. "SLC_NOLINEFILL,SLC cache no line fill Policy: 0= line fill on miss 1=no line fill on miss" "line fill on miss,no line fill on miss" newline bitfld.long 0xEC 10.--11. "SLC_POLICY,SLC cache Policy: 00=Bypass 01=Write Back 10 =Write Through 11=Cached Read" "Bypass,Write Back,?,?" newline bitfld.long 0xEC 9. "TLCACHE_POLICY,Tile cache Policy: 1=no line fill on miss 0=line fill on miss" "line fill on miss,no line fill on miss" newline bitfld.long 0xEC 8. "COR_COLOUR_ENABLE,Correlation Colour Enable 0=off 1=on" "off,on" newline bitfld.long 0xEC 7. "IADDR,Direct/Indirect Addressing: 1=indirect 0=direct" "direct,indirect" newline hexmask.long.byte 0xEC 0.--6. 1. "DIMY,Surface height in terms of TILE_TYPE for this memory region" line.long 0xF0 "RGX_CR_FB_MEM_REGION_CTRL12_0,Framebuffer Compression/Decompression memory regions for Host and TLA accesses" hexmask.long.byte 0xF0 25.--31. 1. "DIMY,Surface height in terms of TILE_TYPE for this memory region" newline hexmask.long.word 0xF0 12.--24. 1. "DIMX,Surface width in terms of TILE_TYPE for this memory region" newline bitfld.long 0xF0 11. "MEML,Surface Memory layout for this memory region 0=linear 1=twiddled" "linear,twiddled" newline bitfld.long 0xF0 9.--10. "DM,Data master to be used for this memory region 00 = TA/Vertex 01 = 3D/Pixel 10 = Compute 11 = Data Master of Requester If the memory region is being accessed by the TLA the data master is set to the TLA data master If the memory region is being.." "TA/Vertex,?,?,?" newline bitfld.long 0xF0 8. "TILE_TYPE,Compressor tile type 0 = 8x8 pixels 1 = 16x4 pixels" "0,1" newline hexmask.long.byte 0xF0 1.--7. 1. "FMT,The pixel format to be used in this memory region" newline bitfld.long 0xF0 0. "MODE,Defines if this memory region maps to BIF or FBC/FBDC access; 0 = BIF 1 = FBC/FBDC" "BIF,FBC/FBDC" line.long 0xF4 "RGX_CR_FB_MEM_REGION_CTRL12_1,Framebuffer Compression/Decompression memory regions for Host and TLA accesses" hexmask.long.tbyte 0xF4 15.--31. 1. "Reserved_47,Reserved_47" newline bitfld.long 0xF4 14. "PORT,Defines if this memory region is to be used by the TLA or Host port. 0 = TLA Port 1 = Host Port" "TLA Port,Host Port" newline bitfld.long 0xF4 13. "ACTIVE,Defines if this memory region is active or not default to INACTIVE. Used in conjuction with MODE field to define if a memory region maps to BIF or FBC/FBDC access. If active then this region base address is used to check if an access is for the.." "0,1" newline bitfld.long 0xF4 12. "SLC_NOLINEFILL,SLC cache no line fill Policy: 0= line fill on miss 1=no line fill on miss" "line fill on miss,no line fill on miss" newline bitfld.long 0xF4 10.--11. "SLC_POLICY,SLC cache Policy: 00=Bypass 01=Write Back 10 =Write Through 11=Cached Read" "Bypass,Write Back,?,?" newline bitfld.long 0xF4 9. "TLCACHE_POLICY,Tile cache Policy: 1=no line fill on miss 0=line fill on miss" "line fill on miss,no line fill on miss" newline bitfld.long 0xF4 8. "COR_COLOUR_ENABLE,Correlation Colour Enable 0=off 1=on" "off,on" newline bitfld.long 0xF4 7. "IADDR,Direct/Indirect Addressing: 1=indirect 0=direct" "direct,indirect" newline hexmask.long.byte 0xF4 0.--6. 1. "DIMY,Surface height in terms of TILE_TYPE for this memory region" line.long 0xF8 "RGX_CR_FB_MEM_REGION_CTRL13_0,Framebuffer Compression/Decompression memory regions for Host and TLA accesses" hexmask.long.byte 0xF8 25.--31. 1. "DIMY,Surface height in terms of TILE_TYPE for this memory region" newline hexmask.long.word 0xF8 12.--24. 1. "DIMX,Surface width in terms of TILE_TYPE for this memory region" newline bitfld.long 0xF8 11. "MEML,Surface Memory layout for this memory region 0=linear 1=twiddled" "linear,twiddled" newline bitfld.long 0xF8 9.--10. "DM,Data master to be used for this memory region 00 = TA/Vertex 01 = 3D/Pixel 10 = Compute 11 = Data Master of Requester If the memory region is being accessed by the TLA the data master is set to the TLA data master If the memory region is being.." "TA/Vertex,?,?,?" newline bitfld.long 0xF8 8. "TILE_TYPE,Compressor tile type 0 = 8x8 pixels 1 = 16x4 pixels" "0,1" newline hexmask.long.byte 0xF8 1.--7. 1. "FMT,The pixel format to be used in this memory region" newline bitfld.long 0xF8 0. "MODE,Defines if this memory region maps to BIF or FBC/FBDC access; 0 = BIF 1 = FBC/FBDC" "BIF,FBC/FBDC" line.long 0xFC "RGX_CR_FB_MEM_REGION_CTRL13_1,Framebuffer Compression/Decompression memory regions for Host and TLA accesses" hexmask.long.tbyte 0xFC 15.--31. 1. "Reserved_47,Reserved_47" newline bitfld.long 0xFC 14. "PORT,Defines if this memory region is to be used by the TLA or Host port. 0 = TLA Port 1 = Host Port" "TLA Port,Host Port" newline bitfld.long 0xFC 13. "ACTIVE,Defines if this memory region is active or not default to INACTIVE. Used in conjuction with MODE field to define if a memory region maps to BIF or FBC/FBDC access. If active then this region base address is used to check if an access is for the.." "0,1" newline bitfld.long 0xFC 12. "SLC_NOLINEFILL,SLC cache no line fill Policy: 0= line fill on miss 1=no line fill on miss" "line fill on miss,no line fill on miss" newline bitfld.long 0xFC 10.--11. "SLC_POLICY,SLC cache Policy: 00=Bypass 01=Write Back 10 =Write Through 11=Cached Read" "Bypass,Write Back,?,?" newline bitfld.long 0xFC 9. "TLCACHE_POLICY,Tile cache Policy: 1=no line fill on miss 0=line fill on miss" "line fill on miss,no line fill on miss" newline bitfld.long 0xFC 8. "COR_COLOUR_ENABLE,Correlation Colour Enable 0=off 1=on" "off,on" newline bitfld.long 0xFC 7. "IADDR,Direct/Indirect Addressing: 1=indirect 0=direct" "direct,indirect" newline hexmask.long.byte 0xFC 0.--6. 1. "DIMY,Surface height in terms of TILE_TYPE for this memory region" line.long 0x100 "RGX_CR_FB_MEM_REGION_CTRL14_0,Framebuffer Compression/Decompression memory regions for Host and TLA accesses" hexmask.long.byte 0x100 25.--31. 1. "DIMY,Surface height in terms of TILE_TYPE for this memory region" newline hexmask.long.word 0x100 12.--24. 1. "DIMX,Surface width in terms of TILE_TYPE for this memory region" newline bitfld.long 0x100 11. "MEML,Surface Memory layout for this memory region 0=linear 1=twiddled" "linear,twiddled" newline bitfld.long 0x100 9.--10. "DM,Data master to be used for this memory region 00 = TA/Vertex 01 = 3D/Pixel 10 = Compute 11 = Data Master of Requester If the memory region is being accessed by the TLA the data master is set to the TLA data master If the memory region is being.." "TA/Vertex,?,?,?" newline bitfld.long 0x100 8. "TILE_TYPE,Compressor tile type 0 = 8x8 pixels 1 = 16x4 pixels" "0,1" newline hexmask.long.byte 0x100 1.--7. 1. "FMT,The pixel format to be used in this memory region" newline bitfld.long 0x100 0. "MODE,Defines if this memory region maps to BIF or FBC/FBDC access; 0 = BIF 1 = FBC/FBDC" "BIF,FBC/FBDC" line.long 0x104 "RGX_CR_FB_MEM_REGION_CTRL14_1,Framebuffer Compression/Decompression memory regions for Host and TLA accesses" hexmask.long.tbyte 0x104 15.--31. 1. "Reserved_47,Reserved_47" newline bitfld.long 0x104 14. "PORT,Defines if this memory region is to be used by the TLA or Host port. 0 = TLA Port 1 = Host Port" "TLA Port,Host Port" newline bitfld.long 0x104 13. "ACTIVE,Defines if this memory region is active or not default to INACTIVE. Used in conjuction with MODE field to define if a memory region maps to BIF or FBC/FBDC access. If active then this region base address is used to check if an access is for the.." "0,1" newline bitfld.long 0x104 12. "SLC_NOLINEFILL,SLC cache no line fill Policy: 0= line fill on miss 1=no line fill on miss" "line fill on miss,no line fill on miss" newline bitfld.long 0x104 10.--11. "SLC_POLICY,SLC cache Policy: 00=Bypass 01=Write Back 10 =Write Through 11=Cached Read" "Bypass,Write Back,?,?" newline bitfld.long 0x104 9. "TLCACHE_POLICY,Tile cache Policy: 1=no line fill on miss 0=line fill on miss" "line fill on miss,no line fill on miss" newline bitfld.long 0x104 8. "COR_COLOUR_ENABLE,Correlation Colour Enable 0=off 1=on" "off,on" newline bitfld.long 0x104 7. "IADDR,Direct/Indirect Addressing: 1=indirect 0=direct" "direct,indirect" newline hexmask.long.byte 0x104 0.--6. 1. "DIMY,Surface height in terms of TILE_TYPE for this memory region" line.long 0x108 "RGX_CR_FB_MEM_REGION_CTRL15_0,Framebuffer Compression/Decompression memory regions for Host and TLA accesses" hexmask.long.byte 0x108 25.--31. 1. "DIMY,Surface height in terms of TILE_TYPE for this memory region" newline hexmask.long.word 0x108 12.--24. 1. "DIMX,Surface width in terms of TILE_TYPE for this memory region" newline bitfld.long 0x108 11. "MEML,Surface Memory layout for this memory region 0=linear 1=twiddled" "linear,twiddled" newline bitfld.long 0x108 9.--10. "DM,Data master to be used for this memory region 00 = TA/Vertex 01 = 3D/Pixel 10 = Compute 11 = Data Master of Requester If the memory region is being accessed by the TLA the data master is set to the TLA data master If the memory region is being.." "TA/Vertex,?,?,?" newline bitfld.long 0x108 8. "TILE_TYPE,Compressor tile type 0 = 8x8 pixels 1 = 16x4 pixels" "0,1" newline hexmask.long.byte 0x108 1.--7. 1. "FMT,The pixel format to be used in this memory region" newline bitfld.long 0x108 0. "MODE,Defines if this memory region maps to BIF or FBC/FBDC access; 0 = BIF 1 = FBC/FBDC" "BIF,FBC/FBDC" line.long 0x10C "RGX_CR_FB_MEM_REGION_CTRL15_1,Framebuffer Compression/Decompression memory regions for Host and TLA accesses" hexmask.long.tbyte 0x10C 15.--31. 1. "Reserved_47,Reserved_47" newline bitfld.long 0x10C 14. "PORT,Defines if this memory region is to be used by the TLA or Host port. 0 = TLA Port 1 = Host Port" "TLA Port,Host Port" newline bitfld.long 0x10C 13. "ACTIVE,Defines if this memory region is active or not default to INACTIVE. Used in conjuction with MODE field to define if a memory region maps to BIF or FBC/FBDC access. If active then this region base address is used to check if an access is for the.." "0,1" newline bitfld.long 0x10C 12. "SLC_NOLINEFILL,SLC cache no line fill Policy: 0= line fill on miss 1=no line fill on miss" "line fill on miss,no line fill on miss" newline bitfld.long 0x10C 10.--11. "SLC_POLICY,SLC cache Policy: 00=Bypass 01=Write Back 10 =Write Through 11=Cached Read" "Bypass,Write Back,?,?" newline bitfld.long 0x10C 9. "TLCACHE_POLICY,Tile cache Policy: 1=no line fill on miss 0=line fill on miss" "line fill on miss,no line fill on miss" newline bitfld.long 0x10C 8. "COR_COLOUR_ENABLE,Correlation Colour Enable 0=off 1=on" "off,on" newline bitfld.long 0x10C 7. "IADDR,Direct/Indirect Addressing: 1=indirect 0=direct" "direct,indirect" newline hexmask.long.byte 0x10C 0.--6. 1. "DIMY,Surface height in terms of TILE_TYPE for this memory region" line.long 0x110 "RGX_CR_FB_CDC_ZLS_0,Framebuffer Compression/Decompression configuration register for ZLS access" hexmask.long.byte 0x110 27.--31. 1. "Reserved_27,Reserved_27" newline hexmask.long.tbyte 0x110 4.--26. 1. "FBC_NUM_TILES,FBC ZLS number of compressor tiles in surface in granularity of 8x8x32dwords" newline bitfld.long 0x110 2.--3. "Reserved_2,Reserved_2" "0,1,2,3" newline bitfld.long 0x110 1. "FBC_IADDR,FBC Addressing mode 0 = direct ; 1 = indirect" "direct ;,indirect" newline bitfld.long 0x110 0. "FBDC_IADDR,FBDC Addressing mode 0 = direct ; 1 = indirect" "direct ;,indirect" line.long 0x114 "RGX_CR_FB_CDC_ZLS_1,Framebuffer Compression/Decompression configuration register for ZLS access" hexmask.long 0x114 0.--31. 1. "Reserved_27,Reserved_27" line.long 0x118 "RGX_CR_FB_0,Rascal Arbiter for FBC/FBDC arbiter modes" hexmask.long 0x118 2.--31. 1. "Reserved_2,Reserved_2" newline bitfld.long 0x118 1. "ZLSMCU_ARB_MODE,ZLS and MCU TLDecode Arbiter Mode Re-arbitrate after burst complete 0 = After each request 1 = valid dropped" "After each request,valid dropped" newline bitfld.long 0x118 0. "ZLSPBE_ARB_MODE,ZLS and PBE FBC Arbiter Mode Re-arbitrate after burst complete and 0 = After each request 1 = valid dropped" "After each request,valid dropped" line.long 0x11C "RGX_CR_FB_1,Rascal Arbiter for FBC/FBDC arbiter modes" hexmask.long 0x11C 0.--31. 1. "Reserved_2,Reserved_2" wgroup.long 0x1720++0x7 line.long 0x0 "RGX_CR_MCU_GLB_CFI_0,Global flush and invalidation control for all Texture and Data Cache. Will flush then invalidate cache if both bit 0 & bit 1 set." hexmask.long.tbyte 0x0 10.--31. 1. "Reserved_10,Reserved_10" newline bitfld.long 0x0 9. "DM_FASTRENDER,When set perform operation on fastrender data master" "0,1" newline bitfld.long 0x0 6.--8. "Reserved_6,Reserved_6" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 5. "FENCE,When set additionally perform a fence to external memory before signalling that a flush is complete" "0,1" newline bitfld.long 0x0 4. "DM_COMPUTE,When set perform operation on compute data master" "0,1" newline bitfld.long 0x0 3. "DM_PIXEL,When set perform operation on pixel data master" "0,1" newline bitfld.long 0x0 2. "DM_VERTEX,When set perform operation on vertex data master" "0,1" newline bitfld.long 0x0 1. "FLUSH,When set will flush cache based on data master" "0,1" newline bitfld.long 0x0 0. "INVALIDATE,When set will invalidate cache based on data master. This bit will also invalidate the L0 cache in the MADD and teh YUV cache in the TAG to reset the CSC coefficients." "0,1" line.long 0x4 "RGX_CR_MCU_GLB_CFI_1,Global flush and invalidation control for all Texture and Data Cache. Will flush then invalidate cache if both bit 0 & bit 1 set." hexmask.long 0x4 0.--31. 1. "Reserved_10,Reserved_10" rgroup.long 0x1728++0x7 line.long 0x0 "RGX_CR_MCU_GLB_CFI_EVENT_0,Global flush and invalidation event for all Texture and Data Cache." hexmask.long 0x0 1.--31. 1. "Reserved_1,Reserved_1" newline bitfld.long 0x0 0. "PENDING,1 Indicate there is a pending global CFI operation on the MCU" "0,1" line.long 0x4 "RGX_CR_MCU_GLB_CFI_EVENT_1,Global flush and invalidation event for all Texture and Data Cache." hexmask.long 0x4 0.--31. 1. "Reserved_1,Reserved_1" group.long 0x1730++0x17 line.long 0x0 "RGX_CR_MCU_LIMIT_0,Define the maximum number of cache lines allowed to be allocated to each Data Master within the SLC. Note that values are specified per group with a value of 0x0 denoting no limit. Also note that the specified values operate as soft.." hexmask.long.byte 0x0 24.--31. 1. "Reserved_24,Reserved_24" newline hexmask.long.byte 0x0 16.--23. 1. "DM_COMPUTE,Maximum number of cachelines which can be used by the Compute data master" newline hexmask.long.byte 0x0 8.--15. 1. "DM_PIXEL,Maximum number of cachelines which can be used by the Pixel data master" newline hexmask.long.byte 0x0 0.--7. 1. "DM_VERTEX,Maximum number of cachelines which can be used by the Vertex data master" line.long 0x4 "RGX_CR_MCU_LIMIT_1,Define the maximum number of cache lines allowed to be allocated to each Data Master within the SLC. Note that values are specified per group with a value of 0x0 denoting no limit. Also note that the specified values operate as soft.." hexmask.long 0x4 0.--31. 1. "Reserved_24,Reserved_24" line.long 0x8 "RGX_CR_MCU_CTRL_0,MCU control registers" hexmask.long.word 0x8 18.--31. 1. "Reserved_18,Reserved_18" newline bitfld.long 0x8 17. "PDSRW_L0_OFF,Turn off MCU PDSRW L0 cache" "0,1" newline hexmask.long.byte 0x8 9.--16. 1. "FBDC_REQ_THRESHOLD,Maximum number of outstanding requests each MCU group can have to the Framebuffer Decompression module" newline bitfld.long 0x8 8. "RD_OVERTAKE_THRESH_ENABLE,Enables the use of the threshold to limit the amount of overtaking which is permitted" "0,1" newline hexmask.long.byte 0x8 2.--7. 1. "RD_OVERTAKE_THRESHOLD,The number of read accesses which are permitted to overtake waiting Writebacks when enabled" newline bitfld.long 0x8 1. "INSTANCE_MERGE_DISABLE,Turn off instance merging in the MCU L1" "0,1" newline bitfld.long 0x8 0. "L1_OFF,Turn off MCU L1" "0,1" line.long 0xC "RGX_CR_MCU_CTRL_1,MCU control registers" hexmask.long 0xC 0.--31. 1. "Reserved_18,Reserved_18" line.long 0x10 "RGX_CR_MCU_FENCE_0,Defines the Data Master and Addresses used when the MCU optionally issues a Fence as part of a Flush operation. See MCU_GLB_CFI register for details." hexmask.long 0x10 5.--31. 1. "ADDR,Address value to use when issuing a Fence" newline hexmask.long.byte 0x10 0.--4. 1. "Reserved_0,Reserved_0" line.long 0x14 "RGX_CR_MCU_FENCE_1,Defines the Data Master and Addresses used when the MCU optionally issues a Fence as part of a Flush operation. See MCU_GLB_CFI register for details." hexmask.long.tbyte 0x14 11.--31. 1. "Reserved_43,Reserved_43" newline bitfld.long 0x14 8.--10. "DM,Data Master value to use when issuing a Fence" "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x14 0.--7. 1. "ADDR,Address value to use when issuing a Fence" group.long 0x1780++0x17 line.long 0x0 "RGX_CR_TPU_0,Global control to TPU_MCU_L0|tpu" hexmask.long.tbyte 0x0 9.--31. 1. "Reserved_9,Reserved_9" newline bitfld.long 0x0 8. "MCU_PDS_L0_OFF,Turn off MCU PDSL0 cache" "0,1" newline bitfld.long 0x0 7. "Reserved_7,Reserved_7" "0,1" newline bitfld.long 0x0 6. "TAG_ENABLE_MMU_PREFETCH,Enables generation of prefetch requests to the MMU" "0,1" newline bitfld.long 0x0 5. "TAG_CEM_4K_FACE_PACKING,Pixel data master. Enable 4K-byte alignment between CEM faces when set to 1. It applies for both when mipmap is enabled or disabled" "0,1" newline bitfld.long 0x0 4. "MADD_CONFIG_L0OFF,When set this disables MADD P0 L0 cache" "0,1" newline bitfld.long 0x0 3. "TAG_CEM_FACE_PACKING,Pixel data master. Enable dword alignment between CEM faces when set to 1" "0,1" newline bitfld.long 0x0 2. "TAG_CEMEDGE_DONTFILTER,Pixel data master. Disable filtering over edges/corners for CEM. When set to 1 HW will be seemfull ie always stay in the current map always honour the addressmode. When set to 0 HW will be seemless ie ignore addressmode.." "0,1" newline bitfld.long 0x0 1. "TAG_CEMGRAD_DONTNEGATE,Pixel data master. Disable negation for user supplied gradients for cem swap i. e. will only swap dudx etc not negate" "0,1" newline bitfld.long 0x0 0. "MADD_CONFIG_DXT35_TRANSOVR,When set this disables alternative mode implied by colour0 > colour1 for DXT3 to DXT5" "colour1 for DXT3 to DXT5,?" line.long 0x4 "RGX_CR_TPU_1,Global control to TPU_MCU_L0|tpu" hexmask.long 0x4 0.--31. 1. "Reserved_9,Reserved_9" line.long 0x8 "RGX_CR_TPU_YUV_CSC_COEFFICIENTS_0,Base address for the YUV CSC set of coefficients stored in memory for pixel data master" hexmask.long 0x8 0.--31. 1. "YUV_CSC_COEFFICIENTS_ADDRESS,Base address DWORD aligned for the location in memory of the CSC coefficients" line.long 0xC "RGX_CR_TPU_YUV_CSC_COEFFICIENTS_1,Base address for the YUV CSC set of coefficients stored in memory for pixel data master" hexmask.long 0xC 6.--31. 1. "Reserved_38,Reserved_38" newline hexmask.long.byte 0xC 0.--5. 1. "YUV_CSC_COEFFICIENTS_ADDRESS,Base address DWORD aligned for the location in memory of the CSC coefficients" line.long 0x10 "RGX_CR_TPU_BORDER_COLOUR_TABLE_PDM_0,Base address for the border colour table" hexmask.long 0x10 0.--31. 1. "BORDER_COLOUR_TABLE_ADDRESS,Base address DWORD aligned for the location in memory of the border colour table for the PDM" line.long 0x14 "RGX_CR_TPU_BORDER_COLOUR_TABLE_PDM_1,Base address for the border colour table" hexmask.long 0x14 6.--31. 1. "Reserved_38,Reserved_38" newline hexmask.long.byte 0x14 0.--5. 1. "BORDER_COLOUR_TABLE_ADDRESS,Base address DWORD aligned for the location in memory of the border colour table for the PDM" rgroup.long 0x1798++0x7 line.long 0x0 "RGX_CR_DUST_IDLE_0,RGX_CR_DUST_IDLE_0" hexmask.long 0x0 7.--31. 1. "Reserved_7,Reserved_7" newline bitfld.long 0x0 6. "MCU_L0_WRAP,MCU L0 WRAP Module IDLE" "0,1" newline bitfld.long 0x0 5. "MCU_L0,MCU L0 Module IDLE" "0,1" newline bitfld.long 0x0 4. "TF,TF Module IDLE" "0,1" newline bitfld.long 0x0 3. "MADD,MADD Module IDLE" "0,1" newline bitfld.long 0x0 2. "TAG,TAG Module IDLE" "0,1" newline bitfld.long 0x0 1. "USC1,USC1 Module IDLE" "0,1" newline bitfld.long 0x0 0. "USC0,USC0 Module IDLE" "0,1" line.long 0x4 "RGX_CR_DUST_IDLE_1,RGX_CR_DUST_IDLE_1" hexmask.long 0x4 0.--31. 1. "Reserved_7,Reserved_7" group.long 0x17A0++0xF line.long 0x0 "RGX_CR_TPU_BORDER_COLOUR_TABLE_VDM_0,Base address for the border colour table" hexmask.long 0x0 0.--31. 1. "BORDER_COLOUR_TABLE_ADDRESS,Base address DWORD aligned for the location in memory of the border colour table for the VDM" line.long 0x4 "RGX_CR_TPU_BORDER_COLOUR_TABLE_VDM_1,Base address for the border colour table" hexmask.long 0x4 6.--31. 1. "Reserved_38,Reserved_38" newline hexmask.long.byte 0x4 0.--5. 1. "BORDER_COLOUR_TABLE_ADDRESS,Base address DWORD aligned for the location in memory of the border colour table for the VDM" line.long 0x8 "RGX_CR_TPU_BORDER_COLOUR_TABLE_CDM_0,Base address for the border colour table" hexmask.long 0x8 0.--31. 1. "BORDER_COLOUR_TABLE_ADDRESS,Base address DWORD aligned for the location in memory of the border colour table for the CDM" line.long 0xC "RGX_CR_TPU_BORDER_COLOUR_TABLE_CDM_1,Base address for the border colour table" hexmask.long 0xC 6.--31. 1. "Reserved_38,Reserved_38" newline hexmask.long.byte 0xC 0.--5. 1. "BORDER_COLOUR_TABLE_ADDRESS,Base address DWORD aligned for the location in memory of the border colour table for the CDM" repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) rgroup.long ($2+0x17B0)++0x3 line.long 0x0 "RGX_CR_TPU_PWR_NUMBER_OF_TEXELS_$1,Peformance counter associated with Power Monitoring." hexmask.long 0x0 0.--31. 1. "VALUE,Number of texels requested per clock" repeat.end group.long 0x17B8++0xF line.long 0x0 "RGX_CR_TPU_TAG_CTRL_0,Global control to TAG for the pixel data master" hexmask.long 0x0 4.--31. 1. "Reserved_4,Reserved_4" newline bitfld.long 0x0 3. "AF_RATIO_TRUNCATE_TO_INTEGER,0 current mode 1 clear the fractional part of the calculated AF ratio" "0,1" newline bitfld.long 0x0 2. "AF_RATIO_TRUNCATE_TO_HALF,0 current mode 1 truncate the fractional part of the calculated AF ratio to 0. 5" "0,1" newline bitfld.long 0x0 1. "AF_FILTERING_MODE,0 current mode 1 new mode." "0,1" newline bitfld.long 0x0 0. "YUV_CAM_INVALIDATE,When set will invalidate YUV CSC CAM to reset the CSC coefficients. It should be set when the TPU is not performing CSC." "0,1" line.long 0x4 "RGX_CR_TPU_TAG_CTRL_1,Global control to TAG for the pixel data master" hexmask.long 0x4 0.--31. 1. "Reserved_4,Reserved_4" line.long 0x8 "RGX_CR_TPU_MADD_CTRL_0,Global control to MADD for pixel data master" hexmask.long 0x8 2.--31. 1. "Reserved_2,Reserved_2" newline bitfld.long 0x8 1. "ASTC_ODD_SCALING_ENABLE,When set ASTC encoded texels use the odd U16->F16 scaling in the TF. When zero the usual scaling will be used in TF." "0,1" newline bitfld.long 0x8 0. "ASTC_MULTICYCLE_TF_FORCE_F16,When set ASTC encoded texels that are filtered over multiple cycles by the TF will be output from the MADD as F16." "0,1" line.long 0xC "RGX_CR_TPU_MADD_CTRL_1,Global control to MADD for pixel data master" hexmask.long 0xC 0.--31. 1. "Reserved_2,Reserved_2" group.long 0x17F0++0x7 line.long 0x0 "RGX_CR_TPU_BORDER_COLOUR_TABLE_TDM_0,Base address for the border colour table" hexmask.long 0x0 0.--31. 1. "BORDER_COLOUR_TABLE_ADDRESS,Base address DWORD aligned for the location in memory of the border colour table for the TDM" line.long 0x4 "RGX_CR_TPU_BORDER_COLOUR_TABLE_TDM_1,Base address for the border colour table" hexmask.long 0x4 6.--31. 1. "Reserved_38,Reserved_38" newline hexmask.long.byte 0x4 0.--5. 1. "BORDER_COLOUR_TABLE_ADDRESS,Base address DWORD aligned for the location in memory of the border colour table for the TDM" group.long 0x18C0++0x17 line.long 0x0 "RGX_CR_TPU_LODBIASREP_CMP_MANTISSA_MASK_PDM_0,Mask for comparing mantissa of f32 LOD Bias/Replace value for PPLOD speedup for the pixel data master" hexmask.long.word 0x0 23.--31. 1. "Reserved_23,Reserved_23" newline hexmask.long.tbyte 0x0 0.--22. 1. "LODBIASREP_CMP_MANTISSA_MASK,Mask for comparing mantissa of f32 LOD Bias/Replace value for PPLOD speedup" line.long 0x4 "RGX_CR_TPU_LODBIASREP_CMP_MANTISSA_MASK_PDM_1,Mask for comparing mantissa of f32 LOD Bias/Replace value for PPLOD speedup for the pixel data master" hexmask.long 0x4 0.--31. 1. "Reserved_23,Reserved_23" line.long 0x8 "RGX_CR_TPU_LODBIASREP_CMP_MANTISSA_MASK_VDM_0,Mask for comparing mantissa of f32 LOD Bias/Replace value for PPLOD speedup for the vertex data master" hexmask.long.word 0x8 23.--31. 1. "Reserved_23,Reserved_23" newline hexmask.long.tbyte 0x8 0.--22. 1. "LODBIASREP_CMP_MANTISSA_MASK,Mask for comparing mantissa of f32 LOD Bias/Replace value for PPLOD speedup" line.long 0xC "RGX_CR_TPU_LODBIASREP_CMP_MANTISSA_MASK_VDM_1,Mask for comparing mantissa of f32 LOD Bias/Replace value for PPLOD speedup for the vertex data master" hexmask.long 0xC 0.--31. 1. "Reserved_23,Reserved_23" line.long 0x10 "RGX_CR_TPU_LODBIASREP_CMP_MANTISSA_MASK_CDM_0,Mask for comparing mantissa of f32 LOD Bias/Replace value for PPLOD speedup for the compute data master" hexmask.long.word 0x10 23.--31. 1. "Reserved_23,Reserved_23" newline hexmask.long.tbyte 0x10 0.--22. 1. "LODBIASREP_CMP_MANTISSA_MASK,Mask for comparing mantissa of f32 LOD Bias/Replace value for PPLOD speedup" line.long 0x14 "RGX_CR_TPU_LODBIASREP_CMP_MANTISSA_MASK_CDM_1,Mask for comparing mantissa of f32 LOD Bias/Replace value for PPLOD speedup for the compute data master" hexmask.long 0x14 0.--31. 1. "Reserved_23,Reserved_23" group.long 0x18E0++0x7 line.long 0x0 "RGX_CR_TPU_LODBIASREP_CMP_MANTISSA_MASK_TDM_0,Mask for comparing mantissa of f32 LOD Bias/Replace value for PPLOD speedup for the fast render data master" hexmask.long.word 0x0 23.--31. 1. "Reserved_23,Reserved_23" newline hexmask.long.tbyte 0x0 0.--22. 1. "LODBIASREP_CMP_MANTISSA_MASK,Mask for comparing mantissa of f32 LOD Bias/Replace value for PPLOD speedup" line.long 0x4 "RGX_CR_TPU_LODBIASREP_CMP_MANTISSA_MASK_TDM_1,Mask for comparing mantissa of f32 LOD Bias/Replace value for PPLOD speedup for the fast render data master" hexmask.long 0x4 0.--31. 1. "Reserved_23,Reserved_23" rgroup.long 0x2000++0xF line.long 0x0 "RGX_CR_PM_TA_MMUPAGE_STATUS_0,RGX_CR_PM_TA_MMUPAGE_STATUS_0" hexmask.long.word 0x0 22.--31. 1. "Reserved_22,Reserved_22" newline hexmask.long.tbyte 0x0 0.--21. 1. "OP,MMU pages(4KB) counter @ the TA context" line.long 0x4 "RGX_CR_PM_TA_MMUPAGE_STATUS_1,RGX_CR_PM_TA_MMUPAGE_STATUS_1" hexmask.long 0x4 0.--31. 1. "Reserved_22,Reserved_22" line.long 0x8 "RGX_CR_PM_3D_MMUPAGE_STATUS_0,RGX_CR_PM_3D_MMUPAGE_STATUS_0" hexmask.long.word 0x8 22.--31. 1. "Reserved_22,Reserved_22" newline hexmask.long.tbyte 0x8 0.--21. 1. "OP,MMU pages(4KB) counter @ the 3D context" line.long 0xC "RGX_CR_PM_3D_MMUPAGE_STATUS_1,RGX_CR_PM_3D_MMUPAGE_STATUS_1" hexmask.long 0xC 0.--31. 1. "Reserved_22,Reserved_22" group.long 0x2010++0xF line.long 0x0 "RGX_CR_PM_MMU_STACK_POLICY_0,This register enables the PM to drain pages for MMU from the dedicated mmu free list stack. (no-pagable) It is static register which can not be changed in the run-time." hexmask.long 0x0 1.--31. 1. "Reserved_1,Reserved_1" newline bitfld.long 0x0 0. "OP,when this bit is '1' PM will try to drain pages from the dedicated mmu free list stack" "0,1" line.long 0x4 "RGX_CR_PM_MMU_STACK_POLICY_1,This register enables the PM to drain pages for MMU from the dedicated mmu free list stack. (no-pagable) It is static register which can not be changed in the run-time." hexmask.long 0x4 0.--31. 1. "Reserved_1,Reserved_1" line.long 0x8 "RGX_CR_PM_TA_MMU_FSTACK_BASE_0,Effective on loading of the MMU TA free list loading . this register defines the base address of the mmu free list stack being referenced during TA processing." hexmask.long 0x8 4.--31. 1. "ADDR,1TB Addressable 128 bits aligned Base Address for MMU TA free list stack" newline hexmask.long.byte 0x8 0.--3. 1. "Reserved_0,Reserved_0" line.long 0xC "RGX_CR_PM_TA_MMU_FSTACK_BASE_1,Effective on loading of the MMU TA free list loading . this register defines the base address of the mmu free list stack being referenced during TA processing." hexmask.long.tbyte 0xC 8.--31. 1. "Reserved_40,Reserved_40" newline hexmask.long.byte 0xC 0.--7. 1. "ADDR,1TB Addressable 128 bits aligned Base Address for MMU TA free list stack" rgroup.long 0x2020++0x7 line.long 0x0 "RGX_CR_PM_TA_MMU_FSTACK_STATUS_0,Note: this is the pointer pointing to the MMU TA free stack top. (4KB page pointer)" hexmask.long.word 0x0 22.--31. 1. "Reserved_22,Reserved_22" newline hexmask.long.tbyte 0x0 0.--21. 1. "TOP,This status register indicated the mmu ta context free list pointer status." line.long 0x4 "RGX_CR_PM_TA_MMU_FSTACK_STATUS_1,Note: this is the pointer pointing to the MMU TA free stack top. (4KB page pointer)" hexmask.long 0x4 0.--31. 1. "Reserved_22,Reserved_22" group.long 0x2028++0x1F line.long 0x0 "RGX_CR_PM_TA_MMU_FSTACK_0,Defines the start of the stack pointer regarding to the MMU free list stack" hexmask.long.word 0x0 22.--31. 1. "Reserved_22,Reserved_22" newline hexmask.long.tbyte 0x0 0.--21. 1. "STARTOF_TOP,This register defines the head pointer of the mmu free list in terms of 4K free pages in the free list stack effective on a loading of the MMU TA free list" line.long 0x4 "RGX_CR_PM_TA_MMU_FSTACK_1,Defines the start of the stack pointer regarding to the MMU free list stack" hexmask.long 0x4 0.--31. 1. "Reserved_22,Reserved_22" line.long 0x8 "RGX_CR_PM_START_OF_MMU_TACONTEXT_0,RGX_CR_PM_START_OF_MMU_TACONTEXT_0" hexmask.long.word 0x8 22.--31. 1. "Reserved_22,Reserved_22" newline hexmask.long.tbyte 0x8 0.--21. 1. "ALLOCATED_MMUPAGE,Start of MMU Freelists TA pages(4KB) on loading of the MMU TA context" line.long 0xC "RGX_CR_PM_START_OF_MMU_TACONTEXT_1,RGX_CR_PM_START_OF_MMU_TACONTEXT_1" hexmask.long 0xC 0.--31. 1. "Reserved_22,Reserved_22" line.long 0x10 "RGX_CR_PM_TASK_TA_MMU_FSTACK_FREE_LOAD_0,RGX_CR_PM_TASK_TA_MMU_FSTACK_FREE_LOAD_0" hexmask.long 0x10 1.--31. 1. "Reserved_1,Reserved_1" newline bitfld.long 0x10 0. "PENDING,A write into this register will cause the TA MMU free list context to be loaded from the relevant configuration registers" "0,1" line.long 0x14 "RGX_CR_PM_TASK_TA_MMU_FSTACK_FREE_LOAD_1,RGX_CR_PM_TASK_TA_MMU_FSTACK_FREE_LOAD_1" hexmask.long 0x14 0.--31. 1. "Reserved_1,Reserved_1" line.long 0x18 "RGX_CR_PM_3D_MMU_FSTACK_BASE_0,Effective on loading of the MMU 3D free list loading . this register defines the base address of the mmu free list stack being referenced during 3D processing." hexmask.long 0x18 4.--31. 1. "ADDR,1TB Addressable 128 bits aligned Base Address for MMU TA free list stack" newline hexmask.long.byte 0x18 0.--3. 1. "Reserved_0,Reserved_0" line.long 0x1C "RGX_CR_PM_3D_MMU_FSTACK_BASE_1,Effective on loading of the MMU 3D free list loading . this register defines the base address of the mmu free list stack being referenced during 3D processing." hexmask.long.tbyte 0x1C 8.--31. 1. "Reserved_40,Reserved_40" newline hexmask.long.byte 0x1C 0.--7. 1. "ADDR,1TB Addressable 128 bits aligned Base Address for MMU TA free list stack" rgroup.long 0x2048++0x7 line.long 0x0 "RGX_CR_PM_3D_MMU_FSTACK_STATUS_0,Note: this is the pointer pointing to the MMU TA free stack top. (4KB page pointer)" hexmask.long.word 0x0 22.--31. 1. "Reserved_22,Reserved_22" newline hexmask.long.tbyte 0x0 0.--21. 1. "TOP,This status register indicated the mmu ta context free list pointer status." line.long 0x4 "RGX_CR_PM_3D_MMU_FSTACK_STATUS_1,Note: this is the pointer pointing to the MMU TA free stack top. (4KB page pointer)" hexmask.long 0x4 0.--31. 1. "Reserved_22,Reserved_22" group.long 0x2050++0x17 line.long 0x0 "RGX_CR_PM_3D_MMU_FSTACK_0,Defines the start of the stack pointer regarding to the MMU free list stack Effective on a 3D MMU fstack load" hexmask.long.word 0x0 22.--31. 1. "Reserved_22,Reserved_22" newline hexmask.long.tbyte 0x0 0.--21. 1. "STARTOF_TOP,This register defines the head pointer of the mmu free list in terms of 4K free pages in the free list stack effective on a loading of the MMU TA free list" line.long 0x4 "RGX_CR_PM_3D_MMU_FSTACK_1,Defines the start of the stack pointer regarding to the MMU free list stack Effective on a 3D MMU fstack load" hexmask.long 0x4 0.--31. 1. "Reserved_22,Reserved_22" line.long 0x8 "RGX_CR_PM_START_OF_MMU_3DCONTEXT_0,Effective on a 3D MMU fstack load" hexmask.long.word 0x8 22.--31. 1. "Reserved_22,Reserved_22" newline hexmask.long.tbyte 0x8 0.--21. 1. "ALLOCATED_MMUPAGE,Start of MMU Freelists 3D pages(4KB) on loading of the MMU TA context" line.long 0xC "RGX_CR_PM_START_OF_MMU_3DCONTEXT_1,Effective on a 3D MMU fstack load" hexmask.long 0xC 0.--31. 1. "Reserved_22,Reserved_22" line.long 0x10 "RGX_CR_PM_TASK_3D_MMU_FSTACK_FREE_LOAD_0,RGX_CR_PM_TASK_3D_MMU_FSTACK_FREE_LOAD_0" hexmask.long 0x10 1.--31. 1. "Reserved_1,Reserved_1" newline bitfld.long 0x10 0. "PENDING,A write into this register will cause the 3D MMU free list context to be loaded from the relevant configuration registers" "0,1" line.long 0x14 "RGX_CR_PM_TASK_3D_MMU_FSTACK_FREE_LOAD_1,RGX_CR_PM_TASK_3D_MMU_FSTACK_FREE_LOAD_1" hexmask.long 0x14 0.--31. 1. "Reserved_1,Reserved_1" rgroup.long 0x2068++0xF line.long 0x0 "RGX_CR_PM_MMUSTACK_LOCK_STATUS_0,RGX_CR_PM_MMUSTACK_LOCK_STATUS_0" hexmask.long 0x0 2.--31. 1. "Reserved_2,Reserved_2" newline bitfld.long 0x0 1. "TD,Bit 1: 3D MMU free list Lock Status. 0 idle/ 1 used" "0,1" newline bitfld.long 0x0 0. "TA,Bit 0: TA MMU free list Lock Status. 0 idle/ 1 used." "TA MMU free list Lock Status,?" line.long 0x4 "RGX_CR_PM_MMUSTACK_LOCK_STATUS_1,RGX_CR_PM_MMUSTACK_LOCK_STATUS_1" hexmask.long 0x4 0.--31. 1. "Reserved_2,Reserved_2" line.long 0x8 "RGX_CR_PM_MMUSTACK_LOCK_OWNER_0,RGX_CR_PM_MMUSTACK_LOCK_OWNER_0" hexmask.long 0x8 2.--31. 1. "Reserved_2,Reserved_2" newline bitfld.long 0x8 1. "TD,Bit 1 :3D free list Lock owner. 0 PMA / 1 PMD" "0,1" newline bitfld.long 0x8 0. "TA,Bit 0: TA free list Lock Owner. 0 PMA / 1 PMD." "TA free list Lock Owner,?" line.long 0xC "RGX_CR_PM_MMUSTACK_LOCK_OWNER_1,RGX_CR_PM_MMUSTACK_LOCK_OWNER_1" hexmask.long 0xC 0.--31. 1. "Reserved_2,Reserved_2" group.long 0x2078++0xF line.long 0x0 "RGX_CR_PM_3D_UFSTACK_BASE_0,Effective on load of the Unified Free List Stack. this register defines the base address of the unified free list stack being referenced." hexmask.long 0x0 4.--31. 1. "ADDR,1TB Addressable 128 bits aligned Base Address for unified free list stack base address" newline hexmask.long.byte 0x0 0.--3. 1. "Reserved_0,Reserved_0" line.long 0x4 "RGX_CR_PM_3D_UFSTACK_BASE_1,Effective on load of the Unified Free List Stack. this register defines the base address of the unified free list stack being referenced." hexmask.long.tbyte 0x4 8.--31. 1. "Reserved_40,Reserved_40" newline hexmask.long.byte 0x4 0.--7. 1. "ADDR,1TB Addressable 128 bits aligned Base Address for unified free list stack base address" line.long 0x8 "RGX_CR_PM_3D_UFSTACK_0,Note: each 16GB 4KB addressable page (22 bits) is rounded to dword aligned Effective on load of the Unified Free List Stack." hexmask.long.word 0x8 22.--31. 1. "Reserved_22,Reserved_22" newline hexmask.long.tbyte 0x8 0.--21. 1. "STARTOF_TOP,This register defines the unified free list stack pointer @ loading time. It is 4K page." line.long 0xC "RGX_CR_PM_3D_UFSTACK_1,Note: each 16GB 4KB addressable page (22 bits) is rounded to dword aligned Effective on load of the Unified Free List Stack." hexmask.long 0xC 0.--31. 1. "Reserved_22,Reserved_22" rgroup.long 0x2088++0x7 line.long 0x0 "RGX_CR_PM_3D_UFSTACK_STATUS_0,Note: this is the pointer pointing to the ufstack top. (4KB page pointer)" hexmask.long.word 0x0 22.--31. 1. "Reserved_22,Reserved_22" newline hexmask.long.tbyte 0x0 0.--21. 1. "TOP,This status register indicated the unified free list stack pointer status." line.long 0x4 "RGX_CR_PM_3D_UFSTACK_STATUS_1,Note: this is the pointer pointing to the ufstack top. (4KB page pointer)" hexmask.long 0x4 0.--31. 1. "Reserved_22,Reserved_22" repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) group.long ($2+0x2090)++0x3 line.long 0x0 "RGX_CR_PM_START_OF_3D_UFSTACK_$1,Effective on load of the Unified Free List Stack." hexmask.long.word 0x0 22.--31. 1. "Reserved_22,Reserved_22" newline hexmask.long.tbyte 0x0 0.--21. 1. "ALLOCATED_PAGE,Start of TA pages(4KB) on loading of the Unified Free List Stack" repeat.end rgroup.long 0x2098++0xF line.long 0x0 "RGX_CR_PM_3D_UFSTACK_PAGE_STATUS_0,RGX_CR_PM_3D_UFSTACK_PAGE_STATUS_0" hexmask.long.word 0x0 22.--31. 1. "Reserved_22,Reserved_22" newline hexmask.long.tbyte 0x0 0.--21. 1. "OP,The number of Unified Free list pages currently allocated for the TA" line.long 0x4 "RGX_CR_PM_3D_UFSTACK_PAGE_STATUS_1,RGX_CR_PM_3D_UFSTACK_PAGE_STATUS_1" hexmask.long 0x4 0.--31. 1. "Reserved_22,Reserved_22" line.long 0x8 "RGX_CR_PM_3D_UFSTACK_MMUPAGE_STATUS_0,RGX_CR_PM_3D_UFSTACK_MMUPAGE_STATUS_0" hexmask.long.word 0x8 22.--31. 1. "Reserved_22,Reserved_22" newline hexmask.long.tbyte 0x8 0.--21. 1. "OP,The number of Unified Free list pages currently allocated for the MMU" line.long 0xC "RGX_CR_PM_3D_UFSTACK_MMUPAGE_STATUS_1,RGX_CR_PM_3D_UFSTACK_MMUPAGE_STATUS_1" hexmask.long 0xC 0.--31. 1. "Reserved_22,Reserved_22" group.long 0x20A8++0x1F line.long 0x0 "RGX_CR_PM_TASK_3D_UFSTACK_LOAD_0,RGX_CR_PM_TASK_3D_UFSTACK_LOAD_0" hexmask.long 0x0 1.--31. 1. "Reserved_1,Reserved_1" newline bitfld.long 0x0 0. "PENDING,pending status register corresponding to the ustack loading operation it will become '1' when this pm_task_ufstack_load being written and deassert until the operation is done" "0,1" line.long 0x4 "RGX_CR_PM_TASK_3D_UFSTACK_LOAD_1,RGX_CR_PM_TASK_3D_UFSTACK_LOAD_1" hexmask.long 0x4 0.--31. 1. "Reserved_1,Reserved_1" line.long 0x8 "RGX_CR_PM_TASK_TA_UFSTACK_LOAD_0,RGX_CR_PM_TASK_TA_UFSTACK_LOAD_0" hexmask.long 0x8 1.--31. 1. "Reserved_1,Reserved_1" newline bitfld.long 0x8 0. "PENDING,pending status register corresponding to the ustack loading operation it will become '1' when this pm_task_ufstack_load being written and deassert until the operation is done" "0,1" line.long 0xC "RGX_CR_PM_TASK_TA_UFSTACK_LOAD_1,RGX_CR_PM_TASK_TA_UFSTACK_LOAD_1" hexmask.long 0xC 0.--31. 1. "Reserved_1,Reserved_1" line.long 0x10 "RGX_CR_PM_TA_UFSTACK_BASE_0,Effective on load of the Unified Free List Stack. this register defines the base address of the unified free list stack being referenced." hexmask.long 0x10 4.--31. 1. "ADDR,1TB Addressable 128 bits aligned Base Address for unified free list stack base address" newline hexmask.long.byte 0x10 0.--3. 1. "Reserved_0,Reserved_0" line.long 0x14 "RGX_CR_PM_TA_UFSTACK_BASE_1,Effective on load of the Unified Free List Stack. this register defines the base address of the unified free list stack being referenced." hexmask.long.tbyte 0x14 8.--31. 1. "Reserved_40,Reserved_40" newline hexmask.long.byte 0x14 0.--7. 1. "ADDR,1TB Addressable 128 bits aligned Base Address for unified free list stack base address" line.long 0x18 "RGX_CR_PM_TA_UFSTACK_0,Note: each 16GB 4KB addressable page (22 bits) is rounded to dword aligned Effective on the loading of the Unified Free List Stack." hexmask.long.word 0x18 22.--31. 1. "Reserved_22,Reserved_22" newline hexmask.long.tbyte 0x18 0.--21. 1. "STARTOF_TOP,This register defines the unified free list stack pointer @ loading time. It is 4K page." line.long 0x1C "RGX_CR_PM_TA_UFSTACK_1,Note: each 16GB 4KB addressable page (22 bits) is rounded to dword aligned Effective on the loading of the Unified Free List Stack." hexmask.long 0x1C 0.--31. 1. "Reserved_22,Reserved_22" rgroup.long 0x20C8++0x7 line.long 0x0 "RGX_CR_PM_TA_UFSTACK_STATUS_0,Note: this is the pointer pointing to the ufstack top. (4KB page pointer)" hexmask.long.word 0x0 22.--31. 1. "Reserved_22,Reserved_22" newline hexmask.long.tbyte 0x0 0.--21. 1. "TOP,This status register indicated the unified free list stack pointer status." line.long 0x4 "RGX_CR_PM_TA_UFSTACK_STATUS_1,Note: this is the pointer pointing to the ufstack top. (4KB page pointer)" hexmask.long 0x4 0.--31. 1. "Reserved_22,Reserved_22" repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) group.long ($2+0x20D0)++0x3 line.long 0x0 "RGX_CR_PM_START_OF_TA_UFSTACK_$1,RGX_CR_PM_START_OF_TA_UFSTACK_0" hexmask.long.word 0x0 22.--31. 1. "Reserved_22,Reserved_22" newline hexmask.long.tbyte 0x0 0.--21. 1. "ALLOCATED_PAGE,Start of TA pages(4KB) on loading of the Unified Free List Stack" repeat.end rgroup.long 0x20D8++0x1F line.long 0x0 "RGX_CR_PM_TA_UFSTACK_PAGE_STATUS_0,RGX_CR_PM_TA_UFSTACK_PAGE_STATUS_0" hexmask.long.word 0x0 22.--31. 1. "Reserved_22,Reserved_22" newline hexmask.long.tbyte 0x0 0.--21. 1. "OP,The number of Unified Free list pages currently allocated for the TA" line.long 0x4 "RGX_CR_PM_TA_UFSTACK_PAGE_STATUS_1,RGX_CR_PM_TA_UFSTACK_PAGE_STATUS_1" hexmask.long 0x4 0.--31. 1. "Reserved_22,Reserved_22" line.long 0x8 "RGX_CR_PM_TA_UFSTACK_MMUPAGE_STATUS_0,RGX_CR_PM_TA_UFSTACK_MMUPAGE_STATUS_0" hexmask.long.word 0x8 22.--31. 1. "Reserved_22,Reserved_22" newline hexmask.long.tbyte 0x8 0.--21. 1. "OP,The number of Unified Free list pages currently allocated for the MMU" line.long 0xC "RGX_CR_PM_TA_UFSTACK_MMUPAGE_STATUS_1,RGX_CR_PM_TA_UFSTACK_MMUPAGE_STATUS_1" hexmask.long 0xC 0.--31. 1. "Reserved_22,Reserved_22" line.long 0x10 "RGX_CR_PM_UFSTACK_LOCK_STATUS_0,In rogue architecture. there is a unified free list whereby shared across multiple context. This lock status indicating the stack owner at the time being. Note PMA and PMD can not acquire the lock @ the same time" hexmask.long 0x10 2.--31. 1. "Reserved_2,Reserved_2" newline bitfld.long 0x10 1. "PMD,Bit 1: Page DeAllocation Manger is grabing the lock. 0:idle/ 1 used." "idle/ 1 used,Page DeAllocation Manger is grabing the lock" newline bitfld.long 0x10 0. "PMA,Bit 0: Page Allocation Manger is grabing the lock. 0:idle/ 1 used." "idle/ 1 used,?" line.long 0x14 "RGX_CR_PM_UFSTACK_LOCK_STATUS_1,In rogue architecture. there is a unified free list whereby shared across multiple context. This lock status indicating the stack owner at the time being. Note PMA and PMD can not acquire the lock @ the same time" hexmask.long 0x14 0.--31. 1. "Reserved_2,Reserved_2" line.long 0x18 "RGX_CR_PM_UFSTACK_LOCK_OWNER_0,RGX_CR_PM_UFSTACK_LOCK_OWNER_0" hexmask.long 0x18 2.--31. 1. "Reserved_2,Reserved_2" newline bitfld.long 0x18 1. "TD,Bit 1 :3D free list Lock owner. 0 PMA / 1 PMD" "0,1" newline bitfld.long 0x18 0. "TA,Bit 0: TA free list Lock Owner. 0 PMA / 1 PMD." "TA free list Lock Owner,?" line.long 0x1C "RGX_CR_PM_UFSTACK_LOCK_OWNER_1,RGX_CR_PM_UFSTACK_LOCK_OWNER_1" hexmask.long 0x1C 0.--31. 1. "Reserved_2,Reserved_2" group.long 0x20F8++0x1F line.long 0x0 "RGX_CR_PM_UFSTACK_POLICY_0,This register enables the PM to drain pages from the unified free list stack It is a static configuration register" hexmask.long 0x0 1.--31. 1. "Reserved_1,Reserved_1" newline bitfld.long 0x0 0. "OP,when this bit is '1' PM will try to drain pages from the unified free list stack as long as the ta free list do not have enough pages for the allocation" "0,1" line.long 0x4 "RGX_CR_PM_UFSTACK_POLICY_1,This register enables the PM to drain pages from the unified free list stack It is a static configuration register" hexmask.long 0x4 0.--31. 1. "Reserved_1,Reserved_1" line.long 0x8 "RGX_CR_PM_VFP_TRAN_EN_0,This register enables the PM to another level of transfrom which is from Virtial Page to VirtualPhysical Page number" hexmask.long 0x8 1.--31. 1. "Reserved_1,Reserved_1" newline bitfld.long 0x8 0. "OP,when this bit is '1' PM will try to another level of lookup between virtual page and the virtual physical page" "0,1" line.long 0xC "RGX_CR_PM_VFP_TRAN_EN_1,This register enables the PM to another level of transfrom which is from Virtial Page to VirtualPhysical Page number" hexmask.long 0xC 0.--31. 1. "Reserved_1,Reserved_1" line.long 0x10 "RGX_CR_PM_TA_VFP_TABLE_BASE_0,Effective on loading TA context. this register defines the base address of the virtual-physical page table during TA processing." hexmask.long 0x10 4.--31. 1. "ADDR,1TB Addressable 128 bits aligned Base Address for TA context page tables in the DPM module" newline hexmask.long.byte 0x10 0.--3. 1. "Reserved_0,Reserved_0" line.long 0x14 "RGX_CR_PM_TA_VFP_TABLE_BASE_1,Effective on loading TA context. this register defines the base address of the virtual-physical page table during TA processing." hexmask.long.tbyte 0x14 8.--31. 1. "Reserved_40,Reserved_40" newline hexmask.long.byte 0x14 0.--7. 1. "ADDR,1TB Addressable 128 bits aligned Base Address for TA context page tables in the DPM module" line.long 0x18 "RGX_CR_PM_3D_VFP_TABLE_BASE_0,Effective on loading 3D context. this register defines the base address of the virtual-physical page table during 3D processing." hexmask.long 0x18 4.--31. 1. "ADDR,1TB Addressable 128 bits aligned Base Address for 3D context page tables in the DPM module" newline hexmask.long.byte 0x18 0.--3. 1. "Reserved_0,Reserved_0" line.long 0x1C "RGX_CR_PM_3D_VFP_TABLE_BASE_1,Effective on loading 3D context. this register defines the base address of the virtual-physical page table during 3D processing." hexmask.long.tbyte 0x1C 8.--31. 1. "Reserved_40,Reserved_40" newline hexmask.long.byte 0x1C 0.--7. 1. "ADDR,1TB Addressable 128 bits aligned Base Address for 3D context page tables in the DPM module" wgroup.long 0x2600++0x7 line.long 0x0 "RGX_CR_TDM_START_0,A write of '1' to this register starts the 2D Data Master (TDM) reading the control stream contained in the circular buffer pointed to by TDM_CB_BASE_ADDR" hexmask.long 0x0 1.--31. 1. "Reserved_1,Reserved_1" newline bitfld.long 0x0 0. "PULSE,Start TDM" "0,1" line.long 0x4 "RGX_CR_TDM_START_1,A write of '1' to this register starts the 2D Data Master (TDM) reading the control stream contained in the circular buffer pointed to by TDM_CB_BASE_ADDR" hexmask.long 0x4 0.--31. 1. "Reserved_1,Reserved_1" group.long 0x2608++0x27 line.long 0x0 "RGX_CR_TDM_CB_BASE_0,TDM Circular Buffer base dddress" hexmask.long.tbyte 0x0 12.--31. 1. "ADDR,1 TB range 4KB aligned base address for TDM control stream circular buffer" newline hexmask.long.word 0x0 0.--11. 1. "Reserved_0,Reserved_0" line.long 0x4 "RGX_CR_TDM_CB_BASE_1,TDM Circular Buffer base dddress" hexmask.long.tbyte 0x4 8.--31. 1. "Reserved_40,Reserved_40" newline hexmask.long.byte 0x4 0.--7. 1. "ADDR,1 TB range 4KB aligned base address for TDM control stream circular buffer" line.long 0x8 "RGX_CR_TDM_CB_0,TDM Circular Buffer Size in 256-bit words" hexmask.long.word 0x8 20.--31. 1. "Reserved_20,Reserved_20" newline hexmask.long.word 0x8 5.--19. 1. "SIZE,1MB range 256-bit granular TDM Circular Buffer Size" newline hexmask.long.byte 0x8 0.--4. 1. "Reserved_0,Reserved_0" line.long 0xC "RGX_CR_TDM_CB_1,TDM Circular Buffer Size in 256-bit words" hexmask.long 0xC 0.--31. 1. "Reserved_20,Reserved_20" line.long 0x10 "RGX_CR_TDM_CB_QUEUE_0,TDM Circular Buffer Queue Control Base Address" hexmask.long 0x10 5.--31. 1. "CTRL_BASE_ADDR,1 TB range 256-bit aligned base address for TDM queue control structure" newline hexmask.long.byte 0x10 0.--4. 1. "Reserved_0,Reserved_0" line.long 0x14 "RGX_CR_TDM_CB_QUEUE_1,TDM Circular Buffer Queue Control Base Address" hexmask.long.tbyte 0x14 8.--31. 1. "Reserved_40,Reserved_40" newline hexmask.long.byte 0x14 0.--7. 1. "CTRL_BASE_ADDR,1 TB range 256-bit aligned base address for TDM queue control structure" line.long 0x18 "RGX_CR_TDM_CB_WRITE_POINTER_GUARD_0,TDM Circular Buffer Write Pointer Guard Size. TDM will refresh it's local copy of the Queue Control Write Pointer from memory when the Read Pointer is within the Guard Size of the Write Pointer." hexmask.long.word 0x18 20.--31. 1. "Reserved_20,Reserved_20" newline hexmask.long.word 0x18 5.--19. 1. "SIZE,1MB range 256-bit granular Write Pointer Guard Size" newline hexmask.long.byte 0x18 0.--4. 1. "Reserved_0,Reserved_0" line.long 0x1C "RGX_CR_TDM_CB_WRITE_POINTER_GUARD_1,TDM Circular Buffer Write Pointer Guard Size. TDM will refresh it's local copy of the Queue Control Write Pointer from memory when the Read Pointer is within the Guard Size of the Write Pointer." hexmask.long 0x1C 0.--31. 1. "Reserved_20,Reserved_20" line.long 0x20 "RGX_CR_TDM_CB_READ_POINTER_UPDATE_0,TDM Circular Buffer Read Pointer Update Frequency. the TDM will update the Queue Control Read Pointer value in memory whenever the Read Pointer has moved by this amount since the last memory write." hexmask.long.word 0x20 20.--31. 1. "Reserved_20,Reserved_20" newline hexmask.long.word 0x20 5.--19. 1. "FREQUENCY,1MB range 256-bit granular Read Pointer Update Frequency" newline hexmask.long.byte 0x20 0.--4. 1. "Reserved_0,Reserved_0" line.long 0x24 "RGX_CR_TDM_CB_READ_POINTER_UPDATE_1,TDM Circular Buffer Read Pointer Update Frequency. the TDM will update the Queue Control Read Pointer value in memory whenever the Read Pointer has moved by this amount since the last memory write." hexmask.long 0x24 0.--31. 1. "Reserved_20,Reserved_20" rgroup.long 0x2630++0x7 line.long 0x0 "RGX_CR_TDM_CB_READ_0,TDM Circular Buffer Read Pointer - current working position of TDM within 2D circular buffer. updated on a BLIT granularity" hexmask.long.word 0x0 20.--31. 1. "Reserved_20,Reserved_20" newline hexmask.long.tbyte 0x0 2.--19. 1. "POINTER,1MB range 32-bit granular Read Pointer" newline bitfld.long 0x0 0.--1. "Reserved_0,Reserved_0" "0,1,2,3" line.long 0x4 "RGX_CR_TDM_CB_READ_1,TDM Circular Buffer Read Pointer - current working position of TDM within 2D circular buffer. updated on a BLIT granularity" hexmask.long 0x4 0.--31. 1. "Reserved_20,Reserved_20" wgroup.long 0x2638++0xF line.long 0x0 "RGX_CR_TDM_RESUME_0,A write of '1' to this register resumes the TDM after 2D circular buffer empty failures." hexmask.long 0x0 1.--31. 1. "Reserved_1,Reserved_1" newline bitfld.long 0x0 0. "PULSE,Resume TDM" "0,1" line.long 0x4 "RGX_CR_TDM_RESUME_1,A write of '1' to this register resumes the TDM after 2D circular buffer empty failures." hexmask.long 0x4 0.--31. 1. "Reserved_1,Reserved_1" line.long 0x8 "RGX_CR_TDM_CONTEXT_STORE_0,Writing '1' to this register starts the TDM context store operation." hexmask.long 0x8 1.--31. 1. "Reserved_1,Reserved_1" newline bitfld.long 0x8 0. "PULSE,PULSE" "0,1" line.long 0xC "RGX_CR_TDM_CONTEXT_STORE_1,Writing '1' to this register starts the TDM context store operation." hexmask.long 0xC 0.--31. 1. "Reserved_1,Reserved_1" group.long 0x2648++0x7 line.long 0x0 "RGX_CR_TDM_CONTEXT_STATE_BASE_0,The base address in external memory of the TDM's context state buffer. to which it will store its snapshot state on a context store and from which it will reload on a TDM start pulse." hexmask.long 0x0 6.--31. 1. "ADDR,1TB range 512-bit aligned base address" newline hexmask.long.byte 0x0 0.--5. 1. "Reserved_0,Reserved_0" line.long 0x4 "RGX_CR_TDM_CONTEXT_STATE_BASE_1,The base address in external memory of the TDM's context state buffer. to which it will store its snapshot state on a context store and from which it will reload on a TDM start pulse." hexmask.long.tbyte 0x4 8.--31. 1. "Reserved_40,Reserved_40" newline hexmask.long.byte 0x4 0.--7. 1. "ADDR,1TB range 512-bit aligned base address" repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) rgroup.long ($2+0x2650)++0x3 line.long 0x0 "RGX_CR_TDM_FENCE_$1,TDM fence counters" hexmask.long 0x0 0.--31. 1. "COUNT,Count of the number of fence received reset to 0 on TDM_START_PULSE" repeat.end group.long 0x2658++0x7 line.long 0x0 "RGX_CR_TDM_YUV_CSC_COEFFICIENTS_0,Base address for the YUV CSC set of coefficients stored in memory for pixel data master" hexmask.long 0x0 0.--31. 1. "COEFFICIENTS,Base address DWORD aligned for the location in memory of the CSC coefficients" line.long 0x4 "RGX_CR_TDM_YUV_CSC_COEFFICIENTS_1,Base address for the YUV CSC set of coefficients stored in memory for pixel data master" hexmask.long 0x4 6.--31. 1. "Reserved_38,Reserved_38" newline hexmask.long.byte 0x4 0.--5. 1. "COEFFICIENTS,Base address DWORD aligned for the location in memory of the CSC coefficients" group.long 0x2678++0x7 line.long 0x0 "RGX_CR_TDM_WORKLOAD_0,TDM workload priority policy." hexmask.long 0x0 2.--31. 1. "Reserved_2,Reserved_2" newline bitfld.long 0x0 0.--1. "PRIORITY,0: Equal priority; 1: 3D has priority; 2: TDM has priority; 3: Reserved" "Equal priority;,?,TDM has priority;,Reserved" line.long 0x4 "RGX_CR_TDM_WORKLOAD_1,TDM workload priority policy." hexmask.long 0x4 0.--31. 1. "Reserved_2,Reserved_2" group.long 0x3800++0x7 line.long 0x0 "RGX_CR_SLC_CTRL_MISC_0,SLC control registers" hexmask.long.byte 0x0 24.--31. 1. "Reserved_24,Reserved_24" newline hexmask.long.byte 0x0 16.--23. 1. "ADDR_DECODE_MODE,Address decoding used to determine cache bank from the address: 0x00 = Bit 6 = 64 byte 0x01 = Bit 7 = 128 byte 0x10 = Simple XOR based address hash 1 see SLC TRM 0x11 = Simple XOR based address hash 2 see SLC TRM 0x20 = PVR address.." newline hexmask.long.byte 0x0 9.--15. 1. "Reserved_9,Reserved_9" newline bitfld.long 0x0 8. "PAUSE,Pause the SLC" "0,1" newline hexmask.long.byte 0x0 4.--7. 1. "Reserved_4,Reserved_4" newline bitfld.long 0x0 3. "RESP_PRIORITY,Priority setting between Hit and Miss on return response. Default is round robin and set to 1 if miss needs priority over hit" "0,1" newline bitfld.long 0x0 2. "ENABLE_LINE_USE_LIMIT,Enable the use of cache line limits" "0,1" newline bitfld.long 0x0 1. "ENABLE_PSG_HAZARD_CHECK,Enable the hazard checking of PSG writes only turn off if strict write ordering is guaranteed in the memory fabric" "0,1" newline bitfld.long 0x0 0. "BYPASS_BURST_COMBINER,Disable the burst combiner on the external memory interface" "0,1" line.long 0x4 "RGX_CR_SLC_CTRL_MISC_1,SLC control registers" hexmask.long 0x4 0.--31. 1. "SCRAMBLE_BITS,Pattern of bits used to determine the Cache Bank in Address Decode mode 0x21. The actual Cache Bank to use is determined by indexing into the 32 Scramble Bits using the 5 LSB's of the Hash result and then XORing this with Bit 6 of the.." wgroup.long 0x3808++0x17 line.long 0x0 "RGX_CR_SLC_CTRL_INVAL_0,SLC Invalidate control. Note that per Data Master operations only invalidate entries that have been referenced solely by the specified Data Master. any cache lines referenced by multiple Data Masters will not be affected by a per.." bitfld.long 0x0 31. "LAZY,Advanced mode of operation whereby other requestors are not blocked whilst the Invalidate is in progress" "0,1" newline hexmask.long.tbyte 0x0 9.--30. 1. "Reserved_9,Reserved_9" newline bitfld.long 0x0 8. "DM_FRC,When set invalidate all SLC entries referenced solely by the FRC Video Core (Optional feature)" "0,1" newline bitfld.long 0x0 7. "DM_VXE,When set invalidate all SLC entries referenced solely by the VXE Video Core (Optional feature)" "0,1" newline bitfld.long 0x0 6. "DM_VXD,When set invalidate all SLC entries referenced solely by the VXD Video Core (Optional feature)" "0,1" newline bitfld.long 0x0 5. "DM_HOST_META,When set invalidate all SLC entries referenced solely by the HOST or META" "0,1" newline bitfld.long 0x0 4. "DM_MMU,When set invalidate all SLC entries referenced solely by the MMU" "0,1" newline bitfld.long 0x0 3. "DM_COMPUTE,When set invalidate all SLC entries referenced solely by the COMPUTE data master" "0,1" newline bitfld.long 0x0 2. "DM_PIXEL,When set invalidate all SLC entries referenced solely by the PIXEL data master" "0,1" newline bitfld.long 0x0 1. "DM_TA,When set invalidate all SLC entries referenced solely by the TA group which includes VERTEX TESSELLATOR & STREAM_OUT data masters" "0,1" newline bitfld.long 0x0 0. "ALL,When set invalidate all SLC entries" "0,1" line.long 0x4 "RGX_CR_SLC_CTRL_INVAL_1,SLC Invalidate control. Note that per Data Master operations only invalidate entries that have been referenced solely by the specified Data Master. any cache lines referenced by multiple Data Masters will not be affected by a per.." hexmask.long 0x4 0.--31. 1. "Reserved_32,Reserved_32" line.long 0x8 "RGX_CR_SLC_CTRL_FLUSH_0,SLC Flush control. Note that per Data Master operations will flush any cache lines that have been made dirty by any writes from the specified Data Master." bitfld.long 0x8 31. "LAZY,Advanced mode of operation whereby other requestors are not blocked whilst the Flush is in progress" "0,1" newline hexmask.long.tbyte 0x8 9.--30. 1. "Reserved_9,Reserved_9" newline bitfld.long 0x8 8. "DM_FRC,When set flush all SLC entries made dirty by the FRC Video Core (Optional feature)" "0,1" newline bitfld.long 0x8 7. "DM_VXE,When set flush all SLC entries made dirty by the VXE Video Core (Optional feature)" "0,1" newline bitfld.long 0x8 6. "DM_VXD,When set flush all SLC entries made dirty by the VXD Video Core (Optional feature)" "0,1" newline bitfld.long 0x8 5. "DM_HOST_META,When set flush all SLC entries made dirty by the HOST or META" "0,1" newline bitfld.long 0x8 4. "DM_MMU,When set flush all SLC entries made dirty by the MMU" "0,1" newline bitfld.long 0x8 3. "DM_COMPUTE,When set flush all SLC entries made dirty by the COMPUTE data master" "0,1" newline bitfld.long 0x8 2. "DM_PIXEL,When set flush all SLC entries made dirty by the PIXEL data master" "0,1" newline bitfld.long 0x8 1. "DM_TA,When set flush all SLC entries made dirty by the TA group which includes VERTEX TESSELLATOR & STREAM_OUT data masters" "0,1" newline bitfld.long 0x8 0. "ALL,When set flush all SLC entries" "0,1" line.long 0xC "RGX_CR_SLC_CTRL_FLUSH_1,SLC Flush control. Note that per Data Master operations will flush any cache lines that have been made dirty by any writes from the specified Data Master." hexmask.long 0xC 0.--31. 1. "Reserved_32,Reserved_32" line.long 0x10 "RGX_CR_SLC_CTRL_FLUSH_INVAL_0,SLC Flush & Invalidate control. Note that per Data Master operations will flush any cache lines that have been made dirty by any writes from the specified Data Master. Combined Invalidate operation then only invalidates.." bitfld.long 0x10 31. "LAZY,Advanced mode of operation whereby other requestors are not blocked whilst the Flush Invalidate is in progress" "0,1" newline hexmask.long.tbyte 0x10 9.--30. 1. "Reserved_9,Reserved_9" newline bitfld.long 0x10 8. "DM_FRC,When set flush all SLC entries made dirty by the FRC Video Core then invalidate all SLC entries referenced solely by the FRC Video Core (Optional feature)" "0,1" newline bitfld.long 0x10 7. "DM_VXE,When set flush all SLC entries made dirty by the VXE Video Core then invalidate all SLC entries referenced solely by the VXE Video Core (Optional feature)" "0,1" newline bitfld.long 0x10 6. "DM_VXD,When set flush all SLC entries made dirty by the VXD Video Core then invalidate all SLC entries referenced solely by the VXD Video Core (Optional feature)" "0,1" newline bitfld.long 0x10 5. "DM_HOST_META,When set flush all SLC entries made dirty by the HOST or META then invalidate all SLC entries referenced solely by the HOST or META" "0,1" newline bitfld.long 0x10 4. "DM_MMU,When set flush all SLC entries made dirty by the MMU then invalidate all SLC entries referenced solely by the MMU" "0,1" newline bitfld.long 0x10 3. "DM_COMPUTE,When set flush all SLC entries made dirty by the COMPUTE data master then invalidate all SLC entries referenced solely by the COMPUTE data master" "0,1" newline bitfld.long 0x10 2. "DM_PIXEL,When set flush all SLC entries made dirty by the PIXEL data master then invalidate all SLC entries referenced solely by the PIXEL data master" "0,1" newline bitfld.long 0x10 1. "DM_TA,When set flush all SLC entries made dirty by the TA group which includes VERTEX TESSELLATOR & STREAM_OUT data masters then invalidate all SLC entries referenced solely by the TA group which includes VERTEX TESSELLATOR & STREAM_OUT data masters" "0,1" newline bitfld.long 0x10 0. "ALL,When set flush all SLC entries then invalidate all SLC entries" "0,1" line.long 0x14 "RGX_CR_SLC_CTRL_FLUSH_INVAL_1,SLC Flush & Invalidate control. Note that per Data Master operations will flush any cache lines that have been made dirty by any writes from the specified Data Master. Combined Invalidate operation then only invalidates.." hexmask.long 0x14 0.--31. 1. "Reserved_32,Reserved_32" rgroup.long 0x3820++0x7 line.long 0x0 "RGX_CR_SLC_STATUS0_0,Current status of Flush / Invalidate operations within the SLC" hexmask.long 0x0 3.--31. 1. "Reserved_3,Reserved_3" newline bitfld.long 0x0 2. "FLUSH_INVAL_PENDING,1 indicates there is a pending request to perform a combined Flush Invalidate on the SLC" "0,1" newline bitfld.long 0x0 1. "INVAL_PENDING,1 indicates there is a pending request to Invalidate the SLC" "0,1" newline bitfld.long 0x0 0. "FLUSH_PENDING,1 indicates there is a pending request to Flush the SLC" "0,1" line.long 0x4 "RGX_CR_SLC_STATUS0_1,Current status of Flush / Invalidate operations within the SLC" hexmask.long 0x4 0.--31. 1. "Reserved_3,Reserved_3" group.long 0x3828++0x7 line.long 0x0 "RGX_CR_SLC_CTRL_BYPASS_0,SLC Bypass control" bitfld.long 0x0 31. "DM_FASTRENDER,Bypass SLC the TDM data master" "0,1" newline bitfld.long 0x0 30. "DM_PM_ALIST,Bypass SLC for the PB_ZLS data master" "0,1" newline bitfld.long 0x0 29. "DM_PB_TE,Bypass SLC for the PB_TE data master" "0,1" newline bitfld.long 0x0 28. "DM_PB_VCE,Bypass SLC for the PB_VCE data master" "0,1" newline bitfld.long 0x0 26.--27. "Reserved_26,Reserved_26" "0,1,2,3" newline bitfld.long 0x0 25. "REQ_IPF_CPF,Bypass SLC for IPF (CPF) requestor" "0,1" newline bitfld.long 0x0 24. "REQ_TPU,Bypass SLC for TPU requests coming from the MCU requestor" "0,1" newline bitfld.long 0x0 23. "REQ_FBDC,Bypass SLC for the FBDC requestor" "0,1" newline bitfld.long 0x0 22. "Reserved_22,Reserved_22" "0,1" newline bitfld.long 0x0 21. "BYP_CC_N,Bypass SLC when Cache Coherency bit is not set" "0,1" newline bitfld.long 0x0 20. "BYP_CC,Bypass SLC when Cache Coherency bit is set" "0,1" newline bitfld.long 0x0 19. "REQ_MCU,Bypass SLC for the MCU requestor" "0,1" newline bitfld.long 0x0 18. "REQ_PDS,Bypass SLC for the PDS requestor" "0,1" newline bitfld.long 0x0 17. "REQ_TPF,Bypass SLC for the TPF requestor" "0,1" newline bitfld.long 0x0 16. "REQ_TA_TPC,Bypass SLC for the TA (Tail Pointer Cache data) requestor" "0,1" newline bitfld.long 0x0 15. "Reserved_15,Reserved_15" "0,1" newline bitfld.long 0x0 14. "REQ_USC,Bypass SLC for the USC requestor" "0,1" newline bitfld.long 0x0 13. "REQ_META,Bypass SLC for the META requestor" "0,1" newline bitfld.long 0x0 12. "REQ_HOST,Bypass SLC for the Host requestor" "0,1" newline bitfld.long 0x0 11. "REQ_MMU_PT,Bypass SLC for the MMU requestor (Page Table data)" "0,1" newline bitfld.long 0x0 10. "REQ_MMU_PD,Bypass SLC for the MMU requestor (Page Directory data)" "0,1" newline bitfld.long 0x0 9. "REQ_MMU_PC,Bypass SLC for the MMU requestor (Page Catalogue data)" "0,1" newline bitfld.long 0x0 8. "DM_FRC,Bypass SLC for the FRC Video Core (Optional feature)" "0,1" newline bitfld.long 0x0 7. "DM_VXE,Bypass SLC for the VXE Video Core (Optional feature)" "0,1" newline bitfld.long 0x0 6. "DM_VXD,Bypass SLC for the VXD Video Core (Optional feature)" "0,1" newline bitfld.long 0x0 5. "DM_HOST_META,Bypass SLC the HOST/META data master" "0,1" newline bitfld.long 0x0 4. "DM_MMU,Bypass SLC the MMU data master" "0,1" newline bitfld.long 0x0 3. "DM_COMPUTE,Bypass SLC the COMPUTE data master" "0,1" newline bitfld.long 0x0 2. "DM_PIXEL,Bypass SLC for the PIXEL data master" "0,1" newline bitfld.long 0x0 1. "DM_TA,Bypass SLC for the TA group which includes VERTEX TESSELLATOR & STREAM_OUT data masters" "0,1" newline bitfld.long 0x0 0. "ALL,Bypass SLC for all requesters" "0,1" line.long 0x4 "RGX_CR_SLC_CTRL_BYPASS_1,SLC Bypass control" hexmask.long.word 0x4 22.--31. 1. "Reserved_54,Reserved_54" newline bitfld.long 0x4 21. "REQ_TCU_DM_COMPUTE,Bypass SLC when DM is COMPUTE for TCU requests" "0,1" newline bitfld.long 0x4 19.--20. "Reserved_51,Reserved_51" "0,1,2,3" newline bitfld.long 0x4 18. "REQ_FBC,Bypass SLC for FBC requestor" "0,1" newline bitfld.long 0x4 17. "REQ_IPF_RREQ,Bypass SLC for IPF (RREQ) requestor" "0,1" newline bitfld.long 0x4 16. "REQ_IPF_CREQ,Bypass SLC for IPF (CREQ) requestor" "0,1" newline bitfld.long 0x4 15. "REQ_IPF_PREQ,Bypass SLC for IPF (PREQ) requestor" "0,1" newline bitfld.long 0x4 14. "REQ_IPF_DBSC,Bypass SLC for IPF (DBSC) requestor" "0,1" newline bitfld.long 0x4 13. "REQ_TCU,Bypass SLC for TCU requests" "0,1" newline bitfld.long 0x4 12. "REQ_PBE,Bypass SLC for PBE requestor" "0,1" newline bitfld.long 0x4 11. "REQ_ISP,Bypass SLC for the ISP requestor" "0,1" newline bitfld.long 0x4 10. "REQ_PM,Bypass SLC for the PM requestor" "0,1" newline bitfld.long 0x4 9. "REQ_TDM,Bypass SLC for the TDM requestor" "0,1" newline bitfld.long 0x4 8. "REQ_CDM,Bypass SLC for the CDM requestor" "0,1" newline bitfld.long 0x4 7. "REQ_TSPF_PDS_STATE,Bypass SLC for the TSPF PDS STATE requestor" "0,1" newline bitfld.long 0x4 6. "REQ_TSPF_DB,Bypass SLC for the TSPF DB requestor" "0,1" newline bitfld.long 0x4 5. "REQ_TSPF_VTX_VAR,Bypass SLC for the TSPF VTX VAR requestor" "0,1" newline bitfld.long 0x4 4. "REQ_VDM,Bypass SLC for VDM requestor" "0,1" newline bitfld.long 0x4 3. "REQ_TA_PSG_STREAM,Bypass SLC for the TA (PSG Stream) requestor" "0,1" newline bitfld.long 0x4 2. "REQ_TA_PSG_REGION,Bypass SLC for the TA (PSG Region) requestor" "0,1" newline bitfld.long 0x4 1. "REQ_TA_VCE,Bypass SLC for the TA (VCE) requestor" "0,1" newline bitfld.long 0x4 0. "REQ_TA_PPP,Bypass SLC for the TA (PPP) requestor" "0,1" repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) group.long ($2+0x3830)++0x3 line.long 0x0 "RGX_CR_SLC_LINE_USE_COUNT_LIMIT0_$1,Define the maximum number of cache lines allowed to be allocated to each requester within the SLC. Note that values are specified per bank as a multiple of 4 cache lines with values of 0x0 denoting no limit. Also note.." hexmask.long.byte 0x0 24.--31. 1. "TDM,Maximum number of cachelines allocated to the TDM requestor" newline hexmask.long.byte 0x0 16.--23. 1. "HOST,Maximum number of cachelines allocated to the HOST requestor" newline hexmask.long.byte 0x0 8.--15. 1. "TCU,Maximum number of cachelines allocated to the TCU requestor" newline hexmask.long.byte 0x0 0.--7. 1. "MMU,Maximum number of cachelines allocated to the MMU requestor" repeat.end group.long 0x3838++0x7 line.long 0x0 "RGX_CR_SLC_LINE_USE_COUNT_LIMIT1_0,Define the maximum number of cache lines allowed to be allocated to each requester within the SLC. Note that values are specified per bank as a multiple of 4 cache lines with values of 0x0 denoting no limit. Also note.." hexmask.long.byte 0x0 24.--31. 1. "VXD,Maximum number of cachelines allocated to the VXD requestor" newline hexmask.long.byte 0x0 16.--23. 1. "FBDC,Maximum number of cachelines allocated to the FBDC requestor" newline hexmask.long.byte 0x0 8.--15. 1. "MCU,Maximum number of cachelines allocated to the MCU requestor" newline hexmask.long.byte 0x0 0.--7. 1. "PDS,Maximum number of cachelines allocated to the PDS requestor" line.long 0x4 "RGX_CR_SLC_LINE_USE_COUNT_LIMIT1_1,Define the maximum number of cache lines allowed to be allocated to each requester within the SLC. Note that values are specified per bank as a multiple of 4 cache lines with values of 0x0 denoting no limit. Also note.." hexmask.long.word 0x4 16.--31. 1. "Reserved_48,Reserved_48" newline hexmask.long.byte 0x4 8.--15. 1. "FRC,Maximum number of cachelines allocated to the FRC requestor" newline hexmask.long.byte 0x4 0.--7. 1. "VXE,Maximum number of cachelines allocated to the VXE requestor" rgroup.long 0x3840++0x37 line.long 0x0 "RGX_CR_SLC_LINE_USE_COUNT_STATUS0_0,Number of cache lines currently allocated to each requester within the SLC. Values will constantly change when the core is active but will give a representative snapshot of cache usage." hexmask.long.byte 0x0 24.--31. 1. "BANK0_TDM,Number of cache lines in bank 0 currently allocated to the TDM" newline hexmask.long.word 0x0 12.--23. 1. "BANK1_MMU,Number of cache lines in bank 1 currently allocated to the MMU" newline hexmask.long.word 0x0 0.--11. 1. "BANK0_MMU,Number of cache lines in bank 0 currently allocated to the MMU" line.long 0x4 "RGX_CR_SLC_LINE_USE_COUNT_STATUS0_1,Number of cache lines currently allocated to each requester within the SLC. Values will constantly change when the core is active but will give a representative snapshot of cache usage." hexmask.long.byte 0x4 28.--31. 1. "Reserved_60,Reserved_60" newline hexmask.long.word 0x4 16.--27. 1. "BANK0_HOST,Number of cache lines in bank 0 currently allocated to the HOST" newline hexmask.long.word 0x4 4.--15. 1. "BANK1_TDM,Number of cache lines in bank 1 currently allocated to the TDM" newline hexmask.long.byte 0x4 0.--3. 1. "BANK0_TDM,Number of cache lines in bank 0 currently allocated to the TDM" line.long 0x8 "RGX_CR_SLC_LINE_USE_COUNT_STATUS1_0,Number of cache lines currently allocated to each requester within the SLC. Values will constantly change when the core is active but will give a representative snapshot of cache usage." hexmask.long.byte 0x8 24.--31. 1. "BANK1_TCU,Number of cache lines in bank 1 currently allocated to the TCU" newline hexmask.long.word 0x8 12.--23. 1. "BANK0_TCU,Number of cache lines in bank 0 currently allocated to the TCU" newline hexmask.long.word 0x8 0.--11. 1. "BANK1_HOST,Number of cache lines in bank 1 currently allocated to the HOST" line.long 0xC "RGX_CR_SLC_LINE_USE_COUNT_STATUS1_1,Number of cache lines currently allocated to each requester within the SLC. Values will constantly change when the core is active but will give a representative snapshot of cache usage." hexmask.long.byte 0xC 28.--31. 1. "Reserved_60,Reserved_60" newline hexmask.long.word 0xC 16.--27. 1. "BANK1_USC,Number of cache lines in bank 1 currently allocated to the USC" newline hexmask.long.word 0xC 4.--15. 1. "BANK0_USC,Number of cache lines in bank 0 currently allocated to the USC" newline hexmask.long.byte 0xC 0.--3. 1. "BANK1_TCU,Number of cache lines in bank 1 currently allocated to the TCU" line.long 0x10 "RGX_CR_SLC_LINE_USE_COUNT_STATUS2_0,Number of cache lines currently allocated to each requester within the SLC. Values will constantly change when the core is active but will give a representative snapshot of cache usage." hexmask.long.byte 0x10 24.--31. 1. "BANK0_TA_TPC,Number of cache lines in bank 0 currently allocated to the TA (Tail Pointer Cache data)" newline hexmask.long.word 0x10 12.--23. 1. "BANK1_IPF_OBJ,Number of cache lines in bank 1 currently allocated to the IPF (Object data)" newline hexmask.long.word 0x10 0.--11. 1. "BANK0_IPF_OBJ,Number of cache lines in bank 0 currently allocated to the IPF (Object data)" line.long 0x14 "RGX_CR_SLC_LINE_USE_COUNT_STATUS2_1,Number of cache lines currently allocated to each requester within the SLC. Values will constantly change when the core is active but will give a representative snapshot of cache usage." hexmask.long.byte 0x14 28.--31. 1. "Reserved_60,Reserved_60" newline hexmask.long.word 0x14 16.--27. 1. "BANK0_TPF,Number of cache lines in bank 0 currently allocated to the TPF" newline hexmask.long.word 0x14 4.--15. 1. "BANK1_TA_TPC,Number of cache lines in bank 1 currently allocated to the TA (Tail Pointer Cache data)" newline hexmask.long.byte 0x14 0.--3. 1. "BANK0_TA_TPC,Number of cache lines in bank 0 currently allocated to the TA (Tail Pointer Cache data)" line.long 0x18 "RGX_CR_SLC_LINE_USE_COUNT_STATUS3_0,Number of cache lines currently allocated to each requester within the SLC. Values will constantly change when the core is active but will give a representative snapshot of cache usage." hexmask.long.byte 0x18 24.--31. 1. "BANK1_PDS,Number of cache lines in bank 1 currently allocated to the PDS" newline hexmask.long.word 0x18 12.--23. 1. "BANK0_PDS,Number of cache lines in bank 0 currently allocated to the PDS" newline hexmask.long.word 0x18 0.--11. 1. "BANK1_TPF,Number of cache lines in bank 1 currently allocated to the TPF" line.long 0x1C "RGX_CR_SLC_LINE_USE_COUNT_STATUS3_1,Number of cache lines currently allocated to each requester within the SLC. Values will constantly change when the core is active but will give a representative snapshot of cache usage." hexmask.long.byte 0x1C 28.--31. 1. "Reserved_60,Reserved_60" newline hexmask.long.word 0x1C 16.--27. 1. "BANK1_MCU,Number of cache lines in bank 1 currently allocated to the MCU" newline hexmask.long.word 0x1C 4.--15. 1. "BANK0_MCU,Number of cache lines in bank 0 currently allocated to the MCU" newline hexmask.long.byte 0x1C 0.--3. 1. "BANK1_PDS,Number of cache lines in bank 1 currently allocated to the PDS" line.long 0x20 "RGX_CR_SLC_LINE_USE_COUNT_STATUS4_0,Number of cache lines currently allocated to each requester within the SLC. Values will constantly change when the core is active but will give a representative snapshot of cache usage." hexmask.long.byte 0x20 24.--31. 1. "BANK0_VXD,Number of cache lines in bank 0 currently allocated to the VXD core" newline hexmask.long.word 0x20 12.--23. 1. "BANK1_FBDC,Number of cache lines in bank 1 currently allocated to the FBDC" newline hexmask.long.word 0x20 0.--11. 1. "BANK0_FBDC,Number of cache lines in bank 0 currently allocated to the FBDC" line.long 0x24 "RGX_CR_SLC_LINE_USE_COUNT_STATUS4_1,Number of cache lines currently allocated to each requester within the SLC. Values will constantly change when the core is active but will give a representative snapshot of cache usage." hexmask.long.byte 0x24 28.--31. 1. "Reserved_60,Reserved_60" newline hexmask.long.word 0x24 16.--27. 1. "BANK0_VXE,Number of cache lines in bank 0 currently allocated to the VXE core" newline hexmask.long.word 0x24 4.--15. 1. "BANK1_VXD,Number of cache lines in bank 1 currently allocated to the VXD core" newline hexmask.long.byte 0x24 0.--3. 1. "BANK0_VXD,Number of cache lines in bank 0 currently allocated to the VXD core" line.long 0x28 "RGX_CR_SLC_LINE_USE_COUNT_STATUS5_0,Number of cache lines currently allocated to each requester within the SLC. Values will constantly change when the core is active but will give a representative snapshot of cache usage." hexmask.long.byte 0x28 24.--31. 1. "BANK1_FRC,Number of cache lines in bank 1 currently allocated to the FRC core" newline hexmask.long.word 0x28 12.--23. 1. "BANK0_FRC,Number of cache lines in bank 0 currently allocated to the FRC core" newline hexmask.long.word 0x28 0.--11. 1. "BANK1_VXE,Number of cache lines in bank 1 currently allocated to the VXE core" line.long 0x2C "RGX_CR_SLC_LINE_USE_COUNT_STATUS5_1,Number of cache lines currently allocated to each requester within the SLC. Values will constantly change when the core is active but will give a representative snapshot of cache usage." hexmask.long.byte 0x2C 28.--31. 1. "Reserved_60,Reserved_60" newline hexmask.long.word 0x2C 16.--27. 1. "BANK1_PM,Number of cache lines in bank 1 currently allocated to the PM core" newline hexmask.long.word 0x2C 4.--15. 1. "BANK0_PM,Number of cache lines in bank 0 currently allocated to the PM core" newline hexmask.long.byte 0x2C 0.--3. 1. "BANK1_FRC,Number of cache lines in bank 1 currently allocated to the FRC core" line.long 0x30 "RGX_CR_SLC_STATUS1_0,Current status of the SLC" hexmask.long.byte 0x30 26.--31. 1. "Reserved_26,Reserved_26" newline hexmask.long.word 0x30 16.--25. 1. "READS0,Number of items of read data SLC bank 0 has in internal pipeline FIFO's" newline hexmask.long.byte 0x30 8.--15. 1. "READS1_EXT,Number of items of read data SLC bank 1 has outstanding from external memory" newline hexmask.long.byte 0x30 0.--7. 1. "READS0_EXT,Number of items of read data SLC bank 0 has outstanding from external memory" line.long 0x34 "RGX_CR_SLC_STATUS1_1,Current status of the SLC" bitfld.long 0x34 31. "PAUSED,All cache banks are Paused" "0,1" newline hexmask.long.tbyte 0x34 10.--30. 1. "Reserved_42,Reserved_42" newline hexmask.long.word 0x34 0.--9. 1. "READS1,Number of items of read data SLC bank 1 has in internal pipeline FIFO's" group.long 0x3878++0x7 line.long 0x0 "RGX_CR_SLC_STATS0_CTRL_0,Configuration of the SLC Stats counters inside SLC bank 0. The type fields should be set to define the events that should be counted. then constraints should be added to specify particular requestors or types of request that.." hexmask.long.byte 0x0 28.--31. 1. "Reserved_28,Reserved_28" newline bitfld.long 0x0 27. "STOP,Pause counting whilst this bit is set" "0,1" newline bitfld.long 0x0 26. "RESET,Reset counter" "0,1" newline bitfld.long 0x0 25. "RNW,If constraint set 0x0 count only writes 0x1 count only reads" "0,1" newline bitfld.long 0x0 24. "BYPASS,If constraint set 0x0 count cached requests 0x1 count bypassed requests" "0,1" newline bitfld.long 0x0 21.--23. "DM,If constraint set count only requests for the specified Data Master" "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x0 16.--20. 1. "TAG_ID,If constraint set count only requests with the specified Tag ID" newline hexmask.long.byte 0x0 8.--15. 1. "TAG_SB,If constraint set count only requests with the specified sideband Tag" newline bitfld.long 0x0 7. "SELECT_TAG_SB,Include Tag sideband in constraints" "0,1" newline bitfld.long 0x0 6. "SELECT_TAG_ID,Include Tag ID in constraints" "0,1" newline bitfld.long 0x0 5. "SELECT_DM,Include Data Master in constraints" "0,1" newline bitfld.long 0x0 4. "SELECT_BYPASS,Include Bypass enable in constraints" "0,1" newline bitfld.long 0x0 3. "SELECT_RNW,Include Wead/Write select in constraints" "0,1" newline bitfld.long 0x0 2. "TYPE_FLUSH,Count number of cache lines flushed" "0,1" newline bitfld.long 0x0 1. "TYPE_MISS,Count number of misses" "0,1" newline bitfld.long 0x0 0. "TYPE_HIT,Count number of hits" "0,1" line.long 0x4 "RGX_CR_SLC_STATS0_CTRL_1,Configuration of the SLC Stats counters inside SLC bank 0. The type fields should be set to define the events that should be counted. then constraints should be added to specify particular requestors or types of request that.." hexmask.long 0x4 0.--31. 1. "Reserved_28,Reserved_28" repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) rgroup.long ($2+0x3880)++0x3 line.long 0x0 "RGX_CR_SLC_STATS0_OUTPUT_$1,Output of the SLC Stats counter inside SLC bank 0." hexmask.long 0x0 0.--31. 1. "VALUE,Value of counter 0" repeat.end group.long 0x3888++0x7 line.long 0x0 "RGX_CR_SLC_STATS1_CTRL_0,Configuration of the SLC Stats counters inside SLC bank 1. The type fields should be set to define the events that should be counted. then constraints should be added to specify particular requestors or types of request that.." hexmask.long.byte 0x0 28.--31. 1. "Reserved_28,Reserved_28" newline bitfld.long 0x0 27. "STOP,Pause counting whilst this bit is set" "0,1" newline bitfld.long 0x0 26. "RESET,Reset counter" "0,1" newline bitfld.long 0x0 25. "RNW,If constraint set 0x0 count only writes 0x1 count only reads" "0,1" newline bitfld.long 0x0 24. "BYPASS,If constraint set 0x0 count cached requests 0x1 count bypassed requests" "0,1" newline bitfld.long 0x0 21.--23. "DM,If constraint set count only requests for the specified Data Master" "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x0 16.--20. 1. "TAG_ID,If constraint set count only requests with the specified Tag ID" newline hexmask.long.byte 0x0 8.--15. 1. "TAG_SB,If constraint set count only requests with the specified sideband Tag" newline bitfld.long 0x0 7. "SELECT_TAG_SB,Include Tag sideband in constraints" "0,1" newline bitfld.long 0x0 6. "SELECT_TAG_ID,Include Tag ID in constraints" "0,1" newline bitfld.long 0x0 5. "SELECT_DM,Include Data Master in constraints" "0,1" newline bitfld.long 0x0 4. "SELECT_BYPASS,Include Bypass enable in constraints" "0,1" newline bitfld.long 0x0 3. "SELECT_RNW,Include Wead/Write select in constraints" "0,1" newline bitfld.long 0x0 2. "TYPE_FLUSH,Count number of cache lines flushed" "0,1" newline bitfld.long 0x0 1. "TYPE_MISS,Count number of misses" "0,1" newline bitfld.long 0x0 0. "TYPE_HIT,Count number of hits" "0,1" line.long 0x4 "RGX_CR_SLC_STATS1_CTRL_1,Configuration of the SLC Stats counters inside SLC bank 1. The type fields should be set to define the events that should be counted. then constraints should be added to specify particular requestors or types of request that.." hexmask.long 0x4 0.--31. 1. "Reserved_28,Reserved_28" repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) rgroup.long ($2+0x3890)++0x3 line.long 0x0 "RGX_CR_SLC_STATS1_OUTPUT_$1,Output of the SLC Stats counter inside SLC bank 1." hexmask.long 0x0 0.--31. 1. "VALUE,Value of counter 1" repeat.end rgroup.long 0x3898++0x7 line.long 0x0 "RGX_CR_SLC_IDLE_0,RGX_CR_SLC_IDLE_0" hexmask.long.tbyte 0x0 10.--31. 1. "Reserved_10,Reserved_10" newline bitfld.long 0x0 9. "MH_SYSARB1,SYSARB1 Module IDLE" "0,1" newline bitfld.long 0x0 8. "MH_SYSARB0,SYSARB0 Module IDLE" "0,1" newline bitfld.long 0x0 7. "IMGBV4,IMG Bus v4 Module IDLE" "0,1" newline bitfld.long 0x0 6. "CACHE_BANKS,Cache Bank IDLEs" "0,1" newline bitfld.long 0x0 5. "RBOFIFO,Read Burst Order FIFO Module IDLE" "0,1" newline bitfld.long 0x0 4. "FRC_CONV,FRC Module IDLE" "0,1" newline bitfld.long 0x0 3. "VXE_CONV,Video Encode Converter Module IDLE" "0,1" newline bitfld.long 0x0 2. "VXD_CONV,Video Decode Converter Module IDLE" "0,1" newline bitfld.long 0x0 1. "BIF1_CONV,BIF128->256 Converter Module IDLE" "0,1" newline bitfld.long 0x0 0. "CBAR,CrossBar Module IDLE" "0,1" line.long 0x4 "RGX_CR_SLC_IDLE_1,RGX_CR_SLC_IDLE_1" hexmask.long 0x4 0.--31. 1. "Reserved_10,Reserved_10" repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) rgroup.long ($2+0x38A0)++0x3 line.long 0x0 "RGX_CR_MCU_PWR_NUM_$1,Power Monitoring register" hexmask.long 0x0 0.--31. 1. "L0_TO_L1_ACCESS,Number of L0 to L1 accesses. Both L0s in a DUST added together" repeat.end group.long 0x38A8++0x7 line.long 0x0 "RGX_CR_SLC_LINE_USE_COUNT_LIMIT2_0,Define the maximum number of cache lines allowed to be allocated to each requester within the SLC. Note that values are specified per bank as a multiple of 4 cache lines with values of 0x0 denoting no limit. Also note.." hexmask.long.byte 0x0 24.--31. 1. "CDM,Maximum number of cachelines allocated to the CDM requestor" newline hexmask.long.byte 0x0 16.--23. 1. "VDM,Maximum number of cachelines allocated to the VDM requestor" newline hexmask.long.byte 0x0 8.--15. 1. "ISP,Maximum number of cachelines allocated to the ISP requestor" newline hexmask.long.byte 0x0 0.--7. 1. "PBE,Maximum number of cachelines allocated to the PBE requestor" line.long 0x4 "RGX_CR_SLC_LINE_USE_COUNT_LIMIT2_1,Define the maximum number of cache lines allowed to be allocated to each requester within the SLC. Note that values are specified per bank as a multiple of 4 cache lines with values of 0x0 denoting no limit. Also note.." hexmask.long.tbyte 0x4 8.--31. 1. "Reserved_40,Reserved_40" newline hexmask.long.byte 0x4 0.--7. 1. "PM,Maximum number of cachelines allocated to the PM requestor" rgroup.long 0x38B0++0xF line.long 0x0 "RGX_CR_SLC_LINE_USE_COUNT_STATUS6_0,Number of cache lines currently allocated to each requester within the SLC. Values will constantly change when the core is active but will give a representative snapshot of cache usage." hexmask.long.byte 0x0 24.--31. 1. "BANK0_ISP,Number of cache lines in bank 0 currently allocated to the ISP core" newline hexmask.long.word 0x0 12.--23. 1. "BANK1_PBE,Number of cache lines in bank 1 currently allocated to the PBE core" newline hexmask.long.word 0x0 0.--11. 1. "BANK0_PBE,Number of cache lines in bank 0 currently allocated to the PBE core" line.long 0x4 "RGX_CR_SLC_LINE_USE_COUNT_STATUS6_1,Number of cache lines currently allocated to each requester within the SLC. Values will constantly change when the core is active but will give a representative snapshot of cache usage." hexmask.long.byte 0x4 28.--31. 1. "Reserved_60,Reserved_60" newline hexmask.long.word 0x4 16.--27. 1. "BANK0_CDM,Number of cache lines in bank 1 currently allocated to the CDM core" newline hexmask.long.word 0x4 4.--15. 1. "BANK1_ISP,Number of cache lines in bank 1 currently allocated to the ISP core" newline hexmask.long.byte 0x4 0.--3. 1. "BANK0_ISP,Number of cache lines in bank 0 currently allocated to the ISP core" line.long 0x8 "RGX_CR_SLC_LINE_USE_COUNT_STATUS7_0,Number of cache lines currently allocated to each requester within the SLC. Values will constantly change when the core is active but will give a representative snapshot of cache usage." hexmask.long.byte 0x8 24.--31. 1. "BANK1_VDM,Number of cache lines in bank 1 currently allocated to the VDM core" newline hexmask.long.word 0x8 12.--23. 1. "BANK0_VDM,Number of cache lines in bank 0 currently allocated to the VDM core" newline hexmask.long.word 0x8 0.--11. 1. "BANK1_CDM,Number of cache lines in bank 1 currently allocated to the CDM core" line.long 0xC "RGX_CR_SLC_LINE_USE_COUNT_STATUS7_1,Number of cache lines currently allocated to each requester within the SLC. Values will constantly change when the core is active but will give a representative snapshot of cache usage." hexmask.long 0xC 4.--31. 1. "Reserved_36,Reserved_36" newline hexmask.long.byte 0xC 0.--3. 1. "BANK1_VDM,Number of cache lines in bank 1 currently allocated to the VDM core" group.long 0x38C0++0x17 line.long 0x0 "RGX_CR_AXI_ACE_LITE_CONFIGURATION_0,AXI ACE-LITE configuration registers" bitfld.long 0x0 30.--31. "ARCACHE_CACHE_MAINTENANCE,Read cache policy for cache maintenance transactions - bit[1] should be set to 1" "0,1,2,3" newline hexmask.long.byte 0x0 26.--29. 1. "ARCACHE_COHERENT,Read cache policy for coherent transactions - bit[1] should be set to 1" newline hexmask.long.byte 0x0 22.--25. 1. "AWCACHE_COHERENT,Write cache policy for coherent transactions - bit[1] should be set to 1" newline bitfld.long 0x0 20.--21. "ARDOMAIN_BARRIER,Read shareability domain for barrier transactions 00 = Non-Shareable 01 = Inner Shareable 10 = Outer Shareable 11 = System" "Non-Shareable,Inner Shareable,?,?" newline bitfld.long 0x0 18.--19. "AWDOMAIN_BARRIER,Write shareability domain for barrier transactions 00 = Non-Shareable 01 = Inner Shareable 10 = Outer Shareable 11 = System" "Non-Shareable,Inner Shareable,?,?" newline bitfld.long 0x0 16.--17. "ARDOMAIN_CACHE_MAINTENANCE,Read shareability domain for cache maintenance transactions 00 = Non-Shareable 01 = Inner Shareable 10 = Outer Shareable" "Non-Shareable,Inner Shareable,?,?" newline bitfld.long 0x0 14.--15. "AWDOMAIN_COHERENT,Write shareability domain for coherant transactions 01 = Inner Shareable 10 = Outer Shareable" "?,Inner Shareable,?,?" newline bitfld.long 0x0 12.--13. "ARDOMAIN_COHERENT,Read shareability domain for coherant transactions 01 = Inner Shareable 10 = Outer Shareable" "?,Inner Shareable,?,?" newline bitfld.long 0x0 10.--11. "ARDOMAIN_NON_SNOOPING,Read shareability domain for non-snooping transactions 00 = Non-Shareable 11 = System" "Non-Shareable,?,?,?" newline bitfld.long 0x0 8.--9. "AWDOMAIN_NON_SNOOPING,Write shareability domain for non-snooping transactions 00 = Non-Shareable 11 = System" "Non-Shareable,?,?,?" newline hexmask.long.byte 0x0 4.--7. 1. "ARCACHE_NON_SNOOPING,Read cache policy for non-snooping transactions" newline hexmask.long.byte 0x0 0.--3. 1. "AWCACHE_NON_SNOOPING,Write cache policy for non-snooping transactions" line.long 0x4 "RGX_CR_AXI_ACE_LITE_CONFIGURATION_1,AXI ACE-LITE configuration registers" hexmask.long.tbyte 0x4 13.--31. 1. "Reserved_45,Reserved_45" newline hexmask.long.byte 0x4 5.--12. 1. "OSID_SECURITY,SET to 1 to disable secure reads/writes for each OSID" newline bitfld.long 0x4 4. "DISABLE_COHERENT_WRITELINEUNIQUE,SET to 1 to disable coherent write line uniques" "0,1" newline bitfld.long 0x4 3. "DISABLE_COHERENT_WRITE,SET to 1 to disable coherent writes" "0,1" newline bitfld.long 0x4 2. "DISABLE_COHERENT_READ,SET to 1 to disable coherent reads" "0,1" newline bitfld.long 0x4 0.--1. "ARCACHE_CACHE_MAINTENANCE,Read cache policy for cache maintenance transactions - bit[1] should be set to 1" "0,1,2,3" line.long 0x8 "RGX_CR_AXI_ACE_LITE_CACHE_MAINTENANCE_CONFIGURATION_0,AXI ACE-LITE Cache Maintenance configuration registers" hexmask.long 0x8 4.--31. 1. "MAINTENANCE_ADDRESS,Address to perform cache maintenace address on" newline bitfld.long 0x8 3. "MAINTENANCE_MAKEINVALID,Writing a 1 issues a makeinvalid operation" "0,1" newline bitfld.long 0x8 2. "MAINTENANCE_CLEAN_INVALID,Writing a 1 issues a clean invalid operation" "0,1" newline bitfld.long 0x8 1. "MAINTENANCE_CLEANSHARED,Writing a 1 issues a clean shared operation" "0,1" newline bitfld.long 0x8 0. "ENABLE_MAINTENANCE,Writing a 1 enables cache maintenance operations" "0,1" line.long 0xC "RGX_CR_AXI_ACE_LITE_CACHE_MAINTENANCE_CONFIGURATION_1,AXI ACE-LITE Cache Maintenance configuration registers" hexmask.long.tbyte 0xC 12.--31. 1. "Reserved_44,Reserved_44" newline hexmask.long.word 0xC 0.--11. 1. "MAINTENANCE_ADDRESS,Address to perform cache maintenace address on" line.long 0x10 "RGX_CR_AXI_ACE_LITE_CACHE_MAINTENANCE_STATUS_0,The hardware will set this to 1 once the cache maintenance operation has completed. The firmware should poll this bit and set it to 0. once it has acknowledged it being set to 1." hexmask.long 0x10 1.--31. 1. "Reserved_1,Reserved_1" newline bitfld.long 0x10 0. "DONE,DONE" "0,1" line.long 0x14 "RGX_CR_AXI_ACE_LITE_CACHE_MAINTENANCE_STATUS_1,The hardware will set this to 1 once the cache maintenance operation has completed. The firmware should poll this bit and set it to 0. once it has acknowledged it being set to 1." hexmask.long 0x14 0.--31. 1. "Reserved_1,Reserved_1" repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) group.long ($2+0x3930)++0x3 line.long 0x0 "RGX_CR_SLC_CTRL_MISC2_$1,SLC control registers" hexmask.long 0x0 0.--31. 1. "SCRAMBLE_BITS,Pattern of bits used to determine the MSB of the Cache Bank in 4 Bank configurations in Address Decode mode 0x21. The actual Cache Bank to use is determined by indexing into the 32 Scramble Bits using the 5 LSB's of the Hash result and then.." repeat.end group.long 0x3938++0x7 line.long 0x0 "RGX_CR_SLC_CROSSBAR_LOAD_BALANCE_0,SLC control registers to bypass SLC crossbar load balancing" hexmask.long 0x0 1.--31. 1. "Reserved_1,Reserved_1" newline bitfld.long 0x0 0. "BYPASS,control register bit to bypass load balancing in SLC crossbar. In this case the requests from img-memif0 will go directly to ocp-memif0 and so on" "0,1" line.long 0x4 "RGX_CR_SLC_CROSSBAR_LOAD_BALANCE_1,SLC control registers to bypass SLC crossbar load balancing" hexmask.long 0x4 0.--31. 1. "Reserved_1,Reserved_1" rgroup.long 0x3960++0x7 line.long 0x0 "RGX_CR_SLC_STATUS3_0,Current status of the SLC" hexmask.long.byte 0x0 24.--31. 1. "WRITES1_TRANSACTIONS_EXT,Number of outsanding write burst transactions in SLC bank 1" newline hexmask.long.byte 0x0 16.--23. 1. "WRITES0_TRANSACTIONS_EXT,Number of outsanding write burst transactions in SLC bank 0" newline hexmask.long.byte 0x0 8.--15. 1. "READS1_TRANSACTIONS_EXT,Number of outsanding read burst transactions in SLC bank 1" newline hexmask.long.byte 0x0 0.--7. 1. "READS0_TRANSACTIONS_EXT,Number of outsanding read burst transactions in SLC bank 0" line.long 0x4 "RGX_CR_SLC_STATUS3_1,Current status of the SLC" hexmask.long 0x4 0.--31. 1. "Reserved_32,Reserved_32" wgroup.long 0x4000++0x7 line.long 0x0 "RGX_CR_USC_INST_CACHE_0,RGX_CR_USC_INST_CACHE_0" hexmask.long 0x0 1.--31. 1. "Reserved_1,Reserved_1" newline bitfld.long 0x0 0. "INVALIDATE,Any write to this location invalidates the L1 and L2 instruction caches automatically" "0,1" line.long 0x4 "RGX_CR_USC_INST_CACHE_1,RGX_CR_USC_INST_CACHE_1" hexmask.long 0x4 0.--31. 1. "Reserved_1,Reserved_1" group.long 0x4008++0xF line.long 0x0 "RGX_CR_USC_CODE_BASE_VERTEX_0,RGX_CR_USC_CODE_BASE_VERTEX_0" hexmask.long 0x0 6.--31. 1. "ADDR,Vertex Data Master Code Base Register bits" newline hexmask.long.byte 0x0 0.--5. 1. "Reserved_0,Reserved_0" line.long 0x4 "RGX_CR_USC_CODE_BASE_VERTEX_1,RGX_CR_USC_CODE_BASE_VERTEX_1" hexmask.long.tbyte 0x4 8.--31. 1. "Reserved_40,Reserved_40" newline hexmask.long.byte 0x4 0.--7. 1. "ADDR,Vertex Data Master Code Base Register bits" line.long 0x8 "RGX_CR_USC_CODE_BASE_PIXEL_0,RGX_CR_USC_CODE_BASE_PIXEL_0" hexmask.long 0x8 6.--31. 1. "ADDR,Pixel Data Master Code Base Register bits" newline hexmask.long.byte 0x8 0.--5. 1. "Reserved_0,Reserved_0" line.long 0xC "RGX_CR_USC_CODE_BASE_PIXEL_1,RGX_CR_USC_CODE_BASE_PIXEL_1" hexmask.long.tbyte 0xC 8.--31. 1. "Reserved_40,Reserved_40" newline hexmask.long.byte 0xC 0.--7. 1. "ADDR,Pixel Data Master Code Base Register bits" group.long 0x4028++0x4F line.long 0x0 "RGX_CR_USC_CODE_BASE_COMPUTE_0,RGX_CR_USC_CODE_BASE_COMPUTE_0" hexmask.long 0x0 6.--31. 1. "ADDR,Compute Data Master Code Base Register bits" newline hexmask.long.byte 0x0 0.--5. 1. "Reserved_0,Reserved_0" line.long 0x4 "RGX_CR_USC_CODE_BASE_COMPUTE_1,RGX_CR_USC_CODE_BASE_COMPUTE_1" hexmask.long.tbyte 0x4 8.--31. 1. "Reserved_40,Reserved_40" newline hexmask.long.byte 0x4 0.--7. 1. "ADDR,Compute Data Master Code Base Register bits" line.long 0x8 "RGX_CR_USC_BREAKPOINT_0,RGX_CR_USC_BREAKPOINT_0" hexmask.long 0x8 1.--31. 1. "ADDR,Breakpoint Address" newline bitfld.long 0x8 0. "Reserved_0,Reserved_0" "0,1" line.long 0xC "RGX_CR_USC_BREAKPOINT_1,RGX_CR_USC_BREAKPOINT_1" hexmask.long 0xC 0.--31. 1. "Reserved_32,Reserved_32" line.long 0x10 "RGX_CR_USC_BREAKPOINT_HANDLER_0,RGX_CR_USC_BREAKPOINT_HANDLER_0" hexmask.long 0x10 1.--31. 1. "ADDR,Breakpoint Handler Address" newline bitfld.long 0x10 0. "Reserved_0,Reserved_0" "0,1" line.long 0x14 "RGX_CR_USC_BREAKPOINT_HANDLER_1,RGX_CR_USC_BREAKPOINT_HANDLER_1" hexmask.long 0x14 0.--31. 1. "Reserved_32,Reserved_32" line.long 0x18 "RGX_CR_USC_BREAKPOINT_CTRL_0,RGX_CR_USC_BREAKPOINT_CTRL_0" hexmask.long 0x18 4.--31. 1. "Reserved_4,Reserved_4" newline bitfld.long 0x18 3. "ENABLE,0 = Breakpoint disabled 1 = Breakpoint enabled" "Breakpoint disabled,Breakpoint enabled" newline bitfld.long 0x18 0.--2. "DM,Data Master of Breakpoint" "0,1,2,3,4,5,6,7" line.long 0x1C "RGX_CR_USC_BREAKPOINT_CTRL_1,RGX_CR_USC_BREAKPOINT_CTRL_1" hexmask.long 0x1C 0.--31. 1. "Reserved_4,Reserved_4" line.long 0x20 "RGX_CR_USC_SMP_SWAP_0,RGX_CR_USC_SMP_SWAP_0" hexmask.long 0x20 1.--31. 1. "Reserved_1,Reserved_1" newline bitfld.long 0x20 0. "ENABLE,Deactivate after SMP instruction" "0,1" line.long 0x24 "RGX_CR_USC_SMP_SWAP_1,RGX_CR_USC_SMP_SWAP_1" hexmask.long 0x24 0.--31. 1. "Reserved_1,Reserved_1" line.long 0x28 "RGX_CR_USC_OVERRIDE_CTRL_0,RGX_CR_USC_OVERRIDE_CTRL_0" hexmask.long.word 0x28 22.--31. 1. "Reserved_22,Reserved_22" newline bitfld.long 0x28 21. "USCIS_LOCKING,0 = Default enable locking of USCIS when queue fills to maintain task ordering 1 = retry USCIS request" "Default,retry USCIS request" newline bitfld.long 0x28 20. "PHASE_BOTH,0 = Default no extra pass groups when single phase followed by multi-phase 1 = generate pass group whenever phases per task changes" "Default,generate pass group whenever phases per task.." newline bitfld.long 0x28 18.--19. "RESERVE_SLOTS,0 = Default allow all slots to be used for first phase tasks 1 = reserve 1 slot 2 = reserve 2 3 = reserve 4" "Default,reserve 1 slot,reserve 2,reserve 4" newline bitfld.long 0x28 17. "NO_RESERVE,0 = Default reserve slots for second phases 1 = Do not reserve slots for second phase tasks" "Default,Do not reserve slots for second phase tasks" newline bitfld.long 0x28 15.--16. "MAX_GROUP,0 = Default - 8 pass groups in flight 1 = 6 pass groups 2 = 4 pass groups 3 = 2 pass groups. To disable entirely see PDS" "Default,?,?,?" newline bitfld.long 0x28 14. "WAKE_UP,0 = Default normal wake up 1 = force task wake up" "Default,force task wake up" newline bitfld.long 0x28 13. "LATE_PARTN,0 = Default enable pixel data master tasks to start before a partition is allocated 1 = wait for partition" "Default,wait for partition" newline bitfld.long 0x28 12. "DMA_LOCKING,0 = Default enable locking of DMA when queue fills to maintain task ordering 1 = retry DMA request" "Default,retry DMA request" newline bitfld.long 0x28 11. "PRIORITY,0 = Default enable state loading and end of tile tasks to run with higher priority 1 = all tasks low priority" "Default,all tasks low priority" newline bitfld.long 0x28 10. "PHASE_PASSES,0 = Default enable inferred pass groups when multiple phase tasks are encountered 1 = disable hard SDs must be used" "Default,disable" newline bitfld.long 0x28 9. "OUTPUT_WRITES,0 = Default enable tracking of output buffer write completion for on-edge buffer validlity 1 = tracking invalid" "Default,tracking invalid" newline bitfld.long 0x28 8. "SELECTIVE_RATE,0 = Default (core specific enable selective rate mode if functional) 1 = disable" "Default,disable" newline bitfld.long 0x28 6.--7. "Reserved_6,Reserved_6" "0,1,2,3" newline hexmask.long.byte 0x28 0.--5. 1. "DEBUG_TEMPS,Number of temps to add to PDS allocation size for debugging. Units of 8" line.long 0x2C "RGX_CR_USC_OVERRIDE_CTRL_1,RGX_CR_USC_OVERRIDE_CTRL_1" hexmask.long 0x2C 0.--31. 1. "Reserved_22,Reserved_22" line.long 0x30 "RGX_CR_USC_DC_CACHE_CTRL_0,RGX_CR_USC_DC_CACHE_CTRL_0" hexmask.long 0x30 1.--31. 1. "Reserved_1,Reserved_1" newline bitfld.long 0x30 0. "LINES,Number of lines in Dynamic Constant Cache - 0=64 1=128" "0,1" line.long 0x34 "RGX_CR_USC_DC_CACHE_CTRL_1,RGX_CR_USC_DC_CACHE_CTRL_1" hexmask.long 0x34 0.--31. 1. "Reserved_1,Reserved_1" line.long 0x38 "RGX_CR_USC_DC_CACHE_INVALIDATE_0,RGX_CR_USC_DC_CACHE_INVALIDATE_0" hexmask.long 0x38 1.--31. 1. "Reserved_1,Reserved_1" newline bitfld.long 0x38 0. "PENDING,A write of 1 to this location will cause an invalidation of the Dynamic Constant Cache. If DMKILL bit is not set then all entries are invalidated. If DMKILL bit is set then only a data master killing invalidation is performed. The invalidation.." "0,1" line.long 0x3C "RGX_CR_USC_DC_CACHE_INVALIDATE_1,RGX_CR_USC_DC_CACHE_INVALIDATE_1" hexmask.long 0x3C 0.--31. 1. "Reserved_1,Reserved_1" line.long 0x40 "RGX_CR_USC_SHARED_GROUP_CLEAR_0,RGX_CR_USC_SHARED_GROUP_CLEAR_0" hexmask.long 0x40 1.--31. 1. "Reserved_1,Reserved_1" newline bitfld.long 0x40 0. "PENDING,Any write to this location requests the USC Shared Group register file to be cleared" "0,1" line.long 0x44 "RGX_CR_USC_SHARED_GROUP_CLEAR_1,RGX_CR_USC_SHARED_GROUP_CLEAR_1" hexmask.long 0x44 0.--31. 1. "Reserved_1,Reserved_1" line.long 0x48 "RGX_CR_USC_PIXEL_OUTPUT_CTRL_0,RGX_CR_USC_PIXEL_OUTPUT_CTRL_0" hexmask.long.word 0x48 17.--31. 1. "Reserved_17,Reserved_17" newline hexmask.long.word 0x48 3.--16. 1. "PARTITION_MASK,Partition Enable Mask for USC. Defines which partitions are for use by the USC to prevent SPM Deadlock" newline bitfld.long 0x48 2. "ENABLE_4TH_PARTITION,Enables 4th Partition" "0,1" newline bitfld.long 0x48 0.--1. "WIDTH,WIDTH" "0,1,2,3" line.long 0x4C "RGX_CR_USC_PIXEL_OUTPUT_CTRL_1,RGX_CR_USC_PIXEL_OUTPUT_CTRL_1" hexmask.long 0x4C 0.--31. 1. "Reserved_17,Reserved_17" repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) group.long ($2+0x4078)++0x3 line.long 0x0 "RGX_CR_USC_CLEAR_REGISTER0_$1,RGX_CR_USC_CLEAR_REGISTER0_0" hexmask.long 0x0 0.--31. 1. "VAL,Clear Colour register 0" repeat.end repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) group.long ($2+0x4080)++0x3 line.long 0x0 "RGX_CR_USC_CLEAR_REGISTER1_$1,RGX_CR_USC_CLEAR_REGISTER1_0" hexmask.long 0x0 0.--31. 1. "VAL,Clear Colour register 1" repeat.end repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) group.long ($2+0x4088)++0x3 line.long 0x0 "RGX_CR_USC_CLEAR_REGISTER2_$1,RGX_CR_USC_CLEAR_REGISTER2_0" hexmask.long 0x0 0.--31. 1. "VAL,Clear Colour register 2" repeat.end repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) group.long ($2+0x4090)++0x3 line.long 0x0 "RGX_CR_USC_CLEAR_REGISTER3_$1,RGX_CR_USC_CLEAR_REGISTER3_0" hexmask.long 0x0 0.--31. 1. "VAL,Clear Colour register 3" repeat.end group.long 0x4098++0x3F line.long 0x0 "RGX_CR_USC_G0_0,RGX_CR_USC_G0_0" hexmask.long.tbyte 0x0 8.--31. 1. "Reserved_8,Reserved_8" newline hexmask.long.byte 0x0 0.--7. 1. "P,Global cross-thread-accessible read/write register for USC programs via the 'special' bank type" line.long 0x4 "RGX_CR_USC_G0_1,RGX_CR_USC_G0_1" hexmask.long 0x4 0.--31. 1. "Reserved_8,Reserved_8" line.long 0x8 "RGX_CR_USC_G1_0,RGX_CR_USC_G1_0" hexmask.long.tbyte 0x8 8.--31. 1. "Reserved_8,Reserved_8" newline hexmask.long.byte 0x8 0.--7. 1. "P,Global cross-thread-accessible read/write register for USC programs via the 'special' bank type" line.long 0xC "RGX_CR_USC_G1_1,RGX_CR_USC_G1_1" hexmask.long 0xC 0.--31. 1. "Reserved_8,Reserved_8" line.long 0x10 "RGX_CR_USC_G2_0,RGX_CR_USC_G2_0" hexmask.long.tbyte 0x10 8.--31. 1. "Reserved_8,Reserved_8" newline hexmask.long.byte 0x10 0.--7. 1. "P,Global cross-thread-accessible read/write register for USC programs via the 'special' bank type" line.long 0x14 "RGX_CR_USC_G2_1,RGX_CR_USC_G2_1" hexmask.long 0x14 0.--31. 1. "Reserved_8,Reserved_8" line.long 0x18 "RGX_CR_USC_G3_0,RGX_CR_USC_G3_0" hexmask.long.tbyte 0x18 8.--31. 1. "Reserved_8,Reserved_8" newline hexmask.long.byte 0x18 0.--7. 1. "P,Global cross-thread-accessible read/write register for USC programs via the 'special' bank type" line.long 0x1C "RGX_CR_USC_G3_1,RGX_CR_USC_G3_1" hexmask.long 0x1C 0.--31. 1. "Reserved_8,Reserved_8" line.long 0x20 "RGX_CR_USC_G4_0,RGX_CR_USC_G4_0" hexmask.long.tbyte 0x20 8.--31. 1. "Reserved_8,Reserved_8" newline hexmask.long.byte 0x20 0.--7. 1. "P,Global cross-thread-accessible read/write register for USC programs via the 'special' bank type" line.long 0x24 "RGX_CR_USC_G4_1,RGX_CR_USC_G4_1" hexmask.long 0x24 0.--31. 1. "Reserved_8,Reserved_8" line.long 0x28 "RGX_CR_USC_G5_0,RGX_CR_USC_G5_0" hexmask.long.tbyte 0x28 8.--31. 1. "Reserved_8,Reserved_8" newline hexmask.long.byte 0x28 0.--7. 1. "P,Global cross-thread-accessible read/write register for USC programs via the 'special' bank type" line.long 0x2C "RGX_CR_USC_G5_1,RGX_CR_USC_G5_1" hexmask.long 0x2C 0.--31. 1. "Reserved_8,Reserved_8" line.long 0x30 "RGX_CR_USC_G6_0,RGX_CR_USC_G6_0" hexmask.long.tbyte 0x30 8.--31. 1. "Reserved_8,Reserved_8" newline hexmask.long.byte 0x30 0.--7. 1. "P,Global cross-thread-accessible read/write register for USC programs via the 'special' bank type" line.long 0x34 "RGX_CR_USC_G6_1,RGX_CR_USC_G6_1" hexmask.long 0x34 0.--31. 1. "Reserved_8,Reserved_8" line.long 0x38 "RGX_CR_USC_G7_0,RGX_CR_USC_G7_0" hexmask.long.tbyte 0x38 8.--31. 1. "Reserved_8,Reserved_8" newline hexmask.long.byte 0x38 0.--7. 1. "P,Global cross-thread-accessible read/write register for USC programs via the 'special' bank type" line.long 0x3C "RGX_CR_USC_G7_1,RGX_CR_USC_G7_1" hexmask.long 0x3C 0.--31. 1. "Reserved_8,Reserved_8" rgroup.long 0x40D8++0x27 line.long 0x0 "RGX_CR_USC_SERV_PIXEL_0,RGX_CR_USC_SERV_PIXEL_0" hexmask.long.word 0x0 17.--31. 1. "Reserved_17,Reserved_17" newline bitfld.long 0x0 16. "EMPTY,No Pixel Data Master tasks in USC0 queue" "0,1" newline hexmask.long.word 0x0 0.--15. 1. "COUNT,Number of Pixel Data Master tasks serviced by USC0" line.long 0x4 "RGX_CR_USC_SERV_PIXEL_1,RGX_CR_USC_SERV_PIXEL_1" hexmask.long 0x4 0.--31. 1. "Reserved_17,Reserved_17" line.long 0x8 "RGX_CR_USC_SERV_VERTEX_0,RGX_CR_USC_SERV_VERTEX_0" hexmask.long.word 0x8 17.--31. 1. "Reserved_17,Reserved_17" newline bitfld.long 0x8 16. "EMPTY,No Vertex Data Master tasks in USC0 queue" "0,1" newline hexmask.long.word 0x8 0.--15. 1. "COUNT,Number of Vertex Data Master tasks serviced by USC0" line.long 0xC "RGX_CR_USC_SERV_VERTEX_1,RGX_CR_USC_SERV_VERTEX_1" hexmask.long 0xC 0.--31. 1. "Reserved_17,Reserved_17" line.long 0x10 "RGX_CR_USC_SERV_TESS_PIXEL_0,RGX_CR_USC_SERV_TESS_PIXEL_0" hexmask.long.word 0x10 17.--31. 1. "Reserved_17,Reserved_17" newline bitfld.long 0x10 16. "EMPTY,No Tessellator Pixel Data Master tasks in USC0 queue" "0,1" newline hexmask.long.word 0x10 0.--15. 1. "COUNT,Number of Tessellator Pixel Data Master tasks serviced by USC0" line.long 0x14 "RGX_CR_USC_SERV_TESS_PIXEL_1,RGX_CR_USC_SERV_TESS_PIXEL_1" hexmask.long 0x14 0.--31. 1. "Reserved_17,Reserved_17" line.long 0x18 "RGX_CR_USC_SERV_TESS_VERTEX_0,RGX_CR_USC_SERV_TESS_VERTEX_0" hexmask.long.word 0x18 17.--31. 1. "Reserved_17,Reserved_17" newline bitfld.long 0x18 16. "EMPTY,No Tessellator Vertex Data Master tasks in USC0 queue" "0,1" newline hexmask.long.word 0x18 0.--15. 1. "COUNT,Number of Tessellator Vertex Data Master tasks serviced by USC0" line.long 0x1C "RGX_CR_USC_SERV_TESS_VERTEX_1,RGX_CR_USC_SERV_TESS_VERTEX_1" hexmask.long 0x1C 0.--31. 1. "Reserved_17,Reserved_17" line.long 0x20 "RGX_CR_USC_SERV_COMPUTE_0,RGX_CR_USC_SERV_COMPUTE_0" hexmask.long.word 0x20 17.--31. 1. "Reserved_17,Reserved_17" newline bitfld.long 0x20 16. "EMPTY,No Compute Data Master tasks in USC0 queue" "0,1" newline hexmask.long.word 0x20 0.--15. 1. "COUNT,Number of Compute Data Master tasks serviced by USC0" line.long 0x24 "RGX_CR_USC_SERV_COMPUTE_1,RGX_CR_USC_SERV_COMPUTE_1" hexmask.long 0x24 0.--31. 1. "Reserved_17,Reserved_17" repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) rgroup.long ($2+0x4100)++0x3 line.long 0x0 "RGX_CR_USC_PARTITION_STATUS_$1,RGX_CR_USC_PARTITION_STATUS_0" hexmask.long.word 0x0 16.--31. 1. "CLOSED,Partition closed - end of tile task started" newline hexmask.long.word 0x0 0.--15. 1. "IN_USE,Partition in use" repeat.end rgroup.long 0x4108++0x17 line.long 0x0 "RGX_CR_USC_OLDEST_TASK_STATUS_0,RGX_CR_USC_OLDEST_TASK_STATUS_0" hexmask.long.word 0x0 20.--31. 1. "Reserved_20,Reserved_20" newline hexmask.long.byte 0x0 16.--19. 1. "PASS_NUM,The present pass group" newline bitfld.long 0x0 13.--15. "DM,The task Data Master" "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x0 9.--12. 1. "TILEQUAD,The stream of the task depends on Data Master Vertex: Indicates the patch of the task Pixel >= 4 cluster: The tile ID of the task Pixel 2 cluster: The tile ID and patch concatenated Compute: 0" newline bitfld.long 0x0 7.--8. "STATE,Queue state for entry" "0,1,2,3" newline bitfld.long 0x0 6. "NEW_SD,This task is at the start of a new SD group bit is cleared when the task is first run" "0,1" newline bitfld.long 0x0 5. "TFPU_CS_ED,This task is waiting for a TFPU strobe which has not been satisfied" "0,1" newline bitfld.long 0x0 4. "MCU_CS_ED,This task is waiting for an MCU CS strobe which has not been satisfied" "0,1" newline bitfld.long 0x0 3. "MCU_US_ED,This task is waiting for an MCU US strobe which has not been satisfied" "0,1" newline bitfld.long 0x0 2. "FRAG_TYPE,Is this task a work or state loading type. '1' indicates a Vertex/Fragment/Work type '0' indicates a Shared/ Coefficient/ Control type" "0,1" newline bitfld.long 0x0 1. "PHAS_ISSUE,This task must issue a PHAS instruction which has not yet been seen" "0,1" newline bitfld.long 0x0 0. "PASS_GROUP,Is the task the start of a new pass group" "0,1" line.long 0x4 "RGX_CR_USC_OLDEST_TASK_STATUS_1,RGX_CR_USC_OLDEST_TASK_STATUS_1" hexmask.long 0x4 0.--31. 1. "Reserved_20,Reserved_20" line.long 0x8 "RGX_CR_USC_PARTITION_TILE_STATUS0_0,RGX_CR_USC_PARTITION_TILE_STATUS0_0" bitfld.long 0x8 30.--31. "TILE_ID5,Tile ID for partition 5" "0,1,2,3" newline hexmask.long.byte 0x8 24.--29. 1. "TILE_ID4,Tile ID for partition 4" newline hexmask.long.byte 0x8 18.--23. 1. "TILE_ID3,Tile ID for partition 3" newline hexmask.long.byte 0x8 12.--17. 1. "TILE_ID2,Tile ID for partition 2" newline hexmask.long.byte 0x8 6.--11. 1. "TILE_ID1,Tile ID for partition 1" newline hexmask.long.byte 0x8 0.--5. 1. "TILE_ID0,Tile ID for partition 0" line.long 0xC "RGX_CR_USC_PARTITION_TILE_STATUS0_1,RGX_CR_USC_PARTITION_TILE_STATUS0_1" hexmask.long.word 0xC 16.--31. 1. "Reserved_48,Reserved_48" newline hexmask.long.byte 0xC 10.--15. 1. "TILE_ID7,Tile ID for partition 7" newline hexmask.long.byte 0xC 4.--9. 1. "TILE_ID6,Tile ID for partition 6" newline hexmask.long.byte 0xC 0.--3. 1. "TILE_ID5,Tile ID for partition 5" line.long 0x10 "RGX_CR_USC_PARTITION_TILE_STATUS1_0,RGX_CR_USC_PARTITION_TILE_STATUS1_0" bitfld.long 0x10 30.--31. "TILE_ID13,Tile ID for partition 13" "0,1,2,3" newline hexmask.long.byte 0x10 24.--29. 1. "TILE_ID12,Tile ID for partition 12" newline hexmask.long.byte 0x10 18.--23. 1. "TILE_ID11,Tile ID for partition 11" newline hexmask.long.byte 0x10 12.--17. 1. "TILE_ID10,Tile ID for partition 10" newline hexmask.long.byte 0x10 6.--11. 1. "TILE_ID9,Tile ID for partition 9" newline hexmask.long.byte 0x10 0.--5. 1. "TILE_ID8,Tile ID for partition 8" line.long 0x14 "RGX_CR_USC_PARTITION_TILE_STATUS1_1,RGX_CR_USC_PARTITION_TILE_STATUS1_1" hexmask.long.byte 0x14 28.--31. 1. "Reserved_60,Reserved_60" newline hexmask.long.byte 0x14 22.--27. 1. "TILE_ID17,Tile ID for partition 17" newline hexmask.long.byte 0x14 16.--21. 1. "TILE_ID16,Tile ID for partition 16" newline hexmask.long.byte 0x14 10.--15. 1. "TILE_ID15,Tile ID for partition 15" newline hexmask.long.byte 0x14 4.--9. 1. "TILE_ID14,Tile ID for partition 14" newline hexmask.long.byte 0x14 0.--3. 1. "TILE_ID13,Tile ID for partition 13" repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) rgroup.long ($2+0x4178)++0x3 line.long 0x0 "RGX_CR_USC_DM_SLOT0_$1,Cluster Data Master in Slots" hexmask.long.byte 0x0 28.--31. 1. "SLOT_7,SLOT_7" newline hexmask.long.byte 0x0 24.--27. 1. "SLOT_6,SLOT_6" newline hexmask.long.byte 0x0 20.--23. 1. "SLOT_5,SLOT_5" newline hexmask.long.byte 0x0 16.--19. 1. "SLOT_4,SLOT_4" newline hexmask.long.byte 0x0 12.--15. 1. "SLOT_3,SLOT_3" newline hexmask.long.byte 0x0 8.--11. 1. "SLOT_2,SLOT_2" newline hexmask.long.byte 0x0 4.--7. 1. "SLOT_1,SLOT_1" newline hexmask.long.byte 0x0 0.--3. 1. "SLOT_0,SLOT_0" repeat.end repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) rgroup.long ($2+0x4180)++0x3 line.long 0x0 "RGX_CR_USC_DM_SLOT1_$1,Cluster Data Master in Slots" hexmask.long.byte 0x0 28.--31. 1. "SLOT_7,SLOT_7" newline hexmask.long.byte 0x0 24.--27. 1. "SLOT_6,SLOT_6" newline hexmask.long.byte 0x0 20.--23. 1. "SLOT_5,SLOT_5" newline hexmask.long.byte 0x0 16.--19. 1. "SLOT_4,SLOT_4" newline hexmask.long.byte 0x0 12.--15. 1. "SLOT_3,SLOT_3" newline hexmask.long.byte 0x0 8.--11. 1. "SLOT_2,SLOT_2" newline hexmask.long.byte 0x0 4.--7. 1. "SLOT_1,SLOT_1" newline hexmask.long.byte 0x0 0.--3. 1. "SLOT_0,SLOT_0" repeat.end repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) rgroup.long ($2+0x4188)++0x3 line.long 0x0 "RGX_CR_USC_DM_SLOT2_$1,Cluster Data Master in Slots" hexmask.long.byte 0x0 28.--31. 1. "SLOT_7,SLOT_7" newline hexmask.long.byte 0x0 24.--27. 1. "SLOT_6,SLOT_6" newline hexmask.long.byte 0x0 20.--23. 1. "SLOT_5,SLOT_5" newline hexmask.long.byte 0x0 16.--19. 1. "SLOT_4,SLOT_4" newline hexmask.long.byte 0x0 12.--15. 1. "SLOT_3,SLOT_3" newline hexmask.long.byte 0x0 8.--11. 1. "SLOT_2,SLOT_2" newline hexmask.long.byte 0x0 4.--7. 1. "SLOT_1,SLOT_1" newline hexmask.long.byte 0x0 0.--3. 1. "SLOT_0,SLOT_0" repeat.end repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) rgroup.long ($2+0x4190)++0x3 line.long 0x0 "RGX_CR_USC_DM_SLOT3_$1,Cluster Data Master in Slots" hexmask.long.byte 0x0 28.--31. 1. "SLOT_7,SLOT_7" newline hexmask.long.byte 0x0 24.--27. 1. "SLOT_6,SLOT_6" newline hexmask.long.byte 0x0 20.--23. 1. "SLOT_5,SLOT_5" newline hexmask.long.byte 0x0 16.--19. 1. "SLOT_4,SLOT_4" newline hexmask.long.byte 0x0 12.--15. 1. "SLOT_3,SLOT_3" newline hexmask.long.byte 0x0 8.--11. 1. "SLOT_2,SLOT_2" newline hexmask.long.byte 0x0 4.--7. 1. "SLOT_1,SLOT_1" newline hexmask.long.byte 0x0 0.--3. 1. "SLOT_0,SLOT_0" repeat.end rgroup.long 0x41B8++0x7 line.long 0x0 "RGX_CR_USC_EXCEPTION_0,RGX_CR_USC_EXCEPTION_0" hexmask.long.word 0x0 16.--31. 1. "CODE,Cluster exception code" newline hexmask.long.word 0x0 1.--15. 1. "Reserved_1,Reserved_1" newline bitfld.long 0x0 0. "STATUS,1=Cluster has raised an exception" "?,Cluster has raised an exception" line.long 0x4 "RGX_CR_USC_EXCEPTION_1,RGX_CR_USC_EXCEPTION_1" hexmask.long 0x4 0.--31. 1. "Reserved_32,Reserved_32" rgroup.long 0x41D8++0xFF line.long 0x0 "RGX_CR_USC_SLOT0_0,RGX_CR_USC_SLOT0_0" hexmask.long 0x0 1.--31. 1. "PC,PC" newline bitfld.long 0x0 0. "Reserved_0,Reserved_0" "0,1" line.long 0x4 "RGX_CR_USC_SLOT0_1,RGX_CR_USC_SLOT0_1" hexmask.long 0x4 4.--31. 1. "Reserved_36,Reserved_36" newline hexmask.long.byte 0x4 0.--3. 1. "STATUS,STATUS" line.long 0x8 "RGX_CR_USC_SLOT1_0,RGX_CR_USC_SLOT1_0" hexmask.long 0x8 1.--31. 1. "PC,PC" newline bitfld.long 0x8 0. "Reserved_0,Reserved_0" "0,1" line.long 0xC "RGX_CR_USC_SLOT1_1,RGX_CR_USC_SLOT1_1" hexmask.long 0xC 4.--31. 1. "Reserved_36,Reserved_36" newline hexmask.long.byte 0xC 0.--3. 1. "STATUS,STATUS" line.long 0x10 "RGX_CR_USC_SLOT2_0,RGX_CR_USC_SLOT2_0" hexmask.long 0x10 1.--31. 1. "PC,PC" newline bitfld.long 0x10 0. "Reserved_0,Reserved_0" "0,1" line.long 0x14 "RGX_CR_USC_SLOT2_1,RGX_CR_USC_SLOT2_1" hexmask.long 0x14 4.--31. 1. "Reserved_36,Reserved_36" newline hexmask.long.byte 0x14 0.--3. 1. "STATUS,STATUS" line.long 0x18 "RGX_CR_USC_SLOT3_0,RGX_CR_USC_SLOT3_0" hexmask.long 0x18 1.--31. 1. "PC,PC" newline bitfld.long 0x18 0. "Reserved_0,Reserved_0" "0,1" line.long 0x1C "RGX_CR_USC_SLOT3_1,RGX_CR_USC_SLOT3_1" hexmask.long 0x1C 4.--31. 1. "Reserved_36,Reserved_36" newline hexmask.long.byte 0x1C 0.--3. 1. "STATUS,STATUS" line.long 0x20 "RGX_CR_USC_SLOT4_0,RGX_CR_USC_SLOT4_0" hexmask.long 0x20 1.--31. 1. "PC,PC" newline bitfld.long 0x20 0. "Reserved_0,Reserved_0" "0,1" line.long 0x24 "RGX_CR_USC_SLOT4_1,RGX_CR_USC_SLOT4_1" hexmask.long 0x24 4.--31. 1. "Reserved_36,Reserved_36" newline hexmask.long.byte 0x24 0.--3. 1. "STATUS,STATUS" line.long 0x28 "RGX_CR_USC_SLOT5_0,RGX_CR_USC_SLOT5_0" hexmask.long 0x28 1.--31. 1. "PC,PC" newline bitfld.long 0x28 0. "Reserved_0,Reserved_0" "0,1" line.long 0x2C "RGX_CR_USC_SLOT5_1,RGX_CR_USC_SLOT5_1" hexmask.long 0x2C 4.--31. 1. "Reserved_36,Reserved_36" newline hexmask.long.byte 0x2C 0.--3. 1. "STATUS,STATUS" line.long 0x30 "RGX_CR_USC_SLOT6_0,RGX_CR_USC_SLOT6_0" hexmask.long 0x30 1.--31. 1. "PC,PC" newline bitfld.long 0x30 0. "Reserved_0,Reserved_0" "0,1" line.long 0x34 "RGX_CR_USC_SLOT6_1,RGX_CR_USC_SLOT6_1" hexmask.long 0x34 4.--31. 1. "Reserved_36,Reserved_36" newline hexmask.long.byte 0x34 0.--3. 1. "STATUS,STATUS" line.long 0x38 "RGX_CR_USC_SLOT7_0,RGX_CR_USC_SLOT7_0" hexmask.long 0x38 1.--31. 1. "PC,PC" newline bitfld.long 0x38 0. "Reserved_0,Reserved_0" "0,1" line.long 0x3C "RGX_CR_USC_SLOT7_1,RGX_CR_USC_SLOT7_1" hexmask.long 0x3C 4.--31. 1. "Reserved_36,Reserved_36" newline hexmask.long.byte 0x3C 0.--3. 1. "STATUS,STATUS" line.long 0x40 "RGX_CR_USC_SLOT8_0,RGX_CR_USC_SLOT8_0" hexmask.long 0x40 1.--31. 1. "PC,PC" newline bitfld.long 0x40 0. "Reserved_0,Reserved_0" "0,1" line.long 0x44 "RGX_CR_USC_SLOT8_1,RGX_CR_USC_SLOT8_1" hexmask.long 0x44 4.--31. 1. "Reserved_36,Reserved_36" newline hexmask.long.byte 0x44 0.--3. 1. "STATUS,STATUS" line.long 0x48 "RGX_CR_USC_SLOT9_0,RGX_CR_USC_SLOT9_0" hexmask.long 0x48 1.--31. 1. "PC,PC" newline bitfld.long 0x48 0. "Reserved_0,Reserved_0" "0,1" line.long 0x4C "RGX_CR_USC_SLOT9_1,RGX_CR_USC_SLOT9_1" hexmask.long 0x4C 4.--31. 1. "Reserved_36,Reserved_36" newline hexmask.long.byte 0x4C 0.--3. 1. "STATUS,STATUS" line.long 0x50 "RGX_CR_USC_SLOT10_0,RGX_CR_USC_SLOT10_0" hexmask.long 0x50 1.--31. 1. "PC,PC" newline bitfld.long 0x50 0. "Reserved_0,Reserved_0" "0,1" line.long 0x54 "RGX_CR_USC_SLOT10_1,RGX_CR_USC_SLOT10_1" hexmask.long 0x54 4.--31. 1. "Reserved_36,Reserved_36" newline hexmask.long.byte 0x54 0.--3. 1. "STATUS,STATUS" line.long 0x58 "RGX_CR_USC_SLOT11_0,RGX_CR_USC_SLOT11_0" hexmask.long 0x58 1.--31. 1. "PC,PC" newline bitfld.long 0x58 0. "Reserved_0,Reserved_0" "0,1" line.long 0x5C "RGX_CR_USC_SLOT11_1,RGX_CR_USC_SLOT11_1" hexmask.long 0x5C 4.--31. 1. "Reserved_36,Reserved_36" newline hexmask.long.byte 0x5C 0.--3. 1. "STATUS,STATUS" line.long 0x60 "RGX_CR_USC_SLOT12_0,RGX_CR_USC_SLOT12_0" hexmask.long 0x60 1.--31. 1. "PC,PC" newline bitfld.long 0x60 0. "Reserved_0,Reserved_0" "0,1" line.long 0x64 "RGX_CR_USC_SLOT12_1,RGX_CR_USC_SLOT12_1" hexmask.long 0x64 4.--31. 1. "Reserved_36,Reserved_36" newline hexmask.long.byte 0x64 0.--3. 1. "STATUS,STATUS" line.long 0x68 "RGX_CR_USC_SLOT13_0,RGX_CR_USC_SLOT13_0" hexmask.long 0x68 1.--31. 1. "PC,PC" newline bitfld.long 0x68 0. "Reserved_0,Reserved_0" "0,1" line.long 0x6C "RGX_CR_USC_SLOT13_1,RGX_CR_USC_SLOT13_1" hexmask.long 0x6C 4.--31. 1. "Reserved_36,Reserved_36" newline hexmask.long.byte 0x6C 0.--3. 1. "STATUS,STATUS" line.long 0x70 "RGX_CR_USC_SLOT14_0,RGX_CR_USC_SLOT14_0" hexmask.long 0x70 1.--31. 1. "PC,PC" newline bitfld.long 0x70 0. "Reserved_0,Reserved_0" "0,1" line.long 0x74 "RGX_CR_USC_SLOT14_1,RGX_CR_USC_SLOT14_1" hexmask.long 0x74 4.--31. 1. "Reserved_36,Reserved_36" newline hexmask.long.byte 0x74 0.--3. 1. "STATUS,STATUS" line.long 0x78 "RGX_CR_USC_SLOT15_0,RGX_CR_USC_SLOT15_0" hexmask.long 0x78 1.--31. 1. "PC,PC" newline bitfld.long 0x78 0. "Reserved_0,Reserved_0" "0,1" line.long 0x7C "RGX_CR_USC_SLOT15_1,RGX_CR_USC_SLOT15_1" hexmask.long 0x7C 4.--31. 1. "Reserved_36,Reserved_36" newline hexmask.long.byte 0x7C 0.--3. 1. "STATUS,STATUS" line.long 0x80 "RGX_CR_USC_SLOT16_0,RGX_CR_USC_SLOT16_0" hexmask.long 0x80 1.--31. 1. "PC,PC" newline bitfld.long 0x80 0. "Reserved_0,Reserved_0" "0,1" line.long 0x84 "RGX_CR_USC_SLOT16_1,RGX_CR_USC_SLOT16_1" hexmask.long 0x84 4.--31. 1. "Reserved_36,Reserved_36" newline hexmask.long.byte 0x84 0.--3. 1. "STATUS,STATUS" line.long 0x88 "RGX_CR_USC_SLOT17_0,RGX_CR_USC_SLOT17_0" hexmask.long 0x88 1.--31. 1. "PC,PC" newline bitfld.long 0x88 0. "Reserved_0,Reserved_0" "0,1" line.long 0x8C "RGX_CR_USC_SLOT17_1,RGX_CR_USC_SLOT17_1" hexmask.long 0x8C 4.--31. 1. "Reserved_36,Reserved_36" newline hexmask.long.byte 0x8C 0.--3. 1. "STATUS,STATUS" line.long 0x90 "RGX_CR_USC_SLOT18_0,RGX_CR_USC_SLOT18_0" hexmask.long 0x90 1.--31. 1. "PC,PC" newline bitfld.long 0x90 0. "Reserved_0,Reserved_0" "0,1" line.long 0x94 "RGX_CR_USC_SLOT18_1,RGX_CR_USC_SLOT18_1" hexmask.long 0x94 4.--31. 1. "Reserved_36,Reserved_36" newline hexmask.long.byte 0x94 0.--3. 1. "STATUS,STATUS" line.long 0x98 "RGX_CR_USC_SLOT19_0,RGX_CR_USC_SLOT19_0" hexmask.long 0x98 1.--31. 1. "PC,PC" newline bitfld.long 0x98 0. "Reserved_0,Reserved_0" "0,1" line.long 0x9C "RGX_CR_USC_SLOT19_1,RGX_CR_USC_SLOT19_1" hexmask.long 0x9C 4.--31. 1. "Reserved_36,Reserved_36" newline hexmask.long.byte 0x9C 0.--3. 1. "STATUS,STATUS" line.long 0xA0 "RGX_CR_USC_SLOT20_0,RGX_CR_USC_SLOT20_0" hexmask.long 0xA0 1.--31. 1. "PC,PC" newline bitfld.long 0xA0 0. "Reserved_0,Reserved_0" "0,1" line.long 0xA4 "RGX_CR_USC_SLOT20_1,RGX_CR_USC_SLOT20_1" hexmask.long 0xA4 4.--31. 1. "Reserved_36,Reserved_36" newline hexmask.long.byte 0xA4 0.--3. 1. "STATUS,STATUS" line.long 0xA8 "RGX_CR_USC_SLOT21_0,RGX_CR_USC_SLOT21_0" hexmask.long 0xA8 1.--31. 1. "PC,PC" newline bitfld.long 0xA8 0. "Reserved_0,Reserved_0" "0,1" line.long 0xAC "RGX_CR_USC_SLOT21_1,RGX_CR_USC_SLOT21_1" hexmask.long 0xAC 4.--31. 1. "Reserved_36,Reserved_36" newline hexmask.long.byte 0xAC 0.--3. 1. "STATUS,STATUS" line.long 0xB0 "RGX_CR_USC_SLOT22_0,RGX_CR_USC_SLOT22_0" hexmask.long 0xB0 1.--31. 1. "PC,PC" newline bitfld.long 0xB0 0. "Reserved_0,Reserved_0" "0,1" line.long 0xB4 "RGX_CR_USC_SLOT22_1,RGX_CR_USC_SLOT22_1" hexmask.long 0xB4 4.--31. 1. "Reserved_36,Reserved_36" newline hexmask.long.byte 0xB4 0.--3. 1. "STATUS,STATUS" line.long 0xB8 "RGX_CR_USC_SLOT23_0,RGX_CR_USC_SLOT23_0" hexmask.long 0xB8 1.--31. 1. "PC,PC" newline bitfld.long 0xB8 0. "Reserved_0,Reserved_0" "0,1" line.long 0xBC "RGX_CR_USC_SLOT23_1,RGX_CR_USC_SLOT23_1" hexmask.long 0xBC 4.--31. 1. "Reserved_36,Reserved_36" newline hexmask.long.byte 0xBC 0.--3. 1. "STATUS,STATUS" line.long 0xC0 "RGX_CR_USC_SLOT24_0,RGX_CR_USC_SLOT24_0" hexmask.long 0xC0 1.--31. 1. "PC,PC" newline bitfld.long 0xC0 0. "Reserved_0,Reserved_0" "0,1" line.long 0xC4 "RGX_CR_USC_SLOT24_1,RGX_CR_USC_SLOT24_1" hexmask.long 0xC4 4.--31. 1. "Reserved_36,Reserved_36" newline hexmask.long.byte 0xC4 0.--3. 1. "STATUS,STATUS" line.long 0xC8 "RGX_CR_USC_SLOT25_0,RGX_CR_USC_SLOT25_0" hexmask.long 0xC8 1.--31. 1. "PC,PC" newline bitfld.long 0xC8 0. "Reserved_0,Reserved_0" "0,1" line.long 0xCC "RGX_CR_USC_SLOT25_1,RGX_CR_USC_SLOT25_1" hexmask.long 0xCC 4.--31. 1. "Reserved_36,Reserved_36" newline hexmask.long.byte 0xCC 0.--3. 1. "STATUS,STATUS" line.long 0xD0 "RGX_CR_USC_SLOT26_0,RGX_CR_USC_SLOT26_0" hexmask.long 0xD0 1.--31. 1. "PC,PC" newline bitfld.long 0xD0 0. "Reserved_0,Reserved_0" "0,1" line.long 0xD4 "RGX_CR_USC_SLOT26_1,RGX_CR_USC_SLOT26_1" hexmask.long 0xD4 4.--31. 1. "Reserved_36,Reserved_36" newline hexmask.long.byte 0xD4 0.--3. 1. "STATUS,STATUS" line.long 0xD8 "RGX_CR_USC_SLOT27_0,RGX_CR_USC_SLOT27_0" hexmask.long 0xD8 1.--31. 1. "PC,PC" newline bitfld.long 0xD8 0. "Reserved_0,Reserved_0" "0,1" line.long 0xDC "RGX_CR_USC_SLOT27_1,RGX_CR_USC_SLOT27_1" hexmask.long 0xDC 4.--31. 1. "Reserved_36,Reserved_36" newline hexmask.long.byte 0xDC 0.--3. 1. "STATUS,STATUS" line.long 0xE0 "RGX_CR_USC_SLOT28_0,RGX_CR_USC_SLOT28_0" hexmask.long 0xE0 1.--31. 1. "PC,PC" newline bitfld.long 0xE0 0. "Reserved_0,Reserved_0" "0,1" line.long 0xE4 "RGX_CR_USC_SLOT28_1,RGX_CR_USC_SLOT28_1" hexmask.long 0xE4 4.--31. 1. "Reserved_36,Reserved_36" newline hexmask.long.byte 0xE4 0.--3. 1. "STATUS,STATUS" line.long 0xE8 "RGX_CR_USC_SLOT29_0,RGX_CR_USC_SLOT29_0" hexmask.long 0xE8 1.--31. 1. "PC,PC" newline bitfld.long 0xE8 0. "Reserved_0,Reserved_0" "0,1" line.long 0xEC "RGX_CR_USC_SLOT29_1,RGX_CR_USC_SLOT29_1" hexmask.long 0xEC 4.--31. 1. "Reserved_36,Reserved_36" newline hexmask.long.byte 0xEC 0.--3. 1. "STATUS,STATUS" line.long 0xF0 "RGX_CR_USC_SLOT30_0,RGX_CR_USC_SLOT30_0" hexmask.long 0xF0 1.--31. 1. "PC,PC" newline bitfld.long 0xF0 0. "Reserved_0,Reserved_0" "0,1" line.long 0xF4 "RGX_CR_USC_SLOT30_1,RGX_CR_USC_SLOT30_1" hexmask.long 0xF4 4.--31. 1. "Reserved_36,Reserved_36" newline hexmask.long.byte 0xF4 0.--3. 1. "STATUS,STATUS" line.long 0xF8 "RGX_CR_USC_SLOT31_0,RGX_CR_USC_SLOT31_0" hexmask.long 0xF8 1.--31. 1. "PC,PC" newline bitfld.long 0xF8 0. "Reserved_0,Reserved_0" "0,1" line.long 0xFC "RGX_CR_USC_SLOT31_1,RGX_CR_USC_SLOT31_1" hexmask.long 0xFC 4.--31. 1. "Reserved_36,Reserved_36" newline hexmask.long.byte 0xFC 0.--3. 1. "STATUS,STATUS" repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) group.long ($2+0x42E0)++0x3 line.long 0x0 "RGX_CR_USC_CLEAR_REGISTER4_$1,RGX_CR_USC_CLEAR_REGISTER4_0" hexmask.long 0x0 0.--31. 1. "VAL,Clear Colour register 4" repeat.end repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) group.long ($2+0x42E8)++0x3 line.long 0x0 "RGX_CR_USC_CLEAR_REGISTER5_$1,RGX_CR_USC_CLEAR_REGISTER5_0" hexmask.long 0x0 0.--31. 1. "VAL,Clear Colour register 5" repeat.end repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) group.long ($2+0x42F0)++0x3 line.long 0x0 "RGX_CR_USC_CLEAR_REGISTER6_$1,RGX_CR_USC_CLEAR_REGISTER6_0" hexmask.long 0x0 0.--31. 1. "VAL,Clear Colour register 6" repeat.end repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) group.long ($2+0x42F8)++0x3 line.long 0x0 "RGX_CR_USC_CLEAR_REGISTER7_$1,RGX_CR_USC_CLEAR_REGISTER7_0" hexmask.long 0x0 0.--31. 1. "VAL,Clear Colour register 7" repeat.end rgroup.long 0x4300++0xFF line.long 0x0 "RGX_CR_USC_SLOT32_0,RGX_CR_USC_SLOT32_0" hexmask.long 0x0 1.--31. 1. "PC,PC" newline bitfld.long 0x0 0. "Reserved_0,Reserved_0" "0,1" line.long 0x4 "RGX_CR_USC_SLOT32_1,RGX_CR_USC_SLOT32_1" hexmask.long 0x4 4.--31. 1. "Reserved_36,Reserved_36" newline hexmask.long.byte 0x4 0.--3. 1. "STATUS,STATUS" line.long 0x8 "RGX_CR_USC_SLOT33_0,RGX_CR_USC_SLOT33_0" hexmask.long 0x8 1.--31. 1. "PC,PC" newline bitfld.long 0x8 0. "Reserved_0,Reserved_0" "0,1" line.long 0xC "RGX_CR_USC_SLOT33_1,RGX_CR_USC_SLOT33_1" hexmask.long 0xC 4.--31. 1. "Reserved_36,Reserved_36" newline hexmask.long.byte 0xC 0.--3. 1. "STATUS,STATUS" line.long 0x10 "RGX_CR_USC_SLOT34_0,RGX_CR_USC_SLOT34_0" hexmask.long 0x10 1.--31. 1. "PC,PC" newline bitfld.long 0x10 0. "Reserved_0,Reserved_0" "0,1" line.long 0x14 "RGX_CR_USC_SLOT34_1,RGX_CR_USC_SLOT34_1" hexmask.long 0x14 4.--31. 1. "Reserved_36,Reserved_36" newline hexmask.long.byte 0x14 0.--3. 1. "STATUS,STATUS" line.long 0x18 "RGX_CR_USC_SLOT35_0,RGX_CR_USC_SLOT35_0" hexmask.long 0x18 1.--31. 1. "PC,PC" newline bitfld.long 0x18 0. "Reserved_0,Reserved_0" "0,1" line.long 0x1C "RGX_CR_USC_SLOT35_1,RGX_CR_USC_SLOT35_1" hexmask.long 0x1C 4.--31. 1. "Reserved_36,Reserved_36" newline hexmask.long.byte 0x1C 0.--3. 1. "STATUS,STATUS" line.long 0x20 "RGX_CR_USC_SLOT36_0,RGX_CR_USC_SLOT36_0" hexmask.long 0x20 1.--31. 1. "PC,PC" newline bitfld.long 0x20 0. "Reserved_0,Reserved_0" "0,1" line.long 0x24 "RGX_CR_USC_SLOT36_1,RGX_CR_USC_SLOT36_1" hexmask.long 0x24 4.--31. 1. "Reserved_36,Reserved_36" newline hexmask.long.byte 0x24 0.--3. 1. "STATUS,STATUS" line.long 0x28 "RGX_CR_USC_SLOT37_0,RGX_CR_USC_SLOT37_0" hexmask.long 0x28 1.--31. 1. "PC,PC" newline bitfld.long 0x28 0. "Reserved_0,Reserved_0" "0,1" line.long 0x2C "RGX_CR_USC_SLOT37_1,RGX_CR_USC_SLOT37_1" hexmask.long 0x2C 4.--31. 1. "Reserved_36,Reserved_36" newline hexmask.long.byte 0x2C 0.--3. 1. "STATUS,STATUS" line.long 0x30 "RGX_CR_USC_SLOT38_0,RGX_CR_USC_SLOT38_0" hexmask.long 0x30 1.--31. 1. "PC,PC" newline bitfld.long 0x30 0. "Reserved_0,Reserved_0" "0,1" line.long 0x34 "RGX_CR_USC_SLOT38_1,RGX_CR_USC_SLOT38_1" hexmask.long 0x34 4.--31. 1. "Reserved_36,Reserved_36" newline hexmask.long.byte 0x34 0.--3. 1. "STATUS,STATUS" line.long 0x38 "RGX_CR_USC_SLOT39_0,RGX_CR_USC_SLOT39_0" hexmask.long 0x38 1.--31. 1. "PC,PC" newline bitfld.long 0x38 0. "Reserved_0,Reserved_0" "0,1" line.long 0x3C "RGX_CR_USC_SLOT39_1,RGX_CR_USC_SLOT39_1" hexmask.long 0x3C 4.--31. 1. "Reserved_36,Reserved_36" newline hexmask.long.byte 0x3C 0.--3. 1. "STATUS,STATUS" line.long 0x40 "RGX_CR_USC_SLOT40_0,RGX_CR_USC_SLOT40_0" hexmask.long 0x40 1.--31. 1. "PC,PC" newline bitfld.long 0x40 0. "Reserved_0,Reserved_0" "0,1" line.long 0x44 "RGX_CR_USC_SLOT40_1,RGX_CR_USC_SLOT40_1" hexmask.long 0x44 4.--31. 1. "Reserved_36,Reserved_36" newline hexmask.long.byte 0x44 0.--3. 1. "STATUS,STATUS" line.long 0x48 "RGX_CR_USC_SLOT41_0,RGX_CR_USC_SLOT41_0" hexmask.long 0x48 1.--31. 1. "PC,PC" newline bitfld.long 0x48 0. "Reserved_0,Reserved_0" "0,1" line.long 0x4C "RGX_CR_USC_SLOT41_1,RGX_CR_USC_SLOT41_1" hexmask.long 0x4C 4.--31. 1. "Reserved_36,Reserved_36" newline hexmask.long.byte 0x4C 0.--3. 1. "STATUS,STATUS" line.long 0x50 "RGX_CR_USC_SLOT42_0,RGX_CR_USC_SLOT42_0" hexmask.long 0x50 1.--31. 1. "PC,PC" newline bitfld.long 0x50 0. "Reserved_0,Reserved_0" "0,1" line.long 0x54 "RGX_CR_USC_SLOT42_1,RGX_CR_USC_SLOT42_1" hexmask.long 0x54 4.--31. 1. "Reserved_36,Reserved_36" newline hexmask.long.byte 0x54 0.--3. 1. "STATUS,STATUS" line.long 0x58 "RGX_CR_USC_SLOT43_0,RGX_CR_USC_SLOT43_0" hexmask.long 0x58 1.--31. 1. "PC,PC" newline bitfld.long 0x58 0. "Reserved_0,Reserved_0" "0,1" line.long 0x5C "RGX_CR_USC_SLOT43_1,RGX_CR_USC_SLOT43_1" hexmask.long 0x5C 4.--31. 1. "Reserved_36,Reserved_36" newline hexmask.long.byte 0x5C 0.--3. 1. "STATUS,STATUS" line.long 0x60 "RGX_CR_USC_SLOT44_0,RGX_CR_USC_SLOT44_0" hexmask.long 0x60 1.--31. 1. "PC,PC" newline bitfld.long 0x60 0. "Reserved_0,Reserved_0" "0,1" line.long 0x64 "RGX_CR_USC_SLOT44_1,RGX_CR_USC_SLOT44_1" hexmask.long 0x64 4.--31. 1. "Reserved_36,Reserved_36" newline hexmask.long.byte 0x64 0.--3. 1. "STATUS,STATUS" line.long 0x68 "RGX_CR_USC_SLOT45_0,RGX_CR_USC_SLOT45_0" hexmask.long 0x68 1.--31. 1. "PC,PC" newline bitfld.long 0x68 0. "Reserved_0,Reserved_0" "0,1" line.long 0x6C "RGX_CR_USC_SLOT45_1,RGX_CR_USC_SLOT45_1" hexmask.long 0x6C 4.--31. 1. "Reserved_36,Reserved_36" newline hexmask.long.byte 0x6C 0.--3. 1. "STATUS,STATUS" line.long 0x70 "RGX_CR_USC_SLOT46_0,RGX_CR_USC_SLOT46_0" hexmask.long 0x70 1.--31. 1. "PC,PC" newline bitfld.long 0x70 0. "Reserved_0,Reserved_0" "0,1" line.long 0x74 "RGX_CR_USC_SLOT46_1,RGX_CR_USC_SLOT46_1" hexmask.long 0x74 4.--31. 1. "Reserved_36,Reserved_36" newline hexmask.long.byte 0x74 0.--3. 1. "STATUS,STATUS" line.long 0x78 "RGX_CR_USC_SLOT47_0,RGX_CR_USC_SLOT47_0" hexmask.long 0x78 1.--31. 1. "PC,PC" newline bitfld.long 0x78 0. "Reserved_0,Reserved_0" "0,1" line.long 0x7C "RGX_CR_USC_SLOT47_1,RGX_CR_USC_SLOT47_1" hexmask.long 0x7C 4.--31. 1. "Reserved_36,Reserved_36" newline hexmask.long.byte 0x7C 0.--3. 1. "STATUS,STATUS" line.long 0x80 "RGX_CR_USC_SLOT48_0,RGX_CR_USC_SLOT48_0" hexmask.long 0x80 1.--31. 1. "PC,PC" newline bitfld.long 0x80 0. "Reserved_0,Reserved_0" "0,1" line.long 0x84 "RGX_CR_USC_SLOT48_1,RGX_CR_USC_SLOT48_1" hexmask.long 0x84 4.--31. 1. "Reserved_36,Reserved_36" newline hexmask.long.byte 0x84 0.--3. 1. "STATUS,STATUS" line.long 0x88 "RGX_CR_USC_SLOT49_0,RGX_CR_USC_SLOT49_0" hexmask.long 0x88 1.--31. 1. "PC,PC" newline bitfld.long 0x88 0. "Reserved_0,Reserved_0" "0,1" line.long 0x8C "RGX_CR_USC_SLOT49_1,RGX_CR_USC_SLOT49_1" hexmask.long 0x8C 4.--31. 1. "Reserved_36,Reserved_36" newline hexmask.long.byte 0x8C 0.--3. 1. "STATUS,STATUS" line.long 0x90 "RGX_CR_USC_SLOT50_0,RGX_CR_USC_SLOT50_0" hexmask.long 0x90 1.--31. 1. "PC,PC" newline bitfld.long 0x90 0. "Reserved_0,Reserved_0" "0,1" line.long 0x94 "RGX_CR_USC_SLOT50_1,RGX_CR_USC_SLOT50_1" hexmask.long 0x94 4.--31. 1. "Reserved_36,Reserved_36" newline hexmask.long.byte 0x94 0.--3. 1. "STATUS,STATUS" line.long 0x98 "RGX_CR_USC_SLOT51_0,RGX_CR_USC_SLOT51_0" hexmask.long 0x98 1.--31. 1. "PC,PC" newline bitfld.long 0x98 0. "Reserved_0,Reserved_0" "0,1" line.long 0x9C "RGX_CR_USC_SLOT51_1,RGX_CR_USC_SLOT51_1" hexmask.long 0x9C 4.--31. 1. "Reserved_36,Reserved_36" newline hexmask.long.byte 0x9C 0.--3. 1. "STATUS,STATUS" line.long 0xA0 "RGX_CR_USC_SLOT52_0,RGX_CR_USC_SLOT52_0" hexmask.long 0xA0 1.--31. 1. "PC,PC" newline bitfld.long 0xA0 0. "Reserved_0,Reserved_0" "0,1" line.long 0xA4 "RGX_CR_USC_SLOT52_1,RGX_CR_USC_SLOT52_1" hexmask.long 0xA4 4.--31. 1. "Reserved_36,Reserved_36" newline hexmask.long.byte 0xA4 0.--3. 1. "STATUS,STATUS" line.long 0xA8 "RGX_CR_USC_SLOT53_0,RGX_CR_USC_SLOT53_0" hexmask.long 0xA8 1.--31. 1. "PC,PC" newline bitfld.long 0xA8 0. "Reserved_0,Reserved_0" "0,1" line.long 0xAC "RGX_CR_USC_SLOT53_1,RGX_CR_USC_SLOT53_1" hexmask.long 0xAC 4.--31. 1. "Reserved_36,Reserved_36" newline hexmask.long.byte 0xAC 0.--3. 1. "STATUS,STATUS" line.long 0xB0 "RGX_CR_USC_SLOT54_0,RGX_CR_USC_SLOT54_0" hexmask.long 0xB0 1.--31. 1. "PC,PC" newline bitfld.long 0xB0 0. "Reserved_0,Reserved_0" "0,1" line.long 0xB4 "RGX_CR_USC_SLOT54_1,RGX_CR_USC_SLOT54_1" hexmask.long 0xB4 4.--31. 1. "Reserved_36,Reserved_36" newline hexmask.long.byte 0xB4 0.--3. 1. "STATUS,STATUS" line.long 0xB8 "RGX_CR_USC_SLOT55_0,RGX_CR_USC_SLOT55_0" hexmask.long 0xB8 1.--31. 1. "PC,PC" newline bitfld.long 0xB8 0. "Reserved_0,Reserved_0" "0,1" line.long 0xBC "RGX_CR_USC_SLOT55_1,RGX_CR_USC_SLOT55_1" hexmask.long 0xBC 4.--31. 1. "Reserved_36,Reserved_36" newline hexmask.long.byte 0xBC 0.--3. 1. "STATUS,STATUS" line.long 0xC0 "RGX_CR_USC_SLOT56_0,RGX_CR_USC_SLOT56_0" hexmask.long 0xC0 1.--31. 1. "PC,PC" newline bitfld.long 0xC0 0. "Reserved_0,Reserved_0" "0,1" line.long 0xC4 "RGX_CR_USC_SLOT56_1,RGX_CR_USC_SLOT56_1" hexmask.long 0xC4 4.--31. 1. "Reserved_36,Reserved_36" newline hexmask.long.byte 0xC4 0.--3. 1. "STATUS,STATUS" line.long 0xC8 "RGX_CR_USC_SLOT57_0,RGX_CR_USC_SLOT57_0" hexmask.long 0xC8 1.--31. 1. "PC,PC" newline bitfld.long 0xC8 0. "Reserved_0,Reserved_0" "0,1" line.long 0xCC "RGX_CR_USC_SLOT57_1,RGX_CR_USC_SLOT57_1" hexmask.long 0xCC 4.--31. 1. "Reserved_36,Reserved_36" newline hexmask.long.byte 0xCC 0.--3. 1. "STATUS,STATUS" line.long 0xD0 "RGX_CR_USC_SLOT58_0,RGX_CR_USC_SLOT58_0" hexmask.long 0xD0 1.--31. 1. "PC,PC" newline bitfld.long 0xD0 0. "Reserved_0,Reserved_0" "0,1" line.long 0xD4 "RGX_CR_USC_SLOT58_1,RGX_CR_USC_SLOT58_1" hexmask.long 0xD4 4.--31. 1. "Reserved_36,Reserved_36" newline hexmask.long.byte 0xD4 0.--3. 1. "STATUS,STATUS" line.long 0xD8 "RGX_CR_USC_SLOT59_0,RGX_CR_USC_SLOT59_0" hexmask.long 0xD8 1.--31. 1. "PC,PC" newline bitfld.long 0xD8 0. "Reserved_0,Reserved_0" "0,1" line.long 0xDC "RGX_CR_USC_SLOT59_1,RGX_CR_USC_SLOT59_1" hexmask.long 0xDC 4.--31. 1. "Reserved_36,Reserved_36" newline hexmask.long.byte 0xDC 0.--3. 1. "STATUS,STATUS" line.long 0xE0 "RGX_CR_USC_SLOT60_0,RGX_CR_USC_SLOT60_0" hexmask.long 0xE0 1.--31. 1. "PC,PC" newline bitfld.long 0xE0 0. "Reserved_0,Reserved_0" "0,1" line.long 0xE4 "RGX_CR_USC_SLOT60_1,RGX_CR_USC_SLOT60_1" hexmask.long 0xE4 4.--31. 1. "Reserved_36,Reserved_36" newline hexmask.long.byte 0xE4 0.--3. 1. "STATUS,STATUS" line.long 0xE8 "RGX_CR_USC_SLOT61_0,RGX_CR_USC_SLOT61_0" hexmask.long 0xE8 1.--31. 1. "PC,PC" newline bitfld.long 0xE8 0. "Reserved_0,Reserved_0" "0,1" line.long 0xEC "RGX_CR_USC_SLOT61_1,RGX_CR_USC_SLOT61_1" hexmask.long 0xEC 4.--31. 1. "Reserved_36,Reserved_36" newline hexmask.long.byte 0xEC 0.--3. 1. "STATUS,STATUS" line.long 0xF0 "RGX_CR_USC_SLOT62_0,RGX_CR_USC_SLOT62_0" hexmask.long 0xF0 1.--31. 1. "PC,PC" newline bitfld.long 0xF0 0. "Reserved_0,Reserved_0" "0,1" line.long 0xF4 "RGX_CR_USC_SLOT62_1,RGX_CR_USC_SLOT62_1" hexmask.long 0xF4 4.--31. 1. "Reserved_36,Reserved_36" newline hexmask.long.byte 0xF4 0.--3. 1. "STATUS,STATUS" line.long 0xF8 "RGX_CR_USC_SLOT63_0,RGX_CR_USC_SLOT63_0" hexmask.long 0xF8 1.--31. 1. "PC,PC" newline bitfld.long 0xF8 0. "Reserved_0,Reserved_0" "0,1" line.long 0xFC "RGX_CR_USC_SLOT63_1,RGX_CR_USC_SLOT63_1" hexmask.long 0xFC 4.--31. 1. "Reserved_36,Reserved_36" newline hexmask.long.byte 0xFC 0.--3. 1. "STATUS,STATUS" group.long 0x4500++0x17 line.long 0x0 "RGX_CR_USC_BREAKPOINT1_0,RGX_CR_USC_BREAKPOINT1_0" hexmask.long 0x0 1.--31. 1. "ADDR,Breakpoint Address" newline bitfld.long 0x0 0. "Reserved_0,Reserved_0" "0,1" line.long 0x4 "RGX_CR_USC_BREAKPOINT1_1,RGX_CR_USC_BREAKPOINT1_1" hexmask.long 0x4 0.--31. 1. "Reserved_32,Reserved_32" line.long 0x8 "RGX_CR_USC_BREAKPOINT1_HANDLER_0,RGX_CR_USC_BREAKPOINT1_HANDLER_0" hexmask.long 0x8 1.--31. 1. "ADDR,Breakpoint Handler Address" newline bitfld.long 0x8 0. "Reserved_0,Reserved_0" "0,1" line.long 0xC "RGX_CR_USC_BREAKPOINT1_HANDLER_1,RGX_CR_USC_BREAKPOINT1_HANDLER_1" hexmask.long 0xC 0.--31. 1. "Reserved_32,Reserved_32" line.long 0x10 "RGX_CR_USC_BREAKPOINT1_CTRL_0,RGX_CR_USC_BREAKPOINT1_CTRL_0" hexmask.long 0x10 4.--31. 1. "Reserved_4,Reserved_4" newline bitfld.long 0x10 3. "ENABLE,0 = Breakpoint disabled 1 = Breakpoint enabled" "Breakpoint disabled,Breakpoint enabled" newline bitfld.long 0x10 0.--2. "DM,Data Master of Breakpoint" "0,1,2,3,4,5,6,7" line.long 0x14 "RGX_CR_USC_BREAKPOINT1_CTRL_1,RGX_CR_USC_BREAKPOINT1_CTRL_1" hexmask.long 0x14 0.--31. 1. "Reserved_4,Reserved_4" rgroup.long 0x45D8++0x7 line.long 0x0 "RGX_CR_USC_IDLE_0,RGX_CR_USC_IDLE_0" hexmask.long.tbyte 0x0 10.--31. 1. "Reserved_10,Reserved_10" newline bitfld.long 0x0 9. "USCITR,USCITR idle" "0,1" newline bitfld.long 0x0 8. "USCDMA,USCDMA idle" "0,1" newline bitfld.long 0x0 7. "USCFS,USCFS idle" "0,1" newline bitfld.long 0x0 6. "USCCS,USCCS idle" "0,1" newline bitfld.long 0x0 5. "USCPD3,USCPD idle" "0,1" newline bitfld.long 0x0 4. "USCPD2,USCPD idle" "0,1" newline bitfld.long 0x0 3. "USCPD1,USCPD idle" "0,1" newline bitfld.long 0x0 2. "USCPD0,USCPD idle" "0,1" newline bitfld.long 0x0 1. "USCPC,USCPC idle" "0,1" newline bitfld.long 0x0 0. "USCC,USCC idle" "0,1" line.long 0x4 "RGX_CR_USC_IDLE_1,RGX_CR_USC_IDLE_1" hexmask.long 0x4 0.--31. 1. "Reserved_10,Reserved_10" group.long 0x45E8++0x17 line.long 0x0 "RGX_CR_USC_ITRCOEFF_CACHE_0,USC Iterator Coefficient Cache Bypass bit" hexmask.long 0x0 1.--31. 1. "Reserved_1,Reserved_1" newline bitfld.long 0x0 0. "BYPASS,Bypass bit of the coefficient cache" "0,1" line.long 0x4 "RGX_CR_USC_ITRCOEFF_CACHE_1,USC Iterator Coefficient Cache Bypass bit" hexmask.long 0x4 0.--31. 1. "Reserved_1,Reserved_1" line.long 0x8 "RGX_CR_USC_ITRSMP_STATE_CACHE_0,USC ITRSMP State Cache Bypass bit" hexmask.long 0x8 1.--31. 1. "Reserved_1,Reserved_1" newline bitfld.long 0x8 0. "BYPASS,Bypass bit of the state cache" "0,1" line.long 0xC "RGX_CR_USC_ITRSMP_STATE_CACHE_1,USC ITRSMP State Cache Bypass bit" hexmask.long 0xC 0.--31. 1. "Reserved_1,Reserved_1" line.long 0x10 "RGX_CR_USC_ITRSMP_PRIORITY_0,USC ITRSMP priority information" hexmask.long 0x10 2.--31. 1. "Reserved_2,Reserved_2" newline bitfld.long 0x10 0.--1. "PERSISTENCE,Persistence value to use for ITRSMP instructions." "0,1,2,3" line.long 0x14 "RGX_CR_USC_ITRSMP_PRIORITY_1,USC ITRSMP priority information" hexmask.long 0x14 0.--31. 1. "Reserved_2,Reserved_2" repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) rgroup.long ($2+0x4600)++0x3 line.long 0x0 "RGX_CR_USC_PWR_INSTR_$1,Peformance counter associated with Power Monitoring" hexmask.long 0x0 0.--31. 1. "EXEC,Number of instructions executed (max 1 per clock)" repeat.end repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) rgroup.long ($2+0x4608)++0x3 line.long 0x0 "RGX_CR_USC_PWR_CMMN_STR_ACCESS_$1,Peformance counter associated with Power Monitoring" hexmask.long 0x0 0.--31. 1. "COUNT,Number of Common Store accesses (max of 4 per lock)" repeat.end repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) rgroup.long ($2+0x4610)++0x3 line.long 0x0 "RGX_CR_USC_PWR_CMMN_STR_$1,Peformance counter associated with Power Monitoring" hexmask.long 0x0 0.--31. 1. "WR_BANK_CLASH,Common Store: Number of write/write bank clashes" repeat.end repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) rgroup.long ($2+0x4618)++0x3 line.long 0x0 "RGX_CR_USC_PWR_UNI_STR_$1,Peformance counter associated with Power Monitoring" hexmask.long 0x0 0.--31. 1. "WR_BANK_CLASH,Unified Store: Number of write/write bank clashes" repeat.end repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) rgroup.long ($2+0x4620)++0x3 line.long 0x0 "RGX_CR_USC_PWR_NUM_FLOAT_$1,Peformance counter associated with Power Monitoring" hexmask.long 0x0 0.--31. 1. "OPS,Number of floating point ops; FAdd/Fmul=1 MAD=2; max 32x2=64 per clock" repeat.end repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) rgroup.long ($2+0x4628)++0x3 line.long 0x0 "RGX_CR_USC_PWR_NUM_INTEGER_$1,Peformance counter associated with Power Monitoring" hexmask.long 0x0 0.--31. 1. "OPS,Number of integer ops; Add/Mul=1 MAD=2 max 16*2=32 per clock" repeat.end repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) rgroup.long ($2+0x4630)++0x3 line.long 0x0 "RGX_CR_USC_PWR_NUM_COALU_$1,Peformance counter associated with Power Monitoring" hexmask.long 0x0 0.--31. 1. "OPS,Number of COALU ops; max of 16 per clock" repeat.end repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) rgroup.long ($2+0x4638)++0x3 line.long 0x0 "RGX_CR_USC_PWR_NUM_$1,Peformance counter associated with Power Monitoring" hexmask.long 0x0 0.--31. 1. "PENALTY_CYCLES,Penalty cycles for read/read and write/write clashes. For each instruction this is max(a b c d)" repeat.end repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) rgroup.long ($2+0x4640)++0x3 line.long 0x0 "RGX_CR_USC_PWR_AV_NUM_INST_VALID_$1,Peformance counter associated with Power Monitoring" hexmask.long 0x0 0.--31. 1. "VERT,Average number of instances valid out of 16 for vertex tasks" repeat.end repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) rgroup.long ($2+0x4648)++0x3 line.long 0x0 "RGX_CR_USC_PWR_NUM_ON_EDGE_PIXL_$1,Peformance counter associated with Power Monitoring" hexmask.long 0x0 0.--31. 1. "WRITE,Number of on-edge pixel output register writes" repeat.end repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) rgroup.long ($2+0x4650)++0x3 line.long 0x0 "RGX_CR_USC_PWR_NUM_OFF_EDGE_PIXL_$1,Peformance counter associated with Power Monitoring" hexmask.long 0x0 0.--31. 1. "WRITE,Number of off-edge pixel output register writes" repeat.end repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) rgroup.long ($2+0x4658)++0x3 line.long 0x0 "RGX_CR_USC_PWR_NUM_F16_$1,Peformance counter associated with Power Monitoring" hexmask.long 0x0 0.--31. 1. "OPS,Number of F16 operations. Max of 16" repeat.end repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) rgroup.long ($2+0x4660)++0x3 line.long 0x0 "RGX_CR_USC_PWR_USCPD_INSTR_$1,Peformance counter associated with Power Monitoring" hexmask.long 0x0 0.--31. 1. "COUNT,Number of instructions executed by USCPD" repeat.end repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) rgroup.long ($2+0x4668)++0x3 line.long 0x0 "RGX_CR_USC_PWR_INT_REG_ACCESS_$1,Peformance counter associated with Power Monitoring" hexmask.long 0x0 0.--31. 1. "COUNT,Number of internal register accesses. Max 128 per clock = 8 registers * 16 instances" repeat.end repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) rgroup.long ($2+0x4670)++0x3 line.long 0x0 "RGX_CR_USC_PWR_US_STR_ACCESS_$1,Peformance counter associated with Power Monitoring" hexmask.long 0x0 0.--31. 1. "COUNT,Number of unified sotre US bank accesses. Max of 32 per clock = 8 banks * 4 pipes" repeat.end group.long 0x4678++0x7 line.long 0x0 "RGX_CR_USC_HQ_RESCH_0,Disable rescheduling of slots in USCPC HQ" hexmask.long 0x0 2.--31. 1. "Reserved_2,Reserved_2" newline bitfld.long 0x0 1. "DISABLE_FOR_BE,Disable rescheduling for BE instr in USCPC" "0,1" newline bitfld.long 0x0 0. "DISABLE,Disable rescheduling in USCPC" "0,1" line.long 0x4 "RGX_CR_USC_HQ_RESCH_1,Disable rescheduling of slots in USCPC HQ" hexmask.long 0x4 0.--31. 1. "Reserved_2,Reserved_2" repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) rgroup.long ($2+0x5000)++0x3 line.long 0x0 "RGX_CR_USC_UVS0_CHECKSUM_$1,RGX_CR_USC_UVS0_CHECKSUM_0" hexmask.long 0x0 0.--31. 1. "VALUE,Checksum of USC to UVS writes from USC0" repeat.end repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) rgroup.long ($2+0x5008)++0x3 line.long 0x0 "RGX_CR_USC_UVS1_CHECKSUM_$1,RGX_CR_USC_UVS1_CHECKSUM_0" hexmask.long 0x0 0.--31. 1. "VALUE,Checksum of USC to UVS writes from USC1" repeat.end repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) rgroup.long ($2+0x5010)++0x3 line.long 0x0 "RGX_CR_USC_UVS2_CHECKSUM_$1,RGX_CR_USC_UVS2_CHECKSUM_0" hexmask.long 0x0 0.--31. 1. "VALUE,Checksum of USC to UVS writes from USC2" repeat.end repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) rgroup.long ($2+0x5018)++0x3 line.long 0x0 "RGX_CR_USC_UVS3_CHECKSUM_$1,RGX_CR_USC_UVS3_CHECKSUM_0" hexmask.long 0x0 0.--31. 1. "VALUE,Checksum of USC to UVS writes from USC3" repeat.end repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) rgroup.long ($2+0x5020)++0x3 line.long 0x0 "RGX_CR_PPP_SIGNATURE_$1,RGX_CR_PPP_SIGNATURE_0" hexmask.long 0x0 0.--31. 1. "VALUE,Signature of PPP to Clipper Interface" repeat.end repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) rgroup.long ($2+0x5028)++0x3 line.long 0x0 "RGX_CR_TE_SIGNATURE_$1,RGX_CR_TE_SIGNATURE_0" hexmask.long 0x0 0.--31. 1. "VALUE,Signature of TE control stream writes" repeat.end repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) rgroup.long ($2+0x5030)++0x3 line.long 0x0 "RGX_CR_VCE_CHECKSUM_$1,RGX_CR_VCE_CHECKSUM_0" hexmask.long 0x0 0.--31. 1. "VALUE,Checksum of VCE memory writes" repeat.end repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) rgroup.long ($2+0x5038)++0x3 line.long 0x0 "RGX_CR_ISP_PDS_CHECKSUM_$1,RGX_CR_ISP_PDS_CHECKSUM_0" hexmask.long 0x0 0.--31. 1. "VALUE,Checksum of ISP PDS Span Output" repeat.end repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) rgroup.long ($2+0x5040)++0x3 line.long 0x0 "RGX_CR_ISP_TPF_CHECKSUM_$1,RGX_CR_ISP_TPF_CHECKSUM_0" hexmask.long 0x0 0.--31. 1. "VALUE,Checksum of ISP TPF Object Output" repeat.end repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) rgroup.long ($2+0x5048)++0x3 line.long 0x0 "RGX_CR_TFPU_PLANE0_CHECKSUM_$1,RGX_CR_TFPU_PLANE0_CHECKSUM_0" hexmask.long 0x0 0.--31. 1. "VALUE,Checksum of TFPU Plane0 Output" repeat.end repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) rgroup.long ($2+0x5050)++0x3 line.long 0x0 "RGX_CR_TFPU_PLANE1_CHECKSUM_$1,RGX_CR_TFPU_PLANE1_CHECKSUM_0" hexmask.long 0x0 0.--31. 1. "VALUE,Checksum of TFPU Plane1 Output" repeat.end repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) rgroup.long ($2+0x5058)++0x3 line.long 0x0 "RGX_CR_PBE_CHECKSUM_$1,RGX_CR_PBE_CHECKSUM_0" hexmask.long 0x0 0.--31. 1. "VALUE,Checksum of PBE memory writes" repeat.end repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) rgroup.long ($2+0x5060)++0x3 line.long 0x0 "RGX_CR_PDS_DOUTM_STM_SIGNATURE_$1,RGX_CR_PDS_DOUTM_STM_SIGNATURE_0" hexmask.long 0x0 0.--31. 1. "VALUE,Signature of PDS DOUTM Stream Out MCU writes" repeat.end repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) rgroup.long ($2+0x5068)++0x3 line.long 0x0 "RGX_CR_IFPU_ISP_CHECKSUM_$1,RGX_CR_IFPU_ISP_CHECKSUM_0" hexmask.long 0x0 0.--31. 1. "VALUE,Checksum of IFPU Output" repeat.end repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) rgroup.long ($2+0x5070)++0x3 line.long 0x0 "RGX_CR_MCU_L0_TA_CHECKSUM_$1,RGX_CR_MCU_L0_TA_CHECKSUM_0" hexmask.long 0x0 0.--31. 1. "VALUE,Checksum of the PDS->USC from MCU for TA data" repeat.end repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) rgroup.long ($2+0x5078)++0x3 line.long 0x0 "RGX_CR_MCU_L0_3D_CHECKSUM_$1,RGX_CR_MCU_L0_3D_CHECKSUM_0" hexmask.long 0x0 0.--31. 1. "VALUE,Checksum of the PDS->USC from MCU for 3D data" repeat.end repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) rgroup.long ($2+0x5080)++0x3 line.long 0x0 "RGX_CR_MCU_L0_WRAP_TA_CHECKSUM_$1,RGX_CR_MCU_L0_WRAP_TA_CHECKSUM_0" hexmask.long 0x0 0.--31. 1. "VALUE,Checksum of the PDS->USC from MCU for TA data" repeat.end repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) rgroup.long ($2+0x5088)++0x3 line.long 0x0 "RGX_CR_MCU_L0_WRAP_3D_CHECKSUM_$1,RGX_CR_MCU_L0_WRAP_3D_CHECKSUM_0" hexmask.long 0x0 0.--31. 1. "VALUE,Checksum of the PDS->USC from MCU for 3D data" repeat.end repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) rgroup.long ($2+0x5100)++0x3 line.long 0x0 "RGX_CR_USC_UVS4_CHECKSUM_$1,RGX_CR_USC_UVS4_CHECKSUM_0" hexmask.long 0x0 0.--31. 1. "VALUE,Checksum of USC to UVS writes from USC4" repeat.end repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) rgroup.long ($2+0x5108)++0x3 line.long 0x0 "RGX_CR_USC_UVS5_CHECKSUM_$1,RGX_CR_USC_UVS5_CHECKSUM_0" hexmask.long 0x0 0.--31. 1. "VALUE,Checksum of USC to UVS writes from USC5" repeat.end repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) rgroup.long ($2+0x5148)++0x3 line.long 0x0 "RGX_CR_TDM_PDS_CHECKSUM_$1,RGX_CR_TDM_PDS_CHECKSUM_0" hexmask.long 0x0 0.--31. 1. "VALUE,Checksum of all TDM to PDS tile emits." repeat.end repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) rgroup.long ($2+0x5160)++0x3 line.long 0x0 "RGX_CR_PBE_CHECKSUM_NO_ADDR_$1,RGX_CR_PBE_CHECKSUM_NO_ADDR_0" hexmask.long 0x0 0.--31. 1. "VALUE,No address checksum of PBE memory writes" repeat.end repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) rgroup.long ($2+0x5200)++0x3 line.long 0x0 "RGX_CR_PBE_CHECKSUM_TDM_$1,RGX_CR_PBE_CHECKSUM_TDM_0" hexmask.long 0x0 0.--31. 1. "VALUE,TDM checksum of PBE memory writes" repeat.end repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) rgroup.long ($2+0x5208)++0x3 line.long 0x0 "RGX_CR_PBE_CHECKSUM_TDM_NO_ADDR_$1,RGX_CR_PBE_CHECKSUM_TDM_NO_ADDR_0" hexmask.long 0x0 0.--31. 1. "VALUE,No address TDM checksum of PBE memory writes" repeat.end group.long 0x6000++0x7 line.long 0x0 "RGX_CR_PERF_COUNTER_0,RGX_CR_PERF_COUNTER_0" hexmask.long 0x0 1.--31. 1. "Reserved_1,Reserved_1" newline bitfld.long 0x0 0. "RESET,A write of 1 to this register resets the Cycle Counters and holds them in Reset. A write of 0 enables them for Counting" "0,1" line.long 0x4 "RGX_CR_PERF_COUNTER_1,RGX_CR_PERF_COUNTER_1" hexmask.long 0x4 0.--31. 1. "Reserved_1,Reserved_1" repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) rgroup.long ($2+0x6008)++0x3 line.long 0x0 "RGX_CR_PERF_TA_PHASE_$1,RGX_CR_PERF_TA_PHASE_0" hexmask.long 0x0 0.--31. 1. "COUNT,The number of TA phases completed" repeat.end repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) rgroup.long ($2+0x6010)++0x3 line.long 0x0 "RGX_CR_PERF_3D_PHASE_$1,RGX_CR_PERF_3D_PHASE_0" hexmask.long 0x0 0.--31. 1. "COUNT,The number of 3D phases completed" repeat.end repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) rgroup.long ($2+0x6018)++0x3 line.long 0x0 "RGX_CR_PERF_COMPUTE_PHASE_$1,RGX_CR_PERF_COMPUTE_PHASE_0" hexmask.long 0x0 0.--31. 1. "COUNT,The number of Compute phases completed" repeat.end repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) rgroup.long ($2+0x6020)++0x3 line.long 0x0 "RGX_CR_PERF_TA_CYCLE_$1,RGX_CR_PERF_TA_CYCLE_0" hexmask.long 0x0 0.--31. 1. "COUNT,The number of cycles spent in TA phases" repeat.end repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) rgroup.long ($2+0x6028)++0x3 line.long 0x0 "RGX_CR_PERF_3D_CYCLE_$1,RGX_CR_PERF_3D_CYCLE_0" hexmask.long 0x0 0.--31. 1. "COUNT,The number of cycles spent in 3D phases" repeat.end repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) rgroup.long ($2+0x6030)++0x3 line.long 0x0 "RGX_CR_PERF_COMPUTE_CYCLE_$1,RGX_CR_PERF_COMPUTE_CYCLE_0" hexmask.long 0x0 0.--31. 1. "COUNT,The number of cycles spent in Compute phases" repeat.end repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) rgroup.long ($2+0x6038)++0x3 line.long 0x0 "RGX_CR_PERF_TA_OR_3D_CYCLE_$1,RGX_CR_PERF_TA_OR_3D_CYCLE_0" hexmask.long 0x0 0.--31. 1. "COUNT,The number of cycles spent in TA phases or 3D phases" repeat.end repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) rgroup.long ($2+0x6040)++0x3 line.long 0x0 "RGX_CR_PERF_INITIAL_TA_CYCLE_$1,RGX_CR_PERF_INITIAL_TA_CYCLE_0" hexmask.long 0x0 0.--31. 1. "COUNT,The number of cycles spent in TA phases before the first 3D phase" repeat.end repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) rgroup.long ($2+0x6048)++0x3 line.long 0x0 "RGX_CR_PERF_FINAL_3D_CYCLE_$1,RGX_CR_PERF_FINAL_3D_CYCLE_0" hexmask.long 0x0 0.--31. 1. "COUNT,The number of cycles spent in the last 3D phase" repeat.end repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) rgroup.long ($2+0x6050)++0x3 line.long 0x0 "RGX_CR_PERF_BIF0_READ_$1,RGX_CR_PERF_BIF0_READ_0" hexmask.long 0x0 0.--31. 1. "COUNT,The number of BIF0-to-SLC reads" repeat.end repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) rgroup.long ($2+0x6058)++0x3 line.long 0x0 "RGX_CR_PERF_BIF0_WRITE_$1,RGX_CR_PERF_BIF0_WRITE_0" hexmask.long 0x0 0.--31. 1. "COUNT,The number of BIF0-to-SLC writes" repeat.end repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) rgroup.long ($2+0x6060)++0x3 line.long 0x0 "RGX_CR_PERF_BIF0_BYTE_WRITE_$1,RGX_CR_PERF_BIF0_BYTE_WRITE_0" hexmask.long 0x0 0.--31. 1. "COUNT,The number of BIF0-to-SLC bytes written" repeat.end repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) rgroup.long ($2+0x6068)++0x3 line.long 0x0 "RGX_CR_PERF_BIF0_READ_STALL_$1,RGX_CR_PERF_BIF0_READ_STALL_0" hexmask.long 0x0 0.--31. 1. "COUNT,The number of BIF0-to-SLC read stalls" repeat.end repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) rgroup.long ($2+0x6070)++0x3 line.long 0x0 "RGX_CR_PERF_BIF0_WRITE_STALL_$1,RGX_CR_PERF_BIF0_WRITE_STALL_0" hexmask.long 0x0 0.--31. 1. "COUNT,The number of BIF0-to-SLC write stalls" repeat.end repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) rgroup.long ($2+0x60A0)++0x3 line.long 0x0 "RGX_CR_PERF_SLC0_READ_$1,RGX_CR_PERF_SLC0_READ_0" hexmask.long 0x0 0.--31. 1. "COUNT,The number of SLC-to-MEM interface 0 reads" repeat.end repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) rgroup.long ($2+0x60A8)++0x3 line.long 0x0 "RGX_CR_PERF_SLC0_WRITE_$1,RGX_CR_PERF_SLC0_WRITE_0" hexmask.long 0x0 0.--31. 1. "COUNT,The number of SLC-to-MEM interface 0 writes" repeat.end repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) rgroup.long ($2+0x60B0)++0x3 line.long 0x0 "RGX_CR_PERF_SLC0_BYTE_WRITE_$1,RGX_CR_PERF_SLC0_BYTE_WRITE_0" hexmask.long 0x0 0.--31. 1. "COUNT,The number of SLC-to-MEM interface 0 bytes written" repeat.end repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) rgroup.long ($2+0x60B8)++0x3 line.long 0x0 "RGX_CR_PERF_SLC0_READ_STALL_$1,RGX_CR_PERF_SLC0_READ_STALL_0" hexmask.long 0x0 0.--31. 1. "COUNT,The number of SLC-to-MEM interface 0 command stalls" repeat.end repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) rgroup.long ($2+0x60C0)++0x3 line.long 0x0 "RGX_CR_PERF_SLC0_WRITE_STALL_$1,RGX_CR_PERF_SLC0_WRITE_STALL_0" hexmask.long 0x0 0.--31. 1. "COUNT,The number of SLC-to-MEM insterface 0 write channel stalls" repeat.end repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) rgroup.long ($2+0x60C8)++0x3 line.long 0x0 "RGX_CR_PERF_SLC1_READ_$1,RGX_CR_PERF_SLC1_READ_0" hexmask.long 0x0 0.--31. 1. "COUNT,The number of SLC-to-MEM interface 1 reads" repeat.end repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) rgroup.long ($2+0x60D0)++0x3 line.long 0x0 "RGX_CR_PERF_SLC1_WRITE_$1,RGX_CR_PERF_SLC1_WRITE_0" hexmask.long 0x0 0.--31. 1. "COUNT,The number of SLC-to-MEM interface 1 writes" repeat.end repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) rgroup.long ($2+0x60D8)++0x3 line.long 0x0 "RGX_CR_PERF_SLC1_BYTE_WRITE_$1,RGX_CR_PERF_SLC1_BYTE_WRITE_0" hexmask.long 0x0 0.--31. 1. "COUNT,The number of SLC-to-MEM interface 1 bytes written" repeat.end repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) rgroup.long ($2+0x60E0)++0x3 line.long 0x0 "RGX_CR_PERF_SLC1_READ_STALL_$1,RGX_CR_PERF_SLC1_READ_STALL_0" hexmask.long 0x0 0.--31. 1. "COUNT,The number of SLC-to-MEM interface 1 command stalls" repeat.end repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) rgroup.long ($2+0x60E8)++0x3 line.long 0x0 "RGX_CR_PERF_SLC1_WRITE_STALL_$1,RGX_CR_PERF_SLC1_WRITE_STALL_0" hexmask.long 0x0 0.--31. 1. "COUNT,The number of SLC-to-MEM interface 1 write channel stalls" repeat.end repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) rgroup.long ($2+0x60F0)++0x3 line.long 0x0 "RGX_CR_PERF_SLC_BURST_SIZE0_IN_$1,RGX_CR_PERF_SLC_BURST_SIZE0_IN_0" hexmask.long 0x0 0.--31. 1. "VALUE,The number of burstlength 0 accesses into the Burst Combiner" repeat.end repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) rgroup.long ($2+0x60F8)++0x3 line.long 0x0 "RGX_CR_PERF_SLC_BURST_SIZE1_IN_$1,RGX_CR_PERF_SLC_BURST_SIZE1_IN_0" hexmask.long 0x0 0.--31. 1. "VALUE,The number of burstlength 1 accesses into the Burst Combiner" repeat.end repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) rgroup.long ($2+0x6100)++0x3 line.long 0x0 "RGX_CR_PERF_SLC_BURST_SIZE0_OUT_$1,RGX_CR_PERF_SLC_BURST_SIZE0_OUT_0" hexmask.long 0x0 0.--31. 1. "VALUE,The number of burstlength 0 accesses out of the Burst Combiner" repeat.end repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) rgroup.long ($2+0x6108)++0x3 line.long 0x0 "RGX_CR_PERF_SLC_BURST_SIZE1_OUT_$1,RGX_CR_PERF_SLC_BURST_SIZE1_OUT_0" hexmask.long 0x0 0.--31. 1. "VALUE,The number of burstlength 1 accesses out of the Burst Combiner" repeat.end repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) rgroup.long ($2+0x6110)++0x3 line.long 0x0 "RGX_CR_PERF_SLC_BURST_SIZE2_OUT_$1,RGX_CR_PERF_SLC_BURST_SIZE2_OUT_0" hexmask.long 0x0 0.--31. 1. "VALUE,The number of burstlength 2 accesses out of the Burst Combiner" repeat.end repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) rgroup.long ($2+0x6118)++0x3 line.long 0x0 "RGX_CR_PERF_SLC0_READ_ID_STALL_$1,RGX_CR_PERF_SLC0_READ_ID_STALL_0" hexmask.long 0x0 0.--31. 1. "COUNT,The number of cycles the SLC spends stalled because all Read IDs on memory interface 0 are currently in use" repeat.end repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) rgroup.long ($2+0x6120)++0x3 line.long 0x0 "RGX_CR_PERF_SLC0_WRITE_ID_STALL_$1,RGX_CR_PERF_SLC0_WRITE_ID_STALL_0" hexmask.long 0x0 0.--31. 1. "COUNT,The number of cycles the SLC spends stalled because all Write IDs on memory interface 0 are currently in use" repeat.end repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) rgroup.long ($2+0x6128)++0x3 line.long 0x0 "RGX_CR_PERF_SLC1_READ_ID_STALL_$1,RGX_CR_PERF_SLC1_READ_ID_STALL_0" hexmask.long 0x0 0.--31. 1. "COUNT,The number of cycles the SLC spends stalled because all Read IDs on memory interface 1 are currently in use" repeat.end repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) rgroup.long ($2+0x6130)++0x3 line.long 0x0 "RGX_CR_PERF_SLC1_WRITE_ID_STALL_$1,RGX_CR_PERF_SLC1_WRITE_ID_STALL_0" hexmask.long 0x0 0.--31. 1. "COUNT,The number of cycles the SLC spends stalled because all Write IDs on memory interface 1 are currently in use" repeat.end repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) rgroup.long ($2+0x6138)++0x3 line.long 0x0 "RGX_CR_PERF_SLC_BURST_SIZE3_OUT_$1,RGX_CR_PERF_SLC_BURST_SIZE3_OUT_0" hexmask.long 0x0 0.--31. 1. "VALUE,The number of burstlength 3 accesses out of the Burst Combiner" repeat.end repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) rgroup.long ($2+0x6140)++0x3 line.long 0x0 "RGX_CR_PERF_SLC2_READ_$1,RGX_CR_PERF_SLC2_READ_0" hexmask.long 0x0 0.--31. 1. "COUNT,The number of SLC-to-MEM interface 2 reads" repeat.end repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) rgroup.long ($2+0x6148)++0x3 line.long 0x0 "RGX_CR_PERF_SLC2_WRITE_$1,RGX_CR_PERF_SLC2_WRITE_0" hexmask.long 0x0 0.--31. 1. "COUNT,The number of SLC-to-MEM interface 2 writes" repeat.end repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) rgroup.long ($2+0x6150)++0x3 line.long 0x0 "RGX_CR_PERF_SLC2_BYTE_WRITE_$1,RGX_CR_PERF_SLC2_BYTE_WRITE_0" hexmask.long 0x0 0.--31. 1. "COUNT,The number of SLC-to-MEM interface 2 bytes written" repeat.end repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) rgroup.long ($2+0x6158)++0x3 line.long 0x0 "RGX_CR_PERF_SLC2_READ_STALL_$1,RGX_CR_PERF_SLC2_READ_STALL_0" hexmask.long 0x0 0.--31. 1. "COUNT,The number of SLC-to-MEM interface 2 command stalls" repeat.end repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) rgroup.long ($2+0x6160)++0x3 line.long 0x0 "RGX_CR_PERF_SLC2_WRITE_STALL_$1,RGX_CR_PERF_SLC2_WRITE_STALL_0" hexmask.long 0x0 0.--31. 1. "COUNT,The number of SLC-to-MEM interface 2 write channel stalls" repeat.end repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) rgroup.long ($2+0x6168)++0x3 line.long 0x0 "RGX_CR_PERF_SLC3_READ_$1,RGX_CR_PERF_SLC3_READ_0" hexmask.long 0x0 0.--31. 1. "COUNT,The number of SLC-to-MEM interface 3 reads" repeat.end repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) rgroup.long ($2+0x6170)++0x3 line.long 0x0 "RGX_CR_PERF_SLC3_WRITE_$1,RGX_CR_PERF_SLC3_WRITE_0" hexmask.long 0x0 0.--31. 1. "COUNT,The number of SLC-to-MEM interface 3 writes" repeat.end repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) rgroup.long ($2+0x6178)++0x3 line.long 0x0 "RGX_CR_PERF_SLC3_BYTE_WRITE_$1,RGX_CR_PERF_SLC3_BYTE_WRITE_0" hexmask.long 0x0 0.--31. 1. "COUNT,The number of SLC-to-MEM interface 3 bytes written" repeat.end repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) rgroup.long ($2+0x6180)++0x3 line.long 0x0 "RGX_CR_PERF_SLC3_READ_STALL_$1,RGX_CR_PERF_SLC3_READ_STALL_0" hexmask.long 0x0 0.--31. 1. "COUNT,The number of SLC-to-MEM interface 3 command stalls" repeat.end repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) rgroup.long ($2+0x6188)++0x3 line.long 0x0 "RGX_CR_PERF_SLC3_WRITE_STALL_$1,RGX_CR_PERF_SLC3_WRITE_STALL_0" hexmask.long 0x0 0.--31. 1. "COUNT,The number of SLC-to-MEM interface 3 write channel stalls" repeat.end repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) rgroup.long ($2+0x6190)++0x3 line.long 0x0 "RGX_CR_PERF_SLC_BURST_SIZE2_IN_$1,RGX_CR_PERF_SLC_BURST_SIZE2_IN_0" hexmask.long 0x0 0.--31. 1. "VALUE,The number of burstlength 2 accesses into the Burst Combiner" repeat.end repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) rgroup.long ($2+0x6198)++0x3 line.long 0x0 "RGX_CR_PERF_SLC_BURST_SIZE3_IN_$1,RGX_CR_PERF_SLC_BURST_SIZE3_IN_0" hexmask.long 0x0 0.--31. 1. "VALUE,The number of burstlength 3 accesses into the Burst Combiner" repeat.end repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) rgroup.long ($2+0x6220)++0x3 line.long 0x0 "RGX_CR_PERF_3D_SPINUP_$1,RGX_CR_PERF_3D_SPINUP_0" hexmask.long 0x0 0.--31. 1. "CYCLES,The number of cycles it takes the 3D pipeline to spin-up" repeat.end group.long 0x6300++0x7 line.long 0x0 "RGX_CR_POWER_ESTIMATE_REQ_RST_0,Power estimate Request/Reset - The generation of the power estimate will be initiated upon a write to the power managment register. This will be driven down to the relevant blocks to reset the counters and also to start.." hexmask.long 0x0 1.--31. 1. "Reserved_1,Reserved_1" newline bitfld.long 0x0 0. "VALUE,VALUE" "0,1" line.long 0x4 "RGX_CR_POWER_ESTIMATE_REQ_RST_1,Power estimate Request/Reset - The generation of the power estimate will be initiated upon a write to the power managment register. This will be driven down to the relevant blocks to reset the counters and also to start.." hexmask.long 0x4 0.--31. 1. "Reserved_1,Reserved_1" repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) group.long ($2+0x6310)++0x3 line.long 0x0 "RGX_CR_POWER_ESTIMATE_SAMPLE_COUNT_$1,Power Estimate Sample Count - This defines the number of cycles over which power monitoring will occur. When the POWER_ESTIMIATE_REQ_RST is written to POWER_ESTIMATE_SAMPLE_COUNT will begin to count down from its.." hexmask.long 0x0 0.--31. 1. "VALUE,VALUE" repeat.end rgroup.long 0x6318++0x7 line.long 0x0 "RGX_CR_POWER_ESTIMATE_READY_0,Power estimate Ready - A system event (portmap signal and maskable interrupt) is output when the power estimate has been completed and the power monitor register is updated. Logic or firmware or both will manage the SOC.." hexmask.long.word 0x0 17.--31. 1. "Reserved_17,Reserved_17" newline bitfld.long 0x0 16. "FB_CDC,FB_CDC" "0,1" newline bitfld.long 0x0 15. "Reserved_15,Reserved_15" "0,1" newline bitfld.long 0x0 14. "SLC,SLC" "0,1" newline bitfld.long 0x0 13. "TILING,TILING" "0,1" newline bitfld.long 0x0 12. "JONES,JONES" "0,1" newline bitfld.long 0x0 10.--11. "Reserved_10,Reserved_10" "0,1,2,3" newline bitfld.long 0x0 9. "TA,TA" "0,1" newline bitfld.long 0x0 8. "RASTERISATION,RASTERISATION" "0,1" newline bitfld.long 0x0 7. "HUB,HUB" "0,1" newline bitfld.long 0x0 6. "BIFPMCACHE,BIFPMCACHE" "0,1" newline bitfld.long 0x0 5. "Reserved_5,Reserved_5" "0,1" newline bitfld.long 0x0 4. "TPU_MCU,TPU_MCU" "0,1" newline bitfld.long 0x0 1.--3. "Reserved_1,Reserved_1" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 0. "USC,USC" "0,1" line.long 0x4 "RGX_CR_POWER_ESTIMATE_READY_1,Power estimate Ready - A system event (portmap signal and maskable interrupt) is output when the power estimate has been completed and the power monitor register is updated. Logic or firmware or both will manage the SOC.." hexmask.long 0x4 0.--31. 1. "Reserved_17,Reserved_17" repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) group.long ($2+0x6320)++0x3 line.long 0x0 "RGX_CR_POWER_ESTIMATE_GAIN_COEFF_$1,Final Gain coefficient to apply to summation of all power monitoring quotients" hexmask.long 0x0 0.--31. 1. "VALUE,VALUE" repeat.end repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) group.long ($2+0x6328)++0x3 line.long 0x0 "RGX_CR_POWER_ESTIMATE_RESULT_$1,Power Estimate Result. This represents the estimation of the total system power usage." hexmask.long 0x0 0.--31. 1. "VALUE,VALUE" repeat.end group.long 0x6330++0x7 line.long 0x0 "RGX_CR_PERF_COUNT_MODE_ONLY_0,This register bit set means we need to do only perf-counter gathering and nothing to do with pwr-perf related counting" hexmask.long 0x0 1.--31. 1. "Reserved_1,Reserved_1" newline bitfld.long 0x0 0. "VALUE,VALUE" "0,1" line.long 0x4 "RGX_CR_PERF_COUNT_MODE_ONLY_1,This register bit set means we need to do only perf-counter gathering and nothing to do with pwr-perf related counting" hexmask.long 0x4 0.--31. 1. "Reserved_1,Reserved_1" rgroup.long 0x6500++0x2F line.long 0x0 "RGX_CR_AVG_NON_CRITICAL_MEM0_LATENCY_0,RGX_CR_AVG_NON_CRITICAL_MEM0_LATENCY_0" hexmask.long.tbyte 0x0 12.--31. 1. "Reserved_12,Reserved_12" newline hexmask.long.word 0x0 0.--11. 1. "COUNT,The average number of read latency cycles incur at external memory for non critical tag" line.long 0x4 "RGX_CR_AVG_NON_CRITICAL_MEM0_LATENCY_1,RGX_CR_AVG_NON_CRITICAL_MEM0_LATENCY_1" hexmask.long 0x4 0.--31. 1. "Reserved_12,Reserved_12" line.long 0x8 "RGX_CR_MIN_NON_CRITICAL_MEM0_LATENCY_0,RGX_CR_MIN_NON_CRITICAL_MEM0_LATENCY_0" hexmask.long.tbyte 0x8 12.--31. 1. "Reserved_12,Reserved_12" newline hexmask.long.word 0x8 0.--11. 1. "COUNT,The min number of read latency cycles incur at external memory for non critical tag" line.long 0xC "RGX_CR_MIN_NON_CRITICAL_MEM0_LATENCY_1,RGX_CR_MIN_NON_CRITICAL_MEM0_LATENCY_1" hexmask.long 0xC 0.--31. 1. "Reserved_12,Reserved_12" line.long 0x10 "RGX_CR_MAX_NON_CRITICAL_MEM0_LATENCY_0,RGX_CR_MAX_NON_CRITICAL_MEM0_LATENCY_0" hexmask.long.tbyte 0x10 12.--31. 1. "Reserved_12,Reserved_12" newline hexmask.long.word 0x10 0.--11. 1. "COUNT,The max number of read latency cycles incur at external memory for non critical tag" line.long 0x14 "RGX_CR_MAX_NON_CRITICAL_MEM0_LATENCY_1,RGX_CR_MAX_NON_CRITICAL_MEM0_LATENCY_1" hexmask.long 0x14 0.--31. 1. "Reserved_12,Reserved_12" line.long 0x18 "RGX_CR_AVG_CRITICAL_MEM0_LATENCY_0,RGX_CR_AVG_CRITICAL_MEM0_LATENCY_0" hexmask.long.tbyte 0x18 12.--31. 1. "Reserved_12,Reserved_12" newline hexmask.long.word 0x18 0.--11. 1. "COUNT,The average number of read latency cycles incur at external memory for critical tag" line.long 0x1C "RGX_CR_AVG_CRITICAL_MEM0_LATENCY_1,RGX_CR_AVG_CRITICAL_MEM0_LATENCY_1" hexmask.long 0x1C 0.--31. 1. "Reserved_12,Reserved_12" line.long 0x20 "RGX_CR_MIN_CRITICAL_MEM0_LATENCY_0,RGX_CR_MIN_CRITICAL_MEM0_LATENCY_0" hexmask.long.tbyte 0x20 12.--31. 1. "Reserved_12,Reserved_12" newline hexmask.long.word 0x20 0.--11. 1. "COUNT,The min number of read latency cycles incur at external memory for critical tag" line.long 0x24 "RGX_CR_MIN_CRITICAL_MEM0_LATENCY_1,RGX_CR_MIN_CRITICAL_MEM0_LATENCY_1" hexmask.long 0x24 0.--31. 1. "Reserved_12,Reserved_12" line.long 0x28 "RGX_CR_MAX_CRITICAL_MEM0_LATENCY_0,RGX_CR_MAX_CRITICAL_MEM0_LATENCY_0" hexmask.long.tbyte 0x28 12.--31. 1. "Reserved_12,Reserved_12" newline hexmask.long.word 0x28 0.--11. 1. "COUNT,The max number of read latency cycles incur at external memory for critical tag" line.long 0x2C "RGX_CR_MAX_CRITICAL_MEM0_LATENCY_1,RGX_CR_MAX_CRITICAL_MEM0_LATENCY_1" hexmask.long 0x2C 0.--31. 1. "Reserved_12,Reserved_12" group.long 0x6530++0x7 line.long 0x0 "RGX_CR_USER_DEFINED_MEM0_MH_TAG_0,Writing '1' followed by mh_tag value at the lsb end of this register starts the user defined mh_tag value for latency calculation. Default value is zero where this feature is turned off. Bit [6] - Enable bit to turn on.." hexmask.long 0x0 7.--31. 1. "Reserved_7,Reserved_7" newline hexmask.long.byte 0x0 0.--6. 1. "VALUE,VALUE" line.long 0x4 "RGX_CR_USER_DEFINED_MEM0_MH_TAG_1,Writing '1' followed by mh_tag value at the lsb end of this register starts the user defined mh_tag value for latency calculation. Default value is zero where this feature is turned off. Bit [6] - Enable bit to turn on.." hexmask.long 0x4 0.--31. 1. "Reserved_7,Reserved_7" rgroup.long 0x6538++0x57 line.long 0x0 "RGX_CR_AVG_USER_MH_TAG_MEM0_LATENCY_0,RGX_CR_AVG_USER_MH_TAG_MEM0_LATENCY_0" hexmask.long.tbyte 0x0 12.--31. 1. "Reserved_12,Reserved_12" newline hexmask.long.word 0x0 0.--11. 1. "COUNT,The average number of read latency cycles incur at external memory for user_defined tag" line.long 0x4 "RGX_CR_AVG_USER_MH_TAG_MEM0_LATENCY_1,RGX_CR_AVG_USER_MH_TAG_MEM0_LATENCY_1" hexmask.long 0x4 0.--31. 1. "Reserved_12,Reserved_12" line.long 0x8 "RGX_CR_MIN_USER_MH_TAG_MEM0_LATENCY_0,RGX_CR_MIN_USER_MH_TAG_MEM0_LATENCY_0" hexmask.long.tbyte 0x8 12.--31. 1. "Reserved_12,Reserved_12" newline hexmask.long.word 0x8 0.--11. 1. "COUNT,The min number of read latency cycles incur at external memory for user defined tag" line.long 0xC "RGX_CR_MIN_USER_MH_TAG_MEM0_LATENCY_1,RGX_CR_MIN_USER_MH_TAG_MEM0_LATENCY_1" hexmask.long 0xC 0.--31. 1. "Reserved_12,Reserved_12" line.long 0x10 "RGX_CR_MAX_USER_MH_TAG_MEM0_LATENCY_0,RGX_CR_MAX_USER_MH_TAG_MEM0_LATENCY_0" hexmask.long.tbyte 0x10 12.--31. 1. "Reserved_12,Reserved_12" newline hexmask.long.word 0x10 0.--11. 1. "COUNT,The max number of read latency cycles incur at external memory for user defined tag" line.long 0x14 "RGX_CR_MAX_USER_MH_TAG_MEM0_LATENCY_1,RGX_CR_MAX_USER_MH_TAG_MEM0_LATENCY_1" hexmask.long 0x14 0.--31. 1. "Reserved_12,Reserved_12" line.long 0x18 "RGX_CR_MIN_NON_CRITICAL_MEM0_LATENCY_MH_TAG_0,RGX_CR_MIN_NON_CRITICAL_MEM0_LATENCY_MH_TAG_0" hexmask.long 0x18 6.--31. 1. "Reserved_6,Reserved_6" newline hexmask.long.byte 0x18 0.--5. 1. "VALUE,The mh_tag value of min read latency cycles for non critical tag" line.long 0x1C "RGX_CR_MIN_NON_CRITICAL_MEM0_LATENCY_MH_TAG_1,RGX_CR_MIN_NON_CRITICAL_MEM0_LATENCY_MH_TAG_1" hexmask.long 0x1C 0.--31. 1. "Reserved_6,Reserved_6" line.long 0x20 "RGX_CR_MAX_NON_CRITICAL_MEM0_LATENCY_MH_TAG_0,RGX_CR_MAX_NON_CRITICAL_MEM0_LATENCY_MH_TAG_0" hexmask.long 0x20 6.--31. 1. "Reserved_6,Reserved_6" newline hexmask.long.byte 0x20 0.--5. 1. "VALUE,The mh_tag value of max read latency cycles for non critical tag" line.long 0x24 "RGX_CR_MAX_NON_CRITICAL_MEM0_LATENCY_MH_TAG_1,RGX_CR_MAX_NON_CRITICAL_MEM0_LATENCY_MH_TAG_1" hexmask.long 0x24 0.--31. 1. "Reserved_6,Reserved_6" line.long 0x28 "RGX_CR_AVG_NON_CRITICAL_MEM1_LATENCY_0,RGX_CR_AVG_NON_CRITICAL_MEM1_LATENCY_0" hexmask.long.tbyte 0x28 12.--31. 1. "Reserved_12,Reserved_12" newline hexmask.long.word 0x28 0.--11. 1. "COUNT,The average number of read latency cycles incur at external memory for non critical tag" line.long 0x2C "RGX_CR_AVG_NON_CRITICAL_MEM1_LATENCY_1,RGX_CR_AVG_NON_CRITICAL_MEM1_LATENCY_1" hexmask.long 0x2C 0.--31. 1. "Reserved_12,Reserved_12" line.long 0x30 "RGX_CR_MIN_NON_CRITICAL_MEM1_LATENCY_0,RGX_CR_MIN_NON_CRITICAL_MEM1_LATENCY_0" hexmask.long.tbyte 0x30 12.--31. 1. "Reserved_12,Reserved_12" newline hexmask.long.word 0x30 0.--11. 1. "COUNT,The min number of read latency cycles incur at external memory for non critical tag" line.long 0x34 "RGX_CR_MIN_NON_CRITICAL_MEM1_LATENCY_1,RGX_CR_MIN_NON_CRITICAL_MEM1_LATENCY_1" hexmask.long 0x34 0.--31. 1. "Reserved_12,Reserved_12" line.long 0x38 "RGX_CR_MAX_NON_CRITICAL_MEM1_LATENCY_0,RGX_CR_MAX_NON_CRITICAL_MEM1_LATENCY_0" hexmask.long.tbyte 0x38 12.--31. 1. "Reserved_12,Reserved_12" newline hexmask.long.word 0x38 0.--11. 1. "COUNT,The max number of read latency cycles incur at external memory for non critical tag" line.long 0x3C "RGX_CR_MAX_NON_CRITICAL_MEM1_LATENCY_1,RGX_CR_MAX_NON_CRITICAL_MEM1_LATENCY_1" hexmask.long 0x3C 0.--31. 1. "Reserved_12,Reserved_12" line.long 0x40 "RGX_CR_AVG_CRITICAL_MEM1_LATENCY_0,RGX_CR_AVG_CRITICAL_MEM1_LATENCY_0" hexmask.long.tbyte 0x40 12.--31. 1. "Reserved_12,Reserved_12" newline hexmask.long.word 0x40 0.--11. 1. "COUNT,The average number of read latency cycles incur at external memory for critical tag" line.long 0x44 "RGX_CR_AVG_CRITICAL_MEM1_LATENCY_1,RGX_CR_AVG_CRITICAL_MEM1_LATENCY_1" hexmask.long 0x44 0.--31. 1. "Reserved_12,Reserved_12" line.long 0x48 "RGX_CR_MIN_CRITICAL_MEM1_LATENCY_0,RGX_CR_MIN_CRITICAL_MEM1_LATENCY_0" hexmask.long.tbyte 0x48 12.--31. 1. "Reserved_12,Reserved_12" newline hexmask.long.word 0x48 0.--11. 1. "COUNT,The min number of read latency cycles incur at external memory for critical tag" line.long 0x4C "RGX_CR_MIN_CRITICAL_MEM1_LATENCY_1,RGX_CR_MIN_CRITICAL_MEM1_LATENCY_1" hexmask.long 0x4C 0.--31. 1. "Reserved_12,Reserved_12" line.long 0x50 "RGX_CR_MAX_CRITICAL_MEM1_LATENCY_0,RGX_CR_MAX_CRITICAL_MEM1_LATENCY_0" hexmask.long.tbyte 0x50 12.--31. 1. "Reserved_12,Reserved_12" newline hexmask.long.word 0x50 0.--11. 1. "COUNT,The max number of read latency cycles incur at external memory for critical tag" line.long 0x54 "RGX_CR_MAX_CRITICAL_MEM1_LATENCY_1,RGX_CR_MAX_CRITICAL_MEM1_LATENCY_1" hexmask.long 0x54 0.--31. 1. "Reserved_12,Reserved_12" group.long 0x6590++0x7 line.long 0x0 "RGX_CR_USER_DEFINED_MEM1_MH_TAG_0,Writing '1' followed by mh_tag value at the lsb end of this register starts the user defined mh_tag value for latency calculation. Default value is zero where this feature is turned off. Bit [6] - Enable bit to turn on.." hexmask.long 0x0 7.--31. 1. "Reserved_7,Reserved_7" newline hexmask.long.byte 0x0 0.--6. 1. "VALUE,VALUE" line.long 0x4 "RGX_CR_USER_DEFINED_MEM1_MH_TAG_1,Writing '1' followed by mh_tag value at the lsb end of this register starts the user defined mh_tag value for latency calculation. Default value is zero where this feature is turned off. Bit [6] - Enable bit to turn on.." hexmask.long 0x4 0.--31. 1. "Reserved_7,Reserved_7" rgroup.long 0x6598++0x27 line.long 0x0 "RGX_CR_AVG_USER_MH_TAG_MEM1_LATENCY_0,RGX_CR_AVG_USER_MH_TAG_MEM1_LATENCY_0" hexmask.long.tbyte 0x0 12.--31. 1. "Reserved_12,Reserved_12" newline hexmask.long.word 0x0 0.--11. 1. "COUNT,The average number of read latency cycles incur at external memory for user_defined tag" line.long 0x4 "RGX_CR_AVG_USER_MH_TAG_MEM1_LATENCY_1,RGX_CR_AVG_USER_MH_TAG_MEM1_LATENCY_1" hexmask.long 0x4 0.--31. 1. "Reserved_12,Reserved_12" line.long 0x8 "RGX_CR_MIN_USER_MH_TAG_MEM1_LATENCY_0,RGX_CR_MIN_USER_MH_TAG_MEM1_LATENCY_0" hexmask.long.tbyte 0x8 12.--31. 1. "Reserved_12,Reserved_12" newline hexmask.long.word 0x8 0.--11. 1. "COUNT,The min number of read latency cycles incur at external memory for user defined tag" line.long 0xC "RGX_CR_MIN_USER_MH_TAG_MEM1_LATENCY_1,RGX_CR_MIN_USER_MH_TAG_MEM1_LATENCY_1" hexmask.long 0xC 0.--31. 1. "Reserved_12,Reserved_12" line.long 0x10 "RGX_CR_MAX_USER_MH_TAG_MEM1_LATENCY_0,RGX_CR_MAX_USER_MH_TAG_MEM1_LATENCY_0" hexmask.long.tbyte 0x10 12.--31. 1. "Reserved_12,Reserved_12" newline hexmask.long.word 0x10 0.--11. 1. "COUNT,The max number of read latency cycles incur at external memory for user defined tag" line.long 0x14 "RGX_CR_MAX_USER_MH_TAG_MEM1_LATENCY_1,RGX_CR_MAX_USER_MH_TAG_MEM1_LATENCY_1" hexmask.long 0x14 0.--31. 1. "Reserved_12,Reserved_12" line.long 0x18 "RGX_CR_MIN_NON_CRITICAL_MEM1_LATENCY_MH_TAG_0,RGX_CR_MIN_NON_CRITICAL_MEM1_LATENCY_MH_TAG_0" hexmask.long 0x18 6.--31. 1. "Reserved_6,Reserved_6" newline hexmask.long.byte 0x18 0.--5. 1. "VALUE,The mh_tag value of min read latency cycles for non critical tag" line.long 0x1C "RGX_CR_MIN_NON_CRITICAL_MEM1_LATENCY_MH_TAG_1,RGX_CR_MIN_NON_CRITICAL_MEM1_LATENCY_MH_TAG_1" hexmask.long 0x1C 0.--31. 1. "Reserved_6,Reserved_6" line.long 0x20 "RGX_CR_MAX_NON_CRITICAL_MEM1_LATENCY_MH_TAG_0,RGX_CR_MAX_NON_CRITICAL_MEM1_LATENCY_MH_TAG_0" hexmask.long 0x20 6.--31. 1. "Reserved_6,Reserved_6" newline hexmask.long.byte 0x20 0.--5. 1. "VALUE,The mh_tag value of max read latency cycles for non critical tag" line.long 0x24 "RGX_CR_MAX_NON_CRITICAL_MEM1_LATENCY_MH_TAG_1,RGX_CR_MAX_NON_CRITICAL_MEM1_LATENCY_MH_TAG_1" hexmask.long 0x24 0.--31. 1. "Reserved_6,Reserved_6" group.long 0x7600++0x27 line.long 0x0 "RGX_CR_TA_PERF_0,RGX_CR_TA_PERF_0" hexmask.long 0x0 5.--31. 1. "Reserved_5,Reserved_5" newline bitfld.long 0x0 4. "CLR_3,clear counter 3" "0,1" newline bitfld.long 0x0 3. "CLR_2,clear counter 2" "0,1" newline bitfld.long 0x0 2. "CLR_1,clear counter 1" "0,1" newline bitfld.long 0x0 1. "CLR_0,clear counter 0" "0,1" newline bitfld.long 0x0 0. "CTRL_ENABLE,enables the perf bus counters" "0,1" line.long 0x4 "RGX_CR_TA_PERF_1,RGX_CR_TA_PERF_1" hexmask.long 0x4 0.--31. 1. "Reserved_5,Reserved_5" line.long 0x8 "RGX_CR_TA_PERF_SELECT0_0,RGX_CR_TA_PERF_SELECT0_0" hexmask.long.word 0x8 22.--31. 1. "Reserved_22,Reserved_22" newline bitfld.long 0x8 21. "MODE,reduction mode 0: bitwise increments 1: unsigned count increment" "bitwise increments,unsigned count increment" newline hexmask.long.byte 0x8 16.--20. 1. "GROUP_SELECT,group select see full PERF documentation for signals in each group" newline hexmask.long.word 0x8 0.--15. 1. "BIT_SELECT,bit mask for enabled signals in group" line.long 0xC "RGX_CR_TA_PERF_SELECT0_1,RGX_CR_TA_PERF_SELECT0_1" hexmask.long 0xC 0.--31. 1. "Reserved_22,Reserved_22" line.long 0x10 "RGX_CR_TA_PERF_SELECT1_0,RGX_CR_TA_PERF_SELECT1_0" hexmask.long.word 0x10 22.--31. 1. "Reserved_22,Reserved_22" newline bitfld.long 0x10 21. "MODE,reduction mode 0: bitwise increments 1: unsigned count increment" "bitwise increments,unsigned count increment" newline hexmask.long.byte 0x10 16.--20. 1. "GROUP_SELECT,group select see full PERF documentation for signals in each group" newline hexmask.long.word 0x10 0.--15. 1. "BIT_SELECT,bit mask for enabled signals in group" line.long 0x14 "RGX_CR_TA_PERF_SELECT1_1,RGX_CR_TA_PERF_SELECT1_1" hexmask.long 0x14 0.--31. 1. "Reserved_22,Reserved_22" line.long 0x18 "RGX_CR_TA_PERF_SELECT2_0,RGX_CR_TA_PERF_SELECT2_0" hexmask.long.word 0x18 22.--31. 1. "Reserved_22,Reserved_22" newline bitfld.long 0x18 21. "MODE,reduction mode 0: bitwise increments 1: unsigned count increment" "bitwise increments,unsigned count increment" newline hexmask.long.byte 0x18 16.--20. 1. "GROUP_SELECT,group select see full PERF documentation for signals in each group" newline hexmask.long.word 0x18 0.--15. 1. "BIT_SELECT,bit mask for enabled signals in group" line.long 0x1C "RGX_CR_TA_PERF_SELECT2_1,RGX_CR_TA_PERF_SELECT2_1" hexmask.long 0x1C 0.--31. 1. "Reserved_22,Reserved_22" line.long 0x20 "RGX_CR_TA_PERF_SELECT3_0,RGX_CR_TA_PERF_SELECT3_0" hexmask.long.word 0x20 22.--31. 1. "Reserved_22,Reserved_22" newline bitfld.long 0x20 21. "MODE,reduction mode 0: bitwise increments 1: unsigned count increment" "bitwise increments,unsigned count increment" newline hexmask.long.byte 0x20 16.--20. 1. "GROUP_SELECT,group select see full PERF documentation for signals in each group" newline hexmask.long.word 0x20 0.--15. 1. "BIT_SELECT,bit mask for enabled signals in group" line.long 0x24 "RGX_CR_TA_PERF_SELECT3_1,RGX_CR_TA_PERF_SELECT3_1" hexmask.long 0x24 0.--31. 1. "Reserved_22,Reserved_22" repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) rgroup.long ($2+0x7648)++0x3 line.long 0x0 "RGX_CR_TA_PERF_SELECTED_BITS_$1,RGX_CR_TA_PERF_SELECTED_BITS_0" hexmask.long.word 0x0 16.--31. 1. "REG1,persent bus signals counter 1" newline hexmask.long.word 0x0 0.--15. 1. "REG0,present bus signals counter 0" repeat.end repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) rgroup.long ($2+0x7650)++0x3 line.long 0x0 "RGX_CR_TA_PERF_COUNTER_0_$1,RGX_CR_TA_PERF_COUNTER_0_0" hexmask.long 0x0 0.--31. 1. "REG,counter a0" repeat.end repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) rgroup.long ($2+0x7658)++0x3 line.long 0x0 "RGX_CR_TA_PERF_COUNTER_1_$1,RGX_CR_TA_PERF_COUNTER_1_0" hexmask.long 0x0 0.--31. 1. "REG,counter a0" repeat.end repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) rgroup.long ($2+0x7660)++0x3 line.long 0x0 "RGX_CR_TA_PERF_COUNTER_2_$1,RGX_CR_TA_PERF_COUNTER_2_0" hexmask.long 0x0 0.--31. 1. "REG,counter a0" repeat.end repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) rgroup.long ($2+0x7668)++0x3 line.long 0x0 "RGX_CR_TA_PERF_COUNTER_3_$1,RGX_CR_TA_PERF_COUNTER_3_0" hexmask.long 0x0 0.--31. 1. "REG,counter a0" repeat.end group.long 0x7700++0x27 line.long 0x0 "RGX_CR_RASTERISATION_PERF_0,RGX_CR_RASTERISATION_PERF_0" hexmask.long 0x0 5.--31. 1. "Reserved_5,Reserved_5" newline bitfld.long 0x0 4. "CLR_3,clear counter 3" "0,1" newline bitfld.long 0x0 3. "CLR_2,clear counter 2" "0,1" newline bitfld.long 0x0 2. "CLR_1,clear counter 1" "0,1" newline bitfld.long 0x0 1. "CLR_0,clear counter 0" "0,1" newline bitfld.long 0x0 0. "CTRL_ENABLE,enables the perf bus counters" "0,1" line.long 0x4 "RGX_CR_RASTERISATION_PERF_1,RGX_CR_RASTERISATION_PERF_1" hexmask.long 0x4 0.--31. 1. "Reserved_5,Reserved_5" line.long 0x8 "RGX_CR_RASTERISATION_PERF_SELECT0_0,RGX_CR_RASTERISATION_PERF_SELECT0_0" hexmask.long.word 0x8 22.--31. 1. "Reserved_22,Reserved_22" newline bitfld.long 0x8 21. "MODE,reduction mode 0: bitwise increments 1: unsigned count increment" "bitwise increments,unsigned count increment" newline hexmask.long.byte 0x8 16.--20. 1. "GROUP_SELECT,group select see full PERF documenrasterisationtion for signals in each group" newline hexmask.long.word 0x8 0.--15. 1. "BIT_SELECT,bit mask for enabled signals in group" line.long 0xC "RGX_CR_RASTERISATION_PERF_SELECT0_1,RGX_CR_RASTERISATION_PERF_SELECT0_1" hexmask.long 0xC 0.--31. 1. "Reserved_22,Reserved_22" line.long 0x10 "RGX_CR_RASTERISATION_PERF_SELECT1_0,RGX_CR_RASTERISATION_PERF_SELECT1_0" hexmask.long.word 0x10 22.--31. 1. "Reserved_22,Reserved_22" newline bitfld.long 0x10 21. "MODE,reduction mode 0: bitwise increments 1: unsigned count increment" "bitwise increments,unsigned count increment" newline hexmask.long.byte 0x10 16.--20. 1. "GROUP_SELECT,group select see full PERF documenrasterisationtion for signals in each group" newline hexmask.long.word 0x10 0.--15. 1. "BIT_SELECT,bit mask for enabled signals in group" line.long 0x14 "RGX_CR_RASTERISATION_PERF_SELECT1_1,RGX_CR_RASTERISATION_PERF_SELECT1_1" hexmask.long 0x14 0.--31. 1. "Reserved_22,Reserved_22" line.long 0x18 "RGX_CR_RASTERISATION_PERF_SELECT2_0,RGX_CR_RASTERISATION_PERF_SELECT2_0" hexmask.long.word 0x18 22.--31. 1. "Reserved_22,Reserved_22" newline bitfld.long 0x18 21. "MODE,reduction mode 0: bitwise increments 1: unsigned count increment" "bitwise increments,unsigned count increment" newline hexmask.long.byte 0x18 16.--20. 1. "GROUP_SELECT,group select see full PERF documenrasterisationtion for signals in each group" newline hexmask.long.word 0x18 0.--15. 1. "BIT_SELECT,bit mask for enabled signals in group" line.long 0x1C "RGX_CR_RASTERISATION_PERF_SELECT2_1,RGX_CR_RASTERISATION_PERF_SELECT2_1" hexmask.long 0x1C 0.--31. 1. "Reserved_22,Reserved_22" line.long 0x20 "RGX_CR_RASTERISATION_PERF_SELECT3_0,RGX_CR_RASTERISATION_PERF_SELECT3_0" hexmask.long.word 0x20 22.--31. 1. "Reserved_22,Reserved_22" newline bitfld.long 0x20 21. "MODE,reduction mode 0: bitwise increments 1: unsigned count increment" "bitwise increments,unsigned count increment" newline hexmask.long.byte 0x20 16.--20. 1. "GROUP_SELECT,group select see full PERF documenrasterisationtion for signals in each group" newline hexmask.long.word 0x20 0.--15. 1. "BIT_SELECT,bit mask for enabled signals in group" line.long 0x24 "RGX_CR_RASTERISATION_PERF_SELECT3_1,RGX_CR_RASTERISATION_PERF_SELECT3_1" hexmask.long 0x24 0.--31. 1. "Reserved_22,Reserved_22" repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) rgroup.long ($2+0x7748)++0x3 line.long 0x0 "RGX_CR_RASTERISATION_PERF_SELECTED_BITS_$1,RGX_CR_RASTERISATION_PERF_SELECTED_BITS_0" hexmask.long.word 0x0 16.--31. 1. "REG1,persent bus signals counter 1" newline hexmask.long.word 0x0 0.--15. 1. "REG0,present bus signals counter 0" repeat.end repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) rgroup.long ($2+0x7750)++0x3 line.long 0x0 "RGX_CR_RASTERISATION_PERF_COUNTER_0_$1,RGX_CR_RASTERISATION_PERF_COUNTER_0_0" hexmask.long 0x0 0.--31. 1. "REG,counter a0" repeat.end repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) rgroup.long ($2+0x7758)++0x3 line.long 0x0 "RGX_CR_RASTERISATION_PERF_COUNTER_1_$1,RGX_CR_RASTERISATION_PERF_COUNTER_1_0" hexmask.long 0x0 0.--31. 1. "REG,counter a0" repeat.end repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) rgroup.long ($2+0x7760)++0x3 line.long 0x0 "RGX_CR_RASTERISATION_PERF_COUNTER_2_$1,RGX_CR_RASTERISATION_PERF_COUNTER_2_0" hexmask.long 0x0 0.--31. 1. "REG,counter a0" repeat.end repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) rgroup.long ($2+0x7768)++0x3 line.long 0x0 "RGX_CR_RASTERISATION_PERF_COUNTER_3_$1,RGX_CR_RASTERISATION_PERF_COUNTER_3_0" hexmask.long 0x0 0.--31. 1. "REG,counter a0" repeat.end group.long 0x7800++0x27 line.long 0x0 "RGX_CR_HUB_BIFPMCACHE_PERF_0,RGX_CR_HUB_BIFPMCACHE_PERF_0" hexmask.long 0x0 5.--31. 1. "Reserved_5,Reserved_5" newline bitfld.long 0x0 4. "CLR_3,clear counter 3" "0,1" newline bitfld.long 0x0 3. "CLR_2,clear counter 2" "0,1" newline bitfld.long 0x0 2. "CLR_1,clear counter 1" "0,1" newline bitfld.long 0x0 1. "CLR_0,clear counter 0" "0,1" newline bitfld.long 0x0 0. "CTRL_ENABLE,enables the perf bus counters" "0,1" line.long 0x4 "RGX_CR_HUB_BIFPMCACHE_PERF_1,RGX_CR_HUB_BIFPMCACHE_PERF_1" hexmask.long 0x4 0.--31. 1. "Reserved_5,Reserved_5" line.long 0x8 "RGX_CR_HUB_BIFPMCACHE_PERF_SELECT0_0,RGX_CR_HUB_BIFPMCACHE_PERF_SELECT0_0" hexmask.long.word 0x8 22.--31. 1. "Reserved_22,Reserved_22" newline bitfld.long 0x8 21. "MODE,reduction mode 0: bitwise increments 1: unsigned count increment" "bitwise increments,unsigned count increment" newline hexmask.long.byte 0x8 16.--20. 1. "GROUP_SELECT,group select see full PERF documenhub_bifpmcachetion for signals in each group" newline hexmask.long.word 0x8 0.--15. 1. "BIT_SELECT,bit mask for enabled signals in group" line.long 0xC "RGX_CR_HUB_BIFPMCACHE_PERF_SELECT0_1,RGX_CR_HUB_BIFPMCACHE_PERF_SELECT0_1" hexmask.long 0xC 0.--31. 1. "Reserved_22,Reserved_22" line.long 0x10 "RGX_CR_HUB_BIFPMCACHE_PERF_SELECT1_0,RGX_CR_HUB_BIFPMCACHE_PERF_SELECT1_0" hexmask.long.word 0x10 22.--31. 1. "Reserved_22,Reserved_22" newline bitfld.long 0x10 21. "MODE,reduction mode 0: bitwise increments 1: unsigned count increment" "bitwise increments,unsigned count increment" newline hexmask.long.byte 0x10 16.--20. 1. "GROUP_SELECT,group select see full PERF documenhub_bifpmcachetion for signals in each group" newline hexmask.long.word 0x10 0.--15. 1. "BIT_SELECT,bit mask for enabled signals in group" line.long 0x14 "RGX_CR_HUB_BIFPMCACHE_PERF_SELECT1_1,RGX_CR_HUB_BIFPMCACHE_PERF_SELECT1_1" hexmask.long 0x14 0.--31. 1. "Reserved_22,Reserved_22" line.long 0x18 "RGX_CR_HUB_BIFPMCACHE_PERF_SELECT2_0,RGX_CR_HUB_BIFPMCACHE_PERF_SELECT2_0" hexmask.long.word 0x18 22.--31. 1. "Reserved_22,Reserved_22" newline bitfld.long 0x18 21. "MODE,reduction mode 0: bitwise increments 1: unsigned count increment" "bitwise increments,unsigned count increment" newline hexmask.long.byte 0x18 16.--20. 1. "GROUP_SELECT,group select see full PERF documenhub_bifpmcachetion for signals in each group" newline hexmask.long.word 0x18 0.--15. 1. "BIT_SELECT,bit mask for enabled signals in group" line.long 0x1C "RGX_CR_HUB_BIFPMCACHE_PERF_SELECT2_1,RGX_CR_HUB_BIFPMCACHE_PERF_SELECT2_1" hexmask.long 0x1C 0.--31. 1. "Reserved_22,Reserved_22" line.long 0x20 "RGX_CR_HUB_BIFPMCACHE_PERF_SELECT3_0,RGX_CR_HUB_BIFPMCACHE_PERF_SELECT3_0" hexmask.long.word 0x20 22.--31. 1. "Reserved_22,Reserved_22" newline bitfld.long 0x20 21. "MODE,reduction mode 0: bitwise increments 1: unsigned count increment" "bitwise increments,unsigned count increment" newline hexmask.long.byte 0x20 16.--20. 1. "GROUP_SELECT,group select see full PERF documenhub_bifpmcachetion for signals in each group" newline hexmask.long.word 0x20 0.--15. 1. "BIT_SELECT,bit mask for enabled signals in group" line.long 0x24 "RGX_CR_HUB_BIFPMCACHE_PERF_SELECT3_1,RGX_CR_HUB_BIFPMCACHE_PERF_SELECT3_1" hexmask.long 0x24 0.--31. 1. "Reserved_22,Reserved_22" repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) rgroup.long ($2+0x7848)++0x3 line.long 0x0 "RGX_CR_HUB_BIFPMCACHE_PERF_SELECTED_BITS_$1,RGX_CR_HUB_BIFPMCACHE_PERF_SELECTED_BITS_0" hexmask.long.word 0x0 16.--31. 1. "REG1,persent bus signals counter 1" newline hexmask.long.word 0x0 0.--15. 1. "REG0,present bus signals counter 0" repeat.end repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) rgroup.long ($2+0x7850)++0x3 line.long 0x0 "RGX_CR_HUB_BIFPMCACHE_PERF_COUNTER_0_$1,RGX_CR_HUB_BIFPMCACHE_PERF_COUNTER_0_0" hexmask.long 0x0 0.--31. 1. "REG,counter a0" repeat.end repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) rgroup.long ($2+0x7858)++0x3 line.long 0x0 "RGX_CR_HUB_BIFPMCACHE_PERF_COUNTER_1_$1,RGX_CR_HUB_BIFPMCACHE_PERF_COUNTER_1_0" hexmask.long 0x0 0.--31. 1. "REG,counter a0" repeat.end repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) rgroup.long ($2+0x7860)++0x3 line.long 0x0 "RGX_CR_HUB_BIFPMCACHE_PERF_COUNTER_2_$1,RGX_CR_HUB_BIFPMCACHE_PERF_COUNTER_2_0" hexmask.long 0x0 0.--31. 1. "REG,counter a0" repeat.end repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) rgroup.long ($2+0x7868)++0x3 line.long 0x0 "RGX_CR_HUB_BIFPMCACHE_PERF_COUNTER_3_$1,RGX_CR_HUB_BIFPMCACHE_PERF_COUNTER_3_0" hexmask.long 0x0 0.--31. 1. "REG,counter a0" repeat.end group.long 0x7900++0x27 line.long 0x0 "RGX_CR_TPU_MCU_L0_PERF_0,RGX_CR_TPU_MCU_L0_PERF_0" hexmask.long 0x0 5.--31. 1. "Reserved_5,Reserved_5" newline bitfld.long 0x0 4. "CLR_3,clear counter 3" "0,1" newline bitfld.long 0x0 3. "CLR_2,clear counter 2" "0,1" newline bitfld.long 0x0 2. "CLR_1,clear counter 1" "0,1" newline bitfld.long 0x0 1. "CLR_0,clear counter 0" "0,1" newline bitfld.long 0x0 0. "CTRL_ENABLE,enables the perf bus counters" "0,1" line.long 0x4 "RGX_CR_TPU_MCU_L0_PERF_1,RGX_CR_TPU_MCU_L0_PERF_1" hexmask.long 0x4 0.--31. 1. "Reserved_5,Reserved_5" line.long 0x8 "RGX_CR_TPU_MCU_L0_PERF_SELECT0_0,RGX_CR_TPU_MCU_L0_PERF_SELECT0_0" hexmask.long.word 0x8 22.--31. 1. "Reserved_22,Reserved_22" newline bitfld.long 0x8 21. "MODE,reduction mode 0: bitwise increments 1: unsigned count increment" "bitwise increments,unsigned count increment" newline hexmask.long.byte 0x8 16.--20. 1. "GROUP_SELECT,group select see full PERF documentation for signals in each group" newline hexmask.long.word 0x8 0.--15. 1. "BIT_SELECT,bit mask for enabled signals in group" line.long 0xC "RGX_CR_TPU_MCU_L0_PERF_SELECT0_1,RGX_CR_TPU_MCU_L0_PERF_SELECT0_1" bitfld.long 0xC 30.--31. "Reserved_62,Reserved_62" "0,1,2,3" newline hexmask.long.word 0xC 16.--29. 1. "BATCH_MAX,this is the min batch number which will be counted in this group" newline bitfld.long 0xC 14.--15. "Reserved_46,Reserved_46" "0,1,2,3" newline hexmask.long.word 0xC 0.--13. 1. "BATCH_MIN,this is the min batch number which will be counted in this group" line.long 0x10 "RGX_CR_TPU_MCU_L0_PERF_SELECT1_0,RGX_CR_TPU_MCU_L0_PERF_SELECT1_0" hexmask.long.word 0x10 22.--31. 1. "Reserved_22,Reserved_22" newline bitfld.long 0x10 21. "MODE,reduction mode 0: bitwise increments 1: unsigned count increment" "bitwise increments,unsigned count increment" newline hexmask.long.byte 0x10 16.--20. 1. "GROUP_SELECT,group select see full PERF documentation for signals in each group" newline hexmask.long.word 0x10 0.--15. 1. "BIT_SELECT,bit mask for enabled signals in group" line.long 0x14 "RGX_CR_TPU_MCU_L0_PERF_SELECT1_1,RGX_CR_TPU_MCU_L0_PERF_SELECT1_1" bitfld.long 0x14 30.--31. "Reserved_62,Reserved_62" "0,1,2,3" newline hexmask.long.word 0x14 16.--29. 1. "BATCH_MAX,this is the min batch number which will be counted in this group" newline bitfld.long 0x14 14.--15. "Reserved_46,Reserved_46" "0,1,2,3" newline hexmask.long.word 0x14 0.--13. 1. "BATCH_MIN,this is the min batch number which will be counted in this group" line.long 0x18 "RGX_CR_TPU_MCU_L0_PERF_SELECT2_0,RGX_CR_TPU_MCU_L0_PERF_SELECT2_0" hexmask.long.word 0x18 22.--31. 1. "Reserved_22,Reserved_22" newline bitfld.long 0x18 21. "MODE,reduction mode 0: bitwise increments 1: unsigned count increment" "bitwise increments,unsigned count increment" newline hexmask.long.byte 0x18 16.--20. 1. "GROUP_SELECT,group select see full PERF documentation for signals in each group" newline hexmask.long.word 0x18 0.--15. 1. "BIT_SELECT,bit mask for enabled signals in group" line.long 0x1C "RGX_CR_TPU_MCU_L0_PERF_SELECT2_1,RGX_CR_TPU_MCU_L0_PERF_SELECT2_1" bitfld.long 0x1C 30.--31. "Reserved_62,Reserved_62" "0,1,2,3" newline hexmask.long.word 0x1C 16.--29. 1. "BATCH_MAX,this is the min batch number which will be counted in this group" newline bitfld.long 0x1C 14.--15. "Reserved_46,Reserved_46" "0,1,2,3" newline hexmask.long.word 0x1C 0.--13. 1. "BATCH_MIN,this is the min batch number which will be counted in this group" line.long 0x20 "RGX_CR_TPU_MCU_L0_PERF_SELECT3_0,RGX_CR_TPU_MCU_L0_PERF_SELECT3_0" hexmask.long.word 0x20 22.--31. 1. "Reserved_22,Reserved_22" newline bitfld.long 0x20 21. "MODE,reduction mode 0: bitwise increments 1: unsigned count increment" "bitwise increments,unsigned count increment" newline hexmask.long.byte 0x20 16.--20. 1. "GROUP_SELECT,group select see full PERF documentation for signals in each group" newline hexmask.long.word 0x20 0.--15. 1. "BIT_SELECT,bit mask for enabled signals in group" line.long 0x24 "RGX_CR_TPU_MCU_L0_PERF_SELECT3_1,RGX_CR_TPU_MCU_L0_PERF_SELECT3_1" bitfld.long 0x24 30.--31. "Reserved_62,Reserved_62" "0,1,2,3" newline hexmask.long.word 0x24 16.--29. 1. "BATCH_MAX,this is the min batch number which will be counted in this group" newline bitfld.long 0x24 14.--15. "Reserved_46,Reserved_46" "0,1,2,3" newline hexmask.long.word 0x24 0.--13. 1. "BATCH_MIN,this is the min batch number which will be counted in this group" repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) rgroup.long ($2+0x7948)++0x3 line.long 0x0 "RGX_CR_TPU_MCU_L0_PERF_SELECTED_BITS_$1,RGX_CR_TPU_MCU_L0_PERF_SELECTED_BITS_0" hexmask.long.word 0x0 16.--31. 1. "REG1,persent bus signals counter 1" newline hexmask.long.word 0x0 0.--15. 1. "REG0,present bus signals counter 0" repeat.end repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) rgroup.long ($2+0x7950)++0x3 line.long 0x0 "RGX_CR_TPU_MCU_L0_PERF_COUNTER_0_$1,RGX_CR_TPU_MCU_L0_PERF_COUNTER_0_0" hexmask.long 0x0 0.--31. 1. "REG,counter a0" repeat.end repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) rgroup.long ($2+0x7958)++0x3 line.long 0x0 "RGX_CR_TPU_MCU_L0_PERF_COUNTER_1_$1,RGX_CR_TPU_MCU_L0_PERF_COUNTER_1_0" hexmask.long 0x0 0.--31. 1. "REG,counter a0" repeat.end repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) rgroup.long ($2+0x7960)++0x3 line.long 0x0 "RGX_CR_TPU_MCU_L0_PERF_COUNTER_2_$1,RGX_CR_TPU_MCU_L0_PERF_COUNTER_2_0" hexmask.long 0x0 0.--31. 1. "REG,counter a0" repeat.end repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) rgroup.long ($2+0x7968)++0x3 line.long 0x0 "RGX_CR_TPU_MCU_L0_PERF_COUNTER_3_$1,RGX_CR_TPU_MCU_L0_PERF_COUNTER_3_0" hexmask.long 0x0 0.--31. 1. "REG,counter a0" repeat.end group.long 0x8000++0xF line.long 0x0 "RGX_CR_USC_INDIRECT_0,RGX_CR_USC_INDIRECT_0" hexmask.long 0x0 4.--31. 1. "Reserved_4,Reserved_4" newline hexmask.long.byte 0x0 0.--3. 1. "ADDRESS,ADDRESS" line.long 0x4 "RGX_CR_USC_INDIRECT_1,RGX_CR_USC_INDIRECT_1" hexmask.long 0x4 0.--31. 1. "Reserved_4,Reserved_4" line.long 0x8 "RGX_CR_TPU_MCU_L0_INDIRECT_0,RGX_CR_TPU_MCU_L0_INDIRECT_0" hexmask.long 0x8 3.--31. 1. "Reserved_3,Reserved_3" newline bitfld.long 0x8 0.--2. "ADDRESS,ADDRESS" "0,1,2,3,4,5,6,7" line.long 0xC "RGX_CR_TPU_MCU_L0_INDIRECT_1,RGX_CR_TPU_MCU_L0_INDIRECT_1" hexmask.long 0xC 0.--31. 1. "Reserved_3,Reserved_3" group.long 0x8020++0x17 line.long 0x0 "RGX_CR_USC_TPU_LOW_PRECISION_ENABLE_0,Enable signal to use low precision across USC and TPU (TAG) in coordinates. gradients and LOD value (calculated or supplied)" hexmask.long 0x0 1.--31. 1. "Reserved_1,Reserved_1" newline bitfld.long 0x0 0. "VALUE,VALUE" "0,1" line.long 0x4 "RGX_CR_USC_TPU_LOW_PRECISION_ENABLE_1,Enable signal to use low precision across USC and TPU (TAG) in coordinates. gradients and LOD value (calculated or supplied)" hexmask.long 0x4 0.--31. 1. "Reserved_1,Reserved_1" line.long 0x8 "RGX_CR_TPU_MCU_L0_PERF_INDIRECT_0,RGX_CR_TPU_MCU_L0_PERF_INDIRECT_0" hexmask.long 0x8 3.--31. 1. "Reserved_3,Reserved_3" newline bitfld.long 0x8 0.--2. "ADDRESS,ADDRESS" "0,1,2,3,4,5,6,7" line.long 0xC "RGX_CR_TPU_MCU_L0_PERF_INDIRECT_1,RGX_CR_TPU_MCU_L0_PERF_INDIRECT_1" hexmask.long 0xC 0.--31. 1. "Reserved_3,Reserved_3" line.long 0x10 "RGX_CR_USC_PERF_INDIRECT_0,RGX_CR_USC_PERF_INDIRECT_0" hexmask.long 0x10 4.--31. 1. "Reserved_4,Reserved_4" newline hexmask.long.byte 0x10 0.--3. 1. "ADDRESS,ADDRESS" line.long 0x14 "RGX_CR_USC_PERF_INDIRECT_1,RGX_CR_USC_PERF_INDIRECT_1" hexmask.long 0x14 0.--31. 1. "Reserved_4,Reserved_4" group.long 0x8100++0x27 line.long 0x0 "RGX_CR_USC_PERF_0,RGX_CR_USC_PERF_0" hexmask.long 0x0 5.--31. 1. "Reserved_5,Reserved_5" newline bitfld.long 0x0 4. "CLR_3,clear counter 3" "0,1" newline bitfld.long 0x0 3. "CLR_2,clear counter 2" "0,1" newline bitfld.long 0x0 2. "CLR_1,clear counter 1" "0,1" newline bitfld.long 0x0 1. "CLR_0,clear counter 0" "0,1" newline bitfld.long 0x0 0. "CTRL_ENABLE,enables the perf bus counters" "0,1" line.long 0x4 "RGX_CR_USC_PERF_1,RGX_CR_USC_PERF_1" hexmask.long 0x4 0.--31. 1. "Reserved_5,Reserved_5" line.long 0x8 "RGX_CR_USC_PERF_SELECT0_0,RGX_CR_USC_PERF_SELECT0_0" hexmask.long.word 0x8 22.--31. 1. "Reserved_22,Reserved_22" newline bitfld.long 0x8 21. "MODE,reduction mode 0: bitwise increments 1: unsigned count increment" "bitwise increments,unsigned count increment" newline hexmask.long.byte 0x8 16.--20. 1. "GROUP_SELECT,group select see full PERF documenusction for signals in each group" newline hexmask.long.word 0x8 0.--15. 1. "BIT_SELECT,bit mask for enabled signals in group" line.long 0xC "RGX_CR_USC_PERF_SELECT0_1,RGX_CR_USC_PERF_SELECT0_1" bitfld.long 0xC 30.--31. "Reserved_62,Reserved_62" "0,1,2,3" newline hexmask.long.word 0xC 16.--29. 1. "BATCH_MAX,this is the min batch number which will be counted in this group" newline bitfld.long 0xC 14.--15. "Reserved_46,Reserved_46" "0,1,2,3" newline hexmask.long.word 0xC 0.--13. 1. "BATCH_MIN,this is the min batch number which will be counted in this group" line.long 0x10 "RGX_CR_USC_PERF_SELECT1_0,RGX_CR_USC_PERF_SELECT1_0" hexmask.long.word 0x10 22.--31. 1. "Reserved_22,Reserved_22" newline bitfld.long 0x10 21. "MODE,reduction mode 0: bitwise increments 1: unsigned count increment" "bitwise increments,unsigned count increment" newline hexmask.long.byte 0x10 16.--20. 1. "GROUP_SELECT,group select see full PERF documenusction for signals in each group" newline hexmask.long.word 0x10 0.--15. 1. "BIT_SELECT,bit mask for enabled signals in group" line.long 0x14 "RGX_CR_USC_PERF_SELECT1_1,RGX_CR_USC_PERF_SELECT1_1" bitfld.long 0x14 30.--31. "Reserved_62,Reserved_62" "0,1,2,3" newline hexmask.long.word 0x14 16.--29. 1. "BATCH_MAX,this is the min batch number which will be counted in this group" newline bitfld.long 0x14 14.--15. "Reserved_46,Reserved_46" "0,1,2,3" newline hexmask.long.word 0x14 0.--13. 1. "BATCH_MIN,this is the min batch number which will be counted in this group" line.long 0x18 "RGX_CR_USC_PERF_SELECT2_0,RGX_CR_USC_PERF_SELECT2_0" hexmask.long.word 0x18 22.--31. 1. "Reserved_22,Reserved_22" newline bitfld.long 0x18 21. "MODE,reduction mode 0: bitwise increments 1: unsigned count increment" "bitwise increments,unsigned count increment" newline hexmask.long.byte 0x18 16.--20. 1. "GROUP_SELECT,group select see full PERF documenusction for signals in each group" newline hexmask.long.word 0x18 0.--15. 1. "BIT_SELECT,bit mask for enabled signals in group" line.long 0x1C "RGX_CR_USC_PERF_SELECT2_1,RGX_CR_USC_PERF_SELECT2_1" bitfld.long 0x1C 30.--31. "Reserved_62,Reserved_62" "0,1,2,3" newline hexmask.long.word 0x1C 16.--29. 1. "BATCH_MAX,this is the min batch number which will be counted in this group" newline bitfld.long 0x1C 14.--15. "Reserved_46,Reserved_46" "0,1,2,3" newline hexmask.long.word 0x1C 0.--13. 1. "BATCH_MIN,this is the min batch number which will be counted in this group" line.long 0x20 "RGX_CR_USC_PERF_SELECT3_0,RGX_CR_USC_PERF_SELECT3_0" hexmask.long.word 0x20 22.--31. 1. "Reserved_22,Reserved_22" newline bitfld.long 0x20 21. "MODE,reduction mode 0: bitwise increments 1: unsigned count increment" "bitwise increments,unsigned count increment" newline hexmask.long.byte 0x20 16.--20. 1. "GROUP_SELECT,group select see full PERF documenusction for signals in each group" newline hexmask.long.word 0x20 0.--15. 1. "BIT_SELECT,bit mask for enabled signals in group" line.long 0x24 "RGX_CR_USC_PERF_SELECT3_1,RGX_CR_USC_PERF_SELECT3_1" bitfld.long 0x24 30.--31. "Reserved_62,Reserved_62" "0,1,2,3" newline hexmask.long.word 0x24 16.--29. 1. "BATCH_MAX,this is the min batch number which will be counted in this group" newline bitfld.long 0x24 14.--15. "Reserved_46,Reserved_46" "0,1,2,3" newline hexmask.long.word 0x24 0.--13. 1. "BATCH_MIN,this is the min batch number which will be counted in this group" repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) rgroup.long ($2+0x8148)++0x3 line.long 0x0 "RGX_CR_USC_PERF_SELECTED_BITS_$1,RGX_CR_USC_PERF_SELECTED_BITS_0" hexmask.long.word 0x0 16.--31. 1. "REG1,persent bus signals counter 1" newline hexmask.long.word 0x0 0.--15. 1. "REG0,present bus signals counter 0" repeat.end repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) rgroup.long ($2+0x8150)++0x3 line.long 0x0 "RGX_CR_USC_PERF_COUNTER_0_$1,RGX_CR_USC_PERF_COUNTER_0_0" hexmask.long 0x0 0.--31. 1. "REG,counter a0" repeat.end repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) rgroup.long ($2+0x8158)++0x3 line.long 0x0 "RGX_CR_USC_PERF_COUNTER_1_$1,RGX_CR_USC_PERF_COUNTER_1_0" hexmask.long 0x0 0.--31. 1. "REG,counter a0" repeat.end repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) rgroup.long ($2+0x8160)++0x3 line.long 0x0 "RGX_CR_USC_PERF_COUNTER_2_$1,RGX_CR_USC_PERF_COUNTER_2_0" hexmask.long 0x0 0.--31. 1. "REG,counter a0" repeat.end repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) rgroup.long ($2+0x8168)++0x3 line.long 0x0 "RGX_CR_USC_PERF_COUNTER_3_$1,RGX_CR_USC_PERF_COUNTER_3_0" hexmask.long 0x0 0.--31. 1. "REG,counter a0" repeat.end group.long 0x8238++0x7 line.long 0x0 "RGX_CR_RASTERISATION_INDIRECT_0,RGX_CR_RASTERISATION_INDIRECT_0" hexmask.long 0x0 4.--31. 1. "Reserved_4,Reserved_4" newline hexmask.long.byte 0x0 0.--3. 1. "ADDRESS,ADDRESS" line.long 0x4 "RGX_CR_RASTERISATION_INDIRECT_1,RGX_CR_RASTERISATION_INDIRECT_1" hexmask.long 0x4 0.--31. 1. "Reserved_4,Reserved_4" group.long 0x8318++0x7 line.long 0x0 "RGX_CR_RASTERISATION_PERF_INDIRECT_0,RGX_CR_RASTERISATION_PERF_INDIRECT_0" hexmask.long 0x0 4.--31. 1. "Reserved_4,Reserved_4" newline hexmask.long.byte 0x0 0.--3. 1. "ADDRESS,ADDRESS" line.long 0x4 "RGX_CR_RASTERISATION_PERF_INDIRECT_1,RGX_CR_RASTERISATION_PERF_INDIRECT_1" hexmask.long 0x4 0.--31. 1. "Reserved_4,Reserved_4" group.long 0x83D8++0x1F line.long 0x0 "RGX_CR_PBE_PERF_INDIRECT_0,RGX_CR_PBE_PERF_INDIRECT_0" hexmask.long 0x0 4.--31. 1. "Reserved_4,Reserved_4" newline hexmask.long.byte 0x0 0.--3. 1. "ADDRESS,ADDRESS" line.long 0x4 "RGX_CR_PBE_PERF_INDIRECT_1,RGX_CR_PBE_PERF_INDIRECT_1" hexmask.long 0x4 0.--31. 1. "Reserved_4,Reserved_4" line.long 0x8 "RGX_CR_PBE_INDIRECT_0,RGX_CR_PBE_INDIRECT_0" hexmask.long 0x8 4.--31. 1. "Reserved_4,Reserved_4" newline hexmask.long.byte 0x8 0.--3. 1. "ADDRESS,ADDRESS" line.long 0xC "RGX_CR_PBE_INDIRECT_1,RGX_CR_PBE_INDIRECT_1" hexmask.long 0xC 0.--31. 1. "Reserved_4,Reserved_4" line.long 0x10 "RGX_CR_TPU_INDIRECT_0,RGX_CR_TPU_INDIRECT_0" hexmask.long 0x10 3.--31. 1. "Reserved_3,Reserved_3" newline bitfld.long 0x10 0.--2. "ADDRESS,ADDRESS" "0,1,2,3,4,5,6,7" line.long 0x14 "RGX_CR_TPU_INDIRECT_1,RGX_CR_TPU_INDIRECT_1" hexmask.long 0x14 0.--31. 1. "Reserved_3,Reserved_3" line.long 0x18 "RGX_CR_TPU_PERF_INDIRECT_0,RGX_CR_TPU_PERF_INDIRECT_0" hexmask.long 0x18 3.--31. 1. "Reserved_3,Reserved_3" newline bitfld.long 0x18 0.--2. "ADDRESS,ADDRESS" "0,1,2,3,4,5,6,7" line.long 0x1C "RGX_CR_TPU_PERF_INDIRECT_1,RGX_CR_TPU_PERF_INDIRECT_1" hexmask.long 0x1C 0.--31. 1. "Reserved_3,Reserved_3" group.long 0x8478++0x1F line.long 0x0 "RGX_CR_PBE_PERF_0,RGX_CR_PBE_PERF_0" hexmask.long 0x0 5.--31. 1. "Reserved_5,Reserved_5" newline bitfld.long 0x0 4. "CLR_3,clear counter 3" "0,1" newline bitfld.long 0x0 3. "CLR_2,clear counter 2" "0,1" newline bitfld.long 0x0 2. "CLR_1,clear counter 1" "0,1" newline bitfld.long 0x0 1. "CLR_0,clear counter 0" "0,1" newline bitfld.long 0x0 0. "CTRL_ENABLE,enables the perf bus counters" "0,1" line.long 0x4 "RGX_CR_PBE_PERF_1,RGX_CR_PBE_PERF_1" hexmask.long 0x4 0.--31. 1. "Reserved_5,Reserved_5" line.long 0x8 "RGX_CR_PBE_PERF_SELECT0_0,RGX_CR_PBE_PERF_SELECT0_0" hexmask.long.word 0x8 22.--31. 1. "Reserved_22,Reserved_22" newline bitfld.long 0x8 21. "MODE,reduction mode 0: bitwise increments 1: unsigned count increment" "bitwise increments,unsigned count increment" newline hexmask.long.byte 0x8 16.--20. 1. "GROUP_SELECT,group select see full PERF documentation for signals in each group" newline hexmask.long.word 0x8 0.--15. 1. "BIT_SELECT,bit mask for enabled signals in group" line.long 0xC "RGX_CR_PBE_PERF_SELECT0_1,RGX_CR_PBE_PERF_SELECT0_1" bitfld.long 0xC 30.--31. "Reserved_62,Reserved_62" "0,1,2,3" newline hexmask.long.word 0xC 16.--29. 1. "BATCH_MAX,this is the max batch number which will be counted in this group" newline bitfld.long 0xC 14.--15. "Reserved_46,Reserved_46" "0,1,2,3" newline hexmask.long.word 0xC 0.--13. 1. "BATCH_MIN,this is the min batch number which will be counted in this group" line.long 0x10 "RGX_CR_PBE_PERF_SELECT1_0,RGX_CR_PBE_PERF_SELECT1_0" hexmask.long.word 0x10 22.--31. 1. "Reserved_22,Reserved_22" newline bitfld.long 0x10 21. "MODE,reduction mode 0: bitwise increments 1: unsigned count increment" "bitwise increments,unsigned count increment" newline hexmask.long.byte 0x10 16.--20. 1. "GROUP_SELECT,group select see full PERF documentation for signals in each group" newline hexmask.long.word 0x10 0.--15. 1. "BIT_SELECT,bit mask for enabled signals in group" line.long 0x14 "RGX_CR_PBE_PERF_SELECT1_1,RGX_CR_PBE_PERF_SELECT1_1" bitfld.long 0x14 30.--31. "Reserved_62,Reserved_62" "0,1,2,3" newline hexmask.long.word 0x14 16.--29. 1. "BATCH_MAX,this is the max batch number which will be counted in this group" newline bitfld.long 0x14 14.--15. "Reserved_46,Reserved_46" "0,1,2,3" newline hexmask.long.word 0x14 0.--13. 1. "BATCH_MIN,this is the min batch number which will be counted in this group" line.long 0x18 "RGX_CR_PBE_PERF_SELECT2_0,RGX_CR_PBE_PERF_SELECT2_0" hexmask.long.word 0x18 22.--31. 1. "Reserved_22,Reserved_22" newline bitfld.long 0x18 21. "MODE,reduction mode 0: bitwise increments 1: unsigned count increment" "bitwise increments,unsigned count increment" newline hexmask.long.byte 0x18 16.--20. 1. "GROUP_SELECT,group select see full PERF documentation for signals in each group" newline hexmask.long.word 0x18 0.--15. 1. "BIT_SELECT,bit mask for enabled signals in group" line.long 0x1C "RGX_CR_PBE_PERF_SELECT2_1,RGX_CR_PBE_PERF_SELECT2_1" bitfld.long 0x1C 30.--31. "Reserved_62,Reserved_62" "0,1,2,3" newline hexmask.long.word 0x1C 16.--29. 1. "BATCH_MAX,this is the max batch number which will be counted in this group" newline bitfld.long 0x1C 14.--15. "Reserved_46,Reserved_46" "0,1,2,3" newline hexmask.long.word 0x1C 0.--13. 1. "BATCH_MIN,this is the min batch number which will be counted in this group" group.long 0x84A0++0x7 line.long 0x0 "RGX_CR_PBE_PERF_SELECT3_0,RGX_CR_PBE_PERF_SELECT3_0" hexmask.long.word 0x0 22.--31. 1. "Reserved_22,Reserved_22" newline bitfld.long 0x0 21. "MODE,reduction mode 0: bitwise increments 1: unsigned count increment" "bitwise increments,unsigned count increment" newline hexmask.long.byte 0x0 16.--20. 1. "GROUP_SELECT,group select see full PERF documentation for signals in each group" newline hexmask.long.word 0x0 0.--15. 1. "BIT_SELECT,bit mask for enabled signals in group" line.long 0x4 "RGX_CR_PBE_PERF_SELECT3_1,RGX_CR_PBE_PERF_SELECT3_1" bitfld.long 0x4 30.--31. "Reserved_62,Reserved_62" "0,1,2,3" newline hexmask.long.word 0x4 16.--29. 1. "BATCH_MAX,this is the max batch number which will be counted in this group" newline bitfld.long 0x4 14.--15. "Reserved_46,Reserved_46" "0,1,2,3" newline hexmask.long.word 0x4 0.--13. 1. "BATCH_MIN,this is the min batch number which will be counted in this group" repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) rgroup.long ($2+0x84A8)++0x3 line.long 0x0 "RGX_CR_PBE_PERF_SELECTED_BITS_$1,RGX_CR_PBE_PERF_SELECTED_BITS_0" hexmask.long.word 0x0 16.--31. 1. "REG1,persent bus signals counter 1" newline hexmask.long.word 0x0 0.--15. 1. "REG0,present bus signals counter 0" repeat.end repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) rgroup.long ($2+0x84B0)++0x3 line.long 0x0 "RGX_CR_PBE_PERF_COUNTER_0_$1,RGX_CR_PBE_PERF_COUNTER_0_0" hexmask.long 0x0 0.--31. 1. "REG,counter a0" repeat.end repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) rgroup.long ($2+0x84B8)++0x3 line.long 0x0 "RGX_CR_PBE_PERF_COUNTER_1_$1,RGX_CR_PBE_PERF_COUNTER_1_0" hexmask.long 0x0 0.--31. 1. "REG,counter a0" repeat.end repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) rgroup.long ($2+0x84C0)++0x3 line.long 0x0 "RGX_CR_PBE_PERF_COUNTER_2_$1,RGX_CR_PBE_PERF_COUNTER_2_0" hexmask.long 0x0 0.--31. 1. "REG,counter a0" repeat.end repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) rgroup.long ($2+0x84C8)++0x3 line.long 0x0 "RGX_CR_PBE_PERF_COUNTER_3_$1,RGX_CR_PBE_PERF_COUNTER_3_0" hexmask.long 0x0 0.--31. 1. "REG,counter a0" repeat.end group.long 0xA000++0x7 line.long 0x0 "RGX_CR_BIF_TRUST_0,Define Requestors/Data Masters which are Trusted/Untrusted and enable/disable the Memory Bus Security feature within the Core When enabled the GPU will emit the security signals out through the external memory interface." hexmask.long.word 0x0 17.--31. 1. "Reserved_17,Reserved_17" newline bitfld.long 0x0 16. "ENABLE,Enable Security feature: 0x1 = Enabled 0x0 = Disabled" "Disabled,Enabled" newline hexmask.long.byte 0x0 9.--15. 1. "DM_TRUSTED,Mask of bits which defines which of the remaining Data Masters are trusted: 0x1 = Trusted 0x0 = Untrusted" newline bitfld.long 0x0 8. "OTHER_COMPUTE_DM_TRUSTED,Defines whether other accesses with the Compute DM are trusted: 0x1 = Trusted 0x0 = Untrusted" "Untrusted,Trusted" newline bitfld.long 0x0 7. "MCU_COMPUTE_DM_TRUSTED,Defines whether MCU accesses with the Compute DM are trusted: 0x1 = Trusted 0x0 = Untrusted" "Untrusted,Trusted" newline bitfld.long 0x0 6. "PBE_COMPUTE_DM_TRUSTED,Defines whether PBE accesses with the Compute DM are trusted: 0x1 = Trusted 0x0 = Untrusted" "Untrusted,Trusted" newline bitfld.long 0x0 5. "OTHER_PIXEL_DM_TRUSTED,Defines whether other accesses with the Pixel DM are trusted: 0x1 = Trusted 0x0 = Untrusted" "Untrusted,Trusted" newline bitfld.long 0x0 4. "MCU_PIXEL_DM_TRUSTED,Defines whether MCU accesses with the Pixel DM are trusted: 0x1 = Trusted 0x0 = Untrusted" "Untrusted,Trusted" newline bitfld.long 0x0 3. "PBE_PIXEL_DM_TRUSTED,Defines whether PBE accesses with the Pixel DM are trusted: 0x1 = Trusted 0x0 = Untrusted" "Untrusted,Trusted" newline bitfld.long 0x0 2. "OTHER_VERTEX_DM_TRUSTED,Defines whether other accesses with the Vertex DM are trusted: 0x1 = Trusted 0x0 = Untrusted" "Untrusted,Trusted" newline bitfld.long 0x0 1. "MCU_VERTEX_DM_TRUSTED,Defines whether MCU accesses with the Vertex DM are trusted: 0x1 = Trusted 0x0 = Untrusted" "Untrusted,Trusted" newline bitfld.long 0x0 0. "PBE_VERTEX_DM_TRUSTED,Defines whether PBE accesses with the Vertex DM are trusted: 0x1 = Trusted 0x0 = Untrusted" "Untrusted,Trusted" line.long 0x4 "RGX_CR_BIF_TRUST_1,Define Requestors/Data Masters which are Trusted/Untrusted and enable/disable the Memory Bus Security feature within the Core When enabled the GPU will emit the security signals out through the external memory interface." hexmask.long 0x4 0.--31. 1. "Reserved_17,Reserved_17" group.long 0xA100++0x7 line.long 0x0 "RGX_CR_SYS_BUS_SECURE_0,Setting this register secures the IMG Configuration Registers from the System Bus. In secure mode all registers have read access only by default. When secure mode is being set. the register must be read back to confirm that the.." hexmask.long 0x0 1.--31. 1. "Reserved_1,Reserved_1" newline bitfld.long 0x0 0. "ENABLE,

0 = No System Bus Security

1 = System Bus Restricted

" "No System Bus Security

1 = System Bus..,?" line.long 0x4 "RGX_CR_SYS_BUS_SECURE_1,Setting this register secures the IMG Configuration Registers from the System Bus. In secure mode all registers have read access only by default. When secure mode is being set. the register must be read back to confirm that the.." hexmask.long 0x4 0.--31. 1. "Reserved_1,Reserved_1" repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) group.long ($2+0xA500)++0x3 line.long 0x0 "RGX_CR_FB_CDC_V3_$1,Framebuffer constant detection configuraton registers" hexmask.long.byte 0x0 24.--31. 1. "FBC_FBDC_UV_VAL1,video pixel format constant value" newline hexmask.long.byte 0x0 16.--23. 1. "FBC_FBDC_Y_VAL1,video pixel format constant value" newline hexmask.long.byte 0x0 8.--15. 1. "FBC_FBDC_UV_VAL0,video pixel format constant value" newline hexmask.long.byte 0x0 0.--7. 1. "FBC_FBDC_Y_VAL0,video pixel format constant value" repeat.end group.long 0xA508++0x7 line.long 0x0 "RGX_CR_FBC_FBDC_CR_FILTER_0,FBCDC corrupt tile filter register" hexmask.long 0x0 5.--31. 1. "Reserved_5,Reserved_5" newline hexmask.long.byte 0x0 1.--4. 1. "CLEAR,Clear corrupt tile filter status 1 bit per requester" newline bitfld.long 0x0 0. "ENABLE,Enable corrupt tile filter" "0,1" line.long 0x4 "RGX_CR_FBC_FBDC_CR_FILTER_1,FBCDC corrupt tile filter register" hexmask.long 0x4 0.--31. 1. "Reserved_5,Reserved_5" rgroup.long 0xA510++0x7 line.long 0x0 "RGX_CR_FBC_FBDC_CR_FILTER_STATUS_0,FBCDC corrupt tile filter register" hexmask.long 0x0 4.--31. 1. "Reserved_4,Reserved_4" newline hexmask.long.byte 0x0 0.--3. 1. "FBC_FBDC_CR_FILTER_STATUS,Status of corrupt tile filter 1 bit per requester" line.long 0x4 "RGX_CR_FBC_FBDC_CR_FILTER_STATUS_1,FBCDC corrupt tile filter register" hexmask.long 0x4 0.--31. 1. "Reserved_4,Reserved_4" group.long 0xA518++0x7 line.long 0x0 "RGX_CR_FBC_FBDC_CR_MODE_V3_1_0,Enable FBC_FBDC mode V3_1 for FBC_FBDC textures" hexmask.long 0x0 1.--31. 1. "Reserved_1,Reserved_1" newline bitfld.long 0x0 0. "EN,Enable FBC_FBDC mode V3_1 for FBCDC formats defaults to V3" "0,1" line.long 0x4 "RGX_CR_FBC_FBDC_CR_MODE_V3_1_1,Enable FBC_FBDC mode V3_1 for FBC_FBDC textures" hexmask.long 0x4 0.--31. 1. "Reserved_1,Reserved_1" repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) group.long ($2+0xA520)++0x3 line.long 0x0 "RGX_CR_FBCDC_CC_$1,RGX_CR_FBCDC_CC_0" hexmask.long.byte 0x0 24.--31. 1. "CH3_VAL0,Constant colour detected value for channel 3." newline hexmask.long.byte 0x0 16.--23. 1. "CH2_VAL0,Constant colour detected value for channel 2." newline hexmask.long.byte 0x0 8.--15. 1. "CH1_VAL0,Constant colour detected value for channel 1." newline hexmask.long.byte 0x0 0.--7. 1. "CH0_VAL0,Constant colour detected value for channel 0." repeat.end repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) group.long ($2+0xA528)++0x3 line.long 0x0 "RGX_CR_FBCDC_CC_YUV_$1,RGX_CR_FBCDC_CC_YUV_0" hexmask.long.byte 0x0 26.--31. 1. "Reserved_26,Reserved_26" newline hexmask.long.word 0x0 16.--25. 1. "UV_VAL0,Constant colour detected value uv-plane." newline hexmask.long.byte 0x0 10.--15. 1. "Reserved_10,Reserved_10" newline hexmask.long.word 0x0 0.--9. 1. "Y_VAL0,Constant colour detected value y-plane." repeat.end group.long 0xB000++0x7 line.long 0x0 "RGX_CR_PIPELINE_STATS_ENABLE_0,This register globally enables per DM pipeline statistics counters. Set this register to '1' to allow pipeline statistics counters to increment. Set this register to '0' to inhibit pipeline statistics from incrementing." hexmask.long.word 0x0 17.--31. 1. "Reserved_17,Reserved_17" newline bitfld.long 0x0 16. "COMPUTE,COMPUTE" "0,1" newline hexmask.long.byte 0x0 9.--15. 1. "Reserved_9,Reserved_9" newline bitfld.long 0x0 8. "_3D,_3D" "0,1" newline hexmask.long.byte 0x0 1.--7. 1. "Reserved_1,Reserved_1" newline bitfld.long 0x0 0. "TA,TA" "0,1" line.long 0x4 "RGX_CR_PIPELINE_STATS_ENABLE_1,This register globally enables per DM pipeline statistics counters. Set this register to '1' to allow pipeline statistics counters to increment. Set this register to '0' to inhibit pipeline statistics from incrementing." hexmask.long 0x4 0.--31. 1. "Reserved_17,Reserved_17" wgroup.long 0xB008++0x7 line.long 0x0 "RGX_CR_PIPELINE_STATS_CLEAR_0,Writing '1' to fields of this register resets the pipeline statistics counters per DM The pipeline statistics should normally be cleared before each TA. 3D or Compute kick" hexmask.long.word 0x0 17.--31. 1. "Reserved_17,Reserved_17" newline bitfld.long 0x0 16. "COMPUTE,COMPUTE" "0,1" newline hexmask.long.byte 0x0 9.--15. 1. "Reserved_9,Reserved_9" newline bitfld.long 0x0 8. "_3D,_3D" "0,1" newline hexmask.long.byte 0x0 1.--7. 1. "Reserved_1,Reserved_1" newline bitfld.long 0x0 0. "TA,TA" "0,1" line.long 0x4 "RGX_CR_PIPELINE_STATS_CLEAR_1,Writing '1' to fields of this register resets the pipeline statistics counters per DM The pipeline statistics should normally be cleared before each TA. 3D or Compute kick" hexmask.long 0x4 0.--31. 1. "Reserved_17,Reserved_17" repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) rgroup.long ($2+0xB010)++0x3 line.long 0x0 "RGX_CR_PIPELINE_STATS_IA_VERTICES_$1,Number of vertices the Input Assembly stage generated (not subtracting any caching)" hexmask.long 0x0 0.--31. 1. "COUNT,COUNT" repeat.end repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) rgroup.long ($2+0xB018)++0x3 line.long 0x0 "RGX_CR_PIPELINE_STATS_IA_PRIMITIVES_$1,Number of primitives the Input Assembly stage generated" hexmask.long 0x0 0.--31. 1. "COUNT,COUNT" repeat.end repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) rgroup.long ($2+0xB020)++0x3 line.long 0x0 "RGX_CR_PIPELINE_STATS_VS_INVOCATIONS_$1,Number of times the Vertex Shader is executed" hexmask.long 0x0 0.--31. 1. "COUNT,COUNT" repeat.end repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) rgroup.long ($2+0xB038)++0x3 line.long 0x0 "RGX_CR_PIPELINE_STATS_GS_INVOCATIONS_$1,Number of times the Geometry Shader is executed" hexmask.long 0x0 0.--31. 1. "COUNT,COUNT" repeat.end repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) rgroup.long ($2+0xB040)++0x3 line.long 0x0 "RGX_CR_PIPELINE_STATS_GS_PRIMITIVES_$1,Number of primitives the Geometry Shader generated" hexmask.long 0x0 0.--31. 1. "COUNT,COUNT" repeat.end repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) rgroup.long ($2+0xB048)++0x3 line.long 0x0 "RGX_CR_PIPELINE_STATS_C_INVOCATIONS_$1,Number of times the Clipper is executed" hexmask.long 0x0 0.--31. 1. "COUNT,COUNT" repeat.end repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) rgroup.long ($2+0xB050)++0x3 line.long 0x0 "RGX_CR_PIPELINE_STATS_C_PRIMITIVES_$1,Number of primitives the Clipper generated" hexmask.long 0x0 0.--31. 1. "COUNT,COUNT" repeat.end repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) rgroup.long ($2+0xB058)++0x3 line.long 0x0 "RGX_CR_PIPELINE_STATS_PS_INVOCATIONS_$1,Number of times the Pixel Shader is executed" hexmask.long 0x0 0.--31. 1. "COUNT,COUNT" repeat.end repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) rgroup.long ($2+0xB060)++0x3 line.long 0x0 "RGX_CR_PIPELINE_STATS_CS_INVOCATIONS_$1,Number of times the Compute Shader is executed" hexmask.long 0x0 0.--31. 1. "COUNT,COUNT" repeat.end rgroup.long 0xE000++0x7 line.long 0x0 "RGX_CR_CACHE_CFI_EVENT_0,Global Flush and Invalidation Pending bits for all Texture and Data Caches in the design. The bits are set high after a Flush/Invalidate is requested and will be set low again as each cache in turn completes processing. therefore.." hexmask.long.word 0x0 16.--31. 1. "MCU_L0_PENDING,1 Indicates there is a pending global CFI operation on the specified MCU L0 cache (there can be up to 16 MCU L0 caches depending on the number of clusters)" newline hexmask.long.word 0x0 0.--15. 1. "MADD_PENDING,1 Indicates there is a pending global CFI operation on the specified MADD Texture cache (there can be up to 16 MADD caches depending on the number of clusters)" line.long 0x4 "RGX_CR_CACHE_CFI_EVENT_1,Global Flush and Invalidation Pending bits for all Texture and Data Caches in the design. The bits are set high after a Flush/Invalidate is requested and will be set low again as each cache in turn completes processing. therefore.." hexmask.long.tbyte 0x4 9.--31. 1. "Reserved_41,Reserved_41" newline bitfld.long 0x4 8. "SLC_PENDING,1 Indicates there is a pending global CFI operation on the SLC cache" "0,1" newline hexmask.long.byte 0x4 0.--7. 1. "MCU_L1_PENDING,1 Indicates there is a pending global CFI operation on the specified MCU L1 cache (there can be up to 8 MCU L1 caches depending on the number of clusters)" group.long 0xE138++0x7 line.long 0x0 "RGX_CR_MMU_CTRL_INVAL_0,MMU invalidation control registers" hexmask.long.tbyte 0x0 12.--31. 1. "Reserved_12,Reserved_12" newline bitfld.long 0x0 11. "ALL_CONTEXTS,When ALL_CONTEXTS is set all context ids get invalidated (global invalidation)" "0,1" newline hexmask.long.byte 0x0 3.--10. 1. "CONTEXT,When ALL_CONTEXTS is not set this field specifies the context id to be invalidated (per-context invalidation)" newline bitfld.long 0x0 2. "PC,Invalidates PC PD & PT" "0,1" newline bitfld.long 0x0 1. "PD,Invalidates PD & PT" "0,1" newline bitfld.long 0x0 0. "PT,Invalidates PT" "0,1" line.long 0x4 "RGX_CR_MMU_CTRL_INVAL_1,MMU invalidation control registers" hexmask.long 0x4 0.--31. 1. "Reserved_12,Reserved_12" repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) rgroup.long ($2+0xF100)++0x3 line.long 0x0 "RGX_CR_FB_CDC_PWR_NUM_$1,Power Monitoring registers for the FBCDC" hexmask.long 0x0 0.--31. 1. "FBDC,Number of accesses to the FBDC per clock" repeat.end repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) rgroup.long ($2+0xF108)++0x3 line.long 0x0 "RGX_CR_FB_CDC_PWR_NUM_MCU_$1,Power Monitoring registers for the FBCDC" hexmask.long 0x0 0.--31. 1. "FBTC,Number of accesses to the MCU FBTC per clock" repeat.end rgroup.long 0xF220++0xF line.long 0x0 "RGX_CR_BIF_BLACKPEARL_RTN_FIFO_WORD_COUNT_0,Blackpearl BIF return FIFO word count" hexmask.long.tbyte 0x0 9.--31. 1. "Reserved_9,Reserved_9" newline hexmask.long.word 0x0 0.--8. 1. "COUNTER,COUNTER" line.long 0x4 "RGX_CR_BIF_BLACKPEARL_RTN_FIFO_WORD_COUNT_1,Blackpearl BIF return FIFO word count" hexmask.long 0x4 0.--31. 1. "Reserved_9,Reserved_9" line.long 0x8 "RGX_CR_BIF_JONES_RTN_FIFO_WORD_COUNT_0,Jones BIF return FIFO word count" hexmask.long.tbyte 0x8 9.--31. 1. "Reserved_9,Reserved_9" newline hexmask.long.word 0x8 0.--8. 1. "COUNTER,COUNTER" line.long 0xC "RGX_CR_BIF_JONES_RTN_FIFO_WORD_COUNT_1,Jones BIF return FIFO word count" hexmask.long 0xC 0.--31. 1. "Reserved_9,Reserved_9" group.long 0xF258++0x7 line.long 0x0 "RGX_CR_TDM_GRIDOFFSET_0,Sample position grid offset for use when MSAA/ODAA is DISABLED DX (0.0.0.0) OpenGL (0.5.0.5) Acts as the 9th multisample position when MSAA is ENABLED." hexmask.long.tbyte 0x0 8.--31. 1. "Reserved_8,Reserved_8" newline hexmask.long.byte 0x0 4.--7. 1. "GRID_Y,Unsigned sub-pixel offset" newline hexmask.long.byte 0x0 0.--3. 1. "GRID_X,Unsigned sub-pixel offset" line.long 0x4 "RGX_CR_TDM_GRIDOFFSET_1,Sample position grid offset for use when MSAA/ODAA is DISABLED DX (0.0.0.0) OpenGL (0.5.0.5) Acts as the 9th multisample position when MSAA is ENABLED." hexmask.long 0x4 0.--31. 1. "Reserved_8,Reserved_8" repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) group.long ($2+0xF260)++0x3 line.long 0x0 "RGX_CR_TDM_MULTISAMPLECTL_$1,Sample position grid offset for use in 2x. 4x. 8xMSAA and ODAA modes." hexmask.long.byte 0x0 28.--31. 1. "MSAA_Y3,Unsigned sub-pixel offset for the 4th multisample Y position" newline hexmask.long.byte 0x0 24.--27. 1. "MSAA_X3,Unsigned sub-pixel offset for the 4th multisample X position" newline hexmask.long.byte 0x0 20.--23. 1. "MSAA_Y2,Unsigned sub-pixel offset for the 3rd multisample Y position" newline hexmask.long.byte 0x0 16.--19. 1. "MSAA_X2,Unsigned sub-pixel offset for the 3rd multisample X position" newline hexmask.long.byte 0x0 12.--15. 1. "MSAA_Y1,Unsigned sub-pixel offset for the 2nd multisample Y position" newline hexmask.long.byte 0x0 8.--11. 1. "MSAA_X1,Unsigned sub-pixel offset for the 2nd multisample X position" newline hexmask.long.byte 0x0 4.--7. 1. "MSAA_Y0,Unsigned sub-pixel offset for the 1st multisample Y position" newline hexmask.long.byte 0x0 0.--3. 1. "MSAA_X0,Unsigned sub-pixel offset for the 1st multisample X position" repeat.end group.long 0xF268++0x7 line.long 0x0 "RGX_CR_USC_CODE_BASE_2D_0,RGX_CR_USC_CODE_BASE_2D_0" hexmask.long 0x0 6.--31. 1. "ADDR,2D Data Master Code Base Register bits" newline hexmask.long.byte 0x0 0.--5. 1. "Reserved_0,Reserved_0" line.long 0x4 "RGX_CR_USC_CODE_BASE_2D_1,RGX_CR_USC_CODE_BASE_2D_1" hexmask.long.tbyte 0x4 8.--31. 1. "Reserved_40,Reserved_40" newline hexmask.long.byte 0x4 0.--7. 1. "ADDR,2D Data Master Code Base Register bits" group.long 0x10B00++0x7 line.long 0x0 "RGX_CR_MTS_SCHEDULE1_0,This register allows firmware tasks to be scheduled on the META (Garten) core." hexmask.long.tbyte 0x0 9.--31. 1. "Reserved_9,Reserved_9" newline bitfld.long 0x0 8. "HOST,Host Interrupte kick" "0,1" newline bitfld.long 0x0 6.--7. "PRIORITY,DataMaster Priority" "0,1,2,3" newline bitfld.long 0x0 5. "CONTEXT,CONTEXT" "0,1" newline bitfld.long 0x0 4. "TASK,TASK" "0,1" newline hexmask.long.byte 0x0 0.--3. 1. "DM,DataMaster Type" line.long 0x4 "RGX_CR_MTS_SCHEDULE1_1,This register allows firmware tasks to be scheduled on the META (Garten) core." hexmask.long 0x4 0.--31. 1. "Reserved_9,Reserved_9" rgroup.long 0x10B98++0x17 line.long 0x0 "RGX_CR_MTS_INTCTX1_0,This register contains the sideband data for the MTS internal interrupt context registers" bitfld.long 0x0 30.--31. "Reserved_30,Reserved_30" "0,1,2,3" newline hexmask.long.byte 0x0 22.--29. 1. "DM_HOST_SCHEDULE,A 1 bit counter per DM for host requests" newline hexmask.long.byte 0x0 16.--21. 1. "Reserved_16,Reserved_16" newline hexmask.long.byte 0x0 8.--15. 1. "DM_TIMER_SCHEDULE,A 1 bit counter per DM for timer requests" newline hexmask.long.byte 0x0 0.--7. 1. "DM_INTERRUPT_SCHEDULE,A 1 bit counter per DM for interrupt requests" line.long 0x4 "RGX_CR_MTS_INTCTX1_1,This register contains the sideband data for the MTS internal interrupt context registers" hexmask.long 0x4 0.--31. 1. "Reserved_30,Reserved_30" line.long 0x8 "RGX_CR_MTS_BGCTX1_0,This register contains the sideband data for the MTS internal background context registers" hexmask.long.tbyte 0x8 8.--31. 1. "Reserved_8,Reserved_8" newline hexmask.long.byte 0x8 0.--7. 1. "DM_NONCOUNTED_SCHEDULE,A 1 bit counter per DM for non-counted background request" line.long 0xC "RGX_CR_MTS_BGCTX1_1,This register contains the sideband data for the MTS internal background context registers" hexmask.long 0xC 0.--31. 1. "Reserved_8,Reserved_8" line.long 0x10 "RGX_CR_MTS_BGCTX_COUNTED_SCHEDULE1_0,This register contains the sideband data for the MTS internal counted background context counters" hexmask.long.byte 0x10 24.--31. 1. "DM3,A 8 bit counter for DM3" newline hexmask.long.byte 0x10 16.--23. 1. "DM2,A 8 bit counter for DM2" newline hexmask.long.byte 0x10 8.--15. 1. "DM1,A 8 bit counter for DM1" newline hexmask.long.byte 0x10 0.--7. 1. "DM0,A 8 bit counter for DM0" line.long 0x14 "RGX_CR_MTS_BGCTX_COUNTED_SCHEDULE1_1,This register contains the sideband data for the MTS internal counted background context counters" hexmask.long.word 0x14 16.--31. 1. "Reserved_48,Reserved_48" newline hexmask.long.byte 0x14 8.--15. 1. "DM5,A 8 bit counter for DM5" newline hexmask.long.byte 0x14 0.--7. 1. "DM4,A 8 bit counter for DM4" rgroup.long 0x10BD8++0x7 line.long 0x0 "RGX_CR_IRQ_OS1_EVENT_STATUS_0,This register indicates the source of a per-OS host interrupt. This register is set by the firmware and cleared by the host." hexmask.long 0x0 1.--31. 1. "Reserved_1,Reserved_1" newline bitfld.long 0x0 0. "SOURCE,SOURCE" "0,1" line.long 0x4 "RGX_CR_IRQ_OS1_EVENT_STATUS_1,This register indicates the source of a per-OS host interrupt. This register is set by the firmware and cleared by the host." hexmask.long 0x4 0.--31. 1. "Reserved_1,Reserved_1" group.long 0x10BE8++0x7 line.long 0x0 "RGX_CR_IRQ_OS1_EVENT_CLEAR_0,This register clears a per-OS host interrupt." hexmask.long 0x0 1.--31. 1. "Reserved_1,Reserved_1" newline bitfld.long 0x0 0. "SOURCE,SOURCE" "0,1" line.long 0x4 "RGX_CR_IRQ_OS1_EVENT_CLEAR_1,This register clears a per-OS host interrupt." hexmask.long 0x4 0.--31. 1. "Reserved_1,Reserved_1" group.long 0x20B00++0x7 line.long 0x0 "RGX_CR_MTS_SCHEDULE2_0,This register allows firmware tasks to be scheduled on the META (Garten) core." hexmask.long.tbyte 0x0 9.--31. 1. "Reserved_9,Reserved_9" newline bitfld.long 0x0 8. "HOST,Host Interrupte kick" "0,1" newline bitfld.long 0x0 6.--7. "PRIORITY,DataMaster Priority" "0,1,2,3" newline bitfld.long 0x0 5. "CONTEXT,CONTEXT" "0,1" newline bitfld.long 0x0 4. "TASK,TASK" "0,1" newline hexmask.long.byte 0x0 0.--3. 1. "DM,DataMaster Type" line.long 0x4 "RGX_CR_MTS_SCHEDULE2_1,This register allows firmware tasks to be scheduled on the META (Garten) core." hexmask.long 0x4 0.--31. 1. "Reserved_9,Reserved_9" rgroup.long 0x20B98++0x17 line.long 0x0 "RGX_CR_MTS_INTCTX2_0,This register contains the sideband data for the MTS internal interrupt context registers" bitfld.long 0x0 30.--31. "Reserved_30,Reserved_30" "0,1,2,3" newline hexmask.long.byte 0x0 22.--29. 1. "DM_HOST_SCHEDULE,A 1 bit counter per DM for host requests" newline hexmask.long.byte 0x0 16.--21. 1. "Reserved_16,Reserved_16" newline hexmask.long.byte 0x0 8.--15. 1. "DM_TIMER_SCHEDULE,A 1 bit counter per DM for timer requests" newline hexmask.long.byte 0x0 0.--7. 1. "DM_INTERRUPT_SCHEDULE,A 1 bit counter per DM for interrupt requests" line.long 0x4 "RGX_CR_MTS_INTCTX2_1,This register contains the sideband data for the MTS internal interrupt context registers" hexmask.long 0x4 0.--31. 1. "Reserved_30,Reserved_30" line.long 0x8 "RGX_CR_MTS_BGCTX2_0,This register contains the sideband data for the MTS internal background context registers" hexmask.long.tbyte 0x8 8.--31. 1. "Reserved_8,Reserved_8" newline hexmask.long.byte 0x8 0.--7. 1. "DM_NONCOUNTED_SCHEDULE,A 1 bit counter per DM for non-counted background request" line.long 0xC "RGX_CR_MTS_BGCTX2_1,This register contains the sideband data for the MTS internal background context registers" hexmask.long 0xC 0.--31. 1. "Reserved_8,Reserved_8" line.long 0x10 "RGX_CR_MTS_BGCTX_COUNTED_SCHEDULE2_0,This register contains the sideband data for the MTS internal counted background context counters" hexmask.long.byte 0x10 24.--31. 1. "DM3,A 8 bit counter for DM3" newline hexmask.long.byte 0x10 16.--23. 1. "DM2,A 8 bit counter for DM2" newline hexmask.long.byte 0x10 8.--15. 1. "DM1,A 8 bit counter for DM1" newline hexmask.long.byte 0x10 0.--7. 1. "DM0,A 8 bit counter for DM0" line.long 0x14 "RGX_CR_MTS_BGCTX_COUNTED_SCHEDULE2_1,This register contains the sideband data for the MTS internal counted background context counters" hexmask.long.word 0x14 16.--31. 1. "Reserved_48,Reserved_48" newline hexmask.long.byte 0x14 8.--15. 1. "DM5,A 8 bit counter for DM5" newline hexmask.long.byte 0x14 0.--7. 1. "DM4,A 8 bit counter for DM4" rgroup.long 0x20BD8++0x7 line.long 0x0 "RGX_CR_IRQ_OS2_EVENT_STATUS_0,This register indicates the source of a per-OS host interrupt. This register is set by the firmware and cleared by the host." hexmask.long 0x0 1.--31. 1. "Reserved_1,Reserved_1" newline bitfld.long 0x0 0. "SOURCE,SOURCE" "0,1" line.long 0x4 "RGX_CR_IRQ_OS2_EVENT_STATUS_1,This register indicates the source of a per-OS host interrupt. This register is set by the firmware and cleared by the host." hexmask.long 0x4 0.--31. 1. "Reserved_1,Reserved_1" group.long 0x20BE8++0x7 line.long 0x0 "RGX_CR_IRQ_OS2_EVENT_CLEAR_0,This register clears a per-OS host interrupt." hexmask.long 0x0 1.--31. 1. "Reserved_1,Reserved_1" newline bitfld.long 0x0 0. "SOURCE,SOURCE" "0,1" line.long 0x4 "RGX_CR_IRQ_OS2_EVENT_CLEAR_1,This register clears a per-OS host interrupt." hexmask.long 0x4 0.--31. 1. "Reserved_1,Reserved_1" group.long 0x30B00++0x7 line.long 0x0 "RGX_CR_MTS_SCHEDULE3_0,This register allows firmware tasks to be scheduled on the META (Garten) core." hexmask.long.tbyte 0x0 9.--31. 1. "Reserved_9,Reserved_9" newline bitfld.long 0x0 8. "HOST,Host Interrupte kick" "0,1" newline bitfld.long 0x0 6.--7. "PRIORITY,DataMaster Priority" "0,1,2,3" newline bitfld.long 0x0 5. "CONTEXT,CONTEXT" "0,1" newline bitfld.long 0x0 4. "TASK,TASK" "0,1" newline hexmask.long.byte 0x0 0.--3. 1. "DM,DataMaster Type" line.long 0x4 "RGX_CR_MTS_SCHEDULE3_1,This register allows firmware tasks to be scheduled on the META (Garten) core." hexmask.long 0x4 0.--31. 1. "Reserved_9,Reserved_9" rgroup.long 0x30B98++0x17 line.long 0x0 "RGX_CR_MTS_INTCTX3_0,This register contains the sideband data for the MTS internal interrupt context registers" bitfld.long 0x0 30.--31. "Reserved_30,Reserved_30" "0,1,2,3" newline hexmask.long.byte 0x0 22.--29. 1. "DM_HOST_SCHEDULE,A 1 bit counter per DM for host requests" newline hexmask.long.byte 0x0 16.--21. 1. "Reserved_16,Reserved_16" newline hexmask.long.byte 0x0 8.--15. 1. "DM_TIMER_SCHEDULE,A 1 bit counter per DM for timer requests" newline hexmask.long.byte 0x0 0.--7. 1. "DM_INTERRUPT_SCHEDULE,A 1 bit counter per DM for interrupt requests" line.long 0x4 "RGX_CR_MTS_INTCTX3_1,This register contains the sideband data for the MTS internal interrupt context registers" hexmask.long 0x4 0.--31. 1. "Reserved_30,Reserved_30" line.long 0x8 "RGX_CR_MTS_BGCTX3_0,This register contains the sideband data for the MTS internal background context registers" hexmask.long.tbyte 0x8 8.--31. 1. "Reserved_8,Reserved_8" newline hexmask.long.byte 0x8 0.--7. 1. "DM_NONCOUNTED_SCHEDULE,A 1 bit counter per DM for non-counted background request" line.long 0xC "RGX_CR_MTS_BGCTX3_1,This register contains the sideband data for the MTS internal background context registers" hexmask.long 0xC 0.--31. 1. "Reserved_8,Reserved_8" line.long 0x10 "RGX_CR_MTS_BGCTX_COUNTED_SCHEDULE3_0,This register contains the sideband data for the MTS internal counted background context counters" hexmask.long.byte 0x10 24.--31. 1. "DM3,A 8 bit counter for DM3" newline hexmask.long.byte 0x10 16.--23. 1. "DM2,A 8 bit counter for DM2" newline hexmask.long.byte 0x10 8.--15. 1. "DM1,A 8 bit counter for DM1" newline hexmask.long.byte 0x10 0.--7. 1. "DM0,A 8 bit counter for DM0" line.long 0x14 "RGX_CR_MTS_BGCTX_COUNTED_SCHEDULE3_1,This register contains the sideband data for the MTS internal counted background context counters" hexmask.long.word 0x14 16.--31. 1. "Reserved_48,Reserved_48" newline hexmask.long.byte 0x14 8.--15. 1. "DM5,A 8 bit counter for DM5" newline hexmask.long.byte 0x14 0.--7. 1. "DM4,A 8 bit counter for DM4" rgroup.long 0x30BD8++0x7 line.long 0x0 "RGX_CR_IRQ_OS3_EVENT_STATUS_0,This register indicates the source of a per-OS host interrupt. This register is set by the firmware and cleared by the host." hexmask.long 0x0 1.--31. 1. "Reserved_1,Reserved_1" newline bitfld.long 0x0 0. "SOURCE,SOURCE" "0,1" line.long 0x4 "RGX_CR_IRQ_OS3_EVENT_STATUS_1,This register indicates the source of a per-OS host interrupt. This register is set by the firmware and cleared by the host." hexmask.long 0x4 0.--31. 1. "Reserved_1,Reserved_1" group.long 0x30BE8++0x7 line.long 0x0 "RGX_CR_IRQ_OS3_EVENT_CLEAR_0,This register clears a per-OS host interrupt." hexmask.long 0x0 1.--31. 1. "Reserved_1,Reserved_1" newline bitfld.long 0x0 0. "SOURCE,SOURCE" "0,1" line.long 0x4 "RGX_CR_IRQ_OS3_EVENT_CLEAR_1,This register clears a per-OS host interrupt." hexmask.long 0x4 0.--31. 1. "Reserved_1,Reserved_1" group.long 0x40B00++0x7 line.long 0x0 "RGX_CR_MTS_SCHEDULE4_0,This register allows firmware tasks to be scheduled on the META (Garten) core." hexmask.long.tbyte 0x0 9.--31. 1. "Reserved_9,Reserved_9" newline bitfld.long 0x0 8. "HOST,Host Interrupte kick" "0,1" newline bitfld.long 0x0 6.--7. "PRIORITY,DataMaster Priority" "0,1,2,3" newline bitfld.long 0x0 5. "CONTEXT,CONTEXT" "0,1" newline bitfld.long 0x0 4. "TASK,TASK" "0,1" newline hexmask.long.byte 0x0 0.--3. 1. "DM,DataMaster Type" line.long 0x4 "RGX_CR_MTS_SCHEDULE4_1,This register allows firmware tasks to be scheduled on the META (Garten) core." hexmask.long 0x4 0.--31. 1. "Reserved_9,Reserved_9" rgroup.long 0x40B98++0x17 line.long 0x0 "RGX_CR_MTS_INTCTX4_0,This register contains the sideband data for the MTS internal interrupt context registers" bitfld.long 0x0 30.--31. "Reserved_30,Reserved_30" "0,1,2,3" newline hexmask.long.byte 0x0 22.--29. 1. "DM_HOST_SCHEDULE,A 1 bit counter per DM for host requests" newline hexmask.long.byte 0x0 16.--21. 1. "Reserved_16,Reserved_16" newline hexmask.long.byte 0x0 8.--15. 1. "DM_TIMER_SCHEDULE,A 1 bit counter per DM for timer requests" newline hexmask.long.byte 0x0 0.--7. 1. "DM_INTERRUPT_SCHEDULE,A 1 bit counter per DM for interrupt requests" line.long 0x4 "RGX_CR_MTS_INTCTX4_1,This register contains the sideband data for the MTS internal interrupt context registers" hexmask.long 0x4 0.--31. 1. "Reserved_30,Reserved_30" line.long 0x8 "RGX_CR_MTS_BGCTX4_0,This register contains the sideband data for the MTS internal background context registers" hexmask.long.tbyte 0x8 8.--31. 1. "Reserved_8,Reserved_8" newline hexmask.long.byte 0x8 0.--7. 1. "DM_NONCOUNTED_SCHEDULE,A 1 bit counter per DM for non-counted background request" line.long 0xC "RGX_CR_MTS_BGCTX4_1,This register contains the sideband data for the MTS internal background context registers" hexmask.long 0xC 0.--31. 1. "Reserved_8,Reserved_8" line.long 0x10 "RGX_CR_MTS_BGCTX_COUNTED_SCHEDULE4_0,This register contains the sideband data for the MTS internal counted background context counters" hexmask.long.byte 0x10 24.--31. 1. "DM3,A 8 bit counter for DM3" newline hexmask.long.byte 0x10 16.--23. 1. "DM2,A 8 bit counter for DM2" newline hexmask.long.byte 0x10 8.--15. 1. "DM1,A 8 bit counter for DM1" newline hexmask.long.byte 0x10 0.--7. 1. "DM0,A 8 bit counter for DM0" line.long 0x14 "RGX_CR_MTS_BGCTX_COUNTED_SCHEDULE4_1,This register contains the sideband data for the MTS internal counted background context counters" hexmask.long.word 0x14 16.--31. 1. "Reserved_48,Reserved_48" newline hexmask.long.byte 0x14 8.--15. 1. "DM5,A 8 bit counter for DM5" newline hexmask.long.byte 0x14 0.--7. 1. "DM4,A 8 bit counter for DM4" rgroup.long 0x40BD8++0x7 line.long 0x0 "RGX_CR_IRQ_OS4_EVENT_STATUS_0,This register indicates the source of a per-OS host interrupt. This register is set by the firmware and cleared by the host." hexmask.long 0x0 1.--31. 1. "Reserved_1,Reserved_1" newline bitfld.long 0x0 0. "SOURCE,SOURCE" "0,1" line.long 0x4 "RGX_CR_IRQ_OS4_EVENT_STATUS_1,This register indicates the source of a per-OS host interrupt. This register is set by the firmware and cleared by the host." hexmask.long 0x4 0.--31. 1. "Reserved_1,Reserved_1" group.long 0x40BE8++0x7 line.long 0x0 "RGX_CR_IRQ_OS4_EVENT_CLEAR_0,This register clears a per-OS host interrupt." hexmask.long 0x0 1.--31. 1. "Reserved_1,Reserved_1" newline bitfld.long 0x0 0. "SOURCE,SOURCE" "0,1" line.long 0x4 "RGX_CR_IRQ_OS4_EVENT_CLEAR_1,This register clears a per-OS host interrupt." hexmask.long 0x4 0.--31. 1. "Reserved_1,Reserved_1" group.long 0x50B00++0x7 line.long 0x0 "RGX_CR_MTS_SCHEDULE5_0,This register allows firmware tasks to be scheduled on the META (Garten) core." hexmask.long.tbyte 0x0 9.--31. 1. "Reserved_9,Reserved_9" newline bitfld.long 0x0 8. "HOST,Host Interrupte kick" "0,1" newline bitfld.long 0x0 6.--7. "PRIORITY,DataMaster Priority" "0,1,2,3" newline bitfld.long 0x0 5. "CONTEXT,CONTEXT" "0,1" newline bitfld.long 0x0 4. "TASK,TASK" "0,1" newline hexmask.long.byte 0x0 0.--3. 1. "DM,DataMaster Type" line.long 0x4 "RGX_CR_MTS_SCHEDULE5_1,This register allows firmware tasks to be scheduled on the META (Garten) core." hexmask.long 0x4 0.--31. 1. "Reserved_9,Reserved_9" rgroup.long 0x50B98++0x17 line.long 0x0 "RGX_CR_MTS_INTCTX5_0,This register contains the sideband data for the MTS internal interrupt context registers" bitfld.long 0x0 30.--31. "Reserved_30,Reserved_30" "0,1,2,3" newline hexmask.long.byte 0x0 22.--29. 1. "DM_HOST_SCHEDULE,A 1 bit counter per DM for host requests" newline hexmask.long.byte 0x0 16.--21. 1. "Reserved_16,Reserved_16" newline hexmask.long.byte 0x0 8.--15. 1. "DM_TIMER_SCHEDULE,A 1 bit counter per DM for timer requests" newline hexmask.long.byte 0x0 0.--7. 1. "DM_INTERRUPT_SCHEDULE,A 1 bit counter per DM for interrupt requests" line.long 0x4 "RGX_CR_MTS_INTCTX5_1,This register contains the sideband data for the MTS internal interrupt context registers" hexmask.long 0x4 0.--31. 1. "Reserved_30,Reserved_30" line.long 0x8 "RGX_CR_MTS_BGCTX5_0,This register contains the sideband data for the MTS internal background context registers" hexmask.long.tbyte 0x8 8.--31. 1. "Reserved_8,Reserved_8" newline hexmask.long.byte 0x8 0.--7. 1. "DM_NONCOUNTED_SCHEDULE,A 1 bit counter per DM for non-counted background request" line.long 0xC "RGX_CR_MTS_BGCTX5_1,This register contains the sideband data for the MTS internal background context registers" hexmask.long 0xC 0.--31. 1. "Reserved_8,Reserved_8" line.long 0x10 "RGX_CR_MTS_BGCTX_COUNTED_SCHEDULE5_0,This register contains the sideband data for the MTS internal counted background context counters" hexmask.long.byte 0x10 24.--31. 1. "DM3,A 8 bit counter for DM3" newline hexmask.long.byte 0x10 16.--23. 1. "DM2,A 8 bit counter for DM2" newline hexmask.long.byte 0x10 8.--15. 1. "DM1,A 8 bit counter for DM1" newline hexmask.long.byte 0x10 0.--7. 1. "DM0,A 8 bit counter for DM0" line.long 0x14 "RGX_CR_MTS_BGCTX_COUNTED_SCHEDULE5_1,This register contains the sideband data for the MTS internal counted background context counters" hexmask.long.word 0x14 16.--31. 1. "Reserved_48,Reserved_48" newline hexmask.long.byte 0x14 8.--15. 1. "DM5,A 8 bit counter for DM5" newline hexmask.long.byte 0x14 0.--7. 1. "DM4,A 8 bit counter for DM4" rgroup.long 0x50BD8++0x7 line.long 0x0 "RGX_CR_IRQ_OS5_EVENT_STATUS_0,This register indicates the source of a per-OS host interrupt. This register is set by the firmware and cleared by the host." hexmask.long 0x0 1.--31. 1. "Reserved_1,Reserved_1" newline bitfld.long 0x0 0. "SOURCE,SOURCE" "0,1" line.long 0x4 "RGX_CR_IRQ_OS5_EVENT_STATUS_1,This register indicates the source of a per-OS host interrupt. This register is set by the firmware and cleared by the host." hexmask.long 0x4 0.--31. 1. "Reserved_1,Reserved_1" group.long 0x50BE8++0x7 line.long 0x0 "RGX_CR_IRQ_OS5_EVENT_CLEAR_0,This register clears a per-OS host interrupt." hexmask.long 0x0 1.--31. 1. "Reserved_1,Reserved_1" newline bitfld.long 0x0 0. "SOURCE,SOURCE" "0,1" line.long 0x4 "RGX_CR_IRQ_OS5_EVENT_CLEAR_1,This register clears a per-OS host interrupt." hexmask.long 0x4 0.--31. 1. "Reserved_1,Reserved_1" group.long 0x60B00++0x7 line.long 0x0 "RGX_CR_MTS_SCHEDULE6_0,This register allows firmware tasks to be scheduled on the META (Garten) core." hexmask.long.tbyte 0x0 9.--31. 1. "Reserved_9,Reserved_9" newline bitfld.long 0x0 8. "HOST,Host Interrupte kick" "0,1" newline bitfld.long 0x0 6.--7. "PRIORITY,DataMaster Priority" "0,1,2,3" newline bitfld.long 0x0 5. "CONTEXT,CONTEXT" "0,1" newline bitfld.long 0x0 4. "TASK,TASK" "0,1" newline hexmask.long.byte 0x0 0.--3. 1. "DM,DataMaster Type" line.long 0x4 "RGX_CR_MTS_SCHEDULE6_1,This register allows firmware tasks to be scheduled on the META (Garten) core." hexmask.long 0x4 0.--31. 1. "Reserved_9,Reserved_9" rgroup.long 0x60B98++0x17 line.long 0x0 "RGX_CR_MTS_INTCTX6_0,This register contains the sideband data for the MTS internal interrupt context registers" bitfld.long 0x0 30.--31. "Reserved_30,Reserved_30" "0,1,2,3" newline hexmask.long.byte 0x0 22.--29. 1. "DM_HOST_SCHEDULE,A 1 bit counter per DM for host requests" newline hexmask.long.byte 0x0 16.--21. 1. "Reserved_16,Reserved_16" newline hexmask.long.byte 0x0 8.--15. 1. "DM_TIMER_SCHEDULE,A 1 bit counter per DM for timer requests" newline hexmask.long.byte 0x0 0.--7. 1. "DM_INTERRUPT_SCHEDULE,A 1 bit counter per DM for interrupt requests" line.long 0x4 "RGX_CR_MTS_INTCTX6_1,This register contains the sideband data for the MTS internal interrupt context registers" hexmask.long 0x4 0.--31. 1. "Reserved_30,Reserved_30" line.long 0x8 "RGX_CR_MTS_BGCTX6_0,This register contains the sideband data for the MTS internal background context registers" hexmask.long.tbyte 0x8 8.--31. 1. "Reserved_8,Reserved_8" newline hexmask.long.byte 0x8 0.--7. 1. "DM_NONCOUNTED_SCHEDULE,A 1 bit counter per DM for non-counted background request" line.long 0xC "RGX_CR_MTS_BGCTX6_1,This register contains the sideband data for the MTS internal background context registers" hexmask.long 0xC 0.--31. 1. "Reserved_8,Reserved_8" line.long 0x10 "RGX_CR_MTS_BGCTX_COUNTED_SCHEDULE6_0,This register contains the sideband data for the MTS internal counted background context counters" hexmask.long.byte 0x10 24.--31. 1. "DM3,A 8 bit counter for DM3" newline hexmask.long.byte 0x10 16.--23. 1. "DM2,A 8 bit counter for DM2" newline hexmask.long.byte 0x10 8.--15. 1. "DM1,A 8 bit counter for DM1" newline hexmask.long.byte 0x10 0.--7. 1. "DM0,A 8 bit counter for DM0" line.long 0x14 "RGX_CR_MTS_BGCTX_COUNTED_SCHEDULE6_1,This register contains the sideband data for the MTS internal counted background context counters" hexmask.long.word 0x14 16.--31. 1. "Reserved_48,Reserved_48" newline hexmask.long.byte 0x14 8.--15. 1. "DM5,A 8 bit counter for DM5" newline hexmask.long.byte 0x14 0.--7. 1. "DM4,A 8 bit counter for DM4" rgroup.long 0x60BD8++0x7 line.long 0x0 "RGX_CR_IRQ_OS6_EVENT_STATUS_0,This register indicates the source of a per-OS host interrupt. This register is set by the firmware and cleared by the host." hexmask.long 0x0 1.--31. 1. "Reserved_1,Reserved_1" newline bitfld.long 0x0 0. "SOURCE,SOURCE" "0,1" line.long 0x4 "RGX_CR_IRQ_OS6_EVENT_STATUS_1,This register indicates the source of a per-OS host interrupt. This register is set by the firmware and cleared by the host." hexmask.long 0x4 0.--31. 1. "Reserved_1,Reserved_1" group.long 0x60BE8++0x7 line.long 0x0 "RGX_CR_IRQ_OS6_EVENT_CLEAR_0,This register clears a per-OS host interrupt." hexmask.long 0x0 1.--31. 1. "Reserved_1,Reserved_1" newline bitfld.long 0x0 0. "SOURCE,SOURCE" "0,1" line.long 0x4 "RGX_CR_IRQ_OS6_EVENT_CLEAR_1,This register clears a per-OS host interrupt." hexmask.long 0x4 0.--31. 1. "Reserved_1,Reserved_1" group.long 0x70B00++0x7 line.long 0x0 "RGX_CR_MTS_SCHEDULE7_0,This register allows firmware tasks to be scheduled on the META (Garten) core." hexmask.long.tbyte 0x0 9.--31. 1. "Reserved_9,Reserved_9" newline bitfld.long 0x0 8. "HOST,Host Interrupte kick" "0,1" newline bitfld.long 0x0 6.--7. "PRIORITY,DataMaster Priority" "0,1,2,3" newline bitfld.long 0x0 5. "CONTEXT,CONTEXT" "0,1" newline bitfld.long 0x0 4. "TASK,TASK" "0,1" newline hexmask.long.byte 0x0 0.--3. 1. "DM,DataMaster Type" line.long 0x4 "RGX_CR_MTS_SCHEDULE7_1,This register allows firmware tasks to be scheduled on the META (Garten) core." hexmask.long 0x4 0.--31. 1. "Reserved_9,Reserved_9" rgroup.long 0x70B98++0x17 line.long 0x0 "RGX_CR_MTS_INTCTX7_0,This register contains the sideband data for the MTS internal interrupt context registers" bitfld.long 0x0 30.--31. "Reserved_30,Reserved_30" "0,1,2,3" newline hexmask.long.byte 0x0 22.--29. 1. "DM_HOST_SCHEDULE,A 1 bit counter per DM for host requests" newline hexmask.long.byte 0x0 16.--21. 1. "Reserved_16,Reserved_16" newline hexmask.long.byte 0x0 8.--15. 1. "DM_TIMER_SCHEDULE,A 1 bit counter per DM for timer requests" newline hexmask.long.byte 0x0 0.--7. 1. "DM_INTERRUPT_SCHEDULE,A 1 bit counter per DM for interrupt requests" line.long 0x4 "RGX_CR_MTS_INTCTX7_1,This register contains the sideband data for the MTS internal interrupt context registers" hexmask.long 0x4 0.--31. 1. "Reserved_30,Reserved_30" line.long 0x8 "RGX_CR_MTS_BGCTX7_0,This register contains the sideband data for the MTS internal background context registers" hexmask.long.tbyte 0x8 8.--31. 1. "Reserved_8,Reserved_8" newline hexmask.long.byte 0x8 0.--7. 1. "DM_NONCOUNTED_SCHEDULE,A 1 bit counter per DM for non-counted background request" line.long 0xC "RGX_CR_MTS_BGCTX7_1,This register contains the sideband data for the MTS internal background context registers" hexmask.long 0xC 0.--31. 1. "Reserved_8,Reserved_8" line.long 0x10 "RGX_CR_MTS_BGCTX_COUNTED_SCHEDULE7_0,This register contains the sideband data for the MTS internal counted background context counters" hexmask.long.byte 0x10 24.--31. 1. "DM3,A 8 bit counter for DM3" newline hexmask.long.byte 0x10 16.--23. 1. "DM2,A 8 bit counter for DM2" newline hexmask.long.byte 0x10 8.--15. 1. "DM1,A 8 bit counter for DM1" newline hexmask.long.byte 0x10 0.--7. 1. "DM0,A 8 bit counter for DM0" line.long 0x14 "RGX_CR_MTS_BGCTX_COUNTED_SCHEDULE7_1,This register contains the sideband data for the MTS internal counted background context counters" hexmask.long.word 0x14 16.--31. 1. "Reserved_48,Reserved_48" newline hexmask.long.byte 0x14 8.--15. 1. "DM5,A 8 bit counter for DM5" newline hexmask.long.byte 0x14 0.--7. 1. "DM4,A 8 bit counter for DM4" rgroup.long 0x70BD8++0x7 line.long 0x0 "RGX_CR_IRQ_OS7_EVENT_STATUS_0,This register indicates the source of a per-OS host interrupt. This register is set by the firmware and cleared by the host." hexmask.long 0x0 1.--31. 1. "Reserved_1,Reserved_1" newline bitfld.long 0x0 0. "SOURCE,SOURCE" "0,1" line.long 0x4 "RGX_CR_IRQ_OS7_EVENT_STATUS_1,This register indicates the source of a per-OS host interrupt. This register is set by the firmware and cleared by the host." hexmask.long 0x4 0.--31. 1. "Reserved_1,Reserved_1" group.long 0x70BE8++0x7 line.long 0x0 "RGX_CR_IRQ_OS7_EVENT_CLEAR_0,This register clears a per-OS host interrupt." hexmask.long 0x0 1.--31. 1. "Reserved_1,Reserved_1" newline bitfld.long 0x0 0. "SOURCE,SOURCE" "0,1" line.long 0x4 "RGX_CR_IRQ_OS7_EVENT_CLEAR_1,This register clears a per-OS host interrupt." hexmask.long 0x4 0.--31. 1. "Reserved_1,Reserved_1" tree.end tree "GPU2" base ad:0xF4E00000 group.long 0x0++0x7 line.long 0x0 "RGX_CR_CLK_CTRL_0,Core Module Clock Control Modes. Allows individual domain clocks to be forced off. forced on or operate under automatic pipeline activity based clock gating. This register is generally controlled by the GPU firmware and should be set to.." bitfld.long 0x0 30.--31. "Reserved_30,Reserved_30" "0,1,2,3" newline bitfld.long 0x0 28.--29. "TPU_MCU_DEMUX,TPU_MCU_DEMUX" "0,1,2,3" newline bitfld.long 0x0 26.--27. "MCU_L0,MCU_L0" "0,1,2,3" newline bitfld.long 0x0 24.--25. "TPU,TPU" "0,1,2,3" newline bitfld.long 0x0 22.--23. "Reserved_22,Reserved_22" "0,1,2,3" newline bitfld.long 0x0 20.--21. "USC,USC" "0,1,2,3" newline bitfld.long 0x0 18.--19. "Reserved_18,Reserved_18" "0,1,2,3" newline bitfld.long 0x0 16.--17. "SLC,SLC" "0,1,2,3" newline bitfld.long 0x0 14.--15. "UVS,UVS" "0,1,2,3" newline bitfld.long 0x0 12.--13. "PDS,PDS" "0,1,2,3" newline bitfld.long 0x0 10.--11. "VDM,VDM" "0,1,2,3" newline bitfld.long 0x0 8.--9. "PM,PM" "0,1,2,3" newline bitfld.long 0x0 6.--7. "GPP,GPP" "0,1,2,3" newline bitfld.long 0x0 4.--5. "TE,TE" "0,1,2,3" newline bitfld.long 0x0 2.--3. "TSP,TSP" "0,1,2,3" newline bitfld.long 0x0 0.--1. "ISP,ISP" "0,1,2,3" line.long 0x4 "RGX_CR_CLK_CTRL_1,Core Module Clock Control Modes. Allows individual domain clocks to be forced off. forced on or operate under automatic pipeline activity based clock gating. This register is generally controlled by the GPU firmware and should be set to.." hexmask.long.byte 0x4 28.--31. 1. "Reserved_60,Reserved_60" newline bitfld.long 0x4 26.--27. "FBC,FBC" "0,1,2,3" newline bitfld.long 0x4 24.--25. "FBDC,FBDC" "0,1,2,3" newline bitfld.long 0x4 22.--23. "FB_TLCACHE,FB_TLCACHE" "0,1,2,3" newline bitfld.long 0x4 20.--21. "USCS,USCS" "0,1,2,3" newline bitfld.long 0x4 18.--19. "PBE,PBE" "0,1,2,3" newline bitfld.long 0x4 16.--17. "MCU_L1,MCU_L1" "0,1,2,3" newline bitfld.long 0x4 14.--15. "CDM,CDM" "0,1,2,3" newline bitfld.long 0x4 12.--13. "SIDEKICK,SIDEKICK" "0,1,2,3" newline bitfld.long 0x4 10.--11. "BIF_SIDEKICK,BIF_SIDEKICK" "0,1,2,3" newline bitfld.long 0x4 8.--9. "BIF,BIF" "0,1,2,3" newline hexmask.long.byte 0x4 0.--7. 1. "Reserved_30,Reserved_30" rgroup.long 0x8++0x7 line.long 0x0 "RGX_CR_CLK_STATUS_0,Reports the current module clock status Clock gating state reflects the condition of the clock for each module" bitfld.long 0x0 30.--31. "Reserved_30,Reserved_30" "0,1,2,3" newline bitfld.long 0x0 29. "FBC,FBC" "0,1" newline bitfld.long 0x0 28. "FBDC,FBDC" "0,1" newline bitfld.long 0x0 27. "FB_TLCACHE,FB_TLCACHE" "0,1" newline bitfld.long 0x0 26. "USCS,USCS" "0,1" newline bitfld.long 0x0 25. "PBE,PBE" "0,1" newline bitfld.long 0x0 24. "MCU_L1,MCU_L1" "0,1" newline bitfld.long 0x0 23. "CDM,CDM" "0,1" newline bitfld.long 0x0 22. "SIDEKICK,SIDEKICK" "0,1" newline bitfld.long 0x0 21. "BIF_SIDEKICK,BIF_SIDEKICK" "0,1" newline bitfld.long 0x0 20. "BIF,BIF" "0,1" newline hexmask.long.byte 0x0 15.--19. 1. "Reserved_15,Reserved_15" newline bitfld.long 0x0 14. "TPU_MCU_DEMUX,TPU_MCU_DEMUX" "0,1" newline bitfld.long 0x0 13. "MCU_L0,MCU_L0" "0,1" newline bitfld.long 0x0 12. "TPU,TPU" "0,1" newline bitfld.long 0x0 11. "Reserved_11,Reserved_11" "0,1" newline bitfld.long 0x0 10. "USC,USC" "0,1" newline bitfld.long 0x0 9. "Reserved_9,Reserved_9" "0,1" newline bitfld.long 0x0 8. "SLC,SLC" "0,1" newline bitfld.long 0x0 7. "UVS,UVS" "0,1" newline bitfld.long 0x0 6. "PDS,PDS" "0,1" newline bitfld.long 0x0 5. "VDM,VDM" "0,1" newline bitfld.long 0x0 4. "PM,PM" "0,1" newline bitfld.long 0x0 3. "GPP,GPP" "0,1" newline bitfld.long 0x0 2. "TE,TE" "0,1" newline bitfld.long 0x0 1. "TSP,TSP" "0,1" newline bitfld.long 0x0 0. "ISP,ISP" "0,1" line.long 0x4 "RGX_CR_CLK_STATUS_1,Reports the current module clock status Clock gating state reflects the condition of the clock for each module" hexmask.long 0x4 1.--31. 1. "Reserved_33,Reserved_33" newline bitfld.long 0x4 0. "MCU_FBTC,MCU_FBTC" "0,1" rgroup.long 0x18++0x7 line.long 0x0 "RGX_CR_PRODUCT_ID_0,Reports the product ID Product ID Register" hexmask.long.word 0x0 16.--31. 1. "IMG_PRODUCT_ID,IMG Product ID" newline hexmask.long.word 0x0 0.--15. 1. "Reserved_0,Reserved_0" line.long 0x4 "RGX_CR_PRODUCT_ID_1,Reports the product ID Product ID Register" hexmask.long 0x4 0.--31. 1. "Reserved_32,Reserved_32" repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) rgroup.long ($2+0x20)++0x3 line.long 0x0 "RGX_CR_CORE_ID_$1,Reports the product ID Core ID Register" hexmask.long.word 0x0 16.--31. 1. "NUMBER_OF_SCALABLE_UNITS,N - Number of scalable Units" newline hexmask.long.word 0x0 0.--15. 1. "CONFIG_ID,C - Config ID" repeat.end repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) rgroup.long ($2+0x28)++0x3 line.long 0x0 "RGX_CR_CORE_IP_INTEGRATOR_ID_$1,Reports the product ID Core IP Integrator ID Register" hexmask.long 0x0 0.--31. 1. "VALUE,IP company ID/Designer" repeat.end repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) rgroup.long ($2+0x30)++0x3 line.long 0x0 "RGX_CR_CORE_IP_CHANGELIST_$1,Reports the version control ID Core IP Changelist Register" hexmask.long 0x0 0.--31. 1. "VALUE,Version control ID" repeat.end group.long 0x38++0x7 line.long 0x0 "RGX_CR_POWER_EVENT_0,Allows the firmware to request a power-up or power-down operation to an external (to Rogue) power-management controller When the power event operation is accepted. the firmware will either receive an.." hexmask.long.byte 0x0 24.--31. 1. "Reserved_24,Reserved_24" newline hexmask.long.word 0x0 8.--23. 1. "DOMAIN,sets which power island is enabled for the current power event request; bit0:jones bit1-8:dusts bit9-12:blackpearls" newline hexmask.long.byte 0x0 2.--7. 1. "Reserved_2,Reserved_2" newline bitfld.long 0x0 1. "REQ,Set when a power event operation is requested" "0,1" newline bitfld.long 0x0 0. "TYPE,The requested power event operation" "0,1" line.long 0x4 "RGX_CR_POWER_EVENT_1,Allows the firmware to request a power-up or power-down operation to an external (to Rogue) power-management controller When the power event operation is accepted. the firmware will either receive an.." hexmask.long 0x4 0.--31. 1. "Reserved_24,Reserved_24" group.long 0x50++0x7 line.long 0x0 "RGX_CR_DUSTS_ENABLE_0,Controls how many Dual Unified Shading and Texturing Units (DUSTs) are enabled. Each DUST Contain 2 USCs and a TPU module. (Available on 2. X.X.X cores and above). Only applicable in cores with a B.V.N.C > 2.0.0.0 Controls how many.." hexmask.long.tbyte 0x0 8.--31. 1. "Reserved_8,Reserved_8" newline hexmask.long.byte 0x0 0.--7. 1. "ENABLE,Dusts enabled" line.long 0x4 "RGX_CR_DUSTS_ENABLE_1,Controls how many Dual Unified Shading and Texturing Units (DUSTs) are enabled. Each DUST Contain 2 USCs and a TPU module. (Available on 2. X.X.X cores and above). Only applicable in cores with a B.V.N.C > 2.0.0.0 Controls how many.." hexmask.long 0x4 0.--31. 1. "Reserved_8,Reserved_8" rgroup.long 0x58++0x7 line.long 0x0 "RGX_CR_DUSTS_FUSE_0,Indicates how many of the available DUST modules are enabled on the Silicon. (Available on 2.X.X.X cores and above). Shows the raw value of dusts_enable port." hexmask.long.tbyte 0x0 8.--31. 1. "Reserved_8,Reserved_8" newline hexmask.long.byte 0x0 0.--7. 1. "ENABLE,Dusts enabled" line.long 0x4 "RGX_CR_DUSTS_FUSE_1,Indicates how many of the available DUST modules are enabled on the Silicon. (Available on 2.X.X.X cores and above). Shows the raw value of dusts_enable port." hexmask.long 0x4 0.--31. 1. "Reserved_8,Reserved_8" group.long 0x80++0x7 line.long 0x0 "RGX_CR_CLK_XTPLUS_CTRL_0,Core Module Clock Control Modes. Allows individual domain clocks to be forced off. forced on or operate under automatic pipeline activity based clock gating. This register is generally controlled by the GPU firmware and should be.." hexmask.long 0x0 0.--31. 1. "Reserved_0,Reserved_0" line.long 0x4 "RGX_CR_CLK_XTPLUS_CTRL_1,Core Module Clock Control Modes. Allows individual domain clocks to be forced off. forced on or operate under automatic pipeline activity based clock gating. This register is generally controlled by the GPU firmware and should be.." hexmask.long 0x4 6.--31. 1. "Reserved_38,Reserved_38" newline bitfld.long 0x4 4.--5. "TDM,TDM" "0,1,2,3" newline bitfld.long 0x4 2.--3. "ASTC,ASTC" "0,1,2,3" newline bitfld.long 0x4 0.--1. "Reserved_0,Reserved_0" "0,1,2,3" rgroup.long 0x88++0x7 line.long 0x0 "RGX_CR_CLK_XTPLUS_STATUS_0,Reports the current module clock status Clock gating state reflects the condition of the clock for each module" hexmask.long.tbyte 0x0 11.--31. 1. "Reserved_11,Reserved_11" newline bitfld.long 0x0 10. "TDM,TDM" "0,1" newline bitfld.long 0x0 9. "IPF,IPF" "0,1" newline bitfld.long 0x0 8. "COMPUTE,COMPUTE" "0,1" newline bitfld.long 0x0 7. "ASTC,ASTC" "0,1" newline bitfld.long 0x0 6. "PIXEL,PIXEL" "0,1" newline bitfld.long 0x0 5. "VERTEX,VERTEX" "0,1" newline bitfld.long 0x0 4. "Reserved_4,Reserved_4" "0,1" newline bitfld.long 0x0 3. "PDS_SHARED,PDS_SHARED" "0,1" newline bitfld.long 0x0 2. "BIF_BLACKPEARL,BIF_BLACKPEARL" "0,1" newline bitfld.long 0x0 1. "USC_SHARED,USC_SHARED" "0,1" newline bitfld.long 0x0 0. "GEOMETRY,GEOMETRY" "0,1" line.long 0x4 "RGX_CR_CLK_XTPLUS_STATUS_1,Reports the current module clock status Clock gating state reflects the condition of the clock for each module" hexmask.long 0x4 0.--31. 1. "Reserved_11,Reserved_11" repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) rgroup.long ($2+0xE0)++0x3 line.long 0x0 "RGX_CR_SOC_TIMER_GRAY_$1,This register contains the value of a 64-bit external gray coded timer. (Available on 2.X.X.X cores and above)." hexmask.long 0x0 0.--31. 1. "VALUE,VALUE" repeat.end repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) rgroup.long ($2+0xE8)++0x3 line.long 0x0 "RGX_CR_SOC_TIMER_BINARY_$1,This register contains the value of a 64-bit external binary coded timer." hexmask.long 0x0 0.--31. 1. "VALUE,VALUE" repeat.end group.long 0x100++0xF line.long 0x0 "RGX_CR_SOFT_RESET_0,Core soft reset control register. Write a '1' to reset and a '0' to clear See the soft reset section in the TRM to understand how to use the soft reset register." bitfld.long 0x0 31. "RASCAL_CORE,Note that the RASL_CORE bit affects logic related to the reading and writing of registers. This soft reset should therefore be used with caution. Upon power down events it is necessary to reset every register so this bit should be used but.." "0,1" newline bitfld.long 0x0 30. "DUST_B_CORE,DUST_B_CORE" "0,1" newline bitfld.long 0x0 29. "DUST_A_CORE,DUST_A_CORE" "0,1" newline bitfld.long 0x0 28. "FB_TLCACHE,FB_TLCACHE" "0,1" newline bitfld.long 0x0 27. "SLC,SLC" "0,1" newline bitfld.long 0x0 26. "Reserved_26,Reserved_26" "0,1" newline bitfld.long 0x0 25. "UVS,UVS" "0,1" newline bitfld.long 0x0 24. "TE,TE" "0,1" newline bitfld.long 0x0 23. "GPP,GPP" "0,1" newline bitfld.long 0x0 22. "FBDC,FBDC" "0,1" newline bitfld.long 0x0 21. "FBC,FBC" "0,1" newline bitfld.long 0x0 20. "PM,PM" "0,1" newline bitfld.long 0x0 19. "PBE,PBE" "0,1" newline bitfld.long 0x0 18. "USC_SHARED,USC_SHARED" "0,1" newline bitfld.long 0x0 17. "MCU_L1,MCU_L1" "0,1" newline bitfld.long 0x0 16. "BIF,Bifpmcache BIF" "0,1" newline bitfld.long 0x0 15. "CDM,CDM" "0,1" newline bitfld.long 0x0 14. "VDM,VDM" "0,1" newline bitfld.long 0x0 13. "Reserved_13,Reserved_13" "0,1" newline bitfld.long 0x0 12. "PDS,PDS" "0,1" newline bitfld.long 0x0 11. "ISP,ISP" "0,1" newline bitfld.long 0x0 10. "TSP,TSP" "0,1" newline hexmask.long.byte 0x0 5.--9. 1. "Reserved_5,Reserved_5" newline bitfld.long 0x0 4. "TPU_MCU_DEMUX,TPU_MCU_DEMUX" "0,1" newline bitfld.long 0x0 3. "MCU_L0,MCU_L0" "0,1" newline bitfld.long 0x0 2. "TPU,TPU" "0,1" newline bitfld.long 0x0 1. "Reserved_1,Reserved_1" "0,1" newline bitfld.long 0x0 0. "USC,USC" "0,1" line.long 0x4 "RGX_CR_SOFT_RESET_1,Core soft reset control register. Write a '1' to reset and a '0' to clear See the soft reset section in the TRM to understand how to use the soft reset register." bitfld.long 0x4 29.--31. "Reserved_61,Reserved_61" "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 28. "JONES_CORE,JONES_CORE" "0,1" newline bitfld.long 0x4 27. "TILING_CORE,TILING_CORE" "0,1" newline bitfld.long 0x4 26. "TE3,TE3" "0,1" newline bitfld.long 0x4 25. "VCE,VCE" "0,1" newline bitfld.long 0x4 24. "VBS,VBS" "0,1" newline hexmask.long.byte 0x4 20.--23. 1. "Reserved_52,Reserved_52" newline bitfld.long 0x4 19. "FB_CDC,FB_CDC" "0,1" newline bitfld.long 0x4 17.--18. "Reserved_49,Reserved_49" "0,1,2,3" newline bitfld.long 0x4 16. "MCU_FBTC,MCU_FBTC" "0,1" newline hexmask.long.word 0x4 3.--15. 1. "Reserved_35,Reserved_35" newline bitfld.long 0x4 2. "MMU,MMU" "0,1" newline bitfld.long 0x4 1. "Reserved_33,Reserved_33" "0,1" newline bitfld.long 0x4 0. "GARTEN,Includes MTS and META or MIPS" "0,1" line.long 0x8 "RGX_CR_SOFT_RESET2_0,Core soft reset control register. Write a '1' to reset and a '0' to clear See the soft reset section in the TRM to understand how to use the soft reset register." hexmask.long.tbyte 0x8 12.--31. 1. "Reserved_12,Reserved_12" newline bitfld.long 0x8 11. "TDM,TDM" "0,1" newline bitfld.long 0x8 10. "ASTC,ASTC" "0,1" newline bitfld.long 0x8 9. "BLACKPEARL,BLACKPEARL" "0,1" newline bitfld.long 0x8 8. "Reserved_8,Reserved_8" "0,1" newline bitfld.long 0x8 7. "IPF,IPF" "0,1" newline bitfld.long 0x8 6. "GEOMETRY,GEOMETRY" "0,1" newline bitfld.long 0x8 5. "USC_SHARED,USC_SHARED" "0,1" newline bitfld.long 0x8 4. "PDS_SHARED,PDS_SHARED" "0,1" newline bitfld.long 0x8 3. "BIF_BLACKPEARL,BIF_BLACKPEARL" "0,1" newline bitfld.long 0x8 2. "PIXEL,PIXEL" "0,1" newline bitfld.long 0x8 1. "Reserved_1,Reserved_1" "0,1" newline bitfld.long 0x8 0. "VERTEX,VERTEX" "0,1" line.long 0xC "RGX_CR_SOFT_RESET2_1,Core soft reset control register. Write a '1' to reset and a '0' to clear See the soft reset section in the TRM to understand how to use the soft reset register." hexmask.long 0xC 0.--31. 1. "Reserved_12,Reserved_12" group.long 0x120++0x17 line.long 0x0 "RGX_CR_CONTEXT_SWITCH_ENABLE_0,The use of the this register has been deprecated." hexmask.long 0x0 4.--31. 1. "Reserved_4,Reserved_4" newline bitfld.long 0x0 3. "SOFT_RESET,SOFT_RESET" "0,1" newline bitfld.long 0x0 2. "IPF,IPF" "0,1" newline bitfld.long 0x0 1. "VDM,VDM" "0,1" newline bitfld.long 0x0 0. "CDM,CDM" "0,1" line.long 0x4 "RGX_CR_CONTEXT_SWITCH_ENABLE_1,The use of the this register has been deprecated." hexmask.long 0x4 0.--31. 1. "Reserved_4,Reserved_4" line.long 0x8 "RGX_CR_EVENT_ENABLE_0,This register is used to enable GPU interrupts directly to the host Writing a '1' to a bit field enables the relevant event This register should only be programmed when the META firmware is not used If the META firmware is used. the.." bitfld.long 0x8 31. "TDM_FENCE_FINISHED,Indicates a 2D fence has been processed" "0,1" newline bitfld.long 0x8 30. "TDM_BUFFER_STALL,The TDM has exhausted the current 2D circular buffer (read pointer = write_pointer)" "0,1" newline hexmask.long.word 0x8 19.--29. 1. "Reserved_19,Reserved_19" newline bitfld.long 0x8 18. "TDM_CONTEXT_STORE_FINISHED,The TDM has completed the requested context store operation." "0,1" newline bitfld.long 0x8 16.--17. "Reserved_16,Reserved_16" "0,1,2,3" newline bitfld.long 0x8 15. "USC_TRIGGER,One or more USC has executed a nop.trigger instruction" "0,1" newline bitfld.long 0x8 14. "ZLS_FINISHED,ZLS has finished all tiles in a Render" "0,1" newline bitfld.long 0x8 13. "GPIO_ACK,General Purpose ouput acknowledgement" "0,1" newline bitfld.long 0x8 12. "GPIO_REQ,General Purpose input request" "0,1" newline bitfld.long 0x8 11. "POWER_ABORT,The requested power operation has been denied." "0,1" newline bitfld.long 0x8 10. "POWER_COMPLETE,The requested power operation has completed" "0,1" newline bitfld.long 0x8 9. "MMU_PAGE_FAULT,An MMU page fault has occurred" "0,1" newline bitfld.long 0x8 8. "PM_3D_MEM_FREE,PM memory allocation completed for the current render" "0,1" newline bitfld.long 0x8 7. "PM_OUT_OF_MEMORY,PM memory allocation failed for a macro-tile" "0,1" newline bitfld.long 0x8 6. "TA_TERMINATE,The TE has aborted a macro tile after a failted PM allocation request" "0,1" newline bitfld.long 0x8 5. "TA_FINISHED,The TA phase has completed" "0,1" newline bitfld.long 0x8 4. "ISP_END_MACROTILE,ISP End-of-Macrotile" "0,1" newline bitfld.long 0x8 3. "PIXELBE_END_RENDER,The 3D phase has completed" "0,1" newline bitfld.long 0x8 2. "COMPUTE_FINISHED,The compute phase has completed" "0,1" newline bitfld.long 0x8 1. "KERNEL_FINISHED,A compute kernel has completed and updated the associated event object in external memory" "0,1" newline bitfld.long 0x8 0. "Reserved_0,Reserved_0" "0,1" line.long 0xC "RGX_CR_EVENT_ENABLE_1,This register is used to enable GPU interrupts directly to the host Writing a '1' to a bit field enables the relevant event This register should only be programmed when the META firmware is not used If the META firmware is used. the.." hexmask.long 0xC 0.--31. 1. "Reserved_32,Reserved_32" line.long 0x10 "RGX_CR_EVENT_STATUS_0,The event status register indicate the source of an interrupt generated by PowerVR RGX These events only schedule an interrupt context thread to run on META when the appropriate enables are set in RGX_CR_DMn_INTERRUPT_ENABLE" bitfld.long 0x10 31. "TDM_FENCE_FINISHED,Indicates a 2D fence has been processed" "0,1" newline bitfld.long 0x10 30. "TDM_BUFFER_STALL,The TDM has exhausted the current 2D circular buffer (read pointer = write_pointer)" "0,1" newline hexmask.long.word 0x10 19.--29. 1. "Reserved_19,Reserved_19" newline bitfld.long 0x10 18. "TDM_CONTEXT_STORE_FINISHED,The TDM has completed the requested context store operation." "0,1" newline bitfld.long 0x10 16.--17. "Reserved_16,Reserved_16" "0,1,2,3" newline bitfld.long 0x10 15. "USC_TRIGGER,One or more USC has executed a nop.trigger instruction" "0,1" newline bitfld.long 0x10 14. "ZLS_FINISHED,ZLS has finished all tiles in a Render" "0,1" newline bitfld.long 0x10 13. "GPIO_ACK,General Purpose ouput acknowledgement" "0,1" newline bitfld.long 0x10 12. "GPIO_REQ,General Purpose input request" "0,1" newline bitfld.long 0x10 11. "POWER_ABORT,The requested power operation has been denied." "0,1" newline bitfld.long 0x10 10. "POWER_COMPLETE,The requested power operation has completed" "0,1" newline bitfld.long 0x10 9. "MMU_PAGE_FAULT,An MMU page fault has occurred" "0,1" newline bitfld.long 0x10 8. "PM_3D_MEM_FREE,PM memory allocation completed for the current render" "0,1" newline bitfld.long 0x10 7. "PM_OUT_OF_MEMORY,PM memory allocation failed for a macro-tile" "0,1" newline bitfld.long 0x10 6. "TA_TERMINATE,The TE has aborted a macro tile after a failted PM allocation request" "0,1" newline bitfld.long 0x10 5. "TA_FINISHED,The TA phase has completed" "0,1" newline bitfld.long 0x10 4. "ISP_END_MACROTILE,ISP End-of-Macrotile" "0,1" newline bitfld.long 0x10 3. "PIXELBE_END_RENDER,The 3D phase has completed" "0,1" newline bitfld.long 0x10 2. "COMPUTE_FINISHED,The compute phase has completed" "0,1" newline bitfld.long 0x10 1. "KERNEL_FINISHED,A compute kernel has completed and updated the associated event object in external memory" "0,1" newline bitfld.long 0x10 0. "Reserved_0,Reserved_0" "0,1" line.long 0x14 "RGX_CR_EVENT_STATUS_1,The event status register indicate the source of an interrupt generated by PowerVR RGX These events only schedule an interrupt context thread to run on META when the appropriate enables are set in RGX_CR_DMn_INTERRUPT_ENABLE" hexmask.long 0x14 0.--31. 1. "Reserved_32,Reserved_32" wgroup.long 0x138++0x7 line.long 0x0 "RGX_CR_EVENT_CLEAR_0,This register is used to clear event interrupts. Writing a '1' to a bit field clears the relevant event." bitfld.long 0x0 31. "TDM_FENCE_FINISHED,Indicates a 2D fence has been processed" "0,1" newline bitfld.long 0x0 30. "TDM_BUFFER_STALL,The TDM has exhausted the current 2D circular buffer (read pointer = write_pointer)" "0,1" newline hexmask.long.word 0x0 19.--29. 1. "Reserved_19,Reserved_19" newline bitfld.long 0x0 18. "TDM_CONTEXT_STORE_FINISHED,The TDM has completed the requested context store operation." "0,1" newline bitfld.long 0x0 16.--17. "Reserved_16,Reserved_16" "0,1,2,3" newline bitfld.long 0x0 15. "USC_TRIGGER,One or more USC has executed a nop.trigger instruction" "0,1" newline bitfld.long 0x0 14. "ZLS_FINISHED,ZLS has finished all tiles in a Render" "0,1" newline bitfld.long 0x0 13. "GPIO_ACK,General Purpose ouput acknowledgement" "0,1" newline bitfld.long 0x0 12. "GPIO_REQ,General Purpose input request" "0,1" newline bitfld.long 0x0 11. "POWER_ABORT,The requested power operation has been denied." "0,1" newline bitfld.long 0x0 10. "POWER_COMPLETE,The requested power operation has completed" "0,1" newline bitfld.long 0x0 9. "MMU_PAGE_FAULT,An MMU page fault has occurred" "0,1" newline bitfld.long 0x0 8. "PM_3D_MEM_FREE,PM memory allocation completed for the current render" "0,1" newline bitfld.long 0x0 7. "PM_OUT_OF_MEMORY,PM memory allocation failed for a macro-tile" "0,1" newline bitfld.long 0x0 6. "TA_TERMINATE,The TE has aborted a macro tile after a failted PM allocation request" "0,1" newline bitfld.long 0x0 5. "TA_FINISHED,The TA phase has completed" "0,1" newline bitfld.long 0x0 4. "ISP_END_MACROTILE,ISP End-of-Macrotile" "0,1" newline bitfld.long 0x0 3. "PIXELBE_END_RENDER,The 3D phase has completed" "0,1" newline bitfld.long 0x0 2. "COMPUTE_FINISHED,The compute phase has completed" "0,1" newline bitfld.long 0x0 1. "KERNEL_FINISHED,A compute kernel has completed and updated the associated event object in external memory" "0,1" newline bitfld.long 0x0 0. "Reserved_0,Reserved_0" "0,1" line.long 0x4 "RGX_CR_EVENT_CLEAR_1,This register is used to clear event interrupts. Writing a '1' to a bit field clears the relevant event." hexmask.long 0x4 0.--31. 1. "Reserved_32,Reserved_32" group.long 0x140++0xF line.long 0x0 "RGX_CR_GPIO_OUTPUT_DATA_0,General Purpose Input/Output interface for implementing communication protocol between HW external to Rogue and the firmware These registers are connected to top-level pins These registers are driven by the firmware. When the.." hexmask.long.tbyte 0x0 8.--31. 1. "Reserved_8,Reserved_8" newline hexmask.long.byte 0x0 0.--7. 1. "DATA,The data the firmware wants to transfer" line.long 0x4 "RGX_CR_GPIO_OUTPUT_DATA_1,General Purpose Input/Output interface for implementing communication protocol between HW external to Rogue and the firmware These registers are connected to top-level pins These registers are driven by the firmware. When the.." hexmask.long 0x4 0.--31. 1. "Reserved_8,Reserved_8" line.long 0x8 "RGX_CR_GPIO_OUTPUT_REQ_0,General Purpose Input/Output interface for implementing communication protocol between HW external to Rogue and the firmware This register is connected to a top-level pin This register is driven by the firmware. When the request.." hexmask.long 0x8 1.--31. 1. "Reserved_1,Reserved_1" newline bitfld.long 0x8 0. "REQ,Set when the firmware wants to communicate with a external HW" "0,1" line.long 0xC "RGX_CR_GPIO_OUTPUT_REQ_1,General Purpose Input/Output interface for implementing communication protocol between HW external to Rogue and the firmware This register is connected to a top-level pin This register is driven by the firmware. When the request.." hexmask.long 0xC 0.--31. 1. "Reserved_1,Reserved_1" rgroup.long 0x150++0x7 line.long 0x0 "RGX_CR_GPIO_INPUT_DATA_0,General Purpose Input/Output interface for implementing communication protocol between HW external to Rogue and the firmware This register is connected to top-level pins This register is driven by HW external to rogue before.." hexmask.long.tbyte 0x0 8.--31. 1. "Reserved_8,Reserved_8" newline hexmask.long.byte 0x0 0.--7. 1. "DATA,The incoming data from HW external to Rogue" line.long 0x4 "RGX_CR_GPIO_INPUT_DATA_1,General Purpose Input/Output interface for implementing communication protocol between HW external to Rogue and the firmware This register is connected to top-level pins This register is driven by HW external to rogue before.." hexmask.long 0x4 0.--31. 1. "Reserved_8,Reserved_8" group.long 0x158++0x7 line.long 0x0 "RGX_CR_GPIO_INPUT_ACK_0,General Purpose Input/Output interface for implementing communication protocol between HW external to Rogue and the firmware This register is connected to a top-level pin This register is driven by external HW in response to an.." hexmask.long 0x0 1.--31. 1. "Reserved_1,Reserved_1" newline bitfld.long 0x0 0. "ACK,Set by the firmware when it has acknowledged the incoming request" "0,1" line.long 0x4 "RGX_CR_GPIO_INPUT_ACK_1,General Purpose Input/Output interface for implementing communication protocol between HW external to Rogue and the firmware This register is connected to a top-level pin This register is driven by external HW in response to an.." hexmask.long 0x4 0.--31. 1. "Reserved_1,Reserved_1" rgroup.long 0x160++0x7 line.long 0x0 "RGX_CR_TIMER_0,This register contains the value of a 48-bit internal timer. The timer runs continuously. and wraps at the top end. It counts 256 cycles at the core clock frequency. This means that at 100 MHz: 1 count value = 1/100MHz = 256 * 10 * 10^-9.." hexmask.long 0x0 0.--31. 1. "VALUE,VALUE" line.long 0x4 "RGX_CR_TIMER_1,This register contains the value of a 48-bit internal timer. The timer runs continuously. and wraps at the top end. It counts 256 cycles at the core clock frequency. This means that at 100 MHz: 1 count value = 1/100MHz = 256 * 10 * 10^-9.." bitfld.long 0x4 31. "BIT31,BIT31" "0,1" newline hexmask.long.word 0x4 16.--30. 1. "Reserved_48,Reserved_48" newline hexmask.long.word 0x4 0.--15. 1. "VALUE,VALUE" group.long 0x168++0x7 line.long 0x0 "RGX_CR_AXI_EXACCESS_0,AXI exclusive access enable register" hexmask.long 0x0 1.--31. 1. "Reserved_1,Reserved_1" newline bitfld.long 0x0 0. "SOCIF_ENABLE,enable the exclusive access logic in the socif img_axi2img. vhd module" "0,1" line.long 0x4 "RGX_CR_AXI_EXACCESS_1,AXI exclusive access enable register" hexmask.long 0x4 0.--31. 1. "Reserved_1,Reserved_1" group.long 0x190++0x17 line.long 0x0 "RGX_CR_PM_TASK_MLIST_LOAD_0,This register is part of the parameter management. which controls the allocation and de-allocation of memory for the 3D display list (parameters). The MLIST is the list of Pages which have been allocated to thew MMU. to map.." hexmask.long 0x0 1.--31. 1. "Reserved_1,Reserved_1" newline bitfld.long 0x0 0. "PENDING,A write to this register will cause the MLIST pointer to be loaded from either PM_MLIST0_START_OF or PM_MLIST1_START_OF depending upon the Context ID contained in PM_CONTEXT_ID_MLS_LS. A read to this register return '1' until this operation has.." "0,1" line.long 0x4 "RGX_CR_PM_TASK_MLIST_LOAD_1,This register is part of the parameter management. which controls the allocation and de-allocation of memory for the 3D display list (parameters). The MLIST is the list of Pages which have been allocated to thew MMU. to map.." hexmask.long 0x4 0.--31. 1. "Reserved_1,Reserved_1" line.long 0x8 "RGX_CR_PM_TASK_MLIST_CLEAR_0,This register is part of the parameter management. which controls the allocation and de-allocation of memory for the 3D display list (parameters). The MLIST is the list of Pages which have been allocated to thew MMU. to map.." hexmask.long 0x8 1.--31. 1. "Reserved_1,Reserved_1" newline bitfld.long 0x8 0. "PENDING,A write to this register will cause the MLIST pointer to be reset to 0. A read to this register return '1' until this operation has completed." "0,1" line.long 0xC "RGX_CR_PM_TASK_MLIST_CLEAR_1,This register is part of the parameter management. which controls the allocation and de-allocation of memory for the 3D display list (parameters). The MLIST is the list of Pages which have been allocated to thew MMU. to map.." hexmask.long 0xC 0.--31. 1. "Reserved_1,Reserved_1" line.long 0x10 "RGX_CR_PM_TA_MAX_RENDER_TARGET_0,This register is deprecated and has no function." hexmask.long.tbyte 0x10 11.--31. 1. "Reserved_11,Reserved_11" newline hexmask.long.word 0x10 0.--10. 1. "ID,If used the software should program this with the maximum render target array index used within the Scene" line.long 0x14 "RGX_CR_PM_TA_MAX_RENDER_TARGET_1,This register is deprecated and has no function." hexmask.long 0x14 0.--31. 1. "Reserved_11,Reserved_11" rgroup.long 0x1A8++0x7 line.long 0x0 "RGX_CR_PM_MTILE_ARRAY_REORDER_VALID_STATUS_0,This register is deprecated and has no function." hexmask.long 0x0 1.--31. 1. "Reserved_1,Reserved_1" newline bitfld.long 0x0 0. "OP,OP" "0,1" line.long 0x4 "RGX_CR_PM_MTILE_ARRAY_REORDER_VALID_STATUS_1,This register is deprecated and has no function." hexmask.long 0x4 0.--31. 1. "Reserved_1,Reserved_1" group.long 0x1B0++0x1F line.long 0x0 "RGX_CR_PM_EMPTY_PAGE_FAST_FREEING_0,This register is part of the parameter management. which controls the allocation and de-allocation of memory for the 3D display list (parameters). This register enables an optimisation which causes pages which have.." hexmask.long 0x0 1.--31. 1. "Reserved_1,Reserved_1" newline bitfld.long 0x0 0. "ID,When set enable freeing of unused pages during TA phase" "0,1" line.long 0x4 "RGX_CR_PM_EMPTY_PAGE_FAST_FREEING_1,This register is part of the parameter management. which controls the allocation and de-allocation of memory for the 3D display list (parameters). This register enables an optimisation which causes pages which have.." hexmask.long 0x4 0.--31. 1. "Reserved_1,Reserved_1" line.long 0x8 "RGX_CR_PM_MMU_REMAP_PENDING_0,This register is part of the parameter management. which controls the allocation and de-allocation of memory for the 3D display list (parameters). This register starts the process of remapping the remaining physical pages at.." hexmask.long 0x8 1.--31. 1. "Reserved_1,Reserved_1" newline bitfld.long 0x8 0. "OP,Pending status register corresponding to the MMU remapping operation it will become '1' when written and deassert when the operation complete." "0,1" line.long 0xC "RGX_CR_PM_MMU_REMAP_PENDING_1,This register is part of the parameter management. which controls the allocation and de-allocation of memory for the 3D display list (parameters). This register starts the process of remapping the remaining physical pages at.." hexmask.long 0xC 0.--31. 1. "Reserved_1,Reserved_1" line.long 0x10 "RGX_CR_PM_PBE_FORCE_FREEING_0,This register is part of the parameter management. which controls the allocation and de-allocation of memory for the 3D display list (parameters). Normally freeing of memory is associated with macrotiles (a portion of the.." hexmask.long 0x10 1.--31. 1. "Reserved_1,Reserved_1" newline bitfld.long 0x10 0. "ENABLE,When this bit is set PM will free all the 3D context Memory when a genuine pixelbe end of render is received." "0,1" line.long 0x14 "RGX_CR_PM_PBE_FORCE_FREEING_1,This register is part of the parameter management. which controls the allocation and de-allocation of memory for the 3D display list (parameters). Normally freeing of memory is associated with macrotiles (a portion of the.." hexmask.long 0x14 0.--31. 1. "Reserved_1,Reserved_1" line.long 0x18 "RGX_CR_PM_PDS_STARTOF_MTILEFREE_0,RGX_CR_PM_PDS_STARTOF_MTILEFREE_0" hexmask.long.word 0x18 17.--31. 1. "Reserved_17,Reserved_17" newline hexmask.long.tbyte 0x18 0.--16. 1. "OP,This startof register indicates the macrotile number of the PDSs current macrotile free request needs to be programmed by FW on a render start" line.long 0x1C "RGX_CR_PM_PDS_STARTOF_MTILEFREE_1,RGX_CR_PM_PDS_STARTOF_MTILEFREE_1" hexmask.long 0x1C 0.--31. 1. "Reserved_17,Reserved_17" group.long 0x200++0x1F line.long 0x0 "RGX_CR_PM_TASK_3D_FREE_LOAD_0,RGX_CR_PM_TASK_3D_FREE_LOAD_0" hexmask.long 0x0 1.--31. 1. "Reserved_1,Reserved_1" newline bitfld.long 0x0 0. "PENDING,A write into this register will cause the 3D free list context to be loaded from the relevant configuration registers" "0,1" line.long 0x4 "RGX_CR_PM_TASK_3D_FREE_LOAD_1,RGX_CR_PM_TASK_3D_FREE_LOAD_1" hexmask.long 0x4 0.--31. 1. "Reserved_1,Reserved_1" line.long 0x8 "RGX_CR_PM_TASK_TA_FREE_LOAD_0,RGX_CR_PM_TASK_TA_FREE_LOAD_0" hexmask.long 0x8 1.--31. 1. "Reserved_1,Reserved_1" newline bitfld.long 0x8 0. "PENDING,A write into this register will cause the TA free list context to be loaded from the relevant configuration registers" "0,1" line.long 0xC "RGX_CR_PM_TASK_TA_FREE_LOAD_1,RGX_CR_PM_TASK_TA_FREE_LOAD_1" hexmask.long 0xC 0.--31. 1. "Reserved_1,Reserved_1" line.long 0x10 "RGX_CR_PM_TA_FSTACK_BASE_0,Effective on load TA context. this register defines the base address of the free list stack being referenced during TA processing." hexmask.long 0x10 4.--31. 1. "ADDR,1TB Addressable 128 bits aligned Base Address for TA context page tables in the DPM module" newline hexmask.long.byte 0x10 0.--3. 1. "Reserved_0,Reserved_0" line.long 0x14 "RGX_CR_PM_TA_FSTACK_BASE_1,Effective on load TA context. this register defines the base address of the free list stack being referenced during TA processing." hexmask.long.tbyte 0x14 8.--31. 1. "Reserved_40,Reserved_40" newline hexmask.long.byte 0x14 0.--7. 1. "ADDR,1TB Addressable 128 bits aligned Base Address for TA context page tables in the DPM module" line.long 0x18 "RGX_CR_PM_3D_FSTACK_BASE_0,Effective on load 3D context. this register defines the base address of the free list table being referenced in the process of de-allocating pages during a 3D render." hexmask.long 0x18 4.--31. 1. "ADDR,1TB Addressable 128 bits aligned Base Address for 3D context page tables in the DPM module" newline hexmask.long.byte 0x18 0.--3. 1. "Reserved_0,Reserved_0" line.long 0x1C "RGX_CR_PM_3D_FSTACK_BASE_1,Effective on load 3D context. this register defines the base address of the free list table being referenced in the process of de-allocating pages during a 3D render." hexmask.long.tbyte 0x1C 8.--31. 1. "Reserved_40,Reserved_40" newline hexmask.long.byte 0x1C 0.--7. 1. "ADDR,1TB Addressable 128 bits aligned Base Address for 3D context page tables in the DPM module" repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) group.long ($2+0x220)++0x3 line.long 0x0 "RGX_CR_PM_TA_FSTACK_$1,Note: each 16GB 4KB addressable page (22 bits) is rounded to dword aligned" hexmask.long.word 0x0 22.--31. 1. "Reserved_22,Reserved_22" newline hexmask.long.tbyte 0x0 0.--21. 1. "SIZE,This register defines the number of 4K pages in the free list stack used for the TA page allocation effective on a load TA context." repeat.end group.long 0x230++0x7 line.long 0x0 "RGX_CR_PM_3D_FSTACK_0,Note: each 16GB 4KB addressable page (22 bits) is rounded to dword aligned" hexmask.long.word 0x0 22.--31. 1. "STARTOF_TOP,This register defines the head pointer of the free list in terms of 4K free pages in the free list stack effective on a load TA context." newline hexmask.long.tbyte 0x0 0.--21. 1. "SIZE,This register defines the number of 4K pages in the free list stack used for the TA page allocation effective on a load TA context." line.long 0x4 "RGX_CR_PM_3D_FSTACK_1,Note: each 16GB 4KB addressable page (22 bits) is rounded to dword aligned" hexmask.long.tbyte 0x4 12.--31. 1. "Reserved_44,Reserved_44" newline hexmask.long.word 0x4 0.--11. 1. "STARTOF_TOP,This register defines the head pointer of the free list in terms of 4K free pages in the free list stack effective on a load TA context." group.long 0x240++0x2F line.long 0x0 "RGX_CR_PM_MTILE_ARRAY_0,Effective Immediately." hexmask.long 0x0 4.--31. 1. "BASE_ADDR,1TB Addressable 128 bits aligned Base Address for Mtile Array Base" newline hexmask.long.byte 0x0 0.--3. 1. "Reserved_0,Reserved_0" line.long 0x4 "RGX_CR_PM_MTILE_ARRAY_1,Effective Immediately." hexmask.long.tbyte 0x4 8.--31. 1. "Reserved_40,Reserved_40" newline hexmask.long.byte 0x4 0.--7. 1. "BASE_ADDR,1TB Addressable 128 bits aligned Base Address for Mtile Array Base" line.long 0x8 "RGX_CR_PM_VHEAP_TABLE_0,Effective immediately. this register defines the base address of the virtual heap table information. The size of the Virtual Heap needs to be no smaller than PM_VHEAP_TABLE_SIZE Dwords." hexmask.long 0x8 4.--31. 1. "BASE_ADDR,1TB Addressable 128 bits aligned Base Address for Virtual Heap Table" newline hexmask.long.byte 0x8 0.--3. 1. "Reserved_0,Reserved_0" line.long 0xC "RGX_CR_PM_VHEAP_TABLE_1,Effective immediately. this register defines the base address of the virtual heap table information. The size of the Virtual Heap needs to be no smaller than PM_VHEAP_TABLE_SIZE Dwords." hexmask.long.tbyte 0xC 8.--31. 1. "Reserved_40,Reserved_40" newline hexmask.long.byte 0xC 0.--7. 1. "BASE_ADDR,1TB Addressable 128 bits aligned Base Address for Virtual Heap Table" line.long 0x10 "RGX_CR_PM_TASK_VHEAP_LOAD_0,RGX_CR_PM_TASK_VHEAP_LOAD_0" hexmask.long 0x10 1.--31. 1. "Reserved_1,Reserved_1" newline bitfld.long 0x10 0. "PENDING,Causes the vheap to be loaded as specified by the relevant configuration registers when it is done the hw will clear this bit" "0,1" line.long 0x14 "RGX_CR_PM_TASK_VHEAP_LOAD_1,RGX_CR_PM_TASK_VHEAP_LOAD_1" hexmask.long 0x14 0.--31. 1. "Reserved_1,Reserved_1" line.long 0x18 "RGX_CR_PM_TASK_VHEAP_CLEAR_0,RGX_CR_PM_TASK_VHEAP_CLEAR_0" hexmask.long 0x18 1.--31. 1. "Reserved_1,Reserved_1" newline bitfld.long 0x18 0. "PENDING,Causes the vheap to be cleared as specified by the relevant configuration registers. When it is done the hw will clear this bit" "0,1" line.long 0x1C "RGX_CR_PM_TASK_VHEAP_CLEAR_1,RGX_CR_PM_TASK_VHEAP_CLEAR_1" hexmask.long 0x1C 0.--31. 1. "Reserved_1,Reserved_1" line.long 0x20 "RGX_CR_PM_TASK_VHEAP_STORE_0,RGX_CR_PM_TASK_VHEAP_STORE_0" hexmask.long 0x20 1.--31. 1. "Reserved_1,Reserved_1" newline bitfld.long 0x20 0. "PENDING,Causes the vheap to be stored as specified by the relevant configuration registers. When it is done the hw will clear this bit" "0,1" line.long 0x24 "RGX_CR_PM_TASK_VHEAP_STORE_1,RGX_CR_PM_TASK_VHEAP_STORE_1" hexmask.long 0x24 0.--31. 1. "Reserved_1,Reserved_1" line.long 0x28 "RGX_CR_PM_ALIST0_START_OF_0,start pointer of the allocation list tail.in size of 8 bytes" hexmask.long 0x28 0.--31. 1. "TAIL,allocation List 0 tail pointer" line.long 0x2C "RGX_CR_PM_ALIST0_START_OF_1,start pointer of the allocation list tail.in size of 8 bytes" hexmask.long 0x2C 1.--31. 1. "Reserved_33,Reserved_33" newline bitfld.long 0x2C 0. "TAIL,allocation List 0 tail pointer" "0,1" rgroup.long 0x270++0x7 line.long 0x0 "RGX_CR_PM_ALIST0_STATUS_0,pointer of current allocation list.in size of 8 bytes" hexmask.long 0x0 0.--31. 1. "TAIL,allocation List tail pointer" line.long 0x4 "RGX_CR_PM_ALIST0_STATUS_1,pointer of current allocation list.in size of 8 bytes" hexmask.long 0x4 1.--31. 1. "Reserved_33,Reserved_33" newline bitfld.long 0x4 0. "TAIL,allocation List tail pointer" "0,1" group.long 0x278++0x7 line.long 0x0 "RGX_CR_PM_ALIST1_START_OF_0,start of the tail pointer of current allocation list.effecitve on an allocation_list_load" hexmask.long 0x0 0.--31. 1. "TAIL,start of the allocation list tail pointer" line.long 0x4 "RGX_CR_PM_ALIST1_START_OF_1,start of the tail pointer of current allocation list.effecitve on an allocation_list_load" hexmask.long 0x4 1.--31. 1. "Reserved_33,Reserved_33" newline bitfld.long 0x4 0. "TAIL,start of the allocation list tail pointer" "0,1" rgroup.long 0x280++0x7 line.long 0x0 "RGX_CR_PM_ALIST1_STATUS_0,pointer of current allocation list.in size of 8 bytes" hexmask.long 0x0 0.--31. 1. "TAIL,allocation List tail pointer" line.long 0x4 "RGX_CR_PM_ALIST1_STATUS_1,pointer of current allocation list.in size of 8 bytes" hexmask.long 0x4 1.--31. 1. "Reserved_33,Reserved_33" newline bitfld.long 0x4 0. "TAIL,allocation List tail pointer" "0,1" group.long 0x288++0x1F line.long 0x0 "RGX_CR_PM_TASK_ALIST_LOAD_0,RGX_CR_PM_TASK_ALIST_LOAD_0" hexmask.long 0x0 1.--31. 1. "Reserved_1,Reserved_1" newline bitfld.long 0x0 0. "PENDING,the write to this register will cause allocation list to be loaded from the relevant configuration registers" "0,1" line.long 0x4 "RGX_CR_PM_TASK_ALIST_LOAD_1,RGX_CR_PM_TASK_ALIST_LOAD_1" hexmask.long 0x4 0.--31. 1. "Reserved_1,Reserved_1" line.long 0x8 "RGX_CR_PM_TASK_ALIST_CLEAR_0,RGX_CR_PM_TASK_ALIST_CLEAR_0" hexmask.long 0x8 1.--31. 1. "Reserved_1,Reserved_1" newline bitfld.long 0x8 0. "PENDING,the write to this register will causes the allocation list to be cleard from the relevant configuration registers" "0,1" line.long 0xC "RGX_CR_PM_TASK_ALIST_CLEAR_1,RGX_CR_PM_TASK_ALIST_CLEAR_1" hexmask.long 0xC 0.--31. 1. "Reserved_1,Reserved_1" line.long 0x10 "RGX_CR_PM_DEALLOCATION_STARTOF_MASK_0,RGX_CR_PM_DEALLOCATION_STARTOF_MASK_0" hexmask.long.word 0x10 16.--31. 1. "Reserved_16,Reserved_16" newline hexmask.long.word 0x10 0.--15. 1. "OP,This is the start of the mask PM deallocation will be based on. Normally it is 0. However in ISP context resume or extra 3D timeout case the driver has to programme the value from the previous render." line.long 0x14 "RGX_CR_PM_DEALLOCATION_STARTOF_MASK_1,RGX_CR_PM_DEALLOCATION_STARTOF_MASK_1" hexmask.long 0x14 0.--31. 1. "Reserved_16,Reserved_16" line.long 0x18 "RGX_CR_PM_PAGE_MANAGEOP_0,RGX_CR_PM_PAGE_MANAGEOP_0" hexmask.long 0x18 3.--31. 1. "Reserved_3,Reserved_3" newline bitfld.long 0x18 2. "COMBINE_DALLOC,1 means the PM writes to the free stack will be burst combined" "0,1" newline bitfld.long 0x18 1. "DISABLE_DALLOC,1 means the PM page management deallocation operation will be disabled" "0,1" newline bitfld.long 0x18 0. "DISABLE_ALLOC,1 means the PM page management allocation operation will be disabled" "0,1" line.long 0x1C "RGX_CR_PM_PAGE_MANAGEOP_1,RGX_CR_PM_PAGE_MANAGEOP_1" hexmask.long 0x1C 0.--31. 1. "Reserved_3,Reserved_3" rgroup.long 0x2A8++0x7 line.long 0x0 "RGX_CR_PM_PAGE_MANAGEOP_STATUS_0,RGX_CR_PM_PAGE_MANAGEOP_STATUS_0" hexmask.long 0x0 2.--31. 1. "Reserved_2,Reserved_2" newline bitfld.long 0x0 1. "DALLOC_DISABLED,1 means the PM page management operation has been disabled" "0,1" newline bitfld.long 0x0 0. "ALLOC_DISABLED,1 means the PM page management operation has been disabled" "0,1" line.long 0x4 "RGX_CR_PM_PAGE_MANAGEOP_STATUS_1,RGX_CR_PM_PAGE_MANAGEOP_STATUS_1" hexmask.long 0x4 0.--31. 1. "Reserved_2,Reserved_2" group.long 0x2B0++0xF line.long 0x0 "RGX_CR_PM_CONTEXT_PB_BASE_0,RGX_CR_PM_CONTEXT_PB_BASE_0" hexmask.long 0x0 3.--31. 1. "Reserved_3,Reserved_3" newline bitfld.long 0x0 0.--2. "CMP,Defines whether the TA/3D/HOST contexts are using the same parameter buffer. Setting a bit to '1' indicates that the context is using a different parameter buffer. Bit 0 = 0 : Unified Free List 3D context Parameter buffer = Unified Free List TA.." "MMU Free List 3D context Parameter buffer = MMU..,?,?,?,?,?,?,?" line.long 0x4 "RGX_CR_PM_CONTEXT_PB_BASE_1,RGX_CR_PM_CONTEXT_PB_BASE_1" hexmask.long 0x4 0.--31. 1. "Reserved_3,Reserved_3" line.long 0x8 "RGX_CR_PM_MLIST0_START_OF_0,start value of the mlist tail @ the loading of the context. in size of 4 bytes. stride is 64KB" hexmask.long.word 0x8 22.--31. 1. "Reserved_22,Reserved_22" newline hexmask.long.tbyte 0x8 0.--21. 1. "TAIL,allocation List 0 tail pointer" line.long 0xC "RGX_CR_PM_MLIST0_START_OF_1,start value of the mlist tail @ the loading of the context. in size of 4 bytes. stride is 64KB" hexmask.long 0xC 0.--31. 1. "Reserved_22,Reserved_22" rgroup.long 0x2C0++0x7 line.long 0x0 "RGX_CR_PM_MLIST0_STATUS_0,pointer of current mmu allocation list.in size of 4 bytes. stride is 64KB" hexmask.long.word 0x0 22.--31. 1. "Reserved_22,Reserved_22" newline hexmask.long.tbyte 0x0 0.--21. 1. "TAIL,allocation List 1 tail pointer" line.long 0x4 "RGX_CR_PM_MLIST0_STATUS_1,pointer of current mmu allocation list.in size of 4 bytes. stride is 64KB" hexmask.long 0x4 0.--31. 1. "Reserved_22,Reserved_22" group.long 0x2C8++0x7 line.long 0x0 "RGX_CR_PM_MLIST1_START_OF_0,start of the tail pointer of mmu allocation list.effecitve on an allocation_list_load" hexmask.long.word 0x0 22.--31. 1. "Reserved_22,Reserved_22" newline hexmask.long.tbyte 0x0 0.--21. 1. "TAIL,start of the allocation list 1 tail pointer" line.long 0x4 "RGX_CR_PM_MLIST1_START_OF_1,start of the tail pointer of mmu allocation list.effecitve on an allocation_list_load" hexmask.long 0x4 0.--31. 1. "Reserved_22,Reserved_22" rgroup.long 0x2D0++0x7 line.long 0x0 "RGX_CR_PM_MLIST1_STATUS_0,pointer of mmu allocation list1 pointer.in size of 4 bytes" hexmask.long.word 0x0 22.--31. 1. "Reserved_22,Reserved_22" newline hexmask.long.tbyte 0x0 0.--21. 1. "TAIL,mmu allocation List 1 tail pointer" line.long 0x4 "RGX_CR_PM_MLIST1_STATUS_1,pointer of mmu allocation list1 pointer.in size of 4 bytes" hexmask.long 0x4 0.--31. 1. "Reserved_22,Reserved_22" group.long 0x2D8++0xF line.long 0x0 "RGX_CR_PM_MLIST0_BASE_0,This register defines the base address of the mmu list 0 for the mmu pages. the stride has to be 64KBytes" hexmask.long 0x0 4.--31. 1. "ADDR,1TB Addressable 128 bits aligned Base Address for mmu list0 module Effective Immediately" newline hexmask.long.byte 0x0 0.--3. 1. "Reserved_0,Reserved_0" line.long 0x4 "RGX_CR_PM_MLIST0_BASE_1,This register defines the base address of the mmu list 0 for the mmu pages. the stride has to be 64KBytes" hexmask.long.tbyte 0x4 8.--31. 1. "Reserved_40,Reserved_40" newline hexmask.long.byte 0x4 0.--7. 1. "ADDR,1TB Addressable 128 bits aligned Base Address for mmu list0 module Effective Immediately" line.long 0x8 "RGX_CR_PM_MLIST1_BASE_0,This register defines the base address of the mmu list 1 for the mmu pages. the stride has to be a 64KBytes" hexmask.long 0x8 4.--31. 1. "ADDR,1TB Addressable 128 bits aligned Base Address for mmu list1 module Effective Immediately" newline hexmask.long.byte 0x8 0.--3. 1. "Reserved_0,Reserved_0" line.long 0xC "RGX_CR_PM_MLIST1_BASE_1,This register defines the base address of the mmu list 1 for the mmu pages. the stride has to be a 64KBytes" hexmask.long.tbyte 0xC 8.--31. 1. "Reserved_40,Reserved_40" newline hexmask.long.byte 0xC 0.--7. 1. "ADDR,1TB Addressable 128 bits aligned Base Address for mmu list1 module Effective Immediately" rgroup.long 0x2F8++0x27 line.long 0x0 "RGX_CR_PM_VCE_VTOP_STATUS_0,RGX_CR_PM_VCE_VTOP_STATUS_0" hexmask.long.word 0x0 20.--31. 1. "Reserved_20,Reserved_20" newline hexmask.long.tbyte 0x0 0.--19. 1. "OP,Virtual Page Pointer for the VCE 16KB granauality" line.long 0x4 "RGX_CR_PM_VCE_VTOP_STATUS_1,RGX_CR_PM_VCE_VTOP_STATUS_1" hexmask.long 0x4 0.--31. 1. "Reserved_20,Reserved_20" line.long 0x8 "RGX_CR_PM_TE_VTOP_STATUS_0,RGX_CR_PM_TE_VTOP_STATUS_0" hexmask.long.word 0x8 20.--31. 1. "Reserved_20,Reserved_20" newline hexmask.long.tbyte 0x8 0.--19. 1. "OP,Virtual Page Pointer for the TE 16KB granauality" line.long 0xC "RGX_CR_PM_TE_VTOP_STATUS_1,RGX_CR_PM_TE_VTOP_STATUS_1" hexmask.long 0xC 0.--31. 1. "Reserved_20,Reserved_20" line.long 0x10 "RGX_CR_PM_OUTOF_MEM_SRC_0,RGX_CR_PM_OUTOF_MEM_SRC_0" hexmask.long 0x10 3.--31. 1. "Reserved_3,Reserved_3" newline bitfld.long 0x10 0.--2. "OP,one hot encoding indicating which part of resource runs out of memory bit 0: normal ta free list bit 1: unified ta free list bit 2: mmu free list" "normal ta free list,unified ta free list,mmu free list,?,?,?,?,?" line.long 0x14 "RGX_CR_PM_OUTOF_MEM_SRC_1,RGX_CR_PM_OUTOF_MEM_SRC_1" hexmask.long 0x14 0.--31. 1. "Reserved_3,Reserved_3" line.long 0x18 "RGX_CR_PM_ALIST_VTOP_STATUS_0,RGX_CR_PM_ALIST_VTOP_STATUS_0" hexmask.long.word 0x18 20.--31. 1. "Reserved_20,Reserved_20" newline hexmask.long.tbyte 0x18 0.--19. 1. "OP,Virtual Page Pointer for the allocation list 16KB granauality" line.long 0x1C "RGX_CR_PM_ALIST_VTOP_STATUS_1,RGX_CR_PM_ALIST_VTOP_STATUS_1" hexmask.long 0x1C 0.--31. 1. "Reserved_20,Reserved_20" line.long 0x20 "RGX_CR_PM_MMU_VTOP_STATUS_0,RGX_CR_PM_MMU_VTOP_STATUS_0" hexmask.long.word 0x20 20.--31. 1. "Reserved_20,Reserved_20" newline hexmask.long.tbyte 0x20 0.--19. 1. "OP,Virtual Page Pointer for the MMU 4KB granauality" line.long 0x24 "RGX_CR_PM_MMU_VTOP_STATUS_1,RGX_CR_PM_MMU_VTOP_STATUS_1" hexmask.long 0x24 0.--31. 1. "Reserved_20,Reserved_20" wgroup.long 0x320++0xF line.long 0x0 "RGX_CR_PM_OUTOFMEM_ABORTALL_0,RGX_CR_PM_OUTOFMEM_ABORTALL_0" hexmask.long 0x0 1.--31. 1. "Reserved_1,Reserved_1" newline bitfld.long 0x0 0. "OP,Instruct the PM to Deny the TE allocation outstanding on Out Of Memory" "0,1" line.long 0x4 "RGX_CR_PM_OUTOFMEM_ABORTALL_1,RGX_CR_PM_OUTOFMEM_ABORTALL_1" hexmask.long 0x4 0.--31. 1. "Reserved_1,Reserved_1" line.long 0x8 "RGX_CR_PM_OUTOFMEM_RESTART_0,RGX_CR_PM_OUTOFMEM_RESTART_0" hexmask.long 0x8 1.--31. 1. "Reserved_1,Reserved_1" newline bitfld.long 0x8 0. "OP,Restart the PM after an Out of Memory and Abort sequence" "0,1" line.long 0xC "RGX_CR_PM_OUTOFMEM_RESTART_1,RGX_CR_PM_OUTOFMEM_RESTART_1" hexmask.long 0xC 0.--31. 1. "Reserved_1,Reserved_1" rgroup.long 0x330++0x7 line.long 0x0 "RGX_CR_PM_REQUESTING_SOURCE_0,RGX_CR_PM_REQUESTING_SOURCE_0" hexmask.long 0x0 2.--31. 1. "Reserved_2,Reserved_2" newline bitfld.long 0x0 0.--1. "OP,Requesting source when out of memory. Bit 1 : VCE Bit 0 : TE" "TE,VCE,?,?" line.long 0x4 "RGX_CR_PM_REQUESTING_SOURCE_1,RGX_CR_PM_REQUESTING_SOURCE_1" hexmask.long 0x4 0.--31. 1. "Reserved_2,Reserved_2" group.long 0x338++0xF line.long 0x0 "RGX_CR_PM_PARTIAL_RENDER_ENABLE_0,RGX_CR_PM_PARTIAL_RENDER_ENABLE_0" hexmask.long 0x0 1.--31. 1. "Reserved_1,Reserved_1" newline bitfld.long 0x0 0. "OP,Partial Render Enable Bit" "0,1" line.long 0x4 "RGX_CR_PM_PARTIAL_RENDER_ENABLE_1,RGX_CR_PM_PARTIAL_RENDER_ENABLE_1" hexmask.long 0x4 0.--31. 1. "Reserved_1,Reserved_1" line.long 0x8 "RGX_CR_PM_3D_DEALLOCATE_SCANMODE_0,RGX_CR_PM_3D_DEALLOCATE_SCANMODE_0" hexmask.long 0x8 5.--31. 1. "Reserved_5,Reserved_5" newline hexmask.long.byte 0x8 0.--4. 1. "OP,This register defines the deallocation behaviour of the PM: value > 2 is only for debug on ZLS mode 0 it can only set less than 2 0: PM will free the macrotile memory as soon as it is possible 1: PM only free one mtile for each traverse 2: PM only.." line.long 0xC "RGX_CR_PM_3D_DEALLOCATE_SCANMODE_1,RGX_CR_PM_3D_DEALLOCATE_SCANMODE_1" hexmask.long 0xC 0.--31. 1. "Reserved_5,Reserved_5" rgroup.long 0x348++0xF line.long 0x0 "RGX_CR_PM_TA_FSTACK_STATUS_0,Note: this is the pointer pointing to the TA free stack top. (4KB page pointer)" hexmask.long.word 0x0 22.--31. 1. "Reserved_22,Reserved_22" newline hexmask.long.tbyte 0x0 0.--21. 1. "TOP,This status register indicated the ta context free list pointer status." line.long 0x4 "RGX_CR_PM_TA_FSTACK_STATUS_1,Note: this is the pointer pointing to the TA free stack top. (4KB page pointer)" hexmask.long 0x4 0.--31. 1. "Reserved_22,Reserved_22" line.long 0x8 "RGX_CR_PM_3D_FSTACK_STATUS_0,Note: this is the pointer pointing to the 3D free stack top. (4KB page pointer)" hexmask.long.word 0x8 22.--31. 1. "Reserved_22,Reserved_22" newline hexmask.long.tbyte 0x8 0.--21. 1. "TOP,This status register indicated the 3D context free list status" line.long 0xC "RGX_CR_PM_3D_FSTACK_STATUS_1,Note: this is the pointer pointing to the 3D free stack top. (4KB page pointer)" hexmask.long 0xC 0.--31. 1. "Reserved_22,Reserved_22" group.long 0x358++0x7 line.long 0x0 "RGX_CR_PM_RESERVE_PAGES_0,RGX_CR_PM_RESERVE_PAGES_0" hexmask.long.word 0x0 16.--31. 1. "Reserved_16,Reserved_16" newline hexmask.long.word 0x0 0.--15. 1. "OP,This register defines the guard page required for one VCE/TE allocation. The requirement is set by the number of ppages needed to create the ALIST nodes when a vpage is closed. The MMU requirement is fixed at 3 ppages max for creatig a new ALIST.." line.long 0x4 "RGX_CR_PM_RESERVE_PAGES_1,RGX_CR_PM_RESERVE_PAGES_1" hexmask.long 0x4 0.--31. 1. "Reserved_16,Reserved_16" rgroup.long 0x360++0x17 line.long 0x0 "RGX_CR_PM_DEALLOCATED_MASK_STATUS_0,RGX_CR_PM_DEALLOCATED_MASK_STATUS_0" hexmask.long.word 0x0 16.--31. 1. "Reserved_16,Reserved_16" newline hexmask.long.word 0x0 0.--15. 1. "TOP,This status register contains a bitmask of the macrotiles freed at this point in the render" line.long 0x4 "RGX_CR_PM_DEALLOCATED_MASK_STATUS_1,RGX_CR_PM_DEALLOCATED_MASK_STATUS_1" hexmask.long 0x4 0.--31. 1. "Reserved_16,Reserved_16" line.long 0x8 "RGX_CR_PM_DEALLOCATING_MASK_STATUS_0,RGX_CR_PM_DEALLOCATING_MASK_STATUS_0" hexmask.long.word 0x8 16.--31. 1. "Reserved_16,Reserved_16" newline hexmask.long.word 0x8 0.--15. 1. "TOP,This status register indicates the mtile mask being freed at the current traverse" line.long 0xC "RGX_CR_PM_DEALLOCATING_MASK_STATUS_1,RGX_CR_PM_DEALLOCATING_MASK_STATUS_1" hexmask.long 0xC 0.--31. 1. "Reserved_16,Reserved_16" line.long 0x10 "RGX_CR_PM_PDS_MTILEFREE_STATUS_0,RGX_CR_PM_PDS_MTILEFREE_STATUS_0" hexmask.long.word 0x10 17.--31. 1. "Reserved_17,Reserved_17" newline hexmask.long.tbyte 0x10 0.--16. 1. "OP,This status register indicates the macrotile number of the PDSs current macrotile free request" line.long 0x14 "RGX_CR_PM_PDS_MTILEFREE_STATUS_1,RGX_CR_PM_PDS_MTILEFREE_STATUS_1" hexmask.long 0x14 0.--31. 1. "Reserved_17,Reserved_17" group.long 0x378++0x7 line.long 0x0 "RGX_CR_PM_TA_FREE_CONTEXT_0,RGX_CR_PM_TA_FREE_CONTEXT_0" hexmask.long 0x0 1.--31. 1. "Reserved_1,Reserved_1" newline bitfld.long 0x0 0. "PENDING,free the ta context register operation" "0,1" line.long 0x4 "RGX_CR_PM_TA_FREE_CONTEXT_1,RGX_CR_PM_TA_FREE_CONTEXT_1" hexmask.long 0x4 0.--31. 1. "Reserved_1,Reserved_1" wgroup.long 0x380++0x7 line.long 0x0 "RGX_CR_PM_3D_TIMEOUT_NOW_0,RGX_CR_PM_3D_TIMEOUT_NOW_0" hexmask.long 0x0 1.--31. 1. "Reserved_1,Reserved_1" newline bitfld.long 0x0 0. "OP,free the 3D context" "0,1" line.long 0x4 "RGX_CR_PM_3D_TIMEOUT_NOW_1,RGX_CR_PM_3D_TIMEOUT_NOW_1" hexmask.long 0x4 0.--31. 1. "Reserved_1,Reserved_1" group.long 0x388++0x7 line.long 0x0 "RGX_CR_PM_3D_DEALLOCATE_ENABLE_0,RGX_CR_PM_3D_DEALLOCATE_ENABLE_0" hexmask.long 0x0 1.--31. 1. "Reserved_1,Reserved_1" newline bitfld.long 0x0 0. "OP,3D deallocate enable mode" "0,1" line.long 0x4 "RGX_CR_PM_3D_DEALLOCATE_ENABLE_1,RGX_CR_PM_3D_DEALLOCATE_ENABLE_1" hexmask.long 0x4 0.--31. 1. "Reserved_1,Reserved_1" repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) group.long ($2+0x390)++0x3 line.long 0x0 "RGX_CR_PM_START_OF_TACONTEXT_$1,RGX_CR_PM_START_OF_TACONTEXT_0" hexmask.long.word 0x0 22.--31. 1. "Reserved_22,Reserved_22" newline hexmask.long.tbyte 0x0 0.--21. 1. "ALLOCATED_PAGE,Start of TA pages(4KB) on loading of the TA context" repeat.end repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) group.long ($2+0x398)++0x3 line.long 0x0 "RGX_CR_PM_START_OF_3DCONTEXT_$1,RGX_CR_PM_START_OF_3DCONTEXT_0" hexmask.long.word 0x0 22.--31. 1. "Reserved_22,Reserved_22" newline hexmask.long.tbyte 0x0 0.--21. 1. "ALLOCATED_PAGE,Start of 3D pages(4KB) on loading of the TA context" repeat.end rgroup.long 0x3A0++0x2F line.long 0x0 "RGX_CR_PM_TA_PAGE_STATUS_0,RGX_CR_PM_TA_PAGE_STATUS_0" hexmask.long.word 0x0 22.--31. 1. "Reserved_22,Reserved_22" newline hexmask.long.tbyte 0x0 0.--21. 1. "OP,The number of TA pages currently allocated" line.long 0x4 "RGX_CR_PM_TA_PAGE_STATUS_1,RGX_CR_PM_TA_PAGE_STATUS_1" hexmask.long 0x4 0.--31. 1. "Reserved_22,Reserved_22" line.long 0x8 "RGX_CR_PM_3D_PAGE_STATUS_0,RGX_CR_PM_3D_PAGE_STATUS_0" hexmask.long.word 0x8 22.--31. 1. "Reserved_22,Reserved_22" newline hexmask.long.tbyte 0x8 0.--21. 1. "OP,The number of 3D pages currently allocated" line.long 0xC "RGX_CR_PM_3D_PAGE_STATUS_1,RGX_CR_PM_3D_PAGE_STATUS_1" hexmask.long 0xC 0.--31. 1. "Reserved_22,Reserved_22" line.long 0x10 "RGX_CR_PM_VCE_INFLIGHT_STATUS_0,RGX_CR_PM_VCE_INFLIGHT_STATUS_0" hexmask.long.word 0x10 20.--31. 1. "Reserved_20,Reserved_20" newline hexmask.long.tbyte 0x10 0.--19. 1. "OP,The Virtual Page Number in flight in the VCE Requestor" line.long 0x14 "RGX_CR_PM_VCE_INFLIGHT_STATUS_1,RGX_CR_PM_VCE_INFLIGHT_STATUS_1" hexmask.long 0x14 0.--31. 1. "Reserved_20,Reserved_20" line.long 0x18 "RGX_CR_PM_TE_INFLIGHT_STATUS_0,RGX_CR_PM_TE_INFLIGHT_STATUS_0" hexmask.long.word 0x18 20.--31. 1. "Reserved_20,Reserved_20" newline hexmask.long.tbyte 0x18 0.--19. 1. "OP,The Virtual Page Number in flight in the TE Requestor" line.long 0x1C "RGX_CR_PM_TE_INFLIGHT_STATUS_1,RGX_CR_PM_TE_INFLIGHT_STATUS_1" hexmask.long 0x1C 0.--31. 1. "Reserved_20,Reserved_20" line.long 0x20 "RGX_CR_BIFPM_IDLE_0,RGX_CR_BIFPM_IDLE_0" hexmask.long 0x20 7.--31. 1. "Reserved_7,Reserved_7" newline bitfld.long 0x20 6. "MCU_L0_MEMIF,MCU L0 MEMIF Module IDLE" "0,1" newline bitfld.long 0x20 5. "PBE,PBE Module IDLE" "0,1" newline bitfld.long 0x20 4. "MCU_L0_PDSRW,MCU L0 PDSRW Module IDLE" "0,1" newline bitfld.long 0x20 3. "MCU_L1,MCU L1 Module IDLE" "0,1" newline bitfld.long 0x20 2. "USCS,USC Shared Module IDLE" "0,1" newline bitfld.long 0x20 1. "PM,PM Module IDLE" "0,1" newline bitfld.long 0x20 0. "BIF256,BIF256 Module IDLE" "0,1" line.long 0x24 "RGX_CR_BIFPM_IDLE_1,RGX_CR_BIFPM_IDLE_1" hexmask.long 0x24 0.--31. 1. "Reserved_7,Reserved_7" line.long 0x28 "RGX_CR_SIDEKICK_IDLE_0,RGX_CR_SIDEKICK_IDLE_0" hexmask.long 0x28 7.--31. 1. "Reserved_7,Reserved_7" newline bitfld.long 0x28 6. "FB_CDC,FB CDC Module IDLE" "0,1" newline bitfld.long 0x28 5. "MMU,MMU Module IDLE" "0,1" newline bitfld.long 0x28 4. "BIF128,BIF128 Module IDLE" "0,1" newline bitfld.long 0x28 3. "TLA,TLA Module IDLE" "0,1" newline bitfld.long 0x28 2. "GARTEN,GARTEN Module IDLE" "0,1" newline bitfld.long 0x28 1. "HOSTIF,HOSTIF Module IDLE" "0,1" newline bitfld.long 0x28 0. "SOCIF,SOCIF Module IDLE" "0,1" line.long 0x2C "RGX_CR_SIDEKICK_IDLE_1,RGX_CR_SIDEKICK_IDLE_1" hexmask.long 0x2C 0.--31. 1. "Reserved_7,Reserved_7" group.long 0x3D0++0x17 line.long 0x0 "RGX_CR_PM_CONTEXT_ID_0,RGX_CR_PM_CONTEXT_ID_0" hexmask.long.byte 0x0 25.--31. 1. "Reserved_25,Reserved_25" newline bitfld.long 0x0 24. "MLIS_ALLOC,MMU page List (TE VCE aligned with this context )Allocation Context ID" "0,1" newline hexmask.long.byte 0x0 17.--23. 1. "Reserved_17,Reserved_17" newline bitfld.long 0x0 16. "LS,Load Store Context ID for the allocation list" "0,1" newline hexmask.long.byte 0x0 9.--15. 1. "Reserved_9,Reserved_9" newline bitfld.long 0x0 8. "DALLOC,DeAllocation Context ID for the allocation list" "0,1" newline hexmask.long.byte 0x0 1.--7. 1. "Reserved_1,Reserved_1" newline bitfld.long 0x0 0. "ALLOC,Allocation Context ID for the allocation list" "0,1" line.long 0x4 "RGX_CR_PM_CONTEXT_ID_1,RGX_CR_PM_CONTEXT_ID_1" hexmask.long.tbyte 0x4 9.--31. 1. "Reserved_41,Reserved_41" newline bitfld.long 0x4 8. "MLIS_LS,MMU page List (TE VCE aligned with this context )Load Store Context ID" "0,1" newline hexmask.long.byte 0x4 1.--7. 1. "Reserved_33,Reserved_33" newline bitfld.long 0x4 0. "MLIS_DALLOC,MMU page List (TE VCE aligned with this context )DeAllocation Context ID" "0,1" line.long 0x8 "RGX_CR_PM_3D_RENDER_TARGET_INDEX_0,RGX_CR_PM_3D_RENDER_TARGET_INDEX_0" hexmask.long.tbyte 0x8 11.--31. 1. "Reserved_11,Reserved_11" newline hexmask.long.word 0x8 0.--10. 1. "ID,Render Target ID which is being rendered" line.long 0xC "RGX_CR_PM_3D_RENDER_TARGET_INDEX_1,RGX_CR_PM_3D_RENDER_TARGET_INDEX_1" hexmask.long 0xC 0.--31. 1. "Reserved_11,Reserved_11" line.long 0x10 "RGX_CR_PM_3D_RENDER_TARGET_LAST_0,RGX_CR_PM_3D_RENDER_TARGET_LAST_0" hexmask.long 0x10 1.--31. 1. "Reserved_1,Reserved_1" newline bitfld.long 0x10 0. "ID,If this bit is set this means the render will be the last one in the whole render target array. If no multiple render target array is present this bit always needs set" "0,1" line.long 0x14 "RGX_CR_PM_3D_RENDER_TARGET_LAST_1,RGX_CR_PM_3D_RENDER_TARGET_LAST_1" hexmask.long 0x14 0.--31. 1. "Reserved_1,Reserved_1" rgroup.long 0x3E8++0x17 line.long 0x0 "RGX_CR_PM_LOCK_STATUS_0,RGX_CR_PM_LOCK_STATUS_0" hexmask.long 0x0 2.--31. 1. "Reserved_2,Reserved_2" newline bitfld.long 0x0 1. "TD,Bit 1: 3D free list Lock Status. 0 idle/ 1 used" "0,1" newline bitfld.long 0x0 0. "TA,Bit 0: TA free list Lock Status. 0 idle/ 1 used." "TA free list Lock Status,?" line.long 0x4 "RGX_CR_PM_LOCK_STATUS_1,RGX_CR_PM_LOCK_STATUS_1" hexmask.long 0x4 0.--31. 1. "Reserved_2,Reserved_2" line.long 0x8 "RGX_CR_PM_LOCK_OWNER_0,RGX_CR_PM_LOCK_OWNER_0" hexmask.long 0x8 2.--31. 1. "Reserved_2,Reserved_2" newline bitfld.long 0x8 1. "TD,Bit 1 :3D free list Lock owner. 0 PMA / 1 PMD" "0,1" newline bitfld.long 0x8 0. "TA,Bit 0: TA free list Lock Owner. 0 PMA / 1 PMD." "TA free list Lock Owner,?" line.long 0xC "RGX_CR_PM_LOCK_OWNER_1,RGX_CR_PM_LOCK_OWNER_1" hexmask.long 0xC 0.--31. 1. "Reserved_2,Reserved_2" line.long 0x10 "RGX_CR_PM_IDLE_STATUS_0,RGX_CR_PM_IDLE_STATUS_0" hexmask.long.tbyte 0x10 8.--31. 1. "Reserved_8,Reserved_8" newline bitfld.long 0x10 7. "PMD_BIF,Idle Status Register of the PMD module bif state machine" "0,1" newline bitfld.long 0x10 6. "PMD_FRE,Idle Status Register of the PMD module master state machine" "0,1" newline bitfld.long 0x10 5. "BIF,Idle Status Register of the BIF Interface default" "0,1" newline bitfld.long 0x10 4. "BARB,Idle Status Register of the BIF Arbiter state BAR" "0,1" newline bitfld.long 0x10 3. "AMAN,Idle Status Register of the Alist state machine" "0,1" newline bitfld.long 0x10 2. "STA,Idle Status Register of the Stack Manager Modul" "0,1" newline bitfld.long 0x10 1. "PMD,Idle Status Register of the PMD module" "0,1" newline bitfld.long 0x10 0. "PMA,Idle Status Register of the PMA module" "0,1" line.long 0x14 "RGX_CR_PM_IDLE_STATUS_1,RGX_CR_PM_IDLE_STATUS_1" hexmask.long 0x14 0.--31. 1. "Reserved_8,Reserved_8" wgroup.long 0x400++0x7 line.long 0x0 "RGX_CR_VDM_START_0,A write of '1' to this register starts the Vertex Data Master (TA) Reading the control stream pointed to by VDM_CTRL_STREAM_BASE" hexmask.long 0x0 1.--31. 1. "Reserved_1,Reserved_1" newline bitfld.long 0x0 0. "PULSE,Start VDM" "0,1" line.long 0x4 "RGX_CR_VDM_START_1,A write of '1' to this register starts the Vertex Data Master (TA) Reading the control stream pointed to by VDM_CTRL_STREAM_BASE" hexmask.long 0x4 0.--31. 1. "Reserved_1,Reserved_1" group.long 0x408++0x7 line.long 0x0 "RGX_CR_VDM_CTRL_STREAM_BASE_0,The base address of the Vertex Data Master's Input Parameter Control Stream in external memory" hexmask.long 0x0 2.--31. 1. "ADDR,1TB range 32-bit aligned base address" newline bitfld.long 0x0 0.--1. "Reserved_0,Reserved_0" "0,1,2,3" line.long 0x4 "RGX_CR_VDM_CTRL_STREAM_BASE_1,The base address of the Vertex Data Master's Input Parameter Control Stream in external memory" hexmask.long.tbyte 0x4 8.--31. 1. "Reserved_40,Reserved_40" newline hexmask.long.byte 0x4 0.--7. 1. "ADDR,1TB range 32-bit aligned base address" rgroup.long 0x410++0x7 line.long 0x0 "RGX_CR_VDM_CTRL_STREAM_CURRENT_0,This status register reports the current position in the input parameter format of the data being processed. This is a debug register. This is NOT the fetch address presented to the BIF. which is reading ahead Since the.." hexmask.long 0x0 2.--31. 1. "ADDR,1TB range 32-bit aligned address" newline bitfld.long 0x0 0.--1. "Reserved_0,Reserved_0" "0,1,2,3" line.long 0x4 "RGX_CR_VDM_CTRL_STREAM_CURRENT_1,This status register reports the current position in the input parameter format of the data being processed. This is a debug register. This is NOT the fetch address presented to the BIF. which is reading ahead Since the.." hexmask.long.tbyte 0x4 8.--31. 1. "Reserved_40,Reserved_40" newline hexmask.long.byte 0x4 0.--7. 1. "ADDR,1TB range 32-bit aligned address" group.long 0x418++0x17 line.long 0x0 "RGX_CR_VDM_CALL_STACK_POINTER_0,The pointer to the control stream call stack. The current pointer within the VDM's call stack in external memory. The call stack is used whenever a call is made to another control stream. to store the return address.." hexmask.long 0x0 3.--31. 1. "ADDR,1TB range 64-bit aligned base address" newline bitfld.long 0x0 0.--2. "Reserved_0,Reserved_0" "0,1,2,3,4,5,6,7" line.long 0x4 "RGX_CR_VDM_CALL_STACK_POINTER_1,The pointer to the control stream call stack. The current pointer within the VDM's call stack in external memory. The call stack is used whenever a call is made to another control stream. to store the return address.." hexmask.long.tbyte 0x4 8.--31. 1. "Reserved_40,Reserved_40" newline hexmask.long.byte 0x4 0.--7. 1. "ADDR,1TB range 64-bit aligned base address" line.long 0x8 "RGX_CR_VDM_BATCH_0,The Batch number is a index list block (draw call) ID which is passed through the GPU pipeline. This is helpful for debug and performance profiling. The starting batch number should be programmed before the first TA phase of every.." hexmask.long.tbyte 0x8 14.--31. 1. "Reserved_14,Reserved_14" newline hexmask.long.word 0x8 0.--13. 1. "NUMBER,NUMBER" line.long 0xC "RGX_CR_VDM_BATCH_1,The Batch number is a index list block (draw call) ID which is passed through the GPU pipeline. This is helpful for debug and performance profiling. The starting batch number should be programmed before the first TA phase of every.." hexmask.long 0xC 0.--31. 1. "Reserved_14,Reserved_14" line.long 0x10 "RGX_CR_VDM_CONTEXT_STATE_BASE_0,The base address in external memory of the VDM's context state buffer. On a context store the VDM will store its state to this address. and reload it on a context resume. The size and format of the data written is defined.." hexmask.long 0x10 4.--31. 1. "ADDR,1TB range 128-bit aligned base address" newline hexmask.long.byte 0x10 0.--3. 1. "Reserved_0,Reserved_0" line.long 0x14 "RGX_CR_VDM_CONTEXT_STATE_BASE_1,The base address in external memory of the VDM's context state buffer. On a context store the VDM will store its state to this address. and reload it on a context resume. The size and format of the data written is defined.." hexmask.long.tbyte 0x14 8.--31. 1. "Reserved_40,Reserved_40" newline hexmask.long.byte 0x14 0.--7. 1. "ADDR,1TB range 128-bit aligned base address" rgroup.long 0x430++0x7 line.long 0x0 "RGX_CR_VDM_CONTEXT_STORE_STATUS_0,This register indicates the status of a VDM context switch operation. If a context store has been requested. then this muist be sample on TA finished. The firmware must wait for the COMPLETE bit to be set. The.." hexmask.long.tbyte 0x0 8.--31. 1. "Reserved_8,Reserved_8" newline hexmask.long.byte 0x0 4.--7. 1. "LAST_PIPE,The TA pipe number to which the VDM last sent indices" newline bitfld.long 0x0 2.--3. "Reserved_2,Reserved_2" "0,1,2,3" newline bitfld.long 0x0 1. "NEED_RESUME,The VDM still has control stream left to process meaning this context must be resumed" "0,1" newline bitfld.long 0x0 0. "COMPLETE,The VDM has completed the context store operation and fenced its state to external memory" "0,1" line.long 0x4 "RGX_CR_VDM_CONTEXT_STORE_STATUS_1,This register indicates the status of a VDM context switch operation. If a context store has been requested. then this muist be sample on TA finished. The firmware must wait for the COMPLETE bit to be set. The.." hexmask.long 0x4 0.--31. 1. "Reserved_8,Reserved_8" repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) group.long ($2+0x438)++0x3 line.long 0x0 "RGX_CR_VDM_CONTEXT_STORE_TASK0_$1,These words define the PDS State Update task which will be inserted into the VDM pipeline on a context store operation. The function of this task is described in the Rogue Context Switching Hardware Specification. Their.." hexmask.long 0x0 0.--31. 1. "PDS_STATE0,PDS_STATE0" repeat.end repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) group.long ($2+0x440)++0x3 line.long 0x0 "RGX_CR_VDM_CONTEXT_STORE_TASK1_$1,This word defines the PDS State Update task which will be inserted into the VDM pipeline on a context store operation. The function of this task is described in the Rogue Context Switching Hardware Specification. Its.." hexmask.long 0x0 0.--31. 1. "PDS_STATE2,PDS_STATE2" repeat.end repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) group.long ($2+0x448)++0x3 line.long 0x0 "RGX_CR_VDM_CONTEXT_STORE_TASK2_$1,These words defines the Stream Out Sync program which will be inserted into the VDM pipeline as a PPP State Update on a context store operation. The function of this task is described in the Rogue Context Switching.." hexmask.long 0x0 0.--31. 1. "STREAM_OUT1,STREAM_OUT1" repeat.end repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) group.long ($2+0x450)++0x3 line.long 0x0 "RGX_CR_VDM_CONTEXT_RESUME_TASK0_$1,These words define the PDS State Update task which will be written by the VDM to its context resume control stream on a context store operation. The function of this task is described in the Rogue Context Switching.." hexmask.long 0x0 0.--31. 1. "PDS_STATE0,PDS_STATE0" repeat.end repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) group.long ($2+0x458)++0x3 line.long 0x0 "RGX_CR_VDM_CONTEXT_RESUME_TASK1_$1,This word defines the PDS State Update task which will be written by the VDM to its context resume control stream on a context store operation. The function of this task is described in the Rogue Context Switching.." hexmask.long 0x0 0.--31. 1. "PDS_STATE2,PDS_STATE2" repeat.end repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) group.long ($2+0x460)++0x3 line.long 0x0 "RGX_CR_VDM_CONTEXT_RESUME_TASK2_$1,These words defines the Stream Out Sync program which will be written. as a PPP State Update. by the VDM to its context resume control stream on a context store operation The function of this task is described in the.." hexmask.long 0x0 0.--31. 1. "STREAM_OUT1,STREAM_OUT1" repeat.end wgroup.long 0x468++0x7 line.long 0x0 "RGX_CR_VDM_CONTEXT_STORE_START_0,Writing '1' to this register starts the VDM context store operation. The function of this task is described in the Rogue Context Switching Hardware Specifiction" hexmask.long 0x0 1.--31. 1. "Reserved_1,Reserved_1" newline bitfld.long 0x0 0. "PULSE,PULSE" "0,1" line.long 0x4 "RGX_CR_VDM_CONTEXT_STORE_START_1,Writing '1' to this register starts the VDM context store operation. The function of this task is described in the Rogue Context Switching Hardware Specifiction" hexmask.long 0x4 0.--31. 1. "Reserved_1,Reserved_1" group.long 0x470++0x7 line.long 0x0 "RGX_CR_VDM_SYNC_PDS_DATA_BASE_0,The base address of the PDS data segment base for all TA state sync program 4GB range. 128-bit granularity The data segment size is always 256 bits The PDS code address for the TA state sync program is always 256 bits on.." hexmask.long 0x0 4.--31. 1. "ADDR,ADDR" newline hexmask.long.byte 0x0 0.--3. 1. "Reserved_0,Reserved_0" line.long 0x4 "RGX_CR_VDM_SYNC_PDS_DATA_BASE_1,The base address of the PDS data segment base for all TA state sync program 4GB range. 128-bit granularity The data segment size is always 256 bits The PDS code address for the TA state sync program is always 256 bits on.." hexmask.long 0x4 0.--31. 1. "Reserved_32,Reserved_32" wgroup.long 0x478++0x7 line.long 0x0 "RGX_CR_CDM_START_0,A write of '1' to this register starts the Compute Data Master reading it's control stream from memory." hexmask.long 0x0 1.--31. 1. "Reserved_1,Reserved_1" newline bitfld.long 0x0 0. "PULSE,Start CDM" "0,1" line.long 0x4 "RGX_CR_CDM_START_1,A write of '1' to this register starts the Compute Data Master reading it's control stream from memory." hexmask.long 0x4 0.--31. 1. "Reserved_1,Reserved_1" group.long 0x480++0x7 line.long 0x0 "RGX_CR_CDM_CTRL_STREAM_BASE_0,The base address of the Compute Data Master's Input Parameter Control Stream in external memory" hexmask.long 0x0 2.--31. 1. "ADDR,1TB range 32-bit aligned base address" newline bitfld.long 0x0 0.--1. "Reserved_0,Reserved_0" "0,1,2,3" line.long 0x4 "RGX_CR_CDM_CTRL_STREAM_BASE_1,The base address of the Compute Data Master's Input Parameter Control Stream in external memory" hexmask.long.tbyte 0x4 8.--31. 1. "Reserved_40,Reserved_40" newline hexmask.long.byte 0x4 0.--7. 1. "ADDR,1TB range 32-bit aligned base address" wgroup.long 0x488++0x7 line.long 0x0 "RGX_CR_CDM_CONTEXT_STORE_0,Writing '1' to this register starts the CDM context store operation." hexmask.long 0x0 1.--31. 1. "Reserved_1,Reserved_1" newline bitfld.long 0x0 0. "PULSE,PULSE" "0,1" line.long 0x4 "RGX_CR_CDM_CONTEXT_STORE_1,Writing '1' to this register starts the CDM context store operation." hexmask.long 0x4 0.--31. 1. "Reserved_1,Reserved_1" group.long 0x490++0xF line.long 0x0 "RGX_CR_CDM_CONTEXT_LOAD_0,The firmware writes a '1' to this register starts the CDM context load operation. The CDM will set this register to '0' when the context load operation is complete The firmware should poll on this register after writing to it" hexmask.long 0x0 1.--31. 1. "Reserved_1,Reserved_1" newline bitfld.long 0x0 0. "PENDING,PENDING" "0,1" line.long 0x4 "RGX_CR_CDM_CONTEXT_LOAD_1,The firmware writes a '1' to this register starts the CDM context load operation. The CDM will set this register to '0' when the context load operation is complete The firmware should poll on this register after writing to it" hexmask.long 0x4 0.--31. 1. "Reserved_1,Reserved_1" line.long 0x8 "RGX_CR_CDM_CONTEXT_STATE_BASE_0,The base address in external memory of the CDM's context state buffer. to which it will store its snapshot state on a context store and from which it will reload on a context resume" hexmask.long 0x8 4.--31. 1. "ADDR,1TB range 128-bit aligned base address" newline hexmask.long.byte 0x8 0.--3. 1. "Reserved_0,Reserved_0" line.long 0xC "RGX_CR_CDM_CONTEXT_STATE_BASE_1,The base address in external memory of the CDM's context state buffer. to which it will store its snapshot state on a context store and from which it will reload on a context resume" hexmask.long.tbyte 0xC 8.--31. 1. "Reserved_40,Reserved_40" newline hexmask.long.byte 0xC 0.--7. 1. "ADDR,1TB range 128-bit aligned base address" rgroup.long 0x4A0++0x7 line.long 0x0 "RGX_CR_CDM_CONTEXT_STORE_STATUS_0,This register indicates the status of a CDM context switch operation. If a context store is in progress. this register must be sampled on a context store compute finished event. The firmware must wait for the COMPLETE.." hexmask.long 0x0 2.--31. 1. "Reserved_2,Reserved_2" newline bitfld.long 0x0 1. "NEED_RESUME,The CDM still has control stream left to process meaning this context must be resumed" "0,1" newline bitfld.long 0x0 0. "COMPLETE,The CDM has completed the context store operation and fenced its state to external memory" "0,1" line.long 0x4 "RGX_CR_CDM_CONTEXT_STORE_STATUS_1,This register indicates the status of a CDM context switch operation. If a context store is in progress. this register must be sampled on a context store compute finished event. The firmware must wait for the COMPLETE.." hexmask.long 0x4 0.--31. 1. "Reserved_2,Reserved_2" repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) group.long ($2+0x4A8)++0x3 line.long 0x0 "RGX_CR_CDM_CONTEXT_PDS0_$1,This register contains the PDS Code and Data Addresses for the Store/Load Program. This program is sent to PDS on Context Store and Context Load." hexmask.long 0x0 4.--31. 1. "CODE_ADDR,PDS Code Address for Store/Load Program 128-bit aligned" newline hexmask.long.byte 0x0 0.--3. 1. "Reserved_0,Reserved_0" repeat.end group.long 0x4B0++0x7 line.long 0x0 "RGX_CR_CDM_CONTEXT_PDS1_0,This register contains the PDS Task Data necessary to produce the Store/Load PDS Program Task from CDM to PDS" bitfld.long 0x0 30.--31. "Reserved_30,Reserved_30" "0,1,2,3" newline bitfld.long 0x0 29. "PDS_SEQ_DEP,PDS Sequential Dependency" "0,1" newline bitfld.long 0x0 28. "USC_SEQ_DEP,USC Sequential Dependency" "0,1" newline bitfld.long 0x0 27. "TARGET,USC Target (0=All 1=Any)" "All,Any)" newline hexmask.long.byte 0x0 21.--26. 1. "UNIFIED_SIZE,Unified Size" newline bitfld.long 0x0 20. "COMMON_SHARED,PDS Common Store Allocation is Shared Registers" "0,1" newline hexmask.long.word 0x0 11.--19. 1. "COMMON_SIZE,PDS Common Size" newline hexmask.long.byte 0x0 7.--10. 1. "TEMP_SIZE,PDS Temp Size" newline hexmask.long.byte 0x0 1.--6. 1. "DATA_SIZE,PDS Data Size" newline bitfld.long 0x0 0. "FENCE,Fence the Task in the PDS/USC - Set on Store unset on Load" "0,1" line.long 0x4 "RGX_CR_CDM_CONTEXT_PDS1_1,This register contains the PDS Task Data necessary to produce the Store/Load PDS Program Task from CDM to PDS" hexmask.long 0x4 0.--31. 1. "Reserved_30,Reserved_30" repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) group.long ($2+0x4B8)++0x3 line.long 0x0 "RGX_CR_CDM_TERMINATE_PDS_$1,This register contains the PDS Code and Data Addresses for the Terminate Program. This program is sent to PDS on Context Store after the Context Store Program" hexmask.long 0x0 4.--31. 1. "CODE_ADDR,PDS Code Address for Terminate Program 128-bit aligned" newline hexmask.long.byte 0x0 0.--3. 1. "Reserved_0,Reserved_0" repeat.end group.long 0x4C0++0x7 line.long 0x0 "RGX_CR_CDM_TERMINATE_PDS1_0,This register contains the PDS Task Data necessary to produce the Context Store Terminate PDS Program Task from CDM to PDS" bitfld.long 0x0 30.--31. "Reserved_30,Reserved_30" "0,1,2,3" newline bitfld.long 0x0 29. "PDS_SEQ_DEP,PDS Sequential Dependency" "0,1" newline bitfld.long 0x0 28. "USC_SEQ_DEP,USC Sequential Dependency" "0,1" newline bitfld.long 0x0 27. "TARGET,USC Target (0=All 1=Any)" "All,Any)" newline hexmask.long.byte 0x0 21.--26. 1. "UNIFIED_SIZE,Unified Size" newline bitfld.long 0x0 20. "COMMON_SHARED,PDS Common Store Allocation is Shared Registers" "0,1" newline hexmask.long.word 0x0 11.--19. 1. "COMMON_SIZE,PDS Common Size" newline hexmask.long.byte 0x0 7.--10. 1. "TEMP_SIZE,PDS Temp Size" newline hexmask.long.byte 0x0 1.--6. 1. "DATA_SIZE,PDS Data Size" newline bitfld.long 0x0 0. "FENCE,Fence the Task in the PDS/USC - Set on Store Terminate" "0,1" line.long 0x4 "RGX_CR_CDM_TERMINATE_PDS1_1,This register contains the PDS Task Data necessary to produce the Context Store Terminate PDS Program Task from CDM to PDS" hexmask.long 0x4 0.--31. 1. "Reserved_30,Reserved_30" repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) group.long ($2+0x4D8)++0x3 line.long 0x0 "RGX_CR_CDM_CONTEXT_LOAD_PDS0_$1,This register contains the PDS Code and Data Addresses for the Store/Load Program. This program is sent to PDS on Context Store and Context Load." hexmask.long 0x0 4.--31. 1. "CODE_ADDR,PDS Code Address for Store/Load Program 128-bit aligned" newline hexmask.long.byte 0x0 0.--3. 1. "Reserved_0,Reserved_0" repeat.end group.long 0x4E0++0x7 line.long 0x0 "RGX_CR_CDM_CONTEXT_LOAD_PDS1_0,This register contains the PDS Task Data necessary to produce the Store/Load PDS Program Task from CDM to PDS" bitfld.long 0x0 30.--31. "Reserved_30,Reserved_30" "0,1,2,3" newline bitfld.long 0x0 29. "PDS_SEQ_DEP,PDS Sequential Dependency" "0,1" newline bitfld.long 0x0 28. "USC_SEQ_DEP,USC Sequential Dependency" "0,1" newline bitfld.long 0x0 27. "TARGET,USC Target (0=All 1=Any)" "All,Any)" newline hexmask.long.byte 0x0 21.--26. 1. "UNIFIED_SIZE,Unified Size" newline bitfld.long 0x0 20. "COMMON_SHARED,PDS Common Store Allocation is Shared Registers" "0,1" newline hexmask.long.word 0x0 11.--19. 1. "COMMON_SIZE,PDS Common Size" newline hexmask.long.byte 0x0 7.--10. 1. "TEMP_SIZE,PDS Temp Size" newline hexmask.long.byte 0x0 1.--6. 1. "DATA_SIZE,PDS Data Size" newline bitfld.long 0x0 0. "FENCE,Fence the Task in the PDS/USC - Set on Store unset on Load" "0,1" line.long 0x4 "RGX_CR_CDM_CONTEXT_LOAD_PDS1_1,This register contains the PDS Task Data necessary to produce the Store/Load PDS Program Task from CDM to PDS" hexmask.long 0x4 0.--31. 1. "Reserved_30,Reserved_30" group.long 0x600++0x7 line.long 0x0 "RGX_CR_PDS_CTRL_0,Controls the maximum number of tasks per data master (per USC). There are a maximum of 48 tasks in the system" hexmask.long.byte 0x0 24.--31. 1. "MAX_NUM_CDM_TASKS,The maximum number of compute tasks allowed on each USC range 0 to 48" newline hexmask.long.byte 0x0 16.--23. 1. "MAX_NUM_PDM_TASKS,The maximum number of pixel tasks allowed on each USC range 0 to 48" newline hexmask.long.byte 0x0 8.--15. 1. "MAX_NUM_VDM_TASKS,The maximum number of vertex tasks (VS HS GS when Tess not enabled) allowed on each USC range 0 to 39 (Note reduced range to prevent Pixel/VDM system deadlock)" newline hexmask.long.byte 0x0 0.--7. 1. "MAX_NUM_TDM_TASKS,The maximum number of fastrender tasks allowed on each USC range 0 to 48" line.long 0x4 "RGX_CR_PDS_CTRL_1,Controls the maximum number of tasks per data master (per USC). There are a maximum of 48 tasks in the system" hexmask.long 0x4 0.--31. 1. "Reserved_32,Reserved_32" wgroup.long 0x608++0x7 line.long 0x0 "RGX_CR_PDS_USC_COLLATOR_0,This register clear the internal resource tracking storage. It must be cleared after reste/power up. A write of '1' to this register clears the PDS Unified Clusters Resource Collator Contents. The PDS USC Resource Collator is a.." hexmask.long 0x0 1.--31. 1. "Reserved_1,Reserved_1" newline bitfld.long 0x0 0. "CLEAR,Clear PDS Unified Clusters Resource Collator" "0,1" line.long 0x4 "RGX_CR_PDS_USC_COLLATOR_1,This register clear the internal resource tracking storage. It must be cleared after reste/power up. A write of '1' to this register clears the PDS Unified Clusters Resource Collator Contents. The PDS USC Resource Collator is a.." hexmask.long 0x4 0.--31. 1. "Reserved_1,Reserved_1" group.long 0x610++0x1F line.long 0x0 "RGX_CR_PDS_EXEC_BASE_0,Base Address in memory where the PDS programs are located" hexmask.long.word 0x0 20.--31. 1. "ADDR,1TB addressable 1 MB aligned base address for PDS programs" newline hexmask.long.tbyte 0x0 0.--19. 1. "Reserved_0,Reserved_0" line.long 0x4 "RGX_CR_PDS_EXEC_BASE_1,Base Address in memory where the PDS programs are located" hexmask.long.tbyte 0x4 8.--31. 1. "Reserved_40,Reserved_40" newline hexmask.long.byte 0x4 0.--7. 1. "ADDR,1TB addressable 1 MB aligned base address for PDS programs" line.long 0x8 "RGX_CR_EVENT_PIXEL_PDS_CODE_0,RGX_CR_EVENT_PIXEL_PDS_CODE_0" hexmask.long 0x8 4.--31. 1. "ADDR,PDS Execution Address for pixel tasks (Positioned as a byte address 128 bit granularity) 4 GB Range" newline hexmask.long.byte 0x8 0.--3. 1. "Reserved_0,Reserved_0" line.long 0xC "RGX_CR_EVENT_PIXEL_PDS_CODE_1,RGX_CR_EVENT_PIXEL_PDS_CODE_1" hexmask.long 0xC 0.--31. 1. "Reserved_32,Reserved_32" line.long 0x10 "RGX_CR_EVENT_PIXEL_PDS_DATA_0,RGX_CR_EVENT_PIXEL_PDS_DATA_0" hexmask.long 0x10 4.--31. 1. "ADDR,PDS Execution Address for pixel tasks (Positioned as a byte address 128 bit granularity) 4 GB Range" newline hexmask.long.byte 0x10 0.--3. 1. "Reserved_0,Reserved_0" line.long 0x14 "RGX_CR_EVENT_PIXEL_PDS_DATA_1,RGX_CR_EVENT_PIXEL_PDS_DATA_1" hexmask.long 0x14 0.--31. 1. "Reserved_32,Reserved_32" line.long 0x18 "RGX_CR_EVENT_PIXEL_PDS_INFO_0,RGX_CR_EVENT_PIXEL_PDS_INFO_0" hexmask.long.tbyte 0x18 15.--31. 1. "Reserved_15,Reserved_15" newline hexmask.long.byte 0x18 9.--14. 1. "USC_SR_SIZE,USC Shared Register Data Size in 4x128 bit words (0=0) for pixel event task if zero pixel event task is skipped" newline hexmask.long.byte 0x18 5.--8. 1. "TEMP_STRIDE,PDS Temp Size in 128 bit words (0=0) for pixel event tasks" newline hexmask.long.byte 0x18 0.--4. 1. "CONST_SIZE,PDS Data Size in 128 bit words (0=0) for pixel event tasks if zero pixel event task is skipped" line.long 0x1C "RGX_CR_EVENT_PIXEL_PDS_INFO_1,RGX_CR_EVENT_PIXEL_PDS_INFO_1" hexmask.long 0x1C 0.--31. 1. "Reserved_15,Reserved_15" wgroup.long 0x630++0x7 line.long 0x0 "RGX_CR_PDS_CSRM_0,A write of '1' to this register clears the PDS Common Store Resource Manager Contents The PDS CSRM is a cross-DM controller. meaning this register must not be written during any active TA. 3D or Compute phase. This register must be.." hexmask.long 0x0 1.--31. 1. "Reserved_1,Reserved_1" newline bitfld.long 0x0 0. "CLEAR,Clear PDS Common Store Resource Manager a write to this register results in a one cycle pulse" "0,1" line.long 0x4 "RGX_CR_PDS_CSRM_1,A write of '1' to this register clears the PDS Common Store Resource Manager Contents The PDS CSRM is a cross-DM controller. meaning this register must not be written during any active TA. 3D or Compute phase. This register must be.." hexmask.long 0x4 0.--31. 1. "Reserved_1,Reserved_1" group.long 0x638++0xF line.long 0x0 "RGX_CR_PDS_MAX_CSRM_CHUNKS_0,Soft Limit Registers for Maximum Allocation Chunks in the Common Store on a Data Master basis. 1024 Allocation Regions exist in the Common Store. Each Allocation Region or Chunk represetns 4x128-bits of space in the Common.." hexmask.long.byte 0x0 27.--31. 1. "Reserved_27,Reserved_27" newline hexmask.long.word 0x0 18.--26. 1. "CDM,Max Number of Allocation Regions to Allocate to the Compute Data Master in Common Store" newline hexmask.long.word 0x0 9.--17. 1. "PDM,Max Number of Allocation Regions to Allocate to the Pixel Data Master in Common Store" newline hexmask.long.word 0x0 0.--8. 1. "VDM,Max Number of Allocation Regions to Allocate to the VDM Data Master in Common Store" line.long 0x4 "RGX_CR_PDS_MAX_CSRM_CHUNKS_1,Soft Limit Registers for Maximum Allocation Chunks in the Common Store on a Data Master basis. 1024 Allocation Regions exist in the Common Store. Each Allocation Region or Chunk represetns 4x128-bits of space in the Common.." hexmask.long 0x4 0.--31. 1. "Reserved_27,Reserved_27" line.long 0x8 "RGX_CR_PDS_CSRM_MAX_COEFF_0,The Common Store contains Coefficients and Shared Registers in a maximum of n Lines of 64 Allocation Chunks numbered 0-19. Allocated Dynamically. This Register sets a Soft Limit for the Maximum Line to Allocate for use as a.." hexmask.long 0x8 6.--31. 1. "Reserved_6,Reserved_6" newline hexmask.long.byte 0x8 1.--5. 1. "LINE,Coefficients are allocated from Line 0 upwards this is the maximum Line to use for Coefficients before wrapping" newline bitfld.long 0x8 0. "LINE_ENABLE,Enable Max Coefficient Line Limit" "0,1" line.long 0xC "RGX_CR_PDS_CSRM_MAX_COEFF_1,The Common Store contains Coefficients and Shared Registers in a maximum of n Lines of 64 Allocation Chunks numbered 0-19. Allocated Dynamically. This Register sets a Soft Limit for the Maximum Line to Allocate for use as a.." hexmask.long 0xC 0.--31. 1. "Reserved_6,Reserved_6" wgroup.long 0x648++0x7 line.long 0x0 "RGX_CR_PDS_USRM_0,A write of '1' to this register clears the PDS Unified Store Resource Manager Contents. The PDS Unified Store Resource Manager only applies to the vertex and compute data masters. This register must be written during the core.." hexmask.long 0x0 1.--31. 1. "Reserved_1,Reserved_1" newline bitfld.long 0x0 0. "CLEAR,Clear PDS Unified Store Resource Manager a write to this register results in a one cycle pulse" "0,1" line.long 0x4 "RGX_CR_PDS_USRM_1,A write of '1' to this register clears the PDS Unified Store Resource Manager Contents. The PDS Unified Store Resource Manager only applies to the vertex and compute data masters. This register must be written during the core.." hexmask.long 0x4 0.--31. 1. "Reserved_1,Reserved_1" group.long 0x650++0xF line.long 0x0 "RGX_CR_PDS_MAX_USRM_CHUNKS_0,Soft Limit Registers for Maximum Allocation Chunks in the Unified Store on a Data Master basis. 400 Allocation Regions exist in the Unified Store. Each Allocation Region represents 4x128-bits of space in the Unified Store." hexmask.long.word 0x0 18.--31. 1. "Reserved_18,Reserved_18" newline hexmask.long.word 0x0 9.--17. 1. "CDM,Max Number of Allocation Regions to Allocate to the Compute Data Master in Unified Store" newline hexmask.long.word 0x0 0.--8. 1. "VDM,Max Number of Allocation Regions to Allocate to the VDM Data Master in Unified Store" line.long 0x4 "RGX_CR_PDS_MAX_USRM_CHUNKS_1,Soft Limit Registers for Maximum Allocation Chunks in the Unified Store on a Data Master basis. 400 Allocation Regions exist in the Unified Store. Each Allocation Region represents 4x128-bits of space in the Unified Store." hexmask.long 0x4 0.--31. 1. "Reserved_18,Reserved_18" line.long 0x8 "RGX_CR_PDS_USRM_MAX_TEMP_0,The Unified Store contains Temporaries and Attributes in n Lines of 16 Allocation Chunks numbered 0- n-1. Allocated Dynamically. This Register sets a Soft Limit for the Maximum Line to Allocate for use as a Temporaries Line.." hexmask.long 0x8 5.--31. 1. "Reserved_5,Reserved_5" newline hexmask.long.byte 0x8 1.--4. 1. "LINE,Max Line for use as Temporaries" newline bitfld.long 0x8 0. "LINE_ENABLE,Enable Max Temporaries Line Limit" "0,1" line.long 0xC "RGX_CR_PDS_USRM_MAX_TEMP_1,The Unified Store contains Temporaries and Attributes in n Lines of 16 Allocation Chunks numbered 0- n-1. Allocated Dynamically. This Register sets a Soft Limit for the Maximum Line to Allocate for use as a Temporaries Line.." hexmask.long 0xC 0.--31. 1. "Reserved_5,Reserved_5" wgroup.long 0x660++0x7 line.long 0x0 "RGX_CR_PDS_UVSRM_0,A write of '1' to this register clears the PDS Unified Vertex Store Resource Manager Contents The UVS Resource Manager only applies to the vertex data master. This register must be written during the core initialisation sequence." hexmask.long 0x0 1.--31. 1. "Reserved_1,Reserved_1" newline bitfld.long 0x0 0. "CLEAR,Clear PDS Unified Vertex Store Resource Manager a write to this register results in a one cycle pulse" "0,1" line.long 0x4 "RGX_CR_PDS_UVSRM_1,A write of '1' to this register clears the PDS Unified Vertex Store Resource Manager Contents The UVS Resource Manager only applies to the vertex data master. This register must be written during the core initialisation sequence." hexmask.long 0x4 0.--31. 1. "Reserved_1,Reserved_1" group.long 0x668++0x7 line.long 0x0 "RGX_CR_MCU_FBTC_ICTRL_0,MCU Framebuffer Tile Cache Invalidate Control" hexmask.long 0x0 4.--31. 1. "Reserved_4,Reserved_4" newline bitfld.long 0x0 3. "COMP_DM,When set to 1 all entries in the tile cache that have been tagged as a compute data master will be invalidate when PENDING is set" "0,1" newline bitfld.long 0x0 2. "VERTEX_DM,When set to 1 all entries in the tile cache that have been tagged as a vertex data master will be invalidate when PENDING is set" "0,1" newline bitfld.long 0x0 1. "PIXEL_DM,When set to 1 all entries in the tile cache that have been tagged as a pixel data master will be invalidate when PENDING is set" "0,1" newline bitfld.long 0x0 0. "PENDING,When written to 1 will invalidate the header cache in the FBDC when read as 1 invalidate is in progress when read as 0 invalidate is complete" "0,1" line.long 0x4 "RGX_CR_MCU_FBTC_ICTRL_1,MCU Framebuffer Tile Cache Invalidate Control" hexmask.long 0x4 0.--31. 1. "Reserved_4,Reserved_4" wgroup.long 0x670++0x7 line.long 0x0 "RGX_CR_PDS_STORERM_0,A write of '1' to this register clears the PDS Store Resource Manager Contents. The PDS Store Resource Manager is a cross-DM controller. meaning this register must not be written during any active TA. 3D or Compute phase. This.." hexmask.long 0x0 1.--31. 1. "Reserved_1,Reserved_1" newline bitfld.long 0x0 0. "CLEAR,Clear PDS Store Resource Manager a write to this register results in a one cycle pulse" "0,1" line.long 0x4 "RGX_CR_PDS_STORERM_1,A write of '1' to this register clears the PDS Store Resource Manager Contents. The PDS Store Resource Manager is a cross-DM controller. meaning this register must not be written during any active TA. 3D or Compute phase. This.." hexmask.long 0x4 0.--31. 1. "Reserved_1,Reserved_1" group.long 0x678++0x27 line.long 0x0 "RGX_CR_PDS_MAX_STORERM_CHUNKS_0,Soft Limit Registers for Maximum Allocation Chunks in the PDS Store on a Data Master basis. 488 Allocation Regions exist in the PDS Store. Each Allocation Chunk/Region represents 8x64-bits of space in the PDS Store." hexmask.long.byte 0x0 27.--31. 1. "STM,Max Number of Allocation Regions to Allocate to the Stream Out Data Master in PDS Store" newline hexmask.long.word 0x0 18.--26. 1. "CDM,Max Number of Allocation Regions to Allocate to the Compute Data Master in PDS Store" newline hexmask.long.word 0x0 9.--17. 1. "PDM,Max Number of Allocation Regions to Allocate to the Pixel Data Master in PDS Store" newline hexmask.long.word 0x0 0.--8. 1. "VDM,Max Number of Allocation Regions to Allocate to the VDM Data Master in PDS Store" line.long 0x4 "RGX_CR_PDS_MAX_STORERM_CHUNKS_1,Soft Limit Registers for Maximum Allocation Chunks in the PDS Store on a Data Master basis. 488 Allocation Regions exist in the PDS Store. Each Allocation Chunk/Region represents 8x64-bits of space in the PDS Store." hexmask.long 0x4 4.--31. 1. "Reserved_36,Reserved_36" newline hexmask.long.byte 0x4 0.--3. 1. "STM,Max Number of Allocation Regions to Allocate to the Stream Out Data Master in PDS Store" line.long 0x8 "RGX_CR_PDS_STORERM_MAX_TEMP_0,The PDS Store Resource Manager contains Temporaries and Constants in 8 Lines of 64 Allocation Chunks each numbered 0-7. Allocated Dynamically. This Register sets a Soft Limit for the Maximum Line to Allocate for use as a.." hexmask.long 0x8 4.--31. 1. "Reserved_4,Reserved_4" newline bitfld.long 0x8 1.--3. "LINE,Temporaries are allocated from Line 0 upwards this is the maximum Line to use for Temporaries before wrapping" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 0. "LINE_ENABLE,Enable Max Temporaries Line Limit" "0,1" line.long 0xC "RGX_CR_PDS_STORERM_MAX_TEMP_1,The PDS Store Resource Manager contains Temporaries and Constants in 8 Lines of 64 Allocation Chunks each numbered 0-7. Allocated Dynamically. This Register sets a Soft Limit for the Maximum Line to Allocate for use as a.." hexmask.long 0xC 0.--31. 1. "Reserved_4,Reserved_4" line.long 0x10 "RGX_CR_PDS_ICC_INVAL_0,A write of '1' any bit to this register clears the PDS Instruction Cache for the selected DM The PDS HW will clear the bits when the operations complete" hexmask.long 0x10 6.--31. 1. "Reserved_6,Reserved_6" newline bitfld.long 0x10 5. "FASTRENDER_PENDING,PDS Instruction Cache Fastrender (DM 6) has been invalidated" "0,1" newline bitfld.long 0x10 3.--4. "Reserved_3,Reserved_3" "0,1,2,3" newline bitfld.long 0x10 2. "COMPUTE_PENDING,PDS Instruction Cache Compute (DM 2) has been invalidated" "0,1" newline bitfld.long 0x10 1. "PIXEL_PENDING,PDS Instruction Cache Pixel (DM 1) has been invalidated" "0,1" newline bitfld.long 0x10 0. "VERTEX_PENDING,PDS Instruction Cache Vertex (DM 0) has been invalidated" "0,1" line.long 0x14 "RGX_CR_PDS_ICC_INVAL_1,A write of '1' any bit to this register clears the PDS Instruction Cache for the selected DM The PDS HW will clear the bits when the operations complete" hexmask.long 0x14 0.--31. 1. "Reserved_6,Reserved_6" line.long 0x18 "RGX_CR_PDS_MCU_REQ_CTRL_0,The PDS makes requests to the MCU to DMA to the PDS store and write data to memory. This register defines the various cache modes that apply to those requests." hexmask.long 0x18 4.--31. 1. "Reserved_4,Reserved_4" newline bitfld.long 0x18 2.--3. "SMODE,SLC cache policy to use for requests from the VDM/PDM/CDM/STM resource requestors inside the PDS" "0,1,2,3" newline bitfld.long 0x18 0.--1. "CMODE,Cache Mode to use for requests from the VDM/PDM/CDM/STM resource requestors inside the PDS" "0,1,2,3" line.long 0x1C "RGX_CR_PDS_MCU_REQ_CTRL_1,The PDS makes requests to the MCU to DMA to the PDS store and write data to memory. This register defines the various cache modes that apply to those requests." hexmask.long 0x1C 0.--31. 1. "Reserved_4,Reserved_4" line.long 0x20 "RGX_CR_PDS_CSRM_MIN_SHARED_0,The Common Store contains Coefficients and Shared Registers in 14 Lines of 64 Allocation Chunks numbered 0-13. Allocated Dynamically. This Register sets a Soft Limit for the Minimum Line to Allocate for use as a Shared Line.." hexmask.long 0x20 6.--31. 1. "Reserved_6,Reserved_6" newline hexmask.long.byte 0x20 1.--5. 1. "LINE,Shared are allocated from top line downwards this is the minimum Line to use for Shared Registers before wrapping" newline bitfld.long 0x20 0. "LINE_ENABLE,Enable Min Shared Register Line Limit" "0,1" line.long 0x24 "RGX_CR_PDS_CSRM_MIN_SHARED_1,The Common Store contains Coefficients and Shared Registers in 14 Lines of 64 Allocation Chunks numbered 0-13. Allocated Dynamically. This Register sets a Soft Limit for the Minimum Line to Allocate for use as a Shared Line.." hexmask.long 0x24 0.--31. 1. "Reserved_6,Reserved_6" repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) group.long ($2+0x6A0)++0x3 line.long 0x0 "RGX_CR_PDS_BGRND0_BASE_$1,PDS Background Setup Word 0" hexmask.long 0x0 4.--31. 1. "SHADER_ADDR,The pixel shader base is the base address of the PDS Data Segment. The code segment is address is PDS_PIXEL_SHADERBASE + PDS_PIXELSHADERSIZE. The pixel shader program issues the DOUTU for the Fragment Shader only." newline hexmask.long.byte 0x0 0.--3. 1. "Reserved_0,Reserved_0" repeat.end repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) group.long ($2+0x6A8)++0x3 line.long 0x0 "RGX_CR_PDS_BGRND1_BASE_$1,PDS Background Setup Word 1" hexmask.long 0x0 4.--31. 1. "VARYING_ADDR,This is the base address of the PDS Data Segment. The code segment is address is PDS_VARYINGBASE + PDS_VARYINGSIZE (PDS_BGRND_SIZEINFO1)." newline hexmask.long.byte 0x0 0.--3. 1. "Reserved_0,Reserved_0" repeat.end group.long 0x6B0++0x37 line.long 0x0 "RGX_CR_PDS_BGRND2_BASE_0,PDS Background Setup Word 2" hexmask.long 0x0 4.--31. 1. "UNIFORMDATA_ADDR,This points to the DMAs to load the Uniforms (or contains the Uniforms with DOUTW commands)" newline hexmask.long.byte 0x0 0.--3. 1. "Reserved_0,Reserved_0" line.long 0x4 "RGX_CR_PDS_BGRND2_BASE_1,PDS Background Setup Word 2" hexmask.long 0x4 0.--31. 1. "Reserved_32,Reserved_32" line.long 0x8 "RGX_CR_PDS_BGRND3_SIZEINFO_0,If any of the size fields are 0. then that program will not be run. PDS_BGRND_PIXELSHADERSIZE is always 2 128 Bit Words" hexmask.long.word 0x8 23.--31. 1. "PDS_UNIFORMSIZE,The size of the Uniform PDS Data Segment in 128 bit words" newline hexmask.long.byte 0x8 16.--22. 1. "PDS_TEXTURESTATESIZE,The size of the Texture PDS Data Segment in 128 bit words" newline hexmask.long.byte 0x8 10.--15. 1. "PDS_VARYINGSIZE,The size of the Varying/Coefficient PDS Data Segment in 128 bit words" newline hexmask.long.byte 0x8 4.--9. 1. "USC_VARYINGSIZE,The size of the Varying/Coefficient USC Common Store Data in 4x128 bit words" newline hexmask.long.byte 0x8 0.--3. 1. "PDS_TEMPSIZE,0 = 0 128 bit words 1 = 1 128 bit word this applies to coefficient uniform and varying state" line.long 0xC "RGX_CR_PDS_BGRND3_SIZEINFO_1,If any of the size fields are 0. then that program will not be run. PDS_BGRND_PIXELSHADERSIZE is always 2 128 Bit Words" hexmask.long.word 0xC 23.--31. 1. "USC_SHAREDSIZE,The common store allocation size for the shared registers (texture and uniform data commbined)" newline hexmask.long.word 0xC 14.--22. 1. "Reserved_46,Reserved_46" newline hexmask.long.word 0xC 0.--13. 1. "PDS_BATCHNUM,The batch ID to be associated with the background" line.long 0x10 "RGX_CR_PDS_USRM_MIN_ATTR_0,The Unified Store contains Temporaries and Attributes in n Lines of 16 Allocation Chunks numbered 0 - n-1. Allocated Dynamically. This Register sets a Soft Limit for the Minimum Line to Allocate for use as an Attribute Line.." hexmask.long 0x10 5.--31. 1. "Reserved_5,Reserved_5" newline hexmask.long.byte 0x10 1.--4. 1. "LINE,Min Line for use for Attributes" newline bitfld.long 0x10 0. "LINE_ENABLE,Enable Min Attributes Line Limit" "0,1" line.long 0x14 "RGX_CR_PDS_USRM_MIN_ATTR_1,The Unified Store contains Temporaries and Attributes in n Lines of 16 Allocation Chunks numbered 0 - n-1. Allocated Dynamically. This Register sets a Soft Limit for the Minimum Line to Allocate for use as an Attribute Line.." hexmask.long 0x14 0.--31. 1. "Reserved_5,Reserved_5" line.long 0x18 "RGX_CR_PDS_STORERM_MIN_CONST_0,The PDS Store Resource Manager contains Temporaries and Constants in 8 Lines of 64 Allocation Chunks each numbered 0-7. Allocated Dynamically. This Register sets a Soft Limit for the Minimum Line to Allocate for use as a.." hexmask.long 0x18 4.--31. 1. "Reserved_4,Reserved_4" newline bitfld.long 0x18 1.--3. "LINE,Constants are allocated from Line 7 down this is the minimum Line to use for Constants before wrapping" "0,1,2,3,4,5,6,7" newline bitfld.long 0x18 0. "LINE_ENABLE,Enable Min Constants Line Limit" "0,1" line.long 0x1C "RGX_CR_PDS_STORERM_MIN_CONST_1,The PDS Store Resource Manager contains Temporaries and Constants in 8 Lines of 64 Allocation Chunks each numbered 0-7. Allocated Dynamically. This Register sets a Soft Limit for the Minimum Line to Allocate for use as a.." hexmask.long 0x1C 0.--31. 1. "Reserved_4,Reserved_4" line.long 0x20 "RGX_CR_PDS_PIXELMERGE_0,RGX_CR_PDS_PIXELMERGE_0" hexmask.long 0x20 7.--31. 1. "Reserved_7,Reserved_7" newline bitfld.long 0x20 6. "TASK_DISABLE,Disable pixel merging within a whole pixel fragment task" "0,1" newline bitfld.long 0x20 5. "DISABLE,Disable pixel merging within each 2x2 pixel block of a pixel fragment task" "0,1" newline hexmask.long.byte 0x20 0.--4. 1. "GRADLIMIT,Gradient difference limit for PDS PP pixel merging" line.long 0x24 "RGX_CR_PDS_PIXELMERGE_1,RGX_CR_PDS_PIXELMERGE_1" hexmask.long 0x24 0.--31. 1. "Reserved_7,Reserved_7" line.long 0x28 "RGX_CR_PDS_CSRM_USC_DEBUG_0,When written a non zero value. this register assigns an extra degree of space to be allocated in the Common Store via the PDS CSRM for USC debugging on Shared Allocations. The SIZE field is Allocation Region Granular (i.e.." hexmask.long 0x28 5.--31. 1. "Reserved_5,Reserved_5" newline hexmask.long.byte 0x28 0.--4. 1. "SIZE,Amount of Space (in 512-bit Allocation Regions) to allocate to USC Debug Space on a Shared Allocation." line.long 0x2C "RGX_CR_PDS_CSRM_USC_DEBUG_1,When written a non zero value. this register assigns an extra degree of space to be allocated in the Common Store via the PDS CSRM for USC debugging on Shared Allocations. The SIZE field is Allocation Region Granular (i.e.." hexmask.long 0x2C 0.--31. 1. "Reserved_5,Reserved_5" line.long 0x30 "RGX_CR_PDS_CSRM_DISABLE_0,When this register is set. the CSRM will be configured on PDS CSRM CLEAR to not reserve any space for Partitions (this is normally governed by the AA MODE and PIXEL OUTPUT CTRL WIDTH register settings). to maximise space in the.." hexmask.long 0x30 3.--31. 1. "Reserved_3,Reserved_3" newline bitfld.long 0x30 2. "COEFF_SLIDE,Disable Slide of Coeff Allocations on Failure" "0,1" newline bitfld.long 0x30 1. "SHARED_SLIDE,Disable Slide of Shared Allocations on Failure" "0,1" newline bitfld.long 0x30 0. "PARTITIONS,Disable Partition Space Reservation in the CSRM" "0,1" line.long 0x34 "RGX_CR_PDS_CSRM_DISABLE_1,When this register is set. the CSRM will be configured on PDS CSRM CLEAR to not reserve any space for Partitions (this is normally governed by the AA MODE and PIXEL OUTPUT CTRL WIDTH register settings). to maximise space in the.." hexmask.long 0x34 0.--31. 1. "Reserved_3,Reserved_3" rgroup.long 0x6E8++0x7 line.long 0x0 "RGX_CR_HUB_IDLE_0,RGX_CR_HUB_IDLE_0" hexmask.long 0x0 4.--31. 1. "Reserved_4,Reserved_4" newline bitfld.long 0x0 3. "TDM,TDM Module IDLE" "0,1" newline bitfld.long 0x0 2. "CDM,CDM Module IDLE" "0,1" newline bitfld.long 0x0 1. "VDM,VDM Module IDLE" "0,1" newline bitfld.long 0x0 0. "PDS,PDS Module IDLE" "0,1" line.long 0x4 "RGX_CR_HUB_IDLE_1,RGX_CR_HUB_IDLE_1" hexmask.long 0x4 0.--31. 1. "Reserved_4,Reserved_4" repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) rgroup.long ($2+0x6F0)++0x3 line.long 0x0 "RGX_CR_HUB_PWR_$1,RGX_CR_HUB_PWR_0" hexmask.long 0x0 0.--31. 1. "NUM_PDS_INST,Number of PDS instructions" repeat.end group.long 0x700++0xF line.long 0x0 "RGX_CR_PDS_PASSGROUP_0,RGX_CR_PDS_PASSGROUP_0" hexmask.long 0x0 2.--31. 1. "Reserved_2,Reserved_2" newline bitfld.long 0x0 1. "FORCE_PT,Force the use of Hard SDs between punchthrough or depth feedback type passes" "0,1" newline bitfld.long 0x0 0. "ENABLE,Enable pass group optimisation within USC by replacing USC Hard SDs with USC Soft SDs for all pass groups in the PDS PP." "0,1" line.long 0x4 "RGX_CR_PDS_PASSGROUP_1,RGX_CR_PDS_PASSGROUP_1" hexmask.long 0x4 0.--31. 1. "Reserved_2,Reserved_2" line.long 0x8 "RGX_CR_PDS_COMPUTE_THREAD_BARRIER_0,RGX_CR_PDS_COMPUTE_THREAD_BARRIER_0" hexmask.long 0x8 1.--31. 1. "Reserved_1,Reserved_1" newline bitfld.long 0x8 0. "ENABLE,Enable thread barrier support in the PDS CDM_RR." "0,1" line.long 0xC "RGX_CR_PDS_COMPUTE_THREAD_BARRIER_1,RGX_CR_PDS_COMPUTE_THREAD_BARRIER_1" hexmask.long 0xC 0.--31. 1. "Reserved_1,Reserved_1" group.long 0x720++0x7 line.long 0x0 "RGX_CR_PDS_CSRM_SETUP_0,If the ENABLE field is set. then when the PDS CSRM is Cleared via the PDS_CSRM_CLEAR register. the value set in the MAX_LINE vector is used to define the maximum Line in the CSRM which is allocatable to Shared.." hexmask.long 0x0 6.--31. 1. "Reserved_6,Reserved_6" newline bitfld.long 0x0 5. "HALF,Top line is prefilled half full" "0,1" newline hexmask.long.byte 0x0 1.--4. 1. "MAX_LINE,(Lower 4 bits of) Maximum Line within the CSRM that can be allocated to Shared Registers/Coefficients" newline bitfld.long 0x0 0. "ENABLE,Enable use of this register to set the Maximum Line the CSRM can allocate on behalf of the USC Common Store" "0,1" line.long 0x4 "RGX_CR_PDS_CSRM_SETUP_1,If the ENABLE field is set. then when the PDS CSRM is Cleared via the PDS_CSRM_CLEAR register. the value set in the MAX_LINE vector is used to define the maximum Line in the CSRM which is allocatable to Shared.." hexmask.long 0x4 0.--31. 1. "Reserved_6,Reserved_6" group.long 0x738++0x7 line.long 0x0 "RGX_CR_PDS_USRM_DISABLE_0,When this register is set. the USRM will be configured on PDS USRM CLEAR to disable the Temp/Attribute slide functionality which allows a Temporaries or Attributes allocation which fails to slide the allocation window. The.." hexmask.long 0x0 1.--31. 1. "Reserved_1,Reserved_1" newline bitfld.long 0x0 0. "TEMP_SLIDE,Disable Slide of Temp Allocations on Failure" "0,1" line.long 0x4 "RGX_CR_PDS_USRM_DISABLE_1,When this register is set. the USRM will be configured on PDS USRM CLEAR to disable the Temp/Attribute slide functionality which allows a Temporaries or Attributes allocation which fails to slide the allocation window. The.." hexmask.long 0x4 0.--31. 1. "Reserved_1,Reserved_1" group.long 0x788++0xF line.long 0x0 "RGX_CR_PDS_CSRM_PIXEL_0,The Common Store contains Coefficients and Shared Registers in a maximum of n Lines of 64 Allocation Chunks numbered 0-31. Allocated Dynamically. This Register sets a Soft Limit for the Maximum Line of available Coefficient space." hexmask.long 0x0 6.--31. 1. "Reserved_6,Reserved_6" newline hexmask.long.byte 0x0 1.--5. 1. "MAX_LINE,Coefficients are allocated from Line 0 upwards this is the maximum Line to reserve for ONLY PDM Coefficients. The Max line of this region is set in the PDS_CSRM_MAX_COEFF register" newline bitfld.long 0x0 0. "MODE_ENABLE,Enable PIXEL RESERVE MODE in the PDS CSRM" "0,1" line.long 0x4 "RGX_CR_PDS_CSRM_PIXEL_1,The Common Store contains Coefficients and Shared Registers in a maximum of n Lines of 64 Allocation Chunks numbered 0-31. Allocated Dynamically. This Register sets a Soft Limit for the Maximum Line of available Coefficient space." hexmask.long 0x4 0.--31. 1. "Reserved_6,Reserved_6" line.long 0x8 "RGX_CR_PDS_MAX_STORERM_CHUNKS2_0,Soft Limit Registers for Maximum Allocation Chunks in the PDS Store on a Data Master basis. 488 Allocation Regions exist in the PDS Store. Each Allocation Chunk/Region represents 8x64-bits of space in the PDS Store." hexmask.long.tbyte 0x8 9.--31. 1. "Reserved_9,Reserved_9" newline hexmask.long.word 0x8 0.--8. 1. "TDM,Max Number of Allocation Regions to Allocate to the Fastrender Data Master in PDS Store" line.long 0xC "RGX_CR_PDS_MAX_STORERM_CHUNKS2_1,Soft Limit Registers for Maximum Allocation Chunks in the PDS Store on a Data Master basis. 488 Allocation Regions exist in the PDS Store. Each Allocation Chunk/Region represents 8x64-bits of space in the PDS Store." hexmask.long 0xC 0.--31. 1. "Reserved_9,Reserved_9" group.long 0x800++0x67 line.long 0x0 "RGX_CR_SIDEKICK_EXT_MEM_ARB_CONFIG_0,This register contains the configuration options for the Sidekick external memory arbiter." hexmask.long 0x0 2.--31. 1. "Reserved_2,Reserved_2" newline bitfld.long 0x0 0.--1. "ARB_PRIO_MODE,Priority mode for external memory access arbiter between GPU scheduler and SLC" "0,1,2,3" line.long 0x4 "RGX_CR_SIDEKICK_EXT_MEM_ARB_CONFIG_1,This register contains the configuration options for the Sidekick external memory arbiter." hexmask.long 0x4 0.--31. 1. "Reserved_2,Reserved_2" line.long 0x8 "RGX_CR_MIPS_WRAPPER_FENCE_0,When writing to this register. the MIPS wrapper holds further transaction from MIPS and emits a memory fence onto the bus" hexmask.long 0x8 1.--31. 1. "Reserved_1,Reserved_1" newline bitfld.long 0x8 0. "SYS_FENCE_ID,reserved address identifier for system fence events" "0,1" line.long 0xC "RGX_CR_MIPS_WRAPPER_FENCE_1,When writing to this register. the MIPS wrapper holds further transaction from MIPS and emits a memory fence onto the bus" hexmask.long 0xC 0.--31. 1. "Reserved_1,Reserved_1" line.long 0x10 "RGX_CR_MIPS_WRAPPER_CONFIG_0,This register contains the configuration options for the MIPS CPU wrapper." hexmask.long.byte 0x10 28.--31. 1. "Reserved_28,Reserved_28" newline bitfld.long 0x10 25.--27. "OS_ID,The default OS_ID of the firmware" "0,1,2,3,4,5,6,7" newline bitfld.long 0x10 24. "TRUSTED,Defines whether these accesses are trusted" "0,1" newline hexmask.long.byte 0x10 17.--23. 1. "Reserved_17,Reserved_17" newline bitfld.long 0x10 16. "BOOT_ISA_MODE,MIPS boot up mode. When set to 0 boot from MIPS32 mode or set to 1 to boot in microMIPS mode" "0,1" newline hexmask.long.word 0x10 0.--15. 1. "REGBANK_BASE_ADDR,16-bit aligned address that identifies rgx register bank transactions emitted from the MIPS core" line.long 0x14 "RGX_CR_MIPS_WRAPPER_CONFIG_1,This register contains the configuration options for the MIPS CPU wrapper." hexmask.long.tbyte 0x14 9.--31. 1. "Reserved_41,Reserved_41" newline bitfld.long 0x14 8. "FW_IDLE_ENABLE,Set to 0x0 overwrites the value of GPU_IDLE to 0x0 set to 0x1 makes GPU Idle dependent on top level idles" "0,1" newline hexmask.long.byte 0x14 2.--7. 1. "Reserved_34,Reserved_34" newline bitfld.long 0x14 1. "DISABLE_BOOT,Stop the MIPS from boot-up even after a soft reset is triggered" "0,1" newline bitfld.long 0x14 0. "L2_CACHE_OFF,Turn off the L2 cache within the MIPS wrapper" "0,1" line.long 0x18 "RGX_CR_MIPS_ADDR_REMAP1_CONFIG1_0,This register contains the address remapping options for the MIPS CPU physical address. e.g. during boot" hexmask.long.tbyte 0x18 12.--31. 1. "BASE_ADDR_IN,4K (12 bits) aligned address used as a input for the address remapping" newline hexmask.long.word 0x18 1.--11. 1. "Reserved_1,Reserved_1" newline bitfld.long 0x18 0. "MODE_ENABLE,Enable address remapping mode" "0,1" line.long 0x1C "RGX_CR_MIPS_ADDR_REMAP1_CONFIG1_1,This register contains the address remapping options for the MIPS CPU physical address. e.g. during boot" hexmask.long 0x1C 0.--31. 1. "Reserved_32,Reserved_32" line.long 0x20 "RGX_CR_MIPS_ADDR_REMAP1_CONFIG2_0,This register contains the address remapping options for the MIPS CPU physical address. e.g. during boot" hexmask.long.tbyte 0x20 12.--31. 1. "ADDR_OUT,4K (12 bits) aligned address used as output for the address remapping" newline bitfld.long 0x20 9.--11. "Reserved_9,Reserved_9" "0,1,2,3,4,5,6,7" newline bitfld.long 0x20 6.--8. "OS_ID,The OS_ID emitted for all address transactions from this region" "0,1,2,3,4,5,6,7" newline bitfld.long 0x20 5. "TRUSTED,Defines whether these accesses are trusted" "0,1" newline hexmask.long.byte 0x20 0.--4. 1. "REGION_SIZE_POW2,Remapped region size or offset size i.e. number of bits from the bottom of the base input address that survive onto the output address. Minimum value of 12" line.long 0x24 "RGX_CR_MIPS_ADDR_REMAP1_CONFIG2_1,This register contains the address remapping options for the MIPS CPU physical address. e.g. during boot" hexmask.long.tbyte 0x24 8.--31. 1. "Reserved_40,Reserved_40" newline hexmask.long.byte 0x24 0.--7. 1. "ADDR_OUT,4K (12 bits) aligned address used as output for the address remapping" line.long 0x28 "RGX_CR_MIPS_ADDR_REMAP2_CONFIG1_0,This register contains the address remapping options for the MIPS CPU physical address. e.g. during boot" hexmask.long.tbyte 0x28 12.--31. 1. "BASE_ADDR_IN,4K (12 bits) aligned address used as a input for the address remapping" newline hexmask.long.word 0x28 1.--11. 1. "Reserved_1,Reserved_1" newline bitfld.long 0x28 0. "MODE_ENABLE,Enable address remapping mode" "0,1" line.long 0x2C "RGX_CR_MIPS_ADDR_REMAP2_CONFIG1_1,This register contains the address remapping options for the MIPS CPU physical address. e.g. during boot" hexmask.long 0x2C 0.--31. 1. "Reserved_32,Reserved_32" line.long 0x30 "RGX_CR_MIPS_ADDR_REMAP2_CONFIG2_0,This register contains the address remapping options for the MIPS CPU physical address. e.g. during boot" hexmask.long.tbyte 0x30 12.--31. 1. "ADDR_OUT,4K (12 bits) aligned address used as output for the address remapping" newline bitfld.long 0x30 9.--11. "Reserved_9,Reserved_9" "0,1,2,3,4,5,6,7" newline bitfld.long 0x30 6.--8. "OS_ID,The OS_ID emitted for all address transactions from this region" "0,1,2,3,4,5,6,7" newline bitfld.long 0x30 5. "TRUSTED,Defines whether these accesses are trusted" "0,1" newline hexmask.long.byte 0x30 0.--4. 1. "REGION_SIZE_POW2,Remapped region size or offset size i.e. number of bits from the bottom of the base input address that survive onto the output address. Minimum value of 12" line.long 0x34 "RGX_CR_MIPS_ADDR_REMAP2_CONFIG2_1,This register contains the address remapping options for the MIPS CPU physical address. e.g. during boot" hexmask.long.tbyte 0x34 8.--31. 1. "Reserved_40,Reserved_40" newline hexmask.long.byte 0x34 0.--7. 1. "ADDR_OUT,4K (12 bits) aligned address used as output for the address remapping" line.long 0x38 "RGX_CR_MIPS_ADDR_REMAP3_CONFIG1_0,This register contains the address remapping options for the MIPS CPU physical address. e.g. during boot" hexmask.long.tbyte 0x38 12.--31. 1. "BASE_ADDR_IN,4K (12 bits) aligned address used as a input for the address remapping" newline hexmask.long.word 0x38 1.--11. 1. "Reserved_1,Reserved_1" newline bitfld.long 0x38 0. "MODE_ENABLE,Enable address remapping mode" "0,1" line.long 0x3C "RGX_CR_MIPS_ADDR_REMAP3_CONFIG1_1,This register contains the address remapping options for the MIPS CPU physical address. e.g. during boot" hexmask.long 0x3C 0.--31. 1. "Reserved_32,Reserved_32" line.long 0x40 "RGX_CR_MIPS_ADDR_REMAP3_CONFIG2_0,This register contains the address remapping options for the MIPS CPU physical address. e.g. during boot" hexmask.long.tbyte 0x40 12.--31. 1. "ADDR_OUT,4K (12 bits) aligned address used as output for the address remapping" newline bitfld.long 0x40 9.--11. "Reserved_9,Reserved_9" "0,1,2,3,4,5,6,7" newline bitfld.long 0x40 6.--8. "OS_ID,The OS_ID emitted for all address transactions from this region" "0,1,2,3,4,5,6,7" newline bitfld.long 0x40 5. "TRUSTED,Defines whether these accesses are trusted" "0,1" newline hexmask.long.byte 0x40 0.--4. 1. "REGION_SIZE_POW2,Remapped region size or offset size i.e. number of bits from the bottom of the base input address that survive onto the output address. Minimum value of 12" line.long 0x44 "RGX_CR_MIPS_ADDR_REMAP3_CONFIG2_1,This register contains the address remapping options for the MIPS CPU physical address. e.g. during boot" hexmask.long.tbyte 0x44 8.--31. 1. "Reserved_40,Reserved_40" newline hexmask.long.byte 0x44 0.--7. 1. "ADDR_OUT,4K (12 bits) aligned address used as output for the address remapping" line.long 0x48 "RGX_CR_MIPS_ADDR_REMAP4_CONFIG1_0,This register contains the address remapping options for the MIPS CPU physical address. e.g. during boot" hexmask.long.tbyte 0x48 12.--31. 1. "BASE_ADDR_IN,4K (12 bits) aligned address used as a input for the address remapping" newline hexmask.long.word 0x48 1.--11. 1. "Reserved_1,Reserved_1" newline bitfld.long 0x48 0. "MODE_ENABLE,Enable address remapping mode" "0,1" line.long 0x4C "RGX_CR_MIPS_ADDR_REMAP4_CONFIG1_1,This register contains the address remapping options for the MIPS CPU physical address. e.g. during boot" hexmask.long 0x4C 0.--31. 1. "Reserved_32,Reserved_32" line.long 0x50 "RGX_CR_MIPS_ADDR_REMAP4_CONFIG2_0,This register contains the address remapping options for the MIPS CPU physical address. e.g. during boot" hexmask.long.tbyte 0x50 12.--31. 1. "ADDR_OUT,4K (12 bits) aligned address used as output for the address remapping" newline bitfld.long 0x50 9.--11. "Reserved_9,Reserved_9" "0,1,2,3,4,5,6,7" newline bitfld.long 0x50 6.--8. "OS_ID,The OS_ID emitted for all address transactions from this region" "0,1,2,3,4,5,6,7" newline bitfld.long 0x50 5. "TRUSTED,Defines whether these accesses are trusted" "0,1" newline hexmask.long.byte 0x50 0.--4. 1. "REGION_SIZE_POW2,Remapped region size or offset size i.e. number of bits from the bottom of the base input address that survive onto the output address. Minimum value of 12" line.long 0x54 "RGX_CR_MIPS_ADDR_REMAP4_CONFIG2_1,This register contains the address remapping options for the MIPS CPU physical address. e.g. during boot" hexmask.long.tbyte 0x54 8.--31. 1. "Reserved_40,Reserved_40" newline hexmask.long.byte 0x54 0.--7. 1. "ADDR_OUT,4K (12 bits) aligned address used as output for the address remapping" line.long 0x58 "RGX_CR_MIPS_ADDR_REMAP5_CONFIG1_0,This register contains the address remapping options for the MIPS CPU physical address. e.g. during boot" hexmask.long.tbyte 0x58 12.--31. 1. "BASE_ADDR_IN,4K (12 bits) aligned address used as a input for the address remapping" newline hexmask.long.word 0x58 1.--11. 1. "Reserved_1,Reserved_1" newline bitfld.long 0x58 0. "MODE_ENABLE,Enable address remapping mode" "0,1" line.long 0x5C "RGX_CR_MIPS_ADDR_REMAP5_CONFIG1_1,This register contains the address remapping options for the MIPS CPU physical address. e.g. during boot" hexmask.long 0x5C 0.--31. 1. "Reserved_32,Reserved_32" line.long 0x60 "RGX_CR_MIPS_ADDR_REMAP5_CONFIG2_0,This register contains the address remapping options for the MIPS CPU physical address. e.g. during boot" hexmask.long.tbyte 0x60 12.--31. 1. "ADDR_OUT,4K (12 bits) aligned address used as output for the address remapping" newline bitfld.long 0x60 9.--11. "Reserved_9,Reserved_9" "0,1,2,3,4,5,6,7" newline bitfld.long 0x60 6.--8. "OS_ID,The OS_ID emitted for all address transactions from this region" "0,1,2,3,4,5,6,7" newline bitfld.long 0x60 5. "TRUSTED,Defines whether these accesses are trusted" "0,1" newline hexmask.long.byte 0x60 0.--4. 1. "REGION_SIZE_POW2,Remapped region size or offset size i.e. number of bits from the bottom of the base input address that survive onto the output address. Minimum value of 12" line.long 0x64 "RGX_CR_MIPS_ADDR_REMAP5_CONFIG2_1,This register contains the address remapping options for the MIPS CPU physical address. e.g. during boot" hexmask.long.tbyte 0x64 8.--31. 1. "Reserved_40,Reserved_40" newline hexmask.long.byte 0x64 0.--7. 1. "ADDR_OUT,4K (12 bits) aligned address used as output for the address remapping" rgroup.long 0x868++0x7 line.long 0x0 "RGX_CR_MIPS_ADDR_REMAP_UNMAPPED_STATUS_0,This register contains the unmapped exception status information of the MIPS GPU scheduler." hexmask.long 0x0 0.--31. 1. "ADDRESS,Unmapped MIPS physical address" line.long 0x4 "RGX_CR_MIPS_ADDR_REMAP_UNMAPPED_STATUS_1,This register contains the unmapped exception status information of the MIPS GPU scheduler." hexmask.long 0x4 1.--31. 1. "Reserved_33,Reserved_33" newline bitfld.long 0x4 0. "EVENT,An address from the MIPS was not remapped to a new range in the GPU" "0,1" wgroup.long 0x870++0x7 line.long 0x0 "RGX_CR_MIPS_ADDR_REMAP_UNMAPPED_CLEAR_0,This register contains the configuration options for the MIPS unmapped exception." hexmask.long 0x0 1.--31. 1. "Reserved_1,Reserved_1" newline bitfld.long 0x0 0. "EVENT,Clears the unmapped exception event" "0,1" line.long 0x4 "RGX_CR_MIPS_ADDR_REMAP_UNMAPPED_CLEAR_1,This register contains the configuration options for the MIPS unmapped exception." hexmask.long 0x4 0.--31. 1. "Reserved_1,Reserved_1" group.long 0x878++0x7 line.long 0x0 "RGX_CR_MIPS_ADDR_REMAP_RANGE_CONFIG_0,This register contains the address remapping options for the MIPS CPU physical address. e.g. during boot" hexmask.long.tbyte 0x0 12.--31. 1. "BASE_ADDR_IN,4K (12 bits) aligned address used as a input for the address remapping" newline bitfld.long 0x0 11. "TRUSTED,Defines whether these accesses are trusted" "0,1" newline hexmask.long.byte 0x0 7.--10. 1. "REGION_SIZE,Remapped region size" newline bitfld.long 0x0 6. "Reserved_6,Reserved_6" "0,1" newline hexmask.long.byte 0x0 1.--5. 1. "ENTRY,Select remap entry to configure. Valid range of Entry 0-31" newline bitfld.long 0x0 0. "MODE_ENABLE,When set configure the entry" "0,1" line.long 0x4 "RGX_CR_MIPS_ADDR_REMAP_RANGE_CONFIG_1,This register contains the address remapping options for the MIPS CPU physical address. e.g. during boot" hexmask.long 0x4 4.--31. 1. "ADDR_OUT,4K (12 bits) aligned address used as output for the address remapping" newline bitfld.long 0x4 3. "Reserved_35,Reserved_35" "0,1" newline bitfld.long 0x4 0.--2. "OS_ID,The OS_ID emitted for all address transactions from this region" "0,1,2,3,4,5,6,7" wgroup.long 0x880++0x7 line.long 0x0 "RGX_CR_MIPS_ADDR_REMAP_RANGE_READ_0,This register contains the configuration options for the MIPS remap register read interface." hexmask.long 0x0 6.--31. 1. "Reserved_6,Reserved_6" newline hexmask.long.byte 0x0 1.--5. 1. "ENTRY,MIPS address remap entry to read" newline bitfld.long 0x0 0. "REQUEST,Issue a read request to the MIPS address remap range entries" "0,1" line.long 0x4 "RGX_CR_MIPS_ADDR_REMAP_RANGE_READ_1,This register contains the configuration options for the MIPS remap register read interface." hexmask.long 0x4 0.--31. 1. "Reserved_6,Reserved_6" rgroup.long 0x888++0x7 line.long 0x0 "RGX_CR_MIPS_ADDR_REMAP_RANGE_DATA_0,This register contains the remapping entry information for the MIPS remap register read interface." hexmask.long.tbyte 0x0 12.--31. 1. "BASE_ADDR_IN,4K (12 bits) aligned address used as a input for the address remapping" newline bitfld.long 0x0 11. "TRUSTED,Defines whether these accesses are trusted" "0,1" newline hexmask.long.byte 0x0 7.--10. 1. "REGION_SIZE,Remapped region size" newline hexmask.long.byte 0x0 1.--6. 1. "Reserved_1,Reserved_1" newline bitfld.long 0x0 0. "MODE_ENABLE,When set configures the entry" "0,1" line.long 0x4 "RGX_CR_MIPS_ADDR_REMAP_RANGE_DATA_1,This register contains the remapping entry information for the MIPS remap register read interface." hexmask.long 0x4 4.--31. 1. "ADDR_OUT,4K (12 bits) aligned address used as output for the address remapping" newline bitfld.long 0x4 3. "Reserved_35,Reserved_35" "0,1" newline bitfld.long 0x4 0.--2. "OS_ID,The OS_ID emitted for all address transactions from this region" "0,1,2,3,4,5,6,7" group.long 0x8A0++0xF line.long 0x0 "RGX_CR_MIPS_WRAPPER_IRQ_ENABLE_0,This register contains the configuration options for the RGX firmware interrupts to HOST." hexmask.long 0x0 1.--31. 1. "Reserved_1,Reserved_1" newline bitfld.long 0x0 0. "EVENT,Allow RGX firmware to send interrupts to HOST" "0,1" line.long 0x4 "RGX_CR_MIPS_WRAPPER_IRQ_ENABLE_1,This register contains the configuration options for the RGX firmware interrupts to HOST." hexmask.long 0x4 0.--31. 1. "Reserved_1,Reserved_1" line.long 0x8 "RGX_CR_MIPS_WRAPPER_IRQ_STATUS_0,This register contains the configuration options for the RGX firmware interrupts to HOST." hexmask.long 0x8 1.--31. 1. "Reserved_1,Reserved_1" newline bitfld.long 0x8 0. "EVENT,Indicates an outstanding interrupt to HOST from RGX firmware" "0,1" line.long 0xC "RGX_CR_MIPS_WRAPPER_IRQ_STATUS_1,This register contains the configuration options for the RGX firmware interrupts to HOST." hexmask.long 0xC 0.--31. 1. "Reserved_1,Reserved_1" wgroup.long 0x8B0++0x7 line.long 0x0 "RGX_CR_MIPS_WRAPPER_IRQ_CLEAR_0,This register contains the configuration options for the RGX firmware interrupts to HOST." hexmask.long 0x0 1.--31. 1. "Reserved_1,Reserved_1" newline bitfld.long 0x0 0. "EVENT,Clears the interrupt event to HOST from RGX firmware" "0,1" line.long 0x4 "RGX_CR_MIPS_WRAPPER_IRQ_CLEAR_1,This register contains the configuration options for the RGX firmware interrupts to HOST." hexmask.long 0x4 0.--31. 1. "Reserved_1,Reserved_1" group.long 0x8B8++0x7 line.long 0x0 "RGX_CR_MIPS_WRAPPER_NMI_ENABLE_0,This register contains the configuration options for the RGX firmware non-maskable interrupts to MIPS." hexmask.long 0x0 1.--31. 1. "Reserved_1,Reserved_1" newline bitfld.long 0x0 0. "EVENT,Allow RGX firmware to send non-maskable interrupts to MIPS" "0,1" line.long 0x4 "RGX_CR_MIPS_WRAPPER_NMI_ENABLE_1,This register contains the configuration options for the RGX firmware non-maskable interrupts to MIPS." hexmask.long 0x4 0.--31. 1. "Reserved_1,Reserved_1" wgroup.long 0x8C0++0x7 line.long 0x0 "RGX_CR_MIPS_WRAPPER_NMI_EVENT_0,This register contains the configuration options for the RGX firmware non-maskable interrupts to MIPS." hexmask.long 0x0 1.--31. 1. "Reserved_1,Reserved_1" newline bitfld.long 0x0 0. "TRIGGER,Issue a non-maskable interrupt to the MIPS SI_NMI pin from RGX firmware" "0,1" line.long 0x4 "RGX_CR_MIPS_WRAPPER_NMI_EVENT_1,This register contains the configuration options for the RGX firmware non-maskable interrupts to MIPS." hexmask.long 0x4 0.--31. 1. "Reserved_1,Reserved_1" group.long 0x8C8++0x7 line.long 0x0 "RGX_CR_MIPS_DEBUG_CONFIG_0,This register contains the security and debug configuration options for the MIPS GPU scheduler." hexmask.long 0x0 1.--31. 1. "Reserved_1,Reserved_1" newline bitfld.long 0x0 0. "DISABLE_PROBE_DEBUG,Enable MIPS SecureDebug. Disables EJTAG access to the MIPS core and PC Sampling" "0,1" line.long 0x4 "RGX_CR_MIPS_DEBUG_CONFIG_1,This register contains the security and debug configuration options for the MIPS GPU scheduler." hexmask.long 0x4 0.--31. 1. "Reserved_1,Reserved_1" rgroup.long 0x8D0++0x7 line.long 0x0 "RGX_CR_MIPS_EXCEPTION_STATUS_0,This register contains the exception status information of the MIPS GPU scheduler." hexmask.long 0x0 6.--31. 1. "Reserved_6,Reserved_6" newline bitfld.long 0x0 5. "SI_SLEEP,Reflects the status of the MIPS SI_Sleep pin" "0,1" newline bitfld.long 0x0 4. "SI_NMI_TAKEN,Reflects the status of the MIPS SI_NMITaken pin" "0,1" newline bitfld.long 0x0 3. "SI_NEST_EXL,Reflects the status of the MIPS SI_NESTEXL pin" "0,1" newline bitfld.long 0x0 2. "SI_NEST_ERL,Reflects the status of the MIPS SI_NESTERL pin" "0,1" newline bitfld.long 0x0 1. "SI_EXL,Reflects the status of the MIPS SI_EXL pin" "0,1" newline bitfld.long 0x0 0. "SI_ERL,Reflects the status of the MIPS SI_ERL pin" "0,1" line.long 0x4 "RGX_CR_MIPS_EXCEPTION_STATUS_1,This register contains the exception status information of the MIPS GPU scheduler." hexmask.long 0x4 0.--31. 1. "Reserved_6,Reserved_6" group.long 0x8D8++0xF line.long 0x0 "RGX_CR_MIPS_WRAPPER_FENCE_CONFIG_0,This register contains the fence configuration options for when MIPS emits a memory fence onto the bus" hexmask.long.tbyte 0x0 12.--31. 1. "BASE_ADDR,4K (12 bits) aligned address that serves as the external memory fence base address" newline hexmask.long.byte 0x0 4.--11. 1. "Reserved_4,Reserved_4" newline bitfld.long 0x0 1.--3. "OS_ID,OS_ID of the emitted fence" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 0. "TRUSTED,Defines whether these accesses are trusted" "0,1" line.long 0x4 "RGX_CR_MIPS_WRAPPER_FENCE_CONFIG_1,This register contains the fence configuration options for when MIPS emits a memory fence onto the bus" hexmask.long.tbyte 0x4 8.--31. 1. "Reserved_40,Reserved_40" newline hexmask.long.byte 0x4 0.--7. 1. "BASE_ADDR,4K (12 bits) aligned address that serves as the external memory fence base address" line.long 0x8 "RGX_CR_MIPS_WRAPPER_CACHE_INVAL_0,A write of '1' to this register invalidates the MIPS wrapper L2 cache The cache hardware will clear this bit when the invalidation operation completes" hexmask.long 0x8 1.--31. 1. "Reserved_1,Reserved_1" newline bitfld.long 0x8 0. "PENDING,MIPS wrapper L2 cache is being invalidated" "0,1" line.long 0xC "RGX_CR_MIPS_WRAPPER_CACHE_INVAL_1,A write of '1' to this register invalidates the MIPS wrapper L2 cache The cache hardware will clear this bit when the invalidation operation completes" hexmask.long 0xC 0.--31. 1. "Reserved_1,Reserved_1" rgroup.long 0x8E8++0x7 line.long 0x0 "RGX_CR_MIPS_WRAPPER_STATUS_0,This register contains status information of the MIPS GPU scheduler." hexmask.long.tbyte 0x0 8.--31. 1. "Reserved_8,Reserved_8" newline hexmask.long.byte 0x0 0.--7. 1. "OUTSTANDING_REQUESTS,Outstanding requests by the MIPS" line.long 0x4 "RGX_CR_MIPS_WRAPPER_STATUS_1,This register contains status information of the MIPS GPU scheduler." hexmask.long 0x4 0.--31. 1. "Reserved_8,Reserved_8" group.long 0x900++0x17 line.long 0x0 "RGX_CR_EVENT_TDM_PDS_CODE_0,PDS code segment address for 2D End-of-Tile event shader." hexmask.long 0x0 4.--31. 1. "ADDR,PDS Execution Address for pixel tasks (Positioned as a byte address 128 bit granularity) 4 GB Range" newline hexmask.long.byte 0x0 0.--3. 1. "Reserved_0,Reserved_0" line.long 0x4 "RGX_CR_EVENT_TDM_PDS_CODE_1,PDS code segment address for 2D End-of-Tile event shader." hexmask.long 0x4 0.--31. 1. "Reserved_32,Reserved_32" line.long 0x8 "RGX_CR_EVENT_TDM_PDS_DATA_0,RGX_CR_EVENT_TDM_PDS_DATA_0" hexmask.long 0x8 4.--31. 1. "ADDR,PDS Execution Address for pixel tasks (Positioned as a byte address 128 bit granularity) 4 GB Range" newline hexmask.long.byte 0x8 0.--3. 1. "Reserved_0,Reserved_0" line.long 0xC "RGX_CR_EVENT_TDM_PDS_DATA_1,RGX_CR_EVENT_TDM_PDS_DATA_1" hexmask.long 0xC 0.--31. 1. "Reserved_32,Reserved_32" line.long 0x10 "RGX_CR_EVENT_TDM_PDS_INFO_0,RGX_CR_EVENT_TDM_PDS_INFO_0" hexmask.long.word 0x10 16.--31. 1. "Reserved_16,Reserved_16" newline hexmask.long.byte 0x10 10.--15. 1. "USC_SR_SIZE,USC Shared Register Data Size in 4x128 bit words (0=0) for pixel event task if zero pixel event task is skipped" newline hexmask.long.byte 0x10 5.--9. 1. "TEMP_STRIDE,PDS Temp Size in 64 bit words (0=0) for pixel event tasks" newline hexmask.long.byte 0x10 0.--4. 1. "CONST_SIZE,PDS Data Size in 128 bit words (0=0) for pixel event tasks if zero pixel event task is skipped" line.long 0x14 "RGX_CR_EVENT_TDM_PDS_INFO_1,RGX_CR_EVENT_TDM_PDS_INFO_1" hexmask.long 0x14 0.--31. 1. "Reserved_16,Reserved_16" repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) group.long ($2+0x918)++0x3 line.long 0x0 "RGX_CR_PDS_TDM_BGRND0_BASE_$1,PDS Background Setup Word 0" hexmask.long 0x0 4.--31. 1. "SHADER_ADDR,The pixel shader base is the base address of the PDS Data Segment. The code segment is address is PDS_PIXEL_SHADERBASE + PDS_PIXELSHADERSIZE. The pixel shader program issues the DOUTU for the Fragment Shader only." newline hexmask.long.byte 0x0 0.--3. 1. "Reserved_0,Reserved_0" repeat.end repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) group.long ($2+0x920)++0x3 line.long 0x0 "RGX_CR_PDS_TDM_BGRND1_BASE_$1,PDS Background Setup Word 1" hexmask.long 0x0 4.--31. 1. "VARYING_ADDR,This is the base address of the PDS Data Segment. The code segment is address is PDS_VARYINGBASE + PDS_VARYINGSIZE (PDS_BGRND_SIZEINFO1)." newline hexmask.long.byte 0x0 0.--3. 1. "Reserved_0,Reserved_0" repeat.end group.long 0x928++0xF line.long 0x0 "RGX_CR_PDS_TDM_BGRND2_BASE_0,PDS Background Setup Word 2" hexmask.long 0x0 4.--31. 1. "UNIFORMDATA_ADDR,This points to the DMAs to load the Uniforms (or contains the Uniforms with DOUTW commands)" newline hexmask.long.byte 0x0 0.--3. 1. "Reserved_0,Reserved_0" line.long 0x4 "RGX_CR_PDS_TDM_BGRND2_BASE_1,PDS Background Setup Word 2" hexmask.long 0x4 0.--31. 1. "Reserved_32,Reserved_32" line.long 0x8 "RGX_CR_PDS_TDM_BGRND3_SIZEINFO_0,If any of the size fields are 0. then that program will not be run. PDS_BGRND_PIXELSHADERSIZE is always 2 128 Bit Words" hexmask.long.byte 0x8 27.--31. 1. "PDS_BATCHNUM,The batch ID to be associated with the background" newline hexmask.long.byte 0x8 21.--26. 1. "PDS_UNIFORMSIZE,The size of the Uniform PDS Data Segment in 128 bit words 0=0. 32 max" newline hexmask.long.byte 0x8 15.--20. 1. "PDS_TEXTURESTATESIZE,The size of the Texture PDS Data Segment in 128 bit words 0=0 32 max" newline hexmask.long.byte 0x8 9.--14. 1. "PDS_VARYINGSIZE,The size of the Varying/Coefficient PDS Data Segment in 128 bit words 0=0 32 max" newline hexmask.long.word 0x8 0.--8. 1. "USC_VARYINGSIZE,The size of the Varying/Coefficient USC Common Store Data in 4x128 bit words 0=0. 256 max" line.long 0xC "RGX_CR_PDS_TDM_BGRND3_SIZEINFO_1,If any of the size fields are 0. then that program will not be run. PDS_BGRND_PIXELSHADERSIZE is always 2 128 Bit Words" hexmask.long.word 0xC 23.--31. 1. "Reserved_55,Reserved_55" newline hexmask.long.word 0xC 14.--22. 1. "USC_SHAREDSIZE,The common store allocation size for the shared registers (texture and uniform data commbined) 256 chunks max" newline hexmask.long.byte 0xC 9.--13. 1. "PDS_TEMPSIZE,0 = 0 64 bit words 1 = 1 64 bit word 248 bytes. This applies to coefficient uniform and texture state updates." newline hexmask.long.word 0xC 0.--8. 1. "PDS_BATCHNUM,The batch ID to be associated with the background" group.long 0xB00++0xF line.long 0x0 "RGX_CR_MTS_SCHEDULE_0,This register allows firmware tasks to be scheduled on the META (Garten) core." hexmask.long.tbyte 0x0 9.--31. 1. "Reserved_9,Reserved_9" newline bitfld.long 0x0 8. "HOST,Host Interrupte kick" "0,1" newline bitfld.long 0x0 6.--7. "PRIORITY,DataMaster Priority" "0,1,2,3" newline bitfld.long 0x0 5. "CONTEXT,CONTEXT" "0,1" newline bitfld.long 0x0 4. "TASK,TASK" "0,1" newline hexmask.long.byte 0x0 0.--3. 1. "DM,DataMaster Type" line.long 0x4 "RGX_CR_MTS_SCHEDULE_1,This register allows firmware tasks to be scheduled on the META (Garten) core." hexmask.long 0x4 0.--31. 1. "Reserved_9,Reserved_9" line.long 0x8 "RGX_CR_MTS_PROC_COMPLETE_0,This register allows firmware tasks to signal process completion." hexmask.long 0x8 2.--31. 1. "Reserved_2,Reserved_2" newline bitfld.long 0x8 1. "CONTEXT,CONTEXT" "0,1" newline bitfld.long 0x8 0. "THREAD,Thread number. This is filled in by hardware and can have any value" "0,1" line.long 0xC "RGX_CR_MTS_PROC_COMPLETE_1,This register allows firmware tasks to signal process completion." hexmask.long 0xC 0.--31. 1. "Reserved_2,Reserved_2" rgroup.long 0xB10++0x1F line.long 0x0 "RGX_CR_MTS_BGCTX_SBDATA0_0,This register contains the sideband data for the process running on the background context of thread 0. Reads of this register will be redirected to the correct. thread specific register by hardware." hexmask.long.tbyte 0x0 9.--31. 1. "Reserved_9,Reserved_9" newline bitfld.long 0x0 6.--8. "OS_ID,The OS_ID of the active thread" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 5. "THREAD_ACTIVE,Indicates the thread is active" "0,1" newline bitfld.long 0x0 4. "TASK,TASK" "0,1" newline hexmask.long.byte 0x0 0.--3. 1. "DM,DataMaster Type" line.long 0x4 "RGX_CR_MTS_BGCTX_SBDATA0_1,This register contains the sideband data for the process running on the background context of thread 0. Reads of this register will be redirected to the correct. thread specific register by hardware." hexmask.long 0x4 0.--31. 1. "Reserved_9,Reserved_9" line.long 0x8 "RGX_CR_MTS_BGCTX_SBDATA1_0,This register contains the sideband data for the process running on the background context of thread 1. Reads of this register will be redirected to the correct. thread specific register by hardware." hexmask.long.tbyte 0x8 9.--31. 1. "Reserved_9,Reserved_9" newline bitfld.long 0x8 6.--8. "OS_ID,The OS_ID of the active thread" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 5. "THREAD_ACTIVE,Indicates the thread is active" "0,1" newline bitfld.long 0x8 4. "TASK,TASK" "0,1" newline hexmask.long.byte 0x8 0.--3. 1. "DM,DataMaster Type" line.long 0xC "RGX_CR_MTS_BGCTX_SBDATA1_1,This register contains the sideband data for the process running on the background context of thread 1. Reads of this register will be redirected to the correct. thread specific register by hardware." hexmask.long 0xC 0.--31. 1. "Reserved_9,Reserved_9" line.long 0x10 "RGX_CR_MTS_INTCTX_SBDATA0_0,This register contains the sideband data for the process running on the interrupt context of thread 0. Reads of this register will be redirected to the correct. thread specific register by hardware." hexmask.long 0x10 6.--31. 1. "INT_STATUS,Interrupt Status for 32 event bus lines" newline hexmask.long.byte 0x10 2.--5. 1. "DM,DataMaster Type" newline bitfld.long 0x10 0.--1. "INT_TASK,Kick Request for timer/BG-request/host" "0,1,2,3" line.long 0x14 "RGX_CR_MTS_INTCTX_SBDATA0_1,This register contains the sideband data for the process running on the interrupt context of thread 0. Reads of this register will be redirected to the correct. thread specific register by hardware." hexmask.long.tbyte 0x14 10.--31. 1. "Reserved_42,Reserved_42" newline bitfld.long 0x14 7.--9. "OS_ID,The OS_ID of the active thread" "0,1,2,3,4,5,6,7" newline bitfld.long 0x14 6. "THREAD_ACTIVE,Indicates the thread is active" "0,1" newline hexmask.long.byte 0x14 0.--5. 1. "INT_STATUS,Interrupt Status for 32 event bus lines" line.long 0x18 "RGX_CR_MTS_INTCTX_SBDATA1_0,This register contains the sideband data for the process running on the interrupt context of thread 1. Reads of this register will be redirected to the correct. thread specific register by hardware." hexmask.long 0x18 6.--31. 1. "INT_STATUS,Interrupt Status for 32 event bus lines" newline hexmask.long.byte 0x18 2.--5. 1. "DM,DataMaster Type" newline bitfld.long 0x18 0.--1. "INT_TASK,Kick Request for timer/BG-request/host" "0,1,2,3" line.long 0x1C "RGX_CR_MTS_INTCTX_SBDATA1_1,This register contains the sideband data for the process running on the interrupt context of thread 1. Reads of this register will be redirected to the correct. thread specific register by hardware." hexmask.long.tbyte 0x1C 10.--31. 1. "Reserved_42,Reserved_42" newline bitfld.long 0x1C 7.--9. "OS_ID,The OS_ID of the active thread" "0,1,2,3,4,5,6,7" newline bitfld.long 0x1C 6. "THREAD_ACTIVE,Indicates the thread is active" "0,1" newline hexmask.long.byte 0x1C 0.--5. 1. "INT_STATUS,Interrupt Status for 32 event bus lines" group.long 0xB30++0x27 line.long 0x0 "RGX_CR_MTS_BGCTX_THREAD0_DM_ASSOC_0,This register is the DataMaster assocation for the background context of thread 0. Bit high represents DataMaster being permitted to run on the background context of thread 0." hexmask.long.word 0x0 16.--31. 1. "Reserved_16,Reserved_16" newline hexmask.long.word 0x0 0.--15. 1. "DM_ASSOC,DataMaster Association (Active High)" line.long 0x4 "RGX_CR_MTS_BGCTX_THREAD0_DM_ASSOC_1,This register is the DataMaster assocation for the background context of thread 0. Bit high represents DataMaster being permitted to run on the background context of thread 0." hexmask.long 0x4 0.--31. 1. "Reserved_16,Reserved_16" line.long 0x8 "RGX_CR_MTS_BGCTX_THREAD1_DM_ASSOC_0,This register is the DataMaster assocation for the background context of thread 1. Bit high represents DataMaster being permitted to run on the background context of thread 1." hexmask.long.word 0x8 16.--31. 1. "Reserved_16,Reserved_16" newline hexmask.long.word 0x8 0.--15. 1. "DM_ASSOC,DataMaster Association (Active High)" line.long 0xC "RGX_CR_MTS_BGCTX_THREAD1_DM_ASSOC_1,This register is the DataMaster assocation for the background context of thread 1. Bit high represents DataMaster being permitted to run on the background context of thread 1." hexmask.long 0xC 0.--31. 1. "Reserved_16,Reserved_16" line.long 0x10 "RGX_CR_MTS_INTCTX_THREAD0_DM_ASSOC_0,This register is the DataMaster assocation for the interrupt context of thread 0. Bit high represents DataMaster being permitted to run on the interrupt context of thread 0." hexmask.long.word 0x10 16.--31. 1. "Reserved_16,Reserved_16" newline hexmask.long.word 0x10 0.--15. 1. "DM_ASSOC,DataMaster Association (Active High)" line.long 0x14 "RGX_CR_MTS_INTCTX_THREAD0_DM_ASSOC_1,This register is the DataMaster assocation for the interrupt context of thread 0. Bit high represents DataMaster being permitted to run on the interrupt context of thread 0." hexmask.long 0x14 0.--31. 1. "Reserved_16,Reserved_16" line.long 0x18 "RGX_CR_MTS_INTCTX_THREAD1_DM_ASSOC_0,This register is the DataMaster assocation for the interrupt context of thread 1. Bit high represents DataMaster being permitted to run on the interrupt context of thread 1." hexmask.long.word 0x18 16.--31. 1. "Reserved_16,Reserved_16" newline hexmask.long.word 0x18 0.--15. 1. "DM_ASSOC,DataMaster Association (Active High)" line.long 0x1C "RGX_CR_MTS_INTCTX_THREAD1_DM_ASSOC_1,This register is the DataMaster assocation for the interrupt context of thread 1. Bit high represents DataMaster being permitted to run on the interrupt context of thread 1." hexmask.long 0x1C 0.--31. 1. "Reserved_16,Reserved_16" line.long 0x20 "RGX_CR_MTS_GARTEN_WRAPPER_CONFIG_0,This register contains the configuration options for the Garten wrapper." hexmask.long.tbyte 0x20 12.--31. 1. "FENCE_ADDR,4k page address to be used for fence requests" newline hexmask.long.word 0x20 1.--11. 1. "Reserved_1,Reserved_1" newline bitfld.long 0x20 0. "IDLE_CTRL,IDLE_CTRL" "0,1" line.long 0x24 "RGX_CR_MTS_GARTEN_WRAPPER_CONFIG_1,This register contains the configuration options for the Garten wrapper." hexmask.long.word 0x24 16.--31. 1. "Reserved_48,Reserved_48" newline hexmask.long.byte 0x24 12.--15. 1. "FENCE_PC_BASE,Page Catalogue base address number to be used for fence requests" newline hexmask.long.byte 0x24 8.--11. 1. "FENCE_DM,Data master value to be used for fence requests" newline hexmask.long.byte 0x24 0.--7. 1. "FENCE_ADDR,4k page address to be used for fence requests" repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) group.long ($2+0xB58)++0x3 line.long 0x0 "RGX_CR_MTS_DM0_INTERRUPT_ENABLE_$1,Interrupt enable status register for DataMaster 0" hexmask.long 0x0 0.--31. 1. "INT_ENABLE,Interrupt Enable" repeat.end repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) group.long ($2+0xB60)++0x3 line.long 0x0 "RGX_CR_MTS_DM1_INTERRUPT_ENABLE_$1,Interrupt enable status register for DataMaster 1" hexmask.long 0x0 0.--31. 1. "INT_ENABLE,Interrupt Enable" repeat.end repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) group.long ($2+0xB68)++0x3 line.long 0x0 "RGX_CR_MTS_DM2_INTERRUPT_ENABLE_$1,Interrupt enable status register for DataMaster 2" hexmask.long 0x0 0.--31. 1. "INT_ENABLE,Interrupt Enable" repeat.end repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) group.long ($2+0xB70)++0x3 line.long 0x0 "RGX_CR_MTS_DM3_INTERRUPT_ENABLE_$1,Interrupt enable status register for DataMaster 3" hexmask.long 0x0 0.--31. 1. "INT_ENABLE,Interrupt Enable" repeat.end repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) group.long ($2+0xB78)++0x3 line.long 0x0 "RGX_CR_MTS_DM4_INTERRUPT_ENABLE_$1,Interrupt enable status register for DataMaster 4" hexmask.long 0x0 0.--31. 1. "INT_ENABLE,Interrupt Enable" repeat.end repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) group.long ($2+0xB80)++0x3 line.long 0x0 "RGX_CR_MTS_DM5_INTERRUPT_ENABLE_$1,Interrupt enable status register for DataMaster 5" hexmask.long 0x0 0.--31. 1. "INT_ENABLE,Interrupt Enable" repeat.end repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) group.long ($2+0xB88)++0x3 line.long 0x0 "RGX_CR_MTS_EVENT_MASK_$1,Mask interrupt events" hexmask.long 0x0 0.--31. 1. "MASK,DESCRIPTION" repeat.end repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) wgroup.long ($2+0xB90)++0x3 line.long 0x0 "RGX_CR_MTS_EVENT_CLEAR_$1,Clear internal interrupt registers" hexmask.long 0x0 0.--31. 1. "CLEAR,DESCRIPTION" repeat.end rgroup.long 0xB98++0x17 line.long 0x0 "RGX_CR_MTS_INTCTX_0,This register contains the sideband data for the MTS internal interrupt context registers" bitfld.long 0x0 30.--31. "Reserved_30,Reserved_30" "0,1,2,3" newline hexmask.long.byte 0x0 22.--29. 1. "DM_HOST_SCHEDULE,A 1 bit counter per DM for host requests" newline hexmask.long.byte 0x0 16.--21. 1. "Reserved_16,Reserved_16" newline hexmask.long.byte 0x0 8.--15. 1. "DM_TIMER_SCHEDULE,A 1 bit counter per DM for timer requests" newline hexmask.long.byte 0x0 0.--7. 1. "DM_INTERRUPT_SCHEDULE,A 1 bit counter per DM for interrupt requests" line.long 0x4 "RGX_CR_MTS_INTCTX_1,This register contains the sideband data for the MTS internal interrupt context registers" hexmask.long 0x4 0.--31. 1. "Reserved_30,Reserved_30" line.long 0x8 "RGX_CR_MTS_BGCTX_0,This register contains the sideband data for the MTS internal background context registers" hexmask.long.tbyte 0x8 8.--31. 1. "Reserved_8,Reserved_8" newline hexmask.long.byte 0x8 0.--7. 1. "DM_NONCOUNTED_SCHEDULE,A 1 bit counter per DM for non-counted background request" line.long 0xC "RGX_CR_MTS_BGCTX_1,This register contains the sideband data for the MTS internal background context registers" hexmask.long 0xC 0.--31. 1. "Reserved_8,Reserved_8" line.long 0x10 "RGX_CR_MTS_BGCTX_COUNTED_SCHEDULE_0,This register contains the sideband data for the MTS internal counted background context counters" hexmask.long.byte 0x10 24.--31. 1. "DM3,A 8 bit counter for DM3" newline hexmask.long.byte 0x10 16.--23. 1. "DM2,A 8 bit counter for DM2" newline hexmask.long.byte 0x10 8.--15. 1. "DM1,A 8 bit counter for DM1" newline hexmask.long.byte 0x10 0.--7. 1. "DM0,A 8 bit counter for DM0" line.long 0x14 "RGX_CR_MTS_BGCTX_COUNTED_SCHEDULE_1,This register contains the sideband data for the MTS internal counted background context counters" hexmask.long.word 0x14 16.--31. 1. "Reserved_48,Reserved_48" newline hexmask.long.byte 0x14 8.--15. 1. "DM5,A 8 bit counter for DM5" newline hexmask.long.byte 0x14 0.--7. 1. "DM4,A 8 bit counter for DM4" repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) rgroup.long ($2+0xBB0)++0x3 line.long 0x0 "RGX_CR_MTS_GPU_INT_STATUS_$1,This register contains the sideband data for the MTS internal GPU interrupt status" hexmask.long 0x0 0.--31. 1. "STATUS,A 32 bit register for recored GPU events" repeat.end group.long 0xBC0++0xF line.long 0x0 "RGX_CR_MTS_OS_PRIORITY_0,Operating System Priority" hexmask.long.word 0x0 16.--31. 1. "Reserved_16,Reserved_16" newline bitfld.long 0x0 14.--15. "ID7,Scheduling priority for operating system 7" "0,1,2,3" newline bitfld.long 0x0 12.--13. "ID6,Scheduling priority for operating system 6" "0,1,2,3" newline bitfld.long 0x0 10.--11. "ID5,Scheduling priority for operating system 5" "0,1,2,3" newline bitfld.long 0x0 8.--9. "ID4,Scheduling priority for operating system 4" "0,1,2,3" newline bitfld.long 0x0 6.--7. "ID3,Scheduling priority for operating system 3" "0,1,2,3" newline bitfld.long 0x0 4.--5. "ID2,Scheduling priority for operating system 2" "0,1,2,3" newline bitfld.long 0x0 2.--3. "ID1,Scheduling priority for operating system 1" "0,1,2,3" newline bitfld.long 0x0 0.--1. "ID0,Scheduling priority for operating system 0" "0,1,2,3" line.long 0x4 "RGX_CR_MTS_OS_PRIORITY_1,Operating System Priority" hexmask.long 0x4 0.--31. 1. "Reserved_16,Reserved_16" line.long 0x8 "RGX_CR_MTS_SCHEDULE_ENABLE_0,This register is an active-high mask. When the bit is 0. the MTS_SCHEDULE kick from the corresponding Guest OS is silently discarded. This allows the FW to mask out a Guest OS in order to prevent denial-of-service style.." hexmask.long.tbyte 0x8 8.--31. 1. "Reserved_8,Reserved_8" newline hexmask.long.byte 0x8 0.--7. 1. "MASK,MASK" line.long 0xC "RGX_CR_MTS_SCHEDULE_ENABLE_1,This register is an active-high mask. When the bit is 0. the MTS_SCHEDULE kick from the corresponding Guest OS is silently discarded. This allows the FW to mask out a Guest OS in order to prevent denial-of-service style.." hexmask.long 0xC 0.--31. 1. "Reserved_8,Reserved_8" rgroup.long 0xBD8++0x7 line.long 0x0 "RGX_CR_IRQ_OS0_EVENT_STATUS_0,This register indicates the source of a per-OS host interrupt. This register is set by the firmware and cleared by the host." hexmask.long 0x0 1.--31. 1. "Reserved_1,Reserved_1" newline bitfld.long 0x0 0. "SOURCE,SOURCE" "0,1" line.long 0x4 "RGX_CR_IRQ_OS0_EVENT_STATUS_1,This register indicates the source of a per-OS host interrupt. This register is set by the firmware and cleared by the host." hexmask.long 0x4 0.--31. 1. "Reserved_1,Reserved_1" group.long 0xBE0++0xF line.long 0x0 "RGX_CR_HOST_IRQ_0,This register triggers a per-OS host interrupt. The hardware sets the corresponding RGX_CR_IRQ_OS_EVENT_STATUS register." hexmask.long 0x0 3.--31. 1. "Reserved_3,Reserved_3" newline bitfld.long 0x0 0.--2. "OSID,Indicates the Guest OS for the interrupt" "0,1,2,3,4,5,6,7" line.long 0x4 "RGX_CR_HOST_IRQ_1,This register triggers a per-OS host interrupt. The hardware sets the corresponding RGX_CR_IRQ_OS_EVENT_STATUS register." hexmask.long 0x4 0.--31. 1. "Reserved_3,Reserved_3" line.long 0x8 "RGX_CR_IRQ_OS0_EVENT_CLEAR_0,This register clears a per-OS host interrupt." hexmask.long 0x8 1.--31. 1. "Reserved_1,Reserved_1" newline bitfld.long 0x8 0. "SOURCE,SOURCE" "0,1" line.long 0xC "RGX_CR_IRQ_OS0_EVENT_CLEAR_1,This register clears a per-OS host interrupt." hexmask.long 0xC 0.--31. 1. "Reserved_1,Reserved_1" group.long 0xBF8++0x5F line.long 0x0 "RGX_CR_META_BOOT_0,RGX_CR_META_BOOT_0" hexmask.long 0x0 1.--31. 1. "Reserved_1,Reserved_1" newline bitfld.long 0x0 0. "MODE,0 = Don't boot 1 = Boot" "Don't boot,Boot" line.long 0x4 "RGX_CR_META_BOOT_1,RGX_CR_META_BOOT_1" hexmask.long 0x4 0.--31. 1. "Reserved_1,Reserved_1" line.long 0x8 "RGX_CR_TE_AA_0,This register controls the anti-aliasing mode of the Tiling Co-Processor. independent control is provided in both X & Y axis. 2xmsaa is achieved by enabling X2 - does not affect TE 4xmsaa is achieved by enabling Y and X2 - TE does AA on Y.." hexmask.long 0x8 3.--31. 1. "Reserved_3,Reserved_3" newline bitfld.long 0x8 2. "Y,Anti-Aliasing in Y Plane Enabled" "0,1" newline bitfld.long 0x8 1. "X,Anti-Aliasing in X Plane Enabled" "0,1" newline bitfld.long 0x8 0. "X2,2x Anti-Aliasing Enabled affects PPP only" "0,1" line.long 0xC "RGX_CR_TE_AA_1,This register controls the anti-aliasing mode of the Tiling Co-Processor. independent control is provided in both X & Y axis. 2xmsaa is achieved by enabling X2 - does not affect TE 4xmsaa is achieved by enabling Y and X2 - TE does AA on Y.." hexmask.long 0xC 0.--31. 1. "Reserved_3,Reserved_3" line.long 0x10 "RGX_CR_TE_MTILE1_0,MacroTile Boundaries X Plane" hexmask.long.byte 0x10 27.--31. 1. "Reserved_27,Reserved_27" newline hexmask.long.word 0x10 18.--26. 1. "X1,X1 MacroTile boundary left tile X for second column of macrotiles (16MT mode) - 32 pixels across tile" newline hexmask.long.word 0x10 9.--17. 1. "X2,X2 MacroTile boundary left tile X for third(16MT) column of macrotiles - 32 pixels across tile" newline hexmask.long.word 0x10 0.--8. 1. "X3,X3 MacroTile boundary left tile X for fourth column of macrotiles (16MT) - 32 pixels across tile" line.long 0x14 "RGX_CR_TE_MTILE1_1,MacroTile Boundaries X Plane" hexmask.long 0x14 0.--31. 1. "Reserved_27,Reserved_27" line.long 0x18 "RGX_CR_TE_MTILE2_0,MacroTile Boundaries Y Plane." hexmask.long.byte 0x18 27.--31. 1. "Reserved_27,Reserved_27" newline hexmask.long.word 0x18 18.--26. 1. "Y1,X1 MacroTile boundary ltop tile Y for second column of macrotiles (16MT mode) - 32 pixels tile height" newline hexmask.long.word 0x18 9.--17. 1. "Y2,X2 MacroTile boundary top tile Y for third(16MT) column of macrotiles - 32 pixels tile height" newline hexmask.long.word 0x18 0.--8. 1. "Y3,X3 MacroTile boundary top tile Y for fourth column of macrotiles (16MT) - 32 pixels tile height" line.long 0x1C "RGX_CR_TE_MTILE2_1,MacroTile Boundaries Y Plane." hexmask.long 0x1C 0.--31. 1. "Reserved_27,Reserved_27" line.long 0x20 "RGX_CR_TE_SCREEN_0,In order to perform the tiling operation and generate the display list the maximum screen size must be configured in terms of the number of tiles in X & Y axis." hexmask.long.word 0x20 21.--31. 1. "Reserved_21,Reserved_21" newline hexmask.long.word 0x20 12.--20. 1. "YMAX,Maximum Y tile address visible on screen 32 pixel tile height 16Kx16K max screen size" newline bitfld.long 0x20 9.--11. "Reserved_9,Reserved_9" "0,1,2,3,4,5,6,7" newline hexmask.long.word 0x20 0.--8. 1. "XMAX,Maximum X tile address visible on screen 32 pixel tile width 16Kx16K max screen size" line.long 0x24 "RGX_CR_TE_SCREEN_1,In order to perform the tiling operation and generate the display list the maximum screen size must be configured in terms of the number of tiles in X & Y axis." hexmask.long 0x24 0.--31. 1. "Reserved_21,Reserved_21" line.long 0x28 "RGX_CR_TE_MTILE_0,In order to perform the tiling operation and generate the display list the maximum screen size must be configured in terms of the number of tiles in X & Y axis." hexmask.long.word 0x28 19.--31. 1. "Reserved_19,Reserved_19" newline hexmask.long.tbyte 0x28 0.--18. 1. "STRIDE,Number of tiles in a Macrotile. Stride = (XTile * YTiles) tiles 32 pixels across by 32 pixels" line.long 0x2C "RGX_CR_TE_MTILE_1,In order to perform the tiling operation and generate the display list the maximum screen size must be configured in terms of the number of tiles in X & Y axis." hexmask.long 0x2C 0.--31. 1. "Reserved_19,Reserved_19" line.long 0x30 "RGX_CR_TE_PSG_0,This register defines the global control for the Parameter Stream Generator within the Tiling Co-Processor. This module formats the display list generated by the Tiling Co-Processor." hexmask.long.word 0x30 22.--31. 1. "Reserved_22,Reserved_22" newline bitfld.long 0x30 21. "CS_SIZE,Size of control stream chunk. 0x0 512 bit 0x1 1024 bit" "0,1" newline bitfld.long 0x30 20. "ENABLE_PWR_GATE_STATE,Enables TE PSG power gate state init. 0x0 Disable 0x1 Enable" "0,1" newline bitfld.long 0x30 19. "ENABLE_CONTEXT_STATE_RESTORE,Enables sampling of Driver TE_STATE_ISP_STATE_ID and TE_ACTIVE_MTILE registers on context switch/restore when set when reset current local value is preserved." "0,1" newline bitfld.long 0x30 18. "ZONLYRENDER,Don't invalidate Tail Pointer Cache entries on a Terminate command. Only effective when COMPLETEONTERMINATE is 0x0 0x0 Do Invalidate 0x1 Don't Invalidate" "0,1" newline bitfld.long 0x30 17. "COMPLETEONTERMINATE,0x1 Write region headers terminate streams and invalidate tail pointer cache entries on terminate. 0x0 If ZONLYRENDER = 0x0 then force an Interrupt however if ZONLYRENDER = 0x1 then write region headers and terminate streams." "0,1" newline bitfld.long 0x30 15.--16. "Reserved_15,Reserved_15" "0,1,2,3" newline bitfld.long 0x30 14. "CACHE_BYPASS,when set VCE sets its write only cache to bypass mode effectively disabling the cache" "0,1" newline bitfld.long 0x30 13. "FORCENEWSTATE,Always embed state information in control stream. Debug only." "0,1" newline bitfld.long 0x30 11.--12. "Reserved_11,Reserved_11" "0,1,2,3" newline hexmask.long.word 0x30 0.--10. 1. "REGION_STRIDE,Number of 4kB Pages devoted to region headers for each Render Target - max needed = 0x500" line.long 0x34 "RGX_CR_TE_PSG_1,This register defines the global control for the Parameter Stream Generator within the Tiling Co-Processor. This module formats the display list generated by the Tiling Co-Processor." hexmask.long 0x34 0.--31. 1. "Reserved_22,Reserved_22" line.long 0x38 "RGX_CR_TE_PSG_TERMINATE_0,This register can be written by the driver to define what the TA should terminate tile control streams with. Default value is 0x00000002. however this can be replaced with a link pointer to some driver defined control stream." hexmask.long 0x38 0.--31. 1. "DWORD,Double-word to terminate all tile control streams with." line.long 0x3C "RGX_CR_TE_PSG_TERMINATE_1,This register can be written by the driver to define what the TA should terminate tile control streams with. Default value is 0x00000002. however this can be replaced with a link pointer to some driver defined control stream." hexmask.long.tbyte 0x3C 8.--31. 1. "Reserved_40,Reserved_40" newline hexmask.long.byte 0x3C 0.--7. 1. "BYTE,Byte to terminate all tile control streams with." line.long 0x40 "RGX_CR_TE_PSGREGION_ADDR_0,This register defines the base address in memory of the Region Header writes by the TA. Region headers are the first part of the display list and contain an entry per tile with information on global setup and a link address to.." hexmask.long 0x40 6.--31. 1. "BASE,16GB Addressable 512-bit aligned Base Address for Region Header writes" newline hexmask.long.byte 0x40 0.--5. 1. "Reserved_0,Reserved_0" line.long 0x44 "RGX_CR_TE_PSGREGION_ADDR_1,This register defines the base address in memory of the Region Header writes by the TA. Region headers are the first part of the display list and contain an entry per tile with information on global setup and a link address to.." hexmask.long.tbyte 0x44 8.--31. 1. "Reserved_40,Reserved_40" newline hexmask.long.byte 0x44 2.--7. 1. "HEAP,1TB Addressable 16GB aligned Heap Address for Region Header writes" newline bitfld.long 0x44 0.--1. "BASE,16GB Addressable 512-bit aligned Base Address for Region Header writes" "0,1,2,3" line.long 0x48 "RGX_CR_TE_TPC_ADDR_0,This register defines the base address in memory of the Tail Pointer Cache. A tail pointer is the current last address written to for a tiles individual display list. an entry for active tiles is maintained as primitives are.." hexmask.long 0x48 6.--31. 1. "BASE,16GB Addressable 512-bit aligned Base Address for Tail Pointer Cache entries. The tail pointer is the current last address written to for a control stream for a tile." newline hexmask.long.byte 0x48 0.--5. 1. "Reserved_0,Reserved_0" line.long 0x4C "RGX_CR_TE_TPC_ADDR_1,This register defines the base address in memory of the Tail Pointer Cache. A tail pointer is the current last address written to for a tiles individual display list. an entry for active tiles is maintained as primitives are.." hexmask.long.tbyte 0x4C 8.--31. 1. "Reserved_40,Reserved_40" newline hexmask.long.byte 0x4C 2.--7. 1. "HEAP,1TB Addressable 16GB aligned Heap Address for Tail Pointer Cache." newline bitfld.long 0x4C 0.--1. "BASE,16GB Addressable 512-bit aligned Base Address for Tail Pointer Cache entries. The tail pointer is the current last address written to for a control stream for a tile." "0,1,2,3" line.long 0x50 "RGX_CR_TE_TPC_0,This register defines the TPC Memory footprint size per Render Target as a Stride of 4KB pages" hexmask.long.tbyte 0x50 12.--31. 1. "Reserved_12,Reserved_12" newline hexmask.long.word 0x50 0.--11. 1. "STRIDE,Number of 4KB pages per Render Target in each TPC footprint - max = 2048" line.long 0x54 "RGX_CR_TE_TPC_1,This register defines the TPC Memory footprint size per Render Target as a Stride of 4KB pages" hexmask.long 0x54 0.--31. 1. "Reserved_12,Reserved_12" line.long 0x58 "RGX_CR_TE_TPC_CONTEXT_0,The Tail Pointer Cache is used to keep track of the last address written to for a particular tile. this is stored in a mixture of on chip cache and external memory. Under certain circumstances it is neccesary to either reset the.." bitfld.long 0x58 31. "CLEAR_PENDING,Reset contents of Tail Pointer Cache" "0,1" newline bitfld.long 0x58 30. "FLUSH_PENDING,Flush contents of Tail Pointer Cache to Memory" "0,1" newline hexmask.long 0x58 0.--29. 1. "Reserved_0,Reserved_0" line.long 0x5C "RGX_CR_TE_TPC_CONTEXT_1,The Tail Pointer Cache is used to keep track of the last address written to for a particular tile. this is stored in a mixture of on chip cache and external memory. Under certain circumstances it is neccesary to either reset the.." hexmask.long 0x5C 0.--31. 1. "Reserved_32,Reserved_32" rgroup.long 0xC58++0xF line.long 0x0 "RGX_CR_TE_RGNBBOX_X_0,Reset or enabled by the PPP_RESETBBOX and PPP_UPDATEBBOX fields in the PPPControl word of the Input Parameter format. This is the maximum extent in X of the post transformed. clipped data before region clipping." hexmask.long.byte 0x0 26.--31. 1. "Reserved_26,Reserved_26" newline hexmask.long.word 0x0 16.--25. 1. "MAX,XMax value for maintained Region Generator Bounding Box tiles 32 pixels in width" newline hexmask.long.byte 0x0 10.--15. 1. "Reserved_10,Reserved_10" newline hexmask.long.word 0x0 0.--9. 1. "MIN,XMin value for maintained Region Generator Bounding Box tiles 32 pixels in width" line.long 0x4 "RGX_CR_TE_RGNBBOX_X_1,Reset or enabled by the PPP_RESETBBOX and PPP_UPDATEBBOX fields in the PPPControl word of the Input Parameter format. This is the maximum extent in X of the post transformed. clipped data before region clipping." hexmask.long 0x4 0.--31. 1. "Reserved_26,Reserved_26" line.long 0x8 "RGX_CR_TE_RGNBBOX_Y_0,Reset or enabled by the PPP_RESETBBOX and PPP_UPDATEBBOX fields in the PPP Control word of the Input Parameter format. This is the maximum extent in Y of the post transformed. clipped data before region clipping." hexmask.long.byte 0x8 26.--31. 1. "Reserved_26,Reserved_26" newline hexmask.long.word 0x8 16.--25. 1. "MAX,YMax value for maintained Region Generator Bounding Box tiles 16 pixels in height" newline hexmask.long.byte 0x8 10.--15. 1. "Reserved_10,Reserved_10" newline hexmask.long.word 0x8 0.--9. 1. "MIN,YMin value for maintained Region Generator Bounding Box tiles 16 pixels in height" line.long 0xC "RGX_CR_TE_RGNBBOX_Y_1,Reset or enabled by the PPP_RESETBBOX and PPP_UPDATEBBOX fields in the PPP Control word of the Input Parameter format. This is the maximum extent in Y of the post transformed. clipped data before region clipping." hexmask.long 0xC 0.--31. 1. "Reserved_26,Reserved_26" group.long 0xC68++0x7 line.long 0x0 "RGX_CR_TE_RGNHDR_INIT_0,A write of '1' to this register starts the TE Region Header Initialisation Sequence The TE HW will clear the PENDING bit once the operation is complete" hexmask.long 0x0 1.--31. 1. "Reserved_1,Reserved_1" newline bitfld.long 0x0 0. "PENDING,Start TE Region Header Initialisation" "0,1" line.long 0x4 "RGX_CR_TE_RGNHDR_INIT_1,A write of '1' to this register starts the TE Region Header Initialisation Sequence The TE HW will clear the PENDING bit once the operation is complete" hexmask.long 0x4 0.--31. 1. "Reserved_1,Reserved_1" group.long 0xC78++0x17 line.long 0x0 "RGX_CR_PPP_GRIDOFFSET_0,Sample position grid offset for use when MSAA/ODAA is DISABLED DX (0.0.0.0) OpenGL (0.5.0.5) Acts as the 9th multisample position when MSAA is ENABLED." hexmask.long.tbyte 0x0 8.--31. 1. "Reserved_8,Reserved_8" newline hexmask.long.byte 0x0 4.--7. 1. "GRID_Y,Unsigned sub-pixel offset" newline hexmask.long.byte 0x0 0.--3. 1. "GRID_X,Unsigned sub-pixel offset" line.long 0x4 "RGX_CR_PPP_GRIDOFFSET_1,Sample position grid offset for use when MSAA/ODAA is DISABLED DX (0.0.0.0) OpenGL (0.5.0.5) Acts as the 9th multisample position when MSAA is ENABLED." hexmask.long 0x4 0.--31. 1. "Reserved_8,Reserved_8" line.long 0x8 "RGX_CR_PPP_MULTISAMPLECTL_0,Sample position grid offset for use in 2x. 4x. 8xMSAA and ODAA modes." hexmask.long.byte 0x8 28.--31. 1. "MSAA_Y3,Unsigned sub-pixel offset for the 4th multisample Y position" newline hexmask.long.byte 0x8 24.--27. 1. "MSAA_X3,Unsigned sub-pixel offset for the 4th multisample X position" newline hexmask.long.byte 0x8 20.--23. 1. "MSAA_Y2,Unsigned sub-pixel offset for the 3rd multisample Y position" newline hexmask.long.byte 0x8 16.--19. 1. "MSAA_X2,Unsigned sub-pixel offset for the 3rd multisample X position" newline hexmask.long.byte 0x8 12.--15. 1. "MSAA_Y1,Unsigned sub-pixel offset for the 2nd multisample Y position" newline hexmask.long.byte 0x8 8.--11. 1. "MSAA_X1,Unsigned sub-pixel offset for the 2nd multisample X position" newline hexmask.long.byte 0x8 4.--7. 1. "MSAA_Y0,Unsigned sub-pixel offset for the 1st multisample Y position" newline hexmask.long.byte 0x8 0.--3. 1. "MSAA_X0,Unsigned sub-pixel offset for the 1st multisample X position" line.long 0xC "RGX_CR_PPP_MULTISAMPLECTL_1,Sample position grid offset for use in 2x. 4x. 8xMSAA and ODAA modes." hexmask.long 0xC 0.--31. 1. "Reserved_32,Reserved_32" line.long 0x10 "RGX_CR_PPP_CTRL_0,This register controls the global setup of the PPP." hexmask.long.tbyte 0x10 13.--31. 1. "Reserved_13,Reserved_13" newline bitfld.long 0x10 12. "VPT_SCISSOR,When 0 the PPP will insert state updates on change of VPT ID When 1 this feature is disabled" "0,1" newline bitfld.long 0x10 11. "FLUSH_MODE,when 0 PPP will supress end of draw call flushed from reaching the Clipper and TA pipeline This will break batch number funstionality but will give better primitive block utiliastion. when 1 PPP will not supress any flushes" "0,1" newline bitfld.long 0x10 10. "BFCULL_RESTRICT_CLIP,When set clipped primitives are only back-face culled after the clipper. 0 Enable early back face cull for clipped primitives 1 Disable early cull" "0,1" newline bitfld.long 0x10 9. "FIXED_POINT_FORMAT,When set the PPP will use a fixed point format of 16. 8 rather than 16.4. 0 16.4 fixed point format 1 16.8 fixed point format" "0,1" newline bitfld.long 0x10 8. "DEFAULT_POINT_SIZE,When set the PPP will use the default point size rather than reading it from the vertex. 0 Point size read from vertex 1 Default point size of 3F800000 used" "0,1" newline bitfld.long 0x10 7. "BFCULL1_DISABLE,Disable for fully clipped culling 0 First back face cull block enabled 1 First back face cull block disabled" "0,1" newline bitfld.long 0x10 6. "BFCULL2_DISABLE,Disable for fully clipped culling 0 Second back face cull block enabled 1 Second back face cull block disabled" "0,1" newline bitfld.long 0x10 5. "FCCULL_DISABLE,Disable for fully clipped culling 0 Fully clipped culling enabled 1 Fully clipped culling disabled" "0,1" newline bitfld.long 0x10 4. "OSCULL_DISABLE,Disable for off screen culling 0 Off screen culling enabled 1 Off screen culling disabled" "0,1" newline bitfld.long 0x10 3. "PSOCULL_DISABLE,Disable for perfect small object culling 0 Perfect small object culling enabled 1 Perfect small object culling disabled" "0,1" newline bitfld.long 0x10 2. "SOCULL_DISABLE,Disable for small object culling 0 Small object culling enabled 1 Small object culling disabled" "0,1" newline bitfld.long 0x10 1. "WCLAMPEN,Enable W clamping 0 W clamping disabled 1 W clamping enabled" "0,1" newline bitfld.long 0x10 0. "OPENGL,Select OpenGL or D3D mode 0 D3D 1 OpenGL" "0,1" line.long 0x14 "RGX_CR_PPP_CTRL_1,This register controls the global setup of the PPP." hexmask.long 0x14 0.--31. 1. "Reserved_13,Reserved_13" repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) group.long ($2+0xC90)++0x3 line.long 0x0 "RGX_CR_PPP_WCLAMP_$1,RGX_CR_PPP_WCLAMP_0" hexmask.long 0x0 0.--31. 1. "CLAMP_VALUE,Clamp value for W clamping. See the Input parameter format viewport transform for details. Clamp is applied post viewport transform if the w value is less than the WCOMPARE value. Note that this value cannot be negative." repeat.end group.long 0xC98++0xF line.long 0x0 "RGX_CR_PPP_SCREEN_0,In order to perform the tiling operation and generate the display list the maximum screen size must be configured in terms of the number of pixels in X & Y axis since this may not be the same as the number of tiles defined in the.." bitfld.long 0x0 31. "Reserved_31,Reserved_31" "0,1" newline hexmask.long.word 0x0 16.--30. 1. "PIXYMAX,Screen height in pixels. (16K x 16K max screen size)" newline bitfld.long 0x0 15. "Reserved_15,Reserved_15" "0,1" newline hexmask.long.word 0x0 0.--14. 1. "PIXXMAX,Screen width in pixels.(16K x 16K max screen size)" line.long 0x4 "RGX_CR_PPP_SCREEN_1,In order to perform the tiling operation and generate the display list the maximum screen size must be configured in terms of the number of pixels in X & Y axis since this may not be the same as the number of tiles defined in the.." hexmask.long 0x4 0.--31. 1. "Reserved_31,Reserved_31" line.long 0x8 "RGX_CR_VCE_CTRL_0,This register controls the global setup of the VCE." hexmask.long 0x8 4.--31. 1. "Reserved_4,Reserved_4" newline bitfld.long 0x8 3. "CACHE_BYPASS,when set VCE sets its write only cache to bypass mode effectively disabling the cache" "0,1" newline bitfld.long 0x8 2. "Reserved_2,Reserved_2" "0,1" newline bitfld.long 0x8 1. "TWO_ORIGIN_DISABLE,When set raw mode is selected in place of 2-origin delta stream compression mode" "0,1" newline bitfld.long 0x8 0. "COMPRESS_DISABLE,When set vertex compression is disabled. I.e. raw mode is forced for all vertices" "0,1" line.long 0xC "RGX_CR_VCE_CTRL_1,This register controls the global setup of the VCE." hexmask.long 0xC 0.--31. 1. "Reserved_4,Reserved_4" wgroup.long 0xCA8++0x7 line.long 0x0 "RGX_CR_TE_CLEAR_LISTS_AFTER_ABORT_0,A write of '1' to this register tells the TE we are resuming after an Abort and Partial Render Sequence" hexmask.long 0x0 1.--31. 1. "Reserved_1,Reserved_1" newline bitfld.long 0x0 0. "PULSE,TE Clears all references after Abort and Partial Render Sequence" "0,1" line.long 0x4 "RGX_CR_TE_CLEAR_LISTS_AFTER_ABORT_1,A write of '1' to this register tells the TE we are resuming after an Abort and Partial Render Sequence" hexmask.long 0x4 0.--31. 1. "Reserved_1,Reserved_1" group.long 0xCB0++0x17 line.long 0x0 "RGX_CR_TA_RTC_ADDR_0,This register defines the base address in memory of the TA Render Target Caches. for the VCE. TEAC and PSG" hexmask.long 0x0 6.--31. 1. "BASE,16GB Addressabreadonly le 512-bit aligned Base Address for TA Render Target Caches." newline hexmask.long.byte 0x0 0.--5. 1. "Reserved_0,Reserved_0" line.long 0x4 "RGX_CR_TA_RTC_ADDR_1,This register defines the base address in memory of the TA Render Target Caches. for the VCE. TEAC and PSG" hexmask.long.tbyte 0x4 8.--31. 1. "Reserved_40,Reserved_40" newline hexmask.long.byte 0x4 2.--7. 1. "HEAP,1TB Addressable 16GB aligned Heap Address for TA Render Target Caches" newline bitfld.long 0x4 0.--1. "BASE,16GB Addressabreadonly le 512-bit aligned Base Address for TA Render Target Caches." "0,1,2,3" line.long 0x8 "RGX_CR_TA_RTC_CTRL_0,A write of '1' to Bit 0 of this register Clears the RTC. A write of '1' to Bit 1 of this register Stores the RTC to memory (address specified in TA_RTC_ADDR register)" hexmask.long 0x8 2.--31. 1. "Reserved_2,Reserved_2" newline bitfld.long 0x8 1. "STORE_PENDING,Store RTC" "0,1" newline bitfld.long 0x8 0. "CLEAR_PENDING,Clear RTC" "0,1" line.long 0xC "RGX_CR_TA_RTC_CTRL_1,A write of '1' to Bit 0 of this register Clears the RTC. A write of '1' to Bit 1 of this register Stores the RTC to memory (address specified in TA_RTC_ADDR register)" hexmask.long 0xC 0.--31. 1. "Reserved_2,Reserved_2" line.long 0x10 "RGX_CR_TA_CONTEXT_STATE_BASE_0,The base address in external memory of the TA's context state buffer. to which the PPP will store the state on a context store and from which the VDM will reload on a context resume" hexmask.long 0x10 4.--31. 1. "ADDR,1TB range 128-bit aligned base address" newline hexmask.long.byte 0x10 0.--3. 1. "Reserved_0,Reserved_0" line.long 0x14 "RGX_CR_TA_CONTEXT_STATE_BASE_1,The base address in external memory of the TA's context state buffer. to which the PPP will store the state on a context store and from which the VDM will reload on a context resume" hexmask.long.tbyte 0x14 8.--31. 1. "Reserved_40,Reserved_40" newline hexmask.long.byte 0x14 0.--7. 1. "ADDR,1TB range 128-bit aligned base address" rgroup.long 0xCC8++0x7 line.long 0x0 "RGX_CR_PPP_DIAG_CULL_0,Diagnois register keeps a count of the number of primtives entering the PPP culling module" hexmask.long.byte 0x0 26.--31. 1. "OP_COUNT,count of primitives exiting the cull block" newline hexmask.long 0x0 0.--25. 1. "IP_COUNT,count of primitives entering the cull block" line.long 0x4 "RGX_CR_PPP_DIAG_CULL_1,Diagnois register keeps a count of the number of primtives entering the PPP culling module" hexmask.long.word 0x4 20.--31. 1. "Reserved_52,Reserved_52" newline hexmask.long.tbyte 0x4 0.--19. 1. "OP_COUNT,count of primitives exiting the cull block" repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) rgroup.long ($2+0xCD0)++0x3 line.long 0x0 "RGX_CR_PPP_$1,Checksum generated from the output of the PPP" hexmask.long 0x0 0.--31. 1. "CHECKSUM,checksum generated from the output of the PPP" repeat.end group.long 0xCD8++0x1F line.long 0x0 "RGX_CR_UVS_CLEAR_0,A write of '1' to this register starts the UVS Clear Operation This register must be written during the core initialisation sequence." hexmask.long 0x0 1.--31. 1. "Reserved_1,Reserved_1" newline bitfld.long 0x0 0. "PENDING,Start UVS Clear Operation a write to this register results in a one cycle pulse" "0,1" line.long 0x4 "RGX_CR_UVS_CLEAR_1,A write of '1' to this register starts the UVS Clear Operation This register must be written during the core initialisation sequence." hexmask.long 0x4 0.--31. 1. "Reserved_1,Reserved_1" line.long 0x8 "RGX_CR_TA_RTC_PRELOAD_0,When set. the RTC will be Preloaded with Zeros (or a nonRTA render target of 1) on a Clear Operation (used when Render Targets are not in use to remove the need for memory allocation)" hexmask.long 0x8 2.--31. 1. "Reserved_2,Reserved_2" newline bitfld.long 0x8 1. "ONE,Preload RTC with Render Target 0 set on a Clear. Used when resuming a TA phase after coarse grain context switch" "0,1" newline bitfld.long 0x8 0. "ZEROS,Preload RTC with Zeros on a Clear" "0,1" line.long 0xC "RGX_CR_TA_RTC_PRELOAD_1,When set. the RTC will be Preloaded with Zeros (or a nonRTA render target of 1) on a Clear Operation (used when Render Targets are not in use to remove the need for memory allocation)" hexmask.long 0xC 0.--31. 1. "Reserved_2,Reserved_2" line.long 0x10 "RGX_CR_TE_STATE_0,This register should be Sampled by the Driver on Context Switch and Restored before the Resume of the TA Context" hexmask.long 0x10 6.--31. 1. "Reserved_6,Reserved_6" newline hexmask.long.byte 0x10 1.--5. 1. "ISP_STATE_ID,ISP State ID" newline bitfld.long 0x10 0. "ABORTED,TA had been aborted in the past" "0,1" line.long 0x14 "RGX_CR_TE_STATE_1,This register should be Sampled by the Driver on Context Switch and Restored before the Resume of the TA Context" hexmask.long 0x14 0.--31. 1. "Reserved_6,Reserved_6" line.long 0x18 "RGX_CR_VCE_HALT_0,The MicroKernel must halt VCE processing (consumption of it's pages allocated by PM) before we can do a Partial Render in the Rogue Architecture. When it writes this register. the VCE will detect this on a notify pulse and assert the.." hexmask.long 0x18 1.--31. 1. "Reserved_1,Reserved_1" newline bitfld.long 0x18 0. "PENDING,VCE is Halting after Current Block" "0,1" line.long 0x1C "RGX_CR_VCE_HALT_1,The MicroKernel must halt VCE processing (consumption of it's pages allocated by PM) before we can do a Partial Render in the Rogue Architecture. When it writes this register. the VCE will detect this on a notify pulse and assert the.." hexmask.long 0x1C 0.--31. 1. "Reserved_1,Reserved_1" wgroup.long 0xCF8++0x7 line.long 0x0 "RGX_CR_TE_RESUME_AFTER_ABORT_0,A write of '1' to this register tells the TE we are resuming after an Abort but that no Partial Render took place" hexmask.long 0x0 1.--31. 1. "Reserved_1,Reserved_1" newline bitfld.long 0x0 0. "PULSE,TE is restarted and reattempts failing allocation after Out Of Memory event only" "0,1" line.long 0x4 "RGX_CR_TE_RESUME_AFTER_ABORT_1,A write of '1' to this register tells the TE we are resuming after an Abort but that no Partial Render took place" hexmask.long 0x4 0.--31. 1. "Reserved_1,Reserved_1" rgroup.long 0xD00++0x7 line.long 0x0 "RGX_CR_TA_IDLE_0,RGX_CR_TA_IDLE_0" hexmask.long 0x0 6.--31. 1. "Reserved_6,Reserved_6" newline bitfld.long 0x0 5. "TE,TE Module IDLE" "0,1" newline bitfld.long 0x0 4. "VCE,VCE Module IDLE" "0,1" newline bitfld.long 0x0 3. "VBG,VBG Module IDLE" "0,1" newline bitfld.long 0x0 2. "CLIP,CLIP Module IDLE" "0,1" newline bitfld.long 0x0 1. "PPP,PPP Module IDLE" "0,1" newline bitfld.long 0x0 0. "UVS,UVS Module IDLE" "0,1" line.long 0x4 "RGX_CR_TA_IDLE_1,RGX_CR_TA_IDLE_1" hexmask.long 0x4 0.--31. 1. "Reserved_6,Reserved_6" repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) rgroup.long ($2+0xD08)++0x3 line.long 0x0 "RGX_CR_STAT_NEW_PRIM_$1,RGX_CR_STAT_NEW_PRIM_0" hexmask.long 0x0 0.--31. 1. "PPP,Number of primitives into PPP" repeat.end repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) rgroup.long ($2+0xD10)++0x3 line.long 0x0 "RGX_CR_STAT_NEW_$1,RGX_CR_STAT_NEW_0" hexmask.long 0x0 0.--31. 1. "VERTEX,Number of vertices" repeat.end group.long 0xD18++0x27 line.long 0x0 "RGX_CR_FBC_MEM_POINTER_0,Framebuffer last memory address written in indirect mode" hexmask.long 0x0 0.--31. 1. "BASE_ADDRESS_REQ,Set to base address of compressed surface to find the last written address for that surface by reading the register when FBC_MEM_POINTER_READ_PENDING =0. BASE_ADDRESS=[33..0] DM=[36..34]" line.long 0x4 "RGX_CR_FBC_MEM_POINTER_1,Framebuffer last memory address written in indirect mode" hexmask.long 0x4 6.--31. 1. "Reserved_38,Reserved_38" newline bitfld.long 0x4 5. "READ_PENDING,Write 1 to perform a lookup for the last memory address written for that surface specified when this register is read as 0 then contents of FBC_MEM_POINTER_BASE_ADDRESS_REQ register contains the last memory address written for the.." "0,1" newline hexmask.long.byte 0x4 0.--4. 1. "BASE_ADDRESS_REQ,Set to base address of compressed surface to find the last written address for that surface by reading the register when FBC_MEM_POINTER_READ_PENDING =0. BASE_ADDRESS=[33..0] DM=[36..34]" line.long 0x8 "RGX_CR_TE_PSG_RTC_0,This register should be Sampled by the Driver on VDM Context Switch Terminate TA FINISHED event and Restored before the Resume of the TA Context" hexmask.long.tbyte 0x8 12.--31. 1. "Reserved_12,Reserved_12" newline hexmask.long.word 0x8 0.--11. 1. "ACTIVE_RTS,RTAs active at the point of the VDM Context SWitch" line.long 0xC "RGX_CR_TE_PSG_RTC_1,This register should be Sampled by the Driver on VDM Context Switch Terminate TA FINISHED event and Restored before the Resume of the TA Context" hexmask.long 0xC 0.--31. 1. "Reserved_12,Reserved_12" line.long 0x10 "RGX_CR_VCE_CACHE_FLUSH_0,The MicroKernel can use this to flush the VCE write only cache at the end of TA phase render. When it writes this register. the VCE will detect this on a notify pulse and assert the return signal until it has completed processing.." hexmask.long 0x10 1.--31. 1. "Reserved_1,Reserved_1" newline bitfld.long 0x10 0. "PENDING,VCE is Flushing its write only cache to memory" "0,1" line.long 0x14 "RGX_CR_VCE_CACHE_FLUSH_1,The MicroKernel can use this to flush the VCE write only cache at the end of TA phase render. When it writes this register. the VCE will detect this on a notify pulse and assert the return signal until it has completed processing.." hexmask.long 0x14 0.--31. 1. "Reserved_1,Reserved_1" line.long 0x18 "RGX_CR_TE_CACHE_FLUSH_0,The MicroKernel can use this to flush the TE write only cache at the end of TA phase render. When it writes this register. the TE will detect this on a notify pulse and assert the return signal until it has completed processing.." hexmask.long 0x18 1.--31. 1. "Reserved_1,Reserved_1" newline bitfld.long 0x18 0. "PENDING,TE is Flushing its write only cache to memory" "0,1" line.long 0x1C "RGX_CR_TE_CACHE_FLUSH_1,The MicroKernel can use this to flush the TE write only cache at the end of TA phase render. When it writes this register. the TE will detect this on a notify pulse and assert the return signal until it has completed processing.." hexmask.long 0x1C 0.--31. 1. "Reserved_1,Reserved_1" line.long 0x20 "RGX_CR_PM_CACHE_FLUSH_0,The MicroKernel can use this to flush the PM write only cache at the end of TA phase render. When it writes this register. the PM will detect this on a notify pulse and assert the return signal until it has completed processing.." hexmask.long 0x20 1.--31. 1. "Reserved_1,Reserved_1" newline bitfld.long 0x20 0. "PENDING,PM is Flushing its write only cache to memory" "0,1" line.long 0x24 "RGX_CR_PM_CACHE_FLUSH_1,The MicroKernel can use this to flush the PM write only cache at the end of TA phase render. When it writes this register. the PM will detect this on a notify pulse and assert the return signal until it has completed processing.." hexmask.long 0x24 0.--31. 1. "Reserved_1,Reserved_1" wgroup.long 0xF00++0x7 line.long 0x0 "RGX_CR_ISP_START_RENDER_0,Writing '1' to this register initiates a 3D render" hexmask.long 0x0 1.--31. 1. "Reserved_1,Reserved_1" newline bitfld.long 0x0 0. "PULSE,PULSE" "0,1" line.long 0x4 "RGX_CR_ISP_START_RENDER_1,Writing '1' to this register initiates a 3D render" hexmask.long 0x4 0.--31. 1. "Reserved_1,Reserved_1" group.long 0xF08++0x77 line.long 0x0 "RGX_CR_ISP_RENDER_0,Controls the render" hexmask.long 0x0 5.--31. 1. "Reserved_5,Reserved_5" newline bitfld.long 0x0 4. "RESUME,Render resume" "0,1" newline bitfld.long 0x0 2.--3. "DIR,Render direction" "0,1,2,3" newline bitfld.long 0x0 0.--1. "MODE,Render type" "0,1,2,3" line.long 0x4 "RGX_CR_ISP_RENDER_1,Controls the render" hexmask.long 0x4 0.--31. 1. "Reserved_5,Reserved_5" line.long 0x8 "RGX_CR_ISP_RENDER_ORIGIN_0,This register defines the top-left tile coordinate for the render." hexmask.long.byte 0x8 26.--31. 1. "Reserved_26,Reserved_26" newline hexmask.long.word 0x8 16.--25. 1. "X,X coordinate in tiles" newline hexmask.long.byte 0x8 10.--15. 1. "Reserved_10,Reserved_10" newline hexmask.long.word 0x8 0.--9. 1. "Y,Y coordinate in tiles" line.long 0xC "RGX_CR_ISP_RENDER_ORIGIN_1,This register defines the top-left tile coordinate for the render." hexmask.long 0xC 0.--31. 1. "Reserved_26,Reserved_26" line.long 0x10 "RGX_CR_ISP_MTILE_SIZE_0,RGX_CR_ISP_MTILE_SIZE_0" hexmask.long.byte 0x10 26.--31. 1. "Reserved_26,Reserved_26" newline hexmask.long.word 0x10 16.--25. 1. "X,Macrotile width in tiles. A value of zero corresponds to the maximum size" newline hexmask.long.byte 0x10 10.--15. 1. "Reserved_10,Reserved_10" newline hexmask.long.word 0x10 0.--9. 1. "Y,Macrotile height in tiles. A value of zero corresponds to the maximum size" line.long 0x14 "RGX_CR_ISP_MTILE_SIZE_1,RGX_CR_ISP_MTILE_SIZE_1" hexmask.long 0x14 0.--31. 1. "Reserved_26,Reserved_26" line.long 0x18 "RGX_CR_ISP_MTILE_BASE_0,RGX_CR_ISP_MTILE_BASE_0" hexmask.long 0x18 2.--31. 1. "ADDR,1TB range 32-bit aligned base address" newline bitfld.long 0x18 0.--1. "Reserved_0,Reserved_0" "0,1,2,3" line.long 0x1C "RGX_CR_ISP_MTILE_BASE_1,RGX_CR_ISP_MTILE_BASE_1" hexmask.long.tbyte 0x1C 8.--31. 1. "Reserved_40,Reserved_40" newline hexmask.long.byte 0x1C 0.--7. 1. "ADDR,1TB range 32-bit aligned base address" line.long 0x20 "RGX_CR_ISP_RGN_0,This register defines the sizes of the allocations of the simple internal parameter data." bitfld.long 0x20 29.--31. "Reserved_29,Reserved_29" "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x20 24.--28. 1. "CS_SIZE,Number of primitive headers in the control stream for a fast 2D render. If the number of primitive headers exceeds the maximum field size or the size of the control stream is unknown a value of all ones should be written" newline hexmask.long.tbyte 0x20 0.--23. 1. "SIZE,Number of Region Headers to fetch" line.long 0x24 "RGX_CR_ISP_RGN_1,This register defines the sizes of the allocations of the simple internal parameter data." hexmask.long 0x24 0.--31. 1. "Reserved_29,Reserved_29" line.long 0x28 "RGX_CR_ISP_AA_0,Controls whether anti-aliasing is enabled or disabled" hexmask.long 0x28 2.--31. 1. "Reserved_2,Reserved_2" newline bitfld.long 0x28 0.--1. "MODE,MODE" "0,1,2,3" line.long 0x2C "RGX_CR_ISP_AA_1,Controls whether anti-aliasing is enabled or disabled" hexmask.long 0x2C 0.--31. 1. "Reserved_2,Reserved_2" line.long 0x30 "RGX_CR_ISP_CTL_0,ISP control register. This register contains the PIPE_NUM field which controls the number of tiles in flight within the IPP and IPF. The values to which this register should be set are dependent on not only the number of tiles in flight.." bitfld.long 0x30 31. "Reserved_31,Reserved_31" "0,1" newline bitfld.long 0x30 30. "LINE_STYLE,Used to enable rendering widelines as rectangles. '0': render as parallelograms '1': render as retangles" "0,1" newline bitfld.long 0x30 29. "LINE_STYLE_PIX,Used to enable rendering single pixel widelines as rectangles. '0': render as parallelograms '1': render as retangles" "0,1" newline bitfld.long 0x30 28. "PAIR_TILES_VERT,If set causes IPF to pair tiles vertically within its pipeline." "0,1" newline bitfld.long 0x30 27. "PAIR_TILES,If set causes IPF to pair tiles within its pipeline." "0,1" newline hexmask.long.byte 0x30 21.--26. 1. "Reserved_21,Reserved_21" newline bitfld.long 0x30 20. "DBIAS_IS_INT,When set depth bias value is a signed integer" "0,1" newline bitfld.long 0x30 19. "OVERLAP_CHECK_MODE,0 - different samples for the same pixel will be sent to different pass groups for translucent objects (pixel to pixel overlap test) 1 - different samples for the same pixel will be sent as the same pass group (sample to sample overlap.." "different samples for the same pixel will be..,different samples for the same pixel will be.." newline bitfld.long 0x30 18. "PT_UPFRONT_DEPTH_DISABLE,When set disable UPFRONT depth test in the Depthsorter" "0,1" newline bitfld.long 0x30 17. "PROCESS_EMPTY_TILES,When set empty tiles are always processed rather than being suppressed" "0,1" newline bitfld.long 0x30 16. "SAMPLE_POS,Specifies the sampling rule to be used when calculating the endpoint adjustment for thin lines" "0,1" newline hexmask.long.byte 0x30 12.--15. 1. "PIPE_ENABLE,Tiles-in-flight" newline bitfld.long 0x30 10.--11. "Reserved_10,Reserved_10" "0,1,2,3" newline hexmask.long.byte 0x30 4.--9. 1. "VALID_ID,Triangle validation value" newline hexmask.long.byte 0x30 0.--3. 1. "UPASS_START,User pass start value" line.long 0x34 "RGX_CR_ISP_CTL_1,ISP control register. This register contains the PIPE_NUM field which controls the number of tiles in flight within the IPP and IPF. The values to which this register should be set are dependent on not only the number of tiles in flight.." hexmask.long 0x34 0.--31. 1. "Reserved_31,Reserved_31" line.long 0x38 "RGX_CR_ISP_SPLIT_RENDER_0,RGX_CR_ISP_SPLIT_RENDER_0" bitfld.long 0x38 30.--31. "Reserved_30,Reserved_30" "0,1,2,3" newline hexmask.long.word 0x38 16.--29. 1. "MAX,Render up to and including this value" newline bitfld.long 0x38 14.--15. "Reserved_14,Reserved_14" "0,1,2,3" newline hexmask.long.word 0x38 0.--13. 1. "MIN,Render up from and including this value" line.long 0x3C "RGX_CR_ISP_SPLIT_RENDER_1,RGX_CR_ISP_SPLIT_RENDER_1" hexmask.long 0x3C 1.--31. 1. "Reserved_33,Reserved_33" newline bitfld.long 0x3C 0. "ENABLE,ENABLE" "0,1" line.long 0x40 "RGX_CR_ISP_ZLSCTL_0,ISP Z Load/Store & format global control register" hexmask.long.byte 0x40 27.--31. 1. "ZLSEXTENT_Y_Z,For Depth buffer Display width of Y in tiles minus one: 0x000 1 tile 0x001 2 tiles .. 0x2FF 1024 tiles zlsextent_y = total_samples_y / 32 samples in non-msaa 4xmsaa mode = total_samples_y / 64 samples in 2xmsaa 8xmsaa mode. In.." newline bitfld.long 0x40 25.--26. "ZSTOREFORMAT,ZSTOREFORMAT" "0,1,2,3" newline bitfld.long 0x40 23.--24. "ZLOADFORMAT,ZLOADFORMAT" "0,1,2,3" newline bitfld.long 0x40 22. "FB_STOREEN,when set frame buffer compression store is enabled" "0,1" newline bitfld.long 0x40 21. "FB_LOADEN,when set frame buffer decompression load is enabled" "0,1" newline bitfld.long 0x40 20. "MSTOREEN,When set and ZSTOREFORMAT = 0x0 mask plane is stored within msb of IEEE format when set and ZSTOREFORMAT = 0x3 mask plane is stored at bit position 31 of IEEE format when set for other format if mask_store_base_enable = '1' background.." "0,1" newline bitfld.long 0x40 19. "ZSTOREEN,When set to 1 if the ZSTORE bit in the region header is also set then the depth buffer is stored to memory after each tile is processed" "0,1" newline bitfld.long 0x40 18. "SSTOREEN,When set to 1 if the ZSTORE bit in the region header is also set then the stencil buffer is stored to memory after each tile is processed" "0,1" newline bitfld.long 0x40 17. "STORETWIDDLED,When set to 1 depth and stencil data is written out in 'Twiddled' order." "0,1" newline bitfld.long 0x40 16. "MLOADEN,When set and ZLOADFORMAT = 0x0 mask plane is loaded from msb of IEEE format when set and ZLOADFORMAT = 0x3 mask plane is loaded from the bit position 31 of IEEE format when set for other format if mask_load_base_enable = '1' mask plane is.." "0,1" newline bitfld.long 0x40 15. "ZLOADEN,When set to 1 if the ZLOAD bit in the region header is also set then the depth buffer is read from memory prior to tile processing" "0,1" newline bitfld.long 0x40 14. "SLOADEN,When set to 1 if the ZLOAD bit in the region header is also set then the stencil buffer is read from memory prior to tile processing" "0,1" newline bitfld.long 0x40 13. "LOADTWIDDLED,When set to 1 depth stencil data is loaded in 'Twiddled' order" "0,1" newline hexmask.long.word 0x40 3.--12. 1. "ZLSEXTENT_X_Z,For depth buffer Display width of X in tiles minus one: 0x000 1 tile 0x001 2 tiles .. 0x2FF 1024 tiles. For different msaa mode 1xmsaa = 1 x (32 32) pixels = 32x1 x 32x1 = 1024 samples = 32 x 32 samples 2xmsaa = 2 x (32 32) pixels =.." newline bitfld.long 0x40 2. "FORCEZSTORE,If set to 1 the depth/stencil buffer is always stored at the end of each tile irrespective of the region header ZSTORE bit." "0,1" newline bitfld.long 0x40 1. "FORCEZLOAD,If set to 1 the depth/stencil buffer is always loaded at the start of each tile irrespective of the region header ZLOAD bit." "0,1" newline bitfld.long 0x40 0. "ZONLYRENDER,When set only the Z buffer is rendered. Opaque and translucent objects are stencil and depth tested as usual but no pixel spans are emitted to the PDS Pixel presenter. Pixels within punch through and depth feedback objects are emitted on.." "0,1" line.long 0x44 "RGX_CR_ISP_ZLSCTL_1,ISP Z Load/Store & format global control register" hexmask.long.byte 0x44 26.--31. 1. "Reserved_58,Reserved_58" newline hexmask.long.word 0x44 16.--25. 1. "ZLSEXTENT_Y_S,For stencil buffer the value calculation is the same as ZLSEXTENT_Y_Z" newline hexmask.long.word 0x44 6.--15. 1. "ZLSEXTENT_X_S,For stencil buffer the value calculation is the same as ZLSEXTENT_X_Z" newline bitfld.long 0x44 5. "STENCIL_EXTENT_ENABLE,When this bit is '1' stencil buffer will use zlsextent_x/y_s value to calculate zload/store address otherwise zlsextent_x/y_z value will be used. The default value is '0' which disables this new function." "0,1" newline hexmask.long.byte 0x44 0.--4. 1. "ZLSEXTENT_Y_Z,For Depth buffer Display width of Y in tiles minus one: 0x000 1 tile 0x001 2 tiles .. 0x2FF 1024 tiles zlsextent_y = total_samples_y / 32 samples in non-msaa 4xmsaa mode = total_samples_y / 64 samples in 2xmsaa 8xmsaa mode. In.." line.long 0x48 "RGX_CR_ISP_ZLOAD_BASE_0,Base address in memory of the Z Buffer base address to load into the ISP for non-compressed ZLS formats." hexmask.long 0x48 4.--31. 1. "ADDR,1TB Addressable 16byte aligned Base Address of the Z Buffer Load base address" newline hexmask.long.byte 0x48 0.--3. 1. "Reserved_0,Reserved_0" line.long 0x4C "RGX_CR_ISP_ZLOAD_BASE_1,Base address in memory of the Z Buffer base address to load into the ISP for non-compressed ZLS formats." hexmask.long.tbyte 0x4C 8.--31. 1. "Reserved_40,Reserved_40" newline hexmask.long.byte 0x4C 0.--7. 1. "ADDR,1TB Addressable 16byte aligned Base Address of the Z Buffer Load base address" line.long 0x50 "RGX_CR_ISP_ZSTORE_BASE_0,Base address in memory of the Z Buffer base address to store into the ISP for non-compressed ZLS formats." hexmask.long 0x50 4.--31. 1. "ADDR,1TB Addressable 16byte aligned Base Address of the Z Buffer Store base address" newline hexmask.long.byte 0x50 0.--3. 1. "Reserved_0,Reserved_0" line.long 0x54 "RGX_CR_ISP_ZSTORE_BASE_1,Base address in memory of the Z Buffer base address to store into the ISP for non-compressed ZLS formats." hexmask.long.tbyte 0x54 8.--31. 1. "Reserved_40,Reserved_40" newline hexmask.long.byte 0x54 0.--7. 1. "ADDR,1TB Addressable 16byte aligned Base Address of the Z Buffer Store base address" line.long 0x58 "RGX_CR_ISP_STENCIL_LOAD_BASE_0,Base address in memory of the Stencil Buffer base address to load into the ISP for non-compressed ZLS formats. This alternate stencil buffer base address is selectable based on the enable bit." hexmask.long 0x58 4.--31. 1. "ADDR,1TB Addressable 16byte aligned Base Address of the Z Buffer Load base address" newline bitfld.long 0x58 1.--3. "Reserved_1,Reserved_1" "0,1,2,3,4,5,6,7" newline bitfld.long 0x58 0. "ENABLE,When set to 1 enables fetching of stencil from a separate base address" "0,1" line.long 0x5C "RGX_CR_ISP_STENCIL_LOAD_BASE_1,Base address in memory of the Stencil Buffer base address to load into the ISP for non-compressed ZLS formats. This alternate stencil buffer base address is selectable based on the enable bit." hexmask.long.tbyte 0x5C 8.--31. 1. "Reserved_40,Reserved_40" newline hexmask.long.byte 0x5C 0.--7. 1. "ADDR,1TB Addressable 16byte aligned Base Address of the Z Buffer Load base address" line.long 0x60 "RGX_CR_ISP_STENCIL_STORE_BASE_0,Base address in memory of the Stencil Buffer base address to store into the ISP for non-compressed ZLS formats. This alternate stencil buffer base address is selectable based on the enable bit." hexmask.long 0x60 4.--31. 1. "ADDR,1TB Addressable 16byte aligned Base Address of the Z Buffer Load base address" newline bitfld.long 0x60 1.--3. "Reserved_1,Reserved_1" "0,1,2,3,4,5,6,7" newline bitfld.long 0x60 0. "ENABLE,When set to 1 enables fetching of stencil from a separate base address" "0,1" line.long 0x64 "RGX_CR_ISP_STENCIL_STORE_BASE_1,Base address in memory of the Stencil Buffer base address to store into the ISP for non-compressed ZLS formats. This alternate stencil buffer base address is selectable based on the enable bit." hexmask.long.tbyte 0x64 8.--31. 1. "Reserved_40,Reserved_40" newline hexmask.long.byte 0x64 0.--7. 1. "ADDR,1TB Addressable 16byte aligned Base Address of the Z Buffer Load base address" line.long 0x68 "RGX_CR_ISP_MASK_LOAD_BASE_0,Base address in memory of the Mask Buffer base address to load into the ISP for non-compressed ZLS formats. This alternate mask buffer base address is selectable based on the enable bit." hexmask.long 0x68 4.--31. 1. "ADDR,1TB Addressable 16byte aligned Base Address of the Z Buffer Load base address" newline bitfld.long 0x68 1.--3. "Reserved_1,Reserved_1" "0,1,2,3,4,5,6,7" newline bitfld.long 0x68 0. "ENABLE,When set to 1 enables fetching of mask from a separate base address" "0,1" line.long 0x6C "RGX_CR_ISP_MASK_LOAD_BASE_1,Base address in memory of the Mask Buffer base address to load into the ISP for non-compressed ZLS formats. This alternate mask buffer base address is selectable based on the enable bit." hexmask.long.tbyte 0x6C 8.--31. 1. "Reserved_40,Reserved_40" newline hexmask.long.byte 0x6C 0.--7. 1. "ADDR,1TB Addressable 16byte aligned Base Address of the Z Buffer Load base address" line.long 0x70 "RGX_CR_ISP_MASK_STORE_BASE_0,Base address in memory of the Mask Buffer base address to store into the ISP for non-compressed ZLS formats. This alternate mask buffer base address is selectable based on the enable bit." hexmask.long 0x70 4.--31. 1. "ADDR,1TB Addressable 16byte aligned Base Address of the Z Buffer Load base address" newline bitfld.long 0x70 1.--3. "Reserved_1,Reserved_1" "0,1,2,3,4,5,6,7" newline bitfld.long 0x70 0. "ENABLE,When set to 1 enables fetching of mask from a separate base address" "0,1" line.long 0x74 "RGX_CR_ISP_MASK_STORE_BASE_1,Base address in memory of the Mask Buffer base address to store into the ISP for non-compressed ZLS formats. This alternate mask buffer base address is selectable based on the enable bit." hexmask.long.tbyte 0x74 8.--31. 1. "Reserved_40,Reserved_40" newline hexmask.long.byte 0x74 0.--7. 1. "ADDR,1TB Addressable 16byte aligned Base Address of the Z Buffer Load base address" repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) group.long ($2+0xF80)++0x3 line.long 0x0 "RGX_CR_ISP_BGOBJDEPTH_$1,The ISP operates by comparing depth values of incoming objects with the results of previous depth compares. in order to make sure there are no unitialised values at the start of the tile or to cover pixels where there are no.." hexmask.long 0x0 0.--31. 1. "VALUE,Note the format in this register has to be consistent with the format defined by ZLS_STORE_FORMAT register. If depth buffer is F32 then the value here should be IEEE 754 single precisoin floating point If depth buffer is /INT16 then the value.." repeat.end group.long 0xF88++0x7 line.long 0x0 "RGX_CR_ISP_BGOBJVALS_0,This register provides enable. mask and stencil information for the hardware background object." hexmask.long.tbyte 0x0 10.--31. 1. "Reserved_10,Reserved_10" newline bitfld.long 0x0 9. "ENABLEBGTAG,When set to 1 at the start of each tile the ISP tag buffer is initialised with the background object tag (default = 1)" "0,1" newline bitfld.long 0x0 8. "MASK,Hardware background object mask plane" "0,1" newline hexmask.long.byte 0x0 0.--7. 1. "STENCIL,Hardware background object stencil" line.long 0x4 "RGX_CR_ISP_BGOBJVALS_1,This register provides enable. mask and stencil information for the hardware background object." hexmask.long 0x4 0.--31. 1. "Reserved_10,Reserved_10" group.long 0xFA0++0x7 line.long 0x0 "RGX_CR_ISP_GRIDOFFSET_0,Sample position grid offset for use when MSAA/ODAA is DISABLED DX (0.0.0.0) OpenGL (0.5.0.5) Acts as the 9th multisample position when MSAA is ENABLED." hexmask.long.tbyte 0x0 8.--31. 1. "Reserved_8,Reserved_8" newline hexmask.long.byte 0x0 4.--7. 1. "GRID_Y,Unsigned sub-pixel offset" newline hexmask.long.byte 0x0 0.--3. 1. "GRID_X,Unsigned sub-pixel offset" line.long 0x4 "RGX_CR_ISP_GRIDOFFSET_1,Sample position grid offset for use when MSAA/ODAA is DISABLED DX (0.0.0.0) OpenGL (0.5.0.5) Acts as the 9th multisample position when MSAA is ENABLED." hexmask.long 0x4 0.--31. 1. "Reserved_8,Reserved_8" repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) group.long ($2+0xFA8)++0x3 line.long 0x0 "RGX_CR_ISP_MULTISAMPLECTL_$1,Sample position grid offset for use in 2x. 4x. 8xMSAA and ODAA modes." hexmask.long.byte 0x0 28.--31. 1. "MSAA_Y3,Unsigned sub-pixel offset for the 4th multisample Y position" newline hexmask.long.byte 0x0 24.--27. 1. "MSAA_X3,Unsigned sub-pixel offset for the 4th multisample X position" newline hexmask.long.byte 0x0 20.--23. 1. "MSAA_Y2,Unsigned sub-pixel offset for the 3rd multisample Y position" newline hexmask.long.byte 0x0 16.--19. 1. "MSAA_X2,Unsigned sub-pixel offset for the 3rd multisample X position" newline hexmask.long.byte 0x0 12.--15. 1. "MSAA_Y1,Unsigned sub-pixel offset for the 2nd multisample Y position" newline hexmask.long.byte 0x0 8.--11. 1. "MSAA_X1,Unsigned sub-pixel offset for the 2nd multisample X position" newline hexmask.long.byte 0x0 4.--7. 1. "MSAA_Y0,Unsigned sub-pixel offset for the 1st multisample Y position" newline hexmask.long.byte 0x0 0.--3. 1. "MSAA_X0,Unsigned sub-pixel offset for the 1st multisample X position" repeat.end group.long 0xFB0++0x2F line.long 0x0 "RGX_CR_ISP_SCISSOR_BASE_0,RGX_CR_ISP_SCISSOR_BASE_0" hexmask.long 0x0 2.--31. 1. "ADDR,1TB range 32-bit aligned base address" newline bitfld.long 0x0 0.--1. "Reserved_0,Reserved_0" "0,1,2,3" line.long 0x4 "RGX_CR_ISP_SCISSOR_BASE_1,RGX_CR_ISP_SCISSOR_BASE_1" hexmask.long.tbyte 0x4 8.--31. 1. "Reserved_40,Reserved_40" newline hexmask.long.byte 0x4 0.--7. 1. "ADDR,1TB range 32-bit aligned base address" line.long 0x8 "RGX_CR_ISP_DBIAS_BASE_0,RGX_CR_ISP_DBIAS_BASE_0" hexmask.long 0x8 2.--31. 1. "ADDR,1TB range 32-bit aligned base address" newline bitfld.long 0x8 0.--1. "Reserved_0,Reserved_0" "0,1,2,3" line.long 0xC "RGX_CR_ISP_DBIAS_BASE_1,RGX_CR_ISP_DBIAS_BASE_1" hexmask.long.tbyte 0xC 8.--31. 1. "Reserved_40,Reserved_40" newline hexmask.long.byte 0xC 0.--7. 1. "ADDR,1TB range 32-bit aligned base address" line.long 0x10 "RGX_CR_ISP_OCLQRY_BASE_0,Base address for occlusion query counter values. For multiple phantom system. base address could be set differently and driver needs to sum up the result from different phantoms which have same occlusion query index." hexmask.long 0x10 4.--31. 1. "ADDR,1TB range 128-bit aligned base address" newline hexmask.long.byte 0x10 0.--3. 1. "Reserved_0,Reserved_0" line.long 0x14 "RGX_CR_ISP_OCLQRY_BASE_1,Base address for occlusion query counter values. For multiple phantom system. base address could be set differently and driver needs to sum up the result from different phantoms which have same occlusion query index." hexmask.long.tbyte 0x14 8.--31. 1. "Reserved_40,Reserved_40" newline hexmask.long.byte 0x14 0.--7. 1. "ADDR,1TB range 128-bit aligned base address" line.long 0x18 "RGX_CR_ISP_PIXEL_BASE_0,Base address for control stream and primitive blocks." hexmask.long 0x18 0.--31. 1. "Reserved_0,Reserved_0" line.long 0x1C "RGX_CR_ISP_PIXEL_BASE_1,Base address for control stream and primitive blocks." hexmask.long.tbyte 0x1C 8.--31. 1. "Reserved_40,Reserved_40" newline hexmask.long.byte 0x1C 2.--7. 1. "ADDR,1TB range 16GB granularity" newline bitfld.long 0x1C 0.--1. "Reserved_0,Reserved_0" "0,1,2,3" line.long 0x20 "RGX_CR_ISP_ZLS_PIXELS_0,screen size in pixel numbers for ZLS." bitfld.long 0x20 30.--31. "Reserved_30,Reserved_30" "0,1,2,3" newline hexmask.long.word 0x20 15.--29. 1. "Y,Display width of Y in pixels minus one. 0x000 1 pixel 0x001 2 pixels ... 0x7FFF 1024*32 pixels. Subtile only supports for non-msaa mode depth load/store so For non-msaa mode if framebuffer compression or separate mask or separate stencil is.." newline hexmask.long.word 0x20 0.--14. 1. "X,Display width of X in pixels minus one. 0x000 1 pixel 0x001 2 pixels ... 0x7FFF 1024*32 pixels. Subtile only supports for non-msaa mode depth load/store so For non-msaa mode if framebuffer compression or separate mask or separate stencil is.." line.long 0x24 "RGX_CR_ISP_ZLS_PIXELS_1,screen size in pixel numbers for ZLS." hexmask.long 0x24 0.--31. 1. "Reserved_30,Reserved_30" line.long 0x28 "RGX_CR_ISP_CTL2_0,RGX_CR_ISP_CTL2_0" hexmask.long 0x28 5.--31. 1. "Reserved_5,Reserved_5" newline hexmask.long.byte 0x28 0.--4. 1. "DEPTHBUFFERS_IN_USE,Specifies the number of depth buffers to use" line.long 0x2C "RGX_CR_ISP_CTL2_1,RGX_CR_ISP_CTL2_1" hexmask.long 0x2C 0.--31. 1. "Reserved_5,Reserved_5" wgroup.long 0x1000++0x7 line.long 0x0 "RGX_CR_ISP_START_CONTEXT_STORE_0,Writing '1' to this register initiates a 3D context store" hexmask.long 0x0 1.--31. 1. "Reserved_1,Reserved_1" newline bitfld.long 0x0 0. "PULSE,PULSE" "0,1" line.long 0x4 "RGX_CR_ISP_START_CONTEXT_STORE_1,Writing '1' to this register initiates a 3D context store" hexmask.long 0x4 0.--31. 1. "Reserved_1,Reserved_1" rgroup.long 0x1008++0x7 line.long 0x0 "RGX_CR_ISP_STORE0_0,ISP context store register" bitfld.long 0x0 31. "Reserved_31,Reserved_31" "0,1" newline bitfld.long 0x0 30. "ACTIVE,ACTIVE" "0,1" newline bitfld.long 0x0 29. "EOR,EOR" "0,1" newline bitfld.long 0x0 28. "TILE_LAST,TILE_LAST" "0,1" newline hexmask.long.byte 0x0 24.--27. 1. "MT,MT" newline bitfld.long 0x0 22.--23. "Reserved_22,Reserved_22" "0,1,2,3" newline hexmask.long.word 0x0 12.--21. 1. "TILE_X,TILE_X" newline bitfld.long 0x0 10.--11. "Reserved_10,Reserved_10" "0,1,2,3" newline hexmask.long.word 0x0 0.--9. 1. "TILE_Y,TILE_Y" line.long 0x4 "RGX_CR_ISP_STORE0_1,ISP context store register" hexmask.long 0x4 0.--31. 1. "Reserved_31,Reserved_31" group.long 0x1020++0x7 line.long 0x0 "RGX_CR_ISP_RESUME0_0,ISP context resume register" hexmask.long.word 0x0 22.--31. 1. "Reserved_22,Reserved_22" newline hexmask.long.word 0x0 12.--21. 1. "TILE_X,TILE_X" newline bitfld.long 0x0 10.--11. "Reserved_10,Reserved_10" "0,1,2,3" newline hexmask.long.word 0x0 0.--9. 1. "TILE_Y,TILE_Y" line.long 0x4 "RGX_CR_ISP_RESUME0_1,ISP context resume register" hexmask.long 0x4 0.--31. 1. "Reserved_22,Reserved_22" rgroup.long 0x1038++0xF line.long 0x0 "RGX_CR_ISP_STATUS_0,ISP status registers" hexmask.long 0x0 3.--31. 1. "Reserved_3,Reserved_3" newline bitfld.long 0x0 2. "SPLIT_MAX,Split Render Maximum Threshold has been Exceeded" "0,1" newline bitfld.long 0x0 1. "ACTIVE,ISP is Active first tile in the render has been assigned" "0,1" newline bitfld.long 0x0 0. "EOR,ISP has assigned the last tile in the render" "0,1" line.long 0x4 "RGX_CR_ISP_STATUS_1,ISP status registers" hexmask.long 0x4 0.--31. 1. "Reserved_3,Reserved_3" line.long 0x8 "RGX_CR_RAST_IDLE_0,RGX_CR_RAST_IDLE_0" hexmask.long 0x8 5.--31. 1. "Reserved_5,Reserved_5" newline bitfld.long 0x8 4. "TFPU,TFPU Module IDLE" "0,1" newline bitfld.long 0x8 3. "TPF,TPF Module IDLE" "0,1" newline bitfld.long 0x8 2. "IFPU,IFPU Module IDLE" "0,1" newline bitfld.long 0x8 1. "ISP,ISP Module IDLE" "0,1" newline bitfld.long 0x8 0. "IPF,IPF Module IDLE" "0,1" line.long 0xC "RGX_CR_RAST_IDLE_1,RGX_CR_RAST_IDLE_1" hexmask.long 0xC 0.--31. 1. "Reserved_5,Reserved_5" repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) rgroup.long ($2+0x1048)++0x3 line.long 0x0 "RGX_CR_ISP_PWR_NUM_$1,RGX_CR_ISP_PWR_NUM_0" hexmask.long 0x0 0.--31. 1. "PIXELS_PROCESS,Number of depth tested pixels(non-MSAA) or samples(MSAA) processed" repeat.end repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) rgroup.long ($2+0x1058)++0x3 line.long 0x0 "RGX_CR_TFPU_PWR_NUM_$1,RGX_CR_TFPU_PWR_NUM_0" hexmask.long 0x0 0.--31. 1. "PRIMITIVES_PROCESSED,Number of primitives processed" repeat.end repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) group.long ($2+0x11D0)++0x3 line.long 0x0 "RGX_CR_ISP_MERGE_LOWER_X_$1,Used by the IFPU to generate the angle vectors used for triangle merging" hexmask.long 0x0 0.--31. 1. "VALUE,tan(15)/16k screen size" repeat.end repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) group.long ($2+0x11D8)++0x3 line.long 0x0 "RGX_CR_ISP_MERGE_LOWER_Y_$1,Used by the IFPU to generate the angle vectors used for triangle merging" hexmask.long 0x0 0.--31. 1. "VALUE,tan(15)/16k screen size" repeat.end repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) group.long ($2+0x11E0)++0x3 line.long 0x0 "RGX_CR_ISP_MERGE_UPPER_X_$1,RGX_CR_ISP_MERGE_UPPER_X_0" hexmask.long 0x0 0.--31. 1. "VALUE,tan(60)/16k screen size" repeat.end repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) group.long ($2+0x11E8)++0x3 line.long 0x0 "RGX_CR_ISP_MERGE_UPPER_Y_$1,Used by the IFPU to generate the angle vectors used for triangle merging" hexmask.long 0x0 0.--31. 1. "VALUE,tan(60)/16k screen size" repeat.end repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) group.long ($2+0x11F0)++0x3 line.long 0x0 "RGX_CR_ISP_MERGE_SCALE_X_$1,RGX_CR_ISP_MERGE_SCALE_X_0" hexmask.long 0x0 0.--31. 1. "VALUE,16 * default screen size of 16k" repeat.end repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) group.long ($2+0x11F8)++0x3 line.long 0x0 "RGX_CR_ISP_MERGE_SCALE_Y_$1,Used by the IFPU to generate the angle vectors used for triangle merging" hexmask.long 0x0 0.--31. 1. "VALUE,16 * default screen size of 16k" repeat.end group.long 0x1200++0x57 line.long 0x0 "RGX_CR_BIF_CAT_BASE0_0,RGX_CR_BIF_CAT_BASE0_0" hexmask.long.tbyte 0x0 12.--31. 1. "ADDR,ADDR" newline hexmask.long.word 0x0 0.--11. 1. "Reserved_0,Reserved_0" line.long 0x4 "RGX_CR_BIF_CAT_BASE0_1,RGX_CR_BIF_CAT_BASE0_1" hexmask.long.tbyte 0x4 8.--31. 1. "Reserved_40,Reserved_40" newline hexmask.long.byte 0x4 0.--7. 1. "ADDR,ADDR" line.long 0x8 "RGX_CR_BIF_CAT_BASE1_0,RGX_CR_BIF_CAT_BASE1_0" hexmask.long.tbyte 0x8 12.--31. 1. "ADDR,ADDR" newline hexmask.long.word 0x8 0.--11. 1. "Reserved_0,Reserved_0" line.long 0xC "RGX_CR_BIF_CAT_BASE1_1,RGX_CR_BIF_CAT_BASE1_1" hexmask.long.tbyte 0xC 8.--31. 1. "Reserved_40,Reserved_40" newline hexmask.long.byte 0xC 0.--7. 1. "ADDR,ADDR" line.long 0x10 "RGX_CR_BIF_CAT_BASE2_0,RGX_CR_BIF_CAT_BASE2_0" hexmask.long.tbyte 0x10 12.--31. 1. "ADDR,ADDR" newline hexmask.long.word 0x10 0.--11. 1. "Reserved_0,Reserved_0" line.long 0x14 "RGX_CR_BIF_CAT_BASE2_1,RGX_CR_BIF_CAT_BASE2_1" hexmask.long.tbyte 0x14 8.--31. 1. "Reserved_40,Reserved_40" newline hexmask.long.byte 0x14 0.--7. 1. "ADDR,ADDR" line.long 0x18 "RGX_CR_BIF_CAT_BASE3_0,RGX_CR_BIF_CAT_BASE3_0" hexmask.long.tbyte 0x18 12.--31. 1. "ADDR,ADDR" newline hexmask.long.word 0x18 0.--11. 1. "Reserved_0,Reserved_0" line.long 0x1C "RGX_CR_BIF_CAT_BASE3_1,RGX_CR_BIF_CAT_BASE3_1" hexmask.long.tbyte 0x1C 8.--31. 1. "Reserved_40,Reserved_40" newline hexmask.long.byte 0x1C 0.--7. 1. "ADDR,ADDR" line.long 0x20 "RGX_CR_BIF_CAT_BASE4_0,RGX_CR_BIF_CAT_BASE4_0" hexmask.long.tbyte 0x20 12.--31. 1. "ADDR,ADDR" newline hexmask.long.word 0x20 0.--11. 1. "Reserved_0,Reserved_0" line.long 0x24 "RGX_CR_BIF_CAT_BASE4_1,RGX_CR_BIF_CAT_BASE4_1" hexmask.long.tbyte 0x24 8.--31. 1. "Reserved_40,Reserved_40" newline hexmask.long.byte 0x24 0.--7. 1. "ADDR,ADDR" line.long 0x28 "RGX_CR_BIF_CAT_BASE5_0,RGX_CR_BIF_CAT_BASE5_0" hexmask.long.tbyte 0x28 12.--31. 1. "ADDR,ADDR" newline hexmask.long.word 0x28 0.--11. 1. "Reserved_0,Reserved_0" line.long 0x2C "RGX_CR_BIF_CAT_BASE5_1,RGX_CR_BIF_CAT_BASE5_1" hexmask.long.tbyte 0x2C 8.--31. 1. "Reserved_40,Reserved_40" newline hexmask.long.byte 0x2C 0.--7. 1. "ADDR,ADDR" line.long 0x30 "RGX_CR_BIF_CAT_BASE6_0,RGX_CR_BIF_CAT_BASE6_0" hexmask.long.tbyte 0x30 12.--31. 1. "ADDR,ADDR" newline hexmask.long.word 0x30 0.--11. 1. "Reserved_0,Reserved_0" line.long 0x34 "RGX_CR_BIF_CAT_BASE6_1,RGX_CR_BIF_CAT_BASE6_1" hexmask.long.tbyte 0x34 8.--31. 1. "Reserved_40,Reserved_40" newline hexmask.long.byte 0x34 0.--7. 1. "ADDR,ADDR" line.long 0x38 "RGX_CR_BIF_CAT_BASE7_0,RGX_CR_BIF_CAT_BASE7_0" hexmask.long.tbyte 0x38 12.--31. 1. "ADDR,ADDR" newline hexmask.long.word 0x38 0.--11. 1. "Reserved_0,Reserved_0" line.long 0x3C "RGX_CR_BIF_CAT_BASE7_1,RGX_CR_BIF_CAT_BASE7_1" hexmask.long.tbyte 0x3C 8.--31. 1. "Reserved_40,Reserved_40" newline hexmask.long.byte 0x3C 0.--7. 1. "ADDR,ADDR" line.long 0x40 "RGX_CR_BIF_CAT_BASE_INDEX_0,Index registers per data master. Byte aligned fields to allow byte-masked access" hexmask.long.word 0x40 22.--31. 1. "Reserved_22,Reserved_22" newline bitfld.long 0x40 19.--21. "TDM,Catalogue Base number for TDM data master" "0,1,2,3,4,5,6,7" newline bitfld.long 0x40 16.--18. "CDM,Catalogue Base number for CDM data master" "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x40 11.--15. 1. "Reserved_11,Reserved_11" newline bitfld.long 0x40 8.--10. "PIXEL,Catalogue Base number for PIXEL data master" "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x40 3.--7. 1. "Reserved_3,Reserved_3" newline bitfld.long 0x40 0.--2. "TA,Catalogue Base number for TA data master" "0,1,2,3,4,5,6,7" line.long 0x44 "RGX_CR_BIF_CAT_BASE_INDEX_1,Index registers per data master. Byte aligned fields to allow byte-masked access" hexmask.long 0x44 3.--31. 1. "Reserved_35,Reserved_35" newline bitfld.long 0x44 0.--2. "HOST,Catalogue Base number for HOST data master" "0,1,2,3,4,5,6,7" line.long 0x48 "RGX_CR_BIF_PM_CAT_BASE_VCE0_0,PM catalogue base address for VCE context 0" hexmask.long.tbyte 0x48 12.--31. 1. "ADDR,ADDR" newline hexmask.long.word 0x48 2.--11. 1. "Reserved_2,Reserved_2" newline bitfld.long 0x48 1. "WRAP,Indicates address space has been fully allocated" "0,1" newline bitfld.long 0x48 0. "VALID,VALID" "0,1" line.long 0x4C "RGX_CR_BIF_PM_CAT_BASE_VCE0_1,PM catalogue base address for VCE context 0" hexmask.long.byte 0x4C 28.--31. 1. "Reserved_60,Reserved_60" newline hexmask.long.tbyte 0x4C 8.--27. 1. "INIT_PAGE,INIT_PAGE" newline hexmask.long.byte 0x4C 0.--7. 1. "ADDR,ADDR" line.long 0x50 "RGX_CR_BIF_PM_CAT_BASE_TE0_0,PM catalogue base address for TE context 0" hexmask.long.tbyte 0x50 12.--31. 1. "ADDR,ADDR" newline hexmask.long.word 0x50 2.--11. 1. "Reserved_2,Reserved_2" newline bitfld.long 0x50 1. "WRAP,WRAP" "0,1" newline bitfld.long 0x50 0. "VALID,VALID" "0,1" line.long 0x54 "RGX_CR_BIF_PM_CAT_BASE_TE0_1,PM catalogue base address for TE context 0" hexmask.long.byte 0x54 28.--31. 1. "Reserved_60,Reserved_60" newline hexmask.long.tbyte 0x54 8.--27. 1. "INIT_PAGE,INIT_PAGE" newline hexmask.long.byte 0x54 0.--7. 1. "ADDR,ADDR" group.long 0x1260++0x17 line.long 0x0 "RGX_CR_BIF_PM_CAT_BASE_ALIST0_0,PM catalogue base address for ALIST context 0" hexmask.long.tbyte 0x0 12.--31. 1. "ADDR,ADDR" newline hexmask.long.word 0x0 2.--11. 1. "Reserved_2,Reserved_2" newline bitfld.long 0x0 1. "WRAP,WRAP" "0,1" newline bitfld.long 0x0 0. "VALID,VALID" "0,1" line.long 0x4 "RGX_CR_BIF_PM_CAT_BASE_ALIST0_1,PM catalogue base address for ALIST context 0" hexmask.long.byte 0x4 28.--31. 1. "Reserved_60,Reserved_60" newline hexmask.long.tbyte 0x4 8.--27. 1. "INIT_PAGE,INIT_PAGE" newline hexmask.long.byte 0x4 0.--7. 1. "ADDR,ADDR" line.long 0x8 "RGX_CR_BIF_PM_CAT_BASE_VCE1_0,PM catalogue base address for VCE context 1" hexmask.long.tbyte 0x8 12.--31. 1. "ADDR,ADDR" newline hexmask.long.word 0x8 2.--11. 1. "Reserved_2,Reserved_2" newline bitfld.long 0x8 1. "WRAP,WRAP" "0,1" newline bitfld.long 0x8 0. "VALID,VALID" "0,1" line.long 0xC "RGX_CR_BIF_PM_CAT_BASE_VCE1_1,PM catalogue base address for VCE context 1" hexmask.long.byte 0xC 28.--31. 1. "Reserved_60,Reserved_60" newline hexmask.long.tbyte 0xC 8.--27. 1. "INIT_PAGE,INIT_PAGE" newline hexmask.long.byte 0xC 0.--7. 1. "ADDR,ADDR" line.long 0x10 "RGX_CR_BIF_PM_CAT_BASE_TE1_0,PM catalogue base address for TE context 1" hexmask.long.tbyte 0x10 12.--31. 1. "ADDR,ADDR" newline hexmask.long.word 0x10 2.--11. 1. "Reserved_2,Reserved_2" newline bitfld.long 0x10 1. "WRAP,WRAP" "0,1" newline bitfld.long 0x10 0. "VALID,VALID" "0,1" line.long 0x14 "RGX_CR_BIF_PM_CAT_BASE_TE1_1,PM catalogue base address for TE context 1" hexmask.long.byte 0x14 28.--31. 1. "Reserved_60,Reserved_60" newline hexmask.long.tbyte 0x14 8.--27. 1. "INIT_PAGE,INIT_PAGE" newline hexmask.long.byte 0x14 0.--7. 1. "ADDR,ADDR" group.long 0x1280++0x7 line.long 0x0 "RGX_CR_BIF_PM_CAT_BASE_ALIST1_0,PM catalogue base address for ALIST context 1" hexmask.long.tbyte 0x0 12.--31. 1. "ADDR,ADDR" newline hexmask.long.word 0x0 2.--11. 1. "Reserved_2,Reserved_2" newline bitfld.long 0x0 1. "WRAP,WRAP" "0,1" newline bitfld.long 0x0 0. "VALID,VALID" "0,1" line.long 0x4 "RGX_CR_BIF_PM_CAT_BASE_ALIST1_1,PM catalogue base address for ALIST context 1" hexmask.long.byte 0x4 28.--31. 1. "Reserved_60,Reserved_60" newline hexmask.long.tbyte 0x4 8.--27. 1. "INIT_PAGE,INIT_PAGE" newline hexmask.long.byte 0x4 0.--7. 1. "ADDR,ADDR" rgroup.long 0x1288++0x7 line.long 0x0 "RGX_CR_BIF_MMU_ENTRY_STATUS_0,Status of pending entry" hexmask.long.tbyte 0x0 12.--31. 1. "ADDRESS,Virtual 4KB address" newline hexmask.long.byte 0x0 8.--11. 1. "Reserved_8,Reserved_8" newline hexmask.long.byte 0x0 4.--7. 1. "CAT_BASE,Catalogue base address number" newline bitfld.long 0x0 2.--3. "Reserved_2,Reserved_2" "0,1,2,3" newline bitfld.long 0x0 0.--1. "DATA_TYPE,MMU data type '00' = PT '01' = PD '10' = PC" "0,1,2,3" line.long 0x4 "RGX_CR_BIF_MMU_ENTRY_STATUS_1,Status of pending entry" hexmask.long.tbyte 0x4 8.--31. 1. "Reserved_40,Reserved_40" newline hexmask.long.byte 0x4 0.--7. 1. "ADDRESS,Virtual 4KB address" group.long 0x1290++0x7 line.long 0x0 "RGX_CR_BIF_MMU_ENTRY_0,Indicates MMU is waiting on the driver to map an entry" hexmask.long 0x0 2.--31. 1. "Reserved_2,Reserved_2" newline bitfld.long 0x0 1. "ENABLE,When set PENDING will trigger an interrupt back to the host CPU (bypassing the FW)" "0,1" newline bitfld.long 0x0 0. "PENDING,PENDING" "0,1" line.long 0x4 "RGX_CR_BIF_MMU_ENTRY_1,Indicates MMU is waiting on the driver to map an entry" hexmask.long 0x4 0.--31. 1. "Reserved_2,Reserved_2" group.long 0x12A0++0xF line.long 0x0 "RGX_CR_BIF_CTRL_INVAL_0,Invalidation bits allowing BIF/MMU to clear when invalidation complete" hexmask.long 0x0 4.--31. 1. "Reserved_4,Reserved_4" newline bitfld.long 0x0 3. "TLB1,TLB1" "0,1" newline bitfld.long 0x0 2. "PC,PC" "0,1" newline bitfld.long 0x0 1. "PD,PD" "0,1" newline bitfld.long 0x0 0. "PT,PT" "0,1" line.long 0x4 "RGX_CR_BIF_CTRL_INVAL_1,Invalidation bits allowing BIF/MMU to clear when invalidation complete" hexmask.long 0x4 0.--31. 1. "Reserved_4,Reserved_4" line.long 0x8 "RGX_CR_BIF_CTRL_0,Miscellaneous controls" hexmask.long.tbyte 0x8 9.--31. 1. "Reserved_9,Reserved_9" newline bitfld.long 0x8 8. "PAUSE_MMU_BIF4,Stalls BIF4 input to MMU" "0,1" newline bitfld.long 0x8 7. "ENABLE_MMU_QUEUE_BYPASS,Enables bypassing of the MMU queue for cache hits" "0,1" newline bitfld.long 0x8 6. "ENABLE_MMU_AUTO_PREFETCH,Enables automatic prefetching based on incoming requests" "0,1" newline bitfld.long 0x8 5. "PAUSE_MMU_BIF3,Stalls BIF3 input to MMU" "0,1" newline bitfld.long 0x8 4. "PAUSE_MMU_BIF2,Stalls BIF2 input to MMU" "0,1" newline bitfld.long 0x8 3. "PAUSE_BIF1,Stalls BIF1 pipeline" "0,1" newline bitfld.long 0x8 2. "PAUSE_MMU_PM,Stalls PM input to MMU" "0,1" newline bitfld.long 0x8 1. "PAUSE_MMU_BIF1,Stalls BIF1 input to MMU" "0,1" newline bitfld.long 0x8 0. "PAUSE_MMU_BIF0,Stalls BIF0 input to MMU" "0,1" line.long 0xC "RGX_CR_BIF_CTRL_1,Miscellaneous controls" hexmask.long 0xC 0.--31. 1. "Reserved_9,Reserved_9" rgroup.long 0x12B0++0x27 line.long 0x0 "RGX_CR_BIF_FAULT_BANK0_MMU_STATUS_0,Indicates a fault has occurred on bank 0 and provides details of fault" hexmask.long.word 0x0 16.--31. 1. "Reserved_16,Reserved_16" newline hexmask.long.byte 0x0 12.--15. 1. "CAT_BASE,Catalogue base address number" newline bitfld.long 0x0 11. "Reserved_11,Reserved_11" "0,1" newline bitfld.long 0x0 8.--10. "PAGE_SIZE,Page size" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 7. "Reserved_7,Reserved_7" "0,1" newline bitfld.long 0x0 5.--6. "DATA_TYPE,MMU data type that was invalid (on valid fault)" "0,1,2,3" newline bitfld.long 0x0 4. "FAULT_RO,Indicates read-only fault('1') or valid fault('0')" "0,1" newline bitfld.long 0x0 3. "Reserved_3,Reserved_3" "0,1" newline bitfld.long 0x0 2. "FAULT_PM_META_RO,Indicates pm/meta protected region fault" "0,1" newline bitfld.long 0x0 1. "Reserved_1,Reserved_1" "0,1" newline bitfld.long 0x0 0. "FAULT,Indicates a fault has occured" "0,1" line.long 0x4 "RGX_CR_BIF_FAULT_BANK0_MMU_STATUS_1,Indicates a fault has occurred on bank 0 and provides details of fault" hexmask.long 0x4 0.--31. 1. "Reserved_16,Reserved_16" line.long 0x8 "RGX_CR_BIF_FAULT_BANK0_REQ_STATUS_0,Provides details of the request that faulted on bank 0" hexmask.long 0x8 4.--31. 1. "ADDRESS,ADDRESS" newline hexmask.long.byte 0x8 0.--3. 1. "Reserved_0,Reserved_0" line.long 0xC "RGX_CR_BIF_FAULT_BANK0_REQ_STATUS_1,Provides details of the request that faulted on bank 0" hexmask.long.word 0xC 21.--31. 1. "Reserved_53,Reserved_53" newline bitfld.long 0xC 20. "RNW,RNW" "0,1" newline hexmask.long.byte 0xC 14.--19. 1. "TAG_SB,TAG_SB" newline hexmask.long.byte 0xC 8.--13. 1. "TAG_ID,TAG_ID" newline hexmask.long.byte 0xC 0.--7. 1. "ADDRESS,ADDRESS" line.long 0x10 "RGX_CR_BIF_FAULT_BANK1_MMU_STATUS_0,Indicates a fault has occurred on bank 1 and provides details of fault" hexmask.long.word 0x10 16.--31. 1. "Reserved_16,Reserved_16" newline hexmask.long.byte 0x10 12.--15. 1. "CAT_BASE,Catalogue base address number" newline bitfld.long 0x10 11. "Reserved_11,Reserved_11" "0,1" newline bitfld.long 0x10 8.--10. "PAGE_SIZE,Page size" "0,1,2,3,4,5,6,7" newline bitfld.long 0x10 7. "Reserved_7,Reserved_7" "0,1" newline bitfld.long 0x10 5.--6. "DATA_TYPE,MMU data type that was invalid (on valid fault)" "0,1,2,3" newline bitfld.long 0x10 4. "FAULT_RO,Indicates read-only fault('1') of valid fault('0')" "0,1" newline bitfld.long 0x10 3. "Reserved_3,Reserved_3" "0,1" newline bitfld.long 0x10 2. "FAULT_PM_META_RO,Indicates pm/meta protected region fault" "0,1" newline bitfld.long 0x10 1. "Reserved_1,Reserved_1" "0,1" newline bitfld.long 0x10 0. "FAULT,Indicates a fault has occured" "0,1" line.long 0x14 "RGX_CR_BIF_FAULT_BANK1_MMU_STATUS_1,Indicates a fault has occurred on bank 1 and provides details of fault" hexmask.long 0x14 0.--31. 1. "Reserved_16,Reserved_16" line.long 0x18 "RGX_CR_BIF_FAULT_BANK1_REQ_STATUS_0,Provides details of the request that faulted on bank 1" hexmask.long 0x18 4.--31. 1. "ADDRESS,ADDRESS" newline hexmask.long.byte 0x18 0.--3. 1. "Reserved_0,Reserved_0" line.long 0x1C "RGX_CR_BIF_FAULT_BANK1_REQ_STATUS_1,Provides details of the request that faulted on bank 1" hexmask.long.word 0x1C 19.--31. 1. "Reserved_51,Reserved_51" newline bitfld.long 0x1C 18. "RNW,RNW" "0,1" newline hexmask.long.byte 0x1C 12.--17. 1. "TAG_SB,TAG_SB" newline hexmask.long.byte 0x1C 8.--11. 1. "TAG_ID,TAG_ID" newline hexmask.long.byte 0x1C 0.--7. 1. "ADDRESS,ADDRESS" line.long 0x20 "RGX_CR_BIF_MMU_STATUS_0,General MMU status" bitfld.long 0x20 29.--31. "Reserved_29,Reserved_29" "0,1,2,3,4,5,6,7" newline bitfld.long 0x20 28. "PM_FAULT,PM_FAULT" "0,1" newline hexmask.long.byte 0x20 20.--27. 1. "PC_DATA,PC_DATA" newline hexmask.long.byte 0x20 12.--19. 1. "PD_DATA,PD_DATA" newline hexmask.long.byte 0x20 4.--11. 1. "PT_DATA,PT_DATA" newline bitfld.long 0x20 3. "Reserved_3,Reserved_3" "0,1" newline bitfld.long 0x20 2. "STALLED,STALLED" "0,1" newline bitfld.long 0x20 1. "PAUSED,PAUSED" "0,1" newline bitfld.long 0x20 0. "BUSY,BUSY" "0,1" line.long 0x24 "RGX_CR_BIF_MMU_STATUS_1,General MMU status" hexmask.long 0x24 0.--31. 1. "Reserved_29,Reserved_29" group.long 0x12D8++0x3F line.long 0x0 "RGX_CR_BIF_TILING_CFG0_0,This register defines 8 RANGEs in which BIF Tiling can be configured. Each RANGE is given a Stride and a MIN and MAX 4KB aligned address to define the region of Address Space to be tiled. The BIF_TILING_CAT_BASE_INDEX register is.." hexmask.long.byte 0x0 28.--31. 1. "Reserved_28,Reserved_28" newline hexmask.long 0x0 0.--27. 1. "MIN_ADDRESS,4KB aligned min address for tiling" line.long 0x4 "RGX_CR_BIF_TILING_CFG0_1,This register defines 8 RANGEs in which BIF Tiling can be configured. Each RANGE is given a Stride and a MIN and MAX 4KB aligned address to define the region of Address Space to be tiled. The BIF_TILING_CAT_BASE_INDEX register is.." bitfld.long 0x4 29.--31. "XSTRIDE,defines x tile stride. The value in the register is equal to log2(number of tiles in x)-1 e. g. a value of 0 gives 2 x-tiles and a value of 3 gives 16 x-tiles" "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 28. "ENABLE,enables tiling range" "0,1" newline hexmask.long 0x4 0.--27. 1. "MAX_ADDRESS,4KB aligned max address for tiling" line.long 0x8 "RGX_CR_BIF_TILING_CFG1_0,This register defines 8 RANGEs in which BIF Tiling can be configured. Each RANGE is given a Stride and a MIN and MAX 4KB aligned address to define the region of Address Space to be tiled. The BIF_TILING_CAT_BASE_INDEX register is.." hexmask.long.byte 0x8 28.--31. 1. "Reserved_28,Reserved_28" newline hexmask.long 0x8 0.--27. 1. "MIN_ADDRESS,4KB aligned min address for tiling" line.long 0xC "RGX_CR_BIF_TILING_CFG1_1,This register defines 8 RANGEs in which BIF Tiling can be configured. Each RANGE is given a Stride and a MIN and MAX 4KB aligned address to define the region of Address Space to be tiled. The BIF_TILING_CAT_BASE_INDEX register is.." bitfld.long 0xC 29.--31. "XSTRIDE,defines x tile stride. The value in the register is equal to log2(number of tiles in x)-1 e. g. a value of 0 gives 2 x-tiles and a value of 3 gives 16 x-tiles" "0,1,2,3,4,5,6,7" newline bitfld.long 0xC 28. "ENABLE,enables tiling range" "0,1" newline hexmask.long 0xC 0.--27. 1. "MAX_ADDRESS,4KB aligned max address for tiling" line.long 0x10 "RGX_CR_BIF_TILING_CFG2_0,This register defines 8 RANGEs in which BIF Tiling can be configured. Each RANGE is given a Stride and a MIN and MAX 4KB aligned address to define the region of Address Space to be tiled. The BIF_TILING_CAT_BASE_INDEX register is.." hexmask.long.byte 0x10 28.--31. 1. "Reserved_28,Reserved_28" newline hexmask.long 0x10 0.--27. 1. "MIN_ADDRESS,4KB aligned min address for tiling" line.long 0x14 "RGX_CR_BIF_TILING_CFG2_1,This register defines 8 RANGEs in which BIF Tiling can be configured. Each RANGE is given a Stride and a MIN and MAX 4KB aligned address to define the region of Address Space to be tiled. The BIF_TILING_CAT_BASE_INDEX register is.." bitfld.long 0x14 29.--31. "XSTRIDE,defines x tile stride. The value in the register is equal to log2(number of tiles in x)-1 e. g. a value of 0 gives 2 x-tiles and a value of 3 gives 16 x-tiles" "0,1,2,3,4,5,6,7" newline bitfld.long 0x14 28. "ENABLE,enables tiling range" "0,1" newline hexmask.long 0x14 0.--27. 1. "MAX_ADDRESS,4KB aligned max address for tiling" line.long 0x18 "RGX_CR_BIF_TILING_CFG3_0,This register defines 8 RANGEs in which BIF Tiling can be configured. Each RANGE is given a Stride and a MIN and MAX 4KB aligned address to define the region of Address Space to be tiled. The BIF_TILING_CAT_BASE_INDEX register is.." hexmask.long.byte 0x18 28.--31. 1. "Reserved_28,Reserved_28" newline hexmask.long 0x18 0.--27. 1. "MIN_ADDRESS,4KB aligned min address for tiling" line.long 0x1C "RGX_CR_BIF_TILING_CFG3_1,This register defines 8 RANGEs in which BIF Tiling can be configured. Each RANGE is given a Stride and a MIN and MAX 4KB aligned address to define the region of Address Space to be tiled. The BIF_TILING_CAT_BASE_INDEX register is.." bitfld.long 0x1C 29.--31. "XSTRIDE,defines x tile stride. The value in the register is equal to log2(number of tiles in x)-1 e. g. a value of 0 gives 2 x-tiles and a value of 3 gives 16 x-tiles" "0,1,2,3,4,5,6,7" newline bitfld.long 0x1C 28. "ENABLE,enables tiling range" "0,1" newline hexmask.long 0x1C 0.--27. 1. "MAX_ADDRESS,4KB aligned max address for tiling" line.long 0x20 "RGX_CR_BIF_TILING_CFG4_0,This register defines 8 RANGEs in which BIF Tiling can be configured. Each RANGE is given a Stride and a MIN and MAX 4KB aligned address to define the region of Address Space to be tiled. The BIF_TILING_CAT_BASE_INDEX register is.." hexmask.long.byte 0x20 28.--31. 1. "Reserved_28,Reserved_28" newline hexmask.long 0x20 0.--27. 1. "MIN_ADDRESS,4KB aligned min address for tiling" line.long 0x24 "RGX_CR_BIF_TILING_CFG4_1,This register defines 8 RANGEs in which BIF Tiling can be configured. Each RANGE is given a Stride and a MIN and MAX 4KB aligned address to define the region of Address Space to be tiled. The BIF_TILING_CAT_BASE_INDEX register is.." bitfld.long 0x24 29.--31. "XSTRIDE,defines x tile stride. The value in the register is equal to log2(number of tiles in x)-1 e. g. a value of 0 gives 2 x-tiles and a value of 3 gives 16 x-tiles" "0,1,2,3,4,5,6,7" newline bitfld.long 0x24 28. "ENABLE,enables tiling range" "0,1" newline hexmask.long 0x24 0.--27. 1. "MAX_ADDRESS,4KB aligned max address for tiling" line.long 0x28 "RGX_CR_BIF_TILING_CFG5_0,This register defines 8 RANGEs in which BIF Tiling can be configured. Each RANGE is given a Stride and a MIN and MAX 4KB aligned address to define the region of Address Space to be tiled. The BIF_TILING_CAT_BASE_INDEX register is.." hexmask.long.byte 0x28 28.--31. 1. "Reserved_28,Reserved_28" newline hexmask.long 0x28 0.--27. 1. "MIN_ADDRESS,4KB aligned min address for tiling" line.long 0x2C "RGX_CR_BIF_TILING_CFG5_1,This register defines 8 RANGEs in which BIF Tiling can be configured. Each RANGE is given a Stride and a MIN and MAX 4KB aligned address to define the region of Address Space to be tiled. The BIF_TILING_CAT_BASE_INDEX register is.." bitfld.long 0x2C 29.--31. "XSTRIDE,defines x tile stride. The value in the register is equal to log2(number of tiles in x)-1 e. g. a value of 0 gives 2 x-tiles and a value of 3 gives 16 x-tiles" "0,1,2,3,4,5,6,7" newline bitfld.long 0x2C 28. "ENABLE,enables tiling range" "0,1" newline hexmask.long 0x2C 0.--27. 1. "MAX_ADDRESS,4KB aligned max address for tiling" line.long 0x30 "RGX_CR_BIF_TILING_CFG6_0,This register defines 8 RANGEs in which BIF Tiling can be configured. Each RANGE is given a Stride and a MIN and MAX 4KB aligned address to define the region of Address Space to be tiled. The BIF_TILING_CAT_BASE_INDEX register is.." hexmask.long.byte 0x30 28.--31. 1. "Reserved_28,Reserved_28" newline hexmask.long 0x30 0.--27. 1. "MIN_ADDRESS,4KB aligned min address for tiling" line.long 0x34 "RGX_CR_BIF_TILING_CFG6_1,This register defines 8 RANGEs in which BIF Tiling can be configured. Each RANGE is given a Stride and a MIN and MAX 4KB aligned address to define the region of Address Space to be tiled. The BIF_TILING_CAT_BASE_INDEX register is.." bitfld.long 0x34 29.--31. "XSTRIDE,defines x tile stride. The value in the register is equal to log2(number of tiles in x)-1 e. g. a value of 0 gives 2 x-tiles and a value of 3 gives 16 x-tiles" "0,1,2,3,4,5,6,7" newline bitfld.long 0x34 28. "ENABLE,enables tiling range" "0,1" newline hexmask.long 0x34 0.--27. 1. "MAX_ADDRESS,4KB aligned max address for tiling" line.long 0x38 "RGX_CR_BIF_TILING_CFG7_0,This register defines 8 RANGEs in which BIF Tiling can be configured. Each RANGE is given a Stride and a MIN and MAX 4KB aligned address to define the region of Address Space to be tiled. The BIF_TILING_CAT_BASE_INDEX register is.." hexmask.long.byte 0x38 28.--31. 1. "Reserved_28,Reserved_28" newline hexmask.long 0x38 0.--27. 1. "MIN_ADDRESS,4KB aligned min address for tiling" line.long 0x3C "RGX_CR_BIF_TILING_CFG7_1,This register defines 8 RANGEs in which BIF Tiling can be configured. Each RANGE is given a Stride and a MIN and MAX 4KB aligned address to define the region of Address Space to be tiled. The BIF_TILING_CAT_BASE_INDEX register is.." bitfld.long 0x3C 29.--31. "XSTRIDE,defines x tile stride. The value in the register is equal to log2(number of tiles in x)-1 e. g. a value of 0 gives 2 x-tiles and a value of 3 gives 16 x-tiles" "0,1,2,3,4,5,6,7" newline bitfld.long 0x3C 28. "ENABLE,enables tiling range" "0,1" newline hexmask.long 0x3C 0.--27. 1. "MAX_ADDRESS,4KB aligned max address for tiling" repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) group.long ($2+0x1318)++0x3 line.long 0x0 "RGX_CR_BIF_TILING_CAT_BASE_INDEX_$1,This register defines the Catalogue Base Index applying to each tiling configuration register. An input address passing the RANGE test is also qualified against the RANGE INDEX before Tiling can proceed." hexmask.long.byte 0x0 27.--31. 1. "Reserved_27,Reserved_27" newline bitfld.long 0x0 24.--26. "RANGE3,RANGE3" "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x0 19.--23. 1. "Reserved_19,Reserved_19" newline bitfld.long 0x0 16.--18. "RANGE2,RANGE2" "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x0 11.--15. 1. "Reserved_11,Reserved_11" newline bitfld.long 0x0 8.--10. "RANGE1,RANGE1" "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x0 3.--7. 1. "Reserved_3,Reserved_3" newline bitfld.long 0x0 0.--2. "RANGE0,RANGE0" "0,1,2,3,4,5,6,7" repeat.end rgroup.long 0x1320++0x1F line.long 0x0 "RGX_CR_BIF_READS_EXT_STATUS_0,Outstanding read data external to BIF for BIF128 and MMU" hexmask.long.word 0x0 23.--31. 1. "Reserved_23,Reserved_23" newline hexmask.long.byte 0x0 16.--22. 1. "MMU,MMU" newline hexmask.long.word 0x0 0.--15. 1. "BANK1,BANK1" line.long 0x4 "RGX_CR_BIF_READS_EXT_STATUS_1,Outstanding read data external to BIF for BIF128 and MMU" hexmask.long 0x4 0.--31. 1. "Reserved_23,Reserved_23" line.long 0x8 "RGX_CR_BIF_READS_INT_STATUS_0,Outstanding 256-bit read data in return data FIFO for BIF128 and MMU" hexmask.long.word 0x8 23.--31. 1. "Reserved_23,Reserved_23" newline hexmask.long.byte 0x8 16.--22. 1. "MMU,MMU" newline hexmask.long.word 0x8 0.--15. 1. "BANK1,BANK1" line.long 0xC "RGX_CR_BIF_READS_INT_STATUS_1,Outstanding 256-bit read data in return data FIFO for BIF128 and MMU" hexmask.long 0xC 0.--31. 1. "Reserved_23,Reserved_23" line.long 0x10 "RGX_CR_BIFPM_READS_INT_STATUS_0,Outstanding 256-bit read data in return data FIFO for BIF256" hexmask.long.word 0x10 16.--31. 1. "Reserved_16,Reserved_16" newline hexmask.long.word 0x10 0.--15. 1. "BANK0,BANK0" line.long 0x14 "RGX_CR_BIFPM_READS_INT_STATUS_1,Outstanding 256-bit read data in return data FIFO for BIF256" hexmask.long 0x14 0.--31. 1. "Reserved_16,Reserved_16" line.long 0x18 "RGX_CR_BIFPM_READS_EXT_STATUS_0,Outstanding 256-bit read data external to BIF for BIF256" hexmask.long.word 0x18 16.--31. 1. "Reserved_16,Reserved_16" newline hexmask.long.word 0x18 0.--15. 1. "BANK0,BANK0" line.long 0x1C "RGX_CR_BIFPM_READS_EXT_STATUS_1,Outstanding 256-bit read data external to BIF for BIF256" hexmask.long 0x1C 0.--31. 1. "Reserved_16,Reserved_16" group.long 0x1340++0xF line.long 0x0 "RGX_CR_BIFPM_CTRL_0,Miscellaneous controls" hexmask.long 0x0 2.--31. 1. "Reserved_2,Reserved_2" newline bitfld.long 0x0 1. "ENABLE_SLC_STALLING,Enables BIF to stall returns from SLC so that requests can be made even when there is no space in the BIF return buffer (only when no chance of lockup)" "0,1" newline bitfld.long 0x0 0. "PAUSE_BIF0,Stalls BIF0 pipeline" "0,1" line.long 0x4 "RGX_CR_BIFPM_CTRL_1,Miscellaneous controls" hexmask.long 0x4 0.--31. 1. "Reserved_2,Reserved_2" line.long 0x8 "RGX_CR_BIFPM_CTRL_INVAL_0,Invalidation bits allowing BIF to clear when invalidation complete" hexmask.long 0x8 1.--31. 1. "Reserved_1,Reserved_1" newline bitfld.long 0x8 0. "TLB0,TLB0" "0,1" line.long 0xC "RGX_CR_BIFPM_CTRL_INVAL_1,Invalidation bits allowing BIF to clear when invalidation complete" hexmask.long 0xC 0.--31. 1. "Reserved_1,Reserved_1" rgroup.long 0x1350++0xF line.long 0x0 "RGX_CR_BIFPM_STATUS_MMU_0,Outstanding MMU requests from BIF0" hexmask.long.tbyte 0x0 8.--31. 1. "Reserved_8,Reserved_8" newline hexmask.long.byte 0x0 0.--7. 1. "REQUESTS,REQUESTS" line.long 0x4 "RGX_CR_BIFPM_STATUS_MMU_1,Outstanding MMU requests from BIF0" hexmask.long 0x4 0.--31. 1. "Reserved_8,Reserved_8" line.long 0x8 "RGX_CR_BIF_STATUS_MMU_0,Outstanding MMU requests from BIF1" hexmask.long.tbyte 0x8 8.--31. 1. "Reserved_8,Reserved_8" newline hexmask.long.byte 0x8 0.--7. 1. "REQUESTS,REQUESTS" line.long 0xC "RGX_CR_BIF_STATUS_MMU_1,Outstanding MMU requests from BIF1" hexmask.long 0xC 0.--31. 1. "Reserved_8,Reserved_8" group.long 0x1360++0x7 line.long 0x0 "RGX_CR_BIF_TILING_0,Sets tiling mode between 256byte x 16 rows (0) and 512byte x 8 rows (1)" hexmask.long 0x0 1.--31. 1. "Reserved_1,Reserved_1" newline bitfld.long 0x0 0. "MODE,MODE" "0,1" line.long 0x4 "RGX_CR_BIF_TILING_1,Sets tiling mode between 256byte x 16 rows (0) and 512byte x 8 rows (1)" hexmask.long 0x4 0.--31. 1. "Reserved_1,Reserved_1" repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) rgroup.long ($2+0x1370)++0x3 line.long 0x0 "RGX_CR_BIF_BLACKPEARL_PWR_$1,Power monitoring register" hexmask.long 0x0 0.--31. 1. "NUM_256BIT_TRANS,Number of 256-bit transactions" repeat.end repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) rgroup.long ($2+0x1378)++0x3 line.long 0x0 "RGX_CR_BIF_JONES_PWR_$1,Power monitoring register" hexmask.long 0x0 0.--31. 1. "NUM_256BIT_TRANS,Number of 256-bit transactions" repeat.end group.long 0x13E0++0x7 line.long 0x0 "RGX_CR_BIF_FAULT_READ_0,Specifies physical address to read from in the event of a faulting read request from BIF1" hexmask.long 0x0 4.--31. 1. "ADDRESS,ADDRESS" newline hexmask.long.byte 0x0 0.--3. 1. "Reserved_0,Reserved_0" line.long 0x4 "RGX_CR_BIF_FAULT_READ_1,Specifies physical address to read from in the event of a faulting read request from BIF1" hexmask.long.tbyte 0x4 8.--31. 1. "Reserved_40,Reserved_40" newline hexmask.long.byte 0x4 0.--7. 1. "ADDRESS,ADDRESS" repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) rgroup.long ($2+0x13E8)++0x3 line.long 0x0 "RGX_CR_BIF_PWR_$1,Power monitoring register" hexmask.long 0x0 0.--31. 1. "NUM_256BIT_TRANS,Number of 256-bit transactions" repeat.end group.long 0x13F8++0x7 line.long 0x0 "RGX_CR_BIF_MCU_RESERVED_0,Allows driver to change the amount of space in the return data FIFO reserved for the MCU" hexmask.long 0x0 5.--31. 1. "Reserved_5,Reserved_5" newline hexmask.long.byte 0x0 0.--4. 1. "SPACE,Granularity of 8 spaces minimum legal value 0x1" line.long 0x4 "RGX_CR_BIF_MCU_RESERVED_1,Allows driver to change the amount of space in the return data FIFO reserved for the MCU" hexmask.long 0x4 0.--31. 1. "Reserved_5,Reserved_5" rgroup.long 0x1430++0x27 line.long 0x0 "RGX_CR_TEXAS_BIF_FAULT_BANK0_MMU_STATUS_0,Indicates a fault has occurred on bank 0 and provides details of fault" hexmask.long.word 0x0 16.--31. 1. "Reserved_16,Reserved_16" newline hexmask.long.byte 0x0 12.--15. 1. "CAT_BASE,Catalogue base address number" newline bitfld.long 0x0 11. "Reserved_11,Reserved_11" "0,1" newline bitfld.long 0x0 8.--10. "PAGE_SIZE,Page size" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 7. "Reserved_7,Reserved_7" "0,1" newline bitfld.long 0x0 5.--6. "DATA_TYPE,MMU data type that was invalid (on valid fault)" "0,1,2,3" newline bitfld.long 0x0 4. "FAULT_RO,Indicates read-only fault('1') or valid fault('0')" "0,1" newline bitfld.long 0x0 3. "Reserved_3,Reserved_3" "0,1" newline bitfld.long 0x0 2. "FAULT_PM_META_RO,Indicates pm/meta protected region fault" "0,1" newline bitfld.long 0x0 1. "Reserved_1,Reserved_1" "0,1" newline bitfld.long 0x0 0. "FAULT,Indicates a fault has occured" "0,1" line.long 0x4 "RGX_CR_TEXAS_BIF_FAULT_BANK0_MMU_STATUS_1,Indicates a fault has occurred on bank 0 and provides details of fault" hexmask.long 0x4 0.--31. 1. "Reserved_16,Reserved_16" line.long 0x8 "RGX_CR_TEXAS_BIF_FAULT_BANK0_REQ_STATUS_0,Provides details of the request that faulted on bank 0" hexmask.long 0x8 4.--31. 1. "ADDRESS,ADDRESS" newline hexmask.long.byte 0x8 0.--3. 1. "Reserved_0,Reserved_0" line.long 0xC "RGX_CR_TEXAS_BIF_FAULT_BANK0_REQ_STATUS_1,Provides details of the request that faulted on bank 0" hexmask.long.word 0xC 19.--31. 1. "Reserved_51,Reserved_51" newline bitfld.long 0xC 18. "RNW,RNW" "0,1" newline hexmask.long.byte 0xC 12.--17. 1. "TAG_SB,TAG_SB" newline hexmask.long.byte 0xC 8.--11. 1. "TAG_ID,TAG_ID" newline hexmask.long.byte 0xC 0.--7. 1. "ADDRESS,ADDRESS" line.long 0x10 "RGX_CR_TEXAS_BIFPM_READS_INT_STATUS_0,Outstanding 256-bit read data in return data FIFO for BIF256" hexmask.long.word 0x10 16.--31. 1. "Reserved_16,Reserved_16" newline hexmask.long.word 0x10 0.--15. 1. "BANK0,BANK0" line.long 0x14 "RGX_CR_TEXAS_BIFPM_READS_INT_STATUS_1,Outstanding 256-bit read data in return data FIFO for BIF256" hexmask.long 0x14 0.--31. 1. "Reserved_16,Reserved_16" line.long 0x18 "RGX_CR_TEXAS_BIFPM_READS_EXT_STATUS_0,Outstanding 256-bit read data external to BIF for BIF256" hexmask.long.word 0x18 16.--31. 1. "Reserved_16,Reserved_16" newline hexmask.long.word 0x18 0.--15. 1. "BANK0,BANK0" line.long 0x1C "RGX_CR_TEXAS_BIFPM_READS_EXT_STATUS_1,Outstanding 256-bit read data external to BIF for BIF256" hexmask.long 0x1C 0.--31. 1. "Reserved_16,Reserved_16" line.long 0x20 "RGX_CR_TEXAS_BIFPM_STATUS_MMU_0,Outstanding MMU requests from BIF0" hexmask.long.tbyte 0x20 8.--31. 1. "Reserved_8,Reserved_8" newline hexmask.long.byte 0x20 0.--7. 1. "REQUESTS,REQUESTS" line.long 0x24 "RGX_CR_TEXAS_BIFPM_STATUS_MMU_1,Outstanding MMU requests from BIF0" hexmask.long 0x24 0.--31. 1. "Reserved_8,Reserved_8" repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) group.long ($2+0x1460)++0x3 line.long 0x0 "RGX_CR_BIF_OSID0_$1,Defines OSID for each CAT_BASE" hexmask.long.byte 0x0 27.--31. 1. "Reserved_27,Reserved_27" newline bitfld.long 0x0 24.--26. "CBASE3,OSID for CAT BASE 3" "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x0 19.--23. 1. "Reserved_19,Reserved_19" newline bitfld.long 0x0 16.--18. "CBASE2,OSID for CAT BASE 2" "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x0 11.--15. 1. "Reserved_11,Reserved_11" newline bitfld.long 0x0 8.--10. "CBASE1,OSID for CAT BASE 1" "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x0 3.--7. 1. "Reserved_3,Reserved_3" newline bitfld.long 0x0 0.--2. "CBASE0,OSID for CAT BASE 0" "0,1,2,3,4,5,6,7" repeat.end group.long 0x1468++0x7 line.long 0x0 "RGX_CR_BIF_OSID1_0,Defines OSID for each data master" hexmask.long.tbyte 0x0 11.--31. 1. "Reserved_11,Reserved_11" newline bitfld.long 0x0 8.--10. "PM_CTX1,OSID for VCE1 TE1 and ALIST1" "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x0 3.--7. 1. "Reserved_3,Reserved_3" newline bitfld.long 0x0 0.--2. "PM_CTX0,OSID for VCE0 TE0 and ALIST0" "0,1,2,3,4,5,6,7" line.long 0x4 "RGX_CR_BIF_OSID1_1,Defines OSID for each data master" hexmask.long 0x4 0.--31. 1. "Reserved_11,Reserved_11" group.long 0x1500++0x7 line.long 0x0 "RGX_CR_PBE_0,The PBE(Pixel back end) module scales and packs the pixel data before writing to memory. this register contains global control signals." hexmask.long.tbyte 0x0 9.--31. 1. "Reserved_9,Reserved_9" newline bitfld.long 0x0 8. "AA_EDGEOPT_OFF,Switches off the PBE-USE read optimisation during Anti aliasing mode. (This is typically for debug purposes only)" "0,1" newline hexmask.long.byte 0x0 0.--7. 1. "ALPHATHRESHOLD,Alpha threshold used when encoding 1555 format. If the internal 8bit Alpha value exceeds this value then a 1 is written to the top bit of the output otherwise a 0 is written" line.long 0x4 "RGX_CR_PBE_1,The PBE(Pixel back end) module scales and packs the pixel data before writing to memory. this register contains global control signals." hexmask.long 0x4 0.--31. 1. "Reserved_9,Reserved_9" rgroup.long 0x1508++0x7 line.long 0x0 "RGX_CR_PBE_EMIT_STATUS_0,This register indicates if the PixelBE would stall the USE if there were another emit. '0' indicates that the PixelBE would stall the USC. '1' indicates that the PixelBE would not stall the USE." hexmask.long.word 0x0 16.--31. 1. "Reserved_16,Reserved_16" newline bitfld.long 0x0 15. "USC15,Pipe 15 status" "0,1" newline bitfld.long 0x0 14. "USC14,Pipe 14 status" "0,1" newline bitfld.long 0x0 13. "USC13,Pipe 13 status" "0,1" newline bitfld.long 0x0 12. "USC12,Pipe 12 status" "0,1" newline bitfld.long 0x0 11. "USC11,Pipe 11 status" "0,1" newline bitfld.long 0x0 10. "USC10,Pipe 10 status" "0,1" newline bitfld.long 0x0 9. "USC9,Pipe 9 status" "0,1" newline bitfld.long 0x0 8. "USC8,Pipe 8 status" "0,1" newline bitfld.long 0x0 7. "USC7,Pipe 7 status" "0,1" newline bitfld.long 0x0 6. "USC6,Pipe 6 status" "0,1" newline bitfld.long 0x0 5. "USC5,Pipe 5 status" "0,1" newline bitfld.long 0x0 4. "USC4,Pipe 4 status" "0,1" newline bitfld.long 0x0 3. "USC3,Pipe 3 status" "0,1" newline bitfld.long 0x0 2. "USC2,Pipe 2 status" "0,1" newline bitfld.long 0x0 1. "USC1,Pipe 1 status" "0,1" newline bitfld.long 0x0 0. "USC0,Pipe 0 status" "0,1" line.long 0x4 "RGX_CR_PBE_EMIT_STATUS_1,This register indicates if the PixelBE would stall the USE if there were another emit. '0' indicates that the PixelBE would stall the USC. '1' indicates that the PixelBE would not stall the USE." hexmask.long 0x4 0.--31. 1. "Reserved_16,Reserved_16" group.long 0x1510++0x3F line.long 0x0 "RGX_CR_PBE_WORD0_MRT0_0,Pixel Back end State Word 0." bitfld.long 0x0 29.--31. "SWIZ_CHAN3,Swizzle for destination channel 3" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 26.--28. "SWIZ_CHAN2,Swizzle for destination channel 2" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 23.--25. "SWIZ_CHAN1,Swizzle for destination channel 1" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 20.--22. "SWIZ_CHAN0,Swizzle for destination channel 0" "0,1,2,3,4,5,6,7" newline hexmask.long.word 0x0 6.--19. 1. "MINCLIP_X,Min X Clip" newline bitfld.long 0x0 5. "TWOCOMP_GAMMA,Sets the gamma mode for 2 component targets" "0,1" newline bitfld.long 0x0 4. "GAMMA,Gamma enabled" "0,1" newline bitfld.long 0x0 3. "COMPRESSION,Frame buffer Compression enabled" "0,1" newline bitfld.long 0x0 2. "COMPRESS_SIZE,Block size for the compressor used with COMPRESS_SIZE_EXT register bit to define 8x8; 16x4 or 32x2 size COMPRESS_SIZE_EXT COMPRESS_SIZE SIZE 0 0 8x8 0 1 16x4 1 0 32x2 1 1 reserved" "0,1" newline bitfld.long 0x0 1. "COMP_INDIRECT_TABLE,If set indicates to the compressor that an indirect addressing is used otherwise direct addressing" "0,1" newline bitfld.long 0x0 0. "Y_FLIP,Y_FLIP" "0,1" line.long 0x4 "RGX_CR_PBE_WORD0_MRT0_1,Pixel Back end State Word 0." bitfld.long 0x4 30.--31. "X_RSRVD,Not used" "0,1,2,3" newline bitfld.long 0x4 29. "COMPRESS_SIZE_EXT,Extra bit to support 32x2 compression size used with COMPRESS_SIZE register bit to define 8x8; 16x4 or 32x2 size COMPRESS_SIZE_EXT COMPRESS_SIZE SIZE 0 0 8x8 0 1 16x4 1 0 32x2 1 1 reserved" "0,1" newline bitfld.long 0x4 28. "COMP_IADDR_MODE,FBC indirect addressing mode" "0,1" newline bitfld.long 0x4 27. "COMP_COR_ENABLE,Enable FBC correlation" "0,1" newline bitfld.long 0x4 26. "DITHER,Enable dither" "0,1" newline bitfld.long 0x4 25. "TILERELATIVE,Add tile offset" "0,1" newline bitfld.long 0x4 24. "DOWNSCALE,Perform box filter downscale" "0,1" newline hexmask.long.byte 0x4 20.--23. 1. "SIZE_Z,Z Size in pixels [log 2]" newline bitfld.long 0x4 18.--19. "ROTATION,Rotation angle" "0,1,2,3" newline hexmask.long.word 0x4 2.--17. 1. "LINESTRIDE,Linestride in 2 pixel units. 0 == 2. Supports 32KDWORD stride memory write" newline bitfld.long 0x4 0.--1. "MEMLAYOUT,Memory layout" "0,1,2,3" line.long 0x8 "RGX_CR_PBE_WORD0_MRT1_0,Pixel Back end State Word 0." bitfld.long 0x8 29.--31. "SWIZ_CHAN3,Swizzle for destination channel 3" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 26.--28. "SWIZ_CHAN2,Swizzle for destination channel 2" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 23.--25. "SWIZ_CHAN1,Swizzle for destination channel 1" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 20.--22. "SWIZ_CHAN0,Swizzle for destination channel 0" "0,1,2,3,4,5,6,7" newline hexmask.long.word 0x8 6.--19. 1. "MINCLIP_X,Min X Clip" newline bitfld.long 0x8 5. "TWOCOMP_GAMMA,Sets the gamma mode for 2 component targets" "0,1" newline bitfld.long 0x8 4. "GAMMA,Gamma enabled" "0,1" newline bitfld.long 0x8 3. "COMPRESSION,Frame buffer Compression enabled" "0,1" newline bitfld.long 0x8 2. "COMPRESS_SIZE,Block size for the compressor used with COMPRESS_SIZE_EXT register bit to define 8x8; 16x4 or 32x2 size COMPRESS_SIZE_EXT COMPRESS_SIZE SIZE 0 0 8x8 0 1 16x4 1 0 32x2 1 1 reserved" "0,1" newline bitfld.long 0x8 1. "COMP_INDIRECT_TABLE,If set indicates to the compressor that an indirect addressing is used otherwise direct addressing" "0,1" newline bitfld.long 0x8 0. "Y_FLIP,Y_FLIP" "0,1" line.long 0xC "RGX_CR_PBE_WORD0_MRT1_1,Pixel Back end State Word 0." bitfld.long 0xC 30.--31. "X_RSRVD,Not used" "0,1,2,3" newline bitfld.long 0xC 29. "COMPRESS_SIZE_EXT,Extra bit to support 32x2 compression size used with COMPRESS_SIZE register bit to define 8x8; 16x4 or 32x2 size COMPRESS_SIZE_EXT COMPRESS_SIZE SIZE 0 0 8x8 0 1 16x4 1 0 32x2 1 1 reserved" "0,1" newline bitfld.long 0xC 28. "COMP_IADDR_MODE,FBC indirect addressing mode" "0,1" newline bitfld.long 0xC 27. "COMP_COR_ENABLE,Enable FBC correlation" "0,1" newline bitfld.long 0xC 26. "DITHER,Enable dither" "0,1" newline bitfld.long 0xC 25. "TILERELATIVE,Add tile offset" "0,1" newline bitfld.long 0xC 24. "DOWNSCALE,Perform box filter downscale" "0,1" newline hexmask.long.byte 0xC 20.--23. 1. "SIZE_Z,Z Size in pixels [log 2]" newline bitfld.long 0xC 18.--19. "ROTATION,Rotation angle" "0,1,2,3" newline hexmask.long.word 0xC 2.--17. 1. "LINESTRIDE,Linestride in 2 pixel units. 0 == 2. Supports 32KDWORD stride memory write" newline bitfld.long 0xC 0.--1. "MEMLAYOUT,Memory layout" "0,1,2,3" line.long 0x10 "RGX_CR_PBE_WORD0_MRT2_0,Pixel Back end State Word 0." bitfld.long 0x10 29.--31. "SWIZ_CHAN3,Swizzle for destination channel 3" "0,1,2,3,4,5,6,7" newline bitfld.long 0x10 26.--28. "SWIZ_CHAN2,Swizzle for destination channel 2" "0,1,2,3,4,5,6,7" newline bitfld.long 0x10 23.--25. "SWIZ_CHAN1,Swizzle for destination channel 1" "0,1,2,3,4,5,6,7" newline bitfld.long 0x10 20.--22. "SWIZ_CHAN0,Swizzle for destination channel 0" "0,1,2,3,4,5,6,7" newline hexmask.long.word 0x10 6.--19. 1. "MINCLIP_X,Min X Clip" newline bitfld.long 0x10 5. "TWOCOMP_GAMMA,Sets the gamma mode for 2 component targets" "0,1" newline bitfld.long 0x10 4. "GAMMA,Gamma enabled" "0,1" newline bitfld.long 0x10 3. "COMPRESSION,Frame buffer Compression enabled" "0,1" newline bitfld.long 0x10 2. "COMPRESS_SIZE,Block size for the compressor used with COMPRESS_SIZE_EXT register bit to define 8x8; 16x4 or 32x2 size COMPRESS_SIZE_EXT COMPRESS_SIZE SIZE 0 0 8x8 0 1 16x4 1 0 32x2 1 1 reserved" "0,1" newline bitfld.long 0x10 1. "COMP_INDIRECT_TABLE,If set indicates to the compressor that an indirect addressing is used otherwise direct addressing" "0,1" newline bitfld.long 0x10 0. "Y_FLIP,Y_FLIP" "0,1" line.long 0x14 "RGX_CR_PBE_WORD0_MRT2_1,Pixel Back end State Word 0." bitfld.long 0x14 30.--31. "X_RSRVD,Not used" "0,1,2,3" newline bitfld.long 0x14 29. "COMPRESS_SIZE_EXT,Extra bit to support 32x2 compression size used with COMPRESS_SIZE register bit to define 8x8; 16x4 or 32x2 size COMPRESS_SIZE_EXT COMPRESS_SIZE SIZE 0 0 8x8 0 1 16x4 1 0 32x2 1 1 reserved" "0,1" newline bitfld.long 0x14 28. "COMP_IADDR_MODE,FBC indirect addressing mode" "0,1" newline bitfld.long 0x14 27. "COMP_COR_ENABLE,Enable FBC correlation" "0,1" newline bitfld.long 0x14 26. "DITHER,Enable dither" "0,1" newline bitfld.long 0x14 25. "TILERELATIVE,Add tile offset" "0,1" newline bitfld.long 0x14 24. "DOWNSCALE,Perform box filter downscale" "0,1" newline hexmask.long.byte 0x14 20.--23. 1. "SIZE_Z,Z Size in pixels [log 2]" newline bitfld.long 0x14 18.--19. "ROTATION,Rotation angle" "0,1,2,3" newline hexmask.long.word 0x14 2.--17. 1. "LINESTRIDE,Linestride in 2 pixel units. 0 == 2. Supports 32KDWORD stride memory write" newline bitfld.long 0x14 0.--1. "MEMLAYOUT,Memory layout" "0,1,2,3" line.long 0x18 "RGX_CR_PBE_WORD0_MRT3_0,Pixel Back end State Word 0." bitfld.long 0x18 29.--31. "SWIZ_CHAN3,Swizzle for destination channel 3" "0,1,2,3,4,5,6,7" newline bitfld.long 0x18 26.--28. "SWIZ_CHAN2,Swizzle for destination channel 2" "0,1,2,3,4,5,6,7" newline bitfld.long 0x18 23.--25. "SWIZ_CHAN1,Swizzle for destination channel 1" "0,1,2,3,4,5,6,7" newline bitfld.long 0x18 20.--22. "SWIZ_CHAN0,Swizzle for destination channel 0" "0,1,2,3,4,5,6,7" newline hexmask.long.word 0x18 6.--19. 1. "MINCLIP_X,Min X Clip" newline bitfld.long 0x18 5. "TWOCOMP_GAMMA,Sets the gamma mode for 2 component targets" "0,1" newline bitfld.long 0x18 4. "GAMMA,Gamma enabled" "0,1" newline bitfld.long 0x18 3. "COMPRESSION,Frame buffer Compression enabled" "0,1" newline bitfld.long 0x18 2. "COMPRESS_SIZE,Block size for the compressor used with COMPRESS_SIZE_EXT register bit to define 8x8; 16x4 or 32x2 size COMPRESS_SIZE_EXT COMPRESS_SIZE SIZE 0 0 8x8 0 1 16x4 1 0 32x2 1 1 reserved" "0,1" newline bitfld.long 0x18 1. "COMP_INDIRECT_TABLE,If set indicates to the compressor that an indirect addressing is used otherwise direct addressing" "0,1" newline bitfld.long 0x18 0. "Y_FLIP,Y_FLIP" "0,1" line.long 0x1C "RGX_CR_PBE_WORD0_MRT3_1,Pixel Back end State Word 0." bitfld.long 0x1C 30.--31. "X_RSRVD,Not used" "0,1,2,3" newline bitfld.long 0x1C 29. "COMPRESS_SIZE_EXT,Extra bit to support 32x2 compression size used with COMPRESS_SIZE register bit to define 8x8; 16x4 or 32x2 size COMPRESS_SIZE_EXT COMPRESS_SIZE SIZE 0 0 8x8 0 1 16x4 1 0 32x2 1 1 reserved" "0,1" newline bitfld.long 0x1C 28. "COMP_IADDR_MODE,FBC indirect addressing mode" "0,1" newline bitfld.long 0x1C 27. "COMP_COR_ENABLE,Enable FBC correlation" "0,1" newline bitfld.long 0x1C 26. "DITHER,Enable dither" "0,1" newline bitfld.long 0x1C 25. "TILERELATIVE,Add tile offset" "0,1" newline bitfld.long 0x1C 24. "DOWNSCALE,Perform box filter downscale" "0,1" newline hexmask.long.byte 0x1C 20.--23. 1. "SIZE_Z,Z Size in pixels [log 2]" newline bitfld.long 0x1C 18.--19. "ROTATION,Rotation angle" "0,1,2,3" newline hexmask.long.word 0x1C 2.--17. 1. "LINESTRIDE,Linestride in 2 pixel units. 0 == 2. Supports 32KDWORD stride memory write" newline bitfld.long 0x1C 0.--1. "MEMLAYOUT,Memory layout" "0,1,2,3" line.long 0x20 "RGX_CR_PBE_WORD0_MRT4_0,Pixel Back end State Word 0." bitfld.long 0x20 29.--31. "SWIZ_CHAN3,Swizzle for destination channel 3" "0,1,2,3,4,5,6,7" newline bitfld.long 0x20 26.--28. "SWIZ_CHAN2,Swizzle for destination channel 2" "0,1,2,3,4,5,6,7" newline bitfld.long 0x20 23.--25. "SWIZ_CHAN1,Swizzle for destination channel 1" "0,1,2,3,4,5,6,7" newline bitfld.long 0x20 20.--22. "SWIZ_CHAN0,Swizzle for destination channel 0" "0,1,2,3,4,5,6,7" newline hexmask.long.word 0x20 6.--19. 1. "MINCLIP_X,Min X Clip" newline bitfld.long 0x20 5. "TWOCOMP_GAMMA,Sets the gamma mode for 2 component targets" "0,1" newline bitfld.long 0x20 4. "GAMMA,Gamma enabled" "0,1" newline bitfld.long 0x20 3. "COMPRESSION,Frame buffer Compression enabled" "0,1" newline bitfld.long 0x20 2. "COMPRESS_SIZE,Block size for the compressor used with COMPRESS_SIZE_EXT register bit to define 8x8; 16x4 or 32x2 size COMPRESS_SIZE_EXT COMPRESS_SIZE SIZE 0 0 8x8 0 1 16x4 1 0 32x2 1 1 reserved" "0,1" newline bitfld.long 0x20 1. "COMP_INDIRECT_TABLE,If set indicates to the compressor that an indirect addressing is used otherwise direct addressing" "0,1" newline bitfld.long 0x20 0. "Y_FLIP,Y_FLIP" "0,1" line.long 0x24 "RGX_CR_PBE_WORD0_MRT4_1,Pixel Back end State Word 0." bitfld.long 0x24 30.--31. "X_RSRVD,Not used" "0,1,2,3" newline bitfld.long 0x24 29. "COMPRESS_SIZE_EXT,Extra bit to support 32x2 compression size used with COMPRESS_SIZE register bit to define 8x8; 16x4 or 32x2 size COMPRESS_SIZE_EXT COMPRESS_SIZE SIZE 0 0 8x8 0 1 16x4 1 0 32x2 1 1 reserved" "0,1" newline bitfld.long 0x24 28. "COMP_IADDR_MODE,FBC indirect addressing mode" "0,1" newline bitfld.long 0x24 27. "COMP_COR_ENABLE,Enable FBC correlation" "0,1" newline bitfld.long 0x24 26. "DITHER,Enable dither" "0,1" newline bitfld.long 0x24 25. "TILERELATIVE,Add tile offset" "0,1" newline bitfld.long 0x24 24. "DOWNSCALE,Perform box filter downscale" "0,1" newline hexmask.long.byte 0x24 20.--23. 1. "SIZE_Z,Z Size in pixels [log 2]" newline bitfld.long 0x24 18.--19. "ROTATION,Rotation angle" "0,1,2,3" newline hexmask.long.word 0x24 2.--17. 1. "LINESTRIDE,Linestride in 2 pixel units. 0 == 2. Supports 32KDWORD stride memory write" newline bitfld.long 0x24 0.--1. "MEMLAYOUT,Memory layout" "0,1,2,3" line.long 0x28 "RGX_CR_PBE_WORD0_MRT5_0,Pixel Back end State Word 0." bitfld.long 0x28 29.--31. "SWIZ_CHAN3,Swizzle for destination channel 3" "0,1,2,3,4,5,6,7" newline bitfld.long 0x28 26.--28. "SWIZ_CHAN2,Swizzle for destination channel 2" "0,1,2,3,4,5,6,7" newline bitfld.long 0x28 23.--25. "SWIZ_CHAN1,Swizzle for destination channel 1" "0,1,2,3,4,5,6,7" newline bitfld.long 0x28 20.--22. "SWIZ_CHAN0,Swizzle for destination channel 0" "0,1,2,3,4,5,6,7" newline hexmask.long.word 0x28 6.--19. 1. "MINCLIP_X,Min X Clip" newline bitfld.long 0x28 5. "TWOCOMP_GAMMA,Sets the gamma mode for 2 component targets" "0,1" newline bitfld.long 0x28 4. "GAMMA,Gamma enabled" "0,1" newline bitfld.long 0x28 3. "COMPRESSION,Frame buffer Compression enabled" "0,1" newline bitfld.long 0x28 2. "COMPRESS_SIZE,Block size for the compressor used with COMPRESS_SIZE_EXT register bit to define 8x8; 16x4 or 32x2 size COMPRESS_SIZE_EXT COMPRESS_SIZE SIZE 0 0 8x8 0 1 16x4 1 0 32x2 1 1 reserved" "0,1" newline bitfld.long 0x28 1. "COMP_INDIRECT_TABLE,If set indicates to the compressor that an indirect addressing is used otherwise direct addressing" "0,1" newline bitfld.long 0x28 0. "Y_FLIP,Y_FLIP" "0,1" line.long 0x2C "RGX_CR_PBE_WORD0_MRT5_1,Pixel Back end State Word 0." bitfld.long 0x2C 30.--31. "X_RSRVD,Not used" "0,1,2,3" newline bitfld.long 0x2C 29. "COMPRESS_SIZE_EXT,Extra bit to support 32x2 compression size used with COMPRESS_SIZE register bit to define 8x8; 16x4 or 32x2 size COMPRESS_SIZE_EXT COMPRESS_SIZE SIZE 0 0 8x8 0 1 16x4 1 0 32x2 1 1 reserved" "0,1" newline bitfld.long 0x2C 28. "COMP_IADDR_MODE,FBC indirect addressing mode" "0,1" newline bitfld.long 0x2C 27. "COMP_COR_ENABLE,Enable FBC correlation" "0,1" newline bitfld.long 0x2C 26. "DITHER,Enable dither" "0,1" newline bitfld.long 0x2C 25. "TILERELATIVE,Add tile offset" "0,1" newline bitfld.long 0x2C 24. "DOWNSCALE,Perform box filter downscale" "0,1" newline hexmask.long.byte 0x2C 20.--23. 1. "SIZE_Z,Z Size in pixels [log 2]" newline bitfld.long 0x2C 18.--19. "ROTATION,Rotation angle" "0,1,2,3" newline hexmask.long.word 0x2C 2.--17. 1. "LINESTRIDE,Linestride in 2 pixel units. 0 == 2. Supports 32KDWORD stride memory write" newline bitfld.long 0x2C 0.--1. "MEMLAYOUT,Memory layout" "0,1,2,3" line.long 0x30 "RGX_CR_PBE_WORD0_MRT6_0,Pixel Back end State Word 0." bitfld.long 0x30 29.--31. "SWIZ_CHAN3,Swizzle for destination channel 3" "0,1,2,3,4,5,6,7" newline bitfld.long 0x30 26.--28. "SWIZ_CHAN2,Swizzle for destination channel 2" "0,1,2,3,4,5,6,7" newline bitfld.long 0x30 23.--25. "SWIZ_CHAN1,Swizzle for destination channel 1" "0,1,2,3,4,5,6,7" newline bitfld.long 0x30 20.--22. "SWIZ_CHAN0,Swizzle for destination channel 0" "0,1,2,3,4,5,6,7" newline hexmask.long.word 0x30 6.--19. 1. "MINCLIP_X,Min X Clip" newline bitfld.long 0x30 5. "TWOCOMP_GAMMA,Sets the gamma mode for 2 component targets" "0,1" newline bitfld.long 0x30 4. "GAMMA,Gamma enabled" "0,1" newline bitfld.long 0x30 3. "COMPRESSION,Frame buffer Compression enabled" "0,1" newline bitfld.long 0x30 2. "COMPRESS_SIZE,Block size for the compressor used with COMPRESS_SIZE_EXT register bit to define 8x8; 16x4 or 32x2 size COMPRESS_SIZE_EXT COMPRESS_SIZE SIZE 0 0 8x8 0 1 16x4 1 0 32x2 1 1 reserved" "0,1" newline bitfld.long 0x30 1. "COMP_INDIRECT_TABLE,If set indicates to the compressor that an indirect addressing is used otherwise direct addressing" "0,1" newline bitfld.long 0x30 0. "Y_FLIP,Y_FLIP" "0,1" line.long 0x34 "RGX_CR_PBE_WORD0_MRT6_1,Pixel Back end State Word 0." bitfld.long 0x34 30.--31. "X_RSRVD,Not used" "0,1,2,3" newline bitfld.long 0x34 29. "COMPRESS_SIZE_EXT,Extra bit to support 32x2 compression size used with COMPRESS_SIZE register bit to define 8x8; 16x4 or 32x2 size COMPRESS_SIZE_EXT COMPRESS_SIZE SIZE 0 0 8x8 0 1 16x4 1 0 32x2 1 1 reserved" "0,1" newline bitfld.long 0x34 28. "COMP_IADDR_MODE,FBC indirect addressing mode" "0,1" newline bitfld.long 0x34 27. "COMP_COR_ENABLE,Enable FBC correlation" "0,1" newline bitfld.long 0x34 26. "DITHER,Enable dither" "0,1" newline bitfld.long 0x34 25. "TILERELATIVE,Add tile offset" "0,1" newline bitfld.long 0x34 24. "DOWNSCALE,Perform box filter downscale" "0,1" newline hexmask.long.byte 0x34 20.--23. 1. "SIZE_Z,Z Size in pixels [log 2]" newline bitfld.long 0x34 18.--19. "ROTATION,Rotation angle" "0,1,2,3" newline hexmask.long.word 0x34 2.--17. 1. "LINESTRIDE,Linestride in 2 pixel units. 0 == 2. Supports 32KDWORD stride memory write" newline bitfld.long 0x34 0.--1. "MEMLAYOUT,Memory layout" "0,1,2,3" line.long 0x38 "RGX_CR_PBE_WORD0_MRT7_0,Pixel Back end State Word 0." bitfld.long 0x38 29.--31. "SWIZ_CHAN3,Swizzle for destination channel 3" "0,1,2,3,4,5,6,7" newline bitfld.long 0x38 26.--28. "SWIZ_CHAN2,Swizzle for destination channel 2" "0,1,2,3,4,5,6,7" newline bitfld.long 0x38 23.--25. "SWIZ_CHAN1,Swizzle for destination channel 1" "0,1,2,3,4,5,6,7" newline bitfld.long 0x38 20.--22. "SWIZ_CHAN0,Swizzle for destination channel 0" "0,1,2,3,4,5,6,7" newline hexmask.long.word 0x38 6.--19. 1. "MINCLIP_X,Min X Clip" newline bitfld.long 0x38 5. "TWOCOMP_GAMMA,Sets the gamma mode for 2 component targets" "0,1" newline bitfld.long 0x38 4. "GAMMA,Gamma enabled" "0,1" newline bitfld.long 0x38 3. "COMPRESSION,Frame buffer Compression enabled" "0,1" newline bitfld.long 0x38 2. "COMPRESS_SIZE,Block size for the compressor used with COMPRESS_SIZE_EXT register bit to define 8x8; 16x4 or 32x2 size COMPRESS_SIZE_EXT COMPRESS_SIZE SIZE 0 0 8x8 0 1 16x4 1 0 32x2 1 1 reserved" "0,1" newline bitfld.long 0x38 1. "COMP_INDIRECT_TABLE,If set indicates to the compressor that an indirect addressing is used otherwise direct addressing" "0,1" newline bitfld.long 0x38 0. "Y_FLIP,Y_FLIP" "0,1" line.long 0x3C "RGX_CR_PBE_WORD0_MRT7_1,Pixel Back end State Word 0." bitfld.long 0x3C 30.--31. "X_RSRVD,Not used" "0,1,2,3" newline bitfld.long 0x3C 29. "COMPRESS_SIZE_EXT,Extra bit to support 32x2 compression size used with COMPRESS_SIZE register bit to define 8x8; 16x4 or 32x2 size COMPRESS_SIZE_EXT COMPRESS_SIZE SIZE 0 0 8x8 0 1 16x4 1 0 32x2 1 1 reserved" "0,1" newline bitfld.long 0x3C 28. "COMP_IADDR_MODE,FBC indirect addressing mode" "0,1" newline bitfld.long 0x3C 27. "COMP_COR_ENABLE,Enable FBC correlation" "0,1" newline bitfld.long 0x3C 26. "DITHER,Enable dither" "0,1" newline bitfld.long 0x3C 25. "TILERELATIVE,Add tile offset" "0,1" newline bitfld.long 0x3C 24. "DOWNSCALE,Perform box filter downscale" "0,1" newline hexmask.long.byte 0x3C 20.--23. 1. "SIZE_Z,Z Size in pixels [log 2]" newline bitfld.long 0x3C 18.--19. "ROTATION,Rotation angle" "0,1,2,3" newline hexmask.long.word 0x3C 2.--17. 1. "LINESTRIDE,Linestride in 2 pixel units. 0 == 2. Supports 32KDWORD stride memory write" newline bitfld.long 0x3C 0.--1. "MEMLAYOUT,Memory layout" "0,1,2,3" repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) group.long ($2+0x1550)++0x3 line.long 0x0 "RGX_CR_PBE_WORD1_MRT0_$1,Pixel Back end State Word 1." hexmask.long.byte 0x0 28.--31. 1. "SIZE_Y,Y Size in pixels [log 2]" newline hexmask.long.word 0x0 14.--27. 1. "ZSLICE,Slice number for render to 3D twiddle target" newline hexmask.long.word 0x0 0.--13. 1. "MAXCLIP_Y,Max Y clip" repeat.end repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) group.long ($2+0x1558)++0x3 line.long 0x0 "RGX_CR_PBE_WORD1_MRT1_$1,Pixel Back end State Word 1." hexmask.long.byte 0x0 28.--31. 1. "SIZE_Y,Y Size in pixels [log 2]" newline hexmask.long.word 0x0 14.--27. 1. "ZSLICE,Slice number for render to 3D twiddle target" newline hexmask.long.word 0x0 0.--13. 1. "MAXCLIP_Y,Max Y clip" repeat.end repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) group.long ($2+0x1560)++0x3 line.long 0x0 "RGX_CR_PBE_WORD1_MRT2_$1,Pixel Back end State Word 1." hexmask.long.byte 0x0 28.--31. 1. "SIZE_Y,Y Size in pixels [log 2]" newline hexmask.long.word 0x0 14.--27. 1. "ZSLICE,Slice number for render to 3D twiddle target" newline hexmask.long.word 0x0 0.--13. 1. "MAXCLIP_Y,Max Y clip" repeat.end repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) group.long ($2+0x1568)++0x3 line.long 0x0 "RGX_CR_PBE_WORD1_MRT3_$1,Pixel Back end State Word 1." hexmask.long.byte 0x0 28.--31. 1. "SIZE_Y,Y Size in pixels [log 2]" newline hexmask.long.word 0x0 14.--27. 1. "ZSLICE,Slice number for render to 3D twiddle target" newline hexmask.long.word 0x0 0.--13. 1. "MAXCLIP_Y,Max Y clip" repeat.end repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) group.long ($2+0x1570)++0x3 line.long 0x0 "RGX_CR_PBE_WORD1_MRT4_$1,Pixel Back end State Word 1." hexmask.long.byte 0x0 28.--31. 1. "SIZE_Y,Y Size in pixels [log 2]" newline hexmask.long.word 0x0 14.--27. 1. "ZSLICE,Slice number for render to 3D twiddle target" newline hexmask.long.word 0x0 0.--13. 1. "MAXCLIP_Y,Max Y clip" repeat.end repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) group.long ($2+0x1578)++0x3 line.long 0x0 "RGX_CR_PBE_WORD1_MRT5_$1,Pixel Back end State Word 1." hexmask.long.byte 0x0 28.--31. 1. "SIZE_Y,Y Size in pixels [log 2]" newline hexmask.long.word 0x0 14.--27. 1. "ZSLICE,Slice number for render to 3D twiddle target" newline hexmask.long.word 0x0 0.--13. 1. "MAXCLIP_Y,Max Y clip" repeat.end repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) group.long ($2+0x1580)++0x3 line.long 0x0 "RGX_CR_PBE_WORD1_MRT6_$1,Pixel Back end State Word 1." hexmask.long.byte 0x0 28.--31. 1. "SIZE_Y,Y Size in pixels [log 2]" newline hexmask.long.word 0x0 14.--27. 1. "ZSLICE,Slice number for render to 3D twiddle target" newline hexmask.long.word 0x0 0.--13. 1. "MAXCLIP_Y,Max Y clip" repeat.end repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) group.long ($2+0x1588)++0x3 line.long 0x0 "RGX_CR_PBE_WORD1_MRT7_$1,Pixel Back end State Word 1." hexmask.long.byte 0x0 28.--31. 1. "SIZE_Y,Y Size in pixels [log 2]" newline hexmask.long.word 0x0 14.--27. 1. "ZSLICE,Slice number for render to 3D twiddle target" newline hexmask.long.word 0x0 0.--13. 1. "MAXCLIP_Y,Max Y clip" repeat.end repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) rgroup.long ($2+0x1590)++0x3 line.long 0x0 "RGX_CR_PBE_PWR_$1,Power monitoring register" hexmask.long 0x0 0.--31. 1. "NUM_PIXELS_PROCESSED,Number of on-edge/off-edge pixels per tile." repeat.end group.long 0x15A0++0x3F line.long 0x0 "RGX_CR_PBE_WORD2_MRT0_0,Pixel Back end State Word 2." hexmask.long 0x0 0.--31. 1. "SW_BYTEMASK,SW driven mask" line.long 0x4 "RGX_CR_PBE_WORD2_MRT0_1,Pixel Back end State Word 2." hexmask.long.tbyte 0x4 15.--31. 1. "Reserved_47,Reserved_47" newline bitfld.long 0x4 14. "PAIR_TILES,If set then PBE will pair 16x16 tiles" "0,1" newline hexmask.long.word 0x4 0.--13. 1. "SURFACE_Y_SIZE,Y Size in pixels (only used for strided memory layout with FBC)" line.long 0x8 "RGX_CR_PBE_WORD2_MRT1_0,Pixel Back end State Word 2." hexmask.long 0x8 0.--31. 1. "SW_BYTEMASK,SW driven mask" line.long 0xC "RGX_CR_PBE_WORD2_MRT1_1,Pixel Back end State Word 2." hexmask.long.tbyte 0xC 15.--31. 1. "Reserved_47,Reserved_47" newline bitfld.long 0xC 14. "PAIR_TILES,If set then PBE will pair 16x16 tiles" "0,1" newline hexmask.long.word 0xC 0.--13. 1. "SURFACE_Y_SIZE,Y Size in pixels (only used for strided memory layout with FBC)" line.long 0x10 "RGX_CR_PBE_WORD2_MRT2_0,Pixel Back end State Word 2." hexmask.long 0x10 0.--31. 1. "SW_BYTEMASK,SW driven mask" line.long 0x14 "RGX_CR_PBE_WORD2_MRT2_1,Pixel Back end State Word 2." hexmask.long.tbyte 0x14 15.--31. 1. "Reserved_47,Reserved_47" newline bitfld.long 0x14 14. "PAIR_TILES,If set then PBE will pair 16x16 tiles" "0,1" newline hexmask.long.word 0x14 0.--13. 1. "SURFACE_Y_SIZE,Y Size in pixels (only used for strided memory layout with FBC)" line.long 0x18 "RGX_CR_PBE_WORD2_MRT3_0,Pixel Back end State Word 2." hexmask.long 0x18 0.--31. 1. "SW_BYTEMASK,SW driven mask" line.long 0x1C "RGX_CR_PBE_WORD2_MRT3_1,Pixel Back end State Word 2." hexmask.long.tbyte 0x1C 15.--31. 1. "Reserved_47,Reserved_47" newline bitfld.long 0x1C 14. "PAIR_TILES,If set then PBE will pair 16x16 tiles" "0,1" newline hexmask.long.word 0x1C 0.--13. 1. "SURFACE_Y_SIZE,Y Size in pixels (only used for strided memory layout with FBC)" line.long 0x20 "RGX_CR_PBE_WORD2_MRT4_0,Pixel Back end State Word 2." hexmask.long 0x20 0.--31. 1. "SW_BYTEMASK,SW driven mask" line.long 0x24 "RGX_CR_PBE_WORD2_MRT4_1,Pixel Back end State Word 2." hexmask.long.tbyte 0x24 15.--31. 1. "Reserved_47,Reserved_47" newline bitfld.long 0x24 14. "PAIR_TILES,If set then PBE will pair 16x16 tiles" "0,1" newline hexmask.long.word 0x24 0.--13. 1. "SURFACE_Y_SIZE,Y Size in pixels (only used for strided memory layout with FBC)" line.long 0x28 "RGX_CR_PBE_WORD2_MRT5_0,Pixel Back end State Word 2." hexmask.long 0x28 0.--31. 1. "SW_BYTEMASK,SW driven mask" line.long 0x2C "RGX_CR_PBE_WORD2_MRT5_1,Pixel Back end State Word 2." hexmask.long.tbyte 0x2C 15.--31. 1. "Reserved_47,Reserved_47" newline bitfld.long 0x2C 14. "PAIR_TILES,If set then PBE will pair 16x16 tiles" "0,1" newline hexmask.long.word 0x2C 0.--13. 1. "SURFACE_Y_SIZE,Y Size in pixels (only used for strided memory layout with FBC)" line.long 0x30 "RGX_CR_PBE_WORD2_MRT6_0,Pixel Back end State Word 2." hexmask.long 0x30 0.--31. 1. "SW_BYTEMASK,SW driven mask" line.long 0x34 "RGX_CR_PBE_WORD2_MRT6_1,Pixel Back end State Word 2." hexmask.long.tbyte 0x34 15.--31. 1. "Reserved_47,Reserved_47" newline bitfld.long 0x34 14. "PAIR_TILES,If set then PBE will pair 16x16 tiles" "0,1" newline hexmask.long.word 0x34 0.--13. 1. "SURFACE_Y_SIZE,Y Size in pixels (only used for strided memory layout with FBC)" line.long 0x38 "RGX_CR_PBE_WORD2_MRT7_0,Pixel Back end State Word 2." hexmask.long 0x38 0.--31. 1. "SW_BYTEMASK,SW driven mask" line.long 0x3C "RGX_CR_PBE_WORD2_MRT7_1,Pixel Back end State Word 2." hexmask.long.tbyte 0x3C 15.--31. 1. "Reserved_47,Reserved_47" newline bitfld.long 0x3C 14. "PAIR_TILES,If set then PBE will pair 16x16 tiles" "0,1" newline hexmask.long.word 0x3C 0.--13. 1. "SURFACE_Y_SIZE,Y Size in pixels (only used for strided memory layout with FBC)" group.long 0x1600++0x11F line.long 0x0 "RGX_CR_FB_CDC_0,Framebuffer Compression/Decompression arbiter modes" bitfld.long 0x0 30.--31. "FBDC_MCU_SLC_HDR_POLICY,SLC Cache policy for MCU requested FBDC header requests" "0,1,2,3" newline bitfld.long 0x0 28.--29. "FBDC_MCU_SLC_DATA_POLICY,SLC Cache policy for MCU requested FBDC tile data requests" "0,1,2,3" newline hexmask.long.word 0x0 12.--27. 1. "FBC_FBDC_COMPATIBILITY,The register defines the mode of operation to ensure that the GPU FBC/FBDC is compatible with any FBC/FBDC existing in the SoC (standalone FBC/FBDC). To be compatible the register needs to be programed with the version of the SoC.." newline bitfld.long 0x0 11. "FBC_FBDC_INVAL_OVERRIDE,When set then all FBDC header cache entries will be invalidate from the FBC otherwise only those associated with the request being processed by the FBC will be invalidated" "0,1" newline bitfld.long 0x0 10. "ZLS_SLC_NOLINEFILL,ZLS write SLC no line fill: 0=line fill on miss 1=no line fill on miss" "line fill on miss,no line fill on miss" newline bitfld.long 0x0 8.--9. "ZLS_SLC_POLICY,ZLS write SLC cache Policy" "0,1,2,3" newline bitfld.long 0x0 7. "PBE_SLC_NOLINEFILL,PBE write SLC no line fill: 0=line fill on miss 1=no line fill on miss" "line fill on miss,no line fill on miss" newline bitfld.long 0x0 5.--6. "PBE_SLC_POLICY,PBE write SLC cache Policy" "0,1,2,3" newline bitfld.long 0x0 4. "PBE_COR_COLOUR_ENABLE,PBE Enable correlation/decorrelation for PBE 0=disbaled 1=enabled" "disbaled,enabled" newline bitfld.long 0x0 3. "FBC_ARB_MODE,FBC Request Arbiter Mode 0 = Re-arbitrate after tile 1 = Re-arbitrate after valid drop and tile complete" "Re-arbitrate after tile,Re-arbitrate after valid drop and tile complete" newline bitfld.long 0x0 2. "Reserved_2,Reserved_2" "0,1" newline bitfld.long 0x0 1. "TLDECODE_ARB_MODE,TLCache Request Arbiter Mode Rearbitration:0 = valid dropped and burst complete 1 = After burst complete" "valid dropped and burst complete,After burst complete" newline bitfld.long 0x0 0. "BIF_ARB_MODE,FBC and FBDC BIF Arbiter Mode 0 = Re-arbitrate after burst 1 = Re-arbitrate after valid drop and burst complete" "Re-arbitrate after burst,Re-arbitrate after valid drop and burst complete" line.long 0x4 "RGX_CR_FB_CDC_1,Framebuffer Compression/Decompression arbiter modes" hexmask.long.tbyte 0x4 13.--31. 1. "Reserved_45,Reserved_45" newline bitfld.long 0x4 12. "FBCDC_COR_ENABLE,writing '0' the compression correlation/decorrelation is disable" "0,1" newline hexmask.long.byte 0x4 4.--11. 1. "Reserved_36,Reserved_36" newline bitfld.long 0x4 2.--3. "FBDC_ZLS_SLC_HDR_POLICY,SLC Cache policy for ZLS requested FBDC header requests" "0,1,2,3" newline bitfld.long 0x4 0.--1. "FBDC_ZLS_SLC_DATA_POLICY,SLC Cache policy for ZLS requested FBDC tile data requests" "0,1,2,3" line.long 0x8 "RGX_CR_FB_ICTRL_0,Framebuffer Invalidates" hexmask.long.word 0x8 23.--31. 1. "Reserved_23,Reserved_23" newline bitfld.long 0x8 22. "TLCACHE_INVALFLUSH_FASTRENDER_DM,When set to 1 all entries in the tile cache that have been tagged as a fastrender data master will be invalidate/flush when TLCACHE_INVALFLUSH_PENDING is set" "0,1" newline bitfld.long 0x8 19.--21. "Reserved_19,Reserved_19" "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x8 15.--18. 1. "FBDC_INVALIDATE_REQUESTER,Bit mask of requester to invalidate when FBDC_INVALIDATE_PENDING is set" newline bitfld.long 0x8 14. "TLCACHE_INVALFLUSH_TOMEM,When set to 1 all flushes will result in a flush fence being sent to memory after the tiles have been flushed. On return of this fence the TLCACHE_INVALFLUSH_PENDING will be cleared. When not set a flush fence is not sent and.." "0,1" newline hexmask.long.byte 0x8 10.--13. 1. "TLCACHE_INVALFLUSH_REQUESTER,Bit mask of requester to flush or invalidate when TLCACHE_INVALFUSH_PENDING is set These are also used in combination with the invalflush__DM mask bits" newline bitfld.long 0x8 8.--9. "Reserved_8,Reserved_8" "0,1,2,3" newline bitfld.long 0x8 7. "TLCACHE_INVALFLUSH_COMP_DM,When set to 1 all entries in the tile cache that have been tagged as a compute data master will be invalidate/flush when TLCACHE_INVALFLUSH_PENDING is set" "0,1" newline bitfld.long 0x8 6. "TLCACHE_INVALFLUSH_VERTEX_DM,When set to 1 all entries in the tile cache that have been tagged as a vertex data master will be invalidate/flush when TLCACHE_INVALFLUSH_PENDING is set" "0,1" newline bitfld.long 0x8 5. "TLCACHE_INVALFLUSH_PIXEL_DM,When set to 1 all entries in the tile cache that have been tagged as a pixel data master will be invalidate/flush when TLCACHE_INVALFLUSH_PENDING is set" "0,1" newline bitfld.long 0x8 3.--4. "TLCACHE_INVALFLUSH_PENDING,The cache may be requested to flush or invalidate or both in a single write access. Each bit when read returns the current status of the flush or invalidate request. Bit 0 = Invalidate Bit 1 = Flush If either bit is read back.." "Invalidate,Flush,?,?" newline bitfld.long 0x8 1.--2. "Reserved_1,Reserved_1" "0,1,2,3" newline bitfld.long 0x8 0. "FBDC_INVALIDATE_PENDING,When written to 1 will invalidate the header cache in the FBDC when read as 1 invalidate is in progress when read as 0 invalidate is complete" "0,1" line.long 0xC "RGX_CR_FB_ICTRL_1,Framebuffer Invalidates" hexmask.long 0xC 0.--31. 1. "Reserved_23,Reserved_23" line.long 0x10 "RGX_CR_FB_MEM_REGION0_0,Framebuffer Compression/Decompression memory regions for Host and TLA accesses" hexmask.long 0x10 0.--31. 1. "BASE_ADDRESS,Base address of this memory region in 512bit granularity" line.long 0x14 "RGX_CR_FB_MEM_REGION0_1,Framebuffer Compression/Decompression memory regions for Host and TLA accesses" hexmask.long.byte 0x14 25.--31. 1. "Reserved_57,Reserved_57" newline hexmask.long.tbyte 0x14 2.--24. 1. "NUM_TILES,The number of compressor tiles to be used in this memory region" newline bitfld.long 0x14 0.--1. "BASE_ADDRESS,Base address of this memory region in 512bit granularity" "0,1,2,3" line.long 0x18 "RGX_CR_FB_MEM_REGION1_0,Framebuffer Compression/Decompression memory regions for Host and TLA accesses" hexmask.long 0x18 0.--31. 1. "BASE_ADDRESS,Base address of this memory region in 512bit granularity" line.long 0x1C "RGX_CR_FB_MEM_REGION1_1,Framebuffer Compression/Decompression memory regions for Host and TLA accesses" hexmask.long.byte 0x1C 25.--31. 1. "Reserved_57,Reserved_57" newline hexmask.long.tbyte 0x1C 2.--24. 1. "NUM_TILES,The number of compressor tiles to be used in this memory region" newline bitfld.long 0x1C 0.--1. "BASE_ADDRESS,Base address of this memory region in 512bit granularity" "0,1,2,3" line.long 0x20 "RGX_CR_FB_MEM_REGION2_0,Framebuffer Compression/Decompression memory regions for Host and TLA accesses" hexmask.long 0x20 0.--31. 1. "BASE_ADDRESS,Base address of this memory region in 512bit granularity" line.long 0x24 "RGX_CR_FB_MEM_REGION2_1,Framebuffer Compression/Decompression memory regions for Host and TLA accesses" hexmask.long.byte 0x24 25.--31. 1. "Reserved_57,Reserved_57" newline hexmask.long.tbyte 0x24 2.--24. 1. "NUM_TILES,The number of compressor tiles to be used in this memory region" newline bitfld.long 0x24 0.--1. "BASE_ADDRESS,Base address of this memory region in 512bit granularity" "0,1,2,3" line.long 0x28 "RGX_CR_FB_MEM_REGION3_0,Framebuffer Compression/Decompression memory regions for Host and TLA accesses" hexmask.long 0x28 0.--31. 1. "BASE_ADDRESS,Base address of this memory region in 512bit granularity" line.long 0x2C "RGX_CR_FB_MEM_REGION3_1,Framebuffer Compression/Decompression memory regions for Host and TLA accesses" hexmask.long.byte 0x2C 25.--31. 1. "Reserved_57,Reserved_57" newline hexmask.long.tbyte 0x2C 2.--24. 1. "NUM_TILES,The number of compressor tiles to be used in this memory region" newline bitfld.long 0x2C 0.--1. "BASE_ADDRESS,Base address of this memory region in 512bit granularity" "0,1,2,3" line.long 0x30 "RGX_CR_FB_MEM_REGION4_0,Framebuffer Compression/Decompression memory regions for Host and TLA accesses" hexmask.long 0x30 0.--31. 1. "BASE_ADDRESS,Base address of this memory region in 512bit granularity" line.long 0x34 "RGX_CR_FB_MEM_REGION4_1,Framebuffer Compression/Decompression memory regions for Host and TLA accesses" hexmask.long.byte 0x34 25.--31. 1. "Reserved_57,Reserved_57" newline hexmask.long.tbyte 0x34 2.--24. 1. "NUM_TILES,The number of compressor tiles to be used in this memory region" newline bitfld.long 0x34 0.--1. "BASE_ADDRESS,Base address of this memory region in 512bit granularity" "0,1,2,3" line.long 0x38 "RGX_CR_FB_MEM_REGION5_0,Framebuffer Compression/Decompression memory regions for Host and TLA accesses" hexmask.long 0x38 0.--31. 1. "BASE_ADDRESS,Base address of this memory region in 512bit granularity" line.long 0x3C "RGX_CR_FB_MEM_REGION5_1,Framebuffer Compression/Decompression memory regions for Host and TLA accesses" hexmask.long.byte 0x3C 25.--31. 1. "Reserved_57,Reserved_57" newline hexmask.long.tbyte 0x3C 2.--24. 1. "NUM_TILES,The number of compressor tiles to be used in this memory region" newline bitfld.long 0x3C 0.--1. "BASE_ADDRESS,Base address of this memory region in 512bit granularity" "0,1,2,3" line.long 0x40 "RGX_CR_FB_MEM_REGION6_0,Framebuffer Compression/Decompression memory regions for Host and TLA accesses" hexmask.long 0x40 0.--31. 1. "BASE_ADDRESS,Base address of this memory region in 512bit granularity" line.long 0x44 "RGX_CR_FB_MEM_REGION6_1,Framebuffer Compression/Decompression memory regions for Host and TLA accesses" hexmask.long.byte 0x44 25.--31. 1. "Reserved_57,Reserved_57" newline hexmask.long.tbyte 0x44 2.--24. 1. "NUM_TILES,The number of compressor tiles to be used in this memory region" newline bitfld.long 0x44 0.--1. "BASE_ADDRESS,Base address of this memory region in 512bit granularity" "0,1,2,3" line.long 0x48 "RGX_CR_FB_MEM_REGION7_0,Framebuffer Compression/Decompression memory regions for Host and TLA accesses" hexmask.long 0x48 0.--31. 1. "BASE_ADDRESS,Base address of this memory region in 512bit granularity" line.long 0x4C "RGX_CR_FB_MEM_REGION7_1,Framebuffer Compression/Decompression memory regions for Host and TLA accesses" hexmask.long.byte 0x4C 25.--31. 1. "Reserved_57,Reserved_57" newline hexmask.long.tbyte 0x4C 2.--24. 1. "NUM_TILES,The number of compressor tiles to be used in this memory region" newline bitfld.long 0x4C 0.--1. "BASE_ADDRESS,Base address of this memory region in 512bit granularity" "0,1,2,3" line.long 0x50 "RGX_CR_FB_MEM_REGION8_0,Framebuffer Compression/Decompression memory regions for Host and TLA accesses" hexmask.long 0x50 0.--31. 1. "BASE_ADDRESS,Base address of this memory region in 512bit granularity" line.long 0x54 "RGX_CR_FB_MEM_REGION8_1,Framebuffer Compression/Decompression memory regions for Host and TLA accesses" hexmask.long.byte 0x54 25.--31. 1. "Reserved_57,Reserved_57" newline hexmask.long.tbyte 0x54 2.--24. 1. "NUM_TILES,The number of compressor tiles to be used in this memory region" newline bitfld.long 0x54 0.--1. "BASE_ADDRESS,Base address of this memory region in 512bit granularity" "0,1,2,3" line.long 0x58 "RGX_CR_FB_MEM_REGION9_0,Framebuffer Compression/Decompression memory regions for Host and TLA accesses" hexmask.long 0x58 0.--31. 1. "BASE_ADDRESS,Base address of this memory region in 512bit granularity" line.long 0x5C "RGX_CR_FB_MEM_REGION9_1,Framebuffer Compression/Decompression memory regions for Host and TLA accesses" hexmask.long.byte 0x5C 25.--31. 1. "Reserved_57,Reserved_57" newline hexmask.long.tbyte 0x5C 2.--24. 1. "NUM_TILES,The number of compressor tiles to be used in this memory region" newline bitfld.long 0x5C 0.--1. "BASE_ADDRESS,Base address of this memory region in 512bit granularity" "0,1,2,3" line.long 0x60 "RGX_CR_FB_MEM_REGION10_0,Framebuffer Compression/Decompression memory regions for Host and TLA accesses" hexmask.long 0x60 0.--31. 1. "BASE_ADDRESS,Base address of this memory region in 512bit granularity" line.long 0x64 "RGX_CR_FB_MEM_REGION10_1,Framebuffer Compression/Decompression memory regions for Host and TLA accesses" hexmask.long.byte 0x64 25.--31. 1. "Reserved_57,Reserved_57" newline hexmask.long.tbyte 0x64 2.--24. 1. "NUM_TILES,The number of compressor tiles to be used in this memory region" newline bitfld.long 0x64 0.--1. "BASE_ADDRESS,Base address of this memory region in 512bit granularity" "0,1,2,3" line.long 0x68 "RGX_CR_FB_MEM_REGION11_0,Framebuffer Compression/Decompression memory regions for Host and TLA accesses" hexmask.long 0x68 0.--31. 1. "BASE_ADDRESS,Base address of this memory region in 512bit granularity" line.long 0x6C "RGX_CR_FB_MEM_REGION11_1,Framebuffer Compression/Decompression memory regions for Host and TLA accesses" hexmask.long.byte 0x6C 25.--31. 1. "Reserved_57,Reserved_57" newline hexmask.long.tbyte 0x6C 2.--24. 1. "NUM_TILES,The number of compressor tiles to be used in this memory region" newline bitfld.long 0x6C 0.--1. "BASE_ADDRESS,Base address of this memory region in 512bit granularity" "0,1,2,3" line.long 0x70 "RGX_CR_FB_MEM_REGION12_0,Framebuffer Compression/Decompression memory regions for Host and TLA accesses" hexmask.long 0x70 0.--31. 1. "BASE_ADDRESS,Base address of this memory region in 512bit granularity" line.long 0x74 "RGX_CR_FB_MEM_REGION12_1,Framebuffer Compression/Decompression memory regions for Host and TLA accesses" hexmask.long.byte 0x74 25.--31. 1. "Reserved_57,Reserved_57" newline hexmask.long.tbyte 0x74 2.--24. 1. "NUM_TILES,The number of compressor tiles to be used in this memory region" newline bitfld.long 0x74 0.--1. "BASE_ADDRESS,Base address of this memory region in 512bit granularity" "0,1,2,3" line.long 0x78 "RGX_CR_FB_MEM_REGION13_0,Framebuffer Compression/Decompression memory regions for Host and TLA accesses" hexmask.long 0x78 0.--31. 1. "BASE_ADDRESS,Base address of this memory region in 512bit granularity" line.long 0x7C "RGX_CR_FB_MEM_REGION13_1,Framebuffer Compression/Decompression memory regions for Host and TLA accesses" hexmask.long.byte 0x7C 25.--31. 1. "Reserved_57,Reserved_57" newline hexmask.long.tbyte 0x7C 2.--24. 1. "NUM_TILES,The number of compressor tiles to be used in this memory region" newline bitfld.long 0x7C 0.--1. "BASE_ADDRESS,Base address of this memory region in 512bit granularity" "0,1,2,3" line.long 0x80 "RGX_CR_FB_MEM_REGION14_0,Framebuffer Compression/Decompression memory regions for Host and TLA accesses" hexmask.long 0x80 0.--31. 1. "BASE_ADDRESS,Base address of this memory region in 512bit granularity" line.long 0x84 "RGX_CR_FB_MEM_REGION14_1,Framebuffer Compression/Decompression memory regions for Host and TLA accesses" hexmask.long.byte 0x84 25.--31. 1. "Reserved_57,Reserved_57" newline hexmask.long.tbyte 0x84 2.--24. 1. "NUM_TILES,The number of compressor tiles to be used in this memory region" newline bitfld.long 0x84 0.--1. "BASE_ADDRESS,Base address of this memory region in 512bit granularity" "0,1,2,3" line.long 0x88 "RGX_CR_FB_MEM_REGION15_0,Framebuffer Compression/Decompression memory regions for Host and TLA accesses" hexmask.long 0x88 0.--31. 1. "BASE_ADDRESS,Base address of this memory region in 512bit granularity" line.long 0x8C "RGX_CR_FB_MEM_REGION15_1,Framebuffer Compression/Decompression memory regions for Host and TLA accesses" hexmask.long.byte 0x8C 25.--31. 1. "Reserved_57,Reserved_57" newline hexmask.long.tbyte 0x8C 2.--24. 1. "NUM_TILES,The number of compressor tiles to be used in this memory region" newline bitfld.long 0x8C 0.--1. "BASE_ADDRESS,Base address of this memory region in 512bit granularity" "0,1,2,3" line.long 0x90 "RGX_CR_FB_MEM_REGION_CTRL0_0,Framebuffer Compression/Decompression memory regions for Host and TLA accesses" hexmask.long.byte 0x90 25.--31. 1. "DIMY,Surface height in terms of TILE_TYPE for this memory region" newline hexmask.long.word 0x90 12.--24. 1. "DIMX,Surface width in terms of TILE_TYPE for this memory region" newline bitfld.long 0x90 11. "MEML,Surface Memory layout for this memory region 0=linear 1=twiddled" "linear,twiddled" newline bitfld.long 0x90 9.--10. "DM,Data master to be used for this memory region 00 = TA/Vertex 01 = 3D/Pixel 10 = Compute 11 = Data Master of Requester If the memory region is being accessed by the TLA the data master is set to the TLA data master If the memory region is being.." "TA/Vertex,?,?,?" newline bitfld.long 0x90 8. "TILE_TYPE,Compressor tile type 0 = 8x8 pixels 1 = 16x4 pixels" "0,1" newline hexmask.long.byte 0x90 1.--7. 1. "FMT,The pixel format to be used in this memory region" newline bitfld.long 0x90 0. "MODE,Defines if this memory region maps to BIF or FBC/FBDC access; 0 = BIF 1 = FBC/FBDC" "BIF,FBC/FBDC" line.long 0x94 "RGX_CR_FB_MEM_REGION_CTRL0_1,Framebuffer Compression/Decompression memory regions for Host and TLA accesses" hexmask.long.tbyte 0x94 15.--31. 1. "Reserved_47,Reserved_47" newline bitfld.long 0x94 14. "PORT,Defines if this memory region is to be used by the TLA or Host port. 0 = TLA Port 1 = Host Port" "TLA Port,Host Port" newline bitfld.long 0x94 13. "ACTIVE,Defines if this memory region is active or not default to INACTIVE. Used in conjuction with MODE field to define if a memory region maps to BIF or FBC/FBDC access. If active then this region base address is used to check if an access is for the.." "0,1" newline bitfld.long 0x94 12. "SLC_NOLINEFILL,SLC cache no line fill Policy: 0= line fill on miss 1=no line fill on miss" "line fill on miss,no line fill on miss" newline bitfld.long 0x94 10.--11. "SLC_POLICY,SLC cache Policy: 00=Bypass 01=Write Back 10 =Write Through 11=Cached Read" "Bypass,Write Back,?,?" newline bitfld.long 0x94 9. "TLCACHE_POLICY,Tile cache Policy: 1=no line fill on miss 0=line fill on miss" "line fill on miss,no line fill on miss" newline bitfld.long 0x94 8. "COR_COLOUR_ENABLE,Correlation Colour Enable 0=off 1=on" "off,on" newline bitfld.long 0x94 7. "IADDR,Direct/Indirect Addressing: 1=indirect 0=direct" "direct,indirect" newline hexmask.long.byte 0x94 0.--6. 1. "DIMY,Surface height in terms of TILE_TYPE for this memory region" line.long 0x98 "RGX_CR_FB_MEM_REGION_CTRL1_0,Framebuffer Compression/Decompression memory regions for Host and TLA accesses" hexmask.long.byte 0x98 25.--31. 1. "DIMY,Surface height in terms of TILE_TYPE for this memory region" newline hexmask.long.word 0x98 12.--24. 1. "DIMX,Surface width in terms of TILE_TYPE for this memory region" newline bitfld.long 0x98 11. "MEML,Surface Memory layout for this memory region 0=linear 1=twiddled" "linear,twiddled" newline bitfld.long 0x98 9.--10. "DM,Data master to be used for this memory region 00 = TA/Vertex 01 = 3D/Pixel 10 = Compute 11 = Data Master of Requester If the memory region is being accessed by the TLA the data master is set to the TLA data master If the memory region is being.." "TA/Vertex,?,?,?" newline bitfld.long 0x98 8. "TILE_TYPE,Compressor tile type 0 = 8x8 pixels 1 = 16x4 pixels" "0,1" newline hexmask.long.byte 0x98 1.--7. 1. "FMT,The pixel format to be used in this memory region" newline bitfld.long 0x98 0. "MODE,Defines if this memory region maps to BIF or FBC/FBDC access; 0 = BIF 1 = FBC/FBDC" "BIF,FBC/FBDC" line.long 0x9C "RGX_CR_FB_MEM_REGION_CTRL1_1,Framebuffer Compression/Decompression memory regions for Host and TLA accesses" hexmask.long.tbyte 0x9C 15.--31. 1. "Reserved_47,Reserved_47" newline bitfld.long 0x9C 14. "PORT,Defines if this memory region is to be used by the TLA or Host port. 0 = TLA Port 1 = Host Port" "TLA Port,Host Port" newline bitfld.long 0x9C 13. "ACTIVE,Defines if this memory region is active or not default to INACTIVE. Used in conjuction with MODE field to define if a memory region maps to BIF or FBC/FBDC access. If active then this region base address is used to check if an access is for the.." "0,1" newline bitfld.long 0x9C 12. "SLC_NOLINEFILL,SLC cache no line fill Policy: 0= line fill on miss 1=no line fill on miss" "line fill on miss,no line fill on miss" newline bitfld.long 0x9C 10.--11. "SLC_POLICY,SLC cache Policy: 00=Bypass 01=Write Back 10 =Write Through 11=Cached Read" "Bypass,Write Back,?,?" newline bitfld.long 0x9C 9. "TLCACHE_POLICY,Tile cache Policy: 1=no line fill on miss 0=line fill on miss" "line fill on miss,no line fill on miss" newline bitfld.long 0x9C 8. "COR_COLOUR_ENABLE,Correlation Colour Enable 0=off 1=on" "off,on" newline bitfld.long 0x9C 7. "IADDR,Direct/Indirect Addressing: 1=indirect 0=direct" "direct,indirect" newline hexmask.long.byte 0x9C 0.--6. 1. "DIMY,Surface height in terms of TILE_TYPE for this memory region" line.long 0xA0 "RGX_CR_FB_MEM_REGION_CTRL2_0,Framebuffer Compression/Decompression memory regions for Host and TLA accesses" hexmask.long.byte 0xA0 25.--31. 1. "DIMY,Surface height in terms of TILE_TYPE for this memory region" newline hexmask.long.word 0xA0 12.--24. 1. "DIMX,Surface width in terms of TILE_TYPE for this memory region" newline bitfld.long 0xA0 11. "MEML,Surface Memory layout for this memory region 0=linear 1=twiddled" "linear,twiddled" newline bitfld.long 0xA0 9.--10. "DM,Data master to be used for this memory region 00 = TA/Vertex 01 = 3D/Pixel 10 = Compute 11 = Data Master of Requester If the memory region is being accessed by the TLA the data master is set to the TLA data master If the memory region is being.." "TA/Vertex,?,?,?" newline bitfld.long 0xA0 8. "TILE_TYPE,Compressor tile type 0 = 8x8 pixels 1 = 16x4 pixels" "0,1" newline hexmask.long.byte 0xA0 1.--7. 1. "FMT,The pixel format to be used in this memory region" newline bitfld.long 0xA0 0. "MODE,Defines if this memory region maps to BIF or FBC/FBDC access; 0 = BIF 1 = FBC/FBDC" "BIF,FBC/FBDC" line.long 0xA4 "RGX_CR_FB_MEM_REGION_CTRL2_1,Framebuffer Compression/Decompression memory regions for Host and TLA accesses" hexmask.long.tbyte 0xA4 15.--31. 1. "Reserved_47,Reserved_47" newline bitfld.long 0xA4 14. "PORT,Defines if this memory region is to be used by the TLA or Host port. 0 = TLA Port 1 = Host Port" "TLA Port,Host Port" newline bitfld.long 0xA4 13. "ACTIVE,Defines if this memory region is active or not default to INACTIVE. Used in conjuction with MODE field to define if a memory region maps to BIF or FBC/FBDC access. If active then this region base address is used to check if an access is for the.." "0,1" newline bitfld.long 0xA4 12. "SLC_NOLINEFILL,SLC cache no line fill Policy: 0= line fill on miss 1=no line fill on miss" "line fill on miss,no line fill on miss" newline bitfld.long 0xA4 10.--11. "SLC_POLICY,SLC cache Policy: 00=Bypass 01=Write Back 10 =Write Through 11=Cached Read" "Bypass,Write Back,?,?" newline bitfld.long 0xA4 9. "TLCACHE_POLICY,Tile cache Policy: 1=no line fill on miss 0=line fill on miss" "line fill on miss,no line fill on miss" newline bitfld.long 0xA4 8. "COR_COLOUR_ENABLE,Correlation Colour Enable 0=off 1=on" "off,on" newline bitfld.long 0xA4 7. "IADDR,Direct/Indirect Addressing: 1=indirect 0=direct" "direct,indirect" newline hexmask.long.byte 0xA4 0.--6. 1. "DIMY,Surface height in terms of TILE_TYPE for this memory region" line.long 0xA8 "RGX_CR_FB_MEM_REGION_CTRL3_0,Framebuffer Compression/Decompression memory regions for Host and TLA accesses" hexmask.long.byte 0xA8 25.--31. 1. "DIMY,Surface height in terms of TILE_TYPE for this memory region" newline hexmask.long.word 0xA8 12.--24. 1. "DIMX,Surface width in terms of TILE_TYPE for this memory region" newline bitfld.long 0xA8 11. "MEML,Surface Memory layout for this memory region 0=linear 1=twiddled" "linear,twiddled" newline bitfld.long 0xA8 9.--10. "DM,Data master to be used for this memory region 00 = TA/Vertex 01 = 3D/Pixel 10 = Compute 11 = Data Master of Requester If the memory region is being accessed by the TLA the data master is set to the TLA data master If the memory region is being.." "TA/Vertex,?,?,?" newline bitfld.long 0xA8 8. "TILE_TYPE,Compressor tile type 0 = 8x8 pixels 1 = 16x4 pixels" "0,1" newline hexmask.long.byte 0xA8 1.--7. 1. "FMT,The pixel format to be used in this memory region" newline bitfld.long 0xA8 0. "MODE,Defines if this memory region maps to BIF or FBC/FBDC access; 0 = BIF 1 = FBC/FBDC" "BIF,FBC/FBDC" line.long 0xAC "RGX_CR_FB_MEM_REGION_CTRL3_1,Framebuffer Compression/Decompression memory regions for Host and TLA accesses" hexmask.long.tbyte 0xAC 15.--31. 1. "Reserved_47,Reserved_47" newline bitfld.long 0xAC 14. "PORT,Defines if this memory region is to be used by the TLA or Host port. 0 = TLA Port 1 = Host Port" "TLA Port,Host Port" newline bitfld.long 0xAC 13. "ACTIVE,Defines if this memory region is active or not default to INACTIVE. Used in conjuction with MODE field to define if a memory region maps to BIF or FBC/FBDC access. If active then this region base address is used to check if an access is for the.." "0,1" newline bitfld.long 0xAC 12. "SLC_NOLINEFILL,SLC cache no line fill Policy: 0= line fill on miss 1=no line fill on miss" "line fill on miss,no line fill on miss" newline bitfld.long 0xAC 10.--11. "SLC_POLICY,SLC cache Policy: 00=Bypass 01=Write Back 10 =Write Through 11=Cached Read" "Bypass,Write Back,?,?" newline bitfld.long 0xAC 9. "TLCACHE_POLICY,Tile cache Policy: 1=no line fill on miss 0=line fill on miss" "line fill on miss,no line fill on miss" newline bitfld.long 0xAC 8. "COR_COLOUR_ENABLE,Correlation Colour Enable 0=off 1=on" "off,on" newline bitfld.long 0xAC 7. "IADDR,Direct/Indirect Addressing: 1=indirect 0=direct" "direct,indirect" newline hexmask.long.byte 0xAC 0.--6. 1. "DIMY,Surface height in terms of TILE_TYPE for this memory region" line.long 0xB0 "RGX_CR_FB_MEM_REGION_CTRL4_0,Framebuffer Compression/Decompression memory regions for Host and TLA accesses" hexmask.long.byte 0xB0 25.--31. 1. "DIMY,Surface height in terms of TILE_TYPE for this memory region" newline hexmask.long.word 0xB0 12.--24. 1. "DIMX,Surface width in terms of TILE_TYPE for this memory region" newline bitfld.long 0xB0 11. "MEML,Surface Memory layout for this memory region 0=linear 1=twiddled" "linear,twiddled" newline bitfld.long 0xB0 9.--10. "DM,Data master to be used for this memory region 00 = TA/Vertex 01 = 3D/Pixel 10 = Compute 11 = Data Master of Requester If the memory region is being accessed by the TLA the data master is set to the TLA data master If the memory region is being.." "TA/Vertex,?,?,?" newline bitfld.long 0xB0 8. "TILE_TYPE,Compressor tile type 0 = 8x8 pixels 1 = 16x4 pixels" "0,1" newline hexmask.long.byte 0xB0 1.--7. 1. "FMT,The pixel format to be used in this memory region" newline bitfld.long 0xB0 0. "MODE,Defines if this memory region maps to BIF or FBC/FBDC access; 0 = BIF 1 = FBC/FBDC" "BIF,FBC/FBDC" line.long 0xB4 "RGX_CR_FB_MEM_REGION_CTRL4_1,Framebuffer Compression/Decompression memory regions for Host and TLA accesses" hexmask.long.tbyte 0xB4 15.--31. 1. "Reserved_47,Reserved_47" newline bitfld.long 0xB4 14. "PORT,Defines if this memory region is to be used by the TLA or Host port. 0 = TLA Port 1 = Host Port" "TLA Port,Host Port" newline bitfld.long 0xB4 13. "ACTIVE,Defines if this memory region is active or not default to INACTIVE. Used in conjuction with MODE field to define if a memory region maps to BIF or FBC/FBDC access. If active then this region base address is used to check if an access is for the.." "0,1" newline bitfld.long 0xB4 12. "SLC_NOLINEFILL,SLC cache no line fill Policy: 0= line fill on miss 1=no line fill on miss" "line fill on miss,no line fill on miss" newline bitfld.long 0xB4 10.--11. "SLC_POLICY,SLC cache Policy: 00=Bypass 01=Write Back 10 =Write Through 11=Cached Read" "Bypass,Write Back,?,?" newline bitfld.long 0xB4 9. "TLCACHE_POLICY,Tile cache Policy: 1=no line fill on miss 0=line fill on miss" "line fill on miss,no line fill on miss" newline bitfld.long 0xB4 8. "COR_COLOUR_ENABLE,Correlation Colour Enable 0=off 1=on" "off,on" newline bitfld.long 0xB4 7. "IADDR,Direct/Indirect Addressing: 1=indirect 0=direct" "direct,indirect" newline hexmask.long.byte 0xB4 0.--6. 1. "DIMY,Surface height in terms of TILE_TYPE for this memory region" line.long 0xB8 "RGX_CR_FB_MEM_REGION_CTRL5_0,Framebuffer Compression/Decompression memory regions for Host and TLA accesses" hexmask.long.byte 0xB8 25.--31. 1. "DIMY,Surface height in terms of TILE_TYPE for this memory region" newline hexmask.long.word 0xB8 12.--24. 1. "DIMX,Surface width in terms of TILE_TYPE for this memory region" newline bitfld.long 0xB8 11. "MEML,Surface Memory layout for this memory region 0=linear 1=twiddled" "linear,twiddled" newline bitfld.long 0xB8 9.--10. "DM,Data master to be used for this memory region 00 = TA/Vertex 01 = 3D/Pixel 10 = Compute 11 = Data Master of Requester If the memory region is being accessed by the TLA the data master is set to the TLA data master If the memory region is being.." "TA/Vertex,?,?,?" newline bitfld.long 0xB8 8. "TILE_TYPE,Compressor tile type 0 = 8x8 pixels 1 = 16x4 pixels" "0,1" newline hexmask.long.byte 0xB8 1.--7. 1. "FMT,The pixel format to be used in this memory region" newline bitfld.long 0xB8 0. "MODE,Defines if this memory region maps to BIF or FBC/FBDC access; 0 = BIF 1 = FBC/FBDC" "BIF,FBC/FBDC" line.long 0xBC "RGX_CR_FB_MEM_REGION_CTRL5_1,Framebuffer Compression/Decompression memory regions for Host and TLA accesses" hexmask.long.tbyte 0xBC 15.--31. 1. "Reserved_47,Reserved_47" newline bitfld.long 0xBC 14. "PORT,Defines if this memory region is to be used by the TLA or Host port. 0 = TLA Port 1 = Host Port" "TLA Port,Host Port" newline bitfld.long 0xBC 13. "ACTIVE,Defines if this memory region is active or not default to INACTIVE. Used in conjuction with MODE field to define if a memory region maps to BIF or FBC/FBDC access. If active then this region base address is used to check if an access is for the.." "0,1" newline bitfld.long 0xBC 12. "SLC_NOLINEFILL,SLC cache no line fill Policy: 0= line fill on miss 1=no line fill on miss" "line fill on miss,no line fill on miss" newline bitfld.long 0xBC 10.--11. "SLC_POLICY,SLC cache Policy: 00=Bypass 01=Write Back 10 =Write Through 11=Cached Read" "Bypass,Write Back,?,?" newline bitfld.long 0xBC 9. "TLCACHE_POLICY,Tile cache Policy: 1=no line fill on miss 0=line fill on miss" "line fill on miss,no line fill on miss" newline bitfld.long 0xBC 8. "COR_COLOUR_ENABLE,Correlation Colour Enable 0=off 1=on" "off,on" newline bitfld.long 0xBC 7. "IADDR,Direct/Indirect Addressing: 1=indirect 0=direct" "direct,indirect" newline hexmask.long.byte 0xBC 0.--6. 1. "DIMY,Surface height in terms of TILE_TYPE for this memory region" line.long 0xC0 "RGX_CR_FB_MEM_REGION_CTRL6_0,Framebuffer Compression/Decompression memory regions for Host and TLA accesses" hexmask.long.byte 0xC0 25.--31. 1. "DIMY,Surface height in terms of TILE_TYPE for this memory region" newline hexmask.long.word 0xC0 12.--24. 1. "DIMX,Surface width in terms of TILE_TYPE for this memory region" newline bitfld.long 0xC0 11. "MEML,Surface Memory layout for this memory region 0=linear 1=twiddled" "linear,twiddled" newline bitfld.long 0xC0 9.--10. "DM,Data master to be used for this memory region 00 = TA/Vertex 01 = 3D/Pixel 10 = Compute 11 = Data Master of Requester If the memory region is being accessed by the TLA the data master is set to the TLA data master If the memory region is being.." "TA/Vertex,?,?,?" newline bitfld.long 0xC0 8. "TILE_TYPE,Compressor tile type 0 = 8x8 pixels 1 = 16x4 pixels" "0,1" newline hexmask.long.byte 0xC0 1.--7. 1. "FMT,The pixel format to be used in this memory region" newline bitfld.long 0xC0 0. "MODE,Defines if this memory region maps to BIF or FBC/FBDC access; 0 = BIF 1 = FBC/FBDC" "BIF,FBC/FBDC" line.long 0xC4 "RGX_CR_FB_MEM_REGION_CTRL6_1,Framebuffer Compression/Decompression memory regions for Host and TLA accesses" hexmask.long.tbyte 0xC4 15.--31. 1. "Reserved_47,Reserved_47" newline bitfld.long 0xC4 14. "PORT,Defines if this memory region is to be used by the TLA or Host port. 0 = TLA Port 1 = Host Port" "TLA Port,Host Port" newline bitfld.long 0xC4 13. "ACTIVE,Defines if this memory region is active or not default to INACTIVE. Used in conjuction with MODE field to define if a memory region maps to BIF or FBC/FBDC access. If active then this region base address is used to check if an access is for the.." "0,1" newline bitfld.long 0xC4 12. "SLC_NOLINEFILL,SLC cache no line fill Policy: 0= line fill on miss 1=no line fill on miss" "line fill on miss,no line fill on miss" newline bitfld.long 0xC4 10.--11. "SLC_POLICY,SLC cache Policy: 00=Bypass 01=Write Back 10 =Write Through 11=Cached Read" "Bypass,Write Back,?,?" newline bitfld.long 0xC4 9. "TLCACHE_POLICY,Tile cache Policy: 1=no line fill on miss 0=line fill on miss" "line fill on miss,no line fill on miss" newline bitfld.long 0xC4 8. "COR_COLOUR_ENABLE,Correlation Colour Enable 0=off 1=on" "off,on" newline bitfld.long 0xC4 7. "IADDR,Direct/Indirect Addressing: 1=indirect 0=direct" "direct,indirect" newline hexmask.long.byte 0xC4 0.--6. 1. "DIMY,Surface height in terms of TILE_TYPE for this memory region" line.long 0xC8 "RGX_CR_FB_MEM_REGION_CTRL7_0,Framebuffer Compression/Decompression memory regions for Host and TLA accesses" hexmask.long.byte 0xC8 25.--31. 1. "DIMY,Surface height in terms of TILE_TYPE for this memory region" newline hexmask.long.word 0xC8 12.--24. 1. "DIMX,Surface width in terms of TILE_TYPE for this memory region" newline bitfld.long 0xC8 11. "MEML,Surface Memory layout for this memory region 0=linear 1=twiddled" "linear,twiddled" newline bitfld.long 0xC8 9.--10. "DM,Data master to be used for this memory region 00 = TA/Vertex 01 = 3D/Pixel 10 = Compute 11 = Data Master of Requester If the memory region is being accessed by the TLA the data master is set to the TLA data master If the memory region is being.." "TA/Vertex,?,?,?" newline bitfld.long 0xC8 8. "TILE_TYPE,Compressor tile type 0 = 8x8 pixels 1 = 16x4 pixels" "0,1" newline hexmask.long.byte 0xC8 1.--7. 1. "FMT,The pixel format to be used in this memory region" newline bitfld.long 0xC8 0. "MODE,Defines if this memory region maps to BIF or FBC/FBDC access; 0 = BIF 1 = FBC/FBDC" "BIF,FBC/FBDC" line.long 0xCC "RGX_CR_FB_MEM_REGION_CTRL7_1,Framebuffer Compression/Decompression memory regions for Host and TLA accesses" hexmask.long.tbyte 0xCC 15.--31. 1. "Reserved_47,Reserved_47" newline bitfld.long 0xCC 14. "PORT,Defines if this memory region is to be used by the TLA or Host port. 0 = TLA Port 1 = Host Port" "TLA Port,Host Port" newline bitfld.long 0xCC 13. "ACTIVE,Defines if this memory region is active or not default to INACTIVE. Used in conjuction with MODE field to define if a memory region maps to BIF or FBC/FBDC access. If active then this region base address is used to check if an access is for the.." "0,1" newline bitfld.long 0xCC 12. "SLC_NOLINEFILL,SLC cache no line fill Policy: 0= line fill on miss 1=no line fill on miss" "line fill on miss,no line fill on miss" newline bitfld.long 0xCC 10.--11. "SLC_POLICY,SLC cache Policy: 00=Bypass 01=Write Back 10 =Write Through 11=Cached Read" "Bypass,Write Back,?,?" newline bitfld.long 0xCC 9. "TLCACHE_POLICY,Tile cache Policy: 1=no line fill on miss 0=line fill on miss" "line fill on miss,no line fill on miss" newline bitfld.long 0xCC 8. "COR_COLOUR_ENABLE,Correlation Colour Enable 0=off 1=on" "off,on" newline bitfld.long 0xCC 7. "IADDR,Direct/Indirect Addressing: 1=indirect 0=direct" "direct,indirect" newline hexmask.long.byte 0xCC 0.--6. 1. "DIMY,Surface height in terms of TILE_TYPE for this memory region" line.long 0xD0 "RGX_CR_FB_MEM_REGION_CTRL8_0,Framebuffer Compression/Decompression memory regions for Host and TLA accesses" hexmask.long.byte 0xD0 25.--31. 1. "DIMY,Surface height in terms of TILE_TYPE for this memory region" newline hexmask.long.word 0xD0 12.--24. 1. "DIMX,Surface width in terms of TILE_TYPE for this memory region" newline bitfld.long 0xD0 11. "MEML,Surface Memory layout for this memory region 0=linear 1=twiddled" "linear,twiddled" newline bitfld.long 0xD0 9.--10. "DM,Data master to be used for this memory region 00 = TA/Vertex 01 = 3D/Pixel 10 = Compute 11 = Data Master of Requester If the memory region is being accessed by the TLA the data master is set to the TLA data master If the memory region is being.." "TA/Vertex,?,?,?" newline bitfld.long 0xD0 8. "TILE_TYPE,Compressor tile type 0 = 8x8 pixels 1 = 16x4 pixels" "0,1" newline hexmask.long.byte 0xD0 1.--7. 1. "FMT,The pixel format to be used in this memory region" newline bitfld.long 0xD0 0. "MODE,Defines if this memory region maps to BIF or FBC/FBDC access; 0 = BIF 1 = FBC/FBDC" "BIF,FBC/FBDC" line.long 0xD4 "RGX_CR_FB_MEM_REGION_CTRL8_1,Framebuffer Compression/Decompression memory regions for Host and TLA accesses" hexmask.long.tbyte 0xD4 15.--31. 1. "Reserved_47,Reserved_47" newline bitfld.long 0xD4 14. "PORT,Defines if this memory region is to be used by the TLA or Host port. 0 = TLA Port 1 = Host Port" "TLA Port,Host Port" newline bitfld.long 0xD4 13. "ACTIVE,Defines if this memory region is active or not default to INACTIVE. Used in conjuction with MODE field to define if a memory region maps to BIF or FBC/FBDC access. If active then this region base address is used to check if an access is for the.." "0,1" newline bitfld.long 0xD4 12. "SLC_NOLINEFILL,SLC cache no line fill Policy: 0= line fill on miss 1=no line fill on miss" "line fill on miss,no line fill on miss" newline bitfld.long 0xD4 10.--11. "SLC_POLICY,SLC cache Policy: 00=Bypass 01=Write Back 10 =Write Through 11=Cached Read" "Bypass,Write Back,?,?" newline bitfld.long 0xD4 9. "TLCACHE_POLICY,Tile cache Policy: 1=no line fill on miss 0=line fill on miss" "line fill on miss,no line fill on miss" newline bitfld.long 0xD4 8. "COR_COLOUR_ENABLE,Correlation Colour Enable 0=off 1=on" "off,on" newline bitfld.long 0xD4 7. "IADDR,Direct/Indirect Addressing: 1=indirect 0=direct" "direct,indirect" newline hexmask.long.byte 0xD4 0.--6. 1. "DIMY,Surface height in terms of TILE_TYPE for this memory region" line.long 0xD8 "RGX_CR_FB_MEM_REGION_CTRL9_0,Framebuffer Compression/Decompression memory regions for Host and TLA accesses" hexmask.long.byte 0xD8 25.--31. 1. "DIMY,Surface height in terms of TILE_TYPE for this memory region" newline hexmask.long.word 0xD8 12.--24. 1. "DIMX,Surface width in terms of TILE_TYPE for this memory region" newline bitfld.long 0xD8 11. "MEML,Surface Memory layout for this memory region 0=linear 1=twiddled" "linear,twiddled" newline bitfld.long 0xD8 9.--10. "DM,Data master to be used for this memory region 00 = TA/Vertex 01 = 3D/Pixel 10 = Compute 11 = Data Master of Requester If the memory region is being accessed by the TLA the data master is set to the TLA data master If the memory region is being.." "TA/Vertex,?,?,?" newline bitfld.long 0xD8 8. "TILE_TYPE,Compressor tile type 0 = 8x8 pixels 1 = 16x4 pixels" "0,1" newline hexmask.long.byte 0xD8 1.--7. 1. "FMT,The pixel format to be used in this memory region" newline bitfld.long 0xD8 0. "MODE,Defines if this memory region maps to BIF or FBC/FBDC access; 0 = BIF 1 = FBC/FBDC" "BIF,FBC/FBDC" line.long 0xDC "RGX_CR_FB_MEM_REGION_CTRL9_1,Framebuffer Compression/Decompression memory regions for Host and TLA accesses" hexmask.long.tbyte 0xDC 15.--31. 1. "Reserved_47,Reserved_47" newline bitfld.long 0xDC 14. "PORT,Defines if this memory region is to be used by the TLA or Host port. 0 = TLA Port 1 = Host Port" "TLA Port,Host Port" newline bitfld.long 0xDC 13. "ACTIVE,Defines if this memory region is active or not default to INACTIVE. Used in conjuction with MODE field to define if a memory region maps to BIF or FBC/FBDC access. If active then this region base address is used to check if an access is for the.." "0,1" newline bitfld.long 0xDC 12. "SLC_NOLINEFILL,SLC cache no line fill Policy: 0= line fill on miss 1=no line fill on miss" "line fill on miss,no line fill on miss" newline bitfld.long 0xDC 10.--11. "SLC_POLICY,SLC cache Policy: 00=Bypass 01=Write Back 10 =Write Through 11=Cached Read" "Bypass,Write Back,?,?" newline bitfld.long 0xDC 9. "TLCACHE_POLICY,Tile cache Policy: 1=no line fill on miss 0=line fill on miss" "line fill on miss,no line fill on miss" newline bitfld.long 0xDC 8. "COR_COLOUR_ENABLE,Correlation Colour Enable 0=off 1=on" "off,on" newline bitfld.long 0xDC 7. "IADDR,Direct/Indirect Addressing: 1=indirect 0=direct" "direct,indirect" newline hexmask.long.byte 0xDC 0.--6. 1. "DIMY,Surface height in terms of TILE_TYPE for this memory region" line.long 0xE0 "RGX_CR_FB_MEM_REGION_CTRL10_0,Framebuffer Compression/Decompression memory regions for Host and TLA accesses" hexmask.long.byte 0xE0 25.--31. 1. "DIMY,Surface height in terms of TILE_TYPE for this memory region" newline hexmask.long.word 0xE0 12.--24. 1. "DIMX,Surface width in terms of TILE_TYPE for this memory region" newline bitfld.long 0xE0 11. "MEML,Surface Memory layout for this memory region 0=linear 1=twiddled" "linear,twiddled" newline bitfld.long 0xE0 9.--10. "DM,Data master to be used for this memory region 00 = TA/Vertex 01 = 3D/Pixel 10 = Compute 11 = Data Master of Requester If the memory region is being accessed by the TLA the data master is set to the TLA data master If the memory region is being.." "TA/Vertex,?,?,?" newline bitfld.long 0xE0 8. "TILE_TYPE,Compressor tile type 0 = 8x8 pixels 1 = 16x4 pixels" "0,1" newline hexmask.long.byte 0xE0 1.--7. 1. "FMT,The pixel format to be used in this memory region" newline bitfld.long 0xE0 0. "MODE,Defines if this memory region maps to BIF or FBC/FBDC access; 0 = BIF 1 = FBC/FBDC" "BIF,FBC/FBDC" line.long 0xE4 "RGX_CR_FB_MEM_REGION_CTRL10_1,Framebuffer Compression/Decompression memory regions for Host and TLA accesses" hexmask.long.tbyte 0xE4 15.--31. 1. "Reserved_47,Reserved_47" newline bitfld.long 0xE4 14. "PORT,Defines if this memory region is to be used by the TLA or Host port. 0 = TLA Port 1 = Host Port" "TLA Port,Host Port" newline bitfld.long 0xE4 13. "ACTIVE,Defines if this memory region is active or not default to INACTIVE. Used in conjuction with MODE field to define if a memory region maps to BIF or FBC/FBDC access. If active then this region base address is used to check if an access is for the.." "0,1" newline bitfld.long 0xE4 12. "SLC_NOLINEFILL,SLC cache no line fill Policy: 0= line fill on miss 1=no line fill on miss" "line fill on miss,no line fill on miss" newline bitfld.long 0xE4 10.--11. "SLC_POLICY,SLC cache Policy: 00=Bypass 01=Write Back 10 =Write Through 11=Cached Read" "Bypass,Write Back,?,?" newline bitfld.long 0xE4 9. "TLCACHE_POLICY,Tile cache Policy: 1=no line fill on miss 0=line fill on miss" "line fill on miss,no line fill on miss" newline bitfld.long 0xE4 8. "COR_COLOUR_ENABLE,Correlation Colour Enable 0=off 1=on" "off,on" newline bitfld.long 0xE4 7. "IADDR,Direct/Indirect Addressing: 1=indirect 0=direct" "direct,indirect" newline hexmask.long.byte 0xE4 0.--6. 1. "DIMY,Surface height in terms of TILE_TYPE for this memory region" line.long 0xE8 "RGX_CR_FB_MEM_REGION_CTRL11_0,Framebuffer Compression/Decompression memory regions for Host and TLA accesses" hexmask.long.byte 0xE8 25.--31. 1. "DIMY,Surface height in terms of TILE_TYPE for this memory region" newline hexmask.long.word 0xE8 12.--24. 1. "DIMX,Surface width in terms of TILE_TYPE for this memory region" newline bitfld.long 0xE8 11. "MEML,Surface Memory layout for this memory region 0=linear 1=twiddled" "linear,twiddled" newline bitfld.long 0xE8 9.--10. "DM,Data master to be used for this memory region 00 = TA/Vertex 01 = 3D/Pixel 10 = Compute 11 = Data Master of Requester If the memory region is being accessed by the TLA the data master is set to the TLA data master If the memory region is being.." "TA/Vertex,?,?,?" newline bitfld.long 0xE8 8. "TILE_TYPE,Compressor tile type 0 = 8x8 pixels 1 = 16x4 pixels" "0,1" newline hexmask.long.byte 0xE8 1.--7. 1. "FMT,The pixel format to be used in this memory region" newline bitfld.long 0xE8 0. "MODE,Defines if this memory region maps to BIF or FBC/FBDC access; 0 = BIF 1 = FBC/FBDC" "BIF,FBC/FBDC" line.long 0xEC "RGX_CR_FB_MEM_REGION_CTRL11_1,Framebuffer Compression/Decompression memory regions for Host and TLA accesses" hexmask.long.tbyte 0xEC 15.--31. 1. "Reserved_47,Reserved_47" newline bitfld.long 0xEC 14. "PORT,Defines if this memory region is to be used by the TLA or Host port. 0 = TLA Port 1 = Host Port" "TLA Port,Host Port" newline bitfld.long 0xEC 13. "ACTIVE,Defines if this memory region is active or not default to INACTIVE. Used in conjuction with MODE field to define if a memory region maps to BIF or FBC/FBDC access. If active then this region base address is used to check if an access is for the.." "0,1" newline bitfld.long 0xEC 12. "SLC_NOLINEFILL,SLC cache no line fill Policy: 0= line fill on miss 1=no line fill on miss" "line fill on miss,no line fill on miss" newline bitfld.long 0xEC 10.--11. "SLC_POLICY,SLC cache Policy: 00=Bypass 01=Write Back 10 =Write Through 11=Cached Read" "Bypass,Write Back,?,?" newline bitfld.long 0xEC 9. "TLCACHE_POLICY,Tile cache Policy: 1=no line fill on miss 0=line fill on miss" "line fill on miss,no line fill on miss" newline bitfld.long 0xEC 8. "COR_COLOUR_ENABLE,Correlation Colour Enable 0=off 1=on" "off,on" newline bitfld.long 0xEC 7. "IADDR,Direct/Indirect Addressing: 1=indirect 0=direct" "direct,indirect" newline hexmask.long.byte 0xEC 0.--6. 1. "DIMY,Surface height in terms of TILE_TYPE for this memory region" line.long 0xF0 "RGX_CR_FB_MEM_REGION_CTRL12_0,Framebuffer Compression/Decompression memory regions for Host and TLA accesses" hexmask.long.byte 0xF0 25.--31. 1. "DIMY,Surface height in terms of TILE_TYPE for this memory region" newline hexmask.long.word 0xF0 12.--24. 1. "DIMX,Surface width in terms of TILE_TYPE for this memory region" newline bitfld.long 0xF0 11. "MEML,Surface Memory layout for this memory region 0=linear 1=twiddled" "linear,twiddled" newline bitfld.long 0xF0 9.--10. "DM,Data master to be used for this memory region 00 = TA/Vertex 01 = 3D/Pixel 10 = Compute 11 = Data Master of Requester If the memory region is being accessed by the TLA the data master is set to the TLA data master If the memory region is being.." "TA/Vertex,?,?,?" newline bitfld.long 0xF0 8. "TILE_TYPE,Compressor tile type 0 = 8x8 pixels 1 = 16x4 pixels" "0,1" newline hexmask.long.byte 0xF0 1.--7. 1. "FMT,The pixel format to be used in this memory region" newline bitfld.long 0xF0 0. "MODE,Defines if this memory region maps to BIF or FBC/FBDC access; 0 = BIF 1 = FBC/FBDC" "BIF,FBC/FBDC" line.long 0xF4 "RGX_CR_FB_MEM_REGION_CTRL12_1,Framebuffer Compression/Decompression memory regions for Host and TLA accesses" hexmask.long.tbyte 0xF4 15.--31. 1. "Reserved_47,Reserved_47" newline bitfld.long 0xF4 14. "PORT,Defines if this memory region is to be used by the TLA or Host port. 0 = TLA Port 1 = Host Port" "TLA Port,Host Port" newline bitfld.long 0xF4 13. "ACTIVE,Defines if this memory region is active or not default to INACTIVE. Used in conjuction with MODE field to define if a memory region maps to BIF or FBC/FBDC access. If active then this region base address is used to check if an access is for the.." "0,1" newline bitfld.long 0xF4 12. "SLC_NOLINEFILL,SLC cache no line fill Policy: 0= line fill on miss 1=no line fill on miss" "line fill on miss,no line fill on miss" newline bitfld.long 0xF4 10.--11. "SLC_POLICY,SLC cache Policy: 00=Bypass 01=Write Back 10 =Write Through 11=Cached Read" "Bypass,Write Back,?,?" newline bitfld.long 0xF4 9. "TLCACHE_POLICY,Tile cache Policy: 1=no line fill on miss 0=line fill on miss" "line fill on miss,no line fill on miss" newline bitfld.long 0xF4 8. "COR_COLOUR_ENABLE,Correlation Colour Enable 0=off 1=on" "off,on" newline bitfld.long 0xF4 7. "IADDR,Direct/Indirect Addressing: 1=indirect 0=direct" "direct,indirect" newline hexmask.long.byte 0xF4 0.--6. 1. "DIMY,Surface height in terms of TILE_TYPE for this memory region" line.long 0xF8 "RGX_CR_FB_MEM_REGION_CTRL13_0,Framebuffer Compression/Decompression memory regions for Host and TLA accesses" hexmask.long.byte 0xF8 25.--31. 1. "DIMY,Surface height in terms of TILE_TYPE for this memory region" newline hexmask.long.word 0xF8 12.--24. 1. "DIMX,Surface width in terms of TILE_TYPE for this memory region" newline bitfld.long 0xF8 11. "MEML,Surface Memory layout for this memory region 0=linear 1=twiddled" "linear,twiddled" newline bitfld.long 0xF8 9.--10. "DM,Data master to be used for this memory region 00 = TA/Vertex 01 = 3D/Pixel 10 = Compute 11 = Data Master of Requester If the memory region is being accessed by the TLA the data master is set to the TLA data master If the memory region is being.." "TA/Vertex,?,?,?" newline bitfld.long 0xF8 8. "TILE_TYPE,Compressor tile type 0 = 8x8 pixels 1 = 16x4 pixels" "0,1" newline hexmask.long.byte 0xF8 1.--7. 1. "FMT,The pixel format to be used in this memory region" newline bitfld.long 0xF8 0. "MODE,Defines if this memory region maps to BIF or FBC/FBDC access; 0 = BIF 1 = FBC/FBDC" "BIF,FBC/FBDC" line.long 0xFC "RGX_CR_FB_MEM_REGION_CTRL13_1,Framebuffer Compression/Decompression memory regions for Host and TLA accesses" hexmask.long.tbyte 0xFC 15.--31. 1. "Reserved_47,Reserved_47" newline bitfld.long 0xFC 14. "PORT,Defines if this memory region is to be used by the TLA or Host port. 0 = TLA Port 1 = Host Port" "TLA Port,Host Port" newline bitfld.long 0xFC 13. "ACTIVE,Defines if this memory region is active or not default to INACTIVE. Used in conjuction with MODE field to define if a memory region maps to BIF or FBC/FBDC access. If active then this region base address is used to check if an access is for the.." "0,1" newline bitfld.long 0xFC 12. "SLC_NOLINEFILL,SLC cache no line fill Policy: 0= line fill on miss 1=no line fill on miss" "line fill on miss,no line fill on miss" newline bitfld.long 0xFC 10.--11. "SLC_POLICY,SLC cache Policy: 00=Bypass 01=Write Back 10 =Write Through 11=Cached Read" "Bypass,Write Back,?,?" newline bitfld.long 0xFC 9. "TLCACHE_POLICY,Tile cache Policy: 1=no line fill on miss 0=line fill on miss" "line fill on miss,no line fill on miss" newline bitfld.long 0xFC 8. "COR_COLOUR_ENABLE,Correlation Colour Enable 0=off 1=on" "off,on" newline bitfld.long 0xFC 7. "IADDR,Direct/Indirect Addressing: 1=indirect 0=direct" "direct,indirect" newline hexmask.long.byte 0xFC 0.--6. 1. "DIMY,Surface height in terms of TILE_TYPE for this memory region" line.long 0x100 "RGX_CR_FB_MEM_REGION_CTRL14_0,Framebuffer Compression/Decompression memory regions for Host and TLA accesses" hexmask.long.byte 0x100 25.--31. 1. "DIMY,Surface height in terms of TILE_TYPE for this memory region" newline hexmask.long.word 0x100 12.--24. 1. "DIMX,Surface width in terms of TILE_TYPE for this memory region" newline bitfld.long 0x100 11. "MEML,Surface Memory layout for this memory region 0=linear 1=twiddled" "linear,twiddled" newline bitfld.long 0x100 9.--10. "DM,Data master to be used for this memory region 00 = TA/Vertex 01 = 3D/Pixel 10 = Compute 11 = Data Master of Requester If the memory region is being accessed by the TLA the data master is set to the TLA data master If the memory region is being.." "TA/Vertex,?,?,?" newline bitfld.long 0x100 8. "TILE_TYPE,Compressor tile type 0 = 8x8 pixels 1 = 16x4 pixels" "0,1" newline hexmask.long.byte 0x100 1.--7. 1. "FMT,The pixel format to be used in this memory region" newline bitfld.long 0x100 0. "MODE,Defines if this memory region maps to BIF or FBC/FBDC access; 0 = BIF 1 = FBC/FBDC" "BIF,FBC/FBDC" line.long 0x104 "RGX_CR_FB_MEM_REGION_CTRL14_1,Framebuffer Compression/Decompression memory regions for Host and TLA accesses" hexmask.long.tbyte 0x104 15.--31. 1. "Reserved_47,Reserved_47" newline bitfld.long 0x104 14. "PORT,Defines if this memory region is to be used by the TLA or Host port. 0 = TLA Port 1 = Host Port" "TLA Port,Host Port" newline bitfld.long 0x104 13. "ACTIVE,Defines if this memory region is active or not default to INACTIVE. Used in conjuction with MODE field to define if a memory region maps to BIF or FBC/FBDC access. If active then this region base address is used to check if an access is for the.." "0,1" newline bitfld.long 0x104 12. "SLC_NOLINEFILL,SLC cache no line fill Policy: 0= line fill on miss 1=no line fill on miss" "line fill on miss,no line fill on miss" newline bitfld.long 0x104 10.--11. "SLC_POLICY,SLC cache Policy: 00=Bypass 01=Write Back 10 =Write Through 11=Cached Read" "Bypass,Write Back,?,?" newline bitfld.long 0x104 9. "TLCACHE_POLICY,Tile cache Policy: 1=no line fill on miss 0=line fill on miss" "line fill on miss,no line fill on miss" newline bitfld.long 0x104 8. "COR_COLOUR_ENABLE,Correlation Colour Enable 0=off 1=on" "off,on" newline bitfld.long 0x104 7. "IADDR,Direct/Indirect Addressing: 1=indirect 0=direct" "direct,indirect" newline hexmask.long.byte 0x104 0.--6. 1. "DIMY,Surface height in terms of TILE_TYPE for this memory region" line.long 0x108 "RGX_CR_FB_MEM_REGION_CTRL15_0,Framebuffer Compression/Decompression memory regions for Host and TLA accesses" hexmask.long.byte 0x108 25.--31. 1. "DIMY,Surface height in terms of TILE_TYPE for this memory region" newline hexmask.long.word 0x108 12.--24. 1. "DIMX,Surface width in terms of TILE_TYPE for this memory region" newline bitfld.long 0x108 11. "MEML,Surface Memory layout for this memory region 0=linear 1=twiddled" "linear,twiddled" newline bitfld.long 0x108 9.--10. "DM,Data master to be used for this memory region 00 = TA/Vertex 01 = 3D/Pixel 10 = Compute 11 = Data Master of Requester If the memory region is being accessed by the TLA the data master is set to the TLA data master If the memory region is being.." "TA/Vertex,?,?,?" newline bitfld.long 0x108 8. "TILE_TYPE,Compressor tile type 0 = 8x8 pixels 1 = 16x4 pixels" "0,1" newline hexmask.long.byte 0x108 1.--7. 1. "FMT,The pixel format to be used in this memory region" newline bitfld.long 0x108 0. "MODE,Defines if this memory region maps to BIF or FBC/FBDC access; 0 = BIF 1 = FBC/FBDC" "BIF,FBC/FBDC" line.long 0x10C "RGX_CR_FB_MEM_REGION_CTRL15_1,Framebuffer Compression/Decompression memory regions for Host and TLA accesses" hexmask.long.tbyte 0x10C 15.--31. 1. "Reserved_47,Reserved_47" newline bitfld.long 0x10C 14. "PORT,Defines if this memory region is to be used by the TLA or Host port. 0 = TLA Port 1 = Host Port" "TLA Port,Host Port" newline bitfld.long 0x10C 13. "ACTIVE,Defines if this memory region is active or not default to INACTIVE. Used in conjuction with MODE field to define if a memory region maps to BIF or FBC/FBDC access. If active then this region base address is used to check if an access is for the.." "0,1" newline bitfld.long 0x10C 12. "SLC_NOLINEFILL,SLC cache no line fill Policy: 0= line fill on miss 1=no line fill on miss" "line fill on miss,no line fill on miss" newline bitfld.long 0x10C 10.--11. "SLC_POLICY,SLC cache Policy: 00=Bypass 01=Write Back 10 =Write Through 11=Cached Read" "Bypass,Write Back,?,?" newline bitfld.long 0x10C 9. "TLCACHE_POLICY,Tile cache Policy: 1=no line fill on miss 0=line fill on miss" "line fill on miss,no line fill on miss" newline bitfld.long 0x10C 8. "COR_COLOUR_ENABLE,Correlation Colour Enable 0=off 1=on" "off,on" newline bitfld.long 0x10C 7. "IADDR,Direct/Indirect Addressing: 1=indirect 0=direct" "direct,indirect" newline hexmask.long.byte 0x10C 0.--6. 1. "DIMY,Surface height in terms of TILE_TYPE for this memory region" line.long 0x110 "RGX_CR_FB_CDC_ZLS_0,Framebuffer Compression/Decompression configuration register for ZLS access" hexmask.long.byte 0x110 27.--31. 1. "Reserved_27,Reserved_27" newline hexmask.long.tbyte 0x110 4.--26. 1. "FBC_NUM_TILES,FBC ZLS number of compressor tiles in surface in granularity of 8x8x32dwords" newline bitfld.long 0x110 2.--3. "Reserved_2,Reserved_2" "0,1,2,3" newline bitfld.long 0x110 1. "FBC_IADDR,FBC Addressing mode 0 = direct ; 1 = indirect" "direct ;,indirect" newline bitfld.long 0x110 0. "FBDC_IADDR,FBDC Addressing mode 0 = direct ; 1 = indirect" "direct ;,indirect" line.long 0x114 "RGX_CR_FB_CDC_ZLS_1,Framebuffer Compression/Decompression configuration register for ZLS access" hexmask.long 0x114 0.--31. 1. "Reserved_27,Reserved_27" line.long 0x118 "RGX_CR_FB_0,Rascal Arbiter for FBC/FBDC arbiter modes" hexmask.long 0x118 2.--31. 1. "Reserved_2,Reserved_2" newline bitfld.long 0x118 1. "ZLSMCU_ARB_MODE,ZLS and MCU TLDecode Arbiter Mode Re-arbitrate after burst complete 0 = After each request 1 = valid dropped" "After each request,valid dropped" newline bitfld.long 0x118 0. "ZLSPBE_ARB_MODE,ZLS and PBE FBC Arbiter Mode Re-arbitrate after burst complete and 0 = After each request 1 = valid dropped" "After each request,valid dropped" line.long 0x11C "RGX_CR_FB_1,Rascal Arbiter for FBC/FBDC arbiter modes" hexmask.long 0x11C 0.--31. 1. "Reserved_2,Reserved_2" wgroup.long 0x1720++0x7 line.long 0x0 "RGX_CR_MCU_GLB_CFI_0,Global flush and invalidation control for all Texture and Data Cache. Will flush then invalidate cache if both bit 0 & bit 1 set." hexmask.long.tbyte 0x0 10.--31. 1. "Reserved_10,Reserved_10" newline bitfld.long 0x0 9. "DM_FASTRENDER,When set perform operation on fastrender data master" "0,1" newline bitfld.long 0x0 6.--8. "Reserved_6,Reserved_6" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 5. "FENCE,When set additionally perform a fence to external memory before signalling that a flush is complete" "0,1" newline bitfld.long 0x0 4. "DM_COMPUTE,When set perform operation on compute data master" "0,1" newline bitfld.long 0x0 3. "DM_PIXEL,When set perform operation on pixel data master" "0,1" newline bitfld.long 0x0 2. "DM_VERTEX,When set perform operation on vertex data master" "0,1" newline bitfld.long 0x0 1. "FLUSH,When set will flush cache based on data master" "0,1" newline bitfld.long 0x0 0. "INVALIDATE,When set will invalidate cache based on data master. This bit will also invalidate the L0 cache in the MADD and teh YUV cache in the TAG to reset the CSC coefficients." "0,1" line.long 0x4 "RGX_CR_MCU_GLB_CFI_1,Global flush and invalidation control for all Texture and Data Cache. Will flush then invalidate cache if both bit 0 & bit 1 set." hexmask.long 0x4 0.--31. 1. "Reserved_10,Reserved_10" rgroup.long 0x1728++0x7 line.long 0x0 "RGX_CR_MCU_GLB_CFI_EVENT_0,Global flush and invalidation event for all Texture and Data Cache." hexmask.long 0x0 1.--31. 1. "Reserved_1,Reserved_1" newline bitfld.long 0x0 0. "PENDING,1 Indicate there is a pending global CFI operation on the MCU" "0,1" line.long 0x4 "RGX_CR_MCU_GLB_CFI_EVENT_1,Global flush and invalidation event for all Texture and Data Cache." hexmask.long 0x4 0.--31. 1. "Reserved_1,Reserved_1" group.long 0x1730++0x17 line.long 0x0 "RGX_CR_MCU_LIMIT_0,Define the maximum number of cache lines allowed to be allocated to each Data Master within the SLC. Note that values are specified per group with a value of 0x0 denoting no limit. Also note that the specified values operate as soft.." hexmask.long.byte 0x0 24.--31. 1. "Reserved_24,Reserved_24" newline hexmask.long.byte 0x0 16.--23. 1. "DM_COMPUTE,Maximum number of cachelines which can be used by the Compute data master" newline hexmask.long.byte 0x0 8.--15. 1. "DM_PIXEL,Maximum number of cachelines which can be used by the Pixel data master" newline hexmask.long.byte 0x0 0.--7. 1. "DM_VERTEX,Maximum number of cachelines which can be used by the Vertex data master" line.long 0x4 "RGX_CR_MCU_LIMIT_1,Define the maximum number of cache lines allowed to be allocated to each Data Master within the SLC. Note that values are specified per group with a value of 0x0 denoting no limit. Also note that the specified values operate as soft.." hexmask.long 0x4 0.--31. 1. "Reserved_24,Reserved_24" line.long 0x8 "RGX_CR_MCU_CTRL_0,MCU control registers" hexmask.long.word 0x8 18.--31. 1. "Reserved_18,Reserved_18" newline bitfld.long 0x8 17. "PDSRW_L0_OFF,Turn off MCU PDSRW L0 cache" "0,1" newline hexmask.long.byte 0x8 9.--16. 1. "FBDC_REQ_THRESHOLD,Maximum number of outstanding requests each MCU group can have to the Framebuffer Decompression module" newline bitfld.long 0x8 8. "RD_OVERTAKE_THRESH_ENABLE,Enables the use of the threshold to limit the amount of overtaking which is permitted" "0,1" newline hexmask.long.byte 0x8 2.--7. 1. "RD_OVERTAKE_THRESHOLD,The number of read accesses which are permitted to overtake waiting Writebacks when enabled" newline bitfld.long 0x8 1. "INSTANCE_MERGE_DISABLE,Turn off instance merging in the MCU L1" "0,1" newline bitfld.long 0x8 0. "L1_OFF,Turn off MCU L1" "0,1" line.long 0xC "RGX_CR_MCU_CTRL_1,MCU control registers" hexmask.long 0xC 0.--31. 1. "Reserved_18,Reserved_18" line.long 0x10 "RGX_CR_MCU_FENCE_0,Defines the Data Master and Addresses used when the MCU optionally issues a Fence as part of a Flush operation. See MCU_GLB_CFI register for details." hexmask.long 0x10 5.--31. 1. "ADDR,Address value to use when issuing a Fence" newline hexmask.long.byte 0x10 0.--4. 1. "Reserved_0,Reserved_0" line.long 0x14 "RGX_CR_MCU_FENCE_1,Defines the Data Master and Addresses used when the MCU optionally issues a Fence as part of a Flush operation. See MCU_GLB_CFI register for details." hexmask.long.tbyte 0x14 11.--31. 1. "Reserved_43,Reserved_43" newline bitfld.long 0x14 8.--10. "DM,Data Master value to use when issuing a Fence" "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x14 0.--7. 1. "ADDR,Address value to use when issuing a Fence" group.long 0x1780++0x17 line.long 0x0 "RGX_CR_TPU_0,Global control to TPU_MCU_L0|tpu" hexmask.long.tbyte 0x0 9.--31. 1. "Reserved_9,Reserved_9" newline bitfld.long 0x0 8. "MCU_PDS_L0_OFF,Turn off MCU PDSL0 cache" "0,1" newline bitfld.long 0x0 7. "Reserved_7,Reserved_7" "0,1" newline bitfld.long 0x0 6. "TAG_ENABLE_MMU_PREFETCH,Enables generation of prefetch requests to the MMU" "0,1" newline bitfld.long 0x0 5. "TAG_CEM_4K_FACE_PACKING,Pixel data master. Enable 4K-byte alignment between CEM faces when set to 1. It applies for both when mipmap is enabled or disabled" "0,1" newline bitfld.long 0x0 4. "MADD_CONFIG_L0OFF,When set this disables MADD P0 L0 cache" "0,1" newline bitfld.long 0x0 3. "TAG_CEM_FACE_PACKING,Pixel data master. Enable dword alignment between CEM faces when set to 1" "0,1" newline bitfld.long 0x0 2. "TAG_CEMEDGE_DONTFILTER,Pixel data master. Disable filtering over edges/corners for CEM. When set to 1 HW will be seemfull ie always stay in the current map always honour the addressmode. When set to 0 HW will be seemless ie ignore addressmode.." "0,1" newline bitfld.long 0x0 1. "TAG_CEMGRAD_DONTNEGATE,Pixel data master. Disable negation for user supplied gradients for cem swap i. e. will only swap dudx etc not negate" "0,1" newline bitfld.long 0x0 0. "MADD_CONFIG_DXT35_TRANSOVR,When set this disables alternative mode implied by colour0 > colour1 for DXT3 to DXT5" "colour1 for DXT3 to DXT5,?" line.long 0x4 "RGX_CR_TPU_1,Global control to TPU_MCU_L0|tpu" hexmask.long 0x4 0.--31. 1. "Reserved_9,Reserved_9" line.long 0x8 "RGX_CR_TPU_YUV_CSC_COEFFICIENTS_0,Base address for the YUV CSC set of coefficients stored in memory for pixel data master" hexmask.long 0x8 0.--31. 1. "YUV_CSC_COEFFICIENTS_ADDRESS,Base address DWORD aligned for the location in memory of the CSC coefficients" line.long 0xC "RGX_CR_TPU_YUV_CSC_COEFFICIENTS_1,Base address for the YUV CSC set of coefficients stored in memory for pixel data master" hexmask.long 0xC 6.--31. 1. "Reserved_38,Reserved_38" newline hexmask.long.byte 0xC 0.--5. 1. "YUV_CSC_COEFFICIENTS_ADDRESS,Base address DWORD aligned for the location in memory of the CSC coefficients" line.long 0x10 "RGX_CR_TPU_BORDER_COLOUR_TABLE_PDM_0,Base address for the border colour table" hexmask.long 0x10 0.--31. 1. "BORDER_COLOUR_TABLE_ADDRESS,Base address DWORD aligned for the location in memory of the border colour table for the PDM" line.long 0x14 "RGX_CR_TPU_BORDER_COLOUR_TABLE_PDM_1,Base address for the border colour table" hexmask.long 0x14 6.--31. 1. "Reserved_38,Reserved_38" newline hexmask.long.byte 0x14 0.--5. 1. "BORDER_COLOUR_TABLE_ADDRESS,Base address DWORD aligned for the location in memory of the border colour table for the PDM" rgroup.long 0x1798++0x7 line.long 0x0 "RGX_CR_DUST_IDLE_0,RGX_CR_DUST_IDLE_0" hexmask.long 0x0 7.--31. 1. "Reserved_7,Reserved_7" newline bitfld.long 0x0 6. "MCU_L0_WRAP,MCU L0 WRAP Module IDLE" "0,1" newline bitfld.long 0x0 5. "MCU_L0,MCU L0 Module IDLE" "0,1" newline bitfld.long 0x0 4. "TF,TF Module IDLE" "0,1" newline bitfld.long 0x0 3. "MADD,MADD Module IDLE" "0,1" newline bitfld.long 0x0 2. "TAG,TAG Module IDLE" "0,1" newline bitfld.long 0x0 1. "USC1,USC1 Module IDLE" "0,1" newline bitfld.long 0x0 0. "USC0,USC0 Module IDLE" "0,1" line.long 0x4 "RGX_CR_DUST_IDLE_1,RGX_CR_DUST_IDLE_1" hexmask.long 0x4 0.--31. 1. "Reserved_7,Reserved_7" group.long 0x17A0++0xF line.long 0x0 "RGX_CR_TPU_BORDER_COLOUR_TABLE_VDM_0,Base address for the border colour table" hexmask.long 0x0 0.--31. 1. "BORDER_COLOUR_TABLE_ADDRESS,Base address DWORD aligned for the location in memory of the border colour table for the VDM" line.long 0x4 "RGX_CR_TPU_BORDER_COLOUR_TABLE_VDM_1,Base address for the border colour table" hexmask.long 0x4 6.--31. 1. "Reserved_38,Reserved_38" newline hexmask.long.byte 0x4 0.--5. 1. "BORDER_COLOUR_TABLE_ADDRESS,Base address DWORD aligned for the location in memory of the border colour table for the VDM" line.long 0x8 "RGX_CR_TPU_BORDER_COLOUR_TABLE_CDM_0,Base address for the border colour table" hexmask.long 0x8 0.--31. 1. "BORDER_COLOUR_TABLE_ADDRESS,Base address DWORD aligned for the location in memory of the border colour table for the CDM" line.long 0xC "RGX_CR_TPU_BORDER_COLOUR_TABLE_CDM_1,Base address for the border colour table" hexmask.long 0xC 6.--31. 1. "Reserved_38,Reserved_38" newline hexmask.long.byte 0xC 0.--5. 1. "BORDER_COLOUR_TABLE_ADDRESS,Base address DWORD aligned for the location in memory of the border colour table for the CDM" repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) rgroup.long ($2+0x17B0)++0x3 line.long 0x0 "RGX_CR_TPU_PWR_NUMBER_OF_TEXELS_$1,Peformance counter associated with Power Monitoring." hexmask.long 0x0 0.--31. 1. "VALUE,Number of texels requested per clock" repeat.end group.long 0x17B8++0xF line.long 0x0 "RGX_CR_TPU_TAG_CTRL_0,Global control to TAG for the pixel data master" hexmask.long 0x0 4.--31. 1. "Reserved_4,Reserved_4" newline bitfld.long 0x0 3. "AF_RATIO_TRUNCATE_TO_INTEGER,0 current mode 1 clear the fractional part of the calculated AF ratio" "0,1" newline bitfld.long 0x0 2. "AF_RATIO_TRUNCATE_TO_HALF,0 current mode 1 truncate the fractional part of the calculated AF ratio to 0. 5" "0,1" newline bitfld.long 0x0 1. "AF_FILTERING_MODE,0 current mode 1 new mode." "0,1" newline bitfld.long 0x0 0. "YUV_CAM_INVALIDATE,When set will invalidate YUV CSC CAM to reset the CSC coefficients. It should be set when the TPU is not performing CSC." "0,1" line.long 0x4 "RGX_CR_TPU_TAG_CTRL_1,Global control to TAG for the pixel data master" hexmask.long 0x4 0.--31. 1. "Reserved_4,Reserved_4" line.long 0x8 "RGX_CR_TPU_MADD_CTRL_0,Global control to MADD for pixel data master" hexmask.long 0x8 2.--31. 1. "Reserved_2,Reserved_2" newline bitfld.long 0x8 1. "ASTC_ODD_SCALING_ENABLE,When set ASTC encoded texels use the odd U16->F16 scaling in the TF. When zero the usual scaling will be used in TF." "0,1" newline bitfld.long 0x8 0. "ASTC_MULTICYCLE_TF_FORCE_F16,When set ASTC encoded texels that are filtered over multiple cycles by the TF will be output from the MADD as F16." "0,1" line.long 0xC "RGX_CR_TPU_MADD_CTRL_1,Global control to MADD for pixel data master" hexmask.long 0xC 0.--31. 1. "Reserved_2,Reserved_2" group.long 0x17F0++0x7 line.long 0x0 "RGX_CR_TPU_BORDER_COLOUR_TABLE_TDM_0,Base address for the border colour table" hexmask.long 0x0 0.--31. 1. "BORDER_COLOUR_TABLE_ADDRESS,Base address DWORD aligned for the location in memory of the border colour table for the TDM" line.long 0x4 "RGX_CR_TPU_BORDER_COLOUR_TABLE_TDM_1,Base address for the border colour table" hexmask.long 0x4 6.--31. 1. "Reserved_38,Reserved_38" newline hexmask.long.byte 0x4 0.--5. 1. "BORDER_COLOUR_TABLE_ADDRESS,Base address DWORD aligned for the location in memory of the border colour table for the TDM" group.long 0x18C0++0x17 line.long 0x0 "RGX_CR_TPU_LODBIASREP_CMP_MANTISSA_MASK_PDM_0,Mask for comparing mantissa of f32 LOD Bias/Replace value for PPLOD speedup for the pixel data master" hexmask.long.word 0x0 23.--31. 1. "Reserved_23,Reserved_23" newline hexmask.long.tbyte 0x0 0.--22. 1. "LODBIASREP_CMP_MANTISSA_MASK,Mask for comparing mantissa of f32 LOD Bias/Replace value for PPLOD speedup" line.long 0x4 "RGX_CR_TPU_LODBIASREP_CMP_MANTISSA_MASK_PDM_1,Mask for comparing mantissa of f32 LOD Bias/Replace value for PPLOD speedup for the pixel data master" hexmask.long 0x4 0.--31. 1. "Reserved_23,Reserved_23" line.long 0x8 "RGX_CR_TPU_LODBIASREP_CMP_MANTISSA_MASK_VDM_0,Mask for comparing mantissa of f32 LOD Bias/Replace value for PPLOD speedup for the vertex data master" hexmask.long.word 0x8 23.--31. 1. "Reserved_23,Reserved_23" newline hexmask.long.tbyte 0x8 0.--22. 1. "LODBIASREP_CMP_MANTISSA_MASK,Mask for comparing mantissa of f32 LOD Bias/Replace value for PPLOD speedup" line.long 0xC "RGX_CR_TPU_LODBIASREP_CMP_MANTISSA_MASK_VDM_1,Mask for comparing mantissa of f32 LOD Bias/Replace value for PPLOD speedup for the vertex data master" hexmask.long 0xC 0.--31. 1. "Reserved_23,Reserved_23" line.long 0x10 "RGX_CR_TPU_LODBIASREP_CMP_MANTISSA_MASK_CDM_0,Mask for comparing mantissa of f32 LOD Bias/Replace value for PPLOD speedup for the compute data master" hexmask.long.word 0x10 23.--31. 1. "Reserved_23,Reserved_23" newline hexmask.long.tbyte 0x10 0.--22. 1. "LODBIASREP_CMP_MANTISSA_MASK,Mask for comparing mantissa of f32 LOD Bias/Replace value for PPLOD speedup" line.long 0x14 "RGX_CR_TPU_LODBIASREP_CMP_MANTISSA_MASK_CDM_1,Mask for comparing mantissa of f32 LOD Bias/Replace value for PPLOD speedup for the compute data master" hexmask.long 0x14 0.--31. 1. "Reserved_23,Reserved_23" group.long 0x18E0++0x7 line.long 0x0 "RGX_CR_TPU_LODBIASREP_CMP_MANTISSA_MASK_TDM_0,Mask for comparing mantissa of f32 LOD Bias/Replace value for PPLOD speedup for the fast render data master" hexmask.long.word 0x0 23.--31. 1. "Reserved_23,Reserved_23" newline hexmask.long.tbyte 0x0 0.--22. 1. "LODBIASREP_CMP_MANTISSA_MASK,Mask for comparing mantissa of f32 LOD Bias/Replace value for PPLOD speedup" line.long 0x4 "RGX_CR_TPU_LODBIASREP_CMP_MANTISSA_MASK_TDM_1,Mask for comparing mantissa of f32 LOD Bias/Replace value for PPLOD speedup for the fast render data master" hexmask.long 0x4 0.--31. 1. "Reserved_23,Reserved_23" rgroup.long 0x2000++0xF line.long 0x0 "RGX_CR_PM_TA_MMUPAGE_STATUS_0,RGX_CR_PM_TA_MMUPAGE_STATUS_0" hexmask.long.word 0x0 22.--31. 1. "Reserved_22,Reserved_22" newline hexmask.long.tbyte 0x0 0.--21. 1. "OP,MMU pages(4KB) counter @ the TA context" line.long 0x4 "RGX_CR_PM_TA_MMUPAGE_STATUS_1,RGX_CR_PM_TA_MMUPAGE_STATUS_1" hexmask.long 0x4 0.--31. 1. "Reserved_22,Reserved_22" line.long 0x8 "RGX_CR_PM_3D_MMUPAGE_STATUS_0,RGX_CR_PM_3D_MMUPAGE_STATUS_0" hexmask.long.word 0x8 22.--31. 1. "Reserved_22,Reserved_22" newline hexmask.long.tbyte 0x8 0.--21. 1. "OP,MMU pages(4KB) counter @ the 3D context" line.long 0xC "RGX_CR_PM_3D_MMUPAGE_STATUS_1,RGX_CR_PM_3D_MMUPAGE_STATUS_1" hexmask.long 0xC 0.--31. 1. "Reserved_22,Reserved_22" group.long 0x2010++0xF line.long 0x0 "RGX_CR_PM_MMU_STACK_POLICY_0,This register enables the PM to drain pages for MMU from the dedicated mmu free list stack. (no-pagable) It is static register which can not be changed in the run-time." hexmask.long 0x0 1.--31. 1. "Reserved_1,Reserved_1" newline bitfld.long 0x0 0. "OP,when this bit is '1' PM will try to drain pages from the dedicated mmu free list stack" "0,1" line.long 0x4 "RGX_CR_PM_MMU_STACK_POLICY_1,This register enables the PM to drain pages for MMU from the dedicated mmu free list stack. (no-pagable) It is static register which can not be changed in the run-time." hexmask.long 0x4 0.--31. 1. "Reserved_1,Reserved_1" line.long 0x8 "RGX_CR_PM_TA_MMU_FSTACK_BASE_0,Effective on loading of the MMU TA free list loading . this register defines the base address of the mmu free list stack being referenced during TA processing." hexmask.long 0x8 4.--31. 1. "ADDR,1TB Addressable 128 bits aligned Base Address for MMU TA free list stack" newline hexmask.long.byte 0x8 0.--3. 1. "Reserved_0,Reserved_0" line.long 0xC "RGX_CR_PM_TA_MMU_FSTACK_BASE_1,Effective on loading of the MMU TA free list loading . this register defines the base address of the mmu free list stack being referenced during TA processing." hexmask.long.tbyte 0xC 8.--31. 1. "Reserved_40,Reserved_40" newline hexmask.long.byte 0xC 0.--7. 1. "ADDR,1TB Addressable 128 bits aligned Base Address for MMU TA free list stack" rgroup.long 0x2020++0x7 line.long 0x0 "RGX_CR_PM_TA_MMU_FSTACK_STATUS_0,Note: this is the pointer pointing to the MMU TA free stack top. (4KB page pointer)" hexmask.long.word 0x0 22.--31. 1. "Reserved_22,Reserved_22" newline hexmask.long.tbyte 0x0 0.--21. 1. "TOP,This status register indicated the mmu ta context free list pointer status." line.long 0x4 "RGX_CR_PM_TA_MMU_FSTACK_STATUS_1,Note: this is the pointer pointing to the MMU TA free stack top. (4KB page pointer)" hexmask.long 0x4 0.--31. 1. "Reserved_22,Reserved_22" group.long 0x2028++0x1F line.long 0x0 "RGX_CR_PM_TA_MMU_FSTACK_0,Defines the start of the stack pointer regarding to the MMU free list stack" hexmask.long.word 0x0 22.--31. 1. "Reserved_22,Reserved_22" newline hexmask.long.tbyte 0x0 0.--21. 1. "STARTOF_TOP,This register defines the head pointer of the mmu free list in terms of 4K free pages in the free list stack effective on a loading of the MMU TA free list" line.long 0x4 "RGX_CR_PM_TA_MMU_FSTACK_1,Defines the start of the stack pointer regarding to the MMU free list stack" hexmask.long 0x4 0.--31. 1. "Reserved_22,Reserved_22" line.long 0x8 "RGX_CR_PM_START_OF_MMU_TACONTEXT_0,RGX_CR_PM_START_OF_MMU_TACONTEXT_0" hexmask.long.word 0x8 22.--31. 1. "Reserved_22,Reserved_22" newline hexmask.long.tbyte 0x8 0.--21. 1. "ALLOCATED_MMUPAGE,Start of MMU Freelists TA pages(4KB) on loading of the MMU TA context" line.long 0xC "RGX_CR_PM_START_OF_MMU_TACONTEXT_1,RGX_CR_PM_START_OF_MMU_TACONTEXT_1" hexmask.long 0xC 0.--31. 1. "Reserved_22,Reserved_22" line.long 0x10 "RGX_CR_PM_TASK_TA_MMU_FSTACK_FREE_LOAD_0,RGX_CR_PM_TASK_TA_MMU_FSTACK_FREE_LOAD_0" hexmask.long 0x10 1.--31. 1. "Reserved_1,Reserved_1" newline bitfld.long 0x10 0. "PENDING,A write into this register will cause the TA MMU free list context to be loaded from the relevant configuration registers" "0,1" line.long 0x14 "RGX_CR_PM_TASK_TA_MMU_FSTACK_FREE_LOAD_1,RGX_CR_PM_TASK_TA_MMU_FSTACK_FREE_LOAD_1" hexmask.long 0x14 0.--31. 1. "Reserved_1,Reserved_1" line.long 0x18 "RGX_CR_PM_3D_MMU_FSTACK_BASE_0,Effective on loading of the MMU 3D free list loading . this register defines the base address of the mmu free list stack being referenced during 3D processing." hexmask.long 0x18 4.--31. 1. "ADDR,1TB Addressable 128 bits aligned Base Address for MMU TA free list stack" newline hexmask.long.byte 0x18 0.--3. 1. "Reserved_0,Reserved_0" line.long 0x1C "RGX_CR_PM_3D_MMU_FSTACK_BASE_1,Effective on loading of the MMU 3D free list loading . this register defines the base address of the mmu free list stack being referenced during 3D processing." hexmask.long.tbyte 0x1C 8.--31. 1. "Reserved_40,Reserved_40" newline hexmask.long.byte 0x1C 0.--7. 1. "ADDR,1TB Addressable 128 bits aligned Base Address for MMU TA free list stack" rgroup.long 0x2048++0x7 line.long 0x0 "RGX_CR_PM_3D_MMU_FSTACK_STATUS_0,Note: this is the pointer pointing to the MMU TA free stack top. (4KB page pointer)" hexmask.long.word 0x0 22.--31. 1. "Reserved_22,Reserved_22" newline hexmask.long.tbyte 0x0 0.--21. 1. "TOP,This status register indicated the mmu ta context free list pointer status." line.long 0x4 "RGX_CR_PM_3D_MMU_FSTACK_STATUS_1,Note: this is the pointer pointing to the MMU TA free stack top. (4KB page pointer)" hexmask.long 0x4 0.--31. 1. "Reserved_22,Reserved_22" group.long 0x2050++0x17 line.long 0x0 "RGX_CR_PM_3D_MMU_FSTACK_0,Defines the start of the stack pointer regarding to the MMU free list stack Effective on a 3D MMU fstack load" hexmask.long.word 0x0 22.--31. 1. "Reserved_22,Reserved_22" newline hexmask.long.tbyte 0x0 0.--21. 1. "STARTOF_TOP,This register defines the head pointer of the mmu free list in terms of 4K free pages in the free list stack effective on a loading of the MMU TA free list" line.long 0x4 "RGX_CR_PM_3D_MMU_FSTACK_1,Defines the start of the stack pointer regarding to the MMU free list stack Effective on a 3D MMU fstack load" hexmask.long 0x4 0.--31. 1. "Reserved_22,Reserved_22" line.long 0x8 "RGX_CR_PM_START_OF_MMU_3DCONTEXT_0,Effective on a 3D MMU fstack load" hexmask.long.word 0x8 22.--31. 1. "Reserved_22,Reserved_22" newline hexmask.long.tbyte 0x8 0.--21. 1. "ALLOCATED_MMUPAGE,Start of MMU Freelists 3D pages(4KB) on loading of the MMU TA context" line.long 0xC "RGX_CR_PM_START_OF_MMU_3DCONTEXT_1,Effective on a 3D MMU fstack load" hexmask.long 0xC 0.--31. 1. "Reserved_22,Reserved_22" line.long 0x10 "RGX_CR_PM_TASK_3D_MMU_FSTACK_FREE_LOAD_0,RGX_CR_PM_TASK_3D_MMU_FSTACK_FREE_LOAD_0" hexmask.long 0x10 1.--31. 1. "Reserved_1,Reserved_1" newline bitfld.long 0x10 0. "PENDING,A write into this register will cause the 3D MMU free list context to be loaded from the relevant configuration registers" "0,1" line.long 0x14 "RGX_CR_PM_TASK_3D_MMU_FSTACK_FREE_LOAD_1,RGX_CR_PM_TASK_3D_MMU_FSTACK_FREE_LOAD_1" hexmask.long 0x14 0.--31. 1. "Reserved_1,Reserved_1" rgroup.long 0x2068++0xF line.long 0x0 "RGX_CR_PM_MMUSTACK_LOCK_STATUS_0,RGX_CR_PM_MMUSTACK_LOCK_STATUS_0" hexmask.long 0x0 2.--31. 1. "Reserved_2,Reserved_2" newline bitfld.long 0x0 1. "TD,Bit 1: 3D MMU free list Lock Status. 0 idle/ 1 used" "0,1" newline bitfld.long 0x0 0. "TA,Bit 0: TA MMU free list Lock Status. 0 idle/ 1 used." "TA MMU free list Lock Status,?" line.long 0x4 "RGX_CR_PM_MMUSTACK_LOCK_STATUS_1,RGX_CR_PM_MMUSTACK_LOCK_STATUS_1" hexmask.long 0x4 0.--31. 1. "Reserved_2,Reserved_2" line.long 0x8 "RGX_CR_PM_MMUSTACK_LOCK_OWNER_0,RGX_CR_PM_MMUSTACK_LOCK_OWNER_0" hexmask.long 0x8 2.--31. 1. "Reserved_2,Reserved_2" newline bitfld.long 0x8 1. "TD,Bit 1 :3D free list Lock owner. 0 PMA / 1 PMD" "0,1" newline bitfld.long 0x8 0. "TA,Bit 0: TA free list Lock Owner. 0 PMA / 1 PMD." "TA free list Lock Owner,?" line.long 0xC "RGX_CR_PM_MMUSTACK_LOCK_OWNER_1,RGX_CR_PM_MMUSTACK_LOCK_OWNER_1" hexmask.long 0xC 0.--31. 1. "Reserved_2,Reserved_2" group.long 0x2078++0xF line.long 0x0 "RGX_CR_PM_3D_UFSTACK_BASE_0,Effective on load of the Unified Free List Stack. this register defines the base address of the unified free list stack being referenced." hexmask.long 0x0 4.--31. 1. "ADDR,1TB Addressable 128 bits aligned Base Address for unified free list stack base address" newline hexmask.long.byte 0x0 0.--3. 1. "Reserved_0,Reserved_0" line.long 0x4 "RGX_CR_PM_3D_UFSTACK_BASE_1,Effective on load of the Unified Free List Stack. this register defines the base address of the unified free list stack being referenced." hexmask.long.tbyte 0x4 8.--31. 1. "Reserved_40,Reserved_40" newline hexmask.long.byte 0x4 0.--7. 1. "ADDR,1TB Addressable 128 bits aligned Base Address for unified free list stack base address" line.long 0x8 "RGX_CR_PM_3D_UFSTACK_0,Note: each 16GB 4KB addressable page (22 bits) is rounded to dword aligned Effective on load of the Unified Free List Stack." hexmask.long.word 0x8 22.--31. 1. "Reserved_22,Reserved_22" newline hexmask.long.tbyte 0x8 0.--21. 1. "STARTOF_TOP,This register defines the unified free list stack pointer @ loading time. It is 4K page." line.long 0xC "RGX_CR_PM_3D_UFSTACK_1,Note: each 16GB 4KB addressable page (22 bits) is rounded to dword aligned Effective on load of the Unified Free List Stack." hexmask.long 0xC 0.--31. 1. "Reserved_22,Reserved_22" rgroup.long 0x2088++0x7 line.long 0x0 "RGX_CR_PM_3D_UFSTACK_STATUS_0,Note: this is the pointer pointing to the ufstack top. (4KB page pointer)" hexmask.long.word 0x0 22.--31. 1. "Reserved_22,Reserved_22" newline hexmask.long.tbyte 0x0 0.--21. 1. "TOP,This status register indicated the unified free list stack pointer status." line.long 0x4 "RGX_CR_PM_3D_UFSTACK_STATUS_1,Note: this is the pointer pointing to the ufstack top. (4KB page pointer)" hexmask.long 0x4 0.--31. 1. "Reserved_22,Reserved_22" repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) group.long ($2+0x2090)++0x3 line.long 0x0 "RGX_CR_PM_START_OF_3D_UFSTACK_$1,Effective on load of the Unified Free List Stack." hexmask.long.word 0x0 22.--31. 1. "Reserved_22,Reserved_22" newline hexmask.long.tbyte 0x0 0.--21. 1. "ALLOCATED_PAGE,Start of TA pages(4KB) on loading of the Unified Free List Stack" repeat.end rgroup.long 0x2098++0xF line.long 0x0 "RGX_CR_PM_3D_UFSTACK_PAGE_STATUS_0,RGX_CR_PM_3D_UFSTACK_PAGE_STATUS_0" hexmask.long.word 0x0 22.--31. 1. "Reserved_22,Reserved_22" newline hexmask.long.tbyte 0x0 0.--21. 1. "OP,The number of Unified Free list pages currently allocated for the TA" line.long 0x4 "RGX_CR_PM_3D_UFSTACK_PAGE_STATUS_1,RGX_CR_PM_3D_UFSTACK_PAGE_STATUS_1" hexmask.long 0x4 0.--31. 1. "Reserved_22,Reserved_22" line.long 0x8 "RGX_CR_PM_3D_UFSTACK_MMUPAGE_STATUS_0,RGX_CR_PM_3D_UFSTACK_MMUPAGE_STATUS_0" hexmask.long.word 0x8 22.--31. 1. "Reserved_22,Reserved_22" newline hexmask.long.tbyte 0x8 0.--21. 1. "OP,The number of Unified Free list pages currently allocated for the MMU" line.long 0xC "RGX_CR_PM_3D_UFSTACK_MMUPAGE_STATUS_1,RGX_CR_PM_3D_UFSTACK_MMUPAGE_STATUS_1" hexmask.long 0xC 0.--31. 1. "Reserved_22,Reserved_22" group.long 0x20A8++0x1F line.long 0x0 "RGX_CR_PM_TASK_3D_UFSTACK_LOAD_0,RGX_CR_PM_TASK_3D_UFSTACK_LOAD_0" hexmask.long 0x0 1.--31. 1. "Reserved_1,Reserved_1" newline bitfld.long 0x0 0. "PENDING,pending status register corresponding to the ustack loading operation it will become '1' when this pm_task_ufstack_load being written and deassert until the operation is done" "0,1" line.long 0x4 "RGX_CR_PM_TASK_3D_UFSTACK_LOAD_1,RGX_CR_PM_TASK_3D_UFSTACK_LOAD_1" hexmask.long 0x4 0.--31. 1. "Reserved_1,Reserved_1" line.long 0x8 "RGX_CR_PM_TASK_TA_UFSTACK_LOAD_0,RGX_CR_PM_TASK_TA_UFSTACK_LOAD_0" hexmask.long 0x8 1.--31. 1. "Reserved_1,Reserved_1" newline bitfld.long 0x8 0. "PENDING,pending status register corresponding to the ustack loading operation it will become '1' when this pm_task_ufstack_load being written and deassert until the operation is done" "0,1" line.long 0xC "RGX_CR_PM_TASK_TA_UFSTACK_LOAD_1,RGX_CR_PM_TASK_TA_UFSTACK_LOAD_1" hexmask.long 0xC 0.--31. 1. "Reserved_1,Reserved_1" line.long 0x10 "RGX_CR_PM_TA_UFSTACK_BASE_0,Effective on load of the Unified Free List Stack. this register defines the base address of the unified free list stack being referenced." hexmask.long 0x10 4.--31. 1. "ADDR,1TB Addressable 128 bits aligned Base Address for unified free list stack base address" newline hexmask.long.byte 0x10 0.--3. 1. "Reserved_0,Reserved_0" line.long 0x14 "RGX_CR_PM_TA_UFSTACK_BASE_1,Effective on load of the Unified Free List Stack. this register defines the base address of the unified free list stack being referenced." hexmask.long.tbyte 0x14 8.--31. 1. "Reserved_40,Reserved_40" newline hexmask.long.byte 0x14 0.--7. 1. "ADDR,1TB Addressable 128 bits aligned Base Address for unified free list stack base address" line.long 0x18 "RGX_CR_PM_TA_UFSTACK_0,Note: each 16GB 4KB addressable page (22 bits) is rounded to dword aligned Effective on the loading of the Unified Free List Stack." hexmask.long.word 0x18 22.--31. 1. "Reserved_22,Reserved_22" newline hexmask.long.tbyte 0x18 0.--21. 1. "STARTOF_TOP,This register defines the unified free list stack pointer @ loading time. It is 4K page." line.long 0x1C "RGX_CR_PM_TA_UFSTACK_1,Note: each 16GB 4KB addressable page (22 bits) is rounded to dword aligned Effective on the loading of the Unified Free List Stack." hexmask.long 0x1C 0.--31. 1. "Reserved_22,Reserved_22" rgroup.long 0x20C8++0x7 line.long 0x0 "RGX_CR_PM_TA_UFSTACK_STATUS_0,Note: this is the pointer pointing to the ufstack top. (4KB page pointer)" hexmask.long.word 0x0 22.--31. 1. "Reserved_22,Reserved_22" newline hexmask.long.tbyte 0x0 0.--21. 1. "TOP,This status register indicated the unified free list stack pointer status." line.long 0x4 "RGX_CR_PM_TA_UFSTACK_STATUS_1,Note: this is the pointer pointing to the ufstack top. (4KB page pointer)" hexmask.long 0x4 0.--31. 1. "Reserved_22,Reserved_22" repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) group.long ($2+0x20D0)++0x3 line.long 0x0 "RGX_CR_PM_START_OF_TA_UFSTACK_$1,RGX_CR_PM_START_OF_TA_UFSTACK_0" hexmask.long.word 0x0 22.--31. 1. "Reserved_22,Reserved_22" newline hexmask.long.tbyte 0x0 0.--21. 1. "ALLOCATED_PAGE,Start of TA pages(4KB) on loading of the Unified Free List Stack" repeat.end rgroup.long 0x20D8++0x1F line.long 0x0 "RGX_CR_PM_TA_UFSTACK_PAGE_STATUS_0,RGX_CR_PM_TA_UFSTACK_PAGE_STATUS_0" hexmask.long.word 0x0 22.--31. 1. "Reserved_22,Reserved_22" newline hexmask.long.tbyte 0x0 0.--21. 1. "OP,The number of Unified Free list pages currently allocated for the TA" line.long 0x4 "RGX_CR_PM_TA_UFSTACK_PAGE_STATUS_1,RGX_CR_PM_TA_UFSTACK_PAGE_STATUS_1" hexmask.long 0x4 0.--31. 1. "Reserved_22,Reserved_22" line.long 0x8 "RGX_CR_PM_TA_UFSTACK_MMUPAGE_STATUS_0,RGX_CR_PM_TA_UFSTACK_MMUPAGE_STATUS_0" hexmask.long.word 0x8 22.--31. 1. "Reserved_22,Reserved_22" newline hexmask.long.tbyte 0x8 0.--21. 1. "OP,The number of Unified Free list pages currently allocated for the MMU" line.long 0xC "RGX_CR_PM_TA_UFSTACK_MMUPAGE_STATUS_1,RGX_CR_PM_TA_UFSTACK_MMUPAGE_STATUS_1" hexmask.long 0xC 0.--31. 1. "Reserved_22,Reserved_22" line.long 0x10 "RGX_CR_PM_UFSTACK_LOCK_STATUS_0,In rogue architecture. there is a unified free list whereby shared across multiple context. This lock status indicating the stack owner at the time being. Note PMA and PMD can not acquire the lock @ the same time" hexmask.long 0x10 2.--31. 1. "Reserved_2,Reserved_2" newline bitfld.long 0x10 1. "PMD,Bit 1: Page DeAllocation Manger is grabing the lock. 0:idle/ 1 used." "idle/ 1 used,Page DeAllocation Manger is grabing the lock" newline bitfld.long 0x10 0. "PMA,Bit 0: Page Allocation Manger is grabing the lock. 0:idle/ 1 used." "idle/ 1 used,?" line.long 0x14 "RGX_CR_PM_UFSTACK_LOCK_STATUS_1,In rogue architecture. there is a unified free list whereby shared across multiple context. This lock status indicating the stack owner at the time being. Note PMA and PMD can not acquire the lock @ the same time" hexmask.long 0x14 0.--31. 1. "Reserved_2,Reserved_2" line.long 0x18 "RGX_CR_PM_UFSTACK_LOCK_OWNER_0,RGX_CR_PM_UFSTACK_LOCK_OWNER_0" hexmask.long 0x18 2.--31. 1. "Reserved_2,Reserved_2" newline bitfld.long 0x18 1. "TD,Bit 1 :3D free list Lock owner. 0 PMA / 1 PMD" "0,1" newline bitfld.long 0x18 0. "TA,Bit 0: TA free list Lock Owner. 0 PMA / 1 PMD." "TA free list Lock Owner,?" line.long 0x1C "RGX_CR_PM_UFSTACK_LOCK_OWNER_1,RGX_CR_PM_UFSTACK_LOCK_OWNER_1" hexmask.long 0x1C 0.--31. 1. "Reserved_2,Reserved_2" group.long 0x20F8++0x1F line.long 0x0 "RGX_CR_PM_UFSTACK_POLICY_0,This register enables the PM to drain pages from the unified free list stack It is a static configuration register" hexmask.long 0x0 1.--31. 1. "Reserved_1,Reserved_1" newline bitfld.long 0x0 0. "OP,when this bit is '1' PM will try to drain pages from the unified free list stack as long as the ta free list do not have enough pages for the allocation" "0,1" line.long 0x4 "RGX_CR_PM_UFSTACK_POLICY_1,This register enables the PM to drain pages from the unified free list stack It is a static configuration register" hexmask.long 0x4 0.--31. 1. "Reserved_1,Reserved_1" line.long 0x8 "RGX_CR_PM_VFP_TRAN_EN_0,This register enables the PM to another level of transfrom which is from Virtial Page to VirtualPhysical Page number" hexmask.long 0x8 1.--31. 1. "Reserved_1,Reserved_1" newline bitfld.long 0x8 0. "OP,when this bit is '1' PM will try to another level of lookup between virtual page and the virtual physical page" "0,1" line.long 0xC "RGX_CR_PM_VFP_TRAN_EN_1,This register enables the PM to another level of transfrom which is from Virtial Page to VirtualPhysical Page number" hexmask.long 0xC 0.--31. 1. "Reserved_1,Reserved_1" line.long 0x10 "RGX_CR_PM_TA_VFP_TABLE_BASE_0,Effective on loading TA context. this register defines the base address of the virtual-physical page table during TA processing." hexmask.long 0x10 4.--31. 1. "ADDR,1TB Addressable 128 bits aligned Base Address for TA context page tables in the DPM module" newline hexmask.long.byte 0x10 0.--3. 1. "Reserved_0,Reserved_0" line.long 0x14 "RGX_CR_PM_TA_VFP_TABLE_BASE_1,Effective on loading TA context. this register defines the base address of the virtual-physical page table during TA processing." hexmask.long.tbyte 0x14 8.--31. 1. "Reserved_40,Reserved_40" newline hexmask.long.byte 0x14 0.--7. 1. "ADDR,1TB Addressable 128 bits aligned Base Address for TA context page tables in the DPM module" line.long 0x18 "RGX_CR_PM_3D_VFP_TABLE_BASE_0,Effective on loading 3D context. this register defines the base address of the virtual-physical page table during 3D processing." hexmask.long 0x18 4.--31. 1. "ADDR,1TB Addressable 128 bits aligned Base Address for 3D context page tables in the DPM module" newline hexmask.long.byte 0x18 0.--3. 1. "Reserved_0,Reserved_0" line.long 0x1C "RGX_CR_PM_3D_VFP_TABLE_BASE_1,Effective on loading 3D context. this register defines the base address of the virtual-physical page table during 3D processing." hexmask.long.tbyte 0x1C 8.--31. 1. "Reserved_40,Reserved_40" newline hexmask.long.byte 0x1C 0.--7. 1. "ADDR,1TB Addressable 128 bits aligned Base Address for 3D context page tables in the DPM module" wgroup.long 0x2600++0x7 line.long 0x0 "RGX_CR_TDM_START_0,A write of '1' to this register starts the 2D Data Master (TDM) reading the control stream contained in the circular buffer pointed to by TDM_CB_BASE_ADDR" hexmask.long 0x0 1.--31. 1. "Reserved_1,Reserved_1" newline bitfld.long 0x0 0. "PULSE,Start TDM" "0,1" line.long 0x4 "RGX_CR_TDM_START_1,A write of '1' to this register starts the 2D Data Master (TDM) reading the control stream contained in the circular buffer pointed to by TDM_CB_BASE_ADDR" hexmask.long 0x4 0.--31. 1. "Reserved_1,Reserved_1" group.long 0x2608++0x27 line.long 0x0 "RGX_CR_TDM_CB_BASE_0,TDM Circular Buffer base dddress" hexmask.long.tbyte 0x0 12.--31. 1. "ADDR,1 TB range 4KB aligned base address for TDM control stream circular buffer" newline hexmask.long.word 0x0 0.--11. 1. "Reserved_0,Reserved_0" line.long 0x4 "RGX_CR_TDM_CB_BASE_1,TDM Circular Buffer base dddress" hexmask.long.tbyte 0x4 8.--31. 1. "Reserved_40,Reserved_40" newline hexmask.long.byte 0x4 0.--7. 1. "ADDR,1 TB range 4KB aligned base address for TDM control stream circular buffer" line.long 0x8 "RGX_CR_TDM_CB_0,TDM Circular Buffer Size in 256-bit words" hexmask.long.word 0x8 20.--31. 1. "Reserved_20,Reserved_20" newline hexmask.long.word 0x8 5.--19. 1. "SIZE,1MB range 256-bit granular TDM Circular Buffer Size" newline hexmask.long.byte 0x8 0.--4. 1. "Reserved_0,Reserved_0" line.long 0xC "RGX_CR_TDM_CB_1,TDM Circular Buffer Size in 256-bit words" hexmask.long 0xC 0.--31. 1. "Reserved_20,Reserved_20" line.long 0x10 "RGX_CR_TDM_CB_QUEUE_0,TDM Circular Buffer Queue Control Base Address" hexmask.long 0x10 5.--31. 1. "CTRL_BASE_ADDR,1 TB range 256-bit aligned base address for TDM queue control structure" newline hexmask.long.byte 0x10 0.--4. 1. "Reserved_0,Reserved_0" line.long 0x14 "RGX_CR_TDM_CB_QUEUE_1,TDM Circular Buffer Queue Control Base Address" hexmask.long.tbyte 0x14 8.--31. 1. "Reserved_40,Reserved_40" newline hexmask.long.byte 0x14 0.--7. 1. "CTRL_BASE_ADDR,1 TB range 256-bit aligned base address for TDM queue control structure" line.long 0x18 "RGX_CR_TDM_CB_WRITE_POINTER_GUARD_0,TDM Circular Buffer Write Pointer Guard Size. TDM will refresh it's local copy of the Queue Control Write Pointer from memory when the Read Pointer is within the Guard Size of the Write Pointer." hexmask.long.word 0x18 20.--31. 1. "Reserved_20,Reserved_20" newline hexmask.long.word 0x18 5.--19. 1. "SIZE,1MB range 256-bit granular Write Pointer Guard Size" newline hexmask.long.byte 0x18 0.--4. 1. "Reserved_0,Reserved_0" line.long 0x1C "RGX_CR_TDM_CB_WRITE_POINTER_GUARD_1,TDM Circular Buffer Write Pointer Guard Size. TDM will refresh it's local copy of the Queue Control Write Pointer from memory when the Read Pointer is within the Guard Size of the Write Pointer." hexmask.long 0x1C 0.--31. 1. "Reserved_20,Reserved_20" line.long 0x20 "RGX_CR_TDM_CB_READ_POINTER_UPDATE_0,TDM Circular Buffer Read Pointer Update Frequency. the TDM will update the Queue Control Read Pointer value in memory whenever the Read Pointer has moved by this amount since the last memory write." hexmask.long.word 0x20 20.--31. 1. "Reserved_20,Reserved_20" newline hexmask.long.word 0x20 5.--19. 1. "FREQUENCY,1MB range 256-bit granular Read Pointer Update Frequency" newline hexmask.long.byte 0x20 0.--4. 1. "Reserved_0,Reserved_0" line.long 0x24 "RGX_CR_TDM_CB_READ_POINTER_UPDATE_1,TDM Circular Buffer Read Pointer Update Frequency. the TDM will update the Queue Control Read Pointer value in memory whenever the Read Pointer has moved by this amount since the last memory write." hexmask.long 0x24 0.--31. 1. "Reserved_20,Reserved_20" rgroup.long 0x2630++0x7 line.long 0x0 "RGX_CR_TDM_CB_READ_0,TDM Circular Buffer Read Pointer - current working position of TDM within 2D circular buffer. updated on a BLIT granularity" hexmask.long.word 0x0 20.--31. 1. "Reserved_20,Reserved_20" newline hexmask.long.tbyte 0x0 2.--19. 1. "POINTER,1MB range 32-bit granular Read Pointer" newline bitfld.long 0x0 0.--1. "Reserved_0,Reserved_0" "0,1,2,3" line.long 0x4 "RGX_CR_TDM_CB_READ_1,TDM Circular Buffer Read Pointer - current working position of TDM within 2D circular buffer. updated on a BLIT granularity" hexmask.long 0x4 0.--31. 1. "Reserved_20,Reserved_20" wgroup.long 0x2638++0xF line.long 0x0 "RGX_CR_TDM_RESUME_0,A write of '1' to this register resumes the TDM after 2D circular buffer empty failures." hexmask.long 0x0 1.--31. 1. "Reserved_1,Reserved_1" newline bitfld.long 0x0 0. "PULSE,Resume TDM" "0,1" line.long 0x4 "RGX_CR_TDM_RESUME_1,A write of '1' to this register resumes the TDM after 2D circular buffer empty failures." hexmask.long 0x4 0.--31. 1. "Reserved_1,Reserved_1" line.long 0x8 "RGX_CR_TDM_CONTEXT_STORE_0,Writing '1' to this register starts the TDM context store operation." hexmask.long 0x8 1.--31. 1. "Reserved_1,Reserved_1" newline bitfld.long 0x8 0. "PULSE,PULSE" "0,1" line.long 0xC "RGX_CR_TDM_CONTEXT_STORE_1,Writing '1' to this register starts the TDM context store operation." hexmask.long 0xC 0.--31. 1. "Reserved_1,Reserved_1" group.long 0x2648++0x7 line.long 0x0 "RGX_CR_TDM_CONTEXT_STATE_BASE_0,The base address in external memory of the TDM's context state buffer. to which it will store its snapshot state on a context store and from which it will reload on a TDM start pulse." hexmask.long 0x0 6.--31. 1. "ADDR,1TB range 512-bit aligned base address" newline hexmask.long.byte 0x0 0.--5. 1. "Reserved_0,Reserved_0" line.long 0x4 "RGX_CR_TDM_CONTEXT_STATE_BASE_1,The base address in external memory of the TDM's context state buffer. to which it will store its snapshot state on a context store and from which it will reload on a TDM start pulse." hexmask.long.tbyte 0x4 8.--31. 1. "Reserved_40,Reserved_40" newline hexmask.long.byte 0x4 0.--7. 1. "ADDR,1TB range 512-bit aligned base address" repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) rgroup.long ($2+0x2650)++0x3 line.long 0x0 "RGX_CR_TDM_FENCE_$1,TDM fence counters" hexmask.long 0x0 0.--31. 1. "COUNT,Count of the number of fence received reset to 0 on TDM_START_PULSE" repeat.end group.long 0x2658++0x7 line.long 0x0 "RGX_CR_TDM_YUV_CSC_COEFFICIENTS_0,Base address for the YUV CSC set of coefficients stored in memory for pixel data master" hexmask.long 0x0 0.--31. 1. "COEFFICIENTS,Base address DWORD aligned for the location in memory of the CSC coefficients" line.long 0x4 "RGX_CR_TDM_YUV_CSC_COEFFICIENTS_1,Base address for the YUV CSC set of coefficients stored in memory for pixel data master" hexmask.long 0x4 6.--31. 1. "Reserved_38,Reserved_38" newline hexmask.long.byte 0x4 0.--5. 1. "COEFFICIENTS,Base address DWORD aligned for the location in memory of the CSC coefficients" group.long 0x2678++0x7 line.long 0x0 "RGX_CR_TDM_WORKLOAD_0,TDM workload priority policy." hexmask.long 0x0 2.--31. 1. "Reserved_2,Reserved_2" newline bitfld.long 0x0 0.--1. "PRIORITY,0: Equal priority; 1: 3D has priority; 2: TDM has priority; 3: Reserved" "Equal priority;,?,TDM has priority;,Reserved" line.long 0x4 "RGX_CR_TDM_WORKLOAD_1,TDM workload priority policy." hexmask.long 0x4 0.--31. 1. "Reserved_2,Reserved_2" group.long 0x3800++0x7 line.long 0x0 "RGX_CR_SLC_CTRL_MISC_0,SLC control registers" hexmask.long.byte 0x0 24.--31. 1. "Reserved_24,Reserved_24" newline hexmask.long.byte 0x0 16.--23. 1. "ADDR_DECODE_MODE,Address decoding used to determine cache bank from the address: 0x00 = Bit 6 = 64 byte 0x01 = Bit 7 = 128 byte 0x10 = Simple XOR based address hash 1 see SLC TRM 0x11 = Simple XOR based address hash 2 see SLC TRM 0x20 = PVR address.." newline hexmask.long.byte 0x0 9.--15. 1. "Reserved_9,Reserved_9" newline bitfld.long 0x0 8. "PAUSE,Pause the SLC" "0,1" newline hexmask.long.byte 0x0 4.--7. 1. "Reserved_4,Reserved_4" newline bitfld.long 0x0 3. "RESP_PRIORITY,Priority setting between Hit and Miss on return response. Default is round robin and set to 1 if miss needs priority over hit" "0,1" newline bitfld.long 0x0 2. "ENABLE_LINE_USE_LIMIT,Enable the use of cache line limits" "0,1" newline bitfld.long 0x0 1. "ENABLE_PSG_HAZARD_CHECK,Enable the hazard checking of PSG writes only turn off if strict write ordering is guaranteed in the memory fabric" "0,1" newline bitfld.long 0x0 0. "BYPASS_BURST_COMBINER,Disable the burst combiner on the external memory interface" "0,1" line.long 0x4 "RGX_CR_SLC_CTRL_MISC_1,SLC control registers" hexmask.long 0x4 0.--31. 1. "SCRAMBLE_BITS,Pattern of bits used to determine the Cache Bank in Address Decode mode 0x21. The actual Cache Bank to use is determined by indexing into the 32 Scramble Bits using the 5 LSB's of the Hash result and then XORing this with Bit 6 of the.." wgroup.long 0x3808++0x17 line.long 0x0 "RGX_CR_SLC_CTRL_INVAL_0,SLC Invalidate control. Note that per Data Master operations only invalidate entries that have been referenced solely by the specified Data Master. any cache lines referenced by multiple Data Masters will not be affected by a per.." bitfld.long 0x0 31. "LAZY,Advanced mode of operation whereby other requestors are not blocked whilst the Invalidate is in progress" "0,1" newline hexmask.long.tbyte 0x0 9.--30. 1. "Reserved_9,Reserved_9" newline bitfld.long 0x0 8. "DM_FRC,When set invalidate all SLC entries referenced solely by the FRC Video Core (Optional feature)" "0,1" newline bitfld.long 0x0 7. "DM_VXE,When set invalidate all SLC entries referenced solely by the VXE Video Core (Optional feature)" "0,1" newline bitfld.long 0x0 6. "DM_VXD,When set invalidate all SLC entries referenced solely by the VXD Video Core (Optional feature)" "0,1" newline bitfld.long 0x0 5. "DM_HOST_META,When set invalidate all SLC entries referenced solely by the HOST or META" "0,1" newline bitfld.long 0x0 4. "DM_MMU,When set invalidate all SLC entries referenced solely by the MMU" "0,1" newline bitfld.long 0x0 3. "DM_COMPUTE,When set invalidate all SLC entries referenced solely by the COMPUTE data master" "0,1" newline bitfld.long 0x0 2. "DM_PIXEL,When set invalidate all SLC entries referenced solely by the PIXEL data master" "0,1" newline bitfld.long 0x0 1. "DM_TA,When set invalidate all SLC entries referenced solely by the TA group which includes VERTEX TESSELLATOR & STREAM_OUT data masters" "0,1" newline bitfld.long 0x0 0. "ALL,When set invalidate all SLC entries" "0,1" line.long 0x4 "RGX_CR_SLC_CTRL_INVAL_1,SLC Invalidate control. Note that per Data Master operations only invalidate entries that have been referenced solely by the specified Data Master. any cache lines referenced by multiple Data Masters will not be affected by a per.." hexmask.long 0x4 0.--31. 1. "Reserved_32,Reserved_32" line.long 0x8 "RGX_CR_SLC_CTRL_FLUSH_0,SLC Flush control. Note that per Data Master operations will flush any cache lines that have been made dirty by any writes from the specified Data Master." bitfld.long 0x8 31. "LAZY,Advanced mode of operation whereby other requestors are not blocked whilst the Flush is in progress" "0,1" newline hexmask.long.tbyte 0x8 9.--30. 1. "Reserved_9,Reserved_9" newline bitfld.long 0x8 8. "DM_FRC,When set flush all SLC entries made dirty by the FRC Video Core (Optional feature)" "0,1" newline bitfld.long 0x8 7. "DM_VXE,When set flush all SLC entries made dirty by the VXE Video Core (Optional feature)" "0,1" newline bitfld.long 0x8 6. "DM_VXD,When set flush all SLC entries made dirty by the VXD Video Core (Optional feature)" "0,1" newline bitfld.long 0x8 5. "DM_HOST_META,When set flush all SLC entries made dirty by the HOST or META" "0,1" newline bitfld.long 0x8 4. "DM_MMU,When set flush all SLC entries made dirty by the MMU" "0,1" newline bitfld.long 0x8 3. "DM_COMPUTE,When set flush all SLC entries made dirty by the COMPUTE data master" "0,1" newline bitfld.long 0x8 2. "DM_PIXEL,When set flush all SLC entries made dirty by the PIXEL data master" "0,1" newline bitfld.long 0x8 1. "DM_TA,When set flush all SLC entries made dirty by the TA group which includes VERTEX TESSELLATOR & STREAM_OUT data masters" "0,1" newline bitfld.long 0x8 0. "ALL,When set flush all SLC entries" "0,1" line.long 0xC "RGX_CR_SLC_CTRL_FLUSH_1,SLC Flush control. Note that per Data Master operations will flush any cache lines that have been made dirty by any writes from the specified Data Master." hexmask.long 0xC 0.--31. 1. "Reserved_32,Reserved_32" line.long 0x10 "RGX_CR_SLC_CTRL_FLUSH_INVAL_0,SLC Flush & Invalidate control. Note that per Data Master operations will flush any cache lines that have been made dirty by any writes from the specified Data Master. Combined Invalidate operation then only invalidates.." bitfld.long 0x10 31. "LAZY,Advanced mode of operation whereby other requestors are not blocked whilst the Flush Invalidate is in progress" "0,1" newline hexmask.long.tbyte 0x10 9.--30. 1. "Reserved_9,Reserved_9" newline bitfld.long 0x10 8. "DM_FRC,When set flush all SLC entries made dirty by the FRC Video Core then invalidate all SLC entries referenced solely by the FRC Video Core (Optional feature)" "0,1" newline bitfld.long 0x10 7. "DM_VXE,When set flush all SLC entries made dirty by the VXE Video Core then invalidate all SLC entries referenced solely by the VXE Video Core (Optional feature)" "0,1" newline bitfld.long 0x10 6. "DM_VXD,When set flush all SLC entries made dirty by the VXD Video Core then invalidate all SLC entries referenced solely by the VXD Video Core (Optional feature)" "0,1" newline bitfld.long 0x10 5. "DM_HOST_META,When set flush all SLC entries made dirty by the HOST or META then invalidate all SLC entries referenced solely by the HOST or META" "0,1" newline bitfld.long 0x10 4. "DM_MMU,When set flush all SLC entries made dirty by the MMU then invalidate all SLC entries referenced solely by the MMU" "0,1" newline bitfld.long 0x10 3. "DM_COMPUTE,When set flush all SLC entries made dirty by the COMPUTE data master then invalidate all SLC entries referenced solely by the COMPUTE data master" "0,1" newline bitfld.long 0x10 2. "DM_PIXEL,When set flush all SLC entries made dirty by the PIXEL data master then invalidate all SLC entries referenced solely by the PIXEL data master" "0,1" newline bitfld.long 0x10 1. "DM_TA,When set flush all SLC entries made dirty by the TA group which includes VERTEX TESSELLATOR & STREAM_OUT data masters then invalidate all SLC entries referenced solely by the TA group which includes VERTEX TESSELLATOR & STREAM_OUT data masters" "0,1" newline bitfld.long 0x10 0. "ALL,When set flush all SLC entries then invalidate all SLC entries" "0,1" line.long 0x14 "RGX_CR_SLC_CTRL_FLUSH_INVAL_1,SLC Flush & Invalidate control. Note that per Data Master operations will flush any cache lines that have been made dirty by any writes from the specified Data Master. Combined Invalidate operation then only invalidates.." hexmask.long 0x14 0.--31. 1. "Reserved_32,Reserved_32" rgroup.long 0x3820++0x7 line.long 0x0 "RGX_CR_SLC_STATUS0_0,Current status of Flush / Invalidate operations within the SLC" hexmask.long 0x0 3.--31. 1. "Reserved_3,Reserved_3" newline bitfld.long 0x0 2. "FLUSH_INVAL_PENDING,1 indicates there is a pending request to perform a combined Flush Invalidate on the SLC" "0,1" newline bitfld.long 0x0 1. "INVAL_PENDING,1 indicates there is a pending request to Invalidate the SLC" "0,1" newline bitfld.long 0x0 0. "FLUSH_PENDING,1 indicates there is a pending request to Flush the SLC" "0,1" line.long 0x4 "RGX_CR_SLC_STATUS0_1,Current status of Flush / Invalidate operations within the SLC" hexmask.long 0x4 0.--31. 1. "Reserved_3,Reserved_3" group.long 0x3828++0x7 line.long 0x0 "RGX_CR_SLC_CTRL_BYPASS_0,SLC Bypass control" bitfld.long 0x0 31. "DM_FASTRENDER,Bypass SLC the TDM data master" "0,1" newline bitfld.long 0x0 30. "DM_PM_ALIST,Bypass SLC for the PB_ZLS data master" "0,1" newline bitfld.long 0x0 29. "DM_PB_TE,Bypass SLC for the PB_TE data master" "0,1" newline bitfld.long 0x0 28. "DM_PB_VCE,Bypass SLC for the PB_VCE data master" "0,1" newline bitfld.long 0x0 26.--27. "Reserved_26,Reserved_26" "0,1,2,3" newline bitfld.long 0x0 25. "REQ_IPF_CPF,Bypass SLC for IPF (CPF) requestor" "0,1" newline bitfld.long 0x0 24. "REQ_TPU,Bypass SLC for TPU requests coming from the MCU requestor" "0,1" newline bitfld.long 0x0 23. "REQ_FBDC,Bypass SLC for the FBDC requestor" "0,1" newline bitfld.long 0x0 22. "Reserved_22,Reserved_22" "0,1" newline bitfld.long 0x0 21. "BYP_CC_N,Bypass SLC when Cache Coherency bit is not set" "0,1" newline bitfld.long 0x0 20. "BYP_CC,Bypass SLC when Cache Coherency bit is set" "0,1" newline bitfld.long 0x0 19. "REQ_MCU,Bypass SLC for the MCU requestor" "0,1" newline bitfld.long 0x0 18. "REQ_PDS,Bypass SLC for the PDS requestor" "0,1" newline bitfld.long 0x0 17. "REQ_TPF,Bypass SLC for the TPF requestor" "0,1" newline bitfld.long 0x0 16. "REQ_TA_TPC,Bypass SLC for the TA (Tail Pointer Cache data) requestor" "0,1" newline bitfld.long 0x0 15. "Reserved_15,Reserved_15" "0,1" newline bitfld.long 0x0 14. "REQ_USC,Bypass SLC for the USC requestor" "0,1" newline bitfld.long 0x0 13. "REQ_META,Bypass SLC for the META requestor" "0,1" newline bitfld.long 0x0 12. "REQ_HOST,Bypass SLC for the Host requestor" "0,1" newline bitfld.long 0x0 11. "REQ_MMU_PT,Bypass SLC for the MMU requestor (Page Table data)" "0,1" newline bitfld.long 0x0 10. "REQ_MMU_PD,Bypass SLC for the MMU requestor (Page Directory data)" "0,1" newline bitfld.long 0x0 9. "REQ_MMU_PC,Bypass SLC for the MMU requestor (Page Catalogue data)" "0,1" newline bitfld.long 0x0 8. "DM_FRC,Bypass SLC for the FRC Video Core (Optional feature)" "0,1" newline bitfld.long 0x0 7. "DM_VXE,Bypass SLC for the VXE Video Core (Optional feature)" "0,1" newline bitfld.long 0x0 6. "DM_VXD,Bypass SLC for the VXD Video Core (Optional feature)" "0,1" newline bitfld.long 0x0 5. "DM_HOST_META,Bypass SLC the HOST/META data master" "0,1" newline bitfld.long 0x0 4. "DM_MMU,Bypass SLC the MMU data master" "0,1" newline bitfld.long 0x0 3. "DM_COMPUTE,Bypass SLC the COMPUTE data master" "0,1" newline bitfld.long 0x0 2. "DM_PIXEL,Bypass SLC for the PIXEL data master" "0,1" newline bitfld.long 0x0 1. "DM_TA,Bypass SLC for the TA group which includes VERTEX TESSELLATOR & STREAM_OUT data masters" "0,1" newline bitfld.long 0x0 0. "ALL,Bypass SLC for all requesters" "0,1" line.long 0x4 "RGX_CR_SLC_CTRL_BYPASS_1,SLC Bypass control" hexmask.long.word 0x4 22.--31. 1. "Reserved_54,Reserved_54" newline bitfld.long 0x4 21. "REQ_TCU_DM_COMPUTE,Bypass SLC when DM is COMPUTE for TCU requests" "0,1" newline bitfld.long 0x4 20. "Reserved_52,Reserved_52" "0,1" newline bitfld.long 0x4 19. "PBE_NOLINEFILL,PBE nolinefill set" "0,1" newline bitfld.long 0x4 18. "REQ_FBC,Bypass SLC for FBC requestor" "0,1" newline bitfld.long 0x4 17. "REQ_IPF_RREQ,Bypass SLC for IPF (RREQ) requestor" "0,1" newline bitfld.long 0x4 16. "REQ_IPF_CREQ,Bypass SLC for IPF (CREQ) requestor" "0,1" newline bitfld.long 0x4 15. "REQ_IPF_PREQ,Bypass SLC for IPF (PREQ) requestor" "0,1" newline bitfld.long 0x4 14. "REQ_IPF_DBSC,Bypass SLC for IPF (DBSC) requestor" "0,1" newline bitfld.long 0x4 13. "REQ_TCU,Bypass SLC for TCU requests" "0,1" newline bitfld.long 0x4 12. "REQ_PBE,Bypass SLC for PBE requestor" "0,1" newline bitfld.long 0x4 11. "REQ_ISP,Bypass SLC for the ISP requestor" "0,1" newline bitfld.long 0x4 10. "REQ_PM,Bypass SLC for the PM requestor" "0,1" newline bitfld.long 0x4 9. "REQ_TDM,Bypass SLC for the TDM requestor" "0,1" newline bitfld.long 0x4 8. "REQ_CDM,Bypass SLC for the CDM requestor" "0,1" newline bitfld.long 0x4 7. "REQ_TSPF_PDS_STATE,Bypass SLC for the TSPF PDS STATE requestor" "0,1" newline bitfld.long 0x4 6. "REQ_TSPF_DB,Bypass SLC for the TSPF DB requestor" "0,1" newline bitfld.long 0x4 5. "REQ_TSPF_VTX_VAR,Bypass SLC for the TSPF VTX VAR requestor" "0,1" newline bitfld.long 0x4 4. "REQ_VDM,Bypass SLC for VDM requestor" "0,1" newline bitfld.long 0x4 3. "REQ_TA_PSG_STREAM,Bypass SLC for the TA (PSG Stream) requestor" "0,1" newline bitfld.long 0x4 2. "REQ_TA_PSG_REGION,Bypass SLC for the TA (PSG Region) requestor" "0,1" newline bitfld.long 0x4 1. "REQ_TA_VCE,Bypass SLC for the TA (VCE) requestor" "0,1" newline bitfld.long 0x4 0. "REQ_TA_PPP,Bypass SLC for the TA (PPP) requestor" "0,1" repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) group.long ($2+0x3830)++0x3 line.long 0x0 "RGX_CR_SLC_LINE_USE_COUNT_LIMIT0_$1,Define the maximum number of cache lines allowed to be allocated to each requester within the SLC. Note that values are specified per bank as a multiple of 4 cache lines with values of 0x0 denoting no limit. Also note.." hexmask.long.byte 0x0 24.--31. 1. "TDM,Maximum number of cachelines allocated to the TDM requestor" newline hexmask.long.byte 0x0 16.--23. 1. "HOST,Maximum number of cachelines allocated to the HOST requestor" newline hexmask.long.byte 0x0 8.--15. 1. "TCU,Maximum number of cachelines allocated to the TCU requestor" newline hexmask.long.byte 0x0 0.--7. 1. "MMU,Maximum number of cachelines allocated to the MMU requestor" repeat.end group.long 0x3838++0x7 line.long 0x0 "RGX_CR_SLC_LINE_USE_COUNT_LIMIT1_0,Define the maximum number of cache lines allowed to be allocated to each requester within the SLC. Note that values are specified per bank as a multiple of 4 cache lines with values of 0x0 denoting no limit. Also note.." hexmask.long.byte 0x0 24.--31. 1. "VXD,Maximum number of cachelines allocated to the VXD requestor" newline hexmask.long.byte 0x0 16.--23. 1. "FBDC,Maximum number of cachelines allocated to the FBDC requestor" newline hexmask.long.byte 0x0 8.--15. 1. "MCU,Maximum number of cachelines allocated to the MCU requestor" newline hexmask.long.byte 0x0 0.--7. 1. "PDS,Maximum number of cachelines allocated to the PDS requestor" line.long 0x4 "RGX_CR_SLC_LINE_USE_COUNT_LIMIT1_1,Define the maximum number of cache lines allowed to be allocated to each requester within the SLC. Note that values are specified per bank as a multiple of 4 cache lines with values of 0x0 denoting no limit. Also note.." hexmask.long.word 0x4 16.--31. 1. "Reserved_48,Reserved_48" newline hexmask.long.byte 0x4 8.--15. 1. "FRC,Maximum number of cachelines allocated to the FRC requestor" newline hexmask.long.byte 0x4 0.--7. 1. "VXE,Maximum number of cachelines allocated to the VXE requestor" rgroup.long 0x3840++0x37 line.long 0x0 "RGX_CR_SLC_LINE_USE_COUNT_STATUS0_0,Number of cache lines currently allocated to each requester within the SLC. Values will constantly change when the core is active but will give a representative snapshot of cache usage." hexmask.long.byte 0x0 24.--31. 1. "BANK0_TDM,Number of cache lines in bank 0 currently allocated to the TDM" newline hexmask.long.word 0x0 12.--23. 1. "BANK1_MMU,Number of cache lines in bank 1 currently allocated to the MMU" newline hexmask.long.word 0x0 0.--11. 1. "BANK0_MMU,Number of cache lines in bank 0 currently allocated to the MMU" line.long 0x4 "RGX_CR_SLC_LINE_USE_COUNT_STATUS0_1,Number of cache lines currently allocated to each requester within the SLC. Values will constantly change when the core is active but will give a representative snapshot of cache usage." hexmask.long.byte 0x4 28.--31. 1. "Reserved_60,Reserved_60" newline hexmask.long.word 0x4 16.--27. 1. "BANK0_HOST,Number of cache lines in bank 0 currently allocated to the HOST" newline hexmask.long.word 0x4 4.--15. 1. "BANK1_TDM,Number of cache lines in bank 1 currently allocated to the TDM" newline hexmask.long.byte 0x4 0.--3. 1. "BANK0_TDM,Number of cache lines in bank 0 currently allocated to the TDM" line.long 0x8 "RGX_CR_SLC_LINE_USE_COUNT_STATUS1_0,Number of cache lines currently allocated to each requester within the SLC. Values will constantly change when the core is active but will give a representative snapshot of cache usage." hexmask.long.byte 0x8 24.--31. 1. "BANK1_TCU,Number of cache lines in bank 1 currently allocated to the TCU" newline hexmask.long.word 0x8 12.--23. 1. "BANK0_TCU,Number of cache lines in bank 0 currently allocated to the TCU" newline hexmask.long.word 0x8 0.--11. 1. "BANK1_HOST,Number of cache lines in bank 1 currently allocated to the HOST" line.long 0xC "RGX_CR_SLC_LINE_USE_COUNT_STATUS1_1,Number of cache lines currently allocated to each requester within the SLC. Values will constantly change when the core is active but will give a representative snapshot of cache usage." hexmask.long.byte 0xC 28.--31. 1. "Reserved_60,Reserved_60" newline hexmask.long.word 0xC 16.--27. 1. "BANK1_USC,Number of cache lines in bank 1 currently allocated to the USC" newline hexmask.long.word 0xC 4.--15. 1. "BANK0_USC,Number of cache lines in bank 0 currently allocated to the USC" newline hexmask.long.byte 0xC 0.--3. 1. "BANK1_TCU,Number of cache lines in bank 1 currently allocated to the TCU" line.long 0x10 "RGX_CR_SLC_LINE_USE_COUNT_STATUS2_0,Number of cache lines currently allocated to each requester within the SLC. Values will constantly change when the core is active but will give a representative snapshot of cache usage." hexmask.long.byte 0x10 24.--31. 1. "BANK0_TA_TPC,Number of cache lines in bank 0 currently allocated to the TA (Tail Pointer Cache data)" newline hexmask.long.word 0x10 12.--23. 1. "BANK1_IPF_OBJ,Number of cache lines in bank 1 currently allocated to the IPF (Object data)" newline hexmask.long.word 0x10 0.--11. 1. "BANK0_IPF_OBJ,Number of cache lines in bank 0 currently allocated to the IPF (Object data)" line.long 0x14 "RGX_CR_SLC_LINE_USE_COUNT_STATUS2_1,Number of cache lines currently allocated to each requester within the SLC. Values will constantly change when the core is active but will give a representative snapshot of cache usage." hexmask.long.byte 0x14 28.--31. 1. "Reserved_60,Reserved_60" newline hexmask.long.word 0x14 16.--27. 1. "BANK0_TPF,Number of cache lines in bank 0 currently allocated to the TPF" newline hexmask.long.word 0x14 4.--15. 1. "BANK1_TA_TPC,Number of cache lines in bank 1 currently allocated to the TA (Tail Pointer Cache data)" newline hexmask.long.byte 0x14 0.--3. 1. "BANK0_TA_TPC,Number of cache lines in bank 0 currently allocated to the TA (Tail Pointer Cache data)" line.long 0x18 "RGX_CR_SLC_LINE_USE_COUNT_STATUS3_0,Number of cache lines currently allocated to each requester within the SLC. Values will constantly change when the core is active but will give a representative snapshot of cache usage." hexmask.long.byte 0x18 24.--31. 1. "BANK1_PDS,Number of cache lines in bank 1 currently allocated to the PDS" newline hexmask.long.word 0x18 12.--23. 1. "BANK0_PDS,Number of cache lines in bank 0 currently allocated to the PDS" newline hexmask.long.word 0x18 0.--11. 1. "BANK1_TPF,Number of cache lines in bank 1 currently allocated to the TPF" line.long 0x1C "RGX_CR_SLC_LINE_USE_COUNT_STATUS3_1,Number of cache lines currently allocated to each requester within the SLC. Values will constantly change when the core is active but will give a representative snapshot of cache usage." hexmask.long.byte 0x1C 28.--31. 1. "Reserved_60,Reserved_60" newline hexmask.long.word 0x1C 16.--27. 1. "BANK1_MCU,Number of cache lines in bank 1 currently allocated to the MCU" newline hexmask.long.word 0x1C 4.--15. 1. "BANK0_MCU,Number of cache lines in bank 0 currently allocated to the MCU" newline hexmask.long.byte 0x1C 0.--3. 1. "BANK1_PDS,Number of cache lines in bank 1 currently allocated to the PDS" line.long 0x20 "RGX_CR_SLC_LINE_USE_COUNT_STATUS4_0,Number of cache lines currently allocated to each requester within the SLC. Values will constantly change when the core is active but will give a representative snapshot of cache usage." hexmask.long.byte 0x20 24.--31. 1. "BANK0_VXD,Number of cache lines in bank 0 currently allocated to the VXD core" newline hexmask.long.word 0x20 12.--23. 1. "BANK1_FBDC,Number of cache lines in bank 1 currently allocated to the FBDC" newline hexmask.long.word 0x20 0.--11. 1. "BANK0_FBDC,Number of cache lines in bank 0 currently allocated to the FBDC" line.long 0x24 "RGX_CR_SLC_LINE_USE_COUNT_STATUS4_1,Number of cache lines currently allocated to each requester within the SLC. Values will constantly change when the core is active but will give a representative snapshot of cache usage." hexmask.long.byte 0x24 28.--31. 1. "Reserved_60,Reserved_60" newline hexmask.long.word 0x24 16.--27. 1. "BANK0_VXE,Number of cache lines in bank 0 currently allocated to the VXE core" newline hexmask.long.word 0x24 4.--15. 1. "BANK1_VXD,Number of cache lines in bank 1 currently allocated to the VXD core" newline hexmask.long.byte 0x24 0.--3. 1. "BANK0_VXD,Number of cache lines in bank 0 currently allocated to the VXD core" line.long 0x28 "RGX_CR_SLC_LINE_USE_COUNT_STATUS5_0,Number of cache lines currently allocated to each requester within the SLC. Values will constantly change when the core is active but will give a representative snapshot of cache usage." hexmask.long.byte 0x28 24.--31. 1. "BANK1_FRC,Number of cache lines in bank 1 currently allocated to the FRC core" newline hexmask.long.word 0x28 12.--23. 1. "BANK0_FRC,Number of cache lines in bank 0 currently allocated to the FRC core" newline hexmask.long.word 0x28 0.--11. 1. "BANK1_VXE,Number of cache lines in bank 1 currently allocated to the VXE core" line.long 0x2C "RGX_CR_SLC_LINE_USE_COUNT_STATUS5_1,Number of cache lines currently allocated to each requester within the SLC. Values will constantly change when the core is active but will give a representative snapshot of cache usage." hexmask.long.byte 0x2C 28.--31. 1. "Reserved_60,Reserved_60" newline hexmask.long.word 0x2C 16.--27. 1. "BANK1_PM,Number of cache lines in bank 1 currently allocated to the PM core" newline hexmask.long.word 0x2C 4.--15. 1. "BANK0_PM,Number of cache lines in bank 0 currently allocated to the PM core" newline hexmask.long.byte 0x2C 0.--3. 1. "BANK1_FRC,Number of cache lines in bank 1 currently allocated to the FRC core" line.long 0x30 "RGX_CR_SLC_STATUS1_0,Current status of the SLC" hexmask.long.byte 0x30 26.--31. 1. "Reserved_26,Reserved_26" newline hexmask.long.word 0x30 16.--25. 1. "READS0,Number of items of read data SLC bank 0 has in internal pipeline FIFO's" newline hexmask.long.byte 0x30 8.--15. 1. "READS1_EXT,Number of items of read data SLC bank 1 has outstanding from external memory" newline hexmask.long.byte 0x30 0.--7. 1. "READS0_EXT,Number of items of read data SLC bank 0 has outstanding from external memory" line.long 0x34 "RGX_CR_SLC_STATUS1_1,Current status of the SLC" bitfld.long 0x34 31. "PAUSED,All cache banks are Paused" "0,1" newline hexmask.long.tbyte 0x34 10.--30. 1. "Reserved_42,Reserved_42" newline hexmask.long.word 0x34 0.--9. 1. "READS1,Number of items of read data SLC bank 1 has in internal pipeline FIFO's" group.long 0x3878++0x7 line.long 0x0 "RGX_CR_SLC_STATS0_CTRL_0,Configuration of the SLC Stats counters inside SLC bank 0. The type fields should be set to define the events that should be counted. then constraints should be added to specify particular requestors or types of request that.." hexmask.long.byte 0x0 28.--31. 1. "Reserved_28,Reserved_28" newline bitfld.long 0x0 27. "STOP,Pause counting whilst this bit is set" "0,1" newline bitfld.long 0x0 26. "RESET,Reset counter" "0,1" newline bitfld.long 0x0 25. "RNW,If constraint set 0x0 count only writes 0x1 count only reads" "0,1" newline bitfld.long 0x0 24. "BYPASS,If constraint set 0x0 count cached requests 0x1 count bypassed requests" "0,1" newline bitfld.long 0x0 21.--23. "DM,If constraint set count only requests for the specified Data Master" "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x0 16.--20. 1. "TAG_ID,If constraint set count only requests with the specified Tag ID" newline hexmask.long.byte 0x0 8.--15. 1. "TAG_SB,If constraint set count only requests with the specified sideband Tag" newline bitfld.long 0x0 7. "SELECT_TAG_SB,Include Tag sideband in constraints" "0,1" newline bitfld.long 0x0 6. "SELECT_TAG_ID,Include Tag ID in constraints" "0,1" newline bitfld.long 0x0 5. "SELECT_DM,Include Data Master in constraints" "0,1" newline bitfld.long 0x0 4. "SELECT_BYPASS,Include Bypass enable in constraints" "0,1" newline bitfld.long 0x0 3. "SELECT_RNW,Include Wead/Write select in constraints" "0,1" newline bitfld.long 0x0 2. "TYPE_FLUSH,Count number of cache lines flushed" "0,1" newline bitfld.long 0x0 1. "TYPE_MISS,Count number of misses" "0,1" newline bitfld.long 0x0 0. "TYPE_HIT,Count number of hits" "0,1" line.long 0x4 "RGX_CR_SLC_STATS0_CTRL_1,Configuration of the SLC Stats counters inside SLC bank 0. The type fields should be set to define the events that should be counted. then constraints should be added to specify particular requestors or types of request that.." hexmask.long 0x4 0.--31. 1. "Reserved_28,Reserved_28" repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) rgroup.long ($2+0x3880)++0x3 line.long 0x0 "RGX_CR_SLC_STATS0_OUTPUT_$1,Output of the SLC Stats counter inside SLC bank 0." hexmask.long 0x0 0.--31. 1. "VALUE,Value of counter 0" repeat.end group.long 0x3888++0x7 line.long 0x0 "RGX_CR_SLC_STATS1_CTRL_0,Configuration of the SLC Stats counters inside SLC bank 1. The type fields should be set to define the events that should be counted. then constraints should be added to specify particular requestors or types of request that.." hexmask.long.byte 0x0 28.--31. 1. "Reserved_28,Reserved_28" newline bitfld.long 0x0 27. "STOP,Pause counting whilst this bit is set" "0,1" newline bitfld.long 0x0 26. "RESET,Reset counter" "0,1" newline bitfld.long 0x0 25. "RNW,If constraint set 0x0 count only writes 0x1 count only reads" "0,1" newline bitfld.long 0x0 24. "BYPASS,If constraint set 0x0 count cached requests 0x1 count bypassed requests" "0,1" newline bitfld.long 0x0 21.--23. "DM,If constraint set count only requests for the specified Data Master" "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x0 16.--20. 1. "TAG_ID,If constraint set count only requests with the specified Tag ID" newline hexmask.long.byte 0x0 8.--15. 1. "TAG_SB,If constraint set count only requests with the specified sideband Tag" newline bitfld.long 0x0 7. "SELECT_TAG_SB,Include Tag sideband in constraints" "0,1" newline bitfld.long 0x0 6. "SELECT_TAG_ID,Include Tag ID in constraints" "0,1" newline bitfld.long 0x0 5. "SELECT_DM,Include Data Master in constraints" "0,1" newline bitfld.long 0x0 4. "SELECT_BYPASS,Include Bypass enable in constraints" "0,1" newline bitfld.long 0x0 3. "SELECT_RNW,Include Wead/Write select in constraints" "0,1" newline bitfld.long 0x0 2. "TYPE_FLUSH,Count number of cache lines flushed" "0,1" newline bitfld.long 0x0 1. "TYPE_MISS,Count number of misses" "0,1" newline bitfld.long 0x0 0. "TYPE_HIT,Count number of hits" "0,1" line.long 0x4 "RGX_CR_SLC_STATS1_CTRL_1,Configuration of the SLC Stats counters inside SLC bank 1. The type fields should be set to define the events that should be counted. then constraints should be added to specify particular requestors or types of request that.." hexmask.long 0x4 0.--31. 1. "Reserved_28,Reserved_28" repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) rgroup.long ($2+0x3890)++0x3 line.long 0x0 "RGX_CR_SLC_STATS1_OUTPUT_$1,Output of the SLC Stats counter inside SLC bank 1." hexmask.long 0x0 0.--31. 1. "VALUE,Value of counter 1" repeat.end rgroup.long 0x3898++0x7 line.long 0x0 "RGX_CR_SLC_IDLE_0,RGX_CR_SLC_IDLE_0" hexmask.long.tbyte 0x0 10.--31. 1. "Reserved_10,Reserved_10" newline bitfld.long 0x0 9. "MH_SYSARB1,SYSARB1 Module IDLE" "0,1" newline bitfld.long 0x0 8. "MH_SYSARB0,SYSARB0 Module IDLE" "0,1" newline bitfld.long 0x0 7. "IMGBV4,IMG Bus v4 Module IDLE" "0,1" newline bitfld.long 0x0 6. "CACHE_BANKS,Cache Bank IDLEs" "0,1" newline bitfld.long 0x0 5. "RBOFIFO,Read Burst Order FIFO Module IDLE" "0,1" newline bitfld.long 0x0 4. "FRC_CONV,FRC Module IDLE" "0,1" newline bitfld.long 0x0 3. "VXE_CONV,Video Encode Converter Module IDLE" "0,1" newline bitfld.long 0x0 2. "VXD_CONV,Video Decode Converter Module IDLE" "0,1" newline bitfld.long 0x0 1. "BIF1_CONV,BIF128->256 Converter Module IDLE" "0,1" newline bitfld.long 0x0 0. "CBAR,CrossBar Module IDLE" "0,1" line.long 0x4 "RGX_CR_SLC_IDLE_1,RGX_CR_SLC_IDLE_1" hexmask.long 0x4 0.--31. 1. "Reserved_10,Reserved_10" repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) rgroup.long ($2+0x38A0)++0x3 line.long 0x0 "RGX_CR_MCU_PWR_NUM_$1,Power Monitoring register" hexmask.long 0x0 0.--31. 1. "L0_TO_L1_ACCESS,Number of L0 to L1 accesses. Both L0s in a DUST added together" repeat.end group.long 0x38A8++0x7 line.long 0x0 "RGX_CR_SLC_LINE_USE_COUNT_LIMIT2_0,Define the maximum number of cache lines allowed to be allocated to each requester within the SLC. Note that values are specified per bank as a multiple of 4 cache lines with values of 0x0 denoting no limit. Also note.." hexmask.long.byte 0x0 24.--31. 1. "CDM,Maximum number of cachelines allocated to the CDM requestor" newline hexmask.long.byte 0x0 16.--23. 1. "VDM,Maximum number of cachelines allocated to the VDM requestor" newline hexmask.long.byte 0x0 8.--15. 1. "ISP,Maximum number of cachelines allocated to the ISP requestor" newline hexmask.long.byte 0x0 0.--7. 1. "PBE,Maximum number of cachelines allocated to the PBE requestor" line.long 0x4 "RGX_CR_SLC_LINE_USE_COUNT_LIMIT2_1,Define the maximum number of cache lines allowed to be allocated to each requester within the SLC. Note that values are specified per bank as a multiple of 4 cache lines with values of 0x0 denoting no limit. Also note.." hexmask.long.tbyte 0x4 8.--31. 1. "Reserved_40,Reserved_40" newline hexmask.long.byte 0x4 0.--7. 1. "PM,Maximum number of cachelines allocated to the PM requestor" rgroup.long 0x38B0++0xF line.long 0x0 "RGX_CR_SLC_LINE_USE_COUNT_STATUS6_0,Number of cache lines currently allocated to each requester within the SLC. Values will constantly change when the core is active but will give a representative snapshot of cache usage." hexmask.long.byte 0x0 24.--31. 1. "BANK0_ISP,Number of cache lines in bank 0 currently allocated to the ISP core" newline hexmask.long.word 0x0 12.--23. 1. "BANK1_PBE,Number of cache lines in bank 1 currently allocated to the PBE core" newline hexmask.long.word 0x0 0.--11. 1. "BANK0_PBE,Number of cache lines in bank 0 currently allocated to the PBE core" line.long 0x4 "RGX_CR_SLC_LINE_USE_COUNT_STATUS6_1,Number of cache lines currently allocated to each requester within the SLC. Values will constantly change when the core is active but will give a representative snapshot of cache usage." hexmask.long.byte 0x4 28.--31. 1. "Reserved_60,Reserved_60" newline hexmask.long.word 0x4 16.--27. 1. "BANK0_CDM,Number of cache lines in bank 1 currently allocated to the CDM core" newline hexmask.long.word 0x4 4.--15. 1. "BANK1_ISP,Number of cache lines in bank 1 currently allocated to the ISP core" newline hexmask.long.byte 0x4 0.--3. 1. "BANK0_ISP,Number of cache lines in bank 0 currently allocated to the ISP core" line.long 0x8 "RGX_CR_SLC_LINE_USE_COUNT_STATUS7_0,Number of cache lines currently allocated to each requester within the SLC. Values will constantly change when the core is active but will give a representative snapshot of cache usage." hexmask.long.byte 0x8 24.--31. 1. "BANK1_VDM,Number of cache lines in bank 1 currently allocated to the VDM core" newline hexmask.long.word 0x8 12.--23. 1. "BANK0_VDM,Number of cache lines in bank 0 currently allocated to the VDM core" newline hexmask.long.word 0x8 0.--11. 1. "BANK1_CDM,Number of cache lines in bank 1 currently allocated to the CDM core" line.long 0xC "RGX_CR_SLC_LINE_USE_COUNT_STATUS7_1,Number of cache lines currently allocated to each requester within the SLC. Values will constantly change when the core is active but will give a representative snapshot of cache usage." hexmask.long 0xC 4.--31. 1. "Reserved_36,Reserved_36" newline hexmask.long.byte 0xC 0.--3. 1. "BANK1_VDM,Number of cache lines in bank 1 currently allocated to the VDM core" group.long 0x38C0++0x17 line.long 0x0 "RGX_CR_AXI_ACE_LITE_CONFIGURATION_0,AXI ACE-LITE configuration registers" bitfld.long 0x0 30.--31. "ARCACHE_CACHE_MAINTENANCE,Read cache policy for cache maintenance transactions - bit[1] should be set to 1" "0,1,2,3" newline hexmask.long.byte 0x0 26.--29. 1. "ARCACHE_COHERENT,Read cache policy for coherent transactions - bit[1] should be set to 1" newline hexmask.long.byte 0x0 22.--25. 1. "AWCACHE_COHERENT,Write cache policy for coherent transactions - bit[1] should be set to 1" newline bitfld.long 0x0 20.--21. "ARDOMAIN_BARRIER,Read shareability domain for barrier transactions 00 = Non-Shareable 01 = Inner Shareable 10 = Outer Shareable 11 = System" "Non-Shareable,Inner Shareable,?,?" newline bitfld.long 0x0 18.--19. "AWDOMAIN_BARRIER,Write shareability domain for barrier transactions 00 = Non-Shareable 01 = Inner Shareable 10 = Outer Shareable 11 = System" "Non-Shareable,Inner Shareable,?,?" newline bitfld.long 0x0 16.--17. "ARDOMAIN_CACHE_MAINTENANCE,Read shareability domain for cache maintenance transactions 00 = Non-Shareable 01 = Inner Shareable 10 = Outer Shareable" "Non-Shareable,Inner Shareable,?,?" newline bitfld.long 0x0 14.--15. "AWDOMAIN_COHERENT,Write shareability domain for coherant transactions 01 = Inner Shareable 10 = Outer Shareable" "?,Inner Shareable,?,?" newline bitfld.long 0x0 12.--13. "ARDOMAIN_COHERENT,Read shareability domain for coherant transactions 01 = Inner Shareable 10 = Outer Shareable" "?,Inner Shareable,?,?" newline bitfld.long 0x0 10.--11. "ARDOMAIN_NON_SNOOPING,Read shareability domain for non-snooping transactions 00 = Non-Shareable 11 = System" "Non-Shareable,?,?,?" newline bitfld.long 0x0 8.--9. "AWDOMAIN_NON_SNOOPING,Write shareability domain for non-snooping transactions 00 = Non-Shareable 11 = System" "Non-Shareable,?,?,?" newline hexmask.long.byte 0x0 4.--7. 1. "ARCACHE_NON_SNOOPING,Read cache policy for non-snooping transactions" newline hexmask.long.byte 0x0 0.--3. 1. "AWCACHE_NON_SNOOPING,Write cache policy for non-snooping transactions" line.long 0x4 "RGX_CR_AXI_ACE_LITE_CONFIGURATION_1,AXI ACE-LITE configuration registers" hexmask.long.tbyte 0x4 13.--31. 1. "Reserved_45,Reserved_45" newline hexmask.long.byte 0x4 5.--12. 1. "OSID_SECURITY,SET to 1 to disable secure reads/writes for each OSID" newline bitfld.long 0x4 4. "DISABLE_COHERENT_WRITELINEUNIQUE,SET to 1 to disable coherent write line uniques" "0,1" newline bitfld.long 0x4 3. "DISABLE_COHERENT_WRITE,SET to 1 to disable coherent writes" "0,1" newline bitfld.long 0x4 2. "DISABLE_COHERENT_READ,SET to 1 to disable coherent reads" "0,1" newline bitfld.long 0x4 0.--1. "ARCACHE_CACHE_MAINTENANCE,Read cache policy for cache maintenance transactions - bit[1] should be set to 1" "0,1,2,3" line.long 0x8 "RGX_CR_AXI_ACE_LITE_CACHE_MAINTENANCE_CONFIGURATION_0,AXI ACE-LITE Cache Maintenance configuration registers" hexmask.long 0x8 4.--31. 1. "MAINTENANCE_ADDRESS,Address to perform cache maintenace address on" newline bitfld.long 0x8 3. "MAINTENANCE_MAKEINVALID,Writing a 1 issues a makeinvalid operation" "0,1" newline bitfld.long 0x8 2. "MAINTENANCE_CLEAN_INVALID,Writing a 1 issues a clean invalid operation" "0,1" newline bitfld.long 0x8 1. "MAINTENANCE_CLEANSHARED,Writing a 1 issues a clean shared operation" "0,1" newline bitfld.long 0x8 0. "ENABLE_MAINTENANCE,Writing a 1 enables cache maintenance operations" "0,1" line.long 0xC "RGX_CR_AXI_ACE_LITE_CACHE_MAINTENANCE_CONFIGURATION_1,AXI ACE-LITE Cache Maintenance configuration registers" hexmask.long.tbyte 0xC 12.--31. 1. "Reserved_44,Reserved_44" newline hexmask.long.word 0xC 0.--11. 1. "MAINTENANCE_ADDRESS,Address to perform cache maintenace address on" line.long 0x10 "RGX_CR_AXI_ACE_LITE_CACHE_MAINTENANCE_STATUS_0,The hardware will set this to 1 once the cache maintenance operation has completed. The firmware should poll this bit and set it to 0. once it has acknowledged it being set to 1." hexmask.long 0x10 1.--31. 1. "Reserved_1,Reserved_1" newline bitfld.long 0x10 0. "DONE,DONE" "0,1" line.long 0x14 "RGX_CR_AXI_ACE_LITE_CACHE_MAINTENANCE_STATUS_1,The hardware will set this to 1 once the cache maintenance operation has completed. The firmware should poll this bit and set it to 0. once it has acknowledged it being set to 1." hexmask.long 0x14 0.--31. 1. "Reserved_1,Reserved_1" repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) group.long ($2+0x3930)++0x3 line.long 0x0 "RGX_CR_SLC_CTRL_MISC2_$1,SLC control registers" hexmask.long 0x0 0.--31. 1. "SCRAMBLE_BITS,Pattern of bits used to determine the MSB of the Cache Bank in 4 Bank configurations in Address Decode mode 0x21. The actual Cache Bank to use is determined by indexing into the 32 Scramble Bits using the 5 LSB's of the Hash result and then.." repeat.end group.long 0x3938++0x7 line.long 0x0 "RGX_CR_SLC_CROSSBAR_LOAD_BALANCE_0,SLC control registers to bypass SLC crossbar load balancing" hexmask.long 0x0 1.--31. 1. "Reserved_1,Reserved_1" newline bitfld.long 0x0 0. "BYPASS,control register bit to bypass load balancing in SLC crossbar. In this case the requests from img-memif0 will go directly to ocp-memif0 and so on" "0,1" line.long 0x4 "RGX_CR_SLC_CROSSBAR_LOAD_BALANCE_1,SLC control registers to bypass SLC crossbar load balancing" hexmask.long 0x4 0.--31. 1. "Reserved_1,Reserved_1" rgroup.long 0x3960++0x7 line.long 0x0 "RGX_CR_SLC_STATUS3_0,Current status of the SLC" hexmask.long.byte 0x0 24.--31. 1. "WRITES1_TRANSACTIONS_EXT,Number of outsanding write burst transactions in SLC bank 1" newline hexmask.long.byte 0x0 16.--23. 1. "WRITES0_TRANSACTIONS_EXT,Number of outsanding write burst transactions in SLC bank 0" newline hexmask.long.byte 0x0 8.--15. 1. "READS1_TRANSACTIONS_EXT,Number of outsanding read burst transactions in SLC bank 1" newline hexmask.long.byte 0x0 0.--7. 1. "READS0_TRANSACTIONS_EXT,Number of outsanding read burst transactions in SLC bank 0" line.long 0x4 "RGX_CR_SLC_STATUS3_1,Current status of the SLC" hexmask.long 0x4 0.--31. 1. "Reserved_32,Reserved_32" wgroup.long 0x4000++0x7 line.long 0x0 "RGX_CR_USC_INST_CACHE_0,RGX_CR_USC_INST_CACHE_0" hexmask.long 0x0 1.--31. 1. "Reserved_1,Reserved_1" newline bitfld.long 0x0 0. "INVALIDATE,Any write to this location invalidates the L1 and L2 instruction caches automatically" "0,1" line.long 0x4 "RGX_CR_USC_INST_CACHE_1,RGX_CR_USC_INST_CACHE_1" hexmask.long 0x4 0.--31. 1. "Reserved_1,Reserved_1" group.long 0x4008++0xF line.long 0x0 "RGX_CR_USC_CODE_BASE_VERTEX_0,RGX_CR_USC_CODE_BASE_VERTEX_0" hexmask.long 0x0 6.--31. 1. "ADDR,Vertex Data Master Code Base Register bits" newline hexmask.long.byte 0x0 0.--5. 1. "Reserved_0,Reserved_0" line.long 0x4 "RGX_CR_USC_CODE_BASE_VERTEX_1,RGX_CR_USC_CODE_BASE_VERTEX_1" hexmask.long.tbyte 0x4 8.--31. 1. "Reserved_40,Reserved_40" newline hexmask.long.byte 0x4 0.--7. 1. "ADDR,Vertex Data Master Code Base Register bits" line.long 0x8 "RGX_CR_USC_CODE_BASE_PIXEL_0,RGX_CR_USC_CODE_BASE_PIXEL_0" hexmask.long 0x8 6.--31. 1. "ADDR,Pixel Data Master Code Base Register bits" newline hexmask.long.byte 0x8 0.--5. 1. "Reserved_0,Reserved_0" line.long 0xC "RGX_CR_USC_CODE_BASE_PIXEL_1,RGX_CR_USC_CODE_BASE_PIXEL_1" hexmask.long.tbyte 0xC 8.--31. 1. "Reserved_40,Reserved_40" newline hexmask.long.byte 0xC 0.--7. 1. "ADDR,Pixel Data Master Code Base Register bits" group.long 0x4028++0x4F line.long 0x0 "RGX_CR_USC_CODE_BASE_COMPUTE_0,RGX_CR_USC_CODE_BASE_COMPUTE_0" hexmask.long 0x0 6.--31. 1. "ADDR,Compute Data Master Code Base Register bits" newline hexmask.long.byte 0x0 0.--5. 1. "Reserved_0,Reserved_0" line.long 0x4 "RGX_CR_USC_CODE_BASE_COMPUTE_1,RGX_CR_USC_CODE_BASE_COMPUTE_1" hexmask.long.tbyte 0x4 8.--31. 1. "Reserved_40,Reserved_40" newline hexmask.long.byte 0x4 0.--7. 1. "ADDR,Compute Data Master Code Base Register bits" line.long 0x8 "RGX_CR_USC_BREAKPOINT_0,RGX_CR_USC_BREAKPOINT_0" hexmask.long 0x8 1.--31. 1. "ADDR,Breakpoint Address" newline bitfld.long 0x8 0. "Reserved_0,Reserved_0" "0,1" line.long 0xC "RGX_CR_USC_BREAKPOINT_1,RGX_CR_USC_BREAKPOINT_1" hexmask.long 0xC 0.--31. 1. "Reserved_32,Reserved_32" line.long 0x10 "RGX_CR_USC_BREAKPOINT_HANDLER_0,RGX_CR_USC_BREAKPOINT_HANDLER_0" hexmask.long 0x10 1.--31. 1. "ADDR,Breakpoint Handler Address" newline bitfld.long 0x10 0. "Reserved_0,Reserved_0" "0,1" line.long 0x14 "RGX_CR_USC_BREAKPOINT_HANDLER_1,RGX_CR_USC_BREAKPOINT_HANDLER_1" hexmask.long 0x14 0.--31. 1. "Reserved_32,Reserved_32" line.long 0x18 "RGX_CR_USC_BREAKPOINT_CTRL_0,RGX_CR_USC_BREAKPOINT_CTRL_0" hexmask.long 0x18 4.--31. 1. "Reserved_4,Reserved_4" newline bitfld.long 0x18 3. "ENABLE,0 = Breakpoint disabled 1 = Breakpoint enabled" "Breakpoint disabled,Breakpoint enabled" newline bitfld.long 0x18 0.--2. "DM,Data Master of Breakpoint" "0,1,2,3,4,5,6,7" line.long 0x1C "RGX_CR_USC_BREAKPOINT_CTRL_1,RGX_CR_USC_BREAKPOINT_CTRL_1" hexmask.long 0x1C 0.--31. 1. "Reserved_4,Reserved_4" line.long 0x20 "RGX_CR_USC_SMP_SWAP_0,RGX_CR_USC_SMP_SWAP_0" hexmask.long 0x20 1.--31. 1. "Reserved_1,Reserved_1" newline bitfld.long 0x20 0. "ENABLE,Deactivate after SMP instruction" "0,1" line.long 0x24 "RGX_CR_USC_SMP_SWAP_1,RGX_CR_USC_SMP_SWAP_1" hexmask.long 0x24 0.--31. 1. "Reserved_1,Reserved_1" line.long 0x28 "RGX_CR_USC_OVERRIDE_CTRL_0,RGX_CR_USC_OVERRIDE_CTRL_0" hexmask.long.word 0x28 22.--31. 1. "Reserved_22,Reserved_22" newline bitfld.long 0x28 21. "USCIS_LOCKING,0 = Default enable locking of USCIS when queue fills to maintain task ordering 1 = retry USCIS request" "Default,retry USCIS request" newline bitfld.long 0x28 20. "PHASE_BOTH,0 = Default no extra pass groups when single phase followed by multi-phase 1 = generate pass group whenever phases per task changes" "Default,generate pass group whenever phases per task.." newline bitfld.long 0x28 18.--19. "RESERVE_SLOTS,0 = Default allow all slots to be used for first phase tasks 1 = reserve 1 slot 2 = reserve 2 3 = reserve 4" "Default,reserve 1 slot,reserve 2,reserve 4" newline bitfld.long 0x28 17. "NO_RESERVE,0 = Default reserve slots for second phases 1 = Do not reserve slots for second phase tasks" "Default,Do not reserve slots for second phase tasks" newline bitfld.long 0x28 15.--16. "MAX_GROUP,0 = Default - 8 pass groups in flight 1 = 6 pass groups 2 = 4 pass groups 3 = 2 pass groups. To disable entirely see PDS" "Default,?,?,?" newline bitfld.long 0x28 14. "WAKE_UP,0 = Default normal wake up 1 = force task wake up" "Default,force task wake up" newline bitfld.long 0x28 13. "LATE_PARTN,0 = Default enable pixel data master tasks to start before a partition is allocated 1 = wait for partition" "Default,wait for partition" newline bitfld.long 0x28 12. "DMA_LOCKING,0 = Default enable locking of DMA when queue fills to maintain task ordering 1 = retry DMA request" "Default,retry DMA request" newline bitfld.long 0x28 11. "PRIORITY,0 = Default enable state loading and end of tile tasks to run with higher priority 1 = all tasks low priority" "Default,all tasks low priority" newline bitfld.long 0x28 10. "PHASE_PASSES,0 = Default enable inferred pass groups when multiple phase tasks are encountered 1 = disable hard SDs must be used" "Default,disable" newline bitfld.long 0x28 9. "OUTPUT_WRITES,0 = Default enable tracking of output buffer write completion for on-edge buffer validlity 1 = tracking invalid" "Default,tracking invalid" newline bitfld.long 0x28 8. "SELECTIVE_RATE,0 = Default (core specific enable selective rate mode if functional) 1 = disable" "Default,disable" newline bitfld.long 0x28 6.--7. "Reserved_6,Reserved_6" "0,1,2,3" newline hexmask.long.byte 0x28 0.--5. 1. "DEBUG_TEMPS,Number of temps to add to PDS allocation size for debugging. Units of 8" line.long 0x2C "RGX_CR_USC_OVERRIDE_CTRL_1,RGX_CR_USC_OVERRIDE_CTRL_1" hexmask.long 0x2C 0.--31. 1. "Reserved_22,Reserved_22" line.long 0x30 "RGX_CR_USC_DC_CACHE_CTRL_0,RGX_CR_USC_DC_CACHE_CTRL_0" hexmask.long 0x30 1.--31. 1. "Reserved_1,Reserved_1" newline bitfld.long 0x30 0. "LINES,Number of lines in Dynamic Constant Cache - 0=64 1=128" "0,1" line.long 0x34 "RGX_CR_USC_DC_CACHE_CTRL_1,RGX_CR_USC_DC_CACHE_CTRL_1" hexmask.long 0x34 0.--31. 1. "Reserved_1,Reserved_1" line.long 0x38 "RGX_CR_USC_DC_CACHE_INVALIDATE_0,RGX_CR_USC_DC_CACHE_INVALIDATE_0" hexmask.long 0x38 1.--31. 1. "Reserved_1,Reserved_1" newline bitfld.long 0x38 0. "PENDING,A write of 1 to this location will cause an invalidation of the Dynamic Constant Cache. If DMKILL bit is not set then all entries are invalidated. If DMKILL bit is set then only a data master killing invalidation is performed. The invalidation.." "0,1" line.long 0x3C "RGX_CR_USC_DC_CACHE_INVALIDATE_1,RGX_CR_USC_DC_CACHE_INVALIDATE_1" hexmask.long 0x3C 0.--31. 1. "Reserved_1,Reserved_1" line.long 0x40 "RGX_CR_USC_SHARED_GROUP_CLEAR_0,RGX_CR_USC_SHARED_GROUP_CLEAR_0" hexmask.long 0x40 1.--31. 1. "Reserved_1,Reserved_1" newline bitfld.long 0x40 0. "PENDING,Any write to this location requests the USC Shared Group register file to be cleared" "0,1" line.long 0x44 "RGX_CR_USC_SHARED_GROUP_CLEAR_1,RGX_CR_USC_SHARED_GROUP_CLEAR_1" hexmask.long 0x44 0.--31. 1. "Reserved_1,Reserved_1" line.long 0x48 "RGX_CR_USC_PIXEL_OUTPUT_CTRL_0,RGX_CR_USC_PIXEL_OUTPUT_CTRL_0" hexmask.long.word 0x48 17.--31. 1. "Reserved_17,Reserved_17" newline hexmask.long.word 0x48 3.--16. 1. "PARTITION_MASK,Partition Enable Mask for USC. Defines which partitions are for use by the USC to prevent SPM Deadlock" newline bitfld.long 0x48 2. "ENABLE_4TH_PARTITION,Enables 4th Partition" "0,1" newline bitfld.long 0x48 0.--1. "WIDTH,WIDTH" "0,1,2,3" line.long 0x4C "RGX_CR_USC_PIXEL_OUTPUT_CTRL_1,RGX_CR_USC_PIXEL_OUTPUT_CTRL_1" hexmask.long 0x4C 0.--31. 1. "Reserved_17,Reserved_17" repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) group.long ($2+0x4078)++0x3 line.long 0x0 "RGX_CR_USC_CLEAR_REGISTER0_$1,RGX_CR_USC_CLEAR_REGISTER0_0" hexmask.long 0x0 0.--31. 1. "VAL,Clear Colour register 0" repeat.end repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) group.long ($2+0x4080)++0x3 line.long 0x0 "RGX_CR_USC_CLEAR_REGISTER1_$1,RGX_CR_USC_CLEAR_REGISTER1_0" hexmask.long 0x0 0.--31. 1. "VAL,Clear Colour register 1" repeat.end repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) group.long ($2+0x4088)++0x3 line.long 0x0 "RGX_CR_USC_CLEAR_REGISTER2_$1,RGX_CR_USC_CLEAR_REGISTER2_0" hexmask.long 0x0 0.--31. 1. "VAL,Clear Colour register 2" repeat.end repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) group.long ($2+0x4090)++0x3 line.long 0x0 "RGX_CR_USC_CLEAR_REGISTER3_$1,RGX_CR_USC_CLEAR_REGISTER3_0" hexmask.long 0x0 0.--31. 1. "VAL,Clear Colour register 3" repeat.end group.long 0x4098++0x3F line.long 0x0 "RGX_CR_USC_G0_0,RGX_CR_USC_G0_0" hexmask.long.tbyte 0x0 8.--31. 1. "Reserved_8,Reserved_8" newline hexmask.long.byte 0x0 0.--7. 1. "P,Global cross-thread-accessible read/write register for USC programs via the 'special' bank type" line.long 0x4 "RGX_CR_USC_G0_1,RGX_CR_USC_G0_1" hexmask.long 0x4 0.--31. 1. "Reserved_8,Reserved_8" line.long 0x8 "RGX_CR_USC_G1_0,RGX_CR_USC_G1_0" hexmask.long.tbyte 0x8 8.--31. 1. "Reserved_8,Reserved_8" newline hexmask.long.byte 0x8 0.--7. 1. "P,Global cross-thread-accessible read/write register for USC programs via the 'special' bank type" line.long 0xC "RGX_CR_USC_G1_1,RGX_CR_USC_G1_1" hexmask.long 0xC 0.--31. 1. "Reserved_8,Reserved_8" line.long 0x10 "RGX_CR_USC_G2_0,RGX_CR_USC_G2_0" hexmask.long.tbyte 0x10 8.--31. 1. "Reserved_8,Reserved_8" newline hexmask.long.byte 0x10 0.--7. 1. "P,Global cross-thread-accessible read/write register for USC programs via the 'special' bank type" line.long 0x14 "RGX_CR_USC_G2_1,RGX_CR_USC_G2_1" hexmask.long 0x14 0.--31. 1. "Reserved_8,Reserved_8" line.long 0x18 "RGX_CR_USC_G3_0,RGX_CR_USC_G3_0" hexmask.long.tbyte 0x18 8.--31. 1. "Reserved_8,Reserved_8" newline hexmask.long.byte 0x18 0.--7. 1. "P,Global cross-thread-accessible read/write register for USC programs via the 'special' bank type" line.long 0x1C "RGX_CR_USC_G3_1,RGX_CR_USC_G3_1" hexmask.long 0x1C 0.--31. 1. "Reserved_8,Reserved_8" line.long 0x20 "RGX_CR_USC_G4_0,RGX_CR_USC_G4_0" hexmask.long.tbyte 0x20 8.--31. 1. "Reserved_8,Reserved_8" newline hexmask.long.byte 0x20 0.--7. 1. "P,Global cross-thread-accessible read/write register for USC programs via the 'special' bank type" line.long 0x24 "RGX_CR_USC_G4_1,RGX_CR_USC_G4_1" hexmask.long 0x24 0.--31. 1. "Reserved_8,Reserved_8" line.long 0x28 "RGX_CR_USC_G5_0,RGX_CR_USC_G5_0" hexmask.long.tbyte 0x28 8.--31. 1. "Reserved_8,Reserved_8" newline hexmask.long.byte 0x28 0.--7. 1. "P,Global cross-thread-accessible read/write register for USC programs via the 'special' bank type" line.long 0x2C "RGX_CR_USC_G5_1,RGX_CR_USC_G5_1" hexmask.long 0x2C 0.--31. 1. "Reserved_8,Reserved_8" line.long 0x30 "RGX_CR_USC_G6_0,RGX_CR_USC_G6_0" hexmask.long.tbyte 0x30 8.--31. 1. "Reserved_8,Reserved_8" newline hexmask.long.byte 0x30 0.--7. 1. "P,Global cross-thread-accessible read/write register for USC programs via the 'special' bank type" line.long 0x34 "RGX_CR_USC_G6_1,RGX_CR_USC_G6_1" hexmask.long 0x34 0.--31. 1. "Reserved_8,Reserved_8" line.long 0x38 "RGX_CR_USC_G7_0,RGX_CR_USC_G7_0" hexmask.long.tbyte 0x38 8.--31. 1. "Reserved_8,Reserved_8" newline hexmask.long.byte 0x38 0.--7. 1. "P,Global cross-thread-accessible read/write register for USC programs via the 'special' bank type" line.long 0x3C "RGX_CR_USC_G7_1,RGX_CR_USC_G7_1" hexmask.long 0x3C 0.--31. 1. "Reserved_8,Reserved_8" rgroup.long 0x40D8++0x27 line.long 0x0 "RGX_CR_USC_SERV_PIXEL_0,RGX_CR_USC_SERV_PIXEL_0" hexmask.long.word 0x0 17.--31. 1. "Reserved_17,Reserved_17" newline bitfld.long 0x0 16. "EMPTY,No Pixel Data Master tasks in USC0 queue" "0,1" newline hexmask.long.word 0x0 0.--15. 1. "COUNT,Number of Pixel Data Master tasks serviced by USC0" line.long 0x4 "RGX_CR_USC_SERV_PIXEL_1,RGX_CR_USC_SERV_PIXEL_1" hexmask.long 0x4 0.--31. 1. "Reserved_17,Reserved_17" line.long 0x8 "RGX_CR_USC_SERV_VERTEX_0,RGX_CR_USC_SERV_VERTEX_0" hexmask.long.word 0x8 17.--31. 1. "Reserved_17,Reserved_17" newline bitfld.long 0x8 16. "EMPTY,No Vertex Data Master tasks in USC0 queue" "0,1" newline hexmask.long.word 0x8 0.--15. 1. "COUNT,Number of Vertex Data Master tasks serviced by USC0" line.long 0xC "RGX_CR_USC_SERV_VERTEX_1,RGX_CR_USC_SERV_VERTEX_1" hexmask.long 0xC 0.--31. 1. "Reserved_17,Reserved_17" line.long 0x10 "RGX_CR_USC_SERV_TESS_PIXEL_0,RGX_CR_USC_SERV_TESS_PIXEL_0" hexmask.long.word 0x10 17.--31. 1. "Reserved_17,Reserved_17" newline bitfld.long 0x10 16. "EMPTY,No Tessellator Pixel Data Master tasks in USC0 queue" "0,1" newline hexmask.long.word 0x10 0.--15. 1. "COUNT,Number of Tessellator Pixel Data Master tasks serviced by USC0" line.long 0x14 "RGX_CR_USC_SERV_TESS_PIXEL_1,RGX_CR_USC_SERV_TESS_PIXEL_1" hexmask.long 0x14 0.--31. 1. "Reserved_17,Reserved_17" line.long 0x18 "RGX_CR_USC_SERV_TESS_VERTEX_0,RGX_CR_USC_SERV_TESS_VERTEX_0" hexmask.long.word 0x18 17.--31. 1. "Reserved_17,Reserved_17" newline bitfld.long 0x18 16. "EMPTY,No Tessellator Vertex Data Master tasks in USC0 queue" "0,1" newline hexmask.long.word 0x18 0.--15. 1. "COUNT,Number of Tessellator Vertex Data Master tasks serviced by USC0" line.long 0x1C "RGX_CR_USC_SERV_TESS_VERTEX_1,RGX_CR_USC_SERV_TESS_VERTEX_1" hexmask.long 0x1C 0.--31. 1. "Reserved_17,Reserved_17" line.long 0x20 "RGX_CR_USC_SERV_COMPUTE_0,RGX_CR_USC_SERV_COMPUTE_0" hexmask.long.word 0x20 17.--31. 1. "Reserved_17,Reserved_17" newline bitfld.long 0x20 16. "EMPTY,No Compute Data Master tasks in USC0 queue" "0,1" newline hexmask.long.word 0x20 0.--15. 1. "COUNT,Number of Compute Data Master tasks serviced by USC0" line.long 0x24 "RGX_CR_USC_SERV_COMPUTE_1,RGX_CR_USC_SERV_COMPUTE_1" hexmask.long 0x24 0.--31. 1. "Reserved_17,Reserved_17" repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) rgroup.long ($2+0x4100)++0x3 line.long 0x0 "RGX_CR_USC_PARTITION_STATUS_$1,RGX_CR_USC_PARTITION_STATUS_0" hexmask.long.word 0x0 16.--31. 1. "CLOSED,Partition closed - end of tile task started" newline hexmask.long.word 0x0 0.--15. 1. "IN_USE,Partition in use" repeat.end rgroup.long 0x4108++0x17 line.long 0x0 "RGX_CR_USC_OLDEST_TASK_STATUS_0,RGX_CR_USC_OLDEST_TASK_STATUS_0" hexmask.long.word 0x0 20.--31. 1. "Reserved_20,Reserved_20" newline hexmask.long.byte 0x0 16.--19. 1. "PASS_NUM,The present pass group" newline bitfld.long 0x0 13.--15. "DM,The task Data Master" "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x0 9.--12. 1. "TILEQUAD,The stream of the task depends on Data Master Vertex: Indicates the patch of the task Pixel >= 4 cluster: The tile ID of the task Pixel 2 cluster: The tile ID and patch concatenated Compute: 0" newline bitfld.long 0x0 7.--8. "STATE,Queue state for entry" "0,1,2,3" newline bitfld.long 0x0 6. "NEW_SD,This task is at the start of a new SD group bit is cleared when the task is first run" "0,1" newline bitfld.long 0x0 5. "TFPU_CS_ED,This task is waiting for a TFPU strobe which has not been satisfied" "0,1" newline bitfld.long 0x0 4. "MCU_CS_ED,This task is waiting for an MCU CS strobe which has not been satisfied" "0,1" newline bitfld.long 0x0 3. "MCU_US_ED,This task is waiting for an MCU US strobe which has not been satisfied" "0,1" newline bitfld.long 0x0 2. "FRAG_TYPE,Is this task a work or state loading type. '1' indicates a Vertex/Fragment/Work type '0' indicates a Shared/ Coefficient/ Control type" "0,1" newline bitfld.long 0x0 1. "PHAS_ISSUE,This task must issue a PHAS instruction which has not yet been seen" "0,1" newline bitfld.long 0x0 0. "PASS_GROUP,Is the task the start of a new pass group" "0,1" line.long 0x4 "RGX_CR_USC_OLDEST_TASK_STATUS_1,RGX_CR_USC_OLDEST_TASK_STATUS_1" hexmask.long 0x4 0.--31. 1. "Reserved_20,Reserved_20" line.long 0x8 "RGX_CR_USC_PARTITION_TILE_STATUS0_0,RGX_CR_USC_PARTITION_TILE_STATUS0_0" bitfld.long 0x8 30.--31. "TILE_ID5,Tile ID for partition 5" "0,1,2,3" newline hexmask.long.byte 0x8 24.--29. 1. "TILE_ID4,Tile ID for partition 4" newline hexmask.long.byte 0x8 18.--23. 1. "TILE_ID3,Tile ID for partition 3" newline hexmask.long.byte 0x8 12.--17. 1. "TILE_ID2,Tile ID for partition 2" newline hexmask.long.byte 0x8 6.--11. 1. "TILE_ID1,Tile ID for partition 1" newline hexmask.long.byte 0x8 0.--5. 1. "TILE_ID0,Tile ID for partition 0" line.long 0xC "RGX_CR_USC_PARTITION_TILE_STATUS0_1,RGX_CR_USC_PARTITION_TILE_STATUS0_1" hexmask.long.word 0xC 16.--31. 1. "Reserved_48,Reserved_48" newline hexmask.long.byte 0xC 10.--15. 1. "TILE_ID7,Tile ID for partition 7" newline hexmask.long.byte 0xC 4.--9. 1. "TILE_ID6,Tile ID for partition 6" newline hexmask.long.byte 0xC 0.--3. 1. "TILE_ID5,Tile ID for partition 5" line.long 0x10 "RGX_CR_USC_PARTITION_TILE_STATUS1_0,RGX_CR_USC_PARTITION_TILE_STATUS1_0" bitfld.long 0x10 30.--31. "TILE_ID13,Tile ID for partition 13" "0,1,2,3" newline hexmask.long.byte 0x10 24.--29. 1. "TILE_ID12,Tile ID for partition 12" newline hexmask.long.byte 0x10 18.--23. 1. "TILE_ID11,Tile ID for partition 11" newline hexmask.long.byte 0x10 12.--17. 1. "TILE_ID10,Tile ID for partition 10" newline hexmask.long.byte 0x10 6.--11. 1. "TILE_ID9,Tile ID for partition 9" newline hexmask.long.byte 0x10 0.--5. 1. "TILE_ID8,Tile ID for partition 8" line.long 0x14 "RGX_CR_USC_PARTITION_TILE_STATUS1_1,RGX_CR_USC_PARTITION_TILE_STATUS1_1" hexmask.long.byte 0x14 28.--31. 1. "Reserved_60,Reserved_60" newline hexmask.long.byte 0x14 22.--27. 1. "TILE_ID17,Tile ID for partition 17" newline hexmask.long.byte 0x14 16.--21. 1. "TILE_ID16,Tile ID for partition 16" newline hexmask.long.byte 0x14 10.--15. 1. "TILE_ID15,Tile ID for partition 15" newline hexmask.long.byte 0x14 4.--9. 1. "TILE_ID14,Tile ID for partition 14" newline hexmask.long.byte 0x14 0.--3. 1. "TILE_ID13,Tile ID for partition 13" repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) rgroup.long ($2+0x4178)++0x3 line.long 0x0 "RGX_CR_USC_DM_SLOT0_$1,Cluster Data Master in Slots" hexmask.long.byte 0x0 28.--31. 1. "SLOT_7,SLOT_7" newline hexmask.long.byte 0x0 24.--27. 1. "SLOT_6,SLOT_6" newline hexmask.long.byte 0x0 20.--23. 1. "SLOT_5,SLOT_5" newline hexmask.long.byte 0x0 16.--19. 1. "SLOT_4,SLOT_4" newline hexmask.long.byte 0x0 12.--15. 1. "SLOT_3,SLOT_3" newline hexmask.long.byte 0x0 8.--11. 1. "SLOT_2,SLOT_2" newline hexmask.long.byte 0x0 4.--7. 1. "SLOT_1,SLOT_1" newline hexmask.long.byte 0x0 0.--3. 1. "SLOT_0,SLOT_0" repeat.end repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) rgroup.long ($2+0x4180)++0x3 line.long 0x0 "RGX_CR_USC_DM_SLOT1_$1,Cluster Data Master in Slots" hexmask.long.byte 0x0 28.--31. 1. "SLOT_7,SLOT_7" newline hexmask.long.byte 0x0 24.--27. 1. "SLOT_6,SLOT_6" newline hexmask.long.byte 0x0 20.--23. 1. "SLOT_5,SLOT_5" newline hexmask.long.byte 0x0 16.--19. 1. "SLOT_4,SLOT_4" newline hexmask.long.byte 0x0 12.--15. 1. "SLOT_3,SLOT_3" newline hexmask.long.byte 0x0 8.--11. 1. "SLOT_2,SLOT_2" newline hexmask.long.byte 0x0 4.--7. 1. "SLOT_1,SLOT_1" newline hexmask.long.byte 0x0 0.--3. 1. "SLOT_0,SLOT_0" repeat.end repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) rgroup.long ($2+0x4188)++0x3 line.long 0x0 "RGX_CR_USC_DM_SLOT2_$1,Cluster Data Master in Slots" hexmask.long.byte 0x0 28.--31. 1. "SLOT_7,SLOT_7" newline hexmask.long.byte 0x0 24.--27. 1. "SLOT_6,SLOT_6" newline hexmask.long.byte 0x0 20.--23. 1. "SLOT_5,SLOT_5" newline hexmask.long.byte 0x0 16.--19. 1. "SLOT_4,SLOT_4" newline hexmask.long.byte 0x0 12.--15. 1. "SLOT_3,SLOT_3" newline hexmask.long.byte 0x0 8.--11. 1. "SLOT_2,SLOT_2" newline hexmask.long.byte 0x0 4.--7. 1. "SLOT_1,SLOT_1" newline hexmask.long.byte 0x0 0.--3. 1. "SLOT_0,SLOT_0" repeat.end repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) rgroup.long ($2+0x4190)++0x3 line.long 0x0 "RGX_CR_USC_DM_SLOT3_$1,Cluster Data Master in Slots" hexmask.long.byte 0x0 28.--31. 1. "SLOT_7,SLOT_7" newline hexmask.long.byte 0x0 24.--27. 1. "SLOT_6,SLOT_6" newline hexmask.long.byte 0x0 20.--23. 1. "SLOT_5,SLOT_5" newline hexmask.long.byte 0x0 16.--19. 1. "SLOT_4,SLOT_4" newline hexmask.long.byte 0x0 12.--15. 1. "SLOT_3,SLOT_3" newline hexmask.long.byte 0x0 8.--11. 1. "SLOT_2,SLOT_2" newline hexmask.long.byte 0x0 4.--7. 1. "SLOT_1,SLOT_1" newline hexmask.long.byte 0x0 0.--3. 1. "SLOT_0,SLOT_0" repeat.end rgroup.long 0x41B8++0x7 line.long 0x0 "RGX_CR_USC_EXCEPTION_0,RGX_CR_USC_EXCEPTION_0" hexmask.long.word 0x0 16.--31. 1. "CODE,Cluster exception code" newline hexmask.long.word 0x0 1.--15. 1. "Reserved_1,Reserved_1" newline bitfld.long 0x0 0. "STATUS,1=Cluster has raised an exception" "?,Cluster has raised an exception" line.long 0x4 "RGX_CR_USC_EXCEPTION_1,RGX_CR_USC_EXCEPTION_1" hexmask.long 0x4 0.--31. 1. "Reserved_32,Reserved_32" rgroup.long 0x41D8++0xFF line.long 0x0 "RGX_CR_USC_SLOT0_0,RGX_CR_USC_SLOT0_0" hexmask.long 0x0 1.--31. 1. "PC,PC" newline bitfld.long 0x0 0. "Reserved_0,Reserved_0" "0,1" line.long 0x4 "RGX_CR_USC_SLOT0_1,RGX_CR_USC_SLOT0_1" hexmask.long 0x4 4.--31. 1. "Reserved_36,Reserved_36" newline hexmask.long.byte 0x4 0.--3. 1. "STATUS,STATUS" line.long 0x8 "RGX_CR_USC_SLOT1_0,RGX_CR_USC_SLOT1_0" hexmask.long 0x8 1.--31. 1. "PC,PC" newline bitfld.long 0x8 0. "Reserved_0,Reserved_0" "0,1" line.long 0xC "RGX_CR_USC_SLOT1_1,RGX_CR_USC_SLOT1_1" hexmask.long 0xC 4.--31. 1. "Reserved_36,Reserved_36" newline hexmask.long.byte 0xC 0.--3. 1. "STATUS,STATUS" line.long 0x10 "RGX_CR_USC_SLOT2_0,RGX_CR_USC_SLOT2_0" hexmask.long 0x10 1.--31. 1. "PC,PC" newline bitfld.long 0x10 0. "Reserved_0,Reserved_0" "0,1" line.long 0x14 "RGX_CR_USC_SLOT2_1,RGX_CR_USC_SLOT2_1" hexmask.long 0x14 4.--31. 1. "Reserved_36,Reserved_36" newline hexmask.long.byte 0x14 0.--3. 1. "STATUS,STATUS" line.long 0x18 "RGX_CR_USC_SLOT3_0,RGX_CR_USC_SLOT3_0" hexmask.long 0x18 1.--31. 1. "PC,PC" newline bitfld.long 0x18 0. "Reserved_0,Reserved_0" "0,1" line.long 0x1C "RGX_CR_USC_SLOT3_1,RGX_CR_USC_SLOT3_1" hexmask.long 0x1C 4.--31. 1. "Reserved_36,Reserved_36" newline hexmask.long.byte 0x1C 0.--3. 1. "STATUS,STATUS" line.long 0x20 "RGX_CR_USC_SLOT4_0,RGX_CR_USC_SLOT4_0" hexmask.long 0x20 1.--31. 1. "PC,PC" newline bitfld.long 0x20 0. "Reserved_0,Reserved_0" "0,1" line.long 0x24 "RGX_CR_USC_SLOT4_1,RGX_CR_USC_SLOT4_1" hexmask.long 0x24 4.--31. 1. "Reserved_36,Reserved_36" newline hexmask.long.byte 0x24 0.--3. 1. "STATUS,STATUS" line.long 0x28 "RGX_CR_USC_SLOT5_0,RGX_CR_USC_SLOT5_0" hexmask.long 0x28 1.--31. 1. "PC,PC" newline bitfld.long 0x28 0. "Reserved_0,Reserved_0" "0,1" line.long 0x2C "RGX_CR_USC_SLOT5_1,RGX_CR_USC_SLOT5_1" hexmask.long 0x2C 4.--31. 1. "Reserved_36,Reserved_36" newline hexmask.long.byte 0x2C 0.--3. 1. "STATUS,STATUS" line.long 0x30 "RGX_CR_USC_SLOT6_0,RGX_CR_USC_SLOT6_0" hexmask.long 0x30 1.--31. 1. "PC,PC" newline bitfld.long 0x30 0. "Reserved_0,Reserved_0" "0,1" line.long 0x34 "RGX_CR_USC_SLOT6_1,RGX_CR_USC_SLOT6_1" hexmask.long 0x34 4.--31. 1. "Reserved_36,Reserved_36" newline hexmask.long.byte 0x34 0.--3. 1. "STATUS,STATUS" line.long 0x38 "RGX_CR_USC_SLOT7_0,RGX_CR_USC_SLOT7_0" hexmask.long 0x38 1.--31. 1. "PC,PC" newline bitfld.long 0x38 0. "Reserved_0,Reserved_0" "0,1" line.long 0x3C "RGX_CR_USC_SLOT7_1,RGX_CR_USC_SLOT7_1" hexmask.long 0x3C 4.--31. 1. "Reserved_36,Reserved_36" newline hexmask.long.byte 0x3C 0.--3. 1. "STATUS,STATUS" line.long 0x40 "RGX_CR_USC_SLOT8_0,RGX_CR_USC_SLOT8_0" hexmask.long 0x40 1.--31. 1. "PC,PC" newline bitfld.long 0x40 0. "Reserved_0,Reserved_0" "0,1" line.long 0x44 "RGX_CR_USC_SLOT8_1,RGX_CR_USC_SLOT8_1" hexmask.long 0x44 4.--31. 1. "Reserved_36,Reserved_36" newline hexmask.long.byte 0x44 0.--3. 1. "STATUS,STATUS" line.long 0x48 "RGX_CR_USC_SLOT9_0,RGX_CR_USC_SLOT9_0" hexmask.long 0x48 1.--31. 1. "PC,PC" newline bitfld.long 0x48 0. "Reserved_0,Reserved_0" "0,1" line.long 0x4C "RGX_CR_USC_SLOT9_1,RGX_CR_USC_SLOT9_1" hexmask.long 0x4C 4.--31. 1. "Reserved_36,Reserved_36" newline hexmask.long.byte 0x4C 0.--3. 1. "STATUS,STATUS" line.long 0x50 "RGX_CR_USC_SLOT10_0,RGX_CR_USC_SLOT10_0" hexmask.long 0x50 1.--31. 1. "PC,PC" newline bitfld.long 0x50 0. "Reserved_0,Reserved_0" "0,1" line.long 0x54 "RGX_CR_USC_SLOT10_1,RGX_CR_USC_SLOT10_1" hexmask.long 0x54 4.--31. 1. "Reserved_36,Reserved_36" newline hexmask.long.byte 0x54 0.--3. 1. "STATUS,STATUS" line.long 0x58 "RGX_CR_USC_SLOT11_0,RGX_CR_USC_SLOT11_0" hexmask.long 0x58 1.--31. 1. "PC,PC" newline bitfld.long 0x58 0. "Reserved_0,Reserved_0" "0,1" line.long 0x5C "RGX_CR_USC_SLOT11_1,RGX_CR_USC_SLOT11_1" hexmask.long 0x5C 4.--31. 1. "Reserved_36,Reserved_36" newline hexmask.long.byte 0x5C 0.--3. 1. "STATUS,STATUS" line.long 0x60 "RGX_CR_USC_SLOT12_0,RGX_CR_USC_SLOT12_0" hexmask.long 0x60 1.--31. 1. "PC,PC" newline bitfld.long 0x60 0. "Reserved_0,Reserved_0" "0,1" line.long 0x64 "RGX_CR_USC_SLOT12_1,RGX_CR_USC_SLOT12_1" hexmask.long 0x64 4.--31. 1. "Reserved_36,Reserved_36" newline hexmask.long.byte 0x64 0.--3. 1. "STATUS,STATUS" line.long 0x68 "RGX_CR_USC_SLOT13_0,RGX_CR_USC_SLOT13_0" hexmask.long 0x68 1.--31. 1. "PC,PC" newline bitfld.long 0x68 0. "Reserved_0,Reserved_0" "0,1" line.long 0x6C "RGX_CR_USC_SLOT13_1,RGX_CR_USC_SLOT13_1" hexmask.long 0x6C 4.--31. 1. "Reserved_36,Reserved_36" newline hexmask.long.byte 0x6C 0.--3. 1. "STATUS,STATUS" line.long 0x70 "RGX_CR_USC_SLOT14_0,RGX_CR_USC_SLOT14_0" hexmask.long 0x70 1.--31. 1. "PC,PC" newline bitfld.long 0x70 0. "Reserved_0,Reserved_0" "0,1" line.long 0x74 "RGX_CR_USC_SLOT14_1,RGX_CR_USC_SLOT14_1" hexmask.long 0x74 4.--31. 1. "Reserved_36,Reserved_36" newline hexmask.long.byte 0x74 0.--3. 1. "STATUS,STATUS" line.long 0x78 "RGX_CR_USC_SLOT15_0,RGX_CR_USC_SLOT15_0" hexmask.long 0x78 1.--31. 1. "PC,PC" newline bitfld.long 0x78 0. "Reserved_0,Reserved_0" "0,1" line.long 0x7C "RGX_CR_USC_SLOT15_1,RGX_CR_USC_SLOT15_1" hexmask.long 0x7C 4.--31. 1. "Reserved_36,Reserved_36" newline hexmask.long.byte 0x7C 0.--3. 1. "STATUS,STATUS" line.long 0x80 "RGX_CR_USC_SLOT16_0,RGX_CR_USC_SLOT16_0" hexmask.long 0x80 1.--31. 1. "PC,PC" newline bitfld.long 0x80 0. "Reserved_0,Reserved_0" "0,1" line.long 0x84 "RGX_CR_USC_SLOT16_1,RGX_CR_USC_SLOT16_1" hexmask.long 0x84 4.--31. 1. "Reserved_36,Reserved_36" newline hexmask.long.byte 0x84 0.--3. 1. "STATUS,STATUS" line.long 0x88 "RGX_CR_USC_SLOT17_0,RGX_CR_USC_SLOT17_0" hexmask.long 0x88 1.--31. 1. "PC,PC" newline bitfld.long 0x88 0. "Reserved_0,Reserved_0" "0,1" line.long 0x8C "RGX_CR_USC_SLOT17_1,RGX_CR_USC_SLOT17_1" hexmask.long 0x8C 4.--31. 1. "Reserved_36,Reserved_36" newline hexmask.long.byte 0x8C 0.--3. 1. "STATUS,STATUS" line.long 0x90 "RGX_CR_USC_SLOT18_0,RGX_CR_USC_SLOT18_0" hexmask.long 0x90 1.--31. 1. "PC,PC" newline bitfld.long 0x90 0. "Reserved_0,Reserved_0" "0,1" line.long 0x94 "RGX_CR_USC_SLOT18_1,RGX_CR_USC_SLOT18_1" hexmask.long 0x94 4.--31. 1. "Reserved_36,Reserved_36" newline hexmask.long.byte 0x94 0.--3. 1. "STATUS,STATUS" line.long 0x98 "RGX_CR_USC_SLOT19_0,RGX_CR_USC_SLOT19_0" hexmask.long 0x98 1.--31. 1. "PC,PC" newline bitfld.long 0x98 0. "Reserved_0,Reserved_0" "0,1" line.long 0x9C "RGX_CR_USC_SLOT19_1,RGX_CR_USC_SLOT19_1" hexmask.long 0x9C 4.--31. 1. "Reserved_36,Reserved_36" newline hexmask.long.byte 0x9C 0.--3. 1. "STATUS,STATUS" line.long 0xA0 "RGX_CR_USC_SLOT20_0,RGX_CR_USC_SLOT20_0" hexmask.long 0xA0 1.--31. 1. "PC,PC" newline bitfld.long 0xA0 0. "Reserved_0,Reserved_0" "0,1" line.long 0xA4 "RGX_CR_USC_SLOT20_1,RGX_CR_USC_SLOT20_1" hexmask.long 0xA4 4.--31. 1. "Reserved_36,Reserved_36" newline hexmask.long.byte 0xA4 0.--3. 1. "STATUS,STATUS" line.long 0xA8 "RGX_CR_USC_SLOT21_0,RGX_CR_USC_SLOT21_0" hexmask.long 0xA8 1.--31. 1. "PC,PC" newline bitfld.long 0xA8 0. "Reserved_0,Reserved_0" "0,1" line.long 0xAC "RGX_CR_USC_SLOT21_1,RGX_CR_USC_SLOT21_1" hexmask.long 0xAC 4.--31. 1. "Reserved_36,Reserved_36" newline hexmask.long.byte 0xAC 0.--3. 1. "STATUS,STATUS" line.long 0xB0 "RGX_CR_USC_SLOT22_0,RGX_CR_USC_SLOT22_0" hexmask.long 0xB0 1.--31. 1. "PC,PC" newline bitfld.long 0xB0 0. "Reserved_0,Reserved_0" "0,1" line.long 0xB4 "RGX_CR_USC_SLOT22_1,RGX_CR_USC_SLOT22_1" hexmask.long 0xB4 4.--31. 1. "Reserved_36,Reserved_36" newline hexmask.long.byte 0xB4 0.--3. 1. "STATUS,STATUS" line.long 0xB8 "RGX_CR_USC_SLOT23_0,RGX_CR_USC_SLOT23_0" hexmask.long 0xB8 1.--31. 1. "PC,PC" newline bitfld.long 0xB8 0. "Reserved_0,Reserved_0" "0,1" line.long 0xBC "RGX_CR_USC_SLOT23_1,RGX_CR_USC_SLOT23_1" hexmask.long 0xBC 4.--31. 1. "Reserved_36,Reserved_36" newline hexmask.long.byte 0xBC 0.--3. 1. "STATUS,STATUS" line.long 0xC0 "RGX_CR_USC_SLOT24_0,RGX_CR_USC_SLOT24_0" hexmask.long 0xC0 1.--31. 1. "PC,PC" newline bitfld.long 0xC0 0. "Reserved_0,Reserved_0" "0,1" line.long 0xC4 "RGX_CR_USC_SLOT24_1,RGX_CR_USC_SLOT24_1" hexmask.long 0xC4 4.--31. 1. "Reserved_36,Reserved_36" newline hexmask.long.byte 0xC4 0.--3. 1. "STATUS,STATUS" line.long 0xC8 "RGX_CR_USC_SLOT25_0,RGX_CR_USC_SLOT25_0" hexmask.long 0xC8 1.--31. 1. "PC,PC" newline bitfld.long 0xC8 0. "Reserved_0,Reserved_0" "0,1" line.long 0xCC "RGX_CR_USC_SLOT25_1,RGX_CR_USC_SLOT25_1" hexmask.long 0xCC 4.--31. 1. "Reserved_36,Reserved_36" newline hexmask.long.byte 0xCC 0.--3. 1. "STATUS,STATUS" line.long 0xD0 "RGX_CR_USC_SLOT26_0,RGX_CR_USC_SLOT26_0" hexmask.long 0xD0 1.--31. 1. "PC,PC" newline bitfld.long 0xD0 0. "Reserved_0,Reserved_0" "0,1" line.long 0xD4 "RGX_CR_USC_SLOT26_1,RGX_CR_USC_SLOT26_1" hexmask.long 0xD4 4.--31. 1. "Reserved_36,Reserved_36" newline hexmask.long.byte 0xD4 0.--3. 1. "STATUS,STATUS" line.long 0xD8 "RGX_CR_USC_SLOT27_0,RGX_CR_USC_SLOT27_0" hexmask.long 0xD8 1.--31. 1. "PC,PC" newline bitfld.long 0xD8 0. "Reserved_0,Reserved_0" "0,1" line.long 0xDC "RGX_CR_USC_SLOT27_1,RGX_CR_USC_SLOT27_1" hexmask.long 0xDC 4.--31. 1. "Reserved_36,Reserved_36" newline hexmask.long.byte 0xDC 0.--3. 1. "STATUS,STATUS" line.long 0xE0 "RGX_CR_USC_SLOT28_0,RGX_CR_USC_SLOT28_0" hexmask.long 0xE0 1.--31. 1. "PC,PC" newline bitfld.long 0xE0 0. "Reserved_0,Reserved_0" "0,1" line.long 0xE4 "RGX_CR_USC_SLOT28_1,RGX_CR_USC_SLOT28_1" hexmask.long 0xE4 4.--31. 1. "Reserved_36,Reserved_36" newline hexmask.long.byte 0xE4 0.--3. 1. "STATUS,STATUS" line.long 0xE8 "RGX_CR_USC_SLOT29_0,RGX_CR_USC_SLOT29_0" hexmask.long 0xE8 1.--31. 1. "PC,PC" newline bitfld.long 0xE8 0. "Reserved_0,Reserved_0" "0,1" line.long 0xEC "RGX_CR_USC_SLOT29_1,RGX_CR_USC_SLOT29_1" hexmask.long 0xEC 4.--31. 1. "Reserved_36,Reserved_36" newline hexmask.long.byte 0xEC 0.--3. 1. "STATUS,STATUS" line.long 0xF0 "RGX_CR_USC_SLOT30_0,RGX_CR_USC_SLOT30_0" hexmask.long 0xF0 1.--31. 1. "PC,PC" newline bitfld.long 0xF0 0. "Reserved_0,Reserved_0" "0,1" line.long 0xF4 "RGX_CR_USC_SLOT30_1,RGX_CR_USC_SLOT30_1" hexmask.long 0xF4 4.--31. 1. "Reserved_36,Reserved_36" newline hexmask.long.byte 0xF4 0.--3. 1. "STATUS,STATUS" line.long 0xF8 "RGX_CR_USC_SLOT31_0,RGX_CR_USC_SLOT31_0" hexmask.long 0xF8 1.--31. 1. "PC,PC" newline bitfld.long 0xF8 0. "Reserved_0,Reserved_0" "0,1" line.long 0xFC "RGX_CR_USC_SLOT31_1,RGX_CR_USC_SLOT31_1" hexmask.long 0xFC 4.--31. 1. "Reserved_36,Reserved_36" newline hexmask.long.byte 0xFC 0.--3. 1. "STATUS,STATUS" repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) group.long ($2+0x42E0)++0x3 line.long 0x0 "RGX_CR_USC_CLEAR_REGISTER4_$1,RGX_CR_USC_CLEAR_REGISTER4_0" hexmask.long 0x0 0.--31. 1. "VAL,Clear Colour register 4" repeat.end repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) group.long ($2+0x42E8)++0x3 line.long 0x0 "RGX_CR_USC_CLEAR_REGISTER5_$1,RGX_CR_USC_CLEAR_REGISTER5_0" hexmask.long 0x0 0.--31. 1. "VAL,Clear Colour register 5" repeat.end repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) group.long ($2+0x42F0)++0x3 line.long 0x0 "RGX_CR_USC_CLEAR_REGISTER6_$1,RGX_CR_USC_CLEAR_REGISTER6_0" hexmask.long 0x0 0.--31. 1. "VAL,Clear Colour register 6" repeat.end repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) group.long ($2+0x42F8)++0x3 line.long 0x0 "RGX_CR_USC_CLEAR_REGISTER7_$1,RGX_CR_USC_CLEAR_REGISTER7_0" hexmask.long 0x0 0.--31. 1. "VAL,Clear Colour register 7" repeat.end rgroup.long 0x4300++0xFF line.long 0x0 "RGX_CR_USC_SLOT32_0,RGX_CR_USC_SLOT32_0" hexmask.long 0x0 1.--31. 1. "PC,PC" newline bitfld.long 0x0 0. "Reserved_0,Reserved_0" "0,1" line.long 0x4 "RGX_CR_USC_SLOT32_1,RGX_CR_USC_SLOT32_1" hexmask.long 0x4 4.--31. 1. "Reserved_36,Reserved_36" newline hexmask.long.byte 0x4 0.--3. 1. "STATUS,STATUS" line.long 0x8 "RGX_CR_USC_SLOT33_0,RGX_CR_USC_SLOT33_0" hexmask.long 0x8 1.--31. 1. "PC,PC" newline bitfld.long 0x8 0. "Reserved_0,Reserved_0" "0,1" line.long 0xC "RGX_CR_USC_SLOT33_1,RGX_CR_USC_SLOT33_1" hexmask.long 0xC 4.--31. 1. "Reserved_36,Reserved_36" newline hexmask.long.byte 0xC 0.--3. 1. "STATUS,STATUS" line.long 0x10 "RGX_CR_USC_SLOT34_0,RGX_CR_USC_SLOT34_0" hexmask.long 0x10 1.--31. 1. "PC,PC" newline bitfld.long 0x10 0. "Reserved_0,Reserved_0" "0,1" line.long 0x14 "RGX_CR_USC_SLOT34_1,RGX_CR_USC_SLOT34_1" hexmask.long 0x14 4.--31. 1. "Reserved_36,Reserved_36" newline hexmask.long.byte 0x14 0.--3. 1. "STATUS,STATUS" line.long 0x18 "RGX_CR_USC_SLOT35_0,RGX_CR_USC_SLOT35_0" hexmask.long 0x18 1.--31. 1. "PC,PC" newline bitfld.long 0x18 0. "Reserved_0,Reserved_0" "0,1" line.long 0x1C "RGX_CR_USC_SLOT35_1,RGX_CR_USC_SLOT35_1" hexmask.long 0x1C 4.--31. 1. "Reserved_36,Reserved_36" newline hexmask.long.byte 0x1C 0.--3. 1. "STATUS,STATUS" line.long 0x20 "RGX_CR_USC_SLOT36_0,RGX_CR_USC_SLOT36_0" hexmask.long 0x20 1.--31. 1. "PC,PC" newline bitfld.long 0x20 0. "Reserved_0,Reserved_0" "0,1" line.long 0x24 "RGX_CR_USC_SLOT36_1,RGX_CR_USC_SLOT36_1" hexmask.long 0x24 4.--31. 1. "Reserved_36,Reserved_36" newline hexmask.long.byte 0x24 0.--3. 1. "STATUS,STATUS" line.long 0x28 "RGX_CR_USC_SLOT37_0,RGX_CR_USC_SLOT37_0" hexmask.long 0x28 1.--31. 1. "PC,PC" newline bitfld.long 0x28 0. "Reserved_0,Reserved_0" "0,1" line.long 0x2C "RGX_CR_USC_SLOT37_1,RGX_CR_USC_SLOT37_1" hexmask.long 0x2C 4.--31. 1. "Reserved_36,Reserved_36" newline hexmask.long.byte 0x2C 0.--3. 1. "STATUS,STATUS" line.long 0x30 "RGX_CR_USC_SLOT38_0,RGX_CR_USC_SLOT38_0" hexmask.long 0x30 1.--31. 1. "PC,PC" newline bitfld.long 0x30 0. "Reserved_0,Reserved_0" "0,1" line.long 0x34 "RGX_CR_USC_SLOT38_1,RGX_CR_USC_SLOT38_1" hexmask.long 0x34 4.--31. 1. "Reserved_36,Reserved_36" newline hexmask.long.byte 0x34 0.--3. 1. "STATUS,STATUS" line.long 0x38 "RGX_CR_USC_SLOT39_0,RGX_CR_USC_SLOT39_0" hexmask.long 0x38 1.--31. 1. "PC,PC" newline bitfld.long 0x38 0. "Reserved_0,Reserved_0" "0,1" line.long 0x3C "RGX_CR_USC_SLOT39_1,RGX_CR_USC_SLOT39_1" hexmask.long 0x3C 4.--31. 1. "Reserved_36,Reserved_36" newline hexmask.long.byte 0x3C 0.--3. 1. "STATUS,STATUS" line.long 0x40 "RGX_CR_USC_SLOT40_0,RGX_CR_USC_SLOT40_0" hexmask.long 0x40 1.--31. 1. "PC,PC" newline bitfld.long 0x40 0. "Reserved_0,Reserved_0" "0,1" line.long 0x44 "RGX_CR_USC_SLOT40_1,RGX_CR_USC_SLOT40_1" hexmask.long 0x44 4.--31. 1. "Reserved_36,Reserved_36" newline hexmask.long.byte 0x44 0.--3. 1. "STATUS,STATUS" line.long 0x48 "RGX_CR_USC_SLOT41_0,RGX_CR_USC_SLOT41_0" hexmask.long 0x48 1.--31. 1. "PC,PC" newline bitfld.long 0x48 0. "Reserved_0,Reserved_0" "0,1" line.long 0x4C "RGX_CR_USC_SLOT41_1,RGX_CR_USC_SLOT41_1" hexmask.long 0x4C 4.--31. 1. "Reserved_36,Reserved_36" newline hexmask.long.byte 0x4C 0.--3. 1. "STATUS,STATUS" line.long 0x50 "RGX_CR_USC_SLOT42_0,RGX_CR_USC_SLOT42_0" hexmask.long 0x50 1.--31. 1. "PC,PC" newline bitfld.long 0x50 0. "Reserved_0,Reserved_0" "0,1" line.long 0x54 "RGX_CR_USC_SLOT42_1,RGX_CR_USC_SLOT42_1" hexmask.long 0x54 4.--31. 1. "Reserved_36,Reserved_36" newline hexmask.long.byte 0x54 0.--3. 1. "STATUS,STATUS" line.long 0x58 "RGX_CR_USC_SLOT43_0,RGX_CR_USC_SLOT43_0" hexmask.long 0x58 1.--31. 1. "PC,PC" newline bitfld.long 0x58 0. "Reserved_0,Reserved_0" "0,1" line.long 0x5C "RGX_CR_USC_SLOT43_1,RGX_CR_USC_SLOT43_1" hexmask.long 0x5C 4.--31. 1. "Reserved_36,Reserved_36" newline hexmask.long.byte 0x5C 0.--3. 1. "STATUS,STATUS" line.long 0x60 "RGX_CR_USC_SLOT44_0,RGX_CR_USC_SLOT44_0" hexmask.long 0x60 1.--31. 1. "PC,PC" newline bitfld.long 0x60 0. "Reserved_0,Reserved_0" "0,1" line.long 0x64 "RGX_CR_USC_SLOT44_1,RGX_CR_USC_SLOT44_1" hexmask.long 0x64 4.--31. 1. "Reserved_36,Reserved_36" newline hexmask.long.byte 0x64 0.--3. 1. "STATUS,STATUS" line.long 0x68 "RGX_CR_USC_SLOT45_0,RGX_CR_USC_SLOT45_0" hexmask.long 0x68 1.--31. 1. "PC,PC" newline bitfld.long 0x68 0. "Reserved_0,Reserved_0" "0,1" line.long 0x6C "RGX_CR_USC_SLOT45_1,RGX_CR_USC_SLOT45_1" hexmask.long 0x6C 4.--31. 1. "Reserved_36,Reserved_36" newline hexmask.long.byte 0x6C 0.--3. 1. "STATUS,STATUS" line.long 0x70 "RGX_CR_USC_SLOT46_0,RGX_CR_USC_SLOT46_0" hexmask.long 0x70 1.--31. 1. "PC,PC" newline bitfld.long 0x70 0. "Reserved_0,Reserved_0" "0,1" line.long 0x74 "RGX_CR_USC_SLOT46_1,RGX_CR_USC_SLOT46_1" hexmask.long 0x74 4.--31. 1. "Reserved_36,Reserved_36" newline hexmask.long.byte 0x74 0.--3. 1. "STATUS,STATUS" line.long 0x78 "RGX_CR_USC_SLOT47_0,RGX_CR_USC_SLOT47_0" hexmask.long 0x78 1.--31. 1. "PC,PC" newline bitfld.long 0x78 0. "Reserved_0,Reserved_0" "0,1" line.long 0x7C "RGX_CR_USC_SLOT47_1,RGX_CR_USC_SLOT47_1" hexmask.long 0x7C 4.--31. 1. "Reserved_36,Reserved_36" newline hexmask.long.byte 0x7C 0.--3. 1. "STATUS,STATUS" line.long 0x80 "RGX_CR_USC_SLOT48_0,RGX_CR_USC_SLOT48_0" hexmask.long 0x80 1.--31. 1. "PC,PC" newline bitfld.long 0x80 0. "Reserved_0,Reserved_0" "0,1" line.long 0x84 "RGX_CR_USC_SLOT48_1,RGX_CR_USC_SLOT48_1" hexmask.long 0x84 4.--31. 1. "Reserved_36,Reserved_36" newline hexmask.long.byte 0x84 0.--3. 1. "STATUS,STATUS" line.long 0x88 "RGX_CR_USC_SLOT49_0,RGX_CR_USC_SLOT49_0" hexmask.long 0x88 1.--31. 1. "PC,PC" newline bitfld.long 0x88 0. "Reserved_0,Reserved_0" "0,1" line.long 0x8C "RGX_CR_USC_SLOT49_1,RGX_CR_USC_SLOT49_1" hexmask.long 0x8C 4.--31. 1. "Reserved_36,Reserved_36" newline hexmask.long.byte 0x8C 0.--3. 1. "STATUS,STATUS" line.long 0x90 "RGX_CR_USC_SLOT50_0,RGX_CR_USC_SLOT50_0" hexmask.long 0x90 1.--31. 1. "PC,PC" newline bitfld.long 0x90 0. "Reserved_0,Reserved_0" "0,1" line.long 0x94 "RGX_CR_USC_SLOT50_1,RGX_CR_USC_SLOT50_1" hexmask.long 0x94 4.--31. 1. "Reserved_36,Reserved_36" newline hexmask.long.byte 0x94 0.--3. 1. "STATUS,STATUS" line.long 0x98 "RGX_CR_USC_SLOT51_0,RGX_CR_USC_SLOT51_0" hexmask.long 0x98 1.--31. 1. "PC,PC" newline bitfld.long 0x98 0. "Reserved_0,Reserved_0" "0,1" line.long 0x9C "RGX_CR_USC_SLOT51_1,RGX_CR_USC_SLOT51_1" hexmask.long 0x9C 4.--31. 1. "Reserved_36,Reserved_36" newline hexmask.long.byte 0x9C 0.--3. 1. "STATUS,STATUS" line.long 0xA0 "RGX_CR_USC_SLOT52_0,RGX_CR_USC_SLOT52_0" hexmask.long 0xA0 1.--31. 1. "PC,PC" newline bitfld.long 0xA0 0. "Reserved_0,Reserved_0" "0,1" line.long 0xA4 "RGX_CR_USC_SLOT52_1,RGX_CR_USC_SLOT52_1" hexmask.long 0xA4 4.--31. 1. "Reserved_36,Reserved_36" newline hexmask.long.byte 0xA4 0.--3. 1. "STATUS,STATUS" line.long 0xA8 "RGX_CR_USC_SLOT53_0,RGX_CR_USC_SLOT53_0" hexmask.long 0xA8 1.--31. 1. "PC,PC" newline bitfld.long 0xA8 0. "Reserved_0,Reserved_0" "0,1" line.long 0xAC "RGX_CR_USC_SLOT53_1,RGX_CR_USC_SLOT53_1" hexmask.long 0xAC 4.--31. 1. "Reserved_36,Reserved_36" newline hexmask.long.byte 0xAC 0.--3. 1. "STATUS,STATUS" line.long 0xB0 "RGX_CR_USC_SLOT54_0,RGX_CR_USC_SLOT54_0" hexmask.long 0xB0 1.--31. 1. "PC,PC" newline bitfld.long 0xB0 0. "Reserved_0,Reserved_0" "0,1" line.long 0xB4 "RGX_CR_USC_SLOT54_1,RGX_CR_USC_SLOT54_1" hexmask.long 0xB4 4.--31. 1. "Reserved_36,Reserved_36" newline hexmask.long.byte 0xB4 0.--3. 1. "STATUS,STATUS" line.long 0xB8 "RGX_CR_USC_SLOT55_0,RGX_CR_USC_SLOT55_0" hexmask.long 0xB8 1.--31. 1. "PC,PC" newline bitfld.long 0xB8 0. "Reserved_0,Reserved_0" "0,1" line.long 0xBC "RGX_CR_USC_SLOT55_1,RGX_CR_USC_SLOT55_1" hexmask.long 0xBC 4.--31. 1. "Reserved_36,Reserved_36" newline hexmask.long.byte 0xBC 0.--3. 1. "STATUS,STATUS" line.long 0xC0 "RGX_CR_USC_SLOT56_0,RGX_CR_USC_SLOT56_0" hexmask.long 0xC0 1.--31. 1. "PC,PC" newline bitfld.long 0xC0 0. "Reserved_0,Reserved_0" "0,1" line.long 0xC4 "RGX_CR_USC_SLOT56_1,RGX_CR_USC_SLOT56_1" hexmask.long 0xC4 4.--31. 1. "Reserved_36,Reserved_36" newline hexmask.long.byte 0xC4 0.--3. 1. "STATUS,STATUS" line.long 0xC8 "RGX_CR_USC_SLOT57_0,RGX_CR_USC_SLOT57_0" hexmask.long 0xC8 1.--31. 1. "PC,PC" newline bitfld.long 0xC8 0. "Reserved_0,Reserved_0" "0,1" line.long 0xCC "RGX_CR_USC_SLOT57_1,RGX_CR_USC_SLOT57_1" hexmask.long 0xCC 4.--31. 1. "Reserved_36,Reserved_36" newline hexmask.long.byte 0xCC 0.--3. 1. "STATUS,STATUS" line.long 0xD0 "RGX_CR_USC_SLOT58_0,RGX_CR_USC_SLOT58_0" hexmask.long 0xD0 1.--31. 1. "PC,PC" newline bitfld.long 0xD0 0. "Reserved_0,Reserved_0" "0,1" line.long 0xD4 "RGX_CR_USC_SLOT58_1,RGX_CR_USC_SLOT58_1" hexmask.long 0xD4 4.--31. 1. "Reserved_36,Reserved_36" newline hexmask.long.byte 0xD4 0.--3. 1. "STATUS,STATUS" line.long 0xD8 "RGX_CR_USC_SLOT59_0,RGX_CR_USC_SLOT59_0" hexmask.long 0xD8 1.--31. 1. "PC,PC" newline bitfld.long 0xD8 0. "Reserved_0,Reserved_0" "0,1" line.long 0xDC "RGX_CR_USC_SLOT59_1,RGX_CR_USC_SLOT59_1" hexmask.long 0xDC 4.--31. 1. "Reserved_36,Reserved_36" newline hexmask.long.byte 0xDC 0.--3. 1. "STATUS,STATUS" line.long 0xE0 "RGX_CR_USC_SLOT60_0,RGX_CR_USC_SLOT60_0" hexmask.long 0xE0 1.--31. 1. "PC,PC" newline bitfld.long 0xE0 0. "Reserved_0,Reserved_0" "0,1" line.long 0xE4 "RGX_CR_USC_SLOT60_1,RGX_CR_USC_SLOT60_1" hexmask.long 0xE4 4.--31. 1. "Reserved_36,Reserved_36" newline hexmask.long.byte 0xE4 0.--3. 1. "STATUS,STATUS" line.long 0xE8 "RGX_CR_USC_SLOT61_0,RGX_CR_USC_SLOT61_0" hexmask.long 0xE8 1.--31. 1. "PC,PC" newline bitfld.long 0xE8 0. "Reserved_0,Reserved_0" "0,1" line.long 0xEC "RGX_CR_USC_SLOT61_1,RGX_CR_USC_SLOT61_1" hexmask.long 0xEC 4.--31. 1. "Reserved_36,Reserved_36" newline hexmask.long.byte 0xEC 0.--3. 1. "STATUS,STATUS" line.long 0xF0 "RGX_CR_USC_SLOT62_0,RGX_CR_USC_SLOT62_0" hexmask.long 0xF0 1.--31. 1. "PC,PC" newline bitfld.long 0xF0 0. "Reserved_0,Reserved_0" "0,1" line.long 0xF4 "RGX_CR_USC_SLOT62_1,RGX_CR_USC_SLOT62_1" hexmask.long 0xF4 4.--31. 1. "Reserved_36,Reserved_36" newline hexmask.long.byte 0xF4 0.--3. 1. "STATUS,STATUS" line.long 0xF8 "RGX_CR_USC_SLOT63_0,RGX_CR_USC_SLOT63_0" hexmask.long 0xF8 1.--31. 1. "PC,PC" newline bitfld.long 0xF8 0. "Reserved_0,Reserved_0" "0,1" line.long 0xFC "RGX_CR_USC_SLOT63_1,RGX_CR_USC_SLOT63_1" hexmask.long 0xFC 4.--31. 1. "Reserved_36,Reserved_36" newline hexmask.long.byte 0xFC 0.--3. 1. "STATUS,STATUS" group.long 0x4500++0x17 line.long 0x0 "RGX_CR_USC_BREAKPOINT1_0,RGX_CR_USC_BREAKPOINT1_0" hexmask.long 0x0 1.--31. 1. "ADDR,Breakpoint Address" newline bitfld.long 0x0 0. "Reserved_0,Reserved_0" "0,1" line.long 0x4 "RGX_CR_USC_BREAKPOINT1_1,RGX_CR_USC_BREAKPOINT1_1" hexmask.long 0x4 0.--31. 1. "Reserved_32,Reserved_32" line.long 0x8 "RGX_CR_USC_BREAKPOINT1_HANDLER_0,RGX_CR_USC_BREAKPOINT1_HANDLER_0" hexmask.long 0x8 1.--31. 1. "ADDR,Breakpoint Handler Address" newline bitfld.long 0x8 0. "Reserved_0,Reserved_0" "0,1" line.long 0xC "RGX_CR_USC_BREAKPOINT1_HANDLER_1,RGX_CR_USC_BREAKPOINT1_HANDLER_1" hexmask.long 0xC 0.--31. 1. "Reserved_32,Reserved_32" line.long 0x10 "RGX_CR_USC_BREAKPOINT1_CTRL_0,RGX_CR_USC_BREAKPOINT1_CTRL_0" hexmask.long 0x10 4.--31. 1. "Reserved_4,Reserved_4" newline bitfld.long 0x10 3. "ENABLE,0 = Breakpoint disabled 1 = Breakpoint enabled" "Breakpoint disabled,Breakpoint enabled" newline bitfld.long 0x10 0.--2. "DM,Data Master of Breakpoint" "0,1,2,3,4,5,6,7" line.long 0x14 "RGX_CR_USC_BREAKPOINT1_CTRL_1,RGX_CR_USC_BREAKPOINT1_CTRL_1" hexmask.long 0x14 0.--31. 1. "Reserved_4,Reserved_4" rgroup.long 0x45D8++0x7 line.long 0x0 "RGX_CR_USC_IDLE_0,RGX_CR_USC_IDLE_0" hexmask.long.tbyte 0x0 10.--31. 1. "Reserved_10,Reserved_10" newline bitfld.long 0x0 9. "USCITR,USCITR idle" "0,1" newline bitfld.long 0x0 8. "USCDMA,USCDMA idle" "0,1" newline bitfld.long 0x0 7. "USCFS,USCFS idle" "0,1" newline bitfld.long 0x0 6. "USCCS,USCCS idle" "0,1" newline bitfld.long 0x0 5. "USCPD3,USCPD idle" "0,1" newline bitfld.long 0x0 4. "USCPD2,USCPD idle" "0,1" newline bitfld.long 0x0 3. "USCPD1,USCPD idle" "0,1" newline bitfld.long 0x0 2. "USCPD0,USCPD idle" "0,1" newline bitfld.long 0x0 1. "USCPC,USCPC idle" "0,1" newline bitfld.long 0x0 0. "USCC,USCC idle" "0,1" line.long 0x4 "RGX_CR_USC_IDLE_1,RGX_CR_USC_IDLE_1" hexmask.long 0x4 0.--31. 1. "Reserved_10,Reserved_10" group.long 0x45E8++0x17 line.long 0x0 "RGX_CR_USC_ITRCOEFF_CACHE_0,USC Iterator Coefficient Cache Bypass bit" hexmask.long 0x0 1.--31. 1. "Reserved_1,Reserved_1" newline bitfld.long 0x0 0. "BYPASS,Bypass bit of the coefficient cache" "0,1" line.long 0x4 "RGX_CR_USC_ITRCOEFF_CACHE_1,USC Iterator Coefficient Cache Bypass bit" hexmask.long 0x4 0.--31. 1. "Reserved_1,Reserved_1" line.long 0x8 "RGX_CR_USC_ITRSMP_STATE_CACHE_0,USC ITRSMP State Cache Bypass bit" hexmask.long 0x8 1.--31. 1. "Reserved_1,Reserved_1" newline bitfld.long 0x8 0. "BYPASS,Bypass bit of the state cache" "0,1" line.long 0xC "RGX_CR_USC_ITRSMP_STATE_CACHE_1,USC ITRSMP State Cache Bypass bit" hexmask.long 0xC 0.--31. 1. "Reserved_1,Reserved_1" line.long 0x10 "RGX_CR_USC_ITRSMP_PRIORITY_0,USC ITRSMP priority information" hexmask.long 0x10 2.--31. 1. "Reserved_2,Reserved_2" newline bitfld.long 0x10 0.--1. "PERSISTENCE,Persistence value to use for ITRSMP instructions." "0,1,2,3" line.long 0x14 "RGX_CR_USC_ITRSMP_PRIORITY_1,USC ITRSMP priority information" hexmask.long 0x14 0.--31. 1. "Reserved_2,Reserved_2" repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) rgroup.long ($2+0x4600)++0x3 line.long 0x0 "RGX_CR_USC_PWR_INSTR_$1,Peformance counter associated with Power Monitoring" hexmask.long 0x0 0.--31. 1. "EXEC,Number of instructions executed (max 1 per clock)" repeat.end repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) rgroup.long ($2+0x4608)++0x3 line.long 0x0 "RGX_CR_USC_PWR_CMMN_STR_ACCESS_$1,Peformance counter associated with Power Monitoring" hexmask.long 0x0 0.--31. 1. "COUNT,Number of Common Store accesses (max of 4 per lock)" repeat.end repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) rgroup.long ($2+0x4610)++0x3 line.long 0x0 "RGX_CR_USC_PWR_CMMN_STR_$1,Peformance counter associated with Power Monitoring" hexmask.long 0x0 0.--31. 1. "WR_BANK_CLASH,Common Store: Number of write/write bank clashes" repeat.end repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) rgroup.long ($2+0x4618)++0x3 line.long 0x0 "RGX_CR_USC_PWR_UNI_STR_$1,Peformance counter associated with Power Monitoring" hexmask.long 0x0 0.--31. 1. "WR_BANK_CLASH,Unified Store: Number of write/write bank clashes" repeat.end repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) rgroup.long ($2+0x4620)++0x3 line.long 0x0 "RGX_CR_USC_PWR_NUM_FLOAT_$1,Peformance counter associated with Power Monitoring" hexmask.long 0x0 0.--31. 1. "OPS,Number of floating point ops; FAdd/Fmul=1 MAD=2; max 32x2=64 per clock" repeat.end repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) rgroup.long ($2+0x4628)++0x3 line.long 0x0 "RGX_CR_USC_PWR_NUM_INTEGER_$1,Peformance counter associated with Power Monitoring" hexmask.long 0x0 0.--31. 1. "OPS,Number of integer ops; Add/Mul=1 MAD=2 max 16*2=32 per clock" repeat.end repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) rgroup.long ($2+0x4630)++0x3 line.long 0x0 "RGX_CR_USC_PWR_NUM_COALU_$1,Peformance counter associated with Power Monitoring" hexmask.long 0x0 0.--31. 1. "OPS,Number of COALU ops; max of 16 per clock" repeat.end repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) rgroup.long ($2+0x4638)++0x3 line.long 0x0 "RGX_CR_USC_PWR_NUM_$1,Peformance counter associated with Power Monitoring" hexmask.long 0x0 0.--31. 1. "PENALTY_CYCLES,Penalty cycles for read/read and write/write clashes. For each instruction this is max(a b c d)" repeat.end repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) rgroup.long ($2+0x4640)++0x3 line.long 0x0 "RGX_CR_USC_PWR_AV_NUM_INST_VALID_$1,Peformance counter associated with Power Monitoring" hexmask.long 0x0 0.--31. 1. "VERT,Average number of instances valid out of 16 for vertex tasks" repeat.end repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) rgroup.long ($2+0x4648)++0x3 line.long 0x0 "RGX_CR_USC_PWR_NUM_ON_EDGE_PIXL_$1,Peformance counter associated with Power Monitoring" hexmask.long 0x0 0.--31. 1. "WRITE,Number of on-edge pixel output register writes" repeat.end repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) rgroup.long ($2+0x4650)++0x3 line.long 0x0 "RGX_CR_USC_PWR_NUM_OFF_EDGE_PIXL_$1,Peformance counter associated with Power Monitoring" hexmask.long 0x0 0.--31. 1. "WRITE,Number of off-edge pixel output register writes" repeat.end repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) rgroup.long ($2+0x4658)++0x3 line.long 0x0 "RGX_CR_USC_PWR_NUM_F16_$1,Peformance counter associated with Power Monitoring" hexmask.long 0x0 0.--31. 1. "OPS,Number of F16 operations. Max of 16" repeat.end repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) rgroup.long ($2+0x4660)++0x3 line.long 0x0 "RGX_CR_USC_PWR_USCPD_INSTR_$1,Peformance counter associated with Power Monitoring" hexmask.long 0x0 0.--31. 1. "COUNT,Number of instructions executed by USCPD" repeat.end repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) rgroup.long ($2+0x4668)++0x3 line.long 0x0 "RGX_CR_USC_PWR_INT_REG_ACCESS_$1,Peformance counter associated with Power Monitoring" hexmask.long 0x0 0.--31. 1. "COUNT,Number of internal register accesses. Max 128 per clock = 8 registers * 16 instances" repeat.end repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) rgroup.long ($2+0x4670)++0x3 line.long 0x0 "RGX_CR_USC_PWR_US_STR_ACCESS_$1,Peformance counter associated with Power Monitoring" hexmask.long 0x0 0.--31. 1. "COUNT,Number of unified sotre US bank accesses. Max of 32 per clock = 8 banks * 4 pipes" repeat.end group.long 0x4678++0x7 line.long 0x0 "RGX_CR_USC_HQ_RESCH_0,Disable rescheduling of slots in USCPC HQ" hexmask.long 0x0 2.--31. 1. "Reserved_2,Reserved_2" newline bitfld.long 0x0 1. "DISABLE_FOR_BE,Disable rescheduling for BE instr in USCPC" "0,1" newline bitfld.long 0x0 0. "DISABLE,Disable rescheduling in USCPC" "0,1" line.long 0x4 "RGX_CR_USC_HQ_RESCH_1,Disable rescheduling of slots in USCPC HQ" hexmask.long 0x4 0.--31. 1. "Reserved_2,Reserved_2" repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) rgroup.long ($2+0x5000)++0x3 line.long 0x0 "RGX_CR_USC_UVS0_CHECKSUM_$1,RGX_CR_USC_UVS0_CHECKSUM_0" hexmask.long 0x0 0.--31. 1. "VALUE,Checksum of USC to UVS writes from USC0" repeat.end repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) rgroup.long ($2+0x5008)++0x3 line.long 0x0 "RGX_CR_USC_UVS1_CHECKSUM_$1,RGX_CR_USC_UVS1_CHECKSUM_0" hexmask.long 0x0 0.--31. 1. "VALUE,Checksum of USC to UVS writes from USC1" repeat.end repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) rgroup.long ($2+0x5010)++0x3 line.long 0x0 "RGX_CR_USC_UVS2_CHECKSUM_$1,RGX_CR_USC_UVS2_CHECKSUM_0" hexmask.long 0x0 0.--31. 1. "VALUE,Checksum of USC to UVS writes from USC2" repeat.end repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) rgroup.long ($2+0x5018)++0x3 line.long 0x0 "RGX_CR_USC_UVS3_CHECKSUM_$1,RGX_CR_USC_UVS3_CHECKSUM_0" hexmask.long 0x0 0.--31. 1. "VALUE,Checksum of USC to UVS writes from USC3" repeat.end repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) rgroup.long ($2+0x5020)++0x3 line.long 0x0 "RGX_CR_PPP_SIGNATURE_$1,RGX_CR_PPP_SIGNATURE_0" hexmask.long 0x0 0.--31. 1. "VALUE,Signature of PPP to Clipper Interface" repeat.end repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) rgroup.long ($2+0x5028)++0x3 line.long 0x0 "RGX_CR_TE_SIGNATURE_$1,RGX_CR_TE_SIGNATURE_0" hexmask.long 0x0 0.--31. 1. "VALUE,Signature of TE control stream writes" repeat.end repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) rgroup.long ($2+0x5030)++0x3 line.long 0x0 "RGX_CR_VCE_CHECKSUM_$1,RGX_CR_VCE_CHECKSUM_0" hexmask.long 0x0 0.--31. 1. "VALUE,Checksum of VCE memory writes" repeat.end repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) rgroup.long ($2+0x5038)++0x3 line.long 0x0 "RGX_CR_ISP_PDS_CHECKSUM_$1,RGX_CR_ISP_PDS_CHECKSUM_0" hexmask.long 0x0 0.--31. 1. "VALUE,Checksum of ISP PDS Span Output" repeat.end repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) rgroup.long ($2+0x5040)++0x3 line.long 0x0 "RGX_CR_ISP_TPF_CHECKSUM_$1,RGX_CR_ISP_TPF_CHECKSUM_0" hexmask.long 0x0 0.--31. 1. "VALUE,Checksum of ISP TPF Object Output" repeat.end repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) rgroup.long ($2+0x5048)++0x3 line.long 0x0 "RGX_CR_TFPU_PLANE0_CHECKSUM_$1,RGX_CR_TFPU_PLANE0_CHECKSUM_0" hexmask.long 0x0 0.--31. 1. "VALUE,Checksum of TFPU Plane0 Output" repeat.end repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) rgroup.long ($2+0x5050)++0x3 line.long 0x0 "RGX_CR_TFPU_PLANE1_CHECKSUM_$1,RGX_CR_TFPU_PLANE1_CHECKSUM_0" hexmask.long 0x0 0.--31. 1. "VALUE,Checksum of TFPU Plane1 Output" repeat.end repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) rgroup.long ($2+0x5058)++0x3 line.long 0x0 "RGX_CR_PBE_CHECKSUM_$1,RGX_CR_PBE_CHECKSUM_0" hexmask.long 0x0 0.--31. 1. "VALUE,Checksum of PBE memory writes" repeat.end repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) rgroup.long ($2+0x5060)++0x3 line.long 0x0 "RGX_CR_PDS_DOUTM_STM_SIGNATURE_$1,RGX_CR_PDS_DOUTM_STM_SIGNATURE_0" hexmask.long 0x0 0.--31. 1. "VALUE,Signature of PDS DOUTM Stream Out MCU writes" repeat.end repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) rgroup.long ($2+0x5068)++0x3 line.long 0x0 "RGX_CR_IFPU_ISP_CHECKSUM_$1,RGX_CR_IFPU_ISP_CHECKSUM_0" hexmask.long 0x0 0.--31. 1. "VALUE,Checksum of IFPU Output" repeat.end repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) rgroup.long ($2+0x5070)++0x3 line.long 0x0 "RGX_CR_MCU_L0_TA_CHECKSUM_$1,RGX_CR_MCU_L0_TA_CHECKSUM_0" hexmask.long 0x0 0.--31. 1. "VALUE,Checksum of the PDS->USC from MCU for TA data" repeat.end repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) rgroup.long ($2+0x5078)++0x3 line.long 0x0 "RGX_CR_MCU_L0_3D_CHECKSUM_$1,RGX_CR_MCU_L0_3D_CHECKSUM_0" hexmask.long 0x0 0.--31. 1. "VALUE,Checksum of the PDS->USC from MCU for 3D data" repeat.end repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) rgroup.long ($2+0x5080)++0x3 line.long 0x0 "RGX_CR_MCU_L0_WRAP_TA_CHECKSUM_$1,RGX_CR_MCU_L0_WRAP_TA_CHECKSUM_0" hexmask.long 0x0 0.--31. 1. "VALUE,Checksum of the PDS->USC from MCU for TA data" repeat.end repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) rgroup.long ($2+0x5088)++0x3 line.long 0x0 "RGX_CR_MCU_L0_WRAP_3D_CHECKSUM_$1,RGX_CR_MCU_L0_WRAP_3D_CHECKSUM_0" hexmask.long 0x0 0.--31. 1. "VALUE,Checksum of the PDS->USC from MCU for 3D data" repeat.end repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) rgroup.long ($2+0x5100)++0x3 line.long 0x0 "RGX_CR_USC_UVS4_CHECKSUM_$1,RGX_CR_USC_UVS4_CHECKSUM_0" hexmask.long 0x0 0.--31. 1. "VALUE,Checksum of USC to UVS writes from USC4" repeat.end repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) rgroup.long ($2+0x5108)++0x3 line.long 0x0 "RGX_CR_USC_UVS5_CHECKSUM_$1,RGX_CR_USC_UVS5_CHECKSUM_0" hexmask.long 0x0 0.--31. 1. "VALUE,Checksum of USC to UVS writes from USC5" repeat.end repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) rgroup.long ($2+0x5148)++0x3 line.long 0x0 "RGX_CR_TDM_PDS_CHECKSUM_$1,RGX_CR_TDM_PDS_CHECKSUM_0" hexmask.long 0x0 0.--31. 1. "VALUE,Checksum of all TDM to PDS tile emits." repeat.end repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) rgroup.long ($2+0x5160)++0x3 line.long 0x0 "RGX_CR_PBE_CHECKSUM_NO_ADDR_$1,RGX_CR_PBE_CHECKSUM_NO_ADDR_0" hexmask.long 0x0 0.--31. 1. "VALUE,No address checksum of PBE memory writes" repeat.end repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) rgroup.long ($2+0x5200)++0x3 line.long 0x0 "RGX_CR_PBE_CHECKSUM_TDM_$1,RGX_CR_PBE_CHECKSUM_TDM_0" hexmask.long 0x0 0.--31. 1. "VALUE,TDM checksum of PBE memory writes" repeat.end repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) rgroup.long ($2+0x5208)++0x3 line.long 0x0 "RGX_CR_PBE_CHECKSUM_TDM_NO_ADDR_$1,RGX_CR_PBE_CHECKSUM_TDM_NO_ADDR_0" hexmask.long 0x0 0.--31. 1. "VALUE,No address TDM checksum of PBE memory writes" repeat.end group.long 0x6000++0x7 line.long 0x0 "RGX_CR_PERF_COUNTER_0,RGX_CR_PERF_COUNTER_0" hexmask.long 0x0 1.--31. 1. "Reserved_1,Reserved_1" newline bitfld.long 0x0 0. "RESET,A write of 1 to this register resets the Cycle Counters and holds them in Reset. A write of 0 enables them for Counting" "0,1" line.long 0x4 "RGX_CR_PERF_COUNTER_1,RGX_CR_PERF_COUNTER_1" hexmask.long 0x4 0.--31. 1. "Reserved_1,Reserved_1" repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) rgroup.long ($2+0x6008)++0x3 line.long 0x0 "RGX_CR_PERF_TA_PHASE_$1,RGX_CR_PERF_TA_PHASE_0" hexmask.long 0x0 0.--31. 1. "COUNT,The number of TA phases completed" repeat.end repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) rgroup.long ($2+0x6010)++0x3 line.long 0x0 "RGX_CR_PERF_3D_PHASE_$1,RGX_CR_PERF_3D_PHASE_0" hexmask.long 0x0 0.--31. 1. "COUNT,The number of 3D phases completed" repeat.end repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) rgroup.long ($2+0x6018)++0x3 line.long 0x0 "RGX_CR_PERF_COMPUTE_PHASE_$1,RGX_CR_PERF_COMPUTE_PHASE_0" hexmask.long 0x0 0.--31. 1. "COUNT,The number of Compute phases completed" repeat.end repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) rgroup.long ($2+0x6020)++0x3 line.long 0x0 "RGX_CR_PERF_TA_CYCLE_$1,RGX_CR_PERF_TA_CYCLE_0" hexmask.long 0x0 0.--31. 1. "COUNT,The number of cycles spent in TA phases" repeat.end repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) rgroup.long ($2+0x6028)++0x3 line.long 0x0 "RGX_CR_PERF_3D_CYCLE_$1,RGX_CR_PERF_3D_CYCLE_0" hexmask.long 0x0 0.--31. 1. "COUNT,The number of cycles spent in 3D phases" repeat.end repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) rgroup.long ($2+0x6030)++0x3 line.long 0x0 "RGX_CR_PERF_COMPUTE_CYCLE_$1,RGX_CR_PERF_COMPUTE_CYCLE_0" hexmask.long 0x0 0.--31. 1. "COUNT,The number of cycles spent in Compute phases" repeat.end repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) rgroup.long ($2+0x6038)++0x3 line.long 0x0 "RGX_CR_PERF_TA_OR_3D_CYCLE_$1,RGX_CR_PERF_TA_OR_3D_CYCLE_0" hexmask.long 0x0 0.--31. 1. "COUNT,The number of cycles spent in TA phases or 3D phases" repeat.end repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) rgroup.long ($2+0x6040)++0x3 line.long 0x0 "RGX_CR_PERF_INITIAL_TA_CYCLE_$1,RGX_CR_PERF_INITIAL_TA_CYCLE_0" hexmask.long 0x0 0.--31. 1. "COUNT,The number of cycles spent in TA phases before the first 3D phase" repeat.end repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) rgroup.long ($2+0x6048)++0x3 line.long 0x0 "RGX_CR_PERF_FINAL_3D_CYCLE_$1,RGX_CR_PERF_FINAL_3D_CYCLE_0" hexmask.long 0x0 0.--31. 1. "COUNT,The number of cycles spent in the last 3D phase" repeat.end repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) rgroup.long ($2+0x6050)++0x3 line.long 0x0 "RGX_CR_PERF_BIF0_READ_$1,RGX_CR_PERF_BIF0_READ_0" hexmask.long 0x0 0.--31. 1. "COUNT,The number of BIF0-to-SLC reads" repeat.end repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) rgroup.long ($2+0x6058)++0x3 line.long 0x0 "RGX_CR_PERF_BIF0_WRITE_$1,RGX_CR_PERF_BIF0_WRITE_0" hexmask.long 0x0 0.--31. 1. "COUNT,The number of BIF0-to-SLC writes" repeat.end repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) rgroup.long ($2+0x6060)++0x3 line.long 0x0 "RGX_CR_PERF_BIF0_BYTE_WRITE_$1,RGX_CR_PERF_BIF0_BYTE_WRITE_0" hexmask.long 0x0 0.--31. 1. "COUNT,The number of BIF0-to-SLC bytes written" repeat.end repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) rgroup.long ($2+0x6068)++0x3 line.long 0x0 "RGX_CR_PERF_BIF0_READ_STALL_$1,RGX_CR_PERF_BIF0_READ_STALL_0" hexmask.long 0x0 0.--31. 1. "COUNT,The number of BIF0-to-SLC read stalls" repeat.end repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) rgroup.long ($2+0x6070)++0x3 line.long 0x0 "RGX_CR_PERF_BIF0_WRITE_STALL_$1,RGX_CR_PERF_BIF0_WRITE_STALL_0" hexmask.long 0x0 0.--31. 1. "COUNT,The number of BIF0-to-SLC write stalls" repeat.end repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) rgroup.long ($2+0x60A0)++0x3 line.long 0x0 "RGX_CR_PERF_SLC0_READ_$1,RGX_CR_PERF_SLC0_READ_0" hexmask.long 0x0 0.--31. 1. "COUNT,The number of SLC-to-MEM interface 0 reads" repeat.end repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) rgroup.long ($2+0x60A8)++0x3 line.long 0x0 "RGX_CR_PERF_SLC0_WRITE_$1,RGX_CR_PERF_SLC0_WRITE_0" hexmask.long 0x0 0.--31. 1. "COUNT,The number of SLC-to-MEM interface 0 writes" repeat.end repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) rgroup.long ($2+0x60B0)++0x3 line.long 0x0 "RGX_CR_PERF_SLC0_BYTE_WRITE_$1,RGX_CR_PERF_SLC0_BYTE_WRITE_0" hexmask.long 0x0 0.--31. 1. "COUNT,The number of SLC-to-MEM interface 0 bytes written" repeat.end repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) rgroup.long ($2+0x60B8)++0x3 line.long 0x0 "RGX_CR_PERF_SLC0_READ_STALL_$1,RGX_CR_PERF_SLC0_READ_STALL_0" hexmask.long 0x0 0.--31. 1. "COUNT,The number of SLC-to-MEM interface 0 command stalls" repeat.end repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) rgroup.long ($2+0x60C0)++0x3 line.long 0x0 "RGX_CR_PERF_SLC0_WRITE_STALL_$1,RGX_CR_PERF_SLC0_WRITE_STALL_0" hexmask.long 0x0 0.--31. 1. "COUNT,The number of SLC-to-MEM insterface 0 write channel stalls" repeat.end repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) rgroup.long ($2+0x60C8)++0x3 line.long 0x0 "RGX_CR_PERF_SLC1_READ_$1,RGX_CR_PERF_SLC1_READ_0" hexmask.long 0x0 0.--31. 1. "COUNT,The number of SLC-to-MEM interface 1 reads" repeat.end repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) rgroup.long ($2+0x60D0)++0x3 line.long 0x0 "RGX_CR_PERF_SLC1_WRITE_$1,RGX_CR_PERF_SLC1_WRITE_0" hexmask.long 0x0 0.--31. 1. "COUNT,The number of SLC-to-MEM interface 1 writes" repeat.end repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) rgroup.long ($2+0x60D8)++0x3 line.long 0x0 "RGX_CR_PERF_SLC1_BYTE_WRITE_$1,RGX_CR_PERF_SLC1_BYTE_WRITE_0" hexmask.long 0x0 0.--31. 1. "COUNT,The number of SLC-to-MEM interface 1 bytes written" repeat.end repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) rgroup.long ($2+0x60E0)++0x3 line.long 0x0 "RGX_CR_PERF_SLC1_READ_STALL_$1,RGX_CR_PERF_SLC1_READ_STALL_0" hexmask.long 0x0 0.--31. 1. "COUNT,The number of SLC-to-MEM interface 1 command stalls" repeat.end repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) rgroup.long ($2+0x60E8)++0x3 line.long 0x0 "RGX_CR_PERF_SLC1_WRITE_STALL_$1,RGX_CR_PERF_SLC1_WRITE_STALL_0" hexmask.long 0x0 0.--31. 1. "COUNT,The number of SLC-to-MEM interface 1 write channel stalls" repeat.end repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) rgroup.long ($2+0x60F0)++0x3 line.long 0x0 "RGX_CR_PERF_SLC_BURST_SIZE0_IN_$1,RGX_CR_PERF_SLC_BURST_SIZE0_IN_0" hexmask.long 0x0 0.--31. 1. "VALUE,The number of burstlength 0 accesses into the Burst Combiner" repeat.end repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) rgroup.long ($2+0x60F8)++0x3 line.long 0x0 "RGX_CR_PERF_SLC_BURST_SIZE1_IN_$1,RGX_CR_PERF_SLC_BURST_SIZE1_IN_0" hexmask.long 0x0 0.--31. 1. "VALUE,The number of burstlength 1 accesses into the Burst Combiner" repeat.end repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) rgroup.long ($2+0x6100)++0x3 line.long 0x0 "RGX_CR_PERF_SLC_BURST_SIZE0_OUT_$1,RGX_CR_PERF_SLC_BURST_SIZE0_OUT_0" hexmask.long 0x0 0.--31. 1. "VALUE,The number of burstlength 0 accesses out of the Burst Combiner" repeat.end repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) rgroup.long ($2+0x6108)++0x3 line.long 0x0 "RGX_CR_PERF_SLC_BURST_SIZE1_OUT_$1,RGX_CR_PERF_SLC_BURST_SIZE1_OUT_0" hexmask.long 0x0 0.--31. 1. "VALUE,The number of burstlength 1 accesses out of the Burst Combiner" repeat.end repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) rgroup.long ($2+0x6110)++0x3 line.long 0x0 "RGX_CR_PERF_SLC_BURST_SIZE2_OUT_$1,RGX_CR_PERF_SLC_BURST_SIZE2_OUT_0" hexmask.long 0x0 0.--31. 1. "VALUE,The number of burstlength 2 accesses out of the Burst Combiner" repeat.end repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) rgroup.long ($2+0x6118)++0x3 line.long 0x0 "RGX_CR_PERF_SLC0_READ_ID_STALL_$1,RGX_CR_PERF_SLC0_READ_ID_STALL_0" hexmask.long 0x0 0.--31. 1. "COUNT,The number of cycles the SLC spends stalled because all Read IDs on memory interface 0 are currently in use" repeat.end repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) rgroup.long ($2+0x6120)++0x3 line.long 0x0 "RGX_CR_PERF_SLC0_WRITE_ID_STALL_$1,RGX_CR_PERF_SLC0_WRITE_ID_STALL_0" hexmask.long 0x0 0.--31. 1. "COUNT,The number of cycles the SLC spends stalled because all Write IDs on memory interface 0 are currently in use" repeat.end repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) rgroup.long ($2+0x6128)++0x3 line.long 0x0 "RGX_CR_PERF_SLC1_READ_ID_STALL_$1,RGX_CR_PERF_SLC1_READ_ID_STALL_0" hexmask.long 0x0 0.--31. 1. "COUNT,The number of cycles the SLC spends stalled because all Read IDs on memory interface 1 are currently in use" repeat.end repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) rgroup.long ($2+0x6130)++0x3 line.long 0x0 "RGX_CR_PERF_SLC1_WRITE_ID_STALL_$1,RGX_CR_PERF_SLC1_WRITE_ID_STALL_0" hexmask.long 0x0 0.--31. 1. "COUNT,The number of cycles the SLC spends stalled because all Write IDs on memory interface 1 are currently in use" repeat.end repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) rgroup.long ($2+0x6138)++0x3 line.long 0x0 "RGX_CR_PERF_SLC_BURST_SIZE3_OUT_$1,RGX_CR_PERF_SLC_BURST_SIZE3_OUT_0" hexmask.long 0x0 0.--31. 1. "VALUE,The number of burstlength 3 accesses out of the Burst Combiner" repeat.end repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) rgroup.long ($2+0x6140)++0x3 line.long 0x0 "RGX_CR_PERF_SLC2_READ_$1,RGX_CR_PERF_SLC2_READ_0" hexmask.long 0x0 0.--31. 1. "COUNT,The number of SLC-to-MEM interface 2 reads" repeat.end repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) rgroup.long ($2+0x6148)++0x3 line.long 0x0 "RGX_CR_PERF_SLC2_WRITE_$1,RGX_CR_PERF_SLC2_WRITE_0" hexmask.long 0x0 0.--31. 1. "COUNT,The number of SLC-to-MEM interface 2 writes" repeat.end repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) rgroup.long ($2+0x6150)++0x3 line.long 0x0 "RGX_CR_PERF_SLC2_BYTE_WRITE_$1,RGX_CR_PERF_SLC2_BYTE_WRITE_0" hexmask.long 0x0 0.--31. 1. "COUNT,The number of SLC-to-MEM interface 2 bytes written" repeat.end repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) rgroup.long ($2+0x6158)++0x3 line.long 0x0 "RGX_CR_PERF_SLC2_READ_STALL_$1,RGX_CR_PERF_SLC2_READ_STALL_0" hexmask.long 0x0 0.--31. 1. "COUNT,The number of SLC-to-MEM interface 2 command stalls" repeat.end repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) rgroup.long ($2+0x6160)++0x3 line.long 0x0 "RGX_CR_PERF_SLC2_WRITE_STALL_$1,RGX_CR_PERF_SLC2_WRITE_STALL_0" hexmask.long 0x0 0.--31. 1. "COUNT,The number of SLC-to-MEM interface 2 write channel stalls" repeat.end repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) rgroup.long ($2+0x6168)++0x3 line.long 0x0 "RGX_CR_PERF_SLC3_READ_$1,RGX_CR_PERF_SLC3_READ_0" hexmask.long 0x0 0.--31. 1. "COUNT,The number of SLC-to-MEM interface 3 reads" repeat.end repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) rgroup.long ($2+0x6170)++0x3 line.long 0x0 "RGX_CR_PERF_SLC3_WRITE_$1,RGX_CR_PERF_SLC3_WRITE_0" hexmask.long 0x0 0.--31. 1. "COUNT,The number of SLC-to-MEM interface 3 writes" repeat.end repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) rgroup.long ($2+0x6178)++0x3 line.long 0x0 "RGX_CR_PERF_SLC3_BYTE_WRITE_$1,RGX_CR_PERF_SLC3_BYTE_WRITE_0" hexmask.long 0x0 0.--31. 1. "COUNT,The number of SLC-to-MEM interface 3 bytes written" repeat.end repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) rgroup.long ($2+0x6180)++0x3 line.long 0x0 "RGX_CR_PERF_SLC3_READ_STALL_$1,RGX_CR_PERF_SLC3_READ_STALL_0" hexmask.long 0x0 0.--31. 1. "COUNT,The number of SLC-to-MEM interface 3 command stalls" repeat.end repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) rgroup.long ($2+0x6188)++0x3 line.long 0x0 "RGX_CR_PERF_SLC3_WRITE_STALL_$1,RGX_CR_PERF_SLC3_WRITE_STALL_0" hexmask.long 0x0 0.--31. 1. "COUNT,The number of SLC-to-MEM interface 3 write channel stalls" repeat.end repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) rgroup.long ($2+0x6190)++0x3 line.long 0x0 "RGX_CR_PERF_SLC_BURST_SIZE2_IN_$1,RGX_CR_PERF_SLC_BURST_SIZE2_IN_0" hexmask.long 0x0 0.--31. 1. "VALUE,The number of burstlength 2 accesses into the Burst Combiner" repeat.end repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) rgroup.long ($2+0x6198)++0x3 line.long 0x0 "RGX_CR_PERF_SLC_BURST_SIZE3_IN_$1,RGX_CR_PERF_SLC_BURST_SIZE3_IN_0" hexmask.long 0x0 0.--31. 1. "VALUE,The number of burstlength 3 accesses into the Burst Combiner" repeat.end repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) rgroup.long ($2+0x6220)++0x3 line.long 0x0 "RGX_CR_PERF_3D_SPINUP_$1,RGX_CR_PERF_3D_SPINUP_0" hexmask.long 0x0 0.--31. 1. "CYCLES,The number of cycles it takes the 3D pipeline to spin-up" repeat.end group.long 0x6300++0x7 line.long 0x0 "RGX_CR_POWER_ESTIMATE_REQ_RST_0,Power estimate Request/Reset - The generation of the power estimate will be initiated upon a write to the power managment register. This will be driven down to the relevant blocks to reset the counters and also to start.." hexmask.long 0x0 1.--31. 1. "Reserved_1,Reserved_1" newline bitfld.long 0x0 0. "VALUE,VALUE" "0,1" line.long 0x4 "RGX_CR_POWER_ESTIMATE_REQ_RST_1,Power estimate Request/Reset - The generation of the power estimate will be initiated upon a write to the power managment register. This will be driven down to the relevant blocks to reset the counters and also to start.." hexmask.long 0x4 0.--31. 1. "Reserved_1,Reserved_1" repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) group.long ($2+0x6310)++0x3 line.long 0x0 "RGX_CR_POWER_ESTIMATE_SAMPLE_COUNT_$1,Power Estimate Sample Count - This defines the number of cycles over which power monitoring will occur. When the POWER_ESTIMIATE_REQ_RST is written to POWER_ESTIMATE_SAMPLE_COUNT will begin to count down from its.." hexmask.long 0x0 0.--31. 1. "VALUE,VALUE" repeat.end rgroup.long 0x6318++0x7 line.long 0x0 "RGX_CR_POWER_ESTIMATE_READY_0,Power estimate Ready - A system event (portmap signal and maskable interrupt) is output when the power estimate has been completed and the power monitor register is updated. Logic or firmware or both will manage the SOC.." hexmask.long.word 0x0 17.--31. 1. "Reserved_17,Reserved_17" newline bitfld.long 0x0 16. "FB_CDC,FB_CDC" "0,1" newline bitfld.long 0x0 15. "Reserved_15,Reserved_15" "0,1" newline bitfld.long 0x0 14. "SLC,SLC" "0,1" newline bitfld.long 0x0 13. "TILING,TILING" "0,1" newline bitfld.long 0x0 12. "JONES,JONES" "0,1" newline bitfld.long 0x0 10.--11. "Reserved_10,Reserved_10" "0,1,2,3" newline bitfld.long 0x0 9. "TA,TA" "0,1" newline bitfld.long 0x0 8. "RASTERISATION,RASTERISATION" "0,1" newline bitfld.long 0x0 7. "HUB,HUB" "0,1" newline bitfld.long 0x0 6. "BIFPMCACHE,BIFPMCACHE" "0,1" newline bitfld.long 0x0 5. "Reserved_5,Reserved_5" "0,1" newline bitfld.long 0x0 4. "TPU_MCU,TPU_MCU" "0,1" newline bitfld.long 0x0 1.--3. "Reserved_1,Reserved_1" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 0. "USC,USC" "0,1" line.long 0x4 "RGX_CR_POWER_ESTIMATE_READY_1,Power estimate Ready - A system event (portmap signal and maskable interrupt) is output when the power estimate has been completed and the power monitor register is updated. Logic or firmware or both will manage the SOC.." hexmask.long 0x4 0.--31. 1. "Reserved_17,Reserved_17" repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) group.long ($2+0x6320)++0x3 line.long 0x0 "RGX_CR_POWER_ESTIMATE_GAIN_COEFF_$1,Final Gain coefficient to apply to summation of all power monitoring quotients" hexmask.long 0x0 0.--31. 1. "VALUE,VALUE" repeat.end repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) group.long ($2+0x6328)++0x3 line.long 0x0 "RGX_CR_POWER_ESTIMATE_RESULT_$1,Power Estimate Result. This represents the estimation of the total system power usage." hexmask.long 0x0 0.--31. 1. "VALUE,VALUE" repeat.end group.long 0x6330++0x7 line.long 0x0 "RGX_CR_PERF_COUNT_MODE_ONLY_0,This register bit set means we need to do only perf-counter gathering and nothing to do with pwr-perf related counting" hexmask.long 0x0 1.--31. 1. "Reserved_1,Reserved_1" newline bitfld.long 0x0 0. "VALUE,VALUE" "0,1" line.long 0x4 "RGX_CR_PERF_COUNT_MODE_ONLY_1,This register bit set means we need to do only perf-counter gathering and nothing to do with pwr-perf related counting" hexmask.long 0x4 0.--31. 1. "Reserved_1,Reserved_1" rgroup.long 0x6500++0x2F line.long 0x0 "RGX_CR_AVG_NON_CRITICAL_MEM0_LATENCY_0,RGX_CR_AVG_NON_CRITICAL_MEM0_LATENCY_0" hexmask.long.tbyte 0x0 12.--31. 1. "Reserved_12,Reserved_12" newline hexmask.long.word 0x0 0.--11. 1. "COUNT,The average number of read latency cycles incur at external memory for non critical tag" line.long 0x4 "RGX_CR_AVG_NON_CRITICAL_MEM0_LATENCY_1,RGX_CR_AVG_NON_CRITICAL_MEM0_LATENCY_1" hexmask.long 0x4 0.--31. 1. "Reserved_12,Reserved_12" line.long 0x8 "RGX_CR_MIN_NON_CRITICAL_MEM0_LATENCY_0,RGX_CR_MIN_NON_CRITICAL_MEM0_LATENCY_0" hexmask.long.tbyte 0x8 12.--31. 1. "Reserved_12,Reserved_12" newline hexmask.long.word 0x8 0.--11. 1. "COUNT,The min number of read latency cycles incur at external memory for non critical tag" line.long 0xC "RGX_CR_MIN_NON_CRITICAL_MEM0_LATENCY_1,RGX_CR_MIN_NON_CRITICAL_MEM0_LATENCY_1" hexmask.long 0xC 0.--31. 1. "Reserved_12,Reserved_12" line.long 0x10 "RGX_CR_MAX_NON_CRITICAL_MEM0_LATENCY_0,RGX_CR_MAX_NON_CRITICAL_MEM0_LATENCY_0" hexmask.long.tbyte 0x10 12.--31. 1. "Reserved_12,Reserved_12" newline hexmask.long.word 0x10 0.--11. 1. "COUNT,The max number of read latency cycles incur at external memory for non critical tag" line.long 0x14 "RGX_CR_MAX_NON_CRITICAL_MEM0_LATENCY_1,RGX_CR_MAX_NON_CRITICAL_MEM0_LATENCY_1" hexmask.long 0x14 0.--31. 1. "Reserved_12,Reserved_12" line.long 0x18 "RGX_CR_AVG_CRITICAL_MEM0_LATENCY_0,RGX_CR_AVG_CRITICAL_MEM0_LATENCY_0" hexmask.long.tbyte 0x18 12.--31. 1. "Reserved_12,Reserved_12" newline hexmask.long.word 0x18 0.--11. 1. "COUNT,The average number of read latency cycles incur at external memory for critical tag" line.long 0x1C "RGX_CR_AVG_CRITICAL_MEM0_LATENCY_1,RGX_CR_AVG_CRITICAL_MEM0_LATENCY_1" hexmask.long 0x1C 0.--31. 1. "Reserved_12,Reserved_12" line.long 0x20 "RGX_CR_MIN_CRITICAL_MEM0_LATENCY_0,RGX_CR_MIN_CRITICAL_MEM0_LATENCY_0" hexmask.long.tbyte 0x20 12.--31. 1. "Reserved_12,Reserved_12" newline hexmask.long.word 0x20 0.--11. 1. "COUNT,The min number of read latency cycles incur at external memory for critical tag" line.long 0x24 "RGX_CR_MIN_CRITICAL_MEM0_LATENCY_1,RGX_CR_MIN_CRITICAL_MEM0_LATENCY_1" hexmask.long 0x24 0.--31. 1. "Reserved_12,Reserved_12" line.long 0x28 "RGX_CR_MAX_CRITICAL_MEM0_LATENCY_0,RGX_CR_MAX_CRITICAL_MEM0_LATENCY_0" hexmask.long.tbyte 0x28 12.--31. 1. "Reserved_12,Reserved_12" newline hexmask.long.word 0x28 0.--11. 1. "COUNT,The max number of read latency cycles incur at external memory for critical tag" line.long 0x2C "RGX_CR_MAX_CRITICAL_MEM0_LATENCY_1,RGX_CR_MAX_CRITICAL_MEM0_LATENCY_1" hexmask.long 0x2C 0.--31. 1. "Reserved_12,Reserved_12" group.long 0x6530++0x7 line.long 0x0 "RGX_CR_USER_DEFINED_MEM0_MH_TAG_0,Writing '1' followed by mh_tag value at the lsb end of this register starts the user defined mh_tag value for latency calculation. Default value is zero where this feature is turned off. Bit [6] - Enable bit to turn on.." hexmask.long 0x0 7.--31. 1. "Reserved_7,Reserved_7" newline hexmask.long.byte 0x0 0.--6. 1. "VALUE,VALUE" line.long 0x4 "RGX_CR_USER_DEFINED_MEM0_MH_TAG_1,Writing '1' followed by mh_tag value at the lsb end of this register starts the user defined mh_tag value for latency calculation. Default value is zero where this feature is turned off. Bit [6] - Enable bit to turn on.." hexmask.long 0x4 0.--31. 1. "Reserved_7,Reserved_7" rgroup.long 0x6538++0x57 line.long 0x0 "RGX_CR_AVG_USER_MH_TAG_MEM0_LATENCY_0,RGX_CR_AVG_USER_MH_TAG_MEM0_LATENCY_0" hexmask.long.tbyte 0x0 12.--31. 1. "Reserved_12,Reserved_12" newline hexmask.long.word 0x0 0.--11. 1. "COUNT,The average number of read latency cycles incur at external memory for user_defined tag" line.long 0x4 "RGX_CR_AVG_USER_MH_TAG_MEM0_LATENCY_1,RGX_CR_AVG_USER_MH_TAG_MEM0_LATENCY_1" hexmask.long 0x4 0.--31. 1. "Reserved_12,Reserved_12" line.long 0x8 "RGX_CR_MIN_USER_MH_TAG_MEM0_LATENCY_0,RGX_CR_MIN_USER_MH_TAG_MEM0_LATENCY_0" hexmask.long.tbyte 0x8 12.--31. 1. "Reserved_12,Reserved_12" newline hexmask.long.word 0x8 0.--11. 1. "COUNT,The min number of read latency cycles incur at external memory for user defined tag" line.long 0xC "RGX_CR_MIN_USER_MH_TAG_MEM0_LATENCY_1,RGX_CR_MIN_USER_MH_TAG_MEM0_LATENCY_1" hexmask.long 0xC 0.--31. 1. "Reserved_12,Reserved_12" line.long 0x10 "RGX_CR_MAX_USER_MH_TAG_MEM0_LATENCY_0,RGX_CR_MAX_USER_MH_TAG_MEM0_LATENCY_0" hexmask.long.tbyte 0x10 12.--31. 1. "Reserved_12,Reserved_12" newline hexmask.long.word 0x10 0.--11. 1. "COUNT,The max number of read latency cycles incur at external memory for user defined tag" line.long 0x14 "RGX_CR_MAX_USER_MH_TAG_MEM0_LATENCY_1,RGX_CR_MAX_USER_MH_TAG_MEM0_LATENCY_1" hexmask.long 0x14 0.--31. 1. "Reserved_12,Reserved_12" line.long 0x18 "RGX_CR_MIN_NON_CRITICAL_MEM0_LATENCY_MH_TAG_0,RGX_CR_MIN_NON_CRITICAL_MEM0_LATENCY_MH_TAG_0" hexmask.long 0x18 6.--31. 1. "Reserved_6,Reserved_6" newline hexmask.long.byte 0x18 0.--5. 1. "VALUE,The mh_tag value of min read latency cycles for non critical tag" line.long 0x1C "RGX_CR_MIN_NON_CRITICAL_MEM0_LATENCY_MH_TAG_1,RGX_CR_MIN_NON_CRITICAL_MEM0_LATENCY_MH_TAG_1" hexmask.long 0x1C 0.--31. 1. "Reserved_6,Reserved_6" line.long 0x20 "RGX_CR_MAX_NON_CRITICAL_MEM0_LATENCY_MH_TAG_0,RGX_CR_MAX_NON_CRITICAL_MEM0_LATENCY_MH_TAG_0" hexmask.long 0x20 6.--31. 1. "Reserved_6,Reserved_6" newline hexmask.long.byte 0x20 0.--5. 1. "VALUE,The mh_tag value of max read latency cycles for non critical tag" line.long 0x24 "RGX_CR_MAX_NON_CRITICAL_MEM0_LATENCY_MH_TAG_1,RGX_CR_MAX_NON_CRITICAL_MEM0_LATENCY_MH_TAG_1" hexmask.long 0x24 0.--31. 1. "Reserved_6,Reserved_6" line.long 0x28 "RGX_CR_AVG_NON_CRITICAL_MEM1_LATENCY_0,RGX_CR_AVG_NON_CRITICAL_MEM1_LATENCY_0" hexmask.long.tbyte 0x28 12.--31. 1. "Reserved_12,Reserved_12" newline hexmask.long.word 0x28 0.--11. 1. "COUNT,The average number of read latency cycles incur at external memory for non critical tag" line.long 0x2C "RGX_CR_AVG_NON_CRITICAL_MEM1_LATENCY_1,RGX_CR_AVG_NON_CRITICAL_MEM1_LATENCY_1" hexmask.long 0x2C 0.--31. 1. "Reserved_12,Reserved_12" line.long 0x30 "RGX_CR_MIN_NON_CRITICAL_MEM1_LATENCY_0,RGX_CR_MIN_NON_CRITICAL_MEM1_LATENCY_0" hexmask.long.tbyte 0x30 12.--31. 1. "Reserved_12,Reserved_12" newline hexmask.long.word 0x30 0.--11. 1. "COUNT,The min number of read latency cycles incur at external memory for non critical tag" line.long 0x34 "RGX_CR_MIN_NON_CRITICAL_MEM1_LATENCY_1,RGX_CR_MIN_NON_CRITICAL_MEM1_LATENCY_1" hexmask.long 0x34 0.--31. 1. "Reserved_12,Reserved_12" line.long 0x38 "RGX_CR_MAX_NON_CRITICAL_MEM1_LATENCY_0,RGX_CR_MAX_NON_CRITICAL_MEM1_LATENCY_0" hexmask.long.tbyte 0x38 12.--31. 1. "Reserved_12,Reserved_12" newline hexmask.long.word 0x38 0.--11. 1. "COUNT,The max number of read latency cycles incur at external memory for non critical tag" line.long 0x3C "RGX_CR_MAX_NON_CRITICAL_MEM1_LATENCY_1,RGX_CR_MAX_NON_CRITICAL_MEM1_LATENCY_1" hexmask.long 0x3C 0.--31. 1. "Reserved_12,Reserved_12" line.long 0x40 "RGX_CR_AVG_CRITICAL_MEM1_LATENCY_0,RGX_CR_AVG_CRITICAL_MEM1_LATENCY_0" hexmask.long.tbyte 0x40 12.--31. 1. "Reserved_12,Reserved_12" newline hexmask.long.word 0x40 0.--11. 1. "COUNT,The average number of read latency cycles incur at external memory for critical tag" line.long 0x44 "RGX_CR_AVG_CRITICAL_MEM1_LATENCY_1,RGX_CR_AVG_CRITICAL_MEM1_LATENCY_1" hexmask.long 0x44 0.--31. 1. "Reserved_12,Reserved_12" line.long 0x48 "RGX_CR_MIN_CRITICAL_MEM1_LATENCY_0,RGX_CR_MIN_CRITICAL_MEM1_LATENCY_0" hexmask.long.tbyte 0x48 12.--31. 1. "Reserved_12,Reserved_12" newline hexmask.long.word 0x48 0.--11. 1. "COUNT,The min number of read latency cycles incur at external memory for critical tag" line.long 0x4C "RGX_CR_MIN_CRITICAL_MEM1_LATENCY_1,RGX_CR_MIN_CRITICAL_MEM1_LATENCY_1" hexmask.long 0x4C 0.--31. 1. "Reserved_12,Reserved_12" line.long 0x50 "RGX_CR_MAX_CRITICAL_MEM1_LATENCY_0,RGX_CR_MAX_CRITICAL_MEM1_LATENCY_0" hexmask.long.tbyte 0x50 12.--31. 1. "Reserved_12,Reserved_12" newline hexmask.long.word 0x50 0.--11. 1. "COUNT,The max number of read latency cycles incur at external memory for critical tag" line.long 0x54 "RGX_CR_MAX_CRITICAL_MEM1_LATENCY_1,RGX_CR_MAX_CRITICAL_MEM1_LATENCY_1" hexmask.long 0x54 0.--31. 1. "Reserved_12,Reserved_12" group.long 0x6590++0x7 line.long 0x0 "RGX_CR_USER_DEFINED_MEM1_MH_TAG_0,Writing '1' followed by mh_tag value at the lsb end of this register starts the user defined mh_tag value for latency calculation. Default value is zero where this feature is turned off. Bit [6] - Enable bit to turn on.." hexmask.long 0x0 7.--31. 1. "Reserved_7,Reserved_7" newline hexmask.long.byte 0x0 0.--6. 1. "VALUE,VALUE" line.long 0x4 "RGX_CR_USER_DEFINED_MEM1_MH_TAG_1,Writing '1' followed by mh_tag value at the lsb end of this register starts the user defined mh_tag value for latency calculation. Default value is zero where this feature is turned off. Bit [6] - Enable bit to turn on.." hexmask.long 0x4 0.--31. 1. "Reserved_7,Reserved_7" rgroup.long 0x6598++0x27 line.long 0x0 "RGX_CR_AVG_USER_MH_TAG_MEM1_LATENCY_0,RGX_CR_AVG_USER_MH_TAG_MEM1_LATENCY_0" hexmask.long.tbyte 0x0 12.--31. 1. "Reserved_12,Reserved_12" newline hexmask.long.word 0x0 0.--11. 1. "COUNT,The average number of read latency cycles incur at external memory for user_defined tag" line.long 0x4 "RGX_CR_AVG_USER_MH_TAG_MEM1_LATENCY_1,RGX_CR_AVG_USER_MH_TAG_MEM1_LATENCY_1" hexmask.long 0x4 0.--31. 1. "Reserved_12,Reserved_12" line.long 0x8 "RGX_CR_MIN_USER_MH_TAG_MEM1_LATENCY_0,RGX_CR_MIN_USER_MH_TAG_MEM1_LATENCY_0" hexmask.long.tbyte 0x8 12.--31. 1. "Reserved_12,Reserved_12" newline hexmask.long.word 0x8 0.--11. 1. "COUNT,The min number of read latency cycles incur at external memory for user defined tag" line.long 0xC "RGX_CR_MIN_USER_MH_TAG_MEM1_LATENCY_1,RGX_CR_MIN_USER_MH_TAG_MEM1_LATENCY_1" hexmask.long 0xC 0.--31. 1. "Reserved_12,Reserved_12" line.long 0x10 "RGX_CR_MAX_USER_MH_TAG_MEM1_LATENCY_0,RGX_CR_MAX_USER_MH_TAG_MEM1_LATENCY_0" hexmask.long.tbyte 0x10 12.--31. 1. "Reserved_12,Reserved_12" newline hexmask.long.word 0x10 0.--11. 1. "COUNT,The max number of read latency cycles incur at external memory for user defined tag" line.long 0x14 "RGX_CR_MAX_USER_MH_TAG_MEM1_LATENCY_1,RGX_CR_MAX_USER_MH_TAG_MEM1_LATENCY_1" hexmask.long 0x14 0.--31. 1. "Reserved_12,Reserved_12" line.long 0x18 "RGX_CR_MIN_NON_CRITICAL_MEM1_LATENCY_MH_TAG_0,RGX_CR_MIN_NON_CRITICAL_MEM1_LATENCY_MH_TAG_0" hexmask.long 0x18 6.--31. 1. "Reserved_6,Reserved_6" newline hexmask.long.byte 0x18 0.--5. 1. "VALUE,The mh_tag value of min read latency cycles for non critical tag" line.long 0x1C "RGX_CR_MIN_NON_CRITICAL_MEM1_LATENCY_MH_TAG_1,RGX_CR_MIN_NON_CRITICAL_MEM1_LATENCY_MH_TAG_1" hexmask.long 0x1C 0.--31. 1. "Reserved_6,Reserved_6" line.long 0x20 "RGX_CR_MAX_NON_CRITICAL_MEM1_LATENCY_MH_TAG_0,RGX_CR_MAX_NON_CRITICAL_MEM1_LATENCY_MH_TAG_0" hexmask.long 0x20 6.--31. 1. "Reserved_6,Reserved_6" newline hexmask.long.byte 0x20 0.--5. 1. "VALUE,The mh_tag value of max read latency cycles for non critical tag" line.long 0x24 "RGX_CR_MAX_NON_CRITICAL_MEM1_LATENCY_MH_TAG_1,RGX_CR_MAX_NON_CRITICAL_MEM1_LATENCY_MH_TAG_1" hexmask.long 0x24 0.--31. 1. "Reserved_6,Reserved_6" group.long 0x7600++0x27 line.long 0x0 "RGX_CR_TA_PERF_0,RGX_CR_TA_PERF_0" hexmask.long 0x0 5.--31. 1. "Reserved_5,Reserved_5" newline bitfld.long 0x0 4. "CLR_3,clear counter 3" "0,1" newline bitfld.long 0x0 3. "CLR_2,clear counter 2" "0,1" newline bitfld.long 0x0 2. "CLR_1,clear counter 1" "0,1" newline bitfld.long 0x0 1. "CLR_0,clear counter 0" "0,1" newline bitfld.long 0x0 0. "CTRL_ENABLE,enables the perf bus counters" "0,1" line.long 0x4 "RGX_CR_TA_PERF_1,RGX_CR_TA_PERF_1" hexmask.long 0x4 0.--31. 1. "Reserved_5,Reserved_5" line.long 0x8 "RGX_CR_TA_PERF_SELECT0_0,RGX_CR_TA_PERF_SELECT0_0" hexmask.long.word 0x8 22.--31. 1. "Reserved_22,Reserved_22" newline bitfld.long 0x8 21. "MODE,reduction mode 0: bitwise increments 1: unsigned count increment" "bitwise increments,unsigned count increment" newline hexmask.long.byte 0x8 16.--20. 1. "GROUP_SELECT,group select see full PERF documentation for signals in each group" newline hexmask.long.word 0x8 0.--15. 1. "BIT_SELECT,bit mask for enabled signals in group" line.long 0xC "RGX_CR_TA_PERF_SELECT0_1,RGX_CR_TA_PERF_SELECT0_1" hexmask.long 0xC 0.--31. 1. "Reserved_22,Reserved_22" line.long 0x10 "RGX_CR_TA_PERF_SELECT1_0,RGX_CR_TA_PERF_SELECT1_0" hexmask.long.word 0x10 22.--31. 1. "Reserved_22,Reserved_22" newline bitfld.long 0x10 21. "MODE,reduction mode 0: bitwise increments 1: unsigned count increment" "bitwise increments,unsigned count increment" newline hexmask.long.byte 0x10 16.--20. 1. "GROUP_SELECT,group select see full PERF documentation for signals in each group" newline hexmask.long.word 0x10 0.--15. 1. "BIT_SELECT,bit mask for enabled signals in group" line.long 0x14 "RGX_CR_TA_PERF_SELECT1_1,RGX_CR_TA_PERF_SELECT1_1" hexmask.long 0x14 0.--31. 1. "Reserved_22,Reserved_22" line.long 0x18 "RGX_CR_TA_PERF_SELECT2_0,RGX_CR_TA_PERF_SELECT2_0" hexmask.long.word 0x18 22.--31. 1. "Reserved_22,Reserved_22" newline bitfld.long 0x18 21. "MODE,reduction mode 0: bitwise increments 1: unsigned count increment" "bitwise increments,unsigned count increment" newline hexmask.long.byte 0x18 16.--20. 1. "GROUP_SELECT,group select see full PERF documentation for signals in each group" newline hexmask.long.word 0x18 0.--15. 1. "BIT_SELECT,bit mask for enabled signals in group" line.long 0x1C "RGX_CR_TA_PERF_SELECT2_1,RGX_CR_TA_PERF_SELECT2_1" hexmask.long 0x1C 0.--31. 1. "Reserved_22,Reserved_22" line.long 0x20 "RGX_CR_TA_PERF_SELECT3_0,RGX_CR_TA_PERF_SELECT3_0" hexmask.long.word 0x20 22.--31. 1. "Reserved_22,Reserved_22" newline bitfld.long 0x20 21. "MODE,reduction mode 0: bitwise increments 1: unsigned count increment" "bitwise increments,unsigned count increment" newline hexmask.long.byte 0x20 16.--20. 1. "GROUP_SELECT,group select see full PERF documentation for signals in each group" newline hexmask.long.word 0x20 0.--15. 1. "BIT_SELECT,bit mask for enabled signals in group" line.long 0x24 "RGX_CR_TA_PERF_SELECT3_1,RGX_CR_TA_PERF_SELECT3_1" hexmask.long 0x24 0.--31. 1. "Reserved_22,Reserved_22" repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) rgroup.long ($2+0x7648)++0x3 line.long 0x0 "RGX_CR_TA_PERF_SELECTED_BITS_$1,RGX_CR_TA_PERF_SELECTED_BITS_0" hexmask.long.word 0x0 16.--31. 1. "REG1,persent bus signals counter 1" newline hexmask.long.word 0x0 0.--15. 1. "REG0,present bus signals counter 0" repeat.end repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) rgroup.long ($2+0x7650)++0x3 line.long 0x0 "RGX_CR_TA_PERF_COUNTER_0_$1,RGX_CR_TA_PERF_COUNTER_0_0" hexmask.long 0x0 0.--31. 1. "REG,counter a0" repeat.end repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) rgroup.long ($2+0x7658)++0x3 line.long 0x0 "RGX_CR_TA_PERF_COUNTER_1_$1,RGX_CR_TA_PERF_COUNTER_1_0" hexmask.long 0x0 0.--31. 1. "REG,counter a0" repeat.end repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) rgroup.long ($2+0x7660)++0x3 line.long 0x0 "RGX_CR_TA_PERF_COUNTER_2_$1,RGX_CR_TA_PERF_COUNTER_2_0" hexmask.long 0x0 0.--31. 1. "REG,counter a0" repeat.end repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) rgroup.long ($2+0x7668)++0x3 line.long 0x0 "RGX_CR_TA_PERF_COUNTER_3_$1,RGX_CR_TA_PERF_COUNTER_3_0" hexmask.long 0x0 0.--31. 1. "REG,counter a0" repeat.end group.long 0x7700++0x27 line.long 0x0 "RGX_CR_RASTERISATION_PERF_0,RGX_CR_RASTERISATION_PERF_0" hexmask.long 0x0 5.--31. 1. "Reserved_5,Reserved_5" newline bitfld.long 0x0 4. "CLR_3,clear counter 3" "0,1" newline bitfld.long 0x0 3. "CLR_2,clear counter 2" "0,1" newline bitfld.long 0x0 2. "CLR_1,clear counter 1" "0,1" newline bitfld.long 0x0 1. "CLR_0,clear counter 0" "0,1" newline bitfld.long 0x0 0. "CTRL_ENABLE,enables the perf bus counters" "0,1" line.long 0x4 "RGX_CR_RASTERISATION_PERF_1,RGX_CR_RASTERISATION_PERF_1" hexmask.long 0x4 0.--31. 1. "Reserved_5,Reserved_5" line.long 0x8 "RGX_CR_RASTERISATION_PERF_SELECT0_0,RGX_CR_RASTERISATION_PERF_SELECT0_0" hexmask.long.word 0x8 22.--31. 1. "Reserved_22,Reserved_22" newline bitfld.long 0x8 21. "MODE,reduction mode 0: bitwise increments 1: unsigned count increment" "bitwise increments,unsigned count increment" newline hexmask.long.byte 0x8 16.--20. 1. "GROUP_SELECT,group select see full PERF documenrasterisationtion for signals in each group" newline hexmask.long.word 0x8 0.--15. 1. "BIT_SELECT,bit mask for enabled signals in group" line.long 0xC "RGX_CR_RASTERISATION_PERF_SELECT0_1,RGX_CR_RASTERISATION_PERF_SELECT0_1" hexmask.long 0xC 0.--31. 1. "Reserved_22,Reserved_22" line.long 0x10 "RGX_CR_RASTERISATION_PERF_SELECT1_0,RGX_CR_RASTERISATION_PERF_SELECT1_0" hexmask.long.word 0x10 22.--31. 1. "Reserved_22,Reserved_22" newline bitfld.long 0x10 21. "MODE,reduction mode 0: bitwise increments 1: unsigned count increment" "bitwise increments,unsigned count increment" newline hexmask.long.byte 0x10 16.--20. 1. "GROUP_SELECT,group select see full PERF documenrasterisationtion for signals in each group" newline hexmask.long.word 0x10 0.--15. 1. "BIT_SELECT,bit mask for enabled signals in group" line.long 0x14 "RGX_CR_RASTERISATION_PERF_SELECT1_1,RGX_CR_RASTERISATION_PERF_SELECT1_1" hexmask.long 0x14 0.--31. 1. "Reserved_22,Reserved_22" line.long 0x18 "RGX_CR_RASTERISATION_PERF_SELECT2_0,RGX_CR_RASTERISATION_PERF_SELECT2_0" hexmask.long.word 0x18 22.--31. 1. "Reserved_22,Reserved_22" newline bitfld.long 0x18 21. "MODE,reduction mode 0: bitwise increments 1: unsigned count increment" "bitwise increments,unsigned count increment" newline hexmask.long.byte 0x18 16.--20. 1. "GROUP_SELECT,group select see full PERF documenrasterisationtion for signals in each group" newline hexmask.long.word 0x18 0.--15. 1. "BIT_SELECT,bit mask for enabled signals in group" line.long 0x1C "RGX_CR_RASTERISATION_PERF_SELECT2_1,RGX_CR_RASTERISATION_PERF_SELECT2_1" hexmask.long 0x1C 0.--31. 1. "Reserved_22,Reserved_22" line.long 0x20 "RGX_CR_RASTERISATION_PERF_SELECT3_0,RGX_CR_RASTERISATION_PERF_SELECT3_0" hexmask.long.word 0x20 22.--31. 1. "Reserved_22,Reserved_22" newline bitfld.long 0x20 21. "MODE,reduction mode 0: bitwise increments 1: unsigned count increment" "bitwise increments,unsigned count increment" newline hexmask.long.byte 0x20 16.--20. 1. "GROUP_SELECT,group select see full PERF documenrasterisationtion for signals in each group" newline hexmask.long.word 0x20 0.--15. 1. "BIT_SELECT,bit mask for enabled signals in group" line.long 0x24 "RGX_CR_RASTERISATION_PERF_SELECT3_1,RGX_CR_RASTERISATION_PERF_SELECT3_1" hexmask.long 0x24 0.--31. 1. "Reserved_22,Reserved_22" repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) rgroup.long ($2+0x7748)++0x3 line.long 0x0 "RGX_CR_RASTERISATION_PERF_SELECTED_BITS_$1,RGX_CR_RASTERISATION_PERF_SELECTED_BITS_0" hexmask.long.word 0x0 16.--31. 1. "REG1,persent bus signals counter 1" newline hexmask.long.word 0x0 0.--15. 1. "REG0,present bus signals counter 0" repeat.end repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) rgroup.long ($2+0x7750)++0x3 line.long 0x0 "RGX_CR_RASTERISATION_PERF_COUNTER_0_$1,RGX_CR_RASTERISATION_PERF_COUNTER_0_0" hexmask.long 0x0 0.--31. 1. "REG,counter a0" repeat.end repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) rgroup.long ($2+0x7758)++0x3 line.long 0x0 "RGX_CR_RASTERISATION_PERF_COUNTER_1_$1,RGX_CR_RASTERISATION_PERF_COUNTER_1_0" hexmask.long 0x0 0.--31. 1. "REG,counter a0" repeat.end repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) rgroup.long ($2+0x7760)++0x3 line.long 0x0 "RGX_CR_RASTERISATION_PERF_COUNTER_2_$1,RGX_CR_RASTERISATION_PERF_COUNTER_2_0" hexmask.long 0x0 0.--31. 1. "REG,counter a0" repeat.end repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) rgroup.long ($2+0x7768)++0x3 line.long 0x0 "RGX_CR_RASTERISATION_PERF_COUNTER_3_$1,RGX_CR_RASTERISATION_PERF_COUNTER_3_0" hexmask.long 0x0 0.--31. 1. "REG,counter a0" repeat.end group.long 0x7800++0x27 line.long 0x0 "RGX_CR_HUB_BIFPMCACHE_PERF_0,RGX_CR_HUB_BIFPMCACHE_PERF_0" hexmask.long 0x0 5.--31. 1. "Reserved_5,Reserved_5" newline bitfld.long 0x0 4. "CLR_3,clear counter 3" "0,1" newline bitfld.long 0x0 3. "CLR_2,clear counter 2" "0,1" newline bitfld.long 0x0 2. "CLR_1,clear counter 1" "0,1" newline bitfld.long 0x0 1. "CLR_0,clear counter 0" "0,1" newline bitfld.long 0x0 0. "CTRL_ENABLE,enables the perf bus counters" "0,1" line.long 0x4 "RGX_CR_HUB_BIFPMCACHE_PERF_1,RGX_CR_HUB_BIFPMCACHE_PERF_1" hexmask.long 0x4 0.--31. 1. "Reserved_5,Reserved_5" line.long 0x8 "RGX_CR_HUB_BIFPMCACHE_PERF_SELECT0_0,RGX_CR_HUB_BIFPMCACHE_PERF_SELECT0_0" hexmask.long.word 0x8 22.--31. 1. "Reserved_22,Reserved_22" newline bitfld.long 0x8 21. "MODE,reduction mode 0: bitwise increments 1: unsigned count increment" "bitwise increments,unsigned count increment" newline hexmask.long.byte 0x8 16.--20. 1. "GROUP_SELECT,group select see full PERF documenhub_bifpmcachetion for signals in each group" newline hexmask.long.word 0x8 0.--15. 1. "BIT_SELECT,bit mask for enabled signals in group" line.long 0xC "RGX_CR_HUB_BIFPMCACHE_PERF_SELECT0_1,RGX_CR_HUB_BIFPMCACHE_PERF_SELECT0_1" hexmask.long 0xC 0.--31. 1. "Reserved_22,Reserved_22" line.long 0x10 "RGX_CR_HUB_BIFPMCACHE_PERF_SELECT1_0,RGX_CR_HUB_BIFPMCACHE_PERF_SELECT1_0" hexmask.long.word 0x10 22.--31. 1. "Reserved_22,Reserved_22" newline bitfld.long 0x10 21. "MODE,reduction mode 0: bitwise increments 1: unsigned count increment" "bitwise increments,unsigned count increment" newline hexmask.long.byte 0x10 16.--20. 1. "GROUP_SELECT,group select see full PERF documenhub_bifpmcachetion for signals in each group" newline hexmask.long.word 0x10 0.--15. 1. "BIT_SELECT,bit mask for enabled signals in group" line.long 0x14 "RGX_CR_HUB_BIFPMCACHE_PERF_SELECT1_1,RGX_CR_HUB_BIFPMCACHE_PERF_SELECT1_1" hexmask.long 0x14 0.--31. 1. "Reserved_22,Reserved_22" line.long 0x18 "RGX_CR_HUB_BIFPMCACHE_PERF_SELECT2_0,RGX_CR_HUB_BIFPMCACHE_PERF_SELECT2_0" hexmask.long.word 0x18 22.--31. 1. "Reserved_22,Reserved_22" newline bitfld.long 0x18 21. "MODE,reduction mode 0: bitwise increments 1: unsigned count increment" "bitwise increments,unsigned count increment" newline hexmask.long.byte 0x18 16.--20. 1. "GROUP_SELECT,group select see full PERF documenhub_bifpmcachetion for signals in each group" newline hexmask.long.word 0x18 0.--15. 1. "BIT_SELECT,bit mask for enabled signals in group" line.long 0x1C "RGX_CR_HUB_BIFPMCACHE_PERF_SELECT2_1,RGX_CR_HUB_BIFPMCACHE_PERF_SELECT2_1" hexmask.long 0x1C 0.--31. 1. "Reserved_22,Reserved_22" line.long 0x20 "RGX_CR_HUB_BIFPMCACHE_PERF_SELECT3_0,RGX_CR_HUB_BIFPMCACHE_PERF_SELECT3_0" hexmask.long.word 0x20 22.--31. 1. "Reserved_22,Reserved_22" newline bitfld.long 0x20 21. "MODE,reduction mode 0: bitwise increments 1: unsigned count increment" "bitwise increments,unsigned count increment" newline hexmask.long.byte 0x20 16.--20. 1. "GROUP_SELECT,group select see full PERF documenhub_bifpmcachetion for signals in each group" newline hexmask.long.word 0x20 0.--15. 1. "BIT_SELECT,bit mask for enabled signals in group" line.long 0x24 "RGX_CR_HUB_BIFPMCACHE_PERF_SELECT3_1,RGX_CR_HUB_BIFPMCACHE_PERF_SELECT3_1" hexmask.long 0x24 0.--31. 1. "Reserved_22,Reserved_22" repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) rgroup.long ($2+0x7848)++0x3 line.long 0x0 "RGX_CR_HUB_BIFPMCACHE_PERF_SELECTED_BITS_$1,RGX_CR_HUB_BIFPMCACHE_PERF_SELECTED_BITS_0" hexmask.long.word 0x0 16.--31. 1. "REG1,persent bus signals counter 1" newline hexmask.long.word 0x0 0.--15. 1. "REG0,present bus signals counter 0" repeat.end repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) rgroup.long ($2+0x7850)++0x3 line.long 0x0 "RGX_CR_HUB_BIFPMCACHE_PERF_COUNTER_0_$1,RGX_CR_HUB_BIFPMCACHE_PERF_COUNTER_0_0" hexmask.long 0x0 0.--31. 1. "REG,counter a0" repeat.end repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) rgroup.long ($2+0x7858)++0x3 line.long 0x0 "RGX_CR_HUB_BIFPMCACHE_PERF_COUNTER_1_$1,RGX_CR_HUB_BIFPMCACHE_PERF_COUNTER_1_0" hexmask.long 0x0 0.--31. 1. "REG,counter a0" repeat.end repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) rgroup.long ($2+0x7860)++0x3 line.long 0x0 "RGX_CR_HUB_BIFPMCACHE_PERF_COUNTER_2_$1,RGX_CR_HUB_BIFPMCACHE_PERF_COUNTER_2_0" hexmask.long 0x0 0.--31. 1. "REG,counter a0" repeat.end repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) rgroup.long ($2+0x7868)++0x3 line.long 0x0 "RGX_CR_HUB_BIFPMCACHE_PERF_COUNTER_3_$1,RGX_CR_HUB_BIFPMCACHE_PERF_COUNTER_3_0" hexmask.long 0x0 0.--31. 1. "REG,counter a0" repeat.end group.long 0x7900++0x27 line.long 0x0 "RGX_CR_TPU_MCU_L0_PERF_0,RGX_CR_TPU_MCU_L0_PERF_0" hexmask.long 0x0 5.--31. 1. "Reserved_5,Reserved_5" newline bitfld.long 0x0 4. "CLR_3,clear counter 3" "0,1" newline bitfld.long 0x0 3. "CLR_2,clear counter 2" "0,1" newline bitfld.long 0x0 2. "CLR_1,clear counter 1" "0,1" newline bitfld.long 0x0 1. "CLR_0,clear counter 0" "0,1" newline bitfld.long 0x0 0. "CTRL_ENABLE,enables the perf bus counters" "0,1" line.long 0x4 "RGX_CR_TPU_MCU_L0_PERF_1,RGX_CR_TPU_MCU_L0_PERF_1" hexmask.long 0x4 0.--31. 1. "Reserved_5,Reserved_5" line.long 0x8 "RGX_CR_TPU_MCU_L0_PERF_SELECT0_0,RGX_CR_TPU_MCU_L0_PERF_SELECT0_0" hexmask.long.word 0x8 22.--31. 1. "Reserved_22,Reserved_22" newline bitfld.long 0x8 21. "MODE,reduction mode 0: bitwise increments 1: unsigned count increment" "bitwise increments,unsigned count increment" newline hexmask.long.byte 0x8 16.--20. 1. "GROUP_SELECT,group select see full PERF documentation for signals in each group" newline hexmask.long.word 0x8 0.--15. 1. "BIT_SELECT,bit mask for enabled signals in group" line.long 0xC "RGX_CR_TPU_MCU_L0_PERF_SELECT0_1,RGX_CR_TPU_MCU_L0_PERF_SELECT0_1" bitfld.long 0xC 30.--31. "Reserved_62,Reserved_62" "0,1,2,3" newline hexmask.long.word 0xC 16.--29. 1. "BATCH_MAX,this is the min batch number which will be counted in this group" newline bitfld.long 0xC 14.--15. "Reserved_46,Reserved_46" "0,1,2,3" newline hexmask.long.word 0xC 0.--13. 1. "BATCH_MIN,this is the min batch number which will be counted in this group" line.long 0x10 "RGX_CR_TPU_MCU_L0_PERF_SELECT1_0,RGX_CR_TPU_MCU_L0_PERF_SELECT1_0" hexmask.long.word 0x10 22.--31. 1. "Reserved_22,Reserved_22" newline bitfld.long 0x10 21. "MODE,reduction mode 0: bitwise increments 1: unsigned count increment" "bitwise increments,unsigned count increment" newline hexmask.long.byte 0x10 16.--20. 1. "GROUP_SELECT,group select see full PERF documentation for signals in each group" newline hexmask.long.word 0x10 0.--15. 1. "BIT_SELECT,bit mask for enabled signals in group" line.long 0x14 "RGX_CR_TPU_MCU_L0_PERF_SELECT1_1,RGX_CR_TPU_MCU_L0_PERF_SELECT1_1" bitfld.long 0x14 30.--31. "Reserved_62,Reserved_62" "0,1,2,3" newline hexmask.long.word 0x14 16.--29. 1. "BATCH_MAX,this is the min batch number which will be counted in this group" newline bitfld.long 0x14 14.--15. "Reserved_46,Reserved_46" "0,1,2,3" newline hexmask.long.word 0x14 0.--13. 1. "BATCH_MIN,this is the min batch number which will be counted in this group" line.long 0x18 "RGX_CR_TPU_MCU_L0_PERF_SELECT2_0,RGX_CR_TPU_MCU_L0_PERF_SELECT2_0" hexmask.long.word 0x18 22.--31. 1. "Reserved_22,Reserved_22" newline bitfld.long 0x18 21. "MODE,reduction mode 0: bitwise increments 1: unsigned count increment" "bitwise increments,unsigned count increment" newline hexmask.long.byte 0x18 16.--20. 1. "GROUP_SELECT,group select see full PERF documentation for signals in each group" newline hexmask.long.word 0x18 0.--15. 1. "BIT_SELECT,bit mask for enabled signals in group" line.long 0x1C "RGX_CR_TPU_MCU_L0_PERF_SELECT2_1,RGX_CR_TPU_MCU_L0_PERF_SELECT2_1" bitfld.long 0x1C 30.--31. "Reserved_62,Reserved_62" "0,1,2,3" newline hexmask.long.word 0x1C 16.--29. 1. "BATCH_MAX,this is the min batch number which will be counted in this group" newline bitfld.long 0x1C 14.--15. "Reserved_46,Reserved_46" "0,1,2,3" newline hexmask.long.word 0x1C 0.--13. 1. "BATCH_MIN,this is the min batch number which will be counted in this group" line.long 0x20 "RGX_CR_TPU_MCU_L0_PERF_SELECT3_0,RGX_CR_TPU_MCU_L0_PERF_SELECT3_0" hexmask.long.word 0x20 22.--31. 1. "Reserved_22,Reserved_22" newline bitfld.long 0x20 21. "MODE,reduction mode 0: bitwise increments 1: unsigned count increment" "bitwise increments,unsigned count increment" newline hexmask.long.byte 0x20 16.--20. 1. "GROUP_SELECT,group select see full PERF documentation for signals in each group" newline hexmask.long.word 0x20 0.--15. 1. "BIT_SELECT,bit mask for enabled signals in group" line.long 0x24 "RGX_CR_TPU_MCU_L0_PERF_SELECT3_1,RGX_CR_TPU_MCU_L0_PERF_SELECT3_1" bitfld.long 0x24 30.--31. "Reserved_62,Reserved_62" "0,1,2,3" newline hexmask.long.word 0x24 16.--29. 1. "BATCH_MAX,this is the min batch number which will be counted in this group" newline bitfld.long 0x24 14.--15. "Reserved_46,Reserved_46" "0,1,2,3" newline hexmask.long.word 0x24 0.--13. 1. "BATCH_MIN,this is the min batch number which will be counted in this group" repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) rgroup.long ($2+0x7948)++0x3 line.long 0x0 "RGX_CR_TPU_MCU_L0_PERF_SELECTED_BITS_$1,RGX_CR_TPU_MCU_L0_PERF_SELECTED_BITS_0" hexmask.long.word 0x0 16.--31. 1. "REG1,persent bus signals counter 1" newline hexmask.long.word 0x0 0.--15. 1. "REG0,present bus signals counter 0" repeat.end repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) rgroup.long ($2+0x7950)++0x3 line.long 0x0 "RGX_CR_TPU_MCU_L0_PERF_COUNTER_0_$1,RGX_CR_TPU_MCU_L0_PERF_COUNTER_0_0" hexmask.long 0x0 0.--31. 1. "REG,counter a0" repeat.end repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) rgroup.long ($2+0x7958)++0x3 line.long 0x0 "RGX_CR_TPU_MCU_L0_PERF_COUNTER_1_$1,RGX_CR_TPU_MCU_L0_PERF_COUNTER_1_0" hexmask.long 0x0 0.--31. 1. "REG,counter a0" repeat.end repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) rgroup.long ($2+0x7960)++0x3 line.long 0x0 "RGX_CR_TPU_MCU_L0_PERF_COUNTER_2_$1,RGX_CR_TPU_MCU_L0_PERF_COUNTER_2_0" hexmask.long 0x0 0.--31. 1. "REG,counter a0" repeat.end repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) rgroup.long ($2+0x7968)++0x3 line.long 0x0 "RGX_CR_TPU_MCU_L0_PERF_COUNTER_3_$1,RGX_CR_TPU_MCU_L0_PERF_COUNTER_3_0" hexmask.long 0x0 0.--31. 1. "REG,counter a0" repeat.end group.long 0x8020++0x7 line.long 0x0 "RGX_CR_USC_TPU_LOW_PRECISION_ENABLE_0,Enable signal to use low precision across USC and TPU (TAG) in coordinates. gradients and LOD value (calculated or supplied)" hexmask.long 0x0 1.--31. 1. "Reserved_1,Reserved_1" newline bitfld.long 0x0 0. "VALUE,VALUE" "0,1" line.long 0x4 "RGX_CR_USC_TPU_LOW_PRECISION_ENABLE_1,Enable signal to use low precision across USC and TPU (TAG) in coordinates. gradients and LOD value (calculated or supplied)" hexmask.long 0x4 0.--31. 1. "Reserved_1,Reserved_1" group.long 0x8100++0x27 line.long 0x0 "RGX_CR_USC_PERF_0,RGX_CR_USC_PERF_0" hexmask.long 0x0 5.--31. 1. "Reserved_5,Reserved_5" newline bitfld.long 0x0 4. "CLR_3,clear counter 3" "0,1" newline bitfld.long 0x0 3. "CLR_2,clear counter 2" "0,1" newline bitfld.long 0x0 2. "CLR_1,clear counter 1" "0,1" newline bitfld.long 0x0 1. "CLR_0,clear counter 0" "0,1" newline bitfld.long 0x0 0. "CTRL_ENABLE,enables the perf bus counters" "0,1" line.long 0x4 "RGX_CR_USC_PERF_1,RGX_CR_USC_PERF_1" hexmask.long 0x4 0.--31. 1. "Reserved_5,Reserved_5" line.long 0x8 "RGX_CR_USC_PERF_SELECT0_0,RGX_CR_USC_PERF_SELECT0_0" hexmask.long.word 0x8 22.--31. 1. "Reserved_22,Reserved_22" newline bitfld.long 0x8 21. "MODE,reduction mode 0: bitwise increments 1: unsigned count increment" "bitwise increments,unsigned count increment" newline hexmask.long.byte 0x8 16.--20. 1. "GROUP_SELECT,group select see full PERF documenusction for signals in each group" newline hexmask.long.word 0x8 0.--15. 1. "BIT_SELECT,bit mask for enabled signals in group" line.long 0xC "RGX_CR_USC_PERF_SELECT0_1,RGX_CR_USC_PERF_SELECT0_1" bitfld.long 0xC 30.--31. "Reserved_62,Reserved_62" "0,1,2,3" newline hexmask.long.word 0xC 16.--29. 1. "BATCH_MAX,this is the min batch number which will be counted in this group" newline bitfld.long 0xC 14.--15. "Reserved_46,Reserved_46" "0,1,2,3" newline hexmask.long.word 0xC 0.--13. 1. "BATCH_MIN,this is the min batch number which will be counted in this group" line.long 0x10 "RGX_CR_USC_PERF_SELECT1_0,RGX_CR_USC_PERF_SELECT1_0" hexmask.long.word 0x10 22.--31. 1. "Reserved_22,Reserved_22" newline bitfld.long 0x10 21. "MODE,reduction mode 0: bitwise increments 1: unsigned count increment" "bitwise increments,unsigned count increment" newline hexmask.long.byte 0x10 16.--20. 1. "GROUP_SELECT,group select see full PERF documenusction for signals in each group" newline hexmask.long.word 0x10 0.--15. 1. "BIT_SELECT,bit mask for enabled signals in group" line.long 0x14 "RGX_CR_USC_PERF_SELECT1_1,RGX_CR_USC_PERF_SELECT1_1" bitfld.long 0x14 30.--31. "Reserved_62,Reserved_62" "0,1,2,3" newline hexmask.long.word 0x14 16.--29. 1. "BATCH_MAX,this is the min batch number which will be counted in this group" newline bitfld.long 0x14 14.--15. "Reserved_46,Reserved_46" "0,1,2,3" newline hexmask.long.word 0x14 0.--13. 1. "BATCH_MIN,this is the min batch number which will be counted in this group" line.long 0x18 "RGX_CR_USC_PERF_SELECT2_0,RGX_CR_USC_PERF_SELECT2_0" hexmask.long.word 0x18 22.--31. 1. "Reserved_22,Reserved_22" newline bitfld.long 0x18 21. "MODE,reduction mode 0: bitwise increments 1: unsigned count increment" "bitwise increments,unsigned count increment" newline hexmask.long.byte 0x18 16.--20. 1. "GROUP_SELECT,group select see full PERF documenusction for signals in each group" newline hexmask.long.word 0x18 0.--15. 1. "BIT_SELECT,bit mask for enabled signals in group" line.long 0x1C "RGX_CR_USC_PERF_SELECT2_1,RGX_CR_USC_PERF_SELECT2_1" bitfld.long 0x1C 30.--31. "Reserved_62,Reserved_62" "0,1,2,3" newline hexmask.long.word 0x1C 16.--29. 1. "BATCH_MAX,this is the min batch number which will be counted in this group" newline bitfld.long 0x1C 14.--15. "Reserved_46,Reserved_46" "0,1,2,3" newline hexmask.long.word 0x1C 0.--13. 1. "BATCH_MIN,this is the min batch number which will be counted in this group" line.long 0x20 "RGX_CR_USC_PERF_SELECT3_0,RGX_CR_USC_PERF_SELECT3_0" hexmask.long.word 0x20 22.--31. 1. "Reserved_22,Reserved_22" newline bitfld.long 0x20 21. "MODE,reduction mode 0: bitwise increments 1: unsigned count increment" "bitwise increments,unsigned count increment" newline hexmask.long.byte 0x20 16.--20. 1. "GROUP_SELECT,group select see full PERF documenusction for signals in each group" newline hexmask.long.word 0x20 0.--15. 1. "BIT_SELECT,bit mask for enabled signals in group" line.long 0x24 "RGX_CR_USC_PERF_SELECT3_1,RGX_CR_USC_PERF_SELECT3_1" bitfld.long 0x24 30.--31. "Reserved_62,Reserved_62" "0,1,2,3" newline hexmask.long.word 0x24 16.--29. 1. "BATCH_MAX,this is the min batch number which will be counted in this group" newline bitfld.long 0x24 14.--15. "Reserved_46,Reserved_46" "0,1,2,3" newline hexmask.long.word 0x24 0.--13. 1. "BATCH_MIN,this is the min batch number which will be counted in this group" repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) rgroup.long ($2+0x8148)++0x3 line.long 0x0 "RGX_CR_USC_PERF_SELECTED_BITS_$1,RGX_CR_USC_PERF_SELECTED_BITS_0" hexmask.long.word 0x0 16.--31. 1. "REG1,persent bus signals counter 1" newline hexmask.long.word 0x0 0.--15. 1. "REG0,present bus signals counter 0" repeat.end repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) rgroup.long ($2+0x8150)++0x3 line.long 0x0 "RGX_CR_USC_PERF_COUNTER_0_$1,RGX_CR_USC_PERF_COUNTER_0_0" hexmask.long 0x0 0.--31. 1. "REG,counter a0" repeat.end repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) rgroup.long ($2+0x8158)++0x3 line.long 0x0 "RGX_CR_USC_PERF_COUNTER_1_$1,RGX_CR_USC_PERF_COUNTER_1_0" hexmask.long 0x0 0.--31. 1. "REG,counter a0" repeat.end repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) rgroup.long ($2+0x8160)++0x3 line.long 0x0 "RGX_CR_USC_PERF_COUNTER_2_$1,RGX_CR_USC_PERF_COUNTER_2_0" hexmask.long 0x0 0.--31. 1. "REG,counter a0" repeat.end repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) rgroup.long ($2+0x8168)++0x3 line.long 0x0 "RGX_CR_USC_PERF_COUNTER_3_$1,RGX_CR_USC_PERF_COUNTER_3_0" hexmask.long 0x0 0.--31. 1. "REG,counter a0" repeat.end group.long 0x8478++0x1F line.long 0x0 "RGX_CR_PBE_PERF_0,RGX_CR_PBE_PERF_0" hexmask.long 0x0 5.--31. 1. "Reserved_5,Reserved_5" newline bitfld.long 0x0 4. "CLR_3,clear counter 3" "0,1" newline bitfld.long 0x0 3. "CLR_2,clear counter 2" "0,1" newline bitfld.long 0x0 2. "CLR_1,clear counter 1" "0,1" newline bitfld.long 0x0 1. "CLR_0,clear counter 0" "0,1" newline bitfld.long 0x0 0. "CTRL_ENABLE,enables the perf bus counters" "0,1" line.long 0x4 "RGX_CR_PBE_PERF_1,RGX_CR_PBE_PERF_1" hexmask.long 0x4 0.--31. 1. "Reserved_5,Reserved_5" line.long 0x8 "RGX_CR_PBE_PERF_SELECT0_0,RGX_CR_PBE_PERF_SELECT0_0" hexmask.long.word 0x8 22.--31. 1. "Reserved_22,Reserved_22" newline bitfld.long 0x8 21. "MODE,reduction mode 0: bitwise increments 1: unsigned count increment" "bitwise increments,unsigned count increment" newline hexmask.long.byte 0x8 16.--20. 1. "GROUP_SELECT,group select see full PERF documentation for signals in each group" newline hexmask.long.word 0x8 0.--15. 1. "BIT_SELECT,bit mask for enabled signals in group" line.long 0xC "RGX_CR_PBE_PERF_SELECT0_1,RGX_CR_PBE_PERF_SELECT0_1" bitfld.long 0xC 30.--31. "Reserved_62,Reserved_62" "0,1,2,3" newline hexmask.long.word 0xC 16.--29. 1. "BATCH_MAX,this is the max batch number which will be counted in this group" newline bitfld.long 0xC 14.--15. "Reserved_46,Reserved_46" "0,1,2,3" newline hexmask.long.word 0xC 0.--13. 1. "BATCH_MIN,this is the min batch number which will be counted in this group" line.long 0x10 "RGX_CR_PBE_PERF_SELECT1_0,RGX_CR_PBE_PERF_SELECT1_0" hexmask.long.word 0x10 22.--31. 1. "Reserved_22,Reserved_22" newline bitfld.long 0x10 21. "MODE,reduction mode 0: bitwise increments 1: unsigned count increment" "bitwise increments,unsigned count increment" newline hexmask.long.byte 0x10 16.--20. 1. "GROUP_SELECT,group select see full PERF documentation for signals in each group" newline hexmask.long.word 0x10 0.--15. 1. "BIT_SELECT,bit mask for enabled signals in group" line.long 0x14 "RGX_CR_PBE_PERF_SELECT1_1,RGX_CR_PBE_PERF_SELECT1_1" bitfld.long 0x14 30.--31. "Reserved_62,Reserved_62" "0,1,2,3" newline hexmask.long.word 0x14 16.--29. 1. "BATCH_MAX,this is the max batch number which will be counted in this group" newline bitfld.long 0x14 14.--15. "Reserved_46,Reserved_46" "0,1,2,3" newline hexmask.long.word 0x14 0.--13. 1. "BATCH_MIN,this is the min batch number which will be counted in this group" line.long 0x18 "RGX_CR_PBE_PERF_SELECT2_0,RGX_CR_PBE_PERF_SELECT2_0" hexmask.long.word 0x18 22.--31. 1. "Reserved_22,Reserved_22" newline bitfld.long 0x18 21. "MODE,reduction mode 0: bitwise increments 1: unsigned count increment" "bitwise increments,unsigned count increment" newline hexmask.long.byte 0x18 16.--20. 1. "GROUP_SELECT,group select see full PERF documentation for signals in each group" newline hexmask.long.word 0x18 0.--15. 1. "BIT_SELECT,bit mask for enabled signals in group" line.long 0x1C "RGX_CR_PBE_PERF_SELECT2_1,RGX_CR_PBE_PERF_SELECT2_1" bitfld.long 0x1C 30.--31. "Reserved_62,Reserved_62" "0,1,2,3" newline hexmask.long.word 0x1C 16.--29. 1. "BATCH_MAX,this is the max batch number which will be counted in this group" newline bitfld.long 0x1C 14.--15. "Reserved_46,Reserved_46" "0,1,2,3" newline hexmask.long.word 0x1C 0.--13. 1. "BATCH_MIN,this is the min batch number which will be counted in this group" group.long 0x84A0++0x7 line.long 0x0 "RGX_CR_PBE_PERF_SELECT3_0,RGX_CR_PBE_PERF_SELECT3_0" hexmask.long.word 0x0 22.--31. 1. "Reserved_22,Reserved_22" newline bitfld.long 0x0 21. "MODE,reduction mode 0: bitwise increments 1: unsigned count increment" "bitwise increments,unsigned count increment" newline hexmask.long.byte 0x0 16.--20. 1. "GROUP_SELECT,group select see full PERF documentation for signals in each group" newline hexmask.long.word 0x0 0.--15. 1. "BIT_SELECT,bit mask for enabled signals in group" line.long 0x4 "RGX_CR_PBE_PERF_SELECT3_1,RGX_CR_PBE_PERF_SELECT3_1" bitfld.long 0x4 30.--31. "Reserved_62,Reserved_62" "0,1,2,3" newline hexmask.long.word 0x4 16.--29. 1. "BATCH_MAX,this is the max batch number which will be counted in this group" newline bitfld.long 0x4 14.--15. "Reserved_46,Reserved_46" "0,1,2,3" newline hexmask.long.word 0x4 0.--13. 1. "BATCH_MIN,this is the min batch number which will be counted in this group" repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) rgroup.long ($2+0x84A8)++0x3 line.long 0x0 "RGX_CR_PBE_PERF_SELECTED_BITS_$1,RGX_CR_PBE_PERF_SELECTED_BITS_0" hexmask.long.word 0x0 16.--31. 1. "REG1,persent bus signals counter 1" newline hexmask.long.word 0x0 0.--15. 1. "REG0,present bus signals counter 0" repeat.end repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) rgroup.long ($2+0x84B0)++0x3 line.long 0x0 "RGX_CR_PBE_PERF_COUNTER_0_$1,RGX_CR_PBE_PERF_COUNTER_0_0" hexmask.long 0x0 0.--31. 1. "REG,counter a0" repeat.end repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) rgroup.long ($2+0x84B8)++0x3 line.long 0x0 "RGX_CR_PBE_PERF_COUNTER_1_$1,RGX_CR_PBE_PERF_COUNTER_1_0" hexmask.long 0x0 0.--31. 1. "REG,counter a0" repeat.end repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) rgroup.long ($2+0x84C0)++0x3 line.long 0x0 "RGX_CR_PBE_PERF_COUNTER_2_$1,RGX_CR_PBE_PERF_COUNTER_2_0" hexmask.long 0x0 0.--31. 1. "REG,counter a0" repeat.end repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) rgroup.long ($2+0x84C8)++0x3 line.long 0x0 "RGX_CR_PBE_PERF_COUNTER_3_$1,RGX_CR_PBE_PERF_COUNTER_3_0" hexmask.long 0x0 0.--31. 1. "REG,counter a0" repeat.end group.long 0xA000++0x7 line.long 0x0 "RGX_CR_BIF_TRUST_0,Define Requestors/Data Masters which are Trusted/Untrusted and enable/disable the Memory Bus Security feature within the Core When enabled the GPU will emit the security signals out through the external memory interface." hexmask.long.word 0x0 17.--31. 1. "Reserved_17,Reserved_17" newline bitfld.long 0x0 16. "ENABLE,Enable Security feature: 0x1 = Enabled 0x0 = Disabled" "Disabled,Enabled" newline hexmask.long.byte 0x0 9.--15. 1. "DM_TRUSTED,Mask of bits which defines which of the remaining Data Masters are trusted: 0x1 = Trusted 0x0 = Untrusted" newline bitfld.long 0x0 8. "OTHER_COMPUTE_DM_TRUSTED,Defines whether other accesses with the Compute DM are trusted: 0x1 = Trusted 0x0 = Untrusted" "Untrusted,Trusted" newline bitfld.long 0x0 7. "MCU_COMPUTE_DM_TRUSTED,Defines whether MCU accesses with the Compute DM are trusted: 0x1 = Trusted 0x0 = Untrusted" "Untrusted,Trusted" newline bitfld.long 0x0 6. "PBE_COMPUTE_DM_TRUSTED,Defines whether PBE accesses with the Compute DM are trusted: 0x1 = Trusted 0x0 = Untrusted" "Untrusted,Trusted" newline bitfld.long 0x0 5. "OTHER_PIXEL_DM_TRUSTED,Defines whether other accesses with the Pixel DM are trusted: 0x1 = Trusted 0x0 = Untrusted" "Untrusted,Trusted" newline bitfld.long 0x0 4. "MCU_PIXEL_DM_TRUSTED,Defines whether MCU accesses with the Pixel DM are trusted: 0x1 = Trusted 0x0 = Untrusted" "Untrusted,Trusted" newline bitfld.long 0x0 3. "PBE_PIXEL_DM_TRUSTED,Defines whether PBE accesses with the Pixel DM are trusted: 0x1 = Trusted 0x0 = Untrusted" "Untrusted,Trusted" newline bitfld.long 0x0 2. "OTHER_VERTEX_DM_TRUSTED,Defines whether other accesses with the Vertex DM are trusted: 0x1 = Trusted 0x0 = Untrusted" "Untrusted,Trusted" newline bitfld.long 0x0 1. "MCU_VERTEX_DM_TRUSTED,Defines whether MCU accesses with the Vertex DM are trusted: 0x1 = Trusted 0x0 = Untrusted" "Untrusted,Trusted" newline bitfld.long 0x0 0. "PBE_VERTEX_DM_TRUSTED,Defines whether PBE accesses with the Vertex DM are trusted: 0x1 = Trusted 0x0 = Untrusted" "Untrusted,Trusted" line.long 0x4 "RGX_CR_BIF_TRUST_1,Define Requestors/Data Masters which are Trusted/Untrusted and enable/disable the Memory Bus Security feature within the Core When enabled the GPU will emit the security signals out through the external memory interface." hexmask.long 0x4 0.--31. 1. "Reserved_17,Reserved_17" group.long 0xA100++0x7 line.long 0x0 "RGX_CR_SYS_BUS_SECURE_0,Setting this register secures the IMG Configuration Registers from the System Bus. In secure mode all registers have read access only by default. When secure mode is being set. the register must be read back to confirm that the.." hexmask.long 0x0 1.--31. 1. "Reserved_1,Reserved_1" newline bitfld.long 0x0 0. "ENABLE,

0 = No System Bus Security

1 = System Bus Restricted

" "No System Bus Security

1 = System Bus..,?" line.long 0x4 "RGX_CR_SYS_BUS_SECURE_1,Setting this register secures the IMG Configuration Registers from the System Bus. In secure mode all registers have read access only by default. When secure mode is being set. the register must be read back to confirm that the.." hexmask.long 0x4 0.--31. 1. "Reserved_1,Reserved_1" repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) group.long ($2+0xA500)++0x3 line.long 0x0 "RGX_CR_FB_CDC_V3_$1,Framebuffer constant detection configuraton registers" hexmask.long.byte 0x0 24.--31. 1. "FBC_FBDC_UV_VAL1,video pixel format constant value" newline hexmask.long.byte 0x0 16.--23. 1. "FBC_FBDC_Y_VAL1,video pixel format constant value" newline hexmask.long.byte 0x0 8.--15. 1. "FBC_FBDC_UV_VAL0,video pixel format constant value" newline hexmask.long.byte 0x0 0.--7. 1. "FBC_FBDC_Y_VAL0,video pixel format constant value" repeat.end group.long 0xA508++0x7 line.long 0x0 "RGX_CR_FBC_FBDC_CR_FILTER_0,FBCDC corrupt tile filter register" hexmask.long 0x0 5.--31. 1. "Reserved_5,Reserved_5" newline hexmask.long.byte 0x0 1.--4. 1. "CLEAR,Clear corrupt tile filter status 1 bit per requester" newline bitfld.long 0x0 0. "ENABLE,Enable corrupt tile filter" "0,1" line.long 0x4 "RGX_CR_FBC_FBDC_CR_FILTER_1,FBCDC corrupt tile filter register" hexmask.long 0x4 0.--31. 1. "Reserved_5,Reserved_5" rgroup.long 0xA510++0x7 line.long 0x0 "RGX_CR_FBC_FBDC_CR_FILTER_STATUS_0,FBCDC corrupt tile filter register" hexmask.long 0x0 4.--31. 1. "Reserved_4,Reserved_4" newline hexmask.long.byte 0x0 0.--3. 1. "FBC_FBDC_CR_FILTER_STATUS,Status of corrupt tile filter 1 bit per requester" line.long 0x4 "RGX_CR_FBC_FBDC_CR_FILTER_STATUS_1,FBCDC corrupt tile filter register" hexmask.long 0x4 0.--31. 1. "Reserved_4,Reserved_4" group.long 0xA518++0x7 line.long 0x0 "RGX_CR_FBC_FBDC_CR_MODE_V3_1_0,Enable FBC_FBDC mode V3_1 for FBC_FBDC textures" hexmask.long 0x0 1.--31. 1. "Reserved_1,Reserved_1" newline bitfld.long 0x0 0. "EN,Enable FBC_FBDC mode V3_1 for FBCDC formats defaults to V3" "0,1" line.long 0x4 "RGX_CR_FBC_FBDC_CR_MODE_V3_1_1,Enable FBC_FBDC mode V3_1 for FBC_FBDC textures" hexmask.long 0x4 0.--31. 1. "Reserved_1,Reserved_1" repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) group.long ($2+0xA520)++0x3 line.long 0x0 "RGX_CR_FBCDC_CC_$1,RGX_CR_FBCDC_CC_0" hexmask.long.byte 0x0 24.--31. 1. "CH3_VAL0,Constant colour detected value for channel 3." newline hexmask.long.byte 0x0 16.--23. 1. "CH2_VAL0,Constant colour detected value for channel 2." newline hexmask.long.byte 0x0 8.--15. 1. "CH1_VAL0,Constant colour detected value for channel 1." newline hexmask.long.byte 0x0 0.--7. 1. "CH0_VAL0,Constant colour detected value for channel 0." repeat.end repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) group.long ($2+0xA528)++0x3 line.long 0x0 "RGX_CR_FBCDC_CC_YUV_$1,RGX_CR_FBCDC_CC_YUV_0" hexmask.long.byte 0x0 26.--31. 1. "Reserved_26,Reserved_26" newline hexmask.long.word 0x0 16.--25. 1. "UV_VAL0,Constant colour detected value uv-plane." newline hexmask.long.byte 0x0 10.--15. 1. "Reserved_10,Reserved_10" newline hexmask.long.word 0x0 0.--9. 1. "Y_VAL0,Constant colour detected value y-plane." repeat.end group.long 0xB000++0x7 line.long 0x0 "RGX_CR_PIPELINE_STATS_ENABLE_0,This register globally enables per DM pipeline statistics counters. Set this register to '1' to allow pipeline statistics counters to increment. Set this register to '0' to inhibit pipeline statistics from incrementing." hexmask.long.word 0x0 17.--31. 1. "Reserved_17,Reserved_17" newline bitfld.long 0x0 16. "COMPUTE,COMPUTE" "0,1" newline hexmask.long.byte 0x0 9.--15. 1. "Reserved_9,Reserved_9" newline bitfld.long 0x0 8. "_3D,_3D" "0,1" newline hexmask.long.byte 0x0 1.--7. 1. "Reserved_1,Reserved_1" newline bitfld.long 0x0 0. "TA,TA" "0,1" line.long 0x4 "RGX_CR_PIPELINE_STATS_ENABLE_1,This register globally enables per DM pipeline statistics counters. Set this register to '1' to allow pipeline statistics counters to increment. Set this register to '0' to inhibit pipeline statistics from incrementing." hexmask.long 0x4 0.--31. 1. "Reserved_17,Reserved_17" wgroup.long 0xB008++0x7 line.long 0x0 "RGX_CR_PIPELINE_STATS_CLEAR_0,Writing '1' to fields of this register resets the pipeline statistics counters per DM The pipeline statistics should normally be cleared before each TA. 3D or Compute kick" hexmask.long.word 0x0 17.--31. 1. "Reserved_17,Reserved_17" newline bitfld.long 0x0 16. "COMPUTE,COMPUTE" "0,1" newline hexmask.long.byte 0x0 9.--15. 1. "Reserved_9,Reserved_9" newline bitfld.long 0x0 8. "_3D,_3D" "0,1" newline hexmask.long.byte 0x0 1.--7. 1. "Reserved_1,Reserved_1" newline bitfld.long 0x0 0. "TA,TA" "0,1" line.long 0x4 "RGX_CR_PIPELINE_STATS_CLEAR_1,Writing '1' to fields of this register resets the pipeline statistics counters per DM The pipeline statistics should normally be cleared before each TA. 3D or Compute kick" hexmask.long 0x4 0.--31. 1. "Reserved_17,Reserved_17" repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) rgroup.long ($2+0xB010)++0x3 line.long 0x0 "RGX_CR_PIPELINE_STATS_IA_VERTICES_$1,Number of vertices the Input Assembly stage generated (not subtracting any caching)" hexmask.long 0x0 0.--31. 1. "COUNT,COUNT" repeat.end repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) rgroup.long ($2+0xB018)++0x3 line.long 0x0 "RGX_CR_PIPELINE_STATS_IA_PRIMITIVES_$1,Number of primitives the Input Assembly stage generated" hexmask.long 0x0 0.--31. 1. "COUNT,COUNT" repeat.end repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) rgroup.long ($2+0xB020)++0x3 line.long 0x0 "RGX_CR_PIPELINE_STATS_VS_INVOCATIONS_$1,Number of times the Vertex Shader is executed" hexmask.long 0x0 0.--31. 1. "COUNT,COUNT" repeat.end repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) rgroup.long ($2+0xB038)++0x3 line.long 0x0 "RGX_CR_PIPELINE_STATS_GS_INVOCATIONS_$1,Number of times the Geometry Shader is executed" hexmask.long 0x0 0.--31. 1. "COUNT,COUNT" repeat.end repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) rgroup.long ($2+0xB040)++0x3 line.long 0x0 "RGX_CR_PIPELINE_STATS_GS_PRIMITIVES_$1,Number of primitives the Geometry Shader generated" hexmask.long 0x0 0.--31. 1. "COUNT,COUNT" repeat.end repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) rgroup.long ($2+0xB048)++0x3 line.long 0x0 "RGX_CR_PIPELINE_STATS_C_INVOCATIONS_$1,Number of times the Clipper is executed" hexmask.long 0x0 0.--31. 1. "COUNT,COUNT" repeat.end repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) rgroup.long ($2+0xB050)++0x3 line.long 0x0 "RGX_CR_PIPELINE_STATS_C_PRIMITIVES_$1,Number of primitives the Clipper generated" hexmask.long 0x0 0.--31. 1. "COUNT,COUNT" repeat.end repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) rgroup.long ($2+0xB058)++0x3 line.long 0x0 "RGX_CR_PIPELINE_STATS_PS_INVOCATIONS_$1,Number of times the Pixel Shader is executed" hexmask.long 0x0 0.--31. 1. "COUNT,COUNT" repeat.end repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) rgroup.long ($2+0xB060)++0x3 line.long 0x0 "RGX_CR_PIPELINE_STATS_CS_INVOCATIONS_$1,Number of times the Compute Shader is executed" hexmask.long 0x0 0.--31. 1. "COUNT,COUNT" repeat.end rgroup.long 0xE000++0x7 line.long 0x0 "RGX_CR_CACHE_CFI_EVENT_0,Global Flush and Invalidation Pending bits for all Texture and Data Caches in the design. The bits are set high after a Flush/Invalidate is requested and will be set low again as each cache in turn completes processing. therefore.." hexmask.long.word 0x0 16.--31. 1. "MCU_L0_PENDING,1 Indicates there is a pending global CFI operation on the specified MCU L0 cache (there can be up to 16 MCU L0 caches depending on the number of clusters)" newline hexmask.long.word 0x0 0.--15. 1. "MADD_PENDING,1 Indicates there is a pending global CFI operation on the specified MADD Texture cache (there can be up to 16 MADD caches depending on the number of clusters)" line.long 0x4 "RGX_CR_CACHE_CFI_EVENT_1,Global Flush and Invalidation Pending bits for all Texture and Data Caches in the design. The bits are set high after a Flush/Invalidate is requested and will be set low again as each cache in turn completes processing. therefore.." hexmask.long.tbyte 0x4 9.--31. 1. "Reserved_41,Reserved_41" newline bitfld.long 0x4 8. "SLC_PENDING,1 Indicates there is a pending global CFI operation on the SLC cache" "0,1" newline hexmask.long.byte 0x4 0.--7. 1. "MCU_L1_PENDING,1 Indicates there is a pending global CFI operation on the specified MCU L1 cache (there can be up to 8 MCU L1 caches depending on the number of clusters)" group.long 0xE138++0x7 line.long 0x0 "RGX_CR_MMU_CTRL_INVAL_0,MMU invalidation control registers" hexmask.long.tbyte 0x0 12.--31. 1. "Reserved_12,Reserved_12" newline bitfld.long 0x0 11. "ALL_CONTEXTS,When ALL_CONTEXTS is set all context ids get invalidated (global invalidation)" "0,1" newline hexmask.long.byte 0x0 3.--10. 1. "CONTEXT,When ALL_CONTEXTS is not set this field specifies the context id to be invalidated (per-context invalidation)" newline bitfld.long 0x0 2. "PC,Invalidates PC PD & PT" "0,1" newline bitfld.long 0x0 1. "PD,Invalidates PD & PT" "0,1" newline bitfld.long 0x0 0. "PT,Invalidates PT" "0,1" line.long 0x4 "RGX_CR_MMU_CTRL_INVAL_1,MMU invalidation control registers" hexmask.long 0x4 0.--31. 1. "Reserved_12,Reserved_12" repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) rgroup.long ($2+0xF100)++0x3 line.long 0x0 "RGX_CR_FB_CDC_PWR_NUM_$1,Power Monitoring registers for the FBCDC" hexmask.long 0x0 0.--31. 1. "FBDC,Number of accesses to the FBDC per clock" repeat.end repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) rgroup.long ($2+0xF108)++0x3 line.long 0x0 "RGX_CR_FB_CDC_PWR_NUM_MCU_$1,Power Monitoring registers for the FBCDC" hexmask.long 0x0 0.--31. 1. "FBTC,Number of accesses to the MCU FBTC per clock" repeat.end rgroup.long 0xF220++0xF line.long 0x0 "RGX_CR_BIF_BLACKPEARL_RTN_FIFO_WORD_COUNT_0,Blackpearl BIF return FIFO word count" hexmask.long.tbyte 0x0 9.--31. 1. "Reserved_9,Reserved_9" newline hexmask.long.word 0x0 0.--8. 1. "COUNTER,COUNTER" line.long 0x4 "RGX_CR_BIF_BLACKPEARL_RTN_FIFO_WORD_COUNT_1,Blackpearl BIF return FIFO word count" hexmask.long 0x4 0.--31. 1. "Reserved_9,Reserved_9" line.long 0x8 "RGX_CR_BIF_JONES_RTN_FIFO_WORD_COUNT_0,Jones BIF return FIFO word count" hexmask.long.tbyte 0x8 9.--31. 1. "Reserved_9,Reserved_9" newline hexmask.long.word 0x8 0.--8. 1. "COUNTER,COUNTER" line.long 0xC "RGX_CR_BIF_JONES_RTN_FIFO_WORD_COUNT_1,Jones BIF return FIFO word count" hexmask.long 0xC 0.--31. 1. "Reserved_9,Reserved_9" group.long 0xF258++0x7 line.long 0x0 "RGX_CR_TDM_GRIDOFFSET_0,Sample position grid offset for use when MSAA/ODAA is DISABLED DX (0.0.0.0) OpenGL (0.5.0.5) Acts as the 9th multisample position when MSAA is ENABLED." hexmask.long.tbyte 0x0 8.--31. 1. "Reserved_8,Reserved_8" newline hexmask.long.byte 0x0 4.--7. 1. "GRID_Y,Unsigned sub-pixel offset" newline hexmask.long.byte 0x0 0.--3. 1. "GRID_X,Unsigned sub-pixel offset" line.long 0x4 "RGX_CR_TDM_GRIDOFFSET_1,Sample position grid offset for use when MSAA/ODAA is DISABLED DX (0.0.0.0) OpenGL (0.5.0.5) Acts as the 9th multisample position when MSAA is ENABLED." hexmask.long 0x4 0.--31. 1. "Reserved_8,Reserved_8" repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) group.long ($2+0xF260)++0x3 line.long 0x0 "RGX_CR_TDM_MULTISAMPLECTL_$1,Sample position grid offset for use in 2x. 4x. 8xMSAA and ODAA modes." hexmask.long.byte 0x0 28.--31. 1. "MSAA_Y3,Unsigned sub-pixel offset for the 4th multisample Y position" newline hexmask.long.byte 0x0 24.--27. 1. "MSAA_X3,Unsigned sub-pixel offset for the 4th multisample X position" newline hexmask.long.byte 0x0 20.--23. 1. "MSAA_Y2,Unsigned sub-pixel offset for the 3rd multisample Y position" newline hexmask.long.byte 0x0 16.--19. 1. "MSAA_X2,Unsigned sub-pixel offset for the 3rd multisample X position" newline hexmask.long.byte 0x0 12.--15. 1. "MSAA_Y1,Unsigned sub-pixel offset for the 2nd multisample Y position" newline hexmask.long.byte 0x0 8.--11. 1. "MSAA_X1,Unsigned sub-pixel offset for the 2nd multisample X position" newline hexmask.long.byte 0x0 4.--7. 1. "MSAA_Y0,Unsigned sub-pixel offset for the 1st multisample Y position" newline hexmask.long.byte 0x0 0.--3. 1. "MSAA_X0,Unsigned sub-pixel offset for the 1st multisample X position" repeat.end group.long 0xF268++0x7 line.long 0x0 "RGX_CR_USC_CODE_BASE_2D_0,RGX_CR_USC_CODE_BASE_2D_0" hexmask.long 0x0 6.--31. 1. "ADDR,2D Data Master Code Base Register bits" newline hexmask.long.byte 0x0 0.--5. 1. "Reserved_0,Reserved_0" line.long 0x4 "RGX_CR_USC_CODE_BASE_2D_1,RGX_CR_USC_CODE_BASE_2D_1" hexmask.long.tbyte 0x4 8.--31. 1. "Reserved_40,Reserved_40" newline hexmask.long.byte 0x4 0.--7. 1. "ADDR,2D Data Master Code Base Register bits" group.long 0x10B00++0x7 line.long 0x0 "RGX_CR_MTS_SCHEDULE1_0,This register allows firmware tasks to be scheduled on the META (Garten) core." hexmask.long.tbyte 0x0 9.--31. 1. "Reserved_9,Reserved_9" newline bitfld.long 0x0 8. "HOST,Host Interrupte kick" "0,1" newline bitfld.long 0x0 6.--7. "PRIORITY,DataMaster Priority" "0,1,2,3" newline bitfld.long 0x0 5. "CONTEXT,CONTEXT" "0,1" newline bitfld.long 0x0 4. "TASK,TASK" "0,1" newline hexmask.long.byte 0x0 0.--3. 1. "DM,DataMaster Type" line.long 0x4 "RGX_CR_MTS_SCHEDULE1_1,This register allows firmware tasks to be scheduled on the META (Garten) core." hexmask.long 0x4 0.--31. 1. "Reserved_9,Reserved_9" rgroup.long 0x10B98++0x17 line.long 0x0 "RGX_CR_MTS_INTCTX1_0,This register contains the sideband data for the MTS internal interrupt context registers" bitfld.long 0x0 30.--31. "Reserved_30,Reserved_30" "0,1,2,3" newline hexmask.long.byte 0x0 22.--29. 1. "DM_HOST_SCHEDULE,A 1 bit counter per DM for host requests" newline hexmask.long.byte 0x0 16.--21. 1. "Reserved_16,Reserved_16" newline hexmask.long.byte 0x0 8.--15. 1. "DM_TIMER_SCHEDULE,A 1 bit counter per DM for timer requests" newline hexmask.long.byte 0x0 0.--7. 1. "DM_INTERRUPT_SCHEDULE,A 1 bit counter per DM for interrupt requests" line.long 0x4 "RGX_CR_MTS_INTCTX1_1,This register contains the sideband data for the MTS internal interrupt context registers" hexmask.long 0x4 0.--31. 1. "Reserved_30,Reserved_30" line.long 0x8 "RGX_CR_MTS_BGCTX1_0,This register contains the sideband data for the MTS internal background context registers" hexmask.long.tbyte 0x8 8.--31. 1. "Reserved_8,Reserved_8" newline hexmask.long.byte 0x8 0.--7. 1. "DM_NONCOUNTED_SCHEDULE,A 1 bit counter per DM for non-counted background request" line.long 0xC "RGX_CR_MTS_BGCTX1_1,This register contains the sideband data for the MTS internal background context registers" hexmask.long 0xC 0.--31. 1. "Reserved_8,Reserved_8" line.long 0x10 "RGX_CR_MTS_BGCTX_COUNTED_SCHEDULE1_0,This register contains the sideband data for the MTS internal counted background context counters" hexmask.long.byte 0x10 24.--31. 1. "DM3,A 8 bit counter for DM3" newline hexmask.long.byte 0x10 16.--23. 1. "DM2,A 8 bit counter for DM2" newline hexmask.long.byte 0x10 8.--15. 1. "DM1,A 8 bit counter for DM1" newline hexmask.long.byte 0x10 0.--7. 1. "DM0,A 8 bit counter for DM0" line.long 0x14 "RGX_CR_MTS_BGCTX_COUNTED_SCHEDULE1_1,This register contains the sideband data for the MTS internal counted background context counters" hexmask.long.word 0x14 16.--31. 1. "Reserved_48,Reserved_48" newline hexmask.long.byte 0x14 8.--15. 1. "DM5,A 8 bit counter for DM5" newline hexmask.long.byte 0x14 0.--7. 1. "DM4,A 8 bit counter for DM4" rgroup.long 0x10BD8++0x7 line.long 0x0 "RGX_CR_IRQ_OS1_EVENT_STATUS_0,This register indicates the source of a per-OS host interrupt. This register is set by the firmware and cleared by the host." hexmask.long 0x0 1.--31. 1. "Reserved_1,Reserved_1" newline bitfld.long 0x0 0. "SOURCE,SOURCE" "0,1" line.long 0x4 "RGX_CR_IRQ_OS1_EVENT_STATUS_1,This register indicates the source of a per-OS host interrupt. This register is set by the firmware and cleared by the host." hexmask.long 0x4 0.--31. 1. "Reserved_1,Reserved_1" group.long 0x10BE8++0x7 line.long 0x0 "RGX_CR_IRQ_OS1_EVENT_CLEAR_0,This register clears a per-OS host interrupt." hexmask.long 0x0 1.--31. 1. "Reserved_1,Reserved_1" newline bitfld.long 0x0 0. "SOURCE,SOURCE" "0,1" line.long 0x4 "RGX_CR_IRQ_OS1_EVENT_CLEAR_1,This register clears a per-OS host interrupt." hexmask.long 0x4 0.--31. 1. "Reserved_1,Reserved_1" group.long 0x20B00++0x7 line.long 0x0 "RGX_CR_MTS_SCHEDULE2_0,This register allows firmware tasks to be scheduled on the META (Garten) core." hexmask.long.tbyte 0x0 9.--31. 1. "Reserved_9,Reserved_9" newline bitfld.long 0x0 8. "HOST,Host Interrupte kick" "0,1" newline bitfld.long 0x0 6.--7. "PRIORITY,DataMaster Priority" "0,1,2,3" newline bitfld.long 0x0 5. "CONTEXT,CONTEXT" "0,1" newline bitfld.long 0x0 4. "TASK,TASK" "0,1" newline hexmask.long.byte 0x0 0.--3. 1. "DM,DataMaster Type" line.long 0x4 "RGX_CR_MTS_SCHEDULE2_1,This register allows firmware tasks to be scheduled on the META (Garten) core." hexmask.long 0x4 0.--31. 1. "Reserved_9,Reserved_9" rgroup.long 0x20B98++0x17 line.long 0x0 "RGX_CR_MTS_INTCTX2_0,This register contains the sideband data for the MTS internal interrupt context registers" bitfld.long 0x0 30.--31. "Reserved_30,Reserved_30" "0,1,2,3" newline hexmask.long.byte 0x0 22.--29. 1. "DM_HOST_SCHEDULE,A 1 bit counter per DM for host requests" newline hexmask.long.byte 0x0 16.--21. 1. "Reserved_16,Reserved_16" newline hexmask.long.byte 0x0 8.--15. 1. "DM_TIMER_SCHEDULE,A 1 bit counter per DM for timer requests" newline hexmask.long.byte 0x0 0.--7. 1. "DM_INTERRUPT_SCHEDULE,A 1 bit counter per DM for interrupt requests" line.long 0x4 "RGX_CR_MTS_INTCTX2_1,This register contains the sideband data for the MTS internal interrupt context registers" hexmask.long 0x4 0.--31. 1. "Reserved_30,Reserved_30" line.long 0x8 "RGX_CR_MTS_BGCTX2_0,This register contains the sideband data for the MTS internal background context registers" hexmask.long.tbyte 0x8 8.--31. 1. "Reserved_8,Reserved_8" newline hexmask.long.byte 0x8 0.--7. 1. "DM_NONCOUNTED_SCHEDULE,A 1 bit counter per DM for non-counted background request" line.long 0xC "RGX_CR_MTS_BGCTX2_1,This register contains the sideband data for the MTS internal background context registers" hexmask.long 0xC 0.--31. 1. "Reserved_8,Reserved_8" line.long 0x10 "RGX_CR_MTS_BGCTX_COUNTED_SCHEDULE2_0,This register contains the sideband data for the MTS internal counted background context counters" hexmask.long.byte 0x10 24.--31. 1. "DM3,A 8 bit counter for DM3" newline hexmask.long.byte 0x10 16.--23. 1. "DM2,A 8 bit counter for DM2" newline hexmask.long.byte 0x10 8.--15. 1. "DM1,A 8 bit counter for DM1" newline hexmask.long.byte 0x10 0.--7. 1. "DM0,A 8 bit counter for DM0" line.long 0x14 "RGX_CR_MTS_BGCTX_COUNTED_SCHEDULE2_1,This register contains the sideband data for the MTS internal counted background context counters" hexmask.long.word 0x14 16.--31. 1. "Reserved_48,Reserved_48" newline hexmask.long.byte 0x14 8.--15. 1. "DM5,A 8 bit counter for DM5" newline hexmask.long.byte 0x14 0.--7. 1. "DM4,A 8 bit counter for DM4" rgroup.long 0x20BD8++0x7 line.long 0x0 "RGX_CR_IRQ_OS2_EVENT_STATUS_0,This register indicates the source of a per-OS host interrupt. This register is set by the firmware and cleared by the host." hexmask.long 0x0 1.--31. 1. "Reserved_1,Reserved_1" newline bitfld.long 0x0 0. "SOURCE,SOURCE" "0,1" line.long 0x4 "RGX_CR_IRQ_OS2_EVENT_STATUS_1,This register indicates the source of a per-OS host interrupt. This register is set by the firmware and cleared by the host." hexmask.long 0x4 0.--31. 1. "Reserved_1,Reserved_1" group.long 0x20BE8++0x7 line.long 0x0 "RGX_CR_IRQ_OS2_EVENT_CLEAR_0,This register clears a per-OS host interrupt." hexmask.long 0x0 1.--31. 1. "Reserved_1,Reserved_1" newline bitfld.long 0x0 0. "SOURCE,SOURCE" "0,1" line.long 0x4 "RGX_CR_IRQ_OS2_EVENT_CLEAR_1,This register clears a per-OS host interrupt." hexmask.long 0x4 0.--31. 1. "Reserved_1,Reserved_1" group.long 0x30B00++0x7 line.long 0x0 "RGX_CR_MTS_SCHEDULE3_0,This register allows firmware tasks to be scheduled on the META (Garten) core." hexmask.long.tbyte 0x0 9.--31. 1. "Reserved_9,Reserved_9" newline bitfld.long 0x0 8. "HOST,Host Interrupte kick" "0,1" newline bitfld.long 0x0 6.--7. "PRIORITY,DataMaster Priority" "0,1,2,3" newline bitfld.long 0x0 5. "CONTEXT,CONTEXT" "0,1" newline bitfld.long 0x0 4. "TASK,TASK" "0,1" newline hexmask.long.byte 0x0 0.--3. 1. "DM,DataMaster Type" line.long 0x4 "RGX_CR_MTS_SCHEDULE3_1,This register allows firmware tasks to be scheduled on the META (Garten) core." hexmask.long 0x4 0.--31. 1. "Reserved_9,Reserved_9" rgroup.long 0x30B98++0x17 line.long 0x0 "RGX_CR_MTS_INTCTX3_0,This register contains the sideband data for the MTS internal interrupt context registers" bitfld.long 0x0 30.--31. "Reserved_30,Reserved_30" "0,1,2,3" newline hexmask.long.byte 0x0 22.--29. 1. "DM_HOST_SCHEDULE,A 1 bit counter per DM for host requests" newline hexmask.long.byte 0x0 16.--21. 1. "Reserved_16,Reserved_16" newline hexmask.long.byte 0x0 8.--15. 1. "DM_TIMER_SCHEDULE,A 1 bit counter per DM for timer requests" newline hexmask.long.byte 0x0 0.--7. 1. "DM_INTERRUPT_SCHEDULE,A 1 bit counter per DM for interrupt requests" line.long 0x4 "RGX_CR_MTS_INTCTX3_1,This register contains the sideband data for the MTS internal interrupt context registers" hexmask.long 0x4 0.--31. 1. "Reserved_30,Reserved_30" line.long 0x8 "RGX_CR_MTS_BGCTX3_0,This register contains the sideband data for the MTS internal background context registers" hexmask.long.tbyte 0x8 8.--31. 1. "Reserved_8,Reserved_8" newline hexmask.long.byte 0x8 0.--7. 1. "DM_NONCOUNTED_SCHEDULE,A 1 bit counter per DM for non-counted background request" line.long 0xC "RGX_CR_MTS_BGCTX3_1,This register contains the sideband data for the MTS internal background context registers" hexmask.long 0xC 0.--31. 1. "Reserved_8,Reserved_8" line.long 0x10 "RGX_CR_MTS_BGCTX_COUNTED_SCHEDULE3_0,This register contains the sideband data for the MTS internal counted background context counters" hexmask.long.byte 0x10 24.--31. 1. "DM3,A 8 bit counter for DM3" newline hexmask.long.byte 0x10 16.--23. 1. "DM2,A 8 bit counter for DM2" newline hexmask.long.byte 0x10 8.--15. 1. "DM1,A 8 bit counter for DM1" newline hexmask.long.byte 0x10 0.--7. 1. "DM0,A 8 bit counter for DM0" line.long 0x14 "RGX_CR_MTS_BGCTX_COUNTED_SCHEDULE3_1,This register contains the sideband data for the MTS internal counted background context counters" hexmask.long.word 0x14 16.--31. 1. "Reserved_48,Reserved_48" newline hexmask.long.byte 0x14 8.--15. 1. "DM5,A 8 bit counter for DM5" newline hexmask.long.byte 0x14 0.--7. 1. "DM4,A 8 bit counter for DM4" rgroup.long 0x30BD8++0x7 line.long 0x0 "RGX_CR_IRQ_OS3_EVENT_STATUS_0,This register indicates the source of a per-OS host interrupt. This register is set by the firmware and cleared by the host." hexmask.long 0x0 1.--31. 1. "Reserved_1,Reserved_1" newline bitfld.long 0x0 0. "SOURCE,SOURCE" "0,1" line.long 0x4 "RGX_CR_IRQ_OS3_EVENT_STATUS_1,This register indicates the source of a per-OS host interrupt. This register is set by the firmware and cleared by the host." hexmask.long 0x4 0.--31. 1. "Reserved_1,Reserved_1" group.long 0x30BE8++0x7 line.long 0x0 "RGX_CR_IRQ_OS3_EVENT_CLEAR_0,This register clears a per-OS host interrupt." hexmask.long 0x0 1.--31. 1. "Reserved_1,Reserved_1" newline bitfld.long 0x0 0. "SOURCE,SOURCE" "0,1" line.long 0x4 "RGX_CR_IRQ_OS3_EVENT_CLEAR_1,This register clears a per-OS host interrupt." hexmask.long 0x4 0.--31. 1. "Reserved_1,Reserved_1" group.long 0x40B00++0x7 line.long 0x0 "RGX_CR_MTS_SCHEDULE4_0,This register allows firmware tasks to be scheduled on the META (Garten) core." hexmask.long.tbyte 0x0 9.--31. 1. "Reserved_9,Reserved_9" newline bitfld.long 0x0 8. "HOST,Host Interrupte kick" "0,1" newline bitfld.long 0x0 6.--7. "PRIORITY,DataMaster Priority" "0,1,2,3" newline bitfld.long 0x0 5. "CONTEXT,CONTEXT" "0,1" newline bitfld.long 0x0 4. "TASK,TASK" "0,1" newline hexmask.long.byte 0x0 0.--3. 1. "DM,DataMaster Type" line.long 0x4 "RGX_CR_MTS_SCHEDULE4_1,This register allows firmware tasks to be scheduled on the META (Garten) core." hexmask.long 0x4 0.--31. 1. "Reserved_9,Reserved_9" rgroup.long 0x40B98++0x17 line.long 0x0 "RGX_CR_MTS_INTCTX4_0,This register contains the sideband data for the MTS internal interrupt context registers" bitfld.long 0x0 30.--31. "Reserved_30,Reserved_30" "0,1,2,3" newline hexmask.long.byte 0x0 22.--29. 1. "DM_HOST_SCHEDULE,A 1 bit counter per DM for host requests" newline hexmask.long.byte 0x0 16.--21. 1. "Reserved_16,Reserved_16" newline hexmask.long.byte 0x0 8.--15. 1. "DM_TIMER_SCHEDULE,A 1 bit counter per DM for timer requests" newline hexmask.long.byte 0x0 0.--7. 1. "DM_INTERRUPT_SCHEDULE,A 1 bit counter per DM for interrupt requests" line.long 0x4 "RGX_CR_MTS_INTCTX4_1,This register contains the sideband data for the MTS internal interrupt context registers" hexmask.long 0x4 0.--31. 1. "Reserved_30,Reserved_30" line.long 0x8 "RGX_CR_MTS_BGCTX4_0,This register contains the sideband data for the MTS internal background context registers" hexmask.long.tbyte 0x8 8.--31. 1. "Reserved_8,Reserved_8" newline hexmask.long.byte 0x8 0.--7. 1. "DM_NONCOUNTED_SCHEDULE,A 1 bit counter per DM for non-counted background request" line.long 0xC "RGX_CR_MTS_BGCTX4_1,This register contains the sideband data for the MTS internal background context registers" hexmask.long 0xC 0.--31. 1. "Reserved_8,Reserved_8" line.long 0x10 "RGX_CR_MTS_BGCTX_COUNTED_SCHEDULE4_0,This register contains the sideband data for the MTS internal counted background context counters" hexmask.long.byte 0x10 24.--31. 1. "DM3,A 8 bit counter for DM3" newline hexmask.long.byte 0x10 16.--23. 1. "DM2,A 8 bit counter for DM2" newline hexmask.long.byte 0x10 8.--15. 1. "DM1,A 8 bit counter for DM1" newline hexmask.long.byte 0x10 0.--7. 1. "DM0,A 8 bit counter for DM0" line.long 0x14 "RGX_CR_MTS_BGCTX_COUNTED_SCHEDULE4_1,This register contains the sideband data for the MTS internal counted background context counters" hexmask.long.word 0x14 16.--31. 1. "Reserved_48,Reserved_48" newline hexmask.long.byte 0x14 8.--15. 1. "DM5,A 8 bit counter for DM5" newline hexmask.long.byte 0x14 0.--7. 1. "DM4,A 8 bit counter for DM4" rgroup.long 0x40BD8++0x7 line.long 0x0 "RGX_CR_IRQ_OS4_EVENT_STATUS_0,This register indicates the source of a per-OS host interrupt. This register is set by the firmware and cleared by the host." hexmask.long 0x0 1.--31. 1. "Reserved_1,Reserved_1" newline bitfld.long 0x0 0. "SOURCE,SOURCE" "0,1" line.long 0x4 "RGX_CR_IRQ_OS4_EVENT_STATUS_1,This register indicates the source of a per-OS host interrupt. This register is set by the firmware and cleared by the host." hexmask.long 0x4 0.--31. 1. "Reserved_1,Reserved_1" group.long 0x40BE8++0x7 line.long 0x0 "RGX_CR_IRQ_OS4_EVENT_CLEAR_0,This register clears a per-OS host interrupt." hexmask.long 0x0 1.--31. 1. "Reserved_1,Reserved_1" newline bitfld.long 0x0 0. "SOURCE,SOURCE" "0,1" line.long 0x4 "RGX_CR_IRQ_OS4_EVENT_CLEAR_1,This register clears a per-OS host interrupt." hexmask.long 0x4 0.--31. 1. "Reserved_1,Reserved_1" group.long 0x50B00++0x7 line.long 0x0 "RGX_CR_MTS_SCHEDULE5_0,This register allows firmware tasks to be scheduled on the META (Garten) core." hexmask.long.tbyte 0x0 9.--31. 1. "Reserved_9,Reserved_9" newline bitfld.long 0x0 8. "HOST,Host Interrupte kick" "0,1" newline bitfld.long 0x0 6.--7. "PRIORITY,DataMaster Priority" "0,1,2,3" newline bitfld.long 0x0 5. "CONTEXT,CONTEXT" "0,1" newline bitfld.long 0x0 4. "TASK,TASK" "0,1" newline hexmask.long.byte 0x0 0.--3. 1. "DM,DataMaster Type" line.long 0x4 "RGX_CR_MTS_SCHEDULE5_1,This register allows firmware tasks to be scheduled on the META (Garten) core." hexmask.long 0x4 0.--31. 1. "Reserved_9,Reserved_9" rgroup.long 0x50B98++0x17 line.long 0x0 "RGX_CR_MTS_INTCTX5_0,This register contains the sideband data for the MTS internal interrupt context registers" bitfld.long 0x0 30.--31. "Reserved_30,Reserved_30" "0,1,2,3" newline hexmask.long.byte 0x0 22.--29. 1. "DM_HOST_SCHEDULE,A 1 bit counter per DM for host requests" newline hexmask.long.byte 0x0 16.--21. 1. "Reserved_16,Reserved_16" newline hexmask.long.byte 0x0 8.--15. 1. "DM_TIMER_SCHEDULE,A 1 bit counter per DM for timer requests" newline hexmask.long.byte 0x0 0.--7. 1. "DM_INTERRUPT_SCHEDULE,A 1 bit counter per DM for interrupt requests" line.long 0x4 "RGX_CR_MTS_INTCTX5_1,This register contains the sideband data for the MTS internal interrupt context registers" hexmask.long 0x4 0.--31. 1. "Reserved_30,Reserved_30" line.long 0x8 "RGX_CR_MTS_BGCTX5_0,This register contains the sideband data for the MTS internal background context registers" hexmask.long.tbyte 0x8 8.--31. 1. "Reserved_8,Reserved_8" newline hexmask.long.byte 0x8 0.--7. 1. "DM_NONCOUNTED_SCHEDULE,A 1 bit counter per DM for non-counted background request" line.long 0xC "RGX_CR_MTS_BGCTX5_1,This register contains the sideband data for the MTS internal background context registers" hexmask.long 0xC 0.--31. 1. "Reserved_8,Reserved_8" line.long 0x10 "RGX_CR_MTS_BGCTX_COUNTED_SCHEDULE5_0,This register contains the sideband data for the MTS internal counted background context counters" hexmask.long.byte 0x10 24.--31. 1. "DM3,A 8 bit counter for DM3" newline hexmask.long.byte 0x10 16.--23. 1. "DM2,A 8 bit counter for DM2" newline hexmask.long.byte 0x10 8.--15. 1. "DM1,A 8 bit counter for DM1" newline hexmask.long.byte 0x10 0.--7. 1. "DM0,A 8 bit counter for DM0" line.long 0x14 "RGX_CR_MTS_BGCTX_COUNTED_SCHEDULE5_1,This register contains the sideband data for the MTS internal counted background context counters" hexmask.long.word 0x14 16.--31. 1. "Reserved_48,Reserved_48" newline hexmask.long.byte 0x14 8.--15. 1. "DM5,A 8 bit counter for DM5" newline hexmask.long.byte 0x14 0.--7. 1. "DM4,A 8 bit counter for DM4" rgroup.long 0x50BD8++0x7 line.long 0x0 "RGX_CR_IRQ_OS5_EVENT_STATUS_0,This register indicates the source of a per-OS host interrupt. This register is set by the firmware and cleared by the host." hexmask.long 0x0 1.--31. 1. "Reserved_1,Reserved_1" newline bitfld.long 0x0 0. "SOURCE,SOURCE" "0,1" line.long 0x4 "RGX_CR_IRQ_OS5_EVENT_STATUS_1,This register indicates the source of a per-OS host interrupt. This register is set by the firmware and cleared by the host." hexmask.long 0x4 0.--31. 1. "Reserved_1,Reserved_1" group.long 0x50BE8++0x7 line.long 0x0 "RGX_CR_IRQ_OS5_EVENT_CLEAR_0,This register clears a per-OS host interrupt." hexmask.long 0x0 1.--31. 1. "Reserved_1,Reserved_1" newline bitfld.long 0x0 0. "SOURCE,SOURCE" "0,1" line.long 0x4 "RGX_CR_IRQ_OS5_EVENT_CLEAR_1,This register clears a per-OS host interrupt." hexmask.long 0x4 0.--31. 1. "Reserved_1,Reserved_1" group.long 0x60B00++0x7 line.long 0x0 "RGX_CR_MTS_SCHEDULE6_0,This register allows firmware tasks to be scheduled on the META (Garten) core." hexmask.long.tbyte 0x0 9.--31. 1. "Reserved_9,Reserved_9" newline bitfld.long 0x0 8. "HOST,Host Interrupte kick" "0,1" newline bitfld.long 0x0 6.--7. "PRIORITY,DataMaster Priority" "0,1,2,3" newline bitfld.long 0x0 5. "CONTEXT,CONTEXT" "0,1" newline bitfld.long 0x0 4. "TASK,TASK" "0,1" newline hexmask.long.byte 0x0 0.--3. 1. "DM,DataMaster Type" line.long 0x4 "RGX_CR_MTS_SCHEDULE6_1,This register allows firmware tasks to be scheduled on the META (Garten) core." hexmask.long 0x4 0.--31. 1. "Reserved_9,Reserved_9" rgroup.long 0x60B98++0x17 line.long 0x0 "RGX_CR_MTS_INTCTX6_0,This register contains the sideband data for the MTS internal interrupt context registers" bitfld.long 0x0 30.--31. "Reserved_30,Reserved_30" "0,1,2,3" newline hexmask.long.byte 0x0 22.--29. 1. "DM_HOST_SCHEDULE,A 1 bit counter per DM for host requests" newline hexmask.long.byte 0x0 16.--21. 1. "Reserved_16,Reserved_16" newline hexmask.long.byte 0x0 8.--15. 1. "DM_TIMER_SCHEDULE,A 1 bit counter per DM for timer requests" newline hexmask.long.byte 0x0 0.--7. 1. "DM_INTERRUPT_SCHEDULE,A 1 bit counter per DM for interrupt requests" line.long 0x4 "RGX_CR_MTS_INTCTX6_1,This register contains the sideband data for the MTS internal interrupt context registers" hexmask.long 0x4 0.--31. 1. "Reserved_30,Reserved_30" line.long 0x8 "RGX_CR_MTS_BGCTX6_0,This register contains the sideband data for the MTS internal background context registers" hexmask.long.tbyte 0x8 8.--31. 1. "Reserved_8,Reserved_8" newline hexmask.long.byte 0x8 0.--7. 1. "DM_NONCOUNTED_SCHEDULE,A 1 bit counter per DM for non-counted background request" line.long 0xC "RGX_CR_MTS_BGCTX6_1,This register contains the sideband data for the MTS internal background context registers" hexmask.long 0xC 0.--31. 1. "Reserved_8,Reserved_8" line.long 0x10 "RGX_CR_MTS_BGCTX_COUNTED_SCHEDULE6_0,This register contains the sideband data for the MTS internal counted background context counters" hexmask.long.byte 0x10 24.--31. 1. "DM3,A 8 bit counter for DM3" newline hexmask.long.byte 0x10 16.--23. 1. "DM2,A 8 bit counter for DM2" newline hexmask.long.byte 0x10 8.--15. 1. "DM1,A 8 bit counter for DM1" newline hexmask.long.byte 0x10 0.--7. 1. "DM0,A 8 bit counter for DM0" line.long 0x14 "RGX_CR_MTS_BGCTX_COUNTED_SCHEDULE6_1,This register contains the sideband data for the MTS internal counted background context counters" hexmask.long.word 0x14 16.--31. 1. "Reserved_48,Reserved_48" newline hexmask.long.byte 0x14 8.--15. 1. "DM5,A 8 bit counter for DM5" newline hexmask.long.byte 0x14 0.--7. 1. "DM4,A 8 bit counter for DM4" rgroup.long 0x60BD8++0x7 line.long 0x0 "RGX_CR_IRQ_OS6_EVENT_STATUS_0,This register indicates the source of a per-OS host interrupt. This register is set by the firmware and cleared by the host." hexmask.long 0x0 1.--31. 1. "Reserved_1,Reserved_1" newline bitfld.long 0x0 0. "SOURCE,SOURCE" "0,1" line.long 0x4 "RGX_CR_IRQ_OS6_EVENT_STATUS_1,This register indicates the source of a per-OS host interrupt. This register is set by the firmware and cleared by the host." hexmask.long 0x4 0.--31. 1. "Reserved_1,Reserved_1" group.long 0x60BE8++0x7 line.long 0x0 "RGX_CR_IRQ_OS6_EVENT_CLEAR_0,This register clears a per-OS host interrupt." hexmask.long 0x0 1.--31. 1. "Reserved_1,Reserved_1" newline bitfld.long 0x0 0. "SOURCE,SOURCE" "0,1" line.long 0x4 "RGX_CR_IRQ_OS6_EVENT_CLEAR_1,This register clears a per-OS host interrupt." hexmask.long 0x4 0.--31. 1. "Reserved_1,Reserved_1" group.long 0x70B00++0x7 line.long 0x0 "RGX_CR_MTS_SCHEDULE7_0,This register allows firmware tasks to be scheduled on the META (Garten) core." hexmask.long.tbyte 0x0 9.--31. 1. "Reserved_9,Reserved_9" newline bitfld.long 0x0 8. "HOST,Host Interrupte kick" "0,1" newline bitfld.long 0x0 6.--7. "PRIORITY,DataMaster Priority" "0,1,2,3" newline bitfld.long 0x0 5. "CONTEXT,CONTEXT" "0,1" newline bitfld.long 0x0 4. "TASK,TASK" "0,1" newline hexmask.long.byte 0x0 0.--3. 1. "DM,DataMaster Type" line.long 0x4 "RGX_CR_MTS_SCHEDULE7_1,This register allows firmware tasks to be scheduled on the META (Garten) core." hexmask.long 0x4 0.--31. 1. "Reserved_9,Reserved_9" rgroup.long 0x70B98++0x17 line.long 0x0 "RGX_CR_MTS_INTCTX7_0,This register contains the sideband data for the MTS internal interrupt context registers" bitfld.long 0x0 30.--31. "Reserved_30,Reserved_30" "0,1,2,3" newline hexmask.long.byte 0x0 22.--29. 1. "DM_HOST_SCHEDULE,A 1 bit counter per DM for host requests" newline hexmask.long.byte 0x0 16.--21. 1. "Reserved_16,Reserved_16" newline hexmask.long.byte 0x0 8.--15. 1. "DM_TIMER_SCHEDULE,A 1 bit counter per DM for timer requests" newline hexmask.long.byte 0x0 0.--7. 1. "DM_INTERRUPT_SCHEDULE,A 1 bit counter per DM for interrupt requests" line.long 0x4 "RGX_CR_MTS_INTCTX7_1,This register contains the sideband data for the MTS internal interrupt context registers" hexmask.long 0x4 0.--31. 1. "Reserved_30,Reserved_30" line.long 0x8 "RGX_CR_MTS_BGCTX7_0,This register contains the sideband data for the MTS internal background context registers" hexmask.long.tbyte 0x8 8.--31. 1. "Reserved_8,Reserved_8" newline hexmask.long.byte 0x8 0.--7. 1. "DM_NONCOUNTED_SCHEDULE,A 1 bit counter per DM for non-counted background request" line.long 0xC "RGX_CR_MTS_BGCTX7_1,This register contains the sideband data for the MTS internal background context registers" hexmask.long 0xC 0.--31. 1. "Reserved_8,Reserved_8" line.long 0x10 "RGX_CR_MTS_BGCTX_COUNTED_SCHEDULE7_0,This register contains the sideband data for the MTS internal counted background context counters" hexmask.long.byte 0x10 24.--31. 1. "DM3,A 8 bit counter for DM3" newline hexmask.long.byte 0x10 16.--23. 1. "DM2,A 8 bit counter for DM2" newline hexmask.long.byte 0x10 8.--15. 1. "DM1,A 8 bit counter for DM1" newline hexmask.long.byte 0x10 0.--7. 1. "DM0,A 8 bit counter for DM0" line.long 0x14 "RGX_CR_MTS_BGCTX_COUNTED_SCHEDULE7_1,This register contains the sideband data for the MTS internal counted background context counters" hexmask.long.word 0x14 16.--31. 1. "Reserved_48,Reserved_48" newline hexmask.long.byte 0x14 8.--15. 1. "DM5,A 8 bit counter for DM5" newline hexmask.long.byte 0x14 0.--7. 1. "DM4,A 8 bit counter for DM4" rgroup.long 0x70BD8++0x7 line.long 0x0 "RGX_CR_IRQ_OS7_EVENT_STATUS_0,This register indicates the source of a per-OS host interrupt. This register is set by the firmware and cleared by the host." hexmask.long 0x0 1.--31. 1. "Reserved_1,Reserved_1" newline bitfld.long 0x0 0. "SOURCE,SOURCE" "0,1" line.long 0x4 "RGX_CR_IRQ_OS7_EVENT_STATUS_1,This register indicates the source of a per-OS host interrupt. This register is set by the firmware and cleared by the host." hexmask.long 0x4 0.--31. 1. "Reserved_1,Reserved_1" group.long 0x70BE8++0x7 line.long 0x0 "RGX_CR_IRQ_OS7_EVENT_CLEAR_0,This register clears a per-OS host interrupt." hexmask.long 0x0 1.--31. 1. "Reserved_1,Reserved_1" newline bitfld.long 0x0 0. "SOURCE,SOURCE" "0,1" line.long 0x4 "RGX_CR_IRQ_OS7_EVENT_CLEAR_1,This register clears a per-OS host interrupt." hexmask.long 0x4 0.--31. 1. "Reserved_1,Reserved_1" tree.end elif (CORENAME()=="CORTEXA55") tree "GPU1" base ad:0x34C00000 group.long 0x0++0x7 line.long 0x0 "RGX_CR_CLK_CTRL_0,Core Module Clock Control Modes. Allows individual domain clocks to be forced off. forced on or operate under automatic pipeline activity based clock gating. This register is generally controlled by the GPU firmware and should be set to.." bitfld.long 0x0 30.--31. "Reserved_30,Reserved_30" "0,1,2,3" newline bitfld.long 0x0 28.--29. "TPU_MCU_DEMUX,TPU_MCU_DEMUX" "0,1,2,3" newline bitfld.long 0x0 26.--27. "MCU_L0,MCU_L0" "0,1,2,3" newline bitfld.long 0x0 24.--25. "TPU,TPU" "0,1,2,3" newline bitfld.long 0x0 22.--23. "Reserved_22,Reserved_22" "0,1,2,3" newline bitfld.long 0x0 20.--21. "USC,USC" "0,1,2,3" newline bitfld.long 0x0 18.--19. "Reserved_18,Reserved_18" "0,1,2,3" newline bitfld.long 0x0 16.--17. "SLC,SLC" "0,1,2,3" newline bitfld.long 0x0 14.--15. "UVS,UVS" "0,1,2,3" newline bitfld.long 0x0 12.--13. "PDS,PDS" "0,1,2,3" newline bitfld.long 0x0 10.--11. "VDM,VDM" "0,1,2,3" newline bitfld.long 0x0 8.--9. "PM,PM" "0,1,2,3" newline bitfld.long 0x0 6.--7. "GPP,GPP" "0,1,2,3" newline bitfld.long 0x0 4.--5. "TE,TE" "0,1,2,3" newline bitfld.long 0x0 2.--3. "TSP,TSP" "0,1,2,3" newline bitfld.long 0x0 0.--1. "ISP,ISP" "0,1,2,3" line.long 0x4 "RGX_CR_CLK_CTRL_1,Core Module Clock Control Modes. Allows individual domain clocks to be forced off. forced on or operate under automatic pipeline activity based clock gating. This register is generally controlled by the GPU firmware and should be set to.." hexmask.long.byte 0x4 28.--31. 1. "Reserved_60,Reserved_60" newline bitfld.long 0x4 26.--27. "FBC,FBC" "0,1,2,3" newline bitfld.long 0x4 24.--25. "FBDC,FBDC" "0,1,2,3" newline bitfld.long 0x4 22.--23. "FB_TLCACHE,FB_TLCACHE" "0,1,2,3" newline bitfld.long 0x4 20.--21. "USCS,USCS" "0,1,2,3" newline bitfld.long 0x4 18.--19. "PBE,PBE" "0,1,2,3" newline bitfld.long 0x4 16.--17. "MCU_L1,MCU_L1" "0,1,2,3" newline bitfld.long 0x4 14.--15. "CDM,CDM" "0,1,2,3" newline bitfld.long 0x4 12.--13. "SIDEKICK,SIDEKICK" "0,1,2,3" newline bitfld.long 0x4 10.--11. "BIF_SIDEKICK,BIF_SIDEKICK" "0,1,2,3" newline bitfld.long 0x4 8.--9. "BIF,BIF" "0,1,2,3" newline hexmask.long.byte 0x4 0.--7. 1. "Reserved_30,Reserved_30" rgroup.long 0x8++0x7 line.long 0x0 "RGX_CR_CLK_STATUS_0,Reports the current module clock status Clock gating state reflects the condition of the clock for each module" bitfld.long 0x0 30.--31. "Reserved_30,Reserved_30" "0,1,2,3" newline bitfld.long 0x0 29. "FBC,FBC" "0,1" newline bitfld.long 0x0 28. "FBDC,FBDC" "0,1" newline bitfld.long 0x0 27. "FB_TLCACHE,FB_TLCACHE" "0,1" newline bitfld.long 0x0 26. "USCS,USCS" "0,1" newline bitfld.long 0x0 25. "PBE,PBE" "0,1" newline bitfld.long 0x0 24. "MCU_L1,MCU_L1" "0,1" newline bitfld.long 0x0 23. "CDM,CDM" "0,1" newline bitfld.long 0x0 22. "SIDEKICK,SIDEKICK" "0,1" newline bitfld.long 0x0 21. "BIF_SIDEKICK,BIF_SIDEKICK" "0,1" newline bitfld.long 0x0 20. "BIF,BIF" "0,1" newline hexmask.long.byte 0x0 15.--19. 1. "Reserved_15,Reserved_15" newline bitfld.long 0x0 14. "TPU_MCU_DEMUX,TPU_MCU_DEMUX" "0,1" newline bitfld.long 0x0 13. "MCU_L0,MCU_L0" "0,1" newline bitfld.long 0x0 12. "TPU,TPU" "0,1" newline bitfld.long 0x0 11. "Reserved_11,Reserved_11" "0,1" newline bitfld.long 0x0 10. "USC,USC" "0,1" newline bitfld.long 0x0 9. "Reserved_9,Reserved_9" "0,1" newline bitfld.long 0x0 8. "SLC,SLC" "0,1" newline bitfld.long 0x0 7. "UVS,UVS" "0,1" newline bitfld.long 0x0 6. "PDS,PDS" "0,1" newline bitfld.long 0x0 5. "VDM,VDM" "0,1" newline bitfld.long 0x0 4. "PM,PM" "0,1" newline bitfld.long 0x0 3. "GPP,GPP" "0,1" newline bitfld.long 0x0 2. "TE,TE" "0,1" newline bitfld.long 0x0 1. "TSP,TSP" "0,1" newline bitfld.long 0x0 0. "ISP,ISP" "0,1" line.long 0x4 "RGX_CR_CLK_STATUS_1,Reports the current module clock status Clock gating state reflects the condition of the clock for each module" hexmask.long 0x4 1.--31. 1. "Reserved_33,Reserved_33" newline bitfld.long 0x4 0. "MCU_FBTC,MCU_FBTC" "0,1" rgroup.long 0x18++0x7 line.long 0x0 "RGX_CR_PRODUCT_ID_0,Reports the product ID Product ID Register" hexmask.long.word 0x0 16.--31. 1. "IMG_PRODUCT_ID,IMG Product ID" newline hexmask.long.word 0x0 0.--15. 1. "Reserved_0,Reserved_0" line.long 0x4 "RGX_CR_PRODUCT_ID_1,Reports the product ID Product ID Register" hexmask.long 0x4 0.--31. 1. "Reserved_32,Reserved_32" repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) rgroup.long ($2+0x20)++0x3 line.long 0x0 "RGX_CR_CORE_ID_$1,Reports the product ID Core ID Register" hexmask.long.word 0x0 16.--31. 1. "NUMBER_OF_SCALABLE_UNITS,N - Number of scalable Units" newline hexmask.long.word 0x0 0.--15. 1. "CONFIG_ID,C - Config ID" repeat.end repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) rgroup.long ($2+0x28)++0x3 line.long 0x0 "RGX_CR_CORE_IP_INTEGRATOR_ID_$1,Reports the product ID Core IP Integrator ID Register" hexmask.long 0x0 0.--31. 1. "VALUE,IP company ID/Designer" repeat.end repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) rgroup.long ($2+0x30)++0x3 line.long 0x0 "RGX_CR_CORE_IP_CHANGELIST_$1,Reports the version control ID Core IP Changelist Register" hexmask.long 0x0 0.--31. 1. "VALUE,Version control ID" repeat.end group.long 0x38++0x7 line.long 0x0 "RGX_CR_POWER_EVENT_0,Allows the firmware to request a power-up or power-down operation to an external (to Rogue) power-management controller When the power event operation is accepted. the firmware will either receive an.." hexmask.long.byte 0x0 24.--31. 1. "Reserved_24,Reserved_24" newline hexmask.long.word 0x0 8.--23. 1. "DOMAIN,sets which power island is enabled for the current power event request; bit0:jones bit1-8:dusts bit9-12:blackpearls" newline hexmask.long.byte 0x0 2.--7. 1. "Reserved_2,Reserved_2" newline bitfld.long 0x0 1. "REQ,Set when a power event operation is requested" "0,1" newline bitfld.long 0x0 0. "TYPE,The requested power event operation" "0,1" line.long 0x4 "RGX_CR_POWER_EVENT_1,Allows the firmware to request a power-up or power-down operation to an external (to Rogue) power-management controller When the power event operation is accepted. the firmware will either receive an.." hexmask.long 0x4 0.--31. 1. "Reserved_24,Reserved_24" group.long 0x50++0x7 line.long 0x0 "RGX_CR_DUSTS_ENABLE_0,Controls how many Dual Unified Shading and Texturing Units (DUSTs) are enabled. Each DUST Contain 2 USCs and a TPU module. (Available on 2. X.X.X cores and above). Only applicable in cores with a B.V.N.C > 2.0.0.0 Controls how many.." hexmask.long.tbyte 0x0 8.--31. 1. "Reserved_8,Reserved_8" newline hexmask.long.byte 0x0 0.--7. 1. "ENABLE,Dusts enabled" line.long 0x4 "RGX_CR_DUSTS_ENABLE_1,Controls how many Dual Unified Shading and Texturing Units (DUSTs) are enabled. Each DUST Contain 2 USCs and a TPU module. (Available on 2. X.X.X cores and above). Only applicable in cores with a B.V.N.C > 2.0.0.0 Controls how many.." hexmask.long 0x4 0.--31. 1. "Reserved_8,Reserved_8" rgroup.long 0x58++0x7 line.long 0x0 "RGX_CR_DUSTS_FUSE_0,Indicates how many of the available DUST modules are enabled on the Silicon. (Available on 2.X.X.X cores and above). Shows the raw value of dusts_enable port." hexmask.long.tbyte 0x0 8.--31. 1. "Reserved_8,Reserved_8" newline hexmask.long.byte 0x0 0.--7. 1. "ENABLE,Dusts enabled" line.long 0x4 "RGX_CR_DUSTS_FUSE_1,Indicates how many of the available DUST modules are enabled on the Silicon. (Available on 2.X.X.X cores and above). Shows the raw value of dusts_enable port." hexmask.long 0x4 0.--31. 1. "Reserved_8,Reserved_8" group.long 0x80++0x7 line.long 0x0 "RGX_CR_CLK_XTPLUS_CTRL_0,Core Module Clock Control Modes. Allows individual domain clocks to be forced off. forced on or operate under automatic pipeline activity based clock gating. This register is generally controlled by the GPU firmware and should be.." hexmask.long 0x0 0.--31. 1. "Reserved_0,Reserved_0" line.long 0x4 "RGX_CR_CLK_XTPLUS_CTRL_1,Core Module Clock Control Modes. Allows individual domain clocks to be forced off. forced on or operate under automatic pipeline activity based clock gating. This register is generally controlled by the GPU firmware and should be.." hexmask.long 0x4 6.--31. 1. "Reserved_38,Reserved_38" newline bitfld.long 0x4 4.--5. "TDM,TDM" "0,1,2,3" newline bitfld.long 0x4 2.--3. "ASTC,ASTC" "0,1,2,3" newline bitfld.long 0x4 0.--1. "Reserved_0,Reserved_0" "0,1,2,3" rgroup.long 0x88++0x7 line.long 0x0 "RGX_CR_CLK_XTPLUS_STATUS_0,Reports the current module clock status Clock gating state reflects the condition of the clock for each module" hexmask.long.tbyte 0x0 11.--31. 1. "Reserved_11,Reserved_11" newline bitfld.long 0x0 10. "TDM,TDM" "0,1" newline bitfld.long 0x0 9. "IPF,IPF" "0,1" newline bitfld.long 0x0 8. "COMPUTE,COMPUTE" "0,1" newline bitfld.long 0x0 7. "ASTC,ASTC" "0,1" newline bitfld.long 0x0 6. "PIXEL,PIXEL" "0,1" newline bitfld.long 0x0 5. "VERTEX,VERTEX" "0,1" newline bitfld.long 0x0 4. "Reserved_4,Reserved_4" "0,1" newline bitfld.long 0x0 3. "PDS_SHARED,PDS_SHARED" "0,1" newline bitfld.long 0x0 2. "BIF_BLACKPEARL,BIF_BLACKPEARL" "0,1" newline bitfld.long 0x0 1. "USC_SHARED,USC_SHARED" "0,1" newline bitfld.long 0x0 0. "GEOMETRY,GEOMETRY" "0,1" line.long 0x4 "RGX_CR_CLK_XTPLUS_STATUS_1,Reports the current module clock status Clock gating state reflects the condition of the clock for each module" hexmask.long 0x4 0.--31. 1. "Reserved_11,Reserved_11" repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) rgroup.long ($2+0xE0)++0x3 line.long 0x0 "RGX_CR_SOC_TIMER_GRAY_$1,This register contains the value of a 64-bit external gray coded timer. (Available on 2.X.X.X cores and above)." hexmask.long 0x0 0.--31. 1. "VALUE,VALUE" repeat.end repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) rgroup.long ($2+0xE8)++0x3 line.long 0x0 "RGX_CR_SOC_TIMER_BINARY_$1,This register contains the value of a 64-bit external binary coded timer." hexmask.long 0x0 0.--31. 1. "VALUE,VALUE" repeat.end group.long 0x100++0xF line.long 0x0 "RGX_CR_SOFT_RESET_0,Core soft reset control register. Write a '1' to reset and a '0' to clear See the soft reset section in the TRM to understand how to use the soft reset register." bitfld.long 0x0 31. "RASCAL_CORE,Note that the RASL_CORE bit affects logic related to the reading and writing of registers. This soft reset should therefore be used with caution. Upon power down events it is necessary to reset every register so this bit should be used but.." "0,1" newline bitfld.long 0x0 30. "DUST_B_CORE,DUST_B_CORE" "0,1" newline bitfld.long 0x0 29. "DUST_A_CORE,DUST_A_CORE" "0,1" newline bitfld.long 0x0 28. "FB_TLCACHE,FB_TLCACHE" "0,1" newline bitfld.long 0x0 27. "SLC,SLC" "0,1" newline bitfld.long 0x0 26. "Reserved_26,Reserved_26" "0,1" newline bitfld.long 0x0 25. "UVS,UVS" "0,1" newline bitfld.long 0x0 24. "TE,TE" "0,1" newline bitfld.long 0x0 23. "GPP,GPP" "0,1" newline bitfld.long 0x0 22. "FBDC,FBDC" "0,1" newline bitfld.long 0x0 21. "FBC,FBC" "0,1" newline bitfld.long 0x0 20. "PM,PM" "0,1" newline bitfld.long 0x0 19. "PBE,PBE" "0,1" newline bitfld.long 0x0 18. "USC_SHARED,USC_SHARED" "0,1" newline bitfld.long 0x0 17. "MCU_L1,MCU_L1" "0,1" newline bitfld.long 0x0 16. "BIF,Bifpmcache BIF" "0,1" newline bitfld.long 0x0 15. "CDM,CDM" "0,1" newline bitfld.long 0x0 14. "VDM,VDM" "0,1" newline bitfld.long 0x0 13. "Reserved_13,Reserved_13" "0,1" newline bitfld.long 0x0 12. "PDS,PDS" "0,1" newline bitfld.long 0x0 11. "ISP,ISP" "0,1" newline bitfld.long 0x0 10. "TSP,TSP" "0,1" newline hexmask.long.byte 0x0 5.--9. 1. "Reserved_5,Reserved_5" newline bitfld.long 0x0 4. "TPU_MCU_DEMUX,TPU_MCU_DEMUX" "0,1" newline bitfld.long 0x0 3. "MCU_L0,MCU_L0" "0,1" newline bitfld.long 0x0 2. "TPU,TPU" "0,1" newline bitfld.long 0x0 1. "Reserved_1,Reserved_1" "0,1" newline bitfld.long 0x0 0. "USC,USC" "0,1" line.long 0x4 "RGX_CR_SOFT_RESET_1,Core soft reset control register. Write a '1' to reset and a '0' to clear See the soft reset section in the TRM to understand how to use the soft reset register." bitfld.long 0x4 29.--31. "Reserved_61,Reserved_61" "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 28. "JONES_CORE,JONES_CORE" "0,1" newline bitfld.long 0x4 27. "TILING_CORE,TILING_CORE" "0,1" newline bitfld.long 0x4 26. "TE3,TE3" "0,1" newline bitfld.long 0x4 25. "VCE,VCE" "0,1" newline bitfld.long 0x4 24. "VBS,VBS" "0,1" newline hexmask.long.byte 0x4 20.--23. 1. "Reserved_52,Reserved_52" newline bitfld.long 0x4 19. "FB_CDC,FB_CDC" "0,1" newline bitfld.long 0x4 17.--18. "Reserved_49,Reserved_49" "0,1,2,3" newline bitfld.long 0x4 16. "MCU_FBTC,MCU_FBTC" "0,1" newline hexmask.long.word 0x4 3.--15. 1. "Reserved_35,Reserved_35" newline bitfld.long 0x4 2. "MMU,MMU" "0,1" newline bitfld.long 0x4 1. "Reserved_33,Reserved_33" "0,1" newline bitfld.long 0x4 0. "GARTEN,Includes MTS and META or MIPS" "0,1" line.long 0x8 "RGX_CR_SOFT_RESET2_0,Core soft reset control register. Write a '1' to reset and a '0' to clear See the soft reset section in the TRM to understand how to use the soft reset register." hexmask.long.tbyte 0x8 12.--31. 1. "Reserved_12,Reserved_12" newline bitfld.long 0x8 11. "TDM,TDM" "0,1" newline bitfld.long 0x8 10. "ASTC,ASTC" "0,1" newline bitfld.long 0x8 9. "BLACKPEARL,BLACKPEARL" "0,1" newline bitfld.long 0x8 8. "Reserved_8,Reserved_8" "0,1" newline bitfld.long 0x8 7. "IPF,IPF" "0,1" newline bitfld.long 0x8 6. "GEOMETRY,GEOMETRY" "0,1" newline bitfld.long 0x8 5. "USC_SHARED,USC_SHARED" "0,1" newline bitfld.long 0x8 4. "PDS_SHARED,PDS_SHARED" "0,1" newline bitfld.long 0x8 3. "BIF_BLACKPEARL,BIF_BLACKPEARL" "0,1" newline bitfld.long 0x8 2. "PIXEL,PIXEL" "0,1" newline bitfld.long 0x8 1. "Reserved_1,Reserved_1" "0,1" newline bitfld.long 0x8 0. "VERTEX,VERTEX" "0,1" line.long 0xC "RGX_CR_SOFT_RESET2_1,Core soft reset control register. Write a '1' to reset and a '0' to clear See the soft reset section in the TRM to understand how to use the soft reset register." hexmask.long 0xC 0.--31. 1. "Reserved_12,Reserved_12" group.long 0x120++0x17 line.long 0x0 "RGX_CR_CONTEXT_SWITCH_ENABLE_0,The use of the this register has been deprecated." hexmask.long 0x0 4.--31. 1. "Reserved_4,Reserved_4" newline bitfld.long 0x0 3. "SOFT_RESET,SOFT_RESET" "0,1" newline bitfld.long 0x0 2. "IPF,IPF" "0,1" newline bitfld.long 0x0 1. "VDM,VDM" "0,1" newline bitfld.long 0x0 0. "CDM,CDM" "0,1" line.long 0x4 "RGX_CR_CONTEXT_SWITCH_ENABLE_1,The use of the this register has been deprecated." hexmask.long 0x4 0.--31. 1. "Reserved_4,Reserved_4" line.long 0x8 "RGX_CR_EVENT_ENABLE_0,This register is used to enable GPU interrupts directly to the host Writing a '1' to a bit field enables the relevant event This register should only be programmed when the META firmware is not used If the META firmware is used. the.." bitfld.long 0x8 31. "TDM_FENCE_FINISHED,Indicates a 2D fence has been processed" "0,1" newline bitfld.long 0x8 30. "TDM_BUFFER_STALL,The TDM has exhausted the current 2D circular buffer (read pointer = write_pointer)" "0,1" newline hexmask.long.word 0x8 19.--29. 1. "Reserved_19,Reserved_19" newline bitfld.long 0x8 18. "TDM_CONTEXT_STORE_FINISHED,The TDM has completed the requested context store operation." "0,1" newline bitfld.long 0x8 16.--17. "Reserved_16,Reserved_16" "0,1,2,3" newline bitfld.long 0x8 15. "USC_TRIGGER,One or more USC has executed a nop.trigger instruction" "0,1" newline bitfld.long 0x8 14. "ZLS_FINISHED,ZLS has finished all tiles in a Render" "0,1" newline bitfld.long 0x8 13. "GPIO_ACK,General Purpose ouput acknowledgement" "0,1" newline bitfld.long 0x8 12. "GPIO_REQ,General Purpose input request" "0,1" newline bitfld.long 0x8 11. "POWER_ABORT,The requested power operation has been denied." "0,1" newline bitfld.long 0x8 10. "POWER_COMPLETE,The requested power operation has completed" "0,1" newline bitfld.long 0x8 9. "MMU_PAGE_FAULT,An MMU page fault has occurred" "0,1" newline bitfld.long 0x8 8. "PM_3D_MEM_FREE,PM memory allocation completed for the current render" "0,1" newline bitfld.long 0x8 7. "PM_OUT_OF_MEMORY,PM memory allocation failed for a macro-tile" "0,1" newline bitfld.long 0x8 6. "TA_TERMINATE,The TE has aborted a macro tile after a failted PM allocation request" "0,1" newline bitfld.long 0x8 5. "TA_FINISHED,The TA phase has completed" "0,1" newline bitfld.long 0x8 4. "ISP_END_MACROTILE,ISP End-of-Macrotile" "0,1" newline bitfld.long 0x8 3. "PIXELBE_END_RENDER,The 3D phase has completed" "0,1" newline bitfld.long 0x8 2. "COMPUTE_FINISHED,The compute phase has completed" "0,1" newline bitfld.long 0x8 1. "KERNEL_FINISHED,A compute kernel has completed and updated the associated event object in external memory" "0,1" newline bitfld.long 0x8 0. "Reserved_0,Reserved_0" "0,1" line.long 0xC "RGX_CR_EVENT_ENABLE_1,This register is used to enable GPU interrupts directly to the host Writing a '1' to a bit field enables the relevant event This register should only be programmed when the META firmware is not used If the META firmware is used. the.." hexmask.long 0xC 0.--31. 1. "Reserved_32,Reserved_32" line.long 0x10 "RGX_CR_EVENT_STATUS_0,The event status register indicate the source of an interrupt generated by PowerVR RGX These events only schedule an interrupt context thread to run on META when the appropriate enables are set in RGX_CR_DMn_INTERRUPT_ENABLE" bitfld.long 0x10 31. "TDM_FENCE_FINISHED,Indicates a 2D fence has been processed" "0,1" newline bitfld.long 0x10 30. "TDM_BUFFER_STALL,The TDM has exhausted the current 2D circular buffer (read pointer = write_pointer)" "0,1" newline hexmask.long.word 0x10 19.--29. 1. "Reserved_19,Reserved_19" newline bitfld.long 0x10 18. "TDM_CONTEXT_STORE_FINISHED,The TDM has completed the requested context store operation." "0,1" newline bitfld.long 0x10 16.--17. "Reserved_16,Reserved_16" "0,1,2,3" newline bitfld.long 0x10 15. "USC_TRIGGER,One or more USC has executed a nop.trigger instruction" "0,1" newline bitfld.long 0x10 14. "ZLS_FINISHED,ZLS has finished all tiles in a Render" "0,1" newline bitfld.long 0x10 13. "GPIO_ACK,General Purpose ouput acknowledgement" "0,1" newline bitfld.long 0x10 12. "GPIO_REQ,General Purpose input request" "0,1" newline bitfld.long 0x10 11. "POWER_ABORT,The requested power operation has been denied." "0,1" newline bitfld.long 0x10 10. "POWER_COMPLETE,The requested power operation has completed" "0,1" newline bitfld.long 0x10 9. "MMU_PAGE_FAULT,An MMU page fault has occurred" "0,1" newline bitfld.long 0x10 8. "PM_3D_MEM_FREE,PM memory allocation completed for the current render" "0,1" newline bitfld.long 0x10 7. "PM_OUT_OF_MEMORY,PM memory allocation failed for a macro-tile" "0,1" newline bitfld.long 0x10 6. "TA_TERMINATE,The TE has aborted a macro tile after a failted PM allocation request" "0,1" newline bitfld.long 0x10 5. "TA_FINISHED,The TA phase has completed" "0,1" newline bitfld.long 0x10 4. "ISP_END_MACROTILE,ISP End-of-Macrotile" "0,1" newline bitfld.long 0x10 3. "PIXELBE_END_RENDER,The 3D phase has completed" "0,1" newline bitfld.long 0x10 2. "COMPUTE_FINISHED,The compute phase has completed" "0,1" newline bitfld.long 0x10 1. "KERNEL_FINISHED,A compute kernel has completed and updated the associated event object in external memory" "0,1" newline bitfld.long 0x10 0. "Reserved_0,Reserved_0" "0,1" line.long 0x14 "RGX_CR_EVENT_STATUS_1,The event status register indicate the source of an interrupt generated by PowerVR RGX These events only schedule an interrupt context thread to run on META when the appropriate enables are set in RGX_CR_DMn_INTERRUPT_ENABLE" hexmask.long 0x14 0.--31. 1. "Reserved_32,Reserved_32" wgroup.long 0x138++0x7 line.long 0x0 "RGX_CR_EVENT_CLEAR_0,This register is used to clear event interrupts. Writing a '1' to a bit field clears the relevant event." bitfld.long 0x0 31. "TDM_FENCE_FINISHED,Indicates a 2D fence has been processed" "0,1" newline bitfld.long 0x0 30. "TDM_BUFFER_STALL,The TDM has exhausted the current 2D circular buffer (read pointer = write_pointer)" "0,1" newline hexmask.long.word 0x0 19.--29. 1. "Reserved_19,Reserved_19" newline bitfld.long 0x0 18. "TDM_CONTEXT_STORE_FINISHED,The TDM has completed the requested context store operation." "0,1" newline bitfld.long 0x0 16.--17. "Reserved_16,Reserved_16" "0,1,2,3" newline bitfld.long 0x0 15. "USC_TRIGGER,One or more USC has executed a nop.trigger instruction" "0,1" newline bitfld.long 0x0 14. "ZLS_FINISHED,ZLS has finished all tiles in a Render" "0,1" newline bitfld.long 0x0 13. "GPIO_ACK,General Purpose ouput acknowledgement" "0,1" newline bitfld.long 0x0 12. "GPIO_REQ,General Purpose input request" "0,1" newline bitfld.long 0x0 11. "POWER_ABORT,The requested power operation has been denied." "0,1" newline bitfld.long 0x0 10. "POWER_COMPLETE,The requested power operation has completed" "0,1" newline bitfld.long 0x0 9. "MMU_PAGE_FAULT,An MMU page fault has occurred" "0,1" newline bitfld.long 0x0 8. "PM_3D_MEM_FREE,PM memory allocation completed for the current render" "0,1" newline bitfld.long 0x0 7. "PM_OUT_OF_MEMORY,PM memory allocation failed for a macro-tile" "0,1" newline bitfld.long 0x0 6. "TA_TERMINATE,The TE has aborted a macro tile after a failted PM allocation request" "0,1" newline bitfld.long 0x0 5. "TA_FINISHED,The TA phase has completed" "0,1" newline bitfld.long 0x0 4. "ISP_END_MACROTILE,ISP End-of-Macrotile" "0,1" newline bitfld.long 0x0 3. "PIXELBE_END_RENDER,The 3D phase has completed" "0,1" newline bitfld.long 0x0 2. "COMPUTE_FINISHED,The compute phase has completed" "0,1" newline bitfld.long 0x0 1. "KERNEL_FINISHED,A compute kernel has completed and updated the associated event object in external memory" "0,1" newline bitfld.long 0x0 0. "Reserved_0,Reserved_0" "0,1" line.long 0x4 "RGX_CR_EVENT_CLEAR_1,This register is used to clear event interrupts. Writing a '1' to a bit field clears the relevant event." hexmask.long 0x4 0.--31. 1. "Reserved_32,Reserved_32" group.long 0x140++0xF line.long 0x0 "RGX_CR_GPIO_OUTPUT_DATA_0,General Purpose Input/Output interface for implementing communication protocol between HW external to Rogue and the firmware These registers are connected to top-level pins These registers are driven by the firmware. When the.." hexmask.long.tbyte 0x0 8.--31. 1. "Reserved_8,Reserved_8" newline hexmask.long.byte 0x0 0.--7. 1. "DATA,The data the firmware wants to transfer" line.long 0x4 "RGX_CR_GPIO_OUTPUT_DATA_1,General Purpose Input/Output interface for implementing communication protocol between HW external to Rogue and the firmware These registers are connected to top-level pins These registers are driven by the firmware. When the.." hexmask.long 0x4 0.--31. 1. "Reserved_8,Reserved_8" line.long 0x8 "RGX_CR_GPIO_OUTPUT_REQ_0,General Purpose Input/Output interface for implementing communication protocol between HW external to Rogue and the firmware This register is connected to a top-level pin This register is driven by the firmware. When the request.." hexmask.long 0x8 1.--31. 1. "Reserved_1,Reserved_1" newline bitfld.long 0x8 0. "REQ,Set when the firmware wants to communicate with a external HW" "0,1" line.long 0xC "RGX_CR_GPIO_OUTPUT_REQ_1,General Purpose Input/Output interface for implementing communication protocol between HW external to Rogue and the firmware This register is connected to a top-level pin This register is driven by the firmware. When the request.." hexmask.long 0xC 0.--31. 1. "Reserved_1,Reserved_1" rgroup.long 0x150++0x7 line.long 0x0 "RGX_CR_GPIO_INPUT_DATA_0,General Purpose Input/Output interface for implementing communication protocol between HW external to Rogue and the firmware This register is connected to top-level pins This register is driven by HW external to rogue before.." hexmask.long.tbyte 0x0 8.--31. 1. "Reserved_8,Reserved_8" newline hexmask.long.byte 0x0 0.--7. 1. "DATA,The incoming data from HW external to Rogue" line.long 0x4 "RGX_CR_GPIO_INPUT_DATA_1,General Purpose Input/Output interface for implementing communication protocol between HW external to Rogue and the firmware This register is connected to top-level pins This register is driven by HW external to rogue before.." hexmask.long 0x4 0.--31. 1. "Reserved_8,Reserved_8" group.long 0x158++0x7 line.long 0x0 "RGX_CR_GPIO_INPUT_ACK_0,General Purpose Input/Output interface for implementing communication protocol between HW external to Rogue and the firmware This register is connected to a top-level pin This register is driven by external HW in response to an.." hexmask.long 0x0 1.--31. 1. "Reserved_1,Reserved_1" newline bitfld.long 0x0 0. "ACK,Set by the firmware when it has acknowledged the incoming request" "0,1" line.long 0x4 "RGX_CR_GPIO_INPUT_ACK_1,General Purpose Input/Output interface for implementing communication protocol between HW external to Rogue and the firmware This register is connected to a top-level pin This register is driven by external HW in response to an.." hexmask.long 0x4 0.--31. 1. "Reserved_1,Reserved_1" rgroup.long 0x160++0x7 line.long 0x0 "RGX_CR_TIMER_0,This register contains the value of a 48-bit internal timer. The timer runs continuously. and wraps at the top end. It counts 256 cycles at the core clock frequency. This means that at 100 MHz: 1 count value = 1/100MHz = 256 * 10 * 10^-9.." hexmask.long 0x0 0.--31. 1. "VALUE,VALUE" line.long 0x4 "RGX_CR_TIMER_1,This register contains the value of a 48-bit internal timer. The timer runs continuously. and wraps at the top end. It counts 256 cycles at the core clock frequency. This means that at 100 MHz: 1 count value = 1/100MHz = 256 * 10 * 10^-9.." bitfld.long 0x4 31. "BIT31,BIT31" "0,1" newline hexmask.long.word 0x4 16.--30. 1. "Reserved_48,Reserved_48" newline hexmask.long.word 0x4 0.--15. 1. "VALUE,VALUE" group.long 0x168++0x7 line.long 0x0 "RGX_CR_AXI_EXACCESS_0,AXI exclusive access enable register" hexmask.long 0x0 1.--31. 1. "Reserved_1,Reserved_1" newline bitfld.long 0x0 0. "SOCIF_ENABLE,enable the exclusive access logic in the socif img_axi2img. vhd module" "0,1" line.long 0x4 "RGX_CR_AXI_EXACCESS_1,AXI exclusive access enable register" hexmask.long 0x4 0.--31. 1. "Reserved_1,Reserved_1" group.long 0x190++0x17 line.long 0x0 "RGX_CR_PM_TASK_MLIST_LOAD_0,This register is part of the parameter management. which controls the allocation and de-allocation of memory for the 3D display list (parameters). The MLIST is the list of Pages which have been allocated to thew MMU. to map.." hexmask.long 0x0 1.--31. 1. "Reserved_1,Reserved_1" newline bitfld.long 0x0 0. "PENDING,A write to this register will cause the MLIST pointer to be loaded from either PM_MLIST0_START_OF or PM_MLIST1_START_OF depending upon the Context ID contained in PM_CONTEXT_ID_MLS_LS. A read to this register return '1' until this operation has.." "0,1" line.long 0x4 "RGX_CR_PM_TASK_MLIST_LOAD_1,This register is part of the parameter management. which controls the allocation and de-allocation of memory for the 3D display list (parameters). The MLIST is the list of Pages which have been allocated to thew MMU. to map.." hexmask.long 0x4 0.--31. 1. "Reserved_1,Reserved_1" line.long 0x8 "RGX_CR_PM_TASK_MLIST_CLEAR_0,This register is part of the parameter management. which controls the allocation and de-allocation of memory for the 3D display list (parameters). The MLIST is the list of Pages which have been allocated to thew MMU. to map.." hexmask.long 0x8 1.--31. 1. "Reserved_1,Reserved_1" newline bitfld.long 0x8 0. "PENDING,A write to this register will cause the MLIST pointer to be reset to 0. A read to this register return '1' until this operation has completed." "0,1" line.long 0xC "RGX_CR_PM_TASK_MLIST_CLEAR_1,This register is part of the parameter management. which controls the allocation and de-allocation of memory for the 3D display list (parameters). The MLIST is the list of Pages which have been allocated to thew MMU. to map.." hexmask.long 0xC 0.--31. 1. "Reserved_1,Reserved_1" line.long 0x10 "RGX_CR_PM_TA_MAX_RENDER_TARGET_0,This register is deprecated and has no function." hexmask.long.tbyte 0x10 11.--31. 1. "Reserved_11,Reserved_11" newline hexmask.long.word 0x10 0.--10. 1. "ID,If used the software should program this with the maximum render target array index used within the Scene" line.long 0x14 "RGX_CR_PM_TA_MAX_RENDER_TARGET_1,This register is deprecated and has no function." hexmask.long 0x14 0.--31. 1. "Reserved_11,Reserved_11" rgroup.long 0x1A8++0x7 line.long 0x0 "RGX_CR_PM_MTILE_ARRAY_REORDER_VALID_STATUS_0,This register is deprecated and has no function." hexmask.long 0x0 1.--31. 1. "Reserved_1,Reserved_1" newline bitfld.long 0x0 0. "OP,OP" "0,1" line.long 0x4 "RGX_CR_PM_MTILE_ARRAY_REORDER_VALID_STATUS_1,This register is deprecated and has no function." hexmask.long 0x4 0.--31. 1. "Reserved_1,Reserved_1" group.long 0x1B0++0x1F line.long 0x0 "RGX_CR_PM_EMPTY_PAGE_FAST_FREEING_0,This register is part of the parameter management. which controls the allocation and de-allocation of memory for the 3D display list (parameters). This register enables an optimisation which causes pages which have.." hexmask.long 0x0 1.--31. 1. "Reserved_1,Reserved_1" newline bitfld.long 0x0 0. "ID,When set enable freeing of unused pages during TA phase" "0,1" line.long 0x4 "RGX_CR_PM_EMPTY_PAGE_FAST_FREEING_1,This register is part of the parameter management. which controls the allocation and de-allocation of memory for the 3D display list (parameters). This register enables an optimisation which causes pages which have.." hexmask.long 0x4 0.--31. 1. "Reserved_1,Reserved_1" line.long 0x8 "RGX_CR_PM_MMU_REMAP_PENDING_0,This register is part of the parameter management. which controls the allocation and de-allocation of memory for the 3D display list (parameters). This register starts the process of remapping the remaining physical pages at.." hexmask.long 0x8 1.--31. 1. "Reserved_1,Reserved_1" newline bitfld.long 0x8 0. "OP,Pending status register corresponding to the MMU remapping operation it will become '1' when written and deassert when the operation complete." "0,1" line.long 0xC "RGX_CR_PM_MMU_REMAP_PENDING_1,This register is part of the parameter management. which controls the allocation and de-allocation of memory for the 3D display list (parameters). This register starts the process of remapping the remaining physical pages at.." hexmask.long 0xC 0.--31. 1. "Reserved_1,Reserved_1" line.long 0x10 "RGX_CR_PM_PBE_FORCE_FREEING_0,This register is part of the parameter management. which controls the allocation and de-allocation of memory for the 3D display list (parameters). Normally freeing of memory is associated with macrotiles (a portion of the.." hexmask.long 0x10 1.--31. 1. "Reserved_1,Reserved_1" newline bitfld.long 0x10 0. "ENABLE,When this bit is set PM will free all the 3D context Memory when a genuine pixelbe end of render is received." "0,1" line.long 0x14 "RGX_CR_PM_PBE_FORCE_FREEING_1,This register is part of the parameter management. which controls the allocation and de-allocation of memory for the 3D display list (parameters). Normally freeing of memory is associated with macrotiles (a portion of the.." hexmask.long 0x14 0.--31. 1. "Reserved_1,Reserved_1" line.long 0x18 "RGX_CR_PM_PDS_STARTOF_MTILEFREE_0,RGX_CR_PM_PDS_STARTOF_MTILEFREE_0" hexmask.long.word 0x18 17.--31. 1. "Reserved_17,Reserved_17" newline hexmask.long.tbyte 0x18 0.--16. 1. "OP,This startof register indicates the macrotile number of the PDSs current macrotile free request needs to be programmed by FW on a render start" line.long 0x1C "RGX_CR_PM_PDS_STARTOF_MTILEFREE_1,RGX_CR_PM_PDS_STARTOF_MTILEFREE_1" hexmask.long 0x1C 0.--31. 1. "Reserved_17,Reserved_17" group.long 0x200++0x1F line.long 0x0 "RGX_CR_PM_TASK_3D_FREE_LOAD_0,RGX_CR_PM_TASK_3D_FREE_LOAD_0" hexmask.long 0x0 1.--31. 1. "Reserved_1,Reserved_1" newline bitfld.long 0x0 0. "PENDING,A write into this register will cause the 3D free list context to be loaded from the relevant configuration registers" "0,1" line.long 0x4 "RGX_CR_PM_TASK_3D_FREE_LOAD_1,RGX_CR_PM_TASK_3D_FREE_LOAD_1" hexmask.long 0x4 0.--31. 1. "Reserved_1,Reserved_1" line.long 0x8 "RGX_CR_PM_TASK_TA_FREE_LOAD_0,RGX_CR_PM_TASK_TA_FREE_LOAD_0" hexmask.long 0x8 1.--31. 1. "Reserved_1,Reserved_1" newline bitfld.long 0x8 0. "PENDING,A write into this register will cause the TA free list context to be loaded from the relevant configuration registers" "0,1" line.long 0xC "RGX_CR_PM_TASK_TA_FREE_LOAD_1,RGX_CR_PM_TASK_TA_FREE_LOAD_1" hexmask.long 0xC 0.--31. 1. "Reserved_1,Reserved_1" line.long 0x10 "RGX_CR_PM_TA_FSTACK_BASE_0,Effective on load TA context. this register defines the base address of the free list stack being referenced during TA processing." hexmask.long 0x10 4.--31. 1. "ADDR,1TB Addressable 128 bits aligned Base Address for TA context page tables in the DPM module" newline hexmask.long.byte 0x10 0.--3. 1. "Reserved_0,Reserved_0" line.long 0x14 "RGX_CR_PM_TA_FSTACK_BASE_1,Effective on load TA context. this register defines the base address of the free list stack being referenced during TA processing." hexmask.long.tbyte 0x14 8.--31. 1. "Reserved_40,Reserved_40" newline hexmask.long.byte 0x14 0.--7. 1. "ADDR,1TB Addressable 128 bits aligned Base Address for TA context page tables in the DPM module" line.long 0x18 "RGX_CR_PM_3D_FSTACK_BASE_0,Effective on load 3D context. this register defines the base address of the free list table being referenced in the process of de-allocating pages during a 3D render." hexmask.long 0x18 4.--31. 1. "ADDR,1TB Addressable 128 bits aligned Base Address for 3D context page tables in the DPM module" newline hexmask.long.byte 0x18 0.--3. 1. "Reserved_0,Reserved_0" line.long 0x1C "RGX_CR_PM_3D_FSTACK_BASE_1,Effective on load 3D context. this register defines the base address of the free list table being referenced in the process of de-allocating pages during a 3D render." hexmask.long.tbyte 0x1C 8.--31. 1. "Reserved_40,Reserved_40" newline hexmask.long.byte 0x1C 0.--7. 1. "ADDR,1TB Addressable 128 bits aligned Base Address for 3D context page tables in the DPM module" repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) group.long ($2+0x220)++0x3 line.long 0x0 "RGX_CR_PM_TA_FSTACK_$1,Note: each 16GB 4KB addressable page (22 bits) is rounded to dword aligned" hexmask.long.word 0x0 22.--31. 1. "Reserved_22,Reserved_22" newline hexmask.long.tbyte 0x0 0.--21. 1. "SIZE,This register defines the number of 4K pages in the free list stack used for the TA page allocation effective on a load TA context." repeat.end group.long 0x230++0x7 line.long 0x0 "RGX_CR_PM_3D_FSTACK_0,Note: each 16GB 4KB addressable page (22 bits) is rounded to dword aligned" hexmask.long.word 0x0 22.--31. 1. "STARTOF_TOP,This register defines the head pointer of the free list in terms of 4K free pages in the free list stack effective on a load TA context." newline hexmask.long.tbyte 0x0 0.--21. 1. "SIZE,This register defines the number of 4K pages in the free list stack used for the TA page allocation effective on a load TA context." line.long 0x4 "RGX_CR_PM_3D_FSTACK_1,Note: each 16GB 4KB addressable page (22 bits) is rounded to dword aligned" hexmask.long.tbyte 0x4 12.--31. 1. "Reserved_44,Reserved_44" newline hexmask.long.word 0x4 0.--11. 1. "STARTOF_TOP,This register defines the head pointer of the free list in terms of 4K free pages in the free list stack effective on a load TA context." group.long 0x240++0x2F line.long 0x0 "RGX_CR_PM_MTILE_ARRAY_0,Effective Immediately." hexmask.long 0x0 4.--31. 1. "BASE_ADDR,1TB Addressable 128 bits aligned Base Address for Mtile Array Base" newline hexmask.long.byte 0x0 0.--3. 1. "Reserved_0,Reserved_0" line.long 0x4 "RGX_CR_PM_MTILE_ARRAY_1,Effective Immediately." hexmask.long.tbyte 0x4 8.--31. 1. "Reserved_40,Reserved_40" newline hexmask.long.byte 0x4 0.--7. 1. "BASE_ADDR,1TB Addressable 128 bits aligned Base Address for Mtile Array Base" line.long 0x8 "RGX_CR_PM_VHEAP_TABLE_0,Effective immediately. this register defines the base address of the virtual heap table information. The size of the Virtual Heap needs to be no smaller than PM_VHEAP_TABLE_SIZE Dwords." hexmask.long 0x8 4.--31. 1. "BASE_ADDR,1TB Addressable 128 bits aligned Base Address for Virtual Heap Table" newline hexmask.long.byte 0x8 0.--3. 1. "Reserved_0,Reserved_0" line.long 0xC "RGX_CR_PM_VHEAP_TABLE_1,Effective immediately. this register defines the base address of the virtual heap table information. The size of the Virtual Heap needs to be no smaller than PM_VHEAP_TABLE_SIZE Dwords." hexmask.long.tbyte 0xC 8.--31. 1. "Reserved_40,Reserved_40" newline hexmask.long.byte 0xC 0.--7. 1. "BASE_ADDR,1TB Addressable 128 bits aligned Base Address for Virtual Heap Table" line.long 0x10 "RGX_CR_PM_TASK_VHEAP_LOAD_0,RGX_CR_PM_TASK_VHEAP_LOAD_0" hexmask.long 0x10 1.--31. 1. "Reserved_1,Reserved_1" newline bitfld.long 0x10 0. "PENDING,Causes the vheap to be loaded as specified by the relevant configuration registers when it is done the hw will clear this bit" "0,1" line.long 0x14 "RGX_CR_PM_TASK_VHEAP_LOAD_1,RGX_CR_PM_TASK_VHEAP_LOAD_1" hexmask.long 0x14 0.--31. 1. "Reserved_1,Reserved_1" line.long 0x18 "RGX_CR_PM_TASK_VHEAP_CLEAR_0,RGX_CR_PM_TASK_VHEAP_CLEAR_0" hexmask.long 0x18 1.--31. 1. "Reserved_1,Reserved_1" newline bitfld.long 0x18 0. "PENDING,Causes the vheap to be cleared as specified by the relevant configuration registers. When it is done the hw will clear this bit" "0,1" line.long 0x1C "RGX_CR_PM_TASK_VHEAP_CLEAR_1,RGX_CR_PM_TASK_VHEAP_CLEAR_1" hexmask.long 0x1C 0.--31. 1. "Reserved_1,Reserved_1" line.long 0x20 "RGX_CR_PM_TASK_VHEAP_STORE_0,RGX_CR_PM_TASK_VHEAP_STORE_0" hexmask.long 0x20 1.--31. 1. "Reserved_1,Reserved_1" newline bitfld.long 0x20 0. "PENDING,Causes the vheap to be stored as specified by the relevant configuration registers. When it is done the hw will clear this bit" "0,1" line.long 0x24 "RGX_CR_PM_TASK_VHEAP_STORE_1,RGX_CR_PM_TASK_VHEAP_STORE_1" hexmask.long 0x24 0.--31. 1. "Reserved_1,Reserved_1" line.long 0x28 "RGX_CR_PM_ALIST0_START_OF_0,start pointer of the allocation list tail.in size of 8 bytes" hexmask.long 0x28 0.--31. 1. "TAIL,allocation List 0 tail pointer" line.long 0x2C "RGX_CR_PM_ALIST0_START_OF_1,start pointer of the allocation list tail.in size of 8 bytes" hexmask.long 0x2C 1.--31. 1. "Reserved_33,Reserved_33" newline bitfld.long 0x2C 0. "TAIL,allocation List 0 tail pointer" "0,1" rgroup.long 0x270++0x7 line.long 0x0 "RGX_CR_PM_ALIST0_STATUS_0,pointer of current allocation list.in size of 8 bytes" hexmask.long 0x0 0.--31. 1. "TAIL,allocation List tail pointer" line.long 0x4 "RGX_CR_PM_ALIST0_STATUS_1,pointer of current allocation list.in size of 8 bytes" hexmask.long 0x4 1.--31. 1. "Reserved_33,Reserved_33" newline bitfld.long 0x4 0. "TAIL,allocation List tail pointer" "0,1" group.long 0x278++0x7 line.long 0x0 "RGX_CR_PM_ALIST1_START_OF_0,start of the tail pointer of current allocation list.effecitve on an allocation_list_load" hexmask.long 0x0 0.--31. 1. "TAIL,start of the allocation list tail pointer" line.long 0x4 "RGX_CR_PM_ALIST1_START_OF_1,start of the tail pointer of current allocation list.effecitve on an allocation_list_load" hexmask.long 0x4 1.--31. 1. "Reserved_33,Reserved_33" newline bitfld.long 0x4 0. "TAIL,start of the allocation list tail pointer" "0,1" rgroup.long 0x280++0x7 line.long 0x0 "RGX_CR_PM_ALIST1_STATUS_0,pointer of current allocation list.in size of 8 bytes" hexmask.long 0x0 0.--31. 1. "TAIL,allocation List tail pointer" line.long 0x4 "RGX_CR_PM_ALIST1_STATUS_1,pointer of current allocation list.in size of 8 bytes" hexmask.long 0x4 1.--31. 1. "Reserved_33,Reserved_33" newline bitfld.long 0x4 0. "TAIL,allocation List tail pointer" "0,1" group.long 0x288++0x1F line.long 0x0 "RGX_CR_PM_TASK_ALIST_LOAD_0,RGX_CR_PM_TASK_ALIST_LOAD_0" hexmask.long 0x0 1.--31. 1. "Reserved_1,Reserved_1" newline bitfld.long 0x0 0. "PENDING,the write to this register will cause allocation list to be loaded from the relevant configuration registers" "0,1" line.long 0x4 "RGX_CR_PM_TASK_ALIST_LOAD_1,RGX_CR_PM_TASK_ALIST_LOAD_1" hexmask.long 0x4 0.--31. 1. "Reserved_1,Reserved_1" line.long 0x8 "RGX_CR_PM_TASK_ALIST_CLEAR_0,RGX_CR_PM_TASK_ALIST_CLEAR_0" hexmask.long 0x8 1.--31. 1. "Reserved_1,Reserved_1" newline bitfld.long 0x8 0. "PENDING,the write to this register will causes the allocation list to be cleard from the relevant configuration registers" "0,1" line.long 0xC "RGX_CR_PM_TASK_ALIST_CLEAR_1,RGX_CR_PM_TASK_ALIST_CLEAR_1" hexmask.long 0xC 0.--31. 1. "Reserved_1,Reserved_1" line.long 0x10 "RGX_CR_PM_DEALLOCATION_STARTOF_MASK_0,RGX_CR_PM_DEALLOCATION_STARTOF_MASK_0" hexmask.long.word 0x10 16.--31. 1. "Reserved_16,Reserved_16" newline hexmask.long.word 0x10 0.--15. 1. "OP,This is the start of the mask PM deallocation will be based on. Normally it is 0. However in ISP context resume or extra 3D timeout case the driver has to programme the value from the previous render." line.long 0x14 "RGX_CR_PM_DEALLOCATION_STARTOF_MASK_1,RGX_CR_PM_DEALLOCATION_STARTOF_MASK_1" hexmask.long 0x14 0.--31. 1. "Reserved_16,Reserved_16" line.long 0x18 "RGX_CR_PM_PAGE_MANAGEOP_0,RGX_CR_PM_PAGE_MANAGEOP_0" hexmask.long 0x18 3.--31. 1. "Reserved_3,Reserved_3" newline bitfld.long 0x18 2. "COMBINE_DALLOC,1 means the PM writes to the free stack will be burst combined" "0,1" newline bitfld.long 0x18 1. "DISABLE_DALLOC,1 means the PM page management deallocation operation will be disabled" "0,1" newline bitfld.long 0x18 0. "DISABLE_ALLOC,1 means the PM page management allocation operation will be disabled" "0,1" line.long 0x1C "RGX_CR_PM_PAGE_MANAGEOP_1,RGX_CR_PM_PAGE_MANAGEOP_1" hexmask.long 0x1C 0.--31. 1. "Reserved_3,Reserved_3" rgroup.long 0x2A8++0x7 line.long 0x0 "RGX_CR_PM_PAGE_MANAGEOP_STATUS_0,RGX_CR_PM_PAGE_MANAGEOP_STATUS_0" hexmask.long 0x0 2.--31. 1. "Reserved_2,Reserved_2" newline bitfld.long 0x0 1. "DALLOC_DISABLED,1 means the PM page management operation has been disabled" "0,1" newline bitfld.long 0x0 0. "ALLOC_DISABLED,1 means the PM page management operation has been disabled" "0,1" line.long 0x4 "RGX_CR_PM_PAGE_MANAGEOP_STATUS_1,RGX_CR_PM_PAGE_MANAGEOP_STATUS_1" hexmask.long 0x4 0.--31. 1. "Reserved_2,Reserved_2" group.long 0x2B0++0xF line.long 0x0 "RGX_CR_PM_CONTEXT_PB_BASE_0,RGX_CR_PM_CONTEXT_PB_BASE_0" hexmask.long 0x0 3.--31. 1. "Reserved_3,Reserved_3" newline bitfld.long 0x0 0.--2. "CMP,Defines whether the TA/3D/HOST contexts are using the same parameter buffer. Setting a bit to '1' indicates that the context is using a different parameter buffer. Bit 0 = 0 : Unified Free List 3D context Parameter buffer = Unified Free List TA.." "MMU Free List 3D context Parameter buffer = MMU..,?,?,?,?,?,?,?" line.long 0x4 "RGX_CR_PM_CONTEXT_PB_BASE_1,RGX_CR_PM_CONTEXT_PB_BASE_1" hexmask.long 0x4 0.--31. 1. "Reserved_3,Reserved_3" line.long 0x8 "RGX_CR_PM_MLIST0_START_OF_0,start value of the mlist tail @ the loading of the context. in size of 4 bytes. stride is 64KB" hexmask.long.word 0x8 22.--31. 1. "Reserved_22,Reserved_22" newline hexmask.long.tbyte 0x8 0.--21. 1. "TAIL,allocation List 0 tail pointer" line.long 0xC "RGX_CR_PM_MLIST0_START_OF_1,start value of the mlist tail @ the loading of the context. in size of 4 bytes. stride is 64KB" hexmask.long 0xC 0.--31. 1. "Reserved_22,Reserved_22" rgroup.long 0x2C0++0x7 line.long 0x0 "RGX_CR_PM_MLIST0_STATUS_0,pointer of current mmu allocation list.in size of 4 bytes. stride is 64KB" hexmask.long.word 0x0 22.--31. 1. "Reserved_22,Reserved_22" newline hexmask.long.tbyte 0x0 0.--21. 1. "TAIL,allocation List 1 tail pointer" line.long 0x4 "RGX_CR_PM_MLIST0_STATUS_1,pointer of current mmu allocation list.in size of 4 bytes. stride is 64KB" hexmask.long 0x4 0.--31. 1. "Reserved_22,Reserved_22" group.long 0x2C8++0x7 line.long 0x0 "RGX_CR_PM_MLIST1_START_OF_0,start of the tail pointer of mmu allocation list.effecitve on an allocation_list_load" hexmask.long.word 0x0 22.--31. 1. "Reserved_22,Reserved_22" newline hexmask.long.tbyte 0x0 0.--21. 1. "TAIL,start of the allocation list 1 tail pointer" line.long 0x4 "RGX_CR_PM_MLIST1_START_OF_1,start of the tail pointer of mmu allocation list.effecitve on an allocation_list_load" hexmask.long 0x4 0.--31. 1. "Reserved_22,Reserved_22" rgroup.long 0x2D0++0x7 line.long 0x0 "RGX_CR_PM_MLIST1_STATUS_0,pointer of mmu allocation list1 pointer.in size of 4 bytes" hexmask.long.word 0x0 22.--31. 1. "Reserved_22,Reserved_22" newline hexmask.long.tbyte 0x0 0.--21. 1. "TAIL,mmu allocation List 1 tail pointer" line.long 0x4 "RGX_CR_PM_MLIST1_STATUS_1,pointer of mmu allocation list1 pointer.in size of 4 bytes" hexmask.long 0x4 0.--31. 1. "Reserved_22,Reserved_22" group.long 0x2D8++0xF line.long 0x0 "RGX_CR_PM_MLIST0_BASE_0,This register defines the base address of the mmu list 0 for the mmu pages. the stride has to be 64KBytes" hexmask.long 0x0 4.--31. 1. "ADDR,1TB Addressable 128 bits aligned Base Address for mmu list0 module Effective Immediately" newline hexmask.long.byte 0x0 0.--3. 1. "Reserved_0,Reserved_0" line.long 0x4 "RGX_CR_PM_MLIST0_BASE_1,This register defines the base address of the mmu list 0 for the mmu pages. the stride has to be 64KBytes" hexmask.long.tbyte 0x4 8.--31. 1. "Reserved_40,Reserved_40" newline hexmask.long.byte 0x4 0.--7. 1. "ADDR,1TB Addressable 128 bits aligned Base Address for mmu list0 module Effective Immediately" line.long 0x8 "RGX_CR_PM_MLIST1_BASE_0,This register defines the base address of the mmu list 1 for the mmu pages. the stride has to be a 64KBytes" hexmask.long 0x8 4.--31. 1. "ADDR,1TB Addressable 128 bits aligned Base Address for mmu list1 module Effective Immediately" newline hexmask.long.byte 0x8 0.--3. 1. "Reserved_0,Reserved_0" line.long 0xC "RGX_CR_PM_MLIST1_BASE_1,This register defines the base address of the mmu list 1 for the mmu pages. the stride has to be a 64KBytes" hexmask.long.tbyte 0xC 8.--31. 1. "Reserved_40,Reserved_40" newline hexmask.long.byte 0xC 0.--7. 1. "ADDR,1TB Addressable 128 bits aligned Base Address for mmu list1 module Effective Immediately" rgroup.long 0x2F8++0x27 line.long 0x0 "RGX_CR_PM_VCE_VTOP_STATUS_0,RGX_CR_PM_VCE_VTOP_STATUS_0" hexmask.long.word 0x0 20.--31. 1. "Reserved_20,Reserved_20" newline hexmask.long.tbyte 0x0 0.--19. 1. "OP,Virtual Page Pointer for the VCE 16KB granauality" line.long 0x4 "RGX_CR_PM_VCE_VTOP_STATUS_1,RGX_CR_PM_VCE_VTOP_STATUS_1" hexmask.long 0x4 0.--31. 1. "Reserved_20,Reserved_20" line.long 0x8 "RGX_CR_PM_TE_VTOP_STATUS_0,RGX_CR_PM_TE_VTOP_STATUS_0" hexmask.long.word 0x8 20.--31. 1. "Reserved_20,Reserved_20" newline hexmask.long.tbyte 0x8 0.--19. 1. "OP,Virtual Page Pointer for the TE 16KB granauality" line.long 0xC "RGX_CR_PM_TE_VTOP_STATUS_1,RGX_CR_PM_TE_VTOP_STATUS_1" hexmask.long 0xC 0.--31. 1. "Reserved_20,Reserved_20" line.long 0x10 "RGX_CR_PM_OUTOF_MEM_SRC_0,RGX_CR_PM_OUTOF_MEM_SRC_0" hexmask.long 0x10 3.--31. 1. "Reserved_3,Reserved_3" newline bitfld.long 0x10 0.--2. "OP,one hot encoding indicating which part of resource runs out of memory bit 0: normal ta free list bit 1: unified ta free list bit 2: mmu free list" "normal ta free list,unified ta free list,mmu free list,?,?,?,?,?" line.long 0x14 "RGX_CR_PM_OUTOF_MEM_SRC_1,RGX_CR_PM_OUTOF_MEM_SRC_1" hexmask.long 0x14 0.--31. 1. "Reserved_3,Reserved_3" line.long 0x18 "RGX_CR_PM_ALIST_VTOP_STATUS_0,RGX_CR_PM_ALIST_VTOP_STATUS_0" hexmask.long.word 0x18 20.--31. 1. "Reserved_20,Reserved_20" newline hexmask.long.tbyte 0x18 0.--19. 1. "OP,Virtual Page Pointer for the allocation list 16KB granauality" line.long 0x1C "RGX_CR_PM_ALIST_VTOP_STATUS_1,RGX_CR_PM_ALIST_VTOP_STATUS_1" hexmask.long 0x1C 0.--31. 1. "Reserved_20,Reserved_20" line.long 0x20 "RGX_CR_PM_MMU_VTOP_STATUS_0,RGX_CR_PM_MMU_VTOP_STATUS_0" hexmask.long.word 0x20 20.--31. 1. "Reserved_20,Reserved_20" newline hexmask.long.tbyte 0x20 0.--19. 1. "OP,Virtual Page Pointer for the MMU 4KB granauality" line.long 0x24 "RGX_CR_PM_MMU_VTOP_STATUS_1,RGX_CR_PM_MMU_VTOP_STATUS_1" hexmask.long 0x24 0.--31. 1. "Reserved_20,Reserved_20" wgroup.long 0x320++0xF line.long 0x0 "RGX_CR_PM_OUTOFMEM_ABORTALL_0,RGX_CR_PM_OUTOFMEM_ABORTALL_0" hexmask.long 0x0 1.--31. 1. "Reserved_1,Reserved_1" newline bitfld.long 0x0 0. "OP,Instruct the PM to Deny the TE allocation outstanding on Out Of Memory" "0,1" line.long 0x4 "RGX_CR_PM_OUTOFMEM_ABORTALL_1,RGX_CR_PM_OUTOFMEM_ABORTALL_1" hexmask.long 0x4 0.--31. 1. "Reserved_1,Reserved_1" line.long 0x8 "RGX_CR_PM_OUTOFMEM_RESTART_0,RGX_CR_PM_OUTOFMEM_RESTART_0" hexmask.long 0x8 1.--31. 1. "Reserved_1,Reserved_1" newline bitfld.long 0x8 0. "OP,Restart the PM after an Out of Memory and Abort sequence" "0,1" line.long 0xC "RGX_CR_PM_OUTOFMEM_RESTART_1,RGX_CR_PM_OUTOFMEM_RESTART_1" hexmask.long 0xC 0.--31. 1. "Reserved_1,Reserved_1" rgroup.long 0x330++0x7 line.long 0x0 "RGX_CR_PM_REQUESTING_SOURCE_0,RGX_CR_PM_REQUESTING_SOURCE_0" hexmask.long 0x0 2.--31. 1. "Reserved_2,Reserved_2" newline bitfld.long 0x0 0.--1. "OP,Requesting source when out of memory. Bit 1 : VCE Bit 0 : TE" "TE,VCE,?,?" line.long 0x4 "RGX_CR_PM_REQUESTING_SOURCE_1,RGX_CR_PM_REQUESTING_SOURCE_1" hexmask.long 0x4 0.--31. 1. "Reserved_2,Reserved_2" group.long 0x338++0xF line.long 0x0 "RGX_CR_PM_PARTIAL_RENDER_ENABLE_0,RGX_CR_PM_PARTIAL_RENDER_ENABLE_0" hexmask.long 0x0 1.--31. 1. "Reserved_1,Reserved_1" newline bitfld.long 0x0 0. "OP,Partial Render Enable Bit" "0,1" line.long 0x4 "RGX_CR_PM_PARTIAL_RENDER_ENABLE_1,RGX_CR_PM_PARTIAL_RENDER_ENABLE_1" hexmask.long 0x4 0.--31. 1. "Reserved_1,Reserved_1" line.long 0x8 "RGX_CR_PM_3D_DEALLOCATE_SCANMODE_0,RGX_CR_PM_3D_DEALLOCATE_SCANMODE_0" hexmask.long 0x8 5.--31. 1. "Reserved_5,Reserved_5" newline hexmask.long.byte 0x8 0.--4. 1. "OP,This register defines the deallocation behaviour of the PM: value > 2 is only for debug on ZLS mode 0 it can only set less than 2 0: PM will free the macrotile memory as soon as it is possible 1: PM only free one mtile for each traverse 2: PM only.." line.long 0xC "RGX_CR_PM_3D_DEALLOCATE_SCANMODE_1,RGX_CR_PM_3D_DEALLOCATE_SCANMODE_1" hexmask.long 0xC 0.--31. 1. "Reserved_5,Reserved_5" rgroup.long 0x348++0xF line.long 0x0 "RGX_CR_PM_TA_FSTACK_STATUS_0,Note: this is the pointer pointing to the TA free stack top. (4KB page pointer)" hexmask.long.word 0x0 22.--31. 1. "Reserved_22,Reserved_22" newline hexmask.long.tbyte 0x0 0.--21. 1. "TOP,This status register indicated the ta context free list pointer status." line.long 0x4 "RGX_CR_PM_TA_FSTACK_STATUS_1,Note: this is the pointer pointing to the TA free stack top. (4KB page pointer)" hexmask.long 0x4 0.--31. 1. "Reserved_22,Reserved_22" line.long 0x8 "RGX_CR_PM_3D_FSTACK_STATUS_0,Note: this is the pointer pointing to the 3D free stack top. (4KB page pointer)" hexmask.long.word 0x8 22.--31. 1. "Reserved_22,Reserved_22" newline hexmask.long.tbyte 0x8 0.--21. 1. "TOP,This status register indicated the 3D context free list status" line.long 0xC "RGX_CR_PM_3D_FSTACK_STATUS_1,Note: this is the pointer pointing to the 3D free stack top. (4KB page pointer)" hexmask.long 0xC 0.--31. 1. "Reserved_22,Reserved_22" group.long 0x358++0x7 line.long 0x0 "RGX_CR_PM_RESERVE_PAGES_0,RGX_CR_PM_RESERVE_PAGES_0" hexmask.long.word 0x0 16.--31. 1. "Reserved_16,Reserved_16" newline hexmask.long.word 0x0 0.--15. 1. "OP,This register defines the guard page required for one VCE/TE allocation. The requirement is set by the number of ppages needed to create the ALIST nodes when a vpage is closed. The MMU requirement is fixed at 3 ppages max for creatig a new ALIST.." line.long 0x4 "RGX_CR_PM_RESERVE_PAGES_1,RGX_CR_PM_RESERVE_PAGES_1" hexmask.long 0x4 0.--31. 1. "Reserved_16,Reserved_16" rgroup.long 0x360++0x17 line.long 0x0 "RGX_CR_PM_DEALLOCATED_MASK_STATUS_0,RGX_CR_PM_DEALLOCATED_MASK_STATUS_0" hexmask.long.word 0x0 16.--31. 1. "Reserved_16,Reserved_16" newline hexmask.long.word 0x0 0.--15. 1. "TOP,This status register contains a bitmask of the macrotiles freed at this point in the render" line.long 0x4 "RGX_CR_PM_DEALLOCATED_MASK_STATUS_1,RGX_CR_PM_DEALLOCATED_MASK_STATUS_1" hexmask.long 0x4 0.--31. 1. "Reserved_16,Reserved_16" line.long 0x8 "RGX_CR_PM_DEALLOCATING_MASK_STATUS_0,RGX_CR_PM_DEALLOCATING_MASK_STATUS_0" hexmask.long.word 0x8 16.--31. 1. "Reserved_16,Reserved_16" newline hexmask.long.word 0x8 0.--15. 1. "TOP,This status register indicates the mtile mask being freed at the current traverse" line.long 0xC "RGX_CR_PM_DEALLOCATING_MASK_STATUS_1,RGX_CR_PM_DEALLOCATING_MASK_STATUS_1" hexmask.long 0xC 0.--31. 1. "Reserved_16,Reserved_16" line.long 0x10 "RGX_CR_PM_PDS_MTILEFREE_STATUS_0,RGX_CR_PM_PDS_MTILEFREE_STATUS_0" hexmask.long.word 0x10 17.--31. 1. "Reserved_17,Reserved_17" newline hexmask.long.tbyte 0x10 0.--16. 1. "OP,This status register indicates the macrotile number of the PDSs current macrotile free request" line.long 0x14 "RGX_CR_PM_PDS_MTILEFREE_STATUS_1,RGX_CR_PM_PDS_MTILEFREE_STATUS_1" hexmask.long 0x14 0.--31. 1. "Reserved_17,Reserved_17" group.long 0x378++0x7 line.long 0x0 "RGX_CR_PM_TA_FREE_CONTEXT_0,RGX_CR_PM_TA_FREE_CONTEXT_0" hexmask.long 0x0 1.--31. 1. "Reserved_1,Reserved_1" newline bitfld.long 0x0 0. "PENDING,free the ta context register operation" "0,1" line.long 0x4 "RGX_CR_PM_TA_FREE_CONTEXT_1,RGX_CR_PM_TA_FREE_CONTEXT_1" hexmask.long 0x4 0.--31. 1. "Reserved_1,Reserved_1" wgroup.long 0x380++0x7 line.long 0x0 "RGX_CR_PM_3D_TIMEOUT_NOW_0,RGX_CR_PM_3D_TIMEOUT_NOW_0" hexmask.long 0x0 1.--31. 1. "Reserved_1,Reserved_1" newline bitfld.long 0x0 0. "OP,free the 3D context" "0,1" line.long 0x4 "RGX_CR_PM_3D_TIMEOUT_NOW_1,RGX_CR_PM_3D_TIMEOUT_NOW_1" hexmask.long 0x4 0.--31. 1. "Reserved_1,Reserved_1" group.long 0x388++0x7 line.long 0x0 "RGX_CR_PM_3D_DEALLOCATE_ENABLE_0,RGX_CR_PM_3D_DEALLOCATE_ENABLE_0" hexmask.long 0x0 1.--31. 1. "Reserved_1,Reserved_1" newline bitfld.long 0x0 0. "OP,3D deallocate enable mode" "0,1" line.long 0x4 "RGX_CR_PM_3D_DEALLOCATE_ENABLE_1,RGX_CR_PM_3D_DEALLOCATE_ENABLE_1" hexmask.long 0x4 0.--31. 1. "Reserved_1,Reserved_1" repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) group.long ($2+0x390)++0x3 line.long 0x0 "RGX_CR_PM_START_OF_TACONTEXT_$1,RGX_CR_PM_START_OF_TACONTEXT_0" hexmask.long.word 0x0 22.--31. 1. "Reserved_22,Reserved_22" newline hexmask.long.tbyte 0x0 0.--21. 1. "ALLOCATED_PAGE,Start of TA pages(4KB) on loading of the TA context" repeat.end repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) group.long ($2+0x398)++0x3 line.long 0x0 "RGX_CR_PM_START_OF_3DCONTEXT_$1,RGX_CR_PM_START_OF_3DCONTEXT_0" hexmask.long.word 0x0 22.--31. 1. "Reserved_22,Reserved_22" newline hexmask.long.tbyte 0x0 0.--21. 1. "ALLOCATED_PAGE,Start of 3D pages(4KB) on loading of the TA context" repeat.end rgroup.long 0x3A0++0x2F line.long 0x0 "RGX_CR_PM_TA_PAGE_STATUS_0,RGX_CR_PM_TA_PAGE_STATUS_0" hexmask.long.word 0x0 22.--31. 1. "Reserved_22,Reserved_22" newline hexmask.long.tbyte 0x0 0.--21. 1. "OP,The number of TA pages currently allocated" line.long 0x4 "RGX_CR_PM_TA_PAGE_STATUS_1,RGX_CR_PM_TA_PAGE_STATUS_1" hexmask.long 0x4 0.--31. 1. "Reserved_22,Reserved_22" line.long 0x8 "RGX_CR_PM_3D_PAGE_STATUS_0,RGX_CR_PM_3D_PAGE_STATUS_0" hexmask.long.word 0x8 22.--31. 1. "Reserved_22,Reserved_22" newline hexmask.long.tbyte 0x8 0.--21. 1. "OP,The number of 3D pages currently allocated" line.long 0xC "RGX_CR_PM_3D_PAGE_STATUS_1,RGX_CR_PM_3D_PAGE_STATUS_1" hexmask.long 0xC 0.--31. 1. "Reserved_22,Reserved_22" line.long 0x10 "RGX_CR_PM_VCE_INFLIGHT_STATUS_0,RGX_CR_PM_VCE_INFLIGHT_STATUS_0" hexmask.long.word 0x10 20.--31. 1. "Reserved_20,Reserved_20" newline hexmask.long.tbyte 0x10 0.--19. 1. "OP,The Virtual Page Number in flight in the VCE Requestor" line.long 0x14 "RGX_CR_PM_VCE_INFLIGHT_STATUS_1,RGX_CR_PM_VCE_INFLIGHT_STATUS_1" hexmask.long 0x14 0.--31. 1. "Reserved_20,Reserved_20" line.long 0x18 "RGX_CR_PM_TE_INFLIGHT_STATUS_0,RGX_CR_PM_TE_INFLIGHT_STATUS_0" hexmask.long.word 0x18 20.--31. 1. "Reserved_20,Reserved_20" newline hexmask.long.tbyte 0x18 0.--19. 1. "OP,The Virtual Page Number in flight in the TE Requestor" line.long 0x1C "RGX_CR_PM_TE_INFLIGHT_STATUS_1,RGX_CR_PM_TE_INFLIGHT_STATUS_1" hexmask.long 0x1C 0.--31. 1. "Reserved_20,Reserved_20" line.long 0x20 "RGX_CR_BIFPM_IDLE_0,RGX_CR_BIFPM_IDLE_0" hexmask.long 0x20 7.--31. 1. "Reserved_7,Reserved_7" newline bitfld.long 0x20 6. "MCU_L0_MEMIF,MCU L0 MEMIF Module IDLE" "0,1" newline bitfld.long 0x20 5. "PBE,PBE Module IDLE" "0,1" newline bitfld.long 0x20 4. "MCU_L0_PDSRW,MCU L0 PDSRW Module IDLE" "0,1" newline bitfld.long 0x20 3. "MCU_L1,MCU L1 Module IDLE" "0,1" newline bitfld.long 0x20 2. "USCS,USC Shared Module IDLE" "0,1" newline bitfld.long 0x20 1. "PM,PM Module IDLE" "0,1" newline bitfld.long 0x20 0. "BIF256,BIF256 Module IDLE" "0,1" line.long 0x24 "RGX_CR_BIFPM_IDLE_1,RGX_CR_BIFPM_IDLE_1" hexmask.long 0x24 0.--31. 1. "Reserved_7,Reserved_7" line.long 0x28 "RGX_CR_SIDEKICK_IDLE_0,RGX_CR_SIDEKICK_IDLE_0" hexmask.long 0x28 7.--31. 1. "Reserved_7,Reserved_7" newline bitfld.long 0x28 6. "FB_CDC,FB CDC Module IDLE" "0,1" newline bitfld.long 0x28 5. "MMU,MMU Module IDLE" "0,1" newline bitfld.long 0x28 4. "BIF128,BIF128 Module IDLE" "0,1" newline bitfld.long 0x28 3. "TLA,TLA Module IDLE" "0,1" newline bitfld.long 0x28 2. "GARTEN,GARTEN Module IDLE" "0,1" newline bitfld.long 0x28 1. "HOSTIF,HOSTIF Module IDLE" "0,1" newline bitfld.long 0x28 0. "SOCIF,SOCIF Module IDLE" "0,1" line.long 0x2C "RGX_CR_SIDEKICK_IDLE_1,RGX_CR_SIDEKICK_IDLE_1" hexmask.long 0x2C 0.--31. 1. "Reserved_7,Reserved_7" group.long 0x3D0++0x17 line.long 0x0 "RGX_CR_PM_CONTEXT_ID_0,RGX_CR_PM_CONTEXT_ID_0" hexmask.long.byte 0x0 25.--31. 1. "Reserved_25,Reserved_25" newline bitfld.long 0x0 24. "MLIS_ALLOC,MMU page List (TE VCE aligned with this context )Allocation Context ID" "0,1" newline hexmask.long.byte 0x0 17.--23. 1. "Reserved_17,Reserved_17" newline bitfld.long 0x0 16. "LS,Load Store Context ID for the allocation list" "0,1" newline hexmask.long.byte 0x0 9.--15. 1. "Reserved_9,Reserved_9" newline bitfld.long 0x0 8. "DALLOC,DeAllocation Context ID for the allocation list" "0,1" newline hexmask.long.byte 0x0 1.--7. 1. "Reserved_1,Reserved_1" newline bitfld.long 0x0 0. "ALLOC,Allocation Context ID for the allocation list" "0,1" line.long 0x4 "RGX_CR_PM_CONTEXT_ID_1,RGX_CR_PM_CONTEXT_ID_1" hexmask.long.tbyte 0x4 9.--31. 1. "Reserved_41,Reserved_41" newline bitfld.long 0x4 8. "MLIS_LS,MMU page List (TE VCE aligned with this context )Load Store Context ID" "0,1" newline hexmask.long.byte 0x4 1.--7. 1. "Reserved_33,Reserved_33" newline bitfld.long 0x4 0. "MLIS_DALLOC,MMU page List (TE VCE aligned with this context )DeAllocation Context ID" "0,1" line.long 0x8 "RGX_CR_PM_3D_RENDER_TARGET_INDEX_0,RGX_CR_PM_3D_RENDER_TARGET_INDEX_0" hexmask.long.tbyte 0x8 11.--31. 1. "Reserved_11,Reserved_11" newline hexmask.long.word 0x8 0.--10. 1. "ID,Render Target ID which is being rendered" line.long 0xC "RGX_CR_PM_3D_RENDER_TARGET_INDEX_1,RGX_CR_PM_3D_RENDER_TARGET_INDEX_1" hexmask.long 0xC 0.--31. 1. "Reserved_11,Reserved_11" line.long 0x10 "RGX_CR_PM_3D_RENDER_TARGET_LAST_0,RGX_CR_PM_3D_RENDER_TARGET_LAST_0" hexmask.long 0x10 1.--31. 1. "Reserved_1,Reserved_1" newline bitfld.long 0x10 0. "ID,If this bit is set this means the render will be the last one in the whole render target array. If no multiple render target array is present this bit always needs set" "0,1" line.long 0x14 "RGX_CR_PM_3D_RENDER_TARGET_LAST_1,RGX_CR_PM_3D_RENDER_TARGET_LAST_1" hexmask.long 0x14 0.--31. 1. "Reserved_1,Reserved_1" rgroup.long 0x3E8++0x17 line.long 0x0 "RGX_CR_PM_LOCK_STATUS_0,RGX_CR_PM_LOCK_STATUS_0" hexmask.long 0x0 2.--31. 1. "Reserved_2,Reserved_2" newline bitfld.long 0x0 1. "TD,Bit 1: 3D free list Lock Status. 0 idle/ 1 used" "0,1" newline bitfld.long 0x0 0. "TA,Bit 0: TA free list Lock Status. 0 idle/ 1 used." "TA free list Lock Status,?" line.long 0x4 "RGX_CR_PM_LOCK_STATUS_1,RGX_CR_PM_LOCK_STATUS_1" hexmask.long 0x4 0.--31. 1. "Reserved_2,Reserved_2" line.long 0x8 "RGX_CR_PM_LOCK_OWNER_0,RGX_CR_PM_LOCK_OWNER_0" hexmask.long 0x8 2.--31. 1. "Reserved_2,Reserved_2" newline bitfld.long 0x8 1. "TD,Bit 1 :3D free list Lock owner. 0 PMA / 1 PMD" "0,1" newline bitfld.long 0x8 0. "TA,Bit 0: TA free list Lock Owner. 0 PMA / 1 PMD." "TA free list Lock Owner,?" line.long 0xC "RGX_CR_PM_LOCK_OWNER_1,RGX_CR_PM_LOCK_OWNER_1" hexmask.long 0xC 0.--31. 1. "Reserved_2,Reserved_2" line.long 0x10 "RGX_CR_PM_IDLE_STATUS_0,RGX_CR_PM_IDLE_STATUS_0" hexmask.long.tbyte 0x10 8.--31. 1. "Reserved_8,Reserved_8" newline bitfld.long 0x10 7. "PMD_BIF,Idle Status Register of the PMD module bif state machine" "0,1" newline bitfld.long 0x10 6. "PMD_FRE,Idle Status Register of the PMD module master state machine" "0,1" newline bitfld.long 0x10 5. "BIF,Idle Status Register of the BIF Interface default" "0,1" newline bitfld.long 0x10 4. "BARB,Idle Status Register of the BIF Arbiter state BAR" "0,1" newline bitfld.long 0x10 3. "AMAN,Idle Status Register of the Alist state machine" "0,1" newline bitfld.long 0x10 2. "STA,Idle Status Register of the Stack Manager Modul" "0,1" newline bitfld.long 0x10 1. "PMD,Idle Status Register of the PMD module" "0,1" newline bitfld.long 0x10 0. "PMA,Idle Status Register of the PMA module" "0,1" line.long 0x14 "RGX_CR_PM_IDLE_STATUS_1,RGX_CR_PM_IDLE_STATUS_1" hexmask.long 0x14 0.--31. 1. "Reserved_8,Reserved_8" wgroup.long 0x400++0x7 line.long 0x0 "RGX_CR_VDM_START_0,A write of '1' to this register starts the Vertex Data Master (TA) Reading the control stream pointed to by VDM_CTRL_STREAM_BASE" hexmask.long 0x0 1.--31. 1. "Reserved_1,Reserved_1" newline bitfld.long 0x0 0. "PULSE,Start VDM" "0,1" line.long 0x4 "RGX_CR_VDM_START_1,A write of '1' to this register starts the Vertex Data Master (TA) Reading the control stream pointed to by VDM_CTRL_STREAM_BASE" hexmask.long 0x4 0.--31. 1. "Reserved_1,Reserved_1" group.long 0x408++0x7 line.long 0x0 "RGX_CR_VDM_CTRL_STREAM_BASE_0,The base address of the Vertex Data Master's Input Parameter Control Stream in external memory" hexmask.long 0x0 2.--31. 1. "ADDR,1TB range 32-bit aligned base address" newline bitfld.long 0x0 0.--1. "Reserved_0,Reserved_0" "0,1,2,3" line.long 0x4 "RGX_CR_VDM_CTRL_STREAM_BASE_1,The base address of the Vertex Data Master's Input Parameter Control Stream in external memory" hexmask.long.tbyte 0x4 8.--31. 1. "Reserved_40,Reserved_40" newline hexmask.long.byte 0x4 0.--7. 1. "ADDR,1TB range 32-bit aligned base address" rgroup.long 0x410++0x7 line.long 0x0 "RGX_CR_VDM_CTRL_STREAM_CURRENT_0,This status register reports the current position in the input parameter format of the data being processed. This is a debug register. This is NOT the fetch address presented to the BIF. which is reading ahead Since the.." hexmask.long 0x0 2.--31. 1. "ADDR,1TB range 32-bit aligned address" newline bitfld.long 0x0 0.--1. "Reserved_0,Reserved_0" "0,1,2,3" line.long 0x4 "RGX_CR_VDM_CTRL_STREAM_CURRENT_1,This status register reports the current position in the input parameter format of the data being processed. This is a debug register. This is NOT the fetch address presented to the BIF. which is reading ahead Since the.." hexmask.long.tbyte 0x4 8.--31. 1. "Reserved_40,Reserved_40" newline hexmask.long.byte 0x4 0.--7. 1. "ADDR,1TB range 32-bit aligned address" group.long 0x418++0x17 line.long 0x0 "RGX_CR_VDM_CALL_STACK_POINTER_0,The pointer to the control stream call stack. The current pointer within the VDM's call stack in external memory. The call stack is used whenever a call is made to another control stream. to store the return address.." hexmask.long 0x0 3.--31. 1. "ADDR,1TB range 64-bit aligned base address" newline bitfld.long 0x0 0.--2. "Reserved_0,Reserved_0" "0,1,2,3,4,5,6,7" line.long 0x4 "RGX_CR_VDM_CALL_STACK_POINTER_1,The pointer to the control stream call stack. The current pointer within the VDM's call stack in external memory. The call stack is used whenever a call is made to another control stream. to store the return address.." hexmask.long.tbyte 0x4 8.--31. 1. "Reserved_40,Reserved_40" newline hexmask.long.byte 0x4 0.--7. 1. "ADDR,1TB range 64-bit aligned base address" line.long 0x8 "RGX_CR_VDM_BATCH_0,The Batch number is a index list block (draw call) ID which is passed through the GPU pipeline. This is helpful for debug and performance profiling. The starting batch number should be programmed before the first TA phase of every.." hexmask.long.tbyte 0x8 14.--31. 1. "Reserved_14,Reserved_14" newline hexmask.long.word 0x8 0.--13. 1. "NUMBER,NUMBER" line.long 0xC "RGX_CR_VDM_BATCH_1,The Batch number is a index list block (draw call) ID which is passed through the GPU pipeline. This is helpful for debug and performance profiling. The starting batch number should be programmed before the first TA phase of every.." hexmask.long 0xC 0.--31. 1. "Reserved_14,Reserved_14" line.long 0x10 "RGX_CR_VDM_CONTEXT_STATE_BASE_0,The base address in external memory of the VDM's context state buffer. On a context store the VDM will store its state to this address. and reload it on a context resume. The size and format of the data written is defined.." hexmask.long 0x10 4.--31. 1. "ADDR,1TB range 128-bit aligned base address" newline hexmask.long.byte 0x10 0.--3. 1. "Reserved_0,Reserved_0" line.long 0x14 "RGX_CR_VDM_CONTEXT_STATE_BASE_1,The base address in external memory of the VDM's context state buffer. On a context store the VDM will store its state to this address. and reload it on a context resume. The size and format of the data written is defined.." hexmask.long.tbyte 0x14 8.--31. 1. "Reserved_40,Reserved_40" newline hexmask.long.byte 0x14 0.--7. 1. "ADDR,1TB range 128-bit aligned base address" rgroup.long 0x430++0x7 line.long 0x0 "RGX_CR_VDM_CONTEXT_STORE_STATUS_0,This register indicates the status of a VDM context switch operation. If a context store has been requested. then this muist be sample on TA finished. The firmware must wait for the COMPLETE bit to be set. The.." hexmask.long.tbyte 0x0 8.--31. 1. "Reserved_8,Reserved_8" newline hexmask.long.byte 0x0 4.--7. 1. "LAST_PIPE,The TA pipe number to which the VDM last sent indices" newline bitfld.long 0x0 2.--3. "Reserved_2,Reserved_2" "0,1,2,3" newline bitfld.long 0x0 1. "NEED_RESUME,The VDM still has control stream left to process meaning this context must be resumed" "0,1" newline bitfld.long 0x0 0. "COMPLETE,The VDM has completed the context store operation and fenced its state to external memory" "0,1" line.long 0x4 "RGX_CR_VDM_CONTEXT_STORE_STATUS_1,This register indicates the status of a VDM context switch operation. If a context store has been requested. then this muist be sample on TA finished. The firmware must wait for the COMPLETE bit to be set. The.." hexmask.long 0x4 0.--31. 1. "Reserved_8,Reserved_8" repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) group.long ($2+0x438)++0x3 line.long 0x0 "RGX_CR_VDM_CONTEXT_STORE_TASK0_$1,These words define the PDS State Update task which will be inserted into the VDM pipeline on a context store operation. The function of this task is described in the Rogue Context Switching Hardware Specification. Their.." hexmask.long 0x0 0.--31. 1. "PDS_STATE0,PDS_STATE0" repeat.end repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) group.long ($2+0x440)++0x3 line.long 0x0 "RGX_CR_VDM_CONTEXT_STORE_TASK1_$1,This word defines the PDS State Update task which will be inserted into the VDM pipeline on a context store operation. The function of this task is described in the Rogue Context Switching Hardware Specification. Its.." hexmask.long 0x0 0.--31. 1. "PDS_STATE2,PDS_STATE2" repeat.end repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) group.long ($2+0x448)++0x3 line.long 0x0 "RGX_CR_VDM_CONTEXT_STORE_TASK2_$1,These words defines the Stream Out Sync program which will be inserted into the VDM pipeline as a PPP State Update on a context store operation. The function of this task is described in the Rogue Context Switching.." hexmask.long 0x0 0.--31. 1. "STREAM_OUT1,STREAM_OUT1" repeat.end repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) group.long ($2+0x450)++0x3 line.long 0x0 "RGX_CR_VDM_CONTEXT_RESUME_TASK0_$1,These words define the PDS State Update task which will be written by the VDM to its context resume control stream on a context store operation. The function of this task is described in the Rogue Context Switching.." hexmask.long 0x0 0.--31. 1. "PDS_STATE0,PDS_STATE0" repeat.end repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) group.long ($2+0x458)++0x3 line.long 0x0 "RGX_CR_VDM_CONTEXT_RESUME_TASK1_$1,This word defines the PDS State Update task which will be written by the VDM to its context resume control stream on a context store operation. The function of this task is described in the Rogue Context Switching.." hexmask.long 0x0 0.--31. 1. "PDS_STATE2,PDS_STATE2" repeat.end repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) group.long ($2+0x460)++0x3 line.long 0x0 "RGX_CR_VDM_CONTEXT_RESUME_TASK2_$1,These words defines the Stream Out Sync program which will be written. as a PPP State Update. by the VDM to its context resume control stream on a context store operation The function of this task is described in the.." hexmask.long 0x0 0.--31. 1. "STREAM_OUT1,STREAM_OUT1" repeat.end wgroup.long 0x468++0x7 line.long 0x0 "RGX_CR_VDM_CONTEXT_STORE_START_0,Writing '1' to this register starts the VDM context store operation. The function of this task is described in the Rogue Context Switching Hardware Specifiction" hexmask.long 0x0 1.--31. 1. "Reserved_1,Reserved_1" newline bitfld.long 0x0 0. "PULSE,PULSE" "0,1" line.long 0x4 "RGX_CR_VDM_CONTEXT_STORE_START_1,Writing '1' to this register starts the VDM context store operation. The function of this task is described in the Rogue Context Switching Hardware Specifiction" hexmask.long 0x4 0.--31. 1. "Reserved_1,Reserved_1" group.long 0x470++0x7 line.long 0x0 "RGX_CR_VDM_SYNC_PDS_DATA_BASE_0,The base address of the PDS data segment base for all TA state sync program 4GB range. 128-bit granularity The data segment size is always 256 bits The PDS code address for the TA state sync program is always 256 bits on.." hexmask.long 0x0 4.--31. 1. "ADDR,ADDR" newline hexmask.long.byte 0x0 0.--3. 1. "Reserved_0,Reserved_0" line.long 0x4 "RGX_CR_VDM_SYNC_PDS_DATA_BASE_1,The base address of the PDS data segment base for all TA state sync program 4GB range. 128-bit granularity The data segment size is always 256 bits The PDS code address for the TA state sync program is always 256 bits on.." hexmask.long 0x4 0.--31. 1. "Reserved_32,Reserved_32" wgroup.long 0x478++0x7 line.long 0x0 "RGX_CR_CDM_START_0,A write of '1' to this register starts the Compute Data Master reading it's control stream from memory." hexmask.long 0x0 1.--31. 1. "Reserved_1,Reserved_1" newline bitfld.long 0x0 0. "PULSE,Start CDM" "0,1" line.long 0x4 "RGX_CR_CDM_START_1,A write of '1' to this register starts the Compute Data Master reading it's control stream from memory." hexmask.long 0x4 0.--31. 1. "Reserved_1,Reserved_1" group.long 0x480++0x7 line.long 0x0 "RGX_CR_CDM_CTRL_STREAM_BASE_0,The base address of the Compute Data Master's Input Parameter Control Stream in external memory" hexmask.long 0x0 2.--31. 1. "ADDR,1TB range 32-bit aligned base address" newline bitfld.long 0x0 0.--1. "Reserved_0,Reserved_0" "0,1,2,3" line.long 0x4 "RGX_CR_CDM_CTRL_STREAM_BASE_1,The base address of the Compute Data Master's Input Parameter Control Stream in external memory" hexmask.long.tbyte 0x4 8.--31. 1. "Reserved_40,Reserved_40" newline hexmask.long.byte 0x4 0.--7. 1. "ADDR,1TB range 32-bit aligned base address" wgroup.long 0x488++0x7 line.long 0x0 "RGX_CR_CDM_CONTEXT_STORE_0,Writing '1' to this register starts the CDM context store operation." hexmask.long 0x0 1.--31. 1. "Reserved_1,Reserved_1" newline bitfld.long 0x0 0. "PULSE,PULSE" "0,1" line.long 0x4 "RGX_CR_CDM_CONTEXT_STORE_1,Writing '1' to this register starts the CDM context store operation." hexmask.long 0x4 0.--31. 1. "Reserved_1,Reserved_1" group.long 0x490++0xF line.long 0x0 "RGX_CR_CDM_CONTEXT_LOAD_0,The firmware writes a '1' to this register starts the CDM context load operation. The CDM will set this register to '0' when the context load operation is complete The firmware should poll on this register after writing to it" hexmask.long 0x0 1.--31. 1. "Reserved_1,Reserved_1" newline bitfld.long 0x0 0. "PENDING,PENDING" "0,1" line.long 0x4 "RGX_CR_CDM_CONTEXT_LOAD_1,The firmware writes a '1' to this register starts the CDM context load operation. The CDM will set this register to '0' when the context load operation is complete The firmware should poll on this register after writing to it" hexmask.long 0x4 0.--31. 1. "Reserved_1,Reserved_1" line.long 0x8 "RGX_CR_CDM_CONTEXT_STATE_BASE_0,The base address in external memory of the CDM's context state buffer. to which it will store its snapshot state on a context store and from which it will reload on a context resume" hexmask.long 0x8 4.--31. 1. "ADDR,1TB range 128-bit aligned base address" newline hexmask.long.byte 0x8 0.--3. 1. "Reserved_0,Reserved_0" line.long 0xC "RGX_CR_CDM_CONTEXT_STATE_BASE_1,The base address in external memory of the CDM's context state buffer. to which it will store its snapshot state on a context store and from which it will reload on a context resume" hexmask.long.tbyte 0xC 8.--31. 1. "Reserved_40,Reserved_40" newline hexmask.long.byte 0xC 0.--7. 1. "ADDR,1TB range 128-bit aligned base address" rgroup.long 0x4A0++0x7 line.long 0x0 "RGX_CR_CDM_CONTEXT_STORE_STATUS_0,This register indicates the status of a CDM context switch operation. If a context store is in progress. this register must be sampled on a context store compute finished event. The firmware must wait for the COMPLETE.." hexmask.long 0x0 2.--31. 1. "Reserved_2,Reserved_2" newline bitfld.long 0x0 1. "NEED_RESUME,The CDM still has control stream left to process meaning this context must be resumed" "0,1" newline bitfld.long 0x0 0. "COMPLETE,The CDM has completed the context store operation and fenced its state to external memory" "0,1" line.long 0x4 "RGX_CR_CDM_CONTEXT_STORE_STATUS_1,This register indicates the status of a CDM context switch operation. If a context store is in progress. this register must be sampled on a context store compute finished event. The firmware must wait for the COMPLETE.." hexmask.long 0x4 0.--31. 1. "Reserved_2,Reserved_2" repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) group.long ($2+0x4A8)++0x3 line.long 0x0 "RGX_CR_CDM_CONTEXT_PDS0_$1,This register contains the PDS Code and Data Addresses for the Store/Load Program. This program is sent to PDS on Context Store and Context Load." hexmask.long 0x0 4.--31. 1. "CODE_ADDR,PDS Code Address for Store/Load Program 128-bit aligned" newline hexmask.long.byte 0x0 0.--3. 1. "Reserved_0,Reserved_0" repeat.end group.long 0x4B0++0x7 line.long 0x0 "RGX_CR_CDM_CONTEXT_PDS1_0,This register contains the PDS Task Data necessary to produce the Store/Load PDS Program Task from CDM to PDS" bitfld.long 0x0 30.--31. "Reserved_30,Reserved_30" "0,1,2,3" newline bitfld.long 0x0 29. "PDS_SEQ_DEP,PDS Sequential Dependency" "0,1" newline bitfld.long 0x0 28. "USC_SEQ_DEP,USC Sequential Dependency" "0,1" newline bitfld.long 0x0 27. "TARGET,USC Target (0=All 1=Any)" "All,Any)" newline hexmask.long.byte 0x0 21.--26. 1. "UNIFIED_SIZE,Unified Size" newline bitfld.long 0x0 20. "COMMON_SHARED,PDS Common Store Allocation is Shared Registers" "0,1" newline hexmask.long.word 0x0 11.--19. 1. "COMMON_SIZE,PDS Common Size" newline hexmask.long.byte 0x0 7.--10. 1. "TEMP_SIZE,PDS Temp Size" newline hexmask.long.byte 0x0 1.--6. 1. "DATA_SIZE,PDS Data Size" newline bitfld.long 0x0 0. "FENCE,Fence the Task in the PDS/USC - Set on Store unset on Load" "0,1" line.long 0x4 "RGX_CR_CDM_CONTEXT_PDS1_1,This register contains the PDS Task Data necessary to produce the Store/Load PDS Program Task from CDM to PDS" hexmask.long 0x4 0.--31. 1. "Reserved_30,Reserved_30" repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) group.long ($2+0x4B8)++0x3 line.long 0x0 "RGX_CR_CDM_TERMINATE_PDS_$1,This register contains the PDS Code and Data Addresses for the Terminate Program. This program is sent to PDS on Context Store after the Context Store Program" hexmask.long 0x0 4.--31. 1. "CODE_ADDR,PDS Code Address for Terminate Program 128-bit aligned" newline hexmask.long.byte 0x0 0.--3. 1. "Reserved_0,Reserved_0" repeat.end group.long 0x4C0++0x7 line.long 0x0 "RGX_CR_CDM_TERMINATE_PDS1_0,This register contains the PDS Task Data necessary to produce the Context Store Terminate PDS Program Task from CDM to PDS" bitfld.long 0x0 30.--31. "Reserved_30,Reserved_30" "0,1,2,3" newline bitfld.long 0x0 29. "PDS_SEQ_DEP,PDS Sequential Dependency" "0,1" newline bitfld.long 0x0 28. "USC_SEQ_DEP,USC Sequential Dependency" "0,1" newline bitfld.long 0x0 27. "TARGET,USC Target (0=All 1=Any)" "All,Any)" newline hexmask.long.byte 0x0 21.--26. 1. "UNIFIED_SIZE,Unified Size" newline bitfld.long 0x0 20. "COMMON_SHARED,PDS Common Store Allocation is Shared Registers" "0,1" newline hexmask.long.word 0x0 11.--19. 1. "COMMON_SIZE,PDS Common Size" newline hexmask.long.byte 0x0 7.--10. 1. "TEMP_SIZE,PDS Temp Size" newline hexmask.long.byte 0x0 1.--6. 1. "DATA_SIZE,PDS Data Size" newline bitfld.long 0x0 0. "FENCE,Fence the Task in the PDS/USC - Set on Store Terminate" "0,1" line.long 0x4 "RGX_CR_CDM_TERMINATE_PDS1_1,This register contains the PDS Task Data necessary to produce the Context Store Terminate PDS Program Task from CDM to PDS" hexmask.long 0x4 0.--31. 1. "Reserved_30,Reserved_30" repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) group.long ($2+0x4D8)++0x3 line.long 0x0 "RGX_CR_CDM_CONTEXT_LOAD_PDS0_$1,This register contains the PDS Code and Data Addresses for the Store/Load Program. This program is sent to PDS on Context Store and Context Load." hexmask.long 0x0 4.--31. 1. "CODE_ADDR,PDS Code Address for Store/Load Program 128-bit aligned" newline hexmask.long.byte 0x0 0.--3. 1. "Reserved_0,Reserved_0" repeat.end group.long 0x4E0++0x7 line.long 0x0 "RGX_CR_CDM_CONTEXT_LOAD_PDS1_0,This register contains the PDS Task Data necessary to produce the Store/Load PDS Program Task from CDM to PDS" bitfld.long 0x0 30.--31. "Reserved_30,Reserved_30" "0,1,2,3" newline bitfld.long 0x0 29. "PDS_SEQ_DEP,PDS Sequential Dependency" "0,1" newline bitfld.long 0x0 28. "USC_SEQ_DEP,USC Sequential Dependency" "0,1" newline bitfld.long 0x0 27. "TARGET,USC Target (0=All 1=Any)" "All,Any)" newline hexmask.long.byte 0x0 21.--26. 1. "UNIFIED_SIZE,Unified Size" newline bitfld.long 0x0 20. "COMMON_SHARED,PDS Common Store Allocation is Shared Registers" "0,1" newline hexmask.long.word 0x0 11.--19. 1. "COMMON_SIZE,PDS Common Size" newline hexmask.long.byte 0x0 7.--10. 1. "TEMP_SIZE,PDS Temp Size" newline hexmask.long.byte 0x0 1.--6. 1. "DATA_SIZE,PDS Data Size" newline bitfld.long 0x0 0. "FENCE,Fence the Task in the PDS/USC - Set on Store unset on Load" "0,1" line.long 0x4 "RGX_CR_CDM_CONTEXT_LOAD_PDS1_1,This register contains the PDS Task Data necessary to produce the Store/Load PDS Program Task from CDM to PDS" hexmask.long 0x4 0.--31. 1. "Reserved_30,Reserved_30" group.long 0x600++0x7 line.long 0x0 "RGX_CR_PDS_CTRL_0,Controls the maximum number of tasks per data master (per USC). There are a maximum of 48 tasks in the system" hexmask.long.byte 0x0 24.--31. 1. "MAX_NUM_CDM_TASKS,The maximum number of compute tasks allowed on each USC range 0 to 48" newline hexmask.long.byte 0x0 16.--23. 1. "MAX_NUM_PDM_TASKS,The maximum number of pixel tasks allowed on each USC range 0 to 48" newline hexmask.long.byte 0x0 8.--15. 1. "MAX_NUM_VDM_TASKS,The maximum number of vertex tasks (VS HS GS when Tess not enabled) allowed on each USC range 0 to 39 (Note reduced range to prevent Pixel/VDM system deadlock)" newline hexmask.long.byte 0x0 0.--7. 1. "MAX_NUM_TDM_TASKS,The maximum number of fastrender tasks allowed on each USC range 0 to 48" line.long 0x4 "RGX_CR_PDS_CTRL_1,Controls the maximum number of tasks per data master (per USC). There are a maximum of 48 tasks in the system" hexmask.long 0x4 0.--31. 1. "Reserved_32,Reserved_32" wgroup.long 0x608++0x7 line.long 0x0 "RGX_CR_PDS_USC_COLLATOR_0,This register clear the internal resource tracking storage. It must be cleared after reste/power up. A write of '1' to this register clears the PDS Unified Clusters Resource Collator Contents. The PDS USC Resource Collator is a.." hexmask.long 0x0 1.--31. 1. "Reserved_1,Reserved_1" newline bitfld.long 0x0 0. "CLEAR,Clear PDS Unified Clusters Resource Collator" "0,1" line.long 0x4 "RGX_CR_PDS_USC_COLLATOR_1,This register clear the internal resource tracking storage. It must be cleared after reste/power up. A write of '1' to this register clears the PDS Unified Clusters Resource Collator Contents. The PDS USC Resource Collator is a.." hexmask.long 0x4 0.--31. 1. "Reserved_1,Reserved_1" group.long 0x610++0x1F line.long 0x0 "RGX_CR_PDS_EXEC_BASE_0,Base Address in memory where the PDS programs are located" hexmask.long.word 0x0 20.--31. 1. "ADDR,1TB addressable 1 MB aligned base address for PDS programs" newline hexmask.long.tbyte 0x0 0.--19. 1. "Reserved_0,Reserved_0" line.long 0x4 "RGX_CR_PDS_EXEC_BASE_1,Base Address in memory where the PDS programs are located" hexmask.long.tbyte 0x4 8.--31. 1. "Reserved_40,Reserved_40" newline hexmask.long.byte 0x4 0.--7. 1. "ADDR,1TB addressable 1 MB aligned base address for PDS programs" line.long 0x8 "RGX_CR_EVENT_PIXEL_PDS_CODE_0,RGX_CR_EVENT_PIXEL_PDS_CODE_0" hexmask.long 0x8 4.--31. 1. "ADDR,PDS Execution Address for pixel tasks (Positioned as a byte address 128 bit granularity) 4 GB Range" newline hexmask.long.byte 0x8 0.--3. 1. "Reserved_0,Reserved_0" line.long 0xC "RGX_CR_EVENT_PIXEL_PDS_CODE_1,RGX_CR_EVENT_PIXEL_PDS_CODE_1" hexmask.long 0xC 0.--31. 1. "Reserved_32,Reserved_32" line.long 0x10 "RGX_CR_EVENT_PIXEL_PDS_DATA_0,RGX_CR_EVENT_PIXEL_PDS_DATA_0" hexmask.long 0x10 4.--31. 1. "ADDR,PDS Execution Address for pixel tasks (Positioned as a byte address 128 bit granularity) 4 GB Range" newline hexmask.long.byte 0x10 0.--3. 1. "Reserved_0,Reserved_0" line.long 0x14 "RGX_CR_EVENT_PIXEL_PDS_DATA_1,RGX_CR_EVENT_PIXEL_PDS_DATA_1" hexmask.long 0x14 0.--31. 1. "Reserved_32,Reserved_32" line.long 0x18 "RGX_CR_EVENT_PIXEL_PDS_INFO_0,RGX_CR_EVENT_PIXEL_PDS_INFO_0" hexmask.long.tbyte 0x18 15.--31. 1. "Reserved_15,Reserved_15" newline hexmask.long.byte 0x18 9.--14. 1. "USC_SR_SIZE,USC Shared Register Data Size in 4x128 bit words (0=0) for pixel event task if zero pixel event task is skipped" newline hexmask.long.byte 0x18 5.--8. 1. "TEMP_STRIDE,PDS Temp Size in 128 bit words (0=0) for pixel event tasks" newline hexmask.long.byte 0x18 0.--4. 1. "CONST_SIZE,PDS Data Size in 128 bit words (0=0) for pixel event tasks if zero pixel event task is skipped" line.long 0x1C "RGX_CR_EVENT_PIXEL_PDS_INFO_1,RGX_CR_EVENT_PIXEL_PDS_INFO_1" hexmask.long 0x1C 0.--31. 1. "Reserved_15,Reserved_15" wgroup.long 0x630++0x7 line.long 0x0 "RGX_CR_PDS_CSRM_0,A write of '1' to this register clears the PDS Common Store Resource Manager Contents The PDS CSRM is a cross-DM controller. meaning this register must not be written during any active TA. 3D or Compute phase. This register must be.." hexmask.long 0x0 1.--31. 1. "Reserved_1,Reserved_1" newline bitfld.long 0x0 0. "CLEAR,Clear PDS Common Store Resource Manager a write to this register results in a one cycle pulse" "0,1" line.long 0x4 "RGX_CR_PDS_CSRM_1,A write of '1' to this register clears the PDS Common Store Resource Manager Contents The PDS CSRM is a cross-DM controller. meaning this register must not be written during any active TA. 3D or Compute phase. This register must be.." hexmask.long 0x4 0.--31. 1. "Reserved_1,Reserved_1" group.long 0x638++0xF line.long 0x0 "RGX_CR_PDS_MAX_CSRM_CHUNKS_0,Soft Limit Registers for Maximum Allocation Chunks in the Common Store on a Data Master basis. 1024 Allocation Regions exist in the Common Store. Each Allocation Region or Chunk represetns 4x128-bits of space in the Common.." hexmask.long.byte 0x0 27.--31. 1. "Reserved_27,Reserved_27" newline hexmask.long.word 0x0 18.--26. 1. "CDM,Max Number of Allocation Regions to Allocate to the Compute Data Master in Common Store" newline hexmask.long.word 0x0 9.--17. 1. "PDM,Max Number of Allocation Regions to Allocate to the Pixel Data Master in Common Store" newline hexmask.long.word 0x0 0.--8. 1. "VDM,Max Number of Allocation Regions to Allocate to the VDM Data Master in Common Store" line.long 0x4 "RGX_CR_PDS_MAX_CSRM_CHUNKS_1,Soft Limit Registers for Maximum Allocation Chunks in the Common Store on a Data Master basis. 1024 Allocation Regions exist in the Common Store. Each Allocation Region or Chunk represetns 4x128-bits of space in the Common.." hexmask.long 0x4 0.--31. 1. "Reserved_27,Reserved_27" line.long 0x8 "RGX_CR_PDS_CSRM_MAX_COEFF_0,The Common Store contains Coefficients and Shared Registers in a maximum of n Lines of 64 Allocation Chunks numbered 0-19. Allocated Dynamically. This Register sets a Soft Limit for the Maximum Line to Allocate for use as a.." hexmask.long 0x8 6.--31. 1. "Reserved_6,Reserved_6" newline hexmask.long.byte 0x8 1.--5. 1. "LINE,Coefficients are allocated from Line 0 upwards this is the maximum Line to use for Coefficients before wrapping" newline bitfld.long 0x8 0. "LINE_ENABLE,Enable Max Coefficient Line Limit" "0,1" line.long 0xC "RGX_CR_PDS_CSRM_MAX_COEFF_1,The Common Store contains Coefficients and Shared Registers in a maximum of n Lines of 64 Allocation Chunks numbered 0-19. Allocated Dynamically. This Register sets a Soft Limit for the Maximum Line to Allocate for use as a.." hexmask.long 0xC 0.--31. 1. "Reserved_6,Reserved_6" wgroup.long 0x648++0x7 line.long 0x0 "RGX_CR_PDS_USRM_0,A write of '1' to this register clears the PDS Unified Store Resource Manager Contents. The PDS Unified Store Resource Manager only applies to the vertex and compute data masters. This register must be written during the core.." hexmask.long 0x0 1.--31. 1. "Reserved_1,Reserved_1" newline bitfld.long 0x0 0. "CLEAR,Clear PDS Unified Store Resource Manager a write to this register results in a one cycle pulse" "0,1" line.long 0x4 "RGX_CR_PDS_USRM_1,A write of '1' to this register clears the PDS Unified Store Resource Manager Contents. The PDS Unified Store Resource Manager only applies to the vertex and compute data masters. This register must be written during the core.." hexmask.long 0x4 0.--31. 1. "Reserved_1,Reserved_1" group.long 0x650++0xF line.long 0x0 "RGX_CR_PDS_MAX_USRM_CHUNKS_0,Soft Limit Registers for Maximum Allocation Chunks in the Unified Store on a Data Master basis. 400 Allocation Regions exist in the Unified Store. Each Allocation Region represents 4x128-bits of space in the Unified Store." hexmask.long.word 0x0 18.--31. 1. "Reserved_18,Reserved_18" newline hexmask.long.word 0x0 9.--17. 1. "CDM,Max Number of Allocation Regions to Allocate to the Compute Data Master in Unified Store" newline hexmask.long.word 0x0 0.--8. 1. "VDM,Max Number of Allocation Regions to Allocate to the VDM Data Master in Unified Store" line.long 0x4 "RGX_CR_PDS_MAX_USRM_CHUNKS_1,Soft Limit Registers for Maximum Allocation Chunks in the Unified Store on a Data Master basis. 400 Allocation Regions exist in the Unified Store. Each Allocation Region represents 4x128-bits of space in the Unified Store." hexmask.long 0x4 0.--31. 1. "Reserved_18,Reserved_18" line.long 0x8 "RGX_CR_PDS_USRM_MAX_TEMP_0,The Unified Store contains Temporaries and Attributes in n Lines of 16 Allocation Chunks numbered 0- n-1. Allocated Dynamically. This Register sets a Soft Limit for the Maximum Line to Allocate for use as a Temporaries Line.." hexmask.long 0x8 5.--31. 1. "Reserved_5,Reserved_5" newline hexmask.long.byte 0x8 1.--4. 1. "LINE,Max Line for use as Temporaries" newline bitfld.long 0x8 0. "LINE_ENABLE,Enable Max Temporaries Line Limit" "0,1" line.long 0xC "RGX_CR_PDS_USRM_MAX_TEMP_1,The Unified Store contains Temporaries and Attributes in n Lines of 16 Allocation Chunks numbered 0- n-1. Allocated Dynamically. This Register sets a Soft Limit for the Maximum Line to Allocate for use as a Temporaries Line.." hexmask.long 0xC 0.--31. 1. "Reserved_5,Reserved_5" wgroup.long 0x660++0x7 line.long 0x0 "RGX_CR_PDS_UVSRM_0,A write of '1' to this register clears the PDS Unified Vertex Store Resource Manager Contents The UVS Resource Manager only applies to the vertex data master. This register must be written during the core initialisation sequence." hexmask.long 0x0 1.--31. 1. "Reserved_1,Reserved_1" newline bitfld.long 0x0 0. "CLEAR,Clear PDS Unified Vertex Store Resource Manager a write to this register results in a one cycle pulse" "0,1" line.long 0x4 "RGX_CR_PDS_UVSRM_1,A write of '1' to this register clears the PDS Unified Vertex Store Resource Manager Contents The UVS Resource Manager only applies to the vertex data master. This register must be written during the core initialisation sequence." hexmask.long 0x4 0.--31. 1. "Reserved_1,Reserved_1" group.long 0x668++0x7 line.long 0x0 "RGX_CR_MCU_FBTC_ICTRL_0,MCU Framebuffer Tile Cache Invalidate Control" hexmask.long 0x0 4.--31. 1. "Reserved_4,Reserved_4" newline bitfld.long 0x0 3. "COMP_DM,When set to 1 all entries in the tile cache that have been tagged as a compute data master will be invalidate when PENDING is set" "0,1" newline bitfld.long 0x0 2. "VERTEX_DM,When set to 1 all entries in the tile cache that have been tagged as a vertex data master will be invalidate when PENDING is set" "0,1" newline bitfld.long 0x0 1. "PIXEL_DM,When set to 1 all entries in the tile cache that have been tagged as a pixel data master will be invalidate when PENDING is set" "0,1" newline bitfld.long 0x0 0. "PENDING,When written to 1 will invalidate the header cache in the FBDC when read as 1 invalidate is in progress when read as 0 invalidate is complete" "0,1" line.long 0x4 "RGX_CR_MCU_FBTC_ICTRL_1,MCU Framebuffer Tile Cache Invalidate Control" hexmask.long 0x4 0.--31. 1. "Reserved_4,Reserved_4" wgroup.long 0x670++0x7 line.long 0x0 "RGX_CR_PDS_STORERM_0,A write of '1' to this register clears the PDS Store Resource Manager Contents. The PDS Store Resource Manager is a cross-DM controller. meaning this register must not be written during any active TA. 3D or Compute phase. This.." hexmask.long 0x0 1.--31. 1. "Reserved_1,Reserved_1" newline bitfld.long 0x0 0. "CLEAR,Clear PDS Store Resource Manager a write to this register results in a one cycle pulse" "0,1" line.long 0x4 "RGX_CR_PDS_STORERM_1,A write of '1' to this register clears the PDS Store Resource Manager Contents. The PDS Store Resource Manager is a cross-DM controller. meaning this register must not be written during any active TA. 3D or Compute phase. This.." hexmask.long 0x4 0.--31. 1. "Reserved_1,Reserved_1" group.long 0x678++0x27 line.long 0x0 "RGX_CR_PDS_MAX_STORERM_CHUNKS_0,Soft Limit Registers for Maximum Allocation Chunks in the PDS Store on a Data Master basis. 488 Allocation Regions exist in the PDS Store. Each Allocation Chunk/Region represents 8x64-bits of space in the PDS Store." hexmask.long.byte 0x0 27.--31. 1. "STM,Max Number of Allocation Regions to Allocate to the Stream Out Data Master in PDS Store" newline hexmask.long.word 0x0 18.--26. 1. "CDM,Max Number of Allocation Regions to Allocate to the Compute Data Master in PDS Store" newline hexmask.long.word 0x0 9.--17. 1. "PDM,Max Number of Allocation Regions to Allocate to the Pixel Data Master in PDS Store" newline hexmask.long.word 0x0 0.--8. 1. "VDM,Max Number of Allocation Regions to Allocate to the VDM Data Master in PDS Store" line.long 0x4 "RGX_CR_PDS_MAX_STORERM_CHUNKS_1,Soft Limit Registers for Maximum Allocation Chunks in the PDS Store on a Data Master basis. 488 Allocation Regions exist in the PDS Store. Each Allocation Chunk/Region represents 8x64-bits of space in the PDS Store." hexmask.long 0x4 4.--31. 1. "Reserved_36,Reserved_36" newline hexmask.long.byte 0x4 0.--3. 1. "STM,Max Number of Allocation Regions to Allocate to the Stream Out Data Master in PDS Store" line.long 0x8 "RGX_CR_PDS_STORERM_MAX_TEMP_0,The PDS Store Resource Manager contains Temporaries and Constants in 8 Lines of 64 Allocation Chunks each numbered 0-7. Allocated Dynamically. This Register sets a Soft Limit for the Maximum Line to Allocate for use as a.." hexmask.long 0x8 4.--31. 1. "Reserved_4,Reserved_4" newline bitfld.long 0x8 1.--3. "LINE,Temporaries are allocated from Line 0 upwards this is the maximum Line to use for Temporaries before wrapping" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 0. "LINE_ENABLE,Enable Max Temporaries Line Limit" "0,1" line.long 0xC "RGX_CR_PDS_STORERM_MAX_TEMP_1,The PDS Store Resource Manager contains Temporaries and Constants in 8 Lines of 64 Allocation Chunks each numbered 0-7. Allocated Dynamically. This Register sets a Soft Limit for the Maximum Line to Allocate for use as a.." hexmask.long 0xC 0.--31. 1. "Reserved_4,Reserved_4" line.long 0x10 "RGX_CR_PDS_ICC_INVAL_0,A write of '1' any bit to this register clears the PDS Instruction Cache for the selected DM The PDS HW will clear the bits when the operations complete" hexmask.long 0x10 6.--31. 1. "Reserved_6,Reserved_6" newline bitfld.long 0x10 5. "FASTRENDER_PENDING,PDS Instruction Cache Fastrender (DM 6) has been invalidated" "0,1" newline bitfld.long 0x10 3.--4. "Reserved_3,Reserved_3" "0,1,2,3" newline bitfld.long 0x10 2. "COMPUTE_PENDING,PDS Instruction Cache Compute (DM 2) has been invalidated" "0,1" newline bitfld.long 0x10 1. "PIXEL_PENDING,PDS Instruction Cache Pixel (DM 1) has been invalidated" "0,1" newline bitfld.long 0x10 0. "VERTEX_PENDING,PDS Instruction Cache Vertex (DM 0) has been invalidated" "0,1" line.long 0x14 "RGX_CR_PDS_ICC_INVAL_1,A write of '1' any bit to this register clears the PDS Instruction Cache for the selected DM The PDS HW will clear the bits when the operations complete" hexmask.long 0x14 0.--31. 1. "Reserved_6,Reserved_6" line.long 0x18 "RGX_CR_PDS_MCU_REQ_CTRL_0,The PDS makes requests to the MCU to DMA to the PDS store and write data to memory. This register defines the various cache modes that apply to those requests." hexmask.long 0x18 4.--31. 1. "Reserved_4,Reserved_4" newline bitfld.long 0x18 2.--3. "SMODE,SLC cache policy to use for requests from the VDM/PDM/CDM/STM resource requestors inside the PDS" "0,1,2,3" newline bitfld.long 0x18 0.--1. "CMODE,Cache Mode to use for requests from the VDM/PDM/CDM/STM resource requestors inside the PDS" "0,1,2,3" line.long 0x1C "RGX_CR_PDS_MCU_REQ_CTRL_1,The PDS makes requests to the MCU to DMA to the PDS store and write data to memory. This register defines the various cache modes that apply to those requests." hexmask.long 0x1C 0.--31. 1. "Reserved_4,Reserved_4" line.long 0x20 "RGX_CR_PDS_CSRM_MIN_SHARED_0,The Common Store contains Coefficients and Shared Registers in 14 Lines of 64 Allocation Chunks numbered 0-13. Allocated Dynamically. This Register sets a Soft Limit for the Minimum Line to Allocate for use as a Shared Line.." hexmask.long 0x20 6.--31. 1. "Reserved_6,Reserved_6" newline hexmask.long.byte 0x20 1.--5. 1. "LINE,Shared are allocated from top line downwards this is the minimum Line to use for Shared Registers before wrapping" newline bitfld.long 0x20 0. "LINE_ENABLE,Enable Min Shared Register Line Limit" "0,1" line.long 0x24 "RGX_CR_PDS_CSRM_MIN_SHARED_1,The Common Store contains Coefficients and Shared Registers in 14 Lines of 64 Allocation Chunks numbered 0-13. Allocated Dynamically. This Register sets a Soft Limit for the Minimum Line to Allocate for use as a Shared Line.." hexmask.long 0x24 0.--31. 1. "Reserved_6,Reserved_6" repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) group.long ($2+0x6A0)++0x3 line.long 0x0 "RGX_CR_PDS_BGRND0_BASE_$1,PDS Background Setup Word 0" hexmask.long 0x0 4.--31. 1. "SHADER_ADDR,The pixel shader base is the base address of the PDS Data Segment. The code segment is address is PDS_PIXEL_SHADERBASE + PDS_PIXELSHADERSIZE. The pixel shader program issues the DOUTU for the Fragment Shader only." newline hexmask.long.byte 0x0 0.--3. 1. "Reserved_0,Reserved_0" repeat.end repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) group.long ($2+0x6A8)++0x3 line.long 0x0 "RGX_CR_PDS_BGRND1_BASE_$1,PDS Background Setup Word 1" hexmask.long 0x0 4.--31. 1. "VARYING_ADDR,This is the base address of the PDS Data Segment. The code segment is address is PDS_VARYINGBASE + PDS_VARYINGSIZE (PDS_BGRND_SIZEINFO1)." newline hexmask.long.byte 0x0 0.--3. 1. "Reserved_0,Reserved_0" repeat.end group.long 0x6B0++0x37 line.long 0x0 "RGX_CR_PDS_BGRND2_BASE_0,PDS Background Setup Word 2" hexmask.long 0x0 4.--31. 1. "UNIFORMDATA_ADDR,This points to the DMAs to load the Uniforms (or contains the Uniforms with DOUTW commands)" newline hexmask.long.byte 0x0 0.--3. 1. "Reserved_0,Reserved_0" line.long 0x4 "RGX_CR_PDS_BGRND2_BASE_1,PDS Background Setup Word 2" hexmask.long 0x4 0.--31. 1. "Reserved_32,Reserved_32" line.long 0x8 "RGX_CR_PDS_BGRND3_SIZEINFO_0,If any of the size fields are 0. then that program will not be run. PDS_BGRND_PIXELSHADERSIZE is always 2 128 Bit Words" hexmask.long.word 0x8 23.--31. 1. "PDS_UNIFORMSIZE,The size of the Uniform PDS Data Segment in 128 bit words" newline hexmask.long.byte 0x8 16.--22. 1. "PDS_TEXTURESTATESIZE,The size of the Texture PDS Data Segment in 128 bit words" newline hexmask.long.byte 0x8 10.--15. 1. "PDS_VARYINGSIZE,The size of the Varying/Coefficient PDS Data Segment in 128 bit words" newline hexmask.long.byte 0x8 4.--9. 1. "USC_VARYINGSIZE,The size of the Varying/Coefficient USC Common Store Data in 4x128 bit words" newline hexmask.long.byte 0x8 0.--3. 1. "PDS_TEMPSIZE,0 = 0 128 bit words 1 = 1 128 bit word this applies to coefficient uniform and varying state" line.long 0xC "RGX_CR_PDS_BGRND3_SIZEINFO_1,If any of the size fields are 0. then that program will not be run. PDS_BGRND_PIXELSHADERSIZE is always 2 128 Bit Words" hexmask.long.word 0xC 23.--31. 1. "USC_SHAREDSIZE,The common store allocation size for the shared registers (texture and uniform data commbined)" newline hexmask.long.word 0xC 14.--22. 1. "Reserved_46,Reserved_46" newline hexmask.long.word 0xC 0.--13. 1. "PDS_BATCHNUM,The batch ID to be associated with the background" line.long 0x10 "RGX_CR_PDS_USRM_MIN_ATTR_0,The Unified Store contains Temporaries and Attributes in n Lines of 16 Allocation Chunks numbered 0 - n-1. Allocated Dynamically. This Register sets a Soft Limit for the Minimum Line to Allocate for use as an Attribute Line.." hexmask.long 0x10 5.--31. 1. "Reserved_5,Reserved_5" newline hexmask.long.byte 0x10 1.--4. 1. "LINE,Min Line for use for Attributes" newline bitfld.long 0x10 0. "LINE_ENABLE,Enable Min Attributes Line Limit" "0,1" line.long 0x14 "RGX_CR_PDS_USRM_MIN_ATTR_1,The Unified Store contains Temporaries and Attributes in n Lines of 16 Allocation Chunks numbered 0 - n-1. Allocated Dynamically. This Register sets a Soft Limit for the Minimum Line to Allocate for use as an Attribute Line.." hexmask.long 0x14 0.--31. 1. "Reserved_5,Reserved_5" line.long 0x18 "RGX_CR_PDS_STORERM_MIN_CONST_0,The PDS Store Resource Manager contains Temporaries and Constants in 8 Lines of 64 Allocation Chunks each numbered 0-7. Allocated Dynamically. This Register sets a Soft Limit for the Minimum Line to Allocate for use as a.." hexmask.long 0x18 4.--31. 1. "Reserved_4,Reserved_4" newline bitfld.long 0x18 1.--3. "LINE,Constants are allocated from Line 7 down this is the minimum Line to use for Constants before wrapping" "0,1,2,3,4,5,6,7" newline bitfld.long 0x18 0. "LINE_ENABLE,Enable Min Constants Line Limit" "0,1" line.long 0x1C "RGX_CR_PDS_STORERM_MIN_CONST_1,The PDS Store Resource Manager contains Temporaries and Constants in 8 Lines of 64 Allocation Chunks each numbered 0-7. Allocated Dynamically. This Register sets a Soft Limit for the Minimum Line to Allocate for use as a.." hexmask.long 0x1C 0.--31. 1. "Reserved_4,Reserved_4" line.long 0x20 "RGX_CR_PDS_PIXELMERGE_0,RGX_CR_PDS_PIXELMERGE_0" hexmask.long 0x20 7.--31. 1. "Reserved_7,Reserved_7" newline bitfld.long 0x20 6. "TASK_DISABLE,Disable pixel merging within a whole pixel fragment task" "0,1" newline bitfld.long 0x20 5. "DISABLE,Disable pixel merging within each 2x2 pixel block of a pixel fragment task" "0,1" newline hexmask.long.byte 0x20 0.--4. 1. "GRADLIMIT,Gradient difference limit for PDS PP pixel merging" line.long 0x24 "RGX_CR_PDS_PIXELMERGE_1,RGX_CR_PDS_PIXELMERGE_1" hexmask.long 0x24 0.--31. 1. "Reserved_7,Reserved_7" line.long 0x28 "RGX_CR_PDS_CSRM_USC_DEBUG_0,When written a non zero value. this register assigns an extra degree of space to be allocated in the Common Store via the PDS CSRM for USC debugging on Shared Allocations. The SIZE field is Allocation Region Granular (i.e.." hexmask.long 0x28 5.--31. 1. "Reserved_5,Reserved_5" newline hexmask.long.byte 0x28 0.--4. 1. "SIZE,Amount of Space (in 512-bit Allocation Regions) to allocate to USC Debug Space on a Shared Allocation." line.long 0x2C "RGX_CR_PDS_CSRM_USC_DEBUG_1,When written a non zero value. this register assigns an extra degree of space to be allocated in the Common Store via the PDS CSRM for USC debugging on Shared Allocations. The SIZE field is Allocation Region Granular (i.e.." hexmask.long 0x2C 0.--31. 1. "Reserved_5,Reserved_5" line.long 0x30 "RGX_CR_PDS_CSRM_DISABLE_0,When this register is set. the CSRM will be configured on PDS CSRM CLEAR to not reserve any space for Partitions (this is normally governed by the AA MODE and PIXEL OUTPUT CTRL WIDTH register settings). to maximise space in the.." hexmask.long 0x30 3.--31. 1. "Reserved_3,Reserved_3" newline bitfld.long 0x30 2. "COEFF_SLIDE,Disable Slide of Coeff Allocations on Failure" "0,1" newline bitfld.long 0x30 1. "SHARED_SLIDE,Disable Slide of Shared Allocations on Failure" "0,1" newline bitfld.long 0x30 0. "PARTITIONS,Disable Partition Space Reservation in the CSRM" "0,1" line.long 0x34 "RGX_CR_PDS_CSRM_DISABLE_1,When this register is set. the CSRM will be configured on PDS CSRM CLEAR to not reserve any space for Partitions (this is normally governed by the AA MODE and PIXEL OUTPUT CTRL WIDTH register settings). to maximise space in the.." hexmask.long 0x34 0.--31. 1. "Reserved_3,Reserved_3" rgroup.long 0x6E8++0x7 line.long 0x0 "RGX_CR_HUB_IDLE_0,RGX_CR_HUB_IDLE_0" hexmask.long 0x0 4.--31. 1. "Reserved_4,Reserved_4" newline bitfld.long 0x0 3. "TDM,TDM Module IDLE" "0,1" newline bitfld.long 0x0 2. "CDM,CDM Module IDLE" "0,1" newline bitfld.long 0x0 1. "VDM,VDM Module IDLE" "0,1" newline bitfld.long 0x0 0. "PDS,PDS Module IDLE" "0,1" line.long 0x4 "RGX_CR_HUB_IDLE_1,RGX_CR_HUB_IDLE_1" hexmask.long 0x4 0.--31. 1. "Reserved_4,Reserved_4" repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) rgroup.long ($2+0x6F0)++0x3 line.long 0x0 "RGX_CR_HUB_PWR_$1,RGX_CR_HUB_PWR_0" hexmask.long 0x0 0.--31. 1. "NUM_PDS_INST,Number of PDS instructions" repeat.end group.long 0x700++0xF line.long 0x0 "RGX_CR_PDS_PASSGROUP_0,RGX_CR_PDS_PASSGROUP_0" hexmask.long 0x0 2.--31. 1. "Reserved_2,Reserved_2" newline bitfld.long 0x0 1. "FORCE_PT,Force the use of Hard SDs between punchthrough or depth feedback type passes" "0,1" newline bitfld.long 0x0 0. "ENABLE,Enable pass group optimisation within USC by replacing USC Hard SDs with USC Soft SDs for all pass groups in the PDS PP." "0,1" line.long 0x4 "RGX_CR_PDS_PASSGROUP_1,RGX_CR_PDS_PASSGROUP_1" hexmask.long 0x4 0.--31. 1. "Reserved_2,Reserved_2" line.long 0x8 "RGX_CR_PDS_COMPUTE_THREAD_BARRIER_0,RGX_CR_PDS_COMPUTE_THREAD_BARRIER_0" hexmask.long 0x8 1.--31. 1. "Reserved_1,Reserved_1" newline bitfld.long 0x8 0. "ENABLE,Enable thread barrier support in the PDS CDM_RR." "0,1" line.long 0xC "RGX_CR_PDS_COMPUTE_THREAD_BARRIER_1,RGX_CR_PDS_COMPUTE_THREAD_BARRIER_1" hexmask.long 0xC 0.--31. 1. "Reserved_1,Reserved_1" group.long 0x720++0x7 line.long 0x0 "RGX_CR_PDS_CSRM_SETUP_0,If the ENABLE field is set. then when the PDS CSRM is Cleared via the PDS_CSRM_CLEAR register. the value set in the MAX_LINE vector is used to define the maximum Line in the CSRM which is allocatable to Shared.." hexmask.long 0x0 6.--31. 1. "Reserved_6,Reserved_6" newline bitfld.long 0x0 5. "HALF,Top line is prefilled half full" "0,1" newline hexmask.long.byte 0x0 1.--4. 1. "MAX_LINE,(Lower 4 bits of) Maximum Line within the CSRM that can be allocated to Shared Registers/Coefficients" newline bitfld.long 0x0 0. "ENABLE,Enable use of this register to set the Maximum Line the CSRM can allocate on behalf of the USC Common Store" "0,1" line.long 0x4 "RGX_CR_PDS_CSRM_SETUP_1,If the ENABLE field is set. then when the PDS CSRM is Cleared via the PDS_CSRM_CLEAR register. the value set in the MAX_LINE vector is used to define the maximum Line in the CSRM which is allocatable to Shared.." hexmask.long 0x4 0.--31. 1. "Reserved_6,Reserved_6" group.long 0x738++0x7 line.long 0x0 "RGX_CR_PDS_USRM_DISABLE_0,When this register is set. the USRM will be configured on PDS USRM CLEAR to disable the Temp/Attribute slide functionality which allows a Temporaries or Attributes allocation which fails to slide the allocation window. The.." hexmask.long 0x0 1.--31. 1. "Reserved_1,Reserved_1" newline bitfld.long 0x0 0. "TEMP_SLIDE,Disable Slide of Temp Allocations on Failure" "0,1" line.long 0x4 "RGX_CR_PDS_USRM_DISABLE_1,When this register is set. the USRM will be configured on PDS USRM CLEAR to disable the Temp/Attribute slide functionality which allows a Temporaries or Attributes allocation which fails to slide the allocation window. The.." hexmask.long 0x4 0.--31. 1. "Reserved_1,Reserved_1" group.long 0x788++0xF line.long 0x0 "RGX_CR_PDS_CSRM_PIXEL_0,The Common Store contains Coefficients and Shared Registers in a maximum of n Lines of 64 Allocation Chunks numbered 0-31. Allocated Dynamically. This Register sets a Soft Limit for the Maximum Line of available Coefficient space." hexmask.long 0x0 6.--31. 1. "Reserved_6,Reserved_6" newline hexmask.long.byte 0x0 1.--5. 1. "MAX_LINE,Coefficients are allocated from Line 0 upwards this is the maximum Line to reserve for ONLY PDM Coefficients. The Max line of this region is set in the PDS_CSRM_MAX_COEFF register" newline bitfld.long 0x0 0. "MODE_ENABLE,Enable PIXEL RESERVE MODE in the PDS CSRM" "0,1" line.long 0x4 "RGX_CR_PDS_CSRM_PIXEL_1,The Common Store contains Coefficients and Shared Registers in a maximum of n Lines of 64 Allocation Chunks numbered 0-31. Allocated Dynamically. This Register sets a Soft Limit for the Maximum Line of available Coefficient space." hexmask.long 0x4 0.--31. 1. "Reserved_6,Reserved_6" line.long 0x8 "RGX_CR_PDS_MAX_STORERM_CHUNKS2_0,Soft Limit Registers for Maximum Allocation Chunks in the PDS Store on a Data Master basis. 488 Allocation Regions exist in the PDS Store. Each Allocation Chunk/Region represents 8x64-bits of space in the PDS Store." hexmask.long.tbyte 0x8 9.--31. 1. "Reserved_9,Reserved_9" newline hexmask.long.word 0x8 0.--8. 1. "TDM,Max Number of Allocation Regions to Allocate to the Fastrender Data Master in PDS Store" line.long 0xC "RGX_CR_PDS_MAX_STORERM_CHUNKS2_1,Soft Limit Registers for Maximum Allocation Chunks in the PDS Store on a Data Master basis. 488 Allocation Regions exist in the PDS Store. Each Allocation Chunk/Region represents 8x64-bits of space in the PDS Store." hexmask.long 0xC 0.--31. 1. "Reserved_9,Reserved_9" group.long 0x800++0x67 line.long 0x0 "RGX_CR_SIDEKICK_EXT_MEM_ARB_CONFIG_0,This register contains the configuration options for the Sidekick external memory arbiter." hexmask.long 0x0 2.--31. 1. "Reserved_2,Reserved_2" newline bitfld.long 0x0 0.--1. "ARB_PRIO_MODE,Priority mode for external memory access arbiter between GPU scheduler and SLC" "0,1,2,3" line.long 0x4 "RGX_CR_SIDEKICK_EXT_MEM_ARB_CONFIG_1,This register contains the configuration options for the Sidekick external memory arbiter." hexmask.long 0x4 0.--31. 1. "Reserved_2,Reserved_2" line.long 0x8 "RGX_CR_MIPS_WRAPPER_FENCE_0,When writing to this register. the MIPS wrapper holds further transaction from MIPS and emits a memory fence onto the bus" hexmask.long 0x8 1.--31. 1. "Reserved_1,Reserved_1" newline bitfld.long 0x8 0. "SYS_FENCE_ID,reserved address identifier for system fence events" "0,1" line.long 0xC "RGX_CR_MIPS_WRAPPER_FENCE_1,When writing to this register. the MIPS wrapper holds further transaction from MIPS and emits a memory fence onto the bus" hexmask.long 0xC 0.--31. 1. "Reserved_1,Reserved_1" line.long 0x10 "RGX_CR_MIPS_WRAPPER_CONFIG_0,This register contains the configuration options for the MIPS CPU wrapper." hexmask.long.byte 0x10 28.--31. 1. "Reserved_28,Reserved_28" newline bitfld.long 0x10 25.--27. "OS_ID,The default OS_ID of the firmware" "0,1,2,3,4,5,6,7" newline bitfld.long 0x10 24. "TRUSTED,Defines whether these accesses are trusted" "0,1" newline hexmask.long.byte 0x10 17.--23. 1. "Reserved_17,Reserved_17" newline bitfld.long 0x10 16. "BOOT_ISA_MODE,MIPS boot up mode. When set to 0 boot from MIPS32 mode or set to 1 to boot in microMIPS mode" "0,1" newline hexmask.long.word 0x10 0.--15. 1. "REGBANK_BASE_ADDR,16-bit aligned address that identifies rgx register bank transactions emitted from the MIPS core" line.long 0x14 "RGX_CR_MIPS_WRAPPER_CONFIG_1,This register contains the configuration options for the MIPS CPU wrapper." hexmask.long.tbyte 0x14 9.--31. 1. "Reserved_41,Reserved_41" newline bitfld.long 0x14 8. "FW_IDLE_ENABLE,Set to 0x0 overwrites the value of GPU_IDLE to 0x0 set to 0x1 makes GPU Idle dependent on top level idles" "0,1" newline hexmask.long.byte 0x14 2.--7. 1. "Reserved_34,Reserved_34" newline bitfld.long 0x14 1. "DISABLE_BOOT,Stop the MIPS from boot-up even after a soft reset is triggered" "0,1" newline bitfld.long 0x14 0. "L2_CACHE_OFF,Turn off the L2 cache within the MIPS wrapper" "0,1" line.long 0x18 "RGX_CR_MIPS_ADDR_REMAP1_CONFIG1_0,This register contains the address remapping options for the MIPS CPU physical address. e.g. during boot" hexmask.long.tbyte 0x18 12.--31. 1. "BASE_ADDR_IN,4K (12 bits) aligned address used as a input for the address remapping" newline hexmask.long.word 0x18 1.--11. 1. "Reserved_1,Reserved_1" newline bitfld.long 0x18 0. "MODE_ENABLE,Enable address remapping mode" "0,1" line.long 0x1C "RGX_CR_MIPS_ADDR_REMAP1_CONFIG1_1,This register contains the address remapping options for the MIPS CPU physical address. e.g. during boot" hexmask.long 0x1C 0.--31. 1. "Reserved_32,Reserved_32" line.long 0x20 "RGX_CR_MIPS_ADDR_REMAP1_CONFIG2_0,This register contains the address remapping options for the MIPS CPU physical address. e.g. during boot" hexmask.long.tbyte 0x20 12.--31. 1. "ADDR_OUT,4K (12 bits) aligned address used as output for the address remapping" newline bitfld.long 0x20 9.--11. "Reserved_9,Reserved_9" "0,1,2,3,4,5,6,7" newline bitfld.long 0x20 6.--8. "OS_ID,The OS_ID emitted for all address transactions from this region" "0,1,2,3,4,5,6,7" newline bitfld.long 0x20 5. "TRUSTED,Defines whether these accesses are trusted" "0,1" newline hexmask.long.byte 0x20 0.--4. 1. "REGION_SIZE_POW2,Remapped region size or offset size i.e. number of bits from the bottom of the base input address that survive onto the output address. Minimum value of 12" line.long 0x24 "RGX_CR_MIPS_ADDR_REMAP1_CONFIG2_1,This register contains the address remapping options for the MIPS CPU physical address. e.g. during boot" hexmask.long.tbyte 0x24 8.--31. 1. "Reserved_40,Reserved_40" newline hexmask.long.byte 0x24 0.--7. 1. "ADDR_OUT,4K (12 bits) aligned address used as output for the address remapping" line.long 0x28 "RGX_CR_MIPS_ADDR_REMAP2_CONFIG1_0,This register contains the address remapping options for the MIPS CPU physical address. e.g. during boot" hexmask.long.tbyte 0x28 12.--31. 1. "BASE_ADDR_IN,4K (12 bits) aligned address used as a input for the address remapping" newline hexmask.long.word 0x28 1.--11. 1. "Reserved_1,Reserved_1" newline bitfld.long 0x28 0. "MODE_ENABLE,Enable address remapping mode" "0,1" line.long 0x2C "RGX_CR_MIPS_ADDR_REMAP2_CONFIG1_1,This register contains the address remapping options for the MIPS CPU physical address. e.g. during boot" hexmask.long 0x2C 0.--31. 1. "Reserved_32,Reserved_32" line.long 0x30 "RGX_CR_MIPS_ADDR_REMAP2_CONFIG2_0,This register contains the address remapping options for the MIPS CPU physical address. e.g. during boot" hexmask.long.tbyte 0x30 12.--31. 1. "ADDR_OUT,4K (12 bits) aligned address used as output for the address remapping" newline bitfld.long 0x30 9.--11. "Reserved_9,Reserved_9" "0,1,2,3,4,5,6,7" newline bitfld.long 0x30 6.--8. "OS_ID,The OS_ID emitted for all address transactions from this region" "0,1,2,3,4,5,6,7" newline bitfld.long 0x30 5. "TRUSTED,Defines whether these accesses are trusted" "0,1" newline hexmask.long.byte 0x30 0.--4. 1. "REGION_SIZE_POW2,Remapped region size or offset size i.e. number of bits from the bottom of the base input address that survive onto the output address. Minimum value of 12" line.long 0x34 "RGX_CR_MIPS_ADDR_REMAP2_CONFIG2_1,This register contains the address remapping options for the MIPS CPU physical address. e.g. during boot" hexmask.long.tbyte 0x34 8.--31. 1. "Reserved_40,Reserved_40" newline hexmask.long.byte 0x34 0.--7. 1. "ADDR_OUT,4K (12 bits) aligned address used as output for the address remapping" line.long 0x38 "RGX_CR_MIPS_ADDR_REMAP3_CONFIG1_0,This register contains the address remapping options for the MIPS CPU physical address. e.g. during boot" hexmask.long.tbyte 0x38 12.--31. 1. "BASE_ADDR_IN,4K (12 bits) aligned address used as a input for the address remapping" newline hexmask.long.word 0x38 1.--11. 1. "Reserved_1,Reserved_1" newline bitfld.long 0x38 0. "MODE_ENABLE,Enable address remapping mode" "0,1" line.long 0x3C "RGX_CR_MIPS_ADDR_REMAP3_CONFIG1_1,This register contains the address remapping options for the MIPS CPU physical address. e.g. during boot" hexmask.long 0x3C 0.--31. 1. "Reserved_32,Reserved_32" line.long 0x40 "RGX_CR_MIPS_ADDR_REMAP3_CONFIG2_0,This register contains the address remapping options for the MIPS CPU physical address. e.g. during boot" hexmask.long.tbyte 0x40 12.--31. 1. "ADDR_OUT,4K (12 bits) aligned address used as output for the address remapping" newline bitfld.long 0x40 9.--11. "Reserved_9,Reserved_9" "0,1,2,3,4,5,6,7" newline bitfld.long 0x40 6.--8. "OS_ID,The OS_ID emitted for all address transactions from this region" "0,1,2,3,4,5,6,7" newline bitfld.long 0x40 5. "TRUSTED,Defines whether these accesses are trusted" "0,1" newline hexmask.long.byte 0x40 0.--4. 1. "REGION_SIZE_POW2,Remapped region size or offset size i.e. number of bits from the bottom of the base input address that survive onto the output address. Minimum value of 12" line.long 0x44 "RGX_CR_MIPS_ADDR_REMAP3_CONFIG2_1,This register contains the address remapping options for the MIPS CPU physical address. e.g. during boot" hexmask.long.tbyte 0x44 8.--31. 1. "Reserved_40,Reserved_40" newline hexmask.long.byte 0x44 0.--7. 1. "ADDR_OUT,4K (12 bits) aligned address used as output for the address remapping" line.long 0x48 "RGX_CR_MIPS_ADDR_REMAP4_CONFIG1_0,This register contains the address remapping options for the MIPS CPU physical address. e.g. during boot" hexmask.long.tbyte 0x48 12.--31. 1. "BASE_ADDR_IN,4K (12 bits) aligned address used as a input for the address remapping" newline hexmask.long.word 0x48 1.--11. 1. "Reserved_1,Reserved_1" newline bitfld.long 0x48 0. "MODE_ENABLE,Enable address remapping mode" "0,1" line.long 0x4C "RGX_CR_MIPS_ADDR_REMAP4_CONFIG1_1,This register contains the address remapping options for the MIPS CPU physical address. e.g. during boot" hexmask.long 0x4C 0.--31. 1. "Reserved_32,Reserved_32" line.long 0x50 "RGX_CR_MIPS_ADDR_REMAP4_CONFIG2_0,This register contains the address remapping options for the MIPS CPU physical address. e.g. during boot" hexmask.long.tbyte 0x50 12.--31. 1. "ADDR_OUT,4K (12 bits) aligned address used as output for the address remapping" newline bitfld.long 0x50 9.--11. "Reserved_9,Reserved_9" "0,1,2,3,4,5,6,7" newline bitfld.long 0x50 6.--8. "OS_ID,The OS_ID emitted for all address transactions from this region" "0,1,2,3,4,5,6,7" newline bitfld.long 0x50 5. "TRUSTED,Defines whether these accesses are trusted" "0,1" newline hexmask.long.byte 0x50 0.--4. 1. "REGION_SIZE_POW2,Remapped region size or offset size i.e. number of bits from the bottom of the base input address that survive onto the output address. Minimum value of 12" line.long 0x54 "RGX_CR_MIPS_ADDR_REMAP4_CONFIG2_1,This register contains the address remapping options for the MIPS CPU physical address. e.g. during boot" hexmask.long.tbyte 0x54 8.--31. 1. "Reserved_40,Reserved_40" newline hexmask.long.byte 0x54 0.--7. 1. "ADDR_OUT,4K (12 bits) aligned address used as output for the address remapping" line.long 0x58 "RGX_CR_MIPS_ADDR_REMAP5_CONFIG1_0,This register contains the address remapping options for the MIPS CPU physical address. e.g. during boot" hexmask.long.tbyte 0x58 12.--31. 1. "BASE_ADDR_IN,4K (12 bits) aligned address used as a input for the address remapping" newline hexmask.long.word 0x58 1.--11. 1. "Reserved_1,Reserved_1" newline bitfld.long 0x58 0. "MODE_ENABLE,Enable address remapping mode" "0,1" line.long 0x5C "RGX_CR_MIPS_ADDR_REMAP5_CONFIG1_1,This register contains the address remapping options for the MIPS CPU physical address. e.g. during boot" hexmask.long 0x5C 0.--31. 1. "Reserved_32,Reserved_32" line.long 0x60 "RGX_CR_MIPS_ADDR_REMAP5_CONFIG2_0,This register contains the address remapping options for the MIPS CPU physical address. e.g. during boot" hexmask.long.tbyte 0x60 12.--31. 1. "ADDR_OUT,4K (12 bits) aligned address used as output for the address remapping" newline bitfld.long 0x60 9.--11. "Reserved_9,Reserved_9" "0,1,2,3,4,5,6,7" newline bitfld.long 0x60 6.--8. "OS_ID,The OS_ID emitted for all address transactions from this region" "0,1,2,3,4,5,6,7" newline bitfld.long 0x60 5. "TRUSTED,Defines whether these accesses are trusted" "0,1" newline hexmask.long.byte 0x60 0.--4. 1. "REGION_SIZE_POW2,Remapped region size or offset size i.e. number of bits from the bottom of the base input address that survive onto the output address. Minimum value of 12" line.long 0x64 "RGX_CR_MIPS_ADDR_REMAP5_CONFIG2_1,This register contains the address remapping options for the MIPS CPU physical address. e.g. during boot" hexmask.long.tbyte 0x64 8.--31. 1. "Reserved_40,Reserved_40" newline hexmask.long.byte 0x64 0.--7. 1. "ADDR_OUT,4K (12 bits) aligned address used as output for the address remapping" rgroup.long 0x868++0x7 line.long 0x0 "RGX_CR_MIPS_ADDR_REMAP_UNMAPPED_STATUS_0,This register contains the unmapped exception status information of the MIPS GPU scheduler." hexmask.long 0x0 0.--31. 1. "ADDRESS,Unmapped MIPS physical address" line.long 0x4 "RGX_CR_MIPS_ADDR_REMAP_UNMAPPED_STATUS_1,This register contains the unmapped exception status information of the MIPS GPU scheduler." hexmask.long 0x4 1.--31. 1. "Reserved_33,Reserved_33" newline bitfld.long 0x4 0. "EVENT,An address from the MIPS was not remapped to a new range in the GPU" "0,1" wgroup.long 0x870++0x7 line.long 0x0 "RGX_CR_MIPS_ADDR_REMAP_UNMAPPED_CLEAR_0,This register contains the configuration options for the MIPS unmapped exception." hexmask.long 0x0 1.--31. 1. "Reserved_1,Reserved_1" newline bitfld.long 0x0 0. "EVENT,Clears the unmapped exception event" "0,1" line.long 0x4 "RGX_CR_MIPS_ADDR_REMAP_UNMAPPED_CLEAR_1,This register contains the configuration options for the MIPS unmapped exception." hexmask.long 0x4 0.--31. 1. "Reserved_1,Reserved_1" group.long 0x878++0x7 line.long 0x0 "RGX_CR_MIPS_ADDR_REMAP_RANGE_CONFIG_0,This register contains the address remapping options for the MIPS CPU physical address. e.g. during boot" hexmask.long.tbyte 0x0 12.--31. 1. "BASE_ADDR_IN,4K (12 bits) aligned address used as a input for the address remapping" newline bitfld.long 0x0 11. "TRUSTED,Defines whether these accesses are trusted" "0,1" newline hexmask.long.byte 0x0 7.--10. 1. "REGION_SIZE,Remapped region size" newline bitfld.long 0x0 6. "Reserved_6,Reserved_6" "0,1" newline hexmask.long.byte 0x0 1.--5. 1. "ENTRY,Select remap entry to configure. Valid range of Entry 0-31" newline bitfld.long 0x0 0. "MODE_ENABLE,When set configure the entry" "0,1" line.long 0x4 "RGX_CR_MIPS_ADDR_REMAP_RANGE_CONFIG_1,This register contains the address remapping options for the MIPS CPU physical address. e.g. during boot" hexmask.long 0x4 4.--31. 1. "ADDR_OUT,4K (12 bits) aligned address used as output for the address remapping" newline bitfld.long 0x4 3. "Reserved_35,Reserved_35" "0,1" newline bitfld.long 0x4 0.--2. "OS_ID,The OS_ID emitted for all address transactions from this region" "0,1,2,3,4,5,6,7" wgroup.long 0x880++0x7 line.long 0x0 "RGX_CR_MIPS_ADDR_REMAP_RANGE_READ_0,This register contains the configuration options for the MIPS remap register read interface." hexmask.long 0x0 6.--31. 1. "Reserved_6,Reserved_6" newline hexmask.long.byte 0x0 1.--5. 1. "ENTRY,MIPS address remap entry to read" newline bitfld.long 0x0 0. "REQUEST,Issue a read request to the MIPS address remap range entries" "0,1" line.long 0x4 "RGX_CR_MIPS_ADDR_REMAP_RANGE_READ_1,This register contains the configuration options for the MIPS remap register read interface." hexmask.long 0x4 0.--31. 1. "Reserved_6,Reserved_6" rgroup.long 0x888++0x7 line.long 0x0 "RGX_CR_MIPS_ADDR_REMAP_RANGE_DATA_0,This register contains the remapping entry information for the MIPS remap register read interface." hexmask.long.tbyte 0x0 12.--31. 1. "BASE_ADDR_IN,4K (12 bits) aligned address used as a input for the address remapping" newline bitfld.long 0x0 11. "TRUSTED,Defines whether these accesses are trusted" "0,1" newline hexmask.long.byte 0x0 7.--10. 1. "REGION_SIZE,Remapped region size" newline hexmask.long.byte 0x0 1.--6. 1. "Reserved_1,Reserved_1" newline bitfld.long 0x0 0. "MODE_ENABLE,When set configures the entry" "0,1" line.long 0x4 "RGX_CR_MIPS_ADDR_REMAP_RANGE_DATA_1,This register contains the remapping entry information for the MIPS remap register read interface." hexmask.long 0x4 4.--31. 1. "ADDR_OUT,4K (12 bits) aligned address used as output for the address remapping" newline bitfld.long 0x4 3. "Reserved_35,Reserved_35" "0,1" newline bitfld.long 0x4 0.--2. "OS_ID,The OS_ID emitted for all address transactions from this region" "0,1,2,3,4,5,6,7" group.long 0x8A0++0xF line.long 0x0 "RGX_CR_MIPS_WRAPPER_IRQ_ENABLE_0,This register contains the configuration options for the RGX firmware interrupts to HOST." hexmask.long 0x0 1.--31. 1. "Reserved_1,Reserved_1" newline bitfld.long 0x0 0. "EVENT,Allow RGX firmware to send interrupts to HOST" "0,1" line.long 0x4 "RGX_CR_MIPS_WRAPPER_IRQ_ENABLE_1,This register contains the configuration options for the RGX firmware interrupts to HOST." hexmask.long 0x4 0.--31. 1. "Reserved_1,Reserved_1" line.long 0x8 "RGX_CR_MIPS_WRAPPER_IRQ_STATUS_0,This register contains the configuration options for the RGX firmware interrupts to HOST." hexmask.long 0x8 1.--31. 1. "Reserved_1,Reserved_1" newline bitfld.long 0x8 0. "EVENT,Indicates an outstanding interrupt to HOST from RGX firmware" "0,1" line.long 0xC "RGX_CR_MIPS_WRAPPER_IRQ_STATUS_1,This register contains the configuration options for the RGX firmware interrupts to HOST." hexmask.long 0xC 0.--31. 1. "Reserved_1,Reserved_1" wgroup.long 0x8B0++0x7 line.long 0x0 "RGX_CR_MIPS_WRAPPER_IRQ_CLEAR_0,This register contains the configuration options for the RGX firmware interrupts to HOST." hexmask.long 0x0 1.--31. 1. "Reserved_1,Reserved_1" newline bitfld.long 0x0 0. "EVENT,Clears the interrupt event to HOST from RGX firmware" "0,1" line.long 0x4 "RGX_CR_MIPS_WRAPPER_IRQ_CLEAR_1,This register contains the configuration options for the RGX firmware interrupts to HOST." hexmask.long 0x4 0.--31. 1. "Reserved_1,Reserved_1" group.long 0x8B8++0x7 line.long 0x0 "RGX_CR_MIPS_WRAPPER_NMI_ENABLE_0,This register contains the configuration options for the RGX firmware non-maskable interrupts to MIPS." hexmask.long 0x0 1.--31. 1. "Reserved_1,Reserved_1" newline bitfld.long 0x0 0. "EVENT,Allow RGX firmware to send non-maskable interrupts to MIPS" "0,1" line.long 0x4 "RGX_CR_MIPS_WRAPPER_NMI_ENABLE_1,This register contains the configuration options for the RGX firmware non-maskable interrupts to MIPS." hexmask.long 0x4 0.--31. 1. "Reserved_1,Reserved_1" wgroup.long 0x8C0++0x7 line.long 0x0 "RGX_CR_MIPS_WRAPPER_NMI_EVENT_0,This register contains the configuration options for the RGX firmware non-maskable interrupts to MIPS." hexmask.long 0x0 1.--31. 1. "Reserved_1,Reserved_1" newline bitfld.long 0x0 0. "TRIGGER,Issue a non-maskable interrupt to the MIPS SI_NMI pin from RGX firmware" "0,1" line.long 0x4 "RGX_CR_MIPS_WRAPPER_NMI_EVENT_1,This register contains the configuration options for the RGX firmware non-maskable interrupts to MIPS." hexmask.long 0x4 0.--31. 1. "Reserved_1,Reserved_1" group.long 0x8C8++0x7 line.long 0x0 "RGX_CR_MIPS_DEBUG_CONFIG_0,This register contains the security and debug configuration options for the MIPS GPU scheduler." hexmask.long 0x0 1.--31. 1. "Reserved_1,Reserved_1" newline bitfld.long 0x0 0. "DISABLE_PROBE_DEBUG,Enable MIPS SecureDebug. Disables EJTAG access to the MIPS core and PC Sampling" "0,1" line.long 0x4 "RGX_CR_MIPS_DEBUG_CONFIG_1,This register contains the security and debug configuration options for the MIPS GPU scheduler." hexmask.long 0x4 0.--31. 1. "Reserved_1,Reserved_1" rgroup.long 0x8D0++0x7 line.long 0x0 "RGX_CR_MIPS_EXCEPTION_STATUS_0,This register contains the exception status information of the MIPS GPU scheduler." hexmask.long 0x0 6.--31. 1. "Reserved_6,Reserved_6" newline bitfld.long 0x0 5. "SI_SLEEP,Reflects the status of the MIPS SI_Sleep pin" "0,1" newline bitfld.long 0x0 4. "SI_NMI_TAKEN,Reflects the status of the MIPS SI_NMITaken pin" "0,1" newline bitfld.long 0x0 3. "SI_NEST_EXL,Reflects the status of the MIPS SI_NESTEXL pin" "0,1" newline bitfld.long 0x0 2. "SI_NEST_ERL,Reflects the status of the MIPS SI_NESTERL pin" "0,1" newline bitfld.long 0x0 1. "SI_EXL,Reflects the status of the MIPS SI_EXL pin" "0,1" newline bitfld.long 0x0 0. "SI_ERL,Reflects the status of the MIPS SI_ERL pin" "0,1" line.long 0x4 "RGX_CR_MIPS_EXCEPTION_STATUS_1,This register contains the exception status information of the MIPS GPU scheduler." hexmask.long 0x4 0.--31. 1. "Reserved_6,Reserved_6" group.long 0x8D8++0xF line.long 0x0 "RGX_CR_MIPS_WRAPPER_FENCE_CONFIG_0,This register contains the fence configuration options for when MIPS emits a memory fence onto the bus" hexmask.long.tbyte 0x0 12.--31. 1. "BASE_ADDR,4K (12 bits) aligned address that serves as the external memory fence base address" newline hexmask.long.byte 0x0 4.--11. 1. "Reserved_4,Reserved_4" newline bitfld.long 0x0 1.--3. "OS_ID,OS_ID of the emitted fence" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 0. "TRUSTED,Defines whether these accesses are trusted" "0,1" line.long 0x4 "RGX_CR_MIPS_WRAPPER_FENCE_CONFIG_1,This register contains the fence configuration options for when MIPS emits a memory fence onto the bus" hexmask.long.tbyte 0x4 8.--31. 1. "Reserved_40,Reserved_40" newline hexmask.long.byte 0x4 0.--7. 1. "BASE_ADDR,4K (12 bits) aligned address that serves as the external memory fence base address" line.long 0x8 "RGX_CR_MIPS_WRAPPER_CACHE_INVAL_0,A write of '1' to this register invalidates the MIPS wrapper L2 cache The cache hardware will clear this bit when the invalidation operation completes" hexmask.long 0x8 1.--31. 1. "Reserved_1,Reserved_1" newline bitfld.long 0x8 0. "PENDING,MIPS wrapper L2 cache is being invalidated" "0,1" line.long 0xC "RGX_CR_MIPS_WRAPPER_CACHE_INVAL_1,A write of '1' to this register invalidates the MIPS wrapper L2 cache The cache hardware will clear this bit when the invalidation operation completes" hexmask.long 0xC 0.--31. 1. "Reserved_1,Reserved_1" rgroup.long 0x8E8++0x7 line.long 0x0 "RGX_CR_MIPS_WRAPPER_STATUS_0,This register contains status information of the MIPS GPU scheduler." hexmask.long.tbyte 0x0 8.--31. 1. "Reserved_8,Reserved_8" newline hexmask.long.byte 0x0 0.--7. 1. "OUTSTANDING_REQUESTS,Outstanding requests by the MIPS" line.long 0x4 "RGX_CR_MIPS_WRAPPER_STATUS_1,This register contains status information of the MIPS GPU scheduler." hexmask.long 0x4 0.--31. 1. "Reserved_8,Reserved_8" group.long 0x900++0x17 line.long 0x0 "RGX_CR_EVENT_TDM_PDS_CODE_0,PDS code segment address for 2D End-of-Tile event shader." hexmask.long 0x0 4.--31. 1. "ADDR,PDS Execution Address for pixel tasks (Positioned as a byte address 128 bit granularity) 4 GB Range" newline hexmask.long.byte 0x0 0.--3. 1. "Reserved_0,Reserved_0" line.long 0x4 "RGX_CR_EVENT_TDM_PDS_CODE_1,PDS code segment address for 2D End-of-Tile event shader." hexmask.long 0x4 0.--31. 1. "Reserved_32,Reserved_32" line.long 0x8 "RGX_CR_EVENT_TDM_PDS_DATA_0,RGX_CR_EVENT_TDM_PDS_DATA_0" hexmask.long 0x8 4.--31. 1. "ADDR,PDS Execution Address for pixel tasks (Positioned as a byte address 128 bit granularity) 4 GB Range" newline hexmask.long.byte 0x8 0.--3. 1. "Reserved_0,Reserved_0" line.long 0xC "RGX_CR_EVENT_TDM_PDS_DATA_1,RGX_CR_EVENT_TDM_PDS_DATA_1" hexmask.long 0xC 0.--31. 1. "Reserved_32,Reserved_32" line.long 0x10 "RGX_CR_EVENT_TDM_PDS_INFO_0,RGX_CR_EVENT_TDM_PDS_INFO_0" hexmask.long.word 0x10 16.--31. 1. "Reserved_16,Reserved_16" newline hexmask.long.byte 0x10 10.--15. 1. "USC_SR_SIZE,USC Shared Register Data Size in 4x128 bit words (0=0) for pixel event task if zero pixel event task is skipped" newline hexmask.long.byte 0x10 5.--9. 1. "TEMP_STRIDE,PDS Temp Size in 64 bit words (0=0) for pixel event tasks" newline hexmask.long.byte 0x10 0.--4. 1. "CONST_SIZE,PDS Data Size in 128 bit words (0=0) for pixel event tasks if zero pixel event task is skipped" line.long 0x14 "RGX_CR_EVENT_TDM_PDS_INFO_1,RGX_CR_EVENT_TDM_PDS_INFO_1" hexmask.long 0x14 0.--31. 1. "Reserved_16,Reserved_16" repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) group.long ($2+0x918)++0x3 line.long 0x0 "RGX_CR_PDS_TDM_BGRND0_BASE_$1,PDS Background Setup Word 0" hexmask.long 0x0 4.--31. 1. "SHADER_ADDR,The pixel shader base is the base address of the PDS Data Segment. The code segment is address is PDS_PIXEL_SHADERBASE + PDS_PIXELSHADERSIZE. The pixel shader program issues the DOUTU for the Fragment Shader only." newline hexmask.long.byte 0x0 0.--3. 1. "Reserved_0,Reserved_0" repeat.end repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) group.long ($2+0x920)++0x3 line.long 0x0 "RGX_CR_PDS_TDM_BGRND1_BASE_$1,PDS Background Setup Word 1" hexmask.long 0x0 4.--31. 1. "VARYING_ADDR,This is the base address of the PDS Data Segment. The code segment is address is PDS_VARYINGBASE + PDS_VARYINGSIZE (PDS_BGRND_SIZEINFO1)." newline hexmask.long.byte 0x0 0.--3. 1. "Reserved_0,Reserved_0" repeat.end group.long 0x928++0xF line.long 0x0 "RGX_CR_PDS_TDM_BGRND2_BASE_0,PDS Background Setup Word 2" hexmask.long 0x0 4.--31. 1. "UNIFORMDATA_ADDR,This points to the DMAs to load the Uniforms (or contains the Uniforms with DOUTW commands)" newline hexmask.long.byte 0x0 0.--3. 1. "Reserved_0,Reserved_0" line.long 0x4 "RGX_CR_PDS_TDM_BGRND2_BASE_1,PDS Background Setup Word 2" hexmask.long 0x4 0.--31. 1. "Reserved_32,Reserved_32" line.long 0x8 "RGX_CR_PDS_TDM_BGRND3_SIZEINFO_0,If any of the size fields are 0. then that program will not be run. PDS_BGRND_PIXELSHADERSIZE is always 2 128 Bit Words" hexmask.long.byte 0x8 27.--31. 1. "PDS_BATCHNUM,The batch ID to be associated with the background" newline hexmask.long.byte 0x8 21.--26. 1. "PDS_UNIFORMSIZE,The size of the Uniform PDS Data Segment in 128 bit words 0=0. 32 max" newline hexmask.long.byte 0x8 15.--20. 1. "PDS_TEXTURESTATESIZE,The size of the Texture PDS Data Segment in 128 bit words 0=0 32 max" newline hexmask.long.byte 0x8 9.--14. 1. "PDS_VARYINGSIZE,The size of the Varying/Coefficient PDS Data Segment in 128 bit words 0=0 32 max" newline hexmask.long.word 0x8 0.--8. 1. "USC_VARYINGSIZE,The size of the Varying/Coefficient USC Common Store Data in 4x128 bit words 0=0. 256 max" line.long 0xC "RGX_CR_PDS_TDM_BGRND3_SIZEINFO_1,If any of the size fields are 0. then that program will not be run. PDS_BGRND_PIXELSHADERSIZE is always 2 128 Bit Words" hexmask.long.word 0xC 23.--31. 1. "Reserved_55,Reserved_55" newline hexmask.long.word 0xC 14.--22. 1. "USC_SHAREDSIZE,The common store allocation size for the shared registers (texture and uniform data commbined) 256 chunks max" newline hexmask.long.byte 0xC 9.--13. 1. "PDS_TEMPSIZE,0 = 0 64 bit words 1 = 1 64 bit word 248 bytes. This applies to coefficient uniform and texture state updates." newline hexmask.long.word 0xC 0.--8. 1. "PDS_BATCHNUM,The batch ID to be associated with the background" group.long 0xB00++0xF line.long 0x0 "RGX_CR_MTS_SCHEDULE_0,This register allows firmware tasks to be scheduled on the META (Garten) core." hexmask.long.tbyte 0x0 9.--31. 1. "Reserved_9,Reserved_9" newline bitfld.long 0x0 8. "HOST,Host Interrupte kick" "0,1" newline bitfld.long 0x0 6.--7. "PRIORITY,DataMaster Priority" "0,1,2,3" newline bitfld.long 0x0 5. "CONTEXT,CONTEXT" "0,1" newline bitfld.long 0x0 4. "TASK,TASK" "0,1" newline hexmask.long.byte 0x0 0.--3. 1. "DM,DataMaster Type" line.long 0x4 "RGX_CR_MTS_SCHEDULE_1,This register allows firmware tasks to be scheduled on the META (Garten) core." hexmask.long 0x4 0.--31. 1. "Reserved_9,Reserved_9" line.long 0x8 "RGX_CR_MTS_PROC_COMPLETE_0,This register allows firmware tasks to signal process completion." hexmask.long 0x8 2.--31. 1. "Reserved_2,Reserved_2" newline bitfld.long 0x8 1. "CONTEXT,CONTEXT" "0,1" newline bitfld.long 0x8 0. "THREAD,Thread number. This is filled in by hardware and can have any value" "0,1" line.long 0xC "RGX_CR_MTS_PROC_COMPLETE_1,This register allows firmware tasks to signal process completion." hexmask.long 0xC 0.--31. 1. "Reserved_2,Reserved_2" rgroup.long 0xB10++0x1F line.long 0x0 "RGX_CR_MTS_BGCTX_SBDATA0_0,This register contains the sideband data for the process running on the background context of thread 0. Reads of this register will be redirected to the correct. thread specific register by hardware." hexmask.long.tbyte 0x0 9.--31. 1. "Reserved_9,Reserved_9" newline bitfld.long 0x0 6.--8. "OS_ID,The OS_ID of the active thread" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 5. "THREAD_ACTIVE,Indicates the thread is active" "0,1" newline bitfld.long 0x0 4. "TASK,TASK" "0,1" newline hexmask.long.byte 0x0 0.--3. 1. "DM,DataMaster Type" line.long 0x4 "RGX_CR_MTS_BGCTX_SBDATA0_1,This register contains the sideband data for the process running on the background context of thread 0. Reads of this register will be redirected to the correct. thread specific register by hardware." hexmask.long 0x4 0.--31. 1. "Reserved_9,Reserved_9" line.long 0x8 "RGX_CR_MTS_BGCTX_SBDATA1_0,This register contains the sideband data for the process running on the background context of thread 1. Reads of this register will be redirected to the correct. thread specific register by hardware." hexmask.long.tbyte 0x8 9.--31. 1. "Reserved_9,Reserved_9" newline bitfld.long 0x8 6.--8. "OS_ID,The OS_ID of the active thread" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 5. "THREAD_ACTIVE,Indicates the thread is active" "0,1" newline bitfld.long 0x8 4. "TASK,TASK" "0,1" newline hexmask.long.byte 0x8 0.--3. 1. "DM,DataMaster Type" line.long 0xC "RGX_CR_MTS_BGCTX_SBDATA1_1,This register contains the sideband data for the process running on the background context of thread 1. Reads of this register will be redirected to the correct. thread specific register by hardware." hexmask.long 0xC 0.--31. 1. "Reserved_9,Reserved_9" line.long 0x10 "RGX_CR_MTS_INTCTX_SBDATA0_0,This register contains the sideband data for the process running on the interrupt context of thread 0. Reads of this register will be redirected to the correct. thread specific register by hardware." hexmask.long 0x10 6.--31. 1. "INT_STATUS,Interrupt Status for 32 event bus lines" newline hexmask.long.byte 0x10 2.--5. 1. "DM,DataMaster Type" newline bitfld.long 0x10 0.--1. "INT_TASK,Kick Request for timer/BG-request/host" "0,1,2,3" line.long 0x14 "RGX_CR_MTS_INTCTX_SBDATA0_1,This register contains the sideband data for the process running on the interrupt context of thread 0. Reads of this register will be redirected to the correct. thread specific register by hardware." hexmask.long.tbyte 0x14 10.--31. 1. "Reserved_42,Reserved_42" newline bitfld.long 0x14 7.--9. "OS_ID,The OS_ID of the active thread" "0,1,2,3,4,5,6,7" newline bitfld.long 0x14 6. "THREAD_ACTIVE,Indicates the thread is active" "0,1" newline hexmask.long.byte 0x14 0.--5. 1. "INT_STATUS,Interrupt Status for 32 event bus lines" line.long 0x18 "RGX_CR_MTS_INTCTX_SBDATA1_0,This register contains the sideband data for the process running on the interrupt context of thread 1. Reads of this register will be redirected to the correct. thread specific register by hardware." hexmask.long 0x18 6.--31. 1. "INT_STATUS,Interrupt Status for 32 event bus lines" newline hexmask.long.byte 0x18 2.--5. 1. "DM,DataMaster Type" newline bitfld.long 0x18 0.--1. "INT_TASK,Kick Request for timer/BG-request/host" "0,1,2,3" line.long 0x1C "RGX_CR_MTS_INTCTX_SBDATA1_1,This register contains the sideband data for the process running on the interrupt context of thread 1. Reads of this register will be redirected to the correct. thread specific register by hardware." hexmask.long.tbyte 0x1C 10.--31. 1. "Reserved_42,Reserved_42" newline bitfld.long 0x1C 7.--9. "OS_ID,The OS_ID of the active thread" "0,1,2,3,4,5,6,7" newline bitfld.long 0x1C 6. "THREAD_ACTIVE,Indicates the thread is active" "0,1" newline hexmask.long.byte 0x1C 0.--5. 1. "INT_STATUS,Interrupt Status for 32 event bus lines" group.long 0xB30++0x27 line.long 0x0 "RGX_CR_MTS_BGCTX_THREAD0_DM_ASSOC_0,This register is the DataMaster assocation for the background context of thread 0. Bit high represents DataMaster being permitted to run on the background context of thread 0." hexmask.long.word 0x0 16.--31. 1. "Reserved_16,Reserved_16" newline hexmask.long.word 0x0 0.--15. 1. "DM_ASSOC,DataMaster Association (Active High)" line.long 0x4 "RGX_CR_MTS_BGCTX_THREAD0_DM_ASSOC_1,This register is the DataMaster assocation for the background context of thread 0. Bit high represents DataMaster being permitted to run on the background context of thread 0." hexmask.long 0x4 0.--31. 1. "Reserved_16,Reserved_16" line.long 0x8 "RGX_CR_MTS_BGCTX_THREAD1_DM_ASSOC_0,This register is the DataMaster assocation for the background context of thread 1. Bit high represents DataMaster being permitted to run on the background context of thread 1." hexmask.long.word 0x8 16.--31. 1. "Reserved_16,Reserved_16" newline hexmask.long.word 0x8 0.--15. 1. "DM_ASSOC,DataMaster Association (Active High)" line.long 0xC "RGX_CR_MTS_BGCTX_THREAD1_DM_ASSOC_1,This register is the DataMaster assocation for the background context of thread 1. Bit high represents DataMaster being permitted to run on the background context of thread 1." hexmask.long 0xC 0.--31. 1. "Reserved_16,Reserved_16" line.long 0x10 "RGX_CR_MTS_INTCTX_THREAD0_DM_ASSOC_0,This register is the DataMaster assocation for the interrupt context of thread 0. Bit high represents DataMaster being permitted to run on the interrupt context of thread 0." hexmask.long.word 0x10 16.--31. 1. "Reserved_16,Reserved_16" newline hexmask.long.word 0x10 0.--15. 1. "DM_ASSOC,DataMaster Association (Active High)" line.long 0x14 "RGX_CR_MTS_INTCTX_THREAD0_DM_ASSOC_1,This register is the DataMaster assocation for the interrupt context of thread 0. Bit high represents DataMaster being permitted to run on the interrupt context of thread 0." hexmask.long 0x14 0.--31. 1. "Reserved_16,Reserved_16" line.long 0x18 "RGX_CR_MTS_INTCTX_THREAD1_DM_ASSOC_0,This register is the DataMaster assocation for the interrupt context of thread 1. Bit high represents DataMaster being permitted to run on the interrupt context of thread 1." hexmask.long.word 0x18 16.--31. 1. "Reserved_16,Reserved_16" newline hexmask.long.word 0x18 0.--15. 1. "DM_ASSOC,DataMaster Association (Active High)" line.long 0x1C "RGX_CR_MTS_INTCTX_THREAD1_DM_ASSOC_1,This register is the DataMaster assocation for the interrupt context of thread 1. Bit high represents DataMaster being permitted to run on the interrupt context of thread 1." hexmask.long 0x1C 0.--31. 1. "Reserved_16,Reserved_16" line.long 0x20 "RGX_CR_MTS_GARTEN_WRAPPER_CONFIG_0,This register contains the configuration options for the Garten wrapper." hexmask.long.tbyte 0x20 12.--31. 1. "FENCE_ADDR,4k page address to be used for fence requests" newline hexmask.long.word 0x20 1.--11. 1. "Reserved_1,Reserved_1" newline bitfld.long 0x20 0. "IDLE_CTRL,IDLE_CTRL" "0,1" line.long 0x24 "RGX_CR_MTS_GARTEN_WRAPPER_CONFIG_1,This register contains the configuration options for the Garten wrapper." hexmask.long.word 0x24 16.--31. 1. "Reserved_48,Reserved_48" newline hexmask.long.byte 0x24 12.--15. 1. "FENCE_PC_BASE,Page Catalogue base address number to be used for fence requests" newline hexmask.long.byte 0x24 8.--11. 1. "FENCE_DM,Data master value to be used for fence requests" newline hexmask.long.byte 0x24 0.--7. 1. "FENCE_ADDR,4k page address to be used for fence requests" repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) group.long ($2+0xB58)++0x3 line.long 0x0 "RGX_CR_MTS_DM0_INTERRUPT_ENABLE_$1,Interrupt enable status register for DataMaster 0" hexmask.long 0x0 0.--31. 1. "INT_ENABLE,Interrupt Enable" repeat.end repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) group.long ($2+0xB60)++0x3 line.long 0x0 "RGX_CR_MTS_DM1_INTERRUPT_ENABLE_$1,Interrupt enable status register for DataMaster 1" hexmask.long 0x0 0.--31. 1. "INT_ENABLE,Interrupt Enable" repeat.end repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) group.long ($2+0xB68)++0x3 line.long 0x0 "RGX_CR_MTS_DM2_INTERRUPT_ENABLE_$1,Interrupt enable status register for DataMaster 2" hexmask.long 0x0 0.--31. 1. "INT_ENABLE,Interrupt Enable" repeat.end repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) group.long ($2+0xB70)++0x3 line.long 0x0 "RGX_CR_MTS_DM3_INTERRUPT_ENABLE_$1,Interrupt enable status register for DataMaster 3" hexmask.long 0x0 0.--31. 1. "INT_ENABLE,Interrupt Enable" repeat.end repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) group.long ($2+0xB78)++0x3 line.long 0x0 "RGX_CR_MTS_DM4_INTERRUPT_ENABLE_$1,Interrupt enable status register for DataMaster 4" hexmask.long 0x0 0.--31. 1. "INT_ENABLE,Interrupt Enable" repeat.end repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) group.long ($2+0xB80)++0x3 line.long 0x0 "RGX_CR_MTS_DM5_INTERRUPT_ENABLE_$1,Interrupt enable status register for DataMaster 5" hexmask.long 0x0 0.--31. 1. "INT_ENABLE,Interrupt Enable" repeat.end repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) group.long ($2+0xB88)++0x3 line.long 0x0 "RGX_CR_MTS_EVENT_MASK_$1,Mask interrupt events" hexmask.long 0x0 0.--31. 1. "MASK,DESCRIPTION" repeat.end repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) wgroup.long ($2+0xB90)++0x3 line.long 0x0 "RGX_CR_MTS_EVENT_CLEAR_$1,Clear internal interrupt registers" hexmask.long 0x0 0.--31. 1. "CLEAR,DESCRIPTION" repeat.end rgroup.long 0xB98++0x17 line.long 0x0 "RGX_CR_MTS_INTCTX_0,This register contains the sideband data for the MTS internal interrupt context registers" bitfld.long 0x0 30.--31. "Reserved_30,Reserved_30" "0,1,2,3" newline hexmask.long.byte 0x0 22.--29. 1. "DM_HOST_SCHEDULE,A 1 bit counter per DM for host requests" newline hexmask.long.byte 0x0 16.--21. 1. "Reserved_16,Reserved_16" newline hexmask.long.byte 0x0 8.--15. 1. "DM_TIMER_SCHEDULE,A 1 bit counter per DM for timer requests" newline hexmask.long.byte 0x0 0.--7. 1. "DM_INTERRUPT_SCHEDULE,A 1 bit counter per DM for interrupt requests" line.long 0x4 "RGX_CR_MTS_INTCTX_1,This register contains the sideband data for the MTS internal interrupt context registers" hexmask.long 0x4 0.--31. 1. "Reserved_30,Reserved_30" line.long 0x8 "RGX_CR_MTS_BGCTX_0,This register contains the sideband data for the MTS internal background context registers" hexmask.long.tbyte 0x8 8.--31. 1. "Reserved_8,Reserved_8" newline hexmask.long.byte 0x8 0.--7. 1. "DM_NONCOUNTED_SCHEDULE,A 1 bit counter per DM for non-counted background request" line.long 0xC "RGX_CR_MTS_BGCTX_1,This register contains the sideband data for the MTS internal background context registers" hexmask.long 0xC 0.--31. 1. "Reserved_8,Reserved_8" line.long 0x10 "RGX_CR_MTS_BGCTX_COUNTED_SCHEDULE_0,This register contains the sideband data for the MTS internal counted background context counters" hexmask.long.byte 0x10 24.--31. 1. "DM3,A 8 bit counter for DM3" newline hexmask.long.byte 0x10 16.--23. 1. "DM2,A 8 bit counter for DM2" newline hexmask.long.byte 0x10 8.--15. 1. "DM1,A 8 bit counter for DM1" newline hexmask.long.byte 0x10 0.--7. 1. "DM0,A 8 bit counter for DM0" line.long 0x14 "RGX_CR_MTS_BGCTX_COUNTED_SCHEDULE_1,This register contains the sideband data for the MTS internal counted background context counters" hexmask.long.word 0x14 16.--31. 1. "Reserved_48,Reserved_48" newline hexmask.long.byte 0x14 8.--15. 1. "DM5,A 8 bit counter for DM5" newline hexmask.long.byte 0x14 0.--7. 1. "DM4,A 8 bit counter for DM4" repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) rgroup.long ($2+0xBB0)++0x3 line.long 0x0 "RGX_CR_MTS_GPU_INT_STATUS_$1,This register contains the sideband data for the MTS internal GPU interrupt status" hexmask.long 0x0 0.--31. 1. "STATUS,A 32 bit register for recored GPU events" repeat.end group.long 0xBC0++0xF line.long 0x0 "RGX_CR_MTS_OS_PRIORITY_0,Operating System Priority" hexmask.long.word 0x0 16.--31. 1. "Reserved_16,Reserved_16" newline bitfld.long 0x0 14.--15. "ID7,Scheduling priority for operating system 7" "0,1,2,3" newline bitfld.long 0x0 12.--13. "ID6,Scheduling priority for operating system 6" "0,1,2,3" newline bitfld.long 0x0 10.--11. "ID5,Scheduling priority for operating system 5" "0,1,2,3" newline bitfld.long 0x0 8.--9. "ID4,Scheduling priority for operating system 4" "0,1,2,3" newline bitfld.long 0x0 6.--7. "ID3,Scheduling priority for operating system 3" "0,1,2,3" newline bitfld.long 0x0 4.--5. "ID2,Scheduling priority for operating system 2" "0,1,2,3" newline bitfld.long 0x0 2.--3. "ID1,Scheduling priority for operating system 1" "0,1,2,3" newline bitfld.long 0x0 0.--1. "ID0,Scheduling priority for operating system 0" "0,1,2,3" line.long 0x4 "RGX_CR_MTS_OS_PRIORITY_1,Operating System Priority" hexmask.long 0x4 0.--31. 1. "Reserved_16,Reserved_16" line.long 0x8 "RGX_CR_MTS_SCHEDULE_ENABLE_0,This register is an active-high mask. When the bit is 0. the MTS_SCHEDULE kick from the corresponding Guest OS is silently discarded. This allows the FW to mask out a Guest OS in order to prevent denial-of-service style.." hexmask.long.tbyte 0x8 8.--31. 1. "Reserved_8,Reserved_8" newline hexmask.long.byte 0x8 0.--7. 1. "MASK,MASK" line.long 0xC "RGX_CR_MTS_SCHEDULE_ENABLE_1,This register is an active-high mask. When the bit is 0. the MTS_SCHEDULE kick from the corresponding Guest OS is silently discarded. This allows the FW to mask out a Guest OS in order to prevent denial-of-service style.." hexmask.long 0xC 0.--31. 1. "Reserved_8,Reserved_8" rgroup.long 0xBD8++0x7 line.long 0x0 "RGX_CR_IRQ_OS0_EVENT_STATUS_0,This register indicates the source of a per-OS host interrupt. This register is set by the firmware and cleared by the host." hexmask.long 0x0 1.--31. 1. "Reserved_1,Reserved_1" newline bitfld.long 0x0 0. "SOURCE,SOURCE" "0,1" line.long 0x4 "RGX_CR_IRQ_OS0_EVENT_STATUS_1,This register indicates the source of a per-OS host interrupt. This register is set by the firmware and cleared by the host." hexmask.long 0x4 0.--31. 1. "Reserved_1,Reserved_1" group.long 0xBE0++0xF line.long 0x0 "RGX_CR_HOST_IRQ_0,This register triggers a per-OS host interrupt. The hardware sets the corresponding RGX_CR_IRQ_OS_EVENT_STATUS register." hexmask.long 0x0 3.--31. 1. "Reserved_3,Reserved_3" newline bitfld.long 0x0 0.--2. "OSID,Indicates the Guest OS for the interrupt" "0,1,2,3,4,5,6,7" line.long 0x4 "RGX_CR_HOST_IRQ_1,This register triggers a per-OS host interrupt. The hardware sets the corresponding RGX_CR_IRQ_OS_EVENT_STATUS register." hexmask.long 0x4 0.--31. 1. "Reserved_3,Reserved_3" line.long 0x8 "RGX_CR_IRQ_OS0_EVENT_CLEAR_0,This register clears a per-OS host interrupt." hexmask.long 0x8 1.--31. 1. "Reserved_1,Reserved_1" newline bitfld.long 0x8 0. "SOURCE,SOURCE" "0,1" line.long 0xC "RGX_CR_IRQ_OS0_EVENT_CLEAR_1,This register clears a per-OS host interrupt." hexmask.long 0xC 0.--31. 1. "Reserved_1,Reserved_1" group.long 0xBF8++0x5F line.long 0x0 "RGX_CR_META_BOOT_0,RGX_CR_META_BOOT_0" hexmask.long 0x0 1.--31. 1. "Reserved_1,Reserved_1" newline bitfld.long 0x0 0. "MODE,0 = Don't boot 1 = Boot" "Don't boot,Boot" line.long 0x4 "RGX_CR_META_BOOT_1,RGX_CR_META_BOOT_1" hexmask.long 0x4 0.--31. 1. "Reserved_1,Reserved_1" line.long 0x8 "RGX_CR_TE_AA_0,This register controls the anti-aliasing mode of the Tiling Co-Processor. independent control is provided in both X & Y axis. 2xmsaa is achieved by enabling X2 - does not affect TE 4xmsaa is achieved by enabling Y and X2 - TE does AA on Y.." hexmask.long 0x8 3.--31. 1. "Reserved_3,Reserved_3" newline bitfld.long 0x8 2. "Y,Anti-Aliasing in Y Plane Enabled" "0,1" newline bitfld.long 0x8 1. "X,Anti-Aliasing in X Plane Enabled" "0,1" newline bitfld.long 0x8 0. "X2,2x Anti-Aliasing Enabled affects PPP only" "0,1" line.long 0xC "RGX_CR_TE_AA_1,This register controls the anti-aliasing mode of the Tiling Co-Processor. independent control is provided in both X & Y axis. 2xmsaa is achieved by enabling X2 - does not affect TE 4xmsaa is achieved by enabling Y and X2 - TE does AA on Y.." hexmask.long 0xC 0.--31. 1. "Reserved_3,Reserved_3" line.long 0x10 "RGX_CR_TE_MTILE1_0,MacroTile Boundaries X Plane" hexmask.long.byte 0x10 27.--31. 1. "Reserved_27,Reserved_27" newline hexmask.long.word 0x10 18.--26. 1. "X1,X1 MacroTile boundary left tile X for second column of macrotiles (16MT mode) - 32 pixels across tile" newline hexmask.long.word 0x10 9.--17. 1. "X2,X2 MacroTile boundary left tile X for third(16MT) column of macrotiles - 32 pixels across tile" newline hexmask.long.word 0x10 0.--8. 1. "X3,X3 MacroTile boundary left tile X for fourth column of macrotiles (16MT) - 32 pixels across tile" line.long 0x14 "RGX_CR_TE_MTILE1_1,MacroTile Boundaries X Plane" hexmask.long 0x14 0.--31. 1. "Reserved_27,Reserved_27" line.long 0x18 "RGX_CR_TE_MTILE2_0,MacroTile Boundaries Y Plane." hexmask.long.byte 0x18 27.--31. 1. "Reserved_27,Reserved_27" newline hexmask.long.word 0x18 18.--26. 1. "Y1,X1 MacroTile boundary ltop tile Y for second column of macrotiles (16MT mode) - 32 pixels tile height" newline hexmask.long.word 0x18 9.--17. 1. "Y2,X2 MacroTile boundary top tile Y for third(16MT) column of macrotiles - 32 pixels tile height" newline hexmask.long.word 0x18 0.--8. 1. "Y3,X3 MacroTile boundary top tile Y for fourth column of macrotiles (16MT) - 32 pixels tile height" line.long 0x1C "RGX_CR_TE_MTILE2_1,MacroTile Boundaries Y Plane." hexmask.long 0x1C 0.--31. 1. "Reserved_27,Reserved_27" line.long 0x20 "RGX_CR_TE_SCREEN_0,In order to perform the tiling operation and generate the display list the maximum screen size must be configured in terms of the number of tiles in X & Y axis." hexmask.long.word 0x20 21.--31. 1. "Reserved_21,Reserved_21" newline hexmask.long.word 0x20 12.--20. 1. "YMAX,Maximum Y tile address visible on screen 32 pixel tile height 16Kx16K max screen size" newline bitfld.long 0x20 9.--11. "Reserved_9,Reserved_9" "0,1,2,3,4,5,6,7" newline hexmask.long.word 0x20 0.--8. 1. "XMAX,Maximum X tile address visible on screen 32 pixel tile width 16Kx16K max screen size" line.long 0x24 "RGX_CR_TE_SCREEN_1,In order to perform the tiling operation and generate the display list the maximum screen size must be configured in terms of the number of tiles in X & Y axis." hexmask.long 0x24 0.--31. 1. "Reserved_21,Reserved_21" line.long 0x28 "RGX_CR_TE_MTILE_0,In order to perform the tiling operation and generate the display list the maximum screen size must be configured in terms of the number of tiles in X & Y axis." hexmask.long.word 0x28 19.--31. 1. "Reserved_19,Reserved_19" newline hexmask.long.tbyte 0x28 0.--18. 1. "STRIDE,Number of tiles in a Macrotile. Stride = (XTile * YTiles) tiles 32 pixels across by 32 pixels" line.long 0x2C "RGX_CR_TE_MTILE_1,In order to perform the tiling operation and generate the display list the maximum screen size must be configured in terms of the number of tiles in X & Y axis." hexmask.long 0x2C 0.--31. 1. "Reserved_19,Reserved_19" line.long 0x30 "RGX_CR_TE_PSG_0,This register defines the global control for the Parameter Stream Generator within the Tiling Co-Processor. This module formats the display list generated by the Tiling Co-Processor." hexmask.long.word 0x30 22.--31. 1. "Reserved_22,Reserved_22" newline bitfld.long 0x30 21. "CS_SIZE,Size of control stream chunk. 0x0 512 bit 0x1 1024 bit" "0,1" newline bitfld.long 0x30 20. "ENABLE_PWR_GATE_STATE,Enables TE PSG power gate state init. 0x0 Disable 0x1 Enable" "0,1" newline bitfld.long 0x30 19. "ENABLE_CONTEXT_STATE_RESTORE,Enables sampling of Driver TE_STATE_ISP_STATE_ID and TE_ACTIVE_MTILE registers on context switch/restore when set when reset current local value is preserved." "0,1" newline bitfld.long 0x30 18. "ZONLYRENDER,Don't invalidate Tail Pointer Cache entries on a Terminate command. Only effective when COMPLETEONTERMINATE is 0x0 0x0 Do Invalidate 0x1 Don't Invalidate" "0,1" newline bitfld.long 0x30 17. "COMPLETEONTERMINATE,0x1 Write region headers terminate streams and invalidate tail pointer cache entries on terminate. 0x0 If ZONLYRENDER = 0x0 then force an Interrupt however if ZONLYRENDER = 0x1 then write region headers and terminate streams." "0,1" newline bitfld.long 0x30 15.--16. "Reserved_15,Reserved_15" "0,1,2,3" newline bitfld.long 0x30 14. "CACHE_BYPASS,when set VCE sets its write only cache to bypass mode effectively disabling the cache" "0,1" newline bitfld.long 0x30 13. "FORCENEWSTATE,Always embed state information in control stream. Debug only." "0,1" newline bitfld.long 0x30 11.--12. "Reserved_11,Reserved_11" "0,1,2,3" newline hexmask.long.word 0x30 0.--10. 1. "REGION_STRIDE,Number of 4kB Pages devoted to region headers for each Render Target - max needed = 0x500" line.long 0x34 "RGX_CR_TE_PSG_1,This register defines the global control for the Parameter Stream Generator within the Tiling Co-Processor. This module formats the display list generated by the Tiling Co-Processor." hexmask.long 0x34 0.--31. 1. "Reserved_22,Reserved_22" line.long 0x38 "RGX_CR_TE_PSG_TERMINATE_0,This register can be written by the driver to define what the TA should terminate tile control streams with. Default value is 0x00000002. however this can be replaced with a link pointer to some driver defined control stream." hexmask.long 0x38 0.--31. 1. "DWORD,Double-word to terminate all tile control streams with." line.long 0x3C "RGX_CR_TE_PSG_TERMINATE_1,This register can be written by the driver to define what the TA should terminate tile control streams with. Default value is 0x00000002. however this can be replaced with a link pointer to some driver defined control stream." hexmask.long.tbyte 0x3C 8.--31. 1. "Reserved_40,Reserved_40" newline hexmask.long.byte 0x3C 0.--7. 1. "BYTE,Byte to terminate all tile control streams with." line.long 0x40 "RGX_CR_TE_PSGREGION_ADDR_0,This register defines the base address in memory of the Region Header writes by the TA. Region headers are the first part of the display list and contain an entry per tile with information on global setup and a link address to.." hexmask.long 0x40 6.--31. 1. "BASE,16GB Addressable 512-bit aligned Base Address for Region Header writes" newline hexmask.long.byte 0x40 0.--5. 1. "Reserved_0,Reserved_0" line.long 0x44 "RGX_CR_TE_PSGREGION_ADDR_1,This register defines the base address in memory of the Region Header writes by the TA. Region headers are the first part of the display list and contain an entry per tile with information on global setup and a link address to.." hexmask.long.tbyte 0x44 8.--31. 1. "Reserved_40,Reserved_40" newline hexmask.long.byte 0x44 2.--7. 1. "HEAP,1TB Addressable 16GB aligned Heap Address for Region Header writes" newline bitfld.long 0x44 0.--1. "BASE,16GB Addressable 512-bit aligned Base Address for Region Header writes" "0,1,2,3" line.long 0x48 "RGX_CR_TE_TPC_ADDR_0,This register defines the base address in memory of the Tail Pointer Cache. A tail pointer is the current last address written to for a tiles individual display list. an entry for active tiles is maintained as primitives are.." hexmask.long 0x48 6.--31. 1. "BASE,16GB Addressable 512-bit aligned Base Address for Tail Pointer Cache entries. The tail pointer is the current last address written to for a control stream for a tile." newline hexmask.long.byte 0x48 0.--5. 1. "Reserved_0,Reserved_0" line.long 0x4C "RGX_CR_TE_TPC_ADDR_1,This register defines the base address in memory of the Tail Pointer Cache. A tail pointer is the current last address written to for a tiles individual display list. an entry for active tiles is maintained as primitives are.." hexmask.long.tbyte 0x4C 8.--31. 1. "Reserved_40,Reserved_40" newline hexmask.long.byte 0x4C 2.--7. 1. "HEAP,1TB Addressable 16GB aligned Heap Address for Tail Pointer Cache." newline bitfld.long 0x4C 0.--1. "BASE,16GB Addressable 512-bit aligned Base Address for Tail Pointer Cache entries. The tail pointer is the current last address written to for a control stream for a tile." "0,1,2,3" line.long 0x50 "RGX_CR_TE_TPC_0,This register defines the TPC Memory footprint size per Render Target as a Stride of 4KB pages" hexmask.long.tbyte 0x50 12.--31. 1. "Reserved_12,Reserved_12" newline hexmask.long.word 0x50 0.--11. 1. "STRIDE,Number of 4KB pages per Render Target in each TPC footprint - max = 2048" line.long 0x54 "RGX_CR_TE_TPC_1,This register defines the TPC Memory footprint size per Render Target as a Stride of 4KB pages" hexmask.long 0x54 0.--31. 1. "Reserved_12,Reserved_12" line.long 0x58 "RGX_CR_TE_TPC_CONTEXT_0,The Tail Pointer Cache is used to keep track of the last address written to for a particular tile. this is stored in a mixture of on chip cache and external memory. Under certain circumstances it is neccesary to either reset the.." bitfld.long 0x58 31. "CLEAR_PENDING,Reset contents of Tail Pointer Cache" "0,1" newline bitfld.long 0x58 30. "FLUSH_PENDING,Flush contents of Tail Pointer Cache to Memory" "0,1" newline hexmask.long 0x58 0.--29. 1. "Reserved_0,Reserved_0" line.long 0x5C "RGX_CR_TE_TPC_CONTEXT_1,The Tail Pointer Cache is used to keep track of the last address written to for a particular tile. this is stored in a mixture of on chip cache and external memory. Under certain circumstances it is neccesary to either reset the.." hexmask.long 0x5C 0.--31. 1. "Reserved_32,Reserved_32" rgroup.long 0xC58++0xF line.long 0x0 "RGX_CR_TE_RGNBBOX_X_0,Reset or enabled by the PPP_RESETBBOX and PPP_UPDATEBBOX fields in the PPPControl word of the Input Parameter format. This is the maximum extent in X of the post transformed. clipped data before region clipping." hexmask.long.byte 0x0 26.--31. 1. "Reserved_26,Reserved_26" newline hexmask.long.word 0x0 16.--25. 1. "MAX,XMax value for maintained Region Generator Bounding Box tiles 32 pixels in width" newline hexmask.long.byte 0x0 10.--15. 1. "Reserved_10,Reserved_10" newline hexmask.long.word 0x0 0.--9. 1. "MIN,XMin value for maintained Region Generator Bounding Box tiles 32 pixels in width" line.long 0x4 "RGX_CR_TE_RGNBBOX_X_1,Reset or enabled by the PPP_RESETBBOX and PPP_UPDATEBBOX fields in the PPPControl word of the Input Parameter format. This is the maximum extent in X of the post transformed. clipped data before region clipping." hexmask.long 0x4 0.--31. 1. "Reserved_26,Reserved_26" line.long 0x8 "RGX_CR_TE_RGNBBOX_Y_0,Reset or enabled by the PPP_RESETBBOX and PPP_UPDATEBBOX fields in the PPP Control word of the Input Parameter format. This is the maximum extent in Y of the post transformed. clipped data before region clipping." hexmask.long.byte 0x8 26.--31. 1. "Reserved_26,Reserved_26" newline hexmask.long.word 0x8 16.--25. 1. "MAX,YMax value for maintained Region Generator Bounding Box tiles 16 pixels in height" newline hexmask.long.byte 0x8 10.--15. 1. "Reserved_10,Reserved_10" newline hexmask.long.word 0x8 0.--9. 1. "MIN,YMin value for maintained Region Generator Bounding Box tiles 16 pixels in height" line.long 0xC "RGX_CR_TE_RGNBBOX_Y_1,Reset or enabled by the PPP_RESETBBOX and PPP_UPDATEBBOX fields in the PPP Control word of the Input Parameter format. This is the maximum extent in Y of the post transformed. clipped data before region clipping." hexmask.long 0xC 0.--31. 1. "Reserved_26,Reserved_26" group.long 0xC68++0x7 line.long 0x0 "RGX_CR_TE_RGNHDR_INIT_0,A write of '1' to this register starts the TE Region Header Initialisation Sequence The TE HW will clear the PENDING bit once the operation is complete" hexmask.long 0x0 1.--31. 1. "Reserved_1,Reserved_1" newline bitfld.long 0x0 0. "PENDING,Start TE Region Header Initialisation" "0,1" line.long 0x4 "RGX_CR_TE_RGNHDR_INIT_1,A write of '1' to this register starts the TE Region Header Initialisation Sequence The TE HW will clear the PENDING bit once the operation is complete" hexmask.long 0x4 0.--31. 1. "Reserved_1,Reserved_1" group.long 0xC78++0x17 line.long 0x0 "RGX_CR_PPP_GRIDOFFSET_0,Sample position grid offset for use when MSAA/ODAA is DISABLED DX (0.0.0.0) OpenGL (0.5.0.5) Acts as the 9th multisample position when MSAA is ENABLED." hexmask.long.tbyte 0x0 8.--31. 1. "Reserved_8,Reserved_8" newline hexmask.long.byte 0x0 4.--7. 1. "GRID_Y,Unsigned sub-pixel offset" newline hexmask.long.byte 0x0 0.--3. 1. "GRID_X,Unsigned sub-pixel offset" line.long 0x4 "RGX_CR_PPP_GRIDOFFSET_1,Sample position grid offset for use when MSAA/ODAA is DISABLED DX (0.0.0.0) OpenGL (0.5.0.5) Acts as the 9th multisample position when MSAA is ENABLED." hexmask.long 0x4 0.--31. 1. "Reserved_8,Reserved_8" line.long 0x8 "RGX_CR_PPP_MULTISAMPLECTL_0,Sample position grid offset for use in 2x. 4x. 8xMSAA and ODAA modes." hexmask.long.byte 0x8 28.--31. 1. "MSAA_Y3,Unsigned sub-pixel offset for the 4th multisample Y position" newline hexmask.long.byte 0x8 24.--27. 1. "MSAA_X3,Unsigned sub-pixel offset for the 4th multisample X position" newline hexmask.long.byte 0x8 20.--23. 1. "MSAA_Y2,Unsigned sub-pixel offset for the 3rd multisample Y position" newline hexmask.long.byte 0x8 16.--19. 1. "MSAA_X2,Unsigned sub-pixel offset for the 3rd multisample X position" newline hexmask.long.byte 0x8 12.--15. 1. "MSAA_Y1,Unsigned sub-pixel offset for the 2nd multisample Y position" newline hexmask.long.byte 0x8 8.--11. 1. "MSAA_X1,Unsigned sub-pixel offset for the 2nd multisample X position" newline hexmask.long.byte 0x8 4.--7. 1. "MSAA_Y0,Unsigned sub-pixel offset for the 1st multisample Y position" newline hexmask.long.byte 0x8 0.--3. 1. "MSAA_X0,Unsigned sub-pixel offset for the 1st multisample X position" line.long 0xC "RGX_CR_PPP_MULTISAMPLECTL_1,Sample position grid offset for use in 2x. 4x. 8xMSAA and ODAA modes." hexmask.long 0xC 0.--31. 1. "Reserved_32,Reserved_32" line.long 0x10 "RGX_CR_PPP_CTRL_0,This register controls the global setup of the PPP." hexmask.long.tbyte 0x10 13.--31. 1. "Reserved_13,Reserved_13" newline bitfld.long 0x10 12. "VPT_SCISSOR,When 0 the PPP will insert state updates on change of VPT ID When 1 this feature is disabled" "0,1" newline bitfld.long 0x10 11. "FLUSH_MODE,when 0 PPP will supress end of draw call flushed from reaching the Clipper and TA pipeline This will break batch number funstionality but will give better primitive block utiliastion. when 1 PPP will not supress any flushes" "0,1" newline bitfld.long 0x10 10. "BFCULL_RESTRICT_CLIP,When set clipped primitives are only back-face culled after the clipper. 0 Enable early back face cull for clipped primitives 1 Disable early cull" "0,1" newline bitfld.long 0x10 9. "FIXED_POINT_FORMAT,When set the PPP will use a fixed point format of 16. 8 rather than 16.4. 0 16.4 fixed point format 1 16.8 fixed point format" "0,1" newline bitfld.long 0x10 8. "DEFAULT_POINT_SIZE,When set the PPP will use the default point size rather than reading it from the vertex. 0 Point size read from vertex 1 Default point size of 3F800000 used" "0,1" newline bitfld.long 0x10 7. "BFCULL1_DISABLE,Disable for fully clipped culling 0 First back face cull block enabled 1 First back face cull block disabled" "0,1" newline bitfld.long 0x10 6. "BFCULL2_DISABLE,Disable for fully clipped culling 0 Second back face cull block enabled 1 Second back face cull block disabled" "0,1" newline bitfld.long 0x10 5. "FCCULL_DISABLE,Disable for fully clipped culling 0 Fully clipped culling enabled 1 Fully clipped culling disabled" "0,1" newline bitfld.long 0x10 4. "OSCULL_DISABLE,Disable for off screen culling 0 Off screen culling enabled 1 Off screen culling disabled" "0,1" newline bitfld.long 0x10 3. "PSOCULL_DISABLE,Disable for perfect small object culling 0 Perfect small object culling enabled 1 Perfect small object culling disabled" "0,1" newline bitfld.long 0x10 2. "SOCULL_DISABLE,Disable for small object culling 0 Small object culling enabled 1 Small object culling disabled" "0,1" newline bitfld.long 0x10 1. "WCLAMPEN,Enable W clamping 0 W clamping disabled 1 W clamping enabled" "0,1" newline bitfld.long 0x10 0. "OPENGL,Select OpenGL or D3D mode 0 D3D 1 OpenGL" "0,1" line.long 0x14 "RGX_CR_PPP_CTRL_1,This register controls the global setup of the PPP." hexmask.long 0x14 0.--31. 1. "Reserved_13,Reserved_13" repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) group.long ($2+0xC90)++0x3 line.long 0x0 "RGX_CR_PPP_WCLAMP_$1,RGX_CR_PPP_WCLAMP_0" hexmask.long 0x0 0.--31. 1. "CLAMP_VALUE,Clamp value for W clamping. See the Input parameter format viewport transform for details. Clamp is applied post viewport transform if the w value is less than the WCOMPARE value. Note that this value cannot be negative." repeat.end group.long 0xC98++0xF line.long 0x0 "RGX_CR_PPP_SCREEN_0,In order to perform the tiling operation and generate the display list the maximum screen size must be configured in terms of the number of pixels in X & Y axis since this may not be the same as the number of tiles defined in the.." bitfld.long 0x0 31. "Reserved_31,Reserved_31" "0,1" newline hexmask.long.word 0x0 16.--30. 1. "PIXYMAX,Screen height in pixels. (16K x 16K max screen size)" newline bitfld.long 0x0 15. "Reserved_15,Reserved_15" "0,1" newline hexmask.long.word 0x0 0.--14. 1. "PIXXMAX,Screen width in pixels.(16K x 16K max screen size)" line.long 0x4 "RGX_CR_PPP_SCREEN_1,In order to perform the tiling operation and generate the display list the maximum screen size must be configured in terms of the number of pixels in X & Y axis since this may not be the same as the number of tiles defined in the.." hexmask.long 0x4 0.--31. 1. "Reserved_31,Reserved_31" line.long 0x8 "RGX_CR_VCE_CTRL_0,This register controls the global setup of the VCE." hexmask.long 0x8 4.--31. 1. "Reserved_4,Reserved_4" newline bitfld.long 0x8 3. "CACHE_BYPASS,when set VCE sets its write only cache to bypass mode effectively disabling the cache" "0,1" newline bitfld.long 0x8 2. "Reserved_2,Reserved_2" "0,1" newline bitfld.long 0x8 1. "TWO_ORIGIN_DISABLE,When set raw mode is selected in place of 2-origin delta stream compression mode" "0,1" newline bitfld.long 0x8 0. "COMPRESS_DISABLE,When set vertex compression is disabled. I.e. raw mode is forced for all vertices" "0,1" line.long 0xC "RGX_CR_VCE_CTRL_1,This register controls the global setup of the VCE." hexmask.long 0xC 0.--31. 1. "Reserved_4,Reserved_4" wgroup.long 0xCA8++0x7 line.long 0x0 "RGX_CR_TE_CLEAR_LISTS_AFTER_ABORT_0,A write of '1' to this register tells the TE we are resuming after an Abort and Partial Render Sequence" hexmask.long 0x0 1.--31. 1. "Reserved_1,Reserved_1" newline bitfld.long 0x0 0. "PULSE,TE Clears all references after Abort and Partial Render Sequence" "0,1" line.long 0x4 "RGX_CR_TE_CLEAR_LISTS_AFTER_ABORT_1,A write of '1' to this register tells the TE we are resuming after an Abort and Partial Render Sequence" hexmask.long 0x4 0.--31. 1. "Reserved_1,Reserved_1" group.long 0xCB0++0x17 line.long 0x0 "RGX_CR_TA_RTC_ADDR_0,This register defines the base address in memory of the TA Render Target Caches. for the VCE. TEAC and PSG" hexmask.long 0x0 6.--31. 1. "BASE,16GB Addressabreadonly le 512-bit aligned Base Address for TA Render Target Caches." newline hexmask.long.byte 0x0 0.--5. 1. "Reserved_0,Reserved_0" line.long 0x4 "RGX_CR_TA_RTC_ADDR_1,This register defines the base address in memory of the TA Render Target Caches. for the VCE. TEAC and PSG" hexmask.long.tbyte 0x4 8.--31. 1. "Reserved_40,Reserved_40" newline hexmask.long.byte 0x4 2.--7. 1. "HEAP,1TB Addressable 16GB aligned Heap Address for TA Render Target Caches" newline bitfld.long 0x4 0.--1. "BASE,16GB Addressabreadonly le 512-bit aligned Base Address for TA Render Target Caches." "0,1,2,3" line.long 0x8 "RGX_CR_TA_RTC_CTRL_0,A write of '1' to Bit 0 of this register Clears the RTC. A write of '1' to Bit 1 of this register Stores the RTC to memory (address specified in TA_RTC_ADDR register)" hexmask.long 0x8 2.--31. 1. "Reserved_2,Reserved_2" newline bitfld.long 0x8 1. "STORE_PENDING,Store RTC" "0,1" newline bitfld.long 0x8 0. "CLEAR_PENDING,Clear RTC" "0,1" line.long 0xC "RGX_CR_TA_RTC_CTRL_1,A write of '1' to Bit 0 of this register Clears the RTC. A write of '1' to Bit 1 of this register Stores the RTC to memory (address specified in TA_RTC_ADDR register)" hexmask.long 0xC 0.--31. 1. "Reserved_2,Reserved_2" line.long 0x10 "RGX_CR_TA_CONTEXT_STATE_BASE_0,The base address in external memory of the TA's context state buffer. to which the PPP will store the state on a context store and from which the VDM will reload on a context resume" hexmask.long 0x10 4.--31. 1. "ADDR,1TB range 128-bit aligned base address" newline hexmask.long.byte 0x10 0.--3. 1. "Reserved_0,Reserved_0" line.long 0x14 "RGX_CR_TA_CONTEXT_STATE_BASE_1,The base address in external memory of the TA's context state buffer. to which the PPP will store the state on a context store and from which the VDM will reload on a context resume" hexmask.long.tbyte 0x14 8.--31. 1. "Reserved_40,Reserved_40" newline hexmask.long.byte 0x14 0.--7. 1. "ADDR,1TB range 128-bit aligned base address" rgroup.long 0xCC8++0x7 line.long 0x0 "RGX_CR_PPP_DIAG_CULL_0,Diagnois register keeps a count of the number of primtives entering the PPP culling module" hexmask.long.byte 0x0 26.--31. 1. "OP_COUNT,count of primitives exiting the cull block" newline hexmask.long 0x0 0.--25. 1. "IP_COUNT,count of primitives entering the cull block" line.long 0x4 "RGX_CR_PPP_DIAG_CULL_1,Diagnois register keeps a count of the number of primtives entering the PPP culling module" hexmask.long.word 0x4 20.--31. 1. "Reserved_52,Reserved_52" newline hexmask.long.tbyte 0x4 0.--19. 1. "OP_COUNT,count of primitives exiting the cull block" repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) rgroup.long ($2+0xCD0)++0x3 line.long 0x0 "RGX_CR_PPP_$1,Checksum generated from the output of the PPP" hexmask.long 0x0 0.--31. 1. "CHECKSUM,checksum generated from the output of the PPP" repeat.end group.long 0xCD8++0x1F line.long 0x0 "RGX_CR_UVS_CLEAR_0,A write of '1' to this register starts the UVS Clear Operation This register must be written during the core initialisation sequence." hexmask.long 0x0 1.--31. 1. "Reserved_1,Reserved_1" newline bitfld.long 0x0 0. "PENDING,Start UVS Clear Operation a write to this register results in a one cycle pulse" "0,1" line.long 0x4 "RGX_CR_UVS_CLEAR_1,A write of '1' to this register starts the UVS Clear Operation This register must be written during the core initialisation sequence." hexmask.long 0x4 0.--31. 1. "Reserved_1,Reserved_1" line.long 0x8 "RGX_CR_TA_RTC_PRELOAD_0,When set. the RTC will be Preloaded with Zeros (or a nonRTA render target of 1) on a Clear Operation (used when Render Targets are not in use to remove the need for memory allocation)" hexmask.long 0x8 2.--31. 1. "Reserved_2,Reserved_2" newline bitfld.long 0x8 1. "ONE,Preload RTC with Render Target 0 set on a Clear. Used when resuming a TA phase after coarse grain context switch" "0,1" newline bitfld.long 0x8 0. "ZEROS,Preload RTC with Zeros on a Clear" "0,1" line.long 0xC "RGX_CR_TA_RTC_PRELOAD_1,When set. the RTC will be Preloaded with Zeros (or a nonRTA render target of 1) on a Clear Operation (used when Render Targets are not in use to remove the need for memory allocation)" hexmask.long 0xC 0.--31. 1. "Reserved_2,Reserved_2" line.long 0x10 "RGX_CR_TE_STATE_0,This register should be Sampled by the Driver on Context Switch and Restored before the Resume of the TA Context" hexmask.long 0x10 6.--31. 1. "Reserved_6,Reserved_6" newline hexmask.long.byte 0x10 1.--5. 1. "ISP_STATE_ID,ISP State ID" newline bitfld.long 0x10 0. "ABORTED,TA had been aborted in the past" "0,1" line.long 0x14 "RGX_CR_TE_STATE_1,This register should be Sampled by the Driver on Context Switch and Restored before the Resume of the TA Context" hexmask.long 0x14 0.--31. 1. "Reserved_6,Reserved_6" line.long 0x18 "RGX_CR_VCE_HALT_0,The MicroKernel must halt VCE processing (consumption of it's pages allocated by PM) before we can do a Partial Render in the Rogue Architecture. When it writes this register. the VCE will detect this on a notify pulse and assert the.." hexmask.long 0x18 1.--31. 1. "Reserved_1,Reserved_1" newline bitfld.long 0x18 0. "PENDING,VCE is Halting after Current Block" "0,1" line.long 0x1C "RGX_CR_VCE_HALT_1,The MicroKernel must halt VCE processing (consumption of it's pages allocated by PM) before we can do a Partial Render in the Rogue Architecture. When it writes this register. the VCE will detect this on a notify pulse and assert the.." hexmask.long 0x1C 0.--31. 1. "Reserved_1,Reserved_1" wgroup.long 0xCF8++0x7 line.long 0x0 "RGX_CR_TE_RESUME_AFTER_ABORT_0,A write of '1' to this register tells the TE we are resuming after an Abort but that no Partial Render took place" hexmask.long 0x0 1.--31. 1. "Reserved_1,Reserved_1" newline bitfld.long 0x0 0. "PULSE,TE is restarted and reattempts failing allocation after Out Of Memory event only" "0,1" line.long 0x4 "RGX_CR_TE_RESUME_AFTER_ABORT_1,A write of '1' to this register tells the TE we are resuming after an Abort but that no Partial Render took place" hexmask.long 0x4 0.--31. 1. "Reserved_1,Reserved_1" rgroup.long 0xD00++0x7 line.long 0x0 "RGX_CR_TA_IDLE_0,RGX_CR_TA_IDLE_0" hexmask.long 0x0 6.--31. 1. "Reserved_6,Reserved_6" newline bitfld.long 0x0 5. "TE,TE Module IDLE" "0,1" newline bitfld.long 0x0 4. "VCE,VCE Module IDLE" "0,1" newline bitfld.long 0x0 3. "VBG,VBG Module IDLE" "0,1" newline bitfld.long 0x0 2. "CLIP,CLIP Module IDLE" "0,1" newline bitfld.long 0x0 1. "PPP,PPP Module IDLE" "0,1" newline bitfld.long 0x0 0. "UVS,UVS Module IDLE" "0,1" line.long 0x4 "RGX_CR_TA_IDLE_1,RGX_CR_TA_IDLE_1" hexmask.long 0x4 0.--31. 1. "Reserved_6,Reserved_6" repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) rgroup.long ($2+0xD08)++0x3 line.long 0x0 "RGX_CR_STAT_NEW_PRIM_$1,RGX_CR_STAT_NEW_PRIM_0" hexmask.long 0x0 0.--31. 1. "PPP,Number of primitives into PPP" repeat.end repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) rgroup.long ($2+0xD10)++0x3 line.long 0x0 "RGX_CR_STAT_NEW_$1,RGX_CR_STAT_NEW_0" hexmask.long 0x0 0.--31. 1. "VERTEX,Number of vertices" repeat.end group.long 0xD18++0x27 line.long 0x0 "RGX_CR_FBC_MEM_POINTER_0,Framebuffer last memory address written in indirect mode" hexmask.long 0x0 0.--31. 1. "BASE_ADDRESS_REQ,Set to base address of compressed surface to find the last written address for that surface by reading the register when FBC_MEM_POINTER_READ_PENDING =0. BASE_ADDRESS=[33..0] DM=[36..34]" line.long 0x4 "RGX_CR_FBC_MEM_POINTER_1,Framebuffer last memory address written in indirect mode" hexmask.long 0x4 6.--31. 1. "Reserved_38,Reserved_38" newline bitfld.long 0x4 5. "READ_PENDING,Write 1 to perform a lookup for the last memory address written for that surface specified when this register is read as 0 then contents of FBC_MEM_POINTER_BASE_ADDRESS_REQ register contains the last memory address written for the.." "0,1" newline hexmask.long.byte 0x4 0.--4. 1. "BASE_ADDRESS_REQ,Set to base address of compressed surface to find the last written address for that surface by reading the register when FBC_MEM_POINTER_READ_PENDING =0. BASE_ADDRESS=[33..0] DM=[36..34]" line.long 0x8 "RGX_CR_TE_PSG_RTC_0,This register should be Sampled by the Driver on VDM Context Switch Terminate TA FINISHED event and Restored before the Resume of the TA Context" hexmask.long.tbyte 0x8 12.--31. 1. "Reserved_12,Reserved_12" newline hexmask.long.word 0x8 0.--11. 1. "ACTIVE_RTS,RTAs active at the point of the VDM Context SWitch" line.long 0xC "RGX_CR_TE_PSG_RTC_1,This register should be Sampled by the Driver on VDM Context Switch Terminate TA FINISHED event and Restored before the Resume of the TA Context" hexmask.long 0xC 0.--31. 1. "Reserved_12,Reserved_12" line.long 0x10 "RGX_CR_VCE_CACHE_FLUSH_0,The MicroKernel can use this to flush the VCE write only cache at the end of TA phase render. When it writes this register. the VCE will detect this on a notify pulse and assert the return signal until it has completed processing.." hexmask.long 0x10 1.--31. 1. "Reserved_1,Reserved_1" newline bitfld.long 0x10 0. "PENDING,VCE is Flushing its write only cache to memory" "0,1" line.long 0x14 "RGX_CR_VCE_CACHE_FLUSH_1,The MicroKernel can use this to flush the VCE write only cache at the end of TA phase render. When it writes this register. the VCE will detect this on a notify pulse and assert the return signal until it has completed processing.." hexmask.long 0x14 0.--31. 1. "Reserved_1,Reserved_1" line.long 0x18 "RGX_CR_TE_CACHE_FLUSH_0,The MicroKernel can use this to flush the TE write only cache at the end of TA phase render. When it writes this register. the TE will detect this on a notify pulse and assert the return signal until it has completed processing.." hexmask.long 0x18 1.--31. 1. "Reserved_1,Reserved_1" newline bitfld.long 0x18 0. "PENDING,TE is Flushing its write only cache to memory" "0,1" line.long 0x1C "RGX_CR_TE_CACHE_FLUSH_1,The MicroKernel can use this to flush the TE write only cache at the end of TA phase render. When it writes this register. the TE will detect this on a notify pulse and assert the return signal until it has completed processing.." hexmask.long 0x1C 0.--31. 1. "Reserved_1,Reserved_1" line.long 0x20 "RGX_CR_PM_CACHE_FLUSH_0,The MicroKernel can use this to flush the PM write only cache at the end of TA phase render. When it writes this register. the PM will detect this on a notify pulse and assert the return signal until it has completed processing.." hexmask.long 0x20 1.--31. 1. "Reserved_1,Reserved_1" newline bitfld.long 0x20 0. "PENDING,PM is Flushing its write only cache to memory" "0,1" line.long 0x24 "RGX_CR_PM_CACHE_FLUSH_1,The MicroKernel can use this to flush the PM write only cache at the end of TA phase render. When it writes this register. the PM will detect this on a notify pulse and assert the return signal until it has completed processing.." hexmask.long 0x24 0.--31. 1. "Reserved_1,Reserved_1" wgroup.long 0xF00++0x7 line.long 0x0 "RGX_CR_ISP_START_RENDER_0,Writing '1' to this register initiates a 3D render" hexmask.long 0x0 1.--31. 1. "Reserved_1,Reserved_1" newline bitfld.long 0x0 0. "PULSE,PULSE" "0,1" line.long 0x4 "RGX_CR_ISP_START_RENDER_1,Writing '1' to this register initiates a 3D render" hexmask.long 0x4 0.--31. 1. "Reserved_1,Reserved_1" group.long 0xF08++0x77 line.long 0x0 "RGX_CR_ISP_RENDER_0,Controls the render" hexmask.long 0x0 5.--31. 1. "Reserved_5,Reserved_5" newline bitfld.long 0x0 4. "RESUME,Render resume" "0,1" newline bitfld.long 0x0 2.--3. "DIR,Render direction" "0,1,2,3" newline bitfld.long 0x0 0.--1. "MODE,Render type" "0,1,2,3" line.long 0x4 "RGX_CR_ISP_RENDER_1,Controls the render" hexmask.long 0x4 0.--31. 1. "Reserved_5,Reserved_5" line.long 0x8 "RGX_CR_ISP_RENDER_ORIGIN_0,This register defines the top-left tile coordinate for the render." hexmask.long.byte 0x8 26.--31. 1. "Reserved_26,Reserved_26" newline hexmask.long.word 0x8 16.--25. 1. "X,X coordinate in tiles" newline hexmask.long.byte 0x8 10.--15. 1. "Reserved_10,Reserved_10" newline hexmask.long.word 0x8 0.--9. 1. "Y,Y coordinate in tiles" line.long 0xC "RGX_CR_ISP_RENDER_ORIGIN_1,This register defines the top-left tile coordinate for the render." hexmask.long 0xC 0.--31. 1. "Reserved_26,Reserved_26" line.long 0x10 "RGX_CR_ISP_MTILE_SIZE_0,RGX_CR_ISP_MTILE_SIZE_0" hexmask.long.byte 0x10 26.--31. 1. "Reserved_26,Reserved_26" newline hexmask.long.word 0x10 16.--25. 1. "X,Macrotile width in tiles. A value of zero corresponds to the maximum size" newline hexmask.long.byte 0x10 10.--15. 1. "Reserved_10,Reserved_10" newline hexmask.long.word 0x10 0.--9. 1. "Y,Macrotile height in tiles. A value of zero corresponds to the maximum size" line.long 0x14 "RGX_CR_ISP_MTILE_SIZE_1,RGX_CR_ISP_MTILE_SIZE_1" hexmask.long 0x14 0.--31. 1. "Reserved_26,Reserved_26" line.long 0x18 "RGX_CR_ISP_MTILE_BASE_0,RGX_CR_ISP_MTILE_BASE_0" hexmask.long 0x18 2.--31. 1. "ADDR,1TB range 32-bit aligned base address" newline bitfld.long 0x18 0.--1. "Reserved_0,Reserved_0" "0,1,2,3" line.long 0x1C "RGX_CR_ISP_MTILE_BASE_1,RGX_CR_ISP_MTILE_BASE_1" hexmask.long.tbyte 0x1C 8.--31. 1. "Reserved_40,Reserved_40" newline hexmask.long.byte 0x1C 0.--7. 1. "ADDR,1TB range 32-bit aligned base address" line.long 0x20 "RGX_CR_ISP_RGN_0,This register defines the sizes of the allocations of the simple internal parameter data." bitfld.long 0x20 29.--31. "Reserved_29,Reserved_29" "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x20 24.--28. 1. "CS_SIZE,Number of primitive headers in the control stream for a fast 2D render. If the number of primitive headers exceeds the maximum field size or the size of the control stream is unknown a value of all ones should be written" newline hexmask.long.tbyte 0x20 0.--23. 1. "SIZE,Number of Region Headers to fetch" line.long 0x24 "RGX_CR_ISP_RGN_1,This register defines the sizes of the allocations of the simple internal parameter data." hexmask.long 0x24 0.--31. 1. "Reserved_29,Reserved_29" line.long 0x28 "RGX_CR_ISP_AA_0,Controls whether anti-aliasing is enabled or disabled" hexmask.long 0x28 2.--31. 1. "Reserved_2,Reserved_2" newline bitfld.long 0x28 0.--1. "MODE,MODE" "0,1,2,3" line.long 0x2C "RGX_CR_ISP_AA_1,Controls whether anti-aliasing is enabled or disabled" hexmask.long 0x2C 0.--31. 1. "Reserved_2,Reserved_2" line.long 0x30 "RGX_CR_ISP_CTL_0,ISP control register. This register contains the PIPE_NUM field which controls the number of tiles in flight within the IPP and IPF. The values to which this register should be set are dependent on not only the number of tiles in flight.." bitfld.long 0x30 31. "Reserved_31,Reserved_31" "0,1" newline bitfld.long 0x30 30. "LINE_STYLE,Used to enable rendering widelines as rectangles. '0': render as parallelograms '1': render as retangles" "0,1" newline bitfld.long 0x30 29. "LINE_STYLE_PIX,Used to enable rendering single pixel widelines as rectangles. '0': render as parallelograms '1': render as retangles" "0,1" newline bitfld.long 0x30 28. "PAIR_TILES_VERT,If set causes IPF to pair tiles vertically within its pipeline." "0,1" newline bitfld.long 0x30 27. "PAIR_TILES,If set causes IPF to pair tiles within its pipeline." "0,1" newline hexmask.long.byte 0x30 21.--26. 1. "Reserved_21,Reserved_21" newline bitfld.long 0x30 20. "DBIAS_IS_INT,When set depth bias value is a signed integer" "0,1" newline bitfld.long 0x30 19. "OVERLAP_CHECK_MODE,0 - different samples for the same pixel will be sent to different pass groups for translucent objects (pixel to pixel overlap test) 1 - different samples for the same pixel will be sent as the same pass group (sample to sample overlap.." "different samples for the same pixel will be..,different samples for the same pixel will be.." newline bitfld.long 0x30 18. "PT_UPFRONT_DEPTH_DISABLE,When set disable UPFRONT depth test in the Depthsorter" "0,1" newline bitfld.long 0x30 17. "PROCESS_EMPTY_TILES,When set empty tiles are always processed rather than being suppressed" "0,1" newline bitfld.long 0x30 16. "SAMPLE_POS,Specifies the sampling rule to be used when calculating the endpoint adjustment for thin lines" "0,1" newline hexmask.long.byte 0x30 12.--15. 1. "PIPE_ENABLE,Tiles-in-flight" newline bitfld.long 0x30 10.--11. "Reserved_10,Reserved_10" "0,1,2,3" newline hexmask.long.byte 0x30 4.--9. 1. "VALID_ID,Triangle validation value" newline hexmask.long.byte 0x30 0.--3. 1. "UPASS_START,User pass start value" line.long 0x34 "RGX_CR_ISP_CTL_1,ISP control register. This register contains the PIPE_NUM field which controls the number of tiles in flight within the IPP and IPF. The values to which this register should be set are dependent on not only the number of tiles in flight.." hexmask.long 0x34 0.--31. 1. "Reserved_31,Reserved_31" line.long 0x38 "RGX_CR_ISP_SPLIT_RENDER_0,RGX_CR_ISP_SPLIT_RENDER_0" bitfld.long 0x38 30.--31. "Reserved_30,Reserved_30" "0,1,2,3" newline hexmask.long.word 0x38 16.--29. 1. "MAX,Render up to and including this value" newline bitfld.long 0x38 14.--15. "Reserved_14,Reserved_14" "0,1,2,3" newline hexmask.long.word 0x38 0.--13. 1. "MIN,Render up from and including this value" line.long 0x3C "RGX_CR_ISP_SPLIT_RENDER_1,RGX_CR_ISP_SPLIT_RENDER_1" hexmask.long 0x3C 1.--31. 1. "Reserved_33,Reserved_33" newline bitfld.long 0x3C 0. "ENABLE,ENABLE" "0,1" line.long 0x40 "RGX_CR_ISP_ZLSCTL_0,ISP Z Load/Store & format global control register" hexmask.long.byte 0x40 27.--31. 1. "ZLSEXTENT_Y_Z,For Depth buffer Display width of Y in tiles minus one: 0x000 1 tile 0x001 2 tiles .. 0x2FF 1024 tiles zlsextent_y = total_samples_y / 32 samples in non-msaa 4xmsaa mode = total_samples_y / 64 samples in 2xmsaa 8xmsaa mode. In.." newline bitfld.long 0x40 25.--26. "ZSTOREFORMAT,ZSTOREFORMAT" "0,1,2,3" newline bitfld.long 0x40 23.--24. "ZLOADFORMAT,ZLOADFORMAT" "0,1,2,3" newline bitfld.long 0x40 22. "FB_STOREEN,when set frame buffer compression store is enabled" "0,1" newline bitfld.long 0x40 21. "FB_LOADEN,when set frame buffer decompression load is enabled" "0,1" newline bitfld.long 0x40 20. "MSTOREEN,When set and ZSTOREFORMAT = 0x0 mask plane is stored within msb of IEEE format when set and ZSTOREFORMAT = 0x3 mask plane is stored at bit position 31 of IEEE format when set for other format if mask_store_base_enable = '1' background.." "0,1" newline bitfld.long 0x40 19. "ZSTOREEN,When set to 1 if the ZSTORE bit in the region header is also set then the depth buffer is stored to memory after each tile is processed" "0,1" newline bitfld.long 0x40 18. "SSTOREEN,When set to 1 if the ZSTORE bit in the region header is also set then the stencil buffer is stored to memory after each tile is processed" "0,1" newline bitfld.long 0x40 17. "STORETWIDDLED,When set to 1 depth and stencil data is written out in 'Twiddled' order." "0,1" newline bitfld.long 0x40 16. "MLOADEN,When set and ZLOADFORMAT = 0x0 mask plane is loaded from msb of IEEE format when set and ZLOADFORMAT = 0x3 mask plane is loaded from the bit position 31 of IEEE format when set for other format if mask_load_base_enable = '1' mask plane is.." "0,1" newline bitfld.long 0x40 15. "ZLOADEN,When set to 1 if the ZLOAD bit in the region header is also set then the depth buffer is read from memory prior to tile processing" "0,1" newline bitfld.long 0x40 14. "SLOADEN,When set to 1 if the ZLOAD bit in the region header is also set then the stencil buffer is read from memory prior to tile processing" "0,1" newline bitfld.long 0x40 13. "LOADTWIDDLED,When set to 1 depth stencil data is loaded in 'Twiddled' order" "0,1" newline hexmask.long.word 0x40 3.--12. 1. "ZLSEXTENT_X_Z,For depth buffer Display width of X in tiles minus one: 0x000 1 tile 0x001 2 tiles .. 0x2FF 1024 tiles. For different msaa mode 1xmsaa = 1 x (32 32) pixels = 32x1 x 32x1 = 1024 samples = 32 x 32 samples 2xmsaa = 2 x (32 32) pixels =.." newline bitfld.long 0x40 2. "FORCEZSTORE,If set to 1 the depth/stencil buffer is always stored at the end of each tile irrespective of the region header ZSTORE bit." "0,1" newline bitfld.long 0x40 1. "FORCEZLOAD,If set to 1 the depth/stencil buffer is always loaded at the start of each tile irrespective of the region header ZLOAD bit." "0,1" newline bitfld.long 0x40 0. "ZONLYRENDER,When set only the Z buffer is rendered. Opaque and translucent objects are stencil and depth tested as usual but no pixel spans are emitted to the PDS Pixel presenter. Pixels within punch through and depth feedback objects are emitted on.." "0,1" line.long 0x44 "RGX_CR_ISP_ZLSCTL_1,ISP Z Load/Store & format global control register" hexmask.long.byte 0x44 26.--31. 1. "Reserved_58,Reserved_58" newline hexmask.long.word 0x44 16.--25. 1. "ZLSEXTENT_Y_S,For stencil buffer the value calculation is the same as ZLSEXTENT_Y_Z" newline hexmask.long.word 0x44 6.--15. 1. "ZLSEXTENT_X_S,For stencil buffer the value calculation is the same as ZLSEXTENT_X_Z" newline bitfld.long 0x44 5. "STENCIL_EXTENT_ENABLE,When this bit is '1' stencil buffer will use zlsextent_x/y_s value to calculate zload/store address otherwise zlsextent_x/y_z value will be used. The default value is '0' which disables this new function." "0,1" newline hexmask.long.byte 0x44 0.--4. 1. "ZLSEXTENT_Y_Z,For Depth buffer Display width of Y in tiles minus one: 0x000 1 tile 0x001 2 tiles .. 0x2FF 1024 tiles zlsextent_y = total_samples_y / 32 samples in non-msaa 4xmsaa mode = total_samples_y / 64 samples in 2xmsaa 8xmsaa mode. In.." line.long 0x48 "RGX_CR_ISP_ZLOAD_BASE_0,Base address in memory of the Z Buffer base address to load into the ISP for non-compressed ZLS formats." hexmask.long 0x48 4.--31. 1. "ADDR,1TB Addressable 16byte aligned Base Address of the Z Buffer Load base address" newline hexmask.long.byte 0x48 0.--3. 1. "Reserved_0,Reserved_0" line.long 0x4C "RGX_CR_ISP_ZLOAD_BASE_1,Base address in memory of the Z Buffer base address to load into the ISP for non-compressed ZLS formats." hexmask.long.tbyte 0x4C 8.--31. 1. "Reserved_40,Reserved_40" newline hexmask.long.byte 0x4C 0.--7. 1. "ADDR,1TB Addressable 16byte aligned Base Address of the Z Buffer Load base address" line.long 0x50 "RGX_CR_ISP_ZSTORE_BASE_0,Base address in memory of the Z Buffer base address to store into the ISP for non-compressed ZLS formats." hexmask.long 0x50 4.--31. 1. "ADDR,1TB Addressable 16byte aligned Base Address of the Z Buffer Store base address" newline hexmask.long.byte 0x50 0.--3. 1. "Reserved_0,Reserved_0" line.long 0x54 "RGX_CR_ISP_ZSTORE_BASE_1,Base address in memory of the Z Buffer base address to store into the ISP for non-compressed ZLS formats." hexmask.long.tbyte 0x54 8.--31. 1. "Reserved_40,Reserved_40" newline hexmask.long.byte 0x54 0.--7. 1. "ADDR,1TB Addressable 16byte aligned Base Address of the Z Buffer Store base address" line.long 0x58 "RGX_CR_ISP_STENCIL_LOAD_BASE_0,Base address in memory of the Stencil Buffer base address to load into the ISP for non-compressed ZLS formats. This alternate stencil buffer base address is selectable based on the enable bit." hexmask.long 0x58 4.--31. 1. "ADDR,1TB Addressable 16byte aligned Base Address of the Z Buffer Load base address" newline bitfld.long 0x58 1.--3. "Reserved_1,Reserved_1" "0,1,2,3,4,5,6,7" newline bitfld.long 0x58 0. "ENABLE,When set to 1 enables fetching of stencil from a separate base address" "0,1" line.long 0x5C "RGX_CR_ISP_STENCIL_LOAD_BASE_1,Base address in memory of the Stencil Buffer base address to load into the ISP for non-compressed ZLS formats. This alternate stencil buffer base address is selectable based on the enable bit." hexmask.long.tbyte 0x5C 8.--31. 1. "Reserved_40,Reserved_40" newline hexmask.long.byte 0x5C 0.--7. 1. "ADDR,1TB Addressable 16byte aligned Base Address of the Z Buffer Load base address" line.long 0x60 "RGX_CR_ISP_STENCIL_STORE_BASE_0,Base address in memory of the Stencil Buffer base address to store into the ISP for non-compressed ZLS formats. This alternate stencil buffer base address is selectable based on the enable bit." hexmask.long 0x60 4.--31. 1. "ADDR,1TB Addressable 16byte aligned Base Address of the Z Buffer Load base address" newline bitfld.long 0x60 1.--3. "Reserved_1,Reserved_1" "0,1,2,3,4,5,6,7" newline bitfld.long 0x60 0. "ENABLE,When set to 1 enables fetching of stencil from a separate base address" "0,1" line.long 0x64 "RGX_CR_ISP_STENCIL_STORE_BASE_1,Base address in memory of the Stencil Buffer base address to store into the ISP for non-compressed ZLS formats. This alternate stencil buffer base address is selectable based on the enable bit." hexmask.long.tbyte 0x64 8.--31. 1. "Reserved_40,Reserved_40" newline hexmask.long.byte 0x64 0.--7. 1. "ADDR,1TB Addressable 16byte aligned Base Address of the Z Buffer Load base address" line.long 0x68 "RGX_CR_ISP_MASK_LOAD_BASE_0,Base address in memory of the Mask Buffer base address to load into the ISP for non-compressed ZLS formats. This alternate mask buffer base address is selectable based on the enable bit." hexmask.long 0x68 4.--31. 1. "ADDR,1TB Addressable 16byte aligned Base Address of the Z Buffer Load base address" newline bitfld.long 0x68 1.--3. "Reserved_1,Reserved_1" "0,1,2,3,4,5,6,7" newline bitfld.long 0x68 0. "ENABLE,When set to 1 enables fetching of mask from a separate base address" "0,1" line.long 0x6C "RGX_CR_ISP_MASK_LOAD_BASE_1,Base address in memory of the Mask Buffer base address to load into the ISP for non-compressed ZLS formats. This alternate mask buffer base address is selectable based on the enable bit." hexmask.long.tbyte 0x6C 8.--31. 1. "Reserved_40,Reserved_40" newline hexmask.long.byte 0x6C 0.--7. 1. "ADDR,1TB Addressable 16byte aligned Base Address of the Z Buffer Load base address" line.long 0x70 "RGX_CR_ISP_MASK_STORE_BASE_0,Base address in memory of the Mask Buffer base address to store into the ISP for non-compressed ZLS formats. This alternate mask buffer base address is selectable based on the enable bit." hexmask.long 0x70 4.--31. 1. "ADDR,1TB Addressable 16byte aligned Base Address of the Z Buffer Load base address" newline bitfld.long 0x70 1.--3. "Reserved_1,Reserved_1" "0,1,2,3,4,5,6,7" newline bitfld.long 0x70 0. "ENABLE,When set to 1 enables fetching of mask from a separate base address" "0,1" line.long 0x74 "RGX_CR_ISP_MASK_STORE_BASE_1,Base address in memory of the Mask Buffer base address to store into the ISP for non-compressed ZLS formats. This alternate mask buffer base address is selectable based on the enable bit." hexmask.long.tbyte 0x74 8.--31. 1. "Reserved_40,Reserved_40" newline hexmask.long.byte 0x74 0.--7. 1. "ADDR,1TB Addressable 16byte aligned Base Address of the Z Buffer Load base address" repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) group.long ($2+0xF80)++0x3 line.long 0x0 "RGX_CR_ISP_BGOBJDEPTH_$1,The ISP operates by comparing depth values of incoming objects with the results of previous depth compares. in order to make sure there are no unitialised values at the start of the tile or to cover pixels where there are no.." hexmask.long 0x0 0.--31. 1. "VALUE,Note the format in this register has to be consistent with the format defined by ZLS_STORE_FORMAT register. If depth buffer is F32 then the value here should be IEEE 754 single precisoin floating point If depth buffer is /INT16 then the value.." repeat.end group.long 0xF88++0x7 line.long 0x0 "RGX_CR_ISP_BGOBJVALS_0,This register provides enable. mask and stencil information for the hardware background object." hexmask.long.tbyte 0x0 10.--31. 1. "Reserved_10,Reserved_10" newline bitfld.long 0x0 9. "ENABLEBGTAG,When set to 1 at the start of each tile the ISP tag buffer is initialised with the background object tag (default = 1)" "0,1" newline bitfld.long 0x0 8. "MASK,Hardware background object mask plane" "0,1" newline hexmask.long.byte 0x0 0.--7. 1. "STENCIL,Hardware background object stencil" line.long 0x4 "RGX_CR_ISP_BGOBJVALS_1,This register provides enable. mask and stencil information for the hardware background object." hexmask.long 0x4 0.--31. 1. "Reserved_10,Reserved_10" group.long 0xFA0++0x7 line.long 0x0 "RGX_CR_ISP_GRIDOFFSET_0,Sample position grid offset for use when MSAA/ODAA is DISABLED DX (0.0.0.0) OpenGL (0.5.0.5) Acts as the 9th multisample position when MSAA is ENABLED." hexmask.long.tbyte 0x0 8.--31. 1. "Reserved_8,Reserved_8" newline hexmask.long.byte 0x0 4.--7. 1. "GRID_Y,Unsigned sub-pixel offset" newline hexmask.long.byte 0x0 0.--3. 1. "GRID_X,Unsigned sub-pixel offset" line.long 0x4 "RGX_CR_ISP_GRIDOFFSET_1,Sample position grid offset for use when MSAA/ODAA is DISABLED DX (0.0.0.0) OpenGL (0.5.0.5) Acts as the 9th multisample position when MSAA is ENABLED." hexmask.long 0x4 0.--31. 1. "Reserved_8,Reserved_8" repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) group.long ($2+0xFA8)++0x3 line.long 0x0 "RGX_CR_ISP_MULTISAMPLECTL_$1,Sample position grid offset for use in 2x. 4x. 8xMSAA and ODAA modes." hexmask.long.byte 0x0 28.--31. 1. "MSAA_Y3,Unsigned sub-pixel offset for the 4th multisample Y position" newline hexmask.long.byte 0x0 24.--27. 1. "MSAA_X3,Unsigned sub-pixel offset for the 4th multisample X position" newline hexmask.long.byte 0x0 20.--23. 1. "MSAA_Y2,Unsigned sub-pixel offset for the 3rd multisample Y position" newline hexmask.long.byte 0x0 16.--19. 1. "MSAA_X2,Unsigned sub-pixel offset for the 3rd multisample X position" newline hexmask.long.byte 0x0 12.--15. 1. "MSAA_Y1,Unsigned sub-pixel offset for the 2nd multisample Y position" newline hexmask.long.byte 0x0 8.--11. 1. "MSAA_X1,Unsigned sub-pixel offset for the 2nd multisample X position" newline hexmask.long.byte 0x0 4.--7. 1. "MSAA_Y0,Unsigned sub-pixel offset for the 1st multisample Y position" newline hexmask.long.byte 0x0 0.--3. 1. "MSAA_X0,Unsigned sub-pixel offset for the 1st multisample X position" repeat.end group.long 0xFB0++0x2F line.long 0x0 "RGX_CR_ISP_SCISSOR_BASE_0,RGX_CR_ISP_SCISSOR_BASE_0" hexmask.long 0x0 2.--31. 1. "ADDR,1TB range 32-bit aligned base address" newline bitfld.long 0x0 0.--1. "Reserved_0,Reserved_0" "0,1,2,3" line.long 0x4 "RGX_CR_ISP_SCISSOR_BASE_1,RGX_CR_ISP_SCISSOR_BASE_1" hexmask.long.tbyte 0x4 8.--31. 1. "Reserved_40,Reserved_40" newline hexmask.long.byte 0x4 0.--7. 1. "ADDR,1TB range 32-bit aligned base address" line.long 0x8 "RGX_CR_ISP_DBIAS_BASE_0,RGX_CR_ISP_DBIAS_BASE_0" hexmask.long 0x8 2.--31. 1. "ADDR,1TB range 32-bit aligned base address" newline bitfld.long 0x8 0.--1. "Reserved_0,Reserved_0" "0,1,2,3" line.long 0xC "RGX_CR_ISP_DBIAS_BASE_1,RGX_CR_ISP_DBIAS_BASE_1" hexmask.long.tbyte 0xC 8.--31. 1. "Reserved_40,Reserved_40" newline hexmask.long.byte 0xC 0.--7. 1. "ADDR,1TB range 32-bit aligned base address" line.long 0x10 "RGX_CR_ISP_OCLQRY_BASE_0,Base address for occlusion query counter values. For multiple phantom system. base address could be set differently and driver needs to sum up the result from different phantoms which have same occlusion query index." hexmask.long 0x10 4.--31. 1. "ADDR,1TB range 128-bit aligned base address" newline hexmask.long.byte 0x10 0.--3. 1. "Reserved_0,Reserved_0" line.long 0x14 "RGX_CR_ISP_OCLQRY_BASE_1,Base address for occlusion query counter values. For multiple phantom system. base address could be set differently and driver needs to sum up the result from different phantoms which have same occlusion query index." hexmask.long.tbyte 0x14 8.--31. 1. "Reserved_40,Reserved_40" newline hexmask.long.byte 0x14 0.--7. 1. "ADDR,1TB range 128-bit aligned base address" line.long 0x18 "RGX_CR_ISP_PIXEL_BASE_0,Base address for control stream and primitive blocks." hexmask.long 0x18 0.--31. 1. "Reserved_0,Reserved_0" line.long 0x1C "RGX_CR_ISP_PIXEL_BASE_1,Base address for control stream and primitive blocks." hexmask.long.tbyte 0x1C 8.--31. 1. "Reserved_40,Reserved_40" newline hexmask.long.byte 0x1C 2.--7. 1. "ADDR,1TB range 16GB granularity" newline bitfld.long 0x1C 0.--1. "Reserved_0,Reserved_0" "0,1,2,3" line.long 0x20 "RGX_CR_ISP_ZLS_PIXELS_0,screen size in pixel numbers for ZLS." bitfld.long 0x20 30.--31. "Reserved_30,Reserved_30" "0,1,2,3" newline hexmask.long.word 0x20 15.--29. 1. "Y,Display width of Y in pixels minus one. 0x000 1 pixel 0x001 2 pixels ... 0x7FFF 1024*32 pixels. Subtile only supports for non-msaa mode depth load/store so For non-msaa mode if framebuffer compression or separate mask or separate stencil is.." newline hexmask.long.word 0x20 0.--14. 1. "X,Display width of X in pixels minus one. 0x000 1 pixel 0x001 2 pixels ... 0x7FFF 1024*32 pixels. Subtile only supports for non-msaa mode depth load/store so For non-msaa mode if framebuffer compression or separate mask or separate stencil is.." line.long 0x24 "RGX_CR_ISP_ZLS_PIXELS_1,screen size in pixel numbers for ZLS." hexmask.long 0x24 0.--31. 1. "Reserved_30,Reserved_30" line.long 0x28 "RGX_CR_ISP_CTL2_0,RGX_CR_ISP_CTL2_0" hexmask.long 0x28 5.--31. 1. "Reserved_5,Reserved_5" newline hexmask.long.byte 0x28 0.--4. 1. "DEPTHBUFFERS_IN_USE,Specifies the number of depth buffers to use" line.long 0x2C "RGX_CR_ISP_CTL2_1,RGX_CR_ISP_CTL2_1" hexmask.long 0x2C 0.--31. 1. "Reserved_5,Reserved_5" wgroup.long 0x1000++0x7 line.long 0x0 "RGX_CR_ISP_START_CONTEXT_STORE_0,Writing '1' to this register initiates a 3D context store" hexmask.long 0x0 1.--31. 1. "Reserved_1,Reserved_1" newline bitfld.long 0x0 0. "PULSE,PULSE" "0,1" line.long 0x4 "RGX_CR_ISP_START_CONTEXT_STORE_1,Writing '1' to this register initiates a 3D context store" hexmask.long 0x4 0.--31. 1. "Reserved_1,Reserved_1" rgroup.long 0x1008++0xF line.long 0x0 "RGX_CR_ISP_STORE0_0,ISP context store register" bitfld.long 0x0 31. "Reserved_31,Reserved_31" "0,1" newline bitfld.long 0x0 30. "ACTIVE,ACTIVE" "0,1" newline bitfld.long 0x0 29. "EOR,EOR" "0,1" newline bitfld.long 0x0 28. "TILE_LAST,TILE_LAST" "0,1" newline hexmask.long.byte 0x0 24.--27. 1. "MT,MT" newline bitfld.long 0x0 22.--23. "Reserved_22,Reserved_22" "0,1,2,3" newline hexmask.long.word 0x0 12.--21. 1. "TILE_X,TILE_X" newline bitfld.long 0x0 10.--11. "Reserved_10,Reserved_10" "0,1,2,3" newline hexmask.long.word 0x0 0.--9. 1. "TILE_Y,TILE_Y" line.long 0x4 "RGX_CR_ISP_STORE0_1,ISP context store register" hexmask.long 0x4 0.--31. 1. "Reserved_31,Reserved_31" line.long 0x8 "RGX_CR_ISP_STORE1_0,ISP context store register" bitfld.long 0x8 31. "Reserved_31,Reserved_31" "0,1" newline bitfld.long 0x8 30. "ACTIVE,ACTIVE" "0,1" newline bitfld.long 0x8 29. "EOR,EOR" "0,1" newline bitfld.long 0x8 28. "TILE_LAST,TILE_LAST" "0,1" newline hexmask.long.byte 0x8 24.--27. 1. "MT,MT" newline bitfld.long 0x8 22.--23. "Reserved_22,Reserved_22" "0,1,2,3" newline hexmask.long.word 0x8 12.--21. 1. "TILE_X,TILE_X" newline bitfld.long 0x8 10.--11. "Reserved_10,Reserved_10" "0,1,2,3" newline hexmask.long.word 0x8 0.--9. 1. "TILE_Y,TILE_Y" line.long 0xC "RGX_CR_ISP_STORE1_1,ISP context store register" hexmask.long 0xC 0.--31. 1. "Reserved_31,Reserved_31" group.long 0x1020++0xF line.long 0x0 "RGX_CR_ISP_RESUME0_0,ISP context resume register" hexmask.long.word 0x0 22.--31. 1. "Reserved_22,Reserved_22" newline hexmask.long.word 0x0 12.--21. 1. "TILE_X,TILE_X" newline bitfld.long 0x0 10.--11. "Reserved_10,Reserved_10" "0,1,2,3" newline hexmask.long.word 0x0 0.--9. 1. "TILE_Y,TILE_Y" line.long 0x4 "RGX_CR_ISP_RESUME0_1,ISP context resume register" hexmask.long 0x4 0.--31. 1. "Reserved_22,Reserved_22" line.long 0x8 "RGX_CR_ISP_RESUME1_0,ISP context resume register" hexmask.long.word 0x8 22.--31. 1. "Reserved_22,Reserved_22" newline hexmask.long.word 0x8 12.--21. 1. "TILE_X,TILE_X" newline bitfld.long 0x8 10.--11. "Reserved_10,Reserved_10" "0,1,2,3" newline hexmask.long.word 0x8 0.--9. 1. "TILE_Y,TILE_Y" line.long 0xC "RGX_CR_ISP_RESUME1_1,ISP context resume register" hexmask.long 0xC 0.--31. 1. "Reserved_22,Reserved_22" rgroup.long 0x1038++0xF line.long 0x0 "RGX_CR_ISP_STATUS_0,ISP status registers" hexmask.long 0x0 3.--31. 1. "Reserved_3,Reserved_3" newline bitfld.long 0x0 2. "SPLIT_MAX,Split Render Maximum Threshold has been Exceeded" "0,1" newline bitfld.long 0x0 1. "ACTIVE,ISP is Active first tile in the render has been assigned" "0,1" newline bitfld.long 0x0 0. "EOR,ISP has assigned the last tile in the render" "0,1" line.long 0x4 "RGX_CR_ISP_STATUS_1,ISP status registers" hexmask.long 0x4 0.--31. 1. "Reserved_3,Reserved_3" line.long 0x8 "RGX_CR_RAST_IDLE_0,RGX_CR_RAST_IDLE_0" hexmask.long 0x8 5.--31. 1. "Reserved_5,Reserved_5" newline bitfld.long 0x8 4. "TFPU,TFPU Module IDLE" "0,1" newline bitfld.long 0x8 3. "TPF,TPF Module IDLE" "0,1" newline bitfld.long 0x8 2. "IFPU,IFPU Module IDLE" "0,1" newline bitfld.long 0x8 1. "ISP,ISP Module IDLE" "0,1" newline bitfld.long 0x8 0. "IPF,IPF Module IDLE" "0,1" line.long 0xC "RGX_CR_RAST_IDLE_1,RGX_CR_RAST_IDLE_1" hexmask.long 0xC 0.--31. 1. "Reserved_5,Reserved_5" repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) rgroup.long ($2+0x1048)++0x3 line.long 0x0 "RGX_CR_ISP_PWR_NUM_$1,RGX_CR_ISP_PWR_NUM_0" hexmask.long 0x0 0.--31. 1. "PIXELS_PROCESS,Number of depth tested pixels(non-MSAA) or samples(MSAA) processed" repeat.end repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) rgroup.long ($2+0x1058)++0x3 line.long 0x0 "RGX_CR_TFPU_PWR_NUM_$1,RGX_CR_TFPU_PWR_NUM_0" hexmask.long 0x0 0.--31. 1. "PRIMITIVES_PROCESSED,Number of primitives processed" repeat.end repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) group.long ($2+0x11D0)++0x3 line.long 0x0 "RGX_CR_ISP_MERGE_LOWER_X_$1,Used by the IFPU to generate the angle vectors used for triangle merging" hexmask.long 0x0 0.--31. 1. "VALUE,tan(15)/16k screen size" repeat.end repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) group.long ($2+0x11D8)++0x3 line.long 0x0 "RGX_CR_ISP_MERGE_LOWER_Y_$1,Used by the IFPU to generate the angle vectors used for triangle merging" hexmask.long 0x0 0.--31. 1. "VALUE,tan(15)/16k screen size" repeat.end repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) group.long ($2+0x11E0)++0x3 line.long 0x0 "RGX_CR_ISP_MERGE_UPPER_X_$1,RGX_CR_ISP_MERGE_UPPER_X_0" hexmask.long 0x0 0.--31. 1. "VALUE,tan(60)/16k screen size" repeat.end repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) group.long ($2+0x11E8)++0x3 line.long 0x0 "RGX_CR_ISP_MERGE_UPPER_Y_$1,Used by the IFPU to generate the angle vectors used for triangle merging" hexmask.long 0x0 0.--31. 1. "VALUE,tan(60)/16k screen size" repeat.end repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) group.long ($2+0x11F0)++0x3 line.long 0x0 "RGX_CR_ISP_MERGE_SCALE_X_$1,RGX_CR_ISP_MERGE_SCALE_X_0" hexmask.long 0x0 0.--31. 1. "VALUE,16 * default screen size of 16k" repeat.end repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) group.long ($2+0x11F8)++0x3 line.long 0x0 "RGX_CR_ISP_MERGE_SCALE_Y_$1,Used by the IFPU to generate the angle vectors used for triangle merging" hexmask.long 0x0 0.--31. 1. "VALUE,16 * default screen size of 16k" repeat.end group.long 0x1200++0x57 line.long 0x0 "RGX_CR_BIF_CAT_BASE0_0,RGX_CR_BIF_CAT_BASE0_0" hexmask.long.tbyte 0x0 12.--31. 1. "ADDR,ADDR" newline hexmask.long.word 0x0 0.--11. 1. "Reserved_0,Reserved_0" line.long 0x4 "RGX_CR_BIF_CAT_BASE0_1,RGX_CR_BIF_CAT_BASE0_1" hexmask.long.tbyte 0x4 8.--31. 1. "Reserved_40,Reserved_40" newline hexmask.long.byte 0x4 0.--7. 1. "ADDR,ADDR" line.long 0x8 "RGX_CR_BIF_CAT_BASE1_0,RGX_CR_BIF_CAT_BASE1_0" hexmask.long.tbyte 0x8 12.--31. 1. "ADDR,ADDR" newline hexmask.long.word 0x8 0.--11. 1. "Reserved_0,Reserved_0" line.long 0xC "RGX_CR_BIF_CAT_BASE1_1,RGX_CR_BIF_CAT_BASE1_1" hexmask.long.tbyte 0xC 8.--31. 1. "Reserved_40,Reserved_40" newline hexmask.long.byte 0xC 0.--7. 1. "ADDR,ADDR" line.long 0x10 "RGX_CR_BIF_CAT_BASE2_0,RGX_CR_BIF_CAT_BASE2_0" hexmask.long.tbyte 0x10 12.--31. 1. "ADDR,ADDR" newline hexmask.long.word 0x10 0.--11. 1. "Reserved_0,Reserved_0" line.long 0x14 "RGX_CR_BIF_CAT_BASE2_1,RGX_CR_BIF_CAT_BASE2_1" hexmask.long.tbyte 0x14 8.--31. 1. "Reserved_40,Reserved_40" newline hexmask.long.byte 0x14 0.--7. 1. "ADDR,ADDR" line.long 0x18 "RGX_CR_BIF_CAT_BASE3_0,RGX_CR_BIF_CAT_BASE3_0" hexmask.long.tbyte 0x18 12.--31. 1. "ADDR,ADDR" newline hexmask.long.word 0x18 0.--11. 1. "Reserved_0,Reserved_0" line.long 0x1C "RGX_CR_BIF_CAT_BASE3_1,RGX_CR_BIF_CAT_BASE3_1" hexmask.long.tbyte 0x1C 8.--31. 1. "Reserved_40,Reserved_40" newline hexmask.long.byte 0x1C 0.--7. 1. "ADDR,ADDR" line.long 0x20 "RGX_CR_BIF_CAT_BASE4_0,RGX_CR_BIF_CAT_BASE4_0" hexmask.long.tbyte 0x20 12.--31. 1. "ADDR,ADDR" newline hexmask.long.word 0x20 0.--11. 1. "Reserved_0,Reserved_0" line.long 0x24 "RGX_CR_BIF_CAT_BASE4_1,RGX_CR_BIF_CAT_BASE4_1" hexmask.long.tbyte 0x24 8.--31. 1. "Reserved_40,Reserved_40" newline hexmask.long.byte 0x24 0.--7. 1. "ADDR,ADDR" line.long 0x28 "RGX_CR_BIF_CAT_BASE5_0,RGX_CR_BIF_CAT_BASE5_0" hexmask.long.tbyte 0x28 12.--31. 1. "ADDR,ADDR" newline hexmask.long.word 0x28 0.--11. 1. "Reserved_0,Reserved_0" line.long 0x2C "RGX_CR_BIF_CAT_BASE5_1,RGX_CR_BIF_CAT_BASE5_1" hexmask.long.tbyte 0x2C 8.--31. 1. "Reserved_40,Reserved_40" newline hexmask.long.byte 0x2C 0.--7. 1. "ADDR,ADDR" line.long 0x30 "RGX_CR_BIF_CAT_BASE6_0,RGX_CR_BIF_CAT_BASE6_0" hexmask.long.tbyte 0x30 12.--31. 1. "ADDR,ADDR" newline hexmask.long.word 0x30 0.--11. 1. "Reserved_0,Reserved_0" line.long 0x34 "RGX_CR_BIF_CAT_BASE6_1,RGX_CR_BIF_CAT_BASE6_1" hexmask.long.tbyte 0x34 8.--31. 1. "Reserved_40,Reserved_40" newline hexmask.long.byte 0x34 0.--7. 1. "ADDR,ADDR" line.long 0x38 "RGX_CR_BIF_CAT_BASE7_0,RGX_CR_BIF_CAT_BASE7_0" hexmask.long.tbyte 0x38 12.--31. 1. "ADDR,ADDR" newline hexmask.long.word 0x38 0.--11. 1. "Reserved_0,Reserved_0" line.long 0x3C "RGX_CR_BIF_CAT_BASE7_1,RGX_CR_BIF_CAT_BASE7_1" hexmask.long.tbyte 0x3C 8.--31. 1. "Reserved_40,Reserved_40" newline hexmask.long.byte 0x3C 0.--7. 1. "ADDR,ADDR" line.long 0x40 "RGX_CR_BIF_CAT_BASE_INDEX_0,Index registers per data master. Byte aligned fields to allow byte-masked access" hexmask.long.word 0x40 22.--31. 1. "Reserved_22,Reserved_22" newline bitfld.long 0x40 19.--21. "TDM,Catalogue Base number for TDM data master" "0,1,2,3,4,5,6,7" newline bitfld.long 0x40 16.--18. "CDM,Catalogue Base number for CDM data master" "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x40 11.--15. 1. "Reserved_11,Reserved_11" newline bitfld.long 0x40 8.--10. "PIXEL,Catalogue Base number for PIXEL data master" "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x40 3.--7. 1. "Reserved_3,Reserved_3" newline bitfld.long 0x40 0.--2. "TA,Catalogue Base number for TA data master" "0,1,2,3,4,5,6,7" line.long 0x44 "RGX_CR_BIF_CAT_BASE_INDEX_1,Index registers per data master. Byte aligned fields to allow byte-masked access" hexmask.long 0x44 3.--31. 1. "Reserved_35,Reserved_35" newline bitfld.long 0x44 0.--2. "HOST,Catalogue Base number for HOST data master" "0,1,2,3,4,5,6,7" line.long 0x48 "RGX_CR_BIF_PM_CAT_BASE_VCE0_0,PM catalogue base address for VCE context 0" hexmask.long.tbyte 0x48 12.--31. 1. "ADDR,ADDR" newline hexmask.long.word 0x48 2.--11. 1. "Reserved_2,Reserved_2" newline bitfld.long 0x48 1. "WRAP,Indicates address space has been fully allocated" "0,1" newline bitfld.long 0x48 0. "VALID,VALID" "0,1" line.long 0x4C "RGX_CR_BIF_PM_CAT_BASE_VCE0_1,PM catalogue base address for VCE context 0" hexmask.long.byte 0x4C 28.--31. 1. "Reserved_60,Reserved_60" newline hexmask.long.tbyte 0x4C 8.--27. 1. "INIT_PAGE,INIT_PAGE" newline hexmask.long.byte 0x4C 0.--7. 1. "ADDR,ADDR" line.long 0x50 "RGX_CR_BIF_PM_CAT_BASE_TE0_0,PM catalogue base address for TE context 0" hexmask.long.tbyte 0x50 12.--31. 1. "ADDR,ADDR" newline hexmask.long.word 0x50 2.--11. 1. "Reserved_2,Reserved_2" newline bitfld.long 0x50 1. "WRAP,WRAP" "0,1" newline bitfld.long 0x50 0. "VALID,VALID" "0,1" line.long 0x54 "RGX_CR_BIF_PM_CAT_BASE_TE0_1,PM catalogue base address for TE context 0" hexmask.long.byte 0x54 28.--31. 1. "Reserved_60,Reserved_60" newline hexmask.long.tbyte 0x54 8.--27. 1. "INIT_PAGE,INIT_PAGE" newline hexmask.long.byte 0x54 0.--7. 1. "ADDR,ADDR" group.long 0x1260++0x17 line.long 0x0 "RGX_CR_BIF_PM_CAT_BASE_ALIST0_0,PM catalogue base address for ALIST context 0" hexmask.long.tbyte 0x0 12.--31. 1. "ADDR,ADDR" newline hexmask.long.word 0x0 2.--11. 1. "Reserved_2,Reserved_2" newline bitfld.long 0x0 1. "WRAP,WRAP" "0,1" newline bitfld.long 0x0 0. "VALID,VALID" "0,1" line.long 0x4 "RGX_CR_BIF_PM_CAT_BASE_ALIST0_1,PM catalogue base address for ALIST context 0" hexmask.long.byte 0x4 28.--31. 1. "Reserved_60,Reserved_60" newline hexmask.long.tbyte 0x4 8.--27. 1. "INIT_PAGE,INIT_PAGE" newline hexmask.long.byte 0x4 0.--7. 1. "ADDR,ADDR" line.long 0x8 "RGX_CR_BIF_PM_CAT_BASE_VCE1_0,PM catalogue base address for VCE context 1" hexmask.long.tbyte 0x8 12.--31. 1. "ADDR,ADDR" newline hexmask.long.word 0x8 2.--11. 1. "Reserved_2,Reserved_2" newline bitfld.long 0x8 1. "WRAP,WRAP" "0,1" newline bitfld.long 0x8 0. "VALID,VALID" "0,1" line.long 0xC "RGX_CR_BIF_PM_CAT_BASE_VCE1_1,PM catalogue base address for VCE context 1" hexmask.long.byte 0xC 28.--31. 1. "Reserved_60,Reserved_60" newline hexmask.long.tbyte 0xC 8.--27. 1. "INIT_PAGE,INIT_PAGE" newline hexmask.long.byte 0xC 0.--7. 1. "ADDR,ADDR" line.long 0x10 "RGX_CR_BIF_PM_CAT_BASE_TE1_0,PM catalogue base address for TE context 1" hexmask.long.tbyte 0x10 12.--31. 1. "ADDR,ADDR" newline hexmask.long.word 0x10 2.--11. 1. "Reserved_2,Reserved_2" newline bitfld.long 0x10 1. "WRAP,WRAP" "0,1" newline bitfld.long 0x10 0. "VALID,VALID" "0,1" line.long 0x14 "RGX_CR_BIF_PM_CAT_BASE_TE1_1,PM catalogue base address for TE context 1" hexmask.long.byte 0x14 28.--31. 1. "Reserved_60,Reserved_60" newline hexmask.long.tbyte 0x14 8.--27. 1. "INIT_PAGE,INIT_PAGE" newline hexmask.long.byte 0x14 0.--7. 1. "ADDR,ADDR" group.long 0x1280++0x7 line.long 0x0 "RGX_CR_BIF_PM_CAT_BASE_ALIST1_0,PM catalogue base address for ALIST context 1" hexmask.long.tbyte 0x0 12.--31. 1. "ADDR,ADDR" newline hexmask.long.word 0x0 2.--11. 1. "Reserved_2,Reserved_2" newline bitfld.long 0x0 1. "WRAP,WRAP" "0,1" newline bitfld.long 0x0 0. "VALID,VALID" "0,1" line.long 0x4 "RGX_CR_BIF_PM_CAT_BASE_ALIST1_1,PM catalogue base address for ALIST context 1" hexmask.long.byte 0x4 28.--31. 1. "Reserved_60,Reserved_60" newline hexmask.long.tbyte 0x4 8.--27. 1. "INIT_PAGE,INIT_PAGE" newline hexmask.long.byte 0x4 0.--7. 1. "ADDR,ADDR" rgroup.long 0x1288++0x7 line.long 0x0 "RGX_CR_BIF_MMU_ENTRY_STATUS_0,Status of pending entry" hexmask.long.tbyte 0x0 12.--31. 1. "ADDRESS,Virtual 4KB address" newline hexmask.long.byte 0x0 8.--11. 1. "Reserved_8,Reserved_8" newline hexmask.long.byte 0x0 4.--7. 1. "CAT_BASE,Catalogue base address number" newline bitfld.long 0x0 2.--3. "Reserved_2,Reserved_2" "0,1,2,3" newline bitfld.long 0x0 0.--1. "DATA_TYPE,MMU data type '00' = PT '01' = PD '10' = PC" "0,1,2,3" line.long 0x4 "RGX_CR_BIF_MMU_ENTRY_STATUS_1,Status of pending entry" hexmask.long.tbyte 0x4 8.--31. 1. "Reserved_40,Reserved_40" newline hexmask.long.byte 0x4 0.--7. 1. "ADDRESS,Virtual 4KB address" group.long 0x1290++0x7 line.long 0x0 "RGX_CR_BIF_MMU_ENTRY_0,Indicates MMU is waiting on the driver to map an entry" hexmask.long 0x0 2.--31. 1. "Reserved_2,Reserved_2" newline bitfld.long 0x0 1. "ENABLE,When set PENDING will trigger an interrupt back to the host CPU (bypassing the FW)" "0,1" newline bitfld.long 0x0 0. "PENDING,PENDING" "0,1" line.long 0x4 "RGX_CR_BIF_MMU_ENTRY_1,Indicates MMU is waiting on the driver to map an entry" hexmask.long 0x4 0.--31. 1. "Reserved_2,Reserved_2" group.long 0x12A0++0xF line.long 0x0 "RGX_CR_BIF_CTRL_INVAL_0,Invalidation bits allowing BIF/MMU to clear when invalidation complete" hexmask.long 0x0 4.--31. 1. "Reserved_4,Reserved_4" newline bitfld.long 0x0 3. "TLB1,TLB1" "0,1" newline bitfld.long 0x0 2. "PC,PC" "0,1" newline bitfld.long 0x0 1. "PD,PD" "0,1" newline bitfld.long 0x0 0. "PT,PT" "0,1" line.long 0x4 "RGX_CR_BIF_CTRL_INVAL_1,Invalidation bits allowing BIF/MMU to clear when invalidation complete" hexmask.long 0x4 0.--31. 1. "Reserved_4,Reserved_4" line.long 0x8 "RGX_CR_BIF_CTRL_0,Miscellaneous controls" hexmask.long.tbyte 0x8 9.--31. 1. "Reserved_9,Reserved_9" newline bitfld.long 0x8 8. "PAUSE_MMU_BIF4,Stalls BIF4 input to MMU" "0,1" newline bitfld.long 0x8 7. "ENABLE_MMU_QUEUE_BYPASS,Enables bypassing of the MMU queue for cache hits" "0,1" newline bitfld.long 0x8 6. "ENABLE_MMU_AUTO_PREFETCH,Enables automatic prefetching based on incoming requests" "0,1" newline bitfld.long 0x8 5. "PAUSE_MMU_BIF3,Stalls BIF3 input to MMU" "0,1" newline bitfld.long 0x8 4. "PAUSE_MMU_BIF2,Stalls BIF2 input to MMU" "0,1" newline bitfld.long 0x8 3. "PAUSE_BIF1,Stalls BIF1 pipeline" "0,1" newline bitfld.long 0x8 2. "PAUSE_MMU_PM,Stalls PM input to MMU" "0,1" newline bitfld.long 0x8 1. "PAUSE_MMU_BIF1,Stalls BIF1 input to MMU" "0,1" newline bitfld.long 0x8 0. "PAUSE_MMU_BIF0,Stalls BIF0 input to MMU" "0,1" line.long 0xC "RGX_CR_BIF_CTRL_1,Miscellaneous controls" hexmask.long 0xC 0.--31. 1. "Reserved_9,Reserved_9" rgroup.long 0x12B0++0x27 line.long 0x0 "RGX_CR_BIF_FAULT_BANK0_MMU_STATUS_0,Indicates a fault has occurred on bank 0 and provides details of fault" hexmask.long.word 0x0 16.--31. 1. "Reserved_16,Reserved_16" newline hexmask.long.byte 0x0 12.--15. 1. "CAT_BASE,Catalogue base address number" newline bitfld.long 0x0 11. "Reserved_11,Reserved_11" "0,1" newline bitfld.long 0x0 8.--10. "PAGE_SIZE,Page size" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 7. "Reserved_7,Reserved_7" "0,1" newline bitfld.long 0x0 5.--6. "DATA_TYPE,MMU data type that was invalid (on valid fault)" "0,1,2,3" newline bitfld.long 0x0 4. "FAULT_RO,Indicates read-only fault('1') or valid fault('0')" "0,1" newline bitfld.long 0x0 3. "Reserved_3,Reserved_3" "0,1" newline bitfld.long 0x0 2. "FAULT_PM_META_RO,Indicates pm/meta protected region fault" "0,1" newline bitfld.long 0x0 1. "Reserved_1,Reserved_1" "0,1" newline bitfld.long 0x0 0. "FAULT,Indicates a fault has occured" "0,1" line.long 0x4 "RGX_CR_BIF_FAULT_BANK0_MMU_STATUS_1,Indicates a fault has occurred on bank 0 and provides details of fault" hexmask.long 0x4 0.--31. 1. "Reserved_16,Reserved_16" line.long 0x8 "RGX_CR_BIF_FAULT_BANK0_REQ_STATUS_0,Provides details of the request that faulted on bank 0" hexmask.long 0x8 4.--31. 1. "ADDRESS,ADDRESS" newline hexmask.long.byte 0x8 0.--3. 1. "Reserved_0,Reserved_0" line.long 0xC "RGX_CR_BIF_FAULT_BANK0_REQ_STATUS_1,Provides details of the request that faulted on bank 0" hexmask.long.word 0xC 21.--31. 1. "Reserved_53,Reserved_53" newline bitfld.long 0xC 20. "RNW,RNW" "0,1" newline hexmask.long.byte 0xC 14.--19. 1. "TAG_SB,TAG_SB" newline hexmask.long.byte 0xC 8.--13. 1. "TAG_ID,TAG_ID" newline hexmask.long.byte 0xC 0.--7. 1. "ADDRESS,ADDRESS" line.long 0x10 "RGX_CR_BIF_FAULT_BANK1_MMU_STATUS_0,Indicates a fault has occurred on bank 1 and provides details of fault" hexmask.long.word 0x10 16.--31. 1. "Reserved_16,Reserved_16" newline hexmask.long.byte 0x10 12.--15. 1. "CAT_BASE,Catalogue base address number" newline bitfld.long 0x10 11. "Reserved_11,Reserved_11" "0,1" newline bitfld.long 0x10 8.--10. "PAGE_SIZE,Page size" "0,1,2,3,4,5,6,7" newline bitfld.long 0x10 7. "Reserved_7,Reserved_7" "0,1" newline bitfld.long 0x10 5.--6. "DATA_TYPE,MMU data type that was invalid (on valid fault)" "0,1,2,3" newline bitfld.long 0x10 4. "FAULT_RO,Indicates read-only fault('1') of valid fault('0')" "0,1" newline bitfld.long 0x10 3. "Reserved_3,Reserved_3" "0,1" newline bitfld.long 0x10 2. "FAULT_PM_META_RO,Indicates pm/meta protected region fault" "0,1" newline bitfld.long 0x10 1. "Reserved_1,Reserved_1" "0,1" newline bitfld.long 0x10 0. "FAULT,Indicates a fault has occured" "0,1" line.long 0x14 "RGX_CR_BIF_FAULT_BANK1_MMU_STATUS_1,Indicates a fault has occurred on bank 1 and provides details of fault" hexmask.long 0x14 0.--31. 1. "Reserved_16,Reserved_16" line.long 0x18 "RGX_CR_BIF_FAULT_BANK1_REQ_STATUS_0,Provides details of the request that faulted on bank 1" hexmask.long 0x18 4.--31. 1. "ADDRESS,ADDRESS" newline hexmask.long.byte 0x18 0.--3. 1. "Reserved_0,Reserved_0" line.long 0x1C "RGX_CR_BIF_FAULT_BANK1_REQ_STATUS_1,Provides details of the request that faulted on bank 1" hexmask.long.word 0x1C 19.--31. 1. "Reserved_51,Reserved_51" newline bitfld.long 0x1C 18. "RNW,RNW" "0,1" newline hexmask.long.byte 0x1C 12.--17. 1. "TAG_SB,TAG_SB" newline hexmask.long.byte 0x1C 8.--11. 1. "TAG_ID,TAG_ID" newline hexmask.long.byte 0x1C 0.--7. 1. "ADDRESS,ADDRESS" line.long 0x20 "RGX_CR_BIF_MMU_STATUS_0,General MMU status" bitfld.long 0x20 29.--31. "Reserved_29,Reserved_29" "0,1,2,3,4,5,6,7" newline bitfld.long 0x20 28. "PM_FAULT,PM_FAULT" "0,1" newline hexmask.long.byte 0x20 20.--27. 1. "PC_DATA,PC_DATA" newline hexmask.long.byte 0x20 12.--19. 1. "PD_DATA,PD_DATA" newline hexmask.long.byte 0x20 4.--11. 1. "PT_DATA,PT_DATA" newline bitfld.long 0x20 3. "Reserved_3,Reserved_3" "0,1" newline bitfld.long 0x20 2. "STALLED,STALLED" "0,1" newline bitfld.long 0x20 1. "PAUSED,PAUSED" "0,1" newline bitfld.long 0x20 0. "BUSY,BUSY" "0,1" line.long 0x24 "RGX_CR_BIF_MMU_STATUS_1,General MMU status" hexmask.long 0x24 0.--31. 1. "Reserved_29,Reserved_29" group.long 0x12D8++0x3F line.long 0x0 "RGX_CR_BIF_TILING_CFG0_0,This register defines 8 RANGEs in which BIF Tiling can be configured. Each RANGE is given a Stride and a MIN and MAX 4KB aligned address to define the region of Address Space to be tiled. The BIF_TILING_CAT_BASE_INDEX register is.." hexmask.long.byte 0x0 28.--31. 1. "Reserved_28,Reserved_28" newline hexmask.long 0x0 0.--27. 1. "MIN_ADDRESS,4KB aligned min address for tiling" line.long 0x4 "RGX_CR_BIF_TILING_CFG0_1,This register defines 8 RANGEs in which BIF Tiling can be configured. Each RANGE is given a Stride and a MIN and MAX 4KB aligned address to define the region of Address Space to be tiled. The BIF_TILING_CAT_BASE_INDEX register is.." bitfld.long 0x4 29.--31. "XSTRIDE,defines x tile stride. The value in the register is equal to log2(number of tiles in x)-1 e. g. a value of 0 gives 2 x-tiles and a value of 3 gives 16 x-tiles" "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 28. "ENABLE,enables tiling range" "0,1" newline hexmask.long 0x4 0.--27. 1. "MAX_ADDRESS,4KB aligned max address for tiling" line.long 0x8 "RGX_CR_BIF_TILING_CFG1_0,This register defines 8 RANGEs in which BIF Tiling can be configured. Each RANGE is given a Stride and a MIN and MAX 4KB aligned address to define the region of Address Space to be tiled. The BIF_TILING_CAT_BASE_INDEX register is.." hexmask.long.byte 0x8 28.--31. 1. "Reserved_28,Reserved_28" newline hexmask.long 0x8 0.--27. 1. "MIN_ADDRESS,4KB aligned min address for tiling" line.long 0xC "RGX_CR_BIF_TILING_CFG1_1,This register defines 8 RANGEs in which BIF Tiling can be configured. Each RANGE is given a Stride and a MIN and MAX 4KB aligned address to define the region of Address Space to be tiled. The BIF_TILING_CAT_BASE_INDEX register is.." bitfld.long 0xC 29.--31. "XSTRIDE,defines x tile stride. The value in the register is equal to log2(number of tiles in x)-1 e. g. a value of 0 gives 2 x-tiles and a value of 3 gives 16 x-tiles" "0,1,2,3,4,5,6,7" newline bitfld.long 0xC 28. "ENABLE,enables tiling range" "0,1" newline hexmask.long 0xC 0.--27. 1. "MAX_ADDRESS,4KB aligned max address for tiling" line.long 0x10 "RGX_CR_BIF_TILING_CFG2_0,This register defines 8 RANGEs in which BIF Tiling can be configured. Each RANGE is given a Stride and a MIN and MAX 4KB aligned address to define the region of Address Space to be tiled. The BIF_TILING_CAT_BASE_INDEX register is.." hexmask.long.byte 0x10 28.--31. 1. "Reserved_28,Reserved_28" newline hexmask.long 0x10 0.--27. 1. "MIN_ADDRESS,4KB aligned min address for tiling" line.long 0x14 "RGX_CR_BIF_TILING_CFG2_1,This register defines 8 RANGEs in which BIF Tiling can be configured. Each RANGE is given a Stride and a MIN and MAX 4KB aligned address to define the region of Address Space to be tiled. The BIF_TILING_CAT_BASE_INDEX register is.." bitfld.long 0x14 29.--31. "XSTRIDE,defines x tile stride. The value in the register is equal to log2(number of tiles in x)-1 e. g. a value of 0 gives 2 x-tiles and a value of 3 gives 16 x-tiles" "0,1,2,3,4,5,6,7" newline bitfld.long 0x14 28. "ENABLE,enables tiling range" "0,1" newline hexmask.long 0x14 0.--27. 1. "MAX_ADDRESS,4KB aligned max address for tiling" line.long 0x18 "RGX_CR_BIF_TILING_CFG3_0,This register defines 8 RANGEs in which BIF Tiling can be configured. Each RANGE is given a Stride and a MIN and MAX 4KB aligned address to define the region of Address Space to be tiled. The BIF_TILING_CAT_BASE_INDEX register is.." hexmask.long.byte 0x18 28.--31. 1. "Reserved_28,Reserved_28" newline hexmask.long 0x18 0.--27. 1. "MIN_ADDRESS,4KB aligned min address for tiling" line.long 0x1C "RGX_CR_BIF_TILING_CFG3_1,This register defines 8 RANGEs in which BIF Tiling can be configured. Each RANGE is given a Stride and a MIN and MAX 4KB aligned address to define the region of Address Space to be tiled. The BIF_TILING_CAT_BASE_INDEX register is.." bitfld.long 0x1C 29.--31. "XSTRIDE,defines x tile stride. The value in the register is equal to log2(number of tiles in x)-1 e. g. a value of 0 gives 2 x-tiles and a value of 3 gives 16 x-tiles" "0,1,2,3,4,5,6,7" newline bitfld.long 0x1C 28. "ENABLE,enables tiling range" "0,1" newline hexmask.long 0x1C 0.--27. 1. "MAX_ADDRESS,4KB aligned max address for tiling" line.long 0x20 "RGX_CR_BIF_TILING_CFG4_0,This register defines 8 RANGEs in which BIF Tiling can be configured. Each RANGE is given a Stride and a MIN and MAX 4KB aligned address to define the region of Address Space to be tiled. The BIF_TILING_CAT_BASE_INDEX register is.." hexmask.long.byte 0x20 28.--31. 1. "Reserved_28,Reserved_28" newline hexmask.long 0x20 0.--27. 1. "MIN_ADDRESS,4KB aligned min address for tiling" line.long 0x24 "RGX_CR_BIF_TILING_CFG4_1,This register defines 8 RANGEs in which BIF Tiling can be configured. Each RANGE is given a Stride and a MIN and MAX 4KB aligned address to define the region of Address Space to be tiled. The BIF_TILING_CAT_BASE_INDEX register is.." bitfld.long 0x24 29.--31. "XSTRIDE,defines x tile stride. The value in the register is equal to log2(number of tiles in x)-1 e. g. a value of 0 gives 2 x-tiles and a value of 3 gives 16 x-tiles" "0,1,2,3,4,5,6,7" newline bitfld.long 0x24 28. "ENABLE,enables tiling range" "0,1" newline hexmask.long 0x24 0.--27. 1. "MAX_ADDRESS,4KB aligned max address for tiling" line.long 0x28 "RGX_CR_BIF_TILING_CFG5_0,This register defines 8 RANGEs in which BIF Tiling can be configured. Each RANGE is given a Stride and a MIN and MAX 4KB aligned address to define the region of Address Space to be tiled. The BIF_TILING_CAT_BASE_INDEX register is.." hexmask.long.byte 0x28 28.--31. 1. "Reserved_28,Reserved_28" newline hexmask.long 0x28 0.--27. 1. "MIN_ADDRESS,4KB aligned min address for tiling" line.long 0x2C "RGX_CR_BIF_TILING_CFG5_1,This register defines 8 RANGEs in which BIF Tiling can be configured. Each RANGE is given a Stride and a MIN and MAX 4KB aligned address to define the region of Address Space to be tiled. The BIF_TILING_CAT_BASE_INDEX register is.." bitfld.long 0x2C 29.--31. "XSTRIDE,defines x tile stride. The value in the register is equal to log2(number of tiles in x)-1 e. g. a value of 0 gives 2 x-tiles and a value of 3 gives 16 x-tiles" "0,1,2,3,4,5,6,7" newline bitfld.long 0x2C 28. "ENABLE,enables tiling range" "0,1" newline hexmask.long 0x2C 0.--27. 1. "MAX_ADDRESS,4KB aligned max address for tiling" line.long 0x30 "RGX_CR_BIF_TILING_CFG6_0,This register defines 8 RANGEs in which BIF Tiling can be configured. Each RANGE is given a Stride and a MIN and MAX 4KB aligned address to define the region of Address Space to be tiled. The BIF_TILING_CAT_BASE_INDEX register is.." hexmask.long.byte 0x30 28.--31. 1. "Reserved_28,Reserved_28" newline hexmask.long 0x30 0.--27. 1. "MIN_ADDRESS,4KB aligned min address for tiling" line.long 0x34 "RGX_CR_BIF_TILING_CFG6_1,This register defines 8 RANGEs in which BIF Tiling can be configured. Each RANGE is given a Stride and a MIN and MAX 4KB aligned address to define the region of Address Space to be tiled. The BIF_TILING_CAT_BASE_INDEX register is.." bitfld.long 0x34 29.--31. "XSTRIDE,defines x tile stride. The value in the register is equal to log2(number of tiles in x)-1 e. g. a value of 0 gives 2 x-tiles and a value of 3 gives 16 x-tiles" "0,1,2,3,4,5,6,7" newline bitfld.long 0x34 28. "ENABLE,enables tiling range" "0,1" newline hexmask.long 0x34 0.--27. 1. "MAX_ADDRESS,4KB aligned max address for tiling" line.long 0x38 "RGX_CR_BIF_TILING_CFG7_0,This register defines 8 RANGEs in which BIF Tiling can be configured. Each RANGE is given a Stride and a MIN and MAX 4KB aligned address to define the region of Address Space to be tiled. The BIF_TILING_CAT_BASE_INDEX register is.." hexmask.long.byte 0x38 28.--31. 1. "Reserved_28,Reserved_28" newline hexmask.long 0x38 0.--27. 1. "MIN_ADDRESS,4KB aligned min address for tiling" line.long 0x3C "RGX_CR_BIF_TILING_CFG7_1,This register defines 8 RANGEs in which BIF Tiling can be configured. Each RANGE is given a Stride and a MIN and MAX 4KB aligned address to define the region of Address Space to be tiled. The BIF_TILING_CAT_BASE_INDEX register is.." bitfld.long 0x3C 29.--31. "XSTRIDE,defines x tile stride. The value in the register is equal to log2(number of tiles in x)-1 e. g. a value of 0 gives 2 x-tiles and a value of 3 gives 16 x-tiles" "0,1,2,3,4,5,6,7" newline bitfld.long 0x3C 28. "ENABLE,enables tiling range" "0,1" newline hexmask.long 0x3C 0.--27. 1. "MAX_ADDRESS,4KB aligned max address for tiling" repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) group.long ($2+0x1318)++0x3 line.long 0x0 "RGX_CR_BIF_TILING_CAT_BASE_INDEX_$1,This register defines the Catalogue Base Index applying to each tiling configuration register. An input address passing the RANGE test is also qualified against the RANGE INDEX before Tiling can proceed." hexmask.long.byte 0x0 27.--31. 1. "Reserved_27,Reserved_27" newline bitfld.long 0x0 24.--26. "RANGE3,RANGE3" "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x0 19.--23. 1. "Reserved_19,Reserved_19" newline bitfld.long 0x0 16.--18. "RANGE2,RANGE2" "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x0 11.--15. 1. "Reserved_11,Reserved_11" newline bitfld.long 0x0 8.--10. "RANGE1,RANGE1" "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x0 3.--7. 1. "Reserved_3,Reserved_3" newline bitfld.long 0x0 0.--2. "RANGE0,RANGE0" "0,1,2,3,4,5,6,7" repeat.end rgroup.long 0x1320++0x1F line.long 0x0 "RGX_CR_BIF_READS_EXT_STATUS_0,Outstanding read data external to BIF for BIF128 and MMU" hexmask.long.word 0x0 23.--31. 1. "Reserved_23,Reserved_23" newline hexmask.long.byte 0x0 16.--22. 1. "MMU,MMU" newline hexmask.long.word 0x0 0.--15. 1. "BANK1,BANK1" line.long 0x4 "RGX_CR_BIF_READS_EXT_STATUS_1,Outstanding read data external to BIF for BIF128 and MMU" hexmask.long 0x4 0.--31. 1. "Reserved_23,Reserved_23" line.long 0x8 "RGX_CR_BIF_READS_INT_STATUS_0,Outstanding 256-bit read data in return data FIFO for BIF128 and MMU" hexmask.long.word 0x8 23.--31. 1. "Reserved_23,Reserved_23" newline hexmask.long.byte 0x8 16.--22. 1. "MMU,MMU" newline hexmask.long.word 0x8 0.--15. 1. "BANK1,BANK1" line.long 0xC "RGX_CR_BIF_READS_INT_STATUS_1,Outstanding 256-bit read data in return data FIFO for BIF128 and MMU" hexmask.long 0xC 0.--31. 1. "Reserved_23,Reserved_23" line.long 0x10 "RGX_CR_BIFPM_READS_INT_STATUS_0,Outstanding 256-bit read data in return data FIFO for BIF256" hexmask.long.word 0x10 16.--31. 1. "Reserved_16,Reserved_16" newline hexmask.long.word 0x10 0.--15. 1. "BANK0,BANK0" line.long 0x14 "RGX_CR_BIFPM_READS_INT_STATUS_1,Outstanding 256-bit read data in return data FIFO for BIF256" hexmask.long 0x14 0.--31. 1. "Reserved_16,Reserved_16" line.long 0x18 "RGX_CR_BIFPM_READS_EXT_STATUS_0,Outstanding 256-bit read data external to BIF for BIF256" hexmask.long.word 0x18 16.--31. 1. "Reserved_16,Reserved_16" newline hexmask.long.word 0x18 0.--15. 1. "BANK0,BANK0" line.long 0x1C "RGX_CR_BIFPM_READS_EXT_STATUS_1,Outstanding 256-bit read data external to BIF for BIF256" hexmask.long 0x1C 0.--31. 1. "Reserved_16,Reserved_16" group.long 0x1340++0xF line.long 0x0 "RGX_CR_BIFPM_CTRL_0,Miscellaneous controls" hexmask.long 0x0 2.--31. 1. "Reserved_2,Reserved_2" newline bitfld.long 0x0 1. "ENABLE_SLC_STALLING,Enables BIF to stall returns from SLC so that requests can be made even when there is no space in the BIF return buffer (only when no chance of lockup)" "0,1" newline bitfld.long 0x0 0. "PAUSE_BIF0,Stalls BIF0 pipeline" "0,1" line.long 0x4 "RGX_CR_BIFPM_CTRL_1,Miscellaneous controls" hexmask.long 0x4 0.--31. 1. "Reserved_2,Reserved_2" line.long 0x8 "RGX_CR_BIFPM_CTRL_INVAL_0,Invalidation bits allowing BIF to clear when invalidation complete" hexmask.long 0x8 1.--31. 1. "Reserved_1,Reserved_1" newline bitfld.long 0x8 0. "TLB0,TLB0" "0,1" line.long 0xC "RGX_CR_BIFPM_CTRL_INVAL_1,Invalidation bits allowing BIF to clear when invalidation complete" hexmask.long 0xC 0.--31. 1. "Reserved_1,Reserved_1" rgroup.long 0x1350++0xF line.long 0x0 "RGX_CR_BIFPM_STATUS_MMU_0,Outstanding MMU requests from BIF0" hexmask.long.tbyte 0x0 8.--31. 1. "Reserved_8,Reserved_8" newline hexmask.long.byte 0x0 0.--7. 1. "REQUESTS,REQUESTS" line.long 0x4 "RGX_CR_BIFPM_STATUS_MMU_1,Outstanding MMU requests from BIF0" hexmask.long 0x4 0.--31. 1. "Reserved_8,Reserved_8" line.long 0x8 "RGX_CR_BIF_STATUS_MMU_0,Outstanding MMU requests from BIF1" hexmask.long.tbyte 0x8 8.--31. 1. "Reserved_8,Reserved_8" newline hexmask.long.byte 0x8 0.--7. 1. "REQUESTS,REQUESTS" line.long 0xC "RGX_CR_BIF_STATUS_MMU_1,Outstanding MMU requests from BIF1" hexmask.long 0xC 0.--31. 1. "Reserved_8,Reserved_8" group.long 0x1360++0x7 line.long 0x0 "RGX_CR_BIF_TILING_0,Sets tiling mode between 256byte x 16 rows (0) and 512byte x 8 rows (1)" hexmask.long 0x0 1.--31. 1. "Reserved_1,Reserved_1" newline bitfld.long 0x0 0. "MODE,MODE" "0,1" line.long 0x4 "RGX_CR_BIF_TILING_1,Sets tiling mode between 256byte x 16 rows (0) and 512byte x 8 rows (1)" hexmask.long 0x4 0.--31. 1. "Reserved_1,Reserved_1" repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) rgroup.long ($2+0x1370)++0x3 line.long 0x0 "RGX_CR_BIF_BLACKPEARL_PWR_$1,Power monitoring register" hexmask.long 0x0 0.--31. 1. "NUM_256BIT_TRANS,Number of 256-bit transactions" repeat.end repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) rgroup.long ($2+0x1378)++0x3 line.long 0x0 "RGX_CR_BIF_JONES_PWR_$1,Power monitoring register" hexmask.long 0x0 0.--31. 1. "NUM_256BIT_TRANS,Number of 256-bit transactions" repeat.end group.long 0x13E0++0x7 line.long 0x0 "RGX_CR_BIF_FAULT_READ_0,Specifies physical address to read from in the event of a faulting read request from BIF1" hexmask.long 0x0 4.--31. 1. "ADDRESS,ADDRESS" newline hexmask.long.byte 0x0 0.--3. 1. "Reserved_0,Reserved_0" line.long 0x4 "RGX_CR_BIF_FAULT_READ_1,Specifies physical address to read from in the event of a faulting read request from BIF1" hexmask.long.tbyte 0x4 8.--31. 1. "Reserved_40,Reserved_40" newline hexmask.long.byte 0x4 0.--7. 1. "ADDRESS,ADDRESS" repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) rgroup.long ($2+0x13E8)++0x3 line.long 0x0 "RGX_CR_BIF_PWR_$1,Power monitoring register" hexmask.long 0x0 0.--31. 1. "NUM_256BIT_TRANS,Number of 256-bit transactions" repeat.end group.long 0x13F8++0x7 line.long 0x0 "RGX_CR_BIF_MCU_RESERVED_0,Allows driver to change the amount of space in the return data FIFO reserved for the MCU" hexmask.long 0x0 5.--31. 1. "Reserved_5,Reserved_5" newline hexmask.long.byte 0x0 0.--4. 1. "SPACE,Granularity of 8 spaces minimum legal value 0x1" line.long 0x4 "RGX_CR_BIF_MCU_RESERVED_1,Allows driver to change the amount of space in the return data FIFO reserved for the MCU" hexmask.long 0x4 0.--31. 1. "Reserved_5,Reserved_5" rgroup.long 0x1430++0x27 line.long 0x0 "RGX_CR_TEXAS_BIF_FAULT_BANK0_MMU_STATUS_0,Indicates a fault has occurred on bank 0 and provides details of fault" hexmask.long.word 0x0 16.--31. 1. "Reserved_16,Reserved_16" newline hexmask.long.byte 0x0 12.--15. 1. "CAT_BASE,Catalogue base address number" newline bitfld.long 0x0 11. "Reserved_11,Reserved_11" "0,1" newline bitfld.long 0x0 8.--10. "PAGE_SIZE,Page size" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 7. "Reserved_7,Reserved_7" "0,1" newline bitfld.long 0x0 5.--6. "DATA_TYPE,MMU data type that was invalid (on valid fault)" "0,1,2,3" newline bitfld.long 0x0 4. "FAULT_RO,Indicates read-only fault('1') or valid fault('0')" "0,1" newline bitfld.long 0x0 3. "Reserved_3,Reserved_3" "0,1" newline bitfld.long 0x0 2. "FAULT_PM_META_RO,Indicates pm/meta protected region fault" "0,1" newline bitfld.long 0x0 1. "Reserved_1,Reserved_1" "0,1" newline bitfld.long 0x0 0. "FAULT,Indicates a fault has occured" "0,1" line.long 0x4 "RGX_CR_TEXAS_BIF_FAULT_BANK0_MMU_STATUS_1,Indicates a fault has occurred on bank 0 and provides details of fault" hexmask.long 0x4 0.--31. 1. "Reserved_16,Reserved_16" line.long 0x8 "RGX_CR_TEXAS_BIF_FAULT_BANK0_REQ_STATUS_0,Provides details of the request that faulted on bank 0" hexmask.long 0x8 4.--31. 1. "ADDRESS,ADDRESS" newline hexmask.long.byte 0x8 0.--3. 1. "Reserved_0,Reserved_0" line.long 0xC "RGX_CR_TEXAS_BIF_FAULT_BANK0_REQ_STATUS_1,Provides details of the request that faulted on bank 0" hexmask.long.word 0xC 19.--31. 1. "Reserved_51,Reserved_51" newline bitfld.long 0xC 18. "RNW,RNW" "0,1" newline hexmask.long.byte 0xC 12.--17. 1. "TAG_SB,TAG_SB" newline hexmask.long.byte 0xC 8.--11. 1. "TAG_ID,TAG_ID" newline hexmask.long.byte 0xC 0.--7. 1. "ADDRESS,ADDRESS" line.long 0x10 "RGX_CR_TEXAS_BIFPM_READS_INT_STATUS_0,Outstanding 256-bit read data in return data FIFO for BIF256" hexmask.long.word 0x10 16.--31. 1. "Reserved_16,Reserved_16" newline hexmask.long.word 0x10 0.--15. 1. "BANK0,BANK0" line.long 0x14 "RGX_CR_TEXAS_BIFPM_READS_INT_STATUS_1,Outstanding 256-bit read data in return data FIFO for BIF256" hexmask.long 0x14 0.--31. 1. "Reserved_16,Reserved_16" line.long 0x18 "RGX_CR_TEXAS_BIFPM_READS_EXT_STATUS_0,Outstanding 256-bit read data external to BIF for BIF256" hexmask.long.word 0x18 16.--31. 1. "Reserved_16,Reserved_16" newline hexmask.long.word 0x18 0.--15. 1. "BANK0,BANK0" line.long 0x1C "RGX_CR_TEXAS_BIFPM_READS_EXT_STATUS_1,Outstanding 256-bit read data external to BIF for BIF256" hexmask.long 0x1C 0.--31. 1. "Reserved_16,Reserved_16" line.long 0x20 "RGX_CR_TEXAS_BIFPM_STATUS_MMU_0,Outstanding MMU requests from BIF0" hexmask.long.tbyte 0x20 8.--31. 1. "Reserved_8,Reserved_8" newline hexmask.long.byte 0x20 0.--7. 1. "REQUESTS,REQUESTS" line.long 0x24 "RGX_CR_TEXAS_BIFPM_STATUS_MMU_1,Outstanding MMU requests from BIF0" hexmask.long 0x24 0.--31. 1. "Reserved_8,Reserved_8" repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) group.long ($2+0x1460)++0x3 line.long 0x0 "RGX_CR_BIF_OSID0_$1,Defines OSID for each CAT_BASE" hexmask.long.byte 0x0 27.--31. 1. "Reserved_27,Reserved_27" newline bitfld.long 0x0 24.--26. "CBASE3,OSID for CAT BASE 3" "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x0 19.--23. 1. "Reserved_19,Reserved_19" newline bitfld.long 0x0 16.--18. "CBASE2,OSID for CAT BASE 2" "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x0 11.--15. 1. "Reserved_11,Reserved_11" newline bitfld.long 0x0 8.--10. "CBASE1,OSID for CAT BASE 1" "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x0 3.--7. 1. "Reserved_3,Reserved_3" newline bitfld.long 0x0 0.--2. "CBASE0,OSID for CAT BASE 0" "0,1,2,3,4,5,6,7" repeat.end group.long 0x1468++0x7 line.long 0x0 "RGX_CR_BIF_OSID1_0,Defines OSID for each data master" hexmask.long.tbyte 0x0 11.--31. 1. "Reserved_11,Reserved_11" newline bitfld.long 0x0 8.--10. "PM_CTX1,OSID for VCE1 TE1 and ALIST1" "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x0 3.--7. 1. "Reserved_3,Reserved_3" newline bitfld.long 0x0 0.--2. "PM_CTX0,OSID for VCE0 TE0 and ALIST0" "0,1,2,3,4,5,6,7" line.long 0x4 "RGX_CR_BIF_OSID1_1,Defines OSID for each data master" hexmask.long 0x4 0.--31. 1. "Reserved_11,Reserved_11" group.long 0x1500++0x7 line.long 0x0 "RGX_CR_PBE_0,The PBE(Pixel back end) module scales and packs the pixel data before writing to memory. this register contains global control signals." hexmask.long.tbyte 0x0 9.--31. 1. "Reserved_9,Reserved_9" newline bitfld.long 0x0 8. "AA_EDGEOPT_OFF,Switches off the PBE-USE read optimisation during Anti aliasing mode. (This is typically for debug purposes only)" "0,1" newline hexmask.long.byte 0x0 0.--7. 1. "ALPHATHRESHOLD,Alpha threshold used when encoding 1555 format. If the internal 8bit Alpha value exceeds this value then a 1 is written to the top bit of the output otherwise a 0 is written" line.long 0x4 "RGX_CR_PBE_1,The PBE(Pixel back end) module scales and packs the pixel data before writing to memory. this register contains global control signals." hexmask.long 0x4 0.--31. 1. "Reserved_9,Reserved_9" rgroup.long 0x1508++0x7 line.long 0x0 "RGX_CR_PBE_EMIT_STATUS_0,This register indicates if the PixelBE would stall the USE if there were another emit. '0' indicates that the PixelBE would stall the USC. '1' indicates that the PixelBE would not stall the USE." hexmask.long.word 0x0 16.--31. 1. "Reserved_16,Reserved_16" newline bitfld.long 0x0 15. "USC15,Pipe 15 status" "0,1" newline bitfld.long 0x0 14. "USC14,Pipe 14 status" "0,1" newline bitfld.long 0x0 13. "USC13,Pipe 13 status" "0,1" newline bitfld.long 0x0 12. "USC12,Pipe 12 status" "0,1" newline bitfld.long 0x0 11. "USC11,Pipe 11 status" "0,1" newline bitfld.long 0x0 10. "USC10,Pipe 10 status" "0,1" newline bitfld.long 0x0 9. "USC9,Pipe 9 status" "0,1" newline bitfld.long 0x0 8. "USC8,Pipe 8 status" "0,1" newline bitfld.long 0x0 7. "USC7,Pipe 7 status" "0,1" newline bitfld.long 0x0 6. "USC6,Pipe 6 status" "0,1" newline bitfld.long 0x0 5. "USC5,Pipe 5 status" "0,1" newline bitfld.long 0x0 4. "USC4,Pipe 4 status" "0,1" newline bitfld.long 0x0 3. "USC3,Pipe 3 status" "0,1" newline bitfld.long 0x0 2. "USC2,Pipe 2 status" "0,1" newline bitfld.long 0x0 1. "USC1,Pipe 1 status" "0,1" newline bitfld.long 0x0 0. "USC0,Pipe 0 status" "0,1" line.long 0x4 "RGX_CR_PBE_EMIT_STATUS_1,This register indicates if the PixelBE would stall the USE if there were another emit. '0' indicates that the PixelBE would stall the USC. '1' indicates that the PixelBE would not stall the USE." hexmask.long 0x4 0.--31. 1. "Reserved_16,Reserved_16" group.long 0x1510++0x3F line.long 0x0 "RGX_CR_PBE_WORD0_MRT0_0,Pixel Back end State Word 0." bitfld.long 0x0 29.--31. "SWIZ_CHAN3,Swizzle for destination channel 3" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 26.--28. "SWIZ_CHAN2,Swizzle for destination channel 2" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 23.--25. "SWIZ_CHAN1,Swizzle for destination channel 1" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 20.--22. "SWIZ_CHAN0,Swizzle for destination channel 0" "0,1,2,3,4,5,6,7" newline hexmask.long.word 0x0 6.--19. 1. "MINCLIP_X,Min X Clip" newline bitfld.long 0x0 5. "TWOCOMP_GAMMA,Sets the gamma mode for 2 component targets" "0,1" newline bitfld.long 0x0 4. "GAMMA,Gamma enabled" "0,1" newline bitfld.long 0x0 3. "COMPRESSION,Frame buffer Compression enabled" "0,1" newline bitfld.long 0x0 2. "COMPRESS_SIZE,Block size for the compressor used with COMPRESS_SIZE_EXT register bit to define 8x8; 16x4 or 32x2 size COMPRESS_SIZE_EXT COMPRESS_SIZE SIZE 0 0 8x8 0 1 16x4 1 0 32x2 1 1 reserved" "0,1" newline bitfld.long 0x0 1. "COMP_INDIRECT_TABLE,If set indicates to the compressor that an indirect addressing is used otherwise direct addressing" "0,1" newline bitfld.long 0x0 0. "Y_FLIP,Y_FLIP" "0,1" line.long 0x4 "RGX_CR_PBE_WORD0_MRT0_1,Pixel Back end State Word 0." bitfld.long 0x4 30.--31. "X_RSRVD,Not used" "0,1,2,3" newline bitfld.long 0x4 29. "COMPRESS_SIZE_EXT,Extra bit to support 32x2 compression size used with COMPRESS_SIZE register bit to define 8x8; 16x4 or 32x2 size COMPRESS_SIZE_EXT COMPRESS_SIZE SIZE 0 0 8x8 0 1 16x4 1 0 32x2 1 1 reserved" "0,1" newline bitfld.long 0x4 28. "COMP_IADDR_MODE,FBC indirect addressing mode" "0,1" newline bitfld.long 0x4 27. "COMP_COR_ENABLE,Enable FBC correlation" "0,1" newline bitfld.long 0x4 26. "DITHER,Enable dither" "0,1" newline bitfld.long 0x4 25. "TILERELATIVE,Add tile offset" "0,1" newline bitfld.long 0x4 24. "DOWNSCALE,Perform box filter downscale" "0,1" newline hexmask.long.byte 0x4 20.--23. 1. "SIZE_Z,Z Size in pixels [log 2]" newline bitfld.long 0x4 18.--19. "ROTATION,Rotation angle" "0,1,2,3" newline hexmask.long.word 0x4 2.--17. 1. "LINESTRIDE,Linestride in 2 pixel units. 0 == 2. Supports 32KDWORD stride memory write" newline bitfld.long 0x4 0.--1. "MEMLAYOUT,Memory layout" "0,1,2,3" line.long 0x8 "RGX_CR_PBE_WORD0_MRT1_0,Pixel Back end State Word 0." bitfld.long 0x8 29.--31. "SWIZ_CHAN3,Swizzle for destination channel 3" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 26.--28. "SWIZ_CHAN2,Swizzle for destination channel 2" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 23.--25. "SWIZ_CHAN1,Swizzle for destination channel 1" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 20.--22. "SWIZ_CHAN0,Swizzle for destination channel 0" "0,1,2,3,4,5,6,7" newline hexmask.long.word 0x8 6.--19. 1. "MINCLIP_X,Min X Clip" newline bitfld.long 0x8 5. "TWOCOMP_GAMMA,Sets the gamma mode for 2 component targets" "0,1" newline bitfld.long 0x8 4. "GAMMA,Gamma enabled" "0,1" newline bitfld.long 0x8 3. "COMPRESSION,Frame buffer Compression enabled" "0,1" newline bitfld.long 0x8 2. "COMPRESS_SIZE,Block size for the compressor used with COMPRESS_SIZE_EXT register bit to define 8x8; 16x4 or 32x2 size COMPRESS_SIZE_EXT COMPRESS_SIZE SIZE 0 0 8x8 0 1 16x4 1 0 32x2 1 1 reserved" "0,1" newline bitfld.long 0x8 1. "COMP_INDIRECT_TABLE,If set indicates to the compressor that an indirect addressing is used otherwise direct addressing" "0,1" newline bitfld.long 0x8 0. "Y_FLIP,Y_FLIP" "0,1" line.long 0xC "RGX_CR_PBE_WORD0_MRT1_1,Pixel Back end State Word 0." bitfld.long 0xC 30.--31. "X_RSRVD,Not used" "0,1,2,3" newline bitfld.long 0xC 29. "COMPRESS_SIZE_EXT,Extra bit to support 32x2 compression size used with COMPRESS_SIZE register bit to define 8x8; 16x4 or 32x2 size COMPRESS_SIZE_EXT COMPRESS_SIZE SIZE 0 0 8x8 0 1 16x4 1 0 32x2 1 1 reserved" "0,1" newline bitfld.long 0xC 28. "COMP_IADDR_MODE,FBC indirect addressing mode" "0,1" newline bitfld.long 0xC 27. "COMP_COR_ENABLE,Enable FBC correlation" "0,1" newline bitfld.long 0xC 26. "DITHER,Enable dither" "0,1" newline bitfld.long 0xC 25. "TILERELATIVE,Add tile offset" "0,1" newline bitfld.long 0xC 24. "DOWNSCALE,Perform box filter downscale" "0,1" newline hexmask.long.byte 0xC 20.--23. 1. "SIZE_Z,Z Size in pixels [log 2]" newline bitfld.long 0xC 18.--19. "ROTATION,Rotation angle" "0,1,2,3" newline hexmask.long.word 0xC 2.--17. 1. "LINESTRIDE,Linestride in 2 pixel units. 0 == 2. Supports 32KDWORD stride memory write" newline bitfld.long 0xC 0.--1. "MEMLAYOUT,Memory layout" "0,1,2,3" line.long 0x10 "RGX_CR_PBE_WORD0_MRT2_0,Pixel Back end State Word 0." bitfld.long 0x10 29.--31. "SWIZ_CHAN3,Swizzle for destination channel 3" "0,1,2,3,4,5,6,7" newline bitfld.long 0x10 26.--28. "SWIZ_CHAN2,Swizzle for destination channel 2" "0,1,2,3,4,5,6,7" newline bitfld.long 0x10 23.--25. "SWIZ_CHAN1,Swizzle for destination channel 1" "0,1,2,3,4,5,6,7" newline bitfld.long 0x10 20.--22. "SWIZ_CHAN0,Swizzle for destination channel 0" "0,1,2,3,4,5,6,7" newline hexmask.long.word 0x10 6.--19. 1. "MINCLIP_X,Min X Clip" newline bitfld.long 0x10 5. "TWOCOMP_GAMMA,Sets the gamma mode for 2 component targets" "0,1" newline bitfld.long 0x10 4. "GAMMA,Gamma enabled" "0,1" newline bitfld.long 0x10 3. "COMPRESSION,Frame buffer Compression enabled" "0,1" newline bitfld.long 0x10 2. "COMPRESS_SIZE,Block size for the compressor used with COMPRESS_SIZE_EXT register bit to define 8x8; 16x4 or 32x2 size COMPRESS_SIZE_EXT COMPRESS_SIZE SIZE 0 0 8x8 0 1 16x4 1 0 32x2 1 1 reserved" "0,1" newline bitfld.long 0x10 1. "COMP_INDIRECT_TABLE,If set indicates to the compressor that an indirect addressing is used otherwise direct addressing" "0,1" newline bitfld.long 0x10 0. "Y_FLIP,Y_FLIP" "0,1" line.long 0x14 "RGX_CR_PBE_WORD0_MRT2_1,Pixel Back end State Word 0." bitfld.long 0x14 30.--31. "X_RSRVD,Not used" "0,1,2,3" newline bitfld.long 0x14 29. "COMPRESS_SIZE_EXT,Extra bit to support 32x2 compression size used with COMPRESS_SIZE register bit to define 8x8; 16x4 or 32x2 size COMPRESS_SIZE_EXT COMPRESS_SIZE SIZE 0 0 8x8 0 1 16x4 1 0 32x2 1 1 reserved" "0,1" newline bitfld.long 0x14 28. "COMP_IADDR_MODE,FBC indirect addressing mode" "0,1" newline bitfld.long 0x14 27. "COMP_COR_ENABLE,Enable FBC correlation" "0,1" newline bitfld.long 0x14 26. "DITHER,Enable dither" "0,1" newline bitfld.long 0x14 25. "TILERELATIVE,Add tile offset" "0,1" newline bitfld.long 0x14 24. "DOWNSCALE,Perform box filter downscale" "0,1" newline hexmask.long.byte 0x14 20.--23. 1. "SIZE_Z,Z Size in pixels [log 2]" newline bitfld.long 0x14 18.--19. "ROTATION,Rotation angle" "0,1,2,3" newline hexmask.long.word 0x14 2.--17. 1. "LINESTRIDE,Linestride in 2 pixel units. 0 == 2. Supports 32KDWORD stride memory write" newline bitfld.long 0x14 0.--1. "MEMLAYOUT,Memory layout" "0,1,2,3" line.long 0x18 "RGX_CR_PBE_WORD0_MRT3_0,Pixel Back end State Word 0." bitfld.long 0x18 29.--31. "SWIZ_CHAN3,Swizzle for destination channel 3" "0,1,2,3,4,5,6,7" newline bitfld.long 0x18 26.--28. "SWIZ_CHAN2,Swizzle for destination channel 2" "0,1,2,3,4,5,6,7" newline bitfld.long 0x18 23.--25. "SWIZ_CHAN1,Swizzle for destination channel 1" "0,1,2,3,4,5,6,7" newline bitfld.long 0x18 20.--22. "SWIZ_CHAN0,Swizzle for destination channel 0" "0,1,2,3,4,5,6,7" newline hexmask.long.word 0x18 6.--19. 1. "MINCLIP_X,Min X Clip" newline bitfld.long 0x18 5. "TWOCOMP_GAMMA,Sets the gamma mode for 2 component targets" "0,1" newline bitfld.long 0x18 4. "GAMMA,Gamma enabled" "0,1" newline bitfld.long 0x18 3. "COMPRESSION,Frame buffer Compression enabled" "0,1" newline bitfld.long 0x18 2. "COMPRESS_SIZE,Block size for the compressor used with COMPRESS_SIZE_EXT register bit to define 8x8; 16x4 or 32x2 size COMPRESS_SIZE_EXT COMPRESS_SIZE SIZE 0 0 8x8 0 1 16x4 1 0 32x2 1 1 reserved" "0,1" newline bitfld.long 0x18 1. "COMP_INDIRECT_TABLE,If set indicates to the compressor that an indirect addressing is used otherwise direct addressing" "0,1" newline bitfld.long 0x18 0. "Y_FLIP,Y_FLIP" "0,1" line.long 0x1C "RGX_CR_PBE_WORD0_MRT3_1,Pixel Back end State Word 0." bitfld.long 0x1C 30.--31. "X_RSRVD,Not used" "0,1,2,3" newline bitfld.long 0x1C 29. "COMPRESS_SIZE_EXT,Extra bit to support 32x2 compression size used with COMPRESS_SIZE register bit to define 8x8; 16x4 or 32x2 size COMPRESS_SIZE_EXT COMPRESS_SIZE SIZE 0 0 8x8 0 1 16x4 1 0 32x2 1 1 reserved" "0,1" newline bitfld.long 0x1C 28. "COMP_IADDR_MODE,FBC indirect addressing mode" "0,1" newline bitfld.long 0x1C 27. "COMP_COR_ENABLE,Enable FBC correlation" "0,1" newline bitfld.long 0x1C 26. "DITHER,Enable dither" "0,1" newline bitfld.long 0x1C 25. "TILERELATIVE,Add tile offset" "0,1" newline bitfld.long 0x1C 24. "DOWNSCALE,Perform box filter downscale" "0,1" newline hexmask.long.byte 0x1C 20.--23. 1. "SIZE_Z,Z Size in pixels [log 2]" newline bitfld.long 0x1C 18.--19. "ROTATION,Rotation angle" "0,1,2,3" newline hexmask.long.word 0x1C 2.--17. 1. "LINESTRIDE,Linestride in 2 pixel units. 0 == 2. Supports 32KDWORD stride memory write" newline bitfld.long 0x1C 0.--1. "MEMLAYOUT,Memory layout" "0,1,2,3" line.long 0x20 "RGX_CR_PBE_WORD0_MRT4_0,Pixel Back end State Word 0." bitfld.long 0x20 29.--31. "SWIZ_CHAN3,Swizzle for destination channel 3" "0,1,2,3,4,5,6,7" newline bitfld.long 0x20 26.--28. "SWIZ_CHAN2,Swizzle for destination channel 2" "0,1,2,3,4,5,6,7" newline bitfld.long 0x20 23.--25. "SWIZ_CHAN1,Swizzle for destination channel 1" "0,1,2,3,4,5,6,7" newline bitfld.long 0x20 20.--22. "SWIZ_CHAN0,Swizzle for destination channel 0" "0,1,2,3,4,5,6,7" newline hexmask.long.word 0x20 6.--19. 1. "MINCLIP_X,Min X Clip" newline bitfld.long 0x20 5. "TWOCOMP_GAMMA,Sets the gamma mode for 2 component targets" "0,1" newline bitfld.long 0x20 4. "GAMMA,Gamma enabled" "0,1" newline bitfld.long 0x20 3. "COMPRESSION,Frame buffer Compression enabled" "0,1" newline bitfld.long 0x20 2. "COMPRESS_SIZE,Block size for the compressor used with COMPRESS_SIZE_EXT register bit to define 8x8; 16x4 or 32x2 size COMPRESS_SIZE_EXT COMPRESS_SIZE SIZE 0 0 8x8 0 1 16x4 1 0 32x2 1 1 reserved" "0,1" newline bitfld.long 0x20 1. "COMP_INDIRECT_TABLE,If set indicates to the compressor that an indirect addressing is used otherwise direct addressing" "0,1" newline bitfld.long 0x20 0. "Y_FLIP,Y_FLIP" "0,1" line.long 0x24 "RGX_CR_PBE_WORD0_MRT4_1,Pixel Back end State Word 0." bitfld.long 0x24 30.--31. "X_RSRVD,Not used" "0,1,2,3" newline bitfld.long 0x24 29. "COMPRESS_SIZE_EXT,Extra bit to support 32x2 compression size used with COMPRESS_SIZE register bit to define 8x8; 16x4 or 32x2 size COMPRESS_SIZE_EXT COMPRESS_SIZE SIZE 0 0 8x8 0 1 16x4 1 0 32x2 1 1 reserved" "0,1" newline bitfld.long 0x24 28. "COMP_IADDR_MODE,FBC indirect addressing mode" "0,1" newline bitfld.long 0x24 27. "COMP_COR_ENABLE,Enable FBC correlation" "0,1" newline bitfld.long 0x24 26. "DITHER,Enable dither" "0,1" newline bitfld.long 0x24 25. "TILERELATIVE,Add tile offset" "0,1" newline bitfld.long 0x24 24. "DOWNSCALE,Perform box filter downscale" "0,1" newline hexmask.long.byte 0x24 20.--23. 1. "SIZE_Z,Z Size in pixels [log 2]" newline bitfld.long 0x24 18.--19. "ROTATION,Rotation angle" "0,1,2,3" newline hexmask.long.word 0x24 2.--17. 1. "LINESTRIDE,Linestride in 2 pixel units. 0 == 2. Supports 32KDWORD stride memory write" newline bitfld.long 0x24 0.--1. "MEMLAYOUT,Memory layout" "0,1,2,3" line.long 0x28 "RGX_CR_PBE_WORD0_MRT5_0,Pixel Back end State Word 0." bitfld.long 0x28 29.--31. "SWIZ_CHAN3,Swizzle for destination channel 3" "0,1,2,3,4,5,6,7" newline bitfld.long 0x28 26.--28. "SWIZ_CHAN2,Swizzle for destination channel 2" "0,1,2,3,4,5,6,7" newline bitfld.long 0x28 23.--25. "SWIZ_CHAN1,Swizzle for destination channel 1" "0,1,2,3,4,5,6,7" newline bitfld.long 0x28 20.--22. "SWIZ_CHAN0,Swizzle for destination channel 0" "0,1,2,3,4,5,6,7" newline hexmask.long.word 0x28 6.--19. 1. "MINCLIP_X,Min X Clip" newline bitfld.long 0x28 5. "TWOCOMP_GAMMA,Sets the gamma mode for 2 component targets" "0,1" newline bitfld.long 0x28 4. "GAMMA,Gamma enabled" "0,1" newline bitfld.long 0x28 3. "COMPRESSION,Frame buffer Compression enabled" "0,1" newline bitfld.long 0x28 2. "COMPRESS_SIZE,Block size for the compressor used with COMPRESS_SIZE_EXT register bit to define 8x8; 16x4 or 32x2 size COMPRESS_SIZE_EXT COMPRESS_SIZE SIZE 0 0 8x8 0 1 16x4 1 0 32x2 1 1 reserved" "0,1" newline bitfld.long 0x28 1. "COMP_INDIRECT_TABLE,If set indicates to the compressor that an indirect addressing is used otherwise direct addressing" "0,1" newline bitfld.long 0x28 0. "Y_FLIP,Y_FLIP" "0,1" line.long 0x2C "RGX_CR_PBE_WORD0_MRT5_1,Pixel Back end State Word 0." bitfld.long 0x2C 30.--31. "X_RSRVD,Not used" "0,1,2,3" newline bitfld.long 0x2C 29. "COMPRESS_SIZE_EXT,Extra bit to support 32x2 compression size used with COMPRESS_SIZE register bit to define 8x8; 16x4 or 32x2 size COMPRESS_SIZE_EXT COMPRESS_SIZE SIZE 0 0 8x8 0 1 16x4 1 0 32x2 1 1 reserved" "0,1" newline bitfld.long 0x2C 28. "COMP_IADDR_MODE,FBC indirect addressing mode" "0,1" newline bitfld.long 0x2C 27. "COMP_COR_ENABLE,Enable FBC correlation" "0,1" newline bitfld.long 0x2C 26. "DITHER,Enable dither" "0,1" newline bitfld.long 0x2C 25. "TILERELATIVE,Add tile offset" "0,1" newline bitfld.long 0x2C 24. "DOWNSCALE,Perform box filter downscale" "0,1" newline hexmask.long.byte 0x2C 20.--23. 1. "SIZE_Z,Z Size in pixels [log 2]" newline bitfld.long 0x2C 18.--19. "ROTATION,Rotation angle" "0,1,2,3" newline hexmask.long.word 0x2C 2.--17. 1. "LINESTRIDE,Linestride in 2 pixel units. 0 == 2. Supports 32KDWORD stride memory write" newline bitfld.long 0x2C 0.--1. "MEMLAYOUT,Memory layout" "0,1,2,3" line.long 0x30 "RGX_CR_PBE_WORD0_MRT6_0,Pixel Back end State Word 0." bitfld.long 0x30 29.--31. "SWIZ_CHAN3,Swizzle for destination channel 3" "0,1,2,3,4,5,6,7" newline bitfld.long 0x30 26.--28. "SWIZ_CHAN2,Swizzle for destination channel 2" "0,1,2,3,4,5,6,7" newline bitfld.long 0x30 23.--25. "SWIZ_CHAN1,Swizzle for destination channel 1" "0,1,2,3,4,5,6,7" newline bitfld.long 0x30 20.--22. "SWIZ_CHAN0,Swizzle for destination channel 0" "0,1,2,3,4,5,6,7" newline hexmask.long.word 0x30 6.--19. 1. "MINCLIP_X,Min X Clip" newline bitfld.long 0x30 5. "TWOCOMP_GAMMA,Sets the gamma mode for 2 component targets" "0,1" newline bitfld.long 0x30 4. "GAMMA,Gamma enabled" "0,1" newline bitfld.long 0x30 3. "COMPRESSION,Frame buffer Compression enabled" "0,1" newline bitfld.long 0x30 2. "COMPRESS_SIZE,Block size for the compressor used with COMPRESS_SIZE_EXT register bit to define 8x8; 16x4 or 32x2 size COMPRESS_SIZE_EXT COMPRESS_SIZE SIZE 0 0 8x8 0 1 16x4 1 0 32x2 1 1 reserved" "0,1" newline bitfld.long 0x30 1. "COMP_INDIRECT_TABLE,If set indicates to the compressor that an indirect addressing is used otherwise direct addressing" "0,1" newline bitfld.long 0x30 0. "Y_FLIP,Y_FLIP" "0,1" line.long 0x34 "RGX_CR_PBE_WORD0_MRT6_1,Pixel Back end State Word 0." bitfld.long 0x34 30.--31. "X_RSRVD,Not used" "0,1,2,3" newline bitfld.long 0x34 29. "COMPRESS_SIZE_EXT,Extra bit to support 32x2 compression size used with COMPRESS_SIZE register bit to define 8x8; 16x4 or 32x2 size COMPRESS_SIZE_EXT COMPRESS_SIZE SIZE 0 0 8x8 0 1 16x4 1 0 32x2 1 1 reserved" "0,1" newline bitfld.long 0x34 28. "COMP_IADDR_MODE,FBC indirect addressing mode" "0,1" newline bitfld.long 0x34 27. "COMP_COR_ENABLE,Enable FBC correlation" "0,1" newline bitfld.long 0x34 26. "DITHER,Enable dither" "0,1" newline bitfld.long 0x34 25. "TILERELATIVE,Add tile offset" "0,1" newline bitfld.long 0x34 24. "DOWNSCALE,Perform box filter downscale" "0,1" newline hexmask.long.byte 0x34 20.--23. 1. "SIZE_Z,Z Size in pixels [log 2]" newline bitfld.long 0x34 18.--19. "ROTATION,Rotation angle" "0,1,2,3" newline hexmask.long.word 0x34 2.--17. 1. "LINESTRIDE,Linestride in 2 pixel units. 0 == 2. Supports 32KDWORD stride memory write" newline bitfld.long 0x34 0.--1. "MEMLAYOUT,Memory layout" "0,1,2,3" line.long 0x38 "RGX_CR_PBE_WORD0_MRT7_0,Pixel Back end State Word 0." bitfld.long 0x38 29.--31. "SWIZ_CHAN3,Swizzle for destination channel 3" "0,1,2,3,4,5,6,7" newline bitfld.long 0x38 26.--28. "SWIZ_CHAN2,Swizzle for destination channel 2" "0,1,2,3,4,5,6,7" newline bitfld.long 0x38 23.--25. "SWIZ_CHAN1,Swizzle for destination channel 1" "0,1,2,3,4,5,6,7" newline bitfld.long 0x38 20.--22. "SWIZ_CHAN0,Swizzle for destination channel 0" "0,1,2,3,4,5,6,7" newline hexmask.long.word 0x38 6.--19. 1. "MINCLIP_X,Min X Clip" newline bitfld.long 0x38 5. "TWOCOMP_GAMMA,Sets the gamma mode for 2 component targets" "0,1" newline bitfld.long 0x38 4. "GAMMA,Gamma enabled" "0,1" newline bitfld.long 0x38 3. "COMPRESSION,Frame buffer Compression enabled" "0,1" newline bitfld.long 0x38 2. "COMPRESS_SIZE,Block size for the compressor used with COMPRESS_SIZE_EXT register bit to define 8x8; 16x4 or 32x2 size COMPRESS_SIZE_EXT COMPRESS_SIZE SIZE 0 0 8x8 0 1 16x4 1 0 32x2 1 1 reserved" "0,1" newline bitfld.long 0x38 1. "COMP_INDIRECT_TABLE,If set indicates to the compressor that an indirect addressing is used otherwise direct addressing" "0,1" newline bitfld.long 0x38 0. "Y_FLIP,Y_FLIP" "0,1" line.long 0x3C "RGX_CR_PBE_WORD0_MRT7_1,Pixel Back end State Word 0." bitfld.long 0x3C 30.--31. "X_RSRVD,Not used" "0,1,2,3" newline bitfld.long 0x3C 29. "COMPRESS_SIZE_EXT,Extra bit to support 32x2 compression size used with COMPRESS_SIZE register bit to define 8x8; 16x4 or 32x2 size COMPRESS_SIZE_EXT COMPRESS_SIZE SIZE 0 0 8x8 0 1 16x4 1 0 32x2 1 1 reserved" "0,1" newline bitfld.long 0x3C 28. "COMP_IADDR_MODE,FBC indirect addressing mode" "0,1" newline bitfld.long 0x3C 27. "COMP_COR_ENABLE,Enable FBC correlation" "0,1" newline bitfld.long 0x3C 26. "DITHER,Enable dither" "0,1" newline bitfld.long 0x3C 25. "TILERELATIVE,Add tile offset" "0,1" newline bitfld.long 0x3C 24. "DOWNSCALE,Perform box filter downscale" "0,1" newline hexmask.long.byte 0x3C 20.--23. 1. "SIZE_Z,Z Size in pixels [log 2]" newline bitfld.long 0x3C 18.--19. "ROTATION,Rotation angle" "0,1,2,3" newline hexmask.long.word 0x3C 2.--17. 1. "LINESTRIDE,Linestride in 2 pixel units. 0 == 2. Supports 32KDWORD stride memory write" newline bitfld.long 0x3C 0.--1. "MEMLAYOUT,Memory layout" "0,1,2,3" repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) group.long ($2+0x1550)++0x3 line.long 0x0 "RGX_CR_PBE_WORD1_MRT0_$1,Pixel Back end State Word 1." hexmask.long.byte 0x0 28.--31. 1. "SIZE_Y,Y Size in pixels [log 2]" newline hexmask.long.word 0x0 14.--27. 1. "ZSLICE,Slice number for render to 3D twiddle target" newline hexmask.long.word 0x0 0.--13. 1. "MAXCLIP_Y,Max Y clip" repeat.end repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) group.long ($2+0x1558)++0x3 line.long 0x0 "RGX_CR_PBE_WORD1_MRT1_$1,Pixel Back end State Word 1." hexmask.long.byte 0x0 28.--31. 1. "SIZE_Y,Y Size in pixels [log 2]" newline hexmask.long.word 0x0 14.--27. 1. "ZSLICE,Slice number for render to 3D twiddle target" newline hexmask.long.word 0x0 0.--13. 1. "MAXCLIP_Y,Max Y clip" repeat.end repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) group.long ($2+0x1560)++0x3 line.long 0x0 "RGX_CR_PBE_WORD1_MRT2_$1,Pixel Back end State Word 1." hexmask.long.byte 0x0 28.--31. 1. "SIZE_Y,Y Size in pixels [log 2]" newline hexmask.long.word 0x0 14.--27. 1. "ZSLICE,Slice number for render to 3D twiddle target" newline hexmask.long.word 0x0 0.--13. 1. "MAXCLIP_Y,Max Y clip" repeat.end repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) group.long ($2+0x1568)++0x3 line.long 0x0 "RGX_CR_PBE_WORD1_MRT3_$1,Pixel Back end State Word 1." hexmask.long.byte 0x0 28.--31. 1. "SIZE_Y,Y Size in pixels [log 2]" newline hexmask.long.word 0x0 14.--27. 1. "ZSLICE,Slice number for render to 3D twiddle target" newline hexmask.long.word 0x0 0.--13. 1. "MAXCLIP_Y,Max Y clip" repeat.end repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) group.long ($2+0x1570)++0x3 line.long 0x0 "RGX_CR_PBE_WORD1_MRT4_$1,Pixel Back end State Word 1." hexmask.long.byte 0x0 28.--31. 1. "SIZE_Y,Y Size in pixels [log 2]" newline hexmask.long.word 0x0 14.--27. 1. "ZSLICE,Slice number for render to 3D twiddle target" newline hexmask.long.word 0x0 0.--13. 1. "MAXCLIP_Y,Max Y clip" repeat.end repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) group.long ($2+0x1578)++0x3 line.long 0x0 "RGX_CR_PBE_WORD1_MRT5_$1,Pixel Back end State Word 1." hexmask.long.byte 0x0 28.--31. 1. "SIZE_Y,Y Size in pixels [log 2]" newline hexmask.long.word 0x0 14.--27. 1. "ZSLICE,Slice number for render to 3D twiddle target" newline hexmask.long.word 0x0 0.--13. 1. "MAXCLIP_Y,Max Y clip" repeat.end repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) group.long ($2+0x1580)++0x3 line.long 0x0 "RGX_CR_PBE_WORD1_MRT6_$1,Pixel Back end State Word 1." hexmask.long.byte 0x0 28.--31. 1. "SIZE_Y,Y Size in pixels [log 2]" newline hexmask.long.word 0x0 14.--27. 1. "ZSLICE,Slice number for render to 3D twiddle target" newline hexmask.long.word 0x0 0.--13. 1. "MAXCLIP_Y,Max Y clip" repeat.end repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) group.long ($2+0x1588)++0x3 line.long 0x0 "RGX_CR_PBE_WORD1_MRT7_$1,Pixel Back end State Word 1." hexmask.long.byte 0x0 28.--31. 1. "SIZE_Y,Y Size in pixels [log 2]" newline hexmask.long.word 0x0 14.--27. 1. "ZSLICE,Slice number for render to 3D twiddle target" newline hexmask.long.word 0x0 0.--13. 1. "MAXCLIP_Y,Max Y clip" repeat.end repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) rgroup.long ($2+0x1590)++0x3 line.long 0x0 "RGX_CR_PBE_PWR_$1,Power monitoring register" hexmask.long 0x0 0.--31. 1. "NUM_PIXELS_PROCESSED,Number of on-edge/off-edge pixels per tile." repeat.end group.long 0x15A0++0x3F line.long 0x0 "RGX_CR_PBE_WORD2_MRT0_0,Pixel Back end State Word 2." hexmask.long 0x0 0.--31. 1. "SW_BYTEMASK,SW driven mask" line.long 0x4 "RGX_CR_PBE_WORD2_MRT0_1,Pixel Back end State Word 2." hexmask.long.tbyte 0x4 15.--31. 1. "Reserved_47,Reserved_47" newline bitfld.long 0x4 14. "PAIR_TILES,If set then PBE will pair 16x16 tiles" "0,1" newline hexmask.long.word 0x4 0.--13. 1. "SURFACE_Y_SIZE,Y Size in pixels (only used for strided memory layout with FBC)" line.long 0x8 "RGX_CR_PBE_WORD2_MRT1_0,Pixel Back end State Word 2." hexmask.long 0x8 0.--31. 1. "SW_BYTEMASK,SW driven mask" line.long 0xC "RGX_CR_PBE_WORD2_MRT1_1,Pixel Back end State Word 2." hexmask.long.tbyte 0xC 15.--31. 1. "Reserved_47,Reserved_47" newline bitfld.long 0xC 14. "PAIR_TILES,If set then PBE will pair 16x16 tiles" "0,1" newline hexmask.long.word 0xC 0.--13. 1. "SURFACE_Y_SIZE,Y Size in pixels (only used for strided memory layout with FBC)" line.long 0x10 "RGX_CR_PBE_WORD2_MRT2_0,Pixel Back end State Word 2." hexmask.long 0x10 0.--31. 1. "SW_BYTEMASK,SW driven mask" line.long 0x14 "RGX_CR_PBE_WORD2_MRT2_1,Pixel Back end State Word 2." hexmask.long.tbyte 0x14 15.--31. 1. "Reserved_47,Reserved_47" newline bitfld.long 0x14 14. "PAIR_TILES,If set then PBE will pair 16x16 tiles" "0,1" newline hexmask.long.word 0x14 0.--13. 1. "SURFACE_Y_SIZE,Y Size in pixels (only used for strided memory layout with FBC)" line.long 0x18 "RGX_CR_PBE_WORD2_MRT3_0,Pixel Back end State Word 2." hexmask.long 0x18 0.--31. 1. "SW_BYTEMASK,SW driven mask" line.long 0x1C "RGX_CR_PBE_WORD2_MRT3_1,Pixel Back end State Word 2." hexmask.long.tbyte 0x1C 15.--31. 1. "Reserved_47,Reserved_47" newline bitfld.long 0x1C 14. "PAIR_TILES,If set then PBE will pair 16x16 tiles" "0,1" newline hexmask.long.word 0x1C 0.--13. 1. "SURFACE_Y_SIZE,Y Size in pixels (only used for strided memory layout with FBC)" line.long 0x20 "RGX_CR_PBE_WORD2_MRT4_0,Pixel Back end State Word 2." hexmask.long 0x20 0.--31. 1. "SW_BYTEMASK,SW driven mask" line.long 0x24 "RGX_CR_PBE_WORD2_MRT4_1,Pixel Back end State Word 2." hexmask.long.tbyte 0x24 15.--31. 1. "Reserved_47,Reserved_47" newline bitfld.long 0x24 14. "PAIR_TILES,If set then PBE will pair 16x16 tiles" "0,1" newline hexmask.long.word 0x24 0.--13. 1. "SURFACE_Y_SIZE,Y Size in pixels (only used for strided memory layout with FBC)" line.long 0x28 "RGX_CR_PBE_WORD2_MRT5_0,Pixel Back end State Word 2." hexmask.long 0x28 0.--31. 1. "SW_BYTEMASK,SW driven mask" line.long 0x2C "RGX_CR_PBE_WORD2_MRT5_1,Pixel Back end State Word 2." hexmask.long.tbyte 0x2C 15.--31. 1. "Reserved_47,Reserved_47" newline bitfld.long 0x2C 14. "PAIR_TILES,If set then PBE will pair 16x16 tiles" "0,1" newline hexmask.long.word 0x2C 0.--13. 1. "SURFACE_Y_SIZE,Y Size in pixels (only used for strided memory layout with FBC)" line.long 0x30 "RGX_CR_PBE_WORD2_MRT6_0,Pixel Back end State Word 2." hexmask.long 0x30 0.--31. 1. "SW_BYTEMASK,SW driven mask" line.long 0x34 "RGX_CR_PBE_WORD2_MRT6_1,Pixel Back end State Word 2." hexmask.long.tbyte 0x34 15.--31. 1. "Reserved_47,Reserved_47" newline bitfld.long 0x34 14. "PAIR_TILES,If set then PBE will pair 16x16 tiles" "0,1" newline hexmask.long.word 0x34 0.--13. 1. "SURFACE_Y_SIZE,Y Size in pixels (only used for strided memory layout with FBC)" line.long 0x38 "RGX_CR_PBE_WORD2_MRT7_0,Pixel Back end State Word 2." hexmask.long 0x38 0.--31. 1. "SW_BYTEMASK,SW driven mask" line.long 0x3C "RGX_CR_PBE_WORD2_MRT7_1,Pixel Back end State Word 2." hexmask.long.tbyte 0x3C 15.--31. 1. "Reserved_47,Reserved_47" newline bitfld.long 0x3C 14. "PAIR_TILES,If set then PBE will pair 16x16 tiles" "0,1" newline hexmask.long.word 0x3C 0.--13. 1. "SURFACE_Y_SIZE,Y Size in pixels (only used for strided memory layout with FBC)" group.long 0x1600++0x11F line.long 0x0 "RGX_CR_FB_CDC_0,Framebuffer Compression/Decompression arbiter modes" bitfld.long 0x0 30.--31. "FBDC_MCU_SLC_HDR_POLICY,SLC Cache policy for MCU requested FBDC header requests" "0,1,2,3" newline bitfld.long 0x0 28.--29. "FBDC_MCU_SLC_DATA_POLICY,SLC Cache policy for MCU requested FBDC tile data requests" "0,1,2,3" newline hexmask.long.word 0x0 12.--27. 1. "FBC_FBDC_COMPATIBILITY,The register defines the mode of operation to ensure that the GPU FBC/FBDC is compatible with any FBC/FBDC existing in the SoC (standalone FBC/FBDC). To be compatible the register needs to be programed with the version of the SoC.." newline bitfld.long 0x0 11. "FBC_FBDC_INVAL_OVERRIDE,When set then all FBDC header cache entries will be invalidate from the FBC otherwise only those associated with the request being processed by the FBC will be invalidated" "0,1" newline bitfld.long 0x0 10. "ZLS_SLC_NOLINEFILL,ZLS write SLC no line fill: 0=line fill on miss 1=no line fill on miss" "line fill on miss,no line fill on miss" newline bitfld.long 0x0 8.--9. "ZLS_SLC_POLICY,ZLS write SLC cache Policy" "0,1,2,3" newline bitfld.long 0x0 7. "PBE_SLC_NOLINEFILL,PBE write SLC no line fill: 0=line fill on miss 1=no line fill on miss" "line fill on miss,no line fill on miss" newline bitfld.long 0x0 5.--6. "PBE_SLC_POLICY,PBE write SLC cache Policy" "0,1,2,3" newline bitfld.long 0x0 4. "PBE_COR_COLOUR_ENABLE,PBE Enable correlation/decorrelation for PBE 0=disbaled 1=enabled" "disbaled,enabled" newline bitfld.long 0x0 3. "FBC_ARB_MODE,FBC Request Arbiter Mode 0 = Re-arbitrate after tile 1 = Re-arbitrate after valid drop and tile complete" "Re-arbitrate after tile,Re-arbitrate after valid drop and tile complete" newline bitfld.long 0x0 2. "Reserved_2,Reserved_2" "0,1" newline bitfld.long 0x0 1. "TLDECODE_ARB_MODE,TLCache Request Arbiter Mode Rearbitration:0 = valid dropped and burst complete 1 = After burst complete" "valid dropped and burst complete,After burst complete" newline bitfld.long 0x0 0. "BIF_ARB_MODE,FBC and FBDC BIF Arbiter Mode 0 = Re-arbitrate after burst 1 = Re-arbitrate after valid drop and burst complete" "Re-arbitrate after burst,Re-arbitrate after valid drop and burst complete" line.long 0x4 "RGX_CR_FB_CDC_1,Framebuffer Compression/Decompression arbiter modes" hexmask.long.tbyte 0x4 13.--31. 1. "Reserved_45,Reserved_45" newline bitfld.long 0x4 12. "FBCDC_COR_ENABLE,writing '0' the compression correlation/decorrelation is disable" "0,1" newline hexmask.long.byte 0x4 4.--11. 1. "Reserved_36,Reserved_36" newline bitfld.long 0x4 2.--3. "FBDC_ZLS_SLC_HDR_POLICY,SLC Cache policy for ZLS requested FBDC header requests" "0,1,2,3" newline bitfld.long 0x4 0.--1. "FBDC_ZLS_SLC_DATA_POLICY,SLC Cache policy for ZLS requested FBDC tile data requests" "0,1,2,3" line.long 0x8 "RGX_CR_FB_ICTRL_0,Framebuffer Invalidates" hexmask.long.word 0x8 23.--31. 1. "Reserved_23,Reserved_23" newline bitfld.long 0x8 22. "TLCACHE_INVALFLUSH_FASTRENDER_DM,When set to 1 all entries in the tile cache that have been tagged as a fastrender data master will be invalidate/flush when TLCACHE_INVALFLUSH_PENDING is set" "0,1" newline bitfld.long 0x8 19.--21. "Reserved_19,Reserved_19" "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x8 15.--18. 1. "FBDC_INVALIDATE_REQUESTER,Bit mask of requester to invalidate when FBDC_INVALIDATE_PENDING is set" newline bitfld.long 0x8 14. "TLCACHE_INVALFLUSH_TOMEM,When set to 1 all flushes will result in a flush fence being sent to memory after the tiles have been flushed. On return of this fence the TLCACHE_INVALFLUSH_PENDING will be cleared. When not set a flush fence is not sent and.." "0,1" newline hexmask.long.byte 0x8 10.--13. 1. "TLCACHE_INVALFLUSH_REQUESTER,Bit mask of requester to flush or invalidate when TLCACHE_INVALFUSH_PENDING is set These are also used in combination with the invalflush__DM mask bits" newline bitfld.long 0x8 8.--9. "Reserved_8,Reserved_8" "0,1,2,3" newline bitfld.long 0x8 7. "TLCACHE_INVALFLUSH_COMP_DM,When set to 1 all entries in the tile cache that have been tagged as a compute data master will be invalidate/flush when TLCACHE_INVALFLUSH_PENDING is set" "0,1" newline bitfld.long 0x8 6. "TLCACHE_INVALFLUSH_VERTEX_DM,When set to 1 all entries in the tile cache that have been tagged as a vertex data master will be invalidate/flush when TLCACHE_INVALFLUSH_PENDING is set" "0,1" newline bitfld.long 0x8 5. "TLCACHE_INVALFLUSH_PIXEL_DM,When set to 1 all entries in the tile cache that have been tagged as a pixel data master will be invalidate/flush when TLCACHE_INVALFLUSH_PENDING is set" "0,1" newline bitfld.long 0x8 3.--4. "TLCACHE_INVALFLUSH_PENDING,The cache may be requested to flush or invalidate or both in a single write access. Each bit when read returns the current status of the flush or invalidate request. Bit 0 = Invalidate Bit 1 = Flush If either bit is read back.." "Invalidate,Flush,?,?" newline bitfld.long 0x8 1.--2. "Reserved_1,Reserved_1" "0,1,2,3" newline bitfld.long 0x8 0. "FBDC_INVALIDATE_PENDING,When written to 1 will invalidate the header cache in the FBDC when read as 1 invalidate is in progress when read as 0 invalidate is complete" "0,1" line.long 0xC "RGX_CR_FB_ICTRL_1,Framebuffer Invalidates" hexmask.long 0xC 0.--31. 1. "Reserved_23,Reserved_23" line.long 0x10 "RGX_CR_FB_MEM_REGION0_0,Framebuffer Compression/Decompression memory regions for Host and TLA accesses" hexmask.long 0x10 0.--31. 1. "BASE_ADDRESS,Base address of this memory region in 512bit granularity" line.long 0x14 "RGX_CR_FB_MEM_REGION0_1,Framebuffer Compression/Decompression memory regions for Host and TLA accesses" hexmask.long.byte 0x14 25.--31. 1. "Reserved_57,Reserved_57" newline hexmask.long.tbyte 0x14 2.--24. 1. "NUM_TILES,The number of compressor tiles to be used in this memory region" newline bitfld.long 0x14 0.--1. "BASE_ADDRESS,Base address of this memory region in 512bit granularity" "0,1,2,3" line.long 0x18 "RGX_CR_FB_MEM_REGION1_0,Framebuffer Compression/Decompression memory regions for Host and TLA accesses" hexmask.long 0x18 0.--31. 1. "BASE_ADDRESS,Base address of this memory region in 512bit granularity" line.long 0x1C "RGX_CR_FB_MEM_REGION1_1,Framebuffer Compression/Decompression memory regions for Host and TLA accesses" hexmask.long.byte 0x1C 25.--31. 1. "Reserved_57,Reserved_57" newline hexmask.long.tbyte 0x1C 2.--24. 1. "NUM_TILES,The number of compressor tiles to be used in this memory region" newline bitfld.long 0x1C 0.--1. "BASE_ADDRESS,Base address of this memory region in 512bit granularity" "0,1,2,3" line.long 0x20 "RGX_CR_FB_MEM_REGION2_0,Framebuffer Compression/Decompression memory regions for Host and TLA accesses" hexmask.long 0x20 0.--31. 1. "BASE_ADDRESS,Base address of this memory region in 512bit granularity" line.long 0x24 "RGX_CR_FB_MEM_REGION2_1,Framebuffer Compression/Decompression memory regions for Host and TLA accesses" hexmask.long.byte 0x24 25.--31. 1. "Reserved_57,Reserved_57" newline hexmask.long.tbyte 0x24 2.--24. 1. "NUM_TILES,The number of compressor tiles to be used in this memory region" newline bitfld.long 0x24 0.--1. "BASE_ADDRESS,Base address of this memory region in 512bit granularity" "0,1,2,3" line.long 0x28 "RGX_CR_FB_MEM_REGION3_0,Framebuffer Compression/Decompression memory regions for Host and TLA accesses" hexmask.long 0x28 0.--31. 1. "BASE_ADDRESS,Base address of this memory region in 512bit granularity" line.long 0x2C "RGX_CR_FB_MEM_REGION3_1,Framebuffer Compression/Decompression memory regions for Host and TLA accesses" hexmask.long.byte 0x2C 25.--31. 1. "Reserved_57,Reserved_57" newline hexmask.long.tbyte 0x2C 2.--24. 1. "NUM_TILES,The number of compressor tiles to be used in this memory region" newline bitfld.long 0x2C 0.--1. "BASE_ADDRESS,Base address of this memory region in 512bit granularity" "0,1,2,3" line.long 0x30 "RGX_CR_FB_MEM_REGION4_0,Framebuffer Compression/Decompression memory regions for Host and TLA accesses" hexmask.long 0x30 0.--31. 1. "BASE_ADDRESS,Base address of this memory region in 512bit granularity" line.long 0x34 "RGX_CR_FB_MEM_REGION4_1,Framebuffer Compression/Decompression memory regions for Host and TLA accesses" hexmask.long.byte 0x34 25.--31. 1. "Reserved_57,Reserved_57" newline hexmask.long.tbyte 0x34 2.--24. 1. "NUM_TILES,The number of compressor tiles to be used in this memory region" newline bitfld.long 0x34 0.--1. "BASE_ADDRESS,Base address of this memory region in 512bit granularity" "0,1,2,3" line.long 0x38 "RGX_CR_FB_MEM_REGION5_0,Framebuffer Compression/Decompression memory regions for Host and TLA accesses" hexmask.long 0x38 0.--31. 1. "BASE_ADDRESS,Base address of this memory region in 512bit granularity" line.long 0x3C "RGX_CR_FB_MEM_REGION5_1,Framebuffer Compression/Decompression memory regions for Host and TLA accesses" hexmask.long.byte 0x3C 25.--31. 1. "Reserved_57,Reserved_57" newline hexmask.long.tbyte 0x3C 2.--24. 1. "NUM_TILES,The number of compressor tiles to be used in this memory region" newline bitfld.long 0x3C 0.--1. "BASE_ADDRESS,Base address of this memory region in 512bit granularity" "0,1,2,3" line.long 0x40 "RGX_CR_FB_MEM_REGION6_0,Framebuffer Compression/Decompression memory regions for Host and TLA accesses" hexmask.long 0x40 0.--31. 1. "BASE_ADDRESS,Base address of this memory region in 512bit granularity" line.long 0x44 "RGX_CR_FB_MEM_REGION6_1,Framebuffer Compression/Decompression memory regions for Host and TLA accesses" hexmask.long.byte 0x44 25.--31. 1. "Reserved_57,Reserved_57" newline hexmask.long.tbyte 0x44 2.--24. 1. "NUM_TILES,The number of compressor tiles to be used in this memory region" newline bitfld.long 0x44 0.--1. "BASE_ADDRESS,Base address of this memory region in 512bit granularity" "0,1,2,3" line.long 0x48 "RGX_CR_FB_MEM_REGION7_0,Framebuffer Compression/Decompression memory regions for Host and TLA accesses" hexmask.long 0x48 0.--31. 1. "BASE_ADDRESS,Base address of this memory region in 512bit granularity" line.long 0x4C "RGX_CR_FB_MEM_REGION7_1,Framebuffer Compression/Decompression memory regions for Host and TLA accesses" hexmask.long.byte 0x4C 25.--31. 1. "Reserved_57,Reserved_57" newline hexmask.long.tbyte 0x4C 2.--24. 1. "NUM_TILES,The number of compressor tiles to be used in this memory region" newline bitfld.long 0x4C 0.--1. "BASE_ADDRESS,Base address of this memory region in 512bit granularity" "0,1,2,3" line.long 0x50 "RGX_CR_FB_MEM_REGION8_0,Framebuffer Compression/Decompression memory regions for Host and TLA accesses" hexmask.long 0x50 0.--31. 1. "BASE_ADDRESS,Base address of this memory region in 512bit granularity" line.long 0x54 "RGX_CR_FB_MEM_REGION8_1,Framebuffer Compression/Decompression memory regions for Host and TLA accesses" hexmask.long.byte 0x54 25.--31. 1. "Reserved_57,Reserved_57" newline hexmask.long.tbyte 0x54 2.--24. 1. "NUM_TILES,The number of compressor tiles to be used in this memory region" newline bitfld.long 0x54 0.--1. "BASE_ADDRESS,Base address of this memory region in 512bit granularity" "0,1,2,3" line.long 0x58 "RGX_CR_FB_MEM_REGION9_0,Framebuffer Compression/Decompression memory regions for Host and TLA accesses" hexmask.long 0x58 0.--31. 1. "BASE_ADDRESS,Base address of this memory region in 512bit granularity" line.long 0x5C "RGX_CR_FB_MEM_REGION9_1,Framebuffer Compression/Decompression memory regions for Host and TLA accesses" hexmask.long.byte 0x5C 25.--31. 1. "Reserved_57,Reserved_57" newline hexmask.long.tbyte 0x5C 2.--24. 1. "NUM_TILES,The number of compressor tiles to be used in this memory region" newline bitfld.long 0x5C 0.--1. "BASE_ADDRESS,Base address of this memory region in 512bit granularity" "0,1,2,3" line.long 0x60 "RGX_CR_FB_MEM_REGION10_0,Framebuffer Compression/Decompression memory regions for Host and TLA accesses" hexmask.long 0x60 0.--31. 1. "BASE_ADDRESS,Base address of this memory region in 512bit granularity" line.long 0x64 "RGX_CR_FB_MEM_REGION10_1,Framebuffer Compression/Decompression memory regions for Host and TLA accesses" hexmask.long.byte 0x64 25.--31. 1. "Reserved_57,Reserved_57" newline hexmask.long.tbyte 0x64 2.--24. 1. "NUM_TILES,The number of compressor tiles to be used in this memory region" newline bitfld.long 0x64 0.--1. "BASE_ADDRESS,Base address of this memory region in 512bit granularity" "0,1,2,3" line.long 0x68 "RGX_CR_FB_MEM_REGION11_0,Framebuffer Compression/Decompression memory regions for Host and TLA accesses" hexmask.long 0x68 0.--31. 1. "BASE_ADDRESS,Base address of this memory region in 512bit granularity" line.long 0x6C "RGX_CR_FB_MEM_REGION11_1,Framebuffer Compression/Decompression memory regions for Host and TLA accesses" hexmask.long.byte 0x6C 25.--31. 1. "Reserved_57,Reserved_57" newline hexmask.long.tbyte 0x6C 2.--24. 1. "NUM_TILES,The number of compressor tiles to be used in this memory region" newline bitfld.long 0x6C 0.--1. "BASE_ADDRESS,Base address of this memory region in 512bit granularity" "0,1,2,3" line.long 0x70 "RGX_CR_FB_MEM_REGION12_0,Framebuffer Compression/Decompression memory regions for Host and TLA accesses" hexmask.long 0x70 0.--31. 1. "BASE_ADDRESS,Base address of this memory region in 512bit granularity" line.long 0x74 "RGX_CR_FB_MEM_REGION12_1,Framebuffer Compression/Decompression memory regions for Host and TLA accesses" hexmask.long.byte 0x74 25.--31. 1. "Reserved_57,Reserved_57" newline hexmask.long.tbyte 0x74 2.--24. 1. "NUM_TILES,The number of compressor tiles to be used in this memory region" newline bitfld.long 0x74 0.--1. "BASE_ADDRESS,Base address of this memory region in 512bit granularity" "0,1,2,3" line.long 0x78 "RGX_CR_FB_MEM_REGION13_0,Framebuffer Compression/Decompression memory regions for Host and TLA accesses" hexmask.long 0x78 0.--31. 1. "BASE_ADDRESS,Base address of this memory region in 512bit granularity" line.long 0x7C "RGX_CR_FB_MEM_REGION13_1,Framebuffer Compression/Decompression memory regions for Host and TLA accesses" hexmask.long.byte 0x7C 25.--31. 1. "Reserved_57,Reserved_57" newline hexmask.long.tbyte 0x7C 2.--24. 1. "NUM_TILES,The number of compressor tiles to be used in this memory region" newline bitfld.long 0x7C 0.--1. "BASE_ADDRESS,Base address of this memory region in 512bit granularity" "0,1,2,3" line.long 0x80 "RGX_CR_FB_MEM_REGION14_0,Framebuffer Compression/Decompression memory regions for Host and TLA accesses" hexmask.long 0x80 0.--31. 1. "BASE_ADDRESS,Base address of this memory region in 512bit granularity" line.long 0x84 "RGX_CR_FB_MEM_REGION14_1,Framebuffer Compression/Decompression memory regions for Host and TLA accesses" hexmask.long.byte 0x84 25.--31. 1. "Reserved_57,Reserved_57" newline hexmask.long.tbyte 0x84 2.--24. 1. "NUM_TILES,The number of compressor tiles to be used in this memory region" newline bitfld.long 0x84 0.--1. "BASE_ADDRESS,Base address of this memory region in 512bit granularity" "0,1,2,3" line.long 0x88 "RGX_CR_FB_MEM_REGION15_0,Framebuffer Compression/Decompression memory regions for Host and TLA accesses" hexmask.long 0x88 0.--31. 1. "BASE_ADDRESS,Base address of this memory region in 512bit granularity" line.long 0x8C "RGX_CR_FB_MEM_REGION15_1,Framebuffer Compression/Decompression memory regions for Host and TLA accesses" hexmask.long.byte 0x8C 25.--31. 1. "Reserved_57,Reserved_57" newline hexmask.long.tbyte 0x8C 2.--24. 1. "NUM_TILES,The number of compressor tiles to be used in this memory region" newline bitfld.long 0x8C 0.--1. "BASE_ADDRESS,Base address of this memory region in 512bit granularity" "0,1,2,3" line.long 0x90 "RGX_CR_FB_MEM_REGION_CTRL0_0,Framebuffer Compression/Decompression memory regions for Host and TLA accesses" hexmask.long.byte 0x90 25.--31. 1. "DIMY,Surface height in terms of TILE_TYPE for this memory region" newline hexmask.long.word 0x90 12.--24. 1. "DIMX,Surface width in terms of TILE_TYPE for this memory region" newline bitfld.long 0x90 11. "MEML,Surface Memory layout for this memory region 0=linear 1=twiddled" "linear,twiddled" newline bitfld.long 0x90 9.--10. "DM,Data master to be used for this memory region 00 = TA/Vertex 01 = 3D/Pixel 10 = Compute 11 = Data Master of Requester If the memory region is being accessed by the TLA the data master is set to the TLA data master If the memory region is being.." "TA/Vertex,?,?,?" newline bitfld.long 0x90 8. "TILE_TYPE,Compressor tile type 0 = 8x8 pixels 1 = 16x4 pixels" "0,1" newline hexmask.long.byte 0x90 1.--7. 1. "FMT,The pixel format to be used in this memory region" newline bitfld.long 0x90 0. "MODE,Defines if this memory region maps to BIF or FBC/FBDC access; 0 = BIF 1 = FBC/FBDC" "BIF,FBC/FBDC" line.long 0x94 "RGX_CR_FB_MEM_REGION_CTRL0_1,Framebuffer Compression/Decompression memory regions for Host and TLA accesses" hexmask.long.tbyte 0x94 15.--31. 1. "Reserved_47,Reserved_47" newline bitfld.long 0x94 14. "PORT,Defines if this memory region is to be used by the TLA or Host port. 0 = TLA Port 1 = Host Port" "TLA Port,Host Port" newline bitfld.long 0x94 13. "ACTIVE,Defines if this memory region is active or not default to INACTIVE. Used in conjuction with MODE field to define if a memory region maps to BIF or FBC/FBDC access. If active then this region base address is used to check if an access is for the.." "0,1" newline bitfld.long 0x94 12. "SLC_NOLINEFILL,SLC cache no line fill Policy: 0= line fill on miss 1=no line fill on miss" "line fill on miss,no line fill on miss" newline bitfld.long 0x94 10.--11. "SLC_POLICY,SLC cache Policy: 00=Bypass 01=Write Back 10 =Write Through 11=Cached Read" "Bypass,Write Back,?,?" newline bitfld.long 0x94 9. "TLCACHE_POLICY,Tile cache Policy: 1=no line fill on miss 0=line fill on miss" "line fill on miss,no line fill on miss" newline bitfld.long 0x94 8. "COR_COLOUR_ENABLE,Correlation Colour Enable 0=off 1=on" "off,on" newline bitfld.long 0x94 7. "IADDR,Direct/Indirect Addressing: 1=indirect 0=direct" "direct,indirect" newline hexmask.long.byte 0x94 0.--6. 1. "DIMY,Surface height in terms of TILE_TYPE for this memory region" line.long 0x98 "RGX_CR_FB_MEM_REGION_CTRL1_0,Framebuffer Compression/Decompression memory regions for Host and TLA accesses" hexmask.long.byte 0x98 25.--31. 1. "DIMY,Surface height in terms of TILE_TYPE for this memory region" newline hexmask.long.word 0x98 12.--24. 1. "DIMX,Surface width in terms of TILE_TYPE for this memory region" newline bitfld.long 0x98 11. "MEML,Surface Memory layout for this memory region 0=linear 1=twiddled" "linear,twiddled" newline bitfld.long 0x98 9.--10. "DM,Data master to be used for this memory region 00 = TA/Vertex 01 = 3D/Pixel 10 = Compute 11 = Data Master of Requester If the memory region is being accessed by the TLA the data master is set to the TLA data master If the memory region is being.." "TA/Vertex,?,?,?" newline bitfld.long 0x98 8. "TILE_TYPE,Compressor tile type 0 = 8x8 pixels 1 = 16x4 pixels" "0,1" newline hexmask.long.byte 0x98 1.--7. 1. "FMT,The pixel format to be used in this memory region" newline bitfld.long 0x98 0. "MODE,Defines if this memory region maps to BIF or FBC/FBDC access; 0 = BIF 1 = FBC/FBDC" "BIF,FBC/FBDC" line.long 0x9C "RGX_CR_FB_MEM_REGION_CTRL1_1,Framebuffer Compression/Decompression memory regions for Host and TLA accesses" hexmask.long.tbyte 0x9C 15.--31. 1. "Reserved_47,Reserved_47" newline bitfld.long 0x9C 14. "PORT,Defines if this memory region is to be used by the TLA or Host port. 0 = TLA Port 1 = Host Port" "TLA Port,Host Port" newline bitfld.long 0x9C 13. "ACTIVE,Defines if this memory region is active or not default to INACTIVE. Used in conjuction with MODE field to define if a memory region maps to BIF or FBC/FBDC access. If active then this region base address is used to check if an access is for the.." "0,1" newline bitfld.long 0x9C 12. "SLC_NOLINEFILL,SLC cache no line fill Policy: 0= line fill on miss 1=no line fill on miss" "line fill on miss,no line fill on miss" newline bitfld.long 0x9C 10.--11. "SLC_POLICY,SLC cache Policy: 00=Bypass 01=Write Back 10 =Write Through 11=Cached Read" "Bypass,Write Back,?,?" newline bitfld.long 0x9C 9. "TLCACHE_POLICY,Tile cache Policy: 1=no line fill on miss 0=line fill on miss" "line fill on miss,no line fill on miss" newline bitfld.long 0x9C 8. "COR_COLOUR_ENABLE,Correlation Colour Enable 0=off 1=on" "off,on" newline bitfld.long 0x9C 7. "IADDR,Direct/Indirect Addressing: 1=indirect 0=direct" "direct,indirect" newline hexmask.long.byte 0x9C 0.--6. 1. "DIMY,Surface height in terms of TILE_TYPE for this memory region" line.long 0xA0 "RGX_CR_FB_MEM_REGION_CTRL2_0,Framebuffer Compression/Decompression memory regions for Host and TLA accesses" hexmask.long.byte 0xA0 25.--31. 1. "DIMY,Surface height in terms of TILE_TYPE for this memory region" newline hexmask.long.word 0xA0 12.--24. 1. "DIMX,Surface width in terms of TILE_TYPE for this memory region" newline bitfld.long 0xA0 11. "MEML,Surface Memory layout for this memory region 0=linear 1=twiddled" "linear,twiddled" newline bitfld.long 0xA0 9.--10. "DM,Data master to be used for this memory region 00 = TA/Vertex 01 = 3D/Pixel 10 = Compute 11 = Data Master of Requester If the memory region is being accessed by the TLA the data master is set to the TLA data master If the memory region is being.." "TA/Vertex,?,?,?" newline bitfld.long 0xA0 8. "TILE_TYPE,Compressor tile type 0 = 8x8 pixels 1 = 16x4 pixels" "0,1" newline hexmask.long.byte 0xA0 1.--7. 1. "FMT,The pixel format to be used in this memory region" newline bitfld.long 0xA0 0. "MODE,Defines if this memory region maps to BIF or FBC/FBDC access; 0 = BIF 1 = FBC/FBDC" "BIF,FBC/FBDC" line.long 0xA4 "RGX_CR_FB_MEM_REGION_CTRL2_1,Framebuffer Compression/Decompression memory regions for Host and TLA accesses" hexmask.long.tbyte 0xA4 15.--31. 1. "Reserved_47,Reserved_47" newline bitfld.long 0xA4 14. "PORT,Defines if this memory region is to be used by the TLA or Host port. 0 = TLA Port 1 = Host Port" "TLA Port,Host Port" newline bitfld.long 0xA4 13. "ACTIVE,Defines if this memory region is active or not default to INACTIVE. Used in conjuction with MODE field to define if a memory region maps to BIF or FBC/FBDC access. If active then this region base address is used to check if an access is for the.." "0,1" newline bitfld.long 0xA4 12. "SLC_NOLINEFILL,SLC cache no line fill Policy: 0= line fill on miss 1=no line fill on miss" "line fill on miss,no line fill on miss" newline bitfld.long 0xA4 10.--11. "SLC_POLICY,SLC cache Policy: 00=Bypass 01=Write Back 10 =Write Through 11=Cached Read" "Bypass,Write Back,?,?" newline bitfld.long 0xA4 9. "TLCACHE_POLICY,Tile cache Policy: 1=no line fill on miss 0=line fill on miss" "line fill on miss,no line fill on miss" newline bitfld.long 0xA4 8. "COR_COLOUR_ENABLE,Correlation Colour Enable 0=off 1=on" "off,on" newline bitfld.long 0xA4 7. "IADDR,Direct/Indirect Addressing: 1=indirect 0=direct" "direct,indirect" newline hexmask.long.byte 0xA4 0.--6. 1. "DIMY,Surface height in terms of TILE_TYPE for this memory region" line.long 0xA8 "RGX_CR_FB_MEM_REGION_CTRL3_0,Framebuffer Compression/Decompression memory regions for Host and TLA accesses" hexmask.long.byte 0xA8 25.--31. 1. "DIMY,Surface height in terms of TILE_TYPE for this memory region" newline hexmask.long.word 0xA8 12.--24. 1. "DIMX,Surface width in terms of TILE_TYPE for this memory region" newline bitfld.long 0xA8 11. "MEML,Surface Memory layout for this memory region 0=linear 1=twiddled" "linear,twiddled" newline bitfld.long 0xA8 9.--10. "DM,Data master to be used for this memory region 00 = TA/Vertex 01 = 3D/Pixel 10 = Compute 11 = Data Master of Requester If the memory region is being accessed by the TLA the data master is set to the TLA data master If the memory region is being.." "TA/Vertex,?,?,?" newline bitfld.long 0xA8 8. "TILE_TYPE,Compressor tile type 0 = 8x8 pixels 1 = 16x4 pixels" "0,1" newline hexmask.long.byte 0xA8 1.--7. 1. "FMT,The pixel format to be used in this memory region" newline bitfld.long 0xA8 0. "MODE,Defines if this memory region maps to BIF or FBC/FBDC access; 0 = BIF 1 = FBC/FBDC" "BIF,FBC/FBDC" line.long 0xAC "RGX_CR_FB_MEM_REGION_CTRL3_1,Framebuffer Compression/Decompression memory regions for Host and TLA accesses" hexmask.long.tbyte 0xAC 15.--31. 1. "Reserved_47,Reserved_47" newline bitfld.long 0xAC 14. "PORT,Defines if this memory region is to be used by the TLA or Host port. 0 = TLA Port 1 = Host Port" "TLA Port,Host Port" newline bitfld.long 0xAC 13. "ACTIVE,Defines if this memory region is active or not default to INACTIVE. Used in conjuction with MODE field to define if a memory region maps to BIF or FBC/FBDC access. If active then this region base address is used to check if an access is for the.." "0,1" newline bitfld.long 0xAC 12. "SLC_NOLINEFILL,SLC cache no line fill Policy: 0= line fill on miss 1=no line fill on miss" "line fill on miss,no line fill on miss" newline bitfld.long 0xAC 10.--11. "SLC_POLICY,SLC cache Policy: 00=Bypass 01=Write Back 10 =Write Through 11=Cached Read" "Bypass,Write Back,?,?" newline bitfld.long 0xAC 9. "TLCACHE_POLICY,Tile cache Policy: 1=no line fill on miss 0=line fill on miss" "line fill on miss,no line fill on miss" newline bitfld.long 0xAC 8. "COR_COLOUR_ENABLE,Correlation Colour Enable 0=off 1=on" "off,on" newline bitfld.long 0xAC 7. "IADDR,Direct/Indirect Addressing: 1=indirect 0=direct" "direct,indirect" newline hexmask.long.byte 0xAC 0.--6. 1. "DIMY,Surface height in terms of TILE_TYPE for this memory region" line.long 0xB0 "RGX_CR_FB_MEM_REGION_CTRL4_0,Framebuffer Compression/Decompression memory regions for Host and TLA accesses" hexmask.long.byte 0xB0 25.--31. 1. "DIMY,Surface height in terms of TILE_TYPE for this memory region" newline hexmask.long.word 0xB0 12.--24. 1. "DIMX,Surface width in terms of TILE_TYPE for this memory region" newline bitfld.long 0xB0 11. "MEML,Surface Memory layout for this memory region 0=linear 1=twiddled" "linear,twiddled" newline bitfld.long 0xB0 9.--10. "DM,Data master to be used for this memory region 00 = TA/Vertex 01 = 3D/Pixel 10 = Compute 11 = Data Master of Requester If the memory region is being accessed by the TLA the data master is set to the TLA data master If the memory region is being.." "TA/Vertex,?,?,?" newline bitfld.long 0xB0 8. "TILE_TYPE,Compressor tile type 0 = 8x8 pixels 1 = 16x4 pixels" "0,1" newline hexmask.long.byte 0xB0 1.--7. 1. "FMT,The pixel format to be used in this memory region" newline bitfld.long 0xB0 0. "MODE,Defines if this memory region maps to BIF or FBC/FBDC access; 0 = BIF 1 = FBC/FBDC" "BIF,FBC/FBDC" line.long 0xB4 "RGX_CR_FB_MEM_REGION_CTRL4_1,Framebuffer Compression/Decompression memory regions for Host and TLA accesses" hexmask.long.tbyte 0xB4 15.--31. 1. "Reserved_47,Reserved_47" newline bitfld.long 0xB4 14. "PORT,Defines if this memory region is to be used by the TLA or Host port. 0 = TLA Port 1 = Host Port" "TLA Port,Host Port" newline bitfld.long 0xB4 13. "ACTIVE,Defines if this memory region is active or not default to INACTIVE. Used in conjuction with MODE field to define if a memory region maps to BIF or FBC/FBDC access. If active then this region base address is used to check if an access is for the.." "0,1" newline bitfld.long 0xB4 12. "SLC_NOLINEFILL,SLC cache no line fill Policy: 0= line fill on miss 1=no line fill on miss" "line fill on miss,no line fill on miss" newline bitfld.long 0xB4 10.--11. "SLC_POLICY,SLC cache Policy: 00=Bypass 01=Write Back 10 =Write Through 11=Cached Read" "Bypass,Write Back,?,?" newline bitfld.long 0xB4 9. "TLCACHE_POLICY,Tile cache Policy: 1=no line fill on miss 0=line fill on miss" "line fill on miss,no line fill on miss" newline bitfld.long 0xB4 8. "COR_COLOUR_ENABLE,Correlation Colour Enable 0=off 1=on" "off,on" newline bitfld.long 0xB4 7. "IADDR,Direct/Indirect Addressing: 1=indirect 0=direct" "direct,indirect" newline hexmask.long.byte 0xB4 0.--6. 1. "DIMY,Surface height in terms of TILE_TYPE for this memory region" line.long 0xB8 "RGX_CR_FB_MEM_REGION_CTRL5_0,Framebuffer Compression/Decompression memory regions for Host and TLA accesses" hexmask.long.byte 0xB8 25.--31. 1. "DIMY,Surface height in terms of TILE_TYPE for this memory region" newline hexmask.long.word 0xB8 12.--24. 1. "DIMX,Surface width in terms of TILE_TYPE for this memory region" newline bitfld.long 0xB8 11. "MEML,Surface Memory layout for this memory region 0=linear 1=twiddled" "linear,twiddled" newline bitfld.long 0xB8 9.--10. "DM,Data master to be used for this memory region 00 = TA/Vertex 01 = 3D/Pixel 10 = Compute 11 = Data Master of Requester If the memory region is being accessed by the TLA the data master is set to the TLA data master If the memory region is being.." "TA/Vertex,?,?,?" newline bitfld.long 0xB8 8. "TILE_TYPE,Compressor tile type 0 = 8x8 pixels 1 = 16x4 pixels" "0,1" newline hexmask.long.byte 0xB8 1.--7. 1. "FMT,The pixel format to be used in this memory region" newline bitfld.long 0xB8 0. "MODE,Defines if this memory region maps to BIF or FBC/FBDC access; 0 = BIF 1 = FBC/FBDC" "BIF,FBC/FBDC" line.long 0xBC "RGX_CR_FB_MEM_REGION_CTRL5_1,Framebuffer Compression/Decompression memory regions for Host and TLA accesses" hexmask.long.tbyte 0xBC 15.--31. 1. "Reserved_47,Reserved_47" newline bitfld.long 0xBC 14. "PORT,Defines if this memory region is to be used by the TLA or Host port. 0 = TLA Port 1 = Host Port" "TLA Port,Host Port" newline bitfld.long 0xBC 13. "ACTIVE,Defines if this memory region is active or not default to INACTIVE. Used in conjuction with MODE field to define if a memory region maps to BIF or FBC/FBDC access. If active then this region base address is used to check if an access is for the.." "0,1" newline bitfld.long 0xBC 12. "SLC_NOLINEFILL,SLC cache no line fill Policy: 0= line fill on miss 1=no line fill on miss" "line fill on miss,no line fill on miss" newline bitfld.long 0xBC 10.--11. "SLC_POLICY,SLC cache Policy: 00=Bypass 01=Write Back 10 =Write Through 11=Cached Read" "Bypass,Write Back,?,?" newline bitfld.long 0xBC 9. "TLCACHE_POLICY,Tile cache Policy: 1=no line fill on miss 0=line fill on miss" "line fill on miss,no line fill on miss" newline bitfld.long 0xBC 8. "COR_COLOUR_ENABLE,Correlation Colour Enable 0=off 1=on" "off,on" newline bitfld.long 0xBC 7. "IADDR,Direct/Indirect Addressing: 1=indirect 0=direct" "direct,indirect" newline hexmask.long.byte 0xBC 0.--6. 1. "DIMY,Surface height in terms of TILE_TYPE for this memory region" line.long 0xC0 "RGX_CR_FB_MEM_REGION_CTRL6_0,Framebuffer Compression/Decompression memory regions for Host and TLA accesses" hexmask.long.byte 0xC0 25.--31. 1. "DIMY,Surface height in terms of TILE_TYPE for this memory region" newline hexmask.long.word 0xC0 12.--24. 1. "DIMX,Surface width in terms of TILE_TYPE for this memory region" newline bitfld.long 0xC0 11. "MEML,Surface Memory layout for this memory region 0=linear 1=twiddled" "linear,twiddled" newline bitfld.long 0xC0 9.--10. "DM,Data master to be used for this memory region 00 = TA/Vertex 01 = 3D/Pixel 10 = Compute 11 = Data Master of Requester If the memory region is being accessed by the TLA the data master is set to the TLA data master If the memory region is being.." "TA/Vertex,?,?,?" newline bitfld.long 0xC0 8. "TILE_TYPE,Compressor tile type 0 = 8x8 pixels 1 = 16x4 pixels" "0,1" newline hexmask.long.byte 0xC0 1.--7. 1. "FMT,The pixel format to be used in this memory region" newline bitfld.long 0xC0 0. "MODE,Defines if this memory region maps to BIF or FBC/FBDC access; 0 = BIF 1 = FBC/FBDC" "BIF,FBC/FBDC" line.long 0xC4 "RGX_CR_FB_MEM_REGION_CTRL6_1,Framebuffer Compression/Decompression memory regions for Host and TLA accesses" hexmask.long.tbyte 0xC4 15.--31. 1. "Reserved_47,Reserved_47" newline bitfld.long 0xC4 14. "PORT,Defines if this memory region is to be used by the TLA or Host port. 0 = TLA Port 1 = Host Port" "TLA Port,Host Port" newline bitfld.long 0xC4 13. "ACTIVE,Defines if this memory region is active or not default to INACTIVE. Used in conjuction with MODE field to define if a memory region maps to BIF or FBC/FBDC access. If active then this region base address is used to check if an access is for the.." "0,1" newline bitfld.long 0xC4 12. "SLC_NOLINEFILL,SLC cache no line fill Policy: 0= line fill on miss 1=no line fill on miss" "line fill on miss,no line fill on miss" newline bitfld.long 0xC4 10.--11. "SLC_POLICY,SLC cache Policy: 00=Bypass 01=Write Back 10 =Write Through 11=Cached Read" "Bypass,Write Back,?,?" newline bitfld.long 0xC4 9. "TLCACHE_POLICY,Tile cache Policy: 1=no line fill on miss 0=line fill on miss" "line fill on miss,no line fill on miss" newline bitfld.long 0xC4 8. "COR_COLOUR_ENABLE,Correlation Colour Enable 0=off 1=on" "off,on" newline bitfld.long 0xC4 7. "IADDR,Direct/Indirect Addressing: 1=indirect 0=direct" "direct,indirect" newline hexmask.long.byte 0xC4 0.--6. 1. "DIMY,Surface height in terms of TILE_TYPE for this memory region" line.long 0xC8 "RGX_CR_FB_MEM_REGION_CTRL7_0,Framebuffer Compression/Decompression memory regions for Host and TLA accesses" hexmask.long.byte 0xC8 25.--31. 1. "DIMY,Surface height in terms of TILE_TYPE for this memory region" newline hexmask.long.word 0xC8 12.--24. 1. "DIMX,Surface width in terms of TILE_TYPE for this memory region" newline bitfld.long 0xC8 11. "MEML,Surface Memory layout for this memory region 0=linear 1=twiddled" "linear,twiddled" newline bitfld.long 0xC8 9.--10. "DM,Data master to be used for this memory region 00 = TA/Vertex 01 = 3D/Pixel 10 = Compute 11 = Data Master of Requester If the memory region is being accessed by the TLA the data master is set to the TLA data master If the memory region is being.." "TA/Vertex,?,?,?" newline bitfld.long 0xC8 8. "TILE_TYPE,Compressor tile type 0 = 8x8 pixels 1 = 16x4 pixels" "0,1" newline hexmask.long.byte 0xC8 1.--7. 1. "FMT,The pixel format to be used in this memory region" newline bitfld.long 0xC8 0. "MODE,Defines if this memory region maps to BIF or FBC/FBDC access; 0 = BIF 1 = FBC/FBDC" "BIF,FBC/FBDC" line.long 0xCC "RGX_CR_FB_MEM_REGION_CTRL7_1,Framebuffer Compression/Decompression memory regions for Host and TLA accesses" hexmask.long.tbyte 0xCC 15.--31. 1. "Reserved_47,Reserved_47" newline bitfld.long 0xCC 14. "PORT,Defines if this memory region is to be used by the TLA or Host port. 0 = TLA Port 1 = Host Port" "TLA Port,Host Port" newline bitfld.long 0xCC 13. "ACTIVE,Defines if this memory region is active or not default to INACTIVE. Used in conjuction with MODE field to define if a memory region maps to BIF or FBC/FBDC access. If active then this region base address is used to check if an access is for the.." "0,1" newline bitfld.long 0xCC 12. "SLC_NOLINEFILL,SLC cache no line fill Policy: 0= line fill on miss 1=no line fill on miss" "line fill on miss,no line fill on miss" newline bitfld.long 0xCC 10.--11. "SLC_POLICY,SLC cache Policy: 00=Bypass 01=Write Back 10 =Write Through 11=Cached Read" "Bypass,Write Back,?,?" newline bitfld.long 0xCC 9. "TLCACHE_POLICY,Tile cache Policy: 1=no line fill on miss 0=line fill on miss" "line fill on miss,no line fill on miss" newline bitfld.long 0xCC 8. "COR_COLOUR_ENABLE,Correlation Colour Enable 0=off 1=on" "off,on" newline bitfld.long 0xCC 7. "IADDR,Direct/Indirect Addressing: 1=indirect 0=direct" "direct,indirect" newline hexmask.long.byte 0xCC 0.--6. 1. "DIMY,Surface height in terms of TILE_TYPE for this memory region" line.long 0xD0 "RGX_CR_FB_MEM_REGION_CTRL8_0,Framebuffer Compression/Decompression memory regions for Host and TLA accesses" hexmask.long.byte 0xD0 25.--31. 1. "DIMY,Surface height in terms of TILE_TYPE for this memory region" newline hexmask.long.word 0xD0 12.--24. 1. "DIMX,Surface width in terms of TILE_TYPE for this memory region" newline bitfld.long 0xD0 11. "MEML,Surface Memory layout for this memory region 0=linear 1=twiddled" "linear,twiddled" newline bitfld.long 0xD0 9.--10. "DM,Data master to be used for this memory region 00 = TA/Vertex 01 = 3D/Pixel 10 = Compute 11 = Data Master of Requester If the memory region is being accessed by the TLA the data master is set to the TLA data master If the memory region is being.." "TA/Vertex,?,?,?" newline bitfld.long 0xD0 8. "TILE_TYPE,Compressor tile type 0 = 8x8 pixels 1 = 16x4 pixels" "0,1" newline hexmask.long.byte 0xD0 1.--7. 1. "FMT,The pixel format to be used in this memory region" newline bitfld.long 0xD0 0. "MODE,Defines if this memory region maps to BIF or FBC/FBDC access; 0 = BIF 1 = FBC/FBDC" "BIF,FBC/FBDC" line.long 0xD4 "RGX_CR_FB_MEM_REGION_CTRL8_1,Framebuffer Compression/Decompression memory regions for Host and TLA accesses" hexmask.long.tbyte 0xD4 15.--31. 1. "Reserved_47,Reserved_47" newline bitfld.long 0xD4 14. "PORT,Defines if this memory region is to be used by the TLA or Host port. 0 = TLA Port 1 = Host Port" "TLA Port,Host Port" newline bitfld.long 0xD4 13. "ACTIVE,Defines if this memory region is active or not default to INACTIVE. Used in conjuction with MODE field to define if a memory region maps to BIF or FBC/FBDC access. If active then this region base address is used to check if an access is for the.." "0,1" newline bitfld.long 0xD4 12. "SLC_NOLINEFILL,SLC cache no line fill Policy: 0= line fill on miss 1=no line fill on miss" "line fill on miss,no line fill on miss" newline bitfld.long 0xD4 10.--11. "SLC_POLICY,SLC cache Policy: 00=Bypass 01=Write Back 10 =Write Through 11=Cached Read" "Bypass,Write Back,?,?" newline bitfld.long 0xD4 9. "TLCACHE_POLICY,Tile cache Policy: 1=no line fill on miss 0=line fill on miss" "line fill on miss,no line fill on miss" newline bitfld.long 0xD4 8. "COR_COLOUR_ENABLE,Correlation Colour Enable 0=off 1=on" "off,on" newline bitfld.long 0xD4 7. "IADDR,Direct/Indirect Addressing: 1=indirect 0=direct" "direct,indirect" newline hexmask.long.byte 0xD4 0.--6. 1. "DIMY,Surface height in terms of TILE_TYPE for this memory region" line.long 0xD8 "RGX_CR_FB_MEM_REGION_CTRL9_0,Framebuffer Compression/Decompression memory regions for Host and TLA accesses" hexmask.long.byte 0xD8 25.--31. 1. "DIMY,Surface height in terms of TILE_TYPE for this memory region" newline hexmask.long.word 0xD8 12.--24. 1. "DIMX,Surface width in terms of TILE_TYPE for this memory region" newline bitfld.long 0xD8 11. "MEML,Surface Memory layout for this memory region 0=linear 1=twiddled" "linear,twiddled" newline bitfld.long 0xD8 9.--10. "DM,Data master to be used for this memory region 00 = TA/Vertex 01 = 3D/Pixel 10 = Compute 11 = Data Master of Requester If the memory region is being accessed by the TLA the data master is set to the TLA data master If the memory region is being.." "TA/Vertex,?,?,?" newline bitfld.long 0xD8 8. "TILE_TYPE,Compressor tile type 0 = 8x8 pixels 1 = 16x4 pixels" "0,1" newline hexmask.long.byte 0xD8 1.--7. 1. "FMT,The pixel format to be used in this memory region" newline bitfld.long 0xD8 0. "MODE,Defines if this memory region maps to BIF or FBC/FBDC access; 0 = BIF 1 = FBC/FBDC" "BIF,FBC/FBDC" line.long 0xDC "RGX_CR_FB_MEM_REGION_CTRL9_1,Framebuffer Compression/Decompression memory regions for Host and TLA accesses" hexmask.long.tbyte 0xDC 15.--31. 1. "Reserved_47,Reserved_47" newline bitfld.long 0xDC 14. "PORT,Defines if this memory region is to be used by the TLA or Host port. 0 = TLA Port 1 = Host Port" "TLA Port,Host Port" newline bitfld.long 0xDC 13. "ACTIVE,Defines if this memory region is active or not default to INACTIVE. Used in conjuction with MODE field to define if a memory region maps to BIF or FBC/FBDC access. If active then this region base address is used to check if an access is for the.." "0,1" newline bitfld.long 0xDC 12. "SLC_NOLINEFILL,SLC cache no line fill Policy: 0= line fill on miss 1=no line fill on miss" "line fill on miss,no line fill on miss" newline bitfld.long 0xDC 10.--11. "SLC_POLICY,SLC cache Policy: 00=Bypass 01=Write Back 10 =Write Through 11=Cached Read" "Bypass,Write Back,?,?" newline bitfld.long 0xDC 9. "TLCACHE_POLICY,Tile cache Policy: 1=no line fill on miss 0=line fill on miss" "line fill on miss,no line fill on miss" newline bitfld.long 0xDC 8. "COR_COLOUR_ENABLE,Correlation Colour Enable 0=off 1=on" "off,on" newline bitfld.long 0xDC 7. "IADDR,Direct/Indirect Addressing: 1=indirect 0=direct" "direct,indirect" newline hexmask.long.byte 0xDC 0.--6. 1. "DIMY,Surface height in terms of TILE_TYPE for this memory region" line.long 0xE0 "RGX_CR_FB_MEM_REGION_CTRL10_0,Framebuffer Compression/Decompression memory regions for Host and TLA accesses" hexmask.long.byte 0xE0 25.--31. 1. "DIMY,Surface height in terms of TILE_TYPE for this memory region" newline hexmask.long.word 0xE0 12.--24. 1. "DIMX,Surface width in terms of TILE_TYPE for this memory region" newline bitfld.long 0xE0 11. "MEML,Surface Memory layout for this memory region 0=linear 1=twiddled" "linear,twiddled" newline bitfld.long 0xE0 9.--10. "DM,Data master to be used for this memory region 00 = TA/Vertex 01 = 3D/Pixel 10 = Compute 11 = Data Master of Requester If the memory region is being accessed by the TLA the data master is set to the TLA data master If the memory region is being.." "TA/Vertex,?,?,?" newline bitfld.long 0xE0 8. "TILE_TYPE,Compressor tile type 0 = 8x8 pixels 1 = 16x4 pixels" "0,1" newline hexmask.long.byte 0xE0 1.--7. 1. "FMT,The pixel format to be used in this memory region" newline bitfld.long 0xE0 0. "MODE,Defines if this memory region maps to BIF or FBC/FBDC access; 0 = BIF 1 = FBC/FBDC" "BIF,FBC/FBDC" line.long 0xE4 "RGX_CR_FB_MEM_REGION_CTRL10_1,Framebuffer Compression/Decompression memory regions for Host and TLA accesses" hexmask.long.tbyte 0xE4 15.--31. 1. "Reserved_47,Reserved_47" newline bitfld.long 0xE4 14. "PORT,Defines if this memory region is to be used by the TLA or Host port. 0 = TLA Port 1 = Host Port" "TLA Port,Host Port" newline bitfld.long 0xE4 13. "ACTIVE,Defines if this memory region is active or not default to INACTIVE. Used in conjuction with MODE field to define if a memory region maps to BIF or FBC/FBDC access. If active then this region base address is used to check if an access is for the.." "0,1" newline bitfld.long 0xE4 12. "SLC_NOLINEFILL,SLC cache no line fill Policy: 0= line fill on miss 1=no line fill on miss" "line fill on miss,no line fill on miss" newline bitfld.long 0xE4 10.--11. "SLC_POLICY,SLC cache Policy: 00=Bypass 01=Write Back 10 =Write Through 11=Cached Read" "Bypass,Write Back,?,?" newline bitfld.long 0xE4 9. "TLCACHE_POLICY,Tile cache Policy: 1=no line fill on miss 0=line fill on miss" "line fill on miss,no line fill on miss" newline bitfld.long 0xE4 8. "COR_COLOUR_ENABLE,Correlation Colour Enable 0=off 1=on" "off,on" newline bitfld.long 0xE4 7. "IADDR,Direct/Indirect Addressing: 1=indirect 0=direct" "direct,indirect" newline hexmask.long.byte 0xE4 0.--6. 1. "DIMY,Surface height in terms of TILE_TYPE for this memory region" line.long 0xE8 "RGX_CR_FB_MEM_REGION_CTRL11_0,Framebuffer Compression/Decompression memory regions for Host and TLA accesses" hexmask.long.byte 0xE8 25.--31. 1. "DIMY,Surface height in terms of TILE_TYPE for this memory region" newline hexmask.long.word 0xE8 12.--24. 1. "DIMX,Surface width in terms of TILE_TYPE for this memory region" newline bitfld.long 0xE8 11. "MEML,Surface Memory layout for this memory region 0=linear 1=twiddled" "linear,twiddled" newline bitfld.long 0xE8 9.--10. "DM,Data master to be used for this memory region 00 = TA/Vertex 01 = 3D/Pixel 10 = Compute 11 = Data Master of Requester If the memory region is being accessed by the TLA the data master is set to the TLA data master If the memory region is being.." "TA/Vertex,?,?,?" newline bitfld.long 0xE8 8. "TILE_TYPE,Compressor tile type 0 = 8x8 pixels 1 = 16x4 pixels" "0,1" newline hexmask.long.byte 0xE8 1.--7. 1. "FMT,The pixel format to be used in this memory region" newline bitfld.long 0xE8 0. "MODE,Defines if this memory region maps to BIF or FBC/FBDC access; 0 = BIF 1 = FBC/FBDC" "BIF,FBC/FBDC" line.long 0xEC "RGX_CR_FB_MEM_REGION_CTRL11_1,Framebuffer Compression/Decompression memory regions for Host and TLA accesses" hexmask.long.tbyte 0xEC 15.--31. 1. "Reserved_47,Reserved_47" newline bitfld.long 0xEC 14. "PORT,Defines if this memory region is to be used by the TLA or Host port. 0 = TLA Port 1 = Host Port" "TLA Port,Host Port" newline bitfld.long 0xEC 13. "ACTIVE,Defines if this memory region is active or not default to INACTIVE. Used in conjuction with MODE field to define if a memory region maps to BIF or FBC/FBDC access. If active then this region base address is used to check if an access is for the.." "0,1" newline bitfld.long 0xEC 12. "SLC_NOLINEFILL,SLC cache no line fill Policy: 0= line fill on miss 1=no line fill on miss" "line fill on miss,no line fill on miss" newline bitfld.long 0xEC 10.--11. "SLC_POLICY,SLC cache Policy: 00=Bypass 01=Write Back 10 =Write Through 11=Cached Read" "Bypass,Write Back,?,?" newline bitfld.long 0xEC 9. "TLCACHE_POLICY,Tile cache Policy: 1=no line fill on miss 0=line fill on miss" "line fill on miss,no line fill on miss" newline bitfld.long 0xEC 8. "COR_COLOUR_ENABLE,Correlation Colour Enable 0=off 1=on" "off,on" newline bitfld.long 0xEC 7. "IADDR,Direct/Indirect Addressing: 1=indirect 0=direct" "direct,indirect" newline hexmask.long.byte 0xEC 0.--6. 1. "DIMY,Surface height in terms of TILE_TYPE for this memory region" line.long 0xF0 "RGX_CR_FB_MEM_REGION_CTRL12_0,Framebuffer Compression/Decompression memory regions for Host and TLA accesses" hexmask.long.byte 0xF0 25.--31. 1. "DIMY,Surface height in terms of TILE_TYPE for this memory region" newline hexmask.long.word 0xF0 12.--24. 1. "DIMX,Surface width in terms of TILE_TYPE for this memory region" newline bitfld.long 0xF0 11. "MEML,Surface Memory layout for this memory region 0=linear 1=twiddled" "linear,twiddled" newline bitfld.long 0xF0 9.--10. "DM,Data master to be used for this memory region 00 = TA/Vertex 01 = 3D/Pixel 10 = Compute 11 = Data Master of Requester If the memory region is being accessed by the TLA the data master is set to the TLA data master If the memory region is being.." "TA/Vertex,?,?,?" newline bitfld.long 0xF0 8. "TILE_TYPE,Compressor tile type 0 = 8x8 pixels 1 = 16x4 pixels" "0,1" newline hexmask.long.byte 0xF0 1.--7. 1. "FMT,The pixel format to be used in this memory region" newline bitfld.long 0xF0 0. "MODE,Defines if this memory region maps to BIF or FBC/FBDC access; 0 = BIF 1 = FBC/FBDC" "BIF,FBC/FBDC" line.long 0xF4 "RGX_CR_FB_MEM_REGION_CTRL12_1,Framebuffer Compression/Decompression memory regions for Host and TLA accesses" hexmask.long.tbyte 0xF4 15.--31. 1. "Reserved_47,Reserved_47" newline bitfld.long 0xF4 14. "PORT,Defines if this memory region is to be used by the TLA or Host port. 0 = TLA Port 1 = Host Port" "TLA Port,Host Port" newline bitfld.long 0xF4 13. "ACTIVE,Defines if this memory region is active or not default to INACTIVE. Used in conjuction with MODE field to define if a memory region maps to BIF or FBC/FBDC access. If active then this region base address is used to check if an access is for the.." "0,1" newline bitfld.long 0xF4 12. "SLC_NOLINEFILL,SLC cache no line fill Policy: 0= line fill on miss 1=no line fill on miss" "line fill on miss,no line fill on miss" newline bitfld.long 0xF4 10.--11. "SLC_POLICY,SLC cache Policy: 00=Bypass 01=Write Back 10 =Write Through 11=Cached Read" "Bypass,Write Back,?,?" newline bitfld.long 0xF4 9. "TLCACHE_POLICY,Tile cache Policy: 1=no line fill on miss 0=line fill on miss" "line fill on miss,no line fill on miss" newline bitfld.long 0xF4 8. "COR_COLOUR_ENABLE,Correlation Colour Enable 0=off 1=on" "off,on" newline bitfld.long 0xF4 7. "IADDR,Direct/Indirect Addressing: 1=indirect 0=direct" "direct,indirect" newline hexmask.long.byte 0xF4 0.--6. 1. "DIMY,Surface height in terms of TILE_TYPE for this memory region" line.long 0xF8 "RGX_CR_FB_MEM_REGION_CTRL13_0,Framebuffer Compression/Decompression memory regions for Host and TLA accesses" hexmask.long.byte 0xF8 25.--31. 1. "DIMY,Surface height in terms of TILE_TYPE for this memory region" newline hexmask.long.word 0xF8 12.--24. 1. "DIMX,Surface width in terms of TILE_TYPE for this memory region" newline bitfld.long 0xF8 11. "MEML,Surface Memory layout for this memory region 0=linear 1=twiddled" "linear,twiddled" newline bitfld.long 0xF8 9.--10. "DM,Data master to be used for this memory region 00 = TA/Vertex 01 = 3D/Pixel 10 = Compute 11 = Data Master of Requester If the memory region is being accessed by the TLA the data master is set to the TLA data master If the memory region is being.." "TA/Vertex,?,?,?" newline bitfld.long 0xF8 8. "TILE_TYPE,Compressor tile type 0 = 8x8 pixels 1 = 16x4 pixels" "0,1" newline hexmask.long.byte 0xF8 1.--7. 1. "FMT,The pixel format to be used in this memory region" newline bitfld.long 0xF8 0. "MODE,Defines if this memory region maps to BIF or FBC/FBDC access; 0 = BIF 1 = FBC/FBDC" "BIF,FBC/FBDC" line.long 0xFC "RGX_CR_FB_MEM_REGION_CTRL13_1,Framebuffer Compression/Decompression memory regions for Host and TLA accesses" hexmask.long.tbyte 0xFC 15.--31. 1. "Reserved_47,Reserved_47" newline bitfld.long 0xFC 14. "PORT,Defines if this memory region is to be used by the TLA or Host port. 0 = TLA Port 1 = Host Port" "TLA Port,Host Port" newline bitfld.long 0xFC 13. "ACTIVE,Defines if this memory region is active or not default to INACTIVE. Used in conjuction with MODE field to define if a memory region maps to BIF or FBC/FBDC access. If active then this region base address is used to check if an access is for the.." "0,1" newline bitfld.long 0xFC 12. "SLC_NOLINEFILL,SLC cache no line fill Policy: 0= line fill on miss 1=no line fill on miss" "line fill on miss,no line fill on miss" newline bitfld.long 0xFC 10.--11. "SLC_POLICY,SLC cache Policy: 00=Bypass 01=Write Back 10 =Write Through 11=Cached Read" "Bypass,Write Back,?,?" newline bitfld.long 0xFC 9. "TLCACHE_POLICY,Tile cache Policy: 1=no line fill on miss 0=line fill on miss" "line fill on miss,no line fill on miss" newline bitfld.long 0xFC 8. "COR_COLOUR_ENABLE,Correlation Colour Enable 0=off 1=on" "off,on" newline bitfld.long 0xFC 7. "IADDR,Direct/Indirect Addressing: 1=indirect 0=direct" "direct,indirect" newline hexmask.long.byte 0xFC 0.--6. 1. "DIMY,Surface height in terms of TILE_TYPE for this memory region" line.long 0x100 "RGX_CR_FB_MEM_REGION_CTRL14_0,Framebuffer Compression/Decompression memory regions for Host and TLA accesses" hexmask.long.byte 0x100 25.--31. 1. "DIMY,Surface height in terms of TILE_TYPE for this memory region" newline hexmask.long.word 0x100 12.--24. 1. "DIMX,Surface width in terms of TILE_TYPE for this memory region" newline bitfld.long 0x100 11. "MEML,Surface Memory layout for this memory region 0=linear 1=twiddled" "linear,twiddled" newline bitfld.long 0x100 9.--10. "DM,Data master to be used for this memory region 00 = TA/Vertex 01 = 3D/Pixel 10 = Compute 11 = Data Master of Requester If the memory region is being accessed by the TLA the data master is set to the TLA data master If the memory region is being.." "TA/Vertex,?,?,?" newline bitfld.long 0x100 8. "TILE_TYPE,Compressor tile type 0 = 8x8 pixels 1 = 16x4 pixels" "0,1" newline hexmask.long.byte 0x100 1.--7. 1. "FMT,The pixel format to be used in this memory region" newline bitfld.long 0x100 0. "MODE,Defines if this memory region maps to BIF or FBC/FBDC access; 0 = BIF 1 = FBC/FBDC" "BIF,FBC/FBDC" line.long 0x104 "RGX_CR_FB_MEM_REGION_CTRL14_1,Framebuffer Compression/Decompression memory regions for Host and TLA accesses" hexmask.long.tbyte 0x104 15.--31. 1. "Reserved_47,Reserved_47" newline bitfld.long 0x104 14. "PORT,Defines if this memory region is to be used by the TLA or Host port. 0 = TLA Port 1 = Host Port" "TLA Port,Host Port" newline bitfld.long 0x104 13. "ACTIVE,Defines if this memory region is active or not default to INACTIVE. Used in conjuction with MODE field to define if a memory region maps to BIF or FBC/FBDC access. If active then this region base address is used to check if an access is for the.." "0,1" newline bitfld.long 0x104 12. "SLC_NOLINEFILL,SLC cache no line fill Policy: 0= line fill on miss 1=no line fill on miss" "line fill on miss,no line fill on miss" newline bitfld.long 0x104 10.--11. "SLC_POLICY,SLC cache Policy: 00=Bypass 01=Write Back 10 =Write Through 11=Cached Read" "Bypass,Write Back,?,?" newline bitfld.long 0x104 9. "TLCACHE_POLICY,Tile cache Policy: 1=no line fill on miss 0=line fill on miss" "line fill on miss,no line fill on miss" newline bitfld.long 0x104 8. "COR_COLOUR_ENABLE,Correlation Colour Enable 0=off 1=on" "off,on" newline bitfld.long 0x104 7. "IADDR,Direct/Indirect Addressing: 1=indirect 0=direct" "direct,indirect" newline hexmask.long.byte 0x104 0.--6. 1. "DIMY,Surface height in terms of TILE_TYPE for this memory region" line.long 0x108 "RGX_CR_FB_MEM_REGION_CTRL15_0,Framebuffer Compression/Decompression memory regions for Host and TLA accesses" hexmask.long.byte 0x108 25.--31. 1. "DIMY,Surface height in terms of TILE_TYPE for this memory region" newline hexmask.long.word 0x108 12.--24. 1. "DIMX,Surface width in terms of TILE_TYPE for this memory region" newline bitfld.long 0x108 11. "MEML,Surface Memory layout for this memory region 0=linear 1=twiddled" "linear,twiddled" newline bitfld.long 0x108 9.--10. "DM,Data master to be used for this memory region 00 = TA/Vertex 01 = 3D/Pixel 10 = Compute 11 = Data Master of Requester If the memory region is being accessed by the TLA the data master is set to the TLA data master If the memory region is being.." "TA/Vertex,?,?,?" newline bitfld.long 0x108 8. "TILE_TYPE,Compressor tile type 0 = 8x8 pixels 1 = 16x4 pixels" "0,1" newline hexmask.long.byte 0x108 1.--7. 1. "FMT,The pixel format to be used in this memory region" newline bitfld.long 0x108 0. "MODE,Defines if this memory region maps to BIF or FBC/FBDC access; 0 = BIF 1 = FBC/FBDC" "BIF,FBC/FBDC" line.long 0x10C "RGX_CR_FB_MEM_REGION_CTRL15_1,Framebuffer Compression/Decompression memory regions for Host and TLA accesses" hexmask.long.tbyte 0x10C 15.--31. 1. "Reserved_47,Reserved_47" newline bitfld.long 0x10C 14. "PORT,Defines if this memory region is to be used by the TLA or Host port. 0 = TLA Port 1 = Host Port" "TLA Port,Host Port" newline bitfld.long 0x10C 13. "ACTIVE,Defines if this memory region is active or not default to INACTIVE. Used in conjuction with MODE field to define if a memory region maps to BIF or FBC/FBDC access. If active then this region base address is used to check if an access is for the.." "0,1" newline bitfld.long 0x10C 12. "SLC_NOLINEFILL,SLC cache no line fill Policy: 0= line fill on miss 1=no line fill on miss" "line fill on miss,no line fill on miss" newline bitfld.long 0x10C 10.--11. "SLC_POLICY,SLC cache Policy: 00=Bypass 01=Write Back 10 =Write Through 11=Cached Read" "Bypass,Write Back,?,?" newline bitfld.long 0x10C 9. "TLCACHE_POLICY,Tile cache Policy: 1=no line fill on miss 0=line fill on miss" "line fill on miss,no line fill on miss" newline bitfld.long 0x10C 8. "COR_COLOUR_ENABLE,Correlation Colour Enable 0=off 1=on" "off,on" newline bitfld.long 0x10C 7. "IADDR,Direct/Indirect Addressing: 1=indirect 0=direct" "direct,indirect" newline hexmask.long.byte 0x10C 0.--6. 1. "DIMY,Surface height in terms of TILE_TYPE for this memory region" line.long 0x110 "RGX_CR_FB_CDC_ZLS_0,Framebuffer Compression/Decompression configuration register for ZLS access" hexmask.long.byte 0x110 27.--31. 1. "Reserved_27,Reserved_27" newline hexmask.long.tbyte 0x110 4.--26. 1. "FBC_NUM_TILES,FBC ZLS number of compressor tiles in surface in granularity of 8x8x32dwords" newline bitfld.long 0x110 2.--3. "Reserved_2,Reserved_2" "0,1,2,3" newline bitfld.long 0x110 1. "FBC_IADDR,FBC Addressing mode 0 = direct ; 1 = indirect" "direct ;,indirect" newline bitfld.long 0x110 0. "FBDC_IADDR,FBDC Addressing mode 0 = direct ; 1 = indirect" "direct ;,indirect" line.long 0x114 "RGX_CR_FB_CDC_ZLS_1,Framebuffer Compression/Decompression configuration register for ZLS access" hexmask.long 0x114 0.--31. 1. "Reserved_27,Reserved_27" line.long 0x118 "RGX_CR_FB_0,Rascal Arbiter for FBC/FBDC arbiter modes" hexmask.long 0x118 2.--31. 1. "Reserved_2,Reserved_2" newline bitfld.long 0x118 1. "ZLSMCU_ARB_MODE,ZLS and MCU TLDecode Arbiter Mode Re-arbitrate after burst complete 0 = After each request 1 = valid dropped" "After each request,valid dropped" newline bitfld.long 0x118 0. "ZLSPBE_ARB_MODE,ZLS and PBE FBC Arbiter Mode Re-arbitrate after burst complete and 0 = After each request 1 = valid dropped" "After each request,valid dropped" line.long 0x11C "RGX_CR_FB_1,Rascal Arbiter for FBC/FBDC arbiter modes" hexmask.long 0x11C 0.--31. 1. "Reserved_2,Reserved_2" wgroup.long 0x1720++0x7 line.long 0x0 "RGX_CR_MCU_GLB_CFI_0,Global flush and invalidation control for all Texture and Data Cache. Will flush then invalidate cache if both bit 0 & bit 1 set." hexmask.long.tbyte 0x0 10.--31. 1. "Reserved_10,Reserved_10" newline bitfld.long 0x0 9. "DM_FASTRENDER,When set perform operation on fastrender data master" "0,1" newline bitfld.long 0x0 6.--8. "Reserved_6,Reserved_6" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 5. "FENCE,When set additionally perform a fence to external memory before signalling that a flush is complete" "0,1" newline bitfld.long 0x0 4. "DM_COMPUTE,When set perform operation on compute data master" "0,1" newline bitfld.long 0x0 3. "DM_PIXEL,When set perform operation on pixel data master" "0,1" newline bitfld.long 0x0 2. "DM_VERTEX,When set perform operation on vertex data master" "0,1" newline bitfld.long 0x0 1. "FLUSH,When set will flush cache based on data master" "0,1" newline bitfld.long 0x0 0. "INVALIDATE,When set will invalidate cache based on data master. This bit will also invalidate the L0 cache in the MADD and teh YUV cache in the TAG to reset the CSC coefficients." "0,1" line.long 0x4 "RGX_CR_MCU_GLB_CFI_1,Global flush and invalidation control for all Texture and Data Cache. Will flush then invalidate cache if both bit 0 & bit 1 set." hexmask.long 0x4 0.--31. 1. "Reserved_10,Reserved_10" rgroup.long 0x1728++0x7 line.long 0x0 "RGX_CR_MCU_GLB_CFI_EVENT_0,Global flush and invalidation event for all Texture and Data Cache." hexmask.long 0x0 1.--31. 1. "Reserved_1,Reserved_1" newline bitfld.long 0x0 0. "PENDING,1 Indicate there is a pending global CFI operation on the MCU" "0,1" line.long 0x4 "RGX_CR_MCU_GLB_CFI_EVENT_1,Global flush and invalidation event for all Texture and Data Cache." hexmask.long 0x4 0.--31. 1. "Reserved_1,Reserved_1" group.long 0x1730++0x17 line.long 0x0 "RGX_CR_MCU_LIMIT_0,Define the maximum number of cache lines allowed to be allocated to each Data Master within the SLC. Note that values are specified per group with a value of 0x0 denoting no limit. Also note that the specified values operate as soft.." hexmask.long.byte 0x0 24.--31. 1. "Reserved_24,Reserved_24" newline hexmask.long.byte 0x0 16.--23. 1. "DM_COMPUTE,Maximum number of cachelines which can be used by the Compute data master" newline hexmask.long.byte 0x0 8.--15. 1. "DM_PIXEL,Maximum number of cachelines which can be used by the Pixel data master" newline hexmask.long.byte 0x0 0.--7. 1. "DM_VERTEX,Maximum number of cachelines which can be used by the Vertex data master" line.long 0x4 "RGX_CR_MCU_LIMIT_1,Define the maximum number of cache lines allowed to be allocated to each Data Master within the SLC. Note that values are specified per group with a value of 0x0 denoting no limit. Also note that the specified values operate as soft.." hexmask.long 0x4 0.--31. 1. "Reserved_24,Reserved_24" line.long 0x8 "RGX_CR_MCU_CTRL_0,MCU control registers" hexmask.long.word 0x8 18.--31. 1. "Reserved_18,Reserved_18" newline bitfld.long 0x8 17. "PDSRW_L0_OFF,Turn off MCU PDSRW L0 cache" "0,1" newline hexmask.long.byte 0x8 9.--16. 1. "FBDC_REQ_THRESHOLD,Maximum number of outstanding requests each MCU group can have to the Framebuffer Decompression module" newline bitfld.long 0x8 8. "RD_OVERTAKE_THRESH_ENABLE,Enables the use of the threshold to limit the amount of overtaking which is permitted" "0,1" newline hexmask.long.byte 0x8 2.--7. 1. "RD_OVERTAKE_THRESHOLD,The number of read accesses which are permitted to overtake waiting Writebacks when enabled" newline bitfld.long 0x8 1. "INSTANCE_MERGE_DISABLE,Turn off instance merging in the MCU L1" "0,1" newline bitfld.long 0x8 0. "L1_OFF,Turn off MCU L1" "0,1" line.long 0xC "RGX_CR_MCU_CTRL_1,MCU control registers" hexmask.long 0xC 0.--31. 1. "Reserved_18,Reserved_18" line.long 0x10 "RGX_CR_MCU_FENCE_0,Defines the Data Master and Addresses used when the MCU optionally issues a Fence as part of a Flush operation. See MCU_GLB_CFI register for details." hexmask.long 0x10 5.--31. 1. "ADDR,Address value to use when issuing a Fence" newline hexmask.long.byte 0x10 0.--4. 1. "Reserved_0,Reserved_0" line.long 0x14 "RGX_CR_MCU_FENCE_1,Defines the Data Master and Addresses used when the MCU optionally issues a Fence as part of a Flush operation. See MCU_GLB_CFI register for details." hexmask.long.tbyte 0x14 11.--31. 1. "Reserved_43,Reserved_43" newline bitfld.long 0x14 8.--10. "DM,Data Master value to use when issuing a Fence" "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x14 0.--7. 1. "ADDR,Address value to use when issuing a Fence" group.long 0x1780++0x17 line.long 0x0 "RGX_CR_TPU_0,Global control to TPU_MCU_L0|tpu" hexmask.long.tbyte 0x0 9.--31. 1. "Reserved_9,Reserved_9" newline bitfld.long 0x0 8. "MCU_PDS_L0_OFF,Turn off MCU PDSL0 cache" "0,1" newline bitfld.long 0x0 7. "Reserved_7,Reserved_7" "0,1" newline bitfld.long 0x0 6. "TAG_ENABLE_MMU_PREFETCH,Enables generation of prefetch requests to the MMU" "0,1" newline bitfld.long 0x0 5. "TAG_CEM_4K_FACE_PACKING,Pixel data master. Enable 4K-byte alignment between CEM faces when set to 1. It applies for both when mipmap is enabled or disabled" "0,1" newline bitfld.long 0x0 4. "MADD_CONFIG_L0OFF,When set this disables MADD P0 L0 cache" "0,1" newline bitfld.long 0x0 3. "TAG_CEM_FACE_PACKING,Pixel data master. Enable dword alignment between CEM faces when set to 1" "0,1" newline bitfld.long 0x0 2. "TAG_CEMEDGE_DONTFILTER,Pixel data master. Disable filtering over edges/corners for CEM. When set to 1 HW will be seemfull ie always stay in the current map always honour the addressmode. When set to 0 HW will be seemless ie ignore addressmode.." "0,1" newline bitfld.long 0x0 1. "TAG_CEMGRAD_DONTNEGATE,Pixel data master. Disable negation for user supplied gradients for cem swap i. e. will only swap dudx etc not negate" "0,1" newline bitfld.long 0x0 0. "MADD_CONFIG_DXT35_TRANSOVR,When set this disables alternative mode implied by colour0 > colour1 for DXT3 to DXT5" "colour1 for DXT3 to DXT5,?" line.long 0x4 "RGX_CR_TPU_1,Global control to TPU_MCU_L0|tpu" hexmask.long 0x4 0.--31. 1. "Reserved_9,Reserved_9" line.long 0x8 "RGX_CR_TPU_YUV_CSC_COEFFICIENTS_0,Base address for the YUV CSC set of coefficients stored in memory for pixel data master" hexmask.long 0x8 0.--31. 1. "YUV_CSC_COEFFICIENTS_ADDRESS,Base address DWORD aligned for the location in memory of the CSC coefficients" line.long 0xC "RGX_CR_TPU_YUV_CSC_COEFFICIENTS_1,Base address for the YUV CSC set of coefficients stored in memory for pixel data master" hexmask.long 0xC 6.--31. 1. "Reserved_38,Reserved_38" newline hexmask.long.byte 0xC 0.--5. 1. "YUV_CSC_COEFFICIENTS_ADDRESS,Base address DWORD aligned for the location in memory of the CSC coefficients" line.long 0x10 "RGX_CR_TPU_BORDER_COLOUR_TABLE_PDM_0,Base address for the border colour table" hexmask.long 0x10 0.--31. 1. "BORDER_COLOUR_TABLE_ADDRESS,Base address DWORD aligned for the location in memory of the border colour table for the PDM" line.long 0x14 "RGX_CR_TPU_BORDER_COLOUR_TABLE_PDM_1,Base address for the border colour table" hexmask.long 0x14 6.--31. 1. "Reserved_38,Reserved_38" newline hexmask.long.byte 0x14 0.--5. 1. "BORDER_COLOUR_TABLE_ADDRESS,Base address DWORD aligned for the location in memory of the border colour table for the PDM" rgroup.long 0x1798++0x7 line.long 0x0 "RGX_CR_DUST_IDLE_0,RGX_CR_DUST_IDLE_0" hexmask.long 0x0 7.--31. 1. "Reserved_7,Reserved_7" newline bitfld.long 0x0 6. "MCU_L0_WRAP,MCU L0 WRAP Module IDLE" "0,1" newline bitfld.long 0x0 5. "MCU_L0,MCU L0 Module IDLE" "0,1" newline bitfld.long 0x0 4. "TF,TF Module IDLE" "0,1" newline bitfld.long 0x0 3. "MADD,MADD Module IDLE" "0,1" newline bitfld.long 0x0 2. "TAG,TAG Module IDLE" "0,1" newline bitfld.long 0x0 1. "USC1,USC1 Module IDLE" "0,1" newline bitfld.long 0x0 0. "USC0,USC0 Module IDLE" "0,1" line.long 0x4 "RGX_CR_DUST_IDLE_1,RGX_CR_DUST_IDLE_1" hexmask.long 0x4 0.--31. 1. "Reserved_7,Reserved_7" group.long 0x17A0++0xF line.long 0x0 "RGX_CR_TPU_BORDER_COLOUR_TABLE_VDM_0,Base address for the border colour table" hexmask.long 0x0 0.--31. 1. "BORDER_COLOUR_TABLE_ADDRESS,Base address DWORD aligned for the location in memory of the border colour table for the VDM" line.long 0x4 "RGX_CR_TPU_BORDER_COLOUR_TABLE_VDM_1,Base address for the border colour table" hexmask.long 0x4 6.--31. 1. "Reserved_38,Reserved_38" newline hexmask.long.byte 0x4 0.--5. 1. "BORDER_COLOUR_TABLE_ADDRESS,Base address DWORD aligned for the location in memory of the border colour table for the VDM" line.long 0x8 "RGX_CR_TPU_BORDER_COLOUR_TABLE_CDM_0,Base address for the border colour table" hexmask.long 0x8 0.--31. 1. "BORDER_COLOUR_TABLE_ADDRESS,Base address DWORD aligned for the location in memory of the border colour table for the CDM" line.long 0xC "RGX_CR_TPU_BORDER_COLOUR_TABLE_CDM_1,Base address for the border colour table" hexmask.long 0xC 6.--31. 1. "Reserved_38,Reserved_38" newline hexmask.long.byte 0xC 0.--5. 1. "BORDER_COLOUR_TABLE_ADDRESS,Base address DWORD aligned for the location in memory of the border colour table for the CDM" repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) rgroup.long ($2+0x17B0)++0x3 line.long 0x0 "RGX_CR_TPU_PWR_NUMBER_OF_TEXELS_$1,Peformance counter associated with Power Monitoring." hexmask.long 0x0 0.--31. 1. "VALUE,Number of texels requested per clock" repeat.end group.long 0x17B8++0xF line.long 0x0 "RGX_CR_TPU_TAG_CTRL_0,Global control to TAG for the pixel data master" hexmask.long 0x0 4.--31. 1. "Reserved_4,Reserved_4" newline bitfld.long 0x0 3. "AF_RATIO_TRUNCATE_TO_INTEGER,0 current mode 1 clear the fractional part of the calculated AF ratio" "0,1" newline bitfld.long 0x0 2. "AF_RATIO_TRUNCATE_TO_HALF,0 current mode 1 truncate the fractional part of the calculated AF ratio to 0. 5" "0,1" newline bitfld.long 0x0 1. "AF_FILTERING_MODE,0 current mode 1 new mode." "0,1" newline bitfld.long 0x0 0. "YUV_CAM_INVALIDATE,When set will invalidate YUV CSC CAM to reset the CSC coefficients. It should be set when the TPU is not performing CSC." "0,1" line.long 0x4 "RGX_CR_TPU_TAG_CTRL_1,Global control to TAG for the pixel data master" hexmask.long 0x4 0.--31. 1. "Reserved_4,Reserved_4" line.long 0x8 "RGX_CR_TPU_MADD_CTRL_0,Global control to MADD for pixel data master" hexmask.long 0x8 2.--31. 1. "Reserved_2,Reserved_2" newline bitfld.long 0x8 1. "ASTC_ODD_SCALING_ENABLE,When set ASTC encoded texels use the odd U16->F16 scaling in the TF. When zero the usual scaling will be used in TF." "0,1" newline bitfld.long 0x8 0. "ASTC_MULTICYCLE_TF_FORCE_F16,When set ASTC encoded texels that are filtered over multiple cycles by the TF will be output from the MADD as F16." "0,1" line.long 0xC "RGX_CR_TPU_MADD_CTRL_1,Global control to MADD for pixel data master" hexmask.long 0xC 0.--31. 1. "Reserved_2,Reserved_2" group.long 0x17F0++0x7 line.long 0x0 "RGX_CR_TPU_BORDER_COLOUR_TABLE_TDM_0,Base address for the border colour table" hexmask.long 0x0 0.--31. 1. "BORDER_COLOUR_TABLE_ADDRESS,Base address DWORD aligned for the location in memory of the border colour table for the TDM" line.long 0x4 "RGX_CR_TPU_BORDER_COLOUR_TABLE_TDM_1,Base address for the border colour table" hexmask.long 0x4 6.--31. 1. "Reserved_38,Reserved_38" newline hexmask.long.byte 0x4 0.--5. 1. "BORDER_COLOUR_TABLE_ADDRESS,Base address DWORD aligned for the location in memory of the border colour table for the TDM" group.long 0x18C0++0x17 line.long 0x0 "RGX_CR_TPU_LODBIASREP_CMP_MANTISSA_MASK_PDM_0,Mask for comparing mantissa of f32 LOD Bias/Replace value for PPLOD speedup for the pixel data master" hexmask.long.word 0x0 23.--31. 1. "Reserved_23,Reserved_23" newline hexmask.long.tbyte 0x0 0.--22. 1. "LODBIASREP_CMP_MANTISSA_MASK,Mask for comparing mantissa of f32 LOD Bias/Replace value for PPLOD speedup" line.long 0x4 "RGX_CR_TPU_LODBIASREP_CMP_MANTISSA_MASK_PDM_1,Mask for comparing mantissa of f32 LOD Bias/Replace value for PPLOD speedup for the pixel data master" hexmask.long 0x4 0.--31. 1. "Reserved_23,Reserved_23" line.long 0x8 "RGX_CR_TPU_LODBIASREP_CMP_MANTISSA_MASK_VDM_0,Mask for comparing mantissa of f32 LOD Bias/Replace value for PPLOD speedup for the vertex data master" hexmask.long.word 0x8 23.--31. 1. "Reserved_23,Reserved_23" newline hexmask.long.tbyte 0x8 0.--22. 1. "LODBIASREP_CMP_MANTISSA_MASK,Mask for comparing mantissa of f32 LOD Bias/Replace value for PPLOD speedup" line.long 0xC "RGX_CR_TPU_LODBIASREP_CMP_MANTISSA_MASK_VDM_1,Mask for comparing mantissa of f32 LOD Bias/Replace value for PPLOD speedup for the vertex data master" hexmask.long 0xC 0.--31. 1. "Reserved_23,Reserved_23" line.long 0x10 "RGX_CR_TPU_LODBIASREP_CMP_MANTISSA_MASK_CDM_0,Mask for comparing mantissa of f32 LOD Bias/Replace value for PPLOD speedup for the compute data master" hexmask.long.word 0x10 23.--31. 1. "Reserved_23,Reserved_23" newline hexmask.long.tbyte 0x10 0.--22. 1. "LODBIASREP_CMP_MANTISSA_MASK,Mask for comparing mantissa of f32 LOD Bias/Replace value for PPLOD speedup" line.long 0x14 "RGX_CR_TPU_LODBIASREP_CMP_MANTISSA_MASK_CDM_1,Mask for comparing mantissa of f32 LOD Bias/Replace value for PPLOD speedup for the compute data master" hexmask.long 0x14 0.--31. 1. "Reserved_23,Reserved_23" group.long 0x18E0++0x7 line.long 0x0 "RGX_CR_TPU_LODBIASREP_CMP_MANTISSA_MASK_TDM_0,Mask for comparing mantissa of f32 LOD Bias/Replace value for PPLOD speedup for the fast render data master" hexmask.long.word 0x0 23.--31. 1. "Reserved_23,Reserved_23" newline hexmask.long.tbyte 0x0 0.--22. 1. "LODBIASREP_CMP_MANTISSA_MASK,Mask for comparing mantissa of f32 LOD Bias/Replace value for PPLOD speedup" line.long 0x4 "RGX_CR_TPU_LODBIASREP_CMP_MANTISSA_MASK_TDM_1,Mask for comparing mantissa of f32 LOD Bias/Replace value for PPLOD speedup for the fast render data master" hexmask.long 0x4 0.--31. 1. "Reserved_23,Reserved_23" rgroup.long 0x2000++0xF line.long 0x0 "RGX_CR_PM_TA_MMUPAGE_STATUS_0,RGX_CR_PM_TA_MMUPAGE_STATUS_0" hexmask.long.word 0x0 22.--31. 1. "Reserved_22,Reserved_22" newline hexmask.long.tbyte 0x0 0.--21. 1. "OP,MMU pages(4KB) counter @ the TA context" line.long 0x4 "RGX_CR_PM_TA_MMUPAGE_STATUS_1,RGX_CR_PM_TA_MMUPAGE_STATUS_1" hexmask.long 0x4 0.--31. 1. "Reserved_22,Reserved_22" line.long 0x8 "RGX_CR_PM_3D_MMUPAGE_STATUS_0,RGX_CR_PM_3D_MMUPAGE_STATUS_0" hexmask.long.word 0x8 22.--31. 1. "Reserved_22,Reserved_22" newline hexmask.long.tbyte 0x8 0.--21. 1. "OP,MMU pages(4KB) counter @ the 3D context" line.long 0xC "RGX_CR_PM_3D_MMUPAGE_STATUS_1,RGX_CR_PM_3D_MMUPAGE_STATUS_1" hexmask.long 0xC 0.--31. 1. "Reserved_22,Reserved_22" group.long 0x2010++0xF line.long 0x0 "RGX_CR_PM_MMU_STACK_POLICY_0,This register enables the PM to drain pages for MMU from the dedicated mmu free list stack. (no-pagable) It is static register which can not be changed in the run-time." hexmask.long 0x0 1.--31. 1. "Reserved_1,Reserved_1" newline bitfld.long 0x0 0. "OP,when this bit is '1' PM will try to drain pages from the dedicated mmu free list stack" "0,1" line.long 0x4 "RGX_CR_PM_MMU_STACK_POLICY_1,This register enables the PM to drain pages for MMU from the dedicated mmu free list stack. (no-pagable) It is static register which can not be changed in the run-time." hexmask.long 0x4 0.--31. 1. "Reserved_1,Reserved_1" line.long 0x8 "RGX_CR_PM_TA_MMU_FSTACK_BASE_0,Effective on loading of the MMU TA free list loading . this register defines the base address of the mmu free list stack being referenced during TA processing." hexmask.long 0x8 4.--31. 1. "ADDR,1TB Addressable 128 bits aligned Base Address for MMU TA free list stack" newline hexmask.long.byte 0x8 0.--3. 1. "Reserved_0,Reserved_0" line.long 0xC "RGX_CR_PM_TA_MMU_FSTACK_BASE_1,Effective on loading of the MMU TA free list loading . this register defines the base address of the mmu free list stack being referenced during TA processing." hexmask.long.tbyte 0xC 8.--31. 1. "Reserved_40,Reserved_40" newline hexmask.long.byte 0xC 0.--7. 1. "ADDR,1TB Addressable 128 bits aligned Base Address for MMU TA free list stack" rgroup.long 0x2020++0x7 line.long 0x0 "RGX_CR_PM_TA_MMU_FSTACK_STATUS_0,Note: this is the pointer pointing to the MMU TA free stack top. (4KB page pointer)" hexmask.long.word 0x0 22.--31. 1. "Reserved_22,Reserved_22" newline hexmask.long.tbyte 0x0 0.--21. 1. "TOP,This status register indicated the mmu ta context free list pointer status." line.long 0x4 "RGX_CR_PM_TA_MMU_FSTACK_STATUS_1,Note: this is the pointer pointing to the MMU TA free stack top. (4KB page pointer)" hexmask.long 0x4 0.--31. 1. "Reserved_22,Reserved_22" group.long 0x2028++0x1F line.long 0x0 "RGX_CR_PM_TA_MMU_FSTACK_0,Defines the start of the stack pointer regarding to the MMU free list stack" hexmask.long.word 0x0 22.--31. 1. "Reserved_22,Reserved_22" newline hexmask.long.tbyte 0x0 0.--21. 1. "STARTOF_TOP,This register defines the head pointer of the mmu free list in terms of 4K free pages in the free list stack effective on a loading of the MMU TA free list" line.long 0x4 "RGX_CR_PM_TA_MMU_FSTACK_1,Defines the start of the stack pointer regarding to the MMU free list stack" hexmask.long 0x4 0.--31. 1. "Reserved_22,Reserved_22" line.long 0x8 "RGX_CR_PM_START_OF_MMU_TACONTEXT_0,RGX_CR_PM_START_OF_MMU_TACONTEXT_0" hexmask.long.word 0x8 22.--31. 1. "Reserved_22,Reserved_22" newline hexmask.long.tbyte 0x8 0.--21. 1. "ALLOCATED_MMUPAGE,Start of MMU Freelists TA pages(4KB) on loading of the MMU TA context" line.long 0xC "RGX_CR_PM_START_OF_MMU_TACONTEXT_1,RGX_CR_PM_START_OF_MMU_TACONTEXT_1" hexmask.long 0xC 0.--31. 1. "Reserved_22,Reserved_22" line.long 0x10 "RGX_CR_PM_TASK_TA_MMU_FSTACK_FREE_LOAD_0,RGX_CR_PM_TASK_TA_MMU_FSTACK_FREE_LOAD_0" hexmask.long 0x10 1.--31. 1. "Reserved_1,Reserved_1" newline bitfld.long 0x10 0. "PENDING,A write into this register will cause the TA MMU free list context to be loaded from the relevant configuration registers" "0,1" line.long 0x14 "RGX_CR_PM_TASK_TA_MMU_FSTACK_FREE_LOAD_1,RGX_CR_PM_TASK_TA_MMU_FSTACK_FREE_LOAD_1" hexmask.long 0x14 0.--31. 1. "Reserved_1,Reserved_1" line.long 0x18 "RGX_CR_PM_3D_MMU_FSTACK_BASE_0,Effective on loading of the MMU 3D free list loading . this register defines the base address of the mmu free list stack being referenced during 3D processing." hexmask.long 0x18 4.--31. 1. "ADDR,1TB Addressable 128 bits aligned Base Address for MMU TA free list stack" newline hexmask.long.byte 0x18 0.--3. 1. "Reserved_0,Reserved_0" line.long 0x1C "RGX_CR_PM_3D_MMU_FSTACK_BASE_1,Effective on loading of the MMU 3D free list loading . this register defines the base address of the mmu free list stack being referenced during 3D processing." hexmask.long.tbyte 0x1C 8.--31. 1. "Reserved_40,Reserved_40" newline hexmask.long.byte 0x1C 0.--7. 1. "ADDR,1TB Addressable 128 bits aligned Base Address for MMU TA free list stack" rgroup.long 0x2048++0x7 line.long 0x0 "RGX_CR_PM_3D_MMU_FSTACK_STATUS_0,Note: this is the pointer pointing to the MMU TA free stack top. (4KB page pointer)" hexmask.long.word 0x0 22.--31. 1. "Reserved_22,Reserved_22" newline hexmask.long.tbyte 0x0 0.--21. 1. "TOP,This status register indicated the mmu ta context free list pointer status." line.long 0x4 "RGX_CR_PM_3D_MMU_FSTACK_STATUS_1,Note: this is the pointer pointing to the MMU TA free stack top. (4KB page pointer)" hexmask.long 0x4 0.--31. 1. "Reserved_22,Reserved_22" group.long 0x2050++0x17 line.long 0x0 "RGX_CR_PM_3D_MMU_FSTACK_0,Defines the start of the stack pointer regarding to the MMU free list stack Effective on a 3D MMU fstack load" hexmask.long.word 0x0 22.--31. 1. "Reserved_22,Reserved_22" newline hexmask.long.tbyte 0x0 0.--21. 1. "STARTOF_TOP,This register defines the head pointer of the mmu free list in terms of 4K free pages in the free list stack effective on a loading of the MMU TA free list" line.long 0x4 "RGX_CR_PM_3D_MMU_FSTACK_1,Defines the start of the stack pointer regarding to the MMU free list stack Effective on a 3D MMU fstack load" hexmask.long 0x4 0.--31. 1. "Reserved_22,Reserved_22" line.long 0x8 "RGX_CR_PM_START_OF_MMU_3DCONTEXT_0,Effective on a 3D MMU fstack load" hexmask.long.word 0x8 22.--31. 1. "Reserved_22,Reserved_22" newline hexmask.long.tbyte 0x8 0.--21. 1. "ALLOCATED_MMUPAGE,Start of MMU Freelists 3D pages(4KB) on loading of the MMU TA context" line.long 0xC "RGX_CR_PM_START_OF_MMU_3DCONTEXT_1,Effective on a 3D MMU fstack load" hexmask.long 0xC 0.--31. 1. "Reserved_22,Reserved_22" line.long 0x10 "RGX_CR_PM_TASK_3D_MMU_FSTACK_FREE_LOAD_0,RGX_CR_PM_TASK_3D_MMU_FSTACK_FREE_LOAD_0" hexmask.long 0x10 1.--31. 1. "Reserved_1,Reserved_1" newline bitfld.long 0x10 0. "PENDING,A write into this register will cause the 3D MMU free list context to be loaded from the relevant configuration registers" "0,1" line.long 0x14 "RGX_CR_PM_TASK_3D_MMU_FSTACK_FREE_LOAD_1,RGX_CR_PM_TASK_3D_MMU_FSTACK_FREE_LOAD_1" hexmask.long 0x14 0.--31. 1. "Reserved_1,Reserved_1" rgroup.long 0x2068++0xF line.long 0x0 "RGX_CR_PM_MMUSTACK_LOCK_STATUS_0,RGX_CR_PM_MMUSTACK_LOCK_STATUS_0" hexmask.long 0x0 2.--31. 1. "Reserved_2,Reserved_2" newline bitfld.long 0x0 1. "TD,Bit 1: 3D MMU free list Lock Status. 0 idle/ 1 used" "0,1" newline bitfld.long 0x0 0. "TA,Bit 0: TA MMU free list Lock Status. 0 idle/ 1 used." "TA MMU free list Lock Status,?" line.long 0x4 "RGX_CR_PM_MMUSTACK_LOCK_STATUS_1,RGX_CR_PM_MMUSTACK_LOCK_STATUS_1" hexmask.long 0x4 0.--31. 1. "Reserved_2,Reserved_2" line.long 0x8 "RGX_CR_PM_MMUSTACK_LOCK_OWNER_0,RGX_CR_PM_MMUSTACK_LOCK_OWNER_0" hexmask.long 0x8 2.--31. 1. "Reserved_2,Reserved_2" newline bitfld.long 0x8 1. "TD,Bit 1 :3D free list Lock owner. 0 PMA / 1 PMD" "0,1" newline bitfld.long 0x8 0. "TA,Bit 0: TA free list Lock Owner. 0 PMA / 1 PMD." "TA free list Lock Owner,?" line.long 0xC "RGX_CR_PM_MMUSTACK_LOCK_OWNER_1,RGX_CR_PM_MMUSTACK_LOCK_OWNER_1" hexmask.long 0xC 0.--31. 1. "Reserved_2,Reserved_2" group.long 0x2078++0xF line.long 0x0 "RGX_CR_PM_3D_UFSTACK_BASE_0,Effective on load of the Unified Free List Stack. this register defines the base address of the unified free list stack being referenced." hexmask.long 0x0 4.--31. 1. "ADDR,1TB Addressable 128 bits aligned Base Address for unified free list stack base address" newline hexmask.long.byte 0x0 0.--3. 1. "Reserved_0,Reserved_0" line.long 0x4 "RGX_CR_PM_3D_UFSTACK_BASE_1,Effective on load of the Unified Free List Stack. this register defines the base address of the unified free list stack being referenced." hexmask.long.tbyte 0x4 8.--31. 1. "Reserved_40,Reserved_40" newline hexmask.long.byte 0x4 0.--7. 1. "ADDR,1TB Addressable 128 bits aligned Base Address for unified free list stack base address" line.long 0x8 "RGX_CR_PM_3D_UFSTACK_0,Note: each 16GB 4KB addressable page (22 bits) is rounded to dword aligned Effective on load of the Unified Free List Stack." hexmask.long.word 0x8 22.--31. 1. "Reserved_22,Reserved_22" newline hexmask.long.tbyte 0x8 0.--21. 1. "STARTOF_TOP,This register defines the unified free list stack pointer @ loading time. It is 4K page." line.long 0xC "RGX_CR_PM_3D_UFSTACK_1,Note: each 16GB 4KB addressable page (22 bits) is rounded to dword aligned Effective on load of the Unified Free List Stack." hexmask.long 0xC 0.--31. 1. "Reserved_22,Reserved_22" rgroup.long 0x2088++0x7 line.long 0x0 "RGX_CR_PM_3D_UFSTACK_STATUS_0,Note: this is the pointer pointing to the ufstack top. (4KB page pointer)" hexmask.long.word 0x0 22.--31. 1. "Reserved_22,Reserved_22" newline hexmask.long.tbyte 0x0 0.--21. 1. "TOP,This status register indicated the unified free list stack pointer status." line.long 0x4 "RGX_CR_PM_3D_UFSTACK_STATUS_1,Note: this is the pointer pointing to the ufstack top. (4KB page pointer)" hexmask.long 0x4 0.--31. 1. "Reserved_22,Reserved_22" repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) group.long ($2+0x2090)++0x3 line.long 0x0 "RGX_CR_PM_START_OF_3D_UFSTACK_$1,Effective on load of the Unified Free List Stack." hexmask.long.word 0x0 22.--31. 1. "Reserved_22,Reserved_22" newline hexmask.long.tbyte 0x0 0.--21. 1. "ALLOCATED_PAGE,Start of TA pages(4KB) on loading of the Unified Free List Stack" repeat.end rgroup.long 0x2098++0xF line.long 0x0 "RGX_CR_PM_3D_UFSTACK_PAGE_STATUS_0,RGX_CR_PM_3D_UFSTACK_PAGE_STATUS_0" hexmask.long.word 0x0 22.--31. 1. "Reserved_22,Reserved_22" newline hexmask.long.tbyte 0x0 0.--21. 1. "OP,The number of Unified Free list pages currently allocated for the TA" line.long 0x4 "RGX_CR_PM_3D_UFSTACK_PAGE_STATUS_1,RGX_CR_PM_3D_UFSTACK_PAGE_STATUS_1" hexmask.long 0x4 0.--31. 1. "Reserved_22,Reserved_22" line.long 0x8 "RGX_CR_PM_3D_UFSTACK_MMUPAGE_STATUS_0,RGX_CR_PM_3D_UFSTACK_MMUPAGE_STATUS_0" hexmask.long.word 0x8 22.--31. 1. "Reserved_22,Reserved_22" newline hexmask.long.tbyte 0x8 0.--21. 1. "OP,The number of Unified Free list pages currently allocated for the MMU" line.long 0xC "RGX_CR_PM_3D_UFSTACK_MMUPAGE_STATUS_1,RGX_CR_PM_3D_UFSTACK_MMUPAGE_STATUS_1" hexmask.long 0xC 0.--31. 1. "Reserved_22,Reserved_22" group.long 0x20A8++0x1F line.long 0x0 "RGX_CR_PM_TASK_3D_UFSTACK_LOAD_0,RGX_CR_PM_TASK_3D_UFSTACK_LOAD_0" hexmask.long 0x0 1.--31. 1. "Reserved_1,Reserved_1" newline bitfld.long 0x0 0. "PENDING,pending status register corresponding to the ustack loading operation it will become '1' when this pm_task_ufstack_load being written and deassert until the operation is done" "0,1" line.long 0x4 "RGX_CR_PM_TASK_3D_UFSTACK_LOAD_1,RGX_CR_PM_TASK_3D_UFSTACK_LOAD_1" hexmask.long 0x4 0.--31. 1. "Reserved_1,Reserved_1" line.long 0x8 "RGX_CR_PM_TASK_TA_UFSTACK_LOAD_0,RGX_CR_PM_TASK_TA_UFSTACK_LOAD_0" hexmask.long 0x8 1.--31. 1. "Reserved_1,Reserved_1" newline bitfld.long 0x8 0. "PENDING,pending status register corresponding to the ustack loading operation it will become '1' when this pm_task_ufstack_load being written and deassert until the operation is done" "0,1" line.long 0xC "RGX_CR_PM_TASK_TA_UFSTACK_LOAD_1,RGX_CR_PM_TASK_TA_UFSTACK_LOAD_1" hexmask.long 0xC 0.--31. 1. "Reserved_1,Reserved_1" line.long 0x10 "RGX_CR_PM_TA_UFSTACK_BASE_0,Effective on load of the Unified Free List Stack. this register defines the base address of the unified free list stack being referenced." hexmask.long 0x10 4.--31. 1. "ADDR,1TB Addressable 128 bits aligned Base Address for unified free list stack base address" newline hexmask.long.byte 0x10 0.--3. 1. "Reserved_0,Reserved_0" line.long 0x14 "RGX_CR_PM_TA_UFSTACK_BASE_1,Effective on load of the Unified Free List Stack. this register defines the base address of the unified free list stack being referenced." hexmask.long.tbyte 0x14 8.--31. 1. "Reserved_40,Reserved_40" newline hexmask.long.byte 0x14 0.--7. 1. "ADDR,1TB Addressable 128 bits aligned Base Address for unified free list stack base address" line.long 0x18 "RGX_CR_PM_TA_UFSTACK_0,Note: each 16GB 4KB addressable page (22 bits) is rounded to dword aligned Effective on the loading of the Unified Free List Stack." hexmask.long.word 0x18 22.--31. 1. "Reserved_22,Reserved_22" newline hexmask.long.tbyte 0x18 0.--21. 1. "STARTOF_TOP,This register defines the unified free list stack pointer @ loading time. It is 4K page." line.long 0x1C "RGX_CR_PM_TA_UFSTACK_1,Note: each 16GB 4KB addressable page (22 bits) is rounded to dword aligned Effective on the loading of the Unified Free List Stack." hexmask.long 0x1C 0.--31. 1. "Reserved_22,Reserved_22" rgroup.long 0x20C8++0x7 line.long 0x0 "RGX_CR_PM_TA_UFSTACK_STATUS_0,Note: this is the pointer pointing to the ufstack top. (4KB page pointer)" hexmask.long.word 0x0 22.--31. 1. "Reserved_22,Reserved_22" newline hexmask.long.tbyte 0x0 0.--21. 1. "TOP,This status register indicated the unified free list stack pointer status." line.long 0x4 "RGX_CR_PM_TA_UFSTACK_STATUS_1,Note: this is the pointer pointing to the ufstack top. (4KB page pointer)" hexmask.long 0x4 0.--31. 1. "Reserved_22,Reserved_22" repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) group.long ($2+0x20D0)++0x3 line.long 0x0 "RGX_CR_PM_START_OF_TA_UFSTACK_$1,RGX_CR_PM_START_OF_TA_UFSTACK_0" hexmask.long.word 0x0 22.--31. 1. "Reserved_22,Reserved_22" newline hexmask.long.tbyte 0x0 0.--21. 1. "ALLOCATED_PAGE,Start of TA pages(4KB) on loading of the Unified Free List Stack" repeat.end rgroup.long 0x20D8++0x1F line.long 0x0 "RGX_CR_PM_TA_UFSTACK_PAGE_STATUS_0,RGX_CR_PM_TA_UFSTACK_PAGE_STATUS_0" hexmask.long.word 0x0 22.--31. 1. "Reserved_22,Reserved_22" newline hexmask.long.tbyte 0x0 0.--21. 1. "OP,The number of Unified Free list pages currently allocated for the TA" line.long 0x4 "RGX_CR_PM_TA_UFSTACK_PAGE_STATUS_1,RGX_CR_PM_TA_UFSTACK_PAGE_STATUS_1" hexmask.long 0x4 0.--31. 1. "Reserved_22,Reserved_22" line.long 0x8 "RGX_CR_PM_TA_UFSTACK_MMUPAGE_STATUS_0,RGX_CR_PM_TA_UFSTACK_MMUPAGE_STATUS_0" hexmask.long.word 0x8 22.--31. 1. "Reserved_22,Reserved_22" newline hexmask.long.tbyte 0x8 0.--21. 1. "OP,The number of Unified Free list pages currently allocated for the MMU" line.long 0xC "RGX_CR_PM_TA_UFSTACK_MMUPAGE_STATUS_1,RGX_CR_PM_TA_UFSTACK_MMUPAGE_STATUS_1" hexmask.long 0xC 0.--31. 1. "Reserved_22,Reserved_22" line.long 0x10 "RGX_CR_PM_UFSTACK_LOCK_STATUS_0,In rogue architecture. there is a unified free list whereby shared across multiple context. This lock status indicating the stack owner at the time being. Note PMA and PMD can not acquire the lock @ the same time" hexmask.long 0x10 2.--31. 1. "Reserved_2,Reserved_2" newline bitfld.long 0x10 1. "PMD,Bit 1: Page DeAllocation Manger is grabing the lock. 0:idle/ 1 used." "idle/ 1 used,Page DeAllocation Manger is grabing the lock" newline bitfld.long 0x10 0. "PMA,Bit 0: Page Allocation Manger is grabing the lock. 0:idle/ 1 used." "idle/ 1 used,?" line.long 0x14 "RGX_CR_PM_UFSTACK_LOCK_STATUS_1,In rogue architecture. there is a unified free list whereby shared across multiple context. This lock status indicating the stack owner at the time being. Note PMA and PMD can not acquire the lock @ the same time" hexmask.long 0x14 0.--31. 1. "Reserved_2,Reserved_2" line.long 0x18 "RGX_CR_PM_UFSTACK_LOCK_OWNER_0,RGX_CR_PM_UFSTACK_LOCK_OWNER_0" hexmask.long 0x18 2.--31. 1. "Reserved_2,Reserved_2" newline bitfld.long 0x18 1. "TD,Bit 1 :3D free list Lock owner. 0 PMA / 1 PMD" "0,1" newline bitfld.long 0x18 0. "TA,Bit 0: TA free list Lock Owner. 0 PMA / 1 PMD." "TA free list Lock Owner,?" line.long 0x1C "RGX_CR_PM_UFSTACK_LOCK_OWNER_1,RGX_CR_PM_UFSTACK_LOCK_OWNER_1" hexmask.long 0x1C 0.--31. 1. "Reserved_2,Reserved_2" group.long 0x20F8++0x1F line.long 0x0 "RGX_CR_PM_UFSTACK_POLICY_0,This register enables the PM to drain pages from the unified free list stack It is a static configuration register" hexmask.long 0x0 1.--31. 1. "Reserved_1,Reserved_1" newline bitfld.long 0x0 0. "OP,when this bit is '1' PM will try to drain pages from the unified free list stack as long as the ta free list do not have enough pages for the allocation" "0,1" line.long 0x4 "RGX_CR_PM_UFSTACK_POLICY_1,This register enables the PM to drain pages from the unified free list stack It is a static configuration register" hexmask.long 0x4 0.--31. 1. "Reserved_1,Reserved_1" line.long 0x8 "RGX_CR_PM_VFP_TRAN_EN_0,This register enables the PM to another level of transfrom which is from Virtial Page to VirtualPhysical Page number" hexmask.long 0x8 1.--31. 1. "Reserved_1,Reserved_1" newline bitfld.long 0x8 0. "OP,when this bit is '1' PM will try to another level of lookup between virtual page and the virtual physical page" "0,1" line.long 0xC "RGX_CR_PM_VFP_TRAN_EN_1,This register enables the PM to another level of transfrom which is from Virtial Page to VirtualPhysical Page number" hexmask.long 0xC 0.--31. 1. "Reserved_1,Reserved_1" line.long 0x10 "RGX_CR_PM_TA_VFP_TABLE_BASE_0,Effective on loading TA context. this register defines the base address of the virtual-physical page table during TA processing." hexmask.long 0x10 4.--31. 1. "ADDR,1TB Addressable 128 bits aligned Base Address for TA context page tables in the DPM module" newline hexmask.long.byte 0x10 0.--3. 1. "Reserved_0,Reserved_0" line.long 0x14 "RGX_CR_PM_TA_VFP_TABLE_BASE_1,Effective on loading TA context. this register defines the base address of the virtual-physical page table during TA processing." hexmask.long.tbyte 0x14 8.--31. 1. "Reserved_40,Reserved_40" newline hexmask.long.byte 0x14 0.--7. 1. "ADDR,1TB Addressable 128 bits aligned Base Address for TA context page tables in the DPM module" line.long 0x18 "RGX_CR_PM_3D_VFP_TABLE_BASE_0,Effective on loading 3D context. this register defines the base address of the virtual-physical page table during 3D processing." hexmask.long 0x18 4.--31. 1. "ADDR,1TB Addressable 128 bits aligned Base Address for 3D context page tables in the DPM module" newline hexmask.long.byte 0x18 0.--3. 1. "Reserved_0,Reserved_0" line.long 0x1C "RGX_CR_PM_3D_VFP_TABLE_BASE_1,Effective on loading 3D context. this register defines the base address of the virtual-physical page table during 3D processing." hexmask.long.tbyte 0x1C 8.--31. 1. "Reserved_40,Reserved_40" newline hexmask.long.byte 0x1C 0.--7. 1. "ADDR,1TB Addressable 128 bits aligned Base Address for 3D context page tables in the DPM module" wgroup.long 0x2600++0x7 line.long 0x0 "RGX_CR_TDM_START_0,A write of '1' to this register starts the 2D Data Master (TDM) reading the control stream contained in the circular buffer pointed to by TDM_CB_BASE_ADDR" hexmask.long 0x0 1.--31. 1. "Reserved_1,Reserved_1" newline bitfld.long 0x0 0. "PULSE,Start TDM" "0,1" line.long 0x4 "RGX_CR_TDM_START_1,A write of '1' to this register starts the 2D Data Master (TDM) reading the control stream contained in the circular buffer pointed to by TDM_CB_BASE_ADDR" hexmask.long 0x4 0.--31. 1. "Reserved_1,Reserved_1" group.long 0x2608++0x27 line.long 0x0 "RGX_CR_TDM_CB_BASE_0,TDM Circular Buffer base dddress" hexmask.long.tbyte 0x0 12.--31. 1. "ADDR,1 TB range 4KB aligned base address for TDM control stream circular buffer" newline hexmask.long.word 0x0 0.--11. 1. "Reserved_0,Reserved_0" line.long 0x4 "RGX_CR_TDM_CB_BASE_1,TDM Circular Buffer base dddress" hexmask.long.tbyte 0x4 8.--31. 1. "Reserved_40,Reserved_40" newline hexmask.long.byte 0x4 0.--7. 1. "ADDR,1 TB range 4KB aligned base address for TDM control stream circular buffer" line.long 0x8 "RGX_CR_TDM_CB_0,TDM Circular Buffer Size in 256-bit words" hexmask.long.word 0x8 20.--31. 1. "Reserved_20,Reserved_20" newline hexmask.long.word 0x8 5.--19. 1. "SIZE,1MB range 256-bit granular TDM Circular Buffer Size" newline hexmask.long.byte 0x8 0.--4. 1. "Reserved_0,Reserved_0" line.long 0xC "RGX_CR_TDM_CB_1,TDM Circular Buffer Size in 256-bit words" hexmask.long 0xC 0.--31. 1. "Reserved_20,Reserved_20" line.long 0x10 "RGX_CR_TDM_CB_QUEUE_0,TDM Circular Buffer Queue Control Base Address" hexmask.long 0x10 5.--31. 1. "CTRL_BASE_ADDR,1 TB range 256-bit aligned base address for TDM queue control structure" newline hexmask.long.byte 0x10 0.--4. 1. "Reserved_0,Reserved_0" line.long 0x14 "RGX_CR_TDM_CB_QUEUE_1,TDM Circular Buffer Queue Control Base Address" hexmask.long.tbyte 0x14 8.--31. 1. "Reserved_40,Reserved_40" newline hexmask.long.byte 0x14 0.--7. 1. "CTRL_BASE_ADDR,1 TB range 256-bit aligned base address for TDM queue control structure" line.long 0x18 "RGX_CR_TDM_CB_WRITE_POINTER_GUARD_0,TDM Circular Buffer Write Pointer Guard Size. TDM will refresh it's local copy of the Queue Control Write Pointer from memory when the Read Pointer is within the Guard Size of the Write Pointer." hexmask.long.word 0x18 20.--31. 1. "Reserved_20,Reserved_20" newline hexmask.long.word 0x18 5.--19. 1. "SIZE,1MB range 256-bit granular Write Pointer Guard Size" newline hexmask.long.byte 0x18 0.--4. 1. "Reserved_0,Reserved_0" line.long 0x1C "RGX_CR_TDM_CB_WRITE_POINTER_GUARD_1,TDM Circular Buffer Write Pointer Guard Size. TDM will refresh it's local copy of the Queue Control Write Pointer from memory when the Read Pointer is within the Guard Size of the Write Pointer." hexmask.long 0x1C 0.--31. 1. "Reserved_20,Reserved_20" line.long 0x20 "RGX_CR_TDM_CB_READ_POINTER_UPDATE_0,TDM Circular Buffer Read Pointer Update Frequency. the TDM will update the Queue Control Read Pointer value in memory whenever the Read Pointer has moved by this amount since the last memory write." hexmask.long.word 0x20 20.--31. 1. "Reserved_20,Reserved_20" newline hexmask.long.word 0x20 5.--19. 1. "FREQUENCY,1MB range 256-bit granular Read Pointer Update Frequency" newline hexmask.long.byte 0x20 0.--4. 1. "Reserved_0,Reserved_0" line.long 0x24 "RGX_CR_TDM_CB_READ_POINTER_UPDATE_1,TDM Circular Buffer Read Pointer Update Frequency. the TDM will update the Queue Control Read Pointer value in memory whenever the Read Pointer has moved by this amount since the last memory write." hexmask.long 0x24 0.--31. 1. "Reserved_20,Reserved_20" rgroup.long 0x2630++0x7 line.long 0x0 "RGX_CR_TDM_CB_READ_0,TDM Circular Buffer Read Pointer - current working position of TDM within 2D circular buffer. updated on a BLIT granularity" hexmask.long.word 0x0 20.--31. 1. "Reserved_20,Reserved_20" newline hexmask.long.tbyte 0x0 2.--19. 1. "POINTER,1MB range 32-bit granular Read Pointer" newline bitfld.long 0x0 0.--1. "Reserved_0,Reserved_0" "0,1,2,3" line.long 0x4 "RGX_CR_TDM_CB_READ_1,TDM Circular Buffer Read Pointer - current working position of TDM within 2D circular buffer. updated on a BLIT granularity" hexmask.long 0x4 0.--31. 1. "Reserved_20,Reserved_20" wgroup.long 0x2638++0xF line.long 0x0 "RGX_CR_TDM_RESUME_0,A write of '1' to this register resumes the TDM after 2D circular buffer empty failures." hexmask.long 0x0 1.--31. 1. "Reserved_1,Reserved_1" newline bitfld.long 0x0 0. "PULSE,Resume TDM" "0,1" line.long 0x4 "RGX_CR_TDM_RESUME_1,A write of '1' to this register resumes the TDM after 2D circular buffer empty failures." hexmask.long 0x4 0.--31. 1. "Reserved_1,Reserved_1" line.long 0x8 "RGX_CR_TDM_CONTEXT_STORE_0,Writing '1' to this register starts the TDM context store operation." hexmask.long 0x8 1.--31. 1. "Reserved_1,Reserved_1" newline bitfld.long 0x8 0. "PULSE,PULSE" "0,1" line.long 0xC "RGX_CR_TDM_CONTEXT_STORE_1,Writing '1' to this register starts the TDM context store operation." hexmask.long 0xC 0.--31. 1. "Reserved_1,Reserved_1" group.long 0x2648++0x7 line.long 0x0 "RGX_CR_TDM_CONTEXT_STATE_BASE_0,The base address in external memory of the TDM's context state buffer. to which it will store its snapshot state on a context store and from which it will reload on a TDM start pulse." hexmask.long 0x0 6.--31. 1. "ADDR,1TB range 512-bit aligned base address" newline hexmask.long.byte 0x0 0.--5. 1. "Reserved_0,Reserved_0" line.long 0x4 "RGX_CR_TDM_CONTEXT_STATE_BASE_1,The base address in external memory of the TDM's context state buffer. to which it will store its snapshot state on a context store and from which it will reload on a TDM start pulse." hexmask.long.tbyte 0x4 8.--31. 1. "Reserved_40,Reserved_40" newline hexmask.long.byte 0x4 0.--7. 1. "ADDR,1TB range 512-bit aligned base address" repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) rgroup.long ($2+0x2650)++0x3 line.long 0x0 "RGX_CR_TDM_FENCE_$1,TDM fence counters" hexmask.long 0x0 0.--31. 1. "COUNT,Count of the number of fence received reset to 0 on TDM_START_PULSE" repeat.end group.long 0x2658++0x7 line.long 0x0 "RGX_CR_TDM_YUV_CSC_COEFFICIENTS_0,Base address for the YUV CSC set of coefficients stored in memory for pixel data master" hexmask.long 0x0 0.--31. 1. "COEFFICIENTS,Base address DWORD aligned for the location in memory of the CSC coefficients" line.long 0x4 "RGX_CR_TDM_YUV_CSC_COEFFICIENTS_1,Base address for the YUV CSC set of coefficients stored in memory for pixel data master" hexmask.long 0x4 6.--31. 1. "Reserved_38,Reserved_38" newline hexmask.long.byte 0x4 0.--5. 1. "COEFFICIENTS,Base address DWORD aligned for the location in memory of the CSC coefficients" group.long 0x2678++0x7 line.long 0x0 "RGX_CR_TDM_WORKLOAD_0,TDM workload priority policy." hexmask.long 0x0 2.--31. 1. "Reserved_2,Reserved_2" newline bitfld.long 0x0 0.--1. "PRIORITY,0: Equal priority; 1: 3D has priority; 2: TDM has priority; 3: Reserved" "Equal priority;,?,TDM has priority;,Reserved" line.long 0x4 "RGX_CR_TDM_WORKLOAD_1,TDM workload priority policy." hexmask.long 0x4 0.--31. 1. "Reserved_2,Reserved_2" group.long 0x3800++0x7 line.long 0x0 "RGX_CR_SLC_CTRL_MISC_0,SLC control registers" hexmask.long.byte 0x0 24.--31. 1. "Reserved_24,Reserved_24" newline hexmask.long.byte 0x0 16.--23. 1. "ADDR_DECODE_MODE,Address decoding used to determine cache bank from the address: 0x00 = Bit 6 = 64 byte 0x01 = Bit 7 = 128 byte 0x10 = Simple XOR based address hash 1 see SLC TRM 0x11 = Simple XOR based address hash 2 see SLC TRM 0x20 = PVR address.." newline hexmask.long.byte 0x0 9.--15. 1. "Reserved_9,Reserved_9" newline bitfld.long 0x0 8. "PAUSE,Pause the SLC" "0,1" newline hexmask.long.byte 0x0 4.--7. 1. "Reserved_4,Reserved_4" newline bitfld.long 0x0 3. "RESP_PRIORITY,Priority setting between Hit and Miss on return response. Default is round robin and set to 1 if miss needs priority over hit" "0,1" newline bitfld.long 0x0 2. "ENABLE_LINE_USE_LIMIT,Enable the use of cache line limits" "0,1" newline bitfld.long 0x0 1. "ENABLE_PSG_HAZARD_CHECK,Enable the hazard checking of PSG writes only turn off if strict write ordering is guaranteed in the memory fabric" "0,1" newline bitfld.long 0x0 0. "BYPASS_BURST_COMBINER,Disable the burst combiner on the external memory interface" "0,1" line.long 0x4 "RGX_CR_SLC_CTRL_MISC_1,SLC control registers" hexmask.long 0x4 0.--31. 1. "SCRAMBLE_BITS,Pattern of bits used to determine the Cache Bank in Address Decode mode 0x21. The actual Cache Bank to use is determined by indexing into the 32 Scramble Bits using the 5 LSB's of the Hash result and then XORing this with Bit 6 of the.." wgroup.long 0x3808++0x17 line.long 0x0 "RGX_CR_SLC_CTRL_INVAL_0,SLC Invalidate control. Note that per Data Master operations only invalidate entries that have been referenced solely by the specified Data Master. any cache lines referenced by multiple Data Masters will not be affected by a per.." bitfld.long 0x0 31. "LAZY,Advanced mode of operation whereby other requestors are not blocked whilst the Invalidate is in progress" "0,1" newline hexmask.long.tbyte 0x0 9.--30. 1. "Reserved_9,Reserved_9" newline bitfld.long 0x0 8. "DM_FRC,When set invalidate all SLC entries referenced solely by the FRC Video Core (Optional feature)" "0,1" newline bitfld.long 0x0 7. "DM_VXE,When set invalidate all SLC entries referenced solely by the VXE Video Core (Optional feature)" "0,1" newline bitfld.long 0x0 6. "DM_VXD,When set invalidate all SLC entries referenced solely by the VXD Video Core (Optional feature)" "0,1" newline bitfld.long 0x0 5. "DM_HOST_META,When set invalidate all SLC entries referenced solely by the HOST or META" "0,1" newline bitfld.long 0x0 4. "DM_MMU,When set invalidate all SLC entries referenced solely by the MMU" "0,1" newline bitfld.long 0x0 3. "DM_COMPUTE,When set invalidate all SLC entries referenced solely by the COMPUTE data master" "0,1" newline bitfld.long 0x0 2. "DM_PIXEL,When set invalidate all SLC entries referenced solely by the PIXEL data master" "0,1" newline bitfld.long 0x0 1. "DM_TA,When set invalidate all SLC entries referenced solely by the TA group which includes VERTEX TESSELLATOR & STREAM_OUT data masters" "0,1" newline bitfld.long 0x0 0. "ALL,When set invalidate all SLC entries" "0,1" line.long 0x4 "RGX_CR_SLC_CTRL_INVAL_1,SLC Invalidate control. Note that per Data Master operations only invalidate entries that have been referenced solely by the specified Data Master. any cache lines referenced by multiple Data Masters will not be affected by a per.." hexmask.long 0x4 0.--31. 1. "Reserved_32,Reserved_32" line.long 0x8 "RGX_CR_SLC_CTRL_FLUSH_0,SLC Flush control. Note that per Data Master operations will flush any cache lines that have been made dirty by any writes from the specified Data Master." bitfld.long 0x8 31. "LAZY,Advanced mode of operation whereby other requestors are not blocked whilst the Flush is in progress" "0,1" newline hexmask.long.tbyte 0x8 9.--30. 1. "Reserved_9,Reserved_9" newline bitfld.long 0x8 8. "DM_FRC,When set flush all SLC entries made dirty by the FRC Video Core (Optional feature)" "0,1" newline bitfld.long 0x8 7. "DM_VXE,When set flush all SLC entries made dirty by the VXE Video Core (Optional feature)" "0,1" newline bitfld.long 0x8 6. "DM_VXD,When set flush all SLC entries made dirty by the VXD Video Core (Optional feature)" "0,1" newline bitfld.long 0x8 5. "DM_HOST_META,When set flush all SLC entries made dirty by the HOST or META" "0,1" newline bitfld.long 0x8 4. "DM_MMU,When set flush all SLC entries made dirty by the MMU" "0,1" newline bitfld.long 0x8 3. "DM_COMPUTE,When set flush all SLC entries made dirty by the COMPUTE data master" "0,1" newline bitfld.long 0x8 2. "DM_PIXEL,When set flush all SLC entries made dirty by the PIXEL data master" "0,1" newline bitfld.long 0x8 1. "DM_TA,When set flush all SLC entries made dirty by the TA group which includes VERTEX TESSELLATOR & STREAM_OUT data masters" "0,1" newline bitfld.long 0x8 0. "ALL,When set flush all SLC entries" "0,1" line.long 0xC "RGX_CR_SLC_CTRL_FLUSH_1,SLC Flush control. Note that per Data Master operations will flush any cache lines that have been made dirty by any writes from the specified Data Master." hexmask.long 0xC 0.--31. 1. "Reserved_32,Reserved_32" line.long 0x10 "RGX_CR_SLC_CTRL_FLUSH_INVAL_0,SLC Flush & Invalidate control. Note that per Data Master operations will flush any cache lines that have been made dirty by any writes from the specified Data Master. Combined Invalidate operation then only invalidates.." bitfld.long 0x10 31. "LAZY,Advanced mode of operation whereby other requestors are not blocked whilst the Flush Invalidate is in progress" "0,1" newline hexmask.long.tbyte 0x10 9.--30. 1. "Reserved_9,Reserved_9" newline bitfld.long 0x10 8. "DM_FRC,When set flush all SLC entries made dirty by the FRC Video Core then invalidate all SLC entries referenced solely by the FRC Video Core (Optional feature)" "0,1" newline bitfld.long 0x10 7. "DM_VXE,When set flush all SLC entries made dirty by the VXE Video Core then invalidate all SLC entries referenced solely by the VXE Video Core (Optional feature)" "0,1" newline bitfld.long 0x10 6. "DM_VXD,When set flush all SLC entries made dirty by the VXD Video Core then invalidate all SLC entries referenced solely by the VXD Video Core (Optional feature)" "0,1" newline bitfld.long 0x10 5. "DM_HOST_META,When set flush all SLC entries made dirty by the HOST or META then invalidate all SLC entries referenced solely by the HOST or META" "0,1" newline bitfld.long 0x10 4. "DM_MMU,When set flush all SLC entries made dirty by the MMU then invalidate all SLC entries referenced solely by the MMU" "0,1" newline bitfld.long 0x10 3. "DM_COMPUTE,When set flush all SLC entries made dirty by the COMPUTE data master then invalidate all SLC entries referenced solely by the COMPUTE data master" "0,1" newline bitfld.long 0x10 2. "DM_PIXEL,When set flush all SLC entries made dirty by the PIXEL data master then invalidate all SLC entries referenced solely by the PIXEL data master" "0,1" newline bitfld.long 0x10 1. "DM_TA,When set flush all SLC entries made dirty by the TA group which includes VERTEX TESSELLATOR & STREAM_OUT data masters then invalidate all SLC entries referenced solely by the TA group which includes VERTEX TESSELLATOR & STREAM_OUT data masters" "0,1" newline bitfld.long 0x10 0. "ALL,When set flush all SLC entries then invalidate all SLC entries" "0,1" line.long 0x14 "RGX_CR_SLC_CTRL_FLUSH_INVAL_1,SLC Flush & Invalidate control. Note that per Data Master operations will flush any cache lines that have been made dirty by any writes from the specified Data Master. Combined Invalidate operation then only invalidates.." hexmask.long 0x14 0.--31. 1. "Reserved_32,Reserved_32" rgroup.long 0x3820++0x7 line.long 0x0 "RGX_CR_SLC_STATUS0_0,Current status of Flush / Invalidate operations within the SLC" hexmask.long 0x0 3.--31. 1. "Reserved_3,Reserved_3" newline bitfld.long 0x0 2. "FLUSH_INVAL_PENDING,1 indicates there is a pending request to perform a combined Flush Invalidate on the SLC" "0,1" newline bitfld.long 0x0 1. "INVAL_PENDING,1 indicates there is a pending request to Invalidate the SLC" "0,1" newline bitfld.long 0x0 0. "FLUSH_PENDING,1 indicates there is a pending request to Flush the SLC" "0,1" line.long 0x4 "RGX_CR_SLC_STATUS0_1,Current status of Flush / Invalidate operations within the SLC" hexmask.long 0x4 0.--31. 1. "Reserved_3,Reserved_3" group.long 0x3828++0x7 line.long 0x0 "RGX_CR_SLC_CTRL_BYPASS_0,SLC Bypass control" bitfld.long 0x0 31. "DM_FASTRENDER,Bypass SLC the TDM data master" "0,1" newline bitfld.long 0x0 30. "DM_PM_ALIST,Bypass SLC for the PB_ZLS data master" "0,1" newline bitfld.long 0x0 29. "DM_PB_TE,Bypass SLC for the PB_TE data master" "0,1" newline bitfld.long 0x0 28. "DM_PB_VCE,Bypass SLC for the PB_VCE data master" "0,1" newline bitfld.long 0x0 26.--27. "Reserved_26,Reserved_26" "0,1,2,3" newline bitfld.long 0x0 25. "REQ_IPF_CPF,Bypass SLC for IPF (CPF) requestor" "0,1" newline bitfld.long 0x0 24. "REQ_TPU,Bypass SLC for TPU requests coming from the MCU requestor" "0,1" newline bitfld.long 0x0 23. "REQ_FBDC,Bypass SLC for the FBDC requestor" "0,1" newline bitfld.long 0x0 22. "Reserved_22,Reserved_22" "0,1" newline bitfld.long 0x0 21. "BYP_CC_N,Bypass SLC when Cache Coherency bit is not set" "0,1" newline bitfld.long 0x0 20. "BYP_CC,Bypass SLC when Cache Coherency bit is set" "0,1" newline bitfld.long 0x0 19. "REQ_MCU,Bypass SLC for the MCU requestor" "0,1" newline bitfld.long 0x0 18. "REQ_PDS,Bypass SLC for the PDS requestor" "0,1" newline bitfld.long 0x0 17. "REQ_TPF,Bypass SLC for the TPF requestor" "0,1" newline bitfld.long 0x0 16. "REQ_TA_TPC,Bypass SLC for the TA (Tail Pointer Cache data) requestor" "0,1" newline bitfld.long 0x0 15. "Reserved_15,Reserved_15" "0,1" newline bitfld.long 0x0 14. "REQ_USC,Bypass SLC for the USC requestor" "0,1" newline bitfld.long 0x0 13. "REQ_META,Bypass SLC for the META requestor" "0,1" newline bitfld.long 0x0 12. "REQ_HOST,Bypass SLC for the Host requestor" "0,1" newline bitfld.long 0x0 11. "REQ_MMU_PT,Bypass SLC for the MMU requestor (Page Table data)" "0,1" newline bitfld.long 0x0 10. "REQ_MMU_PD,Bypass SLC for the MMU requestor (Page Directory data)" "0,1" newline bitfld.long 0x0 9. "REQ_MMU_PC,Bypass SLC for the MMU requestor (Page Catalogue data)" "0,1" newline bitfld.long 0x0 8. "DM_FRC,Bypass SLC for the FRC Video Core (Optional feature)" "0,1" newline bitfld.long 0x0 7. "DM_VXE,Bypass SLC for the VXE Video Core (Optional feature)" "0,1" newline bitfld.long 0x0 6. "DM_VXD,Bypass SLC for the VXD Video Core (Optional feature)" "0,1" newline bitfld.long 0x0 5. "DM_HOST_META,Bypass SLC the HOST/META data master" "0,1" newline bitfld.long 0x0 4. "DM_MMU,Bypass SLC the MMU data master" "0,1" newline bitfld.long 0x0 3. "DM_COMPUTE,Bypass SLC the COMPUTE data master" "0,1" newline bitfld.long 0x0 2. "DM_PIXEL,Bypass SLC for the PIXEL data master" "0,1" newline bitfld.long 0x0 1. "DM_TA,Bypass SLC for the TA group which includes VERTEX TESSELLATOR & STREAM_OUT data masters" "0,1" newline bitfld.long 0x0 0. "ALL,Bypass SLC for all requesters" "0,1" line.long 0x4 "RGX_CR_SLC_CTRL_BYPASS_1,SLC Bypass control" hexmask.long.word 0x4 22.--31. 1. "Reserved_54,Reserved_54" newline bitfld.long 0x4 21. "REQ_TCU_DM_COMPUTE,Bypass SLC when DM is COMPUTE for TCU requests" "0,1" newline bitfld.long 0x4 19.--20. "Reserved_51,Reserved_51" "0,1,2,3" newline bitfld.long 0x4 18. "REQ_FBC,Bypass SLC for FBC requestor" "0,1" newline bitfld.long 0x4 17. "REQ_IPF_RREQ,Bypass SLC for IPF (RREQ) requestor" "0,1" newline bitfld.long 0x4 16. "REQ_IPF_CREQ,Bypass SLC for IPF (CREQ) requestor" "0,1" newline bitfld.long 0x4 15. "REQ_IPF_PREQ,Bypass SLC for IPF (PREQ) requestor" "0,1" newline bitfld.long 0x4 14. "REQ_IPF_DBSC,Bypass SLC for IPF (DBSC) requestor" "0,1" newline bitfld.long 0x4 13. "REQ_TCU,Bypass SLC for TCU requests" "0,1" newline bitfld.long 0x4 12. "REQ_PBE,Bypass SLC for PBE requestor" "0,1" newline bitfld.long 0x4 11. "REQ_ISP,Bypass SLC for the ISP requestor" "0,1" newline bitfld.long 0x4 10. "REQ_PM,Bypass SLC for the PM requestor" "0,1" newline bitfld.long 0x4 9. "REQ_TDM,Bypass SLC for the TDM requestor" "0,1" newline bitfld.long 0x4 8. "REQ_CDM,Bypass SLC for the CDM requestor" "0,1" newline bitfld.long 0x4 7. "REQ_TSPF_PDS_STATE,Bypass SLC for the TSPF PDS STATE requestor" "0,1" newline bitfld.long 0x4 6. "REQ_TSPF_DB,Bypass SLC for the TSPF DB requestor" "0,1" newline bitfld.long 0x4 5. "REQ_TSPF_VTX_VAR,Bypass SLC for the TSPF VTX VAR requestor" "0,1" newline bitfld.long 0x4 4. "REQ_VDM,Bypass SLC for VDM requestor" "0,1" newline bitfld.long 0x4 3. "REQ_TA_PSG_STREAM,Bypass SLC for the TA (PSG Stream) requestor" "0,1" newline bitfld.long 0x4 2. "REQ_TA_PSG_REGION,Bypass SLC for the TA (PSG Region) requestor" "0,1" newline bitfld.long 0x4 1. "REQ_TA_VCE,Bypass SLC for the TA (VCE) requestor" "0,1" newline bitfld.long 0x4 0. "REQ_TA_PPP,Bypass SLC for the TA (PPP) requestor" "0,1" repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) group.long ($2+0x3830)++0x3 line.long 0x0 "RGX_CR_SLC_LINE_USE_COUNT_LIMIT0_$1,Define the maximum number of cache lines allowed to be allocated to each requester within the SLC. Note that values are specified per bank as a multiple of 4 cache lines with values of 0x0 denoting no limit. Also note.." hexmask.long.byte 0x0 24.--31. 1. "TDM,Maximum number of cachelines allocated to the TDM requestor" newline hexmask.long.byte 0x0 16.--23. 1. "HOST,Maximum number of cachelines allocated to the HOST requestor" newline hexmask.long.byte 0x0 8.--15. 1. "TCU,Maximum number of cachelines allocated to the TCU requestor" newline hexmask.long.byte 0x0 0.--7. 1. "MMU,Maximum number of cachelines allocated to the MMU requestor" repeat.end group.long 0x3838++0x7 line.long 0x0 "RGX_CR_SLC_LINE_USE_COUNT_LIMIT1_0,Define the maximum number of cache lines allowed to be allocated to each requester within the SLC. Note that values are specified per bank as a multiple of 4 cache lines with values of 0x0 denoting no limit. Also note.." hexmask.long.byte 0x0 24.--31. 1. "VXD,Maximum number of cachelines allocated to the VXD requestor" newline hexmask.long.byte 0x0 16.--23. 1. "FBDC,Maximum number of cachelines allocated to the FBDC requestor" newline hexmask.long.byte 0x0 8.--15. 1. "MCU,Maximum number of cachelines allocated to the MCU requestor" newline hexmask.long.byte 0x0 0.--7. 1. "PDS,Maximum number of cachelines allocated to the PDS requestor" line.long 0x4 "RGX_CR_SLC_LINE_USE_COUNT_LIMIT1_1,Define the maximum number of cache lines allowed to be allocated to each requester within the SLC. Note that values are specified per bank as a multiple of 4 cache lines with values of 0x0 denoting no limit. Also note.." hexmask.long.word 0x4 16.--31. 1. "Reserved_48,Reserved_48" newline hexmask.long.byte 0x4 8.--15. 1. "FRC,Maximum number of cachelines allocated to the FRC requestor" newline hexmask.long.byte 0x4 0.--7. 1. "VXE,Maximum number of cachelines allocated to the VXE requestor" rgroup.long 0x3840++0x37 line.long 0x0 "RGX_CR_SLC_LINE_USE_COUNT_STATUS0_0,Number of cache lines currently allocated to each requester within the SLC. Values will constantly change when the core is active but will give a representative snapshot of cache usage." hexmask.long.byte 0x0 24.--31. 1. "BANK0_TDM,Number of cache lines in bank 0 currently allocated to the TDM" newline hexmask.long.word 0x0 12.--23. 1. "BANK1_MMU,Number of cache lines in bank 1 currently allocated to the MMU" newline hexmask.long.word 0x0 0.--11. 1. "BANK0_MMU,Number of cache lines in bank 0 currently allocated to the MMU" line.long 0x4 "RGX_CR_SLC_LINE_USE_COUNT_STATUS0_1,Number of cache lines currently allocated to each requester within the SLC. Values will constantly change when the core is active but will give a representative snapshot of cache usage." hexmask.long.byte 0x4 28.--31. 1. "Reserved_60,Reserved_60" newline hexmask.long.word 0x4 16.--27. 1. "BANK0_HOST,Number of cache lines in bank 0 currently allocated to the HOST" newline hexmask.long.word 0x4 4.--15. 1. "BANK1_TDM,Number of cache lines in bank 1 currently allocated to the TDM" newline hexmask.long.byte 0x4 0.--3. 1. "BANK0_TDM,Number of cache lines in bank 0 currently allocated to the TDM" line.long 0x8 "RGX_CR_SLC_LINE_USE_COUNT_STATUS1_0,Number of cache lines currently allocated to each requester within the SLC. Values will constantly change when the core is active but will give a representative snapshot of cache usage." hexmask.long.byte 0x8 24.--31. 1. "BANK1_TCU,Number of cache lines in bank 1 currently allocated to the TCU" newline hexmask.long.word 0x8 12.--23. 1. "BANK0_TCU,Number of cache lines in bank 0 currently allocated to the TCU" newline hexmask.long.word 0x8 0.--11. 1. "BANK1_HOST,Number of cache lines in bank 1 currently allocated to the HOST" line.long 0xC "RGX_CR_SLC_LINE_USE_COUNT_STATUS1_1,Number of cache lines currently allocated to each requester within the SLC. Values will constantly change when the core is active but will give a representative snapshot of cache usage." hexmask.long.byte 0xC 28.--31. 1. "Reserved_60,Reserved_60" newline hexmask.long.word 0xC 16.--27. 1. "BANK1_USC,Number of cache lines in bank 1 currently allocated to the USC" newline hexmask.long.word 0xC 4.--15. 1. "BANK0_USC,Number of cache lines in bank 0 currently allocated to the USC" newline hexmask.long.byte 0xC 0.--3. 1. "BANK1_TCU,Number of cache lines in bank 1 currently allocated to the TCU" line.long 0x10 "RGX_CR_SLC_LINE_USE_COUNT_STATUS2_0,Number of cache lines currently allocated to each requester within the SLC. Values will constantly change when the core is active but will give a representative snapshot of cache usage." hexmask.long.byte 0x10 24.--31. 1. "BANK0_TA_TPC,Number of cache lines in bank 0 currently allocated to the TA (Tail Pointer Cache data)" newline hexmask.long.word 0x10 12.--23. 1. "BANK1_IPF_OBJ,Number of cache lines in bank 1 currently allocated to the IPF (Object data)" newline hexmask.long.word 0x10 0.--11. 1. "BANK0_IPF_OBJ,Number of cache lines in bank 0 currently allocated to the IPF (Object data)" line.long 0x14 "RGX_CR_SLC_LINE_USE_COUNT_STATUS2_1,Number of cache lines currently allocated to each requester within the SLC. Values will constantly change when the core is active but will give a representative snapshot of cache usage." hexmask.long.byte 0x14 28.--31. 1. "Reserved_60,Reserved_60" newline hexmask.long.word 0x14 16.--27. 1. "BANK0_TPF,Number of cache lines in bank 0 currently allocated to the TPF" newline hexmask.long.word 0x14 4.--15. 1. "BANK1_TA_TPC,Number of cache lines in bank 1 currently allocated to the TA (Tail Pointer Cache data)" newline hexmask.long.byte 0x14 0.--3. 1. "BANK0_TA_TPC,Number of cache lines in bank 0 currently allocated to the TA (Tail Pointer Cache data)" line.long 0x18 "RGX_CR_SLC_LINE_USE_COUNT_STATUS3_0,Number of cache lines currently allocated to each requester within the SLC. Values will constantly change when the core is active but will give a representative snapshot of cache usage." hexmask.long.byte 0x18 24.--31. 1. "BANK1_PDS,Number of cache lines in bank 1 currently allocated to the PDS" newline hexmask.long.word 0x18 12.--23. 1. "BANK0_PDS,Number of cache lines in bank 0 currently allocated to the PDS" newline hexmask.long.word 0x18 0.--11. 1. "BANK1_TPF,Number of cache lines in bank 1 currently allocated to the TPF" line.long 0x1C "RGX_CR_SLC_LINE_USE_COUNT_STATUS3_1,Number of cache lines currently allocated to each requester within the SLC. Values will constantly change when the core is active but will give a representative snapshot of cache usage." hexmask.long.byte 0x1C 28.--31. 1. "Reserved_60,Reserved_60" newline hexmask.long.word 0x1C 16.--27. 1. "BANK1_MCU,Number of cache lines in bank 1 currently allocated to the MCU" newline hexmask.long.word 0x1C 4.--15. 1. "BANK0_MCU,Number of cache lines in bank 0 currently allocated to the MCU" newline hexmask.long.byte 0x1C 0.--3. 1. "BANK1_PDS,Number of cache lines in bank 1 currently allocated to the PDS" line.long 0x20 "RGX_CR_SLC_LINE_USE_COUNT_STATUS4_0,Number of cache lines currently allocated to each requester within the SLC. Values will constantly change when the core is active but will give a representative snapshot of cache usage." hexmask.long.byte 0x20 24.--31. 1. "BANK0_VXD,Number of cache lines in bank 0 currently allocated to the VXD core" newline hexmask.long.word 0x20 12.--23. 1. "BANK1_FBDC,Number of cache lines in bank 1 currently allocated to the FBDC" newline hexmask.long.word 0x20 0.--11. 1. "BANK0_FBDC,Number of cache lines in bank 0 currently allocated to the FBDC" line.long 0x24 "RGX_CR_SLC_LINE_USE_COUNT_STATUS4_1,Number of cache lines currently allocated to each requester within the SLC. Values will constantly change when the core is active but will give a representative snapshot of cache usage." hexmask.long.byte 0x24 28.--31. 1. "Reserved_60,Reserved_60" newline hexmask.long.word 0x24 16.--27. 1. "BANK0_VXE,Number of cache lines in bank 0 currently allocated to the VXE core" newline hexmask.long.word 0x24 4.--15. 1. "BANK1_VXD,Number of cache lines in bank 1 currently allocated to the VXD core" newline hexmask.long.byte 0x24 0.--3. 1. "BANK0_VXD,Number of cache lines in bank 0 currently allocated to the VXD core" line.long 0x28 "RGX_CR_SLC_LINE_USE_COUNT_STATUS5_0,Number of cache lines currently allocated to each requester within the SLC. Values will constantly change when the core is active but will give a representative snapshot of cache usage." hexmask.long.byte 0x28 24.--31. 1. "BANK1_FRC,Number of cache lines in bank 1 currently allocated to the FRC core" newline hexmask.long.word 0x28 12.--23. 1. "BANK0_FRC,Number of cache lines in bank 0 currently allocated to the FRC core" newline hexmask.long.word 0x28 0.--11. 1. "BANK1_VXE,Number of cache lines in bank 1 currently allocated to the VXE core" line.long 0x2C "RGX_CR_SLC_LINE_USE_COUNT_STATUS5_1,Number of cache lines currently allocated to each requester within the SLC. Values will constantly change when the core is active but will give a representative snapshot of cache usage." hexmask.long.byte 0x2C 28.--31. 1. "Reserved_60,Reserved_60" newline hexmask.long.word 0x2C 16.--27. 1. "BANK1_PM,Number of cache lines in bank 1 currently allocated to the PM core" newline hexmask.long.word 0x2C 4.--15. 1. "BANK0_PM,Number of cache lines in bank 0 currently allocated to the PM core" newline hexmask.long.byte 0x2C 0.--3. 1. "BANK1_FRC,Number of cache lines in bank 1 currently allocated to the FRC core" line.long 0x30 "RGX_CR_SLC_STATUS1_0,Current status of the SLC" hexmask.long.byte 0x30 26.--31. 1. "Reserved_26,Reserved_26" newline hexmask.long.word 0x30 16.--25. 1. "READS0,Number of items of read data SLC bank 0 has in internal pipeline FIFO's" newline hexmask.long.byte 0x30 8.--15. 1. "READS1_EXT,Number of items of read data SLC bank 1 has outstanding from external memory" newline hexmask.long.byte 0x30 0.--7. 1. "READS0_EXT,Number of items of read data SLC bank 0 has outstanding from external memory" line.long 0x34 "RGX_CR_SLC_STATUS1_1,Current status of the SLC" bitfld.long 0x34 31. "PAUSED,All cache banks are Paused" "0,1" newline hexmask.long.tbyte 0x34 10.--30. 1. "Reserved_42,Reserved_42" newline hexmask.long.word 0x34 0.--9. 1. "READS1,Number of items of read data SLC bank 1 has in internal pipeline FIFO's" group.long 0x3878++0x7 line.long 0x0 "RGX_CR_SLC_STATS0_CTRL_0,Configuration of the SLC Stats counters inside SLC bank 0. The type fields should be set to define the events that should be counted. then constraints should be added to specify particular requestors or types of request that.." hexmask.long.byte 0x0 28.--31. 1. "Reserved_28,Reserved_28" newline bitfld.long 0x0 27. "STOP,Pause counting whilst this bit is set" "0,1" newline bitfld.long 0x0 26. "RESET,Reset counter" "0,1" newline bitfld.long 0x0 25. "RNW,If constraint set 0x0 count only writes 0x1 count only reads" "0,1" newline bitfld.long 0x0 24. "BYPASS,If constraint set 0x0 count cached requests 0x1 count bypassed requests" "0,1" newline bitfld.long 0x0 21.--23. "DM,If constraint set count only requests for the specified Data Master" "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x0 16.--20. 1. "TAG_ID,If constraint set count only requests with the specified Tag ID" newline hexmask.long.byte 0x0 8.--15. 1. "TAG_SB,If constraint set count only requests with the specified sideband Tag" newline bitfld.long 0x0 7. "SELECT_TAG_SB,Include Tag sideband in constraints" "0,1" newline bitfld.long 0x0 6. "SELECT_TAG_ID,Include Tag ID in constraints" "0,1" newline bitfld.long 0x0 5. "SELECT_DM,Include Data Master in constraints" "0,1" newline bitfld.long 0x0 4. "SELECT_BYPASS,Include Bypass enable in constraints" "0,1" newline bitfld.long 0x0 3. "SELECT_RNW,Include Wead/Write select in constraints" "0,1" newline bitfld.long 0x0 2. "TYPE_FLUSH,Count number of cache lines flushed" "0,1" newline bitfld.long 0x0 1. "TYPE_MISS,Count number of misses" "0,1" newline bitfld.long 0x0 0. "TYPE_HIT,Count number of hits" "0,1" line.long 0x4 "RGX_CR_SLC_STATS0_CTRL_1,Configuration of the SLC Stats counters inside SLC bank 0. The type fields should be set to define the events that should be counted. then constraints should be added to specify particular requestors or types of request that.." hexmask.long 0x4 0.--31. 1. "Reserved_28,Reserved_28" repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) rgroup.long ($2+0x3880)++0x3 line.long 0x0 "RGX_CR_SLC_STATS0_OUTPUT_$1,Output of the SLC Stats counter inside SLC bank 0." hexmask.long 0x0 0.--31. 1. "VALUE,Value of counter 0" repeat.end group.long 0x3888++0x7 line.long 0x0 "RGX_CR_SLC_STATS1_CTRL_0,Configuration of the SLC Stats counters inside SLC bank 1. The type fields should be set to define the events that should be counted. then constraints should be added to specify particular requestors or types of request that.." hexmask.long.byte 0x0 28.--31. 1. "Reserved_28,Reserved_28" newline bitfld.long 0x0 27. "STOP,Pause counting whilst this bit is set" "0,1" newline bitfld.long 0x0 26. "RESET,Reset counter" "0,1" newline bitfld.long 0x0 25. "RNW,If constraint set 0x0 count only writes 0x1 count only reads" "0,1" newline bitfld.long 0x0 24. "BYPASS,If constraint set 0x0 count cached requests 0x1 count bypassed requests" "0,1" newline bitfld.long 0x0 21.--23. "DM,If constraint set count only requests for the specified Data Master" "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x0 16.--20. 1. "TAG_ID,If constraint set count only requests with the specified Tag ID" newline hexmask.long.byte 0x0 8.--15. 1. "TAG_SB,If constraint set count only requests with the specified sideband Tag" newline bitfld.long 0x0 7. "SELECT_TAG_SB,Include Tag sideband in constraints" "0,1" newline bitfld.long 0x0 6. "SELECT_TAG_ID,Include Tag ID in constraints" "0,1" newline bitfld.long 0x0 5. "SELECT_DM,Include Data Master in constraints" "0,1" newline bitfld.long 0x0 4. "SELECT_BYPASS,Include Bypass enable in constraints" "0,1" newline bitfld.long 0x0 3. "SELECT_RNW,Include Wead/Write select in constraints" "0,1" newline bitfld.long 0x0 2. "TYPE_FLUSH,Count number of cache lines flushed" "0,1" newline bitfld.long 0x0 1. "TYPE_MISS,Count number of misses" "0,1" newline bitfld.long 0x0 0. "TYPE_HIT,Count number of hits" "0,1" line.long 0x4 "RGX_CR_SLC_STATS1_CTRL_1,Configuration of the SLC Stats counters inside SLC bank 1. The type fields should be set to define the events that should be counted. then constraints should be added to specify particular requestors or types of request that.." hexmask.long 0x4 0.--31. 1. "Reserved_28,Reserved_28" repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) rgroup.long ($2+0x3890)++0x3 line.long 0x0 "RGX_CR_SLC_STATS1_OUTPUT_$1,Output of the SLC Stats counter inside SLC bank 1." hexmask.long 0x0 0.--31. 1. "VALUE,Value of counter 1" repeat.end rgroup.long 0x3898++0x7 line.long 0x0 "RGX_CR_SLC_IDLE_0,RGX_CR_SLC_IDLE_0" hexmask.long.tbyte 0x0 10.--31. 1. "Reserved_10,Reserved_10" newline bitfld.long 0x0 9. "MH_SYSARB1,SYSARB1 Module IDLE" "0,1" newline bitfld.long 0x0 8. "MH_SYSARB0,SYSARB0 Module IDLE" "0,1" newline bitfld.long 0x0 7. "IMGBV4,IMG Bus v4 Module IDLE" "0,1" newline bitfld.long 0x0 6. "CACHE_BANKS,Cache Bank IDLEs" "0,1" newline bitfld.long 0x0 5. "RBOFIFO,Read Burst Order FIFO Module IDLE" "0,1" newline bitfld.long 0x0 4. "FRC_CONV,FRC Module IDLE" "0,1" newline bitfld.long 0x0 3. "VXE_CONV,Video Encode Converter Module IDLE" "0,1" newline bitfld.long 0x0 2. "VXD_CONV,Video Decode Converter Module IDLE" "0,1" newline bitfld.long 0x0 1. "BIF1_CONV,BIF128->256 Converter Module IDLE" "0,1" newline bitfld.long 0x0 0. "CBAR,CrossBar Module IDLE" "0,1" line.long 0x4 "RGX_CR_SLC_IDLE_1,RGX_CR_SLC_IDLE_1" hexmask.long 0x4 0.--31. 1. "Reserved_10,Reserved_10" repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) rgroup.long ($2+0x38A0)++0x3 line.long 0x0 "RGX_CR_MCU_PWR_NUM_$1,Power Monitoring register" hexmask.long 0x0 0.--31. 1. "L0_TO_L1_ACCESS,Number of L0 to L1 accesses. Both L0s in a DUST added together" repeat.end group.long 0x38A8++0x7 line.long 0x0 "RGX_CR_SLC_LINE_USE_COUNT_LIMIT2_0,Define the maximum number of cache lines allowed to be allocated to each requester within the SLC. Note that values are specified per bank as a multiple of 4 cache lines with values of 0x0 denoting no limit. Also note.." hexmask.long.byte 0x0 24.--31. 1. "CDM,Maximum number of cachelines allocated to the CDM requestor" newline hexmask.long.byte 0x0 16.--23. 1. "VDM,Maximum number of cachelines allocated to the VDM requestor" newline hexmask.long.byte 0x0 8.--15. 1. "ISP,Maximum number of cachelines allocated to the ISP requestor" newline hexmask.long.byte 0x0 0.--7. 1. "PBE,Maximum number of cachelines allocated to the PBE requestor" line.long 0x4 "RGX_CR_SLC_LINE_USE_COUNT_LIMIT2_1,Define the maximum number of cache lines allowed to be allocated to each requester within the SLC. Note that values are specified per bank as a multiple of 4 cache lines with values of 0x0 denoting no limit. Also note.." hexmask.long.tbyte 0x4 8.--31. 1. "Reserved_40,Reserved_40" newline hexmask.long.byte 0x4 0.--7. 1. "PM,Maximum number of cachelines allocated to the PM requestor" rgroup.long 0x38B0++0xF line.long 0x0 "RGX_CR_SLC_LINE_USE_COUNT_STATUS6_0,Number of cache lines currently allocated to each requester within the SLC. Values will constantly change when the core is active but will give a representative snapshot of cache usage." hexmask.long.byte 0x0 24.--31. 1. "BANK0_ISP,Number of cache lines in bank 0 currently allocated to the ISP core" newline hexmask.long.word 0x0 12.--23. 1. "BANK1_PBE,Number of cache lines in bank 1 currently allocated to the PBE core" newline hexmask.long.word 0x0 0.--11. 1. "BANK0_PBE,Number of cache lines in bank 0 currently allocated to the PBE core" line.long 0x4 "RGX_CR_SLC_LINE_USE_COUNT_STATUS6_1,Number of cache lines currently allocated to each requester within the SLC. Values will constantly change when the core is active but will give a representative snapshot of cache usage." hexmask.long.byte 0x4 28.--31. 1. "Reserved_60,Reserved_60" newline hexmask.long.word 0x4 16.--27. 1. "BANK0_CDM,Number of cache lines in bank 1 currently allocated to the CDM core" newline hexmask.long.word 0x4 4.--15. 1. "BANK1_ISP,Number of cache lines in bank 1 currently allocated to the ISP core" newline hexmask.long.byte 0x4 0.--3. 1. "BANK0_ISP,Number of cache lines in bank 0 currently allocated to the ISP core" line.long 0x8 "RGX_CR_SLC_LINE_USE_COUNT_STATUS7_0,Number of cache lines currently allocated to each requester within the SLC. Values will constantly change when the core is active but will give a representative snapshot of cache usage." hexmask.long.byte 0x8 24.--31. 1. "BANK1_VDM,Number of cache lines in bank 1 currently allocated to the VDM core" newline hexmask.long.word 0x8 12.--23. 1. "BANK0_VDM,Number of cache lines in bank 0 currently allocated to the VDM core" newline hexmask.long.word 0x8 0.--11. 1. "BANK1_CDM,Number of cache lines in bank 1 currently allocated to the CDM core" line.long 0xC "RGX_CR_SLC_LINE_USE_COUNT_STATUS7_1,Number of cache lines currently allocated to each requester within the SLC. Values will constantly change when the core is active but will give a representative snapshot of cache usage." hexmask.long 0xC 4.--31. 1. "Reserved_36,Reserved_36" newline hexmask.long.byte 0xC 0.--3. 1. "BANK1_VDM,Number of cache lines in bank 1 currently allocated to the VDM core" group.long 0x38C0++0x17 line.long 0x0 "RGX_CR_AXI_ACE_LITE_CONFIGURATION_0,AXI ACE-LITE configuration registers" bitfld.long 0x0 30.--31. "ARCACHE_CACHE_MAINTENANCE,Read cache policy for cache maintenance transactions - bit[1] should be set to 1" "0,1,2,3" newline hexmask.long.byte 0x0 26.--29. 1. "ARCACHE_COHERENT,Read cache policy for coherent transactions - bit[1] should be set to 1" newline hexmask.long.byte 0x0 22.--25. 1. "AWCACHE_COHERENT,Write cache policy for coherent transactions - bit[1] should be set to 1" newline bitfld.long 0x0 20.--21. "ARDOMAIN_BARRIER,Read shareability domain for barrier transactions 00 = Non-Shareable 01 = Inner Shareable 10 = Outer Shareable 11 = System" "Non-Shareable,Inner Shareable,?,?" newline bitfld.long 0x0 18.--19. "AWDOMAIN_BARRIER,Write shareability domain for barrier transactions 00 = Non-Shareable 01 = Inner Shareable 10 = Outer Shareable 11 = System" "Non-Shareable,Inner Shareable,?,?" newline bitfld.long 0x0 16.--17. "ARDOMAIN_CACHE_MAINTENANCE,Read shareability domain for cache maintenance transactions 00 = Non-Shareable 01 = Inner Shareable 10 = Outer Shareable" "Non-Shareable,Inner Shareable,?,?" newline bitfld.long 0x0 14.--15. "AWDOMAIN_COHERENT,Write shareability domain for coherant transactions 01 = Inner Shareable 10 = Outer Shareable" "?,Inner Shareable,?,?" newline bitfld.long 0x0 12.--13. "ARDOMAIN_COHERENT,Read shareability domain for coherant transactions 01 = Inner Shareable 10 = Outer Shareable" "?,Inner Shareable,?,?" newline bitfld.long 0x0 10.--11. "ARDOMAIN_NON_SNOOPING,Read shareability domain for non-snooping transactions 00 = Non-Shareable 11 = System" "Non-Shareable,?,?,?" newline bitfld.long 0x0 8.--9. "AWDOMAIN_NON_SNOOPING,Write shareability domain for non-snooping transactions 00 = Non-Shareable 11 = System" "Non-Shareable,?,?,?" newline hexmask.long.byte 0x0 4.--7. 1. "ARCACHE_NON_SNOOPING,Read cache policy for non-snooping transactions" newline hexmask.long.byte 0x0 0.--3. 1. "AWCACHE_NON_SNOOPING,Write cache policy for non-snooping transactions" line.long 0x4 "RGX_CR_AXI_ACE_LITE_CONFIGURATION_1,AXI ACE-LITE configuration registers" hexmask.long.tbyte 0x4 13.--31. 1. "Reserved_45,Reserved_45" newline hexmask.long.byte 0x4 5.--12. 1. "OSID_SECURITY,SET to 1 to disable secure reads/writes for each OSID" newline bitfld.long 0x4 4. "DISABLE_COHERENT_WRITELINEUNIQUE,SET to 1 to disable coherent write line uniques" "0,1" newline bitfld.long 0x4 3. "DISABLE_COHERENT_WRITE,SET to 1 to disable coherent writes" "0,1" newline bitfld.long 0x4 2. "DISABLE_COHERENT_READ,SET to 1 to disable coherent reads" "0,1" newline bitfld.long 0x4 0.--1. "ARCACHE_CACHE_MAINTENANCE,Read cache policy for cache maintenance transactions - bit[1] should be set to 1" "0,1,2,3" line.long 0x8 "RGX_CR_AXI_ACE_LITE_CACHE_MAINTENANCE_CONFIGURATION_0,AXI ACE-LITE Cache Maintenance configuration registers" hexmask.long 0x8 4.--31. 1. "MAINTENANCE_ADDRESS,Address to perform cache maintenace address on" newline bitfld.long 0x8 3. "MAINTENANCE_MAKEINVALID,Writing a 1 issues a makeinvalid operation" "0,1" newline bitfld.long 0x8 2. "MAINTENANCE_CLEAN_INVALID,Writing a 1 issues a clean invalid operation" "0,1" newline bitfld.long 0x8 1. "MAINTENANCE_CLEANSHARED,Writing a 1 issues a clean shared operation" "0,1" newline bitfld.long 0x8 0. "ENABLE_MAINTENANCE,Writing a 1 enables cache maintenance operations" "0,1" line.long 0xC "RGX_CR_AXI_ACE_LITE_CACHE_MAINTENANCE_CONFIGURATION_1,AXI ACE-LITE Cache Maintenance configuration registers" hexmask.long.tbyte 0xC 12.--31. 1. "Reserved_44,Reserved_44" newline hexmask.long.word 0xC 0.--11. 1. "MAINTENANCE_ADDRESS,Address to perform cache maintenace address on" line.long 0x10 "RGX_CR_AXI_ACE_LITE_CACHE_MAINTENANCE_STATUS_0,The hardware will set this to 1 once the cache maintenance operation has completed. The firmware should poll this bit and set it to 0. once it has acknowledged it being set to 1." hexmask.long 0x10 1.--31. 1. "Reserved_1,Reserved_1" newline bitfld.long 0x10 0. "DONE,DONE" "0,1" line.long 0x14 "RGX_CR_AXI_ACE_LITE_CACHE_MAINTENANCE_STATUS_1,The hardware will set this to 1 once the cache maintenance operation has completed. The firmware should poll this bit and set it to 0. once it has acknowledged it being set to 1." hexmask.long 0x14 0.--31. 1. "Reserved_1,Reserved_1" repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) group.long ($2+0x3930)++0x3 line.long 0x0 "RGX_CR_SLC_CTRL_MISC2_$1,SLC control registers" hexmask.long 0x0 0.--31. 1. "SCRAMBLE_BITS,Pattern of bits used to determine the MSB of the Cache Bank in 4 Bank configurations in Address Decode mode 0x21. The actual Cache Bank to use is determined by indexing into the 32 Scramble Bits using the 5 LSB's of the Hash result and then.." repeat.end group.long 0x3938++0x7 line.long 0x0 "RGX_CR_SLC_CROSSBAR_LOAD_BALANCE_0,SLC control registers to bypass SLC crossbar load balancing" hexmask.long 0x0 1.--31. 1. "Reserved_1,Reserved_1" newline bitfld.long 0x0 0. "BYPASS,control register bit to bypass load balancing in SLC crossbar. In this case the requests from img-memif0 will go directly to ocp-memif0 and so on" "0,1" line.long 0x4 "RGX_CR_SLC_CROSSBAR_LOAD_BALANCE_1,SLC control registers to bypass SLC crossbar load balancing" hexmask.long 0x4 0.--31. 1. "Reserved_1,Reserved_1" rgroup.long 0x3960++0x7 line.long 0x0 "RGX_CR_SLC_STATUS3_0,Current status of the SLC" hexmask.long.byte 0x0 24.--31. 1. "WRITES1_TRANSACTIONS_EXT,Number of outsanding write burst transactions in SLC bank 1" newline hexmask.long.byte 0x0 16.--23. 1. "WRITES0_TRANSACTIONS_EXT,Number of outsanding write burst transactions in SLC bank 0" newline hexmask.long.byte 0x0 8.--15. 1. "READS1_TRANSACTIONS_EXT,Number of outsanding read burst transactions in SLC bank 1" newline hexmask.long.byte 0x0 0.--7. 1. "READS0_TRANSACTIONS_EXT,Number of outsanding read burst transactions in SLC bank 0" line.long 0x4 "RGX_CR_SLC_STATUS3_1,Current status of the SLC" hexmask.long 0x4 0.--31. 1. "Reserved_32,Reserved_32" wgroup.long 0x4000++0x7 line.long 0x0 "RGX_CR_USC_INST_CACHE_0,RGX_CR_USC_INST_CACHE_0" hexmask.long 0x0 1.--31. 1. "Reserved_1,Reserved_1" newline bitfld.long 0x0 0. "INVALIDATE,Any write to this location invalidates the L1 and L2 instruction caches automatically" "0,1" line.long 0x4 "RGX_CR_USC_INST_CACHE_1,RGX_CR_USC_INST_CACHE_1" hexmask.long 0x4 0.--31. 1. "Reserved_1,Reserved_1" group.long 0x4008++0xF line.long 0x0 "RGX_CR_USC_CODE_BASE_VERTEX_0,RGX_CR_USC_CODE_BASE_VERTEX_0" hexmask.long 0x0 6.--31. 1. "ADDR,Vertex Data Master Code Base Register bits" newline hexmask.long.byte 0x0 0.--5. 1. "Reserved_0,Reserved_0" line.long 0x4 "RGX_CR_USC_CODE_BASE_VERTEX_1,RGX_CR_USC_CODE_BASE_VERTEX_1" hexmask.long.tbyte 0x4 8.--31. 1. "Reserved_40,Reserved_40" newline hexmask.long.byte 0x4 0.--7. 1. "ADDR,Vertex Data Master Code Base Register bits" line.long 0x8 "RGX_CR_USC_CODE_BASE_PIXEL_0,RGX_CR_USC_CODE_BASE_PIXEL_0" hexmask.long 0x8 6.--31. 1. "ADDR,Pixel Data Master Code Base Register bits" newline hexmask.long.byte 0x8 0.--5. 1. "Reserved_0,Reserved_0" line.long 0xC "RGX_CR_USC_CODE_BASE_PIXEL_1,RGX_CR_USC_CODE_BASE_PIXEL_1" hexmask.long.tbyte 0xC 8.--31. 1. "Reserved_40,Reserved_40" newline hexmask.long.byte 0xC 0.--7. 1. "ADDR,Pixel Data Master Code Base Register bits" group.long 0x4028++0x4F line.long 0x0 "RGX_CR_USC_CODE_BASE_COMPUTE_0,RGX_CR_USC_CODE_BASE_COMPUTE_0" hexmask.long 0x0 6.--31. 1. "ADDR,Compute Data Master Code Base Register bits" newline hexmask.long.byte 0x0 0.--5. 1. "Reserved_0,Reserved_0" line.long 0x4 "RGX_CR_USC_CODE_BASE_COMPUTE_1,RGX_CR_USC_CODE_BASE_COMPUTE_1" hexmask.long.tbyte 0x4 8.--31. 1. "Reserved_40,Reserved_40" newline hexmask.long.byte 0x4 0.--7. 1. "ADDR,Compute Data Master Code Base Register bits" line.long 0x8 "RGX_CR_USC_BREAKPOINT_0,RGX_CR_USC_BREAKPOINT_0" hexmask.long 0x8 1.--31. 1. "ADDR,Breakpoint Address" newline bitfld.long 0x8 0. "Reserved_0,Reserved_0" "0,1" line.long 0xC "RGX_CR_USC_BREAKPOINT_1,RGX_CR_USC_BREAKPOINT_1" hexmask.long 0xC 0.--31. 1. "Reserved_32,Reserved_32" line.long 0x10 "RGX_CR_USC_BREAKPOINT_HANDLER_0,RGX_CR_USC_BREAKPOINT_HANDLER_0" hexmask.long 0x10 1.--31. 1. "ADDR,Breakpoint Handler Address" newline bitfld.long 0x10 0. "Reserved_0,Reserved_0" "0,1" line.long 0x14 "RGX_CR_USC_BREAKPOINT_HANDLER_1,RGX_CR_USC_BREAKPOINT_HANDLER_1" hexmask.long 0x14 0.--31. 1. "Reserved_32,Reserved_32" line.long 0x18 "RGX_CR_USC_BREAKPOINT_CTRL_0,RGX_CR_USC_BREAKPOINT_CTRL_0" hexmask.long 0x18 4.--31. 1. "Reserved_4,Reserved_4" newline bitfld.long 0x18 3. "ENABLE,0 = Breakpoint disabled 1 = Breakpoint enabled" "Breakpoint disabled,Breakpoint enabled" newline bitfld.long 0x18 0.--2. "DM,Data Master of Breakpoint" "0,1,2,3,4,5,6,7" line.long 0x1C "RGX_CR_USC_BREAKPOINT_CTRL_1,RGX_CR_USC_BREAKPOINT_CTRL_1" hexmask.long 0x1C 0.--31. 1. "Reserved_4,Reserved_4" line.long 0x20 "RGX_CR_USC_SMP_SWAP_0,RGX_CR_USC_SMP_SWAP_0" hexmask.long 0x20 1.--31. 1. "Reserved_1,Reserved_1" newline bitfld.long 0x20 0. "ENABLE,Deactivate after SMP instruction" "0,1" line.long 0x24 "RGX_CR_USC_SMP_SWAP_1,RGX_CR_USC_SMP_SWAP_1" hexmask.long 0x24 0.--31. 1. "Reserved_1,Reserved_1" line.long 0x28 "RGX_CR_USC_OVERRIDE_CTRL_0,RGX_CR_USC_OVERRIDE_CTRL_0" hexmask.long.word 0x28 22.--31. 1. "Reserved_22,Reserved_22" newline bitfld.long 0x28 21. "USCIS_LOCKING,0 = Default enable locking of USCIS when queue fills to maintain task ordering 1 = retry USCIS request" "Default,retry USCIS request" newline bitfld.long 0x28 20. "PHASE_BOTH,0 = Default no extra pass groups when single phase followed by multi-phase 1 = generate pass group whenever phases per task changes" "Default,generate pass group whenever phases per task.." newline bitfld.long 0x28 18.--19. "RESERVE_SLOTS,0 = Default allow all slots to be used for first phase tasks 1 = reserve 1 slot 2 = reserve 2 3 = reserve 4" "Default,reserve 1 slot,reserve 2,reserve 4" newline bitfld.long 0x28 17. "NO_RESERVE,0 = Default reserve slots for second phases 1 = Do not reserve slots for second phase tasks" "Default,Do not reserve slots for second phase tasks" newline bitfld.long 0x28 15.--16. "MAX_GROUP,0 = Default - 8 pass groups in flight 1 = 6 pass groups 2 = 4 pass groups 3 = 2 pass groups. To disable entirely see PDS" "Default,?,?,?" newline bitfld.long 0x28 14. "WAKE_UP,0 = Default normal wake up 1 = force task wake up" "Default,force task wake up" newline bitfld.long 0x28 13. "LATE_PARTN,0 = Default enable pixel data master tasks to start before a partition is allocated 1 = wait for partition" "Default,wait for partition" newline bitfld.long 0x28 12. "DMA_LOCKING,0 = Default enable locking of DMA when queue fills to maintain task ordering 1 = retry DMA request" "Default,retry DMA request" newline bitfld.long 0x28 11. "PRIORITY,0 = Default enable state loading and end of tile tasks to run with higher priority 1 = all tasks low priority" "Default,all tasks low priority" newline bitfld.long 0x28 10. "PHASE_PASSES,0 = Default enable inferred pass groups when multiple phase tasks are encountered 1 = disable hard SDs must be used" "Default,disable" newline bitfld.long 0x28 9. "OUTPUT_WRITES,0 = Default enable tracking of output buffer write completion for on-edge buffer validlity 1 = tracking invalid" "Default,tracking invalid" newline bitfld.long 0x28 8. "SELECTIVE_RATE,0 = Default (core specific enable selective rate mode if functional) 1 = disable" "Default,disable" newline bitfld.long 0x28 6.--7. "Reserved_6,Reserved_6" "0,1,2,3" newline hexmask.long.byte 0x28 0.--5. 1. "DEBUG_TEMPS,Number of temps to add to PDS allocation size for debugging. Units of 8" line.long 0x2C "RGX_CR_USC_OVERRIDE_CTRL_1,RGX_CR_USC_OVERRIDE_CTRL_1" hexmask.long 0x2C 0.--31. 1. "Reserved_22,Reserved_22" line.long 0x30 "RGX_CR_USC_DC_CACHE_CTRL_0,RGX_CR_USC_DC_CACHE_CTRL_0" hexmask.long 0x30 1.--31. 1. "Reserved_1,Reserved_1" newline bitfld.long 0x30 0. "LINES,Number of lines in Dynamic Constant Cache - 0=64 1=128" "0,1" line.long 0x34 "RGX_CR_USC_DC_CACHE_CTRL_1,RGX_CR_USC_DC_CACHE_CTRL_1" hexmask.long 0x34 0.--31. 1. "Reserved_1,Reserved_1" line.long 0x38 "RGX_CR_USC_DC_CACHE_INVALIDATE_0,RGX_CR_USC_DC_CACHE_INVALIDATE_0" hexmask.long 0x38 1.--31. 1. "Reserved_1,Reserved_1" newline bitfld.long 0x38 0. "PENDING,A write of 1 to this location will cause an invalidation of the Dynamic Constant Cache. If DMKILL bit is not set then all entries are invalidated. If DMKILL bit is set then only a data master killing invalidation is performed. The invalidation.." "0,1" line.long 0x3C "RGX_CR_USC_DC_CACHE_INVALIDATE_1,RGX_CR_USC_DC_CACHE_INVALIDATE_1" hexmask.long 0x3C 0.--31. 1. "Reserved_1,Reserved_1" line.long 0x40 "RGX_CR_USC_SHARED_GROUP_CLEAR_0,RGX_CR_USC_SHARED_GROUP_CLEAR_0" hexmask.long 0x40 1.--31. 1. "Reserved_1,Reserved_1" newline bitfld.long 0x40 0. "PENDING,Any write to this location requests the USC Shared Group register file to be cleared" "0,1" line.long 0x44 "RGX_CR_USC_SHARED_GROUP_CLEAR_1,RGX_CR_USC_SHARED_GROUP_CLEAR_1" hexmask.long 0x44 0.--31. 1. "Reserved_1,Reserved_1" line.long 0x48 "RGX_CR_USC_PIXEL_OUTPUT_CTRL_0,RGX_CR_USC_PIXEL_OUTPUT_CTRL_0" hexmask.long.word 0x48 17.--31. 1. "Reserved_17,Reserved_17" newline hexmask.long.word 0x48 3.--16. 1. "PARTITION_MASK,Partition Enable Mask for USC. Defines which partitions are for use by the USC to prevent SPM Deadlock" newline bitfld.long 0x48 2. "ENABLE_4TH_PARTITION,Enables 4th Partition" "0,1" newline bitfld.long 0x48 0.--1. "WIDTH,WIDTH" "0,1,2,3" line.long 0x4C "RGX_CR_USC_PIXEL_OUTPUT_CTRL_1,RGX_CR_USC_PIXEL_OUTPUT_CTRL_1" hexmask.long 0x4C 0.--31. 1. "Reserved_17,Reserved_17" repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) group.long ($2+0x4078)++0x3 line.long 0x0 "RGX_CR_USC_CLEAR_REGISTER0_$1,RGX_CR_USC_CLEAR_REGISTER0_0" hexmask.long 0x0 0.--31. 1. "VAL,Clear Colour register 0" repeat.end repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) group.long ($2+0x4080)++0x3 line.long 0x0 "RGX_CR_USC_CLEAR_REGISTER1_$1,RGX_CR_USC_CLEAR_REGISTER1_0" hexmask.long 0x0 0.--31. 1. "VAL,Clear Colour register 1" repeat.end repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) group.long ($2+0x4088)++0x3 line.long 0x0 "RGX_CR_USC_CLEAR_REGISTER2_$1,RGX_CR_USC_CLEAR_REGISTER2_0" hexmask.long 0x0 0.--31. 1. "VAL,Clear Colour register 2" repeat.end repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) group.long ($2+0x4090)++0x3 line.long 0x0 "RGX_CR_USC_CLEAR_REGISTER3_$1,RGX_CR_USC_CLEAR_REGISTER3_0" hexmask.long 0x0 0.--31. 1. "VAL,Clear Colour register 3" repeat.end group.long 0x4098++0x3F line.long 0x0 "RGX_CR_USC_G0_0,RGX_CR_USC_G0_0" hexmask.long.tbyte 0x0 8.--31. 1. "Reserved_8,Reserved_8" newline hexmask.long.byte 0x0 0.--7. 1. "P,Global cross-thread-accessible read/write register for USC programs via the 'special' bank type" line.long 0x4 "RGX_CR_USC_G0_1,RGX_CR_USC_G0_1" hexmask.long 0x4 0.--31. 1. "Reserved_8,Reserved_8" line.long 0x8 "RGX_CR_USC_G1_0,RGX_CR_USC_G1_0" hexmask.long.tbyte 0x8 8.--31. 1. "Reserved_8,Reserved_8" newline hexmask.long.byte 0x8 0.--7. 1. "P,Global cross-thread-accessible read/write register for USC programs via the 'special' bank type" line.long 0xC "RGX_CR_USC_G1_1,RGX_CR_USC_G1_1" hexmask.long 0xC 0.--31. 1. "Reserved_8,Reserved_8" line.long 0x10 "RGX_CR_USC_G2_0,RGX_CR_USC_G2_0" hexmask.long.tbyte 0x10 8.--31. 1. "Reserved_8,Reserved_8" newline hexmask.long.byte 0x10 0.--7. 1. "P,Global cross-thread-accessible read/write register for USC programs via the 'special' bank type" line.long 0x14 "RGX_CR_USC_G2_1,RGX_CR_USC_G2_1" hexmask.long 0x14 0.--31. 1. "Reserved_8,Reserved_8" line.long 0x18 "RGX_CR_USC_G3_0,RGX_CR_USC_G3_0" hexmask.long.tbyte 0x18 8.--31. 1. "Reserved_8,Reserved_8" newline hexmask.long.byte 0x18 0.--7. 1. "P,Global cross-thread-accessible read/write register for USC programs via the 'special' bank type" line.long 0x1C "RGX_CR_USC_G3_1,RGX_CR_USC_G3_1" hexmask.long 0x1C 0.--31. 1. "Reserved_8,Reserved_8" line.long 0x20 "RGX_CR_USC_G4_0,RGX_CR_USC_G4_0" hexmask.long.tbyte 0x20 8.--31. 1. "Reserved_8,Reserved_8" newline hexmask.long.byte 0x20 0.--7. 1. "P,Global cross-thread-accessible read/write register for USC programs via the 'special' bank type" line.long 0x24 "RGX_CR_USC_G4_1,RGX_CR_USC_G4_1" hexmask.long 0x24 0.--31. 1. "Reserved_8,Reserved_8" line.long 0x28 "RGX_CR_USC_G5_0,RGX_CR_USC_G5_0" hexmask.long.tbyte 0x28 8.--31. 1. "Reserved_8,Reserved_8" newline hexmask.long.byte 0x28 0.--7. 1. "P,Global cross-thread-accessible read/write register for USC programs via the 'special' bank type" line.long 0x2C "RGX_CR_USC_G5_1,RGX_CR_USC_G5_1" hexmask.long 0x2C 0.--31. 1. "Reserved_8,Reserved_8" line.long 0x30 "RGX_CR_USC_G6_0,RGX_CR_USC_G6_0" hexmask.long.tbyte 0x30 8.--31. 1. "Reserved_8,Reserved_8" newline hexmask.long.byte 0x30 0.--7. 1. "P,Global cross-thread-accessible read/write register for USC programs via the 'special' bank type" line.long 0x34 "RGX_CR_USC_G6_1,RGX_CR_USC_G6_1" hexmask.long 0x34 0.--31. 1. "Reserved_8,Reserved_8" line.long 0x38 "RGX_CR_USC_G7_0,RGX_CR_USC_G7_0" hexmask.long.tbyte 0x38 8.--31. 1. "Reserved_8,Reserved_8" newline hexmask.long.byte 0x38 0.--7. 1. "P,Global cross-thread-accessible read/write register for USC programs via the 'special' bank type" line.long 0x3C "RGX_CR_USC_G7_1,RGX_CR_USC_G7_1" hexmask.long 0x3C 0.--31. 1. "Reserved_8,Reserved_8" rgroup.long 0x40D8++0x27 line.long 0x0 "RGX_CR_USC_SERV_PIXEL_0,RGX_CR_USC_SERV_PIXEL_0" hexmask.long.word 0x0 17.--31. 1. "Reserved_17,Reserved_17" newline bitfld.long 0x0 16. "EMPTY,No Pixel Data Master tasks in USC0 queue" "0,1" newline hexmask.long.word 0x0 0.--15. 1. "COUNT,Number of Pixel Data Master tasks serviced by USC0" line.long 0x4 "RGX_CR_USC_SERV_PIXEL_1,RGX_CR_USC_SERV_PIXEL_1" hexmask.long 0x4 0.--31. 1. "Reserved_17,Reserved_17" line.long 0x8 "RGX_CR_USC_SERV_VERTEX_0,RGX_CR_USC_SERV_VERTEX_0" hexmask.long.word 0x8 17.--31. 1. "Reserved_17,Reserved_17" newline bitfld.long 0x8 16. "EMPTY,No Vertex Data Master tasks in USC0 queue" "0,1" newline hexmask.long.word 0x8 0.--15. 1. "COUNT,Number of Vertex Data Master tasks serviced by USC0" line.long 0xC "RGX_CR_USC_SERV_VERTEX_1,RGX_CR_USC_SERV_VERTEX_1" hexmask.long 0xC 0.--31. 1. "Reserved_17,Reserved_17" line.long 0x10 "RGX_CR_USC_SERV_TESS_PIXEL_0,RGX_CR_USC_SERV_TESS_PIXEL_0" hexmask.long.word 0x10 17.--31. 1. "Reserved_17,Reserved_17" newline bitfld.long 0x10 16. "EMPTY,No Tessellator Pixel Data Master tasks in USC0 queue" "0,1" newline hexmask.long.word 0x10 0.--15. 1. "COUNT,Number of Tessellator Pixel Data Master tasks serviced by USC0" line.long 0x14 "RGX_CR_USC_SERV_TESS_PIXEL_1,RGX_CR_USC_SERV_TESS_PIXEL_1" hexmask.long 0x14 0.--31. 1. "Reserved_17,Reserved_17" line.long 0x18 "RGX_CR_USC_SERV_TESS_VERTEX_0,RGX_CR_USC_SERV_TESS_VERTEX_0" hexmask.long.word 0x18 17.--31. 1. "Reserved_17,Reserved_17" newline bitfld.long 0x18 16. "EMPTY,No Tessellator Vertex Data Master tasks in USC0 queue" "0,1" newline hexmask.long.word 0x18 0.--15. 1. "COUNT,Number of Tessellator Vertex Data Master tasks serviced by USC0" line.long 0x1C "RGX_CR_USC_SERV_TESS_VERTEX_1,RGX_CR_USC_SERV_TESS_VERTEX_1" hexmask.long 0x1C 0.--31. 1. "Reserved_17,Reserved_17" line.long 0x20 "RGX_CR_USC_SERV_COMPUTE_0,RGX_CR_USC_SERV_COMPUTE_0" hexmask.long.word 0x20 17.--31. 1. "Reserved_17,Reserved_17" newline bitfld.long 0x20 16. "EMPTY,No Compute Data Master tasks in USC0 queue" "0,1" newline hexmask.long.word 0x20 0.--15. 1. "COUNT,Number of Compute Data Master tasks serviced by USC0" line.long 0x24 "RGX_CR_USC_SERV_COMPUTE_1,RGX_CR_USC_SERV_COMPUTE_1" hexmask.long 0x24 0.--31. 1. "Reserved_17,Reserved_17" repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) rgroup.long ($2+0x4100)++0x3 line.long 0x0 "RGX_CR_USC_PARTITION_STATUS_$1,RGX_CR_USC_PARTITION_STATUS_0" hexmask.long.word 0x0 16.--31. 1. "CLOSED,Partition closed - end of tile task started" newline hexmask.long.word 0x0 0.--15. 1. "IN_USE,Partition in use" repeat.end rgroup.long 0x4108++0x17 line.long 0x0 "RGX_CR_USC_OLDEST_TASK_STATUS_0,RGX_CR_USC_OLDEST_TASK_STATUS_0" hexmask.long.word 0x0 20.--31. 1. "Reserved_20,Reserved_20" newline hexmask.long.byte 0x0 16.--19. 1. "PASS_NUM,The present pass group" newline bitfld.long 0x0 13.--15. "DM,The task Data Master" "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x0 9.--12. 1. "TILEQUAD,The stream of the task depends on Data Master Vertex: Indicates the patch of the task Pixel >= 4 cluster: The tile ID of the task Pixel 2 cluster: The tile ID and patch concatenated Compute: 0" newline bitfld.long 0x0 7.--8. "STATE,Queue state for entry" "0,1,2,3" newline bitfld.long 0x0 6. "NEW_SD,This task is at the start of a new SD group bit is cleared when the task is first run" "0,1" newline bitfld.long 0x0 5. "TFPU_CS_ED,This task is waiting for a TFPU strobe which has not been satisfied" "0,1" newline bitfld.long 0x0 4. "MCU_CS_ED,This task is waiting for an MCU CS strobe which has not been satisfied" "0,1" newline bitfld.long 0x0 3. "MCU_US_ED,This task is waiting for an MCU US strobe which has not been satisfied" "0,1" newline bitfld.long 0x0 2. "FRAG_TYPE,Is this task a work or state loading type. '1' indicates a Vertex/Fragment/Work type '0' indicates a Shared/ Coefficient/ Control type" "0,1" newline bitfld.long 0x0 1. "PHAS_ISSUE,This task must issue a PHAS instruction which has not yet been seen" "0,1" newline bitfld.long 0x0 0. "PASS_GROUP,Is the task the start of a new pass group" "0,1" line.long 0x4 "RGX_CR_USC_OLDEST_TASK_STATUS_1,RGX_CR_USC_OLDEST_TASK_STATUS_1" hexmask.long 0x4 0.--31. 1. "Reserved_20,Reserved_20" line.long 0x8 "RGX_CR_USC_PARTITION_TILE_STATUS0_0,RGX_CR_USC_PARTITION_TILE_STATUS0_0" bitfld.long 0x8 30.--31. "TILE_ID5,Tile ID for partition 5" "0,1,2,3" newline hexmask.long.byte 0x8 24.--29. 1. "TILE_ID4,Tile ID for partition 4" newline hexmask.long.byte 0x8 18.--23. 1. "TILE_ID3,Tile ID for partition 3" newline hexmask.long.byte 0x8 12.--17. 1. "TILE_ID2,Tile ID for partition 2" newline hexmask.long.byte 0x8 6.--11. 1. "TILE_ID1,Tile ID for partition 1" newline hexmask.long.byte 0x8 0.--5. 1. "TILE_ID0,Tile ID for partition 0" line.long 0xC "RGX_CR_USC_PARTITION_TILE_STATUS0_1,RGX_CR_USC_PARTITION_TILE_STATUS0_1" hexmask.long.word 0xC 16.--31. 1. "Reserved_48,Reserved_48" newline hexmask.long.byte 0xC 10.--15. 1. "TILE_ID7,Tile ID for partition 7" newline hexmask.long.byte 0xC 4.--9. 1. "TILE_ID6,Tile ID for partition 6" newline hexmask.long.byte 0xC 0.--3. 1. "TILE_ID5,Tile ID for partition 5" line.long 0x10 "RGX_CR_USC_PARTITION_TILE_STATUS1_0,RGX_CR_USC_PARTITION_TILE_STATUS1_0" bitfld.long 0x10 30.--31. "TILE_ID13,Tile ID for partition 13" "0,1,2,3" newline hexmask.long.byte 0x10 24.--29. 1. "TILE_ID12,Tile ID for partition 12" newline hexmask.long.byte 0x10 18.--23. 1. "TILE_ID11,Tile ID for partition 11" newline hexmask.long.byte 0x10 12.--17. 1. "TILE_ID10,Tile ID for partition 10" newline hexmask.long.byte 0x10 6.--11. 1. "TILE_ID9,Tile ID for partition 9" newline hexmask.long.byte 0x10 0.--5. 1. "TILE_ID8,Tile ID for partition 8" line.long 0x14 "RGX_CR_USC_PARTITION_TILE_STATUS1_1,RGX_CR_USC_PARTITION_TILE_STATUS1_1" hexmask.long.byte 0x14 28.--31. 1. "Reserved_60,Reserved_60" newline hexmask.long.byte 0x14 22.--27. 1. "TILE_ID17,Tile ID for partition 17" newline hexmask.long.byte 0x14 16.--21. 1. "TILE_ID16,Tile ID for partition 16" newline hexmask.long.byte 0x14 10.--15. 1. "TILE_ID15,Tile ID for partition 15" newline hexmask.long.byte 0x14 4.--9. 1. "TILE_ID14,Tile ID for partition 14" newline hexmask.long.byte 0x14 0.--3. 1. "TILE_ID13,Tile ID for partition 13" repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) rgroup.long ($2+0x4178)++0x3 line.long 0x0 "RGX_CR_USC_DM_SLOT0_$1,Cluster Data Master in Slots" hexmask.long.byte 0x0 28.--31. 1. "SLOT_7,SLOT_7" newline hexmask.long.byte 0x0 24.--27. 1. "SLOT_6,SLOT_6" newline hexmask.long.byte 0x0 20.--23. 1. "SLOT_5,SLOT_5" newline hexmask.long.byte 0x0 16.--19. 1. "SLOT_4,SLOT_4" newline hexmask.long.byte 0x0 12.--15. 1. "SLOT_3,SLOT_3" newline hexmask.long.byte 0x0 8.--11. 1. "SLOT_2,SLOT_2" newline hexmask.long.byte 0x0 4.--7. 1. "SLOT_1,SLOT_1" newline hexmask.long.byte 0x0 0.--3. 1. "SLOT_0,SLOT_0" repeat.end repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) rgroup.long ($2+0x4180)++0x3 line.long 0x0 "RGX_CR_USC_DM_SLOT1_$1,Cluster Data Master in Slots" hexmask.long.byte 0x0 28.--31. 1. "SLOT_7,SLOT_7" newline hexmask.long.byte 0x0 24.--27. 1. "SLOT_6,SLOT_6" newline hexmask.long.byte 0x0 20.--23. 1. "SLOT_5,SLOT_5" newline hexmask.long.byte 0x0 16.--19. 1. "SLOT_4,SLOT_4" newline hexmask.long.byte 0x0 12.--15. 1. "SLOT_3,SLOT_3" newline hexmask.long.byte 0x0 8.--11. 1. "SLOT_2,SLOT_2" newline hexmask.long.byte 0x0 4.--7. 1. "SLOT_1,SLOT_1" newline hexmask.long.byte 0x0 0.--3. 1. "SLOT_0,SLOT_0" repeat.end repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) rgroup.long ($2+0x4188)++0x3 line.long 0x0 "RGX_CR_USC_DM_SLOT2_$1,Cluster Data Master in Slots" hexmask.long.byte 0x0 28.--31. 1. "SLOT_7,SLOT_7" newline hexmask.long.byte 0x0 24.--27. 1. "SLOT_6,SLOT_6" newline hexmask.long.byte 0x0 20.--23. 1. "SLOT_5,SLOT_5" newline hexmask.long.byte 0x0 16.--19. 1. "SLOT_4,SLOT_4" newline hexmask.long.byte 0x0 12.--15. 1. "SLOT_3,SLOT_3" newline hexmask.long.byte 0x0 8.--11. 1. "SLOT_2,SLOT_2" newline hexmask.long.byte 0x0 4.--7. 1. "SLOT_1,SLOT_1" newline hexmask.long.byte 0x0 0.--3. 1. "SLOT_0,SLOT_0" repeat.end repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) rgroup.long ($2+0x4190)++0x3 line.long 0x0 "RGX_CR_USC_DM_SLOT3_$1,Cluster Data Master in Slots" hexmask.long.byte 0x0 28.--31. 1. "SLOT_7,SLOT_7" newline hexmask.long.byte 0x0 24.--27. 1. "SLOT_6,SLOT_6" newline hexmask.long.byte 0x0 20.--23. 1. "SLOT_5,SLOT_5" newline hexmask.long.byte 0x0 16.--19. 1. "SLOT_4,SLOT_4" newline hexmask.long.byte 0x0 12.--15. 1. "SLOT_3,SLOT_3" newline hexmask.long.byte 0x0 8.--11. 1. "SLOT_2,SLOT_2" newline hexmask.long.byte 0x0 4.--7. 1. "SLOT_1,SLOT_1" newline hexmask.long.byte 0x0 0.--3. 1. "SLOT_0,SLOT_0" repeat.end rgroup.long 0x41B8++0x7 line.long 0x0 "RGX_CR_USC_EXCEPTION_0,RGX_CR_USC_EXCEPTION_0" hexmask.long.word 0x0 16.--31. 1. "CODE,Cluster exception code" newline hexmask.long.word 0x0 1.--15. 1. "Reserved_1,Reserved_1" newline bitfld.long 0x0 0. "STATUS,1=Cluster has raised an exception" "?,Cluster has raised an exception" line.long 0x4 "RGX_CR_USC_EXCEPTION_1,RGX_CR_USC_EXCEPTION_1" hexmask.long 0x4 0.--31. 1. "Reserved_32,Reserved_32" rgroup.long 0x41D8++0xFF line.long 0x0 "RGX_CR_USC_SLOT0_0,RGX_CR_USC_SLOT0_0" hexmask.long 0x0 1.--31. 1. "PC,PC" newline bitfld.long 0x0 0. "Reserved_0,Reserved_0" "0,1" line.long 0x4 "RGX_CR_USC_SLOT0_1,RGX_CR_USC_SLOT0_1" hexmask.long 0x4 4.--31. 1. "Reserved_36,Reserved_36" newline hexmask.long.byte 0x4 0.--3. 1. "STATUS,STATUS" line.long 0x8 "RGX_CR_USC_SLOT1_0,RGX_CR_USC_SLOT1_0" hexmask.long 0x8 1.--31. 1. "PC,PC" newline bitfld.long 0x8 0. "Reserved_0,Reserved_0" "0,1" line.long 0xC "RGX_CR_USC_SLOT1_1,RGX_CR_USC_SLOT1_1" hexmask.long 0xC 4.--31. 1. "Reserved_36,Reserved_36" newline hexmask.long.byte 0xC 0.--3. 1. "STATUS,STATUS" line.long 0x10 "RGX_CR_USC_SLOT2_0,RGX_CR_USC_SLOT2_0" hexmask.long 0x10 1.--31. 1. "PC,PC" newline bitfld.long 0x10 0. "Reserved_0,Reserved_0" "0,1" line.long 0x14 "RGX_CR_USC_SLOT2_1,RGX_CR_USC_SLOT2_1" hexmask.long 0x14 4.--31. 1. "Reserved_36,Reserved_36" newline hexmask.long.byte 0x14 0.--3. 1. "STATUS,STATUS" line.long 0x18 "RGX_CR_USC_SLOT3_0,RGX_CR_USC_SLOT3_0" hexmask.long 0x18 1.--31. 1. "PC,PC" newline bitfld.long 0x18 0. "Reserved_0,Reserved_0" "0,1" line.long 0x1C "RGX_CR_USC_SLOT3_1,RGX_CR_USC_SLOT3_1" hexmask.long 0x1C 4.--31. 1. "Reserved_36,Reserved_36" newline hexmask.long.byte 0x1C 0.--3. 1. "STATUS,STATUS" line.long 0x20 "RGX_CR_USC_SLOT4_0,RGX_CR_USC_SLOT4_0" hexmask.long 0x20 1.--31. 1. "PC,PC" newline bitfld.long 0x20 0. "Reserved_0,Reserved_0" "0,1" line.long 0x24 "RGX_CR_USC_SLOT4_1,RGX_CR_USC_SLOT4_1" hexmask.long 0x24 4.--31. 1. "Reserved_36,Reserved_36" newline hexmask.long.byte 0x24 0.--3. 1. "STATUS,STATUS" line.long 0x28 "RGX_CR_USC_SLOT5_0,RGX_CR_USC_SLOT5_0" hexmask.long 0x28 1.--31. 1. "PC,PC" newline bitfld.long 0x28 0. "Reserved_0,Reserved_0" "0,1" line.long 0x2C "RGX_CR_USC_SLOT5_1,RGX_CR_USC_SLOT5_1" hexmask.long 0x2C 4.--31. 1. "Reserved_36,Reserved_36" newline hexmask.long.byte 0x2C 0.--3. 1. "STATUS,STATUS" line.long 0x30 "RGX_CR_USC_SLOT6_0,RGX_CR_USC_SLOT6_0" hexmask.long 0x30 1.--31. 1. "PC,PC" newline bitfld.long 0x30 0. "Reserved_0,Reserved_0" "0,1" line.long 0x34 "RGX_CR_USC_SLOT6_1,RGX_CR_USC_SLOT6_1" hexmask.long 0x34 4.--31. 1. "Reserved_36,Reserved_36" newline hexmask.long.byte 0x34 0.--3. 1. "STATUS,STATUS" line.long 0x38 "RGX_CR_USC_SLOT7_0,RGX_CR_USC_SLOT7_0" hexmask.long 0x38 1.--31. 1. "PC,PC" newline bitfld.long 0x38 0. "Reserved_0,Reserved_0" "0,1" line.long 0x3C "RGX_CR_USC_SLOT7_1,RGX_CR_USC_SLOT7_1" hexmask.long 0x3C 4.--31. 1. "Reserved_36,Reserved_36" newline hexmask.long.byte 0x3C 0.--3. 1. "STATUS,STATUS" line.long 0x40 "RGX_CR_USC_SLOT8_0,RGX_CR_USC_SLOT8_0" hexmask.long 0x40 1.--31. 1. "PC,PC" newline bitfld.long 0x40 0. "Reserved_0,Reserved_0" "0,1" line.long 0x44 "RGX_CR_USC_SLOT8_1,RGX_CR_USC_SLOT8_1" hexmask.long 0x44 4.--31. 1. "Reserved_36,Reserved_36" newline hexmask.long.byte 0x44 0.--3. 1. "STATUS,STATUS" line.long 0x48 "RGX_CR_USC_SLOT9_0,RGX_CR_USC_SLOT9_0" hexmask.long 0x48 1.--31. 1. "PC,PC" newline bitfld.long 0x48 0. "Reserved_0,Reserved_0" "0,1" line.long 0x4C "RGX_CR_USC_SLOT9_1,RGX_CR_USC_SLOT9_1" hexmask.long 0x4C 4.--31. 1. "Reserved_36,Reserved_36" newline hexmask.long.byte 0x4C 0.--3. 1. "STATUS,STATUS" line.long 0x50 "RGX_CR_USC_SLOT10_0,RGX_CR_USC_SLOT10_0" hexmask.long 0x50 1.--31. 1. "PC,PC" newline bitfld.long 0x50 0. "Reserved_0,Reserved_0" "0,1" line.long 0x54 "RGX_CR_USC_SLOT10_1,RGX_CR_USC_SLOT10_1" hexmask.long 0x54 4.--31. 1. "Reserved_36,Reserved_36" newline hexmask.long.byte 0x54 0.--3. 1. "STATUS,STATUS" line.long 0x58 "RGX_CR_USC_SLOT11_0,RGX_CR_USC_SLOT11_0" hexmask.long 0x58 1.--31. 1. "PC,PC" newline bitfld.long 0x58 0. "Reserved_0,Reserved_0" "0,1" line.long 0x5C "RGX_CR_USC_SLOT11_1,RGX_CR_USC_SLOT11_1" hexmask.long 0x5C 4.--31. 1. "Reserved_36,Reserved_36" newline hexmask.long.byte 0x5C 0.--3. 1. "STATUS,STATUS" line.long 0x60 "RGX_CR_USC_SLOT12_0,RGX_CR_USC_SLOT12_0" hexmask.long 0x60 1.--31. 1. "PC,PC" newline bitfld.long 0x60 0. "Reserved_0,Reserved_0" "0,1" line.long 0x64 "RGX_CR_USC_SLOT12_1,RGX_CR_USC_SLOT12_1" hexmask.long 0x64 4.--31. 1. "Reserved_36,Reserved_36" newline hexmask.long.byte 0x64 0.--3. 1. "STATUS,STATUS" line.long 0x68 "RGX_CR_USC_SLOT13_0,RGX_CR_USC_SLOT13_0" hexmask.long 0x68 1.--31. 1. "PC,PC" newline bitfld.long 0x68 0. "Reserved_0,Reserved_0" "0,1" line.long 0x6C "RGX_CR_USC_SLOT13_1,RGX_CR_USC_SLOT13_1" hexmask.long 0x6C 4.--31. 1. "Reserved_36,Reserved_36" newline hexmask.long.byte 0x6C 0.--3. 1. "STATUS,STATUS" line.long 0x70 "RGX_CR_USC_SLOT14_0,RGX_CR_USC_SLOT14_0" hexmask.long 0x70 1.--31. 1. "PC,PC" newline bitfld.long 0x70 0. "Reserved_0,Reserved_0" "0,1" line.long 0x74 "RGX_CR_USC_SLOT14_1,RGX_CR_USC_SLOT14_1" hexmask.long 0x74 4.--31. 1. "Reserved_36,Reserved_36" newline hexmask.long.byte 0x74 0.--3. 1. "STATUS,STATUS" line.long 0x78 "RGX_CR_USC_SLOT15_0,RGX_CR_USC_SLOT15_0" hexmask.long 0x78 1.--31. 1. "PC,PC" newline bitfld.long 0x78 0. "Reserved_0,Reserved_0" "0,1" line.long 0x7C "RGX_CR_USC_SLOT15_1,RGX_CR_USC_SLOT15_1" hexmask.long 0x7C 4.--31. 1. "Reserved_36,Reserved_36" newline hexmask.long.byte 0x7C 0.--3. 1. "STATUS,STATUS" line.long 0x80 "RGX_CR_USC_SLOT16_0,RGX_CR_USC_SLOT16_0" hexmask.long 0x80 1.--31. 1. "PC,PC" newline bitfld.long 0x80 0. "Reserved_0,Reserved_0" "0,1" line.long 0x84 "RGX_CR_USC_SLOT16_1,RGX_CR_USC_SLOT16_1" hexmask.long 0x84 4.--31. 1. "Reserved_36,Reserved_36" newline hexmask.long.byte 0x84 0.--3. 1. "STATUS,STATUS" line.long 0x88 "RGX_CR_USC_SLOT17_0,RGX_CR_USC_SLOT17_0" hexmask.long 0x88 1.--31. 1. "PC,PC" newline bitfld.long 0x88 0. "Reserved_0,Reserved_0" "0,1" line.long 0x8C "RGX_CR_USC_SLOT17_1,RGX_CR_USC_SLOT17_1" hexmask.long 0x8C 4.--31. 1. "Reserved_36,Reserved_36" newline hexmask.long.byte 0x8C 0.--3. 1. "STATUS,STATUS" line.long 0x90 "RGX_CR_USC_SLOT18_0,RGX_CR_USC_SLOT18_0" hexmask.long 0x90 1.--31. 1. "PC,PC" newline bitfld.long 0x90 0. "Reserved_0,Reserved_0" "0,1" line.long 0x94 "RGX_CR_USC_SLOT18_1,RGX_CR_USC_SLOT18_1" hexmask.long 0x94 4.--31. 1. "Reserved_36,Reserved_36" newline hexmask.long.byte 0x94 0.--3. 1. "STATUS,STATUS" line.long 0x98 "RGX_CR_USC_SLOT19_0,RGX_CR_USC_SLOT19_0" hexmask.long 0x98 1.--31. 1. "PC,PC" newline bitfld.long 0x98 0. "Reserved_0,Reserved_0" "0,1" line.long 0x9C "RGX_CR_USC_SLOT19_1,RGX_CR_USC_SLOT19_1" hexmask.long 0x9C 4.--31. 1. "Reserved_36,Reserved_36" newline hexmask.long.byte 0x9C 0.--3. 1. "STATUS,STATUS" line.long 0xA0 "RGX_CR_USC_SLOT20_0,RGX_CR_USC_SLOT20_0" hexmask.long 0xA0 1.--31. 1. "PC,PC" newline bitfld.long 0xA0 0. "Reserved_0,Reserved_0" "0,1" line.long 0xA4 "RGX_CR_USC_SLOT20_1,RGX_CR_USC_SLOT20_1" hexmask.long 0xA4 4.--31. 1. "Reserved_36,Reserved_36" newline hexmask.long.byte 0xA4 0.--3. 1. "STATUS,STATUS" line.long 0xA8 "RGX_CR_USC_SLOT21_0,RGX_CR_USC_SLOT21_0" hexmask.long 0xA8 1.--31. 1. "PC,PC" newline bitfld.long 0xA8 0. "Reserved_0,Reserved_0" "0,1" line.long 0xAC "RGX_CR_USC_SLOT21_1,RGX_CR_USC_SLOT21_1" hexmask.long 0xAC 4.--31. 1. "Reserved_36,Reserved_36" newline hexmask.long.byte 0xAC 0.--3. 1. "STATUS,STATUS" line.long 0xB0 "RGX_CR_USC_SLOT22_0,RGX_CR_USC_SLOT22_0" hexmask.long 0xB0 1.--31. 1. "PC,PC" newline bitfld.long 0xB0 0. "Reserved_0,Reserved_0" "0,1" line.long 0xB4 "RGX_CR_USC_SLOT22_1,RGX_CR_USC_SLOT22_1" hexmask.long 0xB4 4.--31. 1. "Reserved_36,Reserved_36" newline hexmask.long.byte 0xB4 0.--3. 1. "STATUS,STATUS" line.long 0xB8 "RGX_CR_USC_SLOT23_0,RGX_CR_USC_SLOT23_0" hexmask.long 0xB8 1.--31. 1. "PC,PC" newline bitfld.long 0xB8 0. "Reserved_0,Reserved_0" "0,1" line.long 0xBC "RGX_CR_USC_SLOT23_1,RGX_CR_USC_SLOT23_1" hexmask.long 0xBC 4.--31. 1. "Reserved_36,Reserved_36" newline hexmask.long.byte 0xBC 0.--3. 1. "STATUS,STATUS" line.long 0xC0 "RGX_CR_USC_SLOT24_0,RGX_CR_USC_SLOT24_0" hexmask.long 0xC0 1.--31. 1. "PC,PC" newline bitfld.long 0xC0 0. "Reserved_0,Reserved_0" "0,1" line.long 0xC4 "RGX_CR_USC_SLOT24_1,RGX_CR_USC_SLOT24_1" hexmask.long 0xC4 4.--31. 1. "Reserved_36,Reserved_36" newline hexmask.long.byte 0xC4 0.--3. 1. "STATUS,STATUS" line.long 0xC8 "RGX_CR_USC_SLOT25_0,RGX_CR_USC_SLOT25_0" hexmask.long 0xC8 1.--31. 1. "PC,PC" newline bitfld.long 0xC8 0. "Reserved_0,Reserved_0" "0,1" line.long 0xCC "RGX_CR_USC_SLOT25_1,RGX_CR_USC_SLOT25_1" hexmask.long 0xCC 4.--31. 1. "Reserved_36,Reserved_36" newline hexmask.long.byte 0xCC 0.--3. 1. "STATUS,STATUS" line.long 0xD0 "RGX_CR_USC_SLOT26_0,RGX_CR_USC_SLOT26_0" hexmask.long 0xD0 1.--31. 1. "PC,PC" newline bitfld.long 0xD0 0. "Reserved_0,Reserved_0" "0,1" line.long 0xD4 "RGX_CR_USC_SLOT26_1,RGX_CR_USC_SLOT26_1" hexmask.long 0xD4 4.--31. 1. "Reserved_36,Reserved_36" newline hexmask.long.byte 0xD4 0.--3. 1. "STATUS,STATUS" line.long 0xD8 "RGX_CR_USC_SLOT27_0,RGX_CR_USC_SLOT27_0" hexmask.long 0xD8 1.--31. 1. "PC,PC" newline bitfld.long 0xD8 0. "Reserved_0,Reserved_0" "0,1" line.long 0xDC "RGX_CR_USC_SLOT27_1,RGX_CR_USC_SLOT27_1" hexmask.long 0xDC 4.--31. 1. "Reserved_36,Reserved_36" newline hexmask.long.byte 0xDC 0.--3. 1. "STATUS,STATUS" line.long 0xE0 "RGX_CR_USC_SLOT28_0,RGX_CR_USC_SLOT28_0" hexmask.long 0xE0 1.--31. 1. "PC,PC" newline bitfld.long 0xE0 0. "Reserved_0,Reserved_0" "0,1" line.long 0xE4 "RGX_CR_USC_SLOT28_1,RGX_CR_USC_SLOT28_1" hexmask.long 0xE4 4.--31. 1. "Reserved_36,Reserved_36" newline hexmask.long.byte 0xE4 0.--3. 1. "STATUS,STATUS" line.long 0xE8 "RGX_CR_USC_SLOT29_0,RGX_CR_USC_SLOT29_0" hexmask.long 0xE8 1.--31. 1. "PC,PC" newline bitfld.long 0xE8 0. "Reserved_0,Reserved_0" "0,1" line.long 0xEC "RGX_CR_USC_SLOT29_1,RGX_CR_USC_SLOT29_1" hexmask.long 0xEC 4.--31. 1. "Reserved_36,Reserved_36" newline hexmask.long.byte 0xEC 0.--3. 1. "STATUS,STATUS" line.long 0xF0 "RGX_CR_USC_SLOT30_0,RGX_CR_USC_SLOT30_0" hexmask.long 0xF0 1.--31. 1. "PC,PC" newline bitfld.long 0xF0 0. "Reserved_0,Reserved_0" "0,1" line.long 0xF4 "RGX_CR_USC_SLOT30_1,RGX_CR_USC_SLOT30_1" hexmask.long 0xF4 4.--31. 1. "Reserved_36,Reserved_36" newline hexmask.long.byte 0xF4 0.--3. 1. "STATUS,STATUS" line.long 0xF8 "RGX_CR_USC_SLOT31_0,RGX_CR_USC_SLOT31_0" hexmask.long 0xF8 1.--31. 1. "PC,PC" newline bitfld.long 0xF8 0. "Reserved_0,Reserved_0" "0,1" line.long 0xFC "RGX_CR_USC_SLOT31_1,RGX_CR_USC_SLOT31_1" hexmask.long 0xFC 4.--31. 1. "Reserved_36,Reserved_36" newline hexmask.long.byte 0xFC 0.--3. 1. "STATUS,STATUS" repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) group.long ($2+0x42E0)++0x3 line.long 0x0 "RGX_CR_USC_CLEAR_REGISTER4_$1,RGX_CR_USC_CLEAR_REGISTER4_0" hexmask.long 0x0 0.--31. 1. "VAL,Clear Colour register 4" repeat.end repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) group.long ($2+0x42E8)++0x3 line.long 0x0 "RGX_CR_USC_CLEAR_REGISTER5_$1,RGX_CR_USC_CLEAR_REGISTER5_0" hexmask.long 0x0 0.--31. 1. "VAL,Clear Colour register 5" repeat.end repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) group.long ($2+0x42F0)++0x3 line.long 0x0 "RGX_CR_USC_CLEAR_REGISTER6_$1,RGX_CR_USC_CLEAR_REGISTER6_0" hexmask.long 0x0 0.--31. 1. "VAL,Clear Colour register 6" repeat.end repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) group.long ($2+0x42F8)++0x3 line.long 0x0 "RGX_CR_USC_CLEAR_REGISTER7_$1,RGX_CR_USC_CLEAR_REGISTER7_0" hexmask.long 0x0 0.--31. 1. "VAL,Clear Colour register 7" repeat.end rgroup.long 0x4300++0xFF line.long 0x0 "RGX_CR_USC_SLOT32_0,RGX_CR_USC_SLOT32_0" hexmask.long 0x0 1.--31. 1. "PC,PC" newline bitfld.long 0x0 0. "Reserved_0,Reserved_0" "0,1" line.long 0x4 "RGX_CR_USC_SLOT32_1,RGX_CR_USC_SLOT32_1" hexmask.long 0x4 4.--31. 1. "Reserved_36,Reserved_36" newline hexmask.long.byte 0x4 0.--3. 1. "STATUS,STATUS" line.long 0x8 "RGX_CR_USC_SLOT33_0,RGX_CR_USC_SLOT33_0" hexmask.long 0x8 1.--31. 1. "PC,PC" newline bitfld.long 0x8 0. "Reserved_0,Reserved_0" "0,1" line.long 0xC "RGX_CR_USC_SLOT33_1,RGX_CR_USC_SLOT33_1" hexmask.long 0xC 4.--31. 1. "Reserved_36,Reserved_36" newline hexmask.long.byte 0xC 0.--3. 1. "STATUS,STATUS" line.long 0x10 "RGX_CR_USC_SLOT34_0,RGX_CR_USC_SLOT34_0" hexmask.long 0x10 1.--31. 1. "PC,PC" newline bitfld.long 0x10 0. "Reserved_0,Reserved_0" "0,1" line.long 0x14 "RGX_CR_USC_SLOT34_1,RGX_CR_USC_SLOT34_1" hexmask.long 0x14 4.--31. 1. "Reserved_36,Reserved_36" newline hexmask.long.byte 0x14 0.--3. 1. "STATUS,STATUS" line.long 0x18 "RGX_CR_USC_SLOT35_0,RGX_CR_USC_SLOT35_0" hexmask.long 0x18 1.--31. 1. "PC,PC" newline bitfld.long 0x18 0. "Reserved_0,Reserved_0" "0,1" line.long 0x1C "RGX_CR_USC_SLOT35_1,RGX_CR_USC_SLOT35_1" hexmask.long 0x1C 4.--31. 1. "Reserved_36,Reserved_36" newline hexmask.long.byte 0x1C 0.--3. 1. "STATUS,STATUS" line.long 0x20 "RGX_CR_USC_SLOT36_0,RGX_CR_USC_SLOT36_0" hexmask.long 0x20 1.--31. 1. "PC,PC" newline bitfld.long 0x20 0. "Reserved_0,Reserved_0" "0,1" line.long 0x24 "RGX_CR_USC_SLOT36_1,RGX_CR_USC_SLOT36_1" hexmask.long 0x24 4.--31. 1. "Reserved_36,Reserved_36" newline hexmask.long.byte 0x24 0.--3. 1. "STATUS,STATUS" line.long 0x28 "RGX_CR_USC_SLOT37_0,RGX_CR_USC_SLOT37_0" hexmask.long 0x28 1.--31. 1. "PC,PC" newline bitfld.long 0x28 0. "Reserved_0,Reserved_0" "0,1" line.long 0x2C "RGX_CR_USC_SLOT37_1,RGX_CR_USC_SLOT37_1" hexmask.long 0x2C 4.--31. 1. "Reserved_36,Reserved_36" newline hexmask.long.byte 0x2C 0.--3. 1. "STATUS,STATUS" line.long 0x30 "RGX_CR_USC_SLOT38_0,RGX_CR_USC_SLOT38_0" hexmask.long 0x30 1.--31. 1. "PC,PC" newline bitfld.long 0x30 0. "Reserved_0,Reserved_0" "0,1" line.long 0x34 "RGX_CR_USC_SLOT38_1,RGX_CR_USC_SLOT38_1" hexmask.long 0x34 4.--31. 1. "Reserved_36,Reserved_36" newline hexmask.long.byte 0x34 0.--3. 1. "STATUS,STATUS" line.long 0x38 "RGX_CR_USC_SLOT39_0,RGX_CR_USC_SLOT39_0" hexmask.long 0x38 1.--31. 1. "PC,PC" newline bitfld.long 0x38 0. "Reserved_0,Reserved_0" "0,1" line.long 0x3C "RGX_CR_USC_SLOT39_1,RGX_CR_USC_SLOT39_1" hexmask.long 0x3C 4.--31. 1. "Reserved_36,Reserved_36" newline hexmask.long.byte 0x3C 0.--3. 1. "STATUS,STATUS" line.long 0x40 "RGX_CR_USC_SLOT40_0,RGX_CR_USC_SLOT40_0" hexmask.long 0x40 1.--31. 1. "PC,PC" newline bitfld.long 0x40 0. "Reserved_0,Reserved_0" "0,1" line.long 0x44 "RGX_CR_USC_SLOT40_1,RGX_CR_USC_SLOT40_1" hexmask.long 0x44 4.--31. 1. "Reserved_36,Reserved_36" newline hexmask.long.byte 0x44 0.--3. 1. "STATUS,STATUS" line.long 0x48 "RGX_CR_USC_SLOT41_0,RGX_CR_USC_SLOT41_0" hexmask.long 0x48 1.--31. 1. "PC,PC" newline bitfld.long 0x48 0. "Reserved_0,Reserved_0" "0,1" line.long 0x4C "RGX_CR_USC_SLOT41_1,RGX_CR_USC_SLOT41_1" hexmask.long 0x4C 4.--31. 1. "Reserved_36,Reserved_36" newline hexmask.long.byte 0x4C 0.--3. 1. "STATUS,STATUS" line.long 0x50 "RGX_CR_USC_SLOT42_0,RGX_CR_USC_SLOT42_0" hexmask.long 0x50 1.--31. 1. "PC,PC" newline bitfld.long 0x50 0. "Reserved_0,Reserved_0" "0,1" line.long 0x54 "RGX_CR_USC_SLOT42_1,RGX_CR_USC_SLOT42_1" hexmask.long 0x54 4.--31. 1. "Reserved_36,Reserved_36" newline hexmask.long.byte 0x54 0.--3. 1. "STATUS,STATUS" line.long 0x58 "RGX_CR_USC_SLOT43_0,RGX_CR_USC_SLOT43_0" hexmask.long 0x58 1.--31. 1. "PC,PC" newline bitfld.long 0x58 0. "Reserved_0,Reserved_0" "0,1" line.long 0x5C "RGX_CR_USC_SLOT43_1,RGX_CR_USC_SLOT43_1" hexmask.long 0x5C 4.--31. 1. "Reserved_36,Reserved_36" newline hexmask.long.byte 0x5C 0.--3. 1. "STATUS,STATUS" line.long 0x60 "RGX_CR_USC_SLOT44_0,RGX_CR_USC_SLOT44_0" hexmask.long 0x60 1.--31. 1. "PC,PC" newline bitfld.long 0x60 0. "Reserved_0,Reserved_0" "0,1" line.long 0x64 "RGX_CR_USC_SLOT44_1,RGX_CR_USC_SLOT44_1" hexmask.long 0x64 4.--31. 1. "Reserved_36,Reserved_36" newline hexmask.long.byte 0x64 0.--3. 1. "STATUS,STATUS" line.long 0x68 "RGX_CR_USC_SLOT45_0,RGX_CR_USC_SLOT45_0" hexmask.long 0x68 1.--31. 1. "PC,PC" newline bitfld.long 0x68 0. "Reserved_0,Reserved_0" "0,1" line.long 0x6C "RGX_CR_USC_SLOT45_1,RGX_CR_USC_SLOT45_1" hexmask.long 0x6C 4.--31. 1. "Reserved_36,Reserved_36" newline hexmask.long.byte 0x6C 0.--3. 1. "STATUS,STATUS" line.long 0x70 "RGX_CR_USC_SLOT46_0,RGX_CR_USC_SLOT46_0" hexmask.long 0x70 1.--31. 1. "PC,PC" newline bitfld.long 0x70 0. "Reserved_0,Reserved_0" "0,1" line.long 0x74 "RGX_CR_USC_SLOT46_1,RGX_CR_USC_SLOT46_1" hexmask.long 0x74 4.--31. 1. "Reserved_36,Reserved_36" newline hexmask.long.byte 0x74 0.--3. 1. "STATUS,STATUS" line.long 0x78 "RGX_CR_USC_SLOT47_0,RGX_CR_USC_SLOT47_0" hexmask.long 0x78 1.--31. 1. "PC,PC" newline bitfld.long 0x78 0. "Reserved_0,Reserved_0" "0,1" line.long 0x7C "RGX_CR_USC_SLOT47_1,RGX_CR_USC_SLOT47_1" hexmask.long 0x7C 4.--31. 1. "Reserved_36,Reserved_36" newline hexmask.long.byte 0x7C 0.--3. 1. "STATUS,STATUS" line.long 0x80 "RGX_CR_USC_SLOT48_0,RGX_CR_USC_SLOT48_0" hexmask.long 0x80 1.--31. 1. "PC,PC" newline bitfld.long 0x80 0. "Reserved_0,Reserved_0" "0,1" line.long 0x84 "RGX_CR_USC_SLOT48_1,RGX_CR_USC_SLOT48_1" hexmask.long 0x84 4.--31. 1. "Reserved_36,Reserved_36" newline hexmask.long.byte 0x84 0.--3. 1. "STATUS,STATUS" line.long 0x88 "RGX_CR_USC_SLOT49_0,RGX_CR_USC_SLOT49_0" hexmask.long 0x88 1.--31. 1. "PC,PC" newline bitfld.long 0x88 0. "Reserved_0,Reserved_0" "0,1" line.long 0x8C "RGX_CR_USC_SLOT49_1,RGX_CR_USC_SLOT49_1" hexmask.long 0x8C 4.--31. 1. "Reserved_36,Reserved_36" newline hexmask.long.byte 0x8C 0.--3. 1. "STATUS,STATUS" line.long 0x90 "RGX_CR_USC_SLOT50_0,RGX_CR_USC_SLOT50_0" hexmask.long 0x90 1.--31. 1. "PC,PC" newline bitfld.long 0x90 0. "Reserved_0,Reserved_0" "0,1" line.long 0x94 "RGX_CR_USC_SLOT50_1,RGX_CR_USC_SLOT50_1" hexmask.long 0x94 4.--31. 1. "Reserved_36,Reserved_36" newline hexmask.long.byte 0x94 0.--3. 1. "STATUS,STATUS" line.long 0x98 "RGX_CR_USC_SLOT51_0,RGX_CR_USC_SLOT51_0" hexmask.long 0x98 1.--31. 1. "PC,PC" newline bitfld.long 0x98 0. "Reserved_0,Reserved_0" "0,1" line.long 0x9C "RGX_CR_USC_SLOT51_1,RGX_CR_USC_SLOT51_1" hexmask.long 0x9C 4.--31. 1. "Reserved_36,Reserved_36" newline hexmask.long.byte 0x9C 0.--3. 1. "STATUS,STATUS" line.long 0xA0 "RGX_CR_USC_SLOT52_0,RGX_CR_USC_SLOT52_0" hexmask.long 0xA0 1.--31. 1. "PC,PC" newline bitfld.long 0xA0 0. "Reserved_0,Reserved_0" "0,1" line.long 0xA4 "RGX_CR_USC_SLOT52_1,RGX_CR_USC_SLOT52_1" hexmask.long 0xA4 4.--31. 1. "Reserved_36,Reserved_36" newline hexmask.long.byte 0xA4 0.--3. 1. "STATUS,STATUS" line.long 0xA8 "RGX_CR_USC_SLOT53_0,RGX_CR_USC_SLOT53_0" hexmask.long 0xA8 1.--31. 1. "PC,PC" newline bitfld.long 0xA8 0. "Reserved_0,Reserved_0" "0,1" line.long 0xAC "RGX_CR_USC_SLOT53_1,RGX_CR_USC_SLOT53_1" hexmask.long 0xAC 4.--31. 1. "Reserved_36,Reserved_36" newline hexmask.long.byte 0xAC 0.--3. 1. "STATUS,STATUS" line.long 0xB0 "RGX_CR_USC_SLOT54_0,RGX_CR_USC_SLOT54_0" hexmask.long 0xB0 1.--31. 1. "PC,PC" newline bitfld.long 0xB0 0. "Reserved_0,Reserved_0" "0,1" line.long 0xB4 "RGX_CR_USC_SLOT54_1,RGX_CR_USC_SLOT54_1" hexmask.long 0xB4 4.--31. 1. "Reserved_36,Reserved_36" newline hexmask.long.byte 0xB4 0.--3. 1. "STATUS,STATUS" line.long 0xB8 "RGX_CR_USC_SLOT55_0,RGX_CR_USC_SLOT55_0" hexmask.long 0xB8 1.--31. 1. "PC,PC" newline bitfld.long 0xB8 0. "Reserved_0,Reserved_0" "0,1" line.long 0xBC "RGX_CR_USC_SLOT55_1,RGX_CR_USC_SLOT55_1" hexmask.long 0xBC 4.--31. 1. "Reserved_36,Reserved_36" newline hexmask.long.byte 0xBC 0.--3. 1. "STATUS,STATUS" line.long 0xC0 "RGX_CR_USC_SLOT56_0,RGX_CR_USC_SLOT56_0" hexmask.long 0xC0 1.--31. 1. "PC,PC" newline bitfld.long 0xC0 0. "Reserved_0,Reserved_0" "0,1" line.long 0xC4 "RGX_CR_USC_SLOT56_1,RGX_CR_USC_SLOT56_1" hexmask.long 0xC4 4.--31. 1. "Reserved_36,Reserved_36" newline hexmask.long.byte 0xC4 0.--3. 1. "STATUS,STATUS" line.long 0xC8 "RGX_CR_USC_SLOT57_0,RGX_CR_USC_SLOT57_0" hexmask.long 0xC8 1.--31. 1. "PC,PC" newline bitfld.long 0xC8 0. "Reserved_0,Reserved_0" "0,1" line.long 0xCC "RGX_CR_USC_SLOT57_1,RGX_CR_USC_SLOT57_1" hexmask.long 0xCC 4.--31. 1. "Reserved_36,Reserved_36" newline hexmask.long.byte 0xCC 0.--3. 1. "STATUS,STATUS" line.long 0xD0 "RGX_CR_USC_SLOT58_0,RGX_CR_USC_SLOT58_0" hexmask.long 0xD0 1.--31. 1. "PC,PC" newline bitfld.long 0xD0 0. "Reserved_0,Reserved_0" "0,1" line.long 0xD4 "RGX_CR_USC_SLOT58_1,RGX_CR_USC_SLOT58_1" hexmask.long 0xD4 4.--31. 1. "Reserved_36,Reserved_36" newline hexmask.long.byte 0xD4 0.--3. 1. "STATUS,STATUS" line.long 0xD8 "RGX_CR_USC_SLOT59_0,RGX_CR_USC_SLOT59_0" hexmask.long 0xD8 1.--31. 1. "PC,PC" newline bitfld.long 0xD8 0. "Reserved_0,Reserved_0" "0,1" line.long 0xDC "RGX_CR_USC_SLOT59_1,RGX_CR_USC_SLOT59_1" hexmask.long 0xDC 4.--31. 1. "Reserved_36,Reserved_36" newline hexmask.long.byte 0xDC 0.--3. 1. "STATUS,STATUS" line.long 0xE0 "RGX_CR_USC_SLOT60_0,RGX_CR_USC_SLOT60_0" hexmask.long 0xE0 1.--31. 1. "PC,PC" newline bitfld.long 0xE0 0. "Reserved_0,Reserved_0" "0,1" line.long 0xE4 "RGX_CR_USC_SLOT60_1,RGX_CR_USC_SLOT60_1" hexmask.long 0xE4 4.--31. 1. "Reserved_36,Reserved_36" newline hexmask.long.byte 0xE4 0.--3. 1. "STATUS,STATUS" line.long 0xE8 "RGX_CR_USC_SLOT61_0,RGX_CR_USC_SLOT61_0" hexmask.long 0xE8 1.--31. 1. "PC,PC" newline bitfld.long 0xE8 0. "Reserved_0,Reserved_0" "0,1" line.long 0xEC "RGX_CR_USC_SLOT61_1,RGX_CR_USC_SLOT61_1" hexmask.long 0xEC 4.--31. 1. "Reserved_36,Reserved_36" newline hexmask.long.byte 0xEC 0.--3. 1. "STATUS,STATUS" line.long 0xF0 "RGX_CR_USC_SLOT62_0,RGX_CR_USC_SLOT62_0" hexmask.long 0xF0 1.--31. 1. "PC,PC" newline bitfld.long 0xF0 0. "Reserved_0,Reserved_0" "0,1" line.long 0xF4 "RGX_CR_USC_SLOT62_1,RGX_CR_USC_SLOT62_1" hexmask.long 0xF4 4.--31. 1. "Reserved_36,Reserved_36" newline hexmask.long.byte 0xF4 0.--3. 1. "STATUS,STATUS" line.long 0xF8 "RGX_CR_USC_SLOT63_0,RGX_CR_USC_SLOT63_0" hexmask.long 0xF8 1.--31. 1. "PC,PC" newline bitfld.long 0xF8 0. "Reserved_0,Reserved_0" "0,1" line.long 0xFC "RGX_CR_USC_SLOT63_1,RGX_CR_USC_SLOT63_1" hexmask.long 0xFC 4.--31. 1. "Reserved_36,Reserved_36" newline hexmask.long.byte 0xFC 0.--3. 1. "STATUS,STATUS" group.long 0x4500++0x17 line.long 0x0 "RGX_CR_USC_BREAKPOINT1_0,RGX_CR_USC_BREAKPOINT1_0" hexmask.long 0x0 1.--31. 1. "ADDR,Breakpoint Address" newline bitfld.long 0x0 0. "Reserved_0,Reserved_0" "0,1" line.long 0x4 "RGX_CR_USC_BREAKPOINT1_1,RGX_CR_USC_BREAKPOINT1_1" hexmask.long 0x4 0.--31. 1. "Reserved_32,Reserved_32" line.long 0x8 "RGX_CR_USC_BREAKPOINT1_HANDLER_0,RGX_CR_USC_BREAKPOINT1_HANDLER_0" hexmask.long 0x8 1.--31. 1. "ADDR,Breakpoint Handler Address" newline bitfld.long 0x8 0. "Reserved_0,Reserved_0" "0,1" line.long 0xC "RGX_CR_USC_BREAKPOINT1_HANDLER_1,RGX_CR_USC_BREAKPOINT1_HANDLER_1" hexmask.long 0xC 0.--31. 1. "Reserved_32,Reserved_32" line.long 0x10 "RGX_CR_USC_BREAKPOINT1_CTRL_0,RGX_CR_USC_BREAKPOINT1_CTRL_0" hexmask.long 0x10 4.--31. 1. "Reserved_4,Reserved_4" newline bitfld.long 0x10 3. "ENABLE,0 = Breakpoint disabled 1 = Breakpoint enabled" "Breakpoint disabled,Breakpoint enabled" newline bitfld.long 0x10 0.--2. "DM,Data Master of Breakpoint" "0,1,2,3,4,5,6,7" line.long 0x14 "RGX_CR_USC_BREAKPOINT1_CTRL_1,RGX_CR_USC_BREAKPOINT1_CTRL_1" hexmask.long 0x14 0.--31. 1. "Reserved_4,Reserved_4" rgroup.long 0x45D8++0x7 line.long 0x0 "RGX_CR_USC_IDLE_0,RGX_CR_USC_IDLE_0" hexmask.long.tbyte 0x0 10.--31. 1. "Reserved_10,Reserved_10" newline bitfld.long 0x0 9. "USCITR,USCITR idle" "0,1" newline bitfld.long 0x0 8. "USCDMA,USCDMA idle" "0,1" newline bitfld.long 0x0 7. "USCFS,USCFS idle" "0,1" newline bitfld.long 0x0 6. "USCCS,USCCS idle" "0,1" newline bitfld.long 0x0 5. "USCPD3,USCPD idle" "0,1" newline bitfld.long 0x0 4. "USCPD2,USCPD idle" "0,1" newline bitfld.long 0x0 3. "USCPD1,USCPD idle" "0,1" newline bitfld.long 0x0 2. "USCPD0,USCPD idle" "0,1" newline bitfld.long 0x0 1. "USCPC,USCPC idle" "0,1" newline bitfld.long 0x0 0. "USCC,USCC idle" "0,1" line.long 0x4 "RGX_CR_USC_IDLE_1,RGX_CR_USC_IDLE_1" hexmask.long 0x4 0.--31. 1. "Reserved_10,Reserved_10" group.long 0x45E8++0x17 line.long 0x0 "RGX_CR_USC_ITRCOEFF_CACHE_0,USC Iterator Coefficient Cache Bypass bit" hexmask.long 0x0 1.--31. 1. "Reserved_1,Reserved_1" newline bitfld.long 0x0 0. "BYPASS,Bypass bit of the coefficient cache" "0,1" line.long 0x4 "RGX_CR_USC_ITRCOEFF_CACHE_1,USC Iterator Coefficient Cache Bypass bit" hexmask.long 0x4 0.--31. 1. "Reserved_1,Reserved_1" line.long 0x8 "RGX_CR_USC_ITRSMP_STATE_CACHE_0,USC ITRSMP State Cache Bypass bit" hexmask.long 0x8 1.--31. 1. "Reserved_1,Reserved_1" newline bitfld.long 0x8 0. "BYPASS,Bypass bit of the state cache" "0,1" line.long 0xC "RGX_CR_USC_ITRSMP_STATE_CACHE_1,USC ITRSMP State Cache Bypass bit" hexmask.long 0xC 0.--31. 1. "Reserved_1,Reserved_1" line.long 0x10 "RGX_CR_USC_ITRSMP_PRIORITY_0,USC ITRSMP priority information" hexmask.long 0x10 2.--31. 1. "Reserved_2,Reserved_2" newline bitfld.long 0x10 0.--1. "PERSISTENCE,Persistence value to use for ITRSMP instructions." "0,1,2,3" line.long 0x14 "RGX_CR_USC_ITRSMP_PRIORITY_1,USC ITRSMP priority information" hexmask.long 0x14 0.--31. 1. "Reserved_2,Reserved_2" repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) rgroup.long ($2+0x4600)++0x3 line.long 0x0 "RGX_CR_USC_PWR_INSTR_$1,Peformance counter associated with Power Monitoring" hexmask.long 0x0 0.--31. 1. "EXEC,Number of instructions executed (max 1 per clock)" repeat.end repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) rgroup.long ($2+0x4608)++0x3 line.long 0x0 "RGX_CR_USC_PWR_CMMN_STR_ACCESS_$1,Peformance counter associated with Power Monitoring" hexmask.long 0x0 0.--31. 1. "COUNT,Number of Common Store accesses (max of 4 per lock)" repeat.end repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) rgroup.long ($2+0x4610)++0x3 line.long 0x0 "RGX_CR_USC_PWR_CMMN_STR_$1,Peformance counter associated with Power Monitoring" hexmask.long 0x0 0.--31. 1. "WR_BANK_CLASH,Common Store: Number of write/write bank clashes" repeat.end repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) rgroup.long ($2+0x4618)++0x3 line.long 0x0 "RGX_CR_USC_PWR_UNI_STR_$1,Peformance counter associated with Power Monitoring" hexmask.long 0x0 0.--31. 1. "WR_BANK_CLASH,Unified Store: Number of write/write bank clashes" repeat.end repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) rgroup.long ($2+0x4620)++0x3 line.long 0x0 "RGX_CR_USC_PWR_NUM_FLOAT_$1,Peformance counter associated with Power Monitoring" hexmask.long 0x0 0.--31. 1. "OPS,Number of floating point ops; FAdd/Fmul=1 MAD=2; max 32x2=64 per clock" repeat.end repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) rgroup.long ($2+0x4628)++0x3 line.long 0x0 "RGX_CR_USC_PWR_NUM_INTEGER_$1,Peformance counter associated with Power Monitoring" hexmask.long 0x0 0.--31. 1. "OPS,Number of integer ops; Add/Mul=1 MAD=2 max 16*2=32 per clock" repeat.end repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) rgroup.long ($2+0x4630)++0x3 line.long 0x0 "RGX_CR_USC_PWR_NUM_COALU_$1,Peformance counter associated with Power Monitoring" hexmask.long 0x0 0.--31. 1. "OPS,Number of COALU ops; max of 16 per clock" repeat.end repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) rgroup.long ($2+0x4638)++0x3 line.long 0x0 "RGX_CR_USC_PWR_NUM_$1,Peformance counter associated with Power Monitoring" hexmask.long 0x0 0.--31. 1. "PENALTY_CYCLES,Penalty cycles for read/read and write/write clashes. For each instruction this is max(a b c d)" repeat.end repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) rgroup.long ($2+0x4640)++0x3 line.long 0x0 "RGX_CR_USC_PWR_AV_NUM_INST_VALID_$1,Peformance counter associated with Power Monitoring" hexmask.long 0x0 0.--31. 1. "VERT,Average number of instances valid out of 16 for vertex tasks" repeat.end repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) rgroup.long ($2+0x4648)++0x3 line.long 0x0 "RGX_CR_USC_PWR_NUM_ON_EDGE_PIXL_$1,Peformance counter associated with Power Monitoring" hexmask.long 0x0 0.--31. 1. "WRITE,Number of on-edge pixel output register writes" repeat.end repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) rgroup.long ($2+0x4650)++0x3 line.long 0x0 "RGX_CR_USC_PWR_NUM_OFF_EDGE_PIXL_$1,Peformance counter associated with Power Monitoring" hexmask.long 0x0 0.--31. 1. "WRITE,Number of off-edge pixel output register writes" repeat.end repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) rgroup.long ($2+0x4658)++0x3 line.long 0x0 "RGX_CR_USC_PWR_NUM_F16_$1,Peformance counter associated with Power Monitoring" hexmask.long 0x0 0.--31. 1. "OPS,Number of F16 operations. Max of 16" repeat.end repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) rgroup.long ($2+0x4660)++0x3 line.long 0x0 "RGX_CR_USC_PWR_USCPD_INSTR_$1,Peformance counter associated with Power Monitoring" hexmask.long 0x0 0.--31. 1. "COUNT,Number of instructions executed by USCPD" repeat.end repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) rgroup.long ($2+0x4668)++0x3 line.long 0x0 "RGX_CR_USC_PWR_INT_REG_ACCESS_$1,Peformance counter associated with Power Monitoring" hexmask.long 0x0 0.--31. 1. "COUNT,Number of internal register accesses. Max 128 per clock = 8 registers * 16 instances" repeat.end repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) rgroup.long ($2+0x4670)++0x3 line.long 0x0 "RGX_CR_USC_PWR_US_STR_ACCESS_$1,Peformance counter associated with Power Monitoring" hexmask.long 0x0 0.--31. 1. "COUNT,Number of unified sotre US bank accesses. Max of 32 per clock = 8 banks * 4 pipes" repeat.end group.long 0x4678++0x7 line.long 0x0 "RGX_CR_USC_HQ_RESCH_0,Disable rescheduling of slots in USCPC HQ" hexmask.long 0x0 2.--31. 1. "Reserved_2,Reserved_2" newline bitfld.long 0x0 1. "DISABLE_FOR_BE,Disable rescheduling for BE instr in USCPC" "0,1" newline bitfld.long 0x0 0. "DISABLE,Disable rescheduling in USCPC" "0,1" line.long 0x4 "RGX_CR_USC_HQ_RESCH_1,Disable rescheduling of slots in USCPC HQ" hexmask.long 0x4 0.--31. 1. "Reserved_2,Reserved_2" repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) rgroup.long ($2+0x5000)++0x3 line.long 0x0 "RGX_CR_USC_UVS0_CHECKSUM_$1,RGX_CR_USC_UVS0_CHECKSUM_0" hexmask.long 0x0 0.--31. 1. "VALUE,Checksum of USC to UVS writes from USC0" repeat.end repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) rgroup.long ($2+0x5008)++0x3 line.long 0x0 "RGX_CR_USC_UVS1_CHECKSUM_$1,RGX_CR_USC_UVS1_CHECKSUM_0" hexmask.long 0x0 0.--31. 1. "VALUE,Checksum of USC to UVS writes from USC1" repeat.end repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) rgroup.long ($2+0x5010)++0x3 line.long 0x0 "RGX_CR_USC_UVS2_CHECKSUM_$1,RGX_CR_USC_UVS2_CHECKSUM_0" hexmask.long 0x0 0.--31. 1. "VALUE,Checksum of USC to UVS writes from USC2" repeat.end repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) rgroup.long ($2+0x5018)++0x3 line.long 0x0 "RGX_CR_USC_UVS3_CHECKSUM_$1,RGX_CR_USC_UVS3_CHECKSUM_0" hexmask.long 0x0 0.--31. 1. "VALUE,Checksum of USC to UVS writes from USC3" repeat.end repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) rgroup.long ($2+0x5020)++0x3 line.long 0x0 "RGX_CR_PPP_SIGNATURE_$1,RGX_CR_PPP_SIGNATURE_0" hexmask.long 0x0 0.--31. 1. "VALUE,Signature of PPP to Clipper Interface" repeat.end repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) rgroup.long ($2+0x5028)++0x3 line.long 0x0 "RGX_CR_TE_SIGNATURE_$1,RGX_CR_TE_SIGNATURE_0" hexmask.long 0x0 0.--31. 1. "VALUE,Signature of TE control stream writes" repeat.end repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) rgroup.long ($2+0x5030)++0x3 line.long 0x0 "RGX_CR_VCE_CHECKSUM_$1,RGX_CR_VCE_CHECKSUM_0" hexmask.long 0x0 0.--31. 1. "VALUE,Checksum of VCE memory writes" repeat.end repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) rgroup.long ($2+0x5038)++0x3 line.long 0x0 "RGX_CR_ISP_PDS_CHECKSUM_$1,RGX_CR_ISP_PDS_CHECKSUM_0" hexmask.long 0x0 0.--31. 1. "VALUE,Checksum of ISP PDS Span Output" repeat.end repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) rgroup.long ($2+0x5040)++0x3 line.long 0x0 "RGX_CR_ISP_TPF_CHECKSUM_$1,RGX_CR_ISP_TPF_CHECKSUM_0" hexmask.long 0x0 0.--31. 1. "VALUE,Checksum of ISP TPF Object Output" repeat.end repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) rgroup.long ($2+0x5048)++0x3 line.long 0x0 "RGX_CR_TFPU_PLANE0_CHECKSUM_$1,RGX_CR_TFPU_PLANE0_CHECKSUM_0" hexmask.long 0x0 0.--31. 1. "VALUE,Checksum of TFPU Plane0 Output" repeat.end repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) rgroup.long ($2+0x5050)++0x3 line.long 0x0 "RGX_CR_TFPU_PLANE1_CHECKSUM_$1,RGX_CR_TFPU_PLANE1_CHECKSUM_0" hexmask.long 0x0 0.--31. 1. "VALUE,Checksum of TFPU Plane1 Output" repeat.end repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) rgroup.long ($2+0x5058)++0x3 line.long 0x0 "RGX_CR_PBE_CHECKSUM_$1,RGX_CR_PBE_CHECKSUM_0" hexmask.long 0x0 0.--31. 1. "VALUE,Checksum of PBE memory writes" repeat.end repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) rgroup.long ($2+0x5060)++0x3 line.long 0x0 "RGX_CR_PDS_DOUTM_STM_SIGNATURE_$1,RGX_CR_PDS_DOUTM_STM_SIGNATURE_0" hexmask.long 0x0 0.--31. 1. "VALUE,Signature of PDS DOUTM Stream Out MCU writes" repeat.end repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) rgroup.long ($2+0x5068)++0x3 line.long 0x0 "RGX_CR_IFPU_ISP_CHECKSUM_$1,RGX_CR_IFPU_ISP_CHECKSUM_0" hexmask.long 0x0 0.--31. 1. "VALUE,Checksum of IFPU Output" repeat.end repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) rgroup.long ($2+0x5070)++0x3 line.long 0x0 "RGX_CR_MCU_L0_TA_CHECKSUM_$1,RGX_CR_MCU_L0_TA_CHECKSUM_0" hexmask.long 0x0 0.--31. 1. "VALUE,Checksum of the PDS->USC from MCU for TA data" repeat.end repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) rgroup.long ($2+0x5078)++0x3 line.long 0x0 "RGX_CR_MCU_L0_3D_CHECKSUM_$1,RGX_CR_MCU_L0_3D_CHECKSUM_0" hexmask.long 0x0 0.--31. 1. "VALUE,Checksum of the PDS->USC from MCU for 3D data" repeat.end repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) rgroup.long ($2+0x5080)++0x3 line.long 0x0 "RGX_CR_MCU_L0_WRAP_TA_CHECKSUM_$1,RGX_CR_MCU_L0_WRAP_TA_CHECKSUM_0" hexmask.long 0x0 0.--31. 1. "VALUE,Checksum of the PDS->USC from MCU for TA data" repeat.end repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) rgroup.long ($2+0x5088)++0x3 line.long 0x0 "RGX_CR_MCU_L0_WRAP_3D_CHECKSUM_$1,RGX_CR_MCU_L0_WRAP_3D_CHECKSUM_0" hexmask.long 0x0 0.--31. 1. "VALUE,Checksum of the PDS->USC from MCU for 3D data" repeat.end repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) rgroup.long ($2+0x5100)++0x3 line.long 0x0 "RGX_CR_USC_UVS4_CHECKSUM_$1,RGX_CR_USC_UVS4_CHECKSUM_0" hexmask.long 0x0 0.--31. 1. "VALUE,Checksum of USC to UVS writes from USC4" repeat.end repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) rgroup.long ($2+0x5108)++0x3 line.long 0x0 "RGX_CR_USC_UVS5_CHECKSUM_$1,RGX_CR_USC_UVS5_CHECKSUM_0" hexmask.long 0x0 0.--31. 1. "VALUE,Checksum of USC to UVS writes from USC5" repeat.end repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) rgroup.long ($2+0x5148)++0x3 line.long 0x0 "RGX_CR_TDM_PDS_CHECKSUM_$1,RGX_CR_TDM_PDS_CHECKSUM_0" hexmask.long 0x0 0.--31. 1. "VALUE,Checksum of all TDM to PDS tile emits." repeat.end repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) rgroup.long ($2+0x5160)++0x3 line.long 0x0 "RGX_CR_PBE_CHECKSUM_NO_ADDR_$1,RGX_CR_PBE_CHECKSUM_NO_ADDR_0" hexmask.long 0x0 0.--31. 1. "VALUE,No address checksum of PBE memory writes" repeat.end repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) rgroup.long ($2+0x5200)++0x3 line.long 0x0 "RGX_CR_PBE_CHECKSUM_TDM_$1,RGX_CR_PBE_CHECKSUM_TDM_0" hexmask.long 0x0 0.--31. 1. "VALUE,TDM checksum of PBE memory writes" repeat.end repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) rgroup.long ($2+0x5208)++0x3 line.long 0x0 "RGX_CR_PBE_CHECKSUM_TDM_NO_ADDR_$1,RGX_CR_PBE_CHECKSUM_TDM_NO_ADDR_0" hexmask.long 0x0 0.--31. 1. "VALUE,No address TDM checksum of PBE memory writes" repeat.end group.long 0x6000++0x7 line.long 0x0 "RGX_CR_PERF_COUNTER_0,RGX_CR_PERF_COUNTER_0" hexmask.long 0x0 1.--31. 1. "Reserved_1,Reserved_1" newline bitfld.long 0x0 0. "RESET,A write of 1 to this register resets the Cycle Counters and holds them in Reset. A write of 0 enables them for Counting" "0,1" line.long 0x4 "RGX_CR_PERF_COUNTER_1,RGX_CR_PERF_COUNTER_1" hexmask.long 0x4 0.--31. 1. "Reserved_1,Reserved_1" repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) rgroup.long ($2+0x6008)++0x3 line.long 0x0 "RGX_CR_PERF_TA_PHASE_$1,RGX_CR_PERF_TA_PHASE_0" hexmask.long 0x0 0.--31. 1. "COUNT,The number of TA phases completed" repeat.end repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) rgroup.long ($2+0x6010)++0x3 line.long 0x0 "RGX_CR_PERF_3D_PHASE_$1,RGX_CR_PERF_3D_PHASE_0" hexmask.long 0x0 0.--31. 1. "COUNT,The number of 3D phases completed" repeat.end repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) rgroup.long ($2+0x6018)++0x3 line.long 0x0 "RGX_CR_PERF_COMPUTE_PHASE_$1,RGX_CR_PERF_COMPUTE_PHASE_0" hexmask.long 0x0 0.--31. 1. "COUNT,The number of Compute phases completed" repeat.end repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) rgroup.long ($2+0x6020)++0x3 line.long 0x0 "RGX_CR_PERF_TA_CYCLE_$1,RGX_CR_PERF_TA_CYCLE_0" hexmask.long 0x0 0.--31. 1. "COUNT,The number of cycles spent in TA phases" repeat.end repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) rgroup.long ($2+0x6028)++0x3 line.long 0x0 "RGX_CR_PERF_3D_CYCLE_$1,RGX_CR_PERF_3D_CYCLE_0" hexmask.long 0x0 0.--31. 1. "COUNT,The number of cycles spent in 3D phases" repeat.end repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) rgroup.long ($2+0x6030)++0x3 line.long 0x0 "RGX_CR_PERF_COMPUTE_CYCLE_$1,RGX_CR_PERF_COMPUTE_CYCLE_0" hexmask.long 0x0 0.--31. 1. "COUNT,The number of cycles spent in Compute phases" repeat.end repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) rgroup.long ($2+0x6038)++0x3 line.long 0x0 "RGX_CR_PERF_TA_OR_3D_CYCLE_$1,RGX_CR_PERF_TA_OR_3D_CYCLE_0" hexmask.long 0x0 0.--31. 1. "COUNT,The number of cycles spent in TA phases or 3D phases" repeat.end repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) rgroup.long ($2+0x6040)++0x3 line.long 0x0 "RGX_CR_PERF_INITIAL_TA_CYCLE_$1,RGX_CR_PERF_INITIAL_TA_CYCLE_0" hexmask.long 0x0 0.--31. 1. "COUNT,The number of cycles spent in TA phases before the first 3D phase" repeat.end repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) rgroup.long ($2+0x6048)++0x3 line.long 0x0 "RGX_CR_PERF_FINAL_3D_CYCLE_$1,RGX_CR_PERF_FINAL_3D_CYCLE_0" hexmask.long 0x0 0.--31. 1. "COUNT,The number of cycles spent in the last 3D phase" repeat.end repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) rgroup.long ($2+0x6050)++0x3 line.long 0x0 "RGX_CR_PERF_BIF0_READ_$1,RGX_CR_PERF_BIF0_READ_0" hexmask.long 0x0 0.--31. 1. "COUNT,The number of BIF0-to-SLC reads" repeat.end repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) rgroup.long ($2+0x6058)++0x3 line.long 0x0 "RGX_CR_PERF_BIF0_WRITE_$1,RGX_CR_PERF_BIF0_WRITE_0" hexmask.long 0x0 0.--31. 1. "COUNT,The number of BIF0-to-SLC writes" repeat.end repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) rgroup.long ($2+0x6060)++0x3 line.long 0x0 "RGX_CR_PERF_BIF0_BYTE_WRITE_$1,RGX_CR_PERF_BIF0_BYTE_WRITE_0" hexmask.long 0x0 0.--31. 1. "COUNT,The number of BIF0-to-SLC bytes written" repeat.end repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) rgroup.long ($2+0x6068)++0x3 line.long 0x0 "RGX_CR_PERF_BIF0_READ_STALL_$1,RGX_CR_PERF_BIF0_READ_STALL_0" hexmask.long 0x0 0.--31. 1. "COUNT,The number of BIF0-to-SLC read stalls" repeat.end repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) rgroup.long ($2+0x6070)++0x3 line.long 0x0 "RGX_CR_PERF_BIF0_WRITE_STALL_$1,RGX_CR_PERF_BIF0_WRITE_STALL_0" hexmask.long 0x0 0.--31. 1. "COUNT,The number of BIF0-to-SLC write stalls" repeat.end repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) rgroup.long ($2+0x60A0)++0x3 line.long 0x0 "RGX_CR_PERF_SLC0_READ_$1,RGX_CR_PERF_SLC0_READ_0" hexmask.long 0x0 0.--31. 1. "COUNT,The number of SLC-to-MEM interface 0 reads" repeat.end repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) rgroup.long ($2+0x60A8)++0x3 line.long 0x0 "RGX_CR_PERF_SLC0_WRITE_$1,RGX_CR_PERF_SLC0_WRITE_0" hexmask.long 0x0 0.--31. 1. "COUNT,The number of SLC-to-MEM interface 0 writes" repeat.end repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) rgroup.long ($2+0x60B0)++0x3 line.long 0x0 "RGX_CR_PERF_SLC0_BYTE_WRITE_$1,RGX_CR_PERF_SLC0_BYTE_WRITE_0" hexmask.long 0x0 0.--31. 1. "COUNT,The number of SLC-to-MEM interface 0 bytes written" repeat.end repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) rgroup.long ($2+0x60B8)++0x3 line.long 0x0 "RGX_CR_PERF_SLC0_READ_STALL_$1,RGX_CR_PERF_SLC0_READ_STALL_0" hexmask.long 0x0 0.--31. 1. "COUNT,The number of SLC-to-MEM interface 0 command stalls" repeat.end repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) rgroup.long ($2+0x60C0)++0x3 line.long 0x0 "RGX_CR_PERF_SLC0_WRITE_STALL_$1,RGX_CR_PERF_SLC0_WRITE_STALL_0" hexmask.long 0x0 0.--31. 1. "COUNT,The number of SLC-to-MEM insterface 0 write channel stalls" repeat.end repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) rgroup.long ($2+0x60C8)++0x3 line.long 0x0 "RGX_CR_PERF_SLC1_READ_$1,RGX_CR_PERF_SLC1_READ_0" hexmask.long 0x0 0.--31. 1. "COUNT,The number of SLC-to-MEM interface 1 reads" repeat.end repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) rgroup.long ($2+0x60D0)++0x3 line.long 0x0 "RGX_CR_PERF_SLC1_WRITE_$1,RGX_CR_PERF_SLC1_WRITE_0" hexmask.long 0x0 0.--31. 1. "COUNT,The number of SLC-to-MEM interface 1 writes" repeat.end repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) rgroup.long ($2+0x60D8)++0x3 line.long 0x0 "RGX_CR_PERF_SLC1_BYTE_WRITE_$1,RGX_CR_PERF_SLC1_BYTE_WRITE_0" hexmask.long 0x0 0.--31. 1. "COUNT,The number of SLC-to-MEM interface 1 bytes written" repeat.end repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) rgroup.long ($2+0x60E0)++0x3 line.long 0x0 "RGX_CR_PERF_SLC1_READ_STALL_$1,RGX_CR_PERF_SLC1_READ_STALL_0" hexmask.long 0x0 0.--31. 1. "COUNT,The number of SLC-to-MEM interface 1 command stalls" repeat.end repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) rgroup.long ($2+0x60E8)++0x3 line.long 0x0 "RGX_CR_PERF_SLC1_WRITE_STALL_$1,RGX_CR_PERF_SLC1_WRITE_STALL_0" hexmask.long 0x0 0.--31. 1. "COUNT,The number of SLC-to-MEM interface 1 write channel stalls" repeat.end repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) rgroup.long ($2+0x60F0)++0x3 line.long 0x0 "RGX_CR_PERF_SLC_BURST_SIZE0_IN_$1,RGX_CR_PERF_SLC_BURST_SIZE0_IN_0" hexmask.long 0x0 0.--31. 1. "VALUE,The number of burstlength 0 accesses into the Burst Combiner" repeat.end repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) rgroup.long ($2+0x60F8)++0x3 line.long 0x0 "RGX_CR_PERF_SLC_BURST_SIZE1_IN_$1,RGX_CR_PERF_SLC_BURST_SIZE1_IN_0" hexmask.long 0x0 0.--31. 1. "VALUE,The number of burstlength 1 accesses into the Burst Combiner" repeat.end repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) rgroup.long ($2+0x6100)++0x3 line.long 0x0 "RGX_CR_PERF_SLC_BURST_SIZE0_OUT_$1,RGX_CR_PERF_SLC_BURST_SIZE0_OUT_0" hexmask.long 0x0 0.--31. 1. "VALUE,The number of burstlength 0 accesses out of the Burst Combiner" repeat.end repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) rgroup.long ($2+0x6108)++0x3 line.long 0x0 "RGX_CR_PERF_SLC_BURST_SIZE1_OUT_$1,RGX_CR_PERF_SLC_BURST_SIZE1_OUT_0" hexmask.long 0x0 0.--31. 1. "VALUE,The number of burstlength 1 accesses out of the Burst Combiner" repeat.end repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) rgroup.long ($2+0x6110)++0x3 line.long 0x0 "RGX_CR_PERF_SLC_BURST_SIZE2_OUT_$1,RGX_CR_PERF_SLC_BURST_SIZE2_OUT_0" hexmask.long 0x0 0.--31. 1. "VALUE,The number of burstlength 2 accesses out of the Burst Combiner" repeat.end repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) rgroup.long ($2+0x6118)++0x3 line.long 0x0 "RGX_CR_PERF_SLC0_READ_ID_STALL_$1,RGX_CR_PERF_SLC0_READ_ID_STALL_0" hexmask.long 0x0 0.--31. 1. "COUNT,The number of cycles the SLC spends stalled because all Read IDs on memory interface 0 are currently in use" repeat.end repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) rgroup.long ($2+0x6120)++0x3 line.long 0x0 "RGX_CR_PERF_SLC0_WRITE_ID_STALL_$1,RGX_CR_PERF_SLC0_WRITE_ID_STALL_0" hexmask.long 0x0 0.--31. 1. "COUNT,The number of cycles the SLC spends stalled because all Write IDs on memory interface 0 are currently in use" repeat.end repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) rgroup.long ($2+0x6128)++0x3 line.long 0x0 "RGX_CR_PERF_SLC1_READ_ID_STALL_$1,RGX_CR_PERF_SLC1_READ_ID_STALL_0" hexmask.long 0x0 0.--31. 1. "COUNT,The number of cycles the SLC spends stalled because all Read IDs on memory interface 1 are currently in use" repeat.end repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) rgroup.long ($2+0x6130)++0x3 line.long 0x0 "RGX_CR_PERF_SLC1_WRITE_ID_STALL_$1,RGX_CR_PERF_SLC1_WRITE_ID_STALL_0" hexmask.long 0x0 0.--31. 1. "COUNT,The number of cycles the SLC spends stalled because all Write IDs on memory interface 1 are currently in use" repeat.end repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) rgroup.long ($2+0x6138)++0x3 line.long 0x0 "RGX_CR_PERF_SLC_BURST_SIZE3_OUT_$1,RGX_CR_PERF_SLC_BURST_SIZE3_OUT_0" hexmask.long 0x0 0.--31. 1. "VALUE,The number of burstlength 3 accesses out of the Burst Combiner" repeat.end repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) rgroup.long ($2+0x6140)++0x3 line.long 0x0 "RGX_CR_PERF_SLC2_READ_$1,RGX_CR_PERF_SLC2_READ_0" hexmask.long 0x0 0.--31. 1. "COUNT,The number of SLC-to-MEM interface 2 reads" repeat.end repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) rgroup.long ($2+0x6148)++0x3 line.long 0x0 "RGX_CR_PERF_SLC2_WRITE_$1,RGX_CR_PERF_SLC2_WRITE_0" hexmask.long 0x0 0.--31. 1. "COUNT,The number of SLC-to-MEM interface 2 writes" repeat.end repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) rgroup.long ($2+0x6150)++0x3 line.long 0x0 "RGX_CR_PERF_SLC2_BYTE_WRITE_$1,RGX_CR_PERF_SLC2_BYTE_WRITE_0" hexmask.long 0x0 0.--31. 1. "COUNT,The number of SLC-to-MEM interface 2 bytes written" repeat.end repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) rgroup.long ($2+0x6158)++0x3 line.long 0x0 "RGX_CR_PERF_SLC2_READ_STALL_$1,RGX_CR_PERF_SLC2_READ_STALL_0" hexmask.long 0x0 0.--31. 1. "COUNT,The number of SLC-to-MEM interface 2 command stalls" repeat.end repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) rgroup.long ($2+0x6160)++0x3 line.long 0x0 "RGX_CR_PERF_SLC2_WRITE_STALL_$1,RGX_CR_PERF_SLC2_WRITE_STALL_0" hexmask.long 0x0 0.--31. 1. "COUNT,The number of SLC-to-MEM interface 2 write channel stalls" repeat.end repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) rgroup.long ($2+0x6168)++0x3 line.long 0x0 "RGX_CR_PERF_SLC3_READ_$1,RGX_CR_PERF_SLC3_READ_0" hexmask.long 0x0 0.--31. 1. "COUNT,The number of SLC-to-MEM interface 3 reads" repeat.end repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) rgroup.long ($2+0x6170)++0x3 line.long 0x0 "RGX_CR_PERF_SLC3_WRITE_$1,RGX_CR_PERF_SLC3_WRITE_0" hexmask.long 0x0 0.--31. 1. "COUNT,The number of SLC-to-MEM interface 3 writes" repeat.end repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) rgroup.long ($2+0x6178)++0x3 line.long 0x0 "RGX_CR_PERF_SLC3_BYTE_WRITE_$1,RGX_CR_PERF_SLC3_BYTE_WRITE_0" hexmask.long 0x0 0.--31. 1. "COUNT,The number of SLC-to-MEM interface 3 bytes written" repeat.end repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) rgroup.long ($2+0x6180)++0x3 line.long 0x0 "RGX_CR_PERF_SLC3_READ_STALL_$1,RGX_CR_PERF_SLC3_READ_STALL_0" hexmask.long 0x0 0.--31. 1. "COUNT,The number of SLC-to-MEM interface 3 command stalls" repeat.end repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) rgroup.long ($2+0x6188)++0x3 line.long 0x0 "RGX_CR_PERF_SLC3_WRITE_STALL_$1,RGX_CR_PERF_SLC3_WRITE_STALL_0" hexmask.long 0x0 0.--31. 1. "COUNT,The number of SLC-to-MEM interface 3 write channel stalls" repeat.end repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) rgroup.long ($2+0x6190)++0x3 line.long 0x0 "RGX_CR_PERF_SLC_BURST_SIZE2_IN_$1,RGX_CR_PERF_SLC_BURST_SIZE2_IN_0" hexmask.long 0x0 0.--31. 1. "VALUE,The number of burstlength 2 accesses into the Burst Combiner" repeat.end repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) rgroup.long ($2+0x6198)++0x3 line.long 0x0 "RGX_CR_PERF_SLC_BURST_SIZE3_IN_$1,RGX_CR_PERF_SLC_BURST_SIZE3_IN_0" hexmask.long 0x0 0.--31. 1. "VALUE,The number of burstlength 3 accesses into the Burst Combiner" repeat.end repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) rgroup.long ($2+0x6220)++0x3 line.long 0x0 "RGX_CR_PERF_3D_SPINUP_$1,RGX_CR_PERF_3D_SPINUP_0" hexmask.long 0x0 0.--31. 1. "CYCLES,The number of cycles it takes the 3D pipeline to spin-up" repeat.end group.long 0x6300++0x7 line.long 0x0 "RGX_CR_POWER_ESTIMATE_REQ_RST_0,Power estimate Request/Reset - The generation of the power estimate will be initiated upon a write to the power managment register. This will be driven down to the relevant blocks to reset the counters and also to start.." hexmask.long 0x0 1.--31. 1. "Reserved_1,Reserved_1" newline bitfld.long 0x0 0. "VALUE,VALUE" "0,1" line.long 0x4 "RGX_CR_POWER_ESTIMATE_REQ_RST_1,Power estimate Request/Reset - The generation of the power estimate will be initiated upon a write to the power managment register. This will be driven down to the relevant blocks to reset the counters and also to start.." hexmask.long 0x4 0.--31. 1. "Reserved_1,Reserved_1" repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) group.long ($2+0x6310)++0x3 line.long 0x0 "RGX_CR_POWER_ESTIMATE_SAMPLE_COUNT_$1,Power Estimate Sample Count - This defines the number of cycles over which power monitoring will occur. When the POWER_ESTIMIATE_REQ_RST is written to POWER_ESTIMATE_SAMPLE_COUNT will begin to count down from its.." hexmask.long 0x0 0.--31. 1. "VALUE,VALUE" repeat.end rgroup.long 0x6318++0x7 line.long 0x0 "RGX_CR_POWER_ESTIMATE_READY_0,Power estimate Ready - A system event (portmap signal and maskable interrupt) is output when the power estimate has been completed and the power monitor register is updated. Logic or firmware or both will manage the SOC.." hexmask.long.word 0x0 17.--31. 1. "Reserved_17,Reserved_17" newline bitfld.long 0x0 16. "FB_CDC,FB_CDC" "0,1" newline bitfld.long 0x0 15. "Reserved_15,Reserved_15" "0,1" newline bitfld.long 0x0 14. "SLC,SLC" "0,1" newline bitfld.long 0x0 13. "TILING,TILING" "0,1" newline bitfld.long 0x0 12. "JONES,JONES" "0,1" newline bitfld.long 0x0 10.--11. "Reserved_10,Reserved_10" "0,1,2,3" newline bitfld.long 0x0 9. "TA,TA" "0,1" newline bitfld.long 0x0 8. "RASTERISATION,RASTERISATION" "0,1" newline bitfld.long 0x0 7. "HUB,HUB" "0,1" newline bitfld.long 0x0 6. "BIFPMCACHE,BIFPMCACHE" "0,1" newline bitfld.long 0x0 5. "Reserved_5,Reserved_5" "0,1" newline bitfld.long 0x0 4. "TPU_MCU,TPU_MCU" "0,1" newline bitfld.long 0x0 1.--3. "Reserved_1,Reserved_1" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 0. "USC,USC" "0,1" line.long 0x4 "RGX_CR_POWER_ESTIMATE_READY_1,Power estimate Ready - A system event (portmap signal and maskable interrupt) is output when the power estimate has been completed and the power monitor register is updated. Logic or firmware or both will manage the SOC.." hexmask.long 0x4 0.--31. 1. "Reserved_17,Reserved_17" repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) group.long ($2+0x6320)++0x3 line.long 0x0 "RGX_CR_POWER_ESTIMATE_GAIN_COEFF_$1,Final Gain coefficient to apply to summation of all power monitoring quotients" hexmask.long 0x0 0.--31. 1. "VALUE,VALUE" repeat.end repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) group.long ($2+0x6328)++0x3 line.long 0x0 "RGX_CR_POWER_ESTIMATE_RESULT_$1,Power Estimate Result. This represents the estimation of the total system power usage." hexmask.long 0x0 0.--31. 1. "VALUE,VALUE" repeat.end group.long 0x6330++0x7 line.long 0x0 "RGX_CR_PERF_COUNT_MODE_ONLY_0,This register bit set means we need to do only perf-counter gathering and nothing to do with pwr-perf related counting" hexmask.long 0x0 1.--31. 1. "Reserved_1,Reserved_1" newline bitfld.long 0x0 0. "VALUE,VALUE" "0,1" line.long 0x4 "RGX_CR_PERF_COUNT_MODE_ONLY_1,This register bit set means we need to do only perf-counter gathering and nothing to do with pwr-perf related counting" hexmask.long 0x4 0.--31. 1. "Reserved_1,Reserved_1" rgroup.long 0x6500++0x2F line.long 0x0 "RGX_CR_AVG_NON_CRITICAL_MEM0_LATENCY_0,RGX_CR_AVG_NON_CRITICAL_MEM0_LATENCY_0" hexmask.long.tbyte 0x0 12.--31. 1. "Reserved_12,Reserved_12" newline hexmask.long.word 0x0 0.--11. 1. "COUNT,The average number of read latency cycles incur at external memory for non critical tag" line.long 0x4 "RGX_CR_AVG_NON_CRITICAL_MEM0_LATENCY_1,RGX_CR_AVG_NON_CRITICAL_MEM0_LATENCY_1" hexmask.long 0x4 0.--31. 1. "Reserved_12,Reserved_12" line.long 0x8 "RGX_CR_MIN_NON_CRITICAL_MEM0_LATENCY_0,RGX_CR_MIN_NON_CRITICAL_MEM0_LATENCY_0" hexmask.long.tbyte 0x8 12.--31. 1. "Reserved_12,Reserved_12" newline hexmask.long.word 0x8 0.--11. 1. "COUNT,The min number of read latency cycles incur at external memory for non critical tag" line.long 0xC "RGX_CR_MIN_NON_CRITICAL_MEM0_LATENCY_1,RGX_CR_MIN_NON_CRITICAL_MEM0_LATENCY_1" hexmask.long 0xC 0.--31. 1. "Reserved_12,Reserved_12" line.long 0x10 "RGX_CR_MAX_NON_CRITICAL_MEM0_LATENCY_0,RGX_CR_MAX_NON_CRITICAL_MEM0_LATENCY_0" hexmask.long.tbyte 0x10 12.--31. 1. "Reserved_12,Reserved_12" newline hexmask.long.word 0x10 0.--11. 1. "COUNT,The max number of read latency cycles incur at external memory for non critical tag" line.long 0x14 "RGX_CR_MAX_NON_CRITICAL_MEM0_LATENCY_1,RGX_CR_MAX_NON_CRITICAL_MEM0_LATENCY_1" hexmask.long 0x14 0.--31. 1. "Reserved_12,Reserved_12" line.long 0x18 "RGX_CR_AVG_CRITICAL_MEM0_LATENCY_0,RGX_CR_AVG_CRITICAL_MEM0_LATENCY_0" hexmask.long.tbyte 0x18 12.--31. 1. "Reserved_12,Reserved_12" newline hexmask.long.word 0x18 0.--11. 1. "COUNT,The average number of read latency cycles incur at external memory for critical tag" line.long 0x1C "RGX_CR_AVG_CRITICAL_MEM0_LATENCY_1,RGX_CR_AVG_CRITICAL_MEM0_LATENCY_1" hexmask.long 0x1C 0.--31. 1. "Reserved_12,Reserved_12" line.long 0x20 "RGX_CR_MIN_CRITICAL_MEM0_LATENCY_0,RGX_CR_MIN_CRITICAL_MEM0_LATENCY_0" hexmask.long.tbyte 0x20 12.--31. 1. "Reserved_12,Reserved_12" newline hexmask.long.word 0x20 0.--11. 1. "COUNT,The min number of read latency cycles incur at external memory for critical tag" line.long 0x24 "RGX_CR_MIN_CRITICAL_MEM0_LATENCY_1,RGX_CR_MIN_CRITICAL_MEM0_LATENCY_1" hexmask.long 0x24 0.--31. 1. "Reserved_12,Reserved_12" line.long 0x28 "RGX_CR_MAX_CRITICAL_MEM0_LATENCY_0,RGX_CR_MAX_CRITICAL_MEM0_LATENCY_0" hexmask.long.tbyte 0x28 12.--31. 1. "Reserved_12,Reserved_12" newline hexmask.long.word 0x28 0.--11. 1. "COUNT,The max number of read latency cycles incur at external memory for critical tag" line.long 0x2C "RGX_CR_MAX_CRITICAL_MEM0_LATENCY_1,RGX_CR_MAX_CRITICAL_MEM0_LATENCY_1" hexmask.long 0x2C 0.--31. 1. "Reserved_12,Reserved_12" group.long 0x6530++0x7 line.long 0x0 "RGX_CR_USER_DEFINED_MEM0_MH_TAG_0,Writing '1' followed by mh_tag value at the lsb end of this register starts the user defined mh_tag value for latency calculation. Default value is zero where this feature is turned off. Bit [6] - Enable bit to turn on.." hexmask.long 0x0 7.--31. 1. "Reserved_7,Reserved_7" newline hexmask.long.byte 0x0 0.--6. 1. "VALUE,VALUE" line.long 0x4 "RGX_CR_USER_DEFINED_MEM0_MH_TAG_1,Writing '1' followed by mh_tag value at the lsb end of this register starts the user defined mh_tag value for latency calculation. Default value is zero where this feature is turned off. Bit [6] - Enable bit to turn on.." hexmask.long 0x4 0.--31. 1. "Reserved_7,Reserved_7" rgroup.long 0x6538++0x57 line.long 0x0 "RGX_CR_AVG_USER_MH_TAG_MEM0_LATENCY_0,RGX_CR_AVG_USER_MH_TAG_MEM0_LATENCY_0" hexmask.long.tbyte 0x0 12.--31. 1. "Reserved_12,Reserved_12" newline hexmask.long.word 0x0 0.--11. 1. "COUNT,The average number of read latency cycles incur at external memory for user_defined tag" line.long 0x4 "RGX_CR_AVG_USER_MH_TAG_MEM0_LATENCY_1,RGX_CR_AVG_USER_MH_TAG_MEM0_LATENCY_1" hexmask.long 0x4 0.--31. 1. "Reserved_12,Reserved_12" line.long 0x8 "RGX_CR_MIN_USER_MH_TAG_MEM0_LATENCY_0,RGX_CR_MIN_USER_MH_TAG_MEM0_LATENCY_0" hexmask.long.tbyte 0x8 12.--31. 1. "Reserved_12,Reserved_12" newline hexmask.long.word 0x8 0.--11. 1. "COUNT,The min number of read latency cycles incur at external memory for user defined tag" line.long 0xC "RGX_CR_MIN_USER_MH_TAG_MEM0_LATENCY_1,RGX_CR_MIN_USER_MH_TAG_MEM0_LATENCY_1" hexmask.long 0xC 0.--31. 1. "Reserved_12,Reserved_12" line.long 0x10 "RGX_CR_MAX_USER_MH_TAG_MEM0_LATENCY_0,RGX_CR_MAX_USER_MH_TAG_MEM0_LATENCY_0" hexmask.long.tbyte 0x10 12.--31. 1. "Reserved_12,Reserved_12" newline hexmask.long.word 0x10 0.--11. 1. "COUNT,The max number of read latency cycles incur at external memory for user defined tag" line.long 0x14 "RGX_CR_MAX_USER_MH_TAG_MEM0_LATENCY_1,RGX_CR_MAX_USER_MH_TAG_MEM0_LATENCY_1" hexmask.long 0x14 0.--31. 1. "Reserved_12,Reserved_12" line.long 0x18 "RGX_CR_MIN_NON_CRITICAL_MEM0_LATENCY_MH_TAG_0,RGX_CR_MIN_NON_CRITICAL_MEM0_LATENCY_MH_TAG_0" hexmask.long 0x18 6.--31. 1. "Reserved_6,Reserved_6" newline hexmask.long.byte 0x18 0.--5. 1. "VALUE,The mh_tag value of min read latency cycles for non critical tag" line.long 0x1C "RGX_CR_MIN_NON_CRITICAL_MEM0_LATENCY_MH_TAG_1,RGX_CR_MIN_NON_CRITICAL_MEM0_LATENCY_MH_TAG_1" hexmask.long 0x1C 0.--31. 1. "Reserved_6,Reserved_6" line.long 0x20 "RGX_CR_MAX_NON_CRITICAL_MEM0_LATENCY_MH_TAG_0,RGX_CR_MAX_NON_CRITICAL_MEM0_LATENCY_MH_TAG_0" hexmask.long 0x20 6.--31. 1. "Reserved_6,Reserved_6" newline hexmask.long.byte 0x20 0.--5. 1. "VALUE,The mh_tag value of max read latency cycles for non critical tag" line.long 0x24 "RGX_CR_MAX_NON_CRITICAL_MEM0_LATENCY_MH_TAG_1,RGX_CR_MAX_NON_CRITICAL_MEM0_LATENCY_MH_TAG_1" hexmask.long 0x24 0.--31. 1. "Reserved_6,Reserved_6" line.long 0x28 "RGX_CR_AVG_NON_CRITICAL_MEM1_LATENCY_0,RGX_CR_AVG_NON_CRITICAL_MEM1_LATENCY_0" hexmask.long.tbyte 0x28 12.--31. 1. "Reserved_12,Reserved_12" newline hexmask.long.word 0x28 0.--11. 1. "COUNT,The average number of read latency cycles incur at external memory for non critical tag" line.long 0x2C "RGX_CR_AVG_NON_CRITICAL_MEM1_LATENCY_1,RGX_CR_AVG_NON_CRITICAL_MEM1_LATENCY_1" hexmask.long 0x2C 0.--31. 1. "Reserved_12,Reserved_12" line.long 0x30 "RGX_CR_MIN_NON_CRITICAL_MEM1_LATENCY_0,RGX_CR_MIN_NON_CRITICAL_MEM1_LATENCY_0" hexmask.long.tbyte 0x30 12.--31. 1. "Reserved_12,Reserved_12" newline hexmask.long.word 0x30 0.--11. 1. "COUNT,The min number of read latency cycles incur at external memory for non critical tag" line.long 0x34 "RGX_CR_MIN_NON_CRITICAL_MEM1_LATENCY_1,RGX_CR_MIN_NON_CRITICAL_MEM1_LATENCY_1" hexmask.long 0x34 0.--31. 1. "Reserved_12,Reserved_12" line.long 0x38 "RGX_CR_MAX_NON_CRITICAL_MEM1_LATENCY_0,RGX_CR_MAX_NON_CRITICAL_MEM1_LATENCY_0" hexmask.long.tbyte 0x38 12.--31. 1. "Reserved_12,Reserved_12" newline hexmask.long.word 0x38 0.--11. 1. "COUNT,The max number of read latency cycles incur at external memory for non critical tag" line.long 0x3C "RGX_CR_MAX_NON_CRITICAL_MEM1_LATENCY_1,RGX_CR_MAX_NON_CRITICAL_MEM1_LATENCY_1" hexmask.long 0x3C 0.--31. 1. "Reserved_12,Reserved_12" line.long 0x40 "RGX_CR_AVG_CRITICAL_MEM1_LATENCY_0,RGX_CR_AVG_CRITICAL_MEM1_LATENCY_0" hexmask.long.tbyte 0x40 12.--31. 1. "Reserved_12,Reserved_12" newline hexmask.long.word 0x40 0.--11. 1. "COUNT,The average number of read latency cycles incur at external memory for critical tag" line.long 0x44 "RGX_CR_AVG_CRITICAL_MEM1_LATENCY_1,RGX_CR_AVG_CRITICAL_MEM1_LATENCY_1" hexmask.long 0x44 0.--31. 1. "Reserved_12,Reserved_12" line.long 0x48 "RGX_CR_MIN_CRITICAL_MEM1_LATENCY_0,RGX_CR_MIN_CRITICAL_MEM1_LATENCY_0" hexmask.long.tbyte 0x48 12.--31. 1. "Reserved_12,Reserved_12" newline hexmask.long.word 0x48 0.--11. 1. "COUNT,The min number of read latency cycles incur at external memory for critical tag" line.long 0x4C "RGX_CR_MIN_CRITICAL_MEM1_LATENCY_1,RGX_CR_MIN_CRITICAL_MEM1_LATENCY_1" hexmask.long 0x4C 0.--31. 1. "Reserved_12,Reserved_12" line.long 0x50 "RGX_CR_MAX_CRITICAL_MEM1_LATENCY_0,RGX_CR_MAX_CRITICAL_MEM1_LATENCY_0" hexmask.long.tbyte 0x50 12.--31. 1. "Reserved_12,Reserved_12" newline hexmask.long.word 0x50 0.--11. 1. "COUNT,The max number of read latency cycles incur at external memory for critical tag" line.long 0x54 "RGX_CR_MAX_CRITICAL_MEM1_LATENCY_1,RGX_CR_MAX_CRITICAL_MEM1_LATENCY_1" hexmask.long 0x54 0.--31. 1. "Reserved_12,Reserved_12" group.long 0x6590++0x7 line.long 0x0 "RGX_CR_USER_DEFINED_MEM1_MH_TAG_0,Writing '1' followed by mh_tag value at the lsb end of this register starts the user defined mh_tag value for latency calculation. Default value is zero where this feature is turned off. Bit [6] - Enable bit to turn on.." hexmask.long 0x0 7.--31. 1. "Reserved_7,Reserved_7" newline hexmask.long.byte 0x0 0.--6. 1. "VALUE,VALUE" line.long 0x4 "RGX_CR_USER_DEFINED_MEM1_MH_TAG_1,Writing '1' followed by mh_tag value at the lsb end of this register starts the user defined mh_tag value for latency calculation. Default value is zero where this feature is turned off. Bit [6] - Enable bit to turn on.." hexmask.long 0x4 0.--31. 1. "Reserved_7,Reserved_7" rgroup.long 0x6598++0x27 line.long 0x0 "RGX_CR_AVG_USER_MH_TAG_MEM1_LATENCY_0,RGX_CR_AVG_USER_MH_TAG_MEM1_LATENCY_0" hexmask.long.tbyte 0x0 12.--31. 1. "Reserved_12,Reserved_12" newline hexmask.long.word 0x0 0.--11. 1. "COUNT,The average number of read latency cycles incur at external memory for user_defined tag" line.long 0x4 "RGX_CR_AVG_USER_MH_TAG_MEM1_LATENCY_1,RGX_CR_AVG_USER_MH_TAG_MEM1_LATENCY_1" hexmask.long 0x4 0.--31. 1. "Reserved_12,Reserved_12" line.long 0x8 "RGX_CR_MIN_USER_MH_TAG_MEM1_LATENCY_0,RGX_CR_MIN_USER_MH_TAG_MEM1_LATENCY_0" hexmask.long.tbyte 0x8 12.--31. 1. "Reserved_12,Reserved_12" newline hexmask.long.word 0x8 0.--11. 1. "COUNT,The min number of read latency cycles incur at external memory for user defined tag" line.long 0xC "RGX_CR_MIN_USER_MH_TAG_MEM1_LATENCY_1,RGX_CR_MIN_USER_MH_TAG_MEM1_LATENCY_1" hexmask.long 0xC 0.--31. 1. "Reserved_12,Reserved_12" line.long 0x10 "RGX_CR_MAX_USER_MH_TAG_MEM1_LATENCY_0,RGX_CR_MAX_USER_MH_TAG_MEM1_LATENCY_0" hexmask.long.tbyte 0x10 12.--31. 1. "Reserved_12,Reserved_12" newline hexmask.long.word 0x10 0.--11. 1. "COUNT,The max number of read latency cycles incur at external memory for user defined tag" line.long 0x14 "RGX_CR_MAX_USER_MH_TAG_MEM1_LATENCY_1,RGX_CR_MAX_USER_MH_TAG_MEM1_LATENCY_1" hexmask.long 0x14 0.--31. 1. "Reserved_12,Reserved_12" line.long 0x18 "RGX_CR_MIN_NON_CRITICAL_MEM1_LATENCY_MH_TAG_0,RGX_CR_MIN_NON_CRITICAL_MEM1_LATENCY_MH_TAG_0" hexmask.long 0x18 6.--31. 1. "Reserved_6,Reserved_6" newline hexmask.long.byte 0x18 0.--5. 1. "VALUE,The mh_tag value of min read latency cycles for non critical tag" line.long 0x1C "RGX_CR_MIN_NON_CRITICAL_MEM1_LATENCY_MH_TAG_1,RGX_CR_MIN_NON_CRITICAL_MEM1_LATENCY_MH_TAG_1" hexmask.long 0x1C 0.--31. 1. "Reserved_6,Reserved_6" line.long 0x20 "RGX_CR_MAX_NON_CRITICAL_MEM1_LATENCY_MH_TAG_0,RGX_CR_MAX_NON_CRITICAL_MEM1_LATENCY_MH_TAG_0" hexmask.long 0x20 6.--31. 1. "Reserved_6,Reserved_6" newline hexmask.long.byte 0x20 0.--5. 1. "VALUE,The mh_tag value of max read latency cycles for non critical tag" line.long 0x24 "RGX_CR_MAX_NON_CRITICAL_MEM1_LATENCY_MH_TAG_1,RGX_CR_MAX_NON_CRITICAL_MEM1_LATENCY_MH_TAG_1" hexmask.long 0x24 0.--31. 1. "Reserved_6,Reserved_6" group.long 0x7600++0x27 line.long 0x0 "RGX_CR_TA_PERF_0,RGX_CR_TA_PERF_0" hexmask.long 0x0 5.--31. 1. "Reserved_5,Reserved_5" newline bitfld.long 0x0 4. "CLR_3,clear counter 3" "0,1" newline bitfld.long 0x0 3. "CLR_2,clear counter 2" "0,1" newline bitfld.long 0x0 2. "CLR_1,clear counter 1" "0,1" newline bitfld.long 0x0 1. "CLR_0,clear counter 0" "0,1" newline bitfld.long 0x0 0. "CTRL_ENABLE,enables the perf bus counters" "0,1" line.long 0x4 "RGX_CR_TA_PERF_1,RGX_CR_TA_PERF_1" hexmask.long 0x4 0.--31. 1. "Reserved_5,Reserved_5" line.long 0x8 "RGX_CR_TA_PERF_SELECT0_0,RGX_CR_TA_PERF_SELECT0_0" hexmask.long.word 0x8 22.--31. 1. "Reserved_22,Reserved_22" newline bitfld.long 0x8 21. "MODE,reduction mode 0: bitwise increments 1: unsigned count increment" "bitwise increments,unsigned count increment" newline hexmask.long.byte 0x8 16.--20. 1. "GROUP_SELECT,group select see full PERF documentation for signals in each group" newline hexmask.long.word 0x8 0.--15. 1. "BIT_SELECT,bit mask for enabled signals in group" line.long 0xC "RGX_CR_TA_PERF_SELECT0_1,RGX_CR_TA_PERF_SELECT0_1" hexmask.long 0xC 0.--31. 1. "Reserved_22,Reserved_22" line.long 0x10 "RGX_CR_TA_PERF_SELECT1_0,RGX_CR_TA_PERF_SELECT1_0" hexmask.long.word 0x10 22.--31. 1. "Reserved_22,Reserved_22" newline bitfld.long 0x10 21. "MODE,reduction mode 0: bitwise increments 1: unsigned count increment" "bitwise increments,unsigned count increment" newline hexmask.long.byte 0x10 16.--20. 1. "GROUP_SELECT,group select see full PERF documentation for signals in each group" newline hexmask.long.word 0x10 0.--15. 1. "BIT_SELECT,bit mask for enabled signals in group" line.long 0x14 "RGX_CR_TA_PERF_SELECT1_1,RGX_CR_TA_PERF_SELECT1_1" hexmask.long 0x14 0.--31. 1. "Reserved_22,Reserved_22" line.long 0x18 "RGX_CR_TA_PERF_SELECT2_0,RGX_CR_TA_PERF_SELECT2_0" hexmask.long.word 0x18 22.--31. 1. "Reserved_22,Reserved_22" newline bitfld.long 0x18 21. "MODE,reduction mode 0: bitwise increments 1: unsigned count increment" "bitwise increments,unsigned count increment" newline hexmask.long.byte 0x18 16.--20. 1. "GROUP_SELECT,group select see full PERF documentation for signals in each group" newline hexmask.long.word 0x18 0.--15. 1. "BIT_SELECT,bit mask for enabled signals in group" line.long 0x1C "RGX_CR_TA_PERF_SELECT2_1,RGX_CR_TA_PERF_SELECT2_1" hexmask.long 0x1C 0.--31. 1. "Reserved_22,Reserved_22" line.long 0x20 "RGX_CR_TA_PERF_SELECT3_0,RGX_CR_TA_PERF_SELECT3_0" hexmask.long.word 0x20 22.--31. 1. "Reserved_22,Reserved_22" newline bitfld.long 0x20 21. "MODE,reduction mode 0: bitwise increments 1: unsigned count increment" "bitwise increments,unsigned count increment" newline hexmask.long.byte 0x20 16.--20. 1. "GROUP_SELECT,group select see full PERF documentation for signals in each group" newline hexmask.long.word 0x20 0.--15. 1. "BIT_SELECT,bit mask for enabled signals in group" line.long 0x24 "RGX_CR_TA_PERF_SELECT3_1,RGX_CR_TA_PERF_SELECT3_1" hexmask.long 0x24 0.--31. 1. "Reserved_22,Reserved_22" repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) rgroup.long ($2+0x7648)++0x3 line.long 0x0 "RGX_CR_TA_PERF_SELECTED_BITS_$1,RGX_CR_TA_PERF_SELECTED_BITS_0" hexmask.long.word 0x0 16.--31. 1. "REG1,persent bus signals counter 1" newline hexmask.long.word 0x0 0.--15. 1. "REG0,present bus signals counter 0" repeat.end repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) rgroup.long ($2+0x7650)++0x3 line.long 0x0 "RGX_CR_TA_PERF_COUNTER_0_$1,RGX_CR_TA_PERF_COUNTER_0_0" hexmask.long 0x0 0.--31. 1. "REG,counter a0" repeat.end repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) rgroup.long ($2+0x7658)++0x3 line.long 0x0 "RGX_CR_TA_PERF_COUNTER_1_$1,RGX_CR_TA_PERF_COUNTER_1_0" hexmask.long 0x0 0.--31. 1. "REG,counter a0" repeat.end repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) rgroup.long ($2+0x7660)++0x3 line.long 0x0 "RGX_CR_TA_PERF_COUNTER_2_$1,RGX_CR_TA_PERF_COUNTER_2_0" hexmask.long 0x0 0.--31. 1. "REG,counter a0" repeat.end repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) rgroup.long ($2+0x7668)++0x3 line.long 0x0 "RGX_CR_TA_PERF_COUNTER_3_$1,RGX_CR_TA_PERF_COUNTER_3_0" hexmask.long 0x0 0.--31. 1. "REG,counter a0" repeat.end group.long 0x7700++0x27 line.long 0x0 "RGX_CR_RASTERISATION_PERF_0,RGX_CR_RASTERISATION_PERF_0" hexmask.long 0x0 5.--31. 1. "Reserved_5,Reserved_5" newline bitfld.long 0x0 4. "CLR_3,clear counter 3" "0,1" newline bitfld.long 0x0 3. "CLR_2,clear counter 2" "0,1" newline bitfld.long 0x0 2. "CLR_1,clear counter 1" "0,1" newline bitfld.long 0x0 1. "CLR_0,clear counter 0" "0,1" newline bitfld.long 0x0 0. "CTRL_ENABLE,enables the perf bus counters" "0,1" line.long 0x4 "RGX_CR_RASTERISATION_PERF_1,RGX_CR_RASTERISATION_PERF_1" hexmask.long 0x4 0.--31. 1. "Reserved_5,Reserved_5" line.long 0x8 "RGX_CR_RASTERISATION_PERF_SELECT0_0,RGX_CR_RASTERISATION_PERF_SELECT0_0" hexmask.long.word 0x8 22.--31. 1. "Reserved_22,Reserved_22" newline bitfld.long 0x8 21. "MODE,reduction mode 0: bitwise increments 1: unsigned count increment" "bitwise increments,unsigned count increment" newline hexmask.long.byte 0x8 16.--20. 1. "GROUP_SELECT,group select see full PERF documenrasterisationtion for signals in each group" newline hexmask.long.word 0x8 0.--15. 1. "BIT_SELECT,bit mask for enabled signals in group" line.long 0xC "RGX_CR_RASTERISATION_PERF_SELECT0_1,RGX_CR_RASTERISATION_PERF_SELECT0_1" hexmask.long 0xC 0.--31. 1. "Reserved_22,Reserved_22" line.long 0x10 "RGX_CR_RASTERISATION_PERF_SELECT1_0,RGX_CR_RASTERISATION_PERF_SELECT1_0" hexmask.long.word 0x10 22.--31. 1. "Reserved_22,Reserved_22" newline bitfld.long 0x10 21. "MODE,reduction mode 0: bitwise increments 1: unsigned count increment" "bitwise increments,unsigned count increment" newline hexmask.long.byte 0x10 16.--20. 1. "GROUP_SELECT,group select see full PERF documenrasterisationtion for signals in each group" newline hexmask.long.word 0x10 0.--15. 1. "BIT_SELECT,bit mask for enabled signals in group" line.long 0x14 "RGX_CR_RASTERISATION_PERF_SELECT1_1,RGX_CR_RASTERISATION_PERF_SELECT1_1" hexmask.long 0x14 0.--31. 1. "Reserved_22,Reserved_22" line.long 0x18 "RGX_CR_RASTERISATION_PERF_SELECT2_0,RGX_CR_RASTERISATION_PERF_SELECT2_0" hexmask.long.word 0x18 22.--31. 1. "Reserved_22,Reserved_22" newline bitfld.long 0x18 21. "MODE,reduction mode 0: bitwise increments 1: unsigned count increment" "bitwise increments,unsigned count increment" newline hexmask.long.byte 0x18 16.--20. 1. "GROUP_SELECT,group select see full PERF documenrasterisationtion for signals in each group" newline hexmask.long.word 0x18 0.--15. 1. "BIT_SELECT,bit mask for enabled signals in group" line.long 0x1C "RGX_CR_RASTERISATION_PERF_SELECT2_1,RGX_CR_RASTERISATION_PERF_SELECT2_1" hexmask.long 0x1C 0.--31. 1. "Reserved_22,Reserved_22" line.long 0x20 "RGX_CR_RASTERISATION_PERF_SELECT3_0,RGX_CR_RASTERISATION_PERF_SELECT3_0" hexmask.long.word 0x20 22.--31. 1. "Reserved_22,Reserved_22" newline bitfld.long 0x20 21. "MODE,reduction mode 0: bitwise increments 1: unsigned count increment" "bitwise increments,unsigned count increment" newline hexmask.long.byte 0x20 16.--20. 1. "GROUP_SELECT,group select see full PERF documenrasterisationtion for signals in each group" newline hexmask.long.word 0x20 0.--15. 1. "BIT_SELECT,bit mask for enabled signals in group" line.long 0x24 "RGX_CR_RASTERISATION_PERF_SELECT3_1,RGX_CR_RASTERISATION_PERF_SELECT3_1" hexmask.long 0x24 0.--31. 1. "Reserved_22,Reserved_22" repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) rgroup.long ($2+0x7748)++0x3 line.long 0x0 "RGX_CR_RASTERISATION_PERF_SELECTED_BITS_$1,RGX_CR_RASTERISATION_PERF_SELECTED_BITS_0" hexmask.long.word 0x0 16.--31. 1. "REG1,persent bus signals counter 1" newline hexmask.long.word 0x0 0.--15. 1. "REG0,present bus signals counter 0" repeat.end repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) rgroup.long ($2+0x7750)++0x3 line.long 0x0 "RGX_CR_RASTERISATION_PERF_COUNTER_0_$1,RGX_CR_RASTERISATION_PERF_COUNTER_0_0" hexmask.long 0x0 0.--31. 1. "REG,counter a0" repeat.end repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) rgroup.long ($2+0x7758)++0x3 line.long 0x0 "RGX_CR_RASTERISATION_PERF_COUNTER_1_$1,RGX_CR_RASTERISATION_PERF_COUNTER_1_0" hexmask.long 0x0 0.--31. 1. "REG,counter a0" repeat.end repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) rgroup.long ($2+0x7760)++0x3 line.long 0x0 "RGX_CR_RASTERISATION_PERF_COUNTER_2_$1,RGX_CR_RASTERISATION_PERF_COUNTER_2_0" hexmask.long 0x0 0.--31. 1. "REG,counter a0" repeat.end repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) rgroup.long ($2+0x7768)++0x3 line.long 0x0 "RGX_CR_RASTERISATION_PERF_COUNTER_3_$1,RGX_CR_RASTERISATION_PERF_COUNTER_3_0" hexmask.long 0x0 0.--31. 1. "REG,counter a0" repeat.end group.long 0x7800++0x27 line.long 0x0 "RGX_CR_HUB_BIFPMCACHE_PERF_0,RGX_CR_HUB_BIFPMCACHE_PERF_0" hexmask.long 0x0 5.--31. 1. "Reserved_5,Reserved_5" newline bitfld.long 0x0 4. "CLR_3,clear counter 3" "0,1" newline bitfld.long 0x0 3. "CLR_2,clear counter 2" "0,1" newline bitfld.long 0x0 2. "CLR_1,clear counter 1" "0,1" newline bitfld.long 0x0 1. "CLR_0,clear counter 0" "0,1" newline bitfld.long 0x0 0. "CTRL_ENABLE,enables the perf bus counters" "0,1" line.long 0x4 "RGX_CR_HUB_BIFPMCACHE_PERF_1,RGX_CR_HUB_BIFPMCACHE_PERF_1" hexmask.long 0x4 0.--31. 1. "Reserved_5,Reserved_5" line.long 0x8 "RGX_CR_HUB_BIFPMCACHE_PERF_SELECT0_0,RGX_CR_HUB_BIFPMCACHE_PERF_SELECT0_0" hexmask.long.word 0x8 22.--31. 1. "Reserved_22,Reserved_22" newline bitfld.long 0x8 21. "MODE,reduction mode 0: bitwise increments 1: unsigned count increment" "bitwise increments,unsigned count increment" newline hexmask.long.byte 0x8 16.--20. 1. "GROUP_SELECT,group select see full PERF documenhub_bifpmcachetion for signals in each group" newline hexmask.long.word 0x8 0.--15. 1. "BIT_SELECT,bit mask for enabled signals in group" line.long 0xC "RGX_CR_HUB_BIFPMCACHE_PERF_SELECT0_1,RGX_CR_HUB_BIFPMCACHE_PERF_SELECT0_1" hexmask.long 0xC 0.--31. 1. "Reserved_22,Reserved_22" line.long 0x10 "RGX_CR_HUB_BIFPMCACHE_PERF_SELECT1_0,RGX_CR_HUB_BIFPMCACHE_PERF_SELECT1_0" hexmask.long.word 0x10 22.--31. 1. "Reserved_22,Reserved_22" newline bitfld.long 0x10 21. "MODE,reduction mode 0: bitwise increments 1: unsigned count increment" "bitwise increments,unsigned count increment" newline hexmask.long.byte 0x10 16.--20. 1. "GROUP_SELECT,group select see full PERF documenhub_bifpmcachetion for signals in each group" newline hexmask.long.word 0x10 0.--15. 1. "BIT_SELECT,bit mask for enabled signals in group" line.long 0x14 "RGX_CR_HUB_BIFPMCACHE_PERF_SELECT1_1,RGX_CR_HUB_BIFPMCACHE_PERF_SELECT1_1" hexmask.long 0x14 0.--31. 1. "Reserved_22,Reserved_22" line.long 0x18 "RGX_CR_HUB_BIFPMCACHE_PERF_SELECT2_0,RGX_CR_HUB_BIFPMCACHE_PERF_SELECT2_0" hexmask.long.word 0x18 22.--31. 1. "Reserved_22,Reserved_22" newline bitfld.long 0x18 21. "MODE,reduction mode 0: bitwise increments 1: unsigned count increment" "bitwise increments,unsigned count increment" newline hexmask.long.byte 0x18 16.--20. 1. "GROUP_SELECT,group select see full PERF documenhub_bifpmcachetion for signals in each group" newline hexmask.long.word 0x18 0.--15. 1. "BIT_SELECT,bit mask for enabled signals in group" line.long 0x1C "RGX_CR_HUB_BIFPMCACHE_PERF_SELECT2_1,RGX_CR_HUB_BIFPMCACHE_PERF_SELECT2_1" hexmask.long 0x1C 0.--31. 1. "Reserved_22,Reserved_22" line.long 0x20 "RGX_CR_HUB_BIFPMCACHE_PERF_SELECT3_0,RGX_CR_HUB_BIFPMCACHE_PERF_SELECT3_0" hexmask.long.word 0x20 22.--31. 1. "Reserved_22,Reserved_22" newline bitfld.long 0x20 21. "MODE,reduction mode 0: bitwise increments 1: unsigned count increment" "bitwise increments,unsigned count increment" newline hexmask.long.byte 0x20 16.--20. 1. "GROUP_SELECT,group select see full PERF documenhub_bifpmcachetion for signals in each group" newline hexmask.long.word 0x20 0.--15. 1. "BIT_SELECT,bit mask for enabled signals in group" line.long 0x24 "RGX_CR_HUB_BIFPMCACHE_PERF_SELECT3_1,RGX_CR_HUB_BIFPMCACHE_PERF_SELECT3_1" hexmask.long 0x24 0.--31. 1. "Reserved_22,Reserved_22" repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) rgroup.long ($2+0x7848)++0x3 line.long 0x0 "RGX_CR_HUB_BIFPMCACHE_PERF_SELECTED_BITS_$1,RGX_CR_HUB_BIFPMCACHE_PERF_SELECTED_BITS_0" hexmask.long.word 0x0 16.--31. 1. "REG1,persent bus signals counter 1" newline hexmask.long.word 0x0 0.--15. 1. "REG0,present bus signals counter 0" repeat.end repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) rgroup.long ($2+0x7850)++0x3 line.long 0x0 "RGX_CR_HUB_BIFPMCACHE_PERF_COUNTER_0_$1,RGX_CR_HUB_BIFPMCACHE_PERF_COUNTER_0_0" hexmask.long 0x0 0.--31. 1. "REG,counter a0" repeat.end repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) rgroup.long ($2+0x7858)++0x3 line.long 0x0 "RGX_CR_HUB_BIFPMCACHE_PERF_COUNTER_1_$1,RGX_CR_HUB_BIFPMCACHE_PERF_COUNTER_1_0" hexmask.long 0x0 0.--31. 1. "REG,counter a0" repeat.end repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) rgroup.long ($2+0x7860)++0x3 line.long 0x0 "RGX_CR_HUB_BIFPMCACHE_PERF_COUNTER_2_$1,RGX_CR_HUB_BIFPMCACHE_PERF_COUNTER_2_0" hexmask.long 0x0 0.--31. 1. "REG,counter a0" repeat.end repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) rgroup.long ($2+0x7868)++0x3 line.long 0x0 "RGX_CR_HUB_BIFPMCACHE_PERF_COUNTER_3_$1,RGX_CR_HUB_BIFPMCACHE_PERF_COUNTER_3_0" hexmask.long 0x0 0.--31. 1. "REG,counter a0" repeat.end group.long 0x7900++0x27 line.long 0x0 "RGX_CR_TPU_MCU_L0_PERF_0,RGX_CR_TPU_MCU_L0_PERF_0" hexmask.long 0x0 5.--31. 1. "Reserved_5,Reserved_5" newline bitfld.long 0x0 4. "CLR_3,clear counter 3" "0,1" newline bitfld.long 0x0 3. "CLR_2,clear counter 2" "0,1" newline bitfld.long 0x0 2. "CLR_1,clear counter 1" "0,1" newline bitfld.long 0x0 1. "CLR_0,clear counter 0" "0,1" newline bitfld.long 0x0 0. "CTRL_ENABLE,enables the perf bus counters" "0,1" line.long 0x4 "RGX_CR_TPU_MCU_L0_PERF_1,RGX_CR_TPU_MCU_L0_PERF_1" hexmask.long 0x4 0.--31. 1. "Reserved_5,Reserved_5" line.long 0x8 "RGX_CR_TPU_MCU_L0_PERF_SELECT0_0,RGX_CR_TPU_MCU_L0_PERF_SELECT0_0" hexmask.long.word 0x8 22.--31. 1. "Reserved_22,Reserved_22" newline bitfld.long 0x8 21. "MODE,reduction mode 0: bitwise increments 1: unsigned count increment" "bitwise increments,unsigned count increment" newline hexmask.long.byte 0x8 16.--20. 1. "GROUP_SELECT,group select see full PERF documentation for signals in each group" newline hexmask.long.word 0x8 0.--15. 1. "BIT_SELECT,bit mask for enabled signals in group" line.long 0xC "RGX_CR_TPU_MCU_L0_PERF_SELECT0_1,RGX_CR_TPU_MCU_L0_PERF_SELECT0_1" bitfld.long 0xC 30.--31. "Reserved_62,Reserved_62" "0,1,2,3" newline hexmask.long.word 0xC 16.--29. 1. "BATCH_MAX,this is the min batch number which will be counted in this group" newline bitfld.long 0xC 14.--15. "Reserved_46,Reserved_46" "0,1,2,3" newline hexmask.long.word 0xC 0.--13. 1. "BATCH_MIN,this is the min batch number which will be counted in this group" line.long 0x10 "RGX_CR_TPU_MCU_L0_PERF_SELECT1_0,RGX_CR_TPU_MCU_L0_PERF_SELECT1_0" hexmask.long.word 0x10 22.--31. 1. "Reserved_22,Reserved_22" newline bitfld.long 0x10 21. "MODE,reduction mode 0: bitwise increments 1: unsigned count increment" "bitwise increments,unsigned count increment" newline hexmask.long.byte 0x10 16.--20. 1. "GROUP_SELECT,group select see full PERF documentation for signals in each group" newline hexmask.long.word 0x10 0.--15. 1. "BIT_SELECT,bit mask for enabled signals in group" line.long 0x14 "RGX_CR_TPU_MCU_L0_PERF_SELECT1_1,RGX_CR_TPU_MCU_L0_PERF_SELECT1_1" bitfld.long 0x14 30.--31. "Reserved_62,Reserved_62" "0,1,2,3" newline hexmask.long.word 0x14 16.--29. 1. "BATCH_MAX,this is the min batch number which will be counted in this group" newline bitfld.long 0x14 14.--15. "Reserved_46,Reserved_46" "0,1,2,3" newline hexmask.long.word 0x14 0.--13. 1. "BATCH_MIN,this is the min batch number which will be counted in this group" line.long 0x18 "RGX_CR_TPU_MCU_L0_PERF_SELECT2_0,RGX_CR_TPU_MCU_L0_PERF_SELECT2_0" hexmask.long.word 0x18 22.--31. 1. "Reserved_22,Reserved_22" newline bitfld.long 0x18 21. "MODE,reduction mode 0: bitwise increments 1: unsigned count increment" "bitwise increments,unsigned count increment" newline hexmask.long.byte 0x18 16.--20. 1. "GROUP_SELECT,group select see full PERF documentation for signals in each group" newline hexmask.long.word 0x18 0.--15. 1. "BIT_SELECT,bit mask for enabled signals in group" line.long 0x1C "RGX_CR_TPU_MCU_L0_PERF_SELECT2_1,RGX_CR_TPU_MCU_L0_PERF_SELECT2_1" bitfld.long 0x1C 30.--31. "Reserved_62,Reserved_62" "0,1,2,3" newline hexmask.long.word 0x1C 16.--29. 1. "BATCH_MAX,this is the min batch number which will be counted in this group" newline bitfld.long 0x1C 14.--15. "Reserved_46,Reserved_46" "0,1,2,3" newline hexmask.long.word 0x1C 0.--13. 1. "BATCH_MIN,this is the min batch number which will be counted in this group" line.long 0x20 "RGX_CR_TPU_MCU_L0_PERF_SELECT3_0,RGX_CR_TPU_MCU_L0_PERF_SELECT3_0" hexmask.long.word 0x20 22.--31. 1. "Reserved_22,Reserved_22" newline bitfld.long 0x20 21. "MODE,reduction mode 0: bitwise increments 1: unsigned count increment" "bitwise increments,unsigned count increment" newline hexmask.long.byte 0x20 16.--20. 1. "GROUP_SELECT,group select see full PERF documentation for signals in each group" newline hexmask.long.word 0x20 0.--15. 1. "BIT_SELECT,bit mask for enabled signals in group" line.long 0x24 "RGX_CR_TPU_MCU_L0_PERF_SELECT3_1,RGX_CR_TPU_MCU_L0_PERF_SELECT3_1" bitfld.long 0x24 30.--31. "Reserved_62,Reserved_62" "0,1,2,3" newline hexmask.long.word 0x24 16.--29. 1. "BATCH_MAX,this is the min batch number which will be counted in this group" newline bitfld.long 0x24 14.--15. "Reserved_46,Reserved_46" "0,1,2,3" newline hexmask.long.word 0x24 0.--13. 1. "BATCH_MIN,this is the min batch number which will be counted in this group" repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) rgroup.long ($2+0x7948)++0x3 line.long 0x0 "RGX_CR_TPU_MCU_L0_PERF_SELECTED_BITS_$1,RGX_CR_TPU_MCU_L0_PERF_SELECTED_BITS_0" hexmask.long.word 0x0 16.--31. 1. "REG1,persent bus signals counter 1" newline hexmask.long.word 0x0 0.--15. 1. "REG0,present bus signals counter 0" repeat.end repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) rgroup.long ($2+0x7950)++0x3 line.long 0x0 "RGX_CR_TPU_MCU_L0_PERF_COUNTER_0_$1,RGX_CR_TPU_MCU_L0_PERF_COUNTER_0_0" hexmask.long 0x0 0.--31. 1. "REG,counter a0" repeat.end repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) rgroup.long ($2+0x7958)++0x3 line.long 0x0 "RGX_CR_TPU_MCU_L0_PERF_COUNTER_1_$1,RGX_CR_TPU_MCU_L0_PERF_COUNTER_1_0" hexmask.long 0x0 0.--31. 1. "REG,counter a0" repeat.end repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) rgroup.long ($2+0x7960)++0x3 line.long 0x0 "RGX_CR_TPU_MCU_L0_PERF_COUNTER_2_$1,RGX_CR_TPU_MCU_L0_PERF_COUNTER_2_0" hexmask.long 0x0 0.--31. 1. "REG,counter a0" repeat.end repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) rgroup.long ($2+0x7968)++0x3 line.long 0x0 "RGX_CR_TPU_MCU_L0_PERF_COUNTER_3_$1,RGX_CR_TPU_MCU_L0_PERF_COUNTER_3_0" hexmask.long 0x0 0.--31. 1. "REG,counter a0" repeat.end group.long 0x8000++0xF line.long 0x0 "RGX_CR_USC_INDIRECT_0,RGX_CR_USC_INDIRECT_0" hexmask.long 0x0 4.--31. 1. "Reserved_4,Reserved_4" newline hexmask.long.byte 0x0 0.--3. 1. "ADDRESS,ADDRESS" line.long 0x4 "RGX_CR_USC_INDIRECT_1,RGX_CR_USC_INDIRECT_1" hexmask.long 0x4 0.--31. 1. "Reserved_4,Reserved_4" line.long 0x8 "RGX_CR_TPU_MCU_L0_INDIRECT_0,RGX_CR_TPU_MCU_L0_INDIRECT_0" hexmask.long 0x8 3.--31. 1. "Reserved_3,Reserved_3" newline bitfld.long 0x8 0.--2. "ADDRESS,ADDRESS" "0,1,2,3,4,5,6,7" line.long 0xC "RGX_CR_TPU_MCU_L0_INDIRECT_1,RGX_CR_TPU_MCU_L0_INDIRECT_1" hexmask.long 0xC 0.--31. 1. "Reserved_3,Reserved_3" group.long 0x8020++0x17 line.long 0x0 "RGX_CR_USC_TPU_LOW_PRECISION_ENABLE_0,Enable signal to use low precision across USC and TPU (TAG) in coordinates. gradients and LOD value (calculated or supplied)" hexmask.long 0x0 1.--31. 1. "Reserved_1,Reserved_1" newline bitfld.long 0x0 0. "VALUE,VALUE" "0,1" line.long 0x4 "RGX_CR_USC_TPU_LOW_PRECISION_ENABLE_1,Enable signal to use low precision across USC and TPU (TAG) in coordinates. gradients and LOD value (calculated or supplied)" hexmask.long 0x4 0.--31. 1. "Reserved_1,Reserved_1" line.long 0x8 "RGX_CR_TPU_MCU_L0_PERF_INDIRECT_0,RGX_CR_TPU_MCU_L0_PERF_INDIRECT_0" hexmask.long 0x8 3.--31. 1. "Reserved_3,Reserved_3" newline bitfld.long 0x8 0.--2. "ADDRESS,ADDRESS" "0,1,2,3,4,5,6,7" line.long 0xC "RGX_CR_TPU_MCU_L0_PERF_INDIRECT_1,RGX_CR_TPU_MCU_L0_PERF_INDIRECT_1" hexmask.long 0xC 0.--31. 1. "Reserved_3,Reserved_3" line.long 0x10 "RGX_CR_USC_PERF_INDIRECT_0,RGX_CR_USC_PERF_INDIRECT_0" hexmask.long 0x10 4.--31. 1. "Reserved_4,Reserved_4" newline hexmask.long.byte 0x10 0.--3. 1. "ADDRESS,ADDRESS" line.long 0x14 "RGX_CR_USC_PERF_INDIRECT_1,RGX_CR_USC_PERF_INDIRECT_1" hexmask.long 0x14 0.--31. 1. "Reserved_4,Reserved_4" group.long 0x8100++0x27 line.long 0x0 "RGX_CR_USC_PERF_0,RGX_CR_USC_PERF_0" hexmask.long 0x0 5.--31. 1. "Reserved_5,Reserved_5" newline bitfld.long 0x0 4. "CLR_3,clear counter 3" "0,1" newline bitfld.long 0x0 3. "CLR_2,clear counter 2" "0,1" newline bitfld.long 0x0 2. "CLR_1,clear counter 1" "0,1" newline bitfld.long 0x0 1. "CLR_0,clear counter 0" "0,1" newline bitfld.long 0x0 0. "CTRL_ENABLE,enables the perf bus counters" "0,1" line.long 0x4 "RGX_CR_USC_PERF_1,RGX_CR_USC_PERF_1" hexmask.long 0x4 0.--31. 1. "Reserved_5,Reserved_5" line.long 0x8 "RGX_CR_USC_PERF_SELECT0_0,RGX_CR_USC_PERF_SELECT0_0" hexmask.long.word 0x8 22.--31. 1. "Reserved_22,Reserved_22" newline bitfld.long 0x8 21. "MODE,reduction mode 0: bitwise increments 1: unsigned count increment" "bitwise increments,unsigned count increment" newline hexmask.long.byte 0x8 16.--20. 1. "GROUP_SELECT,group select see full PERF documenusction for signals in each group" newline hexmask.long.word 0x8 0.--15. 1. "BIT_SELECT,bit mask for enabled signals in group" line.long 0xC "RGX_CR_USC_PERF_SELECT0_1,RGX_CR_USC_PERF_SELECT0_1" bitfld.long 0xC 30.--31. "Reserved_62,Reserved_62" "0,1,2,3" newline hexmask.long.word 0xC 16.--29. 1. "BATCH_MAX,this is the min batch number which will be counted in this group" newline bitfld.long 0xC 14.--15. "Reserved_46,Reserved_46" "0,1,2,3" newline hexmask.long.word 0xC 0.--13. 1. "BATCH_MIN,this is the min batch number which will be counted in this group" line.long 0x10 "RGX_CR_USC_PERF_SELECT1_0,RGX_CR_USC_PERF_SELECT1_0" hexmask.long.word 0x10 22.--31. 1. "Reserved_22,Reserved_22" newline bitfld.long 0x10 21. "MODE,reduction mode 0: bitwise increments 1: unsigned count increment" "bitwise increments,unsigned count increment" newline hexmask.long.byte 0x10 16.--20. 1. "GROUP_SELECT,group select see full PERF documenusction for signals in each group" newline hexmask.long.word 0x10 0.--15. 1. "BIT_SELECT,bit mask for enabled signals in group" line.long 0x14 "RGX_CR_USC_PERF_SELECT1_1,RGX_CR_USC_PERF_SELECT1_1" bitfld.long 0x14 30.--31. "Reserved_62,Reserved_62" "0,1,2,3" newline hexmask.long.word 0x14 16.--29. 1. "BATCH_MAX,this is the min batch number which will be counted in this group" newline bitfld.long 0x14 14.--15. "Reserved_46,Reserved_46" "0,1,2,3" newline hexmask.long.word 0x14 0.--13. 1. "BATCH_MIN,this is the min batch number which will be counted in this group" line.long 0x18 "RGX_CR_USC_PERF_SELECT2_0,RGX_CR_USC_PERF_SELECT2_0" hexmask.long.word 0x18 22.--31. 1. "Reserved_22,Reserved_22" newline bitfld.long 0x18 21. "MODE,reduction mode 0: bitwise increments 1: unsigned count increment" "bitwise increments,unsigned count increment" newline hexmask.long.byte 0x18 16.--20. 1. "GROUP_SELECT,group select see full PERF documenusction for signals in each group" newline hexmask.long.word 0x18 0.--15. 1. "BIT_SELECT,bit mask for enabled signals in group" line.long 0x1C "RGX_CR_USC_PERF_SELECT2_1,RGX_CR_USC_PERF_SELECT2_1" bitfld.long 0x1C 30.--31. "Reserved_62,Reserved_62" "0,1,2,3" newline hexmask.long.word 0x1C 16.--29. 1. "BATCH_MAX,this is the min batch number which will be counted in this group" newline bitfld.long 0x1C 14.--15. "Reserved_46,Reserved_46" "0,1,2,3" newline hexmask.long.word 0x1C 0.--13. 1. "BATCH_MIN,this is the min batch number which will be counted in this group" line.long 0x20 "RGX_CR_USC_PERF_SELECT3_0,RGX_CR_USC_PERF_SELECT3_0" hexmask.long.word 0x20 22.--31. 1. "Reserved_22,Reserved_22" newline bitfld.long 0x20 21. "MODE,reduction mode 0: bitwise increments 1: unsigned count increment" "bitwise increments,unsigned count increment" newline hexmask.long.byte 0x20 16.--20. 1. "GROUP_SELECT,group select see full PERF documenusction for signals in each group" newline hexmask.long.word 0x20 0.--15. 1. "BIT_SELECT,bit mask for enabled signals in group" line.long 0x24 "RGX_CR_USC_PERF_SELECT3_1,RGX_CR_USC_PERF_SELECT3_1" bitfld.long 0x24 30.--31. "Reserved_62,Reserved_62" "0,1,2,3" newline hexmask.long.word 0x24 16.--29. 1. "BATCH_MAX,this is the min batch number which will be counted in this group" newline bitfld.long 0x24 14.--15. "Reserved_46,Reserved_46" "0,1,2,3" newline hexmask.long.word 0x24 0.--13. 1. "BATCH_MIN,this is the min batch number which will be counted in this group" repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) rgroup.long ($2+0x8148)++0x3 line.long 0x0 "RGX_CR_USC_PERF_SELECTED_BITS_$1,RGX_CR_USC_PERF_SELECTED_BITS_0" hexmask.long.word 0x0 16.--31. 1. "REG1,persent bus signals counter 1" newline hexmask.long.word 0x0 0.--15. 1. "REG0,present bus signals counter 0" repeat.end repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) rgroup.long ($2+0x8150)++0x3 line.long 0x0 "RGX_CR_USC_PERF_COUNTER_0_$1,RGX_CR_USC_PERF_COUNTER_0_0" hexmask.long 0x0 0.--31. 1. "REG,counter a0" repeat.end repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) rgroup.long ($2+0x8158)++0x3 line.long 0x0 "RGX_CR_USC_PERF_COUNTER_1_$1,RGX_CR_USC_PERF_COUNTER_1_0" hexmask.long 0x0 0.--31. 1. "REG,counter a0" repeat.end repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) rgroup.long ($2+0x8160)++0x3 line.long 0x0 "RGX_CR_USC_PERF_COUNTER_2_$1,RGX_CR_USC_PERF_COUNTER_2_0" hexmask.long 0x0 0.--31. 1. "REG,counter a0" repeat.end repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) rgroup.long ($2+0x8168)++0x3 line.long 0x0 "RGX_CR_USC_PERF_COUNTER_3_$1,RGX_CR_USC_PERF_COUNTER_3_0" hexmask.long 0x0 0.--31. 1. "REG,counter a0" repeat.end group.long 0x8238++0x7 line.long 0x0 "RGX_CR_RASTERISATION_INDIRECT_0,RGX_CR_RASTERISATION_INDIRECT_0" hexmask.long 0x0 4.--31. 1. "Reserved_4,Reserved_4" newline hexmask.long.byte 0x0 0.--3. 1. "ADDRESS,ADDRESS" line.long 0x4 "RGX_CR_RASTERISATION_INDIRECT_1,RGX_CR_RASTERISATION_INDIRECT_1" hexmask.long 0x4 0.--31. 1. "Reserved_4,Reserved_4" group.long 0x8318++0x7 line.long 0x0 "RGX_CR_RASTERISATION_PERF_INDIRECT_0,RGX_CR_RASTERISATION_PERF_INDIRECT_0" hexmask.long 0x0 4.--31. 1. "Reserved_4,Reserved_4" newline hexmask.long.byte 0x0 0.--3. 1. "ADDRESS,ADDRESS" line.long 0x4 "RGX_CR_RASTERISATION_PERF_INDIRECT_1,RGX_CR_RASTERISATION_PERF_INDIRECT_1" hexmask.long 0x4 0.--31. 1. "Reserved_4,Reserved_4" group.long 0x83D8++0x1F line.long 0x0 "RGX_CR_PBE_PERF_INDIRECT_0,RGX_CR_PBE_PERF_INDIRECT_0" hexmask.long 0x0 4.--31. 1. "Reserved_4,Reserved_4" newline hexmask.long.byte 0x0 0.--3. 1. "ADDRESS,ADDRESS" line.long 0x4 "RGX_CR_PBE_PERF_INDIRECT_1,RGX_CR_PBE_PERF_INDIRECT_1" hexmask.long 0x4 0.--31. 1. "Reserved_4,Reserved_4" line.long 0x8 "RGX_CR_PBE_INDIRECT_0,RGX_CR_PBE_INDIRECT_0" hexmask.long 0x8 4.--31. 1. "Reserved_4,Reserved_4" newline hexmask.long.byte 0x8 0.--3. 1. "ADDRESS,ADDRESS" line.long 0xC "RGX_CR_PBE_INDIRECT_1,RGX_CR_PBE_INDIRECT_1" hexmask.long 0xC 0.--31. 1. "Reserved_4,Reserved_4" line.long 0x10 "RGX_CR_TPU_INDIRECT_0,RGX_CR_TPU_INDIRECT_0" hexmask.long 0x10 3.--31. 1. "Reserved_3,Reserved_3" newline bitfld.long 0x10 0.--2. "ADDRESS,ADDRESS" "0,1,2,3,4,5,6,7" line.long 0x14 "RGX_CR_TPU_INDIRECT_1,RGX_CR_TPU_INDIRECT_1" hexmask.long 0x14 0.--31. 1. "Reserved_3,Reserved_3" line.long 0x18 "RGX_CR_TPU_PERF_INDIRECT_0,RGX_CR_TPU_PERF_INDIRECT_0" hexmask.long 0x18 3.--31. 1. "Reserved_3,Reserved_3" newline bitfld.long 0x18 0.--2. "ADDRESS,ADDRESS" "0,1,2,3,4,5,6,7" line.long 0x1C "RGX_CR_TPU_PERF_INDIRECT_1,RGX_CR_TPU_PERF_INDIRECT_1" hexmask.long 0x1C 0.--31. 1. "Reserved_3,Reserved_3" group.long 0x8478++0x1F line.long 0x0 "RGX_CR_PBE_PERF_0,RGX_CR_PBE_PERF_0" hexmask.long 0x0 5.--31. 1. "Reserved_5,Reserved_5" newline bitfld.long 0x0 4. "CLR_3,clear counter 3" "0,1" newline bitfld.long 0x0 3. "CLR_2,clear counter 2" "0,1" newline bitfld.long 0x0 2. "CLR_1,clear counter 1" "0,1" newline bitfld.long 0x0 1. "CLR_0,clear counter 0" "0,1" newline bitfld.long 0x0 0. "CTRL_ENABLE,enables the perf bus counters" "0,1" line.long 0x4 "RGX_CR_PBE_PERF_1,RGX_CR_PBE_PERF_1" hexmask.long 0x4 0.--31. 1. "Reserved_5,Reserved_5" line.long 0x8 "RGX_CR_PBE_PERF_SELECT0_0,RGX_CR_PBE_PERF_SELECT0_0" hexmask.long.word 0x8 22.--31. 1. "Reserved_22,Reserved_22" newline bitfld.long 0x8 21. "MODE,reduction mode 0: bitwise increments 1: unsigned count increment" "bitwise increments,unsigned count increment" newline hexmask.long.byte 0x8 16.--20. 1. "GROUP_SELECT,group select see full PERF documentation for signals in each group" newline hexmask.long.word 0x8 0.--15. 1. "BIT_SELECT,bit mask for enabled signals in group" line.long 0xC "RGX_CR_PBE_PERF_SELECT0_1,RGX_CR_PBE_PERF_SELECT0_1" bitfld.long 0xC 30.--31. "Reserved_62,Reserved_62" "0,1,2,3" newline hexmask.long.word 0xC 16.--29. 1. "BATCH_MAX,this is the max batch number which will be counted in this group" newline bitfld.long 0xC 14.--15. "Reserved_46,Reserved_46" "0,1,2,3" newline hexmask.long.word 0xC 0.--13. 1. "BATCH_MIN,this is the min batch number which will be counted in this group" line.long 0x10 "RGX_CR_PBE_PERF_SELECT1_0,RGX_CR_PBE_PERF_SELECT1_0" hexmask.long.word 0x10 22.--31. 1. "Reserved_22,Reserved_22" newline bitfld.long 0x10 21. "MODE,reduction mode 0: bitwise increments 1: unsigned count increment" "bitwise increments,unsigned count increment" newline hexmask.long.byte 0x10 16.--20. 1. "GROUP_SELECT,group select see full PERF documentation for signals in each group" newline hexmask.long.word 0x10 0.--15. 1. "BIT_SELECT,bit mask for enabled signals in group" line.long 0x14 "RGX_CR_PBE_PERF_SELECT1_1,RGX_CR_PBE_PERF_SELECT1_1" bitfld.long 0x14 30.--31. "Reserved_62,Reserved_62" "0,1,2,3" newline hexmask.long.word 0x14 16.--29. 1. "BATCH_MAX,this is the max batch number which will be counted in this group" newline bitfld.long 0x14 14.--15. "Reserved_46,Reserved_46" "0,1,2,3" newline hexmask.long.word 0x14 0.--13. 1. "BATCH_MIN,this is the min batch number which will be counted in this group" line.long 0x18 "RGX_CR_PBE_PERF_SELECT2_0,RGX_CR_PBE_PERF_SELECT2_0" hexmask.long.word 0x18 22.--31. 1. "Reserved_22,Reserved_22" newline bitfld.long 0x18 21. "MODE,reduction mode 0: bitwise increments 1: unsigned count increment" "bitwise increments,unsigned count increment" newline hexmask.long.byte 0x18 16.--20. 1. "GROUP_SELECT,group select see full PERF documentation for signals in each group" newline hexmask.long.word 0x18 0.--15. 1. "BIT_SELECT,bit mask for enabled signals in group" line.long 0x1C "RGX_CR_PBE_PERF_SELECT2_1,RGX_CR_PBE_PERF_SELECT2_1" bitfld.long 0x1C 30.--31. "Reserved_62,Reserved_62" "0,1,2,3" newline hexmask.long.word 0x1C 16.--29. 1. "BATCH_MAX,this is the max batch number which will be counted in this group" newline bitfld.long 0x1C 14.--15. "Reserved_46,Reserved_46" "0,1,2,3" newline hexmask.long.word 0x1C 0.--13. 1. "BATCH_MIN,this is the min batch number which will be counted in this group" group.long 0x84A0++0x7 line.long 0x0 "RGX_CR_PBE_PERF_SELECT3_0,RGX_CR_PBE_PERF_SELECT3_0" hexmask.long.word 0x0 22.--31. 1. "Reserved_22,Reserved_22" newline bitfld.long 0x0 21. "MODE,reduction mode 0: bitwise increments 1: unsigned count increment" "bitwise increments,unsigned count increment" newline hexmask.long.byte 0x0 16.--20. 1. "GROUP_SELECT,group select see full PERF documentation for signals in each group" newline hexmask.long.word 0x0 0.--15. 1. "BIT_SELECT,bit mask for enabled signals in group" line.long 0x4 "RGX_CR_PBE_PERF_SELECT3_1,RGX_CR_PBE_PERF_SELECT3_1" bitfld.long 0x4 30.--31. "Reserved_62,Reserved_62" "0,1,2,3" newline hexmask.long.word 0x4 16.--29. 1. "BATCH_MAX,this is the max batch number which will be counted in this group" newline bitfld.long 0x4 14.--15. "Reserved_46,Reserved_46" "0,1,2,3" newline hexmask.long.word 0x4 0.--13. 1. "BATCH_MIN,this is the min batch number which will be counted in this group" repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) rgroup.long ($2+0x84A8)++0x3 line.long 0x0 "RGX_CR_PBE_PERF_SELECTED_BITS_$1,RGX_CR_PBE_PERF_SELECTED_BITS_0" hexmask.long.word 0x0 16.--31. 1. "REG1,persent bus signals counter 1" newline hexmask.long.word 0x0 0.--15. 1. "REG0,present bus signals counter 0" repeat.end repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) rgroup.long ($2+0x84B0)++0x3 line.long 0x0 "RGX_CR_PBE_PERF_COUNTER_0_$1,RGX_CR_PBE_PERF_COUNTER_0_0" hexmask.long 0x0 0.--31. 1. "REG,counter a0" repeat.end repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) rgroup.long ($2+0x84B8)++0x3 line.long 0x0 "RGX_CR_PBE_PERF_COUNTER_1_$1,RGX_CR_PBE_PERF_COUNTER_1_0" hexmask.long 0x0 0.--31. 1. "REG,counter a0" repeat.end repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) rgroup.long ($2+0x84C0)++0x3 line.long 0x0 "RGX_CR_PBE_PERF_COUNTER_2_$1,RGX_CR_PBE_PERF_COUNTER_2_0" hexmask.long 0x0 0.--31. 1. "REG,counter a0" repeat.end repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) rgroup.long ($2+0x84C8)++0x3 line.long 0x0 "RGX_CR_PBE_PERF_COUNTER_3_$1,RGX_CR_PBE_PERF_COUNTER_3_0" hexmask.long 0x0 0.--31. 1. "REG,counter a0" repeat.end group.long 0xA000++0x7 line.long 0x0 "RGX_CR_BIF_TRUST_0,Define Requestors/Data Masters which are Trusted/Untrusted and enable/disable the Memory Bus Security feature within the Core When enabled the GPU will emit the security signals out through the external memory interface." hexmask.long.word 0x0 17.--31. 1. "Reserved_17,Reserved_17" newline bitfld.long 0x0 16. "ENABLE,Enable Security feature: 0x1 = Enabled 0x0 = Disabled" "Disabled,Enabled" newline hexmask.long.byte 0x0 9.--15. 1. "DM_TRUSTED,Mask of bits which defines which of the remaining Data Masters are trusted: 0x1 = Trusted 0x0 = Untrusted" newline bitfld.long 0x0 8. "OTHER_COMPUTE_DM_TRUSTED,Defines whether other accesses with the Compute DM are trusted: 0x1 = Trusted 0x0 = Untrusted" "Untrusted,Trusted" newline bitfld.long 0x0 7. "MCU_COMPUTE_DM_TRUSTED,Defines whether MCU accesses with the Compute DM are trusted: 0x1 = Trusted 0x0 = Untrusted" "Untrusted,Trusted" newline bitfld.long 0x0 6. "PBE_COMPUTE_DM_TRUSTED,Defines whether PBE accesses with the Compute DM are trusted: 0x1 = Trusted 0x0 = Untrusted" "Untrusted,Trusted" newline bitfld.long 0x0 5. "OTHER_PIXEL_DM_TRUSTED,Defines whether other accesses with the Pixel DM are trusted: 0x1 = Trusted 0x0 = Untrusted" "Untrusted,Trusted" newline bitfld.long 0x0 4. "MCU_PIXEL_DM_TRUSTED,Defines whether MCU accesses with the Pixel DM are trusted: 0x1 = Trusted 0x0 = Untrusted" "Untrusted,Trusted" newline bitfld.long 0x0 3. "PBE_PIXEL_DM_TRUSTED,Defines whether PBE accesses with the Pixel DM are trusted: 0x1 = Trusted 0x0 = Untrusted" "Untrusted,Trusted" newline bitfld.long 0x0 2. "OTHER_VERTEX_DM_TRUSTED,Defines whether other accesses with the Vertex DM are trusted: 0x1 = Trusted 0x0 = Untrusted" "Untrusted,Trusted" newline bitfld.long 0x0 1. "MCU_VERTEX_DM_TRUSTED,Defines whether MCU accesses with the Vertex DM are trusted: 0x1 = Trusted 0x0 = Untrusted" "Untrusted,Trusted" newline bitfld.long 0x0 0. "PBE_VERTEX_DM_TRUSTED,Defines whether PBE accesses with the Vertex DM are trusted: 0x1 = Trusted 0x0 = Untrusted" "Untrusted,Trusted" line.long 0x4 "RGX_CR_BIF_TRUST_1,Define Requestors/Data Masters which are Trusted/Untrusted and enable/disable the Memory Bus Security feature within the Core When enabled the GPU will emit the security signals out through the external memory interface." hexmask.long 0x4 0.--31. 1. "Reserved_17,Reserved_17" group.long 0xA100++0x7 line.long 0x0 "RGX_CR_SYS_BUS_SECURE_0,Setting this register secures the IMG Configuration Registers from the System Bus. In secure mode all registers have read access only by default. When secure mode is being set. the register must be read back to confirm that the.." hexmask.long 0x0 1.--31. 1. "Reserved_1,Reserved_1" newline bitfld.long 0x0 0. "ENABLE,

0 = No System Bus Security

1 = System Bus Restricted

" "No System Bus Security

1 = System Bus..,?" line.long 0x4 "RGX_CR_SYS_BUS_SECURE_1,Setting this register secures the IMG Configuration Registers from the System Bus. In secure mode all registers have read access only by default. When secure mode is being set. the register must be read back to confirm that the.." hexmask.long 0x4 0.--31. 1. "Reserved_1,Reserved_1" repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) group.long ($2+0xA500)++0x3 line.long 0x0 "RGX_CR_FB_CDC_V3_$1,Framebuffer constant detection configuraton registers" hexmask.long.byte 0x0 24.--31. 1. "FBC_FBDC_UV_VAL1,video pixel format constant value" newline hexmask.long.byte 0x0 16.--23. 1. "FBC_FBDC_Y_VAL1,video pixel format constant value" newline hexmask.long.byte 0x0 8.--15. 1. "FBC_FBDC_UV_VAL0,video pixel format constant value" newline hexmask.long.byte 0x0 0.--7. 1. "FBC_FBDC_Y_VAL0,video pixel format constant value" repeat.end group.long 0xA508++0x7 line.long 0x0 "RGX_CR_FBC_FBDC_CR_FILTER_0,FBCDC corrupt tile filter register" hexmask.long 0x0 5.--31. 1. "Reserved_5,Reserved_5" newline hexmask.long.byte 0x0 1.--4. 1. "CLEAR,Clear corrupt tile filter status 1 bit per requester" newline bitfld.long 0x0 0. "ENABLE,Enable corrupt tile filter" "0,1" line.long 0x4 "RGX_CR_FBC_FBDC_CR_FILTER_1,FBCDC corrupt tile filter register" hexmask.long 0x4 0.--31. 1. "Reserved_5,Reserved_5" rgroup.long 0xA510++0x7 line.long 0x0 "RGX_CR_FBC_FBDC_CR_FILTER_STATUS_0,FBCDC corrupt tile filter register" hexmask.long 0x0 4.--31. 1. "Reserved_4,Reserved_4" newline hexmask.long.byte 0x0 0.--3. 1. "FBC_FBDC_CR_FILTER_STATUS,Status of corrupt tile filter 1 bit per requester" line.long 0x4 "RGX_CR_FBC_FBDC_CR_FILTER_STATUS_1,FBCDC corrupt tile filter register" hexmask.long 0x4 0.--31. 1. "Reserved_4,Reserved_4" group.long 0xA518++0x7 line.long 0x0 "RGX_CR_FBC_FBDC_CR_MODE_V3_1_0,Enable FBC_FBDC mode V3_1 for FBC_FBDC textures" hexmask.long 0x0 1.--31. 1. "Reserved_1,Reserved_1" newline bitfld.long 0x0 0. "EN,Enable FBC_FBDC mode V3_1 for FBCDC formats defaults to V3" "0,1" line.long 0x4 "RGX_CR_FBC_FBDC_CR_MODE_V3_1_1,Enable FBC_FBDC mode V3_1 for FBC_FBDC textures" hexmask.long 0x4 0.--31. 1. "Reserved_1,Reserved_1" repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) group.long ($2+0xA520)++0x3 line.long 0x0 "RGX_CR_FBCDC_CC_$1,RGX_CR_FBCDC_CC_0" hexmask.long.byte 0x0 24.--31. 1. "CH3_VAL0,Constant colour detected value for channel 3." newline hexmask.long.byte 0x0 16.--23. 1. "CH2_VAL0,Constant colour detected value for channel 2." newline hexmask.long.byte 0x0 8.--15. 1. "CH1_VAL0,Constant colour detected value for channel 1." newline hexmask.long.byte 0x0 0.--7. 1. "CH0_VAL0,Constant colour detected value for channel 0." repeat.end repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) group.long ($2+0xA528)++0x3 line.long 0x0 "RGX_CR_FBCDC_CC_YUV_$1,RGX_CR_FBCDC_CC_YUV_0" hexmask.long.byte 0x0 26.--31. 1. "Reserved_26,Reserved_26" newline hexmask.long.word 0x0 16.--25. 1. "UV_VAL0,Constant colour detected value uv-plane." newline hexmask.long.byte 0x0 10.--15. 1. "Reserved_10,Reserved_10" newline hexmask.long.word 0x0 0.--9. 1. "Y_VAL0,Constant colour detected value y-plane." repeat.end group.long 0xB000++0x7 line.long 0x0 "RGX_CR_PIPELINE_STATS_ENABLE_0,This register globally enables per DM pipeline statistics counters. Set this register to '1' to allow pipeline statistics counters to increment. Set this register to '0' to inhibit pipeline statistics from incrementing." hexmask.long.word 0x0 17.--31. 1. "Reserved_17,Reserved_17" newline bitfld.long 0x0 16. "COMPUTE,COMPUTE" "0,1" newline hexmask.long.byte 0x0 9.--15. 1. "Reserved_9,Reserved_9" newline bitfld.long 0x0 8. "_3D,_3D" "0,1" newline hexmask.long.byte 0x0 1.--7. 1. "Reserved_1,Reserved_1" newline bitfld.long 0x0 0. "TA,TA" "0,1" line.long 0x4 "RGX_CR_PIPELINE_STATS_ENABLE_1,This register globally enables per DM pipeline statistics counters. Set this register to '1' to allow pipeline statistics counters to increment. Set this register to '0' to inhibit pipeline statistics from incrementing." hexmask.long 0x4 0.--31. 1. "Reserved_17,Reserved_17" wgroup.long 0xB008++0x7 line.long 0x0 "RGX_CR_PIPELINE_STATS_CLEAR_0,Writing '1' to fields of this register resets the pipeline statistics counters per DM The pipeline statistics should normally be cleared before each TA. 3D or Compute kick" hexmask.long.word 0x0 17.--31. 1. "Reserved_17,Reserved_17" newline bitfld.long 0x0 16. "COMPUTE,COMPUTE" "0,1" newline hexmask.long.byte 0x0 9.--15. 1. "Reserved_9,Reserved_9" newline bitfld.long 0x0 8. "_3D,_3D" "0,1" newline hexmask.long.byte 0x0 1.--7. 1. "Reserved_1,Reserved_1" newline bitfld.long 0x0 0. "TA,TA" "0,1" line.long 0x4 "RGX_CR_PIPELINE_STATS_CLEAR_1,Writing '1' to fields of this register resets the pipeline statistics counters per DM The pipeline statistics should normally be cleared before each TA. 3D or Compute kick" hexmask.long 0x4 0.--31. 1. "Reserved_17,Reserved_17" repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) rgroup.long ($2+0xB010)++0x3 line.long 0x0 "RGX_CR_PIPELINE_STATS_IA_VERTICES_$1,Number of vertices the Input Assembly stage generated (not subtracting any caching)" hexmask.long 0x0 0.--31. 1. "COUNT,COUNT" repeat.end repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) rgroup.long ($2+0xB018)++0x3 line.long 0x0 "RGX_CR_PIPELINE_STATS_IA_PRIMITIVES_$1,Number of primitives the Input Assembly stage generated" hexmask.long 0x0 0.--31. 1. "COUNT,COUNT" repeat.end repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) rgroup.long ($2+0xB020)++0x3 line.long 0x0 "RGX_CR_PIPELINE_STATS_VS_INVOCATIONS_$1,Number of times the Vertex Shader is executed" hexmask.long 0x0 0.--31. 1. "COUNT,COUNT" repeat.end repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) rgroup.long ($2+0xB038)++0x3 line.long 0x0 "RGX_CR_PIPELINE_STATS_GS_INVOCATIONS_$1,Number of times the Geometry Shader is executed" hexmask.long 0x0 0.--31. 1. "COUNT,COUNT" repeat.end repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) rgroup.long ($2+0xB040)++0x3 line.long 0x0 "RGX_CR_PIPELINE_STATS_GS_PRIMITIVES_$1,Number of primitives the Geometry Shader generated" hexmask.long 0x0 0.--31. 1. "COUNT,COUNT" repeat.end repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) rgroup.long ($2+0xB048)++0x3 line.long 0x0 "RGX_CR_PIPELINE_STATS_C_INVOCATIONS_$1,Number of times the Clipper is executed" hexmask.long 0x0 0.--31. 1. "COUNT,COUNT" repeat.end repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) rgroup.long ($2+0xB050)++0x3 line.long 0x0 "RGX_CR_PIPELINE_STATS_C_PRIMITIVES_$1,Number of primitives the Clipper generated" hexmask.long 0x0 0.--31. 1. "COUNT,COUNT" repeat.end repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) rgroup.long ($2+0xB058)++0x3 line.long 0x0 "RGX_CR_PIPELINE_STATS_PS_INVOCATIONS_$1,Number of times the Pixel Shader is executed" hexmask.long 0x0 0.--31. 1. "COUNT,COUNT" repeat.end repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) rgroup.long ($2+0xB060)++0x3 line.long 0x0 "RGX_CR_PIPELINE_STATS_CS_INVOCATIONS_$1,Number of times the Compute Shader is executed" hexmask.long 0x0 0.--31. 1. "COUNT,COUNT" repeat.end rgroup.long 0xE000++0x7 line.long 0x0 "RGX_CR_CACHE_CFI_EVENT_0,Global Flush and Invalidation Pending bits for all Texture and Data Caches in the design. The bits are set high after a Flush/Invalidate is requested and will be set low again as each cache in turn completes processing. therefore.." hexmask.long.word 0x0 16.--31. 1. "MCU_L0_PENDING,1 Indicates there is a pending global CFI operation on the specified MCU L0 cache (there can be up to 16 MCU L0 caches depending on the number of clusters)" newline hexmask.long.word 0x0 0.--15. 1. "MADD_PENDING,1 Indicates there is a pending global CFI operation on the specified MADD Texture cache (there can be up to 16 MADD caches depending on the number of clusters)" line.long 0x4 "RGX_CR_CACHE_CFI_EVENT_1,Global Flush and Invalidation Pending bits for all Texture and Data Caches in the design. The bits are set high after a Flush/Invalidate is requested and will be set low again as each cache in turn completes processing. therefore.." hexmask.long.tbyte 0x4 9.--31. 1. "Reserved_41,Reserved_41" newline bitfld.long 0x4 8. "SLC_PENDING,1 Indicates there is a pending global CFI operation on the SLC cache" "0,1" newline hexmask.long.byte 0x4 0.--7. 1. "MCU_L1_PENDING,1 Indicates there is a pending global CFI operation on the specified MCU L1 cache (there can be up to 8 MCU L1 caches depending on the number of clusters)" group.long 0xE138++0x7 line.long 0x0 "RGX_CR_MMU_CTRL_INVAL_0,MMU invalidation control registers" hexmask.long.tbyte 0x0 12.--31. 1. "Reserved_12,Reserved_12" newline bitfld.long 0x0 11. "ALL_CONTEXTS,When ALL_CONTEXTS is set all context ids get invalidated (global invalidation)" "0,1" newline hexmask.long.byte 0x0 3.--10. 1. "CONTEXT,When ALL_CONTEXTS is not set this field specifies the context id to be invalidated (per-context invalidation)" newline bitfld.long 0x0 2. "PC,Invalidates PC PD & PT" "0,1" newline bitfld.long 0x0 1. "PD,Invalidates PD & PT" "0,1" newline bitfld.long 0x0 0. "PT,Invalidates PT" "0,1" line.long 0x4 "RGX_CR_MMU_CTRL_INVAL_1,MMU invalidation control registers" hexmask.long 0x4 0.--31. 1. "Reserved_12,Reserved_12" repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) rgroup.long ($2+0xF100)++0x3 line.long 0x0 "RGX_CR_FB_CDC_PWR_NUM_$1,Power Monitoring registers for the FBCDC" hexmask.long 0x0 0.--31. 1. "FBDC,Number of accesses to the FBDC per clock" repeat.end repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) rgroup.long ($2+0xF108)++0x3 line.long 0x0 "RGX_CR_FB_CDC_PWR_NUM_MCU_$1,Power Monitoring registers for the FBCDC" hexmask.long 0x0 0.--31. 1. "FBTC,Number of accesses to the MCU FBTC per clock" repeat.end rgroup.long 0xF220++0xF line.long 0x0 "RGX_CR_BIF_BLACKPEARL_RTN_FIFO_WORD_COUNT_0,Blackpearl BIF return FIFO word count" hexmask.long.tbyte 0x0 9.--31. 1. "Reserved_9,Reserved_9" newline hexmask.long.word 0x0 0.--8. 1. "COUNTER,COUNTER" line.long 0x4 "RGX_CR_BIF_BLACKPEARL_RTN_FIFO_WORD_COUNT_1,Blackpearl BIF return FIFO word count" hexmask.long 0x4 0.--31. 1. "Reserved_9,Reserved_9" line.long 0x8 "RGX_CR_BIF_JONES_RTN_FIFO_WORD_COUNT_0,Jones BIF return FIFO word count" hexmask.long.tbyte 0x8 9.--31. 1. "Reserved_9,Reserved_9" newline hexmask.long.word 0x8 0.--8. 1. "COUNTER,COUNTER" line.long 0xC "RGX_CR_BIF_JONES_RTN_FIFO_WORD_COUNT_1,Jones BIF return FIFO word count" hexmask.long 0xC 0.--31. 1. "Reserved_9,Reserved_9" group.long 0xF258++0x7 line.long 0x0 "RGX_CR_TDM_GRIDOFFSET_0,Sample position grid offset for use when MSAA/ODAA is DISABLED DX (0.0.0.0) OpenGL (0.5.0.5) Acts as the 9th multisample position when MSAA is ENABLED." hexmask.long.tbyte 0x0 8.--31. 1. "Reserved_8,Reserved_8" newline hexmask.long.byte 0x0 4.--7. 1. "GRID_Y,Unsigned sub-pixel offset" newline hexmask.long.byte 0x0 0.--3. 1. "GRID_X,Unsigned sub-pixel offset" line.long 0x4 "RGX_CR_TDM_GRIDOFFSET_1,Sample position grid offset for use when MSAA/ODAA is DISABLED DX (0.0.0.0) OpenGL (0.5.0.5) Acts as the 9th multisample position when MSAA is ENABLED." hexmask.long 0x4 0.--31. 1. "Reserved_8,Reserved_8" repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) group.long ($2+0xF260)++0x3 line.long 0x0 "RGX_CR_TDM_MULTISAMPLECTL_$1,Sample position grid offset for use in 2x. 4x. 8xMSAA and ODAA modes." hexmask.long.byte 0x0 28.--31. 1. "MSAA_Y3,Unsigned sub-pixel offset for the 4th multisample Y position" newline hexmask.long.byte 0x0 24.--27. 1. "MSAA_X3,Unsigned sub-pixel offset for the 4th multisample X position" newline hexmask.long.byte 0x0 20.--23. 1. "MSAA_Y2,Unsigned sub-pixel offset for the 3rd multisample Y position" newline hexmask.long.byte 0x0 16.--19. 1. "MSAA_X2,Unsigned sub-pixel offset for the 3rd multisample X position" newline hexmask.long.byte 0x0 12.--15. 1. "MSAA_Y1,Unsigned sub-pixel offset for the 2nd multisample Y position" newline hexmask.long.byte 0x0 8.--11. 1. "MSAA_X1,Unsigned sub-pixel offset for the 2nd multisample X position" newline hexmask.long.byte 0x0 4.--7. 1. "MSAA_Y0,Unsigned sub-pixel offset for the 1st multisample Y position" newline hexmask.long.byte 0x0 0.--3. 1. "MSAA_X0,Unsigned sub-pixel offset for the 1st multisample X position" repeat.end group.long 0xF268++0x7 line.long 0x0 "RGX_CR_USC_CODE_BASE_2D_0,RGX_CR_USC_CODE_BASE_2D_0" hexmask.long 0x0 6.--31. 1. "ADDR,2D Data Master Code Base Register bits" newline hexmask.long.byte 0x0 0.--5. 1. "Reserved_0,Reserved_0" line.long 0x4 "RGX_CR_USC_CODE_BASE_2D_1,RGX_CR_USC_CODE_BASE_2D_1" hexmask.long.tbyte 0x4 8.--31. 1. "Reserved_40,Reserved_40" newline hexmask.long.byte 0x4 0.--7. 1. "ADDR,2D Data Master Code Base Register bits" group.long 0x10B00++0x7 line.long 0x0 "RGX_CR_MTS_SCHEDULE1_0,This register allows firmware tasks to be scheduled on the META (Garten) core." hexmask.long.tbyte 0x0 9.--31. 1. "Reserved_9,Reserved_9" newline bitfld.long 0x0 8. "HOST,Host Interrupte kick" "0,1" newline bitfld.long 0x0 6.--7. "PRIORITY,DataMaster Priority" "0,1,2,3" newline bitfld.long 0x0 5. "CONTEXT,CONTEXT" "0,1" newline bitfld.long 0x0 4. "TASK,TASK" "0,1" newline hexmask.long.byte 0x0 0.--3. 1. "DM,DataMaster Type" line.long 0x4 "RGX_CR_MTS_SCHEDULE1_1,This register allows firmware tasks to be scheduled on the META (Garten) core." hexmask.long 0x4 0.--31. 1. "Reserved_9,Reserved_9" rgroup.long 0x10B98++0x17 line.long 0x0 "RGX_CR_MTS_INTCTX1_0,This register contains the sideband data for the MTS internal interrupt context registers" bitfld.long 0x0 30.--31. "Reserved_30,Reserved_30" "0,1,2,3" newline hexmask.long.byte 0x0 22.--29. 1. "DM_HOST_SCHEDULE,A 1 bit counter per DM for host requests" newline hexmask.long.byte 0x0 16.--21. 1. "Reserved_16,Reserved_16" newline hexmask.long.byte 0x0 8.--15. 1. "DM_TIMER_SCHEDULE,A 1 bit counter per DM for timer requests" newline hexmask.long.byte 0x0 0.--7. 1. "DM_INTERRUPT_SCHEDULE,A 1 bit counter per DM for interrupt requests" line.long 0x4 "RGX_CR_MTS_INTCTX1_1,This register contains the sideband data for the MTS internal interrupt context registers" hexmask.long 0x4 0.--31. 1. "Reserved_30,Reserved_30" line.long 0x8 "RGX_CR_MTS_BGCTX1_0,This register contains the sideband data for the MTS internal background context registers" hexmask.long.tbyte 0x8 8.--31. 1. "Reserved_8,Reserved_8" newline hexmask.long.byte 0x8 0.--7. 1. "DM_NONCOUNTED_SCHEDULE,A 1 bit counter per DM for non-counted background request" line.long 0xC "RGX_CR_MTS_BGCTX1_1,This register contains the sideband data for the MTS internal background context registers" hexmask.long 0xC 0.--31. 1. "Reserved_8,Reserved_8" line.long 0x10 "RGX_CR_MTS_BGCTX_COUNTED_SCHEDULE1_0,This register contains the sideband data for the MTS internal counted background context counters" hexmask.long.byte 0x10 24.--31. 1. "DM3,A 8 bit counter for DM3" newline hexmask.long.byte 0x10 16.--23. 1. "DM2,A 8 bit counter for DM2" newline hexmask.long.byte 0x10 8.--15. 1. "DM1,A 8 bit counter for DM1" newline hexmask.long.byte 0x10 0.--7. 1. "DM0,A 8 bit counter for DM0" line.long 0x14 "RGX_CR_MTS_BGCTX_COUNTED_SCHEDULE1_1,This register contains the sideband data for the MTS internal counted background context counters" hexmask.long.word 0x14 16.--31. 1. "Reserved_48,Reserved_48" newline hexmask.long.byte 0x14 8.--15. 1. "DM5,A 8 bit counter for DM5" newline hexmask.long.byte 0x14 0.--7. 1. "DM4,A 8 bit counter for DM4" rgroup.long 0x10BD8++0x7 line.long 0x0 "RGX_CR_IRQ_OS1_EVENT_STATUS_0,This register indicates the source of a per-OS host interrupt. This register is set by the firmware and cleared by the host." hexmask.long 0x0 1.--31. 1. "Reserved_1,Reserved_1" newline bitfld.long 0x0 0. "SOURCE,SOURCE" "0,1" line.long 0x4 "RGX_CR_IRQ_OS1_EVENT_STATUS_1,This register indicates the source of a per-OS host interrupt. This register is set by the firmware and cleared by the host." hexmask.long 0x4 0.--31. 1. "Reserved_1,Reserved_1" group.long 0x10BE8++0x7 line.long 0x0 "RGX_CR_IRQ_OS1_EVENT_CLEAR_0,This register clears a per-OS host interrupt." hexmask.long 0x0 1.--31. 1. "Reserved_1,Reserved_1" newline bitfld.long 0x0 0. "SOURCE,SOURCE" "0,1" line.long 0x4 "RGX_CR_IRQ_OS1_EVENT_CLEAR_1,This register clears a per-OS host interrupt." hexmask.long 0x4 0.--31. 1. "Reserved_1,Reserved_1" group.long 0x20B00++0x7 line.long 0x0 "RGX_CR_MTS_SCHEDULE2_0,This register allows firmware tasks to be scheduled on the META (Garten) core." hexmask.long.tbyte 0x0 9.--31. 1. "Reserved_9,Reserved_9" newline bitfld.long 0x0 8. "HOST,Host Interrupte kick" "0,1" newline bitfld.long 0x0 6.--7. "PRIORITY,DataMaster Priority" "0,1,2,3" newline bitfld.long 0x0 5. "CONTEXT,CONTEXT" "0,1" newline bitfld.long 0x0 4. "TASK,TASK" "0,1" newline hexmask.long.byte 0x0 0.--3. 1. "DM,DataMaster Type" line.long 0x4 "RGX_CR_MTS_SCHEDULE2_1,This register allows firmware tasks to be scheduled on the META (Garten) core." hexmask.long 0x4 0.--31. 1. "Reserved_9,Reserved_9" rgroup.long 0x20B98++0x17 line.long 0x0 "RGX_CR_MTS_INTCTX2_0,This register contains the sideband data for the MTS internal interrupt context registers" bitfld.long 0x0 30.--31. "Reserved_30,Reserved_30" "0,1,2,3" newline hexmask.long.byte 0x0 22.--29. 1. "DM_HOST_SCHEDULE,A 1 bit counter per DM for host requests" newline hexmask.long.byte 0x0 16.--21. 1. "Reserved_16,Reserved_16" newline hexmask.long.byte 0x0 8.--15. 1. "DM_TIMER_SCHEDULE,A 1 bit counter per DM for timer requests" newline hexmask.long.byte 0x0 0.--7. 1. "DM_INTERRUPT_SCHEDULE,A 1 bit counter per DM for interrupt requests" line.long 0x4 "RGX_CR_MTS_INTCTX2_1,This register contains the sideband data for the MTS internal interrupt context registers" hexmask.long 0x4 0.--31. 1. "Reserved_30,Reserved_30" line.long 0x8 "RGX_CR_MTS_BGCTX2_0,This register contains the sideband data for the MTS internal background context registers" hexmask.long.tbyte 0x8 8.--31. 1. "Reserved_8,Reserved_8" newline hexmask.long.byte 0x8 0.--7. 1. "DM_NONCOUNTED_SCHEDULE,A 1 bit counter per DM for non-counted background request" line.long 0xC "RGX_CR_MTS_BGCTX2_1,This register contains the sideband data for the MTS internal background context registers" hexmask.long 0xC 0.--31. 1. "Reserved_8,Reserved_8" line.long 0x10 "RGX_CR_MTS_BGCTX_COUNTED_SCHEDULE2_0,This register contains the sideband data for the MTS internal counted background context counters" hexmask.long.byte 0x10 24.--31. 1. "DM3,A 8 bit counter for DM3" newline hexmask.long.byte 0x10 16.--23. 1. "DM2,A 8 bit counter for DM2" newline hexmask.long.byte 0x10 8.--15. 1. "DM1,A 8 bit counter for DM1" newline hexmask.long.byte 0x10 0.--7. 1. "DM0,A 8 bit counter for DM0" line.long 0x14 "RGX_CR_MTS_BGCTX_COUNTED_SCHEDULE2_1,This register contains the sideband data for the MTS internal counted background context counters" hexmask.long.word 0x14 16.--31. 1. "Reserved_48,Reserved_48" newline hexmask.long.byte 0x14 8.--15. 1. "DM5,A 8 bit counter for DM5" newline hexmask.long.byte 0x14 0.--7. 1. "DM4,A 8 bit counter for DM4" rgroup.long 0x20BD8++0x7 line.long 0x0 "RGX_CR_IRQ_OS2_EVENT_STATUS_0,This register indicates the source of a per-OS host interrupt. This register is set by the firmware and cleared by the host." hexmask.long 0x0 1.--31. 1. "Reserved_1,Reserved_1" newline bitfld.long 0x0 0. "SOURCE,SOURCE" "0,1" line.long 0x4 "RGX_CR_IRQ_OS2_EVENT_STATUS_1,This register indicates the source of a per-OS host interrupt. This register is set by the firmware and cleared by the host." hexmask.long 0x4 0.--31. 1. "Reserved_1,Reserved_1" group.long 0x20BE8++0x7 line.long 0x0 "RGX_CR_IRQ_OS2_EVENT_CLEAR_0,This register clears a per-OS host interrupt." hexmask.long 0x0 1.--31. 1. "Reserved_1,Reserved_1" newline bitfld.long 0x0 0. "SOURCE,SOURCE" "0,1" line.long 0x4 "RGX_CR_IRQ_OS2_EVENT_CLEAR_1,This register clears a per-OS host interrupt." hexmask.long 0x4 0.--31. 1. "Reserved_1,Reserved_1" group.long 0x30B00++0x7 line.long 0x0 "RGX_CR_MTS_SCHEDULE3_0,This register allows firmware tasks to be scheduled on the META (Garten) core." hexmask.long.tbyte 0x0 9.--31. 1. "Reserved_9,Reserved_9" newline bitfld.long 0x0 8. "HOST,Host Interrupte kick" "0,1" newline bitfld.long 0x0 6.--7. "PRIORITY,DataMaster Priority" "0,1,2,3" newline bitfld.long 0x0 5. "CONTEXT,CONTEXT" "0,1" newline bitfld.long 0x0 4. "TASK,TASK" "0,1" newline hexmask.long.byte 0x0 0.--3. 1. "DM,DataMaster Type" line.long 0x4 "RGX_CR_MTS_SCHEDULE3_1,This register allows firmware tasks to be scheduled on the META (Garten) core." hexmask.long 0x4 0.--31. 1. "Reserved_9,Reserved_9" rgroup.long 0x30B98++0x17 line.long 0x0 "RGX_CR_MTS_INTCTX3_0,This register contains the sideband data for the MTS internal interrupt context registers" bitfld.long 0x0 30.--31. "Reserved_30,Reserved_30" "0,1,2,3" newline hexmask.long.byte 0x0 22.--29. 1. "DM_HOST_SCHEDULE,A 1 bit counter per DM for host requests" newline hexmask.long.byte 0x0 16.--21. 1. "Reserved_16,Reserved_16" newline hexmask.long.byte 0x0 8.--15. 1. "DM_TIMER_SCHEDULE,A 1 bit counter per DM for timer requests" newline hexmask.long.byte 0x0 0.--7. 1. "DM_INTERRUPT_SCHEDULE,A 1 bit counter per DM for interrupt requests" line.long 0x4 "RGX_CR_MTS_INTCTX3_1,This register contains the sideband data for the MTS internal interrupt context registers" hexmask.long 0x4 0.--31. 1. "Reserved_30,Reserved_30" line.long 0x8 "RGX_CR_MTS_BGCTX3_0,This register contains the sideband data for the MTS internal background context registers" hexmask.long.tbyte 0x8 8.--31. 1. "Reserved_8,Reserved_8" newline hexmask.long.byte 0x8 0.--7. 1. "DM_NONCOUNTED_SCHEDULE,A 1 bit counter per DM for non-counted background request" line.long 0xC "RGX_CR_MTS_BGCTX3_1,This register contains the sideband data for the MTS internal background context registers" hexmask.long 0xC 0.--31. 1. "Reserved_8,Reserved_8" line.long 0x10 "RGX_CR_MTS_BGCTX_COUNTED_SCHEDULE3_0,This register contains the sideband data for the MTS internal counted background context counters" hexmask.long.byte 0x10 24.--31. 1. "DM3,A 8 bit counter for DM3" newline hexmask.long.byte 0x10 16.--23. 1. "DM2,A 8 bit counter for DM2" newline hexmask.long.byte 0x10 8.--15. 1. "DM1,A 8 bit counter for DM1" newline hexmask.long.byte 0x10 0.--7. 1. "DM0,A 8 bit counter for DM0" line.long 0x14 "RGX_CR_MTS_BGCTX_COUNTED_SCHEDULE3_1,This register contains the sideband data for the MTS internal counted background context counters" hexmask.long.word 0x14 16.--31. 1. "Reserved_48,Reserved_48" newline hexmask.long.byte 0x14 8.--15. 1. "DM5,A 8 bit counter for DM5" newline hexmask.long.byte 0x14 0.--7. 1. "DM4,A 8 bit counter for DM4" rgroup.long 0x30BD8++0x7 line.long 0x0 "RGX_CR_IRQ_OS3_EVENT_STATUS_0,This register indicates the source of a per-OS host interrupt. This register is set by the firmware and cleared by the host." hexmask.long 0x0 1.--31. 1. "Reserved_1,Reserved_1" newline bitfld.long 0x0 0. "SOURCE,SOURCE" "0,1" line.long 0x4 "RGX_CR_IRQ_OS3_EVENT_STATUS_1,This register indicates the source of a per-OS host interrupt. This register is set by the firmware and cleared by the host." hexmask.long 0x4 0.--31. 1. "Reserved_1,Reserved_1" group.long 0x30BE8++0x7 line.long 0x0 "RGX_CR_IRQ_OS3_EVENT_CLEAR_0,This register clears a per-OS host interrupt." hexmask.long 0x0 1.--31. 1. "Reserved_1,Reserved_1" newline bitfld.long 0x0 0. "SOURCE,SOURCE" "0,1" line.long 0x4 "RGX_CR_IRQ_OS3_EVENT_CLEAR_1,This register clears a per-OS host interrupt." hexmask.long 0x4 0.--31. 1. "Reserved_1,Reserved_1" group.long 0x40B00++0x7 line.long 0x0 "RGX_CR_MTS_SCHEDULE4_0,This register allows firmware tasks to be scheduled on the META (Garten) core." hexmask.long.tbyte 0x0 9.--31. 1. "Reserved_9,Reserved_9" newline bitfld.long 0x0 8. "HOST,Host Interrupte kick" "0,1" newline bitfld.long 0x0 6.--7. "PRIORITY,DataMaster Priority" "0,1,2,3" newline bitfld.long 0x0 5. "CONTEXT,CONTEXT" "0,1" newline bitfld.long 0x0 4. "TASK,TASK" "0,1" newline hexmask.long.byte 0x0 0.--3. 1. "DM,DataMaster Type" line.long 0x4 "RGX_CR_MTS_SCHEDULE4_1,This register allows firmware tasks to be scheduled on the META (Garten) core." hexmask.long 0x4 0.--31. 1. "Reserved_9,Reserved_9" rgroup.long 0x40B98++0x17 line.long 0x0 "RGX_CR_MTS_INTCTX4_0,This register contains the sideband data for the MTS internal interrupt context registers" bitfld.long 0x0 30.--31. "Reserved_30,Reserved_30" "0,1,2,3" newline hexmask.long.byte 0x0 22.--29. 1. "DM_HOST_SCHEDULE,A 1 bit counter per DM for host requests" newline hexmask.long.byte 0x0 16.--21. 1. "Reserved_16,Reserved_16" newline hexmask.long.byte 0x0 8.--15. 1. "DM_TIMER_SCHEDULE,A 1 bit counter per DM for timer requests" newline hexmask.long.byte 0x0 0.--7. 1. "DM_INTERRUPT_SCHEDULE,A 1 bit counter per DM for interrupt requests" line.long 0x4 "RGX_CR_MTS_INTCTX4_1,This register contains the sideband data for the MTS internal interrupt context registers" hexmask.long 0x4 0.--31. 1. "Reserved_30,Reserved_30" line.long 0x8 "RGX_CR_MTS_BGCTX4_0,This register contains the sideband data for the MTS internal background context registers" hexmask.long.tbyte 0x8 8.--31. 1. "Reserved_8,Reserved_8" newline hexmask.long.byte 0x8 0.--7. 1. "DM_NONCOUNTED_SCHEDULE,A 1 bit counter per DM for non-counted background request" line.long 0xC "RGX_CR_MTS_BGCTX4_1,This register contains the sideband data for the MTS internal background context registers" hexmask.long 0xC 0.--31. 1. "Reserved_8,Reserved_8" line.long 0x10 "RGX_CR_MTS_BGCTX_COUNTED_SCHEDULE4_0,This register contains the sideband data for the MTS internal counted background context counters" hexmask.long.byte 0x10 24.--31. 1. "DM3,A 8 bit counter for DM3" newline hexmask.long.byte 0x10 16.--23. 1. "DM2,A 8 bit counter for DM2" newline hexmask.long.byte 0x10 8.--15. 1. "DM1,A 8 bit counter for DM1" newline hexmask.long.byte 0x10 0.--7. 1. "DM0,A 8 bit counter for DM0" line.long 0x14 "RGX_CR_MTS_BGCTX_COUNTED_SCHEDULE4_1,This register contains the sideband data for the MTS internal counted background context counters" hexmask.long.word 0x14 16.--31. 1. "Reserved_48,Reserved_48" newline hexmask.long.byte 0x14 8.--15. 1. "DM5,A 8 bit counter for DM5" newline hexmask.long.byte 0x14 0.--7. 1. "DM4,A 8 bit counter for DM4" rgroup.long 0x40BD8++0x7 line.long 0x0 "RGX_CR_IRQ_OS4_EVENT_STATUS_0,This register indicates the source of a per-OS host interrupt. This register is set by the firmware and cleared by the host." hexmask.long 0x0 1.--31. 1. "Reserved_1,Reserved_1" newline bitfld.long 0x0 0. "SOURCE,SOURCE" "0,1" line.long 0x4 "RGX_CR_IRQ_OS4_EVENT_STATUS_1,This register indicates the source of a per-OS host interrupt. This register is set by the firmware and cleared by the host." hexmask.long 0x4 0.--31. 1. "Reserved_1,Reserved_1" group.long 0x40BE8++0x7 line.long 0x0 "RGX_CR_IRQ_OS4_EVENT_CLEAR_0,This register clears a per-OS host interrupt." hexmask.long 0x0 1.--31. 1. "Reserved_1,Reserved_1" newline bitfld.long 0x0 0. "SOURCE,SOURCE" "0,1" line.long 0x4 "RGX_CR_IRQ_OS4_EVENT_CLEAR_1,This register clears a per-OS host interrupt." hexmask.long 0x4 0.--31. 1. "Reserved_1,Reserved_1" group.long 0x50B00++0x7 line.long 0x0 "RGX_CR_MTS_SCHEDULE5_0,This register allows firmware tasks to be scheduled on the META (Garten) core." hexmask.long.tbyte 0x0 9.--31. 1. "Reserved_9,Reserved_9" newline bitfld.long 0x0 8. "HOST,Host Interrupte kick" "0,1" newline bitfld.long 0x0 6.--7. "PRIORITY,DataMaster Priority" "0,1,2,3" newline bitfld.long 0x0 5. "CONTEXT,CONTEXT" "0,1" newline bitfld.long 0x0 4. "TASK,TASK" "0,1" newline hexmask.long.byte 0x0 0.--3. 1. "DM,DataMaster Type" line.long 0x4 "RGX_CR_MTS_SCHEDULE5_1,This register allows firmware tasks to be scheduled on the META (Garten) core." hexmask.long 0x4 0.--31. 1. "Reserved_9,Reserved_9" rgroup.long 0x50B98++0x17 line.long 0x0 "RGX_CR_MTS_INTCTX5_0,This register contains the sideband data for the MTS internal interrupt context registers" bitfld.long 0x0 30.--31. "Reserved_30,Reserved_30" "0,1,2,3" newline hexmask.long.byte 0x0 22.--29. 1. "DM_HOST_SCHEDULE,A 1 bit counter per DM for host requests" newline hexmask.long.byte 0x0 16.--21. 1. "Reserved_16,Reserved_16" newline hexmask.long.byte 0x0 8.--15. 1. "DM_TIMER_SCHEDULE,A 1 bit counter per DM for timer requests" newline hexmask.long.byte 0x0 0.--7. 1. "DM_INTERRUPT_SCHEDULE,A 1 bit counter per DM for interrupt requests" line.long 0x4 "RGX_CR_MTS_INTCTX5_1,This register contains the sideband data for the MTS internal interrupt context registers" hexmask.long 0x4 0.--31. 1. "Reserved_30,Reserved_30" line.long 0x8 "RGX_CR_MTS_BGCTX5_0,This register contains the sideband data for the MTS internal background context registers" hexmask.long.tbyte 0x8 8.--31. 1. "Reserved_8,Reserved_8" newline hexmask.long.byte 0x8 0.--7. 1. "DM_NONCOUNTED_SCHEDULE,A 1 bit counter per DM for non-counted background request" line.long 0xC "RGX_CR_MTS_BGCTX5_1,This register contains the sideband data for the MTS internal background context registers" hexmask.long 0xC 0.--31. 1. "Reserved_8,Reserved_8" line.long 0x10 "RGX_CR_MTS_BGCTX_COUNTED_SCHEDULE5_0,This register contains the sideband data for the MTS internal counted background context counters" hexmask.long.byte 0x10 24.--31. 1. "DM3,A 8 bit counter for DM3" newline hexmask.long.byte 0x10 16.--23. 1. "DM2,A 8 bit counter for DM2" newline hexmask.long.byte 0x10 8.--15. 1. "DM1,A 8 bit counter for DM1" newline hexmask.long.byte 0x10 0.--7. 1. "DM0,A 8 bit counter for DM0" line.long 0x14 "RGX_CR_MTS_BGCTX_COUNTED_SCHEDULE5_1,This register contains the sideband data for the MTS internal counted background context counters" hexmask.long.word 0x14 16.--31. 1. "Reserved_48,Reserved_48" newline hexmask.long.byte 0x14 8.--15. 1. "DM5,A 8 bit counter for DM5" newline hexmask.long.byte 0x14 0.--7. 1. "DM4,A 8 bit counter for DM4" rgroup.long 0x50BD8++0x7 line.long 0x0 "RGX_CR_IRQ_OS5_EVENT_STATUS_0,This register indicates the source of a per-OS host interrupt. This register is set by the firmware and cleared by the host." hexmask.long 0x0 1.--31. 1. "Reserved_1,Reserved_1" newline bitfld.long 0x0 0. "SOURCE,SOURCE" "0,1" line.long 0x4 "RGX_CR_IRQ_OS5_EVENT_STATUS_1,This register indicates the source of a per-OS host interrupt. This register is set by the firmware and cleared by the host." hexmask.long 0x4 0.--31. 1. "Reserved_1,Reserved_1" group.long 0x50BE8++0x7 line.long 0x0 "RGX_CR_IRQ_OS5_EVENT_CLEAR_0,This register clears a per-OS host interrupt." hexmask.long 0x0 1.--31. 1. "Reserved_1,Reserved_1" newline bitfld.long 0x0 0. "SOURCE,SOURCE" "0,1" line.long 0x4 "RGX_CR_IRQ_OS5_EVENT_CLEAR_1,This register clears a per-OS host interrupt." hexmask.long 0x4 0.--31. 1. "Reserved_1,Reserved_1" group.long 0x60B00++0x7 line.long 0x0 "RGX_CR_MTS_SCHEDULE6_0,This register allows firmware tasks to be scheduled on the META (Garten) core." hexmask.long.tbyte 0x0 9.--31. 1. "Reserved_9,Reserved_9" newline bitfld.long 0x0 8. "HOST,Host Interrupte kick" "0,1" newline bitfld.long 0x0 6.--7. "PRIORITY,DataMaster Priority" "0,1,2,3" newline bitfld.long 0x0 5. "CONTEXT,CONTEXT" "0,1" newline bitfld.long 0x0 4. "TASK,TASK" "0,1" newline hexmask.long.byte 0x0 0.--3. 1. "DM,DataMaster Type" line.long 0x4 "RGX_CR_MTS_SCHEDULE6_1,This register allows firmware tasks to be scheduled on the META (Garten) core." hexmask.long 0x4 0.--31. 1. "Reserved_9,Reserved_9" rgroup.long 0x60B98++0x17 line.long 0x0 "RGX_CR_MTS_INTCTX6_0,This register contains the sideband data for the MTS internal interrupt context registers" bitfld.long 0x0 30.--31. "Reserved_30,Reserved_30" "0,1,2,3" newline hexmask.long.byte 0x0 22.--29. 1. "DM_HOST_SCHEDULE,A 1 bit counter per DM for host requests" newline hexmask.long.byte 0x0 16.--21. 1. "Reserved_16,Reserved_16" newline hexmask.long.byte 0x0 8.--15. 1. "DM_TIMER_SCHEDULE,A 1 bit counter per DM for timer requests" newline hexmask.long.byte 0x0 0.--7. 1. "DM_INTERRUPT_SCHEDULE,A 1 bit counter per DM for interrupt requests" line.long 0x4 "RGX_CR_MTS_INTCTX6_1,This register contains the sideband data for the MTS internal interrupt context registers" hexmask.long 0x4 0.--31. 1. "Reserved_30,Reserved_30" line.long 0x8 "RGX_CR_MTS_BGCTX6_0,This register contains the sideband data for the MTS internal background context registers" hexmask.long.tbyte 0x8 8.--31. 1. "Reserved_8,Reserved_8" newline hexmask.long.byte 0x8 0.--7. 1. "DM_NONCOUNTED_SCHEDULE,A 1 bit counter per DM for non-counted background request" line.long 0xC "RGX_CR_MTS_BGCTX6_1,This register contains the sideband data for the MTS internal background context registers" hexmask.long 0xC 0.--31. 1. "Reserved_8,Reserved_8" line.long 0x10 "RGX_CR_MTS_BGCTX_COUNTED_SCHEDULE6_0,This register contains the sideband data for the MTS internal counted background context counters" hexmask.long.byte 0x10 24.--31. 1. "DM3,A 8 bit counter for DM3" newline hexmask.long.byte 0x10 16.--23. 1. "DM2,A 8 bit counter for DM2" newline hexmask.long.byte 0x10 8.--15. 1. "DM1,A 8 bit counter for DM1" newline hexmask.long.byte 0x10 0.--7. 1. "DM0,A 8 bit counter for DM0" line.long 0x14 "RGX_CR_MTS_BGCTX_COUNTED_SCHEDULE6_1,This register contains the sideband data for the MTS internal counted background context counters" hexmask.long.word 0x14 16.--31. 1. "Reserved_48,Reserved_48" newline hexmask.long.byte 0x14 8.--15. 1. "DM5,A 8 bit counter for DM5" newline hexmask.long.byte 0x14 0.--7. 1. "DM4,A 8 bit counter for DM4" rgroup.long 0x60BD8++0x7 line.long 0x0 "RGX_CR_IRQ_OS6_EVENT_STATUS_0,This register indicates the source of a per-OS host interrupt. This register is set by the firmware and cleared by the host." hexmask.long 0x0 1.--31. 1. "Reserved_1,Reserved_1" newline bitfld.long 0x0 0. "SOURCE,SOURCE" "0,1" line.long 0x4 "RGX_CR_IRQ_OS6_EVENT_STATUS_1,This register indicates the source of a per-OS host interrupt. This register is set by the firmware and cleared by the host." hexmask.long 0x4 0.--31. 1. "Reserved_1,Reserved_1" group.long 0x60BE8++0x7 line.long 0x0 "RGX_CR_IRQ_OS6_EVENT_CLEAR_0,This register clears a per-OS host interrupt." hexmask.long 0x0 1.--31. 1. "Reserved_1,Reserved_1" newline bitfld.long 0x0 0. "SOURCE,SOURCE" "0,1" line.long 0x4 "RGX_CR_IRQ_OS6_EVENT_CLEAR_1,This register clears a per-OS host interrupt." hexmask.long 0x4 0.--31. 1. "Reserved_1,Reserved_1" group.long 0x70B00++0x7 line.long 0x0 "RGX_CR_MTS_SCHEDULE7_0,This register allows firmware tasks to be scheduled on the META (Garten) core." hexmask.long.tbyte 0x0 9.--31. 1. "Reserved_9,Reserved_9" newline bitfld.long 0x0 8. "HOST,Host Interrupte kick" "0,1" newline bitfld.long 0x0 6.--7. "PRIORITY,DataMaster Priority" "0,1,2,3" newline bitfld.long 0x0 5. "CONTEXT,CONTEXT" "0,1" newline bitfld.long 0x0 4. "TASK,TASK" "0,1" newline hexmask.long.byte 0x0 0.--3. 1. "DM,DataMaster Type" line.long 0x4 "RGX_CR_MTS_SCHEDULE7_1,This register allows firmware tasks to be scheduled on the META (Garten) core." hexmask.long 0x4 0.--31. 1. "Reserved_9,Reserved_9" rgroup.long 0x70B98++0x17 line.long 0x0 "RGX_CR_MTS_INTCTX7_0,This register contains the sideband data for the MTS internal interrupt context registers" bitfld.long 0x0 30.--31. "Reserved_30,Reserved_30" "0,1,2,3" newline hexmask.long.byte 0x0 22.--29. 1. "DM_HOST_SCHEDULE,A 1 bit counter per DM for host requests" newline hexmask.long.byte 0x0 16.--21. 1. "Reserved_16,Reserved_16" newline hexmask.long.byte 0x0 8.--15. 1. "DM_TIMER_SCHEDULE,A 1 bit counter per DM for timer requests" newline hexmask.long.byte 0x0 0.--7. 1. "DM_INTERRUPT_SCHEDULE,A 1 bit counter per DM for interrupt requests" line.long 0x4 "RGX_CR_MTS_INTCTX7_1,This register contains the sideband data for the MTS internal interrupt context registers" hexmask.long 0x4 0.--31. 1. "Reserved_30,Reserved_30" line.long 0x8 "RGX_CR_MTS_BGCTX7_0,This register contains the sideband data for the MTS internal background context registers" hexmask.long.tbyte 0x8 8.--31. 1. "Reserved_8,Reserved_8" newline hexmask.long.byte 0x8 0.--7. 1. "DM_NONCOUNTED_SCHEDULE,A 1 bit counter per DM for non-counted background request" line.long 0xC "RGX_CR_MTS_BGCTX7_1,This register contains the sideband data for the MTS internal background context registers" hexmask.long 0xC 0.--31. 1. "Reserved_8,Reserved_8" line.long 0x10 "RGX_CR_MTS_BGCTX_COUNTED_SCHEDULE7_0,This register contains the sideband data for the MTS internal counted background context counters" hexmask.long.byte 0x10 24.--31. 1. "DM3,A 8 bit counter for DM3" newline hexmask.long.byte 0x10 16.--23. 1. "DM2,A 8 bit counter for DM2" newline hexmask.long.byte 0x10 8.--15. 1. "DM1,A 8 bit counter for DM1" newline hexmask.long.byte 0x10 0.--7. 1. "DM0,A 8 bit counter for DM0" line.long 0x14 "RGX_CR_MTS_BGCTX_COUNTED_SCHEDULE7_1,This register contains the sideband data for the MTS internal counted background context counters" hexmask.long.word 0x14 16.--31. 1. "Reserved_48,Reserved_48" newline hexmask.long.byte 0x14 8.--15. 1. "DM5,A 8 bit counter for DM5" newline hexmask.long.byte 0x14 0.--7. 1. "DM4,A 8 bit counter for DM4" rgroup.long 0x70BD8++0x7 line.long 0x0 "RGX_CR_IRQ_OS7_EVENT_STATUS_0,This register indicates the source of a per-OS host interrupt. This register is set by the firmware and cleared by the host." hexmask.long 0x0 1.--31. 1. "Reserved_1,Reserved_1" newline bitfld.long 0x0 0. "SOURCE,SOURCE" "0,1" line.long 0x4 "RGX_CR_IRQ_OS7_EVENT_STATUS_1,This register indicates the source of a per-OS host interrupt. This register is set by the firmware and cleared by the host." hexmask.long 0x4 0.--31. 1. "Reserved_1,Reserved_1" group.long 0x70BE8++0x7 line.long 0x0 "RGX_CR_IRQ_OS7_EVENT_CLEAR_0,This register clears a per-OS host interrupt." hexmask.long 0x0 1.--31. 1. "Reserved_1,Reserved_1" newline bitfld.long 0x0 0. "SOURCE,SOURCE" "0,1" line.long 0x4 "RGX_CR_IRQ_OS7_EVENT_CLEAR_1,This register clears a per-OS host interrupt." hexmask.long 0x4 0.--31. 1. "Reserved_1,Reserved_1" tree.end tree "GPU2" base ad:0x34E00000 group.long 0x0++0x7 line.long 0x0 "RGX_CR_CLK_CTRL_0,Core Module Clock Control Modes. Allows individual domain clocks to be forced off. forced on or operate under automatic pipeline activity based clock gating. This register is generally controlled by the GPU firmware and should be set to.." bitfld.long 0x0 30.--31. "Reserved_30,Reserved_30" "0,1,2,3" newline bitfld.long 0x0 28.--29. "TPU_MCU_DEMUX,TPU_MCU_DEMUX" "0,1,2,3" newline bitfld.long 0x0 26.--27. "MCU_L0,MCU_L0" "0,1,2,3" newline bitfld.long 0x0 24.--25. "TPU,TPU" "0,1,2,3" newline bitfld.long 0x0 22.--23. "Reserved_22,Reserved_22" "0,1,2,3" newline bitfld.long 0x0 20.--21. "USC,USC" "0,1,2,3" newline bitfld.long 0x0 18.--19. "Reserved_18,Reserved_18" "0,1,2,3" newline bitfld.long 0x0 16.--17. "SLC,SLC" "0,1,2,3" newline bitfld.long 0x0 14.--15. "UVS,UVS" "0,1,2,3" newline bitfld.long 0x0 12.--13. "PDS,PDS" "0,1,2,3" newline bitfld.long 0x0 10.--11. "VDM,VDM" "0,1,2,3" newline bitfld.long 0x0 8.--9. "PM,PM" "0,1,2,3" newline bitfld.long 0x0 6.--7. "GPP,GPP" "0,1,2,3" newline bitfld.long 0x0 4.--5. "TE,TE" "0,1,2,3" newline bitfld.long 0x0 2.--3. "TSP,TSP" "0,1,2,3" newline bitfld.long 0x0 0.--1. "ISP,ISP" "0,1,2,3" line.long 0x4 "RGX_CR_CLK_CTRL_1,Core Module Clock Control Modes. Allows individual domain clocks to be forced off. forced on or operate under automatic pipeline activity based clock gating. This register is generally controlled by the GPU firmware and should be set to.." hexmask.long.byte 0x4 28.--31. 1. "Reserved_60,Reserved_60" newline bitfld.long 0x4 26.--27. "FBC,FBC" "0,1,2,3" newline bitfld.long 0x4 24.--25. "FBDC,FBDC" "0,1,2,3" newline bitfld.long 0x4 22.--23. "FB_TLCACHE,FB_TLCACHE" "0,1,2,3" newline bitfld.long 0x4 20.--21. "USCS,USCS" "0,1,2,3" newline bitfld.long 0x4 18.--19. "PBE,PBE" "0,1,2,3" newline bitfld.long 0x4 16.--17. "MCU_L1,MCU_L1" "0,1,2,3" newline bitfld.long 0x4 14.--15. "CDM,CDM" "0,1,2,3" newline bitfld.long 0x4 12.--13. "SIDEKICK,SIDEKICK" "0,1,2,3" newline bitfld.long 0x4 10.--11. "BIF_SIDEKICK,BIF_SIDEKICK" "0,1,2,3" newline bitfld.long 0x4 8.--9. "BIF,BIF" "0,1,2,3" newline hexmask.long.byte 0x4 0.--7. 1. "Reserved_30,Reserved_30" rgroup.long 0x8++0x7 line.long 0x0 "RGX_CR_CLK_STATUS_0,Reports the current module clock status Clock gating state reflects the condition of the clock for each module" bitfld.long 0x0 30.--31. "Reserved_30,Reserved_30" "0,1,2,3" newline bitfld.long 0x0 29. "FBC,FBC" "0,1" newline bitfld.long 0x0 28. "FBDC,FBDC" "0,1" newline bitfld.long 0x0 27. "FB_TLCACHE,FB_TLCACHE" "0,1" newline bitfld.long 0x0 26. "USCS,USCS" "0,1" newline bitfld.long 0x0 25. "PBE,PBE" "0,1" newline bitfld.long 0x0 24. "MCU_L1,MCU_L1" "0,1" newline bitfld.long 0x0 23. "CDM,CDM" "0,1" newline bitfld.long 0x0 22. "SIDEKICK,SIDEKICK" "0,1" newline bitfld.long 0x0 21. "BIF_SIDEKICK,BIF_SIDEKICK" "0,1" newline bitfld.long 0x0 20. "BIF,BIF" "0,1" newline hexmask.long.byte 0x0 15.--19. 1. "Reserved_15,Reserved_15" newline bitfld.long 0x0 14. "TPU_MCU_DEMUX,TPU_MCU_DEMUX" "0,1" newline bitfld.long 0x0 13. "MCU_L0,MCU_L0" "0,1" newline bitfld.long 0x0 12. "TPU,TPU" "0,1" newline bitfld.long 0x0 11. "Reserved_11,Reserved_11" "0,1" newline bitfld.long 0x0 10. "USC,USC" "0,1" newline bitfld.long 0x0 9. "Reserved_9,Reserved_9" "0,1" newline bitfld.long 0x0 8. "SLC,SLC" "0,1" newline bitfld.long 0x0 7. "UVS,UVS" "0,1" newline bitfld.long 0x0 6. "PDS,PDS" "0,1" newline bitfld.long 0x0 5. "VDM,VDM" "0,1" newline bitfld.long 0x0 4. "PM,PM" "0,1" newline bitfld.long 0x0 3. "GPP,GPP" "0,1" newline bitfld.long 0x0 2. "TE,TE" "0,1" newline bitfld.long 0x0 1. "TSP,TSP" "0,1" newline bitfld.long 0x0 0. "ISP,ISP" "0,1" line.long 0x4 "RGX_CR_CLK_STATUS_1,Reports the current module clock status Clock gating state reflects the condition of the clock for each module" hexmask.long 0x4 1.--31. 1. "Reserved_33,Reserved_33" newline bitfld.long 0x4 0. "MCU_FBTC,MCU_FBTC" "0,1" rgroup.long 0x18++0x7 line.long 0x0 "RGX_CR_PRODUCT_ID_0,Reports the product ID Product ID Register" hexmask.long.word 0x0 16.--31. 1. "IMG_PRODUCT_ID,IMG Product ID" newline hexmask.long.word 0x0 0.--15. 1. "Reserved_0,Reserved_0" line.long 0x4 "RGX_CR_PRODUCT_ID_1,Reports the product ID Product ID Register" hexmask.long 0x4 0.--31. 1. "Reserved_32,Reserved_32" repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) rgroup.long ($2+0x20)++0x3 line.long 0x0 "RGX_CR_CORE_ID_$1,Reports the product ID Core ID Register" hexmask.long.word 0x0 16.--31. 1. "NUMBER_OF_SCALABLE_UNITS,N - Number of scalable Units" newline hexmask.long.word 0x0 0.--15. 1. "CONFIG_ID,C - Config ID" repeat.end repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) rgroup.long ($2+0x28)++0x3 line.long 0x0 "RGX_CR_CORE_IP_INTEGRATOR_ID_$1,Reports the product ID Core IP Integrator ID Register" hexmask.long 0x0 0.--31. 1. "VALUE,IP company ID/Designer" repeat.end repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) rgroup.long ($2+0x30)++0x3 line.long 0x0 "RGX_CR_CORE_IP_CHANGELIST_$1,Reports the version control ID Core IP Changelist Register" hexmask.long 0x0 0.--31. 1. "VALUE,Version control ID" repeat.end group.long 0x38++0x7 line.long 0x0 "RGX_CR_POWER_EVENT_0,Allows the firmware to request a power-up or power-down operation to an external (to Rogue) power-management controller When the power event operation is accepted. the firmware will either receive an.." hexmask.long.byte 0x0 24.--31. 1. "Reserved_24,Reserved_24" newline hexmask.long.word 0x0 8.--23. 1. "DOMAIN,sets which power island is enabled for the current power event request; bit0:jones bit1-8:dusts bit9-12:blackpearls" newline hexmask.long.byte 0x0 2.--7. 1. "Reserved_2,Reserved_2" newline bitfld.long 0x0 1. "REQ,Set when a power event operation is requested" "0,1" newline bitfld.long 0x0 0. "TYPE,The requested power event operation" "0,1" line.long 0x4 "RGX_CR_POWER_EVENT_1,Allows the firmware to request a power-up or power-down operation to an external (to Rogue) power-management controller When the power event operation is accepted. the firmware will either receive an.." hexmask.long 0x4 0.--31. 1. "Reserved_24,Reserved_24" group.long 0x50++0x7 line.long 0x0 "RGX_CR_DUSTS_ENABLE_0,Controls how many Dual Unified Shading and Texturing Units (DUSTs) are enabled. Each DUST Contain 2 USCs and a TPU module. (Available on 2. X.X.X cores and above). Only applicable in cores with a B.V.N.C > 2.0.0.0 Controls how many.." hexmask.long.tbyte 0x0 8.--31. 1. "Reserved_8,Reserved_8" newline hexmask.long.byte 0x0 0.--7. 1. "ENABLE,Dusts enabled" line.long 0x4 "RGX_CR_DUSTS_ENABLE_1,Controls how many Dual Unified Shading and Texturing Units (DUSTs) are enabled. Each DUST Contain 2 USCs and a TPU module. (Available on 2. X.X.X cores and above). Only applicable in cores with a B.V.N.C > 2.0.0.0 Controls how many.." hexmask.long 0x4 0.--31. 1. "Reserved_8,Reserved_8" rgroup.long 0x58++0x7 line.long 0x0 "RGX_CR_DUSTS_FUSE_0,Indicates how many of the available DUST modules are enabled on the Silicon. (Available on 2.X.X.X cores and above). Shows the raw value of dusts_enable port." hexmask.long.tbyte 0x0 8.--31. 1. "Reserved_8,Reserved_8" newline hexmask.long.byte 0x0 0.--7. 1. "ENABLE,Dusts enabled" line.long 0x4 "RGX_CR_DUSTS_FUSE_1,Indicates how many of the available DUST modules are enabled on the Silicon. (Available on 2.X.X.X cores and above). Shows the raw value of dusts_enable port." hexmask.long 0x4 0.--31. 1. "Reserved_8,Reserved_8" group.long 0x80++0x7 line.long 0x0 "RGX_CR_CLK_XTPLUS_CTRL_0,Core Module Clock Control Modes. Allows individual domain clocks to be forced off. forced on or operate under automatic pipeline activity based clock gating. This register is generally controlled by the GPU firmware and should be.." hexmask.long 0x0 0.--31. 1. "Reserved_0,Reserved_0" line.long 0x4 "RGX_CR_CLK_XTPLUS_CTRL_1,Core Module Clock Control Modes. Allows individual domain clocks to be forced off. forced on or operate under automatic pipeline activity based clock gating. This register is generally controlled by the GPU firmware and should be.." hexmask.long 0x4 6.--31. 1. "Reserved_38,Reserved_38" newline bitfld.long 0x4 4.--5. "TDM,TDM" "0,1,2,3" newline bitfld.long 0x4 2.--3. "ASTC,ASTC" "0,1,2,3" newline bitfld.long 0x4 0.--1. "Reserved_0,Reserved_0" "0,1,2,3" rgroup.long 0x88++0x7 line.long 0x0 "RGX_CR_CLK_XTPLUS_STATUS_0,Reports the current module clock status Clock gating state reflects the condition of the clock for each module" hexmask.long.tbyte 0x0 11.--31. 1. "Reserved_11,Reserved_11" newline bitfld.long 0x0 10. "TDM,TDM" "0,1" newline bitfld.long 0x0 9. "IPF,IPF" "0,1" newline bitfld.long 0x0 8. "COMPUTE,COMPUTE" "0,1" newline bitfld.long 0x0 7. "ASTC,ASTC" "0,1" newline bitfld.long 0x0 6. "PIXEL,PIXEL" "0,1" newline bitfld.long 0x0 5. "VERTEX,VERTEX" "0,1" newline bitfld.long 0x0 4. "Reserved_4,Reserved_4" "0,1" newline bitfld.long 0x0 3. "PDS_SHARED,PDS_SHARED" "0,1" newline bitfld.long 0x0 2. "BIF_BLACKPEARL,BIF_BLACKPEARL" "0,1" newline bitfld.long 0x0 1. "USC_SHARED,USC_SHARED" "0,1" newline bitfld.long 0x0 0. "GEOMETRY,GEOMETRY" "0,1" line.long 0x4 "RGX_CR_CLK_XTPLUS_STATUS_1,Reports the current module clock status Clock gating state reflects the condition of the clock for each module" hexmask.long 0x4 0.--31. 1. "Reserved_11,Reserved_11" repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) rgroup.long ($2+0xE0)++0x3 line.long 0x0 "RGX_CR_SOC_TIMER_GRAY_$1,This register contains the value of a 64-bit external gray coded timer. (Available on 2.X.X.X cores and above)." hexmask.long 0x0 0.--31. 1. "VALUE,VALUE" repeat.end repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) rgroup.long ($2+0xE8)++0x3 line.long 0x0 "RGX_CR_SOC_TIMER_BINARY_$1,This register contains the value of a 64-bit external binary coded timer." hexmask.long 0x0 0.--31. 1. "VALUE,VALUE" repeat.end group.long 0x100++0xF line.long 0x0 "RGX_CR_SOFT_RESET_0,Core soft reset control register. Write a '1' to reset and a '0' to clear See the soft reset section in the TRM to understand how to use the soft reset register." bitfld.long 0x0 31. "RASCAL_CORE,Note that the RASL_CORE bit affects logic related to the reading and writing of registers. This soft reset should therefore be used with caution. Upon power down events it is necessary to reset every register so this bit should be used but.." "0,1" newline bitfld.long 0x0 30. "DUST_B_CORE,DUST_B_CORE" "0,1" newline bitfld.long 0x0 29. "DUST_A_CORE,DUST_A_CORE" "0,1" newline bitfld.long 0x0 28. "FB_TLCACHE,FB_TLCACHE" "0,1" newline bitfld.long 0x0 27. "SLC,SLC" "0,1" newline bitfld.long 0x0 26. "Reserved_26,Reserved_26" "0,1" newline bitfld.long 0x0 25. "UVS,UVS" "0,1" newline bitfld.long 0x0 24. "TE,TE" "0,1" newline bitfld.long 0x0 23. "GPP,GPP" "0,1" newline bitfld.long 0x0 22. "FBDC,FBDC" "0,1" newline bitfld.long 0x0 21. "FBC,FBC" "0,1" newline bitfld.long 0x0 20. "PM,PM" "0,1" newline bitfld.long 0x0 19. "PBE,PBE" "0,1" newline bitfld.long 0x0 18. "USC_SHARED,USC_SHARED" "0,1" newline bitfld.long 0x0 17. "MCU_L1,MCU_L1" "0,1" newline bitfld.long 0x0 16. "BIF,Bifpmcache BIF" "0,1" newline bitfld.long 0x0 15. "CDM,CDM" "0,1" newline bitfld.long 0x0 14. "VDM,VDM" "0,1" newline bitfld.long 0x0 13. "Reserved_13,Reserved_13" "0,1" newline bitfld.long 0x0 12. "PDS,PDS" "0,1" newline bitfld.long 0x0 11. "ISP,ISP" "0,1" newline bitfld.long 0x0 10. "TSP,TSP" "0,1" newline hexmask.long.byte 0x0 5.--9. 1. "Reserved_5,Reserved_5" newline bitfld.long 0x0 4. "TPU_MCU_DEMUX,TPU_MCU_DEMUX" "0,1" newline bitfld.long 0x0 3. "MCU_L0,MCU_L0" "0,1" newline bitfld.long 0x0 2. "TPU,TPU" "0,1" newline bitfld.long 0x0 1. "Reserved_1,Reserved_1" "0,1" newline bitfld.long 0x0 0. "USC,USC" "0,1" line.long 0x4 "RGX_CR_SOFT_RESET_1,Core soft reset control register. Write a '1' to reset and a '0' to clear See the soft reset section in the TRM to understand how to use the soft reset register." bitfld.long 0x4 29.--31. "Reserved_61,Reserved_61" "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 28. "JONES_CORE,JONES_CORE" "0,1" newline bitfld.long 0x4 27. "TILING_CORE,TILING_CORE" "0,1" newline bitfld.long 0x4 26. "TE3,TE3" "0,1" newline bitfld.long 0x4 25. "VCE,VCE" "0,1" newline bitfld.long 0x4 24. "VBS,VBS" "0,1" newline hexmask.long.byte 0x4 20.--23. 1. "Reserved_52,Reserved_52" newline bitfld.long 0x4 19. "FB_CDC,FB_CDC" "0,1" newline bitfld.long 0x4 17.--18. "Reserved_49,Reserved_49" "0,1,2,3" newline bitfld.long 0x4 16. "MCU_FBTC,MCU_FBTC" "0,1" newline hexmask.long.word 0x4 3.--15. 1. "Reserved_35,Reserved_35" newline bitfld.long 0x4 2. "MMU,MMU" "0,1" newline bitfld.long 0x4 1. "Reserved_33,Reserved_33" "0,1" newline bitfld.long 0x4 0. "GARTEN,Includes MTS and META or MIPS" "0,1" line.long 0x8 "RGX_CR_SOFT_RESET2_0,Core soft reset control register. Write a '1' to reset and a '0' to clear See the soft reset section in the TRM to understand how to use the soft reset register." hexmask.long.tbyte 0x8 12.--31. 1. "Reserved_12,Reserved_12" newline bitfld.long 0x8 11. "TDM,TDM" "0,1" newline bitfld.long 0x8 10. "ASTC,ASTC" "0,1" newline bitfld.long 0x8 9. "BLACKPEARL,BLACKPEARL" "0,1" newline bitfld.long 0x8 8. "Reserved_8,Reserved_8" "0,1" newline bitfld.long 0x8 7. "IPF,IPF" "0,1" newline bitfld.long 0x8 6. "GEOMETRY,GEOMETRY" "0,1" newline bitfld.long 0x8 5. "USC_SHARED,USC_SHARED" "0,1" newline bitfld.long 0x8 4. "PDS_SHARED,PDS_SHARED" "0,1" newline bitfld.long 0x8 3. "BIF_BLACKPEARL,BIF_BLACKPEARL" "0,1" newline bitfld.long 0x8 2. "PIXEL,PIXEL" "0,1" newline bitfld.long 0x8 1. "Reserved_1,Reserved_1" "0,1" newline bitfld.long 0x8 0. "VERTEX,VERTEX" "0,1" line.long 0xC "RGX_CR_SOFT_RESET2_1,Core soft reset control register. Write a '1' to reset and a '0' to clear See the soft reset section in the TRM to understand how to use the soft reset register." hexmask.long 0xC 0.--31. 1. "Reserved_12,Reserved_12" group.long 0x120++0x17 line.long 0x0 "RGX_CR_CONTEXT_SWITCH_ENABLE_0,The use of the this register has been deprecated." hexmask.long 0x0 4.--31. 1. "Reserved_4,Reserved_4" newline bitfld.long 0x0 3. "SOFT_RESET,SOFT_RESET" "0,1" newline bitfld.long 0x0 2. "IPF,IPF" "0,1" newline bitfld.long 0x0 1. "VDM,VDM" "0,1" newline bitfld.long 0x0 0. "CDM,CDM" "0,1" line.long 0x4 "RGX_CR_CONTEXT_SWITCH_ENABLE_1,The use of the this register has been deprecated." hexmask.long 0x4 0.--31. 1. "Reserved_4,Reserved_4" line.long 0x8 "RGX_CR_EVENT_ENABLE_0,This register is used to enable GPU interrupts directly to the host Writing a '1' to a bit field enables the relevant event This register should only be programmed when the META firmware is not used If the META firmware is used. the.." bitfld.long 0x8 31. "TDM_FENCE_FINISHED,Indicates a 2D fence has been processed" "0,1" newline bitfld.long 0x8 30. "TDM_BUFFER_STALL,The TDM has exhausted the current 2D circular buffer (read pointer = write_pointer)" "0,1" newline hexmask.long.word 0x8 19.--29. 1. "Reserved_19,Reserved_19" newline bitfld.long 0x8 18. "TDM_CONTEXT_STORE_FINISHED,The TDM has completed the requested context store operation." "0,1" newline bitfld.long 0x8 16.--17. "Reserved_16,Reserved_16" "0,1,2,3" newline bitfld.long 0x8 15. "USC_TRIGGER,One or more USC has executed a nop.trigger instruction" "0,1" newline bitfld.long 0x8 14. "ZLS_FINISHED,ZLS has finished all tiles in a Render" "0,1" newline bitfld.long 0x8 13. "GPIO_ACK,General Purpose ouput acknowledgement" "0,1" newline bitfld.long 0x8 12. "GPIO_REQ,General Purpose input request" "0,1" newline bitfld.long 0x8 11. "POWER_ABORT,The requested power operation has been denied." "0,1" newline bitfld.long 0x8 10. "POWER_COMPLETE,The requested power operation has completed" "0,1" newline bitfld.long 0x8 9. "MMU_PAGE_FAULT,An MMU page fault has occurred" "0,1" newline bitfld.long 0x8 8. "PM_3D_MEM_FREE,PM memory allocation completed for the current render" "0,1" newline bitfld.long 0x8 7. "PM_OUT_OF_MEMORY,PM memory allocation failed for a macro-tile" "0,1" newline bitfld.long 0x8 6. "TA_TERMINATE,The TE has aborted a macro tile after a failted PM allocation request" "0,1" newline bitfld.long 0x8 5. "TA_FINISHED,The TA phase has completed" "0,1" newline bitfld.long 0x8 4. "ISP_END_MACROTILE,ISP End-of-Macrotile" "0,1" newline bitfld.long 0x8 3. "PIXELBE_END_RENDER,The 3D phase has completed" "0,1" newline bitfld.long 0x8 2. "COMPUTE_FINISHED,The compute phase has completed" "0,1" newline bitfld.long 0x8 1. "KERNEL_FINISHED,A compute kernel has completed and updated the associated event object in external memory" "0,1" newline bitfld.long 0x8 0. "Reserved_0,Reserved_0" "0,1" line.long 0xC "RGX_CR_EVENT_ENABLE_1,This register is used to enable GPU interrupts directly to the host Writing a '1' to a bit field enables the relevant event This register should only be programmed when the META firmware is not used If the META firmware is used. the.." hexmask.long 0xC 0.--31. 1. "Reserved_32,Reserved_32" line.long 0x10 "RGX_CR_EVENT_STATUS_0,The event status register indicate the source of an interrupt generated by PowerVR RGX These events only schedule an interrupt context thread to run on META when the appropriate enables are set in RGX_CR_DMn_INTERRUPT_ENABLE" bitfld.long 0x10 31. "TDM_FENCE_FINISHED,Indicates a 2D fence has been processed" "0,1" newline bitfld.long 0x10 30. "TDM_BUFFER_STALL,The TDM has exhausted the current 2D circular buffer (read pointer = write_pointer)" "0,1" newline hexmask.long.word 0x10 19.--29. 1. "Reserved_19,Reserved_19" newline bitfld.long 0x10 18. "TDM_CONTEXT_STORE_FINISHED,The TDM has completed the requested context store operation." "0,1" newline bitfld.long 0x10 16.--17. "Reserved_16,Reserved_16" "0,1,2,3" newline bitfld.long 0x10 15. "USC_TRIGGER,One or more USC has executed a nop.trigger instruction" "0,1" newline bitfld.long 0x10 14. "ZLS_FINISHED,ZLS has finished all tiles in a Render" "0,1" newline bitfld.long 0x10 13. "GPIO_ACK,General Purpose ouput acknowledgement" "0,1" newline bitfld.long 0x10 12. "GPIO_REQ,General Purpose input request" "0,1" newline bitfld.long 0x10 11. "POWER_ABORT,The requested power operation has been denied." "0,1" newline bitfld.long 0x10 10. "POWER_COMPLETE,The requested power operation has completed" "0,1" newline bitfld.long 0x10 9. "MMU_PAGE_FAULT,An MMU page fault has occurred" "0,1" newline bitfld.long 0x10 8. "PM_3D_MEM_FREE,PM memory allocation completed for the current render" "0,1" newline bitfld.long 0x10 7. "PM_OUT_OF_MEMORY,PM memory allocation failed for a macro-tile" "0,1" newline bitfld.long 0x10 6. "TA_TERMINATE,The TE has aborted a macro tile after a failted PM allocation request" "0,1" newline bitfld.long 0x10 5. "TA_FINISHED,The TA phase has completed" "0,1" newline bitfld.long 0x10 4. "ISP_END_MACROTILE,ISP End-of-Macrotile" "0,1" newline bitfld.long 0x10 3. "PIXELBE_END_RENDER,The 3D phase has completed" "0,1" newline bitfld.long 0x10 2. "COMPUTE_FINISHED,The compute phase has completed" "0,1" newline bitfld.long 0x10 1. "KERNEL_FINISHED,A compute kernel has completed and updated the associated event object in external memory" "0,1" newline bitfld.long 0x10 0. "Reserved_0,Reserved_0" "0,1" line.long 0x14 "RGX_CR_EVENT_STATUS_1,The event status register indicate the source of an interrupt generated by PowerVR RGX These events only schedule an interrupt context thread to run on META when the appropriate enables are set in RGX_CR_DMn_INTERRUPT_ENABLE" hexmask.long 0x14 0.--31. 1. "Reserved_32,Reserved_32" wgroup.long 0x138++0x7 line.long 0x0 "RGX_CR_EVENT_CLEAR_0,This register is used to clear event interrupts. Writing a '1' to a bit field clears the relevant event." bitfld.long 0x0 31. "TDM_FENCE_FINISHED,Indicates a 2D fence has been processed" "0,1" newline bitfld.long 0x0 30. "TDM_BUFFER_STALL,The TDM has exhausted the current 2D circular buffer (read pointer = write_pointer)" "0,1" newline hexmask.long.word 0x0 19.--29. 1. "Reserved_19,Reserved_19" newline bitfld.long 0x0 18. "TDM_CONTEXT_STORE_FINISHED,The TDM has completed the requested context store operation." "0,1" newline bitfld.long 0x0 16.--17. "Reserved_16,Reserved_16" "0,1,2,3" newline bitfld.long 0x0 15. "USC_TRIGGER,One or more USC has executed a nop.trigger instruction" "0,1" newline bitfld.long 0x0 14. "ZLS_FINISHED,ZLS has finished all tiles in a Render" "0,1" newline bitfld.long 0x0 13. "GPIO_ACK,General Purpose ouput acknowledgement" "0,1" newline bitfld.long 0x0 12. "GPIO_REQ,General Purpose input request" "0,1" newline bitfld.long 0x0 11. "POWER_ABORT,The requested power operation has been denied." "0,1" newline bitfld.long 0x0 10. "POWER_COMPLETE,The requested power operation has completed" "0,1" newline bitfld.long 0x0 9. "MMU_PAGE_FAULT,An MMU page fault has occurred" "0,1" newline bitfld.long 0x0 8. "PM_3D_MEM_FREE,PM memory allocation completed for the current render" "0,1" newline bitfld.long 0x0 7. "PM_OUT_OF_MEMORY,PM memory allocation failed for a macro-tile" "0,1" newline bitfld.long 0x0 6. "TA_TERMINATE,The TE has aborted a macro tile after a failted PM allocation request" "0,1" newline bitfld.long 0x0 5. "TA_FINISHED,The TA phase has completed" "0,1" newline bitfld.long 0x0 4. "ISP_END_MACROTILE,ISP End-of-Macrotile" "0,1" newline bitfld.long 0x0 3. "PIXELBE_END_RENDER,The 3D phase has completed" "0,1" newline bitfld.long 0x0 2. "COMPUTE_FINISHED,The compute phase has completed" "0,1" newline bitfld.long 0x0 1. "KERNEL_FINISHED,A compute kernel has completed and updated the associated event object in external memory" "0,1" newline bitfld.long 0x0 0. "Reserved_0,Reserved_0" "0,1" line.long 0x4 "RGX_CR_EVENT_CLEAR_1,This register is used to clear event interrupts. Writing a '1' to a bit field clears the relevant event." hexmask.long 0x4 0.--31. 1. "Reserved_32,Reserved_32" group.long 0x140++0xF line.long 0x0 "RGX_CR_GPIO_OUTPUT_DATA_0,General Purpose Input/Output interface for implementing communication protocol between HW external to Rogue and the firmware These registers are connected to top-level pins These registers are driven by the firmware. When the.." hexmask.long.tbyte 0x0 8.--31. 1. "Reserved_8,Reserved_8" newline hexmask.long.byte 0x0 0.--7. 1. "DATA,The data the firmware wants to transfer" line.long 0x4 "RGX_CR_GPIO_OUTPUT_DATA_1,General Purpose Input/Output interface for implementing communication protocol between HW external to Rogue and the firmware These registers are connected to top-level pins These registers are driven by the firmware. When the.." hexmask.long 0x4 0.--31. 1. "Reserved_8,Reserved_8" line.long 0x8 "RGX_CR_GPIO_OUTPUT_REQ_0,General Purpose Input/Output interface for implementing communication protocol between HW external to Rogue and the firmware This register is connected to a top-level pin This register is driven by the firmware. When the request.." hexmask.long 0x8 1.--31. 1. "Reserved_1,Reserved_1" newline bitfld.long 0x8 0. "REQ,Set when the firmware wants to communicate with a external HW" "0,1" line.long 0xC "RGX_CR_GPIO_OUTPUT_REQ_1,General Purpose Input/Output interface for implementing communication protocol between HW external to Rogue and the firmware This register is connected to a top-level pin This register is driven by the firmware. When the request.." hexmask.long 0xC 0.--31. 1. "Reserved_1,Reserved_1" rgroup.long 0x150++0x7 line.long 0x0 "RGX_CR_GPIO_INPUT_DATA_0,General Purpose Input/Output interface for implementing communication protocol between HW external to Rogue and the firmware This register is connected to top-level pins This register is driven by HW external to rogue before.." hexmask.long.tbyte 0x0 8.--31. 1. "Reserved_8,Reserved_8" newline hexmask.long.byte 0x0 0.--7. 1. "DATA,The incoming data from HW external to Rogue" line.long 0x4 "RGX_CR_GPIO_INPUT_DATA_1,General Purpose Input/Output interface for implementing communication protocol between HW external to Rogue and the firmware This register is connected to top-level pins This register is driven by HW external to rogue before.." hexmask.long 0x4 0.--31. 1. "Reserved_8,Reserved_8" group.long 0x158++0x7 line.long 0x0 "RGX_CR_GPIO_INPUT_ACK_0,General Purpose Input/Output interface for implementing communication protocol between HW external to Rogue and the firmware This register is connected to a top-level pin This register is driven by external HW in response to an.." hexmask.long 0x0 1.--31. 1. "Reserved_1,Reserved_1" newline bitfld.long 0x0 0. "ACK,Set by the firmware when it has acknowledged the incoming request" "0,1" line.long 0x4 "RGX_CR_GPIO_INPUT_ACK_1,General Purpose Input/Output interface for implementing communication protocol between HW external to Rogue and the firmware This register is connected to a top-level pin This register is driven by external HW in response to an.." hexmask.long 0x4 0.--31. 1. "Reserved_1,Reserved_1" rgroup.long 0x160++0x7 line.long 0x0 "RGX_CR_TIMER_0,This register contains the value of a 48-bit internal timer. The timer runs continuously. and wraps at the top end. It counts 256 cycles at the core clock frequency. This means that at 100 MHz: 1 count value = 1/100MHz = 256 * 10 * 10^-9.." hexmask.long 0x0 0.--31. 1. "VALUE,VALUE" line.long 0x4 "RGX_CR_TIMER_1,This register contains the value of a 48-bit internal timer. The timer runs continuously. and wraps at the top end. It counts 256 cycles at the core clock frequency. This means that at 100 MHz: 1 count value = 1/100MHz = 256 * 10 * 10^-9.." bitfld.long 0x4 31. "BIT31,BIT31" "0,1" newline hexmask.long.word 0x4 16.--30. 1. "Reserved_48,Reserved_48" newline hexmask.long.word 0x4 0.--15. 1. "VALUE,VALUE" group.long 0x168++0x7 line.long 0x0 "RGX_CR_AXI_EXACCESS_0,AXI exclusive access enable register" hexmask.long 0x0 1.--31. 1. "Reserved_1,Reserved_1" newline bitfld.long 0x0 0. "SOCIF_ENABLE,enable the exclusive access logic in the socif img_axi2img. vhd module" "0,1" line.long 0x4 "RGX_CR_AXI_EXACCESS_1,AXI exclusive access enable register" hexmask.long 0x4 0.--31. 1. "Reserved_1,Reserved_1" group.long 0x190++0x17 line.long 0x0 "RGX_CR_PM_TASK_MLIST_LOAD_0,This register is part of the parameter management. which controls the allocation and de-allocation of memory for the 3D display list (parameters). The MLIST is the list of Pages which have been allocated to thew MMU. to map.." hexmask.long 0x0 1.--31. 1. "Reserved_1,Reserved_1" newline bitfld.long 0x0 0. "PENDING,A write to this register will cause the MLIST pointer to be loaded from either PM_MLIST0_START_OF or PM_MLIST1_START_OF depending upon the Context ID contained in PM_CONTEXT_ID_MLS_LS. A read to this register return '1' until this operation has.." "0,1" line.long 0x4 "RGX_CR_PM_TASK_MLIST_LOAD_1,This register is part of the parameter management. which controls the allocation and de-allocation of memory for the 3D display list (parameters). The MLIST is the list of Pages which have been allocated to thew MMU. to map.." hexmask.long 0x4 0.--31. 1. "Reserved_1,Reserved_1" line.long 0x8 "RGX_CR_PM_TASK_MLIST_CLEAR_0,This register is part of the parameter management. which controls the allocation and de-allocation of memory for the 3D display list (parameters). The MLIST is the list of Pages which have been allocated to thew MMU. to map.." hexmask.long 0x8 1.--31. 1. "Reserved_1,Reserved_1" newline bitfld.long 0x8 0. "PENDING,A write to this register will cause the MLIST pointer to be reset to 0. A read to this register return '1' until this operation has completed." "0,1" line.long 0xC "RGX_CR_PM_TASK_MLIST_CLEAR_1,This register is part of the parameter management. which controls the allocation and de-allocation of memory for the 3D display list (parameters). The MLIST is the list of Pages which have been allocated to thew MMU. to map.." hexmask.long 0xC 0.--31. 1. "Reserved_1,Reserved_1" line.long 0x10 "RGX_CR_PM_TA_MAX_RENDER_TARGET_0,This register is deprecated and has no function." hexmask.long.tbyte 0x10 11.--31. 1. "Reserved_11,Reserved_11" newline hexmask.long.word 0x10 0.--10. 1. "ID,If used the software should program this with the maximum render target array index used within the Scene" line.long 0x14 "RGX_CR_PM_TA_MAX_RENDER_TARGET_1,This register is deprecated and has no function." hexmask.long 0x14 0.--31. 1. "Reserved_11,Reserved_11" rgroup.long 0x1A8++0x7 line.long 0x0 "RGX_CR_PM_MTILE_ARRAY_REORDER_VALID_STATUS_0,This register is deprecated and has no function." hexmask.long 0x0 1.--31. 1. "Reserved_1,Reserved_1" newline bitfld.long 0x0 0. "OP,OP" "0,1" line.long 0x4 "RGX_CR_PM_MTILE_ARRAY_REORDER_VALID_STATUS_1,This register is deprecated and has no function." hexmask.long 0x4 0.--31. 1. "Reserved_1,Reserved_1" group.long 0x1B0++0x1F line.long 0x0 "RGX_CR_PM_EMPTY_PAGE_FAST_FREEING_0,This register is part of the parameter management. which controls the allocation and de-allocation of memory for the 3D display list (parameters). This register enables an optimisation which causes pages which have.." hexmask.long 0x0 1.--31. 1. "Reserved_1,Reserved_1" newline bitfld.long 0x0 0. "ID,When set enable freeing of unused pages during TA phase" "0,1" line.long 0x4 "RGX_CR_PM_EMPTY_PAGE_FAST_FREEING_1,This register is part of the parameter management. which controls the allocation and de-allocation of memory for the 3D display list (parameters). This register enables an optimisation which causes pages which have.." hexmask.long 0x4 0.--31. 1. "Reserved_1,Reserved_1" line.long 0x8 "RGX_CR_PM_MMU_REMAP_PENDING_0,This register is part of the parameter management. which controls the allocation and de-allocation of memory for the 3D display list (parameters). This register starts the process of remapping the remaining physical pages at.." hexmask.long 0x8 1.--31. 1. "Reserved_1,Reserved_1" newline bitfld.long 0x8 0. "OP,Pending status register corresponding to the MMU remapping operation it will become '1' when written and deassert when the operation complete." "0,1" line.long 0xC "RGX_CR_PM_MMU_REMAP_PENDING_1,This register is part of the parameter management. which controls the allocation and de-allocation of memory for the 3D display list (parameters). This register starts the process of remapping the remaining physical pages at.." hexmask.long 0xC 0.--31. 1. "Reserved_1,Reserved_1" line.long 0x10 "RGX_CR_PM_PBE_FORCE_FREEING_0,This register is part of the parameter management. which controls the allocation and de-allocation of memory for the 3D display list (parameters). Normally freeing of memory is associated with macrotiles (a portion of the.." hexmask.long 0x10 1.--31. 1. "Reserved_1,Reserved_1" newline bitfld.long 0x10 0. "ENABLE,When this bit is set PM will free all the 3D context Memory when a genuine pixelbe end of render is received." "0,1" line.long 0x14 "RGX_CR_PM_PBE_FORCE_FREEING_1,This register is part of the parameter management. which controls the allocation and de-allocation of memory for the 3D display list (parameters). Normally freeing of memory is associated with macrotiles (a portion of the.." hexmask.long 0x14 0.--31. 1. "Reserved_1,Reserved_1" line.long 0x18 "RGX_CR_PM_PDS_STARTOF_MTILEFREE_0,RGX_CR_PM_PDS_STARTOF_MTILEFREE_0" hexmask.long.word 0x18 17.--31. 1. "Reserved_17,Reserved_17" newline hexmask.long.tbyte 0x18 0.--16. 1. "OP,This startof register indicates the macrotile number of the PDSs current macrotile free request needs to be programmed by FW on a render start" line.long 0x1C "RGX_CR_PM_PDS_STARTOF_MTILEFREE_1,RGX_CR_PM_PDS_STARTOF_MTILEFREE_1" hexmask.long 0x1C 0.--31. 1. "Reserved_17,Reserved_17" group.long 0x200++0x1F line.long 0x0 "RGX_CR_PM_TASK_3D_FREE_LOAD_0,RGX_CR_PM_TASK_3D_FREE_LOAD_0" hexmask.long 0x0 1.--31. 1. "Reserved_1,Reserved_1" newline bitfld.long 0x0 0. "PENDING,A write into this register will cause the 3D free list context to be loaded from the relevant configuration registers" "0,1" line.long 0x4 "RGX_CR_PM_TASK_3D_FREE_LOAD_1,RGX_CR_PM_TASK_3D_FREE_LOAD_1" hexmask.long 0x4 0.--31. 1. "Reserved_1,Reserved_1" line.long 0x8 "RGX_CR_PM_TASK_TA_FREE_LOAD_0,RGX_CR_PM_TASK_TA_FREE_LOAD_0" hexmask.long 0x8 1.--31. 1. "Reserved_1,Reserved_1" newline bitfld.long 0x8 0. "PENDING,A write into this register will cause the TA free list context to be loaded from the relevant configuration registers" "0,1" line.long 0xC "RGX_CR_PM_TASK_TA_FREE_LOAD_1,RGX_CR_PM_TASK_TA_FREE_LOAD_1" hexmask.long 0xC 0.--31. 1. "Reserved_1,Reserved_1" line.long 0x10 "RGX_CR_PM_TA_FSTACK_BASE_0,Effective on load TA context. this register defines the base address of the free list stack being referenced during TA processing." hexmask.long 0x10 4.--31. 1. "ADDR,1TB Addressable 128 bits aligned Base Address for TA context page tables in the DPM module" newline hexmask.long.byte 0x10 0.--3. 1. "Reserved_0,Reserved_0" line.long 0x14 "RGX_CR_PM_TA_FSTACK_BASE_1,Effective on load TA context. this register defines the base address of the free list stack being referenced during TA processing." hexmask.long.tbyte 0x14 8.--31. 1. "Reserved_40,Reserved_40" newline hexmask.long.byte 0x14 0.--7. 1. "ADDR,1TB Addressable 128 bits aligned Base Address for TA context page tables in the DPM module" line.long 0x18 "RGX_CR_PM_3D_FSTACK_BASE_0,Effective on load 3D context. this register defines the base address of the free list table being referenced in the process of de-allocating pages during a 3D render." hexmask.long 0x18 4.--31. 1. "ADDR,1TB Addressable 128 bits aligned Base Address for 3D context page tables in the DPM module" newline hexmask.long.byte 0x18 0.--3. 1. "Reserved_0,Reserved_0" line.long 0x1C "RGX_CR_PM_3D_FSTACK_BASE_1,Effective on load 3D context. this register defines the base address of the free list table being referenced in the process of de-allocating pages during a 3D render." hexmask.long.tbyte 0x1C 8.--31. 1. "Reserved_40,Reserved_40" newline hexmask.long.byte 0x1C 0.--7. 1. "ADDR,1TB Addressable 128 bits aligned Base Address for 3D context page tables in the DPM module" repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) group.long ($2+0x220)++0x3 line.long 0x0 "RGX_CR_PM_TA_FSTACK_$1,Note: each 16GB 4KB addressable page (22 bits) is rounded to dword aligned" hexmask.long.word 0x0 22.--31. 1. "Reserved_22,Reserved_22" newline hexmask.long.tbyte 0x0 0.--21. 1. "SIZE,This register defines the number of 4K pages in the free list stack used for the TA page allocation effective on a load TA context." repeat.end group.long 0x230++0x7 line.long 0x0 "RGX_CR_PM_3D_FSTACK_0,Note: each 16GB 4KB addressable page (22 bits) is rounded to dword aligned" hexmask.long.word 0x0 22.--31. 1. "STARTOF_TOP,This register defines the head pointer of the free list in terms of 4K free pages in the free list stack effective on a load TA context." newline hexmask.long.tbyte 0x0 0.--21. 1. "SIZE,This register defines the number of 4K pages in the free list stack used for the TA page allocation effective on a load TA context." line.long 0x4 "RGX_CR_PM_3D_FSTACK_1,Note: each 16GB 4KB addressable page (22 bits) is rounded to dword aligned" hexmask.long.tbyte 0x4 12.--31. 1. "Reserved_44,Reserved_44" newline hexmask.long.word 0x4 0.--11. 1. "STARTOF_TOP,This register defines the head pointer of the free list in terms of 4K free pages in the free list stack effective on a load TA context." group.long 0x240++0x2F line.long 0x0 "RGX_CR_PM_MTILE_ARRAY_0,Effective Immediately." hexmask.long 0x0 4.--31. 1. "BASE_ADDR,1TB Addressable 128 bits aligned Base Address for Mtile Array Base" newline hexmask.long.byte 0x0 0.--3. 1. "Reserved_0,Reserved_0" line.long 0x4 "RGX_CR_PM_MTILE_ARRAY_1,Effective Immediately." hexmask.long.tbyte 0x4 8.--31. 1. "Reserved_40,Reserved_40" newline hexmask.long.byte 0x4 0.--7. 1. "BASE_ADDR,1TB Addressable 128 bits aligned Base Address for Mtile Array Base" line.long 0x8 "RGX_CR_PM_VHEAP_TABLE_0,Effective immediately. this register defines the base address of the virtual heap table information. The size of the Virtual Heap needs to be no smaller than PM_VHEAP_TABLE_SIZE Dwords." hexmask.long 0x8 4.--31. 1. "BASE_ADDR,1TB Addressable 128 bits aligned Base Address for Virtual Heap Table" newline hexmask.long.byte 0x8 0.--3. 1. "Reserved_0,Reserved_0" line.long 0xC "RGX_CR_PM_VHEAP_TABLE_1,Effective immediately. this register defines the base address of the virtual heap table information. The size of the Virtual Heap needs to be no smaller than PM_VHEAP_TABLE_SIZE Dwords." hexmask.long.tbyte 0xC 8.--31. 1. "Reserved_40,Reserved_40" newline hexmask.long.byte 0xC 0.--7. 1. "BASE_ADDR,1TB Addressable 128 bits aligned Base Address for Virtual Heap Table" line.long 0x10 "RGX_CR_PM_TASK_VHEAP_LOAD_0,RGX_CR_PM_TASK_VHEAP_LOAD_0" hexmask.long 0x10 1.--31. 1. "Reserved_1,Reserved_1" newline bitfld.long 0x10 0. "PENDING,Causes the vheap to be loaded as specified by the relevant configuration registers when it is done the hw will clear this bit" "0,1" line.long 0x14 "RGX_CR_PM_TASK_VHEAP_LOAD_1,RGX_CR_PM_TASK_VHEAP_LOAD_1" hexmask.long 0x14 0.--31. 1. "Reserved_1,Reserved_1" line.long 0x18 "RGX_CR_PM_TASK_VHEAP_CLEAR_0,RGX_CR_PM_TASK_VHEAP_CLEAR_0" hexmask.long 0x18 1.--31. 1. "Reserved_1,Reserved_1" newline bitfld.long 0x18 0. "PENDING,Causes the vheap to be cleared as specified by the relevant configuration registers. When it is done the hw will clear this bit" "0,1" line.long 0x1C "RGX_CR_PM_TASK_VHEAP_CLEAR_1,RGX_CR_PM_TASK_VHEAP_CLEAR_1" hexmask.long 0x1C 0.--31. 1. "Reserved_1,Reserved_1" line.long 0x20 "RGX_CR_PM_TASK_VHEAP_STORE_0,RGX_CR_PM_TASK_VHEAP_STORE_0" hexmask.long 0x20 1.--31. 1. "Reserved_1,Reserved_1" newline bitfld.long 0x20 0. "PENDING,Causes the vheap to be stored as specified by the relevant configuration registers. When it is done the hw will clear this bit" "0,1" line.long 0x24 "RGX_CR_PM_TASK_VHEAP_STORE_1,RGX_CR_PM_TASK_VHEAP_STORE_1" hexmask.long 0x24 0.--31. 1. "Reserved_1,Reserved_1" line.long 0x28 "RGX_CR_PM_ALIST0_START_OF_0,start pointer of the allocation list tail.in size of 8 bytes" hexmask.long 0x28 0.--31. 1. "TAIL,allocation List 0 tail pointer" line.long 0x2C "RGX_CR_PM_ALIST0_START_OF_1,start pointer of the allocation list tail.in size of 8 bytes" hexmask.long 0x2C 1.--31. 1. "Reserved_33,Reserved_33" newline bitfld.long 0x2C 0. "TAIL,allocation List 0 tail pointer" "0,1" rgroup.long 0x270++0x7 line.long 0x0 "RGX_CR_PM_ALIST0_STATUS_0,pointer of current allocation list.in size of 8 bytes" hexmask.long 0x0 0.--31. 1. "TAIL,allocation List tail pointer" line.long 0x4 "RGX_CR_PM_ALIST0_STATUS_1,pointer of current allocation list.in size of 8 bytes" hexmask.long 0x4 1.--31. 1. "Reserved_33,Reserved_33" newline bitfld.long 0x4 0. "TAIL,allocation List tail pointer" "0,1" group.long 0x278++0x7 line.long 0x0 "RGX_CR_PM_ALIST1_START_OF_0,start of the tail pointer of current allocation list.effecitve on an allocation_list_load" hexmask.long 0x0 0.--31. 1. "TAIL,start of the allocation list tail pointer" line.long 0x4 "RGX_CR_PM_ALIST1_START_OF_1,start of the tail pointer of current allocation list.effecitve on an allocation_list_load" hexmask.long 0x4 1.--31. 1. "Reserved_33,Reserved_33" newline bitfld.long 0x4 0. "TAIL,start of the allocation list tail pointer" "0,1" rgroup.long 0x280++0x7 line.long 0x0 "RGX_CR_PM_ALIST1_STATUS_0,pointer of current allocation list.in size of 8 bytes" hexmask.long 0x0 0.--31. 1. "TAIL,allocation List tail pointer" line.long 0x4 "RGX_CR_PM_ALIST1_STATUS_1,pointer of current allocation list.in size of 8 bytes" hexmask.long 0x4 1.--31. 1. "Reserved_33,Reserved_33" newline bitfld.long 0x4 0. "TAIL,allocation List tail pointer" "0,1" group.long 0x288++0x1F line.long 0x0 "RGX_CR_PM_TASK_ALIST_LOAD_0,RGX_CR_PM_TASK_ALIST_LOAD_0" hexmask.long 0x0 1.--31. 1. "Reserved_1,Reserved_1" newline bitfld.long 0x0 0. "PENDING,the write to this register will cause allocation list to be loaded from the relevant configuration registers" "0,1" line.long 0x4 "RGX_CR_PM_TASK_ALIST_LOAD_1,RGX_CR_PM_TASK_ALIST_LOAD_1" hexmask.long 0x4 0.--31. 1. "Reserved_1,Reserved_1" line.long 0x8 "RGX_CR_PM_TASK_ALIST_CLEAR_0,RGX_CR_PM_TASK_ALIST_CLEAR_0" hexmask.long 0x8 1.--31. 1. "Reserved_1,Reserved_1" newline bitfld.long 0x8 0. "PENDING,the write to this register will causes the allocation list to be cleard from the relevant configuration registers" "0,1" line.long 0xC "RGX_CR_PM_TASK_ALIST_CLEAR_1,RGX_CR_PM_TASK_ALIST_CLEAR_1" hexmask.long 0xC 0.--31. 1. "Reserved_1,Reserved_1" line.long 0x10 "RGX_CR_PM_DEALLOCATION_STARTOF_MASK_0,RGX_CR_PM_DEALLOCATION_STARTOF_MASK_0" hexmask.long.word 0x10 16.--31. 1. "Reserved_16,Reserved_16" newline hexmask.long.word 0x10 0.--15. 1. "OP,This is the start of the mask PM deallocation will be based on. Normally it is 0. However in ISP context resume or extra 3D timeout case the driver has to programme the value from the previous render." line.long 0x14 "RGX_CR_PM_DEALLOCATION_STARTOF_MASK_1,RGX_CR_PM_DEALLOCATION_STARTOF_MASK_1" hexmask.long 0x14 0.--31. 1. "Reserved_16,Reserved_16" line.long 0x18 "RGX_CR_PM_PAGE_MANAGEOP_0,RGX_CR_PM_PAGE_MANAGEOP_0" hexmask.long 0x18 3.--31. 1. "Reserved_3,Reserved_3" newline bitfld.long 0x18 2. "COMBINE_DALLOC,1 means the PM writes to the free stack will be burst combined" "0,1" newline bitfld.long 0x18 1. "DISABLE_DALLOC,1 means the PM page management deallocation operation will be disabled" "0,1" newline bitfld.long 0x18 0. "DISABLE_ALLOC,1 means the PM page management allocation operation will be disabled" "0,1" line.long 0x1C "RGX_CR_PM_PAGE_MANAGEOP_1,RGX_CR_PM_PAGE_MANAGEOP_1" hexmask.long 0x1C 0.--31. 1. "Reserved_3,Reserved_3" rgroup.long 0x2A8++0x7 line.long 0x0 "RGX_CR_PM_PAGE_MANAGEOP_STATUS_0,RGX_CR_PM_PAGE_MANAGEOP_STATUS_0" hexmask.long 0x0 2.--31. 1. "Reserved_2,Reserved_2" newline bitfld.long 0x0 1. "DALLOC_DISABLED,1 means the PM page management operation has been disabled" "0,1" newline bitfld.long 0x0 0. "ALLOC_DISABLED,1 means the PM page management operation has been disabled" "0,1" line.long 0x4 "RGX_CR_PM_PAGE_MANAGEOP_STATUS_1,RGX_CR_PM_PAGE_MANAGEOP_STATUS_1" hexmask.long 0x4 0.--31. 1. "Reserved_2,Reserved_2" group.long 0x2B0++0xF line.long 0x0 "RGX_CR_PM_CONTEXT_PB_BASE_0,RGX_CR_PM_CONTEXT_PB_BASE_0" hexmask.long 0x0 3.--31. 1. "Reserved_3,Reserved_3" newline bitfld.long 0x0 0.--2. "CMP,Defines whether the TA/3D/HOST contexts are using the same parameter buffer. Setting a bit to '1' indicates that the context is using a different parameter buffer. Bit 0 = 0 : Unified Free List 3D context Parameter buffer = Unified Free List TA.." "MMU Free List 3D context Parameter buffer = MMU..,?,?,?,?,?,?,?" line.long 0x4 "RGX_CR_PM_CONTEXT_PB_BASE_1,RGX_CR_PM_CONTEXT_PB_BASE_1" hexmask.long 0x4 0.--31. 1. "Reserved_3,Reserved_3" line.long 0x8 "RGX_CR_PM_MLIST0_START_OF_0,start value of the mlist tail @ the loading of the context. in size of 4 bytes. stride is 64KB" hexmask.long.word 0x8 22.--31. 1. "Reserved_22,Reserved_22" newline hexmask.long.tbyte 0x8 0.--21. 1. "TAIL,allocation List 0 tail pointer" line.long 0xC "RGX_CR_PM_MLIST0_START_OF_1,start value of the mlist tail @ the loading of the context. in size of 4 bytes. stride is 64KB" hexmask.long 0xC 0.--31. 1. "Reserved_22,Reserved_22" rgroup.long 0x2C0++0x7 line.long 0x0 "RGX_CR_PM_MLIST0_STATUS_0,pointer of current mmu allocation list.in size of 4 bytes. stride is 64KB" hexmask.long.word 0x0 22.--31. 1. "Reserved_22,Reserved_22" newline hexmask.long.tbyte 0x0 0.--21. 1. "TAIL,allocation List 1 tail pointer" line.long 0x4 "RGX_CR_PM_MLIST0_STATUS_1,pointer of current mmu allocation list.in size of 4 bytes. stride is 64KB" hexmask.long 0x4 0.--31. 1. "Reserved_22,Reserved_22" group.long 0x2C8++0x7 line.long 0x0 "RGX_CR_PM_MLIST1_START_OF_0,start of the tail pointer of mmu allocation list.effecitve on an allocation_list_load" hexmask.long.word 0x0 22.--31. 1. "Reserved_22,Reserved_22" newline hexmask.long.tbyte 0x0 0.--21. 1. "TAIL,start of the allocation list 1 tail pointer" line.long 0x4 "RGX_CR_PM_MLIST1_START_OF_1,start of the tail pointer of mmu allocation list.effecitve on an allocation_list_load" hexmask.long 0x4 0.--31. 1. "Reserved_22,Reserved_22" rgroup.long 0x2D0++0x7 line.long 0x0 "RGX_CR_PM_MLIST1_STATUS_0,pointer of mmu allocation list1 pointer.in size of 4 bytes" hexmask.long.word 0x0 22.--31. 1. "Reserved_22,Reserved_22" newline hexmask.long.tbyte 0x0 0.--21. 1. "TAIL,mmu allocation List 1 tail pointer" line.long 0x4 "RGX_CR_PM_MLIST1_STATUS_1,pointer of mmu allocation list1 pointer.in size of 4 bytes" hexmask.long 0x4 0.--31. 1. "Reserved_22,Reserved_22" group.long 0x2D8++0xF line.long 0x0 "RGX_CR_PM_MLIST0_BASE_0,This register defines the base address of the mmu list 0 for the mmu pages. the stride has to be 64KBytes" hexmask.long 0x0 4.--31. 1. "ADDR,1TB Addressable 128 bits aligned Base Address for mmu list0 module Effective Immediately" newline hexmask.long.byte 0x0 0.--3. 1. "Reserved_0,Reserved_0" line.long 0x4 "RGX_CR_PM_MLIST0_BASE_1,This register defines the base address of the mmu list 0 for the mmu pages. the stride has to be 64KBytes" hexmask.long.tbyte 0x4 8.--31. 1. "Reserved_40,Reserved_40" newline hexmask.long.byte 0x4 0.--7. 1. "ADDR,1TB Addressable 128 bits aligned Base Address for mmu list0 module Effective Immediately" line.long 0x8 "RGX_CR_PM_MLIST1_BASE_0,This register defines the base address of the mmu list 1 for the mmu pages. the stride has to be a 64KBytes" hexmask.long 0x8 4.--31. 1. "ADDR,1TB Addressable 128 bits aligned Base Address for mmu list1 module Effective Immediately" newline hexmask.long.byte 0x8 0.--3. 1. "Reserved_0,Reserved_0" line.long 0xC "RGX_CR_PM_MLIST1_BASE_1,This register defines the base address of the mmu list 1 for the mmu pages. the stride has to be a 64KBytes" hexmask.long.tbyte 0xC 8.--31. 1. "Reserved_40,Reserved_40" newline hexmask.long.byte 0xC 0.--7. 1. "ADDR,1TB Addressable 128 bits aligned Base Address for mmu list1 module Effective Immediately" rgroup.long 0x2F8++0x27 line.long 0x0 "RGX_CR_PM_VCE_VTOP_STATUS_0,RGX_CR_PM_VCE_VTOP_STATUS_0" hexmask.long.word 0x0 20.--31. 1. "Reserved_20,Reserved_20" newline hexmask.long.tbyte 0x0 0.--19. 1. "OP,Virtual Page Pointer for the VCE 16KB granauality" line.long 0x4 "RGX_CR_PM_VCE_VTOP_STATUS_1,RGX_CR_PM_VCE_VTOP_STATUS_1" hexmask.long 0x4 0.--31. 1. "Reserved_20,Reserved_20" line.long 0x8 "RGX_CR_PM_TE_VTOP_STATUS_0,RGX_CR_PM_TE_VTOP_STATUS_0" hexmask.long.word 0x8 20.--31. 1. "Reserved_20,Reserved_20" newline hexmask.long.tbyte 0x8 0.--19. 1. "OP,Virtual Page Pointer for the TE 16KB granauality" line.long 0xC "RGX_CR_PM_TE_VTOP_STATUS_1,RGX_CR_PM_TE_VTOP_STATUS_1" hexmask.long 0xC 0.--31. 1. "Reserved_20,Reserved_20" line.long 0x10 "RGX_CR_PM_OUTOF_MEM_SRC_0,RGX_CR_PM_OUTOF_MEM_SRC_0" hexmask.long 0x10 3.--31. 1. "Reserved_3,Reserved_3" newline bitfld.long 0x10 0.--2. "OP,one hot encoding indicating which part of resource runs out of memory bit 0: normal ta free list bit 1: unified ta free list bit 2: mmu free list" "normal ta free list,unified ta free list,mmu free list,?,?,?,?,?" line.long 0x14 "RGX_CR_PM_OUTOF_MEM_SRC_1,RGX_CR_PM_OUTOF_MEM_SRC_1" hexmask.long 0x14 0.--31. 1. "Reserved_3,Reserved_3" line.long 0x18 "RGX_CR_PM_ALIST_VTOP_STATUS_0,RGX_CR_PM_ALIST_VTOP_STATUS_0" hexmask.long.word 0x18 20.--31. 1. "Reserved_20,Reserved_20" newline hexmask.long.tbyte 0x18 0.--19. 1. "OP,Virtual Page Pointer for the allocation list 16KB granauality" line.long 0x1C "RGX_CR_PM_ALIST_VTOP_STATUS_1,RGX_CR_PM_ALIST_VTOP_STATUS_1" hexmask.long 0x1C 0.--31. 1. "Reserved_20,Reserved_20" line.long 0x20 "RGX_CR_PM_MMU_VTOP_STATUS_0,RGX_CR_PM_MMU_VTOP_STATUS_0" hexmask.long.word 0x20 20.--31. 1. "Reserved_20,Reserved_20" newline hexmask.long.tbyte 0x20 0.--19. 1. "OP,Virtual Page Pointer for the MMU 4KB granauality" line.long 0x24 "RGX_CR_PM_MMU_VTOP_STATUS_1,RGX_CR_PM_MMU_VTOP_STATUS_1" hexmask.long 0x24 0.--31. 1. "Reserved_20,Reserved_20" wgroup.long 0x320++0xF line.long 0x0 "RGX_CR_PM_OUTOFMEM_ABORTALL_0,RGX_CR_PM_OUTOFMEM_ABORTALL_0" hexmask.long 0x0 1.--31. 1. "Reserved_1,Reserved_1" newline bitfld.long 0x0 0. "OP,Instruct the PM to Deny the TE allocation outstanding on Out Of Memory" "0,1" line.long 0x4 "RGX_CR_PM_OUTOFMEM_ABORTALL_1,RGX_CR_PM_OUTOFMEM_ABORTALL_1" hexmask.long 0x4 0.--31. 1. "Reserved_1,Reserved_1" line.long 0x8 "RGX_CR_PM_OUTOFMEM_RESTART_0,RGX_CR_PM_OUTOFMEM_RESTART_0" hexmask.long 0x8 1.--31. 1. "Reserved_1,Reserved_1" newline bitfld.long 0x8 0. "OP,Restart the PM after an Out of Memory and Abort sequence" "0,1" line.long 0xC "RGX_CR_PM_OUTOFMEM_RESTART_1,RGX_CR_PM_OUTOFMEM_RESTART_1" hexmask.long 0xC 0.--31. 1. "Reserved_1,Reserved_1" rgroup.long 0x330++0x7 line.long 0x0 "RGX_CR_PM_REQUESTING_SOURCE_0,RGX_CR_PM_REQUESTING_SOURCE_0" hexmask.long 0x0 2.--31. 1. "Reserved_2,Reserved_2" newline bitfld.long 0x0 0.--1. "OP,Requesting source when out of memory. Bit 1 : VCE Bit 0 : TE" "TE,VCE,?,?" line.long 0x4 "RGX_CR_PM_REQUESTING_SOURCE_1,RGX_CR_PM_REQUESTING_SOURCE_1" hexmask.long 0x4 0.--31. 1. "Reserved_2,Reserved_2" group.long 0x338++0xF line.long 0x0 "RGX_CR_PM_PARTIAL_RENDER_ENABLE_0,RGX_CR_PM_PARTIAL_RENDER_ENABLE_0" hexmask.long 0x0 1.--31. 1. "Reserved_1,Reserved_1" newline bitfld.long 0x0 0. "OP,Partial Render Enable Bit" "0,1" line.long 0x4 "RGX_CR_PM_PARTIAL_RENDER_ENABLE_1,RGX_CR_PM_PARTIAL_RENDER_ENABLE_1" hexmask.long 0x4 0.--31. 1. "Reserved_1,Reserved_1" line.long 0x8 "RGX_CR_PM_3D_DEALLOCATE_SCANMODE_0,RGX_CR_PM_3D_DEALLOCATE_SCANMODE_0" hexmask.long 0x8 5.--31. 1. "Reserved_5,Reserved_5" newline hexmask.long.byte 0x8 0.--4. 1. "OP,This register defines the deallocation behaviour of the PM: value > 2 is only for debug on ZLS mode 0 it can only set less than 2 0: PM will free the macrotile memory as soon as it is possible 1: PM only free one mtile for each traverse 2: PM only.." line.long 0xC "RGX_CR_PM_3D_DEALLOCATE_SCANMODE_1,RGX_CR_PM_3D_DEALLOCATE_SCANMODE_1" hexmask.long 0xC 0.--31. 1. "Reserved_5,Reserved_5" rgroup.long 0x348++0xF line.long 0x0 "RGX_CR_PM_TA_FSTACK_STATUS_0,Note: this is the pointer pointing to the TA free stack top. (4KB page pointer)" hexmask.long.word 0x0 22.--31. 1. "Reserved_22,Reserved_22" newline hexmask.long.tbyte 0x0 0.--21. 1. "TOP,This status register indicated the ta context free list pointer status." line.long 0x4 "RGX_CR_PM_TA_FSTACK_STATUS_1,Note: this is the pointer pointing to the TA free stack top. (4KB page pointer)" hexmask.long 0x4 0.--31. 1. "Reserved_22,Reserved_22" line.long 0x8 "RGX_CR_PM_3D_FSTACK_STATUS_0,Note: this is the pointer pointing to the 3D free stack top. (4KB page pointer)" hexmask.long.word 0x8 22.--31. 1. "Reserved_22,Reserved_22" newline hexmask.long.tbyte 0x8 0.--21. 1. "TOP,This status register indicated the 3D context free list status" line.long 0xC "RGX_CR_PM_3D_FSTACK_STATUS_1,Note: this is the pointer pointing to the 3D free stack top. (4KB page pointer)" hexmask.long 0xC 0.--31. 1. "Reserved_22,Reserved_22" group.long 0x358++0x7 line.long 0x0 "RGX_CR_PM_RESERVE_PAGES_0,RGX_CR_PM_RESERVE_PAGES_0" hexmask.long.word 0x0 16.--31. 1. "Reserved_16,Reserved_16" newline hexmask.long.word 0x0 0.--15. 1. "OP,This register defines the guard page required for one VCE/TE allocation. The requirement is set by the number of ppages needed to create the ALIST nodes when a vpage is closed. The MMU requirement is fixed at 3 ppages max for creatig a new ALIST.." line.long 0x4 "RGX_CR_PM_RESERVE_PAGES_1,RGX_CR_PM_RESERVE_PAGES_1" hexmask.long 0x4 0.--31. 1. "Reserved_16,Reserved_16" rgroup.long 0x360++0x17 line.long 0x0 "RGX_CR_PM_DEALLOCATED_MASK_STATUS_0,RGX_CR_PM_DEALLOCATED_MASK_STATUS_0" hexmask.long.word 0x0 16.--31. 1. "Reserved_16,Reserved_16" newline hexmask.long.word 0x0 0.--15. 1. "TOP,This status register contains a bitmask of the macrotiles freed at this point in the render" line.long 0x4 "RGX_CR_PM_DEALLOCATED_MASK_STATUS_1,RGX_CR_PM_DEALLOCATED_MASK_STATUS_1" hexmask.long 0x4 0.--31. 1. "Reserved_16,Reserved_16" line.long 0x8 "RGX_CR_PM_DEALLOCATING_MASK_STATUS_0,RGX_CR_PM_DEALLOCATING_MASK_STATUS_0" hexmask.long.word 0x8 16.--31. 1. "Reserved_16,Reserved_16" newline hexmask.long.word 0x8 0.--15. 1. "TOP,This status register indicates the mtile mask being freed at the current traverse" line.long 0xC "RGX_CR_PM_DEALLOCATING_MASK_STATUS_1,RGX_CR_PM_DEALLOCATING_MASK_STATUS_1" hexmask.long 0xC 0.--31. 1. "Reserved_16,Reserved_16" line.long 0x10 "RGX_CR_PM_PDS_MTILEFREE_STATUS_0,RGX_CR_PM_PDS_MTILEFREE_STATUS_0" hexmask.long.word 0x10 17.--31. 1. "Reserved_17,Reserved_17" newline hexmask.long.tbyte 0x10 0.--16. 1. "OP,This status register indicates the macrotile number of the PDSs current macrotile free request" line.long 0x14 "RGX_CR_PM_PDS_MTILEFREE_STATUS_1,RGX_CR_PM_PDS_MTILEFREE_STATUS_1" hexmask.long 0x14 0.--31. 1. "Reserved_17,Reserved_17" group.long 0x378++0x7 line.long 0x0 "RGX_CR_PM_TA_FREE_CONTEXT_0,RGX_CR_PM_TA_FREE_CONTEXT_0" hexmask.long 0x0 1.--31. 1. "Reserved_1,Reserved_1" newline bitfld.long 0x0 0. "PENDING,free the ta context register operation" "0,1" line.long 0x4 "RGX_CR_PM_TA_FREE_CONTEXT_1,RGX_CR_PM_TA_FREE_CONTEXT_1" hexmask.long 0x4 0.--31. 1. "Reserved_1,Reserved_1" wgroup.long 0x380++0x7 line.long 0x0 "RGX_CR_PM_3D_TIMEOUT_NOW_0,RGX_CR_PM_3D_TIMEOUT_NOW_0" hexmask.long 0x0 1.--31. 1. "Reserved_1,Reserved_1" newline bitfld.long 0x0 0. "OP,free the 3D context" "0,1" line.long 0x4 "RGX_CR_PM_3D_TIMEOUT_NOW_1,RGX_CR_PM_3D_TIMEOUT_NOW_1" hexmask.long 0x4 0.--31. 1. "Reserved_1,Reserved_1" group.long 0x388++0x7 line.long 0x0 "RGX_CR_PM_3D_DEALLOCATE_ENABLE_0,RGX_CR_PM_3D_DEALLOCATE_ENABLE_0" hexmask.long 0x0 1.--31. 1. "Reserved_1,Reserved_1" newline bitfld.long 0x0 0. "OP,3D deallocate enable mode" "0,1" line.long 0x4 "RGX_CR_PM_3D_DEALLOCATE_ENABLE_1,RGX_CR_PM_3D_DEALLOCATE_ENABLE_1" hexmask.long 0x4 0.--31. 1. "Reserved_1,Reserved_1" repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) group.long ($2+0x390)++0x3 line.long 0x0 "RGX_CR_PM_START_OF_TACONTEXT_$1,RGX_CR_PM_START_OF_TACONTEXT_0" hexmask.long.word 0x0 22.--31. 1. "Reserved_22,Reserved_22" newline hexmask.long.tbyte 0x0 0.--21. 1. "ALLOCATED_PAGE,Start of TA pages(4KB) on loading of the TA context" repeat.end repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) group.long ($2+0x398)++0x3 line.long 0x0 "RGX_CR_PM_START_OF_3DCONTEXT_$1,RGX_CR_PM_START_OF_3DCONTEXT_0" hexmask.long.word 0x0 22.--31. 1. "Reserved_22,Reserved_22" newline hexmask.long.tbyte 0x0 0.--21. 1. "ALLOCATED_PAGE,Start of 3D pages(4KB) on loading of the TA context" repeat.end rgroup.long 0x3A0++0x2F line.long 0x0 "RGX_CR_PM_TA_PAGE_STATUS_0,RGX_CR_PM_TA_PAGE_STATUS_0" hexmask.long.word 0x0 22.--31. 1. "Reserved_22,Reserved_22" newline hexmask.long.tbyte 0x0 0.--21. 1. "OP,The number of TA pages currently allocated" line.long 0x4 "RGX_CR_PM_TA_PAGE_STATUS_1,RGX_CR_PM_TA_PAGE_STATUS_1" hexmask.long 0x4 0.--31. 1. "Reserved_22,Reserved_22" line.long 0x8 "RGX_CR_PM_3D_PAGE_STATUS_0,RGX_CR_PM_3D_PAGE_STATUS_0" hexmask.long.word 0x8 22.--31. 1. "Reserved_22,Reserved_22" newline hexmask.long.tbyte 0x8 0.--21. 1. "OP,The number of 3D pages currently allocated" line.long 0xC "RGX_CR_PM_3D_PAGE_STATUS_1,RGX_CR_PM_3D_PAGE_STATUS_1" hexmask.long 0xC 0.--31. 1. "Reserved_22,Reserved_22" line.long 0x10 "RGX_CR_PM_VCE_INFLIGHT_STATUS_0,RGX_CR_PM_VCE_INFLIGHT_STATUS_0" hexmask.long.word 0x10 20.--31. 1. "Reserved_20,Reserved_20" newline hexmask.long.tbyte 0x10 0.--19. 1. "OP,The Virtual Page Number in flight in the VCE Requestor" line.long 0x14 "RGX_CR_PM_VCE_INFLIGHT_STATUS_1,RGX_CR_PM_VCE_INFLIGHT_STATUS_1" hexmask.long 0x14 0.--31. 1. "Reserved_20,Reserved_20" line.long 0x18 "RGX_CR_PM_TE_INFLIGHT_STATUS_0,RGX_CR_PM_TE_INFLIGHT_STATUS_0" hexmask.long.word 0x18 20.--31. 1. "Reserved_20,Reserved_20" newline hexmask.long.tbyte 0x18 0.--19. 1. "OP,The Virtual Page Number in flight in the TE Requestor" line.long 0x1C "RGX_CR_PM_TE_INFLIGHT_STATUS_1,RGX_CR_PM_TE_INFLIGHT_STATUS_1" hexmask.long 0x1C 0.--31. 1. "Reserved_20,Reserved_20" line.long 0x20 "RGX_CR_BIFPM_IDLE_0,RGX_CR_BIFPM_IDLE_0" hexmask.long 0x20 7.--31. 1. "Reserved_7,Reserved_7" newline bitfld.long 0x20 6. "MCU_L0_MEMIF,MCU L0 MEMIF Module IDLE" "0,1" newline bitfld.long 0x20 5. "PBE,PBE Module IDLE" "0,1" newline bitfld.long 0x20 4. "MCU_L0_PDSRW,MCU L0 PDSRW Module IDLE" "0,1" newline bitfld.long 0x20 3. "MCU_L1,MCU L1 Module IDLE" "0,1" newline bitfld.long 0x20 2. "USCS,USC Shared Module IDLE" "0,1" newline bitfld.long 0x20 1. "PM,PM Module IDLE" "0,1" newline bitfld.long 0x20 0. "BIF256,BIF256 Module IDLE" "0,1" line.long 0x24 "RGX_CR_BIFPM_IDLE_1,RGX_CR_BIFPM_IDLE_1" hexmask.long 0x24 0.--31. 1. "Reserved_7,Reserved_7" line.long 0x28 "RGX_CR_SIDEKICK_IDLE_0,RGX_CR_SIDEKICK_IDLE_0" hexmask.long 0x28 7.--31. 1. "Reserved_7,Reserved_7" newline bitfld.long 0x28 6. "FB_CDC,FB CDC Module IDLE" "0,1" newline bitfld.long 0x28 5. "MMU,MMU Module IDLE" "0,1" newline bitfld.long 0x28 4. "BIF128,BIF128 Module IDLE" "0,1" newline bitfld.long 0x28 3. "TLA,TLA Module IDLE" "0,1" newline bitfld.long 0x28 2. "GARTEN,GARTEN Module IDLE" "0,1" newline bitfld.long 0x28 1. "HOSTIF,HOSTIF Module IDLE" "0,1" newline bitfld.long 0x28 0. "SOCIF,SOCIF Module IDLE" "0,1" line.long 0x2C "RGX_CR_SIDEKICK_IDLE_1,RGX_CR_SIDEKICK_IDLE_1" hexmask.long 0x2C 0.--31. 1. "Reserved_7,Reserved_7" group.long 0x3D0++0x17 line.long 0x0 "RGX_CR_PM_CONTEXT_ID_0,RGX_CR_PM_CONTEXT_ID_0" hexmask.long.byte 0x0 25.--31. 1. "Reserved_25,Reserved_25" newline bitfld.long 0x0 24. "MLIS_ALLOC,MMU page List (TE VCE aligned with this context )Allocation Context ID" "0,1" newline hexmask.long.byte 0x0 17.--23. 1. "Reserved_17,Reserved_17" newline bitfld.long 0x0 16. "LS,Load Store Context ID for the allocation list" "0,1" newline hexmask.long.byte 0x0 9.--15. 1. "Reserved_9,Reserved_9" newline bitfld.long 0x0 8. "DALLOC,DeAllocation Context ID for the allocation list" "0,1" newline hexmask.long.byte 0x0 1.--7. 1. "Reserved_1,Reserved_1" newline bitfld.long 0x0 0. "ALLOC,Allocation Context ID for the allocation list" "0,1" line.long 0x4 "RGX_CR_PM_CONTEXT_ID_1,RGX_CR_PM_CONTEXT_ID_1" hexmask.long.tbyte 0x4 9.--31. 1. "Reserved_41,Reserved_41" newline bitfld.long 0x4 8. "MLIS_LS,MMU page List (TE VCE aligned with this context )Load Store Context ID" "0,1" newline hexmask.long.byte 0x4 1.--7. 1. "Reserved_33,Reserved_33" newline bitfld.long 0x4 0. "MLIS_DALLOC,MMU page List (TE VCE aligned with this context )DeAllocation Context ID" "0,1" line.long 0x8 "RGX_CR_PM_3D_RENDER_TARGET_INDEX_0,RGX_CR_PM_3D_RENDER_TARGET_INDEX_0" hexmask.long.tbyte 0x8 11.--31. 1. "Reserved_11,Reserved_11" newline hexmask.long.word 0x8 0.--10. 1. "ID,Render Target ID which is being rendered" line.long 0xC "RGX_CR_PM_3D_RENDER_TARGET_INDEX_1,RGX_CR_PM_3D_RENDER_TARGET_INDEX_1" hexmask.long 0xC 0.--31. 1. "Reserved_11,Reserved_11" line.long 0x10 "RGX_CR_PM_3D_RENDER_TARGET_LAST_0,RGX_CR_PM_3D_RENDER_TARGET_LAST_0" hexmask.long 0x10 1.--31. 1. "Reserved_1,Reserved_1" newline bitfld.long 0x10 0. "ID,If this bit is set this means the render will be the last one in the whole render target array. If no multiple render target array is present this bit always needs set" "0,1" line.long 0x14 "RGX_CR_PM_3D_RENDER_TARGET_LAST_1,RGX_CR_PM_3D_RENDER_TARGET_LAST_1" hexmask.long 0x14 0.--31. 1. "Reserved_1,Reserved_1" rgroup.long 0x3E8++0x17 line.long 0x0 "RGX_CR_PM_LOCK_STATUS_0,RGX_CR_PM_LOCK_STATUS_0" hexmask.long 0x0 2.--31. 1. "Reserved_2,Reserved_2" newline bitfld.long 0x0 1. "TD,Bit 1: 3D free list Lock Status. 0 idle/ 1 used" "0,1" newline bitfld.long 0x0 0. "TA,Bit 0: TA free list Lock Status. 0 idle/ 1 used." "TA free list Lock Status,?" line.long 0x4 "RGX_CR_PM_LOCK_STATUS_1,RGX_CR_PM_LOCK_STATUS_1" hexmask.long 0x4 0.--31. 1. "Reserved_2,Reserved_2" line.long 0x8 "RGX_CR_PM_LOCK_OWNER_0,RGX_CR_PM_LOCK_OWNER_0" hexmask.long 0x8 2.--31. 1. "Reserved_2,Reserved_2" newline bitfld.long 0x8 1. "TD,Bit 1 :3D free list Lock owner. 0 PMA / 1 PMD" "0,1" newline bitfld.long 0x8 0. "TA,Bit 0: TA free list Lock Owner. 0 PMA / 1 PMD." "TA free list Lock Owner,?" line.long 0xC "RGX_CR_PM_LOCK_OWNER_1,RGX_CR_PM_LOCK_OWNER_1" hexmask.long 0xC 0.--31. 1. "Reserved_2,Reserved_2" line.long 0x10 "RGX_CR_PM_IDLE_STATUS_0,RGX_CR_PM_IDLE_STATUS_0" hexmask.long.tbyte 0x10 8.--31. 1. "Reserved_8,Reserved_8" newline bitfld.long 0x10 7. "PMD_BIF,Idle Status Register of the PMD module bif state machine" "0,1" newline bitfld.long 0x10 6. "PMD_FRE,Idle Status Register of the PMD module master state machine" "0,1" newline bitfld.long 0x10 5. "BIF,Idle Status Register of the BIF Interface default" "0,1" newline bitfld.long 0x10 4. "BARB,Idle Status Register of the BIF Arbiter state BAR" "0,1" newline bitfld.long 0x10 3. "AMAN,Idle Status Register of the Alist state machine" "0,1" newline bitfld.long 0x10 2. "STA,Idle Status Register of the Stack Manager Modul" "0,1" newline bitfld.long 0x10 1. "PMD,Idle Status Register of the PMD module" "0,1" newline bitfld.long 0x10 0. "PMA,Idle Status Register of the PMA module" "0,1" line.long 0x14 "RGX_CR_PM_IDLE_STATUS_1,RGX_CR_PM_IDLE_STATUS_1" hexmask.long 0x14 0.--31. 1. "Reserved_8,Reserved_8" wgroup.long 0x400++0x7 line.long 0x0 "RGX_CR_VDM_START_0,A write of '1' to this register starts the Vertex Data Master (TA) Reading the control stream pointed to by VDM_CTRL_STREAM_BASE" hexmask.long 0x0 1.--31. 1. "Reserved_1,Reserved_1" newline bitfld.long 0x0 0. "PULSE,Start VDM" "0,1" line.long 0x4 "RGX_CR_VDM_START_1,A write of '1' to this register starts the Vertex Data Master (TA) Reading the control stream pointed to by VDM_CTRL_STREAM_BASE" hexmask.long 0x4 0.--31. 1. "Reserved_1,Reserved_1" group.long 0x408++0x7 line.long 0x0 "RGX_CR_VDM_CTRL_STREAM_BASE_0,The base address of the Vertex Data Master's Input Parameter Control Stream in external memory" hexmask.long 0x0 2.--31. 1. "ADDR,1TB range 32-bit aligned base address" newline bitfld.long 0x0 0.--1. "Reserved_0,Reserved_0" "0,1,2,3" line.long 0x4 "RGX_CR_VDM_CTRL_STREAM_BASE_1,The base address of the Vertex Data Master's Input Parameter Control Stream in external memory" hexmask.long.tbyte 0x4 8.--31. 1. "Reserved_40,Reserved_40" newline hexmask.long.byte 0x4 0.--7. 1. "ADDR,1TB range 32-bit aligned base address" rgroup.long 0x410++0x7 line.long 0x0 "RGX_CR_VDM_CTRL_STREAM_CURRENT_0,This status register reports the current position in the input parameter format of the data being processed. This is a debug register. This is NOT the fetch address presented to the BIF. which is reading ahead Since the.." hexmask.long 0x0 2.--31. 1. "ADDR,1TB range 32-bit aligned address" newline bitfld.long 0x0 0.--1. "Reserved_0,Reserved_0" "0,1,2,3" line.long 0x4 "RGX_CR_VDM_CTRL_STREAM_CURRENT_1,This status register reports the current position in the input parameter format of the data being processed. This is a debug register. This is NOT the fetch address presented to the BIF. which is reading ahead Since the.." hexmask.long.tbyte 0x4 8.--31. 1. "Reserved_40,Reserved_40" newline hexmask.long.byte 0x4 0.--7. 1. "ADDR,1TB range 32-bit aligned address" group.long 0x418++0x17 line.long 0x0 "RGX_CR_VDM_CALL_STACK_POINTER_0,The pointer to the control stream call stack. The current pointer within the VDM's call stack in external memory. The call stack is used whenever a call is made to another control stream. to store the return address.." hexmask.long 0x0 3.--31. 1. "ADDR,1TB range 64-bit aligned base address" newline bitfld.long 0x0 0.--2. "Reserved_0,Reserved_0" "0,1,2,3,4,5,6,7" line.long 0x4 "RGX_CR_VDM_CALL_STACK_POINTER_1,The pointer to the control stream call stack. The current pointer within the VDM's call stack in external memory. The call stack is used whenever a call is made to another control stream. to store the return address.." hexmask.long.tbyte 0x4 8.--31. 1. "Reserved_40,Reserved_40" newline hexmask.long.byte 0x4 0.--7. 1. "ADDR,1TB range 64-bit aligned base address" line.long 0x8 "RGX_CR_VDM_BATCH_0,The Batch number is a index list block (draw call) ID which is passed through the GPU pipeline. This is helpful for debug and performance profiling. The starting batch number should be programmed before the first TA phase of every.." hexmask.long.tbyte 0x8 14.--31. 1. "Reserved_14,Reserved_14" newline hexmask.long.word 0x8 0.--13. 1. "NUMBER,NUMBER" line.long 0xC "RGX_CR_VDM_BATCH_1,The Batch number is a index list block (draw call) ID which is passed through the GPU pipeline. This is helpful for debug and performance profiling. The starting batch number should be programmed before the first TA phase of every.." hexmask.long 0xC 0.--31. 1. "Reserved_14,Reserved_14" line.long 0x10 "RGX_CR_VDM_CONTEXT_STATE_BASE_0,The base address in external memory of the VDM's context state buffer. On a context store the VDM will store its state to this address. and reload it on a context resume. The size and format of the data written is defined.." hexmask.long 0x10 4.--31. 1. "ADDR,1TB range 128-bit aligned base address" newline hexmask.long.byte 0x10 0.--3. 1. "Reserved_0,Reserved_0" line.long 0x14 "RGX_CR_VDM_CONTEXT_STATE_BASE_1,The base address in external memory of the VDM's context state buffer. On a context store the VDM will store its state to this address. and reload it on a context resume. The size and format of the data written is defined.." hexmask.long.tbyte 0x14 8.--31. 1. "Reserved_40,Reserved_40" newline hexmask.long.byte 0x14 0.--7. 1. "ADDR,1TB range 128-bit aligned base address" rgroup.long 0x430++0x7 line.long 0x0 "RGX_CR_VDM_CONTEXT_STORE_STATUS_0,This register indicates the status of a VDM context switch operation. If a context store has been requested. then this muist be sample on TA finished. The firmware must wait for the COMPLETE bit to be set. The.." hexmask.long.tbyte 0x0 8.--31. 1. "Reserved_8,Reserved_8" newline hexmask.long.byte 0x0 4.--7. 1. "LAST_PIPE,The TA pipe number to which the VDM last sent indices" newline bitfld.long 0x0 2.--3. "Reserved_2,Reserved_2" "0,1,2,3" newline bitfld.long 0x0 1. "NEED_RESUME,The VDM still has control stream left to process meaning this context must be resumed" "0,1" newline bitfld.long 0x0 0. "COMPLETE,The VDM has completed the context store operation and fenced its state to external memory" "0,1" line.long 0x4 "RGX_CR_VDM_CONTEXT_STORE_STATUS_1,This register indicates the status of a VDM context switch operation. If a context store has been requested. then this muist be sample on TA finished. The firmware must wait for the COMPLETE bit to be set. The.." hexmask.long 0x4 0.--31. 1. "Reserved_8,Reserved_8" repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) group.long ($2+0x438)++0x3 line.long 0x0 "RGX_CR_VDM_CONTEXT_STORE_TASK0_$1,These words define the PDS State Update task which will be inserted into the VDM pipeline on a context store operation. The function of this task is described in the Rogue Context Switching Hardware Specification. Their.." hexmask.long 0x0 0.--31. 1. "PDS_STATE0,PDS_STATE0" repeat.end repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) group.long ($2+0x440)++0x3 line.long 0x0 "RGX_CR_VDM_CONTEXT_STORE_TASK1_$1,This word defines the PDS State Update task which will be inserted into the VDM pipeline on a context store operation. The function of this task is described in the Rogue Context Switching Hardware Specification. Its.." hexmask.long 0x0 0.--31. 1. "PDS_STATE2,PDS_STATE2" repeat.end repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) group.long ($2+0x448)++0x3 line.long 0x0 "RGX_CR_VDM_CONTEXT_STORE_TASK2_$1,These words defines the Stream Out Sync program which will be inserted into the VDM pipeline as a PPP State Update on a context store operation. The function of this task is described in the Rogue Context Switching.." hexmask.long 0x0 0.--31. 1. "STREAM_OUT1,STREAM_OUT1" repeat.end repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) group.long ($2+0x450)++0x3 line.long 0x0 "RGX_CR_VDM_CONTEXT_RESUME_TASK0_$1,These words define the PDS State Update task which will be written by the VDM to its context resume control stream on a context store operation. The function of this task is described in the Rogue Context Switching.." hexmask.long 0x0 0.--31. 1. "PDS_STATE0,PDS_STATE0" repeat.end repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) group.long ($2+0x458)++0x3 line.long 0x0 "RGX_CR_VDM_CONTEXT_RESUME_TASK1_$1,This word defines the PDS State Update task which will be written by the VDM to its context resume control stream on a context store operation. The function of this task is described in the Rogue Context Switching.." hexmask.long 0x0 0.--31. 1. "PDS_STATE2,PDS_STATE2" repeat.end repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) group.long ($2+0x460)++0x3 line.long 0x0 "RGX_CR_VDM_CONTEXT_RESUME_TASK2_$1,These words defines the Stream Out Sync program which will be written. as a PPP State Update. by the VDM to its context resume control stream on a context store operation The function of this task is described in the.." hexmask.long 0x0 0.--31. 1. "STREAM_OUT1,STREAM_OUT1" repeat.end wgroup.long 0x468++0x7 line.long 0x0 "RGX_CR_VDM_CONTEXT_STORE_START_0,Writing '1' to this register starts the VDM context store operation. The function of this task is described in the Rogue Context Switching Hardware Specifiction" hexmask.long 0x0 1.--31. 1. "Reserved_1,Reserved_1" newline bitfld.long 0x0 0. "PULSE,PULSE" "0,1" line.long 0x4 "RGX_CR_VDM_CONTEXT_STORE_START_1,Writing '1' to this register starts the VDM context store operation. The function of this task is described in the Rogue Context Switching Hardware Specifiction" hexmask.long 0x4 0.--31. 1. "Reserved_1,Reserved_1" group.long 0x470++0x7 line.long 0x0 "RGX_CR_VDM_SYNC_PDS_DATA_BASE_0,The base address of the PDS data segment base for all TA state sync program 4GB range. 128-bit granularity The data segment size is always 256 bits The PDS code address for the TA state sync program is always 256 bits on.." hexmask.long 0x0 4.--31. 1. "ADDR,ADDR" newline hexmask.long.byte 0x0 0.--3. 1. "Reserved_0,Reserved_0" line.long 0x4 "RGX_CR_VDM_SYNC_PDS_DATA_BASE_1,The base address of the PDS data segment base for all TA state sync program 4GB range. 128-bit granularity The data segment size is always 256 bits The PDS code address for the TA state sync program is always 256 bits on.." hexmask.long 0x4 0.--31. 1. "Reserved_32,Reserved_32" wgroup.long 0x478++0x7 line.long 0x0 "RGX_CR_CDM_START_0,A write of '1' to this register starts the Compute Data Master reading it's control stream from memory." hexmask.long 0x0 1.--31. 1. "Reserved_1,Reserved_1" newline bitfld.long 0x0 0. "PULSE,Start CDM" "0,1" line.long 0x4 "RGX_CR_CDM_START_1,A write of '1' to this register starts the Compute Data Master reading it's control stream from memory." hexmask.long 0x4 0.--31. 1. "Reserved_1,Reserved_1" group.long 0x480++0x7 line.long 0x0 "RGX_CR_CDM_CTRL_STREAM_BASE_0,The base address of the Compute Data Master's Input Parameter Control Stream in external memory" hexmask.long 0x0 2.--31. 1. "ADDR,1TB range 32-bit aligned base address" newline bitfld.long 0x0 0.--1. "Reserved_0,Reserved_0" "0,1,2,3" line.long 0x4 "RGX_CR_CDM_CTRL_STREAM_BASE_1,The base address of the Compute Data Master's Input Parameter Control Stream in external memory" hexmask.long.tbyte 0x4 8.--31. 1. "Reserved_40,Reserved_40" newline hexmask.long.byte 0x4 0.--7. 1. "ADDR,1TB range 32-bit aligned base address" wgroup.long 0x488++0x7 line.long 0x0 "RGX_CR_CDM_CONTEXT_STORE_0,Writing '1' to this register starts the CDM context store operation." hexmask.long 0x0 1.--31. 1. "Reserved_1,Reserved_1" newline bitfld.long 0x0 0. "PULSE,PULSE" "0,1" line.long 0x4 "RGX_CR_CDM_CONTEXT_STORE_1,Writing '1' to this register starts the CDM context store operation." hexmask.long 0x4 0.--31. 1. "Reserved_1,Reserved_1" group.long 0x490++0xF line.long 0x0 "RGX_CR_CDM_CONTEXT_LOAD_0,The firmware writes a '1' to this register starts the CDM context load operation. The CDM will set this register to '0' when the context load operation is complete The firmware should poll on this register after writing to it" hexmask.long 0x0 1.--31. 1. "Reserved_1,Reserved_1" newline bitfld.long 0x0 0. "PENDING,PENDING" "0,1" line.long 0x4 "RGX_CR_CDM_CONTEXT_LOAD_1,The firmware writes a '1' to this register starts the CDM context load operation. The CDM will set this register to '0' when the context load operation is complete The firmware should poll on this register after writing to it" hexmask.long 0x4 0.--31. 1. "Reserved_1,Reserved_1" line.long 0x8 "RGX_CR_CDM_CONTEXT_STATE_BASE_0,The base address in external memory of the CDM's context state buffer. to which it will store its snapshot state on a context store and from which it will reload on a context resume" hexmask.long 0x8 4.--31. 1. "ADDR,1TB range 128-bit aligned base address" newline hexmask.long.byte 0x8 0.--3. 1. "Reserved_0,Reserved_0" line.long 0xC "RGX_CR_CDM_CONTEXT_STATE_BASE_1,The base address in external memory of the CDM's context state buffer. to which it will store its snapshot state on a context store and from which it will reload on a context resume" hexmask.long.tbyte 0xC 8.--31. 1. "Reserved_40,Reserved_40" newline hexmask.long.byte 0xC 0.--7. 1. "ADDR,1TB range 128-bit aligned base address" rgroup.long 0x4A0++0x7 line.long 0x0 "RGX_CR_CDM_CONTEXT_STORE_STATUS_0,This register indicates the status of a CDM context switch operation. If a context store is in progress. this register must be sampled on a context store compute finished event. The firmware must wait for the COMPLETE.." hexmask.long 0x0 2.--31. 1. "Reserved_2,Reserved_2" newline bitfld.long 0x0 1. "NEED_RESUME,The CDM still has control stream left to process meaning this context must be resumed" "0,1" newline bitfld.long 0x0 0. "COMPLETE,The CDM has completed the context store operation and fenced its state to external memory" "0,1" line.long 0x4 "RGX_CR_CDM_CONTEXT_STORE_STATUS_1,This register indicates the status of a CDM context switch operation. If a context store is in progress. this register must be sampled on a context store compute finished event. The firmware must wait for the COMPLETE.." hexmask.long 0x4 0.--31. 1. "Reserved_2,Reserved_2" repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) group.long ($2+0x4A8)++0x3 line.long 0x0 "RGX_CR_CDM_CONTEXT_PDS0_$1,This register contains the PDS Code and Data Addresses for the Store/Load Program. This program is sent to PDS on Context Store and Context Load." hexmask.long 0x0 4.--31. 1. "CODE_ADDR,PDS Code Address for Store/Load Program 128-bit aligned" newline hexmask.long.byte 0x0 0.--3. 1. "Reserved_0,Reserved_0" repeat.end group.long 0x4B0++0x7 line.long 0x0 "RGX_CR_CDM_CONTEXT_PDS1_0,This register contains the PDS Task Data necessary to produce the Store/Load PDS Program Task from CDM to PDS" bitfld.long 0x0 30.--31. "Reserved_30,Reserved_30" "0,1,2,3" newline bitfld.long 0x0 29. "PDS_SEQ_DEP,PDS Sequential Dependency" "0,1" newline bitfld.long 0x0 28. "USC_SEQ_DEP,USC Sequential Dependency" "0,1" newline bitfld.long 0x0 27. "TARGET,USC Target (0=All 1=Any)" "All,Any)" newline hexmask.long.byte 0x0 21.--26. 1. "UNIFIED_SIZE,Unified Size" newline bitfld.long 0x0 20. "COMMON_SHARED,PDS Common Store Allocation is Shared Registers" "0,1" newline hexmask.long.word 0x0 11.--19. 1. "COMMON_SIZE,PDS Common Size" newline hexmask.long.byte 0x0 7.--10. 1. "TEMP_SIZE,PDS Temp Size" newline hexmask.long.byte 0x0 1.--6. 1. "DATA_SIZE,PDS Data Size" newline bitfld.long 0x0 0. "FENCE,Fence the Task in the PDS/USC - Set on Store unset on Load" "0,1" line.long 0x4 "RGX_CR_CDM_CONTEXT_PDS1_1,This register contains the PDS Task Data necessary to produce the Store/Load PDS Program Task from CDM to PDS" hexmask.long 0x4 0.--31. 1. "Reserved_30,Reserved_30" repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) group.long ($2+0x4B8)++0x3 line.long 0x0 "RGX_CR_CDM_TERMINATE_PDS_$1,This register contains the PDS Code and Data Addresses for the Terminate Program. This program is sent to PDS on Context Store after the Context Store Program" hexmask.long 0x0 4.--31. 1. "CODE_ADDR,PDS Code Address for Terminate Program 128-bit aligned" newline hexmask.long.byte 0x0 0.--3. 1. "Reserved_0,Reserved_0" repeat.end group.long 0x4C0++0x7 line.long 0x0 "RGX_CR_CDM_TERMINATE_PDS1_0,This register contains the PDS Task Data necessary to produce the Context Store Terminate PDS Program Task from CDM to PDS" bitfld.long 0x0 30.--31. "Reserved_30,Reserved_30" "0,1,2,3" newline bitfld.long 0x0 29. "PDS_SEQ_DEP,PDS Sequential Dependency" "0,1" newline bitfld.long 0x0 28. "USC_SEQ_DEP,USC Sequential Dependency" "0,1" newline bitfld.long 0x0 27. "TARGET,USC Target (0=All 1=Any)" "All,Any)" newline hexmask.long.byte 0x0 21.--26. 1. "UNIFIED_SIZE,Unified Size" newline bitfld.long 0x0 20. "COMMON_SHARED,PDS Common Store Allocation is Shared Registers" "0,1" newline hexmask.long.word 0x0 11.--19. 1. "COMMON_SIZE,PDS Common Size" newline hexmask.long.byte 0x0 7.--10. 1. "TEMP_SIZE,PDS Temp Size" newline hexmask.long.byte 0x0 1.--6. 1. "DATA_SIZE,PDS Data Size" newline bitfld.long 0x0 0. "FENCE,Fence the Task in the PDS/USC - Set on Store Terminate" "0,1" line.long 0x4 "RGX_CR_CDM_TERMINATE_PDS1_1,This register contains the PDS Task Data necessary to produce the Context Store Terminate PDS Program Task from CDM to PDS" hexmask.long 0x4 0.--31. 1. "Reserved_30,Reserved_30" repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) group.long ($2+0x4D8)++0x3 line.long 0x0 "RGX_CR_CDM_CONTEXT_LOAD_PDS0_$1,This register contains the PDS Code and Data Addresses for the Store/Load Program. This program is sent to PDS on Context Store and Context Load." hexmask.long 0x0 4.--31. 1. "CODE_ADDR,PDS Code Address for Store/Load Program 128-bit aligned" newline hexmask.long.byte 0x0 0.--3. 1. "Reserved_0,Reserved_0" repeat.end group.long 0x4E0++0x7 line.long 0x0 "RGX_CR_CDM_CONTEXT_LOAD_PDS1_0,This register contains the PDS Task Data necessary to produce the Store/Load PDS Program Task from CDM to PDS" bitfld.long 0x0 30.--31. "Reserved_30,Reserved_30" "0,1,2,3" newline bitfld.long 0x0 29. "PDS_SEQ_DEP,PDS Sequential Dependency" "0,1" newline bitfld.long 0x0 28. "USC_SEQ_DEP,USC Sequential Dependency" "0,1" newline bitfld.long 0x0 27. "TARGET,USC Target (0=All 1=Any)" "All,Any)" newline hexmask.long.byte 0x0 21.--26. 1. "UNIFIED_SIZE,Unified Size" newline bitfld.long 0x0 20. "COMMON_SHARED,PDS Common Store Allocation is Shared Registers" "0,1" newline hexmask.long.word 0x0 11.--19. 1. "COMMON_SIZE,PDS Common Size" newline hexmask.long.byte 0x0 7.--10. 1. "TEMP_SIZE,PDS Temp Size" newline hexmask.long.byte 0x0 1.--6. 1. "DATA_SIZE,PDS Data Size" newline bitfld.long 0x0 0. "FENCE,Fence the Task in the PDS/USC - Set on Store unset on Load" "0,1" line.long 0x4 "RGX_CR_CDM_CONTEXT_LOAD_PDS1_1,This register contains the PDS Task Data necessary to produce the Store/Load PDS Program Task from CDM to PDS" hexmask.long 0x4 0.--31. 1. "Reserved_30,Reserved_30" group.long 0x600++0x7 line.long 0x0 "RGX_CR_PDS_CTRL_0,Controls the maximum number of tasks per data master (per USC). There are a maximum of 48 tasks in the system" hexmask.long.byte 0x0 24.--31. 1. "MAX_NUM_CDM_TASKS,The maximum number of compute tasks allowed on each USC range 0 to 48" newline hexmask.long.byte 0x0 16.--23. 1. "MAX_NUM_PDM_TASKS,The maximum number of pixel tasks allowed on each USC range 0 to 48" newline hexmask.long.byte 0x0 8.--15. 1. "MAX_NUM_VDM_TASKS,The maximum number of vertex tasks (VS HS GS when Tess not enabled) allowed on each USC range 0 to 39 (Note reduced range to prevent Pixel/VDM system deadlock)" newline hexmask.long.byte 0x0 0.--7. 1. "MAX_NUM_TDM_TASKS,The maximum number of fastrender tasks allowed on each USC range 0 to 48" line.long 0x4 "RGX_CR_PDS_CTRL_1,Controls the maximum number of tasks per data master (per USC). There are a maximum of 48 tasks in the system" hexmask.long 0x4 0.--31. 1. "Reserved_32,Reserved_32" wgroup.long 0x608++0x7 line.long 0x0 "RGX_CR_PDS_USC_COLLATOR_0,This register clear the internal resource tracking storage. It must be cleared after reste/power up. A write of '1' to this register clears the PDS Unified Clusters Resource Collator Contents. The PDS USC Resource Collator is a.." hexmask.long 0x0 1.--31. 1. "Reserved_1,Reserved_1" newline bitfld.long 0x0 0. "CLEAR,Clear PDS Unified Clusters Resource Collator" "0,1" line.long 0x4 "RGX_CR_PDS_USC_COLLATOR_1,This register clear the internal resource tracking storage. It must be cleared after reste/power up. A write of '1' to this register clears the PDS Unified Clusters Resource Collator Contents. The PDS USC Resource Collator is a.." hexmask.long 0x4 0.--31. 1. "Reserved_1,Reserved_1" group.long 0x610++0x1F line.long 0x0 "RGX_CR_PDS_EXEC_BASE_0,Base Address in memory where the PDS programs are located" hexmask.long.word 0x0 20.--31. 1. "ADDR,1TB addressable 1 MB aligned base address for PDS programs" newline hexmask.long.tbyte 0x0 0.--19. 1. "Reserved_0,Reserved_0" line.long 0x4 "RGX_CR_PDS_EXEC_BASE_1,Base Address in memory where the PDS programs are located" hexmask.long.tbyte 0x4 8.--31. 1. "Reserved_40,Reserved_40" newline hexmask.long.byte 0x4 0.--7. 1. "ADDR,1TB addressable 1 MB aligned base address for PDS programs" line.long 0x8 "RGX_CR_EVENT_PIXEL_PDS_CODE_0,RGX_CR_EVENT_PIXEL_PDS_CODE_0" hexmask.long 0x8 4.--31. 1. "ADDR,PDS Execution Address for pixel tasks (Positioned as a byte address 128 bit granularity) 4 GB Range" newline hexmask.long.byte 0x8 0.--3. 1. "Reserved_0,Reserved_0" line.long 0xC "RGX_CR_EVENT_PIXEL_PDS_CODE_1,RGX_CR_EVENT_PIXEL_PDS_CODE_1" hexmask.long 0xC 0.--31. 1. "Reserved_32,Reserved_32" line.long 0x10 "RGX_CR_EVENT_PIXEL_PDS_DATA_0,RGX_CR_EVENT_PIXEL_PDS_DATA_0" hexmask.long 0x10 4.--31. 1. "ADDR,PDS Execution Address for pixel tasks (Positioned as a byte address 128 bit granularity) 4 GB Range" newline hexmask.long.byte 0x10 0.--3. 1. "Reserved_0,Reserved_0" line.long 0x14 "RGX_CR_EVENT_PIXEL_PDS_DATA_1,RGX_CR_EVENT_PIXEL_PDS_DATA_1" hexmask.long 0x14 0.--31. 1. "Reserved_32,Reserved_32" line.long 0x18 "RGX_CR_EVENT_PIXEL_PDS_INFO_0,RGX_CR_EVENT_PIXEL_PDS_INFO_0" hexmask.long.tbyte 0x18 15.--31. 1. "Reserved_15,Reserved_15" newline hexmask.long.byte 0x18 9.--14. 1. "USC_SR_SIZE,USC Shared Register Data Size in 4x128 bit words (0=0) for pixel event task if zero pixel event task is skipped" newline hexmask.long.byte 0x18 5.--8. 1. "TEMP_STRIDE,PDS Temp Size in 128 bit words (0=0) for pixel event tasks" newline hexmask.long.byte 0x18 0.--4. 1. "CONST_SIZE,PDS Data Size in 128 bit words (0=0) for pixel event tasks if zero pixel event task is skipped" line.long 0x1C "RGX_CR_EVENT_PIXEL_PDS_INFO_1,RGX_CR_EVENT_PIXEL_PDS_INFO_1" hexmask.long 0x1C 0.--31. 1. "Reserved_15,Reserved_15" wgroup.long 0x630++0x7 line.long 0x0 "RGX_CR_PDS_CSRM_0,A write of '1' to this register clears the PDS Common Store Resource Manager Contents The PDS CSRM is a cross-DM controller. meaning this register must not be written during any active TA. 3D or Compute phase. This register must be.." hexmask.long 0x0 1.--31. 1. "Reserved_1,Reserved_1" newline bitfld.long 0x0 0. "CLEAR,Clear PDS Common Store Resource Manager a write to this register results in a one cycle pulse" "0,1" line.long 0x4 "RGX_CR_PDS_CSRM_1,A write of '1' to this register clears the PDS Common Store Resource Manager Contents The PDS CSRM is a cross-DM controller. meaning this register must not be written during any active TA. 3D or Compute phase. This register must be.." hexmask.long 0x4 0.--31. 1. "Reserved_1,Reserved_1" group.long 0x638++0xF line.long 0x0 "RGX_CR_PDS_MAX_CSRM_CHUNKS_0,Soft Limit Registers for Maximum Allocation Chunks in the Common Store on a Data Master basis. 1024 Allocation Regions exist in the Common Store. Each Allocation Region or Chunk represetns 4x128-bits of space in the Common.." hexmask.long.byte 0x0 27.--31. 1. "Reserved_27,Reserved_27" newline hexmask.long.word 0x0 18.--26. 1. "CDM,Max Number of Allocation Regions to Allocate to the Compute Data Master in Common Store" newline hexmask.long.word 0x0 9.--17. 1. "PDM,Max Number of Allocation Regions to Allocate to the Pixel Data Master in Common Store" newline hexmask.long.word 0x0 0.--8. 1. "VDM,Max Number of Allocation Regions to Allocate to the VDM Data Master in Common Store" line.long 0x4 "RGX_CR_PDS_MAX_CSRM_CHUNKS_1,Soft Limit Registers for Maximum Allocation Chunks in the Common Store on a Data Master basis. 1024 Allocation Regions exist in the Common Store. Each Allocation Region or Chunk represetns 4x128-bits of space in the Common.." hexmask.long 0x4 0.--31. 1. "Reserved_27,Reserved_27" line.long 0x8 "RGX_CR_PDS_CSRM_MAX_COEFF_0,The Common Store contains Coefficients and Shared Registers in a maximum of n Lines of 64 Allocation Chunks numbered 0-19. Allocated Dynamically. This Register sets a Soft Limit for the Maximum Line to Allocate for use as a.." hexmask.long 0x8 6.--31. 1. "Reserved_6,Reserved_6" newline hexmask.long.byte 0x8 1.--5. 1. "LINE,Coefficients are allocated from Line 0 upwards this is the maximum Line to use for Coefficients before wrapping" newline bitfld.long 0x8 0. "LINE_ENABLE,Enable Max Coefficient Line Limit" "0,1" line.long 0xC "RGX_CR_PDS_CSRM_MAX_COEFF_1,The Common Store contains Coefficients and Shared Registers in a maximum of n Lines of 64 Allocation Chunks numbered 0-19. Allocated Dynamically. This Register sets a Soft Limit for the Maximum Line to Allocate for use as a.." hexmask.long 0xC 0.--31. 1. "Reserved_6,Reserved_6" wgroup.long 0x648++0x7 line.long 0x0 "RGX_CR_PDS_USRM_0,A write of '1' to this register clears the PDS Unified Store Resource Manager Contents. The PDS Unified Store Resource Manager only applies to the vertex and compute data masters. This register must be written during the core.." hexmask.long 0x0 1.--31. 1. "Reserved_1,Reserved_1" newline bitfld.long 0x0 0. "CLEAR,Clear PDS Unified Store Resource Manager a write to this register results in a one cycle pulse" "0,1" line.long 0x4 "RGX_CR_PDS_USRM_1,A write of '1' to this register clears the PDS Unified Store Resource Manager Contents. The PDS Unified Store Resource Manager only applies to the vertex and compute data masters. This register must be written during the core.." hexmask.long 0x4 0.--31. 1. "Reserved_1,Reserved_1" group.long 0x650++0xF line.long 0x0 "RGX_CR_PDS_MAX_USRM_CHUNKS_0,Soft Limit Registers for Maximum Allocation Chunks in the Unified Store on a Data Master basis. 400 Allocation Regions exist in the Unified Store. Each Allocation Region represents 4x128-bits of space in the Unified Store." hexmask.long.word 0x0 18.--31. 1. "Reserved_18,Reserved_18" newline hexmask.long.word 0x0 9.--17. 1. "CDM,Max Number of Allocation Regions to Allocate to the Compute Data Master in Unified Store" newline hexmask.long.word 0x0 0.--8. 1. "VDM,Max Number of Allocation Regions to Allocate to the VDM Data Master in Unified Store" line.long 0x4 "RGX_CR_PDS_MAX_USRM_CHUNKS_1,Soft Limit Registers for Maximum Allocation Chunks in the Unified Store on a Data Master basis. 400 Allocation Regions exist in the Unified Store. Each Allocation Region represents 4x128-bits of space in the Unified Store." hexmask.long 0x4 0.--31. 1. "Reserved_18,Reserved_18" line.long 0x8 "RGX_CR_PDS_USRM_MAX_TEMP_0,The Unified Store contains Temporaries and Attributes in n Lines of 16 Allocation Chunks numbered 0- n-1. Allocated Dynamically. This Register sets a Soft Limit for the Maximum Line to Allocate for use as a Temporaries Line.." hexmask.long 0x8 5.--31. 1. "Reserved_5,Reserved_5" newline hexmask.long.byte 0x8 1.--4. 1. "LINE,Max Line for use as Temporaries" newline bitfld.long 0x8 0. "LINE_ENABLE,Enable Max Temporaries Line Limit" "0,1" line.long 0xC "RGX_CR_PDS_USRM_MAX_TEMP_1,The Unified Store contains Temporaries and Attributes in n Lines of 16 Allocation Chunks numbered 0- n-1. Allocated Dynamically. This Register sets a Soft Limit for the Maximum Line to Allocate for use as a Temporaries Line.." hexmask.long 0xC 0.--31. 1. "Reserved_5,Reserved_5" wgroup.long 0x660++0x7 line.long 0x0 "RGX_CR_PDS_UVSRM_0,A write of '1' to this register clears the PDS Unified Vertex Store Resource Manager Contents The UVS Resource Manager only applies to the vertex data master. This register must be written during the core initialisation sequence." hexmask.long 0x0 1.--31. 1. "Reserved_1,Reserved_1" newline bitfld.long 0x0 0. "CLEAR,Clear PDS Unified Vertex Store Resource Manager a write to this register results in a one cycle pulse" "0,1" line.long 0x4 "RGX_CR_PDS_UVSRM_1,A write of '1' to this register clears the PDS Unified Vertex Store Resource Manager Contents The UVS Resource Manager only applies to the vertex data master. This register must be written during the core initialisation sequence." hexmask.long 0x4 0.--31. 1. "Reserved_1,Reserved_1" group.long 0x668++0x7 line.long 0x0 "RGX_CR_MCU_FBTC_ICTRL_0,MCU Framebuffer Tile Cache Invalidate Control" hexmask.long 0x0 4.--31. 1. "Reserved_4,Reserved_4" newline bitfld.long 0x0 3. "COMP_DM,When set to 1 all entries in the tile cache that have been tagged as a compute data master will be invalidate when PENDING is set" "0,1" newline bitfld.long 0x0 2. "VERTEX_DM,When set to 1 all entries in the tile cache that have been tagged as a vertex data master will be invalidate when PENDING is set" "0,1" newline bitfld.long 0x0 1. "PIXEL_DM,When set to 1 all entries in the tile cache that have been tagged as a pixel data master will be invalidate when PENDING is set" "0,1" newline bitfld.long 0x0 0. "PENDING,When written to 1 will invalidate the header cache in the FBDC when read as 1 invalidate is in progress when read as 0 invalidate is complete" "0,1" line.long 0x4 "RGX_CR_MCU_FBTC_ICTRL_1,MCU Framebuffer Tile Cache Invalidate Control" hexmask.long 0x4 0.--31. 1. "Reserved_4,Reserved_4" wgroup.long 0x670++0x7 line.long 0x0 "RGX_CR_PDS_STORERM_0,A write of '1' to this register clears the PDS Store Resource Manager Contents. The PDS Store Resource Manager is a cross-DM controller. meaning this register must not be written during any active TA. 3D or Compute phase. This.." hexmask.long 0x0 1.--31. 1. "Reserved_1,Reserved_1" newline bitfld.long 0x0 0. "CLEAR,Clear PDS Store Resource Manager a write to this register results in a one cycle pulse" "0,1" line.long 0x4 "RGX_CR_PDS_STORERM_1,A write of '1' to this register clears the PDS Store Resource Manager Contents. The PDS Store Resource Manager is a cross-DM controller. meaning this register must not be written during any active TA. 3D or Compute phase. This.." hexmask.long 0x4 0.--31. 1. "Reserved_1,Reserved_1" group.long 0x678++0x27 line.long 0x0 "RGX_CR_PDS_MAX_STORERM_CHUNKS_0,Soft Limit Registers for Maximum Allocation Chunks in the PDS Store on a Data Master basis. 488 Allocation Regions exist in the PDS Store. Each Allocation Chunk/Region represents 8x64-bits of space in the PDS Store." hexmask.long.byte 0x0 27.--31. 1. "STM,Max Number of Allocation Regions to Allocate to the Stream Out Data Master in PDS Store" newline hexmask.long.word 0x0 18.--26. 1. "CDM,Max Number of Allocation Regions to Allocate to the Compute Data Master in PDS Store" newline hexmask.long.word 0x0 9.--17. 1. "PDM,Max Number of Allocation Regions to Allocate to the Pixel Data Master in PDS Store" newline hexmask.long.word 0x0 0.--8. 1. "VDM,Max Number of Allocation Regions to Allocate to the VDM Data Master in PDS Store" line.long 0x4 "RGX_CR_PDS_MAX_STORERM_CHUNKS_1,Soft Limit Registers for Maximum Allocation Chunks in the PDS Store on a Data Master basis. 488 Allocation Regions exist in the PDS Store. Each Allocation Chunk/Region represents 8x64-bits of space in the PDS Store." hexmask.long 0x4 4.--31. 1. "Reserved_36,Reserved_36" newline hexmask.long.byte 0x4 0.--3. 1. "STM,Max Number of Allocation Regions to Allocate to the Stream Out Data Master in PDS Store" line.long 0x8 "RGX_CR_PDS_STORERM_MAX_TEMP_0,The PDS Store Resource Manager contains Temporaries and Constants in 8 Lines of 64 Allocation Chunks each numbered 0-7. Allocated Dynamically. This Register sets a Soft Limit for the Maximum Line to Allocate for use as a.." hexmask.long 0x8 4.--31. 1. "Reserved_4,Reserved_4" newline bitfld.long 0x8 1.--3. "LINE,Temporaries are allocated from Line 0 upwards this is the maximum Line to use for Temporaries before wrapping" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 0. "LINE_ENABLE,Enable Max Temporaries Line Limit" "0,1" line.long 0xC "RGX_CR_PDS_STORERM_MAX_TEMP_1,The PDS Store Resource Manager contains Temporaries and Constants in 8 Lines of 64 Allocation Chunks each numbered 0-7. Allocated Dynamically. This Register sets a Soft Limit for the Maximum Line to Allocate for use as a.." hexmask.long 0xC 0.--31. 1. "Reserved_4,Reserved_4" line.long 0x10 "RGX_CR_PDS_ICC_INVAL_0,A write of '1' any bit to this register clears the PDS Instruction Cache for the selected DM The PDS HW will clear the bits when the operations complete" hexmask.long 0x10 6.--31. 1. "Reserved_6,Reserved_6" newline bitfld.long 0x10 5. "FASTRENDER_PENDING,PDS Instruction Cache Fastrender (DM 6) has been invalidated" "0,1" newline bitfld.long 0x10 3.--4. "Reserved_3,Reserved_3" "0,1,2,3" newline bitfld.long 0x10 2. "COMPUTE_PENDING,PDS Instruction Cache Compute (DM 2) has been invalidated" "0,1" newline bitfld.long 0x10 1. "PIXEL_PENDING,PDS Instruction Cache Pixel (DM 1) has been invalidated" "0,1" newline bitfld.long 0x10 0. "VERTEX_PENDING,PDS Instruction Cache Vertex (DM 0) has been invalidated" "0,1" line.long 0x14 "RGX_CR_PDS_ICC_INVAL_1,A write of '1' any bit to this register clears the PDS Instruction Cache for the selected DM The PDS HW will clear the bits when the operations complete" hexmask.long 0x14 0.--31. 1. "Reserved_6,Reserved_6" line.long 0x18 "RGX_CR_PDS_MCU_REQ_CTRL_0,The PDS makes requests to the MCU to DMA to the PDS store and write data to memory. This register defines the various cache modes that apply to those requests." hexmask.long 0x18 4.--31. 1. "Reserved_4,Reserved_4" newline bitfld.long 0x18 2.--3. "SMODE,SLC cache policy to use for requests from the VDM/PDM/CDM/STM resource requestors inside the PDS" "0,1,2,3" newline bitfld.long 0x18 0.--1. "CMODE,Cache Mode to use for requests from the VDM/PDM/CDM/STM resource requestors inside the PDS" "0,1,2,3" line.long 0x1C "RGX_CR_PDS_MCU_REQ_CTRL_1,The PDS makes requests to the MCU to DMA to the PDS store and write data to memory. This register defines the various cache modes that apply to those requests." hexmask.long 0x1C 0.--31. 1. "Reserved_4,Reserved_4" line.long 0x20 "RGX_CR_PDS_CSRM_MIN_SHARED_0,The Common Store contains Coefficients and Shared Registers in 14 Lines of 64 Allocation Chunks numbered 0-13. Allocated Dynamically. This Register sets a Soft Limit for the Minimum Line to Allocate for use as a Shared Line.." hexmask.long 0x20 6.--31. 1. "Reserved_6,Reserved_6" newline hexmask.long.byte 0x20 1.--5. 1. "LINE,Shared are allocated from top line downwards this is the minimum Line to use for Shared Registers before wrapping" newline bitfld.long 0x20 0. "LINE_ENABLE,Enable Min Shared Register Line Limit" "0,1" line.long 0x24 "RGX_CR_PDS_CSRM_MIN_SHARED_1,The Common Store contains Coefficients and Shared Registers in 14 Lines of 64 Allocation Chunks numbered 0-13. Allocated Dynamically. This Register sets a Soft Limit for the Minimum Line to Allocate for use as a Shared Line.." hexmask.long 0x24 0.--31. 1. "Reserved_6,Reserved_6" repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) group.long ($2+0x6A0)++0x3 line.long 0x0 "RGX_CR_PDS_BGRND0_BASE_$1,PDS Background Setup Word 0" hexmask.long 0x0 4.--31. 1. "SHADER_ADDR,The pixel shader base is the base address of the PDS Data Segment. The code segment is address is PDS_PIXEL_SHADERBASE + PDS_PIXELSHADERSIZE. The pixel shader program issues the DOUTU for the Fragment Shader only." newline hexmask.long.byte 0x0 0.--3. 1. "Reserved_0,Reserved_0" repeat.end repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) group.long ($2+0x6A8)++0x3 line.long 0x0 "RGX_CR_PDS_BGRND1_BASE_$1,PDS Background Setup Word 1" hexmask.long 0x0 4.--31. 1. "VARYING_ADDR,This is the base address of the PDS Data Segment. The code segment is address is PDS_VARYINGBASE + PDS_VARYINGSIZE (PDS_BGRND_SIZEINFO1)." newline hexmask.long.byte 0x0 0.--3. 1. "Reserved_0,Reserved_0" repeat.end group.long 0x6B0++0x37 line.long 0x0 "RGX_CR_PDS_BGRND2_BASE_0,PDS Background Setup Word 2" hexmask.long 0x0 4.--31. 1. "UNIFORMDATA_ADDR,This points to the DMAs to load the Uniforms (or contains the Uniforms with DOUTW commands)" newline hexmask.long.byte 0x0 0.--3. 1. "Reserved_0,Reserved_0" line.long 0x4 "RGX_CR_PDS_BGRND2_BASE_1,PDS Background Setup Word 2" hexmask.long 0x4 0.--31. 1. "Reserved_32,Reserved_32" line.long 0x8 "RGX_CR_PDS_BGRND3_SIZEINFO_0,If any of the size fields are 0. then that program will not be run. PDS_BGRND_PIXELSHADERSIZE is always 2 128 Bit Words" hexmask.long.word 0x8 23.--31. 1. "PDS_UNIFORMSIZE,The size of the Uniform PDS Data Segment in 128 bit words" newline hexmask.long.byte 0x8 16.--22. 1. "PDS_TEXTURESTATESIZE,The size of the Texture PDS Data Segment in 128 bit words" newline hexmask.long.byte 0x8 10.--15. 1. "PDS_VARYINGSIZE,The size of the Varying/Coefficient PDS Data Segment in 128 bit words" newline hexmask.long.byte 0x8 4.--9. 1. "USC_VARYINGSIZE,The size of the Varying/Coefficient USC Common Store Data in 4x128 bit words" newline hexmask.long.byte 0x8 0.--3. 1. "PDS_TEMPSIZE,0 = 0 128 bit words 1 = 1 128 bit word this applies to coefficient uniform and varying state" line.long 0xC "RGX_CR_PDS_BGRND3_SIZEINFO_1,If any of the size fields are 0. then that program will not be run. PDS_BGRND_PIXELSHADERSIZE is always 2 128 Bit Words" hexmask.long.word 0xC 23.--31. 1. "USC_SHAREDSIZE,The common store allocation size for the shared registers (texture and uniform data commbined)" newline hexmask.long.word 0xC 14.--22. 1. "Reserved_46,Reserved_46" newline hexmask.long.word 0xC 0.--13. 1. "PDS_BATCHNUM,The batch ID to be associated with the background" line.long 0x10 "RGX_CR_PDS_USRM_MIN_ATTR_0,The Unified Store contains Temporaries and Attributes in n Lines of 16 Allocation Chunks numbered 0 - n-1. Allocated Dynamically. This Register sets a Soft Limit for the Minimum Line to Allocate for use as an Attribute Line.." hexmask.long 0x10 5.--31. 1. "Reserved_5,Reserved_5" newline hexmask.long.byte 0x10 1.--4. 1. "LINE,Min Line for use for Attributes" newline bitfld.long 0x10 0. "LINE_ENABLE,Enable Min Attributes Line Limit" "0,1" line.long 0x14 "RGX_CR_PDS_USRM_MIN_ATTR_1,The Unified Store contains Temporaries and Attributes in n Lines of 16 Allocation Chunks numbered 0 - n-1. Allocated Dynamically. This Register sets a Soft Limit for the Minimum Line to Allocate for use as an Attribute Line.." hexmask.long 0x14 0.--31. 1. "Reserved_5,Reserved_5" line.long 0x18 "RGX_CR_PDS_STORERM_MIN_CONST_0,The PDS Store Resource Manager contains Temporaries and Constants in 8 Lines of 64 Allocation Chunks each numbered 0-7. Allocated Dynamically. This Register sets a Soft Limit for the Minimum Line to Allocate for use as a.." hexmask.long 0x18 4.--31. 1. "Reserved_4,Reserved_4" newline bitfld.long 0x18 1.--3. "LINE,Constants are allocated from Line 7 down this is the minimum Line to use for Constants before wrapping" "0,1,2,3,4,5,6,7" newline bitfld.long 0x18 0. "LINE_ENABLE,Enable Min Constants Line Limit" "0,1" line.long 0x1C "RGX_CR_PDS_STORERM_MIN_CONST_1,The PDS Store Resource Manager contains Temporaries and Constants in 8 Lines of 64 Allocation Chunks each numbered 0-7. Allocated Dynamically. This Register sets a Soft Limit for the Minimum Line to Allocate for use as a.." hexmask.long 0x1C 0.--31. 1. "Reserved_4,Reserved_4" line.long 0x20 "RGX_CR_PDS_PIXELMERGE_0,RGX_CR_PDS_PIXELMERGE_0" hexmask.long 0x20 7.--31. 1. "Reserved_7,Reserved_7" newline bitfld.long 0x20 6. "TASK_DISABLE,Disable pixel merging within a whole pixel fragment task" "0,1" newline bitfld.long 0x20 5. "DISABLE,Disable pixel merging within each 2x2 pixel block of a pixel fragment task" "0,1" newline hexmask.long.byte 0x20 0.--4. 1. "GRADLIMIT,Gradient difference limit for PDS PP pixel merging" line.long 0x24 "RGX_CR_PDS_PIXELMERGE_1,RGX_CR_PDS_PIXELMERGE_1" hexmask.long 0x24 0.--31. 1. "Reserved_7,Reserved_7" line.long 0x28 "RGX_CR_PDS_CSRM_USC_DEBUG_0,When written a non zero value. this register assigns an extra degree of space to be allocated in the Common Store via the PDS CSRM for USC debugging on Shared Allocations. The SIZE field is Allocation Region Granular (i.e.." hexmask.long 0x28 5.--31. 1. "Reserved_5,Reserved_5" newline hexmask.long.byte 0x28 0.--4. 1. "SIZE,Amount of Space (in 512-bit Allocation Regions) to allocate to USC Debug Space on a Shared Allocation." line.long 0x2C "RGX_CR_PDS_CSRM_USC_DEBUG_1,When written a non zero value. this register assigns an extra degree of space to be allocated in the Common Store via the PDS CSRM for USC debugging on Shared Allocations. The SIZE field is Allocation Region Granular (i.e.." hexmask.long 0x2C 0.--31. 1. "Reserved_5,Reserved_5" line.long 0x30 "RGX_CR_PDS_CSRM_DISABLE_0,When this register is set. the CSRM will be configured on PDS CSRM CLEAR to not reserve any space for Partitions (this is normally governed by the AA MODE and PIXEL OUTPUT CTRL WIDTH register settings). to maximise space in the.." hexmask.long 0x30 3.--31. 1. "Reserved_3,Reserved_3" newline bitfld.long 0x30 2. "COEFF_SLIDE,Disable Slide of Coeff Allocations on Failure" "0,1" newline bitfld.long 0x30 1. "SHARED_SLIDE,Disable Slide of Shared Allocations on Failure" "0,1" newline bitfld.long 0x30 0. "PARTITIONS,Disable Partition Space Reservation in the CSRM" "0,1" line.long 0x34 "RGX_CR_PDS_CSRM_DISABLE_1,When this register is set. the CSRM will be configured on PDS CSRM CLEAR to not reserve any space for Partitions (this is normally governed by the AA MODE and PIXEL OUTPUT CTRL WIDTH register settings). to maximise space in the.." hexmask.long 0x34 0.--31. 1. "Reserved_3,Reserved_3" rgroup.long 0x6E8++0x7 line.long 0x0 "RGX_CR_HUB_IDLE_0,RGX_CR_HUB_IDLE_0" hexmask.long 0x0 4.--31. 1. "Reserved_4,Reserved_4" newline bitfld.long 0x0 3. "TDM,TDM Module IDLE" "0,1" newline bitfld.long 0x0 2. "CDM,CDM Module IDLE" "0,1" newline bitfld.long 0x0 1. "VDM,VDM Module IDLE" "0,1" newline bitfld.long 0x0 0. "PDS,PDS Module IDLE" "0,1" line.long 0x4 "RGX_CR_HUB_IDLE_1,RGX_CR_HUB_IDLE_1" hexmask.long 0x4 0.--31. 1. "Reserved_4,Reserved_4" repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) rgroup.long ($2+0x6F0)++0x3 line.long 0x0 "RGX_CR_HUB_PWR_$1,RGX_CR_HUB_PWR_0" hexmask.long 0x0 0.--31. 1. "NUM_PDS_INST,Number of PDS instructions" repeat.end group.long 0x700++0xF line.long 0x0 "RGX_CR_PDS_PASSGROUP_0,RGX_CR_PDS_PASSGROUP_0" hexmask.long 0x0 2.--31. 1. "Reserved_2,Reserved_2" newline bitfld.long 0x0 1. "FORCE_PT,Force the use of Hard SDs between punchthrough or depth feedback type passes" "0,1" newline bitfld.long 0x0 0. "ENABLE,Enable pass group optimisation within USC by replacing USC Hard SDs with USC Soft SDs for all pass groups in the PDS PP." "0,1" line.long 0x4 "RGX_CR_PDS_PASSGROUP_1,RGX_CR_PDS_PASSGROUP_1" hexmask.long 0x4 0.--31. 1. "Reserved_2,Reserved_2" line.long 0x8 "RGX_CR_PDS_COMPUTE_THREAD_BARRIER_0,RGX_CR_PDS_COMPUTE_THREAD_BARRIER_0" hexmask.long 0x8 1.--31. 1. "Reserved_1,Reserved_1" newline bitfld.long 0x8 0. "ENABLE,Enable thread barrier support in the PDS CDM_RR." "0,1" line.long 0xC "RGX_CR_PDS_COMPUTE_THREAD_BARRIER_1,RGX_CR_PDS_COMPUTE_THREAD_BARRIER_1" hexmask.long 0xC 0.--31. 1. "Reserved_1,Reserved_1" group.long 0x720++0x7 line.long 0x0 "RGX_CR_PDS_CSRM_SETUP_0,If the ENABLE field is set. then when the PDS CSRM is Cleared via the PDS_CSRM_CLEAR register. the value set in the MAX_LINE vector is used to define the maximum Line in the CSRM which is allocatable to Shared.." hexmask.long 0x0 6.--31. 1. "Reserved_6,Reserved_6" newline bitfld.long 0x0 5. "HALF,Top line is prefilled half full" "0,1" newline hexmask.long.byte 0x0 1.--4. 1. "MAX_LINE,(Lower 4 bits of) Maximum Line within the CSRM that can be allocated to Shared Registers/Coefficients" newline bitfld.long 0x0 0. "ENABLE,Enable use of this register to set the Maximum Line the CSRM can allocate on behalf of the USC Common Store" "0,1" line.long 0x4 "RGX_CR_PDS_CSRM_SETUP_1,If the ENABLE field is set. then when the PDS CSRM is Cleared via the PDS_CSRM_CLEAR register. the value set in the MAX_LINE vector is used to define the maximum Line in the CSRM which is allocatable to Shared.." hexmask.long 0x4 0.--31. 1. "Reserved_6,Reserved_6" group.long 0x738++0x7 line.long 0x0 "RGX_CR_PDS_USRM_DISABLE_0,When this register is set. the USRM will be configured on PDS USRM CLEAR to disable the Temp/Attribute slide functionality which allows a Temporaries or Attributes allocation which fails to slide the allocation window. The.." hexmask.long 0x0 1.--31. 1. "Reserved_1,Reserved_1" newline bitfld.long 0x0 0. "TEMP_SLIDE,Disable Slide of Temp Allocations on Failure" "0,1" line.long 0x4 "RGX_CR_PDS_USRM_DISABLE_1,When this register is set. the USRM will be configured on PDS USRM CLEAR to disable the Temp/Attribute slide functionality which allows a Temporaries or Attributes allocation which fails to slide the allocation window. The.." hexmask.long 0x4 0.--31. 1. "Reserved_1,Reserved_1" group.long 0x788++0xF line.long 0x0 "RGX_CR_PDS_CSRM_PIXEL_0,The Common Store contains Coefficients and Shared Registers in a maximum of n Lines of 64 Allocation Chunks numbered 0-31. Allocated Dynamically. This Register sets a Soft Limit for the Maximum Line of available Coefficient space." hexmask.long 0x0 6.--31. 1. "Reserved_6,Reserved_6" newline hexmask.long.byte 0x0 1.--5. 1. "MAX_LINE,Coefficients are allocated from Line 0 upwards this is the maximum Line to reserve for ONLY PDM Coefficients. The Max line of this region is set in the PDS_CSRM_MAX_COEFF register" newline bitfld.long 0x0 0. "MODE_ENABLE,Enable PIXEL RESERVE MODE in the PDS CSRM" "0,1" line.long 0x4 "RGX_CR_PDS_CSRM_PIXEL_1,The Common Store contains Coefficients and Shared Registers in a maximum of n Lines of 64 Allocation Chunks numbered 0-31. Allocated Dynamically. This Register sets a Soft Limit for the Maximum Line of available Coefficient space." hexmask.long 0x4 0.--31. 1. "Reserved_6,Reserved_6" line.long 0x8 "RGX_CR_PDS_MAX_STORERM_CHUNKS2_0,Soft Limit Registers for Maximum Allocation Chunks in the PDS Store on a Data Master basis. 488 Allocation Regions exist in the PDS Store. Each Allocation Chunk/Region represents 8x64-bits of space in the PDS Store." hexmask.long.tbyte 0x8 9.--31. 1. "Reserved_9,Reserved_9" newline hexmask.long.word 0x8 0.--8. 1. "TDM,Max Number of Allocation Regions to Allocate to the Fastrender Data Master in PDS Store" line.long 0xC "RGX_CR_PDS_MAX_STORERM_CHUNKS2_1,Soft Limit Registers for Maximum Allocation Chunks in the PDS Store on a Data Master basis. 488 Allocation Regions exist in the PDS Store. Each Allocation Chunk/Region represents 8x64-bits of space in the PDS Store." hexmask.long 0xC 0.--31. 1. "Reserved_9,Reserved_9" group.long 0x800++0x67 line.long 0x0 "RGX_CR_SIDEKICK_EXT_MEM_ARB_CONFIG_0,This register contains the configuration options for the Sidekick external memory arbiter." hexmask.long 0x0 2.--31. 1. "Reserved_2,Reserved_2" newline bitfld.long 0x0 0.--1. "ARB_PRIO_MODE,Priority mode for external memory access arbiter between GPU scheduler and SLC" "0,1,2,3" line.long 0x4 "RGX_CR_SIDEKICK_EXT_MEM_ARB_CONFIG_1,This register contains the configuration options for the Sidekick external memory arbiter." hexmask.long 0x4 0.--31. 1. "Reserved_2,Reserved_2" line.long 0x8 "RGX_CR_MIPS_WRAPPER_FENCE_0,When writing to this register. the MIPS wrapper holds further transaction from MIPS and emits a memory fence onto the bus" hexmask.long 0x8 1.--31. 1. "Reserved_1,Reserved_1" newline bitfld.long 0x8 0. "SYS_FENCE_ID,reserved address identifier for system fence events" "0,1" line.long 0xC "RGX_CR_MIPS_WRAPPER_FENCE_1,When writing to this register. the MIPS wrapper holds further transaction from MIPS and emits a memory fence onto the bus" hexmask.long 0xC 0.--31. 1. "Reserved_1,Reserved_1" line.long 0x10 "RGX_CR_MIPS_WRAPPER_CONFIG_0,This register contains the configuration options for the MIPS CPU wrapper." hexmask.long.byte 0x10 28.--31. 1. "Reserved_28,Reserved_28" newline bitfld.long 0x10 25.--27. "OS_ID,The default OS_ID of the firmware" "0,1,2,3,4,5,6,7" newline bitfld.long 0x10 24. "TRUSTED,Defines whether these accesses are trusted" "0,1" newline hexmask.long.byte 0x10 17.--23. 1. "Reserved_17,Reserved_17" newline bitfld.long 0x10 16. "BOOT_ISA_MODE,MIPS boot up mode. When set to 0 boot from MIPS32 mode or set to 1 to boot in microMIPS mode" "0,1" newline hexmask.long.word 0x10 0.--15. 1. "REGBANK_BASE_ADDR,16-bit aligned address that identifies rgx register bank transactions emitted from the MIPS core" line.long 0x14 "RGX_CR_MIPS_WRAPPER_CONFIG_1,This register contains the configuration options for the MIPS CPU wrapper." hexmask.long.tbyte 0x14 9.--31. 1. "Reserved_41,Reserved_41" newline bitfld.long 0x14 8. "FW_IDLE_ENABLE,Set to 0x0 overwrites the value of GPU_IDLE to 0x0 set to 0x1 makes GPU Idle dependent on top level idles" "0,1" newline hexmask.long.byte 0x14 2.--7. 1. "Reserved_34,Reserved_34" newline bitfld.long 0x14 1. "DISABLE_BOOT,Stop the MIPS from boot-up even after a soft reset is triggered" "0,1" newline bitfld.long 0x14 0. "L2_CACHE_OFF,Turn off the L2 cache within the MIPS wrapper" "0,1" line.long 0x18 "RGX_CR_MIPS_ADDR_REMAP1_CONFIG1_0,This register contains the address remapping options for the MIPS CPU physical address. e.g. during boot" hexmask.long.tbyte 0x18 12.--31. 1. "BASE_ADDR_IN,4K (12 bits) aligned address used as a input for the address remapping" newline hexmask.long.word 0x18 1.--11. 1. "Reserved_1,Reserved_1" newline bitfld.long 0x18 0. "MODE_ENABLE,Enable address remapping mode" "0,1" line.long 0x1C "RGX_CR_MIPS_ADDR_REMAP1_CONFIG1_1,This register contains the address remapping options for the MIPS CPU physical address. e.g. during boot" hexmask.long 0x1C 0.--31. 1. "Reserved_32,Reserved_32" line.long 0x20 "RGX_CR_MIPS_ADDR_REMAP1_CONFIG2_0,This register contains the address remapping options for the MIPS CPU physical address. e.g. during boot" hexmask.long.tbyte 0x20 12.--31. 1. "ADDR_OUT,4K (12 bits) aligned address used as output for the address remapping" newline bitfld.long 0x20 9.--11. "Reserved_9,Reserved_9" "0,1,2,3,4,5,6,7" newline bitfld.long 0x20 6.--8. "OS_ID,The OS_ID emitted for all address transactions from this region" "0,1,2,3,4,5,6,7" newline bitfld.long 0x20 5. "TRUSTED,Defines whether these accesses are trusted" "0,1" newline hexmask.long.byte 0x20 0.--4. 1. "REGION_SIZE_POW2,Remapped region size or offset size i.e. number of bits from the bottom of the base input address that survive onto the output address. Minimum value of 12" line.long 0x24 "RGX_CR_MIPS_ADDR_REMAP1_CONFIG2_1,This register contains the address remapping options for the MIPS CPU physical address. e.g. during boot" hexmask.long.tbyte 0x24 8.--31. 1. "Reserved_40,Reserved_40" newline hexmask.long.byte 0x24 0.--7. 1. "ADDR_OUT,4K (12 bits) aligned address used as output for the address remapping" line.long 0x28 "RGX_CR_MIPS_ADDR_REMAP2_CONFIG1_0,This register contains the address remapping options for the MIPS CPU physical address. e.g. during boot" hexmask.long.tbyte 0x28 12.--31. 1. "BASE_ADDR_IN,4K (12 bits) aligned address used as a input for the address remapping" newline hexmask.long.word 0x28 1.--11. 1. "Reserved_1,Reserved_1" newline bitfld.long 0x28 0. "MODE_ENABLE,Enable address remapping mode" "0,1" line.long 0x2C "RGX_CR_MIPS_ADDR_REMAP2_CONFIG1_1,This register contains the address remapping options for the MIPS CPU physical address. e.g. during boot" hexmask.long 0x2C 0.--31. 1. "Reserved_32,Reserved_32" line.long 0x30 "RGX_CR_MIPS_ADDR_REMAP2_CONFIG2_0,This register contains the address remapping options for the MIPS CPU physical address. e.g. during boot" hexmask.long.tbyte 0x30 12.--31. 1. "ADDR_OUT,4K (12 bits) aligned address used as output for the address remapping" newline bitfld.long 0x30 9.--11. "Reserved_9,Reserved_9" "0,1,2,3,4,5,6,7" newline bitfld.long 0x30 6.--8. "OS_ID,The OS_ID emitted for all address transactions from this region" "0,1,2,3,4,5,6,7" newline bitfld.long 0x30 5. "TRUSTED,Defines whether these accesses are trusted" "0,1" newline hexmask.long.byte 0x30 0.--4. 1. "REGION_SIZE_POW2,Remapped region size or offset size i.e. number of bits from the bottom of the base input address that survive onto the output address. Minimum value of 12" line.long 0x34 "RGX_CR_MIPS_ADDR_REMAP2_CONFIG2_1,This register contains the address remapping options for the MIPS CPU physical address. e.g. during boot" hexmask.long.tbyte 0x34 8.--31. 1. "Reserved_40,Reserved_40" newline hexmask.long.byte 0x34 0.--7. 1. "ADDR_OUT,4K (12 bits) aligned address used as output for the address remapping" line.long 0x38 "RGX_CR_MIPS_ADDR_REMAP3_CONFIG1_0,This register contains the address remapping options for the MIPS CPU physical address. e.g. during boot" hexmask.long.tbyte 0x38 12.--31. 1. "BASE_ADDR_IN,4K (12 bits) aligned address used as a input for the address remapping" newline hexmask.long.word 0x38 1.--11. 1. "Reserved_1,Reserved_1" newline bitfld.long 0x38 0. "MODE_ENABLE,Enable address remapping mode" "0,1" line.long 0x3C "RGX_CR_MIPS_ADDR_REMAP3_CONFIG1_1,This register contains the address remapping options for the MIPS CPU physical address. e.g. during boot" hexmask.long 0x3C 0.--31. 1. "Reserved_32,Reserved_32" line.long 0x40 "RGX_CR_MIPS_ADDR_REMAP3_CONFIG2_0,This register contains the address remapping options for the MIPS CPU physical address. e.g. during boot" hexmask.long.tbyte 0x40 12.--31. 1. "ADDR_OUT,4K (12 bits) aligned address used as output for the address remapping" newline bitfld.long 0x40 9.--11. "Reserved_9,Reserved_9" "0,1,2,3,4,5,6,7" newline bitfld.long 0x40 6.--8. "OS_ID,The OS_ID emitted for all address transactions from this region" "0,1,2,3,4,5,6,7" newline bitfld.long 0x40 5. "TRUSTED,Defines whether these accesses are trusted" "0,1" newline hexmask.long.byte 0x40 0.--4. 1. "REGION_SIZE_POW2,Remapped region size or offset size i.e. number of bits from the bottom of the base input address that survive onto the output address. Minimum value of 12" line.long 0x44 "RGX_CR_MIPS_ADDR_REMAP3_CONFIG2_1,This register contains the address remapping options for the MIPS CPU physical address. e.g. during boot" hexmask.long.tbyte 0x44 8.--31. 1. "Reserved_40,Reserved_40" newline hexmask.long.byte 0x44 0.--7. 1. "ADDR_OUT,4K (12 bits) aligned address used as output for the address remapping" line.long 0x48 "RGX_CR_MIPS_ADDR_REMAP4_CONFIG1_0,This register contains the address remapping options for the MIPS CPU physical address. e.g. during boot" hexmask.long.tbyte 0x48 12.--31. 1. "BASE_ADDR_IN,4K (12 bits) aligned address used as a input for the address remapping" newline hexmask.long.word 0x48 1.--11. 1. "Reserved_1,Reserved_1" newline bitfld.long 0x48 0. "MODE_ENABLE,Enable address remapping mode" "0,1" line.long 0x4C "RGX_CR_MIPS_ADDR_REMAP4_CONFIG1_1,This register contains the address remapping options for the MIPS CPU physical address. e.g. during boot" hexmask.long 0x4C 0.--31. 1. "Reserved_32,Reserved_32" line.long 0x50 "RGX_CR_MIPS_ADDR_REMAP4_CONFIG2_0,This register contains the address remapping options for the MIPS CPU physical address. e.g. during boot" hexmask.long.tbyte 0x50 12.--31. 1. "ADDR_OUT,4K (12 bits) aligned address used as output for the address remapping" newline bitfld.long 0x50 9.--11. "Reserved_9,Reserved_9" "0,1,2,3,4,5,6,7" newline bitfld.long 0x50 6.--8. "OS_ID,The OS_ID emitted for all address transactions from this region" "0,1,2,3,4,5,6,7" newline bitfld.long 0x50 5. "TRUSTED,Defines whether these accesses are trusted" "0,1" newline hexmask.long.byte 0x50 0.--4. 1. "REGION_SIZE_POW2,Remapped region size or offset size i.e. number of bits from the bottom of the base input address that survive onto the output address. Minimum value of 12" line.long 0x54 "RGX_CR_MIPS_ADDR_REMAP4_CONFIG2_1,This register contains the address remapping options for the MIPS CPU physical address. e.g. during boot" hexmask.long.tbyte 0x54 8.--31. 1. "Reserved_40,Reserved_40" newline hexmask.long.byte 0x54 0.--7. 1. "ADDR_OUT,4K (12 bits) aligned address used as output for the address remapping" line.long 0x58 "RGX_CR_MIPS_ADDR_REMAP5_CONFIG1_0,This register contains the address remapping options for the MIPS CPU physical address. e.g. during boot" hexmask.long.tbyte 0x58 12.--31. 1. "BASE_ADDR_IN,4K (12 bits) aligned address used as a input for the address remapping" newline hexmask.long.word 0x58 1.--11. 1. "Reserved_1,Reserved_1" newline bitfld.long 0x58 0. "MODE_ENABLE,Enable address remapping mode" "0,1" line.long 0x5C "RGX_CR_MIPS_ADDR_REMAP5_CONFIG1_1,This register contains the address remapping options for the MIPS CPU physical address. e.g. during boot" hexmask.long 0x5C 0.--31. 1. "Reserved_32,Reserved_32" line.long 0x60 "RGX_CR_MIPS_ADDR_REMAP5_CONFIG2_0,This register contains the address remapping options for the MIPS CPU physical address. e.g. during boot" hexmask.long.tbyte 0x60 12.--31. 1. "ADDR_OUT,4K (12 bits) aligned address used as output for the address remapping" newline bitfld.long 0x60 9.--11. "Reserved_9,Reserved_9" "0,1,2,3,4,5,6,7" newline bitfld.long 0x60 6.--8. "OS_ID,The OS_ID emitted for all address transactions from this region" "0,1,2,3,4,5,6,7" newline bitfld.long 0x60 5. "TRUSTED,Defines whether these accesses are trusted" "0,1" newline hexmask.long.byte 0x60 0.--4. 1. "REGION_SIZE_POW2,Remapped region size or offset size i.e. number of bits from the bottom of the base input address that survive onto the output address. Minimum value of 12" line.long 0x64 "RGX_CR_MIPS_ADDR_REMAP5_CONFIG2_1,This register contains the address remapping options for the MIPS CPU physical address. e.g. during boot" hexmask.long.tbyte 0x64 8.--31. 1. "Reserved_40,Reserved_40" newline hexmask.long.byte 0x64 0.--7. 1. "ADDR_OUT,4K (12 bits) aligned address used as output for the address remapping" rgroup.long 0x868++0x7 line.long 0x0 "RGX_CR_MIPS_ADDR_REMAP_UNMAPPED_STATUS_0,This register contains the unmapped exception status information of the MIPS GPU scheduler." hexmask.long 0x0 0.--31. 1. "ADDRESS,Unmapped MIPS physical address" line.long 0x4 "RGX_CR_MIPS_ADDR_REMAP_UNMAPPED_STATUS_1,This register contains the unmapped exception status information of the MIPS GPU scheduler." hexmask.long 0x4 1.--31. 1. "Reserved_33,Reserved_33" newline bitfld.long 0x4 0. "EVENT,An address from the MIPS was not remapped to a new range in the GPU" "0,1" wgroup.long 0x870++0x7 line.long 0x0 "RGX_CR_MIPS_ADDR_REMAP_UNMAPPED_CLEAR_0,This register contains the configuration options for the MIPS unmapped exception." hexmask.long 0x0 1.--31. 1. "Reserved_1,Reserved_1" newline bitfld.long 0x0 0. "EVENT,Clears the unmapped exception event" "0,1" line.long 0x4 "RGX_CR_MIPS_ADDR_REMAP_UNMAPPED_CLEAR_1,This register contains the configuration options for the MIPS unmapped exception." hexmask.long 0x4 0.--31. 1. "Reserved_1,Reserved_1" group.long 0x878++0x7 line.long 0x0 "RGX_CR_MIPS_ADDR_REMAP_RANGE_CONFIG_0,This register contains the address remapping options for the MIPS CPU physical address. e.g. during boot" hexmask.long.tbyte 0x0 12.--31. 1. "BASE_ADDR_IN,4K (12 bits) aligned address used as a input for the address remapping" newline bitfld.long 0x0 11. "TRUSTED,Defines whether these accesses are trusted" "0,1" newline hexmask.long.byte 0x0 7.--10. 1. "REGION_SIZE,Remapped region size" newline bitfld.long 0x0 6. "Reserved_6,Reserved_6" "0,1" newline hexmask.long.byte 0x0 1.--5. 1. "ENTRY,Select remap entry to configure. Valid range of Entry 0-31" newline bitfld.long 0x0 0. "MODE_ENABLE,When set configure the entry" "0,1" line.long 0x4 "RGX_CR_MIPS_ADDR_REMAP_RANGE_CONFIG_1,This register contains the address remapping options for the MIPS CPU physical address. e.g. during boot" hexmask.long 0x4 4.--31. 1. "ADDR_OUT,4K (12 bits) aligned address used as output for the address remapping" newline bitfld.long 0x4 3. "Reserved_35,Reserved_35" "0,1" newline bitfld.long 0x4 0.--2. "OS_ID,The OS_ID emitted for all address transactions from this region" "0,1,2,3,4,5,6,7" wgroup.long 0x880++0x7 line.long 0x0 "RGX_CR_MIPS_ADDR_REMAP_RANGE_READ_0,This register contains the configuration options for the MIPS remap register read interface." hexmask.long 0x0 6.--31. 1. "Reserved_6,Reserved_6" newline hexmask.long.byte 0x0 1.--5. 1. "ENTRY,MIPS address remap entry to read" newline bitfld.long 0x0 0. "REQUEST,Issue a read request to the MIPS address remap range entries" "0,1" line.long 0x4 "RGX_CR_MIPS_ADDR_REMAP_RANGE_READ_1,This register contains the configuration options for the MIPS remap register read interface." hexmask.long 0x4 0.--31. 1. "Reserved_6,Reserved_6" rgroup.long 0x888++0x7 line.long 0x0 "RGX_CR_MIPS_ADDR_REMAP_RANGE_DATA_0,This register contains the remapping entry information for the MIPS remap register read interface." hexmask.long.tbyte 0x0 12.--31. 1. "BASE_ADDR_IN,4K (12 bits) aligned address used as a input for the address remapping" newline bitfld.long 0x0 11. "TRUSTED,Defines whether these accesses are trusted" "0,1" newline hexmask.long.byte 0x0 7.--10. 1. "REGION_SIZE,Remapped region size" newline hexmask.long.byte 0x0 1.--6. 1. "Reserved_1,Reserved_1" newline bitfld.long 0x0 0. "MODE_ENABLE,When set configures the entry" "0,1" line.long 0x4 "RGX_CR_MIPS_ADDR_REMAP_RANGE_DATA_1,This register contains the remapping entry information for the MIPS remap register read interface." hexmask.long 0x4 4.--31. 1. "ADDR_OUT,4K (12 bits) aligned address used as output for the address remapping" newline bitfld.long 0x4 3. "Reserved_35,Reserved_35" "0,1" newline bitfld.long 0x4 0.--2. "OS_ID,The OS_ID emitted for all address transactions from this region" "0,1,2,3,4,5,6,7" group.long 0x8A0++0xF line.long 0x0 "RGX_CR_MIPS_WRAPPER_IRQ_ENABLE_0,This register contains the configuration options for the RGX firmware interrupts to HOST." hexmask.long 0x0 1.--31. 1. "Reserved_1,Reserved_1" newline bitfld.long 0x0 0. "EVENT,Allow RGX firmware to send interrupts to HOST" "0,1" line.long 0x4 "RGX_CR_MIPS_WRAPPER_IRQ_ENABLE_1,This register contains the configuration options for the RGX firmware interrupts to HOST." hexmask.long 0x4 0.--31. 1. "Reserved_1,Reserved_1" line.long 0x8 "RGX_CR_MIPS_WRAPPER_IRQ_STATUS_0,This register contains the configuration options for the RGX firmware interrupts to HOST." hexmask.long 0x8 1.--31. 1. "Reserved_1,Reserved_1" newline bitfld.long 0x8 0. "EVENT,Indicates an outstanding interrupt to HOST from RGX firmware" "0,1" line.long 0xC "RGX_CR_MIPS_WRAPPER_IRQ_STATUS_1,This register contains the configuration options for the RGX firmware interrupts to HOST." hexmask.long 0xC 0.--31. 1. "Reserved_1,Reserved_1" wgroup.long 0x8B0++0x7 line.long 0x0 "RGX_CR_MIPS_WRAPPER_IRQ_CLEAR_0,This register contains the configuration options for the RGX firmware interrupts to HOST." hexmask.long 0x0 1.--31. 1. "Reserved_1,Reserved_1" newline bitfld.long 0x0 0. "EVENT,Clears the interrupt event to HOST from RGX firmware" "0,1" line.long 0x4 "RGX_CR_MIPS_WRAPPER_IRQ_CLEAR_1,This register contains the configuration options for the RGX firmware interrupts to HOST." hexmask.long 0x4 0.--31. 1. "Reserved_1,Reserved_1" group.long 0x8B8++0x7 line.long 0x0 "RGX_CR_MIPS_WRAPPER_NMI_ENABLE_0,This register contains the configuration options for the RGX firmware non-maskable interrupts to MIPS." hexmask.long 0x0 1.--31. 1. "Reserved_1,Reserved_1" newline bitfld.long 0x0 0. "EVENT,Allow RGX firmware to send non-maskable interrupts to MIPS" "0,1" line.long 0x4 "RGX_CR_MIPS_WRAPPER_NMI_ENABLE_1,This register contains the configuration options for the RGX firmware non-maskable interrupts to MIPS." hexmask.long 0x4 0.--31. 1. "Reserved_1,Reserved_1" wgroup.long 0x8C0++0x7 line.long 0x0 "RGX_CR_MIPS_WRAPPER_NMI_EVENT_0,This register contains the configuration options for the RGX firmware non-maskable interrupts to MIPS." hexmask.long 0x0 1.--31. 1. "Reserved_1,Reserved_1" newline bitfld.long 0x0 0. "TRIGGER,Issue a non-maskable interrupt to the MIPS SI_NMI pin from RGX firmware" "0,1" line.long 0x4 "RGX_CR_MIPS_WRAPPER_NMI_EVENT_1,This register contains the configuration options for the RGX firmware non-maskable interrupts to MIPS." hexmask.long 0x4 0.--31. 1. "Reserved_1,Reserved_1" group.long 0x8C8++0x7 line.long 0x0 "RGX_CR_MIPS_DEBUG_CONFIG_0,This register contains the security and debug configuration options for the MIPS GPU scheduler." hexmask.long 0x0 1.--31. 1. "Reserved_1,Reserved_1" newline bitfld.long 0x0 0. "DISABLE_PROBE_DEBUG,Enable MIPS SecureDebug. Disables EJTAG access to the MIPS core and PC Sampling" "0,1" line.long 0x4 "RGX_CR_MIPS_DEBUG_CONFIG_1,This register contains the security and debug configuration options for the MIPS GPU scheduler." hexmask.long 0x4 0.--31. 1. "Reserved_1,Reserved_1" rgroup.long 0x8D0++0x7 line.long 0x0 "RGX_CR_MIPS_EXCEPTION_STATUS_0,This register contains the exception status information of the MIPS GPU scheduler." hexmask.long 0x0 6.--31. 1. "Reserved_6,Reserved_6" newline bitfld.long 0x0 5. "SI_SLEEP,Reflects the status of the MIPS SI_Sleep pin" "0,1" newline bitfld.long 0x0 4. "SI_NMI_TAKEN,Reflects the status of the MIPS SI_NMITaken pin" "0,1" newline bitfld.long 0x0 3. "SI_NEST_EXL,Reflects the status of the MIPS SI_NESTEXL pin" "0,1" newline bitfld.long 0x0 2. "SI_NEST_ERL,Reflects the status of the MIPS SI_NESTERL pin" "0,1" newline bitfld.long 0x0 1. "SI_EXL,Reflects the status of the MIPS SI_EXL pin" "0,1" newline bitfld.long 0x0 0. "SI_ERL,Reflects the status of the MIPS SI_ERL pin" "0,1" line.long 0x4 "RGX_CR_MIPS_EXCEPTION_STATUS_1,This register contains the exception status information of the MIPS GPU scheduler." hexmask.long 0x4 0.--31. 1. "Reserved_6,Reserved_6" group.long 0x8D8++0xF line.long 0x0 "RGX_CR_MIPS_WRAPPER_FENCE_CONFIG_0,This register contains the fence configuration options for when MIPS emits a memory fence onto the bus" hexmask.long.tbyte 0x0 12.--31. 1. "BASE_ADDR,4K (12 bits) aligned address that serves as the external memory fence base address" newline hexmask.long.byte 0x0 4.--11. 1. "Reserved_4,Reserved_4" newline bitfld.long 0x0 1.--3. "OS_ID,OS_ID of the emitted fence" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 0. "TRUSTED,Defines whether these accesses are trusted" "0,1" line.long 0x4 "RGX_CR_MIPS_WRAPPER_FENCE_CONFIG_1,This register contains the fence configuration options for when MIPS emits a memory fence onto the bus" hexmask.long.tbyte 0x4 8.--31. 1. "Reserved_40,Reserved_40" newline hexmask.long.byte 0x4 0.--7. 1. "BASE_ADDR,4K (12 bits) aligned address that serves as the external memory fence base address" line.long 0x8 "RGX_CR_MIPS_WRAPPER_CACHE_INVAL_0,A write of '1' to this register invalidates the MIPS wrapper L2 cache The cache hardware will clear this bit when the invalidation operation completes" hexmask.long 0x8 1.--31. 1. "Reserved_1,Reserved_1" newline bitfld.long 0x8 0. "PENDING,MIPS wrapper L2 cache is being invalidated" "0,1" line.long 0xC "RGX_CR_MIPS_WRAPPER_CACHE_INVAL_1,A write of '1' to this register invalidates the MIPS wrapper L2 cache The cache hardware will clear this bit when the invalidation operation completes" hexmask.long 0xC 0.--31. 1. "Reserved_1,Reserved_1" rgroup.long 0x8E8++0x7 line.long 0x0 "RGX_CR_MIPS_WRAPPER_STATUS_0,This register contains status information of the MIPS GPU scheduler." hexmask.long.tbyte 0x0 8.--31. 1. "Reserved_8,Reserved_8" newline hexmask.long.byte 0x0 0.--7. 1. "OUTSTANDING_REQUESTS,Outstanding requests by the MIPS" line.long 0x4 "RGX_CR_MIPS_WRAPPER_STATUS_1,This register contains status information of the MIPS GPU scheduler." hexmask.long 0x4 0.--31. 1. "Reserved_8,Reserved_8" group.long 0x900++0x17 line.long 0x0 "RGX_CR_EVENT_TDM_PDS_CODE_0,PDS code segment address for 2D End-of-Tile event shader." hexmask.long 0x0 4.--31. 1. "ADDR,PDS Execution Address for pixel tasks (Positioned as a byte address 128 bit granularity) 4 GB Range" newline hexmask.long.byte 0x0 0.--3. 1. "Reserved_0,Reserved_0" line.long 0x4 "RGX_CR_EVENT_TDM_PDS_CODE_1,PDS code segment address for 2D End-of-Tile event shader." hexmask.long 0x4 0.--31. 1. "Reserved_32,Reserved_32" line.long 0x8 "RGX_CR_EVENT_TDM_PDS_DATA_0,RGX_CR_EVENT_TDM_PDS_DATA_0" hexmask.long 0x8 4.--31. 1. "ADDR,PDS Execution Address for pixel tasks (Positioned as a byte address 128 bit granularity) 4 GB Range" newline hexmask.long.byte 0x8 0.--3. 1. "Reserved_0,Reserved_0" line.long 0xC "RGX_CR_EVENT_TDM_PDS_DATA_1,RGX_CR_EVENT_TDM_PDS_DATA_1" hexmask.long 0xC 0.--31. 1. "Reserved_32,Reserved_32" line.long 0x10 "RGX_CR_EVENT_TDM_PDS_INFO_0,RGX_CR_EVENT_TDM_PDS_INFO_0" hexmask.long.word 0x10 16.--31. 1. "Reserved_16,Reserved_16" newline hexmask.long.byte 0x10 10.--15. 1. "USC_SR_SIZE,USC Shared Register Data Size in 4x128 bit words (0=0) for pixel event task if zero pixel event task is skipped" newline hexmask.long.byte 0x10 5.--9. 1. "TEMP_STRIDE,PDS Temp Size in 64 bit words (0=0) for pixel event tasks" newline hexmask.long.byte 0x10 0.--4. 1. "CONST_SIZE,PDS Data Size in 128 bit words (0=0) for pixel event tasks if zero pixel event task is skipped" line.long 0x14 "RGX_CR_EVENT_TDM_PDS_INFO_1,RGX_CR_EVENT_TDM_PDS_INFO_1" hexmask.long 0x14 0.--31. 1. "Reserved_16,Reserved_16" repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) group.long ($2+0x918)++0x3 line.long 0x0 "RGX_CR_PDS_TDM_BGRND0_BASE_$1,PDS Background Setup Word 0" hexmask.long 0x0 4.--31. 1. "SHADER_ADDR,The pixel shader base is the base address of the PDS Data Segment. The code segment is address is PDS_PIXEL_SHADERBASE + PDS_PIXELSHADERSIZE. The pixel shader program issues the DOUTU for the Fragment Shader only." newline hexmask.long.byte 0x0 0.--3. 1. "Reserved_0,Reserved_0" repeat.end repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) group.long ($2+0x920)++0x3 line.long 0x0 "RGX_CR_PDS_TDM_BGRND1_BASE_$1,PDS Background Setup Word 1" hexmask.long 0x0 4.--31. 1. "VARYING_ADDR,This is the base address of the PDS Data Segment. The code segment is address is PDS_VARYINGBASE + PDS_VARYINGSIZE (PDS_BGRND_SIZEINFO1)." newline hexmask.long.byte 0x0 0.--3. 1. "Reserved_0,Reserved_0" repeat.end group.long 0x928++0xF line.long 0x0 "RGX_CR_PDS_TDM_BGRND2_BASE_0,PDS Background Setup Word 2" hexmask.long 0x0 4.--31. 1. "UNIFORMDATA_ADDR,This points to the DMAs to load the Uniforms (or contains the Uniforms with DOUTW commands)" newline hexmask.long.byte 0x0 0.--3. 1. "Reserved_0,Reserved_0" line.long 0x4 "RGX_CR_PDS_TDM_BGRND2_BASE_1,PDS Background Setup Word 2" hexmask.long 0x4 0.--31. 1. "Reserved_32,Reserved_32" line.long 0x8 "RGX_CR_PDS_TDM_BGRND3_SIZEINFO_0,If any of the size fields are 0. then that program will not be run. PDS_BGRND_PIXELSHADERSIZE is always 2 128 Bit Words" hexmask.long.byte 0x8 27.--31. 1. "PDS_BATCHNUM,The batch ID to be associated with the background" newline hexmask.long.byte 0x8 21.--26. 1. "PDS_UNIFORMSIZE,The size of the Uniform PDS Data Segment in 128 bit words 0=0. 32 max" newline hexmask.long.byte 0x8 15.--20. 1. "PDS_TEXTURESTATESIZE,The size of the Texture PDS Data Segment in 128 bit words 0=0 32 max" newline hexmask.long.byte 0x8 9.--14. 1. "PDS_VARYINGSIZE,The size of the Varying/Coefficient PDS Data Segment in 128 bit words 0=0 32 max" newline hexmask.long.word 0x8 0.--8. 1. "USC_VARYINGSIZE,The size of the Varying/Coefficient USC Common Store Data in 4x128 bit words 0=0. 256 max" line.long 0xC "RGX_CR_PDS_TDM_BGRND3_SIZEINFO_1,If any of the size fields are 0. then that program will not be run. PDS_BGRND_PIXELSHADERSIZE is always 2 128 Bit Words" hexmask.long.word 0xC 23.--31. 1. "Reserved_55,Reserved_55" newline hexmask.long.word 0xC 14.--22. 1. "USC_SHAREDSIZE,The common store allocation size for the shared registers (texture and uniform data commbined) 256 chunks max" newline hexmask.long.byte 0xC 9.--13. 1. "PDS_TEMPSIZE,0 = 0 64 bit words 1 = 1 64 bit word 248 bytes. This applies to coefficient uniform and texture state updates." newline hexmask.long.word 0xC 0.--8. 1. "PDS_BATCHNUM,The batch ID to be associated with the background" group.long 0xB00++0xF line.long 0x0 "RGX_CR_MTS_SCHEDULE_0,This register allows firmware tasks to be scheduled on the META (Garten) core." hexmask.long.tbyte 0x0 9.--31. 1. "Reserved_9,Reserved_9" newline bitfld.long 0x0 8. "HOST,Host Interrupte kick" "0,1" newline bitfld.long 0x0 6.--7. "PRIORITY,DataMaster Priority" "0,1,2,3" newline bitfld.long 0x0 5. "CONTEXT,CONTEXT" "0,1" newline bitfld.long 0x0 4. "TASK,TASK" "0,1" newline hexmask.long.byte 0x0 0.--3. 1. "DM,DataMaster Type" line.long 0x4 "RGX_CR_MTS_SCHEDULE_1,This register allows firmware tasks to be scheduled on the META (Garten) core." hexmask.long 0x4 0.--31. 1. "Reserved_9,Reserved_9" line.long 0x8 "RGX_CR_MTS_PROC_COMPLETE_0,This register allows firmware tasks to signal process completion." hexmask.long 0x8 2.--31. 1. "Reserved_2,Reserved_2" newline bitfld.long 0x8 1. "CONTEXT,CONTEXT" "0,1" newline bitfld.long 0x8 0. "THREAD,Thread number. This is filled in by hardware and can have any value" "0,1" line.long 0xC "RGX_CR_MTS_PROC_COMPLETE_1,This register allows firmware tasks to signal process completion." hexmask.long 0xC 0.--31. 1. "Reserved_2,Reserved_2" rgroup.long 0xB10++0x1F line.long 0x0 "RGX_CR_MTS_BGCTX_SBDATA0_0,This register contains the sideband data for the process running on the background context of thread 0. Reads of this register will be redirected to the correct. thread specific register by hardware." hexmask.long.tbyte 0x0 9.--31. 1. "Reserved_9,Reserved_9" newline bitfld.long 0x0 6.--8. "OS_ID,The OS_ID of the active thread" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 5. "THREAD_ACTIVE,Indicates the thread is active" "0,1" newline bitfld.long 0x0 4. "TASK,TASK" "0,1" newline hexmask.long.byte 0x0 0.--3. 1. "DM,DataMaster Type" line.long 0x4 "RGX_CR_MTS_BGCTX_SBDATA0_1,This register contains the sideband data for the process running on the background context of thread 0. Reads of this register will be redirected to the correct. thread specific register by hardware." hexmask.long 0x4 0.--31. 1. "Reserved_9,Reserved_9" line.long 0x8 "RGX_CR_MTS_BGCTX_SBDATA1_0,This register contains the sideband data for the process running on the background context of thread 1. Reads of this register will be redirected to the correct. thread specific register by hardware." hexmask.long.tbyte 0x8 9.--31. 1. "Reserved_9,Reserved_9" newline bitfld.long 0x8 6.--8. "OS_ID,The OS_ID of the active thread" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 5. "THREAD_ACTIVE,Indicates the thread is active" "0,1" newline bitfld.long 0x8 4. "TASK,TASK" "0,1" newline hexmask.long.byte 0x8 0.--3. 1. "DM,DataMaster Type" line.long 0xC "RGX_CR_MTS_BGCTX_SBDATA1_1,This register contains the sideband data for the process running on the background context of thread 1. Reads of this register will be redirected to the correct. thread specific register by hardware." hexmask.long 0xC 0.--31. 1. "Reserved_9,Reserved_9" line.long 0x10 "RGX_CR_MTS_INTCTX_SBDATA0_0,This register contains the sideband data for the process running on the interrupt context of thread 0. Reads of this register will be redirected to the correct. thread specific register by hardware." hexmask.long 0x10 6.--31. 1. "INT_STATUS,Interrupt Status for 32 event bus lines" newline hexmask.long.byte 0x10 2.--5. 1. "DM,DataMaster Type" newline bitfld.long 0x10 0.--1. "INT_TASK,Kick Request for timer/BG-request/host" "0,1,2,3" line.long 0x14 "RGX_CR_MTS_INTCTX_SBDATA0_1,This register contains the sideband data for the process running on the interrupt context of thread 0. Reads of this register will be redirected to the correct. thread specific register by hardware." hexmask.long.tbyte 0x14 10.--31. 1. "Reserved_42,Reserved_42" newline bitfld.long 0x14 7.--9. "OS_ID,The OS_ID of the active thread" "0,1,2,3,4,5,6,7" newline bitfld.long 0x14 6. "THREAD_ACTIVE,Indicates the thread is active" "0,1" newline hexmask.long.byte 0x14 0.--5. 1. "INT_STATUS,Interrupt Status for 32 event bus lines" line.long 0x18 "RGX_CR_MTS_INTCTX_SBDATA1_0,This register contains the sideband data for the process running on the interrupt context of thread 1. Reads of this register will be redirected to the correct. thread specific register by hardware." hexmask.long 0x18 6.--31. 1. "INT_STATUS,Interrupt Status for 32 event bus lines" newline hexmask.long.byte 0x18 2.--5. 1. "DM,DataMaster Type" newline bitfld.long 0x18 0.--1. "INT_TASK,Kick Request for timer/BG-request/host" "0,1,2,3" line.long 0x1C "RGX_CR_MTS_INTCTX_SBDATA1_1,This register contains the sideband data for the process running on the interrupt context of thread 1. Reads of this register will be redirected to the correct. thread specific register by hardware." hexmask.long.tbyte 0x1C 10.--31. 1. "Reserved_42,Reserved_42" newline bitfld.long 0x1C 7.--9. "OS_ID,The OS_ID of the active thread" "0,1,2,3,4,5,6,7" newline bitfld.long 0x1C 6. "THREAD_ACTIVE,Indicates the thread is active" "0,1" newline hexmask.long.byte 0x1C 0.--5. 1. "INT_STATUS,Interrupt Status for 32 event bus lines" group.long 0xB30++0x27 line.long 0x0 "RGX_CR_MTS_BGCTX_THREAD0_DM_ASSOC_0,This register is the DataMaster assocation for the background context of thread 0. Bit high represents DataMaster being permitted to run on the background context of thread 0." hexmask.long.word 0x0 16.--31. 1. "Reserved_16,Reserved_16" newline hexmask.long.word 0x0 0.--15. 1. "DM_ASSOC,DataMaster Association (Active High)" line.long 0x4 "RGX_CR_MTS_BGCTX_THREAD0_DM_ASSOC_1,This register is the DataMaster assocation for the background context of thread 0. Bit high represents DataMaster being permitted to run on the background context of thread 0." hexmask.long 0x4 0.--31. 1. "Reserved_16,Reserved_16" line.long 0x8 "RGX_CR_MTS_BGCTX_THREAD1_DM_ASSOC_0,This register is the DataMaster assocation for the background context of thread 1. Bit high represents DataMaster being permitted to run on the background context of thread 1." hexmask.long.word 0x8 16.--31. 1. "Reserved_16,Reserved_16" newline hexmask.long.word 0x8 0.--15. 1. "DM_ASSOC,DataMaster Association (Active High)" line.long 0xC "RGX_CR_MTS_BGCTX_THREAD1_DM_ASSOC_1,This register is the DataMaster assocation for the background context of thread 1. Bit high represents DataMaster being permitted to run on the background context of thread 1." hexmask.long 0xC 0.--31. 1. "Reserved_16,Reserved_16" line.long 0x10 "RGX_CR_MTS_INTCTX_THREAD0_DM_ASSOC_0,This register is the DataMaster assocation for the interrupt context of thread 0. Bit high represents DataMaster being permitted to run on the interrupt context of thread 0." hexmask.long.word 0x10 16.--31. 1. "Reserved_16,Reserved_16" newline hexmask.long.word 0x10 0.--15. 1. "DM_ASSOC,DataMaster Association (Active High)" line.long 0x14 "RGX_CR_MTS_INTCTX_THREAD0_DM_ASSOC_1,This register is the DataMaster assocation for the interrupt context of thread 0. Bit high represents DataMaster being permitted to run on the interrupt context of thread 0." hexmask.long 0x14 0.--31. 1. "Reserved_16,Reserved_16" line.long 0x18 "RGX_CR_MTS_INTCTX_THREAD1_DM_ASSOC_0,This register is the DataMaster assocation for the interrupt context of thread 1. Bit high represents DataMaster being permitted to run on the interrupt context of thread 1." hexmask.long.word 0x18 16.--31. 1. "Reserved_16,Reserved_16" newline hexmask.long.word 0x18 0.--15. 1. "DM_ASSOC,DataMaster Association (Active High)" line.long 0x1C "RGX_CR_MTS_INTCTX_THREAD1_DM_ASSOC_1,This register is the DataMaster assocation for the interrupt context of thread 1. Bit high represents DataMaster being permitted to run on the interrupt context of thread 1." hexmask.long 0x1C 0.--31. 1. "Reserved_16,Reserved_16" line.long 0x20 "RGX_CR_MTS_GARTEN_WRAPPER_CONFIG_0,This register contains the configuration options for the Garten wrapper." hexmask.long.tbyte 0x20 12.--31. 1. "FENCE_ADDR,4k page address to be used for fence requests" newline hexmask.long.word 0x20 1.--11. 1. "Reserved_1,Reserved_1" newline bitfld.long 0x20 0. "IDLE_CTRL,IDLE_CTRL" "0,1" line.long 0x24 "RGX_CR_MTS_GARTEN_WRAPPER_CONFIG_1,This register contains the configuration options for the Garten wrapper." hexmask.long.word 0x24 16.--31. 1. "Reserved_48,Reserved_48" newline hexmask.long.byte 0x24 12.--15. 1. "FENCE_PC_BASE,Page Catalogue base address number to be used for fence requests" newline hexmask.long.byte 0x24 8.--11. 1. "FENCE_DM,Data master value to be used for fence requests" newline hexmask.long.byte 0x24 0.--7. 1. "FENCE_ADDR,4k page address to be used for fence requests" repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) group.long ($2+0xB58)++0x3 line.long 0x0 "RGX_CR_MTS_DM0_INTERRUPT_ENABLE_$1,Interrupt enable status register for DataMaster 0" hexmask.long 0x0 0.--31. 1. "INT_ENABLE,Interrupt Enable" repeat.end repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) group.long ($2+0xB60)++0x3 line.long 0x0 "RGX_CR_MTS_DM1_INTERRUPT_ENABLE_$1,Interrupt enable status register for DataMaster 1" hexmask.long 0x0 0.--31. 1. "INT_ENABLE,Interrupt Enable" repeat.end repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) group.long ($2+0xB68)++0x3 line.long 0x0 "RGX_CR_MTS_DM2_INTERRUPT_ENABLE_$1,Interrupt enable status register for DataMaster 2" hexmask.long 0x0 0.--31. 1. "INT_ENABLE,Interrupt Enable" repeat.end repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) group.long ($2+0xB70)++0x3 line.long 0x0 "RGX_CR_MTS_DM3_INTERRUPT_ENABLE_$1,Interrupt enable status register for DataMaster 3" hexmask.long 0x0 0.--31. 1. "INT_ENABLE,Interrupt Enable" repeat.end repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) group.long ($2+0xB78)++0x3 line.long 0x0 "RGX_CR_MTS_DM4_INTERRUPT_ENABLE_$1,Interrupt enable status register for DataMaster 4" hexmask.long 0x0 0.--31. 1. "INT_ENABLE,Interrupt Enable" repeat.end repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) group.long ($2+0xB80)++0x3 line.long 0x0 "RGX_CR_MTS_DM5_INTERRUPT_ENABLE_$1,Interrupt enable status register for DataMaster 5" hexmask.long 0x0 0.--31. 1. "INT_ENABLE,Interrupt Enable" repeat.end repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) group.long ($2+0xB88)++0x3 line.long 0x0 "RGX_CR_MTS_EVENT_MASK_$1,Mask interrupt events" hexmask.long 0x0 0.--31. 1. "MASK,DESCRIPTION" repeat.end repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) wgroup.long ($2+0xB90)++0x3 line.long 0x0 "RGX_CR_MTS_EVENT_CLEAR_$1,Clear internal interrupt registers" hexmask.long 0x0 0.--31. 1. "CLEAR,DESCRIPTION" repeat.end rgroup.long 0xB98++0x17 line.long 0x0 "RGX_CR_MTS_INTCTX_0,This register contains the sideband data for the MTS internal interrupt context registers" bitfld.long 0x0 30.--31. "Reserved_30,Reserved_30" "0,1,2,3" newline hexmask.long.byte 0x0 22.--29. 1. "DM_HOST_SCHEDULE,A 1 bit counter per DM for host requests" newline hexmask.long.byte 0x0 16.--21. 1. "Reserved_16,Reserved_16" newline hexmask.long.byte 0x0 8.--15. 1. "DM_TIMER_SCHEDULE,A 1 bit counter per DM for timer requests" newline hexmask.long.byte 0x0 0.--7. 1. "DM_INTERRUPT_SCHEDULE,A 1 bit counter per DM for interrupt requests" line.long 0x4 "RGX_CR_MTS_INTCTX_1,This register contains the sideband data for the MTS internal interrupt context registers" hexmask.long 0x4 0.--31. 1. "Reserved_30,Reserved_30" line.long 0x8 "RGX_CR_MTS_BGCTX_0,This register contains the sideband data for the MTS internal background context registers" hexmask.long.tbyte 0x8 8.--31. 1. "Reserved_8,Reserved_8" newline hexmask.long.byte 0x8 0.--7. 1. "DM_NONCOUNTED_SCHEDULE,A 1 bit counter per DM for non-counted background request" line.long 0xC "RGX_CR_MTS_BGCTX_1,This register contains the sideband data for the MTS internal background context registers" hexmask.long 0xC 0.--31. 1. "Reserved_8,Reserved_8" line.long 0x10 "RGX_CR_MTS_BGCTX_COUNTED_SCHEDULE_0,This register contains the sideband data for the MTS internal counted background context counters" hexmask.long.byte 0x10 24.--31. 1. "DM3,A 8 bit counter for DM3" newline hexmask.long.byte 0x10 16.--23. 1. "DM2,A 8 bit counter for DM2" newline hexmask.long.byte 0x10 8.--15. 1. "DM1,A 8 bit counter for DM1" newline hexmask.long.byte 0x10 0.--7. 1. "DM0,A 8 bit counter for DM0" line.long 0x14 "RGX_CR_MTS_BGCTX_COUNTED_SCHEDULE_1,This register contains the sideband data for the MTS internal counted background context counters" hexmask.long.word 0x14 16.--31. 1. "Reserved_48,Reserved_48" newline hexmask.long.byte 0x14 8.--15. 1. "DM5,A 8 bit counter for DM5" newline hexmask.long.byte 0x14 0.--7. 1. "DM4,A 8 bit counter for DM4" repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) rgroup.long ($2+0xBB0)++0x3 line.long 0x0 "RGX_CR_MTS_GPU_INT_STATUS_$1,This register contains the sideband data for the MTS internal GPU interrupt status" hexmask.long 0x0 0.--31. 1. "STATUS,A 32 bit register for recored GPU events" repeat.end group.long 0xBC0++0xF line.long 0x0 "RGX_CR_MTS_OS_PRIORITY_0,Operating System Priority" hexmask.long.word 0x0 16.--31. 1. "Reserved_16,Reserved_16" newline bitfld.long 0x0 14.--15. "ID7,Scheduling priority for operating system 7" "0,1,2,3" newline bitfld.long 0x0 12.--13. "ID6,Scheduling priority for operating system 6" "0,1,2,3" newline bitfld.long 0x0 10.--11. "ID5,Scheduling priority for operating system 5" "0,1,2,3" newline bitfld.long 0x0 8.--9. "ID4,Scheduling priority for operating system 4" "0,1,2,3" newline bitfld.long 0x0 6.--7. "ID3,Scheduling priority for operating system 3" "0,1,2,3" newline bitfld.long 0x0 4.--5. "ID2,Scheduling priority for operating system 2" "0,1,2,3" newline bitfld.long 0x0 2.--3. "ID1,Scheduling priority for operating system 1" "0,1,2,3" newline bitfld.long 0x0 0.--1. "ID0,Scheduling priority for operating system 0" "0,1,2,3" line.long 0x4 "RGX_CR_MTS_OS_PRIORITY_1,Operating System Priority" hexmask.long 0x4 0.--31. 1. "Reserved_16,Reserved_16" line.long 0x8 "RGX_CR_MTS_SCHEDULE_ENABLE_0,This register is an active-high mask. When the bit is 0. the MTS_SCHEDULE kick from the corresponding Guest OS is silently discarded. This allows the FW to mask out a Guest OS in order to prevent denial-of-service style.." hexmask.long.tbyte 0x8 8.--31. 1. "Reserved_8,Reserved_8" newline hexmask.long.byte 0x8 0.--7. 1. "MASK,MASK" line.long 0xC "RGX_CR_MTS_SCHEDULE_ENABLE_1,This register is an active-high mask. When the bit is 0. the MTS_SCHEDULE kick from the corresponding Guest OS is silently discarded. This allows the FW to mask out a Guest OS in order to prevent denial-of-service style.." hexmask.long 0xC 0.--31. 1. "Reserved_8,Reserved_8" rgroup.long 0xBD8++0x7 line.long 0x0 "RGX_CR_IRQ_OS0_EVENT_STATUS_0,This register indicates the source of a per-OS host interrupt. This register is set by the firmware and cleared by the host." hexmask.long 0x0 1.--31. 1. "Reserved_1,Reserved_1" newline bitfld.long 0x0 0. "SOURCE,SOURCE" "0,1" line.long 0x4 "RGX_CR_IRQ_OS0_EVENT_STATUS_1,This register indicates the source of a per-OS host interrupt. This register is set by the firmware and cleared by the host." hexmask.long 0x4 0.--31. 1. "Reserved_1,Reserved_1" group.long 0xBE0++0xF line.long 0x0 "RGX_CR_HOST_IRQ_0,This register triggers a per-OS host interrupt. The hardware sets the corresponding RGX_CR_IRQ_OS_EVENT_STATUS register." hexmask.long 0x0 3.--31. 1. "Reserved_3,Reserved_3" newline bitfld.long 0x0 0.--2. "OSID,Indicates the Guest OS for the interrupt" "0,1,2,3,4,5,6,7" line.long 0x4 "RGX_CR_HOST_IRQ_1,This register triggers a per-OS host interrupt. The hardware sets the corresponding RGX_CR_IRQ_OS_EVENT_STATUS register." hexmask.long 0x4 0.--31. 1. "Reserved_3,Reserved_3" line.long 0x8 "RGX_CR_IRQ_OS0_EVENT_CLEAR_0,This register clears a per-OS host interrupt." hexmask.long 0x8 1.--31. 1. "Reserved_1,Reserved_1" newline bitfld.long 0x8 0. "SOURCE,SOURCE" "0,1" line.long 0xC "RGX_CR_IRQ_OS0_EVENT_CLEAR_1,This register clears a per-OS host interrupt." hexmask.long 0xC 0.--31. 1. "Reserved_1,Reserved_1" group.long 0xBF8++0x5F line.long 0x0 "RGX_CR_META_BOOT_0,RGX_CR_META_BOOT_0" hexmask.long 0x0 1.--31. 1. "Reserved_1,Reserved_1" newline bitfld.long 0x0 0. "MODE,0 = Don't boot 1 = Boot" "Don't boot,Boot" line.long 0x4 "RGX_CR_META_BOOT_1,RGX_CR_META_BOOT_1" hexmask.long 0x4 0.--31. 1. "Reserved_1,Reserved_1" line.long 0x8 "RGX_CR_TE_AA_0,This register controls the anti-aliasing mode of the Tiling Co-Processor. independent control is provided in both X & Y axis. 2xmsaa is achieved by enabling X2 - does not affect TE 4xmsaa is achieved by enabling Y and X2 - TE does AA on Y.." hexmask.long 0x8 3.--31. 1. "Reserved_3,Reserved_3" newline bitfld.long 0x8 2. "Y,Anti-Aliasing in Y Plane Enabled" "0,1" newline bitfld.long 0x8 1. "X,Anti-Aliasing in X Plane Enabled" "0,1" newline bitfld.long 0x8 0. "X2,2x Anti-Aliasing Enabled affects PPP only" "0,1" line.long 0xC "RGX_CR_TE_AA_1,This register controls the anti-aliasing mode of the Tiling Co-Processor. independent control is provided in both X & Y axis. 2xmsaa is achieved by enabling X2 - does not affect TE 4xmsaa is achieved by enabling Y and X2 - TE does AA on Y.." hexmask.long 0xC 0.--31. 1. "Reserved_3,Reserved_3" line.long 0x10 "RGX_CR_TE_MTILE1_0,MacroTile Boundaries X Plane" hexmask.long.byte 0x10 27.--31. 1. "Reserved_27,Reserved_27" newline hexmask.long.word 0x10 18.--26. 1. "X1,X1 MacroTile boundary left tile X for second column of macrotiles (16MT mode) - 32 pixels across tile" newline hexmask.long.word 0x10 9.--17. 1. "X2,X2 MacroTile boundary left tile X for third(16MT) column of macrotiles - 32 pixels across tile" newline hexmask.long.word 0x10 0.--8. 1. "X3,X3 MacroTile boundary left tile X for fourth column of macrotiles (16MT) - 32 pixels across tile" line.long 0x14 "RGX_CR_TE_MTILE1_1,MacroTile Boundaries X Plane" hexmask.long 0x14 0.--31. 1. "Reserved_27,Reserved_27" line.long 0x18 "RGX_CR_TE_MTILE2_0,MacroTile Boundaries Y Plane." hexmask.long.byte 0x18 27.--31. 1. "Reserved_27,Reserved_27" newline hexmask.long.word 0x18 18.--26. 1. "Y1,X1 MacroTile boundary ltop tile Y for second column of macrotiles (16MT mode) - 32 pixels tile height" newline hexmask.long.word 0x18 9.--17. 1. "Y2,X2 MacroTile boundary top tile Y for third(16MT) column of macrotiles - 32 pixels tile height" newline hexmask.long.word 0x18 0.--8. 1. "Y3,X3 MacroTile boundary top tile Y for fourth column of macrotiles (16MT) - 32 pixels tile height" line.long 0x1C "RGX_CR_TE_MTILE2_1,MacroTile Boundaries Y Plane." hexmask.long 0x1C 0.--31. 1. "Reserved_27,Reserved_27" line.long 0x20 "RGX_CR_TE_SCREEN_0,In order to perform the tiling operation and generate the display list the maximum screen size must be configured in terms of the number of tiles in X & Y axis." hexmask.long.word 0x20 21.--31. 1. "Reserved_21,Reserved_21" newline hexmask.long.word 0x20 12.--20. 1. "YMAX,Maximum Y tile address visible on screen 32 pixel tile height 16Kx16K max screen size" newline bitfld.long 0x20 9.--11. "Reserved_9,Reserved_9" "0,1,2,3,4,5,6,7" newline hexmask.long.word 0x20 0.--8. 1. "XMAX,Maximum X tile address visible on screen 32 pixel tile width 16Kx16K max screen size" line.long 0x24 "RGX_CR_TE_SCREEN_1,In order to perform the tiling operation and generate the display list the maximum screen size must be configured in terms of the number of tiles in X & Y axis." hexmask.long 0x24 0.--31. 1. "Reserved_21,Reserved_21" line.long 0x28 "RGX_CR_TE_MTILE_0,In order to perform the tiling operation and generate the display list the maximum screen size must be configured in terms of the number of tiles in X & Y axis." hexmask.long.word 0x28 19.--31. 1. "Reserved_19,Reserved_19" newline hexmask.long.tbyte 0x28 0.--18. 1. "STRIDE,Number of tiles in a Macrotile. Stride = (XTile * YTiles) tiles 32 pixels across by 32 pixels" line.long 0x2C "RGX_CR_TE_MTILE_1,In order to perform the tiling operation and generate the display list the maximum screen size must be configured in terms of the number of tiles in X & Y axis." hexmask.long 0x2C 0.--31. 1. "Reserved_19,Reserved_19" line.long 0x30 "RGX_CR_TE_PSG_0,This register defines the global control for the Parameter Stream Generator within the Tiling Co-Processor. This module formats the display list generated by the Tiling Co-Processor." hexmask.long.word 0x30 22.--31. 1. "Reserved_22,Reserved_22" newline bitfld.long 0x30 21. "CS_SIZE,Size of control stream chunk. 0x0 512 bit 0x1 1024 bit" "0,1" newline bitfld.long 0x30 20. "ENABLE_PWR_GATE_STATE,Enables TE PSG power gate state init. 0x0 Disable 0x1 Enable" "0,1" newline bitfld.long 0x30 19. "ENABLE_CONTEXT_STATE_RESTORE,Enables sampling of Driver TE_STATE_ISP_STATE_ID and TE_ACTIVE_MTILE registers on context switch/restore when set when reset current local value is preserved." "0,1" newline bitfld.long 0x30 18. "ZONLYRENDER,Don't invalidate Tail Pointer Cache entries on a Terminate command. Only effective when COMPLETEONTERMINATE is 0x0 0x0 Do Invalidate 0x1 Don't Invalidate" "0,1" newline bitfld.long 0x30 17. "COMPLETEONTERMINATE,0x1 Write region headers terminate streams and invalidate tail pointer cache entries on terminate. 0x0 If ZONLYRENDER = 0x0 then force an Interrupt however if ZONLYRENDER = 0x1 then write region headers and terminate streams." "0,1" newline bitfld.long 0x30 15.--16. "Reserved_15,Reserved_15" "0,1,2,3" newline bitfld.long 0x30 14. "CACHE_BYPASS,when set VCE sets its write only cache to bypass mode effectively disabling the cache" "0,1" newline bitfld.long 0x30 13. "FORCENEWSTATE,Always embed state information in control stream. Debug only." "0,1" newline bitfld.long 0x30 11.--12. "Reserved_11,Reserved_11" "0,1,2,3" newline hexmask.long.word 0x30 0.--10. 1. "REGION_STRIDE,Number of 4kB Pages devoted to region headers for each Render Target - max needed = 0x500" line.long 0x34 "RGX_CR_TE_PSG_1,This register defines the global control for the Parameter Stream Generator within the Tiling Co-Processor. This module formats the display list generated by the Tiling Co-Processor." hexmask.long 0x34 0.--31. 1. "Reserved_22,Reserved_22" line.long 0x38 "RGX_CR_TE_PSG_TERMINATE_0,This register can be written by the driver to define what the TA should terminate tile control streams with. Default value is 0x00000002. however this can be replaced with a link pointer to some driver defined control stream." hexmask.long 0x38 0.--31. 1. "DWORD,Double-word to terminate all tile control streams with." line.long 0x3C "RGX_CR_TE_PSG_TERMINATE_1,This register can be written by the driver to define what the TA should terminate tile control streams with. Default value is 0x00000002. however this can be replaced with a link pointer to some driver defined control stream." hexmask.long.tbyte 0x3C 8.--31. 1. "Reserved_40,Reserved_40" newline hexmask.long.byte 0x3C 0.--7. 1. "BYTE,Byte to terminate all tile control streams with." line.long 0x40 "RGX_CR_TE_PSGREGION_ADDR_0,This register defines the base address in memory of the Region Header writes by the TA. Region headers are the first part of the display list and contain an entry per tile with information on global setup and a link address to.." hexmask.long 0x40 6.--31. 1. "BASE,16GB Addressable 512-bit aligned Base Address for Region Header writes" newline hexmask.long.byte 0x40 0.--5. 1. "Reserved_0,Reserved_0" line.long 0x44 "RGX_CR_TE_PSGREGION_ADDR_1,This register defines the base address in memory of the Region Header writes by the TA. Region headers are the first part of the display list and contain an entry per tile with information on global setup and a link address to.." hexmask.long.tbyte 0x44 8.--31. 1. "Reserved_40,Reserved_40" newline hexmask.long.byte 0x44 2.--7. 1. "HEAP,1TB Addressable 16GB aligned Heap Address for Region Header writes" newline bitfld.long 0x44 0.--1. "BASE,16GB Addressable 512-bit aligned Base Address for Region Header writes" "0,1,2,3" line.long 0x48 "RGX_CR_TE_TPC_ADDR_0,This register defines the base address in memory of the Tail Pointer Cache. A tail pointer is the current last address written to for a tiles individual display list. an entry for active tiles is maintained as primitives are.." hexmask.long 0x48 6.--31. 1. "BASE,16GB Addressable 512-bit aligned Base Address for Tail Pointer Cache entries. The tail pointer is the current last address written to for a control stream for a tile." newline hexmask.long.byte 0x48 0.--5. 1. "Reserved_0,Reserved_0" line.long 0x4C "RGX_CR_TE_TPC_ADDR_1,This register defines the base address in memory of the Tail Pointer Cache. A tail pointer is the current last address written to for a tiles individual display list. an entry for active tiles is maintained as primitives are.." hexmask.long.tbyte 0x4C 8.--31. 1. "Reserved_40,Reserved_40" newline hexmask.long.byte 0x4C 2.--7. 1. "HEAP,1TB Addressable 16GB aligned Heap Address for Tail Pointer Cache." newline bitfld.long 0x4C 0.--1. "BASE,16GB Addressable 512-bit aligned Base Address for Tail Pointer Cache entries. The tail pointer is the current last address written to for a control stream for a tile." "0,1,2,3" line.long 0x50 "RGX_CR_TE_TPC_0,This register defines the TPC Memory footprint size per Render Target as a Stride of 4KB pages" hexmask.long.tbyte 0x50 12.--31. 1. "Reserved_12,Reserved_12" newline hexmask.long.word 0x50 0.--11. 1. "STRIDE,Number of 4KB pages per Render Target in each TPC footprint - max = 2048" line.long 0x54 "RGX_CR_TE_TPC_1,This register defines the TPC Memory footprint size per Render Target as a Stride of 4KB pages" hexmask.long 0x54 0.--31. 1. "Reserved_12,Reserved_12" line.long 0x58 "RGX_CR_TE_TPC_CONTEXT_0,The Tail Pointer Cache is used to keep track of the last address written to for a particular tile. this is stored in a mixture of on chip cache and external memory. Under certain circumstances it is neccesary to either reset the.." bitfld.long 0x58 31. "CLEAR_PENDING,Reset contents of Tail Pointer Cache" "0,1" newline bitfld.long 0x58 30. "FLUSH_PENDING,Flush contents of Tail Pointer Cache to Memory" "0,1" newline hexmask.long 0x58 0.--29. 1. "Reserved_0,Reserved_0" line.long 0x5C "RGX_CR_TE_TPC_CONTEXT_1,The Tail Pointer Cache is used to keep track of the last address written to for a particular tile. this is stored in a mixture of on chip cache and external memory. Under certain circumstances it is neccesary to either reset the.." hexmask.long 0x5C 0.--31. 1. "Reserved_32,Reserved_32" rgroup.long 0xC58++0xF line.long 0x0 "RGX_CR_TE_RGNBBOX_X_0,Reset or enabled by the PPP_RESETBBOX and PPP_UPDATEBBOX fields in the PPPControl word of the Input Parameter format. This is the maximum extent in X of the post transformed. clipped data before region clipping." hexmask.long.byte 0x0 26.--31. 1. "Reserved_26,Reserved_26" newline hexmask.long.word 0x0 16.--25. 1. "MAX,XMax value for maintained Region Generator Bounding Box tiles 32 pixels in width" newline hexmask.long.byte 0x0 10.--15. 1. "Reserved_10,Reserved_10" newline hexmask.long.word 0x0 0.--9. 1. "MIN,XMin value for maintained Region Generator Bounding Box tiles 32 pixels in width" line.long 0x4 "RGX_CR_TE_RGNBBOX_X_1,Reset or enabled by the PPP_RESETBBOX and PPP_UPDATEBBOX fields in the PPPControl word of the Input Parameter format. This is the maximum extent in X of the post transformed. clipped data before region clipping." hexmask.long 0x4 0.--31. 1. "Reserved_26,Reserved_26" line.long 0x8 "RGX_CR_TE_RGNBBOX_Y_0,Reset or enabled by the PPP_RESETBBOX and PPP_UPDATEBBOX fields in the PPP Control word of the Input Parameter format. This is the maximum extent in Y of the post transformed. clipped data before region clipping." hexmask.long.byte 0x8 26.--31. 1. "Reserved_26,Reserved_26" newline hexmask.long.word 0x8 16.--25. 1. "MAX,YMax value for maintained Region Generator Bounding Box tiles 16 pixels in height" newline hexmask.long.byte 0x8 10.--15. 1. "Reserved_10,Reserved_10" newline hexmask.long.word 0x8 0.--9. 1. "MIN,YMin value for maintained Region Generator Bounding Box tiles 16 pixels in height" line.long 0xC "RGX_CR_TE_RGNBBOX_Y_1,Reset or enabled by the PPP_RESETBBOX and PPP_UPDATEBBOX fields in the PPP Control word of the Input Parameter format. This is the maximum extent in Y of the post transformed. clipped data before region clipping." hexmask.long 0xC 0.--31. 1. "Reserved_26,Reserved_26" group.long 0xC68++0x7 line.long 0x0 "RGX_CR_TE_RGNHDR_INIT_0,A write of '1' to this register starts the TE Region Header Initialisation Sequence The TE HW will clear the PENDING bit once the operation is complete" hexmask.long 0x0 1.--31. 1. "Reserved_1,Reserved_1" newline bitfld.long 0x0 0. "PENDING,Start TE Region Header Initialisation" "0,1" line.long 0x4 "RGX_CR_TE_RGNHDR_INIT_1,A write of '1' to this register starts the TE Region Header Initialisation Sequence The TE HW will clear the PENDING bit once the operation is complete" hexmask.long 0x4 0.--31. 1. "Reserved_1,Reserved_1" group.long 0xC78++0x17 line.long 0x0 "RGX_CR_PPP_GRIDOFFSET_0,Sample position grid offset for use when MSAA/ODAA is DISABLED DX (0.0.0.0) OpenGL (0.5.0.5) Acts as the 9th multisample position when MSAA is ENABLED." hexmask.long.tbyte 0x0 8.--31. 1. "Reserved_8,Reserved_8" newline hexmask.long.byte 0x0 4.--7. 1. "GRID_Y,Unsigned sub-pixel offset" newline hexmask.long.byte 0x0 0.--3. 1. "GRID_X,Unsigned sub-pixel offset" line.long 0x4 "RGX_CR_PPP_GRIDOFFSET_1,Sample position grid offset for use when MSAA/ODAA is DISABLED DX (0.0.0.0) OpenGL (0.5.0.5) Acts as the 9th multisample position when MSAA is ENABLED." hexmask.long 0x4 0.--31. 1. "Reserved_8,Reserved_8" line.long 0x8 "RGX_CR_PPP_MULTISAMPLECTL_0,Sample position grid offset for use in 2x. 4x. 8xMSAA and ODAA modes." hexmask.long.byte 0x8 28.--31. 1. "MSAA_Y3,Unsigned sub-pixel offset for the 4th multisample Y position" newline hexmask.long.byte 0x8 24.--27. 1. "MSAA_X3,Unsigned sub-pixel offset for the 4th multisample X position" newline hexmask.long.byte 0x8 20.--23. 1. "MSAA_Y2,Unsigned sub-pixel offset for the 3rd multisample Y position" newline hexmask.long.byte 0x8 16.--19. 1. "MSAA_X2,Unsigned sub-pixel offset for the 3rd multisample X position" newline hexmask.long.byte 0x8 12.--15. 1. "MSAA_Y1,Unsigned sub-pixel offset for the 2nd multisample Y position" newline hexmask.long.byte 0x8 8.--11. 1. "MSAA_X1,Unsigned sub-pixel offset for the 2nd multisample X position" newline hexmask.long.byte 0x8 4.--7. 1. "MSAA_Y0,Unsigned sub-pixel offset for the 1st multisample Y position" newline hexmask.long.byte 0x8 0.--3. 1. "MSAA_X0,Unsigned sub-pixel offset for the 1st multisample X position" line.long 0xC "RGX_CR_PPP_MULTISAMPLECTL_1,Sample position grid offset for use in 2x. 4x. 8xMSAA and ODAA modes." hexmask.long 0xC 0.--31. 1. "Reserved_32,Reserved_32" line.long 0x10 "RGX_CR_PPP_CTRL_0,This register controls the global setup of the PPP." hexmask.long.tbyte 0x10 13.--31. 1. "Reserved_13,Reserved_13" newline bitfld.long 0x10 12. "VPT_SCISSOR,When 0 the PPP will insert state updates on change of VPT ID When 1 this feature is disabled" "0,1" newline bitfld.long 0x10 11. "FLUSH_MODE,when 0 PPP will supress end of draw call flushed from reaching the Clipper and TA pipeline This will break batch number funstionality but will give better primitive block utiliastion. when 1 PPP will not supress any flushes" "0,1" newline bitfld.long 0x10 10. "BFCULL_RESTRICT_CLIP,When set clipped primitives are only back-face culled after the clipper. 0 Enable early back face cull for clipped primitives 1 Disable early cull" "0,1" newline bitfld.long 0x10 9. "FIXED_POINT_FORMAT,When set the PPP will use a fixed point format of 16. 8 rather than 16.4. 0 16.4 fixed point format 1 16.8 fixed point format" "0,1" newline bitfld.long 0x10 8. "DEFAULT_POINT_SIZE,When set the PPP will use the default point size rather than reading it from the vertex. 0 Point size read from vertex 1 Default point size of 3F800000 used" "0,1" newline bitfld.long 0x10 7. "BFCULL1_DISABLE,Disable for fully clipped culling 0 First back face cull block enabled 1 First back face cull block disabled" "0,1" newline bitfld.long 0x10 6. "BFCULL2_DISABLE,Disable for fully clipped culling 0 Second back face cull block enabled 1 Second back face cull block disabled" "0,1" newline bitfld.long 0x10 5. "FCCULL_DISABLE,Disable for fully clipped culling 0 Fully clipped culling enabled 1 Fully clipped culling disabled" "0,1" newline bitfld.long 0x10 4. "OSCULL_DISABLE,Disable for off screen culling 0 Off screen culling enabled 1 Off screen culling disabled" "0,1" newline bitfld.long 0x10 3. "PSOCULL_DISABLE,Disable for perfect small object culling 0 Perfect small object culling enabled 1 Perfect small object culling disabled" "0,1" newline bitfld.long 0x10 2. "SOCULL_DISABLE,Disable for small object culling 0 Small object culling enabled 1 Small object culling disabled" "0,1" newline bitfld.long 0x10 1. "WCLAMPEN,Enable W clamping 0 W clamping disabled 1 W clamping enabled" "0,1" newline bitfld.long 0x10 0. "OPENGL,Select OpenGL or D3D mode 0 D3D 1 OpenGL" "0,1" line.long 0x14 "RGX_CR_PPP_CTRL_1,This register controls the global setup of the PPP." hexmask.long 0x14 0.--31. 1. "Reserved_13,Reserved_13" repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) group.long ($2+0xC90)++0x3 line.long 0x0 "RGX_CR_PPP_WCLAMP_$1,RGX_CR_PPP_WCLAMP_0" hexmask.long 0x0 0.--31. 1. "CLAMP_VALUE,Clamp value for W clamping. See the Input parameter format viewport transform for details. Clamp is applied post viewport transform if the w value is less than the WCOMPARE value. Note that this value cannot be negative." repeat.end group.long 0xC98++0xF line.long 0x0 "RGX_CR_PPP_SCREEN_0,In order to perform the tiling operation and generate the display list the maximum screen size must be configured in terms of the number of pixels in X & Y axis since this may not be the same as the number of tiles defined in the.." bitfld.long 0x0 31. "Reserved_31,Reserved_31" "0,1" newline hexmask.long.word 0x0 16.--30. 1. "PIXYMAX,Screen height in pixels. (16K x 16K max screen size)" newline bitfld.long 0x0 15. "Reserved_15,Reserved_15" "0,1" newline hexmask.long.word 0x0 0.--14. 1. "PIXXMAX,Screen width in pixels.(16K x 16K max screen size)" line.long 0x4 "RGX_CR_PPP_SCREEN_1,In order to perform the tiling operation and generate the display list the maximum screen size must be configured in terms of the number of pixels in X & Y axis since this may not be the same as the number of tiles defined in the.." hexmask.long 0x4 0.--31. 1. "Reserved_31,Reserved_31" line.long 0x8 "RGX_CR_VCE_CTRL_0,This register controls the global setup of the VCE." hexmask.long 0x8 4.--31. 1. "Reserved_4,Reserved_4" newline bitfld.long 0x8 3. "CACHE_BYPASS,when set VCE sets its write only cache to bypass mode effectively disabling the cache" "0,1" newline bitfld.long 0x8 2. "Reserved_2,Reserved_2" "0,1" newline bitfld.long 0x8 1. "TWO_ORIGIN_DISABLE,When set raw mode is selected in place of 2-origin delta stream compression mode" "0,1" newline bitfld.long 0x8 0. "COMPRESS_DISABLE,When set vertex compression is disabled. I.e. raw mode is forced for all vertices" "0,1" line.long 0xC "RGX_CR_VCE_CTRL_1,This register controls the global setup of the VCE." hexmask.long 0xC 0.--31. 1. "Reserved_4,Reserved_4" wgroup.long 0xCA8++0x7 line.long 0x0 "RGX_CR_TE_CLEAR_LISTS_AFTER_ABORT_0,A write of '1' to this register tells the TE we are resuming after an Abort and Partial Render Sequence" hexmask.long 0x0 1.--31. 1. "Reserved_1,Reserved_1" newline bitfld.long 0x0 0. "PULSE,TE Clears all references after Abort and Partial Render Sequence" "0,1" line.long 0x4 "RGX_CR_TE_CLEAR_LISTS_AFTER_ABORT_1,A write of '1' to this register tells the TE we are resuming after an Abort and Partial Render Sequence" hexmask.long 0x4 0.--31. 1. "Reserved_1,Reserved_1" group.long 0xCB0++0x17 line.long 0x0 "RGX_CR_TA_RTC_ADDR_0,This register defines the base address in memory of the TA Render Target Caches. for the VCE. TEAC and PSG" hexmask.long 0x0 6.--31. 1. "BASE,16GB Addressabreadonly le 512-bit aligned Base Address for TA Render Target Caches." newline hexmask.long.byte 0x0 0.--5. 1. "Reserved_0,Reserved_0" line.long 0x4 "RGX_CR_TA_RTC_ADDR_1,This register defines the base address in memory of the TA Render Target Caches. for the VCE. TEAC and PSG" hexmask.long.tbyte 0x4 8.--31. 1. "Reserved_40,Reserved_40" newline hexmask.long.byte 0x4 2.--7. 1. "HEAP,1TB Addressable 16GB aligned Heap Address for TA Render Target Caches" newline bitfld.long 0x4 0.--1. "BASE,16GB Addressabreadonly le 512-bit aligned Base Address for TA Render Target Caches." "0,1,2,3" line.long 0x8 "RGX_CR_TA_RTC_CTRL_0,A write of '1' to Bit 0 of this register Clears the RTC. A write of '1' to Bit 1 of this register Stores the RTC to memory (address specified in TA_RTC_ADDR register)" hexmask.long 0x8 2.--31. 1. "Reserved_2,Reserved_2" newline bitfld.long 0x8 1. "STORE_PENDING,Store RTC" "0,1" newline bitfld.long 0x8 0. "CLEAR_PENDING,Clear RTC" "0,1" line.long 0xC "RGX_CR_TA_RTC_CTRL_1,A write of '1' to Bit 0 of this register Clears the RTC. A write of '1' to Bit 1 of this register Stores the RTC to memory (address specified in TA_RTC_ADDR register)" hexmask.long 0xC 0.--31. 1. "Reserved_2,Reserved_2" line.long 0x10 "RGX_CR_TA_CONTEXT_STATE_BASE_0,The base address in external memory of the TA's context state buffer. to which the PPP will store the state on a context store and from which the VDM will reload on a context resume" hexmask.long 0x10 4.--31. 1. "ADDR,1TB range 128-bit aligned base address" newline hexmask.long.byte 0x10 0.--3. 1. "Reserved_0,Reserved_0" line.long 0x14 "RGX_CR_TA_CONTEXT_STATE_BASE_1,The base address in external memory of the TA's context state buffer. to which the PPP will store the state on a context store and from which the VDM will reload on a context resume" hexmask.long.tbyte 0x14 8.--31. 1. "Reserved_40,Reserved_40" newline hexmask.long.byte 0x14 0.--7. 1. "ADDR,1TB range 128-bit aligned base address" rgroup.long 0xCC8++0x7 line.long 0x0 "RGX_CR_PPP_DIAG_CULL_0,Diagnois register keeps a count of the number of primtives entering the PPP culling module" hexmask.long.byte 0x0 26.--31. 1. "OP_COUNT,count of primitives exiting the cull block" newline hexmask.long 0x0 0.--25. 1. "IP_COUNT,count of primitives entering the cull block" line.long 0x4 "RGX_CR_PPP_DIAG_CULL_1,Diagnois register keeps a count of the number of primtives entering the PPP culling module" hexmask.long.word 0x4 20.--31. 1. "Reserved_52,Reserved_52" newline hexmask.long.tbyte 0x4 0.--19. 1. "OP_COUNT,count of primitives exiting the cull block" repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) rgroup.long ($2+0xCD0)++0x3 line.long 0x0 "RGX_CR_PPP_$1,Checksum generated from the output of the PPP" hexmask.long 0x0 0.--31. 1. "CHECKSUM,checksum generated from the output of the PPP" repeat.end group.long 0xCD8++0x1F line.long 0x0 "RGX_CR_UVS_CLEAR_0,A write of '1' to this register starts the UVS Clear Operation This register must be written during the core initialisation sequence." hexmask.long 0x0 1.--31. 1. "Reserved_1,Reserved_1" newline bitfld.long 0x0 0. "PENDING,Start UVS Clear Operation a write to this register results in a one cycle pulse" "0,1" line.long 0x4 "RGX_CR_UVS_CLEAR_1,A write of '1' to this register starts the UVS Clear Operation This register must be written during the core initialisation sequence." hexmask.long 0x4 0.--31. 1. "Reserved_1,Reserved_1" line.long 0x8 "RGX_CR_TA_RTC_PRELOAD_0,When set. the RTC will be Preloaded with Zeros (or a nonRTA render target of 1) on a Clear Operation (used when Render Targets are not in use to remove the need for memory allocation)" hexmask.long 0x8 2.--31. 1. "Reserved_2,Reserved_2" newline bitfld.long 0x8 1. "ONE,Preload RTC with Render Target 0 set on a Clear. Used when resuming a TA phase after coarse grain context switch" "0,1" newline bitfld.long 0x8 0. "ZEROS,Preload RTC with Zeros on a Clear" "0,1" line.long 0xC "RGX_CR_TA_RTC_PRELOAD_1,When set. the RTC will be Preloaded with Zeros (or a nonRTA render target of 1) on a Clear Operation (used when Render Targets are not in use to remove the need for memory allocation)" hexmask.long 0xC 0.--31. 1. "Reserved_2,Reserved_2" line.long 0x10 "RGX_CR_TE_STATE_0,This register should be Sampled by the Driver on Context Switch and Restored before the Resume of the TA Context" hexmask.long 0x10 6.--31. 1. "Reserved_6,Reserved_6" newline hexmask.long.byte 0x10 1.--5. 1. "ISP_STATE_ID,ISP State ID" newline bitfld.long 0x10 0. "ABORTED,TA had been aborted in the past" "0,1" line.long 0x14 "RGX_CR_TE_STATE_1,This register should be Sampled by the Driver on Context Switch and Restored before the Resume of the TA Context" hexmask.long 0x14 0.--31. 1. "Reserved_6,Reserved_6" line.long 0x18 "RGX_CR_VCE_HALT_0,The MicroKernel must halt VCE processing (consumption of it's pages allocated by PM) before we can do a Partial Render in the Rogue Architecture. When it writes this register. the VCE will detect this on a notify pulse and assert the.." hexmask.long 0x18 1.--31. 1. "Reserved_1,Reserved_1" newline bitfld.long 0x18 0. "PENDING,VCE is Halting after Current Block" "0,1" line.long 0x1C "RGX_CR_VCE_HALT_1,The MicroKernel must halt VCE processing (consumption of it's pages allocated by PM) before we can do a Partial Render in the Rogue Architecture. When it writes this register. the VCE will detect this on a notify pulse and assert the.." hexmask.long 0x1C 0.--31. 1. "Reserved_1,Reserved_1" wgroup.long 0xCF8++0x7 line.long 0x0 "RGX_CR_TE_RESUME_AFTER_ABORT_0,A write of '1' to this register tells the TE we are resuming after an Abort but that no Partial Render took place" hexmask.long 0x0 1.--31. 1. "Reserved_1,Reserved_1" newline bitfld.long 0x0 0. "PULSE,TE is restarted and reattempts failing allocation after Out Of Memory event only" "0,1" line.long 0x4 "RGX_CR_TE_RESUME_AFTER_ABORT_1,A write of '1' to this register tells the TE we are resuming after an Abort but that no Partial Render took place" hexmask.long 0x4 0.--31. 1. "Reserved_1,Reserved_1" rgroup.long 0xD00++0x7 line.long 0x0 "RGX_CR_TA_IDLE_0,RGX_CR_TA_IDLE_0" hexmask.long 0x0 6.--31. 1. "Reserved_6,Reserved_6" newline bitfld.long 0x0 5. "TE,TE Module IDLE" "0,1" newline bitfld.long 0x0 4. "VCE,VCE Module IDLE" "0,1" newline bitfld.long 0x0 3. "VBG,VBG Module IDLE" "0,1" newline bitfld.long 0x0 2. "CLIP,CLIP Module IDLE" "0,1" newline bitfld.long 0x0 1. "PPP,PPP Module IDLE" "0,1" newline bitfld.long 0x0 0. "UVS,UVS Module IDLE" "0,1" line.long 0x4 "RGX_CR_TA_IDLE_1,RGX_CR_TA_IDLE_1" hexmask.long 0x4 0.--31. 1. "Reserved_6,Reserved_6" repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) rgroup.long ($2+0xD08)++0x3 line.long 0x0 "RGX_CR_STAT_NEW_PRIM_$1,RGX_CR_STAT_NEW_PRIM_0" hexmask.long 0x0 0.--31. 1. "PPP,Number of primitives into PPP" repeat.end repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) rgroup.long ($2+0xD10)++0x3 line.long 0x0 "RGX_CR_STAT_NEW_$1,RGX_CR_STAT_NEW_0" hexmask.long 0x0 0.--31. 1. "VERTEX,Number of vertices" repeat.end group.long 0xD18++0x27 line.long 0x0 "RGX_CR_FBC_MEM_POINTER_0,Framebuffer last memory address written in indirect mode" hexmask.long 0x0 0.--31. 1. "BASE_ADDRESS_REQ,Set to base address of compressed surface to find the last written address for that surface by reading the register when FBC_MEM_POINTER_READ_PENDING =0. BASE_ADDRESS=[33..0] DM=[36..34]" line.long 0x4 "RGX_CR_FBC_MEM_POINTER_1,Framebuffer last memory address written in indirect mode" hexmask.long 0x4 6.--31. 1. "Reserved_38,Reserved_38" newline bitfld.long 0x4 5. "READ_PENDING,Write 1 to perform a lookup for the last memory address written for that surface specified when this register is read as 0 then contents of FBC_MEM_POINTER_BASE_ADDRESS_REQ register contains the last memory address written for the.." "0,1" newline hexmask.long.byte 0x4 0.--4. 1. "BASE_ADDRESS_REQ,Set to base address of compressed surface to find the last written address for that surface by reading the register when FBC_MEM_POINTER_READ_PENDING =0. BASE_ADDRESS=[33..0] DM=[36..34]" line.long 0x8 "RGX_CR_TE_PSG_RTC_0,This register should be Sampled by the Driver on VDM Context Switch Terminate TA FINISHED event and Restored before the Resume of the TA Context" hexmask.long.tbyte 0x8 12.--31. 1. "Reserved_12,Reserved_12" newline hexmask.long.word 0x8 0.--11. 1. "ACTIVE_RTS,RTAs active at the point of the VDM Context SWitch" line.long 0xC "RGX_CR_TE_PSG_RTC_1,This register should be Sampled by the Driver on VDM Context Switch Terminate TA FINISHED event and Restored before the Resume of the TA Context" hexmask.long 0xC 0.--31. 1. "Reserved_12,Reserved_12" line.long 0x10 "RGX_CR_VCE_CACHE_FLUSH_0,The MicroKernel can use this to flush the VCE write only cache at the end of TA phase render. When it writes this register. the VCE will detect this on a notify pulse and assert the return signal until it has completed processing.." hexmask.long 0x10 1.--31. 1. "Reserved_1,Reserved_1" newline bitfld.long 0x10 0. "PENDING,VCE is Flushing its write only cache to memory" "0,1" line.long 0x14 "RGX_CR_VCE_CACHE_FLUSH_1,The MicroKernel can use this to flush the VCE write only cache at the end of TA phase render. When it writes this register. the VCE will detect this on a notify pulse and assert the return signal until it has completed processing.." hexmask.long 0x14 0.--31. 1. "Reserved_1,Reserved_1" line.long 0x18 "RGX_CR_TE_CACHE_FLUSH_0,The MicroKernel can use this to flush the TE write only cache at the end of TA phase render. When it writes this register. the TE will detect this on a notify pulse and assert the return signal until it has completed processing.." hexmask.long 0x18 1.--31. 1. "Reserved_1,Reserved_1" newline bitfld.long 0x18 0. "PENDING,TE is Flushing its write only cache to memory" "0,1" line.long 0x1C "RGX_CR_TE_CACHE_FLUSH_1,The MicroKernel can use this to flush the TE write only cache at the end of TA phase render. When it writes this register. the TE will detect this on a notify pulse and assert the return signal until it has completed processing.." hexmask.long 0x1C 0.--31. 1. "Reserved_1,Reserved_1" line.long 0x20 "RGX_CR_PM_CACHE_FLUSH_0,The MicroKernel can use this to flush the PM write only cache at the end of TA phase render. When it writes this register. the PM will detect this on a notify pulse and assert the return signal until it has completed processing.." hexmask.long 0x20 1.--31. 1. "Reserved_1,Reserved_1" newline bitfld.long 0x20 0. "PENDING,PM is Flushing its write only cache to memory" "0,1" line.long 0x24 "RGX_CR_PM_CACHE_FLUSH_1,The MicroKernel can use this to flush the PM write only cache at the end of TA phase render. When it writes this register. the PM will detect this on a notify pulse and assert the return signal until it has completed processing.." hexmask.long 0x24 0.--31. 1. "Reserved_1,Reserved_1" wgroup.long 0xF00++0x7 line.long 0x0 "RGX_CR_ISP_START_RENDER_0,Writing '1' to this register initiates a 3D render" hexmask.long 0x0 1.--31. 1. "Reserved_1,Reserved_1" newline bitfld.long 0x0 0. "PULSE,PULSE" "0,1" line.long 0x4 "RGX_CR_ISP_START_RENDER_1,Writing '1' to this register initiates a 3D render" hexmask.long 0x4 0.--31. 1. "Reserved_1,Reserved_1" group.long 0xF08++0x77 line.long 0x0 "RGX_CR_ISP_RENDER_0,Controls the render" hexmask.long 0x0 5.--31. 1. "Reserved_5,Reserved_5" newline bitfld.long 0x0 4. "RESUME,Render resume" "0,1" newline bitfld.long 0x0 2.--3. "DIR,Render direction" "0,1,2,3" newline bitfld.long 0x0 0.--1. "MODE,Render type" "0,1,2,3" line.long 0x4 "RGX_CR_ISP_RENDER_1,Controls the render" hexmask.long 0x4 0.--31. 1. "Reserved_5,Reserved_5" line.long 0x8 "RGX_CR_ISP_RENDER_ORIGIN_0,This register defines the top-left tile coordinate for the render." hexmask.long.byte 0x8 26.--31. 1. "Reserved_26,Reserved_26" newline hexmask.long.word 0x8 16.--25. 1. "X,X coordinate in tiles" newline hexmask.long.byte 0x8 10.--15. 1. "Reserved_10,Reserved_10" newline hexmask.long.word 0x8 0.--9. 1. "Y,Y coordinate in tiles" line.long 0xC "RGX_CR_ISP_RENDER_ORIGIN_1,This register defines the top-left tile coordinate for the render." hexmask.long 0xC 0.--31. 1. "Reserved_26,Reserved_26" line.long 0x10 "RGX_CR_ISP_MTILE_SIZE_0,RGX_CR_ISP_MTILE_SIZE_0" hexmask.long.byte 0x10 26.--31. 1. "Reserved_26,Reserved_26" newline hexmask.long.word 0x10 16.--25. 1. "X,Macrotile width in tiles. A value of zero corresponds to the maximum size" newline hexmask.long.byte 0x10 10.--15. 1. "Reserved_10,Reserved_10" newline hexmask.long.word 0x10 0.--9. 1. "Y,Macrotile height in tiles. A value of zero corresponds to the maximum size" line.long 0x14 "RGX_CR_ISP_MTILE_SIZE_1,RGX_CR_ISP_MTILE_SIZE_1" hexmask.long 0x14 0.--31. 1. "Reserved_26,Reserved_26" line.long 0x18 "RGX_CR_ISP_MTILE_BASE_0,RGX_CR_ISP_MTILE_BASE_0" hexmask.long 0x18 2.--31. 1. "ADDR,1TB range 32-bit aligned base address" newline bitfld.long 0x18 0.--1. "Reserved_0,Reserved_0" "0,1,2,3" line.long 0x1C "RGX_CR_ISP_MTILE_BASE_1,RGX_CR_ISP_MTILE_BASE_1" hexmask.long.tbyte 0x1C 8.--31. 1. "Reserved_40,Reserved_40" newline hexmask.long.byte 0x1C 0.--7. 1. "ADDR,1TB range 32-bit aligned base address" line.long 0x20 "RGX_CR_ISP_RGN_0,This register defines the sizes of the allocations of the simple internal parameter data." bitfld.long 0x20 29.--31. "Reserved_29,Reserved_29" "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x20 24.--28. 1. "CS_SIZE,Number of primitive headers in the control stream for a fast 2D render. If the number of primitive headers exceeds the maximum field size or the size of the control stream is unknown a value of all ones should be written" newline hexmask.long.tbyte 0x20 0.--23. 1. "SIZE,Number of Region Headers to fetch" line.long 0x24 "RGX_CR_ISP_RGN_1,This register defines the sizes of the allocations of the simple internal parameter data." hexmask.long 0x24 0.--31. 1. "Reserved_29,Reserved_29" line.long 0x28 "RGX_CR_ISP_AA_0,Controls whether anti-aliasing is enabled or disabled" hexmask.long 0x28 2.--31. 1. "Reserved_2,Reserved_2" newline bitfld.long 0x28 0.--1. "MODE,MODE" "0,1,2,3" line.long 0x2C "RGX_CR_ISP_AA_1,Controls whether anti-aliasing is enabled or disabled" hexmask.long 0x2C 0.--31. 1. "Reserved_2,Reserved_2" line.long 0x30 "RGX_CR_ISP_CTL_0,ISP control register. This register contains the PIPE_NUM field which controls the number of tiles in flight within the IPP and IPF. The values to which this register should be set are dependent on not only the number of tiles in flight.." bitfld.long 0x30 31. "Reserved_31,Reserved_31" "0,1" newline bitfld.long 0x30 30. "LINE_STYLE,Used to enable rendering widelines as rectangles. '0': render as parallelograms '1': render as retangles" "0,1" newline bitfld.long 0x30 29. "LINE_STYLE_PIX,Used to enable rendering single pixel widelines as rectangles. '0': render as parallelograms '1': render as retangles" "0,1" newline bitfld.long 0x30 28. "PAIR_TILES_VERT,If set causes IPF to pair tiles vertically within its pipeline." "0,1" newline bitfld.long 0x30 27. "PAIR_TILES,If set causes IPF to pair tiles within its pipeline." "0,1" newline hexmask.long.byte 0x30 21.--26. 1. "Reserved_21,Reserved_21" newline bitfld.long 0x30 20. "DBIAS_IS_INT,When set depth bias value is a signed integer" "0,1" newline bitfld.long 0x30 19. "OVERLAP_CHECK_MODE,0 - different samples for the same pixel will be sent to different pass groups for translucent objects (pixel to pixel overlap test) 1 - different samples for the same pixel will be sent as the same pass group (sample to sample overlap.." "different samples for the same pixel will be..,different samples for the same pixel will be.." newline bitfld.long 0x30 18. "PT_UPFRONT_DEPTH_DISABLE,When set disable UPFRONT depth test in the Depthsorter" "0,1" newline bitfld.long 0x30 17. "PROCESS_EMPTY_TILES,When set empty tiles are always processed rather than being suppressed" "0,1" newline bitfld.long 0x30 16. "SAMPLE_POS,Specifies the sampling rule to be used when calculating the endpoint adjustment for thin lines" "0,1" newline hexmask.long.byte 0x30 12.--15. 1. "PIPE_ENABLE,Tiles-in-flight" newline bitfld.long 0x30 10.--11. "Reserved_10,Reserved_10" "0,1,2,3" newline hexmask.long.byte 0x30 4.--9. 1. "VALID_ID,Triangle validation value" newline hexmask.long.byte 0x30 0.--3. 1. "UPASS_START,User pass start value" line.long 0x34 "RGX_CR_ISP_CTL_1,ISP control register. This register contains the PIPE_NUM field which controls the number of tiles in flight within the IPP and IPF. The values to which this register should be set are dependent on not only the number of tiles in flight.." hexmask.long 0x34 0.--31. 1. "Reserved_31,Reserved_31" line.long 0x38 "RGX_CR_ISP_SPLIT_RENDER_0,RGX_CR_ISP_SPLIT_RENDER_0" bitfld.long 0x38 30.--31. "Reserved_30,Reserved_30" "0,1,2,3" newline hexmask.long.word 0x38 16.--29. 1. "MAX,Render up to and including this value" newline bitfld.long 0x38 14.--15. "Reserved_14,Reserved_14" "0,1,2,3" newline hexmask.long.word 0x38 0.--13. 1. "MIN,Render up from and including this value" line.long 0x3C "RGX_CR_ISP_SPLIT_RENDER_1,RGX_CR_ISP_SPLIT_RENDER_1" hexmask.long 0x3C 1.--31. 1. "Reserved_33,Reserved_33" newline bitfld.long 0x3C 0. "ENABLE,ENABLE" "0,1" line.long 0x40 "RGX_CR_ISP_ZLSCTL_0,ISP Z Load/Store & format global control register" hexmask.long.byte 0x40 27.--31. 1. "ZLSEXTENT_Y_Z,For Depth buffer Display width of Y in tiles minus one: 0x000 1 tile 0x001 2 tiles .. 0x2FF 1024 tiles zlsextent_y = total_samples_y / 32 samples in non-msaa 4xmsaa mode = total_samples_y / 64 samples in 2xmsaa 8xmsaa mode. In.." newline bitfld.long 0x40 25.--26. "ZSTOREFORMAT,ZSTOREFORMAT" "0,1,2,3" newline bitfld.long 0x40 23.--24. "ZLOADFORMAT,ZLOADFORMAT" "0,1,2,3" newline bitfld.long 0x40 22. "FB_STOREEN,when set frame buffer compression store is enabled" "0,1" newline bitfld.long 0x40 21. "FB_LOADEN,when set frame buffer decompression load is enabled" "0,1" newline bitfld.long 0x40 20. "MSTOREEN,When set and ZSTOREFORMAT = 0x0 mask plane is stored within msb of IEEE format when set and ZSTOREFORMAT = 0x3 mask plane is stored at bit position 31 of IEEE format when set for other format if mask_store_base_enable = '1' background.." "0,1" newline bitfld.long 0x40 19. "ZSTOREEN,When set to 1 if the ZSTORE bit in the region header is also set then the depth buffer is stored to memory after each tile is processed" "0,1" newline bitfld.long 0x40 18. "SSTOREEN,When set to 1 if the ZSTORE bit in the region header is also set then the stencil buffer is stored to memory after each tile is processed" "0,1" newline bitfld.long 0x40 17. "STORETWIDDLED,When set to 1 depth and stencil data is written out in 'Twiddled' order." "0,1" newline bitfld.long 0x40 16. "MLOADEN,When set and ZLOADFORMAT = 0x0 mask plane is loaded from msb of IEEE format when set and ZLOADFORMAT = 0x3 mask plane is loaded from the bit position 31 of IEEE format when set for other format if mask_load_base_enable = '1' mask plane is.." "0,1" newline bitfld.long 0x40 15. "ZLOADEN,When set to 1 if the ZLOAD bit in the region header is also set then the depth buffer is read from memory prior to tile processing" "0,1" newline bitfld.long 0x40 14. "SLOADEN,When set to 1 if the ZLOAD bit in the region header is also set then the stencil buffer is read from memory prior to tile processing" "0,1" newline bitfld.long 0x40 13. "LOADTWIDDLED,When set to 1 depth stencil data is loaded in 'Twiddled' order" "0,1" newline hexmask.long.word 0x40 3.--12. 1. "ZLSEXTENT_X_Z,For depth buffer Display width of X in tiles minus one: 0x000 1 tile 0x001 2 tiles .. 0x2FF 1024 tiles. For different msaa mode 1xmsaa = 1 x (32 32) pixels = 32x1 x 32x1 = 1024 samples = 32 x 32 samples 2xmsaa = 2 x (32 32) pixels =.." newline bitfld.long 0x40 2. "FORCEZSTORE,If set to 1 the depth/stencil buffer is always stored at the end of each tile irrespective of the region header ZSTORE bit." "0,1" newline bitfld.long 0x40 1. "FORCEZLOAD,If set to 1 the depth/stencil buffer is always loaded at the start of each tile irrespective of the region header ZLOAD bit." "0,1" newline bitfld.long 0x40 0. "ZONLYRENDER,When set only the Z buffer is rendered. Opaque and translucent objects are stencil and depth tested as usual but no pixel spans are emitted to the PDS Pixel presenter. Pixels within punch through and depth feedback objects are emitted on.." "0,1" line.long 0x44 "RGX_CR_ISP_ZLSCTL_1,ISP Z Load/Store & format global control register" hexmask.long.byte 0x44 26.--31. 1. "Reserved_58,Reserved_58" newline hexmask.long.word 0x44 16.--25. 1. "ZLSEXTENT_Y_S,For stencil buffer the value calculation is the same as ZLSEXTENT_Y_Z" newline hexmask.long.word 0x44 6.--15. 1. "ZLSEXTENT_X_S,For stencil buffer the value calculation is the same as ZLSEXTENT_X_Z" newline bitfld.long 0x44 5. "STENCIL_EXTENT_ENABLE,When this bit is '1' stencil buffer will use zlsextent_x/y_s value to calculate zload/store address otherwise zlsextent_x/y_z value will be used. The default value is '0' which disables this new function." "0,1" newline hexmask.long.byte 0x44 0.--4. 1. "ZLSEXTENT_Y_Z,For Depth buffer Display width of Y in tiles minus one: 0x000 1 tile 0x001 2 tiles .. 0x2FF 1024 tiles zlsextent_y = total_samples_y / 32 samples in non-msaa 4xmsaa mode = total_samples_y / 64 samples in 2xmsaa 8xmsaa mode. In.." line.long 0x48 "RGX_CR_ISP_ZLOAD_BASE_0,Base address in memory of the Z Buffer base address to load into the ISP for non-compressed ZLS formats." hexmask.long 0x48 4.--31. 1. "ADDR,1TB Addressable 16byte aligned Base Address of the Z Buffer Load base address" newline hexmask.long.byte 0x48 0.--3. 1. "Reserved_0,Reserved_0" line.long 0x4C "RGX_CR_ISP_ZLOAD_BASE_1,Base address in memory of the Z Buffer base address to load into the ISP for non-compressed ZLS formats." hexmask.long.tbyte 0x4C 8.--31. 1. "Reserved_40,Reserved_40" newline hexmask.long.byte 0x4C 0.--7. 1. "ADDR,1TB Addressable 16byte aligned Base Address of the Z Buffer Load base address" line.long 0x50 "RGX_CR_ISP_ZSTORE_BASE_0,Base address in memory of the Z Buffer base address to store into the ISP for non-compressed ZLS formats." hexmask.long 0x50 4.--31. 1. "ADDR,1TB Addressable 16byte aligned Base Address of the Z Buffer Store base address" newline hexmask.long.byte 0x50 0.--3. 1. "Reserved_0,Reserved_0" line.long 0x54 "RGX_CR_ISP_ZSTORE_BASE_1,Base address in memory of the Z Buffer base address to store into the ISP for non-compressed ZLS formats." hexmask.long.tbyte 0x54 8.--31. 1. "Reserved_40,Reserved_40" newline hexmask.long.byte 0x54 0.--7. 1. "ADDR,1TB Addressable 16byte aligned Base Address of the Z Buffer Store base address" line.long 0x58 "RGX_CR_ISP_STENCIL_LOAD_BASE_0,Base address in memory of the Stencil Buffer base address to load into the ISP for non-compressed ZLS formats. This alternate stencil buffer base address is selectable based on the enable bit." hexmask.long 0x58 4.--31. 1. "ADDR,1TB Addressable 16byte aligned Base Address of the Z Buffer Load base address" newline bitfld.long 0x58 1.--3. "Reserved_1,Reserved_1" "0,1,2,3,4,5,6,7" newline bitfld.long 0x58 0. "ENABLE,When set to 1 enables fetching of stencil from a separate base address" "0,1" line.long 0x5C "RGX_CR_ISP_STENCIL_LOAD_BASE_1,Base address in memory of the Stencil Buffer base address to load into the ISP for non-compressed ZLS formats. This alternate stencil buffer base address is selectable based on the enable bit." hexmask.long.tbyte 0x5C 8.--31. 1. "Reserved_40,Reserved_40" newline hexmask.long.byte 0x5C 0.--7. 1. "ADDR,1TB Addressable 16byte aligned Base Address of the Z Buffer Load base address" line.long 0x60 "RGX_CR_ISP_STENCIL_STORE_BASE_0,Base address in memory of the Stencil Buffer base address to store into the ISP for non-compressed ZLS formats. This alternate stencil buffer base address is selectable based on the enable bit." hexmask.long 0x60 4.--31. 1. "ADDR,1TB Addressable 16byte aligned Base Address of the Z Buffer Load base address" newline bitfld.long 0x60 1.--3. "Reserved_1,Reserved_1" "0,1,2,3,4,5,6,7" newline bitfld.long 0x60 0. "ENABLE,When set to 1 enables fetching of stencil from a separate base address" "0,1" line.long 0x64 "RGX_CR_ISP_STENCIL_STORE_BASE_1,Base address in memory of the Stencil Buffer base address to store into the ISP for non-compressed ZLS formats. This alternate stencil buffer base address is selectable based on the enable bit." hexmask.long.tbyte 0x64 8.--31. 1. "Reserved_40,Reserved_40" newline hexmask.long.byte 0x64 0.--7. 1. "ADDR,1TB Addressable 16byte aligned Base Address of the Z Buffer Load base address" line.long 0x68 "RGX_CR_ISP_MASK_LOAD_BASE_0,Base address in memory of the Mask Buffer base address to load into the ISP for non-compressed ZLS formats. This alternate mask buffer base address is selectable based on the enable bit." hexmask.long 0x68 4.--31. 1. "ADDR,1TB Addressable 16byte aligned Base Address of the Z Buffer Load base address" newline bitfld.long 0x68 1.--3. "Reserved_1,Reserved_1" "0,1,2,3,4,5,6,7" newline bitfld.long 0x68 0. "ENABLE,When set to 1 enables fetching of mask from a separate base address" "0,1" line.long 0x6C "RGX_CR_ISP_MASK_LOAD_BASE_1,Base address in memory of the Mask Buffer base address to load into the ISP for non-compressed ZLS formats. This alternate mask buffer base address is selectable based on the enable bit." hexmask.long.tbyte 0x6C 8.--31. 1. "Reserved_40,Reserved_40" newline hexmask.long.byte 0x6C 0.--7. 1. "ADDR,1TB Addressable 16byte aligned Base Address of the Z Buffer Load base address" line.long 0x70 "RGX_CR_ISP_MASK_STORE_BASE_0,Base address in memory of the Mask Buffer base address to store into the ISP for non-compressed ZLS formats. This alternate mask buffer base address is selectable based on the enable bit." hexmask.long 0x70 4.--31. 1. "ADDR,1TB Addressable 16byte aligned Base Address of the Z Buffer Load base address" newline bitfld.long 0x70 1.--3. "Reserved_1,Reserved_1" "0,1,2,3,4,5,6,7" newline bitfld.long 0x70 0. "ENABLE,When set to 1 enables fetching of mask from a separate base address" "0,1" line.long 0x74 "RGX_CR_ISP_MASK_STORE_BASE_1,Base address in memory of the Mask Buffer base address to store into the ISP for non-compressed ZLS formats. This alternate mask buffer base address is selectable based on the enable bit." hexmask.long.tbyte 0x74 8.--31. 1. "Reserved_40,Reserved_40" newline hexmask.long.byte 0x74 0.--7. 1. "ADDR,1TB Addressable 16byte aligned Base Address of the Z Buffer Load base address" repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) group.long ($2+0xF80)++0x3 line.long 0x0 "RGX_CR_ISP_BGOBJDEPTH_$1,The ISP operates by comparing depth values of incoming objects with the results of previous depth compares. in order to make sure there are no unitialised values at the start of the tile or to cover pixels where there are no.." hexmask.long 0x0 0.--31. 1. "VALUE,Note the format in this register has to be consistent with the format defined by ZLS_STORE_FORMAT register. If depth buffer is F32 then the value here should be IEEE 754 single precisoin floating point If depth buffer is /INT16 then the value.." repeat.end group.long 0xF88++0x7 line.long 0x0 "RGX_CR_ISP_BGOBJVALS_0,This register provides enable. mask and stencil information for the hardware background object." hexmask.long.tbyte 0x0 10.--31. 1. "Reserved_10,Reserved_10" newline bitfld.long 0x0 9. "ENABLEBGTAG,When set to 1 at the start of each tile the ISP tag buffer is initialised with the background object tag (default = 1)" "0,1" newline bitfld.long 0x0 8. "MASK,Hardware background object mask plane" "0,1" newline hexmask.long.byte 0x0 0.--7. 1. "STENCIL,Hardware background object stencil" line.long 0x4 "RGX_CR_ISP_BGOBJVALS_1,This register provides enable. mask and stencil information for the hardware background object." hexmask.long 0x4 0.--31. 1. "Reserved_10,Reserved_10" group.long 0xFA0++0x7 line.long 0x0 "RGX_CR_ISP_GRIDOFFSET_0,Sample position grid offset for use when MSAA/ODAA is DISABLED DX (0.0.0.0) OpenGL (0.5.0.5) Acts as the 9th multisample position when MSAA is ENABLED." hexmask.long.tbyte 0x0 8.--31. 1. "Reserved_8,Reserved_8" newline hexmask.long.byte 0x0 4.--7. 1. "GRID_Y,Unsigned sub-pixel offset" newline hexmask.long.byte 0x0 0.--3. 1. "GRID_X,Unsigned sub-pixel offset" line.long 0x4 "RGX_CR_ISP_GRIDOFFSET_1,Sample position grid offset for use when MSAA/ODAA is DISABLED DX (0.0.0.0) OpenGL (0.5.0.5) Acts as the 9th multisample position when MSAA is ENABLED." hexmask.long 0x4 0.--31. 1. "Reserved_8,Reserved_8" repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) group.long ($2+0xFA8)++0x3 line.long 0x0 "RGX_CR_ISP_MULTISAMPLECTL_$1,Sample position grid offset for use in 2x. 4x. 8xMSAA and ODAA modes." hexmask.long.byte 0x0 28.--31. 1. "MSAA_Y3,Unsigned sub-pixel offset for the 4th multisample Y position" newline hexmask.long.byte 0x0 24.--27. 1. "MSAA_X3,Unsigned sub-pixel offset for the 4th multisample X position" newline hexmask.long.byte 0x0 20.--23. 1. "MSAA_Y2,Unsigned sub-pixel offset for the 3rd multisample Y position" newline hexmask.long.byte 0x0 16.--19. 1. "MSAA_X2,Unsigned sub-pixel offset for the 3rd multisample X position" newline hexmask.long.byte 0x0 12.--15. 1. "MSAA_Y1,Unsigned sub-pixel offset for the 2nd multisample Y position" newline hexmask.long.byte 0x0 8.--11. 1. "MSAA_X1,Unsigned sub-pixel offset for the 2nd multisample X position" newline hexmask.long.byte 0x0 4.--7. 1. "MSAA_Y0,Unsigned sub-pixel offset for the 1st multisample Y position" newline hexmask.long.byte 0x0 0.--3. 1. "MSAA_X0,Unsigned sub-pixel offset for the 1st multisample X position" repeat.end group.long 0xFB0++0x2F line.long 0x0 "RGX_CR_ISP_SCISSOR_BASE_0,RGX_CR_ISP_SCISSOR_BASE_0" hexmask.long 0x0 2.--31. 1. "ADDR,1TB range 32-bit aligned base address" newline bitfld.long 0x0 0.--1. "Reserved_0,Reserved_0" "0,1,2,3" line.long 0x4 "RGX_CR_ISP_SCISSOR_BASE_1,RGX_CR_ISP_SCISSOR_BASE_1" hexmask.long.tbyte 0x4 8.--31. 1. "Reserved_40,Reserved_40" newline hexmask.long.byte 0x4 0.--7. 1. "ADDR,1TB range 32-bit aligned base address" line.long 0x8 "RGX_CR_ISP_DBIAS_BASE_0,RGX_CR_ISP_DBIAS_BASE_0" hexmask.long 0x8 2.--31. 1. "ADDR,1TB range 32-bit aligned base address" newline bitfld.long 0x8 0.--1. "Reserved_0,Reserved_0" "0,1,2,3" line.long 0xC "RGX_CR_ISP_DBIAS_BASE_1,RGX_CR_ISP_DBIAS_BASE_1" hexmask.long.tbyte 0xC 8.--31. 1. "Reserved_40,Reserved_40" newline hexmask.long.byte 0xC 0.--7. 1. "ADDR,1TB range 32-bit aligned base address" line.long 0x10 "RGX_CR_ISP_OCLQRY_BASE_0,Base address for occlusion query counter values. For multiple phantom system. base address could be set differently and driver needs to sum up the result from different phantoms which have same occlusion query index." hexmask.long 0x10 4.--31. 1. "ADDR,1TB range 128-bit aligned base address" newline hexmask.long.byte 0x10 0.--3. 1. "Reserved_0,Reserved_0" line.long 0x14 "RGX_CR_ISP_OCLQRY_BASE_1,Base address for occlusion query counter values. For multiple phantom system. base address could be set differently and driver needs to sum up the result from different phantoms which have same occlusion query index." hexmask.long.tbyte 0x14 8.--31. 1. "Reserved_40,Reserved_40" newline hexmask.long.byte 0x14 0.--7. 1. "ADDR,1TB range 128-bit aligned base address" line.long 0x18 "RGX_CR_ISP_PIXEL_BASE_0,Base address for control stream and primitive blocks." hexmask.long 0x18 0.--31. 1. "Reserved_0,Reserved_0" line.long 0x1C "RGX_CR_ISP_PIXEL_BASE_1,Base address for control stream and primitive blocks." hexmask.long.tbyte 0x1C 8.--31. 1. "Reserved_40,Reserved_40" newline hexmask.long.byte 0x1C 2.--7. 1. "ADDR,1TB range 16GB granularity" newline bitfld.long 0x1C 0.--1. "Reserved_0,Reserved_0" "0,1,2,3" line.long 0x20 "RGX_CR_ISP_ZLS_PIXELS_0,screen size in pixel numbers for ZLS." bitfld.long 0x20 30.--31. "Reserved_30,Reserved_30" "0,1,2,3" newline hexmask.long.word 0x20 15.--29. 1. "Y,Display width of Y in pixels minus one. 0x000 1 pixel 0x001 2 pixels ... 0x7FFF 1024*32 pixels. Subtile only supports for non-msaa mode depth load/store so For non-msaa mode if framebuffer compression or separate mask or separate stencil is.." newline hexmask.long.word 0x20 0.--14. 1. "X,Display width of X in pixels minus one. 0x000 1 pixel 0x001 2 pixels ... 0x7FFF 1024*32 pixels. Subtile only supports for non-msaa mode depth load/store so For non-msaa mode if framebuffer compression or separate mask or separate stencil is.." line.long 0x24 "RGX_CR_ISP_ZLS_PIXELS_1,screen size in pixel numbers for ZLS." hexmask.long 0x24 0.--31. 1. "Reserved_30,Reserved_30" line.long 0x28 "RGX_CR_ISP_CTL2_0,RGX_CR_ISP_CTL2_0" hexmask.long 0x28 5.--31. 1. "Reserved_5,Reserved_5" newline hexmask.long.byte 0x28 0.--4. 1. "DEPTHBUFFERS_IN_USE,Specifies the number of depth buffers to use" line.long 0x2C "RGX_CR_ISP_CTL2_1,RGX_CR_ISP_CTL2_1" hexmask.long 0x2C 0.--31. 1. "Reserved_5,Reserved_5" wgroup.long 0x1000++0x7 line.long 0x0 "RGX_CR_ISP_START_CONTEXT_STORE_0,Writing '1' to this register initiates a 3D context store" hexmask.long 0x0 1.--31. 1. "Reserved_1,Reserved_1" newline bitfld.long 0x0 0. "PULSE,PULSE" "0,1" line.long 0x4 "RGX_CR_ISP_START_CONTEXT_STORE_1,Writing '1' to this register initiates a 3D context store" hexmask.long 0x4 0.--31. 1. "Reserved_1,Reserved_1" rgroup.long 0x1008++0x7 line.long 0x0 "RGX_CR_ISP_STORE0_0,ISP context store register" bitfld.long 0x0 31. "Reserved_31,Reserved_31" "0,1" newline bitfld.long 0x0 30. "ACTIVE,ACTIVE" "0,1" newline bitfld.long 0x0 29. "EOR,EOR" "0,1" newline bitfld.long 0x0 28. "TILE_LAST,TILE_LAST" "0,1" newline hexmask.long.byte 0x0 24.--27. 1. "MT,MT" newline bitfld.long 0x0 22.--23. "Reserved_22,Reserved_22" "0,1,2,3" newline hexmask.long.word 0x0 12.--21. 1. "TILE_X,TILE_X" newline bitfld.long 0x0 10.--11. "Reserved_10,Reserved_10" "0,1,2,3" newline hexmask.long.word 0x0 0.--9. 1. "TILE_Y,TILE_Y" line.long 0x4 "RGX_CR_ISP_STORE0_1,ISP context store register" hexmask.long 0x4 0.--31. 1. "Reserved_31,Reserved_31" group.long 0x1020++0x7 line.long 0x0 "RGX_CR_ISP_RESUME0_0,ISP context resume register" hexmask.long.word 0x0 22.--31. 1. "Reserved_22,Reserved_22" newline hexmask.long.word 0x0 12.--21. 1. "TILE_X,TILE_X" newline bitfld.long 0x0 10.--11. "Reserved_10,Reserved_10" "0,1,2,3" newline hexmask.long.word 0x0 0.--9. 1. "TILE_Y,TILE_Y" line.long 0x4 "RGX_CR_ISP_RESUME0_1,ISP context resume register" hexmask.long 0x4 0.--31. 1. "Reserved_22,Reserved_22" rgroup.long 0x1038++0xF line.long 0x0 "RGX_CR_ISP_STATUS_0,ISP status registers" hexmask.long 0x0 3.--31. 1. "Reserved_3,Reserved_3" newline bitfld.long 0x0 2. "SPLIT_MAX,Split Render Maximum Threshold has been Exceeded" "0,1" newline bitfld.long 0x0 1. "ACTIVE,ISP is Active first tile in the render has been assigned" "0,1" newline bitfld.long 0x0 0. "EOR,ISP has assigned the last tile in the render" "0,1" line.long 0x4 "RGX_CR_ISP_STATUS_1,ISP status registers" hexmask.long 0x4 0.--31. 1. "Reserved_3,Reserved_3" line.long 0x8 "RGX_CR_RAST_IDLE_0,RGX_CR_RAST_IDLE_0" hexmask.long 0x8 5.--31. 1. "Reserved_5,Reserved_5" newline bitfld.long 0x8 4. "TFPU,TFPU Module IDLE" "0,1" newline bitfld.long 0x8 3. "TPF,TPF Module IDLE" "0,1" newline bitfld.long 0x8 2. "IFPU,IFPU Module IDLE" "0,1" newline bitfld.long 0x8 1. "ISP,ISP Module IDLE" "0,1" newline bitfld.long 0x8 0. "IPF,IPF Module IDLE" "0,1" line.long 0xC "RGX_CR_RAST_IDLE_1,RGX_CR_RAST_IDLE_1" hexmask.long 0xC 0.--31. 1. "Reserved_5,Reserved_5" repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) rgroup.long ($2+0x1048)++0x3 line.long 0x0 "RGX_CR_ISP_PWR_NUM_$1,RGX_CR_ISP_PWR_NUM_0" hexmask.long 0x0 0.--31. 1. "PIXELS_PROCESS,Number of depth tested pixels(non-MSAA) or samples(MSAA) processed" repeat.end repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) rgroup.long ($2+0x1058)++0x3 line.long 0x0 "RGX_CR_TFPU_PWR_NUM_$1,RGX_CR_TFPU_PWR_NUM_0" hexmask.long 0x0 0.--31. 1. "PRIMITIVES_PROCESSED,Number of primitives processed" repeat.end repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) group.long ($2+0x11D0)++0x3 line.long 0x0 "RGX_CR_ISP_MERGE_LOWER_X_$1,Used by the IFPU to generate the angle vectors used for triangle merging" hexmask.long 0x0 0.--31. 1. "VALUE,tan(15)/16k screen size" repeat.end repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) group.long ($2+0x11D8)++0x3 line.long 0x0 "RGX_CR_ISP_MERGE_LOWER_Y_$1,Used by the IFPU to generate the angle vectors used for triangle merging" hexmask.long 0x0 0.--31. 1. "VALUE,tan(15)/16k screen size" repeat.end repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) group.long ($2+0x11E0)++0x3 line.long 0x0 "RGX_CR_ISP_MERGE_UPPER_X_$1,RGX_CR_ISP_MERGE_UPPER_X_0" hexmask.long 0x0 0.--31. 1. "VALUE,tan(60)/16k screen size" repeat.end repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) group.long ($2+0x11E8)++0x3 line.long 0x0 "RGX_CR_ISP_MERGE_UPPER_Y_$1,Used by the IFPU to generate the angle vectors used for triangle merging" hexmask.long 0x0 0.--31. 1. "VALUE,tan(60)/16k screen size" repeat.end repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) group.long ($2+0x11F0)++0x3 line.long 0x0 "RGX_CR_ISP_MERGE_SCALE_X_$1,RGX_CR_ISP_MERGE_SCALE_X_0" hexmask.long 0x0 0.--31. 1. "VALUE,16 * default screen size of 16k" repeat.end repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) group.long ($2+0x11F8)++0x3 line.long 0x0 "RGX_CR_ISP_MERGE_SCALE_Y_$1,Used by the IFPU to generate the angle vectors used for triangle merging" hexmask.long 0x0 0.--31. 1. "VALUE,16 * default screen size of 16k" repeat.end group.long 0x1200++0x57 line.long 0x0 "RGX_CR_BIF_CAT_BASE0_0,RGX_CR_BIF_CAT_BASE0_0" hexmask.long.tbyte 0x0 12.--31. 1. "ADDR,ADDR" newline hexmask.long.word 0x0 0.--11. 1. "Reserved_0,Reserved_0" line.long 0x4 "RGX_CR_BIF_CAT_BASE0_1,RGX_CR_BIF_CAT_BASE0_1" hexmask.long.tbyte 0x4 8.--31. 1. "Reserved_40,Reserved_40" newline hexmask.long.byte 0x4 0.--7. 1. "ADDR,ADDR" line.long 0x8 "RGX_CR_BIF_CAT_BASE1_0,RGX_CR_BIF_CAT_BASE1_0" hexmask.long.tbyte 0x8 12.--31. 1. "ADDR,ADDR" newline hexmask.long.word 0x8 0.--11. 1. "Reserved_0,Reserved_0" line.long 0xC "RGX_CR_BIF_CAT_BASE1_1,RGX_CR_BIF_CAT_BASE1_1" hexmask.long.tbyte 0xC 8.--31. 1. "Reserved_40,Reserved_40" newline hexmask.long.byte 0xC 0.--7. 1. "ADDR,ADDR" line.long 0x10 "RGX_CR_BIF_CAT_BASE2_0,RGX_CR_BIF_CAT_BASE2_0" hexmask.long.tbyte 0x10 12.--31. 1. "ADDR,ADDR" newline hexmask.long.word 0x10 0.--11. 1. "Reserved_0,Reserved_0" line.long 0x14 "RGX_CR_BIF_CAT_BASE2_1,RGX_CR_BIF_CAT_BASE2_1" hexmask.long.tbyte 0x14 8.--31. 1. "Reserved_40,Reserved_40" newline hexmask.long.byte 0x14 0.--7. 1. "ADDR,ADDR" line.long 0x18 "RGX_CR_BIF_CAT_BASE3_0,RGX_CR_BIF_CAT_BASE3_0" hexmask.long.tbyte 0x18 12.--31. 1. "ADDR,ADDR" newline hexmask.long.word 0x18 0.--11. 1. "Reserved_0,Reserved_0" line.long 0x1C "RGX_CR_BIF_CAT_BASE3_1,RGX_CR_BIF_CAT_BASE3_1" hexmask.long.tbyte 0x1C 8.--31. 1. "Reserved_40,Reserved_40" newline hexmask.long.byte 0x1C 0.--7. 1. "ADDR,ADDR" line.long 0x20 "RGX_CR_BIF_CAT_BASE4_0,RGX_CR_BIF_CAT_BASE4_0" hexmask.long.tbyte 0x20 12.--31. 1. "ADDR,ADDR" newline hexmask.long.word 0x20 0.--11. 1. "Reserved_0,Reserved_0" line.long 0x24 "RGX_CR_BIF_CAT_BASE4_1,RGX_CR_BIF_CAT_BASE4_1" hexmask.long.tbyte 0x24 8.--31. 1. "Reserved_40,Reserved_40" newline hexmask.long.byte 0x24 0.--7. 1. "ADDR,ADDR" line.long 0x28 "RGX_CR_BIF_CAT_BASE5_0,RGX_CR_BIF_CAT_BASE5_0" hexmask.long.tbyte 0x28 12.--31. 1. "ADDR,ADDR" newline hexmask.long.word 0x28 0.--11. 1. "Reserved_0,Reserved_0" line.long 0x2C "RGX_CR_BIF_CAT_BASE5_1,RGX_CR_BIF_CAT_BASE5_1" hexmask.long.tbyte 0x2C 8.--31. 1. "Reserved_40,Reserved_40" newline hexmask.long.byte 0x2C 0.--7. 1. "ADDR,ADDR" line.long 0x30 "RGX_CR_BIF_CAT_BASE6_0,RGX_CR_BIF_CAT_BASE6_0" hexmask.long.tbyte 0x30 12.--31. 1. "ADDR,ADDR" newline hexmask.long.word 0x30 0.--11. 1. "Reserved_0,Reserved_0" line.long 0x34 "RGX_CR_BIF_CAT_BASE6_1,RGX_CR_BIF_CAT_BASE6_1" hexmask.long.tbyte 0x34 8.--31. 1. "Reserved_40,Reserved_40" newline hexmask.long.byte 0x34 0.--7. 1. "ADDR,ADDR" line.long 0x38 "RGX_CR_BIF_CAT_BASE7_0,RGX_CR_BIF_CAT_BASE7_0" hexmask.long.tbyte 0x38 12.--31. 1. "ADDR,ADDR" newline hexmask.long.word 0x38 0.--11. 1. "Reserved_0,Reserved_0" line.long 0x3C "RGX_CR_BIF_CAT_BASE7_1,RGX_CR_BIF_CAT_BASE7_1" hexmask.long.tbyte 0x3C 8.--31. 1. "Reserved_40,Reserved_40" newline hexmask.long.byte 0x3C 0.--7. 1. "ADDR,ADDR" line.long 0x40 "RGX_CR_BIF_CAT_BASE_INDEX_0,Index registers per data master. Byte aligned fields to allow byte-masked access" hexmask.long.word 0x40 22.--31. 1. "Reserved_22,Reserved_22" newline bitfld.long 0x40 19.--21. "TDM,Catalogue Base number for TDM data master" "0,1,2,3,4,5,6,7" newline bitfld.long 0x40 16.--18. "CDM,Catalogue Base number for CDM data master" "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x40 11.--15. 1. "Reserved_11,Reserved_11" newline bitfld.long 0x40 8.--10. "PIXEL,Catalogue Base number for PIXEL data master" "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x40 3.--7. 1. "Reserved_3,Reserved_3" newline bitfld.long 0x40 0.--2. "TA,Catalogue Base number for TA data master" "0,1,2,3,4,5,6,7" line.long 0x44 "RGX_CR_BIF_CAT_BASE_INDEX_1,Index registers per data master. Byte aligned fields to allow byte-masked access" hexmask.long 0x44 3.--31. 1. "Reserved_35,Reserved_35" newline bitfld.long 0x44 0.--2. "HOST,Catalogue Base number for HOST data master" "0,1,2,3,4,5,6,7" line.long 0x48 "RGX_CR_BIF_PM_CAT_BASE_VCE0_0,PM catalogue base address for VCE context 0" hexmask.long.tbyte 0x48 12.--31. 1. "ADDR,ADDR" newline hexmask.long.word 0x48 2.--11. 1. "Reserved_2,Reserved_2" newline bitfld.long 0x48 1. "WRAP,Indicates address space has been fully allocated" "0,1" newline bitfld.long 0x48 0. "VALID,VALID" "0,1" line.long 0x4C "RGX_CR_BIF_PM_CAT_BASE_VCE0_1,PM catalogue base address for VCE context 0" hexmask.long.byte 0x4C 28.--31. 1. "Reserved_60,Reserved_60" newline hexmask.long.tbyte 0x4C 8.--27. 1. "INIT_PAGE,INIT_PAGE" newline hexmask.long.byte 0x4C 0.--7. 1. "ADDR,ADDR" line.long 0x50 "RGX_CR_BIF_PM_CAT_BASE_TE0_0,PM catalogue base address for TE context 0" hexmask.long.tbyte 0x50 12.--31. 1. "ADDR,ADDR" newline hexmask.long.word 0x50 2.--11. 1. "Reserved_2,Reserved_2" newline bitfld.long 0x50 1. "WRAP,WRAP" "0,1" newline bitfld.long 0x50 0. "VALID,VALID" "0,1" line.long 0x54 "RGX_CR_BIF_PM_CAT_BASE_TE0_1,PM catalogue base address for TE context 0" hexmask.long.byte 0x54 28.--31. 1. "Reserved_60,Reserved_60" newline hexmask.long.tbyte 0x54 8.--27. 1. "INIT_PAGE,INIT_PAGE" newline hexmask.long.byte 0x54 0.--7. 1. "ADDR,ADDR" group.long 0x1260++0x17 line.long 0x0 "RGX_CR_BIF_PM_CAT_BASE_ALIST0_0,PM catalogue base address for ALIST context 0" hexmask.long.tbyte 0x0 12.--31. 1. "ADDR,ADDR" newline hexmask.long.word 0x0 2.--11. 1. "Reserved_2,Reserved_2" newline bitfld.long 0x0 1. "WRAP,WRAP" "0,1" newline bitfld.long 0x0 0. "VALID,VALID" "0,1" line.long 0x4 "RGX_CR_BIF_PM_CAT_BASE_ALIST0_1,PM catalogue base address for ALIST context 0" hexmask.long.byte 0x4 28.--31. 1. "Reserved_60,Reserved_60" newline hexmask.long.tbyte 0x4 8.--27. 1. "INIT_PAGE,INIT_PAGE" newline hexmask.long.byte 0x4 0.--7. 1. "ADDR,ADDR" line.long 0x8 "RGX_CR_BIF_PM_CAT_BASE_VCE1_0,PM catalogue base address for VCE context 1" hexmask.long.tbyte 0x8 12.--31. 1. "ADDR,ADDR" newline hexmask.long.word 0x8 2.--11. 1. "Reserved_2,Reserved_2" newline bitfld.long 0x8 1. "WRAP,WRAP" "0,1" newline bitfld.long 0x8 0. "VALID,VALID" "0,1" line.long 0xC "RGX_CR_BIF_PM_CAT_BASE_VCE1_1,PM catalogue base address for VCE context 1" hexmask.long.byte 0xC 28.--31. 1. "Reserved_60,Reserved_60" newline hexmask.long.tbyte 0xC 8.--27. 1. "INIT_PAGE,INIT_PAGE" newline hexmask.long.byte 0xC 0.--7. 1. "ADDR,ADDR" line.long 0x10 "RGX_CR_BIF_PM_CAT_BASE_TE1_0,PM catalogue base address for TE context 1" hexmask.long.tbyte 0x10 12.--31. 1. "ADDR,ADDR" newline hexmask.long.word 0x10 2.--11. 1. "Reserved_2,Reserved_2" newline bitfld.long 0x10 1. "WRAP,WRAP" "0,1" newline bitfld.long 0x10 0. "VALID,VALID" "0,1" line.long 0x14 "RGX_CR_BIF_PM_CAT_BASE_TE1_1,PM catalogue base address for TE context 1" hexmask.long.byte 0x14 28.--31. 1. "Reserved_60,Reserved_60" newline hexmask.long.tbyte 0x14 8.--27. 1. "INIT_PAGE,INIT_PAGE" newline hexmask.long.byte 0x14 0.--7. 1. "ADDR,ADDR" group.long 0x1280++0x7 line.long 0x0 "RGX_CR_BIF_PM_CAT_BASE_ALIST1_0,PM catalogue base address for ALIST context 1" hexmask.long.tbyte 0x0 12.--31. 1. "ADDR,ADDR" newline hexmask.long.word 0x0 2.--11. 1. "Reserved_2,Reserved_2" newline bitfld.long 0x0 1. "WRAP,WRAP" "0,1" newline bitfld.long 0x0 0. "VALID,VALID" "0,1" line.long 0x4 "RGX_CR_BIF_PM_CAT_BASE_ALIST1_1,PM catalogue base address for ALIST context 1" hexmask.long.byte 0x4 28.--31. 1. "Reserved_60,Reserved_60" newline hexmask.long.tbyte 0x4 8.--27. 1. "INIT_PAGE,INIT_PAGE" newline hexmask.long.byte 0x4 0.--7. 1. "ADDR,ADDR" rgroup.long 0x1288++0x7 line.long 0x0 "RGX_CR_BIF_MMU_ENTRY_STATUS_0,Status of pending entry" hexmask.long.tbyte 0x0 12.--31. 1. "ADDRESS,Virtual 4KB address" newline hexmask.long.byte 0x0 8.--11. 1. "Reserved_8,Reserved_8" newline hexmask.long.byte 0x0 4.--7. 1. "CAT_BASE,Catalogue base address number" newline bitfld.long 0x0 2.--3. "Reserved_2,Reserved_2" "0,1,2,3" newline bitfld.long 0x0 0.--1. "DATA_TYPE,MMU data type '00' = PT '01' = PD '10' = PC" "0,1,2,3" line.long 0x4 "RGX_CR_BIF_MMU_ENTRY_STATUS_1,Status of pending entry" hexmask.long.tbyte 0x4 8.--31. 1. "Reserved_40,Reserved_40" newline hexmask.long.byte 0x4 0.--7. 1. "ADDRESS,Virtual 4KB address" group.long 0x1290++0x7 line.long 0x0 "RGX_CR_BIF_MMU_ENTRY_0,Indicates MMU is waiting on the driver to map an entry" hexmask.long 0x0 2.--31. 1. "Reserved_2,Reserved_2" newline bitfld.long 0x0 1. "ENABLE,When set PENDING will trigger an interrupt back to the host CPU (bypassing the FW)" "0,1" newline bitfld.long 0x0 0. "PENDING,PENDING" "0,1" line.long 0x4 "RGX_CR_BIF_MMU_ENTRY_1,Indicates MMU is waiting on the driver to map an entry" hexmask.long 0x4 0.--31. 1. "Reserved_2,Reserved_2" group.long 0x12A0++0xF line.long 0x0 "RGX_CR_BIF_CTRL_INVAL_0,Invalidation bits allowing BIF/MMU to clear when invalidation complete" hexmask.long 0x0 4.--31. 1. "Reserved_4,Reserved_4" newline bitfld.long 0x0 3. "TLB1,TLB1" "0,1" newline bitfld.long 0x0 2. "PC,PC" "0,1" newline bitfld.long 0x0 1. "PD,PD" "0,1" newline bitfld.long 0x0 0. "PT,PT" "0,1" line.long 0x4 "RGX_CR_BIF_CTRL_INVAL_1,Invalidation bits allowing BIF/MMU to clear when invalidation complete" hexmask.long 0x4 0.--31. 1. "Reserved_4,Reserved_4" line.long 0x8 "RGX_CR_BIF_CTRL_0,Miscellaneous controls" hexmask.long.tbyte 0x8 9.--31. 1. "Reserved_9,Reserved_9" newline bitfld.long 0x8 8. "PAUSE_MMU_BIF4,Stalls BIF4 input to MMU" "0,1" newline bitfld.long 0x8 7. "ENABLE_MMU_QUEUE_BYPASS,Enables bypassing of the MMU queue for cache hits" "0,1" newline bitfld.long 0x8 6. "ENABLE_MMU_AUTO_PREFETCH,Enables automatic prefetching based on incoming requests" "0,1" newline bitfld.long 0x8 5. "PAUSE_MMU_BIF3,Stalls BIF3 input to MMU" "0,1" newline bitfld.long 0x8 4. "PAUSE_MMU_BIF2,Stalls BIF2 input to MMU" "0,1" newline bitfld.long 0x8 3. "PAUSE_BIF1,Stalls BIF1 pipeline" "0,1" newline bitfld.long 0x8 2. "PAUSE_MMU_PM,Stalls PM input to MMU" "0,1" newline bitfld.long 0x8 1. "PAUSE_MMU_BIF1,Stalls BIF1 input to MMU" "0,1" newline bitfld.long 0x8 0. "PAUSE_MMU_BIF0,Stalls BIF0 input to MMU" "0,1" line.long 0xC "RGX_CR_BIF_CTRL_1,Miscellaneous controls" hexmask.long 0xC 0.--31. 1. "Reserved_9,Reserved_9" rgroup.long 0x12B0++0x27 line.long 0x0 "RGX_CR_BIF_FAULT_BANK0_MMU_STATUS_0,Indicates a fault has occurred on bank 0 and provides details of fault" hexmask.long.word 0x0 16.--31. 1. "Reserved_16,Reserved_16" newline hexmask.long.byte 0x0 12.--15. 1. "CAT_BASE,Catalogue base address number" newline bitfld.long 0x0 11. "Reserved_11,Reserved_11" "0,1" newline bitfld.long 0x0 8.--10. "PAGE_SIZE,Page size" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 7. "Reserved_7,Reserved_7" "0,1" newline bitfld.long 0x0 5.--6. "DATA_TYPE,MMU data type that was invalid (on valid fault)" "0,1,2,3" newline bitfld.long 0x0 4. "FAULT_RO,Indicates read-only fault('1') or valid fault('0')" "0,1" newline bitfld.long 0x0 3. "Reserved_3,Reserved_3" "0,1" newline bitfld.long 0x0 2. "FAULT_PM_META_RO,Indicates pm/meta protected region fault" "0,1" newline bitfld.long 0x0 1. "Reserved_1,Reserved_1" "0,1" newline bitfld.long 0x0 0. "FAULT,Indicates a fault has occured" "0,1" line.long 0x4 "RGX_CR_BIF_FAULT_BANK0_MMU_STATUS_1,Indicates a fault has occurred on bank 0 and provides details of fault" hexmask.long 0x4 0.--31. 1. "Reserved_16,Reserved_16" line.long 0x8 "RGX_CR_BIF_FAULT_BANK0_REQ_STATUS_0,Provides details of the request that faulted on bank 0" hexmask.long 0x8 4.--31. 1. "ADDRESS,ADDRESS" newline hexmask.long.byte 0x8 0.--3. 1. "Reserved_0,Reserved_0" line.long 0xC "RGX_CR_BIF_FAULT_BANK0_REQ_STATUS_1,Provides details of the request that faulted on bank 0" hexmask.long.word 0xC 21.--31. 1. "Reserved_53,Reserved_53" newline bitfld.long 0xC 20. "RNW,RNW" "0,1" newline hexmask.long.byte 0xC 14.--19. 1. "TAG_SB,TAG_SB" newline hexmask.long.byte 0xC 8.--13. 1. "TAG_ID,TAG_ID" newline hexmask.long.byte 0xC 0.--7. 1. "ADDRESS,ADDRESS" line.long 0x10 "RGX_CR_BIF_FAULT_BANK1_MMU_STATUS_0,Indicates a fault has occurred on bank 1 and provides details of fault" hexmask.long.word 0x10 16.--31. 1. "Reserved_16,Reserved_16" newline hexmask.long.byte 0x10 12.--15. 1. "CAT_BASE,Catalogue base address number" newline bitfld.long 0x10 11. "Reserved_11,Reserved_11" "0,1" newline bitfld.long 0x10 8.--10. "PAGE_SIZE,Page size" "0,1,2,3,4,5,6,7" newline bitfld.long 0x10 7. "Reserved_7,Reserved_7" "0,1" newline bitfld.long 0x10 5.--6. "DATA_TYPE,MMU data type that was invalid (on valid fault)" "0,1,2,3" newline bitfld.long 0x10 4. "FAULT_RO,Indicates read-only fault('1') of valid fault('0')" "0,1" newline bitfld.long 0x10 3. "Reserved_3,Reserved_3" "0,1" newline bitfld.long 0x10 2. "FAULT_PM_META_RO,Indicates pm/meta protected region fault" "0,1" newline bitfld.long 0x10 1. "Reserved_1,Reserved_1" "0,1" newline bitfld.long 0x10 0. "FAULT,Indicates a fault has occured" "0,1" line.long 0x14 "RGX_CR_BIF_FAULT_BANK1_MMU_STATUS_1,Indicates a fault has occurred on bank 1 and provides details of fault" hexmask.long 0x14 0.--31. 1. "Reserved_16,Reserved_16" line.long 0x18 "RGX_CR_BIF_FAULT_BANK1_REQ_STATUS_0,Provides details of the request that faulted on bank 1" hexmask.long 0x18 4.--31. 1. "ADDRESS,ADDRESS" newline hexmask.long.byte 0x18 0.--3. 1. "Reserved_0,Reserved_0" line.long 0x1C "RGX_CR_BIF_FAULT_BANK1_REQ_STATUS_1,Provides details of the request that faulted on bank 1" hexmask.long.word 0x1C 19.--31. 1. "Reserved_51,Reserved_51" newline bitfld.long 0x1C 18. "RNW,RNW" "0,1" newline hexmask.long.byte 0x1C 12.--17. 1. "TAG_SB,TAG_SB" newline hexmask.long.byte 0x1C 8.--11. 1. "TAG_ID,TAG_ID" newline hexmask.long.byte 0x1C 0.--7. 1. "ADDRESS,ADDRESS" line.long 0x20 "RGX_CR_BIF_MMU_STATUS_0,General MMU status" bitfld.long 0x20 29.--31. "Reserved_29,Reserved_29" "0,1,2,3,4,5,6,7" newline bitfld.long 0x20 28. "PM_FAULT,PM_FAULT" "0,1" newline hexmask.long.byte 0x20 20.--27. 1. "PC_DATA,PC_DATA" newline hexmask.long.byte 0x20 12.--19. 1. "PD_DATA,PD_DATA" newline hexmask.long.byte 0x20 4.--11. 1. "PT_DATA,PT_DATA" newline bitfld.long 0x20 3. "Reserved_3,Reserved_3" "0,1" newline bitfld.long 0x20 2. "STALLED,STALLED" "0,1" newline bitfld.long 0x20 1. "PAUSED,PAUSED" "0,1" newline bitfld.long 0x20 0. "BUSY,BUSY" "0,1" line.long 0x24 "RGX_CR_BIF_MMU_STATUS_1,General MMU status" hexmask.long 0x24 0.--31. 1. "Reserved_29,Reserved_29" group.long 0x12D8++0x3F line.long 0x0 "RGX_CR_BIF_TILING_CFG0_0,This register defines 8 RANGEs in which BIF Tiling can be configured. Each RANGE is given a Stride and a MIN and MAX 4KB aligned address to define the region of Address Space to be tiled. The BIF_TILING_CAT_BASE_INDEX register is.." hexmask.long.byte 0x0 28.--31. 1. "Reserved_28,Reserved_28" newline hexmask.long 0x0 0.--27. 1. "MIN_ADDRESS,4KB aligned min address for tiling" line.long 0x4 "RGX_CR_BIF_TILING_CFG0_1,This register defines 8 RANGEs in which BIF Tiling can be configured. Each RANGE is given a Stride and a MIN and MAX 4KB aligned address to define the region of Address Space to be tiled. The BIF_TILING_CAT_BASE_INDEX register is.." bitfld.long 0x4 29.--31. "XSTRIDE,defines x tile stride. The value in the register is equal to log2(number of tiles in x)-1 e. g. a value of 0 gives 2 x-tiles and a value of 3 gives 16 x-tiles" "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 28. "ENABLE,enables tiling range" "0,1" newline hexmask.long 0x4 0.--27. 1. "MAX_ADDRESS,4KB aligned max address for tiling" line.long 0x8 "RGX_CR_BIF_TILING_CFG1_0,This register defines 8 RANGEs in which BIF Tiling can be configured. Each RANGE is given a Stride and a MIN and MAX 4KB aligned address to define the region of Address Space to be tiled. The BIF_TILING_CAT_BASE_INDEX register is.." hexmask.long.byte 0x8 28.--31. 1. "Reserved_28,Reserved_28" newline hexmask.long 0x8 0.--27. 1. "MIN_ADDRESS,4KB aligned min address for tiling" line.long 0xC "RGX_CR_BIF_TILING_CFG1_1,This register defines 8 RANGEs in which BIF Tiling can be configured. Each RANGE is given a Stride and a MIN and MAX 4KB aligned address to define the region of Address Space to be tiled. The BIF_TILING_CAT_BASE_INDEX register is.." bitfld.long 0xC 29.--31. "XSTRIDE,defines x tile stride. The value in the register is equal to log2(number of tiles in x)-1 e. g. a value of 0 gives 2 x-tiles and a value of 3 gives 16 x-tiles" "0,1,2,3,4,5,6,7" newline bitfld.long 0xC 28. "ENABLE,enables tiling range" "0,1" newline hexmask.long 0xC 0.--27. 1. "MAX_ADDRESS,4KB aligned max address for tiling" line.long 0x10 "RGX_CR_BIF_TILING_CFG2_0,This register defines 8 RANGEs in which BIF Tiling can be configured. Each RANGE is given a Stride and a MIN and MAX 4KB aligned address to define the region of Address Space to be tiled. The BIF_TILING_CAT_BASE_INDEX register is.." hexmask.long.byte 0x10 28.--31. 1. "Reserved_28,Reserved_28" newline hexmask.long 0x10 0.--27. 1. "MIN_ADDRESS,4KB aligned min address for tiling" line.long 0x14 "RGX_CR_BIF_TILING_CFG2_1,This register defines 8 RANGEs in which BIF Tiling can be configured. Each RANGE is given a Stride and a MIN and MAX 4KB aligned address to define the region of Address Space to be tiled. The BIF_TILING_CAT_BASE_INDEX register is.." bitfld.long 0x14 29.--31. "XSTRIDE,defines x tile stride. The value in the register is equal to log2(number of tiles in x)-1 e. g. a value of 0 gives 2 x-tiles and a value of 3 gives 16 x-tiles" "0,1,2,3,4,5,6,7" newline bitfld.long 0x14 28. "ENABLE,enables tiling range" "0,1" newline hexmask.long 0x14 0.--27. 1. "MAX_ADDRESS,4KB aligned max address for tiling" line.long 0x18 "RGX_CR_BIF_TILING_CFG3_0,This register defines 8 RANGEs in which BIF Tiling can be configured. Each RANGE is given a Stride and a MIN and MAX 4KB aligned address to define the region of Address Space to be tiled. The BIF_TILING_CAT_BASE_INDEX register is.." hexmask.long.byte 0x18 28.--31. 1. "Reserved_28,Reserved_28" newline hexmask.long 0x18 0.--27. 1. "MIN_ADDRESS,4KB aligned min address for tiling" line.long 0x1C "RGX_CR_BIF_TILING_CFG3_1,This register defines 8 RANGEs in which BIF Tiling can be configured. Each RANGE is given a Stride and a MIN and MAX 4KB aligned address to define the region of Address Space to be tiled. The BIF_TILING_CAT_BASE_INDEX register is.." bitfld.long 0x1C 29.--31. "XSTRIDE,defines x tile stride. The value in the register is equal to log2(number of tiles in x)-1 e. g. a value of 0 gives 2 x-tiles and a value of 3 gives 16 x-tiles" "0,1,2,3,4,5,6,7" newline bitfld.long 0x1C 28. "ENABLE,enables tiling range" "0,1" newline hexmask.long 0x1C 0.--27. 1. "MAX_ADDRESS,4KB aligned max address for tiling" line.long 0x20 "RGX_CR_BIF_TILING_CFG4_0,This register defines 8 RANGEs in which BIF Tiling can be configured. Each RANGE is given a Stride and a MIN and MAX 4KB aligned address to define the region of Address Space to be tiled. The BIF_TILING_CAT_BASE_INDEX register is.." hexmask.long.byte 0x20 28.--31. 1. "Reserved_28,Reserved_28" newline hexmask.long 0x20 0.--27. 1. "MIN_ADDRESS,4KB aligned min address for tiling" line.long 0x24 "RGX_CR_BIF_TILING_CFG4_1,This register defines 8 RANGEs in which BIF Tiling can be configured. Each RANGE is given a Stride and a MIN and MAX 4KB aligned address to define the region of Address Space to be tiled. The BIF_TILING_CAT_BASE_INDEX register is.." bitfld.long 0x24 29.--31. "XSTRIDE,defines x tile stride. The value in the register is equal to log2(number of tiles in x)-1 e. g. a value of 0 gives 2 x-tiles and a value of 3 gives 16 x-tiles" "0,1,2,3,4,5,6,7" newline bitfld.long 0x24 28. "ENABLE,enables tiling range" "0,1" newline hexmask.long 0x24 0.--27. 1. "MAX_ADDRESS,4KB aligned max address for tiling" line.long 0x28 "RGX_CR_BIF_TILING_CFG5_0,This register defines 8 RANGEs in which BIF Tiling can be configured. Each RANGE is given a Stride and a MIN and MAX 4KB aligned address to define the region of Address Space to be tiled. The BIF_TILING_CAT_BASE_INDEX register is.." hexmask.long.byte 0x28 28.--31. 1. "Reserved_28,Reserved_28" newline hexmask.long 0x28 0.--27. 1. "MIN_ADDRESS,4KB aligned min address for tiling" line.long 0x2C "RGX_CR_BIF_TILING_CFG5_1,This register defines 8 RANGEs in which BIF Tiling can be configured. Each RANGE is given a Stride and a MIN and MAX 4KB aligned address to define the region of Address Space to be tiled. The BIF_TILING_CAT_BASE_INDEX register is.." bitfld.long 0x2C 29.--31. "XSTRIDE,defines x tile stride. The value in the register is equal to log2(number of tiles in x)-1 e. g. a value of 0 gives 2 x-tiles and a value of 3 gives 16 x-tiles" "0,1,2,3,4,5,6,7" newline bitfld.long 0x2C 28. "ENABLE,enables tiling range" "0,1" newline hexmask.long 0x2C 0.--27. 1. "MAX_ADDRESS,4KB aligned max address for tiling" line.long 0x30 "RGX_CR_BIF_TILING_CFG6_0,This register defines 8 RANGEs in which BIF Tiling can be configured. Each RANGE is given a Stride and a MIN and MAX 4KB aligned address to define the region of Address Space to be tiled. The BIF_TILING_CAT_BASE_INDEX register is.." hexmask.long.byte 0x30 28.--31. 1. "Reserved_28,Reserved_28" newline hexmask.long 0x30 0.--27. 1. "MIN_ADDRESS,4KB aligned min address for tiling" line.long 0x34 "RGX_CR_BIF_TILING_CFG6_1,This register defines 8 RANGEs in which BIF Tiling can be configured. Each RANGE is given a Stride and a MIN and MAX 4KB aligned address to define the region of Address Space to be tiled. The BIF_TILING_CAT_BASE_INDEX register is.." bitfld.long 0x34 29.--31. "XSTRIDE,defines x tile stride. The value in the register is equal to log2(number of tiles in x)-1 e. g. a value of 0 gives 2 x-tiles and a value of 3 gives 16 x-tiles" "0,1,2,3,4,5,6,7" newline bitfld.long 0x34 28. "ENABLE,enables tiling range" "0,1" newline hexmask.long 0x34 0.--27. 1. "MAX_ADDRESS,4KB aligned max address for tiling" line.long 0x38 "RGX_CR_BIF_TILING_CFG7_0,This register defines 8 RANGEs in which BIF Tiling can be configured. Each RANGE is given a Stride and a MIN and MAX 4KB aligned address to define the region of Address Space to be tiled. The BIF_TILING_CAT_BASE_INDEX register is.." hexmask.long.byte 0x38 28.--31. 1. "Reserved_28,Reserved_28" newline hexmask.long 0x38 0.--27. 1. "MIN_ADDRESS,4KB aligned min address for tiling" line.long 0x3C "RGX_CR_BIF_TILING_CFG7_1,This register defines 8 RANGEs in which BIF Tiling can be configured. Each RANGE is given a Stride and a MIN and MAX 4KB aligned address to define the region of Address Space to be tiled. The BIF_TILING_CAT_BASE_INDEX register is.." bitfld.long 0x3C 29.--31. "XSTRIDE,defines x tile stride. The value in the register is equal to log2(number of tiles in x)-1 e. g. a value of 0 gives 2 x-tiles and a value of 3 gives 16 x-tiles" "0,1,2,3,4,5,6,7" newline bitfld.long 0x3C 28. "ENABLE,enables tiling range" "0,1" newline hexmask.long 0x3C 0.--27. 1. "MAX_ADDRESS,4KB aligned max address for tiling" repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) group.long ($2+0x1318)++0x3 line.long 0x0 "RGX_CR_BIF_TILING_CAT_BASE_INDEX_$1,This register defines the Catalogue Base Index applying to each tiling configuration register. An input address passing the RANGE test is also qualified against the RANGE INDEX before Tiling can proceed." hexmask.long.byte 0x0 27.--31. 1. "Reserved_27,Reserved_27" newline bitfld.long 0x0 24.--26. "RANGE3,RANGE3" "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x0 19.--23. 1. "Reserved_19,Reserved_19" newline bitfld.long 0x0 16.--18. "RANGE2,RANGE2" "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x0 11.--15. 1. "Reserved_11,Reserved_11" newline bitfld.long 0x0 8.--10. "RANGE1,RANGE1" "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x0 3.--7. 1. "Reserved_3,Reserved_3" newline bitfld.long 0x0 0.--2. "RANGE0,RANGE0" "0,1,2,3,4,5,6,7" repeat.end rgroup.long 0x1320++0x1F line.long 0x0 "RGX_CR_BIF_READS_EXT_STATUS_0,Outstanding read data external to BIF for BIF128 and MMU" hexmask.long.word 0x0 23.--31. 1. "Reserved_23,Reserved_23" newline hexmask.long.byte 0x0 16.--22. 1. "MMU,MMU" newline hexmask.long.word 0x0 0.--15. 1. "BANK1,BANK1" line.long 0x4 "RGX_CR_BIF_READS_EXT_STATUS_1,Outstanding read data external to BIF for BIF128 and MMU" hexmask.long 0x4 0.--31. 1. "Reserved_23,Reserved_23" line.long 0x8 "RGX_CR_BIF_READS_INT_STATUS_0,Outstanding 256-bit read data in return data FIFO for BIF128 and MMU" hexmask.long.word 0x8 23.--31. 1. "Reserved_23,Reserved_23" newline hexmask.long.byte 0x8 16.--22. 1. "MMU,MMU" newline hexmask.long.word 0x8 0.--15. 1. "BANK1,BANK1" line.long 0xC "RGX_CR_BIF_READS_INT_STATUS_1,Outstanding 256-bit read data in return data FIFO for BIF128 and MMU" hexmask.long 0xC 0.--31. 1. "Reserved_23,Reserved_23" line.long 0x10 "RGX_CR_BIFPM_READS_INT_STATUS_0,Outstanding 256-bit read data in return data FIFO for BIF256" hexmask.long.word 0x10 16.--31. 1. "Reserved_16,Reserved_16" newline hexmask.long.word 0x10 0.--15. 1. "BANK0,BANK0" line.long 0x14 "RGX_CR_BIFPM_READS_INT_STATUS_1,Outstanding 256-bit read data in return data FIFO for BIF256" hexmask.long 0x14 0.--31. 1. "Reserved_16,Reserved_16" line.long 0x18 "RGX_CR_BIFPM_READS_EXT_STATUS_0,Outstanding 256-bit read data external to BIF for BIF256" hexmask.long.word 0x18 16.--31. 1. "Reserved_16,Reserved_16" newline hexmask.long.word 0x18 0.--15. 1. "BANK0,BANK0" line.long 0x1C "RGX_CR_BIFPM_READS_EXT_STATUS_1,Outstanding 256-bit read data external to BIF for BIF256" hexmask.long 0x1C 0.--31. 1. "Reserved_16,Reserved_16" group.long 0x1340++0xF line.long 0x0 "RGX_CR_BIFPM_CTRL_0,Miscellaneous controls" hexmask.long 0x0 2.--31. 1. "Reserved_2,Reserved_2" newline bitfld.long 0x0 1. "ENABLE_SLC_STALLING,Enables BIF to stall returns from SLC so that requests can be made even when there is no space in the BIF return buffer (only when no chance of lockup)" "0,1" newline bitfld.long 0x0 0. "PAUSE_BIF0,Stalls BIF0 pipeline" "0,1" line.long 0x4 "RGX_CR_BIFPM_CTRL_1,Miscellaneous controls" hexmask.long 0x4 0.--31. 1. "Reserved_2,Reserved_2" line.long 0x8 "RGX_CR_BIFPM_CTRL_INVAL_0,Invalidation bits allowing BIF to clear when invalidation complete" hexmask.long 0x8 1.--31. 1. "Reserved_1,Reserved_1" newline bitfld.long 0x8 0. "TLB0,TLB0" "0,1" line.long 0xC "RGX_CR_BIFPM_CTRL_INVAL_1,Invalidation bits allowing BIF to clear when invalidation complete" hexmask.long 0xC 0.--31. 1. "Reserved_1,Reserved_1" rgroup.long 0x1350++0xF line.long 0x0 "RGX_CR_BIFPM_STATUS_MMU_0,Outstanding MMU requests from BIF0" hexmask.long.tbyte 0x0 8.--31. 1. "Reserved_8,Reserved_8" newline hexmask.long.byte 0x0 0.--7. 1. "REQUESTS,REQUESTS" line.long 0x4 "RGX_CR_BIFPM_STATUS_MMU_1,Outstanding MMU requests from BIF0" hexmask.long 0x4 0.--31. 1. "Reserved_8,Reserved_8" line.long 0x8 "RGX_CR_BIF_STATUS_MMU_0,Outstanding MMU requests from BIF1" hexmask.long.tbyte 0x8 8.--31. 1. "Reserved_8,Reserved_8" newline hexmask.long.byte 0x8 0.--7. 1. "REQUESTS,REQUESTS" line.long 0xC "RGX_CR_BIF_STATUS_MMU_1,Outstanding MMU requests from BIF1" hexmask.long 0xC 0.--31. 1. "Reserved_8,Reserved_8" group.long 0x1360++0x7 line.long 0x0 "RGX_CR_BIF_TILING_0,Sets tiling mode between 256byte x 16 rows (0) and 512byte x 8 rows (1)" hexmask.long 0x0 1.--31. 1. "Reserved_1,Reserved_1" newline bitfld.long 0x0 0. "MODE,MODE" "0,1" line.long 0x4 "RGX_CR_BIF_TILING_1,Sets tiling mode between 256byte x 16 rows (0) and 512byte x 8 rows (1)" hexmask.long 0x4 0.--31. 1. "Reserved_1,Reserved_1" repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) rgroup.long ($2+0x1370)++0x3 line.long 0x0 "RGX_CR_BIF_BLACKPEARL_PWR_$1,Power monitoring register" hexmask.long 0x0 0.--31. 1. "NUM_256BIT_TRANS,Number of 256-bit transactions" repeat.end repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) rgroup.long ($2+0x1378)++0x3 line.long 0x0 "RGX_CR_BIF_JONES_PWR_$1,Power monitoring register" hexmask.long 0x0 0.--31. 1. "NUM_256BIT_TRANS,Number of 256-bit transactions" repeat.end group.long 0x13E0++0x7 line.long 0x0 "RGX_CR_BIF_FAULT_READ_0,Specifies physical address to read from in the event of a faulting read request from BIF1" hexmask.long 0x0 4.--31. 1. "ADDRESS,ADDRESS" newline hexmask.long.byte 0x0 0.--3. 1. "Reserved_0,Reserved_0" line.long 0x4 "RGX_CR_BIF_FAULT_READ_1,Specifies physical address to read from in the event of a faulting read request from BIF1" hexmask.long.tbyte 0x4 8.--31. 1. "Reserved_40,Reserved_40" newline hexmask.long.byte 0x4 0.--7. 1. "ADDRESS,ADDRESS" repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) rgroup.long ($2+0x13E8)++0x3 line.long 0x0 "RGX_CR_BIF_PWR_$1,Power monitoring register" hexmask.long 0x0 0.--31. 1. "NUM_256BIT_TRANS,Number of 256-bit transactions" repeat.end group.long 0x13F8++0x7 line.long 0x0 "RGX_CR_BIF_MCU_RESERVED_0,Allows driver to change the amount of space in the return data FIFO reserved for the MCU" hexmask.long 0x0 5.--31. 1. "Reserved_5,Reserved_5" newline hexmask.long.byte 0x0 0.--4. 1. "SPACE,Granularity of 8 spaces minimum legal value 0x1" line.long 0x4 "RGX_CR_BIF_MCU_RESERVED_1,Allows driver to change the amount of space in the return data FIFO reserved for the MCU" hexmask.long 0x4 0.--31. 1. "Reserved_5,Reserved_5" rgroup.long 0x1430++0x27 line.long 0x0 "RGX_CR_TEXAS_BIF_FAULT_BANK0_MMU_STATUS_0,Indicates a fault has occurred on bank 0 and provides details of fault" hexmask.long.word 0x0 16.--31. 1. "Reserved_16,Reserved_16" newline hexmask.long.byte 0x0 12.--15. 1. "CAT_BASE,Catalogue base address number" newline bitfld.long 0x0 11. "Reserved_11,Reserved_11" "0,1" newline bitfld.long 0x0 8.--10. "PAGE_SIZE,Page size" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 7. "Reserved_7,Reserved_7" "0,1" newline bitfld.long 0x0 5.--6. "DATA_TYPE,MMU data type that was invalid (on valid fault)" "0,1,2,3" newline bitfld.long 0x0 4. "FAULT_RO,Indicates read-only fault('1') or valid fault('0')" "0,1" newline bitfld.long 0x0 3. "Reserved_3,Reserved_3" "0,1" newline bitfld.long 0x0 2. "FAULT_PM_META_RO,Indicates pm/meta protected region fault" "0,1" newline bitfld.long 0x0 1. "Reserved_1,Reserved_1" "0,1" newline bitfld.long 0x0 0. "FAULT,Indicates a fault has occured" "0,1" line.long 0x4 "RGX_CR_TEXAS_BIF_FAULT_BANK0_MMU_STATUS_1,Indicates a fault has occurred on bank 0 and provides details of fault" hexmask.long 0x4 0.--31. 1. "Reserved_16,Reserved_16" line.long 0x8 "RGX_CR_TEXAS_BIF_FAULT_BANK0_REQ_STATUS_0,Provides details of the request that faulted on bank 0" hexmask.long 0x8 4.--31. 1. "ADDRESS,ADDRESS" newline hexmask.long.byte 0x8 0.--3. 1. "Reserved_0,Reserved_0" line.long 0xC "RGX_CR_TEXAS_BIF_FAULT_BANK0_REQ_STATUS_1,Provides details of the request that faulted on bank 0" hexmask.long.word 0xC 19.--31. 1. "Reserved_51,Reserved_51" newline bitfld.long 0xC 18. "RNW,RNW" "0,1" newline hexmask.long.byte 0xC 12.--17. 1. "TAG_SB,TAG_SB" newline hexmask.long.byte 0xC 8.--11. 1. "TAG_ID,TAG_ID" newline hexmask.long.byte 0xC 0.--7. 1. "ADDRESS,ADDRESS" line.long 0x10 "RGX_CR_TEXAS_BIFPM_READS_INT_STATUS_0,Outstanding 256-bit read data in return data FIFO for BIF256" hexmask.long.word 0x10 16.--31. 1. "Reserved_16,Reserved_16" newline hexmask.long.word 0x10 0.--15. 1. "BANK0,BANK0" line.long 0x14 "RGX_CR_TEXAS_BIFPM_READS_INT_STATUS_1,Outstanding 256-bit read data in return data FIFO for BIF256" hexmask.long 0x14 0.--31. 1. "Reserved_16,Reserved_16" line.long 0x18 "RGX_CR_TEXAS_BIFPM_READS_EXT_STATUS_0,Outstanding 256-bit read data external to BIF for BIF256" hexmask.long.word 0x18 16.--31. 1. "Reserved_16,Reserved_16" newline hexmask.long.word 0x18 0.--15. 1. "BANK0,BANK0" line.long 0x1C "RGX_CR_TEXAS_BIFPM_READS_EXT_STATUS_1,Outstanding 256-bit read data external to BIF for BIF256" hexmask.long 0x1C 0.--31. 1. "Reserved_16,Reserved_16" line.long 0x20 "RGX_CR_TEXAS_BIFPM_STATUS_MMU_0,Outstanding MMU requests from BIF0" hexmask.long.tbyte 0x20 8.--31. 1. "Reserved_8,Reserved_8" newline hexmask.long.byte 0x20 0.--7. 1. "REQUESTS,REQUESTS" line.long 0x24 "RGX_CR_TEXAS_BIFPM_STATUS_MMU_1,Outstanding MMU requests from BIF0" hexmask.long 0x24 0.--31. 1. "Reserved_8,Reserved_8" repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) group.long ($2+0x1460)++0x3 line.long 0x0 "RGX_CR_BIF_OSID0_$1,Defines OSID for each CAT_BASE" hexmask.long.byte 0x0 27.--31. 1. "Reserved_27,Reserved_27" newline bitfld.long 0x0 24.--26. "CBASE3,OSID for CAT BASE 3" "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x0 19.--23. 1. "Reserved_19,Reserved_19" newline bitfld.long 0x0 16.--18. "CBASE2,OSID for CAT BASE 2" "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x0 11.--15. 1. "Reserved_11,Reserved_11" newline bitfld.long 0x0 8.--10. "CBASE1,OSID for CAT BASE 1" "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x0 3.--7. 1. "Reserved_3,Reserved_3" newline bitfld.long 0x0 0.--2. "CBASE0,OSID for CAT BASE 0" "0,1,2,3,4,5,6,7" repeat.end group.long 0x1468++0x7 line.long 0x0 "RGX_CR_BIF_OSID1_0,Defines OSID for each data master" hexmask.long.tbyte 0x0 11.--31. 1. "Reserved_11,Reserved_11" newline bitfld.long 0x0 8.--10. "PM_CTX1,OSID for VCE1 TE1 and ALIST1" "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x0 3.--7. 1. "Reserved_3,Reserved_3" newline bitfld.long 0x0 0.--2. "PM_CTX0,OSID for VCE0 TE0 and ALIST0" "0,1,2,3,4,5,6,7" line.long 0x4 "RGX_CR_BIF_OSID1_1,Defines OSID for each data master" hexmask.long 0x4 0.--31. 1. "Reserved_11,Reserved_11" group.long 0x1500++0x7 line.long 0x0 "RGX_CR_PBE_0,The PBE(Pixel back end) module scales and packs the pixel data before writing to memory. this register contains global control signals." hexmask.long.tbyte 0x0 9.--31. 1. "Reserved_9,Reserved_9" newline bitfld.long 0x0 8. "AA_EDGEOPT_OFF,Switches off the PBE-USE read optimisation during Anti aliasing mode. (This is typically for debug purposes only)" "0,1" newline hexmask.long.byte 0x0 0.--7. 1. "ALPHATHRESHOLD,Alpha threshold used when encoding 1555 format. If the internal 8bit Alpha value exceeds this value then a 1 is written to the top bit of the output otherwise a 0 is written" line.long 0x4 "RGX_CR_PBE_1,The PBE(Pixel back end) module scales and packs the pixel data before writing to memory. this register contains global control signals." hexmask.long 0x4 0.--31. 1. "Reserved_9,Reserved_9" rgroup.long 0x1508++0x7 line.long 0x0 "RGX_CR_PBE_EMIT_STATUS_0,This register indicates if the PixelBE would stall the USE if there were another emit. '0' indicates that the PixelBE would stall the USC. '1' indicates that the PixelBE would not stall the USE." hexmask.long.word 0x0 16.--31. 1. "Reserved_16,Reserved_16" newline bitfld.long 0x0 15. "USC15,Pipe 15 status" "0,1" newline bitfld.long 0x0 14. "USC14,Pipe 14 status" "0,1" newline bitfld.long 0x0 13. "USC13,Pipe 13 status" "0,1" newline bitfld.long 0x0 12. "USC12,Pipe 12 status" "0,1" newline bitfld.long 0x0 11. "USC11,Pipe 11 status" "0,1" newline bitfld.long 0x0 10. "USC10,Pipe 10 status" "0,1" newline bitfld.long 0x0 9. "USC9,Pipe 9 status" "0,1" newline bitfld.long 0x0 8. "USC8,Pipe 8 status" "0,1" newline bitfld.long 0x0 7. "USC7,Pipe 7 status" "0,1" newline bitfld.long 0x0 6. "USC6,Pipe 6 status" "0,1" newline bitfld.long 0x0 5. "USC5,Pipe 5 status" "0,1" newline bitfld.long 0x0 4. "USC4,Pipe 4 status" "0,1" newline bitfld.long 0x0 3. "USC3,Pipe 3 status" "0,1" newline bitfld.long 0x0 2. "USC2,Pipe 2 status" "0,1" newline bitfld.long 0x0 1. "USC1,Pipe 1 status" "0,1" newline bitfld.long 0x0 0. "USC0,Pipe 0 status" "0,1" line.long 0x4 "RGX_CR_PBE_EMIT_STATUS_1,This register indicates if the PixelBE would stall the USE if there were another emit. '0' indicates that the PixelBE would stall the USC. '1' indicates that the PixelBE would not stall the USE." hexmask.long 0x4 0.--31. 1. "Reserved_16,Reserved_16" group.long 0x1510++0x3F line.long 0x0 "RGX_CR_PBE_WORD0_MRT0_0,Pixel Back end State Word 0." bitfld.long 0x0 29.--31. "SWIZ_CHAN3,Swizzle for destination channel 3" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 26.--28. "SWIZ_CHAN2,Swizzle for destination channel 2" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 23.--25. "SWIZ_CHAN1,Swizzle for destination channel 1" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 20.--22. "SWIZ_CHAN0,Swizzle for destination channel 0" "0,1,2,3,4,5,6,7" newline hexmask.long.word 0x0 6.--19. 1. "MINCLIP_X,Min X Clip" newline bitfld.long 0x0 5. "TWOCOMP_GAMMA,Sets the gamma mode for 2 component targets" "0,1" newline bitfld.long 0x0 4. "GAMMA,Gamma enabled" "0,1" newline bitfld.long 0x0 3. "COMPRESSION,Frame buffer Compression enabled" "0,1" newline bitfld.long 0x0 2. "COMPRESS_SIZE,Block size for the compressor used with COMPRESS_SIZE_EXT register bit to define 8x8; 16x4 or 32x2 size COMPRESS_SIZE_EXT COMPRESS_SIZE SIZE 0 0 8x8 0 1 16x4 1 0 32x2 1 1 reserved" "0,1" newline bitfld.long 0x0 1. "COMP_INDIRECT_TABLE,If set indicates to the compressor that an indirect addressing is used otherwise direct addressing" "0,1" newline bitfld.long 0x0 0. "Y_FLIP,Y_FLIP" "0,1" line.long 0x4 "RGX_CR_PBE_WORD0_MRT0_1,Pixel Back end State Word 0." bitfld.long 0x4 30.--31. "X_RSRVD,Not used" "0,1,2,3" newline bitfld.long 0x4 29. "COMPRESS_SIZE_EXT,Extra bit to support 32x2 compression size used with COMPRESS_SIZE register bit to define 8x8; 16x4 or 32x2 size COMPRESS_SIZE_EXT COMPRESS_SIZE SIZE 0 0 8x8 0 1 16x4 1 0 32x2 1 1 reserved" "0,1" newline bitfld.long 0x4 28. "COMP_IADDR_MODE,FBC indirect addressing mode" "0,1" newline bitfld.long 0x4 27. "COMP_COR_ENABLE,Enable FBC correlation" "0,1" newline bitfld.long 0x4 26. "DITHER,Enable dither" "0,1" newline bitfld.long 0x4 25. "TILERELATIVE,Add tile offset" "0,1" newline bitfld.long 0x4 24. "DOWNSCALE,Perform box filter downscale" "0,1" newline hexmask.long.byte 0x4 20.--23. 1. "SIZE_Z,Z Size in pixels [log 2]" newline bitfld.long 0x4 18.--19. "ROTATION,Rotation angle" "0,1,2,3" newline hexmask.long.word 0x4 2.--17. 1. "LINESTRIDE,Linestride in 2 pixel units. 0 == 2. Supports 32KDWORD stride memory write" newline bitfld.long 0x4 0.--1. "MEMLAYOUT,Memory layout" "0,1,2,3" line.long 0x8 "RGX_CR_PBE_WORD0_MRT1_0,Pixel Back end State Word 0." bitfld.long 0x8 29.--31. "SWIZ_CHAN3,Swizzle for destination channel 3" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 26.--28. "SWIZ_CHAN2,Swizzle for destination channel 2" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 23.--25. "SWIZ_CHAN1,Swizzle for destination channel 1" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 20.--22. "SWIZ_CHAN0,Swizzle for destination channel 0" "0,1,2,3,4,5,6,7" newline hexmask.long.word 0x8 6.--19. 1. "MINCLIP_X,Min X Clip" newline bitfld.long 0x8 5. "TWOCOMP_GAMMA,Sets the gamma mode for 2 component targets" "0,1" newline bitfld.long 0x8 4. "GAMMA,Gamma enabled" "0,1" newline bitfld.long 0x8 3. "COMPRESSION,Frame buffer Compression enabled" "0,1" newline bitfld.long 0x8 2. "COMPRESS_SIZE,Block size for the compressor used with COMPRESS_SIZE_EXT register bit to define 8x8; 16x4 or 32x2 size COMPRESS_SIZE_EXT COMPRESS_SIZE SIZE 0 0 8x8 0 1 16x4 1 0 32x2 1 1 reserved" "0,1" newline bitfld.long 0x8 1. "COMP_INDIRECT_TABLE,If set indicates to the compressor that an indirect addressing is used otherwise direct addressing" "0,1" newline bitfld.long 0x8 0. "Y_FLIP,Y_FLIP" "0,1" line.long 0xC "RGX_CR_PBE_WORD0_MRT1_1,Pixel Back end State Word 0." bitfld.long 0xC 30.--31. "X_RSRVD,Not used" "0,1,2,3" newline bitfld.long 0xC 29. "COMPRESS_SIZE_EXT,Extra bit to support 32x2 compression size used with COMPRESS_SIZE register bit to define 8x8; 16x4 or 32x2 size COMPRESS_SIZE_EXT COMPRESS_SIZE SIZE 0 0 8x8 0 1 16x4 1 0 32x2 1 1 reserved" "0,1" newline bitfld.long 0xC 28. "COMP_IADDR_MODE,FBC indirect addressing mode" "0,1" newline bitfld.long 0xC 27. "COMP_COR_ENABLE,Enable FBC correlation" "0,1" newline bitfld.long 0xC 26. "DITHER,Enable dither" "0,1" newline bitfld.long 0xC 25. "TILERELATIVE,Add tile offset" "0,1" newline bitfld.long 0xC 24. "DOWNSCALE,Perform box filter downscale" "0,1" newline hexmask.long.byte 0xC 20.--23. 1. "SIZE_Z,Z Size in pixels [log 2]" newline bitfld.long 0xC 18.--19. "ROTATION,Rotation angle" "0,1,2,3" newline hexmask.long.word 0xC 2.--17. 1. "LINESTRIDE,Linestride in 2 pixel units. 0 == 2. Supports 32KDWORD stride memory write" newline bitfld.long 0xC 0.--1. "MEMLAYOUT,Memory layout" "0,1,2,3" line.long 0x10 "RGX_CR_PBE_WORD0_MRT2_0,Pixel Back end State Word 0." bitfld.long 0x10 29.--31. "SWIZ_CHAN3,Swizzle for destination channel 3" "0,1,2,3,4,5,6,7" newline bitfld.long 0x10 26.--28. "SWIZ_CHAN2,Swizzle for destination channel 2" "0,1,2,3,4,5,6,7" newline bitfld.long 0x10 23.--25. "SWIZ_CHAN1,Swizzle for destination channel 1" "0,1,2,3,4,5,6,7" newline bitfld.long 0x10 20.--22. "SWIZ_CHAN0,Swizzle for destination channel 0" "0,1,2,3,4,5,6,7" newline hexmask.long.word 0x10 6.--19. 1. "MINCLIP_X,Min X Clip" newline bitfld.long 0x10 5. "TWOCOMP_GAMMA,Sets the gamma mode for 2 component targets" "0,1" newline bitfld.long 0x10 4. "GAMMA,Gamma enabled" "0,1" newline bitfld.long 0x10 3. "COMPRESSION,Frame buffer Compression enabled" "0,1" newline bitfld.long 0x10 2. "COMPRESS_SIZE,Block size for the compressor used with COMPRESS_SIZE_EXT register bit to define 8x8; 16x4 or 32x2 size COMPRESS_SIZE_EXT COMPRESS_SIZE SIZE 0 0 8x8 0 1 16x4 1 0 32x2 1 1 reserved" "0,1" newline bitfld.long 0x10 1. "COMP_INDIRECT_TABLE,If set indicates to the compressor that an indirect addressing is used otherwise direct addressing" "0,1" newline bitfld.long 0x10 0. "Y_FLIP,Y_FLIP" "0,1" line.long 0x14 "RGX_CR_PBE_WORD0_MRT2_1,Pixel Back end State Word 0." bitfld.long 0x14 30.--31. "X_RSRVD,Not used" "0,1,2,3" newline bitfld.long 0x14 29. "COMPRESS_SIZE_EXT,Extra bit to support 32x2 compression size used with COMPRESS_SIZE register bit to define 8x8; 16x4 or 32x2 size COMPRESS_SIZE_EXT COMPRESS_SIZE SIZE 0 0 8x8 0 1 16x4 1 0 32x2 1 1 reserved" "0,1" newline bitfld.long 0x14 28. "COMP_IADDR_MODE,FBC indirect addressing mode" "0,1" newline bitfld.long 0x14 27. "COMP_COR_ENABLE,Enable FBC correlation" "0,1" newline bitfld.long 0x14 26. "DITHER,Enable dither" "0,1" newline bitfld.long 0x14 25. "TILERELATIVE,Add tile offset" "0,1" newline bitfld.long 0x14 24. "DOWNSCALE,Perform box filter downscale" "0,1" newline hexmask.long.byte 0x14 20.--23. 1. "SIZE_Z,Z Size in pixels [log 2]" newline bitfld.long 0x14 18.--19. "ROTATION,Rotation angle" "0,1,2,3" newline hexmask.long.word 0x14 2.--17. 1. "LINESTRIDE,Linestride in 2 pixel units. 0 == 2. Supports 32KDWORD stride memory write" newline bitfld.long 0x14 0.--1. "MEMLAYOUT,Memory layout" "0,1,2,3" line.long 0x18 "RGX_CR_PBE_WORD0_MRT3_0,Pixel Back end State Word 0." bitfld.long 0x18 29.--31. "SWIZ_CHAN3,Swizzle for destination channel 3" "0,1,2,3,4,5,6,7" newline bitfld.long 0x18 26.--28. "SWIZ_CHAN2,Swizzle for destination channel 2" "0,1,2,3,4,5,6,7" newline bitfld.long 0x18 23.--25. "SWIZ_CHAN1,Swizzle for destination channel 1" "0,1,2,3,4,5,6,7" newline bitfld.long 0x18 20.--22. "SWIZ_CHAN0,Swizzle for destination channel 0" "0,1,2,3,4,5,6,7" newline hexmask.long.word 0x18 6.--19. 1. "MINCLIP_X,Min X Clip" newline bitfld.long 0x18 5. "TWOCOMP_GAMMA,Sets the gamma mode for 2 component targets" "0,1" newline bitfld.long 0x18 4. "GAMMA,Gamma enabled" "0,1" newline bitfld.long 0x18 3. "COMPRESSION,Frame buffer Compression enabled" "0,1" newline bitfld.long 0x18 2. "COMPRESS_SIZE,Block size for the compressor used with COMPRESS_SIZE_EXT register bit to define 8x8; 16x4 or 32x2 size COMPRESS_SIZE_EXT COMPRESS_SIZE SIZE 0 0 8x8 0 1 16x4 1 0 32x2 1 1 reserved" "0,1" newline bitfld.long 0x18 1. "COMP_INDIRECT_TABLE,If set indicates to the compressor that an indirect addressing is used otherwise direct addressing" "0,1" newline bitfld.long 0x18 0. "Y_FLIP,Y_FLIP" "0,1" line.long 0x1C "RGX_CR_PBE_WORD0_MRT3_1,Pixel Back end State Word 0." bitfld.long 0x1C 30.--31. "X_RSRVD,Not used" "0,1,2,3" newline bitfld.long 0x1C 29. "COMPRESS_SIZE_EXT,Extra bit to support 32x2 compression size used with COMPRESS_SIZE register bit to define 8x8; 16x4 or 32x2 size COMPRESS_SIZE_EXT COMPRESS_SIZE SIZE 0 0 8x8 0 1 16x4 1 0 32x2 1 1 reserved" "0,1" newline bitfld.long 0x1C 28. "COMP_IADDR_MODE,FBC indirect addressing mode" "0,1" newline bitfld.long 0x1C 27. "COMP_COR_ENABLE,Enable FBC correlation" "0,1" newline bitfld.long 0x1C 26. "DITHER,Enable dither" "0,1" newline bitfld.long 0x1C 25. "TILERELATIVE,Add tile offset" "0,1" newline bitfld.long 0x1C 24. "DOWNSCALE,Perform box filter downscale" "0,1" newline hexmask.long.byte 0x1C 20.--23. 1. "SIZE_Z,Z Size in pixels [log 2]" newline bitfld.long 0x1C 18.--19. "ROTATION,Rotation angle" "0,1,2,3" newline hexmask.long.word 0x1C 2.--17. 1. "LINESTRIDE,Linestride in 2 pixel units. 0 == 2. Supports 32KDWORD stride memory write" newline bitfld.long 0x1C 0.--1. "MEMLAYOUT,Memory layout" "0,1,2,3" line.long 0x20 "RGX_CR_PBE_WORD0_MRT4_0,Pixel Back end State Word 0." bitfld.long 0x20 29.--31. "SWIZ_CHAN3,Swizzle for destination channel 3" "0,1,2,3,4,5,6,7" newline bitfld.long 0x20 26.--28. "SWIZ_CHAN2,Swizzle for destination channel 2" "0,1,2,3,4,5,6,7" newline bitfld.long 0x20 23.--25. "SWIZ_CHAN1,Swizzle for destination channel 1" "0,1,2,3,4,5,6,7" newline bitfld.long 0x20 20.--22. "SWIZ_CHAN0,Swizzle for destination channel 0" "0,1,2,3,4,5,6,7" newline hexmask.long.word 0x20 6.--19. 1. "MINCLIP_X,Min X Clip" newline bitfld.long 0x20 5. "TWOCOMP_GAMMA,Sets the gamma mode for 2 component targets" "0,1" newline bitfld.long 0x20 4. "GAMMA,Gamma enabled" "0,1" newline bitfld.long 0x20 3. "COMPRESSION,Frame buffer Compression enabled" "0,1" newline bitfld.long 0x20 2. "COMPRESS_SIZE,Block size for the compressor used with COMPRESS_SIZE_EXT register bit to define 8x8; 16x4 or 32x2 size COMPRESS_SIZE_EXT COMPRESS_SIZE SIZE 0 0 8x8 0 1 16x4 1 0 32x2 1 1 reserved" "0,1" newline bitfld.long 0x20 1. "COMP_INDIRECT_TABLE,If set indicates to the compressor that an indirect addressing is used otherwise direct addressing" "0,1" newline bitfld.long 0x20 0. "Y_FLIP,Y_FLIP" "0,1" line.long 0x24 "RGX_CR_PBE_WORD0_MRT4_1,Pixel Back end State Word 0." bitfld.long 0x24 30.--31. "X_RSRVD,Not used" "0,1,2,3" newline bitfld.long 0x24 29. "COMPRESS_SIZE_EXT,Extra bit to support 32x2 compression size used with COMPRESS_SIZE register bit to define 8x8; 16x4 or 32x2 size COMPRESS_SIZE_EXT COMPRESS_SIZE SIZE 0 0 8x8 0 1 16x4 1 0 32x2 1 1 reserved" "0,1" newline bitfld.long 0x24 28. "COMP_IADDR_MODE,FBC indirect addressing mode" "0,1" newline bitfld.long 0x24 27. "COMP_COR_ENABLE,Enable FBC correlation" "0,1" newline bitfld.long 0x24 26. "DITHER,Enable dither" "0,1" newline bitfld.long 0x24 25. "TILERELATIVE,Add tile offset" "0,1" newline bitfld.long 0x24 24. "DOWNSCALE,Perform box filter downscale" "0,1" newline hexmask.long.byte 0x24 20.--23. 1. "SIZE_Z,Z Size in pixels [log 2]" newline bitfld.long 0x24 18.--19. "ROTATION,Rotation angle" "0,1,2,3" newline hexmask.long.word 0x24 2.--17. 1. "LINESTRIDE,Linestride in 2 pixel units. 0 == 2. Supports 32KDWORD stride memory write" newline bitfld.long 0x24 0.--1. "MEMLAYOUT,Memory layout" "0,1,2,3" line.long 0x28 "RGX_CR_PBE_WORD0_MRT5_0,Pixel Back end State Word 0." bitfld.long 0x28 29.--31. "SWIZ_CHAN3,Swizzle for destination channel 3" "0,1,2,3,4,5,6,7" newline bitfld.long 0x28 26.--28. "SWIZ_CHAN2,Swizzle for destination channel 2" "0,1,2,3,4,5,6,7" newline bitfld.long 0x28 23.--25. "SWIZ_CHAN1,Swizzle for destination channel 1" "0,1,2,3,4,5,6,7" newline bitfld.long 0x28 20.--22. "SWIZ_CHAN0,Swizzle for destination channel 0" "0,1,2,3,4,5,6,7" newline hexmask.long.word 0x28 6.--19. 1. "MINCLIP_X,Min X Clip" newline bitfld.long 0x28 5. "TWOCOMP_GAMMA,Sets the gamma mode for 2 component targets" "0,1" newline bitfld.long 0x28 4. "GAMMA,Gamma enabled" "0,1" newline bitfld.long 0x28 3. "COMPRESSION,Frame buffer Compression enabled" "0,1" newline bitfld.long 0x28 2. "COMPRESS_SIZE,Block size for the compressor used with COMPRESS_SIZE_EXT register bit to define 8x8; 16x4 or 32x2 size COMPRESS_SIZE_EXT COMPRESS_SIZE SIZE 0 0 8x8 0 1 16x4 1 0 32x2 1 1 reserved" "0,1" newline bitfld.long 0x28 1. "COMP_INDIRECT_TABLE,If set indicates to the compressor that an indirect addressing is used otherwise direct addressing" "0,1" newline bitfld.long 0x28 0. "Y_FLIP,Y_FLIP" "0,1" line.long 0x2C "RGX_CR_PBE_WORD0_MRT5_1,Pixel Back end State Word 0." bitfld.long 0x2C 30.--31. "X_RSRVD,Not used" "0,1,2,3" newline bitfld.long 0x2C 29. "COMPRESS_SIZE_EXT,Extra bit to support 32x2 compression size used with COMPRESS_SIZE register bit to define 8x8; 16x4 or 32x2 size COMPRESS_SIZE_EXT COMPRESS_SIZE SIZE 0 0 8x8 0 1 16x4 1 0 32x2 1 1 reserved" "0,1" newline bitfld.long 0x2C 28. "COMP_IADDR_MODE,FBC indirect addressing mode" "0,1" newline bitfld.long 0x2C 27. "COMP_COR_ENABLE,Enable FBC correlation" "0,1" newline bitfld.long 0x2C 26. "DITHER,Enable dither" "0,1" newline bitfld.long 0x2C 25. "TILERELATIVE,Add tile offset" "0,1" newline bitfld.long 0x2C 24. "DOWNSCALE,Perform box filter downscale" "0,1" newline hexmask.long.byte 0x2C 20.--23. 1. "SIZE_Z,Z Size in pixels [log 2]" newline bitfld.long 0x2C 18.--19. "ROTATION,Rotation angle" "0,1,2,3" newline hexmask.long.word 0x2C 2.--17. 1. "LINESTRIDE,Linestride in 2 pixel units. 0 == 2. Supports 32KDWORD stride memory write" newline bitfld.long 0x2C 0.--1. "MEMLAYOUT,Memory layout" "0,1,2,3" line.long 0x30 "RGX_CR_PBE_WORD0_MRT6_0,Pixel Back end State Word 0." bitfld.long 0x30 29.--31. "SWIZ_CHAN3,Swizzle for destination channel 3" "0,1,2,3,4,5,6,7" newline bitfld.long 0x30 26.--28. "SWIZ_CHAN2,Swizzle for destination channel 2" "0,1,2,3,4,5,6,7" newline bitfld.long 0x30 23.--25. "SWIZ_CHAN1,Swizzle for destination channel 1" "0,1,2,3,4,5,6,7" newline bitfld.long 0x30 20.--22. "SWIZ_CHAN0,Swizzle for destination channel 0" "0,1,2,3,4,5,6,7" newline hexmask.long.word 0x30 6.--19. 1. "MINCLIP_X,Min X Clip" newline bitfld.long 0x30 5. "TWOCOMP_GAMMA,Sets the gamma mode for 2 component targets" "0,1" newline bitfld.long 0x30 4. "GAMMA,Gamma enabled" "0,1" newline bitfld.long 0x30 3. "COMPRESSION,Frame buffer Compression enabled" "0,1" newline bitfld.long 0x30 2. "COMPRESS_SIZE,Block size for the compressor used with COMPRESS_SIZE_EXT register bit to define 8x8; 16x4 or 32x2 size COMPRESS_SIZE_EXT COMPRESS_SIZE SIZE 0 0 8x8 0 1 16x4 1 0 32x2 1 1 reserved" "0,1" newline bitfld.long 0x30 1. "COMP_INDIRECT_TABLE,If set indicates to the compressor that an indirect addressing is used otherwise direct addressing" "0,1" newline bitfld.long 0x30 0. "Y_FLIP,Y_FLIP" "0,1" line.long 0x34 "RGX_CR_PBE_WORD0_MRT6_1,Pixel Back end State Word 0." bitfld.long 0x34 30.--31. "X_RSRVD,Not used" "0,1,2,3" newline bitfld.long 0x34 29. "COMPRESS_SIZE_EXT,Extra bit to support 32x2 compression size used with COMPRESS_SIZE register bit to define 8x8; 16x4 or 32x2 size COMPRESS_SIZE_EXT COMPRESS_SIZE SIZE 0 0 8x8 0 1 16x4 1 0 32x2 1 1 reserved" "0,1" newline bitfld.long 0x34 28. "COMP_IADDR_MODE,FBC indirect addressing mode" "0,1" newline bitfld.long 0x34 27. "COMP_COR_ENABLE,Enable FBC correlation" "0,1" newline bitfld.long 0x34 26. "DITHER,Enable dither" "0,1" newline bitfld.long 0x34 25. "TILERELATIVE,Add tile offset" "0,1" newline bitfld.long 0x34 24. "DOWNSCALE,Perform box filter downscale" "0,1" newline hexmask.long.byte 0x34 20.--23. 1. "SIZE_Z,Z Size in pixels [log 2]" newline bitfld.long 0x34 18.--19. "ROTATION,Rotation angle" "0,1,2,3" newline hexmask.long.word 0x34 2.--17. 1. "LINESTRIDE,Linestride in 2 pixel units. 0 == 2. Supports 32KDWORD stride memory write" newline bitfld.long 0x34 0.--1. "MEMLAYOUT,Memory layout" "0,1,2,3" line.long 0x38 "RGX_CR_PBE_WORD0_MRT7_0,Pixel Back end State Word 0." bitfld.long 0x38 29.--31. "SWIZ_CHAN3,Swizzle for destination channel 3" "0,1,2,3,4,5,6,7" newline bitfld.long 0x38 26.--28. "SWIZ_CHAN2,Swizzle for destination channel 2" "0,1,2,3,4,5,6,7" newline bitfld.long 0x38 23.--25. "SWIZ_CHAN1,Swizzle for destination channel 1" "0,1,2,3,4,5,6,7" newline bitfld.long 0x38 20.--22. "SWIZ_CHAN0,Swizzle for destination channel 0" "0,1,2,3,4,5,6,7" newline hexmask.long.word 0x38 6.--19. 1. "MINCLIP_X,Min X Clip" newline bitfld.long 0x38 5. "TWOCOMP_GAMMA,Sets the gamma mode for 2 component targets" "0,1" newline bitfld.long 0x38 4. "GAMMA,Gamma enabled" "0,1" newline bitfld.long 0x38 3. "COMPRESSION,Frame buffer Compression enabled" "0,1" newline bitfld.long 0x38 2. "COMPRESS_SIZE,Block size for the compressor used with COMPRESS_SIZE_EXT register bit to define 8x8; 16x4 or 32x2 size COMPRESS_SIZE_EXT COMPRESS_SIZE SIZE 0 0 8x8 0 1 16x4 1 0 32x2 1 1 reserved" "0,1" newline bitfld.long 0x38 1. "COMP_INDIRECT_TABLE,If set indicates to the compressor that an indirect addressing is used otherwise direct addressing" "0,1" newline bitfld.long 0x38 0. "Y_FLIP,Y_FLIP" "0,1" line.long 0x3C "RGX_CR_PBE_WORD0_MRT7_1,Pixel Back end State Word 0." bitfld.long 0x3C 30.--31. "X_RSRVD,Not used" "0,1,2,3" newline bitfld.long 0x3C 29. "COMPRESS_SIZE_EXT,Extra bit to support 32x2 compression size used with COMPRESS_SIZE register bit to define 8x8; 16x4 or 32x2 size COMPRESS_SIZE_EXT COMPRESS_SIZE SIZE 0 0 8x8 0 1 16x4 1 0 32x2 1 1 reserved" "0,1" newline bitfld.long 0x3C 28. "COMP_IADDR_MODE,FBC indirect addressing mode" "0,1" newline bitfld.long 0x3C 27. "COMP_COR_ENABLE,Enable FBC correlation" "0,1" newline bitfld.long 0x3C 26. "DITHER,Enable dither" "0,1" newline bitfld.long 0x3C 25. "TILERELATIVE,Add tile offset" "0,1" newline bitfld.long 0x3C 24. "DOWNSCALE,Perform box filter downscale" "0,1" newline hexmask.long.byte 0x3C 20.--23. 1. "SIZE_Z,Z Size in pixels [log 2]" newline bitfld.long 0x3C 18.--19. "ROTATION,Rotation angle" "0,1,2,3" newline hexmask.long.word 0x3C 2.--17. 1. "LINESTRIDE,Linestride in 2 pixel units. 0 == 2. Supports 32KDWORD stride memory write" newline bitfld.long 0x3C 0.--1. "MEMLAYOUT,Memory layout" "0,1,2,3" repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) group.long ($2+0x1550)++0x3 line.long 0x0 "RGX_CR_PBE_WORD1_MRT0_$1,Pixel Back end State Word 1." hexmask.long.byte 0x0 28.--31. 1. "SIZE_Y,Y Size in pixels [log 2]" newline hexmask.long.word 0x0 14.--27. 1. "ZSLICE,Slice number for render to 3D twiddle target" newline hexmask.long.word 0x0 0.--13. 1. "MAXCLIP_Y,Max Y clip" repeat.end repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) group.long ($2+0x1558)++0x3 line.long 0x0 "RGX_CR_PBE_WORD1_MRT1_$1,Pixel Back end State Word 1." hexmask.long.byte 0x0 28.--31. 1. "SIZE_Y,Y Size in pixels [log 2]" newline hexmask.long.word 0x0 14.--27. 1. "ZSLICE,Slice number for render to 3D twiddle target" newline hexmask.long.word 0x0 0.--13. 1. "MAXCLIP_Y,Max Y clip" repeat.end repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) group.long ($2+0x1560)++0x3 line.long 0x0 "RGX_CR_PBE_WORD1_MRT2_$1,Pixel Back end State Word 1." hexmask.long.byte 0x0 28.--31. 1. "SIZE_Y,Y Size in pixels [log 2]" newline hexmask.long.word 0x0 14.--27. 1. "ZSLICE,Slice number for render to 3D twiddle target" newline hexmask.long.word 0x0 0.--13. 1. "MAXCLIP_Y,Max Y clip" repeat.end repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) group.long ($2+0x1568)++0x3 line.long 0x0 "RGX_CR_PBE_WORD1_MRT3_$1,Pixel Back end State Word 1." hexmask.long.byte 0x0 28.--31. 1. "SIZE_Y,Y Size in pixels [log 2]" newline hexmask.long.word 0x0 14.--27. 1. "ZSLICE,Slice number for render to 3D twiddle target" newline hexmask.long.word 0x0 0.--13. 1. "MAXCLIP_Y,Max Y clip" repeat.end repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) group.long ($2+0x1570)++0x3 line.long 0x0 "RGX_CR_PBE_WORD1_MRT4_$1,Pixel Back end State Word 1." hexmask.long.byte 0x0 28.--31. 1. "SIZE_Y,Y Size in pixels [log 2]" newline hexmask.long.word 0x0 14.--27. 1. "ZSLICE,Slice number for render to 3D twiddle target" newline hexmask.long.word 0x0 0.--13. 1. "MAXCLIP_Y,Max Y clip" repeat.end repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) group.long ($2+0x1578)++0x3 line.long 0x0 "RGX_CR_PBE_WORD1_MRT5_$1,Pixel Back end State Word 1." hexmask.long.byte 0x0 28.--31. 1. "SIZE_Y,Y Size in pixels [log 2]" newline hexmask.long.word 0x0 14.--27. 1. "ZSLICE,Slice number for render to 3D twiddle target" newline hexmask.long.word 0x0 0.--13. 1. "MAXCLIP_Y,Max Y clip" repeat.end repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) group.long ($2+0x1580)++0x3 line.long 0x0 "RGX_CR_PBE_WORD1_MRT6_$1,Pixel Back end State Word 1." hexmask.long.byte 0x0 28.--31. 1. "SIZE_Y,Y Size in pixels [log 2]" newline hexmask.long.word 0x0 14.--27. 1. "ZSLICE,Slice number for render to 3D twiddle target" newline hexmask.long.word 0x0 0.--13. 1. "MAXCLIP_Y,Max Y clip" repeat.end repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) group.long ($2+0x1588)++0x3 line.long 0x0 "RGX_CR_PBE_WORD1_MRT7_$1,Pixel Back end State Word 1." hexmask.long.byte 0x0 28.--31. 1. "SIZE_Y,Y Size in pixels [log 2]" newline hexmask.long.word 0x0 14.--27. 1. "ZSLICE,Slice number for render to 3D twiddle target" newline hexmask.long.word 0x0 0.--13. 1. "MAXCLIP_Y,Max Y clip" repeat.end repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) rgroup.long ($2+0x1590)++0x3 line.long 0x0 "RGX_CR_PBE_PWR_$1,Power monitoring register" hexmask.long 0x0 0.--31. 1. "NUM_PIXELS_PROCESSED,Number of on-edge/off-edge pixels per tile." repeat.end group.long 0x15A0++0x3F line.long 0x0 "RGX_CR_PBE_WORD2_MRT0_0,Pixel Back end State Word 2." hexmask.long 0x0 0.--31. 1. "SW_BYTEMASK,SW driven mask" line.long 0x4 "RGX_CR_PBE_WORD2_MRT0_1,Pixel Back end State Word 2." hexmask.long.tbyte 0x4 15.--31. 1. "Reserved_47,Reserved_47" newline bitfld.long 0x4 14. "PAIR_TILES,If set then PBE will pair 16x16 tiles" "0,1" newline hexmask.long.word 0x4 0.--13. 1. "SURFACE_Y_SIZE,Y Size in pixels (only used for strided memory layout with FBC)" line.long 0x8 "RGX_CR_PBE_WORD2_MRT1_0,Pixel Back end State Word 2." hexmask.long 0x8 0.--31. 1. "SW_BYTEMASK,SW driven mask" line.long 0xC "RGX_CR_PBE_WORD2_MRT1_1,Pixel Back end State Word 2." hexmask.long.tbyte 0xC 15.--31. 1. "Reserved_47,Reserved_47" newline bitfld.long 0xC 14. "PAIR_TILES,If set then PBE will pair 16x16 tiles" "0,1" newline hexmask.long.word 0xC 0.--13. 1. "SURFACE_Y_SIZE,Y Size in pixels (only used for strided memory layout with FBC)" line.long 0x10 "RGX_CR_PBE_WORD2_MRT2_0,Pixel Back end State Word 2." hexmask.long 0x10 0.--31. 1. "SW_BYTEMASK,SW driven mask" line.long 0x14 "RGX_CR_PBE_WORD2_MRT2_1,Pixel Back end State Word 2." hexmask.long.tbyte 0x14 15.--31. 1. "Reserved_47,Reserved_47" newline bitfld.long 0x14 14. "PAIR_TILES,If set then PBE will pair 16x16 tiles" "0,1" newline hexmask.long.word 0x14 0.--13. 1. "SURFACE_Y_SIZE,Y Size in pixels (only used for strided memory layout with FBC)" line.long 0x18 "RGX_CR_PBE_WORD2_MRT3_0,Pixel Back end State Word 2." hexmask.long 0x18 0.--31. 1. "SW_BYTEMASK,SW driven mask" line.long 0x1C "RGX_CR_PBE_WORD2_MRT3_1,Pixel Back end State Word 2." hexmask.long.tbyte 0x1C 15.--31. 1. "Reserved_47,Reserved_47" newline bitfld.long 0x1C 14. "PAIR_TILES,If set then PBE will pair 16x16 tiles" "0,1" newline hexmask.long.word 0x1C 0.--13. 1. "SURFACE_Y_SIZE,Y Size in pixels (only used for strided memory layout with FBC)" line.long 0x20 "RGX_CR_PBE_WORD2_MRT4_0,Pixel Back end State Word 2." hexmask.long 0x20 0.--31. 1. "SW_BYTEMASK,SW driven mask" line.long 0x24 "RGX_CR_PBE_WORD2_MRT4_1,Pixel Back end State Word 2." hexmask.long.tbyte 0x24 15.--31. 1. "Reserved_47,Reserved_47" newline bitfld.long 0x24 14. "PAIR_TILES,If set then PBE will pair 16x16 tiles" "0,1" newline hexmask.long.word 0x24 0.--13. 1. "SURFACE_Y_SIZE,Y Size in pixels (only used for strided memory layout with FBC)" line.long 0x28 "RGX_CR_PBE_WORD2_MRT5_0,Pixel Back end State Word 2." hexmask.long 0x28 0.--31. 1. "SW_BYTEMASK,SW driven mask" line.long 0x2C "RGX_CR_PBE_WORD2_MRT5_1,Pixel Back end State Word 2." hexmask.long.tbyte 0x2C 15.--31. 1. "Reserved_47,Reserved_47" newline bitfld.long 0x2C 14. "PAIR_TILES,If set then PBE will pair 16x16 tiles" "0,1" newline hexmask.long.word 0x2C 0.--13. 1. "SURFACE_Y_SIZE,Y Size in pixels (only used for strided memory layout with FBC)" line.long 0x30 "RGX_CR_PBE_WORD2_MRT6_0,Pixel Back end State Word 2." hexmask.long 0x30 0.--31. 1. "SW_BYTEMASK,SW driven mask" line.long 0x34 "RGX_CR_PBE_WORD2_MRT6_1,Pixel Back end State Word 2." hexmask.long.tbyte 0x34 15.--31. 1. "Reserved_47,Reserved_47" newline bitfld.long 0x34 14. "PAIR_TILES,If set then PBE will pair 16x16 tiles" "0,1" newline hexmask.long.word 0x34 0.--13. 1. "SURFACE_Y_SIZE,Y Size in pixels (only used for strided memory layout with FBC)" line.long 0x38 "RGX_CR_PBE_WORD2_MRT7_0,Pixel Back end State Word 2." hexmask.long 0x38 0.--31. 1. "SW_BYTEMASK,SW driven mask" line.long 0x3C "RGX_CR_PBE_WORD2_MRT7_1,Pixel Back end State Word 2." hexmask.long.tbyte 0x3C 15.--31. 1. "Reserved_47,Reserved_47" newline bitfld.long 0x3C 14. "PAIR_TILES,If set then PBE will pair 16x16 tiles" "0,1" newline hexmask.long.word 0x3C 0.--13. 1. "SURFACE_Y_SIZE,Y Size in pixels (only used for strided memory layout with FBC)" group.long 0x1600++0x11F line.long 0x0 "RGX_CR_FB_CDC_0,Framebuffer Compression/Decompression arbiter modes" bitfld.long 0x0 30.--31. "FBDC_MCU_SLC_HDR_POLICY,SLC Cache policy for MCU requested FBDC header requests" "0,1,2,3" newline bitfld.long 0x0 28.--29. "FBDC_MCU_SLC_DATA_POLICY,SLC Cache policy for MCU requested FBDC tile data requests" "0,1,2,3" newline hexmask.long.word 0x0 12.--27. 1. "FBC_FBDC_COMPATIBILITY,The register defines the mode of operation to ensure that the GPU FBC/FBDC is compatible with any FBC/FBDC existing in the SoC (standalone FBC/FBDC). To be compatible the register needs to be programed with the version of the SoC.." newline bitfld.long 0x0 11. "FBC_FBDC_INVAL_OVERRIDE,When set then all FBDC header cache entries will be invalidate from the FBC otherwise only those associated with the request being processed by the FBC will be invalidated" "0,1" newline bitfld.long 0x0 10. "ZLS_SLC_NOLINEFILL,ZLS write SLC no line fill: 0=line fill on miss 1=no line fill on miss" "line fill on miss,no line fill on miss" newline bitfld.long 0x0 8.--9. "ZLS_SLC_POLICY,ZLS write SLC cache Policy" "0,1,2,3" newline bitfld.long 0x0 7. "PBE_SLC_NOLINEFILL,PBE write SLC no line fill: 0=line fill on miss 1=no line fill on miss" "line fill on miss,no line fill on miss" newline bitfld.long 0x0 5.--6. "PBE_SLC_POLICY,PBE write SLC cache Policy" "0,1,2,3" newline bitfld.long 0x0 4. "PBE_COR_COLOUR_ENABLE,PBE Enable correlation/decorrelation for PBE 0=disbaled 1=enabled" "disbaled,enabled" newline bitfld.long 0x0 3. "FBC_ARB_MODE,FBC Request Arbiter Mode 0 = Re-arbitrate after tile 1 = Re-arbitrate after valid drop and tile complete" "Re-arbitrate after tile,Re-arbitrate after valid drop and tile complete" newline bitfld.long 0x0 2. "Reserved_2,Reserved_2" "0,1" newline bitfld.long 0x0 1. "TLDECODE_ARB_MODE,TLCache Request Arbiter Mode Rearbitration:0 = valid dropped and burst complete 1 = After burst complete" "valid dropped and burst complete,After burst complete" newline bitfld.long 0x0 0. "BIF_ARB_MODE,FBC and FBDC BIF Arbiter Mode 0 = Re-arbitrate after burst 1 = Re-arbitrate after valid drop and burst complete" "Re-arbitrate after burst,Re-arbitrate after valid drop and burst complete" line.long 0x4 "RGX_CR_FB_CDC_1,Framebuffer Compression/Decompression arbiter modes" hexmask.long.tbyte 0x4 13.--31. 1. "Reserved_45,Reserved_45" newline bitfld.long 0x4 12. "FBCDC_COR_ENABLE,writing '0' the compression correlation/decorrelation is disable" "0,1" newline hexmask.long.byte 0x4 4.--11. 1. "Reserved_36,Reserved_36" newline bitfld.long 0x4 2.--3. "FBDC_ZLS_SLC_HDR_POLICY,SLC Cache policy for ZLS requested FBDC header requests" "0,1,2,3" newline bitfld.long 0x4 0.--1. "FBDC_ZLS_SLC_DATA_POLICY,SLC Cache policy for ZLS requested FBDC tile data requests" "0,1,2,3" line.long 0x8 "RGX_CR_FB_ICTRL_0,Framebuffer Invalidates" hexmask.long.word 0x8 23.--31. 1. "Reserved_23,Reserved_23" newline bitfld.long 0x8 22. "TLCACHE_INVALFLUSH_FASTRENDER_DM,When set to 1 all entries in the tile cache that have been tagged as a fastrender data master will be invalidate/flush when TLCACHE_INVALFLUSH_PENDING is set" "0,1" newline bitfld.long 0x8 19.--21. "Reserved_19,Reserved_19" "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x8 15.--18. 1. "FBDC_INVALIDATE_REQUESTER,Bit mask of requester to invalidate when FBDC_INVALIDATE_PENDING is set" newline bitfld.long 0x8 14. "TLCACHE_INVALFLUSH_TOMEM,When set to 1 all flushes will result in a flush fence being sent to memory after the tiles have been flushed. On return of this fence the TLCACHE_INVALFLUSH_PENDING will be cleared. When not set a flush fence is not sent and.." "0,1" newline hexmask.long.byte 0x8 10.--13. 1. "TLCACHE_INVALFLUSH_REQUESTER,Bit mask of requester to flush or invalidate when TLCACHE_INVALFUSH_PENDING is set These are also used in combination with the invalflush__DM mask bits" newline bitfld.long 0x8 8.--9. "Reserved_8,Reserved_8" "0,1,2,3" newline bitfld.long 0x8 7. "TLCACHE_INVALFLUSH_COMP_DM,When set to 1 all entries in the tile cache that have been tagged as a compute data master will be invalidate/flush when TLCACHE_INVALFLUSH_PENDING is set" "0,1" newline bitfld.long 0x8 6. "TLCACHE_INVALFLUSH_VERTEX_DM,When set to 1 all entries in the tile cache that have been tagged as a vertex data master will be invalidate/flush when TLCACHE_INVALFLUSH_PENDING is set" "0,1" newline bitfld.long 0x8 5. "TLCACHE_INVALFLUSH_PIXEL_DM,When set to 1 all entries in the tile cache that have been tagged as a pixel data master will be invalidate/flush when TLCACHE_INVALFLUSH_PENDING is set" "0,1" newline bitfld.long 0x8 3.--4. "TLCACHE_INVALFLUSH_PENDING,The cache may be requested to flush or invalidate or both in a single write access. Each bit when read returns the current status of the flush or invalidate request. Bit 0 = Invalidate Bit 1 = Flush If either bit is read back.." "Invalidate,Flush,?,?" newline bitfld.long 0x8 1.--2. "Reserved_1,Reserved_1" "0,1,2,3" newline bitfld.long 0x8 0. "FBDC_INVALIDATE_PENDING,When written to 1 will invalidate the header cache in the FBDC when read as 1 invalidate is in progress when read as 0 invalidate is complete" "0,1" line.long 0xC "RGX_CR_FB_ICTRL_1,Framebuffer Invalidates" hexmask.long 0xC 0.--31. 1. "Reserved_23,Reserved_23" line.long 0x10 "RGX_CR_FB_MEM_REGION0_0,Framebuffer Compression/Decompression memory regions for Host and TLA accesses" hexmask.long 0x10 0.--31. 1. "BASE_ADDRESS,Base address of this memory region in 512bit granularity" line.long 0x14 "RGX_CR_FB_MEM_REGION0_1,Framebuffer Compression/Decompression memory regions for Host and TLA accesses" hexmask.long.byte 0x14 25.--31. 1. "Reserved_57,Reserved_57" newline hexmask.long.tbyte 0x14 2.--24. 1. "NUM_TILES,The number of compressor tiles to be used in this memory region" newline bitfld.long 0x14 0.--1. "BASE_ADDRESS,Base address of this memory region in 512bit granularity" "0,1,2,3" line.long 0x18 "RGX_CR_FB_MEM_REGION1_0,Framebuffer Compression/Decompression memory regions for Host and TLA accesses" hexmask.long 0x18 0.--31. 1. "BASE_ADDRESS,Base address of this memory region in 512bit granularity" line.long 0x1C "RGX_CR_FB_MEM_REGION1_1,Framebuffer Compression/Decompression memory regions for Host and TLA accesses" hexmask.long.byte 0x1C 25.--31. 1. "Reserved_57,Reserved_57" newline hexmask.long.tbyte 0x1C 2.--24. 1. "NUM_TILES,The number of compressor tiles to be used in this memory region" newline bitfld.long 0x1C 0.--1. "BASE_ADDRESS,Base address of this memory region in 512bit granularity" "0,1,2,3" line.long 0x20 "RGX_CR_FB_MEM_REGION2_0,Framebuffer Compression/Decompression memory regions for Host and TLA accesses" hexmask.long 0x20 0.--31. 1. "BASE_ADDRESS,Base address of this memory region in 512bit granularity" line.long 0x24 "RGX_CR_FB_MEM_REGION2_1,Framebuffer Compression/Decompression memory regions for Host and TLA accesses" hexmask.long.byte 0x24 25.--31. 1. "Reserved_57,Reserved_57" newline hexmask.long.tbyte 0x24 2.--24. 1. "NUM_TILES,The number of compressor tiles to be used in this memory region" newline bitfld.long 0x24 0.--1. "BASE_ADDRESS,Base address of this memory region in 512bit granularity" "0,1,2,3" line.long 0x28 "RGX_CR_FB_MEM_REGION3_0,Framebuffer Compression/Decompression memory regions for Host and TLA accesses" hexmask.long 0x28 0.--31. 1. "BASE_ADDRESS,Base address of this memory region in 512bit granularity" line.long 0x2C "RGX_CR_FB_MEM_REGION3_1,Framebuffer Compression/Decompression memory regions for Host and TLA accesses" hexmask.long.byte 0x2C 25.--31. 1. "Reserved_57,Reserved_57" newline hexmask.long.tbyte 0x2C 2.--24. 1. "NUM_TILES,The number of compressor tiles to be used in this memory region" newline bitfld.long 0x2C 0.--1. "BASE_ADDRESS,Base address of this memory region in 512bit granularity" "0,1,2,3" line.long 0x30 "RGX_CR_FB_MEM_REGION4_0,Framebuffer Compression/Decompression memory regions for Host and TLA accesses" hexmask.long 0x30 0.--31. 1. "BASE_ADDRESS,Base address of this memory region in 512bit granularity" line.long 0x34 "RGX_CR_FB_MEM_REGION4_1,Framebuffer Compression/Decompression memory regions for Host and TLA accesses" hexmask.long.byte 0x34 25.--31. 1. "Reserved_57,Reserved_57" newline hexmask.long.tbyte 0x34 2.--24. 1. "NUM_TILES,The number of compressor tiles to be used in this memory region" newline bitfld.long 0x34 0.--1. "BASE_ADDRESS,Base address of this memory region in 512bit granularity" "0,1,2,3" line.long 0x38 "RGX_CR_FB_MEM_REGION5_0,Framebuffer Compression/Decompression memory regions for Host and TLA accesses" hexmask.long 0x38 0.--31. 1. "BASE_ADDRESS,Base address of this memory region in 512bit granularity" line.long 0x3C "RGX_CR_FB_MEM_REGION5_1,Framebuffer Compression/Decompression memory regions for Host and TLA accesses" hexmask.long.byte 0x3C 25.--31. 1. "Reserved_57,Reserved_57" newline hexmask.long.tbyte 0x3C 2.--24. 1. "NUM_TILES,The number of compressor tiles to be used in this memory region" newline bitfld.long 0x3C 0.--1. "BASE_ADDRESS,Base address of this memory region in 512bit granularity" "0,1,2,3" line.long 0x40 "RGX_CR_FB_MEM_REGION6_0,Framebuffer Compression/Decompression memory regions for Host and TLA accesses" hexmask.long 0x40 0.--31. 1. "BASE_ADDRESS,Base address of this memory region in 512bit granularity" line.long 0x44 "RGX_CR_FB_MEM_REGION6_1,Framebuffer Compression/Decompression memory regions for Host and TLA accesses" hexmask.long.byte 0x44 25.--31. 1. "Reserved_57,Reserved_57" newline hexmask.long.tbyte 0x44 2.--24. 1. "NUM_TILES,The number of compressor tiles to be used in this memory region" newline bitfld.long 0x44 0.--1. "BASE_ADDRESS,Base address of this memory region in 512bit granularity" "0,1,2,3" line.long 0x48 "RGX_CR_FB_MEM_REGION7_0,Framebuffer Compression/Decompression memory regions for Host and TLA accesses" hexmask.long 0x48 0.--31. 1. "BASE_ADDRESS,Base address of this memory region in 512bit granularity" line.long 0x4C "RGX_CR_FB_MEM_REGION7_1,Framebuffer Compression/Decompression memory regions for Host and TLA accesses" hexmask.long.byte 0x4C 25.--31. 1. "Reserved_57,Reserved_57" newline hexmask.long.tbyte 0x4C 2.--24. 1. "NUM_TILES,The number of compressor tiles to be used in this memory region" newline bitfld.long 0x4C 0.--1. "BASE_ADDRESS,Base address of this memory region in 512bit granularity" "0,1,2,3" line.long 0x50 "RGX_CR_FB_MEM_REGION8_0,Framebuffer Compression/Decompression memory regions for Host and TLA accesses" hexmask.long 0x50 0.--31. 1. "BASE_ADDRESS,Base address of this memory region in 512bit granularity" line.long 0x54 "RGX_CR_FB_MEM_REGION8_1,Framebuffer Compression/Decompression memory regions for Host and TLA accesses" hexmask.long.byte 0x54 25.--31. 1. "Reserved_57,Reserved_57" newline hexmask.long.tbyte 0x54 2.--24. 1. "NUM_TILES,The number of compressor tiles to be used in this memory region" newline bitfld.long 0x54 0.--1. "BASE_ADDRESS,Base address of this memory region in 512bit granularity" "0,1,2,3" line.long 0x58 "RGX_CR_FB_MEM_REGION9_0,Framebuffer Compression/Decompression memory regions for Host and TLA accesses" hexmask.long 0x58 0.--31. 1. "BASE_ADDRESS,Base address of this memory region in 512bit granularity" line.long 0x5C "RGX_CR_FB_MEM_REGION9_1,Framebuffer Compression/Decompression memory regions for Host and TLA accesses" hexmask.long.byte 0x5C 25.--31. 1. "Reserved_57,Reserved_57" newline hexmask.long.tbyte 0x5C 2.--24. 1. "NUM_TILES,The number of compressor tiles to be used in this memory region" newline bitfld.long 0x5C 0.--1. "BASE_ADDRESS,Base address of this memory region in 512bit granularity" "0,1,2,3" line.long 0x60 "RGX_CR_FB_MEM_REGION10_0,Framebuffer Compression/Decompression memory regions for Host and TLA accesses" hexmask.long 0x60 0.--31. 1. "BASE_ADDRESS,Base address of this memory region in 512bit granularity" line.long 0x64 "RGX_CR_FB_MEM_REGION10_1,Framebuffer Compression/Decompression memory regions for Host and TLA accesses" hexmask.long.byte 0x64 25.--31. 1. "Reserved_57,Reserved_57" newline hexmask.long.tbyte 0x64 2.--24. 1. "NUM_TILES,The number of compressor tiles to be used in this memory region" newline bitfld.long 0x64 0.--1. "BASE_ADDRESS,Base address of this memory region in 512bit granularity" "0,1,2,3" line.long 0x68 "RGX_CR_FB_MEM_REGION11_0,Framebuffer Compression/Decompression memory regions for Host and TLA accesses" hexmask.long 0x68 0.--31. 1. "BASE_ADDRESS,Base address of this memory region in 512bit granularity" line.long 0x6C "RGX_CR_FB_MEM_REGION11_1,Framebuffer Compression/Decompression memory regions for Host and TLA accesses" hexmask.long.byte 0x6C 25.--31. 1. "Reserved_57,Reserved_57" newline hexmask.long.tbyte 0x6C 2.--24. 1. "NUM_TILES,The number of compressor tiles to be used in this memory region" newline bitfld.long 0x6C 0.--1. "BASE_ADDRESS,Base address of this memory region in 512bit granularity" "0,1,2,3" line.long 0x70 "RGX_CR_FB_MEM_REGION12_0,Framebuffer Compression/Decompression memory regions for Host and TLA accesses" hexmask.long 0x70 0.--31. 1. "BASE_ADDRESS,Base address of this memory region in 512bit granularity" line.long 0x74 "RGX_CR_FB_MEM_REGION12_1,Framebuffer Compression/Decompression memory regions for Host and TLA accesses" hexmask.long.byte 0x74 25.--31. 1. "Reserved_57,Reserved_57" newline hexmask.long.tbyte 0x74 2.--24. 1. "NUM_TILES,The number of compressor tiles to be used in this memory region" newline bitfld.long 0x74 0.--1. "BASE_ADDRESS,Base address of this memory region in 512bit granularity" "0,1,2,3" line.long 0x78 "RGX_CR_FB_MEM_REGION13_0,Framebuffer Compression/Decompression memory regions for Host and TLA accesses" hexmask.long 0x78 0.--31. 1. "BASE_ADDRESS,Base address of this memory region in 512bit granularity" line.long 0x7C "RGX_CR_FB_MEM_REGION13_1,Framebuffer Compression/Decompression memory regions for Host and TLA accesses" hexmask.long.byte 0x7C 25.--31. 1. "Reserved_57,Reserved_57" newline hexmask.long.tbyte 0x7C 2.--24. 1. "NUM_TILES,The number of compressor tiles to be used in this memory region" newline bitfld.long 0x7C 0.--1. "BASE_ADDRESS,Base address of this memory region in 512bit granularity" "0,1,2,3" line.long 0x80 "RGX_CR_FB_MEM_REGION14_0,Framebuffer Compression/Decompression memory regions for Host and TLA accesses" hexmask.long 0x80 0.--31. 1. "BASE_ADDRESS,Base address of this memory region in 512bit granularity" line.long 0x84 "RGX_CR_FB_MEM_REGION14_1,Framebuffer Compression/Decompression memory regions for Host and TLA accesses" hexmask.long.byte 0x84 25.--31. 1. "Reserved_57,Reserved_57" newline hexmask.long.tbyte 0x84 2.--24. 1. "NUM_TILES,The number of compressor tiles to be used in this memory region" newline bitfld.long 0x84 0.--1. "BASE_ADDRESS,Base address of this memory region in 512bit granularity" "0,1,2,3" line.long 0x88 "RGX_CR_FB_MEM_REGION15_0,Framebuffer Compression/Decompression memory regions for Host and TLA accesses" hexmask.long 0x88 0.--31. 1. "BASE_ADDRESS,Base address of this memory region in 512bit granularity" line.long 0x8C "RGX_CR_FB_MEM_REGION15_1,Framebuffer Compression/Decompression memory regions for Host and TLA accesses" hexmask.long.byte 0x8C 25.--31. 1. "Reserved_57,Reserved_57" newline hexmask.long.tbyte 0x8C 2.--24. 1. "NUM_TILES,The number of compressor tiles to be used in this memory region" newline bitfld.long 0x8C 0.--1. "BASE_ADDRESS,Base address of this memory region in 512bit granularity" "0,1,2,3" line.long 0x90 "RGX_CR_FB_MEM_REGION_CTRL0_0,Framebuffer Compression/Decompression memory regions for Host and TLA accesses" hexmask.long.byte 0x90 25.--31. 1. "DIMY,Surface height in terms of TILE_TYPE for this memory region" newline hexmask.long.word 0x90 12.--24. 1. "DIMX,Surface width in terms of TILE_TYPE for this memory region" newline bitfld.long 0x90 11. "MEML,Surface Memory layout for this memory region 0=linear 1=twiddled" "linear,twiddled" newline bitfld.long 0x90 9.--10. "DM,Data master to be used for this memory region 00 = TA/Vertex 01 = 3D/Pixel 10 = Compute 11 = Data Master of Requester If the memory region is being accessed by the TLA the data master is set to the TLA data master If the memory region is being.." "TA/Vertex,?,?,?" newline bitfld.long 0x90 8. "TILE_TYPE,Compressor tile type 0 = 8x8 pixels 1 = 16x4 pixels" "0,1" newline hexmask.long.byte 0x90 1.--7. 1. "FMT,The pixel format to be used in this memory region" newline bitfld.long 0x90 0. "MODE,Defines if this memory region maps to BIF or FBC/FBDC access; 0 = BIF 1 = FBC/FBDC" "BIF,FBC/FBDC" line.long 0x94 "RGX_CR_FB_MEM_REGION_CTRL0_1,Framebuffer Compression/Decompression memory regions for Host and TLA accesses" hexmask.long.tbyte 0x94 15.--31. 1. "Reserved_47,Reserved_47" newline bitfld.long 0x94 14. "PORT,Defines if this memory region is to be used by the TLA or Host port. 0 = TLA Port 1 = Host Port" "TLA Port,Host Port" newline bitfld.long 0x94 13. "ACTIVE,Defines if this memory region is active or not default to INACTIVE. Used in conjuction with MODE field to define if a memory region maps to BIF or FBC/FBDC access. If active then this region base address is used to check if an access is for the.." "0,1" newline bitfld.long 0x94 12. "SLC_NOLINEFILL,SLC cache no line fill Policy: 0= line fill on miss 1=no line fill on miss" "line fill on miss,no line fill on miss" newline bitfld.long 0x94 10.--11. "SLC_POLICY,SLC cache Policy: 00=Bypass 01=Write Back 10 =Write Through 11=Cached Read" "Bypass,Write Back,?,?" newline bitfld.long 0x94 9. "TLCACHE_POLICY,Tile cache Policy: 1=no line fill on miss 0=line fill on miss" "line fill on miss,no line fill on miss" newline bitfld.long 0x94 8. "COR_COLOUR_ENABLE,Correlation Colour Enable 0=off 1=on" "off,on" newline bitfld.long 0x94 7. "IADDR,Direct/Indirect Addressing: 1=indirect 0=direct" "direct,indirect" newline hexmask.long.byte 0x94 0.--6. 1. "DIMY,Surface height in terms of TILE_TYPE for this memory region" line.long 0x98 "RGX_CR_FB_MEM_REGION_CTRL1_0,Framebuffer Compression/Decompression memory regions for Host and TLA accesses" hexmask.long.byte 0x98 25.--31. 1. "DIMY,Surface height in terms of TILE_TYPE for this memory region" newline hexmask.long.word 0x98 12.--24. 1. "DIMX,Surface width in terms of TILE_TYPE for this memory region" newline bitfld.long 0x98 11. "MEML,Surface Memory layout for this memory region 0=linear 1=twiddled" "linear,twiddled" newline bitfld.long 0x98 9.--10. "DM,Data master to be used for this memory region 00 = TA/Vertex 01 = 3D/Pixel 10 = Compute 11 = Data Master of Requester If the memory region is being accessed by the TLA the data master is set to the TLA data master If the memory region is being.." "TA/Vertex,?,?,?" newline bitfld.long 0x98 8. "TILE_TYPE,Compressor tile type 0 = 8x8 pixels 1 = 16x4 pixels" "0,1" newline hexmask.long.byte 0x98 1.--7. 1. "FMT,The pixel format to be used in this memory region" newline bitfld.long 0x98 0. "MODE,Defines if this memory region maps to BIF or FBC/FBDC access; 0 = BIF 1 = FBC/FBDC" "BIF,FBC/FBDC" line.long 0x9C "RGX_CR_FB_MEM_REGION_CTRL1_1,Framebuffer Compression/Decompression memory regions for Host and TLA accesses" hexmask.long.tbyte 0x9C 15.--31. 1. "Reserved_47,Reserved_47" newline bitfld.long 0x9C 14. "PORT,Defines if this memory region is to be used by the TLA or Host port. 0 = TLA Port 1 = Host Port" "TLA Port,Host Port" newline bitfld.long 0x9C 13. "ACTIVE,Defines if this memory region is active or not default to INACTIVE. Used in conjuction with MODE field to define if a memory region maps to BIF or FBC/FBDC access. If active then this region base address is used to check if an access is for the.." "0,1" newline bitfld.long 0x9C 12. "SLC_NOLINEFILL,SLC cache no line fill Policy: 0= line fill on miss 1=no line fill on miss" "line fill on miss,no line fill on miss" newline bitfld.long 0x9C 10.--11. "SLC_POLICY,SLC cache Policy: 00=Bypass 01=Write Back 10 =Write Through 11=Cached Read" "Bypass,Write Back,?,?" newline bitfld.long 0x9C 9. "TLCACHE_POLICY,Tile cache Policy: 1=no line fill on miss 0=line fill on miss" "line fill on miss,no line fill on miss" newline bitfld.long 0x9C 8. "COR_COLOUR_ENABLE,Correlation Colour Enable 0=off 1=on" "off,on" newline bitfld.long 0x9C 7. "IADDR,Direct/Indirect Addressing: 1=indirect 0=direct" "direct,indirect" newline hexmask.long.byte 0x9C 0.--6. 1. "DIMY,Surface height in terms of TILE_TYPE for this memory region" line.long 0xA0 "RGX_CR_FB_MEM_REGION_CTRL2_0,Framebuffer Compression/Decompression memory regions for Host and TLA accesses" hexmask.long.byte 0xA0 25.--31. 1. "DIMY,Surface height in terms of TILE_TYPE for this memory region" newline hexmask.long.word 0xA0 12.--24. 1. "DIMX,Surface width in terms of TILE_TYPE for this memory region" newline bitfld.long 0xA0 11. "MEML,Surface Memory layout for this memory region 0=linear 1=twiddled" "linear,twiddled" newline bitfld.long 0xA0 9.--10. "DM,Data master to be used for this memory region 00 = TA/Vertex 01 = 3D/Pixel 10 = Compute 11 = Data Master of Requester If the memory region is being accessed by the TLA the data master is set to the TLA data master If the memory region is being.." "TA/Vertex,?,?,?" newline bitfld.long 0xA0 8. "TILE_TYPE,Compressor tile type 0 = 8x8 pixels 1 = 16x4 pixels" "0,1" newline hexmask.long.byte 0xA0 1.--7. 1. "FMT,The pixel format to be used in this memory region" newline bitfld.long 0xA0 0. "MODE,Defines if this memory region maps to BIF or FBC/FBDC access; 0 = BIF 1 = FBC/FBDC" "BIF,FBC/FBDC" line.long 0xA4 "RGX_CR_FB_MEM_REGION_CTRL2_1,Framebuffer Compression/Decompression memory regions for Host and TLA accesses" hexmask.long.tbyte 0xA4 15.--31. 1. "Reserved_47,Reserved_47" newline bitfld.long 0xA4 14. "PORT,Defines if this memory region is to be used by the TLA or Host port. 0 = TLA Port 1 = Host Port" "TLA Port,Host Port" newline bitfld.long 0xA4 13. "ACTIVE,Defines if this memory region is active or not default to INACTIVE. Used in conjuction with MODE field to define if a memory region maps to BIF or FBC/FBDC access. If active then this region base address is used to check if an access is for the.." "0,1" newline bitfld.long 0xA4 12. "SLC_NOLINEFILL,SLC cache no line fill Policy: 0= line fill on miss 1=no line fill on miss" "line fill on miss,no line fill on miss" newline bitfld.long 0xA4 10.--11. "SLC_POLICY,SLC cache Policy: 00=Bypass 01=Write Back 10 =Write Through 11=Cached Read" "Bypass,Write Back,?,?" newline bitfld.long 0xA4 9. "TLCACHE_POLICY,Tile cache Policy: 1=no line fill on miss 0=line fill on miss" "line fill on miss,no line fill on miss" newline bitfld.long 0xA4 8. "COR_COLOUR_ENABLE,Correlation Colour Enable 0=off 1=on" "off,on" newline bitfld.long 0xA4 7. "IADDR,Direct/Indirect Addressing: 1=indirect 0=direct" "direct,indirect" newline hexmask.long.byte 0xA4 0.--6. 1. "DIMY,Surface height in terms of TILE_TYPE for this memory region" line.long 0xA8 "RGX_CR_FB_MEM_REGION_CTRL3_0,Framebuffer Compression/Decompression memory regions for Host and TLA accesses" hexmask.long.byte 0xA8 25.--31. 1. "DIMY,Surface height in terms of TILE_TYPE for this memory region" newline hexmask.long.word 0xA8 12.--24. 1. "DIMX,Surface width in terms of TILE_TYPE for this memory region" newline bitfld.long 0xA8 11. "MEML,Surface Memory layout for this memory region 0=linear 1=twiddled" "linear,twiddled" newline bitfld.long 0xA8 9.--10. "DM,Data master to be used for this memory region 00 = TA/Vertex 01 = 3D/Pixel 10 = Compute 11 = Data Master of Requester If the memory region is being accessed by the TLA the data master is set to the TLA data master If the memory region is being.." "TA/Vertex,?,?,?" newline bitfld.long 0xA8 8. "TILE_TYPE,Compressor tile type 0 = 8x8 pixels 1 = 16x4 pixels" "0,1" newline hexmask.long.byte 0xA8 1.--7. 1. "FMT,The pixel format to be used in this memory region" newline bitfld.long 0xA8 0. "MODE,Defines if this memory region maps to BIF or FBC/FBDC access; 0 = BIF 1 = FBC/FBDC" "BIF,FBC/FBDC" line.long 0xAC "RGX_CR_FB_MEM_REGION_CTRL3_1,Framebuffer Compression/Decompression memory regions for Host and TLA accesses" hexmask.long.tbyte 0xAC 15.--31. 1. "Reserved_47,Reserved_47" newline bitfld.long 0xAC 14. "PORT,Defines if this memory region is to be used by the TLA or Host port. 0 = TLA Port 1 = Host Port" "TLA Port,Host Port" newline bitfld.long 0xAC 13. "ACTIVE,Defines if this memory region is active or not default to INACTIVE. Used in conjuction with MODE field to define if a memory region maps to BIF or FBC/FBDC access. If active then this region base address is used to check if an access is for the.." "0,1" newline bitfld.long 0xAC 12. "SLC_NOLINEFILL,SLC cache no line fill Policy: 0= line fill on miss 1=no line fill on miss" "line fill on miss,no line fill on miss" newline bitfld.long 0xAC 10.--11. "SLC_POLICY,SLC cache Policy: 00=Bypass 01=Write Back 10 =Write Through 11=Cached Read" "Bypass,Write Back,?,?" newline bitfld.long 0xAC 9. "TLCACHE_POLICY,Tile cache Policy: 1=no line fill on miss 0=line fill on miss" "line fill on miss,no line fill on miss" newline bitfld.long 0xAC 8. "COR_COLOUR_ENABLE,Correlation Colour Enable 0=off 1=on" "off,on" newline bitfld.long 0xAC 7. "IADDR,Direct/Indirect Addressing: 1=indirect 0=direct" "direct,indirect" newline hexmask.long.byte 0xAC 0.--6. 1. "DIMY,Surface height in terms of TILE_TYPE for this memory region" line.long 0xB0 "RGX_CR_FB_MEM_REGION_CTRL4_0,Framebuffer Compression/Decompression memory regions for Host and TLA accesses" hexmask.long.byte 0xB0 25.--31. 1. "DIMY,Surface height in terms of TILE_TYPE for this memory region" newline hexmask.long.word 0xB0 12.--24. 1. "DIMX,Surface width in terms of TILE_TYPE for this memory region" newline bitfld.long 0xB0 11. "MEML,Surface Memory layout for this memory region 0=linear 1=twiddled" "linear,twiddled" newline bitfld.long 0xB0 9.--10. "DM,Data master to be used for this memory region 00 = TA/Vertex 01 = 3D/Pixel 10 = Compute 11 = Data Master of Requester If the memory region is being accessed by the TLA the data master is set to the TLA data master If the memory region is being.." "TA/Vertex,?,?,?" newline bitfld.long 0xB0 8. "TILE_TYPE,Compressor tile type 0 = 8x8 pixels 1 = 16x4 pixels" "0,1" newline hexmask.long.byte 0xB0 1.--7. 1. "FMT,The pixel format to be used in this memory region" newline bitfld.long 0xB0 0. "MODE,Defines if this memory region maps to BIF or FBC/FBDC access; 0 = BIF 1 = FBC/FBDC" "BIF,FBC/FBDC" line.long 0xB4 "RGX_CR_FB_MEM_REGION_CTRL4_1,Framebuffer Compression/Decompression memory regions for Host and TLA accesses" hexmask.long.tbyte 0xB4 15.--31. 1. "Reserved_47,Reserved_47" newline bitfld.long 0xB4 14. "PORT,Defines if this memory region is to be used by the TLA or Host port. 0 = TLA Port 1 = Host Port" "TLA Port,Host Port" newline bitfld.long 0xB4 13. "ACTIVE,Defines if this memory region is active or not default to INACTIVE. Used in conjuction with MODE field to define if a memory region maps to BIF or FBC/FBDC access. If active then this region base address is used to check if an access is for the.." "0,1" newline bitfld.long 0xB4 12. "SLC_NOLINEFILL,SLC cache no line fill Policy: 0= line fill on miss 1=no line fill on miss" "line fill on miss,no line fill on miss" newline bitfld.long 0xB4 10.--11. "SLC_POLICY,SLC cache Policy: 00=Bypass 01=Write Back 10 =Write Through 11=Cached Read" "Bypass,Write Back,?,?" newline bitfld.long 0xB4 9. "TLCACHE_POLICY,Tile cache Policy: 1=no line fill on miss 0=line fill on miss" "line fill on miss,no line fill on miss" newline bitfld.long 0xB4 8. "COR_COLOUR_ENABLE,Correlation Colour Enable 0=off 1=on" "off,on" newline bitfld.long 0xB4 7. "IADDR,Direct/Indirect Addressing: 1=indirect 0=direct" "direct,indirect" newline hexmask.long.byte 0xB4 0.--6. 1. "DIMY,Surface height in terms of TILE_TYPE for this memory region" line.long 0xB8 "RGX_CR_FB_MEM_REGION_CTRL5_0,Framebuffer Compression/Decompression memory regions for Host and TLA accesses" hexmask.long.byte 0xB8 25.--31. 1. "DIMY,Surface height in terms of TILE_TYPE for this memory region" newline hexmask.long.word 0xB8 12.--24. 1. "DIMX,Surface width in terms of TILE_TYPE for this memory region" newline bitfld.long 0xB8 11. "MEML,Surface Memory layout for this memory region 0=linear 1=twiddled" "linear,twiddled" newline bitfld.long 0xB8 9.--10. "DM,Data master to be used for this memory region 00 = TA/Vertex 01 = 3D/Pixel 10 = Compute 11 = Data Master of Requester If the memory region is being accessed by the TLA the data master is set to the TLA data master If the memory region is being.." "TA/Vertex,?,?,?" newline bitfld.long 0xB8 8. "TILE_TYPE,Compressor tile type 0 = 8x8 pixels 1 = 16x4 pixels" "0,1" newline hexmask.long.byte 0xB8 1.--7. 1. "FMT,The pixel format to be used in this memory region" newline bitfld.long 0xB8 0. "MODE,Defines if this memory region maps to BIF or FBC/FBDC access; 0 = BIF 1 = FBC/FBDC" "BIF,FBC/FBDC" line.long 0xBC "RGX_CR_FB_MEM_REGION_CTRL5_1,Framebuffer Compression/Decompression memory regions for Host and TLA accesses" hexmask.long.tbyte 0xBC 15.--31. 1. "Reserved_47,Reserved_47" newline bitfld.long 0xBC 14. "PORT,Defines if this memory region is to be used by the TLA or Host port. 0 = TLA Port 1 = Host Port" "TLA Port,Host Port" newline bitfld.long 0xBC 13. "ACTIVE,Defines if this memory region is active or not default to INACTIVE. Used in conjuction with MODE field to define if a memory region maps to BIF or FBC/FBDC access. If active then this region base address is used to check if an access is for the.." "0,1" newline bitfld.long 0xBC 12. "SLC_NOLINEFILL,SLC cache no line fill Policy: 0= line fill on miss 1=no line fill on miss" "line fill on miss,no line fill on miss" newline bitfld.long 0xBC 10.--11. "SLC_POLICY,SLC cache Policy: 00=Bypass 01=Write Back 10 =Write Through 11=Cached Read" "Bypass,Write Back,?,?" newline bitfld.long 0xBC 9. "TLCACHE_POLICY,Tile cache Policy: 1=no line fill on miss 0=line fill on miss" "line fill on miss,no line fill on miss" newline bitfld.long 0xBC 8. "COR_COLOUR_ENABLE,Correlation Colour Enable 0=off 1=on" "off,on" newline bitfld.long 0xBC 7. "IADDR,Direct/Indirect Addressing: 1=indirect 0=direct" "direct,indirect" newline hexmask.long.byte 0xBC 0.--6. 1. "DIMY,Surface height in terms of TILE_TYPE for this memory region" line.long 0xC0 "RGX_CR_FB_MEM_REGION_CTRL6_0,Framebuffer Compression/Decompression memory regions for Host and TLA accesses" hexmask.long.byte 0xC0 25.--31. 1. "DIMY,Surface height in terms of TILE_TYPE for this memory region" newline hexmask.long.word 0xC0 12.--24. 1. "DIMX,Surface width in terms of TILE_TYPE for this memory region" newline bitfld.long 0xC0 11. "MEML,Surface Memory layout for this memory region 0=linear 1=twiddled" "linear,twiddled" newline bitfld.long 0xC0 9.--10. "DM,Data master to be used for this memory region 00 = TA/Vertex 01 = 3D/Pixel 10 = Compute 11 = Data Master of Requester If the memory region is being accessed by the TLA the data master is set to the TLA data master If the memory region is being.." "TA/Vertex,?,?,?" newline bitfld.long 0xC0 8. "TILE_TYPE,Compressor tile type 0 = 8x8 pixels 1 = 16x4 pixels" "0,1" newline hexmask.long.byte 0xC0 1.--7. 1. "FMT,The pixel format to be used in this memory region" newline bitfld.long 0xC0 0. "MODE,Defines if this memory region maps to BIF or FBC/FBDC access; 0 = BIF 1 = FBC/FBDC" "BIF,FBC/FBDC" line.long 0xC4 "RGX_CR_FB_MEM_REGION_CTRL6_1,Framebuffer Compression/Decompression memory regions for Host and TLA accesses" hexmask.long.tbyte 0xC4 15.--31. 1. "Reserved_47,Reserved_47" newline bitfld.long 0xC4 14. "PORT,Defines if this memory region is to be used by the TLA or Host port. 0 = TLA Port 1 = Host Port" "TLA Port,Host Port" newline bitfld.long 0xC4 13. "ACTIVE,Defines if this memory region is active or not default to INACTIVE. Used in conjuction with MODE field to define if a memory region maps to BIF or FBC/FBDC access. If active then this region base address is used to check if an access is for the.." "0,1" newline bitfld.long 0xC4 12. "SLC_NOLINEFILL,SLC cache no line fill Policy: 0= line fill on miss 1=no line fill on miss" "line fill on miss,no line fill on miss" newline bitfld.long 0xC4 10.--11. "SLC_POLICY,SLC cache Policy: 00=Bypass 01=Write Back 10 =Write Through 11=Cached Read" "Bypass,Write Back,?,?" newline bitfld.long 0xC4 9. "TLCACHE_POLICY,Tile cache Policy: 1=no line fill on miss 0=line fill on miss" "line fill on miss,no line fill on miss" newline bitfld.long 0xC4 8. "COR_COLOUR_ENABLE,Correlation Colour Enable 0=off 1=on" "off,on" newline bitfld.long 0xC4 7. "IADDR,Direct/Indirect Addressing: 1=indirect 0=direct" "direct,indirect" newline hexmask.long.byte 0xC4 0.--6. 1. "DIMY,Surface height in terms of TILE_TYPE for this memory region" line.long 0xC8 "RGX_CR_FB_MEM_REGION_CTRL7_0,Framebuffer Compression/Decompression memory regions for Host and TLA accesses" hexmask.long.byte 0xC8 25.--31. 1. "DIMY,Surface height in terms of TILE_TYPE for this memory region" newline hexmask.long.word 0xC8 12.--24. 1. "DIMX,Surface width in terms of TILE_TYPE for this memory region" newline bitfld.long 0xC8 11. "MEML,Surface Memory layout for this memory region 0=linear 1=twiddled" "linear,twiddled" newline bitfld.long 0xC8 9.--10. "DM,Data master to be used for this memory region 00 = TA/Vertex 01 = 3D/Pixel 10 = Compute 11 = Data Master of Requester If the memory region is being accessed by the TLA the data master is set to the TLA data master If the memory region is being.." "TA/Vertex,?,?,?" newline bitfld.long 0xC8 8. "TILE_TYPE,Compressor tile type 0 = 8x8 pixels 1 = 16x4 pixels" "0,1" newline hexmask.long.byte 0xC8 1.--7. 1. "FMT,The pixel format to be used in this memory region" newline bitfld.long 0xC8 0. "MODE,Defines if this memory region maps to BIF or FBC/FBDC access; 0 = BIF 1 = FBC/FBDC" "BIF,FBC/FBDC" line.long 0xCC "RGX_CR_FB_MEM_REGION_CTRL7_1,Framebuffer Compression/Decompression memory regions for Host and TLA accesses" hexmask.long.tbyte 0xCC 15.--31. 1. "Reserved_47,Reserved_47" newline bitfld.long 0xCC 14. "PORT,Defines if this memory region is to be used by the TLA or Host port. 0 = TLA Port 1 = Host Port" "TLA Port,Host Port" newline bitfld.long 0xCC 13. "ACTIVE,Defines if this memory region is active or not default to INACTIVE. Used in conjuction with MODE field to define if a memory region maps to BIF or FBC/FBDC access. If active then this region base address is used to check if an access is for the.." "0,1" newline bitfld.long 0xCC 12. "SLC_NOLINEFILL,SLC cache no line fill Policy: 0= line fill on miss 1=no line fill on miss" "line fill on miss,no line fill on miss" newline bitfld.long 0xCC 10.--11. "SLC_POLICY,SLC cache Policy: 00=Bypass 01=Write Back 10 =Write Through 11=Cached Read" "Bypass,Write Back,?,?" newline bitfld.long 0xCC 9. "TLCACHE_POLICY,Tile cache Policy: 1=no line fill on miss 0=line fill on miss" "line fill on miss,no line fill on miss" newline bitfld.long 0xCC 8. "COR_COLOUR_ENABLE,Correlation Colour Enable 0=off 1=on" "off,on" newline bitfld.long 0xCC 7. "IADDR,Direct/Indirect Addressing: 1=indirect 0=direct" "direct,indirect" newline hexmask.long.byte 0xCC 0.--6. 1. "DIMY,Surface height in terms of TILE_TYPE for this memory region" line.long 0xD0 "RGX_CR_FB_MEM_REGION_CTRL8_0,Framebuffer Compression/Decompression memory regions for Host and TLA accesses" hexmask.long.byte 0xD0 25.--31. 1. "DIMY,Surface height in terms of TILE_TYPE for this memory region" newline hexmask.long.word 0xD0 12.--24. 1. "DIMX,Surface width in terms of TILE_TYPE for this memory region" newline bitfld.long 0xD0 11. "MEML,Surface Memory layout for this memory region 0=linear 1=twiddled" "linear,twiddled" newline bitfld.long 0xD0 9.--10. "DM,Data master to be used for this memory region 00 = TA/Vertex 01 = 3D/Pixel 10 = Compute 11 = Data Master of Requester If the memory region is being accessed by the TLA the data master is set to the TLA data master If the memory region is being.." "TA/Vertex,?,?,?" newline bitfld.long 0xD0 8. "TILE_TYPE,Compressor tile type 0 = 8x8 pixels 1 = 16x4 pixels" "0,1" newline hexmask.long.byte 0xD0 1.--7. 1. "FMT,The pixel format to be used in this memory region" newline bitfld.long 0xD0 0. "MODE,Defines if this memory region maps to BIF or FBC/FBDC access; 0 = BIF 1 = FBC/FBDC" "BIF,FBC/FBDC" line.long 0xD4 "RGX_CR_FB_MEM_REGION_CTRL8_1,Framebuffer Compression/Decompression memory regions for Host and TLA accesses" hexmask.long.tbyte 0xD4 15.--31. 1. "Reserved_47,Reserved_47" newline bitfld.long 0xD4 14. "PORT,Defines if this memory region is to be used by the TLA or Host port. 0 = TLA Port 1 = Host Port" "TLA Port,Host Port" newline bitfld.long 0xD4 13. "ACTIVE,Defines if this memory region is active or not default to INACTIVE. Used in conjuction with MODE field to define if a memory region maps to BIF or FBC/FBDC access. If active then this region base address is used to check if an access is for the.." "0,1" newline bitfld.long 0xD4 12. "SLC_NOLINEFILL,SLC cache no line fill Policy: 0= line fill on miss 1=no line fill on miss" "line fill on miss,no line fill on miss" newline bitfld.long 0xD4 10.--11. "SLC_POLICY,SLC cache Policy: 00=Bypass 01=Write Back 10 =Write Through 11=Cached Read" "Bypass,Write Back,?,?" newline bitfld.long 0xD4 9. "TLCACHE_POLICY,Tile cache Policy: 1=no line fill on miss 0=line fill on miss" "line fill on miss,no line fill on miss" newline bitfld.long 0xD4 8. "COR_COLOUR_ENABLE,Correlation Colour Enable 0=off 1=on" "off,on" newline bitfld.long 0xD4 7. "IADDR,Direct/Indirect Addressing: 1=indirect 0=direct" "direct,indirect" newline hexmask.long.byte 0xD4 0.--6. 1. "DIMY,Surface height in terms of TILE_TYPE for this memory region" line.long 0xD8 "RGX_CR_FB_MEM_REGION_CTRL9_0,Framebuffer Compression/Decompression memory regions for Host and TLA accesses" hexmask.long.byte 0xD8 25.--31. 1. "DIMY,Surface height in terms of TILE_TYPE for this memory region" newline hexmask.long.word 0xD8 12.--24. 1. "DIMX,Surface width in terms of TILE_TYPE for this memory region" newline bitfld.long 0xD8 11. "MEML,Surface Memory layout for this memory region 0=linear 1=twiddled" "linear,twiddled" newline bitfld.long 0xD8 9.--10. "DM,Data master to be used for this memory region 00 = TA/Vertex 01 = 3D/Pixel 10 = Compute 11 = Data Master of Requester If the memory region is being accessed by the TLA the data master is set to the TLA data master If the memory region is being.." "TA/Vertex,?,?,?" newline bitfld.long 0xD8 8. "TILE_TYPE,Compressor tile type 0 = 8x8 pixels 1 = 16x4 pixels" "0,1" newline hexmask.long.byte 0xD8 1.--7. 1. "FMT,The pixel format to be used in this memory region" newline bitfld.long 0xD8 0. "MODE,Defines if this memory region maps to BIF or FBC/FBDC access; 0 = BIF 1 = FBC/FBDC" "BIF,FBC/FBDC" line.long 0xDC "RGX_CR_FB_MEM_REGION_CTRL9_1,Framebuffer Compression/Decompression memory regions for Host and TLA accesses" hexmask.long.tbyte 0xDC 15.--31. 1. "Reserved_47,Reserved_47" newline bitfld.long 0xDC 14. "PORT,Defines if this memory region is to be used by the TLA or Host port. 0 = TLA Port 1 = Host Port" "TLA Port,Host Port" newline bitfld.long 0xDC 13. "ACTIVE,Defines if this memory region is active or not default to INACTIVE. Used in conjuction with MODE field to define if a memory region maps to BIF or FBC/FBDC access. If active then this region base address is used to check if an access is for the.." "0,1" newline bitfld.long 0xDC 12. "SLC_NOLINEFILL,SLC cache no line fill Policy: 0= line fill on miss 1=no line fill on miss" "line fill on miss,no line fill on miss" newline bitfld.long 0xDC 10.--11. "SLC_POLICY,SLC cache Policy: 00=Bypass 01=Write Back 10 =Write Through 11=Cached Read" "Bypass,Write Back,?,?" newline bitfld.long 0xDC 9. "TLCACHE_POLICY,Tile cache Policy: 1=no line fill on miss 0=line fill on miss" "line fill on miss,no line fill on miss" newline bitfld.long 0xDC 8. "COR_COLOUR_ENABLE,Correlation Colour Enable 0=off 1=on" "off,on" newline bitfld.long 0xDC 7. "IADDR,Direct/Indirect Addressing: 1=indirect 0=direct" "direct,indirect" newline hexmask.long.byte 0xDC 0.--6. 1. "DIMY,Surface height in terms of TILE_TYPE for this memory region" line.long 0xE0 "RGX_CR_FB_MEM_REGION_CTRL10_0,Framebuffer Compression/Decompression memory regions for Host and TLA accesses" hexmask.long.byte 0xE0 25.--31. 1. "DIMY,Surface height in terms of TILE_TYPE for this memory region" newline hexmask.long.word 0xE0 12.--24. 1. "DIMX,Surface width in terms of TILE_TYPE for this memory region" newline bitfld.long 0xE0 11. "MEML,Surface Memory layout for this memory region 0=linear 1=twiddled" "linear,twiddled" newline bitfld.long 0xE0 9.--10. "DM,Data master to be used for this memory region 00 = TA/Vertex 01 = 3D/Pixel 10 = Compute 11 = Data Master of Requester If the memory region is being accessed by the TLA the data master is set to the TLA data master If the memory region is being.." "TA/Vertex,?,?,?" newline bitfld.long 0xE0 8. "TILE_TYPE,Compressor tile type 0 = 8x8 pixels 1 = 16x4 pixels" "0,1" newline hexmask.long.byte 0xE0 1.--7. 1. "FMT,The pixel format to be used in this memory region" newline bitfld.long 0xE0 0. "MODE,Defines if this memory region maps to BIF or FBC/FBDC access; 0 = BIF 1 = FBC/FBDC" "BIF,FBC/FBDC" line.long 0xE4 "RGX_CR_FB_MEM_REGION_CTRL10_1,Framebuffer Compression/Decompression memory regions for Host and TLA accesses" hexmask.long.tbyte 0xE4 15.--31. 1. "Reserved_47,Reserved_47" newline bitfld.long 0xE4 14. "PORT,Defines if this memory region is to be used by the TLA or Host port. 0 = TLA Port 1 = Host Port" "TLA Port,Host Port" newline bitfld.long 0xE4 13. "ACTIVE,Defines if this memory region is active or not default to INACTIVE. Used in conjuction with MODE field to define if a memory region maps to BIF or FBC/FBDC access. If active then this region base address is used to check if an access is for the.." "0,1" newline bitfld.long 0xE4 12. "SLC_NOLINEFILL,SLC cache no line fill Policy: 0= line fill on miss 1=no line fill on miss" "line fill on miss,no line fill on miss" newline bitfld.long 0xE4 10.--11. "SLC_POLICY,SLC cache Policy: 00=Bypass 01=Write Back 10 =Write Through 11=Cached Read" "Bypass,Write Back,?,?" newline bitfld.long 0xE4 9. "TLCACHE_POLICY,Tile cache Policy: 1=no line fill on miss 0=line fill on miss" "line fill on miss,no line fill on miss" newline bitfld.long 0xE4 8. "COR_COLOUR_ENABLE,Correlation Colour Enable 0=off 1=on" "off,on" newline bitfld.long 0xE4 7. "IADDR,Direct/Indirect Addressing: 1=indirect 0=direct" "direct,indirect" newline hexmask.long.byte 0xE4 0.--6. 1. "DIMY,Surface height in terms of TILE_TYPE for this memory region" line.long 0xE8 "RGX_CR_FB_MEM_REGION_CTRL11_0,Framebuffer Compression/Decompression memory regions for Host and TLA accesses" hexmask.long.byte 0xE8 25.--31. 1. "DIMY,Surface height in terms of TILE_TYPE for this memory region" newline hexmask.long.word 0xE8 12.--24. 1. "DIMX,Surface width in terms of TILE_TYPE for this memory region" newline bitfld.long 0xE8 11. "MEML,Surface Memory layout for this memory region 0=linear 1=twiddled" "linear,twiddled" newline bitfld.long 0xE8 9.--10. "DM,Data master to be used for this memory region 00 = TA/Vertex 01 = 3D/Pixel 10 = Compute 11 = Data Master of Requester If the memory region is being accessed by the TLA the data master is set to the TLA data master If the memory region is being.." "TA/Vertex,?,?,?" newline bitfld.long 0xE8 8. "TILE_TYPE,Compressor tile type 0 = 8x8 pixels 1 = 16x4 pixels" "0,1" newline hexmask.long.byte 0xE8 1.--7. 1. "FMT,The pixel format to be used in this memory region" newline bitfld.long 0xE8 0. "MODE,Defines if this memory region maps to BIF or FBC/FBDC access; 0 = BIF 1 = FBC/FBDC" "BIF,FBC/FBDC" line.long 0xEC "RGX_CR_FB_MEM_REGION_CTRL11_1,Framebuffer Compression/Decompression memory regions for Host and TLA accesses" hexmask.long.tbyte 0xEC 15.--31. 1. "Reserved_47,Reserved_47" newline bitfld.long 0xEC 14. "PORT,Defines if this memory region is to be used by the TLA or Host port. 0 = TLA Port 1 = Host Port" "TLA Port,Host Port" newline bitfld.long 0xEC 13. "ACTIVE,Defines if this memory region is active or not default to INACTIVE. Used in conjuction with MODE field to define if a memory region maps to BIF or FBC/FBDC access. If active then this region base address is used to check if an access is for the.." "0,1" newline bitfld.long 0xEC 12. "SLC_NOLINEFILL,SLC cache no line fill Policy: 0= line fill on miss 1=no line fill on miss" "line fill on miss,no line fill on miss" newline bitfld.long 0xEC 10.--11. "SLC_POLICY,SLC cache Policy: 00=Bypass 01=Write Back 10 =Write Through 11=Cached Read" "Bypass,Write Back,?,?" newline bitfld.long 0xEC 9. "TLCACHE_POLICY,Tile cache Policy: 1=no line fill on miss 0=line fill on miss" "line fill on miss,no line fill on miss" newline bitfld.long 0xEC 8. "COR_COLOUR_ENABLE,Correlation Colour Enable 0=off 1=on" "off,on" newline bitfld.long 0xEC 7. "IADDR,Direct/Indirect Addressing: 1=indirect 0=direct" "direct,indirect" newline hexmask.long.byte 0xEC 0.--6. 1. "DIMY,Surface height in terms of TILE_TYPE for this memory region" line.long 0xF0 "RGX_CR_FB_MEM_REGION_CTRL12_0,Framebuffer Compression/Decompression memory regions for Host and TLA accesses" hexmask.long.byte 0xF0 25.--31. 1. "DIMY,Surface height in terms of TILE_TYPE for this memory region" newline hexmask.long.word 0xF0 12.--24. 1. "DIMX,Surface width in terms of TILE_TYPE for this memory region" newline bitfld.long 0xF0 11. "MEML,Surface Memory layout for this memory region 0=linear 1=twiddled" "linear,twiddled" newline bitfld.long 0xF0 9.--10. "DM,Data master to be used for this memory region 00 = TA/Vertex 01 = 3D/Pixel 10 = Compute 11 = Data Master of Requester If the memory region is being accessed by the TLA the data master is set to the TLA data master If the memory region is being.." "TA/Vertex,?,?,?" newline bitfld.long 0xF0 8. "TILE_TYPE,Compressor tile type 0 = 8x8 pixels 1 = 16x4 pixels" "0,1" newline hexmask.long.byte 0xF0 1.--7. 1. "FMT,The pixel format to be used in this memory region" newline bitfld.long 0xF0 0. "MODE,Defines if this memory region maps to BIF or FBC/FBDC access; 0 = BIF 1 = FBC/FBDC" "BIF,FBC/FBDC" line.long 0xF4 "RGX_CR_FB_MEM_REGION_CTRL12_1,Framebuffer Compression/Decompression memory regions for Host and TLA accesses" hexmask.long.tbyte 0xF4 15.--31. 1. "Reserved_47,Reserved_47" newline bitfld.long 0xF4 14. "PORT,Defines if this memory region is to be used by the TLA or Host port. 0 = TLA Port 1 = Host Port" "TLA Port,Host Port" newline bitfld.long 0xF4 13. "ACTIVE,Defines if this memory region is active or not default to INACTIVE. Used in conjuction with MODE field to define if a memory region maps to BIF or FBC/FBDC access. If active then this region base address is used to check if an access is for the.." "0,1" newline bitfld.long 0xF4 12. "SLC_NOLINEFILL,SLC cache no line fill Policy: 0= line fill on miss 1=no line fill on miss" "line fill on miss,no line fill on miss" newline bitfld.long 0xF4 10.--11. "SLC_POLICY,SLC cache Policy: 00=Bypass 01=Write Back 10 =Write Through 11=Cached Read" "Bypass,Write Back,?,?" newline bitfld.long 0xF4 9. "TLCACHE_POLICY,Tile cache Policy: 1=no line fill on miss 0=line fill on miss" "line fill on miss,no line fill on miss" newline bitfld.long 0xF4 8. "COR_COLOUR_ENABLE,Correlation Colour Enable 0=off 1=on" "off,on" newline bitfld.long 0xF4 7. "IADDR,Direct/Indirect Addressing: 1=indirect 0=direct" "direct,indirect" newline hexmask.long.byte 0xF4 0.--6. 1. "DIMY,Surface height in terms of TILE_TYPE for this memory region" line.long 0xF8 "RGX_CR_FB_MEM_REGION_CTRL13_0,Framebuffer Compression/Decompression memory regions for Host and TLA accesses" hexmask.long.byte 0xF8 25.--31. 1. "DIMY,Surface height in terms of TILE_TYPE for this memory region" newline hexmask.long.word 0xF8 12.--24. 1. "DIMX,Surface width in terms of TILE_TYPE for this memory region" newline bitfld.long 0xF8 11. "MEML,Surface Memory layout for this memory region 0=linear 1=twiddled" "linear,twiddled" newline bitfld.long 0xF8 9.--10. "DM,Data master to be used for this memory region 00 = TA/Vertex 01 = 3D/Pixel 10 = Compute 11 = Data Master of Requester If the memory region is being accessed by the TLA the data master is set to the TLA data master If the memory region is being.." "TA/Vertex,?,?,?" newline bitfld.long 0xF8 8. "TILE_TYPE,Compressor tile type 0 = 8x8 pixels 1 = 16x4 pixels" "0,1" newline hexmask.long.byte 0xF8 1.--7. 1. "FMT,The pixel format to be used in this memory region" newline bitfld.long 0xF8 0. "MODE,Defines if this memory region maps to BIF or FBC/FBDC access; 0 = BIF 1 = FBC/FBDC" "BIF,FBC/FBDC" line.long 0xFC "RGX_CR_FB_MEM_REGION_CTRL13_1,Framebuffer Compression/Decompression memory regions for Host and TLA accesses" hexmask.long.tbyte 0xFC 15.--31. 1. "Reserved_47,Reserved_47" newline bitfld.long 0xFC 14. "PORT,Defines if this memory region is to be used by the TLA or Host port. 0 = TLA Port 1 = Host Port" "TLA Port,Host Port" newline bitfld.long 0xFC 13. "ACTIVE,Defines if this memory region is active or not default to INACTIVE. Used in conjuction with MODE field to define if a memory region maps to BIF or FBC/FBDC access. If active then this region base address is used to check if an access is for the.." "0,1" newline bitfld.long 0xFC 12. "SLC_NOLINEFILL,SLC cache no line fill Policy: 0= line fill on miss 1=no line fill on miss" "line fill on miss,no line fill on miss" newline bitfld.long 0xFC 10.--11. "SLC_POLICY,SLC cache Policy: 00=Bypass 01=Write Back 10 =Write Through 11=Cached Read" "Bypass,Write Back,?,?" newline bitfld.long 0xFC 9. "TLCACHE_POLICY,Tile cache Policy: 1=no line fill on miss 0=line fill on miss" "line fill on miss,no line fill on miss" newline bitfld.long 0xFC 8. "COR_COLOUR_ENABLE,Correlation Colour Enable 0=off 1=on" "off,on" newline bitfld.long 0xFC 7. "IADDR,Direct/Indirect Addressing: 1=indirect 0=direct" "direct,indirect" newline hexmask.long.byte 0xFC 0.--6. 1. "DIMY,Surface height in terms of TILE_TYPE for this memory region" line.long 0x100 "RGX_CR_FB_MEM_REGION_CTRL14_0,Framebuffer Compression/Decompression memory regions for Host and TLA accesses" hexmask.long.byte 0x100 25.--31. 1. "DIMY,Surface height in terms of TILE_TYPE for this memory region" newline hexmask.long.word 0x100 12.--24. 1. "DIMX,Surface width in terms of TILE_TYPE for this memory region" newline bitfld.long 0x100 11. "MEML,Surface Memory layout for this memory region 0=linear 1=twiddled" "linear,twiddled" newline bitfld.long 0x100 9.--10. "DM,Data master to be used for this memory region 00 = TA/Vertex 01 = 3D/Pixel 10 = Compute 11 = Data Master of Requester If the memory region is being accessed by the TLA the data master is set to the TLA data master If the memory region is being.." "TA/Vertex,?,?,?" newline bitfld.long 0x100 8. "TILE_TYPE,Compressor tile type 0 = 8x8 pixels 1 = 16x4 pixels" "0,1" newline hexmask.long.byte 0x100 1.--7. 1. "FMT,The pixel format to be used in this memory region" newline bitfld.long 0x100 0. "MODE,Defines if this memory region maps to BIF or FBC/FBDC access; 0 = BIF 1 = FBC/FBDC" "BIF,FBC/FBDC" line.long 0x104 "RGX_CR_FB_MEM_REGION_CTRL14_1,Framebuffer Compression/Decompression memory regions for Host and TLA accesses" hexmask.long.tbyte 0x104 15.--31. 1. "Reserved_47,Reserved_47" newline bitfld.long 0x104 14. "PORT,Defines if this memory region is to be used by the TLA or Host port. 0 = TLA Port 1 = Host Port" "TLA Port,Host Port" newline bitfld.long 0x104 13. "ACTIVE,Defines if this memory region is active or not default to INACTIVE. Used in conjuction with MODE field to define if a memory region maps to BIF or FBC/FBDC access. If active then this region base address is used to check if an access is for the.." "0,1" newline bitfld.long 0x104 12. "SLC_NOLINEFILL,SLC cache no line fill Policy: 0= line fill on miss 1=no line fill on miss" "line fill on miss,no line fill on miss" newline bitfld.long 0x104 10.--11. "SLC_POLICY,SLC cache Policy: 00=Bypass 01=Write Back 10 =Write Through 11=Cached Read" "Bypass,Write Back,?,?" newline bitfld.long 0x104 9. "TLCACHE_POLICY,Tile cache Policy: 1=no line fill on miss 0=line fill on miss" "line fill on miss,no line fill on miss" newline bitfld.long 0x104 8. "COR_COLOUR_ENABLE,Correlation Colour Enable 0=off 1=on" "off,on" newline bitfld.long 0x104 7. "IADDR,Direct/Indirect Addressing: 1=indirect 0=direct" "direct,indirect" newline hexmask.long.byte 0x104 0.--6. 1. "DIMY,Surface height in terms of TILE_TYPE for this memory region" line.long 0x108 "RGX_CR_FB_MEM_REGION_CTRL15_0,Framebuffer Compression/Decompression memory regions for Host and TLA accesses" hexmask.long.byte 0x108 25.--31. 1. "DIMY,Surface height in terms of TILE_TYPE for this memory region" newline hexmask.long.word 0x108 12.--24. 1. "DIMX,Surface width in terms of TILE_TYPE for this memory region" newline bitfld.long 0x108 11. "MEML,Surface Memory layout for this memory region 0=linear 1=twiddled" "linear,twiddled" newline bitfld.long 0x108 9.--10. "DM,Data master to be used for this memory region 00 = TA/Vertex 01 = 3D/Pixel 10 = Compute 11 = Data Master of Requester If the memory region is being accessed by the TLA the data master is set to the TLA data master If the memory region is being.." "TA/Vertex,?,?,?" newline bitfld.long 0x108 8. "TILE_TYPE,Compressor tile type 0 = 8x8 pixels 1 = 16x4 pixels" "0,1" newline hexmask.long.byte 0x108 1.--7. 1. "FMT,The pixel format to be used in this memory region" newline bitfld.long 0x108 0. "MODE,Defines if this memory region maps to BIF or FBC/FBDC access; 0 = BIF 1 = FBC/FBDC" "BIF,FBC/FBDC" line.long 0x10C "RGX_CR_FB_MEM_REGION_CTRL15_1,Framebuffer Compression/Decompression memory regions for Host and TLA accesses" hexmask.long.tbyte 0x10C 15.--31. 1. "Reserved_47,Reserved_47" newline bitfld.long 0x10C 14. "PORT,Defines if this memory region is to be used by the TLA or Host port. 0 = TLA Port 1 = Host Port" "TLA Port,Host Port" newline bitfld.long 0x10C 13. "ACTIVE,Defines if this memory region is active or not default to INACTIVE. Used in conjuction with MODE field to define if a memory region maps to BIF or FBC/FBDC access. If active then this region base address is used to check if an access is for the.." "0,1" newline bitfld.long 0x10C 12. "SLC_NOLINEFILL,SLC cache no line fill Policy: 0= line fill on miss 1=no line fill on miss" "line fill on miss,no line fill on miss" newline bitfld.long 0x10C 10.--11. "SLC_POLICY,SLC cache Policy: 00=Bypass 01=Write Back 10 =Write Through 11=Cached Read" "Bypass,Write Back,?,?" newline bitfld.long 0x10C 9. "TLCACHE_POLICY,Tile cache Policy: 1=no line fill on miss 0=line fill on miss" "line fill on miss,no line fill on miss" newline bitfld.long 0x10C 8. "COR_COLOUR_ENABLE,Correlation Colour Enable 0=off 1=on" "off,on" newline bitfld.long 0x10C 7. "IADDR,Direct/Indirect Addressing: 1=indirect 0=direct" "direct,indirect" newline hexmask.long.byte 0x10C 0.--6. 1. "DIMY,Surface height in terms of TILE_TYPE for this memory region" line.long 0x110 "RGX_CR_FB_CDC_ZLS_0,Framebuffer Compression/Decompression configuration register for ZLS access" hexmask.long.byte 0x110 27.--31. 1. "Reserved_27,Reserved_27" newline hexmask.long.tbyte 0x110 4.--26. 1. "FBC_NUM_TILES,FBC ZLS number of compressor tiles in surface in granularity of 8x8x32dwords" newline bitfld.long 0x110 2.--3. "Reserved_2,Reserved_2" "0,1,2,3" newline bitfld.long 0x110 1. "FBC_IADDR,FBC Addressing mode 0 = direct ; 1 = indirect" "direct ;,indirect" newline bitfld.long 0x110 0. "FBDC_IADDR,FBDC Addressing mode 0 = direct ; 1 = indirect" "direct ;,indirect" line.long 0x114 "RGX_CR_FB_CDC_ZLS_1,Framebuffer Compression/Decompression configuration register for ZLS access" hexmask.long 0x114 0.--31. 1. "Reserved_27,Reserved_27" line.long 0x118 "RGX_CR_FB_0,Rascal Arbiter for FBC/FBDC arbiter modes" hexmask.long 0x118 2.--31. 1. "Reserved_2,Reserved_2" newline bitfld.long 0x118 1. "ZLSMCU_ARB_MODE,ZLS and MCU TLDecode Arbiter Mode Re-arbitrate after burst complete 0 = After each request 1 = valid dropped" "After each request,valid dropped" newline bitfld.long 0x118 0. "ZLSPBE_ARB_MODE,ZLS and PBE FBC Arbiter Mode Re-arbitrate after burst complete and 0 = After each request 1 = valid dropped" "After each request,valid dropped" line.long 0x11C "RGX_CR_FB_1,Rascal Arbiter for FBC/FBDC arbiter modes" hexmask.long 0x11C 0.--31. 1. "Reserved_2,Reserved_2" wgroup.long 0x1720++0x7 line.long 0x0 "RGX_CR_MCU_GLB_CFI_0,Global flush and invalidation control for all Texture and Data Cache. Will flush then invalidate cache if both bit 0 & bit 1 set." hexmask.long.tbyte 0x0 10.--31. 1. "Reserved_10,Reserved_10" newline bitfld.long 0x0 9. "DM_FASTRENDER,When set perform operation on fastrender data master" "0,1" newline bitfld.long 0x0 6.--8. "Reserved_6,Reserved_6" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 5. "FENCE,When set additionally perform a fence to external memory before signalling that a flush is complete" "0,1" newline bitfld.long 0x0 4. "DM_COMPUTE,When set perform operation on compute data master" "0,1" newline bitfld.long 0x0 3. "DM_PIXEL,When set perform operation on pixel data master" "0,1" newline bitfld.long 0x0 2. "DM_VERTEX,When set perform operation on vertex data master" "0,1" newline bitfld.long 0x0 1. "FLUSH,When set will flush cache based on data master" "0,1" newline bitfld.long 0x0 0. "INVALIDATE,When set will invalidate cache based on data master. This bit will also invalidate the L0 cache in the MADD and teh YUV cache in the TAG to reset the CSC coefficients." "0,1" line.long 0x4 "RGX_CR_MCU_GLB_CFI_1,Global flush and invalidation control for all Texture and Data Cache. Will flush then invalidate cache if both bit 0 & bit 1 set." hexmask.long 0x4 0.--31. 1. "Reserved_10,Reserved_10" rgroup.long 0x1728++0x7 line.long 0x0 "RGX_CR_MCU_GLB_CFI_EVENT_0,Global flush and invalidation event for all Texture and Data Cache." hexmask.long 0x0 1.--31. 1. "Reserved_1,Reserved_1" newline bitfld.long 0x0 0. "PENDING,1 Indicate there is a pending global CFI operation on the MCU" "0,1" line.long 0x4 "RGX_CR_MCU_GLB_CFI_EVENT_1,Global flush and invalidation event for all Texture and Data Cache." hexmask.long 0x4 0.--31. 1. "Reserved_1,Reserved_1" group.long 0x1730++0x17 line.long 0x0 "RGX_CR_MCU_LIMIT_0,Define the maximum number of cache lines allowed to be allocated to each Data Master within the SLC. Note that values are specified per group with a value of 0x0 denoting no limit. Also note that the specified values operate as soft.." hexmask.long.byte 0x0 24.--31. 1. "Reserved_24,Reserved_24" newline hexmask.long.byte 0x0 16.--23. 1. "DM_COMPUTE,Maximum number of cachelines which can be used by the Compute data master" newline hexmask.long.byte 0x0 8.--15. 1. "DM_PIXEL,Maximum number of cachelines which can be used by the Pixel data master" newline hexmask.long.byte 0x0 0.--7. 1. "DM_VERTEX,Maximum number of cachelines which can be used by the Vertex data master" line.long 0x4 "RGX_CR_MCU_LIMIT_1,Define the maximum number of cache lines allowed to be allocated to each Data Master within the SLC. Note that values are specified per group with a value of 0x0 denoting no limit. Also note that the specified values operate as soft.." hexmask.long 0x4 0.--31. 1. "Reserved_24,Reserved_24" line.long 0x8 "RGX_CR_MCU_CTRL_0,MCU control registers" hexmask.long.word 0x8 18.--31. 1. "Reserved_18,Reserved_18" newline bitfld.long 0x8 17. "PDSRW_L0_OFF,Turn off MCU PDSRW L0 cache" "0,1" newline hexmask.long.byte 0x8 9.--16. 1. "FBDC_REQ_THRESHOLD,Maximum number of outstanding requests each MCU group can have to the Framebuffer Decompression module" newline bitfld.long 0x8 8. "RD_OVERTAKE_THRESH_ENABLE,Enables the use of the threshold to limit the amount of overtaking which is permitted" "0,1" newline hexmask.long.byte 0x8 2.--7. 1. "RD_OVERTAKE_THRESHOLD,The number of read accesses which are permitted to overtake waiting Writebacks when enabled" newline bitfld.long 0x8 1. "INSTANCE_MERGE_DISABLE,Turn off instance merging in the MCU L1" "0,1" newline bitfld.long 0x8 0. "L1_OFF,Turn off MCU L1" "0,1" line.long 0xC "RGX_CR_MCU_CTRL_1,MCU control registers" hexmask.long 0xC 0.--31. 1. "Reserved_18,Reserved_18" line.long 0x10 "RGX_CR_MCU_FENCE_0,Defines the Data Master and Addresses used when the MCU optionally issues a Fence as part of a Flush operation. See MCU_GLB_CFI register for details." hexmask.long 0x10 5.--31. 1. "ADDR,Address value to use when issuing a Fence" newline hexmask.long.byte 0x10 0.--4. 1. "Reserved_0,Reserved_0" line.long 0x14 "RGX_CR_MCU_FENCE_1,Defines the Data Master and Addresses used when the MCU optionally issues a Fence as part of a Flush operation. See MCU_GLB_CFI register for details." hexmask.long.tbyte 0x14 11.--31. 1. "Reserved_43,Reserved_43" newline bitfld.long 0x14 8.--10. "DM,Data Master value to use when issuing a Fence" "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x14 0.--7. 1. "ADDR,Address value to use when issuing a Fence" group.long 0x1780++0x17 line.long 0x0 "RGX_CR_TPU_0,Global control to TPU_MCU_L0|tpu" hexmask.long.tbyte 0x0 9.--31. 1. "Reserved_9,Reserved_9" newline bitfld.long 0x0 8. "MCU_PDS_L0_OFF,Turn off MCU PDSL0 cache" "0,1" newline bitfld.long 0x0 7. "Reserved_7,Reserved_7" "0,1" newline bitfld.long 0x0 6. "TAG_ENABLE_MMU_PREFETCH,Enables generation of prefetch requests to the MMU" "0,1" newline bitfld.long 0x0 5. "TAG_CEM_4K_FACE_PACKING,Pixel data master. Enable 4K-byte alignment between CEM faces when set to 1. It applies for both when mipmap is enabled or disabled" "0,1" newline bitfld.long 0x0 4. "MADD_CONFIG_L0OFF,When set this disables MADD P0 L0 cache" "0,1" newline bitfld.long 0x0 3. "TAG_CEM_FACE_PACKING,Pixel data master. Enable dword alignment between CEM faces when set to 1" "0,1" newline bitfld.long 0x0 2. "TAG_CEMEDGE_DONTFILTER,Pixel data master. Disable filtering over edges/corners for CEM. When set to 1 HW will be seemfull ie always stay in the current map always honour the addressmode. When set to 0 HW will be seemless ie ignore addressmode.." "0,1" newline bitfld.long 0x0 1. "TAG_CEMGRAD_DONTNEGATE,Pixel data master. Disable negation for user supplied gradients for cem swap i. e. will only swap dudx etc not negate" "0,1" newline bitfld.long 0x0 0. "MADD_CONFIG_DXT35_TRANSOVR,When set this disables alternative mode implied by colour0 > colour1 for DXT3 to DXT5" "colour1 for DXT3 to DXT5,?" line.long 0x4 "RGX_CR_TPU_1,Global control to TPU_MCU_L0|tpu" hexmask.long 0x4 0.--31. 1. "Reserved_9,Reserved_9" line.long 0x8 "RGX_CR_TPU_YUV_CSC_COEFFICIENTS_0,Base address for the YUV CSC set of coefficients stored in memory for pixel data master" hexmask.long 0x8 0.--31. 1. "YUV_CSC_COEFFICIENTS_ADDRESS,Base address DWORD aligned for the location in memory of the CSC coefficients" line.long 0xC "RGX_CR_TPU_YUV_CSC_COEFFICIENTS_1,Base address for the YUV CSC set of coefficients stored in memory for pixel data master" hexmask.long 0xC 6.--31. 1. "Reserved_38,Reserved_38" newline hexmask.long.byte 0xC 0.--5. 1. "YUV_CSC_COEFFICIENTS_ADDRESS,Base address DWORD aligned for the location in memory of the CSC coefficients" line.long 0x10 "RGX_CR_TPU_BORDER_COLOUR_TABLE_PDM_0,Base address for the border colour table" hexmask.long 0x10 0.--31. 1. "BORDER_COLOUR_TABLE_ADDRESS,Base address DWORD aligned for the location in memory of the border colour table for the PDM" line.long 0x14 "RGX_CR_TPU_BORDER_COLOUR_TABLE_PDM_1,Base address for the border colour table" hexmask.long 0x14 6.--31. 1. "Reserved_38,Reserved_38" newline hexmask.long.byte 0x14 0.--5. 1. "BORDER_COLOUR_TABLE_ADDRESS,Base address DWORD aligned for the location in memory of the border colour table for the PDM" rgroup.long 0x1798++0x7 line.long 0x0 "RGX_CR_DUST_IDLE_0,RGX_CR_DUST_IDLE_0" hexmask.long 0x0 7.--31. 1. "Reserved_7,Reserved_7" newline bitfld.long 0x0 6. "MCU_L0_WRAP,MCU L0 WRAP Module IDLE" "0,1" newline bitfld.long 0x0 5. "MCU_L0,MCU L0 Module IDLE" "0,1" newline bitfld.long 0x0 4. "TF,TF Module IDLE" "0,1" newline bitfld.long 0x0 3. "MADD,MADD Module IDLE" "0,1" newline bitfld.long 0x0 2. "TAG,TAG Module IDLE" "0,1" newline bitfld.long 0x0 1. "USC1,USC1 Module IDLE" "0,1" newline bitfld.long 0x0 0. "USC0,USC0 Module IDLE" "0,1" line.long 0x4 "RGX_CR_DUST_IDLE_1,RGX_CR_DUST_IDLE_1" hexmask.long 0x4 0.--31. 1. "Reserved_7,Reserved_7" group.long 0x17A0++0xF line.long 0x0 "RGX_CR_TPU_BORDER_COLOUR_TABLE_VDM_0,Base address for the border colour table" hexmask.long 0x0 0.--31. 1. "BORDER_COLOUR_TABLE_ADDRESS,Base address DWORD aligned for the location in memory of the border colour table for the VDM" line.long 0x4 "RGX_CR_TPU_BORDER_COLOUR_TABLE_VDM_1,Base address for the border colour table" hexmask.long 0x4 6.--31. 1. "Reserved_38,Reserved_38" newline hexmask.long.byte 0x4 0.--5. 1. "BORDER_COLOUR_TABLE_ADDRESS,Base address DWORD aligned for the location in memory of the border colour table for the VDM" line.long 0x8 "RGX_CR_TPU_BORDER_COLOUR_TABLE_CDM_0,Base address for the border colour table" hexmask.long 0x8 0.--31. 1. "BORDER_COLOUR_TABLE_ADDRESS,Base address DWORD aligned for the location in memory of the border colour table for the CDM" line.long 0xC "RGX_CR_TPU_BORDER_COLOUR_TABLE_CDM_1,Base address for the border colour table" hexmask.long 0xC 6.--31. 1. "Reserved_38,Reserved_38" newline hexmask.long.byte 0xC 0.--5. 1. "BORDER_COLOUR_TABLE_ADDRESS,Base address DWORD aligned for the location in memory of the border colour table for the CDM" repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) rgroup.long ($2+0x17B0)++0x3 line.long 0x0 "RGX_CR_TPU_PWR_NUMBER_OF_TEXELS_$1,Peformance counter associated with Power Monitoring." hexmask.long 0x0 0.--31. 1. "VALUE,Number of texels requested per clock" repeat.end group.long 0x17B8++0xF line.long 0x0 "RGX_CR_TPU_TAG_CTRL_0,Global control to TAG for the pixel data master" hexmask.long 0x0 4.--31. 1. "Reserved_4,Reserved_4" newline bitfld.long 0x0 3. "AF_RATIO_TRUNCATE_TO_INTEGER,0 current mode 1 clear the fractional part of the calculated AF ratio" "0,1" newline bitfld.long 0x0 2. "AF_RATIO_TRUNCATE_TO_HALF,0 current mode 1 truncate the fractional part of the calculated AF ratio to 0. 5" "0,1" newline bitfld.long 0x0 1. "AF_FILTERING_MODE,0 current mode 1 new mode." "0,1" newline bitfld.long 0x0 0. "YUV_CAM_INVALIDATE,When set will invalidate YUV CSC CAM to reset the CSC coefficients. It should be set when the TPU is not performing CSC." "0,1" line.long 0x4 "RGX_CR_TPU_TAG_CTRL_1,Global control to TAG for the pixel data master" hexmask.long 0x4 0.--31. 1. "Reserved_4,Reserved_4" line.long 0x8 "RGX_CR_TPU_MADD_CTRL_0,Global control to MADD for pixel data master" hexmask.long 0x8 2.--31. 1. "Reserved_2,Reserved_2" newline bitfld.long 0x8 1. "ASTC_ODD_SCALING_ENABLE,When set ASTC encoded texels use the odd U16->F16 scaling in the TF. When zero the usual scaling will be used in TF." "0,1" newline bitfld.long 0x8 0. "ASTC_MULTICYCLE_TF_FORCE_F16,When set ASTC encoded texels that are filtered over multiple cycles by the TF will be output from the MADD as F16." "0,1" line.long 0xC "RGX_CR_TPU_MADD_CTRL_1,Global control to MADD for pixel data master" hexmask.long 0xC 0.--31. 1. "Reserved_2,Reserved_2" group.long 0x17F0++0x7 line.long 0x0 "RGX_CR_TPU_BORDER_COLOUR_TABLE_TDM_0,Base address for the border colour table" hexmask.long 0x0 0.--31. 1. "BORDER_COLOUR_TABLE_ADDRESS,Base address DWORD aligned for the location in memory of the border colour table for the TDM" line.long 0x4 "RGX_CR_TPU_BORDER_COLOUR_TABLE_TDM_1,Base address for the border colour table" hexmask.long 0x4 6.--31. 1. "Reserved_38,Reserved_38" newline hexmask.long.byte 0x4 0.--5. 1. "BORDER_COLOUR_TABLE_ADDRESS,Base address DWORD aligned for the location in memory of the border colour table for the TDM" group.long 0x18C0++0x17 line.long 0x0 "RGX_CR_TPU_LODBIASREP_CMP_MANTISSA_MASK_PDM_0,Mask for comparing mantissa of f32 LOD Bias/Replace value for PPLOD speedup for the pixel data master" hexmask.long.word 0x0 23.--31. 1. "Reserved_23,Reserved_23" newline hexmask.long.tbyte 0x0 0.--22. 1. "LODBIASREP_CMP_MANTISSA_MASK,Mask for comparing mantissa of f32 LOD Bias/Replace value for PPLOD speedup" line.long 0x4 "RGX_CR_TPU_LODBIASREP_CMP_MANTISSA_MASK_PDM_1,Mask for comparing mantissa of f32 LOD Bias/Replace value for PPLOD speedup for the pixel data master" hexmask.long 0x4 0.--31. 1. "Reserved_23,Reserved_23" line.long 0x8 "RGX_CR_TPU_LODBIASREP_CMP_MANTISSA_MASK_VDM_0,Mask for comparing mantissa of f32 LOD Bias/Replace value for PPLOD speedup for the vertex data master" hexmask.long.word 0x8 23.--31. 1. "Reserved_23,Reserved_23" newline hexmask.long.tbyte 0x8 0.--22. 1. "LODBIASREP_CMP_MANTISSA_MASK,Mask for comparing mantissa of f32 LOD Bias/Replace value for PPLOD speedup" line.long 0xC "RGX_CR_TPU_LODBIASREP_CMP_MANTISSA_MASK_VDM_1,Mask for comparing mantissa of f32 LOD Bias/Replace value for PPLOD speedup for the vertex data master" hexmask.long 0xC 0.--31. 1. "Reserved_23,Reserved_23" line.long 0x10 "RGX_CR_TPU_LODBIASREP_CMP_MANTISSA_MASK_CDM_0,Mask for comparing mantissa of f32 LOD Bias/Replace value for PPLOD speedup for the compute data master" hexmask.long.word 0x10 23.--31. 1. "Reserved_23,Reserved_23" newline hexmask.long.tbyte 0x10 0.--22. 1. "LODBIASREP_CMP_MANTISSA_MASK,Mask for comparing mantissa of f32 LOD Bias/Replace value for PPLOD speedup" line.long 0x14 "RGX_CR_TPU_LODBIASREP_CMP_MANTISSA_MASK_CDM_1,Mask for comparing mantissa of f32 LOD Bias/Replace value for PPLOD speedup for the compute data master" hexmask.long 0x14 0.--31. 1. "Reserved_23,Reserved_23" group.long 0x18E0++0x7 line.long 0x0 "RGX_CR_TPU_LODBIASREP_CMP_MANTISSA_MASK_TDM_0,Mask for comparing mantissa of f32 LOD Bias/Replace value for PPLOD speedup for the fast render data master" hexmask.long.word 0x0 23.--31. 1. "Reserved_23,Reserved_23" newline hexmask.long.tbyte 0x0 0.--22. 1. "LODBIASREP_CMP_MANTISSA_MASK,Mask for comparing mantissa of f32 LOD Bias/Replace value for PPLOD speedup" line.long 0x4 "RGX_CR_TPU_LODBIASREP_CMP_MANTISSA_MASK_TDM_1,Mask for comparing mantissa of f32 LOD Bias/Replace value for PPLOD speedup for the fast render data master" hexmask.long 0x4 0.--31. 1. "Reserved_23,Reserved_23" rgroup.long 0x2000++0xF line.long 0x0 "RGX_CR_PM_TA_MMUPAGE_STATUS_0,RGX_CR_PM_TA_MMUPAGE_STATUS_0" hexmask.long.word 0x0 22.--31. 1. "Reserved_22,Reserved_22" newline hexmask.long.tbyte 0x0 0.--21. 1. "OP,MMU pages(4KB) counter @ the TA context" line.long 0x4 "RGX_CR_PM_TA_MMUPAGE_STATUS_1,RGX_CR_PM_TA_MMUPAGE_STATUS_1" hexmask.long 0x4 0.--31. 1. "Reserved_22,Reserved_22" line.long 0x8 "RGX_CR_PM_3D_MMUPAGE_STATUS_0,RGX_CR_PM_3D_MMUPAGE_STATUS_0" hexmask.long.word 0x8 22.--31. 1. "Reserved_22,Reserved_22" newline hexmask.long.tbyte 0x8 0.--21. 1. "OP,MMU pages(4KB) counter @ the 3D context" line.long 0xC "RGX_CR_PM_3D_MMUPAGE_STATUS_1,RGX_CR_PM_3D_MMUPAGE_STATUS_1" hexmask.long 0xC 0.--31. 1. "Reserved_22,Reserved_22" group.long 0x2010++0xF line.long 0x0 "RGX_CR_PM_MMU_STACK_POLICY_0,This register enables the PM to drain pages for MMU from the dedicated mmu free list stack. (no-pagable) It is static register which can not be changed in the run-time." hexmask.long 0x0 1.--31. 1. "Reserved_1,Reserved_1" newline bitfld.long 0x0 0. "OP,when this bit is '1' PM will try to drain pages from the dedicated mmu free list stack" "0,1" line.long 0x4 "RGX_CR_PM_MMU_STACK_POLICY_1,This register enables the PM to drain pages for MMU from the dedicated mmu free list stack. (no-pagable) It is static register which can not be changed in the run-time." hexmask.long 0x4 0.--31. 1. "Reserved_1,Reserved_1" line.long 0x8 "RGX_CR_PM_TA_MMU_FSTACK_BASE_0,Effective on loading of the MMU TA free list loading . this register defines the base address of the mmu free list stack being referenced during TA processing." hexmask.long 0x8 4.--31. 1. "ADDR,1TB Addressable 128 bits aligned Base Address for MMU TA free list stack" newline hexmask.long.byte 0x8 0.--3. 1. "Reserved_0,Reserved_0" line.long 0xC "RGX_CR_PM_TA_MMU_FSTACK_BASE_1,Effective on loading of the MMU TA free list loading . this register defines the base address of the mmu free list stack being referenced during TA processing." hexmask.long.tbyte 0xC 8.--31. 1. "Reserved_40,Reserved_40" newline hexmask.long.byte 0xC 0.--7. 1. "ADDR,1TB Addressable 128 bits aligned Base Address for MMU TA free list stack" rgroup.long 0x2020++0x7 line.long 0x0 "RGX_CR_PM_TA_MMU_FSTACK_STATUS_0,Note: this is the pointer pointing to the MMU TA free stack top. (4KB page pointer)" hexmask.long.word 0x0 22.--31. 1. "Reserved_22,Reserved_22" newline hexmask.long.tbyte 0x0 0.--21. 1. "TOP,This status register indicated the mmu ta context free list pointer status." line.long 0x4 "RGX_CR_PM_TA_MMU_FSTACK_STATUS_1,Note: this is the pointer pointing to the MMU TA free stack top. (4KB page pointer)" hexmask.long 0x4 0.--31. 1. "Reserved_22,Reserved_22" group.long 0x2028++0x1F line.long 0x0 "RGX_CR_PM_TA_MMU_FSTACK_0,Defines the start of the stack pointer regarding to the MMU free list stack" hexmask.long.word 0x0 22.--31. 1. "Reserved_22,Reserved_22" newline hexmask.long.tbyte 0x0 0.--21. 1. "STARTOF_TOP,This register defines the head pointer of the mmu free list in terms of 4K free pages in the free list stack effective on a loading of the MMU TA free list" line.long 0x4 "RGX_CR_PM_TA_MMU_FSTACK_1,Defines the start of the stack pointer regarding to the MMU free list stack" hexmask.long 0x4 0.--31. 1. "Reserved_22,Reserved_22" line.long 0x8 "RGX_CR_PM_START_OF_MMU_TACONTEXT_0,RGX_CR_PM_START_OF_MMU_TACONTEXT_0" hexmask.long.word 0x8 22.--31. 1. "Reserved_22,Reserved_22" newline hexmask.long.tbyte 0x8 0.--21. 1. "ALLOCATED_MMUPAGE,Start of MMU Freelists TA pages(4KB) on loading of the MMU TA context" line.long 0xC "RGX_CR_PM_START_OF_MMU_TACONTEXT_1,RGX_CR_PM_START_OF_MMU_TACONTEXT_1" hexmask.long 0xC 0.--31. 1. "Reserved_22,Reserved_22" line.long 0x10 "RGX_CR_PM_TASK_TA_MMU_FSTACK_FREE_LOAD_0,RGX_CR_PM_TASK_TA_MMU_FSTACK_FREE_LOAD_0" hexmask.long 0x10 1.--31. 1. "Reserved_1,Reserved_1" newline bitfld.long 0x10 0. "PENDING,A write into this register will cause the TA MMU free list context to be loaded from the relevant configuration registers" "0,1" line.long 0x14 "RGX_CR_PM_TASK_TA_MMU_FSTACK_FREE_LOAD_1,RGX_CR_PM_TASK_TA_MMU_FSTACK_FREE_LOAD_1" hexmask.long 0x14 0.--31. 1. "Reserved_1,Reserved_1" line.long 0x18 "RGX_CR_PM_3D_MMU_FSTACK_BASE_0,Effective on loading of the MMU 3D free list loading . this register defines the base address of the mmu free list stack being referenced during 3D processing." hexmask.long 0x18 4.--31. 1. "ADDR,1TB Addressable 128 bits aligned Base Address for MMU TA free list stack" newline hexmask.long.byte 0x18 0.--3. 1. "Reserved_0,Reserved_0" line.long 0x1C "RGX_CR_PM_3D_MMU_FSTACK_BASE_1,Effective on loading of the MMU 3D free list loading . this register defines the base address of the mmu free list stack being referenced during 3D processing." hexmask.long.tbyte 0x1C 8.--31. 1. "Reserved_40,Reserved_40" newline hexmask.long.byte 0x1C 0.--7. 1. "ADDR,1TB Addressable 128 bits aligned Base Address for MMU TA free list stack" rgroup.long 0x2048++0x7 line.long 0x0 "RGX_CR_PM_3D_MMU_FSTACK_STATUS_0,Note: this is the pointer pointing to the MMU TA free stack top. (4KB page pointer)" hexmask.long.word 0x0 22.--31. 1. "Reserved_22,Reserved_22" newline hexmask.long.tbyte 0x0 0.--21. 1. "TOP,This status register indicated the mmu ta context free list pointer status." line.long 0x4 "RGX_CR_PM_3D_MMU_FSTACK_STATUS_1,Note: this is the pointer pointing to the MMU TA free stack top. (4KB page pointer)" hexmask.long 0x4 0.--31. 1. "Reserved_22,Reserved_22" group.long 0x2050++0x17 line.long 0x0 "RGX_CR_PM_3D_MMU_FSTACK_0,Defines the start of the stack pointer regarding to the MMU free list stack Effective on a 3D MMU fstack load" hexmask.long.word 0x0 22.--31. 1. "Reserved_22,Reserved_22" newline hexmask.long.tbyte 0x0 0.--21. 1. "STARTOF_TOP,This register defines the head pointer of the mmu free list in terms of 4K free pages in the free list stack effective on a loading of the MMU TA free list" line.long 0x4 "RGX_CR_PM_3D_MMU_FSTACK_1,Defines the start of the stack pointer regarding to the MMU free list stack Effective on a 3D MMU fstack load" hexmask.long 0x4 0.--31. 1. "Reserved_22,Reserved_22" line.long 0x8 "RGX_CR_PM_START_OF_MMU_3DCONTEXT_0,Effective on a 3D MMU fstack load" hexmask.long.word 0x8 22.--31. 1. "Reserved_22,Reserved_22" newline hexmask.long.tbyte 0x8 0.--21. 1. "ALLOCATED_MMUPAGE,Start of MMU Freelists 3D pages(4KB) on loading of the MMU TA context" line.long 0xC "RGX_CR_PM_START_OF_MMU_3DCONTEXT_1,Effective on a 3D MMU fstack load" hexmask.long 0xC 0.--31. 1. "Reserved_22,Reserved_22" line.long 0x10 "RGX_CR_PM_TASK_3D_MMU_FSTACK_FREE_LOAD_0,RGX_CR_PM_TASK_3D_MMU_FSTACK_FREE_LOAD_0" hexmask.long 0x10 1.--31. 1. "Reserved_1,Reserved_1" newline bitfld.long 0x10 0. "PENDING,A write into this register will cause the 3D MMU free list context to be loaded from the relevant configuration registers" "0,1" line.long 0x14 "RGX_CR_PM_TASK_3D_MMU_FSTACK_FREE_LOAD_1,RGX_CR_PM_TASK_3D_MMU_FSTACK_FREE_LOAD_1" hexmask.long 0x14 0.--31. 1. "Reserved_1,Reserved_1" rgroup.long 0x2068++0xF line.long 0x0 "RGX_CR_PM_MMUSTACK_LOCK_STATUS_0,RGX_CR_PM_MMUSTACK_LOCK_STATUS_0" hexmask.long 0x0 2.--31. 1. "Reserved_2,Reserved_2" newline bitfld.long 0x0 1. "TD,Bit 1: 3D MMU free list Lock Status. 0 idle/ 1 used" "0,1" newline bitfld.long 0x0 0. "TA,Bit 0: TA MMU free list Lock Status. 0 idle/ 1 used." "TA MMU free list Lock Status,?" line.long 0x4 "RGX_CR_PM_MMUSTACK_LOCK_STATUS_1,RGX_CR_PM_MMUSTACK_LOCK_STATUS_1" hexmask.long 0x4 0.--31. 1. "Reserved_2,Reserved_2" line.long 0x8 "RGX_CR_PM_MMUSTACK_LOCK_OWNER_0,RGX_CR_PM_MMUSTACK_LOCK_OWNER_0" hexmask.long 0x8 2.--31. 1. "Reserved_2,Reserved_2" newline bitfld.long 0x8 1. "TD,Bit 1 :3D free list Lock owner. 0 PMA / 1 PMD" "0,1" newline bitfld.long 0x8 0. "TA,Bit 0: TA free list Lock Owner. 0 PMA / 1 PMD." "TA free list Lock Owner,?" line.long 0xC "RGX_CR_PM_MMUSTACK_LOCK_OWNER_1,RGX_CR_PM_MMUSTACK_LOCK_OWNER_1" hexmask.long 0xC 0.--31. 1. "Reserved_2,Reserved_2" group.long 0x2078++0xF line.long 0x0 "RGX_CR_PM_3D_UFSTACK_BASE_0,Effective on load of the Unified Free List Stack. this register defines the base address of the unified free list stack being referenced." hexmask.long 0x0 4.--31. 1. "ADDR,1TB Addressable 128 bits aligned Base Address for unified free list stack base address" newline hexmask.long.byte 0x0 0.--3. 1. "Reserved_0,Reserved_0" line.long 0x4 "RGX_CR_PM_3D_UFSTACK_BASE_1,Effective on load of the Unified Free List Stack. this register defines the base address of the unified free list stack being referenced." hexmask.long.tbyte 0x4 8.--31. 1. "Reserved_40,Reserved_40" newline hexmask.long.byte 0x4 0.--7. 1. "ADDR,1TB Addressable 128 bits aligned Base Address for unified free list stack base address" line.long 0x8 "RGX_CR_PM_3D_UFSTACK_0,Note: each 16GB 4KB addressable page (22 bits) is rounded to dword aligned Effective on load of the Unified Free List Stack." hexmask.long.word 0x8 22.--31. 1. "Reserved_22,Reserved_22" newline hexmask.long.tbyte 0x8 0.--21. 1. "STARTOF_TOP,This register defines the unified free list stack pointer @ loading time. It is 4K page." line.long 0xC "RGX_CR_PM_3D_UFSTACK_1,Note: each 16GB 4KB addressable page (22 bits) is rounded to dword aligned Effective on load of the Unified Free List Stack." hexmask.long 0xC 0.--31. 1. "Reserved_22,Reserved_22" rgroup.long 0x2088++0x7 line.long 0x0 "RGX_CR_PM_3D_UFSTACK_STATUS_0,Note: this is the pointer pointing to the ufstack top. (4KB page pointer)" hexmask.long.word 0x0 22.--31. 1. "Reserved_22,Reserved_22" newline hexmask.long.tbyte 0x0 0.--21. 1. "TOP,This status register indicated the unified free list stack pointer status." line.long 0x4 "RGX_CR_PM_3D_UFSTACK_STATUS_1,Note: this is the pointer pointing to the ufstack top. (4KB page pointer)" hexmask.long 0x4 0.--31. 1. "Reserved_22,Reserved_22" repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) group.long ($2+0x2090)++0x3 line.long 0x0 "RGX_CR_PM_START_OF_3D_UFSTACK_$1,Effective on load of the Unified Free List Stack." hexmask.long.word 0x0 22.--31. 1. "Reserved_22,Reserved_22" newline hexmask.long.tbyte 0x0 0.--21. 1. "ALLOCATED_PAGE,Start of TA pages(4KB) on loading of the Unified Free List Stack" repeat.end rgroup.long 0x2098++0xF line.long 0x0 "RGX_CR_PM_3D_UFSTACK_PAGE_STATUS_0,RGX_CR_PM_3D_UFSTACK_PAGE_STATUS_0" hexmask.long.word 0x0 22.--31. 1. "Reserved_22,Reserved_22" newline hexmask.long.tbyte 0x0 0.--21. 1. "OP,The number of Unified Free list pages currently allocated for the TA" line.long 0x4 "RGX_CR_PM_3D_UFSTACK_PAGE_STATUS_1,RGX_CR_PM_3D_UFSTACK_PAGE_STATUS_1" hexmask.long 0x4 0.--31. 1. "Reserved_22,Reserved_22" line.long 0x8 "RGX_CR_PM_3D_UFSTACK_MMUPAGE_STATUS_0,RGX_CR_PM_3D_UFSTACK_MMUPAGE_STATUS_0" hexmask.long.word 0x8 22.--31. 1. "Reserved_22,Reserved_22" newline hexmask.long.tbyte 0x8 0.--21. 1. "OP,The number of Unified Free list pages currently allocated for the MMU" line.long 0xC "RGX_CR_PM_3D_UFSTACK_MMUPAGE_STATUS_1,RGX_CR_PM_3D_UFSTACK_MMUPAGE_STATUS_1" hexmask.long 0xC 0.--31. 1. "Reserved_22,Reserved_22" group.long 0x20A8++0x1F line.long 0x0 "RGX_CR_PM_TASK_3D_UFSTACK_LOAD_0,RGX_CR_PM_TASK_3D_UFSTACK_LOAD_0" hexmask.long 0x0 1.--31. 1. "Reserved_1,Reserved_1" newline bitfld.long 0x0 0. "PENDING,pending status register corresponding to the ustack loading operation it will become '1' when this pm_task_ufstack_load being written and deassert until the operation is done" "0,1" line.long 0x4 "RGX_CR_PM_TASK_3D_UFSTACK_LOAD_1,RGX_CR_PM_TASK_3D_UFSTACK_LOAD_1" hexmask.long 0x4 0.--31. 1. "Reserved_1,Reserved_1" line.long 0x8 "RGX_CR_PM_TASK_TA_UFSTACK_LOAD_0,RGX_CR_PM_TASK_TA_UFSTACK_LOAD_0" hexmask.long 0x8 1.--31. 1. "Reserved_1,Reserved_1" newline bitfld.long 0x8 0. "PENDING,pending status register corresponding to the ustack loading operation it will become '1' when this pm_task_ufstack_load being written and deassert until the operation is done" "0,1" line.long 0xC "RGX_CR_PM_TASK_TA_UFSTACK_LOAD_1,RGX_CR_PM_TASK_TA_UFSTACK_LOAD_1" hexmask.long 0xC 0.--31. 1. "Reserved_1,Reserved_1" line.long 0x10 "RGX_CR_PM_TA_UFSTACK_BASE_0,Effective on load of the Unified Free List Stack. this register defines the base address of the unified free list stack being referenced." hexmask.long 0x10 4.--31. 1. "ADDR,1TB Addressable 128 bits aligned Base Address for unified free list stack base address" newline hexmask.long.byte 0x10 0.--3. 1. "Reserved_0,Reserved_0" line.long 0x14 "RGX_CR_PM_TA_UFSTACK_BASE_1,Effective on load of the Unified Free List Stack. this register defines the base address of the unified free list stack being referenced." hexmask.long.tbyte 0x14 8.--31. 1. "Reserved_40,Reserved_40" newline hexmask.long.byte 0x14 0.--7. 1. "ADDR,1TB Addressable 128 bits aligned Base Address for unified free list stack base address" line.long 0x18 "RGX_CR_PM_TA_UFSTACK_0,Note: each 16GB 4KB addressable page (22 bits) is rounded to dword aligned Effective on the loading of the Unified Free List Stack." hexmask.long.word 0x18 22.--31. 1. "Reserved_22,Reserved_22" newline hexmask.long.tbyte 0x18 0.--21. 1. "STARTOF_TOP,This register defines the unified free list stack pointer @ loading time. It is 4K page." line.long 0x1C "RGX_CR_PM_TA_UFSTACK_1,Note: each 16GB 4KB addressable page (22 bits) is rounded to dword aligned Effective on the loading of the Unified Free List Stack." hexmask.long 0x1C 0.--31. 1. "Reserved_22,Reserved_22" rgroup.long 0x20C8++0x7 line.long 0x0 "RGX_CR_PM_TA_UFSTACK_STATUS_0,Note: this is the pointer pointing to the ufstack top. (4KB page pointer)" hexmask.long.word 0x0 22.--31. 1. "Reserved_22,Reserved_22" newline hexmask.long.tbyte 0x0 0.--21. 1. "TOP,This status register indicated the unified free list stack pointer status." line.long 0x4 "RGX_CR_PM_TA_UFSTACK_STATUS_1,Note: this is the pointer pointing to the ufstack top. (4KB page pointer)" hexmask.long 0x4 0.--31. 1. "Reserved_22,Reserved_22" repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) group.long ($2+0x20D0)++0x3 line.long 0x0 "RGX_CR_PM_START_OF_TA_UFSTACK_$1,RGX_CR_PM_START_OF_TA_UFSTACK_0" hexmask.long.word 0x0 22.--31. 1. "Reserved_22,Reserved_22" newline hexmask.long.tbyte 0x0 0.--21. 1. "ALLOCATED_PAGE,Start of TA pages(4KB) on loading of the Unified Free List Stack" repeat.end rgroup.long 0x20D8++0x1F line.long 0x0 "RGX_CR_PM_TA_UFSTACK_PAGE_STATUS_0,RGX_CR_PM_TA_UFSTACK_PAGE_STATUS_0" hexmask.long.word 0x0 22.--31. 1. "Reserved_22,Reserved_22" newline hexmask.long.tbyte 0x0 0.--21. 1. "OP,The number of Unified Free list pages currently allocated for the TA" line.long 0x4 "RGX_CR_PM_TA_UFSTACK_PAGE_STATUS_1,RGX_CR_PM_TA_UFSTACK_PAGE_STATUS_1" hexmask.long 0x4 0.--31. 1. "Reserved_22,Reserved_22" line.long 0x8 "RGX_CR_PM_TA_UFSTACK_MMUPAGE_STATUS_0,RGX_CR_PM_TA_UFSTACK_MMUPAGE_STATUS_0" hexmask.long.word 0x8 22.--31. 1. "Reserved_22,Reserved_22" newline hexmask.long.tbyte 0x8 0.--21. 1. "OP,The number of Unified Free list pages currently allocated for the MMU" line.long 0xC "RGX_CR_PM_TA_UFSTACK_MMUPAGE_STATUS_1,RGX_CR_PM_TA_UFSTACK_MMUPAGE_STATUS_1" hexmask.long 0xC 0.--31. 1. "Reserved_22,Reserved_22" line.long 0x10 "RGX_CR_PM_UFSTACK_LOCK_STATUS_0,In rogue architecture. there is a unified free list whereby shared across multiple context. This lock status indicating the stack owner at the time being. Note PMA and PMD can not acquire the lock @ the same time" hexmask.long 0x10 2.--31. 1. "Reserved_2,Reserved_2" newline bitfld.long 0x10 1. "PMD,Bit 1: Page DeAllocation Manger is grabing the lock. 0:idle/ 1 used." "idle/ 1 used,Page DeAllocation Manger is grabing the lock" newline bitfld.long 0x10 0. "PMA,Bit 0: Page Allocation Manger is grabing the lock. 0:idle/ 1 used." "idle/ 1 used,?" line.long 0x14 "RGX_CR_PM_UFSTACK_LOCK_STATUS_1,In rogue architecture. there is a unified free list whereby shared across multiple context. This lock status indicating the stack owner at the time being. Note PMA and PMD can not acquire the lock @ the same time" hexmask.long 0x14 0.--31. 1. "Reserved_2,Reserved_2" line.long 0x18 "RGX_CR_PM_UFSTACK_LOCK_OWNER_0,RGX_CR_PM_UFSTACK_LOCK_OWNER_0" hexmask.long 0x18 2.--31. 1. "Reserved_2,Reserved_2" newline bitfld.long 0x18 1. "TD,Bit 1 :3D free list Lock owner. 0 PMA / 1 PMD" "0,1" newline bitfld.long 0x18 0. "TA,Bit 0: TA free list Lock Owner. 0 PMA / 1 PMD." "TA free list Lock Owner,?" line.long 0x1C "RGX_CR_PM_UFSTACK_LOCK_OWNER_1,RGX_CR_PM_UFSTACK_LOCK_OWNER_1" hexmask.long 0x1C 0.--31. 1. "Reserved_2,Reserved_2" group.long 0x20F8++0x1F line.long 0x0 "RGX_CR_PM_UFSTACK_POLICY_0,This register enables the PM to drain pages from the unified free list stack It is a static configuration register" hexmask.long 0x0 1.--31. 1. "Reserved_1,Reserved_1" newline bitfld.long 0x0 0. "OP,when this bit is '1' PM will try to drain pages from the unified free list stack as long as the ta free list do not have enough pages for the allocation" "0,1" line.long 0x4 "RGX_CR_PM_UFSTACK_POLICY_1,This register enables the PM to drain pages from the unified free list stack It is a static configuration register" hexmask.long 0x4 0.--31. 1. "Reserved_1,Reserved_1" line.long 0x8 "RGX_CR_PM_VFP_TRAN_EN_0,This register enables the PM to another level of transfrom which is from Virtial Page to VirtualPhysical Page number" hexmask.long 0x8 1.--31. 1. "Reserved_1,Reserved_1" newline bitfld.long 0x8 0. "OP,when this bit is '1' PM will try to another level of lookup between virtual page and the virtual physical page" "0,1" line.long 0xC "RGX_CR_PM_VFP_TRAN_EN_1,This register enables the PM to another level of transfrom which is from Virtial Page to VirtualPhysical Page number" hexmask.long 0xC 0.--31. 1. "Reserved_1,Reserved_1" line.long 0x10 "RGX_CR_PM_TA_VFP_TABLE_BASE_0,Effective on loading TA context. this register defines the base address of the virtual-physical page table during TA processing." hexmask.long 0x10 4.--31. 1. "ADDR,1TB Addressable 128 bits aligned Base Address for TA context page tables in the DPM module" newline hexmask.long.byte 0x10 0.--3. 1. "Reserved_0,Reserved_0" line.long 0x14 "RGX_CR_PM_TA_VFP_TABLE_BASE_1,Effective on loading TA context. this register defines the base address of the virtual-physical page table during TA processing." hexmask.long.tbyte 0x14 8.--31. 1. "Reserved_40,Reserved_40" newline hexmask.long.byte 0x14 0.--7. 1. "ADDR,1TB Addressable 128 bits aligned Base Address for TA context page tables in the DPM module" line.long 0x18 "RGX_CR_PM_3D_VFP_TABLE_BASE_0,Effective on loading 3D context. this register defines the base address of the virtual-physical page table during 3D processing." hexmask.long 0x18 4.--31. 1. "ADDR,1TB Addressable 128 bits aligned Base Address for 3D context page tables in the DPM module" newline hexmask.long.byte 0x18 0.--3. 1. "Reserved_0,Reserved_0" line.long 0x1C "RGX_CR_PM_3D_VFP_TABLE_BASE_1,Effective on loading 3D context. this register defines the base address of the virtual-physical page table during 3D processing." hexmask.long.tbyte 0x1C 8.--31. 1. "Reserved_40,Reserved_40" newline hexmask.long.byte 0x1C 0.--7. 1. "ADDR,1TB Addressable 128 bits aligned Base Address for 3D context page tables in the DPM module" wgroup.long 0x2600++0x7 line.long 0x0 "RGX_CR_TDM_START_0,A write of '1' to this register starts the 2D Data Master (TDM) reading the control stream contained in the circular buffer pointed to by TDM_CB_BASE_ADDR" hexmask.long 0x0 1.--31. 1. "Reserved_1,Reserved_1" newline bitfld.long 0x0 0. "PULSE,Start TDM" "0,1" line.long 0x4 "RGX_CR_TDM_START_1,A write of '1' to this register starts the 2D Data Master (TDM) reading the control stream contained in the circular buffer pointed to by TDM_CB_BASE_ADDR" hexmask.long 0x4 0.--31. 1. "Reserved_1,Reserved_1" group.long 0x2608++0x27 line.long 0x0 "RGX_CR_TDM_CB_BASE_0,TDM Circular Buffer base dddress" hexmask.long.tbyte 0x0 12.--31. 1. "ADDR,1 TB range 4KB aligned base address for TDM control stream circular buffer" newline hexmask.long.word 0x0 0.--11. 1. "Reserved_0,Reserved_0" line.long 0x4 "RGX_CR_TDM_CB_BASE_1,TDM Circular Buffer base dddress" hexmask.long.tbyte 0x4 8.--31. 1. "Reserved_40,Reserved_40" newline hexmask.long.byte 0x4 0.--7. 1. "ADDR,1 TB range 4KB aligned base address for TDM control stream circular buffer" line.long 0x8 "RGX_CR_TDM_CB_0,TDM Circular Buffer Size in 256-bit words" hexmask.long.word 0x8 20.--31. 1. "Reserved_20,Reserved_20" newline hexmask.long.word 0x8 5.--19. 1. "SIZE,1MB range 256-bit granular TDM Circular Buffer Size" newline hexmask.long.byte 0x8 0.--4. 1. "Reserved_0,Reserved_0" line.long 0xC "RGX_CR_TDM_CB_1,TDM Circular Buffer Size in 256-bit words" hexmask.long 0xC 0.--31. 1. "Reserved_20,Reserved_20" line.long 0x10 "RGX_CR_TDM_CB_QUEUE_0,TDM Circular Buffer Queue Control Base Address" hexmask.long 0x10 5.--31. 1. "CTRL_BASE_ADDR,1 TB range 256-bit aligned base address for TDM queue control structure" newline hexmask.long.byte 0x10 0.--4. 1. "Reserved_0,Reserved_0" line.long 0x14 "RGX_CR_TDM_CB_QUEUE_1,TDM Circular Buffer Queue Control Base Address" hexmask.long.tbyte 0x14 8.--31. 1. "Reserved_40,Reserved_40" newline hexmask.long.byte 0x14 0.--7. 1. "CTRL_BASE_ADDR,1 TB range 256-bit aligned base address for TDM queue control structure" line.long 0x18 "RGX_CR_TDM_CB_WRITE_POINTER_GUARD_0,TDM Circular Buffer Write Pointer Guard Size. TDM will refresh it's local copy of the Queue Control Write Pointer from memory when the Read Pointer is within the Guard Size of the Write Pointer." hexmask.long.word 0x18 20.--31. 1. "Reserved_20,Reserved_20" newline hexmask.long.word 0x18 5.--19. 1. "SIZE,1MB range 256-bit granular Write Pointer Guard Size" newline hexmask.long.byte 0x18 0.--4. 1. "Reserved_0,Reserved_0" line.long 0x1C "RGX_CR_TDM_CB_WRITE_POINTER_GUARD_1,TDM Circular Buffer Write Pointer Guard Size. TDM will refresh it's local copy of the Queue Control Write Pointer from memory when the Read Pointer is within the Guard Size of the Write Pointer." hexmask.long 0x1C 0.--31. 1. "Reserved_20,Reserved_20" line.long 0x20 "RGX_CR_TDM_CB_READ_POINTER_UPDATE_0,TDM Circular Buffer Read Pointer Update Frequency. the TDM will update the Queue Control Read Pointer value in memory whenever the Read Pointer has moved by this amount since the last memory write." hexmask.long.word 0x20 20.--31. 1. "Reserved_20,Reserved_20" newline hexmask.long.word 0x20 5.--19. 1. "FREQUENCY,1MB range 256-bit granular Read Pointer Update Frequency" newline hexmask.long.byte 0x20 0.--4. 1. "Reserved_0,Reserved_0" line.long 0x24 "RGX_CR_TDM_CB_READ_POINTER_UPDATE_1,TDM Circular Buffer Read Pointer Update Frequency. the TDM will update the Queue Control Read Pointer value in memory whenever the Read Pointer has moved by this amount since the last memory write." hexmask.long 0x24 0.--31. 1. "Reserved_20,Reserved_20" rgroup.long 0x2630++0x7 line.long 0x0 "RGX_CR_TDM_CB_READ_0,TDM Circular Buffer Read Pointer - current working position of TDM within 2D circular buffer. updated on a BLIT granularity" hexmask.long.word 0x0 20.--31. 1. "Reserved_20,Reserved_20" newline hexmask.long.tbyte 0x0 2.--19. 1. "POINTER,1MB range 32-bit granular Read Pointer" newline bitfld.long 0x0 0.--1. "Reserved_0,Reserved_0" "0,1,2,3" line.long 0x4 "RGX_CR_TDM_CB_READ_1,TDM Circular Buffer Read Pointer - current working position of TDM within 2D circular buffer. updated on a BLIT granularity" hexmask.long 0x4 0.--31. 1. "Reserved_20,Reserved_20" wgroup.long 0x2638++0xF line.long 0x0 "RGX_CR_TDM_RESUME_0,A write of '1' to this register resumes the TDM after 2D circular buffer empty failures." hexmask.long 0x0 1.--31. 1. "Reserved_1,Reserved_1" newline bitfld.long 0x0 0. "PULSE,Resume TDM" "0,1" line.long 0x4 "RGX_CR_TDM_RESUME_1,A write of '1' to this register resumes the TDM after 2D circular buffer empty failures." hexmask.long 0x4 0.--31. 1. "Reserved_1,Reserved_1" line.long 0x8 "RGX_CR_TDM_CONTEXT_STORE_0,Writing '1' to this register starts the TDM context store operation." hexmask.long 0x8 1.--31. 1. "Reserved_1,Reserved_1" newline bitfld.long 0x8 0. "PULSE,PULSE" "0,1" line.long 0xC "RGX_CR_TDM_CONTEXT_STORE_1,Writing '1' to this register starts the TDM context store operation." hexmask.long 0xC 0.--31. 1. "Reserved_1,Reserved_1" group.long 0x2648++0x7 line.long 0x0 "RGX_CR_TDM_CONTEXT_STATE_BASE_0,The base address in external memory of the TDM's context state buffer. to which it will store its snapshot state on a context store and from which it will reload on a TDM start pulse." hexmask.long 0x0 6.--31. 1. "ADDR,1TB range 512-bit aligned base address" newline hexmask.long.byte 0x0 0.--5. 1. "Reserved_0,Reserved_0" line.long 0x4 "RGX_CR_TDM_CONTEXT_STATE_BASE_1,The base address in external memory of the TDM's context state buffer. to which it will store its snapshot state on a context store and from which it will reload on a TDM start pulse." hexmask.long.tbyte 0x4 8.--31. 1. "Reserved_40,Reserved_40" newline hexmask.long.byte 0x4 0.--7. 1. "ADDR,1TB range 512-bit aligned base address" repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) rgroup.long ($2+0x2650)++0x3 line.long 0x0 "RGX_CR_TDM_FENCE_$1,TDM fence counters" hexmask.long 0x0 0.--31. 1. "COUNT,Count of the number of fence received reset to 0 on TDM_START_PULSE" repeat.end group.long 0x2658++0x7 line.long 0x0 "RGX_CR_TDM_YUV_CSC_COEFFICIENTS_0,Base address for the YUV CSC set of coefficients stored in memory for pixel data master" hexmask.long 0x0 0.--31. 1. "COEFFICIENTS,Base address DWORD aligned for the location in memory of the CSC coefficients" line.long 0x4 "RGX_CR_TDM_YUV_CSC_COEFFICIENTS_1,Base address for the YUV CSC set of coefficients stored in memory for pixel data master" hexmask.long 0x4 6.--31. 1. "Reserved_38,Reserved_38" newline hexmask.long.byte 0x4 0.--5. 1. "COEFFICIENTS,Base address DWORD aligned for the location in memory of the CSC coefficients" group.long 0x2678++0x7 line.long 0x0 "RGX_CR_TDM_WORKLOAD_0,TDM workload priority policy." hexmask.long 0x0 2.--31. 1. "Reserved_2,Reserved_2" newline bitfld.long 0x0 0.--1. "PRIORITY,0: Equal priority; 1: 3D has priority; 2: TDM has priority; 3: Reserved" "Equal priority;,?,TDM has priority;,Reserved" line.long 0x4 "RGX_CR_TDM_WORKLOAD_1,TDM workload priority policy." hexmask.long 0x4 0.--31. 1. "Reserved_2,Reserved_2" group.long 0x3800++0x7 line.long 0x0 "RGX_CR_SLC_CTRL_MISC_0,SLC control registers" hexmask.long.byte 0x0 24.--31. 1. "Reserved_24,Reserved_24" newline hexmask.long.byte 0x0 16.--23. 1. "ADDR_DECODE_MODE,Address decoding used to determine cache bank from the address: 0x00 = Bit 6 = 64 byte 0x01 = Bit 7 = 128 byte 0x10 = Simple XOR based address hash 1 see SLC TRM 0x11 = Simple XOR based address hash 2 see SLC TRM 0x20 = PVR address.." newline hexmask.long.byte 0x0 9.--15. 1. "Reserved_9,Reserved_9" newline bitfld.long 0x0 8. "PAUSE,Pause the SLC" "0,1" newline hexmask.long.byte 0x0 4.--7. 1. "Reserved_4,Reserved_4" newline bitfld.long 0x0 3. "RESP_PRIORITY,Priority setting between Hit and Miss on return response. Default is round robin and set to 1 if miss needs priority over hit" "0,1" newline bitfld.long 0x0 2. "ENABLE_LINE_USE_LIMIT,Enable the use of cache line limits" "0,1" newline bitfld.long 0x0 1. "ENABLE_PSG_HAZARD_CHECK,Enable the hazard checking of PSG writes only turn off if strict write ordering is guaranteed in the memory fabric" "0,1" newline bitfld.long 0x0 0. "BYPASS_BURST_COMBINER,Disable the burst combiner on the external memory interface" "0,1" line.long 0x4 "RGX_CR_SLC_CTRL_MISC_1,SLC control registers" hexmask.long 0x4 0.--31. 1. "SCRAMBLE_BITS,Pattern of bits used to determine the Cache Bank in Address Decode mode 0x21. The actual Cache Bank to use is determined by indexing into the 32 Scramble Bits using the 5 LSB's of the Hash result and then XORing this with Bit 6 of the.." wgroup.long 0x3808++0x17 line.long 0x0 "RGX_CR_SLC_CTRL_INVAL_0,SLC Invalidate control. Note that per Data Master operations only invalidate entries that have been referenced solely by the specified Data Master. any cache lines referenced by multiple Data Masters will not be affected by a per.." bitfld.long 0x0 31. "LAZY,Advanced mode of operation whereby other requestors are not blocked whilst the Invalidate is in progress" "0,1" newline hexmask.long.tbyte 0x0 9.--30. 1. "Reserved_9,Reserved_9" newline bitfld.long 0x0 8. "DM_FRC,When set invalidate all SLC entries referenced solely by the FRC Video Core (Optional feature)" "0,1" newline bitfld.long 0x0 7. "DM_VXE,When set invalidate all SLC entries referenced solely by the VXE Video Core (Optional feature)" "0,1" newline bitfld.long 0x0 6. "DM_VXD,When set invalidate all SLC entries referenced solely by the VXD Video Core (Optional feature)" "0,1" newline bitfld.long 0x0 5. "DM_HOST_META,When set invalidate all SLC entries referenced solely by the HOST or META" "0,1" newline bitfld.long 0x0 4. "DM_MMU,When set invalidate all SLC entries referenced solely by the MMU" "0,1" newline bitfld.long 0x0 3. "DM_COMPUTE,When set invalidate all SLC entries referenced solely by the COMPUTE data master" "0,1" newline bitfld.long 0x0 2. "DM_PIXEL,When set invalidate all SLC entries referenced solely by the PIXEL data master" "0,1" newline bitfld.long 0x0 1. "DM_TA,When set invalidate all SLC entries referenced solely by the TA group which includes VERTEX TESSELLATOR & STREAM_OUT data masters" "0,1" newline bitfld.long 0x0 0. "ALL,When set invalidate all SLC entries" "0,1" line.long 0x4 "RGX_CR_SLC_CTRL_INVAL_1,SLC Invalidate control. Note that per Data Master operations only invalidate entries that have been referenced solely by the specified Data Master. any cache lines referenced by multiple Data Masters will not be affected by a per.." hexmask.long 0x4 0.--31. 1. "Reserved_32,Reserved_32" line.long 0x8 "RGX_CR_SLC_CTRL_FLUSH_0,SLC Flush control. Note that per Data Master operations will flush any cache lines that have been made dirty by any writes from the specified Data Master." bitfld.long 0x8 31. "LAZY,Advanced mode of operation whereby other requestors are not blocked whilst the Flush is in progress" "0,1" newline hexmask.long.tbyte 0x8 9.--30. 1. "Reserved_9,Reserved_9" newline bitfld.long 0x8 8. "DM_FRC,When set flush all SLC entries made dirty by the FRC Video Core (Optional feature)" "0,1" newline bitfld.long 0x8 7. "DM_VXE,When set flush all SLC entries made dirty by the VXE Video Core (Optional feature)" "0,1" newline bitfld.long 0x8 6. "DM_VXD,When set flush all SLC entries made dirty by the VXD Video Core (Optional feature)" "0,1" newline bitfld.long 0x8 5. "DM_HOST_META,When set flush all SLC entries made dirty by the HOST or META" "0,1" newline bitfld.long 0x8 4. "DM_MMU,When set flush all SLC entries made dirty by the MMU" "0,1" newline bitfld.long 0x8 3. "DM_COMPUTE,When set flush all SLC entries made dirty by the COMPUTE data master" "0,1" newline bitfld.long 0x8 2. "DM_PIXEL,When set flush all SLC entries made dirty by the PIXEL data master" "0,1" newline bitfld.long 0x8 1. "DM_TA,When set flush all SLC entries made dirty by the TA group which includes VERTEX TESSELLATOR & STREAM_OUT data masters" "0,1" newline bitfld.long 0x8 0. "ALL,When set flush all SLC entries" "0,1" line.long 0xC "RGX_CR_SLC_CTRL_FLUSH_1,SLC Flush control. Note that per Data Master operations will flush any cache lines that have been made dirty by any writes from the specified Data Master." hexmask.long 0xC 0.--31. 1. "Reserved_32,Reserved_32" line.long 0x10 "RGX_CR_SLC_CTRL_FLUSH_INVAL_0,SLC Flush & Invalidate control. Note that per Data Master operations will flush any cache lines that have been made dirty by any writes from the specified Data Master. Combined Invalidate operation then only invalidates.." bitfld.long 0x10 31. "LAZY,Advanced mode of operation whereby other requestors are not blocked whilst the Flush Invalidate is in progress" "0,1" newline hexmask.long.tbyte 0x10 9.--30. 1. "Reserved_9,Reserved_9" newline bitfld.long 0x10 8. "DM_FRC,When set flush all SLC entries made dirty by the FRC Video Core then invalidate all SLC entries referenced solely by the FRC Video Core (Optional feature)" "0,1" newline bitfld.long 0x10 7. "DM_VXE,When set flush all SLC entries made dirty by the VXE Video Core then invalidate all SLC entries referenced solely by the VXE Video Core (Optional feature)" "0,1" newline bitfld.long 0x10 6. "DM_VXD,When set flush all SLC entries made dirty by the VXD Video Core then invalidate all SLC entries referenced solely by the VXD Video Core (Optional feature)" "0,1" newline bitfld.long 0x10 5. "DM_HOST_META,When set flush all SLC entries made dirty by the HOST or META then invalidate all SLC entries referenced solely by the HOST or META" "0,1" newline bitfld.long 0x10 4. "DM_MMU,When set flush all SLC entries made dirty by the MMU then invalidate all SLC entries referenced solely by the MMU" "0,1" newline bitfld.long 0x10 3. "DM_COMPUTE,When set flush all SLC entries made dirty by the COMPUTE data master then invalidate all SLC entries referenced solely by the COMPUTE data master" "0,1" newline bitfld.long 0x10 2. "DM_PIXEL,When set flush all SLC entries made dirty by the PIXEL data master then invalidate all SLC entries referenced solely by the PIXEL data master" "0,1" newline bitfld.long 0x10 1. "DM_TA,When set flush all SLC entries made dirty by the TA group which includes VERTEX TESSELLATOR & STREAM_OUT data masters then invalidate all SLC entries referenced solely by the TA group which includes VERTEX TESSELLATOR & STREAM_OUT data masters" "0,1" newline bitfld.long 0x10 0. "ALL,When set flush all SLC entries then invalidate all SLC entries" "0,1" line.long 0x14 "RGX_CR_SLC_CTRL_FLUSH_INVAL_1,SLC Flush & Invalidate control. Note that per Data Master operations will flush any cache lines that have been made dirty by any writes from the specified Data Master. Combined Invalidate operation then only invalidates.." hexmask.long 0x14 0.--31. 1. "Reserved_32,Reserved_32" rgroup.long 0x3820++0x7 line.long 0x0 "RGX_CR_SLC_STATUS0_0,Current status of Flush / Invalidate operations within the SLC" hexmask.long 0x0 3.--31. 1. "Reserved_3,Reserved_3" newline bitfld.long 0x0 2. "FLUSH_INVAL_PENDING,1 indicates there is a pending request to perform a combined Flush Invalidate on the SLC" "0,1" newline bitfld.long 0x0 1. "INVAL_PENDING,1 indicates there is a pending request to Invalidate the SLC" "0,1" newline bitfld.long 0x0 0. "FLUSH_PENDING,1 indicates there is a pending request to Flush the SLC" "0,1" line.long 0x4 "RGX_CR_SLC_STATUS0_1,Current status of Flush / Invalidate operations within the SLC" hexmask.long 0x4 0.--31. 1. "Reserved_3,Reserved_3" group.long 0x3828++0x7 line.long 0x0 "RGX_CR_SLC_CTRL_BYPASS_0,SLC Bypass control" bitfld.long 0x0 31. "DM_FASTRENDER,Bypass SLC the TDM data master" "0,1" newline bitfld.long 0x0 30. "DM_PM_ALIST,Bypass SLC for the PB_ZLS data master" "0,1" newline bitfld.long 0x0 29. "DM_PB_TE,Bypass SLC for the PB_TE data master" "0,1" newline bitfld.long 0x0 28. "DM_PB_VCE,Bypass SLC for the PB_VCE data master" "0,1" newline bitfld.long 0x0 26.--27. "Reserved_26,Reserved_26" "0,1,2,3" newline bitfld.long 0x0 25. "REQ_IPF_CPF,Bypass SLC for IPF (CPF) requestor" "0,1" newline bitfld.long 0x0 24. "REQ_TPU,Bypass SLC for TPU requests coming from the MCU requestor" "0,1" newline bitfld.long 0x0 23. "REQ_FBDC,Bypass SLC for the FBDC requestor" "0,1" newline bitfld.long 0x0 22. "Reserved_22,Reserved_22" "0,1" newline bitfld.long 0x0 21. "BYP_CC_N,Bypass SLC when Cache Coherency bit is not set" "0,1" newline bitfld.long 0x0 20. "BYP_CC,Bypass SLC when Cache Coherency bit is set" "0,1" newline bitfld.long 0x0 19. "REQ_MCU,Bypass SLC for the MCU requestor" "0,1" newline bitfld.long 0x0 18. "REQ_PDS,Bypass SLC for the PDS requestor" "0,1" newline bitfld.long 0x0 17. "REQ_TPF,Bypass SLC for the TPF requestor" "0,1" newline bitfld.long 0x0 16. "REQ_TA_TPC,Bypass SLC for the TA (Tail Pointer Cache data) requestor" "0,1" newline bitfld.long 0x0 15. "Reserved_15,Reserved_15" "0,1" newline bitfld.long 0x0 14. "REQ_USC,Bypass SLC for the USC requestor" "0,1" newline bitfld.long 0x0 13. "REQ_META,Bypass SLC for the META requestor" "0,1" newline bitfld.long 0x0 12. "REQ_HOST,Bypass SLC for the Host requestor" "0,1" newline bitfld.long 0x0 11. "REQ_MMU_PT,Bypass SLC for the MMU requestor (Page Table data)" "0,1" newline bitfld.long 0x0 10. "REQ_MMU_PD,Bypass SLC for the MMU requestor (Page Directory data)" "0,1" newline bitfld.long 0x0 9. "REQ_MMU_PC,Bypass SLC for the MMU requestor (Page Catalogue data)" "0,1" newline bitfld.long 0x0 8. "DM_FRC,Bypass SLC for the FRC Video Core (Optional feature)" "0,1" newline bitfld.long 0x0 7. "DM_VXE,Bypass SLC for the VXE Video Core (Optional feature)" "0,1" newline bitfld.long 0x0 6. "DM_VXD,Bypass SLC for the VXD Video Core (Optional feature)" "0,1" newline bitfld.long 0x0 5. "DM_HOST_META,Bypass SLC the HOST/META data master" "0,1" newline bitfld.long 0x0 4. "DM_MMU,Bypass SLC the MMU data master" "0,1" newline bitfld.long 0x0 3. "DM_COMPUTE,Bypass SLC the COMPUTE data master" "0,1" newline bitfld.long 0x0 2. "DM_PIXEL,Bypass SLC for the PIXEL data master" "0,1" newline bitfld.long 0x0 1. "DM_TA,Bypass SLC for the TA group which includes VERTEX TESSELLATOR & STREAM_OUT data masters" "0,1" newline bitfld.long 0x0 0. "ALL,Bypass SLC for all requesters" "0,1" line.long 0x4 "RGX_CR_SLC_CTRL_BYPASS_1,SLC Bypass control" hexmask.long.word 0x4 22.--31. 1. "Reserved_54,Reserved_54" newline bitfld.long 0x4 21. "REQ_TCU_DM_COMPUTE,Bypass SLC when DM is COMPUTE for TCU requests" "0,1" newline bitfld.long 0x4 20. "Reserved_52,Reserved_52" "0,1" newline bitfld.long 0x4 19. "PBE_NOLINEFILL,PBE nolinefill set" "0,1" newline bitfld.long 0x4 18. "REQ_FBC,Bypass SLC for FBC requestor" "0,1" newline bitfld.long 0x4 17. "REQ_IPF_RREQ,Bypass SLC for IPF (RREQ) requestor" "0,1" newline bitfld.long 0x4 16. "REQ_IPF_CREQ,Bypass SLC for IPF (CREQ) requestor" "0,1" newline bitfld.long 0x4 15. "REQ_IPF_PREQ,Bypass SLC for IPF (PREQ) requestor" "0,1" newline bitfld.long 0x4 14. "REQ_IPF_DBSC,Bypass SLC for IPF (DBSC) requestor" "0,1" newline bitfld.long 0x4 13. "REQ_TCU,Bypass SLC for TCU requests" "0,1" newline bitfld.long 0x4 12. "REQ_PBE,Bypass SLC for PBE requestor" "0,1" newline bitfld.long 0x4 11. "REQ_ISP,Bypass SLC for the ISP requestor" "0,1" newline bitfld.long 0x4 10. "REQ_PM,Bypass SLC for the PM requestor" "0,1" newline bitfld.long 0x4 9. "REQ_TDM,Bypass SLC for the TDM requestor" "0,1" newline bitfld.long 0x4 8. "REQ_CDM,Bypass SLC for the CDM requestor" "0,1" newline bitfld.long 0x4 7. "REQ_TSPF_PDS_STATE,Bypass SLC for the TSPF PDS STATE requestor" "0,1" newline bitfld.long 0x4 6. "REQ_TSPF_DB,Bypass SLC for the TSPF DB requestor" "0,1" newline bitfld.long 0x4 5. "REQ_TSPF_VTX_VAR,Bypass SLC for the TSPF VTX VAR requestor" "0,1" newline bitfld.long 0x4 4. "REQ_VDM,Bypass SLC for VDM requestor" "0,1" newline bitfld.long 0x4 3. "REQ_TA_PSG_STREAM,Bypass SLC for the TA (PSG Stream) requestor" "0,1" newline bitfld.long 0x4 2. "REQ_TA_PSG_REGION,Bypass SLC for the TA (PSG Region) requestor" "0,1" newline bitfld.long 0x4 1. "REQ_TA_VCE,Bypass SLC for the TA (VCE) requestor" "0,1" newline bitfld.long 0x4 0. "REQ_TA_PPP,Bypass SLC for the TA (PPP) requestor" "0,1" repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) group.long ($2+0x3830)++0x3 line.long 0x0 "RGX_CR_SLC_LINE_USE_COUNT_LIMIT0_$1,Define the maximum number of cache lines allowed to be allocated to each requester within the SLC. Note that values are specified per bank as a multiple of 4 cache lines with values of 0x0 denoting no limit. Also note.." hexmask.long.byte 0x0 24.--31. 1. "TDM,Maximum number of cachelines allocated to the TDM requestor" newline hexmask.long.byte 0x0 16.--23. 1. "HOST,Maximum number of cachelines allocated to the HOST requestor" newline hexmask.long.byte 0x0 8.--15. 1. "TCU,Maximum number of cachelines allocated to the TCU requestor" newline hexmask.long.byte 0x0 0.--7. 1. "MMU,Maximum number of cachelines allocated to the MMU requestor" repeat.end group.long 0x3838++0x7 line.long 0x0 "RGX_CR_SLC_LINE_USE_COUNT_LIMIT1_0,Define the maximum number of cache lines allowed to be allocated to each requester within the SLC. Note that values are specified per bank as a multiple of 4 cache lines with values of 0x0 denoting no limit. Also note.." hexmask.long.byte 0x0 24.--31. 1. "VXD,Maximum number of cachelines allocated to the VXD requestor" newline hexmask.long.byte 0x0 16.--23. 1. "FBDC,Maximum number of cachelines allocated to the FBDC requestor" newline hexmask.long.byte 0x0 8.--15. 1. "MCU,Maximum number of cachelines allocated to the MCU requestor" newline hexmask.long.byte 0x0 0.--7. 1. "PDS,Maximum number of cachelines allocated to the PDS requestor" line.long 0x4 "RGX_CR_SLC_LINE_USE_COUNT_LIMIT1_1,Define the maximum number of cache lines allowed to be allocated to each requester within the SLC. Note that values are specified per bank as a multiple of 4 cache lines with values of 0x0 denoting no limit. Also note.." hexmask.long.word 0x4 16.--31. 1. "Reserved_48,Reserved_48" newline hexmask.long.byte 0x4 8.--15. 1. "FRC,Maximum number of cachelines allocated to the FRC requestor" newline hexmask.long.byte 0x4 0.--7. 1. "VXE,Maximum number of cachelines allocated to the VXE requestor" rgroup.long 0x3840++0x37 line.long 0x0 "RGX_CR_SLC_LINE_USE_COUNT_STATUS0_0,Number of cache lines currently allocated to each requester within the SLC. Values will constantly change when the core is active but will give a representative snapshot of cache usage." hexmask.long.byte 0x0 24.--31. 1. "BANK0_TDM,Number of cache lines in bank 0 currently allocated to the TDM" newline hexmask.long.word 0x0 12.--23. 1. "BANK1_MMU,Number of cache lines in bank 1 currently allocated to the MMU" newline hexmask.long.word 0x0 0.--11. 1. "BANK0_MMU,Number of cache lines in bank 0 currently allocated to the MMU" line.long 0x4 "RGX_CR_SLC_LINE_USE_COUNT_STATUS0_1,Number of cache lines currently allocated to each requester within the SLC. Values will constantly change when the core is active but will give a representative snapshot of cache usage." hexmask.long.byte 0x4 28.--31. 1. "Reserved_60,Reserved_60" newline hexmask.long.word 0x4 16.--27. 1. "BANK0_HOST,Number of cache lines in bank 0 currently allocated to the HOST" newline hexmask.long.word 0x4 4.--15. 1. "BANK1_TDM,Number of cache lines in bank 1 currently allocated to the TDM" newline hexmask.long.byte 0x4 0.--3. 1. "BANK0_TDM,Number of cache lines in bank 0 currently allocated to the TDM" line.long 0x8 "RGX_CR_SLC_LINE_USE_COUNT_STATUS1_0,Number of cache lines currently allocated to each requester within the SLC. Values will constantly change when the core is active but will give a representative snapshot of cache usage." hexmask.long.byte 0x8 24.--31. 1. "BANK1_TCU,Number of cache lines in bank 1 currently allocated to the TCU" newline hexmask.long.word 0x8 12.--23. 1. "BANK0_TCU,Number of cache lines in bank 0 currently allocated to the TCU" newline hexmask.long.word 0x8 0.--11. 1. "BANK1_HOST,Number of cache lines in bank 1 currently allocated to the HOST" line.long 0xC "RGX_CR_SLC_LINE_USE_COUNT_STATUS1_1,Number of cache lines currently allocated to each requester within the SLC. Values will constantly change when the core is active but will give a representative snapshot of cache usage." hexmask.long.byte 0xC 28.--31. 1. "Reserved_60,Reserved_60" newline hexmask.long.word 0xC 16.--27. 1. "BANK1_USC,Number of cache lines in bank 1 currently allocated to the USC" newline hexmask.long.word 0xC 4.--15. 1. "BANK0_USC,Number of cache lines in bank 0 currently allocated to the USC" newline hexmask.long.byte 0xC 0.--3. 1. "BANK1_TCU,Number of cache lines in bank 1 currently allocated to the TCU" line.long 0x10 "RGX_CR_SLC_LINE_USE_COUNT_STATUS2_0,Number of cache lines currently allocated to each requester within the SLC. Values will constantly change when the core is active but will give a representative snapshot of cache usage." hexmask.long.byte 0x10 24.--31. 1. "BANK0_TA_TPC,Number of cache lines in bank 0 currently allocated to the TA (Tail Pointer Cache data)" newline hexmask.long.word 0x10 12.--23. 1. "BANK1_IPF_OBJ,Number of cache lines in bank 1 currently allocated to the IPF (Object data)" newline hexmask.long.word 0x10 0.--11. 1. "BANK0_IPF_OBJ,Number of cache lines in bank 0 currently allocated to the IPF (Object data)" line.long 0x14 "RGX_CR_SLC_LINE_USE_COUNT_STATUS2_1,Number of cache lines currently allocated to each requester within the SLC. Values will constantly change when the core is active but will give a representative snapshot of cache usage." hexmask.long.byte 0x14 28.--31. 1. "Reserved_60,Reserved_60" newline hexmask.long.word 0x14 16.--27. 1. "BANK0_TPF,Number of cache lines in bank 0 currently allocated to the TPF" newline hexmask.long.word 0x14 4.--15. 1. "BANK1_TA_TPC,Number of cache lines in bank 1 currently allocated to the TA (Tail Pointer Cache data)" newline hexmask.long.byte 0x14 0.--3. 1. "BANK0_TA_TPC,Number of cache lines in bank 0 currently allocated to the TA (Tail Pointer Cache data)" line.long 0x18 "RGX_CR_SLC_LINE_USE_COUNT_STATUS3_0,Number of cache lines currently allocated to each requester within the SLC. Values will constantly change when the core is active but will give a representative snapshot of cache usage." hexmask.long.byte 0x18 24.--31. 1. "BANK1_PDS,Number of cache lines in bank 1 currently allocated to the PDS" newline hexmask.long.word 0x18 12.--23. 1. "BANK0_PDS,Number of cache lines in bank 0 currently allocated to the PDS" newline hexmask.long.word 0x18 0.--11. 1. "BANK1_TPF,Number of cache lines in bank 1 currently allocated to the TPF" line.long 0x1C "RGX_CR_SLC_LINE_USE_COUNT_STATUS3_1,Number of cache lines currently allocated to each requester within the SLC. Values will constantly change when the core is active but will give a representative snapshot of cache usage." hexmask.long.byte 0x1C 28.--31. 1. "Reserved_60,Reserved_60" newline hexmask.long.word 0x1C 16.--27. 1. "BANK1_MCU,Number of cache lines in bank 1 currently allocated to the MCU" newline hexmask.long.word 0x1C 4.--15. 1. "BANK0_MCU,Number of cache lines in bank 0 currently allocated to the MCU" newline hexmask.long.byte 0x1C 0.--3. 1. "BANK1_PDS,Number of cache lines in bank 1 currently allocated to the PDS" line.long 0x20 "RGX_CR_SLC_LINE_USE_COUNT_STATUS4_0,Number of cache lines currently allocated to each requester within the SLC. Values will constantly change when the core is active but will give a representative snapshot of cache usage." hexmask.long.byte 0x20 24.--31. 1. "BANK0_VXD,Number of cache lines in bank 0 currently allocated to the VXD core" newline hexmask.long.word 0x20 12.--23. 1. "BANK1_FBDC,Number of cache lines in bank 1 currently allocated to the FBDC" newline hexmask.long.word 0x20 0.--11. 1. "BANK0_FBDC,Number of cache lines in bank 0 currently allocated to the FBDC" line.long 0x24 "RGX_CR_SLC_LINE_USE_COUNT_STATUS4_1,Number of cache lines currently allocated to each requester within the SLC. Values will constantly change when the core is active but will give a representative snapshot of cache usage." hexmask.long.byte 0x24 28.--31. 1. "Reserved_60,Reserved_60" newline hexmask.long.word 0x24 16.--27. 1. "BANK0_VXE,Number of cache lines in bank 0 currently allocated to the VXE core" newline hexmask.long.word 0x24 4.--15. 1. "BANK1_VXD,Number of cache lines in bank 1 currently allocated to the VXD core" newline hexmask.long.byte 0x24 0.--3. 1. "BANK0_VXD,Number of cache lines in bank 0 currently allocated to the VXD core" line.long 0x28 "RGX_CR_SLC_LINE_USE_COUNT_STATUS5_0,Number of cache lines currently allocated to each requester within the SLC. Values will constantly change when the core is active but will give a representative snapshot of cache usage." hexmask.long.byte 0x28 24.--31. 1. "BANK1_FRC,Number of cache lines in bank 1 currently allocated to the FRC core" newline hexmask.long.word 0x28 12.--23. 1. "BANK0_FRC,Number of cache lines in bank 0 currently allocated to the FRC core" newline hexmask.long.word 0x28 0.--11. 1. "BANK1_VXE,Number of cache lines in bank 1 currently allocated to the VXE core" line.long 0x2C "RGX_CR_SLC_LINE_USE_COUNT_STATUS5_1,Number of cache lines currently allocated to each requester within the SLC. Values will constantly change when the core is active but will give a representative snapshot of cache usage." hexmask.long.byte 0x2C 28.--31. 1. "Reserved_60,Reserved_60" newline hexmask.long.word 0x2C 16.--27. 1. "BANK1_PM,Number of cache lines in bank 1 currently allocated to the PM core" newline hexmask.long.word 0x2C 4.--15. 1. "BANK0_PM,Number of cache lines in bank 0 currently allocated to the PM core" newline hexmask.long.byte 0x2C 0.--3. 1. "BANK1_FRC,Number of cache lines in bank 1 currently allocated to the FRC core" line.long 0x30 "RGX_CR_SLC_STATUS1_0,Current status of the SLC" hexmask.long.byte 0x30 26.--31. 1. "Reserved_26,Reserved_26" newline hexmask.long.word 0x30 16.--25. 1. "READS0,Number of items of read data SLC bank 0 has in internal pipeline FIFO's" newline hexmask.long.byte 0x30 8.--15. 1. "READS1_EXT,Number of items of read data SLC bank 1 has outstanding from external memory" newline hexmask.long.byte 0x30 0.--7. 1. "READS0_EXT,Number of items of read data SLC bank 0 has outstanding from external memory" line.long 0x34 "RGX_CR_SLC_STATUS1_1,Current status of the SLC" bitfld.long 0x34 31. "PAUSED,All cache banks are Paused" "0,1" newline hexmask.long.tbyte 0x34 10.--30. 1. "Reserved_42,Reserved_42" newline hexmask.long.word 0x34 0.--9. 1. "READS1,Number of items of read data SLC bank 1 has in internal pipeline FIFO's" group.long 0x3878++0x7 line.long 0x0 "RGX_CR_SLC_STATS0_CTRL_0,Configuration of the SLC Stats counters inside SLC bank 0. The type fields should be set to define the events that should be counted. then constraints should be added to specify particular requestors or types of request that.." hexmask.long.byte 0x0 28.--31. 1. "Reserved_28,Reserved_28" newline bitfld.long 0x0 27. "STOP,Pause counting whilst this bit is set" "0,1" newline bitfld.long 0x0 26. "RESET,Reset counter" "0,1" newline bitfld.long 0x0 25. "RNW,If constraint set 0x0 count only writes 0x1 count only reads" "0,1" newline bitfld.long 0x0 24. "BYPASS,If constraint set 0x0 count cached requests 0x1 count bypassed requests" "0,1" newline bitfld.long 0x0 21.--23. "DM,If constraint set count only requests for the specified Data Master" "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x0 16.--20. 1. "TAG_ID,If constraint set count only requests with the specified Tag ID" newline hexmask.long.byte 0x0 8.--15. 1. "TAG_SB,If constraint set count only requests with the specified sideband Tag" newline bitfld.long 0x0 7. "SELECT_TAG_SB,Include Tag sideband in constraints" "0,1" newline bitfld.long 0x0 6. "SELECT_TAG_ID,Include Tag ID in constraints" "0,1" newline bitfld.long 0x0 5. "SELECT_DM,Include Data Master in constraints" "0,1" newline bitfld.long 0x0 4. "SELECT_BYPASS,Include Bypass enable in constraints" "0,1" newline bitfld.long 0x0 3. "SELECT_RNW,Include Wead/Write select in constraints" "0,1" newline bitfld.long 0x0 2. "TYPE_FLUSH,Count number of cache lines flushed" "0,1" newline bitfld.long 0x0 1. "TYPE_MISS,Count number of misses" "0,1" newline bitfld.long 0x0 0. "TYPE_HIT,Count number of hits" "0,1" line.long 0x4 "RGX_CR_SLC_STATS0_CTRL_1,Configuration of the SLC Stats counters inside SLC bank 0. The type fields should be set to define the events that should be counted. then constraints should be added to specify particular requestors or types of request that.." hexmask.long 0x4 0.--31. 1. "Reserved_28,Reserved_28" repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) rgroup.long ($2+0x3880)++0x3 line.long 0x0 "RGX_CR_SLC_STATS0_OUTPUT_$1,Output of the SLC Stats counter inside SLC bank 0." hexmask.long 0x0 0.--31. 1. "VALUE,Value of counter 0" repeat.end group.long 0x3888++0x7 line.long 0x0 "RGX_CR_SLC_STATS1_CTRL_0,Configuration of the SLC Stats counters inside SLC bank 1. The type fields should be set to define the events that should be counted. then constraints should be added to specify particular requestors or types of request that.." hexmask.long.byte 0x0 28.--31. 1. "Reserved_28,Reserved_28" newline bitfld.long 0x0 27. "STOP,Pause counting whilst this bit is set" "0,1" newline bitfld.long 0x0 26. "RESET,Reset counter" "0,1" newline bitfld.long 0x0 25. "RNW,If constraint set 0x0 count only writes 0x1 count only reads" "0,1" newline bitfld.long 0x0 24. "BYPASS,If constraint set 0x0 count cached requests 0x1 count bypassed requests" "0,1" newline bitfld.long 0x0 21.--23. "DM,If constraint set count only requests for the specified Data Master" "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x0 16.--20. 1. "TAG_ID,If constraint set count only requests with the specified Tag ID" newline hexmask.long.byte 0x0 8.--15. 1. "TAG_SB,If constraint set count only requests with the specified sideband Tag" newline bitfld.long 0x0 7. "SELECT_TAG_SB,Include Tag sideband in constraints" "0,1" newline bitfld.long 0x0 6. "SELECT_TAG_ID,Include Tag ID in constraints" "0,1" newline bitfld.long 0x0 5. "SELECT_DM,Include Data Master in constraints" "0,1" newline bitfld.long 0x0 4. "SELECT_BYPASS,Include Bypass enable in constraints" "0,1" newline bitfld.long 0x0 3. "SELECT_RNW,Include Wead/Write select in constraints" "0,1" newline bitfld.long 0x0 2. "TYPE_FLUSH,Count number of cache lines flushed" "0,1" newline bitfld.long 0x0 1. "TYPE_MISS,Count number of misses" "0,1" newline bitfld.long 0x0 0. "TYPE_HIT,Count number of hits" "0,1" line.long 0x4 "RGX_CR_SLC_STATS1_CTRL_1,Configuration of the SLC Stats counters inside SLC bank 1. The type fields should be set to define the events that should be counted. then constraints should be added to specify particular requestors or types of request that.." hexmask.long 0x4 0.--31. 1. "Reserved_28,Reserved_28" repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) rgroup.long ($2+0x3890)++0x3 line.long 0x0 "RGX_CR_SLC_STATS1_OUTPUT_$1,Output of the SLC Stats counter inside SLC bank 1." hexmask.long 0x0 0.--31. 1. "VALUE,Value of counter 1" repeat.end rgroup.long 0x3898++0x7 line.long 0x0 "RGX_CR_SLC_IDLE_0,RGX_CR_SLC_IDLE_0" hexmask.long.tbyte 0x0 10.--31. 1. "Reserved_10,Reserved_10" newline bitfld.long 0x0 9. "MH_SYSARB1,SYSARB1 Module IDLE" "0,1" newline bitfld.long 0x0 8. "MH_SYSARB0,SYSARB0 Module IDLE" "0,1" newline bitfld.long 0x0 7. "IMGBV4,IMG Bus v4 Module IDLE" "0,1" newline bitfld.long 0x0 6. "CACHE_BANKS,Cache Bank IDLEs" "0,1" newline bitfld.long 0x0 5. "RBOFIFO,Read Burst Order FIFO Module IDLE" "0,1" newline bitfld.long 0x0 4. "FRC_CONV,FRC Module IDLE" "0,1" newline bitfld.long 0x0 3. "VXE_CONV,Video Encode Converter Module IDLE" "0,1" newline bitfld.long 0x0 2. "VXD_CONV,Video Decode Converter Module IDLE" "0,1" newline bitfld.long 0x0 1. "BIF1_CONV,BIF128->256 Converter Module IDLE" "0,1" newline bitfld.long 0x0 0. "CBAR,CrossBar Module IDLE" "0,1" line.long 0x4 "RGX_CR_SLC_IDLE_1,RGX_CR_SLC_IDLE_1" hexmask.long 0x4 0.--31. 1. "Reserved_10,Reserved_10" repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) rgroup.long ($2+0x38A0)++0x3 line.long 0x0 "RGX_CR_MCU_PWR_NUM_$1,Power Monitoring register" hexmask.long 0x0 0.--31. 1. "L0_TO_L1_ACCESS,Number of L0 to L1 accesses. Both L0s in a DUST added together" repeat.end group.long 0x38A8++0x7 line.long 0x0 "RGX_CR_SLC_LINE_USE_COUNT_LIMIT2_0,Define the maximum number of cache lines allowed to be allocated to each requester within the SLC. Note that values are specified per bank as a multiple of 4 cache lines with values of 0x0 denoting no limit. Also note.." hexmask.long.byte 0x0 24.--31. 1. "CDM,Maximum number of cachelines allocated to the CDM requestor" newline hexmask.long.byte 0x0 16.--23. 1. "VDM,Maximum number of cachelines allocated to the VDM requestor" newline hexmask.long.byte 0x0 8.--15. 1. "ISP,Maximum number of cachelines allocated to the ISP requestor" newline hexmask.long.byte 0x0 0.--7. 1. "PBE,Maximum number of cachelines allocated to the PBE requestor" line.long 0x4 "RGX_CR_SLC_LINE_USE_COUNT_LIMIT2_1,Define the maximum number of cache lines allowed to be allocated to each requester within the SLC. Note that values are specified per bank as a multiple of 4 cache lines with values of 0x0 denoting no limit. Also note.." hexmask.long.tbyte 0x4 8.--31. 1. "Reserved_40,Reserved_40" newline hexmask.long.byte 0x4 0.--7. 1. "PM,Maximum number of cachelines allocated to the PM requestor" rgroup.long 0x38B0++0xF line.long 0x0 "RGX_CR_SLC_LINE_USE_COUNT_STATUS6_0,Number of cache lines currently allocated to each requester within the SLC. Values will constantly change when the core is active but will give a representative snapshot of cache usage." hexmask.long.byte 0x0 24.--31. 1. "BANK0_ISP,Number of cache lines in bank 0 currently allocated to the ISP core" newline hexmask.long.word 0x0 12.--23. 1. "BANK1_PBE,Number of cache lines in bank 1 currently allocated to the PBE core" newline hexmask.long.word 0x0 0.--11. 1. "BANK0_PBE,Number of cache lines in bank 0 currently allocated to the PBE core" line.long 0x4 "RGX_CR_SLC_LINE_USE_COUNT_STATUS6_1,Number of cache lines currently allocated to each requester within the SLC. Values will constantly change when the core is active but will give a representative snapshot of cache usage." hexmask.long.byte 0x4 28.--31. 1. "Reserved_60,Reserved_60" newline hexmask.long.word 0x4 16.--27. 1. "BANK0_CDM,Number of cache lines in bank 1 currently allocated to the CDM core" newline hexmask.long.word 0x4 4.--15. 1. "BANK1_ISP,Number of cache lines in bank 1 currently allocated to the ISP core" newline hexmask.long.byte 0x4 0.--3. 1. "BANK0_ISP,Number of cache lines in bank 0 currently allocated to the ISP core" line.long 0x8 "RGX_CR_SLC_LINE_USE_COUNT_STATUS7_0,Number of cache lines currently allocated to each requester within the SLC. Values will constantly change when the core is active but will give a representative snapshot of cache usage." hexmask.long.byte 0x8 24.--31. 1. "BANK1_VDM,Number of cache lines in bank 1 currently allocated to the VDM core" newline hexmask.long.word 0x8 12.--23. 1. "BANK0_VDM,Number of cache lines in bank 0 currently allocated to the VDM core" newline hexmask.long.word 0x8 0.--11. 1. "BANK1_CDM,Number of cache lines in bank 1 currently allocated to the CDM core" line.long 0xC "RGX_CR_SLC_LINE_USE_COUNT_STATUS7_1,Number of cache lines currently allocated to each requester within the SLC. Values will constantly change when the core is active but will give a representative snapshot of cache usage." hexmask.long 0xC 4.--31. 1. "Reserved_36,Reserved_36" newline hexmask.long.byte 0xC 0.--3. 1. "BANK1_VDM,Number of cache lines in bank 1 currently allocated to the VDM core" group.long 0x38C0++0x17 line.long 0x0 "RGX_CR_AXI_ACE_LITE_CONFIGURATION_0,AXI ACE-LITE configuration registers" bitfld.long 0x0 30.--31. "ARCACHE_CACHE_MAINTENANCE,Read cache policy for cache maintenance transactions - bit[1] should be set to 1" "0,1,2,3" newline hexmask.long.byte 0x0 26.--29. 1. "ARCACHE_COHERENT,Read cache policy for coherent transactions - bit[1] should be set to 1" newline hexmask.long.byte 0x0 22.--25. 1. "AWCACHE_COHERENT,Write cache policy for coherent transactions - bit[1] should be set to 1" newline bitfld.long 0x0 20.--21. "ARDOMAIN_BARRIER,Read shareability domain for barrier transactions 00 = Non-Shareable 01 = Inner Shareable 10 = Outer Shareable 11 = System" "Non-Shareable,Inner Shareable,?,?" newline bitfld.long 0x0 18.--19. "AWDOMAIN_BARRIER,Write shareability domain for barrier transactions 00 = Non-Shareable 01 = Inner Shareable 10 = Outer Shareable 11 = System" "Non-Shareable,Inner Shareable,?,?" newline bitfld.long 0x0 16.--17. "ARDOMAIN_CACHE_MAINTENANCE,Read shareability domain for cache maintenance transactions 00 = Non-Shareable 01 = Inner Shareable 10 = Outer Shareable" "Non-Shareable,Inner Shareable,?,?" newline bitfld.long 0x0 14.--15. "AWDOMAIN_COHERENT,Write shareability domain for coherant transactions 01 = Inner Shareable 10 = Outer Shareable" "?,Inner Shareable,?,?" newline bitfld.long 0x0 12.--13. "ARDOMAIN_COHERENT,Read shareability domain for coherant transactions 01 = Inner Shareable 10 = Outer Shareable" "?,Inner Shareable,?,?" newline bitfld.long 0x0 10.--11. "ARDOMAIN_NON_SNOOPING,Read shareability domain for non-snooping transactions 00 = Non-Shareable 11 = System" "Non-Shareable,?,?,?" newline bitfld.long 0x0 8.--9. "AWDOMAIN_NON_SNOOPING,Write shareability domain for non-snooping transactions 00 = Non-Shareable 11 = System" "Non-Shareable,?,?,?" newline hexmask.long.byte 0x0 4.--7. 1. "ARCACHE_NON_SNOOPING,Read cache policy for non-snooping transactions" newline hexmask.long.byte 0x0 0.--3. 1. "AWCACHE_NON_SNOOPING,Write cache policy for non-snooping transactions" line.long 0x4 "RGX_CR_AXI_ACE_LITE_CONFIGURATION_1,AXI ACE-LITE configuration registers" hexmask.long.tbyte 0x4 13.--31. 1. "Reserved_45,Reserved_45" newline hexmask.long.byte 0x4 5.--12. 1. "OSID_SECURITY,SET to 1 to disable secure reads/writes for each OSID" newline bitfld.long 0x4 4. "DISABLE_COHERENT_WRITELINEUNIQUE,SET to 1 to disable coherent write line uniques" "0,1" newline bitfld.long 0x4 3. "DISABLE_COHERENT_WRITE,SET to 1 to disable coherent writes" "0,1" newline bitfld.long 0x4 2. "DISABLE_COHERENT_READ,SET to 1 to disable coherent reads" "0,1" newline bitfld.long 0x4 0.--1. "ARCACHE_CACHE_MAINTENANCE,Read cache policy for cache maintenance transactions - bit[1] should be set to 1" "0,1,2,3" line.long 0x8 "RGX_CR_AXI_ACE_LITE_CACHE_MAINTENANCE_CONFIGURATION_0,AXI ACE-LITE Cache Maintenance configuration registers" hexmask.long 0x8 4.--31. 1. "MAINTENANCE_ADDRESS,Address to perform cache maintenace address on" newline bitfld.long 0x8 3. "MAINTENANCE_MAKEINVALID,Writing a 1 issues a makeinvalid operation" "0,1" newline bitfld.long 0x8 2. "MAINTENANCE_CLEAN_INVALID,Writing a 1 issues a clean invalid operation" "0,1" newline bitfld.long 0x8 1. "MAINTENANCE_CLEANSHARED,Writing a 1 issues a clean shared operation" "0,1" newline bitfld.long 0x8 0. "ENABLE_MAINTENANCE,Writing a 1 enables cache maintenance operations" "0,1" line.long 0xC "RGX_CR_AXI_ACE_LITE_CACHE_MAINTENANCE_CONFIGURATION_1,AXI ACE-LITE Cache Maintenance configuration registers" hexmask.long.tbyte 0xC 12.--31. 1. "Reserved_44,Reserved_44" newline hexmask.long.word 0xC 0.--11. 1. "MAINTENANCE_ADDRESS,Address to perform cache maintenace address on" line.long 0x10 "RGX_CR_AXI_ACE_LITE_CACHE_MAINTENANCE_STATUS_0,The hardware will set this to 1 once the cache maintenance operation has completed. The firmware should poll this bit and set it to 0. once it has acknowledged it being set to 1." hexmask.long 0x10 1.--31. 1. "Reserved_1,Reserved_1" newline bitfld.long 0x10 0. "DONE,DONE" "0,1" line.long 0x14 "RGX_CR_AXI_ACE_LITE_CACHE_MAINTENANCE_STATUS_1,The hardware will set this to 1 once the cache maintenance operation has completed. The firmware should poll this bit and set it to 0. once it has acknowledged it being set to 1." hexmask.long 0x14 0.--31. 1. "Reserved_1,Reserved_1" repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) group.long ($2+0x3930)++0x3 line.long 0x0 "RGX_CR_SLC_CTRL_MISC2_$1,SLC control registers" hexmask.long 0x0 0.--31. 1. "SCRAMBLE_BITS,Pattern of bits used to determine the MSB of the Cache Bank in 4 Bank configurations in Address Decode mode 0x21. The actual Cache Bank to use is determined by indexing into the 32 Scramble Bits using the 5 LSB's of the Hash result and then.." repeat.end group.long 0x3938++0x7 line.long 0x0 "RGX_CR_SLC_CROSSBAR_LOAD_BALANCE_0,SLC control registers to bypass SLC crossbar load balancing" hexmask.long 0x0 1.--31. 1. "Reserved_1,Reserved_1" newline bitfld.long 0x0 0. "BYPASS,control register bit to bypass load balancing in SLC crossbar. In this case the requests from img-memif0 will go directly to ocp-memif0 and so on" "0,1" line.long 0x4 "RGX_CR_SLC_CROSSBAR_LOAD_BALANCE_1,SLC control registers to bypass SLC crossbar load balancing" hexmask.long 0x4 0.--31. 1. "Reserved_1,Reserved_1" rgroup.long 0x3960++0x7 line.long 0x0 "RGX_CR_SLC_STATUS3_0,Current status of the SLC" hexmask.long.byte 0x0 24.--31. 1. "WRITES1_TRANSACTIONS_EXT,Number of outsanding write burst transactions in SLC bank 1" newline hexmask.long.byte 0x0 16.--23. 1. "WRITES0_TRANSACTIONS_EXT,Number of outsanding write burst transactions in SLC bank 0" newline hexmask.long.byte 0x0 8.--15. 1. "READS1_TRANSACTIONS_EXT,Number of outsanding read burst transactions in SLC bank 1" newline hexmask.long.byte 0x0 0.--7. 1. "READS0_TRANSACTIONS_EXT,Number of outsanding read burst transactions in SLC bank 0" line.long 0x4 "RGX_CR_SLC_STATUS3_1,Current status of the SLC" hexmask.long 0x4 0.--31. 1. "Reserved_32,Reserved_32" wgroup.long 0x4000++0x7 line.long 0x0 "RGX_CR_USC_INST_CACHE_0,RGX_CR_USC_INST_CACHE_0" hexmask.long 0x0 1.--31. 1. "Reserved_1,Reserved_1" newline bitfld.long 0x0 0. "INVALIDATE,Any write to this location invalidates the L1 and L2 instruction caches automatically" "0,1" line.long 0x4 "RGX_CR_USC_INST_CACHE_1,RGX_CR_USC_INST_CACHE_1" hexmask.long 0x4 0.--31. 1. "Reserved_1,Reserved_1" group.long 0x4008++0xF line.long 0x0 "RGX_CR_USC_CODE_BASE_VERTEX_0,RGX_CR_USC_CODE_BASE_VERTEX_0" hexmask.long 0x0 6.--31. 1. "ADDR,Vertex Data Master Code Base Register bits" newline hexmask.long.byte 0x0 0.--5. 1. "Reserved_0,Reserved_0" line.long 0x4 "RGX_CR_USC_CODE_BASE_VERTEX_1,RGX_CR_USC_CODE_BASE_VERTEX_1" hexmask.long.tbyte 0x4 8.--31. 1. "Reserved_40,Reserved_40" newline hexmask.long.byte 0x4 0.--7. 1. "ADDR,Vertex Data Master Code Base Register bits" line.long 0x8 "RGX_CR_USC_CODE_BASE_PIXEL_0,RGX_CR_USC_CODE_BASE_PIXEL_0" hexmask.long 0x8 6.--31. 1. "ADDR,Pixel Data Master Code Base Register bits" newline hexmask.long.byte 0x8 0.--5. 1. "Reserved_0,Reserved_0" line.long 0xC "RGX_CR_USC_CODE_BASE_PIXEL_1,RGX_CR_USC_CODE_BASE_PIXEL_1" hexmask.long.tbyte 0xC 8.--31. 1. "Reserved_40,Reserved_40" newline hexmask.long.byte 0xC 0.--7. 1. "ADDR,Pixel Data Master Code Base Register bits" group.long 0x4028++0x4F line.long 0x0 "RGX_CR_USC_CODE_BASE_COMPUTE_0,RGX_CR_USC_CODE_BASE_COMPUTE_0" hexmask.long 0x0 6.--31. 1. "ADDR,Compute Data Master Code Base Register bits" newline hexmask.long.byte 0x0 0.--5. 1. "Reserved_0,Reserved_0" line.long 0x4 "RGX_CR_USC_CODE_BASE_COMPUTE_1,RGX_CR_USC_CODE_BASE_COMPUTE_1" hexmask.long.tbyte 0x4 8.--31. 1. "Reserved_40,Reserved_40" newline hexmask.long.byte 0x4 0.--7. 1. "ADDR,Compute Data Master Code Base Register bits" line.long 0x8 "RGX_CR_USC_BREAKPOINT_0,RGX_CR_USC_BREAKPOINT_0" hexmask.long 0x8 1.--31. 1. "ADDR,Breakpoint Address" newline bitfld.long 0x8 0. "Reserved_0,Reserved_0" "0,1" line.long 0xC "RGX_CR_USC_BREAKPOINT_1,RGX_CR_USC_BREAKPOINT_1" hexmask.long 0xC 0.--31. 1. "Reserved_32,Reserved_32" line.long 0x10 "RGX_CR_USC_BREAKPOINT_HANDLER_0,RGX_CR_USC_BREAKPOINT_HANDLER_0" hexmask.long 0x10 1.--31. 1. "ADDR,Breakpoint Handler Address" newline bitfld.long 0x10 0. "Reserved_0,Reserved_0" "0,1" line.long 0x14 "RGX_CR_USC_BREAKPOINT_HANDLER_1,RGX_CR_USC_BREAKPOINT_HANDLER_1" hexmask.long 0x14 0.--31. 1. "Reserved_32,Reserved_32" line.long 0x18 "RGX_CR_USC_BREAKPOINT_CTRL_0,RGX_CR_USC_BREAKPOINT_CTRL_0" hexmask.long 0x18 4.--31. 1. "Reserved_4,Reserved_4" newline bitfld.long 0x18 3. "ENABLE,0 = Breakpoint disabled 1 = Breakpoint enabled" "Breakpoint disabled,Breakpoint enabled" newline bitfld.long 0x18 0.--2. "DM,Data Master of Breakpoint" "0,1,2,3,4,5,6,7" line.long 0x1C "RGX_CR_USC_BREAKPOINT_CTRL_1,RGX_CR_USC_BREAKPOINT_CTRL_1" hexmask.long 0x1C 0.--31. 1. "Reserved_4,Reserved_4" line.long 0x20 "RGX_CR_USC_SMP_SWAP_0,RGX_CR_USC_SMP_SWAP_0" hexmask.long 0x20 1.--31. 1. "Reserved_1,Reserved_1" newline bitfld.long 0x20 0. "ENABLE,Deactivate after SMP instruction" "0,1" line.long 0x24 "RGX_CR_USC_SMP_SWAP_1,RGX_CR_USC_SMP_SWAP_1" hexmask.long 0x24 0.--31. 1. "Reserved_1,Reserved_1" line.long 0x28 "RGX_CR_USC_OVERRIDE_CTRL_0,RGX_CR_USC_OVERRIDE_CTRL_0" hexmask.long.word 0x28 22.--31. 1. "Reserved_22,Reserved_22" newline bitfld.long 0x28 21. "USCIS_LOCKING,0 = Default enable locking of USCIS when queue fills to maintain task ordering 1 = retry USCIS request" "Default,retry USCIS request" newline bitfld.long 0x28 20. "PHASE_BOTH,0 = Default no extra pass groups when single phase followed by multi-phase 1 = generate pass group whenever phases per task changes" "Default,generate pass group whenever phases per task.." newline bitfld.long 0x28 18.--19. "RESERVE_SLOTS,0 = Default allow all slots to be used for first phase tasks 1 = reserve 1 slot 2 = reserve 2 3 = reserve 4" "Default,reserve 1 slot,reserve 2,reserve 4" newline bitfld.long 0x28 17. "NO_RESERVE,0 = Default reserve slots for second phases 1 = Do not reserve slots for second phase tasks" "Default,Do not reserve slots for second phase tasks" newline bitfld.long 0x28 15.--16. "MAX_GROUP,0 = Default - 8 pass groups in flight 1 = 6 pass groups 2 = 4 pass groups 3 = 2 pass groups. To disable entirely see PDS" "Default,?,?,?" newline bitfld.long 0x28 14. "WAKE_UP,0 = Default normal wake up 1 = force task wake up" "Default,force task wake up" newline bitfld.long 0x28 13. "LATE_PARTN,0 = Default enable pixel data master tasks to start before a partition is allocated 1 = wait for partition" "Default,wait for partition" newline bitfld.long 0x28 12. "DMA_LOCKING,0 = Default enable locking of DMA when queue fills to maintain task ordering 1 = retry DMA request" "Default,retry DMA request" newline bitfld.long 0x28 11. "PRIORITY,0 = Default enable state loading and end of tile tasks to run with higher priority 1 = all tasks low priority" "Default,all tasks low priority" newline bitfld.long 0x28 10. "PHASE_PASSES,0 = Default enable inferred pass groups when multiple phase tasks are encountered 1 = disable hard SDs must be used" "Default,disable" newline bitfld.long 0x28 9. "OUTPUT_WRITES,0 = Default enable tracking of output buffer write completion for on-edge buffer validlity 1 = tracking invalid" "Default,tracking invalid" newline bitfld.long 0x28 8. "SELECTIVE_RATE,0 = Default (core specific enable selective rate mode if functional) 1 = disable" "Default,disable" newline bitfld.long 0x28 6.--7. "Reserved_6,Reserved_6" "0,1,2,3" newline hexmask.long.byte 0x28 0.--5. 1. "DEBUG_TEMPS,Number of temps to add to PDS allocation size for debugging. Units of 8" line.long 0x2C "RGX_CR_USC_OVERRIDE_CTRL_1,RGX_CR_USC_OVERRIDE_CTRL_1" hexmask.long 0x2C 0.--31. 1. "Reserved_22,Reserved_22" line.long 0x30 "RGX_CR_USC_DC_CACHE_CTRL_0,RGX_CR_USC_DC_CACHE_CTRL_0" hexmask.long 0x30 1.--31. 1. "Reserved_1,Reserved_1" newline bitfld.long 0x30 0. "LINES,Number of lines in Dynamic Constant Cache - 0=64 1=128" "0,1" line.long 0x34 "RGX_CR_USC_DC_CACHE_CTRL_1,RGX_CR_USC_DC_CACHE_CTRL_1" hexmask.long 0x34 0.--31. 1. "Reserved_1,Reserved_1" line.long 0x38 "RGX_CR_USC_DC_CACHE_INVALIDATE_0,RGX_CR_USC_DC_CACHE_INVALIDATE_0" hexmask.long 0x38 1.--31. 1. "Reserved_1,Reserved_1" newline bitfld.long 0x38 0. "PENDING,A write of 1 to this location will cause an invalidation of the Dynamic Constant Cache. If DMKILL bit is not set then all entries are invalidated. If DMKILL bit is set then only a data master killing invalidation is performed. The invalidation.." "0,1" line.long 0x3C "RGX_CR_USC_DC_CACHE_INVALIDATE_1,RGX_CR_USC_DC_CACHE_INVALIDATE_1" hexmask.long 0x3C 0.--31. 1. "Reserved_1,Reserved_1" line.long 0x40 "RGX_CR_USC_SHARED_GROUP_CLEAR_0,RGX_CR_USC_SHARED_GROUP_CLEAR_0" hexmask.long 0x40 1.--31. 1. "Reserved_1,Reserved_1" newline bitfld.long 0x40 0. "PENDING,Any write to this location requests the USC Shared Group register file to be cleared" "0,1" line.long 0x44 "RGX_CR_USC_SHARED_GROUP_CLEAR_1,RGX_CR_USC_SHARED_GROUP_CLEAR_1" hexmask.long 0x44 0.--31. 1. "Reserved_1,Reserved_1" line.long 0x48 "RGX_CR_USC_PIXEL_OUTPUT_CTRL_0,RGX_CR_USC_PIXEL_OUTPUT_CTRL_0" hexmask.long.word 0x48 17.--31. 1. "Reserved_17,Reserved_17" newline hexmask.long.word 0x48 3.--16. 1. "PARTITION_MASK,Partition Enable Mask for USC. Defines which partitions are for use by the USC to prevent SPM Deadlock" newline bitfld.long 0x48 2. "ENABLE_4TH_PARTITION,Enables 4th Partition" "0,1" newline bitfld.long 0x48 0.--1. "WIDTH,WIDTH" "0,1,2,3" line.long 0x4C "RGX_CR_USC_PIXEL_OUTPUT_CTRL_1,RGX_CR_USC_PIXEL_OUTPUT_CTRL_1" hexmask.long 0x4C 0.--31. 1. "Reserved_17,Reserved_17" repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) group.long ($2+0x4078)++0x3 line.long 0x0 "RGX_CR_USC_CLEAR_REGISTER0_$1,RGX_CR_USC_CLEAR_REGISTER0_0" hexmask.long 0x0 0.--31. 1. "VAL,Clear Colour register 0" repeat.end repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) group.long ($2+0x4080)++0x3 line.long 0x0 "RGX_CR_USC_CLEAR_REGISTER1_$1,RGX_CR_USC_CLEAR_REGISTER1_0" hexmask.long 0x0 0.--31. 1. "VAL,Clear Colour register 1" repeat.end repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) group.long ($2+0x4088)++0x3 line.long 0x0 "RGX_CR_USC_CLEAR_REGISTER2_$1,RGX_CR_USC_CLEAR_REGISTER2_0" hexmask.long 0x0 0.--31. 1. "VAL,Clear Colour register 2" repeat.end repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) group.long ($2+0x4090)++0x3 line.long 0x0 "RGX_CR_USC_CLEAR_REGISTER3_$1,RGX_CR_USC_CLEAR_REGISTER3_0" hexmask.long 0x0 0.--31. 1. "VAL,Clear Colour register 3" repeat.end group.long 0x4098++0x3F line.long 0x0 "RGX_CR_USC_G0_0,RGX_CR_USC_G0_0" hexmask.long.tbyte 0x0 8.--31. 1. "Reserved_8,Reserved_8" newline hexmask.long.byte 0x0 0.--7. 1. "P,Global cross-thread-accessible read/write register for USC programs via the 'special' bank type" line.long 0x4 "RGX_CR_USC_G0_1,RGX_CR_USC_G0_1" hexmask.long 0x4 0.--31. 1. "Reserved_8,Reserved_8" line.long 0x8 "RGX_CR_USC_G1_0,RGX_CR_USC_G1_0" hexmask.long.tbyte 0x8 8.--31. 1. "Reserved_8,Reserved_8" newline hexmask.long.byte 0x8 0.--7. 1. "P,Global cross-thread-accessible read/write register for USC programs via the 'special' bank type" line.long 0xC "RGX_CR_USC_G1_1,RGX_CR_USC_G1_1" hexmask.long 0xC 0.--31. 1. "Reserved_8,Reserved_8" line.long 0x10 "RGX_CR_USC_G2_0,RGX_CR_USC_G2_0" hexmask.long.tbyte 0x10 8.--31. 1. "Reserved_8,Reserved_8" newline hexmask.long.byte 0x10 0.--7. 1. "P,Global cross-thread-accessible read/write register for USC programs via the 'special' bank type" line.long 0x14 "RGX_CR_USC_G2_1,RGX_CR_USC_G2_1" hexmask.long 0x14 0.--31. 1. "Reserved_8,Reserved_8" line.long 0x18 "RGX_CR_USC_G3_0,RGX_CR_USC_G3_0" hexmask.long.tbyte 0x18 8.--31. 1. "Reserved_8,Reserved_8" newline hexmask.long.byte 0x18 0.--7. 1. "P,Global cross-thread-accessible read/write register for USC programs via the 'special' bank type" line.long 0x1C "RGX_CR_USC_G3_1,RGX_CR_USC_G3_1" hexmask.long 0x1C 0.--31. 1. "Reserved_8,Reserved_8" line.long 0x20 "RGX_CR_USC_G4_0,RGX_CR_USC_G4_0" hexmask.long.tbyte 0x20 8.--31. 1. "Reserved_8,Reserved_8" newline hexmask.long.byte 0x20 0.--7. 1. "P,Global cross-thread-accessible read/write register for USC programs via the 'special' bank type" line.long 0x24 "RGX_CR_USC_G4_1,RGX_CR_USC_G4_1" hexmask.long 0x24 0.--31. 1. "Reserved_8,Reserved_8" line.long 0x28 "RGX_CR_USC_G5_0,RGX_CR_USC_G5_0" hexmask.long.tbyte 0x28 8.--31. 1. "Reserved_8,Reserved_8" newline hexmask.long.byte 0x28 0.--7. 1. "P,Global cross-thread-accessible read/write register for USC programs via the 'special' bank type" line.long 0x2C "RGX_CR_USC_G5_1,RGX_CR_USC_G5_1" hexmask.long 0x2C 0.--31. 1. "Reserved_8,Reserved_8" line.long 0x30 "RGX_CR_USC_G6_0,RGX_CR_USC_G6_0" hexmask.long.tbyte 0x30 8.--31. 1. "Reserved_8,Reserved_8" newline hexmask.long.byte 0x30 0.--7. 1. "P,Global cross-thread-accessible read/write register for USC programs via the 'special' bank type" line.long 0x34 "RGX_CR_USC_G6_1,RGX_CR_USC_G6_1" hexmask.long 0x34 0.--31. 1. "Reserved_8,Reserved_8" line.long 0x38 "RGX_CR_USC_G7_0,RGX_CR_USC_G7_0" hexmask.long.tbyte 0x38 8.--31. 1. "Reserved_8,Reserved_8" newline hexmask.long.byte 0x38 0.--7. 1. "P,Global cross-thread-accessible read/write register for USC programs via the 'special' bank type" line.long 0x3C "RGX_CR_USC_G7_1,RGX_CR_USC_G7_1" hexmask.long 0x3C 0.--31. 1. "Reserved_8,Reserved_8" rgroup.long 0x40D8++0x27 line.long 0x0 "RGX_CR_USC_SERV_PIXEL_0,RGX_CR_USC_SERV_PIXEL_0" hexmask.long.word 0x0 17.--31. 1. "Reserved_17,Reserved_17" newline bitfld.long 0x0 16. "EMPTY,No Pixel Data Master tasks in USC0 queue" "0,1" newline hexmask.long.word 0x0 0.--15. 1. "COUNT,Number of Pixel Data Master tasks serviced by USC0" line.long 0x4 "RGX_CR_USC_SERV_PIXEL_1,RGX_CR_USC_SERV_PIXEL_1" hexmask.long 0x4 0.--31. 1. "Reserved_17,Reserved_17" line.long 0x8 "RGX_CR_USC_SERV_VERTEX_0,RGX_CR_USC_SERV_VERTEX_0" hexmask.long.word 0x8 17.--31. 1. "Reserved_17,Reserved_17" newline bitfld.long 0x8 16. "EMPTY,No Vertex Data Master tasks in USC0 queue" "0,1" newline hexmask.long.word 0x8 0.--15. 1. "COUNT,Number of Vertex Data Master tasks serviced by USC0" line.long 0xC "RGX_CR_USC_SERV_VERTEX_1,RGX_CR_USC_SERV_VERTEX_1" hexmask.long 0xC 0.--31. 1. "Reserved_17,Reserved_17" line.long 0x10 "RGX_CR_USC_SERV_TESS_PIXEL_0,RGX_CR_USC_SERV_TESS_PIXEL_0" hexmask.long.word 0x10 17.--31. 1. "Reserved_17,Reserved_17" newline bitfld.long 0x10 16. "EMPTY,No Tessellator Pixel Data Master tasks in USC0 queue" "0,1" newline hexmask.long.word 0x10 0.--15. 1. "COUNT,Number of Tessellator Pixel Data Master tasks serviced by USC0" line.long 0x14 "RGX_CR_USC_SERV_TESS_PIXEL_1,RGX_CR_USC_SERV_TESS_PIXEL_1" hexmask.long 0x14 0.--31. 1. "Reserved_17,Reserved_17" line.long 0x18 "RGX_CR_USC_SERV_TESS_VERTEX_0,RGX_CR_USC_SERV_TESS_VERTEX_0" hexmask.long.word 0x18 17.--31. 1. "Reserved_17,Reserved_17" newline bitfld.long 0x18 16. "EMPTY,No Tessellator Vertex Data Master tasks in USC0 queue" "0,1" newline hexmask.long.word 0x18 0.--15. 1. "COUNT,Number of Tessellator Vertex Data Master tasks serviced by USC0" line.long 0x1C "RGX_CR_USC_SERV_TESS_VERTEX_1,RGX_CR_USC_SERV_TESS_VERTEX_1" hexmask.long 0x1C 0.--31. 1. "Reserved_17,Reserved_17" line.long 0x20 "RGX_CR_USC_SERV_COMPUTE_0,RGX_CR_USC_SERV_COMPUTE_0" hexmask.long.word 0x20 17.--31. 1. "Reserved_17,Reserved_17" newline bitfld.long 0x20 16. "EMPTY,No Compute Data Master tasks in USC0 queue" "0,1" newline hexmask.long.word 0x20 0.--15. 1. "COUNT,Number of Compute Data Master tasks serviced by USC0" line.long 0x24 "RGX_CR_USC_SERV_COMPUTE_1,RGX_CR_USC_SERV_COMPUTE_1" hexmask.long 0x24 0.--31. 1. "Reserved_17,Reserved_17" repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) rgroup.long ($2+0x4100)++0x3 line.long 0x0 "RGX_CR_USC_PARTITION_STATUS_$1,RGX_CR_USC_PARTITION_STATUS_0" hexmask.long.word 0x0 16.--31. 1. "CLOSED,Partition closed - end of tile task started" newline hexmask.long.word 0x0 0.--15. 1. "IN_USE,Partition in use" repeat.end rgroup.long 0x4108++0x17 line.long 0x0 "RGX_CR_USC_OLDEST_TASK_STATUS_0,RGX_CR_USC_OLDEST_TASK_STATUS_0" hexmask.long.word 0x0 20.--31. 1. "Reserved_20,Reserved_20" newline hexmask.long.byte 0x0 16.--19. 1. "PASS_NUM,The present pass group" newline bitfld.long 0x0 13.--15. "DM,The task Data Master" "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x0 9.--12. 1. "TILEQUAD,The stream of the task depends on Data Master Vertex: Indicates the patch of the task Pixel >= 4 cluster: The tile ID of the task Pixel 2 cluster: The tile ID and patch concatenated Compute: 0" newline bitfld.long 0x0 7.--8. "STATE,Queue state for entry" "0,1,2,3" newline bitfld.long 0x0 6. "NEW_SD,This task is at the start of a new SD group bit is cleared when the task is first run" "0,1" newline bitfld.long 0x0 5. "TFPU_CS_ED,This task is waiting for a TFPU strobe which has not been satisfied" "0,1" newline bitfld.long 0x0 4. "MCU_CS_ED,This task is waiting for an MCU CS strobe which has not been satisfied" "0,1" newline bitfld.long 0x0 3. "MCU_US_ED,This task is waiting for an MCU US strobe which has not been satisfied" "0,1" newline bitfld.long 0x0 2. "FRAG_TYPE,Is this task a work or state loading type. '1' indicates a Vertex/Fragment/Work type '0' indicates a Shared/ Coefficient/ Control type" "0,1" newline bitfld.long 0x0 1. "PHAS_ISSUE,This task must issue a PHAS instruction which has not yet been seen" "0,1" newline bitfld.long 0x0 0. "PASS_GROUP,Is the task the start of a new pass group" "0,1" line.long 0x4 "RGX_CR_USC_OLDEST_TASK_STATUS_1,RGX_CR_USC_OLDEST_TASK_STATUS_1" hexmask.long 0x4 0.--31. 1. "Reserved_20,Reserved_20" line.long 0x8 "RGX_CR_USC_PARTITION_TILE_STATUS0_0,RGX_CR_USC_PARTITION_TILE_STATUS0_0" bitfld.long 0x8 30.--31. "TILE_ID5,Tile ID for partition 5" "0,1,2,3" newline hexmask.long.byte 0x8 24.--29. 1. "TILE_ID4,Tile ID for partition 4" newline hexmask.long.byte 0x8 18.--23. 1. "TILE_ID3,Tile ID for partition 3" newline hexmask.long.byte 0x8 12.--17. 1. "TILE_ID2,Tile ID for partition 2" newline hexmask.long.byte 0x8 6.--11. 1. "TILE_ID1,Tile ID for partition 1" newline hexmask.long.byte 0x8 0.--5. 1. "TILE_ID0,Tile ID for partition 0" line.long 0xC "RGX_CR_USC_PARTITION_TILE_STATUS0_1,RGX_CR_USC_PARTITION_TILE_STATUS0_1" hexmask.long.word 0xC 16.--31. 1. "Reserved_48,Reserved_48" newline hexmask.long.byte 0xC 10.--15. 1. "TILE_ID7,Tile ID for partition 7" newline hexmask.long.byte 0xC 4.--9. 1. "TILE_ID6,Tile ID for partition 6" newline hexmask.long.byte 0xC 0.--3. 1. "TILE_ID5,Tile ID for partition 5" line.long 0x10 "RGX_CR_USC_PARTITION_TILE_STATUS1_0,RGX_CR_USC_PARTITION_TILE_STATUS1_0" bitfld.long 0x10 30.--31. "TILE_ID13,Tile ID for partition 13" "0,1,2,3" newline hexmask.long.byte 0x10 24.--29. 1. "TILE_ID12,Tile ID for partition 12" newline hexmask.long.byte 0x10 18.--23. 1. "TILE_ID11,Tile ID for partition 11" newline hexmask.long.byte 0x10 12.--17. 1. "TILE_ID10,Tile ID for partition 10" newline hexmask.long.byte 0x10 6.--11. 1. "TILE_ID9,Tile ID for partition 9" newline hexmask.long.byte 0x10 0.--5. 1. "TILE_ID8,Tile ID for partition 8" line.long 0x14 "RGX_CR_USC_PARTITION_TILE_STATUS1_1,RGX_CR_USC_PARTITION_TILE_STATUS1_1" hexmask.long.byte 0x14 28.--31. 1. "Reserved_60,Reserved_60" newline hexmask.long.byte 0x14 22.--27. 1. "TILE_ID17,Tile ID for partition 17" newline hexmask.long.byte 0x14 16.--21. 1. "TILE_ID16,Tile ID for partition 16" newline hexmask.long.byte 0x14 10.--15. 1. "TILE_ID15,Tile ID for partition 15" newline hexmask.long.byte 0x14 4.--9. 1. "TILE_ID14,Tile ID for partition 14" newline hexmask.long.byte 0x14 0.--3. 1. "TILE_ID13,Tile ID for partition 13" repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) rgroup.long ($2+0x4178)++0x3 line.long 0x0 "RGX_CR_USC_DM_SLOT0_$1,Cluster Data Master in Slots" hexmask.long.byte 0x0 28.--31. 1. "SLOT_7,SLOT_7" newline hexmask.long.byte 0x0 24.--27. 1. "SLOT_6,SLOT_6" newline hexmask.long.byte 0x0 20.--23. 1. "SLOT_5,SLOT_5" newline hexmask.long.byte 0x0 16.--19. 1. "SLOT_4,SLOT_4" newline hexmask.long.byte 0x0 12.--15. 1. "SLOT_3,SLOT_3" newline hexmask.long.byte 0x0 8.--11. 1. "SLOT_2,SLOT_2" newline hexmask.long.byte 0x0 4.--7. 1. "SLOT_1,SLOT_1" newline hexmask.long.byte 0x0 0.--3. 1. "SLOT_0,SLOT_0" repeat.end repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) rgroup.long ($2+0x4180)++0x3 line.long 0x0 "RGX_CR_USC_DM_SLOT1_$1,Cluster Data Master in Slots" hexmask.long.byte 0x0 28.--31. 1. "SLOT_7,SLOT_7" newline hexmask.long.byte 0x0 24.--27. 1. "SLOT_6,SLOT_6" newline hexmask.long.byte 0x0 20.--23. 1. "SLOT_5,SLOT_5" newline hexmask.long.byte 0x0 16.--19. 1. "SLOT_4,SLOT_4" newline hexmask.long.byte 0x0 12.--15. 1. "SLOT_3,SLOT_3" newline hexmask.long.byte 0x0 8.--11. 1. "SLOT_2,SLOT_2" newline hexmask.long.byte 0x0 4.--7. 1. "SLOT_1,SLOT_1" newline hexmask.long.byte 0x0 0.--3. 1. "SLOT_0,SLOT_0" repeat.end repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) rgroup.long ($2+0x4188)++0x3 line.long 0x0 "RGX_CR_USC_DM_SLOT2_$1,Cluster Data Master in Slots" hexmask.long.byte 0x0 28.--31. 1. "SLOT_7,SLOT_7" newline hexmask.long.byte 0x0 24.--27. 1. "SLOT_6,SLOT_6" newline hexmask.long.byte 0x0 20.--23. 1. "SLOT_5,SLOT_5" newline hexmask.long.byte 0x0 16.--19. 1. "SLOT_4,SLOT_4" newline hexmask.long.byte 0x0 12.--15. 1. "SLOT_3,SLOT_3" newline hexmask.long.byte 0x0 8.--11. 1. "SLOT_2,SLOT_2" newline hexmask.long.byte 0x0 4.--7. 1. "SLOT_1,SLOT_1" newline hexmask.long.byte 0x0 0.--3. 1. "SLOT_0,SLOT_0" repeat.end repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) rgroup.long ($2+0x4190)++0x3 line.long 0x0 "RGX_CR_USC_DM_SLOT3_$1,Cluster Data Master in Slots" hexmask.long.byte 0x0 28.--31. 1. "SLOT_7,SLOT_7" newline hexmask.long.byte 0x0 24.--27. 1. "SLOT_6,SLOT_6" newline hexmask.long.byte 0x0 20.--23. 1. "SLOT_5,SLOT_5" newline hexmask.long.byte 0x0 16.--19. 1. "SLOT_4,SLOT_4" newline hexmask.long.byte 0x0 12.--15. 1. "SLOT_3,SLOT_3" newline hexmask.long.byte 0x0 8.--11. 1. "SLOT_2,SLOT_2" newline hexmask.long.byte 0x0 4.--7. 1. "SLOT_1,SLOT_1" newline hexmask.long.byte 0x0 0.--3. 1. "SLOT_0,SLOT_0" repeat.end rgroup.long 0x41B8++0x7 line.long 0x0 "RGX_CR_USC_EXCEPTION_0,RGX_CR_USC_EXCEPTION_0" hexmask.long.word 0x0 16.--31. 1. "CODE,Cluster exception code" newline hexmask.long.word 0x0 1.--15. 1. "Reserved_1,Reserved_1" newline bitfld.long 0x0 0. "STATUS,1=Cluster has raised an exception" "?,Cluster has raised an exception" line.long 0x4 "RGX_CR_USC_EXCEPTION_1,RGX_CR_USC_EXCEPTION_1" hexmask.long 0x4 0.--31. 1. "Reserved_32,Reserved_32" rgroup.long 0x41D8++0xFF line.long 0x0 "RGX_CR_USC_SLOT0_0,RGX_CR_USC_SLOT0_0" hexmask.long 0x0 1.--31. 1. "PC,PC" newline bitfld.long 0x0 0. "Reserved_0,Reserved_0" "0,1" line.long 0x4 "RGX_CR_USC_SLOT0_1,RGX_CR_USC_SLOT0_1" hexmask.long 0x4 4.--31. 1. "Reserved_36,Reserved_36" newline hexmask.long.byte 0x4 0.--3. 1. "STATUS,STATUS" line.long 0x8 "RGX_CR_USC_SLOT1_0,RGX_CR_USC_SLOT1_0" hexmask.long 0x8 1.--31. 1. "PC,PC" newline bitfld.long 0x8 0. "Reserved_0,Reserved_0" "0,1" line.long 0xC "RGX_CR_USC_SLOT1_1,RGX_CR_USC_SLOT1_1" hexmask.long 0xC 4.--31. 1. "Reserved_36,Reserved_36" newline hexmask.long.byte 0xC 0.--3. 1. "STATUS,STATUS" line.long 0x10 "RGX_CR_USC_SLOT2_0,RGX_CR_USC_SLOT2_0" hexmask.long 0x10 1.--31. 1. "PC,PC" newline bitfld.long 0x10 0. "Reserved_0,Reserved_0" "0,1" line.long 0x14 "RGX_CR_USC_SLOT2_1,RGX_CR_USC_SLOT2_1" hexmask.long 0x14 4.--31. 1. "Reserved_36,Reserved_36" newline hexmask.long.byte 0x14 0.--3. 1. "STATUS,STATUS" line.long 0x18 "RGX_CR_USC_SLOT3_0,RGX_CR_USC_SLOT3_0" hexmask.long 0x18 1.--31. 1. "PC,PC" newline bitfld.long 0x18 0. "Reserved_0,Reserved_0" "0,1" line.long 0x1C "RGX_CR_USC_SLOT3_1,RGX_CR_USC_SLOT3_1" hexmask.long 0x1C 4.--31. 1. "Reserved_36,Reserved_36" newline hexmask.long.byte 0x1C 0.--3. 1. "STATUS,STATUS" line.long 0x20 "RGX_CR_USC_SLOT4_0,RGX_CR_USC_SLOT4_0" hexmask.long 0x20 1.--31. 1. "PC,PC" newline bitfld.long 0x20 0. "Reserved_0,Reserved_0" "0,1" line.long 0x24 "RGX_CR_USC_SLOT4_1,RGX_CR_USC_SLOT4_1" hexmask.long 0x24 4.--31. 1. "Reserved_36,Reserved_36" newline hexmask.long.byte 0x24 0.--3. 1. "STATUS,STATUS" line.long 0x28 "RGX_CR_USC_SLOT5_0,RGX_CR_USC_SLOT5_0" hexmask.long 0x28 1.--31. 1. "PC,PC" newline bitfld.long 0x28 0. "Reserved_0,Reserved_0" "0,1" line.long 0x2C "RGX_CR_USC_SLOT5_1,RGX_CR_USC_SLOT5_1" hexmask.long 0x2C 4.--31. 1. "Reserved_36,Reserved_36" newline hexmask.long.byte 0x2C 0.--3. 1. "STATUS,STATUS" line.long 0x30 "RGX_CR_USC_SLOT6_0,RGX_CR_USC_SLOT6_0" hexmask.long 0x30 1.--31. 1. "PC,PC" newline bitfld.long 0x30 0. "Reserved_0,Reserved_0" "0,1" line.long 0x34 "RGX_CR_USC_SLOT6_1,RGX_CR_USC_SLOT6_1" hexmask.long 0x34 4.--31. 1. "Reserved_36,Reserved_36" newline hexmask.long.byte 0x34 0.--3. 1. "STATUS,STATUS" line.long 0x38 "RGX_CR_USC_SLOT7_0,RGX_CR_USC_SLOT7_0" hexmask.long 0x38 1.--31. 1. "PC,PC" newline bitfld.long 0x38 0. "Reserved_0,Reserved_0" "0,1" line.long 0x3C "RGX_CR_USC_SLOT7_1,RGX_CR_USC_SLOT7_1" hexmask.long 0x3C 4.--31. 1. "Reserved_36,Reserved_36" newline hexmask.long.byte 0x3C 0.--3. 1. "STATUS,STATUS" line.long 0x40 "RGX_CR_USC_SLOT8_0,RGX_CR_USC_SLOT8_0" hexmask.long 0x40 1.--31. 1. "PC,PC" newline bitfld.long 0x40 0. "Reserved_0,Reserved_0" "0,1" line.long 0x44 "RGX_CR_USC_SLOT8_1,RGX_CR_USC_SLOT8_1" hexmask.long 0x44 4.--31. 1. "Reserved_36,Reserved_36" newline hexmask.long.byte 0x44 0.--3. 1. "STATUS,STATUS" line.long 0x48 "RGX_CR_USC_SLOT9_0,RGX_CR_USC_SLOT9_0" hexmask.long 0x48 1.--31. 1. "PC,PC" newline bitfld.long 0x48 0. "Reserved_0,Reserved_0" "0,1" line.long 0x4C "RGX_CR_USC_SLOT9_1,RGX_CR_USC_SLOT9_1" hexmask.long 0x4C 4.--31. 1. "Reserved_36,Reserved_36" newline hexmask.long.byte 0x4C 0.--3. 1. "STATUS,STATUS" line.long 0x50 "RGX_CR_USC_SLOT10_0,RGX_CR_USC_SLOT10_0" hexmask.long 0x50 1.--31. 1. "PC,PC" newline bitfld.long 0x50 0. "Reserved_0,Reserved_0" "0,1" line.long 0x54 "RGX_CR_USC_SLOT10_1,RGX_CR_USC_SLOT10_1" hexmask.long 0x54 4.--31. 1. "Reserved_36,Reserved_36" newline hexmask.long.byte 0x54 0.--3. 1. "STATUS,STATUS" line.long 0x58 "RGX_CR_USC_SLOT11_0,RGX_CR_USC_SLOT11_0" hexmask.long 0x58 1.--31. 1. "PC,PC" newline bitfld.long 0x58 0. "Reserved_0,Reserved_0" "0,1" line.long 0x5C "RGX_CR_USC_SLOT11_1,RGX_CR_USC_SLOT11_1" hexmask.long 0x5C 4.--31. 1. "Reserved_36,Reserved_36" newline hexmask.long.byte 0x5C 0.--3. 1. "STATUS,STATUS" line.long 0x60 "RGX_CR_USC_SLOT12_0,RGX_CR_USC_SLOT12_0" hexmask.long 0x60 1.--31. 1. "PC,PC" newline bitfld.long 0x60 0. "Reserved_0,Reserved_0" "0,1" line.long 0x64 "RGX_CR_USC_SLOT12_1,RGX_CR_USC_SLOT12_1" hexmask.long 0x64 4.--31. 1. "Reserved_36,Reserved_36" newline hexmask.long.byte 0x64 0.--3. 1. "STATUS,STATUS" line.long 0x68 "RGX_CR_USC_SLOT13_0,RGX_CR_USC_SLOT13_0" hexmask.long 0x68 1.--31. 1. "PC,PC" newline bitfld.long 0x68 0. "Reserved_0,Reserved_0" "0,1" line.long 0x6C "RGX_CR_USC_SLOT13_1,RGX_CR_USC_SLOT13_1" hexmask.long 0x6C 4.--31. 1. "Reserved_36,Reserved_36" newline hexmask.long.byte 0x6C 0.--3. 1. "STATUS,STATUS" line.long 0x70 "RGX_CR_USC_SLOT14_0,RGX_CR_USC_SLOT14_0" hexmask.long 0x70 1.--31. 1. "PC,PC" newline bitfld.long 0x70 0. "Reserved_0,Reserved_0" "0,1" line.long 0x74 "RGX_CR_USC_SLOT14_1,RGX_CR_USC_SLOT14_1" hexmask.long 0x74 4.--31. 1. "Reserved_36,Reserved_36" newline hexmask.long.byte 0x74 0.--3. 1. "STATUS,STATUS" line.long 0x78 "RGX_CR_USC_SLOT15_0,RGX_CR_USC_SLOT15_0" hexmask.long 0x78 1.--31. 1. "PC,PC" newline bitfld.long 0x78 0. "Reserved_0,Reserved_0" "0,1" line.long 0x7C "RGX_CR_USC_SLOT15_1,RGX_CR_USC_SLOT15_1" hexmask.long 0x7C 4.--31. 1. "Reserved_36,Reserved_36" newline hexmask.long.byte 0x7C 0.--3. 1. "STATUS,STATUS" line.long 0x80 "RGX_CR_USC_SLOT16_0,RGX_CR_USC_SLOT16_0" hexmask.long 0x80 1.--31. 1. "PC,PC" newline bitfld.long 0x80 0. "Reserved_0,Reserved_0" "0,1" line.long 0x84 "RGX_CR_USC_SLOT16_1,RGX_CR_USC_SLOT16_1" hexmask.long 0x84 4.--31. 1. "Reserved_36,Reserved_36" newline hexmask.long.byte 0x84 0.--3. 1. "STATUS,STATUS" line.long 0x88 "RGX_CR_USC_SLOT17_0,RGX_CR_USC_SLOT17_0" hexmask.long 0x88 1.--31. 1. "PC,PC" newline bitfld.long 0x88 0. "Reserved_0,Reserved_0" "0,1" line.long 0x8C "RGX_CR_USC_SLOT17_1,RGX_CR_USC_SLOT17_1" hexmask.long 0x8C 4.--31. 1. "Reserved_36,Reserved_36" newline hexmask.long.byte 0x8C 0.--3. 1. "STATUS,STATUS" line.long 0x90 "RGX_CR_USC_SLOT18_0,RGX_CR_USC_SLOT18_0" hexmask.long 0x90 1.--31. 1. "PC,PC" newline bitfld.long 0x90 0. "Reserved_0,Reserved_0" "0,1" line.long 0x94 "RGX_CR_USC_SLOT18_1,RGX_CR_USC_SLOT18_1" hexmask.long 0x94 4.--31. 1. "Reserved_36,Reserved_36" newline hexmask.long.byte 0x94 0.--3. 1. "STATUS,STATUS" line.long 0x98 "RGX_CR_USC_SLOT19_0,RGX_CR_USC_SLOT19_0" hexmask.long 0x98 1.--31. 1. "PC,PC" newline bitfld.long 0x98 0. "Reserved_0,Reserved_0" "0,1" line.long 0x9C "RGX_CR_USC_SLOT19_1,RGX_CR_USC_SLOT19_1" hexmask.long 0x9C 4.--31. 1. "Reserved_36,Reserved_36" newline hexmask.long.byte 0x9C 0.--3. 1. "STATUS,STATUS" line.long 0xA0 "RGX_CR_USC_SLOT20_0,RGX_CR_USC_SLOT20_0" hexmask.long 0xA0 1.--31. 1. "PC,PC" newline bitfld.long 0xA0 0. "Reserved_0,Reserved_0" "0,1" line.long 0xA4 "RGX_CR_USC_SLOT20_1,RGX_CR_USC_SLOT20_1" hexmask.long 0xA4 4.--31. 1. "Reserved_36,Reserved_36" newline hexmask.long.byte 0xA4 0.--3. 1. "STATUS,STATUS" line.long 0xA8 "RGX_CR_USC_SLOT21_0,RGX_CR_USC_SLOT21_0" hexmask.long 0xA8 1.--31. 1. "PC,PC" newline bitfld.long 0xA8 0. "Reserved_0,Reserved_0" "0,1" line.long 0xAC "RGX_CR_USC_SLOT21_1,RGX_CR_USC_SLOT21_1" hexmask.long 0xAC 4.--31. 1. "Reserved_36,Reserved_36" newline hexmask.long.byte 0xAC 0.--3. 1. "STATUS,STATUS" line.long 0xB0 "RGX_CR_USC_SLOT22_0,RGX_CR_USC_SLOT22_0" hexmask.long 0xB0 1.--31. 1. "PC,PC" newline bitfld.long 0xB0 0. "Reserved_0,Reserved_0" "0,1" line.long 0xB4 "RGX_CR_USC_SLOT22_1,RGX_CR_USC_SLOT22_1" hexmask.long 0xB4 4.--31. 1. "Reserved_36,Reserved_36" newline hexmask.long.byte 0xB4 0.--3. 1. "STATUS,STATUS" line.long 0xB8 "RGX_CR_USC_SLOT23_0,RGX_CR_USC_SLOT23_0" hexmask.long 0xB8 1.--31. 1. "PC,PC" newline bitfld.long 0xB8 0. "Reserved_0,Reserved_0" "0,1" line.long 0xBC "RGX_CR_USC_SLOT23_1,RGX_CR_USC_SLOT23_1" hexmask.long 0xBC 4.--31. 1. "Reserved_36,Reserved_36" newline hexmask.long.byte 0xBC 0.--3. 1. "STATUS,STATUS" line.long 0xC0 "RGX_CR_USC_SLOT24_0,RGX_CR_USC_SLOT24_0" hexmask.long 0xC0 1.--31. 1. "PC,PC" newline bitfld.long 0xC0 0. "Reserved_0,Reserved_0" "0,1" line.long 0xC4 "RGX_CR_USC_SLOT24_1,RGX_CR_USC_SLOT24_1" hexmask.long 0xC4 4.--31. 1. "Reserved_36,Reserved_36" newline hexmask.long.byte 0xC4 0.--3. 1. "STATUS,STATUS" line.long 0xC8 "RGX_CR_USC_SLOT25_0,RGX_CR_USC_SLOT25_0" hexmask.long 0xC8 1.--31. 1. "PC,PC" newline bitfld.long 0xC8 0. "Reserved_0,Reserved_0" "0,1" line.long 0xCC "RGX_CR_USC_SLOT25_1,RGX_CR_USC_SLOT25_1" hexmask.long 0xCC 4.--31. 1. "Reserved_36,Reserved_36" newline hexmask.long.byte 0xCC 0.--3. 1. "STATUS,STATUS" line.long 0xD0 "RGX_CR_USC_SLOT26_0,RGX_CR_USC_SLOT26_0" hexmask.long 0xD0 1.--31. 1. "PC,PC" newline bitfld.long 0xD0 0. "Reserved_0,Reserved_0" "0,1" line.long 0xD4 "RGX_CR_USC_SLOT26_1,RGX_CR_USC_SLOT26_1" hexmask.long 0xD4 4.--31. 1. "Reserved_36,Reserved_36" newline hexmask.long.byte 0xD4 0.--3. 1. "STATUS,STATUS" line.long 0xD8 "RGX_CR_USC_SLOT27_0,RGX_CR_USC_SLOT27_0" hexmask.long 0xD8 1.--31. 1. "PC,PC" newline bitfld.long 0xD8 0. "Reserved_0,Reserved_0" "0,1" line.long 0xDC "RGX_CR_USC_SLOT27_1,RGX_CR_USC_SLOT27_1" hexmask.long 0xDC 4.--31. 1. "Reserved_36,Reserved_36" newline hexmask.long.byte 0xDC 0.--3. 1. "STATUS,STATUS" line.long 0xE0 "RGX_CR_USC_SLOT28_0,RGX_CR_USC_SLOT28_0" hexmask.long 0xE0 1.--31. 1. "PC,PC" newline bitfld.long 0xE0 0. "Reserved_0,Reserved_0" "0,1" line.long 0xE4 "RGX_CR_USC_SLOT28_1,RGX_CR_USC_SLOT28_1" hexmask.long 0xE4 4.--31. 1. "Reserved_36,Reserved_36" newline hexmask.long.byte 0xE4 0.--3. 1. "STATUS,STATUS" line.long 0xE8 "RGX_CR_USC_SLOT29_0,RGX_CR_USC_SLOT29_0" hexmask.long 0xE8 1.--31. 1. "PC,PC" newline bitfld.long 0xE8 0. "Reserved_0,Reserved_0" "0,1" line.long 0xEC "RGX_CR_USC_SLOT29_1,RGX_CR_USC_SLOT29_1" hexmask.long 0xEC 4.--31. 1. "Reserved_36,Reserved_36" newline hexmask.long.byte 0xEC 0.--3. 1. "STATUS,STATUS" line.long 0xF0 "RGX_CR_USC_SLOT30_0,RGX_CR_USC_SLOT30_0" hexmask.long 0xF0 1.--31. 1. "PC,PC" newline bitfld.long 0xF0 0. "Reserved_0,Reserved_0" "0,1" line.long 0xF4 "RGX_CR_USC_SLOT30_1,RGX_CR_USC_SLOT30_1" hexmask.long 0xF4 4.--31. 1. "Reserved_36,Reserved_36" newline hexmask.long.byte 0xF4 0.--3. 1. "STATUS,STATUS" line.long 0xF8 "RGX_CR_USC_SLOT31_0,RGX_CR_USC_SLOT31_0" hexmask.long 0xF8 1.--31. 1. "PC,PC" newline bitfld.long 0xF8 0. "Reserved_0,Reserved_0" "0,1" line.long 0xFC "RGX_CR_USC_SLOT31_1,RGX_CR_USC_SLOT31_1" hexmask.long 0xFC 4.--31. 1. "Reserved_36,Reserved_36" newline hexmask.long.byte 0xFC 0.--3. 1. "STATUS,STATUS" repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) group.long ($2+0x42E0)++0x3 line.long 0x0 "RGX_CR_USC_CLEAR_REGISTER4_$1,RGX_CR_USC_CLEAR_REGISTER4_0" hexmask.long 0x0 0.--31. 1. "VAL,Clear Colour register 4" repeat.end repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) group.long ($2+0x42E8)++0x3 line.long 0x0 "RGX_CR_USC_CLEAR_REGISTER5_$1,RGX_CR_USC_CLEAR_REGISTER5_0" hexmask.long 0x0 0.--31. 1. "VAL,Clear Colour register 5" repeat.end repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) group.long ($2+0x42F0)++0x3 line.long 0x0 "RGX_CR_USC_CLEAR_REGISTER6_$1,RGX_CR_USC_CLEAR_REGISTER6_0" hexmask.long 0x0 0.--31. 1. "VAL,Clear Colour register 6" repeat.end repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) group.long ($2+0x42F8)++0x3 line.long 0x0 "RGX_CR_USC_CLEAR_REGISTER7_$1,RGX_CR_USC_CLEAR_REGISTER7_0" hexmask.long 0x0 0.--31. 1. "VAL,Clear Colour register 7" repeat.end rgroup.long 0x4300++0xFF line.long 0x0 "RGX_CR_USC_SLOT32_0,RGX_CR_USC_SLOT32_0" hexmask.long 0x0 1.--31. 1. "PC,PC" newline bitfld.long 0x0 0. "Reserved_0,Reserved_0" "0,1" line.long 0x4 "RGX_CR_USC_SLOT32_1,RGX_CR_USC_SLOT32_1" hexmask.long 0x4 4.--31. 1. "Reserved_36,Reserved_36" newline hexmask.long.byte 0x4 0.--3. 1. "STATUS,STATUS" line.long 0x8 "RGX_CR_USC_SLOT33_0,RGX_CR_USC_SLOT33_0" hexmask.long 0x8 1.--31. 1. "PC,PC" newline bitfld.long 0x8 0. "Reserved_0,Reserved_0" "0,1" line.long 0xC "RGX_CR_USC_SLOT33_1,RGX_CR_USC_SLOT33_1" hexmask.long 0xC 4.--31. 1. "Reserved_36,Reserved_36" newline hexmask.long.byte 0xC 0.--3. 1. "STATUS,STATUS" line.long 0x10 "RGX_CR_USC_SLOT34_0,RGX_CR_USC_SLOT34_0" hexmask.long 0x10 1.--31. 1. "PC,PC" newline bitfld.long 0x10 0. "Reserved_0,Reserved_0" "0,1" line.long 0x14 "RGX_CR_USC_SLOT34_1,RGX_CR_USC_SLOT34_1" hexmask.long 0x14 4.--31. 1. "Reserved_36,Reserved_36" newline hexmask.long.byte 0x14 0.--3. 1. "STATUS,STATUS" line.long 0x18 "RGX_CR_USC_SLOT35_0,RGX_CR_USC_SLOT35_0" hexmask.long 0x18 1.--31. 1. "PC,PC" newline bitfld.long 0x18 0. "Reserved_0,Reserved_0" "0,1" line.long 0x1C "RGX_CR_USC_SLOT35_1,RGX_CR_USC_SLOT35_1" hexmask.long 0x1C 4.--31. 1. "Reserved_36,Reserved_36" newline hexmask.long.byte 0x1C 0.--3. 1. "STATUS,STATUS" line.long 0x20 "RGX_CR_USC_SLOT36_0,RGX_CR_USC_SLOT36_0" hexmask.long 0x20 1.--31. 1. "PC,PC" newline bitfld.long 0x20 0. "Reserved_0,Reserved_0" "0,1" line.long 0x24 "RGX_CR_USC_SLOT36_1,RGX_CR_USC_SLOT36_1" hexmask.long 0x24 4.--31. 1. "Reserved_36,Reserved_36" newline hexmask.long.byte 0x24 0.--3. 1. "STATUS,STATUS" line.long 0x28 "RGX_CR_USC_SLOT37_0,RGX_CR_USC_SLOT37_0" hexmask.long 0x28 1.--31. 1. "PC,PC" newline bitfld.long 0x28 0. "Reserved_0,Reserved_0" "0,1" line.long 0x2C "RGX_CR_USC_SLOT37_1,RGX_CR_USC_SLOT37_1" hexmask.long 0x2C 4.--31. 1. "Reserved_36,Reserved_36" newline hexmask.long.byte 0x2C 0.--3. 1. "STATUS,STATUS" line.long 0x30 "RGX_CR_USC_SLOT38_0,RGX_CR_USC_SLOT38_0" hexmask.long 0x30 1.--31. 1. "PC,PC" newline bitfld.long 0x30 0. "Reserved_0,Reserved_0" "0,1" line.long 0x34 "RGX_CR_USC_SLOT38_1,RGX_CR_USC_SLOT38_1" hexmask.long 0x34 4.--31. 1. "Reserved_36,Reserved_36" newline hexmask.long.byte 0x34 0.--3. 1. "STATUS,STATUS" line.long 0x38 "RGX_CR_USC_SLOT39_0,RGX_CR_USC_SLOT39_0" hexmask.long 0x38 1.--31. 1. "PC,PC" newline bitfld.long 0x38 0. "Reserved_0,Reserved_0" "0,1" line.long 0x3C "RGX_CR_USC_SLOT39_1,RGX_CR_USC_SLOT39_1" hexmask.long 0x3C 4.--31. 1. "Reserved_36,Reserved_36" newline hexmask.long.byte 0x3C 0.--3. 1. "STATUS,STATUS" line.long 0x40 "RGX_CR_USC_SLOT40_0,RGX_CR_USC_SLOT40_0" hexmask.long 0x40 1.--31. 1. "PC,PC" newline bitfld.long 0x40 0. "Reserved_0,Reserved_0" "0,1" line.long 0x44 "RGX_CR_USC_SLOT40_1,RGX_CR_USC_SLOT40_1" hexmask.long 0x44 4.--31. 1. "Reserved_36,Reserved_36" newline hexmask.long.byte 0x44 0.--3. 1. "STATUS,STATUS" line.long 0x48 "RGX_CR_USC_SLOT41_0,RGX_CR_USC_SLOT41_0" hexmask.long 0x48 1.--31. 1. "PC,PC" newline bitfld.long 0x48 0. "Reserved_0,Reserved_0" "0,1" line.long 0x4C "RGX_CR_USC_SLOT41_1,RGX_CR_USC_SLOT41_1" hexmask.long 0x4C 4.--31. 1. "Reserved_36,Reserved_36" newline hexmask.long.byte 0x4C 0.--3. 1. "STATUS,STATUS" line.long 0x50 "RGX_CR_USC_SLOT42_0,RGX_CR_USC_SLOT42_0" hexmask.long 0x50 1.--31. 1. "PC,PC" newline bitfld.long 0x50 0. "Reserved_0,Reserved_0" "0,1" line.long 0x54 "RGX_CR_USC_SLOT42_1,RGX_CR_USC_SLOT42_1" hexmask.long 0x54 4.--31. 1. "Reserved_36,Reserved_36" newline hexmask.long.byte 0x54 0.--3. 1. "STATUS,STATUS" line.long 0x58 "RGX_CR_USC_SLOT43_0,RGX_CR_USC_SLOT43_0" hexmask.long 0x58 1.--31. 1. "PC,PC" newline bitfld.long 0x58 0. "Reserved_0,Reserved_0" "0,1" line.long 0x5C "RGX_CR_USC_SLOT43_1,RGX_CR_USC_SLOT43_1" hexmask.long 0x5C 4.--31. 1. "Reserved_36,Reserved_36" newline hexmask.long.byte 0x5C 0.--3. 1. "STATUS,STATUS" line.long 0x60 "RGX_CR_USC_SLOT44_0,RGX_CR_USC_SLOT44_0" hexmask.long 0x60 1.--31. 1. "PC,PC" newline bitfld.long 0x60 0. "Reserved_0,Reserved_0" "0,1" line.long 0x64 "RGX_CR_USC_SLOT44_1,RGX_CR_USC_SLOT44_1" hexmask.long 0x64 4.--31. 1. "Reserved_36,Reserved_36" newline hexmask.long.byte 0x64 0.--3. 1. "STATUS,STATUS" line.long 0x68 "RGX_CR_USC_SLOT45_0,RGX_CR_USC_SLOT45_0" hexmask.long 0x68 1.--31. 1. "PC,PC" newline bitfld.long 0x68 0. "Reserved_0,Reserved_0" "0,1" line.long 0x6C "RGX_CR_USC_SLOT45_1,RGX_CR_USC_SLOT45_1" hexmask.long 0x6C 4.--31. 1. "Reserved_36,Reserved_36" newline hexmask.long.byte 0x6C 0.--3. 1. "STATUS,STATUS" line.long 0x70 "RGX_CR_USC_SLOT46_0,RGX_CR_USC_SLOT46_0" hexmask.long 0x70 1.--31. 1. "PC,PC" newline bitfld.long 0x70 0. "Reserved_0,Reserved_0" "0,1" line.long 0x74 "RGX_CR_USC_SLOT46_1,RGX_CR_USC_SLOT46_1" hexmask.long 0x74 4.--31. 1. "Reserved_36,Reserved_36" newline hexmask.long.byte 0x74 0.--3. 1. "STATUS,STATUS" line.long 0x78 "RGX_CR_USC_SLOT47_0,RGX_CR_USC_SLOT47_0" hexmask.long 0x78 1.--31. 1. "PC,PC" newline bitfld.long 0x78 0. "Reserved_0,Reserved_0" "0,1" line.long 0x7C "RGX_CR_USC_SLOT47_1,RGX_CR_USC_SLOT47_1" hexmask.long 0x7C 4.--31. 1. "Reserved_36,Reserved_36" newline hexmask.long.byte 0x7C 0.--3. 1. "STATUS,STATUS" line.long 0x80 "RGX_CR_USC_SLOT48_0,RGX_CR_USC_SLOT48_0" hexmask.long 0x80 1.--31. 1. "PC,PC" newline bitfld.long 0x80 0. "Reserved_0,Reserved_0" "0,1" line.long 0x84 "RGX_CR_USC_SLOT48_1,RGX_CR_USC_SLOT48_1" hexmask.long 0x84 4.--31. 1. "Reserved_36,Reserved_36" newline hexmask.long.byte 0x84 0.--3. 1. "STATUS,STATUS" line.long 0x88 "RGX_CR_USC_SLOT49_0,RGX_CR_USC_SLOT49_0" hexmask.long 0x88 1.--31. 1. "PC,PC" newline bitfld.long 0x88 0. "Reserved_0,Reserved_0" "0,1" line.long 0x8C "RGX_CR_USC_SLOT49_1,RGX_CR_USC_SLOT49_1" hexmask.long 0x8C 4.--31. 1. "Reserved_36,Reserved_36" newline hexmask.long.byte 0x8C 0.--3. 1. "STATUS,STATUS" line.long 0x90 "RGX_CR_USC_SLOT50_0,RGX_CR_USC_SLOT50_0" hexmask.long 0x90 1.--31. 1. "PC,PC" newline bitfld.long 0x90 0. "Reserved_0,Reserved_0" "0,1" line.long 0x94 "RGX_CR_USC_SLOT50_1,RGX_CR_USC_SLOT50_1" hexmask.long 0x94 4.--31. 1. "Reserved_36,Reserved_36" newline hexmask.long.byte 0x94 0.--3. 1. "STATUS,STATUS" line.long 0x98 "RGX_CR_USC_SLOT51_0,RGX_CR_USC_SLOT51_0" hexmask.long 0x98 1.--31. 1. "PC,PC" newline bitfld.long 0x98 0. "Reserved_0,Reserved_0" "0,1" line.long 0x9C "RGX_CR_USC_SLOT51_1,RGX_CR_USC_SLOT51_1" hexmask.long 0x9C 4.--31. 1. "Reserved_36,Reserved_36" newline hexmask.long.byte 0x9C 0.--3. 1. "STATUS,STATUS" line.long 0xA0 "RGX_CR_USC_SLOT52_0,RGX_CR_USC_SLOT52_0" hexmask.long 0xA0 1.--31. 1. "PC,PC" newline bitfld.long 0xA0 0. "Reserved_0,Reserved_0" "0,1" line.long 0xA4 "RGX_CR_USC_SLOT52_1,RGX_CR_USC_SLOT52_1" hexmask.long 0xA4 4.--31. 1. "Reserved_36,Reserved_36" newline hexmask.long.byte 0xA4 0.--3. 1. "STATUS,STATUS" line.long 0xA8 "RGX_CR_USC_SLOT53_0,RGX_CR_USC_SLOT53_0" hexmask.long 0xA8 1.--31. 1. "PC,PC" newline bitfld.long 0xA8 0. "Reserved_0,Reserved_0" "0,1" line.long 0xAC "RGX_CR_USC_SLOT53_1,RGX_CR_USC_SLOT53_1" hexmask.long 0xAC 4.--31. 1. "Reserved_36,Reserved_36" newline hexmask.long.byte 0xAC 0.--3. 1. "STATUS,STATUS" line.long 0xB0 "RGX_CR_USC_SLOT54_0,RGX_CR_USC_SLOT54_0" hexmask.long 0xB0 1.--31. 1. "PC,PC" newline bitfld.long 0xB0 0. "Reserved_0,Reserved_0" "0,1" line.long 0xB4 "RGX_CR_USC_SLOT54_1,RGX_CR_USC_SLOT54_1" hexmask.long 0xB4 4.--31. 1. "Reserved_36,Reserved_36" newline hexmask.long.byte 0xB4 0.--3. 1. "STATUS,STATUS" line.long 0xB8 "RGX_CR_USC_SLOT55_0,RGX_CR_USC_SLOT55_0" hexmask.long 0xB8 1.--31. 1. "PC,PC" newline bitfld.long 0xB8 0. "Reserved_0,Reserved_0" "0,1" line.long 0xBC "RGX_CR_USC_SLOT55_1,RGX_CR_USC_SLOT55_1" hexmask.long 0xBC 4.--31. 1. "Reserved_36,Reserved_36" newline hexmask.long.byte 0xBC 0.--3. 1. "STATUS,STATUS" line.long 0xC0 "RGX_CR_USC_SLOT56_0,RGX_CR_USC_SLOT56_0" hexmask.long 0xC0 1.--31. 1. "PC,PC" newline bitfld.long 0xC0 0. "Reserved_0,Reserved_0" "0,1" line.long 0xC4 "RGX_CR_USC_SLOT56_1,RGX_CR_USC_SLOT56_1" hexmask.long 0xC4 4.--31. 1. "Reserved_36,Reserved_36" newline hexmask.long.byte 0xC4 0.--3. 1. "STATUS,STATUS" line.long 0xC8 "RGX_CR_USC_SLOT57_0,RGX_CR_USC_SLOT57_0" hexmask.long 0xC8 1.--31. 1. "PC,PC" newline bitfld.long 0xC8 0. "Reserved_0,Reserved_0" "0,1" line.long 0xCC "RGX_CR_USC_SLOT57_1,RGX_CR_USC_SLOT57_1" hexmask.long 0xCC 4.--31. 1. "Reserved_36,Reserved_36" newline hexmask.long.byte 0xCC 0.--3. 1. "STATUS,STATUS" line.long 0xD0 "RGX_CR_USC_SLOT58_0,RGX_CR_USC_SLOT58_0" hexmask.long 0xD0 1.--31. 1. "PC,PC" newline bitfld.long 0xD0 0. "Reserved_0,Reserved_0" "0,1" line.long 0xD4 "RGX_CR_USC_SLOT58_1,RGX_CR_USC_SLOT58_1" hexmask.long 0xD4 4.--31. 1. "Reserved_36,Reserved_36" newline hexmask.long.byte 0xD4 0.--3. 1. "STATUS,STATUS" line.long 0xD8 "RGX_CR_USC_SLOT59_0,RGX_CR_USC_SLOT59_0" hexmask.long 0xD8 1.--31. 1. "PC,PC" newline bitfld.long 0xD8 0. "Reserved_0,Reserved_0" "0,1" line.long 0xDC "RGX_CR_USC_SLOT59_1,RGX_CR_USC_SLOT59_1" hexmask.long 0xDC 4.--31. 1. "Reserved_36,Reserved_36" newline hexmask.long.byte 0xDC 0.--3. 1. "STATUS,STATUS" line.long 0xE0 "RGX_CR_USC_SLOT60_0,RGX_CR_USC_SLOT60_0" hexmask.long 0xE0 1.--31. 1. "PC,PC" newline bitfld.long 0xE0 0. "Reserved_0,Reserved_0" "0,1" line.long 0xE4 "RGX_CR_USC_SLOT60_1,RGX_CR_USC_SLOT60_1" hexmask.long 0xE4 4.--31. 1. "Reserved_36,Reserved_36" newline hexmask.long.byte 0xE4 0.--3. 1. "STATUS,STATUS" line.long 0xE8 "RGX_CR_USC_SLOT61_0,RGX_CR_USC_SLOT61_0" hexmask.long 0xE8 1.--31. 1. "PC,PC" newline bitfld.long 0xE8 0. "Reserved_0,Reserved_0" "0,1" line.long 0xEC "RGX_CR_USC_SLOT61_1,RGX_CR_USC_SLOT61_1" hexmask.long 0xEC 4.--31. 1. "Reserved_36,Reserved_36" newline hexmask.long.byte 0xEC 0.--3. 1. "STATUS,STATUS" line.long 0xF0 "RGX_CR_USC_SLOT62_0,RGX_CR_USC_SLOT62_0" hexmask.long 0xF0 1.--31. 1. "PC,PC" newline bitfld.long 0xF0 0. "Reserved_0,Reserved_0" "0,1" line.long 0xF4 "RGX_CR_USC_SLOT62_1,RGX_CR_USC_SLOT62_1" hexmask.long 0xF4 4.--31. 1. "Reserved_36,Reserved_36" newline hexmask.long.byte 0xF4 0.--3. 1. "STATUS,STATUS" line.long 0xF8 "RGX_CR_USC_SLOT63_0,RGX_CR_USC_SLOT63_0" hexmask.long 0xF8 1.--31. 1. "PC,PC" newline bitfld.long 0xF8 0. "Reserved_0,Reserved_0" "0,1" line.long 0xFC "RGX_CR_USC_SLOT63_1,RGX_CR_USC_SLOT63_1" hexmask.long 0xFC 4.--31. 1. "Reserved_36,Reserved_36" newline hexmask.long.byte 0xFC 0.--3. 1. "STATUS,STATUS" group.long 0x4500++0x17 line.long 0x0 "RGX_CR_USC_BREAKPOINT1_0,RGX_CR_USC_BREAKPOINT1_0" hexmask.long 0x0 1.--31. 1. "ADDR,Breakpoint Address" newline bitfld.long 0x0 0. "Reserved_0,Reserved_0" "0,1" line.long 0x4 "RGX_CR_USC_BREAKPOINT1_1,RGX_CR_USC_BREAKPOINT1_1" hexmask.long 0x4 0.--31. 1. "Reserved_32,Reserved_32" line.long 0x8 "RGX_CR_USC_BREAKPOINT1_HANDLER_0,RGX_CR_USC_BREAKPOINT1_HANDLER_0" hexmask.long 0x8 1.--31. 1. "ADDR,Breakpoint Handler Address" newline bitfld.long 0x8 0. "Reserved_0,Reserved_0" "0,1" line.long 0xC "RGX_CR_USC_BREAKPOINT1_HANDLER_1,RGX_CR_USC_BREAKPOINT1_HANDLER_1" hexmask.long 0xC 0.--31. 1. "Reserved_32,Reserved_32" line.long 0x10 "RGX_CR_USC_BREAKPOINT1_CTRL_0,RGX_CR_USC_BREAKPOINT1_CTRL_0" hexmask.long 0x10 4.--31. 1. "Reserved_4,Reserved_4" newline bitfld.long 0x10 3. "ENABLE,0 = Breakpoint disabled 1 = Breakpoint enabled" "Breakpoint disabled,Breakpoint enabled" newline bitfld.long 0x10 0.--2. "DM,Data Master of Breakpoint" "0,1,2,3,4,5,6,7" line.long 0x14 "RGX_CR_USC_BREAKPOINT1_CTRL_1,RGX_CR_USC_BREAKPOINT1_CTRL_1" hexmask.long 0x14 0.--31. 1. "Reserved_4,Reserved_4" rgroup.long 0x45D8++0x7 line.long 0x0 "RGX_CR_USC_IDLE_0,RGX_CR_USC_IDLE_0" hexmask.long.tbyte 0x0 10.--31. 1. "Reserved_10,Reserved_10" newline bitfld.long 0x0 9. "USCITR,USCITR idle" "0,1" newline bitfld.long 0x0 8. "USCDMA,USCDMA idle" "0,1" newline bitfld.long 0x0 7. "USCFS,USCFS idle" "0,1" newline bitfld.long 0x0 6. "USCCS,USCCS idle" "0,1" newline bitfld.long 0x0 5. "USCPD3,USCPD idle" "0,1" newline bitfld.long 0x0 4. "USCPD2,USCPD idle" "0,1" newline bitfld.long 0x0 3. "USCPD1,USCPD idle" "0,1" newline bitfld.long 0x0 2. "USCPD0,USCPD idle" "0,1" newline bitfld.long 0x0 1. "USCPC,USCPC idle" "0,1" newline bitfld.long 0x0 0. "USCC,USCC idle" "0,1" line.long 0x4 "RGX_CR_USC_IDLE_1,RGX_CR_USC_IDLE_1" hexmask.long 0x4 0.--31. 1. "Reserved_10,Reserved_10" group.long 0x45E8++0x17 line.long 0x0 "RGX_CR_USC_ITRCOEFF_CACHE_0,USC Iterator Coefficient Cache Bypass bit" hexmask.long 0x0 1.--31. 1. "Reserved_1,Reserved_1" newline bitfld.long 0x0 0. "BYPASS,Bypass bit of the coefficient cache" "0,1" line.long 0x4 "RGX_CR_USC_ITRCOEFF_CACHE_1,USC Iterator Coefficient Cache Bypass bit" hexmask.long 0x4 0.--31. 1. "Reserved_1,Reserved_1" line.long 0x8 "RGX_CR_USC_ITRSMP_STATE_CACHE_0,USC ITRSMP State Cache Bypass bit" hexmask.long 0x8 1.--31. 1. "Reserved_1,Reserved_1" newline bitfld.long 0x8 0. "BYPASS,Bypass bit of the state cache" "0,1" line.long 0xC "RGX_CR_USC_ITRSMP_STATE_CACHE_1,USC ITRSMP State Cache Bypass bit" hexmask.long 0xC 0.--31. 1. "Reserved_1,Reserved_1" line.long 0x10 "RGX_CR_USC_ITRSMP_PRIORITY_0,USC ITRSMP priority information" hexmask.long 0x10 2.--31. 1. "Reserved_2,Reserved_2" newline bitfld.long 0x10 0.--1. "PERSISTENCE,Persistence value to use for ITRSMP instructions." "0,1,2,3" line.long 0x14 "RGX_CR_USC_ITRSMP_PRIORITY_1,USC ITRSMP priority information" hexmask.long 0x14 0.--31. 1. "Reserved_2,Reserved_2" repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) rgroup.long ($2+0x4600)++0x3 line.long 0x0 "RGX_CR_USC_PWR_INSTR_$1,Peformance counter associated with Power Monitoring" hexmask.long 0x0 0.--31. 1. "EXEC,Number of instructions executed (max 1 per clock)" repeat.end repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) rgroup.long ($2+0x4608)++0x3 line.long 0x0 "RGX_CR_USC_PWR_CMMN_STR_ACCESS_$1,Peformance counter associated with Power Monitoring" hexmask.long 0x0 0.--31. 1. "COUNT,Number of Common Store accesses (max of 4 per lock)" repeat.end repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) rgroup.long ($2+0x4610)++0x3 line.long 0x0 "RGX_CR_USC_PWR_CMMN_STR_$1,Peformance counter associated with Power Monitoring" hexmask.long 0x0 0.--31. 1. "WR_BANK_CLASH,Common Store: Number of write/write bank clashes" repeat.end repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) rgroup.long ($2+0x4618)++0x3 line.long 0x0 "RGX_CR_USC_PWR_UNI_STR_$1,Peformance counter associated with Power Monitoring" hexmask.long 0x0 0.--31. 1. "WR_BANK_CLASH,Unified Store: Number of write/write bank clashes" repeat.end repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) rgroup.long ($2+0x4620)++0x3 line.long 0x0 "RGX_CR_USC_PWR_NUM_FLOAT_$1,Peformance counter associated with Power Monitoring" hexmask.long 0x0 0.--31. 1. "OPS,Number of floating point ops; FAdd/Fmul=1 MAD=2; max 32x2=64 per clock" repeat.end repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) rgroup.long ($2+0x4628)++0x3 line.long 0x0 "RGX_CR_USC_PWR_NUM_INTEGER_$1,Peformance counter associated with Power Monitoring" hexmask.long 0x0 0.--31. 1. "OPS,Number of integer ops; Add/Mul=1 MAD=2 max 16*2=32 per clock" repeat.end repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) rgroup.long ($2+0x4630)++0x3 line.long 0x0 "RGX_CR_USC_PWR_NUM_COALU_$1,Peformance counter associated with Power Monitoring" hexmask.long 0x0 0.--31. 1. "OPS,Number of COALU ops; max of 16 per clock" repeat.end repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) rgroup.long ($2+0x4638)++0x3 line.long 0x0 "RGX_CR_USC_PWR_NUM_$1,Peformance counter associated with Power Monitoring" hexmask.long 0x0 0.--31. 1. "PENALTY_CYCLES,Penalty cycles for read/read and write/write clashes. For each instruction this is max(a b c d)" repeat.end repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) rgroup.long ($2+0x4640)++0x3 line.long 0x0 "RGX_CR_USC_PWR_AV_NUM_INST_VALID_$1,Peformance counter associated with Power Monitoring" hexmask.long 0x0 0.--31. 1. "VERT,Average number of instances valid out of 16 for vertex tasks" repeat.end repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) rgroup.long ($2+0x4648)++0x3 line.long 0x0 "RGX_CR_USC_PWR_NUM_ON_EDGE_PIXL_$1,Peformance counter associated with Power Monitoring" hexmask.long 0x0 0.--31. 1. "WRITE,Number of on-edge pixel output register writes" repeat.end repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) rgroup.long ($2+0x4650)++0x3 line.long 0x0 "RGX_CR_USC_PWR_NUM_OFF_EDGE_PIXL_$1,Peformance counter associated with Power Monitoring" hexmask.long 0x0 0.--31. 1. "WRITE,Number of off-edge pixel output register writes" repeat.end repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) rgroup.long ($2+0x4658)++0x3 line.long 0x0 "RGX_CR_USC_PWR_NUM_F16_$1,Peformance counter associated with Power Monitoring" hexmask.long 0x0 0.--31. 1. "OPS,Number of F16 operations. Max of 16" repeat.end repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) rgroup.long ($2+0x4660)++0x3 line.long 0x0 "RGX_CR_USC_PWR_USCPD_INSTR_$1,Peformance counter associated with Power Monitoring" hexmask.long 0x0 0.--31. 1. "COUNT,Number of instructions executed by USCPD" repeat.end repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) rgroup.long ($2+0x4668)++0x3 line.long 0x0 "RGX_CR_USC_PWR_INT_REG_ACCESS_$1,Peformance counter associated with Power Monitoring" hexmask.long 0x0 0.--31. 1. "COUNT,Number of internal register accesses. Max 128 per clock = 8 registers * 16 instances" repeat.end repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) rgroup.long ($2+0x4670)++0x3 line.long 0x0 "RGX_CR_USC_PWR_US_STR_ACCESS_$1,Peformance counter associated with Power Monitoring" hexmask.long 0x0 0.--31. 1. "COUNT,Number of unified sotre US bank accesses. Max of 32 per clock = 8 banks * 4 pipes" repeat.end group.long 0x4678++0x7 line.long 0x0 "RGX_CR_USC_HQ_RESCH_0,Disable rescheduling of slots in USCPC HQ" hexmask.long 0x0 2.--31. 1. "Reserved_2,Reserved_2" newline bitfld.long 0x0 1. "DISABLE_FOR_BE,Disable rescheduling for BE instr in USCPC" "0,1" newline bitfld.long 0x0 0. "DISABLE,Disable rescheduling in USCPC" "0,1" line.long 0x4 "RGX_CR_USC_HQ_RESCH_1,Disable rescheduling of slots in USCPC HQ" hexmask.long 0x4 0.--31. 1. "Reserved_2,Reserved_2" repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) rgroup.long ($2+0x5000)++0x3 line.long 0x0 "RGX_CR_USC_UVS0_CHECKSUM_$1,RGX_CR_USC_UVS0_CHECKSUM_0" hexmask.long 0x0 0.--31. 1. "VALUE,Checksum of USC to UVS writes from USC0" repeat.end repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) rgroup.long ($2+0x5008)++0x3 line.long 0x0 "RGX_CR_USC_UVS1_CHECKSUM_$1,RGX_CR_USC_UVS1_CHECKSUM_0" hexmask.long 0x0 0.--31. 1. "VALUE,Checksum of USC to UVS writes from USC1" repeat.end repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) rgroup.long ($2+0x5010)++0x3 line.long 0x0 "RGX_CR_USC_UVS2_CHECKSUM_$1,RGX_CR_USC_UVS2_CHECKSUM_0" hexmask.long 0x0 0.--31. 1. "VALUE,Checksum of USC to UVS writes from USC2" repeat.end repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) rgroup.long ($2+0x5018)++0x3 line.long 0x0 "RGX_CR_USC_UVS3_CHECKSUM_$1,RGX_CR_USC_UVS3_CHECKSUM_0" hexmask.long 0x0 0.--31. 1. "VALUE,Checksum of USC to UVS writes from USC3" repeat.end repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) rgroup.long ($2+0x5020)++0x3 line.long 0x0 "RGX_CR_PPP_SIGNATURE_$1,RGX_CR_PPP_SIGNATURE_0" hexmask.long 0x0 0.--31. 1. "VALUE,Signature of PPP to Clipper Interface" repeat.end repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) rgroup.long ($2+0x5028)++0x3 line.long 0x0 "RGX_CR_TE_SIGNATURE_$1,RGX_CR_TE_SIGNATURE_0" hexmask.long 0x0 0.--31. 1. "VALUE,Signature of TE control stream writes" repeat.end repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) rgroup.long ($2+0x5030)++0x3 line.long 0x0 "RGX_CR_VCE_CHECKSUM_$1,RGX_CR_VCE_CHECKSUM_0" hexmask.long 0x0 0.--31. 1. "VALUE,Checksum of VCE memory writes" repeat.end repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) rgroup.long ($2+0x5038)++0x3 line.long 0x0 "RGX_CR_ISP_PDS_CHECKSUM_$1,RGX_CR_ISP_PDS_CHECKSUM_0" hexmask.long 0x0 0.--31. 1. "VALUE,Checksum of ISP PDS Span Output" repeat.end repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) rgroup.long ($2+0x5040)++0x3 line.long 0x0 "RGX_CR_ISP_TPF_CHECKSUM_$1,RGX_CR_ISP_TPF_CHECKSUM_0" hexmask.long 0x0 0.--31. 1. "VALUE,Checksum of ISP TPF Object Output" repeat.end repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) rgroup.long ($2+0x5048)++0x3 line.long 0x0 "RGX_CR_TFPU_PLANE0_CHECKSUM_$1,RGX_CR_TFPU_PLANE0_CHECKSUM_0" hexmask.long 0x0 0.--31. 1. "VALUE,Checksum of TFPU Plane0 Output" repeat.end repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) rgroup.long ($2+0x5050)++0x3 line.long 0x0 "RGX_CR_TFPU_PLANE1_CHECKSUM_$1,RGX_CR_TFPU_PLANE1_CHECKSUM_0" hexmask.long 0x0 0.--31. 1. "VALUE,Checksum of TFPU Plane1 Output" repeat.end repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) rgroup.long ($2+0x5058)++0x3 line.long 0x0 "RGX_CR_PBE_CHECKSUM_$1,RGX_CR_PBE_CHECKSUM_0" hexmask.long 0x0 0.--31. 1. "VALUE,Checksum of PBE memory writes" repeat.end repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) rgroup.long ($2+0x5060)++0x3 line.long 0x0 "RGX_CR_PDS_DOUTM_STM_SIGNATURE_$1,RGX_CR_PDS_DOUTM_STM_SIGNATURE_0" hexmask.long 0x0 0.--31. 1. "VALUE,Signature of PDS DOUTM Stream Out MCU writes" repeat.end repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) rgroup.long ($2+0x5068)++0x3 line.long 0x0 "RGX_CR_IFPU_ISP_CHECKSUM_$1,RGX_CR_IFPU_ISP_CHECKSUM_0" hexmask.long 0x0 0.--31. 1. "VALUE,Checksum of IFPU Output" repeat.end repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) rgroup.long ($2+0x5070)++0x3 line.long 0x0 "RGX_CR_MCU_L0_TA_CHECKSUM_$1,RGX_CR_MCU_L0_TA_CHECKSUM_0" hexmask.long 0x0 0.--31. 1. "VALUE,Checksum of the PDS->USC from MCU for TA data" repeat.end repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) rgroup.long ($2+0x5078)++0x3 line.long 0x0 "RGX_CR_MCU_L0_3D_CHECKSUM_$1,RGX_CR_MCU_L0_3D_CHECKSUM_0" hexmask.long 0x0 0.--31. 1. "VALUE,Checksum of the PDS->USC from MCU for 3D data" repeat.end repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) rgroup.long ($2+0x5080)++0x3 line.long 0x0 "RGX_CR_MCU_L0_WRAP_TA_CHECKSUM_$1,RGX_CR_MCU_L0_WRAP_TA_CHECKSUM_0" hexmask.long 0x0 0.--31. 1. "VALUE,Checksum of the PDS->USC from MCU for TA data" repeat.end repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) rgroup.long ($2+0x5088)++0x3 line.long 0x0 "RGX_CR_MCU_L0_WRAP_3D_CHECKSUM_$1,RGX_CR_MCU_L0_WRAP_3D_CHECKSUM_0" hexmask.long 0x0 0.--31. 1. "VALUE,Checksum of the PDS->USC from MCU for 3D data" repeat.end repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) rgroup.long ($2+0x5100)++0x3 line.long 0x0 "RGX_CR_USC_UVS4_CHECKSUM_$1,RGX_CR_USC_UVS4_CHECKSUM_0" hexmask.long 0x0 0.--31. 1. "VALUE,Checksum of USC to UVS writes from USC4" repeat.end repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) rgroup.long ($2+0x5108)++0x3 line.long 0x0 "RGX_CR_USC_UVS5_CHECKSUM_$1,RGX_CR_USC_UVS5_CHECKSUM_0" hexmask.long 0x0 0.--31. 1. "VALUE,Checksum of USC to UVS writes from USC5" repeat.end repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) rgroup.long ($2+0x5148)++0x3 line.long 0x0 "RGX_CR_TDM_PDS_CHECKSUM_$1,RGX_CR_TDM_PDS_CHECKSUM_0" hexmask.long 0x0 0.--31. 1. "VALUE,Checksum of all TDM to PDS tile emits." repeat.end repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) rgroup.long ($2+0x5160)++0x3 line.long 0x0 "RGX_CR_PBE_CHECKSUM_NO_ADDR_$1,RGX_CR_PBE_CHECKSUM_NO_ADDR_0" hexmask.long 0x0 0.--31. 1. "VALUE,No address checksum of PBE memory writes" repeat.end repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) rgroup.long ($2+0x5200)++0x3 line.long 0x0 "RGX_CR_PBE_CHECKSUM_TDM_$1,RGX_CR_PBE_CHECKSUM_TDM_0" hexmask.long 0x0 0.--31. 1. "VALUE,TDM checksum of PBE memory writes" repeat.end repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) rgroup.long ($2+0x5208)++0x3 line.long 0x0 "RGX_CR_PBE_CHECKSUM_TDM_NO_ADDR_$1,RGX_CR_PBE_CHECKSUM_TDM_NO_ADDR_0" hexmask.long 0x0 0.--31. 1. "VALUE,No address TDM checksum of PBE memory writes" repeat.end group.long 0x6000++0x7 line.long 0x0 "RGX_CR_PERF_COUNTER_0,RGX_CR_PERF_COUNTER_0" hexmask.long 0x0 1.--31. 1. "Reserved_1,Reserved_1" newline bitfld.long 0x0 0. "RESET,A write of 1 to this register resets the Cycle Counters and holds them in Reset. A write of 0 enables them for Counting" "0,1" line.long 0x4 "RGX_CR_PERF_COUNTER_1,RGX_CR_PERF_COUNTER_1" hexmask.long 0x4 0.--31. 1. "Reserved_1,Reserved_1" repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) rgroup.long ($2+0x6008)++0x3 line.long 0x0 "RGX_CR_PERF_TA_PHASE_$1,RGX_CR_PERF_TA_PHASE_0" hexmask.long 0x0 0.--31. 1. "COUNT,The number of TA phases completed" repeat.end repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) rgroup.long ($2+0x6010)++0x3 line.long 0x0 "RGX_CR_PERF_3D_PHASE_$1,RGX_CR_PERF_3D_PHASE_0" hexmask.long 0x0 0.--31. 1. "COUNT,The number of 3D phases completed" repeat.end repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) rgroup.long ($2+0x6018)++0x3 line.long 0x0 "RGX_CR_PERF_COMPUTE_PHASE_$1,RGX_CR_PERF_COMPUTE_PHASE_0" hexmask.long 0x0 0.--31. 1. "COUNT,The number of Compute phases completed" repeat.end repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) rgroup.long ($2+0x6020)++0x3 line.long 0x0 "RGX_CR_PERF_TA_CYCLE_$1,RGX_CR_PERF_TA_CYCLE_0" hexmask.long 0x0 0.--31. 1. "COUNT,The number of cycles spent in TA phases" repeat.end repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) rgroup.long ($2+0x6028)++0x3 line.long 0x0 "RGX_CR_PERF_3D_CYCLE_$1,RGX_CR_PERF_3D_CYCLE_0" hexmask.long 0x0 0.--31. 1. "COUNT,The number of cycles spent in 3D phases" repeat.end repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) rgroup.long ($2+0x6030)++0x3 line.long 0x0 "RGX_CR_PERF_COMPUTE_CYCLE_$1,RGX_CR_PERF_COMPUTE_CYCLE_0" hexmask.long 0x0 0.--31. 1. "COUNT,The number of cycles spent in Compute phases" repeat.end repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) rgroup.long ($2+0x6038)++0x3 line.long 0x0 "RGX_CR_PERF_TA_OR_3D_CYCLE_$1,RGX_CR_PERF_TA_OR_3D_CYCLE_0" hexmask.long 0x0 0.--31. 1. "COUNT,The number of cycles spent in TA phases or 3D phases" repeat.end repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) rgroup.long ($2+0x6040)++0x3 line.long 0x0 "RGX_CR_PERF_INITIAL_TA_CYCLE_$1,RGX_CR_PERF_INITIAL_TA_CYCLE_0" hexmask.long 0x0 0.--31. 1. "COUNT,The number of cycles spent in TA phases before the first 3D phase" repeat.end repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) rgroup.long ($2+0x6048)++0x3 line.long 0x0 "RGX_CR_PERF_FINAL_3D_CYCLE_$1,RGX_CR_PERF_FINAL_3D_CYCLE_0" hexmask.long 0x0 0.--31. 1. "COUNT,The number of cycles spent in the last 3D phase" repeat.end repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) rgroup.long ($2+0x6050)++0x3 line.long 0x0 "RGX_CR_PERF_BIF0_READ_$1,RGX_CR_PERF_BIF0_READ_0" hexmask.long 0x0 0.--31. 1. "COUNT,The number of BIF0-to-SLC reads" repeat.end repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) rgroup.long ($2+0x6058)++0x3 line.long 0x0 "RGX_CR_PERF_BIF0_WRITE_$1,RGX_CR_PERF_BIF0_WRITE_0" hexmask.long 0x0 0.--31. 1. "COUNT,The number of BIF0-to-SLC writes" repeat.end repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) rgroup.long ($2+0x6060)++0x3 line.long 0x0 "RGX_CR_PERF_BIF0_BYTE_WRITE_$1,RGX_CR_PERF_BIF0_BYTE_WRITE_0" hexmask.long 0x0 0.--31. 1. "COUNT,The number of BIF0-to-SLC bytes written" repeat.end repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) rgroup.long ($2+0x6068)++0x3 line.long 0x0 "RGX_CR_PERF_BIF0_READ_STALL_$1,RGX_CR_PERF_BIF0_READ_STALL_0" hexmask.long 0x0 0.--31. 1. "COUNT,The number of BIF0-to-SLC read stalls" repeat.end repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) rgroup.long ($2+0x6070)++0x3 line.long 0x0 "RGX_CR_PERF_BIF0_WRITE_STALL_$1,RGX_CR_PERF_BIF0_WRITE_STALL_0" hexmask.long 0x0 0.--31. 1. "COUNT,The number of BIF0-to-SLC write stalls" repeat.end repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) rgroup.long ($2+0x60A0)++0x3 line.long 0x0 "RGX_CR_PERF_SLC0_READ_$1,RGX_CR_PERF_SLC0_READ_0" hexmask.long 0x0 0.--31. 1. "COUNT,The number of SLC-to-MEM interface 0 reads" repeat.end repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) rgroup.long ($2+0x60A8)++0x3 line.long 0x0 "RGX_CR_PERF_SLC0_WRITE_$1,RGX_CR_PERF_SLC0_WRITE_0" hexmask.long 0x0 0.--31. 1. "COUNT,The number of SLC-to-MEM interface 0 writes" repeat.end repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) rgroup.long ($2+0x60B0)++0x3 line.long 0x0 "RGX_CR_PERF_SLC0_BYTE_WRITE_$1,RGX_CR_PERF_SLC0_BYTE_WRITE_0" hexmask.long 0x0 0.--31. 1. "COUNT,The number of SLC-to-MEM interface 0 bytes written" repeat.end repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) rgroup.long ($2+0x60B8)++0x3 line.long 0x0 "RGX_CR_PERF_SLC0_READ_STALL_$1,RGX_CR_PERF_SLC0_READ_STALL_0" hexmask.long 0x0 0.--31. 1. "COUNT,The number of SLC-to-MEM interface 0 command stalls" repeat.end repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) rgroup.long ($2+0x60C0)++0x3 line.long 0x0 "RGX_CR_PERF_SLC0_WRITE_STALL_$1,RGX_CR_PERF_SLC0_WRITE_STALL_0" hexmask.long 0x0 0.--31. 1. "COUNT,The number of SLC-to-MEM insterface 0 write channel stalls" repeat.end repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) rgroup.long ($2+0x60C8)++0x3 line.long 0x0 "RGX_CR_PERF_SLC1_READ_$1,RGX_CR_PERF_SLC1_READ_0" hexmask.long 0x0 0.--31. 1. "COUNT,The number of SLC-to-MEM interface 1 reads" repeat.end repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) rgroup.long ($2+0x60D0)++0x3 line.long 0x0 "RGX_CR_PERF_SLC1_WRITE_$1,RGX_CR_PERF_SLC1_WRITE_0" hexmask.long 0x0 0.--31. 1. "COUNT,The number of SLC-to-MEM interface 1 writes" repeat.end repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) rgroup.long ($2+0x60D8)++0x3 line.long 0x0 "RGX_CR_PERF_SLC1_BYTE_WRITE_$1,RGX_CR_PERF_SLC1_BYTE_WRITE_0" hexmask.long 0x0 0.--31. 1. "COUNT,The number of SLC-to-MEM interface 1 bytes written" repeat.end repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) rgroup.long ($2+0x60E0)++0x3 line.long 0x0 "RGX_CR_PERF_SLC1_READ_STALL_$1,RGX_CR_PERF_SLC1_READ_STALL_0" hexmask.long 0x0 0.--31. 1. "COUNT,The number of SLC-to-MEM interface 1 command stalls" repeat.end repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) rgroup.long ($2+0x60E8)++0x3 line.long 0x0 "RGX_CR_PERF_SLC1_WRITE_STALL_$1,RGX_CR_PERF_SLC1_WRITE_STALL_0" hexmask.long 0x0 0.--31. 1. "COUNT,The number of SLC-to-MEM interface 1 write channel stalls" repeat.end repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) rgroup.long ($2+0x60F0)++0x3 line.long 0x0 "RGX_CR_PERF_SLC_BURST_SIZE0_IN_$1,RGX_CR_PERF_SLC_BURST_SIZE0_IN_0" hexmask.long 0x0 0.--31. 1. "VALUE,The number of burstlength 0 accesses into the Burst Combiner" repeat.end repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) rgroup.long ($2+0x60F8)++0x3 line.long 0x0 "RGX_CR_PERF_SLC_BURST_SIZE1_IN_$1,RGX_CR_PERF_SLC_BURST_SIZE1_IN_0" hexmask.long 0x0 0.--31. 1. "VALUE,The number of burstlength 1 accesses into the Burst Combiner" repeat.end repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) rgroup.long ($2+0x6100)++0x3 line.long 0x0 "RGX_CR_PERF_SLC_BURST_SIZE0_OUT_$1,RGX_CR_PERF_SLC_BURST_SIZE0_OUT_0" hexmask.long 0x0 0.--31. 1. "VALUE,The number of burstlength 0 accesses out of the Burst Combiner" repeat.end repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) rgroup.long ($2+0x6108)++0x3 line.long 0x0 "RGX_CR_PERF_SLC_BURST_SIZE1_OUT_$1,RGX_CR_PERF_SLC_BURST_SIZE1_OUT_0" hexmask.long 0x0 0.--31. 1. "VALUE,The number of burstlength 1 accesses out of the Burst Combiner" repeat.end repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) rgroup.long ($2+0x6110)++0x3 line.long 0x0 "RGX_CR_PERF_SLC_BURST_SIZE2_OUT_$1,RGX_CR_PERF_SLC_BURST_SIZE2_OUT_0" hexmask.long 0x0 0.--31. 1. "VALUE,The number of burstlength 2 accesses out of the Burst Combiner" repeat.end repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) rgroup.long ($2+0x6118)++0x3 line.long 0x0 "RGX_CR_PERF_SLC0_READ_ID_STALL_$1,RGX_CR_PERF_SLC0_READ_ID_STALL_0" hexmask.long 0x0 0.--31. 1. "COUNT,The number of cycles the SLC spends stalled because all Read IDs on memory interface 0 are currently in use" repeat.end repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) rgroup.long ($2+0x6120)++0x3 line.long 0x0 "RGX_CR_PERF_SLC0_WRITE_ID_STALL_$1,RGX_CR_PERF_SLC0_WRITE_ID_STALL_0" hexmask.long 0x0 0.--31. 1. "COUNT,The number of cycles the SLC spends stalled because all Write IDs on memory interface 0 are currently in use" repeat.end repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) rgroup.long ($2+0x6128)++0x3 line.long 0x0 "RGX_CR_PERF_SLC1_READ_ID_STALL_$1,RGX_CR_PERF_SLC1_READ_ID_STALL_0" hexmask.long 0x0 0.--31. 1. "COUNT,The number of cycles the SLC spends stalled because all Read IDs on memory interface 1 are currently in use" repeat.end repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) rgroup.long ($2+0x6130)++0x3 line.long 0x0 "RGX_CR_PERF_SLC1_WRITE_ID_STALL_$1,RGX_CR_PERF_SLC1_WRITE_ID_STALL_0" hexmask.long 0x0 0.--31. 1. "COUNT,The number of cycles the SLC spends stalled because all Write IDs on memory interface 1 are currently in use" repeat.end repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) rgroup.long ($2+0x6138)++0x3 line.long 0x0 "RGX_CR_PERF_SLC_BURST_SIZE3_OUT_$1,RGX_CR_PERF_SLC_BURST_SIZE3_OUT_0" hexmask.long 0x0 0.--31. 1. "VALUE,The number of burstlength 3 accesses out of the Burst Combiner" repeat.end repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) rgroup.long ($2+0x6140)++0x3 line.long 0x0 "RGX_CR_PERF_SLC2_READ_$1,RGX_CR_PERF_SLC2_READ_0" hexmask.long 0x0 0.--31. 1. "COUNT,The number of SLC-to-MEM interface 2 reads" repeat.end repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) rgroup.long ($2+0x6148)++0x3 line.long 0x0 "RGX_CR_PERF_SLC2_WRITE_$1,RGX_CR_PERF_SLC2_WRITE_0" hexmask.long 0x0 0.--31. 1. "COUNT,The number of SLC-to-MEM interface 2 writes" repeat.end repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) rgroup.long ($2+0x6150)++0x3 line.long 0x0 "RGX_CR_PERF_SLC2_BYTE_WRITE_$1,RGX_CR_PERF_SLC2_BYTE_WRITE_0" hexmask.long 0x0 0.--31. 1. "COUNT,The number of SLC-to-MEM interface 2 bytes written" repeat.end repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) rgroup.long ($2+0x6158)++0x3 line.long 0x0 "RGX_CR_PERF_SLC2_READ_STALL_$1,RGX_CR_PERF_SLC2_READ_STALL_0" hexmask.long 0x0 0.--31. 1. "COUNT,The number of SLC-to-MEM interface 2 command stalls" repeat.end repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) rgroup.long ($2+0x6160)++0x3 line.long 0x0 "RGX_CR_PERF_SLC2_WRITE_STALL_$1,RGX_CR_PERF_SLC2_WRITE_STALL_0" hexmask.long 0x0 0.--31. 1. "COUNT,The number of SLC-to-MEM interface 2 write channel stalls" repeat.end repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) rgroup.long ($2+0x6168)++0x3 line.long 0x0 "RGX_CR_PERF_SLC3_READ_$1,RGX_CR_PERF_SLC3_READ_0" hexmask.long 0x0 0.--31. 1. "COUNT,The number of SLC-to-MEM interface 3 reads" repeat.end repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) rgroup.long ($2+0x6170)++0x3 line.long 0x0 "RGX_CR_PERF_SLC3_WRITE_$1,RGX_CR_PERF_SLC3_WRITE_0" hexmask.long 0x0 0.--31. 1. "COUNT,The number of SLC-to-MEM interface 3 writes" repeat.end repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) rgroup.long ($2+0x6178)++0x3 line.long 0x0 "RGX_CR_PERF_SLC3_BYTE_WRITE_$1,RGX_CR_PERF_SLC3_BYTE_WRITE_0" hexmask.long 0x0 0.--31. 1. "COUNT,The number of SLC-to-MEM interface 3 bytes written" repeat.end repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) rgroup.long ($2+0x6180)++0x3 line.long 0x0 "RGX_CR_PERF_SLC3_READ_STALL_$1,RGX_CR_PERF_SLC3_READ_STALL_0" hexmask.long 0x0 0.--31. 1. "COUNT,The number of SLC-to-MEM interface 3 command stalls" repeat.end repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) rgroup.long ($2+0x6188)++0x3 line.long 0x0 "RGX_CR_PERF_SLC3_WRITE_STALL_$1,RGX_CR_PERF_SLC3_WRITE_STALL_0" hexmask.long 0x0 0.--31. 1. "COUNT,The number of SLC-to-MEM interface 3 write channel stalls" repeat.end repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) rgroup.long ($2+0x6190)++0x3 line.long 0x0 "RGX_CR_PERF_SLC_BURST_SIZE2_IN_$1,RGX_CR_PERF_SLC_BURST_SIZE2_IN_0" hexmask.long 0x0 0.--31. 1. "VALUE,The number of burstlength 2 accesses into the Burst Combiner" repeat.end repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) rgroup.long ($2+0x6198)++0x3 line.long 0x0 "RGX_CR_PERF_SLC_BURST_SIZE3_IN_$1,RGX_CR_PERF_SLC_BURST_SIZE3_IN_0" hexmask.long 0x0 0.--31. 1. "VALUE,The number of burstlength 3 accesses into the Burst Combiner" repeat.end repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) rgroup.long ($2+0x6220)++0x3 line.long 0x0 "RGX_CR_PERF_3D_SPINUP_$1,RGX_CR_PERF_3D_SPINUP_0" hexmask.long 0x0 0.--31. 1. "CYCLES,The number of cycles it takes the 3D pipeline to spin-up" repeat.end group.long 0x6300++0x7 line.long 0x0 "RGX_CR_POWER_ESTIMATE_REQ_RST_0,Power estimate Request/Reset - The generation of the power estimate will be initiated upon a write to the power managment register. This will be driven down to the relevant blocks to reset the counters and also to start.." hexmask.long 0x0 1.--31. 1. "Reserved_1,Reserved_1" newline bitfld.long 0x0 0. "VALUE,VALUE" "0,1" line.long 0x4 "RGX_CR_POWER_ESTIMATE_REQ_RST_1,Power estimate Request/Reset - The generation of the power estimate will be initiated upon a write to the power managment register. This will be driven down to the relevant blocks to reset the counters and also to start.." hexmask.long 0x4 0.--31. 1. "Reserved_1,Reserved_1" repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) group.long ($2+0x6310)++0x3 line.long 0x0 "RGX_CR_POWER_ESTIMATE_SAMPLE_COUNT_$1,Power Estimate Sample Count - This defines the number of cycles over which power monitoring will occur. When the POWER_ESTIMIATE_REQ_RST is written to POWER_ESTIMATE_SAMPLE_COUNT will begin to count down from its.." hexmask.long 0x0 0.--31. 1. "VALUE,VALUE" repeat.end rgroup.long 0x6318++0x7 line.long 0x0 "RGX_CR_POWER_ESTIMATE_READY_0,Power estimate Ready - A system event (portmap signal and maskable interrupt) is output when the power estimate has been completed and the power monitor register is updated. Logic or firmware or both will manage the SOC.." hexmask.long.word 0x0 17.--31. 1. "Reserved_17,Reserved_17" newline bitfld.long 0x0 16. "FB_CDC,FB_CDC" "0,1" newline bitfld.long 0x0 15. "Reserved_15,Reserved_15" "0,1" newline bitfld.long 0x0 14. "SLC,SLC" "0,1" newline bitfld.long 0x0 13. "TILING,TILING" "0,1" newline bitfld.long 0x0 12. "JONES,JONES" "0,1" newline bitfld.long 0x0 10.--11. "Reserved_10,Reserved_10" "0,1,2,3" newline bitfld.long 0x0 9. "TA,TA" "0,1" newline bitfld.long 0x0 8. "RASTERISATION,RASTERISATION" "0,1" newline bitfld.long 0x0 7. "HUB,HUB" "0,1" newline bitfld.long 0x0 6. "BIFPMCACHE,BIFPMCACHE" "0,1" newline bitfld.long 0x0 5. "Reserved_5,Reserved_5" "0,1" newline bitfld.long 0x0 4. "TPU_MCU,TPU_MCU" "0,1" newline bitfld.long 0x0 1.--3. "Reserved_1,Reserved_1" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 0. "USC,USC" "0,1" line.long 0x4 "RGX_CR_POWER_ESTIMATE_READY_1,Power estimate Ready - A system event (portmap signal and maskable interrupt) is output when the power estimate has been completed and the power monitor register is updated. Logic or firmware or both will manage the SOC.." hexmask.long 0x4 0.--31. 1. "Reserved_17,Reserved_17" repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) group.long ($2+0x6320)++0x3 line.long 0x0 "RGX_CR_POWER_ESTIMATE_GAIN_COEFF_$1,Final Gain coefficient to apply to summation of all power monitoring quotients" hexmask.long 0x0 0.--31. 1. "VALUE,VALUE" repeat.end repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) group.long ($2+0x6328)++0x3 line.long 0x0 "RGX_CR_POWER_ESTIMATE_RESULT_$1,Power Estimate Result. This represents the estimation of the total system power usage." hexmask.long 0x0 0.--31. 1. "VALUE,VALUE" repeat.end group.long 0x6330++0x7 line.long 0x0 "RGX_CR_PERF_COUNT_MODE_ONLY_0,This register bit set means we need to do only perf-counter gathering and nothing to do with pwr-perf related counting" hexmask.long 0x0 1.--31. 1. "Reserved_1,Reserved_1" newline bitfld.long 0x0 0. "VALUE,VALUE" "0,1" line.long 0x4 "RGX_CR_PERF_COUNT_MODE_ONLY_1,This register bit set means we need to do only perf-counter gathering and nothing to do with pwr-perf related counting" hexmask.long 0x4 0.--31. 1. "Reserved_1,Reserved_1" rgroup.long 0x6500++0x2F line.long 0x0 "RGX_CR_AVG_NON_CRITICAL_MEM0_LATENCY_0,RGX_CR_AVG_NON_CRITICAL_MEM0_LATENCY_0" hexmask.long.tbyte 0x0 12.--31. 1. "Reserved_12,Reserved_12" newline hexmask.long.word 0x0 0.--11. 1. "COUNT,The average number of read latency cycles incur at external memory for non critical tag" line.long 0x4 "RGX_CR_AVG_NON_CRITICAL_MEM0_LATENCY_1,RGX_CR_AVG_NON_CRITICAL_MEM0_LATENCY_1" hexmask.long 0x4 0.--31. 1. "Reserved_12,Reserved_12" line.long 0x8 "RGX_CR_MIN_NON_CRITICAL_MEM0_LATENCY_0,RGX_CR_MIN_NON_CRITICAL_MEM0_LATENCY_0" hexmask.long.tbyte 0x8 12.--31. 1. "Reserved_12,Reserved_12" newline hexmask.long.word 0x8 0.--11. 1. "COUNT,The min number of read latency cycles incur at external memory for non critical tag" line.long 0xC "RGX_CR_MIN_NON_CRITICAL_MEM0_LATENCY_1,RGX_CR_MIN_NON_CRITICAL_MEM0_LATENCY_1" hexmask.long 0xC 0.--31. 1. "Reserved_12,Reserved_12" line.long 0x10 "RGX_CR_MAX_NON_CRITICAL_MEM0_LATENCY_0,RGX_CR_MAX_NON_CRITICAL_MEM0_LATENCY_0" hexmask.long.tbyte 0x10 12.--31. 1. "Reserved_12,Reserved_12" newline hexmask.long.word 0x10 0.--11. 1. "COUNT,The max number of read latency cycles incur at external memory for non critical tag" line.long 0x14 "RGX_CR_MAX_NON_CRITICAL_MEM0_LATENCY_1,RGX_CR_MAX_NON_CRITICAL_MEM0_LATENCY_1" hexmask.long 0x14 0.--31. 1. "Reserved_12,Reserved_12" line.long 0x18 "RGX_CR_AVG_CRITICAL_MEM0_LATENCY_0,RGX_CR_AVG_CRITICAL_MEM0_LATENCY_0" hexmask.long.tbyte 0x18 12.--31. 1. "Reserved_12,Reserved_12" newline hexmask.long.word 0x18 0.--11. 1. "COUNT,The average number of read latency cycles incur at external memory for critical tag" line.long 0x1C "RGX_CR_AVG_CRITICAL_MEM0_LATENCY_1,RGX_CR_AVG_CRITICAL_MEM0_LATENCY_1" hexmask.long 0x1C 0.--31. 1. "Reserved_12,Reserved_12" line.long 0x20 "RGX_CR_MIN_CRITICAL_MEM0_LATENCY_0,RGX_CR_MIN_CRITICAL_MEM0_LATENCY_0" hexmask.long.tbyte 0x20 12.--31. 1. "Reserved_12,Reserved_12" newline hexmask.long.word 0x20 0.--11. 1. "COUNT,The min number of read latency cycles incur at external memory for critical tag" line.long 0x24 "RGX_CR_MIN_CRITICAL_MEM0_LATENCY_1,RGX_CR_MIN_CRITICAL_MEM0_LATENCY_1" hexmask.long 0x24 0.--31. 1. "Reserved_12,Reserved_12" line.long 0x28 "RGX_CR_MAX_CRITICAL_MEM0_LATENCY_0,RGX_CR_MAX_CRITICAL_MEM0_LATENCY_0" hexmask.long.tbyte 0x28 12.--31. 1. "Reserved_12,Reserved_12" newline hexmask.long.word 0x28 0.--11. 1. "COUNT,The max number of read latency cycles incur at external memory for critical tag" line.long 0x2C "RGX_CR_MAX_CRITICAL_MEM0_LATENCY_1,RGX_CR_MAX_CRITICAL_MEM0_LATENCY_1" hexmask.long 0x2C 0.--31. 1. "Reserved_12,Reserved_12" group.long 0x6530++0x7 line.long 0x0 "RGX_CR_USER_DEFINED_MEM0_MH_TAG_0,Writing '1' followed by mh_tag value at the lsb end of this register starts the user defined mh_tag value for latency calculation. Default value is zero where this feature is turned off. Bit [6] - Enable bit to turn on.." hexmask.long 0x0 7.--31. 1. "Reserved_7,Reserved_7" newline hexmask.long.byte 0x0 0.--6. 1. "VALUE,VALUE" line.long 0x4 "RGX_CR_USER_DEFINED_MEM0_MH_TAG_1,Writing '1' followed by mh_tag value at the lsb end of this register starts the user defined mh_tag value for latency calculation. Default value is zero where this feature is turned off. Bit [6] - Enable bit to turn on.." hexmask.long 0x4 0.--31. 1. "Reserved_7,Reserved_7" rgroup.long 0x6538++0x57 line.long 0x0 "RGX_CR_AVG_USER_MH_TAG_MEM0_LATENCY_0,RGX_CR_AVG_USER_MH_TAG_MEM0_LATENCY_0" hexmask.long.tbyte 0x0 12.--31. 1. "Reserved_12,Reserved_12" newline hexmask.long.word 0x0 0.--11. 1. "COUNT,The average number of read latency cycles incur at external memory for user_defined tag" line.long 0x4 "RGX_CR_AVG_USER_MH_TAG_MEM0_LATENCY_1,RGX_CR_AVG_USER_MH_TAG_MEM0_LATENCY_1" hexmask.long 0x4 0.--31. 1. "Reserved_12,Reserved_12" line.long 0x8 "RGX_CR_MIN_USER_MH_TAG_MEM0_LATENCY_0,RGX_CR_MIN_USER_MH_TAG_MEM0_LATENCY_0" hexmask.long.tbyte 0x8 12.--31. 1. "Reserved_12,Reserved_12" newline hexmask.long.word 0x8 0.--11. 1. "COUNT,The min number of read latency cycles incur at external memory for user defined tag" line.long 0xC "RGX_CR_MIN_USER_MH_TAG_MEM0_LATENCY_1,RGX_CR_MIN_USER_MH_TAG_MEM0_LATENCY_1" hexmask.long 0xC 0.--31. 1. "Reserved_12,Reserved_12" line.long 0x10 "RGX_CR_MAX_USER_MH_TAG_MEM0_LATENCY_0,RGX_CR_MAX_USER_MH_TAG_MEM0_LATENCY_0" hexmask.long.tbyte 0x10 12.--31. 1. "Reserved_12,Reserved_12" newline hexmask.long.word 0x10 0.--11. 1. "COUNT,The max number of read latency cycles incur at external memory for user defined tag" line.long 0x14 "RGX_CR_MAX_USER_MH_TAG_MEM0_LATENCY_1,RGX_CR_MAX_USER_MH_TAG_MEM0_LATENCY_1" hexmask.long 0x14 0.--31. 1. "Reserved_12,Reserved_12" line.long 0x18 "RGX_CR_MIN_NON_CRITICAL_MEM0_LATENCY_MH_TAG_0,RGX_CR_MIN_NON_CRITICAL_MEM0_LATENCY_MH_TAG_0" hexmask.long 0x18 6.--31. 1. "Reserved_6,Reserved_6" newline hexmask.long.byte 0x18 0.--5. 1. "VALUE,The mh_tag value of min read latency cycles for non critical tag" line.long 0x1C "RGX_CR_MIN_NON_CRITICAL_MEM0_LATENCY_MH_TAG_1,RGX_CR_MIN_NON_CRITICAL_MEM0_LATENCY_MH_TAG_1" hexmask.long 0x1C 0.--31. 1. "Reserved_6,Reserved_6" line.long 0x20 "RGX_CR_MAX_NON_CRITICAL_MEM0_LATENCY_MH_TAG_0,RGX_CR_MAX_NON_CRITICAL_MEM0_LATENCY_MH_TAG_0" hexmask.long 0x20 6.--31. 1. "Reserved_6,Reserved_6" newline hexmask.long.byte 0x20 0.--5. 1. "VALUE,The mh_tag value of max read latency cycles for non critical tag" line.long 0x24 "RGX_CR_MAX_NON_CRITICAL_MEM0_LATENCY_MH_TAG_1,RGX_CR_MAX_NON_CRITICAL_MEM0_LATENCY_MH_TAG_1" hexmask.long 0x24 0.--31. 1. "Reserved_6,Reserved_6" line.long 0x28 "RGX_CR_AVG_NON_CRITICAL_MEM1_LATENCY_0,RGX_CR_AVG_NON_CRITICAL_MEM1_LATENCY_0" hexmask.long.tbyte 0x28 12.--31. 1. "Reserved_12,Reserved_12" newline hexmask.long.word 0x28 0.--11. 1. "COUNT,The average number of read latency cycles incur at external memory for non critical tag" line.long 0x2C "RGX_CR_AVG_NON_CRITICAL_MEM1_LATENCY_1,RGX_CR_AVG_NON_CRITICAL_MEM1_LATENCY_1" hexmask.long 0x2C 0.--31. 1. "Reserved_12,Reserved_12" line.long 0x30 "RGX_CR_MIN_NON_CRITICAL_MEM1_LATENCY_0,RGX_CR_MIN_NON_CRITICAL_MEM1_LATENCY_0" hexmask.long.tbyte 0x30 12.--31. 1. "Reserved_12,Reserved_12" newline hexmask.long.word 0x30 0.--11. 1. "COUNT,The min number of read latency cycles incur at external memory for non critical tag" line.long 0x34 "RGX_CR_MIN_NON_CRITICAL_MEM1_LATENCY_1,RGX_CR_MIN_NON_CRITICAL_MEM1_LATENCY_1" hexmask.long 0x34 0.--31. 1. "Reserved_12,Reserved_12" line.long 0x38 "RGX_CR_MAX_NON_CRITICAL_MEM1_LATENCY_0,RGX_CR_MAX_NON_CRITICAL_MEM1_LATENCY_0" hexmask.long.tbyte 0x38 12.--31. 1. "Reserved_12,Reserved_12" newline hexmask.long.word 0x38 0.--11. 1. "COUNT,The max number of read latency cycles incur at external memory for non critical tag" line.long 0x3C "RGX_CR_MAX_NON_CRITICAL_MEM1_LATENCY_1,RGX_CR_MAX_NON_CRITICAL_MEM1_LATENCY_1" hexmask.long 0x3C 0.--31. 1. "Reserved_12,Reserved_12" line.long 0x40 "RGX_CR_AVG_CRITICAL_MEM1_LATENCY_0,RGX_CR_AVG_CRITICAL_MEM1_LATENCY_0" hexmask.long.tbyte 0x40 12.--31. 1. "Reserved_12,Reserved_12" newline hexmask.long.word 0x40 0.--11. 1. "COUNT,The average number of read latency cycles incur at external memory for critical tag" line.long 0x44 "RGX_CR_AVG_CRITICAL_MEM1_LATENCY_1,RGX_CR_AVG_CRITICAL_MEM1_LATENCY_1" hexmask.long 0x44 0.--31. 1. "Reserved_12,Reserved_12" line.long 0x48 "RGX_CR_MIN_CRITICAL_MEM1_LATENCY_0,RGX_CR_MIN_CRITICAL_MEM1_LATENCY_0" hexmask.long.tbyte 0x48 12.--31. 1. "Reserved_12,Reserved_12" newline hexmask.long.word 0x48 0.--11. 1. "COUNT,The min number of read latency cycles incur at external memory for critical tag" line.long 0x4C "RGX_CR_MIN_CRITICAL_MEM1_LATENCY_1,RGX_CR_MIN_CRITICAL_MEM1_LATENCY_1" hexmask.long 0x4C 0.--31. 1. "Reserved_12,Reserved_12" line.long 0x50 "RGX_CR_MAX_CRITICAL_MEM1_LATENCY_0,RGX_CR_MAX_CRITICAL_MEM1_LATENCY_0" hexmask.long.tbyte 0x50 12.--31. 1. "Reserved_12,Reserved_12" newline hexmask.long.word 0x50 0.--11. 1. "COUNT,The max number of read latency cycles incur at external memory for critical tag" line.long 0x54 "RGX_CR_MAX_CRITICAL_MEM1_LATENCY_1,RGX_CR_MAX_CRITICAL_MEM1_LATENCY_1" hexmask.long 0x54 0.--31. 1. "Reserved_12,Reserved_12" group.long 0x6590++0x7 line.long 0x0 "RGX_CR_USER_DEFINED_MEM1_MH_TAG_0,Writing '1' followed by mh_tag value at the lsb end of this register starts the user defined mh_tag value for latency calculation. Default value is zero where this feature is turned off. Bit [6] - Enable bit to turn on.." hexmask.long 0x0 7.--31. 1. "Reserved_7,Reserved_7" newline hexmask.long.byte 0x0 0.--6. 1. "VALUE,VALUE" line.long 0x4 "RGX_CR_USER_DEFINED_MEM1_MH_TAG_1,Writing '1' followed by mh_tag value at the lsb end of this register starts the user defined mh_tag value for latency calculation. Default value is zero where this feature is turned off. Bit [6] - Enable bit to turn on.." hexmask.long 0x4 0.--31. 1. "Reserved_7,Reserved_7" rgroup.long 0x6598++0x27 line.long 0x0 "RGX_CR_AVG_USER_MH_TAG_MEM1_LATENCY_0,RGX_CR_AVG_USER_MH_TAG_MEM1_LATENCY_0" hexmask.long.tbyte 0x0 12.--31. 1. "Reserved_12,Reserved_12" newline hexmask.long.word 0x0 0.--11. 1. "COUNT,The average number of read latency cycles incur at external memory for user_defined tag" line.long 0x4 "RGX_CR_AVG_USER_MH_TAG_MEM1_LATENCY_1,RGX_CR_AVG_USER_MH_TAG_MEM1_LATENCY_1" hexmask.long 0x4 0.--31. 1. "Reserved_12,Reserved_12" line.long 0x8 "RGX_CR_MIN_USER_MH_TAG_MEM1_LATENCY_0,RGX_CR_MIN_USER_MH_TAG_MEM1_LATENCY_0" hexmask.long.tbyte 0x8 12.--31. 1. "Reserved_12,Reserved_12" newline hexmask.long.word 0x8 0.--11. 1. "COUNT,The min number of read latency cycles incur at external memory for user defined tag" line.long 0xC "RGX_CR_MIN_USER_MH_TAG_MEM1_LATENCY_1,RGX_CR_MIN_USER_MH_TAG_MEM1_LATENCY_1" hexmask.long 0xC 0.--31. 1. "Reserved_12,Reserved_12" line.long 0x10 "RGX_CR_MAX_USER_MH_TAG_MEM1_LATENCY_0,RGX_CR_MAX_USER_MH_TAG_MEM1_LATENCY_0" hexmask.long.tbyte 0x10 12.--31. 1. "Reserved_12,Reserved_12" newline hexmask.long.word 0x10 0.--11. 1. "COUNT,The max number of read latency cycles incur at external memory for user defined tag" line.long 0x14 "RGX_CR_MAX_USER_MH_TAG_MEM1_LATENCY_1,RGX_CR_MAX_USER_MH_TAG_MEM1_LATENCY_1" hexmask.long 0x14 0.--31. 1. "Reserved_12,Reserved_12" line.long 0x18 "RGX_CR_MIN_NON_CRITICAL_MEM1_LATENCY_MH_TAG_0,RGX_CR_MIN_NON_CRITICAL_MEM1_LATENCY_MH_TAG_0" hexmask.long 0x18 6.--31. 1. "Reserved_6,Reserved_6" newline hexmask.long.byte 0x18 0.--5. 1. "VALUE,The mh_tag value of min read latency cycles for non critical tag" line.long 0x1C "RGX_CR_MIN_NON_CRITICAL_MEM1_LATENCY_MH_TAG_1,RGX_CR_MIN_NON_CRITICAL_MEM1_LATENCY_MH_TAG_1" hexmask.long 0x1C 0.--31. 1. "Reserved_6,Reserved_6" line.long 0x20 "RGX_CR_MAX_NON_CRITICAL_MEM1_LATENCY_MH_TAG_0,RGX_CR_MAX_NON_CRITICAL_MEM1_LATENCY_MH_TAG_0" hexmask.long 0x20 6.--31. 1. "Reserved_6,Reserved_6" newline hexmask.long.byte 0x20 0.--5. 1. "VALUE,The mh_tag value of max read latency cycles for non critical tag" line.long 0x24 "RGX_CR_MAX_NON_CRITICAL_MEM1_LATENCY_MH_TAG_1,RGX_CR_MAX_NON_CRITICAL_MEM1_LATENCY_MH_TAG_1" hexmask.long 0x24 0.--31. 1. "Reserved_6,Reserved_6" group.long 0x7600++0x27 line.long 0x0 "RGX_CR_TA_PERF_0,RGX_CR_TA_PERF_0" hexmask.long 0x0 5.--31. 1. "Reserved_5,Reserved_5" newline bitfld.long 0x0 4. "CLR_3,clear counter 3" "0,1" newline bitfld.long 0x0 3. "CLR_2,clear counter 2" "0,1" newline bitfld.long 0x0 2. "CLR_1,clear counter 1" "0,1" newline bitfld.long 0x0 1. "CLR_0,clear counter 0" "0,1" newline bitfld.long 0x0 0. "CTRL_ENABLE,enables the perf bus counters" "0,1" line.long 0x4 "RGX_CR_TA_PERF_1,RGX_CR_TA_PERF_1" hexmask.long 0x4 0.--31. 1. "Reserved_5,Reserved_5" line.long 0x8 "RGX_CR_TA_PERF_SELECT0_0,RGX_CR_TA_PERF_SELECT0_0" hexmask.long.word 0x8 22.--31. 1. "Reserved_22,Reserved_22" newline bitfld.long 0x8 21. "MODE,reduction mode 0: bitwise increments 1: unsigned count increment" "bitwise increments,unsigned count increment" newline hexmask.long.byte 0x8 16.--20. 1. "GROUP_SELECT,group select see full PERF documentation for signals in each group" newline hexmask.long.word 0x8 0.--15. 1. "BIT_SELECT,bit mask for enabled signals in group" line.long 0xC "RGX_CR_TA_PERF_SELECT0_1,RGX_CR_TA_PERF_SELECT0_1" hexmask.long 0xC 0.--31. 1. "Reserved_22,Reserved_22" line.long 0x10 "RGX_CR_TA_PERF_SELECT1_0,RGX_CR_TA_PERF_SELECT1_0" hexmask.long.word 0x10 22.--31. 1. "Reserved_22,Reserved_22" newline bitfld.long 0x10 21. "MODE,reduction mode 0: bitwise increments 1: unsigned count increment" "bitwise increments,unsigned count increment" newline hexmask.long.byte 0x10 16.--20. 1. "GROUP_SELECT,group select see full PERF documentation for signals in each group" newline hexmask.long.word 0x10 0.--15. 1. "BIT_SELECT,bit mask for enabled signals in group" line.long 0x14 "RGX_CR_TA_PERF_SELECT1_1,RGX_CR_TA_PERF_SELECT1_1" hexmask.long 0x14 0.--31. 1. "Reserved_22,Reserved_22" line.long 0x18 "RGX_CR_TA_PERF_SELECT2_0,RGX_CR_TA_PERF_SELECT2_0" hexmask.long.word 0x18 22.--31. 1. "Reserved_22,Reserved_22" newline bitfld.long 0x18 21. "MODE,reduction mode 0: bitwise increments 1: unsigned count increment" "bitwise increments,unsigned count increment" newline hexmask.long.byte 0x18 16.--20. 1. "GROUP_SELECT,group select see full PERF documentation for signals in each group" newline hexmask.long.word 0x18 0.--15. 1. "BIT_SELECT,bit mask for enabled signals in group" line.long 0x1C "RGX_CR_TA_PERF_SELECT2_1,RGX_CR_TA_PERF_SELECT2_1" hexmask.long 0x1C 0.--31. 1. "Reserved_22,Reserved_22" line.long 0x20 "RGX_CR_TA_PERF_SELECT3_0,RGX_CR_TA_PERF_SELECT3_0" hexmask.long.word 0x20 22.--31. 1. "Reserved_22,Reserved_22" newline bitfld.long 0x20 21. "MODE,reduction mode 0: bitwise increments 1: unsigned count increment" "bitwise increments,unsigned count increment" newline hexmask.long.byte 0x20 16.--20. 1. "GROUP_SELECT,group select see full PERF documentation for signals in each group" newline hexmask.long.word 0x20 0.--15. 1. "BIT_SELECT,bit mask for enabled signals in group" line.long 0x24 "RGX_CR_TA_PERF_SELECT3_1,RGX_CR_TA_PERF_SELECT3_1" hexmask.long 0x24 0.--31. 1. "Reserved_22,Reserved_22" repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) rgroup.long ($2+0x7648)++0x3 line.long 0x0 "RGX_CR_TA_PERF_SELECTED_BITS_$1,RGX_CR_TA_PERF_SELECTED_BITS_0" hexmask.long.word 0x0 16.--31. 1. "REG1,persent bus signals counter 1" newline hexmask.long.word 0x0 0.--15. 1. "REG0,present bus signals counter 0" repeat.end repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) rgroup.long ($2+0x7650)++0x3 line.long 0x0 "RGX_CR_TA_PERF_COUNTER_0_$1,RGX_CR_TA_PERF_COUNTER_0_0" hexmask.long 0x0 0.--31. 1. "REG,counter a0" repeat.end repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) rgroup.long ($2+0x7658)++0x3 line.long 0x0 "RGX_CR_TA_PERF_COUNTER_1_$1,RGX_CR_TA_PERF_COUNTER_1_0" hexmask.long 0x0 0.--31. 1. "REG,counter a0" repeat.end repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) rgroup.long ($2+0x7660)++0x3 line.long 0x0 "RGX_CR_TA_PERF_COUNTER_2_$1,RGX_CR_TA_PERF_COUNTER_2_0" hexmask.long 0x0 0.--31. 1. "REG,counter a0" repeat.end repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) rgroup.long ($2+0x7668)++0x3 line.long 0x0 "RGX_CR_TA_PERF_COUNTER_3_$1,RGX_CR_TA_PERF_COUNTER_3_0" hexmask.long 0x0 0.--31. 1. "REG,counter a0" repeat.end group.long 0x7700++0x27 line.long 0x0 "RGX_CR_RASTERISATION_PERF_0,RGX_CR_RASTERISATION_PERF_0" hexmask.long 0x0 5.--31. 1. "Reserved_5,Reserved_5" newline bitfld.long 0x0 4. "CLR_3,clear counter 3" "0,1" newline bitfld.long 0x0 3. "CLR_2,clear counter 2" "0,1" newline bitfld.long 0x0 2. "CLR_1,clear counter 1" "0,1" newline bitfld.long 0x0 1. "CLR_0,clear counter 0" "0,1" newline bitfld.long 0x0 0. "CTRL_ENABLE,enables the perf bus counters" "0,1" line.long 0x4 "RGX_CR_RASTERISATION_PERF_1,RGX_CR_RASTERISATION_PERF_1" hexmask.long 0x4 0.--31. 1. "Reserved_5,Reserved_5" line.long 0x8 "RGX_CR_RASTERISATION_PERF_SELECT0_0,RGX_CR_RASTERISATION_PERF_SELECT0_0" hexmask.long.word 0x8 22.--31. 1. "Reserved_22,Reserved_22" newline bitfld.long 0x8 21. "MODE,reduction mode 0: bitwise increments 1: unsigned count increment" "bitwise increments,unsigned count increment" newline hexmask.long.byte 0x8 16.--20. 1. "GROUP_SELECT,group select see full PERF documenrasterisationtion for signals in each group" newline hexmask.long.word 0x8 0.--15. 1. "BIT_SELECT,bit mask for enabled signals in group" line.long 0xC "RGX_CR_RASTERISATION_PERF_SELECT0_1,RGX_CR_RASTERISATION_PERF_SELECT0_1" hexmask.long 0xC 0.--31. 1. "Reserved_22,Reserved_22" line.long 0x10 "RGX_CR_RASTERISATION_PERF_SELECT1_0,RGX_CR_RASTERISATION_PERF_SELECT1_0" hexmask.long.word 0x10 22.--31. 1. "Reserved_22,Reserved_22" newline bitfld.long 0x10 21. "MODE,reduction mode 0: bitwise increments 1: unsigned count increment" "bitwise increments,unsigned count increment" newline hexmask.long.byte 0x10 16.--20. 1. "GROUP_SELECT,group select see full PERF documenrasterisationtion for signals in each group" newline hexmask.long.word 0x10 0.--15. 1. "BIT_SELECT,bit mask for enabled signals in group" line.long 0x14 "RGX_CR_RASTERISATION_PERF_SELECT1_1,RGX_CR_RASTERISATION_PERF_SELECT1_1" hexmask.long 0x14 0.--31. 1. "Reserved_22,Reserved_22" line.long 0x18 "RGX_CR_RASTERISATION_PERF_SELECT2_0,RGX_CR_RASTERISATION_PERF_SELECT2_0" hexmask.long.word 0x18 22.--31. 1. "Reserved_22,Reserved_22" newline bitfld.long 0x18 21. "MODE,reduction mode 0: bitwise increments 1: unsigned count increment" "bitwise increments,unsigned count increment" newline hexmask.long.byte 0x18 16.--20. 1. "GROUP_SELECT,group select see full PERF documenrasterisationtion for signals in each group" newline hexmask.long.word 0x18 0.--15. 1. "BIT_SELECT,bit mask for enabled signals in group" line.long 0x1C "RGX_CR_RASTERISATION_PERF_SELECT2_1,RGX_CR_RASTERISATION_PERF_SELECT2_1" hexmask.long 0x1C 0.--31. 1. "Reserved_22,Reserved_22" line.long 0x20 "RGX_CR_RASTERISATION_PERF_SELECT3_0,RGX_CR_RASTERISATION_PERF_SELECT3_0" hexmask.long.word 0x20 22.--31. 1. "Reserved_22,Reserved_22" newline bitfld.long 0x20 21. "MODE,reduction mode 0: bitwise increments 1: unsigned count increment" "bitwise increments,unsigned count increment" newline hexmask.long.byte 0x20 16.--20. 1. "GROUP_SELECT,group select see full PERF documenrasterisationtion for signals in each group" newline hexmask.long.word 0x20 0.--15. 1. "BIT_SELECT,bit mask for enabled signals in group" line.long 0x24 "RGX_CR_RASTERISATION_PERF_SELECT3_1,RGX_CR_RASTERISATION_PERF_SELECT3_1" hexmask.long 0x24 0.--31. 1. "Reserved_22,Reserved_22" repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) rgroup.long ($2+0x7748)++0x3 line.long 0x0 "RGX_CR_RASTERISATION_PERF_SELECTED_BITS_$1,RGX_CR_RASTERISATION_PERF_SELECTED_BITS_0" hexmask.long.word 0x0 16.--31. 1. "REG1,persent bus signals counter 1" newline hexmask.long.word 0x0 0.--15. 1. "REG0,present bus signals counter 0" repeat.end repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) rgroup.long ($2+0x7750)++0x3 line.long 0x0 "RGX_CR_RASTERISATION_PERF_COUNTER_0_$1,RGX_CR_RASTERISATION_PERF_COUNTER_0_0" hexmask.long 0x0 0.--31. 1. "REG,counter a0" repeat.end repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) rgroup.long ($2+0x7758)++0x3 line.long 0x0 "RGX_CR_RASTERISATION_PERF_COUNTER_1_$1,RGX_CR_RASTERISATION_PERF_COUNTER_1_0" hexmask.long 0x0 0.--31. 1. "REG,counter a0" repeat.end repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) rgroup.long ($2+0x7760)++0x3 line.long 0x0 "RGX_CR_RASTERISATION_PERF_COUNTER_2_$1,RGX_CR_RASTERISATION_PERF_COUNTER_2_0" hexmask.long 0x0 0.--31. 1. "REG,counter a0" repeat.end repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) rgroup.long ($2+0x7768)++0x3 line.long 0x0 "RGX_CR_RASTERISATION_PERF_COUNTER_3_$1,RGX_CR_RASTERISATION_PERF_COUNTER_3_0" hexmask.long 0x0 0.--31. 1. "REG,counter a0" repeat.end group.long 0x7800++0x27 line.long 0x0 "RGX_CR_HUB_BIFPMCACHE_PERF_0,RGX_CR_HUB_BIFPMCACHE_PERF_0" hexmask.long 0x0 5.--31. 1. "Reserved_5,Reserved_5" newline bitfld.long 0x0 4. "CLR_3,clear counter 3" "0,1" newline bitfld.long 0x0 3. "CLR_2,clear counter 2" "0,1" newline bitfld.long 0x0 2. "CLR_1,clear counter 1" "0,1" newline bitfld.long 0x0 1. "CLR_0,clear counter 0" "0,1" newline bitfld.long 0x0 0. "CTRL_ENABLE,enables the perf bus counters" "0,1" line.long 0x4 "RGX_CR_HUB_BIFPMCACHE_PERF_1,RGX_CR_HUB_BIFPMCACHE_PERF_1" hexmask.long 0x4 0.--31. 1. "Reserved_5,Reserved_5" line.long 0x8 "RGX_CR_HUB_BIFPMCACHE_PERF_SELECT0_0,RGX_CR_HUB_BIFPMCACHE_PERF_SELECT0_0" hexmask.long.word 0x8 22.--31. 1. "Reserved_22,Reserved_22" newline bitfld.long 0x8 21. "MODE,reduction mode 0: bitwise increments 1: unsigned count increment" "bitwise increments,unsigned count increment" newline hexmask.long.byte 0x8 16.--20. 1. "GROUP_SELECT,group select see full PERF documenhub_bifpmcachetion for signals in each group" newline hexmask.long.word 0x8 0.--15. 1. "BIT_SELECT,bit mask for enabled signals in group" line.long 0xC "RGX_CR_HUB_BIFPMCACHE_PERF_SELECT0_1,RGX_CR_HUB_BIFPMCACHE_PERF_SELECT0_1" hexmask.long 0xC 0.--31. 1. "Reserved_22,Reserved_22" line.long 0x10 "RGX_CR_HUB_BIFPMCACHE_PERF_SELECT1_0,RGX_CR_HUB_BIFPMCACHE_PERF_SELECT1_0" hexmask.long.word 0x10 22.--31. 1. "Reserved_22,Reserved_22" newline bitfld.long 0x10 21. "MODE,reduction mode 0: bitwise increments 1: unsigned count increment" "bitwise increments,unsigned count increment" newline hexmask.long.byte 0x10 16.--20. 1. "GROUP_SELECT,group select see full PERF documenhub_bifpmcachetion for signals in each group" newline hexmask.long.word 0x10 0.--15. 1. "BIT_SELECT,bit mask for enabled signals in group" line.long 0x14 "RGX_CR_HUB_BIFPMCACHE_PERF_SELECT1_1,RGX_CR_HUB_BIFPMCACHE_PERF_SELECT1_1" hexmask.long 0x14 0.--31. 1. "Reserved_22,Reserved_22" line.long 0x18 "RGX_CR_HUB_BIFPMCACHE_PERF_SELECT2_0,RGX_CR_HUB_BIFPMCACHE_PERF_SELECT2_0" hexmask.long.word 0x18 22.--31. 1. "Reserved_22,Reserved_22" newline bitfld.long 0x18 21. "MODE,reduction mode 0: bitwise increments 1: unsigned count increment" "bitwise increments,unsigned count increment" newline hexmask.long.byte 0x18 16.--20. 1. "GROUP_SELECT,group select see full PERF documenhub_bifpmcachetion for signals in each group" newline hexmask.long.word 0x18 0.--15. 1. "BIT_SELECT,bit mask for enabled signals in group" line.long 0x1C "RGX_CR_HUB_BIFPMCACHE_PERF_SELECT2_1,RGX_CR_HUB_BIFPMCACHE_PERF_SELECT2_1" hexmask.long 0x1C 0.--31. 1. "Reserved_22,Reserved_22" line.long 0x20 "RGX_CR_HUB_BIFPMCACHE_PERF_SELECT3_0,RGX_CR_HUB_BIFPMCACHE_PERF_SELECT3_0" hexmask.long.word 0x20 22.--31. 1. "Reserved_22,Reserved_22" newline bitfld.long 0x20 21. "MODE,reduction mode 0: bitwise increments 1: unsigned count increment" "bitwise increments,unsigned count increment" newline hexmask.long.byte 0x20 16.--20. 1. "GROUP_SELECT,group select see full PERF documenhub_bifpmcachetion for signals in each group" newline hexmask.long.word 0x20 0.--15. 1. "BIT_SELECT,bit mask for enabled signals in group" line.long 0x24 "RGX_CR_HUB_BIFPMCACHE_PERF_SELECT3_1,RGX_CR_HUB_BIFPMCACHE_PERF_SELECT3_1" hexmask.long 0x24 0.--31. 1. "Reserved_22,Reserved_22" repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) rgroup.long ($2+0x7848)++0x3 line.long 0x0 "RGX_CR_HUB_BIFPMCACHE_PERF_SELECTED_BITS_$1,RGX_CR_HUB_BIFPMCACHE_PERF_SELECTED_BITS_0" hexmask.long.word 0x0 16.--31. 1. "REG1,persent bus signals counter 1" newline hexmask.long.word 0x0 0.--15. 1. "REG0,present bus signals counter 0" repeat.end repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) rgroup.long ($2+0x7850)++0x3 line.long 0x0 "RGX_CR_HUB_BIFPMCACHE_PERF_COUNTER_0_$1,RGX_CR_HUB_BIFPMCACHE_PERF_COUNTER_0_0" hexmask.long 0x0 0.--31. 1. "REG,counter a0" repeat.end repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) rgroup.long ($2+0x7858)++0x3 line.long 0x0 "RGX_CR_HUB_BIFPMCACHE_PERF_COUNTER_1_$1,RGX_CR_HUB_BIFPMCACHE_PERF_COUNTER_1_0" hexmask.long 0x0 0.--31. 1. "REG,counter a0" repeat.end repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) rgroup.long ($2+0x7860)++0x3 line.long 0x0 "RGX_CR_HUB_BIFPMCACHE_PERF_COUNTER_2_$1,RGX_CR_HUB_BIFPMCACHE_PERF_COUNTER_2_0" hexmask.long 0x0 0.--31. 1. "REG,counter a0" repeat.end repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) rgroup.long ($2+0x7868)++0x3 line.long 0x0 "RGX_CR_HUB_BIFPMCACHE_PERF_COUNTER_3_$1,RGX_CR_HUB_BIFPMCACHE_PERF_COUNTER_3_0" hexmask.long 0x0 0.--31. 1. "REG,counter a0" repeat.end group.long 0x7900++0x27 line.long 0x0 "RGX_CR_TPU_MCU_L0_PERF_0,RGX_CR_TPU_MCU_L0_PERF_0" hexmask.long 0x0 5.--31. 1. "Reserved_5,Reserved_5" newline bitfld.long 0x0 4. "CLR_3,clear counter 3" "0,1" newline bitfld.long 0x0 3. "CLR_2,clear counter 2" "0,1" newline bitfld.long 0x0 2. "CLR_1,clear counter 1" "0,1" newline bitfld.long 0x0 1. "CLR_0,clear counter 0" "0,1" newline bitfld.long 0x0 0. "CTRL_ENABLE,enables the perf bus counters" "0,1" line.long 0x4 "RGX_CR_TPU_MCU_L0_PERF_1,RGX_CR_TPU_MCU_L0_PERF_1" hexmask.long 0x4 0.--31. 1. "Reserved_5,Reserved_5" line.long 0x8 "RGX_CR_TPU_MCU_L0_PERF_SELECT0_0,RGX_CR_TPU_MCU_L0_PERF_SELECT0_0" hexmask.long.word 0x8 22.--31. 1. "Reserved_22,Reserved_22" newline bitfld.long 0x8 21. "MODE,reduction mode 0: bitwise increments 1: unsigned count increment" "bitwise increments,unsigned count increment" newline hexmask.long.byte 0x8 16.--20. 1. "GROUP_SELECT,group select see full PERF documentation for signals in each group" newline hexmask.long.word 0x8 0.--15. 1. "BIT_SELECT,bit mask for enabled signals in group" line.long 0xC "RGX_CR_TPU_MCU_L0_PERF_SELECT0_1,RGX_CR_TPU_MCU_L0_PERF_SELECT0_1" bitfld.long 0xC 30.--31. "Reserved_62,Reserved_62" "0,1,2,3" newline hexmask.long.word 0xC 16.--29. 1. "BATCH_MAX,this is the min batch number which will be counted in this group" newline bitfld.long 0xC 14.--15. "Reserved_46,Reserved_46" "0,1,2,3" newline hexmask.long.word 0xC 0.--13. 1. "BATCH_MIN,this is the min batch number which will be counted in this group" line.long 0x10 "RGX_CR_TPU_MCU_L0_PERF_SELECT1_0,RGX_CR_TPU_MCU_L0_PERF_SELECT1_0" hexmask.long.word 0x10 22.--31. 1. "Reserved_22,Reserved_22" newline bitfld.long 0x10 21. "MODE,reduction mode 0: bitwise increments 1: unsigned count increment" "bitwise increments,unsigned count increment" newline hexmask.long.byte 0x10 16.--20. 1. "GROUP_SELECT,group select see full PERF documentation for signals in each group" newline hexmask.long.word 0x10 0.--15. 1. "BIT_SELECT,bit mask for enabled signals in group" line.long 0x14 "RGX_CR_TPU_MCU_L0_PERF_SELECT1_1,RGX_CR_TPU_MCU_L0_PERF_SELECT1_1" bitfld.long 0x14 30.--31. "Reserved_62,Reserved_62" "0,1,2,3" newline hexmask.long.word 0x14 16.--29. 1. "BATCH_MAX,this is the min batch number which will be counted in this group" newline bitfld.long 0x14 14.--15. "Reserved_46,Reserved_46" "0,1,2,3" newline hexmask.long.word 0x14 0.--13. 1. "BATCH_MIN,this is the min batch number which will be counted in this group" line.long 0x18 "RGX_CR_TPU_MCU_L0_PERF_SELECT2_0,RGX_CR_TPU_MCU_L0_PERF_SELECT2_0" hexmask.long.word 0x18 22.--31. 1. "Reserved_22,Reserved_22" newline bitfld.long 0x18 21. "MODE,reduction mode 0: bitwise increments 1: unsigned count increment" "bitwise increments,unsigned count increment" newline hexmask.long.byte 0x18 16.--20. 1. "GROUP_SELECT,group select see full PERF documentation for signals in each group" newline hexmask.long.word 0x18 0.--15. 1. "BIT_SELECT,bit mask for enabled signals in group" line.long 0x1C "RGX_CR_TPU_MCU_L0_PERF_SELECT2_1,RGX_CR_TPU_MCU_L0_PERF_SELECT2_1" bitfld.long 0x1C 30.--31. "Reserved_62,Reserved_62" "0,1,2,3" newline hexmask.long.word 0x1C 16.--29. 1. "BATCH_MAX,this is the min batch number which will be counted in this group" newline bitfld.long 0x1C 14.--15. "Reserved_46,Reserved_46" "0,1,2,3" newline hexmask.long.word 0x1C 0.--13. 1. "BATCH_MIN,this is the min batch number which will be counted in this group" line.long 0x20 "RGX_CR_TPU_MCU_L0_PERF_SELECT3_0,RGX_CR_TPU_MCU_L0_PERF_SELECT3_0" hexmask.long.word 0x20 22.--31. 1. "Reserved_22,Reserved_22" newline bitfld.long 0x20 21. "MODE,reduction mode 0: bitwise increments 1: unsigned count increment" "bitwise increments,unsigned count increment" newline hexmask.long.byte 0x20 16.--20. 1. "GROUP_SELECT,group select see full PERF documentation for signals in each group" newline hexmask.long.word 0x20 0.--15. 1. "BIT_SELECT,bit mask for enabled signals in group" line.long 0x24 "RGX_CR_TPU_MCU_L0_PERF_SELECT3_1,RGX_CR_TPU_MCU_L0_PERF_SELECT3_1" bitfld.long 0x24 30.--31. "Reserved_62,Reserved_62" "0,1,2,3" newline hexmask.long.word 0x24 16.--29. 1. "BATCH_MAX,this is the min batch number which will be counted in this group" newline bitfld.long 0x24 14.--15. "Reserved_46,Reserved_46" "0,1,2,3" newline hexmask.long.word 0x24 0.--13. 1. "BATCH_MIN,this is the min batch number which will be counted in this group" repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) rgroup.long ($2+0x7948)++0x3 line.long 0x0 "RGX_CR_TPU_MCU_L0_PERF_SELECTED_BITS_$1,RGX_CR_TPU_MCU_L0_PERF_SELECTED_BITS_0" hexmask.long.word 0x0 16.--31. 1. "REG1,persent bus signals counter 1" newline hexmask.long.word 0x0 0.--15. 1. "REG0,present bus signals counter 0" repeat.end repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) rgroup.long ($2+0x7950)++0x3 line.long 0x0 "RGX_CR_TPU_MCU_L0_PERF_COUNTER_0_$1,RGX_CR_TPU_MCU_L0_PERF_COUNTER_0_0" hexmask.long 0x0 0.--31. 1. "REG,counter a0" repeat.end repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) rgroup.long ($2+0x7958)++0x3 line.long 0x0 "RGX_CR_TPU_MCU_L0_PERF_COUNTER_1_$1,RGX_CR_TPU_MCU_L0_PERF_COUNTER_1_0" hexmask.long 0x0 0.--31. 1. "REG,counter a0" repeat.end repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) rgroup.long ($2+0x7960)++0x3 line.long 0x0 "RGX_CR_TPU_MCU_L0_PERF_COUNTER_2_$1,RGX_CR_TPU_MCU_L0_PERF_COUNTER_2_0" hexmask.long 0x0 0.--31. 1. "REG,counter a0" repeat.end repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) rgroup.long ($2+0x7968)++0x3 line.long 0x0 "RGX_CR_TPU_MCU_L0_PERF_COUNTER_3_$1,RGX_CR_TPU_MCU_L0_PERF_COUNTER_3_0" hexmask.long 0x0 0.--31. 1. "REG,counter a0" repeat.end group.long 0x8020++0x7 line.long 0x0 "RGX_CR_USC_TPU_LOW_PRECISION_ENABLE_0,Enable signal to use low precision across USC and TPU (TAG) in coordinates. gradients and LOD value (calculated or supplied)" hexmask.long 0x0 1.--31. 1. "Reserved_1,Reserved_1" newline bitfld.long 0x0 0. "VALUE,VALUE" "0,1" line.long 0x4 "RGX_CR_USC_TPU_LOW_PRECISION_ENABLE_1,Enable signal to use low precision across USC and TPU (TAG) in coordinates. gradients and LOD value (calculated or supplied)" hexmask.long 0x4 0.--31. 1. "Reserved_1,Reserved_1" group.long 0x8100++0x27 line.long 0x0 "RGX_CR_USC_PERF_0,RGX_CR_USC_PERF_0" hexmask.long 0x0 5.--31. 1. "Reserved_5,Reserved_5" newline bitfld.long 0x0 4. "CLR_3,clear counter 3" "0,1" newline bitfld.long 0x0 3. "CLR_2,clear counter 2" "0,1" newline bitfld.long 0x0 2. "CLR_1,clear counter 1" "0,1" newline bitfld.long 0x0 1. "CLR_0,clear counter 0" "0,1" newline bitfld.long 0x0 0. "CTRL_ENABLE,enables the perf bus counters" "0,1" line.long 0x4 "RGX_CR_USC_PERF_1,RGX_CR_USC_PERF_1" hexmask.long 0x4 0.--31. 1. "Reserved_5,Reserved_5" line.long 0x8 "RGX_CR_USC_PERF_SELECT0_0,RGX_CR_USC_PERF_SELECT0_0" hexmask.long.word 0x8 22.--31. 1. "Reserved_22,Reserved_22" newline bitfld.long 0x8 21. "MODE,reduction mode 0: bitwise increments 1: unsigned count increment" "bitwise increments,unsigned count increment" newline hexmask.long.byte 0x8 16.--20. 1. "GROUP_SELECT,group select see full PERF documenusction for signals in each group" newline hexmask.long.word 0x8 0.--15. 1. "BIT_SELECT,bit mask for enabled signals in group" line.long 0xC "RGX_CR_USC_PERF_SELECT0_1,RGX_CR_USC_PERF_SELECT0_1" bitfld.long 0xC 30.--31. "Reserved_62,Reserved_62" "0,1,2,3" newline hexmask.long.word 0xC 16.--29. 1. "BATCH_MAX,this is the min batch number which will be counted in this group" newline bitfld.long 0xC 14.--15. "Reserved_46,Reserved_46" "0,1,2,3" newline hexmask.long.word 0xC 0.--13. 1. "BATCH_MIN,this is the min batch number which will be counted in this group" line.long 0x10 "RGX_CR_USC_PERF_SELECT1_0,RGX_CR_USC_PERF_SELECT1_0" hexmask.long.word 0x10 22.--31. 1. "Reserved_22,Reserved_22" newline bitfld.long 0x10 21. "MODE,reduction mode 0: bitwise increments 1: unsigned count increment" "bitwise increments,unsigned count increment" newline hexmask.long.byte 0x10 16.--20. 1. "GROUP_SELECT,group select see full PERF documenusction for signals in each group" newline hexmask.long.word 0x10 0.--15. 1. "BIT_SELECT,bit mask for enabled signals in group" line.long 0x14 "RGX_CR_USC_PERF_SELECT1_1,RGX_CR_USC_PERF_SELECT1_1" bitfld.long 0x14 30.--31. "Reserved_62,Reserved_62" "0,1,2,3" newline hexmask.long.word 0x14 16.--29. 1. "BATCH_MAX,this is the min batch number which will be counted in this group" newline bitfld.long 0x14 14.--15. "Reserved_46,Reserved_46" "0,1,2,3" newline hexmask.long.word 0x14 0.--13. 1. "BATCH_MIN,this is the min batch number which will be counted in this group" line.long 0x18 "RGX_CR_USC_PERF_SELECT2_0,RGX_CR_USC_PERF_SELECT2_0" hexmask.long.word 0x18 22.--31. 1. "Reserved_22,Reserved_22" newline bitfld.long 0x18 21. "MODE,reduction mode 0: bitwise increments 1: unsigned count increment" "bitwise increments,unsigned count increment" newline hexmask.long.byte 0x18 16.--20. 1. "GROUP_SELECT,group select see full PERF documenusction for signals in each group" newline hexmask.long.word 0x18 0.--15. 1. "BIT_SELECT,bit mask for enabled signals in group" line.long 0x1C "RGX_CR_USC_PERF_SELECT2_1,RGX_CR_USC_PERF_SELECT2_1" bitfld.long 0x1C 30.--31. "Reserved_62,Reserved_62" "0,1,2,3" newline hexmask.long.word 0x1C 16.--29. 1. "BATCH_MAX,this is the min batch number which will be counted in this group" newline bitfld.long 0x1C 14.--15. "Reserved_46,Reserved_46" "0,1,2,3" newline hexmask.long.word 0x1C 0.--13. 1. "BATCH_MIN,this is the min batch number which will be counted in this group" line.long 0x20 "RGX_CR_USC_PERF_SELECT3_0,RGX_CR_USC_PERF_SELECT3_0" hexmask.long.word 0x20 22.--31. 1. "Reserved_22,Reserved_22" newline bitfld.long 0x20 21. "MODE,reduction mode 0: bitwise increments 1: unsigned count increment" "bitwise increments,unsigned count increment" newline hexmask.long.byte 0x20 16.--20. 1. "GROUP_SELECT,group select see full PERF documenusction for signals in each group" newline hexmask.long.word 0x20 0.--15. 1. "BIT_SELECT,bit mask for enabled signals in group" line.long 0x24 "RGX_CR_USC_PERF_SELECT3_1,RGX_CR_USC_PERF_SELECT3_1" bitfld.long 0x24 30.--31. "Reserved_62,Reserved_62" "0,1,2,3" newline hexmask.long.word 0x24 16.--29. 1. "BATCH_MAX,this is the min batch number which will be counted in this group" newline bitfld.long 0x24 14.--15. "Reserved_46,Reserved_46" "0,1,2,3" newline hexmask.long.word 0x24 0.--13. 1. "BATCH_MIN,this is the min batch number which will be counted in this group" repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) rgroup.long ($2+0x8148)++0x3 line.long 0x0 "RGX_CR_USC_PERF_SELECTED_BITS_$1,RGX_CR_USC_PERF_SELECTED_BITS_0" hexmask.long.word 0x0 16.--31. 1. "REG1,persent bus signals counter 1" newline hexmask.long.word 0x0 0.--15. 1. "REG0,present bus signals counter 0" repeat.end repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) rgroup.long ($2+0x8150)++0x3 line.long 0x0 "RGX_CR_USC_PERF_COUNTER_0_$1,RGX_CR_USC_PERF_COUNTER_0_0" hexmask.long 0x0 0.--31. 1. "REG,counter a0" repeat.end repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) rgroup.long ($2+0x8158)++0x3 line.long 0x0 "RGX_CR_USC_PERF_COUNTER_1_$1,RGX_CR_USC_PERF_COUNTER_1_0" hexmask.long 0x0 0.--31. 1. "REG,counter a0" repeat.end repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) rgroup.long ($2+0x8160)++0x3 line.long 0x0 "RGX_CR_USC_PERF_COUNTER_2_$1,RGX_CR_USC_PERF_COUNTER_2_0" hexmask.long 0x0 0.--31. 1. "REG,counter a0" repeat.end repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) rgroup.long ($2+0x8168)++0x3 line.long 0x0 "RGX_CR_USC_PERF_COUNTER_3_$1,RGX_CR_USC_PERF_COUNTER_3_0" hexmask.long 0x0 0.--31. 1. "REG,counter a0" repeat.end group.long 0x8478++0x1F line.long 0x0 "RGX_CR_PBE_PERF_0,RGX_CR_PBE_PERF_0" hexmask.long 0x0 5.--31. 1. "Reserved_5,Reserved_5" newline bitfld.long 0x0 4. "CLR_3,clear counter 3" "0,1" newline bitfld.long 0x0 3. "CLR_2,clear counter 2" "0,1" newline bitfld.long 0x0 2. "CLR_1,clear counter 1" "0,1" newline bitfld.long 0x0 1. "CLR_0,clear counter 0" "0,1" newline bitfld.long 0x0 0. "CTRL_ENABLE,enables the perf bus counters" "0,1" line.long 0x4 "RGX_CR_PBE_PERF_1,RGX_CR_PBE_PERF_1" hexmask.long 0x4 0.--31. 1. "Reserved_5,Reserved_5" line.long 0x8 "RGX_CR_PBE_PERF_SELECT0_0,RGX_CR_PBE_PERF_SELECT0_0" hexmask.long.word 0x8 22.--31. 1. "Reserved_22,Reserved_22" newline bitfld.long 0x8 21. "MODE,reduction mode 0: bitwise increments 1: unsigned count increment" "bitwise increments,unsigned count increment" newline hexmask.long.byte 0x8 16.--20. 1. "GROUP_SELECT,group select see full PERF documentation for signals in each group" newline hexmask.long.word 0x8 0.--15. 1. "BIT_SELECT,bit mask for enabled signals in group" line.long 0xC "RGX_CR_PBE_PERF_SELECT0_1,RGX_CR_PBE_PERF_SELECT0_1" bitfld.long 0xC 30.--31. "Reserved_62,Reserved_62" "0,1,2,3" newline hexmask.long.word 0xC 16.--29. 1. "BATCH_MAX,this is the max batch number which will be counted in this group" newline bitfld.long 0xC 14.--15. "Reserved_46,Reserved_46" "0,1,2,3" newline hexmask.long.word 0xC 0.--13. 1. "BATCH_MIN,this is the min batch number which will be counted in this group" line.long 0x10 "RGX_CR_PBE_PERF_SELECT1_0,RGX_CR_PBE_PERF_SELECT1_0" hexmask.long.word 0x10 22.--31. 1. "Reserved_22,Reserved_22" newline bitfld.long 0x10 21. "MODE,reduction mode 0: bitwise increments 1: unsigned count increment" "bitwise increments,unsigned count increment" newline hexmask.long.byte 0x10 16.--20. 1. "GROUP_SELECT,group select see full PERF documentation for signals in each group" newline hexmask.long.word 0x10 0.--15. 1. "BIT_SELECT,bit mask for enabled signals in group" line.long 0x14 "RGX_CR_PBE_PERF_SELECT1_1,RGX_CR_PBE_PERF_SELECT1_1" bitfld.long 0x14 30.--31. "Reserved_62,Reserved_62" "0,1,2,3" newline hexmask.long.word 0x14 16.--29. 1. "BATCH_MAX,this is the max batch number which will be counted in this group" newline bitfld.long 0x14 14.--15. "Reserved_46,Reserved_46" "0,1,2,3" newline hexmask.long.word 0x14 0.--13. 1. "BATCH_MIN,this is the min batch number which will be counted in this group" line.long 0x18 "RGX_CR_PBE_PERF_SELECT2_0,RGX_CR_PBE_PERF_SELECT2_0" hexmask.long.word 0x18 22.--31. 1. "Reserved_22,Reserved_22" newline bitfld.long 0x18 21. "MODE,reduction mode 0: bitwise increments 1: unsigned count increment" "bitwise increments,unsigned count increment" newline hexmask.long.byte 0x18 16.--20. 1. "GROUP_SELECT,group select see full PERF documentation for signals in each group" newline hexmask.long.word 0x18 0.--15. 1. "BIT_SELECT,bit mask for enabled signals in group" line.long 0x1C "RGX_CR_PBE_PERF_SELECT2_1,RGX_CR_PBE_PERF_SELECT2_1" bitfld.long 0x1C 30.--31. "Reserved_62,Reserved_62" "0,1,2,3" newline hexmask.long.word 0x1C 16.--29. 1. "BATCH_MAX,this is the max batch number which will be counted in this group" newline bitfld.long 0x1C 14.--15. "Reserved_46,Reserved_46" "0,1,2,3" newline hexmask.long.word 0x1C 0.--13. 1. "BATCH_MIN,this is the min batch number which will be counted in this group" group.long 0x84A0++0x7 line.long 0x0 "RGX_CR_PBE_PERF_SELECT3_0,RGX_CR_PBE_PERF_SELECT3_0" hexmask.long.word 0x0 22.--31. 1. "Reserved_22,Reserved_22" newline bitfld.long 0x0 21. "MODE,reduction mode 0: bitwise increments 1: unsigned count increment" "bitwise increments,unsigned count increment" newline hexmask.long.byte 0x0 16.--20. 1. "GROUP_SELECT,group select see full PERF documentation for signals in each group" newline hexmask.long.word 0x0 0.--15. 1. "BIT_SELECT,bit mask for enabled signals in group" line.long 0x4 "RGX_CR_PBE_PERF_SELECT3_1,RGX_CR_PBE_PERF_SELECT3_1" bitfld.long 0x4 30.--31. "Reserved_62,Reserved_62" "0,1,2,3" newline hexmask.long.word 0x4 16.--29. 1. "BATCH_MAX,this is the max batch number which will be counted in this group" newline bitfld.long 0x4 14.--15. "Reserved_46,Reserved_46" "0,1,2,3" newline hexmask.long.word 0x4 0.--13. 1. "BATCH_MIN,this is the min batch number which will be counted in this group" repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) rgroup.long ($2+0x84A8)++0x3 line.long 0x0 "RGX_CR_PBE_PERF_SELECTED_BITS_$1,RGX_CR_PBE_PERF_SELECTED_BITS_0" hexmask.long.word 0x0 16.--31. 1. "REG1,persent bus signals counter 1" newline hexmask.long.word 0x0 0.--15. 1. "REG0,present bus signals counter 0" repeat.end repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) rgroup.long ($2+0x84B0)++0x3 line.long 0x0 "RGX_CR_PBE_PERF_COUNTER_0_$1,RGX_CR_PBE_PERF_COUNTER_0_0" hexmask.long 0x0 0.--31. 1. "REG,counter a0" repeat.end repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) rgroup.long ($2+0x84B8)++0x3 line.long 0x0 "RGX_CR_PBE_PERF_COUNTER_1_$1,RGX_CR_PBE_PERF_COUNTER_1_0" hexmask.long 0x0 0.--31. 1. "REG,counter a0" repeat.end repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) rgroup.long ($2+0x84C0)++0x3 line.long 0x0 "RGX_CR_PBE_PERF_COUNTER_2_$1,RGX_CR_PBE_PERF_COUNTER_2_0" hexmask.long 0x0 0.--31. 1. "REG,counter a0" repeat.end repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) rgroup.long ($2+0x84C8)++0x3 line.long 0x0 "RGX_CR_PBE_PERF_COUNTER_3_$1,RGX_CR_PBE_PERF_COUNTER_3_0" hexmask.long 0x0 0.--31. 1. "REG,counter a0" repeat.end group.long 0xA000++0x7 line.long 0x0 "RGX_CR_BIF_TRUST_0,Define Requestors/Data Masters which are Trusted/Untrusted and enable/disable the Memory Bus Security feature within the Core When enabled the GPU will emit the security signals out through the external memory interface." hexmask.long.word 0x0 17.--31. 1. "Reserved_17,Reserved_17" newline bitfld.long 0x0 16. "ENABLE,Enable Security feature: 0x1 = Enabled 0x0 = Disabled" "Disabled,Enabled" newline hexmask.long.byte 0x0 9.--15. 1. "DM_TRUSTED,Mask of bits which defines which of the remaining Data Masters are trusted: 0x1 = Trusted 0x0 = Untrusted" newline bitfld.long 0x0 8. "OTHER_COMPUTE_DM_TRUSTED,Defines whether other accesses with the Compute DM are trusted: 0x1 = Trusted 0x0 = Untrusted" "Untrusted,Trusted" newline bitfld.long 0x0 7. "MCU_COMPUTE_DM_TRUSTED,Defines whether MCU accesses with the Compute DM are trusted: 0x1 = Trusted 0x0 = Untrusted" "Untrusted,Trusted" newline bitfld.long 0x0 6. "PBE_COMPUTE_DM_TRUSTED,Defines whether PBE accesses with the Compute DM are trusted: 0x1 = Trusted 0x0 = Untrusted" "Untrusted,Trusted" newline bitfld.long 0x0 5. "OTHER_PIXEL_DM_TRUSTED,Defines whether other accesses with the Pixel DM are trusted: 0x1 = Trusted 0x0 = Untrusted" "Untrusted,Trusted" newline bitfld.long 0x0 4. "MCU_PIXEL_DM_TRUSTED,Defines whether MCU accesses with the Pixel DM are trusted: 0x1 = Trusted 0x0 = Untrusted" "Untrusted,Trusted" newline bitfld.long 0x0 3. "PBE_PIXEL_DM_TRUSTED,Defines whether PBE accesses with the Pixel DM are trusted: 0x1 = Trusted 0x0 = Untrusted" "Untrusted,Trusted" newline bitfld.long 0x0 2. "OTHER_VERTEX_DM_TRUSTED,Defines whether other accesses with the Vertex DM are trusted: 0x1 = Trusted 0x0 = Untrusted" "Untrusted,Trusted" newline bitfld.long 0x0 1. "MCU_VERTEX_DM_TRUSTED,Defines whether MCU accesses with the Vertex DM are trusted: 0x1 = Trusted 0x0 = Untrusted" "Untrusted,Trusted" newline bitfld.long 0x0 0. "PBE_VERTEX_DM_TRUSTED,Defines whether PBE accesses with the Vertex DM are trusted: 0x1 = Trusted 0x0 = Untrusted" "Untrusted,Trusted" line.long 0x4 "RGX_CR_BIF_TRUST_1,Define Requestors/Data Masters which are Trusted/Untrusted and enable/disable the Memory Bus Security feature within the Core When enabled the GPU will emit the security signals out through the external memory interface." hexmask.long 0x4 0.--31. 1. "Reserved_17,Reserved_17" group.long 0xA100++0x7 line.long 0x0 "RGX_CR_SYS_BUS_SECURE_0,Setting this register secures the IMG Configuration Registers from the System Bus. In secure mode all registers have read access only by default. When secure mode is being set. the register must be read back to confirm that the.." hexmask.long 0x0 1.--31. 1. "Reserved_1,Reserved_1" newline bitfld.long 0x0 0. "ENABLE,

0 = No System Bus Security

1 = System Bus Restricted

" "No System Bus Security

1 = System Bus..,?" line.long 0x4 "RGX_CR_SYS_BUS_SECURE_1,Setting this register secures the IMG Configuration Registers from the System Bus. In secure mode all registers have read access only by default. When secure mode is being set. the register must be read back to confirm that the.." hexmask.long 0x4 0.--31. 1. "Reserved_1,Reserved_1" repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) group.long ($2+0xA500)++0x3 line.long 0x0 "RGX_CR_FB_CDC_V3_$1,Framebuffer constant detection configuraton registers" hexmask.long.byte 0x0 24.--31. 1. "FBC_FBDC_UV_VAL1,video pixel format constant value" newline hexmask.long.byte 0x0 16.--23. 1. "FBC_FBDC_Y_VAL1,video pixel format constant value" newline hexmask.long.byte 0x0 8.--15. 1. "FBC_FBDC_UV_VAL0,video pixel format constant value" newline hexmask.long.byte 0x0 0.--7. 1. "FBC_FBDC_Y_VAL0,video pixel format constant value" repeat.end group.long 0xA508++0x7 line.long 0x0 "RGX_CR_FBC_FBDC_CR_FILTER_0,FBCDC corrupt tile filter register" hexmask.long 0x0 5.--31. 1. "Reserved_5,Reserved_5" newline hexmask.long.byte 0x0 1.--4. 1. "CLEAR,Clear corrupt tile filter status 1 bit per requester" newline bitfld.long 0x0 0. "ENABLE,Enable corrupt tile filter" "0,1" line.long 0x4 "RGX_CR_FBC_FBDC_CR_FILTER_1,FBCDC corrupt tile filter register" hexmask.long 0x4 0.--31. 1. "Reserved_5,Reserved_5" rgroup.long 0xA510++0x7 line.long 0x0 "RGX_CR_FBC_FBDC_CR_FILTER_STATUS_0,FBCDC corrupt tile filter register" hexmask.long 0x0 4.--31. 1. "Reserved_4,Reserved_4" newline hexmask.long.byte 0x0 0.--3. 1. "FBC_FBDC_CR_FILTER_STATUS,Status of corrupt tile filter 1 bit per requester" line.long 0x4 "RGX_CR_FBC_FBDC_CR_FILTER_STATUS_1,FBCDC corrupt tile filter register" hexmask.long 0x4 0.--31. 1. "Reserved_4,Reserved_4" group.long 0xA518++0x7 line.long 0x0 "RGX_CR_FBC_FBDC_CR_MODE_V3_1_0,Enable FBC_FBDC mode V3_1 for FBC_FBDC textures" hexmask.long 0x0 1.--31. 1. "Reserved_1,Reserved_1" newline bitfld.long 0x0 0. "EN,Enable FBC_FBDC mode V3_1 for FBCDC formats defaults to V3" "0,1" line.long 0x4 "RGX_CR_FBC_FBDC_CR_MODE_V3_1_1,Enable FBC_FBDC mode V3_1 for FBC_FBDC textures" hexmask.long 0x4 0.--31. 1. "Reserved_1,Reserved_1" repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) group.long ($2+0xA520)++0x3 line.long 0x0 "RGX_CR_FBCDC_CC_$1,RGX_CR_FBCDC_CC_0" hexmask.long.byte 0x0 24.--31. 1. "CH3_VAL0,Constant colour detected value for channel 3." newline hexmask.long.byte 0x0 16.--23. 1. "CH2_VAL0,Constant colour detected value for channel 2." newline hexmask.long.byte 0x0 8.--15. 1. "CH1_VAL0,Constant colour detected value for channel 1." newline hexmask.long.byte 0x0 0.--7. 1. "CH0_VAL0,Constant colour detected value for channel 0." repeat.end repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) group.long ($2+0xA528)++0x3 line.long 0x0 "RGX_CR_FBCDC_CC_YUV_$1,RGX_CR_FBCDC_CC_YUV_0" hexmask.long.byte 0x0 26.--31. 1. "Reserved_26,Reserved_26" newline hexmask.long.word 0x0 16.--25. 1. "UV_VAL0,Constant colour detected value uv-plane." newline hexmask.long.byte 0x0 10.--15. 1. "Reserved_10,Reserved_10" newline hexmask.long.word 0x0 0.--9. 1. "Y_VAL0,Constant colour detected value y-plane." repeat.end group.long 0xB000++0x7 line.long 0x0 "RGX_CR_PIPELINE_STATS_ENABLE_0,This register globally enables per DM pipeline statistics counters. Set this register to '1' to allow pipeline statistics counters to increment. Set this register to '0' to inhibit pipeline statistics from incrementing." hexmask.long.word 0x0 17.--31. 1. "Reserved_17,Reserved_17" newline bitfld.long 0x0 16. "COMPUTE,COMPUTE" "0,1" newline hexmask.long.byte 0x0 9.--15. 1. "Reserved_9,Reserved_9" newline bitfld.long 0x0 8. "_3D,_3D" "0,1" newline hexmask.long.byte 0x0 1.--7. 1. "Reserved_1,Reserved_1" newline bitfld.long 0x0 0. "TA,TA" "0,1" line.long 0x4 "RGX_CR_PIPELINE_STATS_ENABLE_1,This register globally enables per DM pipeline statistics counters. Set this register to '1' to allow pipeline statistics counters to increment. Set this register to '0' to inhibit pipeline statistics from incrementing." hexmask.long 0x4 0.--31. 1. "Reserved_17,Reserved_17" wgroup.long 0xB008++0x7 line.long 0x0 "RGX_CR_PIPELINE_STATS_CLEAR_0,Writing '1' to fields of this register resets the pipeline statistics counters per DM The pipeline statistics should normally be cleared before each TA. 3D or Compute kick" hexmask.long.word 0x0 17.--31. 1. "Reserved_17,Reserved_17" newline bitfld.long 0x0 16. "COMPUTE,COMPUTE" "0,1" newline hexmask.long.byte 0x0 9.--15. 1. "Reserved_9,Reserved_9" newline bitfld.long 0x0 8. "_3D,_3D" "0,1" newline hexmask.long.byte 0x0 1.--7. 1. "Reserved_1,Reserved_1" newline bitfld.long 0x0 0. "TA,TA" "0,1" line.long 0x4 "RGX_CR_PIPELINE_STATS_CLEAR_1,Writing '1' to fields of this register resets the pipeline statistics counters per DM The pipeline statistics should normally be cleared before each TA. 3D or Compute kick" hexmask.long 0x4 0.--31. 1. "Reserved_17,Reserved_17" repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) rgroup.long ($2+0xB010)++0x3 line.long 0x0 "RGX_CR_PIPELINE_STATS_IA_VERTICES_$1,Number of vertices the Input Assembly stage generated (not subtracting any caching)" hexmask.long 0x0 0.--31. 1. "COUNT,COUNT" repeat.end repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) rgroup.long ($2+0xB018)++0x3 line.long 0x0 "RGX_CR_PIPELINE_STATS_IA_PRIMITIVES_$1,Number of primitives the Input Assembly stage generated" hexmask.long 0x0 0.--31. 1. "COUNT,COUNT" repeat.end repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) rgroup.long ($2+0xB020)++0x3 line.long 0x0 "RGX_CR_PIPELINE_STATS_VS_INVOCATIONS_$1,Number of times the Vertex Shader is executed" hexmask.long 0x0 0.--31. 1. "COUNT,COUNT" repeat.end repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) rgroup.long ($2+0xB038)++0x3 line.long 0x0 "RGX_CR_PIPELINE_STATS_GS_INVOCATIONS_$1,Number of times the Geometry Shader is executed" hexmask.long 0x0 0.--31. 1. "COUNT,COUNT" repeat.end repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) rgroup.long ($2+0xB040)++0x3 line.long 0x0 "RGX_CR_PIPELINE_STATS_GS_PRIMITIVES_$1,Number of primitives the Geometry Shader generated" hexmask.long 0x0 0.--31. 1. "COUNT,COUNT" repeat.end repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) rgroup.long ($2+0xB048)++0x3 line.long 0x0 "RGX_CR_PIPELINE_STATS_C_INVOCATIONS_$1,Number of times the Clipper is executed" hexmask.long 0x0 0.--31. 1. "COUNT,COUNT" repeat.end repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) rgroup.long ($2+0xB050)++0x3 line.long 0x0 "RGX_CR_PIPELINE_STATS_C_PRIMITIVES_$1,Number of primitives the Clipper generated" hexmask.long 0x0 0.--31. 1. "COUNT,COUNT" repeat.end repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) rgroup.long ($2+0xB058)++0x3 line.long 0x0 "RGX_CR_PIPELINE_STATS_PS_INVOCATIONS_$1,Number of times the Pixel Shader is executed" hexmask.long 0x0 0.--31. 1. "COUNT,COUNT" repeat.end repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) rgroup.long ($2+0xB060)++0x3 line.long 0x0 "RGX_CR_PIPELINE_STATS_CS_INVOCATIONS_$1,Number of times the Compute Shader is executed" hexmask.long 0x0 0.--31. 1. "COUNT,COUNT" repeat.end rgroup.long 0xE000++0x7 line.long 0x0 "RGX_CR_CACHE_CFI_EVENT_0,Global Flush and Invalidation Pending bits for all Texture and Data Caches in the design. The bits are set high after a Flush/Invalidate is requested and will be set low again as each cache in turn completes processing. therefore.." hexmask.long.word 0x0 16.--31. 1. "MCU_L0_PENDING,1 Indicates there is a pending global CFI operation on the specified MCU L0 cache (there can be up to 16 MCU L0 caches depending on the number of clusters)" newline hexmask.long.word 0x0 0.--15. 1. "MADD_PENDING,1 Indicates there is a pending global CFI operation on the specified MADD Texture cache (there can be up to 16 MADD caches depending on the number of clusters)" line.long 0x4 "RGX_CR_CACHE_CFI_EVENT_1,Global Flush and Invalidation Pending bits for all Texture and Data Caches in the design. The bits are set high after a Flush/Invalidate is requested and will be set low again as each cache in turn completes processing. therefore.." hexmask.long.tbyte 0x4 9.--31. 1. "Reserved_41,Reserved_41" newline bitfld.long 0x4 8. "SLC_PENDING,1 Indicates there is a pending global CFI operation on the SLC cache" "0,1" newline hexmask.long.byte 0x4 0.--7. 1. "MCU_L1_PENDING,1 Indicates there is a pending global CFI operation on the specified MCU L1 cache (there can be up to 8 MCU L1 caches depending on the number of clusters)" group.long 0xE138++0x7 line.long 0x0 "RGX_CR_MMU_CTRL_INVAL_0,MMU invalidation control registers" hexmask.long.tbyte 0x0 12.--31. 1. "Reserved_12,Reserved_12" newline bitfld.long 0x0 11. "ALL_CONTEXTS,When ALL_CONTEXTS is set all context ids get invalidated (global invalidation)" "0,1" newline hexmask.long.byte 0x0 3.--10. 1. "CONTEXT,When ALL_CONTEXTS is not set this field specifies the context id to be invalidated (per-context invalidation)" newline bitfld.long 0x0 2. "PC,Invalidates PC PD & PT" "0,1" newline bitfld.long 0x0 1. "PD,Invalidates PD & PT" "0,1" newline bitfld.long 0x0 0. "PT,Invalidates PT" "0,1" line.long 0x4 "RGX_CR_MMU_CTRL_INVAL_1,MMU invalidation control registers" hexmask.long 0x4 0.--31. 1. "Reserved_12,Reserved_12" repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) rgroup.long ($2+0xF100)++0x3 line.long 0x0 "RGX_CR_FB_CDC_PWR_NUM_$1,Power Monitoring registers for the FBCDC" hexmask.long 0x0 0.--31. 1. "FBDC,Number of accesses to the FBDC per clock" repeat.end repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) rgroup.long ($2+0xF108)++0x3 line.long 0x0 "RGX_CR_FB_CDC_PWR_NUM_MCU_$1,Power Monitoring registers for the FBCDC" hexmask.long 0x0 0.--31. 1. "FBTC,Number of accesses to the MCU FBTC per clock" repeat.end rgroup.long 0xF220++0xF line.long 0x0 "RGX_CR_BIF_BLACKPEARL_RTN_FIFO_WORD_COUNT_0,Blackpearl BIF return FIFO word count" hexmask.long.tbyte 0x0 9.--31. 1. "Reserved_9,Reserved_9" newline hexmask.long.word 0x0 0.--8. 1. "COUNTER,COUNTER" line.long 0x4 "RGX_CR_BIF_BLACKPEARL_RTN_FIFO_WORD_COUNT_1,Blackpearl BIF return FIFO word count" hexmask.long 0x4 0.--31. 1. "Reserved_9,Reserved_9" line.long 0x8 "RGX_CR_BIF_JONES_RTN_FIFO_WORD_COUNT_0,Jones BIF return FIFO word count" hexmask.long.tbyte 0x8 9.--31. 1. "Reserved_9,Reserved_9" newline hexmask.long.word 0x8 0.--8. 1. "COUNTER,COUNTER" line.long 0xC "RGX_CR_BIF_JONES_RTN_FIFO_WORD_COUNT_1,Jones BIF return FIFO word count" hexmask.long 0xC 0.--31. 1. "Reserved_9,Reserved_9" group.long 0xF258++0x7 line.long 0x0 "RGX_CR_TDM_GRIDOFFSET_0,Sample position grid offset for use when MSAA/ODAA is DISABLED DX (0.0.0.0) OpenGL (0.5.0.5) Acts as the 9th multisample position when MSAA is ENABLED." hexmask.long.tbyte 0x0 8.--31. 1. "Reserved_8,Reserved_8" newline hexmask.long.byte 0x0 4.--7. 1. "GRID_Y,Unsigned sub-pixel offset" newline hexmask.long.byte 0x0 0.--3. 1. "GRID_X,Unsigned sub-pixel offset" line.long 0x4 "RGX_CR_TDM_GRIDOFFSET_1,Sample position grid offset for use when MSAA/ODAA is DISABLED DX (0.0.0.0) OpenGL (0.5.0.5) Acts as the 9th multisample position when MSAA is ENABLED." hexmask.long 0x4 0.--31. 1. "Reserved_8,Reserved_8" repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) group.long ($2+0xF260)++0x3 line.long 0x0 "RGX_CR_TDM_MULTISAMPLECTL_$1,Sample position grid offset for use in 2x. 4x. 8xMSAA and ODAA modes." hexmask.long.byte 0x0 28.--31. 1. "MSAA_Y3,Unsigned sub-pixel offset for the 4th multisample Y position" newline hexmask.long.byte 0x0 24.--27. 1. "MSAA_X3,Unsigned sub-pixel offset for the 4th multisample X position" newline hexmask.long.byte 0x0 20.--23. 1. "MSAA_Y2,Unsigned sub-pixel offset for the 3rd multisample Y position" newline hexmask.long.byte 0x0 16.--19. 1. "MSAA_X2,Unsigned sub-pixel offset for the 3rd multisample X position" newline hexmask.long.byte 0x0 12.--15. 1. "MSAA_Y1,Unsigned sub-pixel offset for the 2nd multisample Y position" newline hexmask.long.byte 0x0 8.--11. 1. "MSAA_X1,Unsigned sub-pixel offset for the 2nd multisample X position" newline hexmask.long.byte 0x0 4.--7. 1. "MSAA_Y0,Unsigned sub-pixel offset for the 1st multisample Y position" newline hexmask.long.byte 0x0 0.--3. 1. "MSAA_X0,Unsigned sub-pixel offset for the 1st multisample X position" repeat.end group.long 0xF268++0x7 line.long 0x0 "RGX_CR_USC_CODE_BASE_2D_0,RGX_CR_USC_CODE_BASE_2D_0" hexmask.long 0x0 6.--31. 1. "ADDR,2D Data Master Code Base Register bits" newline hexmask.long.byte 0x0 0.--5. 1. "Reserved_0,Reserved_0" line.long 0x4 "RGX_CR_USC_CODE_BASE_2D_1,RGX_CR_USC_CODE_BASE_2D_1" hexmask.long.tbyte 0x4 8.--31. 1. "Reserved_40,Reserved_40" newline hexmask.long.byte 0x4 0.--7. 1. "ADDR,2D Data Master Code Base Register bits" group.long 0x10B00++0x7 line.long 0x0 "RGX_CR_MTS_SCHEDULE1_0,This register allows firmware tasks to be scheduled on the META (Garten) core." hexmask.long.tbyte 0x0 9.--31. 1. "Reserved_9,Reserved_9" newline bitfld.long 0x0 8. "HOST,Host Interrupte kick" "0,1" newline bitfld.long 0x0 6.--7. "PRIORITY,DataMaster Priority" "0,1,2,3" newline bitfld.long 0x0 5. "CONTEXT,CONTEXT" "0,1" newline bitfld.long 0x0 4. "TASK,TASK" "0,1" newline hexmask.long.byte 0x0 0.--3. 1. "DM,DataMaster Type" line.long 0x4 "RGX_CR_MTS_SCHEDULE1_1,This register allows firmware tasks to be scheduled on the META (Garten) core." hexmask.long 0x4 0.--31. 1. "Reserved_9,Reserved_9" rgroup.long 0x10B98++0x17 line.long 0x0 "RGX_CR_MTS_INTCTX1_0,This register contains the sideband data for the MTS internal interrupt context registers" bitfld.long 0x0 30.--31. "Reserved_30,Reserved_30" "0,1,2,3" newline hexmask.long.byte 0x0 22.--29. 1. "DM_HOST_SCHEDULE,A 1 bit counter per DM for host requests" newline hexmask.long.byte 0x0 16.--21. 1. "Reserved_16,Reserved_16" newline hexmask.long.byte 0x0 8.--15. 1. "DM_TIMER_SCHEDULE,A 1 bit counter per DM for timer requests" newline hexmask.long.byte 0x0 0.--7. 1. "DM_INTERRUPT_SCHEDULE,A 1 bit counter per DM for interrupt requests" line.long 0x4 "RGX_CR_MTS_INTCTX1_1,This register contains the sideband data for the MTS internal interrupt context registers" hexmask.long 0x4 0.--31. 1. "Reserved_30,Reserved_30" line.long 0x8 "RGX_CR_MTS_BGCTX1_0,This register contains the sideband data for the MTS internal background context registers" hexmask.long.tbyte 0x8 8.--31. 1. "Reserved_8,Reserved_8" newline hexmask.long.byte 0x8 0.--7. 1. "DM_NONCOUNTED_SCHEDULE,A 1 bit counter per DM for non-counted background request" line.long 0xC "RGX_CR_MTS_BGCTX1_1,This register contains the sideband data for the MTS internal background context registers" hexmask.long 0xC 0.--31. 1. "Reserved_8,Reserved_8" line.long 0x10 "RGX_CR_MTS_BGCTX_COUNTED_SCHEDULE1_0,This register contains the sideband data for the MTS internal counted background context counters" hexmask.long.byte 0x10 24.--31. 1. "DM3,A 8 bit counter for DM3" newline hexmask.long.byte 0x10 16.--23. 1. "DM2,A 8 bit counter for DM2" newline hexmask.long.byte 0x10 8.--15. 1. "DM1,A 8 bit counter for DM1" newline hexmask.long.byte 0x10 0.--7. 1. "DM0,A 8 bit counter for DM0" line.long 0x14 "RGX_CR_MTS_BGCTX_COUNTED_SCHEDULE1_1,This register contains the sideband data for the MTS internal counted background context counters" hexmask.long.word 0x14 16.--31. 1. "Reserved_48,Reserved_48" newline hexmask.long.byte 0x14 8.--15. 1. "DM5,A 8 bit counter for DM5" newline hexmask.long.byte 0x14 0.--7. 1. "DM4,A 8 bit counter for DM4" rgroup.long 0x10BD8++0x7 line.long 0x0 "RGX_CR_IRQ_OS1_EVENT_STATUS_0,This register indicates the source of a per-OS host interrupt. This register is set by the firmware and cleared by the host." hexmask.long 0x0 1.--31. 1. "Reserved_1,Reserved_1" newline bitfld.long 0x0 0. "SOURCE,SOURCE" "0,1" line.long 0x4 "RGX_CR_IRQ_OS1_EVENT_STATUS_1,This register indicates the source of a per-OS host interrupt. This register is set by the firmware and cleared by the host." hexmask.long 0x4 0.--31. 1. "Reserved_1,Reserved_1" group.long 0x10BE8++0x7 line.long 0x0 "RGX_CR_IRQ_OS1_EVENT_CLEAR_0,This register clears a per-OS host interrupt." hexmask.long 0x0 1.--31. 1. "Reserved_1,Reserved_1" newline bitfld.long 0x0 0. "SOURCE,SOURCE" "0,1" line.long 0x4 "RGX_CR_IRQ_OS1_EVENT_CLEAR_1,This register clears a per-OS host interrupt." hexmask.long 0x4 0.--31. 1. "Reserved_1,Reserved_1" group.long 0x20B00++0x7 line.long 0x0 "RGX_CR_MTS_SCHEDULE2_0,This register allows firmware tasks to be scheduled on the META (Garten) core." hexmask.long.tbyte 0x0 9.--31. 1. "Reserved_9,Reserved_9" newline bitfld.long 0x0 8. "HOST,Host Interrupte kick" "0,1" newline bitfld.long 0x0 6.--7. "PRIORITY,DataMaster Priority" "0,1,2,3" newline bitfld.long 0x0 5. "CONTEXT,CONTEXT" "0,1" newline bitfld.long 0x0 4. "TASK,TASK" "0,1" newline hexmask.long.byte 0x0 0.--3. 1. "DM,DataMaster Type" line.long 0x4 "RGX_CR_MTS_SCHEDULE2_1,This register allows firmware tasks to be scheduled on the META (Garten) core." hexmask.long 0x4 0.--31. 1. "Reserved_9,Reserved_9" rgroup.long 0x20B98++0x17 line.long 0x0 "RGX_CR_MTS_INTCTX2_0,This register contains the sideband data for the MTS internal interrupt context registers" bitfld.long 0x0 30.--31. "Reserved_30,Reserved_30" "0,1,2,3" newline hexmask.long.byte 0x0 22.--29. 1. "DM_HOST_SCHEDULE,A 1 bit counter per DM for host requests" newline hexmask.long.byte 0x0 16.--21. 1. "Reserved_16,Reserved_16" newline hexmask.long.byte 0x0 8.--15. 1. "DM_TIMER_SCHEDULE,A 1 bit counter per DM for timer requests" newline hexmask.long.byte 0x0 0.--7. 1. "DM_INTERRUPT_SCHEDULE,A 1 bit counter per DM for interrupt requests" line.long 0x4 "RGX_CR_MTS_INTCTX2_1,This register contains the sideband data for the MTS internal interrupt context registers" hexmask.long 0x4 0.--31. 1. "Reserved_30,Reserved_30" line.long 0x8 "RGX_CR_MTS_BGCTX2_0,This register contains the sideband data for the MTS internal background context registers" hexmask.long.tbyte 0x8 8.--31. 1. "Reserved_8,Reserved_8" newline hexmask.long.byte 0x8 0.--7. 1. "DM_NONCOUNTED_SCHEDULE,A 1 bit counter per DM for non-counted background request" line.long 0xC "RGX_CR_MTS_BGCTX2_1,This register contains the sideband data for the MTS internal background context registers" hexmask.long 0xC 0.--31. 1. "Reserved_8,Reserved_8" line.long 0x10 "RGX_CR_MTS_BGCTX_COUNTED_SCHEDULE2_0,This register contains the sideband data for the MTS internal counted background context counters" hexmask.long.byte 0x10 24.--31. 1. "DM3,A 8 bit counter for DM3" newline hexmask.long.byte 0x10 16.--23. 1. "DM2,A 8 bit counter for DM2" newline hexmask.long.byte 0x10 8.--15. 1. "DM1,A 8 bit counter for DM1" newline hexmask.long.byte 0x10 0.--7. 1. "DM0,A 8 bit counter for DM0" line.long 0x14 "RGX_CR_MTS_BGCTX_COUNTED_SCHEDULE2_1,This register contains the sideband data for the MTS internal counted background context counters" hexmask.long.word 0x14 16.--31. 1. "Reserved_48,Reserved_48" newline hexmask.long.byte 0x14 8.--15. 1. "DM5,A 8 bit counter for DM5" newline hexmask.long.byte 0x14 0.--7. 1. "DM4,A 8 bit counter for DM4" rgroup.long 0x20BD8++0x7 line.long 0x0 "RGX_CR_IRQ_OS2_EVENT_STATUS_0,This register indicates the source of a per-OS host interrupt. This register is set by the firmware and cleared by the host." hexmask.long 0x0 1.--31. 1. "Reserved_1,Reserved_1" newline bitfld.long 0x0 0. "SOURCE,SOURCE" "0,1" line.long 0x4 "RGX_CR_IRQ_OS2_EVENT_STATUS_1,This register indicates the source of a per-OS host interrupt. This register is set by the firmware and cleared by the host." hexmask.long 0x4 0.--31. 1. "Reserved_1,Reserved_1" group.long 0x20BE8++0x7 line.long 0x0 "RGX_CR_IRQ_OS2_EVENT_CLEAR_0,This register clears a per-OS host interrupt." hexmask.long 0x0 1.--31. 1. "Reserved_1,Reserved_1" newline bitfld.long 0x0 0. "SOURCE,SOURCE" "0,1" line.long 0x4 "RGX_CR_IRQ_OS2_EVENT_CLEAR_1,This register clears a per-OS host interrupt." hexmask.long 0x4 0.--31. 1. "Reserved_1,Reserved_1" group.long 0x30B00++0x7 line.long 0x0 "RGX_CR_MTS_SCHEDULE3_0,This register allows firmware tasks to be scheduled on the META (Garten) core." hexmask.long.tbyte 0x0 9.--31. 1. "Reserved_9,Reserved_9" newline bitfld.long 0x0 8. "HOST,Host Interrupte kick" "0,1" newline bitfld.long 0x0 6.--7. "PRIORITY,DataMaster Priority" "0,1,2,3" newline bitfld.long 0x0 5. "CONTEXT,CONTEXT" "0,1" newline bitfld.long 0x0 4. "TASK,TASK" "0,1" newline hexmask.long.byte 0x0 0.--3. 1. "DM,DataMaster Type" line.long 0x4 "RGX_CR_MTS_SCHEDULE3_1,This register allows firmware tasks to be scheduled on the META (Garten) core." hexmask.long 0x4 0.--31. 1. "Reserved_9,Reserved_9" rgroup.long 0x30B98++0x17 line.long 0x0 "RGX_CR_MTS_INTCTX3_0,This register contains the sideband data for the MTS internal interrupt context registers" bitfld.long 0x0 30.--31. "Reserved_30,Reserved_30" "0,1,2,3" newline hexmask.long.byte 0x0 22.--29. 1. "DM_HOST_SCHEDULE,A 1 bit counter per DM for host requests" newline hexmask.long.byte 0x0 16.--21. 1. "Reserved_16,Reserved_16" newline hexmask.long.byte 0x0 8.--15. 1. "DM_TIMER_SCHEDULE,A 1 bit counter per DM for timer requests" newline hexmask.long.byte 0x0 0.--7. 1. "DM_INTERRUPT_SCHEDULE,A 1 bit counter per DM for interrupt requests" line.long 0x4 "RGX_CR_MTS_INTCTX3_1,This register contains the sideband data for the MTS internal interrupt context registers" hexmask.long 0x4 0.--31. 1. "Reserved_30,Reserved_30" line.long 0x8 "RGX_CR_MTS_BGCTX3_0,This register contains the sideband data for the MTS internal background context registers" hexmask.long.tbyte 0x8 8.--31. 1. "Reserved_8,Reserved_8" newline hexmask.long.byte 0x8 0.--7. 1. "DM_NONCOUNTED_SCHEDULE,A 1 bit counter per DM for non-counted background request" line.long 0xC "RGX_CR_MTS_BGCTX3_1,This register contains the sideband data for the MTS internal background context registers" hexmask.long 0xC 0.--31. 1. "Reserved_8,Reserved_8" line.long 0x10 "RGX_CR_MTS_BGCTX_COUNTED_SCHEDULE3_0,This register contains the sideband data for the MTS internal counted background context counters" hexmask.long.byte 0x10 24.--31. 1. "DM3,A 8 bit counter for DM3" newline hexmask.long.byte 0x10 16.--23. 1. "DM2,A 8 bit counter for DM2" newline hexmask.long.byte 0x10 8.--15. 1. "DM1,A 8 bit counter for DM1" newline hexmask.long.byte 0x10 0.--7. 1. "DM0,A 8 bit counter for DM0" line.long 0x14 "RGX_CR_MTS_BGCTX_COUNTED_SCHEDULE3_1,This register contains the sideband data for the MTS internal counted background context counters" hexmask.long.word 0x14 16.--31. 1. "Reserved_48,Reserved_48" newline hexmask.long.byte 0x14 8.--15. 1. "DM5,A 8 bit counter for DM5" newline hexmask.long.byte 0x14 0.--7. 1. "DM4,A 8 bit counter for DM4" rgroup.long 0x30BD8++0x7 line.long 0x0 "RGX_CR_IRQ_OS3_EVENT_STATUS_0,This register indicates the source of a per-OS host interrupt. This register is set by the firmware and cleared by the host." hexmask.long 0x0 1.--31. 1. "Reserved_1,Reserved_1" newline bitfld.long 0x0 0. "SOURCE,SOURCE" "0,1" line.long 0x4 "RGX_CR_IRQ_OS3_EVENT_STATUS_1,This register indicates the source of a per-OS host interrupt. This register is set by the firmware and cleared by the host." hexmask.long 0x4 0.--31. 1. "Reserved_1,Reserved_1" group.long 0x30BE8++0x7 line.long 0x0 "RGX_CR_IRQ_OS3_EVENT_CLEAR_0,This register clears a per-OS host interrupt." hexmask.long 0x0 1.--31. 1. "Reserved_1,Reserved_1" newline bitfld.long 0x0 0. "SOURCE,SOURCE" "0,1" line.long 0x4 "RGX_CR_IRQ_OS3_EVENT_CLEAR_1,This register clears a per-OS host interrupt." hexmask.long 0x4 0.--31. 1. "Reserved_1,Reserved_1" group.long 0x40B00++0x7 line.long 0x0 "RGX_CR_MTS_SCHEDULE4_0,This register allows firmware tasks to be scheduled on the META (Garten) core." hexmask.long.tbyte 0x0 9.--31. 1. "Reserved_9,Reserved_9" newline bitfld.long 0x0 8. "HOST,Host Interrupte kick" "0,1" newline bitfld.long 0x0 6.--7. "PRIORITY,DataMaster Priority" "0,1,2,3" newline bitfld.long 0x0 5. "CONTEXT,CONTEXT" "0,1" newline bitfld.long 0x0 4. "TASK,TASK" "0,1" newline hexmask.long.byte 0x0 0.--3. 1. "DM,DataMaster Type" line.long 0x4 "RGX_CR_MTS_SCHEDULE4_1,This register allows firmware tasks to be scheduled on the META (Garten) core." hexmask.long 0x4 0.--31. 1. "Reserved_9,Reserved_9" rgroup.long 0x40B98++0x17 line.long 0x0 "RGX_CR_MTS_INTCTX4_0,This register contains the sideband data for the MTS internal interrupt context registers" bitfld.long 0x0 30.--31. "Reserved_30,Reserved_30" "0,1,2,3" newline hexmask.long.byte 0x0 22.--29. 1. "DM_HOST_SCHEDULE,A 1 bit counter per DM for host requests" newline hexmask.long.byte 0x0 16.--21. 1. "Reserved_16,Reserved_16" newline hexmask.long.byte 0x0 8.--15. 1. "DM_TIMER_SCHEDULE,A 1 bit counter per DM for timer requests" newline hexmask.long.byte 0x0 0.--7. 1. "DM_INTERRUPT_SCHEDULE,A 1 bit counter per DM for interrupt requests" line.long 0x4 "RGX_CR_MTS_INTCTX4_1,This register contains the sideband data for the MTS internal interrupt context registers" hexmask.long 0x4 0.--31. 1. "Reserved_30,Reserved_30" line.long 0x8 "RGX_CR_MTS_BGCTX4_0,This register contains the sideband data for the MTS internal background context registers" hexmask.long.tbyte 0x8 8.--31. 1. "Reserved_8,Reserved_8" newline hexmask.long.byte 0x8 0.--7. 1. "DM_NONCOUNTED_SCHEDULE,A 1 bit counter per DM for non-counted background request" line.long 0xC "RGX_CR_MTS_BGCTX4_1,This register contains the sideband data for the MTS internal background context registers" hexmask.long 0xC 0.--31. 1. "Reserved_8,Reserved_8" line.long 0x10 "RGX_CR_MTS_BGCTX_COUNTED_SCHEDULE4_0,This register contains the sideband data for the MTS internal counted background context counters" hexmask.long.byte 0x10 24.--31. 1. "DM3,A 8 bit counter for DM3" newline hexmask.long.byte 0x10 16.--23. 1. "DM2,A 8 bit counter for DM2" newline hexmask.long.byte 0x10 8.--15. 1. "DM1,A 8 bit counter for DM1" newline hexmask.long.byte 0x10 0.--7. 1. "DM0,A 8 bit counter for DM0" line.long 0x14 "RGX_CR_MTS_BGCTX_COUNTED_SCHEDULE4_1,This register contains the sideband data for the MTS internal counted background context counters" hexmask.long.word 0x14 16.--31. 1. "Reserved_48,Reserved_48" newline hexmask.long.byte 0x14 8.--15. 1. "DM5,A 8 bit counter for DM5" newline hexmask.long.byte 0x14 0.--7. 1. "DM4,A 8 bit counter for DM4" rgroup.long 0x40BD8++0x7 line.long 0x0 "RGX_CR_IRQ_OS4_EVENT_STATUS_0,This register indicates the source of a per-OS host interrupt. This register is set by the firmware and cleared by the host." hexmask.long 0x0 1.--31. 1. "Reserved_1,Reserved_1" newline bitfld.long 0x0 0. "SOURCE,SOURCE" "0,1" line.long 0x4 "RGX_CR_IRQ_OS4_EVENT_STATUS_1,This register indicates the source of a per-OS host interrupt. This register is set by the firmware and cleared by the host." hexmask.long 0x4 0.--31. 1. "Reserved_1,Reserved_1" group.long 0x40BE8++0x7 line.long 0x0 "RGX_CR_IRQ_OS4_EVENT_CLEAR_0,This register clears a per-OS host interrupt." hexmask.long 0x0 1.--31. 1. "Reserved_1,Reserved_1" newline bitfld.long 0x0 0. "SOURCE,SOURCE" "0,1" line.long 0x4 "RGX_CR_IRQ_OS4_EVENT_CLEAR_1,This register clears a per-OS host interrupt." hexmask.long 0x4 0.--31. 1. "Reserved_1,Reserved_1" group.long 0x50B00++0x7 line.long 0x0 "RGX_CR_MTS_SCHEDULE5_0,This register allows firmware tasks to be scheduled on the META (Garten) core." hexmask.long.tbyte 0x0 9.--31. 1. "Reserved_9,Reserved_9" newline bitfld.long 0x0 8. "HOST,Host Interrupte kick" "0,1" newline bitfld.long 0x0 6.--7. "PRIORITY,DataMaster Priority" "0,1,2,3" newline bitfld.long 0x0 5. "CONTEXT,CONTEXT" "0,1" newline bitfld.long 0x0 4. "TASK,TASK" "0,1" newline hexmask.long.byte 0x0 0.--3. 1. "DM,DataMaster Type" line.long 0x4 "RGX_CR_MTS_SCHEDULE5_1,This register allows firmware tasks to be scheduled on the META (Garten) core." hexmask.long 0x4 0.--31. 1. "Reserved_9,Reserved_9" rgroup.long 0x50B98++0x17 line.long 0x0 "RGX_CR_MTS_INTCTX5_0,This register contains the sideband data for the MTS internal interrupt context registers" bitfld.long 0x0 30.--31. "Reserved_30,Reserved_30" "0,1,2,3" newline hexmask.long.byte 0x0 22.--29. 1. "DM_HOST_SCHEDULE,A 1 bit counter per DM for host requests" newline hexmask.long.byte 0x0 16.--21. 1. "Reserved_16,Reserved_16" newline hexmask.long.byte 0x0 8.--15. 1. "DM_TIMER_SCHEDULE,A 1 bit counter per DM for timer requests" newline hexmask.long.byte 0x0 0.--7. 1. "DM_INTERRUPT_SCHEDULE,A 1 bit counter per DM for interrupt requests" line.long 0x4 "RGX_CR_MTS_INTCTX5_1,This register contains the sideband data for the MTS internal interrupt context registers" hexmask.long 0x4 0.--31. 1. "Reserved_30,Reserved_30" line.long 0x8 "RGX_CR_MTS_BGCTX5_0,This register contains the sideband data for the MTS internal background context registers" hexmask.long.tbyte 0x8 8.--31. 1. "Reserved_8,Reserved_8" newline hexmask.long.byte 0x8 0.--7. 1. "DM_NONCOUNTED_SCHEDULE,A 1 bit counter per DM for non-counted background request" line.long 0xC "RGX_CR_MTS_BGCTX5_1,This register contains the sideband data for the MTS internal background context registers" hexmask.long 0xC 0.--31. 1. "Reserved_8,Reserved_8" line.long 0x10 "RGX_CR_MTS_BGCTX_COUNTED_SCHEDULE5_0,This register contains the sideband data for the MTS internal counted background context counters" hexmask.long.byte 0x10 24.--31. 1. "DM3,A 8 bit counter for DM3" newline hexmask.long.byte 0x10 16.--23. 1. "DM2,A 8 bit counter for DM2" newline hexmask.long.byte 0x10 8.--15. 1. "DM1,A 8 bit counter for DM1" newline hexmask.long.byte 0x10 0.--7. 1. "DM0,A 8 bit counter for DM0" line.long 0x14 "RGX_CR_MTS_BGCTX_COUNTED_SCHEDULE5_1,This register contains the sideband data for the MTS internal counted background context counters" hexmask.long.word 0x14 16.--31. 1. "Reserved_48,Reserved_48" newline hexmask.long.byte 0x14 8.--15. 1. "DM5,A 8 bit counter for DM5" newline hexmask.long.byte 0x14 0.--7. 1. "DM4,A 8 bit counter for DM4" rgroup.long 0x50BD8++0x7 line.long 0x0 "RGX_CR_IRQ_OS5_EVENT_STATUS_0,This register indicates the source of a per-OS host interrupt. This register is set by the firmware and cleared by the host." hexmask.long 0x0 1.--31. 1. "Reserved_1,Reserved_1" newline bitfld.long 0x0 0. "SOURCE,SOURCE" "0,1" line.long 0x4 "RGX_CR_IRQ_OS5_EVENT_STATUS_1,This register indicates the source of a per-OS host interrupt. This register is set by the firmware and cleared by the host." hexmask.long 0x4 0.--31. 1. "Reserved_1,Reserved_1" group.long 0x50BE8++0x7 line.long 0x0 "RGX_CR_IRQ_OS5_EVENT_CLEAR_0,This register clears a per-OS host interrupt." hexmask.long 0x0 1.--31. 1. "Reserved_1,Reserved_1" newline bitfld.long 0x0 0. "SOURCE,SOURCE" "0,1" line.long 0x4 "RGX_CR_IRQ_OS5_EVENT_CLEAR_1,This register clears a per-OS host interrupt." hexmask.long 0x4 0.--31. 1. "Reserved_1,Reserved_1" group.long 0x60B00++0x7 line.long 0x0 "RGX_CR_MTS_SCHEDULE6_0,This register allows firmware tasks to be scheduled on the META (Garten) core." hexmask.long.tbyte 0x0 9.--31. 1. "Reserved_9,Reserved_9" newline bitfld.long 0x0 8. "HOST,Host Interrupte kick" "0,1" newline bitfld.long 0x0 6.--7. "PRIORITY,DataMaster Priority" "0,1,2,3" newline bitfld.long 0x0 5. "CONTEXT,CONTEXT" "0,1" newline bitfld.long 0x0 4. "TASK,TASK" "0,1" newline hexmask.long.byte 0x0 0.--3. 1. "DM,DataMaster Type" line.long 0x4 "RGX_CR_MTS_SCHEDULE6_1,This register allows firmware tasks to be scheduled on the META (Garten) core." hexmask.long 0x4 0.--31. 1. "Reserved_9,Reserved_9" rgroup.long 0x60B98++0x17 line.long 0x0 "RGX_CR_MTS_INTCTX6_0,This register contains the sideband data for the MTS internal interrupt context registers" bitfld.long 0x0 30.--31. "Reserved_30,Reserved_30" "0,1,2,3" newline hexmask.long.byte 0x0 22.--29. 1. "DM_HOST_SCHEDULE,A 1 bit counter per DM for host requests" newline hexmask.long.byte 0x0 16.--21. 1. "Reserved_16,Reserved_16" newline hexmask.long.byte 0x0 8.--15. 1. "DM_TIMER_SCHEDULE,A 1 bit counter per DM for timer requests" newline hexmask.long.byte 0x0 0.--7. 1. "DM_INTERRUPT_SCHEDULE,A 1 bit counter per DM for interrupt requests" line.long 0x4 "RGX_CR_MTS_INTCTX6_1,This register contains the sideband data for the MTS internal interrupt context registers" hexmask.long 0x4 0.--31. 1. "Reserved_30,Reserved_30" line.long 0x8 "RGX_CR_MTS_BGCTX6_0,This register contains the sideband data for the MTS internal background context registers" hexmask.long.tbyte 0x8 8.--31. 1. "Reserved_8,Reserved_8" newline hexmask.long.byte 0x8 0.--7. 1. "DM_NONCOUNTED_SCHEDULE,A 1 bit counter per DM for non-counted background request" line.long 0xC "RGX_CR_MTS_BGCTX6_1,This register contains the sideband data for the MTS internal background context registers" hexmask.long 0xC 0.--31. 1. "Reserved_8,Reserved_8" line.long 0x10 "RGX_CR_MTS_BGCTX_COUNTED_SCHEDULE6_0,This register contains the sideband data for the MTS internal counted background context counters" hexmask.long.byte 0x10 24.--31. 1. "DM3,A 8 bit counter for DM3" newline hexmask.long.byte 0x10 16.--23. 1. "DM2,A 8 bit counter for DM2" newline hexmask.long.byte 0x10 8.--15. 1. "DM1,A 8 bit counter for DM1" newline hexmask.long.byte 0x10 0.--7. 1. "DM0,A 8 bit counter for DM0" line.long 0x14 "RGX_CR_MTS_BGCTX_COUNTED_SCHEDULE6_1,This register contains the sideband data for the MTS internal counted background context counters" hexmask.long.word 0x14 16.--31. 1. "Reserved_48,Reserved_48" newline hexmask.long.byte 0x14 8.--15. 1. "DM5,A 8 bit counter for DM5" newline hexmask.long.byte 0x14 0.--7. 1. "DM4,A 8 bit counter for DM4" rgroup.long 0x60BD8++0x7 line.long 0x0 "RGX_CR_IRQ_OS6_EVENT_STATUS_0,This register indicates the source of a per-OS host interrupt. This register is set by the firmware and cleared by the host." hexmask.long 0x0 1.--31. 1. "Reserved_1,Reserved_1" newline bitfld.long 0x0 0. "SOURCE,SOURCE" "0,1" line.long 0x4 "RGX_CR_IRQ_OS6_EVENT_STATUS_1,This register indicates the source of a per-OS host interrupt. This register is set by the firmware and cleared by the host." hexmask.long 0x4 0.--31. 1. "Reserved_1,Reserved_1" group.long 0x60BE8++0x7 line.long 0x0 "RGX_CR_IRQ_OS6_EVENT_CLEAR_0,This register clears a per-OS host interrupt." hexmask.long 0x0 1.--31. 1. "Reserved_1,Reserved_1" newline bitfld.long 0x0 0. "SOURCE,SOURCE" "0,1" line.long 0x4 "RGX_CR_IRQ_OS6_EVENT_CLEAR_1,This register clears a per-OS host interrupt." hexmask.long 0x4 0.--31. 1. "Reserved_1,Reserved_1" group.long 0x70B00++0x7 line.long 0x0 "RGX_CR_MTS_SCHEDULE7_0,This register allows firmware tasks to be scheduled on the META (Garten) core." hexmask.long.tbyte 0x0 9.--31. 1. "Reserved_9,Reserved_9" newline bitfld.long 0x0 8. "HOST,Host Interrupte kick" "0,1" newline bitfld.long 0x0 6.--7. "PRIORITY,DataMaster Priority" "0,1,2,3" newline bitfld.long 0x0 5. "CONTEXT,CONTEXT" "0,1" newline bitfld.long 0x0 4. "TASK,TASK" "0,1" newline hexmask.long.byte 0x0 0.--3. 1. "DM,DataMaster Type" line.long 0x4 "RGX_CR_MTS_SCHEDULE7_1,This register allows firmware tasks to be scheduled on the META (Garten) core." hexmask.long 0x4 0.--31. 1. "Reserved_9,Reserved_9" rgroup.long 0x70B98++0x17 line.long 0x0 "RGX_CR_MTS_INTCTX7_0,This register contains the sideband data for the MTS internal interrupt context registers" bitfld.long 0x0 30.--31. "Reserved_30,Reserved_30" "0,1,2,3" newline hexmask.long.byte 0x0 22.--29. 1. "DM_HOST_SCHEDULE,A 1 bit counter per DM for host requests" newline hexmask.long.byte 0x0 16.--21. 1. "Reserved_16,Reserved_16" newline hexmask.long.byte 0x0 8.--15. 1. "DM_TIMER_SCHEDULE,A 1 bit counter per DM for timer requests" newline hexmask.long.byte 0x0 0.--7. 1. "DM_INTERRUPT_SCHEDULE,A 1 bit counter per DM for interrupt requests" line.long 0x4 "RGX_CR_MTS_INTCTX7_1,This register contains the sideband data for the MTS internal interrupt context registers" hexmask.long 0x4 0.--31. 1. "Reserved_30,Reserved_30" line.long 0x8 "RGX_CR_MTS_BGCTX7_0,This register contains the sideband data for the MTS internal background context registers" hexmask.long.tbyte 0x8 8.--31. 1. "Reserved_8,Reserved_8" newline hexmask.long.byte 0x8 0.--7. 1. "DM_NONCOUNTED_SCHEDULE,A 1 bit counter per DM for non-counted background request" line.long 0xC "RGX_CR_MTS_BGCTX7_1,This register contains the sideband data for the MTS internal background context registers" hexmask.long 0xC 0.--31. 1. "Reserved_8,Reserved_8" line.long 0x10 "RGX_CR_MTS_BGCTX_COUNTED_SCHEDULE7_0,This register contains the sideband data for the MTS internal counted background context counters" hexmask.long.byte 0x10 24.--31. 1. "DM3,A 8 bit counter for DM3" newline hexmask.long.byte 0x10 16.--23. 1. "DM2,A 8 bit counter for DM2" newline hexmask.long.byte 0x10 8.--15. 1. "DM1,A 8 bit counter for DM1" newline hexmask.long.byte 0x10 0.--7. 1. "DM0,A 8 bit counter for DM0" line.long 0x14 "RGX_CR_MTS_BGCTX_COUNTED_SCHEDULE7_1,This register contains the sideband data for the MTS internal counted background context counters" hexmask.long.word 0x14 16.--31. 1. "Reserved_48,Reserved_48" newline hexmask.long.byte 0x14 8.--15. 1. "DM5,A 8 bit counter for DM5" newline hexmask.long.byte 0x14 0.--7. 1. "DM4,A 8 bit counter for DM4" rgroup.long 0x70BD8++0x7 line.long 0x0 "RGX_CR_IRQ_OS7_EVENT_STATUS_0,This register indicates the source of a per-OS host interrupt. This register is set by the firmware and cleared by the host." hexmask.long 0x0 1.--31. 1. "Reserved_1,Reserved_1" newline bitfld.long 0x0 0. "SOURCE,SOURCE" "0,1" line.long 0x4 "RGX_CR_IRQ_OS7_EVENT_STATUS_1,This register indicates the source of a per-OS host interrupt. This register is set by the firmware and cleared by the host." hexmask.long 0x4 0.--31. 1. "Reserved_1,Reserved_1" group.long 0x70BE8++0x7 line.long 0x0 "RGX_CR_IRQ_OS7_EVENT_CLEAR_0,This register clears a per-OS host interrupt." hexmask.long 0x0 1.--31. 1. "Reserved_1,Reserved_1" newline bitfld.long 0x0 0. "SOURCE,SOURCE" "0,1" line.long 0x4 "RGX_CR_IRQ_OS7_EVENT_CLEAR_1,This register clears a per-OS host interrupt." hexmask.long 0x4 0.--31. 1. "Reserved_1,Reserved_1" tree.end endif tree.end tree "I2C (Inter-Integrated Circuit Interface)" sif (CORENAME()=="CORTEXR5F") repeat 12. (increment 1. 1.) (list ad:0xF00B0000 ad:0xF00C0000 ad:0xF00D0000 ad:0xF00E0000 ad:0xF0AC0000 ad:0xF0AD0000 ad:0xF0AE0000 ad:0xF0AF0000 ad:0xF0B00000 ad:0xF0B10000 ad:0xF0B20000 ad:0xF0B30000) tree "I2C$1" base $2 group.long 0x0++0xB line.long 0x0 "IC_CON,I2C Control Register. This register can be written only when the DW_apb_i2c is disabled. which corresponds to the IC_ENABLE[0] register being set to 0. Writes at other times have no effect. Read/Write Access: - If configuration parameter.." hexmask.long.word 0x0 20.--31. 1. "RSVD_IC_CON_2,IC_CON_2 Reserved bits - Read Only" newline bitfld.long 0x0 19. "SMBUS_PERSISTENT_SLV_ADDR_EN,The bit controls to enable DW_apb_i2c slave as persistent or non persistent slave. If the slave is non-PSA then DW_apb_i2c slave device clears the Address valid flag for both General and Directed Reset ARP command else the.." "SMBus Persistent Slave address control is disabled,SMBus Persistent Slave address control is enabled" newline bitfld.long 0x0 18. "SMBUS_ARP_EN,This bit controls whether DW_apb_i2c should enable Address Resolution Logic in SMBus Mode. The Slave mode will decode the Address Resolution Protocol commands and respond to it. The DW_apb_i2c slave also includes the generation/validity of.." "SMBus ARP control is disabled,SMBus ARP control is enabled" newline bitfld.long 0x0 17. "SMBUS_SLAVE_QUICK_EN,If this bit is set to 1 DW_apb_i2c slave only receives Quick commands in SMBus Mode. If this bit is set to 0 DW_apb_i2c slave receives all bus protocols but not Quick commands. This bit is applicable only in slave mode. Reset.." "SMBus SLave is disabled to receive Quick command,SMBus SLave is enabled to receive Quick command" newline rbitfld.long 0x0 16. "RSVD_OPTIONAL_SAR_CTRL,OPTIONAL_SAR_CTRL Reserved bits - Read Only" "0,1" newline hexmask.long.byte 0x0 12.--15. 1. "RSVD_IC_CON_1,IC_CON_1 Reserved bits - Read Only" newline bitfld.long 0x0 11. "BUS_CLEAR_FEATURE_CTRL,In Master mode: - 1'b1: Bus Clear Feature is enabled. - 1'b0: Bus Clear Feature is Disabled. In Slave mode this register bit is not applicable. Reset value: 0x0. 0x0: Bus Clear Feature is disabled. 0x1: Bus Clear Feature ois.." "Bus Clear Feature is disabled,Bus Clear Feature ois enabled" newline rbitfld.long 0x0 10. "STOP_DET_IF_MASTER_ACTIVE,In Master mode: - 1'b1: issues the STOP_DET interrupt only when master is active. - 1'b0: issues the STOP_DET irrespective of whether master is active or not. Reset value: 0x0. 0x0: Master issues the STOP_DET interrupt.." "Master issues the STOP_DET interrupt..,Master issues the STOP_DET interrupt only when.." newline bitfld.long 0x0 9. "RX_FIFO_FULL_HLD_CTRL,This bit controls whether DW_apb_i2c should hold the bus when the Rx FIFO is physically full to its RX_BUFFER_DEPTH as described in the IC_RX_FULL_HLD_BUS_EN parameter. Reset value: 0x0. 0x0: Overflow when RX_FIFO is full 0x1: Hold.." "Overflow when RX_FIFO is full,Hold bus when RX_FIFO is full" newline bitfld.long 0x0 8. "TX_EMPTY_CTRL,This bit controls the generation of the TX_EMPTY interrupt as described in the IC_RAW_INTR_STAT register. Reset value: 0x0. 0x0: Default behaviour of TX_EMPTY interrupt 0x1: Controlled generation of TX_EMPTY interrupt" "Default behaviour of TX_EMPTY interrupt,Controlled generation of TX_EMPTY interrupt" newline bitfld.long 0x0 7. "STOP_DET_IFADDRESSED,In slave mode: - 1'b1: issues the STOP_DET interrrupt only when it is addressed. - 0'b0: issues the STOP_DET irrespective of whether it's addressed or not. Reset value: 0x0 NOTE: During a general call address this slave does not.." "slave issues STOP_DET intr always,slave issues STOP_DET intr only if addressed" newline bitfld.long 0x0 6. "IC_SLAVE_DISABLE,This bit controls whether I2C has its slave disabled which means once the presetn signal is applied then this bit takes on the value of the configuration parameter IC_SLAVE_DISABLE. You have the choice of having the slave enabled or.." "Slave mode is enabled,Slave mode is disabled" newline bitfld.long 0x0 5. "IC_RESTART_EN,Determines whether RESTART conditions may be sent when acting as a master. Some older slaves do not support handling RESTART conditions; however RESTART conditions are used in several DW_apb_i2c operations. When RESTART is disabled the.." "Master restart disabled,Master restart enabled" newline bitfld.long 0x0 4. "IC_10BITADDR_MASTER,If the I2C_DYNAMIC_TAR_UPDATE configuration parameter is set to 'No' (0) this bit is named IC_10BITADDR_MASTER and controls whether the DW_apb_i2c starts its transfers in 7- or 10-bit addressing mode when acting as a master. If.." "Master 7Bit addressing mode,Master 10Bit addressing mode" newline bitfld.long 0x0 3. "IC_10BITADDR_SLAVE,When acting as a slave this bit controls whether the DW_apb_i2c responds to 7- or 10-bit addresses. - 0: 7-bit addressing. The DW_apb_i2c ignores transactions that involve 10-bit addressing; for 7-bit addressing only the lower 7 bits.." "Slave 7Bit addressing,Slave 10Bit addressing" newline bitfld.long 0x0 1.--2. "SPEED,These bits control at which speed the DW_apb_i2c operates; its setting is relevant only if one is operating the DW_apb_i2c in master mode. Hardware protects against illegal values being programmed by software. These bits must be programmed.." "?,Standard Speed mode of operation,Fast or Fast Plus mode of operation,High Speed mode of operation" newline bitfld.long 0x0 0. "MASTER_MODE,This bit controls whether the DW_apb_i2c master is enabled. Reset value: IC_MASTER_MODE configuration parameter NOTE: Software should ensure that if this bit is written with '1' then bit 6 should also be written with a '1'. 0x0: Master mode.." "Master mode is disabled,Master mode is enabled" line.long 0x4 "IC_TAR,I2C Target Address Register If the configuration parameter I2C_DYNAMIC_TAR_UPDATE is set to 'No' (0). this register is 12 bits wide. and bits 31:12 are reserved. This register can be written to only when IC_ENABLE[0] is set to 0. However. if.." hexmask.long.word 0x4 17.--31. 1. "RSVD_IC_TAR_2,IC_TAR_2 Reserved bits - Read Only" newline bitfld.long 0x4 16. "SMBUS_QUICK_CMD,If bit 11 (SPECIAL) is set to 1 then this bit indicates whether a Quick command is to be performed by the DW_apb_i2c. Reset value: 0x0 0x0: Disables programming of QUICK-CMD transmission 0x1: Enables programming of QUICK-CMD transmission" "Disables programming of QUICK-CMD transmission,Enables programming of QUICK-CMD transmission" newline rbitfld.long 0x4 14.--15. "RSVD_IC_TAR_1,IC_TAR_1 Reserved bits - Read Only" "0,1,2,3" newline rbitfld.long 0x4 13. "RSVD_DEVICE_ID,DEVICE_ID Reserved bits - Read Only" "0,1" newline rbitfld.long 0x4 12. "RSVD_IC_10BITADDR_MASTER,IC_10BITADDR_MASTER Reserved bits - Read Only" "0,1" newline bitfld.long 0x4 11. "SPECIAL,This bit indicates whether software performs a Device-ID or General Call or START BYTE command. - 0: ignore bit 10 GC_OR_START and use IC_TAR normally - 1: perform special I2C command as specified in Device_ID or GC_OR_START bit Reset value: 0x0.." "Disables programming of GENERAL_CALL or..,Enables programming of GENERAL_CALL or.." newline bitfld.long 0x4 10. "GC_OR_START,If bit 11 (SPECIAL) is set to 1 and bit 13(Device-ID) is set to 0 then this bit indicates whether a General Call or START byte command is to be performed by the DW_apb_i2c. - 0: General Call Address - after issuing a General Call only.." "GENERAL_CALL byte transmission,START byte transmission" newline hexmask.long.word 0x4 0.--9. 1. "IC_TAR,This is the target address for any master transaction. When transmitting a General Call these bits are ignored. To generate a START BYTE the CPU needs to write only once into these bits. If the IC_TAR and IC_SAR are the same loopback exists but.." line.long 0x8 "IC_SAR,I2C Slave Address Register" hexmask.long.tbyte 0x8 10.--31. 1. "RSVD_IC_SAR,IC_SAR Reserved bits - Read Only" newline hexmask.long.word 0x8 0.--9. 1. "IC_SAR,The IC_SAR holds the slave address when the I2C is operating as a slave. For 7-bit addressing only IC_SAR[6:0] is used. This register can be written only when the I2C interface is disabled which corresponds to the IC_ENABLE[0] register being set.." group.long 0x10++0x13 line.long 0x0 "IC_DATA_CMD,I2C Rx/Tx Data Buffer and Command Register; this is the register the CPU writes to when filling the TX FIFO and the CPU reads from when retrieving bytes from RX FIFO. The size of the register changes as follows: Write: - 11 bits when.." hexmask.long.tbyte 0x0 12.--31. 1. "RSVD_IC_DATA_CMD,IC_DATA_CMD Reserved bits - Read Only" newline rbitfld.long 0x0 11. "FIRST_DATA_BYTE,Indicates the first data byte received after the address phase for receive transfer in Master receiver or Slave receiver mode. Reset value : 0x0 NOTE: In case of APB_DATA_WIDTH=8 1. The user has to perform two APB Reads to IC_DATA_CMD in.." "Sequential data byte received,Non sequential data byte received" newline bitfld.long 0x0 10. "RESTART,This bit controls whether a RESTART is issued before the byte is sent or received. This bit is available only if IC_EMPTYFIFO_HOLD_MASTER_EN is configured to 1. 1 - If IC_RESTART_EN is 1 a RESTART is issued before the data is sent/received.." "Donot Issue RESTART before this command,Issue RESTART before this command" newline bitfld.long 0x0 9. "STOP,This bit controls whether a STOP is issued after the byte is sent or received. This bit is available only if IC_EMPTYFIFO_HOLD_MASTER_EN is configured to 1. - 1 - STOP is issued after this byte regardless of whether or not the Tx FIFO is empty. If.." "Donot Issue STOP after this command,Issue STOP after this command" newline bitfld.long 0x0 8. "CMD,This bit controls whether a read or a write is performed. This bit does not control the direction when the DW_apb_i2c acts as a slave. It controls only the direction when it acts as a master. When a command is entered in the TX FIFO this bit.." "Master Write Command,Master Read Command" newline hexmask.long.byte 0x0 0.--7. 1. "DAT,This register contains the data to be transmitted or received on the I2C bus. If you are writing to this register and want to perform a read bits 7:0 (DAT) are ignored by the DW_apb_i2c. However when you read this register these bits return the.." line.long 0x4 "IC_SS_SCL_HCNT,Standard Speed I2C Clock SCL High Count Register" hexmask.long.word 0x4 16.--31. 1. "RSVD_IC_SS_SCL_HIGH_COUNT,IC_SS_SCL_HCNT Reserved bits - Read Only" newline hexmask.long.word 0x4 0.--15. 1. "IC_SS_SCL_HCNT,This register must be set before any I2C bus transaction can take place to ensure proper I/O timing. This register sets the SCL clock high-period count for standard speed. For more information refer to 'IC_CLK Frequency Configuration'." line.long 0x8 "IC_SS_SCL_LCNT,Standard Speed I2C Clock SCL Low Count Register" hexmask.long.word 0x8 16.--31. 1. "RSVD_IC_SS_SCL_LOW_COUNT,RSVD_IC_SS_SCL_LOW_COUNT Reserved bits - Read Only" newline hexmask.long.word 0x8 0.--15. 1. "IC_SS_SCL_LCNT,This register must be set before any I2C bus transaction can take place to ensure proper I/O timing. This register sets the SCL clock low period count for standard speed. For more information refer to 'IC_CLK Frequency Configuration' This.." line.long 0xC "IC_FS_SCL_HCNT,Fast Mode or Fast Mode Plus I2C Clock SCL High Count Register" hexmask.long.word 0xC 16.--31. 1. "RSVD_IC_FS_SCL_HCNT,IC_FS_SCL_HCNT Reserved bits - Read Only" newline hexmask.long.word 0xC 0.--15. 1. "IC_FS_SCL_HCNT,This register must be set before any I2C bus transaction can take place to ensure proper I/O timing. This register sets the SCL clock high-period count for fast mode or fast mode plus. It is used in high-speed mode to send the Master Code.." line.long 0x10 "IC_FS_SCL_LCNT,Fast Mode or Fast Mode Plus I2C Clock SCL Low Count Register" hexmask.long.word 0x10 16.--31. 1. "RSVD_IC_FS_SCL_LCNT,IC_FS_SCL_LCNT Reserved bits - Read Only" newline hexmask.long.word 0x10 0.--15. 1. "IC_FS_SCL_LCNT,This register must be set before any I2C bus transaction can take place to ensure proper I/O timing. This register sets the SCL clock low period count for fast speed. It is used in high-speed mode to send the Master Code and START BYTE or.." rgroup.long 0x2C++0x3 line.long 0x0 "IC_INTR_STAT,I2C Interrupt Status Register Each bit in this register has a corresponding mask bit in the IC_INTR_MASK register. These bits are cleared by reading the matching interrupt clear register. The unmasked raw versions of these bits are available.." hexmask.long.tbyte 0x0 15.--31. 1. "RSVD_IC_INTR_STAT,IC_INTR_STAT Reserved bits - Read Only" newline bitfld.long 0x0 14. "R_SCL_STUCK_AT_LOW,See IC_RAW_INTR_STAT for a detailed description of R_SCL_STUCK_AT_LOW bit. Reset Value: 0x0 0x1: R_SCL_STUCK_AT_LOW interrupt is active 0x0: R_SCL_STUCK_AT_LOW interrupt is inactive" "R_SCL_STUCK_AT_LOW interrupt is inactive,R_SCL_STUCK_AT_LOW interrupt is active" newline bitfld.long 0x0 13. "R_MASTER_ON_HOLD,See IC_RAW_INTR_STAT for a detailed description of R_MASTER_ON_HOLD bit. Reset value: 0x0 0x1: R_MASTER_ON_HOLD interrupt is active 0x0: R_MASTER_ON_HOLD interrupt is inactive" "R_MASTER_ON_HOLD interrupt is inactive,R_MASTER_ON_HOLD interrupt is active" newline bitfld.long 0x0 12. "R_RESTART_DET,See IC_RAW_INTR_STAT for a detailed description of R_RESTART_DET bit. Reset value: 0x0 0x1: R_RESTART_DET interrupt is active 0x0: R_RESTART_DET interrupt is inactive" "R_RESTART_DET interrupt is inactive,R_RESTART_DET interrupt is active" newline bitfld.long 0x0 11. "R_GEN_CALL,See IC_RAW_INTR_STAT for a detailed description of R_GEN_CALL bit. Reset value: 0x0 0x1: R_GEN_CALL interrupt is active 0x0: R_GEN_CALL interrupt is inactive" "R_GEN_CALL interrupt is inactive,R_GEN_CALL interrupt is active" newline bitfld.long 0x0 10. "R_START_DET,See IC_RAW_INTR_STAT for a detailed description of R_START_DET bit. Reset value: 0x0 0x1: R_START_DET interrupt is active 0x0: R_START_DET interrupt is inactive" "R_START_DET interrupt is inactive,R_START_DET interrupt is active" newline bitfld.long 0x0 9. "R_STOP_DET,See IC_RAW_INTR_STAT for a detailed description of R_STOP_DET bit. Reset value: 0x0 0x1: R_STOP_DET interrupt is active 0x0: R_STOP_DET interrupt is inactive" "R_STOP_DET interrupt is inactive,R_STOP_DET interrupt is active" newline bitfld.long 0x0 8. "R_ACTIVITY,See IC_RAW_INTR_STAT for a detailed description of R_ACTIVITY bit. Reset value: 0x0 0x1: R_ACTIVITY interrupt is active 0x0: R_ACTIVITY interrupt is inactive" "R_ACTIVITY interrupt is inactive,R_ACTIVITY interrupt is active" newline bitfld.long 0x0 7. "R_RX_DONE,See IC_RAW_INTR_STAT for a detailed description of R_RX_DONE bit. Reset value: 0x0 0x1: R_RX_DONE interrupt is active 0x0: R_RX_DONE interrupt is inactive" "R_RX_DONE interrupt is inactive,R_RX_DONE interrupt is active" newline bitfld.long 0x0 6. "R_TX_ABRT,See IC_RAW_INTR_STAT for a detailed description of R_TX_ABRT bit. Reset value: 0x0 0x1: R_TX_ABRT interrupt is active 0x0: R_TX_ABRT interrupt is inactive" "R_TX_ABRT interrupt is inactive,R_TX_ABRT interrupt is active" newline bitfld.long 0x0 5. "R_RD_REQ,See IC_RAW_INTR_STAT for a detailed description of R_RD_REQ bit. Reset value: 0x0 0x1: R_RD_REQ interrupt is active 0x0: R_RD_REQ interrupt is inactive" "R_RD_REQ interrupt is inactive,R_RD_REQ interrupt is active" newline bitfld.long 0x0 4. "R_TX_EMPTY,See IC_RAW_INTR_STAT for a detailed description of R_TX_EMPTY bit. Reset value: 0x0 0x1: R_TX_EMPTY interrupt is active 0x0: R_TX_EMPTY interrupt is inactive" "R_TX_EMPTY interrupt is inactive,R_TX_EMPTY interrupt is active" newline bitfld.long 0x0 3. "R_TX_OVER,See IC_RAW_INTR_STAT for a detailed description of R_TX_OVER bit. Reset value: 0x0 0x1: R_TX_OVER interrupt is active 0x0: R_TX_OVER interrupt is inactive" "R_TX_OVER interrupt is inactive,R_TX_OVER interrupt is active" newline bitfld.long 0x0 2. "R_RX_FULL,See IC_RAW_INTR_STAT for a detailed description of R_RX_FULL bit. Reset value: 0x0 0x1: R_RX_FULL interrupt is active 0x0: R_RX_FULL interrupt is inactive" "R_RX_FULL interrupt is inactive,R_RX_FULL interrupt is active" newline bitfld.long 0x0 1. "R_RX_OVER,See IC_RAW_INTR_STAT for a detailed description of R_RX_OVER bit. Reset value: 0x0 0x1: R_RX_OVER interrupt is active 0x0: R_RX_OVER interrupt is inactive" "R_RX_OVER interrupt is inactive,R_RX_OVER interrupt is active" newline bitfld.long 0x0 0. "R_RX_UNDER,See IC_RAW_INTR_STAT for a detailed description of R_RX_UNDER bit. Reset value: 0x0 0x1: RX_UNDER interrupt is active 0x0: RX_UNDER interrupt is inactive" "RX_UNDER interrupt is inactive,RX_UNDER interrupt is active" group.long 0x30++0x3 line.long 0x0 "IC_INTR_MASK,I2C Interrupt Mask Register. These bits mask their corresponding interrupt status bits. This register is active low; a value of 0 masks the interrupt. whereas a value of 1 unmasks the interrupt." hexmask.long.tbyte 0x0 15.--31. 1. "RSVD_IC_INTR_STAT,IC_INTR_STAT Reserved bits - Read Only" newline bitfld.long 0x0 14. "M_SCL_STUCK_AT_LOW,This bit masks the R_SCL_STUCK_AT_LOW interrupt in IC_INTR_STAT register. Reset Value: 0x0 0x1: SCL_STUCK_AT_LOW interrupt is unmasked 0x0: SCL_STUCK_AT_LOW interrupt is masked" "SCL_STUCK_AT_LOW interrupt is masked,SCL_STUCK_AT_LOW interrupt is unmasked" newline rbitfld.long 0x0 13. "M_MASTER_ON_HOLD_READ_ONLY,This M_MASTER_ON_HOLD_read_only bit masks the R_MASTER_ON_HOLD interrupt in IC_INTR_STAT register. Reset value: 0x0 0x1: MASTER_ON_HOLD interrupt is unmasked 0x0: MASTER_ON_HOLD interrupt is masked" "MASTER_ON_HOLD interrupt is masked,MASTER_ON_HOLD interrupt is unmasked" newline bitfld.long 0x0 12. "M_RESTART_DET,This bit masks the R_RESTART_DET interrupt in IC_INTR_STAT register. Reset value: 0x0 0x1: RESTART_DET interrupt is unmasked 0x0: RESTART_DET interrupt is masked" "RESTART_DET interrupt is masked,RESTART_DET interrupt is unmasked" newline bitfld.long 0x0 11. "M_GEN_CALL,This bit masks the R_GEN_CALL interrupt in IC_INTR_STAT register. Reset value: 0x1 0x1: GEN_CALL interrupt is unmasked 0x0: GEN_CALL interrupt is masked" "GEN_CALL interrupt is masked,GEN_CALL interrupt is unmasked" newline bitfld.long 0x0 10. "M_START_DET,This bit masks the R_START_DET interrupt in IC_INTR_STAT register. Reset value: 0x0 0x1: START_DET interrupt is unmasked 0x0: START_DET interrupt is masked" "START_DET interrupt is masked,START_DET interrupt is unmasked" newline bitfld.long 0x0 9. "M_STOP_DET,This bit masks the R_STOP_DET interrupt in IC_INTR_STAT register. Reset value: 0x0 0x1: STOP_DET interrupt is unmasked 0x0: STOP_DET interrupt is masked" "STOP_DET interrupt is masked,STOP_DET interrupt is unmasked" newline bitfld.long 0x0 8. "M_ACTIVITY,This bit masks the R_ACTIVITY interrupt in IC_INTR_STAT register. Reset value: 0x0 0x1: ACTIVITY interrupt is unmasked 0x0: ACTIVITY interrupt is masked" "ACTIVITY interrupt is masked,ACTIVITY interrupt is unmasked" newline bitfld.long 0x0 7. "M_RX_DONE,This bit masks the R_RX_DONE interrupt in IC_INTR_STAT register. Reset value: 0x1 0x1: RX_DONE interrupt is unmasked 0x0: RX_DONE interrupt is masked" "RX_DONE interrupt is masked,RX_DONE interrupt is unmasked" newline bitfld.long 0x0 6. "M_TX_ABRT,This bit masks the R_TX_ABRT interrupt in IC_INTR_STAT register. Reset value: 0x1 0x1: TX_ABORT interrupt is unmasked 0x0: TX_ABORT interrupt is masked" "TX_ABORT interrupt is masked,TX_ABORT interrupt is unmasked" newline bitfld.long 0x0 5. "M_RD_REQ,This bit masks the R_RD_REQ interrupt in IC_INTR_STAT register. Reset value: 0x1 0x1: RD_REQ interrupt is unmasked 0x0: RD_REQ interrupt is masked" "RD_REQ interrupt is masked,RD_REQ interrupt is unmasked" newline bitfld.long 0x0 4. "M_TX_EMPTY,This bit masks the R_TX_EMPTY interrupt in IC_INTR_STAT register. Reset value: 0x1 0x1: TX_EMPTY interrupt is unmasked 0x0: TX_EMPTY interrupt is masked" "TX_EMPTY interrupt is masked,TX_EMPTY interrupt is unmasked" newline bitfld.long 0x0 3. "M_TX_OVER,This bit masks the R_TX_OVER interrupt in IC_INTR_STAT register. Reset value: 0x1 0x1: TX_OVER interrupt is unmasked 0x0: TX_OVER interrupt is masked" "TX_OVER interrupt is masked,TX_OVER interrupt is unmasked" newline bitfld.long 0x0 2. "M_RX_FULL,This bit masks the R_RX_FULL interrupt in IC_INTR_STAT register. Reset value: 0x1 0x1: RX_FULL interrupt is unmasked 0x0: RX_FULL interrupt is masked" "RX_FULL interrupt is masked,RX_FULL interrupt is unmasked" newline bitfld.long 0x0 1. "M_RX_OVER,This bit masks the R_RX_OVER interrupt in IC_INTR_STAT register. Reset value: 0x1 0x1: RX_OVER interrupt is unmasked 0x0: RX_OVER interrupt is masked" "RX_OVER interrupt is masked,RX_OVER interrupt is unmasked" newline bitfld.long 0x0 0. "M_RX_UNDER,This bit masks the R_RX_UNDER interrupt in IC_INTR_STAT register. Reset value: 0x1 0x1: RX_UNDER interrupt is unmasked 0x0: RX_UNDER interrupt is masked" "RX_UNDER interrupt is masked,RX_UNDER interrupt is unmasked" rgroup.long 0x34++0x3 line.long 0x0 "IC_RAW_INTR_STAT,I2C Raw Interrupt Status Register Unlike the IC_INTR_STAT register. these bits are not masked so they always show the true status of the DW_apb_i2c." hexmask.long.tbyte 0x0 15.--31. 1. "RSVD_IC_RAW_INTR_STAT,IC_RAW_INTR_STAT Reserved bits - Read Only" newline bitfld.long 0x0 14. "SCL_STUCK_AT_LOW,Indicates whether the SCL Line is stuck at low for the IC_SCL_STUCK_LOW_TIMEOUT number of ic_clk periods. Enabled only when IC_BUS_CLEAR_FEATURE=1 and IC_ULTRA_FAST_MODE=0. Reset Value: 0x0 0x1: SCL_STUCK_AT_LOW interrupt is active 0x0:.." "SCL_STUCK_AT_LOW interrupt is inactive,SCL_STUCK_AT_LOW interrupt is active" newline bitfld.long 0x0 13. "MASTER_ON_HOLD,Indicates whether master is holding the bus and TX FIFO is empty. Enabled only when I2C_DYNAMIC_TAR_UPDATE=1 and IC_EMPTYFIFO_HOLD_MASTER_EN=1. Reset value: 0x0 0x1: MASTER_ON_HOLD interrupt is active 0x0: MASTER_ON_HOLD interrupt is.." "MASTER_ON_HOLD interrupt is inactive,MASTER_ON_HOLD interrupt is active" newline bitfld.long 0x0 12. "RESTART_DET,Indicates whether a RESTART condition has occurred on the I2C interface when DW_apb_i2c is operating in Slave mode and the slave is being addressed. Enabled only when IC_SLV_RESTART_DET_EN=1. Note: However in high-speed mode or during a.." "RESTART_DET interrupt is inactive,RESTART_DET interrupt is active" newline bitfld.long 0x0 11. "GEN_CALL,Set only when a General Call address is received and it is acknowledged. It stays set until it is cleared either by disabling DW_apb_i2c or when the CPU reads bit 0 of the IC_CLR_GEN_CALL register. DW_apb_i2c stores the received data in the Rx.." "GEN_CALL interrupt is inactive,GEN_CALL interrupt is active" newline bitfld.long 0x0 10. "START_DET,Indicates whether a START or RESTART condition has occurred on the I2C interface regardless of whether DW_apb_i2c is operating in slave or master mode. Reset value: 0x0 0x1: START_DET interrupt is active 0x0: START_DET interrupt is inactive" "START_DET interrupt is inactive,START_DET interrupt is active" newline bitfld.long 0x0 9. "STOP_DET,Indicates whether a STOP condition has occurred on the I2C interface regardless of whether DW_apb_i2c is operating in slave or master mode. In Slave Mode: - If IC_CON[7]=1'b1 (STOP_DET_IFADDRESSED) the STOP_DET interrupt will be issued only if.." "STOP_DET interrupt is inactive,STOP_DET interrupt is active" newline bitfld.long 0x0 8. "ACTIVITY,This bit captures DW_apb_i2c activity and stays set until it is cleared. There are four ways to clear it: - Disabling the DW_apb_i2c - Reading the IC_CLR_ACTIVITY register - Reading the IC_CLR_INTR register - System reset Once this bit is set.." "RAW_INTR_ACTIVITY interrupt is inactive,RAW_INTR_ACTIVITY interrupt is active" newline bitfld.long 0x0 7. "RX_DONE,When the DW_apb_i2c is acting as a slave-transmitter this bit is set to 1 if the master does not acknowledge a transmitted byte. This occurs on the last byte of the transmission indicating that the transmission is done. Reset value: 0x0 0x1:.." "RX_DONE interrupt is inactive,RX_DONE interrupt is active" newline bitfld.long 0x0 6. "TX_ABRT,This bit indicates if DW_apb_i2c as an I2C transmitter is unable to complete the intended actions on the contents of the transmit FIFO. This situation can occur both as an I2C master or an I2C slave and is referred to as a 'transmit abort'." "TX_ABRT interrupt is inactive,TX_ABRT interrupt is active" newline bitfld.long 0x0 5. "RD_REQ,This bit is set to 1 when DW_apb_i2c is acting as a slave and another I2C master is attempting to read data from DW_apb_i2c. The DW_apb_i2c holds the I2C bus in a wait state (SCL=0) until this interrupt is serviced which means that the slave has.." "RD_REQ interrupt is inactive,RD_REQ interrupt is active" newline bitfld.long 0x0 4. "TX_EMPTY,The behavior of the TX_EMPTY interrupt status differs based on the TX_EMPTY_CTRL selection in the IC_CON register. - When TX_EMPTY_CTRL = 0: This bit is set to 1 when the transmit buffer is at or below the threshold value set in the IC_TX_TL.." "TX_EMPTY interrupt is inactive,TX_EMPTY interrupt is active" newline bitfld.long 0x0 3. "TX_OVER,Set during transmit if the transmit buffer is filled to IC_TX_BUFFER_DEPTH and the processor attempts to issue another I2C command by writing to the IC_DATA_CMD register. When the module is disabled this bit keeps its level until the master or.." "TX_OVER interrupt is inactive,TX_OVER interrupt is active" newline bitfld.long 0x0 2. "RX_FULL,Set when the receive buffer reaches or goes above the RX_TL threshold in the IC_RX_TL register. It is automatically cleared by hardware when buffer level goes below the threshold. If the module is disabled (IC_ENABLE[0]=0) the RX FIFO is flushed.." "RX_FULL interrupt is inactive,RX_FULL interrupt is active" newline bitfld.long 0x0 1. "RX_OVER,Set if the receive buffer is completely filled to IC_RX_BUFFER_DEPTH and an additional byte is received from an external I2C device. The DW_apb_i2c acknowledges this but any data bytes received after the FIFO is full are lost. If the module is.." "RX_OVER interrupt is inactive,RX_OVER interrupt is active" newline bitfld.long 0x0 0. "RX_UNDER,Set if the processor attempts to read the receive buffer when it is empty by reading from the IC_DATA_CMD register. If the module is disabled (IC_ENABLE[0]=0) this bit keeps its level until the master or slave state machines go into idle and.." "RX_UNDER interrupt is inactive,RX_UNDER interrupt is active" group.long 0x38++0x7 line.long 0x0 "IC_RX_TL,I2C Receive FIFO Threshold Register" hexmask.long.tbyte 0x0 8.--31. 1. "RSVD_IC_RX_TL,IC_RX_TL Reserved bits - Read Only" newline hexmask.long.byte 0x0 0.--7. 1. "RX_TL,Receive FIFO Threshold Level. Controls the level of entries (or above) that triggers the RX_FULL interrupt (bit 2 in IC_RAW_INTR_STAT register). The valid range is 0-255 with the additional restriction that hardware does not allow this value to be.." line.long 0x4 "IC_TX_TL,I2C Transmit FIFO Threshold Register" hexmask.long.tbyte 0x4 8.--31. 1. "RSVD_IC_TX_TL,IC_TX_TL Reserved bits - Read Only" newline hexmask.long.byte 0x4 0.--7. 1. "TX_TL,Transmit FIFO Threshold Level. Controls the level of entries (or below) that trigger the TX_EMPTY interrupt (bit 4 in IC_RAW_INTR_STAT register). The valid range is 0-255 with the additional restriction that it may not be set to value larger than.." rgroup.long 0x40++0x2B line.long 0x0 "IC_CLR_INTR,Clear Combined and Individual Interrupt Register" hexmask.long 0x0 1.--31. 1. "RSVD_IC_CLR_INTR,CLR_INTR Reserved bits - Read Only" newline bitfld.long 0x0 0. "CLR_INTR,Read this register to clear the combined interrupt all individual interrupts and the IC_TX_ABRT_SOURCE register. This bit does not clear hardware clearable interrupts but software clearable interrupts. Refer to Bit 9 of the IC_TX_ABRT_SOURCE.." "0,1" line.long 0x4 "IC_CLR_RX_UNDER,Clear RX_UNDER Interrupt Register" hexmask.long 0x4 1.--31. 1. "RSVD_IC_CLR_RX_UNDER,IC_CLR_RX_UNDER Reserved bits - Read Only" newline bitfld.long 0x4 0. "CLR_RX_UNDER,Read this register to clear the RX_UNDER interrupt (bit 0) of the IC_RAW_INTR_STAT register. Reset value: 0x0" "0,1" line.long 0x8 "IC_CLR_RX_OVER,Clear RX_OVER Interrupt Register" hexmask.long 0x8 1.--31. 1. "RSVD_IC_CLR_RX_OVER,IC_CLR_RX_OVER Reserved bits - Read Only" newline bitfld.long 0x8 0. "CLR_RX_OVER,Read this register to clear the RX_OVER interrupt (bit 1) of the IC_RAW_INTR_STAT register. Reset value: 0x0" "0,1" line.long 0xC "IC_CLR_TX_OVER,Clear TX_OVER Interrupt Register" hexmask.long 0xC 1.--31. 1. "RSVD_IC_CLR_TX_OVER,IC_CLR_TX_OVER Reserved bits - Read Only" newline bitfld.long 0xC 0. "CLR_TX_OVER,Read this register to clear the TX_OVER interrupt (bit 3) of the IC_RAW_INTR_STAT register. Reset value: 0x0" "0,1" line.long 0x10 "IC_CLR_RD_REQ,Clear RD_REQ Interrupt Register" hexmask.long 0x10 1.--31. 1. "RSVD_IC_CLR_RD_REQ,IC_CLR_RD_REQ Reserved bits - Read Only" newline bitfld.long 0x10 0. "CLR_RD_REQ,Read this register to clear the RD_REQ interrupt (bit 5) of the IC_RAW_INTR_STAT register. Reset value: 0x0" "0,1" line.long 0x14 "IC_CLR_TX_ABRT,Clear TX_ABRT Interrupt Register" hexmask.long 0x14 1.--31. 1. "RSVD_IC_CLR_TX_ABRT,IC_CLR_TX_ABRT Reserved bits - Read Only" newline bitfld.long 0x14 0. "CLR_TX_ABRT,Read this register to clear the TX_ABRT interrupt (bit 6) of the IC_RAW_INTR_STAT register and the IC_TX_ABRT_SOURCE register. This also releases the TX FIFO from the flushed/reset state allowing more writes to the TX FIFO. Refer to Bit 9.." "0,1" line.long 0x18 "IC_CLR_RX_DONE,Clear RX_DONE Interrupt Register" hexmask.long 0x18 1.--31. 1. "RSVD_IC_CLR_RX_DONE,IC_CLR_RX_DONE Reserved bits - Read Only" newline bitfld.long 0x18 0. "CLR_RX_DONE,Read this register to clear the RX_DONE interrupt (bit 7) of the IC_RAW_INTR_STAT register. Reset value: 0x0" "0,1" line.long 0x1C "IC_CLR_ACTIVITY,Clear ACTIVITY Interrupt Register" hexmask.long 0x1C 1.--31. 1. "RSVD_IC_CLR_ACTIVITY,IC_CLR_ACTIVITY Reserved bits - Read Only" newline bitfld.long 0x1C 0. "CLR_ACTIVITY,Reading this register clears the ACTIVITY interrupt if the I2C is not active anymore. If the I2C module is still active on the bus the ACTIVITY interrupt bit continues to be set. It is automatically cleared by hardware if the module is.." "0,1" line.long 0x20 "IC_CLR_STOP_DET,Clear STOP_DET Interrupt Register" hexmask.long 0x20 1.--31. 1. "RSVD_IC_CLR_STOP_DET,IC_CLR_STOP_DET Reserved bits - Read Only" newline bitfld.long 0x20 0. "CLR_STOP_DET,Read this register to clear the STOP_DET interrupt (bit 9) of the IC_RAW_INTR_STAT register. Reset value: 0x0" "0,1" line.long 0x24 "IC_CLR_START_DET,Clear START_DET Interrupt Register" hexmask.long 0x24 1.--31. 1. "RSVD_IC_CLR_START_DET,IC_CLR_START_DET Reserved bits - Read Only" newline bitfld.long 0x24 0. "CLR_START_DET,Read this register to clear the START_DET interrupt (bit 10) of the IC_RAW_INTR_STAT register. Reset value: 0x0" "0,1" line.long 0x28 "IC_CLR_GEN_CALL,Clear GEN_CALL Interrupt Register" hexmask.long 0x28 1.--31. 1. "RSVD_IC_CLR_GEN_CALL,IC_CLR_GEN_CALL Reserved bits - Read Only" newline bitfld.long 0x28 0. "CLR_GEN_CALL,Read this register to clear the GEN_CALL interrupt (bit 11) of IC_RAW_INTR_STAT register. Reset value: 0x0" "0,1" group.long 0x6C++0x3 line.long 0x0 "IC_ENABLE,I2C Enable Register" hexmask.long.word 0x0 19.--31. 1. "RSVD_IC_ENABLE_2,IC_ENABLE Reserved bits - Read Only" newline rbitfld.long 0x0 18. "RSVD_SMBUS_ALERT_EN,SMBUS_ALERT_EN Register field Reserved bits - Read Only" "0,1" newline rbitfld.long 0x0 17. "RSVD_SMBUS_SUSPEND_EN,SMBUS_SUSPEND_EN Register field Reserved bits - Read Only" "0,1" newline bitfld.long 0x0 16. "SMBUS_CLK_RESET,This bit is used in SMBus Host mode to initiate the SMBus Master Clock Reset. This bit should be enabled only when Master is in idle. Whenever this bit is enabled the SMBCLK is held low for the IC_SCL_STUCK_TIMEOUT ic_clk cycles to reset.." "Master will not initates SMBUS Clock Reset..,Master initates the SMBUS Clock Reset Mechanism" newline hexmask.long.word 0x0 4.--15. 1. "RSVD_IC_ENABLE_1,RSVD_IC_ENABLE_1 Reserved bits - Read Only" newline bitfld.long 0x0 3. "SDA_STUCK_RECOVERY_ENABLE,If SDA is stuck at low indicated through the TX_ABORT interrupt (IC_TX_ABRT_SOURCE[17]) then this bit is used as a control knob to initiate the SDA Recovery Mechanism (that is send at most 9 SCL clocks and STOP to release the.." "Master disabled the SDA stuck at low recovery..,Master initates the SDA stuck at low recovery.." newline bitfld.long 0x0 2. "TX_CMD_BLOCK,In Master mode: - 1'b1: Blocks the transmission of data on I2C bus even if Tx FIFO has data to transmit. - 1'b0: The transmission of data starts on I2C bus automatically as soon as the first data is available in the Tx FIFO. Note: To block.." "Tx Command execution not blocked,Tx Command execution blocked" newline bitfld.long 0x0 1. "ABORT,When set the controller initiates the transfer abort. - 0: ABORT not initiated or ABORT done - 1: ABORT operation in progress The software can abort the I2C transfer in master mode by setting this bit. The software can set this bit only when.." "ABORT operation not in progress,ABORT operation in progress" newline bitfld.long 0x0 0. "ENABLE,Controls whether the DW_apb_i2c is enabled. - 0: Disables DW_apb_i2c (TX and RX FIFOs are held in an erased state) - 1: Enables DW_apb_i2c Software can disable DW_apb_i2c while it is active. However it is important that care be taken to ensure.." "I2C is disabled,I2C is enabled" rgroup.long 0x70++0xB line.long 0x0 "IC_STATUS,I2C Status Register This is a read-only register used to indicate the current transfer status and FIFO status. The status register may be read at any time. None of the bits in this register request an interrupt. When the I2C is disabled by.." hexmask.long.word 0x0 21.--31. 1. "RSVD_IC_STATUS_2,IC_STATUS Reserved bits - Read Only" newline bitfld.long 0x0 20. "RSVD_SMBUS_ALERT_STATUS,SMBUS_ALERT_STATUS Register field Reserved bits - Read Only" "0,1" newline bitfld.long 0x0 19. "RSVD_SMBUS_SUSPEND_STATUS,SMBUS_SUSPEND_STATUS Register field Reserved bits - Read Only" "0,1" newline bitfld.long 0x0 18. "SMBUS_SLAVE_ADDR_RESOLVED,This bit indicates whether the slave address (ic_sar) is resolved by the ARP Master. Reset value: 0x0. 0x1: SMBUS Slave Address is Resolved. 0x0: SMBUS Slave Address is not Resolved." "SMBUS Slave Address is not Resolved,SMBUS Slave Address is Resolved" newline bitfld.long 0x0 17. "SMBUS_SLAVE_ADDR_VALID,This bit indicates whether the slave address (ic_sar) is valid or not. Reset value: IC_PERSISTANT_SLV_ADDR_DEFAULT 0x1: SMBUS Slave Address is Valid. 0x0: SMBUS SLave Address is not valid." "SMBUS SLave Address is not valid,SMBUS Slave Address is Valid" newline bitfld.long 0x0 16. "SMBUS_QUICK_CMD_BIT,This bit indicates the R/W bit of the Quick command received. This bit will be cleared after the user has read this bit. Reset value: 0x0. 0x1: SMBUS QUICK CMD Read/write is set to 1. 0x0: SMBUS QUICK CMD Read/write is set to 0." "SMBUS QUICK CMD Read/write is set to 0,SMBUS QUICK CMD Read/write is set to 1" newline hexmask.long.byte 0x0 12.--15. 1. "RSVD_IC_STATUS_1,RSVD_IC_STATUS_1 Reserved bits - Read Only" newline bitfld.long 0x0 11. "SDA_STUCK_NOT_RECOVERED,This bit indicates that SDA stuck at low is not recovered after the recovery mechanism. In Slave mode this register bit is not applicable. Reset value: 0x0. 0x1: SDA Stuck at low is recovered after recovery mechanism. 0x0: SDA.." "SDA Stuck at low is not recovered after recovery..,SDA Stuck at low is recovered after recovery.." newline bitfld.long 0x0 10. "RSVD_SLV_HOLD_RX_FIFO_FULL,SLV_HOLD_RX_FIFO_FULL Register field Reserved bits - Read Only" "0,1" newline bitfld.long 0x0 9. "RSVD_SLV_HOLD_TX_FIFO_EMPTY,SLV_HOLD_TX_FIFO_EMPTY Regsiter field Reserved bits - Read Only" "0,1" newline bitfld.long 0x0 8. "RSVD_MST_HOLD_RX_FIFO_FULL,MST_HOLD_RX_FIFO_FULL Register field Reserved bits - Read Only" "0,1" newline bitfld.long 0x0 7. "RSVD_MST_HOLD_TX_FIFO_EMPTY,MST_HOLD_TX_FIFO_EMPTY Register field Reserved bits - Read Only" "0,1" newline bitfld.long 0x0 6. "SLV_ACTIVITY,Slave FSM Activity Status. When the Slave Finite State Machine (FSM) is not in the IDLE state this bit is set. - 0: Slave FSM is in IDLE state so the Slave part of DW_apb_i2c is not Active - 1: Slave FSM is not in IDLE state so the Slave.." "Slave is idle,Slave not idle" newline bitfld.long 0x0 5. "MST_ACTIVITY,Master FSM Activity Status. When the Master Finite State Machine (FSM) is not in the IDLE state this bit is set. - 0: Master FSM is in IDLE state so the Master part of DW_apb_i2c is not Active - 1: Master FSM is not in IDLE state so the.." "Master is idle,Master not idle" newline bitfld.long 0x0 4. "RFF,Receive FIFO Completely Full. When the receive FIFO is completely full this bit is set. When the receive FIFO contains one or more empty location this bit is cleared. - 0: Receive FIFO is not full - 1: Receive FIFO is full Reset value: 0x0 0x1: Rx.." "Rx FIFO not full,Rx FIFO is full" newline bitfld.long 0x0 3. "RFNE,Receive FIFO Not Empty. This bit is set when the receive FIFO contains one or more entries; it is cleared when the receive FIFO is empty. - 0: Receive FIFO is empty - 1: Receive FIFO is not empty Reset value: 0x0 0x0: Rx FIFO is empty 0x1: Rx FIFO.." "Rx FIFO is empty,Rx FIFO not empty" newline bitfld.long 0x0 2. "TFE,Transmit FIFO Completely Empty. When the transmit FIFO is completely empty this bit is set. When it contains one or more valid entries this bit is cleared. This bit field does not request an interrupt. - 0: Transmit FIFO is not empty - 1: Transmit.." "Tx FIFO not empty,Tx FIFO is empty" newline bitfld.long 0x0 1. "TFNF,Transmit FIFO Not Full. Set when the transmit FIFO contains one or more empty locations and is cleared when the FIFO is full. - 0: Transmit FIFO is full - 1: Transmit FIFO is not full Reset value: 0x1 0x0: Tx FIFO is full 0x1: Tx FIFO not full" "Tx FIFO is full,Tx FIFO not full" newline bitfld.long 0x0 0. "ACTIVITY,I2C Activity Status. Reset value: 0x0 0x1: I2C is active 0x0: I2C is idle" "I2C is idle,I2C is active" line.long 0x4 "IC_TXFLR,I2C Transmit FIFO Level Register This register contains the number of valid data entries in the transmit FIFO buffer. It is cleared whenever: - The I2C is disabled - There is a transmit abort - that is. TX_ABRT bit is set in the IC_RAW_INTR_STAT.." hexmask.long 0x4 5.--31. 1. "RSVD_TXFLR,TXFLR Register field Reserved bits - Read Only" newline hexmask.long.byte 0x4 0.--4. 1. "TXFLR,Transmit FIFO Level. Contains the number of valid data entries in the transmit FIFO. Reset value: 0x0" line.long 0x8 "IC_RXFLR,I2C Receive FIFO Level Register This register contains the number of valid data entries in the receive FIFO buffer. It is cleared whenever: - The I2C is disabled - Whenever there is a transmit abort caused by any of the events tracked in.." hexmask.long 0x8 5.--31. 1. "RSVD_RXFLR,RXFLR Reserved bits - Read Only" newline hexmask.long.byte 0x8 0.--4. 1. "RXFLR,Receive FIFO Level. Contains the number of valid data entries in the receive FIFO. Reset value: 0x0" group.long 0x7C++0x3 line.long 0x0 "IC_SDA_HOLD,I2C SDA Hold Time Length Register The bits [15:0] of this register are used to control the hold time of SDA during transmit in both slave and master mode (after SCL goes from HIGH to LOW). The bits [23:16] of this register are used to extend.." hexmask.long.byte 0x0 24.--31. 1. "RSVD_IC_SDA_HOLD,IC_SDA_HOLD Reserved bits - Read Only" newline hexmask.long.byte 0x0 16.--23. 1. "IC_SDA_RX_HOLD,Sets the required SDA hold time in units of ic_clk period when DW_apb_i2c acts as a receiver. Reset value: IC_DEFAULT_SDA_HOLD[23:16]." newline hexmask.long.word 0x0 0.--15. 1. "IC_SDA_TX_HOLD,Sets the required SDA hold time in units of ic_clk period when DW_apb_i2c acts as a transmitter. Reset value: IC_DEFAULT_SDA_HOLD[15:0]." rgroup.long 0x80++0x3 line.long 0x0 "IC_TX_ABRT_SOURCE,I2C Transmit Abort Source Register This register has 32 bits that indicate the source of the TX_ABRT bit. Except for Bit 9. this register is cleared whenever the IC_CLR_TX_ABRT register or the IC_CLR_INTR register is read. To clear Bit.." hexmask.long.word 0x0 23.--31. 1. "TX_FLUSH_CNT,This field indicates the number of Tx FIFO Data Commands which are flushed due to TX_ABRT interrupt. It is cleared whenever I2C is disabled. Reset value: 0x0 Role of DW_apb_i2c: Master-Transmitter or Slave-Transmitter" newline bitfld.long 0x0 21.--22. "RSVD_IC_TX_ABRT_SOURCE,IC_TX_ABRT_SOURCE Reserved bits - Read Only" "0,1,2,3" newline bitfld.long 0x0 18.--20. "RSVD_ABRT_DEVICE_WRITE,ABRT_DEVICE_WRITE Register field Reserved bits - Read Only" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 17. "ABRT_SDA_STUCK_AT_LOW,This is a master-mode-only bit. Master detects the SDA Stuck at low for the IC_SDA_STUCK_AT_LOW_TIMEOUT value of ic_clks. Reset value: 0x0 Role of DW_apb_i2c: Master 0x1: This abort is generated because of Sda stuck at low for.." "This abort is not generated,This abort is generated because of Sda stuck at.." newline bitfld.long 0x0 16. "ABRT_USER_ABRT,This is a master-mode-only bit. Master has detected the transfer abort (IC_ENABLE[1]) Reset value: 0x0 Role of DW_apb_i2c: Master-Transmitter 0x1: Transfer abort detected by master 0x0: Transfer abort detected by master- scenario not present" "Transfer abort detected by master,Transfer abort detected by master" newline bitfld.long 0x0 15. "ABRT_SLVRD_INTX,1: When the processor side responds to a slave mode request for data to be transmitted to a remote master and user writes a 1 in CMD (bit 8) of IC_DATA_CMD register. Reset value: 0x0 Role of DW_apb_i2c: Slave-Transmitter 0x1: Slave trying.." "Slave trying to transmit to remote master in..,Slave trying to transmit to remote master in.." newline bitfld.long 0x0 14. "ABRT_SLV_ARBLOST,This field indicates that a Slave has lost the bus while transmitting data to a remote master. IC_TX_ABRT_SOURCE[12] is set at the same time. Note: Even though the slave never 'owns' the bus something could go wrong on the bus. This is.." "Slave lost arbitration to remote master,Slave lost arbitration to remote master" newline bitfld.long 0x0 13. "ABRT_SLVFLUSH_TXFIFO,This field specifies that the Slave has received a read command and some data exists in the TX FIFO so the slave issues a TX_ABRT interrupt to flush old data in TX FIFO. Reset value: 0x0 Role of DW_apb_i2c: Slave-Transmitter 0x1:.." "Slave flushes existing data in TX-FIFO upon..,Slave flushes existing data in TX-FIFO upon.." newline bitfld.long 0x0 12. "ARB_LOST,This field specifies that the Master has lost arbitration or if IC_TX_ABRT_SOURCE[14] is also set then the slave transmitter has lost arbitration. Reset value: 0x0 Role of DW_apb_i2c: Master-Transmitter or Slave-Transmitter 0x1: Master or.." "Master or Slave-Transmitter lost arbitration,Master or Slave-Transmitter lost arbitration" newline bitfld.long 0x0 11. "ABRT_MASTER_DIS,This field indicates that the User tries to initiate a Master operation with the Master mode disabled. Reset value: 0x0 Role of DW_apb_i2c: Master-Transmitter or Master-Receiver 0x1: User intitating master operation when MASTER disabled.." "User initiating master operation when MASTER..,User intitating master operation when MASTER.." newline bitfld.long 0x0 10. "ABRT_10B_RD_NORSTRT,This field indicates that the restart is disabled (IC_RESTART_EN bit (IC_CON[5]) =0) and the master sends a read command in 10-bit addressing mode. Reset value: 0x0 Role of DW_apb_i2c: Master-Receiver 0x1: Master trying to read in.." "Master not trying to read in 10Bit addressing..,Master trying to read in 10Bit addressing mode.." newline bitfld.long 0x0 9. "ABRT_SBYTE_NORSTRT,To clear Bit 9 the source of the ABRT_SBYTE_NORSTRT must be fixed first; restart must be enabled (IC_CON[5]=1) the SPECIAL bit must be cleared (IC_TAR[11]) or the GC_OR_START bit must be cleared (IC_TAR[10]). Once the source of the.." "User trying to send START byte when RESTART..,User trying to send START byte when RESTART.." newline bitfld.long 0x0 8. "ABRT_HS_NORSTRT,This field indicates that the restart is disabled (IC_RESTART_EN bit (IC_CON[5]) =0) and the user is trying to use the master to transfer data in High Speed mode. Reset value: 0x0 Role of DW_apb_i2c: Master-Transmitter or Master-Receiver.." "User trying to switch Master to HS mode when..,User trying to switch Master to HS mode when.." newline bitfld.long 0x0 7. "ABRT_SBYTE_ACKDET,This field indicates that the Master has sent a START Byte and the START Byte was acknowledged (wrong behavior). Reset value: 0x0 Role of DW_apb_i2c: Master 0x1: ACK detected for START byte 0x0: ACK detected for START byte- scenario not.." "ACK detected for START byte,ACK detected for START byte" newline bitfld.long 0x0 6. "ABRT_HS_ACKDET,This field indicates that the Master is in High Speed mode and the High Speed Master code was acknowledged (wrong behavior). Reset value: 0x0 Role of DW_apb_i2c: Master 0x1: HS Master code ACKed in HS Mode 0x0: HS Master code ACKed in HS.." "HS Master code ACKed in HS Mode,HS Master code ACKed in HS Mode" newline bitfld.long 0x0 5. "ABRT_GCALL_READ,This field indicates that DW_apb_i2c in the master mode has sent a General Call but the user programmed the byte following the General Call to be a read from the bus (IC_DATA_CMD[9] is set to 1). Reset value: 0x0 Role of DW_apb_i2c:.." "GCALL is followed by read from bus-scenario not..,GCALL is followed by read from bus" newline bitfld.long 0x0 4. "ABRT_GCALL_NOACK,This field indicates that DW_apb_i2c in master mode has sent a General Call and no slave on the bus acknowledged the General Call. Reset value: 0x0 Role of DW_apb_i2c: Master-Transmitter 0x1: GCALL not ACKed by any slave 0x0: GCALL not.." "GCALL not ACKed by any slave-scenario not present,GCALL not ACKed by any slave" newline bitfld.long 0x0 3. "ABRT_TXDATA_NOACK,This field indicates the master-mode only bit. When the master receives an acknowledgement for the address but when it sends data byte(s) following the address it did not receive an acknowledge from the remote slave(s). Reset value:.." "Transmitted data non-ACKed by addressed..,Transmitted data not ACKed by addressed slave" newline bitfld.long 0x0 2. "ABRT_10ADDR2_NOACK,This field indicates that the Master is in 10-bit address mode and that the second address byte of the 10-bit address was not acknowledged by any slave. Reset value: 0x0 Role of DW_apb_i2c: Master-Transmitter or Master-Receiver 0x1:.." "This abort is not generated,Byte 2 of 10Bit Address not ACKed by any slave" newline bitfld.long 0x0 1. "ABRT_10ADDR1_NOACK,This field indicates that the Master is in 10-bit address mode and the first 10-bit address byte was not acknowledged by any slave. Reset value: 0x0 Role of DW_apb_i2c: Master-Transmitter or Master-Receiver 0x1: Byte 1 of 10Bit Address.." "This abort is not generated,Byte 1 of 10Bit Address not ACKed by any slave" newline bitfld.long 0x0 0. "ABRT_7B_ADDR_NOACK,This field indicates that the Master is in 7-bit addressing mode and the address sent was not acknowledged by any slave. Reset value: 0x0 Role of DW_apb_i2c: Master-Transmitter or Master-Receiver 0x1: This abort is generated because of.." "This abort is not generated,This abort is generated because of NOACK for.." group.long 0x88++0x13 line.long 0x0 "IC_DMA_CR,DMA Control Register This register is only valid when DW_apb_i2c is configured with a set of DMA Controller interface signals (IC_HAS_DMA = 1). When DW_apb_i2c is not configured for DMA operation. this register does not exist and writing to the.." hexmask.long 0x0 2.--31. 1. "RSVD_IC_DMA_CR_2_31,RSVD_IC_DMA_CR_2_31 Reserved bits - Read Only" newline bitfld.long 0x0 1. "TDMAE,Transmit DMA Enable. This bit enables/disables the transmit FIFO DMA channel. Reset value: 0x0 0x0: transmit FIFO DMA channel disabled 0x1: Transmit FIFO DMA channel enabled" "transmit FIFO DMA channel disabled,Transmit FIFO DMA channel enabled" newline bitfld.long 0x0 0. "RDMAE,Receive DMA Enable. This bit enables/disables the receive FIFO DMA channel. Reset value: 0x0 0x0: Receive FIFO DMA channel disabled 0x1: Receive FIFO DMA channel enabled" "Receive FIFO DMA channel disabled,Receive FIFO DMA channel enabled" line.long 0x4 "IC_DMA_TDLR,DMA Transmit Data Level Register This register is only valid when the DW_apb_i2c is configured with a set of DMA interface signals (IC_HAS_DMA = 1). When DW_apb_i2c is not configured for DMA operation. this register does not exist; writing to.." hexmask.long 0x4 4.--31. 1. "RSVD_DMA_TDLR,DMA_TDLR Reserved bits - Read Only" newline hexmask.long.byte 0x4 0.--3. 1. "DMATDL,Transmit Data Level. This bit field controls the level at which a DMA request is made by the transmit logic. It is equal to the watermark level; that is the dma_tx_req signal is generated when the number of valid data entries in the transmit FIFO.." line.long 0x8 "IC_DMA_RDLR,I2C Receive Data Level Register This register is only valid when DW_apb_i2c is configured with a set of DMA interface signals (IC_HAS_DMA = 1). When DW_apb_i2c is not configured for DMA operation. this register does not exist; writing to its.." hexmask.long 0x8 4.--31. 1. "RSVD_DMA_RDLR,DMA_RDLR Reserved bits - Read Only" newline hexmask.long.byte 0x8 0.--3. 1. "DMARDL,Receive Data Level. This bit field controls the level at which a DMA request is made by the receive logic. The watermark level = DMARDL+1; that is dma_rx_req is generated when the number of valid data entries in the receive FIFO is equal to or.." line.long 0xC "IC_SDA_SETUP,I2C SDA Setup Register This register controls the amount of time delay (in terms of number of ic_clk clock periods) introduced in the rising edge of SCL - relative to SDA changing - when DW_apb_i2c services a read request in a.." hexmask.long.tbyte 0xC 8.--31. 1. "RSVD_IC_SDA_SETUP,IC_SDA_SETUP Reserved bits - Read Only" newline hexmask.long.byte 0xC 0.--7. 1. "SDA_SETUP,SDA Setup. It is recommended that if the required delay is 1000ns then for an ic_clk frequency of 10 MHz IC_SDA_SETUP should be programmed to a value of 11. IC_SDA_SETUP must be programmed with a minimum value of 2. Reset value: 0x64 but can.." line.long 0x10 "IC_ACK_GENERAL_CALL,I2C ACK General Call Register The register controls whether DW_apb_i2c responds with a ACK or NACK when it receives an I2C General Call address. This register is applicable only when the DW_apb_i2c is in slave mode." hexmask.long 0x10 1.--31. 1. "RSVD_IC_ACK_GEN_1_31,RSVD_IC_ACK_GEN_1_31 Reserved bits - Read Only" newline bitfld.long 0x10 0. "ACK_GEN_CALL,ACK General Call. When set to 1 DW_apb_i2c responds with a ACK (by asserting ic_data_oe) when it receives a General Call. Otherwise DW_apb_i2c responds with a NACK (by negating ic_data_oe). Reset value: 0x1 but can be hardcoded by setting.." "Generate NACK for General Call,Generate ACK for a General Call" rgroup.long 0x9C++0x3 line.long 0x0 "IC_ENABLE_STATUS,I2C Enable Status Register The register is used to report the DW_apb_i2c hardware status when the IC_ENABLE[0] register is set from 1 to 0; that is. when DW_apb_i2c is disabled. If IC_ENABLE[0] has been set to 1. bits 2:1 are forced to.." hexmask.long 0x0 3.--31. 1. "RSVD_IC_ENABLE_STATUS,IC_ENABLE_STATUS Reserved bits - Read Only" newline bitfld.long 0x0 2. "SLV_RX_DATA_LOST,Slave Received Data Lost. This bit indicates if a Slave-Receiver operation has been aborted with at least one data byte received from an I2C transfer due to the setting bit 0 of IC_ENABLE from 1 to 0. When read as 1 DW_apb_i2c is deemed.." "Slave RX Data is not lost,Slave RX Data is lost" newline bitfld.long 0x0 1. "SLV_DISABLED_WHILE_BUSY,Slave Disabled While Busy (Transmit Receive). This bit indicates if a potential or active Slave operation has been aborted due to the setting bit 0 of the IC_ENABLE register from 1 to 0. This bit is set when the CPU writes a 0 to.." "Slave is disabled when it is idle,Slave is disabled when it is active" newline bitfld.long 0x0 0. "IC_EN,ic_en Status. This bit always reflects the value driven on the output port ic_en. - When read as 1 DW_apb_i2c is deemed to be in an enabled state. - When read as 0 DW_apb_i2c is deemed completely inactive. Note: The CPU can safely read this bit.." "I2C disabled,I2C enabled" group.long 0xA0++0x3 line.long 0x0 "IC_FS_SPKLEN,I2C SS. FS or FM+ spike suppression limit This register is used to store the duration. measured in ic_clk cycles. of the longest spike that is filtered out by the spike suppression logic w hen the component is operating in SS. FS or FM+.." hexmask.long.tbyte 0x0 8.--31. 1. "RSVD_IC_FS_SPKLEN,IC_FS_SPKLEN Reserved bits - Read Only" newline hexmask.long.byte 0x0 0.--7. 1. "IC_FS_SPKLEN,This register must be set before any I2C bus transaction can take place to ensure stable operation. This register sets the duration measured in ic_clk cycles of the longest spike in the SCL or SDA lines that will be filtered out by the.." rgroup.long 0xA8++0x3 line.long 0x0 "IC_CLR_RESTART_DET,Clear RESTART_DET Interrupt Register" hexmask.long 0x0 1.--31. 1. "RSVD_IC_CLR_RESTART_DET,IC_CLR_RESTART_DET Reserved bits - Read Only" newline bitfld.long 0x0 0. "CLR_RESTART_DET,Read this register to clear the RESTART_DET interrupt (bit 12) of IC_RAW_INTR_STAT register. Reset value: 0x0" "0,1" group.long 0xAC++0x7 line.long 0x0 "IC_SCL_STUCK_AT_LOW_TIMEOUT,I2C SCL Stuck at Low Timeout This register is used to store the duration. measured in ic_clk cycles. used to Generate an Interrupt (SCL_STUCK_AT_LOW) if SCL is held low for the IC_SCL_STUCK_LOW_TIMEOUT duration." hexmask.long 0x0 0.--31. 1. "IC_SCL_STUCK_LOW_TIMEOUT,DW_apb_i2c generate the interrupt to indicate SCL stuck at low (SCL_STUCK_AT_LOW) if it detects the SCL stuck at low for the IC_SCL_STUCK_LOW_TIMEOUT in units of ic_clk period. This register can be written only when the I2C.." line.long 0x4 "IC_SDA_STUCK_AT_LOW_TIMEOUT,I2C SDA Stuck at Low Timeout This register is used to store the duration. measured in ic_clk cycles. used to Recover the Data (SDA) line through sending SCL pulses if SDA is held low for the mentioned duration." hexmask.long 0x4 0.--31. 1. "IC_SDA_STUCK_LOW_TIMEOUT,DW_apb_i2c initiates the recovery of SDA line through enabling the SDA_STUCK_RECOVERY_EN (IC_ENABLE[3]) register bit if it detects the SDA stuck at low for the IC_SDA_STUCK_LOW_TIMEOUT in units of ic_clk period. Reset value:.." rgroup.long 0xB4++0x3 line.long 0x0 "IC_CLR_SCL_STUCK_DET,Clear SCL Stuck at Low Detect Interrupt Register" hexmask.long 0x0 1.--31. 1. "RSVD_CLR_SCL_STUCK_DET,CLR_SCL_STUCK_DET Reserved bits - Read Only" newline bitfld.long 0x0 0. "CLR_SCL_STUCK_DET,Read this register to clear the SCL_STUCT_AT_LOW interrupt (bit 15) of the IC_RAW_INTR_STAT register. Reset value: 0x0" "0,1" group.long 0xBC++0xB line.long 0x0 "IC_SMBUS_CLK_LOW_SEXT,SMBus Slave Clock Extend Timeout Register This Register contains the Timeout value used to determine the Slave Clock Extend Timeout in one transfer (from START to STOP). This Register can be written only when the DW_apb_i2c is.." hexmask.long 0x0 0.--31. 1. "SMBUS_CLK_LOW_SEXT_TIMEOUT,This field is used to detect the Slave Clock Extend timeout (tLOW:SEXT) in master mode extended by the slave device in one message from the initial START to the STOP. The values in this register are in units of ic_clk period." line.long 0x4 "IC_SMBUS_CLK_LOW_MEXT,SMBus Master Clock Extend Timeout Register This Register contains the Timeout value used to determine the Master Clock Extend Timeout in one byte of transfer. This Register can be written only when the DW_apb_i2c is disabled. which.." hexmask.long 0x4 0.--31. 1. "SMBUS_CLK_LOW_MEXT_TIMEOUT,This field is used to detect the Master extend SMBus clock (SCLK) timeout defined from START-to-ACK ACK-to-ACK or ACK-to-STOP in Master mode. The values in this register are in units of ic_clk period. Reset value:.." line.long 0x8 "IC_SMBUS_THIGH_MAX_IDLE_COUNT,SMBus Master THigh MAX Bus-idle count Register This register programs the Bus-idle time period used when a master has been dynamically added to the bus or when a master has generated a clock reset on the bus. This register.." hexmask.long.word 0x8 16.--31. 1. "RSVD_SMBUS_THIGH_MAX_BUS_IDLE_CNT,SMBUS_THIGH_MAX_BUS_IDLE_CNT Reserved bits - Read Only" newline hexmask.long.word 0x8 0.--15. 1. "SMBUS_THIGH_MAX_BUS_IDLE_CNT,This field is used to set the required Bus-Idle time period used when a master has been dynamically added to the bus and may not have detected a state transition on the SMBCLK or SMBDAT lines. In this case the master must.." rgroup.long 0xC8++0x3 line.long 0x0 "IC_SMBUS_INTR_STAT,SMBUS Interrupt Status Register Each bit in this register has a corresponding mask bit in the IC_SMBUS_INTR_MASK register. These bits are cleared by writing the matching SMBus interrupt clear register(IC_CLR_SMBUS_INTR) bits. The.." hexmask.long.tbyte 0x0 11.--31. 1. "RSVD_IC_SMBUS_INTR_STAT,IC_SMBUS_INTR_STAT Reserved bits - Read Only" newline bitfld.long 0x0 10. "RSVD_R_SMBUS_ALERT_DET,R_SMBUS_ALERT_DET Register field Reserved bits - Read Only" "0,1" newline bitfld.long 0x0 9. "RSVD_R_SMBUS_SUSPEND_DET,R_SMBUS_SUSPEND_DET Register field Reserved bits - Read Only" "0,1" newline bitfld.long 0x0 8. "R_SLV_RX_PEC_NACK,See IC_SMBUS_INTR_RAW_STATUS for a detailed description of R_SLV_RX_PEC_NACK bit. Reset value: 0x0 0x1: SLV_RX_PEC_NACK interrupt is active 0x0: SLV_RX_PEC_NACK interrupt is inactive" "SLV_RX_PEC_NACK interrupt is inactive,SLV_RX_PEC_NACK interrupt is active" newline bitfld.long 0x0 7. "R_ARP_ASSGN_ADDR_CMD_DET,See IC_SMBUS_INTR_RAW_STATUS for a detailed description of R_ARP_ASSGN_ADDR_CMD_DET bit. Reset value: 0x0 0x1: ARP_ASSGN_ADDR_CMD_DET interrupt is active 0x0: ARP_ASSGN_ADDR_CMD_DET interrupt is inactive" "ARP_ASSGN_ADDR_CMD_DET interrupt is inactive,ARP_ASSGN_ADDR_CMD_DET interrupt is active" newline bitfld.long 0x0 6. "R_ARP_GET_UDID_CMD_DET,See IC_SMBUS_INTR_RAW_STATUS for a detailed description of R_ARP_GET_UDID_CMD_DET bit. Reset value: 0x0 0x1: ARP_GET_UDID_CMD_DET interrupt is active 0x0: ARP_GET_UDID_CMD_DET interrupt is inactive" "ARP_GET_UDID_CMD_DET interrupt is inactive,ARP_GET_UDID_CMD_DET interrupt is active" newline bitfld.long 0x0 5. "R_ARP_RST_CMD_DET,See IC_SMBUS_INTR_RAW_STATUS for a detailed description of R_ARP_RST_CMD_DET bit. Reset value: 0x0 0x1: ARP_RST_CMD_DET interrupt is active 0x0: ARP_RST_CMD_DET interrupt is inactive" "ARP_RST_CMD_DET interrupt is inactive,ARP_RST_CMD_DET interrupt is active" newline bitfld.long 0x0 4. "R_ARP_PREPARE_CMD_DET,See IC_SMBUS_INTR_RAW_STATUS for a detailed description of R_ARP_PREPARE_CMD_DET bit. Reset value: 0x0 0x1: ARP_PREPARE_CMD_DET interrupt is active 0x0: ARP_PREPARE_CMD_DET interrupt is inactive" "ARP_PREPARE_CMD_DET interrupt is inactive,ARP_PREPARE_CMD_DET interrupt is active" newline bitfld.long 0x0 3. "R_HOST_NOTIFY_MST_DET,See IC_SMBUS_INTR_RAW_STATUS for a detailed description of R_HOST_NOTIFY_MST_DET bit. Reset value: 0x0 0x1: HOST_NOTIFY_MST_DET interrupt is active 0x0: HOST_NOTIFY_MST_DET interrupt is inactive" "HOST_NOTIFY_MST_DET interrupt is inactive,HOST_NOTIFY_MST_DET interrupt is active" newline bitfld.long 0x0 2. "R_QUICK_CMD_DET,See IC_SMBUS_INTR_RAW_STATUS for a detailed description of R_QUICK_CMD_DET bit. Reset value: 0x0 0x1: QUICK_CMD_DET interrupt is active 0x0: QUICK_CMD_DET interrupt is inactive" "QUICK_CMD_DET interrupt is inactive,QUICK_CMD_DET interrupt is active" newline bitfld.long 0x0 1. "R_MST_CLOCK_EXTND_TIMEOUT,See IC_SMBUS_INTR_RAW_STATUS for a detailed description of R_MST_CLOCK_EXTND_TIMEOUT bit. Reset value: 0x0 0x1: MST_CLOCK_EXTND_TIMEOUT interrupt is active 0x0: MST_CLOCK_EXTND_TIMEOUT interrupt is inactive" "MST_CLOCK_EXTND_TIMEOUT interrupt is inactive,MST_CLOCK_EXTND_TIMEOUT interrupt is active" newline bitfld.long 0x0 0. "R_SLV_CLOCK_EXTND_TIMEOUT,See IC_SMBUS_INTR_RAW_STATUS for a detailed description of R_SLV_CLOCK_EXTND_TIMEOUT bit. Reset value: 0x0 0x1: SLV_CLOCK_EXTND_TIMEOUT interrupt is active 0x0: SLV_CLOCK_EXTND_TIMEOUT interrupt is inactive" "SLV_CLOCK_EXTND_TIMEOUT interrupt is inactive,SLV_CLOCK_EXTND_TIMEOUT interrupt is active" group.long 0xCC++0x3 line.long 0x0 "IC_SMBUS_INTR_MASK,SMBus Interrupt Mask Register" hexmask.long.tbyte 0x0 11.--31. 1. "RSVD_IC_SMBUS_INTR_MASK,IC_SMBUS_INTR_MASK Reserved bits - Read Only" newline rbitfld.long 0x0 9.--10. "RSVD_IC_SMBUS_INTR_MASK_9_10,RSVD_IC_SMBUS_INTR_MASK_9_10 Register field Reserved bits." "0,1,2,3" newline bitfld.long 0x0 8. "M_SLV_RX_PEC_NACK,This bit masks the R_SLV_RX_PEC_NACK interrupt in IC_SMBUS_INTR_STAT register. Reset value: 0x1 0x1: SLV_RX_PEC_NACK interrupt is unmasked 0x0: SLV_RX_PEC_NACK interrupt is masked" "SLV_RX_PEC_NACK interrupt is masked,SLV_RX_PEC_NACK interrupt is unmasked" newline bitfld.long 0x0 7. "M_ARP_ASSGN_ADDR_CMD_DET,This bit masks the R_ARP_ASSGN_ADDR_CMD_DET interrupt in IC_SMBUS_INTR_STAT register. Reset value: 0x1 0x1: ARP_ASSGN_ADDR_CMD_DET interrupt is unmasked 0x0: ARP_ASSGN_ADDR_CMD_DET interrupt is masked" "ARP_ASSGN_ADDR_CMD_DET interrupt is masked,ARP_ASSGN_ADDR_CMD_DET interrupt is unmasked" newline bitfld.long 0x0 6. "M_ARP_GET_UDID_CMD_DET,This bit masks the R_ARP_GET_UDID_CMD_DET interrupt in IC_SMBUS_INTR_STAT register. Reset value: 0x1 0x1: ARP_GET_UDID_CMD_DET interrupt is unmasked 0x0: ARP_GET_UDID_CMD_DET interrupt is masked" "ARP_GET_UDID_CMD_DET interrupt is masked,ARP_GET_UDID_CMD_DET interrupt is unmasked" newline bitfld.long 0x0 5. "M_ARP_RST_CMD_DET,This bit masks the R_ARP_RST_CMD_DET interrupt in IC_SMBUS_INTR_STAT register. Reset value: 0x1 0x1: ARP_RST_CMD_DET interrupt is unmasked 0x0: ARP_RST_CMD_DET interrupt is masked" "ARP_RST_CMD_DET interrupt is masked,ARP_RST_CMD_DET interrupt is unmasked" newline bitfld.long 0x0 4. "M_ARP_PREPARE_CMD_DET,This bit masks the R_ARP_PREPARE_CMD_DET interrupt in IC_SMBUS_INTR_STAT register. Reset value: 0x1 0x1: ARP_PREPARE_CMD_DET interrupt is unmasked 0x0: ARP_PREPARE_CMD_DET interrupt is masked" "ARP_PREPARE_CMD_DET interrupt is masked,ARP_PREPARE_CMD_DET interrupt is unmasked" newline bitfld.long 0x0 3. "M_HOST_NOTIFY_MST_DET,This bit masks the R_HOST_NOTIFY_MST_DET interrupt in IC_SMBUS_INTR_STAT register. Reset value: 0x1 0x1: HOST_NOTIFY_MST_DET interrupt is unmasked 0x0: HOST_NOTIFY_MST_DET interrupt is masked" "HOST_NOTIFY_MST_DET interrupt is masked,HOST_NOTIFY_MST_DET interrupt is unmasked" newline bitfld.long 0x0 2. "M_QUICK_CMD_DET,This bit masks the R_QUICK_CMD_DET interrupt in IC_SMBUS_INTR_STAT register. Reset value: 0x1 0x1: QUICK_CMD_DET interrupt is unmasked 0x0: QUICK_CMD_DET interrupt is masked" "QUICK_CMD_DET interrupt is masked,QUICK_CMD_DET interrupt is unmasked" newline bitfld.long 0x0 1. "M_MST_CLOCK_EXTND_TIMEOUT,This bit masks the R_MST_CLOCK_EXTND_TIMEOUT interrupt in IC_SMBUS_INTR_STAT register. Reset value: 0x1 0x1: MST_CLOCK_EXTND_TIMEOUT interrupt is unmasked 0x0: MST_CLOCK_EXTND_TIMEOUT interrupt is masked" "MST_CLOCK_EXTND_TIMEOUT interrupt is masked,MST_CLOCK_EXTND_TIMEOUT interrupt is unmasked" newline bitfld.long 0x0 0. "M_SLV_CLOCK_EXTND_TIMEOUT,This bit masks the R_SLV_CLOCK_EXTND_TIMEOUT interrupt in IC_SMBUS_INTR_STAT register. Reset value: 0x1 0x1: SLV_CLOCK_EXTND_TIMEOUT interrupt is unmasked 0x0: SLV_CLOCK_EXTND_TIMEOUT interrupt is masked" "SLV_CLOCK_EXTND_TIMEOUT interrupt is masked,SLV_CLOCK_EXTND_TIMEOUT interrupt is unmasked" rgroup.long 0xD0++0x3 line.long 0x0 "IC_SMBUS_RAW_INTR_STAT,SMBus Raw Interrupt Status Register Unlike the IC_SMBUS_INTR_STAT register. these bits are not masked so they always show the true status of the DW_apb_i2c." hexmask.long.tbyte 0x0 11.--31. 1. "RSVD_IC_SMBUS_RAW_INTR_STAT,IC_SMBUS_RAW_INTR_STAT Reserved bits - Read Only" newline bitfld.long 0x0 10. "RSVD_SMBUS_ALERT_DET,SMBUS_ALERT_DET Register field Reserved bits - Read Only" "0,1" newline bitfld.long 0x0 9. "RSVD_SMBUS_SUSPEND_DET,SMBUS_SUSPEND_DET Register field Reserved bits - Read Only" "0,1" newline bitfld.long 0x0 8. "SLV_RX_PEC_NACK,Indicates whether a NACK has been sent due to PEC mismatch while working as ARP slave. Reset value: 0x0 0x1: SLV_RX_PEC_NACK interrupt is active 0x0: SLV_RX_PEC_NACK interrupt is inactive" "SLV_RX_PEC_NACK interrupt is inactive,SLV_RX_PEC_NACK interrupt is active" newline bitfld.long 0x0 7. "ARP_ASSGN_ADDR_CMD_DET,Indicates whether an Assign Address ARP command has been received. Reset value: 0x0 0x1: ARP_ASSGN_ADDR_CMD_DET interrupt is active 0x0: ARP_ASSGN_ADDR_CMD_DET interrupt is inactive" "ARP_ASSGN_ADDR_CMD_DET interrupt is inactive,ARP_ASSGN_ADDR_CMD_DET interrupt is active" newline bitfld.long 0x0 6. "ARP_GET_UDID_CMD_DET,Indicates whether a Get UDID ARP command has been received. Reset value: 0x0 0x1: ARP_GET_UDID_CMD_DET interrupt is active 0x0: ARP_GET_UDID_CMD_DET interrupt is inactive" "ARP_GET_UDID_CMD_DET interrupt is inactive,ARP_GET_UDID_CMD_DET interrupt is active" newline bitfld.long 0x0 5. "ARP_RST_CMD_DET,Indicates whether a General or Directed Reset ARP command has been received. Reset value: 0x0 0x1: ARP_RST_CMD_DET interrupt is active 0x0: ARP_RST_CMD_DET interrupt is inactive" "ARP_RST_CMD_DET interrupt is inactive,ARP_RST_CMD_DET interrupt is active" newline bitfld.long 0x0 4. "ARP_PREPARE_CMD_DET,Indicates whether a prepare to ARP command has been received. Reset value: 0x0 0x1: ARP_PREPARE_CMD_DET interrupt is active 0x0: ARP_PREPARE_CMD_DET interrupt is inactive" "ARP_PREPARE_CMD_DET interrupt is inactive,ARP_PREPARE_CMD_DET interrupt is active" newline bitfld.long 0x0 3. "HOST_NTFY_MST_DET,Indicates whether a Notify ARP Master ARP command has been received. Reset value: 0x0 0x1: HOST_NTFY_MST_DET interrupt is active 0x0: HOST_NTFY_MST_DET interrupt is inactive" "HOST_NTFY_MST_DET interrupt is inactive,HOST_NTFY_MST_DET interrupt is active" newline bitfld.long 0x0 2. "QUICK_CMD_DET,Indicates whether a Quick command has been received on the SMBus interface regardless of whether DW_apb_i2c is operating in slave or master mode. Enabled only when IC_SMBUS=1 is set to 1. Reset value: 0x0 0x1: Quick Command interrupt is.." "Quick Command interrupt is inactive,Quick Command interrupt is active" newline bitfld.long 0x0 1. "MST_CLOCK_EXTND_TIMEOUT,Indicates whether the Master device transaction (START-to-ACK ACK-to-ACK or ACK-to-STOP) from START to STOP exceeds IC_SMBUS_CLOCK_LOW_MEXT time with in each byte of message. This bit is enabled only when: - IC_SMBUS=1 -.." "Master Clock Extend Timeout interrupt is inactive,Master Clock Extend Timeout interrupt is active" newline bitfld.long 0x0 0. "SLV_CLOCK_EXTND_TIMEOUT,Indicates whether the transaction from Slave (i.e from START to STOP) exceeds IC_SMBUS_CLK_LOW_SEXT time. This bit is enabled only when: - IC_SMBUS=1 - IC_CON[0]=1 Reset value: 0x0 0x1: Slave Clock Extend Timeout interrupt is.." "Slave Clock Extend Timeout interrupt is inactive,Slave Clock Extend Timeout interrupt is active" wgroup.long 0xD4++0x3 line.long 0x0 "IC_CLR_SMBUS_INTR,SMBus Clear Interrupt Register" hexmask.long.tbyte 0x0 11.--31. 1. "RSVD_IC_CLR_SMBUS_INTR,IC_CLR_SMBUS_INTR Reserved bits - Read Only" newline bitfld.long 0x0 10. "RSVD_CLR_SMBUS_ALERT_DET,CLR_SMBUS_ALERT_DET Register field Reserved bits - Read Only" "0,1" newline bitfld.long 0x0 9. "RSVD_CLR_SMBUS_SUSPEND_DET,CLR_SMBUS_SUSPEND_DET Register field Reserved bits - Read Only" "0,1" newline bitfld.long 0x0 8. "CLR_SLV_RX_PEC_NACK,Write this register bit to clear the SLV_RX_PEC_NACK interrupt (bit 8) of the IC_SMBUS_RAW_INTR_STAT register. Reset value: 0x0" "0,1" newline bitfld.long 0x0 7. "CLR_ARP_ASSGN_ADDR_CMD_DET,Write this register bit to clear the ARP_ASSGN_ADDR_CMD_DET interrupt (bit 7) of the IC_SMBUS_RAW_INTR_STAT register. Reset value: 0x0" "0,1" newline bitfld.long 0x0 6. "CLR_ARP_GET_UDID_CMD_DET,Write this register bit to clear the ARP_GET_UDID_CMD_DET interrupt (bit 6) of the IC_SMBUS_RAW_INTR_STAT register. Reset value: 0x0" "0,1" newline bitfld.long 0x0 5. "CLR_ARP_RST_CMD_DET,Write this register bit to clear the ARP_RST_CMD_DET interrupt (bit 5) of the IC_SMBUS_RAW_INTR_STAT register. Reset value: 0x0" "0,1" newline bitfld.long 0x0 4. "CLR_ARP_PREPARE_CMD_DET,Write this register bit to clear the ARP_PREPARE_CMD_DET interrupt (bit 4) of the IC_SMBUS_RAW_INTR_STAT register. Reset value: 0x0" "0,1" newline bitfld.long 0x0 3. "CLR_HOST_NOTIFY_MST_DET,Write this register bit to clear the HOST_NOTIFY_MST_DET interrupt (bit 3) of the IC_SMBUS_RAW_INTR_STAT register. Reset value: 0x0" "0,1" newline bitfld.long 0x0 2. "CLR_QUICK_CMD_DET,Write this register bit to clear the QUICK_CMD_DET interrupt (bit 2) of the IC_SMBUS_RAW_INTR_STAT register. Reset value: 0x0" "0,1" newline bitfld.long 0x0 1. "CLR_MST_CLOCK_EXTND_TIMEOUT,Write this register bit to clear the MST_CLOCK_EXTND_TIMEOUT interrupt (bit 1) of the IC_SMBUS_RAW_INTR_STAT register. Reset value: 0x0" "0,1" newline bitfld.long 0x0 0. "CLR_SLV_CLOCK_EXTND_TIMEOUT,Write this register bit to clear the SLV_CLOCK_EXTND_TIMEOUT interrupt (bit 0) of the IC_SMBUS_RAW_INTR_STAT register. Reset value: 0x0" "0,1" group.long 0xDC++0x3 line.long 0x0 "IC_SMBUS_UDID_LSB,SMBUS ARP UDID LSB Register This Register can be written only when the DW_apb_i2c is disabled. which corresponds to IC_ENABLE[0] being set to 0. This register is present only if configuration parameter IC_SMBUS_ARP is set to 1. This.." hexmask.long 0x0 0.--31. 1. "SMBUS_UDID_LSB,This field is used to store the LSB 32 bit value of slave unique device identifier used in Address Resolution Protocol. Reset Value: IC_SMBUS_UDID_LSB_DEFAULT" rgroup.long 0xF4++0xB line.long 0x0 "IC_COMP_PARAM_1,Component Parameter Register 1 Note This is a constant read-only register that contains encoded information about the component's parameter settings. The reset value depends on coreConsultant parameter(s)." hexmask.long.byte 0x0 24.--31. 1. "RSVD_IC_COMP_PARAM_1,IC_COMP_PARAM_1 Reserved bits - Read Only" newline hexmask.long.byte 0x0 16.--23. 1. "TX_BUFFER_DEPTH,The value of this register is derived from the IC_TX_BUFFER_DEPTH coreConsultant parameter. - 0x00 = Reserved - 0x01 = 2 - 0x02 = 3 - ... - 0xFF = 256" newline hexmask.long.byte 0x0 8.--15. 1. "RX_BUFFER_DEPTH,The value of this register is derived from the IC_RX_BUFFER_DEPTH coreConsultant parameter. - 0x00: Reserved - 0x01: 2 - 0x02: 3 - ... - 0xFF: 256" newline bitfld.long 0x0 7. "ADD_ENCODED_PARAMS,The value of this register is derived from the IC_ADD_ENCODED_PARAMS coreConsultant parameter. Reading 1 in this bit means that the capability of reading these encoded parameters via software has been included. Otherwise the entire.." "Disables capability of reading encoded parameters,Enables capability of reading encoded parameters" newline bitfld.long 0x0 6. "HAS_DMA,The value of this register is derived from the IC_HAS_DMA coreConsultant parameter. 0x0: DMA handshaking signals are disabled 0x1: DMA handshaking signals are enabled" "DMA handshaking signals are disabled,DMA handshaking signals are enabled" newline bitfld.long 0x0 5. "INTR_IO,The value of this register is derived from the IC_INTR_IO coreConsultant parameter. 0x1: COMBINED Interrupt outputs 0x0: INDIVIDUAL Interrupt outputs" "INDIVIDUAL Interrupt outputs,COMBINED Interrupt outputs" newline bitfld.long 0x0 4. "HC_COUNT_VALUES,The value of this register is derived from the IC_HC_COUNT VALUES coreConsultant parameter. 0x0: Programmable count values for each mode. 0x1: Hard code the count values for each mode." "Programmable count values for each mode,Hard code the count values for each mode" newline bitfld.long 0x0 2.--3. "MAX_SPEED_MODE,The value of this register is derived from the IC_MAX_SPEED_MODE coreConsultant parameter. - 0x0: Reserved - 0x1: Standard - 0x2: Fast - 0x3: High 0x2: IC MAX SPEED is FAST MODE 0x3: IC MAX SPEED is HIGH MODE 0x1: IC MAX SPEED is STANDARD.." "Reserved,IC MAX SPEED is STANDARD MODE,IC MAX SPEED is FAST MODE,IC MAX SPEED is HIGH MODE" newline bitfld.long 0x0 0.--1. "APB_DATA_WIDTH,The value of this register is derived from the APB_DATA_WIDTH coreConsultant parameter. 0x0: APB data bus width is 08 bits 0x1: APB data bus width is 16 bits 0x2: APB data bus width is 32 bits 0x3: Reserved bits" "APB data bus width is 08 bits,APB data bus width is 16 bits,APB data bus width is 32 bits,Reserved bits" line.long 0x4 "IC_COMP_VERSION,I2C Component Version Register" hexmask.long 0x4 0.--31. 1. "IC_COMP_VERSION,Specific values for this register are described in the Releases Table in the DW_apb_i2c Release Notes" line.long 0x8 "IC_COMP_TYPE,I2C Component Type Register" hexmask.long 0x8 0.--31. 1. "IC_COMP_TYPE,Designware Component Type number = 0x44_57_01_40. This assigned unique hex value is constant and is derived from the two ASCII letters 'DW' followed by a 16-bit unsigned number." tree.end repeat.end elif (CORENAME()=="CORTEXA55") repeat 12. (increment 1. 1.) (list ad:0x300B0000 ad:0x300C0000 ad:0x300D0000 ad:0x300E0000 ad:0x30AC0000 ad:0x30AD0000 ad:0x30AE0000 ad:0x30AF0000 ad:0x30B00000 ad:0x30B10000 ad:0x30B20000 ad:0x30B30000) tree "I2C$1" base $2 group.long 0x0++0xB line.long 0x0 "IC_CON,I2C Control Register. This register can be written only when the DW_apb_i2c is disabled. which corresponds to the IC_ENABLE[0] register being set to 0. Writes at other times have no effect. Read/Write Access: - If configuration parameter.." hexmask.long.word 0x0 20.--31. 1. "RSVD_IC_CON_2,IC_CON_2 Reserved bits - Read Only" newline bitfld.long 0x0 19. "SMBUS_PERSISTENT_SLV_ADDR_EN,The bit controls to enable DW_apb_i2c slave as persistent or non persistent slave. If the slave is non-PSA then DW_apb_i2c slave device clears the Address valid flag for both General and Directed Reset ARP command else the.." "SMBus Persistent Slave address control is disabled,SMBus Persistent Slave address control is enabled" newline bitfld.long 0x0 18. "SMBUS_ARP_EN,This bit controls whether DW_apb_i2c should enable Address Resolution Logic in SMBus Mode. The Slave mode will decode the Address Resolution Protocol commands and respond to it. The DW_apb_i2c slave also includes the generation/validity of.." "SMBus ARP control is disabled,SMBus ARP control is enabled" newline bitfld.long 0x0 17. "SMBUS_SLAVE_QUICK_EN,If this bit is set to 1 DW_apb_i2c slave only receives Quick commands in SMBus Mode. If this bit is set to 0 DW_apb_i2c slave receives all bus protocols but not Quick commands. This bit is applicable only in slave mode. Reset.." "SMBus SLave is disabled to receive Quick command,SMBus SLave is enabled to receive Quick command" newline rbitfld.long 0x0 16. "RSVD_OPTIONAL_SAR_CTRL,OPTIONAL_SAR_CTRL Reserved bits - Read Only" "0,1" newline hexmask.long.byte 0x0 12.--15. 1. "RSVD_IC_CON_1,IC_CON_1 Reserved bits - Read Only" newline bitfld.long 0x0 11. "BUS_CLEAR_FEATURE_CTRL,In Master mode: - 1'b1: Bus Clear Feature is enabled. - 1'b0: Bus Clear Feature is Disabled. In Slave mode this register bit is not applicable. Reset value: 0x0. 0x0: Bus Clear Feature is disabled. 0x1: Bus Clear Feature ois.." "Bus Clear Feature is disabled,Bus Clear Feature ois enabled" newline rbitfld.long 0x0 10. "STOP_DET_IF_MASTER_ACTIVE,In Master mode: - 1'b1: issues the STOP_DET interrupt only when master is active. - 1'b0: issues the STOP_DET irrespective of whether master is active or not. Reset value: 0x0. 0x0: Master issues the STOP_DET interrupt.." "Master issues the STOP_DET interrupt..,Master issues the STOP_DET interrupt only when.." newline bitfld.long 0x0 9. "RX_FIFO_FULL_HLD_CTRL,This bit controls whether DW_apb_i2c should hold the bus when the Rx FIFO is physically full to its RX_BUFFER_DEPTH as described in the IC_RX_FULL_HLD_BUS_EN parameter. Reset value: 0x0. 0x0: Overflow when RX_FIFO is full 0x1: Hold.." "Overflow when RX_FIFO is full,Hold bus when RX_FIFO is full" newline bitfld.long 0x0 8. "TX_EMPTY_CTRL,This bit controls the generation of the TX_EMPTY interrupt as described in the IC_RAW_INTR_STAT register. Reset value: 0x0. 0x0: Default behaviour of TX_EMPTY interrupt 0x1: Controlled generation of TX_EMPTY interrupt" "Default behaviour of TX_EMPTY interrupt,Controlled generation of TX_EMPTY interrupt" newline bitfld.long 0x0 7. "STOP_DET_IFADDRESSED,In slave mode: - 1'b1: issues the STOP_DET interrrupt only when it is addressed. - 0'b0: issues the STOP_DET irrespective of whether it's addressed or not. Reset value: 0x0 NOTE: During a general call address this slave does not.." "slave issues STOP_DET intr always,slave issues STOP_DET intr only if addressed" newline bitfld.long 0x0 6. "IC_SLAVE_DISABLE,This bit controls whether I2C has its slave disabled which means once the presetn signal is applied then this bit takes on the value of the configuration parameter IC_SLAVE_DISABLE. You have the choice of having the slave enabled or.." "Slave mode is enabled,Slave mode is disabled" newline bitfld.long 0x0 5. "IC_RESTART_EN,Determines whether RESTART conditions may be sent when acting as a master. Some older slaves do not support handling RESTART conditions; however RESTART conditions are used in several DW_apb_i2c operations. When RESTART is disabled the.." "Master restart disabled,Master restart enabled" newline bitfld.long 0x0 4. "IC_10BITADDR_MASTER,If the I2C_DYNAMIC_TAR_UPDATE configuration parameter is set to 'No' (0) this bit is named IC_10BITADDR_MASTER and controls whether the DW_apb_i2c starts its transfers in 7- or 10-bit addressing mode when acting as a master. If.." "Master 7Bit addressing mode,Master 10Bit addressing mode" newline bitfld.long 0x0 3. "IC_10BITADDR_SLAVE,When acting as a slave this bit controls whether the DW_apb_i2c responds to 7- or 10-bit addresses. - 0: 7-bit addressing. The DW_apb_i2c ignores transactions that involve 10-bit addressing; for 7-bit addressing only the lower 7 bits.." "Slave 7Bit addressing,Slave 10Bit addressing" newline bitfld.long 0x0 1.--2. "SPEED,These bits control at which speed the DW_apb_i2c operates; its setting is relevant only if one is operating the DW_apb_i2c in master mode. Hardware protects against illegal values being programmed by software. These bits must be programmed.." "?,Standard Speed mode of operation,Fast or Fast Plus mode of operation,High Speed mode of operation" newline bitfld.long 0x0 0. "MASTER_MODE,This bit controls whether the DW_apb_i2c master is enabled. Reset value: IC_MASTER_MODE configuration parameter NOTE: Software should ensure that if this bit is written with '1' then bit 6 should also be written with a '1'. 0x0: Master mode.." "Master mode is disabled,Master mode is enabled" line.long 0x4 "IC_TAR,I2C Target Address Register If the configuration parameter I2C_DYNAMIC_TAR_UPDATE is set to 'No' (0). this register is 12 bits wide. and bits 31:12 are reserved. This register can be written to only when IC_ENABLE[0] is set to 0. However. if.." hexmask.long.word 0x4 17.--31. 1. "RSVD_IC_TAR_2,IC_TAR_2 Reserved bits - Read Only" newline bitfld.long 0x4 16. "SMBUS_QUICK_CMD,If bit 11 (SPECIAL) is set to 1 then this bit indicates whether a Quick command is to be performed by the DW_apb_i2c. Reset value: 0x0 0x0: Disables programming of QUICK-CMD transmission 0x1: Enables programming of QUICK-CMD transmission" "Disables programming of QUICK-CMD transmission,Enables programming of QUICK-CMD transmission" newline rbitfld.long 0x4 14.--15. "RSVD_IC_TAR_1,IC_TAR_1 Reserved bits - Read Only" "0,1,2,3" newline rbitfld.long 0x4 13. "RSVD_DEVICE_ID,DEVICE_ID Reserved bits - Read Only" "0,1" newline rbitfld.long 0x4 12. "RSVD_IC_10BITADDR_MASTER,IC_10BITADDR_MASTER Reserved bits - Read Only" "0,1" newline bitfld.long 0x4 11. "SPECIAL,This bit indicates whether software performs a Device-ID or General Call or START BYTE command. - 0: ignore bit 10 GC_OR_START and use IC_TAR normally - 1: perform special I2C command as specified in Device_ID or GC_OR_START bit Reset value: 0x0.." "Disables programming of GENERAL_CALL or..,Enables programming of GENERAL_CALL or.." newline bitfld.long 0x4 10. "GC_OR_START,If bit 11 (SPECIAL) is set to 1 and bit 13(Device-ID) is set to 0 then this bit indicates whether a General Call or START byte command is to be performed by the DW_apb_i2c. - 0: General Call Address - after issuing a General Call only.." "GENERAL_CALL byte transmission,START byte transmission" newline hexmask.long.word 0x4 0.--9. 1. "IC_TAR,This is the target address for any master transaction. When transmitting a General Call these bits are ignored. To generate a START BYTE the CPU needs to write only once into these bits. If the IC_TAR and IC_SAR are the same loopback exists but.." line.long 0x8 "IC_SAR,I2C Slave Address Register" hexmask.long.tbyte 0x8 10.--31. 1. "RSVD_IC_SAR,IC_SAR Reserved bits - Read Only" newline hexmask.long.word 0x8 0.--9. 1. "IC_SAR,The IC_SAR holds the slave address when the I2C is operating as a slave. For 7-bit addressing only IC_SAR[6:0] is used. This register can be written only when the I2C interface is disabled which corresponds to the IC_ENABLE[0] register being set.." group.long 0x10++0x13 line.long 0x0 "IC_DATA_CMD,I2C Rx/Tx Data Buffer and Command Register; this is the register the CPU writes to when filling the TX FIFO and the CPU reads from when retrieving bytes from RX FIFO. The size of the register changes as follows: Write: - 11 bits when.." hexmask.long.tbyte 0x0 12.--31. 1. "RSVD_IC_DATA_CMD,IC_DATA_CMD Reserved bits - Read Only" newline rbitfld.long 0x0 11. "FIRST_DATA_BYTE,Indicates the first data byte received after the address phase for receive transfer in Master receiver or Slave receiver mode. Reset value : 0x0 NOTE: In case of APB_DATA_WIDTH=8 1. The user has to perform two APB Reads to IC_DATA_CMD in.." "Sequential data byte received,Non sequential data byte received" newline bitfld.long 0x0 10. "RESTART,This bit controls whether a RESTART is issued before the byte is sent or received. This bit is available only if IC_EMPTYFIFO_HOLD_MASTER_EN is configured to 1. 1 - If IC_RESTART_EN is 1 a RESTART is issued before the data is sent/received.." "Donot Issue RESTART before this command,Issue RESTART before this command" newline bitfld.long 0x0 9. "STOP,This bit controls whether a STOP is issued after the byte is sent or received. This bit is available only if IC_EMPTYFIFO_HOLD_MASTER_EN is configured to 1. - 1 - STOP is issued after this byte regardless of whether or not the Tx FIFO is empty. If.." "Donot Issue STOP after this command,Issue STOP after this command" newline bitfld.long 0x0 8. "CMD,This bit controls whether a read or a write is performed. This bit does not control the direction when the DW_apb_i2c acts as a slave. It controls only the direction when it acts as a master. When a command is entered in the TX FIFO this bit.." "Master Write Command,Master Read Command" newline hexmask.long.byte 0x0 0.--7. 1. "DAT,This register contains the data to be transmitted or received on the I2C bus. If you are writing to this register and want to perform a read bits 7:0 (DAT) are ignored by the DW_apb_i2c. However when you read this register these bits return the.." line.long 0x4 "IC_SS_SCL_HCNT,Standard Speed I2C Clock SCL High Count Register" hexmask.long.word 0x4 16.--31. 1. "RSVD_IC_SS_SCL_HIGH_COUNT,IC_SS_SCL_HCNT Reserved bits - Read Only" newline hexmask.long.word 0x4 0.--15. 1. "IC_SS_SCL_HCNT,This register must be set before any I2C bus transaction can take place to ensure proper I/O timing. This register sets the SCL clock high-period count for standard speed. For more information refer to 'IC_CLK Frequency Configuration'." line.long 0x8 "IC_SS_SCL_LCNT,Standard Speed I2C Clock SCL Low Count Register" hexmask.long.word 0x8 16.--31. 1. "RSVD_IC_SS_SCL_LOW_COUNT,RSVD_IC_SS_SCL_LOW_COUNT Reserved bits - Read Only" newline hexmask.long.word 0x8 0.--15. 1. "IC_SS_SCL_LCNT,This register must be set before any I2C bus transaction can take place to ensure proper I/O timing. This register sets the SCL clock low period count for standard speed. For more information refer to 'IC_CLK Frequency Configuration' This.." line.long 0xC "IC_FS_SCL_HCNT,Fast Mode or Fast Mode Plus I2C Clock SCL High Count Register" hexmask.long.word 0xC 16.--31. 1. "RSVD_IC_FS_SCL_HCNT,IC_FS_SCL_HCNT Reserved bits - Read Only" newline hexmask.long.word 0xC 0.--15. 1. "IC_FS_SCL_HCNT,This register must be set before any I2C bus transaction can take place to ensure proper I/O timing. This register sets the SCL clock high-period count for fast mode or fast mode plus. It is used in high-speed mode to send the Master Code.." line.long 0x10 "IC_FS_SCL_LCNT,Fast Mode or Fast Mode Plus I2C Clock SCL Low Count Register" hexmask.long.word 0x10 16.--31. 1. "RSVD_IC_FS_SCL_LCNT,IC_FS_SCL_LCNT Reserved bits - Read Only" newline hexmask.long.word 0x10 0.--15. 1. "IC_FS_SCL_LCNT,This register must be set before any I2C bus transaction can take place to ensure proper I/O timing. This register sets the SCL clock low period count for fast speed. It is used in high-speed mode to send the Master Code and START BYTE or.." rgroup.long 0x2C++0x3 line.long 0x0 "IC_INTR_STAT,I2C Interrupt Status Register Each bit in this register has a corresponding mask bit in the IC_INTR_MASK register. These bits are cleared by reading the matching interrupt clear register. The unmasked raw versions of these bits are available.." hexmask.long.tbyte 0x0 15.--31. 1. "RSVD_IC_INTR_STAT,IC_INTR_STAT Reserved bits - Read Only" newline bitfld.long 0x0 14. "R_SCL_STUCK_AT_LOW,See IC_RAW_INTR_STAT for a detailed description of R_SCL_STUCK_AT_LOW bit. Reset Value: 0x0 0x1: R_SCL_STUCK_AT_LOW interrupt is active 0x0: R_SCL_STUCK_AT_LOW interrupt is inactive" "R_SCL_STUCK_AT_LOW interrupt is inactive,R_SCL_STUCK_AT_LOW interrupt is active" newline bitfld.long 0x0 13. "R_MASTER_ON_HOLD,See IC_RAW_INTR_STAT for a detailed description of R_MASTER_ON_HOLD bit. Reset value: 0x0 0x1: R_MASTER_ON_HOLD interrupt is active 0x0: R_MASTER_ON_HOLD interrupt is inactive" "R_MASTER_ON_HOLD interrupt is inactive,R_MASTER_ON_HOLD interrupt is active" newline bitfld.long 0x0 12. "R_RESTART_DET,See IC_RAW_INTR_STAT for a detailed description of R_RESTART_DET bit. Reset value: 0x0 0x1: R_RESTART_DET interrupt is active 0x0: R_RESTART_DET interrupt is inactive" "R_RESTART_DET interrupt is inactive,R_RESTART_DET interrupt is active" newline bitfld.long 0x0 11. "R_GEN_CALL,See IC_RAW_INTR_STAT for a detailed description of R_GEN_CALL bit. Reset value: 0x0 0x1: R_GEN_CALL interrupt is active 0x0: R_GEN_CALL interrupt is inactive" "R_GEN_CALL interrupt is inactive,R_GEN_CALL interrupt is active" newline bitfld.long 0x0 10. "R_START_DET,See IC_RAW_INTR_STAT for a detailed description of R_START_DET bit. Reset value: 0x0 0x1: R_START_DET interrupt is active 0x0: R_START_DET interrupt is inactive" "R_START_DET interrupt is inactive,R_START_DET interrupt is active" newline bitfld.long 0x0 9. "R_STOP_DET,See IC_RAW_INTR_STAT for a detailed description of R_STOP_DET bit. Reset value: 0x0 0x1: R_STOP_DET interrupt is active 0x0: R_STOP_DET interrupt is inactive" "R_STOP_DET interrupt is inactive,R_STOP_DET interrupt is active" newline bitfld.long 0x0 8. "R_ACTIVITY,See IC_RAW_INTR_STAT for a detailed description of R_ACTIVITY bit. Reset value: 0x0 0x1: R_ACTIVITY interrupt is active 0x0: R_ACTIVITY interrupt is inactive" "R_ACTIVITY interrupt is inactive,R_ACTIVITY interrupt is active" newline bitfld.long 0x0 7. "R_RX_DONE,See IC_RAW_INTR_STAT for a detailed description of R_RX_DONE bit. Reset value: 0x0 0x1: R_RX_DONE interrupt is active 0x0: R_RX_DONE interrupt is inactive" "R_RX_DONE interrupt is inactive,R_RX_DONE interrupt is active" newline bitfld.long 0x0 6. "R_TX_ABRT,See IC_RAW_INTR_STAT for a detailed description of R_TX_ABRT bit. Reset value: 0x0 0x1: R_TX_ABRT interrupt is active 0x0: R_TX_ABRT interrupt is inactive" "R_TX_ABRT interrupt is inactive,R_TX_ABRT interrupt is active" newline bitfld.long 0x0 5. "R_RD_REQ,See IC_RAW_INTR_STAT for a detailed description of R_RD_REQ bit. Reset value: 0x0 0x1: R_RD_REQ interrupt is active 0x0: R_RD_REQ interrupt is inactive" "R_RD_REQ interrupt is inactive,R_RD_REQ interrupt is active" newline bitfld.long 0x0 4. "R_TX_EMPTY,See IC_RAW_INTR_STAT for a detailed description of R_TX_EMPTY bit. Reset value: 0x0 0x1: R_TX_EMPTY interrupt is active 0x0: R_TX_EMPTY interrupt is inactive" "R_TX_EMPTY interrupt is inactive,R_TX_EMPTY interrupt is active" newline bitfld.long 0x0 3. "R_TX_OVER,See IC_RAW_INTR_STAT for a detailed description of R_TX_OVER bit. Reset value: 0x0 0x1: R_TX_OVER interrupt is active 0x0: R_TX_OVER interrupt is inactive" "R_TX_OVER interrupt is inactive,R_TX_OVER interrupt is active" newline bitfld.long 0x0 2. "R_RX_FULL,See IC_RAW_INTR_STAT for a detailed description of R_RX_FULL bit. Reset value: 0x0 0x1: R_RX_FULL interrupt is active 0x0: R_RX_FULL interrupt is inactive" "R_RX_FULL interrupt is inactive,R_RX_FULL interrupt is active" newline bitfld.long 0x0 1. "R_RX_OVER,See IC_RAW_INTR_STAT for a detailed description of R_RX_OVER bit. Reset value: 0x0 0x1: R_RX_OVER interrupt is active 0x0: R_RX_OVER interrupt is inactive" "R_RX_OVER interrupt is inactive,R_RX_OVER interrupt is active" newline bitfld.long 0x0 0. "R_RX_UNDER,See IC_RAW_INTR_STAT for a detailed description of R_RX_UNDER bit. Reset value: 0x0 0x1: RX_UNDER interrupt is active 0x0: RX_UNDER interrupt is inactive" "RX_UNDER interrupt is inactive,RX_UNDER interrupt is active" group.long 0x30++0x3 line.long 0x0 "IC_INTR_MASK,I2C Interrupt Mask Register. These bits mask their corresponding interrupt status bits. This register is active low; a value of 0 masks the interrupt. whereas a value of 1 unmasks the interrupt." hexmask.long.tbyte 0x0 15.--31. 1. "RSVD_IC_INTR_STAT,IC_INTR_STAT Reserved bits - Read Only" newline bitfld.long 0x0 14. "M_SCL_STUCK_AT_LOW,This bit masks the R_SCL_STUCK_AT_LOW interrupt in IC_INTR_STAT register. Reset Value: 0x0 0x1: SCL_STUCK_AT_LOW interrupt is unmasked 0x0: SCL_STUCK_AT_LOW interrupt is masked" "SCL_STUCK_AT_LOW interrupt is masked,SCL_STUCK_AT_LOW interrupt is unmasked" newline rbitfld.long 0x0 13. "M_MASTER_ON_HOLD_READ_ONLY,This M_MASTER_ON_HOLD_read_only bit masks the R_MASTER_ON_HOLD interrupt in IC_INTR_STAT register. Reset value: 0x0 0x1: MASTER_ON_HOLD interrupt is unmasked 0x0: MASTER_ON_HOLD interrupt is masked" "MASTER_ON_HOLD interrupt is masked,MASTER_ON_HOLD interrupt is unmasked" newline bitfld.long 0x0 12. "M_RESTART_DET,This bit masks the R_RESTART_DET interrupt in IC_INTR_STAT register. Reset value: 0x0 0x1: RESTART_DET interrupt is unmasked 0x0: RESTART_DET interrupt is masked" "RESTART_DET interrupt is masked,RESTART_DET interrupt is unmasked" newline bitfld.long 0x0 11. "M_GEN_CALL,This bit masks the R_GEN_CALL interrupt in IC_INTR_STAT register. Reset value: 0x1 0x1: GEN_CALL interrupt is unmasked 0x0: GEN_CALL interrupt is masked" "GEN_CALL interrupt is masked,GEN_CALL interrupt is unmasked" newline bitfld.long 0x0 10. "M_START_DET,This bit masks the R_START_DET interrupt in IC_INTR_STAT register. Reset value: 0x0 0x1: START_DET interrupt is unmasked 0x0: START_DET interrupt is masked" "START_DET interrupt is masked,START_DET interrupt is unmasked" newline bitfld.long 0x0 9. "M_STOP_DET,This bit masks the R_STOP_DET interrupt in IC_INTR_STAT register. Reset value: 0x0 0x1: STOP_DET interrupt is unmasked 0x0: STOP_DET interrupt is masked" "STOP_DET interrupt is masked,STOP_DET interrupt is unmasked" newline bitfld.long 0x0 8. "M_ACTIVITY,This bit masks the R_ACTIVITY interrupt in IC_INTR_STAT register. Reset value: 0x0 0x1: ACTIVITY interrupt is unmasked 0x0: ACTIVITY interrupt is masked" "ACTIVITY interrupt is masked,ACTIVITY interrupt is unmasked" newline bitfld.long 0x0 7. "M_RX_DONE,This bit masks the R_RX_DONE interrupt in IC_INTR_STAT register. Reset value: 0x1 0x1: RX_DONE interrupt is unmasked 0x0: RX_DONE interrupt is masked" "RX_DONE interrupt is masked,RX_DONE interrupt is unmasked" newline bitfld.long 0x0 6. "M_TX_ABRT,This bit masks the R_TX_ABRT interrupt in IC_INTR_STAT register. Reset value: 0x1 0x1: TX_ABORT interrupt is unmasked 0x0: TX_ABORT interrupt is masked" "TX_ABORT interrupt is masked,TX_ABORT interrupt is unmasked" newline bitfld.long 0x0 5. "M_RD_REQ,This bit masks the R_RD_REQ interrupt in IC_INTR_STAT register. Reset value: 0x1 0x1: RD_REQ interrupt is unmasked 0x0: RD_REQ interrupt is masked" "RD_REQ interrupt is masked,RD_REQ interrupt is unmasked" newline bitfld.long 0x0 4. "M_TX_EMPTY,This bit masks the R_TX_EMPTY interrupt in IC_INTR_STAT register. Reset value: 0x1 0x1: TX_EMPTY interrupt is unmasked 0x0: TX_EMPTY interrupt is masked" "TX_EMPTY interrupt is masked,TX_EMPTY interrupt is unmasked" newline bitfld.long 0x0 3. "M_TX_OVER,This bit masks the R_TX_OVER interrupt in IC_INTR_STAT register. Reset value: 0x1 0x1: TX_OVER interrupt is unmasked 0x0: TX_OVER interrupt is masked" "TX_OVER interrupt is masked,TX_OVER interrupt is unmasked" newline bitfld.long 0x0 2. "M_RX_FULL,This bit masks the R_RX_FULL interrupt in IC_INTR_STAT register. Reset value: 0x1 0x1: RX_FULL interrupt is unmasked 0x0: RX_FULL interrupt is masked" "RX_FULL interrupt is masked,RX_FULL interrupt is unmasked" newline bitfld.long 0x0 1. "M_RX_OVER,This bit masks the R_RX_OVER interrupt in IC_INTR_STAT register. Reset value: 0x1 0x1: RX_OVER interrupt is unmasked 0x0: RX_OVER interrupt is masked" "RX_OVER interrupt is masked,RX_OVER interrupt is unmasked" newline bitfld.long 0x0 0. "M_RX_UNDER,This bit masks the R_RX_UNDER interrupt in IC_INTR_STAT register. Reset value: 0x1 0x1: RX_UNDER interrupt is unmasked 0x0: RX_UNDER interrupt is masked" "RX_UNDER interrupt is masked,RX_UNDER interrupt is unmasked" rgroup.long 0x34++0x3 line.long 0x0 "IC_RAW_INTR_STAT,I2C Raw Interrupt Status Register Unlike the IC_INTR_STAT register. these bits are not masked so they always show the true status of the DW_apb_i2c." hexmask.long.tbyte 0x0 15.--31. 1. "RSVD_IC_RAW_INTR_STAT,IC_RAW_INTR_STAT Reserved bits - Read Only" newline bitfld.long 0x0 14. "SCL_STUCK_AT_LOW,Indicates whether the SCL Line is stuck at low for the IC_SCL_STUCK_LOW_TIMEOUT number of ic_clk periods. Enabled only when IC_BUS_CLEAR_FEATURE=1 and IC_ULTRA_FAST_MODE=0. Reset Value: 0x0 0x1: SCL_STUCK_AT_LOW interrupt is active 0x0:.." "SCL_STUCK_AT_LOW interrupt is inactive,SCL_STUCK_AT_LOW interrupt is active" newline bitfld.long 0x0 13. "MASTER_ON_HOLD,Indicates whether master is holding the bus and TX FIFO is empty. Enabled only when I2C_DYNAMIC_TAR_UPDATE=1 and IC_EMPTYFIFO_HOLD_MASTER_EN=1. Reset value: 0x0 0x1: MASTER_ON_HOLD interrupt is active 0x0: MASTER_ON_HOLD interrupt is.." "MASTER_ON_HOLD interrupt is inactive,MASTER_ON_HOLD interrupt is active" newline bitfld.long 0x0 12. "RESTART_DET,Indicates whether a RESTART condition has occurred on the I2C interface when DW_apb_i2c is operating in Slave mode and the slave is being addressed. Enabled only when IC_SLV_RESTART_DET_EN=1. Note: However in high-speed mode or during a.." "RESTART_DET interrupt is inactive,RESTART_DET interrupt is active" newline bitfld.long 0x0 11. "GEN_CALL,Set only when a General Call address is received and it is acknowledged. It stays set until it is cleared either by disabling DW_apb_i2c or when the CPU reads bit 0 of the IC_CLR_GEN_CALL register. DW_apb_i2c stores the received data in the Rx.." "GEN_CALL interrupt is inactive,GEN_CALL interrupt is active" newline bitfld.long 0x0 10. "START_DET,Indicates whether a START or RESTART condition has occurred on the I2C interface regardless of whether DW_apb_i2c is operating in slave or master mode. Reset value: 0x0 0x1: START_DET interrupt is active 0x0: START_DET interrupt is inactive" "START_DET interrupt is inactive,START_DET interrupt is active" newline bitfld.long 0x0 9. "STOP_DET,Indicates whether a STOP condition has occurred on the I2C interface regardless of whether DW_apb_i2c is operating in slave or master mode. In Slave Mode: - If IC_CON[7]=1'b1 (STOP_DET_IFADDRESSED) the STOP_DET interrupt will be issued only if.." "STOP_DET interrupt is inactive,STOP_DET interrupt is active" newline bitfld.long 0x0 8. "ACTIVITY,This bit captures DW_apb_i2c activity and stays set until it is cleared. There are four ways to clear it: - Disabling the DW_apb_i2c - Reading the IC_CLR_ACTIVITY register - Reading the IC_CLR_INTR register - System reset Once this bit is set.." "RAW_INTR_ACTIVITY interrupt is inactive,RAW_INTR_ACTIVITY interrupt is active" newline bitfld.long 0x0 7. "RX_DONE,When the DW_apb_i2c is acting as a slave-transmitter this bit is set to 1 if the master does not acknowledge a transmitted byte. This occurs on the last byte of the transmission indicating that the transmission is done. Reset value: 0x0 0x1:.." "RX_DONE interrupt is inactive,RX_DONE interrupt is active" newline bitfld.long 0x0 6. "TX_ABRT,This bit indicates if DW_apb_i2c as an I2C transmitter is unable to complete the intended actions on the contents of the transmit FIFO. This situation can occur both as an I2C master or an I2C slave and is referred to as a 'transmit abort'." "TX_ABRT interrupt is inactive,TX_ABRT interrupt is active" newline bitfld.long 0x0 5. "RD_REQ,This bit is set to 1 when DW_apb_i2c is acting as a slave and another I2C master is attempting to read data from DW_apb_i2c. The DW_apb_i2c holds the I2C bus in a wait state (SCL=0) until this interrupt is serviced which means that the slave has.." "RD_REQ interrupt is inactive,RD_REQ interrupt is active" newline bitfld.long 0x0 4. "TX_EMPTY,The behavior of the TX_EMPTY interrupt status differs based on the TX_EMPTY_CTRL selection in the IC_CON register. - When TX_EMPTY_CTRL = 0: This bit is set to 1 when the transmit buffer is at or below the threshold value set in the IC_TX_TL.." "TX_EMPTY interrupt is inactive,TX_EMPTY interrupt is active" newline bitfld.long 0x0 3. "TX_OVER,Set during transmit if the transmit buffer is filled to IC_TX_BUFFER_DEPTH and the processor attempts to issue another I2C command by writing to the IC_DATA_CMD register. When the module is disabled this bit keeps its level until the master or.." "TX_OVER interrupt is inactive,TX_OVER interrupt is active" newline bitfld.long 0x0 2. "RX_FULL,Set when the receive buffer reaches or goes above the RX_TL threshold in the IC_RX_TL register. It is automatically cleared by hardware when buffer level goes below the threshold. If the module is disabled (IC_ENABLE[0]=0) the RX FIFO is flushed.." "RX_FULL interrupt is inactive,RX_FULL interrupt is active" newline bitfld.long 0x0 1. "RX_OVER,Set if the receive buffer is completely filled to IC_RX_BUFFER_DEPTH and an additional byte is received from an external I2C device. The DW_apb_i2c acknowledges this but any data bytes received after the FIFO is full are lost. If the module is.." "RX_OVER interrupt is inactive,RX_OVER interrupt is active" newline bitfld.long 0x0 0. "RX_UNDER,Set if the processor attempts to read the receive buffer when it is empty by reading from the IC_DATA_CMD register. If the module is disabled (IC_ENABLE[0]=0) this bit keeps its level until the master or slave state machines go into idle and.." "RX_UNDER interrupt is inactive,RX_UNDER interrupt is active" group.long 0x38++0x7 line.long 0x0 "IC_RX_TL,I2C Receive FIFO Threshold Register" hexmask.long.tbyte 0x0 8.--31. 1. "RSVD_IC_RX_TL,IC_RX_TL Reserved bits - Read Only" newline hexmask.long.byte 0x0 0.--7. 1. "RX_TL,Receive FIFO Threshold Level. Controls the level of entries (or above) that triggers the RX_FULL interrupt (bit 2 in IC_RAW_INTR_STAT register). The valid range is 0-255 with the additional restriction that hardware does not allow this value to be.." line.long 0x4 "IC_TX_TL,I2C Transmit FIFO Threshold Register" hexmask.long.tbyte 0x4 8.--31. 1. "RSVD_IC_TX_TL,IC_TX_TL Reserved bits - Read Only" newline hexmask.long.byte 0x4 0.--7. 1. "TX_TL,Transmit FIFO Threshold Level. Controls the level of entries (or below) that trigger the TX_EMPTY interrupt (bit 4 in IC_RAW_INTR_STAT register). The valid range is 0-255 with the additional restriction that it may not be set to value larger than.." rgroup.long 0x40++0x2B line.long 0x0 "IC_CLR_INTR,Clear Combined and Individual Interrupt Register" hexmask.long 0x0 1.--31. 1. "RSVD_IC_CLR_INTR,CLR_INTR Reserved bits - Read Only" newline bitfld.long 0x0 0. "CLR_INTR,Read this register to clear the combined interrupt all individual interrupts and the IC_TX_ABRT_SOURCE register. This bit does not clear hardware clearable interrupts but software clearable interrupts. Refer to Bit 9 of the IC_TX_ABRT_SOURCE.." "0,1" line.long 0x4 "IC_CLR_RX_UNDER,Clear RX_UNDER Interrupt Register" hexmask.long 0x4 1.--31. 1. "RSVD_IC_CLR_RX_UNDER,IC_CLR_RX_UNDER Reserved bits - Read Only" newline bitfld.long 0x4 0. "CLR_RX_UNDER,Read this register to clear the RX_UNDER interrupt (bit 0) of the IC_RAW_INTR_STAT register. Reset value: 0x0" "0,1" line.long 0x8 "IC_CLR_RX_OVER,Clear RX_OVER Interrupt Register" hexmask.long 0x8 1.--31. 1. "RSVD_IC_CLR_RX_OVER,IC_CLR_RX_OVER Reserved bits - Read Only" newline bitfld.long 0x8 0. "CLR_RX_OVER,Read this register to clear the RX_OVER interrupt (bit 1) of the IC_RAW_INTR_STAT register. Reset value: 0x0" "0,1" line.long 0xC "IC_CLR_TX_OVER,Clear TX_OVER Interrupt Register" hexmask.long 0xC 1.--31. 1. "RSVD_IC_CLR_TX_OVER,IC_CLR_TX_OVER Reserved bits - Read Only" newline bitfld.long 0xC 0. "CLR_TX_OVER,Read this register to clear the TX_OVER interrupt (bit 3) of the IC_RAW_INTR_STAT register. Reset value: 0x0" "0,1" line.long 0x10 "IC_CLR_RD_REQ,Clear RD_REQ Interrupt Register" hexmask.long 0x10 1.--31. 1. "RSVD_IC_CLR_RD_REQ,IC_CLR_RD_REQ Reserved bits - Read Only" newline bitfld.long 0x10 0. "CLR_RD_REQ,Read this register to clear the RD_REQ interrupt (bit 5) of the IC_RAW_INTR_STAT register. Reset value: 0x0" "0,1" line.long 0x14 "IC_CLR_TX_ABRT,Clear TX_ABRT Interrupt Register" hexmask.long 0x14 1.--31. 1. "RSVD_IC_CLR_TX_ABRT,IC_CLR_TX_ABRT Reserved bits - Read Only" newline bitfld.long 0x14 0. "CLR_TX_ABRT,Read this register to clear the TX_ABRT interrupt (bit 6) of the IC_RAW_INTR_STAT register and the IC_TX_ABRT_SOURCE register. This also releases the TX FIFO from the flushed/reset state allowing more writes to the TX FIFO. Refer to Bit 9.." "0,1" line.long 0x18 "IC_CLR_RX_DONE,Clear RX_DONE Interrupt Register" hexmask.long 0x18 1.--31. 1. "RSVD_IC_CLR_RX_DONE,IC_CLR_RX_DONE Reserved bits - Read Only" newline bitfld.long 0x18 0. "CLR_RX_DONE,Read this register to clear the RX_DONE interrupt (bit 7) of the IC_RAW_INTR_STAT register. Reset value: 0x0" "0,1" line.long 0x1C "IC_CLR_ACTIVITY,Clear ACTIVITY Interrupt Register" hexmask.long 0x1C 1.--31. 1. "RSVD_IC_CLR_ACTIVITY,IC_CLR_ACTIVITY Reserved bits - Read Only" newline bitfld.long 0x1C 0. "CLR_ACTIVITY,Reading this register clears the ACTIVITY interrupt if the I2C is not active anymore. If the I2C module is still active on the bus the ACTIVITY interrupt bit continues to be set. It is automatically cleared by hardware if the module is.." "0,1" line.long 0x20 "IC_CLR_STOP_DET,Clear STOP_DET Interrupt Register" hexmask.long 0x20 1.--31. 1. "RSVD_IC_CLR_STOP_DET,IC_CLR_STOP_DET Reserved bits - Read Only" newline bitfld.long 0x20 0. "CLR_STOP_DET,Read this register to clear the STOP_DET interrupt (bit 9) of the IC_RAW_INTR_STAT register. Reset value: 0x0" "0,1" line.long 0x24 "IC_CLR_START_DET,Clear START_DET Interrupt Register" hexmask.long 0x24 1.--31. 1. "RSVD_IC_CLR_START_DET,IC_CLR_START_DET Reserved bits - Read Only" newline bitfld.long 0x24 0. "CLR_START_DET,Read this register to clear the START_DET interrupt (bit 10) of the IC_RAW_INTR_STAT register. Reset value: 0x0" "0,1" line.long 0x28 "IC_CLR_GEN_CALL,Clear GEN_CALL Interrupt Register" hexmask.long 0x28 1.--31. 1. "RSVD_IC_CLR_GEN_CALL,IC_CLR_GEN_CALL Reserved bits - Read Only" newline bitfld.long 0x28 0. "CLR_GEN_CALL,Read this register to clear the GEN_CALL interrupt (bit 11) of IC_RAW_INTR_STAT register. Reset value: 0x0" "0,1" group.long 0x6C++0x3 line.long 0x0 "IC_ENABLE,I2C Enable Register" hexmask.long.word 0x0 19.--31. 1. "RSVD_IC_ENABLE_2,IC_ENABLE Reserved bits - Read Only" newline rbitfld.long 0x0 18. "RSVD_SMBUS_ALERT_EN,SMBUS_ALERT_EN Register field Reserved bits - Read Only" "0,1" newline rbitfld.long 0x0 17. "RSVD_SMBUS_SUSPEND_EN,SMBUS_SUSPEND_EN Register field Reserved bits - Read Only" "0,1" newline bitfld.long 0x0 16. "SMBUS_CLK_RESET,This bit is used in SMBus Host mode to initiate the SMBus Master Clock Reset. This bit should be enabled only when Master is in idle. Whenever this bit is enabled the SMBCLK is held low for the IC_SCL_STUCK_TIMEOUT ic_clk cycles to reset.." "Master will not initates SMBUS Clock Reset..,Master initates the SMBUS Clock Reset Mechanism" newline hexmask.long.word 0x0 4.--15. 1. "RSVD_IC_ENABLE_1,RSVD_IC_ENABLE_1 Reserved bits - Read Only" newline bitfld.long 0x0 3. "SDA_STUCK_RECOVERY_ENABLE,If SDA is stuck at low indicated through the TX_ABORT interrupt (IC_TX_ABRT_SOURCE[17]) then this bit is used as a control knob to initiate the SDA Recovery Mechanism (that is send at most 9 SCL clocks and STOP to release the.." "Master disabled the SDA stuck at low recovery..,Master initates the SDA stuck at low recovery.." newline bitfld.long 0x0 2. "TX_CMD_BLOCK,In Master mode: - 1'b1: Blocks the transmission of data on I2C bus even if Tx FIFO has data to transmit. - 1'b0: The transmission of data starts on I2C bus automatically as soon as the first data is available in the Tx FIFO. Note: To block.." "Tx Command execution not blocked,Tx Command execution blocked" newline bitfld.long 0x0 1. "ABORT,When set the controller initiates the transfer abort. - 0: ABORT not initiated or ABORT done - 1: ABORT operation in progress The software can abort the I2C transfer in master mode by setting this bit. The software can set this bit only when.." "ABORT operation not in progress,ABORT operation in progress" newline bitfld.long 0x0 0. "ENABLE,Controls whether the DW_apb_i2c is enabled. - 0: Disables DW_apb_i2c (TX and RX FIFOs are held in an erased state) - 1: Enables DW_apb_i2c Software can disable DW_apb_i2c while it is active. However it is important that care be taken to ensure.." "I2C is disabled,I2C is enabled" rgroup.long 0x70++0xB line.long 0x0 "IC_STATUS,I2C Status Register This is a read-only register used to indicate the current transfer status and FIFO status. The status register may be read at any time. None of the bits in this register request an interrupt. When the I2C is disabled by.." hexmask.long.word 0x0 21.--31. 1. "RSVD_IC_STATUS_2,IC_STATUS Reserved bits - Read Only" newline bitfld.long 0x0 20. "RSVD_SMBUS_ALERT_STATUS,SMBUS_ALERT_STATUS Register field Reserved bits - Read Only" "0,1" newline bitfld.long 0x0 19. "RSVD_SMBUS_SUSPEND_STATUS,SMBUS_SUSPEND_STATUS Register field Reserved bits - Read Only" "0,1" newline bitfld.long 0x0 18. "SMBUS_SLAVE_ADDR_RESOLVED,This bit indicates whether the slave address (ic_sar) is resolved by the ARP Master. Reset value: 0x0. 0x1: SMBUS Slave Address is Resolved. 0x0: SMBUS Slave Address is not Resolved." "SMBUS Slave Address is not Resolved,SMBUS Slave Address is Resolved" newline bitfld.long 0x0 17. "SMBUS_SLAVE_ADDR_VALID,This bit indicates whether the slave address (ic_sar) is valid or not. Reset value: IC_PERSISTANT_SLV_ADDR_DEFAULT 0x1: SMBUS Slave Address is Valid. 0x0: SMBUS SLave Address is not valid." "SMBUS SLave Address is not valid,SMBUS Slave Address is Valid" newline bitfld.long 0x0 16. "SMBUS_QUICK_CMD_BIT,This bit indicates the R/W bit of the Quick command received. This bit will be cleared after the user has read this bit. Reset value: 0x0. 0x1: SMBUS QUICK CMD Read/write is set to 1. 0x0: SMBUS QUICK CMD Read/write is set to 0." "SMBUS QUICK CMD Read/write is set to 0,SMBUS QUICK CMD Read/write is set to 1" newline hexmask.long.byte 0x0 12.--15. 1. "RSVD_IC_STATUS_1,RSVD_IC_STATUS_1 Reserved bits - Read Only" newline bitfld.long 0x0 11. "SDA_STUCK_NOT_RECOVERED,This bit indicates that SDA stuck at low is not recovered after the recovery mechanism. In Slave mode this register bit is not applicable. Reset value: 0x0. 0x1: SDA Stuck at low is recovered after recovery mechanism. 0x0: SDA.." "SDA Stuck at low is not recovered after recovery..,SDA Stuck at low is recovered after recovery.." newline bitfld.long 0x0 10. "RSVD_SLV_HOLD_RX_FIFO_FULL,SLV_HOLD_RX_FIFO_FULL Register field Reserved bits - Read Only" "0,1" newline bitfld.long 0x0 9. "RSVD_SLV_HOLD_TX_FIFO_EMPTY,SLV_HOLD_TX_FIFO_EMPTY Regsiter field Reserved bits - Read Only" "0,1" newline bitfld.long 0x0 8. "RSVD_MST_HOLD_RX_FIFO_FULL,MST_HOLD_RX_FIFO_FULL Register field Reserved bits - Read Only" "0,1" newline bitfld.long 0x0 7. "RSVD_MST_HOLD_TX_FIFO_EMPTY,MST_HOLD_TX_FIFO_EMPTY Register field Reserved bits - Read Only" "0,1" newline bitfld.long 0x0 6. "SLV_ACTIVITY,Slave FSM Activity Status. When the Slave Finite State Machine (FSM) is not in the IDLE state this bit is set. - 0: Slave FSM is in IDLE state so the Slave part of DW_apb_i2c is not Active - 1: Slave FSM is not in IDLE state so the Slave.." "Slave is idle,Slave not idle" newline bitfld.long 0x0 5. "MST_ACTIVITY,Master FSM Activity Status. When the Master Finite State Machine (FSM) is not in the IDLE state this bit is set. - 0: Master FSM is in IDLE state so the Master part of DW_apb_i2c is not Active - 1: Master FSM is not in IDLE state so the.." "Master is idle,Master not idle" newline bitfld.long 0x0 4. "RFF,Receive FIFO Completely Full. When the receive FIFO is completely full this bit is set. When the receive FIFO contains one or more empty location this bit is cleared. - 0: Receive FIFO is not full - 1: Receive FIFO is full Reset value: 0x0 0x1: Rx.." "Rx FIFO not full,Rx FIFO is full" newline bitfld.long 0x0 3. "RFNE,Receive FIFO Not Empty. This bit is set when the receive FIFO contains one or more entries; it is cleared when the receive FIFO is empty. - 0: Receive FIFO is empty - 1: Receive FIFO is not empty Reset value: 0x0 0x0: Rx FIFO is empty 0x1: Rx FIFO.." "Rx FIFO is empty,Rx FIFO not empty" newline bitfld.long 0x0 2. "TFE,Transmit FIFO Completely Empty. When the transmit FIFO is completely empty this bit is set. When it contains one or more valid entries this bit is cleared. This bit field does not request an interrupt. - 0: Transmit FIFO is not empty - 1: Transmit.." "Tx FIFO not empty,Tx FIFO is empty" newline bitfld.long 0x0 1. "TFNF,Transmit FIFO Not Full. Set when the transmit FIFO contains one or more empty locations and is cleared when the FIFO is full. - 0: Transmit FIFO is full - 1: Transmit FIFO is not full Reset value: 0x1 0x0: Tx FIFO is full 0x1: Tx FIFO not full" "Tx FIFO is full,Tx FIFO not full" newline bitfld.long 0x0 0. "ACTIVITY,I2C Activity Status. Reset value: 0x0 0x1: I2C is active 0x0: I2C is idle" "I2C is idle,I2C is active" line.long 0x4 "IC_TXFLR,I2C Transmit FIFO Level Register This register contains the number of valid data entries in the transmit FIFO buffer. It is cleared whenever: - The I2C is disabled - There is a transmit abort - that is. TX_ABRT bit is set in the IC_RAW_INTR_STAT.." hexmask.long 0x4 5.--31. 1. "RSVD_TXFLR,TXFLR Register field Reserved bits - Read Only" newline hexmask.long.byte 0x4 0.--4. 1. "TXFLR,Transmit FIFO Level. Contains the number of valid data entries in the transmit FIFO. Reset value: 0x0" line.long 0x8 "IC_RXFLR,I2C Receive FIFO Level Register This register contains the number of valid data entries in the receive FIFO buffer. It is cleared whenever: - The I2C is disabled - Whenever there is a transmit abort caused by any of the events tracked in.." hexmask.long 0x8 5.--31. 1. "RSVD_RXFLR,RXFLR Reserved bits - Read Only" newline hexmask.long.byte 0x8 0.--4. 1. "RXFLR,Receive FIFO Level. Contains the number of valid data entries in the receive FIFO. Reset value: 0x0" group.long 0x7C++0x3 line.long 0x0 "IC_SDA_HOLD,I2C SDA Hold Time Length Register The bits [15:0] of this register are used to control the hold time of SDA during transmit in both slave and master mode (after SCL goes from HIGH to LOW). The bits [23:16] of this register are used to extend.." hexmask.long.byte 0x0 24.--31. 1. "RSVD_IC_SDA_HOLD,IC_SDA_HOLD Reserved bits - Read Only" newline hexmask.long.byte 0x0 16.--23. 1. "IC_SDA_RX_HOLD,Sets the required SDA hold time in units of ic_clk period when DW_apb_i2c acts as a receiver. Reset value: IC_DEFAULT_SDA_HOLD[23:16]." newline hexmask.long.word 0x0 0.--15. 1. "IC_SDA_TX_HOLD,Sets the required SDA hold time in units of ic_clk period when DW_apb_i2c acts as a transmitter. Reset value: IC_DEFAULT_SDA_HOLD[15:0]." rgroup.long 0x80++0x3 line.long 0x0 "IC_TX_ABRT_SOURCE,I2C Transmit Abort Source Register This register has 32 bits that indicate the source of the TX_ABRT bit. Except for Bit 9. this register is cleared whenever the IC_CLR_TX_ABRT register or the IC_CLR_INTR register is read. To clear Bit.." hexmask.long.word 0x0 23.--31. 1. "TX_FLUSH_CNT,This field indicates the number of Tx FIFO Data Commands which are flushed due to TX_ABRT interrupt. It is cleared whenever I2C is disabled. Reset value: 0x0 Role of DW_apb_i2c: Master-Transmitter or Slave-Transmitter" newline bitfld.long 0x0 21.--22. "RSVD_IC_TX_ABRT_SOURCE,IC_TX_ABRT_SOURCE Reserved bits - Read Only" "0,1,2,3" newline bitfld.long 0x0 18.--20. "RSVD_ABRT_DEVICE_WRITE,ABRT_DEVICE_WRITE Register field Reserved bits - Read Only" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 17. "ABRT_SDA_STUCK_AT_LOW,This is a master-mode-only bit. Master detects the SDA Stuck at low for the IC_SDA_STUCK_AT_LOW_TIMEOUT value of ic_clks. Reset value: 0x0 Role of DW_apb_i2c: Master 0x1: This abort is generated because of Sda stuck at low for.." "This abort is not generated,This abort is generated because of Sda stuck at.." newline bitfld.long 0x0 16. "ABRT_USER_ABRT,This is a master-mode-only bit. Master has detected the transfer abort (IC_ENABLE[1]) Reset value: 0x0 Role of DW_apb_i2c: Master-Transmitter 0x1: Transfer abort detected by master 0x0: Transfer abort detected by master- scenario not present" "Transfer abort detected by master,Transfer abort detected by master" newline bitfld.long 0x0 15. "ABRT_SLVRD_INTX,1: When the processor side responds to a slave mode request for data to be transmitted to a remote master and user writes a 1 in CMD (bit 8) of IC_DATA_CMD register. Reset value: 0x0 Role of DW_apb_i2c: Slave-Transmitter 0x1: Slave trying.." "Slave trying to transmit to remote master in..,Slave trying to transmit to remote master in.." newline bitfld.long 0x0 14. "ABRT_SLV_ARBLOST,This field indicates that a Slave has lost the bus while transmitting data to a remote master. IC_TX_ABRT_SOURCE[12] is set at the same time. Note: Even though the slave never 'owns' the bus something could go wrong on the bus. This is.." "Slave lost arbitration to remote master,Slave lost arbitration to remote master" newline bitfld.long 0x0 13. "ABRT_SLVFLUSH_TXFIFO,This field specifies that the Slave has received a read command and some data exists in the TX FIFO so the slave issues a TX_ABRT interrupt to flush old data in TX FIFO. Reset value: 0x0 Role of DW_apb_i2c: Slave-Transmitter 0x1:.." "Slave flushes existing data in TX-FIFO upon..,Slave flushes existing data in TX-FIFO upon.." newline bitfld.long 0x0 12. "ARB_LOST,This field specifies that the Master has lost arbitration or if IC_TX_ABRT_SOURCE[14] is also set then the slave transmitter has lost arbitration. Reset value: 0x0 Role of DW_apb_i2c: Master-Transmitter or Slave-Transmitter 0x1: Master or.." "Master or Slave-Transmitter lost arbitration,Master or Slave-Transmitter lost arbitration" newline bitfld.long 0x0 11. "ABRT_MASTER_DIS,This field indicates that the User tries to initiate a Master operation with the Master mode disabled. Reset value: 0x0 Role of DW_apb_i2c: Master-Transmitter or Master-Receiver 0x1: User intitating master operation when MASTER disabled.." "User initiating master operation when MASTER..,User intitating master operation when MASTER.." newline bitfld.long 0x0 10. "ABRT_10B_RD_NORSTRT,This field indicates that the restart is disabled (IC_RESTART_EN bit (IC_CON[5]) =0) and the master sends a read command in 10-bit addressing mode. Reset value: 0x0 Role of DW_apb_i2c: Master-Receiver 0x1: Master trying to read in.." "Master not trying to read in 10Bit addressing..,Master trying to read in 10Bit addressing mode.." newline bitfld.long 0x0 9. "ABRT_SBYTE_NORSTRT,To clear Bit 9 the source of the ABRT_SBYTE_NORSTRT must be fixed first; restart must be enabled (IC_CON[5]=1) the SPECIAL bit must be cleared (IC_TAR[11]) or the GC_OR_START bit must be cleared (IC_TAR[10]). Once the source of the.." "User trying to send START byte when RESTART..,User trying to send START byte when RESTART.." newline bitfld.long 0x0 8. "ABRT_HS_NORSTRT,This field indicates that the restart is disabled (IC_RESTART_EN bit (IC_CON[5]) =0) and the user is trying to use the master to transfer data in High Speed mode. Reset value: 0x0 Role of DW_apb_i2c: Master-Transmitter or Master-Receiver.." "User trying to switch Master to HS mode when..,User trying to switch Master to HS mode when.." newline bitfld.long 0x0 7. "ABRT_SBYTE_ACKDET,This field indicates that the Master has sent a START Byte and the START Byte was acknowledged (wrong behavior). Reset value: 0x0 Role of DW_apb_i2c: Master 0x1: ACK detected for START byte 0x0: ACK detected for START byte- scenario not.." "ACK detected for START byte,ACK detected for START byte" newline bitfld.long 0x0 6. "ABRT_HS_ACKDET,This field indicates that the Master is in High Speed mode and the High Speed Master code was acknowledged (wrong behavior). Reset value: 0x0 Role of DW_apb_i2c: Master 0x1: HS Master code ACKed in HS Mode 0x0: HS Master code ACKed in HS.." "HS Master code ACKed in HS Mode,HS Master code ACKed in HS Mode" newline bitfld.long 0x0 5. "ABRT_GCALL_READ,This field indicates that DW_apb_i2c in the master mode has sent a General Call but the user programmed the byte following the General Call to be a read from the bus (IC_DATA_CMD[9] is set to 1). Reset value: 0x0 Role of DW_apb_i2c:.." "GCALL is followed by read from bus-scenario not..,GCALL is followed by read from bus" newline bitfld.long 0x0 4. "ABRT_GCALL_NOACK,This field indicates that DW_apb_i2c in master mode has sent a General Call and no slave on the bus acknowledged the General Call. Reset value: 0x0 Role of DW_apb_i2c: Master-Transmitter 0x1: GCALL not ACKed by any slave 0x0: GCALL not.." "GCALL not ACKed by any slave-scenario not present,GCALL not ACKed by any slave" newline bitfld.long 0x0 3. "ABRT_TXDATA_NOACK,This field indicates the master-mode only bit. When the master receives an acknowledgement for the address but when it sends data byte(s) following the address it did not receive an acknowledge from the remote slave(s). Reset value:.." "Transmitted data non-ACKed by addressed..,Transmitted data not ACKed by addressed slave" newline bitfld.long 0x0 2. "ABRT_10ADDR2_NOACK,This field indicates that the Master is in 10-bit address mode and that the second address byte of the 10-bit address was not acknowledged by any slave. Reset value: 0x0 Role of DW_apb_i2c: Master-Transmitter or Master-Receiver 0x1:.." "This abort is not generated,Byte 2 of 10Bit Address not ACKed by any slave" newline bitfld.long 0x0 1. "ABRT_10ADDR1_NOACK,This field indicates that the Master is in 10-bit address mode and the first 10-bit address byte was not acknowledged by any slave. Reset value: 0x0 Role of DW_apb_i2c: Master-Transmitter or Master-Receiver 0x1: Byte 1 of 10Bit Address.." "This abort is not generated,Byte 1 of 10Bit Address not ACKed by any slave" newline bitfld.long 0x0 0. "ABRT_7B_ADDR_NOACK,This field indicates that the Master is in 7-bit addressing mode and the address sent was not acknowledged by any slave. Reset value: 0x0 Role of DW_apb_i2c: Master-Transmitter or Master-Receiver 0x1: This abort is generated because of.." "This abort is not generated,This abort is generated because of NOACK for.." group.long 0x88++0x13 line.long 0x0 "IC_DMA_CR,DMA Control Register This register is only valid when DW_apb_i2c is configured with a set of DMA Controller interface signals (IC_HAS_DMA = 1). When DW_apb_i2c is not configured for DMA operation. this register does not exist and writing to the.." hexmask.long 0x0 2.--31. 1. "RSVD_IC_DMA_CR_2_31,RSVD_IC_DMA_CR_2_31 Reserved bits - Read Only" newline bitfld.long 0x0 1. "TDMAE,Transmit DMA Enable. This bit enables/disables the transmit FIFO DMA channel. Reset value: 0x0 0x0: transmit FIFO DMA channel disabled 0x1: Transmit FIFO DMA channel enabled" "transmit FIFO DMA channel disabled,Transmit FIFO DMA channel enabled" newline bitfld.long 0x0 0. "RDMAE,Receive DMA Enable. This bit enables/disables the receive FIFO DMA channel. Reset value: 0x0 0x0: Receive FIFO DMA channel disabled 0x1: Receive FIFO DMA channel enabled" "Receive FIFO DMA channel disabled,Receive FIFO DMA channel enabled" line.long 0x4 "IC_DMA_TDLR,DMA Transmit Data Level Register This register is only valid when the DW_apb_i2c is configured with a set of DMA interface signals (IC_HAS_DMA = 1). When DW_apb_i2c is not configured for DMA operation. this register does not exist; writing to.." hexmask.long 0x4 4.--31. 1. "RSVD_DMA_TDLR,DMA_TDLR Reserved bits - Read Only" newline hexmask.long.byte 0x4 0.--3. 1. "DMATDL,Transmit Data Level. This bit field controls the level at which a DMA request is made by the transmit logic. It is equal to the watermark level; that is the dma_tx_req signal is generated when the number of valid data entries in the transmit FIFO.." line.long 0x8 "IC_DMA_RDLR,I2C Receive Data Level Register This register is only valid when DW_apb_i2c is configured with a set of DMA interface signals (IC_HAS_DMA = 1). When DW_apb_i2c is not configured for DMA operation. this register does not exist; writing to its.." hexmask.long 0x8 4.--31. 1. "RSVD_DMA_RDLR,DMA_RDLR Reserved bits - Read Only" newline hexmask.long.byte 0x8 0.--3. 1. "DMARDL,Receive Data Level. This bit field controls the level at which a DMA request is made by the receive logic. The watermark level = DMARDL+1; that is dma_rx_req is generated when the number of valid data entries in the receive FIFO is equal to or.." line.long 0xC "IC_SDA_SETUP,I2C SDA Setup Register This register controls the amount of time delay (in terms of number of ic_clk clock periods) introduced in the rising edge of SCL - relative to SDA changing - when DW_apb_i2c services a read request in a.." hexmask.long.tbyte 0xC 8.--31. 1. "RSVD_IC_SDA_SETUP,IC_SDA_SETUP Reserved bits - Read Only" newline hexmask.long.byte 0xC 0.--7. 1. "SDA_SETUP,SDA Setup. It is recommended that if the required delay is 1000ns then for an ic_clk frequency of 10 MHz IC_SDA_SETUP should be programmed to a value of 11. IC_SDA_SETUP must be programmed with a minimum value of 2. Reset value: 0x64 but can.." line.long 0x10 "IC_ACK_GENERAL_CALL,I2C ACK General Call Register The register controls whether DW_apb_i2c responds with a ACK or NACK when it receives an I2C General Call address. This register is applicable only when the DW_apb_i2c is in slave mode." hexmask.long 0x10 1.--31. 1. "RSVD_IC_ACK_GEN_1_31,RSVD_IC_ACK_GEN_1_31 Reserved bits - Read Only" newline bitfld.long 0x10 0. "ACK_GEN_CALL,ACK General Call. When set to 1 DW_apb_i2c responds with a ACK (by asserting ic_data_oe) when it receives a General Call. Otherwise DW_apb_i2c responds with a NACK (by negating ic_data_oe). Reset value: 0x1 but can be hardcoded by setting.." "Generate NACK for General Call,Generate ACK for a General Call" rgroup.long 0x9C++0x3 line.long 0x0 "IC_ENABLE_STATUS,I2C Enable Status Register The register is used to report the DW_apb_i2c hardware status when the IC_ENABLE[0] register is set from 1 to 0; that is. when DW_apb_i2c is disabled. If IC_ENABLE[0] has been set to 1. bits 2:1 are forced to.." hexmask.long 0x0 3.--31. 1. "RSVD_IC_ENABLE_STATUS,IC_ENABLE_STATUS Reserved bits - Read Only" newline bitfld.long 0x0 2. "SLV_RX_DATA_LOST,Slave Received Data Lost. This bit indicates if a Slave-Receiver operation has been aborted with at least one data byte received from an I2C transfer due to the setting bit 0 of IC_ENABLE from 1 to 0. When read as 1 DW_apb_i2c is deemed.." "Slave RX Data is not lost,Slave RX Data is lost" newline bitfld.long 0x0 1. "SLV_DISABLED_WHILE_BUSY,Slave Disabled While Busy (Transmit Receive). This bit indicates if a potential or active Slave operation has been aborted due to the setting bit 0 of the IC_ENABLE register from 1 to 0. This bit is set when the CPU writes a 0 to.." "Slave is disabled when it is idle,Slave is disabled when it is active" newline bitfld.long 0x0 0. "IC_EN,ic_en Status. This bit always reflects the value driven on the output port ic_en. - When read as 1 DW_apb_i2c is deemed to be in an enabled state. - When read as 0 DW_apb_i2c is deemed completely inactive. Note: The CPU can safely read this bit.." "I2C disabled,I2C enabled" group.long 0xA0++0x3 line.long 0x0 "IC_FS_SPKLEN,I2C SS. FS or FM+ spike suppression limit This register is used to store the duration. measured in ic_clk cycles. of the longest spike that is filtered out by the spike suppression logic w hen the component is operating in SS. FS or FM+.." hexmask.long.tbyte 0x0 8.--31. 1. "RSVD_IC_FS_SPKLEN,IC_FS_SPKLEN Reserved bits - Read Only" newline hexmask.long.byte 0x0 0.--7. 1. "IC_FS_SPKLEN,This register must be set before any I2C bus transaction can take place to ensure stable operation. This register sets the duration measured in ic_clk cycles of the longest spike in the SCL or SDA lines that will be filtered out by the.." rgroup.long 0xA8++0x3 line.long 0x0 "IC_CLR_RESTART_DET,Clear RESTART_DET Interrupt Register" hexmask.long 0x0 1.--31. 1. "RSVD_IC_CLR_RESTART_DET,IC_CLR_RESTART_DET Reserved bits - Read Only" newline bitfld.long 0x0 0. "CLR_RESTART_DET,Read this register to clear the RESTART_DET interrupt (bit 12) of IC_RAW_INTR_STAT register. Reset value: 0x0" "0,1" group.long 0xAC++0x7 line.long 0x0 "IC_SCL_STUCK_AT_LOW_TIMEOUT,I2C SCL Stuck at Low Timeout This register is used to store the duration. measured in ic_clk cycles. used to Generate an Interrupt (SCL_STUCK_AT_LOW) if SCL is held low for the IC_SCL_STUCK_LOW_TIMEOUT duration." hexmask.long 0x0 0.--31. 1. "IC_SCL_STUCK_LOW_TIMEOUT,DW_apb_i2c generate the interrupt to indicate SCL stuck at low (SCL_STUCK_AT_LOW) if it detects the SCL stuck at low for the IC_SCL_STUCK_LOW_TIMEOUT in units of ic_clk period. This register can be written only when the I2C.." line.long 0x4 "IC_SDA_STUCK_AT_LOW_TIMEOUT,I2C SDA Stuck at Low Timeout This register is used to store the duration. measured in ic_clk cycles. used to Recover the Data (SDA) line through sending SCL pulses if SDA is held low for the mentioned duration." hexmask.long 0x4 0.--31. 1. "IC_SDA_STUCK_LOW_TIMEOUT,DW_apb_i2c initiates the recovery of SDA line through enabling the SDA_STUCK_RECOVERY_EN (IC_ENABLE[3]) register bit if it detects the SDA stuck at low for the IC_SDA_STUCK_LOW_TIMEOUT in units of ic_clk period. Reset value:.." rgroup.long 0xB4++0x3 line.long 0x0 "IC_CLR_SCL_STUCK_DET,Clear SCL Stuck at Low Detect Interrupt Register" hexmask.long 0x0 1.--31. 1. "RSVD_CLR_SCL_STUCK_DET,CLR_SCL_STUCK_DET Reserved bits - Read Only" newline bitfld.long 0x0 0. "CLR_SCL_STUCK_DET,Read this register to clear the SCL_STUCT_AT_LOW interrupt (bit 15) of the IC_RAW_INTR_STAT register. Reset value: 0x0" "0,1" group.long 0xBC++0xB line.long 0x0 "IC_SMBUS_CLK_LOW_SEXT,SMBus Slave Clock Extend Timeout Register This Register contains the Timeout value used to determine the Slave Clock Extend Timeout in one transfer (from START to STOP). This Register can be written only when the DW_apb_i2c is.." hexmask.long 0x0 0.--31. 1. "SMBUS_CLK_LOW_SEXT_TIMEOUT,This field is used to detect the Slave Clock Extend timeout (tLOW:SEXT) in master mode extended by the slave device in one message from the initial START to the STOP. The values in this register are in units of ic_clk period." line.long 0x4 "IC_SMBUS_CLK_LOW_MEXT,SMBus Master Clock Extend Timeout Register This Register contains the Timeout value used to determine the Master Clock Extend Timeout in one byte of transfer. This Register can be written only when the DW_apb_i2c is disabled. which.." hexmask.long 0x4 0.--31. 1. "SMBUS_CLK_LOW_MEXT_TIMEOUT,This field is used to detect the Master extend SMBus clock (SCLK) timeout defined from START-to-ACK ACK-to-ACK or ACK-to-STOP in Master mode. The values in this register are in units of ic_clk period. Reset value:.." line.long 0x8 "IC_SMBUS_THIGH_MAX_IDLE_COUNT,SMBus Master THigh MAX Bus-idle count Register This register programs the Bus-idle time period used when a master has been dynamically added to the bus or when a master has generated a clock reset on the bus. This register.." hexmask.long.word 0x8 16.--31. 1. "RSVD_SMBUS_THIGH_MAX_BUS_IDLE_CNT,SMBUS_THIGH_MAX_BUS_IDLE_CNT Reserved bits - Read Only" newline hexmask.long.word 0x8 0.--15. 1. "SMBUS_THIGH_MAX_BUS_IDLE_CNT,This field is used to set the required Bus-Idle time period used when a master has been dynamically added to the bus and may not have detected a state transition on the SMBCLK or SMBDAT lines. In this case the master must.." rgroup.long 0xC8++0x3 line.long 0x0 "IC_SMBUS_INTR_STAT,SMBUS Interrupt Status Register Each bit in this register has a corresponding mask bit in the IC_SMBUS_INTR_MASK register. These bits are cleared by writing the matching SMBus interrupt clear register(IC_CLR_SMBUS_INTR) bits. The.." hexmask.long.tbyte 0x0 11.--31. 1. "RSVD_IC_SMBUS_INTR_STAT,IC_SMBUS_INTR_STAT Reserved bits - Read Only" newline bitfld.long 0x0 10. "RSVD_R_SMBUS_ALERT_DET,R_SMBUS_ALERT_DET Register field Reserved bits - Read Only" "0,1" newline bitfld.long 0x0 9. "RSVD_R_SMBUS_SUSPEND_DET,R_SMBUS_SUSPEND_DET Register field Reserved bits - Read Only" "0,1" newline bitfld.long 0x0 8. "R_SLV_RX_PEC_NACK,See IC_SMBUS_INTR_RAW_STATUS for a detailed description of R_SLV_RX_PEC_NACK bit. Reset value: 0x0 0x1: SLV_RX_PEC_NACK interrupt is active 0x0: SLV_RX_PEC_NACK interrupt is inactive" "SLV_RX_PEC_NACK interrupt is inactive,SLV_RX_PEC_NACK interrupt is active" newline bitfld.long 0x0 7. "R_ARP_ASSGN_ADDR_CMD_DET,See IC_SMBUS_INTR_RAW_STATUS for a detailed description of R_ARP_ASSGN_ADDR_CMD_DET bit. Reset value: 0x0 0x1: ARP_ASSGN_ADDR_CMD_DET interrupt is active 0x0: ARP_ASSGN_ADDR_CMD_DET interrupt is inactive" "ARP_ASSGN_ADDR_CMD_DET interrupt is inactive,ARP_ASSGN_ADDR_CMD_DET interrupt is active" newline bitfld.long 0x0 6. "R_ARP_GET_UDID_CMD_DET,See IC_SMBUS_INTR_RAW_STATUS for a detailed description of R_ARP_GET_UDID_CMD_DET bit. Reset value: 0x0 0x1: ARP_GET_UDID_CMD_DET interrupt is active 0x0: ARP_GET_UDID_CMD_DET interrupt is inactive" "ARP_GET_UDID_CMD_DET interrupt is inactive,ARP_GET_UDID_CMD_DET interrupt is active" newline bitfld.long 0x0 5. "R_ARP_RST_CMD_DET,See IC_SMBUS_INTR_RAW_STATUS for a detailed description of R_ARP_RST_CMD_DET bit. Reset value: 0x0 0x1: ARP_RST_CMD_DET interrupt is active 0x0: ARP_RST_CMD_DET interrupt is inactive" "ARP_RST_CMD_DET interrupt is inactive,ARP_RST_CMD_DET interrupt is active" newline bitfld.long 0x0 4. "R_ARP_PREPARE_CMD_DET,See IC_SMBUS_INTR_RAW_STATUS for a detailed description of R_ARP_PREPARE_CMD_DET bit. Reset value: 0x0 0x1: ARP_PREPARE_CMD_DET interrupt is active 0x0: ARP_PREPARE_CMD_DET interrupt is inactive" "ARP_PREPARE_CMD_DET interrupt is inactive,ARP_PREPARE_CMD_DET interrupt is active" newline bitfld.long 0x0 3. "R_HOST_NOTIFY_MST_DET,See IC_SMBUS_INTR_RAW_STATUS for a detailed description of R_HOST_NOTIFY_MST_DET bit. Reset value: 0x0 0x1: HOST_NOTIFY_MST_DET interrupt is active 0x0: HOST_NOTIFY_MST_DET interrupt is inactive" "HOST_NOTIFY_MST_DET interrupt is inactive,HOST_NOTIFY_MST_DET interrupt is active" newline bitfld.long 0x0 2. "R_QUICK_CMD_DET,See IC_SMBUS_INTR_RAW_STATUS for a detailed description of R_QUICK_CMD_DET bit. Reset value: 0x0 0x1: QUICK_CMD_DET interrupt is active 0x0: QUICK_CMD_DET interrupt is inactive" "QUICK_CMD_DET interrupt is inactive,QUICK_CMD_DET interrupt is active" newline bitfld.long 0x0 1. "R_MST_CLOCK_EXTND_TIMEOUT,See IC_SMBUS_INTR_RAW_STATUS for a detailed description of R_MST_CLOCK_EXTND_TIMEOUT bit. Reset value: 0x0 0x1: MST_CLOCK_EXTND_TIMEOUT interrupt is active 0x0: MST_CLOCK_EXTND_TIMEOUT interrupt is inactive" "MST_CLOCK_EXTND_TIMEOUT interrupt is inactive,MST_CLOCK_EXTND_TIMEOUT interrupt is active" newline bitfld.long 0x0 0. "R_SLV_CLOCK_EXTND_TIMEOUT,See IC_SMBUS_INTR_RAW_STATUS for a detailed description of R_SLV_CLOCK_EXTND_TIMEOUT bit. Reset value: 0x0 0x1: SLV_CLOCK_EXTND_TIMEOUT interrupt is active 0x0: SLV_CLOCK_EXTND_TIMEOUT interrupt is inactive" "SLV_CLOCK_EXTND_TIMEOUT interrupt is inactive,SLV_CLOCK_EXTND_TIMEOUT interrupt is active" group.long 0xCC++0x3 line.long 0x0 "IC_SMBUS_INTR_MASK,SMBus Interrupt Mask Register" hexmask.long.tbyte 0x0 11.--31. 1. "RSVD_IC_SMBUS_INTR_MASK,IC_SMBUS_INTR_MASK Reserved bits - Read Only" newline rbitfld.long 0x0 9.--10. "RSVD_IC_SMBUS_INTR_MASK_9_10,RSVD_IC_SMBUS_INTR_MASK_9_10 Register field Reserved bits." "0,1,2,3" newline bitfld.long 0x0 8. "M_SLV_RX_PEC_NACK,This bit masks the R_SLV_RX_PEC_NACK interrupt in IC_SMBUS_INTR_STAT register. Reset value: 0x1 0x1: SLV_RX_PEC_NACK interrupt is unmasked 0x0: SLV_RX_PEC_NACK interrupt is masked" "SLV_RX_PEC_NACK interrupt is masked,SLV_RX_PEC_NACK interrupt is unmasked" newline bitfld.long 0x0 7. "M_ARP_ASSGN_ADDR_CMD_DET,This bit masks the R_ARP_ASSGN_ADDR_CMD_DET interrupt in IC_SMBUS_INTR_STAT register. Reset value: 0x1 0x1: ARP_ASSGN_ADDR_CMD_DET interrupt is unmasked 0x0: ARP_ASSGN_ADDR_CMD_DET interrupt is masked" "ARP_ASSGN_ADDR_CMD_DET interrupt is masked,ARP_ASSGN_ADDR_CMD_DET interrupt is unmasked" newline bitfld.long 0x0 6. "M_ARP_GET_UDID_CMD_DET,This bit masks the R_ARP_GET_UDID_CMD_DET interrupt in IC_SMBUS_INTR_STAT register. Reset value: 0x1 0x1: ARP_GET_UDID_CMD_DET interrupt is unmasked 0x0: ARP_GET_UDID_CMD_DET interrupt is masked" "ARP_GET_UDID_CMD_DET interrupt is masked,ARP_GET_UDID_CMD_DET interrupt is unmasked" newline bitfld.long 0x0 5. "M_ARP_RST_CMD_DET,This bit masks the R_ARP_RST_CMD_DET interrupt in IC_SMBUS_INTR_STAT register. Reset value: 0x1 0x1: ARP_RST_CMD_DET interrupt is unmasked 0x0: ARP_RST_CMD_DET interrupt is masked" "ARP_RST_CMD_DET interrupt is masked,ARP_RST_CMD_DET interrupt is unmasked" newline bitfld.long 0x0 4. "M_ARP_PREPARE_CMD_DET,This bit masks the R_ARP_PREPARE_CMD_DET interrupt in IC_SMBUS_INTR_STAT register. Reset value: 0x1 0x1: ARP_PREPARE_CMD_DET interrupt is unmasked 0x0: ARP_PREPARE_CMD_DET interrupt is masked" "ARP_PREPARE_CMD_DET interrupt is masked,ARP_PREPARE_CMD_DET interrupt is unmasked" newline bitfld.long 0x0 3. "M_HOST_NOTIFY_MST_DET,This bit masks the R_HOST_NOTIFY_MST_DET interrupt in IC_SMBUS_INTR_STAT register. Reset value: 0x1 0x1: HOST_NOTIFY_MST_DET interrupt is unmasked 0x0: HOST_NOTIFY_MST_DET interrupt is masked" "HOST_NOTIFY_MST_DET interrupt is masked,HOST_NOTIFY_MST_DET interrupt is unmasked" newline bitfld.long 0x0 2. "M_QUICK_CMD_DET,This bit masks the R_QUICK_CMD_DET interrupt in IC_SMBUS_INTR_STAT register. Reset value: 0x1 0x1: QUICK_CMD_DET interrupt is unmasked 0x0: QUICK_CMD_DET interrupt is masked" "QUICK_CMD_DET interrupt is masked,QUICK_CMD_DET interrupt is unmasked" newline bitfld.long 0x0 1. "M_MST_CLOCK_EXTND_TIMEOUT,This bit masks the R_MST_CLOCK_EXTND_TIMEOUT interrupt in IC_SMBUS_INTR_STAT register. Reset value: 0x1 0x1: MST_CLOCK_EXTND_TIMEOUT interrupt is unmasked 0x0: MST_CLOCK_EXTND_TIMEOUT interrupt is masked" "MST_CLOCK_EXTND_TIMEOUT interrupt is masked,MST_CLOCK_EXTND_TIMEOUT interrupt is unmasked" newline bitfld.long 0x0 0. "M_SLV_CLOCK_EXTND_TIMEOUT,This bit masks the R_SLV_CLOCK_EXTND_TIMEOUT interrupt in IC_SMBUS_INTR_STAT register. Reset value: 0x1 0x1: SLV_CLOCK_EXTND_TIMEOUT interrupt is unmasked 0x0: SLV_CLOCK_EXTND_TIMEOUT interrupt is masked" "SLV_CLOCK_EXTND_TIMEOUT interrupt is masked,SLV_CLOCK_EXTND_TIMEOUT interrupt is unmasked" rgroup.long 0xD0++0x3 line.long 0x0 "IC_SMBUS_RAW_INTR_STAT,SMBus Raw Interrupt Status Register Unlike the IC_SMBUS_INTR_STAT register. these bits are not masked so they always show the true status of the DW_apb_i2c." hexmask.long.tbyte 0x0 11.--31. 1. "RSVD_IC_SMBUS_RAW_INTR_STAT,IC_SMBUS_RAW_INTR_STAT Reserved bits - Read Only" newline bitfld.long 0x0 10. "RSVD_SMBUS_ALERT_DET,SMBUS_ALERT_DET Register field Reserved bits - Read Only" "0,1" newline bitfld.long 0x0 9. "RSVD_SMBUS_SUSPEND_DET,SMBUS_SUSPEND_DET Register field Reserved bits - Read Only" "0,1" newline bitfld.long 0x0 8. "SLV_RX_PEC_NACK,Indicates whether a NACK has been sent due to PEC mismatch while working as ARP slave. Reset value: 0x0 0x1: SLV_RX_PEC_NACK interrupt is active 0x0: SLV_RX_PEC_NACK interrupt is inactive" "SLV_RX_PEC_NACK interrupt is inactive,SLV_RX_PEC_NACK interrupt is active" newline bitfld.long 0x0 7. "ARP_ASSGN_ADDR_CMD_DET,Indicates whether an Assign Address ARP command has been received. Reset value: 0x0 0x1: ARP_ASSGN_ADDR_CMD_DET interrupt is active 0x0: ARP_ASSGN_ADDR_CMD_DET interrupt is inactive" "ARP_ASSGN_ADDR_CMD_DET interrupt is inactive,ARP_ASSGN_ADDR_CMD_DET interrupt is active" newline bitfld.long 0x0 6. "ARP_GET_UDID_CMD_DET,Indicates whether a Get UDID ARP command has been received. Reset value: 0x0 0x1: ARP_GET_UDID_CMD_DET interrupt is active 0x0: ARP_GET_UDID_CMD_DET interrupt is inactive" "ARP_GET_UDID_CMD_DET interrupt is inactive,ARP_GET_UDID_CMD_DET interrupt is active" newline bitfld.long 0x0 5. "ARP_RST_CMD_DET,Indicates whether a General or Directed Reset ARP command has been received. Reset value: 0x0 0x1: ARP_RST_CMD_DET interrupt is active 0x0: ARP_RST_CMD_DET interrupt is inactive" "ARP_RST_CMD_DET interrupt is inactive,ARP_RST_CMD_DET interrupt is active" newline bitfld.long 0x0 4. "ARP_PREPARE_CMD_DET,Indicates whether a prepare to ARP command has been received. Reset value: 0x0 0x1: ARP_PREPARE_CMD_DET interrupt is active 0x0: ARP_PREPARE_CMD_DET interrupt is inactive" "ARP_PREPARE_CMD_DET interrupt is inactive,ARP_PREPARE_CMD_DET interrupt is active" newline bitfld.long 0x0 3. "HOST_NTFY_MST_DET,Indicates whether a Notify ARP Master ARP command has been received. Reset value: 0x0 0x1: HOST_NTFY_MST_DET interrupt is active 0x0: HOST_NTFY_MST_DET interrupt is inactive" "HOST_NTFY_MST_DET interrupt is inactive,HOST_NTFY_MST_DET interrupt is active" newline bitfld.long 0x0 2. "QUICK_CMD_DET,Indicates whether a Quick command has been received on the SMBus interface regardless of whether DW_apb_i2c is operating in slave or master mode. Enabled only when IC_SMBUS=1 is set to 1. Reset value: 0x0 0x1: Quick Command interrupt is.." "Quick Command interrupt is inactive,Quick Command interrupt is active" newline bitfld.long 0x0 1. "MST_CLOCK_EXTND_TIMEOUT,Indicates whether the Master device transaction (START-to-ACK ACK-to-ACK or ACK-to-STOP) from START to STOP exceeds IC_SMBUS_CLOCK_LOW_MEXT time with in each byte of message. This bit is enabled only when: - IC_SMBUS=1 -.." "Master Clock Extend Timeout interrupt is inactive,Master Clock Extend Timeout interrupt is active" newline bitfld.long 0x0 0. "SLV_CLOCK_EXTND_TIMEOUT,Indicates whether the transaction from Slave (i.e from START to STOP) exceeds IC_SMBUS_CLK_LOW_SEXT time. This bit is enabled only when: - IC_SMBUS=1 - IC_CON[0]=1 Reset value: 0x0 0x1: Slave Clock Extend Timeout interrupt is.." "Slave Clock Extend Timeout interrupt is inactive,Slave Clock Extend Timeout interrupt is active" wgroup.long 0xD4++0x3 line.long 0x0 "IC_CLR_SMBUS_INTR,SMBus Clear Interrupt Register" hexmask.long.tbyte 0x0 11.--31. 1. "RSVD_IC_CLR_SMBUS_INTR,IC_CLR_SMBUS_INTR Reserved bits - Read Only" newline bitfld.long 0x0 10. "RSVD_CLR_SMBUS_ALERT_DET,CLR_SMBUS_ALERT_DET Register field Reserved bits - Read Only" "0,1" newline bitfld.long 0x0 9. "RSVD_CLR_SMBUS_SUSPEND_DET,CLR_SMBUS_SUSPEND_DET Register field Reserved bits - Read Only" "0,1" newline bitfld.long 0x0 8. "CLR_SLV_RX_PEC_NACK,Write this register bit to clear the SLV_RX_PEC_NACK interrupt (bit 8) of the IC_SMBUS_RAW_INTR_STAT register. Reset value: 0x0" "0,1" newline bitfld.long 0x0 7. "CLR_ARP_ASSGN_ADDR_CMD_DET,Write this register bit to clear the ARP_ASSGN_ADDR_CMD_DET interrupt (bit 7) of the IC_SMBUS_RAW_INTR_STAT register. Reset value: 0x0" "0,1" newline bitfld.long 0x0 6. "CLR_ARP_GET_UDID_CMD_DET,Write this register bit to clear the ARP_GET_UDID_CMD_DET interrupt (bit 6) of the IC_SMBUS_RAW_INTR_STAT register. Reset value: 0x0" "0,1" newline bitfld.long 0x0 5. "CLR_ARP_RST_CMD_DET,Write this register bit to clear the ARP_RST_CMD_DET interrupt (bit 5) of the IC_SMBUS_RAW_INTR_STAT register. Reset value: 0x0" "0,1" newline bitfld.long 0x0 4. "CLR_ARP_PREPARE_CMD_DET,Write this register bit to clear the ARP_PREPARE_CMD_DET interrupt (bit 4) of the IC_SMBUS_RAW_INTR_STAT register. Reset value: 0x0" "0,1" newline bitfld.long 0x0 3. "CLR_HOST_NOTIFY_MST_DET,Write this register bit to clear the HOST_NOTIFY_MST_DET interrupt (bit 3) of the IC_SMBUS_RAW_INTR_STAT register. Reset value: 0x0" "0,1" newline bitfld.long 0x0 2. "CLR_QUICK_CMD_DET,Write this register bit to clear the QUICK_CMD_DET interrupt (bit 2) of the IC_SMBUS_RAW_INTR_STAT register. Reset value: 0x0" "0,1" newline bitfld.long 0x0 1. "CLR_MST_CLOCK_EXTND_TIMEOUT,Write this register bit to clear the MST_CLOCK_EXTND_TIMEOUT interrupt (bit 1) of the IC_SMBUS_RAW_INTR_STAT register. Reset value: 0x0" "0,1" newline bitfld.long 0x0 0. "CLR_SLV_CLOCK_EXTND_TIMEOUT,Write this register bit to clear the SLV_CLOCK_EXTND_TIMEOUT interrupt (bit 0) of the IC_SMBUS_RAW_INTR_STAT register. Reset value: 0x0" "0,1" group.long 0xDC++0x3 line.long 0x0 "IC_SMBUS_UDID_LSB,SMBUS ARP UDID LSB Register This Register can be written only when the DW_apb_i2c is disabled. which corresponds to IC_ENABLE[0] being set to 0. This register is present only if configuration parameter IC_SMBUS_ARP is set to 1. This.." hexmask.long 0x0 0.--31. 1. "SMBUS_UDID_LSB,This field is used to store the LSB 32 bit value of slave unique device identifier used in Address Resolution Protocol. Reset Value: IC_SMBUS_UDID_LSB_DEFAULT" rgroup.long 0xF4++0xB line.long 0x0 "IC_COMP_PARAM_1,Component Parameter Register 1 Note This is a constant read-only register that contains encoded information about the component's parameter settings. The reset value depends on coreConsultant parameter(s)." hexmask.long.byte 0x0 24.--31. 1. "RSVD_IC_COMP_PARAM_1,IC_COMP_PARAM_1 Reserved bits - Read Only" newline hexmask.long.byte 0x0 16.--23. 1. "TX_BUFFER_DEPTH,The value of this register is derived from the IC_TX_BUFFER_DEPTH coreConsultant parameter. - 0x00 = Reserved - 0x01 = 2 - 0x02 = 3 - ... - 0xFF = 256" newline hexmask.long.byte 0x0 8.--15. 1. "RX_BUFFER_DEPTH,The value of this register is derived from the IC_RX_BUFFER_DEPTH coreConsultant parameter. - 0x00: Reserved - 0x01: 2 - 0x02: 3 - ... - 0xFF: 256" newline bitfld.long 0x0 7. "ADD_ENCODED_PARAMS,The value of this register is derived from the IC_ADD_ENCODED_PARAMS coreConsultant parameter. Reading 1 in this bit means that the capability of reading these encoded parameters via software has been included. Otherwise the entire.." "Disables capability of reading encoded parameters,Enables capability of reading encoded parameters" newline bitfld.long 0x0 6. "HAS_DMA,The value of this register is derived from the IC_HAS_DMA coreConsultant parameter. 0x0: DMA handshaking signals are disabled 0x1: DMA handshaking signals are enabled" "DMA handshaking signals are disabled,DMA handshaking signals are enabled" newline bitfld.long 0x0 5. "INTR_IO,The value of this register is derived from the IC_INTR_IO coreConsultant parameter. 0x1: COMBINED Interrupt outputs 0x0: INDIVIDUAL Interrupt outputs" "INDIVIDUAL Interrupt outputs,COMBINED Interrupt outputs" newline bitfld.long 0x0 4. "HC_COUNT_VALUES,The value of this register is derived from the IC_HC_COUNT VALUES coreConsultant parameter. 0x0: Programmable count values for each mode. 0x1: Hard code the count values for each mode." "Programmable count values for each mode,Hard code the count values for each mode" newline bitfld.long 0x0 2.--3. "MAX_SPEED_MODE,The value of this register is derived from the IC_MAX_SPEED_MODE coreConsultant parameter. - 0x0: Reserved - 0x1: Standard - 0x2: Fast - 0x3: High 0x2: IC MAX SPEED is FAST MODE 0x3: IC MAX SPEED is HIGH MODE 0x1: IC MAX SPEED is STANDARD.." "Reserved,IC MAX SPEED is STANDARD MODE,IC MAX SPEED is FAST MODE,IC MAX SPEED is HIGH MODE" newline bitfld.long 0x0 0.--1. "APB_DATA_WIDTH,The value of this register is derived from the APB_DATA_WIDTH coreConsultant parameter. 0x0: APB data bus width is 08 bits 0x1: APB data bus width is 16 bits 0x2: APB data bus width is 32 bits 0x3: Reserved bits" "APB data bus width is 08 bits,APB data bus width is 16 bits,APB data bus width is 32 bits,Reserved bits" line.long 0x4 "IC_COMP_VERSION,I2C Component Version Register" hexmask.long 0x4 0.--31. 1. "IC_COMP_VERSION,Specific values for this register are described in the Releases Table in the DW_apb_i2c Release Notes" line.long 0x8 "IC_COMP_TYPE,I2C Component Type Register" hexmask.long 0x8 0.--31. 1. "IC_COMP_TYPE,Designware Component Type number = 0x44_57_01_40. This assigned unique hex value is constant and is derived from the two ASCII letters 'DW' followed by a 16-bit unsigned number." tree.end repeat.end endif tree.end tree "I2S (Inter-Integrated Circuit Sound)" sif (CORENAME()=="CORTEXR5F") repeat 2. (increment 1. 1.) (list ad:0xF05C0000 ad:0xF05D0000) tree "I2S_MC$1" base $2 group.long 0x0++0x27 line.long 0x0 "I2S_CTRL,'I2S Control Register'" rbitfld.long 0x0 29.--31. "RESERVED0,'Not implemented. Return '0' when read.'" "0,1,2,3,4,5,6,7" bitfld.long 0x0 28. "RSYNC_LOOP_BACK,'Loop-back configuration bit for receiver synchronization unit. When 0 (normal mode) the scki and wsi inputs of the I2S module (configured to be receiver synchronization unit) are connected to the external inputs rclki and rwsi. When 1.." "0,1" bitfld.long 0x0 27. "TSYNC_LOOP_BACK,'Loop-back configuration bit for transmitter synchronization unit. When 0 (normal mode) the scki and wsi inputs of the I2S module (configured to be transmitter synchronization unit) are connected to the external inputs tclki and twsi." "0,1" bitfld.long 0x0 26. "RSYNC_RST,'Reset for receiver synchronizing unit. Active LOW. Sampled on the rising edge of the clock.'" "0,1" bitfld.long 0x0 25. "TSYNC_RST,'Reset for transmitter synchronizing unit. Active LOW. Sampled on the rising edge of the clock.'" "0,1" newline bitfld.long 0x0 24. "RFIFO_RST,'Receive FIFO reset. When '0' receive FIFO pointers are reset to zero. Threshold level for this FIFO is unchanged. This bit is automatically set to '1' after one clock cycle. Sampled on the rising edge of the clock.'" "0,1" bitfld.long 0x0 23. "TFIFO_RST,'Transmit FIFO reset. When '0' transmit FIFO pointers are reset to zero. Threshold level for this FIFO is unchanged. This bit is automatically set to '1' after one clock cycle. Sampled on the rising edge of the clock.'" "0,1" bitfld.long 0x0 22. "R_MS,'Master (value '1') or slave (value '0') configuration bit for unit synchronizing all receivers with I2S bus. Sampled on the rising edge of the clock.'" "0,1" bitfld.long 0x0 21. "T_MS,'Master (value '1') or slave (value '0') configuration bit for unit synchronizing all transmitters with I2S bus. Sampled on the rising edge of the clock.'" "0,1" bitfld.long 0x0 20. "SFR_RST,'SFR block synchronous reset. When '0' all bits in SFR registers are reset to default values. This bit is automatically set to '1' after one clock cycle. Sampled on the rising edge of the clock.'" "0,1" newline bitfld.long 0x0 19. "LOOP_BACK_6_7,'Loop back test configuration bit. When '1' it configures channels 6 and 7 into the loop-back mode. In this mode channels 6 and 7 can work in both directions depending on configuration bits. Default value '0' causes normal operation.." "0,1" bitfld.long 0x0 18. "LOOP_BACK_4_5,'Loop back test configuration bit. When '1' it configures channels 4 and 5 into the loop-back mode. In this mode channels 4 and 5 can work in both directions depending on configuration bits. Default value '0' causes normal operation.." "0,1" bitfld.long 0x0 17. "LOOP_BACK_2_3,'Loop back test configuration bit. When '1' it configures channels 2 and 3 into the loop-back mode. In this mode channels 2 and 3 can work in both directions depending on configuration bits. Default value '0' causes normal operation.." "0,1" bitfld.long 0x0 16. "LOOP_BACK_0_1,'Loop back test configuration bit. When '1' it configures channels 0 and 1 into the loop-back mode. In this mode channels 0 and 1 can work in both directions depending on configuration bits. Default value '0' causes normal operation.." "0,1" bitfld.long 0x0 15. "TR_CFG_7,'Transmitter (value '1') or receiver (value '0') configuration bit for I2S channel 7. Sampled on the rising edge of the clock.'" "0,1" newline bitfld.long 0x0 14. "TR_CFG_6,'Transmitter (value '1') or receiver (value '0') configuration bit for I2S channel 6. Sampled on the rising edge of the clock.'" "0,1" bitfld.long 0x0 13. "TR_CFG_5,'Transmitter (value '1') or receiver (value '0') configuration bit for I2S channel 5. Sampled on the rising edge of the clock.'" "0,1" bitfld.long 0x0 12. "TR_CFG_4,'Transmitter (value '1') or receiver (value '0') configuration bit for I2S channel 4. Sampled on the rising edge of the clock.'" "0,1" bitfld.long 0x0 11. "TR_CFG_3,'Transmitter (value '1') or receiver (value '0') configuration bit for I2S channel 3. Sampled on the rising edge of the clock.'" "0,1" bitfld.long 0x0 10. "TR_CFG_2,'Transmitter (value '1') or receiver (value '0') configuration bit for I2S channel 2. Sampled on the rising edge of the clock.'" "0,1" newline bitfld.long 0x0 9. "TR_CFG_1,'Transmitter (value '1') or receiver (value '0') configuration bit for I2S channel 1. Sampled on the rising edge of the clock.'" "0,1" bitfld.long 0x0 8. "TR_CFG_0,'Transmitter (value '1') or receiver (value '0') configuration bit for I2S channel 0. Sampled on the rising edge of the clock.'" "0,1" bitfld.long 0x0 7. "I2S_EN_7,'Enable bit for I2S channel 7. Value '0' causes reset signal for this channel (i2s_rst_7) configuration SFR bits for this channel are unchanged. Value '1' enables channel. Sampled on the rising edge of the clock.'" "0,1" bitfld.long 0x0 6. "I2S_EN_6,'Enable bit for I2S channel 6. Value '0' causes reset signal for this channel (i2s_rst_6) configuration SFR bits for this channel are unchanged. Value '1' enables channel. Sampled on the rising edge of the clock.'" "0,1" bitfld.long 0x0 5. "I2S_EN_5,'Enable bit for I2S channel 5. Value '0' causes reset signal for this channel (i2s_rst_5) configuration SFR bits for this channel are unchanged. Value '1' enables channel. Sampled on the rising edge of the clock.'" "0,1" newline bitfld.long 0x0 4. "I2S_EN_4,'Enable bit for I2S channel 4. Value '0' causes reset signal for this channel (i2s_rst_4) configuration SFR bits for this channel are unchanged. Value '1' enables channel. Sampled on the rising edge of the clock.'" "0,1" bitfld.long 0x0 3. "I2S_EN_3,'Enable bit for I2S channel 3. Value '0' causes reset signal for this channel (i2s_rst_3) configuration SFR bits for this channel are unchanged. Value '1' enables channel. Sampled on the rising edge of the clock.'" "0,1" bitfld.long 0x0 2. "I2S_EN_2,'Enable bit for I2S channel 2. Value '0' causes reset signal for this channel (i2s_rst_2) configuration SFR bits for this channel are unchanged. Value '1' enables channel. Sampled on the rising edge of the clock.'" "0,1" bitfld.long 0x0 1. "I2S_EN_1,'Enable bit for I2S channel 1. Value '0' causes reset signal for this channel (i2s_rst_1) configuration SFR bits for this channel are unchanged. Value '1' enables channel. Sampled on the rising edge of the clock.'" "0,1" bitfld.long 0x0 0. "I2S_EN_0,'Enable bit for I2S channel 0. Value '0' causes reset signal for this channel (i2s_rst_0) configuration SFR bits for this channel are unchanged. Value '1' enables channel. Sampled on the rising edge of the clock.'" "0,1" line.long 0x4 "I2S_INTR_STAT,'I2S Interrupt Status Register'" hexmask.long.word 0x4 16.--31. 1. "RESERVED0,'Not implemented. Return '0' when read.'" bitfld.long 0x4 15. "RFIFO_AFULL,'Receive FIFO almost full flag active HIGH. This flag is set to HIGH when RX FIFO becomes almost full (rising edge of 'almost full' condition). Updated on the rising edge of the clock. This bit can trigger the interrupt.'" "0,1" bitfld.long 0x4 14. "RFIFO_FULL,'Receive FIFO full flag active HIGH. This flag is set to HIGH when RX FIFO is full. Updated on the rising edge of the clock. This bit can trigger the interrupt.'" "0,1" bitfld.long 0x4 13. "RFIFO_AEMPTY,'Receive FIFO almost empty flag active HIGH. This flag is set to HIGH when RX FIFO becomes almost empty (rising edge of 'almost empty' condition). Updated on the rising edge of the clock. This bit can trigger the interrupt.'" "0,1" bitfld.long 0x4 12. "RFIFO_EMPTY,'Receive FIFO empty flag active HIGH. This flag is set to HIGH when RX FIFO is empty. Updated on the rising edge of the clock. This bit can trigger the interrupt.'" "0,1" newline bitfld.long 0x4 11. "TFIFO_AFULL,'Transmit FIFO almost full flag active HIGH. This flag is set to HIGH when TX FIFO becomes almost full (rising edge of 'almost full' condition). Updated on the rising edge of the clock. This bit can trigger the interrupt.'" "0,1" bitfld.long 0x4 10. "TFIFO_FULL,'Transmit FIFO full flag active HIGH. This flag is set to HIGH when TX FIFO is full. Updated on the rising edge of the clock. This bit can trigger the interrupt.'" "0,1" bitfld.long 0x4 9. "TFIFO_AEMPTY,'Transmit FIFO almost empty flag active HIGH. This flag is set to HIGH when TX FIFO becomes almost empty (rising edge of 'almost empty' condition). Updated on the rising edge of the clock. This bit can trigger the interrupt.'" "0,1" bitfld.long 0x4 8. "TFIFO_EMPTY,'Transmit FIFO empty flag active HIGH. This flag is set to HIGH when TX FIFO is empty. Updated on the rising edge of the clock. This bit can trigger the interrupt.'" "0,1" rbitfld.long 0x4 5.--7. "OVRERR_CODE,'Code of the receiver that caused overrun error. Updated on the rising edge of the clock. These bits are cleared when bit rdata_ovrerr is cleared. The code is a binary notation of the channel's number.'" "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 4. "RDATA_OVRERR,'Receiver data overrun error active HIGH. This flag is set to HIGH when RX overrun arises (rising edge of 'overrun' condition). Updated on the rising edge of the clock. This bit can trigger the interrupt. Writing a LOW value to this bit.." "0,1" rbitfld.long 0x4 1.--3. "UNDERR_CODE,'Code of the transmitter that caused underrun event. Updated on the rising edge of the clock. These bits are cleared when bit tdata_underr is cleared. The code is a binary notation of the channel's number.'" "0,1,2,3,4,5,6,7" bitfld.long 0x4 0. "TDATA_UNDERR,'Transmitter data underrun event active HIGH. This flag is set to HIGH when TX underrun arises (rising edge of 'underrun' condition). Updated on the rising edge of the clock. This bit can trigger the interrupt.'" "0,1" line.long 0x8 "I2S_SRR,'I2S Channels Sample Rate and Resolution Configuration Register'" hexmask.long.byte 0x8 27.--31. 1. "RRESOLUTION,'Receiver resolution (0 to 31). Sampled on the rising edge of the clock. It simply should be assigned the value equal to the number of valid bits minus one.'" hexmask.long.byte 0x8 23.--26. 1. "RESERVED1,'Not implemented. Return '0' when read.'" hexmask.long.byte 0x8 16.--22. 1. "RSAMPLE_RATE,'Receiver sample rate. Sampled on the rising edge of the clock.'" hexmask.long.byte 0x8 11.--15. 1. "TRESOLUTION,'Transmitter resolution (0 to 31). Sampled on the rising edge of the clock. It simply should be assigned the value equal to the number of valid bits minus one.'" hexmask.long.byte 0x8 7.--10. 1. "RESERVED0,'Not implemented. Return '0' when read.'" newline hexmask.long.byte 0x8 0.--6. 1. "TSAMPLE_RATE,'Transmitter sample rate. Sampled on the rising edge of the clock.'" line.long 0xC "CID_CTRL,'Clock. Interrupt and DMA Control Register'" bitfld.long 0xC 31. "RFIFO_AFULL_MASK,'Bit masking interrupt request generation after receive FIFO becomes almost full. When LOW masks generation of interrupt request. Sampled on the rising edge of the clock.'" "0,1" bitfld.long 0xC 30. "RFIFO_FULL_MASK,'Bit masking interrupt request generation after receive FIFO becomes full. When LOW masks generation of interrupt request. Sampled on the rising edge of the clock.'" "0,1" bitfld.long 0xC 29. "RFIFO_AEMPTY_MASK,'Bit masking interrupt request generation after receive FIFO becomes almost empty. When LOW masks generation of interrupt request. Sampled on the rising edge of the clock.'" "0,1" bitfld.long 0xC 28. "RFIFO_EMPTY_MASK,'Bit masking interrupt request generation after receive FIFO becomes empty. When LOW masks generation of interrupt request. Sampled on the rising edge of the clock.'" "0,1" bitfld.long 0xC 27. "TFIFO_AFULL_MASK,'Bit masking interrupt request generation after transmit FIFO becomes almost full. When LOW masks generation of interrupt request. Sampled on the rising edge of the clock.'" "0,1" newline bitfld.long 0xC 26. "TFIFO_FULL_MASK,'Bit masking interrupt request generation after transmit FIFO becomes full. When LOW masks generation of interrupt request. Sampled on the rising edge of the clock.'" "0,1" bitfld.long 0xC 25. "TFIFO_AEMPTY_MASK,'Bit masking interrupt request generation after transmit FIFO becomes almost empty. When LOW masks generation of interrupt request. Sampled on the rising edge of the clock.'" "0,1" bitfld.long 0xC 24. "TFIFO_EMPTY_MASK,'Bit masking interrupt request generation after transmit FIFO becomes empty. When LOW masks generation of interrupt request. Sampled on the rising edge of the clock.'" "0,1" bitfld.long 0xC 23. "I2S_MASK_7,'Bit masking interrupt request generation after underrun / overrun condition occurrence in I2S channel 7. When LOW masks generation of interrupt request caused by the channel 7. Sampled on the rising edge of the clock.'" "0,1" bitfld.long 0xC 22. "I2S_MASK_6,'Bit masking interrupt request generation after underrun / overrun condition occurrence in I2S channel 6. When LOW masks generation of interrupt request caused by the channel 6. Sampled on the rising edge of the clock.'" "0,1" newline bitfld.long 0xC 21. "I2S_MASK_5,'Bit masking interrupt request generation after underrun / overrun condition occurrence in I2S channel 5. When LOW masks generation of interrupt request caused by the channel 5. Sampled on the rising edge of the clock.'" "0,1" bitfld.long 0xC 20. "I2S_MASK_4,'Bit masking interrupt request generation after underrun / overrun condition occurrence in I2S channel 4. When LOW masks generation of interrupt request caused by the channel 4. Sampled on the rising edge of the clock.'" "0,1" bitfld.long 0xC 19. "I2S_MASK_3,'Bit masking interrupt request generation after underrun / overrun condition occurrence in I2S channel 3. When LOW masks generation of interrupt request caused by the channel 3. Sampled on the rising edge of the clock.'" "0,1" bitfld.long 0xC 18. "I2S_MASK_2,'Bit masking interrupt request generation after underrun / overrun condition occurrence in I2S channel 2. When LOW masks generation of interrupt request caused by the channel 2. Sampled on the rising edge of the clock.'" "0,1" bitfld.long 0xC 17. "I2S_MASK_1,'Bit masking interrupt request generation after underrun / overrun condition occurrence in I2S channel 1. When LOW masks generation of interrupt request caused by the channel 1. Sampled on the rising edge of the clock.'" "0,1" newline bitfld.long 0xC 16. "I2S_MASK_0,'Bit masking interrupt request generation after underrun / overrun condition occurrence in I2S channel 0. When LOW masks generation of interrupt request caused by the channel 0. Sampled on the rising edge of the clock.'" "0,1" bitfld.long 0xC 15. "INTREQ_MASK,'Bit masking all interrupt requests. When '0' all interrupts are masked when '1' interrupts use individual masks. Sampled on the rising edge of the clock.'" "0,1" hexmask.long.byte 0xC 10.--14. 1. "RESERVED0,'Not implemented. Return '0' when read.'" bitfld.long 0xC 9. "STROBE_RS,'Clock enable for the unit synchronizing receivers. When high the clk_rs clock is blocked else it is enabled. Sampled on the rising edge of the clock.'" "0,1" bitfld.long 0xC 8. "STROBE_TS,'Clock enable for the unit synchronizing transmitters. When high the clk_ts clock is blocked else it is enabled. Sampled on the rising edge of the clock.'" "0,1" newline bitfld.long 0xC 7. "I2S_STROBE_7,'Clock enable channel 7. When high the clk_7 clock is blocked else it is enabled. Sampled on the rising edge of the clock.'" "0,1" bitfld.long 0xC 6. "I2S_STROBE_6,'Clock enable channel 6. When high the clk_6 clock is blocked else it is enabled. Sampled on the rising edge of the clock.'" "0,1" bitfld.long 0xC 5. "I2S_STROBE_5,'Clock enable channel 5. When high the clk_5 clock is blocked else it is enabled. Sampled on the rising edge of the clock.'" "0,1" bitfld.long 0xC 4. "I2S_STROBE_4,'Clock enable channel 4. When high the clk_4 clock is blocked else it is enabled. Sampled on the rising edge of the clock.'" "0,1" bitfld.long 0xC 3. "I2S_STROBE_3,'Clock enable channel 3. When high the clk_3 clock is blocked else it is enabled. Sampled on the rising edge of the clock.'" "0,1" newline bitfld.long 0xC 2. "I2S_STROBE_2,'Clock enable channel 2. When high the clk_2 clock is blocked else it is enabled. Sampled on the rising edge of the clock.'" "0,1" bitfld.long 0xC 1. "I2S_STROBE_1,'Clock enable channel 1. When high the clk_1 clock is blocked else it is enabled. Sampled on the rising edge of the clock.'" "0,1" bitfld.long 0xC 0. "I2S_STROBE_0,'Clock enable channel 0. When high the clk_0 clock is blocked else it is enabled. Sampled on the rising edge of the clock.'" "0,1" line.long 0x10 "TFIFO_STAT,'Transmit FIFO Status Register'" hexmask.long.tbyte 0x10 10.--31. 1. "RESERVED0,'Not implemented. Return '0' when read.'" hexmask.long.word 0x10 0.--9. 1. "TLEVEL,'Indicates transmit FIFO level. Updated on the rising edge of the clock.'" line.long 0x14 "RFIFO_STAT,'Receive FIFO Status Register'" hexmask.long.tbyte 0x14 10.--31. 1. "RESERVED0,'Not implemented. Return '0' when read.'" hexmask.long.word 0x14 0.--9. 1. "RLEVEL,'Indicates receive FIFO level. Updated on the rising edge of the clock.'" line.long 0x18 "TFIFO_CTRL,'Transmit FIFO Control Register'" hexmask.long.word 0x18 20.--31. 1. "RESERVED1,'Not implemented. Return '0' when read.'" hexmask.long.byte 0x18 16.--19. 1. "TAFULL_THRESHOLD,'Determines threshold for almost full flag in the transmit FIFO. Sampled on the rising edge of the clock.'" hexmask.long.word 0x18 4.--15. 1. "RESERVED0,'Not implemented. Return '0' when read.'" hexmask.long.byte 0x18 0.--3. 1. "TAEMPTY_THRESHOLD,'Determines threshold for almost empty flag in the transmit FIFO. Sampled on the rising edge of the clock.'" line.long 0x1C "RFIFO_CTRL,'Receive FIFO Control Register'" hexmask.long.word 0x1C 20.--31. 1. "RESERVED1,'Not implemented. Return '0' when read.'" hexmask.long.byte 0x1C 16.--19. 1. "RAFULL_THRESHOLD,'Determines threshold for almost full flag in the receive FIFO. Sampled on the rising edge of the clock.'" hexmask.long.word 0x1C 4.--15. 1. "RESERVED0,'Not implemented. Return '0' when read.'" hexmask.long.byte 0x1C 0.--3. 1. "RAEMPTY_THRESHOLD,'Determines threshold for almost empty flag in the receive FIFO. Sampled on the rising edge of the clock.'" line.long 0x20 "DEV_CONF,'Device Configuration Register'" hexmask.long.tbyte 0x20 12.--31. 1. "RESERVED0,'Not implemented. Return '0' when read.'" bitfld.long 0x20 11. "REC_WS_DSP_MODE,'The word select signal format change indicator according to the DSP audio interface specification for the receiver units. HIGH value of this bit determines generation of the word select signal format specific to the DSP audio interface.." "0,1" bitfld.long 0x20 10. "REC_DATA_WS_DEL,'The received valid data delay indicator at the I2S serial data input line after the word select signal edge. When HIGH the received serial data are updated on the second rising/falling edge of the clock signal after the word select.." "0,1" bitfld.long 0x20 9. "REC_I2S_ALIGN_LR,'Alignment of the received digital data sample at the I2S serial data line. When HIGH it determines the MSB adjustment of the resolution-width received digital data sample at the I2S serial data input line. If the received data sample.." "0,1" bitfld.long 0x20 8. "REC_APB_ALIGN_LR,'Alignment of the received digital data sample at the APB bus. HIGH value of this bit determines the MSB side alignment of the resolution-width received data sample at the APB data bus. LOW value of this bit determines the LSB side.." "0,1" newline bitfld.long 0x20 7. "REC_WS_POLAR,'The word select signal polarity selection for reception. When HIGH the level of the word select signal for the received left channel data sample is '1' and the level of this signal for the received right channel data sample is '0'. When.." "0,1" bitfld.long 0x20 6. "REC_SCK_POLAR,'The continuous serial clock active edge for reception. When HIGH the received serial data are sampled on the falling edge of the bit clock. When LOW the received serial data are sampled on the rising edge of the bit clock. Default value.." "0,1" bitfld.long 0x20 5. "TRAN_WS_DSP_MODE,'The word select signal format change indicator according to the DSP audio interface specification for the transmitter units. HIGH value of this bit determines generation of the word select signal format specific to the DSP audio.." "0,1" bitfld.long 0x20 4. "TRAN_DATA_WS_DEL,'The transmitted valid data delay indicator at the I2S serial data output line after the word select signal edge. When HIGH the serial data for transmission are updated on the first rising/falling edge of the clock signal after the word.." "0,1" bitfld.long 0x20 3. "TRAN_I2S_ALIGN_LR,'Alignment of the transmitted digital data sample at the I2S serial data line. When HIGH it determines the MSB adjustment of the resolution-width transmitted digital data sample at the I2S serial data output line. If the transmitted.." "0,1" newline bitfld.long 0x20 2. "TRAN_APB_ALIGN_LR,'Alignment of the transmitted digital data sample at the APB bus. HIGH value of this bit determines the MSB side alignment of the resolution-width transmitted data sample at the APB data bus. LOW value of this bit determines the LSB.." "0,1" bitfld.long 0x20 1. "TRAN_WS_POLAR,'The word select signal polarity selection for transmission. When HIGH the level of the word select signal for the transmitted left channel data sample is '1' and the level of this signal for the transmitted right channel data sample is.." "0,1" bitfld.long 0x20 0. "TRAN_SCK_POLAR,'The continuous serial clock active edge for transmission. When HIGH the serial data for transmission are updated on the falling edge of the bit clock. When LOW the serial data for transmission are updated on the rising edge of the bit.." "0,1" line.long 0x24 "I2S_POLL_STAT,'The I2S status register for controlling the IP by polling is read only special function register. All used bits reflect current status of FIFO flags. data overrun and data underrun.'" hexmask.long 0x24 7.--31. 1. "RESERVED1,'Not implemented. Return '0' when read.'" bitfld.long 0x24 6. "RX_OVERRUN,'Receiver data overrun: 1 - RX data overrun has occurred 0 - No RX data overrun Updated on the rising edge of the clock. '" "0,1" bitfld.long 0x24 5. "RX_AFULL,'Receive FIFO almost full flag: 1 - RX FIFO is almost full 0 - RX FIFO is not almost full Updated on the rising edge of the clock.'" "0,1" bitfld.long 0x24 4. "RX_FULL,'Receive FIFO full flag: 1 - RX FIFO is full 0 - RX FIFO is not full Updated on the rising edge of the clock.'" "0,1" bitfld.long 0x24 3. "RESERVED0,'Not implemented. Return '0' when read.'" "0,1" newline bitfld.long 0x24 2. "TX_UNDERRUN,'Transmitter data underrun: 1 - TX data underrun has occurred 0 - No TX data underrun Updated on the rising edge of the clock.'" "0,1" bitfld.long 0x24 1. "TX_AEMPTY,'Transmit FIFO almost empty flag: 1 - TX FIFO is almost empty 0 - TX FIFO is not almost empty Updated on the rising edge of the clock.'" "0,1" bitfld.long 0x24 0. "TX_EMPTY,'Transmit FIFO empty flag: 1 - TX FIFO is empty 0 - TX FIFO is not empty Updated on the rising edge of the clock.'" "0,1" tree.end repeat.end repeat 8. (increment 1. 1.) (list ad:0xF0300000 ad:0xF0310000 ad:0xF0600000 ad:0xF0610000 ad:0xF0620000 ad:0xF0630000 ad:0xF0640000 ad:0xF0650000) tree "I2S_SC$1" base $2 group.long 0x0++0x17 line.long 0x0 "I2S_CTRL,'I2S control register. After end of reset bit sfr_rst triggers to 1 and bit fifo_rst triggers to 1. Therefore register value after end of reset is 000001B8'" bitfld.long 0x0 31. "LR_PACK,Left/Right packing mode enable When HIGH the Left/Right packing mode is enabled and then the left audio channel sample data is created from less significant bits of FIFO data..Respectively the right audio channel sample data is created from.." "0,1" bitfld.long 0x0 30. "FIFO_AFULL_MASK,Bit masking interrupt request generation after full-duplex mode receive FIFO becomes almost full. When LOW masks generation of interrupt request." "0,1" bitfld.long 0x0 29. "FIFO_FULL_MASK,Bit masking interrupt request generation after full-duplex mode receive FIFO becomes full. When LOW masks generation of interrupt request." "0,1" bitfld.long 0x0 28. "FIFO_AEMPTY_MASK,Bit masking interrupt request generation after full-duplex mode receive FIFO becomes almost empty. When LOW masks generation of interrupt request." "0,1" bitfld.long 0x0 27. "FIFO_EMPTY_MASK,Bit masking interrupt request generation after FIFO becomes empty. When LOW masks generation of interrupt request.When full-duplex mode is active this bit is a mask only for transmitter FIFO empty condition. Sampled on the rising edge.." "0,1" newline bitfld.long 0x0 26. "I2S_MASK,Bit masking interrupt request generation after underrun/overrun condition occurrence in I2S-SC transceiver. When LOW masks generation of interrupt request.When full-duplex mode is active this bit is a mask only for underrun event interrupt." "0,1" bitfld.long 0x0 25. "INTREQ_MASK,Bit masking all interrupt requests. When LOW all interrupts are masked when HIGH interrupts use individual masks. Sampled on the rising edge of the clock." "0,1" bitfld.long 0x0 24. "I2S_STB,Transceiver clock enable. When LOW the clk_i2s clock is enabled else clock is disabled. Sampled on the rising edge of the clock." "0,1" bitfld.long 0x0 23. "HOST_DATA_ALIGN,Audio data sample alignment at host data bus. When LOW the audio sample data is aligned to the LSB at the host data bus. When HIGH the audio sample data is aligned to the MSB at host data bus. Sampled on the rising edge of the clock." "0,1" bitfld.long 0x0 22. "DATA_ORDER,Audio data sample arrangement in audio data slot. When LOW audio sample arrangement in audio data slot is MSB-first. When HIGH audio sample arrangement in audio data slot is LSB-first. Sampled on the rising edge of the clock." "0,1" newline bitfld.long 0x0 21. "DATA_ALIGN,Audio sample alignment in audio data time slot. When LOW the audio sample bits are left justified in audio data time slot. When HIGH the audio sample bits are right justified in audio data time slot. Sampled on the rising edge of the clock." "0,1" hexmask.long.byte 0x0 16.--20. 1. "DATA_WS_DEL,Audio data delay after WS signal edge at serial line. TDM mode is not active: Value from 0...(CHN_WIDTH-1) range specified that first audio data bit is updated/received at the first second...last edge of the SCK signal after the WS signal.." bitfld.long 0x0 15. "WS_POLAR,The word select signal polarity selection. I2S Word Select (WS) mode is active: When HIGH the level of the word select signal for the left channel data sample is '1' and the level of this signal for the right channel data sample is '0'. When.." "0,1" bitfld.long 0x0 14. "SCK_POLAR,The continuous serial clock active edge. When HIGH the serial data are updated on the falling edge of the bit clock.When LOW serial data are updated on the rising edge of the bit clock. Sampled on the rising edge of the clock." "0,1" bitfld.long 0x0 13. "AUDIO_MODE,Mono/stereo audio mode selection. Active only when TDM mode is inactive and I2S-SC works at standard stereo audio interface mode. When LOW both left and right channel audio samples are transmitted/received for transmitter/receiver mode.." "0,1" newline bitfld.long 0x0 12. "MONO_MODE,Active audio channel in mono mode. When LOW left audio channel is active. When HIGH right audio channel is active. Sampled on the rising edge of the clock." "0,1" hexmask.long.byte 0x0 8.--11. 1. "WS_MODE,Word select signal (WS) format. TDM mode is not active: Only bit 8 is relevant. If it is set to LOW (even value of ws_mode) WS signal have DSP audio interface specification format. If it is set to HIGH (odd value of ws_mode) WS signal have.." bitfld.long 0x0 5.--7. "CHN_WIDTH,Audio channel time slot width in I2S master or DSP/TDM master and slave modes. 0 - 8 SCK cycles per audio channel 1 - 12 SCK cycles per audio channel 2 - 16 SCK cycles per audio channel 3 - 18 SCK cycles per audio channel 4 - 20 SCK cycles per.." "0,1,2,3,4,5,6,7" bitfld.long 0x0 4. "FIFO_RST,Full-duplex mode receiver FIFO reset. Active only in full-duplex mode. When '0' RFIFO pointer is reset to zero. Threshold levels for RFIFO are unchanged. The bit is automatically set to '1' after one clock cycle." "0,1" bitfld.long 0x0 3. "SFR_RST,SFR block synchronous reset. When LOW all bits in SFR registers are reset to default values. This bit is automatically set to HIGH after one clock cycle. Sampled on the rising edge of the clock." "0,1" newline bitfld.long 0x0 2. "MS_CFG,Configuration bit for transceiver synchronizing unit: 1 - Master 0 - Slave Sampled on the rising edge of the clock." "0,1" bitfld.long 0x0 1. "DIR_CFG,Hal-duplex direction of transmission: 1 - Transmitter 0 - Receiver Sampled on the rising edge of the clock." "0,1" bitfld.long 0x0 0. "I2S_EN,Enable bit for I2S transceiver 1 - enables transceiver 0 - disables transceiver causes reset signal configuration SFR bits are unchanged Sampled on the rising edge of the clock." "0,1" line.long 0x4 "I2S_CTRL_FDX,'I2S Full-Duplex Mode Control register. After end of reset bit fifo_rst triggers to 1. Therefore register value after end of reset is 00000010'" bitfld.long 0x4 30. "RFIFO_AFULL_MASK,Bit masking interrupt request generation after full-duplex mode receive FIFO becomes almost full.When LOW masks generation of interrupt request." "0,1" bitfld.long 0x4 29. "RFIFO_FULL_MASK,Bit masking interrupt request generation after full-duplex mode receive FIFO becomes full. When LOW masks generation of interrupt request." "0,1" bitfld.long 0x4 28. "RFIFO_AEMPTY_MASK,Bit masking interrupt request generation after full-duplex mode receive FIFO becomes almost empty.When LOW masks generation of interrupt request." "0,1" bitfld.long 0x4 27. "RFIFO_EMPTY_MASK,Bit masking interrupt request generation after full-duplex mode receive FIFO becomes empty. When LOW masks generation of interrupt request." "0,1" newline bitfld.long 0x4 26. "RI2S_MASK,Bit masking interrupt request generation after overrun condition occurrence in I2S-SC full-duplex mode receiver. When LOW masks generation of interrupt request." "0,1" bitfld.long 0x4 4. "FIFO_RST,Full-duplex mode receiver FIFO reset. Active only in full-duplex mode. When '0' RFIFO pointer is reset to zero. Threshold levels for RFIFO are unchanged. The bit is automatically set to '1' after one clock cycle." "0,1" bitfld.long 0x4 2. "I2S_FRX_EN,Full-duplex mode receiver enable When full_duplex mode enable bit is active the bit controls receiving data through sdi serial data input.Otherwise the bit setup is not applicable." "0,1" newline bitfld.long 0x4 1. "I2S_FTX_EN,Full-duplex mode transmitter enable When full_duplex mode enable bit is active the bit controls transmitting data through sdo serial data output. Otherwise the bit setup is not applicable." "0,1" bitfld.long 0x4 0. "FULL_DUPLEX,Full-duplex mode enable When HIGH transmitter and receiver data units enable are controlled dynamically by the i2s_ftx_en (I2S_CTRL_FDX[1]) and i2s_frx_en (I2S_CTRL_FDX[2]) bits. Modifiable only when I2S transceiver is disabled (i2s_en bit of.." "0,1" line.long 0x8 "I2S_SRES,'Transceiver Sample Resolution'" hexmask.long.byte 0x8 0.--4. 1. "RESOLUTION,Samples resolution. When full-duplex mode is active this value specifies resolution only for transmitted samples. Sampled on the rising edge of the clock. It simply should be assigned the value equal to the number of valid bits minus one for.." line.long 0xC "I2S_SRES_FDR,'Full Duplex Mode Receive Samples Resolution'" hexmask.long.byte 0xC 0.--4. 1. "RRESOLUTION,Full-duplex mode receive samples resolution. When half-duplex mode is active this value is ignored. It simply should be assigned the value equal to the number of valid bits minus one for example: 00000 B - sample resolution = 1 bit 11111 B -.." line.long 0x10 "I2S_SRATE,'Transceiver Sample Rate'" hexmask.long.tbyte 0x10 0.--19. 1. "SAMPLE_RATE,In general value of sample rate is the quotient of clk frequency and I2S rate [bit/s]. The value of sample rate is the higher the clk frequency is greater than I2S rate." line.long 0x14 "I2S_STAT,'I2S-SC Status Flags Register'" bitfld.long 0x14 19. "RFIFO_AFULL,Receive FIFO almost full flag in full-duplex mode. Active HIGH. This flag is set to HIGH when RX FIFO becomes almost full (rising edge of 'almost full' condition). This bit can trigger the interrupt." "0,1" bitfld.long 0x14 18. "RFIFO_FULL,Receive FIFO full flag in full-duplex mode. Active HIGH. This flag is set to HIGH when RX FIFO is full. This bit can trigger the interrupt." "0,1" bitfld.long 0x14 17. "RFIFO_AEMPTY,Receive FIFO almost empty flag in full-duplex mode. Active HIGH. This flag is set to HIGH when RX FIFO becomes almost empty (rising edge of 'almost empty' condition). This bit can trigger the interrupt." "0,1" bitfld.long 0x14 16. "RFIFO_EMPTY,Receive FIFO empty flag in full-duplex mode.Active HIGH. This flag is set to HIGH when RX FIFO is empty. This bit can trigger the interrupt." "0,1" newline hexmask.long.word 0x14 6.--15. 1. "RESERVED," bitfld.long 0x14 5. "FIFO_AFULL,FIFO almost full flag. Active HIGH. This flag is set to HIGH when FIFO becomes almost full (rising edge of 'almost full' condition). When full-duplex mode is active this bit is a flag only for transmitter FIFO almost full condition. This bit.." "0,1" bitfld.long 0x14 4. "FIFO_FULL,FIFO full flag. Active HIGH. This flag is set to HIGH when FIFO is full. When full-duplex mode is active this bit is a flag only for transmitter FIFO full condition. This bit can trigger the interrupt." "0,1" bitfld.long 0x14 3. "FIFO_AEMPTY,FIFO almost empty flag. Active HIGH. This flag is set to HIGH when FIFO becomes almost empty (rising edge of 'almost empty' condition). When full-duplex mode is active this bit is a flag only for transmitter FIFO almost empty condition. This.." "0,1" bitfld.long 0x14 2. "FIFO_EMPTY,FIFO empty flag. Active HIGH. This flag is set to HIGH when FIFO is empty. When full-duplex mode is active this bit is a flag only for transmitter FIFO empty condition. This bit can trigger the interrupt." "0,1" newline bitfld.long 0x14 1. "RDATA_OVRERR,Indicates data overrun event in receiver mode active HIGH. This flag is set to HIGH when RX overrun arises (rising edge of 'overrun'condition). Updated on the rising edge of the clock. This bit can trigger the interrupt." "0,1" bitfld.long 0x14 0. "TDATA_UNDERR,Indicates data underrun event active HIGH. This flag is set to HIGH when TX underrun arises (rising edge of 'underrun'condition). Updated on the rising edge of the clock. This bit can trigger the interrupt." "0,1" rgroup.long 0x18++0x3 line.long 0x0 "FIFO_LEVEL,'FIFO Using Level Register (read only)'" hexmask.long.byte 0x0 0.--7. 1. "FIFO_LEVEL,FIFO Using Level Register (read only)" group.long 0x1C++0x7 line.long 0x0 "FIFO_AEMPTY,'FIFO Almost Empty Level'" hexmask.long.byte 0x0 0.--6. 1. "AEMPTY_THRESHOLD,Determines threshold for almost empty flag in the FIFO. When full-duplex mode is active this register specifies an almost empty level of the transmitter FIFO level. Sampled on the rising edge of the clock." line.long 0x4 "FIFO_AFULL,'FIFO Almost Empty Level'" hexmask.long.byte 0x4 0.--6. 1. "AFULL_THRESHOLD,Determines threshold for almost full flag in the FIFO. When full-duplex mode is active this register specifies an almost full level of the transmitter FIFO level. Sampled on the rising edge of the clock." rgroup.long 0x24++0x3 line.long 0x0 "FIFO_LEVEL_FDR,'Full-Duplex Mode Receiver FIFO Level Register (read only)'" hexmask.long.byte 0x0 0.--7. 1. "FIFO_LEVEL,FIFO Using Level Register (read only)" group.long 0x28++0xF line.long 0x0 "FIFO_AEMPTY_FDR,'Full-Duplex Mode Receiver FIFO Almost Empty Level'" hexmask.long.byte 0x0 0.--6. 1. "AEMPTY_THRESHOLD,Determines threshold for almost empty flag in the FIFO. When full-duplex mode is active this register specifies an almost empty level of the transmitter FIFO level. Sampled on the rising edge of the clock." line.long 0x4 "FIFO_AFULL_FDR,'Full-Duplex Mode Receiver FIFO Almost Full Level'" hexmask.long.byte 0x4 0.--6. 1. "AFULL_THRESHOLD,Determines threshold for almost full flag in the FIFO. When full-duplex mode is active this register specifies an almost full level of the transmitter FIFO level. Sampled on the rising edge of the clock." line.long 0x8 "TDM_CTRL,'Time Division Multiplexing Control Register'" bitfld.long 0x8 31. "CH15_EN,TDM interface channel 15 activating bit. When HIGH 15th time slot sample is transmitted and/or received depending on transceiver mode. Sampled on the rising edge of the clock." "0,1" bitfld.long 0x8 30. "CH14_EN,TDM interface channel 14 activating bit. When HIGH 14th time slot sample is transmitted and/or received depending on transceiver mode. Sampled on the rising edge of the clock." "0,1" bitfld.long 0x8 29. "CH13_EN,TDM interface channel 13 activating bit. When HIGH 13th time slot sample is transmitted and/or received depending on transceiver mode. Sampled on the rising edge of the clock." "0,1" bitfld.long 0x8 28. "CH12_EN,TDM interface channel 12 activating bit. When HIGH 12th time slot sample is transmitted and/or received depending on transceiver mode. Sampled on the rising edge of the clock." "0,1" bitfld.long 0x8 27. "CH11_EN,TDM interface channel 11 activating bit. When HIGH 11th time slot sample is transmitted and/or received depending on transceiver mode. Sampled on the rising edge of the clock." "0,1" newline bitfld.long 0x8 26. "CH10_EN,TDM interface channel 10 activating bit. When HIGH 10th time slot sample is transmitted and/or received depending on transceiver mode. Sampled on the rising edge of the clock." "0,1" bitfld.long 0x8 25. "CH9_EN,TDM interface channel 9 activating bit. When HIGH 9th time slot sample is transmitted and/or received depending on transceiver mode. Sampled on the rising edge of the clock." "0,1" bitfld.long 0x8 24. "CH8_EN,TDM interface channel 8 activating bit. When HIGH 8th time slot sample is transmitted and/or received depending on transceiver mode. Sampled on the rising edge of the clock." "0,1" bitfld.long 0x8 23. "CH7_EN,TDM interface channel 7 activating bit. When HIGH 7th time slot sample is transmitted and/or received depending on transceiver mode. Sampled on the rising edge of the clock." "0,1" bitfld.long 0x8 22. "CH6_EN,TDM interface channel 6 activating bit. When HIGH 6th time slot sample is transmitted and/or received depending on transceiver mode. Sampled on the rising edge of the clock." "0,1" newline bitfld.long 0x8 21. "CH5_EN,TDM interface channel 5 activating bit. When HIGH 5th time slot sample is transmitted and/or received depending on transceiver mode. Sampled on the rising edge of the clock." "0,1" bitfld.long 0x8 20. "CH4_EN,TDM interface channel 4 activating bit. When HIGH 4th time slot sample is transmitted and/or received depending on transceiver mode. Sampled on the rising edge of the clock." "0,1" bitfld.long 0x8 19. "CH3_EN,TDM interface channel 3 activating bit. When HIGH 3th time slot sample is transmitted and/or received depending on transceiver mode. Sampled on the rising edge of the clock." "0,1" bitfld.long 0x8 18. "CH2_EN,TDM interface channel 2 activating bit. When HIGH 2nd time slot sample is transmitted and/or received depending on transceiver mode. Sampled on the rising edge of the clock." "0,1" bitfld.long 0x8 17. "CH1_EN,TDM interface channel 1 activating bit. When HIGH 1st time slot sample is transmitted and/or received depending on transceiver mode. Sampled on the rising edge of the clock." "0,1" newline bitfld.long 0x8 16. "CH0_EN,TDM interface channel 0 activating bit. When HIGH zero time slot sample is transmitted and/or received depending on transceiver mode. Sampled on the rising edge of the clock." "0,1" hexmask.long.byte 0x8 1.--4. 1. "CHN_NO,Number of supported audio channels in TDM compatible interface mode. Written value equals channels number minus 1. Sampled on the rising edge of the clock" bitfld.long 0x8 0. "TDM_EN,Time Division Multiplexing audio interface enable. When HIGH audio interface works in TDM compatible mode determined by this register value. When LOW audio interface works in standard stereo I 2 S mode. Sampled on the rising edge of the clock." "0,1" line.long 0xC "TDM_FD_DIR,'Time Division Multiplexing Full-Duplex Mode Channels Direction Register'" bitfld.long 0xC 31. "CH15_RXEN,TDM interface channel 15 receive enable bit. Active only in full-duplex mode. When HIGH and ch15_en bit in TDM_CTRL register is HIGH audio sample is received from sdi line at 15 time slot." "0,1" bitfld.long 0xC 30. "CH14_RXEN,TDM interface channel 14 receive enable bit. Active only in full-duplex mode. When HIGH and ch14_en bit in TDM_CTRL register is HIGH audio sample is received from sdi line at 14 time slot." "0,1" bitfld.long 0xC 29. "CH13_RXEN,TDM interface channel 13 receive enable bit. Active only in full-duplex mode. When HIGH and ch13_en bit in TDM_CTRL register is HIGH audio sample is received from sdi line at 13 time slot." "0,1" bitfld.long 0xC 28. "CH12_RXEN,TDM interface channel 12 receive enable bit. Active only in full-duplex mode. When HIGH and ch12_en bit in TDM_CTRL register is HIGH audio sample is received from sdi line at 12 time slot." "0,1" bitfld.long 0xC 27. "CH11_RXEN,TDM interface channel 11 receive enable bit. Active only in full-duplex mode. When HIGH and ch11_en bit in TDM_CTRL register is HIGH audio sample is received from sdi line at 11 time slot." "0,1" newline bitfld.long 0xC 26. "CH10_RXEN,TDM interface channel 10 receive enable bit. Active only in full-duplex mode. When HIGH and ch10_en bit in TDM_CTRL register is HIGH audio sample is received from sdi line at 10 time slot." "0,1" bitfld.long 0xC 25. "CH9_RXEN,TDM interface channel 9 receive enable bit. Active only in full-duplex mode. When HIGH and ch9_en bit in TDM_CTRL register is HIGH audio sample is received from sdi line at 9 time slot." "0,1" bitfld.long 0xC 24. "CH8_RXEN,TDM interface channel 8 receive enable bit. Active only in full-duplex mode. When HIGH and ch8_en bit in TDM_CTRL register is HIGH audio sample is received from sdi line at 8 time slot." "0,1" bitfld.long 0xC 23. "CH7_RXEN,TDM interface channel 7 receive enable bit. Active only in full-duplex mode. When HIGH and ch7_en bit in TDM_CTRL register is HIGH audio sample is received from sdi line at 7 time slot." "0,1" bitfld.long 0xC 22. "CH6_RXEN,TDM interface channel 6 receive enable bit. Active only in full-duplex mode. When HIGH and ch6_en bit in TDM_CTRL register is HIGH audio sample is received from sdi line at 6 time slot." "0,1" newline bitfld.long 0xC 21. "CH5_RXEN,TDM interface channel 5 receive enable bit. Active only in full-duplex mode. When HIGH and ch5_en bit in TDM_CTRL register is HIGH audio sample is received from sdi line at 5 time slot." "0,1" bitfld.long 0xC 20. "CH4_RXEN,TDM interface channel 4 receive enable bit. Active only in full-duplex mode. When HIGH and ch4_en bit in TDM_CTRL register is HIGH audio sample is received from sdi line at 4 time slot." "0,1" bitfld.long 0xC 19. "CH3_RXEN,TDM interface channel 3 receive enable bit. Active only in full-duplex mode. When HIGH and ch3_en bit in TDM_CTRL register is HIGH audio sample is received from sdi line at 3 time slot." "0,1" bitfld.long 0xC 18. "CH2_RXEN,TDM interface channel 2 receive enable bit. Active only in full-duplex mode. When HIGH and ch2_en bit in TDM_CTRL register is HIGH audio sample is received from sdi line at 2 time slot." "0,1" bitfld.long 0xC 17. "CH1_RXEN,TDM interface channel 1 receive enable bit. Active only in full-duplex mode. When HIGH and ch1_en bit in TDM_CTRL register is HIGH audio sample is received from sdi line at 1 time slot." "0,1" newline bitfld.long 0xC 16. "CH0_RXEN,TDM interface channel 0 receive enable bit. Active only in full-duplex mode. When HIGH and ch0_en bit in TDM_CTRL register is HIGH audio sample is received from sdi line at 0 time slot." "0,1" bitfld.long 0xC 15. "CH15_TXEN,TDM interface channel 15 transmit enable bit. Active only in full-duplex mode. When HIGH and ch15_en bit in TDM_CTRL register is HIGH audio sample is transmitted at 15 time slot through sdo line." "0,1" bitfld.long 0xC 14. "CH14_TXEN,TDM interface channel 14 transmit enable bit. Active only in full-duplex mode. When HIGH and ch14_en bit in TDM_CTRL register is HIGH audio sample is transmitted at 14 time slot through sdo line." "0,1" bitfld.long 0xC 13. "CH13_TXEN,TDM interface channel 13 transmit enable bit. Active only in full-duplex mode. When HIGH and ch13_en bit in TDM_CTRL register is HIGH audio sample is transmitted at 13 time slot through sdo line." "0,1" bitfld.long 0xC 12. "CH12_TXEN,TDM interface channel 12 transmit enable bit. Active only in full-duplex mode. When HIGH and ch12_en bit in TDM_CTRL register is HIGH audio sample is transmitted at 12 time slot through sdo line." "0,1" newline bitfld.long 0xC 11. "CH11_TXEN,TDM interface channel 11 transmit enable bit. Active only in full-duplex mode. When HIGH and ch11_en bit in TDM_CTRL register is HIGH audio sample is transmitted at 11 time slot through sdo line." "0,1" bitfld.long 0xC 10. "CH10_TXEN,TDM interface channel 10 transmit enable bit. Active only in full-duplex mode. When HIGH and ch10_en bit in TDM_CTRL register is HIGH audio sample is transmitted at 10 time slot through sdo line." "0,1" bitfld.long 0xC 9. "CH9_TXEN,TDM interface channel 9 transmit enable bit. Active only in full-duplex mode. When HIGH and ch9_en bit in TDM_CTRL register is HIGH audio sample is transmitted at 9 time slot through sdo line." "0,1" bitfld.long 0xC 8. "CH8_TXEN,TDM interface channel 8 transmit enable bit. Active only in full-duplex mode. When HIGH and ch8_en bit in TDM_CTRL register is HIGH audio sample is transmitted at 8 time slot through sdo line." "0,1" bitfld.long 0xC 7. "CH7_TXEN,TDM interface channel 7 transmit enable bit. Active only in full-duplex mode. When HIGH and ch7_en bit in TDM_CTRL register is HIGH audio sample is transmitted at 7 time slot through sdo line." "0,1" newline bitfld.long 0xC 6. "CH6_TXEN,TDM interface channel 6 transmit enable bit. Active only in full-duplex mode. When HIGH and ch6_en bit in TDM_CTRL register is HIGH audio sample is transmitted at 6 time slot through sdo line." "0,1" bitfld.long 0xC 5. "CH5_TXEN,TDM interface channel 5 transmit enable bit. Active only in full-duplex mode. When HIGH and ch5_en bit in TDM_CTRL register is HIGH audio sample is transmitted at 5 time slot through sdo line." "0,1" bitfld.long 0xC 4. "CH4_TXEN,TDM interface channel 4 transmit enable bit. Active only in full-duplex mode. When HIGH and ch4_en bit in TDM_CTRL register is HIGH audio sample is transmitted at 4 time slot through sdo line." "0,1" bitfld.long 0xC 3. "CH3_TXEN,TDM interface channel 3 transmit enable bit. Active only in full-duplex mode. When HIGH and ch3_en bit in TDM_CTRL register is HIGH audio sample is transmitted at 3 time slot through sdo line." "0,1" bitfld.long 0xC 2. "CH2_TXEN,TDM interface channel 2 transmit enable bit. Active only in full-duplex mode. When HIGH and ch2_en bit in TDM_CTRL register is HIGH audio sample is transmitted at 2 time slot through sdo line." "0,1" newline bitfld.long 0xC 1. "CH1_TXEN,TDM interface channel 1 transmit enable bit. Active only in full-duplex mode. When HIGH and ch1_en bit in TDM_CTRL register is HIGH audio sample is transmitted at 1 time slot through sdo line." "0,1" bitfld.long 0xC 0. "CH0_TXEN,TDM interface channel 0 transmit enable bit. Active only in full-duplex mode. When HIGH and ch0_en bit in TDM_CTRL register is HIGH audio sample is transmitted at 0 time slot through sdo line." "0,1" tree.end repeat.end elif (CORENAME()=="CORTEXA55") repeat 2. (increment 1. 1.) (list ad:0x305C0000 ad:0x305D0000) tree "I2S_MC$1" base $2 group.long 0x0++0x27 line.long 0x0 "I2S_CTRL,'I2S Control Register'" rbitfld.long 0x0 29.--31. "RESERVED0,'Not implemented. Return '0' when read.'" "0,1,2,3,4,5,6,7" bitfld.long 0x0 28. "RSYNC_LOOP_BACK,'Loop-back configuration bit for receiver synchronization unit. When 0 (normal mode) the scki and wsi inputs of the I2S module (configured to be receiver synchronization unit) are connected to the external inputs rclki and rwsi. When 1.." "0,1" bitfld.long 0x0 27. "TSYNC_LOOP_BACK,'Loop-back configuration bit for transmitter synchronization unit. When 0 (normal mode) the scki and wsi inputs of the I2S module (configured to be transmitter synchronization unit) are connected to the external inputs tclki and twsi." "0,1" bitfld.long 0x0 26. "RSYNC_RST,'Reset for receiver synchronizing unit. Active LOW. Sampled on the rising edge of the clock.'" "0,1" bitfld.long 0x0 25. "TSYNC_RST,'Reset for transmitter synchronizing unit. Active LOW. Sampled on the rising edge of the clock.'" "0,1" newline bitfld.long 0x0 24. "RFIFO_RST,'Receive FIFO reset. When '0' receive FIFO pointers are reset to zero. Threshold level for this FIFO is unchanged. This bit is automatically set to '1' after one clock cycle. Sampled on the rising edge of the clock.'" "0,1" bitfld.long 0x0 23. "TFIFO_RST,'Transmit FIFO reset. When '0' transmit FIFO pointers are reset to zero. Threshold level for this FIFO is unchanged. This bit is automatically set to '1' after one clock cycle. Sampled on the rising edge of the clock.'" "0,1" bitfld.long 0x0 22. "R_MS,'Master (value '1') or slave (value '0') configuration bit for unit synchronizing all receivers with I2S bus. Sampled on the rising edge of the clock.'" "0,1" bitfld.long 0x0 21. "T_MS,'Master (value '1') or slave (value '0') configuration bit for unit synchronizing all transmitters with I2S bus. Sampled on the rising edge of the clock.'" "0,1" bitfld.long 0x0 20. "SFR_RST,'SFR block synchronous reset. When '0' all bits in SFR registers are reset to default values. This bit is automatically set to '1' after one clock cycle. Sampled on the rising edge of the clock.'" "0,1" newline bitfld.long 0x0 19. "LOOP_BACK_6_7,'Loop back test configuration bit. When '1' it configures channels 6 and 7 into the loop-back mode. In this mode channels 6 and 7 can work in both directions depending on configuration bits. Default value '0' causes normal operation.." "0,1" bitfld.long 0x0 18. "LOOP_BACK_4_5,'Loop back test configuration bit. When '1' it configures channels 4 and 5 into the loop-back mode. In this mode channels 4 and 5 can work in both directions depending on configuration bits. Default value '0' causes normal operation.." "0,1" bitfld.long 0x0 17. "LOOP_BACK_2_3,'Loop back test configuration bit. When '1' it configures channels 2 and 3 into the loop-back mode. In this mode channels 2 and 3 can work in both directions depending on configuration bits. Default value '0' causes normal operation.." "0,1" bitfld.long 0x0 16. "LOOP_BACK_0_1,'Loop back test configuration bit. When '1' it configures channels 0 and 1 into the loop-back mode. In this mode channels 0 and 1 can work in both directions depending on configuration bits. Default value '0' causes normal operation.." "0,1" bitfld.long 0x0 15. "TR_CFG_7,'Transmitter (value '1') or receiver (value '0') configuration bit for I2S channel 7. Sampled on the rising edge of the clock.'" "0,1" newline bitfld.long 0x0 14. "TR_CFG_6,'Transmitter (value '1') or receiver (value '0') configuration bit for I2S channel 6. Sampled on the rising edge of the clock.'" "0,1" bitfld.long 0x0 13. "TR_CFG_5,'Transmitter (value '1') or receiver (value '0') configuration bit for I2S channel 5. Sampled on the rising edge of the clock.'" "0,1" bitfld.long 0x0 12. "TR_CFG_4,'Transmitter (value '1') or receiver (value '0') configuration bit for I2S channel 4. Sampled on the rising edge of the clock.'" "0,1" bitfld.long 0x0 11. "TR_CFG_3,'Transmitter (value '1') or receiver (value '0') configuration bit for I2S channel 3. Sampled on the rising edge of the clock.'" "0,1" bitfld.long 0x0 10. "TR_CFG_2,'Transmitter (value '1') or receiver (value '0') configuration bit for I2S channel 2. Sampled on the rising edge of the clock.'" "0,1" newline bitfld.long 0x0 9. "TR_CFG_1,'Transmitter (value '1') or receiver (value '0') configuration bit for I2S channel 1. Sampled on the rising edge of the clock.'" "0,1" bitfld.long 0x0 8. "TR_CFG_0,'Transmitter (value '1') or receiver (value '0') configuration bit for I2S channel 0. Sampled on the rising edge of the clock.'" "0,1" bitfld.long 0x0 7. "I2S_EN_7,'Enable bit for I2S channel 7. Value '0' causes reset signal for this channel (i2s_rst_7) configuration SFR bits for this channel are unchanged. Value '1' enables channel. Sampled on the rising edge of the clock.'" "0,1" bitfld.long 0x0 6. "I2S_EN_6,'Enable bit for I2S channel 6. Value '0' causes reset signal for this channel (i2s_rst_6) configuration SFR bits for this channel are unchanged. Value '1' enables channel. Sampled on the rising edge of the clock.'" "0,1" bitfld.long 0x0 5. "I2S_EN_5,'Enable bit for I2S channel 5. Value '0' causes reset signal for this channel (i2s_rst_5) configuration SFR bits for this channel are unchanged. Value '1' enables channel. Sampled on the rising edge of the clock.'" "0,1" newline bitfld.long 0x0 4. "I2S_EN_4,'Enable bit for I2S channel 4. Value '0' causes reset signal for this channel (i2s_rst_4) configuration SFR bits for this channel are unchanged. Value '1' enables channel. Sampled on the rising edge of the clock.'" "0,1" bitfld.long 0x0 3. "I2S_EN_3,'Enable bit for I2S channel 3. Value '0' causes reset signal for this channel (i2s_rst_3) configuration SFR bits for this channel are unchanged. Value '1' enables channel. Sampled on the rising edge of the clock.'" "0,1" bitfld.long 0x0 2. "I2S_EN_2,'Enable bit for I2S channel 2. Value '0' causes reset signal for this channel (i2s_rst_2) configuration SFR bits for this channel are unchanged. Value '1' enables channel. Sampled on the rising edge of the clock.'" "0,1" bitfld.long 0x0 1. "I2S_EN_1,'Enable bit for I2S channel 1. Value '0' causes reset signal for this channel (i2s_rst_1) configuration SFR bits for this channel are unchanged. Value '1' enables channel. Sampled on the rising edge of the clock.'" "0,1" bitfld.long 0x0 0. "I2S_EN_0,'Enable bit for I2S channel 0. Value '0' causes reset signal for this channel (i2s_rst_0) configuration SFR bits for this channel are unchanged. Value '1' enables channel. Sampled on the rising edge of the clock.'" "0,1" line.long 0x4 "I2S_INTR_STAT,'I2S Interrupt Status Register'" hexmask.long.word 0x4 16.--31. 1. "RESERVED0,'Not implemented. Return '0' when read.'" bitfld.long 0x4 15. "RFIFO_AFULL,'Receive FIFO almost full flag active HIGH. This flag is set to HIGH when RX FIFO becomes almost full (rising edge of 'almost full' condition). Updated on the rising edge of the clock. This bit can trigger the interrupt.'" "0,1" bitfld.long 0x4 14. "RFIFO_FULL,'Receive FIFO full flag active HIGH. This flag is set to HIGH when RX FIFO is full. Updated on the rising edge of the clock. This bit can trigger the interrupt.'" "0,1" bitfld.long 0x4 13. "RFIFO_AEMPTY,'Receive FIFO almost empty flag active HIGH. This flag is set to HIGH when RX FIFO becomes almost empty (rising edge of 'almost empty' condition). Updated on the rising edge of the clock. This bit can trigger the interrupt.'" "0,1" bitfld.long 0x4 12. "RFIFO_EMPTY,'Receive FIFO empty flag active HIGH. This flag is set to HIGH when RX FIFO is empty. Updated on the rising edge of the clock. This bit can trigger the interrupt.'" "0,1" newline bitfld.long 0x4 11. "TFIFO_AFULL,'Transmit FIFO almost full flag active HIGH. This flag is set to HIGH when TX FIFO becomes almost full (rising edge of 'almost full' condition). Updated on the rising edge of the clock. This bit can trigger the interrupt.'" "0,1" bitfld.long 0x4 10. "TFIFO_FULL,'Transmit FIFO full flag active HIGH. This flag is set to HIGH when TX FIFO is full. Updated on the rising edge of the clock. This bit can trigger the interrupt.'" "0,1" bitfld.long 0x4 9. "TFIFO_AEMPTY,'Transmit FIFO almost empty flag active HIGH. This flag is set to HIGH when TX FIFO becomes almost empty (rising edge of 'almost empty' condition). Updated on the rising edge of the clock. This bit can trigger the interrupt.'" "0,1" bitfld.long 0x4 8. "TFIFO_EMPTY,'Transmit FIFO empty flag active HIGH. This flag is set to HIGH when TX FIFO is empty. Updated on the rising edge of the clock. This bit can trigger the interrupt.'" "0,1" rbitfld.long 0x4 5.--7. "OVRERR_CODE,'Code of the receiver that caused overrun error. Updated on the rising edge of the clock. These bits are cleared when bit rdata_ovrerr is cleared. The code is a binary notation of the channel's number.'" "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 4. "RDATA_OVRERR,'Receiver data overrun error active HIGH. This flag is set to HIGH when RX overrun arises (rising edge of 'overrun' condition). Updated on the rising edge of the clock. This bit can trigger the interrupt. Writing a LOW value to this bit.." "0,1" rbitfld.long 0x4 1.--3. "UNDERR_CODE,'Code of the transmitter that caused underrun event. Updated on the rising edge of the clock. These bits are cleared when bit tdata_underr is cleared. The code is a binary notation of the channel's number.'" "0,1,2,3,4,5,6,7" bitfld.long 0x4 0. "TDATA_UNDERR,'Transmitter data underrun event active HIGH. This flag is set to HIGH when TX underrun arises (rising edge of 'underrun' condition). Updated on the rising edge of the clock. This bit can trigger the interrupt.'" "0,1" line.long 0x8 "I2S_SRR,'I2S Channels Sample Rate and Resolution Configuration Register'" hexmask.long.byte 0x8 27.--31. 1. "RRESOLUTION,'Receiver resolution (0 to 31). Sampled on the rising edge of the clock. It simply should be assigned the value equal to the number of valid bits minus one.'" hexmask.long.byte 0x8 23.--26. 1. "RESERVED1,'Not implemented. Return '0' when read.'" hexmask.long.byte 0x8 16.--22. 1. "RSAMPLE_RATE,'Receiver sample rate. Sampled on the rising edge of the clock.'" hexmask.long.byte 0x8 11.--15. 1. "TRESOLUTION,'Transmitter resolution (0 to 31). Sampled on the rising edge of the clock. It simply should be assigned the value equal to the number of valid bits minus one.'" hexmask.long.byte 0x8 7.--10. 1. "RESERVED0,'Not implemented. Return '0' when read.'" newline hexmask.long.byte 0x8 0.--6. 1. "TSAMPLE_RATE,'Transmitter sample rate. Sampled on the rising edge of the clock.'" line.long 0xC "CID_CTRL,'Clock. Interrupt and DMA Control Register'" bitfld.long 0xC 31. "RFIFO_AFULL_MASK,'Bit masking interrupt request generation after receive FIFO becomes almost full. When LOW masks generation of interrupt request. Sampled on the rising edge of the clock.'" "0,1" bitfld.long 0xC 30. "RFIFO_FULL_MASK,'Bit masking interrupt request generation after receive FIFO becomes full. When LOW masks generation of interrupt request. Sampled on the rising edge of the clock.'" "0,1" bitfld.long 0xC 29. "RFIFO_AEMPTY_MASK,'Bit masking interrupt request generation after receive FIFO becomes almost empty. When LOW masks generation of interrupt request. Sampled on the rising edge of the clock.'" "0,1" bitfld.long 0xC 28. "RFIFO_EMPTY_MASK,'Bit masking interrupt request generation after receive FIFO becomes empty. When LOW masks generation of interrupt request. Sampled on the rising edge of the clock.'" "0,1" bitfld.long 0xC 27. "TFIFO_AFULL_MASK,'Bit masking interrupt request generation after transmit FIFO becomes almost full. When LOW masks generation of interrupt request. Sampled on the rising edge of the clock.'" "0,1" newline bitfld.long 0xC 26. "TFIFO_FULL_MASK,'Bit masking interrupt request generation after transmit FIFO becomes full. When LOW masks generation of interrupt request. Sampled on the rising edge of the clock.'" "0,1" bitfld.long 0xC 25. "TFIFO_AEMPTY_MASK,'Bit masking interrupt request generation after transmit FIFO becomes almost empty. When LOW masks generation of interrupt request. Sampled on the rising edge of the clock.'" "0,1" bitfld.long 0xC 24. "TFIFO_EMPTY_MASK,'Bit masking interrupt request generation after transmit FIFO becomes empty. When LOW masks generation of interrupt request. Sampled on the rising edge of the clock.'" "0,1" bitfld.long 0xC 23. "I2S_MASK_7,'Bit masking interrupt request generation after underrun / overrun condition occurrence in I2S channel 7. When LOW masks generation of interrupt request caused by the channel 7. Sampled on the rising edge of the clock.'" "0,1" bitfld.long 0xC 22. "I2S_MASK_6,'Bit masking interrupt request generation after underrun / overrun condition occurrence in I2S channel 6. When LOW masks generation of interrupt request caused by the channel 6. Sampled on the rising edge of the clock.'" "0,1" newline bitfld.long 0xC 21. "I2S_MASK_5,'Bit masking interrupt request generation after underrun / overrun condition occurrence in I2S channel 5. When LOW masks generation of interrupt request caused by the channel 5. Sampled on the rising edge of the clock.'" "0,1" bitfld.long 0xC 20. "I2S_MASK_4,'Bit masking interrupt request generation after underrun / overrun condition occurrence in I2S channel 4. When LOW masks generation of interrupt request caused by the channel 4. Sampled on the rising edge of the clock.'" "0,1" bitfld.long 0xC 19. "I2S_MASK_3,'Bit masking interrupt request generation after underrun / overrun condition occurrence in I2S channel 3. When LOW masks generation of interrupt request caused by the channel 3. Sampled on the rising edge of the clock.'" "0,1" bitfld.long 0xC 18. "I2S_MASK_2,'Bit masking interrupt request generation after underrun / overrun condition occurrence in I2S channel 2. When LOW masks generation of interrupt request caused by the channel 2. Sampled on the rising edge of the clock.'" "0,1" bitfld.long 0xC 17. "I2S_MASK_1,'Bit masking interrupt request generation after underrun / overrun condition occurrence in I2S channel 1. When LOW masks generation of interrupt request caused by the channel 1. Sampled on the rising edge of the clock.'" "0,1" newline bitfld.long 0xC 16. "I2S_MASK_0,'Bit masking interrupt request generation after underrun / overrun condition occurrence in I2S channel 0. When LOW masks generation of interrupt request caused by the channel 0. Sampled on the rising edge of the clock.'" "0,1" bitfld.long 0xC 15. "INTREQ_MASK,'Bit masking all interrupt requests. When '0' all interrupts are masked when '1' interrupts use individual masks. Sampled on the rising edge of the clock.'" "0,1" hexmask.long.byte 0xC 10.--14. 1. "RESERVED0,'Not implemented. Return '0' when read.'" bitfld.long 0xC 9. "STROBE_RS,'Clock enable for the unit synchronizing receivers. When high the clk_rs clock is blocked else it is enabled. Sampled on the rising edge of the clock.'" "0,1" bitfld.long 0xC 8. "STROBE_TS,'Clock enable for the unit synchronizing transmitters. When high the clk_ts clock is blocked else it is enabled. Sampled on the rising edge of the clock.'" "0,1" newline bitfld.long 0xC 7. "I2S_STROBE_7,'Clock enable channel 7. When high the clk_7 clock is blocked else it is enabled. Sampled on the rising edge of the clock.'" "0,1" bitfld.long 0xC 6. "I2S_STROBE_6,'Clock enable channel 6. When high the clk_6 clock is blocked else it is enabled. Sampled on the rising edge of the clock.'" "0,1" bitfld.long 0xC 5. "I2S_STROBE_5,'Clock enable channel 5. When high the clk_5 clock is blocked else it is enabled. Sampled on the rising edge of the clock.'" "0,1" bitfld.long 0xC 4. "I2S_STROBE_4,'Clock enable channel 4. When high the clk_4 clock is blocked else it is enabled. Sampled on the rising edge of the clock.'" "0,1" bitfld.long 0xC 3. "I2S_STROBE_3,'Clock enable channel 3. When high the clk_3 clock is blocked else it is enabled. Sampled on the rising edge of the clock.'" "0,1" newline bitfld.long 0xC 2. "I2S_STROBE_2,'Clock enable channel 2. When high the clk_2 clock is blocked else it is enabled. Sampled on the rising edge of the clock.'" "0,1" bitfld.long 0xC 1. "I2S_STROBE_1,'Clock enable channel 1. When high the clk_1 clock is blocked else it is enabled. Sampled on the rising edge of the clock.'" "0,1" bitfld.long 0xC 0. "I2S_STROBE_0,'Clock enable channel 0. When high the clk_0 clock is blocked else it is enabled. Sampled on the rising edge of the clock.'" "0,1" line.long 0x10 "TFIFO_STAT,'Transmit FIFO Status Register'" hexmask.long.tbyte 0x10 10.--31. 1. "RESERVED0,'Not implemented. Return '0' when read.'" hexmask.long.word 0x10 0.--9. 1. "TLEVEL,'Indicates transmit FIFO level. Updated on the rising edge of the clock.'" line.long 0x14 "RFIFO_STAT,'Receive FIFO Status Register'" hexmask.long.tbyte 0x14 10.--31. 1. "RESERVED0,'Not implemented. Return '0' when read.'" hexmask.long.word 0x14 0.--9. 1. "RLEVEL,'Indicates receive FIFO level. Updated on the rising edge of the clock.'" line.long 0x18 "TFIFO_CTRL,'Transmit FIFO Control Register'" hexmask.long.word 0x18 20.--31. 1. "RESERVED1,'Not implemented. Return '0' when read.'" hexmask.long.byte 0x18 16.--19. 1. "TAFULL_THRESHOLD,'Determines threshold for almost full flag in the transmit FIFO. Sampled on the rising edge of the clock.'" hexmask.long.word 0x18 4.--15. 1. "RESERVED0,'Not implemented. Return '0' when read.'" hexmask.long.byte 0x18 0.--3. 1. "TAEMPTY_THRESHOLD,'Determines threshold for almost empty flag in the transmit FIFO. Sampled on the rising edge of the clock.'" line.long 0x1C "RFIFO_CTRL,'Receive FIFO Control Register'" hexmask.long.word 0x1C 20.--31. 1. "RESERVED1,'Not implemented. Return '0' when read.'" hexmask.long.byte 0x1C 16.--19. 1. "RAFULL_THRESHOLD,'Determines threshold for almost full flag in the receive FIFO. Sampled on the rising edge of the clock.'" hexmask.long.word 0x1C 4.--15. 1. "RESERVED0,'Not implemented. Return '0' when read.'" hexmask.long.byte 0x1C 0.--3. 1. "RAEMPTY_THRESHOLD,'Determines threshold for almost empty flag in the receive FIFO. Sampled on the rising edge of the clock.'" line.long 0x20 "DEV_CONF,'Device Configuration Register'" hexmask.long.tbyte 0x20 12.--31. 1. "RESERVED0,'Not implemented. Return '0' when read.'" bitfld.long 0x20 11. "REC_WS_DSP_MODE,'The word select signal format change indicator according to the DSP audio interface specification for the receiver units. HIGH value of this bit determines generation of the word select signal format specific to the DSP audio interface.." "0,1" bitfld.long 0x20 10. "REC_DATA_WS_DEL,'The received valid data delay indicator at the I2S serial data input line after the word select signal edge. When HIGH the received serial data are updated on the second rising/falling edge of the clock signal after the word select.." "0,1" bitfld.long 0x20 9. "REC_I2S_ALIGN_LR,'Alignment of the received digital data sample at the I2S serial data line. When HIGH it determines the MSB adjustment of the resolution-width received digital data sample at the I2S serial data input line. If the received data sample.." "0,1" bitfld.long 0x20 8. "REC_APB_ALIGN_LR,'Alignment of the received digital data sample at the APB bus. HIGH value of this bit determines the MSB side alignment of the resolution-width received data sample at the APB data bus. LOW value of this bit determines the LSB side.." "0,1" newline bitfld.long 0x20 7. "REC_WS_POLAR,'The word select signal polarity selection for reception. When HIGH the level of the word select signal for the received left channel data sample is '1' and the level of this signal for the received right channel data sample is '0'. When.." "0,1" bitfld.long 0x20 6. "REC_SCK_POLAR,'The continuous serial clock active edge for reception. When HIGH the received serial data are sampled on the falling edge of the bit clock. When LOW the received serial data are sampled on the rising edge of the bit clock. Default value.." "0,1" bitfld.long 0x20 5. "TRAN_WS_DSP_MODE,'The word select signal format change indicator according to the DSP audio interface specification for the transmitter units. HIGH value of this bit determines generation of the word select signal format specific to the DSP audio.." "0,1" bitfld.long 0x20 4. "TRAN_DATA_WS_DEL,'The transmitted valid data delay indicator at the I2S serial data output line after the word select signal edge. When HIGH the serial data for transmission are updated on the first rising/falling edge of the clock signal after the word.." "0,1" bitfld.long 0x20 3. "TRAN_I2S_ALIGN_LR,'Alignment of the transmitted digital data sample at the I2S serial data line. When HIGH it determines the MSB adjustment of the resolution-width transmitted digital data sample at the I2S serial data output line. If the transmitted.." "0,1" newline bitfld.long 0x20 2. "TRAN_APB_ALIGN_LR,'Alignment of the transmitted digital data sample at the APB bus. HIGH value of this bit determines the MSB side alignment of the resolution-width transmitted data sample at the APB data bus. LOW value of this bit determines the LSB.." "0,1" bitfld.long 0x20 1. "TRAN_WS_POLAR,'The word select signal polarity selection for transmission. When HIGH the level of the word select signal for the transmitted left channel data sample is '1' and the level of this signal for the transmitted right channel data sample is.." "0,1" bitfld.long 0x20 0. "TRAN_SCK_POLAR,'The continuous serial clock active edge for transmission. When HIGH the serial data for transmission are updated on the falling edge of the bit clock. When LOW the serial data for transmission are updated on the rising edge of the bit.." "0,1" line.long 0x24 "I2S_POLL_STAT,'The I2S status register for controlling the IP by polling is read only special function register. All used bits reflect current status of FIFO flags. data overrun and data underrun.'" hexmask.long 0x24 7.--31. 1. "RESERVED1,'Not implemented. Return '0' when read.'" bitfld.long 0x24 6. "RX_OVERRUN,'Receiver data overrun: 1 - RX data overrun has occurred 0 - No RX data overrun Updated on the rising edge of the clock. '" "0,1" bitfld.long 0x24 5. "RX_AFULL,'Receive FIFO almost full flag: 1 - RX FIFO is almost full 0 - RX FIFO is not almost full Updated on the rising edge of the clock.'" "0,1" bitfld.long 0x24 4. "RX_FULL,'Receive FIFO full flag: 1 - RX FIFO is full 0 - RX FIFO is not full Updated on the rising edge of the clock.'" "0,1" bitfld.long 0x24 3. "RESERVED0,'Not implemented. Return '0' when read.'" "0,1" newline bitfld.long 0x24 2. "TX_UNDERRUN,'Transmitter data underrun: 1 - TX data underrun has occurred 0 - No TX data underrun Updated on the rising edge of the clock.'" "0,1" bitfld.long 0x24 1. "TX_AEMPTY,'Transmit FIFO almost empty flag: 1 - TX FIFO is almost empty 0 - TX FIFO is not almost empty Updated on the rising edge of the clock.'" "0,1" bitfld.long 0x24 0. "TX_EMPTY,'Transmit FIFO empty flag: 1 - TX FIFO is empty 0 - TX FIFO is not empty Updated on the rising edge of the clock.'" "0,1" tree.end repeat.end repeat 8. (increment 1. 1.) (list ad:0x30300000 ad:0x30310000 ad:0x30600000 ad:0x30610000 ad:0x30620000 ad:0x30630000 ad:0x30640000 ad:0x30650000) tree "I2S_SC$1" base $2 group.long 0x0++0x17 line.long 0x0 "I2S_CTRL,'I2S control register. After end of reset bit sfr_rst triggers to 1 and bit fifo_rst triggers to 1. Therefore register value after end of reset is 000001B8'" bitfld.long 0x0 31. "LR_PACK,Left/Right packing mode enable When HIGH the Left/Right packing mode is enabled and then the left audio channel sample data is created from less significant bits of FIFO data..Respectively the right audio channel sample data is created from.." "0,1" bitfld.long 0x0 30. "FIFO_AFULL_MASK,Bit masking interrupt request generation after full-duplex mode receive FIFO becomes almost full. When LOW masks generation of interrupt request." "0,1" bitfld.long 0x0 29. "FIFO_FULL_MASK,Bit masking interrupt request generation after full-duplex mode receive FIFO becomes full. When LOW masks generation of interrupt request." "0,1" bitfld.long 0x0 28. "FIFO_AEMPTY_MASK,Bit masking interrupt request generation after full-duplex mode receive FIFO becomes almost empty. When LOW masks generation of interrupt request." "0,1" bitfld.long 0x0 27. "FIFO_EMPTY_MASK,Bit masking interrupt request generation after FIFO becomes empty. When LOW masks generation of interrupt request.When full-duplex mode is active this bit is a mask only for transmitter FIFO empty condition. Sampled on the rising edge.." "0,1" newline bitfld.long 0x0 26. "I2S_MASK,Bit masking interrupt request generation after underrun/overrun condition occurrence in I2S-SC transceiver. When LOW masks generation of interrupt request.When full-duplex mode is active this bit is a mask only for underrun event interrupt." "0,1" bitfld.long 0x0 25. "INTREQ_MASK,Bit masking all interrupt requests. When LOW all interrupts are masked when HIGH interrupts use individual masks. Sampled on the rising edge of the clock." "0,1" bitfld.long 0x0 24. "I2S_STB,Transceiver clock enable. When LOW the clk_i2s clock is enabled else clock is disabled. Sampled on the rising edge of the clock." "0,1" bitfld.long 0x0 23. "HOST_DATA_ALIGN,Audio data sample alignment at host data bus. When LOW the audio sample data is aligned to the LSB at the host data bus. When HIGH the audio sample data is aligned to the MSB at host data bus. Sampled on the rising edge of the clock." "0,1" bitfld.long 0x0 22. "DATA_ORDER,Audio data sample arrangement in audio data slot. When LOW audio sample arrangement in audio data slot is MSB-first. When HIGH audio sample arrangement in audio data slot is LSB-first. Sampled on the rising edge of the clock." "0,1" newline bitfld.long 0x0 21. "DATA_ALIGN,Audio sample alignment in audio data time slot. When LOW the audio sample bits are left justified in audio data time slot. When HIGH the audio sample bits are right justified in audio data time slot. Sampled on the rising edge of the clock." "0,1" hexmask.long.byte 0x0 16.--20. 1. "DATA_WS_DEL,Audio data delay after WS signal edge at serial line. TDM mode is not active: Value from 0...(CHN_WIDTH-1) range specified that first audio data bit is updated/received at the first second...last edge of the SCK signal after the WS signal.." bitfld.long 0x0 15. "WS_POLAR,The word select signal polarity selection. I2S Word Select (WS) mode is active: When HIGH the level of the word select signal for the left channel data sample is '1' and the level of this signal for the right channel data sample is '0'. When.." "0,1" bitfld.long 0x0 14. "SCK_POLAR,The continuous serial clock active edge. When HIGH the serial data are updated on the falling edge of the bit clock.When LOW serial data are updated on the rising edge of the bit clock. Sampled on the rising edge of the clock." "0,1" bitfld.long 0x0 13. "AUDIO_MODE,Mono/stereo audio mode selection. Active only when TDM mode is inactive and I2S-SC works at standard stereo audio interface mode. When LOW both left and right channel audio samples are transmitted/received for transmitter/receiver mode.." "0,1" newline bitfld.long 0x0 12. "MONO_MODE,Active audio channel in mono mode. When LOW left audio channel is active. When HIGH right audio channel is active. Sampled on the rising edge of the clock." "0,1" hexmask.long.byte 0x0 8.--11. 1. "WS_MODE,Word select signal (WS) format. TDM mode is not active: Only bit 8 is relevant. If it is set to LOW (even value of ws_mode) WS signal have DSP audio interface specification format. If it is set to HIGH (odd value of ws_mode) WS signal have.." bitfld.long 0x0 5.--7. "CHN_WIDTH,Audio channel time slot width in I2S master or DSP/TDM master and slave modes. 0 - 8 SCK cycles per audio channel 1 - 12 SCK cycles per audio channel 2 - 16 SCK cycles per audio channel 3 - 18 SCK cycles per audio channel 4 - 20 SCK cycles per.." "0,1,2,3,4,5,6,7" bitfld.long 0x0 4. "FIFO_RST,Full-duplex mode receiver FIFO reset. Active only in full-duplex mode. When '0' RFIFO pointer is reset to zero. Threshold levels for RFIFO are unchanged. The bit is automatically set to '1' after one clock cycle." "0,1" bitfld.long 0x0 3. "SFR_RST,SFR block synchronous reset. When LOW all bits in SFR registers are reset to default values. This bit is automatically set to HIGH after one clock cycle. Sampled on the rising edge of the clock." "0,1" newline bitfld.long 0x0 2. "MS_CFG,Configuration bit for transceiver synchronizing unit: 1 - Master 0 - Slave Sampled on the rising edge of the clock." "0,1" bitfld.long 0x0 1. "DIR_CFG,Hal-duplex direction of transmission: 1 - Transmitter 0 - Receiver Sampled on the rising edge of the clock." "0,1" bitfld.long 0x0 0. "I2S_EN,Enable bit for I2S transceiver 1 - enables transceiver 0 - disables transceiver causes reset signal configuration SFR bits are unchanged Sampled on the rising edge of the clock." "0,1" line.long 0x4 "I2S_CTRL_FDX,'I2S Full-Duplex Mode Control register. After end of reset bit fifo_rst triggers to 1. Therefore register value after end of reset is 00000010'" bitfld.long 0x4 30. "RFIFO_AFULL_MASK,Bit masking interrupt request generation after full-duplex mode receive FIFO becomes almost full.When LOW masks generation of interrupt request." "0,1" bitfld.long 0x4 29. "RFIFO_FULL_MASK,Bit masking interrupt request generation after full-duplex mode receive FIFO becomes full. When LOW masks generation of interrupt request." "0,1" bitfld.long 0x4 28. "RFIFO_AEMPTY_MASK,Bit masking interrupt request generation after full-duplex mode receive FIFO becomes almost empty.When LOW masks generation of interrupt request." "0,1" bitfld.long 0x4 27. "RFIFO_EMPTY_MASK,Bit masking interrupt request generation after full-duplex mode receive FIFO becomes empty. When LOW masks generation of interrupt request." "0,1" newline bitfld.long 0x4 26. "RI2S_MASK,Bit masking interrupt request generation after overrun condition occurrence in I2S-SC full-duplex mode receiver. When LOW masks generation of interrupt request." "0,1" bitfld.long 0x4 4. "FIFO_RST,Full-duplex mode receiver FIFO reset. Active only in full-duplex mode. When '0' RFIFO pointer is reset to zero. Threshold levels for RFIFO are unchanged. The bit is automatically set to '1' after one clock cycle." "0,1" bitfld.long 0x4 2. "I2S_FRX_EN,Full-duplex mode receiver enable When full_duplex mode enable bit is active the bit controls receiving data through sdi serial data input.Otherwise the bit setup is not applicable." "0,1" newline bitfld.long 0x4 1. "I2S_FTX_EN,Full-duplex mode transmitter enable When full_duplex mode enable bit is active the bit controls transmitting data through sdo serial data output. Otherwise the bit setup is not applicable." "0,1" bitfld.long 0x4 0. "FULL_DUPLEX,Full-duplex mode enable When HIGH transmitter and receiver data units enable are controlled dynamically by the i2s_ftx_en (I2S_CTRL_FDX[1]) and i2s_frx_en (I2S_CTRL_FDX[2]) bits. Modifiable only when I2S transceiver is disabled (i2s_en bit of.." "0,1" line.long 0x8 "I2S_SRES,'Transceiver Sample Resolution'" hexmask.long.byte 0x8 0.--4. 1. "RESOLUTION,Samples resolution. When full-duplex mode is active this value specifies resolution only for transmitted samples. Sampled on the rising edge of the clock. It simply should be assigned the value equal to the number of valid bits minus one for.." line.long 0xC "I2S_SRES_FDR,'Full Duplex Mode Receive Samples Resolution'" hexmask.long.byte 0xC 0.--4. 1. "RRESOLUTION,Full-duplex mode receive samples resolution. When half-duplex mode is active this value is ignored. It simply should be assigned the value equal to the number of valid bits minus one for example: 00000 B - sample resolution = 1 bit 11111 B -.." line.long 0x10 "I2S_SRATE,'Transceiver Sample Rate'" hexmask.long.tbyte 0x10 0.--19. 1. "SAMPLE_RATE,In general value of sample rate is the quotient of clk frequency and I2S rate [bit/s]. The value of sample rate is the higher the clk frequency is greater than I2S rate." line.long 0x14 "I2S_STAT,'I2S-SC Status Flags Register'" bitfld.long 0x14 19. "RFIFO_AFULL,Receive FIFO almost full flag in full-duplex mode. Active HIGH. This flag is set to HIGH when RX FIFO becomes almost full (rising edge of 'almost full' condition). This bit can trigger the interrupt." "0,1" bitfld.long 0x14 18. "RFIFO_FULL,Receive FIFO full flag in full-duplex mode. Active HIGH. This flag is set to HIGH when RX FIFO is full. This bit can trigger the interrupt." "0,1" bitfld.long 0x14 17. "RFIFO_AEMPTY,Receive FIFO almost empty flag in full-duplex mode. Active HIGH. This flag is set to HIGH when RX FIFO becomes almost empty (rising edge of 'almost empty' condition). This bit can trigger the interrupt." "0,1" bitfld.long 0x14 16. "RFIFO_EMPTY,Receive FIFO empty flag in full-duplex mode.Active HIGH. This flag is set to HIGH when RX FIFO is empty. This bit can trigger the interrupt." "0,1" newline hexmask.long.word 0x14 6.--15. 1. "RESERVED," bitfld.long 0x14 5. "FIFO_AFULL,FIFO almost full flag. Active HIGH. This flag is set to HIGH when FIFO becomes almost full (rising edge of 'almost full' condition). When full-duplex mode is active this bit is a flag only for transmitter FIFO almost full condition. This bit.." "0,1" bitfld.long 0x14 4. "FIFO_FULL,FIFO full flag. Active HIGH. This flag is set to HIGH when FIFO is full. When full-duplex mode is active this bit is a flag only for transmitter FIFO full condition. This bit can trigger the interrupt." "0,1" bitfld.long 0x14 3. "FIFO_AEMPTY,FIFO almost empty flag. Active HIGH. This flag is set to HIGH when FIFO becomes almost empty (rising edge of 'almost empty' condition). When full-duplex mode is active this bit is a flag only for transmitter FIFO almost empty condition. This.." "0,1" bitfld.long 0x14 2. "FIFO_EMPTY,FIFO empty flag. Active HIGH. This flag is set to HIGH when FIFO is empty. When full-duplex mode is active this bit is a flag only for transmitter FIFO empty condition. This bit can trigger the interrupt." "0,1" newline bitfld.long 0x14 1. "RDATA_OVRERR,Indicates data overrun event in receiver mode active HIGH. This flag is set to HIGH when RX overrun arises (rising edge of 'overrun'condition). Updated on the rising edge of the clock. This bit can trigger the interrupt." "0,1" bitfld.long 0x14 0. "TDATA_UNDERR,Indicates data underrun event active HIGH. This flag is set to HIGH when TX underrun arises (rising edge of 'underrun'condition). Updated on the rising edge of the clock. This bit can trigger the interrupt." "0,1" rgroup.long 0x18++0x3 line.long 0x0 "FIFO_LEVEL,'FIFO Using Level Register (read only)'" hexmask.long.byte 0x0 0.--7. 1. "FIFO_LEVEL,FIFO Using Level Register (read only)" group.long 0x1C++0x7 line.long 0x0 "FIFO_AEMPTY,'FIFO Almost Empty Level'" hexmask.long.byte 0x0 0.--6. 1. "AEMPTY_THRESHOLD,Determines threshold for almost empty flag in the FIFO. When full-duplex mode is active this register specifies an almost empty level of the transmitter FIFO level. Sampled on the rising edge of the clock." line.long 0x4 "FIFO_AFULL,'FIFO Almost Empty Level'" hexmask.long.byte 0x4 0.--6. 1. "AFULL_THRESHOLD,Determines threshold for almost full flag in the FIFO. When full-duplex mode is active this register specifies an almost full level of the transmitter FIFO level. Sampled on the rising edge of the clock." rgroup.long 0x24++0x3 line.long 0x0 "FIFO_LEVEL_FDR,'Full-Duplex Mode Receiver FIFO Level Register (read only)'" hexmask.long.byte 0x0 0.--7. 1. "FIFO_LEVEL,FIFO Using Level Register (read only)" group.long 0x28++0xF line.long 0x0 "FIFO_AEMPTY_FDR,'Full-Duplex Mode Receiver FIFO Almost Empty Level'" hexmask.long.byte 0x0 0.--6. 1. "AEMPTY_THRESHOLD,Determines threshold for almost empty flag in the FIFO. When full-duplex mode is active this register specifies an almost empty level of the transmitter FIFO level. Sampled on the rising edge of the clock." line.long 0x4 "FIFO_AFULL_FDR,'Full-Duplex Mode Receiver FIFO Almost Full Level'" hexmask.long.byte 0x4 0.--6. 1. "AFULL_THRESHOLD,Determines threshold for almost full flag in the FIFO. When full-duplex mode is active this register specifies an almost full level of the transmitter FIFO level. Sampled on the rising edge of the clock." line.long 0x8 "TDM_CTRL,'Time Division Multiplexing Control Register'" bitfld.long 0x8 31. "CH15_EN,TDM interface channel 15 activating bit. When HIGH 15th time slot sample is transmitted and/or received depending on transceiver mode. Sampled on the rising edge of the clock." "0,1" bitfld.long 0x8 30. "CH14_EN,TDM interface channel 14 activating bit. When HIGH 14th time slot sample is transmitted and/or received depending on transceiver mode. Sampled on the rising edge of the clock." "0,1" bitfld.long 0x8 29. "CH13_EN,TDM interface channel 13 activating bit. When HIGH 13th time slot sample is transmitted and/or received depending on transceiver mode. Sampled on the rising edge of the clock." "0,1" bitfld.long 0x8 28. "CH12_EN,TDM interface channel 12 activating bit. When HIGH 12th time slot sample is transmitted and/or received depending on transceiver mode. Sampled on the rising edge of the clock." "0,1" bitfld.long 0x8 27. "CH11_EN,TDM interface channel 11 activating bit. When HIGH 11th time slot sample is transmitted and/or received depending on transceiver mode. Sampled on the rising edge of the clock." "0,1" newline bitfld.long 0x8 26. "CH10_EN,TDM interface channel 10 activating bit. When HIGH 10th time slot sample is transmitted and/or received depending on transceiver mode. Sampled on the rising edge of the clock." "0,1" bitfld.long 0x8 25. "CH9_EN,TDM interface channel 9 activating bit. When HIGH 9th time slot sample is transmitted and/or received depending on transceiver mode. Sampled on the rising edge of the clock." "0,1" bitfld.long 0x8 24. "CH8_EN,TDM interface channel 8 activating bit. When HIGH 8th time slot sample is transmitted and/or received depending on transceiver mode. Sampled on the rising edge of the clock." "0,1" bitfld.long 0x8 23. "CH7_EN,TDM interface channel 7 activating bit. When HIGH 7th time slot sample is transmitted and/or received depending on transceiver mode. Sampled on the rising edge of the clock." "0,1" bitfld.long 0x8 22. "CH6_EN,TDM interface channel 6 activating bit. When HIGH 6th time slot sample is transmitted and/or received depending on transceiver mode. Sampled on the rising edge of the clock." "0,1" newline bitfld.long 0x8 21. "CH5_EN,TDM interface channel 5 activating bit. When HIGH 5th time slot sample is transmitted and/or received depending on transceiver mode. Sampled on the rising edge of the clock." "0,1" bitfld.long 0x8 20. "CH4_EN,TDM interface channel 4 activating bit. When HIGH 4th time slot sample is transmitted and/or received depending on transceiver mode. Sampled on the rising edge of the clock." "0,1" bitfld.long 0x8 19. "CH3_EN,TDM interface channel 3 activating bit. When HIGH 3th time slot sample is transmitted and/or received depending on transceiver mode. Sampled on the rising edge of the clock." "0,1" bitfld.long 0x8 18. "CH2_EN,TDM interface channel 2 activating bit. When HIGH 2nd time slot sample is transmitted and/or received depending on transceiver mode. Sampled on the rising edge of the clock." "0,1" bitfld.long 0x8 17. "CH1_EN,TDM interface channel 1 activating bit. When HIGH 1st time slot sample is transmitted and/or received depending on transceiver mode. Sampled on the rising edge of the clock." "0,1" newline bitfld.long 0x8 16. "CH0_EN,TDM interface channel 0 activating bit. When HIGH zero time slot sample is transmitted and/or received depending on transceiver mode. Sampled on the rising edge of the clock." "0,1" hexmask.long.byte 0x8 1.--4. 1. "CHN_NO,Number of supported audio channels in TDM compatible interface mode. Written value equals channels number minus 1. Sampled on the rising edge of the clock" bitfld.long 0x8 0. "TDM_EN,Time Division Multiplexing audio interface enable. When HIGH audio interface works in TDM compatible mode determined by this register value. When LOW audio interface works in standard stereo I 2 S mode. Sampled on the rising edge of the clock." "0,1" line.long 0xC "TDM_FD_DIR,'Time Division Multiplexing Full-Duplex Mode Channels Direction Register'" bitfld.long 0xC 31. "CH15_RXEN,TDM interface channel 15 receive enable bit. Active only in full-duplex mode. When HIGH and ch15_en bit in TDM_CTRL register is HIGH audio sample is received from sdi line at 15 time slot." "0,1" bitfld.long 0xC 30. "CH14_RXEN,TDM interface channel 14 receive enable bit. Active only in full-duplex mode. When HIGH and ch14_en bit in TDM_CTRL register is HIGH audio sample is received from sdi line at 14 time slot." "0,1" bitfld.long 0xC 29. "CH13_RXEN,TDM interface channel 13 receive enable bit. Active only in full-duplex mode. When HIGH and ch13_en bit in TDM_CTRL register is HIGH audio sample is received from sdi line at 13 time slot." "0,1" bitfld.long 0xC 28. "CH12_RXEN,TDM interface channel 12 receive enable bit. Active only in full-duplex mode. When HIGH and ch12_en bit in TDM_CTRL register is HIGH audio sample is received from sdi line at 12 time slot." "0,1" bitfld.long 0xC 27. "CH11_RXEN,TDM interface channel 11 receive enable bit. Active only in full-duplex mode. When HIGH and ch11_en bit in TDM_CTRL register is HIGH audio sample is received from sdi line at 11 time slot." "0,1" newline bitfld.long 0xC 26. "CH10_RXEN,TDM interface channel 10 receive enable bit. Active only in full-duplex mode. When HIGH and ch10_en bit in TDM_CTRL register is HIGH audio sample is received from sdi line at 10 time slot." "0,1" bitfld.long 0xC 25. "CH9_RXEN,TDM interface channel 9 receive enable bit. Active only in full-duplex mode. When HIGH and ch9_en bit in TDM_CTRL register is HIGH audio sample is received from sdi line at 9 time slot." "0,1" bitfld.long 0xC 24. "CH8_RXEN,TDM interface channel 8 receive enable bit. Active only in full-duplex mode. When HIGH and ch8_en bit in TDM_CTRL register is HIGH audio sample is received from sdi line at 8 time slot." "0,1" bitfld.long 0xC 23. "CH7_RXEN,TDM interface channel 7 receive enable bit. Active only in full-duplex mode. When HIGH and ch7_en bit in TDM_CTRL register is HIGH audio sample is received from sdi line at 7 time slot." "0,1" bitfld.long 0xC 22. "CH6_RXEN,TDM interface channel 6 receive enable bit. Active only in full-duplex mode. When HIGH and ch6_en bit in TDM_CTRL register is HIGH audio sample is received from sdi line at 6 time slot." "0,1" newline bitfld.long 0xC 21. "CH5_RXEN,TDM interface channel 5 receive enable bit. Active only in full-duplex mode. When HIGH and ch5_en bit in TDM_CTRL register is HIGH audio sample is received from sdi line at 5 time slot." "0,1" bitfld.long 0xC 20. "CH4_RXEN,TDM interface channel 4 receive enable bit. Active only in full-duplex mode. When HIGH and ch4_en bit in TDM_CTRL register is HIGH audio sample is received from sdi line at 4 time slot." "0,1" bitfld.long 0xC 19. "CH3_RXEN,TDM interface channel 3 receive enable bit. Active only in full-duplex mode. When HIGH and ch3_en bit in TDM_CTRL register is HIGH audio sample is received from sdi line at 3 time slot." "0,1" bitfld.long 0xC 18. "CH2_RXEN,TDM interface channel 2 receive enable bit. Active only in full-duplex mode. When HIGH and ch2_en bit in TDM_CTRL register is HIGH audio sample is received from sdi line at 2 time slot." "0,1" bitfld.long 0xC 17. "CH1_RXEN,TDM interface channel 1 receive enable bit. Active only in full-duplex mode. When HIGH and ch1_en bit in TDM_CTRL register is HIGH audio sample is received from sdi line at 1 time slot." "0,1" newline bitfld.long 0xC 16. "CH0_RXEN,TDM interface channel 0 receive enable bit. Active only in full-duplex mode. When HIGH and ch0_en bit in TDM_CTRL register is HIGH audio sample is received from sdi line at 0 time slot." "0,1" bitfld.long 0xC 15. "CH15_TXEN,TDM interface channel 15 transmit enable bit. Active only in full-duplex mode. When HIGH and ch15_en bit in TDM_CTRL register is HIGH audio sample is transmitted at 15 time slot through sdo line." "0,1" bitfld.long 0xC 14. "CH14_TXEN,TDM interface channel 14 transmit enable bit. Active only in full-duplex mode. When HIGH and ch14_en bit in TDM_CTRL register is HIGH audio sample is transmitted at 14 time slot through sdo line." "0,1" bitfld.long 0xC 13. "CH13_TXEN,TDM interface channel 13 transmit enable bit. Active only in full-duplex mode. When HIGH and ch13_en bit in TDM_CTRL register is HIGH audio sample is transmitted at 13 time slot through sdo line." "0,1" bitfld.long 0xC 12. "CH12_TXEN,TDM interface channel 12 transmit enable bit. Active only in full-duplex mode. When HIGH and ch12_en bit in TDM_CTRL register is HIGH audio sample is transmitted at 12 time slot through sdo line." "0,1" newline bitfld.long 0xC 11. "CH11_TXEN,TDM interface channel 11 transmit enable bit. Active only in full-duplex mode. When HIGH and ch11_en bit in TDM_CTRL register is HIGH audio sample is transmitted at 11 time slot through sdo line." "0,1" bitfld.long 0xC 10. "CH10_TXEN,TDM interface channel 10 transmit enable bit. Active only in full-duplex mode. When HIGH and ch10_en bit in TDM_CTRL register is HIGH audio sample is transmitted at 10 time slot through sdo line." "0,1" bitfld.long 0xC 9. "CH9_TXEN,TDM interface channel 9 transmit enable bit. Active only in full-duplex mode. When HIGH and ch9_en bit in TDM_CTRL register is HIGH audio sample is transmitted at 9 time slot through sdo line." "0,1" bitfld.long 0xC 8. "CH8_TXEN,TDM interface channel 8 transmit enable bit. Active only in full-duplex mode. When HIGH and ch8_en bit in TDM_CTRL register is HIGH audio sample is transmitted at 8 time slot through sdo line." "0,1" bitfld.long 0xC 7. "CH7_TXEN,TDM interface channel 7 transmit enable bit. Active only in full-duplex mode. When HIGH and ch7_en bit in TDM_CTRL register is HIGH audio sample is transmitted at 7 time slot through sdo line." "0,1" newline bitfld.long 0xC 6. "CH6_TXEN,TDM interface channel 6 transmit enable bit. Active only in full-duplex mode. When HIGH and ch6_en bit in TDM_CTRL register is HIGH audio sample is transmitted at 6 time slot through sdo line." "0,1" bitfld.long 0xC 5. "CH5_TXEN,TDM interface channel 5 transmit enable bit. Active only in full-duplex mode. When HIGH and ch5_en bit in TDM_CTRL register is HIGH audio sample is transmitted at 5 time slot through sdo line." "0,1" bitfld.long 0xC 4. "CH4_TXEN,TDM interface channel 4 transmit enable bit. Active only in full-duplex mode. When HIGH and ch4_en bit in TDM_CTRL register is HIGH audio sample is transmitted at 4 time slot through sdo line." "0,1" bitfld.long 0xC 3. "CH3_TXEN,TDM interface channel 3 transmit enable bit. Active only in full-duplex mode. When HIGH and ch3_en bit in TDM_CTRL register is HIGH audio sample is transmitted at 3 time slot through sdo line." "0,1" bitfld.long 0xC 2. "CH2_TXEN,TDM interface channel 2 transmit enable bit. Active only in full-duplex mode. When HIGH and ch2_en bit in TDM_CTRL register is HIGH audio sample is transmitted at 2 time slot through sdo line." "0,1" newline bitfld.long 0xC 1. "CH1_TXEN,TDM interface channel 1 transmit enable bit. Active only in full-duplex mode. When HIGH and ch1_en bit in TDM_CTRL register is HIGH audio sample is transmitted at 1 time slot through sdo line." "0,1" bitfld.long 0xC 0. "CH0_TXEN,TDM interface channel 0 transmit enable bit. Active only in full-duplex mode. When HIGH and ch0_en bit in TDM_CTRL register is HIGH audio sample is transmitted at 0 time slot through sdo line." "0,1" tree.end repeat.end endif tree.end tree "IRAMC (IRAM Controller)" sif (CORENAME()=="CORTEXR5F") repeat 5. (increment 1. 1.) (list ad:0xF01F0000 ad:0xF0710000 ad:0xF0720000 ad:0xF0730000 ad:0xF0CB0000) tree "IRAMC$1" base $2 group.long 0x0++0x23 line.long 0x0 "MEM_ERR_INT_STATUS,Memory ECC error interrupt status" bitfld.long 0x0 3. "RDATA_FATAL,It can report memory ECC correction issue and protect normal rdata internal path in iram_ctrl" "0,1" bitfld.long 0x0 2. "WR_RDATA_FATAL,It can report memory ECC correction issue and protect read-modify-write rdata internal path in iram_ctrl" "0,1" bitfld.long 0x0 1. "MUL_ERR,Indicate double bit errors are detected." "0,1" bitfld.long 0x0 0. "SIG_ERR,Indicate single bit error is detected." "0,1" line.long 0x4 "MEM_ERR_INT_STA_EN,Memory ECC error interrupt status enable" bitfld.long 0x4 3. "RDATA_FATAL_EN,Fatal normal rdata interrupt status enable." "0,1" bitfld.long 0x4 2. "WR_RDATA_FATAL_EN,Fatal read-modify-write rdata interrupt status enable." "0,1" bitfld.long 0x4 1. "MUL_ERR_EN,Multiple bit error interrupt status enable." "0,1" bitfld.long 0x4 0. "SIG_ERR_EN,Single bit error interrupt status enable." "0,1" line.long 0x8 "MEM_ERR_INT_SIG_EN,Memory ECC error interrupt signal enable" bitfld.long 0x8 3. "RDATA_FATAL_EN,Fatal normal rdata interrupt signal enable" "0,1" bitfld.long 0x8 2. "WR_RDATA_FATAL_EN,Fatal read-modify-write rdata interrupt signal enable." "0,1" bitfld.long 0x8 1. "MUL_ERR_EN,Multiple bits errors interrupt signal enable." "0,1" bitfld.long 0x8 0. "SIG_ERR_EN,Single bit error interrupt signal enable." "0,1" line.long 0xC "UNCERR_INT_STA,AXI bus uncorrectable error interrupt status" bitfld.long 0xC 31. "BREADY,Uncorrectable error for BREADY" "0,1" bitfld.long 0xC 27. "WSTRB_FATAL,It can report BIP ECC correction issue and protect wstrb internal path in iram_ctrl" "0,1" bitfld.long 0xC 26. "WDATA_FATAL,It can report BIP ECC correction issue and protect wdata internal path in iram_ctrl" "0,1" bitfld.long 0xC 25. "WVALID,Uncorrectable error for WVALID" "0,1" newline bitfld.long 0xC 24. "WEOBI,Uncorrectable error for WEOBI" "0,1" bitfld.long 0xC 22. "WCTL,Uncorrectable error for WCTL(WLAST WSTRB)" "0,1" bitfld.long 0xC 21. "WDATA,Uncorrectable error for WDATA" "0,1" bitfld.long 0xC 20. "RREADY,Uncorrectable error for RREADY" "0,1" newline bitfld.long 0xC 12. "AWVALID,Uncorrectable error for AWVALID" "0,1" bitfld.long 0xC 10. "AWCTL1,Uncorrectable error for AWCTL1(AWLOCK AWBURST AWSIZE AWLEN)" "0,1" newline bitfld.long 0xC 8. "AWADDR,Uncorrectable error for AWADDR" "0,1" bitfld.long 0xC 7. "AWID,Uncorrectable error for AWID" "0,1" bitfld.long 0xC 5. "ARVALID,Uncorrectable error for ARVALID" "0,1" newline bitfld.long 0xC 3. "ARCTL1,Uncorrectable error for ARCTL1(ARLOCK ARBURST ARSIZE ARLEN)" "0,1" bitfld.long 0xC 1. "ARADDR,Uncorrectable error for ARADDR" "0,1" bitfld.long 0xC 0. "ARID,Uncorrectable error for ARID" "0,1" line.long 0x10 "UNCERR_INT_STA_EN,AXI bus uncorrectable error interrupt status enable" bitfld.long 0x10 31. "BREADY,Status enable for BREADY uncorrectable error interrupt." "0,1" bitfld.long 0x10 27. "WSTRB_FATAL,Status enable for WSTRB_FATAL uncorrectable error interrupt." "0,1" bitfld.long 0x10 26. "WDATA_FATAL,Status enable for WDATA_FATAL uncorrectable error interrupt." "0,1" bitfld.long 0x10 25. "WVALID,Status enable for WVALID uncorrectable error interrupt." "0,1" newline bitfld.long 0x10 24. "WEOBI,Status enable for WEOBI uncorrectable error interrupt." "0,1" bitfld.long 0x10 22. "WCTL,Status enable for WCTL(WLAST WSTRB) uncorrectable error interrupt." "0,1" bitfld.long 0x10 21. "WDATA,Status enable for WDATA uncorrectable error interrupt." "0,1" bitfld.long 0x10 20. "RREADY,Status enable for RREADY uncorrectable error interrupt." "0,1" newline bitfld.long 0x10 12. "AWVALID,Status enable for AWVALID uncorrectable error interrupt." "0,1" bitfld.long 0x10 10. "AWCTL1,Status enable for AWCTL1(AWLOCK AWBURST AWSIZE AWLEN) uncorrectable error interrupt." "0,1" newline bitfld.long 0x10 8. "AWADDR,Status enable for AWADDR uncorrectable error interrupt." "0,1" bitfld.long 0x10 7. "AWID,Status enable for AWID uncorrectable error interrupt." "0,1" bitfld.long 0x10 5. "ARVALID,Status enable for ARVALID uncorrectable error interrupt." "0,1" newline bitfld.long 0x10 3. "ARCTL1,Status enable for ARCTL1(ARLOCK ARBURST ARSIZE ARLEN) uncorrectable error interrupt." "0,1" bitfld.long 0x10 1. "ARADDR,Status enable for ARADDR uncorrectable error interrupt." "0,1" bitfld.long 0x10 0. "ARID,Status enable for ARID uncorrectable error interrupt." "0,1" line.long 0x14 "UNCERR_INT_SIG_EN,AXI bus uncorrectable error interrupt signal enable" bitfld.long 0x14 31. "BREADY,Signal enable for BREADY uncorrectable error interrupt." "0,1" bitfld.long 0x14 27. "WSTRB_FATAL,Signal enable for WSTRB_FATAL uncorrectable error interrupt." "0,1" bitfld.long 0x14 26. "WDATA_FATAL,Signal enable for WDATA_FATAL uncorrectable error interrupt." "0,1" bitfld.long 0x14 25. "WVALID,Signal enable for WVALID uncorrectable error interrupt." "0,1" newline bitfld.long 0x14 24. "WEOBI,Signal enable for WEOBI uncorrectable error interrupt." "0,1" bitfld.long 0x14 22. "WCTL,Signal enable for WCTL(WLAST WSTRB) uncorrectable error interrupt." "0,1" bitfld.long 0x14 21. "WDATA,Signal enable for WDATA uncorrectable error interrupt." "0,1" bitfld.long 0x14 20. "RREADY,Signal enable for RREADY uncorrectable error interrupt." "0,1" newline bitfld.long 0x14 12. "AWVALID,Signal enable for AWVALID uncorrectable error interrupt." "0,1" bitfld.long 0x14 10. "AWCTL1,Signal enable for AWCTL1(AWLOCK AWBURST AWSIZE AWLEN) uncorrectable error interrupt." "0,1" newline bitfld.long 0x14 8. "AWADDR,Signal enable for AWADDR uncorrectable error interrupt." "0,1" bitfld.long 0x14 7. "AWID,Signal enable for AWID uncorrectable error interrupt." "0,1" bitfld.long 0x14 5. "ARVALID,Signal enable for ARVALID uncorrectable error interrupt." "0,1" newline bitfld.long 0x14 3. "ARCTL1,Signal enable for ARCTL1(ARLOCK ARBURST ARSIZE ARLEN) uncorrectable error interrupt." "0,1" bitfld.long 0x14 1. "ARADDR,Signal enable for ARADDR uncorrectable error interrupt." "0,1" bitfld.long 0x14 0. "ARID,Signal enable for ARID uncorrectable error interrupt." "0,1" line.long 0x18 "CORERR_INT_STA,AXI bus correctable error interrupt status" bitfld.long 0x18 3. "WDATA,Correctable error interrupt status for WDATA." "0,1" bitfld.long 0x18 1. "AWADDR,Correctable error interrupt status for AWADDR" "0,1" bitfld.long 0x18 0. "ARADDR,Correctable error interrupt status for ARADDR" "0,1" line.long 0x1C "CORERR_INT_STA_EN,AXI bus correctable error interrupt status enable" bitfld.long 0x1C 3. "WDATA,Status enable for WDATA correctable erorr interrupt." "0,1" bitfld.long 0x1C 1. "AWADDR,Status enable for AWADDR correctable erorr interrupt." "0,1" bitfld.long 0x1C 0. "ARADDR,Status enable for ARADDR correctable erorr interrupt." "0,1" line.long 0x20 "CORERR_INT_SIG_EN,AXI bus correctable error interrupt signal enable" bitfld.long 0x20 3. "WDATA,Signal enable for WDATA correctable erorr interrupt." "0,1" bitfld.long 0x20 1. "AWADDR,Signal enable for AWADDRcorrectable erorr interrupt." "0,1" bitfld.long 0x20 0. "ARADDR,Signal enable for ARADDR correctable erorr interrupt." "0,1" rgroup.long 0x40++0x27 line.long 0x0 "SIG_ERR_ADDR,This register is used to store access address when detect first single bit error." hexmask.long 0x0 0.--31. 1. "ADDR,Error addr" line.long 0x4 "SIG_ERR_DATA_31_0,This register is used to store error data[31:0] when detect first single bit error." hexmask.long 0x4 0.--31. 1. "DATA,Error data" line.long 0x8 "SIG_ERR_DATA_63_32,This register is used to store error data[63:32] when detect first single bit error." hexmask.long 0x8 0.--31. 1. "DATA,Error data" line.long 0xC "SIG_ERR_DATA_95_64,This register is used to store error data[95:64] when detect first single bit error." hexmask.long 0xC 0.--31. 1. "DATA,Error data" line.long 0x10 "SIG_ERR_DATA_127_96,This register is used to store error data[127:96] when detect first single bit error." hexmask.long 0x10 0.--31. 1. "DATA,Error data" line.long 0x14 "MUL_ERR_ADDR,This register is used to store access address when detect first multiple bits error." hexmask.long 0x14 0.--31. 1. "ADDR,Error address" line.long 0x18 "MUL_ERR_DATA_31_0,This register is used to store error data[31:0] when detect first multiple bits error." hexmask.long 0x18 0.--31. 1. "DATA,Error data" line.long 0x1C "MUL_ERR_DATA_63_32,This register is used to store error data[63:31] when detect first multiple bits error." hexmask.long 0x1C 0.--31. 1. "DATA,Error data" line.long 0x20 "MUL_ERR_DATA_95_64,This register is used to store error data[95:64] when detect first multiple bits error." hexmask.long 0x20 0.--31. 1. "DATA,Error data" line.long 0x24 "MUL_ERR_DATA_127_96,This register is used to store error data[127:96] when detect first multiple bits error." hexmask.long 0x24 0.--31. 1. "DATA,Error data" group.long 0x80++0x3 line.long 0x0 "DATA_INIT,This register is used to initializate all the ram data and ecc data" bitfld.long 0x0 31. "LOCK,Once this bit is set INIT and this bit can be not be written unless IRAM_CTRL is reset" "0,1" bitfld.long 0x0 0. "INIT,After this bit is set iram_ctrl will automatically initialize all the ram data and ecc data to 0. Once initialization is completed this bit will be auto cleared." "0,1" group.long 0x100++0x4F line.long 0x0 "BANK0_DATA_31_0_INJ,This register provides error injection on bank0 read data[31:0]" hexmask.long 0x0 0.--31. 1. "DATA_INJ,Error injection on read data" line.long 0x4 "BANK0_DATA_63_32_INJ,This register provides error injection on bank0 read data[63:32]" hexmask.long 0x4 0.--31. 1. "DATA_INJ,Error injection on read data" line.long 0x8 "BANK0_DATA_95_64_INJ,This register provides error injection on bank0 read data[95:64]" hexmask.long 0x8 0.--31. 1. "DATA_INJ,Error injection on read data" line.long 0xC "BANK0_DATA_127_96_INJ,This register provides error injection on bank0 read data[127:96]" hexmask.long 0xC 0.--31. 1. "DATA_INJ,Error injection on read data" line.long 0x10 "BANK1_DATA_31_0_INJ,This register provides error injection on bank1 read data[31:0]" hexmask.long 0x10 0.--31. 1. "DATA_INJ,Error injection on read data" line.long 0x14 "BANK1_DATA_63_32_INJ,This register provides error injection on bank1 read data[63:32]" hexmask.long 0x14 0.--31. 1. "DATA_INJ,Error injection on read data" line.long 0x18 "BANK1_DATA_95_64_INJ,This register provides error injection on bank1 read data[95:64]" hexmask.long 0x18 0.--31. 1. "DATA_INJ,Error injection on read data" line.long 0x1C "BANK1_DATA_127_96_INJ,This register provides error injection on bank1 read data[127:96]" hexmask.long 0x1C 0.--31. 1. "DATA_INJ,Error injection on read data" line.long 0x20 "BANK2_DATA_31_0_INJ,This register provides error injection on bank2 read data[31:0]" hexmask.long 0x20 0.--31. 1. "DATA_INJ,Error injection on read data" line.long 0x24 "BANK2_DATA_63_32_INJ,This register provides error injection on bank2 read data[63:32]" hexmask.long 0x24 0.--31. 1. "DATA_INJ,Error injection on read data" line.long 0x28 "BANK2_DATA_95_64_INJ,This register provides error injection on bank2 read data[95:64]" hexmask.long 0x28 0.--31. 1. "DATA_INJ,Error injection on read data" line.long 0x2C "BANK2_DATA_127_96_INJ,This register provides error injection on bank2 read data[127:96]" hexmask.long 0x2C 0.--31. 1. "DATA_INJ,Error injection on read data" line.long 0x30 "BANK3_DATA_31_0_INJ,This register provides error injection on bank3 read data[31:0]" hexmask.long 0x30 0.--31. 1. "DATA_INJ,Error injection on read data" line.long 0x34 "BANK3_DATA_63_32_INJ,This register provides error injection on bank3 read data[63:32]" hexmask.long 0x34 0.--31. 1. "DATA_INJ,Error injection on read data" line.long 0x38 "BANK3_DATA_95_64_INJ,This register provides error injection on bank0 read data[95:64]" hexmask.long 0x38 0.--31. 1. "DATA_INJ,Error injection on read data" line.long 0x3C "BANK3_DATA_127_96_INJ,This register provides error injection on bank3 read data[127:96]" hexmask.long 0x3C 0.--31. 1. "DATA_INJ,Error injection on read data" line.long 0x40 "BANK0_ECC_INJ,This register provides error injection on bank0 ecc code" hexmask.long.byte 0x40 8.--15. 1. "ECC_INJ1,Error injection on 8 ecc code for high 64 bits read data" hexmask.long.byte 0x40 0.--7. 1. "ECC_INJ0,Error injection on 8 ecc code for low 64 bits read data" line.long 0x44 "BANK1_ECC_INJ,This register provides error injection on bank1 ecc code" hexmask.long.byte 0x44 8.--15. 1. "ECC_INJ1,Error injection on 8 ecc code for high 64 bits read data" hexmask.long.byte 0x44 0.--7. 1. "ECC_INJ0,Error injection on 8 ecc code for low 64 bits read data" line.long 0x48 "BANK2_ECC_INJ,This register provides error injection on bank2 ecc code" hexmask.long.byte 0x48 8.--15. 1. "ECC_INJ1,Error injection on 8 ecc code for high 64 bits read data" hexmask.long.byte 0x48 0.--7. 1. "ECC_INJ0,Error injection on 8 ecc code for low 64 bits read data" line.long 0x4C "BANK3_ECC_INJ,This register provides error injection on bank3 ecc code" hexmask.long.byte 0x4C 8.--15. 1. "ECC_INJ1,Error injection on 8 ecc code for high 64 bits read data" hexmask.long.byte 0x4C 0.--7. 1. "ECC_INJ0,Error injection on 8 ecc code for low 64 bits read data" group.long 0x200++0x13 line.long 0x0 "RDATA_31_0_INJ,This register provides error injection on secded monitor read data[31:0]" hexmask.long 0x0 0.--31. 1. "DATA_INJ,Error injection on read data" line.long 0x4 "RDATA_63_32_INJ,This register provides error injection on secded monitor read data[63:31]" hexmask.long 0x4 0.--31. 1. "DATA_INJ,Error injection on read data" line.long 0x8 "RDATA_95_64_INJ,This register provides error injection on secded monitor read data[95:32]" hexmask.long 0x8 0.--31. 1. "DATA_INJ,Error injection on read data" line.long 0xC "RDATA_127_96_INJ,This register provides error injection on secded monitor read data[127:96]" hexmask.long 0xC 0.--31. 1. "DATA_INJ,Error injection on read data" line.long 0x10 "RECC_INJ,This register provides error injection on secded monitor read ecc code" hexmask.long.byte 0x10 8.--15. 1. "ECC_INJ1,Error injection on 8 ecc code for high 64 bits read data" hexmask.long.byte 0x10 0.--7. 1. "ECC_INJ0,Error injection on 8 ecc code for low 64 bits read data" group.long 0x220++0x13 line.long 0x0 "WDATA_31_0_INJ,This register provides error injection on secded monitor wdata data[31:0]" hexmask.long 0x0 0.--31. 1. "DATA_INJ,Error injection on read data" line.long 0x4 "WDATA_63_32_INJ,This register provides error injection on secded monitor wdata data[63:32]" hexmask.long 0x4 0.--31. 1. "DATA_INJ,Error injection on read data" line.long 0x8 "WDATA_95_64_INJ,This register provides error injection on secded monitor wdata data[95:64]" hexmask.long 0x8 0.--31. 1. "DATA_INJ,Error injection on read data" line.long 0xC "WDATA_127_96_INJ,This register provides error injection on secded monitor wdata data[127:96]" hexmask.long 0xC 0.--31. 1. "DATA_INJ,Error injection on read data" line.long 0x10 "WECC_INJ,This register provides error injection on secded monitor write ecc code" hexmask.long.byte 0x10 8.--15. 1. "ECC_INJ1,Error injection on 8 ecc code for high 64 bits read data" hexmask.long.byte 0x10 0.--7. 1. "ECC_INJ0,Error injection on 8 ecc code for low 64 bits read data" group.long 0x240++0x3 line.long 0x0 "WSTRB_INJ,This register provides error injection on ded monitor wstrb and wctl code" hexmask.long.byte 0x0 16.--20. 1. "WCTLCODE_INJ,Error injection on wctlcode" hexmask.long.word 0x0 0.--15. 1. "WTSTRB_INJ,Error injection on wstrb data" tree.end repeat.end elif (CORENAME()=="CORTEXA55") repeat 5. (increment 1. 1.) (list ad:0x301F0000 ad:0x30710000 ad:0x30720000 ad:0x30730000 ad:0x30CB0000) tree "IRAMC$1" base $2 group.long 0x0++0x23 line.long 0x0 "MEM_ERR_INT_STATUS,Memory ECC error interrupt status" bitfld.long 0x0 3. "RDATA_FATAL,It can report memory ECC correction issue and protect normal rdata internal path in iram_ctrl" "0,1" bitfld.long 0x0 2. "WR_RDATA_FATAL,It can report memory ECC correction issue and protect read-modify-write rdata internal path in iram_ctrl" "0,1" bitfld.long 0x0 1. "MUL_ERR,Indicate double bit errors are detected." "0,1" bitfld.long 0x0 0. "SIG_ERR,Indicate single bit error is detected." "0,1" line.long 0x4 "MEM_ERR_INT_STA_EN,Memory ECC error interrupt status enable" bitfld.long 0x4 3. "RDATA_FATAL_EN,Fatal normal rdata interrupt status enable." "0,1" bitfld.long 0x4 2. "WR_RDATA_FATAL_EN,Fatal read-modify-write rdata interrupt status enable." "0,1" bitfld.long 0x4 1. "MUL_ERR_EN,Multiple bit error interrupt status enable." "0,1" bitfld.long 0x4 0. "SIG_ERR_EN,Single bit error interrupt status enable." "0,1" line.long 0x8 "MEM_ERR_INT_SIG_EN,Memory ECC error interrupt signal enable" bitfld.long 0x8 3. "RDATA_FATAL_EN,Fatal normal rdata interrupt signal enable" "0,1" bitfld.long 0x8 2. "WR_RDATA_FATAL_EN,Fatal read-modify-write rdata interrupt signal enable." "0,1" bitfld.long 0x8 1. "MUL_ERR_EN,Multiple bits errors interrupt signal enable." "0,1" bitfld.long 0x8 0. "SIG_ERR_EN,Single bit error interrupt signal enable." "0,1" line.long 0xC "UNCERR_INT_STA,AXI bus uncorrectable error interrupt status" bitfld.long 0xC 31. "BREADY,Uncorrectable error for BREADY" "0,1" bitfld.long 0xC 27. "WSTRB_FATAL,It can report BIP ECC correction issue and protect wstrb internal path in iram_ctrl" "0,1" bitfld.long 0xC 26. "WDATA_FATAL,It can report BIP ECC correction issue and protect wdata internal path in iram_ctrl" "0,1" bitfld.long 0xC 25. "WVALID,Uncorrectable error for WVALID" "0,1" newline bitfld.long 0xC 24. "WEOBI,Uncorrectable error for WEOBI" "0,1" bitfld.long 0xC 22. "WCTL,Uncorrectable error for WCTL(WLAST WSTRB)" "0,1" bitfld.long 0xC 21. "WDATA,Uncorrectable error for WDATA" "0,1" bitfld.long 0xC 20. "RREADY,Uncorrectable error for RREADY" "0,1" newline bitfld.long 0xC 12. "AWVALID,Uncorrectable error for AWVALID" "0,1" bitfld.long 0xC 10. "AWCTL1,Uncorrectable error for AWCTL1(AWLOCK AWBURST AWSIZE AWLEN)" "0,1" newline bitfld.long 0xC 8. "AWADDR,Uncorrectable error for AWADDR" "0,1" bitfld.long 0xC 7. "AWID,Uncorrectable error for AWID" "0,1" bitfld.long 0xC 5. "ARVALID,Uncorrectable error for ARVALID" "0,1" newline bitfld.long 0xC 3. "ARCTL1,Uncorrectable error for ARCTL1(ARLOCK ARBURST ARSIZE ARLEN)" "0,1" bitfld.long 0xC 1. "ARADDR,Uncorrectable error for ARADDR" "0,1" bitfld.long 0xC 0. "ARID,Uncorrectable error for ARID" "0,1" line.long 0x10 "UNCERR_INT_STA_EN,AXI bus uncorrectable error interrupt status enable" bitfld.long 0x10 31. "BREADY,Status enable for BREADY uncorrectable error interrupt." "0,1" bitfld.long 0x10 27. "WSTRB_FATAL,Status enable for WSTRB_FATAL uncorrectable error interrupt." "0,1" bitfld.long 0x10 26. "WDATA_FATAL,Status enable for WDATA_FATAL uncorrectable error interrupt." "0,1" bitfld.long 0x10 25. "WVALID,Status enable for WVALID uncorrectable error interrupt." "0,1" newline bitfld.long 0x10 24. "WEOBI,Status enable for WEOBI uncorrectable error interrupt." "0,1" bitfld.long 0x10 22. "WCTL,Status enable for WCTL(WLAST WSTRB) uncorrectable error interrupt." "0,1" bitfld.long 0x10 21. "WDATA,Status enable for WDATA uncorrectable error interrupt." "0,1" bitfld.long 0x10 20. "RREADY,Status enable for RREADY uncorrectable error interrupt." "0,1" newline bitfld.long 0x10 12. "AWVALID,Status enable for AWVALID uncorrectable error interrupt." "0,1" bitfld.long 0x10 10. "AWCTL1,Status enable for AWCTL1(AWLOCK AWBURST AWSIZE AWLEN) uncorrectable error interrupt." "0,1" newline bitfld.long 0x10 8. "AWADDR,Status enable for AWADDR uncorrectable error interrupt." "0,1" bitfld.long 0x10 7. "AWID,Status enable for AWID uncorrectable error interrupt." "0,1" bitfld.long 0x10 5. "ARVALID,Status enable for ARVALID uncorrectable error interrupt." "0,1" newline bitfld.long 0x10 3. "ARCTL1,Status enable for ARCTL1(ARLOCK ARBURST ARSIZE ARLEN) uncorrectable error interrupt." "0,1" bitfld.long 0x10 1. "ARADDR,Status enable for ARADDR uncorrectable error interrupt." "0,1" bitfld.long 0x10 0. "ARID,Status enable for ARID uncorrectable error interrupt." "0,1" line.long 0x14 "UNCERR_INT_SIG_EN,AXI bus uncorrectable error interrupt signal enable" bitfld.long 0x14 31. "BREADY,Signal enable for BREADY uncorrectable error interrupt." "0,1" bitfld.long 0x14 27. "WSTRB_FATAL,Signal enable for WSTRB_FATAL uncorrectable error interrupt." "0,1" bitfld.long 0x14 26. "WDATA_FATAL,Signal enable for WDATA_FATAL uncorrectable error interrupt." "0,1" bitfld.long 0x14 25. "WVALID,Signal enable for WVALID uncorrectable error interrupt." "0,1" newline bitfld.long 0x14 24. "WEOBI,Signal enable for WEOBI uncorrectable error interrupt." "0,1" bitfld.long 0x14 22. "WCTL,Signal enable for WCTL(WLAST WSTRB) uncorrectable error interrupt." "0,1" bitfld.long 0x14 21. "WDATA,Signal enable for WDATA uncorrectable error interrupt." "0,1" bitfld.long 0x14 20. "RREADY,Signal enable for RREADY uncorrectable error interrupt." "0,1" newline bitfld.long 0x14 12. "AWVALID,Signal enable for AWVALID uncorrectable error interrupt." "0,1" bitfld.long 0x14 10. "AWCTL1,Signal enable for AWCTL1(AWLOCK AWBURST AWSIZE AWLEN) uncorrectable error interrupt." "0,1" newline bitfld.long 0x14 8. "AWADDR,Signal enable for AWADDR uncorrectable error interrupt." "0,1" bitfld.long 0x14 7. "AWID,Signal enable for AWID uncorrectable error interrupt." "0,1" bitfld.long 0x14 5. "ARVALID,Signal enable for ARVALID uncorrectable error interrupt." "0,1" newline bitfld.long 0x14 3. "ARCTL1,Signal enable for ARCTL1(ARLOCK ARBURST ARSIZE ARLEN) uncorrectable error interrupt." "0,1" bitfld.long 0x14 1. "ARADDR,Signal enable for ARADDR uncorrectable error interrupt." "0,1" bitfld.long 0x14 0. "ARID,Signal enable for ARID uncorrectable error interrupt." "0,1" line.long 0x18 "CORERR_INT_STA,AXI bus correctable error interrupt status" bitfld.long 0x18 3. "WDATA,Correctable error interrupt status for WDATA." "0,1" bitfld.long 0x18 1. "AWADDR,Correctable error interrupt status for AWADDR" "0,1" bitfld.long 0x18 0. "ARADDR,Correctable error interrupt status for ARADDR" "0,1" line.long 0x1C "CORERR_INT_STA_EN,AXI bus correctable error interrupt status enable" bitfld.long 0x1C 3. "WDATA,Status enable for WDATA correctable erorr interrupt." "0,1" bitfld.long 0x1C 1. "AWADDR,Status enable for AWADDR correctable erorr interrupt." "0,1" bitfld.long 0x1C 0. "ARADDR,Status enable for ARADDR correctable erorr interrupt." "0,1" line.long 0x20 "CORERR_INT_SIG_EN,AXI bus correctable error interrupt signal enable" bitfld.long 0x20 3. "WDATA,Signal enable for WDATA correctable erorr interrupt." "0,1" bitfld.long 0x20 1. "AWADDR,Signal enable for AWADDRcorrectable erorr interrupt." "0,1" bitfld.long 0x20 0. "ARADDR,Signal enable for ARADDR correctable erorr interrupt." "0,1" rgroup.long 0x40++0x27 line.long 0x0 "SIG_ERR_ADDR,This register is used to store access address when detect first single bit error." hexmask.long 0x0 0.--31. 1. "ADDR,Error addr" line.long 0x4 "SIG_ERR_DATA_31_0,This register is used to store error data[31:0] when detect first single bit error." hexmask.long 0x4 0.--31. 1. "DATA,Error data" line.long 0x8 "SIG_ERR_DATA_63_32,This register is used to store error data[63:32] when detect first single bit error." hexmask.long 0x8 0.--31. 1. "DATA,Error data" line.long 0xC "SIG_ERR_DATA_95_64,This register is used to store error data[95:64] when detect first single bit error." hexmask.long 0xC 0.--31. 1. "DATA,Error data" line.long 0x10 "SIG_ERR_DATA_127_96,This register is used to store error data[127:96] when detect first single bit error." hexmask.long 0x10 0.--31. 1. "DATA,Error data" line.long 0x14 "MUL_ERR_ADDR,This register is used to store access address when detect first multiple bits error." hexmask.long 0x14 0.--31. 1. "ADDR,Error address" line.long 0x18 "MUL_ERR_DATA_31_0,This register is used to store error data[31:0] when detect first multiple bits error." hexmask.long 0x18 0.--31. 1. "DATA,Error data" line.long 0x1C "MUL_ERR_DATA_63_32,This register is used to store error data[63:31] when detect first multiple bits error." hexmask.long 0x1C 0.--31. 1. "DATA,Error data" line.long 0x20 "MUL_ERR_DATA_95_64,This register is used to store error data[95:64] when detect first multiple bits error." hexmask.long 0x20 0.--31. 1. "DATA,Error data" line.long 0x24 "MUL_ERR_DATA_127_96,This register is used to store error data[127:96] when detect first multiple bits error." hexmask.long 0x24 0.--31. 1. "DATA,Error data" group.long 0x80++0x3 line.long 0x0 "DATA_INIT,This register is used to initializate all the ram data and ecc data" bitfld.long 0x0 31. "LOCK,Once this bit is set INIT and this bit can be not be written unless IRAM_CTRL is reset" "0,1" bitfld.long 0x0 0. "INIT,After this bit is set iram_ctrl will automatically initialize all the ram data and ecc data to 0. Once initialization is completed this bit will be auto cleared." "0,1" group.long 0x100++0x4F line.long 0x0 "BANK0_DATA_31_0_INJ,This register provides error injection on bank0 read data[31:0]" hexmask.long 0x0 0.--31. 1. "DATA_INJ,Error injection on read data" line.long 0x4 "BANK0_DATA_63_32_INJ,This register provides error injection on bank0 read data[63:32]" hexmask.long 0x4 0.--31. 1. "DATA_INJ,Error injection on read data" line.long 0x8 "BANK0_DATA_95_64_INJ,This register provides error injection on bank0 read data[95:64]" hexmask.long 0x8 0.--31. 1. "DATA_INJ,Error injection on read data" line.long 0xC "BANK0_DATA_127_96_INJ,This register provides error injection on bank0 read data[127:96]" hexmask.long 0xC 0.--31. 1. "DATA_INJ,Error injection on read data" line.long 0x10 "BANK1_DATA_31_0_INJ,This register provides error injection on bank1 read data[31:0]" hexmask.long 0x10 0.--31. 1. "DATA_INJ,Error injection on read data" line.long 0x14 "BANK1_DATA_63_32_INJ,This register provides error injection on bank1 read data[63:32]" hexmask.long 0x14 0.--31. 1. "DATA_INJ,Error injection on read data" line.long 0x18 "BANK1_DATA_95_64_INJ,This register provides error injection on bank1 read data[95:64]" hexmask.long 0x18 0.--31. 1. "DATA_INJ,Error injection on read data" line.long 0x1C "BANK1_DATA_127_96_INJ,This register provides error injection on bank1 read data[127:96]" hexmask.long 0x1C 0.--31. 1. "DATA_INJ,Error injection on read data" line.long 0x20 "BANK2_DATA_31_0_INJ,This register provides error injection on bank2 read data[31:0]" hexmask.long 0x20 0.--31. 1. "DATA_INJ,Error injection on read data" line.long 0x24 "BANK2_DATA_63_32_INJ,This register provides error injection on bank2 read data[63:32]" hexmask.long 0x24 0.--31. 1. "DATA_INJ,Error injection on read data" line.long 0x28 "BANK2_DATA_95_64_INJ,This register provides error injection on bank2 read data[95:64]" hexmask.long 0x28 0.--31. 1. "DATA_INJ,Error injection on read data" line.long 0x2C "BANK2_DATA_127_96_INJ,This register provides error injection on bank2 read data[127:96]" hexmask.long 0x2C 0.--31. 1. "DATA_INJ,Error injection on read data" line.long 0x30 "BANK3_DATA_31_0_INJ,This register provides error injection on bank3 read data[31:0]" hexmask.long 0x30 0.--31. 1. "DATA_INJ,Error injection on read data" line.long 0x34 "BANK3_DATA_63_32_INJ,This register provides error injection on bank3 read data[63:32]" hexmask.long 0x34 0.--31. 1. "DATA_INJ,Error injection on read data" line.long 0x38 "BANK3_DATA_95_64_INJ,This register provides error injection on bank0 read data[95:64]" hexmask.long 0x38 0.--31. 1. "DATA_INJ,Error injection on read data" line.long 0x3C "BANK3_DATA_127_96_INJ,This register provides error injection on bank3 read data[127:96]" hexmask.long 0x3C 0.--31. 1. "DATA_INJ,Error injection on read data" line.long 0x40 "BANK0_ECC_INJ,This register provides error injection on bank0 ecc code" hexmask.long.byte 0x40 8.--15. 1. "ECC_INJ1,Error injection on 8 ecc code for high 64 bits read data" hexmask.long.byte 0x40 0.--7. 1. "ECC_INJ0,Error injection on 8 ecc code for low 64 bits read data" line.long 0x44 "BANK1_ECC_INJ,This register provides error injection on bank1 ecc code" hexmask.long.byte 0x44 8.--15. 1. "ECC_INJ1,Error injection on 8 ecc code for high 64 bits read data" hexmask.long.byte 0x44 0.--7. 1. "ECC_INJ0,Error injection on 8 ecc code for low 64 bits read data" line.long 0x48 "BANK2_ECC_INJ,This register provides error injection on bank2 ecc code" hexmask.long.byte 0x48 8.--15. 1. "ECC_INJ1,Error injection on 8 ecc code for high 64 bits read data" hexmask.long.byte 0x48 0.--7. 1. "ECC_INJ0,Error injection on 8 ecc code for low 64 bits read data" line.long 0x4C "BANK3_ECC_INJ,This register provides error injection on bank3 ecc code" hexmask.long.byte 0x4C 8.--15. 1. "ECC_INJ1,Error injection on 8 ecc code for high 64 bits read data" hexmask.long.byte 0x4C 0.--7. 1. "ECC_INJ0,Error injection on 8 ecc code for low 64 bits read data" group.long 0x200++0x13 line.long 0x0 "RDATA_31_0_INJ,This register provides error injection on secded monitor read data[31:0]" hexmask.long 0x0 0.--31. 1. "DATA_INJ,Error injection on read data" line.long 0x4 "RDATA_63_32_INJ,This register provides error injection on secded monitor read data[63:31]" hexmask.long 0x4 0.--31. 1. "DATA_INJ,Error injection on read data" line.long 0x8 "RDATA_95_64_INJ,This register provides error injection on secded monitor read data[95:32]" hexmask.long 0x8 0.--31. 1. "DATA_INJ,Error injection on read data" line.long 0xC "RDATA_127_96_INJ,This register provides error injection on secded monitor read data[127:96]" hexmask.long 0xC 0.--31. 1. "DATA_INJ,Error injection on read data" line.long 0x10 "RECC_INJ,This register provides error injection on secded monitor read ecc code" hexmask.long.byte 0x10 8.--15. 1. "ECC_INJ1,Error injection on 8 ecc code for high 64 bits read data" hexmask.long.byte 0x10 0.--7. 1. "ECC_INJ0,Error injection on 8 ecc code for low 64 bits read data" group.long 0x220++0x13 line.long 0x0 "WDATA_31_0_INJ,This register provides error injection on secded monitor wdata data[31:0]" hexmask.long 0x0 0.--31. 1. "DATA_INJ,Error injection on read data" line.long 0x4 "WDATA_63_32_INJ,This register provides error injection on secded monitor wdata data[63:32]" hexmask.long 0x4 0.--31. 1. "DATA_INJ,Error injection on read data" line.long 0x8 "WDATA_95_64_INJ,This register provides error injection on secded monitor wdata data[95:64]" hexmask.long 0x8 0.--31. 1. "DATA_INJ,Error injection on read data" line.long 0xC "WDATA_127_96_INJ,This register provides error injection on secded monitor wdata data[127:96]" hexmask.long 0xC 0.--31. 1. "DATA_INJ,Error injection on read data" line.long 0x10 "WECC_INJ,This register provides error injection on secded monitor write ecc code" hexmask.long.byte 0x10 8.--15. 1. "ECC_INJ1,Error injection on 8 ecc code for high 64 bits read data" hexmask.long.byte 0x10 0.--7. 1. "ECC_INJ0,Error injection on 8 ecc code for low 64 bits read data" group.long 0x240++0x3 line.long 0x0 "WSTRB_INJ,This register provides error injection on ded monitor wstrb and wctl code" hexmask.long.byte 0x0 16.--20. 1. "WCTLCODE_INJ,Error injection on wctlcode" hexmask.long.word 0x0 0.--15. 1. "WTSTRB_INJ,Error injection on wstrb data" tree.end repeat.end endif tree.end tree "LVDS (LVDS Interface)" sif (CORENAME()=="CORTEXR5F") tree "LVDS_COMMON" base ad:0xF0C40000 group.long 0x0++0xF line.long 0x0 "SOFT_RESET,lvds softreset" bitfld.long 0x0 6. "TRIM_MODE,trim_mode 1: from fuse 0: form REG" "form REG,from fuse" bitfld.long 0x0 5. "RTE_CTL,rte_ctl control io" "0,1" newline bitfld.long 0x0 4. "COMBINE_SOFT_RESET,combine SOFT_RESET" "0,1" bitfld.long 0x0 3. "CH3_SOFT_RESET,CH4 SOFT_RESET" "0,1" bitfld.long 0x0 2. "CH2_SOFT_RESET,CH3 SOFT_RESET" "0,1" newline bitfld.long 0x0 1. "CH1_SOFT_RESET,CH2 SOFT_RESET" "0,1" bitfld.long 0x0 0. "CH0_SOFT_RESET,CH0 SOFT_RESET" "0,1" line.long 0x4 "MUX_SEL,lvds subsyestem mux sel" bitfld.long 0x4 19.--20. "MUX8_SEL,MUX8_SEL group2 ch2 lvds clock source 00: LVDS PLL1 x7 clock 01: LVDS PLL2 x7 clock 10: LVDS PLL3 x7 clock 11: LVDS PLL4 x7 clock" "LVDS PLL1 x7 clock,LVDS PLL2 x7 clock,?,?" bitfld.long 0x4 17.--18. "MUX7_SEL,MUX7_SEL group2 ch1 lvds clock source 00: LVDS PLL1 x7 clock 01: LVDS PLL2 x7 clock 10: LVDS PLL3 x7 clock 11: LVDS PLL4 x7 clock" "LVDS PLL1 x7 clock,LVDS PLL2 x7 clock,?,?" newline bitfld.long 0x4 15.--16. "MUX6_SEL,MUX6_SEL group 1 ch2 lvds clock source 00: LVDS PLL1 x7 clock 01: LVDS PLL2 x7 clock 10: LVDS PLL3 x7 clock 11: LVDS PLL4 x7 clock" "LVDS PLL1 x7 clock,LVDS PLL2 x7 clock,?,?" bitfld.long 0x4 13.--14. "MUX5_SEL,MUX5_SEL group 1 ch1 lvds clock source 00: LVDS PLL1 x7 clock 01: LVDS PLL2 x7 clock 10: LVDS PLL3 x7 clock 11: LVDS PLL4 x7 clock" "LVDS PLL1 x7 clock,LVDS PLL2 x7 clock,?,?" bitfld.long 0x4 12. "MUX4_SEL,MUX4_SEL pixel combine 0: DC1 and DC2 1: DC3 and DC4" "DC1 and DC2,DC3 and DC4" newline bitfld.long 0x4 9.--11. "MUX3_SEL,MUX0_SEL :group 2 CH2 000: DC1 001: DC2 010: DC3 011: DC4 100: DC5 101: combine output channel 1 110: combine output channel 2 111:not support" "DC1,DC2,?,?,?,?,?,?" bitfld.long 0x4 6.--8. "MUX2_SEL,MUX0_SEL :group 2 CH1 000: DC1 001: DC2 010: DC3 011: DC4 100: DC5 101: combine output channel 1 110: combine output channel 2 111:not support" "DC1,DC2,?,?,?,?,?,?" bitfld.long 0x4 3.--5. "MUX1_SEL,MUX1_SEL :group 1 CH2 000: DC1 001: DC2 010: DC3 011: DC4 100: DC5 101: combine output channel 1 110: combine output channel 2 111:not support" "DC1,DC2,?,?,?,?,?,?" newline bitfld.long 0x4 0.--2. "MUX0_SEL,MUX0_SEL :group1 CH1 000: DC1 001: DC2 010: DC3 011: DC4 100: DC5 101: combine output channel 1 110: combine output channel 2 111:not support" "DC1,DC2,?,?,?,?,?,?" line.long 0x8 "LVDS_COMBINE,lvds_combine" bitfld.long 0x8 29. "ENABLE,lvde combine enable" "0,1" bitfld.long 0x8 28. "COMBINE_MODE,lvds combine mode 0:mode 0 1:mode 1" "mode 0,mode 1" newline bitfld.long 0x8 27. "DATA_EN_POL,data_en polarity" "0,1" bitfld.long 0x8 26. "HSYNC_POL,hsync polarity" "0,1" bitfld.long 0x8 25. "VSYNC_POL,vsync polarity" "0,1" newline bitfld.long 0x8 24. "CH_SWAP,channel swap" "0,1" hexmask.long.byte 0x8 16.--23. 1. "GAP,skip gap" hexmask.long.word 0x8 0.--15. 1. "VLD_HEIGHT,valid height" line.long 0xC "LVDS_BIAS_SET,lvds BIAS setting" bitfld.long 0xC 2.--3. "BIAS_TRIM,bias_trim" "0,1,2,3" bitfld.long 0xC 1. "BIAS_SELVDD,bias_selvdd" "0,1" newline bitfld.long 0xC 0. "BIAS_EN,BIAS_EN" "0,1" repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) group.long ($2+0x100)++0x3 line.long 0x0 "TEST_CFG_$1,test data/enable configure" bitfld.long 0x0 7. "ENABLE,test cfg enable" "0,1" hexmask.long.byte 0x0 0.--6. 1. "DATA,test cfg data" repeat.end group.long 0x10000++0xB line.long 0x0 "LVDS_CH_0,lvds ch0 channel" bitfld.long 0x0 31. "ENABLE,enable" "0,1" bitfld.long 0x0 23.--24. "MUX,mux : the source of data come from 00:: lvds pair0 odd 01:lvds pair0 even 01:lvds pair1 odd 11:lvds pair1 even" "lvds pair0 odd,lvds pair1 odd,?,?" newline bitfld.long 0x0 22. "DUALODD,dual odd/even only when 30bit dualmode" "0,1" hexmask.long.word 0x0 7.--21. 1. "LANE_UPDATE,each lane update slot 2:0 clk lane 5:3 tx0 lane 8:6 tx1 lane 11:9 tx2 lane 14:12 tx3 lane" bitfld.long 0x0 5.--6. "FRAME_MASK,frame mask 00: 0 frame mask 01: 1 frame mask 10: 2 frame mask 11: 3 frame mask" "0,1,2,3" newline bitfld.long 0x0 4. "VSYNC_POL,vsync polarity" "0,1" bitfld.long 0x0 3. "FORMAT,map format 0:jeida 1:swpg" "jeida 1:swpg,?" bitfld.long 0x0 1.--2. "BPP,pixel format 00:18bit 01:24bit 10:30bit" "0,1,2,3" newline bitfld.long 0x0 0. "DUALMODE,dual mode" "0,1" line.long 0x4 "LVDS_CLOCK_0,lvds 0 clock div setting" hexmask.long.byte 0x4 11.--14. 1. "DIV_NUM_DBG,dbg div" hexmask.long.byte 0x4 7.--10. 1. "DIV_NUM_LVDS,lvds div" newline rbitfld.long 0x4 6. "GATING_ACK,gating_ack" "0,1" hexmask.long.byte 0x4 1.--5. 1. "GATING_EN,clock 0:clock disable 1:clock enable gating_en[0]:lvds_clk gating_en[1]:lvds_clk_x7 gating_en[2]:lvds_clk_x3.5 gating_en[3]:dbg_clk gating_en[4]:dsp_clk(from lvds_clk_x7 or lvds_clk_x3.5)" bitfld.long 0x4 0. "SRC_SEL,0: 7 clock 1: 3.5 clock" "0,1" line.long 0x8 "LVDS_CH0_PAD_COM_SET,lvds ch0 common setting" bitfld.long 0x8 14.--16. "LVDS_TRIM,lvds pad trim" "0,1,2,3,4,5,6,7" bitfld.long 0x8 13. "TEST_TXD_P,test_txd_p" "0,1" newline bitfld.long 0x8 12. "TEST_TXD_N,test_tx_n" "0,1" bitfld.long 0x8 11. "TEST_SCHMITT_EN,test_schmitt_en" "0,1" bitfld.long 0x8 10. "TEST_RXEN,test_rxen" "0,1" newline bitfld.long 0x8 9. "TEST_RXCM_EN,test_rxcm_en" "0,1" bitfld.long 0x8 8. "TEST_PULLDN,test_pulldn" "0,1" bitfld.long 0x8 7. "TEST_OEN_P,test_oen_p" "0,1" newline bitfld.long 0x8 6. "TEST_OEN_N,test_oen_n" "0,1" bitfld.long 0x8 5. "TEST_IEN_P,test_ien_p" "0,1" bitfld.long 0x8 4. "TEST_IEN_N,test_ien_n" "0,1" newline group.long 0x10010++0x13 line.long 0x0 "LVDS_CH0_PAD_SET,lvds ch0 pad setting" rbitfld.long 0x0 11. "RXDA,rxda data" "0,1" rbitfld.long 0x0 10. "RXD_P,rxd_p data" "0,1" newline rbitfld.long 0x0 9. "RXD_N,rxd_n data" "0,1" bitfld.long 0x0 8. "VBIAS_SEL,vbais_sel" "0,1" bitfld.long 0x0 7. "TXEN,tx_en" "0,1" newline hexmask.long.byte 0x0 3.--6. 1. "TXDRV,tx_drv" bitfld.long 0x0 2. "TX_CM,tx_cm" "0,1" bitfld.long 0x0 1. "RTERM_EN,rterm enable" "0,1" newline bitfld.long 0x0 0. "BIAS_EN,bias enable" "0,1" line.long 0x4 "LVDS_CH0_PAD_SET,lvds ch0 pad setting" rbitfld.long 0x4 11. "RXDA,rxda data" "0,1" rbitfld.long 0x4 10. "RXD_P,rxd_p data" "0,1" newline rbitfld.long 0x4 9. "RXD_N,rxd_n data" "0,1" bitfld.long 0x4 8. "VBIAS_SEL,vbais_sel" "0,1" bitfld.long 0x4 7. "TXEN,tx_en" "0,1" newline hexmask.long.byte 0x4 3.--6. 1. "TXDRV,tx_drv" bitfld.long 0x4 2. "TX_CM,tx_cm" "0,1" bitfld.long 0x4 1. "RTERM_EN,rterm enable" "0,1" newline bitfld.long 0x4 0. "BIAS_EN,bias enable" "0,1" line.long 0x8 "LVDS_CH0_PAD_SET,lvds ch0 pad setting" rbitfld.long 0x8 11. "RXDA,rxda data" "0,1" rbitfld.long 0x8 10. "RXD_P,rxd_p data" "0,1" newline rbitfld.long 0x8 9. "RXD_N,rxd_n data" "0,1" bitfld.long 0x8 8. "VBIAS_SEL,vbais_sel" "0,1" bitfld.long 0x8 7. "TXEN,tx_en" "0,1" newline hexmask.long.byte 0x8 3.--6. 1. "TXDRV,tx_drv" bitfld.long 0x8 2. "TX_CM,tx_cm" "0,1" bitfld.long 0x8 1. "RTERM_EN,rterm enable" "0,1" newline bitfld.long 0x8 0. "BIAS_EN,bias enable" "0,1" line.long 0xC "LVDS_CH0_PAD_SET,lvds ch0 pad setting" rbitfld.long 0xC 11. "RXDA,rxda data" "0,1" rbitfld.long 0xC 10. "RXD_P,rxd_p data" "0,1" newline rbitfld.long 0xC 9. "RXD_N,rxd_n data" "0,1" bitfld.long 0xC 8. "VBIAS_SEL,vbais_sel" "0,1" bitfld.long 0xC 7. "TXEN,tx_en" "0,1" newline hexmask.long.byte 0xC 3.--6. 1. "TXDRV,tx_drv" bitfld.long 0xC 2. "TX_CM,tx_cm" "0,1" bitfld.long 0xC 1. "RTERM_EN,rterm enable" "0,1" newline bitfld.long 0xC 0. "BIAS_EN,bias enable" "0,1" line.long 0x10 "LVDS_CH0_PAD_SET,lvds ch0 pad setting" rbitfld.long 0x10 11. "RXDA,rxda data" "0,1" rbitfld.long 0x10 10. "RXD_P,rxd_p data" "0,1" newline rbitfld.long 0x10 9. "RXD_N,rxd_n data" "0,1" bitfld.long 0x10 8. "VBIAS_SEL,vbais_sel" "0,1" bitfld.long 0x10 7. "TXEN,tx_en" "0,1" newline hexmask.long.byte 0x10 3.--6. 1. "TXDRV,tx_drv" bitfld.long 0x10 2. "TX_CM,tx_cm" "0,1" bitfld.long 0x10 1. "RTERM_EN,rterm enable" "0,1" newline bitfld.long 0x10 0. "BIAS_EN,bias enable" "0,1" group.long 0x20000++0xB line.long 0x0 "LVDS_CH_1,lvds ch1 channel" bitfld.long 0x0 31. "ENABLE,enable" "0,1" bitfld.long 0x0 23.--24. "MUX,mux : the source of data come from 00:: lvds pair0 odd 01:lvds pair0 even 01:lvds pair1 odd 11:lvds pair1 even" "lvds pair0 odd,lvds pair1 odd,?,?" newline bitfld.long 0x0 22. "DUALODD,dual odd/even only when 30bit dualmode" "0,1" hexmask.long.word 0x0 7.--21. 1. "LANE_UPDATE,each lane update slot 2:0 clk lane 5:3 tx0 lane 8:6 tx1 lane 11:9 tx2 lane 14:12 tx3 lane" bitfld.long 0x0 5.--6. "FRAME_MASK,frame mask 00: 0 frame mask 01: 1 frame mask 10: 2 frame mask 11: 3 frame mask" "0,1,2,3" newline bitfld.long 0x0 4. "VSYNC_POL,vsync polarity" "0,1" bitfld.long 0x0 3. "FORMAT,map format 0:jeida 1:swpg" "jeida 1:swpg,?" bitfld.long 0x0 1.--2. "BPP,pixel format 00:18bit 01:24bit 10:30bit" "0,1,2,3" newline bitfld.long 0x0 0. "DUALMODE,dual mode" "0,1" line.long 0x4 "LVDS_CLOCK_1,lvds 1 clock div setting" hexmask.long.byte 0x4 11.--14. 1. "DIV_NUM_DBG,dbg div" hexmask.long.byte 0x4 7.--10. 1. "DIV_NUM_LVDS,lvds div" newline rbitfld.long 0x4 6. "GATING_ACK,gating_ack" "0,1" hexmask.long.byte 0x4 1.--5. 1. "GATING_EN,clock 0:clock disable 1:clock enable gating_en[0]:lvds_clk gating_en[1]:lvds_clk_x7 gating_en[2]:lvds_clk_x3.5 gating_en[3]:dbg_clk gating_en[4]:dsp_clk(from lvds_clk_x7 or lvds_clk_x3.5)" bitfld.long 0x4 0. "SRC_SEL,0: 7 clock 1: 3.5 clock" "0,1" line.long 0x8 "LVDS_CH1_PAD_COM_SET,lvds ch1 common setting" bitfld.long 0x8 14.--16. "LVDS_TRIM,lvds pad trim" "0,1,2,3,4,5,6,7" bitfld.long 0x8 13. "TEST_TXD_P,test_txd_p" "0,1" newline bitfld.long 0x8 12. "TEST_TXD_N,test_tx_n" "0,1" bitfld.long 0x8 11. "TEST_SCHMITT_EN,test_schmitt_en" "0,1" bitfld.long 0x8 10. "TEST_RXEN,test_rxen" "0,1" newline bitfld.long 0x8 9. "TEST_RXCM_EN,test_rxcm_en" "0,1" bitfld.long 0x8 8. "TEST_PULLDN,test_pulldn" "0,1" bitfld.long 0x8 7. "TEST_OEN_P,test_oen_p" "0,1" newline bitfld.long 0x8 6. "TEST_OEN_N,test_oen_n" "0,1" bitfld.long 0x8 5. "TEST_IEN_P,test_ien_p" "0,1" bitfld.long 0x8 4. "TEST_IEN_N,test_ien_n" "0,1" newline group.long 0x20010++0x13 line.long 0x0 "LVDS_CH1_PAD_SET,lvds ch1 pad setting" rbitfld.long 0x0 11. "RXDA,rxda data" "0,1" rbitfld.long 0x0 10. "RXD_P,rxd_p data" "0,1" newline rbitfld.long 0x0 9. "RXD_N,rxd_n data" "0,1" bitfld.long 0x0 8. "VBIAS_SEL,vbais_sel" "0,1" bitfld.long 0x0 7. "TXEN,tx_en" "0,1" newline hexmask.long.byte 0x0 3.--6. 1. "TXDRV,tx_drv" bitfld.long 0x0 2. "TX_CM,tx_cm" "0,1" bitfld.long 0x0 1. "RTERM_EN,rterm enable" "0,1" newline bitfld.long 0x0 0. "BIAS_EN,bias enable" "0,1" line.long 0x4 "LVDS_CH1_PAD_SET,lvds ch1 pad setting" rbitfld.long 0x4 11. "RXDA,rxda data" "0,1" rbitfld.long 0x4 10. "RXD_P,rxd_p data" "0,1" newline rbitfld.long 0x4 9. "RXD_N,rxd_n data" "0,1" bitfld.long 0x4 8. "VBIAS_SEL,vbais_sel" "0,1" bitfld.long 0x4 7. "TXEN,tx_en" "0,1" newline hexmask.long.byte 0x4 3.--6. 1. "TXDRV,tx_drv" bitfld.long 0x4 2. "TX_CM,tx_cm" "0,1" bitfld.long 0x4 1. "RTERM_EN,rterm enable" "0,1" newline bitfld.long 0x4 0. "BIAS_EN,bias enable" "0,1" line.long 0x8 "LVDS_CH1_PAD_SET,lvds ch1 pad setting" rbitfld.long 0x8 11. "RXDA,rxda data" "0,1" rbitfld.long 0x8 10. "RXD_P,rxd_p data" "0,1" newline rbitfld.long 0x8 9. "RXD_N,rxd_n data" "0,1" bitfld.long 0x8 8. "VBIAS_SEL,vbais_sel" "0,1" bitfld.long 0x8 7. "TXEN,tx_en" "0,1" newline hexmask.long.byte 0x8 3.--6. 1. "TXDRV,tx_drv" bitfld.long 0x8 2. "TX_CM,tx_cm" "0,1" bitfld.long 0x8 1. "RTERM_EN,rterm enable" "0,1" newline bitfld.long 0x8 0. "BIAS_EN,bias enable" "0,1" line.long 0xC "LVDS_CH1_PAD_SET,lvds ch1 pad setting" rbitfld.long 0xC 11. "RXDA,rxda data" "0,1" rbitfld.long 0xC 10. "RXD_P,rxd_p data" "0,1" newline rbitfld.long 0xC 9. "RXD_N,rxd_n data" "0,1" bitfld.long 0xC 8. "VBIAS_SEL,vbais_sel" "0,1" bitfld.long 0xC 7. "TXEN,tx_en" "0,1" newline hexmask.long.byte 0xC 3.--6. 1. "TXDRV,tx_drv" bitfld.long 0xC 2. "TX_CM,tx_cm" "0,1" bitfld.long 0xC 1. "RTERM_EN,rterm enable" "0,1" newline bitfld.long 0xC 0. "BIAS_EN,bias enable" "0,1" line.long 0x10 "LVDS_CH1_PAD_SET,lvds ch1 pad setting" rbitfld.long 0x10 11. "RXDA,rxda data" "0,1" rbitfld.long 0x10 10. "RXD_P,rxd_p data" "0,1" newline rbitfld.long 0x10 9. "RXD_N,rxd_n data" "0,1" bitfld.long 0x10 8. "VBIAS_SEL,vbais_sel" "0,1" bitfld.long 0x10 7. "TXEN,tx_en" "0,1" newline hexmask.long.byte 0x10 3.--6. 1. "TXDRV,tx_drv" bitfld.long 0x10 2. "TX_CM,tx_cm" "0,1" bitfld.long 0x10 1. "RTERM_EN,rterm enable" "0,1" newline bitfld.long 0x10 0. "BIAS_EN,bias enable" "0,1" group.long 0x30000++0xB line.long 0x0 "LVDS_CH_2,lvds ch2 channel" bitfld.long 0x0 31. "ENABLE,enable" "0,1" bitfld.long 0x0 23.--24. "MUX,mux : the source of data come from 00:: lvds pair0 odd 01:lvds pair0 even 01:lvds pair1 odd 11:lvds pair1 even" "lvds pair0 odd,lvds pair1 odd,?,?" newline bitfld.long 0x0 22. "DUALODD,dual odd/even only when 30bit dualmode" "0,1" hexmask.long.word 0x0 7.--21. 1. "LANE_UPDATE,each lane update slot 2:0 clk lane 5:3 tx0 lane 8:6 tx1 lane 11:9 tx2 lane 14:12 tx3 lane" bitfld.long 0x0 5.--6. "FRAME_MASK,frame mask 00: 0 frame mask 01: 1 frame mask 10: 2 frame mask 11: 3 frame mask" "0,1,2,3" newline bitfld.long 0x0 4. "VSYNC_POL,vsync polarity" "0,1" bitfld.long 0x0 3. "FORMAT,map format 0:jeida 1:swpg" "jeida 1:swpg,?" bitfld.long 0x0 1.--2. "BPP,pixel format 00:18bit 01:24bit 10:30bit" "0,1,2,3" newline bitfld.long 0x0 0. "DUALMODE,dual mode" "0,1" line.long 0x4 "LVDS_CLOCK_2,lvds 2 clock div setting" hexmask.long.byte 0x4 11.--14. 1. "DIV_NUM_DBG,dbg div" hexmask.long.byte 0x4 7.--10. 1. "DIV_NUM_LVDS,lvds div" newline rbitfld.long 0x4 6. "GATING_ACK,gating_ack" "0,1" hexmask.long.byte 0x4 1.--5. 1. "GATING_EN,clock 0:clock disable 1:clock enable gating_en[0]:lvds_clk gating_en[1]:lvds_clk_x7 gating_en[2]:lvds_clk_x3.5 gating_en[3]:dbg_clk gating_en[4]:dsp_clk(from lvds_clk_x7 or lvds_clk_x3.5)" bitfld.long 0x4 0. "SRC_SEL,0: 7 clock 1: 3.5 clock" "0,1" line.long 0x8 "LVDS_CH2_PAD_COM_SET,lvds ch2 common setting" bitfld.long 0x8 14.--16. "LVDS_TRIM,lvds pad trim" "0,1,2,3,4,5,6,7" bitfld.long 0x8 13. "TEST_TXD_P,test_txd_p" "0,1" newline bitfld.long 0x8 12. "TEST_TXD_N,test_tx_n" "0,1" bitfld.long 0x8 11. "TEST_SCHMITT_EN,test_schmitt_en" "0,1" bitfld.long 0x8 10. "TEST_RXEN,test_rxen" "0,1" newline bitfld.long 0x8 9. "TEST_RXCM_EN,test_rxcm_en" "0,1" bitfld.long 0x8 8. "TEST_PULLDN,test_pulldn" "0,1" bitfld.long 0x8 7. "TEST_OEN_P,test_oen_p" "0,1" newline bitfld.long 0x8 6. "TEST_OEN_N,test_oen_n" "0,1" bitfld.long 0x8 5. "TEST_IEN_P,test_ien_p" "0,1" bitfld.long 0x8 4. "TEST_IEN_N,test_ien_n" "0,1" newline group.long 0x30010++0x13 line.long 0x0 "LVDS_CH2_PAD_SET,lvds ch2 pad setting" rbitfld.long 0x0 11. "RXDA,rxda data" "0,1" rbitfld.long 0x0 10. "RXD_P,rxd_p data" "0,1" newline rbitfld.long 0x0 9. "RXD_N,rxd_n data" "0,1" bitfld.long 0x0 8. "VBIAS_SEL,vbais_sel" "0,1" bitfld.long 0x0 7. "TXEN,tx_en" "0,1" newline hexmask.long.byte 0x0 3.--6. 1. "TXDRV,tx_drv" bitfld.long 0x0 2. "TX_CM,tx_cm" "0,1" bitfld.long 0x0 1. "RTERM_EN,rterm enable" "0,1" newline bitfld.long 0x0 0. "BIAS_EN,bias enable" "0,1" line.long 0x4 "LVDS_CH2_PAD_SET,lvds ch2 pad setting" rbitfld.long 0x4 11. "RXDA,rxda data" "0,1" rbitfld.long 0x4 10. "RXD_P,rxd_p data" "0,1" newline rbitfld.long 0x4 9. "RXD_N,rxd_n data" "0,1" bitfld.long 0x4 8. "VBIAS_SEL,vbais_sel" "0,1" bitfld.long 0x4 7. "TXEN,tx_en" "0,1" newline hexmask.long.byte 0x4 3.--6. 1. "TXDRV,tx_drv" bitfld.long 0x4 2. "TX_CM,tx_cm" "0,1" bitfld.long 0x4 1. "RTERM_EN,rterm enable" "0,1" newline bitfld.long 0x4 0. "BIAS_EN,bias enable" "0,1" line.long 0x8 "LVDS_CH2_PAD_SET,lvds ch2 pad setting" rbitfld.long 0x8 11. "RXDA,rxda data" "0,1" rbitfld.long 0x8 10. "RXD_P,rxd_p data" "0,1" newline rbitfld.long 0x8 9. "RXD_N,rxd_n data" "0,1" bitfld.long 0x8 8. "VBIAS_SEL,vbais_sel" "0,1" bitfld.long 0x8 7. "TXEN,tx_en" "0,1" newline hexmask.long.byte 0x8 3.--6. 1. "TXDRV,tx_drv" bitfld.long 0x8 2. "TX_CM,tx_cm" "0,1" bitfld.long 0x8 1. "RTERM_EN,rterm enable" "0,1" newline bitfld.long 0x8 0. "BIAS_EN,bias enable" "0,1" line.long 0xC "LVDS_CH2_PAD_SET,lvds ch2 pad setting" rbitfld.long 0xC 11. "RXDA,rxda data" "0,1" rbitfld.long 0xC 10. "RXD_P,rxd_p data" "0,1" newline rbitfld.long 0xC 9. "RXD_N,rxd_n data" "0,1" bitfld.long 0xC 8. "VBIAS_SEL,vbais_sel" "0,1" bitfld.long 0xC 7. "TXEN,tx_en" "0,1" newline hexmask.long.byte 0xC 3.--6. 1. "TXDRV,tx_drv" bitfld.long 0xC 2. "TX_CM,tx_cm" "0,1" bitfld.long 0xC 1. "RTERM_EN,rterm enable" "0,1" newline bitfld.long 0xC 0. "BIAS_EN,bias enable" "0,1" line.long 0x10 "LVDS_CH2_PAD_SET,lvds ch2 pad setting" rbitfld.long 0x10 11. "RXDA,rxda data" "0,1" rbitfld.long 0x10 10. "RXD_P,rxd_p data" "0,1" newline rbitfld.long 0x10 9. "RXD_N,rxd_n data" "0,1" bitfld.long 0x10 8. "VBIAS_SEL,vbais_sel" "0,1" bitfld.long 0x10 7. "TXEN,tx_en" "0,1" newline hexmask.long.byte 0x10 3.--6. 1. "TXDRV,tx_drv" bitfld.long 0x10 2. "TX_CM,tx_cm" "0,1" bitfld.long 0x10 1. "RTERM_EN,rterm enable" "0,1" newline bitfld.long 0x10 0. "BIAS_EN,bias enable" "0,1" group.long 0x40000++0xB line.long 0x0 "LVDS_CH_3,lvds ch3 channel" bitfld.long 0x0 31. "ENABLE,enable" "0,1" bitfld.long 0x0 23.--24. "MUX,mux : the source of data come from 00:: lvds pair0 odd 01:lvds pair0 even 01:lvds pair1 odd 11:lvds pair1 even" "lvds pair0 odd,lvds pair1 odd,?,?" newline bitfld.long 0x0 22. "DUALODD,dual odd/even only when 30bit dualmode" "0,1" hexmask.long.word 0x0 7.--21. 1. "LANE_UPDATE,each lane update slot 2:0 clk lane 5:3 tx0 lane 8:6 tx1 lane 11:9 tx2 lane 14:12 tx3 lane" bitfld.long 0x0 5.--6. "FRAME_MASK,frame mask 00: 0 frame mask 01: 1 frame mask 10: 2 frame mask 11: 3 frame mask" "0,1,2,3" newline bitfld.long 0x0 4. "VSYNC_POL,vsync polarity" "0,1" bitfld.long 0x0 3. "FORMAT,map format 0:jeida 1:swpg" "jeida 1:swpg,?" bitfld.long 0x0 1.--2. "BPP,pixel format 00:18bit 01:24bit 10:30bit" "0,1,2,3" newline bitfld.long 0x0 0. "DUALMODE,dual mode" "0,1" line.long 0x4 "LVDS_CLOCK_3,lvds 3 clock div setting" hexmask.long.byte 0x4 11.--14. 1. "DIV_NUM_DBG,dbg div" hexmask.long.byte 0x4 7.--10. 1. "DIV_NUM_LVDS,lvds div" newline rbitfld.long 0x4 6. "GATING_ACK,gating_ack" "0,1" hexmask.long.byte 0x4 1.--5. 1. "GATING_EN,clock 0:clock disable 1:clock enable gating_en[0]:lvds_clk gating_en[1]:lvds_clk_x7 gating_en[2]:lvds_clk_x3.5 gating_en[3]:dbg_clk gating_en[4]:dsp_clk(from lvds_clk_x7 or lvds_clk_x3.5)" bitfld.long 0x4 0. "SRC_SEL,0: 7 clock 1: 3.5 clock" "0,1" line.long 0x8 "LVDS_CH3_PAD_COM_SET,lvds ch3 common setting" bitfld.long 0x8 14.--16. "LVDS_TRIM,lvds pad trim" "0,1,2,3,4,5,6,7" bitfld.long 0x8 13. "TEST_TXD_P,test_txd_p" "0,1" newline bitfld.long 0x8 12. "TEST_TXD_N,test_tx_n" "0,1" bitfld.long 0x8 11. "TEST_SCHMITT_EN,test_schmitt_en" "0,1" bitfld.long 0x8 10. "TEST_RXEN,test_rxen" "0,1" newline bitfld.long 0x8 9. "TEST_RXCM_EN,test_rxcm_en" "0,1" bitfld.long 0x8 8. "TEST_PULLDN,test_pulldn" "0,1" bitfld.long 0x8 7. "TEST_OEN_P,test_oen_p" "0,1" newline bitfld.long 0x8 6. "TEST_OEN_N,test_oen_n" "0,1" bitfld.long 0x8 5. "TEST_IEN_P,test_ien_p" "0,1" bitfld.long 0x8 4. "TEST_IEN_N,test_ien_n" "0,1" newline group.long 0x40010++0x13 line.long 0x0 "LVDS_CH3_PAD_SET,lvds ch3 pad setting" rbitfld.long 0x0 11. "RXDA,rxda data" "0,1" rbitfld.long 0x0 10. "RXD_P,rxd_p data" "0,1" newline rbitfld.long 0x0 9. "RXD_N,rxd_n data" "0,1" bitfld.long 0x0 8. "VBIAS_SEL,vbais_sel" "0,1" bitfld.long 0x0 7. "TXEN,tx_en" "0,1" newline hexmask.long.byte 0x0 3.--6. 1. "TXDRV,tx_drv" bitfld.long 0x0 2. "TX_CM,tx_cm" "0,1" bitfld.long 0x0 1. "RTERM_EN,rterm enable" "0,1" newline bitfld.long 0x0 0. "BIAS_EN,bias enable" "0,1" line.long 0x4 "LVDS_CH3_PAD_SET,lvds ch3 pad setting" rbitfld.long 0x4 11. "RXDA,rxda data" "0,1" rbitfld.long 0x4 10. "RXD_P,rxd_p data" "0,1" newline rbitfld.long 0x4 9. "RXD_N,rxd_n data" "0,1" bitfld.long 0x4 8. "VBIAS_SEL,vbais_sel" "0,1" bitfld.long 0x4 7. "TXEN,tx_en" "0,1" newline hexmask.long.byte 0x4 3.--6. 1. "TXDRV,tx_drv" bitfld.long 0x4 2. "TX_CM,tx_cm" "0,1" bitfld.long 0x4 1. "RTERM_EN,rterm enable" "0,1" newline bitfld.long 0x4 0. "BIAS_EN,bias enable" "0,1" line.long 0x8 "LVDS_CH3_PAD_SET,lvds ch3 pad setting" rbitfld.long 0x8 11. "RXDA,rxda data" "0,1" rbitfld.long 0x8 10. "RXD_P,rxd_p data" "0,1" newline rbitfld.long 0x8 9. "RXD_N,rxd_n data" "0,1" bitfld.long 0x8 8. "VBIAS_SEL,vbais_sel" "0,1" bitfld.long 0x8 7. "TXEN,tx_en" "0,1" newline hexmask.long.byte 0x8 3.--6. 1. "TXDRV,tx_drv" bitfld.long 0x8 2. "TX_CM,tx_cm" "0,1" bitfld.long 0x8 1. "RTERM_EN,rterm enable" "0,1" newline bitfld.long 0x8 0. "BIAS_EN,bias enable" "0,1" line.long 0xC "LVDS_CH3_PAD_SET,lvds ch3 pad setting" rbitfld.long 0xC 11. "RXDA,rxda data" "0,1" rbitfld.long 0xC 10. "RXD_P,rxd_p data" "0,1" newline rbitfld.long 0xC 9. "RXD_N,rxd_n data" "0,1" bitfld.long 0xC 8. "VBIAS_SEL,vbais_sel" "0,1" bitfld.long 0xC 7. "TXEN,tx_en" "0,1" newline hexmask.long.byte 0xC 3.--6. 1. "TXDRV,tx_drv" bitfld.long 0xC 2. "TX_CM,tx_cm" "0,1" bitfld.long 0xC 1. "RTERM_EN,rterm enable" "0,1" newline bitfld.long 0xC 0. "BIAS_EN,bias enable" "0,1" line.long 0x10 "LVDS_CH3_PAD_SET,lvds ch3 pad setting" rbitfld.long 0x10 11. "RXDA,rxda data" "0,1" rbitfld.long 0x10 10. "RXD_P,rxd_p data" "0,1" newline rbitfld.long 0x10 9. "RXD_N,rxd_n data" "0,1" bitfld.long 0x10 8. "VBIAS_SEL,vbais_sel" "0,1" bitfld.long 0x10 7. "TXEN,tx_en" "0,1" newline hexmask.long.byte 0x10 3.--6. 1. "TXDRV,tx_drv" bitfld.long 0x10 2. "TX_CM,tx_cm" "0,1" bitfld.long 0x10 1. "RTERM_EN,rterm enable" "0,1" newline bitfld.long 0x10 0. "BIAS_EN,bias enable" "0,1" tree.end repeat 4. (increment 1. 1) (list ad:0xF0C50000 ad:0xF0C60000 ad:0xF0C70000 ad:0xF0C80000) tree "LVDS$1" base $2 group.long 0x0++0xF line.long 0x0 "SOFT_RESET,lvds softreset" bitfld.long 0x0 6. "TRIM_MODE,trim_mode 1: from fuse 0: form REG" "form REG,from fuse" bitfld.long 0x0 5. "RTE_CTL,rte_ctl control io" "0,1" newline bitfld.long 0x0 4. "COMBINE_SOFT_RESET,combine SOFT_RESET" "0,1" bitfld.long 0x0 3. "CH3_SOFT_RESET,CH4 SOFT_RESET" "0,1" bitfld.long 0x0 2. "CH2_SOFT_RESET,CH3 SOFT_RESET" "0,1" newline bitfld.long 0x0 1. "CH1_SOFT_RESET,CH2 SOFT_RESET" "0,1" bitfld.long 0x0 0. "CH0_SOFT_RESET,CH0 SOFT_RESET" "0,1" line.long 0x4 "MUX_SEL,lvds subsyestem mux sel" bitfld.long 0x4 19.--20. "MUX8_SEL,MUX8_SEL group2 ch2 lvds clock source 00: LVDS PLL1 x7 clock 01: LVDS PLL2 x7 clock 10: LVDS PLL3 x7 clock 11: LVDS PLL4 x7 clock" "LVDS PLL1 x7 clock,LVDS PLL2 x7 clock,?,?" bitfld.long 0x4 17.--18. "MUX7_SEL,MUX7_SEL group2 ch1 lvds clock source 00: LVDS PLL1 x7 clock 01: LVDS PLL2 x7 clock 10: LVDS PLL3 x7 clock 11: LVDS PLL4 x7 clock" "LVDS PLL1 x7 clock,LVDS PLL2 x7 clock,?,?" newline bitfld.long 0x4 15.--16. "MUX6_SEL,MUX6_SEL group 1 ch2 lvds clock source 00: LVDS PLL1 x7 clock 01: LVDS PLL2 x7 clock 10: LVDS PLL3 x7 clock 11: LVDS PLL4 x7 clock" "LVDS PLL1 x7 clock,LVDS PLL2 x7 clock,?,?" bitfld.long 0x4 13.--14. "MUX5_SEL,MUX5_SEL group 1 ch1 lvds clock source 00: LVDS PLL1 x7 clock 01: LVDS PLL2 x7 clock 10: LVDS PLL3 x7 clock 11: LVDS PLL4 x7 clock" "LVDS PLL1 x7 clock,LVDS PLL2 x7 clock,?,?" bitfld.long 0x4 12. "MUX4_SEL,MUX4_SEL pixel combine 0: DC1 and DC2 1: DC3 and DC4" "DC1 and DC2,DC3 and DC4" newline bitfld.long 0x4 9.--11. "MUX3_SEL,MUX0_SEL :group 2 CH2 000: DC1 001: DC2 010: DC3 011: DC4 100: DC5 101: combine output channel 1 110: combine output channel 2 111:not support" "DC1,DC2,?,?,?,?,?,?" bitfld.long 0x4 6.--8. "MUX2_SEL,MUX0_SEL :group 2 CH1 000: DC1 001: DC2 010: DC3 011: DC4 100: DC5 101: combine output channel 1 110: combine output channel 2 111:not support" "DC1,DC2,?,?,?,?,?,?" bitfld.long 0x4 3.--5. "MUX1_SEL,MUX1_SEL :group 1 CH2 000: DC1 001: DC2 010: DC3 011: DC4 100: DC5 101: combine output channel 1 110: combine output channel 2 111:not support" "DC1,DC2,?,?,?,?,?,?" newline bitfld.long 0x4 0.--2. "MUX0_SEL,MUX0_SEL :group1 CH1 000: DC1 001: DC2 010: DC3 011: DC4 100: DC5 101: combine output channel 1 110: combine output channel 2 111:not support" "DC1,DC2,?,?,?,?,?,?" line.long 0x8 "LVDS_COMBINE,lvds_combine" bitfld.long 0x8 29. "ENABLE,lvde combine enable" "0,1" bitfld.long 0x8 28. "COMBINE_MODE,lvds combine mode 0:mode 0 1:mode 1" "mode 0,mode 1" newline bitfld.long 0x8 27. "DATA_EN_POL,data_en polarity" "0,1" bitfld.long 0x8 26. "HSYNC_POL,hsync polarity" "0,1" bitfld.long 0x8 25. "VSYNC_POL,vsync polarity" "0,1" newline bitfld.long 0x8 24. "CH_SWAP,channel swap" "0,1" hexmask.long.byte 0x8 16.--23. 1. "GAP,skip gap" hexmask.long.word 0x8 0.--15. 1. "VLD_HEIGHT,valid height" line.long 0xC "LVDS_BIAS_SET,lvds BIAS setting" bitfld.long 0xC 2.--3. "BIAS_TRIM,bias_trim" "0,1,2,3" bitfld.long 0xC 1. "BIAS_SELVDD,bias_selvdd" "0,1" newline bitfld.long 0xC 0. "BIAS_EN,BIAS_EN" "0,1" repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) group.long ($2+0x100)++0x3 line.long 0x0 "TEST_CFG_$1,test data/enable configure" bitfld.long 0x0 7. "ENABLE,test cfg enable" "0,1" hexmask.long.byte 0x0 0.--6. 1. "DATA,test cfg data" repeat.end group.long 0x10000++0xB line.long 0x0 "LVDS_CH_0,lvds ch0 channel" bitfld.long 0x0 31. "ENABLE,enable" "0,1" bitfld.long 0x0 23.--24. "MUX,mux : the source of data come from 00:: lvds pair0 odd 01:lvds pair0 even 01:lvds pair1 odd 11:lvds pair1 even" "lvds pair0 odd,lvds pair1 odd,?,?" newline bitfld.long 0x0 22. "DUALODD,dual odd/even only when 30bit dualmode" "0,1" hexmask.long.word 0x0 7.--21. 1. "LANE_UPDATE,each lane update slot 2:0 clk lane 5:3 tx0 lane 8:6 tx1 lane 11:9 tx2 lane 14:12 tx3 lane" bitfld.long 0x0 5.--6. "FRAME_MASK,frame mask 00: 0 frame mask 01: 1 frame mask 10: 2 frame mask 11: 3 frame mask" "0,1,2,3" newline bitfld.long 0x0 4. "VSYNC_POL,vsync polarity" "0,1" bitfld.long 0x0 3. "FORMAT,map format 0:jeida 1:swpg" "jeida 1:swpg,?" bitfld.long 0x0 1.--2. "BPP,pixel format 00:18bit 01:24bit 10:30bit" "0,1,2,3" newline bitfld.long 0x0 0. "DUALMODE,dual mode" "0,1" line.long 0x4 "LVDS_CLOCK_0,lvds 0 clock div setting" hexmask.long.byte 0x4 11.--14. 1. "DIV_NUM_DBG,dbg div" hexmask.long.byte 0x4 7.--10. 1. "DIV_NUM_LVDS,lvds div" newline rbitfld.long 0x4 6. "GATING_ACK,gating_ack" "0,1" hexmask.long.byte 0x4 1.--5. 1. "GATING_EN,clock 0:clock disable 1:clock enable gating_en[0]:lvds_clk gating_en[1]:lvds_clk_x7 gating_en[2]:lvds_clk_x3.5 gating_en[3]:dbg_clk gating_en[4]:dsp_clk(from lvds_clk_x7 or lvds_clk_x3.5)" bitfld.long 0x4 0. "SRC_SEL,0: 7 clock 1: 3.5 clock" "0,1" line.long 0x8 "LVDS_CH0_PAD_COM_SET,lvds ch0 common setting" bitfld.long 0x8 14.--16. "LVDS_TRIM,lvds pad trim" "0,1,2,3,4,5,6,7" bitfld.long 0x8 13. "TEST_TXD_P,test_txd_p" "0,1" newline bitfld.long 0x8 12. "TEST_TXD_N,test_tx_n" "0,1" bitfld.long 0x8 11. "TEST_SCHMITT_EN,test_schmitt_en" "0,1" bitfld.long 0x8 10. "TEST_RXEN,test_rxen" "0,1" newline bitfld.long 0x8 9. "TEST_RXCM_EN,test_rxcm_en" "0,1" bitfld.long 0x8 8. "TEST_PULLDN,test_pulldn" "0,1" bitfld.long 0x8 7. "TEST_OEN_P,test_oen_p" "0,1" newline bitfld.long 0x8 6. "TEST_OEN_N,test_oen_n" "0,1" bitfld.long 0x8 5. "TEST_IEN_P,test_ien_p" "0,1" bitfld.long 0x8 4. "TEST_IEN_N,test_ien_n" "0,1" newline group.long 0x10010++0x13 line.long 0x0 "LVDS_CH0_PAD_SET,lvds ch0 pad setting" rbitfld.long 0x0 11. "RXDA,rxda data" "0,1" rbitfld.long 0x0 10. "RXD_P,rxd_p data" "0,1" newline rbitfld.long 0x0 9. "RXD_N,rxd_n data" "0,1" bitfld.long 0x0 8. "VBIAS_SEL,vbais_sel" "0,1" bitfld.long 0x0 7. "TXEN,tx_en" "0,1" newline hexmask.long.byte 0x0 3.--6. 1. "TXDRV,tx_drv" bitfld.long 0x0 2. "TX_CM,tx_cm" "0,1" bitfld.long 0x0 1. "RTERM_EN,rterm enable" "0,1" newline bitfld.long 0x0 0. "BIAS_EN,bias enable" "0,1" line.long 0x4 "LVDS_CH0_PAD_SET,lvds ch0 pad setting" rbitfld.long 0x4 11. "RXDA,rxda data" "0,1" rbitfld.long 0x4 10. "RXD_P,rxd_p data" "0,1" newline rbitfld.long 0x4 9. "RXD_N,rxd_n data" "0,1" bitfld.long 0x4 8. "VBIAS_SEL,vbais_sel" "0,1" bitfld.long 0x4 7. "TXEN,tx_en" "0,1" newline hexmask.long.byte 0x4 3.--6. 1. "TXDRV,tx_drv" bitfld.long 0x4 2. "TX_CM,tx_cm" "0,1" bitfld.long 0x4 1. "RTERM_EN,rterm enable" "0,1" newline bitfld.long 0x4 0. "BIAS_EN,bias enable" "0,1" line.long 0x8 "LVDS_CH0_PAD_SET,lvds ch0 pad setting" rbitfld.long 0x8 11. "RXDA,rxda data" "0,1" rbitfld.long 0x8 10. "RXD_P,rxd_p data" "0,1" newline rbitfld.long 0x8 9. "RXD_N,rxd_n data" "0,1" bitfld.long 0x8 8. "VBIAS_SEL,vbais_sel" "0,1" bitfld.long 0x8 7. "TXEN,tx_en" "0,1" newline hexmask.long.byte 0x8 3.--6. 1. "TXDRV,tx_drv" bitfld.long 0x8 2. "TX_CM,tx_cm" "0,1" bitfld.long 0x8 1. "RTERM_EN,rterm enable" "0,1" newline bitfld.long 0x8 0. "BIAS_EN,bias enable" "0,1" line.long 0xC "LVDS_CH0_PAD_SET,lvds ch0 pad setting" rbitfld.long 0xC 11. "RXDA,rxda data" "0,1" rbitfld.long 0xC 10. "RXD_P,rxd_p data" "0,1" newline rbitfld.long 0xC 9. "RXD_N,rxd_n data" "0,1" bitfld.long 0xC 8. "VBIAS_SEL,vbais_sel" "0,1" bitfld.long 0xC 7. "TXEN,tx_en" "0,1" newline hexmask.long.byte 0xC 3.--6. 1. "TXDRV,tx_drv" bitfld.long 0xC 2. "TX_CM,tx_cm" "0,1" bitfld.long 0xC 1. "RTERM_EN,rterm enable" "0,1" newline bitfld.long 0xC 0. "BIAS_EN,bias enable" "0,1" line.long 0x10 "LVDS_CH0_PAD_SET,lvds ch0 pad setting" rbitfld.long 0x10 11. "RXDA,rxda data" "0,1" rbitfld.long 0x10 10. "RXD_P,rxd_p data" "0,1" newline rbitfld.long 0x10 9. "RXD_N,rxd_n data" "0,1" bitfld.long 0x10 8. "VBIAS_SEL,vbais_sel" "0,1" bitfld.long 0x10 7. "TXEN,tx_en" "0,1" newline hexmask.long.byte 0x10 3.--6. 1. "TXDRV,tx_drv" bitfld.long 0x10 2. "TX_CM,tx_cm" "0,1" bitfld.long 0x10 1. "RTERM_EN,rterm enable" "0,1" newline bitfld.long 0x10 0. "BIAS_EN,bias enable" "0,1" group.long 0x20000++0xB line.long 0x0 "LVDS_CH_1,lvds ch1 channel" bitfld.long 0x0 31. "ENABLE,enable" "0,1" bitfld.long 0x0 23.--24. "MUX,mux : the source of data come from 00:: lvds pair0 odd 01:lvds pair0 even 01:lvds pair1 odd 11:lvds pair1 even" "lvds pair0 odd,lvds pair1 odd,?,?" newline bitfld.long 0x0 22. "DUALODD,dual odd/even only when 30bit dualmode" "0,1" hexmask.long.word 0x0 7.--21. 1. "LANE_UPDATE,each lane update slot 2:0 clk lane 5:3 tx0 lane 8:6 tx1 lane 11:9 tx2 lane 14:12 tx3 lane" bitfld.long 0x0 5.--6. "FRAME_MASK,frame mask 00: 0 frame mask 01: 1 frame mask 10: 2 frame mask 11: 3 frame mask" "0,1,2,3" newline bitfld.long 0x0 4. "VSYNC_POL,vsync polarity" "0,1" bitfld.long 0x0 3. "FORMAT,map format 0:jeida 1:swpg" "jeida 1:swpg,?" bitfld.long 0x0 1.--2. "BPP,pixel format 00:18bit 01:24bit 10:30bit" "0,1,2,3" newline bitfld.long 0x0 0. "DUALMODE,dual mode" "0,1" line.long 0x4 "LVDS_CLOCK_1,lvds 1 clock div setting" hexmask.long.byte 0x4 11.--14. 1. "DIV_NUM_DBG,dbg div" hexmask.long.byte 0x4 7.--10. 1. "DIV_NUM_LVDS,lvds div" newline rbitfld.long 0x4 6. "GATING_ACK,gating_ack" "0,1" hexmask.long.byte 0x4 1.--5. 1. "GATING_EN,clock 0:clock disable 1:clock enable gating_en[0]:lvds_clk gating_en[1]:lvds_clk_x7 gating_en[2]:lvds_clk_x3.5 gating_en[3]:dbg_clk gating_en[4]:dsp_clk(from lvds_clk_x7 or lvds_clk_x3.5)" bitfld.long 0x4 0. "SRC_SEL,0: 7 clock 1: 3.5 clock" "0,1" line.long 0x8 "LVDS_CH1_PAD_COM_SET,lvds ch1 common setting" bitfld.long 0x8 14.--16. "LVDS_TRIM,lvds pad trim" "0,1,2,3,4,5,6,7" bitfld.long 0x8 13. "TEST_TXD_P,test_txd_p" "0,1" newline bitfld.long 0x8 12. "TEST_TXD_N,test_tx_n" "0,1" bitfld.long 0x8 11. "TEST_SCHMITT_EN,test_schmitt_en" "0,1" bitfld.long 0x8 10. "TEST_RXEN,test_rxen" "0,1" newline bitfld.long 0x8 9. "TEST_RXCM_EN,test_rxcm_en" "0,1" bitfld.long 0x8 8. "TEST_PULLDN,test_pulldn" "0,1" bitfld.long 0x8 7. "TEST_OEN_P,test_oen_p" "0,1" newline bitfld.long 0x8 6. "TEST_OEN_N,test_oen_n" "0,1" bitfld.long 0x8 5. "TEST_IEN_P,test_ien_p" "0,1" bitfld.long 0x8 4. "TEST_IEN_N,test_ien_n" "0,1" newline group.long 0x20010++0x13 line.long 0x0 "LVDS_CH1_PAD_SET,lvds ch1 pad setting" rbitfld.long 0x0 11. "RXDA,rxda data" "0,1" rbitfld.long 0x0 10. "RXD_P,rxd_p data" "0,1" newline rbitfld.long 0x0 9. "RXD_N,rxd_n data" "0,1" bitfld.long 0x0 8. "VBIAS_SEL,vbais_sel" "0,1" bitfld.long 0x0 7. "TXEN,tx_en" "0,1" newline hexmask.long.byte 0x0 3.--6. 1. "TXDRV,tx_drv" bitfld.long 0x0 2. "TX_CM,tx_cm" "0,1" bitfld.long 0x0 1. "RTERM_EN,rterm enable" "0,1" newline bitfld.long 0x0 0. "BIAS_EN,bias enable" "0,1" line.long 0x4 "LVDS_CH1_PAD_SET,lvds ch1 pad setting" rbitfld.long 0x4 11. "RXDA,rxda data" "0,1" rbitfld.long 0x4 10. "RXD_P,rxd_p data" "0,1" newline rbitfld.long 0x4 9. "RXD_N,rxd_n data" "0,1" bitfld.long 0x4 8. "VBIAS_SEL,vbais_sel" "0,1" bitfld.long 0x4 7. "TXEN,tx_en" "0,1" newline hexmask.long.byte 0x4 3.--6. 1. "TXDRV,tx_drv" bitfld.long 0x4 2. "TX_CM,tx_cm" "0,1" bitfld.long 0x4 1. "RTERM_EN,rterm enable" "0,1" newline bitfld.long 0x4 0. "BIAS_EN,bias enable" "0,1" line.long 0x8 "LVDS_CH1_PAD_SET,lvds ch1 pad setting" rbitfld.long 0x8 11. "RXDA,rxda data" "0,1" rbitfld.long 0x8 10. "RXD_P,rxd_p data" "0,1" newline rbitfld.long 0x8 9. "RXD_N,rxd_n data" "0,1" bitfld.long 0x8 8. "VBIAS_SEL,vbais_sel" "0,1" bitfld.long 0x8 7. "TXEN,tx_en" "0,1" newline hexmask.long.byte 0x8 3.--6. 1. "TXDRV,tx_drv" bitfld.long 0x8 2. "TX_CM,tx_cm" "0,1" bitfld.long 0x8 1. "RTERM_EN,rterm enable" "0,1" newline bitfld.long 0x8 0. "BIAS_EN,bias enable" "0,1" line.long 0xC "LVDS_CH1_PAD_SET,lvds ch1 pad setting" rbitfld.long 0xC 11. "RXDA,rxda data" "0,1" rbitfld.long 0xC 10. "RXD_P,rxd_p data" "0,1" newline rbitfld.long 0xC 9. "RXD_N,rxd_n data" "0,1" bitfld.long 0xC 8. "VBIAS_SEL,vbais_sel" "0,1" bitfld.long 0xC 7. "TXEN,tx_en" "0,1" newline hexmask.long.byte 0xC 3.--6. 1. "TXDRV,tx_drv" bitfld.long 0xC 2. "TX_CM,tx_cm" "0,1" bitfld.long 0xC 1. "RTERM_EN,rterm enable" "0,1" newline bitfld.long 0xC 0. "BIAS_EN,bias enable" "0,1" line.long 0x10 "LVDS_CH1_PAD_SET,lvds ch1 pad setting" rbitfld.long 0x10 11. "RXDA,rxda data" "0,1" rbitfld.long 0x10 10. "RXD_P,rxd_p data" "0,1" newline rbitfld.long 0x10 9. "RXD_N,rxd_n data" "0,1" bitfld.long 0x10 8. "VBIAS_SEL,vbais_sel" "0,1" bitfld.long 0x10 7. "TXEN,tx_en" "0,1" newline hexmask.long.byte 0x10 3.--6. 1. "TXDRV,tx_drv" bitfld.long 0x10 2. "TX_CM,tx_cm" "0,1" bitfld.long 0x10 1. "RTERM_EN,rterm enable" "0,1" newline bitfld.long 0x10 0. "BIAS_EN,bias enable" "0,1" group.long 0x30000++0xB line.long 0x0 "LVDS_CH_2,lvds ch2 channel" bitfld.long 0x0 31. "ENABLE,enable" "0,1" bitfld.long 0x0 23.--24. "MUX,mux : the source of data come from 00:: lvds pair0 odd 01:lvds pair0 even 01:lvds pair1 odd 11:lvds pair1 even" "lvds pair0 odd,lvds pair1 odd,?,?" newline bitfld.long 0x0 22. "DUALODD,dual odd/even only when 30bit dualmode" "0,1" hexmask.long.word 0x0 7.--21. 1. "LANE_UPDATE,each lane update slot 2:0 clk lane 5:3 tx0 lane 8:6 tx1 lane 11:9 tx2 lane 14:12 tx3 lane" bitfld.long 0x0 5.--6. "FRAME_MASK,frame mask 00: 0 frame mask 01: 1 frame mask 10: 2 frame mask 11: 3 frame mask" "0,1,2,3" newline bitfld.long 0x0 4. "VSYNC_POL,vsync polarity" "0,1" bitfld.long 0x0 3. "FORMAT,map format 0:jeida 1:swpg" "jeida 1:swpg,?" bitfld.long 0x0 1.--2. "BPP,pixel format 00:18bit 01:24bit 10:30bit" "0,1,2,3" newline bitfld.long 0x0 0. "DUALMODE,dual mode" "0,1" line.long 0x4 "LVDS_CLOCK_2,lvds 2 clock div setting" hexmask.long.byte 0x4 11.--14. 1. "DIV_NUM_DBG,dbg div" hexmask.long.byte 0x4 7.--10. 1. "DIV_NUM_LVDS,lvds div" newline rbitfld.long 0x4 6. "GATING_ACK,gating_ack" "0,1" hexmask.long.byte 0x4 1.--5. 1. "GATING_EN,clock 0:clock disable 1:clock enable gating_en[0]:lvds_clk gating_en[1]:lvds_clk_x7 gating_en[2]:lvds_clk_x3.5 gating_en[3]:dbg_clk gating_en[4]:dsp_clk(from lvds_clk_x7 or lvds_clk_x3.5)" bitfld.long 0x4 0. "SRC_SEL,0: 7 clock 1: 3.5 clock" "0,1" line.long 0x8 "LVDS_CH2_PAD_COM_SET,lvds ch2 common setting" bitfld.long 0x8 14.--16. "LVDS_TRIM,lvds pad trim" "0,1,2,3,4,5,6,7" bitfld.long 0x8 13. "TEST_TXD_P,test_txd_p" "0,1" newline bitfld.long 0x8 12. "TEST_TXD_N,test_tx_n" "0,1" bitfld.long 0x8 11. "TEST_SCHMITT_EN,test_schmitt_en" "0,1" bitfld.long 0x8 10. "TEST_RXEN,test_rxen" "0,1" newline bitfld.long 0x8 9. "TEST_RXCM_EN,test_rxcm_en" "0,1" bitfld.long 0x8 8. "TEST_PULLDN,test_pulldn" "0,1" bitfld.long 0x8 7. "TEST_OEN_P,test_oen_p" "0,1" newline bitfld.long 0x8 6. "TEST_OEN_N,test_oen_n" "0,1" bitfld.long 0x8 5. "TEST_IEN_P,test_ien_p" "0,1" bitfld.long 0x8 4. "TEST_IEN_N,test_ien_n" "0,1" newline group.long 0x30010++0x13 line.long 0x0 "LVDS_CH2_PAD_SET,lvds ch2 pad setting" rbitfld.long 0x0 11. "RXDA,rxda data" "0,1" rbitfld.long 0x0 10. "RXD_P,rxd_p data" "0,1" newline rbitfld.long 0x0 9. "RXD_N,rxd_n data" "0,1" bitfld.long 0x0 8. "VBIAS_SEL,vbais_sel" "0,1" bitfld.long 0x0 7. "TXEN,tx_en" "0,1" newline hexmask.long.byte 0x0 3.--6. 1. "TXDRV,tx_drv" bitfld.long 0x0 2. "TX_CM,tx_cm" "0,1" bitfld.long 0x0 1. "RTERM_EN,rterm enable" "0,1" newline bitfld.long 0x0 0. "BIAS_EN,bias enable" "0,1" line.long 0x4 "LVDS_CH2_PAD_SET,lvds ch2 pad setting" rbitfld.long 0x4 11. "RXDA,rxda data" "0,1" rbitfld.long 0x4 10. "RXD_P,rxd_p data" "0,1" newline rbitfld.long 0x4 9. "RXD_N,rxd_n data" "0,1" bitfld.long 0x4 8. "VBIAS_SEL,vbais_sel" "0,1" bitfld.long 0x4 7. "TXEN,tx_en" "0,1" newline hexmask.long.byte 0x4 3.--6. 1. "TXDRV,tx_drv" bitfld.long 0x4 2. "TX_CM,tx_cm" "0,1" bitfld.long 0x4 1. "RTERM_EN,rterm enable" "0,1" newline bitfld.long 0x4 0. "BIAS_EN,bias enable" "0,1" line.long 0x8 "LVDS_CH2_PAD_SET,lvds ch2 pad setting" rbitfld.long 0x8 11. "RXDA,rxda data" "0,1" rbitfld.long 0x8 10. "RXD_P,rxd_p data" "0,1" newline rbitfld.long 0x8 9. "RXD_N,rxd_n data" "0,1" bitfld.long 0x8 8. "VBIAS_SEL,vbais_sel" "0,1" bitfld.long 0x8 7. "TXEN,tx_en" "0,1" newline hexmask.long.byte 0x8 3.--6. 1. "TXDRV,tx_drv" bitfld.long 0x8 2. "TX_CM,tx_cm" "0,1" bitfld.long 0x8 1. "RTERM_EN,rterm enable" "0,1" newline bitfld.long 0x8 0. "BIAS_EN,bias enable" "0,1" line.long 0xC "LVDS_CH2_PAD_SET,lvds ch2 pad setting" rbitfld.long 0xC 11. "RXDA,rxda data" "0,1" rbitfld.long 0xC 10. "RXD_P,rxd_p data" "0,1" newline rbitfld.long 0xC 9. "RXD_N,rxd_n data" "0,1" bitfld.long 0xC 8. "VBIAS_SEL,vbais_sel" "0,1" bitfld.long 0xC 7. "TXEN,tx_en" "0,1" newline hexmask.long.byte 0xC 3.--6. 1. "TXDRV,tx_drv" bitfld.long 0xC 2. "TX_CM,tx_cm" "0,1" bitfld.long 0xC 1. "RTERM_EN,rterm enable" "0,1" newline bitfld.long 0xC 0. "BIAS_EN,bias enable" "0,1" line.long 0x10 "LVDS_CH2_PAD_SET,lvds ch2 pad setting" rbitfld.long 0x10 11. "RXDA,rxda data" "0,1" rbitfld.long 0x10 10. "RXD_P,rxd_p data" "0,1" newline rbitfld.long 0x10 9. "RXD_N,rxd_n data" "0,1" bitfld.long 0x10 8. "VBIAS_SEL,vbais_sel" "0,1" bitfld.long 0x10 7. "TXEN,tx_en" "0,1" newline hexmask.long.byte 0x10 3.--6. 1. "TXDRV,tx_drv" bitfld.long 0x10 2. "TX_CM,tx_cm" "0,1" bitfld.long 0x10 1. "RTERM_EN,rterm enable" "0,1" newline bitfld.long 0x10 0. "BIAS_EN,bias enable" "0,1" group.long 0x40000++0xB line.long 0x0 "LVDS_CH_3,lvds ch3 channel" bitfld.long 0x0 31. "ENABLE,enable" "0,1" bitfld.long 0x0 23.--24. "MUX,mux : the source of data come from 00:: lvds pair0 odd 01:lvds pair0 even 01:lvds pair1 odd 11:lvds pair1 even" "lvds pair0 odd,lvds pair1 odd,?,?" newline bitfld.long 0x0 22. "DUALODD,dual odd/even only when 30bit dualmode" "0,1" hexmask.long.word 0x0 7.--21. 1. "LANE_UPDATE,each lane update slot 2:0 clk lane 5:3 tx0 lane 8:6 tx1 lane 11:9 tx2 lane 14:12 tx3 lane" bitfld.long 0x0 5.--6. "FRAME_MASK,frame mask 00: 0 frame mask 01: 1 frame mask 10: 2 frame mask 11: 3 frame mask" "0,1,2,3" newline bitfld.long 0x0 4. "VSYNC_POL,vsync polarity" "0,1" bitfld.long 0x0 3. "FORMAT,map format 0:jeida 1:swpg" "jeida 1:swpg,?" bitfld.long 0x0 1.--2. "BPP,pixel format 00:18bit 01:24bit 10:30bit" "0,1,2,3" newline bitfld.long 0x0 0. "DUALMODE,dual mode" "0,1" line.long 0x4 "LVDS_CLOCK_3,lvds 3 clock div setting" hexmask.long.byte 0x4 11.--14. 1. "DIV_NUM_DBG,dbg div" hexmask.long.byte 0x4 7.--10. 1. "DIV_NUM_LVDS,lvds div" newline rbitfld.long 0x4 6. "GATING_ACK,gating_ack" "0,1" hexmask.long.byte 0x4 1.--5. 1. "GATING_EN,clock 0:clock disable 1:clock enable gating_en[0]:lvds_clk gating_en[1]:lvds_clk_x7 gating_en[2]:lvds_clk_x3.5 gating_en[3]:dbg_clk gating_en[4]:dsp_clk(from lvds_clk_x7 or lvds_clk_x3.5)" bitfld.long 0x4 0. "SRC_SEL,0: 7 clock 1: 3.5 clock" "0,1" line.long 0x8 "LVDS_CH3_PAD_COM_SET,lvds ch3 common setting" bitfld.long 0x8 14.--16. "LVDS_TRIM,lvds pad trim" "0,1,2,3,4,5,6,7" bitfld.long 0x8 13. "TEST_TXD_P,test_txd_p" "0,1" newline bitfld.long 0x8 12. "TEST_TXD_N,test_tx_n" "0,1" bitfld.long 0x8 11. "TEST_SCHMITT_EN,test_schmitt_en" "0,1" bitfld.long 0x8 10. "TEST_RXEN,test_rxen" "0,1" newline bitfld.long 0x8 9. "TEST_RXCM_EN,test_rxcm_en" "0,1" bitfld.long 0x8 8. "TEST_PULLDN,test_pulldn" "0,1" bitfld.long 0x8 7. "TEST_OEN_P,test_oen_p" "0,1" newline bitfld.long 0x8 6. "TEST_OEN_N,test_oen_n" "0,1" bitfld.long 0x8 5. "TEST_IEN_P,test_ien_p" "0,1" bitfld.long 0x8 4. "TEST_IEN_N,test_ien_n" "0,1" newline group.long 0x40010++0x13 line.long 0x0 "LVDS_CH3_PAD_SET,lvds ch3 pad setting" rbitfld.long 0x0 11. "RXDA,rxda data" "0,1" rbitfld.long 0x0 10. "RXD_P,rxd_p data" "0,1" newline rbitfld.long 0x0 9. "RXD_N,rxd_n data" "0,1" bitfld.long 0x0 8. "VBIAS_SEL,vbais_sel" "0,1" bitfld.long 0x0 7. "TXEN,tx_en" "0,1" newline hexmask.long.byte 0x0 3.--6. 1. "TXDRV,tx_drv" bitfld.long 0x0 2. "TX_CM,tx_cm" "0,1" bitfld.long 0x0 1. "RTERM_EN,rterm enable" "0,1" newline bitfld.long 0x0 0. "BIAS_EN,bias enable" "0,1" line.long 0x4 "LVDS_CH3_PAD_SET,lvds ch3 pad setting" rbitfld.long 0x4 11. "RXDA,rxda data" "0,1" rbitfld.long 0x4 10. "RXD_P,rxd_p data" "0,1" newline rbitfld.long 0x4 9. "RXD_N,rxd_n data" "0,1" bitfld.long 0x4 8. "VBIAS_SEL,vbais_sel" "0,1" bitfld.long 0x4 7. "TXEN,tx_en" "0,1" newline hexmask.long.byte 0x4 3.--6. 1. "TXDRV,tx_drv" bitfld.long 0x4 2. "TX_CM,tx_cm" "0,1" bitfld.long 0x4 1. "RTERM_EN,rterm enable" "0,1" newline bitfld.long 0x4 0. "BIAS_EN,bias enable" "0,1" line.long 0x8 "LVDS_CH3_PAD_SET,lvds ch3 pad setting" rbitfld.long 0x8 11. "RXDA,rxda data" "0,1" rbitfld.long 0x8 10. "RXD_P,rxd_p data" "0,1" newline rbitfld.long 0x8 9. "RXD_N,rxd_n data" "0,1" bitfld.long 0x8 8. "VBIAS_SEL,vbais_sel" "0,1" bitfld.long 0x8 7. "TXEN,tx_en" "0,1" newline hexmask.long.byte 0x8 3.--6. 1. "TXDRV,tx_drv" bitfld.long 0x8 2. "TX_CM,tx_cm" "0,1" bitfld.long 0x8 1. "RTERM_EN,rterm enable" "0,1" newline bitfld.long 0x8 0. "BIAS_EN,bias enable" "0,1" line.long 0xC "LVDS_CH3_PAD_SET,lvds ch3 pad setting" rbitfld.long 0xC 11. "RXDA,rxda data" "0,1" rbitfld.long 0xC 10. "RXD_P,rxd_p data" "0,1" newline rbitfld.long 0xC 9. "RXD_N,rxd_n data" "0,1" bitfld.long 0xC 8. "VBIAS_SEL,vbais_sel" "0,1" bitfld.long 0xC 7. "TXEN,tx_en" "0,1" newline hexmask.long.byte 0xC 3.--6. 1. "TXDRV,tx_drv" bitfld.long 0xC 2. "TX_CM,tx_cm" "0,1" bitfld.long 0xC 1. "RTERM_EN,rterm enable" "0,1" newline bitfld.long 0xC 0. "BIAS_EN,bias enable" "0,1" line.long 0x10 "LVDS_CH3_PAD_SET,lvds ch3 pad setting" rbitfld.long 0x10 11. "RXDA,rxda data" "0,1" rbitfld.long 0x10 10. "RXD_P,rxd_p data" "0,1" newline rbitfld.long 0x10 9. "RXD_N,rxd_n data" "0,1" bitfld.long 0x10 8. "VBIAS_SEL,vbais_sel" "0,1" bitfld.long 0x10 7. "TXEN,tx_en" "0,1" newline hexmask.long.byte 0x10 3.--6. 1. "TXDRV,tx_drv" bitfld.long 0x10 2. "TX_CM,tx_cm" "0,1" bitfld.long 0x10 1. "RTERM_EN,rterm enable" "0,1" newline bitfld.long 0x10 0. "BIAS_EN,bias enable" "0,1" tree.end repeat.end elif (CORENAME()=="CORTEXA55") tree "LVDS_COMMON" base ad:0x30C40000 group.long 0x0++0xF line.long 0x0 "SOFT_RESET,lvds softreset" bitfld.long 0x0 6. "TRIM_MODE,trim_mode 1: from fuse 0: form REG" "form REG,from fuse" bitfld.long 0x0 5. "RTE_CTL,rte_ctl control io" "0,1" newline bitfld.long 0x0 4. "COMBINE_SOFT_RESET,combine SOFT_RESET" "0,1" bitfld.long 0x0 3. "CH3_SOFT_RESET,CH4 SOFT_RESET" "0,1" bitfld.long 0x0 2. "CH2_SOFT_RESET,CH3 SOFT_RESET" "0,1" newline bitfld.long 0x0 1. "CH1_SOFT_RESET,CH2 SOFT_RESET" "0,1" bitfld.long 0x0 0. "CH0_SOFT_RESET,CH0 SOFT_RESET" "0,1" line.long 0x4 "MUX_SEL,lvds subsyestem mux sel" bitfld.long 0x4 19.--20. "MUX8_SEL,MUX8_SEL group2 ch2 lvds clock source 00: LVDS PLL1 x7 clock 01: LVDS PLL2 x7 clock 10: LVDS PLL3 x7 clock 11: LVDS PLL4 x7 clock" "LVDS PLL1 x7 clock,LVDS PLL2 x7 clock,?,?" bitfld.long 0x4 17.--18. "MUX7_SEL,MUX7_SEL group2 ch1 lvds clock source 00: LVDS PLL1 x7 clock 01: LVDS PLL2 x7 clock 10: LVDS PLL3 x7 clock 11: LVDS PLL4 x7 clock" "LVDS PLL1 x7 clock,LVDS PLL2 x7 clock,?,?" newline bitfld.long 0x4 15.--16. "MUX6_SEL,MUX6_SEL group 1 ch2 lvds clock source 00: LVDS PLL1 x7 clock 01: LVDS PLL2 x7 clock 10: LVDS PLL3 x7 clock 11: LVDS PLL4 x7 clock" "LVDS PLL1 x7 clock,LVDS PLL2 x7 clock,?,?" bitfld.long 0x4 13.--14. "MUX5_SEL,MUX5_SEL group 1 ch1 lvds clock source 00: LVDS PLL1 x7 clock 01: LVDS PLL2 x7 clock 10: LVDS PLL3 x7 clock 11: LVDS PLL4 x7 clock" "LVDS PLL1 x7 clock,LVDS PLL2 x7 clock,?,?" bitfld.long 0x4 12. "MUX4_SEL,MUX4_SEL pixel combine 0: DC1 and DC2 1: DC3 and DC4" "DC1 and DC2,DC3 and DC4" newline bitfld.long 0x4 9.--11. "MUX3_SEL,MUX0_SEL :group 2 CH2 000: DC1 001: DC2 010: DC3 011: DC4 100: DC5 101: combine output channel 1 110: combine output channel 2 111:not support" "DC1,DC2,?,?,?,?,?,?" bitfld.long 0x4 6.--8. "MUX2_SEL,MUX0_SEL :group 2 CH1 000: DC1 001: DC2 010: DC3 011: DC4 100: DC5 101: combine output channel 1 110: combine output channel 2 111:not support" "DC1,DC2,?,?,?,?,?,?" bitfld.long 0x4 3.--5. "MUX1_SEL,MUX1_SEL :group 1 CH2 000: DC1 001: DC2 010: DC3 011: DC4 100: DC5 101: combine output channel 1 110: combine output channel 2 111:not support" "DC1,DC2,?,?,?,?,?,?" newline bitfld.long 0x4 0.--2. "MUX0_SEL,MUX0_SEL :group1 CH1 000: DC1 001: DC2 010: DC3 011: DC4 100: DC5 101: combine output channel 1 110: combine output channel 2 111:not support" "DC1,DC2,?,?,?,?,?,?" line.long 0x8 "LVDS_COMBINE,lvds_combine" bitfld.long 0x8 29. "ENABLE,lvde combine enable" "0,1" bitfld.long 0x8 28. "COMBINE_MODE,lvds combine mode 0:mode 0 1:mode 1" "mode 0,mode 1" newline bitfld.long 0x8 27. "DATA_EN_POL,data_en polarity" "0,1" bitfld.long 0x8 26. "HSYNC_POL,hsync polarity" "0,1" bitfld.long 0x8 25. "VSYNC_POL,vsync polarity" "0,1" newline bitfld.long 0x8 24. "CH_SWAP,channel swap" "0,1" hexmask.long.byte 0x8 16.--23. 1. "GAP,skip gap" hexmask.long.word 0x8 0.--15. 1. "VLD_HEIGHT,valid height" line.long 0xC "LVDS_BIAS_SET,lvds BIAS setting" bitfld.long 0xC 2.--3. "BIAS_TRIM,bias_trim" "0,1,2,3" bitfld.long 0xC 1. "BIAS_SELVDD,bias_selvdd" "0,1" newline bitfld.long 0xC 0. "BIAS_EN,BIAS_EN" "0,1" repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) group.long ($2+0x100)++0x3 line.long 0x0 "TEST_CFG_$1,test data/enable configure" bitfld.long 0x0 7. "ENABLE,test cfg enable" "0,1" hexmask.long.byte 0x0 0.--6. 1. "DATA,test cfg data" repeat.end group.long 0x10000++0xB line.long 0x0 "LVDS_CH_0,lvds ch0 channel" bitfld.long 0x0 31. "ENABLE,enable" "0,1" bitfld.long 0x0 23.--24. "MUX,mux : the source of data come from 00:: lvds pair0 odd 01:lvds pair0 even 01:lvds pair1 odd 11:lvds pair1 even" "lvds pair0 odd,lvds pair1 odd,?,?" newline bitfld.long 0x0 22. "DUALODD,dual odd/even only when 30bit dualmode" "0,1" hexmask.long.word 0x0 7.--21. 1. "LANE_UPDATE,each lane update slot 2:0 clk lane 5:3 tx0 lane 8:6 tx1 lane 11:9 tx2 lane 14:12 tx3 lane" bitfld.long 0x0 5.--6. "FRAME_MASK,frame mask 00: 0 frame mask 01: 1 frame mask 10: 2 frame mask 11: 3 frame mask" "0,1,2,3" newline bitfld.long 0x0 4. "VSYNC_POL,vsync polarity" "0,1" bitfld.long 0x0 3. "FORMAT,map format 0:jeida 1:swpg" "jeida 1:swpg,?" bitfld.long 0x0 1.--2. "BPP,pixel format 00:18bit 01:24bit 10:30bit" "0,1,2,3" newline bitfld.long 0x0 0. "DUALMODE,dual mode" "0,1" line.long 0x4 "LVDS_CLOCK_0,lvds 0 clock div setting" hexmask.long.byte 0x4 11.--14. 1. "DIV_NUM_DBG,dbg div" hexmask.long.byte 0x4 7.--10. 1. "DIV_NUM_LVDS,lvds div" newline rbitfld.long 0x4 6. "GATING_ACK,gating_ack" "0,1" hexmask.long.byte 0x4 1.--5. 1. "GATING_EN,clock 0:clock disable 1:clock enable gating_en[0]:lvds_clk gating_en[1]:lvds_clk_x7 gating_en[2]:lvds_clk_x3.5 gating_en[3]:dbg_clk gating_en[4]:dsp_clk(from lvds_clk_x7 or lvds_clk_x3.5)" bitfld.long 0x4 0. "SRC_SEL,0: 7 clock 1: 3.5 clock" "0,1" line.long 0x8 "LVDS_CH0_PAD_COM_SET,lvds ch0 common setting" bitfld.long 0x8 14.--16. "LVDS_TRIM,lvds pad trim" "0,1,2,3,4,5,6,7" bitfld.long 0x8 13. "TEST_TXD_P,test_txd_p" "0,1" newline bitfld.long 0x8 12. "TEST_TXD_N,test_tx_n" "0,1" bitfld.long 0x8 11. "TEST_SCHMITT_EN,test_schmitt_en" "0,1" bitfld.long 0x8 10. "TEST_RXEN,test_rxen" "0,1" newline bitfld.long 0x8 9. "TEST_RXCM_EN,test_rxcm_en" "0,1" bitfld.long 0x8 8. "TEST_PULLDN,test_pulldn" "0,1" bitfld.long 0x8 7. "TEST_OEN_P,test_oen_p" "0,1" newline bitfld.long 0x8 6. "TEST_OEN_N,test_oen_n" "0,1" bitfld.long 0x8 5. "TEST_IEN_P,test_ien_p" "0,1" bitfld.long 0x8 4. "TEST_IEN_N,test_ien_n" "0,1" newline group.long 0x10010++0x13 line.long 0x0 "LVDS_CH0_PAD_SET,lvds ch0 pad setting" rbitfld.long 0x0 11. "RXDA,rxda data" "0,1" rbitfld.long 0x0 10. "RXD_P,rxd_p data" "0,1" newline rbitfld.long 0x0 9. "RXD_N,rxd_n data" "0,1" bitfld.long 0x0 8. "VBIAS_SEL,vbais_sel" "0,1" bitfld.long 0x0 7. "TXEN,tx_en" "0,1" newline hexmask.long.byte 0x0 3.--6. 1. "TXDRV,tx_drv" bitfld.long 0x0 2. "TX_CM,tx_cm" "0,1" bitfld.long 0x0 1. "RTERM_EN,rterm enable" "0,1" newline bitfld.long 0x0 0. "BIAS_EN,bias enable" "0,1" line.long 0x4 "LVDS_CH0_PAD_SET,lvds ch0 pad setting" rbitfld.long 0x4 11. "RXDA,rxda data" "0,1" rbitfld.long 0x4 10. "RXD_P,rxd_p data" "0,1" newline rbitfld.long 0x4 9. "RXD_N,rxd_n data" "0,1" bitfld.long 0x4 8. "VBIAS_SEL,vbais_sel" "0,1" bitfld.long 0x4 7. "TXEN,tx_en" "0,1" newline hexmask.long.byte 0x4 3.--6. 1. "TXDRV,tx_drv" bitfld.long 0x4 2. "TX_CM,tx_cm" "0,1" bitfld.long 0x4 1. "RTERM_EN,rterm enable" "0,1" newline bitfld.long 0x4 0. "BIAS_EN,bias enable" "0,1" line.long 0x8 "LVDS_CH0_PAD_SET,lvds ch0 pad setting" rbitfld.long 0x8 11. "RXDA,rxda data" "0,1" rbitfld.long 0x8 10. "RXD_P,rxd_p data" "0,1" newline rbitfld.long 0x8 9. "RXD_N,rxd_n data" "0,1" bitfld.long 0x8 8. "VBIAS_SEL,vbais_sel" "0,1" bitfld.long 0x8 7. "TXEN,tx_en" "0,1" newline hexmask.long.byte 0x8 3.--6. 1. "TXDRV,tx_drv" bitfld.long 0x8 2. "TX_CM,tx_cm" "0,1" bitfld.long 0x8 1. "RTERM_EN,rterm enable" "0,1" newline bitfld.long 0x8 0. "BIAS_EN,bias enable" "0,1" line.long 0xC "LVDS_CH0_PAD_SET,lvds ch0 pad setting" rbitfld.long 0xC 11. "RXDA,rxda data" "0,1" rbitfld.long 0xC 10. "RXD_P,rxd_p data" "0,1" newline rbitfld.long 0xC 9. "RXD_N,rxd_n data" "0,1" bitfld.long 0xC 8. "VBIAS_SEL,vbais_sel" "0,1" bitfld.long 0xC 7. "TXEN,tx_en" "0,1" newline hexmask.long.byte 0xC 3.--6. 1. "TXDRV,tx_drv" bitfld.long 0xC 2. "TX_CM,tx_cm" "0,1" bitfld.long 0xC 1. "RTERM_EN,rterm enable" "0,1" newline bitfld.long 0xC 0. "BIAS_EN,bias enable" "0,1" line.long 0x10 "LVDS_CH0_PAD_SET,lvds ch0 pad setting" rbitfld.long 0x10 11. "RXDA,rxda data" "0,1" rbitfld.long 0x10 10. "RXD_P,rxd_p data" "0,1" newline rbitfld.long 0x10 9. "RXD_N,rxd_n data" "0,1" bitfld.long 0x10 8. "VBIAS_SEL,vbais_sel" "0,1" bitfld.long 0x10 7. "TXEN,tx_en" "0,1" newline hexmask.long.byte 0x10 3.--6. 1. "TXDRV,tx_drv" bitfld.long 0x10 2. "TX_CM,tx_cm" "0,1" bitfld.long 0x10 1. "RTERM_EN,rterm enable" "0,1" newline bitfld.long 0x10 0. "BIAS_EN,bias enable" "0,1" group.long 0x20000++0xB line.long 0x0 "LVDS_CH_1,lvds ch1 channel" bitfld.long 0x0 31. "ENABLE,enable" "0,1" bitfld.long 0x0 23.--24. "MUX,mux : the source of data come from 00:: lvds pair0 odd 01:lvds pair0 even 01:lvds pair1 odd 11:lvds pair1 even" "lvds pair0 odd,lvds pair1 odd,?,?" newline bitfld.long 0x0 22. "DUALODD,dual odd/even only when 30bit dualmode" "0,1" hexmask.long.word 0x0 7.--21. 1. "LANE_UPDATE,each lane update slot 2:0 clk lane 5:3 tx0 lane 8:6 tx1 lane 11:9 tx2 lane 14:12 tx3 lane" bitfld.long 0x0 5.--6. "FRAME_MASK,frame mask 00: 0 frame mask 01: 1 frame mask 10: 2 frame mask 11: 3 frame mask" "0,1,2,3" newline bitfld.long 0x0 4. "VSYNC_POL,vsync polarity" "0,1" bitfld.long 0x0 3. "FORMAT,map format 0:jeida 1:swpg" "jeida 1:swpg,?" bitfld.long 0x0 1.--2. "BPP,pixel format 00:18bit 01:24bit 10:30bit" "0,1,2,3" newline bitfld.long 0x0 0. "DUALMODE,dual mode" "0,1" line.long 0x4 "LVDS_CLOCK_1,lvds 1 clock div setting" hexmask.long.byte 0x4 11.--14. 1. "DIV_NUM_DBG,dbg div" hexmask.long.byte 0x4 7.--10. 1. "DIV_NUM_LVDS,lvds div" newline rbitfld.long 0x4 6. "GATING_ACK,gating_ack" "0,1" hexmask.long.byte 0x4 1.--5. 1. "GATING_EN,clock 0:clock disable 1:clock enable gating_en[0]:lvds_clk gating_en[1]:lvds_clk_x7 gating_en[2]:lvds_clk_x3.5 gating_en[3]:dbg_clk gating_en[4]:dsp_clk(from lvds_clk_x7 or lvds_clk_x3.5)" bitfld.long 0x4 0. "SRC_SEL,0: 7 clock 1: 3.5 clock" "0,1" line.long 0x8 "LVDS_CH1_PAD_COM_SET,lvds ch1 common setting" bitfld.long 0x8 14.--16. "LVDS_TRIM,lvds pad trim" "0,1,2,3,4,5,6,7" bitfld.long 0x8 13. "TEST_TXD_P,test_txd_p" "0,1" newline bitfld.long 0x8 12. "TEST_TXD_N,test_tx_n" "0,1" bitfld.long 0x8 11. "TEST_SCHMITT_EN,test_schmitt_en" "0,1" bitfld.long 0x8 10. "TEST_RXEN,test_rxen" "0,1" newline bitfld.long 0x8 9. "TEST_RXCM_EN,test_rxcm_en" "0,1" bitfld.long 0x8 8. "TEST_PULLDN,test_pulldn" "0,1" bitfld.long 0x8 7. "TEST_OEN_P,test_oen_p" "0,1" newline bitfld.long 0x8 6. "TEST_OEN_N,test_oen_n" "0,1" bitfld.long 0x8 5. "TEST_IEN_P,test_ien_p" "0,1" bitfld.long 0x8 4. "TEST_IEN_N,test_ien_n" "0,1" newline group.long 0x20010++0x13 line.long 0x0 "LVDS_CH1_PAD_SET,lvds ch1 pad setting" rbitfld.long 0x0 11. "RXDA,rxda data" "0,1" rbitfld.long 0x0 10. "RXD_P,rxd_p data" "0,1" newline rbitfld.long 0x0 9. "RXD_N,rxd_n data" "0,1" bitfld.long 0x0 8. "VBIAS_SEL,vbais_sel" "0,1" bitfld.long 0x0 7. "TXEN,tx_en" "0,1" newline hexmask.long.byte 0x0 3.--6. 1. "TXDRV,tx_drv" bitfld.long 0x0 2. "TX_CM,tx_cm" "0,1" bitfld.long 0x0 1. "RTERM_EN,rterm enable" "0,1" newline bitfld.long 0x0 0. "BIAS_EN,bias enable" "0,1" line.long 0x4 "LVDS_CH1_PAD_SET,lvds ch1 pad setting" rbitfld.long 0x4 11. "RXDA,rxda data" "0,1" rbitfld.long 0x4 10. "RXD_P,rxd_p data" "0,1" newline rbitfld.long 0x4 9. "RXD_N,rxd_n data" "0,1" bitfld.long 0x4 8. "VBIAS_SEL,vbais_sel" "0,1" bitfld.long 0x4 7. "TXEN,tx_en" "0,1" newline hexmask.long.byte 0x4 3.--6. 1. "TXDRV,tx_drv" bitfld.long 0x4 2. "TX_CM,tx_cm" "0,1" bitfld.long 0x4 1. "RTERM_EN,rterm enable" "0,1" newline bitfld.long 0x4 0. "BIAS_EN,bias enable" "0,1" line.long 0x8 "LVDS_CH1_PAD_SET,lvds ch1 pad setting" rbitfld.long 0x8 11. "RXDA,rxda data" "0,1" rbitfld.long 0x8 10. "RXD_P,rxd_p data" "0,1" newline rbitfld.long 0x8 9. "RXD_N,rxd_n data" "0,1" bitfld.long 0x8 8. "VBIAS_SEL,vbais_sel" "0,1" bitfld.long 0x8 7. "TXEN,tx_en" "0,1" newline hexmask.long.byte 0x8 3.--6. 1. "TXDRV,tx_drv" bitfld.long 0x8 2. "TX_CM,tx_cm" "0,1" bitfld.long 0x8 1. "RTERM_EN,rterm enable" "0,1" newline bitfld.long 0x8 0. "BIAS_EN,bias enable" "0,1" line.long 0xC "LVDS_CH1_PAD_SET,lvds ch1 pad setting" rbitfld.long 0xC 11. "RXDA,rxda data" "0,1" rbitfld.long 0xC 10. "RXD_P,rxd_p data" "0,1" newline rbitfld.long 0xC 9. "RXD_N,rxd_n data" "0,1" bitfld.long 0xC 8. "VBIAS_SEL,vbais_sel" "0,1" bitfld.long 0xC 7. "TXEN,tx_en" "0,1" newline hexmask.long.byte 0xC 3.--6. 1. "TXDRV,tx_drv" bitfld.long 0xC 2. "TX_CM,tx_cm" "0,1" bitfld.long 0xC 1. "RTERM_EN,rterm enable" "0,1" newline bitfld.long 0xC 0. "BIAS_EN,bias enable" "0,1" line.long 0x10 "LVDS_CH1_PAD_SET,lvds ch1 pad setting" rbitfld.long 0x10 11. "RXDA,rxda data" "0,1" rbitfld.long 0x10 10. "RXD_P,rxd_p data" "0,1" newline rbitfld.long 0x10 9. "RXD_N,rxd_n data" "0,1" bitfld.long 0x10 8. "VBIAS_SEL,vbais_sel" "0,1" bitfld.long 0x10 7. "TXEN,tx_en" "0,1" newline hexmask.long.byte 0x10 3.--6. 1. "TXDRV,tx_drv" bitfld.long 0x10 2. "TX_CM,tx_cm" "0,1" bitfld.long 0x10 1. "RTERM_EN,rterm enable" "0,1" newline bitfld.long 0x10 0. "BIAS_EN,bias enable" "0,1" group.long 0x30000++0xB line.long 0x0 "LVDS_CH_2,lvds ch2 channel" bitfld.long 0x0 31. "ENABLE,enable" "0,1" bitfld.long 0x0 23.--24. "MUX,mux : the source of data come from 00:: lvds pair0 odd 01:lvds pair0 even 01:lvds pair1 odd 11:lvds pair1 even" "lvds pair0 odd,lvds pair1 odd,?,?" newline bitfld.long 0x0 22. "DUALODD,dual odd/even only when 30bit dualmode" "0,1" hexmask.long.word 0x0 7.--21. 1. "LANE_UPDATE,each lane update slot 2:0 clk lane 5:3 tx0 lane 8:6 tx1 lane 11:9 tx2 lane 14:12 tx3 lane" bitfld.long 0x0 5.--6. "FRAME_MASK,frame mask 00: 0 frame mask 01: 1 frame mask 10: 2 frame mask 11: 3 frame mask" "0,1,2,3" newline bitfld.long 0x0 4. "VSYNC_POL,vsync polarity" "0,1" bitfld.long 0x0 3. "FORMAT,map format 0:jeida 1:swpg" "jeida 1:swpg,?" bitfld.long 0x0 1.--2. "BPP,pixel format 00:18bit 01:24bit 10:30bit" "0,1,2,3" newline bitfld.long 0x0 0. "DUALMODE,dual mode" "0,1" line.long 0x4 "LVDS_CLOCK_2,lvds 2 clock div setting" hexmask.long.byte 0x4 11.--14. 1. "DIV_NUM_DBG,dbg div" hexmask.long.byte 0x4 7.--10. 1. "DIV_NUM_LVDS,lvds div" newline rbitfld.long 0x4 6. "GATING_ACK,gating_ack" "0,1" hexmask.long.byte 0x4 1.--5. 1. "GATING_EN,clock 0:clock disable 1:clock enable gating_en[0]:lvds_clk gating_en[1]:lvds_clk_x7 gating_en[2]:lvds_clk_x3.5 gating_en[3]:dbg_clk gating_en[4]:dsp_clk(from lvds_clk_x7 or lvds_clk_x3.5)" bitfld.long 0x4 0. "SRC_SEL,0: 7 clock 1: 3.5 clock" "0,1" line.long 0x8 "LVDS_CH2_PAD_COM_SET,lvds ch2 common setting" bitfld.long 0x8 14.--16. "LVDS_TRIM,lvds pad trim" "0,1,2,3,4,5,6,7" bitfld.long 0x8 13. "TEST_TXD_P,test_txd_p" "0,1" newline bitfld.long 0x8 12. "TEST_TXD_N,test_tx_n" "0,1" bitfld.long 0x8 11. "TEST_SCHMITT_EN,test_schmitt_en" "0,1" bitfld.long 0x8 10. "TEST_RXEN,test_rxen" "0,1" newline bitfld.long 0x8 9. "TEST_RXCM_EN,test_rxcm_en" "0,1" bitfld.long 0x8 8. "TEST_PULLDN,test_pulldn" "0,1" bitfld.long 0x8 7. "TEST_OEN_P,test_oen_p" "0,1" newline bitfld.long 0x8 6. "TEST_OEN_N,test_oen_n" "0,1" bitfld.long 0x8 5. "TEST_IEN_P,test_ien_p" "0,1" bitfld.long 0x8 4. "TEST_IEN_N,test_ien_n" "0,1" newline group.long 0x30010++0x13 line.long 0x0 "LVDS_CH2_PAD_SET,lvds ch2 pad setting" rbitfld.long 0x0 11. "RXDA,rxda data" "0,1" rbitfld.long 0x0 10. "RXD_P,rxd_p data" "0,1" newline rbitfld.long 0x0 9. "RXD_N,rxd_n data" "0,1" bitfld.long 0x0 8. "VBIAS_SEL,vbais_sel" "0,1" bitfld.long 0x0 7. "TXEN,tx_en" "0,1" newline hexmask.long.byte 0x0 3.--6. 1. "TXDRV,tx_drv" bitfld.long 0x0 2. "TX_CM,tx_cm" "0,1" bitfld.long 0x0 1. "RTERM_EN,rterm enable" "0,1" newline bitfld.long 0x0 0. "BIAS_EN,bias enable" "0,1" line.long 0x4 "LVDS_CH2_PAD_SET,lvds ch2 pad setting" rbitfld.long 0x4 11. "RXDA,rxda data" "0,1" rbitfld.long 0x4 10. "RXD_P,rxd_p data" "0,1" newline rbitfld.long 0x4 9. "RXD_N,rxd_n data" "0,1" bitfld.long 0x4 8. "VBIAS_SEL,vbais_sel" "0,1" bitfld.long 0x4 7. "TXEN,tx_en" "0,1" newline hexmask.long.byte 0x4 3.--6. 1. "TXDRV,tx_drv" bitfld.long 0x4 2. "TX_CM,tx_cm" "0,1" bitfld.long 0x4 1. "RTERM_EN,rterm enable" "0,1" newline bitfld.long 0x4 0. "BIAS_EN,bias enable" "0,1" line.long 0x8 "LVDS_CH2_PAD_SET,lvds ch2 pad setting" rbitfld.long 0x8 11. "RXDA,rxda data" "0,1" rbitfld.long 0x8 10. "RXD_P,rxd_p data" "0,1" newline rbitfld.long 0x8 9. "RXD_N,rxd_n data" "0,1" bitfld.long 0x8 8. "VBIAS_SEL,vbais_sel" "0,1" bitfld.long 0x8 7. "TXEN,tx_en" "0,1" newline hexmask.long.byte 0x8 3.--6. 1. "TXDRV,tx_drv" bitfld.long 0x8 2. "TX_CM,tx_cm" "0,1" bitfld.long 0x8 1. "RTERM_EN,rterm enable" "0,1" newline bitfld.long 0x8 0. "BIAS_EN,bias enable" "0,1" line.long 0xC "LVDS_CH2_PAD_SET,lvds ch2 pad setting" rbitfld.long 0xC 11. "RXDA,rxda data" "0,1" rbitfld.long 0xC 10. "RXD_P,rxd_p data" "0,1" newline rbitfld.long 0xC 9. "RXD_N,rxd_n data" "0,1" bitfld.long 0xC 8. "VBIAS_SEL,vbais_sel" "0,1" bitfld.long 0xC 7. "TXEN,tx_en" "0,1" newline hexmask.long.byte 0xC 3.--6. 1. "TXDRV,tx_drv" bitfld.long 0xC 2. "TX_CM,tx_cm" "0,1" bitfld.long 0xC 1. "RTERM_EN,rterm enable" "0,1" newline bitfld.long 0xC 0. "BIAS_EN,bias enable" "0,1" line.long 0x10 "LVDS_CH2_PAD_SET,lvds ch2 pad setting" rbitfld.long 0x10 11. "RXDA,rxda data" "0,1" rbitfld.long 0x10 10. "RXD_P,rxd_p data" "0,1" newline rbitfld.long 0x10 9. "RXD_N,rxd_n data" "0,1" bitfld.long 0x10 8. "VBIAS_SEL,vbais_sel" "0,1" bitfld.long 0x10 7. "TXEN,tx_en" "0,1" newline hexmask.long.byte 0x10 3.--6. 1. "TXDRV,tx_drv" bitfld.long 0x10 2. "TX_CM,tx_cm" "0,1" bitfld.long 0x10 1. "RTERM_EN,rterm enable" "0,1" newline bitfld.long 0x10 0. "BIAS_EN,bias enable" "0,1" group.long 0x40000++0xB line.long 0x0 "LVDS_CH_3,lvds ch3 channel" bitfld.long 0x0 31. "ENABLE,enable" "0,1" bitfld.long 0x0 23.--24. "MUX,mux : the source of data come from 00:: lvds pair0 odd 01:lvds pair0 even 01:lvds pair1 odd 11:lvds pair1 even" "lvds pair0 odd,lvds pair1 odd,?,?" newline bitfld.long 0x0 22. "DUALODD,dual odd/even only when 30bit dualmode" "0,1" hexmask.long.word 0x0 7.--21. 1. "LANE_UPDATE,each lane update slot 2:0 clk lane 5:3 tx0 lane 8:6 tx1 lane 11:9 tx2 lane 14:12 tx3 lane" bitfld.long 0x0 5.--6. "FRAME_MASK,frame mask 00: 0 frame mask 01: 1 frame mask 10: 2 frame mask 11: 3 frame mask" "0,1,2,3" newline bitfld.long 0x0 4. "VSYNC_POL,vsync polarity" "0,1" bitfld.long 0x0 3. "FORMAT,map format 0:jeida 1:swpg" "jeida 1:swpg,?" bitfld.long 0x0 1.--2. "BPP,pixel format 00:18bit 01:24bit 10:30bit" "0,1,2,3" newline bitfld.long 0x0 0. "DUALMODE,dual mode" "0,1" line.long 0x4 "LVDS_CLOCK_3,lvds 3 clock div setting" hexmask.long.byte 0x4 11.--14. 1. "DIV_NUM_DBG,dbg div" hexmask.long.byte 0x4 7.--10. 1. "DIV_NUM_LVDS,lvds div" newline rbitfld.long 0x4 6. "GATING_ACK,gating_ack" "0,1" hexmask.long.byte 0x4 1.--5. 1. "GATING_EN,clock 0:clock disable 1:clock enable gating_en[0]:lvds_clk gating_en[1]:lvds_clk_x7 gating_en[2]:lvds_clk_x3.5 gating_en[3]:dbg_clk gating_en[4]:dsp_clk(from lvds_clk_x7 or lvds_clk_x3.5)" bitfld.long 0x4 0. "SRC_SEL,0: 7 clock 1: 3.5 clock" "0,1" line.long 0x8 "LVDS_CH3_PAD_COM_SET,lvds ch3 common setting" bitfld.long 0x8 14.--16. "LVDS_TRIM,lvds pad trim" "0,1,2,3,4,5,6,7" bitfld.long 0x8 13. "TEST_TXD_P,test_txd_p" "0,1" newline bitfld.long 0x8 12. "TEST_TXD_N,test_tx_n" "0,1" bitfld.long 0x8 11. "TEST_SCHMITT_EN,test_schmitt_en" "0,1" bitfld.long 0x8 10. "TEST_RXEN,test_rxen" "0,1" newline bitfld.long 0x8 9. "TEST_RXCM_EN,test_rxcm_en" "0,1" bitfld.long 0x8 8. "TEST_PULLDN,test_pulldn" "0,1" bitfld.long 0x8 7. "TEST_OEN_P,test_oen_p" "0,1" newline bitfld.long 0x8 6. "TEST_OEN_N,test_oen_n" "0,1" bitfld.long 0x8 5. "TEST_IEN_P,test_ien_p" "0,1" bitfld.long 0x8 4. "TEST_IEN_N,test_ien_n" "0,1" newline group.long 0x40010++0x13 line.long 0x0 "LVDS_CH3_PAD_SET,lvds ch3 pad setting" rbitfld.long 0x0 11. "RXDA,rxda data" "0,1" rbitfld.long 0x0 10. "RXD_P,rxd_p data" "0,1" newline rbitfld.long 0x0 9. "RXD_N,rxd_n data" "0,1" bitfld.long 0x0 8. "VBIAS_SEL,vbais_sel" "0,1" bitfld.long 0x0 7. "TXEN,tx_en" "0,1" newline hexmask.long.byte 0x0 3.--6. 1. "TXDRV,tx_drv" bitfld.long 0x0 2. "TX_CM,tx_cm" "0,1" bitfld.long 0x0 1. "RTERM_EN,rterm enable" "0,1" newline bitfld.long 0x0 0. "BIAS_EN,bias enable" "0,1" line.long 0x4 "LVDS_CH3_PAD_SET,lvds ch3 pad setting" rbitfld.long 0x4 11. "RXDA,rxda data" "0,1" rbitfld.long 0x4 10. "RXD_P,rxd_p data" "0,1" newline rbitfld.long 0x4 9. "RXD_N,rxd_n data" "0,1" bitfld.long 0x4 8. "VBIAS_SEL,vbais_sel" "0,1" bitfld.long 0x4 7. "TXEN,tx_en" "0,1" newline hexmask.long.byte 0x4 3.--6. 1. "TXDRV,tx_drv" bitfld.long 0x4 2. "TX_CM,tx_cm" "0,1" bitfld.long 0x4 1. "RTERM_EN,rterm enable" "0,1" newline bitfld.long 0x4 0. "BIAS_EN,bias enable" "0,1" line.long 0x8 "LVDS_CH3_PAD_SET,lvds ch3 pad setting" rbitfld.long 0x8 11. "RXDA,rxda data" "0,1" rbitfld.long 0x8 10. "RXD_P,rxd_p data" "0,1" newline rbitfld.long 0x8 9. "RXD_N,rxd_n data" "0,1" bitfld.long 0x8 8. "VBIAS_SEL,vbais_sel" "0,1" bitfld.long 0x8 7. "TXEN,tx_en" "0,1" newline hexmask.long.byte 0x8 3.--6. 1. "TXDRV,tx_drv" bitfld.long 0x8 2. "TX_CM,tx_cm" "0,1" bitfld.long 0x8 1. "RTERM_EN,rterm enable" "0,1" newline bitfld.long 0x8 0. "BIAS_EN,bias enable" "0,1" line.long 0xC "LVDS_CH3_PAD_SET,lvds ch3 pad setting" rbitfld.long 0xC 11. "RXDA,rxda data" "0,1" rbitfld.long 0xC 10. "RXD_P,rxd_p data" "0,1" newline rbitfld.long 0xC 9. "RXD_N,rxd_n data" "0,1" bitfld.long 0xC 8. "VBIAS_SEL,vbais_sel" "0,1" bitfld.long 0xC 7. "TXEN,tx_en" "0,1" newline hexmask.long.byte 0xC 3.--6. 1. "TXDRV,tx_drv" bitfld.long 0xC 2. "TX_CM,tx_cm" "0,1" bitfld.long 0xC 1. "RTERM_EN,rterm enable" "0,1" newline bitfld.long 0xC 0. "BIAS_EN,bias enable" "0,1" line.long 0x10 "LVDS_CH3_PAD_SET,lvds ch3 pad setting" rbitfld.long 0x10 11. "RXDA,rxda data" "0,1" rbitfld.long 0x10 10. "RXD_P,rxd_p data" "0,1" newline rbitfld.long 0x10 9. "RXD_N,rxd_n data" "0,1" bitfld.long 0x10 8. "VBIAS_SEL,vbais_sel" "0,1" bitfld.long 0x10 7. "TXEN,tx_en" "0,1" newline hexmask.long.byte 0x10 3.--6. 1. "TXDRV,tx_drv" bitfld.long 0x10 2. "TX_CM,tx_cm" "0,1" bitfld.long 0x10 1. "RTERM_EN,rterm enable" "0,1" newline bitfld.long 0x10 0. "BIAS_EN,bias enable" "0,1" tree.end repeat 4. (increment 1. 1) (list ad:0x30C50000 ad:0x30C60000 ad:0x30C70000 ad:0x30C80000) tree "LVDS$1" base $2 group.long 0x0++0xF line.long 0x0 "SOFT_RESET,lvds softreset" bitfld.long 0x0 6. "TRIM_MODE,trim_mode 1: from fuse 0: form REG" "form REG,from fuse" bitfld.long 0x0 5. "RTE_CTL,rte_ctl control io" "0,1" newline bitfld.long 0x0 4. "COMBINE_SOFT_RESET,combine SOFT_RESET" "0,1" bitfld.long 0x0 3. "CH3_SOFT_RESET,CH4 SOFT_RESET" "0,1" bitfld.long 0x0 2. "CH2_SOFT_RESET,CH3 SOFT_RESET" "0,1" newline bitfld.long 0x0 1. "CH1_SOFT_RESET,CH2 SOFT_RESET" "0,1" bitfld.long 0x0 0. "CH0_SOFT_RESET,CH0 SOFT_RESET" "0,1" line.long 0x4 "MUX_SEL,lvds subsyestem mux sel" bitfld.long 0x4 19.--20. "MUX8_SEL,MUX8_SEL group2 ch2 lvds clock source 00: LVDS PLL1 x7 clock 01: LVDS PLL2 x7 clock 10: LVDS PLL3 x7 clock 11: LVDS PLL4 x7 clock" "LVDS PLL1 x7 clock,LVDS PLL2 x7 clock,?,?" bitfld.long 0x4 17.--18. "MUX7_SEL,MUX7_SEL group2 ch1 lvds clock source 00: LVDS PLL1 x7 clock 01: LVDS PLL2 x7 clock 10: LVDS PLL3 x7 clock 11: LVDS PLL4 x7 clock" "LVDS PLL1 x7 clock,LVDS PLL2 x7 clock,?,?" newline bitfld.long 0x4 15.--16. "MUX6_SEL,MUX6_SEL group 1 ch2 lvds clock source 00: LVDS PLL1 x7 clock 01: LVDS PLL2 x7 clock 10: LVDS PLL3 x7 clock 11: LVDS PLL4 x7 clock" "LVDS PLL1 x7 clock,LVDS PLL2 x7 clock,?,?" bitfld.long 0x4 13.--14. "MUX5_SEL,MUX5_SEL group 1 ch1 lvds clock source 00: LVDS PLL1 x7 clock 01: LVDS PLL2 x7 clock 10: LVDS PLL3 x7 clock 11: LVDS PLL4 x7 clock" "LVDS PLL1 x7 clock,LVDS PLL2 x7 clock,?,?" bitfld.long 0x4 12. "MUX4_SEL,MUX4_SEL pixel combine 0: DC1 and DC2 1: DC3 and DC4" "DC1 and DC2,DC3 and DC4" newline bitfld.long 0x4 9.--11. "MUX3_SEL,MUX0_SEL :group 2 CH2 000: DC1 001: DC2 010: DC3 011: DC4 100: DC5 101: combine output channel 1 110: combine output channel 2 111:not support" "DC1,DC2,?,?,?,?,?,?" bitfld.long 0x4 6.--8. "MUX2_SEL,MUX0_SEL :group 2 CH1 000: DC1 001: DC2 010: DC3 011: DC4 100: DC5 101: combine output channel 1 110: combine output channel 2 111:not support" "DC1,DC2,?,?,?,?,?,?" bitfld.long 0x4 3.--5. "MUX1_SEL,MUX1_SEL :group 1 CH2 000: DC1 001: DC2 010: DC3 011: DC4 100: DC5 101: combine output channel 1 110: combine output channel 2 111:not support" "DC1,DC2,?,?,?,?,?,?" newline bitfld.long 0x4 0.--2. "MUX0_SEL,MUX0_SEL :group1 CH1 000: DC1 001: DC2 010: DC3 011: DC4 100: DC5 101: combine output channel 1 110: combine output channel 2 111:not support" "DC1,DC2,?,?,?,?,?,?" line.long 0x8 "LVDS_COMBINE,lvds_combine" bitfld.long 0x8 29. "ENABLE,lvde combine enable" "0,1" bitfld.long 0x8 28. "COMBINE_MODE,lvds combine mode 0:mode 0 1:mode 1" "mode 0,mode 1" newline bitfld.long 0x8 27. "DATA_EN_POL,data_en polarity" "0,1" bitfld.long 0x8 26. "HSYNC_POL,hsync polarity" "0,1" bitfld.long 0x8 25. "VSYNC_POL,vsync polarity" "0,1" newline bitfld.long 0x8 24. "CH_SWAP,channel swap" "0,1" hexmask.long.byte 0x8 16.--23. 1. "GAP,skip gap" hexmask.long.word 0x8 0.--15. 1. "VLD_HEIGHT,valid height" line.long 0xC "LVDS_BIAS_SET,lvds BIAS setting" bitfld.long 0xC 2.--3. "BIAS_TRIM,bias_trim" "0,1,2,3" bitfld.long 0xC 1. "BIAS_SELVDD,bias_selvdd" "0,1" newline bitfld.long 0xC 0. "BIAS_EN,BIAS_EN" "0,1" repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) group.long ($2+0x100)++0x3 line.long 0x0 "TEST_CFG_$1,test data/enable configure" bitfld.long 0x0 7. "ENABLE,test cfg enable" "0,1" hexmask.long.byte 0x0 0.--6. 1. "DATA,test cfg data" repeat.end group.long 0x10000++0xB line.long 0x0 "LVDS_CH_0,lvds ch0 channel" bitfld.long 0x0 31. "ENABLE,enable" "0,1" bitfld.long 0x0 23.--24. "MUX,mux : the source of data come from 00:: lvds pair0 odd 01:lvds pair0 even 01:lvds pair1 odd 11:lvds pair1 even" "lvds pair0 odd,lvds pair1 odd,?,?" newline bitfld.long 0x0 22. "DUALODD,dual odd/even only when 30bit dualmode" "0,1" hexmask.long.word 0x0 7.--21. 1. "LANE_UPDATE,each lane update slot 2:0 clk lane 5:3 tx0 lane 8:6 tx1 lane 11:9 tx2 lane 14:12 tx3 lane" bitfld.long 0x0 5.--6. "FRAME_MASK,frame mask 00: 0 frame mask 01: 1 frame mask 10: 2 frame mask 11: 3 frame mask" "0,1,2,3" newline bitfld.long 0x0 4. "VSYNC_POL,vsync polarity" "0,1" bitfld.long 0x0 3. "FORMAT,map format 0:jeida 1:swpg" "jeida 1:swpg,?" bitfld.long 0x0 1.--2. "BPP,pixel format 00:18bit 01:24bit 10:30bit" "0,1,2,3" newline bitfld.long 0x0 0. "DUALMODE,dual mode" "0,1" line.long 0x4 "LVDS_CLOCK_0,lvds 0 clock div setting" hexmask.long.byte 0x4 11.--14. 1. "DIV_NUM_DBG,dbg div" hexmask.long.byte 0x4 7.--10. 1. "DIV_NUM_LVDS,lvds div" newline rbitfld.long 0x4 6. "GATING_ACK,gating_ack" "0,1" hexmask.long.byte 0x4 1.--5. 1. "GATING_EN,clock 0:clock disable 1:clock enable gating_en[0]:lvds_clk gating_en[1]:lvds_clk_x7 gating_en[2]:lvds_clk_x3.5 gating_en[3]:dbg_clk gating_en[4]:dsp_clk(from lvds_clk_x7 or lvds_clk_x3.5)" bitfld.long 0x4 0. "SRC_SEL,0: 7 clock 1: 3.5 clock" "0,1" line.long 0x8 "LVDS_CH0_PAD_COM_SET,lvds ch0 common setting" bitfld.long 0x8 14.--16. "LVDS_TRIM,lvds pad trim" "0,1,2,3,4,5,6,7" bitfld.long 0x8 13. "TEST_TXD_P,test_txd_p" "0,1" newline bitfld.long 0x8 12. "TEST_TXD_N,test_tx_n" "0,1" bitfld.long 0x8 11. "TEST_SCHMITT_EN,test_schmitt_en" "0,1" bitfld.long 0x8 10. "TEST_RXEN,test_rxen" "0,1" newline bitfld.long 0x8 9. "TEST_RXCM_EN,test_rxcm_en" "0,1" bitfld.long 0x8 8. "TEST_PULLDN,test_pulldn" "0,1" bitfld.long 0x8 7. "TEST_OEN_P,test_oen_p" "0,1" newline bitfld.long 0x8 6. "TEST_OEN_N,test_oen_n" "0,1" bitfld.long 0x8 5. "TEST_IEN_P,test_ien_p" "0,1" bitfld.long 0x8 4. "TEST_IEN_N,test_ien_n" "0,1" newline group.long 0x10010++0x13 line.long 0x0 "LVDS_CH0_PAD_SET,lvds ch0 pad setting" rbitfld.long 0x0 11. "RXDA,rxda data" "0,1" rbitfld.long 0x0 10. "RXD_P,rxd_p data" "0,1" newline rbitfld.long 0x0 9. "RXD_N,rxd_n data" "0,1" bitfld.long 0x0 8. "VBIAS_SEL,vbais_sel" "0,1" bitfld.long 0x0 7. "TXEN,tx_en" "0,1" newline hexmask.long.byte 0x0 3.--6. 1. "TXDRV,tx_drv" bitfld.long 0x0 2. "TX_CM,tx_cm" "0,1" bitfld.long 0x0 1. "RTERM_EN,rterm enable" "0,1" newline bitfld.long 0x0 0. "BIAS_EN,bias enable" "0,1" line.long 0x4 "LVDS_CH0_PAD_SET,lvds ch0 pad setting" rbitfld.long 0x4 11. "RXDA,rxda data" "0,1" rbitfld.long 0x4 10. "RXD_P,rxd_p data" "0,1" newline rbitfld.long 0x4 9. "RXD_N,rxd_n data" "0,1" bitfld.long 0x4 8. "VBIAS_SEL,vbais_sel" "0,1" bitfld.long 0x4 7. "TXEN,tx_en" "0,1" newline hexmask.long.byte 0x4 3.--6. 1. "TXDRV,tx_drv" bitfld.long 0x4 2. "TX_CM,tx_cm" "0,1" bitfld.long 0x4 1. "RTERM_EN,rterm enable" "0,1" newline bitfld.long 0x4 0. "BIAS_EN,bias enable" "0,1" line.long 0x8 "LVDS_CH0_PAD_SET,lvds ch0 pad setting" rbitfld.long 0x8 11. "RXDA,rxda data" "0,1" rbitfld.long 0x8 10. "RXD_P,rxd_p data" "0,1" newline rbitfld.long 0x8 9. "RXD_N,rxd_n data" "0,1" bitfld.long 0x8 8. "VBIAS_SEL,vbais_sel" "0,1" bitfld.long 0x8 7. "TXEN,tx_en" "0,1" newline hexmask.long.byte 0x8 3.--6. 1. "TXDRV,tx_drv" bitfld.long 0x8 2. "TX_CM,tx_cm" "0,1" bitfld.long 0x8 1. "RTERM_EN,rterm enable" "0,1" newline bitfld.long 0x8 0. "BIAS_EN,bias enable" "0,1" line.long 0xC "LVDS_CH0_PAD_SET,lvds ch0 pad setting" rbitfld.long 0xC 11. "RXDA,rxda data" "0,1" rbitfld.long 0xC 10. "RXD_P,rxd_p data" "0,1" newline rbitfld.long 0xC 9. "RXD_N,rxd_n data" "0,1" bitfld.long 0xC 8. "VBIAS_SEL,vbais_sel" "0,1" bitfld.long 0xC 7. "TXEN,tx_en" "0,1" newline hexmask.long.byte 0xC 3.--6. 1. "TXDRV,tx_drv" bitfld.long 0xC 2. "TX_CM,tx_cm" "0,1" bitfld.long 0xC 1. "RTERM_EN,rterm enable" "0,1" newline bitfld.long 0xC 0. "BIAS_EN,bias enable" "0,1" line.long 0x10 "LVDS_CH0_PAD_SET,lvds ch0 pad setting" rbitfld.long 0x10 11. "RXDA,rxda data" "0,1" rbitfld.long 0x10 10. "RXD_P,rxd_p data" "0,1" newline rbitfld.long 0x10 9. "RXD_N,rxd_n data" "0,1" bitfld.long 0x10 8. "VBIAS_SEL,vbais_sel" "0,1" bitfld.long 0x10 7. "TXEN,tx_en" "0,1" newline hexmask.long.byte 0x10 3.--6. 1. "TXDRV,tx_drv" bitfld.long 0x10 2. "TX_CM,tx_cm" "0,1" bitfld.long 0x10 1. "RTERM_EN,rterm enable" "0,1" newline bitfld.long 0x10 0. "BIAS_EN,bias enable" "0,1" group.long 0x20000++0xB line.long 0x0 "LVDS_CH_1,lvds ch1 channel" bitfld.long 0x0 31. "ENABLE,enable" "0,1" bitfld.long 0x0 23.--24. "MUX,mux : the source of data come from 00:: lvds pair0 odd 01:lvds pair0 even 01:lvds pair1 odd 11:lvds pair1 even" "lvds pair0 odd,lvds pair1 odd,?,?" newline bitfld.long 0x0 22. "DUALODD,dual odd/even only when 30bit dualmode" "0,1" hexmask.long.word 0x0 7.--21. 1. "LANE_UPDATE,each lane update slot 2:0 clk lane 5:3 tx0 lane 8:6 tx1 lane 11:9 tx2 lane 14:12 tx3 lane" bitfld.long 0x0 5.--6. "FRAME_MASK,frame mask 00: 0 frame mask 01: 1 frame mask 10: 2 frame mask 11: 3 frame mask" "0,1,2,3" newline bitfld.long 0x0 4. "VSYNC_POL,vsync polarity" "0,1" bitfld.long 0x0 3. "FORMAT,map format 0:jeida 1:swpg" "jeida 1:swpg,?" bitfld.long 0x0 1.--2. "BPP,pixel format 00:18bit 01:24bit 10:30bit" "0,1,2,3" newline bitfld.long 0x0 0. "DUALMODE,dual mode" "0,1" line.long 0x4 "LVDS_CLOCK_1,lvds 1 clock div setting" hexmask.long.byte 0x4 11.--14. 1. "DIV_NUM_DBG,dbg div" hexmask.long.byte 0x4 7.--10. 1. "DIV_NUM_LVDS,lvds div" newline rbitfld.long 0x4 6. "GATING_ACK,gating_ack" "0,1" hexmask.long.byte 0x4 1.--5. 1. "GATING_EN,clock 0:clock disable 1:clock enable gating_en[0]:lvds_clk gating_en[1]:lvds_clk_x7 gating_en[2]:lvds_clk_x3.5 gating_en[3]:dbg_clk gating_en[4]:dsp_clk(from lvds_clk_x7 or lvds_clk_x3.5)" bitfld.long 0x4 0. "SRC_SEL,0: 7 clock 1: 3.5 clock" "0,1" line.long 0x8 "LVDS_CH1_PAD_COM_SET,lvds ch1 common setting" bitfld.long 0x8 14.--16. "LVDS_TRIM,lvds pad trim" "0,1,2,3,4,5,6,7" bitfld.long 0x8 13. "TEST_TXD_P,test_txd_p" "0,1" newline bitfld.long 0x8 12. "TEST_TXD_N,test_tx_n" "0,1" bitfld.long 0x8 11. "TEST_SCHMITT_EN,test_schmitt_en" "0,1" bitfld.long 0x8 10. "TEST_RXEN,test_rxen" "0,1" newline bitfld.long 0x8 9. "TEST_RXCM_EN,test_rxcm_en" "0,1" bitfld.long 0x8 8. "TEST_PULLDN,test_pulldn" "0,1" bitfld.long 0x8 7. "TEST_OEN_P,test_oen_p" "0,1" newline bitfld.long 0x8 6. "TEST_OEN_N,test_oen_n" "0,1" bitfld.long 0x8 5. "TEST_IEN_P,test_ien_p" "0,1" bitfld.long 0x8 4. "TEST_IEN_N,test_ien_n" "0,1" newline group.long 0x20010++0x13 line.long 0x0 "LVDS_CH1_PAD_SET,lvds ch1 pad setting" rbitfld.long 0x0 11. "RXDA,rxda data" "0,1" rbitfld.long 0x0 10. "RXD_P,rxd_p data" "0,1" newline rbitfld.long 0x0 9. "RXD_N,rxd_n data" "0,1" bitfld.long 0x0 8. "VBIAS_SEL,vbais_sel" "0,1" bitfld.long 0x0 7. "TXEN,tx_en" "0,1" newline hexmask.long.byte 0x0 3.--6. 1. "TXDRV,tx_drv" bitfld.long 0x0 2. "TX_CM,tx_cm" "0,1" bitfld.long 0x0 1. "RTERM_EN,rterm enable" "0,1" newline bitfld.long 0x0 0. "BIAS_EN,bias enable" "0,1" line.long 0x4 "LVDS_CH1_PAD_SET,lvds ch1 pad setting" rbitfld.long 0x4 11. "RXDA,rxda data" "0,1" rbitfld.long 0x4 10. "RXD_P,rxd_p data" "0,1" newline rbitfld.long 0x4 9. "RXD_N,rxd_n data" "0,1" bitfld.long 0x4 8. "VBIAS_SEL,vbais_sel" "0,1" bitfld.long 0x4 7. "TXEN,tx_en" "0,1" newline hexmask.long.byte 0x4 3.--6. 1. "TXDRV,tx_drv" bitfld.long 0x4 2. "TX_CM,tx_cm" "0,1" bitfld.long 0x4 1. "RTERM_EN,rterm enable" "0,1" newline bitfld.long 0x4 0. "BIAS_EN,bias enable" "0,1" line.long 0x8 "LVDS_CH1_PAD_SET,lvds ch1 pad setting" rbitfld.long 0x8 11. "RXDA,rxda data" "0,1" rbitfld.long 0x8 10. "RXD_P,rxd_p data" "0,1" newline rbitfld.long 0x8 9. "RXD_N,rxd_n data" "0,1" bitfld.long 0x8 8. "VBIAS_SEL,vbais_sel" "0,1" bitfld.long 0x8 7. "TXEN,tx_en" "0,1" newline hexmask.long.byte 0x8 3.--6. 1. "TXDRV,tx_drv" bitfld.long 0x8 2. "TX_CM,tx_cm" "0,1" bitfld.long 0x8 1. "RTERM_EN,rterm enable" "0,1" newline bitfld.long 0x8 0. "BIAS_EN,bias enable" "0,1" line.long 0xC "LVDS_CH1_PAD_SET,lvds ch1 pad setting" rbitfld.long 0xC 11. "RXDA,rxda data" "0,1" rbitfld.long 0xC 10. "RXD_P,rxd_p data" "0,1" newline rbitfld.long 0xC 9. "RXD_N,rxd_n data" "0,1" bitfld.long 0xC 8. "VBIAS_SEL,vbais_sel" "0,1" bitfld.long 0xC 7. "TXEN,tx_en" "0,1" newline hexmask.long.byte 0xC 3.--6. 1. "TXDRV,tx_drv" bitfld.long 0xC 2. "TX_CM,tx_cm" "0,1" bitfld.long 0xC 1. "RTERM_EN,rterm enable" "0,1" newline bitfld.long 0xC 0. "BIAS_EN,bias enable" "0,1" line.long 0x10 "LVDS_CH1_PAD_SET,lvds ch1 pad setting" rbitfld.long 0x10 11. "RXDA,rxda data" "0,1" rbitfld.long 0x10 10. "RXD_P,rxd_p data" "0,1" newline rbitfld.long 0x10 9. "RXD_N,rxd_n data" "0,1" bitfld.long 0x10 8. "VBIAS_SEL,vbais_sel" "0,1" bitfld.long 0x10 7. "TXEN,tx_en" "0,1" newline hexmask.long.byte 0x10 3.--6. 1. "TXDRV,tx_drv" bitfld.long 0x10 2. "TX_CM,tx_cm" "0,1" bitfld.long 0x10 1. "RTERM_EN,rterm enable" "0,1" newline bitfld.long 0x10 0. "BIAS_EN,bias enable" "0,1" group.long 0x30000++0xB line.long 0x0 "LVDS_CH_2,lvds ch2 channel" bitfld.long 0x0 31. "ENABLE,enable" "0,1" bitfld.long 0x0 23.--24. "MUX,mux : the source of data come from 00:: lvds pair0 odd 01:lvds pair0 even 01:lvds pair1 odd 11:lvds pair1 even" "lvds pair0 odd,lvds pair1 odd,?,?" newline bitfld.long 0x0 22. "DUALODD,dual odd/even only when 30bit dualmode" "0,1" hexmask.long.word 0x0 7.--21. 1. "LANE_UPDATE,each lane update slot 2:0 clk lane 5:3 tx0 lane 8:6 tx1 lane 11:9 tx2 lane 14:12 tx3 lane" bitfld.long 0x0 5.--6. "FRAME_MASK,frame mask 00: 0 frame mask 01: 1 frame mask 10: 2 frame mask 11: 3 frame mask" "0,1,2,3" newline bitfld.long 0x0 4. "VSYNC_POL,vsync polarity" "0,1" bitfld.long 0x0 3. "FORMAT,map format 0:jeida 1:swpg" "jeida 1:swpg,?" bitfld.long 0x0 1.--2. "BPP,pixel format 00:18bit 01:24bit 10:30bit" "0,1,2,3" newline bitfld.long 0x0 0. "DUALMODE,dual mode" "0,1" line.long 0x4 "LVDS_CLOCK_2,lvds 2 clock div setting" hexmask.long.byte 0x4 11.--14. 1. "DIV_NUM_DBG,dbg div" hexmask.long.byte 0x4 7.--10. 1. "DIV_NUM_LVDS,lvds div" newline rbitfld.long 0x4 6. "GATING_ACK,gating_ack" "0,1" hexmask.long.byte 0x4 1.--5. 1. "GATING_EN,clock 0:clock disable 1:clock enable gating_en[0]:lvds_clk gating_en[1]:lvds_clk_x7 gating_en[2]:lvds_clk_x3.5 gating_en[3]:dbg_clk gating_en[4]:dsp_clk(from lvds_clk_x7 or lvds_clk_x3.5)" bitfld.long 0x4 0. "SRC_SEL,0: 7 clock 1: 3.5 clock" "0,1" line.long 0x8 "LVDS_CH2_PAD_COM_SET,lvds ch2 common setting" bitfld.long 0x8 14.--16. "LVDS_TRIM,lvds pad trim" "0,1,2,3,4,5,6,7" bitfld.long 0x8 13. "TEST_TXD_P,test_txd_p" "0,1" newline bitfld.long 0x8 12. "TEST_TXD_N,test_tx_n" "0,1" bitfld.long 0x8 11. "TEST_SCHMITT_EN,test_schmitt_en" "0,1" bitfld.long 0x8 10. "TEST_RXEN,test_rxen" "0,1" newline bitfld.long 0x8 9. "TEST_RXCM_EN,test_rxcm_en" "0,1" bitfld.long 0x8 8. "TEST_PULLDN,test_pulldn" "0,1" bitfld.long 0x8 7. "TEST_OEN_P,test_oen_p" "0,1" newline bitfld.long 0x8 6. "TEST_OEN_N,test_oen_n" "0,1" bitfld.long 0x8 5. "TEST_IEN_P,test_ien_p" "0,1" bitfld.long 0x8 4. "TEST_IEN_N,test_ien_n" "0,1" newline group.long 0x30010++0x13 line.long 0x0 "LVDS_CH2_PAD_SET,lvds ch2 pad setting" rbitfld.long 0x0 11. "RXDA,rxda data" "0,1" rbitfld.long 0x0 10. "RXD_P,rxd_p data" "0,1" newline rbitfld.long 0x0 9. "RXD_N,rxd_n data" "0,1" bitfld.long 0x0 8. "VBIAS_SEL,vbais_sel" "0,1" bitfld.long 0x0 7. "TXEN,tx_en" "0,1" newline hexmask.long.byte 0x0 3.--6. 1. "TXDRV,tx_drv" bitfld.long 0x0 2. "TX_CM,tx_cm" "0,1" bitfld.long 0x0 1. "RTERM_EN,rterm enable" "0,1" newline bitfld.long 0x0 0. "BIAS_EN,bias enable" "0,1" line.long 0x4 "LVDS_CH2_PAD_SET,lvds ch2 pad setting" rbitfld.long 0x4 11. "RXDA,rxda data" "0,1" rbitfld.long 0x4 10. "RXD_P,rxd_p data" "0,1" newline rbitfld.long 0x4 9. "RXD_N,rxd_n data" "0,1" bitfld.long 0x4 8. "VBIAS_SEL,vbais_sel" "0,1" bitfld.long 0x4 7. "TXEN,tx_en" "0,1" newline hexmask.long.byte 0x4 3.--6. 1. "TXDRV,tx_drv" bitfld.long 0x4 2. "TX_CM,tx_cm" "0,1" bitfld.long 0x4 1. "RTERM_EN,rterm enable" "0,1" newline bitfld.long 0x4 0. "BIAS_EN,bias enable" "0,1" line.long 0x8 "LVDS_CH2_PAD_SET,lvds ch2 pad setting" rbitfld.long 0x8 11. "RXDA,rxda data" "0,1" rbitfld.long 0x8 10. "RXD_P,rxd_p data" "0,1" newline rbitfld.long 0x8 9. "RXD_N,rxd_n data" "0,1" bitfld.long 0x8 8. "VBIAS_SEL,vbais_sel" "0,1" bitfld.long 0x8 7. "TXEN,tx_en" "0,1" newline hexmask.long.byte 0x8 3.--6. 1. "TXDRV,tx_drv" bitfld.long 0x8 2. "TX_CM,tx_cm" "0,1" bitfld.long 0x8 1. "RTERM_EN,rterm enable" "0,1" newline bitfld.long 0x8 0. "BIAS_EN,bias enable" "0,1" line.long 0xC "LVDS_CH2_PAD_SET,lvds ch2 pad setting" rbitfld.long 0xC 11. "RXDA,rxda data" "0,1" rbitfld.long 0xC 10. "RXD_P,rxd_p data" "0,1" newline rbitfld.long 0xC 9. "RXD_N,rxd_n data" "0,1" bitfld.long 0xC 8. "VBIAS_SEL,vbais_sel" "0,1" bitfld.long 0xC 7. "TXEN,tx_en" "0,1" newline hexmask.long.byte 0xC 3.--6. 1. "TXDRV,tx_drv" bitfld.long 0xC 2. "TX_CM,tx_cm" "0,1" bitfld.long 0xC 1. "RTERM_EN,rterm enable" "0,1" newline bitfld.long 0xC 0. "BIAS_EN,bias enable" "0,1" line.long 0x10 "LVDS_CH2_PAD_SET,lvds ch2 pad setting" rbitfld.long 0x10 11. "RXDA,rxda data" "0,1" rbitfld.long 0x10 10. "RXD_P,rxd_p data" "0,1" newline rbitfld.long 0x10 9. "RXD_N,rxd_n data" "0,1" bitfld.long 0x10 8. "VBIAS_SEL,vbais_sel" "0,1" bitfld.long 0x10 7. "TXEN,tx_en" "0,1" newline hexmask.long.byte 0x10 3.--6. 1. "TXDRV,tx_drv" bitfld.long 0x10 2. "TX_CM,tx_cm" "0,1" bitfld.long 0x10 1. "RTERM_EN,rterm enable" "0,1" newline bitfld.long 0x10 0. "BIAS_EN,bias enable" "0,1" group.long 0x40000++0xB line.long 0x0 "LVDS_CH_3,lvds ch3 channel" bitfld.long 0x0 31. "ENABLE,enable" "0,1" bitfld.long 0x0 23.--24. "MUX,mux : the source of data come from 00:: lvds pair0 odd 01:lvds pair0 even 01:lvds pair1 odd 11:lvds pair1 even" "lvds pair0 odd,lvds pair1 odd,?,?" newline bitfld.long 0x0 22. "DUALODD,dual odd/even only when 30bit dualmode" "0,1" hexmask.long.word 0x0 7.--21. 1. "LANE_UPDATE,each lane update slot 2:0 clk lane 5:3 tx0 lane 8:6 tx1 lane 11:9 tx2 lane 14:12 tx3 lane" bitfld.long 0x0 5.--6. "FRAME_MASK,frame mask 00: 0 frame mask 01: 1 frame mask 10: 2 frame mask 11: 3 frame mask" "0,1,2,3" newline bitfld.long 0x0 4. "VSYNC_POL,vsync polarity" "0,1" bitfld.long 0x0 3. "FORMAT,map format 0:jeida 1:swpg" "jeida 1:swpg,?" bitfld.long 0x0 1.--2. "BPP,pixel format 00:18bit 01:24bit 10:30bit" "0,1,2,3" newline bitfld.long 0x0 0. "DUALMODE,dual mode" "0,1" line.long 0x4 "LVDS_CLOCK_3,lvds 3 clock div setting" hexmask.long.byte 0x4 11.--14. 1. "DIV_NUM_DBG,dbg div" hexmask.long.byte 0x4 7.--10. 1. "DIV_NUM_LVDS,lvds div" newline rbitfld.long 0x4 6. "GATING_ACK,gating_ack" "0,1" hexmask.long.byte 0x4 1.--5. 1. "GATING_EN,clock 0:clock disable 1:clock enable gating_en[0]:lvds_clk gating_en[1]:lvds_clk_x7 gating_en[2]:lvds_clk_x3.5 gating_en[3]:dbg_clk gating_en[4]:dsp_clk(from lvds_clk_x7 or lvds_clk_x3.5)" bitfld.long 0x4 0. "SRC_SEL,0: 7 clock 1: 3.5 clock" "0,1" line.long 0x8 "LVDS_CH3_PAD_COM_SET,lvds ch3 common setting" bitfld.long 0x8 14.--16. "LVDS_TRIM,lvds pad trim" "0,1,2,3,4,5,6,7" bitfld.long 0x8 13. "TEST_TXD_P,test_txd_p" "0,1" newline bitfld.long 0x8 12. "TEST_TXD_N,test_tx_n" "0,1" bitfld.long 0x8 11. "TEST_SCHMITT_EN,test_schmitt_en" "0,1" bitfld.long 0x8 10. "TEST_RXEN,test_rxen" "0,1" newline bitfld.long 0x8 9. "TEST_RXCM_EN,test_rxcm_en" "0,1" bitfld.long 0x8 8. "TEST_PULLDN,test_pulldn" "0,1" bitfld.long 0x8 7. "TEST_OEN_P,test_oen_p" "0,1" newline bitfld.long 0x8 6. "TEST_OEN_N,test_oen_n" "0,1" bitfld.long 0x8 5. "TEST_IEN_P,test_ien_p" "0,1" bitfld.long 0x8 4. "TEST_IEN_N,test_ien_n" "0,1" newline group.long 0x40010++0x13 line.long 0x0 "LVDS_CH3_PAD_SET,lvds ch3 pad setting" rbitfld.long 0x0 11. "RXDA,rxda data" "0,1" rbitfld.long 0x0 10. "RXD_P,rxd_p data" "0,1" newline rbitfld.long 0x0 9. "RXD_N,rxd_n data" "0,1" bitfld.long 0x0 8. "VBIAS_SEL,vbais_sel" "0,1" bitfld.long 0x0 7. "TXEN,tx_en" "0,1" newline hexmask.long.byte 0x0 3.--6. 1. "TXDRV,tx_drv" bitfld.long 0x0 2. "TX_CM,tx_cm" "0,1" bitfld.long 0x0 1. "RTERM_EN,rterm enable" "0,1" newline bitfld.long 0x0 0. "BIAS_EN,bias enable" "0,1" line.long 0x4 "LVDS_CH3_PAD_SET,lvds ch3 pad setting" rbitfld.long 0x4 11. "RXDA,rxda data" "0,1" rbitfld.long 0x4 10. "RXD_P,rxd_p data" "0,1" newline rbitfld.long 0x4 9. "RXD_N,rxd_n data" "0,1" bitfld.long 0x4 8. "VBIAS_SEL,vbais_sel" "0,1" bitfld.long 0x4 7. "TXEN,tx_en" "0,1" newline hexmask.long.byte 0x4 3.--6. 1. "TXDRV,tx_drv" bitfld.long 0x4 2. "TX_CM,tx_cm" "0,1" bitfld.long 0x4 1. "RTERM_EN,rterm enable" "0,1" newline bitfld.long 0x4 0. "BIAS_EN,bias enable" "0,1" line.long 0x8 "LVDS_CH3_PAD_SET,lvds ch3 pad setting" rbitfld.long 0x8 11. "RXDA,rxda data" "0,1" rbitfld.long 0x8 10. "RXD_P,rxd_p data" "0,1" newline rbitfld.long 0x8 9. "RXD_N,rxd_n data" "0,1" bitfld.long 0x8 8. "VBIAS_SEL,vbais_sel" "0,1" bitfld.long 0x8 7. "TXEN,tx_en" "0,1" newline hexmask.long.byte 0x8 3.--6. 1. "TXDRV,tx_drv" bitfld.long 0x8 2. "TX_CM,tx_cm" "0,1" bitfld.long 0x8 1. "RTERM_EN,rterm enable" "0,1" newline bitfld.long 0x8 0. "BIAS_EN,bias enable" "0,1" line.long 0xC "LVDS_CH3_PAD_SET,lvds ch3 pad setting" rbitfld.long 0xC 11. "RXDA,rxda data" "0,1" rbitfld.long 0xC 10. "RXD_P,rxd_p data" "0,1" newline rbitfld.long 0xC 9. "RXD_N,rxd_n data" "0,1" bitfld.long 0xC 8. "VBIAS_SEL,vbais_sel" "0,1" bitfld.long 0xC 7. "TXEN,tx_en" "0,1" newline hexmask.long.byte 0xC 3.--6. 1. "TXDRV,tx_drv" bitfld.long 0xC 2. "TX_CM,tx_cm" "0,1" bitfld.long 0xC 1. "RTERM_EN,rterm enable" "0,1" newline bitfld.long 0xC 0. "BIAS_EN,bias enable" "0,1" line.long 0x10 "LVDS_CH3_PAD_SET,lvds ch3 pad setting" rbitfld.long 0x10 11. "RXDA,rxda data" "0,1" rbitfld.long 0x10 10. "RXD_P,rxd_p data" "0,1" newline rbitfld.long 0x10 9. "RXD_N,rxd_n data" "0,1" bitfld.long 0x10 8. "VBIAS_SEL,vbais_sel" "0,1" bitfld.long 0x10 7. "TXEN,tx_en" "0,1" newline hexmask.long.byte 0x10 3.--6. 1. "TXDRV,tx_drv" bitfld.long 0x10 2. "TX_CM,tx_cm" "0,1" bitfld.long 0x10 1. "RTERM_EN,rterm enable" "0,1" newline bitfld.long 0x10 0. "BIAS_EN,bias enable" "0,1" tree.end repeat.end endif tree.end tree "MAC (Memory Access Controller)" sif (CORENAME()=="CORTEXR5F") repeat 4. (increment 1. 1.) (list ad:0xF0BC0000 ad:0xF0BD0000 ad:0xF0BE0000 ad:0xF0BF0000) tree "MAC$1" base $2 group.long 0x0++0x17 line.long 0x0 "GLB_CTL,Global enable settings" bitfld.long 0x0 5. "DOM_CFG_LOCK,Lock write for DOM_CFG_MODE bit." "0,1" bitfld.long 0x0 4. "DOM_CFG_MODE,When enabled all the source setting can be configured by secure core which master ID is 1 if it is not locked. When disabled only resource manager can configure the permission of the resource." "0,1" bitfld.long 0x0 3. "PERCK_DIS_LOCK,Lock write for PERCK_DIS" "0,1" newline bitfld.long 0x0 2. "PERCK_DIS,All the permission check disable." "0,1" bitfld.long 0x0 1. "DOM_PRO_LOCK,Lock write for DOM_PRO_EN bit." "0,1" bitfld.long 0x0 0. "DOM_PRO_EN,When disabled no domain access permission check" "0,1" line.long 0x4 "RES_MGR,Assign Resource manager for global resource access control" bitfld.long 0x4 17. "MID_LOCK,Lock write for MID_EN and MID_LOW and MID_HIG registers." "0,1" bitfld.long 0x4 16. "MID_EN,Master ID check enable" "0,1" bitfld.long 0x4 15. "PRI_PER_LOCK,Lock write for PRI_PER and PRI_PER_EN" "0,1" newline bitfld.long 0x4 13.--14. "PRI_PER,Resource manager privileged access permission. bit0 for privileged access bit1 for user access" "0,1,2,3" bitfld.long 0x4 12. "PRI_PER_EN,Resource manager privileged access permission enable." "0,1" bitfld.long 0x4 11. "SEC_PER_LOCK,Lock for SEC_PER and SEC_PER_LOCK" "0,1" bitfld.long 0x4 9.--10. "SEC_PER,Resource manager secure access permission. bit 0 for secure access bit 1 for non-secure access" "0,1,2,3" newline bitfld.long 0x4 8. "SEC_PER_EN,Resource manager secure permission enable" "0,1" bitfld.long 0x4 7. "DID_LOCK,Lock write for DID_EN and DID" "0,1" hexmask.long.byte 0x4 3.--6. 1. "DID,Resource manager domain ID" bitfld.long 0x4 2. "DID_EN,Resource manager Domain ID enable" "0,1" newline bitfld.long 0x4 1. "RES_MGR_EN_LOCK,Lock for RES_MGR_EN" "0,1" bitfld.long 0x4 0. "RES_MGR_EN,Resource manager enable. When the bit is disable there is no resource manager." "0,1" line.long 0x8 "RES_MGR_MA0,Assign master 0~31 for resource manager" hexmask.long 0x8 0.--31. 1. "MID,Assign master 0~31 for resource manager" line.long 0xC "RES_MGR_MA1,Assign master 32~63 for resource manager" hexmask.long 0xC 0.--31. 1. "MID,Indicate if master 32~63 is resource manager." line.long 0x10 "RES_MGR_MA2,Assign master 64~95 for resource manager" hexmask.long 0x10 0.--31. 1. "MID,Indicate if master 64~95 is resource manager." line.long 0x14 "RES_MGR_MA3,Assign master 96~127 for resource manager" hexmask.long 0x14 0.--31. 1. "MID,Indicate if master 96~127 is resource manager." repeat 8. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 )(list 0x0 0x14 0x28 0x3C 0x50 0x64 0x78 0x8C ) group.long ($2+0x100)++0x3 line.long 0x0 "GRP_MGR_$1,Assign group manager 0" bitfld.long 0x0 17. "MID_LOCK,Lock write for MID_EN and MID_LOW and MID_HIG registers." "0,1" bitfld.long 0x0 16. "MID_EN,Master ID check enable" "0,1" bitfld.long 0x0 15. "PRI_PER_LOCK,Lock write for PRI_PER and PRI_PER_EN" "0,1" newline bitfld.long 0x0 13.--14. "PRI_PER,Group manager privileged access permission. bit0 for privileged access bit1 for user access" "0,1,2,3" bitfld.long 0x0 12. "PRI_PER_EN,Group manager privileged access permission enable." "0,1" bitfld.long 0x0 11. "SEC_PER_LOCK,Lock for SEC_PER and SEC_PER_LOCK" "0,1" bitfld.long 0x0 9.--10. "SEC_PER,Group manager secure access permission. bit 0 for secure access bit 1 for non-secure access" "0,1,2,3" newline bitfld.long 0x0 8. "SEC_PER_EN,Group manager secure permission enable" "0,1" bitfld.long 0x0 7. "DID_LOCK,Lock write for DID_EN and DID" "0,1" hexmask.long.byte 0x0 3.--6. 1. "DID,Group manager domain ID" bitfld.long 0x0 2. "DID_EN,Group manager Domain ID enable" "0,1" newline bitfld.long 0x0 1. "GRP_MGR_EN_LOCK,Lock write for GPR_MGR_EN" "0,1" bitfld.long 0x0 0. "GRP_MGR_EN,Group manager enable. When the bit is disable there is no resource manager." "0,1" repeat.end repeat 8. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 )(list 0x0 0x14 0x28 0x3C 0x50 0x64 0x78 0x8C ) group.long ($2+0x104)++0x3 line.long 0x0 "GRP_MGR_MA0_$1,Assign master 0~31 for group manager 0" hexmask.long 0x0 0.--31. 1. "MID,Assign master 0~31 for resource manager" repeat.end repeat 8. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 )(list 0x0 0x14 0x28 0x3C 0x50 0x64 0x78 0x8C ) group.long ($2+0x108)++0x3 line.long 0x0 "GRP_MGR_MA1_$1,Assign master 32~63 for group manager 0" hexmask.long 0x0 0.--31. 1. "MID,Indicate if master 32~63 is resource manager." repeat.end repeat 8. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 )(list 0x0 0x14 0x28 0x3C 0x50 0x64 0x78 0x8C ) group.long ($2+0x10C)++0x3 line.long 0x0 "GRP_MGR_MA2_$1,Assign master 64~95 for group manager 0" hexmask.long 0x0 0.--31. 1. "MID,Indicate if master 64~95 is resource manager." repeat.end repeat 8. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 )(list 0x0 0x14 0x28 0x3C 0x50 0x64 0x78 0x8C ) group.long ($2+0x110)++0x3 line.long 0x0 "GRP_MGR_MA3_$1,Assign master 96~127 for group manager 0" hexmask.long 0x0 0.--31. 1. "MID,Indicate if master 96~127 is resource manager." repeat.end group.long 0x200++0x3 line.long 0x0 "DOM_GID_0,Indicate which group domain 0 belong to" bitfld.long 0x0 3. "LOCK,Lock write for GID" "0,1" bitfld.long 0x0 0.--2. "GID,Group ID" "0,1,2,3,4,5,6,7" repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x18 0x30 0x48 0x60 0x78 0x90 0xA8 0xC0 0xD8 0xF0 0x108 0x120 0x138 0x150 0x168 ) group.long ($2+0x204)++0x3 line.long 0x0 "DOM_OWN_$1,Assign owner for function domain 0." bitfld.long 0x0 17. "MID_LOCK,Lock write for MID_EN and MID_LOW and MID_HIG registers." "0,1" bitfld.long 0x0 16. "MID_EN,Master ID check enable" "0,1" bitfld.long 0x0 15. "PRI_PER_LOCK,Lock write for PRI_PER and PRI_PER_EN" "0,1" newline bitfld.long 0x0 13.--14. "PRI_PER,Group manager privileged access permission. bit0 for privileged access bit1 for user access" "0,1,2,3" bitfld.long 0x0 12. "PRI_PER_EN,Group manager privileged access permission enable." "0,1" bitfld.long 0x0 11. "SEC_PER_LOCK,Lock for SEC_PER and SEC_PER_LOCK" "0,1" bitfld.long 0x0 9.--10. "SEC_PER,Domain owner secure access permission. bit 0 for secure access bit 1 for non-secure access" "0,1,2,3" newline bitfld.long 0x0 8. "SEC_PER_EN,Domain owner secure permission enable" "0,1" bitfld.long 0x0 1. "DOM_OWN_EN_LOCK,Lock for DOM_OWN_EN" "0,1" bitfld.long 0x0 0. "DOM_OWN_EN,Domain owner enable. When the bit is disable there is no domain owner." "0,1" repeat.end repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x18 0x30 0x48 0x60 0x78 0x90 0xA8 0xC0 0xD8 0xF0 0x108 0x120 0x138 0x150 0x168 ) group.long ($2+0x208)++0x3 line.long 0x0 "DOM_OWN_MA0_$1,Assign master 0~31 for domain owner 0" hexmask.long 0x0 0.--31. 1. "MID,Assign master 0~31 for resource manager" repeat.end repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x18 0x30 0x48 0x60 0x78 0x90 0xA8 0xC0 0xD8 0xF0 0x108 0x120 0x138 0x150 0x168 ) group.long ($2+0x20C)++0x3 line.long 0x0 "DOM_OWN_MA1_$1,Assign master 32~63 for domain owner 0" hexmask.long 0x0 0.--31. 1. "MID,Indicate if master 32~63 is resource manager." repeat.end repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x18 0x30 0x48 0x60 0x78 0x90 0xA8 0xC0 0xD8 0xF0 0x108 0x120 0x138 0x150 0x168 ) group.long ($2+0x210)++0x3 line.long 0x0 "DOM_OWN_MA2_$1,Assign master 64~95 for domain owner 0" hexmask.long 0x0 0.--31. 1. "MID,Indicate if master 64~95 is resource manager." repeat.end repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x18 0x30 0x48 0x60 0x78 0x90 0xA8 0xC0 0xD8 0xF0 0x108 0x120 0x138 0x150 0x168 ) group.long ($2+0x214)++0x3 line.long 0x0 "DOM_OWN_MA3_$1,Assign master 96~127 for domain owner 0" hexmask.long 0x0 0.--31. 1. "MID,Indicate if master 96~127 is resource manager." repeat.end group.long 0x218++0x3 line.long 0x0 "DOM_GID_1,Indicate which group domain 1 belong to" bitfld.long 0x0 3. "LOCK,Lock write for GID" "0,1" bitfld.long 0x0 0.--2. "GID,Group ID" "0,1,2,3,4,5,6,7" group.long 0x230++0x3 line.long 0x0 "DOM_GID_2,Indicate which group domain 2 belong to" bitfld.long 0x0 3. "LOCK,Lock write for GID" "0,1" bitfld.long 0x0 0.--2. "GID,Group ID" "0,1,2,3,4,5,6,7" group.long 0x248++0x3 line.long 0x0 "DOM_GID_3,Indicate which group domain 3 belong to" bitfld.long 0x0 3. "LOCK,Lock write for GID" "0,1" bitfld.long 0x0 0.--2. "GID,Group ID" "0,1,2,3,4,5,6,7" group.long 0x260++0x3 line.long 0x0 "DOM_GID_4,Indicate which group domain 4 belong to" bitfld.long 0x0 3. "LOCK,Lock write for GID" "0,1" bitfld.long 0x0 0.--2. "GID,Group ID" "0,1,2,3,4,5,6,7" group.long 0x278++0x3 line.long 0x0 "DOM_GID_5,Indicate which group domain 5 belong to" bitfld.long 0x0 3. "LOCK,Lock write for GID" "0,1" bitfld.long 0x0 0.--2. "GID,Group ID" "0,1,2,3,4,5,6,7" group.long 0x290++0x3 line.long 0x0 "DOM_GID_6,Indicate which group domain 6 belong to" bitfld.long 0x0 3. "LOCK,Lock write for GID" "0,1" bitfld.long 0x0 0.--2. "GID,Group ID" "0,1,2,3,4,5,6,7" group.long 0x2A8++0x3 line.long 0x0 "DOM_GID_7,Indicate which group domain 7 belong to" bitfld.long 0x0 3. "LOCK,Lock write for GID" "0,1" bitfld.long 0x0 0.--2. "GID,Group ID" "0,1,2,3,4,5,6,7" group.long 0x2C0++0x3 line.long 0x0 "DOM_GID_8,Indicate which group domain 8 belong to" bitfld.long 0x0 3. "LOCK,Lock write for GID" "0,1" bitfld.long 0x0 0.--2. "GID,Group ID" "0,1,2,3,4,5,6,7" group.long 0x2D8++0x3 line.long 0x0 "DOM_GID_9,Indicate which group domain 9 belong to" bitfld.long 0x0 3. "LOCK,Lock write for GID" "0,1" bitfld.long 0x0 0.--2. "GID,Group ID" "0,1,2,3,4,5,6,7" group.long 0x2F0++0x3 line.long 0x0 "DOM_GID_10,Indicate which group domain 10 belong to" bitfld.long 0x0 3. "LOCK,Lock write for GID" "0,1" bitfld.long 0x0 0.--2. "GID,Group ID" "0,1,2,3,4,5,6,7" group.long 0x308++0x3 line.long 0x0 "DOM_GID_11,Indicate which group domain 11 belong to" bitfld.long 0x0 3. "LOCK,Lock write for GID" "0,1" bitfld.long 0x0 0.--2. "GID,Group ID" "0,1,2,3,4,5,6,7" group.long 0x320++0x3 line.long 0x0 "DOM_GID_12,Indicate which group domain 12 belong to" bitfld.long 0x0 3. "LOCK,Lock write for GID" "0,1" bitfld.long 0x0 0.--2. "GID,Group ID" "0,1,2,3,4,5,6,7" group.long 0x338++0x3 line.long 0x0 "DOM_GID_13,Indicate which group domain 13 belong to" bitfld.long 0x0 3. "LOCK,Lock write for GID" "0,1" bitfld.long 0x0 0.--2. "GID,Group ID" "0,1,2,3,4,5,6,7" group.long 0x350++0x3 line.long 0x0 "DOM_GID_14,Indicate which group domain 14 belong to" bitfld.long 0x0 3. "LOCK,Lock write for GID" "0,1" bitfld.long 0x0 0.--2. "GID,Group ID" "0,1,2,3,4,5,6,7" group.long 0x368++0x3 line.long 0x0 "DOM_GID_15,Indicate which group domain 15 belong to" bitfld.long 0x0 3. "LOCK,Lock write for GID" "0,1" bitfld.long 0x0 0.--2. "GID,Group ID" "0,1,2,3,4,5,6,7" repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x8 0x10 0x18 0x20 0x28 0x30 0x38 0x40 0x48 0x50 0x58 0x60 0x68 0x70 0x78 ) group.long ($2+0x400)++0x3 line.long 0x0 "MDA_$1,Assign domian for Master 0." bitfld.long 0x0 31. "LOCK,Lock write for DID" "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for master" repeat.end repeat 16. (list 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1A 0x1B 0x1C 0x1D 0x1E 0x1F )(list 0x80 0x88 0x90 0x98 0xA0 0xA8 0xB0 0xB8 0xC0 0xC8 0xD0 0xD8 0xE0 0xE8 0xF0 0xF8 ) group.long ($2+0x400)++0x3 line.long 0x0 "MDA_$1,Assign domian for Master 0." bitfld.long 0x0 31. "LOCK,Lock write for DID" "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for master" repeat.end repeat 16. (list 0x20 0x21 0x22 0x23 0x24 0x25 0x26 0x27 0x28 0x29 0x2A 0x2B 0x2C 0x2D 0x2E 0x2F )(list 0x100 0x108 0x110 0x118 0x120 0x128 0x130 0x138 0x140 0x148 0x150 0x158 0x160 0x168 0x170 0x178 ) group.long ($2+0x400)++0x3 line.long 0x0 "MDA_$1,Assign domian for Master 0." bitfld.long 0x0 31. "LOCK,Lock write for DID" "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for master" repeat.end repeat 16. (list 0x30 0x31 0x32 0x33 0x34 0x35 0x36 0x37 0x38 0x39 0x3A 0x3B 0x3C 0x3D 0x3E 0x3F )(list 0x180 0x188 0x190 0x198 0x1A0 0x1A8 0x1B0 0x1B8 0x1C0 0x1C8 0x1D0 0x1D8 0x1E0 0x1E8 0x1F0 0x1F8 ) group.long ($2+0x400)++0x3 line.long 0x0 "MDA_$1,Assign domian for Master 0." bitfld.long 0x0 31. "LOCK,Lock write for DID" "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for master" repeat.end repeat 16. (list 0x40 0x41 0x42 0x43 0x44 0x45 0x46 0x47 0x48 0x49 0x4A 0x4B 0x4C 0x4D 0x4E 0x4F )(list 0x200 0x208 0x210 0x218 0x220 0x228 0x230 0x238 0x240 0x248 0x250 0x258 0x260 0x268 0x270 0x278 ) group.long ($2+0x400)++0x3 line.long 0x0 "MDA_$1,Assign domian for Master 0." bitfld.long 0x0 31. "LOCK,Lock write for DID" "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for master" repeat.end repeat 16. (list 0x50 0x51 0x52 0x53 0x54 0x55 0x56 0x57 0x58 0x59 0x5A 0x5B 0x5C 0x5D 0x5E 0x5F )(list 0x280 0x288 0x290 0x298 0x2A0 0x2A8 0x2B0 0x2B8 0x2C0 0x2C8 0x2D0 0x2D8 0x2E0 0x2E8 0x2F0 0x2F8 ) group.long ($2+0x400)++0x3 line.long 0x0 "MDA_$1,Assign domian for Master 0." bitfld.long 0x0 31. "LOCK,Lock write for DID" "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for master" repeat.end repeat 16. (list 0x60 0x61 0x62 0x63 0x64 0x65 0x66 0x67 0x68 0x69 0x6A 0x6B 0x6C 0x6D 0x6E 0x6F )(list 0x300 0x308 0x310 0x318 0x320 0x328 0x330 0x338 0x340 0x348 0x350 0x358 0x360 0x368 0x370 0x378 ) group.long ($2+0x400)++0x3 line.long 0x0 "MDA_$1,Assign domian for Master 0." bitfld.long 0x0 31. "LOCK,Lock write for DID" "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for master" repeat.end repeat 16. (list 0x70 0x71 0x72 0x73 0x74 0x75 0x76 0x77 0x78 0x79 0x7A 0x7B 0x7C 0x7D 0x7E 0x7F )(list 0x380 0x388 0x390 0x398 0x3A0 0x3A8 0x3B0 0x3B8 0x3C0 0x3C8 0x3D0 0x3D8 0x3E0 0x3E8 0x3F0 0x3F8 ) group.long ($2+0x400)++0x3 line.long 0x0 "MDA_$1,Assign domian for Master 0." bitfld.long 0x0 31. "LOCK,Lock write for DID" "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for master" repeat.end repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x8 0x10 0x18 0x20 0x28 0x30 0x38 0x40 0x48 0x50 0x58 0x60 0x68 0x70 0x78 ) group.long ($2+0x404)++0x3 line.long 0x0 "MAA_$1,Assign stream ID . secure/privileged attribute for master 0." bitfld.long 0x0 14. "SRID_LOCK,lock write for SRID_OV_EN and SRID bits" "0,1" hexmask.long.byte 0x0 6.--13. 1. "SRID,Only bit7 and bit6 are used as RID in SOC." bitfld.long 0x0 5. "PRI_LOCK,Lock write for PRI_OV_EN and PRI bits." "0,1" newline bitfld.long 0x0 4. "PRI_OV_EN,Master privileged signal override enable" "0,1" bitfld.long 0x0 3. "PRI,0 : user access 1 : Privileged access" "user access,Privileged access" bitfld.long 0x0 2. "SEC_LOCK,Lock write for SEC_OV_EN and SEC bits." "0,1" bitfld.long 0x0 1. "SEC_OV_EN,Master secure signal override enable" "0,1" newline bitfld.long 0x0 0. "SEC,0:Secure access 1: Non-secure access" "Secure access,Non-secure access" repeat.end repeat 16. (list 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1A 0x1B 0x1C 0x1D 0x1E 0x1F )(list 0x80 0x88 0x90 0x98 0xA0 0xA8 0xB0 0xB8 0xC0 0xC8 0xD0 0xD8 0xE0 0xE8 0xF0 0xF8 ) group.long ($2+0x404)++0x3 line.long 0x0 "MAA_$1,Assign stream ID . secure/privileged attribute for master 0." bitfld.long 0x0 14. "SRID_LOCK,lock write for SRID_OV_EN and SRID bits" "0,1" hexmask.long.byte 0x0 6.--13. 1. "SRID,Only bit7 and bit6 are used as RID in SOC." bitfld.long 0x0 5. "PRI_LOCK,Lock write for PRI_OV_EN and PRI bits." "0,1" newline bitfld.long 0x0 4. "PRI_OV_EN,Master privileged signal override enable" "0,1" bitfld.long 0x0 3. "PRI,0 : user access 1 : Privileged access" "user access,Privileged access" bitfld.long 0x0 2. "SEC_LOCK,Lock write for SEC_OV_EN and SEC bits." "0,1" bitfld.long 0x0 1. "SEC_OV_EN,Master secure signal override enable" "0,1" newline bitfld.long 0x0 0. "SEC,0:Secure access 1: Non-secure access" "Secure access,Non-secure access" repeat.end repeat 16. (list 0x20 0x21 0x22 0x23 0x24 0x25 0x26 0x27 0x28 0x29 0x2A 0x2B 0x2C 0x2D 0x2E 0x2F )(list 0x100 0x108 0x110 0x118 0x120 0x128 0x130 0x138 0x140 0x148 0x150 0x158 0x160 0x168 0x170 0x178 ) group.long ($2+0x404)++0x3 line.long 0x0 "MAA_$1,Assign stream ID . secure/privileged attribute for master 0." bitfld.long 0x0 14. "SRID_LOCK,lock write for SRID_OV_EN and SRID bits" "0,1" hexmask.long.byte 0x0 6.--13. 1. "SRID,Only bit7 and bit6 are used as RID in SOC." bitfld.long 0x0 5. "PRI_LOCK,Lock write for PRI_OV_EN and PRI bits." "0,1" newline bitfld.long 0x0 4. "PRI_OV_EN,Master privileged signal override enable" "0,1" bitfld.long 0x0 3. "PRI,0 : user access 1 : Privileged access" "user access,Privileged access" bitfld.long 0x0 2. "SEC_LOCK,Lock write for SEC_OV_EN and SEC bits." "0,1" bitfld.long 0x0 1. "SEC_OV_EN,Master secure signal override enable" "0,1" newline bitfld.long 0x0 0. "SEC,0:Secure access 1: Non-secure access" "Secure access,Non-secure access" repeat.end repeat 16. (list 0x30 0x31 0x32 0x33 0x34 0x35 0x36 0x37 0x38 0x39 0x3A 0x3B 0x3C 0x3D 0x3E 0x3F )(list 0x180 0x188 0x190 0x198 0x1A0 0x1A8 0x1B0 0x1B8 0x1C0 0x1C8 0x1D0 0x1D8 0x1E0 0x1E8 0x1F0 0x1F8 ) group.long ($2+0x404)++0x3 line.long 0x0 "MAA_$1,Assign stream ID . secure/privileged attribute for master 0." bitfld.long 0x0 14. "SRID_LOCK,lock write for SRID_OV_EN and SRID bits" "0,1" hexmask.long.byte 0x0 6.--13. 1. "SRID,Only bit7 and bit6 are used as RID in SOC." bitfld.long 0x0 5. "PRI_LOCK,Lock write for PRI_OV_EN and PRI bits." "0,1" newline bitfld.long 0x0 4. "PRI_OV_EN,Master privileged signal override enable" "0,1" bitfld.long 0x0 3. "PRI,0 : user access 1 : Privileged access" "user access,Privileged access" bitfld.long 0x0 2. "SEC_LOCK,Lock write for SEC_OV_EN and SEC bits." "0,1" bitfld.long 0x0 1. "SEC_OV_EN,Master secure signal override enable" "0,1" newline bitfld.long 0x0 0. "SEC,0:Secure access 1: Non-secure access" "Secure access,Non-secure access" repeat.end repeat 16. (list 0x40 0x41 0x42 0x43 0x44 0x45 0x46 0x47 0x48 0x49 0x4A 0x4B 0x4C 0x4D 0x4E 0x4F )(list 0x200 0x208 0x210 0x218 0x220 0x228 0x230 0x238 0x240 0x248 0x250 0x258 0x260 0x268 0x270 0x278 ) group.long ($2+0x404)++0x3 line.long 0x0 "MAA_$1,Assign stream ID . secure/privileged attribute for master 0." bitfld.long 0x0 14. "SRID_LOCK,lock write for SRID_OV_EN and SRID bits" "0,1" hexmask.long.byte 0x0 6.--13. 1. "SRID,Only bit7 and bit6 are used as RID in SOC." bitfld.long 0x0 5. "PRI_LOCK,Lock write for PRI_OV_EN and PRI bits." "0,1" newline bitfld.long 0x0 4. "PRI_OV_EN,Master privileged signal override enable" "0,1" bitfld.long 0x0 3. "PRI,0 : user access 1 : Privileged access" "user access,Privileged access" bitfld.long 0x0 2. "SEC_LOCK,Lock write for SEC_OV_EN and SEC bits." "0,1" bitfld.long 0x0 1. "SEC_OV_EN,Master secure signal override enable" "0,1" newline bitfld.long 0x0 0. "SEC,0:Secure access 1: Non-secure access" "Secure access,Non-secure access" repeat.end repeat 16. (list 0x50 0x51 0x52 0x53 0x54 0x55 0x56 0x57 0x58 0x59 0x5A 0x5B 0x5C 0x5D 0x5E 0x5F )(list 0x280 0x288 0x290 0x298 0x2A0 0x2A8 0x2B0 0x2B8 0x2C0 0x2C8 0x2D0 0x2D8 0x2E0 0x2E8 0x2F0 0x2F8 ) group.long ($2+0x404)++0x3 line.long 0x0 "MAA_$1,Assign stream ID . secure/privileged attribute for master 0." bitfld.long 0x0 14. "SRID_LOCK,lock write for SRID_OV_EN and SRID bits" "0,1" hexmask.long.byte 0x0 6.--13. 1. "SRID,Only bit7 and bit6 are used as RID in SOC." bitfld.long 0x0 5. "PRI_LOCK,Lock write for PRI_OV_EN and PRI bits." "0,1" newline bitfld.long 0x0 4. "PRI_OV_EN,Master privileged signal override enable" "0,1" bitfld.long 0x0 3. "PRI,0 : user access 1 : Privileged access" "user access,Privileged access" bitfld.long 0x0 2. "SEC_LOCK,Lock write for SEC_OV_EN and SEC bits." "0,1" bitfld.long 0x0 1. "SEC_OV_EN,Master secure signal override enable" "0,1" newline bitfld.long 0x0 0. "SEC,0:Secure access 1: Non-secure access" "Secure access,Non-secure access" repeat.end repeat 16. (list 0x60 0x61 0x62 0x63 0x64 0x65 0x66 0x67 0x68 0x69 0x6A 0x6B 0x6C 0x6D 0x6E 0x6F )(list 0x300 0x308 0x310 0x318 0x320 0x328 0x330 0x338 0x340 0x348 0x350 0x358 0x360 0x368 0x370 0x378 ) group.long ($2+0x404)++0x3 line.long 0x0 "MAA_$1,Assign stream ID . secure/privileged attribute for master 0." bitfld.long 0x0 14. "SRID_LOCK,lock write for SRID_OV_EN and SRID bits" "0,1" hexmask.long.byte 0x0 6.--13. 1. "SRID,Only bit7 and bit6 are used as RID in SOC." bitfld.long 0x0 5. "PRI_LOCK,Lock write for PRI_OV_EN and PRI bits." "0,1" newline bitfld.long 0x0 4. "PRI_OV_EN,Master privileged signal override enable" "0,1" bitfld.long 0x0 3. "PRI,0 : user access 1 : Privileged access" "user access,Privileged access" bitfld.long 0x0 2. "SEC_LOCK,Lock write for SEC_OV_EN and SEC bits." "0,1" bitfld.long 0x0 1. "SEC_OV_EN,Master secure signal override enable" "0,1" newline bitfld.long 0x0 0. "SEC,0:Secure access 1: Non-secure access" "Secure access,Non-secure access" repeat.end repeat 16. (list 0x70 0x71 0x72 0x73 0x74 0x75 0x76 0x77 0x78 0x79 0x7A 0x7B 0x7C 0x7D 0x7E 0x7F )(list 0x380 0x388 0x390 0x398 0x3A0 0x3A8 0x3B0 0x3B8 0x3C0 0x3C8 0x3D0 0x3D8 0x3E0 0x3E8 0x3F0 0x3F8 ) group.long ($2+0x404)++0x3 line.long 0x0 "MAA_$1,Assign stream ID . secure/privileged attribute for master 0." bitfld.long 0x0 14. "SRID_LOCK,lock write for SRID_OV_EN and SRID bits" "0,1" hexmask.long.byte 0x0 6.--13. 1. "SRID,Only bit7 and bit6 are used as RID in SOC." bitfld.long 0x0 5. "PRI_LOCK,Lock write for PRI_OV_EN and PRI bits." "0,1" newline bitfld.long 0x0 4. "PRI_OV_EN,Master privileged signal override enable" "0,1" bitfld.long 0x0 3. "PRI,0 : user access 1 : Privileged access" "user access,Privileged access" bitfld.long 0x0 2. "SEC_LOCK,Lock write for SEC_OV_EN and SEC bits." "0,1" bitfld.long 0x0 1. "SEC_OV_EN,Master secure signal override enable" "0,1" newline bitfld.long 0x0 0. "SEC,0:Secure access 1: Non-secure access" "Secure access,Non-secure access" repeat.end tree.end repeat.end elif (CORENAME()=="CORTEXA55") repeat 4. (increment 1. 1.) (list ad:0x30BC0000 ad:0x30BD0000 ad:0x30BE0000 ad:0x30BF0000) tree "MAC$1" base $2 group.long 0x0++0x17 line.long 0x0 "GLB_CTL,Global enable settings" bitfld.long 0x0 5. "DOM_CFG_LOCK,Lock write for DOM_CFG_MODE bit." "0,1" bitfld.long 0x0 4. "DOM_CFG_MODE,When enabled all the source setting can be configured by secure core which master ID is 1 if it is not locked. When disabled only resource manager can configure the permission of the resource." "0,1" bitfld.long 0x0 3. "PERCK_DIS_LOCK,Lock write for PERCK_DIS" "0,1" newline bitfld.long 0x0 2. "PERCK_DIS,All the permission check disable." "0,1" bitfld.long 0x0 1. "DOM_PRO_LOCK,Lock write for DOM_PRO_EN bit." "0,1" bitfld.long 0x0 0. "DOM_PRO_EN,When disabled no domain access permission check" "0,1" line.long 0x4 "RES_MGR,Assign Resource manager for global resource access control" bitfld.long 0x4 17. "MID_LOCK,Lock write for MID_EN and MID_LOW and MID_HIG registers." "0,1" bitfld.long 0x4 16. "MID_EN,Master ID check enable" "0,1" bitfld.long 0x4 15. "PRI_PER_LOCK,Lock write for PRI_PER and PRI_PER_EN" "0,1" newline bitfld.long 0x4 13.--14. "PRI_PER,Resource manager privileged access permission. bit0 for privileged access bit1 for user access" "0,1,2,3" bitfld.long 0x4 12. "PRI_PER_EN,Resource manager privileged access permission enable." "0,1" bitfld.long 0x4 11. "SEC_PER_LOCK,Lock for SEC_PER and SEC_PER_LOCK" "0,1" bitfld.long 0x4 9.--10. "SEC_PER,Resource manager secure access permission. bit 0 for secure access bit 1 for non-secure access" "0,1,2,3" newline bitfld.long 0x4 8. "SEC_PER_EN,Resource manager secure permission enable" "0,1" bitfld.long 0x4 7. "DID_LOCK,Lock write for DID_EN and DID" "0,1" hexmask.long.byte 0x4 3.--6. 1. "DID,Resource manager domain ID" bitfld.long 0x4 2. "DID_EN,Resource manager Domain ID enable" "0,1" newline bitfld.long 0x4 1. "RES_MGR_EN_LOCK,Lock for RES_MGR_EN" "0,1" bitfld.long 0x4 0. "RES_MGR_EN,Resource manager enable. When the bit is disable there is no resource manager." "0,1" line.long 0x8 "RES_MGR_MA0,Assign master 0~31 for resource manager" hexmask.long 0x8 0.--31. 1. "MID,Assign master 0~31 for resource manager" line.long 0xC "RES_MGR_MA1,Assign master 32~63 for resource manager" hexmask.long 0xC 0.--31. 1. "MID,Indicate if master 32~63 is resource manager." line.long 0x10 "RES_MGR_MA2,Assign master 64~95 for resource manager" hexmask.long 0x10 0.--31. 1. "MID,Indicate if master 64~95 is resource manager." line.long 0x14 "RES_MGR_MA3,Assign master 96~127 for resource manager" hexmask.long 0x14 0.--31. 1. "MID,Indicate if master 96~127 is resource manager." repeat 8. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 )(list 0x0 0x14 0x28 0x3C 0x50 0x64 0x78 0x8C ) group.long ($2+0x100)++0x3 line.long 0x0 "GRP_MGR_$1,Assign group manager 0" bitfld.long 0x0 17. "MID_LOCK,Lock write for MID_EN and MID_LOW and MID_HIG registers." "0,1" bitfld.long 0x0 16. "MID_EN,Master ID check enable" "0,1" bitfld.long 0x0 15. "PRI_PER_LOCK,Lock write for PRI_PER and PRI_PER_EN" "0,1" newline bitfld.long 0x0 13.--14. "PRI_PER,Group manager privileged access permission. bit0 for privileged access bit1 for user access" "0,1,2,3" bitfld.long 0x0 12. "PRI_PER_EN,Group manager privileged access permission enable." "0,1" bitfld.long 0x0 11. "SEC_PER_LOCK,Lock for SEC_PER and SEC_PER_LOCK" "0,1" bitfld.long 0x0 9.--10. "SEC_PER,Group manager secure access permission. bit 0 for secure access bit 1 for non-secure access" "0,1,2,3" newline bitfld.long 0x0 8. "SEC_PER_EN,Group manager secure permission enable" "0,1" bitfld.long 0x0 7. "DID_LOCK,Lock write for DID_EN and DID" "0,1" hexmask.long.byte 0x0 3.--6. 1. "DID,Group manager domain ID" bitfld.long 0x0 2. "DID_EN,Group manager Domain ID enable" "0,1" newline bitfld.long 0x0 1. "GRP_MGR_EN_LOCK,Lock write for GPR_MGR_EN" "0,1" bitfld.long 0x0 0. "GRP_MGR_EN,Group manager enable. When the bit is disable there is no resource manager." "0,1" repeat.end repeat 8. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 )(list 0x0 0x14 0x28 0x3C 0x50 0x64 0x78 0x8C ) group.long ($2+0x104)++0x3 line.long 0x0 "GRP_MGR_MA0_$1,Assign master 0~31 for group manager 0" hexmask.long 0x0 0.--31. 1. "MID,Assign master 0~31 for resource manager" repeat.end repeat 8. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 )(list 0x0 0x14 0x28 0x3C 0x50 0x64 0x78 0x8C ) group.long ($2+0x108)++0x3 line.long 0x0 "GRP_MGR_MA1_$1,Assign master 32~63 for group manager 0" hexmask.long 0x0 0.--31. 1. "MID,Indicate if master 32~63 is resource manager." repeat.end repeat 8. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 )(list 0x0 0x14 0x28 0x3C 0x50 0x64 0x78 0x8C ) group.long ($2+0x10C)++0x3 line.long 0x0 "GRP_MGR_MA2_$1,Assign master 64~95 for group manager 0" hexmask.long 0x0 0.--31. 1. "MID,Indicate if master 64~95 is resource manager." repeat.end repeat 8. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 )(list 0x0 0x14 0x28 0x3C 0x50 0x64 0x78 0x8C ) group.long ($2+0x110)++0x3 line.long 0x0 "GRP_MGR_MA3_$1,Assign master 96~127 for group manager 0" hexmask.long 0x0 0.--31. 1. "MID,Indicate if master 96~127 is resource manager." repeat.end group.long 0x200++0x3 line.long 0x0 "DOM_GID_0,Indicate which group domain 0 belong to" bitfld.long 0x0 3. "LOCK,Lock write for GID" "0,1" bitfld.long 0x0 0.--2. "GID,Group ID" "0,1,2,3,4,5,6,7" repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x18 0x30 0x48 0x60 0x78 0x90 0xA8 0xC0 0xD8 0xF0 0x108 0x120 0x138 0x150 0x168 ) group.long ($2+0x204)++0x3 line.long 0x0 "DOM_OWN_$1,Assign owner for function domain 0." bitfld.long 0x0 17. "MID_LOCK,Lock write for MID_EN and MID_LOW and MID_HIG registers." "0,1" bitfld.long 0x0 16. "MID_EN,Master ID check enable" "0,1" bitfld.long 0x0 15. "PRI_PER_LOCK,Lock write for PRI_PER and PRI_PER_EN" "0,1" newline bitfld.long 0x0 13.--14. "PRI_PER,Group manager privileged access permission. bit0 for privileged access bit1 for user access" "0,1,2,3" bitfld.long 0x0 12. "PRI_PER_EN,Group manager privileged access permission enable." "0,1" bitfld.long 0x0 11. "SEC_PER_LOCK,Lock for SEC_PER and SEC_PER_LOCK" "0,1" bitfld.long 0x0 9.--10. "SEC_PER,Domain owner secure access permission. bit 0 for secure access bit 1 for non-secure access" "0,1,2,3" newline bitfld.long 0x0 8. "SEC_PER_EN,Domain owner secure permission enable" "0,1" bitfld.long 0x0 1. "DOM_OWN_EN_LOCK,Lock for DOM_OWN_EN" "0,1" bitfld.long 0x0 0. "DOM_OWN_EN,Domain owner enable. When the bit is disable there is no domain owner." "0,1" repeat.end repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x18 0x30 0x48 0x60 0x78 0x90 0xA8 0xC0 0xD8 0xF0 0x108 0x120 0x138 0x150 0x168 ) group.long ($2+0x208)++0x3 line.long 0x0 "DOM_OWN_MA0_$1,Assign master 0~31 for domain owner 0" hexmask.long 0x0 0.--31. 1. "MID,Assign master 0~31 for resource manager" repeat.end repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x18 0x30 0x48 0x60 0x78 0x90 0xA8 0xC0 0xD8 0xF0 0x108 0x120 0x138 0x150 0x168 ) group.long ($2+0x20C)++0x3 line.long 0x0 "DOM_OWN_MA1_$1,Assign master 32~63 for domain owner 0" hexmask.long 0x0 0.--31. 1. "MID,Indicate if master 32~63 is resource manager." repeat.end repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x18 0x30 0x48 0x60 0x78 0x90 0xA8 0xC0 0xD8 0xF0 0x108 0x120 0x138 0x150 0x168 ) group.long ($2+0x210)++0x3 line.long 0x0 "DOM_OWN_MA2_$1,Assign master 64~95 for domain owner 0" hexmask.long 0x0 0.--31. 1. "MID,Indicate if master 64~95 is resource manager." repeat.end repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x18 0x30 0x48 0x60 0x78 0x90 0xA8 0xC0 0xD8 0xF0 0x108 0x120 0x138 0x150 0x168 ) group.long ($2+0x214)++0x3 line.long 0x0 "DOM_OWN_MA3_$1,Assign master 96~127 for domain owner 0" hexmask.long 0x0 0.--31. 1. "MID,Indicate if master 96~127 is resource manager." repeat.end group.long 0x218++0x3 line.long 0x0 "DOM_GID_1,Indicate which group domain 1 belong to" bitfld.long 0x0 3. "LOCK,Lock write for GID" "0,1" bitfld.long 0x0 0.--2. "GID,Group ID" "0,1,2,3,4,5,6,7" group.long 0x230++0x3 line.long 0x0 "DOM_GID_2,Indicate which group domain 2 belong to" bitfld.long 0x0 3. "LOCK,Lock write for GID" "0,1" bitfld.long 0x0 0.--2. "GID,Group ID" "0,1,2,3,4,5,6,7" group.long 0x248++0x3 line.long 0x0 "DOM_GID_3,Indicate which group domain 3 belong to" bitfld.long 0x0 3. "LOCK,Lock write for GID" "0,1" bitfld.long 0x0 0.--2. "GID,Group ID" "0,1,2,3,4,5,6,7" group.long 0x260++0x3 line.long 0x0 "DOM_GID_4,Indicate which group domain 4 belong to" bitfld.long 0x0 3. "LOCK,Lock write for GID" "0,1" bitfld.long 0x0 0.--2. "GID,Group ID" "0,1,2,3,4,5,6,7" group.long 0x278++0x3 line.long 0x0 "DOM_GID_5,Indicate which group domain 5 belong to" bitfld.long 0x0 3. "LOCK,Lock write for GID" "0,1" bitfld.long 0x0 0.--2. "GID,Group ID" "0,1,2,3,4,5,6,7" group.long 0x290++0x3 line.long 0x0 "DOM_GID_6,Indicate which group domain 6 belong to" bitfld.long 0x0 3. "LOCK,Lock write for GID" "0,1" bitfld.long 0x0 0.--2. "GID,Group ID" "0,1,2,3,4,5,6,7" group.long 0x2A8++0x3 line.long 0x0 "DOM_GID_7,Indicate which group domain 7 belong to" bitfld.long 0x0 3. "LOCK,Lock write for GID" "0,1" bitfld.long 0x0 0.--2. "GID,Group ID" "0,1,2,3,4,5,6,7" group.long 0x2C0++0x3 line.long 0x0 "DOM_GID_8,Indicate which group domain 8 belong to" bitfld.long 0x0 3. "LOCK,Lock write for GID" "0,1" bitfld.long 0x0 0.--2. "GID,Group ID" "0,1,2,3,4,5,6,7" group.long 0x2D8++0x3 line.long 0x0 "DOM_GID_9,Indicate which group domain 9 belong to" bitfld.long 0x0 3. "LOCK,Lock write for GID" "0,1" bitfld.long 0x0 0.--2. "GID,Group ID" "0,1,2,3,4,5,6,7" group.long 0x2F0++0x3 line.long 0x0 "DOM_GID_10,Indicate which group domain 10 belong to" bitfld.long 0x0 3. "LOCK,Lock write for GID" "0,1" bitfld.long 0x0 0.--2. "GID,Group ID" "0,1,2,3,4,5,6,7" group.long 0x308++0x3 line.long 0x0 "DOM_GID_11,Indicate which group domain 11 belong to" bitfld.long 0x0 3. "LOCK,Lock write for GID" "0,1" bitfld.long 0x0 0.--2. "GID,Group ID" "0,1,2,3,4,5,6,7" group.long 0x320++0x3 line.long 0x0 "DOM_GID_12,Indicate which group domain 12 belong to" bitfld.long 0x0 3. "LOCK,Lock write for GID" "0,1" bitfld.long 0x0 0.--2. "GID,Group ID" "0,1,2,3,4,5,6,7" group.long 0x338++0x3 line.long 0x0 "DOM_GID_13,Indicate which group domain 13 belong to" bitfld.long 0x0 3. "LOCK,Lock write for GID" "0,1" bitfld.long 0x0 0.--2. "GID,Group ID" "0,1,2,3,4,5,6,7" group.long 0x350++0x3 line.long 0x0 "DOM_GID_14,Indicate which group domain 14 belong to" bitfld.long 0x0 3. "LOCK,Lock write for GID" "0,1" bitfld.long 0x0 0.--2. "GID,Group ID" "0,1,2,3,4,5,6,7" group.long 0x368++0x3 line.long 0x0 "DOM_GID_15,Indicate which group domain 15 belong to" bitfld.long 0x0 3. "LOCK,Lock write for GID" "0,1" bitfld.long 0x0 0.--2. "GID,Group ID" "0,1,2,3,4,5,6,7" repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x8 0x10 0x18 0x20 0x28 0x30 0x38 0x40 0x48 0x50 0x58 0x60 0x68 0x70 0x78 ) group.long ($2+0x400)++0x3 line.long 0x0 "MDA_$1,Assign domian for Master 0." bitfld.long 0x0 31. "LOCK,Lock write for DID" "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for master" repeat.end repeat 16. (list 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1A 0x1B 0x1C 0x1D 0x1E 0x1F )(list 0x80 0x88 0x90 0x98 0xA0 0xA8 0xB0 0xB8 0xC0 0xC8 0xD0 0xD8 0xE0 0xE8 0xF0 0xF8 ) group.long ($2+0x400)++0x3 line.long 0x0 "MDA_$1,Assign domian for Master 0." bitfld.long 0x0 31. "LOCK,Lock write for DID" "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for master" repeat.end repeat 16. (list 0x20 0x21 0x22 0x23 0x24 0x25 0x26 0x27 0x28 0x29 0x2A 0x2B 0x2C 0x2D 0x2E 0x2F )(list 0x100 0x108 0x110 0x118 0x120 0x128 0x130 0x138 0x140 0x148 0x150 0x158 0x160 0x168 0x170 0x178 ) group.long ($2+0x400)++0x3 line.long 0x0 "MDA_$1,Assign domian for Master 0." bitfld.long 0x0 31. "LOCK,Lock write for DID" "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for master" repeat.end repeat 16. (list 0x30 0x31 0x32 0x33 0x34 0x35 0x36 0x37 0x38 0x39 0x3A 0x3B 0x3C 0x3D 0x3E 0x3F )(list 0x180 0x188 0x190 0x198 0x1A0 0x1A8 0x1B0 0x1B8 0x1C0 0x1C8 0x1D0 0x1D8 0x1E0 0x1E8 0x1F0 0x1F8 ) group.long ($2+0x400)++0x3 line.long 0x0 "MDA_$1,Assign domian for Master 0." bitfld.long 0x0 31. "LOCK,Lock write for DID" "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for master" repeat.end repeat 16. (list 0x40 0x41 0x42 0x43 0x44 0x45 0x46 0x47 0x48 0x49 0x4A 0x4B 0x4C 0x4D 0x4E 0x4F )(list 0x200 0x208 0x210 0x218 0x220 0x228 0x230 0x238 0x240 0x248 0x250 0x258 0x260 0x268 0x270 0x278 ) group.long ($2+0x400)++0x3 line.long 0x0 "MDA_$1,Assign domian for Master 0." bitfld.long 0x0 31. "LOCK,Lock write for DID" "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for master" repeat.end repeat 16. (list 0x50 0x51 0x52 0x53 0x54 0x55 0x56 0x57 0x58 0x59 0x5A 0x5B 0x5C 0x5D 0x5E 0x5F )(list 0x280 0x288 0x290 0x298 0x2A0 0x2A8 0x2B0 0x2B8 0x2C0 0x2C8 0x2D0 0x2D8 0x2E0 0x2E8 0x2F0 0x2F8 ) group.long ($2+0x400)++0x3 line.long 0x0 "MDA_$1,Assign domian for Master 0." bitfld.long 0x0 31. "LOCK,Lock write for DID" "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for master" repeat.end repeat 16. (list 0x60 0x61 0x62 0x63 0x64 0x65 0x66 0x67 0x68 0x69 0x6A 0x6B 0x6C 0x6D 0x6E 0x6F )(list 0x300 0x308 0x310 0x318 0x320 0x328 0x330 0x338 0x340 0x348 0x350 0x358 0x360 0x368 0x370 0x378 ) group.long ($2+0x400)++0x3 line.long 0x0 "MDA_$1,Assign domian for Master 0." bitfld.long 0x0 31. "LOCK,Lock write for DID" "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for master" repeat.end repeat 16. (list 0x70 0x71 0x72 0x73 0x74 0x75 0x76 0x77 0x78 0x79 0x7A 0x7B 0x7C 0x7D 0x7E 0x7F )(list 0x380 0x388 0x390 0x398 0x3A0 0x3A8 0x3B0 0x3B8 0x3C0 0x3C8 0x3D0 0x3D8 0x3E0 0x3E8 0x3F0 0x3F8 ) group.long ($2+0x400)++0x3 line.long 0x0 "MDA_$1,Assign domian for Master 0." bitfld.long 0x0 31. "LOCK,Lock write for DID" "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for master" repeat.end repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x8 0x10 0x18 0x20 0x28 0x30 0x38 0x40 0x48 0x50 0x58 0x60 0x68 0x70 0x78 ) group.long ($2+0x404)++0x3 line.long 0x0 "MAA_$1,Assign stream ID . secure/privileged attribute for master 0." bitfld.long 0x0 14. "SRID_LOCK,lock write for SRID_OV_EN and SRID bits" "0,1" hexmask.long.byte 0x0 6.--13. 1. "SRID,Only bit7 and bit6 are used as RID in SOC." bitfld.long 0x0 5. "PRI_LOCK,Lock write for PRI_OV_EN and PRI bits." "0,1" newline bitfld.long 0x0 4. "PRI_OV_EN,Master privileged signal override enable" "0,1" bitfld.long 0x0 3. "PRI,0 : user access 1 : Privileged access" "user access,Privileged access" bitfld.long 0x0 2. "SEC_LOCK,Lock write for SEC_OV_EN and SEC bits." "0,1" bitfld.long 0x0 1. "SEC_OV_EN,Master secure signal override enable" "0,1" newline bitfld.long 0x0 0. "SEC,0:Secure access 1: Non-secure access" "Secure access,Non-secure access" repeat.end repeat 16. (list 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1A 0x1B 0x1C 0x1D 0x1E 0x1F )(list 0x80 0x88 0x90 0x98 0xA0 0xA8 0xB0 0xB8 0xC0 0xC8 0xD0 0xD8 0xE0 0xE8 0xF0 0xF8 ) group.long ($2+0x404)++0x3 line.long 0x0 "MAA_$1,Assign stream ID . secure/privileged attribute for master 0." bitfld.long 0x0 14. "SRID_LOCK,lock write for SRID_OV_EN and SRID bits" "0,1" hexmask.long.byte 0x0 6.--13. 1. "SRID,Only bit7 and bit6 are used as RID in SOC." bitfld.long 0x0 5. "PRI_LOCK,Lock write for PRI_OV_EN and PRI bits." "0,1" newline bitfld.long 0x0 4. "PRI_OV_EN,Master privileged signal override enable" "0,1" bitfld.long 0x0 3. "PRI,0 : user access 1 : Privileged access" "user access,Privileged access" bitfld.long 0x0 2. "SEC_LOCK,Lock write for SEC_OV_EN and SEC bits." "0,1" bitfld.long 0x0 1. "SEC_OV_EN,Master secure signal override enable" "0,1" newline bitfld.long 0x0 0. "SEC,0:Secure access 1: Non-secure access" "Secure access,Non-secure access" repeat.end repeat 16. (list 0x20 0x21 0x22 0x23 0x24 0x25 0x26 0x27 0x28 0x29 0x2A 0x2B 0x2C 0x2D 0x2E 0x2F )(list 0x100 0x108 0x110 0x118 0x120 0x128 0x130 0x138 0x140 0x148 0x150 0x158 0x160 0x168 0x170 0x178 ) group.long ($2+0x404)++0x3 line.long 0x0 "MAA_$1,Assign stream ID . secure/privileged attribute for master 0." bitfld.long 0x0 14. "SRID_LOCK,lock write for SRID_OV_EN and SRID bits" "0,1" hexmask.long.byte 0x0 6.--13. 1. "SRID,Only bit7 and bit6 are used as RID in SOC." bitfld.long 0x0 5. "PRI_LOCK,Lock write for PRI_OV_EN and PRI bits." "0,1" newline bitfld.long 0x0 4. "PRI_OV_EN,Master privileged signal override enable" "0,1" bitfld.long 0x0 3. "PRI,0 : user access 1 : Privileged access" "user access,Privileged access" bitfld.long 0x0 2. "SEC_LOCK,Lock write for SEC_OV_EN and SEC bits." "0,1" bitfld.long 0x0 1. "SEC_OV_EN,Master secure signal override enable" "0,1" newline bitfld.long 0x0 0. "SEC,0:Secure access 1: Non-secure access" "Secure access,Non-secure access" repeat.end repeat 16. (list 0x30 0x31 0x32 0x33 0x34 0x35 0x36 0x37 0x38 0x39 0x3A 0x3B 0x3C 0x3D 0x3E 0x3F )(list 0x180 0x188 0x190 0x198 0x1A0 0x1A8 0x1B0 0x1B8 0x1C0 0x1C8 0x1D0 0x1D8 0x1E0 0x1E8 0x1F0 0x1F8 ) group.long ($2+0x404)++0x3 line.long 0x0 "MAA_$1,Assign stream ID . secure/privileged attribute for master 0." bitfld.long 0x0 14. "SRID_LOCK,lock write for SRID_OV_EN and SRID bits" "0,1" hexmask.long.byte 0x0 6.--13. 1. "SRID,Only bit7 and bit6 are used as RID in SOC." bitfld.long 0x0 5. "PRI_LOCK,Lock write for PRI_OV_EN and PRI bits." "0,1" newline bitfld.long 0x0 4. "PRI_OV_EN,Master privileged signal override enable" "0,1" bitfld.long 0x0 3. "PRI,0 : user access 1 : Privileged access" "user access,Privileged access" bitfld.long 0x0 2. "SEC_LOCK,Lock write for SEC_OV_EN and SEC bits." "0,1" bitfld.long 0x0 1. "SEC_OV_EN,Master secure signal override enable" "0,1" newline bitfld.long 0x0 0. "SEC,0:Secure access 1: Non-secure access" "Secure access,Non-secure access" repeat.end repeat 16. (list 0x40 0x41 0x42 0x43 0x44 0x45 0x46 0x47 0x48 0x49 0x4A 0x4B 0x4C 0x4D 0x4E 0x4F )(list 0x200 0x208 0x210 0x218 0x220 0x228 0x230 0x238 0x240 0x248 0x250 0x258 0x260 0x268 0x270 0x278 ) group.long ($2+0x404)++0x3 line.long 0x0 "MAA_$1,Assign stream ID . secure/privileged attribute for master 0." bitfld.long 0x0 14. "SRID_LOCK,lock write for SRID_OV_EN and SRID bits" "0,1" hexmask.long.byte 0x0 6.--13. 1. "SRID,Only bit7 and bit6 are used as RID in SOC." bitfld.long 0x0 5. "PRI_LOCK,Lock write for PRI_OV_EN and PRI bits." "0,1" newline bitfld.long 0x0 4. "PRI_OV_EN,Master privileged signal override enable" "0,1" bitfld.long 0x0 3. "PRI,0 : user access 1 : Privileged access" "user access,Privileged access" bitfld.long 0x0 2. "SEC_LOCK,Lock write for SEC_OV_EN and SEC bits." "0,1" bitfld.long 0x0 1. "SEC_OV_EN,Master secure signal override enable" "0,1" newline bitfld.long 0x0 0. "SEC,0:Secure access 1: Non-secure access" "Secure access,Non-secure access" repeat.end repeat 16. (list 0x50 0x51 0x52 0x53 0x54 0x55 0x56 0x57 0x58 0x59 0x5A 0x5B 0x5C 0x5D 0x5E 0x5F )(list 0x280 0x288 0x290 0x298 0x2A0 0x2A8 0x2B0 0x2B8 0x2C0 0x2C8 0x2D0 0x2D8 0x2E0 0x2E8 0x2F0 0x2F8 ) group.long ($2+0x404)++0x3 line.long 0x0 "MAA_$1,Assign stream ID . secure/privileged attribute for master 0." bitfld.long 0x0 14. "SRID_LOCK,lock write for SRID_OV_EN and SRID bits" "0,1" hexmask.long.byte 0x0 6.--13. 1. "SRID,Only bit7 and bit6 are used as RID in SOC." bitfld.long 0x0 5. "PRI_LOCK,Lock write for PRI_OV_EN and PRI bits." "0,1" newline bitfld.long 0x0 4. "PRI_OV_EN,Master privileged signal override enable" "0,1" bitfld.long 0x0 3. "PRI,0 : user access 1 : Privileged access" "user access,Privileged access" bitfld.long 0x0 2. "SEC_LOCK,Lock write for SEC_OV_EN and SEC bits." "0,1" bitfld.long 0x0 1. "SEC_OV_EN,Master secure signal override enable" "0,1" newline bitfld.long 0x0 0. "SEC,0:Secure access 1: Non-secure access" "Secure access,Non-secure access" repeat.end repeat 16. (list 0x60 0x61 0x62 0x63 0x64 0x65 0x66 0x67 0x68 0x69 0x6A 0x6B 0x6C 0x6D 0x6E 0x6F )(list 0x300 0x308 0x310 0x318 0x320 0x328 0x330 0x338 0x340 0x348 0x350 0x358 0x360 0x368 0x370 0x378 ) group.long ($2+0x404)++0x3 line.long 0x0 "MAA_$1,Assign stream ID . secure/privileged attribute for master 0." bitfld.long 0x0 14. "SRID_LOCK,lock write for SRID_OV_EN and SRID bits" "0,1" hexmask.long.byte 0x0 6.--13. 1. "SRID,Only bit7 and bit6 are used as RID in SOC." bitfld.long 0x0 5. "PRI_LOCK,Lock write for PRI_OV_EN and PRI bits." "0,1" newline bitfld.long 0x0 4. "PRI_OV_EN,Master privileged signal override enable" "0,1" bitfld.long 0x0 3. "PRI,0 : user access 1 : Privileged access" "user access,Privileged access" bitfld.long 0x0 2. "SEC_LOCK,Lock write for SEC_OV_EN and SEC bits." "0,1" bitfld.long 0x0 1. "SEC_OV_EN,Master secure signal override enable" "0,1" newline bitfld.long 0x0 0. "SEC,0:Secure access 1: Non-secure access" "Secure access,Non-secure access" repeat.end repeat 16. (list 0x70 0x71 0x72 0x73 0x74 0x75 0x76 0x77 0x78 0x79 0x7A 0x7B 0x7C 0x7D 0x7E 0x7F )(list 0x380 0x388 0x390 0x398 0x3A0 0x3A8 0x3B0 0x3B8 0x3C0 0x3C8 0x3D0 0x3D8 0x3E0 0x3E8 0x3F0 0x3F8 ) group.long ($2+0x404)++0x3 line.long 0x0 "MAA_$1,Assign stream ID . secure/privileged attribute for master 0." bitfld.long 0x0 14. "SRID_LOCK,lock write for SRID_OV_EN and SRID bits" "0,1" hexmask.long.byte 0x0 6.--13. 1. "SRID,Only bit7 and bit6 are used as RID in SOC." bitfld.long 0x0 5. "PRI_LOCK,Lock write for PRI_OV_EN and PRI bits." "0,1" newline bitfld.long 0x0 4. "PRI_OV_EN,Master privileged signal override enable" "0,1" bitfld.long 0x0 3. "PRI,0 : user access 1 : Privileged access" "user access,Privileged access" bitfld.long 0x0 2. "SEC_LOCK,Lock write for SEC_OV_EN and SEC bits." "0,1" bitfld.long 0x0 1. "SEC_OV_EN,Master secure signal override enable" "0,1" newline bitfld.long 0x0 0. "SEC,0:Secure access 1: Non-secure access" "Secure access,Non-secure access" repeat.end tree.end repeat.end endif tree.end tree "MAILBOX (MAILBOX)" sif (CORENAME()=="CORTEXR5F") base ad:0xF4040000 group.long 0x0++0xB line.long 0x0 "TMH0,Transmitter Message Header(TMH0). 32 bit register. each processor has a TMH0" hexmask.long.byte 0x0 24.--31. 1. "MID,Message Index (MID[7:0]) as MU only support 4 outstanding messages to each one of those other processers only MID[1:0] is used for physical message index decoding" hexmask.long.byte 0x0 16.--23. 1. "MDP,Message Destination Processer (MDP) of this message. E.g. when MDP[7:0] = 10000001 this message is meant to be received by processer-0 and processer-7. To unify programming model processer which initiates this message is also encoded in MAB[7:0].." hexmask.long.byte 0x0 12.--15. 1. "MBM,message buffer mask(MBM) each bit of MBM represents the MB which are used for transferring this message. e.g. MBM[3:0] = b0101 means that the message is stored in MB0 and MB2" bitfld.long 0x0 11. "TXUSE_MB,whether this messge buffer(MB) are used in this message" "0,1" newline hexmask.long.word 0x0 0.--10. 1. "TXMES_LEN,Message length(ML) 1x2 to 2048 x 2 Byte" line.long 0x4 "TMH1,Transmitter Message Header(TMH1). 32 bit register. each processor has a TMH1" hexmask.long 0x4 0.--31. 1. "TMH1,side-band message information which is user defined.Useful in short messaging which doesnot need large message buffer" line.long 0x8 "TMH2,Transmitter Message Header(TMH2). 32 bit register. each processor has a TMH2" hexmask.long 0x8 0.--31. 1. "TMH2,side-band message information which is user defined.Useful in short messaging which doesnot need large message buffer" repeat 4. (list 0x0 0x1 0x2 0x3 )(list 0x0 0x4 0x8 0xC ) group.long ($2+0xC)++0x3 line.long 0x0 "TMC$1,Transmitter Message Control(TMC): 32bit register each processor has 4 TMC" hexmask.long.byte 0x0 16.--23. 1. "TMC0_WAK_REQ,self-cleared. When set to 1 wakeup interrupt to corresponding processer is initiated" bitfld.long 0x0 8. "TMC0_MSG_CANCEL,Self cleared controls message interrupt to other processer. E.g. when set to 1 message interrupt to processer as described in MDP and MID are cleared. In the meantime MB allocated for this message is free" "0,1" newline bitfld.long 0x0 0. "TMC0_MSG_SEND,When Write 1 the messaging interrupts to other processers are asserted e.g. the message are sent. when read the status will be cleared when message are received by all destination processors." "0,1" repeat.end rgroup.long 0x1C++0x3 line.long 0x0 "TMS,32-bit register each processor has a TMS" hexmask.long 0x0 0.--31. 1. "TMS,TMS[31:0] Message In Transfer status MIT[M][N] where M <8 N<4.Each bit represents message-N which transfer from processer-M is sent out.This field is set by message initiator.Clear by message receiver by writing 1 to transfer acknowledge (TACK).." group.long 0x20++0x3 line.long 0x0 "TPWES,Transmitter Proccessor wakeup event status(TPWES). 32 bit register each processor has a TPWES" hexmask.long.byte 0x0 0.--7. 1. "TPWES,wakeup status. TPWES[M] = 1 means that related processer-M Will be cleared by destination processer reset even or writing 1 to WACK register." wgroup.long 0x24++0x3 line.long 0x0 "RMC,32-bit register. each processor has a RMC" hexmask.long 0x0 0.--31. 1. "RMC,Message acknowledgement TACK[M][N] where M<8 N<4. Self-cleared when sets 1to TACK[M][N] message-N interrupts from processer-M are cleared." group.long 0x28++0x7 line.long 0x0 "RWC,32bit register.each processor has a RWC" hexmask.long.byte 0x0 8.--15. 1. "WEM,processer Wakeup Event Mask (WEM). When set wakeup event from corresponding processer is masked" bitfld.long 0x0 0. "WACK,RWC processer Wakeup Acknowledgement(WACK). Self-cleared when set all interrupt from other processers are cleared" "0,1" line.long 0x4 "CPU0_MSG0_RMH0,receiver message header0(RMH0) . each processor has (NumberOfProcessor)x4 RMH0" hexmask.long.byte 0x4 24.--31. 1. "CPU0_MSG0_RMH0,RMH[31:26] could be used to transfer the message RMH[25:24] is actually the message index" rbitfld.long 0x4 16. "CPU0_MSG0_VLD,message valid(MV) of this message e.g. when MV = 1 this message is meant to be received by the processor" "0,1" hexmask.long.byte 0x4 12.--15. 1. "CPU0_MSG0_MBM,Message Buffer Mask(MBM) each bit of MBM[3:0] represents the MB which are used for transferring this message. e.g. MBM[3:0] = 4b0101 means that the message is stored in MB0 and MB2" newline rbitfld.long 0x4 11. "CPU0_MSG0_USE_MB,whether this Message Buffer (MB) are used in this message" "0,1" hexmask.long.word 0x4 0.--10. 1. "CPU0_MSG0_LEN,Message Length (ML) 1x2 to 2048x2Byte" rgroup.long 0x30++0x7 line.long 0x0 "CPU0_MSG0_RMH1,Receiver Message header1(RMH1): 32 bit register each processor has (NumberOfProcessor)x4 RMH1" hexmask.long 0x0 0.--31. 1. "CPU0_MSG0_RMH1,side-band message information which is user defined.Useful in short messaging which doesnot need large message buffer" line.long 0x4 "CPU0_MSG0_RMH2,Receiver Message header2(RMH2): 32 bit register each processor has (NumberOfProcessor)x4 RMH2" hexmask.long 0x4 0.--31. 1. "CPU0_MSG0_RMH2,side-band message information which is user defined.Useful in short messaging which doesnot need large message buffer" group.long 0x38++0x3 line.long 0x0 "CPU0_MSG1_RMH0,receiver message header0(RMH0) . each processor has (NumberOfProcessor)x4 RMH0" hexmask.long.byte 0x0 24.--31. 1. "CPU0_MSG1_RMH0,RMH[31:26] could be used to transfer the message RMH[25:24] is actually the message index" rbitfld.long 0x0 16. "CPU0_MSG1_VLD,message valid(MV) of this message e.g. when MV = 1 this message is meant to be received by the processor" "0,1" hexmask.long.byte 0x0 12.--15. 1. "CPU0_MSG1_MBM,Message Buffer Mask(MBM) each bit of MBM[3:0] represents the MB which are used for transferring this message. e.g. MBM[3:0] = 4b0101 means that the message is stored in MB0 and MB2" newline rbitfld.long 0x0 11. "CPU0_MSG1_USE_MB,whether this Message Buffer (MB) are used in this message" "0,1" hexmask.long.word 0x0 0.--10. 1. "CPU0_MSG1_LEN,Message Length (ML) 1x2 to 2048x2Byte" rgroup.long 0x3C++0x7 line.long 0x0 "CPU0_MSG1_RMH1,Receiver Message header1(RMH1): 32 bit register each processor has (NumberOfProcessor)x4 RMH1" hexmask.long 0x0 0.--31. 1. "CPU0_MSG1_RMH1,side-band message information which is user defined.Useful in short messaging which doesnot need large message buffer" line.long 0x4 "CPU0_MSG1_RMH2,Receiver Message header2(RMH2): 32 bit register each processor has (NumberOfProcessor)x4 RMH2" hexmask.long 0x4 0.--31. 1. "CPU0_MSG1_RMH2,side-band message information which is user defined.Useful in short messaging which doesnot need large message buffer" group.long 0x44++0x3 line.long 0x0 "CPU0_MSG2_RMH0,receiver message header0(RMH0) . each processor has (NumberOfProcessor)x4 RMH0" hexmask.long.byte 0x0 24.--31. 1. "CPU0_MSG2_RMH0,RMH[31:26] could be used to transfer the message RMH[25:24] is actually the message index" rbitfld.long 0x0 16. "CPU0_MSG2_VLD,message valid(MV) of this message e.g. when MV = 1 this message is meant to be received by the processor" "0,1" hexmask.long.byte 0x0 12.--15. 1. "CPU0_MSG2_MBM,Message Buffer Mask(MBM) each bit of MBM[3:0] represents the MB which are used for transferring this message. e.g. MBM[3:0] = 4b0101 means that the message is stored in MB0 and MB2" newline rbitfld.long 0x0 11. "CPU0_MSG2_USE_MB,whether this Message Buffer (MB) are used in this message" "0,1" hexmask.long.word 0x0 0.--10. 1. "CPU0_MSG2_LEN,Message Length (ML) 1x2 to 2048x2Byte" rgroup.long 0x48++0x7 line.long 0x0 "CPU0_MSG2_RMH1,Receiver Message header1(RMH1): 32 bit register each processor has (NumberOfProcessor)x4 RMH1" hexmask.long 0x0 0.--31. 1. "CPU0_MSG2_RMH1,side-band message information which is user defined.Useful in short messaging which doesnot need large message buffer" line.long 0x4 "CPU0_MSG2_RMH2,Receiver Message header2(RMH2): 32 bit register each processor has (NumberOfProcessor)x4 RMH2" hexmask.long 0x4 0.--31. 1. "CPU0_MSG2_RMH2,side-band message information which is user defined.Useful in short messaging which doesnot need large message buffer" group.long 0x50++0x3 line.long 0x0 "CPU0_MSG3_RMH0,receiver message header0(RMH0) . each processor has (NumberOfProcessor)x4 RMH0" hexmask.long.byte 0x0 24.--31. 1. "CPU0_MSG3_RMH0,RMH[31:26] could be used to transfer the message RMH[25:24] is actually the message index" rbitfld.long 0x0 16. "CPU0_MSG3_VLD,message valid(MV) of this message e.g. when MV = 1 this message is meant to be received by the processor" "0,1" hexmask.long.byte 0x0 12.--15. 1. "CPU0_MSG3_MBM,Message Buffer Mask(MBM) each bit of MBM[3:0] represents the MB which are used for transferring this message. e.g. MBM[3:0] = 4b0101 means that the message is stored in MB0 and MB2" newline rbitfld.long 0x0 11. "CPU0_MSG3_USE_MB,whether this Message Buffer (MB) are used in this message" "0,1" hexmask.long.word 0x0 0.--10. 1. "CPU0_MSG3_LEN,Message Length (ML) 1x2 to 2048x2Byte" rgroup.long 0x54++0x7 line.long 0x0 "CPU0_MSG3_RMH1,Receiver Message header1(RMH1): 32 bit register each processor has (NumberOfProcessor)x4 RMH1" hexmask.long 0x0 0.--31. 1. "CPU0_MSG3_RMH1,side-band message information which is user defined.Useful in short messaging which doesnot need large message buffer" line.long 0x4 "CPU0_MSG3_RMH2,Receiver Message header2(RMH2): 32 bit register each processor has (NumberOfProcessor)x4 RMH2" hexmask.long 0x4 0.--31. 1. "CPU0_MSG3_RMH2,side-band message information which is user defined.Useful in short messaging which doesnot need large message buffer" group.long 0x5C++0x3 line.long 0x0 "CPU1_MSG0_RMH0,receiver message header0(RMH0) . each processor has (NumberOfProcessor)x4 RMH0" hexmask.long.byte 0x0 24.--31. 1. "CPU1_MSG0_RMH0,RMH[31:26] could be used to transfer the message RMH[25:24] is actually the message index" rbitfld.long 0x0 16. "CPU1_MSG0_VLD,message valid(MV) of this message e.g. when MV = 1 this message is meant to be received by the processor" "0,1" hexmask.long.byte 0x0 12.--15. 1. "CPU1_MSG0_MBM,Message Buffer Mask(MBM) each bit of MBM[3:0] represents the MB which are used for transferring this message. e.g. MBM[3:0] = 4b0101 means that the message is stored in MB0 and MB2" newline rbitfld.long 0x0 11. "CPU1_MSG0_USE_MB,whether this Message Buffer (MB) are used in this message" "0,1" hexmask.long.word 0x0 0.--10. 1. "CPU1_MSG0_LEN,Message Length (ML) 1x2 to 2048x2Byte" rgroup.long 0x60++0x7 line.long 0x0 "CPU1_MSG0_RMH1,Receiver Message header1(RMH1): 32 bit register each processor has (NumberOfProcessor)x4 RMH1" hexmask.long 0x0 0.--31. 1. "CPU1_MSG0_RMH1,side-band message information which is user defined.Useful in short messaging which doesnot need large message buffer" line.long 0x4 "CPU1_MSG0_RMH2,Receiver Message header2(RMH2): 32 bit register each processor has (NumberOfProcessor)x4 RMH2" hexmask.long 0x4 0.--31. 1. "CPU1_MSG0_RMH2,side-band message information which is user defined.Useful in short messaging which doesnot need large message buffer" group.long 0x68++0x3 line.long 0x0 "CPU1_MSG1_RMH0,receiver message header0(RMH0) . each processor has (NumberOfProcessor)x4 RMH0" hexmask.long.byte 0x0 24.--31. 1. "CPU1_MSG1_RMH0,RMH[31:26] could be used to transfer the message RMH[25:24] is actually the message index" rbitfld.long 0x0 16. "CPU1_MSG1_VLD,message valid(MV) of this message e.g. when MV = 1 this message is meant to be received by the processor" "0,1" hexmask.long.byte 0x0 12.--15. 1. "CPU1_MSG1_MBM,Message Buffer Mask(MBM) each bit of MBM[3:0] represents the MB which are used for transferring this message. e.g. MBM[3:0] = 4b0101 means that the message is stored in MB0 and MB2" newline rbitfld.long 0x0 11. "CPU1_MSG1_USE_MB,whether this Message Buffer (MB) are used in this message" "0,1" hexmask.long.word 0x0 0.--10. 1. "CPU1_MSG1_LEN,Message Length (ML) 1x2 to 2048x2Byte" rgroup.long 0x6C++0x7 line.long 0x0 "CPU1_MSG1_RMH1,Receiver Message header1(RMH1): 32 bit register each processor has (NumberOfProcessor)x4 RMH1" hexmask.long 0x0 0.--31. 1. "CPU1_MSG1_RMH1,side-band message information which is user defined.Useful in short messaging which doesnot need large message buffer" line.long 0x4 "CPU1_MSG1_RMH2,Receiver Message header2(RMH2): 32 bit register each processor has (NumberOfProcessor)x4 RMH2" hexmask.long 0x4 0.--31. 1. "CPU1_MSG1_RMH2,side-band message information which is user defined.Useful in short messaging which doesnot need large message buffer" group.long 0x74++0x3 line.long 0x0 "CPU1_MSG2_RMH0,receiver message header0(RMH0) . each processor has (NumberOfProcessor)x4 RMH0" hexmask.long.byte 0x0 24.--31. 1. "CPU1_MSG2_RMH0,RMH[31:26] could be used to transfer the message RMH[25:24] is actually the message index" rbitfld.long 0x0 16. "CPU1_MSG2_VLD,message valid(MV) of this message e.g. when MV = 1 this message is meant to be received by the processor" "0,1" hexmask.long.byte 0x0 12.--15. 1. "CPU1_MSG2_MBM,Message Buffer Mask(MBM) each bit of MBM[3:0] represents the MB which are used for transferring this message. e.g. MBM[3:0] = 4b0101 means that the message is stored in MB0 and MB2" newline rbitfld.long 0x0 11. "CPU1_MSG2_USE_MB,whether this Message Buffer (MB) are used in this message" "0,1" hexmask.long.word 0x0 0.--10. 1. "CPU1_MSG2_LEN,Message Length (ML) 1x2 to 2048x2Byte" rgroup.long 0x78++0x7 line.long 0x0 "CPU1_MSG2_RMH1,Receiver Message header1(RMH1): 32 bit register each processor has (NumberOfProcessor)x4 RMH1" hexmask.long 0x0 0.--31. 1. "CPU1_MSG2_RMH1,side-band message information which is user defined.Useful in short messaging which doesnot need large message buffer" line.long 0x4 "CPU1_MSG2_RMH2,Receiver Message header2(RMH2): 32 bit register each processor has (NumberOfProcessor)x4 RMH2" hexmask.long 0x4 0.--31. 1. "CPU1_MSG2_RMH2,side-band message information which is user defined.Useful in short messaging which doesnot need large message buffer" group.long 0x80++0x3 line.long 0x0 "CPU1_MSG3_RMH0,receiver message header0(RMH0) . each processor has (NumberOfProcessor)x4 RMH0" hexmask.long.byte 0x0 24.--31. 1. "CPU1_MSG3_RMH0,RMH[31:26] could be used to transfer the message RMH[25:24] is actually the message index" rbitfld.long 0x0 16. "CPU1_MSG3_VLD,message valid(MV) of this message e.g. when MV = 1 this message is meant to be received by the processor" "0,1" hexmask.long.byte 0x0 12.--15. 1. "CPU1_MSG3_MBM,Message Buffer Mask(MBM) each bit of MBM[3:0] represents the MB which are used for transferring this message. e.g. MBM[3:0] = 4b0101 means that the message is stored in MB0 and MB2" newline rbitfld.long 0x0 11. "CPU1_MSG3_USE_MB,whether this Message Buffer (MB) are used in this message" "0,1" hexmask.long.word 0x0 0.--10. 1. "CPU1_MSG3_LEN,Message Length (ML) 1x2 to 2048x2Byte" rgroup.long 0x84++0x7 line.long 0x0 "CPU1_MSG3_RMH1,Receiver Message header1(RMH1): 32 bit register each processor has (NumberOfProcessor)x4 RMH1" hexmask.long 0x0 0.--31. 1. "CPU1_MSG3_RMH1,side-band message information which is user defined.Useful in short messaging which doesnot need large message buffer" line.long 0x4 "CPU1_MSG3_RMH2,Receiver Message header2(RMH2): 32 bit register each processor has (NumberOfProcessor)x4 RMH2" hexmask.long 0x4 0.--31. 1. "CPU1_MSG3_RMH2,side-band message information which is user defined.Useful in short messaging which doesnot need large message buffer" group.long 0x8C++0x3 line.long 0x0 "CPU2_MSG0_RMH0,receiver message header0(RMH0) . each processor has (NumberOfProcessor)x4 RMH0" hexmask.long.byte 0x0 24.--31. 1. "CPU2_MSG0_RMH0,RMH[31:26] could be used to transfer the message RMH[25:24] is actually the message index" rbitfld.long 0x0 16. "CPU2_MSG0_VLD,message valid(MV) of this message e.g. when MV = 1 this message is meant to be received by the processor" "0,1" hexmask.long.byte 0x0 12.--15. 1. "CPU2_MSG0_MBM,Message Buffer Mask(MBM) each bit of MBM[3:0] represents the MB which are used for transferring this message. e.g. MBM[3:0] = 4b0101 means that the message is stored in MB0 and MB2" newline rbitfld.long 0x0 11. "CPU2_MSG0_USE_MB,whether this Message Buffer (MB) are used in this message" "0,1" hexmask.long.word 0x0 0.--10. 1. "CPU2_MSG0_LEN,Message Length (ML) 1x2 to 2048x2Byte" rgroup.long 0x90++0x7 line.long 0x0 "CPU2_MSG0_RMH1,Receiver Message header1(RMH1): 32 bit register each processor has (NumberOfProcessor)x4 RMH1" hexmask.long 0x0 0.--31. 1. "CPU2_MSG0_RMH1,side-band message information which is user defined.Useful in short messaging which doesnot need large message buffer" line.long 0x4 "CPU2_MSG0_RMH2,Receiver Message header2(RMH2): 32 bit register each processor has (NumberOfProcessor)x4 RMH2" hexmask.long 0x4 0.--31. 1. "CPU2_MSG0_RMH2,side-band message information which is user defined.Useful in short messaging which doesnot need large message buffer" group.long 0x98++0x3 line.long 0x0 "CPU2_MSG1_RMH0,receiver message header0(RMH0) . each processor has (NumberOfProcessor)x4 RMH0" hexmask.long.byte 0x0 24.--31. 1. "CPU2_MSG1_RMH0,RMH[31:26] could be used to transfer the message RMH[25:24] is actually the message index" rbitfld.long 0x0 16. "CPU2_MSG1_VLD,message valid(MV) of this message e.g. when MV = 1 this message is meant to be received by the processor" "0,1" hexmask.long.byte 0x0 12.--15. 1. "CPU2_MSG1_MBM,Message Buffer Mask(MBM) each bit of MBM[3:0] represents the MB which are used for transferring this message. e.g. MBM[3:0] = 4b0101 means that the message is stored in MB0 and MB2" newline rbitfld.long 0x0 11. "CPU2_MSG1_USE_MB,whether this Message Buffer (MB) are used in this message" "0,1" hexmask.long.word 0x0 0.--10. 1. "CPU2_MSG1_LEN,Message Length (ML) 1x2 to 2048x2Byte" rgroup.long 0x9C++0x7 line.long 0x0 "CPU2_MSG1_RMH1,Receiver Message header1(RMH1): 32 bit register each processor has (NumberOfProcessor)x4 RMH1" hexmask.long 0x0 0.--31. 1. "CPU2_MSG1_RMH1,side-band message information which is user defined.Useful in short messaging which doesnot need large message buffer" line.long 0x4 "CPU2_MSG1_RMH2,Receiver Message header2(RMH2): 32 bit register each processor has (NumberOfProcessor)x4 RMH2" hexmask.long 0x4 0.--31. 1. "CPU2_MSG1_RMH2,side-band message information which is user defined.Useful in short messaging which doesnot need large message buffer" group.long 0xA4++0x3 line.long 0x0 "CPU2_MSG2_RMH0,receiver message header0(RMH0) . each processor has (NumberOfProcessor)x4 RMH0" hexmask.long.byte 0x0 24.--31. 1. "CPU2_MSG2_RMH0,RMH[31:26] could be used to transfer the message RMH[25:24] is actually the message index" rbitfld.long 0x0 16. "CPU2_MSG2_VLD,message valid(MV) of this message e.g. when MV = 1 this message is meant to be received by the processor" "0,1" hexmask.long.byte 0x0 12.--15. 1. "CPU2_MSG2_MBM,Message Buffer Mask(MBM) each bit of MBM[3:0] represents the MB which are used for transferring this message. e.g. MBM[3:0] = 4b0101 means that the message is stored in MB0 and MB2" newline rbitfld.long 0x0 11. "CPU2_MSG2_USE_MB,whether this Message Buffer (MB) are used in this message" "0,1" hexmask.long.word 0x0 0.--10. 1. "CPU2_MSG2_LEN,Message Length (ML) 1x2 to 2048x2Byte" rgroup.long 0xA8++0x7 line.long 0x0 "CPU2_MSG2_RMH1,Receiver Message header1(RMH1): 32 bit register each processor has (NumberOfProcessor)x4 RMH1" hexmask.long 0x0 0.--31. 1. "CPU2_MSG2_RMH1,side-band message information which is user defined.Useful in short messaging which doesnot need large message buffer" line.long 0x4 "CPU2_MSG2_RMH2,Receiver Message header2(RMH2): 32 bit register each processor has (NumberOfProcessor)x4 RMH2" hexmask.long 0x4 0.--31. 1. "CPU2_MSG2_RMH2,side-band message information which is user defined.Useful in short messaging which doesnot need large message buffer" group.long 0xB0++0x3 line.long 0x0 "CPU2_MSG3_RMH0,receiver message header0(RMH0) . each processor has (NumberOfProcessor)x4 RMH0" hexmask.long.byte 0x0 24.--31. 1. "CPU2_MSG3_RMH0,RMH[31:26] could be used to transfer the message RMH[25:24] is actually the message index" rbitfld.long 0x0 16. "CPU2_MSG3_VLD,message valid(MV) of this message e.g. when MV = 1 this message is meant to be received by the processor" "0,1" hexmask.long.byte 0x0 12.--15. 1. "CPU2_MSG3_MBM,Message Buffer Mask(MBM) each bit of MBM[3:0] represents the MB which are used for transferring this message. e.g. MBM[3:0] = 4b0101 means that the message is stored in MB0 and MB2" newline rbitfld.long 0x0 11. "CPU2_MSG3_USE_MB,whether this Message Buffer (MB) are used in this message" "0,1" hexmask.long.word 0x0 0.--10. 1. "CPU2_MSG3_LEN,Message Length (ML) 1x2 to 2048x2Byte" rgroup.long 0xB4++0x7 line.long 0x0 "CPU2_MSG3_RMH1,Receiver Message header1(RMH1): 32 bit register each processor has (NumberOfProcessor)x4 RMH1" hexmask.long 0x0 0.--31. 1. "CPU2_MSG3_RMH1,side-band message information which is user defined.Useful in short messaging which doesnot need large message buffer" line.long 0x4 "CPU2_MSG3_RMH2,Receiver Message header2(RMH2): 32 bit register each processor has (NumberOfProcessor)x4 RMH2" hexmask.long 0x4 0.--31. 1. "CPU2_MSG3_RMH2,side-band message information which is user defined.Useful in short messaging which doesnot need large message buffer" group.long 0xBC++0x3 line.long 0x0 "CPU3_MSG0_RMH0,receiver message header0(RMH0) . each processor has (NumberOfProcessor)x4 RMH0" hexmask.long.byte 0x0 24.--31. 1. "CPU3_MSG0_RMH0,RMH[31:26] could be used to transfer the message RMH[25:24] is actually the message index" rbitfld.long 0x0 16. "CPU3_MSG0_VLD,message valid(MV) of this message e.g. when MV = 1 this message is meant to be received by the processor" "0,1" hexmask.long.byte 0x0 12.--15. 1. "CPU3_MSG0_MBM,Message Buffer Mask(MBM) each bit of MBM[3:0] represents the MB which are used for transferring this message. e.g. MBM[3:0] = 4b0101 means that the message is stored in MB0 and MB2" newline rbitfld.long 0x0 11. "CPU3_MSG0_USE_MB,whether this Message Buffer (MB) are used in this message" "0,1" hexmask.long.word 0x0 0.--10. 1. "CPU3_MSG0_LEN,Message Length (ML) 1x2 to 2048x2Byte" rgroup.long 0xC0++0x7 line.long 0x0 "CPU3_MSG0_RMH1,Receiver Message header1(RMH1): 32 bit register each processor has (NumberOfProcessor)x4 RMH1" hexmask.long 0x0 0.--31. 1. "CPU3_MSG0_RMH1,side-band message information which is user defined.Useful in short messaging which doesnot need large message buffer" line.long 0x4 "CPU3_MSG0_RMH2,Receiver Message header2(RMH2): 32 bit register each processor has (NumberOfProcessor)x4 RMH2" hexmask.long 0x4 0.--31. 1. "CPU3_MSG0_RMH2,side-band message information which is user defined.Useful in short messaging which doesnot need large message buffer" group.long 0xC8++0x3 line.long 0x0 "CPU3_MSG1_RMH0,receiver message header0(RMH0) . each processor has (NumberOfProcessor)x4 RMH0" hexmask.long.byte 0x0 24.--31. 1. "CPU3_MSG1_RMH0,RMH[31:26] could be used to transfer the message RMH[25:24] is actually the message index" rbitfld.long 0x0 16. "CPU3_MSG1_VLD,message valid(MV) of this message e.g. when MV = 1 this message is meant to be received by the processor" "0,1" hexmask.long.byte 0x0 12.--15. 1. "CPU3_MSG1_MBM,Message Buffer Mask(MBM) each bit of MBM[3:0] represents the MB which are used for transferring this message. e.g. MBM[3:0] = 4b0101 means that the message is stored in MB0 and MB2" newline rbitfld.long 0x0 11. "CPU3_MSG1_USE_MB,whether this Message Buffer (MB) are used in this message" "0,1" hexmask.long.word 0x0 0.--10. 1. "CPU3_MSG1_LEN,Message Length (ML) 1x2 to 2048x2Byte" rgroup.long 0xCC++0x7 line.long 0x0 "CPU3_MSG1_RMH1,Receiver Message header1(RMH1): 32 bit register each processor has (NumberOfProcessor)x4 RMH1" hexmask.long 0x0 0.--31. 1. "CPU3_MSG1_RMH1,side-band message information which is user defined.Useful in short messaging which doesnot need large message buffer" line.long 0x4 "CPU3_MSG1_RMH2,Receiver Message header2(RMH2): 32 bit register each processor has (NumberOfProcessor)x4 RMH2" hexmask.long 0x4 0.--31. 1. "CPU3_MSG1_RMH2,side-band message information which is user defined.Useful in short messaging which doesnot need large message buffer" group.long 0xD4++0x3 line.long 0x0 "CPU3_MSG2_RMH0,receiver message header0(RMH0) . each processor has (NumberOfProcessor)x4 RMH0" hexmask.long.byte 0x0 24.--31. 1. "CPU3_MSG2_RMH0,RMH[31:26] could be used to transfer the message RMH[25:24] is actually the message index" rbitfld.long 0x0 16. "CPU3_MSG2_VLD,message valid(MV) of this message e.g. when MV = 1 this message is meant to be received by the processor" "0,1" hexmask.long.byte 0x0 12.--15. 1. "CPU3_MSG2_MBM,Message Buffer Mask(MBM) each bit of MBM[3:0] represents the MB which are used for transferring this message. e.g. MBM[3:0] = 4b0101 means that the message is stored in MB0 and MB2" newline rbitfld.long 0x0 11. "CPU3_MSG2_USE_MB,whether this Message Buffer (MB) are used in this message" "0,1" hexmask.long.word 0x0 0.--10. 1. "CPU3_MSG2_LEN,Message Length (ML) 1x2 to 2048x2Byte" rgroup.long 0xD8++0x7 line.long 0x0 "CPU3_MSG2_RMH1,Receiver Message header1(RMH1): 32 bit register each processor has (NumberOfProcessor)x4 RMH1" hexmask.long 0x0 0.--31. 1. "CPU3_MSG2_RMH1,side-band message information which is user defined.Useful in short messaging which doesnot need large message buffer" line.long 0x4 "CPU3_MSG2_RMH2,Receiver Message header2(RMH2): 32 bit register each processor has (NumberOfProcessor)x4 RMH2" hexmask.long 0x4 0.--31. 1. "CPU3_MSG2_RMH2,side-band message information which is user defined.Useful in short messaging which doesnot need large message buffer" group.long 0xE0++0x3 line.long 0x0 "CPU3_MSG3_RMH0,receiver message header0(RMH0) . each processor has (NumberOfProcessor)x4 RMH0" hexmask.long.byte 0x0 24.--31. 1. "CPU3_MSG3_RMH0,RMH[31:26] could be used to transfer the message RMH[25:24] is actually the message index" rbitfld.long 0x0 16. "CPU3_MSG3_VLD,message valid(MV) of this message e.g. when MV = 1 this message is meant to be received by the processor" "0,1" hexmask.long.byte 0x0 12.--15. 1. "CPU3_MSG3_MBM,Message Buffer Mask(MBM) each bit of MBM[3:0] represents the MB which are used for transferring this message. e.g. MBM[3:0] = 4b0101 means that the message is stored in MB0 and MB2" newline rbitfld.long 0x0 11. "CPU3_MSG3_USE_MB,whether this Message Buffer (MB) are used in this message" "0,1" hexmask.long.word 0x0 0.--10. 1. "CPU3_MSG3_LEN,Message Length (ML) 1x2 to 2048x2Byte" rgroup.long 0xE4++0x7 line.long 0x0 "CPU3_MSG3_RMH1,Receiver Message header1(RMH1): 32 bit register each processor has (NumberOfProcessor)x4 RMH1" hexmask.long 0x0 0.--31. 1. "CPU3_MSG3_RMH1,side-band message information which is user defined.Useful in short messaging which doesnot need large message buffer" line.long 0x4 "CPU3_MSG3_RMH2,Receiver Message header2(RMH2): 32 bit register each processor has (NumberOfProcessor)x4 RMH2" hexmask.long 0x4 0.--31. 1. "CPU3_MSG3_RMH2,side-band message information which is user defined.Useful in short messaging which doesnot need large message buffer" group.long 0xEC++0x3 line.long 0x0 "CPU4_MSG0_RMH0,receiver message header0(RMH0) . each processor has (NumberOfProcessor)x4 RMH0" hexmask.long.byte 0x0 24.--31. 1. "CPU4_MSG0_RMH0,RMH[31:26] could be used to transfer the message RMH[25:24] is actually the message index" rbitfld.long 0x0 16. "CPU4_MSG0_VLD,message valid(MV) of this message e.g. when MV = 1 this message is meant to be received by the processor" "0,1" hexmask.long.byte 0x0 12.--15. 1. "CPU4_MSG0_MBM,Message Buffer Mask(MBM) each bit of MBM[3:0] represents the MB which are used for transferring this message. e.g. MBM[3:0] = 4b0101 means that the message is stored in MB0 and MB2" newline rbitfld.long 0x0 11. "CPU4_MSG0_USE_MB,whether this Message Buffer (MB) are used in this message" "0,1" hexmask.long.word 0x0 0.--10. 1. "CPU4_MSG0_LEN,Message Length (ML) 1x2 to 2048x2Byte" rgroup.long 0xF0++0x7 line.long 0x0 "CPU4_MSG0_RMH1,Receiver Message header1(RMH1): 32 bit register each processor has (NumberOfProcessor)x4 RMH1" hexmask.long 0x0 0.--31. 1. "CPU4_MSG0_RMH1,side-band message information which is user defined.Useful in short messaging which doesnot need large message buffer" line.long 0x4 "CPU4_MSG0_RMH2,Receiver Message header2(RMH2): 32 bit register each processor has (NumberOfProcessor)x4 RMH2" hexmask.long 0x4 0.--31. 1. "CPU4_MSG0_RMH2,side-band message information which is user defined.Useful in short messaging which doesnot need large message buffer" group.long 0xF8++0x3 line.long 0x0 "CPU4_MSG1_RMH0,receiver message header0(RMH0) . each processor has (NumberOfProcessor)x4 RMH0" hexmask.long.byte 0x0 24.--31. 1. "CPU4_MSG1_RMH0,RMH[31:26] could be used to transfer the message RMH[25:24] is actually the message index" rbitfld.long 0x0 16. "CPU4_MSG1_VLD,message valid(MV) of this message e.g. when MV = 1 this message is meant to be received by the processor" "0,1" hexmask.long.byte 0x0 12.--15. 1. "CPU4_MSG1_MBM,Message Buffer Mask(MBM) each bit of MBM[3:0] represents the MB which are used for transferring this message. e.g. MBM[3:0] = 4b0101 means that the message is stored in MB0 and MB2" newline rbitfld.long 0x0 11. "CPU4_MSG1_USE_MB,whether this Message Buffer (MB) are used in this message" "0,1" hexmask.long.word 0x0 0.--10. 1. "CPU4_MSG1_LEN,Message Length (ML) 1x2 to 2048x2Byte" rgroup.long 0xFC++0x7 line.long 0x0 "CPU4_MSG1_RMH1,Receiver Message header1(RMH1): 32 bit register each processor has (NumberOfProcessor)x4 RMH1" hexmask.long 0x0 0.--31. 1. "CPU4_MSG1_RMH1,side-band message information which is user defined.Useful in short messaging which doesnot need large message buffer" line.long 0x4 "CPU4_MSG1_RMH2,Receiver Message header2(RMH2): 32 bit register each processor has (NumberOfProcessor)x4 RMH2" hexmask.long 0x4 0.--31. 1. "CPU4_MSG1_RMH2,side-band message information which is user defined.Useful in short messaging which doesnot need large message buffer" group.long 0x104++0x3 line.long 0x0 "CPU4_MSG2_RMH0,receiver message header0(RMH0) . each processor has (NumberOfProcessor)x4 RMH0" hexmask.long.byte 0x0 24.--31. 1. "CPU4_MSG2_RMH0,RMH[31:26] could be used to transfer the message RMH[25:24] is actually the message index" rbitfld.long 0x0 16. "CPU4_MSG2_VLD,message valid(MV) of this message e.g. when MV = 1 this message is meant to be received by the processor" "0,1" hexmask.long.byte 0x0 12.--15. 1. "CPU4_MSG2_MBM,Message Buffer Mask(MBM) each bit of MBM[3:0] represents the MB which are used for transferring this message. e.g. MBM[3:0] = 4b0101 means that the message is stored in MB0 and MB2" newline rbitfld.long 0x0 11. "CPU4_MSG2_USE_MB,whether this Message Buffer (MB) are used in this message" "0,1" hexmask.long.word 0x0 0.--10. 1. "CPU4_MSG2_LEN,Message Length (ML) 1x2 to 2048x2Byte" rgroup.long 0x108++0x7 line.long 0x0 "CPU4_MSG2_RMH1,Receiver Message header1(RMH1): 32 bit register each processor has (NumberOfProcessor)x4 RMH1" hexmask.long 0x0 0.--31. 1. "CPU4_MSG2_RMH1,side-band message information which is user defined.Useful in short messaging which doesnot need large message buffer" line.long 0x4 "CPU4_MSG2_RMH2,Receiver Message header2(RMH2): 32 bit register each processor has (NumberOfProcessor)x4 RMH2" hexmask.long 0x4 0.--31. 1. "CPU4_MSG2_RMH2,side-band message information which is user defined.Useful in short messaging which doesnot need large message buffer" group.long 0x110++0x3 line.long 0x0 "CPU4_MSG3_RMH0,receiver message header0(RMH0) . each processor has (NumberOfProcessor)x4 RMH0" hexmask.long.byte 0x0 24.--31. 1. "CPU4_MSG3_RMH0,RMH[31:26] could be used to transfer the message RMH[25:24] is actually the message index" rbitfld.long 0x0 16. "CPU4_MSG3_VLD,message valid(MV) of this message e.g. when MV = 1 this message is meant to be received by the processor" "0,1" hexmask.long.byte 0x0 12.--15. 1. "CPU4_MSG3_MBM,Message Buffer Mask(MBM) each bit of MBM[3:0] represents the MB which are used for transferring this message. e.g. MBM[3:0] = 4b0101 means that the message is stored in MB0 and MB2" newline rbitfld.long 0x0 11. "CPU4_MSG3_USE_MB,whether this Message Buffer (MB) are used in this message" "0,1" hexmask.long.word 0x0 0.--10. 1. "CPU4_MSG3_LEN,Message Length (ML) 1x2 to 2048x2Byte" rgroup.long 0x114++0x7 line.long 0x0 "CPU4_MSG3_RMH1,Receiver Message header1(RMH1): 32 bit register each processor has (NumberOfProcessor)x4 RMH1" hexmask.long 0x0 0.--31. 1. "CPU4_MSG3_RMH1,side-band message information which is user defined.Useful in short messaging which doesnot need large message buffer" line.long 0x4 "CPU4_MSG3_RMH2,Receiver Message header2(RMH2): 32 bit register each processor has (NumberOfProcessor)x4 RMH2" hexmask.long 0x4 0.--31. 1. "CPU4_MSG3_RMH2,side-band message information which is user defined.Useful in short messaging which doesnot need large message buffer" group.long 0x11C++0x3 line.long 0x0 "CPU5_MSG0_RMH0,receiver message header0(RMH0) . each processor has (NumberOfProcessor)x4 RMH0" hexmask.long.byte 0x0 24.--31. 1. "CPU5_MSG0_RMH0,RMH[31:26] could be used to transfer the message RMH[25:24] is actually the message index" rbitfld.long 0x0 16. "CPU5_MSG0_VLD,message valid(MV) of this message e.g. when MV = 1 this message is meant to be received by the processor" "0,1" hexmask.long.byte 0x0 12.--15. 1. "CPU5_MSG0_MBM,Message Buffer Mask(MBM) each bit of MBM[3:0] represents the MB which are used for transferring this message. e.g. MBM[3:0] = 4b0101 means that the message is stored in MB0 and MB2" newline rbitfld.long 0x0 11. "CPU5_MSG0_USE_MB,whether this Message Buffer (MB) are used in this message" "0,1" hexmask.long.word 0x0 0.--10. 1. "CPU5_MSG0_LEN,Message Length (ML) 1x2 to 2048x2Byte" rgroup.long 0x120++0x7 line.long 0x0 "CPU5_MSG0_RMH1,Receiver Message header1(RMH1): 32 bit register each processor has (NumberOfProcessor)x4 RMH1" hexmask.long 0x0 0.--31. 1. "CPU5_MSG0_RMH1,side-band message information which is user defined.Useful in short messaging which doesnot need large message buffer" line.long 0x4 "CPU5_MSG0_RMH2,Receiver Message header2(RMH2): 32 bit register each processor has (NumberOfProcessor)x4 RMH2" hexmask.long 0x4 0.--31. 1. "CPU5_MSG0_RMH2,side-band message information which is user defined.Useful in short messaging which doesnot need large message buffer" group.long 0x128++0x3 line.long 0x0 "CPU5_MSG1_RMH0,receiver message header0(RMH0) . each processor has (NumberOfProcessor)x4 RMH0" hexmask.long.byte 0x0 24.--31. 1. "CPU5_MSG1_RMH0,RMH[31:26] could be used to transfer the message RMH[25:24] is actually the message index" rbitfld.long 0x0 16. "CPU5_MSG1_VLD,message valid(MV) of this message e.g. when MV = 1 this message is meant to be received by the processor" "0,1" hexmask.long.byte 0x0 12.--15. 1. "CPU5_MSG1_MBM,Message Buffer Mask(MBM) each bit of MBM[3:0] represents the MB which are used for transferring this message. e.g. MBM[3:0] = 4b0101 means that the message is stored in MB0 and MB2" newline rbitfld.long 0x0 11. "CPU5_MSG1_USE_MB,whether this Message Buffer (MB) are used in this message" "0,1" hexmask.long.word 0x0 0.--10. 1. "CPU5_MSG1_LEN,Message Length (ML) 1x2 to 2048x2Byte" rgroup.long 0x12C++0x7 line.long 0x0 "CPU5_MSG1_RMH1,Receiver Message header1(RMH1): 32 bit register each processor has (NumberOfProcessor)x4 RMH1" hexmask.long 0x0 0.--31. 1. "CPU5_MSG1_RMH1,side-band message information which is user defined.Useful in short messaging which doesnot need large message buffer" line.long 0x4 "CPU5_MSG1_RMH2,Receiver Message header2(RMH2): 32 bit register each processor has (NumberOfProcessor)x4 RMH2" hexmask.long 0x4 0.--31. 1. "CPU5_MSG1_RMH2,side-band message information which is user defined.Useful in short messaging which doesnot need large message buffer" group.long 0x134++0x3 line.long 0x0 "CPU5_MSG2_RMH0,receiver message header0(RMH0) . each processor has (NumberOfProcessor)x4 RMH0" hexmask.long.byte 0x0 24.--31. 1. "CPU5_MSG2_RMH0,RMH[31:26] could be used to transfer the message RMH[25:24] is actually the message index" rbitfld.long 0x0 16. "CPU5_MSG2_VLD,message valid(MV) of this message e.g. when MV = 1 this message is meant to be received by the processor" "0,1" hexmask.long.byte 0x0 12.--15. 1. "CPU5_MSG2_MBM,Message Buffer Mask(MBM) each bit of MBM[3:0] represents the MB which are used for transferring this message. e.g. MBM[3:0] = 4b0101 means that the message is stored in MB0 and MB2" newline rbitfld.long 0x0 11. "CPU5_MSG2_USE_MB,whether this Message Buffer (MB) are used in this message" "0,1" hexmask.long.word 0x0 0.--10. 1. "CPU5_MSG2_LEN,Message Length (ML) 1x2 to 2048x2Byte" rgroup.long 0x138++0x7 line.long 0x0 "CPU5_MSG2_RMH1,Receiver Message header1(RMH1): 32 bit register each processor has (NumberOfProcessor)x4 RMH1" hexmask.long 0x0 0.--31. 1. "CPU5_MSG2_RMH1,side-band message information which is user defined.Useful in short messaging which doesnot need large message buffer" line.long 0x4 "CPU5_MSG2_RMH2,Receiver Message header2(RMH2): 32 bit register each processor has (NumberOfProcessor)x4 RMH2" hexmask.long 0x4 0.--31. 1. "CPU5_MSG2_RMH2,side-band message information which is user defined.Useful in short messaging which doesnot need large message buffer" group.long 0x140++0x3 line.long 0x0 "CPU5_MSG3_RMH0,receiver message header0(RMH0) . each processor has (NumberOfProcessor)x4 RMH0" hexmask.long.byte 0x0 24.--31. 1. "CPU5_MSG3_RMH0,RMH[31:26] could be used to transfer the message RMH[25:24] is actually the message index" rbitfld.long 0x0 16. "CPU5_MSG3_VLD,message valid(MV) of this message e.g. when MV = 1 this message is meant to be received by the processor" "0,1" hexmask.long.byte 0x0 12.--15. 1. "CPU5_MSG3_MBM,Message Buffer Mask(MBM) each bit of MBM[3:0] represents the MB which are used for transferring this message. e.g. MBM[3:0] = 4b0101 means that the message is stored in MB0 and MB2" newline rbitfld.long 0x0 11. "CPU5_MSG3_USE_MB,whether this Message Buffer (MB) are used in this message" "0,1" hexmask.long.word 0x0 0.--10. 1. "CPU5_MSG3_LEN,Message Length (ML) 1x2 to 2048x2Byte" rgroup.long 0x144++0x7 line.long 0x0 "CPU5_MSG3_RMH1,Receiver Message header1(RMH1): 32 bit register each processor has (NumberOfProcessor)x4 RMH1" hexmask.long 0x0 0.--31. 1. "CPU5_MSG3_RMH1,side-band message information which is user defined.Useful in short messaging which doesnot need large message buffer" line.long 0x4 "CPU5_MSG3_RMH2,Receiver Message header2(RMH2): 32 bit register each processor has (NumberOfProcessor)x4 RMH2" hexmask.long 0x4 0.--31. 1. "CPU5_MSG3_RMH2,side-band message information which is user defined.Useful in short messaging which doesnot need large message buffer" group.long 0x14C++0x3 line.long 0x0 "CPU6_MSG0_RMH0,receiver message header0(RMH0) . each processor has (NumberOfProcessor)x4 RMH0" hexmask.long.byte 0x0 24.--31. 1. "CPU6_MSG0_RMH0,RMH[31:26] could be used to transfer the message RMH[25:24] is actually the message index" rbitfld.long 0x0 16. "CPU6_MSG0_VLD,message valid(MV) of this message e.g. when MV = 1 this message is meant to be received by the processor" "0,1" hexmask.long.byte 0x0 12.--15. 1. "CPU6_MSG0_MBM,Message Buffer Mask(MBM) each bit of MBM[3:0] represents the MB which are used for transferring this message. e.g. MBM[3:0] = 4b0101 means that the message is stored in MB0 and MB2" newline rbitfld.long 0x0 11. "CPU6_MSG0_USE_MB,whether this Message Buffer (MB) are used in this message" "0,1" hexmask.long.word 0x0 0.--10. 1. "CPU6_MSG0_LEN,Message Length (ML) 1x2 to 2048x2Byte" rgroup.long 0x150++0x7 line.long 0x0 "CPU6_MSG0_RMH1,Receiver Message header1(RMH1): 32 bit register each processor has (NumberOfProcessor)x4 RMH1" hexmask.long 0x0 0.--31. 1. "CPU6_MSG0_RMH1,side-band message information which is user defined.Useful in short messaging which doesnot need large message buffer" line.long 0x4 "CPU6_MSG0_RMH2,Receiver Message header2(RMH2): 32 bit register each processor has (NumberOfProcessor)x4 RMH2" hexmask.long 0x4 0.--31. 1. "CPU6_MSG0_RMH2,side-band message information which is user defined.Useful in short messaging which doesnot need large message buffer" group.long 0x158++0x3 line.long 0x0 "CPU6_MSG1_RMH0,receiver message header0(RMH0) . each processor has (NumberOfProcessor)x4 RMH0" hexmask.long.byte 0x0 24.--31. 1. "CPU6_MSG1_RMH0,RMH[31:26] could be used to transfer the message RMH[25:24] is actually the message index" rbitfld.long 0x0 16. "CPU6_MSG1_VLD,message valid(MV) of this message e.g. when MV = 1 this message is meant to be received by the processor" "0,1" hexmask.long.byte 0x0 12.--15. 1. "CPU6_MSG1_MBM,Message Buffer Mask(MBM) each bit of MBM[3:0] represents the MB which are used for transferring this message. e.g. MBM[3:0] = 4b0101 means that the message is stored in MB0 and MB2" newline rbitfld.long 0x0 11. "CPU6_MSG1_USE_MB,whether this Message Buffer (MB) are used in this message" "0,1" hexmask.long.word 0x0 0.--10. 1. "CPU6_MSG1_LEN,Message Length (ML) 1x2 to 2048x2Byte" rgroup.long 0x15C++0x7 line.long 0x0 "CPU6_MSG1_RMH1,Receiver Message header1(RMH1): 32 bit register each processor has (NumberOfProcessor)x4 RMH1" hexmask.long 0x0 0.--31. 1. "CPU6_MSG1_RMH1,side-band message information which is user defined.Useful in short messaging which doesnot need large message buffer" line.long 0x4 "CPU6_MSG1_RMH2,Receiver Message header2(RMH2): 32 bit register each processor has (NumberOfProcessor)x4 RMH2" hexmask.long 0x4 0.--31. 1. "CPU6_MSG1_RMH2,side-band message information which is user defined.Useful in short messaging which doesnot need large message buffer" group.long 0x164++0x3 line.long 0x0 "CPU6_MSG2_RMH0,receiver message header0(RMH0) . each processor has (NumberOfProcessor)x4 RMH0" hexmask.long.byte 0x0 24.--31. 1. "CPU6_MSG2_RMH0,RMH[31:26] could be used to transfer the message RMH[25:24] is actually the message index" rbitfld.long 0x0 16. "CPU6_MSG2_VLD,message valid(MV) of this message e.g. when MV = 1 this message is meant to be received by the processor" "0,1" hexmask.long.byte 0x0 12.--15. 1. "CPU6_MSG2_MBM,Message Buffer Mask(MBM) each bit of MBM[3:0] represents the MB which are used for transferring this message. e.g. MBM[3:0] = 4b0101 means that the message is stored in MB0 and MB2" newline rbitfld.long 0x0 11. "CPU6_MSG2_USE_MB,whether this Message Buffer (MB) are used in this message" "0,1" hexmask.long.word 0x0 0.--10. 1. "CPU6_MSG2_LEN,Message Length (ML) 1x2 to 2048x2Byte" rgroup.long 0x168++0x7 line.long 0x0 "CPU6_MSG2_RMH1,Receiver Message header1(RMH1): 32 bit register each processor has (NumberOfProcessor)x4 RMH1" hexmask.long 0x0 0.--31. 1. "CPU6_MSG2_RMH1,side-band message information which is user defined.Useful in short messaging which doesnot need large message buffer" line.long 0x4 "CPU6_MSG2_RMH2,Receiver Message header2(RMH2): 32 bit register each processor has (NumberOfProcessor)x4 RMH2" hexmask.long 0x4 0.--31. 1. "CPU6_MSG2_RMH2,side-band message information which is user defined.Useful in short messaging which doesnot need large message buffer" group.long 0x170++0x3 line.long 0x0 "CPU6_MSG3_RMH0,receiver message header0(RMH0) . each processor has (NumberOfProcessor)x4 RMH0" hexmask.long.byte 0x0 24.--31. 1. "CPU6_MSG3_RMH0,RMH[31:26] could be used to transfer the message RMH[25:24] is actually the message index" rbitfld.long 0x0 16. "CPU6_MSG3_VLD,message valid(MV) of this message e.g. when MV = 1 this message is meant to be received by the processor" "0,1" hexmask.long.byte 0x0 12.--15. 1. "CPU6_MSG3_MBM,Message Buffer Mask(MBM) each bit of MBM[3:0] represents the MB which are used for transferring this message. e.g. MBM[3:0] = 4b0101 means that the message is stored in MB0 and MB2" newline rbitfld.long 0x0 11. "CPU6_MSG3_USE_MB,whether this Message Buffer (MB) are used in this message" "0,1" hexmask.long.word 0x0 0.--10. 1. "CPU6_MSG3_LEN,Message Length (ML) 1x2 to 2048x2Byte" rgroup.long 0x174++0x7 line.long 0x0 "CPU6_MSG3_RMH1,Receiver Message header1(RMH1): 32 bit register each processor has (NumberOfProcessor)x4 RMH1" hexmask.long 0x0 0.--31. 1. "CPU6_MSG3_RMH1,side-band message information which is user defined.Useful in short messaging which doesnot need large message buffer" line.long 0x4 "CPU6_MSG3_RMH2,Receiver Message header2(RMH2): 32 bit register each processor has (NumberOfProcessor)x4 RMH2" hexmask.long 0x4 0.--31. 1. "CPU6_MSG3_RMH2,side-band message information which is user defined.Useful in short messaging which doesnot need large message buffer" group.long 0x17C++0x3 line.long 0x0 "CPU7_MSG0_RMH0,receiver message header0(RMH0) . each processor has (NumberOfProcessor)x4 RMH0" hexmask.long.byte 0x0 24.--31. 1. "CPU7_MSG0_RMH0,RMH[31:26] could be used to transfer the message RMH[25:24] is actually the message index" rbitfld.long 0x0 16. "CPU7_MSG0_VLD,message valid(MV) of this message e.g. when MV = 1 this message is meant to be received by the processor" "0,1" hexmask.long.byte 0x0 12.--15. 1. "CPU7_MSG0_MBM,Message Buffer Mask(MBM) each bit of MBM[3:0] represents the MB which are used for transferring this message. e.g. MBM[3:0] = 4b0101 means that the message is stored in MB0 and MB2" newline rbitfld.long 0x0 11. "CPU7_MSG0_USE_MB,whether this Message Buffer (MB) are used in this message" "0,1" hexmask.long.word 0x0 0.--10. 1. "CPU7_MSG0_LEN,Message Length (ML) 1x2 to 2048x2Byte" rgroup.long 0x180++0x7 line.long 0x0 "CPU7_MSG0_RMH1,Receiver Message header1(RMH1): 32 bit register each processor has (NumberOfProcessor)x4 RMH1" hexmask.long 0x0 0.--31. 1. "CPU7_MSG0_RMH1,side-band message information which is user defined.Useful in short messaging which doesnot need large message buffer" line.long 0x4 "CPU7_MSG0_RMH2,Receiver Message header2(RMH2): 32 bit register each processor has (NumberOfProcessor)x4 RMH2" hexmask.long 0x4 0.--31. 1. "CPU7_MSG0_RMH2,side-band message information which is user defined.Useful in short messaging which doesnot need large message buffer" group.long 0x188++0x3 line.long 0x0 "CPU7_MSG1_RMH0,receiver message header0(RMH0) . each processor has (NumberOfProcessor)x4 RMH0" hexmask.long.byte 0x0 24.--31. 1. "CPU7_MSG1_RMH0,RMH[31:26] could be used to transfer the message RMH[25:24] is actually the message index" rbitfld.long 0x0 16. "CPU7_MSG1_VLD,message valid(MV) of this message e.g. when MV = 1 this message is meant to be received by the processor" "0,1" hexmask.long.byte 0x0 12.--15. 1. "CPU7_MSG1_MBM,Message Buffer Mask(MBM) each bit of MBM[3:0] represents the MB which are used for transferring this message. e.g. MBM[3:0] = 4b0101 means that the message is stored in MB0 and MB2" newline rbitfld.long 0x0 11. "CPU7_MSG1_USE_MB,whether this Message Buffer (MB) are used in this message" "0,1" hexmask.long.word 0x0 0.--10. 1. "CPU7_MSG1_LEN,Message Length (ML) 1x2 to 2048x2Byte" rgroup.long 0x18C++0x7 line.long 0x0 "CPU7_MSG1_RMH1,Receiver Message header1(RMH1): 32 bit register each processor has (NumberOfProcessor)x4 RMH1" hexmask.long 0x0 0.--31. 1. "CPU7_MSG1_RMH1,side-band message information which is user defined.Useful in short messaging which doesnot need large message buffer" line.long 0x4 "CPU7_MSG1_RMH2,Receiver Message header2(RMH2): 32 bit register each processor has (NumberOfProcessor)x4 RMH2" hexmask.long 0x4 0.--31. 1. "CPU7_MSG1_RMH2,side-band message information which is user defined.Useful in short messaging which doesnot need large message buffer" group.long 0x194++0x3 line.long 0x0 "CPU7_MSG2_RMH0,receiver message header0(RMH0) . each processor has (NumberOfProcessor)x4 RMH0" hexmask.long.byte 0x0 24.--31. 1. "CPU7_MSG2_RMH0,RMH[31:26] could be used to transfer the message RMH[25:24] is actually the message index" rbitfld.long 0x0 16. "CPU7_MSG2_VLD,message valid(MV) of this message e.g. when MV = 1 this message is meant to be received by the processor" "0,1" hexmask.long.byte 0x0 12.--15. 1. "CPU7_MSG2_MBM,Message Buffer Mask(MBM) each bit of MBM[3:0] represents the MB which are used for transferring this message. e.g. MBM[3:0] = 4b0101 means that the message is stored in MB0 and MB2" newline rbitfld.long 0x0 11. "CPU7_MSG2_USE_MB,whether this Message Buffer (MB) are used in this message" "0,1" hexmask.long.word 0x0 0.--10. 1. "CPU7_MSG2_LEN,Message Length (ML) 1x2 to 2048x2Byte" rgroup.long 0x198++0x7 line.long 0x0 "CPU7_MSG2_RMH1,Receiver Message header1(RMH1): 32 bit register each processor has (NumberOfProcessor)x4 RMH1" hexmask.long 0x0 0.--31. 1. "CPU7_MSG2_RMH1,side-band message information which is user defined.Useful in short messaging which doesnot need large message buffer" line.long 0x4 "CPU7_MSG2_RMH2,Receiver Message header2(RMH2): 32 bit register each processor has (NumberOfProcessor)x4 RMH2" hexmask.long 0x4 0.--31. 1. "CPU7_MSG2_RMH2,side-band message information which is user defined.Useful in short messaging which doesnot need large message buffer" group.long 0x1A0++0x3 line.long 0x0 "CPU7_MSG3_RMH0,receiver message header0(RMH0) . each processor has (NumberOfProcessor)x4 RMH0" hexmask.long.byte 0x0 24.--31. 1. "CPU7_MSG3_RMH0,RMH[31:26] could be used to transfer the message RMH[25:24] is actually the message index" rbitfld.long 0x0 16. "CPU7_MSG3_VLD,message valid(MV) of this message e.g. when MV = 1 this message is meant to be received by the processor" "0,1" hexmask.long.byte 0x0 12.--15. 1. "CPU7_MSG3_MBM,Message Buffer Mask(MBM) each bit of MBM[3:0] represents the MB which are used for transferring this message. e.g. MBM[3:0] = 4b0101 means that the message is stored in MB0 and MB2" newline rbitfld.long 0x0 11. "CPU7_MSG3_USE_MB,whether this Message Buffer (MB) are used in this message" "0,1" hexmask.long.word 0x0 0.--10. 1. "CPU7_MSG3_LEN,Message Length (ML) 1x2 to 2048x2Byte" rgroup.long 0x1A4++0x7 line.long 0x0 "CPU7_MSG3_RMH1,Receiver Message header1(RMH1): 32 bit register each processor has (NumberOfProcessor)x4 RMH1" hexmask.long 0x0 0.--31. 1. "CPU7_MSG3_RMH1,side-band message information which is user defined.Useful in short messaging which doesnot need large message buffer" line.long 0x4 "CPU7_MSG3_RMH2,Receiver Message header2(RMH2): 32 bit register each processor has (NumberOfProcessor)x4 RMH2" hexmask.long 0x4 0.--31. 1. "CPU7_MSG3_RMH2,side-band message information which is user defined.Useful in short messaging which doesnot need large message buffer" repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x8 0x10 0x18 0x20 0x28 0x30 0x38 0x40 0x48 0x50 0x58 0x60 0x68 0x70 0x78 ) group.long ($2+0x200)++0x3 line.long 0x0 "SEMAG$1,SEMAphore gate. 32 bit register. update to 64Gate based on parameter configuration" bitfld.long 0x0 24. "SG0LIC,Semaphore Gate 0 Lock interrupt clear (SGLIC[7:0]) write 1 to this register will clear the lock fail interrrupt to the processor" "0,1" hexmask.long.byte 0x0 16.--23. 1. "SG0LS,Semaphore Gate 0 Lock Status (SGLS[7:0]) SG0LS=8b00001000 means the gate is locked by Processor" newline bitfld.long 0x0 8. "IESG0LF,Interrupt Enable on Semaphore Gate Lock Failure (IESGLF) When 1 MU will send interrupt to the Processer which failed to lock the semaphore gate on semaphore gate release" "0,1" bitfld.long 0x0 0. "SG0C,Can be accessed by all processors. One Processor can write 1 to SGC to request lock of this gate. Processer can read this bit to check if semaphore is locked or not (when 0 locked when 1 locked).The lock can be removed by write 0 to this field by.." "0,1" repeat.end repeat 16. (list 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1A 0x1B 0x1C 0x1D 0x1E 0x1F )(list 0x80 0x88 0x90 0x98 0xA0 0xA8 0xB0 0xB8 0xC0 0xC8 0xD0 0xD8 0xE0 0xE8 0xF0 0xF8 ) group.long ($2+0x200)++0x3 line.long 0x0 "SEMAG$1,SEMAphore gate. 32 bit register. update to 64Gate based on parameter configuration" bitfld.long 0x0 24. "SG0LIC,Semaphore Gate 0 Lock interrupt clear (SGLIC[7:0]) write 1 to this register will clear the lock fail interrrupt to the processor" "0,1" hexmask.long.byte 0x0 16.--23. 1. "SG0LS,Semaphore Gate 0 Lock Status (SGLS[7:0]) SG0LS=8b00001000 means the gate is locked by Processor" newline bitfld.long 0x0 8. "IESG0LF,Interrupt Enable on Semaphore Gate Lock Failure (IESGLF) When 1 MU will send interrupt to the Processer which failed to lock the semaphore gate on semaphore gate release" "0,1" bitfld.long 0x0 0. "SG0C,Can be accessed by all processors. One Processor can write 1 to SGC to request lock of this gate. Processer can read this bit to check if semaphore is locked or not (when 0 locked when 1 locked).The lock can be removed by write 0 to this field by.." "0,1" repeat.end repeat 16. (list 0x20 0x21 0x22 0x23 0x24 0x25 0x26 0x27 0x28 0x29 0x2A 0x2B 0x2C 0x2D 0x2E 0x2F )(list 0x100 0x108 0x110 0x118 0x120 0x128 0x130 0x138 0x140 0x148 0x150 0x158 0x160 0x168 0x170 0x178 ) group.long ($2+0x200)++0x3 line.long 0x0 "SEMAG$1,SEMAphore gate. 32 bit register. update to 64Gate based on parameter configuration" bitfld.long 0x0 24. "SG0LIC,Semaphore Gate 0 Lock interrupt clear (SGLIC[7:0]) write 1 to this register will clear the lock fail interrrupt to the processor" "0,1" hexmask.long.byte 0x0 16.--23. 1. "SG0LS,Semaphore Gate 0 Lock Status (SGLS[7:0]) SG0LS=8b00001000 means the gate is locked by Processor" newline bitfld.long 0x0 8. "IESG0LF,Interrupt Enable on Semaphore Gate Lock Failure (IESGLF) When 1 MU will send interrupt to the Processer which failed to lock the semaphore gate on semaphore gate release" "0,1" bitfld.long 0x0 0. "SG0C,Can be accessed by all processors. One Processor can write 1 to SGC to request lock of this gate. Processer can read this bit to check if semaphore is locked or not (when 0 locked when 1 locked).The lock can be removed by write 0 to this field by.." "0,1" repeat.end repeat 16. (list 0x30 0x31 0x32 0x33 0x34 0x35 0x36 0x37 0x38 0x39 0x3A 0x3B 0x3C 0x3D 0x3E 0x3F )(list 0x180 0x188 0x190 0x198 0x1A0 0x1A8 0x1B0 0x1B8 0x1C0 0x1C8 0x1D0 0x1D8 0x1E0 0x1E8 0x1F0 0x1F8 ) group.long ($2+0x200)++0x3 line.long 0x0 "SEMAG$1,SEMAphore gate. 32 bit register. update to 64Gate based on parameter configuration" bitfld.long 0x0 24. "SG0LIC,Semaphore Gate 0 Lock interrupt clear (SGLIC[7:0]) write 1 to this register will clear the lock fail interrrupt to the processor" "0,1" hexmask.long.byte 0x0 16.--23. 1. "SG0LS,Semaphore Gate 0 Lock Status (SGLS[7:0]) SG0LS=8b00001000 means the gate is locked by Processor" newline bitfld.long 0x0 8. "IESG0LF,Interrupt Enable on Semaphore Gate Lock Failure (IESGLF) When 1 MU will send interrupt to the Processer which failed to lock the semaphore gate on semaphore gate release" "0,1" bitfld.long 0x0 0. "SG0C,Can be accessed by all processors. One Processor can write 1 to SGC to request lock of this gate. Processer can read this bit to check if semaphore is locked or not (when 0 locked when 1 locked).The lock can be removed by write 0 to this field by.." "0,1" repeat.end group.long 0x204++0x3 line.long 0x0 "SEMAG0PC,32 bit register up to 64 gates based on parameter configuration" bitfld.long 0x0 8. "SG0PL,Semaphore Gate 0 Permission Lock (SGPL)" "0,1" hexmask.long.byte 0x0 0.--7. 1. "SG0P,Semaphore access permission enable bit for those 8 Processers. When SGP[M]=1 access permission of Processer-M to this gate is enabled." group.long 0x20C++0x3 line.long 0x0 "SEMAG1PC,32 bit register up to 64 gates based on parameter configuration" bitfld.long 0x0 8. "SG1PL,Semaphore Gate 1 Permission Lock (SGPL)" "0,1" hexmask.long.byte 0x0 0.--7. 1. "SG1P,Semaphore access permission enable bit for those 8 Processers. When SGP[M]=1 access permission of Processer-M to this gate is enabled." group.long 0x214++0x3 line.long 0x0 "SEMAG2PC,32 bit register up to 64 gates based on parameter configuration" bitfld.long 0x0 8. "SG2PL,Semaphore Gate 2 Permission Lock (SGPL)" "0,1" hexmask.long.byte 0x0 0.--7. 1. "SG2P,Semaphore access permission enable bit for those 8 Processers. When SGP[M]=1 access permission of Processer-M to this gate is enabled." group.long 0x21C++0x3 line.long 0x0 "SEMAG3PC,32 bit register up to 64 gates based on parameter configuration" bitfld.long 0x0 8. "SG3PL,Semaphore Gate3 Permission Lock (SGPL)" "0,1" hexmask.long.byte 0x0 0.--7. 1. "SG3P,Semaphore access permission enable bit for those 8 Processers. When SGP[M]=1 access permission of Processer-M to this gate is enabled." group.long 0x224++0x3 line.long 0x0 "SEMAG4PC,32 bit register up to 64 gates based on parameter configuration" bitfld.long 0x0 8. "SG4PL,Semaphore Gate4 Permission Lock (SGPL)" "0,1" hexmask.long.byte 0x0 0.--7. 1. "SG4P,Semaphore access permission enable bit for those 8 Processers. When SGP[M]=1 access permission of Processer-M to this gate is enabled." group.long 0x22C++0x3 line.long 0x0 "SEMAG5PC,32 bit register up to 64 gates based on parameter configuration" bitfld.long 0x0 8. "SG5PL,Semaphore Gate 5 Permission Lock (SGPL)" "0,1" hexmask.long.byte 0x0 0.--7. 1. "SG5P,Semaphore access permission enable bit for those 8 Processers. When SGP[M]=1 access permission of Processer-M to this gate is enabled." group.long 0x234++0x3 line.long 0x0 "SEMAG6PC,32 bit register up to 64 gates based on parameter configuration" bitfld.long 0x0 8. "SG6PL,Semaphore Gate6 Permission Lock (SGPL)" "0,1" hexmask.long.byte 0x0 0.--7. 1. "SG6P,Semaphore access permission enable bit for those 8 Processers. When SGP[M]=1 access permission of Processer-M to this gate is enabled." group.long 0x23C++0x3 line.long 0x0 "SEMAG7PC,32 bit register up to 64 gates based on parameter configuration" bitfld.long 0x0 8. "SG7PL,Semaphore Gate7 Permission Lock (SGPL)" "0,1" hexmask.long.byte 0x0 0.--7. 1. "SG7P,Semaphore access permission enable bit for those 8 Processers. When SGP[M]=1 access permission of Processer-M to this gate is enabled." group.long 0x244++0x3 line.long 0x0 "SEMAG8PC,32 bit register up to 64 gates based on parameter configuration" bitfld.long 0x0 8. "SG8PL,Semaphore Gate 8 Permission Lock (SGPL)" "0,1" hexmask.long.byte 0x0 0.--7. 1. "SG8P,Semaphore access permission enable bit for those 8 Processers. When SGP[M]=1 access permission of Processer-M to this gate is enabled." group.long 0x24C++0x3 line.long 0x0 "SEMAG9PC,32 bit register up to 64 gates based on parameter configuration" bitfld.long 0x0 8. "SG9PL,Semaphore Gate9 Permission Lock (SGPL)" "0,1" hexmask.long.byte 0x0 0.--7. 1. "SG9P,Semaphore access permission enable bit for those 8 Processers. When SGP[M]=1 access permission of Processer-M to this gate is enabled." group.long 0x254++0x3 line.long 0x0 "SEMAG10PC,32 bit register up to 64 gates based on parameter configuration" bitfld.long 0x0 8. "SG10PL,Semaphore Gate 0 Permission Lock (SGPL)" "0,1" hexmask.long.byte 0x0 0.--7. 1. "SG10P,Semaphore access permission enable bit for those 8 Processers. When SGP[M]=1 access permission of Processer-M to this gate is enabled." group.long 0x25C++0x3 line.long 0x0 "SEMAG11PC,32 bit register up to 64 gates based on parameter configuration" bitfld.long 0x0 8. "SG11PL,Semaphore Gate 1 Permission Lock (SGPL)" "0,1" hexmask.long.byte 0x0 0.--7. 1. "SG11P,Semaphore access permission enable bit for those 8 Processers. When SGP[M]=1 access permission of Processer-M to this gate is enabled." group.long 0x264++0x3 line.long 0x0 "SEMAG12PC,32 bit register up to 64 gates based on parameter configuration" bitfld.long 0x0 8. "SG12PL,Semaphore Gate 2 Permission Lock (SGPL)" "0,1" hexmask.long.byte 0x0 0.--7. 1. "SG12P,Semaphore access permission enable bit for those 8 Processers. When SGP[M]=1 access permission of Processer-M to this gate is enabled." group.long 0x26C++0x3 line.long 0x0 "SEMAG13PC,32 bit register up to 64 gates based on parameter configuration" bitfld.long 0x0 8. "SG13PL,Semaphore Gate13 Permission Lock (SGPL)" "0,1" hexmask.long.byte 0x0 0.--7. 1. "SG13P,Semaphore access permission enable bit for those 8 Processers. When SGP[M]=1 access permission of Processer-M to this gate is enabled." group.long 0x274++0x3 line.long 0x0 "SEMAG14PC,32 bit register up to 64 gates based on parameter configuration" bitfld.long 0x0 8. "SG14PL,Semaphore Gate14 Permission Lock (SGPL)" "0,1" hexmask.long.byte 0x0 0.--7. 1. "SG14P,Semaphore access permission enable bit for those 8 Processers. When SGP[M]=1 access permission of Processer-M to this gate is enabled." group.long 0x27C++0x3 line.long 0x0 "SEMAG15PC,32 bit register up to 64 gates based on parameter configuration" bitfld.long 0x0 8. "SG15PL,Semaphore Gate 5 Permission Lock (SGPL)" "0,1" hexmask.long.byte 0x0 0.--7. 1. "SG15P,Semaphore access permission enable bit for those 8 Processers. When SGP[M]=1 access permission of Processer-M to this gate is enabled." group.long 0x284++0x3 line.long 0x0 "SEMAG16PC,32 bit register up to 64 gates based on parameter configuration" bitfld.long 0x0 8. "SG16PL,Semaphore Gate16 Permission Lock (SGPL)" "0,1" hexmask.long.byte 0x0 0.--7. 1. "SG16P,Semaphore access permission enable bit for those 8 Processers. When SGP[M]=1 access permission of Processer-M to this gate is enabled." group.long 0x28C++0x3 line.long 0x0 "SEMAG17PC,32 bit register up to 64 gates based on parameter configuration" bitfld.long 0x0 8. "SG17PL,Semaphore Gate17 Permission Lock (SGPL)" "0,1" hexmask.long.byte 0x0 0.--7. 1. "SG17P,Semaphore access permission enable bit for those 8 Processers. When SGP[M]=1 access permission of Processer-M to this gate is enabled." group.long 0x294++0x3 line.long 0x0 "SEMAG18PC,32 bit register up to 64 gates based on parameter configuration" bitfld.long 0x0 8. "SG18PL,Semaphore Gate 8 Permission Lock (SGPL)" "0,1" hexmask.long.byte 0x0 0.--7. 1. "SG18P,Semaphore access permission enable bit for those 8 Processers. When SGP[M]=1 access permission of Processer-M to this gate is enabled." group.long 0x29C++0x3 line.long 0x0 "SEMAG19PC,32 bit register up to 64 gates based on parameter configuration" bitfld.long 0x0 8. "SG19PL,Semaphore Gate19 Permission Lock (SGPL)" "0,1" hexmask.long.byte 0x0 0.--7. 1. "SG19P,Semaphore access permission enable bit for those 8 Processers. When SGP[M]=1 access permission of Processer-M to this gate is enabled." group.long 0x2A4++0x3 line.long 0x0 "SEMAG20PC,32 bit register up to 64 gates based on parameter configuration" bitfld.long 0x0 8. "SG20PL,Semaphore Gate 20 Permission Lock (SGPL)" "0,1" hexmask.long.byte 0x0 0.--7. 1. "SG20P,Semaphore access permission enable bit for those 8 Processers. When SGP[M]=1 access permission of Processer-M to this gate is enabled." group.long 0x2AC++0x3 line.long 0x0 "SEMAG21PC,32 bit register up to 64 gates based on parameter configuration" bitfld.long 0x0 8. "SG21PL,Semaphore Gate 1 Permission Lock (SGPL)" "0,1" hexmask.long.byte 0x0 0.--7. 1. "SG21P,Semaphore access permission enable bit for those 8 Processers. When SGP[M]=1 access permission of Processer-M to this gate is enabled." group.long 0x2B4++0x3 line.long 0x0 "SEMAG22PC,32 bit register up to 64 gates based on parameter configuration" bitfld.long 0x0 8. "SG22PL,Semaphore Gate 2 Permission Lock (SGPL)" "0,1" hexmask.long.byte 0x0 0.--7. 1. "SG22P,Semaphore access permission enable bit for those 8 Processers. When SGP[M]=1 access permission of Processer-M to this gate is enabled." group.long 0x2BC++0x3 line.long 0x0 "SEMAG23PC,32 bit register up to 64 gates based on parameter configuration" bitfld.long 0x0 8. "SG23PL,Semaphore Gate23 Permission Lock (SGPL)" "0,1" hexmask.long.byte 0x0 0.--7. 1. "SG23P,Semaphore access permission enable bit for those 8 Processers. When SGP[M]=1 access permission of Processer-M to this gate is enabled." group.long 0x2C4++0x3 line.long 0x0 "SEMAG24PC,32 bit register up to 64 gates based on parameter configuration" bitfld.long 0x0 8. "SG24PL,Semaphore Gate24 Permission Lock (SGPL)" "0,1" hexmask.long.byte 0x0 0.--7. 1. "SG24P,Semaphore access permission enable bit for those 8 Processers. When SGP[M]=1 access permission of Processer-M to this gate is enabled." group.long 0x2CC++0x3 line.long 0x0 "SEMAG25PC,32 bit register up to 64 gates based on parameter configuration" bitfld.long 0x0 8. "SG25PL,Semaphore Gate25 Permission Lock (SGPL)" "0,1" hexmask.long.byte 0x0 0.--7. 1. "SG25P,Semaphore access permission enable bit for those 8 Processers. When SGP[M]=1 access permission of Processer-M to this gate is enabled." group.long 0x2D4++0x3 line.long 0x0 "SEMAG26PC,32 bit register up to 64 gates based on parameter configuration" bitfld.long 0x0 8. "SG26PL,Semaphore Gate26 Permission Lock (SGPL)" "0,1" hexmask.long.byte 0x0 0.--7. 1. "SG26P,Semaphore access permission enable bit for those 8 Processers. When SGP[M]=1 access permission of Processer-M to this gate is enabled." group.long 0x2DC++0x3 line.long 0x0 "SEMAG27PC,32 bit register up to 64 gates based on parameter configuration" bitfld.long 0x0 8. "SG27PL,Semaphore Gate27 Permission Lock (SGPL)" "0,1" hexmask.long.byte 0x0 0.--7. 1. "SG27P,Semaphore access permission enable bit for those 8 Processers. When SGP[M]=1 access permission of Processer-M to this gate is enabled." group.long 0x2E4++0x3 line.long 0x0 "SEMAG28PC,32 bit register up to 64 gates based on parameter configuration" bitfld.long 0x0 8. "SG28PL,Semaphore Gate 8 Permission Lock (SGPL)" "0,1" hexmask.long.byte 0x0 0.--7. 1. "SG28P,Semaphore access permission enable bit for those 8 Processers. When SGP[M]=1 access permission of Processer-M to this gate is enabled." group.long 0x2EC++0x3 line.long 0x0 "SEMAG29PC,32 bit register up to 64 gates based on parameter configuration" bitfld.long 0x0 8. "SG29PL,Semaphore Gate29 Permission Lock (SGPL)" "0,1" hexmask.long.byte 0x0 0.--7. 1. "SG29P,Semaphore access permission enable bit for those 8 Processers. When SGP[M]=1 access permission of Processer-M to this gate is enabled." group.long 0x2F4++0x3 line.long 0x0 "SEMAG30PC,32 bit register up to 64 gates based on parameter configuration" bitfld.long 0x0 8. "SG30PL,Semaphore Gate 0 Permission Lock (SGPL)" "0,1" hexmask.long.byte 0x0 0.--7. 1. "SG30P,Semaphore access permission enable bit for those 8 Processers. When SGP[M]=1 access permission of Processer-M to this gate is enabled." group.long 0x2FC++0x3 line.long 0x0 "SEMAG31PC,32 bit register up to 64 gates based on parameter configuration" bitfld.long 0x0 8. "SG31PL,Semaphore Gate 1 Permission Lock (SGPL)" "0,1" hexmask.long.byte 0x0 0.--7. 1. "SG31P,Semaphore access permission enable bit for those 8 Processers. When SGP[M]=1 access permission of Processer-M to this gate is enabled." group.long 0x304++0x3 line.long 0x0 "SEMAG32PC,32 bit register up to 64 gates based on parameter configuration" bitfld.long 0x0 8. "SG32PL,Semaphore Gate 2 Permission Lock (SGPL)" "0,1" hexmask.long.byte 0x0 0.--7. 1. "SG32P,Semaphore access permission enable bit for those 8 Processers. When SGP[M]=1 access permission of Processer-M to this gate is enabled." group.long 0x30C++0x3 line.long 0x0 "SEMAG33PC,32 bit register up to 64 gates based on parameter configuration" bitfld.long 0x0 8. "SG33PL,Semaphore Gate33 Permission Lock (SGPL)" "0,1" hexmask.long.byte 0x0 0.--7. 1. "SG33P,Semaphore access permission enable bit for those 8 Processers. When SGP[M]=1 access permission of Processer-M to this gate is enabled." group.long 0x314++0x3 line.long 0x0 "SEMAG34PC,32 bit register up to 64 gates based on parameter configuration" bitfld.long 0x0 8. "SG34PL,Semaphore Gate34 Permission Lock (SGPL)" "0,1" hexmask.long.byte 0x0 0.--7. 1. "SG34P,Semaphore access permission enable bit for those 8 Processers. When SGP[M]=1 access permission of Processer-M to this gate is enabled." group.long 0x31C++0x3 line.long 0x0 "SEMAG35PC,32 bit register up to 64 gates based on parameter configuration" bitfld.long 0x0 8. "SG35PL,Semaphore Gate 5 Permission Lock (SGPL)" "0,1" hexmask.long.byte 0x0 0.--7. 1. "SG35P,Semaphore access permission enable bit for those 8 Processers. When SGP[M]=1 access permission of Processer-M to this gate is enabled." group.long 0x324++0x3 line.long 0x0 "SEMAG36PC,32 bit register up to 64 gates based on parameter configuration" bitfld.long 0x0 8. "SG36PL,Semaphore Gate36 Permission Lock (SGPL)" "0,1" hexmask.long.byte 0x0 0.--7. 1. "SG36P,Semaphore access permission enable bit for those 8 Processers. When SGP[M]=1 access permission of Processer-M to this gate is enabled." group.long 0x32C++0x3 line.long 0x0 "SEMAG37PC,32 bit register up to 64 gates based on parameter configuration" bitfld.long 0x0 8. "SG37PL,Semaphore Gate37 Permission Lock (SGPL)" "0,1" hexmask.long.byte 0x0 0.--7. 1. "SG37P,Semaphore access permission enable bit for those 8 Processers. When SGP[M]=1 access permission of Processer-M to this gate is enabled." group.long 0x334++0x3 line.long 0x0 "SEMAG38PC,32 bit register up to 64 gates based on parameter configuration" bitfld.long 0x0 8. "SG38PL,Semaphore Gate 8 Permission Lock (SGPL)" "0,1" hexmask.long.byte 0x0 0.--7. 1. "SG38P,Semaphore access permission enable bit for those 8 Processers. When SGP[M]=1 access permission of Processer-M to this gate is enabled." group.long 0x33C++0x3 line.long 0x0 "SEMAG39PC,32 bit register up to 64 gates based on parameter configuration" bitfld.long 0x0 8. "SG39PL,Semaphore Gate39 Permission Lock (SGPL)" "0,1" hexmask.long.byte 0x0 0.--7. 1. "SG39P,Semaphore access permission enable bit for those 8 Processers. When SGP[M]=1 access permission of Processer-M to this gate is enabled." group.long 0x344++0x3 line.long 0x0 "SEMAG40PC,32 bit register up to 64 gates based on parameter configuration" bitfld.long 0x0 8. "SG40PL,Semaphore Gate 0 Permission Lock (SGPL)" "0,1" hexmask.long.byte 0x0 0.--7. 1. "SG40P,Semaphore access permission enable bit for those 8 Processers. When SGP[M]=1 access permission of Processer-M to this gate is enabled." group.long 0x34C++0x3 line.long 0x0 "SEMAG41PC,32 bit register up to 64 gates based on parameter configuration" bitfld.long 0x0 8. "SG41PL,Semaphore Gate 1 Permission Lock (SGPL)" "0,1" hexmask.long.byte 0x0 0.--7. 1. "SG41P,Semaphore access permission enable bit for those 8 Processers. When SGP[M]=1 access permission of Processer-M to this gate is enabled." group.long 0x354++0x3 line.long 0x0 "SEMAG42PC,32 bit register up to 64 gates based on parameter configuration" bitfld.long 0x0 8. "SG42PL,Semaphore Gate 2 Permission Lock (SGPL)" "0,1" hexmask.long.byte 0x0 0.--7. 1. "SG42P,Semaphore access permission enable bit for those 8 Processers. When SGP[M]=1 access permission of Processer-M to this gate is enabled." group.long 0x35C++0x3 line.long 0x0 "SEMAG43PC,32 bit register up to 64 gates based on parameter configuration" bitfld.long 0x0 8. "SG43PL,Semaphore Gate43 Permission Lock (SGPL)" "0,1" hexmask.long.byte 0x0 0.--7. 1. "SG43P,Semaphore access permission enable bit for those 8 Processers. When SGP[M]=1 access permission of Processer-M to this gate is enabled." group.long 0x364++0x3 line.long 0x0 "SEMAG44PC,32 bit register up to 64 gates based on parameter configuration" bitfld.long 0x0 8. "SG44PL,Semaphore Gate44 Permission Lock (SGPL)" "0,1" hexmask.long.byte 0x0 0.--7. 1. "SG44P,Semaphore access permission enable bit for those 8 Processers. When SGP[M]=1 access permission of Processer-M to this gate is enabled." group.long 0x36C++0x3 line.long 0x0 "SEMAG45PC,32 bit register up to 64 gates based on parameter configuration" bitfld.long 0x0 8. "SG45PL,Semaphore Gate 5 Permission Lock (SGPL)" "0,1" hexmask.long.byte 0x0 0.--7. 1. "SG45P,Semaphore access permission enable bit for those 8 Processers. When SGP[M]=1 access permission of Processer-M to this gate is enabled." group.long 0x374++0x3 line.long 0x0 "SEMAG46PC,32 bit register up to 64 gates based on parameter configuration" bitfld.long 0x0 8. "SG46PL,Semaphore Gate46 Permission Lock (SGPL)" "0,1" hexmask.long.byte 0x0 0.--7. 1. "SG46P,Semaphore access permission enable bit for those 8 Processers. When SGP[M]=1 access permission of Processer-M to this gate is enabled." group.long 0x37C++0x3 line.long 0x0 "SEMAG47PC,32 bit register up to 64 gates based on parameter configuration" bitfld.long 0x0 8. "SG47PL,Semaphore Gate47 Permission Lock (SGPL)" "0,1" hexmask.long.byte 0x0 0.--7. 1. "SG47P,Semaphore access permission enable bit for those 8 Processers. When SGP[M]=1 access permission of Processer-M to this gate is enabled." group.long 0x384++0x3 line.long 0x0 "SEMAG48PC,32 bit register up to 64 gates based on parameter configuration" bitfld.long 0x0 8. "SG48PL,Semaphore Gate 8 Permission Lock (SGPL)" "0,1" hexmask.long.byte 0x0 0.--7. 1. "SG48P,Semaphore access permission enable bit for those 8 Processers. When SGP[M]=1 access permission of Processer-M to this gate is enabled." group.long 0x38C++0x3 line.long 0x0 "SEMAG49PC,32 bit register up to 64 gates based on parameter configuration" bitfld.long 0x0 8. "SG49PL,Semaphore Gate49 Permission Lock (SGPL)" "0,1" hexmask.long.byte 0x0 0.--7. 1. "SG49P,Semaphore access permission enable bit for those 8 Processers. When SGP[M]=1 access permission of Processer-M to this gate is enabled." group.long 0x394++0x3 line.long 0x0 "SEMAG50PC,32 bit register up to 64 gates based on parameter configuration" bitfld.long 0x0 8. "SG50PL,Semaphore Gate 0 Permission Lock (SGPL)" "0,1" hexmask.long.byte 0x0 0.--7. 1. "SG50P,Semaphore access permission enable bit for those 8 Processers. When SGP[M]=1 access permission of Processer-M to this gate is enabled." group.long 0x39C++0x3 line.long 0x0 "SEMAG51PC,32 bit register up to 64 gates based on parameter configuration" bitfld.long 0x0 8. "SG51PL,Semaphore Gate 1 Permission Lock (SGPL)" "0,1" hexmask.long.byte 0x0 0.--7. 1. "SG51P,Semaphore access permission enable bit for those 8 Processers. When SGP[M]=1 access permission of Processer-M to this gate is enabled." group.long 0x3A4++0x3 line.long 0x0 "SEMAG52PC,32 bit register up to 64 gates based on parameter configuration" bitfld.long 0x0 8. "SG52PL,Semaphore Gate 2 Permission Lock (SGPL)" "0,1" hexmask.long.byte 0x0 0.--7. 1. "SG52P,Semaphore access permission enable bit for those 8 Processers. When SGP[M]=1 access permission of Processer-M to this gate is enabled." group.long 0x3AC++0x3 line.long 0x0 "SEMAG53PC,32 bit register up to 64 gates based on parameter configuration" bitfld.long 0x0 8. "SG53PL,Semaphore Gate53 Permission Lock (SGPL)" "0,1" hexmask.long.byte 0x0 0.--7. 1. "SG53P,Semaphore access permission enable bit for those 8 Processers. When SGP[M]=1 access permission of Processer-M to this gate is enabled." group.long 0x3B4++0x3 line.long 0x0 "SEMAG54PC,32 bit register up to 64 gates based on parameter configuration" bitfld.long 0x0 8. "SG54PL,Semaphore Gate54 Permission Lock (SGPL)" "0,1" hexmask.long.byte 0x0 0.--7. 1. "SG54P,Semaphore access permission enable bit for those 8 Processers. When SGP[M]=1 access permission of Processer-M to this gate is enabled." group.long 0x3BC++0x3 line.long 0x0 "SEMAG55PC,32 bit register up to 64 gates based on parameter configuration" bitfld.long 0x0 8. "SG55PL,Semaphore Gate 5 Permission Lock (SGPL)" "0,1" hexmask.long.byte 0x0 0.--7. 1. "SG55P,Semaphore access permission enable bit for those 8 Processers. When SGP[M]=1 access permission of Processer-M to this gate is enabled." group.long 0x3C4++0x3 line.long 0x0 "SEMAG56PC,32 bit register up to 64 gates based on parameter configuration" bitfld.long 0x0 8. "SG56PL,Semaphore Gate56 Permission Lock (SGPL)" "0,1" hexmask.long.byte 0x0 0.--7. 1. "SG56P,Semaphore access permission enable bit for those 8 Processers. When SGP[M]=1 access permission of Processer-M to this gate is enabled." group.long 0x3CC++0x3 line.long 0x0 "SEMAG57PC,32 bit register up to 64 gates based on parameter configuration" bitfld.long 0x0 8. "SG57PL,Semaphore Gate57 Permission Lock (SGPL)" "0,1" hexmask.long.byte 0x0 0.--7. 1. "SG57P,Semaphore access permission enable bit for those 8 Processers. When SGP[M]=1 access permission of Processer-M to this gate is enabled." group.long 0x3D4++0x3 line.long 0x0 "SEMAG58PC,32 bit register up to 64 gates based on parameter configuration" bitfld.long 0x0 8. "SG58PL,Semaphore Gate 8 Permission Lock (SGPL)" "0,1" hexmask.long.byte 0x0 0.--7. 1. "SG58P,Semaphore access permission enable bit for those 8 Processers. When SGP[M]=1 access permission of Processer-M to this gate is enabled." group.long 0x3DC++0x3 line.long 0x0 "SEMAG59PC,32 bit register up to 64 gates based on parameter configuration" bitfld.long 0x0 8. "SG59PL,Semaphore Gate59 Permission Lock (SGPL)" "0,1" hexmask.long.byte 0x0 0.--7. 1. "SG59P,Semaphore access permission enable bit for those 8 Processers. When SGP[M]=1 access permission of Processer-M to this gate is enabled." group.long 0x3E4++0x3 line.long 0x0 "SEMAG60PC,32 bit register up to 64 gates based on parameter configuration" bitfld.long 0x0 8. "SG60PL,Semaphore Gate 0 Permission Lock (SGPL)" "0,1" hexmask.long.byte 0x0 0.--7. 1. "SG60P,Semaphore access permission enable bit for those 8 Processers. When SGP[M]=1 access permission of Processer-M to this gate is enabled." group.long 0x3EC++0x3 line.long 0x0 "SEMAG61PC,32 bit register up to 64 gates based on parameter configuration" bitfld.long 0x0 8. "SG61PL,Semaphore Gate 1 Permission Lock (SGPL)" "0,1" hexmask.long.byte 0x0 0.--7. 1. "SG61P,Semaphore access permission enable bit for those 8 Processers. When SGP[M]=1 access permission of Processer-M to this gate is enabled." group.long 0x3F4++0x3 line.long 0x0 "SEMAG62PC,32 bit register up to 64 gates based on parameter configuration" bitfld.long 0x0 8. "SG62PL,Semaphore Gate 2 Permission Lock (SGPL)" "0,1" hexmask.long.byte 0x0 0.--7. 1. "SG62P,Semaphore access permission enable bit for those 8 Processers. When SGP[M]=1 access permission of Processer-M to this gate is enabled." group.long 0x3FC++0xF line.long 0x0 "SEMAG63PC,32 bit register up to 64 gates based on parameter configuration" bitfld.long 0x0 8. "SG63PL,Semaphore Gate63 Permission Lock (SGPL)" "0,1" hexmask.long.byte 0x0 0.--7. 1. "SG63P,Semaphore access permission enable bit for those 8 Processers. When SGP[M]=1 access permission of Processer-M to this gate is enabled." line.long 0x4 "SGR,semaphone gate reset" bitfld.long 0x4 25. "GSGREL,Global Semaphore Gate Reset Enable Lock (GSGREL) sticky bit which locks" "0,1" bitfld.long 0x4 24. "GSGRE,Global Semaphore Gate Reset Enable (GSGRE) when 1 GSGR is enabled when 0 GSGT is disabled" "0,1" hexmask.long.byte 0x4 16.--23. 1. "RESERVED,Reserved bit" newline hexmask.long.byte 0x4 8.--15. 1. "GSGR,When writes to 1 semaphore gates which locked by corresponding processor are released." bitfld.long 0x4 0. "SGR,Semaphore Gate Reset. When writes to 1 all semaphore gates which locked by current processor are released each processor has a SGR" "0,1" line.long 0x8 "SGI0,Semaphore gates status change interrupt status-0" hexmask.long 0x8 0.--31. 1. "SGI0,interrupt status of Semaphore gate[31:0].Hardware set when registered interrupt notification of related semaphore gate is released. Software can clear this interrupt by writes 1 to related bit. Be noted that if SGI0=32hFFFF_FFFF writing.." line.long 0xC "SGI1,semaphore gate status change interrupt status-1" hexmask.long 0xC 0.--31. 1. "SGI1,interrupt status of Semaphore gate[63:32].Hardware set when registered interrupt notification of related semaphore gate is released. Software can clear this interrupt by writes 1 to related bit. Be noted that if SGI0=32hFFFF_FFFF writing.." group.long 0x500++0x1F line.long 0x0 "CPU0_MASTERID,CPU0_MASTERID" bitfld.long 0x0 31. "CPU0_MASTER_ID3_LOCK,CPU0_MASTER_ID3_LOCK" "0,1" hexmask.long.byte 0x0 24.--30. 1. "CPU0_MASTER_ID3,CPU0_MASTER_ID3" bitfld.long 0x0 23. "CPU0_MASTER_ID2_LOCK,CPU0_MASTER_ID2_LOCK" "0,1" hexmask.long.byte 0x0 16.--22. 1. "CPU0_MASTER_ID2,CPU0_MASTER_ID2" newline bitfld.long 0x0 15. "CPU0_MASTER_ID1_LOCK,CPU0_MASTER_ID1_LOCK" "0,1" hexmask.long.byte 0x0 8.--14. 1. "CPU0_MASTER_ID1,CPU0_MASTER_ID1" bitfld.long 0x0 7. "CPU0_MASTER_ID0_LOCK,CPU0_MASTER_ID0_LOCK" "0,1" hexmask.long.byte 0x0 0.--6. 1. "CPU0_MASTER_ID0,CPU0_MASTER_ID0" line.long 0x4 "CPU1_MASTERID,CPU1_MASTERID" bitfld.long 0x4 31. "CPU1_MASTER_ID3_LOCK,CPU1_MASTER_ID3_LOCK" "0,1" hexmask.long.byte 0x4 24.--30. 1. "CPU1_MASTER_ID3,CPU1_MASTER_ID3" bitfld.long 0x4 23. "CPU1_MASTER_ID2_LOCK,CPU1_MASTER_ID2_LOCK" "0,1" hexmask.long.byte 0x4 16.--22. 1. "CPU1_MASTER_ID2,CPU1_MASTER_ID2" newline bitfld.long 0x4 15. "CPU1_MASTER_ID1_LOCK,CPU1_MASTER_ID1_LOCK" "0,1" hexmask.long.byte 0x4 8.--14. 1. "CPU1_MASTER_ID1,CPU1_MASTER_ID1" bitfld.long 0x4 7. "CPU1_MASTER_ID0_LOCK,CPU1_MASTER_ID0_LOCK" "0,1" hexmask.long.byte 0x4 0.--6. 1. "CPU1_MASTER_ID0,CPU1_MASTER_ID0" line.long 0x8 "CPU2_MASTERID,CPU2_MASTERID" bitfld.long 0x8 31. "CPU2_MASTER_ID3_LOCK,CPU2_MASTER_ID3_LOCK" "0,1" hexmask.long.byte 0x8 24.--30. 1. "CPU2_MASTER_ID3,CPU2_MASTER_ID3" bitfld.long 0x8 23. "CPU2_MASTER_ID2_LOCK,CPU2_MASTER_ID2_LOCK" "0,1" hexmask.long.byte 0x8 16.--22. 1. "CPU2_MASTER_ID2,CPU2_MASTER_ID2" newline bitfld.long 0x8 15. "CPU2_MASTER_ID1_LOCK,CPU2_MASTER_ID1_LOCK" "0,1" hexmask.long.byte 0x8 8.--14. 1. "CPU2_MASTER_ID1,CPU2_MASTER_ID1" bitfld.long 0x8 7. "CPU2_MASTER_ID0_LOCK,CPU2_MASTER_ID0_LOCK" "0,1" hexmask.long.byte 0x8 0.--6. 1. "CPU2_MASTER_ID0,CPU2_MASTER_ID0" line.long 0xC "CPU3_MASTERID,CPU3_MASTERID" bitfld.long 0xC 31. "CPU3_MASTER_ID3_LOCK,CPU3_MASTER_ID3_LOCK" "0,1" hexmask.long.byte 0xC 24.--30. 1. "CPU3_MASTER_ID3,CPU3_MASTER_ID3" bitfld.long 0xC 23. "CPU3_MASTER_ID2_LOCK,CPU3_MASTER_ID2_LOCK" "0,1" hexmask.long.byte 0xC 16.--22. 1. "CPU3_MASTER_ID2,CPU3_MASTER_ID2" newline bitfld.long 0xC 15. "CPU3_MASTER_ID1_LOCK,CPU3_MASTER_ID1_LOCK" "0,1" hexmask.long.byte 0xC 8.--14. 1. "CPU3_MASTER_ID1,CPU3_MASTER_ID1" bitfld.long 0xC 7. "CPU3_MASTER_ID0_LOCK,CPU3_MASTER_ID0_LOCK" "0,1" hexmask.long.byte 0xC 0.--6. 1. "CPU3_MASTER_ID0,CPU3_MASTER_ID0" line.long 0x10 "CPU4_MASTERID,CPU4_MASTERID" bitfld.long 0x10 31. "CPU4_MASTER_ID3_LOCK,CPU4_MASTER_ID3_LOCK" "0,1" hexmask.long.byte 0x10 24.--30. 1. "CPU4_MASTER_ID3,CPU4_MASTER_ID3" bitfld.long 0x10 23. "CPU4_MASTER_ID2_LOCK,CPU4_MASTER_ID2_LOCK" "0,1" hexmask.long.byte 0x10 16.--22. 1. "CPU4_MASTER_ID2,CPU4_MASTER_ID2" newline bitfld.long 0x10 15. "CPU4_MASTER_ID1_LOCK,CPU4_MASTER_ID1_LOCK" "0,1" hexmask.long.byte 0x10 8.--14. 1. "CPU4_MASTER_ID1,CPU4_MASTER_ID1" bitfld.long 0x10 7. "CPU4_MASTER_ID0_LOCK,CPU4_MASTER_ID0_LOCK" "0,1" hexmask.long.byte 0x10 0.--6. 1. "CPU4_MASTER_ID0,CPU4_MASTER_ID0" line.long 0x14 "CPU5_MASTERID,CPU5_MASTERID" bitfld.long 0x14 31. "CPU5_MASTER_ID3_LOCK,CPU5_MASTER_ID3_LOCK" "0,1" hexmask.long.byte 0x14 24.--30. 1. "CPU5_MASTER_ID3,CPU5_MASTER_ID3" bitfld.long 0x14 23. "CPU5_MASTER_ID2_LOCK,CPU5_MASTER_ID2_LOCK" "0,1" hexmask.long.byte 0x14 16.--22. 1. "CPU5_MASTER_ID2,CPU5_MASTER_ID2" newline bitfld.long 0x14 15. "CPU5_MASTER_ID1_LOCK,CPU5_MASTER_ID1_LOCK" "0,1" hexmask.long.byte 0x14 8.--14. 1. "CPU5_MASTER_ID1,CPU5_MASTER_ID1" bitfld.long 0x14 7. "CPU5_MASTER_ID0_LOCK,CPU5_MASTER_ID0_LOCK" "0,1" hexmask.long.byte 0x14 0.--6. 1. "CPU5_MASTER_ID0,CPU5_MASTER_ID0" line.long 0x18 "CPU6_MASTERID,CPU6_MASTERID" bitfld.long 0x18 31. "CPU6_MASTER_ID3_LOCK,CPU6_MASTER_ID3_LOCK" "0,1" hexmask.long.byte 0x18 24.--30. 1. "CPU6_MASTER_ID3,CPU6_MASTER_ID3" bitfld.long 0x18 23. "CPU6_MASTER_ID2_LOCK,CPU6_MASTER_ID2_LOCK" "0,1" hexmask.long.byte 0x18 16.--22. 1. "CPU6_MASTER_ID2,CPU6_MASTER_ID2" newline bitfld.long 0x18 15. "CPU6_MASTER_ID1_LOCK,CPU6_MASTER_ID1_LOCK" "0,1" hexmask.long.byte 0x18 8.--14. 1. "CPU6_MASTER_ID1,CPU6_MASTER_ID1" bitfld.long 0x18 7. "CPU6_MASTER_ID0_LOCK,CPU6_MASTER_ID0_LOCK" "0,1" hexmask.long.byte 0x18 0.--6. 1. "CPU6_MASTER_ID0,CPU6_MASTER_ID0" line.long 0x1C "CPU7_MASTERID,CPU7_MASTERID" bitfld.long 0x1C 31. "CPU7_MASTER_ID3_LOCK,CPU7_MASTER_ID3_LOCK" "0,1" hexmask.long.byte 0x1C 24.--30. 1. "CPU7_MASTER_ID3,CPU7_MASTER_ID3" bitfld.long 0x1C 23. "CPU7_MASTER_ID2_LOCK,CPU7_MASTER_ID2_LOCK" "0,1" hexmask.long.byte 0x1C 16.--22. 1. "CPU7_MASTER_ID2,CPU7_MASTER_ID2" newline bitfld.long 0x1C 15. "CPU7_MASTER_ID1_LOCK,CPU7_MASTER_ID1_LOCK" "0,1" hexmask.long.byte 0x1C 8.--14. 1. "CPU7_MASTER_ID1,CPU7_MASTER_ID1" bitfld.long 0x1C 7. "CPU7_MASTER_ID0_LOCK,CPU7_MASTER_ID0_LOCK" "0,1" hexmask.long.byte 0x1C 0.--6. 1. "CPU7_MASTER_ID0,CPU7_MASTER_ID0" rgroup.long 0x1000++0x3 line.long 0x0 "TX_BUFFER,the TX BUFFER . same for all CPUs" rgroup.long 0x2000++0x3 line.long 0x0 "RX_CPU0_BUFFER,the RX CPU0 buffer address" rgroup.long 0x3000++0x3 line.long 0x0 "RX_CPU1_BUFFER,the RX CPU1 buffer address" rgroup.long 0x4000++0x3 line.long 0x0 "RX_CPU2_BUFFER,the RX CPU2 buffer address" rgroup.long 0x5000++0x3 line.long 0x0 "RX_CPU3_BUFFER,the RX CPU3 buffer address" rgroup.long 0x6000++0x3 line.long 0x0 "RX_CPU4_BUFFER,the RX CPU4 buffer address" rgroup.long 0x7000++0x3 line.long 0x0 "RX_CPU5_BUFFER,the RX CPU5 buffer address" rgroup.long 0x8000++0x3 line.long 0x0 "RX_CPU6_BUFFER,the RX CPU6 buffer address" rgroup.long 0x9000++0x3 line.long 0x0 "RX_CPU7_BUFFER,the RX CPU7 buffer address" elif (CORENAME()=="CORTEXA55") base ad:0x34040000 group.long 0x0++0xB line.long 0x0 "TMH0,Transmitter Message Header(TMH0). 32 bit register. each processor has a TMH0" hexmask.long.byte 0x0 24.--31. 1. "MID,Message Index (MID[7:0]) as MU only support 4 outstanding messages to each one of those other processers only MID[1:0] is used for physical message index decoding" hexmask.long.byte 0x0 16.--23. 1. "MDP,Message Destination Processer (MDP) of this message. E.g. when MDP[7:0] = 10000001 this message is meant to be received by processer-0 and processer-7. To unify programming model processer which initiates this message is also encoded in MAB[7:0].." hexmask.long.byte 0x0 12.--15. 1. "MBM,message buffer mask(MBM) each bit of MBM represents the MB which are used for transferring this message. e.g. MBM[3:0] = b0101 means that the message is stored in MB0 and MB2" bitfld.long 0x0 11. "TXUSE_MB,whether this messge buffer(MB) are used in this message" "0,1" newline hexmask.long.word 0x0 0.--10. 1. "TXMES_LEN,Message length(ML) 1x2 to 2048 x 2 Byte" line.long 0x4 "TMH1,Transmitter Message Header(TMH1). 32 bit register. each processor has a TMH1" hexmask.long 0x4 0.--31. 1. "TMH1,side-band message information which is user defined.Useful in short messaging which doesnot need large message buffer" line.long 0x8 "TMH2,Transmitter Message Header(TMH2). 32 bit register. each processor has a TMH2" hexmask.long 0x8 0.--31. 1. "TMH2,side-band message information which is user defined.Useful in short messaging which doesnot need large message buffer" repeat 4. (list 0x0 0x1 0x2 0x3 )(list 0x0 0x4 0x8 0xC ) group.long ($2+0xC)++0x3 line.long 0x0 "TMC$1,Transmitter Message Control(TMC): 32bit register each processor has 4 TMC" hexmask.long.byte 0x0 16.--23. 1. "TMC0_WAK_REQ,self-cleared. When set to 1 wakeup interrupt to corresponding processer is initiated" bitfld.long 0x0 8. "TMC0_MSG_CANCEL,Self cleared controls message interrupt to other processer. E.g. when set to 1 message interrupt to processer as described in MDP and MID are cleared. In the meantime MB allocated for this message is free" "0,1" newline bitfld.long 0x0 0. "TMC0_MSG_SEND,When Write 1 the messaging interrupts to other processers are asserted e.g. the message are sent. when read the status will be cleared when message are received by all destination processors." "0,1" repeat.end rgroup.long 0x1C++0x3 line.long 0x0 "TMS,32-bit register each processor has a TMS" hexmask.long 0x0 0.--31. 1. "TMS,TMS[31:0] Message In Transfer status MIT[M][N] where M <8 N<4.Each bit represents message-N which transfer from processer-M is sent out.This field is set by message initiator.Clear by message receiver by writing 1 to transfer acknowledge (TACK).." group.long 0x20++0x3 line.long 0x0 "TPWES,Transmitter Proccessor wakeup event status(TPWES). 32 bit register each processor has a TPWES" hexmask.long.byte 0x0 0.--7. 1. "TPWES,wakeup status. TPWES[M] = 1 means that related processer-M Will be cleared by destination processer reset even or writing 1 to WACK register." wgroup.long 0x24++0x3 line.long 0x0 "RMC,32-bit register. each processor has a RMC" hexmask.long 0x0 0.--31. 1. "RMC,Message acknowledgement TACK[M][N] where M<8 N<4. Self-cleared when sets 1to TACK[M][N] message-N interrupts from processer-M are cleared." group.long 0x28++0x7 line.long 0x0 "RWC,32bit register.each processor has a RWC" hexmask.long.byte 0x0 8.--15. 1. "WEM,processer Wakeup Event Mask (WEM). When set wakeup event from corresponding processer is masked" bitfld.long 0x0 0. "WACK,RWC processer Wakeup Acknowledgement(WACK). Self-cleared when set all interrupt from other processers are cleared" "0,1" line.long 0x4 "CPU0_MSG0_RMH0,receiver message header0(RMH0) . each processor has (NumberOfProcessor)x4 RMH0" hexmask.long.byte 0x4 24.--31. 1. "CPU0_MSG0_RMH0,RMH[31:26] could be used to transfer the message RMH[25:24] is actually the message index" rbitfld.long 0x4 16. "CPU0_MSG0_VLD,message valid(MV) of this message e.g. when MV = 1 this message is meant to be received by the processor" "0,1" hexmask.long.byte 0x4 12.--15. 1. "CPU0_MSG0_MBM,Message Buffer Mask(MBM) each bit of MBM[3:0] represents the MB which are used for transferring this message. e.g. MBM[3:0] = 4b0101 means that the message is stored in MB0 and MB2" newline rbitfld.long 0x4 11. "CPU0_MSG0_USE_MB,whether this Message Buffer (MB) are used in this message" "0,1" hexmask.long.word 0x4 0.--10. 1. "CPU0_MSG0_LEN,Message Length (ML) 1x2 to 2048x2Byte" rgroup.long 0x30++0x7 line.long 0x0 "CPU0_MSG0_RMH1,Receiver Message header1(RMH1): 32 bit register each processor has (NumberOfProcessor)x4 RMH1" hexmask.long 0x0 0.--31. 1. "CPU0_MSG0_RMH1,side-band message information which is user defined.Useful in short messaging which doesnot need large message buffer" line.long 0x4 "CPU0_MSG0_RMH2,Receiver Message header2(RMH2): 32 bit register each processor has (NumberOfProcessor)x4 RMH2" hexmask.long 0x4 0.--31. 1. "CPU0_MSG0_RMH2,side-band message information which is user defined.Useful in short messaging which doesnot need large message buffer" group.long 0x38++0x3 line.long 0x0 "CPU0_MSG1_RMH0,receiver message header0(RMH0) . each processor has (NumberOfProcessor)x4 RMH0" hexmask.long.byte 0x0 24.--31. 1. "CPU0_MSG1_RMH0,RMH[31:26] could be used to transfer the message RMH[25:24] is actually the message index" rbitfld.long 0x0 16. "CPU0_MSG1_VLD,message valid(MV) of this message e.g. when MV = 1 this message is meant to be received by the processor" "0,1" hexmask.long.byte 0x0 12.--15. 1. "CPU0_MSG1_MBM,Message Buffer Mask(MBM) each bit of MBM[3:0] represents the MB which are used for transferring this message. e.g. MBM[3:0] = 4b0101 means that the message is stored in MB0 and MB2" newline rbitfld.long 0x0 11. "CPU0_MSG1_USE_MB,whether this Message Buffer (MB) are used in this message" "0,1" hexmask.long.word 0x0 0.--10. 1. "CPU0_MSG1_LEN,Message Length (ML) 1x2 to 2048x2Byte" rgroup.long 0x3C++0x7 line.long 0x0 "CPU0_MSG1_RMH1,Receiver Message header1(RMH1): 32 bit register each processor has (NumberOfProcessor)x4 RMH1" hexmask.long 0x0 0.--31. 1. "CPU0_MSG1_RMH1,side-band message information which is user defined.Useful in short messaging which doesnot need large message buffer" line.long 0x4 "CPU0_MSG1_RMH2,Receiver Message header2(RMH2): 32 bit register each processor has (NumberOfProcessor)x4 RMH2" hexmask.long 0x4 0.--31. 1. "CPU0_MSG1_RMH2,side-band message information which is user defined.Useful in short messaging which doesnot need large message buffer" group.long 0x44++0x3 line.long 0x0 "CPU0_MSG2_RMH0,receiver message header0(RMH0) . each processor has (NumberOfProcessor)x4 RMH0" hexmask.long.byte 0x0 24.--31. 1. "CPU0_MSG2_RMH0,RMH[31:26] could be used to transfer the message RMH[25:24] is actually the message index" rbitfld.long 0x0 16. "CPU0_MSG2_VLD,message valid(MV) of this message e.g. when MV = 1 this message is meant to be received by the processor" "0,1" hexmask.long.byte 0x0 12.--15. 1. "CPU0_MSG2_MBM,Message Buffer Mask(MBM) each bit of MBM[3:0] represents the MB which are used for transferring this message. e.g. MBM[3:0] = 4b0101 means that the message is stored in MB0 and MB2" newline rbitfld.long 0x0 11. "CPU0_MSG2_USE_MB,whether this Message Buffer (MB) are used in this message" "0,1" hexmask.long.word 0x0 0.--10. 1. "CPU0_MSG2_LEN,Message Length (ML) 1x2 to 2048x2Byte" rgroup.long 0x48++0x7 line.long 0x0 "CPU0_MSG2_RMH1,Receiver Message header1(RMH1): 32 bit register each processor has (NumberOfProcessor)x4 RMH1" hexmask.long 0x0 0.--31. 1. "CPU0_MSG2_RMH1,side-band message information which is user defined.Useful in short messaging which doesnot need large message buffer" line.long 0x4 "CPU0_MSG2_RMH2,Receiver Message header2(RMH2): 32 bit register each processor has (NumberOfProcessor)x4 RMH2" hexmask.long 0x4 0.--31. 1. "CPU0_MSG2_RMH2,side-band message information which is user defined.Useful in short messaging which doesnot need large message buffer" group.long 0x50++0x3 line.long 0x0 "CPU0_MSG3_RMH0,receiver message header0(RMH0) . each processor has (NumberOfProcessor)x4 RMH0" hexmask.long.byte 0x0 24.--31. 1. "CPU0_MSG3_RMH0,RMH[31:26] could be used to transfer the message RMH[25:24] is actually the message index" rbitfld.long 0x0 16. "CPU0_MSG3_VLD,message valid(MV) of this message e.g. when MV = 1 this message is meant to be received by the processor" "0,1" hexmask.long.byte 0x0 12.--15. 1. "CPU0_MSG3_MBM,Message Buffer Mask(MBM) each bit of MBM[3:0] represents the MB which are used for transferring this message. e.g. MBM[3:0] = 4b0101 means that the message is stored in MB0 and MB2" newline rbitfld.long 0x0 11. "CPU0_MSG3_USE_MB,whether this Message Buffer (MB) are used in this message" "0,1" hexmask.long.word 0x0 0.--10. 1. "CPU0_MSG3_LEN,Message Length (ML) 1x2 to 2048x2Byte" rgroup.long 0x54++0x7 line.long 0x0 "CPU0_MSG3_RMH1,Receiver Message header1(RMH1): 32 bit register each processor has (NumberOfProcessor)x4 RMH1" hexmask.long 0x0 0.--31. 1. "CPU0_MSG3_RMH1,side-band message information which is user defined.Useful in short messaging which doesnot need large message buffer" line.long 0x4 "CPU0_MSG3_RMH2,Receiver Message header2(RMH2): 32 bit register each processor has (NumberOfProcessor)x4 RMH2" hexmask.long 0x4 0.--31. 1. "CPU0_MSG3_RMH2,side-band message information which is user defined.Useful in short messaging which doesnot need large message buffer" group.long 0x5C++0x3 line.long 0x0 "CPU1_MSG0_RMH0,receiver message header0(RMH0) . each processor has (NumberOfProcessor)x4 RMH0" hexmask.long.byte 0x0 24.--31. 1. "CPU1_MSG0_RMH0,RMH[31:26] could be used to transfer the message RMH[25:24] is actually the message index" rbitfld.long 0x0 16. "CPU1_MSG0_VLD,message valid(MV) of this message e.g. when MV = 1 this message is meant to be received by the processor" "0,1" hexmask.long.byte 0x0 12.--15. 1. "CPU1_MSG0_MBM,Message Buffer Mask(MBM) each bit of MBM[3:0] represents the MB which are used for transferring this message. e.g. MBM[3:0] = 4b0101 means that the message is stored in MB0 and MB2" newline rbitfld.long 0x0 11. "CPU1_MSG0_USE_MB,whether this Message Buffer (MB) are used in this message" "0,1" hexmask.long.word 0x0 0.--10. 1. "CPU1_MSG0_LEN,Message Length (ML) 1x2 to 2048x2Byte" rgroup.long 0x60++0x7 line.long 0x0 "CPU1_MSG0_RMH1,Receiver Message header1(RMH1): 32 bit register each processor has (NumberOfProcessor)x4 RMH1" hexmask.long 0x0 0.--31. 1. "CPU1_MSG0_RMH1,side-band message information which is user defined.Useful in short messaging which doesnot need large message buffer" line.long 0x4 "CPU1_MSG0_RMH2,Receiver Message header2(RMH2): 32 bit register each processor has (NumberOfProcessor)x4 RMH2" hexmask.long 0x4 0.--31. 1. "CPU1_MSG0_RMH2,side-band message information which is user defined.Useful in short messaging which doesnot need large message buffer" group.long 0x68++0x3 line.long 0x0 "CPU1_MSG1_RMH0,receiver message header0(RMH0) . each processor has (NumberOfProcessor)x4 RMH0" hexmask.long.byte 0x0 24.--31. 1. "CPU1_MSG1_RMH0,RMH[31:26] could be used to transfer the message RMH[25:24] is actually the message index" rbitfld.long 0x0 16. "CPU1_MSG1_VLD,message valid(MV) of this message e.g. when MV = 1 this message is meant to be received by the processor" "0,1" hexmask.long.byte 0x0 12.--15. 1. "CPU1_MSG1_MBM,Message Buffer Mask(MBM) each bit of MBM[3:0] represents the MB which are used for transferring this message. e.g. MBM[3:0] = 4b0101 means that the message is stored in MB0 and MB2" newline rbitfld.long 0x0 11. "CPU1_MSG1_USE_MB,whether this Message Buffer (MB) are used in this message" "0,1" hexmask.long.word 0x0 0.--10. 1. "CPU1_MSG1_LEN,Message Length (ML) 1x2 to 2048x2Byte" rgroup.long 0x6C++0x7 line.long 0x0 "CPU1_MSG1_RMH1,Receiver Message header1(RMH1): 32 bit register each processor has (NumberOfProcessor)x4 RMH1" hexmask.long 0x0 0.--31. 1. "CPU1_MSG1_RMH1,side-band message information which is user defined.Useful in short messaging which doesnot need large message buffer" line.long 0x4 "CPU1_MSG1_RMH2,Receiver Message header2(RMH2): 32 bit register each processor has (NumberOfProcessor)x4 RMH2" hexmask.long 0x4 0.--31. 1. "CPU1_MSG1_RMH2,side-band message information which is user defined.Useful in short messaging which doesnot need large message buffer" group.long 0x74++0x3 line.long 0x0 "CPU1_MSG2_RMH0,receiver message header0(RMH0) . each processor has (NumberOfProcessor)x4 RMH0" hexmask.long.byte 0x0 24.--31. 1. "CPU1_MSG2_RMH0,RMH[31:26] could be used to transfer the message RMH[25:24] is actually the message index" rbitfld.long 0x0 16. "CPU1_MSG2_VLD,message valid(MV) of this message e.g. when MV = 1 this message is meant to be received by the processor" "0,1" hexmask.long.byte 0x0 12.--15. 1. "CPU1_MSG2_MBM,Message Buffer Mask(MBM) each bit of MBM[3:0] represents the MB which are used for transferring this message. e.g. MBM[3:0] = 4b0101 means that the message is stored in MB0 and MB2" newline rbitfld.long 0x0 11. "CPU1_MSG2_USE_MB,whether this Message Buffer (MB) are used in this message" "0,1" hexmask.long.word 0x0 0.--10. 1. "CPU1_MSG2_LEN,Message Length (ML) 1x2 to 2048x2Byte" rgroup.long 0x78++0x7 line.long 0x0 "CPU1_MSG2_RMH1,Receiver Message header1(RMH1): 32 bit register each processor has (NumberOfProcessor)x4 RMH1" hexmask.long 0x0 0.--31. 1. "CPU1_MSG2_RMH1,side-band message information which is user defined.Useful in short messaging which doesnot need large message buffer" line.long 0x4 "CPU1_MSG2_RMH2,Receiver Message header2(RMH2): 32 bit register each processor has (NumberOfProcessor)x4 RMH2" hexmask.long 0x4 0.--31. 1. "CPU1_MSG2_RMH2,side-band message information which is user defined.Useful in short messaging which doesnot need large message buffer" group.long 0x80++0x3 line.long 0x0 "CPU1_MSG3_RMH0,receiver message header0(RMH0) . each processor has (NumberOfProcessor)x4 RMH0" hexmask.long.byte 0x0 24.--31. 1. "CPU1_MSG3_RMH0,RMH[31:26] could be used to transfer the message RMH[25:24] is actually the message index" rbitfld.long 0x0 16. "CPU1_MSG3_VLD,message valid(MV) of this message e.g. when MV = 1 this message is meant to be received by the processor" "0,1" hexmask.long.byte 0x0 12.--15. 1. "CPU1_MSG3_MBM,Message Buffer Mask(MBM) each bit of MBM[3:0] represents the MB which are used for transferring this message. e.g. MBM[3:0] = 4b0101 means that the message is stored in MB0 and MB2" newline rbitfld.long 0x0 11. "CPU1_MSG3_USE_MB,whether this Message Buffer (MB) are used in this message" "0,1" hexmask.long.word 0x0 0.--10. 1. "CPU1_MSG3_LEN,Message Length (ML) 1x2 to 2048x2Byte" rgroup.long 0x84++0x7 line.long 0x0 "CPU1_MSG3_RMH1,Receiver Message header1(RMH1): 32 bit register each processor has (NumberOfProcessor)x4 RMH1" hexmask.long 0x0 0.--31. 1. "CPU1_MSG3_RMH1,side-band message information which is user defined.Useful in short messaging which doesnot need large message buffer" line.long 0x4 "CPU1_MSG3_RMH2,Receiver Message header2(RMH2): 32 bit register each processor has (NumberOfProcessor)x4 RMH2" hexmask.long 0x4 0.--31. 1. "CPU1_MSG3_RMH2,side-band message information which is user defined.Useful in short messaging which doesnot need large message buffer" group.long 0x8C++0x3 line.long 0x0 "CPU2_MSG0_RMH0,receiver message header0(RMH0) . each processor has (NumberOfProcessor)x4 RMH0" hexmask.long.byte 0x0 24.--31. 1. "CPU2_MSG0_RMH0,RMH[31:26] could be used to transfer the message RMH[25:24] is actually the message index" rbitfld.long 0x0 16. "CPU2_MSG0_VLD,message valid(MV) of this message e.g. when MV = 1 this message is meant to be received by the processor" "0,1" hexmask.long.byte 0x0 12.--15. 1. "CPU2_MSG0_MBM,Message Buffer Mask(MBM) each bit of MBM[3:0] represents the MB which are used for transferring this message. e.g. MBM[3:0] = 4b0101 means that the message is stored in MB0 and MB2" newline rbitfld.long 0x0 11. "CPU2_MSG0_USE_MB,whether this Message Buffer (MB) are used in this message" "0,1" hexmask.long.word 0x0 0.--10. 1. "CPU2_MSG0_LEN,Message Length (ML) 1x2 to 2048x2Byte" rgroup.long 0x90++0x7 line.long 0x0 "CPU2_MSG0_RMH1,Receiver Message header1(RMH1): 32 bit register each processor has (NumberOfProcessor)x4 RMH1" hexmask.long 0x0 0.--31. 1. "CPU2_MSG0_RMH1,side-band message information which is user defined.Useful in short messaging which doesnot need large message buffer" line.long 0x4 "CPU2_MSG0_RMH2,Receiver Message header2(RMH2): 32 bit register each processor has (NumberOfProcessor)x4 RMH2" hexmask.long 0x4 0.--31. 1. "CPU2_MSG0_RMH2,side-band message information which is user defined.Useful in short messaging which doesnot need large message buffer" group.long 0x98++0x3 line.long 0x0 "CPU2_MSG1_RMH0,receiver message header0(RMH0) . each processor has (NumberOfProcessor)x4 RMH0" hexmask.long.byte 0x0 24.--31. 1. "CPU2_MSG1_RMH0,RMH[31:26] could be used to transfer the message RMH[25:24] is actually the message index" rbitfld.long 0x0 16. "CPU2_MSG1_VLD,message valid(MV) of this message e.g. when MV = 1 this message is meant to be received by the processor" "0,1" hexmask.long.byte 0x0 12.--15. 1. "CPU2_MSG1_MBM,Message Buffer Mask(MBM) each bit of MBM[3:0] represents the MB which are used for transferring this message. e.g. MBM[3:0] = 4b0101 means that the message is stored in MB0 and MB2" newline rbitfld.long 0x0 11. "CPU2_MSG1_USE_MB,whether this Message Buffer (MB) are used in this message" "0,1" hexmask.long.word 0x0 0.--10. 1. "CPU2_MSG1_LEN,Message Length (ML) 1x2 to 2048x2Byte" rgroup.long 0x9C++0x7 line.long 0x0 "CPU2_MSG1_RMH1,Receiver Message header1(RMH1): 32 bit register each processor has (NumberOfProcessor)x4 RMH1" hexmask.long 0x0 0.--31. 1. "CPU2_MSG1_RMH1,side-band message information which is user defined.Useful in short messaging which doesnot need large message buffer" line.long 0x4 "CPU2_MSG1_RMH2,Receiver Message header2(RMH2): 32 bit register each processor has (NumberOfProcessor)x4 RMH2" hexmask.long 0x4 0.--31. 1. "CPU2_MSG1_RMH2,side-band message information which is user defined.Useful in short messaging which doesnot need large message buffer" group.long 0xA4++0x3 line.long 0x0 "CPU2_MSG2_RMH0,receiver message header0(RMH0) . each processor has (NumberOfProcessor)x4 RMH0" hexmask.long.byte 0x0 24.--31. 1. "CPU2_MSG2_RMH0,RMH[31:26] could be used to transfer the message RMH[25:24] is actually the message index" rbitfld.long 0x0 16. "CPU2_MSG2_VLD,message valid(MV) of this message e.g. when MV = 1 this message is meant to be received by the processor" "0,1" hexmask.long.byte 0x0 12.--15. 1. "CPU2_MSG2_MBM,Message Buffer Mask(MBM) each bit of MBM[3:0] represents the MB which are used for transferring this message. e.g. MBM[3:0] = 4b0101 means that the message is stored in MB0 and MB2" newline rbitfld.long 0x0 11. "CPU2_MSG2_USE_MB,whether this Message Buffer (MB) are used in this message" "0,1" hexmask.long.word 0x0 0.--10. 1. "CPU2_MSG2_LEN,Message Length (ML) 1x2 to 2048x2Byte" rgroup.long 0xA8++0x7 line.long 0x0 "CPU2_MSG2_RMH1,Receiver Message header1(RMH1): 32 bit register each processor has (NumberOfProcessor)x4 RMH1" hexmask.long 0x0 0.--31. 1. "CPU2_MSG2_RMH1,side-band message information which is user defined.Useful in short messaging which doesnot need large message buffer" line.long 0x4 "CPU2_MSG2_RMH2,Receiver Message header2(RMH2): 32 bit register each processor has (NumberOfProcessor)x4 RMH2" hexmask.long 0x4 0.--31. 1. "CPU2_MSG2_RMH2,side-band message information which is user defined.Useful in short messaging which doesnot need large message buffer" group.long 0xB0++0x3 line.long 0x0 "CPU2_MSG3_RMH0,receiver message header0(RMH0) . each processor has (NumberOfProcessor)x4 RMH0" hexmask.long.byte 0x0 24.--31. 1. "CPU2_MSG3_RMH0,RMH[31:26] could be used to transfer the message RMH[25:24] is actually the message index" rbitfld.long 0x0 16. "CPU2_MSG3_VLD,message valid(MV) of this message e.g. when MV = 1 this message is meant to be received by the processor" "0,1" hexmask.long.byte 0x0 12.--15. 1. "CPU2_MSG3_MBM,Message Buffer Mask(MBM) each bit of MBM[3:0] represents the MB which are used for transferring this message. e.g. MBM[3:0] = 4b0101 means that the message is stored in MB0 and MB2" newline rbitfld.long 0x0 11. "CPU2_MSG3_USE_MB,whether this Message Buffer (MB) are used in this message" "0,1" hexmask.long.word 0x0 0.--10. 1. "CPU2_MSG3_LEN,Message Length (ML) 1x2 to 2048x2Byte" rgroup.long 0xB4++0x7 line.long 0x0 "CPU2_MSG3_RMH1,Receiver Message header1(RMH1): 32 bit register each processor has (NumberOfProcessor)x4 RMH1" hexmask.long 0x0 0.--31. 1. "CPU2_MSG3_RMH1,side-band message information which is user defined.Useful in short messaging which doesnot need large message buffer" line.long 0x4 "CPU2_MSG3_RMH2,Receiver Message header2(RMH2): 32 bit register each processor has (NumberOfProcessor)x4 RMH2" hexmask.long 0x4 0.--31. 1. "CPU2_MSG3_RMH2,side-band message information which is user defined.Useful in short messaging which doesnot need large message buffer" group.long 0xBC++0x3 line.long 0x0 "CPU3_MSG0_RMH0,receiver message header0(RMH0) . each processor has (NumberOfProcessor)x4 RMH0" hexmask.long.byte 0x0 24.--31. 1. "CPU3_MSG0_RMH0,RMH[31:26] could be used to transfer the message RMH[25:24] is actually the message index" rbitfld.long 0x0 16. "CPU3_MSG0_VLD,message valid(MV) of this message e.g. when MV = 1 this message is meant to be received by the processor" "0,1" hexmask.long.byte 0x0 12.--15. 1. "CPU3_MSG0_MBM,Message Buffer Mask(MBM) each bit of MBM[3:0] represents the MB which are used for transferring this message. e.g. MBM[3:0] = 4b0101 means that the message is stored in MB0 and MB2" newline rbitfld.long 0x0 11. "CPU3_MSG0_USE_MB,whether this Message Buffer (MB) are used in this message" "0,1" hexmask.long.word 0x0 0.--10. 1. "CPU3_MSG0_LEN,Message Length (ML) 1x2 to 2048x2Byte" rgroup.long 0xC0++0x7 line.long 0x0 "CPU3_MSG0_RMH1,Receiver Message header1(RMH1): 32 bit register each processor has (NumberOfProcessor)x4 RMH1" hexmask.long 0x0 0.--31. 1. "CPU3_MSG0_RMH1,side-band message information which is user defined.Useful in short messaging which doesnot need large message buffer" line.long 0x4 "CPU3_MSG0_RMH2,Receiver Message header2(RMH2): 32 bit register each processor has (NumberOfProcessor)x4 RMH2" hexmask.long 0x4 0.--31. 1. "CPU3_MSG0_RMH2,side-band message information which is user defined.Useful in short messaging which doesnot need large message buffer" group.long 0xC8++0x3 line.long 0x0 "CPU3_MSG1_RMH0,receiver message header0(RMH0) . each processor has (NumberOfProcessor)x4 RMH0" hexmask.long.byte 0x0 24.--31. 1. "CPU3_MSG1_RMH0,RMH[31:26] could be used to transfer the message RMH[25:24] is actually the message index" rbitfld.long 0x0 16. "CPU3_MSG1_VLD,message valid(MV) of this message e.g. when MV = 1 this message is meant to be received by the processor" "0,1" hexmask.long.byte 0x0 12.--15. 1. "CPU3_MSG1_MBM,Message Buffer Mask(MBM) each bit of MBM[3:0] represents the MB which are used for transferring this message. e.g. MBM[3:0] = 4b0101 means that the message is stored in MB0 and MB2" newline rbitfld.long 0x0 11. "CPU3_MSG1_USE_MB,whether this Message Buffer (MB) are used in this message" "0,1" hexmask.long.word 0x0 0.--10. 1. "CPU3_MSG1_LEN,Message Length (ML) 1x2 to 2048x2Byte" rgroup.long 0xCC++0x7 line.long 0x0 "CPU3_MSG1_RMH1,Receiver Message header1(RMH1): 32 bit register each processor has (NumberOfProcessor)x4 RMH1" hexmask.long 0x0 0.--31. 1. "CPU3_MSG1_RMH1,side-band message information which is user defined.Useful in short messaging which doesnot need large message buffer" line.long 0x4 "CPU3_MSG1_RMH2,Receiver Message header2(RMH2): 32 bit register each processor has (NumberOfProcessor)x4 RMH2" hexmask.long 0x4 0.--31. 1. "CPU3_MSG1_RMH2,side-band message information which is user defined.Useful in short messaging which doesnot need large message buffer" group.long 0xD4++0x3 line.long 0x0 "CPU3_MSG2_RMH0,receiver message header0(RMH0) . each processor has (NumberOfProcessor)x4 RMH0" hexmask.long.byte 0x0 24.--31. 1. "CPU3_MSG2_RMH0,RMH[31:26] could be used to transfer the message RMH[25:24] is actually the message index" rbitfld.long 0x0 16. "CPU3_MSG2_VLD,message valid(MV) of this message e.g. when MV = 1 this message is meant to be received by the processor" "0,1" hexmask.long.byte 0x0 12.--15. 1. "CPU3_MSG2_MBM,Message Buffer Mask(MBM) each bit of MBM[3:0] represents the MB which are used for transferring this message. e.g. MBM[3:0] = 4b0101 means that the message is stored in MB0 and MB2" newline rbitfld.long 0x0 11. "CPU3_MSG2_USE_MB,whether this Message Buffer (MB) are used in this message" "0,1" hexmask.long.word 0x0 0.--10. 1. "CPU3_MSG2_LEN,Message Length (ML) 1x2 to 2048x2Byte" rgroup.long 0xD8++0x7 line.long 0x0 "CPU3_MSG2_RMH1,Receiver Message header1(RMH1): 32 bit register each processor has (NumberOfProcessor)x4 RMH1" hexmask.long 0x0 0.--31. 1. "CPU3_MSG2_RMH1,side-band message information which is user defined.Useful in short messaging which doesnot need large message buffer" line.long 0x4 "CPU3_MSG2_RMH2,Receiver Message header2(RMH2): 32 bit register each processor has (NumberOfProcessor)x4 RMH2" hexmask.long 0x4 0.--31. 1. "CPU3_MSG2_RMH2,side-band message information which is user defined.Useful in short messaging which doesnot need large message buffer" group.long 0xE0++0x3 line.long 0x0 "CPU3_MSG3_RMH0,receiver message header0(RMH0) . each processor has (NumberOfProcessor)x4 RMH0" hexmask.long.byte 0x0 24.--31. 1. "CPU3_MSG3_RMH0,RMH[31:26] could be used to transfer the message RMH[25:24] is actually the message index" rbitfld.long 0x0 16. "CPU3_MSG3_VLD,message valid(MV) of this message e.g. when MV = 1 this message is meant to be received by the processor" "0,1" hexmask.long.byte 0x0 12.--15. 1. "CPU3_MSG3_MBM,Message Buffer Mask(MBM) each bit of MBM[3:0] represents the MB which are used for transferring this message. e.g. MBM[3:0] = 4b0101 means that the message is stored in MB0 and MB2" newline rbitfld.long 0x0 11. "CPU3_MSG3_USE_MB,whether this Message Buffer (MB) are used in this message" "0,1" hexmask.long.word 0x0 0.--10. 1. "CPU3_MSG3_LEN,Message Length (ML) 1x2 to 2048x2Byte" rgroup.long 0xE4++0x7 line.long 0x0 "CPU3_MSG3_RMH1,Receiver Message header1(RMH1): 32 bit register each processor has (NumberOfProcessor)x4 RMH1" hexmask.long 0x0 0.--31. 1. "CPU3_MSG3_RMH1,side-band message information which is user defined.Useful in short messaging which doesnot need large message buffer" line.long 0x4 "CPU3_MSG3_RMH2,Receiver Message header2(RMH2): 32 bit register each processor has (NumberOfProcessor)x4 RMH2" hexmask.long 0x4 0.--31. 1. "CPU3_MSG3_RMH2,side-band message information which is user defined.Useful in short messaging which doesnot need large message buffer" group.long 0xEC++0x3 line.long 0x0 "CPU4_MSG0_RMH0,receiver message header0(RMH0) . each processor has (NumberOfProcessor)x4 RMH0" hexmask.long.byte 0x0 24.--31. 1. "CPU4_MSG0_RMH0,RMH[31:26] could be used to transfer the message RMH[25:24] is actually the message index" rbitfld.long 0x0 16. "CPU4_MSG0_VLD,message valid(MV) of this message e.g. when MV = 1 this message is meant to be received by the processor" "0,1" hexmask.long.byte 0x0 12.--15. 1. "CPU4_MSG0_MBM,Message Buffer Mask(MBM) each bit of MBM[3:0] represents the MB which are used for transferring this message. e.g. MBM[3:0] = 4b0101 means that the message is stored in MB0 and MB2" newline rbitfld.long 0x0 11. "CPU4_MSG0_USE_MB,whether this Message Buffer (MB) are used in this message" "0,1" hexmask.long.word 0x0 0.--10. 1. "CPU4_MSG0_LEN,Message Length (ML) 1x2 to 2048x2Byte" rgroup.long 0xF0++0x7 line.long 0x0 "CPU4_MSG0_RMH1,Receiver Message header1(RMH1): 32 bit register each processor has (NumberOfProcessor)x4 RMH1" hexmask.long 0x0 0.--31. 1. "CPU4_MSG0_RMH1,side-band message information which is user defined.Useful in short messaging which doesnot need large message buffer" line.long 0x4 "CPU4_MSG0_RMH2,Receiver Message header2(RMH2): 32 bit register each processor has (NumberOfProcessor)x4 RMH2" hexmask.long 0x4 0.--31. 1. "CPU4_MSG0_RMH2,side-band message information which is user defined.Useful in short messaging which doesnot need large message buffer" group.long 0xF8++0x3 line.long 0x0 "CPU4_MSG1_RMH0,receiver message header0(RMH0) . each processor has (NumberOfProcessor)x4 RMH0" hexmask.long.byte 0x0 24.--31. 1. "CPU4_MSG1_RMH0,RMH[31:26] could be used to transfer the message RMH[25:24] is actually the message index" rbitfld.long 0x0 16. "CPU4_MSG1_VLD,message valid(MV) of this message e.g. when MV = 1 this message is meant to be received by the processor" "0,1" hexmask.long.byte 0x0 12.--15. 1. "CPU4_MSG1_MBM,Message Buffer Mask(MBM) each bit of MBM[3:0] represents the MB which are used for transferring this message. e.g. MBM[3:0] = 4b0101 means that the message is stored in MB0 and MB2" newline rbitfld.long 0x0 11. "CPU4_MSG1_USE_MB,whether this Message Buffer (MB) are used in this message" "0,1" hexmask.long.word 0x0 0.--10. 1. "CPU4_MSG1_LEN,Message Length (ML) 1x2 to 2048x2Byte" rgroup.long 0xFC++0x7 line.long 0x0 "CPU4_MSG1_RMH1,Receiver Message header1(RMH1): 32 bit register each processor has (NumberOfProcessor)x4 RMH1" hexmask.long 0x0 0.--31. 1. "CPU4_MSG1_RMH1,side-band message information which is user defined.Useful in short messaging which doesnot need large message buffer" line.long 0x4 "CPU4_MSG1_RMH2,Receiver Message header2(RMH2): 32 bit register each processor has (NumberOfProcessor)x4 RMH2" hexmask.long 0x4 0.--31. 1. "CPU4_MSG1_RMH2,side-band message information which is user defined.Useful in short messaging which doesnot need large message buffer" group.long 0x104++0x3 line.long 0x0 "CPU4_MSG2_RMH0,receiver message header0(RMH0) . each processor has (NumberOfProcessor)x4 RMH0" hexmask.long.byte 0x0 24.--31. 1. "CPU4_MSG2_RMH0,RMH[31:26] could be used to transfer the message RMH[25:24] is actually the message index" rbitfld.long 0x0 16. "CPU4_MSG2_VLD,message valid(MV) of this message e.g. when MV = 1 this message is meant to be received by the processor" "0,1" hexmask.long.byte 0x0 12.--15. 1. "CPU4_MSG2_MBM,Message Buffer Mask(MBM) each bit of MBM[3:0] represents the MB which are used for transferring this message. e.g. MBM[3:0] = 4b0101 means that the message is stored in MB0 and MB2" newline rbitfld.long 0x0 11. "CPU4_MSG2_USE_MB,whether this Message Buffer (MB) are used in this message" "0,1" hexmask.long.word 0x0 0.--10. 1. "CPU4_MSG2_LEN,Message Length (ML) 1x2 to 2048x2Byte" rgroup.long 0x108++0x7 line.long 0x0 "CPU4_MSG2_RMH1,Receiver Message header1(RMH1): 32 bit register each processor has (NumberOfProcessor)x4 RMH1" hexmask.long 0x0 0.--31. 1. "CPU4_MSG2_RMH1,side-band message information which is user defined.Useful in short messaging which doesnot need large message buffer" line.long 0x4 "CPU4_MSG2_RMH2,Receiver Message header2(RMH2): 32 bit register each processor has (NumberOfProcessor)x4 RMH2" hexmask.long 0x4 0.--31. 1. "CPU4_MSG2_RMH2,side-band message information which is user defined.Useful in short messaging which doesnot need large message buffer" group.long 0x110++0x3 line.long 0x0 "CPU4_MSG3_RMH0,receiver message header0(RMH0) . each processor has (NumberOfProcessor)x4 RMH0" hexmask.long.byte 0x0 24.--31. 1. "CPU4_MSG3_RMH0,RMH[31:26] could be used to transfer the message RMH[25:24] is actually the message index" rbitfld.long 0x0 16. "CPU4_MSG3_VLD,message valid(MV) of this message e.g. when MV = 1 this message is meant to be received by the processor" "0,1" hexmask.long.byte 0x0 12.--15. 1. "CPU4_MSG3_MBM,Message Buffer Mask(MBM) each bit of MBM[3:0] represents the MB which are used for transferring this message. e.g. MBM[3:0] = 4b0101 means that the message is stored in MB0 and MB2" newline rbitfld.long 0x0 11. "CPU4_MSG3_USE_MB,whether this Message Buffer (MB) are used in this message" "0,1" hexmask.long.word 0x0 0.--10. 1. "CPU4_MSG3_LEN,Message Length (ML) 1x2 to 2048x2Byte" rgroup.long 0x114++0x7 line.long 0x0 "CPU4_MSG3_RMH1,Receiver Message header1(RMH1): 32 bit register each processor has (NumberOfProcessor)x4 RMH1" hexmask.long 0x0 0.--31. 1. "CPU4_MSG3_RMH1,side-band message information which is user defined.Useful in short messaging which doesnot need large message buffer" line.long 0x4 "CPU4_MSG3_RMH2,Receiver Message header2(RMH2): 32 bit register each processor has (NumberOfProcessor)x4 RMH2" hexmask.long 0x4 0.--31. 1. "CPU4_MSG3_RMH2,side-band message information which is user defined.Useful in short messaging which doesnot need large message buffer" group.long 0x11C++0x3 line.long 0x0 "CPU5_MSG0_RMH0,receiver message header0(RMH0) . each processor has (NumberOfProcessor)x4 RMH0" hexmask.long.byte 0x0 24.--31. 1. "CPU5_MSG0_RMH0,RMH[31:26] could be used to transfer the message RMH[25:24] is actually the message index" rbitfld.long 0x0 16. "CPU5_MSG0_VLD,message valid(MV) of this message e.g. when MV = 1 this message is meant to be received by the processor" "0,1" hexmask.long.byte 0x0 12.--15. 1. "CPU5_MSG0_MBM,Message Buffer Mask(MBM) each bit of MBM[3:0] represents the MB which are used for transferring this message. e.g. MBM[3:0] = 4b0101 means that the message is stored in MB0 and MB2" newline rbitfld.long 0x0 11. "CPU5_MSG0_USE_MB,whether this Message Buffer (MB) are used in this message" "0,1" hexmask.long.word 0x0 0.--10. 1. "CPU5_MSG0_LEN,Message Length (ML) 1x2 to 2048x2Byte" rgroup.long 0x120++0x7 line.long 0x0 "CPU5_MSG0_RMH1,Receiver Message header1(RMH1): 32 bit register each processor has (NumberOfProcessor)x4 RMH1" hexmask.long 0x0 0.--31. 1. "CPU5_MSG0_RMH1,side-band message information which is user defined.Useful in short messaging which doesnot need large message buffer" line.long 0x4 "CPU5_MSG0_RMH2,Receiver Message header2(RMH2): 32 bit register each processor has (NumberOfProcessor)x4 RMH2" hexmask.long 0x4 0.--31. 1. "CPU5_MSG0_RMH2,side-band message information which is user defined.Useful in short messaging which doesnot need large message buffer" group.long 0x128++0x3 line.long 0x0 "CPU5_MSG1_RMH0,receiver message header0(RMH0) . each processor has (NumberOfProcessor)x4 RMH0" hexmask.long.byte 0x0 24.--31. 1. "CPU5_MSG1_RMH0,RMH[31:26] could be used to transfer the message RMH[25:24] is actually the message index" rbitfld.long 0x0 16. "CPU5_MSG1_VLD,message valid(MV) of this message e.g. when MV = 1 this message is meant to be received by the processor" "0,1" hexmask.long.byte 0x0 12.--15. 1. "CPU5_MSG1_MBM,Message Buffer Mask(MBM) each bit of MBM[3:0] represents the MB which are used for transferring this message. e.g. MBM[3:0] = 4b0101 means that the message is stored in MB0 and MB2" newline rbitfld.long 0x0 11. "CPU5_MSG1_USE_MB,whether this Message Buffer (MB) are used in this message" "0,1" hexmask.long.word 0x0 0.--10. 1. "CPU5_MSG1_LEN,Message Length (ML) 1x2 to 2048x2Byte" rgroup.long 0x12C++0x7 line.long 0x0 "CPU5_MSG1_RMH1,Receiver Message header1(RMH1): 32 bit register each processor has (NumberOfProcessor)x4 RMH1" hexmask.long 0x0 0.--31. 1. "CPU5_MSG1_RMH1,side-band message information which is user defined.Useful in short messaging which doesnot need large message buffer" line.long 0x4 "CPU5_MSG1_RMH2,Receiver Message header2(RMH2): 32 bit register each processor has (NumberOfProcessor)x4 RMH2" hexmask.long 0x4 0.--31. 1. "CPU5_MSG1_RMH2,side-band message information which is user defined.Useful in short messaging which doesnot need large message buffer" group.long 0x134++0x3 line.long 0x0 "CPU5_MSG2_RMH0,receiver message header0(RMH0) . each processor has (NumberOfProcessor)x4 RMH0" hexmask.long.byte 0x0 24.--31. 1. "CPU5_MSG2_RMH0,RMH[31:26] could be used to transfer the message RMH[25:24] is actually the message index" rbitfld.long 0x0 16. "CPU5_MSG2_VLD,message valid(MV) of this message e.g. when MV = 1 this message is meant to be received by the processor" "0,1" hexmask.long.byte 0x0 12.--15. 1. "CPU5_MSG2_MBM,Message Buffer Mask(MBM) each bit of MBM[3:0] represents the MB which are used for transferring this message. e.g. MBM[3:0] = 4b0101 means that the message is stored in MB0 and MB2" newline rbitfld.long 0x0 11. "CPU5_MSG2_USE_MB,whether this Message Buffer (MB) are used in this message" "0,1" hexmask.long.word 0x0 0.--10. 1. "CPU5_MSG2_LEN,Message Length (ML) 1x2 to 2048x2Byte" rgroup.long 0x138++0x7 line.long 0x0 "CPU5_MSG2_RMH1,Receiver Message header1(RMH1): 32 bit register each processor has (NumberOfProcessor)x4 RMH1" hexmask.long 0x0 0.--31. 1. "CPU5_MSG2_RMH1,side-band message information which is user defined.Useful in short messaging which doesnot need large message buffer" line.long 0x4 "CPU5_MSG2_RMH2,Receiver Message header2(RMH2): 32 bit register each processor has (NumberOfProcessor)x4 RMH2" hexmask.long 0x4 0.--31. 1. "CPU5_MSG2_RMH2,side-band message information which is user defined.Useful in short messaging which doesnot need large message buffer" group.long 0x140++0x3 line.long 0x0 "CPU5_MSG3_RMH0,receiver message header0(RMH0) . each processor has (NumberOfProcessor)x4 RMH0" hexmask.long.byte 0x0 24.--31. 1. "CPU5_MSG3_RMH0,RMH[31:26] could be used to transfer the message RMH[25:24] is actually the message index" rbitfld.long 0x0 16. "CPU5_MSG3_VLD,message valid(MV) of this message e.g. when MV = 1 this message is meant to be received by the processor" "0,1" hexmask.long.byte 0x0 12.--15. 1. "CPU5_MSG3_MBM,Message Buffer Mask(MBM) each bit of MBM[3:0] represents the MB which are used for transferring this message. e.g. MBM[3:0] = 4b0101 means that the message is stored in MB0 and MB2" newline rbitfld.long 0x0 11. "CPU5_MSG3_USE_MB,whether this Message Buffer (MB) are used in this message" "0,1" hexmask.long.word 0x0 0.--10. 1. "CPU5_MSG3_LEN,Message Length (ML) 1x2 to 2048x2Byte" rgroup.long 0x144++0x7 line.long 0x0 "CPU5_MSG3_RMH1,Receiver Message header1(RMH1): 32 bit register each processor has (NumberOfProcessor)x4 RMH1" hexmask.long 0x0 0.--31. 1. "CPU5_MSG3_RMH1,side-band message information which is user defined.Useful in short messaging which doesnot need large message buffer" line.long 0x4 "CPU5_MSG3_RMH2,Receiver Message header2(RMH2): 32 bit register each processor has (NumberOfProcessor)x4 RMH2" hexmask.long 0x4 0.--31. 1. "CPU5_MSG3_RMH2,side-band message information which is user defined.Useful in short messaging which doesnot need large message buffer" group.long 0x14C++0x3 line.long 0x0 "CPU6_MSG0_RMH0,receiver message header0(RMH0) . each processor has (NumberOfProcessor)x4 RMH0" hexmask.long.byte 0x0 24.--31. 1. "CPU6_MSG0_RMH0,RMH[31:26] could be used to transfer the message RMH[25:24] is actually the message index" rbitfld.long 0x0 16. "CPU6_MSG0_VLD,message valid(MV) of this message e.g. when MV = 1 this message is meant to be received by the processor" "0,1" hexmask.long.byte 0x0 12.--15. 1. "CPU6_MSG0_MBM,Message Buffer Mask(MBM) each bit of MBM[3:0] represents the MB which are used for transferring this message. e.g. MBM[3:0] = 4b0101 means that the message is stored in MB0 and MB2" newline rbitfld.long 0x0 11. "CPU6_MSG0_USE_MB,whether this Message Buffer (MB) are used in this message" "0,1" hexmask.long.word 0x0 0.--10. 1. "CPU6_MSG0_LEN,Message Length (ML) 1x2 to 2048x2Byte" rgroup.long 0x150++0x7 line.long 0x0 "CPU6_MSG0_RMH1,Receiver Message header1(RMH1): 32 bit register each processor has (NumberOfProcessor)x4 RMH1" hexmask.long 0x0 0.--31. 1. "CPU6_MSG0_RMH1,side-band message information which is user defined.Useful in short messaging which doesnot need large message buffer" line.long 0x4 "CPU6_MSG0_RMH2,Receiver Message header2(RMH2): 32 bit register each processor has (NumberOfProcessor)x4 RMH2" hexmask.long 0x4 0.--31. 1. "CPU6_MSG0_RMH2,side-band message information which is user defined.Useful in short messaging which doesnot need large message buffer" group.long 0x158++0x3 line.long 0x0 "CPU6_MSG1_RMH0,receiver message header0(RMH0) . each processor has (NumberOfProcessor)x4 RMH0" hexmask.long.byte 0x0 24.--31. 1. "CPU6_MSG1_RMH0,RMH[31:26] could be used to transfer the message RMH[25:24] is actually the message index" rbitfld.long 0x0 16. "CPU6_MSG1_VLD,message valid(MV) of this message e.g. when MV = 1 this message is meant to be received by the processor" "0,1" hexmask.long.byte 0x0 12.--15. 1. "CPU6_MSG1_MBM,Message Buffer Mask(MBM) each bit of MBM[3:0] represents the MB which are used for transferring this message. e.g. MBM[3:0] = 4b0101 means that the message is stored in MB0 and MB2" newline rbitfld.long 0x0 11. "CPU6_MSG1_USE_MB,whether this Message Buffer (MB) are used in this message" "0,1" hexmask.long.word 0x0 0.--10. 1. "CPU6_MSG1_LEN,Message Length (ML) 1x2 to 2048x2Byte" rgroup.long 0x15C++0x7 line.long 0x0 "CPU6_MSG1_RMH1,Receiver Message header1(RMH1): 32 bit register each processor has (NumberOfProcessor)x4 RMH1" hexmask.long 0x0 0.--31. 1. "CPU6_MSG1_RMH1,side-band message information which is user defined.Useful in short messaging which doesnot need large message buffer" line.long 0x4 "CPU6_MSG1_RMH2,Receiver Message header2(RMH2): 32 bit register each processor has (NumberOfProcessor)x4 RMH2" hexmask.long 0x4 0.--31. 1. "CPU6_MSG1_RMH2,side-band message information which is user defined.Useful in short messaging which doesnot need large message buffer" group.long 0x164++0x3 line.long 0x0 "CPU6_MSG2_RMH0,receiver message header0(RMH0) . each processor has (NumberOfProcessor)x4 RMH0" hexmask.long.byte 0x0 24.--31. 1. "CPU6_MSG2_RMH0,RMH[31:26] could be used to transfer the message RMH[25:24] is actually the message index" rbitfld.long 0x0 16. "CPU6_MSG2_VLD,message valid(MV) of this message e.g. when MV = 1 this message is meant to be received by the processor" "0,1" hexmask.long.byte 0x0 12.--15. 1. "CPU6_MSG2_MBM,Message Buffer Mask(MBM) each bit of MBM[3:0] represents the MB which are used for transferring this message. e.g. MBM[3:0] = 4b0101 means that the message is stored in MB0 and MB2" newline rbitfld.long 0x0 11. "CPU6_MSG2_USE_MB,whether this Message Buffer (MB) are used in this message" "0,1" hexmask.long.word 0x0 0.--10. 1. "CPU6_MSG2_LEN,Message Length (ML) 1x2 to 2048x2Byte" rgroup.long 0x168++0x7 line.long 0x0 "CPU6_MSG2_RMH1,Receiver Message header1(RMH1): 32 bit register each processor has (NumberOfProcessor)x4 RMH1" hexmask.long 0x0 0.--31. 1. "CPU6_MSG2_RMH1,side-band message information which is user defined.Useful in short messaging which doesnot need large message buffer" line.long 0x4 "CPU6_MSG2_RMH2,Receiver Message header2(RMH2): 32 bit register each processor has (NumberOfProcessor)x4 RMH2" hexmask.long 0x4 0.--31. 1. "CPU6_MSG2_RMH2,side-band message information which is user defined.Useful in short messaging which doesnot need large message buffer" group.long 0x170++0x3 line.long 0x0 "CPU6_MSG3_RMH0,receiver message header0(RMH0) . each processor has (NumberOfProcessor)x4 RMH0" hexmask.long.byte 0x0 24.--31. 1. "CPU6_MSG3_RMH0,RMH[31:26] could be used to transfer the message RMH[25:24] is actually the message index" rbitfld.long 0x0 16. "CPU6_MSG3_VLD,message valid(MV) of this message e.g. when MV = 1 this message is meant to be received by the processor" "0,1" hexmask.long.byte 0x0 12.--15. 1. "CPU6_MSG3_MBM,Message Buffer Mask(MBM) each bit of MBM[3:0] represents the MB which are used for transferring this message. e.g. MBM[3:0] = 4b0101 means that the message is stored in MB0 and MB2" newline rbitfld.long 0x0 11. "CPU6_MSG3_USE_MB,whether this Message Buffer (MB) are used in this message" "0,1" hexmask.long.word 0x0 0.--10. 1. "CPU6_MSG3_LEN,Message Length (ML) 1x2 to 2048x2Byte" rgroup.long 0x174++0x7 line.long 0x0 "CPU6_MSG3_RMH1,Receiver Message header1(RMH1): 32 bit register each processor has (NumberOfProcessor)x4 RMH1" hexmask.long 0x0 0.--31. 1. "CPU6_MSG3_RMH1,side-band message information which is user defined.Useful in short messaging which doesnot need large message buffer" line.long 0x4 "CPU6_MSG3_RMH2,Receiver Message header2(RMH2): 32 bit register each processor has (NumberOfProcessor)x4 RMH2" hexmask.long 0x4 0.--31. 1. "CPU6_MSG3_RMH2,side-band message information which is user defined.Useful in short messaging which doesnot need large message buffer" group.long 0x17C++0x3 line.long 0x0 "CPU7_MSG0_RMH0,receiver message header0(RMH0) . each processor has (NumberOfProcessor)x4 RMH0" hexmask.long.byte 0x0 24.--31. 1. "CPU7_MSG0_RMH0,RMH[31:26] could be used to transfer the message RMH[25:24] is actually the message index" rbitfld.long 0x0 16. "CPU7_MSG0_VLD,message valid(MV) of this message e.g. when MV = 1 this message is meant to be received by the processor" "0,1" hexmask.long.byte 0x0 12.--15. 1. "CPU7_MSG0_MBM,Message Buffer Mask(MBM) each bit of MBM[3:0] represents the MB which are used for transferring this message. e.g. MBM[3:0] = 4b0101 means that the message is stored in MB0 and MB2" newline rbitfld.long 0x0 11. "CPU7_MSG0_USE_MB,whether this Message Buffer (MB) are used in this message" "0,1" hexmask.long.word 0x0 0.--10. 1. "CPU7_MSG0_LEN,Message Length (ML) 1x2 to 2048x2Byte" rgroup.long 0x180++0x7 line.long 0x0 "CPU7_MSG0_RMH1,Receiver Message header1(RMH1): 32 bit register each processor has (NumberOfProcessor)x4 RMH1" hexmask.long 0x0 0.--31. 1. "CPU7_MSG0_RMH1,side-band message information which is user defined.Useful in short messaging which doesnot need large message buffer" line.long 0x4 "CPU7_MSG0_RMH2,Receiver Message header2(RMH2): 32 bit register each processor has (NumberOfProcessor)x4 RMH2" hexmask.long 0x4 0.--31. 1. "CPU7_MSG0_RMH2,side-band message information which is user defined.Useful in short messaging which doesnot need large message buffer" group.long 0x188++0x3 line.long 0x0 "CPU7_MSG1_RMH0,receiver message header0(RMH0) . each processor has (NumberOfProcessor)x4 RMH0" hexmask.long.byte 0x0 24.--31. 1. "CPU7_MSG1_RMH0,RMH[31:26] could be used to transfer the message RMH[25:24] is actually the message index" rbitfld.long 0x0 16. "CPU7_MSG1_VLD,message valid(MV) of this message e.g. when MV = 1 this message is meant to be received by the processor" "0,1" hexmask.long.byte 0x0 12.--15. 1. "CPU7_MSG1_MBM,Message Buffer Mask(MBM) each bit of MBM[3:0] represents the MB which are used for transferring this message. e.g. MBM[3:0] = 4b0101 means that the message is stored in MB0 and MB2" newline rbitfld.long 0x0 11. "CPU7_MSG1_USE_MB,whether this Message Buffer (MB) are used in this message" "0,1" hexmask.long.word 0x0 0.--10. 1. "CPU7_MSG1_LEN,Message Length (ML) 1x2 to 2048x2Byte" rgroup.long 0x18C++0x7 line.long 0x0 "CPU7_MSG1_RMH1,Receiver Message header1(RMH1): 32 bit register each processor has (NumberOfProcessor)x4 RMH1" hexmask.long 0x0 0.--31. 1. "CPU7_MSG1_RMH1,side-band message information which is user defined.Useful in short messaging which doesnot need large message buffer" line.long 0x4 "CPU7_MSG1_RMH2,Receiver Message header2(RMH2): 32 bit register each processor has (NumberOfProcessor)x4 RMH2" hexmask.long 0x4 0.--31. 1. "CPU7_MSG1_RMH2,side-band message information which is user defined.Useful in short messaging which doesnot need large message buffer" group.long 0x194++0x3 line.long 0x0 "CPU7_MSG2_RMH0,receiver message header0(RMH0) . each processor has (NumberOfProcessor)x4 RMH0" hexmask.long.byte 0x0 24.--31. 1. "CPU7_MSG2_RMH0,RMH[31:26] could be used to transfer the message RMH[25:24] is actually the message index" rbitfld.long 0x0 16. "CPU7_MSG2_VLD,message valid(MV) of this message e.g. when MV = 1 this message is meant to be received by the processor" "0,1" hexmask.long.byte 0x0 12.--15. 1. "CPU7_MSG2_MBM,Message Buffer Mask(MBM) each bit of MBM[3:0] represents the MB which are used for transferring this message. e.g. MBM[3:0] = 4b0101 means that the message is stored in MB0 and MB2" newline rbitfld.long 0x0 11. "CPU7_MSG2_USE_MB,whether this Message Buffer (MB) are used in this message" "0,1" hexmask.long.word 0x0 0.--10. 1. "CPU7_MSG2_LEN,Message Length (ML) 1x2 to 2048x2Byte" rgroup.long 0x198++0x7 line.long 0x0 "CPU7_MSG2_RMH1,Receiver Message header1(RMH1): 32 bit register each processor has (NumberOfProcessor)x4 RMH1" hexmask.long 0x0 0.--31. 1. "CPU7_MSG2_RMH1,side-band message information which is user defined.Useful in short messaging which doesnot need large message buffer" line.long 0x4 "CPU7_MSG2_RMH2,Receiver Message header2(RMH2): 32 bit register each processor has (NumberOfProcessor)x4 RMH2" hexmask.long 0x4 0.--31. 1. "CPU7_MSG2_RMH2,side-band message information which is user defined.Useful in short messaging which doesnot need large message buffer" group.long 0x1A0++0x3 line.long 0x0 "CPU7_MSG3_RMH0,receiver message header0(RMH0) . each processor has (NumberOfProcessor)x4 RMH0" hexmask.long.byte 0x0 24.--31. 1. "CPU7_MSG3_RMH0,RMH[31:26] could be used to transfer the message RMH[25:24] is actually the message index" rbitfld.long 0x0 16. "CPU7_MSG3_VLD,message valid(MV) of this message e.g. when MV = 1 this message is meant to be received by the processor" "0,1" hexmask.long.byte 0x0 12.--15. 1. "CPU7_MSG3_MBM,Message Buffer Mask(MBM) each bit of MBM[3:0] represents the MB which are used for transferring this message. e.g. MBM[3:0] = 4b0101 means that the message is stored in MB0 and MB2" newline rbitfld.long 0x0 11. "CPU7_MSG3_USE_MB,whether this Message Buffer (MB) are used in this message" "0,1" hexmask.long.word 0x0 0.--10. 1. "CPU7_MSG3_LEN,Message Length (ML) 1x2 to 2048x2Byte" rgroup.long 0x1A4++0x7 line.long 0x0 "CPU7_MSG3_RMH1,Receiver Message header1(RMH1): 32 bit register each processor has (NumberOfProcessor)x4 RMH1" hexmask.long 0x0 0.--31. 1. "CPU7_MSG3_RMH1,side-band message information which is user defined.Useful in short messaging which doesnot need large message buffer" line.long 0x4 "CPU7_MSG3_RMH2,Receiver Message header2(RMH2): 32 bit register each processor has (NumberOfProcessor)x4 RMH2" hexmask.long 0x4 0.--31. 1. "CPU7_MSG3_RMH2,side-band message information which is user defined.Useful in short messaging which doesnot need large message buffer" repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x8 0x10 0x18 0x20 0x28 0x30 0x38 0x40 0x48 0x50 0x58 0x60 0x68 0x70 0x78 ) group.long ($2+0x200)++0x3 line.long 0x0 "SEMAG$1,SEMAphore gate. 32 bit register. update to 64Gate based on parameter configuration" bitfld.long 0x0 24. "SG0LIC,Semaphore Gate 0 Lock interrupt clear (SGLIC[7:0]) write 1 to this register will clear the lock fail interrrupt to the processor" "0,1" hexmask.long.byte 0x0 16.--23. 1. "SG0LS,Semaphore Gate 0 Lock Status (SGLS[7:0]) SG0LS=8b00001000 means the gate is locked by Processor" newline bitfld.long 0x0 8. "IESG0LF,Interrupt Enable on Semaphore Gate Lock Failure (IESGLF) When 1 MU will send interrupt to the Processer which failed to lock the semaphore gate on semaphore gate release" "0,1" bitfld.long 0x0 0. "SG0C,Can be accessed by all processors. One Processor can write 1 to SGC to request lock of this gate. Processer can read this bit to check if semaphore is locked or not (when 0 locked when 1 locked).The lock can be removed by write 0 to this field by.." "0,1" repeat.end repeat 16. (list 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1A 0x1B 0x1C 0x1D 0x1E 0x1F )(list 0x80 0x88 0x90 0x98 0xA0 0xA8 0xB0 0xB8 0xC0 0xC8 0xD0 0xD8 0xE0 0xE8 0xF0 0xF8 ) group.long ($2+0x200)++0x3 line.long 0x0 "SEMAG$1,SEMAphore gate. 32 bit register. update to 64Gate based on parameter configuration" bitfld.long 0x0 24. "SG0LIC,Semaphore Gate 0 Lock interrupt clear (SGLIC[7:0]) write 1 to this register will clear the lock fail interrrupt to the processor" "0,1" hexmask.long.byte 0x0 16.--23. 1. "SG0LS,Semaphore Gate 0 Lock Status (SGLS[7:0]) SG0LS=8b00001000 means the gate is locked by Processor" newline bitfld.long 0x0 8. "IESG0LF,Interrupt Enable on Semaphore Gate Lock Failure (IESGLF) When 1 MU will send interrupt to the Processer which failed to lock the semaphore gate on semaphore gate release" "0,1" bitfld.long 0x0 0. "SG0C,Can be accessed by all processors. One Processor can write 1 to SGC to request lock of this gate. Processer can read this bit to check if semaphore is locked or not (when 0 locked when 1 locked).The lock can be removed by write 0 to this field by.." "0,1" repeat.end repeat 16. (list 0x20 0x21 0x22 0x23 0x24 0x25 0x26 0x27 0x28 0x29 0x2A 0x2B 0x2C 0x2D 0x2E 0x2F )(list 0x100 0x108 0x110 0x118 0x120 0x128 0x130 0x138 0x140 0x148 0x150 0x158 0x160 0x168 0x170 0x178 ) group.long ($2+0x200)++0x3 line.long 0x0 "SEMAG$1,SEMAphore gate. 32 bit register. update to 64Gate based on parameter configuration" bitfld.long 0x0 24. "SG0LIC,Semaphore Gate 0 Lock interrupt clear (SGLIC[7:0]) write 1 to this register will clear the lock fail interrrupt to the processor" "0,1" hexmask.long.byte 0x0 16.--23. 1. "SG0LS,Semaphore Gate 0 Lock Status (SGLS[7:0]) SG0LS=8b00001000 means the gate is locked by Processor" newline bitfld.long 0x0 8. "IESG0LF,Interrupt Enable on Semaphore Gate Lock Failure (IESGLF) When 1 MU will send interrupt to the Processer which failed to lock the semaphore gate on semaphore gate release" "0,1" bitfld.long 0x0 0. "SG0C,Can be accessed by all processors. One Processor can write 1 to SGC to request lock of this gate. Processer can read this bit to check if semaphore is locked or not (when 0 locked when 1 locked).The lock can be removed by write 0 to this field by.." "0,1" repeat.end repeat 16. (list 0x30 0x31 0x32 0x33 0x34 0x35 0x36 0x37 0x38 0x39 0x3A 0x3B 0x3C 0x3D 0x3E 0x3F )(list 0x180 0x188 0x190 0x198 0x1A0 0x1A8 0x1B0 0x1B8 0x1C0 0x1C8 0x1D0 0x1D8 0x1E0 0x1E8 0x1F0 0x1F8 ) group.long ($2+0x200)++0x3 line.long 0x0 "SEMAG$1,SEMAphore gate. 32 bit register. update to 64Gate based on parameter configuration" bitfld.long 0x0 24. "SG0LIC,Semaphore Gate 0 Lock interrupt clear (SGLIC[7:0]) write 1 to this register will clear the lock fail interrrupt to the processor" "0,1" hexmask.long.byte 0x0 16.--23. 1. "SG0LS,Semaphore Gate 0 Lock Status (SGLS[7:0]) SG0LS=8b00001000 means the gate is locked by Processor" newline bitfld.long 0x0 8. "IESG0LF,Interrupt Enable on Semaphore Gate Lock Failure (IESGLF) When 1 MU will send interrupt to the Processer which failed to lock the semaphore gate on semaphore gate release" "0,1" bitfld.long 0x0 0. "SG0C,Can be accessed by all processors. One Processor can write 1 to SGC to request lock of this gate. Processer can read this bit to check if semaphore is locked or not (when 0 locked when 1 locked).The lock can be removed by write 0 to this field by.." "0,1" repeat.end group.long 0x204++0x3 line.long 0x0 "SEMAG0PC,32 bit register up to 64 gates based on parameter configuration" bitfld.long 0x0 8. "SG0PL,Semaphore Gate 0 Permission Lock (SGPL)" "0,1" hexmask.long.byte 0x0 0.--7. 1. "SG0P,Semaphore access permission enable bit for those 8 Processers. When SGP[M]=1 access permission of Processer-M to this gate is enabled." group.long 0x20C++0x3 line.long 0x0 "SEMAG1PC,32 bit register up to 64 gates based on parameter configuration" bitfld.long 0x0 8. "SG1PL,Semaphore Gate 1 Permission Lock (SGPL)" "0,1" hexmask.long.byte 0x0 0.--7. 1. "SG1P,Semaphore access permission enable bit for those 8 Processers. When SGP[M]=1 access permission of Processer-M to this gate is enabled." group.long 0x214++0x3 line.long 0x0 "SEMAG2PC,32 bit register up to 64 gates based on parameter configuration" bitfld.long 0x0 8. "SG2PL,Semaphore Gate 2 Permission Lock (SGPL)" "0,1" hexmask.long.byte 0x0 0.--7. 1. "SG2P,Semaphore access permission enable bit for those 8 Processers. When SGP[M]=1 access permission of Processer-M to this gate is enabled." group.long 0x21C++0x3 line.long 0x0 "SEMAG3PC,32 bit register up to 64 gates based on parameter configuration" bitfld.long 0x0 8. "SG3PL,Semaphore Gate3 Permission Lock (SGPL)" "0,1" hexmask.long.byte 0x0 0.--7. 1. "SG3P,Semaphore access permission enable bit for those 8 Processers. When SGP[M]=1 access permission of Processer-M to this gate is enabled." group.long 0x224++0x3 line.long 0x0 "SEMAG4PC,32 bit register up to 64 gates based on parameter configuration" bitfld.long 0x0 8. "SG4PL,Semaphore Gate4 Permission Lock (SGPL)" "0,1" hexmask.long.byte 0x0 0.--7. 1. "SG4P,Semaphore access permission enable bit for those 8 Processers. When SGP[M]=1 access permission of Processer-M to this gate is enabled." group.long 0x22C++0x3 line.long 0x0 "SEMAG5PC,32 bit register up to 64 gates based on parameter configuration" bitfld.long 0x0 8. "SG5PL,Semaphore Gate 5 Permission Lock (SGPL)" "0,1" hexmask.long.byte 0x0 0.--7. 1. "SG5P,Semaphore access permission enable bit for those 8 Processers. When SGP[M]=1 access permission of Processer-M to this gate is enabled." group.long 0x234++0x3 line.long 0x0 "SEMAG6PC,32 bit register up to 64 gates based on parameter configuration" bitfld.long 0x0 8. "SG6PL,Semaphore Gate6 Permission Lock (SGPL)" "0,1" hexmask.long.byte 0x0 0.--7. 1. "SG6P,Semaphore access permission enable bit for those 8 Processers. When SGP[M]=1 access permission of Processer-M to this gate is enabled." group.long 0x23C++0x3 line.long 0x0 "SEMAG7PC,32 bit register up to 64 gates based on parameter configuration" bitfld.long 0x0 8. "SG7PL,Semaphore Gate7 Permission Lock (SGPL)" "0,1" hexmask.long.byte 0x0 0.--7. 1. "SG7P,Semaphore access permission enable bit for those 8 Processers. When SGP[M]=1 access permission of Processer-M to this gate is enabled." group.long 0x244++0x3 line.long 0x0 "SEMAG8PC,32 bit register up to 64 gates based on parameter configuration" bitfld.long 0x0 8. "SG8PL,Semaphore Gate 8 Permission Lock (SGPL)" "0,1" hexmask.long.byte 0x0 0.--7. 1. "SG8P,Semaphore access permission enable bit for those 8 Processers. When SGP[M]=1 access permission of Processer-M to this gate is enabled." group.long 0x24C++0x3 line.long 0x0 "SEMAG9PC,32 bit register up to 64 gates based on parameter configuration" bitfld.long 0x0 8. "SG9PL,Semaphore Gate9 Permission Lock (SGPL)" "0,1" hexmask.long.byte 0x0 0.--7. 1. "SG9P,Semaphore access permission enable bit for those 8 Processers. When SGP[M]=1 access permission of Processer-M to this gate is enabled." group.long 0x254++0x3 line.long 0x0 "SEMAG10PC,32 bit register up to 64 gates based on parameter configuration" bitfld.long 0x0 8. "SG10PL,Semaphore Gate 0 Permission Lock (SGPL)" "0,1" hexmask.long.byte 0x0 0.--7. 1. "SG10P,Semaphore access permission enable bit for those 8 Processers. When SGP[M]=1 access permission of Processer-M to this gate is enabled." group.long 0x25C++0x3 line.long 0x0 "SEMAG11PC,32 bit register up to 64 gates based on parameter configuration" bitfld.long 0x0 8. "SG11PL,Semaphore Gate 1 Permission Lock (SGPL)" "0,1" hexmask.long.byte 0x0 0.--7. 1. "SG11P,Semaphore access permission enable bit for those 8 Processers. When SGP[M]=1 access permission of Processer-M to this gate is enabled." group.long 0x264++0x3 line.long 0x0 "SEMAG12PC,32 bit register up to 64 gates based on parameter configuration" bitfld.long 0x0 8. "SG12PL,Semaphore Gate 2 Permission Lock (SGPL)" "0,1" hexmask.long.byte 0x0 0.--7. 1. "SG12P,Semaphore access permission enable bit for those 8 Processers. When SGP[M]=1 access permission of Processer-M to this gate is enabled." group.long 0x26C++0x3 line.long 0x0 "SEMAG13PC,32 bit register up to 64 gates based on parameter configuration" bitfld.long 0x0 8. "SG13PL,Semaphore Gate13 Permission Lock (SGPL)" "0,1" hexmask.long.byte 0x0 0.--7. 1. "SG13P,Semaphore access permission enable bit for those 8 Processers. When SGP[M]=1 access permission of Processer-M to this gate is enabled." group.long 0x274++0x3 line.long 0x0 "SEMAG14PC,32 bit register up to 64 gates based on parameter configuration" bitfld.long 0x0 8. "SG14PL,Semaphore Gate14 Permission Lock (SGPL)" "0,1" hexmask.long.byte 0x0 0.--7. 1. "SG14P,Semaphore access permission enable bit for those 8 Processers. When SGP[M]=1 access permission of Processer-M to this gate is enabled." group.long 0x27C++0x3 line.long 0x0 "SEMAG15PC,32 bit register up to 64 gates based on parameter configuration" bitfld.long 0x0 8. "SG15PL,Semaphore Gate 5 Permission Lock (SGPL)" "0,1" hexmask.long.byte 0x0 0.--7. 1. "SG15P,Semaphore access permission enable bit for those 8 Processers. When SGP[M]=1 access permission of Processer-M to this gate is enabled." group.long 0x284++0x3 line.long 0x0 "SEMAG16PC,32 bit register up to 64 gates based on parameter configuration" bitfld.long 0x0 8. "SG16PL,Semaphore Gate16 Permission Lock (SGPL)" "0,1" hexmask.long.byte 0x0 0.--7. 1. "SG16P,Semaphore access permission enable bit for those 8 Processers. When SGP[M]=1 access permission of Processer-M to this gate is enabled." group.long 0x28C++0x3 line.long 0x0 "SEMAG17PC,32 bit register up to 64 gates based on parameter configuration" bitfld.long 0x0 8. "SG17PL,Semaphore Gate17 Permission Lock (SGPL)" "0,1" hexmask.long.byte 0x0 0.--7. 1. "SG17P,Semaphore access permission enable bit for those 8 Processers. When SGP[M]=1 access permission of Processer-M to this gate is enabled." group.long 0x294++0x3 line.long 0x0 "SEMAG18PC,32 bit register up to 64 gates based on parameter configuration" bitfld.long 0x0 8. "SG18PL,Semaphore Gate 8 Permission Lock (SGPL)" "0,1" hexmask.long.byte 0x0 0.--7. 1. "SG18P,Semaphore access permission enable bit for those 8 Processers. When SGP[M]=1 access permission of Processer-M to this gate is enabled." group.long 0x29C++0x3 line.long 0x0 "SEMAG19PC,32 bit register up to 64 gates based on parameter configuration" bitfld.long 0x0 8. "SG19PL,Semaphore Gate19 Permission Lock (SGPL)" "0,1" hexmask.long.byte 0x0 0.--7. 1. "SG19P,Semaphore access permission enable bit for those 8 Processers. When SGP[M]=1 access permission of Processer-M to this gate is enabled." group.long 0x2A4++0x3 line.long 0x0 "SEMAG20PC,32 bit register up to 64 gates based on parameter configuration" bitfld.long 0x0 8. "SG20PL,Semaphore Gate 20 Permission Lock (SGPL)" "0,1" hexmask.long.byte 0x0 0.--7. 1. "SG20P,Semaphore access permission enable bit for those 8 Processers. When SGP[M]=1 access permission of Processer-M to this gate is enabled." group.long 0x2AC++0x3 line.long 0x0 "SEMAG21PC,32 bit register up to 64 gates based on parameter configuration" bitfld.long 0x0 8. "SG21PL,Semaphore Gate 1 Permission Lock (SGPL)" "0,1" hexmask.long.byte 0x0 0.--7. 1. "SG21P,Semaphore access permission enable bit for those 8 Processers. When SGP[M]=1 access permission of Processer-M to this gate is enabled." group.long 0x2B4++0x3 line.long 0x0 "SEMAG22PC,32 bit register up to 64 gates based on parameter configuration" bitfld.long 0x0 8. "SG22PL,Semaphore Gate 2 Permission Lock (SGPL)" "0,1" hexmask.long.byte 0x0 0.--7. 1. "SG22P,Semaphore access permission enable bit for those 8 Processers. When SGP[M]=1 access permission of Processer-M to this gate is enabled." group.long 0x2BC++0x3 line.long 0x0 "SEMAG23PC,32 bit register up to 64 gates based on parameter configuration" bitfld.long 0x0 8. "SG23PL,Semaphore Gate23 Permission Lock (SGPL)" "0,1" hexmask.long.byte 0x0 0.--7. 1. "SG23P,Semaphore access permission enable bit for those 8 Processers. When SGP[M]=1 access permission of Processer-M to this gate is enabled." group.long 0x2C4++0x3 line.long 0x0 "SEMAG24PC,32 bit register up to 64 gates based on parameter configuration" bitfld.long 0x0 8. "SG24PL,Semaphore Gate24 Permission Lock (SGPL)" "0,1" hexmask.long.byte 0x0 0.--7. 1. "SG24P,Semaphore access permission enable bit for those 8 Processers. When SGP[M]=1 access permission of Processer-M to this gate is enabled." group.long 0x2CC++0x3 line.long 0x0 "SEMAG25PC,32 bit register up to 64 gates based on parameter configuration" bitfld.long 0x0 8. "SG25PL,Semaphore Gate25 Permission Lock (SGPL)" "0,1" hexmask.long.byte 0x0 0.--7. 1. "SG25P,Semaphore access permission enable bit for those 8 Processers. When SGP[M]=1 access permission of Processer-M to this gate is enabled." group.long 0x2D4++0x3 line.long 0x0 "SEMAG26PC,32 bit register up to 64 gates based on parameter configuration" bitfld.long 0x0 8. "SG26PL,Semaphore Gate26 Permission Lock (SGPL)" "0,1" hexmask.long.byte 0x0 0.--7. 1. "SG26P,Semaphore access permission enable bit for those 8 Processers. When SGP[M]=1 access permission of Processer-M to this gate is enabled." group.long 0x2DC++0x3 line.long 0x0 "SEMAG27PC,32 bit register up to 64 gates based on parameter configuration" bitfld.long 0x0 8. "SG27PL,Semaphore Gate27 Permission Lock (SGPL)" "0,1" hexmask.long.byte 0x0 0.--7. 1. "SG27P,Semaphore access permission enable bit for those 8 Processers. When SGP[M]=1 access permission of Processer-M to this gate is enabled." group.long 0x2E4++0x3 line.long 0x0 "SEMAG28PC,32 bit register up to 64 gates based on parameter configuration" bitfld.long 0x0 8. "SG28PL,Semaphore Gate 8 Permission Lock (SGPL)" "0,1" hexmask.long.byte 0x0 0.--7. 1. "SG28P,Semaphore access permission enable bit for those 8 Processers. When SGP[M]=1 access permission of Processer-M to this gate is enabled." group.long 0x2EC++0x3 line.long 0x0 "SEMAG29PC,32 bit register up to 64 gates based on parameter configuration" bitfld.long 0x0 8. "SG29PL,Semaphore Gate29 Permission Lock (SGPL)" "0,1" hexmask.long.byte 0x0 0.--7. 1. "SG29P,Semaphore access permission enable bit for those 8 Processers. When SGP[M]=1 access permission of Processer-M to this gate is enabled." group.long 0x2F4++0x3 line.long 0x0 "SEMAG30PC,32 bit register up to 64 gates based on parameter configuration" bitfld.long 0x0 8. "SG30PL,Semaphore Gate 0 Permission Lock (SGPL)" "0,1" hexmask.long.byte 0x0 0.--7. 1. "SG30P,Semaphore access permission enable bit for those 8 Processers. When SGP[M]=1 access permission of Processer-M to this gate is enabled." group.long 0x2FC++0x3 line.long 0x0 "SEMAG31PC,32 bit register up to 64 gates based on parameter configuration" bitfld.long 0x0 8. "SG31PL,Semaphore Gate 1 Permission Lock (SGPL)" "0,1" hexmask.long.byte 0x0 0.--7. 1. "SG31P,Semaphore access permission enable bit for those 8 Processers. When SGP[M]=1 access permission of Processer-M to this gate is enabled." group.long 0x304++0x3 line.long 0x0 "SEMAG32PC,32 bit register up to 64 gates based on parameter configuration" bitfld.long 0x0 8. "SG32PL,Semaphore Gate 2 Permission Lock (SGPL)" "0,1" hexmask.long.byte 0x0 0.--7. 1. "SG32P,Semaphore access permission enable bit for those 8 Processers. When SGP[M]=1 access permission of Processer-M to this gate is enabled." group.long 0x30C++0x3 line.long 0x0 "SEMAG33PC,32 bit register up to 64 gates based on parameter configuration" bitfld.long 0x0 8. "SG33PL,Semaphore Gate33 Permission Lock (SGPL)" "0,1" hexmask.long.byte 0x0 0.--7. 1. "SG33P,Semaphore access permission enable bit for those 8 Processers. When SGP[M]=1 access permission of Processer-M to this gate is enabled." group.long 0x314++0x3 line.long 0x0 "SEMAG34PC,32 bit register up to 64 gates based on parameter configuration" bitfld.long 0x0 8. "SG34PL,Semaphore Gate34 Permission Lock (SGPL)" "0,1" hexmask.long.byte 0x0 0.--7. 1. "SG34P,Semaphore access permission enable bit for those 8 Processers. When SGP[M]=1 access permission of Processer-M to this gate is enabled." group.long 0x31C++0x3 line.long 0x0 "SEMAG35PC,32 bit register up to 64 gates based on parameter configuration" bitfld.long 0x0 8. "SG35PL,Semaphore Gate 5 Permission Lock (SGPL)" "0,1" hexmask.long.byte 0x0 0.--7. 1. "SG35P,Semaphore access permission enable bit for those 8 Processers. When SGP[M]=1 access permission of Processer-M to this gate is enabled." group.long 0x324++0x3 line.long 0x0 "SEMAG36PC,32 bit register up to 64 gates based on parameter configuration" bitfld.long 0x0 8. "SG36PL,Semaphore Gate36 Permission Lock (SGPL)" "0,1" hexmask.long.byte 0x0 0.--7. 1. "SG36P,Semaphore access permission enable bit for those 8 Processers. When SGP[M]=1 access permission of Processer-M to this gate is enabled." group.long 0x32C++0x3 line.long 0x0 "SEMAG37PC,32 bit register up to 64 gates based on parameter configuration" bitfld.long 0x0 8. "SG37PL,Semaphore Gate37 Permission Lock (SGPL)" "0,1" hexmask.long.byte 0x0 0.--7. 1. "SG37P,Semaphore access permission enable bit for those 8 Processers. When SGP[M]=1 access permission of Processer-M to this gate is enabled." group.long 0x334++0x3 line.long 0x0 "SEMAG38PC,32 bit register up to 64 gates based on parameter configuration" bitfld.long 0x0 8. "SG38PL,Semaphore Gate 8 Permission Lock (SGPL)" "0,1" hexmask.long.byte 0x0 0.--7. 1. "SG38P,Semaphore access permission enable bit for those 8 Processers. When SGP[M]=1 access permission of Processer-M to this gate is enabled." group.long 0x33C++0x3 line.long 0x0 "SEMAG39PC,32 bit register up to 64 gates based on parameter configuration" bitfld.long 0x0 8. "SG39PL,Semaphore Gate39 Permission Lock (SGPL)" "0,1" hexmask.long.byte 0x0 0.--7. 1. "SG39P,Semaphore access permission enable bit for those 8 Processers. When SGP[M]=1 access permission of Processer-M to this gate is enabled." group.long 0x344++0x3 line.long 0x0 "SEMAG40PC,32 bit register up to 64 gates based on parameter configuration" bitfld.long 0x0 8. "SG40PL,Semaphore Gate 0 Permission Lock (SGPL)" "0,1" hexmask.long.byte 0x0 0.--7. 1. "SG40P,Semaphore access permission enable bit for those 8 Processers. When SGP[M]=1 access permission of Processer-M to this gate is enabled." group.long 0x34C++0x3 line.long 0x0 "SEMAG41PC,32 bit register up to 64 gates based on parameter configuration" bitfld.long 0x0 8. "SG41PL,Semaphore Gate 1 Permission Lock (SGPL)" "0,1" hexmask.long.byte 0x0 0.--7. 1. "SG41P,Semaphore access permission enable bit for those 8 Processers. When SGP[M]=1 access permission of Processer-M to this gate is enabled." group.long 0x354++0x3 line.long 0x0 "SEMAG42PC,32 bit register up to 64 gates based on parameter configuration" bitfld.long 0x0 8. "SG42PL,Semaphore Gate 2 Permission Lock (SGPL)" "0,1" hexmask.long.byte 0x0 0.--7. 1. "SG42P,Semaphore access permission enable bit for those 8 Processers. When SGP[M]=1 access permission of Processer-M to this gate is enabled." group.long 0x35C++0x3 line.long 0x0 "SEMAG43PC,32 bit register up to 64 gates based on parameter configuration" bitfld.long 0x0 8. "SG43PL,Semaphore Gate43 Permission Lock (SGPL)" "0,1" hexmask.long.byte 0x0 0.--7. 1. "SG43P,Semaphore access permission enable bit for those 8 Processers. When SGP[M]=1 access permission of Processer-M to this gate is enabled." group.long 0x364++0x3 line.long 0x0 "SEMAG44PC,32 bit register up to 64 gates based on parameter configuration" bitfld.long 0x0 8. "SG44PL,Semaphore Gate44 Permission Lock (SGPL)" "0,1" hexmask.long.byte 0x0 0.--7. 1. "SG44P,Semaphore access permission enable bit for those 8 Processers. When SGP[M]=1 access permission of Processer-M to this gate is enabled." group.long 0x36C++0x3 line.long 0x0 "SEMAG45PC,32 bit register up to 64 gates based on parameter configuration" bitfld.long 0x0 8. "SG45PL,Semaphore Gate 5 Permission Lock (SGPL)" "0,1" hexmask.long.byte 0x0 0.--7. 1. "SG45P,Semaphore access permission enable bit for those 8 Processers. When SGP[M]=1 access permission of Processer-M to this gate is enabled." group.long 0x374++0x3 line.long 0x0 "SEMAG46PC,32 bit register up to 64 gates based on parameter configuration" bitfld.long 0x0 8. "SG46PL,Semaphore Gate46 Permission Lock (SGPL)" "0,1" hexmask.long.byte 0x0 0.--7. 1. "SG46P,Semaphore access permission enable bit for those 8 Processers. When SGP[M]=1 access permission of Processer-M to this gate is enabled." group.long 0x37C++0x3 line.long 0x0 "SEMAG47PC,32 bit register up to 64 gates based on parameter configuration" bitfld.long 0x0 8. "SG47PL,Semaphore Gate47 Permission Lock (SGPL)" "0,1" hexmask.long.byte 0x0 0.--7. 1. "SG47P,Semaphore access permission enable bit for those 8 Processers. When SGP[M]=1 access permission of Processer-M to this gate is enabled." group.long 0x384++0x3 line.long 0x0 "SEMAG48PC,32 bit register up to 64 gates based on parameter configuration" bitfld.long 0x0 8. "SG48PL,Semaphore Gate 8 Permission Lock (SGPL)" "0,1" hexmask.long.byte 0x0 0.--7. 1. "SG48P,Semaphore access permission enable bit for those 8 Processers. When SGP[M]=1 access permission of Processer-M to this gate is enabled." group.long 0x38C++0x3 line.long 0x0 "SEMAG49PC,32 bit register up to 64 gates based on parameter configuration" bitfld.long 0x0 8. "SG49PL,Semaphore Gate49 Permission Lock (SGPL)" "0,1" hexmask.long.byte 0x0 0.--7. 1. "SG49P,Semaphore access permission enable bit for those 8 Processers. When SGP[M]=1 access permission of Processer-M to this gate is enabled." group.long 0x394++0x3 line.long 0x0 "SEMAG50PC,32 bit register up to 64 gates based on parameter configuration" bitfld.long 0x0 8. "SG50PL,Semaphore Gate 0 Permission Lock (SGPL)" "0,1" hexmask.long.byte 0x0 0.--7. 1. "SG50P,Semaphore access permission enable bit for those 8 Processers. When SGP[M]=1 access permission of Processer-M to this gate is enabled." group.long 0x39C++0x3 line.long 0x0 "SEMAG51PC,32 bit register up to 64 gates based on parameter configuration" bitfld.long 0x0 8. "SG51PL,Semaphore Gate 1 Permission Lock (SGPL)" "0,1" hexmask.long.byte 0x0 0.--7. 1. "SG51P,Semaphore access permission enable bit for those 8 Processers. When SGP[M]=1 access permission of Processer-M to this gate is enabled." group.long 0x3A4++0x3 line.long 0x0 "SEMAG52PC,32 bit register up to 64 gates based on parameter configuration" bitfld.long 0x0 8. "SG52PL,Semaphore Gate 2 Permission Lock (SGPL)" "0,1" hexmask.long.byte 0x0 0.--7. 1. "SG52P,Semaphore access permission enable bit for those 8 Processers. When SGP[M]=1 access permission of Processer-M to this gate is enabled." group.long 0x3AC++0x3 line.long 0x0 "SEMAG53PC,32 bit register up to 64 gates based on parameter configuration" bitfld.long 0x0 8. "SG53PL,Semaphore Gate53 Permission Lock (SGPL)" "0,1" hexmask.long.byte 0x0 0.--7. 1. "SG53P,Semaphore access permission enable bit for those 8 Processers. When SGP[M]=1 access permission of Processer-M to this gate is enabled." group.long 0x3B4++0x3 line.long 0x0 "SEMAG54PC,32 bit register up to 64 gates based on parameter configuration" bitfld.long 0x0 8. "SG54PL,Semaphore Gate54 Permission Lock (SGPL)" "0,1" hexmask.long.byte 0x0 0.--7. 1. "SG54P,Semaphore access permission enable bit for those 8 Processers. When SGP[M]=1 access permission of Processer-M to this gate is enabled." group.long 0x3BC++0x3 line.long 0x0 "SEMAG55PC,32 bit register up to 64 gates based on parameter configuration" bitfld.long 0x0 8. "SG55PL,Semaphore Gate 5 Permission Lock (SGPL)" "0,1" hexmask.long.byte 0x0 0.--7. 1. "SG55P,Semaphore access permission enable bit for those 8 Processers. When SGP[M]=1 access permission of Processer-M to this gate is enabled." group.long 0x3C4++0x3 line.long 0x0 "SEMAG56PC,32 bit register up to 64 gates based on parameter configuration" bitfld.long 0x0 8. "SG56PL,Semaphore Gate56 Permission Lock (SGPL)" "0,1" hexmask.long.byte 0x0 0.--7. 1. "SG56P,Semaphore access permission enable bit for those 8 Processers. When SGP[M]=1 access permission of Processer-M to this gate is enabled." group.long 0x3CC++0x3 line.long 0x0 "SEMAG57PC,32 bit register up to 64 gates based on parameter configuration" bitfld.long 0x0 8. "SG57PL,Semaphore Gate57 Permission Lock (SGPL)" "0,1" hexmask.long.byte 0x0 0.--7. 1. "SG57P,Semaphore access permission enable bit for those 8 Processers. When SGP[M]=1 access permission of Processer-M to this gate is enabled." group.long 0x3D4++0x3 line.long 0x0 "SEMAG58PC,32 bit register up to 64 gates based on parameter configuration" bitfld.long 0x0 8. "SG58PL,Semaphore Gate 8 Permission Lock (SGPL)" "0,1" hexmask.long.byte 0x0 0.--7. 1. "SG58P,Semaphore access permission enable bit for those 8 Processers. When SGP[M]=1 access permission of Processer-M to this gate is enabled." group.long 0x3DC++0x3 line.long 0x0 "SEMAG59PC,32 bit register up to 64 gates based on parameter configuration" bitfld.long 0x0 8. "SG59PL,Semaphore Gate59 Permission Lock (SGPL)" "0,1" hexmask.long.byte 0x0 0.--7. 1. "SG59P,Semaphore access permission enable bit for those 8 Processers. When SGP[M]=1 access permission of Processer-M to this gate is enabled." group.long 0x3E4++0x3 line.long 0x0 "SEMAG60PC,32 bit register up to 64 gates based on parameter configuration" bitfld.long 0x0 8. "SG60PL,Semaphore Gate 0 Permission Lock (SGPL)" "0,1" hexmask.long.byte 0x0 0.--7. 1. "SG60P,Semaphore access permission enable bit for those 8 Processers. When SGP[M]=1 access permission of Processer-M to this gate is enabled." group.long 0x3EC++0x3 line.long 0x0 "SEMAG61PC,32 bit register up to 64 gates based on parameter configuration" bitfld.long 0x0 8. "SG61PL,Semaphore Gate 1 Permission Lock (SGPL)" "0,1" hexmask.long.byte 0x0 0.--7. 1. "SG61P,Semaphore access permission enable bit for those 8 Processers. When SGP[M]=1 access permission of Processer-M to this gate is enabled." group.long 0x3F4++0x3 line.long 0x0 "SEMAG62PC,32 bit register up to 64 gates based on parameter configuration" bitfld.long 0x0 8. "SG62PL,Semaphore Gate 2 Permission Lock (SGPL)" "0,1" hexmask.long.byte 0x0 0.--7. 1. "SG62P,Semaphore access permission enable bit for those 8 Processers. When SGP[M]=1 access permission of Processer-M to this gate is enabled." group.long 0x3FC++0xF line.long 0x0 "SEMAG63PC,32 bit register up to 64 gates based on parameter configuration" bitfld.long 0x0 8. "SG63PL,Semaphore Gate63 Permission Lock (SGPL)" "0,1" hexmask.long.byte 0x0 0.--7. 1. "SG63P,Semaphore access permission enable bit for those 8 Processers. When SGP[M]=1 access permission of Processer-M to this gate is enabled." line.long 0x4 "SGR,semaphone gate reset" bitfld.long 0x4 25. "GSGREL,Global Semaphore Gate Reset Enable Lock (GSGREL) sticky bit which locks" "0,1" bitfld.long 0x4 24. "GSGRE,Global Semaphore Gate Reset Enable (GSGRE) when 1 GSGR is enabled when 0 GSGT is disabled" "0,1" hexmask.long.byte 0x4 16.--23. 1. "RESERVED,Reserved bit" newline hexmask.long.byte 0x4 8.--15. 1. "GSGR,When writes to 1 semaphore gates which locked by corresponding processor are released." bitfld.long 0x4 0. "SGR,Semaphore Gate Reset. When writes to 1 all semaphore gates which locked by current processor are released each processor has a SGR" "0,1" line.long 0x8 "SGI0,Semaphore gates status change interrupt status-0" hexmask.long 0x8 0.--31. 1. "SGI0,interrupt status of Semaphore gate[31:0].Hardware set when registered interrupt notification of related semaphore gate is released. Software can clear this interrupt by writes 1 to related bit. Be noted that if SGI0=32hFFFF_FFFF writing.." line.long 0xC "SGI1,semaphore gate status change interrupt status-1" hexmask.long 0xC 0.--31. 1. "SGI1,interrupt status of Semaphore gate[63:32].Hardware set when registered interrupt notification of related semaphore gate is released. Software can clear this interrupt by writes 1 to related bit. Be noted that if SGI0=32hFFFF_FFFF writing.." group.long 0x500++0x1F line.long 0x0 "CPU0_MASTERID,CPU0_MASTERID" bitfld.long 0x0 31. "CPU0_MASTER_ID3_LOCK,CPU0_MASTER_ID3_LOCK" "0,1" hexmask.long.byte 0x0 24.--30. 1. "CPU0_MASTER_ID3,CPU0_MASTER_ID3" bitfld.long 0x0 23. "CPU0_MASTER_ID2_LOCK,CPU0_MASTER_ID2_LOCK" "0,1" hexmask.long.byte 0x0 16.--22. 1. "CPU0_MASTER_ID2,CPU0_MASTER_ID2" newline bitfld.long 0x0 15. "CPU0_MASTER_ID1_LOCK,CPU0_MASTER_ID1_LOCK" "0,1" hexmask.long.byte 0x0 8.--14. 1. "CPU0_MASTER_ID1,CPU0_MASTER_ID1" bitfld.long 0x0 7. "CPU0_MASTER_ID0_LOCK,CPU0_MASTER_ID0_LOCK" "0,1" hexmask.long.byte 0x0 0.--6. 1. "CPU0_MASTER_ID0,CPU0_MASTER_ID0" line.long 0x4 "CPU1_MASTERID,CPU1_MASTERID" bitfld.long 0x4 31. "CPU1_MASTER_ID3_LOCK,CPU1_MASTER_ID3_LOCK" "0,1" hexmask.long.byte 0x4 24.--30. 1. "CPU1_MASTER_ID3,CPU1_MASTER_ID3" bitfld.long 0x4 23. "CPU1_MASTER_ID2_LOCK,CPU1_MASTER_ID2_LOCK" "0,1" hexmask.long.byte 0x4 16.--22. 1. "CPU1_MASTER_ID2,CPU1_MASTER_ID2" newline bitfld.long 0x4 15. "CPU1_MASTER_ID1_LOCK,CPU1_MASTER_ID1_LOCK" "0,1" hexmask.long.byte 0x4 8.--14. 1. "CPU1_MASTER_ID1,CPU1_MASTER_ID1" bitfld.long 0x4 7. "CPU1_MASTER_ID0_LOCK,CPU1_MASTER_ID0_LOCK" "0,1" hexmask.long.byte 0x4 0.--6. 1. "CPU1_MASTER_ID0,CPU1_MASTER_ID0" line.long 0x8 "CPU2_MASTERID,CPU2_MASTERID" bitfld.long 0x8 31. "CPU2_MASTER_ID3_LOCK,CPU2_MASTER_ID3_LOCK" "0,1" hexmask.long.byte 0x8 24.--30. 1. "CPU2_MASTER_ID3,CPU2_MASTER_ID3" bitfld.long 0x8 23. "CPU2_MASTER_ID2_LOCK,CPU2_MASTER_ID2_LOCK" "0,1" hexmask.long.byte 0x8 16.--22. 1. "CPU2_MASTER_ID2,CPU2_MASTER_ID2" newline bitfld.long 0x8 15. "CPU2_MASTER_ID1_LOCK,CPU2_MASTER_ID1_LOCK" "0,1" hexmask.long.byte 0x8 8.--14. 1. "CPU2_MASTER_ID1,CPU2_MASTER_ID1" bitfld.long 0x8 7. "CPU2_MASTER_ID0_LOCK,CPU2_MASTER_ID0_LOCK" "0,1" hexmask.long.byte 0x8 0.--6. 1. "CPU2_MASTER_ID0,CPU2_MASTER_ID0" line.long 0xC "CPU3_MASTERID,CPU3_MASTERID" bitfld.long 0xC 31. "CPU3_MASTER_ID3_LOCK,CPU3_MASTER_ID3_LOCK" "0,1" hexmask.long.byte 0xC 24.--30. 1. "CPU3_MASTER_ID3,CPU3_MASTER_ID3" bitfld.long 0xC 23. "CPU3_MASTER_ID2_LOCK,CPU3_MASTER_ID2_LOCK" "0,1" hexmask.long.byte 0xC 16.--22. 1. "CPU3_MASTER_ID2,CPU3_MASTER_ID2" newline bitfld.long 0xC 15. "CPU3_MASTER_ID1_LOCK,CPU3_MASTER_ID1_LOCK" "0,1" hexmask.long.byte 0xC 8.--14. 1. "CPU3_MASTER_ID1,CPU3_MASTER_ID1" bitfld.long 0xC 7. "CPU3_MASTER_ID0_LOCK,CPU3_MASTER_ID0_LOCK" "0,1" hexmask.long.byte 0xC 0.--6. 1. "CPU3_MASTER_ID0,CPU3_MASTER_ID0" line.long 0x10 "CPU4_MASTERID,CPU4_MASTERID" bitfld.long 0x10 31. "CPU4_MASTER_ID3_LOCK,CPU4_MASTER_ID3_LOCK" "0,1" hexmask.long.byte 0x10 24.--30. 1. "CPU4_MASTER_ID3,CPU4_MASTER_ID3" bitfld.long 0x10 23. "CPU4_MASTER_ID2_LOCK,CPU4_MASTER_ID2_LOCK" "0,1" hexmask.long.byte 0x10 16.--22. 1. "CPU4_MASTER_ID2,CPU4_MASTER_ID2" newline bitfld.long 0x10 15. "CPU4_MASTER_ID1_LOCK,CPU4_MASTER_ID1_LOCK" "0,1" hexmask.long.byte 0x10 8.--14. 1. "CPU4_MASTER_ID1,CPU4_MASTER_ID1" bitfld.long 0x10 7. "CPU4_MASTER_ID0_LOCK,CPU4_MASTER_ID0_LOCK" "0,1" hexmask.long.byte 0x10 0.--6. 1. "CPU4_MASTER_ID0,CPU4_MASTER_ID0" line.long 0x14 "CPU5_MASTERID,CPU5_MASTERID" bitfld.long 0x14 31. "CPU5_MASTER_ID3_LOCK,CPU5_MASTER_ID3_LOCK" "0,1" hexmask.long.byte 0x14 24.--30. 1. "CPU5_MASTER_ID3,CPU5_MASTER_ID3" bitfld.long 0x14 23. "CPU5_MASTER_ID2_LOCK,CPU5_MASTER_ID2_LOCK" "0,1" hexmask.long.byte 0x14 16.--22. 1. "CPU5_MASTER_ID2,CPU5_MASTER_ID2" newline bitfld.long 0x14 15. "CPU5_MASTER_ID1_LOCK,CPU5_MASTER_ID1_LOCK" "0,1" hexmask.long.byte 0x14 8.--14. 1. "CPU5_MASTER_ID1,CPU5_MASTER_ID1" bitfld.long 0x14 7. "CPU5_MASTER_ID0_LOCK,CPU5_MASTER_ID0_LOCK" "0,1" hexmask.long.byte 0x14 0.--6. 1. "CPU5_MASTER_ID0,CPU5_MASTER_ID0" line.long 0x18 "CPU6_MASTERID,CPU6_MASTERID" bitfld.long 0x18 31. "CPU6_MASTER_ID3_LOCK,CPU6_MASTER_ID3_LOCK" "0,1" hexmask.long.byte 0x18 24.--30. 1. "CPU6_MASTER_ID3,CPU6_MASTER_ID3" bitfld.long 0x18 23. "CPU6_MASTER_ID2_LOCK,CPU6_MASTER_ID2_LOCK" "0,1" hexmask.long.byte 0x18 16.--22. 1. "CPU6_MASTER_ID2,CPU6_MASTER_ID2" newline bitfld.long 0x18 15. "CPU6_MASTER_ID1_LOCK,CPU6_MASTER_ID1_LOCK" "0,1" hexmask.long.byte 0x18 8.--14. 1. "CPU6_MASTER_ID1,CPU6_MASTER_ID1" bitfld.long 0x18 7. "CPU6_MASTER_ID0_LOCK,CPU6_MASTER_ID0_LOCK" "0,1" hexmask.long.byte 0x18 0.--6. 1. "CPU6_MASTER_ID0,CPU6_MASTER_ID0" line.long 0x1C "CPU7_MASTERID,CPU7_MASTERID" bitfld.long 0x1C 31. "CPU7_MASTER_ID3_LOCK,CPU7_MASTER_ID3_LOCK" "0,1" hexmask.long.byte 0x1C 24.--30. 1. "CPU7_MASTER_ID3,CPU7_MASTER_ID3" bitfld.long 0x1C 23. "CPU7_MASTER_ID2_LOCK,CPU7_MASTER_ID2_LOCK" "0,1" hexmask.long.byte 0x1C 16.--22. 1. "CPU7_MASTER_ID2,CPU7_MASTER_ID2" newline bitfld.long 0x1C 15. "CPU7_MASTER_ID1_LOCK,CPU7_MASTER_ID1_LOCK" "0,1" hexmask.long.byte 0x1C 8.--14. 1. "CPU7_MASTER_ID1,CPU7_MASTER_ID1" bitfld.long 0x1C 7. "CPU7_MASTER_ID0_LOCK,CPU7_MASTER_ID0_LOCK" "0,1" hexmask.long.byte 0x1C 0.--6. 1. "CPU7_MASTER_ID0,CPU7_MASTER_ID0" rgroup.long 0x1000++0x3 line.long 0x0 "TX_BUFFER,the TX BUFFER . same for all CPUs" rgroup.long 0x2000++0x3 line.long 0x0 "RX_CPU0_BUFFER,the RX CPU0 buffer address" rgroup.long 0x3000++0x3 line.long 0x0 "RX_CPU1_BUFFER,the RX CPU1 buffer address" rgroup.long 0x4000++0x3 line.long 0x0 "RX_CPU2_BUFFER,the RX CPU2 buffer address" rgroup.long 0x5000++0x3 line.long 0x0 "RX_CPU3_BUFFER,the RX CPU3 buffer address" rgroup.long 0x6000++0x3 line.long 0x0 "RX_CPU4_BUFFER,the RX CPU4 buffer address" rgroup.long 0x7000++0x3 line.long 0x0 "RX_CPU5_BUFFER,the RX CPU5 buffer address" rgroup.long 0x8000++0x3 line.long 0x0 "RX_CPU6_BUFFER,the RX CPU6 buffer address" rgroup.long 0x9000++0x3 line.long 0x0 "RX_CPU7_BUFFER,the RX CPU7 buffer address" endif tree.end tree "MSHC (SD/eMMC)" sif (CORENAME()=="CORTEXR5F") repeat 4. (increment 1. 1.) (list ad:0xF4180000 ad:0xF4190000 ad:0xF41A0000 ad:0xF41B0000) tree "MSHC$1" base $2 tree "DWC_mshc_block (This register block defines the standard SD Host Controller register set)" group.long 0x0++0x3 line.long 0x0 "SDMASA_R,This register is used to configure a 32-bit Block Count or an SDMA System Address based on the Host Version 4 Enable bit in the Host Control 2 register. This register is applicable for both SD and eMMC modes." hexmask.long 0x0 0.--31. 1. "BLOCKCNT_SDMASA,32-bit Block Count (SDMA System Address) - SDMA System Address (Host Version 4 Enable = 0): This register contains the system memory address for an SDMA transfer in the 32-bit addressing mode. When the Host Controller stops an SDMA.." group.word 0x4++0x3 line.word 0x0 "BLOCKSIZE_R,This register is used to configure an SDMA buffer boundary and the number of bytes in a data block. This register is applicable for both SD and eMMC modes." newline rbitfld.word 0x0 15. "RSVD_BLOCKSIZE15,This bit of the BLOCKSIZE_R register is reserved. It always returns 0." "0,1" newline bitfld.word 0x0 12.--14. "SDMA_BUF_BDARY,SDMA Buffer Boundary These bits specify the size of contiguous buffer in system memory. The SDMA transfer waits at every boundary specified by these fields and the Host Controller generates the DMA interrupt to request the Host Driver to.." "0,1,2,3,4,5,6,7" newline hexmask.word 0x0 0.--11. 1. "XFER_BLOCK_SIZE,Transfer Block Size These bits specify the block size of data transfers. In case of memory it is set to 512 bytes. It can be accessed only if no transaction is executing. Read operations during transfers may return an invalid value and.." line.word 0x2 "BLOCKCOUNT_R,This register is used to configure the number of data blocks. This register is applicable for both SD and eMMC modes." newline hexmask.word 0x2 0.--15. 1. "BLOCK_CNT,16-bit Block Count - If the Host Version 4 Enable bit is set 0 or the 16-bit Block Count register is set to non-zero the 16-bit Block Count register is selected. - If the Host Version 4 Enable bit is set 1 and the 16-bit Block Count register.." group.long 0x8++0x3 line.long 0x0 "ARGUMENT_R,This register is used to configure the SD/eMMC command argument." hexmask.long 0x0 0.--31. 1. "ARGUMENT,Command Argument These bits specify the SD/eMMC command argument that is specified in bits 39-8 of the Command format." group.word 0xC++0x3 line.word 0x0 "XFER_MODE_R,This register is used to control the operation of data transfers for an SD/eMMC mode. The Host driver sets this register before issuing a command that transfers data." newline hexmask.word.byte 0x0 9.--15. 1. "RSVD,These bits of the XFER_MODE_R register are reserved. They always return 0." newline bitfld.word 0x0 8. "RESP_INT_DISABLE,Response Interrupt Disable The Host Controller supports response check function to avoid overhead of response error check by the Host driver. Response types of only R1 and R5 can be checked by the Controller. If Host Driver checks the.." "Response Interrupt is enabled,Response Interrupt is disabled" newline bitfld.word 0x0 7. "RESP_ERR_CHK_ENABLE,Response Error Check Enable The Host Controller supports response check function to avoid overhead of response error check by Host driver. Response types of only R1 and R5 can be checked by the Controller. If the Host Controller.." "Response Error Check is disabled,Response Error Check is enabled" newline bitfld.word 0x0 6. "RESP_TYPE,Response Type R1/R5 This bit selects either R1 or R5 as a response type when the Response Error Check is selected. Error statuses checked in R1: - OUT_OF_RANGE - ADDRESS_ERROR - BLOCK_LEN_ERROR - WP_VIOLATION - CARD_IS_LOCKED - COM_CRC_ERROR -.." "R1,R5" newline bitfld.word 0x0 5. "MULTI_BLK_SEL,Multi/Single Block Select This bit is set when issuing multiple-block transfer commands using the DAT line. If this bit is set to 0 it is not necessary to set the Block Count register. 0x1: Multiple Block 0x0: Single Block" "Single Block,Multiple Block" newline bitfld.word 0x0 4. "DATA_XFER_DIR,Data Transfer Direction Select This bit defines the direction of DAT line data transfers. This bit is set to 1 by the Host Driver to transfer data from the SD/eMMC card to the Host Controller and it is set to 0 for all other commands. 0x1:.." "Write,Read" newline bitfld.word 0x0 2.--3. "AUTO_CMD_ENABLE,Auto Command Enable This field determines use of Auto Command functions. Note: In SDIO this field must be set as 00b (Auto Command Disabled). 0x1: Auto CMD12 Enable 0x2: Auto CMD23 Enable 0x3: Auto CMD Auto Select 0x0: Auto Command.." "Auto Command Disabled,Auto CMD12 Enable,Auto CMD23 Enable,Auto CMD Auto Select" newline bitfld.word 0x0 1. "BLOCK_COUNT_ENABLE,Block Count Enable This bit is used to enable the Block Count register which is relevant for multiple block transfers. If this bit is set to 0 the Block Count register is disabled which is useful in executing an infinite transfer." "Disable,Enable" newline bitfld.word 0x0 0. "DMA_ENABLE,DMA Enable This bit enables the DMA functionality. If this bit is set to 1 a DMA operation begins when the Host Driver writes to the Command register. You can select one of the DMA modes by using DMA Select in the Host Control 1 register." "No data transfer or Non-DMA data transfer,DMA Data transfer" line.word 0x2 "CMD_R,This register is used to provide the information related to a command and a response packet. This register is applicable for an SD/eMMC mode." newline rbitfld.word 0x2 14.--15. "RSVD,These bits of the CMD_R register are reserved. They always return 0." "0,1,2,3" newline hexmask.word.byte 0x2 8.--13. 1. "CMD_INDEX,Command Index These bits are set to the command number that is specified in bits 45-40 of the Command Format." newline bitfld.word 0x2 6.--7. "CMD_TYPE,Command Type These bits indicate the command type. Note: While issuing Abort CMD using CMD12/CMD52 or reset CMD using CMD0/CMD52 CMD_TYPE field shall be set to 0x3. 0x3: Abort 0x0: Normal 0x2: Resume 0x1: Suspend" "Normal,Suspend,Resume,Abort" newline bitfld.word 0x2 5. "DATA_PRESENT_SEL,Data Present Select This bit is set to 1 to indicate that data is present and that the data is transferred using the DAT line. This bit is set to 0 in the following instances: - Command using the CMD line - Command with no data transfer.." "No Data Present,Data Present" newline bitfld.word 0x2 4. "CMD_IDX_CHK_ENABLE,Command Index Check Enable This bit enables the Host Controller to check the index field in the response to verify if it has the same value as the command index. If the value is not the same it is reported as a Command Index error." "Disable,Enable" newline bitfld.word 0x2 3. "CMD_CRC_CHK_ENABLE,Command CRC Check Enable This bit enables the Host Controller to check the CRC field in the response. If an error is detected it is reported as a Command CRC error. Note: - CRC Check enable must be set to 0 for the command with no.." "Disable,Enable" newline bitfld.word 0x2 2. "SUB_CMD_FLAG,Sub Command Flag This bit distinguishes between a main command and a sub command. 0x0: Main Command 0x1: Sub Command" "Main Command,Sub Command" newline bitfld.word 0x2 0.--1. "RESP_TYPE_SELECT,Response Type Select This bit indicates the type of response expected from the card. 0x0: No Response 0x1: Response Length 136 0x2: Response Length 48 0x3: Response Length 48; Check Busy after response" "No Response,Response Length 136,Response Length 48,Response Length 48; Check Busy after response" rgroup.long 0x10++0xF line.long 0x0 "RESP01_R,This register stores 39-08 bits of the Response Field for an SD/eMMC mode. The response for an SD/eMMC command can be a maximum of 128 bits. These 128 bits are segregated into four 32-bit registers: RESP01_R. RESP23_R. RESP45_R and RESP67_R." hexmask.long 0x0 0.--31. 1. "RESP01,Command Response These bits reflect 39-8 bits of SD/eMMC Response Field. Note: For Auto CMD the 32-bit response (bits 39-8 of the Response Field) is updated in the RESP67_R register." line.long 0x4 "RESP23_R,This register stores 71-40 bits of the Response Field for an SD/eMMC mode. This register is used to store the response from the cards. The response can be a maximum of 128 bits. These 128 bits are segregated into four 32-bit registers: RESP01_R." hexmask.long 0x4 0.--31. 1. "RESP23,Command Response These bits reflect 71-40 bits of the SD/eMMC Response Field." line.long 0x8 "RESP45_R,This register stores 103-72 bits of the Response Field for an SD/eMMC mode. The response for SD/eMMC command can be a maximum of 128 bits. These 128 bits are segregated into four 32-bit registers: RESP01_R. RESP23_R. RESP45_R and RESP67_R." hexmask.long 0x8 0.--31. 1. "RESP45,Command Response These bits reflect 103-72 bits of the Response Field." line.long 0xC "RESP67_R,This register stores 135-104 bits of the Response Field for an SD/eMMC mode. The SD/eMMC response can be a maximum of 128 bits. These 128 bits are segregated into four 32-bit registers: RESP01_R. RESP23_R. RESP45_R and RESP67_R." hexmask.long 0xC 0.--31. 1. "RESP67,Command Response These bits reflect bits 135-104 of SD/EMMC Response Field. Note: For Auto CMD this register also reflects the 32-bit response (bits 39-8 of the Response Field)." group.long 0x20++0x3 line.long 0x0 "BUF_DATA_R,This register is used to access the packet buffer. This register is applicable for an SD/eMMC/UHS-II mode." hexmask.long 0x0 0.--31. 1. "BUF_DATA,Buffer Data These bits enable access to the Host Controller packet buffer." rgroup.long 0x24++0x3 line.long 0x0 "PSTATE_REG,This register indicates the present status of the Host Controller. This register is applicable for an SD/eMMC/UHS-II mode." bitfld.long 0x0 31. "UHS2_IF_DETECT,UHS-II Interface Detection For SD/eMMC mode this bit always returns 0. 0x0: UHS-II interface is not detected 0x1: UHS-II interface is detected" "UHS-II interface is not detected,UHS-II interface is detected" newline bitfld.long 0x0 30. "LANE_SYNC,Lane Synchronization For SD/eMMC mode this bit always returns 0. 0x0: UHS-II PHY is not initialized 0x1: UHS-II PHY is initialized" "UHS-II PHY is not initialized,UHS-II PHY is initialized" newline bitfld.long 0x0 29. "IN_DORMANT_ST,In Dormant Status For SD/eMMC mode this bit always returns 0. 0x0: Not in DORMANT state 0x1: In DORMANT state" "Not in DORMANT state,In DORMANT state" newline bitfld.long 0x0 28. "SUB_CMD_STAT,Sub Command Status This bit is used to distinguish between a main command and a sub command status. 0x0: Main Command Status 0x1: Sub Command Status" "Main Command Status,Sub Command Status" newline bitfld.long 0x0 27. "CMD_ISSUE_ERR,Command Not Issued by Error This bit is set if a command cannot be issued after setting the command register due to an error except the Auto CMD12 error. 0x0: No error for issuing a command 0x1: Command cannot be issued" "No error for issuing a command,Command cannot be issued" newline bitfld.long 0x0 26. "RSVD_26,This bit of the PRESENT_ST_R register is reserved bits. It always returns 0." "0,1" newline bitfld.long 0x0 25. "HOST_REG_VOL,Host Regulator Voltage Stable This bit is used to check whether the host regulator voltage is stable for switching the voltage of UHS-I mode. This bit reflects the synchronized value of the host_reg_vol_stable signal. 0x0: Host Regulator.." "Host Regulator Voltage is not stable,Host Regulator Voltage is stable" newline bitfld.long 0x0 24. "CMD_LINE_LVL,Command-Line Signal Level This bit is used to check the CMD line level to recover from errors and for debugging. These bits reflect the value of the sd_cmd_in signal." "0,1" newline hexmask.long.byte 0x0 20.--23. 1. "DAT_3_0,DAT[3:0] Line Signal Level This bit is used to check the DAT line level to recover from errors and for debugging. These bits reflect the value of the sd_dat_in (lower nibble) signal." newline bitfld.long 0x0 19. "WR_PROTECT_SW_LVL,Write Protect Switch Pin Level This bit is supported only for memory and combo cards. This bit reflects the synchronized value of the card_write_prot signal. 0x0: Write protected 0x1: Write enabled" "Write protected,Write enabled" newline bitfld.long 0x0 18. "CARD_DETECT_PIN_LEVEL,Card Detect Pin Level This bit reflects the inverse synchronized value of the card_detect_n signal. 0x0: No card present 0x1: Card Present" "No card present,Card Present" newline bitfld.long 0x0 17. "CARD_STABLE,Card Stable This bit indicates the stability of the Card Detect Pin Level. A card is not detected if this bit is set to 1 and the value of the CARD_INSERTED bit is 0. 0x0: Reset or Debouncing 0x1: No Card or Inserted" "Reset or Debouncing,No Card or Inserted" newline bitfld.long 0x0 16. "CARD_INSERTED,Card Inserted This bit indicates whether a card has been inserted. The Host Controller debounces this signal so that Host Driver need not wait for it to stabilize. 0x0: Reset Debouncing or No card 0x1: Card Inserted" "Reset,Card Inserted" newline hexmask.long.byte 0x0 12.--15. 1. "RSVD_15_12,These bits of the PRESENT_STAT_R register are reserved. They always return 0." newline bitfld.long 0x0 11. "BUF_RD_ENABLE,Buffer Read Enable This bit is used for non-DMA transfers. This bit is set if valid data exists in the Host buffer. 0x0: Read disable 0x1: Read enable" "Read disable,Read enable" newline bitfld.long 0x0 10. "BUF_WR_ENABLE,Buffer Write Enable This bit is used for non-DMA transfers. This bit is set if space is available for writing data. 0x0: Write disable 0x1: Write enable" "Write disable,Write enable" newline bitfld.long 0x0 9. "RD_XFER_ACTIVE,Read Transfer Active This bit indicates whether a read transfer is active for SD/eMMC mode. 0x1: Transferring data 0x0: No valid data" "No valid data,Transferring data" newline bitfld.long 0x0 8. "WR_XFER_ACTIVE,Write Transfer Active This status indicates whether a write transfer is active for SD/eMMC mode. 0x1: Transferring data 0x0: No valid data" "No valid data,Transferring data" newline hexmask.long.byte 0x0 4.--7. 1. "DAT_7_4,DAT[7:4] Line Signal Level This bit is used to check the DAT line level to recover from errors and for debugging. These bits reflect the value of the sd_dat_in (upper nibble) signal." newline bitfld.long 0x0 3. "RE_TUNE_REQ,Re-Tuning Request DWC_mshc does not generate retuning request. The software must maintain the Retuning timer." "0,1" newline bitfld.long 0x0 2. "DAT_LINE_ACTIVE,DAT Line Active (SD/eMMC Mode only) This bit indicates whether one of the DAT lines on the SD/eMMC bus is in use. In the case of read transactions this bit indicates whether a read transfer is executing on the SD/eMMC bus. In the case of.." "DAT Line Inactive,DAT Line Active" newline bitfld.long 0x0 1. "CMD_INHIBIT_DAT,Command Inhibit (DAT) This bit is applicable for SD/eMMC mode and is generated if either DAT line active or Read transfer active is set to 1. If this bit is set to 0 it indicates that the Host Controller can issue subsequent SD/eMMC.." "Can issue command which used DAT line,Cannot issue command which used DAT line" newline bitfld.long 0x0 0. "CMD_INHIBIT,Command Inhibit (CMD) This bit indicates the following : - SD/eMMC mode: If this bit is set to 0 it indicates that the CMD line is not in use and the Host controller can issue an SD/eMMC command using the CMD line. This bit is set when the.." "Host Controller is ready to issue a command,Host Controller is not ready to issue a command" group.byte 0x28++0x3 line.byte 0x0 "HOST_CTRL1_R,This register is used to control the operation of the Host Controller. This register is applicable for an SD/eMMC/UHS-II mode." newline bitfld.byte 0x0 7. "CARD_DETECT_SIG_SEL,Card Detect Signal Selection This bit selects a source for card detection. When the source for the card detection is switched the interrupt must be disabled during the switching period. 0x1: Card Detect Test Level is selected (for.." "SDCD#,Card Detect Test Level is selected" newline bitfld.byte 0x0 6. "CARD_DETECT_TEST_LVL,Card Detect Test Level This bit is enabled while the Card Detect Signal Selection is set to 1 and it indicates whether a card inserted or not. 0x1: Card Inserted 0x0: No Card" "No Card,Card Inserted" newline bitfld.byte 0x0 5. "EXT_DAT_XFER,Extended Data Transfer Width This bit controls 8-bit bus width mode of embedded device. 0x0: Bus Width is selected by the Data Transfer Width 0x1: 8-bit Bus Width" "Bus Width is selected by the Data Transfer Width,?" newline bitfld.byte 0x0 3.--4. "DMA_SEL,DMA Select This field is used to select the DMA type. When Host Version 4 Enable is 1 in Host Control 2 register: - 0x0 - SDMA is selected - 0x1 - Reserved - 0x2 - ADMA2 is selected - 0x3 - ADMA2 or ADMA3 is selected When Host Version 4 Enable is.." "SDMA is selected,Reserved,ADMA2 is selected,ADMA2 or ADMA3 is selected" newline bitfld.byte 0x0 2. "HIGH_SPEED_EN,High Speed Enable (SD/eMMC Mode only) In SD/eMMC mode this bit is used to determine the selection of preset value for High Speed mode. Before setting this bit the Host Driver checks the High Speed Support in the Capabilities register." "Normal Speed mode,High Speed mode" newline bitfld.byte 0x0 1. "DAT_XFER_WIDTH,Data Transfer Width For SD/eMMC mode this bit selects the data transfer width of the Host Controller. The Host Driver sets it to match the data width of the SD/eMMC card. 0x1: 4-bit mode 0x0: 1-bit mode" "?,bit mode" newline bitfld.byte 0x0 0. "LED_CTRL,LED Control This bit is used to caution the user not to remove the card while the SD card is being accessed. The value is reflected on the led_control signal. 0x0: LED off 0x1: LED on" "LED off,LED on" line.byte 0x1 "PWR_CTRL_R,This register is used to control the bus power for the Card. This register is applicable for an SD. eMMC. and UHS-II modes." newline bitfld.byte 0x1 5.--7. "SD_BUS_VOL_VDD2,SD Bus Voltage Select for VDD2. This is irrelevant for SD/eMMC card. 0x6: Not used 0x7: Not used 0x0: VDD2 Not Supported 0x1: Reserved 0x2: Reserved 0x3: Reserved 0x4: Reserved for 1.2V 0x5: 1.8V" "VDD2 Not Supported,Reserved,Reserved,Reserved,Reserved for 1,?,Not used,Not used" newline bitfld.byte 0x1 4. "SD_BUS_PWR_VDD2,SD Bus Power for VDD2. This is irrelevant for SD/eMMC card. 0x0: Power off 0x1: Power on" "Power off,Power on" newline bitfld.byte 0x1 1.--3. "SD_BUS_VOL_VDD1,SD Bus Voltage Select for VDD1/eMMC Bus Voltage Select for VDD These bits enable the Host Driver to select the voltage level for an SD/eMMC card. Before setting this register the Host Driver checks the Voltage Support bits in the.." "Reserved,Reserved,Reserved,Reserved,Reserved,?,?,?" newline bitfld.byte 0x1 0. "SD_BUS_PWR_VDD1,SD Bus Power for VDD1 This bit enables VDD1 power of the card. This setting is available on the sd_vdd1_on output of DWC_mshc so that it can be used to control the VDD1 power supply of the card. Before setting this bit the SD Host Driver.." "Power off,Power on" line.byte 0x2 "BGAP_CTRL_R,This register is used by the host driver to control any operation related to Block Gap. This register is applicable for an SD/eMMC/UHS-II mode." newline hexmask.byte 0x2 4.--7. 1. "RSVD_7_4,These bits of the Block Gap Control register are reserved. They always return 0." newline bitfld.byte 0x2 3. "INT_AT_BGAP,Interrupt At Block Gap This bit is valid only in the 4-bit mode of an SDIO card and is used to select a sample point in the interrupt cycle. Setting to 1 enables interrupt detection at the block gap for a multiple block transfer. 0x0:.." "Disabled,Enabled" newline bitfld.byte 0x2 2. "RD_WAIT_CTRL,Read Wait Control This bit is used to enable the read wait protocol to stop read data using DAT[2] line if the card supports read wait. Otherwise the Host Controller has to stop the card clock to hold the read data. 0x0: Disable Read Wait.." "Disable Read Wait Control,Enable Read Wait Control" newline bitfld.byte 0x2 1. "CONTINUE_REQ,Continue Request This bit is used to restart the transaction which was stopped using the Stop At Block Gap Request. The Host Controller automatically clears this bit when the transaction restarts. If stop at block gap request is set to 1.." "No Affect,Restart" newline bitfld.byte 0x2 0. "STOP_BG_REQ,Stop At Block Gap Request This bit is used to stop executing read and write transactions at the next block gap for non-DMA SDMA and ADMA transfers. 0x1: Stop 0x0: Transfer" "Transfer,Stop" line.byte 0x3 "WUP_CTRL_R,This register is mandatory for the Host Controller. but the wakeup functionality depends on the Host Controller system hardware and software. The Host Driver maintains voltage on the SD Bus by setting the SD Bus Power to 1 in the Power Control.." newline hexmask.byte 0x3 3.--7. 1. "RSVD_7_3,These bits of Wakeup Control register are reserved. They always return 0." newline bitfld.byte 0x3 2. "CARD_REMOVAL,Wakeup Event Enable on SD Card Removal This bit enables wakeup event through Card Removal assertion in the Normal Interrupt Status register. For the SDIO card Wake Up Support (FN_WUS) in the Card Information Structure (CIS) register does.." "Disable,Enable" newline bitfld.byte 0x3 1. "CARD_INSERT,Wakeup Event Enable on SD Card Insertion This bit enables wakeup event through Card Insertion assertion in the Normal Interrupt Status register. FN_WUS (Wake Up Support) in CIS does not affect this bit. 0x0: Disable 0x1: Enable" "Disable,Enable" newline bitfld.byte 0x3 0. "CARD_INT,Wakeup Event Enable on Card Interrupt This bit enables wakeup event through a Card Interrupt assertion in the Normal Interrupt Status register. This bit can be set to 1 if FN_WUS (Wake Up Support) in CIS is set to 1. 0x0: Disable 0x1: Enable" "Disable,Enable" group.word 0x2C++0x1 line.word 0x0 "CLK_CTRL_R,This register controls SDCLK (card clock) in an SD/eMMC mode and RCLK in the UHS-II mode. This register is applicable for an SD/eMMC/UHS-II mode." newline hexmask.word.byte 0x0 8.--15. 1. "FREQ_SEL,SDCLK/RCLK Frequency Select These bits are used to select the frequency of the SDCLK signal. These bits depend on setting of Preset Value Enable in the Host Control 2 register. If Preset Value Enable = 0 these bits are set by the Host Driver." newline bitfld.word 0x0 6.--7. "UPPER_FREQ_SEL,These bits specify the upper 2 bits of 10-bit SDCLK/RCLK Frequency Select control. The value is reflected on the upper 2 bits of the card_clk_freq_sel signal." "0,1,2,3" newline bitfld.word 0x0 5. "CLK_GEN_SELECT,Clock Generator Select This bit is used to select the clock generator mode in SDCLK/RCLK Frequency Select. If Preset Value Enable = 0 this bit is set by the Host Driver. If Preset Value Enable = 1 this bit is automatically set to a value.." "Divided Clock Mode,Programmable Clock Mode" newline rbitfld.word 0x0 4. "RSVD_4,This bit of the CLK_CTRL_R register is reserved. It always returns 0." "0,1" newline bitfld.word 0x0 3. "PLL_ENABLE,PLL Enable This bit is used to activate the PLL (applicable when Host Version 4 Enable = 1). When Host Version 4 Enable = 0 INTERNAL_CLK_EN bit may be used to activate PLL. The value is reflected on the card_clk_en signal. Note: If this bit.." "PLL is in low power mode,PLL is enabled" newline bitfld.word 0x0 2. "SD_CLK_EN,SD/eMMC Clock Enable This bit stops the SDCLK or RCLK when set to 0. The SDCLK/RCLK Frequency Select bit can be changed when this bit is set to 0. The value is reflected on the clk2card_on pin. 0x0: Disable providing SDCLK/RCLK 0x1: Enable.." "Disable providing SDCLK/RCLK,Enable providing SDCLK/RCLK" newline rbitfld.word 0x0 1. "INTERNAL_CLK_STABLE,Internal Clock Stable This bit enables the Host Driver to check the clock stability twice after the Internal Clock Enable bit is set and after the PLL Enable bit is set. This bit reflects the synchronized value of the intclk_stable.." "Not Ready,Ready" newline bitfld.word 0x0 0. "INTERNAL_CLK_EN,Internal Clock Enable This bit is set to 0 when the Host Driver is not using the Host Controller or the Host Controller awaits a wakeup interrupt. The Host Controller must stop its internal clock to enter a very low power state. However.." "Stop,Oscillate" group.byte 0x2E++0x1 line.byte 0x0 "TOUT_CTRL_R,This register is used to set the Data Timeout Counter value for an SD/eMMC mode according to the timer clock defined by the Capabilities register. while initializig the Host Controller." newline hexmask.byte 0x0 4.--7. 1. "RSVD_7_4,These bits of the Timeout Control register are reserved. They always return 0." newline hexmask.byte 0x0 0.--3. 1. "TOUT_CNT,Data Timeout Counter Value. This value determines the interval by which DAT line timeouts are detected. The Timeout clock frequency is generated by dividing the base clock TMCLK value by this value. When setting this register prevent.." line.byte 0x1 "SW_RST_R,This register is used to generate a reset pulse by writing 1 to each bit of this register. After completing the reset. the Host Controller clears each bit. As it takes some time to complete a software reset. the Host Driver confirms that these.." newline hexmask.byte 0x1 3.--7. 1. "RSVD_7_3,These bits of the SW_RST_R register are reserved. They always return 0." newline bitfld.byte 0x1 2. "SW_RST_DAT,Software Reset For DAT line This bit is used in SD/eMMC mode and it resets only a part of the data circuit and the DMA circuit is also reset. The following registers and bits are cleared by this bit: - Buffer Data Port register -- Buffer is.." "Work,Reset" newline bitfld.byte 0x1 1. "SW_RST_CMD,Software Reset For CMD line This bit resets only a part of the command circuit to be able to issue a command. This reset is effective only for a command issuing circuit (including response error statuses related to Command Inhibit (CMD).." "Work,Reset" newline bitfld.byte 0x1 0. "SW_RST_ALL,Software Reset For All This reset affects the entire Host Controller except for the card detection circuit. During its initialization the Host Driver sets this bit to 1 to reset the Host Controller. All registers are reset except the.." "Work,Reset" group.word 0x30++0xB line.word 0x0 "NORMAL_INT_STAT_R,This register reflects the status of the Normal Interrupt. This register is applicable for an SD/eMMC/UHS-II mode." newline rbitfld.word 0x0 15. "ERR_INTERRUPT,Error Interrupt If any of the bits in the Error Interrupt Status register are set then this bit is set. 0x0: No Error 0x1: Error" "No Error,Error" newline bitfld.word 0x0 14. "CQE_EVENT,Command Queuing Event This status is set if Command Queuing/Crypto related event has occurred in eMMC/SD mode. Read CQHCI's CQIS/CRNQIS register for more details. 0x0: No Event 0x1: Command Queuing Event is detected" "No Event,Command Queuing Event is detected" newline rbitfld.word 0x0 13. "FX_EVENT,FX Event This status is set when R[14] of response register is set to 1 and Response Type R1/R5 is set to 0 in Transfer Mode register. This interrupt is used with response check function. 0x0: No Event 0x1: FX Event is detected" "No Event,FX Event is detected" newline rbitfld.word 0x0 12. "RE_TUNE_EVENT,Re-tuning Event This bit is set if the Re-Tuning Request changes from 0 to 1. Re-Tuning request is not supported." "0,1" newline rbitfld.word 0x0 11. "INT_C,INT_C (Embedded) This bit is set if INT_C is enabled and if INT_C# pin is in low level. The INT_C# pin is not supported." "0,1" newline rbitfld.word 0x0 10. "INT_B,INT_B (Embedded) This bit is set if INT_B is enabled and if INT_B# pin is in low level. The INT_B# pin is not supported." "0,1" newline rbitfld.word 0x0 9. "INT_A,INT_A (Embedded) This bit is set if INT_A is enabled and if INT_A# pin is in low level. The INT_A# pin is not supported." "0,1" newline rbitfld.word 0x0 8. "CARD_INTERRUPT,Card Interrupt This bit reflects the synchronized value of: - DAT[1] Interrupt Input for SD Mode - DAT[2] Interrupt Input for UHS-II Mode 0x0: No Card Interrupt 0x1: Generate Card Interrupt" "No Card Interrupt,Generate Card Interrupt" newline bitfld.word 0x0 7. "CARD_REMOVAL,Card Removal This bit is set if the Card Inserted in the Present State register changes from 1 to 0. 0x0: Card state stable or Debouncing 0x1: Card Removed" "Card state stable or Debouncing,Card Removed" newline bitfld.word 0x0 6. "CARD_INSERTION,Card Insertion This bit is set if the Card Inserted in the Present State register changes from 0 to 1. 0x0: Card state stable or Debouncing 0x1: Card Inserted" "Card state stable or Debouncing,Card Inserted" newline bitfld.word 0x0 5. "BUF_RD_READY,Buffer Read Ready This bit is set if the Buffer Read Enable changes from 0 to 1. 0x0: Not ready to read buffer 0x1: Ready to read buffer" "Not ready to read buffer,Ready to read buffer" newline bitfld.word 0x0 4. "BUF_WR_READY,Buffer Write Ready This bit is set if the Buffer Write Enable changes from 0 to 1. 0x0: Not ready to write buffer 0x1: Ready to write buffer" "Not ready to write buffer,Ready to write buffer" newline bitfld.word 0x0 3. "DMA_INTERRUPT,DMA Interrupt This bit is set if the Host Controller detects the SDMA Buffer Boundary during transfer. In case of ADMA by setting the Int field in the descriptor table the Host controller generates this interrupt. This interrupt is not.." "No DMA Interrupt,DMA Interrupt is generated" newline bitfld.word 0x0 2. "BGAP_EVENT,Block Gap Event This bit is set when both read/write transaction is stopped at block gap due to a Stop at Block Gap Request. 0x0: No Block Gap Event 0x1: Transaction stopped at block gap" "No Block Gap Event,Transaction stopped at block gap" newline bitfld.word 0x0 1. "XFER_COMPLETE,Transfer Complete This bit is set when a read/write transfer and a command with status busy is completed. 0x0: Not complete 0x1: Command execution is completed" "Not complete,Command execution is completed" newline bitfld.word 0x0 0. "CMD_COMPLETE,Command Complete In an SD/eMMC Mode this bit is set when the end bit of a response except for Auto CMD12 and Auto CMD23. This interrupt is not generated when the Response Interrupt Disable in Transfer Mode Register is set to 1. 0x0: No.." "No command complete,Command Complete" line.word 0x2 "ERROR_INT_STAT_R,This register enables an interrupt when the Error Interrupt Status Enable is enabled and at least one of the statuses is set to 1. Writing to 1 clears the bit and writing to 0 retains the bit unchanged. Signals defined in this register.." newline bitfld.word 0x2 15. "VENDOR_ERR3,This bit (VENDOR_ERR3) of the ERROR_INT_STAT_R register is reserved. It always returns 0." "0,1" newline bitfld.word 0x2 14. "VENDOR_ERR2,This bit (VENDOR_ERR2) of the ERROR_INT_STAT_R register is reserved. It always returns 0." "0,1" newline bitfld.word 0x2 13. "VENDOR_ERR1,This bit (VENDOR_ERR1) of the ERROR_INT_STAT_R register is reserved. It always returns 0." "0,1" newline bitfld.word 0x2 12. "BOOT_ACK_ERR,Boot Acknowledgement Error This bit is set when there is a timeout for boot acknowledgement or when detecting boot ack status having a value other than 010. This is applicable only when boot acknowledgement is expected in eMMC mode. 0x0: No.." "No error,Error" newline bitfld.word 0x2 11. "RESP_ERR,Response Error Host Controller Version 4.00 supports response error check function to avoid overhead of response error check by Host Driver during DMA execution. If Response Error Check Enable is set to 1 in the Transfer Mode register Host.." "No error,Error" newline bitfld.word 0x2 10. "TUNING_ERR,Tuning Error This bit is set when an unrecoverable error is detected in a tuning circuit except during the tuning procedure (occurrence of an error during tuning procedure is indicated by Sampling Clock Select in the Host Control 2 register)." "No error,Error" newline bitfld.word 0x2 9. "ADMA_ERR,ADMA Error This bit is set when the Host Controller detects error during ADMA-based data transfer. The error could be due to following reasons: - Error response received from System bus (Master I/F) - ADMA3 ADMA2 Descriptors invalid - CQE Task.." "No error,Error" newline bitfld.word 0x2 8. "AUTO_CMD_ERR,Auto CMD Error This error status is used by Auto CMD12 and Auto CMD23 in SD/eMMC mode. This bit is set when detecting that any of the bits D00 to D05 in Auto CMD Error Status register has changed from 0 to 1. D07 is effective in case of Auto.." "No error,Error" newline bitfld.word 0x2 7. "CUR_LMT_ERR,Current Limit Error By setting the SD Bus Power bit in the Power Control register the Host Controller is requested to supply power for the SD Bus. If the Host Controller supports the Current Limit function it can be protected from an.." "No error,Power Fail" newline bitfld.word 0x2 6. "DATA_END_BIT_ERR,Data End Bit Error This error occurs in SD/eMMC mode either when detecting 0 at the end bit position of read data that uses the DAT line or at the end bit position of the CRC status. 0x0: No error 0x1: Error" "No error,Error" newline bitfld.word 0x2 5. "DATA_CRC_ERR,Data CRC Error This error occurs in SD/eMMC mode when detecting CRC error when transferring read data which uses the DAT line when detecting the Write CRC status having a value of other than 010 or when write CRC status timeout. 0x0: No.." "No error,Error" newline bitfld.word 0x2 4. "DATA_TOUT_ERR,Data Timeout Error This bit is set in SD/eMMC mode when detecting one of the following timeout conditions: - Busy timeout for R1b R5b type - Busy timeout after Write CRC status - Write CRC Status timeout - Read Data timeout 0x0: No error.." "No error,Time out" newline bitfld.word 0x2 3. "CMD_IDX_ERR,Command Index Error This bit is set if a Command Index error occurs in the command respons in SD/eMMC mode. 0x0: No error 0x1: Error" "No error,Error" newline bitfld.word 0x2 2. "CMD_END_BIT_ERR,Command End Bit Error This bit is set when detecting that the end bit of a command response is 0 in SD/eMMC mode. 0x0: No error 0x1: End Bit error generated" "No error,End Bit error generated" newline bitfld.word 0x2 1. "CMD_CRC_ERR,Command CRC Error Command CRC Error is generated in SD/eMMC mode for following two cases. - If a response is returned and the Command Timeout Error is set to 0 (indicating no timeout) this bit is set to 1 when detecting a CRC error in the.." "No error,CRC error generated" newline bitfld.word 0x2 0. "CMD_TOUT_ERR,Command Timeout Error In SD/eMMC Mode this bit is set only if no response is returned within 64 SD clock cycles from the end bit of the command. If the Host Controller detects a CMD line conflict along with Command CRC Error bit this bit.." "No error,Time out" line.word 0x4 "NORMAL_INT_STAT_EN_R,This register enables the Interrupt Status for Normal Interrupt Status register (NORMAL_INT_STAT_R) when NORMAL_INT_STAT_R is set to 1. This register is applicable for an SD/eMMC/UHS-II mode." newline rbitfld.word 0x4 15. "RSVD_15,This bit of the NORMAL_INT_STAT_EN_R register is reserved. It always returns 0." "0,1" newline bitfld.word 0x4 14. "CQE_EVENT_STAT_EN,CQE Event Status Enable 0x0: Masked 0x1: Enabled" "Masked,Enabled" newline bitfld.word 0x4 13. "FX_EVENT_STAT_EN,FX Event Status Enable This bit is added from Version 4.10. 0x0: Masked 0x1: Enabled" "Masked,Enabled" newline bitfld.word 0x4 12. "RE_TUNE_EVENT_STAT_EN,Re-Tuning Event (UHS-I only) Status Enable 0x0: Masked 0x1: Enabled" "Masked,Enabled" newline bitfld.word 0x4 11. "INT_C_STAT_EN,INT_C (Embedded) Status Enable If this bit is set to 0 the Host Controller clears the interrupt request to the System. The Host Driver may clear this bit before servicing the INT_C and may set this bit again after all interrupt requests to.." "Masked,Enabled" newline bitfld.word 0x4 10. "INT_B_STAT_EN,INT_B (Embedded) Status Enable If this bit is set to 0 the Host Controller clears the interrupt request to the System. The Host Driver may clear this bit before servicing the INT_B and may set this bit again after all interrupt requests to.." "Masked,Enabled" newline bitfld.word 0x4 9. "INT_A_STAT_EN,INT_A (Embedded) Status Enable If this bit is set to 0 the Host Controller clears the interrupt request to the System. The Host Driver may clear this bit before servicing the INT_A and may set this bit again after all interrupt requests to.." "Masked,Enabled" newline bitfld.word 0x4 8. "CARD_INTERRUPT_STAT_EN,Card Interrupt Status Enable If this bit is set to 0 the Host Controller clears the interrupt request to the System. The Card Interrupt detection is stopped when this bit is cleared and restarted when this bit is set to 1. The.." "Masked,Enabled" newline bitfld.word 0x4 7. "CARD_REMOVAL_STAT_EN,Card Removal Status Enable 0x0: Masked 0x1: Enabled" "Masked,Enabled" newline bitfld.word 0x4 6. "CARD_INSERTION_STAT_EN,Card Insertion Status Enable 0x0: Masked 0x1: Enabled" "Masked,Enabled" newline bitfld.word 0x4 5. "BUF_RD_READY_STAT_EN,Buffer Read Ready Status Enable 0x0: Masked 0x1: Enabled" "Masked,Enabled" newline bitfld.word 0x4 4. "BUF_WR_READY_STAT_EN,Buffer Write Ready Status Enable 0x0: Masked 0x1: Enabled" "Masked,Enabled" newline bitfld.word 0x4 3. "DMA_INTERRUPT_STAT_EN,DMA Interrupt Status Enable 0x0: Masked 0x1: Enabled" "Masked,Enabled" newline bitfld.word 0x4 2. "BGAP_EVENT_STAT_EN,Block Gap Event Status Enable 0x0: Masked 0x1: Enabled" "Masked,Enabled" newline bitfld.word 0x4 1. "XFER_COMPLETE_STAT_EN,Transfer Complete Status Enable 0x0: Masked 0x1: Enabled" "Masked,Enabled" newline bitfld.word 0x4 0. "CMD_COMPLETE_STAT_EN,Command Complete Status Enable 0x0: Masked 0x1: Enabled" "Masked,Enabled" line.word 0x6 "ERROR_INT_STAT_EN_R,This register sets the Interrupt Status for Error Interrupt Status register (ERROR_INT_STAT_R). when ERROR_INT_STAT_EN_R is set to 1. This register is applicable for an SD/eMMC/UHS-II mode." newline bitfld.word 0x6 15. "VENDOR_ERR_STAT_EN3,The 15th bit of Error Interrupt Status Enable register is reserved. 0x0: Masked 0x1: Enabled" "Masked,Enabled" newline bitfld.word 0x6 14. "VENDOR_ERR_STAT_EN2,The 14th bit of Error Interrupt Status Enable register is reserved. 0x0: Masked 0x1: Enabled" "Masked,Enabled" newline bitfld.word 0x6 13. "VENDOR_ERR_STAT_EN1,The 13th bit of Error Interrupt Status Enable register is reserved. 0x0: Masked 0x1: Enabled" "Masked,Enabled" newline bitfld.word 0x6 12. "BOOT_ACK_ERR_STAT_EN,Boot Acknowledgment Error (eMMC Mode only) Setting this bit to 1 enables setting of Boot Acknowledgment Error in Error Interrupt Status register (ERROR_INT_STAT_R). 0x0: Masked 0x1: Enabled" "Masked,Enabled" newline bitfld.word 0x6 11. "RESP_ERR_STAT_EN,Response Error Status Enable (SD Mode only) 0x0: Masked 0x1: Enabled" "Masked,Enabled" newline bitfld.word 0x6 10. "TUNING_ERR_STAT_EN,Tuning Error Status Enable (UHS-I Mode only) 0x0: Masked 0x1: Enabled" "Masked,Enabled" newline bitfld.word 0x6 9. "ADMA_ERR_STAT_EN,ADMA Error Status Enable 0x0: Masked 0x1: Enabled" "Masked,Enabled" newline bitfld.word 0x6 8. "AUTO_CMD_ERR_STAT_EN,Auto CMD Error Status Enable (SD/eMMC Mode only). 0x0: Masked 0x1: Enabled" "Masked,Enabled" newline bitfld.word 0x6 7. "CUR_LMT_ERR_STAT_EN,Current Limit Error Status Enable 0x0: Masked 0x1: Enabled" "Masked,Enabled" newline bitfld.word 0x6 6. "DATA_END_BIT_ERR_STAT_EN,Data End Bit Error Status Enable (SD/eMMC Mode only). 0x0: Masked 0x1: Enabled" "Masked,Enabled" newline bitfld.word 0x6 5. "DATA_CRC_ERR_STAT_EN,Data CRC Error Status Enable (SD/eMMC Mode only) 0x0: Masked 0x1: Enabled" "Masked,Enabled" newline bitfld.word 0x6 4. "DATA_TOUT_ERR_STAT_EN,Data Timeout Error Status Enable (SD/eMMC Mode only) 0x0: Masked 0x1: Enabled" "Masked,Enabled" newline bitfld.word 0x6 3. "CMD_IDX_ERR_STAT_EN,Command Index Error Status Enable (SD/eMMC Mode only) 0x0: Masked 0x1: Enabled" "Masked,Enabled" newline bitfld.word 0x6 2. "CMD_END_BIT_ERR_STAT_EN,Command End Bit Error Status Enable (SD/eMMC Mode only) 0x0: Masked 0x1: Enabled" "Masked,Enabled" newline bitfld.word 0x6 1. "CMD_CRC_ERR_STAT_EN,Command CRC Error Status Enable (SD/eMMC Mode only) 0x0: Masked 0x1: Enabled" "Masked,Enabled" newline bitfld.word 0x6 0. "CMD_TOUT_ERR_STAT_EN,Command Timeout Error Status Enable (SD/eMMC Mode only). 0x0: Masked 0x1: Enabled" "Masked,Enabled" line.word 0x8 "NORMAL_INT_SIGNAL_EN_R,This register is used to select the interrupt status that is indicated to the Host System as the interrupt. All these status bits share the same 1-bit interrupt line. Setting any of these bits to 1. enables interrupt generation." newline rbitfld.word 0x8 15. "RSVD_15,This bit of the NORMAL_INT_STAT_R register is reserved. It always returns 0." "0,1" newline bitfld.word 0x8 14. "CQE_EVENT_SIGNAL_EN,Command Queuing Engine Event Signal Enable 0x0: Masked 0x1: Enabled" "Masked,Enabled" newline bitfld.word 0x8 13. "FX_EVENT_SIGNAL_EN,FX Event Signal Enable 0x0: Masked 0x1: Enabled" "Masked,Enabled" newline bitfld.word 0x8 12. "RE_TUNE_EVENT_SIGNAL_EN,Re-Tuning Event (UHS-I only) Signal Enable. 0x0: Masked 0x1: Enabled" "Masked,Enabled" newline bitfld.word 0x8 11. "INT_C_SIGNAL_EN,INT_C (Embedded) Signal Enable 0x0: Masked 0x1: Enabled" "Masked,Enabled" newline bitfld.word 0x8 10. "INT_B_SIGNAL_EN,INT_B (Embedded) Signal Enable 0x0: Masked 0x1: Enabled" "Masked,Enabled" newline bitfld.word 0x8 9. "INT_A_SIGNAL_EN,INT_A (Embedded) Signal Enable 0x0: Masked 0x1: Enabled" "Masked,Enabled" newline bitfld.word 0x8 8. "CARD_INTERRUPT_SIGNAL_EN,Card Interrupt Signal Enable 0x0: Masked 0x1: Enabled" "Masked,Enabled" newline bitfld.word 0x8 7. "CARD_REMOVAL_SIGNAL_EN,Card Removal Signal Enable 0x0: Masked 0x1: Enabled" "Masked,Enabled" newline bitfld.word 0x8 6. "CARD_INSERTION_SIGNAL_EN,Card Insertion Signal Enable 0x0: Masked 0x1: Enabled" "Masked,Enabled" newline bitfld.word 0x8 5. "BUF_RD_READY_SIGNAL_EN,Buffer Read Ready Signal Enable 0x0: Masked 0x1: Enabled" "Masked,Enabled" newline bitfld.word 0x8 4. "BUF_WR_READY_SIGNAL_EN,Buffer Write Ready Signal Enable 0x0: Masked 0x1: Enabled" "Masked,Enabled" newline bitfld.word 0x8 3. "DMA_INTERRUPT_SIGNAL_EN,DMA Interrupt Signal Enable 0x0: Masked 0x1: Enabled" "Masked,Enabled" newline bitfld.word 0x8 2. "BGAP_EVENT_SIGNAL_EN,Block Gap Event Signal Enable 0x0: Masked 0x1: Enabled" "Masked,Enabled" newline bitfld.word 0x8 1. "XFER_COMPLETE_SIGNAL_EN,Transfer Complete Signal Enable 0x0: Masked 0x1: Enabled" "Masked,Enabled" newline bitfld.word 0x8 0. "CMD_COMPLETE_SIGNAL_EN,Command Complete Signal Enable 0x0: Masked 0x1: Enabled" "Masked,Enabled" line.word 0xA "ERROR_INT_SIGNAL_EN_R,This register is used to select the interrupt status that is notified to the Host System as an interrupt. All these status bits share the same 1-bit interrupt line. Setting any of these bits to 1 enables interrupt generation. This.." newline bitfld.word 0xA 15. "VENDOR_ERR_SIGNAL_EN3,The 16th bit of Error Interrupt Signal Enable is reserved. 0x0: Masked 0x1: Enabled" "Masked,Enabled" newline bitfld.word 0xA 14. "VENDOR_ERR_SIGNAL_EN2,The 15th bit of Error Interrupt Signal Enable is reserved. 0x0: Masked 0x1: Enabled" "Masked,Enabled" newline bitfld.word 0xA 13. "VENDOR_ERR_SIGNAL_EN1,The 14th bit of Error Interrupt Signal Enable is reserved. 0x0: Masked 0x1: Enabled" "Masked,Enabled" newline bitfld.word 0xA 12. "BOOT_ACK_ERR_SIGNAL_EN,Boot Acknowledgment Error (eMMC Mode only). Setting this bit to 1 enables generating interrupt signal when Boot Acknowledgement Error in Error Interrupt Status register is set. 0x0: Masked 0x1: Enabled" "Masked,Enabled" newline bitfld.word 0xA 11. "RESP_ERR_SIGNAL_EN,Response Error Signal Enable (SD Mode only) 0x0: Masked 0x1: Enabled" "Masked,Enabled" newline bitfld.word 0xA 10. "TUNING_ERR_SIGNAL_EN,Tuning Error Signal Enable (UHS-I Mode only) 0x0: Masked 0x1: Enabled" "Masked,Enabled" newline bitfld.word 0xA 9. "ADMA_ERR_SIGNAL_EN,ADMA Error Signal Enable 0x0: Masked 0x1: Enabled" "Masked,Enabled" newline bitfld.word 0xA 8. "AUTO_CMD_ERR_SIGNAL_EN,Auto CMD Error Signal Enable (SD/eMMC Mode only) 0x0: Masked 0x1: Enabled" "Masked,Enabled" newline bitfld.word 0xA 7. "CUR_LMT_ERR_SIGNAL_EN,Current Limit Error Signal Enable 0x0: Masked 0x1: Enabled" "Masked,Enabled" newline bitfld.word 0xA 6. "DATA_END_BIT_ERR_SIGNAL_EN,Data End Bit Error Signal Enable (SD/eMMC Mode only) 0x0: Masked 0x1: Enabled" "Masked,Enabled" newline bitfld.word 0xA 5. "DATA_CRC_ERR_SIGNAL_EN,Data CRC Error Signal Enable (SD/eMMC Mode only) 0x0: Masked 0x1: Enabled" "Masked,Enabled" newline bitfld.word 0xA 4. "DATA_TOUT_ERR_SIGNAL_EN,Data Timeout Error Signal Enable (SD/eMMC Mode only) 0x0: Masked 0x1: Enabled" "Masked,Enabled" newline bitfld.word 0xA 3. "CMD_IDX_ERR_SIGNAL_EN,Command Index Error Signal Enable (SD/eMMC Mode only) 0x0: No error 0x1: Error" "No error,Error" newline bitfld.word 0xA 2. "CMD_END_BIT_ERR_SIGNAL_EN,Command End Bit Error Signal Enable (SD/eMMC Mode only) 0x0: Masked 0x1: Enabled" "Masked,Enabled" newline bitfld.word 0xA 1. "CMD_CRC_ERR_SIGNAL_EN,Command CRC Error Signal Enable (SD/eMMC Mode only) 0x0: Masked 0x1: Enabled" "Masked,Enabled" newline bitfld.word 0xA 0. "CMD_TOUT_ERR_SIGNAL_EN,Command Timeout Error Signal Enable (SD/eMMC Mode only) 0x0: Masked 0x1: Enabled" "Masked,Enabled" rgroup.word 0x3C++0x1 line.word 0x0 "AUTO_CMD_STAT_R,This register is used to indicate the CMD12 response error of Auto CMD12. and the CMD23 response error of Auto CMD23. The Host driver can determine the kind of Auto CMD12/CMD23 errors that can occur in this register. Auto CMD23 errors are.." newline hexmask.word.byte 0x0 8.--15. 1. "RSVD_15_8,These bits of the AUTO_CMD_STAT_R register are reserved bits. They always return 0." newline bitfld.word 0x0 7. "CMD_NOT_ISSUED_AUTO_CMD12,Command Not Issued By Auto CMD12 Error If this bit is set to 1 CMD_wo_DAT is not executed due to an Auto CMD12 Error (D04-D01) in this register. This bit is set to 0 when Auto CMD Error is generated by Auto CMD23. 0x0: No Error.." "No Error,Not Issued" newline bitfld.word 0x0 6. "RSVD_6,This bit of the AUTO_CMD_STAR_R register is reserved. It always returns 0." "0,1" newline bitfld.word 0x0 5. "AUTO_CMD_RESP_ERR,Auto CMD Response Error This bit is set when Response Error Check Enable in the Transfer Mode register is set to 1 and an error is detected in R1 response of either Auto CMD12 or CMD13. This status is ignored if any bit between D00 to.." "No Error,Error" newline bitfld.word 0x0 4. "AUTO_CMD_IDX_ERR,Auto CMD Index Error This bit is set if the command index error occurs in response to a command. 0x0: No Error 0x1: Error" "No Error,Error" newline bitfld.word 0x0 3. "AUTO_CMD_EBIT_ERR,Auto CMD End Bit Error This bit is set when detecting that the end bit of command response is 0. 0x0: No Error 0x1: End Bit Error Generated" "No Error,End Bit Error Generated" newline bitfld.word 0x0 2. "AUTO_CMD_CRC_ERR,Auto CMD CRC Error This bit is set when detecting a CRC error in the command response. 0x0: No Error 0x1: CRC Error Generated" "No Error,CRC Error Generated" newline bitfld.word 0x0 1. "AUTO_CMD_TOUT_ERR,Auto CMD Timeout Error This bit is set if no response is returned with 64 SDCLK cycles from the end bit of the command. If this bit is set to 1 error status bits (D04-D01) are meaningless. 0x0: No Error 0x1: Time out" "No Error,Time out" newline bitfld.word 0x0 0. "AUTO_CMD12_NOT_EXEC,Auto CMD12 Not Executed If multiple memory block data transfer is not started due to a command error this bit is not set because it is not necessary to issue an Auto CMD12. Setting this bit to 1 means that the Host Controller cannot.." "Executed,Not Executed" group.word 0x3E++0x1 line.word 0x0 "HOST_CTRL2_R,This register is used to control how the Host Controller operates. This register is applicable for an SD/eMMC/UHS-II mode." newline bitfld.word 0x0 15. "PRESET_VAL_ENABLE,Preset Value Enable This bit enables automatic selection of SDCLK frequency and Driver strength Preset Value registers. When Preset Value Enable is set SDCLK frequency generation (Frequency Select and Clock Generator Select) and the.." "SDCLK and Driver Strength are controlled by Host..,Automatic Selection by Preset Value are Enabled" newline bitfld.word 0x0 14. "ASYNC_INT_ENABLE,Asynchronous Interrupt Enable This bit can be set if a card supports asynchronous interrupts and Asynchronous Interrupt Support is set to 1 in the Capabilities register. 0x0: Disabled 0x1: Enabled" "Disabled,Enabled" newline bitfld.word 0x0 13. "ADDRESSING,64-bit Addressing This bit is effective when Host Version 4 Enable is set to 1. 0x0: 32 bits addressing 0x1: 64 bits addressing" "0,1" newline bitfld.word 0x0 12. "HOST_VER4_ENABLE,Host Version 4 Enable This bit selects either Version 3.00 compatible mode or Version 4 mode. Functions of following fields are modified for Host Version 4 mode: - SDMA Address: SDMA uses ADMA System Address (05Fh-058h) instead of SDMA.." "Version 3,Version 4 mode" newline bitfld.word 0x0 11. "CMD23_ENABLE,CMD23 Enable If the card supports CMD23 this bit is set to 1. This bit is used to select Auto CMD23 or Auto CMD12 for ADMA3 data transfer. 0x0: Auto CMD23 is disabled 0x1: Auto CMD23 is enabled" "Auto CMD23 is disabled,Auto CMD23 is enabled" newline bitfld.word 0x0 10. "ADMA2_LEN_MODE,ADMA2 Length Mode This bit selects ADMA2 Length mode to be either 16-bit or 26-bit. 0x0: 16-bit Data Length Mode 0x1: 26-bit Data Length Mode" "0,1" newline rbitfld.word 0x0 9. "RSVD_9,This bit of the HOST_CTRL2_R register is reserved. It always returns 0." "0,1" newline bitfld.word 0x0 8. "UHS2_IF_ENABLE,UHS-II Interface Enable This bit is used to enable the UHS-II Interface. The value is reflected on the uhs2_if_en pin. 0x0: SD/eMMC Interface Enabled 0x1: UHS-II Interface Enabled" "SD/eMMC Interface Enabled,UHS-II Interface Enabled" newline bitfld.word 0x0 7. "SAMPLE_CLK_SEL,Sampling Clock Select This bit is used by the Host Controller to select the sampling clock in SD/eMMC mode to receive CMD and DAT. This bit is set by the tuning procedure and is valid after the completion of tuning (when Execute Tuning is.." "Fixed clock is used to sample data,Tuned clock is used to sample data" newline bitfld.word 0x0 6. "EXEC_TUNING,Execute Tuning This bit is set to 1 to start the tuning procedure in UHS-I/eMMC speed modes and this bit is automatically cleared when tuning procedure is completed. 0x0: Not Tuned or Tuning completed 0x1: Execute Tuning" "Not Tuned or Tuning completed,Execute Tuning" newline bitfld.word 0x0 4.--5. "DRV_STRENGTH_SEL,Driver Strength Select This bit is used to select the Host Controller output driver in 1.8V signaling UHS-I/eMMC speed modes. The bit depends on setting of Preset Value Enable. The value is reflected on the uhs1_drv_sth pin. 0x1: Driver.." "Driver TYPEB is selected,Driver TYPEA is selected,Driver TYPEC is selected,Driver TYPED is selected" newline bitfld.word 0x0 3. "SIGNALING_EN,1.8V Signaling Enable This bit controls voltage regulator for I/O cell in UHS-I/eMMC speed modes. Setting this bit from 0 to 1 starts changing the signal voltage from 3.3V to 1.8V. Host Controller clears this bit if switching to 1.8.." "0,1" newline bitfld.word 0x0 0.--2. "UHS_MODE_SEL,UHS Mode/eMMC Speed Mode Select These bits are used to select UHS mode in the SD mode of operation. In eMMC mode these bits are used to select eMMC Speed mode. UHS Mode (SD/UHS-II mode only): - 0x0: SDR12 - 0x1: SDR25 - 0x2: SDR50 - 0x3:.." "SDR12/Legacy,SDR25/High Speed SDR,SDR50,SDR104/HS200,DDR50/High Speed DDR,Reserved,Reserved,UHS-II/HS400" rgroup.long 0x40++0xF line.long 0x0 "CAPABILITIES1_R,This register provides the Host Driver with information specific to the Host Controller implementation. The host controller may implement these values as fixed or loaded from the flash memory during power on initialization. Capabilities.." bitfld.long 0x0 30.--31. "SLOT_TYPE_R,Slot Type These bits indicate usage of a slot by a specific Host System. 0x1: Embedded Slot for one Device 0x0: Removable Card Slot 0x2: Shared Bus Slot (SD mode) 0x3: UHS-II Multiple Embedded Devices" "Removable Card Slot,Embedded Slot for one Device,Shared Bus Slot,UHS-II Multiple Embedded Devices" newline bitfld.long 0x0 29. "ASYNC_INT_SUPPORT,Asynchronous Interrupt Support (SD Mode only) 0x0: Asynchronous Interrupt Not Supported 0x1: Asynchronous Interrupt Supported" "Asynchronous Interrupt Not Supported,Asynchronous Interrupt Supported" newline bitfld.long 0x0 28. "SYS_ADDR_64_V3,64-bit System Address Support for V3 This bit sets the Host controller to support 64-bit System Addressing of V3 mode. SDMA cannot be used in 64-bit Addressing in Version 3 Mode. If this bit is set to 1 64-bit ADMA2 with using 96-bit.." "0,1" newline bitfld.long 0x0 27. "SYS_ADDR_64_V4,64-bit System Address Support for V4 This bit sets the Host Controller to support 64-bit System Addressing of V4 mode. When this bit is set to 1 full or part of 64-bit address must be used to decode the Host Controller Registers so that.." "0,1" newline bitfld.long 0x0 26. "VOLT_18,Voltage Support for 1.8V 0x0: 1.8V Not Supported 0x1: 1.8V Supported" "0,1" newline bitfld.long 0x0 25. "VOLT_30,Voltage Support for SD 3.0V or Embedded 1.2V 0x0: SD 3.0V or Embedded 1.2V Not Supported 0x1: SD 3.0V or Embedded Supported" "SD 3,SD 3" newline bitfld.long 0x0 24. "VOLT_33,Voltage Support for 3.3V 0x0: 3.3V Not Supported 0x1: 3.3V Supported" "0,1" newline bitfld.long 0x0 23. "SUS_RES_SUPPORT,Suspense/Resume Support This bit indicates whether the Host Controller supports Suspend/Resume functionality. If this bit is 0 the Host Driver does not issue either Suspend or Resume commands because the Suspend and Resume mechanism is.." "Not Supported,Supported" newline bitfld.long 0x0 22. "SDMA_SUPPORT,SDMA Support This bit indicates whether the Host Controller is capable of using SDMA to transfer data between the system memory and the Host Controller directly. 0x0: SDMA not Supported 0x1: SDMA Supported" "SDMA not Supported,SDMA Supported" newline bitfld.long 0x0 21. "HIGH_SPEED_SUPPORT,High Speed Support This bit indicates whether the Host Controller and the Host System supports High Speed mode and they can supply the SD Clock frequency from 25 MHz to 50 MHz. 0x0: High Speed not Supported 0x1: High Speed Supported" "High Speed not Supported,High Speed Supported" newline bitfld.long 0x0 20. "RSVD_20,This bit of the CAPABILITIES1_R is a reserved. It always returns 0." "0,1" newline bitfld.long 0x0 19. "ADMA2_SUPPORT,ADMA2 Support This bit indicates whether the Host Controller is capable of using ADMA2. 0x0: ADMA2 not Supported 0x1: ADMA2 Supported" "ADMA2 not Supported,ADMA2 Supported" newline bitfld.long 0x0 18. "EMBEDDED_8_BIT,8-bit Support for Embedded Device This bit indicates whether the Host Controller is capable of using an 8-bit bus width mode. This bit is not effective when the Slot Type is set to 10b. 0x0: 8-bit Bus Width not Supported 0x1: 8-bit Bus.." "0,1" newline bitfld.long 0x0 16.--17. "MAX_BLK_LEN,Maximum Block Length This bit indicates the maximum block size that the Host driver can read and write to the buffer in the Host Controller. The buffer transfers this block size without wait cycles. The transfer block length is always 512.." "?,?,?,Reserved" newline hexmask.long.byte 0x0 8.--15. 1. "BASE_CLK_FREQ,Base Clock Frequency for SD clock These bits indicate the base (maximum) clock frequency for the SD Clock. The definition of these bits depend on the Host Controller Version. - 6-Bit Base Clock Frequency: This mode is supported by the Host.." newline bitfld.long 0x0 7. "TOUT_CLK_UNIT,Timeout Clock Unit This bit shows the unit of base clock frequency used to detect Data TImeout Error. 0x0: KHz 0x1: MHz" "KHz,MHz" newline bitfld.long 0x0 6. "RSVD_6,This bit of the CAPABILITIES1_R register is reserved. It always returns 0." "0,1" newline hexmask.long.byte 0x0 0.--5. 1. "TOUT_CLK_FREQ,Timeout Clock Frequency This bit shows the base clock frequency used to detect Data Timeout Error. The Timeout Clock unit defines the unit of timeout clock frequency. It can be KHz or MHz. - 0x00 - Get information through another method -.." line.long 0x4 "CAPABILITIES2_R,This register provides the Host Driver with information specific to the Host Controller implementation. The host controller may implement these values as fixed or as loaded from flash memory during power on initialization. Capabilities.." bitfld.long 0x4 30.--31. "RSVD_62_63,These bits (RSVD_62_63) of the CAPABILITIES2_R register are reserved bits. They always return 0." "0,1,2,3" newline bitfld.long 0x4 29. "RSVD_61,This bit (RSVD_61) of the CAPABILITIES2_R register is reserved. It always returns 0." "0,1" newline bitfld.long 0x4 28. "VDD2_18V_SUPPORT,1.8V VDD2 Support This bit indicates support of VDD2 for the Host System. 0x0: 1.8V VDD2 is not Supported 0x1: 1.8V VDD2 is Supported" "0,1" newline bitfld.long 0x4 27. "ADMA3_SUPPORT,ADMA3 Support This bit indicates whether the Host Controller is capable of using ADMA3. 0x0: ADMA3 not Supported 0x1: ADMA3 Supported" "ADMA3 not Supported,ADMA3 Supported" newline bitfld.long 0x4 24.--26. "RSVD_56_58,These bits (RSVD_56_58) of the CAPABILITIES2_R register are reserved. They always return 0." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x4 16.--23. 1. "CLK_MUL,Clock Multiplier These bits indicate the clock multiplier of the programmable clock generator. Setting these bits to 0 means that the Host Controller does not support a programmable clock generator. - 0x0: Clock Multiplier is not Supported - 0x1:.." newline bitfld.long 0x4 14.--15. "RE_TUNING_MODES,Re-Tuning Modes (UHS-I only) These bits select the re-tuning method and limit the maximum data length. 0x0: Timer 0x1: Timer and Re-Tuning Request (Not supported) 0x2: Auto Re-Tuning (for transfer) 0x3: Reserved" "Timer,Timer and Re-Tuning Request,Auto Re-Tuning,Reserved" newline bitfld.long 0x4 13. "USE_TUNING_SDR50,Use Tuning for SDR50 (UHS-I only) 0x1: SDR50 requires tuning 0x0: SDR50 does not require tuning" "SDR50 does not require tuning,SDR50 requires tuning" newline bitfld.long 0x4 12. "RSVD_44,This bit (RSVD_44) of the CAPABILITIES2_R register is reserved. It always returns 0." "0,1" newline hexmask.long.byte 0x4 8.--11. 1. "RETUNE_CNT,Timer Count for Re-Tuning (UHS-I only) - 0x0: Re-Tuning Timer disabled - 0x1: 1 seconds - 0x2: 2 seconds - 0x3: 4 seconds - ........ - 0xB: 1024 seconds - 0xC: Reserved - 0xD: Reserved - 0xE: Reserved - 0xF: Get information from other source" newline bitfld.long 0x4 7. "RSVD_39,This bit (RSVD_39) of the CAPABILITIES2_R register is reserved. It always returns 0." "0,1" newline bitfld.long 0x4 6. "DRV_TYPED,Driver Type D Support (UHS-I only) This bit indicates support of Driver Type D for 1.8 Signaling. 0x0: Driver Type D is not supported 0x1: Driver Type D is supported" "Driver Type D is not supported,Driver Type D is supported" newline bitfld.long 0x4 5. "DRV_TYPEC,Driver Type C Support (UHS-I only) This bit indicates support of Driver Type C for 1.8 Signaling. 0x0: Driver Type C is not supported 0x1: Driver Type C is supported" "Driver Type C is not supported,Driver Type C is supported" newline bitfld.long 0x4 4. "DRV_TYPEA,Driver Type A Support (UHS-I only) This bit indicates support of Driver Type A for 1.8 Signaling. 0x0: Driver Type A is not supported 0x1: Driver Type A is supported" "Driver Type A is not supported,Driver Type A is supported" newline bitfld.long 0x4 3. "UHS2_SUPPORT,UHS-II Support (UHS-II only) This bit indicates whether Host Controller supports UHS-II. 0x0: UHS-II is not supported 0x1: UHS-II is supported" "UHS-II is not supported,UHS-II is supported" newline bitfld.long 0x4 2. "DDR50_SUPPORT,DDR50 Support (UHS-I only) 0x0: DDR50 is not supported 0x1: DDR50 is supported" "DDR50 is not supported,DDR50 is supported" newline bitfld.long 0x4 1. "SDR104_SUPPORT,SDR104 Support (UHS-I only) This bit mentions that SDR104 requires tuning. 0x0: SDR104 is not supported 0x1: SDR104 is supported" "SDR104 is not supported,SDR104 is supported" newline bitfld.long 0x4 0. "SDR50_SUPPORT,SDR50 Support (UHS-I only) Thsi bit indicates that SDR50 is supported. The bit 13 (USE_TUNING_SDR50) indicates whether SDR50 requires tuning or not. 0x0: SDR50 is not supported 0x1: SDR50 is supported" "SDR50 is not supported,SDR50 is supported" line.long 0x8 "CURR_CAPABILITIES1_R,This register indicate the maximum current capability for each voltage. for VDD1. The value is meaningful if the Voltage Support is set in the Capabilities register. If this information is supplied by the Host System through another.." hexmask.long.byte 0x8 24.--31. 1. "RSVD_31_24,These bits of the CURR_CAPABILITIES1_R register are reserved. They always return 0." newline hexmask.long.byte 0x8 16.--23. 1. "MAX_CUR_18V,Maximum Current for 1.8V This bit specifies the Maximum Current for 1.8V VDD1 power supply for the card. - 0: Get information through another method - 1: 4mA - 2: 8mA - 3: 13mA - ....... - 255: 1020mA" newline hexmask.long.byte 0x8 8.--15. 1. "MAX_CUR_30V,Maximum Current for 3.0V This bit specifies the Maximum Current for 3.0V VDD1 power supply for the card. - 0: Get information through another method - 1: 4mA - 2: 8mA - 3: 13mA - ....... - 255: 1020mA" newline hexmask.long.byte 0x8 0.--7. 1. "MAX_CUR_33V,Maximum Current for 3.3V This bit specifies the Maximum Current for 3.3V VDD1 power supply for the card. - 0: Get information through another method - 1: 4mA - 2: 8mA - 3: 13mA - ....... - 255: 1020mA" line.long 0xC "CURR_CAPABILITIES2_R,This register indicates the maximum current capability for each voltage (for VDD2). The value is meaningful if Voltage Support is set in the Capabilities register. If this information is supplied by the Host System through another.." hexmask.long.tbyte 0xC 8.--31. 1. "RSVD_63_40,These bits of the CURR_CAPABILITIES2_R register are reserved. They always return 0." newline hexmask.long.byte 0xC 0.--7. 1. "MAX_CUR_VDD2_18V,Maximum Current for 1.8V VDD2 This bit specifies the Maximum Current for 1.8V VDD2 power supply for the UHS-II card. - 0: Get information through another method - 1: 4mA - 2: 8mA - 3: 13mA - ....... - 255: 1020mA" group.word 0x50++0x3 line.word 0x0 "FORCE_AUTO_CMD_STAT_R,The register is not a physically implemented but is an address at which the Auto CMD Error Status register can be written.This register is applicable for an SD/eMMC mode. - 1 : Sets each bit of the Auto CMD Error Status register - 0.." newline hexmask.word.byte 0x0 8.--15. 1. "RSVD_15_8,These bits of the FORCE_AUTO_CMD_STAT_R register are reserved. They always return 0." newline bitfld.word 0x0 7. "FORCE_CMD_NOT_ISSUED_AUTO_CMD12,Force Event for Command Not Issued By Auto CMD12 Error 0x0: Not Affected 0x1: Command Not Issued By Auto CMD12 Error Status is set" "Not Affected,Command Not Issued By Auto CMD12 Error Status is.." newline rbitfld.word 0x0 6. "RSVD_6,This bit of the FORCE_AUTO_CMD_STAT_R register are reserved. They always return 0." "0,1" newline bitfld.word 0x0 5. "FORCE_AUTO_CMD_RESP_ERR,Force Event for Auto CMD Response Error 0x0: Not Affected 0x1: Auto CMD Response Error Status is set" "Not Affected,Auto CMD Response Error Status is set" newline bitfld.word 0x0 4. "FORCE_AUTO_CMD_IDX_ERR,Force Event for Auto CMD Index Error 0x0: Not Affected 0x1: Auto CMD Index Error Status is set" "Not Affected,Auto CMD Index Error Status is set" newline bitfld.word 0x0 3. "FORCE_AUTO_CMD_EBIT_ERR,Force Event for Auto CMD End Bit Error 0x0: Not Affected 0x1: Auto CMD End Bit Error Status is set" "Not Affected,Auto CMD End Bit Error Status is set" newline bitfld.word 0x0 2. "FORCE_AUTO_CMD_CRC_ERR,Force Event for Auto CMD CRC Error 0x0: Not Affected 0x1: Auto CMD CRC Error Status is set" "Not Affected,Auto CMD CRC Error Status is set" newline bitfld.word 0x0 1. "FORCE_AUTO_CMD_TOUT_ERR,Force Event for Auto CMD Timeout Error 0x0: Not Affected 0x1: Auto CMD Timeout Error Status is set" "Not Affected,Auto CMD Timeout Error Status is set" newline bitfld.word 0x0 0. "FORCE_AUTO_CMD12_NOT_EXEC,Force Event for Auto CMD12 Not Executed 0x0: Not Affected 0x1: Auto CMD12 Not Executed Status is set" "Not Affected,Auto CMD12 Not Executed Status is set" line.word 0x2 "FORCE_ERROR_INT_STAT_R,This register is not physically implemented but is an address at which the Error Interrupt Status register can be written. The effect of a write to this address is reflected in the Error Interrupt Status register if the.." newline bitfld.word 0x2 15. "FORCE_VENDOR_ERR3,This bit (FORCE_VENDOR_ERR3) of the FORCE_ERROR_INT_STAT_R register is reserved. It always returns 0." "0,1" newline bitfld.word 0x2 14. "FORCE_VENDOR_ERR2,This bit (FORCE_VENDOR_ERR2) of the FORCE_ERROR_INT_STAT_R register is reserved. It always returns 0." "0,1" newline bitfld.word 0x2 13. "FORCE_VENDOR_ERR1,This bit (FORCE_VENDOR_ERR1) of the FORCE_ERROR_INT_STAT_R register is reserved. It always returns 0." "0,1" newline bitfld.word 0x2 12. "FORCE_BOOT_ACK_ERR,Force Event for Boot Ack error 0x0: Not Affected 0x1: Boot ack Error Status is set" "Not Affected,Boot ack Error Status is set" newline bitfld.word 0x2 11. "FORCE_RESP_ERR,Force Event for Response Error (SD Mode only) 0x0: Not Affected 0x1: Response Error Status is set" "Not Affected,Response Error Status is set" newline bitfld.word 0x2 10. "FORCE_TUNING_ERR,Force Event for Tuning Error (UHS-I Mode only) 0x0: Not Affected 0x1: Tuning Error Status is set" "Not Affected,Tuning Error Status is set" newline bitfld.word 0x2 9. "FORCE_ADMA_ERR,Force Event for ADMA Error 0x0: Not Affected 0x1: ADMA Error Status is set" "Not Affected,ADMA Error Status is set" newline bitfld.word 0x2 8. "FORCE_AUTO_CMD_ERR,Force Event for Auto CMD Error (SD/eMMC Mode only) 0x0: Not Affected 0x1: Auto CMD Error Status is set" "Not Affected,Auto CMD Error Status is set" newline bitfld.word 0x2 7. "FORCE_CUR_LMT_ERR,Force Event for Current Limit Error 0x0: Not Affected 0x1: Current Limit Error Status is set" "Not Affected,Current Limit Error Status is set" newline bitfld.word 0x2 6. "FORCE_DATA_END_BIT_ERR,Force Event for Data End Bit Error (SD/eMMC Mode only) 0x0: Not Affected 0x1: Data End Bit Error Status is set" "Not Affected,Data End Bit Error Status is set" newline bitfld.word 0x2 5. "FORCE_DATA_CRC_ERR,Force Event for Data CRC Error (SD/eMMC Mode only) 0x0: Not Affected 0x1: Data CRC Error Status is set" "Not Affected,Data CRC Error Status is set" newline bitfld.word 0x2 4. "FORCE_DATA_TOUT_ERR,Force Event for Data Timeout Error (SD/eMMC Mode only) 0x0: Not Affected 0x1: Data Timeout Error Status is set" "Not Affected,Data Timeout Error Status is set" newline bitfld.word 0x2 3. "FORCE_CMD_IDX_ERR,Force Event for Command Index Error (SD/eMMC Mode only) 0x0: Not Affected 0x1: Command Index Error Status is set" "Not Affected,Command Index Error Status is set" newline bitfld.word 0x2 2. "FORCE_CMD_END_BIT_ERR,Force Event for Command End Bit Error (SD/eMMC Mode only) 0x0: Not Affected 0x1: Command End Bit Error Status is set" "Not Affected,Command End Bit Error Status is set" newline bitfld.word 0x2 1. "FORCE_CMD_CRC_ERR,Force Event for Command CRC Error (SD/eMMC Mode only) 0x0: Not Affected 0x1: Command CRC Error Status is set" "Not Affected,Command CRC Error Status is set" newline bitfld.word 0x2 0. "FORCE_CMD_TOUT_ERR,Force Event for Command Timeout Error (SD/eMMC Mode only) 0x0: Not Affected 0x1: Command Timeout Error Status is set" "Not Affected,Command Timeout Error Status is set" rgroup.byte 0x54++0x0 line.byte 0x0 "ADMA_ERR_STAT_R,This register stores the ADMA state during an ADMA error. This register is applicable for an SD/eMMC/UHS-II mode." newline hexmask.byte 0x0 3.--7. 1. "RSVD_7_3,These bits of the ADMA_ERR_STAT_R register are reserved. They always return 0." newline bitfld.byte 0x0 2. "ADMA_LEN_ERR,ADMA Length Mismatch Error States This error occurs in the following instances: - While the Block Count Enable is being set the total data length specified by the Descriptor table is different from that specified by the Block Count and.." "No Error,Error" newline bitfld.byte 0x0 0.--1. "ADMA_ERR_STATES,ADMA Error States These bits indicate the state of ADMA when an error occurs during ADMA data transfer. 0x1: Fetch Descriptor - SYS_ADR register points to the error descriptor 0x0: Stop DMA - SYS_ADR register points to a location next to.." "Stop DMA,Fetch Descriptor,Never set this state,Transfer Data" group.long 0x58++0x7 line.long 0x0 "ADMA_SA_LOW_R,This register holds the lower 32-bit system address for DMA transfer. This register is applicable for an SD/eMMC/UHS-II mode." hexmask.long 0x0 0.--31. 1. "ADMA_SA_LOW,ADMA System Address These bits indicate the lower 32 bits of the ADMA system address. - SDMA: If Host Version 4 Enable is set to 1 this register stores the system address of the data location - ADMA2: This register stores the byte address of.." line.long 0x4 "ADMA_SA_HIGH_R,This register holds the upper 32-bit system address for the DMA transfer. This register is applicable for an SD/eMMC/UHS-II mode." hexmask.long 0x4 0.--31. 1. "ADMA_SA_HIGH,ADMA System Address These bits indicate the higher 32-bit of the ADMA system address." rgroup.word 0x60++0xF line.word 0x0 "PRESET_INIT_R,This register defines Preset Value for Initialization in SD/eMMC mode." newline bitfld.word 0x0 14.--15. "DRV_SEL_VAL,Driver Strength Select Value These bits indicate that the Driver strength is supported by 1.8V signaling bus speed modes. These bits are meaningless for 3.3V signaling. 0x1: Driver Type A is selected 0x0: Driver Type B is selected 0x2: Driver.." "Driver Type B is selected,Driver Type A is selected,Driver Type C is selected,Driver Type D is selected" newline bitfld.word 0x0 11.--13. "RSVD_13_11,These bits of the PRESET_INIT_R register are reserved. They always return 0." "0,1,2,3,4,5,6,7" newline bitfld.word 0x0 10. "CLK_GEN_SEL_VAL,Clock Generator Select Value This bit is effective when the Host Controller supports a programmable clock generator. 0x0: Host Controller Ver2.0 Compatible Clock Generator 0x1: Programmable Clock Generator" "Host Controller Ver2,Programmable Clock Generator" newline hexmask.word 0x0 0.--9. 1. "FREQ_SEL_VAL,SDCLK/RCLK Frequency Select Value 10-bit preset value to be set in SDCLK/RCLK Frequency Select field of the Clock Control register described by a Host System." line.word 0x2 "PRESET_DS_R,This register defines Preset Value for Default Speed mode in SD mode." newline bitfld.word 0x2 14.--15. "DRV_SEL_VAL,Driver Strength Select Value These bits indicate the Driver strength value supported by 1.8V signaling bus speed modes. This field is meaningless for the Default speed mode as it uses 3.3V signaling. 0x1: Driver Type A is selected 0x0: Driver.." "Driver Type B is selected,Driver Type A is selected,Driver Type C is selected,Driver Type D is selected" newline bitfld.word 0x2 11.--13. "RSVD_13_11,These bits of the PRESET_DS_R register are reserved. They always return 0." "0,1,2,3,4,5,6,7" newline bitfld.word 0x2 10. "CLK_GEN_SEL_VAL,Clock Generator Select Value This bit is effective when Host Controller supports programmable clock generator. 0x0: Host Controller Ver2.0 Compatible Clock Generator 0x1: Programmable Clock Generator" "Host Controller Ver2,Programmable Clock Generator" newline hexmask.word 0x2 0.--9. 1. "FREQ_SEL_VAL,SDCLK/RCLK Frequency Select Value 10-bit preset value to be set in SDCLK/RCLK Frequency Select field of the Clock Control register described by a Host System." line.word 0x4 "PRESET_HS_R,This register defines Preset Value for High Speed mode in SD mode." newline bitfld.word 0x4 14.--15. "DRV_SEL_VAL,Driver Strength Select Value These bits indicate the Driver strength value supported by 1.8V signaling bus speed modes. This field is meaningless for High speed mode as it uses 3.3V signaling. 0x1: Driver Type A is selected 0x0: Driver Type B.." "Driver Type B is selected,Driver Type A is selected,Driver Type C is selected,Driver Type D is selected" newline bitfld.word 0x4 11.--13. "RSVD_13_11,These bits of the PRESET_HS_R register are reserved. They always return 0." "0,1,2,3,4,5,6,7" newline bitfld.word 0x4 10. "CLK_GEN_SEL_VAL,Clock Generator Select Value This bit is effective when Host Controller supports programmable clock generator. 0x0: Host Controller Ver2.0 Compatible Clock Generator 0x1: Programmable Clock Generator" "Host Controller Ver2,Programmable Clock Generator" newline hexmask.word 0x4 0.--9. 1. "FREQ_SEL_VAL,SDCLK/RCLK Frequency Select Value 10-bit preset value to be set in SDCLK/RCLK Frequency Select field of the Clock Control register described by a Host System." line.word 0x6 "PRESET_SDR12_R,This register defines Preset Value for SDR12 and Legacy speed mode in SD and eMMC mode respectively." newline bitfld.word 0x6 14.--15. "DRV_SEL_VAL,Driver Strength Select Value These bits indicate the Driver strength value supported for the SDR12 bus speed mode. These bits are meaningless for 3.3V signaling. 0x1: Driver Type A is selected 0x0: Driver Type B is selected 0x2: Driver Type C.." "Driver Type B is selected,Driver Type A is selected,Driver Type C is selected,Driver Type D is selected" newline bitfld.word 0x6 11.--13. "RSVD_13_11,These bits of the PRESET_SDR12_R register are reserved. They always return 0." "0,1,2,3,4,5,6,7" newline bitfld.word 0x6 10. "CLK_GEN_SEL_VAL,Clock Generator Select Value This bit is effective when Host Controller supports programmable clock generator 0x0: Host Controller Ver2.0 Compatible Clock Generator 0x1: Programmable Clock Generator" "Host Controller Ver2,Programmable Clock Generator" newline hexmask.word 0x6 0.--9. 1. "FREQ_SEL_VAL,SDCLK/RCLK Frequency Select Value 10-bit preset value to be set in SDCLK/RCLK Frequency Select field of the Clock Control register described by a Host System." line.word 0x8 "PRESET_SDR25_R,This register defines Preset Value for SDR25 and High Speed SDR speed mode in SD and eMMC mode respectively." newline bitfld.word 0x8 14.--15. "DRV_SEL_VAL,Driver Strength Select Value These bits indicate the Driver strength value supported for the SDR25 bus speed mode. These bits are meaningless for 3.3V signaling. 0x1: Driver Type A is selected 0x0: Driver Type B is selected 0x2: Driver Type C.." "Driver Type B is selected,Driver Type A is selected,Driver Type C is selected,Driver Type D is selected" newline bitfld.word 0x8 11.--13. "RSVD_13_11,These bits of the PRESET_SDR25_R register are reserved. They always return 0." "0,1,2,3,4,5,6,7" newline bitfld.word 0x8 10. "CLK_GEN_SEL_VAL,Clock Generator Select Value This bit is effective when Host Controller supports programmable clock generator. 0x0: Host Controller Ver2.0 Compatible Clock Generator 0x1: Programmable Clock Generator" "Host Controller Ver2,Programmable Clock Generator" newline hexmask.word 0x8 0.--9. 1. "FREQ_SEL_VAL,SDCLK/RCLK Frequency Select Value 10-bit preset value to be set in SDCLK/RCLK Frequency Select field of the Clock Control register described by a Host System." line.word 0xA "PRESET_SDR50_R,This register defines Preset Value for SDR50 speed mode in SD mode." newline bitfld.word 0xA 14.--15. "DRV_SEL_VAL,Driver Strength Select Value These bits indicate Driver strength value supported for SDR50 bus speed mode. These bits are meaningless for 3.3V signaling. 0x1: Driver Type A is selected 0x0: Driver Type B is selected 0x2: Driver Type C is.." "Driver Type B is selected,Driver Type A is selected,Driver Type C is selected,Driver Type D is selected" newline bitfld.word 0xA 11.--13. "RSVD_13_11,These bits of the PRESET_SDR50_R register are reserved. They always return 0." "0,1,2,3,4,5,6,7" newline bitfld.word 0xA 10. "CLK_GEN_SEL_VAL,Clock Generator Select Value This bit is effective when Host Controller supports programmable clock generator. 0x0: Host Controller Ver2.0 Compatible Clock Generator 0x1: Programmable Clock Generator" "Host Controller Ver2,Programmable Clock Generator" newline hexmask.word 0xA 0.--9. 1. "FREQ_SEL_VAL,SDCLK/RCLK Frequency Select Value 10-bit preset value to be set in SDCLK/RCLK Frequency Select field of the Clock Control register described by a Host System." line.word 0xC "PRESET_SDR104_R,This register defines Preset Value for SDR104 and HS200 speed modes in the SD and eMMC modes. respectively." newline bitfld.word 0xC 14.--15. "DRV_SEL_VAL,Driver Strength Select Value These bits indicate Driver strength value supported for SDR104 bus speed mode. These bits are meaningless for 3.3V signaling. 0x1: Driver Type A is selected 0x0: Driver Type B is selected 0x2: Driver Type C is.." "Driver Type B is selected,Driver Type A is selected,Driver Type C is selected,Driver Type D is selected" newline bitfld.word 0xC 11.--13. "RSVD_13_11,These bits of the PRESET_SDR104_R register are reserved. They always return 0." "0,1,2,3,4,5,6,7" newline bitfld.word 0xC 10. "CLK_GEN_SEL_VAL,Clock Generator Select Value This bit is effective when Host Controller supports programmable clock generator. 0x0: Host Controller Ver2.0 Compatible Clock Generator 0x1: Programmable Clock Generator" "Host Controller Ver2,Programmable Clock Generator" newline hexmask.word 0xC 0.--9. 1. "FREQ_SEL_VAL,SDCLK/RCLK Frequency Select Value These bits specify a 10-bit preset value that must be set in the SDCLK/RCLK Frequency Select field of the Clock Control register described by a Host System." line.word 0xE "PRESET_DDR50_R,This register defines the Preset Value for DDR50 and High Speed DDR speed modes in the SD and eMMC modes. respectively." newline bitfld.word 0xE 14.--15. "DRV_SEL_VAL,Driver Strength Select Value These bits indicate Driver strength value supported for DDR50 bus speed mode. These bits are meaningless for 3.3V signaling. 0x1: Driver Type A is selected 0x0: Driver Type B is selected 0x2: Driver Type C is.." "Driver Type B is selected,Driver Type A is selected,Driver Type C is selected,Driver Type D is selected" newline bitfld.word 0xE 11.--13. "RSVD_13_11,These bits of the PRESET_DDR50_R register are reserved. They always return 0." "0,1,2,3,4,5,6,7" newline bitfld.word 0xE 10. "CLK_GEN_SEL_VAL,Clock Generator Select Value This bit is effective when Host Controller supports programmable clock generator. 0x0: Host Controller Ver2.0 Compatible Clock Generator 0x1: Programmable Clock Generator" "Host Controller Ver2,Programmable Clock Generator" newline hexmask.word 0xE 0.--9. 1. "FREQ_SEL_VAL,SDCLK/RCLK Frequency Select Value These bits specify a 10-bit preset value that must be set in the SDCLK/RCLK Frequency Select field of the Clock Control register as described by a Host System." rgroup.word 0x74++0x1 line.word 0x0 "PRESET_UHS2_R,This register is used to hold the preset value for UHS-II and HS400 speed modes in the SD and eMMC modes. respectively." newline bitfld.word 0x0 14.--15. "DRV_SEL_VAL,Driver Strength Select Value These bits indicate the Driver strength value supported by 1.8V signaling bus speed modes in the SD mode. This field is meaningless for UHS-II mode. In eMMC mode these bits can be used for selecting the Drive.." "Driver Type B is selected,Driver Type A is selected,Driver Type C is selected,Driver Type D is selected" newline bitfld.word 0x0 11.--13. "RSVD_13_11,These bits of UHS-II Preset register are reserved. They always return 0." "0,1,2,3,4,5,6,7" newline bitfld.word 0x0 10. "CLK_GEN_SEL_VAL,Clock Generator Select Value This bit is effective when the Host Controller supports a programmable clock generator. 0x0: Host Controller Ver2.0 Compatible Clock Generator 0x1: Programmable Clock Generator" "Host Controller Ver2,Programmable Clock Generator" newline hexmask.word 0x0 0.--9. 1. "FREQ_SEL_VAL,SDCLK/RCLK Frequency Select Value These bits specify the 10-bit preset value that must be set in the SDCLK/RCLK Frequency Select field of the Clock Control register as described by a Host System." group.long 0x78++0x7 line.long 0x0 "ADMA_ID_LOW_R,This register holds the lower 32-bit Integrated Descriptor address.This register is applicable for an SD/eMMC/UHS-II mode." hexmask.long 0x0 0.--31. 1. "ADMA_ID_LOW,ADMA Integrated Descriptor Address These bits indicate the lower 32-bit of the ADMA Integrated Descriptor address. The start address of Integrated Descriptor is set to these register bits. The ADMA3 fetches one Descriptor Address and.." line.long 0x4 "ADMA_ID_HIGH_R,This register holds the upper 32-bit Integrated Descriptor address.This register is applicable for an SD/eMMC/UHS-II mode." hexmask.long 0x4 0.--31. 1. "ADMA_ID_HIGH,ADMA Integrated Descriptor Address These bits indicate the higher 32 bit of the ADMA Integrated Descriptor address." rgroup.word 0xE6++0x5 line.word 0x0 "P_EMBEDDED_CNTRL,This register points to the location of UHS-II embedded control registers." newline hexmask.word.byte 0x0 12.--15. 1. "RESERVED_15_12,These bits of the P_EMBEDDED_CNTRL register are reserved. They always return 0." newline hexmask.word 0x0 0.--11. 1. "REG_OFFSET_ADDR,Offset Address of Embedded Control register." line.word 0x2 "P_VENDOR_SPECIFIC_AREA,This register used as a pointer for the Vendor Specific Area 1." newline hexmask.word.byte 0x2 12.--15. 1. "RESERVED_15_12,These bits of the P_VENDOR_SPECIFIC_AREA register are reserved. They always return 0." newline hexmask.word 0x2 0.--11. 1. "REG_OFFSET_ADDR,Base offset Address for Vendor-Specific registers." line.word 0x4 "P_VENDOR2_SPECIFIC_AREA,This register is used as a pointer for the Vendor Specific Area 2." newline hexmask.word 0x4 0.--15. 1. "REG_OFFSET_ADDR,Base offset Address for Command Queuing registers." rgroup.word 0xFC++0x3 line.word 0x0 "SLOT_INTR_STATUS_R,This register indicates the Interrupt status of each slot." newline hexmask.word.byte 0x0 8.--15. 1. "RESERVED_15_8,These bits of the SLOT_INTR_STATUS_R register are reserved. They always return 0." newline hexmask.word.byte 0x0 0.--7. 1. "INTR_SLOT,Interrupt signal for each Slot These status bits indicate the logical OR of Interrupt signal and Wakeup signal for each slot. A maximum of 8 slots can be defined. If one interrupt signal is associated with multiple slots the Host Driver can.." line.word 0x2 "HOST_CNTRL_VERS_R,This register is used to indicate the Host Controller Version number." newline hexmask.word.byte 0x2 8.--15. 1. "VENDOR_VERSION_NUM,Vendor Version Number This field is reserved for the vendor version number. Host Driver must not use this status." newline hexmask.word.byte 0x2 0.--7. 1. "SPEC_VERSION_NUM,Specification Version Number These bits indicate the Host controller specification version. The upper and lower 4-bits indicate the version. Values 0x06-0xFF are reserved. 0x0: SD Host Controller Specification Version 1.00 0x1: SD Host.." tree.end tree "DWC_mshc_embedded_control_block (This register block defines embedded control registers)" base ad:0x3948 group.long 0x0++0x3 line.long 0x0 "EMBEDDED_CTRL_R,This register controls the embedded device. When the Host Controller is connected to a removable device. this register is not used." rbitfld.long 0x0 31. "RSVD_31,This bit (RSVD_31) of the EMBEDDED_CTRL_R register is reserved. It always returns 0." "0,1" hexmask.long.byte 0x0 24.--30. 1. "BACK_END_PWR_CTRL,Back-End Power Control (SD Mode) Each bit of this field controls back-end power supply for an embedded device. - 0 - Back-End Power is off - 1 - Back-End Power is supplied D24 - Back-End Power for Device 1 D25 - Back-End Power for.." rbitfld.long 0x0 23. "RSVD_23,This bit (RSVD_23) of the EMBEDDED_CTRL_R register is reserved. It always returns 0." "0,1" newline bitfld.long 0x0 20.--22. "INT_PIN_SEL,Interrupt Pin Select These bits enable the interrupt pin inputs. - 000 - Interrupts (INT_A INT_B INT_C) are disabled - xx1 - INT_A is enabled - x1x - INT_B is enabled - 1xx - INT_C is enabled" "Interrupts,INT_A is enabled,?,?,?,?,?,?" rbitfld.long 0x0 19. "RSVD_19,This bit (RSVD_19) of the EMBEDDED_CTRL_R register is reserved. It always returns 0." "0,1" bitfld.long 0x0 16.--18. "CLK_PIN_SEL,Clock Pin Select (SD Mode) This bit is selected by one of clock pin outputs. - 0x0 - Clock pins are disabled - 0x1 - CLK[1] is selected - 0x2 - CLK[2] is selected - . . - . . - . . - 0x7 - CLK[7] is selected" "Clock pins are disabled,CLK[1] is selected,CLK[2] is selected,?,?,?,?,CLK[7] is selected" newline rbitfld.long 0x0 15. "RSVD_15,This bit (RSVD_15) of the EMBEDDED_CTRL_R register is reserved. It always returns 0." "0,1" hexmask.long.byte 0x0 8.--14. 1. "BUS_WIDTH_PRESET,Bus Width Preset (SD Mode) Each bit of this field specifies the bus width for each embedded device. The shared bus supports mixing of 4-bit and 8-bit bus width devices. - D08 - Bus Width Preset for Device 1 - D09 - Bus Width Preset for.." rbitfld.long 0x0 6.--7. "RSVD_7_6,These bits (RSVD_7_6) of the EMBEDDED_CTRL_R register are reserved. They always return 0." "0,1,2,3" newline rbitfld.long 0x0 4.--5. "NUM_INT_PIN,Number of Interrupt Input Pins This field indicates support of interrupt input pins for an embedded system." "0,1,2,3" rbitfld.long 0x0 3. "RSVD_3,This bit (RSVD_3) of the EMBEDDED_CTRL_R register is reserved. It always returns 0." "0,1" rbitfld.long 0x0 0.--2. "NUM_CLK_PIN,Number of Clock Pins (SD Mode) This field indicates support of clock pins to select one of devices for shared bus system. Up to 7 clock pins can be supported. - 0x0 - Shared bus is not supported - 0x1 - 1 SDCLK is supported - 0x2 - 2 SDCLK is.." "Shared bus is not supported,?,?,?,?,?,?,?" tree.end tree "DWC_mshc_vendor1_block (This register block defines Vendor-1 related registers)" base ad:0x1280 rgroup.long 0x0++0x7 line.long 0x0 "MSHC_VER_ID_R,This register reflects the current release number of DWC_mshc/DWC_mshc_lite." hexmask.long 0x0 0.--31. 1. "MSHC_VER_ID,Current release number This field indicates the Synopsys DesignWare Cores DWC_mshc/DWC_mshc_lite current release number that is read by an application. For example release number '1.70a' is represented in ASCII as 0x313730. Lower 8 bits read.." line.long 0x4 "MSHC_VER_TYPE_R,This register reflects the current release type of DWC_mshc/DWC_mshc_lite." hexmask.long 0x4 0.--31. 1. "MSHC_VER_TYPE,Current release type This field indicates the Synopsys DesignWare Cores DWC_mshc/DWC_mshc_lite current release type that is read by an application. For example release type is 'ga' is represented in ASCII as 0x6761. Lower 16 bits read from.." group.byte 0x8++0x0 line.byte 0x0 "MSHC_CTRL_R,This register is used to control the operation of MSHC Host Controller." bitfld.byte 0x0 4. "SW_CG_DIS,Internal clock gating disable control This bit must be used to disable IP's internal clock gating when required. when disabled clocks are not gated. Clocks to the core (except hclk) must be stopped when programming this bit. 0x1: Internal clock.." "Internal clock gates are active and clock gating..,Internal clock gating is disabled" newline rbitfld.byte 0x0 1.--3. "RSVD1,These bits (RSVD1) of the MSHC_CTRL_R register are reserved. They always return 0." "0,1,2,3,4,5,6,7" newline bitfld.byte 0x0 0. "CMD_CONFLICT_CHECK,Command conflict check This bit enables command conflict check. Note: DWC_mshc controller monitors the CMD line whenever a command is issued and checks whether the value driven on sd_cmd_out matches the value on sd_cmd_in at next.." "Disable command conflict check,Check for command conflict after 1 card clock.." group.byte 0x10++0x0 line.byte 0x0 "MBIU_CTRL_R,This register is used to select the valid burst types that the AHB Master bus interface can generate. When more than one bit is set the master selects the burst it prefers among those that are enabled in this register." hexmask.byte 0x0 4.--7. 1. "RSVD,Reserved field" newline bitfld.byte 0x0 3. "BURST_INCR16_EN,INCR16 Burst Controls generation of INCR16 transfers on Master interface. 0x0: AHB INCR16 burst type is not generated on Master I/F 0x1: AHB INCR16 burst type can be generated on Master I/F" "AHB INCR16 burst type is not generated on Master..,AHB INCR16 burst type can be generated on Master.." newline bitfld.byte 0x0 2. "BURST_INCR8_EN,INCR8 Burst Controls generation of INCR8 transfers on Master interface. 0x0: AHB INCR8 burst type is not generated on Master I/F 0x1: AHB INCR8 burst type can be generated on Master I/F" "AHB INCR8 burst type is not generated on Master..,AHB INCR8 burst type can be generated on Master.." newline bitfld.byte 0x0 1. "BURST_INCR4_EN,INCR4 Burst Controls generation of INCR4 transfers on Master interface. 0x0: AHB INCR4 burst type is not generated on Master I/F 0x1: AHB INCR4 burst type can be generated on Master I/F" "AHB INCR4 burst type is not generated on Master..,AHB INCR4 burst type can be generated on Master.." newline bitfld.byte 0x0 0. "UNDEFL_INCR_EN,Undefined INCR Burst Controls generation of undefined length INCR transfer on Master interface. 0x0: Undefined INCR type burst is the least preferred burst on AHB Master I/F 0x1: Undefined INCR type burst is the most preferred burst on AHB.." "Undefined INCR type burst is the least preferred..,Undefined INCR type burst is the most preferred.." group.word 0x2C++0x3 line.word 0x0 "EMMC_CTRL_R,This register is used to control the eMMC operation." hexmask.word.byte 0x0 11.--15. 1. "RSVD,These bits (RSVD) of the EMMC_CTRL_R register are reserved. They always return 0." newline bitfld.word 0x0 10. "CQE_PREFETCH_DISABLE,Enable or Disable CQE's PREFETCH feature This field allows Software to disable CQE's data prefetch feature when set to 1. 0x1: Prefetch for WRITE and Pipeline for READ are disabled 0x0: CQE can Prefetch data for sucessive WRITE.." "CQE can Prefetch data for sucessive WRITE..,Prefetch for WRITE and Pipeline for READ are.." newline bitfld.word 0x0 9. "CQE_ALGO_SEL,Scheduler algorithm selected for execution This bit selects the Algorithm used for selecting one of the many ready tasks for execution. 0x1: First come First serve in the order of DBR rings 0x0: Priority based reordering with FCFS to.." "Priority based reordering with FCFS to resolve..,First come First serve" newline bitfld.word 0x0 8. "ENH_STROBE_ENABLE,Enhanced Strobe Enable This bit instructs DWC_mshc to sample the CMD line using data strobe for HS400 mode. 0x1: CMD line is sampled using data strobe for HS400 mode 0x0: CMD line is sampled using cclk_rx for HS400 mode" "CMD line is sampled using cclk_rx for HS400 mode,CMD line is sampled using data strobe for HS400.." newline bitfld.word 0x0 3. "EMMC_RST_N_OE,Output Enable control for EMMC Device Reset signal PAD control. This field drived sd_rst_n_oe output of DWC_mshc 0x0: sd_rst_n_oe is 0 0x1: sd_rst_n_oe is 1" "sd_rst_n_oe is 0,sd_rst_n_oe is 1" newline bitfld.word 0x0 2. "EMMC_RST_N,EMMC Device Reset signal control. This register field controls the sd_rst_n output of DWC_mshc 0x0: Reset to eMMC device asserted (active low) 0x1: Reset to eMMC device is deasserted" "Reset to eMMC device asserted,Reset to eMMC device is deasserted" newline bitfld.word 0x0 1. "DISABLE_DATA_CRC_CHK,Disable Data CRC Check This bit controls masking of CRC16 error for Card Write in eMMC mode. This is useful in bus testing (CMD19) for an eMMC device. In bus testing an eMMC card does not send CRC status for a block which may.." "DATA CRC check is enabled,DATA CRC check is disabled" newline bitfld.word 0x0 0. "CARD_IS_EMMC,eMMC Card present This bit indicates the type of card connected. An application program this bit based on the card connected to MSHC. 0x1: Card connected to MSHC is an eMMC card 0x0: Card connected to MSHC is a non-eMMC card" "Card connected to MSHC is a non-eMMC card,Card connected to MSHC is an eMMC card" line.word 0x2 "BOOT_CTRL_R,This register is used to control the eMMC Boot operation." hexmask.word.byte 0x2 12.--15. 1. "BOOT_TOUT_CNT,Boot Ack Timeout Counter Value. This value determines the interval by which boot ack timeout (50 ms) is detected when boot ack is expected during boot operation. - 0xF - Reserved - 0xE - TMCLK x 2^27 - .. - ............ - 0x1 - TMCLK x 2^14.." newline rbitfld.word 0x2 9.--11. "RSVD_11_9,These bits (RSVD_11_9) of the BOOT_CTRL_R register are reserved. They always return 0." "0,1,2,3,4,5,6,7" newline bitfld.word 0x2 8. "BOOT_ACK_ENABLE,Boot Acknowledge Enable When this bit set DWC_mshc checks for boot acknowledge start pattern of 0-1-0 during boot operation. This bit is applicable for both mandatory and alternate boot mode. 0x0: Boot Ack disable 0x1: Boot Ack enable" "Boot Ack disable,Boot Ack enable" newline bitfld.word 0x2 7. "VALIDATE_BOOT,Validate Mandatory Boot Enable bit This bit is used to validate the MAN_BOOT_EN bit. 0x0: Ignore Mandatory boot Enable bit 0x1: Validate Mandatory boot enable bit" "Ignore Mandatory boot Enable bit,Validate Mandatory boot enable bit" newline hexmask.word.byte 0x2 1.--6. 1. "RSVD_6_1,These bits (RSVD _6_1) of the BOOT_CTRL_R register are reserved. They always return 0." newline bitfld.word 0x2 0. "MAN_BOOT_EN,Mandatory Boot Enable This bit is used to initiate the mandatory boot operation. The application sets this bit along with VALIDATE_BOOT bit. Writing 0 is ignored. The DWC_mshc clears this bit after the boot transfer is completed or.." "Mandatory boot disable,Mandatory boot enable" group.long 0x40++0x7 line.long 0x0 "AT_CTRL_R,This register controls some aspects of tuning and auto-tuning features. Do not program this register when HOST_CTRL2_R.SAMPLE_CLK_SEL is '1'" hexmask.long.byte 0x0 24.--30. 1. "SWIN_TH_VAL,Sampling window threshold value setting The maximum value that can be set here depends on the length of delayline used for tuning. A delayLine with 128 taps can use values from 0x0 to 0x7F. This field is valid only when SWIN_TH_EN is '1'." newline bitfld.long 0x0 19.--20. "POST_CHANGE_DLY,Time taken for phase switching and stable clock output. Specifies the maximum time (in terms of cclk cycles) that the delay line can take to switch its output phase after a change in tuning_cclk_sel or autotuning_cclk_sel. 0x0: Less than.." "Less than 1-cycle latency,Less than 2-cycle latency,Less than 3-cycle latency,Less than 4-cycle latency" newline bitfld.long 0x0 17.--18. "PRE_CHANGE_DLY,Maximum Latency specification between cclk_tx and cclk_rx. 0x0: Less than 1-cycle latency 0x1: Less than 2-cycle latency 0x2: Less than 3-cycle latency 0x3: Less than 4-cycle latency" "Less than 1-cycle latency,Less than 2-cycle latency,Less than 3-cycle latency,Less than 4-cycle latency" newline bitfld.long 0x0 16. "TUNE_CLK_STOP_EN,Clock stopping control for Tuning and auto-tuning circuit. When enabled clock gate control output of DWC_mshc (clk2card_on) is pulled low before changing phase select codes on tuning_cclk_sel and autotuning_cclk_sel. This effectively.." "Clocks not stopped,Clocks stopped during phase code change" newline hexmask.long.byte 0x0 12.--15. 1. "RSDV3,These bits (RSVD3) of the AT_CTRL_R register are reserved. They always return 0." newline hexmask.long.byte 0x0 8.--11. 1. "WIN_EDGE_SEL,This field sets the phase for Left and Right edges for drift monitoring. [Left edge offset + Right edge offset] must not be less than total taps of delayLine. - 0x0: User selection disabled. Tuning calculated edges are used. - 0x1: Right.." newline rbitfld.long 0x0 5.--7. "RSDV2,These bits (RSVD2) of the AT_CTRL_R register are reserved. They always return 0." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 4. "SW_TUNE_EN,This fields enables software-managed tuning flow. 0x0: Software-managed tuning disabled. 0x1: Software-managed tuning enabled. AT_STAT_R.CENTER_PH_CODE Field is now writable." "Software-managed tuning disabled,Software-managed tuning enabled" newline bitfld.long 0x0 3. "RPT_TUNE_ERR,Framing errors are not generated when executing tuning. This debug bit allows users to report these errors. 0x1: Debug mode for reporting framing errors 0x0: Default mode where as per SD-HCI no errors are reported." "Default mode where as per SD-HCI no errors are..,Debug mode for reporting framing errors" newline bitfld.long 0x0 2. "SWIN_TH_EN,Sampling window Threshold enable Selects the tuning mode Field should be programmed only when SAMPLE_CLK_SEL is '0' 0x0: Tuning engine sweeps all taps and settles at the largest window 0x1: Tuning engine selects the first complete sampling.." "Tuning engine sweeps all taps and settles at the..,Tuning engine selects the first complete.." newline bitfld.long 0x0 1. "CI_SEL,Selects the interval when the corrected center phase select code can be driven on tuning_cclk_sel output. 0x0: Driven in block gap interval 0x1: Driven at the end of the transfer" "Driven in block gap interval,Driven at the end of the transfer" newline bitfld.long 0x0 0. "AT_EN,Setting this bit enables Auto tuning engine. This bit is enabled by default when core is configured with mode3 retuning support. Clear this bit to 0 when core is configured to have Mode3 re-tuning but SW wishes to disable mode3 re-tuning. This.." "AutoTuning is disabled,AutoTuning is enabled" line.long 0x4 "AT_STAT_R,Register to read the Center. Left and Right codes used by tuning and auto-tuning engines. Center code field is also used for software managed tuning." hexmask.long.byte 0x4 24.--31. 1. "RSDV1,These bits of the AT_STAT_R register are reserved. They always return 0." newline hexmask.long.byte 0x4 16.--23. 1. "L_EDGE_PH_CODE,Left Edge Phase code. Reading this field returns the phase code value used by Auto-tuning engine to sample data on Left edge of sampling window." newline hexmask.long.byte 0x4 8.--15. 1. "R_EDGE_PH_CODE,Right Edge Phase code. Reading this field returns the phase code value used by Auto-tuning engine to sample data on Right edge of sampling window." newline hexmask.long.byte 0x4 0.--7. 1. "CENTER_PH_CODE,Centered Phase code. Reading this field returns the current value on tuning_cclk_sel output. Setting AT_CTRL_R.SW_TUNE_EN enables software to write to this field and its contents are reflected on tuning_cclk_sel." tree.end tree "DWC_mshc_vendor2_block (This register block defines Vendor-2 related registers)" base ad:0x384 rgroup.long 0x0++0x7 line.long 0x0 "CQVER,This register provides information about the version of the eMMC Command Queueing standard. which is implemented by the CQE in BCD format." hexmask.long.tbyte 0x0 12.--31. 1. "EMMMC_VER_RSVD,These bits of the CQVER register are reserved. They always return 0." hexmask.long.byte 0x0 8.--11. 1. "EMMC_VER_MAJOR,This bit indicates the eMMC major version (1st digit left of decimal point) in BCD format." newline hexmask.long.byte 0x0 4.--7. 1. "EMMC_VER_MINOR,This bit indicates the eMMC minor version (1st digit right of decimal point) in BCD format." hexmask.long.byte 0x0 0.--3. 1. "EMMC_VER_SUFFIX,This bit indicates the eMMC version suffix (2nd digit right of decimal point) in BCD format." line.long 0x4 "CQCAP,This register indicates the capabilities of the command queuing engine." bitfld.long 0x4 29.--31. "CQCCAP_RSVD3,These bits [31:29] of the CQCAP register are reserved. They always return 0." "0,1,2,3,4,5,6,7" bitfld.long 0x4 28. "CRYPTO_SUPPORT,Crypto Support This bit indicates whether the Host Controller supports cryptographic operations. 0x0: Crypto not Supported 0x1: Crypto Supported" "Crypto not Supported,Crypto Supported" newline hexmask.long.word 0x4 16.--27. 1. "CQCCAP_RSVD2,These bits [27:16] of the CQCAP register are reserved. They always return 0." hexmask.long.byte 0x4 12.--15. 1. "ITCFMUL,Internal Timer Clock Frequency Multiplier (ITCFMUL) This field indicates the frequency of the clock used for interrupt coalescing timer and for determining the SQS polling period. See ITCFVAL definition for details. Values 0x5 to 0xF are.." newline bitfld.long 0x4 10.--11. "CQCCAP_RSVD1,These bits of the CQCAP register are reserved. They always return 0." "0,1,2,3" hexmask.long.word 0x4 0.--9. 1. "ITCFVAL,Internal Timer Clock Frequency Value (ITCFVAL) This field scales the frequency of the timer clock provided by ITCFMUL. The Final clock frequency of actual timer clock is calculated as ITCFVAL* ITCFMUL." group.long 0x8++0x27 line.long 0x0 "CQCFG,This register controls CQE behavior affecting the general operation of command queuing engine." hexmask.long.tbyte 0x0 13.--31. 1. "CQCCFG_RSVD3,These bits (CQCCFG_RSVD3) of the CQCFG register are reserved. They always return 0." bitfld.long 0x0 12. "DCMD_EN,This bit indicates to the hardware whether the Task Descriptor in slot #31 of the TDL is a data transfer descriptor or a direct-command descriptor. CQE uses this bit when a task is issued in slot #31 to determine how to decode the Task.." "Task descriptor in slot #31 is a data Transfer..,Task descriptor in slot #31 is a DCMD Task.." newline rbitfld.long 0x0 9.--11. "CQCCFG_RSVD2,These bits (CQCCFG_RSVD2) of the CQCFG register are reserved. They always return 0." "0,1,2,3,4,5,6,7" bitfld.long 0x0 8. "TASK_DESC_SIZE,Bit Value Description This bit indicates the size of task descriptor used in host memory. This bit can only be configured when Command Queuing Enable bit is 0 (command queuing is disabled). 0x1: Task descriptor size is 128 bits 0x0: Task.." "Task descriptor size is 64 bits,Task descriptor size is 128 bits" newline hexmask.long.byte 0x0 2.--7. 1. "CQCCFG_RSVD1,These bits (CQCCFG_RSVD1) of the CQCFG register are reserved. They always return 0." bitfld.long 0x0 0. "CQ_EN,Enable command queuing engine (CQE). When CQE is disable the software controls the eMMC bus using the registers between the addresses 0x000 to 0x1FF. Before the software writes to this bit the software verifies that the eMMC host controller is in.." "Disable command queuing,Enable command queuing" line.long 0x4 "CQCTL,This register controls CQE behavior affecting the general operation of command queuing module or simultaneous operation of multiple tasks." hexmask.long.tbyte 0x4 9.--31. 1. "CQCTL_RSVD2,These bits (CQCTL_RSVD2) of the CQCTL register are reserved. They always return 0." bitfld.long 0x4 8. "CLR_ALL_TASKS,Clear all tasks This bit can only be written when the controller is halted. This bit does not clear tasks in the device. The software has to use the CMDQ_TASK_MGMT command to clear device's queue. 0x1: Clears all the tasks in the controller.." "Programming 0 has no effect,Clears all the tasks in the controller" newline hexmask.long.byte 0x4 1.--7. 1. "CQCTL_RSVD1,These bits (CQCTL_RSVD1) of the CQCTL register are reserved. They always return 0." bitfld.long 0x4 0. "HALT,Halt request and resume 0x1: Software writes 1 to this bit when it wants to acquire software control over the eMMC bus and to disable CQE from issuing command on the bus. For example issuing a Discard Task command (CMDQ_TASK_MGMT). When the.." "Software writes 0 to this bit to exit from the..,Software writes 1 to this bit when it wants to.." line.long 0x8 "CQIS,This register indicates pending interrupts that require service. Each bit in this register is asserted in response to a specific event. only if the respective bit is set in the CQISE register." hexmask.long 0x8 6.--31. 1. "CQIS_RSVD1,These bits of the CQIS register are reserved. They always return 0." bitfld.long 0x8 3. "TCL,Task cleared interrupt This status bit is asserted (if CQISE.TCL_STE=1) when a task clear operation is completed by CQE. The completed task clear operation is either an individual task clear (by writing CQTCLR) or clearing of all tasks (by writing.." "TCL Interrupt is not set,TCL Interrupt is set" newline bitfld.long 0x8 2. "RED,Response error detected interrupt This status bit is asserted (if CQISE.RED_STE=1) when a response is received with an error bit set in the device status field. Configure the CQRMEM register to identify device status bit fields that may trigger an.." "RED Interrupt is not set,RED Interrupt is set" bitfld.long 0x8 1. "TCC,Task complete interrupt This status bit is asserted (if CQISE.TCC_STE=1) when at least one of the following conditions are met: - A task is completed and the INT bit is set in its Task Descriptor - Interrupt caused by Interrupt Coalescing logic due.." "TCC Interrupt is not set,TCC Interrupt is set" newline bitfld.long 0x8 0. "HAC,Halt complete interrupt This status bit is asserted (only if CQISE.HAC_STE=1) when halt bit in the CQCTL register transitions from 0 to 1 indicating that the host controller has completed its current ongoing task and has entered halt state. A value.." "HAC Interrupt is not set,HAC Interrupt is set" line.long 0xC "CQISE,This register enables and disables the reporting of the corresponding interrupt to host software in the CQIS register. When a bit is set (1) and the corresponding interrupt condition is active. then the bit in CQIS is asserted. Interrupt sources.." hexmask.long 0xC 6.--31. 1. "CQISTE_RSVD1,These bits of the CQISE register are reserved. They always return 0." bitfld.long 0xC 3. "TCL_STE,Task cleared interrupt status enable 0x0: CQIS.TCL is disabled 0x1: CQIS.TCL is set when its interrupt condition is active" "CQIS,CQIS" newline bitfld.long 0xC 2. "RED_STE,Response error detected interrupt status enable 0x0: CQIS.RED is disabled 0x1: CQIS.RED is set when its interrupt condition is active" "CQIS,CQIS" bitfld.long 0xC 1. "TCC_STE,Task complete interrupt status enable 0x0: CQIS.TCC is disabled 0x1: CQIS.TCC is set when its interrupt condition is active" "CQIS,CQIS" newline bitfld.long 0xC 0. "HAC_STE,Halt complete interrupt status enable 0x0: CQIS.HAC is disabled 0x1: CQIS.HAC is set when its interrupt condition is active" "CQIS,CQIS" line.long 0x10 "CQISGE,This register enables and disables the generation of interrupts to host software. When a bit is set and the corresponding bit in CQIS is set. then an interrupt is generated. Interrupt sources that are disabled are still indicated in the CQIS.." hexmask.long 0x10 6.--31. 1. "CQISGE_RSVD1,These bits of the CQISGE register are reserved. They always return 0." bitfld.long 0x10 3. "TCL_SGE,Task cleared interrupt signal enable 0x0: CQIS.TCL interrupt signal generation is disabled 0x1: CQIS.TCL interrupt signal generation is active" "CQIS,CQIS" newline bitfld.long 0x10 2. "RED_SGE,Response error detected interrupt signal enable 0x0: CQIS.RED interrupt signal generation is disabled 0x1: CQIS.RED interrupt signal generation is active" "CQIS,CQIS" bitfld.long 0x10 1. "TCC_SGE,Task complete interrupt signal enable 0x0: CQIS.TCC interrupt signal generation is disabled 0x1: CQIS.TCC interrupt signal generation is active" "CQIS,CQIS" newline bitfld.long 0x10 0. "HAC_SGE,Halt complete interrupt signal enable 0x0: CQIS.HAC interrupt signal generation is disabled 0x1: CQIS.HAC interrupt signal generation is active" "CQIS,CQIS" line.long 0x14 "CQIC,This register controls and configures interrupt coalescing feature." bitfld.long 0x14 31. "INTC_EN,Interrupt Coalescing Enable Bit 0x0: Interrupt coalescing mechanism is disabled (Default). 0x1: Interrupt coalescing mechanism is active. Interrupts are counted and timed and coalesced interrupts are generated" "Interrupt coalescing mechanism is disabled,Interrupt coalescing mechanism is active" hexmask.long.word 0x14 21.--30. 1. "CQIC_RSVD3,These bits (CQIC_RSVD3) of the CQIC register are reserved. They always return 0." newline rbitfld.long 0x14 20. "INTC_STAT,Interrupt Coalescing Status Bit This bit indicates to the software whether any tasks (with INT=0) have completed and counted towards interrupt coalescing (that is this is set if and only if INTC counter > 0). 0x1: At least one INT0 task.." "INT0 Task completions have not occurred since..,At least one INT0 task completion has been.." rbitfld.long 0x14 17.--19. "CQIC_RSVD2,These bits (CQIC_RSVD2) of the CQIC register are reserved. They always return 0." "0,1,2,3,4,5,6,7" newline bitfld.long 0x14 16. "INTC_RST,Counter and Timer Reset When host driver writes 1 the interrupt coalescing timer and counter are reset. 0x1: Interrupt coalescing timer and counter are reset 0x0: No Effect" "No Effect,Interrupt coalescing timer and counter are reset" bitfld.long 0x14 15. "INTC_TH_WEN,Interrupt Coalescing Counter Threshold Write Enable When software writes 1 to this bit the value INTC_TH is updated with the contents written on the same cycle. 0x0: Clears INTC_TH_WEN 0x1: Sets INTC_TH_WEN" "Clears INTC_TH_WEN,Sets INTC_TH_WEN" newline rbitfld.long 0x14 13.--14. "CQIC_RSVD1,These bits (CQIC_RSVD1) of the CQIC register are reserved. They always return 0." "0,1,2,3" hexmask.long.byte 0x14 8.--12. 1. "INTC_TH,Interrupt Coalescing Counter Threshold filed Software uses this field to configure the number of task completions (only tasks with INT=0 in the Task Descriptor) which are required in order to generate an interrupt. Counter Operation: As data.." newline bitfld.long 0x14 7. "TOUT_VAL_WEN,When software writes 1 to this bit the value TOUT_VAL is updated with the contents written on the same cycle. 0x0: clears TOUT_VAL_WEN 0x1: Sets TOUT_VAL_WEN" "clears TOUT_VAL_WEN,Sets TOUT_VAL_WEN" hexmask.long.byte 0x14 0.--6. 1. "TOUT_VAL,Interrupt Coalescing Timeout Value Software uses this field to configure the maximum time allowed between the completion of a task on the bus and the generation of an interrupt. Timer Operation: The timer is reset by software during the.." line.long 0x18 "CQTDLBA,This register is used for configuring the lower 32 bits of the byte address of the head of the Task Descriptor List in the host memory." hexmask.long 0x18 0.--31. 1. "TDLBA,This register stores the LSB bits (31:0) of the byte address of the head of the Task Descriptor List in system memory. The size of the task descriptor list is 32 * (Task Descriptor size + Transfer Descriptor size) as configured by the host driver." line.long 0x1C "CQTDLBAU,This register is used for configuring the upper 32 bits of the byte address of the head of the Task Descriptor List in the host memory." hexmask.long 0x1C 0.--31. 1. "TDLBAU,This register stores the MSB bits (63:32) of the byte address of the head of the Task Descriptor List in system memory. The size of the task descriptor list is 32 * (Task Descriptor size + Transfer Descriptor size) as configured by Host driver." line.long 0x20 "CQTDBR,Using this register. software triggers CQE to process a new task." hexmask.long 0x20 0.--31. 1. "DBR,The software configures TDLBA and TDLBAU and enable CQE in CQCFG before using this register. Writing 1 to bit n of this register triggers CQE to start processing the task encoded in slot n of the TDL. Writing 0 by the software does not have any.." line.long 0x24 "CQTCN,This register is used by CQE to notify software about completed tasks." hexmask.long 0x24 0.--31. 1. "TCN,Task Completion Notification Each of the 32 bits are bit mapped to the 32 tasks. - Bit-N(1): Task-N has completed execution (with success or errors) - Bit-N(0): Task-N has not completed could be pending or not submitted. On task completion software.." rgroup.long 0x30++0x7 line.long 0x0 "CQDQS,This register stores the most recent value of the device's queue status." hexmask.long 0x0 0.--31. 1. "DQS,Device Queue Status Each of the 32 bits are bit mapped to the 32 tasks. - Bit-N(1): Device has marked task N as ready for execution - Bit-N(0): Task-N is not ready for execution. This task could be pending in device or not submitted. Host controller.." line.long 0x4 "CQDPT,This register maintains the list of tasks that are queued into device and are awaiting execution completion." hexmask.long 0x4 0.--31. 1. "DPT,Device-Pending Tasks Each of the 32 bits are bit mapped to the 32 tasks. - Bit-N(1): Task-N has been successfully queued into the device and is awaiting execution - Bit-N(0): Task-N is not yet queued. Bit n of this register is set if and only if.." group.long 0x38++0x3 line.long 0x0 "CQTCLR,This register is used for removing an outstanding task in the CQE. The register must be used only when CQE is in Halt state." hexmask.long 0x0 0.--31. 1. "TCLR,Writing 1 to bit n of this register orders CQE to clear a task that the software has previously issued. This bit can only be written when CQE is in Halt state as indicated in CQCFG register Halt bit. When software writes 1 to a bit in this register.." group.long 0x40++0x7 line.long 0x0 "CQSSC1,This register is used for removing an outstanding task in the CQE. The register controls when SEND_QUEUE_STATUS commands are sent." hexmask.long.word 0x0 20.--31. 1. "RSVD_20_31,These bits of the CQSSC1 register are reserved. They always return 0." hexmask.long.byte 0x0 16.--19. 1. "SQSCMD_BLK_CNT,This field indicates when SQS CMD is sent while data transfer is in progress. A value of 'n' indicates that CQE sends status command on the CMD line during the transfer of data block BLOCK_CNT-n on the data lines where BLOCK_CNT is the.." newline hexmask.long.word 0x0 0.--15. 1. "SQSCMD_IDLE_TMR,This field configures the polling period to be used when using periodic SEND_QUEUE_STATUS (CMD13) polling. Periodic polling is used when tasks are pending in the device but no data transfer is in progress. When a SEND_QUEUE_STATUS.." line.long 0x4 "CQSSC2,The register is used for configuring the RCA field in SEND_QUEUE_STATUS command argument." hexmask.long.word 0x4 16.--31. 1. "RSVD_16_31,These bits of the CQSSC2 register are reserved. They always return 0." hexmask.long.word 0x4 0.--15. 1. "SQSCMD_RCA,This field provides CQE with the contents of the 16-bit RCA field in SEND_QUEUE_STATUS (CMD13) command argument. CQE copies this field to bits 31:16 of the argument when transmitting SEND_QUEUE_STATUS (CMD13) command." rgroup.long 0x48++0x3 line.long 0x0 "CQCRDCT,This register stores the response of last executed DCMD." hexmask.long 0x0 0.--31. 1. "DCMD_RESP,This register contains the response of the command generated by the last direct command (DCMD) task that was sent. Contents of this register are valid only after bit 31 of CQTDBR register is cleared by the controller." group.long 0x50++0x3 line.long 0x0 "CQRMEM,This register controls the generation of response error detect (RED) interrupt. Only the bits enabled here can contribute to RED." hexmask.long 0x0 0.--31. 1. "RESP_ERR_MASK,The bits of this field are bit mapped to the device response. This bit is used as an interrupt mask on the device status filed that is received in R1/R1b responses. - 1: When a R1/R1b response is received with a bit i in the device status.." rgroup.long 0x54++0xB line.long 0x0 "CQTERRI,This register is updated by CQE when an error occurs on data or command related to a task activity. When such an error is detected by CQE or indicated by the eMMC controller. CQE stores the following in the CQTERRI register: task IDs and indices.." bitfld.long 0x0 31. "TRANS_ERR_FIELDS_VALID,This bit is updated when an error is detected while a data transfer transaction was in progress. 0x0: Ignore contents of TRANS_ERR_TASKID and TRANS_ERR_CMD_INDX 0x1: data transfer related error detected. Check contents of.." "Ignore contents of TRANS_ERR_TASKID and..,data transfer related error detected" bitfld.long 0x0 29.--30. "RSVD_30_29,These bits (RSVD_30_29) of the CQTERRI register are reserved. They always return 0." "0,1,2,3" newline hexmask.long.byte 0x0 24.--28. 1. "TRANS_ERR_TASKID,This field captures the ID of the task that was executed and whose data transfer has errors." bitfld.long 0x0 22.--23. "RSVD_23_22,These bits (RSVD_23_22) of the CQTERRI register are reserved. They always return 0." "0,1,2,3" newline hexmask.long.byte 0x0 16.--21. 1. "TRANS_ERR_CMD_INDX,This field captures the index of the command that was executed and whose data transfer has errors." bitfld.long 0x0 15. "RESP_ERR_FIELDS_VALID,This bit is updated when an error is detected while a command transaction was in progress. 0x0: Ignore contents of RESP_ERR_TASKID and RESP_ERR_CMD_INDX 0x1: Response-related error is detected. Check contents of RESP_ERR_TASKID and.." "Ignore contents of RESP_ERR_TASKID and..,Response-related error is detected" newline bitfld.long 0x0 13.--14. "RSVD_13_14,These bits (RSVD_13_14) of the CQTERRI register are reserved. They always return 0." "0,1,2,3" hexmask.long.byte 0x0 8.--12. 1. "RESP_ERR_TASKID,This field captures the ID of the task which was executed on the command line when the error occurred." newline bitfld.long 0x0 6.--7. "RSVD_6_7,These bits (RSVD_6_7) of the CQTERRI register are reserved. They always return 0." "0,1,2,3" hexmask.long.byte 0x0 0.--5. 1. "RESP_ERR_CMD_INDX,This field captures the index of the command that was executed on the command line when the error occurred." line.long 0x4 "CQCRI,This register stores the index of the last received command response." hexmask.long 0x4 6.--31. 1. "RSVD_31_6,These bits of the CQCRI register are reserved. They always return 0." hexmask.long.byte 0x4 0.--5. 1. "CMD_RESP_INDX,Last Command Response index This field stores the index of the last received command response. Controller updates the value every time a command response is received." line.long 0x8 "CQCRA,This register stores the argument of the last received command response." hexmask.long 0x8 0.--31. 1. "CMD_RESP_ARG,Last Command Response argument This field stores the argument of the last received command response. Controller updates the value every time a command response is received." tree.end tree "DWC_mshc_phy_block (This register block has PHY related registers)" base ad:0x768 group.long 0x0++0x3 line.long 0x0 "PHY_CNFG,SD/eMMC PHY general configuration register" hexmask.long.byte 0x0 20.--23. 1. "PAD_SN,NMOS TX drive strength control. Common config for all for SD/eMMC Pads." hexmask.long.byte 0x0 16.--19. 1. "PAD_SP,PMOS TX drive strength control. Common config for all for SD/eMMC Pads." newline rbitfld.long 0x0 1. "PHY_PWRGOOD,Phy's Power Good status is captured here. Ensure this is '1' before stating transactions." "0,1" bitfld.long 0x0 0. "PHY_RSTN,Active-Low reset control for PHY write '0' to reset PHY Write '1' to deassert reset." "0,1" group.word 0x4++0xF line.word 0x0 "CMDPAD_CNFG,SD/eMMC PHY's Command/Response PAD settings are controlled here" hexmask.word.byte 0x0 9.--12. 1. "TXSLEW_CTRL_N,Slew control for N-Type CMD Pad's TX" hexmask.word.byte 0x0 5.--8. 1. "TXSLEW_CTRL_P,Slew control for P-Type CMD Pad's TX" newline bitfld.word 0x0 3.--4. "WEAKPULL_EN,Pull-up/Pul-down enable control for CMD PAD 0x0: Pull-up and pull-down functionality disabled 0x3: Should not be used 0x2: Weak pull down enabled 0x1: Weak pull up enabled" "Pull-up and pull-down functionality disabled,Weak pull up enabled,Weak pull down enabled,Should not be used" bitfld.word 0x0 0.--2. "RXSEL,Reciver type select for PAD. Controls the RXSEL value of SD/eMMC PHY CMD PAD" "0,1,2,3,4,5,6,7" line.word 0x2 "DATPAD_CNFG,SD/eMMC PHY's Data PAD settings are controlled here. common settings for all data pads" hexmask.word.byte 0x2 9.--12. 1. "TXSLEW_CTRL_N,Slew control for N-Type DATA Pad's TX" hexmask.word.byte 0x2 5.--8. 1. "TXSLEW_CTRL_P,Slew control for P-Type DATA Pad's TX" newline bitfld.word 0x2 3.--4. "WEAKPULL_EN,Pull-up/Pull-down enable control for DATA PADs 0x0: Pull-up and pull-down functionality disabled 0x3: Should not be used 0x2: Weak pull down enabled 0x1: Weak pull up enabled" "Pull-up and pull-down functionality disabled,Weak pull up enabled,Weak pull down enabled,Should not be used" bitfld.word 0x2 0.--2. "RXSEL,Reciver type select for PAD. Controls the RXSEL value of SD/eMMC PHY DATA PADs" "0,1,2,3,4,5,6,7" line.word 0x4 "CLKPAD_CNFG,SD/eMMC PHY's CLK PAD settings are controlled here." hexmask.word.byte 0x4 9.--12. 1. "TXSLEW_CTRL_N,Slew control for N-Type CLK Pad's TX" hexmask.word.byte 0x4 5.--8. 1. "TXSLEW_CTRL_P,Slew control for P-Type CLK Pad's TX" newline bitfld.word 0x4 3.--4. "WEAKPULL_EN,Pull-up/Pul-down enable control for CLK PAD 0x0: Pull-up and pull-down functionality disabled 0x3: Should not be used 0x2: Weak pull down enabled 0x1: Weak pull up enabled" "Pull-up and pull-down functionality disabled,Weak pull up enabled,Weak pull down enabled,Should not be used" bitfld.word 0x4 0.--2. "RXSEL,Reciver type select for PAD. Controls the RXSEL value of SD/eMMC PHY CLK PAD" "0,1,2,3,4,5,6,7" line.word 0x6 "STBPAD_CNFG,SD/eMMC PHY's Strobe PAD settings are controlled here." hexmask.word.byte 0x6 9.--12. 1. "TXSLEW_CTRL_N,Slew control for N-Type Strobe Pad's TX" hexmask.word.byte 0x6 5.--8. 1. "TXSLEW_CTRL_P,Slew control for P-Type Strobe Pad's TX" newline bitfld.word 0x6 3.--4. "WEAKPULL_EN,Pull-up/Pul-down enable control for STROBE PAD 0x0: Pull-up and pull-down functionality disabled 0x3: Should not be used 0x2: Weak pull down enabled 0x1: Weak pull up enabled" "Pull-up and pull-down functionality disabled,Weak pull up enabled,Weak pull down enabled,Should not be used" bitfld.word 0x6 0.--2. "RXSEL,Reciver type select for PAD. Controls the RXSEL value of SD/eMMC PHY STROBE PAD" "0,1,2,3,4,5,6,7" line.word 0x8 "RSTNPAD_CNFG,SD/eMMC PHY's RSTN PAD settings are controlled here." hexmask.word.byte 0x8 9.--12. 1. "TXSLEW_CTRL_N,Slew control for N-Type RST_N Pad's TX" hexmask.word.byte 0x8 5.--8. 1. "TXSLEW_CTRL_P,Slew control for P-Type RST_N Pad's TX" newline bitfld.word 0x8 3.--4. "WEAKPULL_EN,Pull-up/Pul-down enable control for RST_N PAD(s) 0x0: Pull-up and pull-down functionality disabled 0x3: Should not be used 0x2: Weak pull down enabled 0x1: Weak pull up enabled" "Pull-up and pull-down functionality disabled,Weak pull up enabled,Weak pull down enabled,Should not be used" bitfld.word 0x8 0.--2. "RXSEL,Reciver type select for PAD. Controls the RXSEL value of SD/eMMC PHY RST_N PAD(s)" "0,1,2,3,4,5,6,7" line.word 0xA "PADTEST_CNFG,PAD TEST Path and direction control" hexmask.word 0xA 4.--15. 1. "TEST_OE,test interface OE control. Drive's PHY's itest_oe inputs." rbitfld.word 0xA 1.--3. "RSVD_1,RSVD1 field is reserved" "0,1,2,3,4,5,6,7" newline bitfld.word 0xA 0. "TESTMODE_EN,enables test mode interface for all PADS. Functional interface is disabled. 0x0: PAD's functional mode I/F is active 0x1: PAD's test mode interface is active" "PAD's functional mode I/F is active,PAD's test mode interface is active" line.word 0xC "PADTEST_OUT,PAD TEST Path Data out. Drives itest_a input of SD/eMMC PHY" hexmask.word 0xC 0.--11. 1. "TESTDATA_OUT,Data written here is reflected on corresponding itest_a. Indivitual bits are mapped to corresponding itest_a inputs of the PHY" line.word 0xE "PADTEST_IN,PAD TEST Path Data in. reflects value of otest_y output of SD/eMMC PHY" hexmask.word 0xE 0.--11. 1. "TESTDATA_IN,individual bits here capture data avaliable on corresponding otest_y output. should be used for DC test and low freq data patterns." group.word 0x18++0x1 line.word 0x0 "PRBS_CNFG,Register to configure PRBS engine" hexmask.word 0x0 0.--15. 1. "INIT_SEED,Value programmed here is used as SEED for PRBS engine" group.byte 0x1A++0x0 line.byte 0x0 "PHYLPBK_CNFG,Register to setup loopback mode" bitfld.byte 0x0 0. "PHYLPBK_EN,PHY Local loop back mode is enable 0x0: Controller is not in PHY loopback mode 0x1: Controller is now in PHY Loopback mode" "Controller is not in PHY loopback mode,Controller is now in PHY Loopback mode" group.byte 0x1C++0x2 line.byte 0x0 "COMMDL_CNFG,Config register to settings common to all DelayLines used in PHY" bitfld.byte 0x0 1. "DLOUT_EN,When '1' DL outputs can be sampled on PADs. Drives idlout_en for all PADs 0x0: DelayLine outputs on PAD disabled 0x1: DelayLine outputs on PAD enabled" "DelayLine outputs on PAD disabled,DelayLine outputs on PAD enabled" bitfld.byte 0x0 0. "DLSTEP_SEL,DelayLine's per step delay selection Drives PHY's idl_step input" "0,1" line.byte 0x1 "SDCLKDL_CNFG,Settings for SD/eMMC CLK DelayLine." bitfld.byte 0x1 4. "UPDATE_DC,Prepares DealyLine for code update when '1'. Its recommended that this bit is 1 when SDCLKDL_DC is being written. Ensure this is '0' when not updating code. Note: Turn-off card clock using CLK_CTRL_R.SD_CLK_EN before programing this field. 0x1:.." "DelayLine output is enabled,output of DelayLine is DelayLine output active" bitfld.byte 0x1 2.--3. "INPSEL_CNFG,Drives SD/eMMC CLK DelayLine's config input. Value here selects the input source to DelayLine" "0,1,2,3" newline bitfld.byte 0x1 1. "BYPASS_EN,Drives SD/eMMC CLK DelayLine's bypassen input 0x1: DelayLine is bypass mode 0x0: Delay line active mode" "Delay line active mode,DelayLine is bypass mode" bitfld.byte 0x1 0. "EXTDLY_EN,Drives SD/eMMC CLK DelayLine's extdlyen input 0x0: Delay line defaut range setting 0x1: DelayLine works with extended delay range setting" "Delay line defaut range setting,DelayLine works with extended delay range setting" line.byte 0x2 "SDCLKDL_DC,SD/eMMC CLK DelayLine Delay Code value" hexmask.byte 0x2 0.--6. 1. "CCKDL_DC,Drives SD/eMMC CLK DelayLine's Delay Code input. Value here Selects the number of active stages in the card clock delay line. Note: Turn-off card clock using CLK_CTRL_R.SD_CLK_EN before programing this field." group.byte 0x20++0x1 line.byte 0x0 "SMPLDL_CNFG,SD/eMMC cclk_rx DelayLine configuration settings" bitfld.byte 0x0 4. "INPSEL_OVERRIDE,PHY's Sampling delay line config is controlled by controller using sample_cclk_sel this signal overides sample_cclk_sel such that INPSEL_CFG field directly control's PHY's config input. - 0x0 : Controller logic drive Sampling delay line.." "Controller logic drive Sampling delay line config,SMPLDL_CNFG" bitfld.byte 0x0 2.--3. "INPSEL_CNFG,Drives CCLK_RX DelayLine's config input. Value here selects the input source to DelayLine" "0,1,2,3" newline bitfld.byte 0x0 1. "BYPASS_EN,Drives CCLK_RX DelayLine's bypassen input 0x1: DelayLine is bypass mode 0x0: Delay line active mode" "Delay line active mode,DelayLine is bypass mode" bitfld.byte 0x0 0. "EXTDLY_EN,Drives CCLK_RX DelayLine's extdlyen input 0x0: Delay line defaut range setting 0x1: DelayLine works with extended delay range setting" "Delay line defaut range setting,DelayLine works with extended delay range setting" line.byte 0x1 "ATDL_CNFG,SD/eMMC drift_cclk_rx DelayLine configuration settings" bitfld.byte 0x1 2.--3. "INPSEL_CNFG,Drives drift_cclk_rx DelayLine's config input. Value here selects the input source to DelayLine" "0,1,2,3" bitfld.byte 0x1 1. "BYPASS_EN,Drives drift_cclk_rx DelayLine's bypassen input 0x1: DelayLine is bypass mode 0x0: Delay line active mode" "Delay line active mode,DelayLine is bypass mode" newline bitfld.byte 0x1 0. "EXTDLY_EN,Drives drift_cclk_rx DelayLine's extdlyen input 0x0: Delay line defaut range setting 0x1: DelayLine works with extended delay range setting" "Delay line defaut range setting,DelayLine works with extended delay range setting" group.byte 0x24++0x2 line.byte 0x0 "DLL_CTRL,SD/eMMC PHY's DLL Control settings register" hexmask.byte 0x0 3.--7. 1. "RSVD_3_7,These bits of the register are reserved." bitfld.byte 0x0 2. "SLV_SWDC_UPDATE,Corresponding output drives PHY's DLL Slave's dc update input. This is used to turn-off Slave Delay line's output when changing its delay code using DLL_OFFST register 0x1: Update in progress 0x0: Update completed" "Update completed,Update in progress" newline bitfld.byte 0x0 1. "OFFST_EN,Enables offset mode of PHY when DLL is enabled. when DLL is disabled this allows direct control of delay generated by DLL's Slave 0x0: offset value is invalid 0x1: Offset value is valid" "offset value is invalid,Offset value is valid" bitfld.byte 0x0 0. "DLL_EN,Enable's DLL when '1' 0x0: PHY DLL is disabled 0x1: PHY DLL is enabled" "PHY DLL is disabled,PHY DLL is enabled" line.byte 0x1 "DLL_CNFG1,SD/eMMC PHY DLL configuration register 1" bitfld.byte 0x1 4.--5. "SLVDLY,Sets the value of DLL slave's update delay input islv_update_dly" "0,1,2,3" bitfld.byte 0x1 0.--2. "WAITCYCLE,Sets the value of DLL's wait cycle input" "0,1,2,3,4,5,6,7" line.byte 0x2 "DLL_CNFG2,SD/eMMC PHY DLL configuration register 2" hexmask.byte 0x2 0.--6. 1. "JUMPSTEP,Sets the value of DLL's jump step input" group.byte 0x28++0x2 line.byte 0x0 "DLLDL_CNFG,SD/eMMC PHY DLL MST & Slave DL configuration settings" bitfld.byte 0x0 7. "SLV_BYPASS,Bypass enable control for Slave DL" "0,1" bitfld.byte 0x0 5.--6. "SLV_INPSEL,Clock source select for Slave DL" "0,1,2,3" newline bitfld.byte 0x0 4. "SLV_EXTDLYEN,Enable Extended delay mode for Slave" "0,1" bitfld.byte 0x0 3. "MST_BYPASS,Bypass enable control for Master DL" "0,1" newline bitfld.byte 0x0 1.--2. "MST_INPSEL,Clock source select for Master DL" "0,1,2,3" bitfld.byte 0x0 0. "MST_EXTDLYEN,Enable Extended delay mode for master" "0,1" line.byte 0x1 "DLL_OFFST,SD/eMMC PHY DLL Offset value settings" hexmask.byte 0x1 0.--6. 1. "OFFST,Sets the value of DLL's offset input" line.byte 0x2 "DLLMST_TSTDC,SD/eMMC PHY DLL Master testing Delay code register" hexmask.byte 0x2 0.--6. 1. "MSTTST_DC,Sets the value of DLL's Master test code input when DLL is disabled." group.word 0x2C++0x1 line.word 0x0 "DLLLBT_CNFG,SD/eMMC PHY DLL Low Bandwidth Timer configuration register" hexmask.word 0x0 0.--15. 1. "LBT_LOADVAL,Sets the value of DLL's olbt_loadval input. Controls the lbt timer's timeout value at which DLL runs a revalidation cycle." rgroup.byte 0x2E++0x0 line.byte 0x0 "DLL_STATUS,SD/eMMC PHY DLL Status register" bitfld.byte 0x0 1. "ERROR_STS,Captures the value of DLL's lock error status information. Value is valid only when LOCK_STS is set. - IF LOCK_STS =1 and ERR_STS = 0 then DLL is locked and no errors are generated - IF LOCK_STS =1 and ERR_STS = 1 then DLL is locked to default.." "DLL has not locked,DLL is locked and ready" bitfld.byte 0x0 0. "LOCK_STS,Captures the value of DLL's lock status information 0x1: DLL is locked and ready 0x0: DLL has not locked" "DLL has not locked,DLL is locked and ready" rgroup.byte 0x30++0x0 line.byte 0x0 "DLLDBG_MLKDC,SD/eMMC PHY DLL's Master lock code status" hexmask.byte 0x0 0.--6. 1. "MSTLKDC,Captures the value Delay Code to which DLL's Master has locked" rgroup.byte 0x32++0x0 line.byte 0x0 "DLLDBG_SLKDC,SD/eMMC PHY DLL's Slave lock code status" hexmask.byte 0x0 0.--6. 1. "SLVLKDC,Captures the value Delay Code to which DLL's Slave has locked" tree.end tree.end repeat.end elif (CORENAME()=="CORTEXA55") repeat 4. (increment 1. 1.) (list ad:0x34180000 ad:0x34190000 ad:0x341A0000 ad:0x341B0000) tree "MSHC$1" base $2 tree "DWC_mshc_block (This register block defines the standard SD Host Controller register set)" group.long 0x0++0x3 line.long 0x0 "SDMASA_R,This register is used to configure a 32-bit Block Count or an SDMA System Address based on the Host Version 4 Enable bit in the Host Control 2 register. This register is applicable for both SD and eMMC modes." hexmask.long 0x0 0.--31. 1. "BLOCKCNT_SDMASA,32-bit Block Count (SDMA System Address) - SDMA System Address (Host Version 4 Enable = 0): This register contains the system memory address for an SDMA transfer in the 32-bit addressing mode. When the Host Controller stops an SDMA.." group.word 0x4++0x3 line.word 0x0 "BLOCKSIZE_R,This register is used to configure an SDMA buffer boundary and the number of bytes in a data block. This register is applicable for both SD and eMMC modes." newline rbitfld.word 0x0 15. "RSVD_BLOCKSIZE15,This bit of the BLOCKSIZE_R register is reserved. It always returns 0." "0,1" newline bitfld.word 0x0 12.--14. "SDMA_BUF_BDARY,SDMA Buffer Boundary These bits specify the size of contiguous buffer in system memory. The SDMA transfer waits at every boundary specified by these fields and the Host Controller generates the DMA interrupt to request the Host Driver to.." "0,1,2,3,4,5,6,7" newline hexmask.word 0x0 0.--11. 1. "XFER_BLOCK_SIZE,Transfer Block Size These bits specify the block size of data transfers. In case of memory it is set to 512 bytes. It can be accessed only if no transaction is executing. Read operations during transfers may return an invalid value and.." line.word 0x2 "BLOCKCOUNT_R,This register is used to configure the number of data blocks. This register is applicable for both SD and eMMC modes." newline hexmask.word 0x2 0.--15. 1. "BLOCK_CNT,16-bit Block Count - If the Host Version 4 Enable bit is set 0 or the 16-bit Block Count register is set to non-zero the 16-bit Block Count register is selected. - If the Host Version 4 Enable bit is set 1 and the 16-bit Block Count register.." group.long 0x8++0x3 line.long 0x0 "ARGUMENT_R,This register is used to configure the SD/eMMC command argument." hexmask.long 0x0 0.--31. 1. "ARGUMENT,Command Argument These bits specify the SD/eMMC command argument that is specified in bits 39-8 of the Command format." group.word 0xC++0x3 line.word 0x0 "XFER_MODE_R,This register is used to control the operation of data transfers for an SD/eMMC mode. The Host driver sets this register before issuing a command that transfers data." newline hexmask.word.byte 0x0 9.--15. 1. "RSVD,These bits of the XFER_MODE_R register are reserved. They always return 0." newline bitfld.word 0x0 8. "RESP_INT_DISABLE,Response Interrupt Disable The Host Controller supports response check function to avoid overhead of response error check by the Host driver. Response types of only R1 and R5 can be checked by the Controller. If Host Driver checks the.." "Response Interrupt is enabled,Response Interrupt is disabled" newline bitfld.word 0x0 7. "RESP_ERR_CHK_ENABLE,Response Error Check Enable The Host Controller supports response check function to avoid overhead of response error check by Host driver. Response types of only R1 and R5 can be checked by the Controller. If the Host Controller.." "Response Error Check is disabled,Response Error Check is enabled" newline bitfld.word 0x0 6. "RESP_TYPE,Response Type R1/R5 This bit selects either R1 or R5 as a response type when the Response Error Check is selected. Error statuses checked in R1: - OUT_OF_RANGE - ADDRESS_ERROR - BLOCK_LEN_ERROR - WP_VIOLATION - CARD_IS_LOCKED - COM_CRC_ERROR -.." "R1,R5" newline bitfld.word 0x0 5. "MULTI_BLK_SEL,Multi/Single Block Select This bit is set when issuing multiple-block transfer commands using the DAT line. If this bit is set to 0 it is not necessary to set the Block Count register. 0x1: Multiple Block 0x0: Single Block" "Single Block,Multiple Block" newline bitfld.word 0x0 4. "DATA_XFER_DIR,Data Transfer Direction Select This bit defines the direction of DAT line data transfers. This bit is set to 1 by the Host Driver to transfer data from the SD/eMMC card to the Host Controller and it is set to 0 for all other commands. 0x1:.." "Write,Read" newline bitfld.word 0x0 2.--3. "AUTO_CMD_ENABLE,Auto Command Enable This field determines use of Auto Command functions. Note: In SDIO this field must be set as 00b (Auto Command Disabled). 0x1: Auto CMD12 Enable 0x2: Auto CMD23 Enable 0x3: Auto CMD Auto Select 0x0: Auto Command.." "Auto Command Disabled,Auto CMD12 Enable,Auto CMD23 Enable,Auto CMD Auto Select" newline bitfld.word 0x0 1. "BLOCK_COUNT_ENABLE,Block Count Enable This bit is used to enable the Block Count register which is relevant for multiple block transfers. If this bit is set to 0 the Block Count register is disabled which is useful in executing an infinite transfer." "Disable,Enable" newline bitfld.word 0x0 0. "DMA_ENABLE,DMA Enable This bit enables the DMA functionality. If this bit is set to 1 a DMA operation begins when the Host Driver writes to the Command register. You can select one of the DMA modes by using DMA Select in the Host Control 1 register." "No data transfer or Non-DMA data transfer,DMA Data transfer" line.word 0x2 "CMD_R,This register is used to provide the information related to a command and a response packet. This register is applicable for an SD/eMMC mode." newline rbitfld.word 0x2 14.--15. "RSVD,These bits of the CMD_R register are reserved. They always return 0." "0,1,2,3" newline hexmask.word.byte 0x2 8.--13. 1. "CMD_INDEX,Command Index These bits are set to the command number that is specified in bits 45-40 of the Command Format." newline bitfld.word 0x2 6.--7. "CMD_TYPE,Command Type These bits indicate the command type. Note: While issuing Abort CMD using CMD12/CMD52 or reset CMD using CMD0/CMD52 CMD_TYPE field shall be set to 0x3. 0x3: Abort 0x0: Normal 0x2: Resume 0x1: Suspend" "Normal,Suspend,Resume,Abort" newline bitfld.word 0x2 5. "DATA_PRESENT_SEL,Data Present Select This bit is set to 1 to indicate that data is present and that the data is transferred using the DAT line. This bit is set to 0 in the following instances: - Command using the CMD line - Command with no data transfer.." "No Data Present,Data Present" newline bitfld.word 0x2 4. "CMD_IDX_CHK_ENABLE,Command Index Check Enable This bit enables the Host Controller to check the index field in the response to verify if it has the same value as the command index. If the value is not the same it is reported as a Command Index error." "Disable,Enable" newline bitfld.word 0x2 3. "CMD_CRC_CHK_ENABLE,Command CRC Check Enable This bit enables the Host Controller to check the CRC field in the response. If an error is detected it is reported as a Command CRC error. Note: - CRC Check enable must be set to 0 for the command with no.." "Disable,Enable" newline bitfld.word 0x2 2. "SUB_CMD_FLAG,Sub Command Flag This bit distinguishes between a main command and a sub command. 0x0: Main Command 0x1: Sub Command" "Main Command,Sub Command" newline bitfld.word 0x2 0.--1. "RESP_TYPE_SELECT,Response Type Select This bit indicates the type of response expected from the card. 0x0: No Response 0x1: Response Length 136 0x2: Response Length 48 0x3: Response Length 48; Check Busy after response" "No Response,Response Length 136,Response Length 48,Response Length 48; Check Busy after response" rgroup.long 0x10++0xF line.long 0x0 "RESP01_R,This register stores 39-08 bits of the Response Field for an SD/eMMC mode. The response for an SD/eMMC command can be a maximum of 128 bits. These 128 bits are segregated into four 32-bit registers: RESP01_R. RESP23_R. RESP45_R and RESP67_R." hexmask.long 0x0 0.--31. 1. "RESP01,Command Response These bits reflect 39-8 bits of SD/eMMC Response Field. Note: For Auto CMD the 32-bit response (bits 39-8 of the Response Field) is updated in the RESP67_R register." line.long 0x4 "RESP23_R,This register stores 71-40 bits of the Response Field for an SD/eMMC mode. This register is used to store the response from the cards. The response can be a maximum of 128 bits. These 128 bits are segregated into four 32-bit registers: RESP01_R." hexmask.long 0x4 0.--31. 1. "RESP23,Command Response These bits reflect 71-40 bits of the SD/eMMC Response Field." line.long 0x8 "RESP45_R,This register stores 103-72 bits of the Response Field for an SD/eMMC mode. The response for SD/eMMC command can be a maximum of 128 bits. These 128 bits are segregated into four 32-bit registers: RESP01_R. RESP23_R. RESP45_R and RESP67_R." hexmask.long 0x8 0.--31. 1. "RESP45,Command Response These bits reflect 103-72 bits of the Response Field." line.long 0xC "RESP67_R,This register stores 135-104 bits of the Response Field for an SD/eMMC mode. The SD/eMMC response can be a maximum of 128 bits. These 128 bits are segregated into four 32-bit registers: RESP01_R. RESP23_R. RESP45_R and RESP67_R." hexmask.long 0xC 0.--31. 1. "RESP67,Command Response These bits reflect bits 135-104 of SD/EMMC Response Field. Note: For Auto CMD this register also reflects the 32-bit response (bits 39-8 of the Response Field)." group.long 0x20++0x3 line.long 0x0 "BUF_DATA_R,This register is used to access the packet buffer. This register is applicable for an SD/eMMC/UHS-II mode." hexmask.long 0x0 0.--31. 1. "BUF_DATA,Buffer Data These bits enable access to the Host Controller packet buffer." rgroup.long 0x24++0x3 line.long 0x0 "PSTATE_REG,This register indicates the present status of the Host Controller. This register is applicable for an SD/eMMC/UHS-II mode." bitfld.long 0x0 31. "UHS2_IF_DETECT,UHS-II Interface Detection For SD/eMMC mode this bit always returns 0. 0x0: UHS-II interface is not detected 0x1: UHS-II interface is detected" "UHS-II interface is not detected,UHS-II interface is detected" newline bitfld.long 0x0 30. "LANE_SYNC,Lane Synchronization For SD/eMMC mode this bit always returns 0. 0x0: UHS-II PHY is not initialized 0x1: UHS-II PHY is initialized" "UHS-II PHY is not initialized,UHS-II PHY is initialized" newline bitfld.long 0x0 29. "IN_DORMANT_ST,In Dormant Status For SD/eMMC mode this bit always returns 0. 0x0: Not in DORMANT state 0x1: In DORMANT state" "Not in DORMANT state,In DORMANT state" newline bitfld.long 0x0 28. "SUB_CMD_STAT,Sub Command Status This bit is used to distinguish between a main command and a sub command status. 0x0: Main Command Status 0x1: Sub Command Status" "Main Command Status,Sub Command Status" newline bitfld.long 0x0 27. "CMD_ISSUE_ERR,Command Not Issued by Error This bit is set if a command cannot be issued after setting the command register due to an error except the Auto CMD12 error. 0x0: No error for issuing a command 0x1: Command cannot be issued" "No error for issuing a command,Command cannot be issued" newline bitfld.long 0x0 26. "RSVD_26,This bit of the PRESENT_ST_R register is reserved bits. It always returns 0." "0,1" newline bitfld.long 0x0 25. "HOST_REG_VOL,Host Regulator Voltage Stable This bit is used to check whether the host regulator voltage is stable for switching the voltage of UHS-I mode. This bit reflects the synchronized value of the host_reg_vol_stable signal. 0x0: Host Regulator.." "Host Regulator Voltage is not stable,Host Regulator Voltage is stable" newline bitfld.long 0x0 24. "CMD_LINE_LVL,Command-Line Signal Level This bit is used to check the CMD line level to recover from errors and for debugging. These bits reflect the value of the sd_cmd_in signal." "0,1" newline hexmask.long.byte 0x0 20.--23. 1. "DAT_3_0,DAT[3:0] Line Signal Level This bit is used to check the DAT line level to recover from errors and for debugging. These bits reflect the value of the sd_dat_in (lower nibble) signal." newline bitfld.long 0x0 19. "WR_PROTECT_SW_LVL,Write Protect Switch Pin Level This bit is supported only for memory and combo cards. This bit reflects the synchronized value of the card_write_prot signal. 0x0: Write protected 0x1: Write enabled" "Write protected,Write enabled" newline bitfld.long 0x0 18. "CARD_DETECT_PIN_LEVEL,Card Detect Pin Level This bit reflects the inverse synchronized value of the card_detect_n signal. 0x0: No card present 0x1: Card Present" "No card present,Card Present" newline bitfld.long 0x0 17. "CARD_STABLE,Card Stable This bit indicates the stability of the Card Detect Pin Level. A card is not detected if this bit is set to 1 and the value of the CARD_INSERTED bit is 0. 0x0: Reset or Debouncing 0x1: No Card or Inserted" "Reset or Debouncing,No Card or Inserted" newline bitfld.long 0x0 16. "CARD_INSERTED,Card Inserted This bit indicates whether a card has been inserted. The Host Controller debounces this signal so that Host Driver need not wait for it to stabilize. 0x0: Reset Debouncing or No card 0x1: Card Inserted" "Reset,Card Inserted" newline hexmask.long.byte 0x0 12.--15. 1. "RSVD_15_12,These bits of the PRESENT_STAT_R register are reserved. They always return 0." newline bitfld.long 0x0 11. "BUF_RD_ENABLE,Buffer Read Enable This bit is used for non-DMA transfers. This bit is set if valid data exists in the Host buffer. 0x0: Read disable 0x1: Read enable" "Read disable,Read enable" newline bitfld.long 0x0 10. "BUF_WR_ENABLE,Buffer Write Enable This bit is used for non-DMA transfers. This bit is set if space is available for writing data. 0x0: Write disable 0x1: Write enable" "Write disable,Write enable" newline bitfld.long 0x0 9. "RD_XFER_ACTIVE,Read Transfer Active This bit indicates whether a read transfer is active for SD/eMMC mode. 0x1: Transferring data 0x0: No valid data" "No valid data,Transferring data" newline bitfld.long 0x0 8. "WR_XFER_ACTIVE,Write Transfer Active This status indicates whether a write transfer is active for SD/eMMC mode. 0x1: Transferring data 0x0: No valid data" "No valid data,Transferring data" newline hexmask.long.byte 0x0 4.--7. 1. "DAT_7_4,DAT[7:4] Line Signal Level This bit is used to check the DAT line level to recover from errors and for debugging. These bits reflect the value of the sd_dat_in (upper nibble) signal." newline bitfld.long 0x0 3. "RE_TUNE_REQ,Re-Tuning Request DWC_mshc does not generate retuning request. The software must maintain the Retuning timer." "0,1" newline bitfld.long 0x0 2. "DAT_LINE_ACTIVE,DAT Line Active (SD/eMMC Mode only) This bit indicates whether one of the DAT lines on the SD/eMMC bus is in use. In the case of read transactions this bit indicates whether a read transfer is executing on the SD/eMMC bus. In the case of.." "DAT Line Inactive,DAT Line Active" newline bitfld.long 0x0 1. "CMD_INHIBIT_DAT,Command Inhibit (DAT) This bit is applicable for SD/eMMC mode and is generated if either DAT line active or Read transfer active is set to 1. If this bit is set to 0 it indicates that the Host Controller can issue subsequent SD/eMMC.." "Can issue command which used DAT line,Cannot issue command which used DAT line" newline bitfld.long 0x0 0. "CMD_INHIBIT,Command Inhibit (CMD) This bit indicates the following : - SD/eMMC mode: If this bit is set to 0 it indicates that the CMD line is not in use and the Host controller can issue an SD/eMMC command using the CMD line. This bit is set when the.." "Host Controller is ready to issue a command,Host Controller is not ready to issue a command" group.byte 0x28++0x3 line.byte 0x0 "HOST_CTRL1_R,This register is used to control the operation of the Host Controller. This register is applicable for an SD/eMMC/UHS-II mode." newline bitfld.byte 0x0 7. "CARD_DETECT_SIG_SEL,Card Detect Signal Selection This bit selects a source for card detection. When the source for the card detection is switched the interrupt must be disabled during the switching period. 0x1: Card Detect Test Level is selected (for.." "SDCD#,Card Detect Test Level is selected" newline bitfld.byte 0x0 6. "CARD_DETECT_TEST_LVL,Card Detect Test Level This bit is enabled while the Card Detect Signal Selection is set to 1 and it indicates whether a card inserted or not. 0x1: Card Inserted 0x0: No Card" "No Card,Card Inserted" newline bitfld.byte 0x0 5. "EXT_DAT_XFER,Extended Data Transfer Width This bit controls 8-bit bus width mode of embedded device. 0x0: Bus Width is selected by the Data Transfer Width 0x1: 8-bit Bus Width" "Bus Width is selected by the Data Transfer Width,?" newline bitfld.byte 0x0 3.--4. "DMA_SEL,DMA Select This field is used to select the DMA type. When Host Version 4 Enable is 1 in Host Control 2 register: - 0x0 - SDMA is selected - 0x1 - Reserved - 0x2 - ADMA2 is selected - 0x3 - ADMA2 or ADMA3 is selected When Host Version 4 Enable is.." "SDMA is selected,Reserved,ADMA2 is selected,ADMA2 or ADMA3 is selected" newline bitfld.byte 0x0 2. "HIGH_SPEED_EN,High Speed Enable (SD/eMMC Mode only) In SD/eMMC mode this bit is used to determine the selection of preset value for High Speed mode. Before setting this bit the Host Driver checks the High Speed Support in the Capabilities register." "Normal Speed mode,High Speed mode" newline bitfld.byte 0x0 1. "DAT_XFER_WIDTH,Data Transfer Width For SD/eMMC mode this bit selects the data transfer width of the Host Controller. The Host Driver sets it to match the data width of the SD/eMMC card. 0x1: 4-bit mode 0x0: 1-bit mode" "?,bit mode" newline bitfld.byte 0x0 0. "LED_CTRL,LED Control This bit is used to caution the user not to remove the card while the SD card is being accessed. The value is reflected on the led_control signal. 0x0: LED off 0x1: LED on" "LED off,LED on" line.byte 0x1 "PWR_CTRL_R,This register is used to control the bus power for the Card. This register is applicable for an SD. eMMC. and UHS-II modes." newline bitfld.byte 0x1 5.--7. "SD_BUS_VOL_VDD2,SD Bus Voltage Select for VDD2. This is irrelevant for SD/eMMC card. 0x6: Not used 0x7: Not used 0x0: VDD2 Not Supported 0x1: Reserved 0x2: Reserved 0x3: Reserved 0x4: Reserved for 1.2V 0x5: 1.8V" "VDD2 Not Supported,Reserved,Reserved,Reserved,Reserved for 1,?,Not used,Not used" newline bitfld.byte 0x1 4. "SD_BUS_PWR_VDD2,SD Bus Power for VDD2. This is irrelevant for SD/eMMC card. 0x0: Power off 0x1: Power on" "Power off,Power on" newline bitfld.byte 0x1 1.--3. "SD_BUS_VOL_VDD1,SD Bus Voltage Select for VDD1/eMMC Bus Voltage Select for VDD These bits enable the Host Driver to select the voltage level for an SD/eMMC card. Before setting this register the Host Driver checks the Voltage Support bits in the.." "Reserved,Reserved,Reserved,Reserved,Reserved,?,?,?" newline bitfld.byte 0x1 0. "SD_BUS_PWR_VDD1,SD Bus Power for VDD1 This bit enables VDD1 power of the card. This setting is available on the sd_vdd1_on output of DWC_mshc so that it can be used to control the VDD1 power supply of the card. Before setting this bit the SD Host Driver.." "Power off,Power on" line.byte 0x2 "BGAP_CTRL_R,This register is used by the host driver to control any operation related to Block Gap. This register is applicable for an SD/eMMC/UHS-II mode." newline hexmask.byte 0x2 4.--7. 1. "RSVD_7_4,These bits of the Block Gap Control register are reserved. They always return 0." newline bitfld.byte 0x2 3. "INT_AT_BGAP,Interrupt At Block Gap This bit is valid only in the 4-bit mode of an SDIO card and is used to select a sample point in the interrupt cycle. Setting to 1 enables interrupt detection at the block gap for a multiple block transfer. 0x0:.." "Disabled,Enabled" newline bitfld.byte 0x2 2. "RD_WAIT_CTRL,Read Wait Control This bit is used to enable the read wait protocol to stop read data using DAT[2] line if the card supports read wait. Otherwise the Host Controller has to stop the card clock to hold the read data. 0x0: Disable Read Wait.." "Disable Read Wait Control,Enable Read Wait Control" newline bitfld.byte 0x2 1. "CONTINUE_REQ,Continue Request This bit is used to restart the transaction which was stopped using the Stop At Block Gap Request. The Host Controller automatically clears this bit when the transaction restarts. If stop at block gap request is set to 1.." "No Affect,Restart" newline bitfld.byte 0x2 0. "STOP_BG_REQ,Stop At Block Gap Request This bit is used to stop executing read and write transactions at the next block gap for non-DMA SDMA and ADMA transfers. 0x1: Stop 0x0: Transfer" "Transfer,Stop" line.byte 0x3 "WUP_CTRL_R,This register is mandatory for the Host Controller. but the wakeup functionality depends on the Host Controller system hardware and software. The Host Driver maintains voltage on the SD Bus by setting the SD Bus Power to 1 in the Power Control.." newline hexmask.byte 0x3 3.--7. 1. "RSVD_7_3,These bits of Wakeup Control register are reserved. They always return 0." newline bitfld.byte 0x3 2. "CARD_REMOVAL,Wakeup Event Enable on SD Card Removal This bit enables wakeup event through Card Removal assertion in the Normal Interrupt Status register. For the SDIO card Wake Up Support (FN_WUS) in the Card Information Structure (CIS) register does.." "Disable,Enable" newline bitfld.byte 0x3 1. "CARD_INSERT,Wakeup Event Enable on SD Card Insertion This bit enables wakeup event through Card Insertion assertion in the Normal Interrupt Status register. FN_WUS (Wake Up Support) in CIS does not affect this bit. 0x0: Disable 0x1: Enable" "Disable,Enable" newline bitfld.byte 0x3 0. "CARD_INT,Wakeup Event Enable on Card Interrupt This bit enables wakeup event through a Card Interrupt assertion in the Normal Interrupt Status register. This bit can be set to 1 if FN_WUS (Wake Up Support) in CIS is set to 1. 0x0: Disable 0x1: Enable" "Disable,Enable" group.word 0x2C++0x1 line.word 0x0 "CLK_CTRL_R,This register controls SDCLK (card clock) in an SD/eMMC mode and RCLK in the UHS-II mode. This register is applicable for an SD/eMMC/UHS-II mode." newline hexmask.word.byte 0x0 8.--15. 1. "FREQ_SEL,SDCLK/RCLK Frequency Select These bits are used to select the frequency of the SDCLK signal. These bits depend on setting of Preset Value Enable in the Host Control 2 register. If Preset Value Enable = 0 these bits are set by the Host Driver." newline bitfld.word 0x0 6.--7. "UPPER_FREQ_SEL,These bits specify the upper 2 bits of 10-bit SDCLK/RCLK Frequency Select control. The value is reflected on the upper 2 bits of the card_clk_freq_sel signal." "0,1,2,3" newline bitfld.word 0x0 5. "CLK_GEN_SELECT,Clock Generator Select This bit is used to select the clock generator mode in SDCLK/RCLK Frequency Select. If Preset Value Enable = 0 this bit is set by the Host Driver. If Preset Value Enable = 1 this bit is automatically set to a value.." "Divided Clock Mode,Programmable Clock Mode" newline rbitfld.word 0x0 4. "RSVD_4,This bit of the CLK_CTRL_R register is reserved. It always returns 0." "0,1" newline bitfld.word 0x0 3. "PLL_ENABLE,PLL Enable This bit is used to activate the PLL (applicable when Host Version 4 Enable = 1). When Host Version 4 Enable = 0 INTERNAL_CLK_EN bit may be used to activate PLL. The value is reflected on the card_clk_en signal. Note: If this bit.." "PLL is in low power mode,PLL is enabled" newline bitfld.word 0x0 2. "SD_CLK_EN,SD/eMMC Clock Enable This bit stops the SDCLK or RCLK when set to 0. The SDCLK/RCLK Frequency Select bit can be changed when this bit is set to 0. The value is reflected on the clk2card_on pin. 0x0: Disable providing SDCLK/RCLK 0x1: Enable.." "Disable providing SDCLK/RCLK,Enable providing SDCLK/RCLK" newline rbitfld.word 0x0 1. "INTERNAL_CLK_STABLE,Internal Clock Stable This bit enables the Host Driver to check the clock stability twice after the Internal Clock Enable bit is set and after the PLL Enable bit is set. This bit reflects the synchronized value of the intclk_stable.." "Not Ready,Ready" newline bitfld.word 0x0 0. "INTERNAL_CLK_EN,Internal Clock Enable This bit is set to 0 when the Host Driver is not using the Host Controller or the Host Controller awaits a wakeup interrupt. The Host Controller must stop its internal clock to enter a very low power state. However.." "Stop,Oscillate" group.byte 0x2E++0x1 line.byte 0x0 "TOUT_CTRL_R,This register is used to set the Data Timeout Counter value for an SD/eMMC mode according to the timer clock defined by the Capabilities register. while initializig the Host Controller." newline hexmask.byte 0x0 4.--7. 1. "RSVD_7_4,These bits of the Timeout Control register are reserved. They always return 0." newline hexmask.byte 0x0 0.--3. 1. "TOUT_CNT,Data Timeout Counter Value. This value determines the interval by which DAT line timeouts are detected. The Timeout clock frequency is generated by dividing the base clock TMCLK value by this value. When setting this register prevent.." line.byte 0x1 "SW_RST_R,This register is used to generate a reset pulse by writing 1 to each bit of this register. After completing the reset. the Host Controller clears each bit. As it takes some time to complete a software reset. the Host Driver confirms that these.." newline hexmask.byte 0x1 3.--7. 1. "RSVD_7_3,These bits of the SW_RST_R register are reserved. They always return 0." newline bitfld.byte 0x1 2. "SW_RST_DAT,Software Reset For DAT line This bit is used in SD/eMMC mode and it resets only a part of the data circuit and the DMA circuit is also reset. The following registers and bits are cleared by this bit: - Buffer Data Port register -- Buffer is.." "Work,Reset" newline bitfld.byte 0x1 1. "SW_RST_CMD,Software Reset For CMD line This bit resets only a part of the command circuit to be able to issue a command. This reset is effective only for a command issuing circuit (including response error statuses related to Command Inhibit (CMD).." "Work,Reset" newline bitfld.byte 0x1 0. "SW_RST_ALL,Software Reset For All This reset affects the entire Host Controller except for the card detection circuit. During its initialization the Host Driver sets this bit to 1 to reset the Host Controller. All registers are reset except the.." "Work,Reset" group.word 0x30++0xB line.word 0x0 "NORMAL_INT_STAT_R,This register reflects the status of the Normal Interrupt. This register is applicable for an SD/eMMC/UHS-II mode." newline rbitfld.word 0x0 15. "ERR_INTERRUPT,Error Interrupt If any of the bits in the Error Interrupt Status register are set then this bit is set. 0x0: No Error 0x1: Error" "No Error,Error" newline bitfld.word 0x0 14. "CQE_EVENT,Command Queuing Event This status is set if Command Queuing/Crypto related event has occurred in eMMC/SD mode. Read CQHCI's CQIS/CRNQIS register for more details. 0x0: No Event 0x1: Command Queuing Event is detected" "No Event,Command Queuing Event is detected" newline rbitfld.word 0x0 13. "FX_EVENT,FX Event This status is set when R[14] of response register is set to 1 and Response Type R1/R5 is set to 0 in Transfer Mode register. This interrupt is used with response check function. 0x0: No Event 0x1: FX Event is detected" "No Event,FX Event is detected" newline rbitfld.word 0x0 12. "RE_TUNE_EVENT,Re-tuning Event This bit is set if the Re-Tuning Request changes from 0 to 1. Re-Tuning request is not supported." "0,1" newline rbitfld.word 0x0 11. "INT_C,INT_C (Embedded) This bit is set if INT_C is enabled and if INT_C# pin is in low level. The INT_C# pin is not supported." "0,1" newline rbitfld.word 0x0 10. "INT_B,INT_B (Embedded) This bit is set if INT_B is enabled and if INT_B# pin is in low level. The INT_B# pin is not supported." "0,1" newline rbitfld.word 0x0 9. "INT_A,INT_A (Embedded) This bit is set if INT_A is enabled and if INT_A# pin is in low level. The INT_A# pin is not supported." "0,1" newline rbitfld.word 0x0 8. "CARD_INTERRUPT,Card Interrupt This bit reflects the synchronized value of: - DAT[1] Interrupt Input for SD Mode - DAT[2] Interrupt Input for UHS-II Mode 0x0: No Card Interrupt 0x1: Generate Card Interrupt" "No Card Interrupt,Generate Card Interrupt" newline bitfld.word 0x0 7. "CARD_REMOVAL,Card Removal This bit is set if the Card Inserted in the Present State register changes from 1 to 0. 0x0: Card state stable or Debouncing 0x1: Card Removed" "Card state stable or Debouncing,Card Removed" newline bitfld.word 0x0 6. "CARD_INSERTION,Card Insertion This bit is set if the Card Inserted in the Present State register changes from 0 to 1. 0x0: Card state stable or Debouncing 0x1: Card Inserted" "Card state stable or Debouncing,Card Inserted" newline bitfld.word 0x0 5. "BUF_RD_READY,Buffer Read Ready This bit is set if the Buffer Read Enable changes from 0 to 1. 0x0: Not ready to read buffer 0x1: Ready to read buffer" "Not ready to read buffer,Ready to read buffer" newline bitfld.word 0x0 4. "BUF_WR_READY,Buffer Write Ready This bit is set if the Buffer Write Enable changes from 0 to 1. 0x0: Not ready to write buffer 0x1: Ready to write buffer" "Not ready to write buffer,Ready to write buffer" newline bitfld.word 0x0 3. "DMA_INTERRUPT,DMA Interrupt This bit is set if the Host Controller detects the SDMA Buffer Boundary during transfer. In case of ADMA by setting the Int field in the descriptor table the Host controller generates this interrupt. This interrupt is not.." "No DMA Interrupt,DMA Interrupt is generated" newline bitfld.word 0x0 2. "BGAP_EVENT,Block Gap Event This bit is set when both read/write transaction is stopped at block gap due to a Stop at Block Gap Request. 0x0: No Block Gap Event 0x1: Transaction stopped at block gap" "No Block Gap Event,Transaction stopped at block gap" newline bitfld.word 0x0 1. "XFER_COMPLETE,Transfer Complete This bit is set when a read/write transfer and a command with status busy is completed. 0x0: Not complete 0x1: Command execution is completed" "Not complete,Command execution is completed" newline bitfld.word 0x0 0. "CMD_COMPLETE,Command Complete In an SD/eMMC Mode this bit is set when the end bit of a response except for Auto CMD12 and Auto CMD23. This interrupt is not generated when the Response Interrupt Disable in Transfer Mode Register is set to 1. 0x0: No.." "No command complete,Command Complete" line.word 0x2 "ERROR_INT_STAT_R,This register enables an interrupt when the Error Interrupt Status Enable is enabled and at least one of the statuses is set to 1. Writing to 1 clears the bit and writing to 0 retains the bit unchanged. Signals defined in this register.." newline bitfld.word 0x2 15. "VENDOR_ERR3,This bit (VENDOR_ERR3) of the ERROR_INT_STAT_R register is reserved. It always returns 0." "0,1" newline bitfld.word 0x2 14. "VENDOR_ERR2,This bit (VENDOR_ERR2) of the ERROR_INT_STAT_R register is reserved. It always returns 0." "0,1" newline bitfld.word 0x2 13. "VENDOR_ERR1,This bit (VENDOR_ERR1) of the ERROR_INT_STAT_R register is reserved. It always returns 0." "0,1" newline bitfld.word 0x2 12. "BOOT_ACK_ERR,Boot Acknowledgement Error This bit is set when there is a timeout for boot acknowledgement or when detecting boot ack status having a value other than 010. This is applicable only when boot acknowledgement is expected in eMMC mode. 0x0: No.." "No error,Error" newline bitfld.word 0x2 11. "RESP_ERR,Response Error Host Controller Version 4.00 supports response error check function to avoid overhead of response error check by Host Driver during DMA execution. If Response Error Check Enable is set to 1 in the Transfer Mode register Host.." "No error,Error" newline bitfld.word 0x2 10. "TUNING_ERR,Tuning Error This bit is set when an unrecoverable error is detected in a tuning circuit except during the tuning procedure (occurrence of an error during tuning procedure is indicated by Sampling Clock Select in the Host Control 2 register)." "No error,Error" newline bitfld.word 0x2 9. "ADMA_ERR,ADMA Error This bit is set when the Host Controller detects error during ADMA-based data transfer. The error could be due to following reasons: - Error response received from System bus (Master I/F) - ADMA3 ADMA2 Descriptors invalid - CQE Task.." "No error,Error" newline bitfld.word 0x2 8. "AUTO_CMD_ERR,Auto CMD Error This error status is used by Auto CMD12 and Auto CMD23 in SD/eMMC mode. This bit is set when detecting that any of the bits D00 to D05 in Auto CMD Error Status register has changed from 0 to 1. D07 is effective in case of Auto.." "No error,Error" newline bitfld.word 0x2 7. "CUR_LMT_ERR,Current Limit Error By setting the SD Bus Power bit in the Power Control register the Host Controller is requested to supply power for the SD Bus. If the Host Controller supports the Current Limit function it can be protected from an.." "No error,Power Fail" newline bitfld.word 0x2 6. "DATA_END_BIT_ERR,Data End Bit Error This error occurs in SD/eMMC mode either when detecting 0 at the end bit position of read data that uses the DAT line or at the end bit position of the CRC status. 0x0: No error 0x1: Error" "No error,Error" newline bitfld.word 0x2 5. "DATA_CRC_ERR,Data CRC Error This error occurs in SD/eMMC mode when detecting CRC error when transferring read data which uses the DAT line when detecting the Write CRC status having a value of other than 010 or when write CRC status timeout. 0x0: No.." "No error,Error" newline bitfld.word 0x2 4. "DATA_TOUT_ERR,Data Timeout Error This bit is set in SD/eMMC mode when detecting one of the following timeout conditions: - Busy timeout for R1b R5b type - Busy timeout after Write CRC status - Write CRC Status timeout - Read Data timeout 0x0: No error.." "No error,Time out" newline bitfld.word 0x2 3. "CMD_IDX_ERR,Command Index Error This bit is set if a Command Index error occurs in the command respons in SD/eMMC mode. 0x0: No error 0x1: Error" "No error,Error" newline bitfld.word 0x2 2. "CMD_END_BIT_ERR,Command End Bit Error This bit is set when detecting that the end bit of a command response is 0 in SD/eMMC mode. 0x0: No error 0x1: End Bit error generated" "No error,End Bit error generated" newline bitfld.word 0x2 1. "CMD_CRC_ERR,Command CRC Error Command CRC Error is generated in SD/eMMC mode for following two cases. - If a response is returned and the Command Timeout Error is set to 0 (indicating no timeout) this bit is set to 1 when detecting a CRC error in the.." "No error,CRC error generated" newline bitfld.word 0x2 0. "CMD_TOUT_ERR,Command Timeout Error In SD/eMMC Mode this bit is set only if no response is returned within 64 SD clock cycles from the end bit of the command. If the Host Controller detects a CMD line conflict along with Command CRC Error bit this bit.." "No error,Time out" line.word 0x4 "NORMAL_INT_STAT_EN_R,This register enables the Interrupt Status for Normal Interrupt Status register (NORMAL_INT_STAT_R) when NORMAL_INT_STAT_R is set to 1. This register is applicable for an SD/eMMC/UHS-II mode." newline rbitfld.word 0x4 15. "RSVD_15,This bit of the NORMAL_INT_STAT_EN_R register is reserved. It always returns 0." "0,1" newline bitfld.word 0x4 14. "CQE_EVENT_STAT_EN,CQE Event Status Enable 0x0: Masked 0x1: Enabled" "Masked,Enabled" newline bitfld.word 0x4 13. "FX_EVENT_STAT_EN,FX Event Status Enable This bit is added from Version 4.10. 0x0: Masked 0x1: Enabled" "Masked,Enabled" newline bitfld.word 0x4 12. "RE_TUNE_EVENT_STAT_EN,Re-Tuning Event (UHS-I only) Status Enable 0x0: Masked 0x1: Enabled" "Masked,Enabled" newline bitfld.word 0x4 11. "INT_C_STAT_EN,INT_C (Embedded) Status Enable If this bit is set to 0 the Host Controller clears the interrupt request to the System. The Host Driver may clear this bit before servicing the INT_C and may set this bit again after all interrupt requests to.." "Masked,Enabled" newline bitfld.word 0x4 10. "INT_B_STAT_EN,INT_B (Embedded) Status Enable If this bit is set to 0 the Host Controller clears the interrupt request to the System. The Host Driver may clear this bit before servicing the INT_B and may set this bit again after all interrupt requests to.." "Masked,Enabled" newline bitfld.word 0x4 9. "INT_A_STAT_EN,INT_A (Embedded) Status Enable If this bit is set to 0 the Host Controller clears the interrupt request to the System. The Host Driver may clear this bit before servicing the INT_A and may set this bit again after all interrupt requests to.." "Masked,Enabled" newline bitfld.word 0x4 8. "CARD_INTERRUPT_STAT_EN,Card Interrupt Status Enable If this bit is set to 0 the Host Controller clears the interrupt request to the System. The Card Interrupt detection is stopped when this bit is cleared and restarted when this bit is set to 1. The.." "Masked,Enabled" newline bitfld.word 0x4 7. "CARD_REMOVAL_STAT_EN,Card Removal Status Enable 0x0: Masked 0x1: Enabled" "Masked,Enabled" newline bitfld.word 0x4 6. "CARD_INSERTION_STAT_EN,Card Insertion Status Enable 0x0: Masked 0x1: Enabled" "Masked,Enabled" newline bitfld.word 0x4 5. "BUF_RD_READY_STAT_EN,Buffer Read Ready Status Enable 0x0: Masked 0x1: Enabled" "Masked,Enabled" newline bitfld.word 0x4 4. "BUF_WR_READY_STAT_EN,Buffer Write Ready Status Enable 0x0: Masked 0x1: Enabled" "Masked,Enabled" newline bitfld.word 0x4 3. "DMA_INTERRUPT_STAT_EN,DMA Interrupt Status Enable 0x0: Masked 0x1: Enabled" "Masked,Enabled" newline bitfld.word 0x4 2. "BGAP_EVENT_STAT_EN,Block Gap Event Status Enable 0x0: Masked 0x1: Enabled" "Masked,Enabled" newline bitfld.word 0x4 1. "XFER_COMPLETE_STAT_EN,Transfer Complete Status Enable 0x0: Masked 0x1: Enabled" "Masked,Enabled" newline bitfld.word 0x4 0. "CMD_COMPLETE_STAT_EN,Command Complete Status Enable 0x0: Masked 0x1: Enabled" "Masked,Enabled" line.word 0x6 "ERROR_INT_STAT_EN_R,This register sets the Interrupt Status for Error Interrupt Status register (ERROR_INT_STAT_R). when ERROR_INT_STAT_EN_R is set to 1. This register is applicable for an SD/eMMC/UHS-II mode." newline bitfld.word 0x6 15. "VENDOR_ERR_STAT_EN3,The 15th bit of Error Interrupt Status Enable register is reserved. 0x0: Masked 0x1: Enabled" "Masked,Enabled" newline bitfld.word 0x6 14. "VENDOR_ERR_STAT_EN2,The 14th bit of Error Interrupt Status Enable register is reserved. 0x0: Masked 0x1: Enabled" "Masked,Enabled" newline bitfld.word 0x6 13. "VENDOR_ERR_STAT_EN1,The 13th bit of Error Interrupt Status Enable register is reserved. 0x0: Masked 0x1: Enabled" "Masked,Enabled" newline bitfld.word 0x6 12. "BOOT_ACK_ERR_STAT_EN,Boot Acknowledgment Error (eMMC Mode only) Setting this bit to 1 enables setting of Boot Acknowledgment Error in Error Interrupt Status register (ERROR_INT_STAT_R). 0x0: Masked 0x1: Enabled" "Masked,Enabled" newline bitfld.word 0x6 11. "RESP_ERR_STAT_EN,Response Error Status Enable (SD Mode only) 0x0: Masked 0x1: Enabled" "Masked,Enabled" newline bitfld.word 0x6 10. "TUNING_ERR_STAT_EN,Tuning Error Status Enable (UHS-I Mode only) 0x0: Masked 0x1: Enabled" "Masked,Enabled" newline bitfld.word 0x6 9. "ADMA_ERR_STAT_EN,ADMA Error Status Enable 0x0: Masked 0x1: Enabled" "Masked,Enabled" newline bitfld.word 0x6 8. "AUTO_CMD_ERR_STAT_EN,Auto CMD Error Status Enable (SD/eMMC Mode only). 0x0: Masked 0x1: Enabled" "Masked,Enabled" newline bitfld.word 0x6 7. "CUR_LMT_ERR_STAT_EN,Current Limit Error Status Enable 0x0: Masked 0x1: Enabled" "Masked,Enabled" newline bitfld.word 0x6 6. "DATA_END_BIT_ERR_STAT_EN,Data End Bit Error Status Enable (SD/eMMC Mode only). 0x0: Masked 0x1: Enabled" "Masked,Enabled" newline bitfld.word 0x6 5. "DATA_CRC_ERR_STAT_EN,Data CRC Error Status Enable (SD/eMMC Mode only) 0x0: Masked 0x1: Enabled" "Masked,Enabled" newline bitfld.word 0x6 4. "DATA_TOUT_ERR_STAT_EN,Data Timeout Error Status Enable (SD/eMMC Mode only) 0x0: Masked 0x1: Enabled" "Masked,Enabled" newline bitfld.word 0x6 3. "CMD_IDX_ERR_STAT_EN,Command Index Error Status Enable (SD/eMMC Mode only) 0x0: Masked 0x1: Enabled" "Masked,Enabled" newline bitfld.word 0x6 2. "CMD_END_BIT_ERR_STAT_EN,Command End Bit Error Status Enable (SD/eMMC Mode only) 0x0: Masked 0x1: Enabled" "Masked,Enabled" newline bitfld.word 0x6 1. "CMD_CRC_ERR_STAT_EN,Command CRC Error Status Enable (SD/eMMC Mode only) 0x0: Masked 0x1: Enabled" "Masked,Enabled" newline bitfld.word 0x6 0. "CMD_TOUT_ERR_STAT_EN,Command Timeout Error Status Enable (SD/eMMC Mode only). 0x0: Masked 0x1: Enabled" "Masked,Enabled" line.word 0x8 "NORMAL_INT_SIGNAL_EN_R,This register is used to select the interrupt status that is indicated to the Host System as the interrupt. All these status bits share the same 1-bit interrupt line. Setting any of these bits to 1. enables interrupt generation." newline rbitfld.word 0x8 15. "RSVD_15,This bit of the NORMAL_INT_STAT_R register is reserved. It always returns 0." "0,1" newline bitfld.word 0x8 14. "CQE_EVENT_SIGNAL_EN,Command Queuing Engine Event Signal Enable 0x0: Masked 0x1: Enabled" "Masked,Enabled" newline bitfld.word 0x8 13. "FX_EVENT_SIGNAL_EN,FX Event Signal Enable 0x0: Masked 0x1: Enabled" "Masked,Enabled" newline bitfld.word 0x8 12. "RE_TUNE_EVENT_SIGNAL_EN,Re-Tuning Event (UHS-I only) Signal Enable. 0x0: Masked 0x1: Enabled" "Masked,Enabled" newline bitfld.word 0x8 11. "INT_C_SIGNAL_EN,INT_C (Embedded) Signal Enable 0x0: Masked 0x1: Enabled" "Masked,Enabled" newline bitfld.word 0x8 10. "INT_B_SIGNAL_EN,INT_B (Embedded) Signal Enable 0x0: Masked 0x1: Enabled" "Masked,Enabled" newline bitfld.word 0x8 9. "INT_A_SIGNAL_EN,INT_A (Embedded) Signal Enable 0x0: Masked 0x1: Enabled" "Masked,Enabled" newline bitfld.word 0x8 8. "CARD_INTERRUPT_SIGNAL_EN,Card Interrupt Signal Enable 0x0: Masked 0x1: Enabled" "Masked,Enabled" newline bitfld.word 0x8 7. "CARD_REMOVAL_SIGNAL_EN,Card Removal Signal Enable 0x0: Masked 0x1: Enabled" "Masked,Enabled" newline bitfld.word 0x8 6. "CARD_INSERTION_SIGNAL_EN,Card Insertion Signal Enable 0x0: Masked 0x1: Enabled" "Masked,Enabled" newline bitfld.word 0x8 5. "BUF_RD_READY_SIGNAL_EN,Buffer Read Ready Signal Enable 0x0: Masked 0x1: Enabled" "Masked,Enabled" newline bitfld.word 0x8 4. "BUF_WR_READY_SIGNAL_EN,Buffer Write Ready Signal Enable 0x0: Masked 0x1: Enabled" "Masked,Enabled" newline bitfld.word 0x8 3. "DMA_INTERRUPT_SIGNAL_EN,DMA Interrupt Signal Enable 0x0: Masked 0x1: Enabled" "Masked,Enabled" newline bitfld.word 0x8 2. "BGAP_EVENT_SIGNAL_EN,Block Gap Event Signal Enable 0x0: Masked 0x1: Enabled" "Masked,Enabled" newline bitfld.word 0x8 1. "XFER_COMPLETE_SIGNAL_EN,Transfer Complete Signal Enable 0x0: Masked 0x1: Enabled" "Masked,Enabled" newline bitfld.word 0x8 0. "CMD_COMPLETE_SIGNAL_EN,Command Complete Signal Enable 0x0: Masked 0x1: Enabled" "Masked,Enabled" line.word 0xA "ERROR_INT_SIGNAL_EN_R,This register is used to select the interrupt status that is notified to the Host System as an interrupt. All these status bits share the same 1-bit interrupt line. Setting any of these bits to 1 enables interrupt generation. This.." newline bitfld.word 0xA 15. "VENDOR_ERR_SIGNAL_EN3,The 16th bit of Error Interrupt Signal Enable is reserved. 0x0: Masked 0x1: Enabled" "Masked,Enabled" newline bitfld.word 0xA 14. "VENDOR_ERR_SIGNAL_EN2,The 15th bit of Error Interrupt Signal Enable is reserved. 0x0: Masked 0x1: Enabled" "Masked,Enabled" newline bitfld.word 0xA 13. "VENDOR_ERR_SIGNAL_EN1,The 14th bit of Error Interrupt Signal Enable is reserved. 0x0: Masked 0x1: Enabled" "Masked,Enabled" newline bitfld.word 0xA 12. "BOOT_ACK_ERR_SIGNAL_EN,Boot Acknowledgment Error (eMMC Mode only). Setting this bit to 1 enables generating interrupt signal when Boot Acknowledgement Error in Error Interrupt Status register is set. 0x0: Masked 0x1: Enabled" "Masked,Enabled" newline bitfld.word 0xA 11. "RESP_ERR_SIGNAL_EN,Response Error Signal Enable (SD Mode only) 0x0: Masked 0x1: Enabled" "Masked,Enabled" newline bitfld.word 0xA 10. "TUNING_ERR_SIGNAL_EN,Tuning Error Signal Enable (UHS-I Mode only) 0x0: Masked 0x1: Enabled" "Masked,Enabled" newline bitfld.word 0xA 9. "ADMA_ERR_SIGNAL_EN,ADMA Error Signal Enable 0x0: Masked 0x1: Enabled" "Masked,Enabled" newline bitfld.word 0xA 8. "AUTO_CMD_ERR_SIGNAL_EN,Auto CMD Error Signal Enable (SD/eMMC Mode only) 0x0: Masked 0x1: Enabled" "Masked,Enabled" newline bitfld.word 0xA 7. "CUR_LMT_ERR_SIGNAL_EN,Current Limit Error Signal Enable 0x0: Masked 0x1: Enabled" "Masked,Enabled" newline bitfld.word 0xA 6. "DATA_END_BIT_ERR_SIGNAL_EN,Data End Bit Error Signal Enable (SD/eMMC Mode only) 0x0: Masked 0x1: Enabled" "Masked,Enabled" newline bitfld.word 0xA 5. "DATA_CRC_ERR_SIGNAL_EN,Data CRC Error Signal Enable (SD/eMMC Mode only) 0x0: Masked 0x1: Enabled" "Masked,Enabled" newline bitfld.word 0xA 4. "DATA_TOUT_ERR_SIGNAL_EN,Data Timeout Error Signal Enable (SD/eMMC Mode only) 0x0: Masked 0x1: Enabled" "Masked,Enabled" newline bitfld.word 0xA 3. "CMD_IDX_ERR_SIGNAL_EN,Command Index Error Signal Enable (SD/eMMC Mode only) 0x0: No error 0x1: Error" "No error,Error" newline bitfld.word 0xA 2. "CMD_END_BIT_ERR_SIGNAL_EN,Command End Bit Error Signal Enable (SD/eMMC Mode only) 0x0: Masked 0x1: Enabled" "Masked,Enabled" newline bitfld.word 0xA 1. "CMD_CRC_ERR_SIGNAL_EN,Command CRC Error Signal Enable (SD/eMMC Mode only) 0x0: Masked 0x1: Enabled" "Masked,Enabled" newline bitfld.word 0xA 0. "CMD_TOUT_ERR_SIGNAL_EN,Command Timeout Error Signal Enable (SD/eMMC Mode only) 0x0: Masked 0x1: Enabled" "Masked,Enabled" rgroup.word 0x3C++0x1 line.word 0x0 "AUTO_CMD_STAT_R,This register is used to indicate the CMD12 response error of Auto CMD12. and the CMD23 response error of Auto CMD23. The Host driver can determine the kind of Auto CMD12/CMD23 errors that can occur in this register. Auto CMD23 errors are.." newline hexmask.word.byte 0x0 8.--15. 1. "RSVD_15_8,These bits of the AUTO_CMD_STAT_R register are reserved bits. They always return 0." newline bitfld.word 0x0 7. "CMD_NOT_ISSUED_AUTO_CMD12,Command Not Issued By Auto CMD12 Error If this bit is set to 1 CMD_wo_DAT is not executed due to an Auto CMD12 Error (D04-D01) in this register. This bit is set to 0 when Auto CMD Error is generated by Auto CMD23. 0x0: No Error.." "No Error,Not Issued" newline bitfld.word 0x0 6. "RSVD_6,This bit of the AUTO_CMD_STAR_R register is reserved. It always returns 0." "0,1" newline bitfld.word 0x0 5. "AUTO_CMD_RESP_ERR,Auto CMD Response Error This bit is set when Response Error Check Enable in the Transfer Mode register is set to 1 and an error is detected in R1 response of either Auto CMD12 or CMD13. This status is ignored if any bit between D00 to.." "No Error,Error" newline bitfld.word 0x0 4. "AUTO_CMD_IDX_ERR,Auto CMD Index Error This bit is set if the command index error occurs in response to a command. 0x0: No Error 0x1: Error" "No Error,Error" newline bitfld.word 0x0 3. "AUTO_CMD_EBIT_ERR,Auto CMD End Bit Error This bit is set when detecting that the end bit of command response is 0. 0x0: No Error 0x1: End Bit Error Generated" "No Error,End Bit Error Generated" newline bitfld.word 0x0 2. "AUTO_CMD_CRC_ERR,Auto CMD CRC Error This bit is set when detecting a CRC error in the command response. 0x0: No Error 0x1: CRC Error Generated" "No Error,CRC Error Generated" newline bitfld.word 0x0 1. "AUTO_CMD_TOUT_ERR,Auto CMD Timeout Error This bit is set if no response is returned with 64 SDCLK cycles from the end bit of the command. If this bit is set to 1 error status bits (D04-D01) are meaningless. 0x0: No Error 0x1: Time out" "No Error,Time out" newline bitfld.word 0x0 0. "AUTO_CMD12_NOT_EXEC,Auto CMD12 Not Executed If multiple memory block data transfer is not started due to a command error this bit is not set because it is not necessary to issue an Auto CMD12. Setting this bit to 1 means that the Host Controller cannot.." "Executed,Not Executed" group.word 0x3E++0x1 line.word 0x0 "HOST_CTRL2_R,This register is used to control how the Host Controller operates. This register is applicable for an SD/eMMC/UHS-II mode." newline bitfld.word 0x0 15. "PRESET_VAL_ENABLE,Preset Value Enable This bit enables automatic selection of SDCLK frequency and Driver strength Preset Value registers. When Preset Value Enable is set SDCLK frequency generation (Frequency Select and Clock Generator Select) and the.." "SDCLK and Driver Strength are controlled by Host..,Automatic Selection by Preset Value are Enabled" newline bitfld.word 0x0 14. "ASYNC_INT_ENABLE,Asynchronous Interrupt Enable This bit can be set if a card supports asynchronous interrupts and Asynchronous Interrupt Support is set to 1 in the Capabilities register. 0x0: Disabled 0x1: Enabled" "Disabled,Enabled" newline bitfld.word 0x0 13. "ADDRESSING,64-bit Addressing This bit is effective when Host Version 4 Enable is set to 1. 0x0: 32 bits addressing 0x1: 64 bits addressing" "0,1" newline bitfld.word 0x0 12. "HOST_VER4_ENABLE,Host Version 4 Enable This bit selects either Version 3.00 compatible mode or Version 4 mode. Functions of following fields are modified for Host Version 4 mode: - SDMA Address: SDMA uses ADMA System Address (05Fh-058h) instead of SDMA.." "Version 3,Version 4 mode" newline bitfld.word 0x0 11. "CMD23_ENABLE,CMD23 Enable If the card supports CMD23 this bit is set to 1. This bit is used to select Auto CMD23 or Auto CMD12 for ADMA3 data transfer. 0x0: Auto CMD23 is disabled 0x1: Auto CMD23 is enabled" "Auto CMD23 is disabled,Auto CMD23 is enabled" newline bitfld.word 0x0 10. "ADMA2_LEN_MODE,ADMA2 Length Mode This bit selects ADMA2 Length mode to be either 16-bit or 26-bit. 0x0: 16-bit Data Length Mode 0x1: 26-bit Data Length Mode" "0,1" newline rbitfld.word 0x0 9. "RSVD_9,This bit of the HOST_CTRL2_R register is reserved. It always returns 0." "0,1" newline bitfld.word 0x0 8. "UHS2_IF_ENABLE,UHS-II Interface Enable This bit is used to enable the UHS-II Interface. The value is reflected on the uhs2_if_en pin. 0x0: SD/eMMC Interface Enabled 0x1: UHS-II Interface Enabled" "SD/eMMC Interface Enabled,UHS-II Interface Enabled" newline bitfld.word 0x0 7. "SAMPLE_CLK_SEL,Sampling Clock Select This bit is used by the Host Controller to select the sampling clock in SD/eMMC mode to receive CMD and DAT. This bit is set by the tuning procedure and is valid after the completion of tuning (when Execute Tuning is.." "Fixed clock is used to sample data,Tuned clock is used to sample data" newline bitfld.word 0x0 6. "EXEC_TUNING,Execute Tuning This bit is set to 1 to start the tuning procedure in UHS-I/eMMC speed modes and this bit is automatically cleared when tuning procedure is completed. 0x0: Not Tuned or Tuning completed 0x1: Execute Tuning" "Not Tuned or Tuning completed,Execute Tuning" newline bitfld.word 0x0 4.--5. "DRV_STRENGTH_SEL,Driver Strength Select This bit is used to select the Host Controller output driver in 1.8V signaling UHS-I/eMMC speed modes. The bit depends on setting of Preset Value Enable. The value is reflected on the uhs1_drv_sth pin. 0x1: Driver.." "Driver TYPEB is selected,Driver TYPEA is selected,Driver TYPEC is selected,Driver TYPED is selected" newline bitfld.word 0x0 3. "SIGNALING_EN,1.8V Signaling Enable This bit controls voltage regulator for I/O cell in UHS-I/eMMC speed modes. Setting this bit from 0 to 1 starts changing the signal voltage from 3.3V to 1.8V. Host Controller clears this bit if switching to 1.8.." "0,1" newline bitfld.word 0x0 0.--2. "UHS_MODE_SEL,UHS Mode/eMMC Speed Mode Select These bits are used to select UHS mode in the SD mode of operation. In eMMC mode these bits are used to select eMMC Speed mode. UHS Mode (SD/UHS-II mode only): - 0x0: SDR12 - 0x1: SDR25 - 0x2: SDR50 - 0x3:.." "SDR12/Legacy,SDR25/High Speed SDR,SDR50,SDR104/HS200,DDR50/High Speed DDR,Reserved,Reserved,UHS-II/HS400" rgroup.long 0x40++0xF line.long 0x0 "CAPABILITIES1_R,This register provides the Host Driver with information specific to the Host Controller implementation. The host controller may implement these values as fixed or loaded from the flash memory during power on initialization. Capabilities.." bitfld.long 0x0 30.--31. "SLOT_TYPE_R,Slot Type These bits indicate usage of a slot by a specific Host System. 0x1: Embedded Slot for one Device 0x0: Removable Card Slot 0x2: Shared Bus Slot (SD mode) 0x3: UHS-II Multiple Embedded Devices" "Removable Card Slot,Embedded Slot for one Device,Shared Bus Slot,UHS-II Multiple Embedded Devices" newline bitfld.long 0x0 29. "ASYNC_INT_SUPPORT,Asynchronous Interrupt Support (SD Mode only) 0x0: Asynchronous Interrupt Not Supported 0x1: Asynchronous Interrupt Supported" "Asynchronous Interrupt Not Supported,Asynchronous Interrupt Supported" newline bitfld.long 0x0 28. "SYS_ADDR_64_V3,64-bit System Address Support for V3 This bit sets the Host controller to support 64-bit System Addressing of V3 mode. SDMA cannot be used in 64-bit Addressing in Version 3 Mode. If this bit is set to 1 64-bit ADMA2 with using 96-bit.." "0,1" newline bitfld.long 0x0 27. "SYS_ADDR_64_V4,64-bit System Address Support for V4 This bit sets the Host Controller to support 64-bit System Addressing of V4 mode. When this bit is set to 1 full or part of 64-bit address must be used to decode the Host Controller Registers so that.." "0,1" newline bitfld.long 0x0 26. "VOLT_18,Voltage Support for 1.8V 0x0: 1.8V Not Supported 0x1: 1.8V Supported" "0,1" newline bitfld.long 0x0 25. "VOLT_30,Voltage Support for SD 3.0V or Embedded 1.2V 0x0: SD 3.0V or Embedded 1.2V Not Supported 0x1: SD 3.0V or Embedded Supported" "SD 3,SD 3" newline bitfld.long 0x0 24. "VOLT_33,Voltage Support for 3.3V 0x0: 3.3V Not Supported 0x1: 3.3V Supported" "0,1" newline bitfld.long 0x0 23. "SUS_RES_SUPPORT,Suspense/Resume Support This bit indicates whether the Host Controller supports Suspend/Resume functionality. If this bit is 0 the Host Driver does not issue either Suspend or Resume commands because the Suspend and Resume mechanism is.." "Not Supported,Supported" newline bitfld.long 0x0 22. "SDMA_SUPPORT,SDMA Support This bit indicates whether the Host Controller is capable of using SDMA to transfer data between the system memory and the Host Controller directly. 0x0: SDMA not Supported 0x1: SDMA Supported" "SDMA not Supported,SDMA Supported" newline bitfld.long 0x0 21. "HIGH_SPEED_SUPPORT,High Speed Support This bit indicates whether the Host Controller and the Host System supports High Speed mode and they can supply the SD Clock frequency from 25 MHz to 50 MHz. 0x0: High Speed not Supported 0x1: High Speed Supported" "High Speed not Supported,High Speed Supported" newline bitfld.long 0x0 20. "RSVD_20,This bit of the CAPABILITIES1_R is a reserved. It always returns 0." "0,1" newline bitfld.long 0x0 19. "ADMA2_SUPPORT,ADMA2 Support This bit indicates whether the Host Controller is capable of using ADMA2. 0x0: ADMA2 not Supported 0x1: ADMA2 Supported" "ADMA2 not Supported,ADMA2 Supported" newline bitfld.long 0x0 18. "EMBEDDED_8_BIT,8-bit Support for Embedded Device This bit indicates whether the Host Controller is capable of using an 8-bit bus width mode. This bit is not effective when the Slot Type is set to 10b. 0x0: 8-bit Bus Width not Supported 0x1: 8-bit Bus.." "0,1" newline bitfld.long 0x0 16.--17. "MAX_BLK_LEN,Maximum Block Length This bit indicates the maximum block size that the Host driver can read and write to the buffer in the Host Controller. The buffer transfers this block size without wait cycles. The transfer block length is always 512.." "?,?,?,Reserved" newline hexmask.long.byte 0x0 8.--15. 1. "BASE_CLK_FREQ,Base Clock Frequency for SD clock These bits indicate the base (maximum) clock frequency for the SD Clock. The definition of these bits depend on the Host Controller Version. - 6-Bit Base Clock Frequency: This mode is supported by the Host.." newline bitfld.long 0x0 7. "TOUT_CLK_UNIT,Timeout Clock Unit This bit shows the unit of base clock frequency used to detect Data TImeout Error. 0x0: KHz 0x1: MHz" "KHz,MHz" newline bitfld.long 0x0 6. "RSVD_6,This bit of the CAPABILITIES1_R register is reserved. It always returns 0." "0,1" newline hexmask.long.byte 0x0 0.--5. 1. "TOUT_CLK_FREQ,Timeout Clock Frequency This bit shows the base clock frequency used to detect Data Timeout Error. The Timeout Clock unit defines the unit of timeout clock frequency. It can be KHz or MHz. - 0x00 - Get information through another method -.." line.long 0x4 "CAPABILITIES2_R,This register provides the Host Driver with information specific to the Host Controller implementation. The host controller may implement these values as fixed or as loaded from flash memory during power on initialization. Capabilities.." bitfld.long 0x4 30.--31. "RSVD_62_63,These bits (RSVD_62_63) of the CAPABILITIES2_R register are reserved bits. They always return 0." "0,1,2,3" newline bitfld.long 0x4 29. "RSVD_61,This bit (RSVD_61) of the CAPABILITIES2_R register is reserved. It always returns 0." "0,1" newline bitfld.long 0x4 28. "VDD2_18V_SUPPORT,1.8V VDD2 Support This bit indicates support of VDD2 for the Host System. 0x0: 1.8V VDD2 is not Supported 0x1: 1.8V VDD2 is Supported" "0,1" newline bitfld.long 0x4 27. "ADMA3_SUPPORT,ADMA3 Support This bit indicates whether the Host Controller is capable of using ADMA3. 0x0: ADMA3 not Supported 0x1: ADMA3 Supported" "ADMA3 not Supported,ADMA3 Supported" newline bitfld.long 0x4 24.--26. "RSVD_56_58,These bits (RSVD_56_58) of the CAPABILITIES2_R register are reserved. They always return 0." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x4 16.--23. 1. "CLK_MUL,Clock Multiplier These bits indicate the clock multiplier of the programmable clock generator. Setting these bits to 0 means that the Host Controller does not support a programmable clock generator. - 0x0: Clock Multiplier is not Supported - 0x1:.." newline bitfld.long 0x4 14.--15. "RE_TUNING_MODES,Re-Tuning Modes (UHS-I only) These bits select the re-tuning method and limit the maximum data length. 0x0: Timer 0x1: Timer and Re-Tuning Request (Not supported) 0x2: Auto Re-Tuning (for transfer) 0x3: Reserved" "Timer,Timer and Re-Tuning Request,Auto Re-Tuning,Reserved" newline bitfld.long 0x4 13. "USE_TUNING_SDR50,Use Tuning for SDR50 (UHS-I only) 0x1: SDR50 requires tuning 0x0: SDR50 does not require tuning" "SDR50 does not require tuning,SDR50 requires tuning" newline bitfld.long 0x4 12. "RSVD_44,This bit (RSVD_44) of the CAPABILITIES2_R register is reserved. It always returns 0." "0,1" newline hexmask.long.byte 0x4 8.--11. 1. "RETUNE_CNT,Timer Count for Re-Tuning (UHS-I only) - 0x0: Re-Tuning Timer disabled - 0x1: 1 seconds - 0x2: 2 seconds - 0x3: 4 seconds - ........ - 0xB: 1024 seconds - 0xC: Reserved - 0xD: Reserved - 0xE: Reserved - 0xF: Get information from other source" newline bitfld.long 0x4 7. "RSVD_39,This bit (RSVD_39) of the CAPABILITIES2_R register is reserved. It always returns 0." "0,1" newline bitfld.long 0x4 6. "DRV_TYPED,Driver Type D Support (UHS-I only) This bit indicates support of Driver Type D for 1.8 Signaling. 0x0: Driver Type D is not supported 0x1: Driver Type D is supported" "Driver Type D is not supported,Driver Type D is supported" newline bitfld.long 0x4 5. "DRV_TYPEC,Driver Type C Support (UHS-I only) This bit indicates support of Driver Type C for 1.8 Signaling. 0x0: Driver Type C is not supported 0x1: Driver Type C is supported" "Driver Type C is not supported,Driver Type C is supported" newline bitfld.long 0x4 4. "DRV_TYPEA,Driver Type A Support (UHS-I only) This bit indicates support of Driver Type A for 1.8 Signaling. 0x0: Driver Type A is not supported 0x1: Driver Type A is supported" "Driver Type A is not supported,Driver Type A is supported" newline bitfld.long 0x4 3. "UHS2_SUPPORT,UHS-II Support (UHS-II only) This bit indicates whether Host Controller supports UHS-II. 0x0: UHS-II is not supported 0x1: UHS-II is supported" "UHS-II is not supported,UHS-II is supported" newline bitfld.long 0x4 2. "DDR50_SUPPORT,DDR50 Support (UHS-I only) 0x0: DDR50 is not supported 0x1: DDR50 is supported" "DDR50 is not supported,DDR50 is supported" newline bitfld.long 0x4 1. "SDR104_SUPPORT,SDR104 Support (UHS-I only) This bit mentions that SDR104 requires tuning. 0x0: SDR104 is not supported 0x1: SDR104 is supported" "SDR104 is not supported,SDR104 is supported" newline bitfld.long 0x4 0. "SDR50_SUPPORT,SDR50 Support (UHS-I only) Thsi bit indicates that SDR50 is supported. The bit 13 (USE_TUNING_SDR50) indicates whether SDR50 requires tuning or not. 0x0: SDR50 is not supported 0x1: SDR50 is supported" "SDR50 is not supported,SDR50 is supported" line.long 0x8 "CURR_CAPABILITIES1_R,This register indicate the maximum current capability for each voltage. for VDD1. The value is meaningful if the Voltage Support is set in the Capabilities register. If this information is supplied by the Host System through another.." hexmask.long.byte 0x8 24.--31. 1. "RSVD_31_24,These bits of the CURR_CAPABILITIES1_R register are reserved. They always return 0." newline hexmask.long.byte 0x8 16.--23. 1. "MAX_CUR_18V,Maximum Current for 1.8V This bit specifies the Maximum Current for 1.8V VDD1 power supply for the card. - 0: Get information through another method - 1: 4mA - 2: 8mA - 3: 13mA - ....... - 255: 1020mA" newline hexmask.long.byte 0x8 8.--15. 1. "MAX_CUR_30V,Maximum Current for 3.0V This bit specifies the Maximum Current for 3.0V VDD1 power supply for the card. - 0: Get information through another method - 1: 4mA - 2: 8mA - 3: 13mA - ....... - 255: 1020mA" newline hexmask.long.byte 0x8 0.--7. 1. "MAX_CUR_33V,Maximum Current for 3.3V This bit specifies the Maximum Current for 3.3V VDD1 power supply for the card. - 0: Get information through another method - 1: 4mA - 2: 8mA - 3: 13mA - ....... - 255: 1020mA" line.long 0xC "CURR_CAPABILITIES2_R,This register indicates the maximum current capability for each voltage (for VDD2). The value is meaningful if Voltage Support is set in the Capabilities register. If this information is supplied by the Host System through another.." hexmask.long.tbyte 0xC 8.--31. 1. "RSVD_63_40,These bits of the CURR_CAPABILITIES2_R register are reserved. They always return 0." newline hexmask.long.byte 0xC 0.--7. 1. "MAX_CUR_VDD2_18V,Maximum Current for 1.8V VDD2 This bit specifies the Maximum Current for 1.8V VDD2 power supply for the UHS-II card. - 0: Get information through another method - 1: 4mA - 2: 8mA - 3: 13mA - ....... - 255: 1020mA" group.word 0x50++0x3 line.word 0x0 "FORCE_AUTO_CMD_STAT_R,The register is not a physically implemented but is an address at which the Auto CMD Error Status register can be written.This register is applicable for an SD/eMMC mode. - 1 : Sets each bit of the Auto CMD Error Status register - 0.." newline hexmask.word.byte 0x0 8.--15. 1. "RSVD_15_8,These bits of the FORCE_AUTO_CMD_STAT_R register are reserved. They always return 0." newline bitfld.word 0x0 7. "FORCE_CMD_NOT_ISSUED_AUTO_CMD12,Force Event for Command Not Issued By Auto CMD12 Error 0x0: Not Affected 0x1: Command Not Issued By Auto CMD12 Error Status is set" "Not Affected,Command Not Issued By Auto CMD12 Error Status is.." newline rbitfld.word 0x0 6. "RSVD_6,This bit of the FORCE_AUTO_CMD_STAT_R register are reserved. They always return 0." "0,1" newline bitfld.word 0x0 5. "FORCE_AUTO_CMD_RESP_ERR,Force Event for Auto CMD Response Error 0x0: Not Affected 0x1: Auto CMD Response Error Status is set" "Not Affected,Auto CMD Response Error Status is set" newline bitfld.word 0x0 4. "FORCE_AUTO_CMD_IDX_ERR,Force Event for Auto CMD Index Error 0x0: Not Affected 0x1: Auto CMD Index Error Status is set" "Not Affected,Auto CMD Index Error Status is set" newline bitfld.word 0x0 3. "FORCE_AUTO_CMD_EBIT_ERR,Force Event for Auto CMD End Bit Error 0x0: Not Affected 0x1: Auto CMD End Bit Error Status is set" "Not Affected,Auto CMD End Bit Error Status is set" newline bitfld.word 0x0 2. "FORCE_AUTO_CMD_CRC_ERR,Force Event for Auto CMD CRC Error 0x0: Not Affected 0x1: Auto CMD CRC Error Status is set" "Not Affected,Auto CMD CRC Error Status is set" newline bitfld.word 0x0 1. "FORCE_AUTO_CMD_TOUT_ERR,Force Event for Auto CMD Timeout Error 0x0: Not Affected 0x1: Auto CMD Timeout Error Status is set" "Not Affected,Auto CMD Timeout Error Status is set" newline bitfld.word 0x0 0. "FORCE_AUTO_CMD12_NOT_EXEC,Force Event for Auto CMD12 Not Executed 0x0: Not Affected 0x1: Auto CMD12 Not Executed Status is set" "Not Affected,Auto CMD12 Not Executed Status is set" line.word 0x2 "FORCE_ERROR_INT_STAT_R,This register is not physically implemented but is an address at which the Error Interrupt Status register can be written. The effect of a write to this address is reflected in the Error Interrupt Status register if the.." newline bitfld.word 0x2 15. "FORCE_VENDOR_ERR3,This bit (FORCE_VENDOR_ERR3) of the FORCE_ERROR_INT_STAT_R register is reserved. It always returns 0." "0,1" newline bitfld.word 0x2 14. "FORCE_VENDOR_ERR2,This bit (FORCE_VENDOR_ERR2) of the FORCE_ERROR_INT_STAT_R register is reserved. It always returns 0." "0,1" newline bitfld.word 0x2 13. "FORCE_VENDOR_ERR1,This bit (FORCE_VENDOR_ERR1) of the FORCE_ERROR_INT_STAT_R register is reserved. It always returns 0." "0,1" newline bitfld.word 0x2 12. "FORCE_BOOT_ACK_ERR,Force Event for Boot Ack error 0x0: Not Affected 0x1: Boot ack Error Status is set" "Not Affected,Boot ack Error Status is set" newline bitfld.word 0x2 11. "FORCE_RESP_ERR,Force Event for Response Error (SD Mode only) 0x0: Not Affected 0x1: Response Error Status is set" "Not Affected,Response Error Status is set" newline bitfld.word 0x2 10. "FORCE_TUNING_ERR,Force Event for Tuning Error (UHS-I Mode only) 0x0: Not Affected 0x1: Tuning Error Status is set" "Not Affected,Tuning Error Status is set" newline bitfld.word 0x2 9. "FORCE_ADMA_ERR,Force Event for ADMA Error 0x0: Not Affected 0x1: ADMA Error Status is set" "Not Affected,ADMA Error Status is set" newline bitfld.word 0x2 8. "FORCE_AUTO_CMD_ERR,Force Event for Auto CMD Error (SD/eMMC Mode only) 0x0: Not Affected 0x1: Auto CMD Error Status is set" "Not Affected,Auto CMD Error Status is set" newline bitfld.word 0x2 7. "FORCE_CUR_LMT_ERR,Force Event for Current Limit Error 0x0: Not Affected 0x1: Current Limit Error Status is set" "Not Affected,Current Limit Error Status is set" newline bitfld.word 0x2 6. "FORCE_DATA_END_BIT_ERR,Force Event for Data End Bit Error (SD/eMMC Mode only) 0x0: Not Affected 0x1: Data End Bit Error Status is set" "Not Affected,Data End Bit Error Status is set" newline bitfld.word 0x2 5. "FORCE_DATA_CRC_ERR,Force Event for Data CRC Error (SD/eMMC Mode only) 0x0: Not Affected 0x1: Data CRC Error Status is set" "Not Affected,Data CRC Error Status is set" newline bitfld.word 0x2 4. "FORCE_DATA_TOUT_ERR,Force Event for Data Timeout Error (SD/eMMC Mode only) 0x0: Not Affected 0x1: Data Timeout Error Status is set" "Not Affected,Data Timeout Error Status is set" newline bitfld.word 0x2 3. "FORCE_CMD_IDX_ERR,Force Event for Command Index Error (SD/eMMC Mode only) 0x0: Not Affected 0x1: Command Index Error Status is set" "Not Affected,Command Index Error Status is set" newline bitfld.word 0x2 2. "FORCE_CMD_END_BIT_ERR,Force Event for Command End Bit Error (SD/eMMC Mode only) 0x0: Not Affected 0x1: Command End Bit Error Status is set" "Not Affected,Command End Bit Error Status is set" newline bitfld.word 0x2 1. "FORCE_CMD_CRC_ERR,Force Event for Command CRC Error (SD/eMMC Mode only) 0x0: Not Affected 0x1: Command CRC Error Status is set" "Not Affected,Command CRC Error Status is set" newline bitfld.word 0x2 0. "FORCE_CMD_TOUT_ERR,Force Event for Command Timeout Error (SD/eMMC Mode only) 0x0: Not Affected 0x1: Command Timeout Error Status is set" "Not Affected,Command Timeout Error Status is set" rgroup.byte 0x54++0x0 line.byte 0x0 "ADMA_ERR_STAT_R,This register stores the ADMA state during an ADMA error. This register is applicable for an SD/eMMC/UHS-II mode." newline hexmask.byte 0x0 3.--7. 1. "RSVD_7_3,These bits of the ADMA_ERR_STAT_R register are reserved. They always return 0." newline bitfld.byte 0x0 2. "ADMA_LEN_ERR,ADMA Length Mismatch Error States This error occurs in the following instances: - While the Block Count Enable is being set the total data length specified by the Descriptor table is different from that specified by the Block Count and.." "No Error,Error" newline bitfld.byte 0x0 0.--1. "ADMA_ERR_STATES,ADMA Error States These bits indicate the state of ADMA when an error occurs during ADMA data transfer. 0x1: Fetch Descriptor - SYS_ADR register points to the error descriptor 0x0: Stop DMA - SYS_ADR register points to a location next to.." "Stop DMA,Fetch Descriptor,Never set this state,Transfer Data" group.long 0x58++0x7 line.long 0x0 "ADMA_SA_LOW_R,This register holds the lower 32-bit system address for DMA transfer. This register is applicable for an SD/eMMC/UHS-II mode." hexmask.long 0x0 0.--31. 1. "ADMA_SA_LOW,ADMA System Address These bits indicate the lower 32 bits of the ADMA system address. - SDMA: If Host Version 4 Enable is set to 1 this register stores the system address of the data location - ADMA2: This register stores the byte address of.." line.long 0x4 "ADMA_SA_HIGH_R,This register holds the upper 32-bit system address for the DMA transfer. This register is applicable for an SD/eMMC/UHS-II mode." hexmask.long 0x4 0.--31. 1. "ADMA_SA_HIGH,ADMA System Address These bits indicate the higher 32-bit of the ADMA system address." rgroup.word 0x60++0xF line.word 0x0 "PRESET_INIT_R,This register defines Preset Value for Initialization in SD/eMMC mode." newline bitfld.word 0x0 14.--15. "DRV_SEL_VAL,Driver Strength Select Value These bits indicate that the Driver strength is supported by 1.8V signaling bus speed modes. These bits are meaningless for 3.3V signaling. 0x1: Driver Type A is selected 0x0: Driver Type B is selected 0x2: Driver.." "Driver Type B is selected,Driver Type A is selected,Driver Type C is selected,Driver Type D is selected" newline bitfld.word 0x0 11.--13. "RSVD_13_11,These bits of the PRESET_INIT_R register are reserved. They always return 0." "0,1,2,3,4,5,6,7" newline bitfld.word 0x0 10. "CLK_GEN_SEL_VAL,Clock Generator Select Value This bit is effective when the Host Controller supports a programmable clock generator. 0x0: Host Controller Ver2.0 Compatible Clock Generator 0x1: Programmable Clock Generator" "Host Controller Ver2,Programmable Clock Generator" newline hexmask.word 0x0 0.--9. 1. "FREQ_SEL_VAL,SDCLK/RCLK Frequency Select Value 10-bit preset value to be set in SDCLK/RCLK Frequency Select field of the Clock Control register described by a Host System." line.word 0x2 "PRESET_DS_R,This register defines Preset Value for Default Speed mode in SD mode." newline bitfld.word 0x2 14.--15. "DRV_SEL_VAL,Driver Strength Select Value These bits indicate the Driver strength value supported by 1.8V signaling bus speed modes. This field is meaningless for the Default speed mode as it uses 3.3V signaling. 0x1: Driver Type A is selected 0x0: Driver.." "Driver Type B is selected,Driver Type A is selected,Driver Type C is selected,Driver Type D is selected" newline bitfld.word 0x2 11.--13. "RSVD_13_11,These bits of the PRESET_DS_R register are reserved. They always return 0." "0,1,2,3,4,5,6,7" newline bitfld.word 0x2 10. "CLK_GEN_SEL_VAL,Clock Generator Select Value This bit is effective when Host Controller supports programmable clock generator. 0x0: Host Controller Ver2.0 Compatible Clock Generator 0x1: Programmable Clock Generator" "Host Controller Ver2,Programmable Clock Generator" newline hexmask.word 0x2 0.--9. 1. "FREQ_SEL_VAL,SDCLK/RCLK Frequency Select Value 10-bit preset value to be set in SDCLK/RCLK Frequency Select field of the Clock Control register described by a Host System." line.word 0x4 "PRESET_HS_R,This register defines Preset Value for High Speed mode in SD mode." newline bitfld.word 0x4 14.--15. "DRV_SEL_VAL,Driver Strength Select Value These bits indicate the Driver strength value supported by 1.8V signaling bus speed modes. This field is meaningless for High speed mode as it uses 3.3V signaling. 0x1: Driver Type A is selected 0x0: Driver Type B.." "Driver Type B is selected,Driver Type A is selected,Driver Type C is selected,Driver Type D is selected" newline bitfld.word 0x4 11.--13. "RSVD_13_11,These bits of the PRESET_HS_R register are reserved. They always return 0." "0,1,2,3,4,5,6,7" newline bitfld.word 0x4 10. "CLK_GEN_SEL_VAL,Clock Generator Select Value This bit is effective when Host Controller supports programmable clock generator. 0x0: Host Controller Ver2.0 Compatible Clock Generator 0x1: Programmable Clock Generator" "Host Controller Ver2,Programmable Clock Generator" newline hexmask.word 0x4 0.--9. 1. "FREQ_SEL_VAL,SDCLK/RCLK Frequency Select Value 10-bit preset value to be set in SDCLK/RCLK Frequency Select field of the Clock Control register described by a Host System." line.word 0x6 "PRESET_SDR12_R,This register defines Preset Value for SDR12 and Legacy speed mode in SD and eMMC mode respectively." newline bitfld.word 0x6 14.--15. "DRV_SEL_VAL,Driver Strength Select Value These bits indicate the Driver strength value supported for the SDR12 bus speed mode. These bits are meaningless for 3.3V signaling. 0x1: Driver Type A is selected 0x0: Driver Type B is selected 0x2: Driver Type C.." "Driver Type B is selected,Driver Type A is selected,Driver Type C is selected,Driver Type D is selected" newline bitfld.word 0x6 11.--13. "RSVD_13_11,These bits of the PRESET_SDR12_R register are reserved. They always return 0." "0,1,2,3,4,5,6,7" newline bitfld.word 0x6 10. "CLK_GEN_SEL_VAL,Clock Generator Select Value This bit is effective when Host Controller supports programmable clock generator 0x0: Host Controller Ver2.0 Compatible Clock Generator 0x1: Programmable Clock Generator" "Host Controller Ver2,Programmable Clock Generator" newline hexmask.word 0x6 0.--9. 1. "FREQ_SEL_VAL,SDCLK/RCLK Frequency Select Value 10-bit preset value to be set in SDCLK/RCLK Frequency Select field of the Clock Control register described by a Host System." line.word 0x8 "PRESET_SDR25_R,This register defines Preset Value for SDR25 and High Speed SDR speed mode in SD and eMMC mode respectively." newline bitfld.word 0x8 14.--15. "DRV_SEL_VAL,Driver Strength Select Value These bits indicate the Driver strength value supported for the SDR25 bus speed mode. These bits are meaningless for 3.3V signaling. 0x1: Driver Type A is selected 0x0: Driver Type B is selected 0x2: Driver Type C.." "Driver Type B is selected,Driver Type A is selected,Driver Type C is selected,Driver Type D is selected" newline bitfld.word 0x8 11.--13. "RSVD_13_11,These bits of the PRESET_SDR25_R register are reserved. They always return 0." "0,1,2,3,4,5,6,7" newline bitfld.word 0x8 10. "CLK_GEN_SEL_VAL,Clock Generator Select Value This bit is effective when Host Controller supports programmable clock generator. 0x0: Host Controller Ver2.0 Compatible Clock Generator 0x1: Programmable Clock Generator" "Host Controller Ver2,Programmable Clock Generator" newline hexmask.word 0x8 0.--9. 1. "FREQ_SEL_VAL,SDCLK/RCLK Frequency Select Value 10-bit preset value to be set in SDCLK/RCLK Frequency Select field of the Clock Control register described by a Host System." line.word 0xA "PRESET_SDR50_R,This register defines Preset Value for SDR50 speed mode in SD mode." newline bitfld.word 0xA 14.--15. "DRV_SEL_VAL,Driver Strength Select Value These bits indicate Driver strength value supported for SDR50 bus speed mode. These bits are meaningless for 3.3V signaling. 0x1: Driver Type A is selected 0x0: Driver Type B is selected 0x2: Driver Type C is.." "Driver Type B is selected,Driver Type A is selected,Driver Type C is selected,Driver Type D is selected" newline bitfld.word 0xA 11.--13. "RSVD_13_11,These bits of the PRESET_SDR50_R register are reserved. They always return 0." "0,1,2,3,4,5,6,7" newline bitfld.word 0xA 10. "CLK_GEN_SEL_VAL,Clock Generator Select Value This bit is effective when Host Controller supports programmable clock generator. 0x0: Host Controller Ver2.0 Compatible Clock Generator 0x1: Programmable Clock Generator" "Host Controller Ver2,Programmable Clock Generator" newline hexmask.word 0xA 0.--9. 1. "FREQ_SEL_VAL,SDCLK/RCLK Frequency Select Value 10-bit preset value to be set in SDCLK/RCLK Frequency Select field of the Clock Control register described by a Host System." line.word 0xC "PRESET_SDR104_R,This register defines Preset Value for SDR104 and HS200 speed modes in the SD and eMMC modes. respectively." newline bitfld.word 0xC 14.--15. "DRV_SEL_VAL,Driver Strength Select Value These bits indicate Driver strength value supported for SDR104 bus speed mode. These bits are meaningless for 3.3V signaling. 0x1: Driver Type A is selected 0x0: Driver Type B is selected 0x2: Driver Type C is.." "Driver Type B is selected,Driver Type A is selected,Driver Type C is selected,Driver Type D is selected" newline bitfld.word 0xC 11.--13. "RSVD_13_11,These bits of the PRESET_SDR104_R register are reserved. They always return 0." "0,1,2,3,4,5,6,7" newline bitfld.word 0xC 10. "CLK_GEN_SEL_VAL,Clock Generator Select Value This bit is effective when Host Controller supports programmable clock generator. 0x0: Host Controller Ver2.0 Compatible Clock Generator 0x1: Programmable Clock Generator" "Host Controller Ver2,Programmable Clock Generator" newline hexmask.word 0xC 0.--9. 1. "FREQ_SEL_VAL,SDCLK/RCLK Frequency Select Value These bits specify a 10-bit preset value that must be set in the SDCLK/RCLK Frequency Select field of the Clock Control register described by a Host System." line.word 0xE "PRESET_DDR50_R,This register defines the Preset Value for DDR50 and High Speed DDR speed modes in the SD and eMMC modes. respectively." newline bitfld.word 0xE 14.--15. "DRV_SEL_VAL,Driver Strength Select Value These bits indicate Driver strength value supported for DDR50 bus speed mode. These bits are meaningless for 3.3V signaling. 0x1: Driver Type A is selected 0x0: Driver Type B is selected 0x2: Driver Type C is.." "Driver Type B is selected,Driver Type A is selected,Driver Type C is selected,Driver Type D is selected" newline bitfld.word 0xE 11.--13. "RSVD_13_11,These bits of the PRESET_DDR50_R register are reserved. They always return 0." "0,1,2,3,4,5,6,7" newline bitfld.word 0xE 10. "CLK_GEN_SEL_VAL,Clock Generator Select Value This bit is effective when Host Controller supports programmable clock generator. 0x0: Host Controller Ver2.0 Compatible Clock Generator 0x1: Programmable Clock Generator" "Host Controller Ver2,Programmable Clock Generator" newline hexmask.word 0xE 0.--9. 1. "FREQ_SEL_VAL,SDCLK/RCLK Frequency Select Value These bits specify a 10-bit preset value that must be set in the SDCLK/RCLK Frequency Select field of the Clock Control register as described by a Host System." rgroup.word 0x74++0x1 line.word 0x0 "PRESET_UHS2_R,This register is used to hold the preset value for UHS-II and HS400 speed modes in the SD and eMMC modes. respectively." newline bitfld.word 0x0 14.--15. "DRV_SEL_VAL,Driver Strength Select Value These bits indicate the Driver strength value supported by 1.8V signaling bus speed modes in the SD mode. This field is meaningless for UHS-II mode. In eMMC mode these bits can be used for selecting the Drive.." "Driver Type B is selected,Driver Type A is selected,Driver Type C is selected,Driver Type D is selected" newline bitfld.word 0x0 11.--13. "RSVD_13_11,These bits of UHS-II Preset register are reserved. They always return 0." "0,1,2,3,4,5,6,7" newline bitfld.word 0x0 10. "CLK_GEN_SEL_VAL,Clock Generator Select Value This bit is effective when the Host Controller supports a programmable clock generator. 0x0: Host Controller Ver2.0 Compatible Clock Generator 0x1: Programmable Clock Generator" "Host Controller Ver2,Programmable Clock Generator" newline hexmask.word 0x0 0.--9. 1. "FREQ_SEL_VAL,SDCLK/RCLK Frequency Select Value These bits specify the 10-bit preset value that must be set in the SDCLK/RCLK Frequency Select field of the Clock Control register as described by a Host System." group.long 0x78++0x7 line.long 0x0 "ADMA_ID_LOW_R,This register holds the lower 32-bit Integrated Descriptor address.This register is applicable for an SD/eMMC/UHS-II mode." hexmask.long 0x0 0.--31. 1. "ADMA_ID_LOW,ADMA Integrated Descriptor Address These bits indicate the lower 32-bit of the ADMA Integrated Descriptor address. The start address of Integrated Descriptor is set to these register bits. The ADMA3 fetches one Descriptor Address and.." line.long 0x4 "ADMA_ID_HIGH_R,This register holds the upper 32-bit Integrated Descriptor address.This register is applicable for an SD/eMMC/UHS-II mode." hexmask.long 0x4 0.--31. 1. "ADMA_ID_HIGH,ADMA Integrated Descriptor Address These bits indicate the higher 32 bit of the ADMA Integrated Descriptor address." rgroup.word 0xE6++0x5 line.word 0x0 "P_EMBEDDED_CNTRL,This register points to the location of UHS-II embedded control registers." newline hexmask.word.byte 0x0 12.--15. 1. "RESERVED_15_12,These bits of the P_EMBEDDED_CNTRL register are reserved. They always return 0." newline hexmask.word 0x0 0.--11. 1. "REG_OFFSET_ADDR,Offset Address of Embedded Control register." line.word 0x2 "P_VENDOR_SPECIFIC_AREA,This register used as a pointer for the Vendor Specific Area 1." newline hexmask.word.byte 0x2 12.--15. 1. "RESERVED_15_12,These bits of the P_VENDOR_SPECIFIC_AREA register are reserved. They always return 0." newline hexmask.word 0x2 0.--11. 1. "REG_OFFSET_ADDR,Base offset Address for Vendor-Specific registers." line.word 0x4 "P_VENDOR2_SPECIFIC_AREA,This register is used as a pointer for the Vendor Specific Area 2." newline hexmask.word 0x4 0.--15. 1. "REG_OFFSET_ADDR,Base offset Address for Command Queuing registers." rgroup.word 0xFC++0x3 line.word 0x0 "SLOT_INTR_STATUS_R,This register indicates the Interrupt status of each slot." newline hexmask.word.byte 0x0 8.--15. 1. "RESERVED_15_8,These bits of the SLOT_INTR_STATUS_R register are reserved. They always return 0." newline hexmask.word.byte 0x0 0.--7. 1. "INTR_SLOT,Interrupt signal for each Slot These status bits indicate the logical OR of Interrupt signal and Wakeup signal for each slot. A maximum of 8 slots can be defined. If one interrupt signal is associated with multiple slots the Host Driver can.." line.word 0x2 "HOST_CNTRL_VERS_R,This register is used to indicate the Host Controller Version number." newline hexmask.word.byte 0x2 8.--15. 1. "VENDOR_VERSION_NUM,Vendor Version Number This field is reserved for the vendor version number. Host Driver must not use this status." newline hexmask.word.byte 0x2 0.--7. 1. "SPEC_VERSION_NUM,Specification Version Number These bits indicate the Host controller specification version. The upper and lower 4-bits indicate the version. Values 0x06-0xFF are reserved. 0x0: SD Host Controller Specification Version 1.00 0x1: SD Host.." tree.end tree "DWC_mshc_embedded_control_block (This register block defines embedded control registers)" base ad:0x3948 group.long 0x0++0x3 line.long 0x0 "EMBEDDED_CTRL_R,This register controls the embedded device. When the Host Controller is connected to a removable device. this register is not used." rbitfld.long 0x0 31. "RSVD_31,This bit (RSVD_31) of the EMBEDDED_CTRL_R register is reserved. It always returns 0." "0,1" hexmask.long.byte 0x0 24.--30. 1. "BACK_END_PWR_CTRL,Back-End Power Control (SD Mode) Each bit of this field controls back-end power supply for an embedded device. - 0 - Back-End Power is off - 1 - Back-End Power is supplied D24 - Back-End Power for Device 1 D25 - Back-End Power for.." rbitfld.long 0x0 23. "RSVD_23,This bit (RSVD_23) of the EMBEDDED_CTRL_R register is reserved. It always returns 0." "0,1" newline bitfld.long 0x0 20.--22. "INT_PIN_SEL,Interrupt Pin Select These bits enable the interrupt pin inputs. - 000 - Interrupts (INT_A INT_B INT_C) are disabled - xx1 - INT_A is enabled - x1x - INT_B is enabled - 1xx - INT_C is enabled" "Interrupts,INT_A is enabled,?,?,?,?,?,?" rbitfld.long 0x0 19. "RSVD_19,This bit (RSVD_19) of the EMBEDDED_CTRL_R register is reserved. It always returns 0." "0,1" bitfld.long 0x0 16.--18. "CLK_PIN_SEL,Clock Pin Select (SD Mode) This bit is selected by one of clock pin outputs. - 0x0 - Clock pins are disabled - 0x1 - CLK[1] is selected - 0x2 - CLK[2] is selected - . . - . . - . . - 0x7 - CLK[7] is selected" "Clock pins are disabled,CLK[1] is selected,CLK[2] is selected,?,?,?,?,CLK[7] is selected" newline rbitfld.long 0x0 15. "RSVD_15,This bit (RSVD_15) of the EMBEDDED_CTRL_R register is reserved. It always returns 0." "0,1" hexmask.long.byte 0x0 8.--14. 1. "BUS_WIDTH_PRESET,Bus Width Preset (SD Mode) Each bit of this field specifies the bus width for each embedded device. The shared bus supports mixing of 4-bit and 8-bit bus width devices. - D08 - Bus Width Preset for Device 1 - D09 - Bus Width Preset for.." rbitfld.long 0x0 6.--7. "RSVD_7_6,These bits (RSVD_7_6) of the EMBEDDED_CTRL_R register are reserved. They always return 0." "0,1,2,3" newline rbitfld.long 0x0 4.--5. "NUM_INT_PIN,Number of Interrupt Input Pins This field indicates support of interrupt input pins for an embedded system." "0,1,2,3" rbitfld.long 0x0 3. "RSVD_3,This bit (RSVD_3) of the EMBEDDED_CTRL_R register is reserved. It always returns 0." "0,1" rbitfld.long 0x0 0.--2. "NUM_CLK_PIN,Number of Clock Pins (SD Mode) This field indicates support of clock pins to select one of devices for shared bus system. Up to 7 clock pins can be supported. - 0x0 - Shared bus is not supported - 0x1 - 1 SDCLK is supported - 0x2 - 2 SDCLK is.." "Shared bus is not supported,?,?,?,?,?,?,?" tree.end tree "DWC_mshc_vendor1_block (This register block defines Vendor-1 related registers)" base ad:0x1280 rgroup.long 0x0++0x7 line.long 0x0 "MSHC_VER_ID_R,This register reflects the current release number of DWC_mshc/DWC_mshc_lite." hexmask.long 0x0 0.--31. 1. "MSHC_VER_ID,Current release number This field indicates the Synopsys DesignWare Cores DWC_mshc/DWC_mshc_lite current release number that is read by an application. For example release number '1.70a' is represented in ASCII as 0x313730. Lower 8 bits read.." line.long 0x4 "MSHC_VER_TYPE_R,This register reflects the current release type of DWC_mshc/DWC_mshc_lite." hexmask.long 0x4 0.--31. 1. "MSHC_VER_TYPE,Current release type This field indicates the Synopsys DesignWare Cores DWC_mshc/DWC_mshc_lite current release type that is read by an application. For example release type is 'ga' is represented in ASCII as 0x6761. Lower 16 bits read from.." group.byte 0x8++0x0 line.byte 0x0 "MSHC_CTRL_R,This register is used to control the operation of MSHC Host Controller." bitfld.byte 0x0 4. "SW_CG_DIS,Internal clock gating disable control This bit must be used to disable IP's internal clock gating when required. when disabled clocks are not gated. Clocks to the core (except hclk) must be stopped when programming this bit. 0x1: Internal clock.." "Internal clock gates are active and clock gating..,Internal clock gating is disabled" newline rbitfld.byte 0x0 1.--3. "RSVD1,These bits (RSVD1) of the MSHC_CTRL_R register are reserved. They always return 0." "0,1,2,3,4,5,6,7" newline bitfld.byte 0x0 0. "CMD_CONFLICT_CHECK,Command conflict check This bit enables command conflict check. Note: DWC_mshc controller monitors the CMD line whenever a command is issued and checks whether the value driven on sd_cmd_out matches the value on sd_cmd_in at next.." "Disable command conflict check,Check for command conflict after 1 card clock.." group.byte 0x10++0x0 line.byte 0x0 "MBIU_CTRL_R,This register is used to select the valid burst types that the AHB Master bus interface can generate. When more than one bit is set the master selects the burst it prefers among those that are enabled in this register." hexmask.byte 0x0 4.--7. 1. "RSVD,Reserved field" newline bitfld.byte 0x0 3. "BURST_INCR16_EN,INCR16 Burst Controls generation of INCR16 transfers on Master interface. 0x0: AHB INCR16 burst type is not generated on Master I/F 0x1: AHB INCR16 burst type can be generated on Master I/F" "AHB INCR16 burst type is not generated on Master..,AHB INCR16 burst type can be generated on Master.." newline bitfld.byte 0x0 2. "BURST_INCR8_EN,INCR8 Burst Controls generation of INCR8 transfers on Master interface. 0x0: AHB INCR8 burst type is not generated on Master I/F 0x1: AHB INCR8 burst type can be generated on Master I/F" "AHB INCR8 burst type is not generated on Master..,AHB INCR8 burst type can be generated on Master.." newline bitfld.byte 0x0 1. "BURST_INCR4_EN,INCR4 Burst Controls generation of INCR4 transfers on Master interface. 0x0: AHB INCR4 burst type is not generated on Master I/F 0x1: AHB INCR4 burst type can be generated on Master I/F" "AHB INCR4 burst type is not generated on Master..,AHB INCR4 burst type can be generated on Master.." newline bitfld.byte 0x0 0. "UNDEFL_INCR_EN,Undefined INCR Burst Controls generation of undefined length INCR transfer on Master interface. 0x0: Undefined INCR type burst is the least preferred burst on AHB Master I/F 0x1: Undefined INCR type burst is the most preferred burst on AHB.." "Undefined INCR type burst is the least preferred..,Undefined INCR type burst is the most preferred.." group.word 0x2C++0x3 line.word 0x0 "EMMC_CTRL_R,This register is used to control the eMMC operation." hexmask.word.byte 0x0 11.--15. 1. "RSVD,These bits (RSVD) of the EMMC_CTRL_R register are reserved. They always return 0." newline bitfld.word 0x0 10. "CQE_PREFETCH_DISABLE,Enable or Disable CQE's PREFETCH feature This field allows Software to disable CQE's data prefetch feature when set to 1. 0x1: Prefetch for WRITE and Pipeline for READ are disabled 0x0: CQE can Prefetch data for sucessive WRITE.." "CQE can Prefetch data for sucessive WRITE..,Prefetch for WRITE and Pipeline for READ are.." newline bitfld.word 0x0 9. "CQE_ALGO_SEL,Scheduler algorithm selected for execution This bit selects the Algorithm used for selecting one of the many ready tasks for execution. 0x1: First come First serve in the order of DBR rings 0x0: Priority based reordering with FCFS to.." "Priority based reordering with FCFS to resolve..,First come First serve" newline bitfld.word 0x0 8. "ENH_STROBE_ENABLE,Enhanced Strobe Enable This bit instructs DWC_mshc to sample the CMD line using data strobe for HS400 mode. 0x1: CMD line is sampled using data strobe for HS400 mode 0x0: CMD line is sampled using cclk_rx for HS400 mode" "CMD line is sampled using cclk_rx for HS400 mode,CMD line is sampled using data strobe for HS400.." newline bitfld.word 0x0 3. "EMMC_RST_N_OE,Output Enable control for EMMC Device Reset signal PAD control. This field drived sd_rst_n_oe output of DWC_mshc 0x0: sd_rst_n_oe is 0 0x1: sd_rst_n_oe is 1" "sd_rst_n_oe is 0,sd_rst_n_oe is 1" newline bitfld.word 0x0 2. "EMMC_RST_N,EMMC Device Reset signal control. This register field controls the sd_rst_n output of DWC_mshc 0x0: Reset to eMMC device asserted (active low) 0x1: Reset to eMMC device is deasserted" "Reset to eMMC device asserted,Reset to eMMC device is deasserted" newline bitfld.word 0x0 1. "DISABLE_DATA_CRC_CHK,Disable Data CRC Check This bit controls masking of CRC16 error for Card Write in eMMC mode. This is useful in bus testing (CMD19) for an eMMC device. In bus testing an eMMC card does not send CRC status for a block which may.." "DATA CRC check is enabled,DATA CRC check is disabled" newline bitfld.word 0x0 0. "CARD_IS_EMMC,eMMC Card present This bit indicates the type of card connected. An application program this bit based on the card connected to MSHC. 0x1: Card connected to MSHC is an eMMC card 0x0: Card connected to MSHC is a non-eMMC card" "Card connected to MSHC is a non-eMMC card,Card connected to MSHC is an eMMC card" line.word 0x2 "BOOT_CTRL_R,This register is used to control the eMMC Boot operation." hexmask.word.byte 0x2 12.--15. 1. "BOOT_TOUT_CNT,Boot Ack Timeout Counter Value. This value determines the interval by which boot ack timeout (50 ms) is detected when boot ack is expected during boot operation. - 0xF - Reserved - 0xE - TMCLK x 2^27 - .. - ............ - 0x1 - TMCLK x 2^14.." newline rbitfld.word 0x2 9.--11. "RSVD_11_9,These bits (RSVD_11_9) of the BOOT_CTRL_R register are reserved. They always return 0." "0,1,2,3,4,5,6,7" newline bitfld.word 0x2 8. "BOOT_ACK_ENABLE,Boot Acknowledge Enable When this bit set DWC_mshc checks for boot acknowledge start pattern of 0-1-0 during boot operation. This bit is applicable for both mandatory and alternate boot mode. 0x0: Boot Ack disable 0x1: Boot Ack enable" "Boot Ack disable,Boot Ack enable" newline bitfld.word 0x2 7. "VALIDATE_BOOT,Validate Mandatory Boot Enable bit This bit is used to validate the MAN_BOOT_EN bit. 0x0: Ignore Mandatory boot Enable bit 0x1: Validate Mandatory boot enable bit" "Ignore Mandatory boot Enable bit,Validate Mandatory boot enable bit" newline hexmask.word.byte 0x2 1.--6. 1. "RSVD_6_1,These bits (RSVD _6_1) of the BOOT_CTRL_R register are reserved. They always return 0." newline bitfld.word 0x2 0. "MAN_BOOT_EN,Mandatory Boot Enable This bit is used to initiate the mandatory boot operation. The application sets this bit along with VALIDATE_BOOT bit. Writing 0 is ignored. The DWC_mshc clears this bit after the boot transfer is completed or.." "Mandatory boot disable,Mandatory boot enable" group.long 0x40++0x7 line.long 0x0 "AT_CTRL_R,This register controls some aspects of tuning and auto-tuning features. Do not program this register when HOST_CTRL2_R.SAMPLE_CLK_SEL is '1'" hexmask.long.byte 0x0 24.--30. 1. "SWIN_TH_VAL,Sampling window threshold value setting The maximum value that can be set here depends on the length of delayline used for tuning. A delayLine with 128 taps can use values from 0x0 to 0x7F. This field is valid only when SWIN_TH_EN is '1'." newline bitfld.long 0x0 19.--20. "POST_CHANGE_DLY,Time taken for phase switching and stable clock output. Specifies the maximum time (in terms of cclk cycles) that the delay line can take to switch its output phase after a change in tuning_cclk_sel or autotuning_cclk_sel. 0x0: Less than.." "Less than 1-cycle latency,Less than 2-cycle latency,Less than 3-cycle latency,Less than 4-cycle latency" newline bitfld.long 0x0 17.--18. "PRE_CHANGE_DLY,Maximum Latency specification between cclk_tx and cclk_rx. 0x0: Less than 1-cycle latency 0x1: Less than 2-cycle latency 0x2: Less than 3-cycle latency 0x3: Less than 4-cycle latency" "Less than 1-cycle latency,Less than 2-cycle latency,Less than 3-cycle latency,Less than 4-cycle latency" newline bitfld.long 0x0 16. "TUNE_CLK_STOP_EN,Clock stopping control for Tuning and auto-tuning circuit. When enabled clock gate control output of DWC_mshc (clk2card_on) is pulled low before changing phase select codes on tuning_cclk_sel and autotuning_cclk_sel. This effectively.." "Clocks not stopped,Clocks stopped during phase code change" newline hexmask.long.byte 0x0 12.--15. 1. "RSDV3,These bits (RSVD3) of the AT_CTRL_R register are reserved. They always return 0." newline hexmask.long.byte 0x0 8.--11. 1. "WIN_EDGE_SEL,This field sets the phase for Left and Right edges for drift monitoring. [Left edge offset + Right edge offset] must not be less than total taps of delayLine. - 0x0: User selection disabled. Tuning calculated edges are used. - 0x1: Right.." newline rbitfld.long 0x0 5.--7. "RSDV2,These bits (RSVD2) of the AT_CTRL_R register are reserved. They always return 0." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 4. "SW_TUNE_EN,This fields enables software-managed tuning flow. 0x0: Software-managed tuning disabled. 0x1: Software-managed tuning enabled. AT_STAT_R.CENTER_PH_CODE Field is now writable." "Software-managed tuning disabled,Software-managed tuning enabled" newline bitfld.long 0x0 3. "RPT_TUNE_ERR,Framing errors are not generated when executing tuning. This debug bit allows users to report these errors. 0x1: Debug mode for reporting framing errors 0x0: Default mode where as per SD-HCI no errors are reported." "Default mode where as per SD-HCI no errors are..,Debug mode for reporting framing errors" newline bitfld.long 0x0 2. "SWIN_TH_EN,Sampling window Threshold enable Selects the tuning mode Field should be programmed only when SAMPLE_CLK_SEL is '0' 0x0: Tuning engine sweeps all taps and settles at the largest window 0x1: Tuning engine selects the first complete sampling.." "Tuning engine sweeps all taps and settles at the..,Tuning engine selects the first complete.." newline bitfld.long 0x0 1. "CI_SEL,Selects the interval when the corrected center phase select code can be driven on tuning_cclk_sel output. 0x0: Driven in block gap interval 0x1: Driven at the end of the transfer" "Driven in block gap interval,Driven at the end of the transfer" newline bitfld.long 0x0 0. "AT_EN,Setting this bit enables Auto tuning engine. This bit is enabled by default when core is configured with mode3 retuning support. Clear this bit to 0 when core is configured to have Mode3 re-tuning but SW wishes to disable mode3 re-tuning. This.." "AutoTuning is disabled,AutoTuning is enabled" line.long 0x4 "AT_STAT_R,Register to read the Center. Left and Right codes used by tuning and auto-tuning engines. Center code field is also used for software managed tuning." hexmask.long.byte 0x4 24.--31. 1. "RSDV1,These bits of the AT_STAT_R register are reserved. They always return 0." newline hexmask.long.byte 0x4 16.--23. 1. "L_EDGE_PH_CODE,Left Edge Phase code. Reading this field returns the phase code value used by Auto-tuning engine to sample data on Left edge of sampling window." newline hexmask.long.byte 0x4 8.--15. 1. "R_EDGE_PH_CODE,Right Edge Phase code. Reading this field returns the phase code value used by Auto-tuning engine to sample data on Right edge of sampling window." newline hexmask.long.byte 0x4 0.--7. 1. "CENTER_PH_CODE,Centered Phase code. Reading this field returns the current value on tuning_cclk_sel output. Setting AT_CTRL_R.SW_TUNE_EN enables software to write to this field and its contents are reflected on tuning_cclk_sel." tree.end tree "DWC_mshc_vendor2_block (This register block defines Vendor-2 related registers)" base ad:0x384 rgroup.long 0x0++0x7 line.long 0x0 "CQVER,This register provides information about the version of the eMMC Command Queueing standard. which is implemented by the CQE in BCD format." hexmask.long.tbyte 0x0 12.--31. 1. "EMMMC_VER_RSVD,These bits of the CQVER register are reserved. They always return 0." hexmask.long.byte 0x0 8.--11. 1. "EMMC_VER_MAJOR,This bit indicates the eMMC major version (1st digit left of decimal point) in BCD format." newline hexmask.long.byte 0x0 4.--7. 1. "EMMC_VER_MINOR,This bit indicates the eMMC minor version (1st digit right of decimal point) in BCD format." hexmask.long.byte 0x0 0.--3. 1. "EMMC_VER_SUFFIX,This bit indicates the eMMC version suffix (2nd digit right of decimal point) in BCD format." line.long 0x4 "CQCAP,This register indicates the capabilities of the command queuing engine." bitfld.long 0x4 29.--31. "CQCCAP_RSVD3,These bits [31:29] of the CQCAP register are reserved. They always return 0." "0,1,2,3,4,5,6,7" bitfld.long 0x4 28. "CRYPTO_SUPPORT,Crypto Support This bit indicates whether the Host Controller supports cryptographic operations. 0x0: Crypto not Supported 0x1: Crypto Supported" "Crypto not Supported,Crypto Supported" newline hexmask.long.word 0x4 16.--27. 1. "CQCCAP_RSVD2,These bits [27:16] of the CQCAP register are reserved. They always return 0." hexmask.long.byte 0x4 12.--15. 1. "ITCFMUL,Internal Timer Clock Frequency Multiplier (ITCFMUL) This field indicates the frequency of the clock used for interrupt coalescing timer and for determining the SQS polling period. See ITCFVAL definition for details. Values 0x5 to 0xF are.." newline bitfld.long 0x4 10.--11. "CQCCAP_RSVD1,These bits of the CQCAP register are reserved. They always return 0." "0,1,2,3" hexmask.long.word 0x4 0.--9. 1. "ITCFVAL,Internal Timer Clock Frequency Value (ITCFVAL) This field scales the frequency of the timer clock provided by ITCFMUL. The Final clock frequency of actual timer clock is calculated as ITCFVAL* ITCFMUL." group.long 0x8++0x27 line.long 0x0 "CQCFG,This register controls CQE behavior affecting the general operation of command queuing engine." hexmask.long.tbyte 0x0 13.--31. 1. "CQCCFG_RSVD3,These bits (CQCCFG_RSVD3) of the CQCFG register are reserved. They always return 0." bitfld.long 0x0 12. "DCMD_EN,This bit indicates to the hardware whether the Task Descriptor in slot #31 of the TDL is a data transfer descriptor or a direct-command descriptor. CQE uses this bit when a task is issued in slot #31 to determine how to decode the Task.." "Task descriptor in slot #31 is a data Transfer..,Task descriptor in slot #31 is a DCMD Task.." newline rbitfld.long 0x0 9.--11. "CQCCFG_RSVD2,These bits (CQCCFG_RSVD2) of the CQCFG register are reserved. They always return 0." "0,1,2,3,4,5,6,7" bitfld.long 0x0 8. "TASK_DESC_SIZE,Bit Value Description This bit indicates the size of task descriptor used in host memory. This bit can only be configured when Command Queuing Enable bit is 0 (command queuing is disabled). 0x1: Task descriptor size is 128 bits 0x0: Task.." "Task descriptor size is 64 bits,Task descriptor size is 128 bits" newline hexmask.long.byte 0x0 2.--7. 1. "CQCCFG_RSVD1,These bits (CQCCFG_RSVD1) of the CQCFG register are reserved. They always return 0." bitfld.long 0x0 0. "CQ_EN,Enable command queuing engine (CQE). When CQE is disable the software controls the eMMC bus using the registers between the addresses 0x000 to 0x1FF. Before the software writes to this bit the software verifies that the eMMC host controller is in.." "Disable command queuing,Enable command queuing" line.long 0x4 "CQCTL,This register controls CQE behavior affecting the general operation of command queuing module or simultaneous operation of multiple tasks." hexmask.long.tbyte 0x4 9.--31. 1. "CQCTL_RSVD2,These bits (CQCTL_RSVD2) of the CQCTL register are reserved. They always return 0." bitfld.long 0x4 8. "CLR_ALL_TASKS,Clear all tasks This bit can only be written when the controller is halted. This bit does not clear tasks in the device. The software has to use the CMDQ_TASK_MGMT command to clear device's queue. 0x1: Clears all the tasks in the controller.." "Programming 0 has no effect,Clears all the tasks in the controller" newline hexmask.long.byte 0x4 1.--7. 1. "CQCTL_RSVD1,These bits (CQCTL_RSVD1) of the CQCTL register are reserved. They always return 0." bitfld.long 0x4 0. "HALT,Halt request and resume 0x1: Software writes 1 to this bit when it wants to acquire software control over the eMMC bus and to disable CQE from issuing command on the bus. For example issuing a Discard Task command (CMDQ_TASK_MGMT). When the.." "Software writes 0 to this bit to exit from the..,Software writes 1 to this bit when it wants to.." line.long 0x8 "CQIS,This register indicates pending interrupts that require service. Each bit in this register is asserted in response to a specific event. only if the respective bit is set in the CQISE register." hexmask.long 0x8 6.--31. 1. "CQIS_RSVD1,These bits of the CQIS register are reserved. They always return 0." bitfld.long 0x8 3. "TCL,Task cleared interrupt This status bit is asserted (if CQISE.TCL_STE=1) when a task clear operation is completed by CQE. The completed task clear operation is either an individual task clear (by writing CQTCLR) or clearing of all tasks (by writing.." "TCL Interrupt is not set,TCL Interrupt is set" newline bitfld.long 0x8 2. "RED,Response error detected interrupt This status bit is asserted (if CQISE.RED_STE=1) when a response is received with an error bit set in the device status field. Configure the CQRMEM register to identify device status bit fields that may trigger an.." "RED Interrupt is not set,RED Interrupt is set" bitfld.long 0x8 1. "TCC,Task complete interrupt This status bit is asserted (if CQISE.TCC_STE=1) when at least one of the following conditions are met: - A task is completed and the INT bit is set in its Task Descriptor - Interrupt caused by Interrupt Coalescing logic due.." "TCC Interrupt is not set,TCC Interrupt is set" newline bitfld.long 0x8 0. "HAC,Halt complete interrupt This status bit is asserted (only if CQISE.HAC_STE=1) when halt bit in the CQCTL register transitions from 0 to 1 indicating that the host controller has completed its current ongoing task and has entered halt state. A value.." "HAC Interrupt is not set,HAC Interrupt is set" line.long 0xC "CQISE,This register enables and disables the reporting of the corresponding interrupt to host software in the CQIS register. When a bit is set (1) and the corresponding interrupt condition is active. then the bit in CQIS is asserted. Interrupt sources.." hexmask.long 0xC 6.--31. 1. "CQISTE_RSVD1,These bits of the CQISE register are reserved. They always return 0." bitfld.long 0xC 3. "TCL_STE,Task cleared interrupt status enable 0x0: CQIS.TCL is disabled 0x1: CQIS.TCL is set when its interrupt condition is active" "CQIS,CQIS" newline bitfld.long 0xC 2. "RED_STE,Response error detected interrupt status enable 0x0: CQIS.RED is disabled 0x1: CQIS.RED is set when its interrupt condition is active" "CQIS,CQIS" bitfld.long 0xC 1. "TCC_STE,Task complete interrupt status enable 0x0: CQIS.TCC is disabled 0x1: CQIS.TCC is set when its interrupt condition is active" "CQIS,CQIS" newline bitfld.long 0xC 0. "HAC_STE,Halt complete interrupt status enable 0x0: CQIS.HAC is disabled 0x1: CQIS.HAC is set when its interrupt condition is active" "CQIS,CQIS" line.long 0x10 "CQISGE,This register enables and disables the generation of interrupts to host software. When a bit is set and the corresponding bit in CQIS is set. then an interrupt is generated. Interrupt sources that are disabled are still indicated in the CQIS.." hexmask.long 0x10 6.--31. 1. "CQISGE_RSVD1,These bits of the CQISGE register are reserved. They always return 0." bitfld.long 0x10 3. "TCL_SGE,Task cleared interrupt signal enable 0x0: CQIS.TCL interrupt signal generation is disabled 0x1: CQIS.TCL interrupt signal generation is active" "CQIS,CQIS" newline bitfld.long 0x10 2. "RED_SGE,Response error detected interrupt signal enable 0x0: CQIS.RED interrupt signal generation is disabled 0x1: CQIS.RED interrupt signal generation is active" "CQIS,CQIS" bitfld.long 0x10 1. "TCC_SGE,Task complete interrupt signal enable 0x0: CQIS.TCC interrupt signal generation is disabled 0x1: CQIS.TCC interrupt signal generation is active" "CQIS,CQIS" newline bitfld.long 0x10 0. "HAC_SGE,Halt complete interrupt signal enable 0x0: CQIS.HAC interrupt signal generation is disabled 0x1: CQIS.HAC interrupt signal generation is active" "CQIS,CQIS" line.long 0x14 "CQIC,This register controls and configures interrupt coalescing feature." bitfld.long 0x14 31. "INTC_EN,Interrupt Coalescing Enable Bit 0x0: Interrupt coalescing mechanism is disabled (Default). 0x1: Interrupt coalescing mechanism is active. Interrupts are counted and timed and coalesced interrupts are generated" "Interrupt coalescing mechanism is disabled,Interrupt coalescing mechanism is active" hexmask.long.word 0x14 21.--30. 1. "CQIC_RSVD3,These bits (CQIC_RSVD3) of the CQIC register are reserved. They always return 0." newline rbitfld.long 0x14 20. "INTC_STAT,Interrupt Coalescing Status Bit This bit indicates to the software whether any tasks (with INT=0) have completed and counted towards interrupt coalescing (that is this is set if and only if INTC counter > 0). 0x1: At least one INT0 task.." "INT0 Task completions have not occurred since..,At least one INT0 task completion has been.." rbitfld.long 0x14 17.--19. "CQIC_RSVD2,These bits (CQIC_RSVD2) of the CQIC register are reserved. They always return 0." "0,1,2,3,4,5,6,7" newline bitfld.long 0x14 16. "INTC_RST,Counter and Timer Reset When host driver writes 1 the interrupt coalescing timer and counter are reset. 0x1: Interrupt coalescing timer and counter are reset 0x0: No Effect" "No Effect,Interrupt coalescing timer and counter are reset" bitfld.long 0x14 15. "INTC_TH_WEN,Interrupt Coalescing Counter Threshold Write Enable When software writes 1 to this bit the value INTC_TH is updated with the contents written on the same cycle. 0x0: Clears INTC_TH_WEN 0x1: Sets INTC_TH_WEN" "Clears INTC_TH_WEN,Sets INTC_TH_WEN" newline rbitfld.long 0x14 13.--14. "CQIC_RSVD1,These bits (CQIC_RSVD1) of the CQIC register are reserved. They always return 0." "0,1,2,3" hexmask.long.byte 0x14 8.--12. 1. "INTC_TH,Interrupt Coalescing Counter Threshold filed Software uses this field to configure the number of task completions (only tasks with INT=0 in the Task Descriptor) which are required in order to generate an interrupt. Counter Operation: As data.." newline bitfld.long 0x14 7. "TOUT_VAL_WEN,When software writes 1 to this bit the value TOUT_VAL is updated with the contents written on the same cycle. 0x0: clears TOUT_VAL_WEN 0x1: Sets TOUT_VAL_WEN" "clears TOUT_VAL_WEN,Sets TOUT_VAL_WEN" hexmask.long.byte 0x14 0.--6. 1. "TOUT_VAL,Interrupt Coalescing Timeout Value Software uses this field to configure the maximum time allowed between the completion of a task on the bus and the generation of an interrupt. Timer Operation: The timer is reset by software during the.." line.long 0x18 "CQTDLBA,This register is used for configuring the lower 32 bits of the byte address of the head of the Task Descriptor List in the host memory." hexmask.long 0x18 0.--31. 1. "TDLBA,This register stores the LSB bits (31:0) of the byte address of the head of the Task Descriptor List in system memory. The size of the task descriptor list is 32 * (Task Descriptor size + Transfer Descriptor size) as configured by the host driver." line.long 0x1C "CQTDLBAU,This register is used for configuring the upper 32 bits of the byte address of the head of the Task Descriptor List in the host memory." hexmask.long 0x1C 0.--31. 1. "TDLBAU,This register stores the MSB bits (63:32) of the byte address of the head of the Task Descriptor List in system memory. The size of the task descriptor list is 32 * (Task Descriptor size + Transfer Descriptor size) as configured by Host driver." line.long 0x20 "CQTDBR,Using this register. software triggers CQE to process a new task." hexmask.long 0x20 0.--31. 1. "DBR,The software configures TDLBA and TDLBAU and enable CQE in CQCFG before using this register. Writing 1 to bit n of this register triggers CQE to start processing the task encoded in slot n of the TDL. Writing 0 by the software does not have any.." line.long 0x24 "CQTCN,This register is used by CQE to notify software about completed tasks." hexmask.long 0x24 0.--31. 1. "TCN,Task Completion Notification Each of the 32 bits are bit mapped to the 32 tasks. - Bit-N(1): Task-N has completed execution (with success or errors) - Bit-N(0): Task-N has not completed could be pending or not submitted. On task completion software.." rgroup.long 0x30++0x7 line.long 0x0 "CQDQS,This register stores the most recent value of the device's queue status." hexmask.long 0x0 0.--31. 1. "DQS,Device Queue Status Each of the 32 bits are bit mapped to the 32 tasks. - Bit-N(1): Device has marked task N as ready for execution - Bit-N(0): Task-N is not ready for execution. This task could be pending in device or not submitted. Host controller.." line.long 0x4 "CQDPT,This register maintains the list of tasks that are queued into device and are awaiting execution completion." hexmask.long 0x4 0.--31. 1. "DPT,Device-Pending Tasks Each of the 32 bits are bit mapped to the 32 tasks. - Bit-N(1): Task-N has been successfully queued into the device and is awaiting execution - Bit-N(0): Task-N is not yet queued. Bit n of this register is set if and only if.." group.long 0x38++0x3 line.long 0x0 "CQTCLR,This register is used for removing an outstanding task in the CQE. The register must be used only when CQE is in Halt state." hexmask.long 0x0 0.--31. 1. "TCLR,Writing 1 to bit n of this register orders CQE to clear a task that the software has previously issued. This bit can only be written when CQE is in Halt state as indicated in CQCFG register Halt bit. When software writes 1 to a bit in this register.." group.long 0x40++0x7 line.long 0x0 "CQSSC1,This register is used for removing an outstanding task in the CQE. The register controls when SEND_QUEUE_STATUS commands are sent." hexmask.long.word 0x0 20.--31. 1. "RSVD_20_31,These bits of the CQSSC1 register are reserved. They always return 0." hexmask.long.byte 0x0 16.--19. 1. "SQSCMD_BLK_CNT,This field indicates when SQS CMD is sent while data transfer is in progress. A value of 'n' indicates that CQE sends status command on the CMD line during the transfer of data block BLOCK_CNT-n on the data lines where BLOCK_CNT is the.." newline hexmask.long.word 0x0 0.--15. 1. "SQSCMD_IDLE_TMR,This field configures the polling period to be used when using periodic SEND_QUEUE_STATUS (CMD13) polling. Periodic polling is used when tasks are pending in the device but no data transfer is in progress. When a SEND_QUEUE_STATUS.." line.long 0x4 "CQSSC2,The register is used for configuring the RCA field in SEND_QUEUE_STATUS command argument." hexmask.long.word 0x4 16.--31. 1. "RSVD_16_31,These bits of the CQSSC2 register are reserved. They always return 0." hexmask.long.word 0x4 0.--15. 1. "SQSCMD_RCA,This field provides CQE with the contents of the 16-bit RCA field in SEND_QUEUE_STATUS (CMD13) command argument. CQE copies this field to bits 31:16 of the argument when transmitting SEND_QUEUE_STATUS (CMD13) command." rgroup.long 0x48++0x3 line.long 0x0 "CQCRDCT,This register stores the response of last executed DCMD." hexmask.long 0x0 0.--31. 1. "DCMD_RESP,This register contains the response of the command generated by the last direct command (DCMD) task that was sent. Contents of this register are valid only after bit 31 of CQTDBR register is cleared by the controller." group.long 0x50++0x3 line.long 0x0 "CQRMEM,This register controls the generation of response error detect (RED) interrupt. Only the bits enabled here can contribute to RED." hexmask.long 0x0 0.--31. 1. "RESP_ERR_MASK,The bits of this field are bit mapped to the device response. This bit is used as an interrupt mask on the device status filed that is received in R1/R1b responses. - 1: When a R1/R1b response is received with a bit i in the device status.." rgroup.long 0x54++0xB line.long 0x0 "CQTERRI,This register is updated by CQE when an error occurs on data or command related to a task activity. When such an error is detected by CQE or indicated by the eMMC controller. CQE stores the following in the CQTERRI register: task IDs and indices.." bitfld.long 0x0 31. "TRANS_ERR_FIELDS_VALID,This bit is updated when an error is detected while a data transfer transaction was in progress. 0x0: Ignore contents of TRANS_ERR_TASKID and TRANS_ERR_CMD_INDX 0x1: data transfer related error detected. Check contents of.." "Ignore contents of TRANS_ERR_TASKID and..,data transfer related error detected" bitfld.long 0x0 29.--30. "RSVD_30_29,These bits (RSVD_30_29) of the CQTERRI register are reserved. They always return 0." "0,1,2,3" newline hexmask.long.byte 0x0 24.--28. 1. "TRANS_ERR_TASKID,This field captures the ID of the task that was executed and whose data transfer has errors." bitfld.long 0x0 22.--23. "RSVD_23_22,These bits (RSVD_23_22) of the CQTERRI register are reserved. They always return 0." "0,1,2,3" newline hexmask.long.byte 0x0 16.--21. 1. "TRANS_ERR_CMD_INDX,This field captures the index of the command that was executed and whose data transfer has errors." bitfld.long 0x0 15. "RESP_ERR_FIELDS_VALID,This bit is updated when an error is detected while a command transaction was in progress. 0x0: Ignore contents of RESP_ERR_TASKID and RESP_ERR_CMD_INDX 0x1: Response-related error is detected. Check contents of RESP_ERR_TASKID and.." "Ignore contents of RESP_ERR_TASKID and..,Response-related error is detected" newline bitfld.long 0x0 13.--14. "RSVD_13_14,These bits (RSVD_13_14) of the CQTERRI register are reserved. They always return 0." "0,1,2,3" hexmask.long.byte 0x0 8.--12. 1. "RESP_ERR_TASKID,This field captures the ID of the task which was executed on the command line when the error occurred." newline bitfld.long 0x0 6.--7. "RSVD_6_7,These bits (RSVD_6_7) of the CQTERRI register are reserved. They always return 0." "0,1,2,3" hexmask.long.byte 0x0 0.--5. 1. "RESP_ERR_CMD_INDX,This field captures the index of the command that was executed on the command line when the error occurred." line.long 0x4 "CQCRI,This register stores the index of the last received command response." hexmask.long 0x4 6.--31. 1. "RSVD_31_6,These bits of the CQCRI register are reserved. They always return 0." hexmask.long.byte 0x4 0.--5. 1. "CMD_RESP_INDX,Last Command Response index This field stores the index of the last received command response. Controller updates the value every time a command response is received." line.long 0x8 "CQCRA,This register stores the argument of the last received command response." hexmask.long 0x8 0.--31. 1. "CMD_RESP_ARG,Last Command Response argument This field stores the argument of the last received command response. Controller updates the value every time a command response is received." tree.end tree "DWC_mshc_phy_block (This register block has PHY related registers)" base ad:0x768 group.long 0x0++0x3 line.long 0x0 "PHY_CNFG,SD/eMMC PHY general configuration register" hexmask.long.byte 0x0 20.--23. 1. "PAD_SN,NMOS TX drive strength control. Common config for all for SD/eMMC Pads." hexmask.long.byte 0x0 16.--19. 1. "PAD_SP,PMOS TX drive strength control. Common config for all for SD/eMMC Pads." newline rbitfld.long 0x0 1. "PHY_PWRGOOD,Phy's Power Good status is captured here. Ensure this is '1' before stating transactions." "0,1" bitfld.long 0x0 0. "PHY_RSTN,Active-Low reset control for PHY write '0' to reset PHY Write '1' to deassert reset." "0,1" group.word 0x4++0xF line.word 0x0 "CMDPAD_CNFG,SD/eMMC PHY's Command/Response PAD settings are controlled here" hexmask.word.byte 0x0 9.--12. 1. "TXSLEW_CTRL_N,Slew control for N-Type CMD Pad's TX" hexmask.word.byte 0x0 5.--8. 1. "TXSLEW_CTRL_P,Slew control for P-Type CMD Pad's TX" newline bitfld.word 0x0 3.--4. "WEAKPULL_EN,Pull-up/Pul-down enable control for CMD PAD 0x0: Pull-up and pull-down functionality disabled 0x3: Should not be used 0x2: Weak pull down enabled 0x1: Weak pull up enabled" "Pull-up and pull-down functionality disabled,Weak pull up enabled,Weak pull down enabled,Should not be used" bitfld.word 0x0 0.--2. "RXSEL,Reciver type select for PAD. Controls the RXSEL value of SD/eMMC PHY CMD PAD" "0,1,2,3,4,5,6,7" line.word 0x2 "DATPAD_CNFG,SD/eMMC PHY's Data PAD settings are controlled here. common settings for all data pads" hexmask.word.byte 0x2 9.--12. 1. "TXSLEW_CTRL_N,Slew control for N-Type DATA Pad's TX" hexmask.word.byte 0x2 5.--8. 1. "TXSLEW_CTRL_P,Slew control for P-Type DATA Pad's TX" newline bitfld.word 0x2 3.--4. "WEAKPULL_EN,Pull-up/Pull-down enable control for DATA PADs 0x0: Pull-up and pull-down functionality disabled 0x3: Should not be used 0x2: Weak pull down enabled 0x1: Weak pull up enabled" "Pull-up and pull-down functionality disabled,Weak pull up enabled,Weak pull down enabled,Should not be used" bitfld.word 0x2 0.--2. "RXSEL,Reciver type select for PAD. Controls the RXSEL value of SD/eMMC PHY DATA PADs" "0,1,2,3,4,5,6,7" line.word 0x4 "CLKPAD_CNFG,SD/eMMC PHY's CLK PAD settings are controlled here." hexmask.word.byte 0x4 9.--12. 1. "TXSLEW_CTRL_N,Slew control for N-Type CLK Pad's TX" hexmask.word.byte 0x4 5.--8. 1. "TXSLEW_CTRL_P,Slew control for P-Type CLK Pad's TX" newline bitfld.word 0x4 3.--4. "WEAKPULL_EN,Pull-up/Pul-down enable control for CLK PAD 0x0: Pull-up and pull-down functionality disabled 0x3: Should not be used 0x2: Weak pull down enabled 0x1: Weak pull up enabled" "Pull-up and pull-down functionality disabled,Weak pull up enabled,Weak pull down enabled,Should not be used" bitfld.word 0x4 0.--2. "RXSEL,Reciver type select for PAD. Controls the RXSEL value of SD/eMMC PHY CLK PAD" "0,1,2,3,4,5,6,7" line.word 0x6 "STBPAD_CNFG,SD/eMMC PHY's Strobe PAD settings are controlled here." hexmask.word.byte 0x6 9.--12. 1. "TXSLEW_CTRL_N,Slew control for N-Type Strobe Pad's TX" hexmask.word.byte 0x6 5.--8. 1. "TXSLEW_CTRL_P,Slew control for P-Type Strobe Pad's TX" newline bitfld.word 0x6 3.--4. "WEAKPULL_EN,Pull-up/Pul-down enable control for STROBE PAD 0x0: Pull-up and pull-down functionality disabled 0x3: Should not be used 0x2: Weak pull down enabled 0x1: Weak pull up enabled" "Pull-up and pull-down functionality disabled,Weak pull up enabled,Weak pull down enabled,Should not be used" bitfld.word 0x6 0.--2. "RXSEL,Reciver type select for PAD. Controls the RXSEL value of SD/eMMC PHY STROBE PAD" "0,1,2,3,4,5,6,7" line.word 0x8 "RSTNPAD_CNFG,SD/eMMC PHY's RSTN PAD settings are controlled here." hexmask.word.byte 0x8 9.--12. 1. "TXSLEW_CTRL_N,Slew control for N-Type RST_N Pad's TX" hexmask.word.byte 0x8 5.--8. 1. "TXSLEW_CTRL_P,Slew control for P-Type RST_N Pad's TX" newline bitfld.word 0x8 3.--4. "WEAKPULL_EN,Pull-up/Pul-down enable control for RST_N PAD(s) 0x0: Pull-up and pull-down functionality disabled 0x3: Should not be used 0x2: Weak pull down enabled 0x1: Weak pull up enabled" "Pull-up and pull-down functionality disabled,Weak pull up enabled,Weak pull down enabled,Should not be used" bitfld.word 0x8 0.--2. "RXSEL,Reciver type select for PAD. Controls the RXSEL value of SD/eMMC PHY RST_N PAD(s)" "0,1,2,3,4,5,6,7" line.word 0xA "PADTEST_CNFG,PAD TEST Path and direction control" hexmask.word 0xA 4.--15. 1. "TEST_OE,test interface OE control. Drive's PHY's itest_oe inputs." rbitfld.word 0xA 1.--3. "RSVD_1,RSVD1 field is reserved" "0,1,2,3,4,5,6,7" newline bitfld.word 0xA 0. "TESTMODE_EN,enables test mode interface for all PADS. Functional interface is disabled. 0x0: PAD's functional mode I/F is active 0x1: PAD's test mode interface is active" "PAD's functional mode I/F is active,PAD's test mode interface is active" line.word 0xC "PADTEST_OUT,PAD TEST Path Data out. Drives itest_a input of SD/eMMC PHY" hexmask.word 0xC 0.--11. 1. "TESTDATA_OUT,Data written here is reflected on corresponding itest_a. Indivitual bits are mapped to corresponding itest_a inputs of the PHY" line.word 0xE "PADTEST_IN,PAD TEST Path Data in. reflects value of otest_y output of SD/eMMC PHY" hexmask.word 0xE 0.--11. 1. "TESTDATA_IN,individual bits here capture data avaliable on corresponding otest_y output. should be used for DC test and low freq data patterns." group.word 0x18++0x1 line.word 0x0 "PRBS_CNFG,Register to configure PRBS engine" hexmask.word 0x0 0.--15. 1. "INIT_SEED,Value programmed here is used as SEED for PRBS engine" group.byte 0x1A++0x0 line.byte 0x0 "PHYLPBK_CNFG,Register to setup loopback mode" bitfld.byte 0x0 0. "PHYLPBK_EN,PHY Local loop back mode is enable 0x0: Controller is not in PHY loopback mode 0x1: Controller is now in PHY Loopback mode" "Controller is not in PHY loopback mode,Controller is now in PHY Loopback mode" group.byte 0x1C++0x2 line.byte 0x0 "COMMDL_CNFG,Config register to settings common to all DelayLines used in PHY" bitfld.byte 0x0 1. "DLOUT_EN,When '1' DL outputs can be sampled on PADs. Drives idlout_en for all PADs 0x0: DelayLine outputs on PAD disabled 0x1: DelayLine outputs on PAD enabled" "DelayLine outputs on PAD disabled,DelayLine outputs on PAD enabled" bitfld.byte 0x0 0. "DLSTEP_SEL,DelayLine's per step delay selection Drives PHY's idl_step input" "0,1" line.byte 0x1 "SDCLKDL_CNFG,Settings for SD/eMMC CLK DelayLine." bitfld.byte 0x1 4. "UPDATE_DC,Prepares DealyLine for code update when '1'. Its recommended that this bit is 1 when SDCLKDL_DC is being written. Ensure this is '0' when not updating code. Note: Turn-off card clock using CLK_CTRL_R.SD_CLK_EN before programing this field. 0x1:.." "DelayLine output is enabled,output of DelayLine is DelayLine output active" bitfld.byte 0x1 2.--3. "INPSEL_CNFG,Drives SD/eMMC CLK DelayLine's config input. Value here selects the input source to DelayLine" "0,1,2,3" newline bitfld.byte 0x1 1. "BYPASS_EN,Drives SD/eMMC CLK DelayLine's bypassen input 0x1: DelayLine is bypass mode 0x0: Delay line active mode" "Delay line active mode,DelayLine is bypass mode" bitfld.byte 0x1 0. "EXTDLY_EN,Drives SD/eMMC CLK DelayLine's extdlyen input 0x0: Delay line defaut range setting 0x1: DelayLine works with extended delay range setting" "Delay line defaut range setting,DelayLine works with extended delay range setting" line.byte 0x2 "SDCLKDL_DC,SD/eMMC CLK DelayLine Delay Code value" hexmask.byte 0x2 0.--6. 1. "CCKDL_DC,Drives SD/eMMC CLK DelayLine's Delay Code input. Value here Selects the number of active stages in the card clock delay line. Note: Turn-off card clock using CLK_CTRL_R.SD_CLK_EN before programing this field." group.byte 0x20++0x1 line.byte 0x0 "SMPLDL_CNFG,SD/eMMC cclk_rx DelayLine configuration settings" bitfld.byte 0x0 4. "INPSEL_OVERRIDE,PHY's Sampling delay line config is controlled by controller using sample_cclk_sel this signal overides sample_cclk_sel such that INPSEL_CFG field directly control's PHY's config input. - 0x0 : Controller logic drive Sampling delay line.." "Controller logic drive Sampling delay line config,SMPLDL_CNFG" bitfld.byte 0x0 2.--3. "INPSEL_CNFG,Drives CCLK_RX DelayLine's config input. Value here selects the input source to DelayLine" "0,1,2,3" newline bitfld.byte 0x0 1. "BYPASS_EN,Drives CCLK_RX DelayLine's bypassen input 0x1: DelayLine is bypass mode 0x0: Delay line active mode" "Delay line active mode,DelayLine is bypass mode" bitfld.byte 0x0 0. "EXTDLY_EN,Drives CCLK_RX DelayLine's extdlyen input 0x0: Delay line defaut range setting 0x1: DelayLine works with extended delay range setting" "Delay line defaut range setting,DelayLine works with extended delay range setting" line.byte 0x1 "ATDL_CNFG,SD/eMMC drift_cclk_rx DelayLine configuration settings" bitfld.byte 0x1 2.--3. "INPSEL_CNFG,Drives drift_cclk_rx DelayLine's config input. Value here selects the input source to DelayLine" "0,1,2,3" bitfld.byte 0x1 1. "BYPASS_EN,Drives drift_cclk_rx DelayLine's bypassen input 0x1: DelayLine is bypass mode 0x0: Delay line active mode" "Delay line active mode,DelayLine is bypass mode" newline bitfld.byte 0x1 0. "EXTDLY_EN,Drives drift_cclk_rx DelayLine's extdlyen input 0x0: Delay line defaut range setting 0x1: DelayLine works with extended delay range setting" "Delay line defaut range setting,DelayLine works with extended delay range setting" group.byte 0x24++0x2 line.byte 0x0 "DLL_CTRL,SD/eMMC PHY's DLL Control settings register" hexmask.byte 0x0 3.--7. 1. "RSVD_3_7,These bits of the register are reserved." bitfld.byte 0x0 2. "SLV_SWDC_UPDATE,Corresponding output drives PHY's DLL Slave's dc update input. This is used to turn-off Slave Delay line's output when changing its delay code using DLL_OFFST register 0x1: Update in progress 0x0: Update completed" "Update completed,Update in progress" newline bitfld.byte 0x0 1. "OFFST_EN,Enables offset mode of PHY when DLL is enabled. when DLL is disabled this allows direct control of delay generated by DLL's Slave 0x0: offset value is invalid 0x1: Offset value is valid" "offset value is invalid,Offset value is valid" bitfld.byte 0x0 0. "DLL_EN,Enable's DLL when '1' 0x0: PHY DLL is disabled 0x1: PHY DLL is enabled" "PHY DLL is disabled,PHY DLL is enabled" line.byte 0x1 "DLL_CNFG1,SD/eMMC PHY DLL configuration register 1" bitfld.byte 0x1 4.--5. "SLVDLY,Sets the value of DLL slave's update delay input islv_update_dly" "0,1,2,3" bitfld.byte 0x1 0.--2. "WAITCYCLE,Sets the value of DLL's wait cycle input" "0,1,2,3,4,5,6,7" line.byte 0x2 "DLL_CNFG2,SD/eMMC PHY DLL configuration register 2" hexmask.byte 0x2 0.--6. 1. "JUMPSTEP,Sets the value of DLL's jump step input" group.byte 0x28++0x2 line.byte 0x0 "DLLDL_CNFG,SD/eMMC PHY DLL MST & Slave DL configuration settings" bitfld.byte 0x0 7. "SLV_BYPASS,Bypass enable control for Slave DL" "0,1" bitfld.byte 0x0 5.--6. "SLV_INPSEL,Clock source select for Slave DL" "0,1,2,3" newline bitfld.byte 0x0 4. "SLV_EXTDLYEN,Enable Extended delay mode for Slave" "0,1" bitfld.byte 0x0 3. "MST_BYPASS,Bypass enable control for Master DL" "0,1" newline bitfld.byte 0x0 1.--2. "MST_INPSEL,Clock source select for Master DL" "0,1,2,3" bitfld.byte 0x0 0. "MST_EXTDLYEN,Enable Extended delay mode for master" "0,1" line.byte 0x1 "DLL_OFFST,SD/eMMC PHY DLL Offset value settings" hexmask.byte 0x1 0.--6. 1. "OFFST,Sets the value of DLL's offset input" line.byte 0x2 "DLLMST_TSTDC,SD/eMMC PHY DLL Master testing Delay code register" hexmask.byte 0x2 0.--6. 1. "MSTTST_DC,Sets the value of DLL's Master test code input when DLL is disabled." group.word 0x2C++0x1 line.word 0x0 "DLLLBT_CNFG,SD/eMMC PHY DLL Low Bandwidth Timer configuration register" hexmask.word 0x0 0.--15. 1. "LBT_LOADVAL,Sets the value of DLL's olbt_loadval input. Controls the lbt timer's timeout value at which DLL runs a revalidation cycle." rgroup.byte 0x2E++0x0 line.byte 0x0 "DLL_STATUS,SD/eMMC PHY DLL Status register" bitfld.byte 0x0 1. "ERROR_STS,Captures the value of DLL's lock error status information. Value is valid only when LOCK_STS is set. - IF LOCK_STS =1 and ERR_STS = 0 then DLL is locked and no errors are generated - IF LOCK_STS =1 and ERR_STS = 1 then DLL is locked to default.." "DLL has not locked,DLL is locked and ready" bitfld.byte 0x0 0. "LOCK_STS,Captures the value of DLL's lock status information 0x1: DLL is locked and ready 0x0: DLL has not locked" "DLL has not locked,DLL is locked and ready" rgroup.byte 0x30++0x0 line.byte 0x0 "DLLDBG_MLKDC,SD/eMMC PHY DLL's Master lock code status" hexmask.byte 0x0 0.--6. 1. "MSTLKDC,Captures the value Delay Code to which DLL's Master has locked" rgroup.byte 0x32++0x0 line.byte 0x0 "DLLDBG_SLKDC,SD/eMMC PHY DLL's Slave lock code status" hexmask.byte 0x0 0.--6. 1. "SLVLKDC,Captures the value Delay Code to which DLL's Slave has locked" tree.end tree.end repeat.end endif tree.end tree "OSC (Crystal-less Oscillator)" sif (CORENAME()=="CORTEXR5F") tree "OSC_SAFETY" base ad:0xF0240000 group.long 0x0++0xB line.long 0x0 "OSC_CAL,OSC CALIBRATION SETTING" rbitfld.long 0x0 31. "OSC_READY,oscillator and counter both ready" "0,1" bitfld.long 0x0 14. "OSC_SRC,Oscillator setting source select 0: setting from register 1: setting from fuse" "setting from register,setting from fuse" newline hexmask.long.word 0x0 2.--13. 1. "OSC_FCAL,Trim to set nominal oscillator frequency to adjust for process variations. Provides between a 0.05% (low-end) to 0.02% (high-end) step. Ensuresthat frequency will remain within +/- 2% of target over PVT after calibration(MODE==1)Trim can be.." bitfld.long 0x0 1. "OSC_MODE,High Frequency/Low Frequency Mode Select 0: Low Power Mode Low Frequency Operation. FOSC=0.9MHz to 2.0MHz depending on process corner 1: Normal Operating Mode. FOSC=25MHz after calibration" "Low Power Mode,Normal Operating Mode" bitfld.long 0x0 0. "OSC_EN,Oscillator global analog enable signal 0: Oscillator is powered down 1: Oscillator is enabled" "Oscillator is powered down,Oscillator is enabled" line.long 0x4 "CLK_SEL,OUTPUT CLK SOUCE SELECT REGISTER" bitfld.long 0x4 0. "CLK_SEL,output clock source select 0: from oscillator 1: from XTAL" "from oscillator,from XTAL" line.long 0x8 "CLK_CHK,OSC AND XTAL CHECK REGISTER" rbitfld.long 0x8 9. "OSC_FORCE_STA,osc force status." "0,1" rbitfld.long 0x8 8. "XTAL_FORCE_STA,xtal force status." "0,1" newline rbitfld.long 0x8 7. "OSC_NG_INT_STA,osc ng interrupt status" "0,1" bitfld.long 0x8 6. "OSC_NG_INT_CLR,osc ng interrupt clear write 1 clear will auto clear to 0." "0,1" bitfld.long 0x8 5. "OSC_NG_INT_EN,osc ng interrupt enable 0: disable 1: enable" "disable,enable" newline rbitfld.long 0x8 4. "XTAL_NG_INT_STA,xtal ng interrupt status" "0,1" bitfld.long 0x8 3. "XTAL_NG_INT_CLR,xtal ng interrupt clear write 1 clear will auto clear to 0." "0,1" bitfld.long 0x8 2. "XTAL_NG_INT_EN,xtal ng interrupt enable 0: disable 1: enable" "disable,enable" newline bitfld.long 0x8 1. "OSC_NG_CHK_EN,osc ng check enable 0: disable 1: enable" "disable,enable" bitfld.long 0x8 0. "XTAL_NG_CHK_EN,xtal ng check enable 0: disable 1: enable" "disable,enable" tree.end tree "OSC_RTC" base ad:0xF1820000 group.long 0x0++0xB line.long 0x0 "OSC_CAL,OSC CALIBRATION SETTING" rbitfld.long 0x0 31. "OSC_READY,oscillator and counter both ready" "0,1" bitfld.long 0x0 14. "OSC_SRC,Oscillator setting source select 0: setting from register 1: setting from fuse" "setting from register,setting from fuse" newline hexmask.long.word 0x0 2.--13. 1. "OSC_FCAL,Trim to set nominal oscillator frequency to adjust for process variations. Provides between a 0.05% (low-end) to 0.02% (high-end) step. Ensuresthat frequency will remain within +/- 2% of target over PVT after calibration(MODE==1)Trim can be.." bitfld.long 0x0 1. "OSC_MODE,High Frequency/Low Frequency Mode Select 0: Low Power Mode Low Frequency Operation. FOSC=0.9MHz to 2.0MHz depending on process corner 1: Normal Operating Mode. FOSC=25MHz after calibration" "Low Power Mode,Normal Operating Mode" bitfld.long 0x0 0. "OSC_EN,Oscillator global analog enable signal 0: Oscillator is powered down 1: Oscillator is enabled" "Oscillator is powered down,Oscillator is enabled" line.long 0x4 "CLK_SEL,OUTPUT CLK SOUCE SELECT REGISTER" bitfld.long 0x4 0. "CLK_SEL,output clock source select 0: from oscillator 1: from XTAL" "from oscillator,from XTAL" line.long 0x8 "CLK_CHK,OSC AND XTAL CHECK REGISTER" rbitfld.long 0x8 9. "OSC_FORCE_STA,osc force status." "0,1" rbitfld.long 0x8 8. "XTAL_FORCE_STA,xtal force status." "0,1" newline rbitfld.long 0x8 7. "OSC_NG_INT_STA,osc ng interrupt status" "0,1" bitfld.long 0x8 6. "OSC_NG_INT_CLR,osc ng interrupt clear write 1 clear will auto clear to 0." "0,1" bitfld.long 0x8 5. "OSC_NG_INT_EN,osc ng interrupt enable 0: disable 1: enable" "disable,enable" newline rbitfld.long 0x8 4. "XTAL_NG_INT_STA,xtal ng interrupt status" "0,1" bitfld.long 0x8 3. "XTAL_NG_INT_CLR,xtal ng interrupt clear write 1 clear will auto clear to 0." "0,1" bitfld.long 0x8 2. "XTAL_NG_INT_EN,xtal ng interrupt enable 0: disable 1: enable" "disable,enable" newline bitfld.long 0x8 1. "OSC_NG_CHK_EN,osc ng check enable 0: disable 1: enable" "disable,enable" bitfld.long 0x8 0. "XTAL_NG_CHK_EN,xtal ng check enable 0: disable 1: enable" "disable,enable" tree.end elif (CORENAME()=="CORTEXA55") tree "OSC_SAFETY" base ad:0x30240000 group.long 0x0++0xB line.long 0x0 "OSC_CAL,OSC CALIBRATION SETTING" rbitfld.long 0x0 31. "OSC_READY,oscillator and counter both ready" "0,1" bitfld.long 0x0 14. "OSC_SRC,Oscillator setting source select 0: setting from register 1: setting from fuse" "setting from register,setting from fuse" newline hexmask.long.word 0x0 2.--13. 1. "OSC_FCAL,Trim to set nominal oscillator frequency to adjust for process variations. Provides between a 0.05% (low-end) to 0.02% (high-end) step. Ensuresthat frequency will remain within +/- 2% of target over PVT after calibration(MODE==1)Trim can be.." bitfld.long 0x0 1. "OSC_MODE,High Frequency/Low Frequency Mode Select 0: Low Power Mode Low Frequency Operation. FOSC=0.9MHz to 2.0MHz depending on process corner 1: Normal Operating Mode. FOSC=25MHz after calibration" "Low Power Mode,Normal Operating Mode" bitfld.long 0x0 0. "OSC_EN,Oscillator global analog enable signal 0: Oscillator is powered down 1: Oscillator is enabled" "Oscillator is powered down,Oscillator is enabled" line.long 0x4 "CLK_SEL,OUTPUT CLK SOUCE SELECT REGISTER" bitfld.long 0x4 0. "CLK_SEL,output clock source select 0: from oscillator 1: from XTAL" "from oscillator,from XTAL" line.long 0x8 "CLK_CHK,OSC AND XTAL CHECK REGISTER" rbitfld.long 0x8 9. "OSC_FORCE_STA,osc force status." "0,1" rbitfld.long 0x8 8. "XTAL_FORCE_STA,xtal force status." "0,1" newline rbitfld.long 0x8 7. "OSC_NG_INT_STA,osc ng interrupt status" "0,1" bitfld.long 0x8 6. "OSC_NG_INT_CLR,osc ng interrupt clear write 1 clear will auto clear to 0." "0,1" bitfld.long 0x8 5. "OSC_NG_INT_EN,osc ng interrupt enable 0: disable 1: enable" "disable,enable" newline rbitfld.long 0x8 4. "XTAL_NG_INT_STA,xtal ng interrupt status" "0,1" bitfld.long 0x8 3. "XTAL_NG_INT_CLR,xtal ng interrupt clear write 1 clear will auto clear to 0." "0,1" bitfld.long 0x8 2. "XTAL_NG_INT_EN,xtal ng interrupt enable 0: disable 1: enable" "disable,enable" newline bitfld.long 0x8 1. "OSC_NG_CHK_EN,osc ng check enable 0: disable 1: enable" "disable,enable" bitfld.long 0x8 0. "XTAL_NG_CHK_EN,xtal ng check enable 0: disable 1: enable" "disable,enable" tree.end tree "OSC_RTC" base ad:0x31820000 group.long 0x0++0xB line.long 0x0 "OSC_CAL,OSC CALIBRATION SETTING" rbitfld.long 0x0 31. "OSC_READY,oscillator and counter both ready" "0,1" bitfld.long 0x0 14. "OSC_SRC,Oscillator setting source select 0: setting from register 1: setting from fuse" "setting from register,setting from fuse" newline hexmask.long.word 0x0 2.--13. 1. "OSC_FCAL,Trim to set nominal oscillator frequency to adjust for process variations. Provides between a 0.05% (low-end) to 0.02% (high-end) step. Ensuresthat frequency will remain within +/- 2% of target over PVT after calibration(MODE==1)Trim can be.." bitfld.long 0x0 1. "OSC_MODE,High Frequency/Low Frequency Mode Select 0: Low Power Mode Low Frequency Operation. FOSC=0.9MHz to 2.0MHz depending on process corner 1: Normal Operating Mode. FOSC=25MHz after calibration" "Low Power Mode,Normal Operating Mode" bitfld.long 0x0 0. "OSC_EN,Oscillator global analog enable signal 0: Oscillator is powered down 1: Oscillator is enabled" "Oscillator is powered down,Oscillator is enabled" line.long 0x4 "CLK_SEL,OUTPUT CLK SOUCE SELECT REGISTER" bitfld.long 0x4 0. "CLK_SEL,output clock source select 0: from oscillator 1: from XTAL" "from oscillator,from XTAL" line.long 0x8 "CLK_CHK,OSC AND XTAL CHECK REGISTER" rbitfld.long 0x8 9. "OSC_FORCE_STA,osc force status." "0,1" rbitfld.long 0x8 8. "XTAL_FORCE_STA,xtal force status." "0,1" newline rbitfld.long 0x8 7. "OSC_NG_INT_STA,osc ng interrupt status" "0,1" bitfld.long 0x8 6. "OSC_NG_INT_CLR,osc ng interrupt clear write 1 clear will auto clear to 0." "0,1" bitfld.long 0x8 5. "OSC_NG_INT_EN,osc ng interrupt enable 0: disable 1: enable" "disable,enable" newline rbitfld.long 0x8 4. "XTAL_NG_INT_STA,xtal ng interrupt status" "0,1" bitfld.long 0x8 3. "XTAL_NG_INT_CLR,xtal ng interrupt clear write 1 clear will auto clear to 0." "0,1" bitfld.long 0x8 2. "XTAL_NG_INT_EN,xtal ng interrupt enable 0: disable 1: enable" "disable,enable" newline bitfld.long 0x8 1. "OSC_NG_CHK_EN,osc ng check enable 0: disable 1: enable" "disable,enable" bitfld.long 0x8 0. "XTAL_NG_CHK_EN,xtal ng check enable 0: disable 1: enable" "disable,enable" tree.end endif tree.end tree "OSPI (Octal-SPI)" sif (CORENAME()=="CORTEXR5F") tree "OSPI1" base ad:0xF0020000 group.long 0x0++0x2B line.long 0x0 "CONFIG_REG,Octal-SPI Configuration Register" rbitfld.long 0x0 31. "IDLE_FLD,Serial interface and low level SPI pipeline is IDLE: This is a STATUS read-only bit. Note this is a retimed signal so there will be some inherent delay on the generation of this status signal." "0,1" newline bitfld.long 0x0 30. "DUAL_BYTE_OPCODE_EN_FLD,Dual-byte Opcode Mode enable bit This bit is to be set in case the target Flash Device supports dual byte opcode (i.e. Macronix MX25). It is applicable for Octal I/O Mode or Protocol only so should be set back to low if the device.." "0,1" newline bitfld.long 0x0 29. "CRC_ENABLE_FLD,CRC enable bit This bit is to be set in case the target Flash Device supports CRC (Macronix MX25). It is applicable for Octal DDR Protocol only so should be set back to low if the device is configured to work in another SPI Mode." "0,1" newline bitfld.long 0x0 28. "FLIPPER_ENABLE_FLD,Flip enable bit This bit is to be set in case the target Flash Device supports data slices swapped in order of D1 D0 D3 D2 etc. It is applicable for DTR-OPI Mode of Macronix MX25 devices." "0,1" newline rbitfld.long 0x0 26.--27. "CONFIG_RESV2_FLD,Reserved" "0,1,2,3" newline bitfld.long 0x0 25. "PIPELINE_PHY_FLD,Pipeline PHY Mode enable: This bit is relevant only for configuration with PHY Module. It should be asserted to '1' between consecutive PHY pipeline reads transfers and de-asserted to '0' otherwise." "0,1" newline bitfld.long 0x0 24. "ENABLE_DTR_PROTOCOL_FLD,Enable DTR Protocol: This bit should be set if device is configured to work in DTR protocol." "0,1" newline bitfld.long 0x0 23. "ENABLE_AHB_DECODER_FLD,Enable AHB Decoder: Value=0 : Active slave is selected based on Peripheral Chip Select Lines (bits [13:10]). Value=1 Active slave is selected based on actual AHB address (the partition for each device is calculated with respect to.." "Active slave is selected based on Peripheral..,?" newline hexmask.long.byte 0x0 19.--22. 1. "MSTR_BAUD_DIV_FLD,Master Mode Baud Rate Divisor: SPI baud rate = (master reference clock) baud_rate_divisor" newline bitfld.long 0x0 18. "ENTER_XIP_MODE_IMM_FLD,Enter XIP Mode immediately: Value=0 : If XIP is enabled then setting to 0 will cause the controller to exit XIP mode on the next READ instruction. Value=1 : Operate the device in XIP mode immediately Use this register when the.." "If XIP is enabled,Operate the device in XIP mode immediately Use.." newline bitfld.long 0x0 17. "ENTER_XIP_MODE_FLD,Enter XIP Mode on next READ: Value=0 : If XIP is enabled then setting to 0 will cause the controller to exit XIP mode on the next READ instruction. Value=1 : If XIP is disabled then setting to ?1? will inform the controller that the.." "If XIP is enabled,If XIP is disabled" newline bitfld.long 0x0 16. "ENB_AHB_ADDR_REMAP_FLD,Enable AHB Address Re-mapping: (Direct Access Mode Only) When set to 1 the incoming AHB address will be adapted and sent to the FLASH device as (address + N) where N is the value stored in the remap address register." "0,1" newline bitfld.long 0x0 15. "ENB_DMA_IF_FLD,Enable DMA Peripheral Interface: Set to 1 to enable the DMA handshaking logic. When enabled the controller will trigger DMA transfer requests via the DMA peripheral interface. Set to 0 to disable" "0,1" newline bitfld.long 0x0 14. "WR_PROT_FLASH_FLD,Write Protect Flash Pin: Set to drive the Write Protect pin of the FLASH device. This is resynchronized to the generated memory clock as necessary." "0,1" newline hexmask.long.byte 0x0 10.--13. 1. "PERIPH_CS_LINES_FLD,Peripheral Chip Select Lines: Peripheral chip select lines If pdec = 0 ss[3:0] are output thus: ss[3:0] n_ss_out[3:0] xxx0 1110 xx01 1101 x011 1011 0111 0111 1111 1111 (no peripheral selected) else ss[3:0] directly drives n_ss_out[3:0]" newline bitfld.long 0x0 9. "PERIPH_SEL_DEC_FLD,Peripheral select decode: 0 : only 1 of 4 selects n_ss_out[3:0] is active 1 : allow external 4-to-16 decode (n_ss_out = ss)" "only 1 of 4 selects n_ss_out[3:0] is active,allow external 4-to-16 decode" newline bitfld.long 0x0 8. "ENB_LEGACY_IP_MODE_FLD,Legacy IP Mode Enable: 0 : Use Direct Access Controller/Indirect Access Controller 1 : legacy Mode is enabled. In this mode any write to the controller via the AHB interface is serialized and sent to the FLASH device. Any valid.." "Use Direct Access Controller/Indirect Access..,legacy Mode is enabled" newline bitfld.long 0x0 7. "ENB_DIR_ACC_CTLR_FLD,Enable Direct Access Controller: 0 : disable the Direct Access Controller once current transfer of the data word (FF_W) is complete. 1 : enable the Direct Access Controller When the Direct Access Controller and Indirect Access.." "disable the Direct Access Controller once..,enable the Direct Access Controller When the.." newline bitfld.long 0x0 6. "RESET_CFG_FLD,RESET pin configuration: 0 = RESET feature on DQ3 pin of the device 1 = RESET feature on dedicated pin of the device (controlling of 5th bit influences on reset_out output)" "RESET feature on DQ3 pin of the device,RESET feature on dedicated pin of the device" newline bitfld.long 0x0 5. "RESET_PIN_FLD,Set to drive the RESET pin of the FLASH device and reset for de-activation of the RESET pin feature" "0,1" newline bitfld.long 0x0 4. "HOLD_PIN_FLD,Set to drive the HOLD pin of the FLASH device and reset for de-activation of the HOLD pin feature" "0,1" newline bitfld.long 0x0 3. "PHY_MODE_ENABLE_FLD,PHY mode enable: When enabled the controller is informed that PHY Module is to be used for handling SPI transfers. This bit is relevant only for configuration with PHY Module. Note: - When changing this bit field software should.." "0,1" newline bitfld.long 0x0 2. "SEL_CLK_PHASE_FLD,Select Clock Phase: Selects whether the clock is in an active or inactive phase outside the SPI word. 0 : the SPI clock is active outside the word 1 : the SPI clock is inactive outside the word" "the SPI clock is active outside the word,the SPI clock is inactive outside the word" newline bitfld.long 0x0 1. "SEL_CLK_POL_FLD,Clock polarity outside SPI word: 0 : the SPI clock is quiescent low 1 : the SPI clock is quiescent high" "the SPI clock is quiescent low,the SPI clock is quiescent high" newline bitfld.long 0x0 0. "ENB_SPI_FLD,Octal-SPI Enable: 0 : disable the Octal-SPI once current transfer of the data word (FF_W) is complete. 1 : enable the Octal-SPI when spi_enable = 0 all output enables are inactive and all pins are set to input mode." "disable the Octal-SPI,enable the Octal-SPI" line.long 0x4 "DEV_INSTR_RD_CONFIG_REG,Device Read Instruction Configuration Register" rbitfld.long 0x4 29.--31. "RD_INSTR_RESV5_FLD,Reserved" "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x4 24.--28. 1. "DUMMY_RD_CLK_CYCLES_FLD,Dummy Read Clock Cycles: Number of dummy clock cycles required by device for read instruction." newline rbitfld.long 0x4 21.--23. "RD_INSTR_RESV4_FLD,Reserved" "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 20. "MODE_BIT_ENABLE_FLD,Mode Bit Enable: Set this field to 1 to ensure that the mode bits as defined in the Mode Bit Configuration register are sent following the address bytes." "0,1" newline rbitfld.long 0x4 18.--19. "RD_INSTR_RESV3_FLD,Reserved" "0,1,2,3" newline bitfld.long 0x4 16.--17. "DATA_XFER_TYPE_EXT_MODE_FLD,Data Transfer Type for Standard SPI modes: 0 : SIO mode data is shifted to the device on DQ0 only and from the device on DQ1 only 1 : Used for Dual Input/Output instructions. For data transfers DQ0 and DQ1 are used as both.." "SIO mode data is shifted to the device on DQ0..,Used for Dual Input/Output instructions,Used for Quad Input/Output instructions,Used for Quad Input/Output instructions" newline rbitfld.long 0x4 14.--15. "RD_INSTR_RESV2_FLD,Reserved" "0,1,2,3" newline bitfld.long 0x4 12.--13. "ADDR_XFER_TYPE_STD_MODE_FLD,Address Transfer Type for Standard SPI modes: 0 : Addresses can be shifted to the device on DQ0 only 1 : Addresses can be shifted to the device on DQ0 and DQ1 only 2 : Addresses can be shifted to the device on DQ0 DQ1 DQ2.." "Addresses can be shifted to the device on DQ0 only,Addresses can be shifted to the device on DQ0..,Addresses can be shifted to the device on DQ0,Addresses can be shifted to the device on DQ[7:0]" newline bitfld.long 0x4 11. "PRED_DIS_FLD,Predicted Read Disable Bit: Disable generation of predicted read when doing read accesses using Direct Mode" "0,1" newline bitfld.long 0x4 10. "DDR_EN_FLD,DDR Enable: This is to inform that opcode from rd_opcode_non_xip_fld is compliant with one of the DDR READ Commands" "0,1" newline bitfld.long 0x4 8.--9. "INSTR_TYPE_FLD,Instruction Type: 0 : Use Standard SPI mode (instruction always shifted into the device on DQ0 only) 1 : Use DIO-SPI mode (Instructions Address and Data always sent on DQ0 and DQ1) 2 : Use QIO-SPI mode (Instructions Address and Data.." "Use Standard SPI mode,Use DIO-SPI mode,Use QIO-SPI mode,Use Octal-IO-SPI mode" newline hexmask.long.byte 0x4 0.--7. 1. "RD_OPCODE_NON_XIP_FLD,Read Opcode in non-XIP mode: Read Opcode to use when not in XIP mode" line.long 0x8 "DEV_INSTR_WR_CONFIG_REG,Device Write Instruction Configuration Register" rbitfld.long 0x8 29.--31. "WR_INSTR_RESV4_FLD,Reserved" "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x8 24.--28. 1. "DUMMY_WR_CLK_CYCLES_FLD,Dummy Write Clock Cycles: Number of dummy clock cycles required by device for write instruction." newline hexmask.long.byte 0x8 18.--23. 1. "WR_INSTR_RESV3_FLD,Reserved" newline bitfld.long 0x8 16.--17. "DATA_XFER_TYPE_EXT_MODE_FLD,Data Transfer Type for Standard SPI modes: 0 : SIO mode data is shifted to the device on DQ0 only and from the device on DQ1 only 1 : Used for Dual Input/Output instructions. For data transfers DQ0 and DQ1 are used as both.." "SIO mode data is shifted to the device on DQ0..,Used for Dual Input/Output instructions,Used for Quad Input/Output instructions,Used for Octal Input/Output instructions" newline rbitfld.long 0x8 14.--15. "WR_INSTR_RESV2_FLD,Reserved" "0,1,2,3" newline bitfld.long 0x8 12.--13. "ADDR_XFER_TYPE_STD_MODE_FLD,Address Transfer Type for Standard SPI modes: 0 : Addresses can be shifted to the device on DQ0 only 1 : Addresses can be shifted to the device on DQ0 and DQ1 only 2 : Addresses can be shifted to the device on DQ0 DQ1 DQ2.." "Addresses can be shifted to the device on DQ0 only,Addresses can be shifted to the device on DQ0..,Addresses can be shifted to the device on DQ0,Addresses can be shifted to the device on DQ[7:0]" newline rbitfld.long 0x8 9.--11. "WR_INSTR_RESV1_FLD,Reserved" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 8. "WEL_DIS_FLD,WEL Disable: This is to turn off automatic issuing of WEL Command before write operation for DAC or INDAC" "0,1" newline hexmask.long.byte 0x8 0.--7. 1. "WR_OPCODE_FLD,Write Opcode" line.long 0xC "DEV_DELAY_REG,Octal-SPI Device Delay Register: This register is used to introduce relative delays into the generation of the master output signals. All timings are defined in cycles of the SPI REFERENCE CLOCK/ext_clk. defined in this table as SPI master.." hexmask.long.byte 0xC 24.--31. 1. "D_NSS_FLD,Clock Delay for Chip Select Deassert: Delay in master reference clocks for the length that the master mode chip select outputs are de-asserted between transactions. The minimum delay is always SCLK period to ensure the chip select is never.." newline hexmask.long.byte 0xC 16.--23. 1. "D_BTWN_FLD,Clock Delay for Chip Select Deactivation: Delay in master reference clocks between one chip select being de-activated and the activation of another. This is used to ensure a quiet period between the selection of two different slaves and.." newline hexmask.long.byte 0xC 8.--15. 1. "D_AFTER_FLD,Clock Delay for Last Transaction Bit: Delay in master reference clocks between last bit of current transaction and deasserting the device chip select (n_ss_out). By default the chip select will be deasserted on the cycle following the.." newline hexmask.long.byte 0xC 0.--7. 1. "D_INIT_FLD,Clock Delay with n_ss_out: Delay in master reference clocks between setting n_ss_out low and first bit transfer." line.long 0x10 "RD_DATA_CAPTURE_REG,Read Data Capture Register" hexmask.long.word 0x10 20.--31. 1. "RD_DATA_RESV3_FLD,Reserved" newline hexmask.long.byte 0x10 16.--19. 1. "DDR_READ_DELAY_FLD,DDR read delay: Delay the transmitted data by the programmed number of ref_clk cycles.This field is only relevant when DDR Read Command is executed. Otherwise can be ignored." newline hexmask.long.byte 0x10 9.--15. 1. "RD_DATA_RESV2_FLD,Reserved" newline bitfld.long 0x10 8. "DQS_ENABLE_FLD,DQS enable bit: If enabled signal from DQS input is driven into RX DLL and is used for data capturing in PHY Mode rather than internally generated gated ref_clk.." "0,1" newline rbitfld.long 0x10 6.--7. "RD_DATA_RESV1_FLD,Reserved" "0,1,2,3" newline bitfld.long 0x10 5. "SAMPLE_EDGE_SEL_FLD,Sample edge selection: Choose edge on which data outputs from flash memory will be sampled" "0,1" newline hexmask.long.byte 0x10 1.--4. 1. "DELAY_FLD,Read Delay: Delay the read data capturing logic by the programmed number of ref_clk cycles" newline bitfld.long 0x10 0. "BYPASS_FLD,Bypass the adapted loopback clock circuit" "0,1" line.long 0x14 "DEV_SIZE_CONFIG_REG,Device Size Configuration Register" rbitfld.long 0x14 29.--31. "DEV_SIZE_RESV_FLD,Reserved" "0,1,2,3,4,5,6,7" newline bitfld.long 0x14 27.--28. "MEM_SIZE_ON_CS3_FLD,Size of Flash Device connected to CS[3] pin: Value=00 : size of 512Mb. Value=01 : size of 1Gb. Value=10 : size of 2Gb. Value=11 : size of 4Gb." "size of 512Mb,size of 1Gb,?,?" newline bitfld.long 0x14 25.--26. "MEM_SIZE_ON_CS2_FLD,Size of Flash Device connected to CS[2] pin: Value=00 : size of 512Mb. Value=01 : size of 1Gb. Value=10 : size of 2Gb. Value=11 : size of 4Gb." "size of 512Mb,size of 1Gb,?,?" newline bitfld.long 0x14 23.--24. "MEM_SIZE_ON_CS1_FLD,Size of Flash Device connected to CS[1] pin: Value=00 : size of 512Mb. Value=01 : size of 1Gb. Value=10 : size of 2Gb. Value=11 : size of 4Gb." "size of 512Mb,size of 1Gb,?,?" newline bitfld.long 0x14 21.--22. "MEM_SIZE_ON_CS0_FLD,Size of Flash Device connected to CS[0] pin: Value=00 : size of 512Mb. Value=01 : size of 1Gb. Value=10 : size of 2Gb. Value=11 : size of 4Gb." "size of 512Mb,size of 1Gb,?,?" newline hexmask.long.byte 0x14 16.--20. 1. "BYTES_PER_SUBSECTOR_FLD,Number of bytes per Block. This is required by the controller for performing the write protection logic. The number of bytes per block must be a power of 2 number." newline hexmask.long.word 0x14 4.--15. 1. "BYTES_PER_DEVICE_PAGE_FLD,Number of bytes per device page. This is required by the controller for performing FLASH writes up to and across page boundaries." newline hexmask.long.byte 0x14 0.--3. 1. "NUM_ADDR_BYTES_FLD,Number of address bytes. A value of 0 indicates 1 byte." line.long 0x18 "SRAM_PARTITION_CFG_REG,SRAM Partition Configuration Register" hexmask.long.tbyte 0x18 8.--31. 1. "SRAM_PARTITION_RESV_FLD,Reserved" newline hexmask.long.byte 0x18 0.--7. 1. "ADDR_FLD,Indirect Read Partition Size: Defines the size of the indirect read partition in the SRAM in units of SRAM locations. By default half of the SRAM is reserved for indirect read operation and half for indirect write. The size of this register.." line.long 0x1C "IND_AHB_ADDR_TRIGGER_REG,Indirect AHB Address Trigger Register" hexmask.long 0x1C 0.--31. 1. "ADDR_FLD,This is the base address that will be used by the AHB controller. When the incoming AHB read access address matches a range of addresses from this trigger address to the trigger address + 15 then the AHB request will be completed by fetching.." line.long 0x20 "DMA_PERIPH_CONFIG_REG,DMA Peripheral Configuration Register" hexmask.long.tbyte 0x20 12.--31. 1. "DMA_PERIPH_RESV2_FLD,Reserved" newline hexmask.long.byte 0x20 8.--11. 1. "NUM_BURST_REQ_BYTES_FLD,Number of Burst Bytes: Number of bytes in a burst type request on the DMA peripheral request. A programmed value of 0 represents a single byte. This should be setup before starting the indirect read or write operation. The actual.." newline hexmask.long.byte 0x20 4.--7. 1. "DMA_PERIPH_RESV1_FLD,Reserved" newline hexmask.long.byte 0x20 0.--3. 1. "NUM_SINGLE_REQ_BYTES_FLD,Number of Single Bytes: Number of bytes in a single type request on the DMA peripheral request. A programmed value of 0 represents a single byte. This should be setup before starting the indirect read or write operation. The.." line.long 0x24 "REMAP_ADDR_REG,Remap Address Register" hexmask.long 0x24 0.--31. 1. "VALUE_FLD,This register is used to remap an incoming AHB address to a different address used by the FLASH device." line.long 0x28 "MODE_BIT_CONFIG_REG,Mode Bit Configuration Register" hexmask.long.byte 0x28 24.--31. 1. "RX_CRC_DATA_LOW_FLD,RX CRC data (lower) The first CRC byte returned after RX data chunk." newline hexmask.long.byte 0x28 16.--23. 1. "RX_CRC_DATA_UP_FLD,RX CRC data (upper) The second CRC byte returned after RX data chunk." newline bitfld.long 0x28 15. "CRC_OUT_ENABLE_FLD,CRC# output enable bit When enabled the controller expects the Flash Device to toggle CRC data on both SPI clock edges in CRC->CRC# sequence and calculates CRC compliance accordingly." "0,1" newline hexmask.long.byte 0x28 11.--14. 1. "MODE_BIT_RESV1_FLD,Reserved" newline bitfld.long 0x28 8.--10. "CHUNK_SIZE_FLD,It defines size of chunk after which CRC data is expected to show up on the SPI interface for write and read data transfers." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x28 0.--7. 1. "MODE_FLD,These are the 8 mode bits that are sent to the device following the address bytes if mode bit transmission has been enabled." rgroup.long 0x2C++0x3 line.long 0x0 "SRAM_FILL_REG,SRAM Fill Register" hexmask.long.word 0x0 16.--31. 1. "SRAM_FILL_INDAC_WRITE_FLD,SRAM Fill Level (Indirect Write Partition): Identifies the current fill level of the SRAM Indirect Write partition" newline hexmask.long.word 0x0 0.--15. 1. "SRAM_FILL_INDAC_READ_FLD,SRAM Fill Level (Indirect Read Partition): Identifies the current fill level of the SRAM Indirect Read partition" group.long 0x30++0x17 line.long 0x0 "TX_THRESH_REG,TX Threshold Register" hexmask.long 0x0 5.--31. 1. "TX_THRESH_RESV_FLD,Reserved" newline hexmask.long.byte 0x0 0.--4. 1. "LEVEL_FLD,Defines the level at which the small TX FIFO not full interrupt is generated" line.long 0x4 "RX_THRESH_REG,RX Threshold Register" hexmask.long 0x4 5.--31. 1. "RX_THRESH_RESV_FLD,Reserved" newline hexmask.long.byte 0x4 0.--4. 1. "LEVEL_FLD,Defines the level at which the small RX FIFO not empty interrupt is generated" line.long 0x8 "WRITE_COMPLETION_CTRL_REG,Write Completion Control Register: This register defines how the controller will poll the device following a write transfer" hexmask.long.byte 0x8 24.--31. 1. "POLL_REP_DELAY_FLD,Defines additional delay for maintain Chip Select de-asserted during auto-polling phase" newline hexmask.long.byte 0x8 16.--23. 1. "POLL_COUNT_FLD,Defines the number of times the controller should expect to see a true result from the polling in successive reads of the device register." newline bitfld.long 0x8 15. "ENABLE_POLLING_EXP_FLD,Set to '1' for enabling auto-polling expiration." "0,1" newline bitfld.long 0x8 14. "DISABLE_POLLING_FLD,This switches off the automatic polling function" "0,1" newline bitfld.long 0x8 13. "POLLING_POLARITY_FLD,Defines the polling polarity. If '1' then the write transfer to the device will be complete if the polled bit is equal to '1'. If '0' then the write transfer to the device will be complete if the polled bit is equal to '0'." "0,1" newline rbitfld.long 0x8 12. "WR_COMP_CTRL_RESV1_FLD,Reserved" "0,1" newline bitfld.long 0x8 11. "POLLING_ADDR_EN_FLD,Enables address phase of auto-polling (Read Status) command." "0,1" newline bitfld.long 0x8 8.--10. "POLLING_BIT_INDEX_FLD,Defines the bit index that should be polled. A value of 010 means that bit 2 of the returned data will be polled for.A value of 111 means that bit 7 of the returned data will be polled for." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x8 0.--7. 1. "OPCODE_FLD,Defines the opcode that should be issued by the controller when it is automatically polling for device program completion. This command is issued followed all device write operations. By default this will poll the standard device STATUS.." line.long 0xC "NO_OF_POLLS_BEF_EXP_REG,Polling Expiration Register" hexmask.long 0xC 0.--31. 1. "NO_OF_POLLS_BEF_EXP_FLD,Number of polls cycles before expiration" line.long 0x10 "IRQ_STATUS_REG,Interrupt Status Register: The status fields in this register are set when the described event occurs and the interrupt is enabled in the mask register. When any of these bit fields are set. the interrupt output is asserted high. The.." hexmask.long.word 0x10 21.--31. 1. "IRQ_STAT_RESV_FLD,Reserved" newline bitfld.long 0x10 20. "HYPER_INT_FLD,HyperFlash interrupt This interrupt informs the system that Flash Device reported interrupt on its INT# output" "0,1" newline bitfld.long 0x10 19. "ECC_FAIL_FLD,ECC failure This interrupt informs the system that Flash Device reported ECC error." "0,1" newline bitfld.long 0x10 18. "TX_CRC_CHUNK_BRK_FLD,TX CRC chunk was broken This interrupt informs the system that program page SPI transfer was discontinued somewhere inside the chunk." "0,1" newline bitfld.long 0x10 17. "RX_CRC_DATA_VAL_FLD,RX CRC data valid New RX CRC data was captured from Flash Device" "0,1" newline bitfld.long 0x10 16. "RX_CRC_DATA_ERR_FLD,RX CRC data error CRC data from Flash Device does not correspond to the one dynamically calculated by the controller." "0,1" newline rbitfld.long 0x10 15. "IRQ_STAT_RESV1_FLD,Reserved" "0,1" newline bitfld.long 0x10 14. "STIG_REQ_INT_FLD,The controller is ready for getting another STIG request." "0,1" newline bitfld.long 0x10 13. "POLL_EXP_INT_FLD,The maximum number of programmed polls cycles is expired" "0,1" newline bitfld.long 0x10 12. "INDRD_SRAM_FULL_FLD,Indirect Read Partition overflow: Indirect Read Partition of SRAM is full and unable to immediately complete indirect operation" "0,1" newline bitfld.long 0x10 11. "RX_FIFO_FULL_FLD,Small RX FIFO full: Current FIFO status can be ignored in non-SPI legacy mode 0 : FIFO is not full 1 : FIFO is full" "FIFO is not full,FIFO is full" newline bitfld.long 0x10 10. "RX_FIFO_NOT_EMPTY_FLD,Small RX FIFO not empty: Current FIFO status can be ignored in non-SPI legacy mode 0 : FIFO has less than RX THRESHOLD entries 1 : FIFO has >= THRESHOLD entries" "FIFO has less than RX THRESHOLD entries,FIFO has >= THRESHOLD entries" newline bitfld.long 0x10 9. "TX_FIFO_FULL_FLD,Small TX FIFO full: Current FIFO status can be ignored in non-SPI legacy mode 0 : FIFO is not full 1 : FIFO is full" "FIFO is not full,FIFO is full" newline bitfld.long 0x10 8. "TX_FIFO_NOT_FULL_FLD,Small TX FIFO not full: Current FIFO status can be ignored in non-SPI legacy mode 0 : FIFO has >= THRESHOLD entries 1 : FIFO has less than THRESHOLD entries" "FIFO has >= THRESHOLD entries,FIFO has less than THRESHOLD entries" newline bitfld.long 0x10 7. "RECV_OVERFLOW_FLD,Receive Overflow: This should only occur in Legacy SPI mode. Set if an attempt is made to push the RX FIFO when it is full. This bit is reset only by a system reset and cleared only when this register is read. If a new push to the RX.." "no overflow has been detected,an overflow has occurred" newline bitfld.long 0x10 6. "INDIRECT_XFER_LEVEL_BREACH_FLD,Indirect Transfer Watermark Level Breached" "0,1" newline bitfld.long 0x10 5. "ILLEGAL_ACCESS_DET_FLD,Illegal AHB access has been detected. AHB wrapping bursts and the use of SPLIT/RETRY accesses will cause this error interrupt to trigger." "0,1" newline bitfld.long 0x10 4. "PROT_WR_ATTEMPT_FLD,Write to protected area was attempted and rejected." "0,1" newline bitfld.long 0x10 3. "INDIRECT_TRANSFER_REJECT_FLD,Indirect operation was requested but could not be accepted. Two indirect operations already in storage." "0,1" newline bitfld.long 0x10 2. "INDIRECT_OP_DONE_FLD,Indirect Operation Complete: Controller has completed last triggered indirect operation" "0,1" newline bitfld.long 0x10 1. "UNDERFLOW_DET_FLD,Underflow Detected: 0 : no underflow has been detected 1 : underflow is detected and an attempt to transfer data is made when the small TX FIFO is empty. This may occur when AHB write data is being supplied too slowly to keep up with.." "no underflow has been detected,underflow is detected and an attempt to transfer.." newline bitfld.long 0x10 0. "MODE_M_FAIL_FLD,Mode M Failure: Mode M failure indicates the voltage on pin n_ss_in is inconsistent with the SPI mode. Set =1 if n_ss_in is low in master mode (multi-master contention). These conditions will clear the spi_enable bit and disable the SPI." "no mode fault has been detected,a mode fault has occurred" line.long 0x14 "IRQ_MASK_REG,Interrupt Mask: 0 : the interrupt for the corresponding interrupt status register bit is disabled. 1 : the interrupt for the corresponding interrupt status register bit is enabled." hexmask.long.word 0x14 21.--31. 1. "IRQ_MASK_RESV_FLD,Reserved" newline bitfld.long 0x14 20. "HYPER_INT_MASK_FLD,HyperFlash interrupt Mask" "0,1" newline bitfld.long 0x14 19. "ECC_FAIL_MASK_FLD,ECC failure Mask" "0,1" newline bitfld.long 0x14 18. "TX_CRC_CHUNK_BRK_MASK_FLD,TX CRC chunk was broken Mask" "0,1" newline bitfld.long 0x14 17. "RX_CRC_DATA_VAL_MASK_FLD,RX CRC data valid Mask" "0,1" newline bitfld.long 0x14 16. "RX_CRC_DATA_ERR_MASK_FLD,RX CRC data error Mask" "0,1" newline rbitfld.long 0x14 15. "IRQ_MASK_RESV1_FLD,Reserved" "0,1" newline bitfld.long 0x14 14. "STIG_REQ_MASK_FLD,STIG request completion Mask" "0,1" newline bitfld.long 0x14 13. "POLL_EXP_INT_MASK_FLD,Polling expiration detected Mask" "0,1" newline bitfld.long 0x14 12. "INDRD_SRAM_FULL_MASK_FLD,Indirect Read Partition overflow mask" "0,1" newline bitfld.long 0x14 11. "RX_FIFO_FULL_MASK_FLD,Small RX FIFO full Mask" "0,1" newline bitfld.long 0x14 10. "RX_FIFO_NOT_EMPTY_MASK_FLD,Small RX FIFO not empty Mask" "0,1" newline bitfld.long 0x14 9. "TX_FIFO_FULL_MASK_FLD,Small TX FIFO full Mask" "0,1" newline bitfld.long 0x14 8. "TX_FIFO_NOT_FULL_MASK_FLD,Small TX FIFO not full Mask" "0,1" newline bitfld.long 0x14 7. "RECV_OVERFLOW_MASK_FLD,Receive Overflow Mask" "0,1" newline bitfld.long 0x14 6. "INDIRECT_XFER_LEVEL_BREACH_MASK_FLD,Transfer Watermark Breach Mask" "0,1" newline bitfld.long 0x14 5. "ILLEGAL_ACCESS_DET_MASK_FLD,Illegal Access Detected Mask" "0,1" newline bitfld.long 0x14 4. "PROT_WR_ATTEMPT_MASK_FLD,Protected Area Write Attempt Mask" "0,1" newline bitfld.long 0x14 3. "INDIRECT_TRANSFER_REJECT_MASK_FLD,Indirect Read Reject Mask" "0,1" newline bitfld.long 0x14 2. "INDIRECT_OP_DONE_MASK_FLD,Indirect Complete Mask" "0,1" newline bitfld.long 0x14 1. "UNDERFLOW_DET_MASK_FLD,Underflow Detected Mask" "0,1" newline bitfld.long 0x14 0. "MODE_M_FAIL_MASK_FLD,Mode M Failure Mask" "0,1" group.long 0x50++0xB line.long 0x0 "LOWER_WR_PROT_REG,Lower Write Protection Register" hexmask.long 0x0 0.--31. 1. "SUBSECTOR_FLD,The block number that defines the lower block in the range of blocks that is to be locked from writing. The definition of a block in terms of number of bytes is programmable via the Device Size Configuration register." line.long 0x4 "UPPER_WR_PROT_REG,Upper Write Protection Register" hexmask.long 0x4 0.--31. 1. "SUBSECTOR_FLD,The block number that defines the upper block in the range of blocks that is to be locked from writing. The definition of a block in terms of number of bytes is programmable via the Device Size Configuration register." line.long 0x8 "WR_PROT_CTRL_REG,Write Protection Control Register" hexmask.long 0x8 2.--31. 1. "WR_PROT_CTRL_RESV_FLD,Reserved" newline bitfld.long 0x8 1. "ENB_FLD,Write Protection Enable Bit: When set to 1 any AHB write access with an address within the protection region defined in the lower and upper write protection registers is rejected. An AHB error response is generated and an interrupt source.." "0,1" newline bitfld.long 0x8 0. "INV_FLD,Write Protection Inversion Bit: When set to 1 the protection region defined in the lower and upper write protection registers is inverted meaning it is the region that the system is permitted to write to. When set to 0 the protection region.." "0,1" group.long 0x60++0x23 line.long 0x0 "INDIRECT_READ_XFER_CTRL_REG,Indirect Read Transfer Control Register" hexmask.long.tbyte 0x0 8.--31. 1. "INDIR_RD_XFER_RESV_FLD,Reserved" newline rbitfld.long 0x0 6.--7. "NUM_IND_OPS_DONE_FLD,This field contains the number of indirect operations which have been completed. This is used in conjunction with the indirect completion status field (bit 5). It is incremented by hardware when an indirect operation has completed." "0,1,2,3" newline bitfld.long 0x0 5. "IND_OPS_DONE_STATUS_FLD,Indirect Completion Status: This field is set to 1 when an indirect operation has completed. Write a 1 to this field to clear it." "0,1" newline rbitfld.long 0x0 4. "RD_QUEUED_FLD,Two indirect read operations have been queued" "0,1" newline bitfld.long 0x0 3. "SRAM_FULL_FLD,SRAM Full: SRAM full and unable to immediately complete an indirect operation. Write a 1 to this field to clear it.\'; indirect operation (status)" "0,1" newline rbitfld.long 0x0 2. "RD_STATUS_FLD,Indirect Read Status: Indirect read operation in progress (status)" "0,1" newline bitfld.long 0x0 1. "CANCEL_FLD,Cancel Indirect Read: Writing a 1 to this bit will cancel all ongoing indirect read operations." "0,1" newline bitfld.long 0x0 0. "START_FLD,Start Indirect Read: Writing a 1 to this bit will trigger an indirect read operation. The assumption is that the indirect start address and the indirect number of bytes register is setup before triggering the indirect read operation." "0,1" line.long 0x4 "INDIRECT_READ_XFER_WATERMARK_REG,Indirect Read Transfer Watermark Register" hexmask.long 0x4 0.--31. 1. "LEVEL_FLD,Watermark Value: This represents the minimum fill level of the SRAM before a DMA peripheral access is permitted. When the SRAM fill level passes the watermark an interrupt is also generated. This field can be disabled by writing a value of all.." line.long 0x8 "INDIRECT_READ_XFER_START_REG,Indirect Read Transfer Start Address Register" hexmask.long 0x8 0.--31. 1. "ADDR_FLD,This is the start address from which the indirect access will commence its READ operation." line.long 0xC "INDIRECT_READ_XFER_NUM_BYTES_REG,Indirect Read Transfer Number Bytes Register" hexmask.long 0xC 0.--31. 1. "VALUE_FLD,This is the number of bytes that the indirect access will consume. This can be bigger than the configured size of SRAM." line.long 0x10 "INDIRECT_WRITE_XFER_CTRL_REG,Indirect Write Transfer Control Register" hexmask.long.tbyte 0x10 8.--31. 1. "INDIR_WR_XFER_RESV2_FLD,Reserved" newline rbitfld.long 0x10 6.--7. "NUM_IND_OPS_DONE_FLD,This field contains the number of indirect operations which have been completed. This is used in conjunction with the indirect completion status field (bit 5). It is incremented by hardware when an indirect operation has completed." "0,1,2,3" newline bitfld.long 0x10 5. "IND_OPS_DONE_STATUS_FLD,Indirect Completion Status: This field is set to 1 when an indirect operation has completed. Write a 1 to this field to clear it." "0,1" newline rbitfld.long 0x10 4. "WR_QUEUED_FLD,Two indirect write operations have been queued" "0,1" newline rbitfld.long 0x10 3. "INDIR_WR_XFER_RESV1_FLD,Reserved" "0,1" newline rbitfld.long 0x10 2. "WR_STATUS_FLD,Indirect Write Status: Indirect write operation in progress (status)" "0,1" newline bitfld.long 0x10 1. "CANCEL_FLD,Cancel Indirect Write: Writing a 1 to this bit will cancel all ongoing indirect write operations." "0,1" newline bitfld.long 0x10 0. "START_FLD,Start Indirect Write: Writing a 1 to this bit will trigger an indirect write operation. The assumption is that the indirect start address and the indirect number of bytes register is setup before triggering the indirect write operation." "0,1" line.long 0x14 "INDIRECT_WRITE_XFER_WATERMARK_REG,Indirect Write Transfer Watermark Register" hexmask.long 0x14 0.--31. 1. "LEVEL_FLD,Watermark Value: This represents the maximum fill level of the SRAM before a DMA peripheral access is permitted. When the SRAM fill level falls below the watermark an interrupt is also generated. This field can be disabled by writing a value.." line.long 0x18 "INDIRECT_WRITE_XFER_START_REG,Indirect Write Transfer Start Address Register" hexmask.long 0x18 0.--31. 1. "ADDR_FLD,Start of Indirect Access: This is the start address from which the indirect access will commence its READ operation." line.long 0x1C "INDIRECT_WRITE_XFER_NUM_BYTES_REG,Indirect Write Transfer Number Bytes Register" hexmask.long 0x1C 0.--31. 1. "VALUE_FLD,Indirect Number of Bytes: This is the number of bytes that the indirect access will consume. This can be bigger than the configured size of SRAM." line.long 0x20 "INDIRECT_TRIGGER_ADDR_RANGE_REG,Indirect Trigger Address Range Register" hexmask.long 0x20 4.--31. 1. "IND_RANGE_RESV1_FLD,Reserved" newline hexmask.long.byte 0x20 0.--3. 1. "IND_RANGE_WIDTH_FLD,This is the address offset of Indirect Trigger Address Register." group.long 0x8C++0xB line.long 0x0 "FLASH_COMMAND_CTRL_MEM_REG,Flash Command Control Memory Register" rbitfld.long 0x0 29.--31. "FLASH_COMMAND_CTRL_MEM_RESV1_FLD,Reserved" "0,1,2,3,4,5,6,7" newline hexmask.long.word 0x0 20.--28. 1. "MEM_BANK_ADDR_FLD,The address of the Memory Bank which data will be read from." newline rbitfld.long 0x0 19. "FLASH_COMMAND_CTRL_MEM_RESV2_FLD,Reserved" "0,1" newline bitfld.long 0x0 16.--18. "NB_OF_STIG_READ_BYTES_FLD,It defines the number of read bytes for the extended STIG." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x0 8.--15. 1. "MEM_BANK_READ_DATA_FLD,Last requested data from the STIG Memory Bank." newline hexmask.long.byte 0x0 2.--7. 1. "FLASH_COMMAND_CTRL_MEM_RESV3_FLD,Reserved" newline rbitfld.long 0x0 1. "MEM_BANK_REQ_IN_PROGRESS_FLD,Memory Bank data request in progress." "0,1" newline bitfld.long 0x0 0. "TRIGGER_MEM_BANK_REQ_FLD,Trigger the Memory Bank data request." "0,1" line.long 0x4 "FLASH_CMD_CTRL_REG,Flash Command Control Register" hexmask.long.byte 0x4 24.--31. 1. "CMD_OPCODE_FLD,Command Opcode: The command opcode field should be setup before triggering the command. For example 0x20 maps to SubSector Erase. Writing to the execute field (bit 0) of this register launches the command. NOTE : Using this approach to.." newline bitfld.long 0x4 23. "ENB_READ_DATA_FLD,Read Data Enable: Set to 1 if the command specified in the command opcode field (bits 31:24) requires read data bytes to be received from the device." "0,1" newline bitfld.long 0x4 20.--22. "NUM_RD_DATA_BYTES_FLD,Number of Read Data Bytes: Up to 8 data bytes may be read using this command. Set to 0 for 1 byte and 7 for 8 bytes." "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 19. "ENB_COMD_ADDR_FLD,Command Address Enable: Set to 1 if the command specified in bits 31:24 requires an address. This should be setup before triggering the command via writing a 1 to the execute field." "0,1" newline bitfld.long 0x4 18. "ENB_MODE_BIT_FLD,Mode Bit Enable: Set to 1 to ensure the mode bits as defined in the Mode Bit Configuration register are sent following the address bytes." "0,1" newline bitfld.long 0x4 16.--17. "NUM_ADDR_BYTES_FLD,Number of Address Bytes: Set to the number of address bytes required (the address itself is programmed in the FLASH COMMAND ADDRESS REGISTERS). This should be setup before triggering the command via bit 0 of this register. 2'b00 : 1.." "0,1,2,3" newline bitfld.long 0x4 15. "ENB_WRITE_DATA_FLD,Write Data Enable: Set to 1 if the command specified in the command opcode field requires write data bytes to be sent to the device." "0,1" newline bitfld.long 0x4 12.--14. "NUM_WR_DATA_BYTES_FLD,Number of Write Data Bytes: Up to 8 Data bytes may be written using this command Set to 0 for 1 byte 7 for 8 bytes." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x4 7.--11. 1. "NUM_DUMMY_CYCLES_FLD,Number of Dummy cycles: Set to the number of dummy cycles required. This should be setup before triggering the command via the execute field of this register." newline hexmask.long.byte 0x4 3.--6. 1. "FLASH_CMD_CTRL_RESV1_FLD,Reserved" newline bitfld.long 0x4 2. "STIG_MEM_BANK_EN_FLD,STIG Memory Bank enable bit." "0,1" newline rbitfld.long 0x4 1. "CMD_EXEC_STATUS_FLD,Command execution in progress." "0,1" newline bitfld.long 0x4 0. "CMD_EXEC_FLD,Execute the command." "0,1" line.long 0x8 "FLASH_CMD_ADDR_REG,Flash Command Address Register" hexmask.long 0x8 0.--31. 1. "ADDR_FLD,Command Address: This should be setup before triggering the command with execute field (bit 0) of the Flash Command Control register. It is the address used by the command specified in the opcode field (bits 31:24) of the Flash Command Control.." rgroup.long 0xA0++0x7 line.long 0x0 "FLASH_RD_DATA_LOWER_REG,Flash Command Read Data Register (Lower)" hexmask.long 0x0 0.--31. 1. "DATA_FLD,This is the data that is returned by the flash device for any status or configuration read operation carried out by triggering the event in the control register. The register will be valid when the polling bit in the control register is low." line.long 0x4 "FLASH_RD_DATA_UPPER_REG,Flash Command Read Data Register (Upper)" hexmask.long 0x4 0.--31. 1. "DATA_FLD,This is the data that is returned by the FLASH device for any status or configuration read operation carried out by triggering the event in the control register. The register will be valid when the polling bit in the control register is low." group.long 0xA8++0x13 line.long 0x0 "FLASH_WR_DATA_LOWER_REG,Flash Command Write Data Register (Lower)" hexmask.long 0x0 0.--31. 1. "DATA_FLD,Command Write Data Lower Byte: This is the command write data lower byte. This should be setup before triggering the command with execute field (bit 0) of the Flash Command Control register. It is the data that is to be written to the flash for.." line.long 0x4 "FLASH_WR_DATA_UPPER_REG,Flash Command Write Data Register (Upper)" hexmask.long 0x4 0.--31. 1. "DATA_FLD,Command Write Data Upper Byte: This is the command write data upper byte. This should be setup before triggering the command with execute field (bit 0) of the Flash Command Control register. It is the data that is to be written to the flash for.." line.long 0x8 "POLLING_FLASH_STATUS_REG,Polling Flash Status Register" hexmask.long.word 0x8 21.--31. 1. "DEVICE_STATUS_RSVD_FLD2,Reserved" newline hexmask.long.byte 0x8 16.--20. 1. "DEVICE_STATUS_NB_DUMMY,Number of dummy cycles for auto-polling" newline hexmask.long.byte 0x8 9.--15. 1. "DEVICE_STATUS_RSVD_FLD1,Reserved" newline rbitfld.long 0x8 8. "DEVICE_STATUS_VALID_FLD,Device Status Valid: This should be set when value in bits from 7 to 0 is valid." "0,1" newline hexmask.long.byte 0x8 0.--7. 1. "DEVICE_STATUS_FLD,Defines actual Status Register of Device" line.long 0xC "PHY_CONFIGURATION_REG,PHY Configuration Register" bitfld.long 0xC 31. "PHY_CONFIG_RESYNC_FLD,This bit is used for re-synchronisation delay lines to update them with values from TX DLL Delay and RX DLL Delay fields." "0,1" newline bitfld.long 0xC 30. "PHY_CONFIG_RESET_FLD,DLL Reset bit: This bit is used for reset of Delay Lines by software." "0,1" newline bitfld.long 0xC 29. "PHY_CONFIG_RX_DLL_BYPASS_FLD,RX DLL Bypass: This field determines id RX DLL is bypassed." "0,1" newline hexmask.long.byte 0xC 23.--28. 1. "PHY_CONFIG_RESV2_FLD,Reserved" newline hexmask.long.byte 0xC 16.--22. 1. "PHY_CONFIG_TX_DLL_DELAY_FLD,TX DLL Delay: This field determines the number of delay elements to insert on data path between ref_clk and spi_clk." newline hexmask.long.word 0xC 7.--15. 1. "PHY_CONFIG_RESV1_FLD,Reserved" newline hexmask.long.byte 0xC 0.--6. 1. "PHY_CONFIG_RX_DLL_DELAY_FLD,RX DLL Delay: This field determines the number of delay elements to insert on data path between ref_clk and rx_dll_clk." line.long 0x10 "PHY_MASTER_CONTROL_REG,PHY DLL Master Control Register" hexmask.long.byte 0x10 25.--31. 1. "PHY_MASTER_CONTROL_RESV3_FLD,Reserved" newline bitfld.long 0x10 24. "PHY_MASTER_LOCK_MODE_FLD,Determines if the master delay line locks on a full cycle or half cycle of delay." "0,1" newline bitfld.long 0x10 23. "PHY_MASTER_BYPASS_MODE_FLD,Controls the bypass mode of the master and slave DLLs." "0,1" newline bitfld.long 0x10 20.--22. "PHY_MASTER_PHASE_DETECT_SELECTOR_FLD,Selects the number of delay elements to be inserted between the phase detect flip-flops." "0,1,2,3,4,5,6,7" newline rbitfld.long 0x10 19. "PHY_MASTER_CONTROL_RESV2_FLD,Reserved" "0,1" newline bitfld.long 0x10 16.--18. "PHY_MASTER_NB_INDICATIONS_FLD,Holds the number of consecutive increment or decrement indications." "0,1,2,3,4,5,6,7" newline hexmask.long.word 0x10 7.--15. 1. "PHY_MASTER_CONTROL_RESV1_FLD,Reserved" newline hexmask.long.byte 0x10 0.--6. 1. "PHY_MASTER_INITIAL_DELAY_FLD,This value is the initial delay value for the DLL." rgroup.long 0xBC++0x7 line.long 0x0 "DLL_OBSERVABLE_LOWER_REG,DLL Observable Register Lower" hexmask.long.byte 0x0 24.--31. 1. "DLL_OBSERVABLE_LOWER_DLL_LOCK_INC_FLD,Holds the state of the cumulative dll_lock_inc register." newline hexmask.long.byte 0x0 16.--23. 1. "DLL_OBSERVABLE_LOWER_DLL_LOCK_DEC_FLD,Holds the state of the cumulative dll_lock_dec register." newline bitfld.long 0x0 15. "DLL_OBSERVABLE_LOWER_LOOPBACK_LOCK_FLD,This bit indicates that lock of loopback is done." "0,1" newline hexmask.long.byte 0x0 8.--14. 1. "DLL_OBSERVABLE_LOWER_LOCK_VALUE_FLD,Reports the DLL encoder value from the master DLL to the slave DLLs." newline hexmask.long.byte 0x0 3.--7. 1. "DLL_OBSERVABLE_LOWER_UNLOCK_COUNTER_FLD,Reports the number of increments or decrements required for the master DLL to complete the locking process." newline bitfld.long 0x0 1.--2. "DLL_OBSERVABLE_LOWER_LOCK_MODE_FLD,Defines the mode in which the DLL has achieved the lock." "0,1,2,3" newline bitfld.long 0x0 0. "DLL_OBSERVABLE_LOWER_DLL_LOCK_FLD,Indicates status of DLL." "0,1" line.long 0x4 "DLL_OBSERVABLE_UPPER_REG,DLL Observable Register Upper" hexmask.long.word 0x4 23.--31. 1. "DLL_OBSERVABLE_UPPER_RESV2_FLD,Reserved" newline hexmask.long.byte 0x4 16.--22. 1. "DLL_OBSERVABLE_UPPER_TX_DECODER_OUTPUT_FLD,Holds the encoded value for the TX delay line for this slice." newline hexmask.long.word 0x4 7.--15. 1. "DLL_OBSERVABLE_UPPER_RESV1_FLD,Reserved" newline hexmask.long.byte 0x4 0.--6. 1. "DLL_OBSERVABLE__UPPER_RX_DECODER_OUTPUT_FLD,Holds the encoded value for the RX delay line for this slice." group.long 0xE0++0x7 line.long 0x0 "OPCODE_EXT_LOWER_REG,Opcode Extension Register (Lower)" hexmask.long.byte 0x0 24.--31. 1. "EXT_READ_OPCODE_FLD,Supplement byte of any Read Opcode" newline hexmask.long.byte 0x0 16.--23. 1. "EXT_WRITE_OPCODE_FLD,Supplement byte of any Write Opcode" newline hexmask.long.byte 0x0 8.--15. 1. "EXT_POLL_OPCODE_FLD,Supplement byte of any Polling Opcode" newline hexmask.long.byte 0x0 0.--7. 1. "EXT_STIG_OPCODE_FLD,Supplement byte of any STIG Opcode" line.long 0x4 "OPCODE_EXT_UPPER_REG,Opcode Extension Register (Upper)" hexmask.long.byte 0x4 24.--31. 1. "WEL_OPCODE_FLD,First byte of any WEL Opcode" newline hexmask.long.byte 0x4 16.--23. 1. "EXT_WEL_OPCODE_FLD,Supplement byte of any WEL Opcode" newline hexmask.long.word 0x4 0.--15. 1. "OPCODE_EXT_UPPER_RESV1_FLD,Reserved" group.long 0xF0++0x3 line.long 0x0 "CUSTOM_CONF_REG,Custom Configuration Register" hexmask.long 0x0 5.--31. 1. "CUSTOM_CONF_RESV_FLD2,Reserved" newline bitfld.long 0x0 4. "PIPE_SMRT_ACC_FLD,PHY POP delay functionality" "0,1" newline hexmask.long.byte 0x0 0.--3. 1. "CUSTOM_CONF_RESV_FLD1,Reserved" rgroup.long 0xFC++0x3 line.long 0x0 "MODULE_ID_REG,Module ID Register" hexmask.long.byte 0x0 24.--31. 1. "FIX_PATCH_FLD,Fix/path number related to revision described by 3 LSBs of this register" newline hexmask.long.word 0x0 8.--23. 1. "MODULE_ID_FLD,Module/Revision ID number" newline hexmask.long.byte 0x0 3.--7. 1. "MODULE_ID_RESV_FLD,Reserved" newline bitfld.long 0x0 2. "HYPER_SUPPORT_FLD,HyperFlash Support" "0,1" newline bitfld.long 0x0 0.--1. "CONF_FLD,Configuration ID number: 0 : OCTAL + PHY Configuration 1 : OCTAL Configuration 2 : QUAD + PHY Configuration 3 : QUAD Configuration" "OCTAL + PHY Configuration,OCTAL Configuration,QUAD + PHY Configuration,QUAD Configuration" group.long 0x100++0x3 line.long 0x0 "HYPERFLASH_CONFIG_REG,HyperFlash Configuration Register" rbitfld.long 0x0 31. "HYPERFLASH_CONFIG_RESV3_FLD,Reserved" "0,1" newline bitfld.long 0x0 30. "TARGET_HYPERFLASH_STIG_FLD,Identifies the target of final STIG HyperFlash transaction as follows: 1'b0 = Memory Space 1'b1 = Register Space" "Memory Space 1'b1 = Register Space,?" newline bitfld.long 0x0 29. "BURST_TYPE_HYPERFLASH_STIG_FLD,Identifies the burst type of final STIG HyperFlash transaction" "0,1" newline hexmask.long.word 0x0 20.--28. 1. "HYPERFLASH_CONFIG_RESV2_FLD,Reserved" newline hexmask.long.byte 0x0 16.--19. 1. "HYPERFLASH_LAT_CODE_FLD,Identifies the latency code for HyperFlash" newline hexmask.long.word 0x0 1.--15. 1. "HYPERFLASH_CONFIG_RESV1_FLD,Reserved" newline bitfld.long 0x0 0. "HYPERFLASH_ENABLE_FLD,HyperFlash Mode enable bit" "0,1" group.long 0x110++0x3 line.long 0x0 "OSPI_MISC0,Misc configuration Register #0" newline bitfld.long 0x0 5. "CTL3,sample clocl polarity control for sclk_dlyd_i 0x1 - Invert sample clock sclk_dlyd_i 0x0 - sample clock sclk_dlyd_i not inverted" "sample clock sclk_dlyd_i not inverted,Invert sample clock sclk_dlyd_i" newline bitfld.long 0x0 4. "CTL2,DQS pad output enable When CTL0 is set 0x2 this bit should be enable to enable loopback path from internal sclk_out to DQS pad." "0,1" newline bitfld.long 0x0 2.--3. "CTL1,SCLK output logic control. 0x0 - orginal logic without any delay (Delay added by TX DLL) 0x1 - original logic (sclk_out) with dleay 1/4 cycle of SCLK (by ref_clk_2x fall edge) 0x2 - original logic (sclk_out) with delay 1/2 cycle of SCLk (by.." "orginal logic without any delay,original logic,original logic,original logic" newline bitfld.long 0x0 0.--1. "CTL0,loopback SCLK input logic control (sclk_dlyd). 0x0 - loopback from SCLK pad 0x1 - loopback from internal (sclk_out with delay selected by OSPI_MISC0.CTL1) 0x2 - loopback from DQS pad 0x3 - loopback from ref_clk_2x (for DFT test only)." "loopback from SCLK pad,loopback from internal,loopback from DQS pad,loopback from ref_clk_2x" repeat 3. (list 0x1 0x2 0x3 )(list 0x0 0x4 0x8 ) group.long ($2+0x114)++0x3 line.long 0x0 "OSPI_MISC$1,Misc Configuration Register #1" hexmask.long 0x0 0.--31. 1. "CTL,Reserved for future" repeat.end group.long 0x200++0x3 line.long 0x0 "HYPERFLASH_STIG_CONFIG_REG,HyperFlash STIG Configuration Register" hexmask.long.byte 0x0 27.--31. 1. "HYPERFLASH_STIG_CONFIG_REG_RESV0_FLD,Reserved" newline bitfld.long 0x0 24.--26. "HYPERFLASH_STIG_CONFIG_NB_PRE_TRAN_FLD,Identifies the number of STIG HyperFlash pre-transactions" "0,1,2,3,4,5,6,7" newline hexmask.long.word 0x0 13.--23. 1. "HYPERFLASH_STIG_CONFIG_REG_RESV1_FLD,Reserved" newline bitfld.long 0x0 12. "HYPERFLASH_STIG_PRE_TRAN_DATA7_SIZE_FLD,Identifies data size of STIG HyperFlash pre-transaction 7" "0,1" newline rbitfld.long 0x0 11. "HYPERFLASH_STIG_CONFIG_REG_RESV2_FLD,Reserved" "0,1" newline bitfld.long 0x0 10. "HYPERFLASH_STIG_PRE_TRAN_DATA6_SIZE_FLD,Identifies data size of STIG HyperFlash pre-transaction 6" "0,1" newline rbitfld.long 0x0 9. "HYPERFLASH_STIG_CONFIG_REG_RESV3_FLD,Reserved" "0,1" newline bitfld.long 0x0 8. "HYPERFLASH_STIG_PRE_TRAN_DATA5_SIZE_FLD,Identifies data size of STIG HyperFlash pre-transaction 5" "0,1" newline rbitfld.long 0x0 7. "HYPERFLASH_STIG_CONFIG_REG_RESV4_FLD,Reserved" "0,1" newline bitfld.long 0x0 6. "HYPERFLASH_STIG_PRE_TRAN_DATA4_SIZE_FLD,Identifies data size of STIG HyperFlash pre-transaction 4" "0,1" newline rbitfld.long 0x0 5. "HYPERFLASH_STIG_CONFIG_REG_RESV5_FLD,Reserved" "0,1" newline bitfld.long 0x0 4. "HYPERFLASH_STIG_PRE_TRAN_DATA3_SIZE_FLD,Identifies data size of STIG HyperFlash pre-transaction 3" "0,1" newline rbitfld.long 0x0 3. "HYPERFLASH_STIG_CONFIG_REG_RESV6_FLD,Reserved" "0,1" newline bitfld.long 0x0 2. "HYPERFLASH_STIG_PRE_TRAN_DATA2_SIZE_FLD,Identifies data size of STIG HyperFlash pre-transaction 2" "0,1" newline rbitfld.long 0x0 1. "HYPERFLASH_STIG_CONFIG_REG_RESV7_FLD,Reserved" "0,1" newline bitfld.long 0x0 0. "HYPERFLASH_STIG_PRE_TRAN_DATA1_SIZE_FLD,Identifies data size of STIG HyperFlash pre-transaction 1" "0,1" group.long 0x210++0x7 line.long 0x0 "HYPERFLASH_STIG_PRE_TRAN1_ADDRESS_REG,HyperFlash STIG Pre-transaction 1 Address Register" hexmask.long 0x0 0.--31. 1. "HYPERFLASH_STIG_PRE_TRAN1_ADDRESS_FLD,Identifies Address of HyperFlash STIG Pre-transaction 1" line.long 0x4 "HYPERFLASH_STIG_PRE_TRAN1_DATA_REG,HyperFlash STIG Pre-transaction 1 Data Register" hexmask.long 0x4 0.--31. 1. "HYPERFLASH_STIG_PRE_TRAN1_DATA_FLD,Identifies Data of HyperFlash STIG Pre-transaction 1" group.long 0x220++0x7 line.long 0x0 "HYPERFLASH_STIG_PRE_TRAN2_ADDRESS_REG,HyperFlash STIG Pre-transaction 2 Address Register" hexmask.long 0x0 0.--31. 1. "HYPERFLASH_STIG_PRE_TRAN2_ADDRESS_FLD,Identifies Address of HyperFlash STIG Pre-transaction 2" line.long 0x4 "HYPERFLASH_STIG_PRE_TRAN2_DATA_REG,HyperFlash STIG Pre-transaction 2 Data Register" hexmask.long 0x4 0.--31. 1. "HYPERFLASH_STIG_PRE_TRAN2_DATA_FLD,Identifies Data of HyperFlash STIG Pre-transaction 2" group.long 0x230++0x7 line.long 0x0 "HYPERFLASH_STIG_PRE_TRAN3_ADDRESS_REG,HyperFlash STIG Pre-transaction 3 Address Register" hexmask.long 0x0 0.--31. 1. "HYPERFLASH_STIG_PRE_TRAN3_ADDRESS_FLD,Identifies Address of HyperFlash STIG Pre-transaction 3" line.long 0x4 "HYPERFLASH_STIG_PRE_TRAN3_DATA_REG,HyperFlash STIG Pre-transaction 3 Data Register" hexmask.long 0x4 0.--31. 1. "HYPERFLASH_STIG_PRE_TRAN3_DATA_FLD,Identifies Data of HyperFlash STIG Pre-transaction 3" group.long 0x240++0x7 line.long 0x0 "HYPERFLASH_STIG_PRE_TRAN4_ADDRESS_REG,HyperFlash STIG Pre-transaction 4 Address Register" hexmask.long 0x0 0.--31. 1. "HYPERFLASH_STIG_PRE_TRAN4_ADDRESS_FLD,Identifies Address of HyperFlash STIG Pre-transaction 4" line.long 0x4 "HYPERFLASH_STIG_PRE_TRAN4_DATA_REG,HyperFlash STIG Pre-transaction 4 Data Register" hexmask.long 0x4 0.--31. 1. "HYPERFLASH_STIG_PRE_TRAN4_DATA_FLD,Identifies Data of HyperFlash STIG Pre-transaction 4" group.long 0x250++0x7 line.long 0x0 "HYPERFLASH_STIG_PRE_TRAN5_ADDRESS_REG,HyperFlash STIG Pre-transaction 5 Address Register" hexmask.long 0x0 0.--31. 1. "HYPERFLASH_STIG_PRE_TRAN5_ADDRESS_FLD,Identifies Address of HyperFlash STIG Pre-transaction 5" line.long 0x4 "HYPERFLASH_STIG_PRE_TRAN5_DATA_REG,HyperFlash STIG Pre-transaction 5 Data Register" hexmask.long 0x4 0.--31. 1. "HYPERFLASH_STIG_PRE_TRAN5_DATA_FLD,Identifies Data of HyperFlash STIG Pre-transaction 5" group.long 0x260++0x7 line.long 0x0 "HYPERFLASH_STIG_PRE_TRAN6_ADDRESS_REG,HyperFlash STIG Pre-transaction 6 Address Register" hexmask.long 0x0 0.--31. 1. "HYPERFLASH_STIG_PRE_TRAN6_ADDRESS_FLD,Identifies Address of HyperFlash STIG Pre-transaction 6" line.long 0x4 "HYPERFLASH_STIG_PRE_TRAN6_DATA_REG,HyperFlash STIG Pre-transaction 6 Data Register" hexmask.long 0x4 0.--31. 1. "HYPERFLASH_STIG_PRE_TRAN6_DATA_FLD,Identifies Data of HyperFlash STIG Pre-transaction 6" group.long 0x270++0x7 line.long 0x0 "HYPERFLASH_STIG_PRE_TRAN7_ADDRESS_REG,HyperFlash STIG Pre-transaction 7 Address Register" hexmask.long 0x0 0.--31. 1. "HYPERFLASH_STIG_PRE_TRAN7_ADDRESS_FLD,Identifies Address of HyperFlash STIG Pre-transaction 7" line.long 0x4 "HYPERFLASH_STIG_PRE_TRAN7_DATA_REG,HyperFlash STIG Pre-transaction 7 Data Register" hexmask.long 0x4 0.--31. 1. "HYPERFLASH_STIG_PRE_TRAN7_DATA_FLD,Identifies Data of HyperFlash STIG Pre-transaction 7" group.long 0x300++0x3 line.long 0x0 "HYPERFLASH_WRITE_CONFIG_REG,HyperFlash Write Configuration Register" hexmask.long.byte 0x0 27.--31. 1. "HYPERFLASH_WRITE_CONFIG_REG_RESV0_FLD,Reserved" newline bitfld.long 0x0 24.--26. "HYPERFLASH_WRITE_CONFIG_NB_PRE_TRAN_FLD,Identifies the number of Write HyperFlash pre-transactions" "0,1,2,3,4,5,6,7" newline hexmask.long.word 0x0 13.--23. 1. "HYPERFLASH_WRITE_CONFIG_REG_RESV1_FLD,Reserved" newline bitfld.long 0x0 12. "HYPERFLASH_WRITE_PRE_TRAN_DATA7_SIZE_FLD,Identifies data size of Write HyperFlash pre-transaction 7" "0,1" newline rbitfld.long 0x0 11. "HYPERFLASH_WRITE_CONFIG_REG_RESV2_FLD,Reserved" "0,1" newline bitfld.long 0x0 10. "HYPERFLASH_WRITE_PRE_TRAN_DATA6_SIZE_FLD,Identifies data size of Write HyperFlash pre-transaction 6" "0,1" newline rbitfld.long 0x0 9. "HYPERFLASH_WRITE_CONFIG_REG_RESV3_FLD,Reserved" "0,1" newline bitfld.long 0x0 8. "HYPERFLASH_WRITE_PRE_TRAN_DATA5_SIZE_FLD,Identifies data size of Write HyperFlash pre-transaction 5" "0,1" newline rbitfld.long 0x0 7. "HYPERFLASH_WRITE_CONFIG_REG_RESV4_FLD,Reserved" "0,1" newline bitfld.long 0x0 6. "HYPERFLASH_WRITE_PRE_TRAN_DATA4_SIZE_FLD,Identifies data size of Write HyperFlash pre-transaction 4" "0,1" newline rbitfld.long 0x0 5. "HYPERFLASH_WRITE_CONFIG_REG_RESV5_FLD,Reserved" "0,1" newline bitfld.long 0x0 4. "HYPERFLASH_WRITE_PRE_TRAN_DATA3_SIZE_FLD,Identifies data size of Write HyperFlash pre-transaction 3" "0,1" newline rbitfld.long 0x0 3. "HYPERFLASH_WRITE_CONFIG_REG_RESV6_FLD,Reserved" "0,1" newline bitfld.long 0x0 2. "HYPERFLASH_WRITE_PRE_TRAN_DATA2_SIZE_FLD,Identifies data size of Write HyperFlash pre-transaction 2" "0,1" newline rbitfld.long 0x0 1. "HYPERFLASH_WRITE_CONFIG_REG_RESV7_FLD,Reserved" "0,1" newline bitfld.long 0x0 0. "HYPERFLASH_WRITE_PRE_TRAN_DATA1_SIZE_FLD,Identifies data size of Write HyperFlash pre-transaction 1" "0,1" group.long 0x310++0x7 line.long 0x0 "HYPERFLASH_WRITE_PRE_TRAN1_ADDRESS_REG,HyperFlash Write Pre-transaction 1 Address Register" hexmask.long 0x0 0.--31. 1. "HYPERFLASH_WRITE_PRE_TRAN1_ADDRESS_FLD,Identifies Address of HyperFlash Write Pre-transaction 1" line.long 0x4 "HYPERFLASH_WRITE_PRE_TRAN1_DATA_REG,HyperFlash Write Pre-transaction 1 Data Register" hexmask.long 0x4 0.--31. 1. "HYPERFLASH_WRITE_PRE_TRAN1_DATA_FLD,Identifies Data of HyperFlash Write Pre-transaction 1" group.long 0x320++0x7 line.long 0x0 "HYPERFLASH_WRITE_PRE_TRAN2_ADDRESS_REG,HyperFlash Write Pre-transaction 2 Address Register" hexmask.long 0x0 0.--31. 1. "HYPERFLASH_WRITE_PRE_TRAN2_ADDRESS_FLD,Identifies Address of HyperFlash Write Pre-transaction 2" line.long 0x4 "HYPERFLASH_WRITE_PRE_TRAN2_DATA_REG,HyperFlash Write Pre-transaction 2 Data Register" hexmask.long 0x4 0.--31. 1. "HYPERFLASH_WRITE_PRE_TRAN2_DATA_FLD,Identifies Data of HyperFlash Write Pre-transaction 2" group.long 0x330++0x7 line.long 0x0 "HYPERFLASH_WRITE_PRE_TRAN3_ADDRESS_REG,HyperFlash Write Pre-transaction 3 Address Register" hexmask.long 0x0 0.--31. 1. "HYPERFLASH_WRITE_PRE_TRAN3_ADDRESS_FLD,Identifies Address of HyperFlash Write Pre-transaction 3" line.long 0x4 "HYPERFLASH_WRITE_PRE_TRAN3_DATA_REG,HyperFlash Write Pre-transaction 3 Data Register" hexmask.long 0x4 0.--31. 1. "HYPERFLASH_WRITE_PRE_TRAN3_DATA_FLD,Identifies Data of HyperFlash Write Pre-transaction 3" group.long 0x340++0x7 line.long 0x0 "HYPERFLASH_WRITE_PRE_TRAN4_ADDRESS_REG,HyperFlash Write Pre-transaction 4 Address Register" hexmask.long 0x0 0.--31. 1. "HYPERFLASH_WRITE_PRE_TRAN4_ADDRESS_FLD,Identifies Address of HyperFlash Write Pre-transaction 4" line.long 0x4 "HYPERFLASH_WRITE_PRE_TRAN4_DATA_REG,HyperFlash Write Pre-transaction 4 Data Register" hexmask.long 0x4 0.--31. 1. "HYPERFLASH_WRITE_PRE_TRAN4_DATA_FLD,Identifies Data of HyperFlash Write Pre-transaction 4" group.long 0x350++0x7 line.long 0x0 "HYPERFLASH_WRITE_PRE_TRAN5_ADDRESS_REG,HyperFlash Write Pre-transaction 5 Address Register" hexmask.long 0x0 0.--31. 1. "HYPERFLASH_WRITE_PRE_TRAN5_ADDRESS_FLD,Identifies Address of HyperFlash Write Pre-transaction 5" line.long 0x4 "HYPERFLASH_WRITE_PRE_TRAN5_DATA_REG,HyperFlash Write Pre-transaction 5 Data Register" hexmask.long 0x4 0.--31. 1. "HYPERFLASH_WRITE_PRE_TRAN5_DATA_FLD,Identifies Data of HyperFlash Write Pre-transaction 5" group.long 0x360++0x7 line.long 0x0 "HYPERFLASH_WRITE_PRE_TRAN6_ADDRESS_REG,HyperFlash Write Pre-transaction 6 Address Register" hexmask.long 0x0 0.--31. 1. "HYPERFLASH_WRITE_PRE_TRAN6_ADDRESS_FLD,Identifies Address of HyperFlash Write Pre-transaction 6" line.long 0x4 "HYPERFLASH_WRITE_PRE_TRAN6_DATA_REG,HyperFlash Write Pre-transaction 6 Data Register" hexmask.long 0x4 0.--31. 1. "HYPERFLASH_WRITE_PRE_TRAN6_DATA_FLD,Identifies Data of HyperFlash Write Pre-transaction 6" group.long 0x370++0x7 line.long 0x0 "HYPERFLASH_WRITE_PRE_TRAN7_ADDRESS_REG,HyperFlash Write Pre-transaction 7 Address Register" hexmask.long 0x0 0.--31. 1. "HYPERFLASH_WRITE_PRE_TRAN7_ADDRESS_FLD,Identifies Address of HyperFlash Write Pre-transaction 7" line.long 0x4 "HYPERFLASH_WRITE_PRE_TRAN7_DATA_REG,HyperFlash Write Pre-transaction 7 Data Register" hexmask.long 0x4 0.--31. 1. "HYPERFLASH_WRITE_PRE_TRAN7_DATA_FLD,Identifies Data of HyperFlash Write Pre-transaction 7" group.long 0x400++0x3 line.long 0x0 "HYPERFLASH_READ_CONFIG_REG,HyperFlash Read Configuration Register" hexmask.long.byte 0x0 27.--31. 1. "HYPERFLASH_READ_CONFIG_REG_RESV0_FLD,Reserved" newline bitfld.long 0x0 24.--26. "HYPERFLASH_READ_CONFIG_NB_PRE_TRAN_FLD,Identifies the number of Read HyperFlash pre-transactions" "0,1,2,3,4,5,6,7" newline hexmask.long.word 0x0 13.--23. 1. "HYPERFLASH_READ_CONFIG_REG_RESV1_FLD,Reserved" newline bitfld.long 0x0 12. "HYPERFLASH_READ_PRE_TRAN_DATA7_SIZE_FLD,Identifies data size of Read HyperFlash pre-transaction 7" "0,1" newline rbitfld.long 0x0 11. "HYPERFLASH_READ_CONFIG_REG_RESV2_FLD,Reserved" "0,1" newline bitfld.long 0x0 10. "HYPERFLASH_READ_PRE_TRAN_DATA6_SIZE_FLD,Identifies data size of Read HyperFlash pre-transaction 6" "0,1" newline rbitfld.long 0x0 9. "HYPERFLASH_READ_CONFIG_REG_RESV3_FLD,Reserved" "0,1" newline bitfld.long 0x0 8. "HYPERFLASH_READ_PRE_TRAN_DATA5_SIZE_FLD,Identifies data size of Read HyperFlash pre-transaction 5" "0,1" newline rbitfld.long 0x0 7. "HYPERFLASH_READ_CONFIG_REG_RESV4_FLD,Reserved" "0,1" newline bitfld.long 0x0 6. "HYPERFLASH_READ_PRE_TRAN_DATA4_SIZE_FLD,Identifies data size of Read HyperFlash pre-transaction 4" "0,1" newline rbitfld.long 0x0 5. "HYPERFLASH_READ_CONFIG_REG_RESV5_FLD,Reserved" "0,1" newline bitfld.long 0x0 4. "HYPERFLASH_READ_PRE_TRAN_DATA3_SIZE_FLD,Identifies data size of Read HyperFlash pre-transaction 3" "0,1" newline rbitfld.long 0x0 3. "HYPERFLASH_READ_CONFIG_REG_RESV6_FLD,Reserved" "0,1" newline bitfld.long 0x0 2. "HYPERFLASH_READ_PRE_TRAN_DATA2_SIZE_FLD,Identifies data size of Read HyperFlash pre-transaction 2" "0,1" newline rbitfld.long 0x0 1. "HYPERFLASH_READ_CONFIG_REG_RESV7_FLD,Reserved" "0,1" newline bitfld.long 0x0 0. "HYPERFLASH_READ_PRE_TRAN_DATA1_SIZE_FLD,Identifies data size of Read HyperFlash pre-transaction 1" "0,1" group.long 0x410++0x7 line.long 0x0 "HYPERFLASH_READ_PRE_TRAN1_ADDRESS_REG,HyperFlash Read Pre-transaction 1 Address Register" hexmask.long 0x0 0.--31. 1. "HYPERFLASH_READ_PRE_TRAN1_ADDRESS_FLD,Identifies Address of HyperFlash Read Pre-transaction 1" line.long 0x4 "HYPERFLASH_READ_PRE_TRAN1_DATA_REG,HyperFlash Read Pre-transaction 1 Data Register" hexmask.long 0x4 0.--31. 1. "HYPERFLASH_READ_PRE_TRAN1_DATA_FLD,Identifies Data of HyperFlash Read Pre-transaction 1" group.long 0x420++0x7 line.long 0x0 "HYPERFLASH_READ_PRE_TRAN2_ADDRESS_REG,HyperFlash Read Pre-transaction 2 Address Register" hexmask.long 0x0 0.--31. 1. "HYPERFLASH_READ_PRE_TRAN2_ADDRESS_FLD,Identifies Address of HyperFlash Read Pre-transaction 2" line.long 0x4 "HYPERFLASH_READ_PRE_TRAN2_DATA_REG,HyperFlash Read Pre-transaction 2 Data Register" hexmask.long 0x4 0.--31. 1. "HYPERFLASH_READ_PRE_TRAN2_DATA_FLD,Identifies Data of HyperFlash Read Pre-transaction 2" group.long 0x430++0x7 line.long 0x0 "HYPERFLASH_READ_PRE_TRAN3_ADDRESS_REG,HyperFlash Read Pre-transaction 3 Address Register" hexmask.long 0x0 0.--31. 1. "HYPERFLASH_READ_PRE_TRAN3_ADDRESS_FLD,Identifies Address of HyperFlash Read Pre-transaction 3" line.long 0x4 "HYPERFLASH_READ_PRE_TRAN3_DATA_REG,HyperFlash Read Pre-transaction 3 Data Register" hexmask.long 0x4 0.--31. 1. "HYPERFLASH_READ_PRE_TRAN3_DATA_FLD,Identifies Data of HyperFlash Read Pre-transaction 3" group.long 0x440++0x7 line.long 0x0 "HYPERFLASH_READ_PRE_TRAN4_ADDRESS_REG,HyperFlash Read Pre-transaction 4 Address Register" hexmask.long 0x0 0.--31. 1. "HYPERFLASH_READ_PRE_TRAN4_ADDRESS_FLD,Identifies Address of HyperFlash Read Pre-transaction 4" line.long 0x4 "HYPERFLASH_READ_PRE_TRAN4_DATA_REG,HyperFlash Read Pre-transaction 4 Data Register" hexmask.long 0x4 0.--31. 1. "HYPERFLASH_READ_PRE_TRAN4_DATA_FLD,Identifies Data of HyperFlash Read Pre-transaction 4" group.long 0x450++0x7 line.long 0x0 "HYPERFLASH_READ_PRE_TRAN5_ADDRESS_REG,HyperFlash Read Pre-transaction 5 Address Register" hexmask.long 0x0 0.--31. 1. "HYPERFLASH_READ_PRE_TRAN5_ADDRESS_FLD,Identifies Address of HyperFlash Read Pre-transaction 5" line.long 0x4 "HYPERFLASH_READ_PRE_TRAN5_DATA_REG,HyperFlash Read Pre-transaction 5 Data Register" hexmask.long 0x4 0.--31. 1. "HYPERFLASH_READ_PRE_TRAN5_DATA_FLD,Identifies Data of HyperFlash Read Pre-transaction 5" group.long 0x460++0x7 line.long 0x0 "HYPERFLASH_READ_PRE_TRAN6_ADDRESS_REG,HyperFlash Read Pre-transaction 6 Address Register" hexmask.long 0x0 0.--31. 1. "HYPERFLASH_READ_PRE_TRAN6_ADDRESS_FLD,Identifies Address of HyperFlash Read Pre-transaction 6" line.long 0x4 "HYPERFLASH_READ_PRE_TRAN6_DATA_REG,HyperFlash Read Pre-transaction 6 Data Register" hexmask.long 0x4 0.--31. 1. "HYPERFLASH_READ_PRE_TRAN6_DATA_FLD,Identifies Data of HyperFlash Read Pre-transaction 6" group.long 0x470++0x7 line.long 0x0 "HYPERFLASH_READ_PRE_TRAN7_ADDRESS_REG,HyperFlash Read Pre-transaction 7 Address Register" hexmask.long 0x0 0.--31. 1. "HYPERFLASH_READ_PRE_TRAN7_ADDRESS_FLD,Identifies Address of HyperFlash Read Pre-transaction 7" line.long 0x4 "HYPERFLASH_READ_PRE_TRAN7_DATA_REG,HyperFlash Read Pre-transaction 7 Data Register" hexmask.long 0x4 0.--31. 1. "HYPERFLASH_READ_PRE_TRAN7_DATA_FLD,Identifies Data of HyperFlash Read Pre-transaction 7" group.long 0x500++0x3 line.long 0x0 "HYPERFLASH_POLLING_CONFIG_REG,HyperFlash Polling Configuration Register" hexmask.long.byte 0x0 27.--31. 1. "HYPERFLASH_POLLING_CONFIG_REG_RESV0_FLD,Reserved" newline bitfld.long 0x0 24.--26. "HYPERFLASH_POLLING_CONFIG_NB_PRE_TRAN_FLD,Identifies the number of Polling HyperFlash pre-transactions" "0,1,2,3,4,5,6,7" newline hexmask.long.word 0x0 13.--23. 1. "HYPERFLASH_POLLING_CONFIG_REG_RESV1_FLD,Reserved" newline bitfld.long 0x0 12. "HYPERFLASH_POLLING_PRE_TRAN_DATA7_SIZE_FLD,Identifies data size of Polling HyperFlash pre-transaction 7" "0,1" newline rbitfld.long 0x0 11. "HYPERFLASH_POLLING_CONFIG_REG_RESV2_FLD,Reserved" "0,1" newline bitfld.long 0x0 10. "HYPERFLASH_POLLING_PRE_TRAN_DATA6_SIZE_FLD,Identifies data size of Polling HyperFlash pre-transaction 6" "0,1" newline rbitfld.long 0x0 9. "HYPERFLASH_POLLING_CONFIG_REG_RESV3_FLD,Reserved" "0,1" newline bitfld.long 0x0 8. "HYPERFLASH_POLLING_PRE_TRAN_DATA5_SIZE_FLD,Identifies data size of Polling HyperFlash pre-transaction 5" "0,1" newline rbitfld.long 0x0 7. "HYPERFLASH_POLLING_CONFIG_REG_RESV4_FLD,Reserved" "0,1" newline bitfld.long 0x0 6. "HYPERFLASH_POLLING_PRE_TRAN_DATA4_SIZE_FLD,Identifies data size of Polling HyperFlash pre-transaction 4" "0,1" newline rbitfld.long 0x0 5. "HYPERFLASH_POLLING_CONFIG_REG_RESV5_FLD,Reserved" "0,1" newline bitfld.long 0x0 4. "HYPERFLASH_POLLING_PRE_TRAN_DATA3_SIZE_FLD,Identifies data size of Polling HyperFlash pre-transaction 3" "0,1" newline rbitfld.long 0x0 3. "HYPERFLASH_POLLING_CONFIG_REG_RESV6_FLD,Reserved" "0,1" newline bitfld.long 0x0 2. "HYPERFLASH_POLLING_PRE_TRAN_DATA2_SIZE_FLD,Identifies data size of Polling HyperFlash pre-transaction 2" "0,1" newline rbitfld.long 0x0 1. "HYPERFLASH_POLLING_CONFIG_REG_RESV7_FLD,Reserved" "0,1" newline bitfld.long 0x0 0. "HYPERFLASH_POLLING_PRE_TRAN_DATA1_SIZE_FLD,Identifies data size of Polling HyperFlash pre-transaction 1" "0,1" group.long 0x510++0x7 line.long 0x0 "HYPERFLASH_POLLING_PRE_TRAN1_ADDRESS_REG,HyperFlash Polling Pre-transaction 1 Address Register" hexmask.long 0x0 0.--31. 1. "HYPERFLASH_POLLING_PRE_TRAN1_ADDRESS_FLD,Identifies Address of HyperFlash Polling Pre-transaction 1" line.long 0x4 "HYPERFLASH_POLLING_PRE_TRAN1_DATA_REG,HyperFlash Polling Pre-transaction 1 Data Register" hexmask.long 0x4 0.--31. 1. "HYPERFLASH_POLLING_PRE_TRAN1_DATA_FLD,Identifies Data of HyperFlash Polling Pre-transaction 1" group.long 0x520++0x7 line.long 0x0 "HYPERFLASH_POLLING_PRE_TRAN2_ADDRESS_REG,HyperFlash Polling Pre-transaction 2 Address Register" hexmask.long 0x0 0.--31. 1. "HYPERFLASH_POLLING_PRE_TRAN2_ADDRESS_FLD,Identifies Address of HyperFlash Polling Pre-transaction 2" line.long 0x4 "HYPERFLASH_POLLING_PRE_TRAN2_DATA_REG,HyperFlash Polling Pre-transaction 2 Data Register" hexmask.long 0x4 0.--31. 1. "HYPERFLASH_POLLING_PRE_TRAN2_DATA_FLD,Identifies Data of HyperFlash Polling Pre-transaction 2" group.long 0x530++0x7 line.long 0x0 "HYPERFLASH_POLLING_PRE_TRAN3_ADDRESS_REG,HyperFlash Polling Pre-transaction 3 Address Register" hexmask.long 0x0 0.--31. 1. "HYPERFLASH_POLLING_PRE_TRAN3_ADDRESS_FLD,Identifies Address of HyperFlash Polling Pre-transaction 3" line.long 0x4 "HYPERFLASH_POLLING_PRE_TRAN3_DATA_REG,HyperFlash Polling Pre-transaction 3 Data Register" hexmask.long 0x4 0.--31. 1. "HYPERFLASH_POLLING_PRE_TRAN3_DATA_FLD,Identifies Data of HyperFlash Polling Pre-transaction 3" group.long 0x540++0x7 line.long 0x0 "HYPERFLASH_POLLING_PRE_TRAN4_ADDRESS_REG,HyperFlash Polling Pre-transaction 4 Address Register" hexmask.long 0x0 0.--31. 1. "HYPERFLASH_POLLING_PRE_TRAN4_ADDRESS_FLD,Identifies Address of HyperFlash Polling Pre-transaction 4" line.long 0x4 "HYPERFLASH_POLLING_PRE_TRAN4_DATA_REG,HyperFlash Polling Pre-transaction 4 Data Register" hexmask.long 0x4 0.--31. 1. "HYPERFLASH_POLLING_PRE_TRAN4_DATA_FLD,Identifies Data of HyperFlash Polling Pre-transaction 4" group.long 0x550++0x7 line.long 0x0 "HYPERFLASH_POLLING_PRE_TRAN5_ADDRESS_REG,HyperFlash Polling Pre-transaction 5 Address Register" hexmask.long 0x0 0.--31. 1. "HYPERFLASH_POLLING_PRE_TRAN5_ADDRESS_FLD,Identifies Address of HyperFlash Polling Pre-transaction 5" line.long 0x4 "HYPERFLASH_POLLING_PRE_TRAN5_DATA_REG,HyperFlash Polling Pre-transaction 5 Data Register" hexmask.long 0x4 0.--31. 1. "HYPERFLASH_POLLING_PRE_TRAN5_DATA_FLD,Identifies Data of HyperFlash Polling Pre-transaction 5" group.long 0x560++0x7 line.long 0x0 "HYPERFLASH_POLLING_PRE_TRAN6_ADDRESS_REG,HyperFlash Polling Pre-transaction 6 Address Register" hexmask.long 0x0 0.--31. 1. "HYPERFLASH_POLLING_PRE_TRAN6_ADDRESS_FLD,Identifies Address of HyperFlash Polling Pre-transaction 6" line.long 0x4 "HYPERFLASH_POLLING_PRE_TRAN6_DATA_REG,HyperFlash Polling Pre-transaction 6 Data Register" hexmask.long 0x4 0.--31. 1. "HYPERFLASH_POLLING_PRE_TRAN6_DATA_FLD,Identifies Data of HyperFlash Polling Pre-transaction 6" group.long 0x570++0x7 line.long 0x0 "HYPERFLASH_POLLING_PRE_TRAN7_ADDRESS_REG,HyperFlash Polling Pre-transaction 7 Address Register" hexmask.long 0x0 0.--31. 1. "HYPERFLASH_POLLING_PRE_TRAN7_ADDRESS_FLD,Identifies Address of HyperFlash Polling Pre-transaction 7" line.long 0x4 "HYPERFLASH_POLLING_PRE_TRAN7_DATA_REG,HyperFlash Polling Pre-transaction 7 Data Register" hexmask.long 0x4 0.--31. 1. "HYPERFLASH_POLLING_PRE_TRAN7_DATA_FLD,Identifies Data of HyperFlash Polling Pre-transaction 7" group.long 0xA00++0x13 line.long 0x0 "ASF_INT_STATUS_REG,ASF Interrupt Status Register" hexmask.long 0x0 7.--31. 1. "ASF_INT_STATUS_RESV1_FLD,Reserved" newline bitfld.long 0x0 6. "ASF_INTEGRITY_ERR_FLD,Integrity error interrupt" "0,1" newline bitfld.long 0x0 5. "ASF_PROTOCOL_ERR_FLD,Protocol error interrupt" "0,1" newline bitfld.long 0x0 4. "ASF_TRANS_TO_ERR_FLD,Transaction timeouts interrupt" "0,1" newline bitfld.long 0x0 3. "ASF_CSR_ERR_FLD,Configuration and status registers error interrupt" "0,1" newline bitfld.long 0x0 2. "ASF_DAP_ERR_FLD,Data and address paths error interrupt" "0,1" newline bitfld.long 0x0 1. "ASF_SRAM_UNCORR_ERR_FLD,SRAM uncorrectable error interrupt" "0,1" newline bitfld.long 0x0 0. "ASF_SRAM_CORR_ERR_FLD,SRAM correctable error interrupt" "0,1" line.long 0x4 "ASF_INT_RAW_STATUS_REG,ASF Interrupt Raw Status Register" hexmask.long 0x4 7.--31. 1. "ASF_INT_RAW_STATUS_RESV1_FLD,Reserved" newline bitfld.long 0x4 6. "ASF_INTEGRITY_ERR_FLD,Integrity error interrupt" "0,1" newline bitfld.long 0x4 5. "ASF_PROTOCOL_ERR_FLD,Protocol error interrupt" "0,1" newline bitfld.long 0x4 4. "ASF_TRANS_TO_ERR_FLD,Transaction timeouts interrupt" "0,1" newline bitfld.long 0x4 3. "ASF_CSR_ERR_FLD,Configuration and status registers error interrupt" "0,1" newline bitfld.long 0x4 2. "ASF_DAP_ERR_FLD,Data and address paths error interrupt" "0,1" newline bitfld.long 0x4 1. "ASF_SRAM_UNCORR_ERR_FLD,SRAM uncorrectable error interrupt" "0,1" newline bitfld.long 0x4 0. "ASF_SRAM_CORR_ERR_FLD,SRAM correctable error interrupt" "0,1" line.long 0x8 "ASF_INT_MASK_REG,The ASF interrupt mask register indicating which interrupt bits in the ASF Interrupt Status Register are masked" hexmask.long 0x8 7.--31. 1. "ASF_INT_MASK_RESV1_FLD,Reserved" newline bitfld.long 0x8 6. "ASF_INTEGRITY_ERR_MASK_FLD,Mask bit for integrity error interrupt" "0,1" newline bitfld.long 0x8 5. "ASF_PROTOCOL_ERR_MASK_FLD,Mask bit for protocol error interrupt" "0,1" newline bitfld.long 0x8 4. "ASF_TRANS_TO_ERR_MASK_FLD,Mask bit for transaction timeouts interrupt" "0,1" newline bitfld.long 0x8 3. "ASF_CSR_ERR_MASK_FLD,Mask bit for configuration and status registers error interrupt" "0,1" newline bitfld.long 0x8 2. "ASF_DAP_ERR_MASK_FLD,Mask bit for data and address paths error interrupt" "0,1" newline bitfld.long 0x8 1. "ASF_SRAM_UNCORR_ERR_MASK_FLD,Mask bit for SRAM uncorrectable error interrupt" "0,1" newline bitfld.long 0x8 0. "ASF_SRAM_CORR_ERR_MASK_FLD,Mask bit for SRAM correctable error interrupt" "0,1" line.long 0xC "ASF_INT_TEST_REG,The ASF interrupt test register emulate hardware even" hexmask.long 0xC 7.--31. 1. "ASF_INT_TEST_RESV1_FLD,Reserved" newline bitfld.long 0xC 6. "ASF_INTEGRITY_ERR_TEST_FLD,Test bit for integrity error interrupt" "0,1" newline bitfld.long 0xC 5. "ASF_PROTOCOL_ERR_TEST_FLD,Test bit for protocol error interrupt" "0,1" newline bitfld.long 0xC 4. "ASF_TRANS_TO_ERR_TEST_FLD,Test bit for transaction timeouts interrupt" "0,1" newline bitfld.long 0xC 3. "ASF_CSR_ERR_TEST_FLD,Test bit for configuration and status registers error interrupt" "0,1" newline bitfld.long 0xC 2. "ASF_DAP_ERR_TEST_FLD,Test bit for data and address paths error interrupt" "0,1" newline bitfld.long 0xC 1. "ASF_SRAM_UNCORR_ERR_TEST_FLD,Test bit form SRAM uncorrectable error interrupt" "0,1" newline bitfld.long 0xC 0. "ASF_SRAM_CORR_ERR_TEST_FLD,Test bit for SRAM correctable error interupt" "0,1" line.long 0x10 "ASF_FATAL_NONFATAL_SELECT_REG,The fatal or non-fatal interrupt registers selects whether a fatal or non-fatal interrupt is triggered." hexmask.long 0x10 7.--31. 1. "ASF_FATAL_NONFATAL_SELECT_RESV1_FLD,Reserved" newline bitfld.long 0x10 6. "ASF_INTEGRITY_ERR_SEL_FLD,Enable integrity interrupt as fatal" "0,1" newline bitfld.long 0x10 5. "ASF_PROTOCOL_ERR_SEL_FLD,Enable protocol interrupt as fatal" "0,1" newline bitfld.long 0x10 4. "ASF_TRANS_TO_ERR_SEL_FLD,Enable transaction timeouts interrupt as fatal" "0,1" newline bitfld.long 0x10 3. "ASF_CSR_ERR_SEL_FLD,Enable configuration and status registers interrupts as fatal" "0,1" newline bitfld.long 0x10 2. "ASF_DAP_ERR_SEL_FLD,Enable data and address paths interrupt as fatal" "0,1" newline bitfld.long 0x10 1. "ASF_SRAM_UNCORR_ERR_SEL_FLD,Enable SRAM uncorrectable interrupt as fatal" "0,1" newline bitfld.long 0x10 0. "ASF_SRAM_CORR_ERR_SEL_FLD,Enable SRAM correctable interrupt as fatal" "0,1" rgroup.long 0xA20++0x7 line.long 0x0 "ASF_SRAM_CORR_FAULT_STATUS_REG,Status register for SRAM correctable fault' field{ desc = 'Last SRAM address that generated fault" line.long 0x4 "ASF_SRAM_UNCORR_FAULT_STATUS_REG,Status register for SRAM uncorrectable fault" hexmask.long.word 0x4 16.--31. 1. "ASF_SRAM_UNCORR_FAULT_STATUS_RESV1_FLD,Reserved" newline hexmask.long.word 0x4 0.--15. 1. "ASF_SRAM_UNCORR_FAULT_ADDR_FLD,Last SRAM address that generated" group.long 0xA28++0x3 line.long 0x0 "ASF_SRAM_FAULT_STATS_REG,Statics register for SRAM faults" hexmask.long.word 0x0 16.--31. 1. "ASF_SRAM_FAULT_UNCORR_STATS_FLS,Count of number of uncorrectable errors" newline hexmask.long.word 0x0 0.--15. 1. "ASF_SRAM_FAULT_CORR_STATS_FLD,Count of number of correctable errors" group.long 0xA30++0xB line.long 0x0 "ASF_TRANS_TO_CTRL_REG,Control register to configure the ASF transaction timeout monitors" bitfld.long 0x0 31. "ASF_TRANS_TO_EN_FLD,Enable transaction timeout monitoring" "0,1" newline hexmask.long.word 0x0 16.--30. 1. "ASF_TRANS_TO_CTRL_RESV1_FLD,Reserved" newline hexmask.long.word 0x0 0.--15. 1. "ASF_TRANS_TO_CTRL_FLD,Time value to use for transaction timeout monitor" line.long 0x4 "ASF_TRANS_TO_FAULT_MASK_REG,Control Register to mask out ASF transaction timeout faults from triggering interrupts" hexmask.long 0x4 1.--31. 1. "ASF_TRANS_TO_FAULT_STATUS_RESV1_FLD,Reserved" newline bitfld.long 0x4 0. "ASF_TRANS_TO_FAULT_MASK_FLD,Mask for AHB ASF transaction timeout fault source" "0,1" line.long 0x8 "ASF_TRANS_TO_FAULT_STATUS_REG,Status register for transaction timeouts fault" hexmask.long 0x8 1.--31. 1. "ASF_TRANS_TO_FAULT_STATUS_RESV1_FLD,Reserved" newline bitfld.long 0x8 0. "ASF_TRANS,Status bit for transaction timeouts faults" "0,1" group.long 0xA40++0x7 line.long 0x0 "ASF_PROTOCOL_FAULT_MASK_REG,Control register to mask out ASF Protocol faults from triggering interrupts" hexmask.long.word 0x0 19.--31. 1. "ASF_PROTOCOL_FAULT_MASK_RESV2_FLD,Reserved" newline bitfld.long 0x0 18. "ASF_PROTOCOL_FAULT_MASK_FLASH_CFG_FLD,Mask bit for Tri state enable fault" "0,1" newline bitfld.long 0x0 17. "ASF_PROTOCOL_FAULD_MASK_CS_FLD,Mask bit for Tri state enable fault" "0,1" newline bitfld.long 0x0 16. "ASF_PROTOCOL_FAULT_MASK_TRI_FLD,Mask bit for Tri state enable fault" "0,1" newline hexmask.long.word 0x0 4.--15. 1. "ASF_PROTOCOL_FAULT_MASK_RESV1_FLD,Reserved" newline bitfld.long 0x0 3. "ASF_PROTOCOL_FAULT_MASK_ECC_FLD,Mask bit for ECC failure" "0,1" newline bitfld.long 0x0 2. "ASF_PROTOCOL_MASK_TX_CRC_FLD,Mask bit for Polling expiration error" "0,1" newline bitfld.long 0x0 1. "ASF_PROTOCOL_FAULT_MASK_RX_CRC_FLD,Mask bit for Polling expiration error" "0,1" newline bitfld.long 0x0 0. "ASF_PROTOCOL_FAULT_MASK_POLL_FLD,Mask bit for Polling expiration error" "0,1" line.long 0x4 "ASF_PROTOCOL_FAULT_STATUS_REG,Status register for protocol faults" hexmask.long.word 0x4 19.--31. 1. "ASF_PROTOCOL_FAULT_STATUS_RESV2_FLD,Reserved" newline bitfld.long 0x4 18. "ASF_PROTOCOL_FAULT_STATUS_FLASH_CFG_FLD,Flash Configuration failure" "0,1" newline bitfld.long 0x4 17. "ASF_PROTOCOL_FAULT_STATUS_CS_FLD,#CS fault" "0,1" newline bitfld.long 0x4 16. "ASF_PROTOCOL_FAULT_STATUS_TRI_FLD,Tri state enable fault" "0,1" newline hexmask.long.word 0x4 4.--15. 1. "ASF_PROTOCOL_FAULT_STATUS_RESV1_FLD,Reserved" newline bitfld.long 0x4 3. "ASF_PROTOCOL_FAULT_STATUS_ECC,ECC failure" "0,1" newline bitfld.long 0x4 2. "ASF_PROTOCOL_FAULT_STATUS_TX_CRC,TX CRC chunk was broken" "0,1" newline bitfld.long 0x4 1. "ASF_PROTOCOL_FAULT_STATUS_RX_CRC_FLD,RX CRC data error" "0,1" newline bitfld.long 0x4 0. "ASF_PROTOCOL_FAULT_STATUS_POLL_FLD,Polling expiration error" "0,1" tree.end tree "OSPI2" base ad:0xF06D0000 group.long 0x0++0x2B line.long 0x0 "CONFIG_REG,Octal-SPI Configuration Register" rbitfld.long 0x0 31. "IDLE_FLD,Serial interface and low level SPI pipeline is IDLE: This is a STATUS read-only bit. Note this is a retimed signal so there will be some inherent delay on the generation of this status signal." "0,1" newline bitfld.long 0x0 30. "DUAL_BYTE_OPCODE_EN_FLD,Dual-byte Opcode Mode enable bit This bit is to be set in case the target Flash Device supports dual byte opcode (i.e. Macronix MX25). It is applicable for Octal I/O Mode or Protocol only so should be set back to low if the device.." "0,1" newline bitfld.long 0x0 29. "CRC_ENABLE_FLD,CRC enable bit This bit is to be set in case the target Flash Device supports CRC (Macronix MX25). It is applicable for Octal DDR Protocol only so should be set back to low if the device is configured to work in another SPI Mode." "0,1" newline bitfld.long 0x0 28. "FLIPPER_ENABLE_FLD,Flip enable bit This bit is to be set in case the target Flash Device supports data slices swapped in order of D1 D0 D3 D2 etc. It is applicable for DTR-OPI Mode of Macronix MX25 devices." "0,1" newline rbitfld.long 0x0 26.--27. "CONFIG_RESV2_FLD,Reserved" "0,1,2,3" newline bitfld.long 0x0 25. "PIPELINE_PHY_FLD,Pipeline PHY Mode enable: This bit is relevant only for configuration with PHY Module. It should be asserted to '1' between consecutive PHY pipeline reads transfers and de-asserted to '0' otherwise." "0,1" newline bitfld.long 0x0 24. "ENABLE_DTR_PROTOCOL_FLD,Enable DTR Protocol: This bit should be set if device is configured to work in DTR protocol." "0,1" newline bitfld.long 0x0 23. "ENABLE_AHB_DECODER_FLD,Enable AHB Decoder: Value=0 : Active slave is selected based on Peripheral Chip Select Lines (bits [13:10]). Value=1 Active slave is selected based on actual AHB address (the partition for each device is calculated with respect to.." "Active slave is selected based on Peripheral..,?" newline hexmask.long.byte 0x0 19.--22. 1. "MSTR_BAUD_DIV_FLD,Master Mode Baud Rate Divisor: SPI baud rate = (master reference clock) baud_rate_divisor" newline bitfld.long 0x0 18. "ENTER_XIP_MODE_IMM_FLD,Enter XIP Mode immediately: Value=0 : If XIP is enabled then setting to 0 will cause the controller to exit XIP mode on the next READ instruction. Value=1 : Operate the device in XIP mode immediately Use this register when the.." "If XIP is enabled,Operate the device in XIP mode immediately Use.." newline bitfld.long 0x0 17. "ENTER_XIP_MODE_FLD,Enter XIP Mode on next READ: Value=0 : If XIP is enabled then setting to 0 will cause the controller to exit XIP mode on the next READ instruction. Value=1 : If XIP is disabled then setting to ?1? will inform the controller that the.." "If XIP is enabled,If XIP is disabled" newline bitfld.long 0x0 16. "ENB_AHB_ADDR_REMAP_FLD,Enable AHB Address Re-mapping: (Direct Access Mode Only) When set to 1 the incoming AHB address will be adapted and sent to the FLASH device as (address + N) where N is the value stored in the remap address register." "0,1" newline bitfld.long 0x0 15. "ENB_DMA_IF_FLD,Enable DMA Peripheral Interface: Set to 1 to enable the DMA handshaking logic. When enabled the controller will trigger DMA transfer requests via the DMA peripheral interface. Set to 0 to disable" "0,1" newline bitfld.long 0x0 14. "WR_PROT_FLASH_FLD,Write Protect Flash Pin: Set to drive the Write Protect pin of the FLASH device. This is resynchronized to the generated memory clock as necessary." "0,1" newline hexmask.long.byte 0x0 10.--13. 1. "PERIPH_CS_LINES_FLD,Peripheral Chip Select Lines: Peripheral chip select lines If pdec = 0 ss[3:0] are output thus: ss[3:0] n_ss_out[3:0] xxx0 1110 xx01 1101 x011 1011 0111 0111 1111 1111 (no peripheral selected) else ss[3:0] directly drives n_ss_out[3:0]" newline bitfld.long 0x0 9. "PERIPH_SEL_DEC_FLD,Peripheral select decode: 0 : only 1 of 4 selects n_ss_out[3:0] is active 1 : allow external 4-to-16 decode (n_ss_out = ss)" "only 1 of 4 selects n_ss_out[3:0] is active,allow external 4-to-16 decode" newline bitfld.long 0x0 8. "ENB_LEGACY_IP_MODE_FLD,Legacy IP Mode Enable: 0 : Use Direct Access Controller/Indirect Access Controller 1 : legacy Mode is enabled. In this mode any write to the controller via the AHB interface is serialized and sent to the FLASH device. Any valid.." "Use Direct Access Controller/Indirect Access..,legacy Mode is enabled" newline bitfld.long 0x0 7. "ENB_DIR_ACC_CTLR_FLD,Enable Direct Access Controller: 0 : disable the Direct Access Controller once current transfer of the data word (FF_W) is complete. 1 : enable the Direct Access Controller When the Direct Access Controller and Indirect Access.." "disable the Direct Access Controller once..,enable the Direct Access Controller When the.." newline bitfld.long 0x0 6. "RESET_CFG_FLD,RESET pin configuration: 0 = RESET feature on DQ3 pin of the device 1 = RESET feature on dedicated pin of the device (controlling of 5th bit influences on reset_out output)" "RESET feature on DQ3 pin of the device,RESET feature on dedicated pin of the device" newline bitfld.long 0x0 5. "RESET_PIN_FLD,Set to drive the RESET pin of the FLASH device and reset for de-activation of the RESET pin feature" "0,1" newline bitfld.long 0x0 4. "HOLD_PIN_FLD,Set to drive the HOLD pin of the FLASH device and reset for de-activation of the HOLD pin feature" "0,1" newline bitfld.long 0x0 3. "PHY_MODE_ENABLE_FLD,PHY mode enable: When enabled the controller is informed that PHY Module is to be used for handling SPI transfers. This bit is relevant only for configuration with PHY Module. Note: - When changing this bit field software should.." "0,1" newline bitfld.long 0x0 2. "SEL_CLK_PHASE_FLD,Select Clock Phase: Selects whether the clock is in an active or inactive phase outside the SPI word. 0 : the SPI clock is active outside the word 1 : the SPI clock is inactive outside the word" "the SPI clock is active outside the word,the SPI clock is inactive outside the word" newline bitfld.long 0x0 1. "SEL_CLK_POL_FLD,Clock polarity outside SPI word: 0 : the SPI clock is quiescent low 1 : the SPI clock is quiescent high" "the SPI clock is quiescent low,the SPI clock is quiescent high" newline bitfld.long 0x0 0. "ENB_SPI_FLD,Octal-SPI Enable: 0 : disable the Octal-SPI once current transfer of the data word (FF_W) is complete. 1 : enable the Octal-SPI when spi_enable = 0 all output enables are inactive and all pins are set to input mode." "disable the Octal-SPI,enable the Octal-SPI" line.long 0x4 "DEV_INSTR_RD_CONFIG_REG,Device Read Instruction Configuration Register" rbitfld.long 0x4 29.--31. "RD_INSTR_RESV5_FLD,Reserved" "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x4 24.--28. 1. "DUMMY_RD_CLK_CYCLES_FLD,Dummy Read Clock Cycles: Number of dummy clock cycles required by device for read instruction." newline rbitfld.long 0x4 21.--23. "RD_INSTR_RESV4_FLD,Reserved" "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 20. "MODE_BIT_ENABLE_FLD,Mode Bit Enable: Set this field to 1 to ensure that the mode bits as defined in the Mode Bit Configuration register are sent following the address bytes." "0,1" newline rbitfld.long 0x4 18.--19. "RD_INSTR_RESV3_FLD,Reserved" "0,1,2,3" newline bitfld.long 0x4 16.--17. "DATA_XFER_TYPE_EXT_MODE_FLD,Data Transfer Type for Standard SPI modes: 0 : SIO mode data is shifted to the device on DQ0 only and from the device on DQ1 only 1 : Used for Dual Input/Output instructions. For data transfers DQ0 and DQ1 are used as both.." "SIO mode data is shifted to the device on DQ0..,Used for Dual Input/Output instructions,Used for Quad Input/Output instructions,Used for Quad Input/Output instructions" newline rbitfld.long 0x4 14.--15. "RD_INSTR_RESV2_FLD,Reserved" "0,1,2,3" newline bitfld.long 0x4 12.--13. "ADDR_XFER_TYPE_STD_MODE_FLD,Address Transfer Type for Standard SPI modes: 0 : Addresses can be shifted to the device on DQ0 only 1 : Addresses can be shifted to the device on DQ0 and DQ1 only 2 : Addresses can be shifted to the device on DQ0 DQ1 DQ2.." "Addresses can be shifted to the device on DQ0 only,Addresses can be shifted to the device on DQ0..,Addresses can be shifted to the device on DQ0,Addresses can be shifted to the device on DQ[7:0]" newline bitfld.long 0x4 11. "PRED_DIS_FLD,Predicted Read Disable Bit: Disable generation of predicted read when doing read accesses using Direct Mode" "0,1" newline bitfld.long 0x4 10. "DDR_EN_FLD,DDR Enable: This is to inform that opcode from rd_opcode_non_xip_fld is compliant with one of the DDR READ Commands" "0,1" newline bitfld.long 0x4 8.--9. "INSTR_TYPE_FLD,Instruction Type: 0 : Use Standard SPI mode (instruction always shifted into the device on DQ0 only) 1 : Use DIO-SPI mode (Instructions Address and Data always sent on DQ0 and DQ1) 2 : Use QIO-SPI mode (Instructions Address and Data.." "Use Standard SPI mode,Use DIO-SPI mode,Use QIO-SPI mode,Use Octal-IO-SPI mode" newline hexmask.long.byte 0x4 0.--7. 1. "RD_OPCODE_NON_XIP_FLD,Read Opcode in non-XIP mode: Read Opcode to use when not in XIP mode" line.long 0x8 "DEV_INSTR_WR_CONFIG_REG,Device Write Instruction Configuration Register" rbitfld.long 0x8 29.--31. "WR_INSTR_RESV4_FLD,Reserved" "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x8 24.--28. 1. "DUMMY_WR_CLK_CYCLES_FLD,Dummy Write Clock Cycles: Number of dummy clock cycles required by device for write instruction." newline hexmask.long.byte 0x8 18.--23. 1. "WR_INSTR_RESV3_FLD,Reserved" newline bitfld.long 0x8 16.--17. "DATA_XFER_TYPE_EXT_MODE_FLD,Data Transfer Type for Standard SPI modes: 0 : SIO mode data is shifted to the device on DQ0 only and from the device on DQ1 only 1 : Used for Dual Input/Output instructions. For data transfers DQ0 and DQ1 are used as both.." "SIO mode data is shifted to the device on DQ0..,Used for Dual Input/Output instructions,Used for Quad Input/Output instructions,Used for Octal Input/Output instructions" newline rbitfld.long 0x8 14.--15. "WR_INSTR_RESV2_FLD,Reserved" "0,1,2,3" newline bitfld.long 0x8 12.--13. "ADDR_XFER_TYPE_STD_MODE_FLD,Address Transfer Type for Standard SPI modes: 0 : Addresses can be shifted to the device on DQ0 only 1 : Addresses can be shifted to the device on DQ0 and DQ1 only 2 : Addresses can be shifted to the device on DQ0 DQ1 DQ2.." "Addresses can be shifted to the device on DQ0 only,Addresses can be shifted to the device on DQ0..,Addresses can be shifted to the device on DQ0,Addresses can be shifted to the device on DQ[7:0]" newline rbitfld.long 0x8 9.--11. "WR_INSTR_RESV1_FLD,Reserved" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 8. "WEL_DIS_FLD,WEL Disable: This is to turn off automatic issuing of WEL Command before write operation for DAC or INDAC" "0,1" newline hexmask.long.byte 0x8 0.--7. 1. "WR_OPCODE_FLD,Write Opcode" line.long 0xC "DEV_DELAY_REG,Octal-SPI Device Delay Register: This register is used to introduce relative delays into the generation of the master output signals. All timings are defined in cycles of the SPI REFERENCE CLOCK/ext_clk. defined in this table as SPI master.." hexmask.long.byte 0xC 24.--31. 1. "D_NSS_FLD,Clock Delay for Chip Select Deassert: Delay in master reference clocks for the length that the master mode chip select outputs are de-asserted between transactions. The minimum delay is always SCLK period to ensure the chip select is never.." newline hexmask.long.byte 0xC 16.--23. 1. "D_BTWN_FLD,Clock Delay for Chip Select Deactivation: Delay in master reference clocks between one chip select being de-activated and the activation of another. This is used to ensure a quiet period between the selection of two different slaves and.." newline hexmask.long.byte 0xC 8.--15. 1. "D_AFTER_FLD,Clock Delay for Last Transaction Bit: Delay in master reference clocks between last bit of current transaction and deasserting the device chip select (n_ss_out). By default the chip select will be deasserted on the cycle following the.." newline hexmask.long.byte 0xC 0.--7. 1. "D_INIT_FLD,Clock Delay with n_ss_out: Delay in master reference clocks between setting n_ss_out low and first bit transfer." line.long 0x10 "RD_DATA_CAPTURE_REG,Read Data Capture Register" hexmask.long.word 0x10 20.--31. 1. "RD_DATA_RESV3_FLD,Reserved" newline hexmask.long.byte 0x10 16.--19. 1. "DDR_READ_DELAY_FLD,DDR read delay: Delay the transmitted data by the programmed number of ref_clk cycles.This field is only relevant when DDR Read Command is executed. Otherwise can be ignored." newline hexmask.long.byte 0x10 9.--15. 1. "RD_DATA_RESV2_FLD,Reserved" newline bitfld.long 0x10 8. "DQS_ENABLE_FLD,DQS enable bit: If enabled signal from DQS input is driven into RX DLL and is used for data capturing in PHY Mode rather than internally generated gated ref_clk.." "0,1" newline rbitfld.long 0x10 6.--7. "RD_DATA_RESV1_FLD,Reserved" "0,1,2,3" newline bitfld.long 0x10 5. "SAMPLE_EDGE_SEL_FLD,Sample edge selection: Choose edge on which data outputs from flash memory will be sampled" "0,1" newline hexmask.long.byte 0x10 1.--4. 1. "DELAY_FLD,Read Delay: Delay the read data capturing logic by the programmed number of ref_clk cycles" newline bitfld.long 0x10 0. "BYPASS_FLD,Bypass the adapted loopback clock circuit" "0,1" line.long 0x14 "DEV_SIZE_CONFIG_REG,Device Size Configuration Register" rbitfld.long 0x14 29.--31. "DEV_SIZE_RESV_FLD,Reserved" "0,1,2,3,4,5,6,7" newline bitfld.long 0x14 27.--28. "MEM_SIZE_ON_CS3_FLD,Size of Flash Device connected to CS[3] pin: Value=00 : size of 512Mb. Value=01 : size of 1Gb. Value=10 : size of 2Gb. Value=11 : size of 4Gb." "size of 512Mb,size of 1Gb,?,?" newline bitfld.long 0x14 25.--26. "MEM_SIZE_ON_CS2_FLD,Size of Flash Device connected to CS[2] pin: Value=00 : size of 512Mb. Value=01 : size of 1Gb. Value=10 : size of 2Gb. Value=11 : size of 4Gb." "size of 512Mb,size of 1Gb,?,?" newline bitfld.long 0x14 23.--24. "MEM_SIZE_ON_CS1_FLD,Size of Flash Device connected to CS[1] pin: Value=00 : size of 512Mb. Value=01 : size of 1Gb. Value=10 : size of 2Gb. Value=11 : size of 4Gb." "size of 512Mb,size of 1Gb,?,?" newline bitfld.long 0x14 21.--22. "MEM_SIZE_ON_CS0_FLD,Size of Flash Device connected to CS[0] pin: Value=00 : size of 512Mb. Value=01 : size of 1Gb. Value=10 : size of 2Gb. Value=11 : size of 4Gb." "size of 512Mb,size of 1Gb,?,?" newline hexmask.long.byte 0x14 16.--20. 1. "BYTES_PER_SUBSECTOR_FLD,Number of bytes per Block. This is required by the controller for performing the write protection logic. The number of bytes per block must be a power of 2 number." newline hexmask.long.word 0x14 4.--15. 1. "BYTES_PER_DEVICE_PAGE_FLD,Number of bytes per device page. This is required by the controller for performing FLASH writes up to and across page boundaries." newline hexmask.long.byte 0x14 0.--3. 1. "NUM_ADDR_BYTES_FLD,Number of address bytes. A value of 0 indicates 1 byte." line.long 0x18 "SRAM_PARTITION_CFG_REG,SRAM Partition Configuration Register" hexmask.long.tbyte 0x18 8.--31. 1. "SRAM_PARTITION_RESV_FLD,Reserved" newline hexmask.long.byte 0x18 0.--7. 1. "ADDR_FLD,Indirect Read Partition Size: Defines the size of the indirect read partition in the SRAM in units of SRAM locations. By default half of the SRAM is reserved for indirect read operation and half for indirect write. The size of this register.." line.long 0x1C "IND_AHB_ADDR_TRIGGER_REG,Indirect AHB Address Trigger Register" hexmask.long 0x1C 0.--31. 1. "ADDR_FLD,This is the base address that will be used by the AHB controller. When the incoming AHB read access address matches a range of addresses from this trigger address to the trigger address + 15 then the AHB request will be completed by fetching.." line.long 0x20 "DMA_PERIPH_CONFIG_REG,DMA Peripheral Configuration Register" hexmask.long.tbyte 0x20 12.--31. 1. "DMA_PERIPH_RESV2_FLD,Reserved" newline hexmask.long.byte 0x20 8.--11. 1. "NUM_BURST_REQ_BYTES_FLD,Number of Burst Bytes: Number of bytes in a burst type request on the DMA peripheral request. A programmed value of 0 represents a single byte. This should be setup before starting the indirect read or write operation. The actual.." newline hexmask.long.byte 0x20 4.--7. 1. "DMA_PERIPH_RESV1_FLD,Reserved" newline hexmask.long.byte 0x20 0.--3. 1. "NUM_SINGLE_REQ_BYTES_FLD,Number of Single Bytes: Number of bytes in a single type request on the DMA peripheral request. A programmed value of 0 represents a single byte. This should be setup before starting the indirect read or write operation. The.." line.long 0x24 "REMAP_ADDR_REG,Remap Address Register" hexmask.long 0x24 0.--31. 1. "VALUE_FLD,This register is used to remap an incoming AHB address to a different address used by the FLASH device." line.long 0x28 "MODE_BIT_CONFIG_REG,Mode Bit Configuration Register" hexmask.long.byte 0x28 24.--31. 1. "RX_CRC_DATA_LOW_FLD,RX CRC data (lower) The first CRC byte returned after RX data chunk." newline hexmask.long.byte 0x28 16.--23. 1. "RX_CRC_DATA_UP_FLD,RX CRC data (upper) The second CRC byte returned after RX data chunk." newline bitfld.long 0x28 15. "CRC_OUT_ENABLE_FLD,CRC# output enable bit When enabled the controller expects the Flash Device to toggle CRC data on both SPI clock edges in CRC->CRC# sequence and calculates CRC compliance accordingly." "0,1" newline hexmask.long.byte 0x28 11.--14. 1. "MODE_BIT_RESV1_FLD,Reserved" newline bitfld.long 0x28 8.--10. "CHUNK_SIZE_FLD,It defines size of chunk after which CRC data is expected to show up on the SPI interface for write and read data transfers." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x28 0.--7. 1. "MODE_FLD,These are the 8 mode bits that are sent to the device following the address bytes if mode bit transmission has been enabled." rgroup.long 0x2C++0x3 line.long 0x0 "SRAM_FILL_REG,SRAM Fill Register" hexmask.long.word 0x0 16.--31. 1. "SRAM_FILL_INDAC_WRITE_FLD,SRAM Fill Level (Indirect Write Partition): Identifies the current fill level of the SRAM Indirect Write partition" newline hexmask.long.word 0x0 0.--15. 1. "SRAM_FILL_INDAC_READ_FLD,SRAM Fill Level (Indirect Read Partition): Identifies the current fill level of the SRAM Indirect Read partition" group.long 0x30++0x17 line.long 0x0 "TX_THRESH_REG,TX Threshold Register" hexmask.long 0x0 5.--31. 1. "TX_THRESH_RESV_FLD,Reserved" newline hexmask.long.byte 0x0 0.--4. 1. "LEVEL_FLD,Defines the level at which the small TX FIFO not full interrupt is generated" line.long 0x4 "RX_THRESH_REG,RX Threshold Register" hexmask.long 0x4 5.--31. 1. "RX_THRESH_RESV_FLD,Reserved" newline hexmask.long.byte 0x4 0.--4. 1. "LEVEL_FLD,Defines the level at which the small RX FIFO not empty interrupt is generated" line.long 0x8 "WRITE_COMPLETION_CTRL_REG,Write Completion Control Register: This register defines how the controller will poll the device following a write transfer" hexmask.long.byte 0x8 24.--31. 1. "POLL_REP_DELAY_FLD,Defines additional delay for maintain Chip Select de-asserted during auto-polling phase" newline hexmask.long.byte 0x8 16.--23. 1. "POLL_COUNT_FLD,Defines the number of times the controller should expect to see a true result from the polling in successive reads of the device register." newline bitfld.long 0x8 15. "ENABLE_POLLING_EXP_FLD,Set to '1' for enabling auto-polling expiration." "0,1" newline bitfld.long 0x8 14. "DISABLE_POLLING_FLD,This switches off the automatic polling function" "0,1" newline bitfld.long 0x8 13. "POLLING_POLARITY_FLD,Defines the polling polarity. If '1' then the write transfer to the device will be complete if the polled bit is equal to '1'. If '0' then the write transfer to the device will be complete if the polled bit is equal to '0'." "0,1" newline rbitfld.long 0x8 12. "WR_COMP_CTRL_RESV1_FLD,Reserved" "0,1" newline bitfld.long 0x8 11. "POLLING_ADDR_EN_FLD,Enables address phase of auto-polling (Read Status) command." "0,1" newline bitfld.long 0x8 8.--10. "POLLING_BIT_INDEX_FLD,Defines the bit index that should be polled. A value of 010 means that bit 2 of the returned data will be polled for.A value of 111 means that bit 7 of the returned data will be polled for." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x8 0.--7. 1. "OPCODE_FLD,Defines the opcode that should be issued by the controller when it is automatically polling for device program completion. This command is issued followed all device write operations. By default this will poll the standard device STATUS.." line.long 0xC "NO_OF_POLLS_BEF_EXP_REG,Polling Expiration Register" hexmask.long 0xC 0.--31. 1. "NO_OF_POLLS_BEF_EXP_FLD,Number of polls cycles before expiration" line.long 0x10 "IRQ_STATUS_REG,Interrupt Status Register: The status fields in this register are set when the described event occurs and the interrupt is enabled in the mask register. When any of these bit fields are set. the interrupt output is asserted high. The.." hexmask.long.word 0x10 21.--31. 1. "IRQ_STAT_RESV_FLD,Reserved" newline bitfld.long 0x10 20. "HYPER_INT_FLD,HyperFlash interrupt This interrupt informs the system that Flash Device reported interrupt on its INT# output" "0,1" newline bitfld.long 0x10 19. "ECC_FAIL_FLD,ECC failure This interrupt informs the system that Flash Device reported ECC error." "0,1" newline bitfld.long 0x10 18. "TX_CRC_CHUNK_BRK_FLD,TX CRC chunk was broken This interrupt informs the system that program page SPI transfer was discontinued somewhere inside the chunk." "0,1" newline bitfld.long 0x10 17. "RX_CRC_DATA_VAL_FLD,RX CRC data valid New RX CRC data was captured from Flash Device" "0,1" newline bitfld.long 0x10 16. "RX_CRC_DATA_ERR_FLD,RX CRC data error CRC data from Flash Device does not correspond to the one dynamically calculated by the controller." "0,1" newline rbitfld.long 0x10 15. "IRQ_STAT_RESV1_FLD,Reserved" "0,1" newline bitfld.long 0x10 14. "STIG_REQ_INT_FLD,The controller is ready for getting another STIG request." "0,1" newline bitfld.long 0x10 13. "POLL_EXP_INT_FLD,The maximum number of programmed polls cycles is expired" "0,1" newline bitfld.long 0x10 12. "INDRD_SRAM_FULL_FLD,Indirect Read Partition overflow: Indirect Read Partition of SRAM is full and unable to immediately complete indirect operation" "0,1" newline bitfld.long 0x10 11. "RX_FIFO_FULL_FLD,Small RX FIFO full: Current FIFO status can be ignored in non-SPI legacy mode 0 : FIFO is not full 1 : FIFO is full" "FIFO is not full,FIFO is full" newline bitfld.long 0x10 10. "RX_FIFO_NOT_EMPTY_FLD,Small RX FIFO not empty: Current FIFO status can be ignored in non-SPI legacy mode 0 : FIFO has less than RX THRESHOLD entries 1 : FIFO has >= THRESHOLD entries" "FIFO has less than RX THRESHOLD entries,FIFO has >= THRESHOLD entries" newline bitfld.long 0x10 9. "TX_FIFO_FULL_FLD,Small TX FIFO full: Current FIFO status can be ignored in non-SPI legacy mode 0 : FIFO is not full 1 : FIFO is full" "FIFO is not full,FIFO is full" newline bitfld.long 0x10 8. "TX_FIFO_NOT_FULL_FLD,Small TX FIFO not full: Current FIFO status can be ignored in non-SPI legacy mode 0 : FIFO has >= THRESHOLD entries 1 : FIFO has less than THRESHOLD entries" "FIFO has >= THRESHOLD entries,FIFO has less than THRESHOLD entries" newline bitfld.long 0x10 7. "RECV_OVERFLOW_FLD,Receive Overflow: This should only occur in Legacy SPI mode. Set if an attempt is made to push the RX FIFO when it is full. This bit is reset only by a system reset and cleared only when this register is read. If a new push to the RX.." "no overflow has been detected,an overflow has occurred" newline bitfld.long 0x10 6. "INDIRECT_XFER_LEVEL_BREACH_FLD,Indirect Transfer Watermark Level Breached" "0,1" newline bitfld.long 0x10 5. "ILLEGAL_ACCESS_DET_FLD,Illegal AHB access has been detected. AHB wrapping bursts and the use of SPLIT/RETRY accesses will cause this error interrupt to trigger." "0,1" newline bitfld.long 0x10 4. "PROT_WR_ATTEMPT_FLD,Write to protected area was attempted and rejected." "0,1" newline bitfld.long 0x10 3. "INDIRECT_TRANSFER_REJECT_FLD,Indirect operation was requested but could not be accepted. Two indirect operations already in storage." "0,1" newline bitfld.long 0x10 2. "INDIRECT_OP_DONE_FLD,Indirect Operation Complete: Controller has completed last triggered indirect operation" "0,1" newline bitfld.long 0x10 1. "UNDERFLOW_DET_FLD,Underflow Detected: 0 : no underflow has been detected 1 : underflow is detected and an attempt to transfer data is made when the small TX FIFO is empty. This may occur when AHB write data is being supplied too slowly to keep up with.." "no underflow has been detected,underflow is detected and an attempt to transfer.." newline bitfld.long 0x10 0. "MODE_M_FAIL_FLD,Mode M Failure: Mode M failure indicates the voltage on pin n_ss_in is inconsistent with the SPI mode. Set =1 if n_ss_in is low in master mode (multi-master contention). These conditions will clear the spi_enable bit and disable the SPI." "no mode fault has been detected,a mode fault has occurred" line.long 0x14 "IRQ_MASK_REG,Interrupt Mask: 0 : the interrupt for the corresponding interrupt status register bit is disabled. 1 : the interrupt for the corresponding interrupt status register bit is enabled." hexmask.long.word 0x14 21.--31. 1. "IRQ_MASK_RESV_FLD,Reserved" newline bitfld.long 0x14 20. "HYPER_INT_MASK_FLD,HyperFlash interrupt Mask" "0,1" newline bitfld.long 0x14 19. "ECC_FAIL_MASK_FLD,ECC failure Mask" "0,1" newline bitfld.long 0x14 18. "TX_CRC_CHUNK_BRK_MASK_FLD,TX CRC chunk was broken Mask" "0,1" newline bitfld.long 0x14 17. "RX_CRC_DATA_VAL_MASK_FLD,RX CRC data valid Mask" "0,1" newline bitfld.long 0x14 16. "RX_CRC_DATA_ERR_MASK_FLD,RX CRC data error Mask" "0,1" newline rbitfld.long 0x14 15. "IRQ_MASK_RESV1_FLD,Reserved" "0,1" newline bitfld.long 0x14 14. "STIG_REQ_MASK_FLD,STIG request completion Mask" "0,1" newline bitfld.long 0x14 13. "POLL_EXP_INT_MASK_FLD,Polling expiration detected Mask" "0,1" newline bitfld.long 0x14 12. "INDRD_SRAM_FULL_MASK_FLD,Indirect Read Partition overflow mask" "0,1" newline bitfld.long 0x14 11. "RX_FIFO_FULL_MASK_FLD,Small RX FIFO full Mask" "0,1" newline bitfld.long 0x14 10. "RX_FIFO_NOT_EMPTY_MASK_FLD,Small RX FIFO not empty Mask" "0,1" newline bitfld.long 0x14 9. "TX_FIFO_FULL_MASK_FLD,Small TX FIFO full Mask" "0,1" newline bitfld.long 0x14 8. "TX_FIFO_NOT_FULL_MASK_FLD,Small TX FIFO not full Mask" "0,1" newline bitfld.long 0x14 7. "RECV_OVERFLOW_MASK_FLD,Receive Overflow Mask" "0,1" newline bitfld.long 0x14 6. "INDIRECT_XFER_LEVEL_BREACH_MASK_FLD,Transfer Watermark Breach Mask" "0,1" newline bitfld.long 0x14 5. "ILLEGAL_ACCESS_DET_MASK_FLD,Illegal Access Detected Mask" "0,1" newline bitfld.long 0x14 4. "PROT_WR_ATTEMPT_MASK_FLD,Protected Area Write Attempt Mask" "0,1" newline bitfld.long 0x14 3. "INDIRECT_TRANSFER_REJECT_MASK_FLD,Indirect Read Reject Mask" "0,1" newline bitfld.long 0x14 2. "INDIRECT_OP_DONE_MASK_FLD,Indirect Complete Mask" "0,1" newline bitfld.long 0x14 1. "UNDERFLOW_DET_MASK_FLD,Underflow Detected Mask" "0,1" newline bitfld.long 0x14 0. "MODE_M_FAIL_MASK_FLD,Mode M Failure Mask" "0,1" group.long 0x50++0xB line.long 0x0 "LOWER_WR_PROT_REG,Lower Write Protection Register" hexmask.long 0x0 0.--31. 1. "SUBSECTOR_FLD,The block number that defines the lower block in the range of blocks that is to be locked from writing. The definition of a block in terms of number of bytes is programmable via the Device Size Configuration register." line.long 0x4 "UPPER_WR_PROT_REG,Upper Write Protection Register" hexmask.long 0x4 0.--31. 1. "SUBSECTOR_FLD,The block number that defines the upper block in the range of blocks that is to be locked from writing. The definition of a block in terms of number of bytes is programmable via the Device Size Configuration register." line.long 0x8 "WR_PROT_CTRL_REG,Write Protection Control Register" hexmask.long 0x8 2.--31. 1. "WR_PROT_CTRL_RESV_FLD,Reserved" newline bitfld.long 0x8 1. "ENB_FLD,Write Protection Enable Bit: When set to 1 any AHB write access with an address within the protection region defined in the lower and upper write protection registers is rejected. An AHB error response is generated and an interrupt source.." "0,1" newline bitfld.long 0x8 0. "INV_FLD,Write Protection Inversion Bit: When set to 1 the protection region defined in the lower and upper write protection registers is inverted meaning it is the region that the system is permitted to write to. When set to 0 the protection region.." "0,1" group.long 0x60++0x23 line.long 0x0 "INDIRECT_READ_XFER_CTRL_REG,Indirect Read Transfer Control Register" hexmask.long.tbyte 0x0 8.--31. 1. "INDIR_RD_XFER_RESV_FLD,Reserved" newline rbitfld.long 0x0 6.--7. "NUM_IND_OPS_DONE_FLD,This field contains the number of indirect operations which have been completed. This is used in conjunction with the indirect completion status field (bit 5). It is incremented by hardware when an indirect operation has completed." "0,1,2,3" newline bitfld.long 0x0 5. "IND_OPS_DONE_STATUS_FLD,Indirect Completion Status: This field is set to 1 when an indirect operation has completed. Write a 1 to this field to clear it." "0,1" newline rbitfld.long 0x0 4. "RD_QUEUED_FLD,Two indirect read operations have been queued" "0,1" newline bitfld.long 0x0 3. "SRAM_FULL_FLD,SRAM Full: SRAM full and unable to immediately complete an indirect operation. Write a 1 to this field to clear it.\'; indirect operation (status)" "0,1" newline rbitfld.long 0x0 2. "RD_STATUS_FLD,Indirect Read Status: Indirect read operation in progress (status)" "0,1" newline bitfld.long 0x0 1. "CANCEL_FLD,Cancel Indirect Read: Writing a 1 to this bit will cancel all ongoing indirect read operations." "0,1" newline bitfld.long 0x0 0. "START_FLD,Start Indirect Read: Writing a 1 to this bit will trigger an indirect read operation. The assumption is that the indirect start address and the indirect number of bytes register is setup before triggering the indirect read operation." "0,1" line.long 0x4 "INDIRECT_READ_XFER_WATERMARK_REG,Indirect Read Transfer Watermark Register" hexmask.long 0x4 0.--31. 1. "LEVEL_FLD,Watermark Value: This represents the minimum fill level of the SRAM before a DMA peripheral access is permitted. When the SRAM fill level passes the watermark an interrupt is also generated. This field can be disabled by writing a value of all.." line.long 0x8 "INDIRECT_READ_XFER_START_REG,Indirect Read Transfer Start Address Register" hexmask.long 0x8 0.--31. 1. "ADDR_FLD,This is the start address from which the indirect access will commence its READ operation." line.long 0xC "INDIRECT_READ_XFER_NUM_BYTES_REG,Indirect Read Transfer Number Bytes Register" hexmask.long 0xC 0.--31. 1. "VALUE_FLD,This is the number of bytes that the indirect access will consume. This can be bigger than the configured size of SRAM." line.long 0x10 "INDIRECT_WRITE_XFER_CTRL_REG,Indirect Write Transfer Control Register" hexmask.long.tbyte 0x10 8.--31. 1. "INDIR_WR_XFER_RESV2_FLD,Reserved" newline rbitfld.long 0x10 6.--7. "NUM_IND_OPS_DONE_FLD,This field contains the number of indirect operations which have been completed. This is used in conjunction with the indirect completion status field (bit 5). It is incremented by hardware when an indirect operation has completed." "0,1,2,3" newline bitfld.long 0x10 5. "IND_OPS_DONE_STATUS_FLD,Indirect Completion Status: This field is set to 1 when an indirect operation has completed. Write a 1 to this field to clear it." "0,1" newline rbitfld.long 0x10 4. "WR_QUEUED_FLD,Two indirect write operations have been queued" "0,1" newline rbitfld.long 0x10 3. "INDIR_WR_XFER_RESV1_FLD,Reserved" "0,1" newline rbitfld.long 0x10 2. "WR_STATUS_FLD,Indirect Write Status: Indirect write operation in progress (status)" "0,1" newline bitfld.long 0x10 1. "CANCEL_FLD,Cancel Indirect Write: Writing a 1 to this bit will cancel all ongoing indirect write operations." "0,1" newline bitfld.long 0x10 0. "START_FLD,Start Indirect Write: Writing a 1 to this bit will trigger an indirect write operation. The assumption is that the indirect start address and the indirect number of bytes register is setup before triggering the indirect write operation." "0,1" line.long 0x14 "INDIRECT_WRITE_XFER_WATERMARK_REG,Indirect Write Transfer Watermark Register" hexmask.long 0x14 0.--31. 1. "LEVEL_FLD,Watermark Value: This represents the maximum fill level of the SRAM before a DMA peripheral access is permitted. When the SRAM fill level falls below the watermark an interrupt is also generated. This field can be disabled by writing a value.." line.long 0x18 "INDIRECT_WRITE_XFER_START_REG,Indirect Write Transfer Start Address Register" hexmask.long 0x18 0.--31. 1. "ADDR_FLD,Start of Indirect Access: This is the start address from which the indirect access will commence its READ operation." line.long 0x1C "INDIRECT_WRITE_XFER_NUM_BYTES_REG,Indirect Write Transfer Number Bytes Register" hexmask.long 0x1C 0.--31. 1. "VALUE_FLD,Indirect Number of Bytes: This is the number of bytes that the indirect access will consume. This can be bigger than the configured size of SRAM." line.long 0x20 "INDIRECT_TRIGGER_ADDR_RANGE_REG,Indirect Trigger Address Range Register" hexmask.long 0x20 4.--31. 1. "IND_RANGE_RESV1_FLD,Reserved" newline hexmask.long.byte 0x20 0.--3. 1. "IND_RANGE_WIDTH_FLD,This is the address offset of Indirect Trigger Address Register." group.long 0x8C++0xB line.long 0x0 "FLASH_COMMAND_CTRL_MEM_REG,Flash Command Control Memory Register" rbitfld.long 0x0 29.--31. "FLASH_COMMAND_CTRL_MEM_RESV1_FLD,Reserved" "0,1,2,3,4,5,6,7" newline hexmask.long.word 0x0 20.--28. 1. "MEM_BANK_ADDR_FLD,The address of the Memory Bank which data will be read from." newline rbitfld.long 0x0 19. "FLASH_COMMAND_CTRL_MEM_RESV2_FLD,Reserved" "0,1" newline bitfld.long 0x0 16.--18. "NB_OF_STIG_READ_BYTES_FLD,It defines the number of read bytes for the extended STIG." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x0 8.--15. 1. "MEM_BANK_READ_DATA_FLD,Last requested data from the STIG Memory Bank." newline hexmask.long.byte 0x0 2.--7. 1. "FLASH_COMMAND_CTRL_MEM_RESV3_FLD,Reserved" newline rbitfld.long 0x0 1. "MEM_BANK_REQ_IN_PROGRESS_FLD,Memory Bank data request in progress." "0,1" newline bitfld.long 0x0 0. "TRIGGER_MEM_BANK_REQ_FLD,Trigger the Memory Bank data request." "0,1" line.long 0x4 "FLASH_CMD_CTRL_REG,Flash Command Control Register" hexmask.long.byte 0x4 24.--31. 1. "CMD_OPCODE_FLD,Command Opcode: The command opcode field should be setup before triggering the command. For example 0x20 maps to SubSector Erase. Writing to the execute field (bit 0) of this register launches the command. NOTE : Using this approach to.." newline bitfld.long 0x4 23. "ENB_READ_DATA_FLD,Read Data Enable: Set to 1 if the command specified in the command opcode field (bits 31:24) requires read data bytes to be received from the device." "0,1" newline bitfld.long 0x4 20.--22. "NUM_RD_DATA_BYTES_FLD,Number of Read Data Bytes: Up to 8 data bytes may be read using this command. Set to 0 for 1 byte and 7 for 8 bytes." "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 19. "ENB_COMD_ADDR_FLD,Command Address Enable: Set to 1 if the command specified in bits 31:24 requires an address. This should be setup before triggering the command via writing a 1 to the execute field." "0,1" newline bitfld.long 0x4 18. "ENB_MODE_BIT_FLD,Mode Bit Enable: Set to 1 to ensure the mode bits as defined in the Mode Bit Configuration register are sent following the address bytes." "0,1" newline bitfld.long 0x4 16.--17. "NUM_ADDR_BYTES_FLD,Number of Address Bytes: Set to the number of address bytes required (the address itself is programmed in the FLASH COMMAND ADDRESS REGISTERS). This should be setup before triggering the command via bit 0 of this register. 2'b00 : 1.." "0,1,2,3" newline bitfld.long 0x4 15. "ENB_WRITE_DATA_FLD,Write Data Enable: Set to 1 if the command specified in the command opcode field requires write data bytes to be sent to the device." "0,1" newline bitfld.long 0x4 12.--14. "NUM_WR_DATA_BYTES_FLD,Number of Write Data Bytes: Up to 8 Data bytes may be written using this command Set to 0 for 1 byte 7 for 8 bytes." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x4 7.--11. 1. "NUM_DUMMY_CYCLES_FLD,Number of Dummy cycles: Set to the number of dummy cycles required. This should be setup before triggering the command via the execute field of this register." newline hexmask.long.byte 0x4 3.--6. 1. "FLASH_CMD_CTRL_RESV1_FLD,Reserved" newline bitfld.long 0x4 2. "STIG_MEM_BANK_EN_FLD,STIG Memory Bank enable bit." "0,1" newline rbitfld.long 0x4 1. "CMD_EXEC_STATUS_FLD,Command execution in progress." "0,1" newline bitfld.long 0x4 0. "CMD_EXEC_FLD,Execute the command." "0,1" line.long 0x8 "FLASH_CMD_ADDR_REG,Flash Command Address Register" hexmask.long 0x8 0.--31. 1. "ADDR_FLD,Command Address: This should be setup before triggering the command with execute field (bit 0) of the Flash Command Control register. It is the address used by the command specified in the opcode field (bits 31:24) of the Flash Command Control.." rgroup.long 0xA0++0x7 line.long 0x0 "FLASH_RD_DATA_LOWER_REG,Flash Command Read Data Register (Lower)" hexmask.long 0x0 0.--31. 1. "DATA_FLD,This is the data that is returned by the flash device for any status or configuration read operation carried out by triggering the event in the control register. The register will be valid when the polling bit in the control register is low." line.long 0x4 "FLASH_RD_DATA_UPPER_REG,Flash Command Read Data Register (Upper)" hexmask.long 0x4 0.--31. 1. "DATA_FLD,This is the data that is returned by the FLASH device for any status or configuration read operation carried out by triggering the event in the control register. The register will be valid when the polling bit in the control register is low." group.long 0xA8++0x13 line.long 0x0 "FLASH_WR_DATA_LOWER_REG,Flash Command Write Data Register (Lower)" hexmask.long 0x0 0.--31. 1. "DATA_FLD,Command Write Data Lower Byte: This is the command write data lower byte. This should be setup before triggering the command with execute field (bit 0) of the Flash Command Control register. It is the data that is to be written to the flash for.." line.long 0x4 "FLASH_WR_DATA_UPPER_REG,Flash Command Write Data Register (Upper)" hexmask.long 0x4 0.--31. 1. "DATA_FLD,Command Write Data Upper Byte: This is the command write data upper byte. This should be setup before triggering the command with execute field (bit 0) of the Flash Command Control register. It is the data that is to be written to the flash for.." line.long 0x8 "POLLING_FLASH_STATUS_REG,Polling Flash Status Register" hexmask.long.word 0x8 21.--31. 1. "DEVICE_STATUS_RSVD_FLD2,Reserved" newline hexmask.long.byte 0x8 16.--20. 1. "DEVICE_STATUS_NB_DUMMY,Number of dummy cycles for auto-polling" newline hexmask.long.byte 0x8 9.--15. 1. "DEVICE_STATUS_RSVD_FLD1,Reserved" newline rbitfld.long 0x8 8. "DEVICE_STATUS_VALID_FLD,Device Status Valid: This should be set when value in bits from 7 to 0 is valid." "0,1" newline hexmask.long.byte 0x8 0.--7. 1. "DEVICE_STATUS_FLD,Defines actual Status Register of Device" line.long 0xC "PHY_CONFIGURATION_REG,PHY Configuration Register" bitfld.long 0xC 31. "PHY_CONFIG_RESYNC_FLD,This bit is used for re-synchronisation delay lines to update them with values from TX DLL Delay and RX DLL Delay fields." "0,1" newline bitfld.long 0xC 30. "PHY_CONFIG_RESET_FLD,DLL Reset bit: This bit is used for reset of Delay Lines by software." "0,1" newline bitfld.long 0xC 29. "PHY_CONFIG_RX_DLL_BYPASS_FLD,RX DLL Bypass: This field determines id RX DLL is bypassed." "0,1" newline hexmask.long.byte 0xC 23.--28. 1. "PHY_CONFIG_RESV2_FLD,Reserved" newline hexmask.long.byte 0xC 16.--22. 1. "PHY_CONFIG_TX_DLL_DELAY_FLD,TX DLL Delay: This field determines the number of delay elements to insert on data path between ref_clk and spi_clk." newline hexmask.long.word 0xC 7.--15. 1. "PHY_CONFIG_RESV1_FLD,Reserved" newline hexmask.long.byte 0xC 0.--6. 1. "PHY_CONFIG_RX_DLL_DELAY_FLD,RX DLL Delay: This field determines the number of delay elements to insert on data path between ref_clk and rx_dll_clk." line.long 0x10 "PHY_MASTER_CONTROL_REG,PHY DLL Master Control Register" hexmask.long.byte 0x10 25.--31. 1. "PHY_MASTER_CONTROL_RESV3_FLD,Reserved" newline bitfld.long 0x10 24. "PHY_MASTER_LOCK_MODE_FLD,Determines if the master delay line locks on a full cycle or half cycle of delay." "0,1" newline bitfld.long 0x10 23. "PHY_MASTER_BYPASS_MODE_FLD,Controls the bypass mode of the master and slave DLLs." "0,1" newline bitfld.long 0x10 20.--22. "PHY_MASTER_PHASE_DETECT_SELECTOR_FLD,Selects the number of delay elements to be inserted between the phase detect flip-flops." "0,1,2,3,4,5,6,7" newline rbitfld.long 0x10 19. "PHY_MASTER_CONTROL_RESV2_FLD,Reserved" "0,1" newline bitfld.long 0x10 16.--18. "PHY_MASTER_NB_INDICATIONS_FLD,Holds the number of consecutive increment or decrement indications." "0,1,2,3,4,5,6,7" newline hexmask.long.word 0x10 7.--15. 1. "PHY_MASTER_CONTROL_RESV1_FLD,Reserved" newline hexmask.long.byte 0x10 0.--6. 1. "PHY_MASTER_INITIAL_DELAY_FLD,This value is the initial delay value for the DLL." rgroup.long 0xBC++0x7 line.long 0x0 "DLL_OBSERVABLE_LOWER_REG,DLL Observable Register Lower" hexmask.long.byte 0x0 24.--31. 1. "DLL_OBSERVABLE_LOWER_DLL_LOCK_INC_FLD,Holds the state of the cumulative dll_lock_inc register." newline hexmask.long.byte 0x0 16.--23. 1. "DLL_OBSERVABLE_LOWER_DLL_LOCK_DEC_FLD,Holds the state of the cumulative dll_lock_dec register." newline bitfld.long 0x0 15. "DLL_OBSERVABLE_LOWER_LOOPBACK_LOCK_FLD,This bit indicates that lock of loopback is done." "0,1" newline hexmask.long.byte 0x0 8.--14. 1. "DLL_OBSERVABLE_LOWER_LOCK_VALUE_FLD,Reports the DLL encoder value from the master DLL to the slave DLLs." newline hexmask.long.byte 0x0 3.--7. 1. "DLL_OBSERVABLE_LOWER_UNLOCK_COUNTER_FLD,Reports the number of increments or decrements required for the master DLL to complete the locking process." newline bitfld.long 0x0 1.--2. "DLL_OBSERVABLE_LOWER_LOCK_MODE_FLD,Defines the mode in which the DLL has achieved the lock." "0,1,2,3" newline bitfld.long 0x0 0. "DLL_OBSERVABLE_LOWER_DLL_LOCK_FLD,Indicates status of DLL." "0,1" line.long 0x4 "DLL_OBSERVABLE_UPPER_REG,DLL Observable Register Upper" hexmask.long.word 0x4 23.--31. 1. "DLL_OBSERVABLE_UPPER_RESV2_FLD,Reserved" newline hexmask.long.byte 0x4 16.--22. 1. "DLL_OBSERVABLE_UPPER_TX_DECODER_OUTPUT_FLD,Holds the encoded value for the TX delay line for this slice." newline hexmask.long.word 0x4 7.--15. 1. "DLL_OBSERVABLE_UPPER_RESV1_FLD,Reserved" newline hexmask.long.byte 0x4 0.--6. 1. "DLL_OBSERVABLE__UPPER_RX_DECODER_OUTPUT_FLD,Holds the encoded value for the RX delay line for this slice." group.long 0xE0++0x7 line.long 0x0 "OPCODE_EXT_LOWER_REG,Opcode Extension Register (Lower)" hexmask.long.byte 0x0 24.--31. 1. "EXT_READ_OPCODE_FLD,Supplement byte of any Read Opcode" newline hexmask.long.byte 0x0 16.--23. 1. "EXT_WRITE_OPCODE_FLD,Supplement byte of any Write Opcode" newline hexmask.long.byte 0x0 8.--15. 1. "EXT_POLL_OPCODE_FLD,Supplement byte of any Polling Opcode" newline hexmask.long.byte 0x0 0.--7. 1. "EXT_STIG_OPCODE_FLD,Supplement byte of any STIG Opcode" line.long 0x4 "OPCODE_EXT_UPPER_REG,Opcode Extension Register (Upper)" hexmask.long.byte 0x4 24.--31. 1. "WEL_OPCODE_FLD,First byte of any WEL Opcode" newline hexmask.long.byte 0x4 16.--23. 1. "EXT_WEL_OPCODE_FLD,Supplement byte of any WEL Opcode" newline hexmask.long.word 0x4 0.--15. 1. "OPCODE_EXT_UPPER_RESV1_FLD,Reserved" group.long 0xF0++0x3 line.long 0x0 "CUSTOM_CONF_REG,Custom Configuration Register" hexmask.long 0x0 5.--31. 1. "CUSTOM_CONF_RESV_FLD2,Reserved" newline bitfld.long 0x0 4. "PIPE_SMRT_ACC_FLD,PHY POP delay functionality" "0,1" newline hexmask.long.byte 0x0 0.--3. 1. "CUSTOM_CONF_RESV_FLD1,Reserved" rgroup.long 0xFC++0x3 line.long 0x0 "MODULE_ID_REG,Module ID Register" hexmask.long.byte 0x0 24.--31. 1. "FIX_PATCH_FLD,Fix/path number related to revision described by 3 LSBs of this register" newline hexmask.long.word 0x0 8.--23. 1. "MODULE_ID_FLD,Module/Revision ID number" newline hexmask.long.byte 0x0 3.--7. 1. "MODULE_ID_RESV_FLD,Reserved" newline bitfld.long 0x0 2. "HYPER_SUPPORT_FLD,HyperFlash Support" "0,1" newline bitfld.long 0x0 0.--1. "CONF_FLD,Configuration ID number: 0 : OCTAL + PHY Configuration 1 : OCTAL Configuration 2 : QUAD + PHY Configuration 3 : QUAD Configuration" "OCTAL + PHY Configuration,OCTAL Configuration,QUAD + PHY Configuration,QUAD Configuration" group.long 0x100++0x3 line.long 0x0 "HYPERFLASH_CONFIG_REG,HyperFlash Configuration Register" rbitfld.long 0x0 31. "HYPERFLASH_CONFIG_RESV3_FLD,Reserved" "0,1" newline bitfld.long 0x0 30. "TARGET_HYPERFLASH_STIG_FLD,Identifies the target of final STIG HyperFlash transaction as follows: 1'b0 = Memory Space 1'b1 = Register Space" "Memory Space 1'b1 = Register Space,?" newline bitfld.long 0x0 29. "BURST_TYPE_HYPERFLASH_STIG_FLD,Identifies the burst type of final STIG HyperFlash transaction" "0,1" newline hexmask.long.word 0x0 20.--28. 1. "HYPERFLASH_CONFIG_RESV2_FLD,Reserved" newline hexmask.long.byte 0x0 16.--19. 1. "HYPERFLASH_LAT_CODE_FLD,Identifies the latency code for HyperFlash" newline hexmask.long.word 0x0 1.--15. 1. "HYPERFLASH_CONFIG_RESV1_FLD,Reserved" newline bitfld.long 0x0 0. "HYPERFLASH_ENABLE_FLD,HyperFlash Mode enable bit" "0,1" group.long 0x110++0x3 line.long 0x0 "OSPI_MISC0,Misc configuration Register #0" newline bitfld.long 0x0 5. "CTL3,sample clocl polarity control for sclk_dlyd_i 0x1 - Invert sample clock sclk_dlyd_i 0x0 - sample clock sclk_dlyd_i not inverted" "sample clock sclk_dlyd_i not inverted,Invert sample clock sclk_dlyd_i" newline bitfld.long 0x0 4. "CTL2,DQS pad output enable When CTL0 is set 0x2 this bit should be enable to enable loopback path from internal sclk_out to DQS pad." "0,1" newline bitfld.long 0x0 2.--3. "CTL1,SCLK output logic control. 0x0 - orginal logic without any delay (Delay added by TX DLL) 0x1 - original logic (sclk_out) with dleay 1/4 cycle of SCLK (by ref_clk_2x fall edge) 0x2 - original logic (sclk_out) with delay 1/2 cycle of SCLk (by.." "orginal logic without any delay,original logic,original logic,original logic" newline bitfld.long 0x0 0.--1. "CTL0,loopback SCLK input logic control (sclk_dlyd). 0x0 - loopback from SCLK pad 0x1 - loopback from internal (sclk_out with delay selected by OSPI_MISC0.CTL1) 0x2 - loopback from DQS pad 0x3 - loopback from ref_clk_2x (for DFT test only)." "loopback from SCLK pad,loopback from internal,loopback from DQS pad,loopback from ref_clk_2x" repeat 3. (list 0x1 0x2 0x3 )(list 0x0 0x4 0x8 ) group.long ($2+0x114)++0x3 line.long 0x0 "OSPI_MISC$1,Misc Configuration Register #1" hexmask.long 0x0 0.--31. 1. "CTL,Reserved for future" repeat.end group.long 0x200++0x3 line.long 0x0 "HYPERFLASH_STIG_CONFIG_REG,HyperFlash STIG Configuration Register" hexmask.long.byte 0x0 27.--31. 1. "HYPERFLASH_STIG_CONFIG_REG_RESV0_FLD,Reserved" newline bitfld.long 0x0 24.--26. "HYPERFLASH_STIG_CONFIG_NB_PRE_TRAN_FLD,Identifies the number of STIG HyperFlash pre-transactions" "0,1,2,3,4,5,6,7" newline hexmask.long.word 0x0 13.--23. 1. "HYPERFLASH_STIG_CONFIG_REG_RESV1_FLD,Reserved" newline bitfld.long 0x0 12. "HYPERFLASH_STIG_PRE_TRAN_DATA7_SIZE_FLD,Identifies data size of STIG HyperFlash pre-transaction 7" "0,1" newline rbitfld.long 0x0 11. "HYPERFLASH_STIG_CONFIG_REG_RESV2_FLD,Reserved" "0,1" newline bitfld.long 0x0 10. "HYPERFLASH_STIG_PRE_TRAN_DATA6_SIZE_FLD,Identifies data size of STIG HyperFlash pre-transaction 6" "0,1" newline rbitfld.long 0x0 9. "HYPERFLASH_STIG_CONFIG_REG_RESV3_FLD,Reserved" "0,1" newline bitfld.long 0x0 8. "HYPERFLASH_STIG_PRE_TRAN_DATA5_SIZE_FLD,Identifies data size of STIG HyperFlash pre-transaction 5" "0,1" newline rbitfld.long 0x0 7. "HYPERFLASH_STIG_CONFIG_REG_RESV4_FLD,Reserved" "0,1" newline bitfld.long 0x0 6. "HYPERFLASH_STIG_PRE_TRAN_DATA4_SIZE_FLD,Identifies data size of STIG HyperFlash pre-transaction 4" "0,1" newline rbitfld.long 0x0 5. "HYPERFLASH_STIG_CONFIG_REG_RESV5_FLD,Reserved" "0,1" newline bitfld.long 0x0 4. "HYPERFLASH_STIG_PRE_TRAN_DATA3_SIZE_FLD,Identifies data size of STIG HyperFlash pre-transaction 3" "0,1" newline rbitfld.long 0x0 3. "HYPERFLASH_STIG_CONFIG_REG_RESV6_FLD,Reserved" "0,1" newline bitfld.long 0x0 2. "HYPERFLASH_STIG_PRE_TRAN_DATA2_SIZE_FLD,Identifies data size of STIG HyperFlash pre-transaction 2" "0,1" newline rbitfld.long 0x0 1. "HYPERFLASH_STIG_CONFIG_REG_RESV7_FLD,Reserved" "0,1" newline bitfld.long 0x0 0. "HYPERFLASH_STIG_PRE_TRAN_DATA1_SIZE_FLD,Identifies data size of STIG HyperFlash pre-transaction 1" "0,1" group.long 0x210++0x7 line.long 0x0 "HYPERFLASH_STIG_PRE_TRAN1_ADDRESS_REG,HyperFlash STIG Pre-transaction 1 Address Register" hexmask.long 0x0 0.--31. 1. "HYPERFLASH_STIG_PRE_TRAN1_ADDRESS_FLD,Identifies Address of HyperFlash STIG Pre-transaction 1" line.long 0x4 "HYPERFLASH_STIG_PRE_TRAN1_DATA_REG,HyperFlash STIG Pre-transaction 1 Data Register" hexmask.long 0x4 0.--31. 1. "HYPERFLASH_STIG_PRE_TRAN1_DATA_FLD,Identifies Data of HyperFlash STIG Pre-transaction 1" group.long 0x220++0x7 line.long 0x0 "HYPERFLASH_STIG_PRE_TRAN2_ADDRESS_REG,HyperFlash STIG Pre-transaction 2 Address Register" hexmask.long 0x0 0.--31. 1. "HYPERFLASH_STIG_PRE_TRAN2_ADDRESS_FLD,Identifies Address of HyperFlash STIG Pre-transaction 2" line.long 0x4 "HYPERFLASH_STIG_PRE_TRAN2_DATA_REG,HyperFlash STIG Pre-transaction 2 Data Register" hexmask.long 0x4 0.--31. 1. "HYPERFLASH_STIG_PRE_TRAN2_DATA_FLD,Identifies Data of HyperFlash STIG Pre-transaction 2" group.long 0x230++0x7 line.long 0x0 "HYPERFLASH_STIG_PRE_TRAN3_ADDRESS_REG,HyperFlash STIG Pre-transaction 3 Address Register" hexmask.long 0x0 0.--31. 1. "HYPERFLASH_STIG_PRE_TRAN3_ADDRESS_FLD,Identifies Address of HyperFlash STIG Pre-transaction 3" line.long 0x4 "HYPERFLASH_STIG_PRE_TRAN3_DATA_REG,HyperFlash STIG Pre-transaction 3 Data Register" hexmask.long 0x4 0.--31. 1. "HYPERFLASH_STIG_PRE_TRAN3_DATA_FLD,Identifies Data of HyperFlash STIG Pre-transaction 3" group.long 0x240++0x7 line.long 0x0 "HYPERFLASH_STIG_PRE_TRAN4_ADDRESS_REG,HyperFlash STIG Pre-transaction 4 Address Register" hexmask.long 0x0 0.--31. 1. "HYPERFLASH_STIG_PRE_TRAN4_ADDRESS_FLD,Identifies Address of HyperFlash STIG Pre-transaction 4" line.long 0x4 "HYPERFLASH_STIG_PRE_TRAN4_DATA_REG,HyperFlash STIG Pre-transaction 4 Data Register" hexmask.long 0x4 0.--31. 1. "HYPERFLASH_STIG_PRE_TRAN4_DATA_FLD,Identifies Data of HyperFlash STIG Pre-transaction 4" group.long 0x250++0x7 line.long 0x0 "HYPERFLASH_STIG_PRE_TRAN5_ADDRESS_REG,HyperFlash STIG Pre-transaction 5 Address Register" hexmask.long 0x0 0.--31. 1. "HYPERFLASH_STIG_PRE_TRAN5_ADDRESS_FLD,Identifies Address of HyperFlash STIG Pre-transaction 5" line.long 0x4 "HYPERFLASH_STIG_PRE_TRAN5_DATA_REG,HyperFlash STIG Pre-transaction 5 Data Register" hexmask.long 0x4 0.--31. 1. "HYPERFLASH_STIG_PRE_TRAN5_DATA_FLD,Identifies Data of HyperFlash STIG Pre-transaction 5" group.long 0x260++0x7 line.long 0x0 "HYPERFLASH_STIG_PRE_TRAN6_ADDRESS_REG,HyperFlash STIG Pre-transaction 6 Address Register" hexmask.long 0x0 0.--31. 1. "HYPERFLASH_STIG_PRE_TRAN6_ADDRESS_FLD,Identifies Address of HyperFlash STIG Pre-transaction 6" line.long 0x4 "HYPERFLASH_STIG_PRE_TRAN6_DATA_REG,HyperFlash STIG Pre-transaction 6 Data Register" hexmask.long 0x4 0.--31. 1. "HYPERFLASH_STIG_PRE_TRAN6_DATA_FLD,Identifies Data of HyperFlash STIG Pre-transaction 6" group.long 0x270++0x7 line.long 0x0 "HYPERFLASH_STIG_PRE_TRAN7_ADDRESS_REG,HyperFlash STIG Pre-transaction 7 Address Register" hexmask.long 0x0 0.--31. 1. "HYPERFLASH_STIG_PRE_TRAN7_ADDRESS_FLD,Identifies Address of HyperFlash STIG Pre-transaction 7" line.long 0x4 "HYPERFLASH_STIG_PRE_TRAN7_DATA_REG,HyperFlash STIG Pre-transaction 7 Data Register" hexmask.long 0x4 0.--31. 1. "HYPERFLASH_STIG_PRE_TRAN7_DATA_FLD,Identifies Data of HyperFlash STIG Pre-transaction 7" group.long 0x300++0x3 line.long 0x0 "HYPERFLASH_WRITE_CONFIG_REG,HyperFlash Write Configuration Register" hexmask.long.byte 0x0 27.--31. 1. "HYPERFLASH_WRITE_CONFIG_REG_RESV0_FLD,Reserved" newline bitfld.long 0x0 24.--26. "HYPERFLASH_WRITE_CONFIG_NB_PRE_TRAN_FLD,Identifies the number of Write HyperFlash pre-transactions" "0,1,2,3,4,5,6,7" newline hexmask.long.word 0x0 13.--23. 1. "HYPERFLASH_WRITE_CONFIG_REG_RESV1_FLD,Reserved" newline bitfld.long 0x0 12. "HYPERFLASH_WRITE_PRE_TRAN_DATA7_SIZE_FLD,Identifies data size of Write HyperFlash pre-transaction 7" "0,1" newline rbitfld.long 0x0 11. "HYPERFLASH_WRITE_CONFIG_REG_RESV2_FLD,Reserved" "0,1" newline bitfld.long 0x0 10. "HYPERFLASH_WRITE_PRE_TRAN_DATA6_SIZE_FLD,Identifies data size of Write HyperFlash pre-transaction 6" "0,1" newline rbitfld.long 0x0 9. "HYPERFLASH_WRITE_CONFIG_REG_RESV3_FLD,Reserved" "0,1" newline bitfld.long 0x0 8. "HYPERFLASH_WRITE_PRE_TRAN_DATA5_SIZE_FLD,Identifies data size of Write HyperFlash pre-transaction 5" "0,1" newline rbitfld.long 0x0 7. "HYPERFLASH_WRITE_CONFIG_REG_RESV4_FLD,Reserved" "0,1" newline bitfld.long 0x0 6. "HYPERFLASH_WRITE_PRE_TRAN_DATA4_SIZE_FLD,Identifies data size of Write HyperFlash pre-transaction 4" "0,1" newline rbitfld.long 0x0 5. "HYPERFLASH_WRITE_CONFIG_REG_RESV5_FLD,Reserved" "0,1" newline bitfld.long 0x0 4. "HYPERFLASH_WRITE_PRE_TRAN_DATA3_SIZE_FLD,Identifies data size of Write HyperFlash pre-transaction 3" "0,1" newline rbitfld.long 0x0 3. "HYPERFLASH_WRITE_CONFIG_REG_RESV6_FLD,Reserved" "0,1" newline bitfld.long 0x0 2. "HYPERFLASH_WRITE_PRE_TRAN_DATA2_SIZE_FLD,Identifies data size of Write HyperFlash pre-transaction 2" "0,1" newline rbitfld.long 0x0 1. "HYPERFLASH_WRITE_CONFIG_REG_RESV7_FLD,Reserved" "0,1" newline bitfld.long 0x0 0. "HYPERFLASH_WRITE_PRE_TRAN_DATA1_SIZE_FLD,Identifies data size of Write HyperFlash pre-transaction 1" "0,1" group.long 0x310++0x7 line.long 0x0 "HYPERFLASH_WRITE_PRE_TRAN1_ADDRESS_REG,HyperFlash Write Pre-transaction 1 Address Register" hexmask.long 0x0 0.--31. 1. "HYPERFLASH_WRITE_PRE_TRAN1_ADDRESS_FLD,Identifies Address of HyperFlash Write Pre-transaction 1" line.long 0x4 "HYPERFLASH_WRITE_PRE_TRAN1_DATA_REG,HyperFlash Write Pre-transaction 1 Data Register" hexmask.long 0x4 0.--31. 1. "HYPERFLASH_WRITE_PRE_TRAN1_DATA_FLD,Identifies Data of HyperFlash Write Pre-transaction 1" group.long 0x320++0x7 line.long 0x0 "HYPERFLASH_WRITE_PRE_TRAN2_ADDRESS_REG,HyperFlash Write Pre-transaction 2 Address Register" hexmask.long 0x0 0.--31. 1. "HYPERFLASH_WRITE_PRE_TRAN2_ADDRESS_FLD,Identifies Address of HyperFlash Write Pre-transaction 2" line.long 0x4 "HYPERFLASH_WRITE_PRE_TRAN2_DATA_REG,HyperFlash Write Pre-transaction 2 Data Register" hexmask.long 0x4 0.--31. 1. "HYPERFLASH_WRITE_PRE_TRAN2_DATA_FLD,Identifies Data of HyperFlash Write Pre-transaction 2" group.long 0x330++0x7 line.long 0x0 "HYPERFLASH_WRITE_PRE_TRAN3_ADDRESS_REG,HyperFlash Write Pre-transaction 3 Address Register" hexmask.long 0x0 0.--31. 1. "HYPERFLASH_WRITE_PRE_TRAN3_ADDRESS_FLD,Identifies Address of HyperFlash Write Pre-transaction 3" line.long 0x4 "HYPERFLASH_WRITE_PRE_TRAN3_DATA_REG,HyperFlash Write Pre-transaction 3 Data Register" hexmask.long 0x4 0.--31. 1. "HYPERFLASH_WRITE_PRE_TRAN3_DATA_FLD,Identifies Data of HyperFlash Write Pre-transaction 3" group.long 0x340++0x7 line.long 0x0 "HYPERFLASH_WRITE_PRE_TRAN4_ADDRESS_REG,HyperFlash Write Pre-transaction 4 Address Register" hexmask.long 0x0 0.--31. 1. "HYPERFLASH_WRITE_PRE_TRAN4_ADDRESS_FLD,Identifies Address of HyperFlash Write Pre-transaction 4" line.long 0x4 "HYPERFLASH_WRITE_PRE_TRAN4_DATA_REG,HyperFlash Write Pre-transaction 4 Data Register" hexmask.long 0x4 0.--31. 1. "HYPERFLASH_WRITE_PRE_TRAN4_DATA_FLD,Identifies Data of HyperFlash Write Pre-transaction 4" group.long 0x350++0x7 line.long 0x0 "HYPERFLASH_WRITE_PRE_TRAN5_ADDRESS_REG,HyperFlash Write Pre-transaction 5 Address Register" hexmask.long 0x0 0.--31. 1. "HYPERFLASH_WRITE_PRE_TRAN5_ADDRESS_FLD,Identifies Address of HyperFlash Write Pre-transaction 5" line.long 0x4 "HYPERFLASH_WRITE_PRE_TRAN5_DATA_REG,HyperFlash Write Pre-transaction 5 Data Register" hexmask.long 0x4 0.--31. 1. "HYPERFLASH_WRITE_PRE_TRAN5_DATA_FLD,Identifies Data of HyperFlash Write Pre-transaction 5" group.long 0x360++0x7 line.long 0x0 "HYPERFLASH_WRITE_PRE_TRAN6_ADDRESS_REG,HyperFlash Write Pre-transaction 6 Address Register" hexmask.long 0x0 0.--31. 1. "HYPERFLASH_WRITE_PRE_TRAN6_ADDRESS_FLD,Identifies Address of HyperFlash Write Pre-transaction 6" line.long 0x4 "HYPERFLASH_WRITE_PRE_TRAN6_DATA_REG,HyperFlash Write Pre-transaction 6 Data Register" hexmask.long 0x4 0.--31. 1. "HYPERFLASH_WRITE_PRE_TRAN6_DATA_FLD,Identifies Data of HyperFlash Write Pre-transaction 6" group.long 0x370++0x7 line.long 0x0 "HYPERFLASH_WRITE_PRE_TRAN7_ADDRESS_REG,HyperFlash Write Pre-transaction 7 Address Register" hexmask.long 0x0 0.--31. 1. "HYPERFLASH_WRITE_PRE_TRAN7_ADDRESS_FLD,Identifies Address of HyperFlash Write Pre-transaction 7" line.long 0x4 "HYPERFLASH_WRITE_PRE_TRAN7_DATA_REG,HyperFlash Write Pre-transaction 7 Data Register" hexmask.long 0x4 0.--31. 1. "HYPERFLASH_WRITE_PRE_TRAN7_DATA_FLD,Identifies Data of HyperFlash Write Pre-transaction 7" group.long 0x400++0x3 line.long 0x0 "HYPERFLASH_READ_CONFIG_REG,HyperFlash Read Configuration Register" hexmask.long.byte 0x0 27.--31. 1. "HYPERFLASH_READ_CONFIG_REG_RESV0_FLD,Reserved" newline bitfld.long 0x0 24.--26. "HYPERFLASH_READ_CONFIG_NB_PRE_TRAN_FLD,Identifies the number of Read HyperFlash pre-transactions" "0,1,2,3,4,5,6,7" newline hexmask.long.word 0x0 13.--23. 1. "HYPERFLASH_READ_CONFIG_REG_RESV1_FLD,Reserved" newline bitfld.long 0x0 12. "HYPERFLASH_READ_PRE_TRAN_DATA7_SIZE_FLD,Identifies data size of Read HyperFlash pre-transaction 7" "0,1" newline rbitfld.long 0x0 11. "HYPERFLASH_READ_CONFIG_REG_RESV2_FLD,Reserved" "0,1" newline bitfld.long 0x0 10. "HYPERFLASH_READ_PRE_TRAN_DATA6_SIZE_FLD,Identifies data size of Read HyperFlash pre-transaction 6" "0,1" newline rbitfld.long 0x0 9. "HYPERFLASH_READ_CONFIG_REG_RESV3_FLD,Reserved" "0,1" newline bitfld.long 0x0 8. "HYPERFLASH_READ_PRE_TRAN_DATA5_SIZE_FLD,Identifies data size of Read HyperFlash pre-transaction 5" "0,1" newline rbitfld.long 0x0 7. "HYPERFLASH_READ_CONFIG_REG_RESV4_FLD,Reserved" "0,1" newline bitfld.long 0x0 6. "HYPERFLASH_READ_PRE_TRAN_DATA4_SIZE_FLD,Identifies data size of Read HyperFlash pre-transaction 4" "0,1" newline rbitfld.long 0x0 5. "HYPERFLASH_READ_CONFIG_REG_RESV5_FLD,Reserved" "0,1" newline bitfld.long 0x0 4. "HYPERFLASH_READ_PRE_TRAN_DATA3_SIZE_FLD,Identifies data size of Read HyperFlash pre-transaction 3" "0,1" newline rbitfld.long 0x0 3. "HYPERFLASH_READ_CONFIG_REG_RESV6_FLD,Reserved" "0,1" newline bitfld.long 0x0 2. "HYPERFLASH_READ_PRE_TRAN_DATA2_SIZE_FLD,Identifies data size of Read HyperFlash pre-transaction 2" "0,1" newline rbitfld.long 0x0 1. "HYPERFLASH_READ_CONFIG_REG_RESV7_FLD,Reserved" "0,1" newline bitfld.long 0x0 0. "HYPERFLASH_READ_PRE_TRAN_DATA1_SIZE_FLD,Identifies data size of Read HyperFlash pre-transaction 1" "0,1" group.long 0x410++0x7 line.long 0x0 "HYPERFLASH_READ_PRE_TRAN1_ADDRESS_REG,HyperFlash Read Pre-transaction 1 Address Register" hexmask.long 0x0 0.--31. 1. "HYPERFLASH_READ_PRE_TRAN1_ADDRESS_FLD,Identifies Address of HyperFlash Read Pre-transaction 1" line.long 0x4 "HYPERFLASH_READ_PRE_TRAN1_DATA_REG,HyperFlash Read Pre-transaction 1 Data Register" hexmask.long 0x4 0.--31. 1. "HYPERFLASH_READ_PRE_TRAN1_DATA_FLD,Identifies Data of HyperFlash Read Pre-transaction 1" group.long 0x420++0x7 line.long 0x0 "HYPERFLASH_READ_PRE_TRAN2_ADDRESS_REG,HyperFlash Read Pre-transaction 2 Address Register" hexmask.long 0x0 0.--31. 1. "HYPERFLASH_READ_PRE_TRAN2_ADDRESS_FLD,Identifies Address of HyperFlash Read Pre-transaction 2" line.long 0x4 "HYPERFLASH_READ_PRE_TRAN2_DATA_REG,HyperFlash Read Pre-transaction 2 Data Register" hexmask.long 0x4 0.--31. 1. "HYPERFLASH_READ_PRE_TRAN2_DATA_FLD,Identifies Data of HyperFlash Read Pre-transaction 2" group.long 0x430++0x7 line.long 0x0 "HYPERFLASH_READ_PRE_TRAN3_ADDRESS_REG,HyperFlash Read Pre-transaction 3 Address Register" hexmask.long 0x0 0.--31. 1. "HYPERFLASH_READ_PRE_TRAN3_ADDRESS_FLD,Identifies Address of HyperFlash Read Pre-transaction 3" line.long 0x4 "HYPERFLASH_READ_PRE_TRAN3_DATA_REG,HyperFlash Read Pre-transaction 3 Data Register" hexmask.long 0x4 0.--31. 1. "HYPERFLASH_READ_PRE_TRAN3_DATA_FLD,Identifies Data of HyperFlash Read Pre-transaction 3" group.long 0x440++0x7 line.long 0x0 "HYPERFLASH_READ_PRE_TRAN4_ADDRESS_REG,HyperFlash Read Pre-transaction 4 Address Register" hexmask.long 0x0 0.--31. 1. "HYPERFLASH_READ_PRE_TRAN4_ADDRESS_FLD,Identifies Address of HyperFlash Read Pre-transaction 4" line.long 0x4 "HYPERFLASH_READ_PRE_TRAN4_DATA_REG,HyperFlash Read Pre-transaction 4 Data Register" hexmask.long 0x4 0.--31. 1. "HYPERFLASH_READ_PRE_TRAN4_DATA_FLD,Identifies Data of HyperFlash Read Pre-transaction 4" group.long 0x450++0x7 line.long 0x0 "HYPERFLASH_READ_PRE_TRAN5_ADDRESS_REG,HyperFlash Read Pre-transaction 5 Address Register" hexmask.long 0x0 0.--31. 1. "HYPERFLASH_READ_PRE_TRAN5_ADDRESS_FLD,Identifies Address of HyperFlash Read Pre-transaction 5" line.long 0x4 "HYPERFLASH_READ_PRE_TRAN5_DATA_REG,HyperFlash Read Pre-transaction 5 Data Register" hexmask.long 0x4 0.--31. 1. "HYPERFLASH_READ_PRE_TRAN5_DATA_FLD,Identifies Data of HyperFlash Read Pre-transaction 5" group.long 0x460++0x7 line.long 0x0 "HYPERFLASH_READ_PRE_TRAN6_ADDRESS_REG,HyperFlash Read Pre-transaction 6 Address Register" hexmask.long 0x0 0.--31. 1. "HYPERFLASH_READ_PRE_TRAN6_ADDRESS_FLD,Identifies Address of HyperFlash Read Pre-transaction 6" line.long 0x4 "HYPERFLASH_READ_PRE_TRAN6_DATA_REG,HyperFlash Read Pre-transaction 6 Data Register" hexmask.long 0x4 0.--31. 1. "HYPERFLASH_READ_PRE_TRAN6_DATA_FLD,Identifies Data of HyperFlash Read Pre-transaction 6" group.long 0x470++0x7 line.long 0x0 "HYPERFLASH_READ_PRE_TRAN7_ADDRESS_REG,HyperFlash Read Pre-transaction 7 Address Register" hexmask.long 0x0 0.--31. 1. "HYPERFLASH_READ_PRE_TRAN7_ADDRESS_FLD,Identifies Address of HyperFlash Read Pre-transaction 7" line.long 0x4 "HYPERFLASH_READ_PRE_TRAN7_DATA_REG,HyperFlash Read Pre-transaction 7 Data Register" hexmask.long 0x4 0.--31. 1. "HYPERFLASH_READ_PRE_TRAN7_DATA_FLD,Identifies Data of HyperFlash Read Pre-transaction 7" group.long 0x500++0x3 line.long 0x0 "HYPERFLASH_POLLING_CONFIG_REG,HyperFlash Polling Configuration Register" hexmask.long.byte 0x0 27.--31. 1. "HYPERFLASH_POLLING_CONFIG_REG_RESV0_FLD,Reserved" newline bitfld.long 0x0 24.--26. "HYPERFLASH_POLLING_CONFIG_NB_PRE_TRAN_FLD,Identifies the number of Polling HyperFlash pre-transactions" "0,1,2,3,4,5,6,7" newline hexmask.long.word 0x0 13.--23. 1. "HYPERFLASH_POLLING_CONFIG_REG_RESV1_FLD,Reserved" newline bitfld.long 0x0 12. "HYPERFLASH_POLLING_PRE_TRAN_DATA7_SIZE_FLD,Identifies data size of Polling HyperFlash pre-transaction 7" "0,1" newline rbitfld.long 0x0 11. "HYPERFLASH_POLLING_CONFIG_REG_RESV2_FLD,Reserved" "0,1" newline bitfld.long 0x0 10. "HYPERFLASH_POLLING_PRE_TRAN_DATA6_SIZE_FLD,Identifies data size of Polling HyperFlash pre-transaction 6" "0,1" newline rbitfld.long 0x0 9. "HYPERFLASH_POLLING_CONFIG_REG_RESV3_FLD,Reserved" "0,1" newline bitfld.long 0x0 8. "HYPERFLASH_POLLING_PRE_TRAN_DATA5_SIZE_FLD,Identifies data size of Polling HyperFlash pre-transaction 5" "0,1" newline rbitfld.long 0x0 7. "HYPERFLASH_POLLING_CONFIG_REG_RESV4_FLD,Reserved" "0,1" newline bitfld.long 0x0 6. "HYPERFLASH_POLLING_PRE_TRAN_DATA4_SIZE_FLD,Identifies data size of Polling HyperFlash pre-transaction 4" "0,1" newline rbitfld.long 0x0 5. "HYPERFLASH_POLLING_CONFIG_REG_RESV5_FLD,Reserved" "0,1" newline bitfld.long 0x0 4. "HYPERFLASH_POLLING_PRE_TRAN_DATA3_SIZE_FLD,Identifies data size of Polling HyperFlash pre-transaction 3" "0,1" newline rbitfld.long 0x0 3. "HYPERFLASH_POLLING_CONFIG_REG_RESV6_FLD,Reserved" "0,1" newline bitfld.long 0x0 2. "HYPERFLASH_POLLING_PRE_TRAN_DATA2_SIZE_FLD,Identifies data size of Polling HyperFlash pre-transaction 2" "0,1" newline rbitfld.long 0x0 1. "HYPERFLASH_POLLING_CONFIG_REG_RESV7_FLD,Reserved" "0,1" newline bitfld.long 0x0 0. "HYPERFLASH_POLLING_PRE_TRAN_DATA1_SIZE_FLD,Identifies data size of Polling HyperFlash pre-transaction 1" "0,1" group.long 0x510++0x7 line.long 0x0 "HYPERFLASH_POLLING_PRE_TRAN1_ADDRESS_REG,HyperFlash Polling Pre-transaction 1 Address Register" hexmask.long 0x0 0.--31. 1. "HYPERFLASH_POLLING_PRE_TRAN1_ADDRESS_FLD,Identifies Address of HyperFlash Polling Pre-transaction 1" line.long 0x4 "HYPERFLASH_POLLING_PRE_TRAN1_DATA_REG,HyperFlash Polling Pre-transaction 1 Data Register" hexmask.long 0x4 0.--31. 1. "HYPERFLASH_POLLING_PRE_TRAN1_DATA_FLD,Identifies Data of HyperFlash Polling Pre-transaction 1" group.long 0x520++0x7 line.long 0x0 "HYPERFLASH_POLLING_PRE_TRAN2_ADDRESS_REG,HyperFlash Polling Pre-transaction 2 Address Register" hexmask.long 0x0 0.--31. 1. "HYPERFLASH_POLLING_PRE_TRAN2_ADDRESS_FLD,Identifies Address of HyperFlash Polling Pre-transaction 2" line.long 0x4 "HYPERFLASH_POLLING_PRE_TRAN2_DATA_REG,HyperFlash Polling Pre-transaction 2 Data Register" hexmask.long 0x4 0.--31. 1. "HYPERFLASH_POLLING_PRE_TRAN2_DATA_FLD,Identifies Data of HyperFlash Polling Pre-transaction 2" group.long 0x530++0x7 line.long 0x0 "HYPERFLASH_POLLING_PRE_TRAN3_ADDRESS_REG,HyperFlash Polling Pre-transaction 3 Address Register" hexmask.long 0x0 0.--31. 1. "HYPERFLASH_POLLING_PRE_TRAN3_ADDRESS_FLD,Identifies Address of HyperFlash Polling Pre-transaction 3" line.long 0x4 "HYPERFLASH_POLLING_PRE_TRAN3_DATA_REG,HyperFlash Polling Pre-transaction 3 Data Register" hexmask.long 0x4 0.--31. 1. "HYPERFLASH_POLLING_PRE_TRAN3_DATA_FLD,Identifies Data of HyperFlash Polling Pre-transaction 3" group.long 0x540++0x7 line.long 0x0 "HYPERFLASH_POLLING_PRE_TRAN4_ADDRESS_REG,HyperFlash Polling Pre-transaction 4 Address Register" hexmask.long 0x0 0.--31. 1. "HYPERFLASH_POLLING_PRE_TRAN4_ADDRESS_FLD,Identifies Address of HyperFlash Polling Pre-transaction 4" line.long 0x4 "HYPERFLASH_POLLING_PRE_TRAN4_DATA_REG,HyperFlash Polling Pre-transaction 4 Data Register" hexmask.long 0x4 0.--31. 1. "HYPERFLASH_POLLING_PRE_TRAN4_DATA_FLD,Identifies Data of HyperFlash Polling Pre-transaction 4" group.long 0x550++0x7 line.long 0x0 "HYPERFLASH_POLLING_PRE_TRAN5_ADDRESS_REG,HyperFlash Polling Pre-transaction 5 Address Register" hexmask.long 0x0 0.--31. 1. "HYPERFLASH_POLLING_PRE_TRAN5_ADDRESS_FLD,Identifies Address of HyperFlash Polling Pre-transaction 5" line.long 0x4 "HYPERFLASH_POLLING_PRE_TRAN5_DATA_REG,HyperFlash Polling Pre-transaction 5 Data Register" hexmask.long 0x4 0.--31. 1. "HYPERFLASH_POLLING_PRE_TRAN5_DATA_FLD,Identifies Data of HyperFlash Polling Pre-transaction 5" group.long 0x560++0x7 line.long 0x0 "HYPERFLASH_POLLING_PRE_TRAN6_ADDRESS_REG,HyperFlash Polling Pre-transaction 6 Address Register" hexmask.long 0x0 0.--31. 1. "HYPERFLASH_POLLING_PRE_TRAN6_ADDRESS_FLD,Identifies Address of HyperFlash Polling Pre-transaction 6" line.long 0x4 "HYPERFLASH_POLLING_PRE_TRAN6_DATA_REG,HyperFlash Polling Pre-transaction 6 Data Register" hexmask.long 0x4 0.--31. 1. "HYPERFLASH_POLLING_PRE_TRAN6_DATA_FLD,Identifies Data of HyperFlash Polling Pre-transaction 6" group.long 0x570++0x7 line.long 0x0 "HYPERFLASH_POLLING_PRE_TRAN7_ADDRESS_REG,HyperFlash Polling Pre-transaction 7 Address Register" hexmask.long 0x0 0.--31. 1. "HYPERFLASH_POLLING_PRE_TRAN7_ADDRESS_FLD,Identifies Address of HyperFlash Polling Pre-transaction 7" line.long 0x4 "HYPERFLASH_POLLING_PRE_TRAN7_DATA_REG,HyperFlash Polling Pre-transaction 7 Data Register" hexmask.long 0x4 0.--31. 1. "HYPERFLASH_POLLING_PRE_TRAN7_DATA_FLD,Identifies Data of HyperFlash Polling Pre-transaction 7" group.long 0xA00++0x13 line.long 0x0 "ASF_INT_STATUS_REG,ASF Interrupt Status Register" hexmask.long 0x0 7.--31. 1. "ASF_INT_STATUS_RESV1_FLD,Reserved" newline bitfld.long 0x0 6. "ASF_INTEGRITY_ERR_FLD,Integrity error interrupt" "0,1" newline bitfld.long 0x0 5. "ASF_PROTOCOL_ERR_FLD,Protocol error interrupt" "0,1" newline bitfld.long 0x0 4. "ASF_TRANS_TO_ERR_FLD,Transaction timeouts interrupt" "0,1" newline bitfld.long 0x0 3. "ASF_CSR_ERR_FLD,Configuration and status registers error interrupt" "0,1" newline bitfld.long 0x0 2. "ASF_DAP_ERR_FLD,Data and address paths error interrupt" "0,1" newline bitfld.long 0x0 1. "ASF_SRAM_UNCORR_ERR_FLD,SRAM uncorrectable error interrupt" "0,1" newline bitfld.long 0x0 0. "ASF_SRAM_CORR_ERR_FLD,SRAM correctable error interrupt" "0,1" line.long 0x4 "ASF_INT_RAW_STATUS_REG,ASF Interrupt Raw Status Register" hexmask.long 0x4 7.--31. 1. "ASF_INT_RAW_STATUS_RESV1_FLD,Reserved" newline bitfld.long 0x4 6. "ASF_INTEGRITY_ERR_FLD,Integrity error interrupt" "0,1" newline bitfld.long 0x4 5. "ASF_PROTOCOL_ERR_FLD,Protocol error interrupt" "0,1" newline bitfld.long 0x4 4. "ASF_TRANS_TO_ERR_FLD,Transaction timeouts interrupt" "0,1" newline bitfld.long 0x4 3. "ASF_CSR_ERR_FLD,Configuration and status registers error interrupt" "0,1" newline bitfld.long 0x4 2. "ASF_DAP_ERR_FLD,Data and address paths error interrupt" "0,1" newline bitfld.long 0x4 1. "ASF_SRAM_UNCORR_ERR_FLD,SRAM uncorrectable error interrupt" "0,1" newline bitfld.long 0x4 0. "ASF_SRAM_CORR_ERR_FLD,SRAM correctable error interrupt" "0,1" line.long 0x8 "ASF_INT_MASK_REG,The ASF interrupt mask register indicating which interrupt bits in the ASF Interrupt Status Register are masked" hexmask.long 0x8 7.--31. 1. "ASF_INT_MASK_RESV1_FLD,Reserved" newline bitfld.long 0x8 6. "ASF_INTEGRITY_ERR_MASK_FLD,Mask bit for integrity error interrupt" "0,1" newline bitfld.long 0x8 5. "ASF_PROTOCOL_ERR_MASK_FLD,Mask bit for protocol error interrupt" "0,1" newline bitfld.long 0x8 4. "ASF_TRANS_TO_ERR_MASK_FLD,Mask bit for transaction timeouts interrupt" "0,1" newline bitfld.long 0x8 3. "ASF_CSR_ERR_MASK_FLD,Mask bit for configuration and status registers error interrupt" "0,1" newline bitfld.long 0x8 2. "ASF_DAP_ERR_MASK_FLD,Mask bit for data and address paths error interrupt" "0,1" newline bitfld.long 0x8 1. "ASF_SRAM_UNCORR_ERR_MASK_FLD,Mask bit for SRAM uncorrectable error interrupt" "0,1" newline bitfld.long 0x8 0. "ASF_SRAM_CORR_ERR_MASK_FLD,Mask bit for SRAM correctable error interrupt" "0,1" line.long 0xC "ASF_INT_TEST_REG,The ASF interrupt test register emulate hardware even" hexmask.long 0xC 7.--31. 1. "ASF_INT_TEST_RESV1_FLD,Reserved" newline bitfld.long 0xC 6. "ASF_INTEGRITY_ERR_TEST_FLD,Test bit for integrity error interrupt" "0,1" newline bitfld.long 0xC 5. "ASF_PROTOCOL_ERR_TEST_FLD,Test bit for protocol error interrupt" "0,1" newline bitfld.long 0xC 4. "ASF_TRANS_TO_ERR_TEST_FLD,Test bit for transaction timeouts interrupt" "0,1" newline bitfld.long 0xC 3. "ASF_CSR_ERR_TEST_FLD,Test bit for configuration and status registers error interrupt" "0,1" newline bitfld.long 0xC 2. "ASF_DAP_ERR_TEST_FLD,Test bit for data and address paths error interrupt" "0,1" newline bitfld.long 0xC 1. "ASF_SRAM_UNCORR_ERR_TEST_FLD,Test bit form SRAM uncorrectable error interrupt" "0,1" newline bitfld.long 0xC 0. "ASF_SRAM_CORR_ERR_TEST_FLD,Test bit for SRAM correctable error interupt" "0,1" line.long 0x10 "ASF_FATAL_NONFATAL_SELECT_REG,The fatal or non-fatal interrupt registers selects whether a fatal or non-fatal interrupt is triggered." hexmask.long 0x10 7.--31. 1. "ASF_FATAL_NONFATAL_SELECT_RESV1_FLD,Reserved" newline bitfld.long 0x10 6. "ASF_INTEGRITY_ERR_SEL_FLD,Enable integrity interrupt as fatal" "0,1" newline bitfld.long 0x10 5. "ASF_PROTOCOL_ERR_SEL_FLD,Enable protocol interrupt as fatal" "0,1" newline bitfld.long 0x10 4. "ASF_TRANS_TO_ERR_SEL_FLD,Enable transaction timeouts interrupt as fatal" "0,1" newline bitfld.long 0x10 3. "ASF_CSR_ERR_SEL_FLD,Enable configuration and status registers interrupts as fatal" "0,1" newline bitfld.long 0x10 2. "ASF_DAP_ERR_SEL_FLD,Enable data and address paths interrupt as fatal" "0,1" newline bitfld.long 0x10 1. "ASF_SRAM_UNCORR_ERR_SEL_FLD,Enable SRAM uncorrectable interrupt as fatal" "0,1" newline bitfld.long 0x10 0. "ASF_SRAM_CORR_ERR_SEL_FLD,Enable SRAM correctable interrupt as fatal" "0,1" rgroup.long 0xA20++0x7 line.long 0x0 "ASF_SRAM_CORR_FAULT_STATUS_REG,Status register for SRAM correctable fault' field{ desc = 'Last SRAM address that generated fault" line.long 0x4 "ASF_SRAM_UNCORR_FAULT_STATUS_REG,Status register for SRAM uncorrectable fault" hexmask.long.word 0x4 16.--31. 1. "ASF_SRAM_UNCORR_FAULT_STATUS_RESV1_FLD,Reserved" newline hexmask.long.word 0x4 0.--15. 1. "ASF_SRAM_UNCORR_FAULT_ADDR_FLD,Last SRAM address that generated" group.long 0xA28++0x3 line.long 0x0 "ASF_SRAM_FAULT_STATS_REG,Statics register for SRAM faults" hexmask.long.word 0x0 16.--31. 1. "ASF_SRAM_FAULT_UNCORR_STATS_FLS,Count of number of uncorrectable errors" newline hexmask.long.word 0x0 0.--15. 1. "ASF_SRAM_FAULT_CORR_STATS_FLD,Count of number of correctable errors" group.long 0xA30++0xB line.long 0x0 "ASF_TRANS_TO_CTRL_REG,Control register to configure the ASF transaction timeout monitors" bitfld.long 0x0 31. "ASF_TRANS_TO_EN_FLD,Enable transaction timeout monitoring" "0,1" newline hexmask.long.word 0x0 16.--30. 1. "ASF_TRANS_TO_CTRL_RESV1_FLD,Reserved" newline hexmask.long.word 0x0 0.--15. 1. "ASF_TRANS_TO_CTRL_FLD,Time value to use for transaction timeout monitor" line.long 0x4 "ASF_TRANS_TO_FAULT_MASK_REG,Control Register to mask out ASF transaction timeout faults from triggering interrupts" hexmask.long 0x4 1.--31. 1. "ASF_TRANS_TO_FAULT_STATUS_RESV1_FLD,Reserved" newline bitfld.long 0x4 0. "ASF_TRANS_TO_FAULT_MASK_FLD,Mask for AHB ASF transaction timeout fault source" "0,1" line.long 0x8 "ASF_TRANS_TO_FAULT_STATUS_REG,Status register for transaction timeouts fault" hexmask.long 0x8 1.--31. 1. "ASF_TRANS_TO_FAULT_STATUS_RESV1_FLD,Reserved" newline bitfld.long 0x8 0. "ASF_TRANS,Status bit for transaction timeouts faults" "0,1" group.long 0xA40++0x7 line.long 0x0 "ASF_PROTOCOL_FAULT_MASK_REG,Control register to mask out ASF Protocol faults from triggering interrupts" hexmask.long.word 0x0 19.--31. 1. "ASF_PROTOCOL_FAULT_MASK_RESV2_FLD,Reserved" newline bitfld.long 0x0 18. "ASF_PROTOCOL_FAULT_MASK_FLASH_CFG_FLD,Mask bit for Tri state enable fault" "0,1" newline bitfld.long 0x0 17. "ASF_PROTOCOL_FAULD_MASK_CS_FLD,Mask bit for Tri state enable fault" "0,1" newline bitfld.long 0x0 16. "ASF_PROTOCOL_FAULT_MASK_TRI_FLD,Mask bit for Tri state enable fault" "0,1" newline hexmask.long.word 0x0 4.--15. 1. "ASF_PROTOCOL_FAULT_MASK_RESV1_FLD,Reserved" newline bitfld.long 0x0 3. "ASF_PROTOCOL_FAULT_MASK_ECC_FLD,Mask bit for ECC failure" "0,1" newline bitfld.long 0x0 2. "ASF_PROTOCOL_MASK_TX_CRC_FLD,Mask bit for Polling expiration error" "0,1" newline bitfld.long 0x0 1. "ASF_PROTOCOL_FAULT_MASK_RX_CRC_FLD,Mask bit for Polling expiration error" "0,1" newline bitfld.long 0x0 0. "ASF_PROTOCOL_FAULT_MASK_POLL_FLD,Mask bit for Polling expiration error" "0,1" line.long 0x4 "ASF_PROTOCOL_FAULT_STATUS_REG,Status register for protocol faults" hexmask.long.word 0x4 19.--31. 1. "ASF_PROTOCOL_FAULT_STATUS_RESV2_FLD,Reserved" newline bitfld.long 0x4 18. "ASF_PROTOCOL_FAULT_STATUS_FLASH_CFG_FLD,Flash Configuration failure" "0,1" newline bitfld.long 0x4 17. "ASF_PROTOCOL_FAULT_STATUS_CS_FLD,#CS fault" "0,1" newline bitfld.long 0x4 16. "ASF_PROTOCOL_FAULT_STATUS_TRI_FLD,Tri state enable fault" "0,1" newline hexmask.long.word 0x4 4.--15. 1. "ASF_PROTOCOL_FAULT_STATUS_RESV1_FLD,Reserved" newline bitfld.long 0x4 3. "ASF_PROTOCOL_FAULT_STATUS_ECC,ECC failure" "0,1" newline bitfld.long 0x4 2. "ASF_PROTOCOL_FAULT_STATUS_TX_CRC,TX CRC chunk was broken" "0,1" newline bitfld.long 0x4 1. "ASF_PROTOCOL_FAULT_STATUS_RX_CRC_FLD,RX CRC data error" "0,1" newline bitfld.long 0x4 0. "ASF_PROTOCOL_FAULT_STATUS_POLL_FLD,Polling expiration error" "0,1" tree.end elif (CORENAME()=="CORTEXA55") tree "OSPI1" base ad:0x30020000 group.long 0x0++0x2B line.long 0x0 "CONFIG_REG,Octal-SPI Configuration Register" rbitfld.long 0x0 31. "IDLE_FLD,Serial interface and low level SPI pipeline is IDLE: This is a STATUS read-only bit. Note this is a retimed signal so there will be some inherent delay on the generation of this status signal." "0,1" newline bitfld.long 0x0 30. "DUAL_BYTE_OPCODE_EN_FLD,Dual-byte Opcode Mode enable bit This bit is to be set in case the target Flash Device supports dual byte opcode (i.e. Macronix MX25). It is applicable for Octal I/O Mode or Protocol only so should be set back to low if the device.." "0,1" newline bitfld.long 0x0 29. "CRC_ENABLE_FLD,CRC enable bit This bit is to be set in case the target Flash Device supports CRC (Macronix MX25). It is applicable for Octal DDR Protocol only so should be set back to low if the device is configured to work in another SPI Mode." "0,1" newline bitfld.long 0x0 28. "FLIPPER_ENABLE_FLD,Flip enable bit This bit is to be set in case the target Flash Device supports data slices swapped in order of D1 D0 D3 D2 etc. It is applicable for DTR-OPI Mode of Macronix MX25 devices." "0,1" newline rbitfld.long 0x0 26.--27. "CONFIG_RESV2_FLD,Reserved" "0,1,2,3" newline bitfld.long 0x0 25. "PIPELINE_PHY_FLD,Pipeline PHY Mode enable: This bit is relevant only for configuration with PHY Module. It should be asserted to '1' between consecutive PHY pipeline reads transfers and de-asserted to '0' otherwise." "0,1" newline bitfld.long 0x0 24. "ENABLE_DTR_PROTOCOL_FLD,Enable DTR Protocol: This bit should be set if device is configured to work in DTR protocol." "0,1" newline bitfld.long 0x0 23. "ENABLE_AHB_DECODER_FLD,Enable AHB Decoder: Value=0 : Active slave is selected based on Peripheral Chip Select Lines (bits [13:10]). Value=1 Active slave is selected based on actual AHB address (the partition for each device is calculated with respect to.." "Active slave is selected based on Peripheral..,?" newline hexmask.long.byte 0x0 19.--22. 1. "MSTR_BAUD_DIV_FLD,Master Mode Baud Rate Divisor: SPI baud rate = (master reference clock) baud_rate_divisor" newline bitfld.long 0x0 18. "ENTER_XIP_MODE_IMM_FLD,Enter XIP Mode immediately: Value=0 : If XIP is enabled then setting to 0 will cause the controller to exit XIP mode on the next READ instruction. Value=1 : Operate the device in XIP mode immediately Use this register when the.." "If XIP is enabled,Operate the device in XIP mode immediately Use.." newline bitfld.long 0x0 17. "ENTER_XIP_MODE_FLD,Enter XIP Mode on next READ: Value=0 : If XIP is enabled then setting to 0 will cause the controller to exit XIP mode on the next READ instruction. Value=1 : If XIP is disabled then setting to ?1? will inform the controller that the.." "If XIP is enabled,If XIP is disabled" newline bitfld.long 0x0 16. "ENB_AHB_ADDR_REMAP_FLD,Enable AHB Address Re-mapping: (Direct Access Mode Only) When set to 1 the incoming AHB address will be adapted and sent to the FLASH device as (address + N) where N is the value stored in the remap address register." "0,1" newline bitfld.long 0x0 15. "ENB_DMA_IF_FLD,Enable DMA Peripheral Interface: Set to 1 to enable the DMA handshaking logic. When enabled the controller will trigger DMA transfer requests via the DMA peripheral interface. Set to 0 to disable" "0,1" newline bitfld.long 0x0 14. "WR_PROT_FLASH_FLD,Write Protect Flash Pin: Set to drive the Write Protect pin of the FLASH device. This is resynchronized to the generated memory clock as necessary." "0,1" newline hexmask.long.byte 0x0 10.--13. 1. "PERIPH_CS_LINES_FLD,Peripheral Chip Select Lines: Peripheral chip select lines If pdec = 0 ss[3:0] are output thus: ss[3:0] n_ss_out[3:0] xxx0 1110 xx01 1101 x011 1011 0111 0111 1111 1111 (no peripheral selected) else ss[3:0] directly drives n_ss_out[3:0]" newline bitfld.long 0x0 9. "PERIPH_SEL_DEC_FLD,Peripheral select decode: 0 : only 1 of 4 selects n_ss_out[3:0] is active 1 : allow external 4-to-16 decode (n_ss_out = ss)" "only 1 of 4 selects n_ss_out[3:0] is active,allow external 4-to-16 decode" newline bitfld.long 0x0 8. "ENB_LEGACY_IP_MODE_FLD,Legacy IP Mode Enable: 0 : Use Direct Access Controller/Indirect Access Controller 1 : legacy Mode is enabled. In this mode any write to the controller via the AHB interface is serialized and sent to the FLASH device. Any valid.." "Use Direct Access Controller/Indirect Access..,legacy Mode is enabled" newline bitfld.long 0x0 7. "ENB_DIR_ACC_CTLR_FLD,Enable Direct Access Controller: 0 : disable the Direct Access Controller once current transfer of the data word (FF_W) is complete. 1 : enable the Direct Access Controller When the Direct Access Controller and Indirect Access.." "disable the Direct Access Controller once..,enable the Direct Access Controller When the.." newline bitfld.long 0x0 6. "RESET_CFG_FLD,RESET pin configuration: 0 = RESET feature on DQ3 pin of the device 1 = RESET feature on dedicated pin of the device (controlling of 5th bit influences on reset_out output)" "RESET feature on DQ3 pin of the device,RESET feature on dedicated pin of the device" newline bitfld.long 0x0 5. "RESET_PIN_FLD,Set to drive the RESET pin of the FLASH device and reset for de-activation of the RESET pin feature" "0,1" newline bitfld.long 0x0 4. "HOLD_PIN_FLD,Set to drive the HOLD pin of the FLASH device and reset for de-activation of the HOLD pin feature" "0,1" newline bitfld.long 0x0 3. "PHY_MODE_ENABLE_FLD,PHY mode enable: When enabled the controller is informed that PHY Module is to be used for handling SPI transfers. This bit is relevant only for configuration with PHY Module. Note: - When changing this bit field software should.." "0,1" newline bitfld.long 0x0 2. "SEL_CLK_PHASE_FLD,Select Clock Phase: Selects whether the clock is in an active or inactive phase outside the SPI word. 0 : the SPI clock is active outside the word 1 : the SPI clock is inactive outside the word" "the SPI clock is active outside the word,the SPI clock is inactive outside the word" newline bitfld.long 0x0 1. "SEL_CLK_POL_FLD,Clock polarity outside SPI word: 0 : the SPI clock is quiescent low 1 : the SPI clock is quiescent high" "the SPI clock is quiescent low,the SPI clock is quiescent high" newline bitfld.long 0x0 0. "ENB_SPI_FLD,Octal-SPI Enable: 0 : disable the Octal-SPI once current transfer of the data word (FF_W) is complete. 1 : enable the Octal-SPI when spi_enable = 0 all output enables are inactive and all pins are set to input mode." "disable the Octal-SPI,enable the Octal-SPI" line.long 0x4 "DEV_INSTR_RD_CONFIG_REG,Device Read Instruction Configuration Register" rbitfld.long 0x4 29.--31. "RD_INSTR_RESV5_FLD,Reserved" "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x4 24.--28. 1. "DUMMY_RD_CLK_CYCLES_FLD,Dummy Read Clock Cycles: Number of dummy clock cycles required by device for read instruction." newline rbitfld.long 0x4 21.--23. "RD_INSTR_RESV4_FLD,Reserved" "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 20. "MODE_BIT_ENABLE_FLD,Mode Bit Enable: Set this field to 1 to ensure that the mode bits as defined in the Mode Bit Configuration register are sent following the address bytes." "0,1" newline rbitfld.long 0x4 18.--19. "RD_INSTR_RESV3_FLD,Reserved" "0,1,2,3" newline bitfld.long 0x4 16.--17. "DATA_XFER_TYPE_EXT_MODE_FLD,Data Transfer Type for Standard SPI modes: 0 : SIO mode data is shifted to the device on DQ0 only and from the device on DQ1 only 1 : Used for Dual Input/Output instructions. For data transfers DQ0 and DQ1 are used as both.." "SIO mode data is shifted to the device on DQ0..,Used for Dual Input/Output instructions,Used for Quad Input/Output instructions,Used for Quad Input/Output instructions" newline rbitfld.long 0x4 14.--15. "RD_INSTR_RESV2_FLD,Reserved" "0,1,2,3" newline bitfld.long 0x4 12.--13. "ADDR_XFER_TYPE_STD_MODE_FLD,Address Transfer Type for Standard SPI modes: 0 : Addresses can be shifted to the device on DQ0 only 1 : Addresses can be shifted to the device on DQ0 and DQ1 only 2 : Addresses can be shifted to the device on DQ0 DQ1 DQ2.." "Addresses can be shifted to the device on DQ0 only,Addresses can be shifted to the device on DQ0..,Addresses can be shifted to the device on DQ0,Addresses can be shifted to the device on DQ[7:0]" newline bitfld.long 0x4 11. "PRED_DIS_FLD,Predicted Read Disable Bit: Disable generation of predicted read when doing read accesses using Direct Mode" "0,1" newline bitfld.long 0x4 10. "DDR_EN_FLD,DDR Enable: This is to inform that opcode from rd_opcode_non_xip_fld is compliant with one of the DDR READ Commands" "0,1" newline bitfld.long 0x4 8.--9. "INSTR_TYPE_FLD,Instruction Type: 0 : Use Standard SPI mode (instruction always shifted into the device on DQ0 only) 1 : Use DIO-SPI mode (Instructions Address and Data always sent on DQ0 and DQ1) 2 : Use QIO-SPI mode (Instructions Address and Data.." "Use Standard SPI mode,Use DIO-SPI mode,Use QIO-SPI mode,Use Octal-IO-SPI mode" newline hexmask.long.byte 0x4 0.--7. 1. "RD_OPCODE_NON_XIP_FLD,Read Opcode in non-XIP mode: Read Opcode to use when not in XIP mode" line.long 0x8 "DEV_INSTR_WR_CONFIG_REG,Device Write Instruction Configuration Register" rbitfld.long 0x8 29.--31. "WR_INSTR_RESV4_FLD,Reserved" "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x8 24.--28. 1. "DUMMY_WR_CLK_CYCLES_FLD,Dummy Write Clock Cycles: Number of dummy clock cycles required by device for write instruction." newline hexmask.long.byte 0x8 18.--23. 1. "WR_INSTR_RESV3_FLD,Reserved" newline bitfld.long 0x8 16.--17. "DATA_XFER_TYPE_EXT_MODE_FLD,Data Transfer Type for Standard SPI modes: 0 : SIO mode data is shifted to the device on DQ0 only and from the device on DQ1 only 1 : Used for Dual Input/Output instructions. For data transfers DQ0 and DQ1 are used as both.." "SIO mode data is shifted to the device on DQ0..,Used for Dual Input/Output instructions,Used for Quad Input/Output instructions,Used for Octal Input/Output instructions" newline rbitfld.long 0x8 14.--15. "WR_INSTR_RESV2_FLD,Reserved" "0,1,2,3" newline bitfld.long 0x8 12.--13. "ADDR_XFER_TYPE_STD_MODE_FLD,Address Transfer Type for Standard SPI modes: 0 : Addresses can be shifted to the device on DQ0 only 1 : Addresses can be shifted to the device on DQ0 and DQ1 only 2 : Addresses can be shifted to the device on DQ0 DQ1 DQ2.." "Addresses can be shifted to the device on DQ0 only,Addresses can be shifted to the device on DQ0..,Addresses can be shifted to the device on DQ0,Addresses can be shifted to the device on DQ[7:0]" newline rbitfld.long 0x8 9.--11. "WR_INSTR_RESV1_FLD,Reserved" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 8. "WEL_DIS_FLD,WEL Disable: This is to turn off automatic issuing of WEL Command before write operation for DAC or INDAC" "0,1" newline hexmask.long.byte 0x8 0.--7. 1. "WR_OPCODE_FLD,Write Opcode" line.long 0xC "DEV_DELAY_REG,Octal-SPI Device Delay Register: This register is used to introduce relative delays into the generation of the master output signals. All timings are defined in cycles of the SPI REFERENCE CLOCK/ext_clk. defined in this table as SPI master.." hexmask.long.byte 0xC 24.--31. 1. "D_NSS_FLD,Clock Delay for Chip Select Deassert: Delay in master reference clocks for the length that the master mode chip select outputs are de-asserted between transactions. The minimum delay is always SCLK period to ensure the chip select is never.." newline hexmask.long.byte 0xC 16.--23. 1. "D_BTWN_FLD,Clock Delay for Chip Select Deactivation: Delay in master reference clocks between one chip select being de-activated and the activation of another. This is used to ensure a quiet period between the selection of two different slaves and.." newline hexmask.long.byte 0xC 8.--15. 1. "D_AFTER_FLD,Clock Delay for Last Transaction Bit: Delay in master reference clocks between last bit of current transaction and deasserting the device chip select (n_ss_out). By default the chip select will be deasserted on the cycle following the.." newline hexmask.long.byte 0xC 0.--7. 1. "D_INIT_FLD,Clock Delay with n_ss_out: Delay in master reference clocks between setting n_ss_out low and first bit transfer." line.long 0x10 "RD_DATA_CAPTURE_REG,Read Data Capture Register" hexmask.long.word 0x10 20.--31. 1. "RD_DATA_RESV3_FLD,Reserved" newline hexmask.long.byte 0x10 16.--19. 1. "DDR_READ_DELAY_FLD,DDR read delay: Delay the transmitted data by the programmed number of ref_clk cycles.This field is only relevant when DDR Read Command is executed. Otherwise can be ignored." newline hexmask.long.byte 0x10 9.--15. 1. "RD_DATA_RESV2_FLD,Reserved" newline bitfld.long 0x10 8. "DQS_ENABLE_FLD,DQS enable bit: If enabled signal from DQS input is driven into RX DLL and is used for data capturing in PHY Mode rather than internally generated gated ref_clk.." "0,1" newline rbitfld.long 0x10 6.--7. "RD_DATA_RESV1_FLD,Reserved" "0,1,2,3" newline bitfld.long 0x10 5. "SAMPLE_EDGE_SEL_FLD,Sample edge selection: Choose edge on which data outputs from flash memory will be sampled" "0,1" newline hexmask.long.byte 0x10 1.--4. 1. "DELAY_FLD,Read Delay: Delay the read data capturing logic by the programmed number of ref_clk cycles" newline bitfld.long 0x10 0. "BYPASS_FLD,Bypass the adapted loopback clock circuit" "0,1" line.long 0x14 "DEV_SIZE_CONFIG_REG,Device Size Configuration Register" rbitfld.long 0x14 29.--31. "DEV_SIZE_RESV_FLD,Reserved" "0,1,2,3,4,5,6,7" newline bitfld.long 0x14 27.--28. "MEM_SIZE_ON_CS3_FLD,Size of Flash Device connected to CS[3] pin: Value=00 : size of 512Mb. Value=01 : size of 1Gb. Value=10 : size of 2Gb. Value=11 : size of 4Gb." "size of 512Mb,size of 1Gb,?,?" newline bitfld.long 0x14 25.--26. "MEM_SIZE_ON_CS2_FLD,Size of Flash Device connected to CS[2] pin: Value=00 : size of 512Mb. Value=01 : size of 1Gb. Value=10 : size of 2Gb. Value=11 : size of 4Gb." "size of 512Mb,size of 1Gb,?,?" newline bitfld.long 0x14 23.--24. "MEM_SIZE_ON_CS1_FLD,Size of Flash Device connected to CS[1] pin: Value=00 : size of 512Mb. Value=01 : size of 1Gb. Value=10 : size of 2Gb. Value=11 : size of 4Gb." "size of 512Mb,size of 1Gb,?,?" newline bitfld.long 0x14 21.--22. "MEM_SIZE_ON_CS0_FLD,Size of Flash Device connected to CS[0] pin: Value=00 : size of 512Mb. Value=01 : size of 1Gb. Value=10 : size of 2Gb. Value=11 : size of 4Gb." "size of 512Mb,size of 1Gb,?,?" newline hexmask.long.byte 0x14 16.--20. 1. "BYTES_PER_SUBSECTOR_FLD,Number of bytes per Block. This is required by the controller for performing the write protection logic. The number of bytes per block must be a power of 2 number." newline hexmask.long.word 0x14 4.--15. 1. "BYTES_PER_DEVICE_PAGE_FLD,Number of bytes per device page. This is required by the controller for performing FLASH writes up to and across page boundaries." newline hexmask.long.byte 0x14 0.--3. 1. "NUM_ADDR_BYTES_FLD,Number of address bytes. A value of 0 indicates 1 byte." line.long 0x18 "SRAM_PARTITION_CFG_REG,SRAM Partition Configuration Register" hexmask.long.tbyte 0x18 8.--31. 1. "SRAM_PARTITION_RESV_FLD,Reserved" newline hexmask.long.byte 0x18 0.--7. 1. "ADDR_FLD,Indirect Read Partition Size: Defines the size of the indirect read partition in the SRAM in units of SRAM locations. By default half of the SRAM is reserved for indirect read operation and half for indirect write. The size of this register.." line.long 0x1C "IND_AHB_ADDR_TRIGGER_REG,Indirect AHB Address Trigger Register" hexmask.long 0x1C 0.--31. 1. "ADDR_FLD,This is the base address that will be used by the AHB controller. When the incoming AHB read access address matches a range of addresses from this trigger address to the trigger address + 15 then the AHB request will be completed by fetching.." line.long 0x20 "DMA_PERIPH_CONFIG_REG,DMA Peripheral Configuration Register" hexmask.long.tbyte 0x20 12.--31. 1. "DMA_PERIPH_RESV2_FLD,Reserved" newline hexmask.long.byte 0x20 8.--11. 1. "NUM_BURST_REQ_BYTES_FLD,Number of Burst Bytes: Number of bytes in a burst type request on the DMA peripheral request. A programmed value of 0 represents a single byte. This should be setup before starting the indirect read or write operation. The actual.." newline hexmask.long.byte 0x20 4.--7. 1. "DMA_PERIPH_RESV1_FLD,Reserved" newline hexmask.long.byte 0x20 0.--3. 1. "NUM_SINGLE_REQ_BYTES_FLD,Number of Single Bytes: Number of bytes in a single type request on the DMA peripheral request. A programmed value of 0 represents a single byte. This should be setup before starting the indirect read or write operation. The.." line.long 0x24 "REMAP_ADDR_REG,Remap Address Register" hexmask.long 0x24 0.--31. 1. "VALUE_FLD,This register is used to remap an incoming AHB address to a different address used by the FLASH device." line.long 0x28 "MODE_BIT_CONFIG_REG,Mode Bit Configuration Register" hexmask.long.byte 0x28 24.--31. 1. "RX_CRC_DATA_LOW_FLD,RX CRC data (lower) The first CRC byte returned after RX data chunk." newline hexmask.long.byte 0x28 16.--23. 1. "RX_CRC_DATA_UP_FLD,RX CRC data (upper) The second CRC byte returned after RX data chunk." newline bitfld.long 0x28 15. "CRC_OUT_ENABLE_FLD,CRC# output enable bit When enabled the controller expects the Flash Device to toggle CRC data on both SPI clock edges in CRC->CRC# sequence and calculates CRC compliance accordingly." "0,1" newline hexmask.long.byte 0x28 11.--14. 1. "MODE_BIT_RESV1_FLD,Reserved" newline bitfld.long 0x28 8.--10. "CHUNK_SIZE_FLD,It defines size of chunk after which CRC data is expected to show up on the SPI interface for write and read data transfers." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x28 0.--7. 1. "MODE_FLD,These are the 8 mode bits that are sent to the device following the address bytes if mode bit transmission has been enabled." rgroup.long 0x2C++0x3 line.long 0x0 "SRAM_FILL_REG,SRAM Fill Register" hexmask.long.word 0x0 16.--31. 1. "SRAM_FILL_INDAC_WRITE_FLD,SRAM Fill Level (Indirect Write Partition): Identifies the current fill level of the SRAM Indirect Write partition" newline hexmask.long.word 0x0 0.--15. 1. "SRAM_FILL_INDAC_READ_FLD,SRAM Fill Level (Indirect Read Partition): Identifies the current fill level of the SRAM Indirect Read partition" group.long 0x30++0x17 line.long 0x0 "TX_THRESH_REG,TX Threshold Register" hexmask.long 0x0 5.--31. 1. "TX_THRESH_RESV_FLD,Reserved" newline hexmask.long.byte 0x0 0.--4. 1. "LEVEL_FLD,Defines the level at which the small TX FIFO not full interrupt is generated" line.long 0x4 "RX_THRESH_REG,RX Threshold Register" hexmask.long 0x4 5.--31. 1. "RX_THRESH_RESV_FLD,Reserved" newline hexmask.long.byte 0x4 0.--4. 1. "LEVEL_FLD,Defines the level at which the small RX FIFO not empty interrupt is generated" line.long 0x8 "WRITE_COMPLETION_CTRL_REG,Write Completion Control Register: This register defines how the controller will poll the device following a write transfer" hexmask.long.byte 0x8 24.--31. 1. "POLL_REP_DELAY_FLD,Defines additional delay for maintain Chip Select de-asserted during auto-polling phase" newline hexmask.long.byte 0x8 16.--23. 1. "POLL_COUNT_FLD,Defines the number of times the controller should expect to see a true result from the polling in successive reads of the device register." newline bitfld.long 0x8 15. "ENABLE_POLLING_EXP_FLD,Set to '1' for enabling auto-polling expiration." "0,1" newline bitfld.long 0x8 14. "DISABLE_POLLING_FLD,This switches off the automatic polling function" "0,1" newline bitfld.long 0x8 13. "POLLING_POLARITY_FLD,Defines the polling polarity. If '1' then the write transfer to the device will be complete if the polled bit is equal to '1'. If '0' then the write transfer to the device will be complete if the polled bit is equal to '0'." "0,1" newline rbitfld.long 0x8 12. "WR_COMP_CTRL_RESV1_FLD,Reserved" "0,1" newline bitfld.long 0x8 11. "POLLING_ADDR_EN_FLD,Enables address phase of auto-polling (Read Status) command." "0,1" newline bitfld.long 0x8 8.--10. "POLLING_BIT_INDEX_FLD,Defines the bit index that should be polled. A value of 010 means that bit 2 of the returned data will be polled for.A value of 111 means that bit 7 of the returned data will be polled for." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x8 0.--7. 1. "OPCODE_FLD,Defines the opcode that should be issued by the controller when it is automatically polling for device program completion. This command is issued followed all device write operations. By default this will poll the standard device STATUS.." line.long 0xC "NO_OF_POLLS_BEF_EXP_REG,Polling Expiration Register" hexmask.long 0xC 0.--31. 1. "NO_OF_POLLS_BEF_EXP_FLD,Number of polls cycles before expiration" line.long 0x10 "IRQ_STATUS_REG,Interrupt Status Register: The status fields in this register are set when the described event occurs and the interrupt is enabled in the mask register. When any of these bit fields are set. the interrupt output is asserted high. The.." hexmask.long.word 0x10 21.--31. 1. "IRQ_STAT_RESV_FLD,Reserved" newline bitfld.long 0x10 20. "HYPER_INT_FLD,HyperFlash interrupt This interrupt informs the system that Flash Device reported interrupt on its INT# output" "0,1" newline bitfld.long 0x10 19. "ECC_FAIL_FLD,ECC failure This interrupt informs the system that Flash Device reported ECC error." "0,1" newline bitfld.long 0x10 18. "TX_CRC_CHUNK_BRK_FLD,TX CRC chunk was broken This interrupt informs the system that program page SPI transfer was discontinued somewhere inside the chunk." "0,1" newline bitfld.long 0x10 17. "RX_CRC_DATA_VAL_FLD,RX CRC data valid New RX CRC data was captured from Flash Device" "0,1" newline bitfld.long 0x10 16. "RX_CRC_DATA_ERR_FLD,RX CRC data error CRC data from Flash Device does not correspond to the one dynamically calculated by the controller." "0,1" newline rbitfld.long 0x10 15. "IRQ_STAT_RESV1_FLD,Reserved" "0,1" newline bitfld.long 0x10 14. "STIG_REQ_INT_FLD,The controller is ready for getting another STIG request." "0,1" newline bitfld.long 0x10 13. "POLL_EXP_INT_FLD,The maximum number of programmed polls cycles is expired" "0,1" newline bitfld.long 0x10 12. "INDRD_SRAM_FULL_FLD,Indirect Read Partition overflow: Indirect Read Partition of SRAM is full and unable to immediately complete indirect operation" "0,1" newline bitfld.long 0x10 11. "RX_FIFO_FULL_FLD,Small RX FIFO full: Current FIFO status can be ignored in non-SPI legacy mode 0 : FIFO is not full 1 : FIFO is full" "FIFO is not full,FIFO is full" newline bitfld.long 0x10 10. "RX_FIFO_NOT_EMPTY_FLD,Small RX FIFO not empty: Current FIFO status can be ignored in non-SPI legacy mode 0 : FIFO has less than RX THRESHOLD entries 1 : FIFO has >= THRESHOLD entries" "FIFO has less than RX THRESHOLD entries,FIFO has >= THRESHOLD entries" newline bitfld.long 0x10 9. "TX_FIFO_FULL_FLD,Small TX FIFO full: Current FIFO status can be ignored in non-SPI legacy mode 0 : FIFO is not full 1 : FIFO is full" "FIFO is not full,FIFO is full" newline bitfld.long 0x10 8. "TX_FIFO_NOT_FULL_FLD,Small TX FIFO not full: Current FIFO status can be ignored in non-SPI legacy mode 0 : FIFO has >= THRESHOLD entries 1 : FIFO has less than THRESHOLD entries" "FIFO has >= THRESHOLD entries,FIFO has less than THRESHOLD entries" newline bitfld.long 0x10 7. "RECV_OVERFLOW_FLD,Receive Overflow: This should only occur in Legacy SPI mode. Set if an attempt is made to push the RX FIFO when it is full. This bit is reset only by a system reset and cleared only when this register is read. If a new push to the RX.." "no overflow has been detected,an overflow has occurred" newline bitfld.long 0x10 6. "INDIRECT_XFER_LEVEL_BREACH_FLD,Indirect Transfer Watermark Level Breached" "0,1" newline bitfld.long 0x10 5. "ILLEGAL_ACCESS_DET_FLD,Illegal AHB access has been detected. AHB wrapping bursts and the use of SPLIT/RETRY accesses will cause this error interrupt to trigger." "0,1" newline bitfld.long 0x10 4. "PROT_WR_ATTEMPT_FLD,Write to protected area was attempted and rejected." "0,1" newline bitfld.long 0x10 3. "INDIRECT_TRANSFER_REJECT_FLD,Indirect operation was requested but could not be accepted. Two indirect operations already in storage." "0,1" newline bitfld.long 0x10 2. "INDIRECT_OP_DONE_FLD,Indirect Operation Complete: Controller has completed last triggered indirect operation" "0,1" newline bitfld.long 0x10 1. "UNDERFLOW_DET_FLD,Underflow Detected: 0 : no underflow has been detected 1 : underflow is detected and an attempt to transfer data is made when the small TX FIFO is empty. This may occur when AHB write data is being supplied too slowly to keep up with.." "no underflow has been detected,underflow is detected and an attempt to transfer.." newline bitfld.long 0x10 0. "MODE_M_FAIL_FLD,Mode M Failure: Mode M failure indicates the voltage on pin n_ss_in is inconsistent with the SPI mode. Set =1 if n_ss_in is low in master mode (multi-master contention). These conditions will clear the spi_enable bit and disable the SPI." "no mode fault has been detected,a mode fault has occurred" line.long 0x14 "IRQ_MASK_REG,Interrupt Mask: 0 : the interrupt for the corresponding interrupt status register bit is disabled. 1 : the interrupt for the corresponding interrupt status register bit is enabled." hexmask.long.word 0x14 21.--31. 1. "IRQ_MASK_RESV_FLD,Reserved" newline bitfld.long 0x14 20. "HYPER_INT_MASK_FLD,HyperFlash interrupt Mask" "0,1" newline bitfld.long 0x14 19. "ECC_FAIL_MASK_FLD,ECC failure Mask" "0,1" newline bitfld.long 0x14 18. "TX_CRC_CHUNK_BRK_MASK_FLD,TX CRC chunk was broken Mask" "0,1" newline bitfld.long 0x14 17. "RX_CRC_DATA_VAL_MASK_FLD,RX CRC data valid Mask" "0,1" newline bitfld.long 0x14 16. "RX_CRC_DATA_ERR_MASK_FLD,RX CRC data error Mask" "0,1" newline rbitfld.long 0x14 15. "IRQ_MASK_RESV1_FLD,Reserved" "0,1" newline bitfld.long 0x14 14. "STIG_REQ_MASK_FLD,STIG request completion Mask" "0,1" newline bitfld.long 0x14 13. "POLL_EXP_INT_MASK_FLD,Polling expiration detected Mask" "0,1" newline bitfld.long 0x14 12. "INDRD_SRAM_FULL_MASK_FLD,Indirect Read Partition overflow mask" "0,1" newline bitfld.long 0x14 11. "RX_FIFO_FULL_MASK_FLD,Small RX FIFO full Mask" "0,1" newline bitfld.long 0x14 10. "RX_FIFO_NOT_EMPTY_MASK_FLD,Small RX FIFO not empty Mask" "0,1" newline bitfld.long 0x14 9. "TX_FIFO_FULL_MASK_FLD,Small TX FIFO full Mask" "0,1" newline bitfld.long 0x14 8. "TX_FIFO_NOT_FULL_MASK_FLD,Small TX FIFO not full Mask" "0,1" newline bitfld.long 0x14 7. "RECV_OVERFLOW_MASK_FLD,Receive Overflow Mask" "0,1" newline bitfld.long 0x14 6. "INDIRECT_XFER_LEVEL_BREACH_MASK_FLD,Transfer Watermark Breach Mask" "0,1" newline bitfld.long 0x14 5. "ILLEGAL_ACCESS_DET_MASK_FLD,Illegal Access Detected Mask" "0,1" newline bitfld.long 0x14 4. "PROT_WR_ATTEMPT_MASK_FLD,Protected Area Write Attempt Mask" "0,1" newline bitfld.long 0x14 3. "INDIRECT_TRANSFER_REJECT_MASK_FLD,Indirect Read Reject Mask" "0,1" newline bitfld.long 0x14 2. "INDIRECT_OP_DONE_MASK_FLD,Indirect Complete Mask" "0,1" newline bitfld.long 0x14 1. "UNDERFLOW_DET_MASK_FLD,Underflow Detected Mask" "0,1" newline bitfld.long 0x14 0. "MODE_M_FAIL_MASK_FLD,Mode M Failure Mask" "0,1" group.long 0x50++0xB line.long 0x0 "LOWER_WR_PROT_REG,Lower Write Protection Register" hexmask.long 0x0 0.--31. 1. "SUBSECTOR_FLD,The block number that defines the lower block in the range of blocks that is to be locked from writing. The definition of a block in terms of number of bytes is programmable via the Device Size Configuration register." line.long 0x4 "UPPER_WR_PROT_REG,Upper Write Protection Register" hexmask.long 0x4 0.--31. 1. "SUBSECTOR_FLD,The block number that defines the upper block in the range of blocks that is to be locked from writing. The definition of a block in terms of number of bytes is programmable via the Device Size Configuration register." line.long 0x8 "WR_PROT_CTRL_REG,Write Protection Control Register" hexmask.long 0x8 2.--31. 1. "WR_PROT_CTRL_RESV_FLD,Reserved" newline bitfld.long 0x8 1. "ENB_FLD,Write Protection Enable Bit: When set to 1 any AHB write access with an address within the protection region defined in the lower and upper write protection registers is rejected. An AHB error response is generated and an interrupt source.." "0,1" newline bitfld.long 0x8 0. "INV_FLD,Write Protection Inversion Bit: When set to 1 the protection region defined in the lower and upper write protection registers is inverted meaning it is the region that the system is permitted to write to. When set to 0 the protection region.." "0,1" group.long 0x60++0x23 line.long 0x0 "INDIRECT_READ_XFER_CTRL_REG,Indirect Read Transfer Control Register" hexmask.long.tbyte 0x0 8.--31. 1. "INDIR_RD_XFER_RESV_FLD,Reserved" newline rbitfld.long 0x0 6.--7. "NUM_IND_OPS_DONE_FLD,This field contains the number of indirect operations which have been completed. This is used in conjunction with the indirect completion status field (bit 5). It is incremented by hardware when an indirect operation has completed." "0,1,2,3" newline bitfld.long 0x0 5. "IND_OPS_DONE_STATUS_FLD,Indirect Completion Status: This field is set to 1 when an indirect operation has completed. Write a 1 to this field to clear it." "0,1" newline rbitfld.long 0x0 4. "RD_QUEUED_FLD,Two indirect read operations have been queued" "0,1" newline bitfld.long 0x0 3. "SRAM_FULL_FLD,SRAM Full: SRAM full and unable to immediately complete an indirect operation. Write a 1 to this field to clear it.\'; indirect operation (status)" "0,1" newline rbitfld.long 0x0 2. "RD_STATUS_FLD,Indirect Read Status: Indirect read operation in progress (status)" "0,1" newline bitfld.long 0x0 1. "CANCEL_FLD,Cancel Indirect Read: Writing a 1 to this bit will cancel all ongoing indirect read operations." "0,1" newline bitfld.long 0x0 0. "START_FLD,Start Indirect Read: Writing a 1 to this bit will trigger an indirect read operation. The assumption is that the indirect start address and the indirect number of bytes register is setup before triggering the indirect read operation." "0,1" line.long 0x4 "INDIRECT_READ_XFER_WATERMARK_REG,Indirect Read Transfer Watermark Register" hexmask.long 0x4 0.--31. 1. "LEVEL_FLD,Watermark Value: This represents the minimum fill level of the SRAM before a DMA peripheral access is permitted. When the SRAM fill level passes the watermark an interrupt is also generated. This field can be disabled by writing a value of all.." line.long 0x8 "INDIRECT_READ_XFER_START_REG,Indirect Read Transfer Start Address Register" hexmask.long 0x8 0.--31. 1. "ADDR_FLD,This is the start address from which the indirect access will commence its READ operation." line.long 0xC "INDIRECT_READ_XFER_NUM_BYTES_REG,Indirect Read Transfer Number Bytes Register" hexmask.long 0xC 0.--31. 1. "VALUE_FLD,This is the number of bytes that the indirect access will consume. This can be bigger than the configured size of SRAM." line.long 0x10 "INDIRECT_WRITE_XFER_CTRL_REG,Indirect Write Transfer Control Register" hexmask.long.tbyte 0x10 8.--31. 1. "INDIR_WR_XFER_RESV2_FLD,Reserved" newline rbitfld.long 0x10 6.--7. "NUM_IND_OPS_DONE_FLD,This field contains the number of indirect operations which have been completed. This is used in conjunction with the indirect completion status field (bit 5). It is incremented by hardware when an indirect operation has completed." "0,1,2,3" newline bitfld.long 0x10 5. "IND_OPS_DONE_STATUS_FLD,Indirect Completion Status: This field is set to 1 when an indirect operation has completed. Write a 1 to this field to clear it." "0,1" newline rbitfld.long 0x10 4. "WR_QUEUED_FLD,Two indirect write operations have been queued" "0,1" newline rbitfld.long 0x10 3. "INDIR_WR_XFER_RESV1_FLD,Reserved" "0,1" newline rbitfld.long 0x10 2. "WR_STATUS_FLD,Indirect Write Status: Indirect write operation in progress (status)" "0,1" newline bitfld.long 0x10 1. "CANCEL_FLD,Cancel Indirect Write: Writing a 1 to this bit will cancel all ongoing indirect write operations." "0,1" newline bitfld.long 0x10 0. "START_FLD,Start Indirect Write: Writing a 1 to this bit will trigger an indirect write operation. The assumption is that the indirect start address and the indirect number of bytes register is setup before triggering the indirect write operation." "0,1" line.long 0x14 "INDIRECT_WRITE_XFER_WATERMARK_REG,Indirect Write Transfer Watermark Register" hexmask.long 0x14 0.--31. 1. "LEVEL_FLD,Watermark Value: This represents the maximum fill level of the SRAM before a DMA peripheral access is permitted. When the SRAM fill level falls below the watermark an interrupt is also generated. This field can be disabled by writing a value.." line.long 0x18 "INDIRECT_WRITE_XFER_START_REG,Indirect Write Transfer Start Address Register" hexmask.long 0x18 0.--31. 1. "ADDR_FLD,Start of Indirect Access: This is the start address from which the indirect access will commence its READ operation." line.long 0x1C "INDIRECT_WRITE_XFER_NUM_BYTES_REG,Indirect Write Transfer Number Bytes Register" hexmask.long 0x1C 0.--31. 1. "VALUE_FLD,Indirect Number of Bytes: This is the number of bytes that the indirect access will consume. This can be bigger than the configured size of SRAM." line.long 0x20 "INDIRECT_TRIGGER_ADDR_RANGE_REG,Indirect Trigger Address Range Register" hexmask.long 0x20 4.--31. 1. "IND_RANGE_RESV1_FLD,Reserved" newline hexmask.long.byte 0x20 0.--3. 1. "IND_RANGE_WIDTH_FLD,This is the address offset of Indirect Trigger Address Register." group.long 0x8C++0xB line.long 0x0 "FLASH_COMMAND_CTRL_MEM_REG,Flash Command Control Memory Register" rbitfld.long 0x0 29.--31. "FLASH_COMMAND_CTRL_MEM_RESV1_FLD,Reserved" "0,1,2,3,4,5,6,7" newline hexmask.long.word 0x0 20.--28. 1. "MEM_BANK_ADDR_FLD,The address of the Memory Bank which data will be read from." newline rbitfld.long 0x0 19. "FLASH_COMMAND_CTRL_MEM_RESV2_FLD,Reserved" "0,1" newline bitfld.long 0x0 16.--18. "NB_OF_STIG_READ_BYTES_FLD,It defines the number of read bytes for the extended STIG." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x0 8.--15. 1. "MEM_BANK_READ_DATA_FLD,Last requested data from the STIG Memory Bank." newline hexmask.long.byte 0x0 2.--7. 1. "FLASH_COMMAND_CTRL_MEM_RESV3_FLD,Reserved" newline rbitfld.long 0x0 1. "MEM_BANK_REQ_IN_PROGRESS_FLD,Memory Bank data request in progress." "0,1" newline bitfld.long 0x0 0. "TRIGGER_MEM_BANK_REQ_FLD,Trigger the Memory Bank data request." "0,1" line.long 0x4 "FLASH_CMD_CTRL_REG,Flash Command Control Register" hexmask.long.byte 0x4 24.--31. 1. "CMD_OPCODE_FLD,Command Opcode: The command opcode field should be setup before triggering the command. For example 0x20 maps to SubSector Erase. Writing to the execute field (bit 0) of this register launches the command. NOTE : Using this approach to.." newline bitfld.long 0x4 23. "ENB_READ_DATA_FLD,Read Data Enable: Set to 1 if the command specified in the command opcode field (bits 31:24) requires read data bytes to be received from the device." "0,1" newline bitfld.long 0x4 20.--22. "NUM_RD_DATA_BYTES_FLD,Number of Read Data Bytes: Up to 8 data bytes may be read using this command. Set to 0 for 1 byte and 7 for 8 bytes." "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 19. "ENB_COMD_ADDR_FLD,Command Address Enable: Set to 1 if the command specified in bits 31:24 requires an address. This should be setup before triggering the command via writing a 1 to the execute field." "0,1" newline bitfld.long 0x4 18. "ENB_MODE_BIT_FLD,Mode Bit Enable: Set to 1 to ensure the mode bits as defined in the Mode Bit Configuration register are sent following the address bytes." "0,1" newline bitfld.long 0x4 16.--17. "NUM_ADDR_BYTES_FLD,Number of Address Bytes: Set to the number of address bytes required (the address itself is programmed in the FLASH COMMAND ADDRESS REGISTERS). This should be setup before triggering the command via bit 0 of this register. 2'b00 : 1.." "0,1,2,3" newline bitfld.long 0x4 15. "ENB_WRITE_DATA_FLD,Write Data Enable: Set to 1 if the command specified in the command opcode field requires write data bytes to be sent to the device." "0,1" newline bitfld.long 0x4 12.--14. "NUM_WR_DATA_BYTES_FLD,Number of Write Data Bytes: Up to 8 Data bytes may be written using this command Set to 0 for 1 byte 7 for 8 bytes." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x4 7.--11. 1. "NUM_DUMMY_CYCLES_FLD,Number of Dummy cycles: Set to the number of dummy cycles required. This should be setup before triggering the command via the execute field of this register." newline hexmask.long.byte 0x4 3.--6. 1. "FLASH_CMD_CTRL_RESV1_FLD,Reserved" newline bitfld.long 0x4 2. "STIG_MEM_BANK_EN_FLD,STIG Memory Bank enable bit." "0,1" newline rbitfld.long 0x4 1. "CMD_EXEC_STATUS_FLD,Command execution in progress." "0,1" newline bitfld.long 0x4 0. "CMD_EXEC_FLD,Execute the command." "0,1" line.long 0x8 "FLASH_CMD_ADDR_REG,Flash Command Address Register" hexmask.long 0x8 0.--31. 1. "ADDR_FLD,Command Address: This should be setup before triggering the command with execute field (bit 0) of the Flash Command Control register. It is the address used by the command specified in the opcode field (bits 31:24) of the Flash Command Control.." rgroup.long 0xA0++0x7 line.long 0x0 "FLASH_RD_DATA_LOWER_REG,Flash Command Read Data Register (Lower)" hexmask.long 0x0 0.--31. 1. "DATA_FLD,This is the data that is returned by the flash device for any status or configuration read operation carried out by triggering the event in the control register. The register will be valid when the polling bit in the control register is low." line.long 0x4 "FLASH_RD_DATA_UPPER_REG,Flash Command Read Data Register (Upper)" hexmask.long 0x4 0.--31. 1. "DATA_FLD,This is the data that is returned by the FLASH device for any status or configuration read operation carried out by triggering the event in the control register. The register will be valid when the polling bit in the control register is low." group.long 0xA8++0x13 line.long 0x0 "FLASH_WR_DATA_LOWER_REG,Flash Command Write Data Register (Lower)" hexmask.long 0x0 0.--31. 1. "DATA_FLD,Command Write Data Lower Byte: This is the command write data lower byte. This should be setup before triggering the command with execute field (bit 0) of the Flash Command Control register. It is the data that is to be written to the flash for.." line.long 0x4 "FLASH_WR_DATA_UPPER_REG,Flash Command Write Data Register (Upper)" hexmask.long 0x4 0.--31. 1. "DATA_FLD,Command Write Data Upper Byte: This is the command write data upper byte. This should be setup before triggering the command with execute field (bit 0) of the Flash Command Control register. It is the data that is to be written to the flash for.." line.long 0x8 "POLLING_FLASH_STATUS_REG,Polling Flash Status Register" hexmask.long.word 0x8 21.--31. 1. "DEVICE_STATUS_RSVD_FLD2,Reserved" newline hexmask.long.byte 0x8 16.--20. 1. "DEVICE_STATUS_NB_DUMMY,Number of dummy cycles for auto-polling" newline hexmask.long.byte 0x8 9.--15. 1. "DEVICE_STATUS_RSVD_FLD1,Reserved" newline rbitfld.long 0x8 8. "DEVICE_STATUS_VALID_FLD,Device Status Valid: This should be set when value in bits from 7 to 0 is valid." "0,1" newline hexmask.long.byte 0x8 0.--7. 1. "DEVICE_STATUS_FLD,Defines actual Status Register of Device" line.long 0xC "PHY_CONFIGURATION_REG,PHY Configuration Register" bitfld.long 0xC 31. "PHY_CONFIG_RESYNC_FLD,This bit is used for re-synchronisation delay lines to update them with values from TX DLL Delay and RX DLL Delay fields." "0,1" newline bitfld.long 0xC 30. "PHY_CONFIG_RESET_FLD,DLL Reset bit: This bit is used for reset of Delay Lines by software." "0,1" newline bitfld.long 0xC 29. "PHY_CONFIG_RX_DLL_BYPASS_FLD,RX DLL Bypass: This field determines id RX DLL is bypassed." "0,1" newline hexmask.long.byte 0xC 23.--28. 1. "PHY_CONFIG_RESV2_FLD,Reserved" newline hexmask.long.byte 0xC 16.--22. 1. "PHY_CONFIG_TX_DLL_DELAY_FLD,TX DLL Delay: This field determines the number of delay elements to insert on data path between ref_clk and spi_clk." newline hexmask.long.word 0xC 7.--15. 1. "PHY_CONFIG_RESV1_FLD,Reserved" newline hexmask.long.byte 0xC 0.--6. 1. "PHY_CONFIG_RX_DLL_DELAY_FLD,RX DLL Delay: This field determines the number of delay elements to insert on data path between ref_clk and rx_dll_clk." line.long 0x10 "PHY_MASTER_CONTROL_REG,PHY DLL Master Control Register" hexmask.long.byte 0x10 25.--31. 1. "PHY_MASTER_CONTROL_RESV3_FLD,Reserved" newline bitfld.long 0x10 24. "PHY_MASTER_LOCK_MODE_FLD,Determines if the master delay line locks on a full cycle or half cycle of delay." "0,1" newline bitfld.long 0x10 23. "PHY_MASTER_BYPASS_MODE_FLD,Controls the bypass mode of the master and slave DLLs." "0,1" newline bitfld.long 0x10 20.--22. "PHY_MASTER_PHASE_DETECT_SELECTOR_FLD,Selects the number of delay elements to be inserted between the phase detect flip-flops." "0,1,2,3,4,5,6,7" newline rbitfld.long 0x10 19. "PHY_MASTER_CONTROL_RESV2_FLD,Reserved" "0,1" newline bitfld.long 0x10 16.--18. "PHY_MASTER_NB_INDICATIONS_FLD,Holds the number of consecutive increment or decrement indications." "0,1,2,3,4,5,6,7" newline hexmask.long.word 0x10 7.--15. 1. "PHY_MASTER_CONTROL_RESV1_FLD,Reserved" newline hexmask.long.byte 0x10 0.--6. 1. "PHY_MASTER_INITIAL_DELAY_FLD,This value is the initial delay value for the DLL." rgroup.long 0xBC++0x7 line.long 0x0 "DLL_OBSERVABLE_LOWER_REG,DLL Observable Register Lower" hexmask.long.byte 0x0 24.--31. 1. "DLL_OBSERVABLE_LOWER_DLL_LOCK_INC_FLD,Holds the state of the cumulative dll_lock_inc register." newline hexmask.long.byte 0x0 16.--23. 1. "DLL_OBSERVABLE_LOWER_DLL_LOCK_DEC_FLD,Holds the state of the cumulative dll_lock_dec register." newline bitfld.long 0x0 15. "DLL_OBSERVABLE_LOWER_LOOPBACK_LOCK_FLD,This bit indicates that lock of loopback is done." "0,1" newline hexmask.long.byte 0x0 8.--14. 1. "DLL_OBSERVABLE_LOWER_LOCK_VALUE_FLD,Reports the DLL encoder value from the master DLL to the slave DLLs." newline hexmask.long.byte 0x0 3.--7. 1. "DLL_OBSERVABLE_LOWER_UNLOCK_COUNTER_FLD,Reports the number of increments or decrements required for the master DLL to complete the locking process." newline bitfld.long 0x0 1.--2. "DLL_OBSERVABLE_LOWER_LOCK_MODE_FLD,Defines the mode in which the DLL has achieved the lock." "0,1,2,3" newline bitfld.long 0x0 0. "DLL_OBSERVABLE_LOWER_DLL_LOCK_FLD,Indicates status of DLL." "0,1" line.long 0x4 "DLL_OBSERVABLE_UPPER_REG,DLL Observable Register Upper" hexmask.long.word 0x4 23.--31. 1. "DLL_OBSERVABLE_UPPER_RESV2_FLD,Reserved" newline hexmask.long.byte 0x4 16.--22. 1. "DLL_OBSERVABLE_UPPER_TX_DECODER_OUTPUT_FLD,Holds the encoded value for the TX delay line for this slice." newline hexmask.long.word 0x4 7.--15. 1. "DLL_OBSERVABLE_UPPER_RESV1_FLD,Reserved" newline hexmask.long.byte 0x4 0.--6. 1. "DLL_OBSERVABLE__UPPER_RX_DECODER_OUTPUT_FLD,Holds the encoded value for the RX delay line for this slice." group.long 0xE0++0x7 line.long 0x0 "OPCODE_EXT_LOWER_REG,Opcode Extension Register (Lower)" hexmask.long.byte 0x0 24.--31. 1. "EXT_READ_OPCODE_FLD,Supplement byte of any Read Opcode" newline hexmask.long.byte 0x0 16.--23. 1. "EXT_WRITE_OPCODE_FLD,Supplement byte of any Write Opcode" newline hexmask.long.byte 0x0 8.--15. 1. "EXT_POLL_OPCODE_FLD,Supplement byte of any Polling Opcode" newline hexmask.long.byte 0x0 0.--7. 1. "EXT_STIG_OPCODE_FLD,Supplement byte of any STIG Opcode" line.long 0x4 "OPCODE_EXT_UPPER_REG,Opcode Extension Register (Upper)" hexmask.long.byte 0x4 24.--31. 1. "WEL_OPCODE_FLD,First byte of any WEL Opcode" newline hexmask.long.byte 0x4 16.--23. 1. "EXT_WEL_OPCODE_FLD,Supplement byte of any WEL Opcode" newline hexmask.long.word 0x4 0.--15. 1. "OPCODE_EXT_UPPER_RESV1_FLD,Reserved" group.long 0xF0++0x3 line.long 0x0 "CUSTOM_CONF_REG,Custom Configuration Register" hexmask.long 0x0 5.--31. 1. "CUSTOM_CONF_RESV_FLD2,Reserved" newline bitfld.long 0x0 4. "PIPE_SMRT_ACC_FLD,PHY POP delay functionality" "0,1" newline hexmask.long.byte 0x0 0.--3. 1. "CUSTOM_CONF_RESV_FLD1,Reserved" rgroup.long 0xFC++0x3 line.long 0x0 "MODULE_ID_REG,Module ID Register" hexmask.long.byte 0x0 24.--31. 1. "FIX_PATCH_FLD,Fix/path number related to revision described by 3 LSBs of this register" newline hexmask.long.word 0x0 8.--23. 1. "MODULE_ID_FLD,Module/Revision ID number" newline hexmask.long.byte 0x0 3.--7. 1. "MODULE_ID_RESV_FLD,Reserved" newline bitfld.long 0x0 2. "HYPER_SUPPORT_FLD,HyperFlash Support" "0,1" newline bitfld.long 0x0 0.--1. "CONF_FLD,Configuration ID number: 0 : OCTAL + PHY Configuration 1 : OCTAL Configuration 2 : QUAD + PHY Configuration 3 : QUAD Configuration" "OCTAL + PHY Configuration,OCTAL Configuration,QUAD + PHY Configuration,QUAD Configuration" group.long 0x100++0x3 line.long 0x0 "HYPERFLASH_CONFIG_REG,HyperFlash Configuration Register" rbitfld.long 0x0 31. "HYPERFLASH_CONFIG_RESV3_FLD,Reserved" "0,1" newline bitfld.long 0x0 30. "TARGET_HYPERFLASH_STIG_FLD,Identifies the target of final STIG HyperFlash transaction as follows: 1'b0 = Memory Space 1'b1 = Register Space" "Memory Space 1'b1 = Register Space,?" newline bitfld.long 0x0 29. "BURST_TYPE_HYPERFLASH_STIG_FLD,Identifies the burst type of final STIG HyperFlash transaction" "0,1" newline hexmask.long.word 0x0 20.--28. 1. "HYPERFLASH_CONFIG_RESV2_FLD,Reserved" newline hexmask.long.byte 0x0 16.--19. 1. "HYPERFLASH_LAT_CODE_FLD,Identifies the latency code for HyperFlash" newline hexmask.long.word 0x0 1.--15. 1. "HYPERFLASH_CONFIG_RESV1_FLD,Reserved" newline bitfld.long 0x0 0. "HYPERFLASH_ENABLE_FLD,HyperFlash Mode enable bit" "0,1" group.long 0x110++0x3 line.long 0x0 "OSPI_MISC0,Misc configuration Register #0" newline bitfld.long 0x0 5. "CTL3,sample clocl polarity control for sclk_dlyd_i 0x1 - Invert sample clock sclk_dlyd_i 0x0 - sample clock sclk_dlyd_i not inverted" "sample clock sclk_dlyd_i not inverted,Invert sample clock sclk_dlyd_i" newline bitfld.long 0x0 4. "CTL2,DQS pad output enable When CTL0 is set 0x2 this bit should be enable to enable loopback path from internal sclk_out to DQS pad." "0,1" newline bitfld.long 0x0 2.--3. "CTL1,SCLK output logic control. 0x0 - orginal logic without any delay (Delay added by TX DLL) 0x1 - original logic (sclk_out) with dleay 1/4 cycle of SCLK (by ref_clk_2x fall edge) 0x2 - original logic (sclk_out) with delay 1/2 cycle of SCLk (by.." "orginal logic without any delay,original logic,original logic,original logic" newline bitfld.long 0x0 0.--1. "CTL0,loopback SCLK input logic control (sclk_dlyd). 0x0 - loopback from SCLK pad 0x1 - loopback from internal (sclk_out with delay selected by OSPI_MISC0.CTL1) 0x2 - loopback from DQS pad 0x3 - loopback from ref_clk_2x (for DFT test only)." "loopback from SCLK pad,loopback from internal,loopback from DQS pad,loopback from ref_clk_2x" repeat 3. (list 0x1 0x2 0x3 )(list 0x0 0x4 0x8 ) group.long ($2+0x114)++0x3 line.long 0x0 "OSPI_MISC$1,Misc Configuration Register #1" hexmask.long 0x0 0.--31. 1. "CTL,Reserved for future" repeat.end group.long 0x200++0x3 line.long 0x0 "HYPERFLASH_STIG_CONFIG_REG,HyperFlash STIG Configuration Register" hexmask.long.byte 0x0 27.--31. 1. "HYPERFLASH_STIG_CONFIG_REG_RESV0_FLD,Reserved" newline bitfld.long 0x0 24.--26. "HYPERFLASH_STIG_CONFIG_NB_PRE_TRAN_FLD,Identifies the number of STIG HyperFlash pre-transactions" "0,1,2,3,4,5,6,7" newline hexmask.long.word 0x0 13.--23. 1. "HYPERFLASH_STIG_CONFIG_REG_RESV1_FLD,Reserved" newline bitfld.long 0x0 12. "HYPERFLASH_STIG_PRE_TRAN_DATA7_SIZE_FLD,Identifies data size of STIG HyperFlash pre-transaction 7" "0,1" newline rbitfld.long 0x0 11. "HYPERFLASH_STIG_CONFIG_REG_RESV2_FLD,Reserved" "0,1" newline bitfld.long 0x0 10. "HYPERFLASH_STIG_PRE_TRAN_DATA6_SIZE_FLD,Identifies data size of STIG HyperFlash pre-transaction 6" "0,1" newline rbitfld.long 0x0 9. "HYPERFLASH_STIG_CONFIG_REG_RESV3_FLD,Reserved" "0,1" newline bitfld.long 0x0 8. "HYPERFLASH_STIG_PRE_TRAN_DATA5_SIZE_FLD,Identifies data size of STIG HyperFlash pre-transaction 5" "0,1" newline rbitfld.long 0x0 7. "HYPERFLASH_STIG_CONFIG_REG_RESV4_FLD,Reserved" "0,1" newline bitfld.long 0x0 6. "HYPERFLASH_STIG_PRE_TRAN_DATA4_SIZE_FLD,Identifies data size of STIG HyperFlash pre-transaction 4" "0,1" newline rbitfld.long 0x0 5. "HYPERFLASH_STIG_CONFIG_REG_RESV5_FLD,Reserved" "0,1" newline bitfld.long 0x0 4. "HYPERFLASH_STIG_PRE_TRAN_DATA3_SIZE_FLD,Identifies data size of STIG HyperFlash pre-transaction 3" "0,1" newline rbitfld.long 0x0 3. "HYPERFLASH_STIG_CONFIG_REG_RESV6_FLD,Reserved" "0,1" newline bitfld.long 0x0 2. "HYPERFLASH_STIG_PRE_TRAN_DATA2_SIZE_FLD,Identifies data size of STIG HyperFlash pre-transaction 2" "0,1" newline rbitfld.long 0x0 1. "HYPERFLASH_STIG_CONFIG_REG_RESV7_FLD,Reserved" "0,1" newline bitfld.long 0x0 0. "HYPERFLASH_STIG_PRE_TRAN_DATA1_SIZE_FLD,Identifies data size of STIG HyperFlash pre-transaction 1" "0,1" group.long 0x210++0x7 line.long 0x0 "HYPERFLASH_STIG_PRE_TRAN1_ADDRESS_REG,HyperFlash STIG Pre-transaction 1 Address Register" hexmask.long 0x0 0.--31. 1. "HYPERFLASH_STIG_PRE_TRAN1_ADDRESS_FLD,Identifies Address of HyperFlash STIG Pre-transaction 1" line.long 0x4 "HYPERFLASH_STIG_PRE_TRAN1_DATA_REG,HyperFlash STIG Pre-transaction 1 Data Register" hexmask.long 0x4 0.--31. 1. "HYPERFLASH_STIG_PRE_TRAN1_DATA_FLD,Identifies Data of HyperFlash STIG Pre-transaction 1" group.long 0x220++0x7 line.long 0x0 "HYPERFLASH_STIG_PRE_TRAN2_ADDRESS_REG,HyperFlash STIG Pre-transaction 2 Address Register" hexmask.long 0x0 0.--31. 1. "HYPERFLASH_STIG_PRE_TRAN2_ADDRESS_FLD,Identifies Address of HyperFlash STIG Pre-transaction 2" line.long 0x4 "HYPERFLASH_STIG_PRE_TRAN2_DATA_REG,HyperFlash STIG Pre-transaction 2 Data Register" hexmask.long 0x4 0.--31. 1. "HYPERFLASH_STIG_PRE_TRAN2_DATA_FLD,Identifies Data of HyperFlash STIG Pre-transaction 2" group.long 0x230++0x7 line.long 0x0 "HYPERFLASH_STIG_PRE_TRAN3_ADDRESS_REG,HyperFlash STIG Pre-transaction 3 Address Register" hexmask.long 0x0 0.--31. 1. "HYPERFLASH_STIG_PRE_TRAN3_ADDRESS_FLD,Identifies Address of HyperFlash STIG Pre-transaction 3" line.long 0x4 "HYPERFLASH_STIG_PRE_TRAN3_DATA_REG,HyperFlash STIG Pre-transaction 3 Data Register" hexmask.long 0x4 0.--31. 1. "HYPERFLASH_STIG_PRE_TRAN3_DATA_FLD,Identifies Data of HyperFlash STIG Pre-transaction 3" group.long 0x240++0x7 line.long 0x0 "HYPERFLASH_STIG_PRE_TRAN4_ADDRESS_REG,HyperFlash STIG Pre-transaction 4 Address Register" hexmask.long 0x0 0.--31. 1. "HYPERFLASH_STIG_PRE_TRAN4_ADDRESS_FLD,Identifies Address of HyperFlash STIG Pre-transaction 4" line.long 0x4 "HYPERFLASH_STIG_PRE_TRAN4_DATA_REG,HyperFlash STIG Pre-transaction 4 Data Register" hexmask.long 0x4 0.--31. 1. "HYPERFLASH_STIG_PRE_TRAN4_DATA_FLD,Identifies Data of HyperFlash STIG Pre-transaction 4" group.long 0x250++0x7 line.long 0x0 "HYPERFLASH_STIG_PRE_TRAN5_ADDRESS_REG,HyperFlash STIG Pre-transaction 5 Address Register" hexmask.long 0x0 0.--31. 1. "HYPERFLASH_STIG_PRE_TRAN5_ADDRESS_FLD,Identifies Address of HyperFlash STIG Pre-transaction 5" line.long 0x4 "HYPERFLASH_STIG_PRE_TRAN5_DATA_REG,HyperFlash STIG Pre-transaction 5 Data Register" hexmask.long 0x4 0.--31. 1. "HYPERFLASH_STIG_PRE_TRAN5_DATA_FLD,Identifies Data of HyperFlash STIG Pre-transaction 5" group.long 0x260++0x7 line.long 0x0 "HYPERFLASH_STIG_PRE_TRAN6_ADDRESS_REG,HyperFlash STIG Pre-transaction 6 Address Register" hexmask.long 0x0 0.--31. 1. "HYPERFLASH_STIG_PRE_TRAN6_ADDRESS_FLD,Identifies Address of HyperFlash STIG Pre-transaction 6" line.long 0x4 "HYPERFLASH_STIG_PRE_TRAN6_DATA_REG,HyperFlash STIG Pre-transaction 6 Data Register" hexmask.long 0x4 0.--31. 1. "HYPERFLASH_STIG_PRE_TRAN6_DATA_FLD,Identifies Data of HyperFlash STIG Pre-transaction 6" group.long 0x270++0x7 line.long 0x0 "HYPERFLASH_STIG_PRE_TRAN7_ADDRESS_REG,HyperFlash STIG Pre-transaction 7 Address Register" hexmask.long 0x0 0.--31. 1. "HYPERFLASH_STIG_PRE_TRAN7_ADDRESS_FLD,Identifies Address of HyperFlash STIG Pre-transaction 7" line.long 0x4 "HYPERFLASH_STIG_PRE_TRAN7_DATA_REG,HyperFlash STIG Pre-transaction 7 Data Register" hexmask.long 0x4 0.--31. 1. "HYPERFLASH_STIG_PRE_TRAN7_DATA_FLD,Identifies Data of HyperFlash STIG Pre-transaction 7" group.long 0x300++0x3 line.long 0x0 "HYPERFLASH_WRITE_CONFIG_REG,HyperFlash Write Configuration Register" hexmask.long.byte 0x0 27.--31. 1. "HYPERFLASH_WRITE_CONFIG_REG_RESV0_FLD,Reserved" newline bitfld.long 0x0 24.--26. "HYPERFLASH_WRITE_CONFIG_NB_PRE_TRAN_FLD,Identifies the number of Write HyperFlash pre-transactions" "0,1,2,3,4,5,6,7" newline hexmask.long.word 0x0 13.--23. 1. "HYPERFLASH_WRITE_CONFIG_REG_RESV1_FLD,Reserved" newline bitfld.long 0x0 12. "HYPERFLASH_WRITE_PRE_TRAN_DATA7_SIZE_FLD,Identifies data size of Write HyperFlash pre-transaction 7" "0,1" newline rbitfld.long 0x0 11. "HYPERFLASH_WRITE_CONFIG_REG_RESV2_FLD,Reserved" "0,1" newline bitfld.long 0x0 10. "HYPERFLASH_WRITE_PRE_TRAN_DATA6_SIZE_FLD,Identifies data size of Write HyperFlash pre-transaction 6" "0,1" newline rbitfld.long 0x0 9. "HYPERFLASH_WRITE_CONFIG_REG_RESV3_FLD,Reserved" "0,1" newline bitfld.long 0x0 8. "HYPERFLASH_WRITE_PRE_TRAN_DATA5_SIZE_FLD,Identifies data size of Write HyperFlash pre-transaction 5" "0,1" newline rbitfld.long 0x0 7. "HYPERFLASH_WRITE_CONFIG_REG_RESV4_FLD,Reserved" "0,1" newline bitfld.long 0x0 6. "HYPERFLASH_WRITE_PRE_TRAN_DATA4_SIZE_FLD,Identifies data size of Write HyperFlash pre-transaction 4" "0,1" newline rbitfld.long 0x0 5. "HYPERFLASH_WRITE_CONFIG_REG_RESV5_FLD,Reserved" "0,1" newline bitfld.long 0x0 4. "HYPERFLASH_WRITE_PRE_TRAN_DATA3_SIZE_FLD,Identifies data size of Write HyperFlash pre-transaction 3" "0,1" newline rbitfld.long 0x0 3. "HYPERFLASH_WRITE_CONFIG_REG_RESV6_FLD,Reserved" "0,1" newline bitfld.long 0x0 2. "HYPERFLASH_WRITE_PRE_TRAN_DATA2_SIZE_FLD,Identifies data size of Write HyperFlash pre-transaction 2" "0,1" newline rbitfld.long 0x0 1. "HYPERFLASH_WRITE_CONFIG_REG_RESV7_FLD,Reserved" "0,1" newline bitfld.long 0x0 0. "HYPERFLASH_WRITE_PRE_TRAN_DATA1_SIZE_FLD,Identifies data size of Write HyperFlash pre-transaction 1" "0,1" group.long 0x310++0x7 line.long 0x0 "HYPERFLASH_WRITE_PRE_TRAN1_ADDRESS_REG,HyperFlash Write Pre-transaction 1 Address Register" hexmask.long 0x0 0.--31. 1. "HYPERFLASH_WRITE_PRE_TRAN1_ADDRESS_FLD,Identifies Address of HyperFlash Write Pre-transaction 1" line.long 0x4 "HYPERFLASH_WRITE_PRE_TRAN1_DATA_REG,HyperFlash Write Pre-transaction 1 Data Register" hexmask.long 0x4 0.--31. 1. "HYPERFLASH_WRITE_PRE_TRAN1_DATA_FLD,Identifies Data of HyperFlash Write Pre-transaction 1" group.long 0x320++0x7 line.long 0x0 "HYPERFLASH_WRITE_PRE_TRAN2_ADDRESS_REG,HyperFlash Write Pre-transaction 2 Address Register" hexmask.long 0x0 0.--31. 1. "HYPERFLASH_WRITE_PRE_TRAN2_ADDRESS_FLD,Identifies Address of HyperFlash Write Pre-transaction 2" line.long 0x4 "HYPERFLASH_WRITE_PRE_TRAN2_DATA_REG,HyperFlash Write Pre-transaction 2 Data Register" hexmask.long 0x4 0.--31. 1. "HYPERFLASH_WRITE_PRE_TRAN2_DATA_FLD,Identifies Data of HyperFlash Write Pre-transaction 2" group.long 0x330++0x7 line.long 0x0 "HYPERFLASH_WRITE_PRE_TRAN3_ADDRESS_REG,HyperFlash Write Pre-transaction 3 Address Register" hexmask.long 0x0 0.--31. 1. "HYPERFLASH_WRITE_PRE_TRAN3_ADDRESS_FLD,Identifies Address of HyperFlash Write Pre-transaction 3" line.long 0x4 "HYPERFLASH_WRITE_PRE_TRAN3_DATA_REG,HyperFlash Write Pre-transaction 3 Data Register" hexmask.long 0x4 0.--31. 1. "HYPERFLASH_WRITE_PRE_TRAN3_DATA_FLD,Identifies Data of HyperFlash Write Pre-transaction 3" group.long 0x340++0x7 line.long 0x0 "HYPERFLASH_WRITE_PRE_TRAN4_ADDRESS_REG,HyperFlash Write Pre-transaction 4 Address Register" hexmask.long 0x0 0.--31. 1. "HYPERFLASH_WRITE_PRE_TRAN4_ADDRESS_FLD,Identifies Address of HyperFlash Write Pre-transaction 4" line.long 0x4 "HYPERFLASH_WRITE_PRE_TRAN4_DATA_REG,HyperFlash Write Pre-transaction 4 Data Register" hexmask.long 0x4 0.--31. 1. "HYPERFLASH_WRITE_PRE_TRAN4_DATA_FLD,Identifies Data of HyperFlash Write Pre-transaction 4" group.long 0x350++0x7 line.long 0x0 "HYPERFLASH_WRITE_PRE_TRAN5_ADDRESS_REG,HyperFlash Write Pre-transaction 5 Address Register" hexmask.long 0x0 0.--31. 1. "HYPERFLASH_WRITE_PRE_TRAN5_ADDRESS_FLD,Identifies Address of HyperFlash Write Pre-transaction 5" line.long 0x4 "HYPERFLASH_WRITE_PRE_TRAN5_DATA_REG,HyperFlash Write Pre-transaction 5 Data Register" hexmask.long 0x4 0.--31. 1. "HYPERFLASH_WRITE_PRE_TRAN5_DATA_FLD,Identifies Data of HyperFlash Write Pre-transaction 5" group.long 0x360++0x7 line.long 0x0 "HYPERFLASH_WRITE_PRE_TRAN6_ADDRESS_REG,HyperFlash Write Pre-transaction 6 Address Register" hexmask.long 0x0 0.--31. 1. "HYPERFLASH_WRITE_PRE_TRAN6_ADDRESS_FLD,Identifies Address of HyperFlash Write Pre-transaction 6" line.long 0x4 "HYPERFLASH_WRITE_PRE_TRAN6_DATA_REG,HyperFlash Write Pre-transaction 6 Data Register" hexmask.long 0x4 0.--31. 1. "HYPERFLASH_WRITE_PRE_TRAN6_DATA_FLD,Identifies Data of HyperFlash Write Pre-transaction 6" group.long 0x370++0x7 line.long 0x0 "HYPERFLASH_WRITE_PRE_TRAN7_ADDRESS_REG,HyperFlash Write Pre-transaction 7 Address Register" hexmask.long 0x0 0.--31. 1. "HYPERFLASH_WRITE_PRE_TRAN7_ADDRESS_FLD,Identifies Address of HyperFlash Write Pre-transaction 7" line.long 0x4 "HYPERFLASH_WRITE_PRE_TRAN7_DATA_REG,HyperFlash Write Pre-transaction 7 Data Register" hexmask.long 0x4 0.--31. 1. "HYPERFLASH_WRITE_PRE_TRAN7_DATA_FLD,Identifies Data of HyperFlash Write Pre-transaction 7" group.long 0x400++0x3 line.long 0x0 "HYPERFLASH_READ_CONFIG_REG,HyperFlash Read Configuration Register" hexmask.long.byte 0x0 27.--31. 1. "HYPERFLASH_READ_CONFIG_REG_RESV0_FLD,Reserved" newline bitfld.long 0x0 24.--26. "HYPERFLASH_READ_CONFIG_NB_PRE_TRAN_FLD,Identifies the number of Read HyperFlash pre-transactions" "0,1,2,3,4,5,6,7" newline hexmask.long.word 0x0 13.--23. 1. "HYPERFLASH_READ_CONFIG_REG_RESV1_FLD,Reserved" newline bitfld.long 0x0 12. "HYPERFLASH_READ_PRE_TRAN_DATA7_SIZE_FLD,Identifies data size of Read HyperFlash pre-transaction 7" "0,1" newline rbitfld.long 0x0 11. "HYPERFLASH_READ_CONFIG_REG_RESV2_FLD,Reserved" "0,1" newline bitfld.long 0x0 10. "HYPERFLASH_READ_PRE_TRAN_DATA6_SIZE_FLD,Identifies data size of Read HyperFlash pre-transaction 6" "0,1" newline rbitfld.long 0x0 9. "HYPERFLASH_READ_CONFIG_REG_RESV3_FLD,Reserved" "0,1" newline bitfld.long 0x0 8. "HYPERFLASH_READ_PRE_TRAN_DATA5_SIZE_FLD,Identifies data size of Read HyperFlash pre-transaction 5" "0,1" newline rbitfld.long 0x0 7. "HYPERFLASH_READ_CONFIG_REG_RESV4_FLD,Reserved" "0,1" newline bitfld.long 0x0 6. "HYPERFLASH_READ_PRE_TRAN_DATA4_SIZE_FLD,Identifies data size of Read HyperFlash pre-transaction 4" "0,1" newline rbitfld.long 0x0 5. "HYPERFLASH_READ_CONFIG_REG_RESV5_FLD,Reserved" "0,1" newline bitfld.long 0x0 4. "HYPERFLASH_READ_PRE_TRAN_DATA3_SIZE_FLD,Identifies data size of Read HyperFlash pre-transaction 3" "0,1" newline rbitfld.long 0x0 3. "HYPERFLASH_READ_CONFIG_REG_RESV6_FLD,Reserved" "0,1" newline bitfld.long 0x0 2. "HYPERFLASH_READ_PRE_TRAN_DATA2_SIZE_FLD,Identifies data size of Read HyperFlash pre-transaction 2" "0,1" newline rbitfld.long 0x0 1. "HYPERFLASH_READ_CONFIG_REG_RESV7_FLD,Reserved" "0,1" newline bitfld.long 0x0 0. "HYPERFLASH_READ_PRE_TRAN_DATA1_SIZE_FLD,Identifies data size of Read HyperFlash pre-transaction 1" "0,1" group.long 0x410++0x7 line.long 0x0 "HYPERFLASH_READ_PRE_TRAN1_ADDRESS_REG,HyperFlash Read Pre-transaction 1 Address Register" hexmask.long 0x0 0.--31. 1. "HYPERFLASH_READ_PRE_TRAN1_ADDRESS_FLD,Identifies Address of HyperFlash Read Pre-transaction 1" line.long 0x4 "HYPERFLASH_READ_PRE_TRAN1_DATA_REG,HyperFlash Read Pre-transaction 1 Data Register" hexmask.long 0x4 0.--31. 1. "HYPERFLASH_READ_PRE_TRAN1_DATA_FLD,Identifies Data of HyperFlash Read Pre-transaction 1" group.long 0x420++0x7 line.long 0x0 "HYPERFLASH_READ_PRE_TRAN2_ADDRESS_REG,HyperFlash Read Pre-transaction 2 Address Register" hexmask.long 0x0 0.--31. 1. "HYPERFLASH_READ_PRE_TRAN2_ADDRESS_FLD,Identifies Address of HyperFlash Read Pre-transaction 2" line.long 0x4 "HYPERFLASH_READ_PRE_TRAN2_DATA_REG,HyperFlash Read Pre-transaction 2 Data Register" hexmask.long 0x4 0.--31. 1. "HYPERFLASH_READ_PRE_TRAN2_DATA_FLD,Identifies Data of HyperFlash Read Pre-transaction 2" group.long 0x430++0x7 line.long 0x0 "HYPERFLASH_READ_PRE_TRAN3_ADDRESS_REG,HyperFlash Read Pre-transaction 3 Address Register" hexmask.long 0x0 0.--31. 1. "HYPERFLASH_READ_PRE_TRAN3_ADDRESS_FLD,Identifies Address of HyperFlash Read Pre-transaction 3" line.long 0x4 "HYPERFLASH_READ_PRE_TRAN3_DATA_REG,HyperFlash Read Pre-transaction 3 Data Register" hexmask.long 0x4 0.--31. 1. "HYPERFLASH_READ_PRE_TRAN3_DATA_FLD,Identifies Data of HyperFlash Read Pre-transaction 3" group.long 0x440++0x7 line.long 0x0 "HYPERFLASH_READ_PRE_TRAN4_ADDRESS_REG,HyperFlash Read Pre-transaction 4 Address Register" hexmask.long 0x0 0.--31. 1. "HYPERFLASH_READ_PRE_TRAN4_ADDRESS_FLD,Identifies Address of HyperFlash Read Pre-transaction 4" line.long 0x4 "HYPERFLASH_READ_PRE_TRAN4_DATA_REG,HyperFlash Read Pre-transaction 4 Data Register" hexmask.long 0x4 0.--31. 1. "HYPERFLASH_READ_PRE_TRAN4_DATA_FLD,Identifies Data of HyperFlash Read Pre-transaction 4" group.long 0x450++0x7 line.long 0x0 "HYPERFLASH_READ_PRE_TRAN5_ADDRESS_REG,HyperFlash Read Pre-transaction 5 Address Register" hexmask.long 0x0 0.--31. 1. "HYPERFLASH_READ_PRE_TRAN5_ADDRESS_FLD,Identifies Address of HyperFlash Read Pre-transaction 5" line.long 0x4 "HYPERFLASH_READ_PRE_TRAN5_DATA_REG,HyperFlash Read Pre-transaction 5 Data Register" hexmask.long 0x4 0.--31. 1. "HYPERFLASH_READ_PRE_TRAN5_DATA_FLD,Identifies Data of HyperFlash Read Pre-transaction 5" group.long 0x460++0x7 line.long 0x0 "HYPERFLASH_READ_PRE_TRAN6_ADDRESS_REG,HyperFlash Read Pre-transaction 6 Address Register" hexmask.long 0x0 0.--31. 1. "HYPERFLASH_READ_PRE_TRAN6_ADDRESS_FLD,Identifies Address of HyperFlash Read Pre-transaction 6" line.long 0x4 "HYPERFLASH_READ_PRE_TRAN6_DATA_REG,HyperFlash Read Pre-transaction 6 Data Register" hexmask.long 0x4 0.--31. 1. "HYPERFLASH_READ_PRE_TRAN6_DATA_FLD,Identifies Data of HyperFlash Read Pre-transaction 6" group.long 0x470++0x7 line.long 0x0 "HYPERFLASH_READ_PRE_TRAN7_ADDRESS_REG,HyperFlash Read Pre-transaction 7 Address Register" hexmask.long 0x0 0.--31. 1. "HYPERFLASH_READ_PRE_TRAN7_ADDRESS_FLD,Identifies Address of HyperFlash Read Pre-transaction 7" line.long 0x4 "HYPERFLASH_READ_PRE_TRAN7_DATA_REG,HyperFlash Read Pre-transaction 7 Data Register" hexmask.long 0x4 0.--31. 1. "HYPERFLASH_READ_PRE_TRAN7_DATA_FLD,Identifies Data of HyperFlash Read Pre-transaction 7" group.long 0x500++0x3 line.long 0x0 "HYPERFLASH_POLLING_CONFIG_REG,HyperFlash Polling Configuration Register" hexmask.long.byte 0x0 27.--31. 1. "HYPERFLASH_POLLING_CONFIG_REG_RESV0_FLD,Reserved" newline bitfld.long 0x0 24.--26. "HYPERFLASH_POLLING_CONFIG_NB_PRE_TRAN_FLD,Identifies the number of Polling HyperFlash pre-transactions" "0,1,2,3,4,5,6,7" newline hexmask.long.word 0x0 13.--23. 1. "HYPERFLASH_POLLING_CONFIG_REG_RESV1_FLD,Reserved" newline bitfld.long 0x0 12. "HYPERFLASH_POLLING_PRE_TRAN_DATA7_SIZE_FLD,Identifies data size of Polling HyperFlash pre-transaction 7" "0,1" newline rbitfld.long 0x0 11. "HYPERFLASH_POLLING_CONFIG_REG_RESV2_FLD,Reserved" "0,1" newline bitfld.long 0x0 10. "HYPERFLASH_POLLING_PRE_TRAN_DATA6_SIZE_FLD,Identifies data size of Polling HyperFlash pre-transaction 6" "0,1" newline rbitfld.long 0x0 9. "HYPERFLASH_POLLING_CONFIG_REG_RESV3_FLD,Reserved" "0,1" newline bitfld.long 0x0 8. "HYPERFLASH_POLLING_PRE_TRAN_DATA5_SIZE_FLD,Identifies data size of Polling HyperFlash pre-transaction 5" "0,1" newline rbitfld.long 0x0 7. "HYPERFLASH_POLLING_CONFIG_REG_RESV4_FLD,Reserved" "0,1" newline bitfld.long 0x0 6. "HYPERFLASH_POLLING_PRE_TRAN_DATA4_SIZE_FLD,Identifies data size of Polling HyperFlash pre-transaction 4" "0,1" newline rbitfld.long 0x0 5. "HYPERFLASH_POLLING_CONFIG_REG_RESV5_FLD,Reserved" "0,1" newline bitfld.long 0x0 4. "HYPERFLASH_POLLING_PRE_TRAN_DATA3_SIZE_FLD,Identifies data size of Polling HyperFlash pre-transaction 3" "0,1" newline rbitfld.long 0x0 3. "HYPERFLASH_POLLING_CONFIG_REG_RESV6_FLD,Reserved" "0,1" newline bitfld.long 0x0 2. "HYPERFLASH_POLLING_PRE_TRAN_DATA2_SIZE_FLD,Identifies data size of Polling HyperFlash pre-transaction 2" "0,1" newline rbitfld.long 0x0 1. "HYPERFLASH_POLLING_CONFIG_REG_RESV7_FLD,Reserved" "0,1" newline bitfld.long 0x0 0. "HYPERFLASH_POLLING_PRE_TRAN_DATA1_SIZE_FLD,Identifies data size of Polling HyperFlash pre-transaction 1" "0,1" group.long 0x510++0x7 line.long 0x0 "HYPERFLASH_POLLING_PRE_TRAN1_ADDRESS_REG,HyperFlash Polling Pre-transaction 1 Address Register" hexmask.long 0x0 0.--31. 1. "HYPERFLASH_POLLING_PRE_TRAN1_ADDRESS_FLD,Identifies Address of HyperFlash Polling Pre-transaction 1" line.long 0x4 "HYPERFLASH_POLLING_PRE_TRAN1_DATA_REG,HyperFlash Polling Pre-transaction 1 Data Register" hexmask.long 0x4 0.--31. 1. "HYPERFLASH_POLLING_PRE_TRAN1_DATA_FLD,Identifies Data of HyperFlash Polling Pre-transaction 1" group.long 0x520++0x7 line.long 0x0 "HYPERFLASH_POLLING_PRE_TRAN2_ADDRESS_REG,HyperFlash Polling Pre-transaction 2 Address Register" hexmask.long 0x0 0.--31. 1. "HYPERFLASH_POLLING_PRE_TRAN2_ADDRESS_FLD,Identifies Address of HyperFlash Polling Pre-transaction 2" line.long 0x4 "HYPERFLASH_POLLING_PRE_TRAN2_DATA_REG,HyperFlash Polling Pre-transaction 2 Data Register" hexmask.long 0x4 0.--31. 1. "HYPERFLASH_POLLING_PRE_TRAN2_DATA_FLD,Identifies Data of HyperFlash Polling Pre-transaction 2" group.long 0x530++0x7 line.long 0x0 "HYPERFLASH_POLLING_PRE_TRAN3_ADDRESS_REG,HyperFlash Polling Pre-transaction 3 Address Register" hexmask.long 0x0 0.--31. 1. "HYPERFLASH_POLLING_PRE_TRAN3_ADDRESS_FLD,Identifies Address of HyperFlash Polling Pre-transaction 3" line.long 0x4 "HYPERFLASH_POLLING_PRE_TRAN3_DATA_REG,HyperFlash Polling Pre-transaction 3 Data Register" hexmask.long 0x4 0.--31. 1. "HYPERFLASH_POLLING_PRE_TRAN3_DATA_FLD,Identifies Data of HyperFlash Polling Pre-transaction 3" group.long 0x540++0x7 line.long 0x0 "HYPERFLASH_POLLING_PRE_TRAN4_ADDRESS_REG,HyperFlash Polling Pre-transaction 4 Address Register" hexmask.long 0x0 0.--31. 1. "HYPERFLASH_POLLING_PRE_TRAN4_ADDRESS_FLD,Identifies Address of HyperFlash Polling Pre-transaction 4" line.long 0x4 "HYPERFLASH_POLLING_PRE_TRAN4_DATA_REG,HyperFlash Polling Pre-transaction 4 Data Register" hexmask.long 0x4 0.--31. 1. "HYPERFLASH_POLLING_PRE_TRAN4_DATA_FLD,Identifies Data of HyperFlash Polling Pre-transaction 4" group.long 0x550++0x7 line.long 0x0 "HYPERFLASH_POLLING_PRE_TRAN5_ADDRESS_REG,HyperFlash Polling Pre-transaction 5 Address Register" hexmask.long 0x0 0.--31. 1. "HYPERFLASH_POLLING_PRE_TRAN5_ADDRESS_FLD,Identifies Address of HyperFlash Polling Pre-transaction 5" line.long 0x4 "HYPERFLASH_POLLING_PRE_TRAN5_DATA_REG,HyperFlash Polling Pre-transaction 5 Data Register" hexmask.long 0x4 0.--31. 1. "HYPERFLASH_POLLING_PRE_TRAN5_DATA_FLD,Identifies Data of HyperFlash Polling Pre-transaction 5" group.long 0x560++0x7 line.long 0x0 "HYPERFLASH_POLLING_PRE_TRAN6_ADDRESS_REG,HyperFlash Polling Pre-transaction 6 Address Register" hexmask.long 0x0 0.--31. 1. "HYPERFLASH_POLLING_PRE_TRAN6_ADDRESS_FLD,Identifies Address of HyperFlash Polling Pre-transaction 6" line.long 0x4 "HYPERFLASH_POLLING_PRE_TRAN6_DATA_REG,HyperFlash Polling Pre-transaction 6 Data Register" hexmask.long 0x4 0.--31. 1. "HYPERFLASH_POLLING_PRE_TRAN6_DATA_FLD,Identifies Data of HyperFlash Polling Pre-transaction 6" group.long 0x570++0x7 line.long 0x0 "HYPERFLASH_POLLING_PRE_TRAN7_ADDRESS_REG,HyperFlash Polling Pre-transaction 7 Address Register" hexmask.long 0x0 0.--31. 1. "HYPERFLASH_POLLING_PRE_TRAN7_ADDRESS_FLD,Identifies Address of HyperFlash Polling Pre-transaction 7" line.long 0x4 "HYPERFLASH_POLLING_PRE_TRAN7_DATA_REG,HyperFlash Polling Pre-transaction 7 Data Register" hexmask.long 0x4 0.--31. 1. "HYPERFLASH_POLLING_PRE_TRAN7_DATA_FLD,Identifies Data of HyperFlash Polling Pre-transaction 7" group.long 0xA00++0x13 line.long 0x0 "ASF_INT_STATUS_REG,ASF Interrupt Status Register" hexmask.long 0x0 7.--31. 1. "ASF_INT_STATUS_RESV1_FLD,Reserved" newline bitfld.long 0x0 6. "ASF_INTEGRITY_ERR_FLD,Integrity error interrupt" "0,1" newline bitfld.long 0x0 5. "ASF_PROTOCOL_ERR_FLD,Protocol error interrupt" "0,1" newline bitfld.long 0x0 4. "ASF_TRANS_TO_ERR_FLD,Transaction timeouts interrupt" "0,1" newline bitfld.long 0x0 3. "ASF_CSR_ERR_FLD,Configuration and status registers error interrupt" "0,1" newline bitfld.long 0x0 2. "ASF_DAP_ERR_FLD,Data and address paths error interrupt" "0,1" newline bitfld.long 0x0 1. "ASF_SRAM_UNCORR_ERR_FLD,SRAM uncorrectable error interrupt" "0,1" newline bitfld.long 0x0 0. "ASF_SRAM_CORR_ERR_FLD,SRAM correctable error interrupt" "0,1" line.long 0x4 "ASF_INT_RAW_STATUS_REG,ASF Interrupt Raw Status Register" hexmask.long 0x4 7.--31. 1. "ASF_INT_RAW_STATUS_RESV1_FLD,Reserved" newline bitfld.long 0x4 6. "ASF_INTEGRITY_ERR_FLD,Integrity error interrupt" "0,1" newline bitfld.long 0x4 5. "ASF_PROTOCOL_ERR_FLD,Protocol error interrupt" "0,1" newline bitfld.long 0x4 4. "ASF_TRANS_TO_ERR_FLD,Transaction timeouts interrupt" "0,1" newline bitfld.long 0x4 3. "ASF_CSR_ERR_FLD,Configuration and status registers error interrupt" "0,1" newline bitfld.long 0x4 2. "ASF_DAP_ERR_FLD,Data and address paths error interrupt" "0,1" newline bitfld.long 0x4 1. "ASF_SRAM_UNCORR_ERR_FLD,SRAM uncorrectable error interrupt" "0,1" newline bitfld.long 0x4 0. "ASF_SRAM_CORR_ERR_FLD,SRAM correctable error interrupt" "0,1" line.long 0x8 "ASF_INT_MASK_REG,The ASF interrupt mask register indicating which interrupt bits in the ASF Interrupt Status Register are masked" hexmask.long 0x8 7.--31. 1. "ASF_INT_MASK_RESV1_FLD,Reserved" newline bitfld.long 0x8 6. "ASF_INTEGRITY_ERR_MASK_FLD,Mask bit for integrity error interrupt" "0,1" newline bitfld.long 0x8 5. "ASF_PROTOCOL_ERR_MASK_FLD,Mask bit for protocol error interrupt" "0,1" newline bitfld.long 0x8 4. "ASF_TRANS_TO_ERR_MASK_FLD,Mask bit for transaction timeouts interrupt" "0,1" newline bitfld.long 0x8 3. "ASF_CSR_ERR_MASK_FLD,Mask bit for configuration and status registers error interrupt" "0,1" newline bitfld.long 0x8 2. "ASF_DAP_ERR_MASK_FLD,Mask bit for data and address paths error interrupt" "0,1" newline bitfld.long 0x8 1. "ASF_SRAM_UNCORR_ERR_MASK_FLD,Mask bit for SRAM uncorrectable error interrupt" "0,1" newline bitfld.long 0x8 0. "ASF_SRAM_CORR_ERR_MASK_FLD,Mask bit for SRAM correctable error interrupt" "0,1" line.long 0xC "ASF_INT_TEST_REG,The ASF interrupt test register emulate hardware even" hexmask.long 0xC 7.--31. 1. "ASF_INT_TEST_RESV1_FLD,Reserved" newline bitfld.long 0xC 6. "ASF_INTEGRITY_ERR_TEST_FLD,Test bit for integrity error interrupt" "0,1" newline bitfld.long 0xC 5. "ASF_PROTOCOL_ERR_TEST_FLD,Test bit for protocol error interrupt" "0,1" newline bitfld.long 0xC 4. "ASF_TRANS_TO_ERR_TEST_FLD,Test bit for transaction timeouts interrupt" "0,1" newline bitfld.long 0xC 3. "ASF_CSR_ERR_TEST_FLD,Test bit for configuration and status registers error interrupt" "0,1" newline bitfld.long 0xC 2. "ASF_DAP_ERR_TEST_FLD,Test bit for data and address paths error interrupt" "0,1" newline bitfld.long 0xC 1. "ASF_SRAM_UNCORR_ERR_TEST_FLD,Test bit form SRAM uncorrectable error interrupt" "0,1" newline bitfld.long 0xC 0. "ASF_SRAM_CORR_ERR_TEST_FLD,Test bit for SRAM correctable error interupt" "0,1" line.long 0x10 "ASF_FATAL_NONFATAL_SELECT_REG,The fatal or non-fatal interrupt registers selects whether a fatal or non-fatal interrupt is triggered." hexmask.long 0x10 7.--31. 1. "ASF_FATAL_NONFATAL_SELECT_RESV1_FLD,Reserved" newline bitfld.long 0x10 6. "ASF_INTEGRITY_ERR_SEL_FLD,Enable integrity interrupt as fatal" "0,1" newline bitfld.long 0x10 5. "ASF_PROTOCOL_ERR_SEL_FLD,Enable protocol interrupt as fatal" "0,1" newline bitfld.long 0x10 4. "ASF_TRANS_TO_ERR_SEL_FLD,Enable transaction timeouts interrupt as fatal" "0,1" newline bitfld.long 0x10 3. "ASF_CSR_ERR_SEL_FLD,Enable configuration and status registers interrupts as fatal" "0,1" newline bitfld.long 0x10 2. "ASF_DAP_ERR_SEL_FLD,Enable data and address paths interrupt as fatal" "0,1" newline bitfld.long 0x10 1. "ASF_SRAM_UNCORR_ERR_SEL_FLD,Enable SRAM uncorrectable interrupt as fatal" "0,1" newline bitfld.long 0x10 0. "ASF_SRAM_CORR_ERR_SEL_FLD,Enable SRAM correctable interrupt as fatal" "0,1" rgroup.long 0xA20++0x7 line.long 0x0 "ASF_SRAM_CORR_FAULT_STATUS_REG,Status register for SRAM correctable fault' field{ desc = 'Last SRAM address that generated fault" line.long 0x4 "ASF_SRAM_UNCORR_FAULT_STATUS_REG,Status register for SRAM uncorrectable fault" hexmask.long.word 0x4 16.--31. 1. "ASF_SRAM_UNCORR_FAULT_STATUS_RESV1_FLD,Reserved" newline hexmask.long.word 0x4 0.--15. 1. "ASF_SRAM_UNCORR_FAULT_ADDR_FLD,Last SRAM address that generated" group.long 0xA28++0x3 line.long 0x0 "ASF_SRAM_FAULT_STATS_REG,Statics register for SRAM faults" hexmask.long.word 0x0 16.--31. 1. "ASF_SRAM_FAULT_UNCORR_STATS_FLS,Count of number of uncorrectable errors" newline hexmask.long.word 0x0 0.--15. 1. "ASF_SRAM_FAULT_CORR_STATS_FLD,Count of number of correctable errors" group.long 0xA30++0xB line.long 0x0 "ASF_TRANS_TO_CTRL_REG,Control register to configure the ASF transaction timeout monitors" bitfld.long 0x0 31. "ASF_TRANS_TO_EN_FLD,Enable transaction timeout monitoring" "0,1" newline hexmask.long.word 0x0 16.--30. 1. "ASF_TRANS_TO_CTRL_RESV1_FLD,Reserved" newline hexmask.long.word 0x0 0.--15. 1. "ASF_TRANS_TO_CTRL_FLD,Time value to use for transaction timeout monitor" line.long 0x4 "ASF_TRANS_TO_FAULT_MASK_REG,Control Register to mask out ASF transaction timeout faults from triggering interrupts" hexmask.long 0x4 1.--31. 1. "ASF_TRANS_TO_FAULT_STATUS_RESV1_FLD,Reserved" newline bitfld.long 0x4 0. "ASF_TRANS_TO_FAULT_MASK_FLD,Mask for AHB ASF transaction timeout fault source" "0,1" line.long 0x8 "ASF_TRANS_TO_FAULT_STATUS_REG,Status register for transaction timeouts fault" hexmask.long 0x8 1.--31. 1. "ASF_TRANS_TO_FAULT_STATUS_RESV1_FLD,Reserved" newline bitfld.long 0x8 0. "ASF_TRANS,Status bit for transaction timeouts faults" "0,1" group.long 0xA40++0x7 line.long 0x0 "ASF_PROTOCOL_FAULT_MASK_REG,Control register to mask out ASF Protocol faults from triggering interrupts" hexmask.long.word 0x0 19.--31. 1. "ASF_PROTOCOL_FAULT_MASK_RESV2_FLD,Reserved" newline bitfld.long 0x0 18. "ASF_PROTOCOL_FAULT_MASK_FLASH_CFG_FLD,Mask bit for Tri state enable fault" "0,1" newline bitfld.long 0x0 17. "ASF_PROTOCOL_FAULD_MASK_CS_FLD,Mask bit for Tri state enable fault" "0,1" newline bitfld.long 0x0 16. "ASF_PROTOCOL_FAULT_MASK_TRI_FLD,Mask bit for Tri state enable fault" "0,1" newline hexmask.long.word 0x0 4.--15. 1. "ASF_PROTOCOL_FAULT_MASK_RESV1_FLD,Reserved" newline bitfld.long 0x0 3. "ASF_PROTOCOL_FAULT_MASK_ECC_FLD,Mask bit for ECC failure" "0,1" newline bitfld.long 0x0 2. "ASF_PROTOCOL_MASK_TX_CRC_FLD,Mask bit for Polling expiration error" "0,1" newline bitfld.long 0x0 1. "ASF_PROTOCOL_FAULT_MASK_RX_CRC_FLD,Mask bit for Polling expiration error" "0,1" newline bitfld.long 0x0 0. "ASF_PROTOCOL_FAULT_MASK_POLL_FLD,Mask bit for Polling expiration error" "0,1" line.long 0x4 "ASF_PROTOCOL_FAULT_STATUS_REG,Status register for protocol faults" hexmask.long.word 0x4 19.--31. 1. "ASF_PROTOCOL_FAULT_STATUS_RESV2_FLD,Reserved" newline bitfld.long 0x4 18. "ASF_PROTOCOL_FAULT_STATUS_FLASH_CFG_FLD,Flash Configuration failure" "0,1" newline bitfld.long 0x4 17. "ASF_PROTOCOL_FAULT_STATUS_CS_FLD,#CS fault" "0,1" newline bitfld.long 0x4 16. "ASF_PROTOCOL_FAULT_STATUS_TRI_FLD,Tri state enable fault" "0,1" newline hexmask.long.word 0x4 4.--15. 1. "ASF_PROTOCOL_FAULT_STATUS_RESV1_FLD,Reserved" newline bitfld.long 0x4 3. "ASF_PROTOCOL_FAULT_STATUS_ECC,ECC failure" "0,1" newline bitfld.long 0x4 2. "ASF_PROTOCOL_FAULT_STATUS_TX_CRC,TX CRC chunk was broken" "0,1" newline bitfld.long 0x4 1. "ASF_PROTOCOL_FAULT_STATUS_RX_CRC_FLD,RX CRC data error" "0,1" newline bitfld.long 0x4 0. "ASF_PROTOCOL_FAULT_STATUS_POLL_FLD,Polling expiration error" "0,1" tree.end tree "OSPI2" base ad:0x306D0000 group.long 0x0++0x2B line.long 0x0 "CONFIG_REG,Octal-SPI Configuration Register" rbitfld.long 0x0 31. "IDLE_FLD,Serial interface and low level SPI pipeline is IDLE: This is a STATUS read-only bit. Note this is a retimed signal so there will be some inherent delay on the generation of this status signal." "0,1" newline bitfld.long 0x0 30. "DUAL_BYTE_OPCODE_EN_FLD,Dual-byte Opcode Mode enable bit This bit is to be set in case the target Flash Device supports dual byte opcode (i.e. Macronix MX25). It is applicable for Octal I/O Mode or Protocol only so should be set back to low if the device.." "0,1" newline bitfld.long 0x0 29. "CRC_ENABLE_FLD,CRC enable bit This bit is to be set in case the target Flash Device supports CRC (Macronix MX25). It is applicable for Octal DDR Protocol only so should be set back to low if the device is configured to work in another SPI Mode." "0,1" newline bitfld.long 0x0 28. "FLIPPER_ENABLE_FLD,Flip enable bit This bit is to be set in case the target Flash Device supports data slices swapped in order of D1 D0 D3 D2 etc. It is applicable for DTR-OPI Mode of Macronix MX25 devices." "0,1" newline rbitfld.long 0x0 26.--27. "CONFIG_RESV2_FLD,Reserved" "0,1,2,3" newline bitfld.long 0x0 25. "PIPELINE_PHY_FLD,Pipeline PHY Mode enable: This bit is relevant only for configuration with PHY Module. It should be asserted to '1' between consecutive PHY pipeline reads transfers and de-asserted to '0' otherwise." "0,1" newline bitfld.long 0x0 24. "ENABLE_DTR_PROTOCOL_FLD,Enable DTR Protocol: This bit should be set if device is configured to work in DTR protocol." "0,1" newline bitfld.long 0x0 23. "ENABLE_AHB_DECODER_FLD,Enable AHB Decoder: Value=0 : Active slave is selected based on Peripheral Chip Select Lines (bits [13:10]). Value=1 Active slave is selected based on actual AHB address (the partition for each device is calculated with respect to.." "Active slave is selected based on Peripheral..,?" newline hexmask.long.byte 0x0 19.--22. 1. "MSTR_BAUD_DIV_FLD,Master Mode Baud Rate Divisor: SPI baud rate = (master reference clock) baud_rate_divisor" newline bitfld.long 0x0 18. "ENTER_XIP_MODE_IMM_FLD,Enter XIP Mode immediately: Value=0 : If XIP is enabled then setting to 0 will cause the controller to exit XIP mode on the next READ instruction. Value=1 : Operate the device in XIP mode immediately Use this register when the.." "If XIP is enabled,Operate the device in XIP mode immediately Use.." newline bitfld.long 0x0 17. "ENTER_XIP_MODE_FLD,Enter XIP Mode on next READ: Value=0 : If XIP is enabled then setting to 0 will cause the controller to exit XIP mode on the next READ instruction. Value=1 : If XIP is disabled then setting to ?1? will inform the controller that the.." "If XIP is enabled,If XIP is disabled" newline bitfld.long 0x0 16. "ENB_AHB_ADDR_REMAP_FLD,Enable AHB Address Re-mapping: (Direct Access Mode Only) When set to 1 the incoming AHB address will be adapted and sent to the FLASH device as (address + N) where N is the value stored in the remap address register." "0,1" newline bitfld.long 0x0 15. "ENB_DMA_IF_FLD,Enable DMA Peripheral Interface: Set to 1 to enable the DMA handshaking logic. When enabled the controller will trigger DMA transfer requests via the DMA peripheral interface. Set to 0 to disable" "0,1" newline bitfld.long 0x0 14. "WR_PROT_FLASH_FLD,Write Protect Flash Pin: Set to drive the Write Protect pin of the FLASH device. This is resynchronized to the generated memory clock as necessary." "0,1" newline hexmask.long.byte 0x0 10.--13. 1. "PERIPH_CS_LINES_FLD,Peripheral Chip Select Lines: Peripheral chip select lines If pdec = 0 ss[3:0] are output thus: ss[3:0] n_ss_out[3:0] xxx0 1110 xx01 1101 x011 1011 0111 0111 1111 1111 (no peripheral selected) else ss[3:0] directly drives n_ss_out[3:0]" newline bitfld.long 0x0 9. "PERIPH_SEL_DEC_FLD,Peripheral select decode: 0 : only 1 of 4 selects n_ss_out[3:0] is active 1 : allow external 4-to-16 decode (n_ss_out = ss)" "only 1 of 4 selects n_ss_out[3:0] is active,allow external 4-to-16 decode" newline bitfld.long 0x0 8. "ENB_LEGACY_IP_MODE_FLD,Legacy IP Mode Enable: 0 : Use Direct Access Controller/Indirect Access Controller 1 : legacy Mode is enabled. In this mode any write to the controller via the AHB interface is serialized and sent to the FLASH device. Any valid.." "Use Direct Access Controller/Indirect Access..,legacy Mode is enabled" newline bitfld.long 0x0 7. "ENB_DIR_ACC_CTLR_FLD,Enable Direct Access Controller: 0 : disable the Direct Access Controller once current transfer of the data word (FF_W) is complete. 1 : enable the Direct Access Controller When the Direct Access Controller and Indirect Access.." "disable the Direct Access Controller once..,enable the Direct Access Controller When the.." newline bitfld.long 0x0 6. "RESET_CFG_FLD,RESET pin configuration: 0 = RESET feature on DQ3 pin of the device 1 = RESET feature on dedicated pin of the device (controlling of 5th bit influences on reset_out output)" "RESET feature on DQ3 pin of the device,RESET feature on dedicated pin of the device" newline bitfld.long 0x0 5. "RESET_PIN_FLD,Set to drive the RESET pin of the FLASH device and reset for de-activation of the RESET pin feature" "0,1" newline bitfld.long 0x0 4. "HOLD_PIN_FLD,Set to drive the HOLD pin of the FLASH device and reset for de-activation of the HOLD pin feature" "0,1" newline bitfld.long 0x0 3. "PHY_MODE_ENABLE_FLD,PHY mode enable: When enabled the controller is informed that PHY Module is to be used for handling SPI transfers. This bit is relevant only for configuration with PHY Module. Note: - When changing this bit field software should.." "0,1" newline bitfld.long 0x0 2. "SEL_CLK_PHASE_FLD,Select Clock Phase: Selects whether the clock is in an active or inactive phase outside the SPI word. 0 : the SPI clock is active outside the word 1 : the SPI clock is inactive outside the word" "the SPI clock is active outside the word,the SPI clock is inactive outside the word" newline bitfld.long 0x0 1. "SEL_CLK_POL_FLD,Clock polarity outside SPI word: 0 : the SPI clock is quiescent low 1 : the SPI clock is quiescent high" "the SPI clock is quiescent low,the SPI clock is quiescent high" newline bitfld.long 0x0 0. "ENB_SPI_FLD,Octal-SPI Enable: 0 : disable the Octal-SPI once current transfer of the data word (FF_W) is complete. 1 : enable the Octal-SPI when spi_enable = 0 all output enables are inactive and all pins are set to input mode." "disable the Octal-SPI,enable the Octal-SPI" line.long 0x4 "DEV_INSTR_RD_CONFIG_REG,Device Read Instruction Configuration Register" rbitfld.long 0x4 29.--31. "RD_INSTR_RESV5_FLD,Reserved" "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x4 24.--28. 1. "DUMMY_RD_CLK_CYCLES_FLD,Dummy Read Clock Cycles: Number of dummy clock cycles required by device for read instruction." newline rbitfld.long 0x4 21.--23. "RD_INSTR_RESV4_FLD,Reserved" "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 20. "MODE_BIT_ENABLE_FLD,Mode Bit Enable: Set this field to 1 to ensure that the mode bits as defined in the Mode Bit Configuration register are sent following the address bytes." "0,1" newline rbitfld.long 0x4 18.--19. "RD_INSTR_RESV3_FLD,Reserved" "0,1,2,3" newline bitfld.long 0x4 16.--17. "DATA_XFER_TYPE_EXT_MODE_FLD,Data Transfer Type for Standard SPI modes: 0 : SIO mode data is shifted to the device on DQ0 only and from the device on DQ1 only 1 : Used for Dual Input/Output instructions. For data transfers DQ0 and DQ1 are used as both.." "SIO mode data is shifted to the device on DQ0..,Used for Dual Input/Output instructions,Used for Quad Input/Output instructions,Used for Quad Input/Output instructions" newline rbitfld.long 0x4 14.--15. "RD_INSTR_RESV2_FLD,Reserved" "0,1,2,3" newline bitfld.long 0x4 12.--13. "ADDR_XFER_TYPE_STD_MODE_FLD,Address Transfer Type for Standard SPI modes: 0 : Addresses can be shifted to the device on DQ0 only 1 : Addresses can be shifted to the device on DQ0 and DQ1 only 2 : Addresses can be shifted to the device on DQ0 DQ1 DQ2.." "Addresses can be shifted to the device on DQ0 only,Addresses can be shifted to the device on DQ0..,Addresses can be shifted to the device on DQ0,Addresses can be shifted to the device on DQ[7:0]" newline bitfld.long 0x4 11. "PRED_DIS_FLD,Predicted Read Disable Bit: Disable generation of predicted read when doing read accesses using Direct Mode" "0,1" newline bitfld.long 0x4 10. "DDR_EN_FLD,DDR Enable: This is to inform that opcode from rd_opcode_non_xip_fld is compliant with one of the DDR READ Commands" "0,1" newline bitfld.long 0x4 8.--9. "INSTR_TYPE_FLD,Instruction Type: 0 : Use Standard SPI mode (instruction always shifted into the device on DQ0 only) 1 : Use DIO-SPI mode (Instructions Address and Data always sent on DQ0 and DQ1) 2 : Use QIO-SPI mode (Instructions Address and Data.." "Use Standard SPI mode,Use DIO-SPI mode,Use QIO-SPI mode,Use Octal-IO-SPI mode" newline hexmask.long.byte 0x4 0.--7. 1. "RD_OPCODE_NON_XIP_FLD,Read Opcode in non-XIP mode: Read Opcode to use when not in XIP mode" line.long 0x8 "DEV_INSTR_WR_CONFIG_REG,Device Write Instruction Configuration Register" rbitfld.long 0x8 29.--31. "WR_INSTR_RESV4_FLD,Reserved" "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x8 24.--28. 1. "DUMMY_WR_CLK_CYCLES_FLD,Dummy Write Clock Cycles: Number of dummy clock cycles required by device for write instruction." newline hexmask.long.byte 0x8 18.--23. 1. "WR_INSTR_RESV3_FLD,Reserved" newline bitfld.long 0x8 16.--17. "DATA_XFER_TYPE_EXT_MODE_FLD,Data Transfer Type for Standard SPI modes: 0 : SIO mode data is shifted to the device on DQ0 only and from the device on DQ1 only 1 : Used for Dual Input/Output instructions. For data transfers DQ0 and DQ1 are used as both.." "SIO mode data is shifted to the device on DQ0..,Used for Dual Input/Output instructions,Used for Quad Input/Output instructions,Used for Octal Input/Output instructions" newline rbitfld.long 0x8 14.--15. "WR_INSTR_RESV2_FLD,Reserved" "0,1,2,3" newline bitfld.long 0x8 12.--13. "ADDR_XFER_TYPE_STD_MODE_FLD,Address Transfer Type for Standard SPI modes: 0 : Addresses can be shifted to the device on DQ0 only 1 : Addresses can be shifted to the device on DQ0 and DQ1 only 2 : Addresses can be shifted to the device on DQ0 DQ1 DQ2.." "Addresses can be shifted to the device on DQ0 only,Addresses can be shifted to the device on DQ0..,Addresses can be shifted to the device on DQ0,Addresses can be shifted to the device on DQ[7:0]" newline rbitfld.long 0x8 9.--11. "WR_INSTR_RESV1_FLD,Reserved" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 8. "WEL_DIS_FLD,WEL Disable: This is to turn off automatic issuing of WEL Command before write operation for DAC or INDAC" "0,1" newline hexmask.long.byte 0x8 0.--7. 1. "WR_OPCODE_FLD,Write Opcode" line.long 0xC "DEV_DELAY_REG,Octal-SPI Device Delay Register: This register is used to introduce relative delays into the generation of the master output signals. All timings are defined in cycles of the SPI REFERENCE CLOCK/ext_clk. defined in this table as SPI master.." hexmask.long.byte 0xC 24.--31. 1. "D_NSS_FLD,Clock Delay for Chip Select Deassert: Delay in master reference clocks for the length that the master mode chip select outputs are de-asserted between transactions. The minimum delay is always SCLK period to ensure the chip select is never.." newline hexmask.long.byte 0xC 16.--23. 1. "D_BTWN_FLD,Clock Delay for Chip Select Deactivation: Delay in master reference clocks between one chip select being de-activated and the activation of another. This is used to ensure a quiet period between the selection of two different slaves and.." newline hexmask.long.byte 0xC 8.--15. 1. "D_AFTER_FLD,Clock Delay for Last Transaction Bit: Delay in master reference clocks between last bit of current transaction and deasserting the device chip select (n_ss_out). By default the chip select will be deasserted on the cycle following the.." newline hexmask.long.byte 0xC 0.--7. 1. "D_INIT_FLD,Clock Delay with n_ss_out: Delay in master reference clocks between setting n_ss_out low and first bit transfer." line.long 0x10 "RD_DATA_CAPTURE_REG,Read Data Capture Register" hexmask.long.word 0x10 20.--31. 1. "RD_DATA_RESV3_FLD,Reserved" newline hexmask.long.byte 0x10 16.--19. 1. "DDR_READ_DELAY_FLD,DDR read delay: Delay the transmitted data by the programmed number of ref_clk cycles.This field is only relevant when DDR Read Command is executed. Otherwise can be ignored." newline hexmask.long.byte 0x10 9.--15. 1. "RD_DATA_RESV2_FLD,Reserved" newline bitfld.long 0x10 8. "DQS_ENABLE_FLD,DQS enable bit: If enabled signal from DQS input is driven into RX DLL and is used for data capturing in PHY Mode rather than internally generated gated ref_clk.." "0,1" newline rbitfld.long 0x10 6.--7. "RD_DATA_RESV1_FLD,Reserved" "0,1,2,3" newline bitfld.long 0x10 5. "SAMPLE_EDGE_SEL_FLD,Sample edge selection: Choose edge on which data outputs from flash memory will be sampled" "0,1" newline hexmask.long.byte 0x10 1.--4. 1. "DELAY_FLD,Read Delay: Delay the read data capturing logic by the programmed number of ref_clk cycles" newline bitfld.long 0x10 0. "BYPASS_FLD,Bypass the adapted loopback clock circuit" "0,1" line.long 0x14 "DEV_SIZE_CONFIG_REG,Device Size Configuration Register" rbitfld.long 0x14 29.--31. "DEV_SIZE_RESV_FLD,Reserved" "0,1,2,3,4,5,6,7" newline bitfld.long 0x14 27.--28. "MEM_SIZE_ON_CS3_FLD,Size of Flash Device connected to CS[3] pin: Value=00 : size of 512Mb. Value=01 : size of 1Gb. Value=10 : size of 2Gb. Value=11 : size of 4Gb." "size of 512Mb,size of 1Gb,?,?" newline bitfld.long 0x14 25.--26. "MEM_SIZE_ON_CS2_FLD,Size of Flash Device connected to CS[2] pin: Value=00 : size of 512Mb. Value=01 : size of 1Gb. Value=10 : size of 2Gb. Value=11 : size of 4Gb." "size of 512Mb,size of 1Gb,?,?" newline bitfld.long 0x14 23.--24. "MEM_SIZE_ON_CS1_FLD,Size of Flash Device connected to CS[1] pin: Value=00 : size of 512Mb. Value=01 : size of 1Gb. Value=10 : size of 2Gb. Value=11 : size of 4Gb." "size of 512Mb,size of 1Gb,?,?" newline bitfld.long 0x14 21.--22. "MEM_SIZE_ON_CS0_FLD,Size of Flash Device connected to CS[0] pin: Value=00 : size of 512Mb. Value=01 : size of 1Gb. Value=10 : size of 2Gb. Value=11 : size of 4Gb." "size of 512Mb,size of 1Gb,?,?" newline hexmask.long.byte 0x14 16.--20. 1. "BYTES_PER_SUBSECTOR_FLD,Number of bytes per Block. This is required by the controller for performing the write protection logic. The number of bytes per block must be a power of 2 number." newline hexmask.long.word 0x14 4.--15. 1. "BYTES_PER_DEVICE_PAGE_FLD,Number of bytes per device page. This is required by the controller for performing FLASH writes up to and across page boundaries." newline hexmask.long.byte 0x14 0.--3. 1. "NUM_ADDR_BYTES_FLD,Number of address bytes. A value of 0 indicates 1 byte." line.long 0x18 "SRAM_PARTITION_CFG_REG,SRAM Partition Configuration Register" hexmask.long.tbyte 0x18 8.--31. 1. "SRAM_PARTITION_RESV_FLD,Reserved" newline hexmask.long.byte 0x18 0.--7. 1. "ADDR_FLD,Indirect Read Partition Size: Defines the size of the indirect read partition in the SRAM in units of SRAM locations. By default half of the SRAM is reserved for indirect read operation and half for indirect write. The size of this register.." line.long 0x1C "IND_AHB_ADDR_TRIGGER_REG,Indirect AHB Address Trigger Register" hexmask.long 0x1C 0.--31. 1. "ADDR_FLD,This is the base address that will be used by the AHB controller. When the incoming AHB read access address matches a range of addresses from this trigger address to the trigger address + 15 then the AHB request will be completed by fetching.." line.long 0x20 "DMA_PERIPH_CONFIG_REG,DMA Peripheral Configuration Register" hexmask.long.tbyte 0x20 12.--31. 1. "DMA_PERIPH_RESV2_FLD,Reserved" newline hexmask.long.byte 0x20 8.--11. 1. "NUM_BURST_REQ_BYTES_FLD,Number of Burst Bytes: Number of bytes in a burst type request on the DMA peripheral request. A programmed value of 0 represents a single byte. This should be setup before starting the indirect read or write operation. The actual.." newline hexmask.long.byte 0x20 4.--7. 1. "DMA_PERIPH_RESV1_FLD,Reserved" newline hexmask.long.byte 0x20 0.--3. 1. "NUM_SINGLE_REQ_BYTES_FLD,Number of Single Bytes: Number of bytes in a single type request on the DMA peripheral request. A programmed value of 0 represents a single byte. This should be setup before starting the indirect read or write operation. The.." line.long 0x24 "REMAP_ADDR_REG,Remap Address Register" hexmask.long 0x24 0.--31. 1. "VALUE_FLD,This register is used to remap an incoming AHB address to a different address used by the FLASH device." line.long 0x28 "MODE_BIT_CONFIG_REG,Mode Bit Configuration Register" hexmask.long.byte 0x28 24.--31. 1. "RX_CRC_DATA_LOW_FLD,RX CRC data (lower) The first CRC byte returned after RX data chunk." newline hexmask.long.byte 0x28 16.--23. 1. "RX_CRC_DATA_UP_FLD,RX CRC data (upper) The second CRC byte returned after RX data chunk." newline bitfld.long 0x28 15. "CRC_OUT_ENABLE_FLD,CRC# output enable bit When enabled the controller expects the Flash Device to toggle CRC data on both SPI clock edges in CRC->CRC# sequence and calculates CRC compliance accordingly." "0,1" newline hexmask.long.byte 0x28 11.--14. 1. "MODE_BIT_RESV1_FLD,Reserved" newline bitfld.long 0x28 8.--10. "CHUNK_SIZE_FLD,It defines size of chunk after which CRC data is expected to show up on the SPI interface for write and read data transfers." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x28 0.--7. 1. "MODE_FLD,These are the 8 mode bits that are sent to the device following the address bytes if mode bit transmission has been enabled." rgroup.long 0x2C++0x3 line.long 0x0 "SRAM_FILL_REG,SRAM Fill Register" hexmask.long.word 0x0 16.--31. 1. "SRAM_FILL_INDAC_WRITE_FLD,SRAM Fill Level (Indirect Write Partition): Identifies the current fill level of the SRAM Indirect Write partition" newline hexmask.long.word 0x0 0.--15. 1. "SRAM_FILL_INDAC_READ_FLD,SRAM Fill Level (Indirect Read Partition): Identifies the current fill level of the SRAM Indirect Read partition" group.long 0x30++0x17 line.long 0x0 "TX_THRESH_REG,TX Threshold Register" hexmask.long 0x0 5.--31. 1. "TX_THRESH_RESV_FLD,Reserved" newline hexmask.long.byte 0x0 0.--4. 1. "LEVEL_FLD,Defines the level at which the small TX FIFO not full interrupt is generated" line.long 0x4 "RX_THRESH_REG,RX Threshold Register" hexmask.long 0x4 5.--31. 1. "RX_THRESH_RESV_FLD,Reserved" newline hexmask.long.byte 0x4 0.--4. 1. "LEVEL_FLD,Defines the level at which the small RX FIFO not empty interrupt is generated" line.long 0x8 "WRITE_COMPLETION_CTRL_REG,Write Completion Control Register: This register defines how the controller will poll the device following a write transfer" hexmask.long.byte 0x8 24.--31. 1. "POLL_REP_DELAY_FLD,Defines additional delay for maintain Chip Select de-asserted during auto-polling phase" newline hexmask.long.byte 0x8 16.--23. 1. "POLL_COUNT_FLD,Defines the number of times the controller should expect to see a true result from the polling in successive reads of the device register." newline bitfld.long 0x8 15. "ENABLE_POLLING_EXP_FLD,Set to '1' for enabling auto-polling expiration." "0,1" newline bitfld.long 0x8 14. "DISABLE_POLLING_FLD,This switches off the automatic polling function" "0,1" newline bitfld.long 0x8 13. "POLLING_POLARITY_FLD,Defines the polling polarity. If '1' then the write transfer to the device will be complete if the polled bit is equal to '1'. If '0' then the write transfer to the device will be complete if the polled bit is equal to '0'." "0,1" newline rbitfld.long 0x8 12. "WR_COMP_CTRL_RESV1_FLD,Reserved" "0,1" newline bitfld.long 0x8 11. "POLLING_ADDR_EN_FLD,Enables address phase of auto-polling (Read Status) command." "0,1" newline bitfld.long 0x8 8.--10. "POLLING_BIT_INDEX_FLD,Defines the bit index that should be polled. A value of 010 means that bit 2 of the returned data will be polled for.A value of 111 means that bit 7 of the returned data will be polled for." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x8 0.--7. 1. "OPCODE_FLD,Defines the opcode that should be issued by the controller when it is automatically polling for device program completion. This command is issued followed all device write operations. By default this will poll the standard device STATUS.." line.long 0xC "NO_OF_POLLS_BEF_EXP_REG,Polling Expiration Register" hexmask.long 0xC 0.--31. 1. "NO_OF_POLLS_BEF_EXP_FLD,Number of polls cycles before expiration" line.long 0x10 "IRQ_STATUS_REG,Interrupt Status Register: The status fields in this register are set when the described event occurs and the interrupt is enabled in the mask register. When any of these bit fields are set. the interrupt output is asserted high. The.." hexmask.long.word 0x10 21.--31. 1. "IRQ_STAT_RESV_FLD,Reserved" newline bitfld.long 0x10 20. "HYPER_INT_FLD,HyperFlash interrupt This interrupt informs the system that Flash Device reported interrupt on its INT# output" "0,1" newline bitfld.long 0x10 19. "ECC_FAIL_FLD,ECC failure This interrupt informs the system that Flash Device reported ECC error." "0,1" newline bitfld.long 0x10 18. "TX_CRC_CHUNK_BRK_FLD,TX CRC chunk was broken This interrupt informs the system that program page SPI transfer was discontinued somewhere inside the chunk." "0,1" newline bitfld.long 0x10 17. "RX_CRC_DATA_VAL_FLD,RX CRC data valid New RX CRC data was captured from Flash Device" "0,1" newline bitfld.long 0x10 16. "RX_CRC_DATA_ERR_FLD,RX CRC data error CRC data from Flash Device does not correspond to the one dynamically calculated by the controller." "0,1" newline rbitfld.long 0x10 15. "IRQ_STAT_RESV1_FLD,Reserved" "0,1" newline bitfld.long 0x10 14. "STIG_REQ_INT_FLD,The controller is ready for getting another STIG request." "0,1" newline bitfld.long 0x10 13. "POLL_EXP_INT_FLD,The maximum number of programmed polls cycles is expired" "0,1" newline bitfld.long 0x10 12. "INDRD_SRAM_FULL_FLD,Indirect Read Partition overflow: Indirect Read Partition of SRAM is full and unable to immediately complete indirect operation" "0,1" newline bitfld.long 0x10 11. "RX_FIFO_FULL_FLD,Small RX FIFO full: Current FIFO status can be ignored in non-SPI legacy mode 0 : FIFO is not full 1 : FIFO is full" "FIFO is not full,FIFO is full" newline bitfld.long 0x10 10. "RX_FIFO_NOT_EMPTY_FLD,Small RX FIFO not empty: Current FIFO status can be ignored in non-SPI legacy mode 0 : FIFO has less than RX THRESHOLD entries 1 : FIFO has >= THRESHOLD entries" "FIFO has less than RX THRESHOLD entries,FIFO has >= THRESHOLD entries" newline bitfld.long 0x10 9. "TX_FIFO_FULL_FLD,Small TX FIFO full: Current FIFO status can be ignored in non-SPI legacy mode 0 : FIFO is not full 1 : FIFO is full" "FIFO is not full,FIFO is full" newline bitfld.long 0x10 8. "TX_FIFO_NOT_FULL_FLD,Small TX FIFO not full: Current FIFO status can be ignored in non-SPI legacy mode 0 : FIFO has >= THRESHOLD entries 1 : FIFO has less than THRESHOLD entries" "FIFO has >= THRESHOLD entries,FIFO has less than THRESHOLD entries" newline bitfld.long 0x10 7. "RECV_OVERFLOW_FLD,Receive Overflow: This should only occur in Legacy SPI mode. Set if an attempt is made to push the RX FIFO when it is full. This bit is reset only by a system reset and cleared only when this register is read. If a new push to the RX.." "no overflow has been detected,an overflow has occurred" newline bitfld.long 0x10 6. "INDIRECT_XFER_LEVEL_BREACH_FLD,Indirect Transfer Watermark Level Breached" "0,1" newline bitfld.long 0x10 5. "ILLEGAL_ACCESS_DET_FLD,Illegal AHB access has been detected. AHB wrapping bursts and the use of SPLIT/RETRY accesses will cause this error interrupt to trigger." "0,1" newline bitfld.long 0x10 4. "PROT_WR_ATTEMPT_FLD,Write to protected area was attempted and rejected." "0,1" newline bitfld.long 0x10 3. "INDIRECT_TRANSFER_REJECT_FLD,Indirect operation was requested but could not be accepted. Two indirect operations already in storage." "0,1" newline bitfld.long 0x10 2. "INDIRECT_OP_DONE_FLD,Indirect Operation Complete: Controller has completed last triggered indirect operation" "0,1" newline bitfld.long 0x10 1. "UNDERFLOW_DET_FLD,Underflow Detected: 0 : no underflow has been detected 1 : underflow is detected and an attempt to transfer data is made when the small TX FIFO is empty. This may occur when AHB write data is being supplied too slowly to keep up with.." "no underflow has been detected,underflow is detected and an attempt to transfer.." newline bitfld.long 0x10 0. "MODE_M_FAIL_FLD,Mode M Failure: Mode M failure indicates the voltage on pin n_ss_in is inconsistent with the SPI mode. Set =1 if n_ss_in is low in master mode (multi-master contention). These conditions will clear the spi_enable bit and disable the SPI." "no mode fault has been detected,a mode fault has occurred" line.long 0x14 "IRQ_MASK_REG,Interrupt Mask: 0 : the interrupt for the corresponding interrupt status register bit is disabled. 1 : the interrupt for the corresponding interrupt status register bit is enabled." hexmask.long.word 0x14 21.--31. 1. "IRQ_MASK_RESV_FLD,Reserved" newline bitfld.long 0x14 20. "HYPER_INT_MASK_FLD,HyperFlash interrupt Mask" "0,1" newline bitfld.long 0x14 19. "ECC_FAIL_MASK_FLD,ECC failure Mask" "0,1" newline bitfld.long 0x14 18. "TX_CRC_CHUNK_BRK_MASK_FLD,TX CRC chunk was broken Mask" "0,1" newline bitfld.long 0x14 17. "RX_CRC_DATA_VAL_MASK_FLD,RX CRC data valid Mask" "0,1" newline bitfld.long 0x14 16. "RX_CRC_DATA_ERR_MASK_FLD,RX CRC data error Mask" "0,1" newline rbitfld.long 0x14 15. "IRQ_MASK_RESV1_FLD,Reserved" "0,1" newline bitfld.long 0x14 14. "STIG_REQ_MASK_FLD,STIG request completion Mask" "0,1" newline bitfld.long 0x14 13. "POLL_EXP_INT_MASK_FLD,Polling expiration detected Mask" "0,1" newline bitfld.long 0x14 12. "INDRD_SRAM_FULL_MASK_FLD,Indirect Read Partition overflow mask" "0,1" newline bitfld.long 0x14 11. "RX_FIFO_FULL_MASK_FLD,Small RX FIFO full Mask" "0,1" newline bitfld.long 0x14 10. "RX_FIFO_NOT_EMPTY_MASK_FLD,Small RX FIFO not empty Mask" "0,1" newline bitfld.long 0x14 9. "TX_FIFO_FULL_MASK_FLD,Small TX FIFO full Mask" "0,1" newline bitfld.long 0x14 8. "TX_FIFO_NOT_FULL_MASK_FLD,Small TX FIFO not full Mask" "0,1" newline bitfld.long 0x14 7. "RECV_OVERFLOW_MASK_FLD,Receive Overflow Mask" "0,1" newline bitfld.long 0x14 6. "INDIRECT_XFER_LEVEL_BREACH_MASK_FLD,Transfer Watermark Breach Mask" "0,1" newline bitfld.long 0x14 5. "ILLEGAL_ACCESS_DET_MASK_FLD,Illegal Access Detected Mask" "0,1" newline bitfld.long 0x14 4. "PROT_WR_ATTEMPT_MASK_FLD,Protected Area Write Attempt Mask" "0,1" newline bitfld.long 0x14 3. "INDIRECT_TRANSFER_REJECT_MASK_FLD,Indirect Read Reject Mask" "0,1" newline bitfld.long 0x14 2. "INDIRECT_OP_DONE_MASK_FLD,Indirect Complete Mask" "0,1" newline bitfld.long 0x14 1. "UNDERFLOW_DET_MASK_FLD,Underflow Detected Mask" "0,1" newline bitfld.long 0x14 0. "MODE_M_FAIL_MASK_FLD,Mode M Failure Mask" "0,1" group.long 0x50++0xB line.long 0x0 "LOWER_WR_PROT_REG,Lower Write Protection Register" hexmask.long 0x0 0.--31. 1. "SUBSECTOR_FLD,The block number that defines the lower block in the range of blocks that is to be locked from writing. The definition of a block in terms of number of bytes is programmable via the Device Size Configuration register." line.long 0x4 "UPPER_WR_PROT_REG,Upper Write Protection Register" hexmask.long 0x4 0.--31. 1. "SUBSECTOR_FLD,The block number that defines the upper block in the range of blocks that is to be locked from writing. The definition of a block in terms of number of bytes is programmable via the Device Size Configuration register." line.long 0x8 "WR_PROT_CTRL_REG,Write Protection Control Register" hexmask.long 0x8 2.--31. 1. "WR_PROT_CTRL_RESV_FLD,Reserved" newline bitfld.long 0x8 1. "ENB_FLD,Write Protection Enable Bit: When set to 1 any AHB write access with an address within the protection region defined in the lower and upper write protection registers is rejected. An AHB error response is generated and an interrupt source.." "0,1" newline bitfld.long 0x8 0. "INV_FLD,Write Protection Inversion Bit: When set to 1 the protection region defined in the lower and upper write protection registers is inverted meaning it is the region that the system is permitted to write to. When set to 0 the protection region.." "0,1" group.long 0x60++0x23 line.long 0x0 "INDIRECT_READ_XFER_CTRL_REG,Indirect Read Transfer Control Register" hexmask.long.tbyte 0x0 8.--31. 1. "INDIR_RD_XFER_RESV_FLD,Reserved" newline rbitfld.long 0x0 6.--7. "NUM_IND_OPS_DONE_FLD,This field contains the number of indirect operations which have been completed. This is used in conjunction with the indirect completion status field (bit 5). It is incremented by hardware when an indirect operation has completed." "0,1,2,3" newline bitfld.long 0x0 5. "IND_OPS_DONE_STATUS_FLD,Indirect Completion Status: This field is set to 1 when an indirect operation has completed. Write a 1 to this field to clear it." "0,1" newline rbitfld.long 0x0 4. "RD_QUEUED_FLD,Two indirect read operations have been queued" "0,1" newline bitfld.long 0x0 3. "SRAM_FULL_FLD,SRAM Full: SRAM full and unable to immediately complete an indirect operation. Write a 1 to this field to clear it.\'; indirect operation (status)" "0,1" newline rbitfld.long 0x0 2. "RD_STATUS_FLD,Indirect Read Status: Indirect read operation in progress (status)" "0,1" newline bitfld.long 0x0 1. "CANCEL_FLD,Cancel Indirect Read: Writing a 1 to this bit will cancel all ongoing indirect read operations." "0,1" newline bitfld.long 0x0 0. "START_FLD,Start Indirect Read: Writing a 1 to this bit will trigger an indirect read operation. The assumption is that the indirect start address and the indirect number of bytes register is setup before triggering the indirect read operation." "0,1" line.long 0x4 "INDIRECT_READ_XFER_WATERMARK_REG,Indirect Read Transfer Watermark Register" hexmask.long 0x4 0.--31. 1. "LEVEL_FLD,Watermark Value: This represents the minimum fill level of the SRAM before a DMA peripheral access is permitted. When the SRAM fill level passes the watermark an interrupt is also generated. This field can be disabled by writing a value of all.." line.long 0x8 "INDIRECT_READ_XFER_START_REG,Indirect Read Transfer Start Address Register" hexmask.long 0x8 0.--31. 1. "ADDR_FLD,This is the start address from which the indirect access will commence its READ operation." line.long 0xC "INDIRECT_READ_XFER_NUM_BYTES_REG,Indirect Read Transfer Number Bytes Register" hexmask.long 0xC 0.--31. 1. "VALUE_FLD,This is the number of bytes that the indirect access will consume. This can be bigger than the configured size of SRAM." line.long 0x10 "INDIRECT_WRITE_XFER_CTRL_REG,Indirect Write Transfer Control Register" hexmask.long.tbyte 0x10 8.--31. 1. "INDIR_WR_XFER_RESV2_FLD,Reserved" newline rbitfld.long 0x10 6.--7. "NUM_IND_OPS_DONE_FLD,This field contains the number of indirect operations which have been completed. This is used in conjunction with the indirect completion status field (bit 5). It is incremented by hardware when an indirect operation has completed." "0,1,2,3" newline bitfld.long 0x10 5. "IND_OPS_DONE_STATUS_FLD,Indirect Completion Status: This field is set to 1 when an indirect operation has completed. Write a 1 to this field to clear it." "0,1" newline rbitfld.long 0x10 4. "WR_QUEUED_FLD,Two indirect write operations have been queued" "0,1" newline rbitfld.long 0x10 3. "INDIR_WR_XFER_RESV1_FLD,Reserved" "0,1" newline rbitfld.long 0x10 2. "WR_STATUS_FLD,Indirect Write Status: Indirect write operation in progress (status)" "0,1" newline bitfld.long 0x10 1. "CANCEL_FLD,Cancel Indirect Write: Writing a 1 to this bit will cancel all ongoing indirect write operations." "0,1" newline bitfld.long 0x10 0. "START_FLD,Start Indirect Write: Writing a 1 to this bit will trigger an indirect write operation. The assumption is that the indirect start address and the indirect number of bytes register is setup before triggering the indirect write operation." "0,1" line.long 0x14 "INDIRECT_WRITE_XFER_WATERMARK_REG,Indirect Write Transfer Watermark Register" hexmask.long 0x14 0.--31. 1. "LEVEL_FLD,Watermark Value: This represents the maximum fill level of the SRAM before a DMA peripheral access is permitted. When the SRAM fill level falls below the watermark an interrupt is also generated. This field can be disabled by writing a value.." line.long 0x18 "INDIRECT_WRITE_XFER_START_REG,Indirect Write Transfer Start Address Register" hexmask.long 0x18 0.--31. 1. "ADDR_FLD,Start of Indirect Access: This is the start address from which the indirect access will commence its READ operation." line.long 0x1C "INDIRECT_WRITE_XFER_NUM_BYTES_REG,Indirect Write Transfer Number Bytes Register" hexmask.long 0x1C 0.--31. 1. "VALUE_FLD,Indirect Number of Bytes: This is the number of bytes that the indirect access will consume. This can be bigger than the configured size of SRAM." line.long 0x20 "INDIRECT_TRIGGER_ADDR_RANGE_REG,Indirect Trigger Address Range Register" hexmask.long 0x20 4.--31. 1. "IND_RANGE_RESV1_FLD,Reserved" newline hexmask.long.byte 0x20 0.--3. 1. "IND_RANGE_WIDTH_FLD,This is the address offset of Indirect Trigger Address Register." group.long 0x8C++0xB line.long 0x0 "FLASH_COMMAND_CTRL_MEM_REG,Flash Command Control Memory Register" rbitfld.long 0x0 29.--31. "FLASH_COMMAND_CTRL_MEM_RESV1_FLD,Reserved" "0,1,2,3,4,5,6,7" newline hexmask.long.word 0x0 20.--28. 1. "MEM_BANK_ADDR_FLD,The address of the Memory Bank which data will be read from." newline rbitfld.long 0x0 19. "FLASH_COMMAND_CTRL_MEM_RESV2_FLD,Reserved" "0,1" newline bitfld.long 0x0 16.--18. "NB_OF_STIG_READ_BYTES_FLD,It defines the number of read bytes for the extended STIG." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x0 8.--15. 1. "MEM_BANK_READ_DATA_FLD,Last requested data from the STIG Memory Bank." newline hexmask.long.byte 0x0 2.--7. 1. "FLASH_COMMAND_CTRL_MEM_RESV3_FLD,Reserved" newline rbitfld.long 0x0 1. "MEM_BANK_REQ_IN_PROGRESS_FLD,Memory Bank data request in progress." "0,1" newline bitfld.long 0x0 0. "TRIGGER_MEM_BANK_REQ_FLD,Trigger the Memory Bank data request." "0,1" line.long 0x4 "FLASH_CMD_CTRL_REG,Flash Command Control Register" hexmask.long.byte 0x4 24.--31. 1. "CMD_OPCODE_FLD,Command Opcode: The command opcode field should be setup before triggering the command. For example 0x20 maps to SubSector Erase. Writing to the execute field (bit 0) of this register launches the command. NOTE : Using this approach to.." newline bitfld.long 0x4 23. "ENB_READ_DATA_FLD,Read Data Enable: Set to 1 if the command specified in the command opcode field (bits 31:24) requires read data bytes to be received from the device." "0,1" newline bitfld.long 0x4 20.--22. "NUM_RD_DATA_BYTES_FLD,Number of Read Data Bytes: Up to 8 data bytes may be read using this command. Set to 0 for 1 byte and 7 for 8 bytes." "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 19. "ENB_COMD_ADDR_FLD,Command Address Enable: Set to 1 if the command specified in bits 31:24 requires an address. This should be setup before triggering the command via writing a 1 to the execute field." "0,1" newline bitfld.long 0x4 18. "ENB_MODE_BIT_FLD,Mode Bit Enable: Set to 1 to ensure the mode bits as defined in the Mode Bit Configuration register are sent following the address bytes." "0,1" newline bitfld.long 0x4 16.--17. "NUM_ADDR_BYTES_FLD,Number of Address Bytes: Set to the number of address bytes required (the address itself is programmed in the FLASH COMMAND ADDRESS REGISTERS). This should be setup before triggering the command via bit 0 of this register. 2'b00 : 1.." "0,1,2,3" newline bitfld.long 0x4 15. "ENB_WRITE_DATA_FLD,Write Data Enable: Set to 1 if the command specified in the command opcode field requires write data bytes to be sent to the device." "0,1" newline bitfld.long 0x4 12.--14. "NUM_WR_DATA_BYTES_FLD,Number of Write Data Bytes: Up to 8 Data bytes may be written using this command Set to 0 for 1 byte 7 for 8 bytes." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x4 7.--11. 1. "NUM_DUMMY_CYCLES_FLD,Number of Dummy cycles: Set to the number of dummy cycles required. This should be setup before triggering the command via the execute field of this register." newline hexmask.long.byte 0x4 3.--6. 1. "FLASH_CMD_CTRL_RESV1_FLD,Reserved" newline bitfld.long 0x4 2. "STIG_MEM_BANK_EN_FLD,STIG Memory Bank enable bit." "0,1" newline rbitfld.long 0x4 1. "CMD_EXEC_STATUS_FLD,Command execution in progress." "0,1" newline bitfld.long 0x4 0. "CMD_EXEC_FLD,Execute the command." "0,1" line.long 0x8 "FLASH_CMD_ADDR_REG,Flash Command Address Register" hexmask.long 0x8 0.--31. 1. "ADDR_FLD,Command Address: This should be setup before triggering the command with execute field (bit 0) of the Flash Command Control register. It is the address used by the command specified in the opcode field (bits 31:24) of the Flash Command Control.." rgroup.long 0xA0++0x7 line.long 0x0 "FLASH_RD_DATA_LOWER_REG,Flash Command Read Data Register (Lower)" hexmask.long 0x0 0.--31. 1. "DATA_FLD,This is the data that is returned by the flash device for any status or configuration read operation carried out by triggering the event in the control register. The register will be valid when the polling bit in the control register is low." line.long 0x4 "FLASH_RD_DATA_UPPER_REG,Flash Command Read Data Register (Upper)" hexmask.long 0x4 0.--31. 1. "DATA_FLD,This is the data that is returned by the FLASH device for any status or configuration read operation carried out by triggering the event in the control register. The register will be valid when the polling bit in the control register is low." group.long 0xA8++0x13 line.long 0x0 "FLASH_WR_DATA_LOWER_REG,Flash Command Write Data Register (Lower)" hexmask.long 0x0 0.--31. 1. "DATA_FLD,Command Write Data Lower Byte: This is the command write data lower byte. This should be setup before triggering the command with execute field (bit 0) of the Flash Command Control register. It is the data that is to be written to the flash for.." line.long 0x4 "FLASH_WR_DATA_UPPER_REG,Flash Command Write Data Register (Upper)" hexmask.long 0x4 0.--31. 1. "DATA_FLD,Command Write Data Upper Byte: This is the command write data upper byte. This should be setup before triggering the command with execute field (bit 0) of the Flash Command Control register. It is the data that is to be written to the flash for.." line.long 0x8 "POLLING_FLASH_STATUS_REG,Polling Flash Status Register" hexmask.long.word 0x8 21.--31. 1. "DEVICE_STATUS_RSVD_FLD2,Reserved" newline hexmask.long.byte 0x8 16.--20. 1. "DEVICE_STATUS_NB_DUMMY,Number of dummy cycles for auto-polling" newline hexmask.long.byte 0x8 9.--15. 1. "DEVICE_STATUS_RSVD_FLD1,Reserved" newline rbitfld.long 0x8 8. "DEVICE_STATUS_VALID_FLD,Device Status Valid: This should be set when value in bits from 7 to 0 is valid." "0,1" newline hexmask.long.byte 0x8 0.--7. 1. "DEVICE_STATUS_FLD,Defines actual Status Register of Device" line.long 0xC "PHY_CONFIGURATION_REG,PHY Configuration Register" bitfld.long 0xC 31. "PHY_CONFIG_RESYNC_FLD,This bit is used for re-synchronisation delay lines to update them with values from TX DLL Delay and RX DLL Delay fields." "0,1" newline bitfld.long 0xC 30. "PHY_CONFIG_RESET_FLD,DLL Reset bit: This bit is used for reset of Delay Lines by software." "0,1" newline bitfld.long 0xC 29. "PHY_CONFIG_RX_DLL_BYPASS_FLD,RX DLL Bypass: This field determines id RX DLL is bypassed." "0,1" newline hexmask.long.byte 0xC 23.--28. 1. "PHY_CONFIG_RESV2_FLD,Reserved" newline hexmask.long.byte 0xC 16.--22. 1. "PHY_CONFIG_TX_DLL_DELAY_FLD,TX DLL Delay: This field determines the number of delay elements to insert on data path between ref_clk and spi_clk." newline hexmask.long.word 0xC 7.--15. 1. "PHY_CONFIG_RESV1_FLD,Reserved" newline hexmask.long.byte 0xC 0.--6. 1. "PHY_CONFIG_RX_DLL_DELAY_FLD,RX DLL Delay: This field determines the number of delay elements to insert on data path between ref_clk and rx_dll_clk." line.long 0x10 "PHY_MASTER_CONTROL_REG,PHY DLL Master Control Register" hexmask.long.byte 0x10 25.--31. 1. "PHY_MASTER_CONTROL_RESV3_FLD,Reserved" newline bitfld.long 0x10 24. "PHY_MASTER_LOCK_MODE_FLD,Determines if the master delay line locks on a full cycle or half cycle of delay." "0,1" newline bitfld.long 0x10 23. "PHY_MASTER_BYPASS_MODE_FLD,Controls the bypass mode of the master and slave DLLs." "0,1" newline bitfld.long 0x10 20.--22. "PHY_MASTER_PHASE_DETECT_SELECTOR_FLD,Selects the number of delay elements to be inserted between the phase detect flip-flops." "0,1,2,3,4,5,6,7" newline rbitfld.long 0x10 19. "PHY_MASTER_CONTROL_RESV2_FLD,Reserved" "0,1" newline bitfld.long 0x10 16.--18. "PHY_MASTER_NB_INDICATIONS_FLD,Holds the number of consecutive increment or decrement indications." "0,1,2,3,4,5,6,7" newline hexmask.long.word 0x10 7.--15. 1. "PHY_MASTER_CONTROL_RESV1_FLD,Reserved" newline hexmask.long.byte 0x10 0.--6. 1. "PHY_MASTER_INITIAL_DELAY_FLD,This value is the initial delay value for the DLL." rgroup.long 0xBC++0x7 line.long 0x0 "DLL_OBSERVABLE_LOWER_REG,DLL Observable Register Lower" hexmask.long.byte 0x0 24.--31. 1. "DLL_OBSERVABLE_LOWER_DLL_LOCK_INC_FLD,Holds the state of the cumulative dll_lock_inc register." newline hexmask.long.byte 0x0 16.--23. 1. "DLL_OBSERVABLE_LOWER_DLL_LOCK_DEC_FLD,Holds the state of the cumulative dll_lock_dec register." newline bitfld.long 0x0 15. "DLL_OBSERVABLE_LOWER_LOOPBACK_LOCK_FLD,This bit indicates that lock of loopback is done." "0,1" newline hexmask.long.byte 0x0 8.--14. 1. "DLL_OBSERVABLE_LOWER_LOCK_VALUE_FLD,Reports the DLL encoder value from the master DLL to the slave DLLs." newline hexmask.long.byte 0x0 3.--7. 1. "DLL_OBSERVABLE_LOWER_UNLOCK_COUNTER_FLD,Reports the number of increments or decrements required for the master DLL to complete the locking process." newline bitfld.long 0x0 1.--2. "DLL_OBSERVABLE_LOWER_LOCK_MODE_FLD,Defines the mode in which the DLL has achieved the lock." "0,1,2,3" newline bitfld.long 0x0 0. "DLL_OBSERVABLE_LOWER_DLL_LOCK_FLD,Indicates status of DLL." "0,1" line.long 0x4 "DLL_OBSERVABLE_UPPER_REG,DLL Observable Register Upper" hexmask.long.word 0x4 23.--31. 1. "DLL_OBSERVABLE_UPPER_RESV2_FLD,Reserved" newline hexmask.long.byte 0x4 16.--22. 1. "DLL_OBSERVABLE_UPPER_TX_DECODER_OUTPUT_FLD,Holds the encoded value for the TX delay line for this slice." newline hexmask.long.word 0x4 7.--15. 1. "DLL_OBSERVABLE_UPPER_RESV1_FLD,Reserved" newline hexmask.long.byte 0x4 0.--6. 1. "DLL_OBSERVABLE__UPPER_RX_DECODER_OUTPUT_FLD,Holds the encoded value for the RX delay line for this slice." group.long 0xE0++0x7 line.long 0x0 "OPCODE_EXT_LOWER_REG,Opcode Extension Register (Lower)" hexmask.long.byte 0x0 24.--31. 1. "EXT_READ_OPCODE_FLD,Supplement byte of any Read Opcode" newline hexmask.long.byte 0x0 16.--23. 1. "EXT_WRITE_OPCODE_FLD,Supplement byte of any Write Opcode" newline hexmask.long.byte 0x0 8.--15. 1. "EXT_POLL_OPCODE_FLD,Supplement byte of any Polling Opcode" newline hexmask.long.byte 0x0 0.--7. 1. "EXT_STIG_OPCODE_FLD,Supplement byte of any STIG Opcode" line.long 0x4 "OPCODE_EXT_UPPER_REG,Opcode Extension Register (Upper)" hexmask.long.byte 0x4 24.--31. 1. "WEL_OPCODE_FLD,First byte of any WEL Opcode" newline hexmask.long.byte 0x4 16.--23. 1. "EXT_WEL_OPCODE_FLD,Supplement byte of any WEL Opcode" newline hexmask.long.word 0x4 0.--15. 1. "OPCODE_EXT_UPPER_RESV1_FLD,Reserved" group.long 0xF0++0x3 line.long 0x0 "CUSTOM_CONF_REG,Custom Configuration Register" hexmask.long 0x0 5.--31. 1. "CUSTOM_CONF_RESV_FLD2,Reserved" newline bitfld.long 0x0 4. "PIPE_SMRT_ACC_FLD,PHY POP delay functionality" "0,1" newline hexmask.long.byte 0x0 0.--3. 1. "CUSTOM_CONF_RESV_FLD1,Reserved" rgroup.long 0xFC++0x3 line.long 0x0 "MODULE_ID_REG,Module ID Register" hexmask.long.byte 0x0 24.--31. 1. "FIX_PATCH_FLD,Fix/path number related to revision described by 3 LSBs of this register" newline hexmask.long.word 0x0 8.--23. 1. "MODULE_ID_FLD,Module/Revision ID number" newline hexmask.long.byte 0x0 3.--7. 1. "MODULE_ID_RESV_FLD,Reserved" newline bitfld.long 0x0 2. "HYPER_SUPPORT_FLD,HyperFlash Support" "0,1" newline bitfld.long 0x0 0.--1. "CONF_FLD,Configuration ID number: 0 : OCTAL + PHY Configuration 1 : OCTAL Configuration 2 : QUAD + PHY Configuration 3 : QUAD Configuration" "OCTAL + PHY Configuration,OCTAL Configuration,QUAD + PHY Configuration,QUAD Configuration" group.long 0x100++0x3 line.long 0x0 "HYPERFLASH_CONFIG_REG,HyperFlash Configuration Register" rbitfld.long 0x0 31. "HYPERFLASH_CONFIG_RESV3_FLD,Reserved" "0,1" newline bitfld.long 0x0 30. "TARGET_HYPERFLASH_STIG_FLD,Identifies the target of final STIG HyperFlash transaction as follows: 1'b0 = Memory Space 1'b1 = Register Space" "Memory Space 1'b1 = Register Space,?" newline bitfld.long 0x0 29. "BURST_TYPE_HYPERFLASH_STIG_FLD,Identifies the burst type of final STIG HyperFlash transaction" "0,1" newline hexmask.long.word 0x0 20.--28. 1. "HYPERFLASH_CONFIG_RESV2_FLD,Reserved" newline hexmask.long.byte 0x0 16.--19. 1. "HYPERFLASH_LAT_CODE_FLD,Identifies the latency code for HyperFlash" newline hexmask.long.word 0x0 1.--15. 1. "HYPERFLASH_CONFIG_RESV1_FLD,Reserved" newline bitfld.long 0x0 0. "HYPERFLASH_ENABLE_FLD,HyperFlash Mode enable bit" "0,1" group.long 0x110++0x3 line.long 0x0 "OSPI_MISC0,Misc configuration Register #0" newline bitfld.long 0x0 5. "CTL3,sample clocl polarity control for sclk_dlyd_i 0x1 - Invert sample clock sclk_dlyd_i 0x0 - sample clock sclk_dlyd_i not inverted" "sample clock sclk_dlyd_i not inverted,Invert sample clock sclk_dlyd_i" newline bitfld.long 0x0 4. "CTL2,DQS pad output enable When CTL0 is set 0x2 this bit should be enable to enable loopback path from internal sclk_out to DQS pad." "0,1" newline bitfld.long 0x0 2.--3. "CTL1,SCLK output logic control. 0x0 - orginal logic without any delay (Delay added by TX DLL) 0x1 - original logic (sclk_out) with dleay 1/4 cycle of SCLK (by ref_clk_2x fall edge) 0x2 - original logic (sclk_out) with delay 1/2 cycle of SCLk (by.." "orginal logic without any delay,original logic,original logic,original logic" newline bitfld.long 0x0 0.--1. "CTL0,loopback SCLK input logic control (sclk_dlyd). 0x0 - loopback from SCLK pad 0x1 - loopback from internal (sclk_out with delay selected by OSPI_MISC0.CTL1) 0x2 - loopback from DQS pad 0x3 - loopback from ref_clk_2x (for DFT test only)." "loopback from SCLK pad,loopback from internal,loopback from DQS pad,loopback from ref_clk_2x" repeat 3. (list 0x1 0x2 0x3 )(list 0x0 0x4 0x8 ) group.long ($2+0x114)++0x3 line.long 0x0 "OSPI_MISC$1,Misc Configuration Register #1" hexmask.long 0x0 0.--31. 1. "CTL,Reserved for future" repeat.end group.long 0x200++0x3 line.long 0x0 "HYPERFLASH_STIG_CONFIG_REG,HyperFlash STIG Configuration Register" hexmask.long.byte 0x0 27.--31. 1. "HYPERFLASH_STIG_CONFIG_REG_RESV0_FLD,Reserved" newline bitfld.long 0x0 24.--26. "HYPERFLASH_STIG_CONFIG_NB_PRE_TRAN_FLD,Identifies the number of STIG HyperFlash pre-transactions" "0,1,2,3,4,5,6,7" newline hexmask.long.word 0x0 13.--23. 1. "HYPERFLASH_STIG_CONFIG_REG_RESV1_FLD,Reserved" newline bitfld.long 0x0 12. "HYPERFLASH_STIG_PRE_TRAN_DATA7_SIZE_FLD,Identifies data size of STIG HyperFlash pre-transaction 7" "0,1" newline rbitfld.long 0x0 11. "HYPERFLASH_STIG_CONFIG_REG_RESV2_FLD,Reserved" "0,1" newline bitfld.long 0x0 10. "HYPERFLASH_STIG_PRE_TRAN_DATA6_SIZE_FLD,Identifies data size of STIG HyperFlash pre-transaction 6" "0,1" newline rbitfld.long 0x0 9. "HYPERFLASH_STIG_CONFIG_REG_RESV3_FLD,Reserved" "0,1" newline bitfld.long 0x0 8. "HYPERFLASH_STIG_PRE_TRAN_DATA5_SIZE_FLD,Identifies data size of STIG HyperFlash pre-transaction 5" "0,1" newline rbitfld.long 0x0 7. "HYPERFLASH_STIG_CONFIG_REG_RESV4_FLD,Reserved" "0,1" newline bitfld.long 0x0 6. "HYPERFLASH_STIG_PRE_TRAN_DATA4_SIZE_FLD,Identifies data size of STIG HyperFlash pre-transaction 4" "0,1" newline rbitfld.long 0x0 5. "HYPERFLASH_STIG_CONFIG_REG_RESV5_FLD,Reserved" "0,1" newline bitfld.long 0x0 4. "HYPERFLASH_STIG_PRE_TRAN_DATA3_SIZE_FLD,Identifies data size of STIG HyperFlash pre-transaction 3" "0,1" newline rbitfld.long 0x0 3. "HYPERFLASH_STIG_CONFIG_REG_RESV6_FLD,Reserved" "0,1" newline bitfld.long 0x0 2. "HYPERFLASH_STIG_PRE_TRAN_DATA2_SIZE_FLD,Identifies data size of STIG HyperFlash pre-transaction 2" "0,1" newline rbitfld.long 0x0 1. "HYPERFLASH_STIG_CONFIG_REG_RESV7_FLD,Reserved" "0,1" newline bitfld.long 0x0 0. "HYPERFLASH_STIG_PRE_TRAN_DATA1_SIZE_FLD,Identifies data size of STIG HyperFlash pre-transaction 1" "0,1" group.long 0x210++0x7 line.long 0x0 "HYPERFLASH_STIG_PRE_TRAN1_ADDRESS_REG,HyperFlash STIG Pre-transaction 1 Address Register" hexmask.long 0x0 0.--31. 1. "HYPERFLASH_STIG_PRE_TRAN1_ADDRESS_FLD,Identifies Address of HyperFlash STIG Pre-transaction 1" line.long 0x4 "HYPERFLASH_STIG_PRE_TRAN1_DATA_REG,HyperFlash STIG Pre-transaction 1 Data Register" hexmask.long 0x4 0.--31. 1. "HYPERFLASH_STIG_PRE_TRAN1_DATA_FLD,Identifies Data of HyperFlash STIG Pre-transaction 1" group.long 0x220++0x7 line.long 0x0 "HYPERFLASH_STIG_PRE_TRAN2_ADDRESS_REG,HyperFlash STIG Pre-transaction 2 Address Register" hexmask.long 0x0 0.--31. 1. "HYPERFLASH_STIG_PRE_TRAN2_ADDRESS_FLD,Identifies Address of HyperFlash STIG Pre-transaction 2" line.long 0x4 "HYPERFLASH_STIG_PRE_TRAN2_DATA_REG,HyperFlash STIG Pre-transaction 2 Data Register" hexmask.long 0x4 0.--31. 1. "HYPERFLASH_STIG_PRE_TRAN2_DATA_FLD,Identifies Data of HyperFlash STIG Pre-transaction 2" group.long 0x230++0x7 line.long 0x0 "HYPERFLASH_STIG_PRE_TRAN3_ADDRESS_REG,HyperFlash STIG Pre-transaction 3 Address Register" hexmask.long 0x0 0.--31. 1. "HYPERFLASH_STIG_PRE_TRAN3_ADDRESS_FLD,Identifies Address of HyperFlash STIG Pre-transaction 3" line.long 0x4 "HYPERFLASH_STIG_PRE_TRAN3_DATA_REG,HyperFlash STIG Pre-transaction 3 Data Register" hexmask.long 0x4 0.--31. 1. "HYPERFLASH_STIG_PRE_TRAN3_DATA_FLD,Identifies Data of HyperFlash STIG Pre-transaction 3" group.long 0x240++0x7 line.long 0x0 "HYPERFLASH_STIG_PRE_TRAN4_ADDRESS_REG,HyperFlash STIG Pre-transaction 4 Address Register" hexmask.long 0x0 0.--31. 1. "HYPERFLASH_STIG_PRE_TRAN4_ADDRESS_FLD,Identifies Address of HyperFlash STIG Pre-transaction 4" line.long 0x4 "HYPERFLASH_STIG_PRE_TRAN4_DATA_REG,HyperFlash STIG Pre-transaction 4 Data Register" hexmask.long 0x4 0.--31. 1. "HYPERFLASH_STIG_PRE_TRAN4_DATA_FLD,Identifies Data of HyperFlash STIG Pre-transaction 4" group.long 0x250++0x7 line.long 0x0 "HYPERFLASH_STIG_PRE_TRAN5_ADDRESS_REG,HyperFlash STIG Pre-transaction 5 Address Register" hexmask.long 0x0 0.--31. 1. "HYPERFLASH_STIG_PRE_TRAN5_ADDRESS_FLD,Identifies Address of HyperFlash STIG Pre-transaction 5" line.long 0x4 "HYPERFLASH_STIG_PRE_TRAN5_DATA_REG,HyperFlash STIG Pre-transaction 5 Data Register" hexmask.long 0x4 0.--31. 1. "HYPERFLASH_STIG_PRE_TRAN5_DATA_FLD,Identifies Data of HyperFlash STIG Pre-transaction 5" group.long 0x260++0x7 line.long 0x0 "HYPERFLASH_STIG_PRE_TRAN6_ADDRESS_REG,HyperFlash STIG Pre-transaction 6 Address Register" hexmask.long 0x0 0.--31. 1. "HYPERFLASH_STIG_PRE_TRAN6_ADDRESS_FLD,Identifies Address of HyperFlash STIG Pre-transaction 6" line.long 0x4 "HYPERFLASH_STIG_PRE_TRAN6_DATA_REG,HyperFlash STIG Pre-transaction 6 Data Register" hexmask.long 0x4 0.--31. 1. "HYPERFLASH_STIG_PRE_TRAN6_DATA_FLD,Identifies Data of HyperFlash STIG Pre-transaction 6" group.long 0x270++0x7 line.long 0x0 "HYPERFLASH_STIG_PRE_TRAN7_ADDRESS_REG,HyperFlash STIG Pre-transaction 7 Address Register" hexmask.long 0x0 0.--31. 1. "HYPERFLASH_STIG_PRE_TRAN7_ADDRESS_FLD,Identifies Address of HyperFlash STIG Pre-transaction 7" line.long 0x4 "HYPERFLASH_STIG_PRE_TRAN7_DATA_REG,HyperFlash STIG Pre-transaction 7 Data Register" hexmask.long 0x4 0.--31. 1. "HYPERFLASH_STIG_PRE_TRAN7_DATA_FLD,Identifies Data of HyperFlash STIG Pre-transaction 7" group.long 0x300++0x3 line.long 0x0 "HYPERFLASH_WRITE_CONFIG_REG,HyperFlash Write Configuration Register" hexmask.long.byte 0x0 27.--31. 1. "HYPERFLASH_WRITE_CONFIG_REG_RESV0_FLD,Reserved" newline bitfld.long 0x0 24.--26. "HYPERFLASH_WRITE_CONFIG_NB_PRE_TRAN_FLD,Identifies the number of Write HyperFlash pre-transactions" "0,1,2,3,4,5,6,7" newline hexmask.long.word 0x0 13.--23. 1. "HYPERFLASH_WRITE_CONFIG_REG_RESV1_FLD,Reserved" newline bitfld.long 0x0 12. "HYPERFLASH_WRITE_PRE_TRAN_DATA7_SIZE_FLD,Identifies data size of Write HyperFlash pre-transaction 7" "0,1" newline rbitfld.long 0x0 11. "HYPERFLASH_WRITE_CONFIG_REG_RESV2_FLD,Reserved" "0,1" newline bitfld.long 0x0 10. "HYPERFLASH_WRITE_PRE_TRAN_DATA6_SIZE_FLD,Identifies data size of Write HyperFlash pre-transaction 6" "0,1" newline rbitfld.long 0x0 9. "HYPERFLASH_WRITE_CONFIG_REG_RESV3_FLD,Reserved" "0,1" newline bitfld.long 0x0 8. "HYPERFLASH_WRITE_PRE_TRAN_DATA5_SIZE_FLD,Identifies data size of Write HyperFlash pre-transaction 5" "0,1" newline rbitfld.long 0x0 7. "HYPERFLASH_WRITE_CONFIG_REG_RESV4_FLD,Reserved" "0,1" newline bitfld.long 0x0 6. "HYPERFLASH_WRITE_PRE_TRAN_DATA4_SIZE_FLD,Identifies data size of Write HyperFlash pre-transaction 4" "0,1" newline rbitfld.long 0x0 5. "HYPERFLASH_WRITE_CONFIG_REG_RESV5_FLD,Reserved" "0,1" newline bitfld.long 0x0 4. "HYPERFLASH_WRITE_PRE_TRAN_DATA3_SIZE_FLD,Identifies data size of Write HyperFlash pre-transaction 3" "0,1" newline rbitfld.long 0x0 3. "HYPERFLASH_WRITE_CONFIG_REG_RESV6_FLD,Reserved" "0,1" newline bitfld.long 0x0 2. "HYPERFLASH_WRITE_PRE_TRAN_DATA2_SIZE_FLD,Identifies data size of Write HyperFlash pre-transaction 2" "0,1" newline rbitfld.long 0x0 1. "HYPERFLASH_WRITE_CONFIG_REG_RESV7_FLD,Reserved" "0,1" newline bitfld.long 0x0 0. "HYPERFLASH_WRITE_PRE_TRAN_DATA1_SIZE_FLD,Identifies data size of Write HyperFlash pre-transaction 1" "0,1" group.long 0x310++0x7 line.long 0x0 "HYPERFLASH_WRITE_PRE_TRAN1_ADDRESS_REG,HyperFlash Write Pre-transaction 1 Address Register" hexmask.long 0x0 0.--31. 1. "HYPERFLASH_WRITE_PRE_TRAN1_ADDRESS_FLD,Identifies Address of HyperFlash Write Pre-transaction 1" line.long 0x4 "HYPERFLASH_WRITE_PRE_TRAN1_DATA_REG,HyperFlash Write Pre-transaction 1 Data Register" hexmask.long 0x4 0.--31. 1. "HYPERFLASH_WRITE_PRE_TRAN1_DATA_FLD,Identifies Data of HyperFlash Write Pre-transaction 1" group.long 0x320++0x7 line.long 0x0 "HYPERFLASH_WRITE_PRE_TRAN2_ADDRESS_REG,HyperFlash Write Pre-transaction 2 Address Register" hexmask.long 0x0 0.--31. 1. "HYPERFLASH_WRITE_PRE_TRAN2_ADDRESS_FLD,Identifies Address of HyperFlash Write Pre-transaction 2" line.long 0x4 "HYPERFLASH_WRITE_PRE_TRAN2_DATA_REG,HyperFlash Write Pre-transaction 2 Data Register" hexmask.long 0x4 0.--31. 1. "HYPERFLASH_WRITE_PRE_TRAN2_DATA_FLD,Identifies Data of HyperFlash Write Pre-transaction 2" group.long 0x330++0x7 line.long 0x0 "HYPERFLASH_WRITE_PRE_TRAN3_ADDRESS_REG,HyperFlash Write Pre-transaction 3 Address Register" hexmask.long 0x0 0.--31. 1. "HYPERFLASH_WRITE_PRE_TRAN3_ADDRESS_FLD,Identifies Address of HyperFlash Write Pre-transaction 3" line.long 0x4 "HYPERFLASH_WRITE_PRE_TRAN3_DATA_REG,HyperFlash Write Pre-transaction 3 Data Register" hexmask.long 0x4 0.--31. 1. "HYPERFLASH_WRITE_PRE_TRAN3_DATA_FLD,Identifies Data of HyperFlash Write Pre-transaction 3" group.long 0x340++0x7 line.long 0x0 "HYPERFLASH_WRITE_PRE_TRAN4_ADDRESS_REG,HyperFlash Write Pre-transaction 4 Address Register" hexmask.long 0x0 0.--31. 1. "HYPERFLASH_WRITE_PRE_TRAN4_ADDRESS_FLD,Identifies Address of HyperFlash Write Pre-transaction 4" line.long 0x4 "HYPERFLASH_WRITE_PRE_TRAN4_DATA_REG,HyperFlash Write Pre-transaction 4 Data Register" hexmask.long 0x4 0.--31. 1. "HYPERFLASH_WRITE_PRE_TRAN4_DATA_FLD,Identifies Data of HyperFlash Write Pre-transaction 4" group.long 0x350++0x7 line.long 0x0 "HYPERFLASH_WRITE_PRE_TRAN5_ADDRESS_REG,HyperFlash Write Pre-transaction 5 Address Register" hexmask.long 0x0 0.--31. 1. "HYPERFLASH_WRITE_PRE_TRAN5_ADDRESS_FLD,Identifies Address of HyperFlash Write Pre-transaction 5" line.long 0x4 "HYPERFLASH_WRITE_PRE_TRAN5_DATA_REG,HyperFlash Write Pre-transaction 5 Data Register" hexmask.long 0x4 0.--31. 1. "HYPERFLASH_WRITE_PRE_TRAN5_DATA_FLD,Identifies Data of HyperFlash Write Pre-transaction 5" group.long 0x360++0x7 line.long 0x0 "HYPERFLASH_WRITE_PRE_TRAN6_ADDRESS_REG,HyperFlash Write Pre-transaction 6 Address Register" hexmask.long 0x0 0.--31. 1. "HYPERFLASH_WRITE_PRE_TRAN6_ADDRESS_FLD,Identifies Address of HyperFlash Write Pre-transaction 6" line.long 0x4 "HYPERFLASH_WRITE_PRE_TRAN6_DATA_REG,HyperFlash Write Pre-transaction 6 Data Register" hexmask.long 0x4 0.--31. 1. "HYPERFLASH_WRITE_PRE_TRAN6_DATA_FLD,Identifies Data of HyperFlash Write Pre-transaction 6" group.long 0x370++0x7 line.long 0x0 "HYPERFLASH_WRITE_PRE_TRAN7_ADDRESS_REG,HyperFlash Write Pre-transaction 7 Address Register" hexmask.long 0x0 0.--31. 1. "HYPERFLASH_WRITE_PRE_TRAN7_ADDRESS_FLD,Identifies Address of HyperFlash Write Pre-transaction 7" line.long 0x4 "HYPERFLASH_WRITE_PRE_TRAN7_DATA_REG,HyperFlash Write Pre-transaction 7 Data Register" hexmask.long 0x4 0.--31. 1. "HYPERFLASH_WRITE_PRE_TRAN7_DATA_FLD,Identifies Data of HyperFlash Write Pre-transaction 7" group.long 0x400++0x3 line.long 0x0 "HYPERFLASH_READ_CONFIG_REG,HyperFlash Read Configuration Register" hexmask.long.byte 0x0 27.--31. 1. "HYPERFLASH_READ_CONFIG_REG_RESV0_FLD,Reserved" newline bitfld.long 0x0 24.--26. "HYPERFLASH_READ_CONFIG_NB_PRE_TRAN_FLD,Identifies the number of Read HyperFlash pre-transactions" "0,1,2,3,4,5,6,7" newline hexmask.long.word 0x0 13.--23. 1. "HYPERFLASH_READ_CONFIG_REG_RESV1_FLD,Reserved" newline bitfld.long 0x0 12. "HYPERFLASH_READ_PRE_TRAN_DATA7_SIZE_FLD,Identifies data size of Read HyperFlash pre-transaction 7" "0,1" newline rbitfld.long 0x0 11. "HYPERFLASH_READ_CONFIG_REG_RESV2_FLD,Reserved" "0,1" newline bitfld.long 0x0 10. "HYPERFLASH_READ_PRE_TRAN_DATA6_SIZE_FLD,Identifies data size of Read HyperFlash pre-transaction 6" "0,1" newline rbitfld.long 0x0 9. "HYPERFLASH_READ_CONFIG_REG_RESV3_FLD,Reserved" "0,1" newline bitfld.long 0x0 8. "HYPERFLASH_READ_PRE_TRAN_DATA5_SIZE_FLD,Identifies data size of Read HyperFlash pre-transaction 5" "0,1" newline rbitfld.long 0x0 7. "HYPERFLASH_READ_CONFIG_REG_RESV4_FLD,Reserved" "0,1" newline bitfld.long 0x0 6. "HYPERFLASH_READ_PRE_TRAN_DATA4_SIZE_FLD,Identifies data size of Read HyperFlash pre-transaction 4" "0,1" newline rbitfld.long 0x0 5. "HYPERFLASH_READ_CONFIG_REG_RESV5_FLD,Reserved" "0,1" newline bitfld.long 0x0 4. "HYPERFLASH_READ_PRE_TRAN_DATA3_SIZE_FLD,Identifies data size of Read HyperFlash pre-transaction 3" "0,1" newline rbitfld.long 0x0 3. "HYPERFLASH_READ_CONFIG_REG_RESV6_FLD,Reserved" "0,1" newline bitfld.long 0x0 2. "HYPERFLASH_READ_PRE_TRAN_DATA2_SIZE_FLD,Identifies data size of Read HyperFlash pre-transaction 2" "0,1" newline rbitfld.long 0x0 1. "HYPERFLASH_READ_CONFIG_REG_RESV7_FLD,Reserved" "0,1" newline bitfld.long 0x0 0. "HYPERFLASH_READ_PRE_TRAN_DATA1_SIZE_FLD,Identifies data size of Read HyperFlash pre-transaction 1" "0,1" group.long 0x410++0x7 line.long 0x0 "HYPERFLASH_READ_PRE_TRAN1_ADDRESS_REG,HyperFlash Read Pre-transaction 1 Address Register" hexmask.long 0x0 0.--31. 1. "HYPERFLASH_READ_PRE_TRAN1_ADDRESS_FLD,Identifies Address of HyperFlash Read Pre-transaction 1" line.long 0x4 "HYPERFLASH_READ_PRE_TRAN1_DATA_REG,HyperFlash Read Pre-transaction 1 Data Register" hexmask.long 0x4 0.--31. 1. "HYPERFLASH_READ_PRE_TRAN1_DATA_FLD,Identifies Data of HyperFlash Read Pre-transaction 1" group.long 0x420++0x7 line.long 0x0 "HYPERFLASH_READ_PRE_TRAN2_ADDRESS_REG,HyperFlash Read Pre-transaction 2 Address Register" hexmask.long 0x0 0.--31. 1. "HYPERFLASH_READ_PRE_TRAN2_ADDRESS_FLD,Identifies Address of HyperFlash Read Pre-transaction 2" line.long 0x4 "HYPERFLASH_READ_PRE_TRAN2_DATA_REG,HyperFlash Read Pre-transaction 2 Data Register" hexmask.long 0x4 0.--31. 1. "HYPERFLASH_READ_PRE_TRAN2_DATA_FLD,Identifies Data of HyperFlash Read Pre-transaction 2" group.long 0x430++0x7 line.long 0x0 "HYPERFLASH_READ_PRE_TRAN3_ADDRESS_REG,HyperFlash Read Pre-transaction 3 Address Register" hexmask.long 0x0 0.--31. 1. "HYPERFLASH_READ_PRE_TRAN3_ADDRESS_FLD,Identifies Address of HyperFlash Read Pre-transaction 3" line.long 0x4 "HYPERFLASH_READ_PRE_TRAN3_DATA_REG,HyperFlash Read Pre-transaction 3 Data Register" hexmask.long 0x4 0.--31. 1. "HYPERFLASH_READ_PRE_TRAN3_DATA_FLD,Identifies Data of HyperFlash Read Pre-transaction 3" group.long 0x440++0x7 line.long 0x0 "HYPERFLASH_READ_PRE_TRAN4_ADDRESS_REG,HyperFlash Read Pre-transaction 4 Address Register" hexmask.long 0x0 0.--31. 1. "HYPERFLASH_READ_PRE_TRAN4_ADDRESS_FLD,Identifies Address of HyperFlash Read Pre-transaction 4" line.long 0x4 "HYPERFLASH_READ_PRE_TRAN4_DATA_REG,HyperFlash Read Pre-transaction 4 Data Register" hexmask.long 0x4 0.--31. 1. "HYPERFLASH_READ_PRE_TRAN4_DATA_FLD,Identifies Data of HyperFlash Read Pre-transaction 4" group.long 0x450++0x7 line.long 0x0 "HYPERFLASH_READ_PRE_TRAN5_ADDRESS_REG,HyperFlash Read Pre-transaction 5 Address Register" hexmask.long 0x0 0.--31. 1. "HYPERFLASH_READ_PRE_TRAN5_ADDRESS_FLD,Identifies Address of HyperFlash Read Pre-transaction 5" line.long 0x4 "HYPERFLASH_READ_PRE_TRAN5_DATA_REG,HyperFlash Read Pre-transaction 5 Data Register" hexmask.long 0x4 0.--31. 1. "HYPERFLASH_READ_PRE_TRAN5_DATA_FLD,Identifies Data of HyperFlash Read Pre-transaction 5" group.long 0x460++0x7 line.long 0x0 "HYPERFLASH_READ_PRE_TRAN6_ADDRESS_REG,HyperFlash Read Pre-transaction 6 Address Register" hexmask.long 0x0 0.--31. 1. "HYPERFLASH_READ_PRE_TRAN6_ADDRESS_FLD,Identifies Address of HyperFlash Read Pre-transaction 6" line.long 0x4 "HYPERFLASH_READ_PRE_TRAN6_DATA_REG,HyperFlash Read Pre-transaction 6 Data Register" hexmask.long 0x4 0.--31. 1. "HYPERFLASH_READ_PRE_TRAN6_DATA_FLD,Identifies Data of HyperFlash Read Pre-transaction 6" group.long 0x470++0x7 line.long 0x0 "HYPERFLASH_READ_PRE_TRAN7_ADDRESS_REG,HyperFlash Read Pre-transaction 7 Address Register" hexmask.long 0x0 0.--31. 1. "HYPERFLASH_READ_PRE_TRAN7_ADDRESS_FLD,Identifies Address of HyperFlash Read Pre-transaction 7" line.long 0x4 "HYPERFLASH_READ_PRE_TRAN7_DATA_REG,HyperFlash Read Pre-transaction 7 Data Register" hexmask.long 0x4 0.--31. 1. "HYPERFLASH_READ_PRE_TRAN7_DATA_FLD,Identifies Data of HyperFlash Read Pre-transaction 7" group.long 0x500++0x3 line.long 0x0 "HYPERFLASH_POLLING_CONFIG_REG,HyperFlash Polling Configuration Register" hexmask.long.byte 0x0 27.--31. 1. "HYPERFLASH_POLLING_CONFIG_REG_RESV0_FLD,Reserved" newline bitfld.long 0x0 24.--26. "HYPERFLASH_POLLING_CONFIG_NB_PRE_TRAN_FLD,Identifies the number of Polling HyperFlash pre-transactions" "0,1,2,3,4,5,6,7" newline hexmask.long.word 0x0 13.--23. 1. "HYPERFLASH_POLLING_CONFIG_REG_RESV1_FLD,Reserved" newline bitfld.long 0x0 12. "HYPERFLASH_POLLING_PRE_TRAN_DATA7_SIZE_FLD,Identifies data size of Polling HyperFlash pre-transaction 7" "0,1" newline rbitfld.long 0x0 11. "HYPERFLASH_POLLING_CONFIG_REG_RESV2_FLD,Reserved" "0,1" newline bitfld.long 0x0 10. "HYPERFLASH_POLLING_PRE_TRAN_DATA6_SIZE_FLD,Identifies data size of Polling HyperFlash pre-transaction 6" "0,1" newline rbitfld.long 0x0 9. "HYPERFLASH_POLLING_CONFIG_REG_RESV3_FLD,Reserved" "0,1" newline bitfld.long 0x0 8. "HYPERFLASH_POLLING_PRE_TRAN_DATA5_SIZE_FLD,Identifies data size of Polling HyperFlash pre-transaction 5" "0,1" newline rbitfld.long 0x0 7. "HYPERFLASH_POLLING_CONFIG_REG_RESV4_FLD,Reserved" "0,1" newline bitfld.long 0x0 6. "HYPERFLASH_POLLING_PRE_TRAN_DATA4_SIZE_FLD,Identifies data size of Polling HyperFlash pre-transaction 4" "0,1" newline rbitfld.long 0x0 5. "HYPERFLASH_POLLING_CONFIG_REG_RESV5_FLD,Reserved" "0,1" newline bitfld.long 0x0 4. "HYPERFLASH_POLLING_PRE_TRAN_DATA3_SIZE_FLD,Identifies data size of Polling HyperFlash pre-transaction 3" "0,1" newline rbitfld.long 0x0 3. "HYPERFLASH_POLLING_CONFIG_REG_RESV6_FLD,Reserved" "0,1" newline bitfld.long 0x0 2. "HYPERFLASH_POLLING_PRE_TRAN_DATA2_SIZE_FLD,Identifies data size of Polling HyperFlash pre-transaction 2" "0,1" newline rbitfld.long 0x0 1. "HYPERFLASH_POLLING_CONFIG_REG_RESV7_FLD,Reserved" "0,1" newline bitfld.long 0x0 0. "HYPERFLASH_POLLING_PRE_TRAN_DATA1_SIZE_FLD,Identifies data size of Polling HyperFlash pre-transaction 1" "0,1" group.long 0x510++0x7 line.long 0x0 "HYPERFLASH_POLLING_PRE_TRAN1_ADDRESS_REG,HyperFlash Polling Pre-transaction 1 Address Register" hexmask.long 0x0 0.--31. 1. "HYPERFLASH_POLLING_PRE_TRAN1_ADDRESS_FLD,Identifies Address of HyperFlash Polling Pre-transaction 1" line.long 0x4 "HYPERFLASH_POLLING_PRE_TRAN1_DATA_REG,HyperFlash Polling Pre-transaction 1 Data Register" hexmask.long 0x4 0.--31. 1. "HYPERFLASH_POLLING_PRE_TRAN1_DATA_FLD,Identifies Data of HyperFlash Polling Pre-transaction 1" group.long 0x520++0x7 line.long 0x0 "HYPERFLASH_POLLING_PRE_TRAN2_ADDRESS_REG,HyperFlash Polling Pre-transaction 2 Address Register" hexmask.long 0x0 0.--31. 1. "HYPERFLASH_POLLING_PRE_TRAN2_ADDRESS_FLD,Identifies Address of HyperFlash Polling Pre-transaction 2" line.long 0x4 "HYPERFLASH_POLLING_PRE_TRAN2_DATA_REG,HyperFlash Polling Pre-transaction 2 Data Register" hexmask.long 0x4 0.--31. 1. "HYPERFLASH_POLLING_PRE_TRAN2_DATA_FLD,Identifies Data of HyperFlash Polling Pre-transaction 2" group.long 0x530++0x7 line.long 0x0 "HYPERFLASH_POLLING_PRE_TRAN3_ADDRESS_REG,HyperFlash Polling Pre-transaction 3 Address Register" hexmask.long 0x0 0.--31. 1. "HYPERFLASH_POLLING_PRE_TRAN3_ADDRESS_FLD,Identifies Address of HyperFlash Polling Pre-transaction 3" line.long 0x4 "HYPERFLASH_POLLING_PRE_TRAN3_DATA_REG,HyperFlash Polling Pre-transaction 3 Data Register" hexmask.long 0x4 0.--31. 1. "HYPERFLASH_POLLING_PRE_TRAN3_DATA_FLD,Identifies Data of HyperFlash Polling Pre-transaction 3" group.long 0x540++0x7 line.long 0x0 "HYPERFLASH_POLLING_PRE_TRAN4_ADDRESS_REG,HyperFlash Polling Pre-transaction 4 Address Register" hexmask.long 0x0 0.--31. 1. "HYPERFLASH_POLLING_PRE_TRAN4_ADDRESS_FLD,Identifies Address of HyperFlash Polling Pre-transaction 4" line.long 0x4 "HYPERFLASH_POLLING_PRE_TRAN4_DATA_REG,HyperFlash Polling Pre-transaction 4 Data Register" hexmask.long 0x4 0.--31. 1. "HYPERFLASH_POLLING_PRE_TRAN4_DATA_FLD,Identifies Data of HyperFlash Polling Pre-transaction 4" group.long 0x550++0x7 line.long 0x0 "HYPERFLASH_POLLING_PRE_TRAN5_ADDRESS_REG,HyperFlash Polling Pre-transaction 5 Address Register" hexmask.long 0x0 0.--31. 1. "HYPERFLASH_POLLING_PRE_TRAN5_ADDRESS_FLD,Identifies Address of HyperFlash Polling Pre-transaction 5" line.long 0x4 "HYPERFLASH_POLLING_PRE_TRAN5_DATA_REG,HyperFlash Polling Pre-transaction 5 Data Register" hexmask.long 0x4 0.--31. 1. "HYPERFLASH_POLLING_PRE_TRAN5_DATA_FLD,Identifies Data of HyperFlash Polling Pre-transaction 5" group.long 0x560++0x7 line.long 0x0 "HYPERFLASH_POLLING_PRE_TRAN6_ADDRESS_REG,HyperFlash Polling Pre-transaction 6 Address Register" hexmask.long 0x0 0.--31. 1. "HYPERFLASH_POLLING_PRE_TRAN6_ADDRESS_FLD,Identifies Address of HyperFlash Polling Pre-transaction 6" line.long 0x4 "HYPERFLASH_POLLING_PRE_TRAN6_DATA_REG,HyperFlash Polling Pre-transaction 6 Data Register" hexmask.long 0x4 0.--31. 1. "HYPERFLASH_POLLING_PRE_TRAN6_DATA_FLD,Identifies Data of HyperFlash Polling Pre-transaction 6" group.long 0x570++0x7 line.long 0x0 "HYPERFLASH_POLLING_PRE_TRAN7_ADDRESS_REG,HyperFlash Polling Pre-transaction 7 Address Register" hexmask.long 0x0 0.--31. 1. "HYPERFLASH_POLLING_PRE_TRAN7_ADDRESS_FLD,Identifies Address of HyperFlash Polling Pre-transaction 7" line.long 0x4 "HYPERFLASH_POLLING_PRE_TRAN7_DATA_REG,HyperFlash Polling Pre-transaction 7 Data Register" hexmask.long 0x4 0.--31. 1. "HYPERFLASH_POLLING_PRE_TRAN7_DATA_FLD,Identifies Data of HyperFlash Polling Pre-transaction 7" group.long 0xA00++0x13 line.long 0x0 "ASF_INT_STATUS_REG,ASF Interrupt Status Register" hexmask.long 0x0 7.--31. 1. "ASF_INT_STATUS_RESV1_FLD,Reserved" newline bitfld.long 0x0 6. "ASF_INTEGRITY_ERR_FLD,Integrity error interrupt" "0,1" newline bitfld.long 0x0 5. "ASF_PROTOCOL_ERR_FLD,Protocol error interrupt" "0,1" newline bitfld.long 0x0 4. "ASF_TRANS_TO_ERR_FLD,Transaction timeouts interrupt" "0,1" newline bitfld.long 0x0 3. "ASF_CSR_ERR_FLD,Configuration and status registers error interrupt" "0,1" newline bitfld.long 0x0 2. "ASF_DAP_ERR_FLD,Data and address paths error interrupt" "0,1" newline bitfld.long 0x0 1. "ASF_SRAM_UNCORR_ERR_FLD,SRAM uncorrectable error interrupt" "0,1" newline bitfld.long 0x0 0. "ASF_SRAM_CORR_ERR_FLD,SRAM correctable error interrupt" "0,1" line.long 0x4 "ASF_INT_RAW_STATUS_REG,ASF Interrupt Raw Status Register" hexmask.long 0x4 7.--31. 1. "ASF_INT_RAW_STATUS_RESV1_FLD,Reserved" newline bitfld.long 0x4 6. "ASF_INTEGRITY_ERR_FLD,Integrity error interrupt" "0,1" newline bitfld.long 0x4 5. "ASF_PROTOCOL_ERR_FLD,Protocol error interrupt" "0,1" newline bitfld.long 0x4 4. "ASF_TRANS_TO_ERR_FLD,Transaction timeouts interrupt" "0,1" newline bitfld.long 0x4 3. "ASF_CSR_ERR_FLD,Configuration and status registers error interrupt" "0,1" newline bitfld.long 0x4 2. "ASF_DAP_ERR_FLD,Data and address paths error interrupt" "0,1" newline bitfld.long 0x4 1. "ASF_SRAM_UNCORR_ERR_FLD,SRAM uncorrectable error interrupt" "0,1" newline bitfld.long 0x4 0. "ASF_SRAM_CORR_ERR_FLD,SRAM correctable error interrupt" "0,1" line.long 0x8 "ASF_INT_MASK_REG,The ASF interrupt mask register indicating which interrupt bits in the ASF Interrupt Status Register are masked" hexmask.long 0x8 7.--31. 1. "ASF_INT_MASK_RESV1_FLD,Reserved" newline bitfld.long 0x8 6. "ASF_INTEGRITY_ERR_MASK_FLD,Mask bit for integrity error interrupt" "0,1" newline bitfld.long 0x8 5. "ASF_PROTOCOL_ERR_MASK_FLD,Mask bit for protocol error interrupt" "0,1" newline bitfld.long 0x8 4. "ASF_TRANS_TO_ERR_MASK_FLD,Mask bit for transaction timeouts interrupt" "0,1" newline bitfld.long 0x8 3. "ASF_CSR_ERR_MASK_FLD,Mask bit for configuration and status registers error interrupt" "0,1" newline bitfld.long 0x8 2. "ASF_DAP_ERR_MASK_FLD,Mask bit for data and address paths error interrupt" "0,1" newline bitfld.long 0x8 1. "ASF_SRAM_UNCORR_ERR_MASK_FLD,Mask bit for SRAM uncorrectable error interrupt" "0,1" newline bitfld.long 0x8 0. "ASF_SRAM_CORR_ERR_MASK_FLD,Mask bit for SRAM correctable error interrupt" "0,1" line.long 0xC "ASF_INT_TEST_REG,The ASF interrupt test register emulate hardware even" hexmask.long 0xC 7.--31. 1. "ASF_INT_TEST_RESV1_FLD,Reserved" newline bitfld.long 0xC 6. "ASF_INTEGRITY_ERR_TEST_FLD,Test bit for integrity error interrupt" "0,1" newline bitfld.long 0xC 5. "ASF_PROTOCOL_ERR_TEST_FLD,Test bit for protocol error interrupt" "0,1" newline bitfld.long 0xC 4. "ASF_TRANS_TO_ERR_TEST_FLD,Test bit for transaction timeouts interrupt" "0,1" newline bitfld.long 0xC 3. "ASF_CSR_ERR_TEST_FLD,Test bit for configuration and status registers error interrupt" "0,1" newline bitfld.long 0xC 2. "ASF_DAP_ERR_TEST_FLD,Test bit for data and address paths error interrupt" "0,1" newline bitfld.long 0xC 1. "ASF_SRAM_UNCORR_ERR_TEST_FLD,Test bit form SRAM uncorrectable error interrupt" "0,1" newline bitfld.long 0xC 0. "ASF_SRAM_CORR_ERR_TEST_FLD,Test bit for SRAM correctable error interupt" "0,1" line.long 0x10 "ASF_FATAL_NONFATAL_SELECT_REG,The fatal or non-fatal interrupt registers selects whether a fatal or non-fatal interrupt is triggered." hexmask.long 0x10 7.--31. 1. "ASF_FATAL_NONFATAL_SELECT_RESV1_FLD,Reserved" newline bitfld.long 0x10 6. "ASF_INTEGRITY_ERR_SEL_FLD,Enable integrity interrupt as fatal" "0,1" newline bitfld.long 0x10 5. "ASF_PROTOCOL_ERR_SEL_FLD,Enable protocol interrupt as fatal" "0,1" newline bitfld.long 0x10 4. "ASF_TRANS_TO_ERR_SEL_FLD,Enable transaction timeouts interrupt as fatal" "0,1" newline bitfld.long 0x10 3. "ASF_CSR_ERR_SEL_FLD,Enable configuration and status registers interrupts as fatal" "0,1" newline bitfld.long 0x10 2. "ASF_DAP_ERR_SEL_FLD,Enable data and address paths interrupt as fatal" "0,1" newline bitfld.long 0x10 1. "ASF_SRAM_UNCORR_ERR_SEL_FLD,Enable SRAM uncorrectable interrupt as fatal" "0,1" newline bitfld.long 0x10 0. "ASF_SRAM_CORR_ERR_SEL_FLD,Enable SRAM correctable interrupt as fatal" "0,1" rgroup.long 0xA20++0x7 line.long 0x0 "ASF_SRAM_CORR_FAULT_STATUS_REG,Status register for SRAM correctable fault' field{ desc = 'Last SRAM address that generated fault" line.long 0x4 "ASF_SRAM_UNCORR_FAULT_STATUS_REG,Status register for SRAM uncorrectable fault" hexmask.long.word 0x4 16.--31. 1. "ASF_SRAM_UNCORR_FAULT_STATUS_RESV1_FLD,Reserved" newline hexmask.long.word 0x4 0.--15. 1. "ASF_SRAM_UNCORR_FAULT_ADDR_FLD,Last SRAM address that generated" group.long 0xA28++0x3 line.long 0x0 "ASF_SRAM_FAULT_STATS_REG,Statics register for SRAM faults" hexmask.long.word 0x0 16.--31. 1. "ASF_SRAM_FAULT_UNCORR_STATS_FLS,Count of number of uncorrectable errors" newline hexmask.long.word 0x0 0.--15. 1. "ASF_SRAM_FAULT_CORR_STATS_FLD,Count of number of correctable errors" group.long 0xA30++0xB line.long 0x0 "ASF_TRANS_TO_CTRL_REG,Control register to configure the ASF transaction timeout monitors" bitfld.long 0x0 31. "ASF_TRANS_TO_EN_FLD,Enable transaction timeout monitoring" "0,1" newline hexmask.long.word 0x0 16.--30. 1. "ASF_TRANS_TO_CTRL_RESV1_FLD,Reserved" newline hexmask.long.word 0x0 0.--15. 1. "ASF_TRANS_TO_CTRL_FLD,Time value to use for transaction timeout monitor" line.long 0x4 "ASF_TRANS_TO_FAULT_MASK_REG,Control Register to mask out ASF transaction timeout faults from triggering interrupts" hexmask.long 0x4 1.--31. 1. "ASF_TRANS_TO_FAULT_STATUS_RESV1_FLD,Reserved" newline bitfld.long 0x4 0. "ASF_TRANS_TO_FAULT_MASK_FLD,Mask for AHB ASF transaction timeout fault source" "0,1" line.long 0x8 "ASF_TRANS_TO_FAULT_STATUS_REG,Status register for transaction timeouts fault" hexmask.long 0x8 1.--31. 1. "ASF_TRANS_TO_FAULT_STATUS_RESV1_FLD,Reserved" newline bitfld.long 0x8 0. "ASF_TRANS,Status bit for transaction timeouts faults" "0,1" group.long 0xA40++0x7 line.long 0x0 "ASF_PROTOCOL_FAULT_MASK_REG,Control register to mask out ASF Protocol faults from triggering interrupts" hexmask.long.word 0x0 19.--31. 1. "ASF_PROTOCOL_FAULT_MASK_RESV2_FLD,Reserved" newline bitfld.long 0x0 18. "ASF_PROTOCOL_FAULT_MASK_FLASH_CFG_FLD,Mask bit for Tri state enable fault" "0,1" newline bitfld.long 0x0 17. "ASF_PROTOCOL_FAULD_MASK_CS_FLD,Mask bit for Tri state enable fault" "0,1" newline bitfld.long 0x0 16. "ASF_PROTOCOL_FAULT_MASK_TRI_FLD,Mask bit for Tri state enable fault" "0,1" newline hexmask.long.word 0x0 4.--15. 1. "ASF_PROTOCOL_FAULT_MASK_RESV1_FLD,Reserved" newline bitfld.long 0x0 3. "ASF_PROTOCOL_FAULT_MASK_ECC_FLD,Mask bit for ECC failure" "0,1" newline bitfld.long 0x0 2. "ASF_PROTOCOL_MASK_TX_CRC_FLD,Mask bit for Polling expiration error" "0,1" newline bitfld.long 0x0 1. "ASF_PROTOCOL_FAULT_MASK_RX_CRC_FLD,Mask bit for Polling expiration error" "0,1" newline bitfld.long 0x0 0. "ASF_PROTOCOL_FAULT_MASK_POLL_FLD,Mask bit for Polling expiration error" "0,1" line.long 0x4 "ASF_PROTOCOL_FAULT_STATUS_REG,Status register for protocol faults" hexmask.long.word 0x4 19.--31. 1. "ASF_PROTOCOL_FAULT_STATUS_RESV2_FLD,Reserved" newline bitfld.long 0x4 18. "ASF_PROTOCOL_FAULT_STATUS_FLASH_CFG_FLD,Flash Configuration failure" "0,1" newline bitfld.long 0x4 17. "ASF_PROTOCOL_FAULT_STATUS_CS_FLD,#CS fault" "0,1" newline bitfld.long 0x4 16. "ASF_PROTOCOL_FAULT_STATUS_TRI_FLD,Tri state enable fault" "0,1" newline hexmask.long.word 0x4 4.--15. 1. "ASF_PROTOCOL_FAULT_STATUS_RESV1_FLD,Reserved" newline bitfld.long 0x4 3. "ASF_PROTOCOL_FAULT_STATUS_ECC,ECC failure" "0,1" newline bitfld.long 0x4 2. "ASF_PROTOCOL_FAULT_STATUS_TX_CRC,TX CRC chunk was broken" "0,1" newline bitfld.long 0x4 1. "ASF_PROTOCOL_FAULT_STATUS_RX_CRC_FLD,RX CRC data error" "0,1" newline bitfld.long 0x4 0. "ASF_PROTOCOL_FAULT_STATUS_POLL_FLD,Polling expiration error" "0,1" tree.end endif tree.end tree "PCIE1 (PCI Express 1)" sif (CORENAME()=="CORTEXR5F") tree "PCIE1_PF0" base ad:0xF1000000 tree "PF0_TYPE1_HDR (PCI-Compatible Configuration Space Header Type1)" group.long 0x0++0x2F line.long 0x0 "TYPE1_DEV_ID_VEND_ID_REG,Device ID and Vendor ID Register." hexmask.long.word 0x0 16.--31. 1. "DEVICE_ID,Device ID. The Device ID register identifies the particular Function. This identifier is allocated by the vendor. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else.." newline hexmask.long.word 0x0 0.--15. 1. "VENDOR_ID,Vendor ID. The Vendor ID register identifies the manufacturer of the Function. Valid vendor identifiers are allocated by the PCI-SIG to ensure uniqueness. It is not permitted to populate this register with a value of FFFFh which is an invalid.." line.long 0x4 "TYPE1_STATUS_COMMAND_REG,Status and Command Register." bitfld.long 0x4 31. "DETECTED_PARITY_ERROR,Detected Parity Error. This bit is set by a Function whenever it receives a Poisoned TLP regardless of the state the Parity Error Response bit in the Command register. The bit is set when the Poisoned TLP is received by a.." "0,1" newline bitfld.long 0x4 30. "SIGNALED_SYS_ERROR,Signaled System Error. This bit is set when a Function sends an ERR_FATAL or ERR_NONFATAL Message and the SERR# Enable bit in the Command register is 1b." "0,1" newline bitfld.long 0x4 29. "RCVD_MASTER_ABORT,Received Master Abort. This bit is set when a Requester receives a Completion with Unsupported Request Completion status. The bit is set when the Unsupported Request is received by a Function's primary side." "0,1" newline bitfld.long 0x4 28. "RCVD_TARGET_ABORT,Received Target Abort. This bit is set when a Requester receives a Completion with Completer Abort Completion status. The bit is set when the Completer Abort is received by a Function's primary side." "0,1" newline bitfld.long 0x4 27. "SIGNALED_TARGET_ABORT,Signaled Target Abort. This bit is set when a Function completes a Posted or Non-Posted Request as a Completer Abort error. This applies to a Function when the Completer Abort was generated by its primary side." "0,1" newline rbitfld.long 0x4 25.--26. "DEV_SEL_TIMING,DEVSEL Timing. This field was originally described in the PCI Local Bus Specification. Its functionality does not apply to PCI Express. The controller hardwires it to 00b." "0,1,2,3" newline bitfld.long 0x4 24. "MASTER_DPE,Master Data Parity Error. This bit is set by a Function if the Parity Error Response bit in the Command register is 1b and either of the following two conditions occurs: - Port receives a Poisoned Completion going downstream - Port transmits a.." "0,1" newline rbitfld.long 0x4 23. "FAST_B2B_CAP,Fast Back-to-Back Transactions Capable. This bit was originally described in the PCI Local Bus Specification. Its functionality does not apply to PCI Express. The controller hardwires this bit to 0b." "0,1" newline rbitfld.long 0x4 22. "RSVDP_22,Reserved for future use." "0,1" newline rbitfld.long 0x4 21. "FAST_66MHZ_CAP,66 MHz Capable. This bit was originally described in the PCI Local Bus Specification. Its functionality does not apply to PCI Express. The controller hardwires this bit to 0b." "0,1" newline rbitfld.long 0x4 20. "CAP_LIST,Capabilities List. Indicates the presence of an Extended Capability list item. Since all PCI Express device Functions are required to implement the PCI Express Capability structure the controller hardwires this bit to 1b." "0,1" newline rbitfld.long 0x4 19. "INT_STATUS,Interrupt Status. When set indicates that an INTx emulation interrupt is pending internally in the Function. INTx emulation interrupts forwarded by Functions from the secondary side are not reflected in this bit. Setting the Interrupt Disable.." "0,1" newline rbitfld.long 0x4 17.--18. "RSVDP_17,Reserved for future use." "0,1,2,3" newline bitfld.long 0x4 16. "IMM_READINESS,Immediate Readiness. This optional bit when set indicates the Function is guaranteed to be ready to successfully complete valid configuration accesses at any time following any reset that the host is capable of issuing Configuration.." "0,1" newline hexmask.long.byte 0x4 11.--15. 1. "RESERV,Reserved." newline bitfld.long 0x4 10. "INT_EN,Interrupt Disable. Controls the ability of a Function to generate INTx emulation interrupts. When set Functions are prevented from asserting INTx interrupts. Note: - Any INTx emulation interrupts already asserted by the Function must be.." "0,1" newline rbitfld.long 0x4 9. "RSVDP_9,Reserved for future use." "0,1" newline bitfld.long 0x4 8. "SERREN,SERR# Enable. When set this bit enables reporting upstream of Non-fatal and Fatal errors detected by the Function. Note: The errors are reported if enabled either through this bit or through the PCI Express specific bits in the Device Control.." "0,1" newline rbitfld.long 0x4 7. "IDSEL,IDSEL Stepping/Wait Cycle Control. This bit was originally described in the PCI Local Bus Specification. Its functionality does not apply to PCI Express. The controller hardwires this bit to 0b." "0,1" newline bitfld.long 0x4 6. "PERREN,Parity Error Response. This bit controls the logging of poisoned TLPs in the Master Data Parity Error bit in the Status register. For more details see the 'Error Registers' section of the PCI Express Base Specification." "0,1" newline rbitfld.long 0x4 5. "VGAPS,VGA Palette Snoop. This bit was originally described in the PCI Local Bus Specification and the PCI-to-PCI Bridge Architecture Specification. Its functionality does not apply to PCI Express. The controller hardwires this bit to 0b." "0,1" newline rbitfld.long 0x4 4. "MWI_EN,Memory Write and Invalidate. This bit was originally described in the PCI Local Bus Specification and the PCI-to-PCI Bridge Architecture Specification. Its functionality does not apply to PCI Express. The controller hardwires this bit to 0b. For.." "0,1" newline rbitfld.long 0x4 3. "SCO,Special Cycle Enable. This bit was originally described in the PCI Local Bus Specification. Its functionality does not apply to PCI Express. The controller hardwires this bit to 0b." "0,1" newline bitfld.long 0x4 2. "BME,Bus Master Enable. This bit controls forwarding of Memory or I/O requests by a port in the Upstream direction. When this bit is 0b Memory and I/O Requests received at a Root Port must be handled as Unsupported Requests (UR) For Non-Posted Requests a.." "0,1" newline bitfld.long 0x4 1. "MSE,Memory Space Enable. This bit controls a Function's response to Memory Space accesses received on its primary side. - When set the Function is enabled to decode the address and further process Memory Space accesses. - When clear all received Memory.." "0,1" newline bitfld.long 0x4 0. "IO_EN,IO Space Enable. This bit controls a Function's response to I/O Space accesses received on its primary side. - When set the Function is enabled to decode the address and further process I/O Space accesses. - When clear all received I/O accesses.." "0,1" line.long 0x8 "TYPE1_CLASS_CODE_REV_ID_REG,Class Code and Revision ID Register." hexmask.long.byte 0x8 24.--31. 1. "BASE_CLASS_CODE,Base Class Code. A code that broadly classifies the type of operation the Function performs. Encodings for base class are provided in the PCI Code and ID Assignment Specification. All unspecified encodings are reserved. Note: The access.." newline hexmask.long.byte 0x8 16.--23. 1. "SUBCLASS_CODE,Sub-Class Code. Specifies a base class sub-class which identifies more specifically the operation of the Function. Encodings for sub-class are provided in the PCI Code and ID Assignment Specification. All unspecified encodings are.." newline hexmask.long.byte 0x8 8.--15. 1. "PROGRAM_INTERFACE,Programming Interface. This field identifies a specific register level programming interface (if any) so that device independent software can interact with the Function. Encodings for interface are provided in the PCI Code and ID.." newline hexmask.long.byte 0x8 0.--7. 1. "REVISION_ID,Revision ID. The value of this field specifies a Function specific revision identifier. The value is chosen by the vendor. Zero is an acceptable value. The Revision ID should be viewed as a vendor defined extension to the Device ID. Note: The.." line.long 0xC "TYPE1_BIST_HDR_TYPE_LAT_CACHE_LINE_SIZE_REG,BIST. Header Type. Latency Timer. and Cache Line Size Register." hexmask.long.byte 0xC 24.--31. 1. "BIST,BIST. This register is used for control and status of BIST. Functions that do not support BIST must hardwire the register to 00h. A Function whose BIST is invoked must not prevent normal operation of the PCI Express Link. Bit descriptions: - [31]:.." newline rbitfld.long 0xC 23. "MULTI_FUNC,Multi-Function Device. - When set indicates that the device may contain multiple Functions but not necessarily. Software is permitted to probe for Functions other than Function 0. - When clear software must not probe for Functions other.." "0,1" newline hexmask.long.byte 0xC 16.--22. 1. "HEADER_TYPE,Header Layout. This field identifies the layout of the second part of the predefined header. The controller uses 000 0001b encoding. The encoding 000 0010b is reserved. This encoding was originally described in the PC Card Standard Electrical.." newline hexmask.long.byte 0xC 8.--15. 1. "LATENCY_MASTER_TIMER,Latency Timer. This register is also referred to as Primary Latency Timer. The Latency Timer was originally described in the PCI Local Bus Specification and the PCI-to-PCI Bridge Architecture Specification. Its functionality does not.." newline hexmask.long.byte 0xC 0.--7. 1. "CACHE_LINE_SIZE,Cache Line Size. The Cache Line Size register is programmed by the system firmware or the operating system to system cache line size. However legacy conventional PCI software may not always be able to program this register correctly.." line.long 0x10 "BAR0_REG,BAR0 Register. System software must build a consistent address map before booting the machine to an operating system. This means it has to determine how much memory is in the system. and how much address space the Functions in the system.." hexmask.long 0x10 4.--31. 1. "BAR0_START,BAR0 Base Address. - Memory Space: Base Address. - IO Space: bits[31:2] are used to map the function into IO space/Base. Address. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R(Sticky)/W(Sticky) if.." newline bitfld.long 0x10 3. "BAR0_PREFETCH,BAR0 Prefetchable. - Memory Space: Set to one if data is pre-fetchable. A Function is permitted to mark a range as prefetchable. If there are no side effects on reads the function returns all bytes on reads regardless of the byte enables.." "0,1" newline bitfld.long 0x10 1.--2. "BAR0_TYPE,BAR0 Type. - Memory Space: Base Address registers that map into Memory Space can be 32 bits or 64 bits wide (to support mapping into a 64-bit address space). The bit encoding is as follows: -- 00: Base register is 32 bits wide and can be mapped.." "Base register is 32 bits wide and can be mapped..,Reserved,?,?" newline bitfld.long 0x10 0. "BAR0_MEM_IO,BAR0 Memory Space Indicator. This bit is used to determine whether the register maps into Memory or I/O Space. Base Address registers that map to Memory Space must return a 0b. Base Address registers that map to I/O Space must return a 1b." "0,1" line.long 0x14 "BAR1_REG,BAR1 Register. System software must build a consistent address map before booting the machine to an operating system. This means it has to determine how much memory is in the system. and how much address space the Functions in the system.." hexmask.long 0x14 4.--31. 1. "BAR1_START,BAR1 Base Address. - Memory Space: Base Address. - IO Space: bits[31:2] are used to map the function into IO space/Base. Address. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R(Sticky)/W(Sticky) if.." newline bitfld.long 0x14 3. "BAR1_PREFETCH,BAR1 Prefetchable. - Memory Space: Set to one if data is pre-fetchable. A Function is permitted to mark a range as prefetchable. If there are no side effects on reads the function returns all bytes on reads regardless of the byte enables.." "0,1" newline bitfld.long 0x14 1.--2. "BAR1_TYPE,BAR1 Type. - Memory Space: Base Address registers that map into Memory Space can be 32 bits or 64 bits wide (to support mapping into a 64-bit address space). The bit encoding is as follows: -- 00: Base register is 32 bits wide and can be mapped.." "Base register is 32 bits wide and can be mapped..,Reserved,?,?" newline bitfld.long 0x14 0. "BAR1_MEM_IO,BAR1 Memory Space Indicator. This bit is used to determine whether the register maps into Memory or I/O Space. Base Address registers that map to Memory Space must return a 0b. Base Address registers that map to I/O Space must return a 1b." "0,1" line.long 0x18 "SEC_LAT_TIMER_SUB_BUS_SEC_BUS_PRI_BUS_REG,Secondary Latency Timer. Subordinate Bus Number. Secondary Bus Number. and Primary Bus Number Register." hexmask.long.byte 0x18 24.--31. 1. "SEC_LAT_TIMER,Secondary Latency Timer. This register does not apply to PCI Express. The controller hardwires it to 00h." newline hexmask.long.byte 0x18 16.--23. 1. "SUB_BUS,Subordinate Bus Number. The Subordinate Bus Number register is used to record the bus number of the highest numbered PCI bus segment which is behind (or subordinate to) the bridge. Configuration software programs the value in this register. The.." newline hexmask.long.byte 0x18 8.--15. 1. "SEC_BUS,Secondary Bus Number. The Secondary Bus Number register is used to record the bus number of the PCI bus segment to which the secondary interface of the bridge is connected. Configuration software programs the value in this register. The bridge.." newline hexmask.long.byte 0x18 0.--7. 1. "PRIM_BUS,Primary Bus Number. This register is not used by PCI Express Functions. It is implemented for compatibility with legacy software." line.long 0x1C "SEC_STAT_IO_LIMIT_IO_BASE_REG,Secondary Status. and I/O Limit and Base Register. The I/O Limit and I/O Base registers are optional and define an address range that is used by the bridge to determine when to forward I/O transactions from one interface to.." bitfld.long 0x1C 31. "SEC_STAT_DPE,Detected Parity Error. This bit is set by a Function when a Poisoned TLP is received by its secondary side regardless of the state the Parity Error Response Enable bit in the Bridge Control register." "0,1" newline bitfld.long 0x1C 30. "SEC_STAT_RCVD_SYS_ERR,Received System Error. This bit is set when the secondary side of a Function receives an ERR_FATAL or ERR_NONFATAL message." "0,1" newline bitfld.long 0x1C 29. "SEC_STAT_RCVD_MSTR_ABRT,Received Master Abort. This bit is set when the secondary side of a Function (for requests initiated by the Type 1 header Function itself) receives a Completion with Unsupported Request Completion status." "0,1" newline bitfld.long 0x1C 28. "SEC_STAT_RCVD_TRGT_ABRT,Received Target Abort. This bit is set when the secondary side of a Function (for requests initiated by the Type 1 header Function itself) receives a Completion with Completer Abort Completion status." "0,1" newline bitfld.long 0x1C 27. "SEC_STAT_SIG_TRGT_ABRT,Signaled Target Abort. This bit is set when the secondary side of the Function (for Requests completed by the Type 1 header Function itself) completes a Posted or Non-Posted request as a Completer Abort error." "0,1" newline rbitfld.long 0x1C 25.--26. "RSVDP_25,Reserved for future use." "0,1,2,3" newline bitfld.long 0x1C 24. "SEC_STAT_MDPE,Master Data Parity Error. This bit is set by a Function if the Parity Error Response Enable bit in the Bridge Control register is set and either of the following two conditions occurs: - Port receives a Poisoned Completion coming Upstream.." "0,1" newline rbitfld.long 0x1C 23. "RSVDP_23,Reserved for future use." "0,1" newline hexmask.long.byte 0x1C 16.--22. 1. "SEC_STAT_RESERV,Reserved." newline hexmask.long.byte 0x1C 12.--15. 1. "IO_LIMIT,I/O Limit Address. These bits correspond to the address[15:12] of IO address range. For the purpose of address decoding the bridge assumes that the lower 12 address bits address[11:0] of the I/O limit address (not implemented in the I/O Limit.." newline rbitfld.long 0x1C 9.--11. "IO_RESERV1,Reserved." "0,1,2,3,4,5,6,7" newline bitfld.long 0x1C 8. "IO_DECODE_BIT8,I/O Addressing Encode (IO Limit Address). This bit encodes the IO addressing capability of the bridge. IO_DECODE_BIT8 indicates the following: - 0h: The bridge supports only 16-bit I/O addressing (for ISA compatibility). For the purpose of.." "0,1" newline hexmask.long.byte 0x1C 4.--7. 1. "IO_BASE,I/O Base Address. These bits correspond to the address[15:12] of IO address range. For the purpose of address decoding the bridge assumes that the lower 12 address bits address[11:0] of the I/O base address (not implemented in the I/O Base.." newline rbitfld.long 0x1C 1.--3. "IO_RESERV,Reserved." "0,1,2,3,4,5,6,7" newline bitfld.long 0x1C 0. "IO_DECODE,I/O Addressing Encode (IO Base Address) This bit encodes the IO addressing capability of the bridge. IO_DECODE indicates the following: - 0h: The bridge supports only 16-bit I/O addressing (for ISA compatibility). For the purpose of address.." "0,1" line.long 0x20 "MEM_LIMIT_MEM_BASE_REG,Memory Limit and Base Register. The Memory Limit and Memory Base registers define a memory mapped address range which is used by the bridge to determine when to forward memory transactions from one interface to the other. If there.." hexmask.long.word 0x20 20.--31. 1. "MEM_LIMIT,Memory Limit Address. These bits correspond to the upper 12 address bits Address[31:20] of 32-bit addresses. For the purpose of address decoding the bridge assumes that the lower 20 address bits Address[19:0] of the memory limit address.." newline hexmask.long.byte 0x20 16.--19. 1. "MEM_LIMIT_RESERV,Reserved." newline hexmask.long.word 0x20 4.--15. 1. "MEM_BASE,Memory Base Address. These bits correspond to the upper 12 address bits Address[31:20] of 32-bit addresses. For the purpose of address decoding the bridge assumes that the lower 20 address bits Address[19:0] of the memory base address (not.." newline hexmask.long.byte 0x20 0.--3. 1. "MEM_BASE_RESERV,Reserved." line.long 0x24 "PREF_MEM_LIMIT_PREF_MEM_BASE_REG,Prefetchable Memory Limit and Base Register. The Prefetchable Memory Limit and Prefetchable Memory Base registers must indicate that 64-bit addresses are supported. as defined in PCI-to-PCI Bridge Architecture.." hexmask.long.word 0x24 20.--31. 1. "PREF_MEM_LIMIT,Prefetchable Memory Limit Address. If the Prefetchable Memory Limit register indicates support for 32-bit addressing then the Prefetchable Limit Upper 32 Bits register is implemented as a read-only register that returns zero when read. If.." newline rbitfld.long 0x24 17.--19. "PREF_RESERV1,Reserved." "0,1,2,3,4,5,6,7" newline rbitfld.long 0x24 16. "PREF_MEM_LIMIT_DECODE,Prefetchable Memory Limit Decode. This bit encodes whether or not the bridge supports 64-bit addresses. Note: This bit is a copy of the PREF_MEM_DECODE bit and always reflects the current value of that bit. The value of.." "0,1" newline hexmask.long.word 0x24 4.--15. 1. "PREF_MEM_BASE,Prefetchable Memory Base Address. If the Prefetchable Memory Base register indicates support for 32-bit addressing then the Prefetchable Base Upper 32 Bits register is implemented as a read-only register that returns zero when read. If the.." newline rbitfld.long 0x24 1.--3. "PREF_RESERV,Reserved." "0,1,2,3,4,5,6,7" newline bitfld.long 0x24 0. "PREF_MEM_DECODE,Prefetchable Memory Base Decode. This bit encodes whether or not the bridge supports 64-bit addresses. Note: By default the bit is set to 1'b1 indicating that 64-bit addresses are supported. If the bridge only supports 32-bit prefetchable.." "0,1" line.long 0x28 "PREF_BASE_UPPER_REG,Prefetchable Base Upper 32 Bits Register. The Prefetchable Base Upper 32 Bits register is an optional extension to the Prefetchable Memory Base register." hexmask.long 0x28 0.--31. 1. "PREF_MEM_BASE_UPPER,Prefetchable Base Upper 32 Bit. If the Prefetchable Memory Base register indicates support for 32-bit addressing then this register is implemented as read-only register that returns zero when read. If the Prefetchable Memory Base.." line.long 0x2C "PREF_LIMIT_UPPER_REG,Prefetchable Limit Upper 32 Bits Register. The Prefetchable Limit Upper 32 Bits register is an optional extension to the Prefetchable Memory Limit register." hexmask.long 0x2C 0.--31. 1. "PREF_MEM_LIMIT_UPPER,Prefetchable Limit Upper 32 Bit. If the Prefetchable Memory Limit register indicate support for 64-bit addressing then this register is implemented as read/write register which must be initialized by configuration software. This.." rgroup.long 0x30++0x3 line.long 0x0 "IO_LIMIT_UPPER_IO_BASE_UPPER_REG,I/O Limit and Base Upper 16 Bits Register. The I/O Limit Upper 16 Bits and I/O Base Upper 16 Bits registers are optional extensions to the I/O Limit and I/O Base registers." hexmask.long.word 0x0 16.--31. 1. "IO_LIMIT_UPPER,I/O Limit Upper 16 Bits. If the I/O Limit register indicates support for 16-bit I/O address decoding then this register is implemented as a read-only register which return zero when read. If the I/O Limit register indicates support for.." newline hexmask.long.word 0x0 0.--15. 1. "IO_BASE_UPPER,I/O Base Upper 16 Bits. If the I/O Base register indicates support for 16-bit I/O address decoding then this register is implemented as a read-only register which return zero when read. If the I/O base register indicates support for 32-bit.." group.long 0x34++0xB line.long 0x0 "TYPE1_CAP_PTR_REG,Capabilities Pointer Register." hexmask.long.tbyte 0x0 8.--31. 1. "RSVDP_8,Reserved for future use." newline hexmask.long.byte 0x0 0.--7. 1. "CAP_POINTER,Capabilities Pointer. This register is used to point to a linked list of capabilities implemented by this Function. Since all PCI Express Functions are required to implement the PCI Express Capability structure this register must point to a.." line.long 0x4 "TYPE1_EXP_ROM_BASE_REG,Expansion ROM Base Address Register. This register is defined to handle the base address and size information for this expansion ROM. The mask for this ROM BAR exists (if implemented) as a shadow register at this address. The.." hexmask.long.tbyte 0x4 11.--31. 1. "EXP_ROM_BASE_ADDRESS,Expansion ROM Base Address. Upper 21 bits of the Expansion ROM base address. The number of bits (out of these 21) that a Function actually implements depends on how much address space the Function requires. The mask for this ROM BAR.." newline hexmask.long.word 0x4 1.--10. 1. "RSVDP_1,Reserved for future use." newline bitfld.long 0x4 0. "ROM_BAR_ENABLE,Expansion ROM Enable. This bit controls whether or not the Function accepts accesses to its expansion ROM. When this bit is 0b the Function's expansion ROM address space is disabled. When the bit is 1b address decoding is enabled using.." "0,1" line.long 0x8 "BRIDGE_CTRL_INT_PIN_INT_LINE_REG,Bridge Control. Interrupt Pin. and Interrupt Line Register." hexmask.long.word 0x8 23.--31. 1. "BRIDGE_CTRL_RESERV,Reserved." newline bitfld.long 0x8 22. "SBR,Secondary Bus Reset. Setting this bit triggers a hot reset on the corresponding PCI Express Port. Software must ensure a minimum reset duration (Trst) as defined in the PCI Local Bus Specification. Software and systems must honor.." "0,1" newline rbitfld.long 0x8 21. "MSTR_ABORT_MODE,Master Abort Mode. This bit was originally described in the PCI-to-PCI Bridge Architecture Specification. Its functionality does not apply to PCI Express. The controller hardwires this bit to 0b. Note: The access attributes of this field.." "0,1" newline rbitfld.long 0x8 20. "VGA_16B_DEC,VGA 16 bit decode. This bit only has meaning if VGA Enable bit is set. This bit enables system configuration software to select between 10-bit and 16-bit I/O address decoding for all VGA I/O register accesses that are forwarded from primary.." "0,1" newline rbitfld.long 0x8 19. "VGA_EN,VGA Enable. Modifies the response by the bridge to VGA compatible addresses. If the VGA Enable bit is set the bridge will positively decode and forward the following accesses on the primary interface to the secondary interface (and conversely.." "0,1" newline bitfld.long 0x8 18. "ISA_EN,ISA Enable. Modifies the response by the bridge to ISA I/O addresses. This applies only to I/O addresses that are enabled by the I/O Base and I/O Limit registers and are in the first 64 KB of I/O address space (0000 0000h to 0000 FFFFh). If this.." "?,KB block" newline bitfld.long 0x8 17. "SERR_EN,SERR# Enable. This bit controls forwarding of ERR_COR ERR_NONFATAL and ERR_FATAL from secondary to primary." "0,1" newline bitfld.long 0x8 16. "PERE,Parity Error Response Enable. This bit controls the logging of poisoned TLPs in the Master Data Parity Error bit in the Secondary Status register." "0,1" newline hexmask.long.byte 0x8 8.--15. 1. "INT_PIN,Interrupt PIN. The Interrupt Pin register register that identifies the legacy interrupt Message(s) the Function uses. Valid values are: - 01h 02h 03h and 04h: map to legacy interrupt Messages for INTA INTB INTC and INTD respectively. - 00h:.." newline hexmask.long.byte 0x8 0.--7. 1. "INT_LINE,Interrupt Line. The Interrupt Line register communicates interrupt line routing information. The register must be implemented by any Function that uses an interrupt pin. Values in this register are programmed by system software and are system.." tree.end tree "PF0_SPCIE_CAP (Secondary PCI Express Capability Structure)" group.long (0x0+0x1A0)++0xF line.long 0x0 "SPCIE_CAP_HEADER_REG,SPCIE Capability Header. For a description of this standard PCIe register. see the PCI Express Specification." hexmask.long.word 0x0 20.--31. 1. "NEXT_OFFSET,Next Capability Offset. For a description of this standard PCIe register field see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky).." hexmask.long.byte 0x0 16.--19. 1. "CAP_VERSION,Capability Version. For a description of this standard PCIe register field see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else.." hexmask.long.word 0x0 0.--15. 1. "EXTENDED_CAP_ID,Secondary PCI Express Extended Capability ID. For a description of this standard PCIe register field see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN.." line.long 0x4 "LINK_CONTROL3_REG,Link Control 3 Register. For a description of this standard PCIe register. see the PCI Express Specification." hexmask.long 0x4 2.--31. 1. "RSVDP_2,Reserved for future use." bitfld.long 0x4 1. "EQ_REQ_INT_EN,Link Equalization Request Interrupt Enable. For a description of this standard PCIe register field see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" "0,1" bitfld.long 0x4 0. "PERFORM_EQ,Perform Equalization. For a description of this standard PCIe register field see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" "0,1" line.long 0x8 "LANE_ERR_STATUS_REG,Lane Error Status Register. For a description of this standard PCIe register. see the PCI Express Specification." hexmask.long 0x8 2.--31. 1. "RSVDP_LANE_ERR_STATUS,Reserved for future use." bitfld.long 0x8 0.--1. "LANE_ERR_STATUS,Lane Error Status Bits per Lane. For a description of this standard PCIe register field see the PCI Express Specification." "0,1,2,3" line.long 0xC "SPCIE_CAP_OFF_0CH_REG,Lane Equalization Control Register for lanes 1 and 0. For a description of this standard PCIe register. see the PCI Express Specification." rbitfld.long 0xC 31. "RSVDP_31,Reserved for future use." "0,1" bitfld.long 0xC 28.--30. "USP_RX_PRESET_HINT1,Upstream Port 8.0 GT/s Receiver Preset Hint 1. The write value is gated with the PCIE_CAP_CROSS_LINK_SUPPORT field of LINK_CAPABILITIES2_REG. For a description of this standard PCIe register field see the PCI Express Specification." "0,1,2,3,4,5,6,7" hexmask.long.byte 0xC 24.--27. 1. "USP_TX_PRESET1,Upstream Port 8.0 GT/s Transmitter Preset 1. The write value is gated with the PCIE_CAP_CROSS_LINK_SUPPORT field of LINK_CAPABILITIES2_REG. For a description of this standard PCIe register field see the PCI Express Specification. Note:.." rbitfld.long 0xC 23. "RSVDP_23,Reserved for future use." "0,1" newline bitfld.long 0xC 20.--22. "DSP_RX_PRESET_HINT1,Downstream Port 8.0 GT/s Receiver Preset Hint 1. For a description of this standard PCIe register field see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if.." "0,1,2,3,4,5,6,7" hexmask.long.byte 0xC 16.--19. 1. "DSP_TX_PRESET1,Downstream Port 8.0 GT/s Transmitter Preset 1. For a description of this standard PCIe register field see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN.." rbitfld.long 0xC 15. "RSVDP_15,Reserved for future use." "0,1" bitfld.long 0xC 12.--14. "USP_RX_PRESET_HINT0,Upstream Port 8.0 GT/s Receiver Preset Hint 0. The write value is gated with the PCIE_CAP_CROSS_LINK_SUPPORT field of LINK_CAPABILITIES2_REG. For a description of this standard PCIe register field see the PCI Express Specification." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0xC 8.--11. 1. "USP_TX_PRESET0,Upstream Port 8.0 GT/s Transmitter Preset 0. The write value is gated with the PCIE_CAP_CROSS_LINK_SUPPORT field of LINK_CAPABILITIES2_REG. For a description of this standard PCIe register field see the PCI Express Specification. Note:.." rbitfld.long 0xC 7. "RSVDP_7,Reserved for future use." "0,1" bitfld.long 0xC 4.--6. "DSP_RX_PRESET_HINT0,Downstream Port 8.0 GT/s Receiver Preset Hint 0. For a description of this standard PCIe register field see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if.." "0,1,2,3,4,5,6,7" hexmask.long.byte 0xC 0.--3. 1. "DSP_TX_PRESET0,Downstream Port 8.0 GT/s Transmitter Preset 0. For a description of this standard PCIe register field see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN.." tree.end tree "PF0_L1SUB_CAP (L1 Substates Capability Structure)" group.long (0x0+0x2E8)++0xF line.long 0x0 "L1SUB_CAP_HEADER_REG,L1 Substates Extended Capability Header. This register provides capbility ID. capability version and next offset value for L1 Substates." hexmask.long.word 0x0 20.--31. 1. "NEXT_OFFSET,Next Capability Offset. This field contains the offset to the next PCI Express Capability structure or 000h if no other items exist in the linked list of Capabilities. For Extended Capabilities implemented in Configuration Space this offset.." hexmask.long.byte 0x0 16.--19. 1. "CAP_VERSION,Capability Version. This field is a PCI-SIG defined version number that indicates the version of the Capability structure present. This field is depends on version of the specification. Note: The access attributes of this field are as.." hexmask.long.word 0x0 0.--15. 1. "EXTENDED_CAP_ID,L1SUB Extended Capability ID. This field is a PCI-SIG defined ID number that indicates the nature and format of the Extended Capability. Extended Capability ID for L1 PM Substates is 001Eh. Note: The access attributes of this field are as.." line.long 0x4 "L1SUB_CAPABILITY_REG,L1 Substates Capability Register. This register provides extended capability of L1 Substates." hexmask.long.byte 0x4 24.--31. 1. "RSVDP_24,Reserved for future use." hexmask.long.byte 0x4 19.--23. 1. "PWR_ON_VALUE_SUPPORT,Port T Power On Value. Along with the Port T_POWER_ON Scale field in the L1 PM Substates Capabilities register sets the time (in us) that this Port requires the port on the opposite side of Link to wait in L1.2.Exit after sampling.." rbitfld.long 0x4 18. "RSVDP_18,Reserved for future use." "0,1" bitfld.long 0x4 16.--17. "PWR_ON_SCALE_SUPPORT,Port T Power On Scale. Specifies the scale used for the Port T_POWER_ON Value field in the L1 PM Substates Capabilities register. Range of values are given below. Required for all Ports for which either the PCI-PM L1.2 Supported bit.." "?,?,?,Reserved" newline hexmask.long.byte 0x4 8.--15. 1. "COMM_MODE_SUPPORT,Port Common Mode Restore Time. Time (in us) required for this Port to re-establish common mode. Required for all Ports for which either the PCI-PM L1.2 Supported bit is Set ASPM L1.2 Supported bit is Set or both are Set otherwise.." rbitfld.long 0x4 5.--7. "RSVDP_5,Reserved for future use." "0,1,2,3,4,5,6,7" bitfld.long 0x4 4. "L1_PMSUB_SUPPORT,L1 PM Substates ECN Supported. When Set this bit indicates that this Port supports L1 PM Substates. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W (sticky)" "0,1" bitfld.long 0x4 3. "L1_1_ASPM_SUPPORT,ASPM L11 Supported. When Set this bit indicates that ASPM L1.1 is supported. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W (sticky)" "0,1" newline bitfld.long 0x4 2. "L1_2_ASPM_SUPPORT,ASPM L12 Supported. When Set this bit indicates that ASPM L1.2 is supported. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W (sticky)" "0,1" bitfld.long 0x4 1. "L1_1_PCIPM_SUPPORT,PCI-PM L11 Supported. When Set this bit indicates that PCI-PM L1.1 is supported and must be Set by all Ports implementing L1 PM Substates. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W (sticky)" "0,1" bitfld.long 0x4 0. "L1_2_PCIPM_SUPPORT,PCI-PM L12 Supported. When Set this bit indicates that PCI-PM L1.2 is supported. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W (sticky)" "0,1" line.long 0x8 "L1SUB_CONTROL1_REG,L1 Substates Control 1 Register. This register provides Controls to extended capability." bitfld.long 0x8 29.--31. "L1_2_TH_SCA,LTR L12 Threshold Scale. This field provides a scale for the value contained within the LTR_L1.2_THRESHOLD_Value.The default value for this field is 000b.Hardware operation is undefined if software writes a Not-Permitted value to this field." "0,1,2,3,4,5,6,7" rbitfld.long 0x8 26.--28. "RSVDP_26,Reserved for future use." "0,1,2,3,4,5,6,7" hexmask.long.word 0x8 16.--25. 1. "L1_2_TH_VAL,LTR L12 Threshold Value. Along with the LTR_L1.2_THRESHOLD_Scale this field indicates the LTR threshold used to determine if entry into L1 results in L1.1 (if enabled) or L1.2 (if enabled). The default value for this field is 00 0000 0000b." hexmask.long.byte 0x8 8.--15. 1. "T_COMMON_MODE,Common Mode Restore Time. Sets value of TCOMMONMODE (in us) which must be used by the Downstream Ports for timing the re-establishment of common mode.This field is of type RsvdP for Upstream Ports. Default value is implementation.." newline hexmask.long.byte 0x8 4.--7. 1. "RSVDP_4,Reserved for future use." bitfld.long 0x8 3. "L1_1_ASPM_EN,ASPM L11 Enable. When Set this bit enables ASPM L1.1.For Ports for which the ASPM L1.1 Supported bit is Clear this bit is permitted to be hardwired to 0.Default value is 0b." "0,1" bitfld.long 0x8 2. "L1_2_ASPM_EN,ASPM L12 Enable. When Set this bit enables ASPM L1.2.For Ports for which the ASPM L1.2 Supported bit is Clear this bit is permitted to be hardwired to 0.Default value is 0b." "0,1" bitfld.long 0x8 1. "L1_1_PCIPM_EN,PCI-PM L11 Enable. When Set this bit enables PCI-PM L1.1. Default value is 0b." "0,1" newline bitfld.long 0x8 0. "L1_2_PCIPM_EN,PCI-PM L12 Enable. When Set this bit enables PCI-PM L1.2.For Ports for which the PCI-PM L1.2 Supported bit is Clear this bit is permitted to be hardwired to 0.Default value is 0b." "0,1" line.long 0xC "L1SUB_CONTROL2_REG,L1 Substates Control 2 Register. This register provides Controls to extended capability." hexmask.long.tbyte 0xC 8.--31. 1. "RSVDP_8,Reserved for future use." hexmask.long.byte 0xC 3.--7. 1. "T_POWER_ON_VALUE,T Power On Value. Along with the T_POWER_ON Scale sets the minimum amount of time (in us) that the Port must wait in L1.2.Exit after sampling CLKREQ# asserted before actively driving the interface.Default value is 00101b. T_POWER_ON is.." rbitfld.long 0xC 2. "RSVDP_2,Reserved for future use." "0,1" bitfld.long 0xC 0.--1. "T_POWER_ON_SCALE,T Power On Scale. Specifies the scale used for T_POWER_ON Value. Range of values are given below. Required for all Ports that support L1.2 otherwise this field is of type RsvdP. This field must only be modified when the ASPM L1.2 Enable.." "?,?,?,Reserved" tree.end tree "PF0_RAS_DES_CAP (RAS D.E.S. Capability Structure (VSEC))" group.long (0x0+0x30C)++0x3 line.long 0x0 "RAS_DES_CAP_HEADER_REG,Vendor-Specific Extended Capability Header. For a description of this standard PCIe register. see the PCI Express Specification." hexmask.long.word 0x0 20.--31. 1. "NEXT_OFFSET,Next Capability Offset. For a description of this standard PCIe register field see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky).." newline hexmask.long.byte 0x0 16.--19. 1. "CAP_VERSION,Capability Version. For a description of this standard PCIe register field see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else.." newline hexmask.long.word 0x0 0.--15. 1. "EXTENDED_CAP_ID,PCI Express Extended Capability ID. For a description of this standard PCIe register field see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then.." rgroup.long (0x4+0x30C)++0x3 line.long 0x0 "VENDOR_SPECIFIC_HEADER_REG,Vendor-Specific Header. For a description of this standard PCIe register. see the PCI Express Specification." hexmask.long.word 0x0 20.--31. 1. "VSEC_LENGTH,VSEC Length. For a description of this standard PCIe register field see the PCI Express Specification." newline hexmask.long.byte 0x0 16.--19. 1. "VSEC_REV,VSEC Rev. For a description of this standard PCIe register field see the PCI Express Specification." newline hexmask.long.word 0x0 0.--15. 1. "VSEC_ID,VSEC ID. For a description of this standard PCIe register field see the PCI Express Specification." group.long (0x8+0x30C)++0x3 line.long 0x0 "EVENT_COUNTER_CONTROL_REG,Event Counter Control. This is a viewport control register. - Setting the EVENT_COUNTER_EVENT_SELECT and EVENT_COUNTER_LANE_SELECT fields in this register determine the Event Counter data returned by the EVENT_COUNTER_DATA_REG.." hexmask.long.byte 0x0 28.--31. 1. "RSVDP_28,Reserved for future use." newline hexmask.long.word 0x0 16.--27. 1. "EVENT_COUNTER_EVENT_SELECT,Event Counter Data Select. This field in conjunction with the EVENT_COUNTER_LANE_SELECT field indexes the Event Counter data returned by the EVENT_COUNTER_DATA_REG register. - 27-24: Group number(4-bit: 0..0x7) - 23-16: Event.." newline hexmask.long.byte 0x0 12.--15. 1. "RSVDP_12,Reserved for future use." newline hexmask.long.byte 0x0 8.--11. 1. "EVENT_COUNTER_LANE_SELECT,Event Counter Lane Select. This field in conjunction with EVENT_COUNTER_EVENT_SELECT indexes the Event Counter data returned by the EVENT_COUNTER_DATA_REG register. - 0x0: Lane0 - 0x1: Lane1 - 0x2: Lane2 - .. - 0xF: Lane15 Note:.." newline rbitfld.long 0x0 7. "EVENT_COUNTER_STATUS,Event Counter Status. This register returns the current value of the Event Counter selected by the following fields: - EVENT_COUNTER_EVENT_SELECT - EVENT_COUNTER_LANE_SELECT Note: This register field is sticky." "0,1" newline rbitfld.long 0x0 5.--6. "RSVDP_5,Reserved for future use." "0,1,2,3" newline bitfld.long 0x0 2.--4. "EVENT_COUNTER_ENABLE,Event Counter Enable. Enables/disables the Event Counter selected by the EVENT_COUNTER_EVENT_SELECT and EVENT_COUNTER_LANE_SELECT fields in this register. By default all event counters are disabled. You can enable/disable a specific.." "no change,per event off,?,?,?,?,?,?" newline bitfld.long 0x0 0.--1. "EVENT_COUNTER_CLEAR,Event Counter Clear. Clears the Event Counter selected by the EVENT_COUNTER_EVENT_SELECT and EVENT_COUNTER_LANE_SELECT fields in this register. You can clear the value of a specific Event Counter by writing the 'per clear' code and.." "no change,per clear,?,?" rgroup.long (0xC+0x30C)++0x3 line.long 0x0 "EVENT_COUNTER_DATA_REG,Event Counter Data. This viewport register returns the data selected by the following fields: - EVENT_COUNTER_EVENT_SELECT in EVENT_COUNTER_CONTROL_REG - EVENT_COUNTER_LANE_SELECT in EVENT_COUNTER_CONTROL_REG For more details. see.." hexmask.long 0x0 0.--31. 1. "EVENT_COUNTER_DATA,Event Counter Data. This register returns the data selected by the following fields: - EVENT_COUNTER_EVENT_SELECT in EVENT_COUNTER_CONTROL_REG - EVENT_COUNTER_LANE_SELECT in EVENT_COUNTER_CONTROL_REG Note: This register field is sticky." group.long (0x10+0x30C)++0x3 line.long 0x0 "TIME_BASED_ANALYSIS_CONTROL_REG,Time-based Analysis Control. Used for controlling the measurement of RX/TX data throughput and time spent in each low-power LTSSM state. For more details. see the RAS DES section in the Core Operations chapter of the.." hexmask.long.byte 0x0 24.--31. 1. "TIME_BASED_REPORT_SELECT,Time-based Report Select. Selects what type of data is measured for the selected duration (TIME_BASED_DURATION_SELECT) and returned in TIME_BASED_ANALYSIS_DATA. Each type of data is measured using one of three types of units: -.." newline hexmask.long.byte 0x0 16.--23. 1. "RSVDP_16,Reserved for future use." newline hexmask.long.byte 0x0 8.--15. 1. "TIME_BASED_DURATION_SELECT,Time-based Duration Select. Selects the duration of time-based analysis. When 'manual control' is selected and TIMER_START is set to '1' this analysis never stops until TIMER_STOP is set to '0'. - 0x0: Manual control - 0x1:.." newline hexmask.long.byte 0x0 1.--7. 1. "RSVDP_1,Reserved for future use." newline bitfld.long 0x0 0. "TIMER_START,Timer Start. - 1: Start/Restart - 0: Stop This bit will be cleared automatically when the measurement is finished. Note: The app_ras_des_tba_ctrl input also sets the contents of this field and controls the measurement start/stop. Note: This.." "Stop,Start/Restart" rgroup.long (0x14+0x30C)++0x7 line.long 0x0 "TIME_BASED_ANALYSIS_DATA_REG,Time-based Analysis Data. Contains the measurement results of RX/TX data throughput and time spent in each low-power LTSSM state. This viewport register returns the data selected by the TIME_BASED_REPORT_SELECT field in.." hexmask.long 0x0 0.--31. 1. "TIME_BASED_ANALYSIS_DATA,Time Based Analysis Data. This register returns the data selected by the TIME_BASED_REPORT_SELECT field in TIME_BASED_ANALYSIS_CONTROL_REG. The results are cleared when next measurement starts. Note: This register field is sticky." line.long 0x4 "TIME_BASED_ANALYSIS_DATA_63_32_REG,Upper 32 bits of Time-based Analysis Data. This viewport register returns the data selected by the TIME_BASED_REPORT_SELECT field in TIME_BASED_ANALYSIS_CONTROL_REG. For more details. see the RAS DES section in the Core.." hexmask.long 0x4 0.--31. 1. "TIME_BASED_ANALYSIS_DATA_63_32,Upper 32 bits of Time Based Analysis Data. Note: This register field is sticky." group.long (0x30+0x30C)++0x5F line.long 0x0 "EINJ_ENABLE_REG,Error Injection Enable. Each type of error insertion is enabled by the corresponding bit in this register. The specific injection controls for each type of error are defined in the following registers: - 0: CRC Error: EINJ0_CRC_REG - 1:.." hexmask.long 0x0 7.--31. 1. "RSVDP_7,Reserved for future use." newline bitfld.long 0x0 6. "ERROR_INJECTION6_ENABLE,Error Injection6 Enable (Specific TLP Error). Enables insertion of errors into the packets that you select. You can set this bit to '1' when you have disabled RAS datapath protection (DP) by setting CX_RASDP = CX_RASDP_RAM_PROT.." "0,1" newline bitfld.long 0x0 5. "ERROR_INJECTION5_ENABLE,Error Injection5 Enable (TLP Duplicate/Nullify Error). Enables insertion of duplicate/nullified TLPs. For more details see the EINJ5_SP_TLP_REG register. Note: This register field is sticky." "0,1" newline bitfld.long 0x0 4. "ERROR_INJECTION4_ENABLE,Error Injection4 Enable (FC Credit Update Error). Enables insertion of errors into UpdateFCs. For more details see the EINJ4_FC_REG register. Note: This register field is sticky." "0,1" newline bitfld.long 0x0 3. "ERROR_INJECTION3_ENABLE,Error Injection3 Enable (Symbol DataK Mask Error or Sync Header Error). Enables DataK masking of special symbols or the breaking of the sync header. For more details see the EINJ3_SYMBOL_REG register. Note: This register field is.." "0,1" newline bitfld.long 0x0 2. "ERROR_INJECTION2_ENABLE,Error Injection2 Enable (DLLP Error). Enables insertion of DLLP errors. For more details see the EINJ2_DLLP_REG register. Note: This register field is sticky." "0,1" newline bitfld.long 0x0 1. "ERROR_INJECTION1_ENABLE,Error Injection1 Enable (Sequence Number Error). Enables insertion of errors into sequence numbers. For more details see the EINJ1_SEQNUM_REG register. Note: This register field is sticky." "0,1" newline bitfld.long 0x0 0. "ERROR_INJECTION0_ENABLE,Error Injection0 Enable (CRC Error). Enables insertion of errors into various CRC. For more details see the EINJ0_CRC_REG register. Note: This register field is sticky." "0,1" line.long 0x4 "EINJ0_CRC_REG,Error Injection Control 0 (CRC Error). Controls the insertion of errors into the CRC. and parity of ordered sets for the selected type of the packets as follows: - LCRC. Bad TLP will be detected at the receiver side; receiver responds with.." hexmask.long.tbyte 0x4 12.--31. 1. "RSVDP_12,Reserved for future use." newline hexmask.long.byte 0x4 8.--11. 1. "EINJ0_CRC_TYPE,Error injection type. Selects the type of CRC error to be inserted. Tx Path - 0000b: New TLP's LCRC error injection - 0001b: 16bCRC error injection of ACK/NAK DLLP - 0010b: 16bCRC error injection of Update-FC DLLP - 0011b: New TLP's ECRC.." newline hexmask.long.byte 0x4 0.--7. 1. "EINJ0_COUNT,Error injection count. Indicates the number of errors. This register is decremented when the errors have been inserted. - If the counter value is 0x01 and error is inserted ERROR_INJECTION0_ENABLE in EINJ_ENABLE_REG returns 0b. - If the.." line.long 0x8 "EINJ1_SEQNUM_REG,Error Injection Control 1 (Sequence Number Error). Controls the sequence number of the specific TLPs and ACK/NAK DLLPs. Data Link Protocol Error will be detected at the Rx side of ACK/NAL DLLPs when one of these conditions is true: -.." rbitfld.long 0x8 29.--31. "RSVDP_29,Reserved for future use." "0,1,2,3,4,5,6,7" newline hexmask.long.word 0x8 16.--28. 1. "EINJ1_BAD_SEQNUM,Bad sequence number. Indicates the value to add/subtract from the naturally-assigned sequence numbers. This value is represented by two's complement. - 0x0FFF: +4095 - .. - 0x0002: +2 - 0x0001: +1 - 0x0000: 0 - 0x1FFF: -1 - 0x1FFE: -2 -.." newline hexmask.long.byte 0x8 9.--15. 1. "RSVDP_9,Reserved for future use." newline bitfld.long 0x8 8. "EINJ1_SEQNUM_TYPE,Sequence number type. Selects the type of sequence number. - 0b: Insertion of New TLP's SEQ# error - 1b: Insertion of ACK/NAK DLLP's SEQ# Error Note: This register field is sticky." "0,1" newline hexmask.long.byte 0x8 0.--7. 1. "EINJ1_COUNT,Error injection count. Indicates the number of errors. This register is decremented as the errors are being inserted. - If the counter value is 0x01 and error is inserted ERROR_INJECTION1_ENABLE in EINJ_ENABLE_REG returns '0'. - If the.." line.long 0xC "EINJ2_DLLP_REG,Error Injection Control 2 (DLLP Error). Controls the transmission of DLLPs and inserts the following errors: - If 'ACK/NAK DLLP's transmission block' is selected. replay timeout error will occur at the transmitter of the TLPs and then Data.." hexmask.long.tbyte 0xC 10.--31. 1. "RSVDP_10,Reserved for future use." newline bitfld.long 0xC 8.--9. "EINJ2_DLLP_TYPE,DLLP Type. Selects the type of DLLP errors to be inserted. - 00b: ACK/NAK DLLP's transmission block - 01b: Update FC DLLP's transmission block - 10b: Always Transmission for NAK DLLP - 11b: Reserved Note: This register field is sticky." "0,1,2,3" newline hexmask.long.byte 0xC 0.--7. 1. "EINJ2_COUNT,Error injection count. Indicates the number of errors. This register is decremented as the errors are being inserted. - If the counter value is 0x01 and the error is inserted ERROR_INJECTION2_ENABLE in EINJ_ENABLE_REG returns '0'. - If the.." line.long 0x10 "EINJ3_SYMBOL_REG,Error Injection Control 3 (Symbol Error). When 8b/10b encoding is used. this register controls error insertion into the special (K code) symbols. - If TS1/TS2/FTS/E-Idle/SKP is selected. it affects whole of the ordered set. It might.." hexmask.long.tbyte 0x10 11.--31. 1. "RSVDP_11,Reserved for future use." newline bitfld.long 0x10 8.--10. "EINJ3_SYMBOL_TYPE,Error Type. 8b/10b encoding - Mask K symbol. It is not supported to insert errors into the first ordered-set after exiting from TxElecIdle when CX_FREQ_STEP_EN has been enabled. - 000b: Reserved - 001b: COM/PAD(TS1 Order set) - 010b:.." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x10 0.--7. 1. "EINJ3_COUNT,Error injection count. Indicates the number of errors. This register is decremented as the errors are being inserted. - If the counter value is 0x01 and error is inserted ERROR_INJECTION3_ENABLE in EINJ_ENABLE_REG returns '0'. - If the.." line.long 0x14 "EINJ4_FC_REG,Error Injection Control 4 (FC Credit Error). Controls error insertion into the credit value in the UpdateFCs. It is possible to insert errors for any of the following types: - Posted TLP Header credit - Non-Posted TLP Header credit -.." rbitfld.long 0x14 29.--31. "RSVDP_29,Reserved for future use." "0,1,2,3,4,5,6,7" newline hexmask.long.word 0x14 16.--28. 1. "EINJ4_BAD_UPDFC_VALUE,Bad update-FC credit value. Indicates the value to add/subtract from the UpdateFC credit. This value is represented by two's complement. - 0x0FFF: +4095 - .. - 0x0002: +2 - 0x0001: +1 - 0x0000: 0 - 0x1FFF: -1 - 0x1FFE: -2 - .. -.." newline rbitfld.long 0x14 15. "RSVDP_15,Reserved for future use." "0,1" newline bitfld.long 0x14 12.--14. "EINJ4_VC_NUMBER,VC Number. Indicates target VC Number. Note: This register field is sticky." "0,1,2,3,4,5,6,7" newline rbitfld.long 0x14 11. "RSVDP_11,Reserved for future use." "0,1" newline bitfld.long 0x14 8.--10. "EINJ4_UPDFC_TYPE,Update-FC type. Selects the credit type. - 000b: Posted TLP Header Credit value control - 001b: Non-Posted TLP Header Credit value control - 010b: Completion TLP Header Credit value control - 011b: Reserved - 100b: Posted TLP Data Credit.." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x14 0.--7. 1. "EINJ4_COUNT,Error injection count. Indicates the number of errors. This register is decremented as the errors are being inserted. - If the counter value is 0x01 and error is inserted ERROR_INJECTION4_ENABLE in EINJ_ENABLE_REG returns '0'. - If the.." line.long 0x18 "EINJ5_SP_TLP_REG,Error Injection Control 5 (Specific TLP Error). Controls the generation of specified TLPs. Correctable errors will occur which will be fixed by the PCIe protocol. - For Duplicate TLP. the controller initiates Data Link Retry by handling.." hexmask.long.tbyte 0x18 9.--31. 1. "RSVDP_9,Reserved for future use." newline bitfld.long 0x18 8. "EINJ5_SPECIFIED_TLP,Specified TLP. Selects the specified TLP to be inserted. - 0: Generates duplicate TLPs by handling ACK DLLP as NAK DLLP. - 1: Generates Nullified TLP (Original TLP will be stored in retry buffer). Note: This register field is sticky." "Generates duplicate TLPs by handling ACK DLLP as..,Generates Nullified TLP" newline hexmask.long.byte 0x18 0.--7. 1. "EINJ5_COUNT,Error injection count. Indicates the number of errors. This register is decremented as the errors are being inserted. - If the counter value is 0x01 and error is inserted ERROR_INJECTION5_ENABLE in EINJ_ENABLE_REG returns '0'. - If the.." line.long 0x1C "EINJ6_COMPARE_POINT_H0_REG,Error Injection Control 6 (Compare Point Header DWORD #0). Program this register for the 1st DWORD of TLP header/prefix. It is necessary to carefully consider the endianness when you program this register. Bits [31:0] =.." hexmask.long 0x1C 0.--31. 1. "EINJ6_COMPARE_POINT_H0,Packet Compare Point: 1st DWORD. Specifies which Tx TLP header DWORD#0 bits to compare with the corresponding bits in the Packet Compare Value registers (EINJ6_COMPARE_VALUE*). When all specified bits (in the Tx TLP header and.." line.long 0x20 "EINJ6_COMPARE_POINT_H1_REG,Error Injection Control 6 (Compare Point Header DWORD #1). Program this register for the 2nd DWORD of TLP header/prefix. It is necessary to carefully consider the endianness when you program this register. Bits [31:0] =.." hexmask.long 0x20 0.--31. 1. "EINJ6_COMPARE_POINT_H1,Packet Compare Point: 2nd DWORD. Specifies which Tx TLP header DWORD#1 bits to compare with the corresponding bits in the Packet Compare Value registers (EINJ6_COMPARE_VALUE*). When all specified bits (in the Tx TLP header and.." line.long 0x24 "EINJ6_COMPARE_POINT_H2_REG,Error Injection Control 6 (Compare Point Header DWORD #2). Program this register for the 3rd DWORD of TLP header/prefix. It is necessary to carefully consider the endianness when you program this register. Bits [31:0] =.." hexmask.long 0x24 0.--31. 1. "EINJ6_COMPARE_POINT_H2,Packet Compare Point: 3rd DWORD. Specifies which Tx TLP header DWORD#2 bits to compare with the corresponding bits in the Packet Compare Value registers (EINJ6_COMPARE_VALUE*). When all specified bits (in the Tx TLP header and.." line.long 0x28 "EINJ6_COMPARE_POINT_H3_REG,Error Injection Control 6 (Compare Point Header DWORD #3). Program this register for the 4th DWORD of TLP header/prefix. It is necessary to carefully consider the endianness when you program this register. Bits [31:0] =.." hexmask.long 0x28 0.--31. 1. "EINJ6_COMPARE_POINT_H3,Packet Compare Point: 4th DWORD. Specifies which Tx TLP header DWORD#3 bits to compare with the corresponding bits in the Packet Compare Value registers (EINJ6_COMPARE_VALUE*). When all specified bits (in the Tx TLP header and.." line.long 0x2C "EINJ6_COMPARE_VALUE_H0_REG,Error Injection Control 6 (Compare Value Header DWORD #0). Program this register for the 1st DWORD of TLP header/prefix. It is necessary to carefully consider the endianness when you program this register. Bits [31:0] =.." hexmask.long 0x2C 0.--31. 1. "EINJ6_COMPARE_VALUE_H0,Packet Compare Value: 1st DWORD. Specifies the value to compare against Tx the TLP header DWORD#0 bits specified in the Packet Compare Point registers (EINJ6_COMPARE_POINT*). Note: This register field is sticky." line.long 0x30 "EINJ6_COMPARE_VALUE_H1_REG,Error Injection Control 6 (Compare Value Header DWORD #1). Program this register for the 2nd DWORD of TLP header/prefix. It is necessary to carefully consider the endianness when you program this register. Bits [31:0] =.." hexmask.long 0x30 0.--31. 1. "EINJ6_COMPARE_VALUE_H1,Packet Compare Value: 2nd DWORD. Specifies the value to compare against Tx the TLP header DWORD#1 bits specified in the Packet Compare Point registers (EINJ6_COMPARE_POINT*). Note: This register field is sticky." line.long 0x34 "EINJ6_COMPARE_VALUE_H2_REG,Error Injection Control 6 (Compare Value Header DWORD #2). Program this register for the 3rd DWORD of TLP header/prefix. It is necessary to carefully consider the endianness when you program this register. Bits [31:0] =.." hexmask.long 0x34 0.--31. 1. "EINJ6_COMPARE_VALUE_H2,Packet Compare Value: 3rd DWORD. Specifies the value to compare against Tx the TLP header DWORD#2 bits specified in the Packet Compare Point registers (EINJ6_COMPARE_POINT*). Note: This register field is sticky." line.long 0x38 "EINJ6_COMPARE_VALUE_H3_REG,Error Injection Control 6 (Compare Value Header DWORD #3). Program this register for the 4th DWORD of TLP header/prefix. It is necessary to carefully consider the endianness when you program this register. Bits [31:0] =.." hexmask.long 0x38 0.--31. 1. "EINJ6_COMPARE_VALUE_H3,Packet Compare Value: 4th DWORD. Specifies the value to compare against Tx the TLP header DWORD#3 bits specified in the Packet Compare Point registers (EINJ6_COMPARE_POINT*). Note: This register field is sticky." line.long 0x3C "EINJ6_CHANGE_POINT_H0_REG,Error Injection Control 6 (Change Point Header DWORD #0). Program this register for the 1st DWORD of TLP header/prefix. It is necessary to carefully consider the endianness when you program this register. Bits [31:0] =.." hexmask.long 0x3C 0.--31. 1. "EINJ6_CHANGE_POINT_H0,Packet Change Point: 1st DWORD. Specifies which Tx TLP header DWORD#0 bits to replace with the corresponding bits in the Packet Change Value registers (EINJ6_CHANGE_VALUE*). Note: This register field is sticky." line.long 0x40 "EINJ6_CHANGE_POINT_H1_REG,Error Injection Control 6 (Change Point Header DWORD #1). Program this register for the 2nd DWORD of TLP header/prefix. It is necessary to carefully consider the endianness when you program this register. Bits [31:0] =.." hexmask.long 0x40 0.--31. 1. "EINJ6_CHANGE_POINT_H1,Packet Change Point: 2nd DWORD. Specifies which Tx TLP header DWORD#1 bits to replace with the corresponding bits in the Packet Change Value registers (EINJ6_CHANGE_VALUE*). Note: This register field is sticky." line.long 0x44 "EINJ6_CHANGE_POINT_H2_REG,Error Injection Control 6 (Change Point Header DWORD #2). Program this register for the 3rd DWORD of TLP header/prefix. It is necessary to carefully consider the endianness when you program this register. Bits [31:0] =.." hexmask.long 0x44 0.--31. 1. "EINJ6_CHANGE_POINT_H2,Packet Change Point: 3rd DWORD. Specifies which Tx TLP header DWORD#2 bits to replace with the corresponding bits in the Packet Change Value registers (EINJ6_CHANGE_VALUE*). Note: This register field is sticky." line.long 0x48 "EINJ6_CHANGE_POINT_H3_REG,Error Injection Control 6 (Change Point Header DWORD #3). Program this register for the 4th DWORD of TLP header/prefix. It is necessary to carefully consider the endianness when you program this register. Bits [31:0] =.." hexmask.long 0x48 0.--31. 1. "EINJ6_CHANGE_POINT_H3,Packet Change Point: 4th DWORD. Specifies which Tx TLP header DWORD#3 bits to replace with the corresponding bits in the Packet Change Value registers (EINJ6_CHANGE_VALUE*). Note: This register field is sticky." line.long 0x4C "EINJ6_CHANGE_VALUE_H0_REG,Error Injection Control 6 (Change Value Header DWORD #0). Program this register for the 1st DWORD of TLP header/prefix. It is necessary to carefully consider the endianness when you program this register. Bits [31:0] =.." hexmask.long 0x4C 0.--31. 1. "EINJ6_CHANGE_VALUE_H0,Packet Change Value: 1st DWORD. Specifies replacement values for the Tx TLP header DWORD#0 bits defined in the Packet Change Point registers (EINJ6_CHANGE_POINT*). Only applies when the EINJ6_INVERTED_CONTROL field in EINJ6_TLP_REG.." line.long 0x50 "EINJ6_CHANGE_VALUE_H1_REG,Error Injection Control 6 (Change Value Header DWORD #1). Program this register for the 2nd DWORD of TLP header/prefix. It is necessary to carefully consider the endianness when you program this register. Bits [31:0] =.." hexmask.long 0x50 0.--31. 1. "EINJ6_CHANGE_VALUE_H1,Packet Change Value: 2nd DWORD. Specifies replacement values for the Tx TLP header DWORD#1 bits defined in the Packet Change Point registers (EINJ6_CHANGE_POINT*). Only applies when the EINJ6_INVERTED_CONTROL field in EINJ6_TLP_REG.." line.long 0x54 "EINJ6_CHANGE_VALUE_H2_REG,Error Injection Control 6 (Change Value Header DWORD #2). Program this register for the 3rd DWORD of TLP header/prefix. It is necessary to carefully consider the endianness when you program this register. Bits [31:0] =.." hexmask.long 0x54 0.--31. 1. "EINJ6_CHANGE_VALUE_H2,Packet Change Value: 3rd DWORD. Specifies replacement values for the Tx TLP header DWORD#2 bits defined in the Packet Change Point registers (EINJ6_CHANGE_POINT*). Only applies when the EINJ6_INVERTED_CONTROL field in EINJ6_TLP_REG.." line.long 0x58 "EINJ6_CHANGE_VALUE_H3_REG,Error Injection Control 6 (Change Value Header DWORD #3). Program this register for the 4th DWORD of TLP header/prefix. It is necessary to carefully consider the endianness when you program this register. Bits [31:0] =.." hexmask.long 0x58 0.--31. 1. "EINJ6_CHANGE_VALUE_H3,Packet Change Value: 4th DWORD. Specifies replacement values for the Tx TLP header DWORD#3 bits defined in the Packet Change Point registers (EINJ6_CHANGE_POINT*). Only applies when the EINJ6_INVERTED_CONTROL field in EINJ6_TLP_REG.." line.long 0x5C "EINJ6_TLP_REG,Error Injection Control 6 (Packet Error). The Packet Compare Point registers (EINJ6_COMPARE_POINT*) specify which Tx TLP header bits to compare with the corresponding bits in the Packet Compare Value registers (EINJ6_COMPARE_VALUE*). When.." hexmask.long.tbyte 0x5C 12.--31. 1. "RSVDP_12,Reserved for future use." newline bitfld.long 0x5C 9.--11. "EINJ6_PACKET_TYPE,Packet type. Selects the TLP packets to inject errors into. - 0: TLP Header - 1: TLP Prefix 1st 4-DWORDs - 2: TLP Prefix 2nd -DWORDs - Else: Reserved Note: This register field is sticky." "TLP Header,TLP Prefix 1st 4-DWORDs,TLP Prefix 2nd -DWORDs,?,?,?,?,?" newline bitfld.long 0x5C 8. "EINJ6_INVERTED_CONTROL,Inverted Error Injection Control. - 0: EINJ6_CHANGE_VALUE_H[0/1/2/3] is used to replace bits specified by EINJ6_CHANGE_POINT_H[0/1/2/3]. - 1: EINJ6_CHANGE_VALUE_H[0/1/2/3] is ignored and inverts bits specified by.." "EINJ6_CHANGE_VALUE_H[0/1/2/3] is used to replace..,EINJ6_CHANGE_VALUE_H[0/1/2/3] is ignored and.." newline hexmask.long.byte 0x5C 0.--7. 1. "EINJ6_COUNT,Error Injection Count. Indicates the number of errors to insert. This counter is decremented while errors are been inserted. - If the counter value is 0x01 and error is inserted ERROR_INJECTION6_ENABLE in EINJ_ENABLE_REG returns '0'. - If.." group.long (0xA0+0x30C)++0x7 line.long 0x0 "SD_CONTROL1_REG,Silicon Debug Control 1. For more details. see the RAS DES section in the Core Operations chapter of the Databook." hexmask.long.byte 0x0 24.--31. 1. "RSVDP_24,Reserved for future use." newline bitfld.long 0x0 22.--23. "LOW_POWER_INTERVAL,Low Power Entry Interval Time. Interval Time that the controller starts monitoring RXELECIDLE signal after L0s/L1/L2 entry. You should set the value according to the latency from receiving EIOS to RXELECIDLE assertion at the PHY. -.." "0,1,2,3" newline bitfld.long 0x0 20.--21. "TX_EIOS_NUM,Number of Tx EIOS. This register sets the number of transmit EIOS for L0s/L1 entry and Disable/Loopback/Hot-reset exit. The controller selects the greater value between this register and the value defined by the PCI-SIG specification. 2.5GT/s.." "0,1,2,3" newline rbitfld.long 0x0 17.--19. "RSVDP_17,Reserved for future use." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 16. "FORCE_DETECT_LANE_EN,Force Detect Lane Enable. When this bit is set the controller ignores receiver detection from PHY during LTSSM Detect state and uses FORCE_DETECT_LANE. Note: This register field is sticky." "0,1" newline hexmask.long.word 0x0 0.--15. 1. "FORCE_DETECT_LANE,Force Detect Lane. When the FORCE_DETECT_LANE_EN field is set the controller ignores receiver detection from PHY during LTSSM Detect state and uses this value instead. - 0: Lane0 - 1: Lane1 - 2: Lane2 - .. - 15: Lane15 Note: This.." line.long 0x4 "SD_CONTROL2_REG,Silicon Debug Control 2. For more details. see the RAS DES section in the Core Operations chapter of the Databook." hexmask.long.word 0x4 17.--31. 1. "RSVDP_17,Reserved for future use." newline bitfld.long 0x4 16. "FRAMING_ERR_RECOVERY_DISABLE,Framing Error Recovery Disable. This bit disables a transition to Recovery state when a Framing Error is occurred. Note: This register field is sticky." "0,1" newline hexmask.long.byte 0x4 11.--15. 1. "RSVDP_11,Reserved for future use." newline bitfld.long 0x4 10. "DIRECT_LPBKSLV_TO_EXIT,Direct Loopback Slave To Exit. When this bit is set and the LTSSM is in Loopback Slave Active State the LTSSM transitions to Loopback Slave Exit state. Note: This register field is sticky." "0,1" newline bitfld.long 0x4 9. "DIRECT_POLCOMP_TO_DETECT,Direct Polling.Compliance to Detect. When this bit is set and the LTSSM is in Polling Compliance State the LTSSM transitions to Detect state. Note: This register field is sticky." "0,1" newline bitfld.long 0x4 8. "DIRECT_RECIDLE_TO_CONFIG,Direct Recovery.Idle to Configuration. When this bit is set and the LTSSM is in Recovery Idle State the LTSSM transitions to Configuration state. Note: This register field is sticky." "0,1" newline hexmask.long.byte 0x4 3.--7. 1. "RSVDP_3,Reserved for future use." newline bitfld.long 0x4 2. "NOACK_FORCE_LINKDOWN,Force LinkDown. When this bit is set and the controller detects REPLY_NUM rolling over 4 times the LTSSM transitions to Detect State. Note: This register field is sticky." "0,1" newline bitfld.long 0x4 1. "RECOVERY_REQUEST,Recovery Request. When this bit is set to '1' in L0 or L0s the LTSSM starts transitioning to Recovery State. This request does not cause a speed change or re-equalization." "0,1" newline bitfld.long 0x4 0. "HOLD_LTSSM,Hold and Release LTSSM. For as long as this register is '1' the controller stays in the current LTSSM. Note: This register field is sticky." "0,1" group.long (0xB0+0x30C)++0xB line.long 0x0 "SD_STATUS_L1LANE_REG,Silicon Debug Status(Layer1 Per-lane). This viewport register returns the data selected by the following field: - LANE_SELECT in SD_STATUS_L1LANE_REG For more details. see the RAS DES section in the Core Operations chapter of the.." hexmask.long.byte 0x0 24.--31. 1. "DESKEW_POINTER,Deskew Pointer. Indicates Deskew pointer of internal Deskew buffer of selected lane number(LANE_SELECT). Note: This register field is sticky." newline rbitfld.long 0x0 21.--23. "RSVDP_21,Reserved for future use." "0,1,2,3,4,5,6,7" newline rbitfld.long 0x0 20. "PIPE_TXELECIDLE,PIPE:TxElecIdle. Indicates PIPE TXELECIDLE signal of selected lane number(LANE_SELECT). Note: This register field is sticky." "0,1" newline rbitfld.long 0x0 19. "PIPE_RXELECIDLE,PIPE:RxElecIdle. Indicates PIPE RXELECIDLE signal of selected lane number(LANE_SELECT). Note: This register field is sticky." "0,1" newline rbitfld.long 0x0 18. "PIPE_RXVALID,PIPE:RxValid. Indicates PIPE RXVALID signal of selected lane number(LANE_SELECT). Note: This register field is sticky." "0,1" newline rbitfld.long 0x0 17. "PIPE_DETECT_LANE,PIPE:Detect Lane. Indicates whether PHY indicates receiver detection or not on selected lane number(LANE_SELECT). Note: This register field is sticky." "0,1" newline rbitfld.long 0x0 16. "PIPE_RXPOLARITY,PIPE:RxPolarity. Indicates PIPE RXPOLARITY signal of selected lane number(LANE_SELECT). Note: This register field is sticky." "0,1" newline hexmask.long.word 0x0 4.--15. 1. "RSVDP_4,Reserved for future use." newline hexmask.long.byte 0x0 0.--3. 1. "LANE_SELECT,Lane Select. Lane Select register for Silicon Debug Status Register of Layer1-PerLane. - 0x0: Lane0 - 0x1: Lane1 - 0x2: Lane2 - .. - 0xF: Lane15 Note: This register field is sticky." line.long 0x4 "SD_STATUS_L1LTSSM_REG,Silicon Debug Status(Layer1 LTSSM). For more details. see the RAS DES section in the Core Operations chapter of the Databook." hexmask.long.word 0x4 16.--31. 1. "LTSSM_VARIABLE,LTSSM Variable. Indicates internal LTSSM variables defined in the PCI Express Base Specification. C-PCIe Mode: - 0: directed_speed_change - 1: changed_speed_recovery - 2: successful_speed_negotiation - 3: upconfigure_capable; Set to '1' if.." newline rbitfld.long 0x4 15. "LANE_REVERSAL,Lane Reversal Operation. Receiver detected lane reversal. This field is only valid in the L0 LTSSM state. Note: This register field is sticky." "0,1" newline hexmask.long.byte 0x4 11.--14. 1. "RSVDP_11,Reserved for future use." newline rbitfld.long 0x4 8.--10. "PIPE_POWER_DOWN,PIPE:PowerDown. Indicates PIPE PowerDown signal. Note: This register field is sticky." "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 7. "FRAMING_ERR,Framing Error. Indicates Framing Error detection status." "0,1" newline hexmask.long.byte 0x4 0.--6. 1. "FRAMING_ERR_PTR,First Framing Error Pointer. Identifies the first Framing Error using the following encoding. The field contents are only valid value when FRAMING_ERR =1. Received Unexpected Framing Token - 01h: When non- STP/SDP/IDL Token was received.." line.long 0x8 "SD_STATUS_PM_REG,Silicon Debug Status(PM). For more details. see the RAS DES section in the Core Operations chapter of the Databook." hexmask.long.byte 0x8 24.--31. 1. "RSVDP_24,Reserved for future use." newline hexmask.long.byte 0x8 16.--23. 1. "LATCHED_NFTS,Latched N_FTS. Indicates the value of N_FTS in the received TS Ordered Sets from the Link Partner Note: This register field is sticky." newline rbitfld.long 0x8 13.--15. "L1SUB_STATE,L1Sub State. Indicates internal state machine of L1Sub state. - 0h: S_L1_U : idle state - 1h: S_L1_0 : wait for aux_clk_active - 2h: S_L1_0_WAIT4_ACK : wait for pclkack - 3h: S_L1_0_WAIT4_CLKREQ : wait for clkreq - 4h: S_L1_N_ENTRY : check.." "wait for aux_clk_active,?,?,?,?,?,?,?" newline bitfld.long 0x8 12. "PME_RESEND_FLAG,PME Re-send flag. When the DUT sends a PM_PME message TLP the DUT sets PME_Status bit. If host software does not clear PME_Status bit for 100ms(+50%/-5%) the DUT resends the PM_PME Message. This bit indicates that a PM_PME was resent." "0,1" newline hexmask.long.byte 0x8 8.--11. 1. "INTERNAL_PM_SSTATE,Internal PM State(Slave). Indicates internal state machine of Power Management Slave controller. - 0h: S_IDLE - 1h: S_RESPOND_NAK - 2h: S_BLOCK_TLP - 3h: S_WAIT_LAST_TLP_ACK - 4h: S_WAIT_EIDLE - 5h: S_LINK_ENTR_L1 - 6h: S_L1 - 7h:.." newline rbitfld.long 0x8 5.--7. "RSVDP_5,Reserved for future use." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x8 0.--4. 1. "INTERNAL_PM_MSTATE,Internal PM State(Master). Indicates internal state machine of Power Management Master controller. - 00h: IDLE - 01h: L0 - 02h: L0S - 03h: ENTER_L0S - 04h: L0S_EXIT - 05h: WAIT_PMCSR_CPL_SENT - 08h: L1 - 09h: L1_BLOCK_TLP - 0Ah:.." rgroup.long (0xBC+0x30C)++0x3 line.long 0x0 "SD_STATUS_L2_REG,Silicon Debug Status(Layer2). For more details. see the RAS DES section in the Core Operations chapter of the Databook." hexmask.long.byte 0x0 28.--31. 1. "RSVDP_28,Reserved for future use." newline bitfld.long 0x0 27. "FC_INIT2,FC_INIT2. Indicates the controller is in FC_INIT2(VC0) state. Note: This register field is sticky." "0,1" newline bitfld.long 0x0 26. "FC_INIT1,FC_INIT1. Indicates the controller is in FC_INIT1(VC0) state. Note: This register field is sticky." "0,1" newline bitfld.long 0x0 24.--25. "DLCMSM,DLCMSM. Indicates the current DLCMSM. - 00b: DL_INACTIVE - 01b: DL_FC_INIT - 11b: DL_ACTIVE Note: This register field is sticky." "0,1,2,3" newline hexmask.long.word 0x0 12.--23. 1. "RX_ACK_SEQ_NO,Tx Ack Sequence Number. Indicates ACKD_SEQ which is updated by receiving ACK/NAK DLLP. Note: This register field is sticky." newline hexmask.long.word 0x0 0.--11. 1. "TX_TLP_SEQ_NO,Tx Tlp Sequence Number. Indicates next transmit sequence number for transmit TLP. Note: This register field is sticky." group.long (0xC0+0x30C)++0x7 line.long 0x0 "SD_STATUS_L3FC_REG,Silicon Debug Status(Layer3 FC). The CREDIT_DATA[0/1] fields in this viewport register return the data for the VC and TLP Type selected by the following fields: - CREDIT_SEL_VC - CREDIT_SEL_CREDIT_TYPE - CREDIT_SEL_TLP_TYPE -.." hexmask.long.word 0x0 20.--31. 1. "CREDIT_DATA1,Credit Data1. Current FC credit data selected by the CREDIT_SEL_VC CREDIT_SEL_CREDIT_TYPE CREDIT_SEL_TLP_TYPE and CREDIT_SEL_HD viewport-select fields. - Rx: Credit Allocated Value - Tx: Credit Limit Value. This value is valid when.." newline hexmask.long.word 0x0 8.--19. 1. "CREDIT_DATA0,Credit Data0. Current FC credit data selected by the CREDIT_SEL_VC CREDIT_SEL_CREDIT_TYPE CREDIT_SEL_TLP_TYPE and CREDIT_SEL_HD viewport-select fields. - Rx: Credit Received Value - Tx: Credit Consumed Value Note: This register field is.." newline rbitfld.long 0x0 7. "RSVDP_7,Reserved for future use." "0,1" newline bitfld.long 0x0 6. "CREDIT_SEL_HD,Credit Select(HeaderData). This field in conjunction with the CREDIT_SEL_VC CREDIT_SEL_CREDIT_TYPE and CREDIT_SEL_TLP_TYPE viewport-select fields determines that data that is returned by the CREDIT_DATA0 and CREDIT_DATA1 data fields. -.." "Header Credit,Data Credit" newline bitfld.long 0x0 4.--5. "CREDIT_SEL_TLP_TYPE,Credit Select(TLP Type). This field in conjunction with the CREDIT_SEL_VC CREDIT_SEL_CREDIT_TYPE and CREDIT_SEL_HD viewport-select fields determines that data that is returned by the CREDIT_DATA0 and CREDIT_DATA1 data fields. - 0x0:.." "Posted,Non-Posted,Completion,?" newline bitfld.long 0x0 3. "CREDIT_SEL_CREDIT_TYPE,Credit Select(Credit Type). This field in conjunction with the CREDIT_SEL_VC CREDIT_SEL_TLP_TYPE and CREDIT_SEL_HD viewport-select fields determines that data that is returned by the CREDIT_DATA0 and CREDIT_DATA1 data fields. -.." "Rx,Tx" newline bitfld.long 0x0 0.--2. "CREDIT_SEL_VC,Credit Select(VC). This field in conjunction with the CREDIT_SEL_CREDIT_TYPE CREDIT_SEL_TLP_TYPE and CREDIT_SEL_HD viewport-select fields determines that data that is returned by the CREDIT_DATA0 and CREDIT_DATA1 data fields. - 0x0: VC0 -.." "VC0,VC1,VC2,?,?,?,?,VC7" line.long 0x4 "SD_STATUS_L3_REG,Silicon Debug Status(Layer3). For more details. see the RAS DES section in the Core Operations chapter of the Databook." hexmask.long.tbyte 0x4 8.--31. 1. "RSVDP_8,Reserved for future use." newline bitfld.long 0x4 7. "MFTLP_STATUS,Malformed TLP Status. Indicates malformed TLP has occurred." "0,1" newline hexmask.long.byte 0x4 0.--6. 1. "MFTLP_POINTER,First Malformed TLP Error Pointer. Indicates the element of the received first malformed TLP. This pointer is validated by MFTLP_STATUS. - 01h: AtomicOp address alignment - 02h: AtomicOp operand - 03h: AtomicOp byte enable - 04h: TLP length.." group.long (0xD0+0x30C)++0xB line.long 0x0 "SD_EQ_CONTROL1_REG,Silicon Debug EQ Control 1. This is a viewport control register. Setting the EQ_RATE_SEL and EQ_LANE_SEL fields in this register determine the per-lane Silicon Debug EQ Status data returned by the SD_EQ_STATUS[1/2/3] viewport.." hexmask.long.byte 0x0 24.--31. 1. "FOM_TARGET,FOM Target. Indicates figure of merit target criteria value of EQ Master(DSP in EQ Phase3/USP in EQ Phase2). This field is only valid when GEN3_EQ_FB_MODE is 0001b(Figure Of Merit). Note: This register field is sticky." newline bitfld.long 0x0 23. "FOM_TARGET_ENABLE,FOM Target Enable. Enables the FOM_TARGET fields. Note: This register field is sticky." "0,1" newline hexmask.long.byte 0x0 18.--22. 1. "RSVDP_18,Reserved for future use." newline bitfld.long 0x0 16.--17. "EVAL_INTERVAL_TIME,Eval Interval Time. Indicates interval time of RxEqEval assertion. - 00: 500ns - 01: 1us - 10: 2us - 11: 4us This field is used for EQ Master(DSP in EQ Phase3/USP in EQ Phase2). Note: This register field is sticky." "0,1,2,3" newline hexmask.long.byte 0x0 10.--15. 1. "RSVDP_10,Reserved for future use." newline bitfld.long 0x0 8.--9. "EXT_EQ_TIMEOUT,Extends EQ Phase2/3 Timeout. This field is used when the Ltssm is in Recovery.EQ2/3. When this field is set the value of EQ2/3 timeout is extended. EQ Master(DSP in EQ Phase3/USP in EQ Phase2). - 00: 24ms (default) - 01: 48ms (x2) - 10:.." "0,1,2,3" newline rbitfld.long 0x0 6.--7. "RSVDP_6,Reserved for future use." "0,1,2,3" newline bitfld.long 0x0 4.--5. "EQ_RATE_SEL,EQ Status Rate Select. Setting this field in conjunction with the EQ_LANE_SEL field determines the per-lane Silicon Debug EQ Status data returned by the SD_EQ_CONTROL[2/3] and SD_EQ_STATUS[1/2/3] viewport registers. - 0x0: 8.0GT/s Speed.." "0,1,2,3" newline hexmask.long.byte 0x0 0.--3. 1. "EQ_LANE_SEL,EQ Status Lane Select. Setting this field in conjunction with the EQ_RATE_SEL field determines the per-lane Silicon Debug EQ Status data returned by the SD_EQ_CONTROL[2/3] and SD_EQ_STATUS[1/2/3] viewport registers. - 0x0: Lane0 - 0x1: Lane1.." line.long 0x4 "SD_EQ_CONTROL2_REG,Silicon Debug EQ Control 2. This viewport register returns the value for the rate and lane selected by the EQ_RATE_SEL and EQ_LANE_SEL fields in the SD_EQ_CONTROL1_REG register. For more details. see the RAS DES section in the Core.." rbitfld.long 0x4 31. "RSVDP_31,Reserved for future use." "0,1" newline bitfld.long 0x4 30. "FORCE_LOCAL_TX_PRESET_ENABLE,Force Local Transmitter Preset Enable. Enables the FORCE_LOCAL_TX_PRESET field. If select rate in the EQ_RATE_SEL field is 32.0GT/s Speed this feature is not available. Note: This register field is sticky." "0,1" newline bitfld.long 0x4 29. "FORCE_LOCAL_RX_HINT_ENABLE,Force Local Receiver Preset Hint Enable. Enables the FORCE_LOCAL_RX_HINT field. If select rate in the EQ_RATE_SEL field is other than 8.0GT/s Speed this feature is not available. Note: This register field is sticky." "0,1" newline bitfld.long 0x4 28. "FORCE_LOCAL_TX_COEF_ENABLE,Force Local Transmitter Coefficient Enable. Enables the following fields: - FORCE_LOCAL_TX_PRE_CURSOR - FORCE_LOCAL_TX_CURSOR - FORCE_LOCAL_TX_POST_CURSOR Note: This register field is sticky." "0,1" newline hexmask.long.byte 0x4 24.--27. 1. "FORCE_LOCAL_TX_PRESET,Force Local Transmitter Preset. Indicates initial preset value of USP in EQ Slave(EQ Phase2) instead of receiving EQ TS2. If select rate in the EQ_RATE_SEL field is 32.0GT/s Speed this feature is not available. Note: This register.." newline rbitfld.long 0x4 21.--23. "RSVDP_21,Reserved for future use." "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 18.--20. "FORCE_LOCAL_RX_HINT,Force Local Receiver Preset Hint. Indicates the RxPresetHint value of EQ Slave(DSP in EQ Phase2/USP in EQ Phase3) instead of received or set value. If select rate in the EQ_RATE_SEL field is other than 8.0GT/s Speed this feature is.." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x4 12.--17. 1. "FORCE_LOCAL_TX_POST_CURSOR,Force Local Transmitter Post-Cursor. Indicates the coefficient value of EQ Slave(DSP in EQ Phase2/USP in EQ Phase3) instead of the value instructed from link partner. Note: This register field is sticky." newline hexmask.long.byte 0x4 6.--11. 1. "FORCE_LOCAL_TX_CURSOR,Force Local Transmitter Cursor. Indicates the coefficient value of EQ Slave(DSP in EQ Phase2/USP in EQ Phase3) instead of the value instructed from link partner. Note: This register field is sticky." newline hexmask.long.byte 0x4 0.--5. 1. "FORCE_LOCAL_TX_PRE_CURSOR,Force Local Transmitter Pre-cursor. Indicates the coefficient value of EQ Slave(DSP in EQ Phase2/USP in EQ Phase3) instead of the value instructed from link partner. Note: This register field is sticky." line.long 0x8 "SD_EQ_CONTROL3_REG,Silicon Debug EQ Control 3. This viewport register returns the value for the rate and lane selected by the EQ_RATE_SEL and EQ_LANE_SEL fields in the SD_EQ_CONTROL1_REG register. For more details. see the RAS DES section in the Core.." rbitfld.long 0x8 29.--31. "RSVDP_29,Reserved for future use." "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 28. "FORCE_REMOTE_TX_COEF_ENABLE,Force Remote Transmitter Coefficient Enable. Enables the following fields: - FORCE_REMOTE_TX_PRE_CURSOR - FORCE_REMOTE_TX_CURSOR - FORCE_REMOTE_TX_POST_CURSOR This function can only be used when GEN3_EQ_FB_MODE =.." "0,1" newline hexmask.long.word 0x8 18.--27. 1. "RSVDP_18,Reserved for future use." newline hexmask.long.byte 0x8 12.--17. 1. "FORCE_REMOTE_TX_POST_CURSOR,Force Remote Transmitter Post-Cursor. Indicates the coefficient value of EQ Master(DSP in EQ Phase3/USP in EQ Phase2) instead of the value instructed from local phy in dirchange mode. Note: This register field is sticky." newline hexmask.long.byte 0x8 6.--11. 1. "FORCE_REMOTE_TX_CURSOR,Force Remote Transmitter Cursor. Indicates the coefficient value of EQ Master(DSP in EQ Phase3/USP in EQ Phase2) instead of the value instructed from local phy in dirchange mode. Note: This register field is sticky." newline hexmask.long.byte 0x8 0.--5. 1. "FORCE_REMOTE_TX_PRE_CURSOR,Force Remote Transmitter Pre-Cursor. Indicates the coefficient value of EQ Master(DSP in EQ Phase3/USP in EQ Phase2) instead of the value instructed from local phy in dirchange mode. Note: This register field is sticky." rgroup.long (0xE0+0x30C)++0xB line.long 0x0 "SD_EQ_STATUS1_REG,Silicon Debug EQ Status 1. This viewport register returns the first of three words of Silicon Debug EQ Status data for the rate and lane selected by the EQ_RATE_SEL and EQ_LANE_SEL fields in the SD_EQ_CONTROL1_REG register. The.." hexmask.long.tbyte 0x0 8.--31. 1. "RSVDP_8,Reserved for future use." newline bitfld.long 0x0 7. "EQ_REJECT_EVENT,EQ Reject Event. Indicates that the controller receives two consecutive TS1 OS w/Reject=1b during EQ Master phase(DSP in EQ Phase3/USP in EQ Phase2). This bit is automatically cleared when the controller starts EQ Master phase again." "0,1" newline bitfld.long 0x0 6. "EQ_RULEC_VIOLATION,EQ Rule C Violation. Indicates that coefficients rule C violation is detected in the values provided by PHY using direction change method during EQ Master phase(DSP in EQ Phase3/USP in EQ Phase2). The coefficients rule C correspond to.." "0,1" newline bitfld.long 0x0 5. "EQ_RULEB_VIOLATION,EQ Rule B Violation. Indicates that coefficients rule B violation is detected in the values provided by PHY using direction change method during EQ Master phase(DSP in EQ Phase3/USP in EQ Phase2). The coefficients rules B correspond to.." "0,1" newline bitfld.long 0x0 4. "EQ_RULEA_VIOLATION,EQ Rule A Violation. Indicates that coefficients rule A violation is detected in the values provided by PHY using direction change method during EQ Master phase(DSP in EQ Phase3/USP in EQ Phase2). The coefficients rules A correspond to.." "0,1" newline bitfld.long 0x0 3. "RSVDP_3,Reserved for future use." "0,1" newline bitfld.long 0x0 1.--2. "EQ_CONVERGENCE_INFO,EQ Convergence Info. Indicates equalization convergence information. - 0x0: Equalization is not attempted - 0x1: Equalization finished successfully - 0x2: Equalization finished unsuccessfully - 0x3: Reserved This bit is automatically.." "Equalization is not attempted,Equalization finished successfully,Equalization finished unsuccessfully,Reserved" newline bitfld.long 0x0 0. "EQ_SEQUENCE,EQ Sequence. Indicates that the controller is starting the equalization sequence. Note: This register field is sticky." "0,1" line.long 0x4 "SD_EQ_STATUS2_REG,Silicon Debug EQ Status 2. This viewport register returns the second of three words of Silicon Debug EQ Status data for the rate and lane selected by the EQ_RATE_SEL and EQ_LANE_SEL fields in the SD_EQ_CONTROL1_REG register. Each field.." hexmask.long.byte 0x4 24.--31. 1. "EQ_LOCAL_FOM_VALUE,EQ Local Figure of Merit. Indicates Local maximum Figure of Merit value. Note: This register field is sticky." newline bitfld.long 0x4 21.--23. "RSVDP_21,Reserved for future use." "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 18.--20. "EQ_LOCAL_RX_HINT,EQ Local Receiver Preset Hint. Indicates Local Receiver Preset Hint value. If select rate in the EQ_RATE_SEL field is other than 8.0GT/s Speed this feature is not available. Note: This register field is sticky." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x4 12.--17. 1. "EQ_LOCAL_POST_CURSOR,EQ Local Post-Cursor. Indicates Local post cursor coefficient value. Note: This register field is sticky." newline hexmask.long.byte 0x4 6.--11. 1. "EQ_LOCAL_CURSOR,EQ Local Cursor. Indicates Local cursor coefficient value. Note: This register field is sticky." newline hexmask.long.byte 0x4 0.--5. 1. "EQ_LOCAL_PRE_CURSOR,EQ Local Pre-Cursor. Indicates Local pre cursor coefficient value. Note: This register field is sticky." line.long 0x8 "SD_EQ_STATUS3_REG,Silicon Debug EQ Status 3. This viewport register returns the third of three words of Silicon Debug EQ Status data for the rate and lane selected by the EQ_RATE_SEL and EQ_LANE_SEL fields in the SD_EQ_CONTROL1_REG register. Each field.." bitfld.long 0x8 30.--31. "RSVDP_30,Reserved for future use." "0,1,2,3" newline hexmask.long.byte 0x8 24.--29. 1. "EQ_REMOTE_FS,EQ Remote FS. Indicates Remote FS value. Note: This register field is sticky." newline hexmask.long.byte 0x8 18.--23. 1. "EQ_REMOTE_LF,EQ Remote LF. Indicates Remote LF value. Note: This register field is sticky." newline hexmask.long.byte 0x8 12.--17. 1. "EQ_REMOTE_POST_CURSOR,EQ Remote Post-Cursor. Indicates Remote post cursor coefficient value. Note: This register field is sticky." newline hexmask.long.byte 0x8 6.--11. 1. "EQ_REMOTE_CURSOR,EQ Remote Cursor. Indicates Remote cursor coefficient value. Note: This register field is sticky." newline hexmask.long.byte 0x8 0.--5. 1. "EQ_REMOTE_PRE_CURSOR,EQ Remote Pre-Cursor. Indicates Remote pre cursor coefficient value. Note: This register field is sticky." tree.end tree "PF0_SN_CAP (Device Serial Number Capability Structure)" group.long (0x0+0x170)++0xB line.long 0x0 "SN_BASE,Device Serial Number Extended Capability Header. For a description of this standard PCIe register. see the PCI Express Base Specification." hexmask.long.word 0x0 20.--31. 1. "SN_NEXT_OFFSET,Next Capability Offset. For a description of this standard PCIe register field see the PCI Express Base Specification. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then.." hexmask.long.byte 0x0 16.--19. 1. "SN_CAP_VERSION,Capability Version. For a description of this standard PCIe register field see the PCI Express Base Specification. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky).." hexmask.long.word 0x0 0.--15. 1. "SN_PCIE_EXTENDED_CAP_ID,Serial Number Extended Capability ID. For a description of this standard PCIe register field see the PCI Express Base Specification. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if.." line.long 0x4 "SER_NUM_REG_DW_1,Serial Number 1 Register. For a description of this standard PCIe register. see the PCI Express Base Specification." hexmask.long 0x4 0.--31. 1. "SN_SER_NUM_REG_1_DW,IEEE 64 bit Device Serial Number (DW 1). For a description of this standard PCIe register field see the PCI Express Base Specification. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if.." line.long 0x8 "SER_NUM_REG_DW_2,Serial Number 2 Register. For a description of this standard PCIe register. see the PCI Express Base Specification." hexmask.long 0x8 0.--31. 1. "SN_SER_NUM_REG_2_DW,IEEE 64 bit Device Serial Number (DW 2). For a description of this standard PCIe register field see the PCI Express Base Specification. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if.." tree.end tree "PF0_VSECRAS_CAP (PF RAS Datapath Protection Capability Structure (VSEC))" group.long (0x0+0x480)++0x3 line.long 0x0 "RASDP_EXT_CAP_HDR_OFF,PCIe Extended capability ID. Capability version and Next capability offset. For a description of this standard PCIe register. see the PCI Express Specification." hexmask.long.word 0x0 20.--31. 1. "NEXT_OFFSET,Next Capability Offset. For a description of this standard PCIe register see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else.." newline hexmask.long.byte 0x0 16.--19. 1. "CAP,Capability Version. For a description of this standard PCIe register see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note:.." newline hexmask.long.word 0x0 0.--15. 1. "ID,PCI Express Extended Capability ID. For a description of this standard PCIe register see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else.." rgroup.long (0x4+0x480)++0x3 line.long 0x0 "RASDP_VENDOR_SPECIFIC_HDR_OFF,Vendor Specific Header. For a description of this standard PCIe register. see the PCI Express Specification." hexmask.long.word 0x0 20.--31. 1. "VSEC_LENGTH,VSEC Length. For a description of this standard PCIe register see the PCI Express Specification. Note: This register field is sticky." newline hexmask.long.byte 0x0 16.--19. 1. "VSEC_REV,VSEC Rev. For a description of this standard PCIe register see the PCI Express Specification. Note: This register field is sticky." newline hexmask.long.word 0x0 0.--15. 1. "VSEC_ID,VSEC ID. For a description of this standard PCIe register see the PCI Express Specification. Note: This register field is sticky." group.long (0x8+0x480)++0x7 line.long 0x0 "RASDP_ERROR_PROT_CTRL_OFF,ECC error correction control. Allows you to disable ECC error correction for RAMs and datapath. When the AXI Bridge Module is implemented and the master / slave clocks are asynchronous to the PCIe native controller clock.." hexmask.long.byte 0x0 24.--31. 1. "RSVDP_24,Reserved for future use." newline bitfld.long 0x0 23. "ERROR_PROT_DISABLE_CXS_RX,Error correction disable for CXS Tx path (PCIe Rx path). Note: This register field is sticky." "0,1" newline bitfld.long 0x0 22. "ERROR_PROT_DISABLE_ADM_RX,Error correction disable for ADM Rx path. Note: This register field is sticky." "0,1" newline bitfld.long 0x0 21. "ERROR_PROT_DISABLE_LAYER3_RX,Error correction disable for layer 3 Rx path. Note: This register field is sticky." "0,1" newline bitfld.long 0x0 20. "ERROR_PROT_DISABLE_LAYER2_RX,Error correction disable for layer 2 Rx path. Note: This register field is sticky." "0,1" newline bitfld.long 0x0 19. "ERROR_PROT_DISABLE_DMA_READ,Error correction disable for DMA read engine. Note: This register field is sticky." "0,1" newline bitfld.long 0x0 18. "ERROR_PROT_DISABLE_AXI_BRIDGE_INBOUND_REQUEST,Error correction disable for AXI bridge inbound request path. Note: This register field is sticky." "0,1" newline bitfld.long 0x0 17. "ERROR_PROT_DISABLE_AXI_BRIDGE_INBOUND_COMPLETION,Error correction disable for AXI bridge inbound completion composer. Does not disable the error detection reporting for 1-bit and 2-bit ECC errors. Note: This register field is sticky." "?,bit and 2-bit ECC errors" newline bitfld.long 0x0 16. "ERROR_PROT_DISABLE_RX,Global error correction disable for all Rx layers. Note: This register field is sticky." "0,1" newline hexmask.long.byte 0x0 9.--15. 1. "RSVDP_9,Reserved for future use." newline bitfld.long 0x0 8. "ERROR_PROT_DISABLE_DTIM_TX,Error correction disable for DTIM Tx path. Note: This register field is sticky." "0,1" newline bitfld.long 0x0 7. "ERROR_PROT_DISABLE_CXS_TX,Error correction disable for CXS Rx path (PCIe Tx path). Note: This register field is sticky." "0,1" newline bitfld.long 0x0 6. "ERROR_PROT_DISABLE_ADM_TX,Error correction disable for Adm Tx path. Note: This register field is sticky." "0,1" newline bitfld.long 0x0 5. "ERROR_PROT_DISABLE_LAYER3_TX,Error correction disable for layer 3 Tx path. Note: This register field is sticky." "0,1" newline bitfld.long 0x0 4. "ERROR_PROT_DISABLE_LAYER2_TX,Error correction disable for layer 2 Tx path. Note: This register field is sticky." "0,1" newline bitfld.long 0x0 3. "ERROR_PROT_DISABLE_DMA_WRITE,Error correction disable for DMA write engine. Note: This register field is sticky." "0,1" newline bitfld.long 0x0 2. "ERROR_PROT_DISABLE_AXI_BRIDGE_OUTBOUND,Error correction disable for AXI bridge outbound request path. Note: This register field is sticky." "0,1" newline bitfld.long 0x0 1. "ERROR_PROT_DISABLE_AXI_BRIDGE_MASTER,Error correction disable for AXI bridge master completion buffer. Note: This register field is sticky." "0,1" newline bitfld.long 0x0 0. "ERROR_PROT_DISABLE_TX,Global error correction disable for all Tx layers. Does not disable the error detection reporting for 1-bit and 2-bit ECC errors. Note: This register field is sticky." "?,bit and 2-bit ECC errors" line.long 0x4 "RASDP_CORR_COUNTER_CTRL_OFF,Corrected error (1-bit ECC) counter selection and control. This is a viewport control register. Setting the CORR_COUNTER_SELECTION_REGION and CORR_COUNTER_SELECTION fields in this register determine the counter data returned.." hexmask.long.byte 0x4 24.--31. 1. "CORR_COUNTER_SELECTION,Counter selection. This field selects the counter ID (within the region defined by CORR_COUNTER_SELECTION_REGION) whose contents can be read from the RASDP_CORR_COUNT_REPORT_OFF register. You can cycle this field value from 0 to.." newline hexmask.long.byte 0x4 20.--23. 1. "CORR_COUNTER_SELECTION_REGION,Select correctable counter region: - 0x0: Region select for Adm Rx path - 0x1: Region select for layer 3 Rx path - 0x2: Region select for layer 2 Rx path - 0x3: Region select for DMA inbound path - 0x4: Region select for AXI.." newline hexmask.long.word 0x4 5.--19. 1. "RSVDP_5,Reserved for future use." newline bitfld.long 0x4 4. "CORR_EN_COUNTERS,Enable correctable errors counters. - 1: counters increment when the controller detects a correctable error - 0: counters are frozen The counters are enabled by default." "counters are frozen,counters increment when the controller detects a.." newline rbitfld.long 0x4 1.--3. "RSVDP_1,Reserved for future use." "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 0. "CORR_CLEAR_COUNTERS,Clear all correctable error counters." "0,1" rgroup.long (0x10+0x480)++0x3 line.long 0x0 "RASDP_CORR_COUNT_REPORT_OFF,Corrected error (1-bit ECC) counter data. This viewport register returns the counter data selected by the CORR_COUNTER_SELECTION_REGION and CORR_COUNTER_SELECTION fields in the RASDP_CORR_COUNTER_CTRL_OFF register." hexmask.long.byte 0x0 24.--31. 1. "CORR_COUNTER_SELECTED,Counter selection. Returns the value set in the CORR_COUNTER_SELECTION field of the RASDP_CORR_COUNTER_CTRL_OFF register." newline hexmask.long.byte 0x0 20.--23. 1. "CORR_COUNTER_SELECTED_REGION,Selected correctable counter region: - 0x0: Region select for Adm Rx path - 0x1: Region select for layer 3 Rx path - 0x2: Region select for layer 2 Rx path - 0x3: Region select for DMA inbound path - 0x4: Region select for.." newline hexmask.long.word 0x0 8.--19. 1. "RSVDP_8,Reserved for future use." newline hexmask.long.byte 0x0 0.--7. 1. "CORR_COUNTER,Current corrected error count for the selected counter." group.long (0x14+0x480)++0x3 line.long 0x0 "RASDP_UNCORR_COUNTER_CTRL_OFF,Uncorrected error (2-bit ECC and parity) counter selection and control. This is a viewport control register. Setting the UNCORR_COUNTER_SELECTION_REGION and UNCORR_COUNTER_SELECTION fields in this register determine the.." hexmask.long.byte 0x0 24.--31. 1. "UNCORR_COUNTER_SELECTION,Counter selection. This field selects the counter ID (within the region defined by UNCORR_COUNTER_SELECTION_REGION) whose contents can be read from the RASDP_UNCORR_COUNT_REPORT_OFF register. You can cycle this field value from 0.." newline hexmask.long.byte 0x0 20.--23. 1. "UNCORR_COUNTER_SELECTION_REGION,Select uncorrectable counter region: - 0x0: Region select for Adm Rx path - 0x1: Region select for layer 3 Rx path - 0x2: Region select for layer 2 Rx path - 0x3: Region select for DMA inbound path - 0x4: Region select for.." newline hexmask.long.word 0x0 5.--19. 1. "RSVDP_5,Reserved for future use." newline bitfld.long 0x0 4. "UNCORR_EN_COUNTERS,Enable uncorrectable errors counters. - 1: enables the counters to increment on detected correctable errors - 0: counters are frozen The counters are enabled by default." "counters are frozen,enables the counters to increment on detected.." newline rbitfld.long 0x0 1.--3. "RSVDP_1,Reserved for future use." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 0. "UNCORR_CLEAR_COUNTERS,Clear uncorrectable errors counters. When asserted causes all counters tracking the uncorrectable errors to be cleared." "0,1" rgroup.long (0x18+0x480)++0x3 line.long 0x0 "RASDP_UNCORR_COUNT_REPORT_OFF,Uncorrected error (2-bit ECC and parity) counter data. This viewport register returns the counter data selected by the UNCORR_COUNTER_SELECTION_REGION and UNCORR_COUNTER_SELECTION fields in the RASDP_UNCORR_COUNTER_CTRL_OFF.." hexmask.long.byte 0x0 24.--31. 1. "UNCORR_COUNTER_SELECTED,Counter selection. Returns the value set in the UNCORR_COUNTER_SELECTION field of the RASDP_UNCORR_COUNTER_CTRL_OFF register." newline hexmask.long.byte 0x0 20.--23. 1. "UNCORR_COUNTER_SELECTED_REGION,Selected uncorrectable counter region: - 0x0: Region select for Adm Rx path - 0x1: Region select for layer 3 Rx path - 0x2: Region select for layer 2 Rx path - 0x3: Region select for DMA inbound path - 0x4: Region select.." newline hexmask.long.word 0x0 8.--19. 1. "RSVDP_8,Reserved for future use." newline hexmask.long.byte 0x0 0.--7. 1. "UNCORR_COUNTER,Current uncorrected error count for the selected counter" group.long (0x1C+0x480)++0x3 line.long 0x0 "RASDP_ERROR_INJ_CTRL_OFF,Error injection control for the following features: - 1-bit or 2-bit injection - Continuous or fixed-number (n) injection modes - Global enable/disable - Selectable location where injection occurs" hexmask.long.byte 0x0 24.--31. 1. "RSVDP_24,Reserved for future use." newline hexmask.long.byte 0x0 16.--23. 1. "ERROR_INJ_LOC,Error injection location. Selects where error injection takes place. You can cycle this field value from 0 to 255 to access all locations according to the detailed report of check points at.." newline hexmask.long.byte 0x0 8.--15. 1. "ERROR_INJ_COUNT,Error injection count. - 0: errors are inserted in every TLP until you clear ERROR_INJ_EN. - 1: one errors injected - 2: two errors injected - n: amount of errors injected" newline rbitfld.long 0x0 6.--7. "RSVDP_6,Reserved for future use." "0,1,2,3" newline bitfld.long 0x0 4.--5. "ERROR_INJ_TYPE,Error injection type: - 0: none - 1: 1-bit - 2: 2-bit" "none,bit,bit,?" newline rbitfld.long 0x0 1.--3. "RSVDP_1,Reserved for future use." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 0. "ERROR_INJ_EN,Error injection global enable. When set enables the error insertion logic." "0,1" rgroup.long (0x20+0x480)++0x7 line.long 0x0 "RASDP_CORR_ERROR_LOCATION_OFF,Corrected errors locations. For more details. see the RAS Data Protection (DP) section in the Core Operations chapter of the Databook." hexmask.long.byte 0x0 24.--31. 1. "LOC_LAST_CORR_ERROR,Location/ID of the last corrected error within the region defined by REG_LAST_CORR_ERROR. You can cycle this field value from 0 to 255 to access all counters according to the detailed report of check points at.." newline hexmask.long.byte 0x0 20.--23. 1. "REG_LAST_CORR_ERROR,Region of the last corrected error: - 0x0: Region select for Adm Rx path - 0x1: Region select for layer 3 Rx path - 0x2: Region select for layer 2 Rx path - 0x3: Region select for DMA inbound path - 0x4: Region select for AXI bridge.." newline hexmask.long.byte 0x0 16.--19. 1. "RSVDP_16,Reserved for future use." newline hexmask.long.byte 0x0 8.--15. 1. "LOC_FIRST_CORR_ERROR,Location/ID of the first corrected error within the region defined by REG_FIRST_CORR_ERROR. You can cycle this field value from 0 to 255 to access all counters according to the detailed report of check points at.." newline hexmask.long.byte 0x0 4.--7. 1. "REG_FIRST_CORR_ERROR,Region of the first corrected error: - 0x0: Region select for Adm Rx path - 0x1: Region select for layer 3 Rx path - 0x2: Region select for layer 2 Rx path - 0x3: Region select for DMA inbound path - 0x4: Region select for AXI bridge.." newline hexmask.long.byte 0x0 0.--3. 1. "RSVDP_0,Reserved for future use." line.long 0x4 "RASDP_UNCORR_ERROR_LOCATION_OFF,Uncorrected errors locations. For more details. see the RAS Data Protection (DP) section in the Core Operations chapter of the Databook." hexmask.long.byte 0x4 24.--31. 1. "LOC_LAST_UNCORR_ERROR,Location/ID of the last uncorrected error within the region defined by REG_LAST_UNCORR_ERROR. You can cycle this field value from 0 to 255 to access all counters according to the detailed report of check points at.." newline hexmask.long.byte 0x4 20.--23. 1. "REG_LAST_UNCORR_ERROR,Region of the last uncorrected error: - 0x0: Region select for Adm Rx path - 0x1: Region select for layer 3 Rx path - 0x2: Region select for layer 2 Rx path - 0x3: Region select for DMA inbound path - 0x4: Region select for AXI.." newline hexmask.long.byte 0x4 16.--19. 1. "RSVDP_16,Reserved for future use." newline hexmask.long.byte 0x4 8.--15. 1. "LOC_FIRST_UNCORR_ERROR,Location/ID of the first uncorrected error within the region defined by REG_FIRST_UNCORR_ERROR. You can cycle this field value from 0 to 255 to access all counters according to the detailed report of check points at.." newline hexmask.long.byte 0x4 4.--7. 1. "REG_FIRST_UNCORR_ERROR,Region of the first uncorrected error: - 0x0: Region select for Adm Rx path - 0x1: Region select for layer 3 Rx path - 0x2: Region select for layer 2 Rx path - 0x3: Region select for DMA inbound path - 0x4: Region select for AXI.." newline hexmask.long.byte 0x4 0.--3. 1. "RSVDP_0,Reserved for future use." group.long (0x28+0x480)++0x7 line.long 0x0 "RASDP_ERROR_MODE_EN_OFF,RASDP error mode enable. The controller enters RASDP error mode (if ERROR_MODE_EN =1) upon detection of the first uncorrectable error. During this mode: - Rx TLPs that are forwarded to your application are not guaranteed to be.." hexmask.long 0x0 2.--31. 1. "RSVDP_2,Reserved for future use." newline bitfld.long 0x0 1. "AUTO_LINK_DOWN_EN,Write '1' to enable the controller to bring the link down when the controller enters RASDP error mode. Note: This register field is sticky." "0,1" newline bitfld.long 0x0 0. "ERROR_MODE_EN,Write '1' to enable the controller enter RASDP error mode when it detects an uncorrectable error. Note: This register field is sticky." "0,1" line.long 0x4 "RASDP_ERROR_MODE_CLEAR_OFF,Exit RASDP error mode. For more details. see the RAS Data Protection (DP) section in the Core Operations chapter of the Databook." hexmask.long 0x4 1.--31. 1. "RSVDP_1,Reserved for future use." newline bitfld.long 0x4 0. "ERROR_MODE_CLEAR,Write '1' to take the controller out of RASDP error mode. The controller will then report uncorrectable errors (through AER internal error reporting) and also stop nullifying/discarding TLPs." "0,1" rgroup.long (0x30+0x480)++0x7 line.long 0x0 "RASDP_RAM_ADDR_CORR_ERROR_OFF,RAM Address where a corrected error (1-bit ECC) has been detected. For more details. see the RAS Data Protection (DP) section in the Core Operations chapter of the Databook." hexmask.long.byte 0x0 28.--31. 1. "RAM_INDEX_CORR_ERROR,RAM index where a corrected error (1-bit ECC) has been detected." newline bitfld.long 0x0 27. "RSVDP_27,Reserved for future use." "0,1" newline hexmask.long 0x0 0.--26. 1. "RAM_ADDR_CORR_ERROR,RAM Address where a corrected error (1-bit ECC) has been detected." line.long 0x4 "RASDP_RAM_ADDR_UNCORR_ERROR_OFF,RAM Address where an uncorrected error (2-bit ECC) has been detected. For more details. see the RAS Data Protection (DP) section in the Core Operations chapter of the Databook." hexmask.long.byte 0x4 28.--31. 1. "RAM_INDEX_UNCORR_ERROR,RAM index where an uncorrected error (2-bit ECC) has been detected." newline bitfld.long 0x4 27. "RSVDP_27,Reserved for future use." "0,1" newline hexmask.long 0x4 0.--26. 1. "RAM_ADDR_UNCORR_ERROR,RAM Address where an uncorrected error (2-bit ECC) has been detected." tree.end tree "PF0_RTR_CAP (PF RTR Capability Structure)" group.long (0x0+0x2F8)++0xB line.long 0x0 "RTR_EXT_CAP_HDR_OFF,Readiness Time Reporting PCI Express Extended Capability Header. For a description of this standard PCIe register. see the PCI Express Specification." hexmask.long.word 0x0 20.--31. 1. "RTR_NEXT_OFFSET,Next Capability Offset. For a description of this standard PCIe register field see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky).." hexmask.long.byte 0x0 16.--19. 1. "RTR_CAP_VERSION,Capability Version. For a description of this standard PCIe register field see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky).." hexmask.long.word 0x0 0.--15. 1. "RTR_EXT_CAP_ID,PCI Express Extended Capability ID. For a description of this standard PCIe register field see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then.." line.long 0x4 "READI_TIME_REPORTING1_OFF,Readiness Time Reporting 1. For a description of this standard PCIe register. see the PCI Express Specification." bitfld.long 0x4 31. "RTR_TIME_VALID,Valid. For a description of this standard PCIe register field see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky)" "0,1" hexmask.long.byte 0x4 24.--30. 1. "RSVDP_24,Reserved for future use." hexmask.long.word 0x4 12.--23. 1. "DL_UP_TIME,DL_UP Time. For a description of this standard PCIe register field see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky)" hexmask.long.word 0x4 0.--11. 1. "RESET_TIME,Reset Time. For a description of this standard PCIe register field see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky)" line.long 0x8 "READI_TIME_REPORTING2_OFF,Readiness Time Reporting 2. For a description of this standard PCIe register. see the PCI Express Specification." hexmask.long.byte 0x8 24.--31. 1. "RSVDP_24,Reserved for future use." hexmask.long.word 0x8 12.--23. 1. "D3HOT_D0_TIME,D3hot to D0 Time. For a description of this standard PCIe register field see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else.." hexmask.long.word 0x8 0.--11. 1. "FLR_TIME,FLR Time. For a description of this standard PCIe register field see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky)" tree.end tree "PF0_RTR_CAP_DBI2 (DBI2 Shadow Block: PF RTR Capability Structure)" rgroup.long (0x4+0x12F8)++0x7 line.long 0x0 "SHADOW_READI_TIME_REPORTING1_OFF,Shadow Register Readiness Time Reporting 1. For a description of this standard PCIe register. see the PCI Express Specification." bitfld.long 0x0 31. "RTR_TIME_VALID,Shadow Valid in the shadow register. For a description of this standard PCIe register field see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access - Dbi: No access - Dbi2: if.." "0,1" hexmask.long.tbyte 0x0 12.--30. 1. "RSVDP_12,Reserved for future use." hexmask.long.word 0x0 0.--11. 1. "RESET_TIME,Shadow Reset Time in the shadow register. For a description of this standard PCIe register field see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access - Dbi: No access - Dbi2: if.." line.long 0x4 "SHADOW_READI_TIME_REPORTING2_OFF,Shadow Register Readiness Time Reporting 2. For a description of this standard PCIe register. see the PCI Express Specification." hexmask.long.byte 0x4 24.--31. 1. "RSVDP_24,Reserved for future use." hexmask.long.word 0x4 12.--23. 1. "D3HOT_D0_TIME,Shadow D3hot to D0 Time in the shadow register. For a description of this standard PCIe register field see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access - Dbi: No access - Dbi2:.." hexmask.long.word 0x4 0.--11. 1. "FLR_TIME,Shadow FLR Time in the shadow register. For a description of this standard PCIe register field see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access - Dbi: No access - Dbi2: if.." tree.end tree "PF0_FRSQ_CAP (PF FRSQ Capability Structure)" group.long (0x0+0x2E8)++0xB line.long 0x0 "FRSQ_EXT_CAP_HDR_OFF,FRS Queuing Extended Capability Header. For a description of this standard PCIe register. see the PCI Express Specification." hexmask.long.word 0x0 20.--31. 1. "FRSQ_NEXT_OFFSET,Next Capability Offset. For a description of this standard PCIe register field see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then.." hexmask.long.byte 0x0 16.--19. 1. "FRSQ_CAP_VERSION,Capability Version. For a description of this standard PCIe register field see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky).." hexmask.long.word 0x0 0.--15. 1. "FRSQ_EXT_CAP_ID,PCI Express Extended Capability ID. For a description of this standard PCIe register field see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then.." line.long 0x4 "FRSQ_CAP_OFF,FRS Queuing Capability Register. For a description of this standard PCIe register. see the PCI Express Specification." hexmask.long.word 0x4 21.--31. 1. "RSVDP_21,Reserved for future use." hexmask.long.byte 0x4 16.--20. 1. "FRS_INT_MESSAGE_NUMBER,FRS Interrupt Message Number. For a description of this standard PCIe register field see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1).." hexmask.long.byte 0x4 12.--15. 1. "RSVDP_12,Reserved for future use." hexmask.long.word 0x4 0.--11. 1. "FRSQ_MAX_DEPTH,FRS Queue Max Depth. For a description of this standard PCIe register field see the PCI Express Specification." line.long 0x8 "FRSQ_CONTROL_FRSQ_STATUS_OFF,FRS Queuing Status and Control Register. For a description of this standard PCIe register. see the PCI Express Specification." hexmask.long.word 0x8 17.--31. 1. "RSVDP_17,Reserved for future use." bitfld.long 0x8 16. "FRS_INTERRUPT_ENABLE,FRS Interrupt Enable. For a description of this standard PCIe register field see the PCI Express Specification." "0,1" hexmask.long.word 0x8 2.--15. 1. "RSVDP_2,Reserved for future use." bitfld.long 0x8 1. "FRS_MESSAGE_OVERFLOW,FRS Message Overflow. For a description of this standard PCIe register field see the PCI Express Specification." "0,1" newline bitfld.long 0x8 0. "FRS_MESSAGE_RECEIVED,FRS Message Received. For a description of this standard PCIe register field see the PCI Express Specification." "0,1" rgroup.long (0xC+0x2E8)++0x3 line.long 0x0 "FRS_MESSAGE_QUEUE_OFF,FRS Message Queue Register. For a description of this standard PCIe register. see the PCI Express Specification." hexmask.long.word 0x0 20.--31. 1. "FRS_MESSAGE_QUE_DEPTH,FRS Message Queue Depth. For a description of this standard PCIe register field see the PCI Express Specification." hexmask.long.byte 0x0 16.--19. 1. "FRS_MESSAGE_QUE_REASON,FRS Message Queue Reason. For a description of this standard PCIe register field see the PCI Express Specification." hexmask.long.word 0x0 0.--15. 1. "FRS_MESSAGE_QUE_FUNC_ID,FRS Message Queue Function ID. For a description of this standard PCIe register field see the PCI Express Specification." tree.end tree "PF0_PTM_CAP (PF PTM Capability Structure)" group.long (0x0+0x40C)++0xB line.long 0x0 "PTM_EXT_CAP_HDR_OFF,Precision Time Measurement Capability Header. For a description of this standard PCIe register. see the PCI Express Specification." hexmask.long.word 0x0 20.--31. 1. "PTM_NEXT_OFFSET,Precision Time Measurement PCI Express Extended Capability Next Offset. For a description of this standard PCIe register see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access. -.." hexmask.long.byte 0x0 16.--19. 1. "PTM_CAP_VERSION,Precision Time Measurement PCI Express Extended Capability Version. For a description of this standard PCIe register see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi:.." hexmask.long.word 0x0 0.--15. 1. "PTM_CAP_ID,Precision Time Measurement PCI Express Extended Capability ID. For a description of this standard PCIe register see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if.." line.long 0x4 "PTM_CAP_OFF,PTM Capability Register. For a description of this standard PCIe register. see the PCI Express Specification." hexmask.long.word 0x4 16.--31. 1. "RSVDP_16,Reserved for future use." hexmask.long.byte 0x4 8.--15. 1. "PTM_CLK_GRAN,PTM Local Clock Granularity. For a description of this standard PCIe register see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky).." hexmask.long.byte 0x4 3.--7. 1. "RSVDP_3,Reserved for future use." bitfld.long 0x4 2. "PTM_ROOT_CAPABLE,PTM Root Capable. For a description of this standard PCIe register see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else.." "0,1" bitfld.long 0x4 1. "PTM_RES_CAPABLE,PTM Responder Capable. For a description of this standard PCIe register see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else.." "0,1" newline bitfld.long 0x4 0. "PTM_REQ_CAPABLE,PTM Requester Capable. For a description of this standard PCIe register see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else.." "0,1" line.long 0x8 "PTM_CONTROL_OFF,PTM Control Register. For a description of this standard PCIe register. see the PCI Express Specification." hexmask.long.word 0x8 16.--31. 1. "RSVDP_16,Reserved for future use." hexmask.long.byte 0x8 8.--15. 1. "EFF_GRAN,PTM Effective Granularity. For a description of this standard PCIe register see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: HWINIT" hexmask.long.byte 0x8 2.--7. 1. "RSVDP_2,Reserved for future use." rbitfld.long 0x8 1. "ROOT_SELECT,PTM Root Select. When set this Time Source is the PTM Root. For a description of this standard PCIe register see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: HWINIT" "0,1" bitfld.long 0x8 0. "PTM_ENABLE,PTM Enable. When set this function is permitted to participate in the PTM mechanism. For a description of this standard PCIe register see the PCI Express Specification." "0,1" tree.end tree "PF0_PTM_RES_CAP (PF PTM Responder Capability Structure (VSEC))" group.long (0x0+0x418)++0xB line.long 0x0 "PTM_RES_CAP_HDR_OFF,Precision Time Measurement Responder Capability Header (VSEC). For more details. see the PTM section in the Databook." hexmask.long.word 0x0 20.--31. 1. "PTM_RES_EXT_CAP_NEXT_OFFS,Precision Time Measurement Responder VSEC Next Pointer. For more details see the PTM section in the Databook. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then.." hexmask.long.byte 0x0 16.--19. 1. "PTM_RES_EXT_CAP_VER,Precision Time Measurement Responder VSEC Version. For more details see the PTM section in the Databook. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else.." hexmask.long.word 0x0 0.--15. 1. "PTM_RES_EXT_CAP_ID,Precision Time Measurement Responder VSEC ID. For more details see the PTM section in the Databook. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else.." line.long 0x4 "PTM_RES_HDR_OFF,Precision Time Measurement Responder Vendor Specific Header. For more details. see the PTM section in the Databook." hexmask.long.word 0x4 20.--31. 1. "PTM_RES_VSEC_LENGTH,PTM Responder VSEC Length. For more details see the PTM section in the Databook. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This.." hexmask.long.byte 0x4 16.--19. 1. "PTM_RES_VSEC_REV,PTM Responder VSEC Revision. For more details see the PTM section in the Databook. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This.." hexmask.long.word 0x4 0.--15. 1. "PTM_RES_VSEC_ID,PTM Responder VSEC ID. For more details see the PTM section in the Databook. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register.." line.long 0x8 "PTM_RES_CONTROL_OFF,PTM Responder Control Register. For more details. see the PTM section in the Databook." hexmask.long 0x8 2.--31. 1. "RSVDP_2,Reserved for future use." bitfld.long 0x8 1. "PTM_RES_PDEL_BYTE_REV,PTM Requester Propagation Delay Byte Reversal - Reverse the order of bytes in the PTM Propagation Delay data word of the PTM ResponseD Message for compatibility with previous revisions. For more details see the PTM section in the.." "0,1" bitfld.long 0x8 0. "PTM_RES_CCONTEXT_VALID,PTM Responder Control Context Valid - PTM Local Timing is valid. This bit is set over the DBI. A speed change or aux_clk_active will set this bit low. For more details see the PTM section in the Databook. Note: The access.." "0,1" rgroup.long (0xC+0x418)++0x3 line.long 0x0 "PTM_RES_STATUS_OFF,PTM Responder Status Register. For more details. see the PTM section in the Databook." hexmask.long 0x0 2.--31. 1. "RSVDP_2,Reserved for future use." bitfld.long 0x0 1. "PTM_RES_REQUEST_RECEIVED,PTM 1st Request Received - PTM Responder has received the first PTM Request Message. Upon receipt of a second PTM Request Message a ResponseD message with timing information will be sent from the Responder if the context is.." "0,1" bitfld.long 0x0 0. "PTM_RES_CONTEXT_VALID,PTM Responder Status Context Valid - PTM Local Timing Context is Valid. Value set from upstream port Requester in a Switch. Shadows the same in the control register in all other products. For more details see the PTM section in the.." "0,1" group.long (0x10+0x418)++0x7 line.long 0x0 "PTM_RES_LOCAL_LSB_OFF,PTM Responder Local Clock LSB. For more details. see the PTM section in the Databook." hexmask.long 0x0 0.--31. 1. "PTM_RES_LOCAL_LSB,PTM Responder Local Clock LSB - Lower 32 bits of local timer value. For more details see the PTM section in the Databook. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then.." line.long 0x4 "PTM_RES_LOCAL_MSB_OFF,PTM Responder Local Clock MSB. For more details. see the PTM section in the Databook." hexmask.long 0x4 0.--31. 1. "PTM_RES_LOCAL_MSB,PTM Responder Local Clock MSB - Upper 32 bits of local timer value. For more details see the PTM section in the Databook. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then.." rgroup.long (0x18+0x418)++0x1F line.long 0x0 "PTM_RES_T2_LSB_OFF,PTM Responder T2 Timestamp LSB. For more details. see the PTM section in the Databook." hexmask.long 0x0 0.--31. 1. "PTM_RES_T2_LSB,PTM Responder T2 Timestamp LSB - Lower 32 bits of the T2 Timestamp value. For more details see the PTM section in the Databook. Note: This register field is sticky." line.long 0x4 "PTM_RES_T2_MSB_OFF,PTM Responder T2 Timestamp MSB. For more details. see the PTM section in the Databook." hexmask.long 0x4 0.--31. 1. "PTM_RES_T2_MSB,PTM Responder T2 Timestamp MSB - Upper 32 bits of the T2 Timestamp value. For more details see the PTM section in the Databook. Note: This register field is sticky." line.long 0x8 "PTM_RES_T2P_LSB_OFF,PTM Responder T2 Previous Timestamp LSB. For more details. see the PTM section in the Databook." hexmask.long 0x8 0.--31. 1. "PTM_RES_T2P_LSB,PTM Responder T2 Previous Timestamp LSB - Lower 32 bits of the previously stored T2 Timestamp value. For more details see the PTM section in the Databook. Note: This register field is sticky." line.long 0xC "PTM_RES_T2P_MSB_OFF,PTM Responder T2 Previous Timestamp MSB. For more details. see the PTM section in the Databook." hexmask.long 0xC 0.--31. 1. "PTM_RES_T2P_MSB,PTM Responder T2 Previous Timestamp MSB - Upper 32 bits of the previously stored T2 Timestamp value. For more details see the PTM section in the Databook. Note: This register field is sticky." line.long 0x10 "PTM_RES_T3_LSB_OFF,PTM Responder T3 Timestamp LSB. For more details. see the PTM section in the Databook." hexmask.long 0x10 0.--31. 1. "PTM_RES_T3_LSB,PTM Responder T3 Timestamp LSB - Lower 32 bits of the T3 Timestamp value. For more details see the PTM section in the Databook. Note: This register field is sticky." line.long 0x14 "PTM_RES_T3_MSB_OFF,PTM Responder T3 Timestamp MSB. For more details. see the PTM section in the Databook." hexmask.long 0x14 0.--31. 1. "PTM_RES_T3_MSB,PTM Responder T3 Timestamp MSB - Upper 32 bits of the T2 Timestamp value. For more details see the PTM section in the Databook. Note: This register field is sticky." line.long 0x18 "PTM_RES_T3P_LSB_OFF,PTM Responder T3 Previous Timestamp LSB. For more details. see the PTM section in the Databook." hexmask.long 0x18 0.--31. 1. "PTM_RES_T3P_LSB,PTM Responder T3 Previous Timestamp LSB - Lower 32 bits of the previously stored T3 Timestamp value. For more details see the PTM section in the Databook. Note: This register field is sticky." line.long 0x1C "PTM_RES_T3P_MSB_OFF,PTM Responder T3 Previous Timestamp MSB. For more details. see the PTM section in the Databook." hexmask.long 0x1C 0.--31. 1. "PTM_RES_T3P_MSB,PTM Responder T3 Previous Timestamp MSB - Upper 32 bits of the previously stored T3 Timestamp value. For more details see the PTM section in the Databook. Note: This register field is sticky." group.long (0x38+0x418)++0x7 line.long 0x0 "PTM_RES_TX_LATENCY_OFF,PTM Responder TX Latency. For more details. see the PTM section in the Databook." hexmask.long.tbyte 0x0 12.--31. 1. "RSVDP_12,Reserved for future use." hexmask.long.word 0x0 0.--11. 1. "PTM_RES_TX_LATENCY,PTM Responder TX Latency - Responder Transmit path latency (12 bit wide). For more details see the PTM section in the Databook. Note: This register field is sticky." line.long 0x4 "PTM_RES_RX_LATENCY_OFF,PTM Responder RX Latency. For more details. see the PTM section in the Databook." hexmask.long.tbyte 0x4 12.--31. 1. "RSVDP_12,Reserved for future use." hexmask.long.word 0x4 0.--11. 1. "PTM_RES_RX_LATENCY,PTM Responder RX Latency - Responder Receive path latency (12 bit wide). For more details see the PTM section in the Databook. Note: This register field is sticky." rgroup.long (0x40+0x418)++0x3 line.long 0x0 "PTM_RES_NOM_CLOCK_T_OFF,PTM Responder Nominal Clock Period. For more details. see the PTM section in the Databook." hexmask.long.byte 0x0 24.--31. 1. "RSVDP_24,Reserved for future use." hexmask.long.byte 0x0 16.--23. 1. "PTM_RES_NOM_CLOCK_T_INT,PTM Responder Nominal Clock Period Integral - Integral part of the nominal PTM local clock period in nanoseconds. For more details see the PTM section in the Databook. Note: This register field is sticky." hexmask.long.word 0x0 0.--15. 1. "PTM_RES_NOM_CLOCK_T_FRAC,PTM Responder Nominal Clock Period Fractional - Fractional part of the nominal PTM local clock period. LSB is 1/(2^16) nanoseconds. For more details see the PTM section in the Databook. Note: This register field is sticky." group.long (0x44+0x418)++0x3 line.long 0x0 "PTM_RES_SCALED_CLOCK_T_OFF,PTM Responder Scaled Clock Period. For more details. see the PTM section in the Databook." bitfld.long 0x0 31. "PTM_RES_SCALED_CLOCK_T_EN,PTM Responder Scaled Clock Period Enable - Use the programmed scaled PTM clock period rather than the nominal values. This bit is cleared when the core_clk rate starts to change and can only be set when the clock period change.." "0,1" hexmask.long.byte 0x0 24.--30. 1. "RSVDP_24,Reserved for future use." hexmask.long.byte 0x0 16.--23. 1. "PTM_RES_SCALED_CLOCK_T_INT,PTM Responder Scaled Clock Period Integral - Integral part of the nominal PTM local clock period in nanoseconds. For more details see the PTM section in the Databook. Note: This register field is sticky." newline hexmask.long.word 0x0 0.--15. 1. "PTM_RES_SCALED_CLOCK_T_FRAC,PTM Responder Scaled Clock Period Fractional - Fractional part of the nominal PTM local clock period. LSB is 1/(2^16) nanoseconds. For more details see the PTM section in the Databook. Note: This register field is sticky." tree.end tree "PF0_PM_CAP (PF PCI Power Management Capability Structure)" group.long (0x0+0x40)++0x7 line.long 0x0 "CAP_ID_NXT_PTR_REG,Power Management Capabilities Register." hexmask.long.byte 0x0 27.--31. 1. "PME_SUPPORT,PME_Support. This 5-bit field indicates the power states in which the function may generate a PME and/or forward PME messages. A value of 0b for any bit indicates that the function is not capable of asserting PME while in that power state. -.." bitfld.long 0x0 26. "D2_SUPPORT,D2_Support. If this bit is set this function supports the D2 Power Management state. Functions that do not support D2 must always return a value of 0b for this bit. Note: The access attributes of this field are as follows: - Wire: No access." "0,1" bitfld.long 0x0 25. "D1_SUPPORT,D1_Support. If this bit is set this function supports the D1 Power Management state. Functions that do not support D1 must always return a value of 0b for this bit. Note: The access attributes of this field are as follows: - Wire: No access." "0,1" bitfld.long 0x0 22.--24. "AUX_CURR,Aux_Current. This 3 bit field reports the Vaux auxiliary current requirements for the function. If this function implements the Data Register the controller hardwires this field to 000b. If PME_Support is 0 xxxxb (PME assertion from D3cold is.." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 21. "DSI,Device Specific Initialization. The DSI bit indicates whether special initialization of this function is required. When set indicates that the function requires a device specific initialization sequence following a transition to the D0uninitialized.." "0,1" bitfld.long 0x0 20. "PME_IMM_READI_RETURN_DO,Immediate_Readiness_on_Return_to_D0. - If this bit is a '1' this function is guaranteed to be ready to successfully complete valid accesses immediately after being set to D0. These accesses include configuration cycles and if.." "0,1" rbitfld.long 0x0 19. "PME_CLK,PME Clock. Does not apply to PCI Express the controller hardwires it to 0b. Note: This register field is sticky." "0,1" bitfld.long 0x0 16.--18. "PM_SPEC_VER,Version. This field provides the Power Management specification version. The controller hardwires this field to 011b for functions compliant to PCI Express Base Specification Revision 4.0 Version 1.0>. Note: The access attributes of this.." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x0 8.--15. 1. "PM_NEXT_POINTER,Next Capability Pointer. This field provides an offset into the function's configuration space pointing to the location of next item in the capabilities list. If there are no additional items in the capabilities list this field is set to.." hexmask.long.byte 0x0 0.--7. 1. "PM_CAP_ID,Capability ID. This field returns 01h to indicate that this is the PCI Power Management Capability. Each function may have only one item in its capability list with Capability ID set to 01h." line.long 0x4 "CON_STATUS_REG,Power Management Control and Status Register. This register is used to manage the PCI function's power management state as well as to enable/monitor PMEs." hexmask.long.byte 0x4 24.--31. 1. "DATA_REG_ADD_INFO,Data. This field is used to report the state dependent data requested by the Data_Select field. The value of this field is scaled by the value reported by the Data_Scale field." rbitfld.long 0x4 23. "BUS_PWR_CLK_CON_EN,Bus Power/Clock Control Enable. For a description of this standard PCIe register field see the PCI Express Base Specification." "0,1" rbitfld.long 0x4 22. "B2_B3_SUPPORT,B2B3 Support for D3hot. For a description of this standard PCIe register field see the PCI Express Base Specification." "0,1" hexmask.long.byte 0x4 16.--21. 1. "RSVDP_16,Reserved for future use." newline bitfld.long 0x4 15. "PME_STATUS,PME_Status. This bit is set when the function normally generates a PME signal. The value of this bit is not affected by the value of the PME_En bit. If PME_Support bit 31 of the Power Management Capabilities register is clear this bit is.." "0,1" rbitfld.long 0x4 13.--14. "DATA_SCALE,Data_Scale. This field indicates the scaling factor to be used when interpreting the value of the Data field. The value and meaning of this field varies depending on which data value has been selected by the Data_Select field. For more details.." "0,1,2,3" hexmask.long.byte 0x4 9.--12. 1. "DATA_SELECT,Data_Select. This 4-bit field is used to select which data is to be reported through the Data and Data_Scale field. If the Data field is not implemented this field must be hardwired to 0000b." bitfld.long 0x4 8. "PME_ENABLE,PME_En. - When set the function is permitted to generate a PME. - When clear the function is not permitted to generate a PME. If PME_Support is 1 xxxxb (PME generation from D3cold) or the function consumes Aux power and Aux power is.." "0,1" newline hexmask.long.byte 0x4 4.--7. 1. "RSVDP_4,Reserved for future use." bitfld.long 0x4 3. "NO_SOFT_RST,No_Soft_Reset. This bit indicates the state of the function after writing the PowerState field to transition the function from D3hot to D0. - When set this transition preserves internal function state. The function is in D0Active and no.." "0,1" rbitfld.long 0x4 2. "RSVDP_2,Reserved for future use." "0,1" bitfld.long 0x4 0.--1. "POWER_STATE,PowerState. This 2-bit field is used both to determine the current power state of a function and to set the function into a new power state. The definition of the field values is given below. You can write to this register; however the.." "D0,D1,D2,D3hot" tree.end tree "PF0_PCIE_CAP (PF PCI Express Capability Structure)" group.long (0x0+0x70)++0x33 line.long 0x0 "PCIE_CAP_ID_PCIE_NEXT_CAP_PTR_PCIE_CAP_REG,PCI Express Capabilities. ID. Next Pointer Register." rbitfld.long 0x0 31. "RSVDP_31,Reserved for future use." "0,1" rbitfld.long 0x0 30. "RSVD,Reserved." "0,1" newline hexmask.long.byte 0x0 25.--29. 1. "PCIE_INT_MSG_NUM,PCIE Interrupt Message Number. For a description of this standard PCIe register field see the PCI Express Base Specification. Interrupt Message Number. This field indicates which MSI/MSI-X vector is used for the interrupt message.." bitfld.long 0x0 24. "PCIE_SLOT_IMP,Slot Implemented. When set this bit indicates that the Link associated with this Port is connected to a slot (as compared to being connected to a system-integrated device or being disabled). This bit is valid for Downstream Ports. This bit.." "0,1" newline hexmask.long.byte 0x0 20.--23. 1. "PCIE_DEV_PORT_TYPE,Device/Port Type. Indicates the specific type of this PCI Express function. Note: Different functions in a Multi-Function Device can generally be of different types. Defined encodings for functions that implement a Type 00h PCI.." hexmask.long.byte 0x0 16.--19. 1. "PCIE_CAP_REG,Capability Version. Indicates PCI-SIG defined PCI Express Capability structure version number. A version of the specification that changes the PCI Express Capability structure in a way that is not otherwise identifiable (for example through.." newline hexmask.long.byte 0x0 8.--15. 1. "PCIE_CAP_NEXT_PTR,Next Capability Pointer. This field contains the offset to the next PCI Capability structure or 00h if no other items exist in the linked list of Capabilities. Note: The access attributes of this field are as follows: - Wire: No access." hexmask.long.byte 0x0 0.--7. 1. "PCIE_CAP_ID,Capability ID. Indicates the PCI Express Capability structure. This field must return a Capability ID of 10h indicating that this is a PCI Express Capability structure." line.long 0x4 "DEVICE_CAPABILITIES_REG,Device Capabilities Register. The Device Capabilities register identifies PCI Express device function specific capabilities." hexmask.long.word 0x4 16.--31. 1. "RSVDP_16,Reserved for future use." bitfld.long 0x4 15. "PCIE_CAP_ROLE_BASED_ERR_REPORT,Role-Based Error Reporting. When set this bit indicates that the function implements the functionality originally defined in the Error Reporting ECN for PCI Express Base Specification Revision 1.0a and later incorporated.." "0,1" newline hexmask.long.word 0x4 6.--14. 1. "RSVDP_6,Reserved for future use." bitfld.long 0x4 5. "PCIE_CAP_EXT_TAG_SUPP,Extended Tag Field Supported. This bit in combination with the 10-Bit Tag Requester Supported bit in the Device Capabilities 2 register indicates the maximum supported size of the Tag field as a Requester. This bit must be set if.." "0,1" newline bitfld.long 0x4 3.--4. "PCIE_CAP_PHANTOM_FUNC_SUPPORT,Phantom Functions Supported. This field indicates the support for use of unclaimed function numbers to extend the number of outstanding transactions allowed by logically combining unclaimed function numbers (called Phantom.." "0,1,2,3" bitfld.long 0x4 0.--2. "PCIE_CAP_MAX_PAYLOAD_SIZE,Max_Payload_Size Supported. This field indicates the maximum payload size that the function can support for TLPs. Defined encodings are: - 000b: 128 bytes max payload size - 001b: 256 bytes max payload size - 010b: 512 bytes max.." "0,1,2,3,4,5,6,7" line.long 0x8 "DEVICE_CONTROL_DEVICE_STATUS,Device Control and Device Status Register. This register controls PCI Express device specific parameters and provides information about PCI Express device (function) specific parameters." hexmask.long.word 0x8 22.--31. 1. "RSVDP_22,Reserved for future use." rbitfld.long 0x8 21. "PCIE_CAP_TRANS_PENDING,Transactions Pending. Endpoints: When set this bit indicates that the function has issued Non-Posted Requests that have not been completed. A Function reports this bit cleared only when all outstanding Non-Posted Requests have.." "0,1" newline rbitfld.long 0x8 20. "PCIE_CAP_AUX_POWER_DETECTED,AUX Power Detected. Functions that require Aux power report this bit as set if Aux power is detected by the function. This bit is derived by sampling the sys_aux_pwr_det input." "0,1" bitfld.long 0x8 19. "PCIE_CAP_UNSUPPORTED_REQ_DETECTED,Unsupported Request Detected. This bit indicates that the function received an Unsupported Request. Errors are logged in this register regardless of whether error reporting is enabled or not in the Device Control.." "0,1" newline bitfld.long 0x8 18. "PCIE_CAP_FATAL_ERR_DETECTED,Fatal Error Detected. This bit indicates status of Fatal errors detected. Errors are logged in this register regardless of whether error reporting is enabled or not in the Device Control register. For a Multi-Function device.." "0,1" bitfld.long 0x8 17. "PCIE_CAP_NON_FATAL_ERR_DETECTED,Non-Fatal Error Detected. This bit indicates status of Non-fatal errors detected. Errors are logged in this register regardless of whether error reporting is enabled or not in the Device Control register. For a.." "0,1" newline bitfld.long 0x8 16. "PCIE_CAP_CORR_ERR_DETECTED,Correctable Error Detected. This bit indicates status of correctable errors detected. Errors are logged in this register regardless of whether error reporting is enabled or not in the Device Control register. For a.." "0,1" bitfld.long 0x8 15. "PCIE_CAP_INITIATE_FLR,Initiate Function Level Reset (applicable to Endpoints with Function Level Reset Capability set to 1b). A write of 1b initiates Function Level Reset to the Function. The value read by software from this bit is always 0b." "0,1" newline bitfld.long 0x8 12.--14. "PCIE_CAP_MAX_READ_REQ_SIZE,Max_Read_Request_Size. This field sets the maximum Read Request size for the function as a Requester. The function must not generate Read Requests with a size exceeding the set value. Defined encodings for this field are: -.." "0,1,2,3,4,5,6,7" rbitfld.long 0x8 11. "PCIE_CAP_EN_NO_SNOOP,Enable No Snoop. If this bit is set the function is permitted to Set the No Snoop bit in the Requester Attributes of transactions it initiates that do not require hardware enforced cache coherency (see section 2.2.6.5 in PCI Express.." "0,1" newline bitfld.long 0x8 10. "PCIE_CAP_AUX_POWER_PM_EN,Aux Power PM Enable. This bit is derived by sampling the sys_aux_pwr_det input. When set this bit enables a function to draw Aux power independent of PME Aux power. Functions that require Aux power on legacy operating systems.." "0,1" rbitfld.long 0x8 9. "PCIE_CAP_PHANTOM_FUNC_EN,Phantom Functions Enable. This bit in combination with the 10-Bit Tag Requester Enable bit in the Device Control 2 register determines how many Tag field bits a Requester is permitted to use. When the 10-Bit Tag Requester.." "0,1" newline rbitfld.long 0x8 8. "PCIE_CAP_EXT_TAG_EN,Extended Tag Field Enable. This bit in combination with the 10-Bit Tag Requester Enable bit in the Device Control 2 register determines how many Tag field bits a Requester is permitted to use. When the 10-Bit Tag Requester Enable.." "0,1" bitfld.long 0x8 5.--7. "PCIE_CAP_MAX_PAYLOAD_SIZE_CS,Max_Payload_Size. This field sets maximum TLP payload size for the Function. As a Receiver the Function must handle TLPs as large as the set value. As a Transmitter the Function must not generate TLPs exceeding the set.." "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 4. "PCIE_CAP_EN_REL_ORDER,Enable Relaxed Ordering. If this bit is set the function is permitted to set the Relaxed Ordering bit in the Attributes field of transactions it initiates that do not require strong write ordering (for more details see section.." "0,1" bitfld.long 0x8 3. "PCIE_CAP_UNSUPPORT_REQ_REP_EN,Unsupported Request Reporting Enable. This bit in conjunction with other bits controls the signaling of Unsupported Request Errors by sending error Messages (for more details see section 6.2.5 and section 6.2.6 of PCI.." "0,1" newline bitfld.long 0x8 2. "PCIE_CAP_FATAL_ERR_REPORT_EN,Fatal Error Reporting Enable. This bit in conjunction with other bits controls sending ERR_FATAL Messages (for more details see section 6.2.5 and section 6.2.6 of of PCI Express Base Specification). For a Multi-Function.." "0,1" bitfld.long 0x8 1. "PCIE_CAP_NON_FATAL_ERR_REPORT_EN,Non-Fatal Error Reporting Enable. This bit in conjunction with other bits controls sending ERR_NONFATAL Messages (for more details see section 6.2.5 and Section 6.2.6 of PCI Express Base Specification). For a.." "0,1" newline bitfld.long 0x8 0. "PCIE_CAP_CORR_ERR_REPORT_EN,Correctable Error Reporting Enable. This bit in conjunction with other bits controls sending ERR_COR Messages (for more details see section 6.2.5 section 6.2.6 and section 6.2.10.2 of PCI Express Base Specification). For.." "0,1" line.long 0xC "LINK_CAPABILITIES_REG,Link Capabilities Register. The Link Capabilities register identifies PCI Express Link specific capabilities." hexmask.long.byte 0xC 24.--31. 1. "PCIE_CAP_PORT_NUM,Port Number. This field indicates the PCI Express Port number for the given PCI Express Link. Multi-Function Devices associated with an Upstream Port must report the same value in this field for all functions. Note: The access.." rbitfld.long 0xC 23. "RSVDP_23,Reserved for future use." "0,1" newline bitfld.long 0xC 22. "PCIE_CAP_ASPM_OPT_COMPLIANCE,ASPM Optionality Compliance. This bit must be set to 1b in all functions. Components implemented against certain earlier versions of this specification will have this bit set to 0b. Software is permitted to use the value of.." "0,1" bitfld.long 0xC 21. "PCIE_CAP_LINK_BW_NOT_CAP,Link Bandwidth Notification Capability. A value of 1b indicates support for the Link Bandwidth Notification status and interrupt mechanisms. This capability is required for all Root Ports and Switch Downstream Ports supporting.." "0,1" newline rbitfld.long 0xC 20. "PCIE_CAP_DLL_ACTIVE_REP_CAP,Data Link Layer Link Active Reporting Capable. For a Downstream Port the controller hardwires this bit to 1b if the component supports the optional capability of reporting the DL_Active state of the Data Link Control and.." "0,1" bitfld.long 0xC 19. "PCIE_CAP_SURPRISE_DOWN_ERR_REP_CAP,Surprise Down Error Reporting Capable. For a Downstream Port this bit must be set if the component supports the optional capability of detecting and reporting a Surprise Down error condition. For Upstream Ports and.." "0,1" newline rbitfld.long 0xC 18. "PCIE_CAP_CLOCK_POWER_MAN,Clock Power Management. For Upstream Ports a value of 1b in this bit indicates that the component tolerates the removal of any reference clock(s) via the 'clock request' (CLKREQ#) mechanism when the Link is in the L1 and L2/L3.." "0,1" bitfld.long 0xC 15.--17. "PCIE_CAP_L1_EXIT_LATENCY,L1 Exit Latency. This field indicates the L1 exit latency for the given PCI Express Link. The value reported indicates the length of time this Port requires to complete transition from ASPM L1 to L0. If ASPM L1 is not supported.." "0,1,2,3,4,5,6,7" newline bitfld.long 0xC 12.--14. "PCIE_CAP_L0S_EXIT_LATENCY,L0s Exit Latency. This field indicates the L0s exit latency for the given PCI Express Link. The value reported indicates the length of time this Port requires to complete transition from L0s to L0. If L0s is not supported the.." "0,1,2,3,4,5,6,7" bitfld.long 0xC 10.--11. "PCIE_CAP_ACTIVE_STATE_LINK_PM_SUPPORT,Active State Power Management (ASPM) Support. This field indicates the level of ASPM supported on the given PCI Express Link. For more details on ASPM support requirements see section 5.4.1 of PCI Express Base.." "0,1,2,3" newline hexmask.long.byte 0xC 4.--9. 1. "PCIE_CAP_MAX_LINK_WIDTH,Maximum Link Width. This field indicates the maximum Link width (xN - corresponding to N Lanes) implemented by the component. This value is permitted to exceed the number of Lanes routed to the slot (Downstream Port) adapter.." hexmask.long.byte 0xC 0.--3. 1. "PCIE_CAP_MAX_LINK_SPEED,Max Link Speed. This field indicates the maximum Link speed of the associated Port. The encoded value specifies a bit location in the Supported Link Speeds Vector (in the Link Capabilities 2 register) that corresponds to the.." line.long 0x10 "LINK_CONTROL_LINK_STATUS_REG,Link Control and Link Status Register. This register controls and provides information about PCI Express Link specific parameters." bitfld.long 0x10 31. "PCIE_CAP_LINK_AUTO_BW_STATUS,Link Autonomous Bandwidth Status. This bit is set by hardware to indicate that hardware has autonomously changed Link speed or width without the Port transitioning through DL_Down status for reasons other than to attempt to.." "0,1" bitfld.long 0x10 30. "PCIE_CAP_LINK_BW_MAN_STATUS,Link Bandwidth Management Status. This bit is set by hardware to indicate that either of the following has occurred without the Port transitioning through DL_Down status: - A Link retraining has completed following a write of.." "0,1" newline rbitfld.long 0x10 29. "PCIE_CAP_DLL_ACTIVE,Data Link Layer Link Active. This bit indicates the status of the Data Link Control and Management State Machine. It returns a 1b to indicate the DL_Active state 0b otherwise. This bit must be implemented if the Data Link Layer Link.." "0,1" bitfld.long 0x10 28. "PCIE_CAP_SLOT_CLK_CONFIG,Slot Clock Configuration. This bit indicates that the component uses the same physical reference clock that the platform provides on the connector. If the device uses an independent clock irrespective of the presence of a.." "0,1" newline rbitfld.long 0x10 27. "PCIE_CAP_LINK_TRAINING,Link Training. This read-only bit indicates that the Physical Layer LTSSM is in the Configuration or Recovery state or that 1b was written to the Retrain Link bit but Link training has not yet begun. Hardware clears this bit when.." "0,1" rbitfld.long 0x10 26. "RSVDP_26,Reserved for future use." "0,1" newline hexmask.long.byte 0x10 20.--25. 1. "PCIE_CAP_NEGO_LINK_WIDTH,Negotiated Link Width. This field indicates the negotiated width of the given PCI Express Link. Defined encodings are: -00 0001b: x1 -00 0010b: x2 -00 0100b: x4 -00 1000b: x8 -00 1100b: x12 -01 0000b: x16 -10 0000b: x32 All other.." hexmask.long.byte 0x10 16.--19. 1. "PCIE_CAP_LINK_SPEED,Current Link Speed. This field indicates the negotiated Link speed of the given PCI Express Link. The encoded value specifies a bit location in the Supported Link Speeds Vector (in the Link Capabilities 2 register) that corresponds to.." newline bitfld.long 0x10 14.--15. "PCIE_CAP_DRS_SIGNALING_CONTROL,DRS Signaling Control. Indicates the mechanism used to report reception of a DRS message. Must be implemented for Downstream Ports with the DRS Supported bit Set in the Link Capabilities 2 Register. Encodings are: - 00b:.." "0,1,2,3" rbitfld.long 0x10 12.--13. "RSVDP_12,Reserved for future use." "0,1,2,3" newline bitfld.long 0x10 11. "PCIE_CAP_LINK_AUTO_BW_INT_EN,Link Autonomous Bandwidth Management Interrupt Enable. When set this bit enables the generation of an interrupt to indicate that the Link Autonomous Bandwidth Status bit has been set. The write value is gated with the.." "0,1" bitfld.long 0x10 10. "PCIE_CAP_LINK_BW_MAN_INT_EN,Link Bandwidth Management Interrupt Enable. When set this bit enables the generation of an interrupt to indicate that the Link Bandwidth Management Status bit has been set. The write value is gated with the.." "0,1" newline bitfld.long 0x10 9. "PCIE_CAP_HW_AUTO_WIDTH_DISABLE,Hardware Autonomous Width Disable. When set this bit disables hardware from changing the Link width for reasons other than attempting to correct unreliable Link operation by reducing Link width. For a Multi-Function Device.." "0,1" bitfld.long 0x10 8. "PCIE_CAP_EN_CLK_POWER_MAN,Enable Clock Power Management. Applicable only for Upstream Ports and with form factors that support a 'Clock Request' (CLKREQ#) mechanism this bit operates as follows: - 0b: Clock power management is disabled and device must.." "0,1" newline bitfld.long 0x10 7. "PCIE_CAP_EXTENDED_SYNCH,Extended Synch. When set this bit forces the transmission of additional Ordered Sets when exiting the L0s state (see section 4.2.4.5 of PCI Express Base Specification) and when in the Recovery state (see section 4.2.6.4.1 of PCI.." "0,1" bitfld.long 0x10 6. "PCIE_CAP_COMMON_CLK_CONFIG,Common Clock Configuration. When set this bit indicates that this component and the component at the opposite end of this Link are operating with a distributed common reference clock. A value of 0b indicates that this.." "0,1" newline bitfld.long 0x10 5. "PCIE_CAP_RETRAIN_LINK,Retrain Link. A write of 1b to this bit initiates Link retraining by directing the Physical Layer LTSSM to the Recovery state. If the LTSSM is already in Recovery or Configuration re-entering Recovery is permitted but not required." "0,1" bitfld.long 0x10 4. "PCIE_CAP_LINK_DISABLE,Link Disable. This bit disables the Link by directing the LTSSM to the Disabled state when set; this bit is Reserved on Endpoints PCI Express to PCI/PCI-X bridges and Upstream Ports of Switches. Writes to this bit are immediately.." "0,1" newline bitfld.long 0x10 3. "PCIE_CAP_RCB,Read Completion Boundary (RCB). Root Ports: Indicates the RCB value for the Root Port. Refer to section 2.3.1.1 of PCI Express Base Specification for the definition of the parameter RCB. Defined encodings are: - 0b: 64 byte - 1b: 128 byte.." "0,1" rbitfld.long 0x10 2. "RSVDP_2,Reserved for future use." "0,1" newline bitfld.long 0x10 0.--1. "PCIE_CAP_ACTIVE_STATE_LINK_PM_CONTROL,Active State Power Management (ASPM) Control. This field controls the level of ASPM enabled on the given PCI Express Link. See section 5.4.1.3 of PCI Express Base Specification for requirements on when and how to.." "0,1,2,3" line.long 0x14 "SLOT_CAPABILITIES_REG,Slot Capabilities Register. The Slot Capabilities register identifies PCI Express slot specific capabilities." hexmask.long.word 0x14 19.--31. 1. "PCIE_CAP_PHY_SLOT_NUM,Physical Slot Number. This field indicates the physical slot number attached to this Port. This field must be hardware initialized to a value that assigns a slot number that is unique within the chassis regardless of the form.." bitfld.long 0x14 18. "PCIE_CAP_NO_CMD_CPL_SUPPORT,No Command Completed Support. When set this bit indicates that this slot does not generate software notification when an issued command is completed by the Hot-Plug Controller. This bit is only permitted to be set if the.." "0,1" newline bitfld.long 0x14 17. "PCIE_CAP_ELECTROMECH_INTERLOCK,Electromechanical Interlock Present. When set this bit indicates that an Electromechanical Interlock is implemented on the chassis for this slot. Note: The access attributes of this field are as follows: - Wire: No access." "0,1" bitfld.long 0x14 15.--16. "PCIE_CAP_SLOT_POWER_LIMIT_SCALE,Slot Power Limit Scale. Specifies the scale used for the Slot Power Limit Value (for more details see Section 6.9 of PCI Express Base Specification). Range of Values: - 00b: 1.0x - 01b: 0.1x - 10b: 0.01x - 11b: 0.001x.." "0,1,2,3" newline hexmask.long.byte 0x14 7.--14. 1. "PCIE_CAP_SLOT_POWER_LIMIT_VALUE,Slot Power Limit Value. In combination with the Slot Power Limit Scale value specifies the upper limit on power supplied by the slot (for more detais see Section 6.9 of PCI Express Base Specification) or by other means.." bitfld.long 0x14 6. "PCIE_CAP_HOT_PLUG_CAPABLE,Hot-Plug Capable. When set this bit indicates that this slot is capable of supporting hot-plug operations. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then R/W else R" "0,1" newline bitfld.long 0x14 5. "PCIE_CAP_HOT_PLUG_SURPRISE,Hot-Plug Surprise. When set this bit indicates that an adapter present in this slot might be removed from the system without any prior notification. This is a form factor specific capability. This bit is an indication to the.." "0,1" bitfld.long 0x14 4. "PCIE_CAP_POWER_INDICATOR,Power Indicator Present. When set this bit indicates that a Power Indicator is electrically controlled by the chassis for this slot. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if.." "0,1" newline bitfld.long 0x14 3. "PCIE_CAP_ATTENTION_INDICATOR,Attention Indicator Present. When set this bit indicates that an Attention Indicator is electrically controlled by the chassis. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if.." "0,1" bitfld.long 0x14 2. "PCIE_CAP_MRL_SENSOR,MRL Sensor Present. When set this bit indicates that an MRL Sensor is implemented on the chassis for this slot. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then R/W else R" "0,1" newline bitfld.long 0x14 1. "PCIE_CAP_POWER_CONTROLLER,Power Controller Present. When set this bit indicates that a software programmable Power Controller is implemented for this slot/adapter (depending on form factor). Note: The access attributes of this field are as follows: -.." "0,1" bitfld.long 0x14 0. "PCIE_CAP_ATTENTION_INDICATOR_BUTTON,Attention Button Present. When set this bit indicates that an Attention Button for this slot is electrically controlled by the chassis. Note: The access attributes of this field are as follows: - Wire: No access. -.." "0,1" line.long 0x18 "SLOT_CONTROL_SLOT_STATUS,Slot Control and Status Register. This register controls and provides information about PCI Express Slot specific parameters." hexmask.long.byte 0x18 25.--31. 1. "RSVDP_25,Reserved for future use." bitfld.long 0x18 24. "PCIE_CAP_DLL_STATE_CHANGED,Data Link Layer State Changed. This bit is set when the value reported in the Data Link Layer Link Active bit of the Link Status register is changed. In response to a Data Link Layer State Changed event software must read the.." "0,1" newline rbitfld.long 0x18 23. "PCIE_CAP_ELECTROMECH_INTERLOCK_STATUS,Electromechanical Interlock Status. If an Electromechanical Interlock is implemented this bit indicates the status of the Electromechanical Interlock. Defined encodings are: - 0b: Electromechanical Interlock.." "0,1" rbitfld.long 0x18 22. "PCIE_CAP_PRESENCE_DETECT_STATE,Presence Detect State. This bit indicates the presence of an adapter in the slot reflected by the logical 'OR' of the Physical Layer in-band presence detect mechanism and if present any out-of-band presence detect.." "0,1" newline rbitfld.long 0x18 21. "PCIE_CAP_MRL_SENSOR_STATE,MRL Sensor State. This bit reports the status of the MRL sensor if implemented. Defined encodings are: - 0b: MRL Closed - 1b: MRL Open" "0,1" bitfld.long 0x18 20. "PCIE_CAP_CMD_CPLD,Command Completed. If Command Completed notification is supported (if the No Command Completed Support bit in the Slot Capabilities register is 0b) this bit is set when a hot-plug command has completed and the Hot-Plug Controller is.." "0,1" newline bitfld.long 0x18 19. "PCIE_CAP_PRESENCE_DETECTED_CHANGED,Presence Detect Changed. This bit is set when the value reported in the Presence Detect State bit is changed." "0,1" bitfld.long 0x18 18. "PCIE_CAP_MRL_SENSOR_CHANGED,MRL Sensor Changed. If an MRL sensor is implemented this bit is set when a MRL Sensor state change is detected. If an MRL sensor is not implemented this bit must not be set." "0,1" newline bitfld.long 0x18 17. "PCIE_CAP_POWER_FAULT_DETECTED,Power Fault Detected. If a Power Controller that supports power fault detection is implemented this bit issSet when the Power Controller detects a power fault at this slot. Note: Depending on hardware capability it is.." "0,1" bitfld.long 0x18 16. "PCIE_CAP_ATTENTION_BUTTON_PRESSED,Attention Button Pressed. If an Attention Button is implemented this bit is set when the attention button is pressed. If an Attention Button is not supported this bit must not be set." "0,1" newline rbitfld.long 0x18 14.--15. "RSVDP_14,Reserved for future use." "0,1,2,3" bitfld.long 0x18 12. "PCIE_CAP_DLL_STATE_CHANGED_EN,Data Link Layer State Changed Enable. If the Data Link Layer Link Active Reporting capability is 1b this bit enables software notification when Data Link Layer Link Active bit is changed. If the Data Link Layer Link Active.." "0,1" newline bitfld.long 0x18 11. "PCIE_CAP_ELECTROMECH_INTERLOCK_CTRL,Electromechanical Interlock Control. If an Electromechanical Interlock is implemented a write of 1b to this bit causes the state of the interlock to toggle. A write of 0b to this bit has no effect. A read of this bit.." "0,1" bitfld.long 0x18 10. "PCIE_CAP_POWER_CONTROLLER_CTRL,Power Controller Control. If a Power Controller is implemented this bit when written sets the power state of the slot per the defined encodings. Reads of this bit must reflect the value from the latest write even if the.." "0,1" newline bitfld.long 0x18 8.--9. "PCIE_CAP_POWER_INDICATOR_CTRL,Power Indicator Control. If a Power Indicator is implemented writes to this field set the Power Indicator to the written state. Reads of this field must reflect the value from the latest write even if the corresponding.." "0,1,2,3" bitfld.long 0x18 6.--7. "PCIE_CAP_ATTENTION_INDICATOR_CTRL,Attention Indicator Control. If an Attention Indicator is implemented writes to this field set the Attention Indicator to the written state. Reads of this field must reflect the value from the latest write even if the.." "0,1,2,3" newline bitfld.long 0x18 5. "PCIE_CAP_HOT_PLUG_INT_EN,Hot-Plug Interrupt Enable. When set this bit enables generation of an interrupt on enabled hot-plug events. If the Hot Plug Capable bit in the Slot Capabilities register is clear this bit is permitted to be read-only with a.." "0,1" bitfld.long 0x18 4. "PCIE_CAP_CMD_CPL_INT_EN,Command Completed Interrupt Enable. If Command Completed notification is supported (if the No Command Completed Support bit in the Slot Capabilities register is 0b) when set this bit enables software notification when a hot-plug.." "0,1" newline bitfld.long 0x18 3. "PCIE_CAP_PRESENCE_DETECT_CHANGE_EN,Presence Detect Changed Enable. When set this bit enables software notification on a presence detect changed event (for more details see Section 6.7.3 of PCI Express Base Specification). If the Hot-Plug Capable bit in.." "0,1" bitfld.long 0x18 2. "PCIE_CAP_MRL_SENSOR_CHANGED_EN,MRL Sensor Changed Enable. When set this bit enables software notification on a MRL sensor changed event (for more details see Section 6.7.3 of PCI Express Base Specification). If the MRL Sensor Present bit in the Slot.." "0,1" newline bitfld.long 0x18 1. "PCIE_CAP_POWER_FAULT_DETECTED_EN,Power Fault Detected Enable. When set this bit enables software notification on a power fault event (for more details see Section 6.7.3 of PCI Express Base Specification). If a Power Controller that supports power fault.." "0,1" bitfld.long 0x18 0. "PCIE_CAP_ATTENTION_BUTTON_PRESSED_EN,Attention Button Pressed Enable. When set to 1b this bit enables software notification on an attention button pressed event (for more details see Section 6.7.3 of PCI Express Base Specification). If the Attention.." "0,1" line.long 0x1C "ROOT_CONTROL_ROOT_CAPABILITIES_REG,Root Control and Capabilities Register. This register controls PCI Express Root Complex specific parameters and identifies PCI Express Root Port specific capabilities." hexmask.long.word 0x1C 17.--31. 1. "RSVDP_17,Reserved for future use." bitfld.long 0x1C 16. "PCIE_CAP_CRS_SW_VISIBILITY,CRS Software Visibility Capable. For a description of this standard PCIe register field see the PCI Express Base Specification. CRS Software Visibility. When set this bit indicates that the Root Port is capable of returning.." "0,1" newline hexmask.long.word 0x1C 5.--15. 1. "RSVDP_5,Reserved for future use." bitfld.long 0x1C 4. "PCIE_CAP_CRS_SW_VISIBILITY_EN,CRS Software Visibility Enable. When set this bit enables the Root Port to return Configuration Request Retry Status (CRS) Completion Status to software (for more details see section 2.3.1 of PCI Express Base.." "0,1" newline bitfld.long 0x1C 3. "PCIE_CAP_PME_INT_EN,PME Interrupt Enable. When set this bit enables PME interrupt generation upon receipt of a PME Message as reflected in the PME Status bit (for more details see Table 7-29 of PCI Express Base Specification). A PME interrupt is also.." "0,1" bitfld.long 0x1C 2. "PCIE_CAP_SYS_ERR_ON_FATAL_ERR_EN,System Error on Fatal Error Enable. If set this bit indicates that a System Error should be generated if a Fatal error (ERR_FATAL) is reported by any of the devices in the Hierarchy Domain associated with this Root Port.." "0,1" newline bitfld.long 0x1C 1. "PCIE_CAP_SYS_ERR_ON_NON_FATAL_ERR_EN,System Error on Non-Fatal Error Enable. If set this bit indicates that a System Error should be generated if a Non-fatal error (ERR_NONFATAL) is reported by any of the devices in the Hierarchy Domain associated with.." "0,1" bitfld.long 0x1C 0. "PCIE_CAP_SYS_ERR_ON_CORR_ERR_EN,System Error on Correctable Error Enable. If set this bit indicates that a System Error should be generated if a correctable error (ERR_COR) is reported by any of the devices in the Hierarchy Domain associated with this.." "0,1" line.long 0x20 "ROOT_STATUS_REG,Root Status Register. The Root Status register provides information about PCI Express device specific parameters." hexmask.long.word 0x20 18.--31. 1. "RSVDP_18,Reserved for future use." rbitfld.long 0x20 17. "PCIE_CAP_PME_PENDING,PME Pending. This bit indicates that another PME is pending when the PME Status bit is s et. When the PME Status bit is cleared by software; the PME is delivered by hardware by setting the PME Status bit again and updating the PME.." "0,1" newline bitfld.long 0x20 16. "PCIE_CAP_PME_STATUS,PME Status. This bit indicates that PME was asserted by the PME Requester indicated in the PME Requester ID field. Subsequent PMEs are kept pending until the status register is cleared by software by writing a 1b." "0,1" hexmask.long.word 0x20 0.--15. 1. "PCIE_CAP_PME_REQ_ID,PME Requester ID. This field indicates the PCI Requester ID of the last PME Requester. This field is only valid when the PME Status bit is set." line.long 0x24 "DEVICE_CAPABILITIES2_REG,Device Capabilities 2 Register." bitfld.long 0x24 31. "PCIE_CAP_FRS_SUPPORTED,FRS Supported. When set indicates support for the optional Function Readiness Status (FRS) capability. Must be set for all Functions that support generation or reception capabilities of FRS Messages. Must not be set by Switch.." "0,1" hexmask.long.byte 0x24 24.--30. 1. "RSVDP_24,Reserved for future use." newline bitfld.long 0x24 22.--23. "PCIE_CAP2_CFG_MAX_END2END_TLP_PRFXS,Max End-End TLP Prefixes. Indicates the maximum number of End-End TLP Prefixes supported by this Function. For more details see Section 2.2.10.2 of PCI Express Base Specification. Values are: - 01b: 1 End-End TLP.." "0,1,2,3" bitfld.long 0x24 21. "PCIE_CAP2_CFG_END2END_TLP_PRFX_SUPPORT,End-End TLP Prefix Supported. Indicates whether End-End TLP Prefix support is offered by a Function. Values are: - 0b: No Support - 1b: Support is provided to receive TLPs containing End-End TLP Prefixes. All Ports.." "0,1" newline bitfld.long 0x24 20. "PCIE_CAP2_CFG_EXTND_FMT_SUPPORT,Extended Fmt Field Supported. If set the Function supports the 3-bit definition of the Fmt field. If clear the Function supports a 2-bit definition of the Fmt field. For more details see section 2.2 of PCI Express Base.." "0,1" rbitfld.long 0x24 17. "PCIE_CAP2_10_BIT_TAG_REQ_SUPPORT,10-Bit Tag Requester Supported. If this bit is set the Function supports 10-Bit Tag Requester capability; otherwise the Function does not. This bit must not be set if the 10-Bit Tag Completer Supported bit is clear." "0,1" newline rbitfld.long 0x24 16. "PCIE_CAP2_10_BIT_TAG_COMP_SUPPORT,10-Bit Tag Completer Supported. If this bit is set the Function supports 10-Bit Tag Completer capability; otherwise the Function does not. For more details see section 2.2.6.2. of PCI Express Base Specification." "0,1" rbitfld.long 0x24 13. "PCIE_CAP_TPH_CMPLT_SUPPORT_1,TPH Completer Supported Bit 1." "0,1" newline rbitfld.long 0x24 12. "PCIE_CAP_TPH_CMPLT_SUPPORT_0,TPH Completer Supported Bit 0. Value of this bit along with TPH Completer Supported Bit 1 indicates Completer support for TPH or Extended TPH. Applicable only to Root Ports and Endpoints. For all other Functions this field.." "0,1" bitfld.long 0x24 11. "PCIE_CAP_LTR_SUPP,LTR Mechanism Supported. A value of 1b indicates support for the optional Latency Tolerance Reporting (LTR) mechanism. Root Ports Switches and Endpoints are permitted to implement this capability. For a Multi-Function Device associated.." "0,1" newline rbitfld.long 0x24 10. "PCIE_CAP_NO_RO_EN_PR2PR_PAR,No RO-enabled PR-PR Passing. If this bit is set the routing element never carries out the passing permitted by Table 2-39 of PCI Express Base Specification entry A2b that is associated with the Relaxed Ordering Attribute.." "0,1" rbitfld.long 0x24 9. "PCIE_CAP_128_CAS_CPL_SUPP,128-bit CAS Completer Supported. Applicable to Functions with Memory Space BARs as well as all Root Ports; must be 0b otherwise. This bit must be set to 1b if the Function supports this optional capability. For more details see.." "0,1" newline rbitfld.long 0x24 8. "PCIE_CAP_64_ATOMIC_CPL_SUPP,64-bit AtomicOp Completer Supported. Applicable to Functions with Memory Space BARs as well as all Root Ports; must be 0b otherwise. Includes FetchAdd Swap and CAS AtomicOps. This bit must be set to 1b if the Function.." "0,1" rbitfld.long 0x24 7. "PCIE_CAP_32_ATOMIC_CPL_SUPP,32-bit AtomicOp Completer Supported. Applicable to Functions with Memory Space BARs as well as all Root Ports; must be 0b otherwise. Includes FetchAdd Swap and CAS AtomicOps. This bit must be set to 1b if the Function.." "0,1" newline rbitfld.long 0x24 6. "PCIE_CAP_ATOMIC_ROUTING_SUPP,AtomicOp Routing Supported. Applicable only to Switch Upstream Ports Switch Downstream Ports and Root Ports; must be 0b for other Function types. This bit must be set to 1b if the Port supports this optional capability. For.." "0,1" rbitfld.long 0x24 5. "PCIE_CAP_ARI_FORWARD_SUPPORT,ARI Forwarding Supported. Applicable only to Switch Downstream Ports and Root Ports; must be 0b for other Function types. This bit must be set to 1b if a Switch Downstream Port or Root Port supports this optional capability." "0,1" newline rbitfld.long 0x24 4. "PCIE_CAP_CPL_TIMEOUT_DISABLE_SUPPORT,Completion Timeout Disable Supported. A value of 1b indicates support for the Completion Timeout Disable mechanism. The Completion Timeout Disable mechanism is required for Endpoints that issue Requests on their own.." "0,1" hexmask.long.byte 0x24 0.--3. 1. "PCIE_CAP_CPL_TIMEOUT_RANGE,Completion Timeout Ranges Supported. This field indicates device Function support for the optional Completion Timeout programmability mechanism. This mechanism allows system software to modify the Completion Timeout value. This.." line.long 0x28 "DEVICE_CONTROL2_DEVICE_STATUS2_REG,Device Control 2 and Status 2 Register." hexmask.long.word 0x28 16.--31. 1. "RSVDP_16,Reserved for future use." bitfld.long 0x28 15. "PCIE_CTRL2_CFG_END2END_TLP_PFX_BLCK,End-End TLP Prefix Blocking. Controls whether the routing function is permitted to forward TLPs containing an End-End TLP Prefix. Values are: - 0b: Forwarding Enabled - Function is permitted to send TLPs with End-End.." "0,1" newline rbitfld.long 0x28 11. "RSVDP_11,Reserved for future use." "0,1" bitfld.long 0x28 10. "PCIE_CAP_LTR_EN,LTR Mechanism Enable. When set to 1b this bit enables Upstream Ports to send LTR messages and Downstream Ports to process LTR Messages. For a Multi-Function Device associated with an Upstream Port of a device that implements LTR the bit.." "0,1" newline rbitfld.long 0x28 5. "PCIE_CAP_ARI_FORWARD_SUPPORT_CS,ARI Forwarding Enable. When set the Downstream Port disables its traditional Device Number field being 0 enforcement when turning a Type 1 Configuration Request into a Type 0 Configuration Request permitting access to.." "0,1" bitfld.long 0x28 4. "PCIE_CAP_CPL_TIMEOUT_DISABLE,Completion Timeout Disable. When set this bit disables the Completion Timeout mechanism. This bit is required for all Functions that support the Completion Timeout Disable Capability. Functions that do not support this.." "0,1" newline hexmask.long.byte 0x28 0.--3. 1. "PCIE_CAP_CPL_TIMEOUT_VALUE,Completion Timeout Value. In device Functions that support Completion Timeout programmability this field allows system software to modify the Completion Timeout value. This field is applicable to Root Ports Endpoints that.." line.long 0x2C "LINK_CAPABILITIES2_REG,Link Capabilities 2 Register." bitfld.long 0x2C 31. "DRS_SUPPORTED,DRS Supported. When set indicates support for the optional Device Readiness Status (DRS) capability. Must be Set in Downstream Ports that support DRS. Must be Set in Downstream Ports that support FRS. For Upstream Ports that support DRS.." "0,1" hexmask.long.byte 0x2C 25.--30. 1. "RSVDP_25,Reserved for future use." newline hexmask.long.word 0x2C 9.--22. 1. "RSVDP_9,Reserved for future use." rbitfld.long 0x2C 8. "PCIE_CAP_CROSS_LINK_SUPPORT,Crosslink Supported. When set to 1b this bit indicates that the associated Port supports crosslinks (for more details see section 4.2.6.3.1 of PCI Express Base Specification). When set to 0b on a Port that supports Link.." "0,1" newline hexmask.long.byte 0x2C 1.--7. 1. "PCIE_CAP_SUPPORT_LINK_SPEED_VECTOR,Supported Link Speeds Vector. This field indicates the supported Link speed(s) of the associated Port. For each bit a value of 1b indicates that the corresponding Link speed is supported; otherwise the Link speed is.." rbitfld.long 0x2C 0. "RSVDP_0,Reserved for future use." "0,1" line.long 0x30 "LINK_CONTROL2_LINK_STATUS2_REG,Link Control 2 and Status 2 Register." bitfld.long 0x30 31. "DRS_MESSAGE_RECEIVED,DRS Message Received. This bit must be set whenever the Port receives a DRS Message. This bit must be cleared in DL_Down. This bit must be implemented in any Downstream Port where the DRS Supported bit is Set in the Link Capabilities.." "0,1" rbitfld.long 0x30 28.--30. "DOWNSTREAM_COMPO_PRESENCE,Downstream Component Presence. This field indicates the presence and DRS status for the Downstream Component if any connected to the Link; defined values are: - 000b: Link Down - Presence Not Determined - 001b: Link Down -.." "0,1,2,3,4,5,6,7" newline rbitfld.long 0x30 26.--27. "RSVDP_26,Reserved for future use." "0,1,2,3" bitfld.long 0x30 21. "PCIE_CAP_LINK_EQ_REQ,Link Equalization Request 8.0 GT/s. This bit is set by hardware to request the 8.0 GT/s Link equalization process to be performed on the Link. For more details see sections 4.2.3 and 4.2.6.4.2 of PCI Express Base Specification. For.." "0,1" newline rbitfld.long 0x30 20. "PCIE_CAP_EQ_CPL_P3,EEqualization 8.0 GT/s Phase 3 Successful. When set to 1b this bit indicates that Phase 3 of the 8.0 GT/s Transmitter Equalization procedure has successfully completed. Details of the Transmitter Equalization process and when this bit.." "0,1" rbitfld.long 0x30 19. "PCIE_CAP_EQ_CPL_P2,Equalization 8.0 GT/s Phase 2 Successful. When set to 1b this bit indicates that Phase 2 of the 8.0 GT/s Transmitter Equalization procedure has successfully completed. Details of the Transmitter Equalization process and when this bit.." "0,1" newline rbitfld.long 0x30 18. "PCIE_CAP_EQ_CPL_P1,Equalization 8.0 GT/s Phase 1 Successful. When set to 1b this bit indicates that Phase 1 of the 8.0 GT/s Transmitter Equalization procedure has successfully completed. Details of the Transmitter Equalization process and when this bit.." "0,1" rbitfld.long 0x30 17. "PCIE_CAP_EQ_CPL,Equalization 8.0 GT/s Complete. When set to 1b this bit indicates that the Transmitter Equalization procedure at the 8.0 GT/s data rate has completed. Details of the Transmitter Equalization process and when this bit needs to be set to.." "0,1" newline rbitfld.long 0x30 16. "PCIE_CAP_CURR_DEEMPHASIS,Current De-emphasis Level. When the Link is operating at 5.0 GT/s speed this bit reflects the level of de-emphasis. Encodings: - 1b: -3.5 dB - 0b: -6 dB The value in this bit is undefined when the Link is not operating at 5.0.." "0,1" hexmask.long.byte 0x30 12.--15. 1. "PCIE_CAP_COMPLIANCE_PRESET,Compliance Preset/De-emphasis. For 8.0 GT/s and higher Data Rate: This field sets the Transmitter Preset in Polling.Compliance state if the entry occurred due to the Enter Compliance bit being 1b. The encodings are defined in.." newline bitfld.long 0x30 11. "PCIE_CAP_COMPLIANCE_SOS,Compliance SOS. When set to 1b the LTSSM is required to send SKP Ordered Sets between sequences when sending the Compliance Pattern or Modified Compliance Pattern. For a Multi-Function Device associated with an Upstream Port the.." "0,1" bitfld.long 0x30 10. "PCIE_CAP_ENTER_MODIFIED_COMPLIANCE,Enter Modified Compliance. When this bit is set to 1b the device transmits Modified Compliance Pattern if the LTSSM enters Polling.Compliance substate. Components that support only the 2.5 GT/s speed are permitted to.." "0,1" newline bitfld.long 0x30 7.--9. "PCIE_CAP_TX_MARGIN,Transmit Margin - This field controls the value of the non-deemphasized voltage level at the Transmitter pins. This field is reset to 000b on entry to the LTSSM Polling.Configuration substate (see Chapter 4 of PCI Express Base.." "0,1,2,3,4,5,6,7" bitfld.long 0x30 6. "PCIE_CAP_SEL_DEEMPHASIS,Selectable De-emphasis. When the Link is operating at 5.0 GT/s speed this bit is used to control the transmit de-emphasis of the link in specific situations. For more details see section 4.2.6 of PCI Express Base Specification." "0,1" newline bitfld.long 0x30 5. "PCIE_CAP_HW_AUTO_SPEED_DISABLE,Hardware Autonomous Speed Disable. When set this bit disables hardware from changing the Link speed for device-specific reasons other than attempting to correct unreliable Link operation by reducing Link speed. Initial.." "0,1" bitfld.long 0x30 4. "PCIE_CAP_ENTER_COMPLIANCE,Enter Compliance. Software is permitted to force a Link to enter Compliance mode (at the speed indicated in the Target Link Speed field and the de-emphasis/preset level indicated by the Compliance Preset/De-emphasis field) by.." "0,1" newline hexmask.long.byte 0x30 0.--3. 1. "PCIE_CAP_TARGET_LINK_SPEED,Target Link Speed. For Downstream Ports this field sets an upper limit on Link operational speed by restricting the values advertised by the Upstream component in its training sequences. The encoded value specifies a bit.." tree.end tree "PF0_AER_CAP (PF Advanced Error Reporting Capability Structure)" group.long (0x0+0x100)++0x1B line.long 0x0 "AER_EXT_CAP_HDR_OFF,Advanced Error Reporting Extended Capability Header. For a description of this standard PCIe register. see the PCI Express Specification." hexmask.long.word 0x0 20.--31. 1. "NEXT_OFFSET,Next Capability Offset. For a description of this standard PCIe register field see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky).." hexmask.long.byte 0x0 16.--19. 1. "CAP_VERSION,Capability Version. For a description of this standard PCIe register field see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else.." hexmask.long.word 0x0 0.--15. 1. "CAP_ID,AER Extended Capability ID. For a description of this standard PCIe register field see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else.." line.long 0x4 "UNCORR_ERR_STATUS_OFF,Uncorrectable Error Status Register. For a description of this standard PCIe register. see the PCI Express Specification." hexmask.long.byte 0x4 27.--31. 1. "RSVDP_27,Reserved for future use." bitfld.long 0x4 25. "TLP_PRFX_BLOCKED_ERR_STATUS,TLP Prefix Blocked Error Status. For a description of this standard PCIe register field see the PCI Express Specification. Note: Not supported." "0,1" rbitfld.long 0x4 23. "RSVDP_23,Reserved for future use." "0,1" newline bitfld.long 0x4 22. "INTERNAL_ERR_STATUS,Uncorrectable Internal Error Status. For a description of this standard PCIe register field see the PCI Express Specification. The controller sets this bit when your application asserts app_err_bus[9]. It does not set this bit when.." "0,1" bitfld.long 0x4 20. "UNSUPPORTED_REQ_ERR_STATUS,Unsupported Request Error Status. For a description of this standard PCIe register field see the PCI Express Specification." "0,1" bitfld.long 0x4 19. "ECRC_ERR_STATUS,ECRC Error Status. For a description of this standard PCIe register field see the PCI Express Specification. Note:If CX_ECRC_ENABLE=0 the register field always reads 0." "0,1" newline bitfld.long 0x4 18. "MALF_TLP_ERR_STATUS,Malformed TLP Status. For a description of this standard PCIe register field see the PCI Express Specification." "0,1" bitfld.long 0x4 17. "REC_OVERFLOW_ERR_STATUS,Receiver Overflow Status. For a description of this standard PCIe register field see the PCI Express Specification." "0,1" bitfld.long 0x4 16. "UNEXP_CMPLT_ERR_STATUS,Unexpected Completion Status. For a description of this standard PCIe register field see the PCI Express Specification." "0,1" newline bitfld.long 0x4 15. "CMPLT_ABORT_ERR_STATUS,Completer Abort Status. For a description of this standard PCIe register field see the PCI Express Specification." "0,1" bitfld.long 0x4 14. "CMPLT_TIMEOUT_ERR_STATUS,Completion Timeout Status. For a description of this standard PCIe register field see the PCI Express Specification." "0,1" bitfld.long 0x4 13. "FC_PROTOCOL_ERR_STATUS,Flow Control Protocol Error Status. For a description of this standard PCIe register field see the PCI Express Specification." "0,1" newline bitfld.long 0x4 12. "POIS_TLP_ERR_STATUS,Poisoned TLP Status. For a description of this standard PCIe register field see the PCI Express Specification." "0,1" hexmask.long.byte 0x4 6.--11. 1. "RSVDP_6,Reserved for future use." bitfld.long 0x4 5. "SURPRISE_DOWN_ERR_STATUS,Surprise Down Error Status (Optional). For a description of this standard PCIe register field see the PCI Express Specification." "0,1" newline bitfld.long 0x4 4. "DL_PROTOCOL_ERR_STATUS,Data Link Protocol Error Status. For a description of this standard PCIe register field see the PCI Express Specification." "0,1" hexmask.long.byte 0x4 0.--3. 1. "RSVDP_0,Reserved for future use." line.long 0x8 "UNCORR_ERR_MASK_OFF,Uncorrectable Error Mask Register. For a description of this standard PCIe register. see the PCI Express Specification." hexmask.long.byte 0x8 27.--31. 1. "RSVDP_27,Reserved for future use." bitfld.long 0x8 25. "TLP_PRFX_BLOCKED_ERR_MASK,TLP Prefix Blocked Error Mask. For a description of this standard PCIe register field see the PCI Express Specification. Note: Not supported. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi:.." "0,1" rbitfld.long 0x8 23. "RSVDP_23,Reserved for future use." "0,1" newline bitfld.long 0x8 22. "INTERNAL_ERR_MASK,Uncorrectable Internal Error Mask (Optional). For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." "0,1" rbitfld.long 0x8 21. "ACS_VIOLATION_MASK,ACS Violation Mask. Setting the ACS Violation Mask bit disables error logging and signaling for ACS Violation errors. The bit is Read-Only Zero for upstream ports when ACS P2P Egress Control Enable is not set. For a description of.." "0,1" bitfld.long 0x8 20. "UNSUPPORTED_REQ_ERR_MASK,Unsupported Request Error Mask. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." "0,1" newline bitfld.long 0x8 19. "ECRC_ERR_MASK,ECRC Error Mask (Optional). For a description of this standard PCIe register field see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W (sticky) Note: This register.." "0,1" bitfld.long 0x8 18. "MALF_TLP_ERR_MASK,Malformed TLP Mask. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." "0,1" bitfld.long 0x8 17. "REC_OVERFLOW_ERR_MASK,Receiver Overflow Mask (Optional). For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." "0,1" newline bitfld.long 0x8 16. "UNEXP_CMPLT_ERR_MASK,Unexpected Completion Mask. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." "0,1" bitfld.long 0x8 15. "CMPLT_ABORT_ERR_MASK,Completer Abort Error Mask (Optional). For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." "0,1" bitfld.long 0x8 14. "CMPLT_TIMEOUT_ERR_MASK,Completion Timeout Error Mask. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." "0,1" newline bitfld.long 0x8 13. "FC_PROTOCOL_ERR_MASK,Flow Control Protocol Error Mask. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." "0,1" bitfld.long 0x8 12. "POIS_TLP_ERR_MASK,Poisoned TLP Error Mask. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." "0,1" hexmask.long.byte 0x8 6.--11. 1. "RSVDP_6,Reserved for future use." newline rbitfld.long 0x8 5. "SURPRISE_DOWN_ERR_MASK,Surprise Down Error Mask. For a description of this standard PCIe register field see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi:.." "0,1" bitfld.long 0x8 4. "DL_PROTOCOL_ERR_MASK,Data Link Protocol Error Mask. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." "0,1" hexmask.long.byte 0x8 0.--3. 1. "RSVDP_0,Reserved for future use." line.long 0xC "UNCORR_ERR_SEV_OFF,Uncorrectable Error Severity Register. For a description of this standard PCIe register. see the PCI Express Specification." hexmask.long.byte 0xC 27.--31. 1. "RSVDP_27,Reserved for future use." bitfld.long 0xC 25. "TLP_PRFX_BLOCKED_ERR_SEVERITY,TLP Prefix Blocked Error Severity (Optional). For a description of this standard PCIe register field see the PCI Express Specification. Note: Not supported. Note: The access attributes of this field are as follows: - Wire:.." "0,1" rbitfld.long 0xC 24. "ATOMIC_EGRESS_BLOCKED_ERR_SEVERITY,AtomicOp Egress Blocked Severity (Optional). For a description of this standard PCIe register field see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi:.." "0,1" newline rbitfld.long 0xC 23. "RSVDP_23,Reserved for future use." "0,1" bitfld.long 0xC 22. "INTERNAL_ERR_SEVERITY,Uncorrectable Internal Error Severity (Optional). For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." "0,1" bitfld.long 0xC 20. "UNSUPPORTED_REQ_ERR_SEVERITY,Unsupported Request Error Severity. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." "0,1" newline bitfld.long 0xC 19. "ECRC_ERR_SEVERITY,ECRC Error Severity (Optional). For a description of this standard PCIe register field see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W (sticky) Note: This.." "0,1" bitfld.long 0xC 18. "MALF_TLP_ERR_SEVERITY,Malformed TLP Severity. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." "0,1" bitfld.long 0xC 17. "REC_OVERFLOW_ERR_SEVERITY,Receiver Overflow Error Severity (Optional). For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." "0,1" newline bitfld.long 0xC 16. "UNEXP_CMPLT_ERR_SEVERITY,Unexpected Completion Error Severity. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." "0,1" bitfld.long 0xC 15. "CMPLT_ABORT_ERR_SEVERITY,Completer Abort Error Severity (Optional). For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." "0,1" bitfld.long 0xC 14. "CMPLT_TIMEOUT_ERR_SEVERITY,Completion Timeout Error Severity. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." "0,1" newline bitfld.long 0xC 13. "FC_PROTOCOL_ERR_SEVERITY,Flow Control Protocol Error Severity (Optional). For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." "0,1" bitfld.long 0xC 12. "POIS_TLP_ERR_SEVERITY,Poisoned TLP Severity. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." "0,1" hexmask.long.byte 0xC 6.--11. 1. "RSVDP_6,Reserved for future use." newline rbitfld.long 0xC 5. "SURPRISE_DOWN_ERR_SVRITY,Surprise Down Error Severity (Optional). For a description of this standard PCIe register field see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi:.." "0,1" bitfld.long 0xC 4. "DL_PROTOCOL_ERR_SEVERITY,Data Link Protocol Error Severity. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." "0,1" hexmask.long.byte 0xC 0.--3. 1. "RSVDP_0,Reserved for future use." line.long 0x10 "CORR_ERR_STATUS_OFF,Correctable Error Status Register. For a description of this standard PCIe register. see the PCI Express Specification." hexmask.long.word 0x10 16.--31. 1. "RSVDP_16,Reserved for future use." bitfld.long 0x10 15. "HEADER_LOG_OVERFLOW_STATUS,Header Log Overflow Error Status (Optional). For a description of this standard PCIe register field see the PCI Express Specification." "0,1" bitfld.long 0x10 14. "CORRECTED_INT_ERR_STATUS,Corrected Internal Error Status (Optional). For a description of this standard PCIe register field see the PCI Express Specification." "0,1" newline bitfld.long 0x10 13. "ADVISORY_NON_FATAL_ERR_STATUS,Advisory Non-Fatal Error Status. For a description of this standard PCIe register field see the PCI Express Specification." "0,1" bitfld.long 0x10 12. "RPL_TIMER_TIMEOUT_STATUS,Replay Timer Timeout Status. For a description of this standard PCIe register field see the PCI Express Specification." "0,1" rbitfld.long 0x10 9.--11. "RSVDP_9,Reserved for future use." "0,1,2,3,4,5,6,7" newline bitfld.long 0x10 8. "REPLAY_NO_ROLEOVER_STATUS,REPLAY_NUM Rollover Status. For a description of this standard PCIe register field see the PCI Express Specification." "0,1" bitfld.long 0x10 7. "BAD_DLLP_STATUS,Bad DLLP Status. For a description of this standard PCIe register field see the PCI Express Specification." "0,1" bitfld.long 0x10 6. "BAD_TLP_STATUS,Bad TLP Status. For a description of this standard PCIe register field see the PCI Express Specification." "0,1" newline hexmask.long.byte 0x10 1.--5. 1. "RSVDP_1,Reserved for future use." bitfld.long 0x10 0. "RX_ERR_STATUS,Receiver Error Status (Optional). For a description of this standard PCIe register field see the PCI Express Specification." "0,1" line.long 0x14 "CORR_ERR_MASK_OFF,Correctable Error Mask Register. For a description of this standard PCIe register. see the PCI Express Specification." hexmask.long.word 0x14 16.--31. 1. "RSVDP_16,Reserved for future use." bitfld.long 0x14 15. "HEADER_LOG_OVERFLOW_MASK,Header Log Overflow Error Mask (Optional). For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." "0,1" bitfld.long 0x14 14. "CORRECTED_INT_ERR_MASK,Corrected Internal Error Mask (Optional). For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." "0,1" newline bitfld.long 0x14 13. "ADVISORY_NON_FATAL_ERR_MASK,Advisory Non-Fatal Error Mask. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." "0,1" bitfld.long 0x14 12. "RPL_TIMER_TIMEOUT_MASK,Replay Timer Timeout Mask. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." "0,1" rbitfld.long 0x14 9.--11. "RSVDP_9,Reserved for future use." "0,1,2,3,4,5,6,7" newline bitfld.long 0x14 8. "REPLAY_NO_ROLEOVER_MASK,REPLAY_NUM Rollover Mask. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." "0,1" bitfld.long 0x14 7. "BAD_DLLP_MASK,Bad DLLP Mask. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." "0,1" bitfld.long 0x14 6. "BAD_TLP_MASK,Bad TLP Mask. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." "0,1" newline hexmask.long.byte 0x14 1.--5. 1. "RSVDP_1,Reserved for future use." bitfld.long 0x14 0. "RX_ERR_MASK,Receiver Error Mask (Optional). For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." "0,1" line.long 0x18 "ADV_ERR_CAP_CTRL_OFF,Advanced Error Capabilities and Control Register. For a description of this standard PCIe register. see the PCI Express Specification." hexmask.long.tbyte 0x18 13.--31. 1. "RSVDP_13,Reserved for future use." rbitfld.long 0x18 12. "CTO_PRFX_HDR_LOG_CAP,TLP Prefix Log Present. For a description of this standard PCIe register field see the PCI Express Specification." "0,1" rbitfld.long 0x18 11. "TLP_PRFX_LOG_PRESENT,Completion Timeout Prefix/Header Log Capable. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." "0,1" newline rbitfld.long 0x18 10. "MULTIPLE_HEADER_EN,Multiple Header Recording Enable. For a description of this standard PCIe register field see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R (sticky) Note: This.." "0,1" rbitfld.long 0x18 9. "MULTIPLE_HEADER_CAP,Multiple Header Recording Capable. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." "0,1" bitfld.long 0x18 8. "ECRC_CHECK_EN,ECRC Check Enable. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." "0,1" newline rbitfld.long 0x18 7. "ECRC_CHECK_CAP,ECRC Check Capable. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." "0,1" bitfld.long 0x18 6. "ECRC_GEN_EN,ECRC Generation Enable. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." "0,1" rbitfld.long 0x18 5. "ECRC_GEN_CAP,ECRC Generation Capable. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." "0,1" newline hexmask.long.byte 0x18 0.--4. 1. "FIRST_ERR_POINTER,First Error Pointer. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." rgroup.long (0x1C+0x100)++0xF line.long 0x0 "HDR_LOG_0_OFF,Header Log Register 0. For a description of this standard PCIe register. see the PCI Express Specification." hexmask.long.byte 0x0 24.--31. 1. "FIRST_DWORD_FOURTH_BYTE,Byte 3 of Header log register of First 32 bit Data Word. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." hexmask.long.byte 0x0 16.--23. 1. "FIRST_DWORD_THIRD_BYTE,Byte 2 of Header log register of First 32 bit Data Word. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." hexmask.long.byte 0x0 8.--15. 1. "FIRST_DWORD_SECOND_BYTE,Byte 1 of Header log register of First 32 bit Data Word. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." newline hexmask.long.byte 0x0 0.--7. 1. "FIRST_DWORD_FIRST_BYTE,Byte 0 of Header log register of First 32 bit Data Word. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." line.long 0x4 "HDR_LOG_1_OFF,Header Log Register 1. For a description of this standard PCIe register. see the PCI Express Specification." hexmask.long.byte 0x4 24.--31. 1. "SECOND_DWORD_FOURTH_BYTE,Byte 3 of Header log register of Second 32 bit Data Word. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." hexmask.long.byte 0x4 16.--23. 1. "SECOND_DWORD_THIRD_BYTE,Byte 2 of Header log register of Second 32 bit Data Word. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." hexmask.long.byte 0x4 8.--15. 1. "SECOND_DWORD_SECOND_BYTE,Byte 1 of Header log register of Second 32 bit Data Word. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." newline hexmask.long.byte 0x4 0.--7. 1. "SECOND_DWORD_FIRST_BYTE,Byte 0 of Header log register of Second 32 bit Data Word. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." line.long 0x8 "HDR_LOG_2_OFF,Header Log Register 2. For a description of this standard PCIe register. see the PCI Express Specification." hexmask.long.byte 0x8 24.--31. 1. "THIRD_DWORD_FOURTH_BYTE,Byte 3 of Header log register of Third 32 bit Data Word. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." hexmask.long.byte 0x8 16.--23. 1. "THIRD_DWORD_THIRD_BYTE,Byte 2 of Header log register of Third 32 bit Data Word. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." hexmask.long.byte 0x8 8.--15. 1. "THIRD_DWORD_SECOND_BYTE,Byte 1 of Header log register of Third 32 bit Data Word. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." newline hexmask.long.byte 0x8 0.--7. 1. "THIRD_DWORD_FIRST_BYTE,Byte 0 of Header log register of Third 32 bit Data Word. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." line.long 0xC "HDR_LOG_3_OFF,Header Log Register 3. For a description of this standard PCIe register. see the PCI Express Specification." hexmask.long.byte 0xC 24.--31. 1. "FOURTH_DWORD_FOURTH_BYTE,Byte 3 of Header log register of Fourth 32 bit Data Word. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." hexmask.long.byte 0xC 16.--23. 1. "FOURTH_DWORD_THIRD_BYTE,Byte 2 of Header log register of Fourth 32 bit Data Word. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." hexmask.long.byte 0xC 8.--15. 1. "FOURTH_DWORD_SECOND_BYTE,Byte 1 of Header log register of Fourth 32 bit Data Word. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." newline hexmask.long.byte 0xC 0.--7. 1. "FOURTH_DWORD_FIRST_BYTE,Byte 0 of Header log register of Fourth 32 bit Data Word. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." group.long (0x2C+0x100)++0x7 line.long 0x0 "ROOT_ERR_CMD_OFF,Root Error Command Register. For a description of this standard PCIe register. see the PCI Express Specification." hexmask.long 0x0 3.--31. 1. "RSVDP_3,Reserved for future use." bitfld.long 0x0 2. "FATAL_ERR_REPORTING_EN,Fatal Error Reporting Enable. For a description of this standard PCIe register field see the PCI Express Specification." "0,1" bitfld.long 0x0 1. "NON_FATAL_ERR_REPORTING_EN,Non-Fatal Error Reporting Enable. For a description of this standard PCIe register field see the PCI Express Specification." "0,1" newline bitfld.long 0x0 0. "CORR_ERR_REPORTING_EN,Correctable Error Reporting Enable. For a description of this standard PCIe register field see the PCI Express Specification." "0,1" line.long 0x4 "ROOT_ERR_STATUS_OFF,Root Error Status Register. For a description of this standard PCIe register. see the PCI Express Specification." hexmask.long.byte 0x4 27.--31. 1. "ADV_ERR_INT_MSG_NUM,Advanced Error Interrupt Message Number. For a description of this standard PCIe register field see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN.." hexmask.long.tbyte 0x4 7.--26. 1. "RSVDP_7,Reserved for future use." bitfld.long 0x4 6. "FATAL_ERR_MSG_RX,One or more Fatal Error Messages Received. For a description of this standard PCIe register field see the PCI Express Specification." "0,1" newline bitfld.long 0x4 5. "NON_FATAL_ERR_MSG_RX,One or more Non-Fatal Error Messages Received. For a description of this standard PCIe register field see the PCI Express Specification." "0,1" bitfld.long 0x4 4. "FIRST_UNCORR_FATAL,First Uncorrectable Error is Fatal. For a description of this standard PCIe register field see the PCI Express Specification." "0,1" bitfld.long 0x4 3. "MUL_ERR_FATAL_NON_FATAL_RX,Multiple Fatal or Non-Fatal Errors Received. For a description of this standard PCIe register field see the PCI Express Specification." "0,1" newline bitfld.long 0x4 2. "ERR_FATAL_NON_FATAL_RX,Fatal or Non-Fatal Error Received. For a description of this standard PCIe register field see the PCI Express Specification." "0,1" bitfld.long 0x4 1. "MUL_ERR_COR_RX,Multiple Correctable Errors Received. For a description of this standard PCIe register field see the PCI Express Specification." "0,1" bitfld.long 0x4 0. "ERR_COR_RX,Correctable Error Received. For a description of this standard PCIe register field see the PCI Express Specification." "0,1" rgroup.long (0x34+0x100)++0x13 line.long 0x0 "ERR_SRC_ID_OFF,Error Source Identification Register. For a description of this standard PCIe register. see the PCI Express Specification." hexmask.long.word 0x0 16.--31. 1. "ERR_FATAL_NON_FATAL_SOURCE_ID,Source of Fatal/Non-Fatal Error. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." hexmask.long.word 0x0 0.--15. 1. "ERR_COR_SOURCE_ID,Source of Correctable Error. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." line.long 0x4 "TLP_PREFIX_LOG_1_OFF,TLP Prefix Log Register 1. For a description of this standard PCIe register. see the PCI Express Specification." hexmask.long.byte 0x4 24.--31. 1. "CFG_TLP_PFX_LOG_1_FOURTH_BYTE,Byte 3 of Error TLP Prefix Log 1. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." hexmask.long.byte 0x4 16.--23. 1. "CFG_TLP_PFX_LOG_1_THIRD_BYTE,Byte 2 of Error TLP Prefix Log 1. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." hexmask.long.byte 0x4 8.--15. 1. "CFG_TLP_PFX_LOG_1_SECOND_BYTE,Byte 1 of Error TLP Prefix Log 1. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." newline hexmask.long.byte 0x4 0.--7. 1. "CFG_TLP_PFX_LOG_1_FIRST_BYTE,Byte 0 of Error TLP Prefix Log 1. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." line.long 0x8 "TLP_PREFIX_LOG_2_OFF,TLP Prefix Log Register 2. For a description of this standard PCIe register. see the PCI Express Specification." hexmask.long.byte 0x8 24.--31. 1. "CFG_TLP_PFX_LOG_2_FOURTH_BYTE,Byte 3 Error TLP Prefix Log 2. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." hexmask.long.byte 0x8 16.--23. 1. "CFG_TLP_PFX_LOG_2_THIRD_BYTE,Byte 2 Error TLP Prefix Log 2. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." hexmask.long.byte 0x8 8.--15. 1. "CFG_TLP_PFX_LOG_2_SECOND_BYTE,Byte 1 Error TLP Prefix Log 2. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." newline hexmask.long.byte 0x8 0.--7. 1. "CFG_TLP_PFX_LOG_2_FIRST_BYTE,Byte 0 Error TLP Prefix Log 2. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." line.long 0xC "TLP_PREFIX_LOG_3_OFF,TLP Prefix Log Register 3. For a description of this standard PCIe register. see the PCI Express Specification." hexmask.long.byte 0xC 24.--31. 1. "CFG_TLP_PFX_LOG_3_FOURTH_BYTE,Byte 3 Error TLP Prefix Log 3. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." hexmask.long.byte 0xC 16.--23. 1. "CFG_TLP_PFX_LOG_3_THIRD_BYTE,Byte 2 Error TLP Prefix Log 3. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." hexmask.long.byte 0xC 8.--15. 1. "CFG_TLP_PFX_LOG_3_SECOND_BYTE,Byte 1 Error TLP Prefix Log 3. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." newline hexmask.long.byte 0xC 0.--7. 1. "CFG_TLP_PFX_LOG_3_FIRST_BYTE,Byte 0 Error TLP Prefix Log 3. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." line.long 0x10 "TLP_PREFIX_LOG_4_OFF,TLP Prefix Log Register 4. For a description of this standard PCIe register. see the PCI Express Specification." hexmask.long.byte 0x10 24.--31. 1. "CFG_TLP_PFX_LOG_4_FOURTH_BYTE,Byte 3 Error TLP Prefix Log 4. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." hexmask.long.byte 0x10 16.--23. 1. "CFG_TLP_PFX_LOG_4_THIRD_BYTE,Byte 2 Error TLP Prefix Log 4. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." hexmask.long.byte 0x10 8.--15. 1. "CFG_TLP_PFX_LOG_4_SECOND_BYTE,Byte 1 Error TLP Prefix Log 4. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." newline hexmask.long.byte 0x10 0.--7. 1. "CFG_TLP_PFX_LOG_4_FIRST_BYTE,Byte 0 Error TLP Prefix Log 4. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." tree.end tree "PF0_MSI_CAP (PF MSI Capability Structure)" group.long (0x0+0x50)++0x13 line.long 0x0 "PCI_MSI_CAP_ID_NEXT_CTRL_REG,MSI Capability Header and Message Control Register." hexmask.long.byte 0x0 27.--31. 1. "RSVDP_27,Reserved for future use." bitfld.long 0x0 26. "PCI_MSI_EXT_DATA_EN,Extended Message Data Enable. - If set the function is enabled to provide Extended Message Data. - If clear the function is not enabled to provide Extended Message Data. Note: The access attributes of this field are as follows: -.." "0,1" bitfld.long 0x0 25. "PCI_MSI_EXT_DATA_CAP,Extended Message Data Capable. - If set the function is capable of providing Extended Message Data. - If clear the function does not support providing Extended Message Data. Note: The access attributes of this field are as follows:.." "0,1" newline rbitfld.long 0x0 24. "PCI_PVM_SUPPORT,Per-Vector Masking Capable. - If set the function supports MSI Per-Vector Masking. - If clear the function does not support MSI Per-Vector Masking. This bit must be set if the function is a PF or VF within an SR-IOV Device." "0,1" bitfld.long 0x0 23. "PCI_MSI_64_BIT_ADDR_CAP,64 bit address capable. - If set the function is capable of sending a 64-bit message address. - If clear the function is not capable of sending a 64-bit message address. This bit must be set if the function is a PCI Express.." "0,1" bitfld.long 0x0 20.--22. "PCI_MSI_MULTIPLE_MSG_EN,Multiple Message Enable. Software writes to this field to indicate the number of allocated vectors (equal to or less than the number of requested vectors). The number of allocated vectors is aligned to a power of two. If a.." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 17.--19. "PCI_MSI_MULTIPLE_MSG_CAP,Multiple Message Capable. System software reads this field to determine the number of requested vectors. The number of requested vectors must be aligned to a power of two (if a function requires three vectors it requests four by.." "0,1,2,3,4,5,6,7" bitfld.long 0x0 16. "PCI_MSI_ENABLE,MSI Enable. - If set and the MSI-X Enable bit in the MSI-X Message Control register is clear the function is permitted to use MSI to request service and is prohibited from using INTx interrupts. System configuration software sets this bit.." "0,1" hexmask.long.byte 0x0 8.--15. 1. "PCI_MSI_CAP_NEXT_OFFSET,Next Capability Pointer. This field contains the offset to the next PCI Capability structure or 00h if no other items exist in the linked list of Capabilities. Note: The access attributes of this field are as follows: - Wire: No.." newline hexmask.long.byte 0x0 0.--7. 1. "PCI_MSI_CAP_ID,Capability ID. Indicates the MSI Capability structure. This field returns a Capability ID of 05h indicating that this is an MSI Capability structure." line.long 0x4 "MSI_CAP_OFF_04H_REG,Message Address Register for MSI (Offset 04h)." hexmask.long 0x4 2.--31. 1. "PCI_MSI_CAP_OFF_04H,Message Address - System-specified message address. If the Message Enable bit (bit 16 of the PCI_MSI_CAP_ID_NEXT_CTRL_REG register) is set the contents of this field specify the DWORD-aligned address (Address[31:02]) for the MSI.." rbitfld.long 0x4 0.--1. "RSVDP_0,Reserved for future use." "0,1,2,3" line.long 0x8 "MSI_CAP_OFF_08H_REG,For a function that supports a 32-bit message address. - bits[31:16] of this register represent the Extended Message Data. and - bits[15:0] of this register represent the Message Data For a function that supports a 64-bit message.." hexmask.long.word 0x8 16.--31. 1. "PCI_MSI_CAP_OFF_0AH,For a function that supports a 32-bit message address this field contains Extended Message Data (System-specified message data). For the MSI Capability structures without per-vector masking it must be implemented if the Extended.." hexmask.long.word 0x8 0.--15. 1. "PCI_MSI_CAP_OFF_08H,For a function that supports a 32-bit message address this field contains Message Data (System-specified message data). If the Message Enable bit (bit 16 of the PCI_MSI_CAP_ID_NEXT_CTRL_REG) is set the function sends a DWORD Memory.." line.long 0xC "MSI_CAP_OFF_0CH_REG,For a function that supports a 32-bit message address. this register contains the Mask Bits when the Per-Vector Masking Capable bit (bit 24 of PCI_MSI_CAP_ID_NEXT_CTRL_REG) is set. For a function that supports a 64-bit message.." hexmask.long.word 0xC 16.--31. 1. "PCI_MSI_CAP_OFF_0EH,For a function that supports a 32-bit message address this field contains the upper Mask Bits when the Per Vector Masking Capable bit (PCI_MSI_CAP_ID_NEXT_CTRL_REG.PCI_PVM_SUPPORT) is set. For a function that supports a 64-bit.." hexmask.long.word 0xC 0.--15. 1. "PCI_MSI_CAP_OFF_0CH,For a function that supports a 32-bit message address this field contains the lower Mask Bits when the Per Vector Masking Capable bit (PCI_MSI_CAP_ID_NEXT_CTRL_REG.PCI_PVM_SUPPORT) is set. For a function that supports a 64-bit.." line.long 0x10 "MSI_CAP_OFF_10H_REG,For a function that supports a 32-bit message address. this register contains the Pending Bits when the Per-Vector Masking Capable bit (bit 24 of PCI_MSI_CAP_ID_NEXT_CTRL_REG) is set. For a function that supports a 64-bit message.." hexmask.long 0x10 0.--31. 1. "PCI_MSI_CAP_OFF_10H,Used for MSI when the Per Vector Masking Capable bit (PCI_MSI_CAP_ID_NEXT_CTRL_REG.PCI_PVM_SUPPORT) is set. For 32-bit contains Pending Bits. For 64-bit contains Mask Bits. For a description of this standard PCIe register field see.." rgroup.long (0x14+0x50)++0x3 line.long 0x0 "MSI_CAP_OFF_14H_REG,Pending Bits Register for MSI. This register is used for a function that supports a 64-bit message address when the Per-Vector Masking Capable bit (bit 24 of PCI_MSI_CAP_ID_NEXT_CTRL_REG) is set." hexmask.long 0x0 0.--31. 1. "PCI_MSI_CAP_OFF_14H,Pending Bits. For each pending bit that is set the function has a pending associated message." tree.end tree "PF0_MSIX_CAP (PF MSI-X Capability Structure)" group.long (0x0+0xB0)++0xB line.long 0x0 "PCI_MSIX_CAP_ID_NEXT_CTRL_REG,MSI-X Capability ID. Next Pointer. Control Registers. For a description of this standard PCIe register. see the PCI Express Base Specification." bitfld.long 0x0 31. "PCI_MSIX_ENABLE,MSI-X Enable. For a description of this standard PCIe register field see the PCI Express Base Specification." "0,1" bitfld.long 0x0 30. "PCI_MSIX_FUNCTION_MASK,Function Mask. For a description of this standard PCIe register field see the PCI Express Base Specification. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" "0,1" rbitfld.long 0x0 27.--29. "RSVDP_27,Reserved for future use." "0,1,2,3,4,5,6,7" newline hexmask.long.word 0x0 16.--26. 1. "PCI_MSIX_TABLE_SIZE,MSI-X Table Size. For a description of this standard PCIe register field see the PCI Express Base Specification. SRIOV Note: All VFs in a single PF have the same value for 'MSI-X Table Size' (PCI_MSIX_TABLE_SIZE field in.." hexmask.long.byte 0x0 8.--15. 1. "PCI_MSIX_CAP_NEXT_OFFSET,MSI-X Next Capability Pointer. For a description of this standard PCIe register field see the PCI Express Base Specification. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN.." hexmask.long.byte 0x0 0.--7. 1. "PCI_MSIX_CAP_ID,MSI-X Capability ID. For a description of this standard PCIe register field see the PCI Express Base Specification." line.long 0x4 "MSIX_TABLE_OFFSET_REG,MSI-X Table Offset and BIR Register. For a description of this standard PCIe register. see the PCI Express Base Specification." hexmask.long 0x4 3.--31. 1. "PCI_MSIX_TABLE_OFFSET,MSI-X Table Offset. For a description of this standard PCIe register field see the PCI Express Base Specification. SRIOV Note: All VFs in a single PF have the same value for 'MSI-X Table Offset' (PCI_MSIX_TABLE_OFFSET field in.." bitfld.long 0x4 0.--2. "PCI_MSIX_BIR,MSI-X Table BAR Indicator Register Field. For a description of this standard PCIe register field see the PCI Express Base Specification. SRIOV Note: All VFs in a single PF have the same value for 'MSI-X Table BAR Indicator Register'.." "0,1,2,3,4,5,6,7" line.long 0x8 "MSIX_PBA_OFFSET_REG,MSI-X PBA Offset and BIR Register. For a description of this standard PCIe register. see the PCI Express Base Specification." hexmask.long 0x8 3.--31. 1. "PCI_MSIX_PBA_OFFSET,MSI-X PBA Offset. For a description of this standard PCIe register field see the PCI Express Base Specification. SRIOV Note: All VFs in a single PF have the same value for 'MSI-X PBA Offset' (PCI_MSIX_PBA_OFFSET field in.." bitfld.long 0x8 0.--2. "PCI_MSIX_PBA_BIR,MSI-X PBA BIR. For a description of this standard PCIe register field see the PCI Express Base Specification. SRIOV Note: All VFs in a single PF have the same value for 'MSI-X PBA BIR' (PCI_MSIX_PBA_BIR field in.." "0,1,2,3,4,5,6,7" tree.end tree "PF0_MSIX_CAP_DBI2 (DBI2 Shadow Block: PF MSI-X Capability Structure)" rgroup.long (0x0+0x10B0)++0x3 line.long 0x0 "SHADOW_PCI_MSIX_CAP_ID_NEXT_CTRL_REG,MSI-X Capability ID. Next Pointer. Control Registers. For a description of this standard PCIe register. see the PCI Express Base Specification." hexmask.long.byte 0x0 27.--31. 1. "RSVDP_27,Reserved for future use." hexmask.long.word 0x0 16.--26. 1. "PCI_MSIX_TABLE_SIZE,MSI-X Table Size in the shadow register. Note: The access attributes of this field are as follows: - Wire: No access - Dbi: No access - Dbi2: if (DBI_RO_WR_EN == 1) then R/W else R Note: This register field is sticky." hexmask.long.word 0x0 0.--15. 1. "RSVDP_0,Reserved for future use." group.long 0x4++0x7 line.long 0x0 "SHADOW_MSIX_TABLE_OFFSET_REG,MSI-X Table Offset and BIR Register. For a description of this standard PCIe register. see the PCI Express Base Specification." hexmask.long 0x0 3.--31. 1. "PCI_MSIX_TABLE_OFFSET,MSI-X Table Offset. For a description of this standard PCIe register field see the PCI Express Base Specification. Note: The access attributes of this field are as follows: - Wire: No access - Dbi: No access - Dbi2: if.." bitfld.long 0x0 0.--2. "PCI_MSIX_BIR,MSI-X Table BAR Indicator Register Field. For a description of this standard PCIe register field see the PCI Express Base Specification. Note: The access attributes of this field are as follows: - Wire: No access - Dbi: No access - Dbi2: if.." "?,?,if,?,?,?,?,?" line.long 0x4 "SHADOW_MSIX_PBA_OFFSET_REG,MSI-X PBA Offset and BIR Register. For a description of this standard PCIe register. see the PCI Express Base Specification." hexmask.long 0x4 3.--31. 1. "PCI_MSIX_PBA_OFFSET,MSI-X PBA Offset. For a description of this standard PCIe register field see the PCI Express Base Specification. Note: The access attributes of this field are as follows: - Wire: No access - Dbi: No access - Dbi2: if (DBI_RO_WR_EN ==.." bitfld.long 0x4 0.--2. "PCI_MSIX_PBA_BIR,MSI-X PBA BIR. For a description of this standard PCIe register field see the PCI Express Base Specification. Note: The access attributes of this field are as follows: - Wire: No access - Dbi: No access - Dbi2: if (DBI_RO_WR_EN == 1 &&.." "?,?,if,?,?,?,?,?" tree.end tree "PF0_DMA_CAP (DMA Port Logic Structure)" group.long (0x0+0xC8000)++0x3 line.long 0x0 "DMA_CTRL_DATA_ARB_PRIOR_OFF,DMA Arbitration Scheme for TRGT1 Interface. This register is used to control traffic priorities among various sources that are delivered to your application through TRGT1 where 0x0 represents the highest priority. - Non-DMA Rx.." hexmask.long.tbyte 0x0 12.--31. 1. "RSVDP_12,Reserved for future use." bitfld.long 0x0 9.--11. "RDBUFF_TRGT_WEIGHT,DMA Read Channel MWr Requests. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 6.--8. "RD_CTRL_TRGT_WEIGHT,DMA Read Channel MRd Requests. For LL element/descriptor access. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" "0,1,2,3,4,5,6,7" bitfld.long 0x0 3.--5. "WR_CTRL_TRGT_WEIGHT,DMA Write Channel MRd Requests. For DMA data requests and LL element/descriptor access. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 0.--2. "RTRGT1_WEIGHT,Non-DMA Rx Requests. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" "0,1,2,3,4,5,6,7" group.long (0x8+0xC8000)++0xB line.long 0x0 "DMA_CTRL_OFF,DMA Number of Channels Register." hexmask.long.byte 0x0 26.--31. 1. "RSVDP_26,Reserved for future use." bitfld.long 0x0 25. "DIS_C2W_CACHE_RD,Disable DMA Read Channels 'completion to memory write' context cache pre-fetch function. Note: For internal debugging only. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" "0,1" newline bitfld.long 0x0 24. "DIS_C2W_CACHE_WR,Disable DMA Write Channels 'completion to memory write' context cache pre-fetch function. Note: For internal debugging only. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" "0,1" hexmask.long.byte 0x0 20.--23. 1. "RSVDP_20,Reserved for future use." newline hexmask.long.byte 0x0 16.--19. 1. "NUM_DMA_RD_CHAN,Number of Read Channels. You can read this register to determine the number of read channels the DMA controller has been configured to support." hexmask.long.word 0x0 4.--15. 1. "RSVDP_4,Reserved for future use." newline hexmask.long.byte 0x0 0.--3. 1. "NUM_DMA_WR_CHAN,Number of Write Channels. You can read this register to determine the number of write channels the DMA controller has been configured to support." line.long 0x4 "DMA_WRITE_ENGINE_EN_OFF,DMA Write Engine Enable Register." hexmask.long.byte 0x4 24.--31. 1. "RSVDP_24,Reserved for future use." bitfld.long 0x4 23. "DMA_WRITE_ENGINE_EN_HSHAKE_CH7,Enable Handshake for DMA Write Engine Channel 7. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" "0,1" newline bitfld.long 0x4 22. "DMA_WRITE_ENGINE_EN_HSHAKE_CH6,Enable Handshake for DMA Write Engine Channel 6. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" "0,1" bitfld.long 0x4 21. "DMA_WRITE_ENGINE_EN_HSHAKE_CH5,Enable Handshake for DMA Write Engine Channel 5. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" "0,1" newline bitfld.long 0x4 20. "DMA_WRITE_ENGINE_EN_HSHAKE_CH4,Enable Handshake for DMA Write Engine Channel 4. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" "0,1" bitfld.long 0x4 19. "DMA_WRITE_ENGINE_EN_HSHAKE_CH3,Enable Handshake for DMA Write Engine Channel 3. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" "0,1" newline bitfld.long 0x4 18. "DMA_WRITE_ENGINE_EN_HSHAKE_CH2,Enable Handshake for DMA Write Engine Channel 2. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" "0,1" bitfld.long 0x4 17. "DMA_WRITE_ENGINE_EN_HSHAKE_CH1,Enable Handshake for DMA Write Engine Channel 1. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" "0,1" newline bitfld.long 0x4 16. "DMA_WRITE_ENGINE_EN_HSHAKE_CH0,Enable Handshake for DMA Write Engine Channel 0. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" "0,1" hexmask.long.word 0x4 1.--15. 1. "RSVDP_1,Reserved for future use." newline bitfld.long 0x4 0. "DMA_WRITE_ENGINE,DMA Write Engine Enable. - 1: Enable - 0: Disable (Soft Reset) For normal operation you must initially set this bit to '1' before any other software setup actions. You do not need to toggle or rewrite to this bit during normal.." "Disable,Enable" line.long 0x8 "DMA_WRITE_DOORBELL_OFF,DMA Write Doorbell Register." bitfld.long 0x8 31. "WR_STOP,Stop. Set in conjunction with the Doorbell Number field. The DMA write channel stops issuing requests sets the channel status to 'Stopped' and asserts the 'Abort' interrupt if it is enabled. Before setting the Stop bit you must read the.." "0,1" hexmask.long 0x8 3.--30. 1. "RSVDP_3,Reserved for future use." newline bitfld.long 0x8 0.--2. "WR_DOORBELL_NUM,Doorbell Number. You must write the channel number to this register to start the DMA write transfer for that channel. The DMA detects a write to this register field even if the value of this field does not change. You do not need to.." "0,1,2,3,4,5,6,7" group.long (0x18+0xC8000)++0x7 line.long 0x0 "DMA_WRITE_CHANNEL_ARB_WEIGHT_LOW_OFF,DMA Write Engine Channel Arbitration Weight Low Register. The 5-bit channel weight (for write channels 0-3) specifies the maximum number of TLP requests that the DMA can issue for that channel before it must return to.." hexmask.long.word 0x0 20.--31. 1. "RSVDP_20,Reserved for future use." hexmask.long.byte 0x0 15.--19. 1. "WRITE_CHANNEL3_WEIGHT,Channel 3 Weight. The weight is initialized by software before ringing the doorbell. The value is used by the channel weighted round robin arbiter to select the next channel read request. A value of '0' means that one TLP is issued.." newline hexmask.long.byte 0x0 10.--14. 1. "WRITE_CHANNEL2_WEIGHT,Channel 2 Weight. The weight is initialized by software before ringing the doorbell. The value is used by the channel weighted round robin arbiter to select the next channel read request. A value of '0' means that one TLP is issued.." hexmask.long.byte 0x0 5.--9. 1. "WRITE_CHANNEL1_WEIGHT,Channel 1 Weight. The weight is initialized by software before ringing the doorbell. The value is used by the channel weighted round robin arbiter to select the next channel read request. A value of '0' means that one TLP is issued.." newline hexmask.long.byte 0x0 0.--4. 1. "WRITE_CHANNEL0_WEIGHT,Channel 0 Weight. The weight is initialized by software before ringing the doorbell. The value is used by the channel weighted round robin arbiter to select the next channel read request. A value of '0' means that one TLP is issued.." line.long 0x4 "DMA_WRITE_CHANNEL_ARB_WEIGHT_HIGH_OFF,DMA Write Engine Channel Arbitration Weight High Register. The 5-bit channel weight (for write channels 4-7) specifies the maximum number of TLP requests that the DMA can issue for that channel before it must return.." hexmask.long.word 0x4 20.--31. 1. "RSVDP_20,Reserved for future use." hexmask.long.byte 0x4 15.--19. 1. "WRITE_CHANNEL7_WEIGHT,Channel 7 Weight. The weight is initialized by software before ringing the doorbell. The value is used by the channel weighted round robin arbiter to select the next channel read request. A value of '0' means that one TLP is issued.." newline hexmask.long.byte 0x4 10.--14. 1. "WRITE_CHANNEL6_WEIGHT,Channel 6 Weight. The weight is initialized by software before ringing the doorbell. The value is used by the channel weighted round robin arbiter to select the next channel read request. A value of '0' means that one TLP is issued.." hexmask.long.byte 0x4 5.--9. 1. "WRITE_CHANNEL5_WEIGHT,Channel 5 Weight. The weight is initialized by software before ringing the doorbell. The value is used by the channel weighted round robin arbiter to select the next channel read request. A value of '0' means that one TLP is issued.." newline hexmask.long.byte 0x4 0.--4. 1. "WRITE_CHANNEL4_WEIGHT,Channel 4 Weight. The weight is initialized by software before ringing the doorbell. The value is used by the channel weighted round robin arbiter to select the next channel read request. A value of '0' means that one TLP is issued.." group.long (0x2C+0xC8000)++0x7 line.long 0x0 "DMA_READ_ENGINE_EN_OFF,DMA Read Engine Enable Register." hexmask.long.byte 0x0 24.--31. 1. "RSVDP_24,Reserved for future use." bitfld.long 0x0 23. "DMA_READ_ENGINE_EN_HSHAKE_CH7,Enable Handshake for DMA Read Engine Channel 7. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" "0,1" newline bitfld.long 0x0 22. "DMA_READ_ENGINE_EN_HSHAKE_CH6,Enable Handshake for DMA Read Engine Channel 6. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" "0,1" bitfld.long 0x0 21. "DMA_READ_ENGINE_EN_HSHAKE_CH5,Enable Handshake for DMA Read Engine Channel 5. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" "0,1" newline bitfld.long 0x0 20. "DMA_READ_ENGINE_EN_HSHAKE_CH4,Enable Handshake for DMA Read Engine Channel 4. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" "0,1" bitfld.long 0x0 19. "DMA_READ_ENGINE_EN_HSHAKE_CH3,Enable Handshake for DMA Read Engine Channel 3. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" "0,1" newline bitfld.long 0x0 18. "DMA_READ_ENGINE_EN_HSHAKE_CH2,Enable Handshake for DMA Read Engine Channel 2. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" "0,1" bitfld.long 0x0 17. "DMA_READ_ENGINE_EN_HSHAKE_CH1,Enable Handshake for DMA Read Engine Channel 1. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" "0,1" newline bitfld.long 0x0 16. "DMA_READ_ENGINE_EN_HSHAKE_CH0,Enable Handshake for DMA Read Engine Channel 0. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" "0,1" hexmask.long.word 0x0 1.--15. 1. "RSVDP_1,Reserved for future use." newline bitfld.long 0x0 0. "DMA_READ_ENGINE,DMA Read Engine Enable. - 1: Enable - 0: Disable (Soft Reset) For normal operation you must initially set this bit to '1' before any other software setup actions. You do not need to toggle or rewrite to this bit during normal operation." "Disable,Enable" line.long 0x4 "DMA_READ_DOORBELL_OFF,DMA Read Doorbell Register." bitfld.long 0x4 31. "RD_STOP,Stop. Set in conjunction with the Doorbell Number field. The DMA read channel stops issuing requests sets the channel status to 'Stopped' and asserts the 'Abort' interrupt if it is enabled. Before setting the Stop bit you must read the channel.." "0,1" hexmask.long 0x4 3.--30. 1. "RSVDP_3,Reserved for future use." newline bitfld.long 0x4 0.--2. "RD_DOORBELL_NUM,Doorbell Number. You must write 0x0 to this register to start the DMA read transfer for that channel. The DMA detects a write to this register field even if the value of this field does not change. The range of this field is 0x0 to 0x7.." "0,1,2,3,4,5,6,7" group.long (0x38+0xC8000)++0x7 line.long 0x0 "DMA_READ_CHANNEL_ARB_WEIGHT_LOW_OFF,DMA Read Engine Channel Arbitration Weight Low Register. The 5-bit channel weight (for read channels 0-3) specifies the maximum number of TLP requests that the DMA can issue for that channel before it must return to.." hexmask.long.word 0x0 20.--31. 1. "RSVDP_20,Reserved for future use." hexmask.long.byte 0x0 15.--19. 1. "READ_CHANNEL3_WEIGHT,Channel 3 Weight. The weight is initialized by software before ringing the doorbell. The value is used by the channel weighted round robin arbiter to select the next channel read request. Note: The access attributes of this field are.." newline hexmask.long.byte 0x0 10.--14. 1. "READ_CHANNEL2_WEIGHT,Channel 2 Weight. The weight is initialized by software before ringing the doorbell. The value is used by the channel weighted round robin arbiter to select the next channel read request. Note: The access attributes of this field are.." hexmask.long.byte 0x0 5.--9. 1. "READ_CHANNEL1_WEIGHT,Channel 1 Weight. The weight is initialized by software before ringing the doorbell. The value is used by the channel weighted round robin arbiter to select the next channel read request. Note: The access attributes of this field are.." newline hexmask.long.byte 0x0 0.--4. 1. "READ_CHANNEL0_WEIGHT,Channel 0 Weight. The weight is initialized by software before ringing the doorbell. The value is used by the channel weighted round robin arbiter to select the next channel read request. Note: The access attributes of this field are.." line.long 0x4 "DMA_READ_CHANNEL_ARB_WEIGHT_HIGH_OFF,DMA Read Engine Channel Arbitration Weight High Register. The 5-bit channel weight (for read channels 4-7) specifies the maximum number of TLP requests that the DMA can issue for that channel before it must return to.." hexmask.long.word 0x4 20.--31. 1. "RSVDP_20,Reserved for future use." hexmask.long.byte 0x4 15.--19. 1. "READ_CHANNEL7_WEIGHT,Channel 7 Weight. The weight is initialized by software before ringing the doorbell. The value is used by the channel weighted round robin arbiter to select the next channel read request. Note: The access attributes of this field are.." newline hexmask.long.byte 0x4 10.--14. 1. "READ_CHANNEL6_WEIGHT,Channel 6 Weight. The weight is initialized by software before ringing the doorbell. The value is used by the channel weighted round robin arbiter to select the next channel read request. Note: The access attributes of this field are.." hexmask.long.byte 0x4 5.--9. 1. "READ_CHANNEL5_WEIGHT,Channel 5 Weight. The weight is initialized by software before ringing the doorbell. The value is used by the channel weighted round robin arbiter to select the next channel read request. Note: The access attributes of this field are.." newline hexmask.long.byte 0x4 0.--4. 1. "READ_CHANNEL4_WEIGHT,Channel 4 Weight. The weight is initialized by software before ringing the doorbell. The value is used by the channel weighted round robin arbiter to select the next channel read request. Note: The access attributes of this field are.." group.long (0x4C+0xC8000)++0x3 line.long 0x0 "DMA_WRITE_INT_STATUS_OFF,DMA Write Interrupt Status Register." hexmask.long.byte 0x0 24.--31. 1. "RSVDP_24,Reserved for future use." hexmask.long.byte 0x0 16.--23. 1. "WR_ABORT_INT_STATUS,Abort Interrupt Status. The DMA write channel has detected an error or you manually stopped the transfer as described in 'Error Handling Assistance by Remote Software'. Each bit corresponds to a DMA channel. Bit [0] corresponds to.." newline hexmask.long.byte 0x0 8.--15. 1. "RSVDP_8,Reserved for future use." hexmask.long.byte 0x0 0.--7. 1. "WR_DONE_INT_STATUS,Done Interrupt Status. The DMA write channel has successfully completed the DMA transfer. For more details see 'Interrupts and Error Handling'. Each bit corresponds to a DMA channel. Bit [0] corresponds to channel 0. - Enabling: For.." group.long (0x54+0xC8000)++0x7 line.long 0x0 "DMA_WRITE_INT_MASK_OFF,DMA Write Interrupt Mask Register." hexmask.long.byte 0x0 24.--31. 1. "RSVDP_24,Reserved for future use." hexmask.long.byte 0x0 16.--23. 1. "WR_ABORT_INT_MASK,Abort Interrupt Mask. Prevents the Abort interrupt status field in the DMA write interrupt status register from asserting the edma_int output. Each bit corresponds to a DMA channel. Bit [0] corresponds to channel 0. Note: The access.." newline hexmask.long.byte 0x0 8.--15. 1. "RSVDP_8,Reserved for future use." hexmask.long.byte 0x0 0.--7. 1. "WR_DONE_INT_MASK,Done Interrupt Mask. Prevents the Done interrupt status field in the DMA write interrupt status register from asserting the edma_int output. Each bit corresponds to a DMA channel. Bit [0] corresponds to channel 0. Note: The access.." line.long 0x4 "DMA_WRITE_INT_CLEAR_OFF,DMA Write Interrupt Clear Register." hexmask.long.byte 0x4 24.--31. 1. "RSVDP_24,Reserved for future use." hexmask.long.byte 0x4 16.--23. 1. "WR_ABORT_INT_CLEAR,Abort Interrupt Clear. You must write a 1'b1 to clear the corresponding bit in the Abort interrupt status field of the DMA write interrupt status register. Each bit corresponds to a DMA channel. Bit [0] corresponds to channel 0. Note:.." newline hexmask.long.byte 0x4 8.--15. 1. "RSVDP_8,Reserved for future use." hexmask.long.byte 0x4 0.--7. 1. "WR_DONE_INT_CLEAR,Done Interrupt Clear. You must write a 1'b1 to clear the corresponding bit in the Done interrupt status field of the DMA write interrupt status register. Each bit corresponds to a DMA channel. Bit [0] corresponds to channel 0. Note:.." rgroup.long (0x5C+0xC8000)++0x3 line.long 0x0 "DMA_WRITE_ERR_STATUS_OFF,DMA Write Error Status Register" hexmask.long.byte 0x0 24.--31. 1. "RSVDP_24,Reserved for future use." hexmask.long.byte 0x0 16.--23. 1. "LINKLIST_ELEMENT_FETCH_ERR_DETECT,Linked List Element Fetch Error Detected. The DMA write channel has received an error response from the AXI bus (or TRGT1 interface when the AXI Bridge is not used) while reading a linked list element from local memory." newline hexmask.long.byte 0x0 8.--15. 1. "RSVDP_8,Reserved for future use." hexmask.long.byte 0x0 0.--7. 1. "APP_READ_ERR_DETECT,Application Read Error Detected. The DMA write channel has received an error response from the AXI bus (or TRGT1 interface when the AXI Bridge is not used) while reading data from it. Each bit corresponds to a DMA channel. Bit [0].." group.long (0x60+0xC8000)++0x1F line.long 0x0 "DMA_WRITE_DONE_IMWR_LOW_OFF,DMA Write Done IMWr Address Low Register." hexmask.long 0x0 0.--31. 1. "DMA_WRITE_DONE_LOW_REG,The DMA uses this field to generate bits [31:0] of the address field for the Done IMWr TLP. Bits [1:0] must be '00' as this address must be dword aligned. Note: The access attributes of this field are as follows: - Wire: No access." line.long 0x4 "DMA_WRITE_DONE_IMWR_HIGH_OFF,DMA Write Done IMWr Interrupt Address High Register." hexmask.long 0x4 0.--31. 1. "DMA_WRITE_DONE_HIGH_REG,The DMA uses this field to generate bits [63:32] of the address field for the Done IMWr TLP. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" line.long 0x8 "DMA_WRITE_ABORT_IMWR_LOW_OFF,DMA Write Abort IMWr Address Low Register." hexmask.long 0x8 0.--31. 1. "DMA_WRITE_ABORT_LOW_REG,The DMA uses this field to generate bits [31:0] of the address field for the Abort IMWr TLP it generates. Bits [1:0] must be '00' as this address must be dword aligned. Note: The access attributes of this field are as follows: -.." line.long 0xC "DMA_WRITE_ABORT_IMWR_HIGH_OFF,DMA Write Abort IMWr Address High Register." hexmask.long 0xC 0.--31. 1. "DMA_WRITE_ABORT_HIGH_REG,The DMA uses this field to generate bits [63:32] of the address field for the Abort IMWr TLP. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" line.long 0x10 "DMA_WRITE_CH01_IMWR_DATA_OFF,DMA Write Channel 1 and 0 IMWr Data Register." hexmask.long.word 0x10 16.--31. 1. "WR_CHANNEL_1_DATA,The DMA uses this field to generate the data field for the Done or Abort IMWr TLPs it generates for write channel 1. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" hexmask.long.word 0x10 0.--15. 1. "WR_CHANNEL_0_DATA,The DMA uses this field to generate the data field for the Done or Abort IMWr TLPs it generates for write channel 0. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" line.long 0x14 "DMA_WRITE_CH23_IMWR_DATA_OFF,DMA Write Channel 3 and 2 IMWr Data Register." hexmask.long.word 0x14 16.--31. 1. "WR_CHANNEL_3_DATA,The DMA uses this field to generate the data field for the Done or Abort IMWr TLPs it generates for write channel 3. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" hexmask.long.word 0x14 0.--15. 1. "WR_CHANNEL_2_DATA,The DMA uses this field to generate the data field for the Done or Abort IMWr TLPs it generates for write channel 2. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" line.long 0x18 "DMA_WRITE_CH45_IMWR_DATA_OFF,DMA Write Channel 5 and 4 IMWr Data Register." hexmask.long.word 0x18 16.--31. 1. "WR_CHANNEL_5_DATA,The DMA uses this field to generate the data field for the Done or Abort IMWr TLPs it generates for write channel 5. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" hexmask.long.word 0x18 0.--15. 1. "WR_CHANNEL_4_DATA,The DMA uses this field to generate the data field for the Done or Abort IMWr TLPs it generates for write channel 4. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" line.long 0x1C "DMA_WRITE_CH67_IMWR_DATA_OFF,DMA Write Channel 7 and 6 IMWr Data Register." hexmask.long.word 0x1C 16.--31. 1. "WR_CHANNEL_7_DATA,The DMA uses this field to generate the data field for the Done or Abort IMWr TLPs it generates for write channel 7. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" hexmask.long.word 0x1C 0.--15. 1. "WR_CHANNEL_6_DATA,The DMA uses this field to generate the data field for the Done or Abort IMWr TLPs it generates for write channel 6. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" group.long (0x90+0xC8000)++0x3 line.long 0x0 "DMA_WRITE_LINKED_LIST_ERR_EN_OFF,DMA Write Linked List Error Enable Register. The LIE and RIE bits in the LL element enable the channel 'done' interrupts (local and remote). The LLLAIE and LLRAIE bits enable the channel 'abort' interrupts (local and.." hexmask.long.byte 0x0 24.--31. 1. "RSVDP_24,Reserved for future use." hexmask.long.byte 0x0 16.--23. 1. "WR_CHANNEL_LLLAIE,Write Channel LL Local Abort Interrupt Enable (LLLAIE). You enable the write channel local abort interrupt through this bit. The LIE and RIE bits in the LL element enable the write channel done interrupts. Each bit corresponds to a DMA.." newline hexmask.long.byte 0x0 8.--15. 1. "RSVDP_8,Reserved for future use." hexmask.long.byte 0x0 0.--7. 1. "WR_CHANNEL_LLRAIE,Write Channel LL Remote Abort Interrupt Enable (LLRAIE). You enable the write channel remote abort interrupt through this bit. The LIE and RIE bits in the LL element enable the write channel done interrupts. Each bit corresponds to a.." group.long (0xA0+0xC8000)++0x3 line.long 0x0 "DMA_READ_INT_STATUS_OFF,DMA Read Interrupt Status Register." hexmask.long.byte 0x0 24.--31. 1. "RSVDP_24,Reserved for future use." hexmask.long.byte 0x0 16.--23. 1. "RD_ABORT_INT_STATUS,Abort Interrupt Status. The DMA read channel has detected an error or you manually stopped the transfer as described in 'Stopping the DMA Transfer (Software Stop)'. Each bit corresponds to a DMA channel. Bit [0] corresponds to.." newline hexmask.long.byte 0x0 8.--15. 1. "RSVDP_8,Reserved for future use." hexmask.long.byte 0x0 0.--7. 1. "RD_DONE_INT_STATUS,Done Interrupt Status. The DMA read channel has successfully completed the DMA read transfer. Each bit corresponds to a DMA channel. Bit [0] corresponds to channel 0. - Enabling: For details see 'Interrupts and Error Handling'. -.." group.long (0xA8+0xC8000)++0x7 line.long 0x0 "DMA_READ_INT_MASK_OFF,DMA Read Interrupt Mask Register." hexmask.long.byte 0x0 24.--31. 1. "RSVDP_24,Reserved for future use." hexmask.long.byte 0x0 16.--23. 1. "RD_ABORT_INT_MASK,Abort Interrupt Mask. Prevents the Abort interrupt status field in the DMA read interrupt status register from asserting the edma_int output. Each bit corresponds to a DMA channel. Bit [0] corresponds to channel 0. Note: The access.." newline hexmask.long.byte 0x0 8.--15. 1. "RSVDP_8,Reserved for future use." hexmask.long.byte 0x0 0.--7. 1. "RD_DONE_INT_MASK,Done Interrupt Mask. Prevents the Done interrupt status field in the DMA read interrupt status register from asserting the edma_int output. Each bit corresponds to a DMA channel. Bit [0] corresponds to channel 0. Note: The access.." line.long 0x4 "DMA_READ_INT_CLEAR_OFF,DMA Read Interrupt Clear Register." hexmask.long.byte 0x4 24.--31. 1. "RSVDP_24,Reserved for future use." hexmask.long.byte 0x4 16.--23. 1. "RD_ABORT_INT_CLEAR,Abort Interrupt Clear. You must write a 1'b1 to clear the corresponding bit in the Abort interrupt status field of the DMA read interrupt status register. Each bit corresponds to a DMA channel. Bit [0] corresponds to channel 0. Note:.." newline hexmask.long.byte 0x4 8.--15. 1. "RSVDP_8,Reserved for future use." hexmask.long.byte 0x4 0.--7. 1. "RD_DONE_INT_CLEAR,Done Interrupt Clear. You must write a 1'b1 to clear the corresponding bit in the Done interrupt status field of the DMA read interrupt status register. Each bit corresponds to a DMA channel. Bit [0] corresponds to channel 0. Note:.." rgroup.long (0xB4+0xC8000)++0x7 line.long 0x0 "DMA_READ_ERR_STATUS_LOW_OFF,DMA Read Error Status Low Register." hexmask.long.byte 0x0 24.--31. 1. "RSVDP_24,Reserved for future use." hexmask.long.byte 0x0 16.--23. 1. "LINK_LIST_ELEMENT_FETCH_ERR_DETECT,Linked List Element Fetch Error Detected. - The DMA read channel has received an error response from the AXI bus while reading a linked list element from local memory. Each bit corresponds to a DMA channel. Bit [0].." newline hexmask.long.byte 0x0 8.--15. 1. "RSVDP_8,Reserved for future use." hexmask.long.byte 0x0 0.--7. 1. "APP_WR_ERR_DETECT,Application Write Error Detected. The DMA read channel has received an error response from the AXI bus (or TRGT1 interface when the AXI Bridge is not used) while writing data to it. This error is fatal. You must restart the transfer.." line.long 0x4 "DMA_READ_ERR_STATUS_HIGH_OFF,DMA Read Error Status High Register." hexmask.long.byte 0x4 24.--31. 1. "DATA_POISIONING,Data Poisoning. The DMA read channel has detected data poisoning in the completion from the remote device (in response to the MRd request). The DMA read channel will drop the completion and then be halted. The CX_FLT_MASK_UR_POIS filter.." hexmask.long.byte 0x4 16.--23. 1. "CPL_TIMEOUT,Completion Time Out. The DMA read channel has timed-out while waiting for the remote device to respond to the MRd request or a malformed CplD has been received. For more details see 'Linked List Mode'. Each bit corresponds to a DMA channel." newline hexmask.long.byte 0x4 8.--15. 1. "CPL_ABORT,Completer Abort. The DMA read channel has received a PCIe completer abort completion status from the remote device in response to the MRd request. For more details see 'Linked List Mode'. Each bit corresponds to a DMA channel. Bit [0].." hexmask.long.byte 0x4 0.--7. 1. "UNSUPPORTED_REQ,Unsupported Request. The DMA read channel has received a PCIe unsupported request completion status from the remote device in response to the MRd request. For more details see 'Linked List Mode'. Each bit corresponds to a DMA channel." group.long (0xC4+0xC8000)++0x3 line.long 0x0 "DMA_READ_LINKED_LIST_ERR_EN_OFF,DMA Read Linked List Error Enable Register. The LIE and RIE bits in the LL element enable the channel 'done' interrupts (local and remote). The LLLAIE and LLRAIE bits enable the channel 'abort' interrupts (local and remote)." hexmask.long.byte 0x0 24.--31. 1. "RSVDP_24,Reserved for future use." hexmask.long.byte 0x0 16.--23. 1. "RD_CHANNEL_LLLAIE,Read Channel LL Local Abort Interrupt Enable (LLLAIE). You enable the read channel Local Abort interrupt through this bit. The LIE and RIE bits in the LL element enable the read channel done interrupts. Each bit corresponds to a DMA.." newline hexmask.long.byte 0x0 8.--15. 1. "RSVDP_8,Reserved for future use." hexmask.long.byte 0x0 0.--7. 1. "RD_CHANNEL_LLRAIE,Read Channel LL Remote Abort Interrupt Enable (LLRAIE). You enable the read channel Remote Abort interrupt through this bit. The LIE and RIE bits in the LL element enable the read channel done interrupts. Each bit corresponds to a DMA.." group.long (0xCC+0xC8000)++0x1F line.long 0x0 "DMA_READ_DONE_IMWR_LOW_OFF,DMA Read Done IMWr Address Low Register." hexmask.long 0x0 0.--31. 1. "DMA_READ_DONE_LOW_REG,The DMA uses this field to generate bits [31:0] of the address field for the Done IMWr TLP. Bits [1:0] must be '00' as this address must be dword aligned. Note: The access attributes of this field are as follows: - Wire: No access." line.long 0x4 "DMA_READ_DONE_IMWR_HIGH_OFF,DMA Read Done IMWr Address High Register." hexmask.long 0x4 0.--31. 1. "DMA_READ_DONE_HIGH_REG,The DMA uses this field to generate bits [63:32] of the address field for the Done IMWr TLP. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" line.long 0x8 "DMA_READ_ABORT_IMWR_LOW_OFF,DMA Read Abort IMWr Address Low Register." hexmask.long 0x8 0.--31. 1. "DMA_READ_ABORT_LOW_REG,The DMA uses this field to generate bits [31:0] of the address field for the Abort IMWr TLP. Bits [1:0] must be '00' as this address must be dword aligned. Note: The access attributes of this field are as follows: - Wire: No.." line.long 0xC "DMA_READ_ABORT_IMWR_HIGH_OFF,DMA Read Abort IMWr Address High Register." hexmask.long 0xC 0.--31. 1. "DMA_READ_ABORT_HIGH_REG,The DMA uses this field to generate bits [63:32] of the address field for the Abort IMWr TLP. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" line.long 0x10 "DMA_READ_CH01_IMWR_DATA_OFF,DMA Read Channel 1 and 0 IMWr Data Register." hexmask.long.word 0x10 16.--31. 1. "RD_CHANNEL_1_DATA,The DMA uses this field to generate the data field for the Done or Abort IMWr TLPs it generates for read channel 1. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" hexmask.long.word 0x10 0.--15. 1. "RD_CHANNEL_0_DATA,The DMA uses this field to generate the data field for the Done or Abort IMWr TLPs it generates for read channel 0. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" line.long 0x14 "DMA_READ_CH23_IMWR_DATA_OFF,DMA Read Channel 3 and 2 IMWr Data Register." hexmask.long.word 0x14 16.--31. 1. "RD_CHANNEL_3_DATA,The DMA uses this field to generate the data field for the Done or Abort IMWr TLPs it generates for read channel 3. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" hexmask.long.word 0x14 0.--15. 1. "RD_CHANNEL_2_DATA,The DMA uses this field to generate the data field for the Done or Abort IMWr TLPs it generates for read channel 2. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" line.long 0x18 "DMA_READ_CH45_IMWR_DATA_OFF,DMA Read Channel 5 and 4 IMWr Data Register." hexmask.long.word 0x18 16.--31. 1. "RD_CHANNEL_5_DATA,The DMA uses this field to generate the data field for the Done or Abort IMWr TLPs it generates for read channel 5. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" hexmask.long.word 0x18 0.--15. 1. "RD_CHANNEL_4_DATA,The DMA uses this field to generate the data field for the Done or Abort IMWr TLPs it generates for read channel 4. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" line.long 0x1C "DMA_READ_CH67_IMWR_DATA_OFF,DMA Read Channel 7 and 6 IMWr Data Register." hexmask.long.word 0x1C 16.--31. 1. "RD_CHANNEL_7_DATA,The DMA uses this field to generate the data field for the Done or Abort IMWr TLPs it generates for read channel 7. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" hexmask.long.word 0x1C 0.--15. 1. "RD_CHANNEL_6_DATA,The DMA uses this field to generate the data field for the Done or Abort IMWr TLPs it generates for read channel 6. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" rgroup.long (0x108+0xC8000)++0x7 line.long 0x0 "DMA_WRITE_ENGINE_HSHAKE_CNT_LOW_OFF,DMA Write Engine Handshake Counter Channel 0/1/2/3 Register." bitfld.long 0x0 29.--31. "RSVDP_29,Reserved for future use." "0,1,2,3,4,5,6,7" hexmask.long.byte 0x0 24.--28. 1. "DMA_WRITE_ENGINE_HSHAKE_CNT_CH3,DMA handshake counter for DMA Write Engine Channel 3. If CC_DMA_HSHAKE =1 the data transfer in Linked List mode starts only when the counter is non-zero." newline bitfld.long 0x0 21.--23. "RSVDP_21,Reserved for future use." "0,1,2,3,4,5,6,7" hexmask.long.byte 0x0 16.--20. 1. "DMA_WRITE_ENGINE_HSHAKE_CNT_CH2,DMA handshake counter for DMA Write Engine Channel 2. If CC_DMA_HSHAKE =1 the data transfer in Linked List mode starts only when the counter is non-zero." newline bitfld.long 0x0 13.--15. "RSVDP_13,Reserved for future use." "0,1,2,3,4,5,6,7" hexmask.long.byte 0x0 8.--12. 1. "DMA_WRITE_ENGINE_HSHAKE_CNT_CH1,DMA handshake counter for DMA Write Engine Channel 1. If CC_DMA_HSHAKE =1 the data transfer in Linked List mode starts only when the counter is non-zero." newline bitfld.long 0x0 5.--7. "RSVDP_5,Reserved for future use." "0,1,2,3,4,5,6,7" hexmask.long.byte 0x0 0.--4. 1. "DMA_WRITE_ENGINE_HSHAKE_CNT_CH0,DMA handshake counter for DMA Write Engine Channel 0. If CC_DMA_HSHAKE =1 the data transfer in Linked List mode starts only when the counter is non-zero." line.long 0x4 "DMA_WRITE_ENGINE_HSHAKE_CNT_HIGH_OFF,DMA Write Engine Handshake Counter Channel 4/5/6/7 Register." bitfld.long 0x4 29.--31. "RSVDP_29,Reserved for future use." "0,1,2,3,4,5,6,7" hexmask.long.byte 0x4 24.--28. 1. "DMA_WRITE_ENGINE_HSHAKE_CNT_CH7,DMA handshake counter for DMA Write Engine Channel 7. If CC_DMA_HSHAKE =1 the data transfer in Linked List mode starts only when the counter is non-zero." newline bitfld.long 0x4 21.--23. "RSVDP_21,Reserved for future use." "0,1,2,3,4,5,6,7" hexmask.long.byte 0x4 16.--20. 1. "DMA_WRITE_ENGINE_HSHAKE_CNT_CH6,DMA handshake counter for DMA Write Engine Channel 6. If CC_DMA_HSHAKE =1 the data transfer in Linked List mode starts only when the counter is non-zero." newline bitfld.long 0x4 13.--15. "RSVDP_13,Reserved for future use." "0,1,2,3,4,5,6,7" hexmask.long.byte 0x4 8.--12. 1. "DMA_WRITE_ENGINE_HSHAKE_CNT_CH5,DMA handshake counter for DMA Write Engine Channel 5. If CC_DMA_HSHAKE =1 the data transfer in Linked List mode starts only when the counter is non-zero." newline bitfld.long 0x4 5.--7. "RSVDP_5,Reserved for future use." "0,1,2,3,4,5,6,7" hexmask.long.byte 0x4 0.--4. 1. "DMA_WRITE_ENGINE_HSHAKE_CNT_CH4,DMA handshake counter for DMA Write Engine Channel 4. If CC_DMA_HSHAKE =1 the data transfer in Linked List mode starts only when the counter is non-zero." rgroup.long (0x118+0xC8000)++0x7 line.long 0x0 "DMA_READ_ENGINE_HSHAKE_CNT_LOW_OFF,DMA Read Engine Handshake Counter Channel 0/1/2/3 Register." bitfld.long 0x0 29.--31. "RSVDP_29,Reserved for future use." "0,1,2,3,4,5,6,7" hexmask.long.byte 0x0 24.--28. 1. "DMA_READ_ENGINE_HSHAKE_CNT_CH3,DMA handshake counter for DMA Read Engine Channel 3. If CC_DMA_HSHAKE =1 the data transfer in Linked List mode starts only when the counter is non-zero." newline bitfld.long 0x0 21.--23. "RSVDP_21,Reserved for future use." "0,1,2,3,4,5,6,7" hexmask.long.byte 0x0 16.--20. 1. "DMA_READ_ENGINE_HSHAKE_CNT_CH2,DMA handshake counter for DMA Read Engine Channel 2. If CC_DMA_HSHAKE =1 the data transfer in Linked List mode starts only when the counter is non-zero." newline bitfld.long 0x0 13.--15. "RSVDP_13,Reserved for future use." "0,1,2,3,4,5,6,7" hexmask.long.byte 0x0 8.--12. 1. "DMA_READ_ENGINE_HSHAKE_CNT_CH1,DMA handshake counter for DMA Read Engine Channel 1. If CC_DMA_HSHAKE =1 the data transfer in Linked List mode starts only when the counter is non-zero." newline bitfld.long 0x0 5.--7. "RSVDP_5,Reserved for future use." "0,1,2,3,4,5,6,7" hexmask.long.byte 0x0 0.--4. 1. "DMA_READ_ENGINE_HSHAKE_CNT_CH0,DMA handshake counter for DMA Read Engine Channel 0. If CC_DMA_HSHAKE =1 the data transfer in Linked List mode starts only when the counter is non-zero." line.long 0x4 "DMA_READ_ENGINE_HSHAKE_CNT_HIGH_OFF,DMA Read Engine Handshake Counter Channel 4/5/6/7 Register." bitfld.long 0x4 29.--31. "RSVDP_29,Reserved for future use." "0,1,2,3,4,5,6,7" hexmask.long.byte 0x4 24.--28. 1. "DMA_READ_ENGINE_HSHAKE_CNT_CH7,DMA handshake counter for DMA Read Engine Channel 7. If CC_DMA_HSHAKE =1 the data transfer in Linked List mode starts only when the counter is non-zero." newline bitfld.long 0x4 21.--23. "RSVDP_21,Reserved for future use." "0,1,2,3,4,5,6,7" hexmask.long.byte 0x4 16.--20. 1. "DMA_READ_ENGINE_HSHAKE_CNT_CH6,DMA handshake counter for DMA Read Engine Channel 6. If CC_DMA_HSHAKE =1 the data transfer in Linked List mode starts only when the counter is non-zero." newline bitfld.long 0x4 13.--15. "RSVDP_13,Reserved for future use." "0,1,2,3,4,5,6,7" hexmask.long.byte 0x4 8.--12. 1. "DMA_READ_ENGINE_HSHAKE_CNT_CH5,DMA handshake counter for DMA Read Engine Channel 5. If CC_DMA_HSHAKE =1 the data transfer in Linked List mode starts only when the counter is non-zero." newline bitfld.long 0x4 5.--7. "RSVDP_5,Reserved for future use." "0,1,2,3,4,5,6,7" hexmask.long.byte 0x4 0.--4. 1. "DMA_READ_ENGINE_HSHAKE_CNT_CH4,DMA handshake counter for DMA Read Engine Channel 4. If CC_DMA_HSHAKE =1 the data transfer in Linked List mode starts only when the counter is non-zero." repeat 8. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 )(list 0x0 0x200 0x400 0x600 0x800 0xA00 0xC00 0xE00 ) group.long ($2+0x200+0xC8000)++0x3 line.long 0x0 "DMA_CH_CONTROL1_OFF_WRCH_$1,DMA Write Channel Control 1 Register." bitfld.long 0x0 30.--31. "DMA_AT,Address Translation TLP Header Bit (AT) The DMA uses this TLP header field when generating MRd/MWr (not IMWr) TLPs. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" "0,1,2,3" bitfld.long 0x0 27.--29. "DMA_TC,Traffic Class TLP Header Bit (TC) The DMA uses this TLP header field when generating MRd/MWr (not IMWr) TLPs. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 26. "DMA_RESERVED5,Reserved. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" "0,1" bitfld.long 0x0 25. "DMA_RO,Relaxed Ordering TLP Header Bit (RO) The DMA uses this TLP header field when generating MRd/MWr (not IMWr) TLPs. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" "0,1" newline bitfld.long 0x0 24. "DMA_NS_SRC,Source No Snoop TLP Header Bit (DMA_NS_SRC). The DMA uses this TLP header field when generating MRd (SAR addressing space) (not IMWr) TLPs. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" "0,1" bitfld.long 0x0 23. "DMA_NS_DST,Destination No Snoop TLP Header Bit (DMA_NS_DST). The DMA uses this TLP header field when generating MWr (DAR addressing space) (not IMWr) TLPs. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" "0,1" newline bitfld.long 0x0 22. "DMA_MEM_TYPE,Master AXI ACE-Lite Cache Coherency Control. This field sets the DMA channel memory type of the address space of the data transfer as follows: - 0x0:peripheral type - 0x1:memory type For more details see 'ACE-Lite Features and Limitations'.." "peripheral type,memory type" hexmask.long.byte 0x0 17.--21. 1. "DMA_RESERVED2,Reserved. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" newline hexmask.long.byte 0x0 12.--16. 1. "DMA_FUNC_NUM,Function Number (FN). The controller uses this field when generating the requester ID for the MRd/MWr DMA TLP. When you have enabled SR-IOV then this field is ignored if you have set the VFE field in the 'DMA Write Channel Control 2.." bitfld.long 0x0 10.--11. "DMA_RESERVED1,Reserved. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" "0,1,2,3" newline bitfld.long 0x0 9. "LLE,Linked List Enable (LLE). - 0: Disable linked list operation - 1: Enable linked list operation Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" "Disable linked list operation,Enable linked list operation" bitfld.long 0x0 8. "CCS,Consumer Cycle State (CCS). Used in linked list mode only. It is used to synchronize the producer (software) and the consumer (DMA). For more details see 'PCS-CCS-CB-TCB Producer-Consumer Synchronization'. You must initialize this bit. The DMA.." "0,1" newline bitfld.long 0x0 7. "DMA_RESERVED0,Reserved. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" "0,1" bitfld.long 0x0 5.--6. "CS,Channel Status (CS). The channel status bits identify the current operational state of the DMA channel. The operation state encoding for each DMA channel is a s follows: - 00: Reserved - 01: Running. This channel is active and transferring data. - 10:.." "Reserved,Running,?,?" newline bitfld.long 0x0 4. "RIE,Remote Interrupt Enable (RIE). You must set this bit to enable the generation of the Done or Abort Remote interrupts. For more details see 'Interrupts and Error Handling'. In LL mode the DMA overwrites this with the RIE of the LL element. The RIE.." "0,1" bitfld.long 0x0 3. "LIE,Local Interrupt Enable (LIE). You must set this bit to enable the generation of the Done or Abort Local interrupts. For more details see 'Interrupts and Error Handling'. In LL mode the DMA overwrites this with the LIE of the LL element. The LIE bit.." "0,1" newline bitfld.long 0x0 2. "LLP,Load Link Pointer (LLP). Used in linked list mode only. Indicates that this linked list element is a link element and its LL element pointer dwords are pointing to the next (non-contiguous) element. The DMA loads this field with the LLP of the.." "0,1" bitfld.long 0x0 1. "TCB,Toggle Cycle Bit (TCB). Indicates to the DMA to toggle its interpretation of the CB. Used in linked list mode only. It is used to synchronize the producer (software) and the consumer (DMA). For more details see 'PCS-CCS-CB-TCB Producer-Consumer.." "0,1" newline bitfld.long 0x0 0. "CB,Cycle Bit (CB). Used in linked list mode only. It is used to synchronize the producer (software) and the consumer (DMA). For more details see 'PCS-CCS-CB-TCB Producer-Consumer Synchronization'. The DMA loads this field with the CB of the linked list.." "0,1" repeat.end repeat 8. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 )(list 0x0 0x200 0x400 0x600 0x800 0xA00 0xC00 0xE00 ) group.long ($2+0x208+0xC8000)++0x3 line.long 0x0 "DMA_TRANSFER_SIZE_OFF_WRCH_$1,DMA Write Transfer Size Register." hexmask.long 0x0 0.--31. 1. "DMA_TRANSFER_SIZE,DMA Transfer Size. You program this register with the size of the DMA transfer. The maximum DMA transfer size is 4Gbytes. The minimum transfer size is one byte (0x1). This field is automatically decremented by the DMA as the DMA write.." repeat.end repeat 8. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 )(list 0x0 0x200 0x400 0x600 0x800 0xA00 0xC00 0xE00 ) group.long ($2+0x20C+0xC8000)++0x3 line.long 0x0 "DMA_SAR_LOW_OFF_WRCH_$1,DMA Write SAR Low Register." hexmask.long 0x0 0.--31. 1. "SRC_ADDR_REG_LOW,Source Address Register (Lower 32 bits). Indicates the next address to be read from. The DMA increments the SAR as the DMA transfer progresses. In LL mode the DMA overwrites this with the corresponding dword of the LL element. - DMA.." repeat.end repeat 8. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 )(list 0x0 0x200 0x400 0x600 0x800 0xA00 0xC00 0xE00 ) group.long ($2+0x210+0xC8000)++0x3 line.long 0x0 "DMA_SAR_HIGH_OFF_WRCH_$1,DMA Write SAR High Register." hexmask.long 0x0 0.--31. 1. "SRC_ADDR_REG_HIGH,Source Address Register (Higher 32 bits). In LL mode the DMA overwrites this with the corresponding dword of the LL element. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" repeat.end repeat 8. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 )(list 0x0 0x200 0x400 0x600 0x800 0xA00 0xC00 0xE00 ) group.long ($2+0x214+0xC8000)++0x3 line.long 0x0 "DMA_DAR_LOW_OFF_WRCH_$1,DMA Write DAR Low Register." hexmask.long 0x0 0.--31. 1. "DST_ADDR_REG_LOW,Destination Address Register (Lower 32 bits). Indicates the next address to be written to. The DMA increments the DAR as the DMA transfer progresses. In LL mode the DMA overwrites this with the corresponding dword of the LL element. -.." repeat.end repeat 8. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 )(list 0x0 0x200 0x400 0x600 0x800 0xA00 0xC00 0xE00 ) group.long ($2+0x218+0xC8000)++0x3 line.long 0x0 "DMA_DAR_HIGH_OFF_WRCH_$1,DMA Write DAR High Register." hexmask.long 0x0 0.--31. 1. "DST_ADDR_REG_HIGH,Destination Address Register (Higher 32 bits). In LL mode the DMA overwrites this with the corresponding dword of the LL element. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" repeat.end repeat 8. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 )(list 0x0 0x200 0x400 0x600 0x800 0xA00 0xC00 0xE00 ) group.long ($2+0x21C+0xC8000)++0x3 line.long 0x0 "DMA_LLP_LOW_OFF_WRCH_$1,DMA Write Linked List Pointer Low Register." hexmask.long 0x0 0.--31. 1. "LLP_LOW,Lower bits of the address of the linked list transfer list in local memory. Used in linked list mode only. Updated by the DMA to point to the next element in the transfer list after the previous element is consumed. - When the current element is.." repeat.end repeat 8. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 )(list 0x0 0x200 0x400 0x600 0x800 0xA00 0xC00 0xE00 ) group.long ($2+0x220+0xC8000)++0x3 line.long 0x0 "DMA_LLP_HIGH_OFF_WRCH_$1,DMA Write Linked List Pointer High Register." hexmask.long 0x0 0.--31. 1. "LLP_HIGH,Upper 32 bits of the address of the linked list transfer list in local memory. Used in linked list mode only. Updated by the DMA to point to the next element in the transfer list as elements are consumed. Note: The access attributes of this.." repeat.end repeat 8. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 )(list 0x0 0x200 0x400 0x600 0x800 0xA00 0xC00 0xE00 ) group.long ($2+0x300+0xC8000)++0x3 line.long 0x0 "DMA_CH_CONTROL1_OFF_RDCH_$1,DMA Read Channel Control 1 Register." bitfld.long 0x0 30.--31. "DMA_AT,Address Translation TLP Header Bit (AT) The DMA uses this TLP header field when generating MRd/MWr (not IMWr) TLPs. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" "0,1,2,3" bitfld.long 0x0 27.--29. "DMA_TC,Traffic Class TLP Header Bit (TC) The DMA uses this TLP header field when generating MRd/MWr (not IMWr) TLPs. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 26. "DMA_RESERVED5,Reserved. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" "0,1" bitfld.long 0x0 25. "DMA_RO,Relaxed Ordering TLP Header Bit (RO) The DMA uses this TLP header field when generating MRd/MWr (not IMWr) TLPs. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" "0,1" newline bitfld.long 0x0 24. "DMA_NS_SRC,Source No Snoop TLP Header Bit (DMA_NS_SRC). The DMA uses this TLP header field when generating MRd (SAR addressing space) (not IMWr) TLPs. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" "0,1" bitfld.long 0x0 23. "DMA_NS_DST,Destination No Snoop TLP Header Bit (DMA_NS_DST). The DMA uses this TLP header field when generating MWr (DAR addressing space) (not IMWr) TLPs. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" "0,1" newline bitfld.long 0x0 22. "DMA_MEM_TYPE,Master AXI ACE-Lite Cache Coherency Control. This field sets the DMA channel memory type of the address space of the data transfer as follows: - 0x0:peripheral type - 0x1:memory type For more details see 'ACE-Lite Features and Limitations'.." "peripheral type,memory type" hexmask.long.byte 0x0 17.--21. 1. "DMA_RESERVED2,Reserved. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" newline hexmask.long.byte 0x0 12.--16. 1. "DMA_FUNC_NUM,Function Number (FN). The controller uses this field when generating the requester ID for the MRd/MWr DMA TLP. When you have enabled SR-IOV then this field is ignored if you have set the VFE field in the 'DMA Read Channel Control 2.." bitfld.long 0x0 10.--11. "DMA_RESERVED1,Reserved. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" "0,1,2,3" newline bitfld.long 0x0 9. "LLE,Linked List Enable (LLE). - 0: Disable linked list operation - 1: Enable linked list operation Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" "Disable linked list operation,Enable linked list operation" bitfld.long 0x0 8. "CCS,Consumer Cycle State (CCS). Used in linked list mode only. It is used to synchronize the producer (software) and the consumer (DMA). For more details see 'PCS-CCS-CB-TCB Producer-Consumer Synchronization'. You must initialize this bit. The DMA.." "0,1" newline bitfld.long 0x0 7. "DMA_RESERVED0,Reserved. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" "0,1" bitfld.long 0x0 5.--6. "CS,Channel Status (CS). The channel status bits identify the current operational state of the DMA channel. The operation state encoding for each DMA channel is a s follows: - 00: Reserved - 01: Running. This channel is active and transferring data. - 10:.." "Reserved,Running,?,?" newline bitfld.long 0x0 4. "RIE,Remote Interrupt Enable (RIE). You must set this bit to enable the generation of the Done or Abort Remote interrupts. For more details see 'Interrupts and Error Handling'. In LL mode the DMA overwrites this with the RIE of the LL element. The RIE.." "0,1" bitfld.long 0x0 3. "LIE,Local Interrupt Enable (LIE). You must set this bit to enable the generation of the Done or Abort Local interrupts. For more details see 'Interrupts and Error Handling'. In LL mode the DMA overwrites this with the LIE of the LL element. The LIE bit.." "0,1" newline bitfld.long 0x0 2. "LLP,Load Link Pointer (LLP). Used in linked list mode only. Indicates that this linked list element is a link element and its LL element pointer dwords are pointing to the next (non-contiguous) element. The DMA loads this field with the LLP of the.." "0,1" bitfld.long 0x0 1. "TCB,Toggle Cycle Bit (TCB). Indicates to the DMA to toggle its interpretation of the CB. Used in linked list mode only. It is used to synchronize the producer (software) and the consumer (DMA). For more details see 'PCS-CCS-CB-TCB Producer-Consumer.." "0,1" newline bitfld.long 0x0 0. "CB,Cycle Bit (CB). Used in linked list mode only. It is used to synchronize the producer (software) and the consumer (DMA). For more details see 'PCS-CCS-CB-TCB Producer-Consumer Synchronization'. The DMA loads this field with the CB of the linked list.." "0,1" repeat.end repeat 8. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 )(list 0x0 0x200 0x400 0x600 0x800 0xA00 0xC00 0xE00 ) group.long ($2+0x308+0xC8000)++0x3 line.long 0x0 "DMA_TRANSFER_SIZE_OFF_RDCH_$1,DMA Read Transfer Size Register." hexmask.long 0x0 0.--31. 1. "DMA_TRANSFER_SIZE,DMA Transfer Size. You program this register with the size of the DMA transfer. The maximum DMA transfer size is 4Gbytes. The minimum transfer size is one byte (0x1). This field is automatically decremented by the DMA as the DMA read.." repeat.end repeat 8. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 )(list 0x0 0x200 0x400 0x600 0x800 0xA00 0xC00 0xE00 ) group.long ($2+0x30C+0xC8000)++0x3 line.long 0x0 "DMA_SAR_LOW_OFF_RDCH_$1,DMA Read SAR Low Register." hexmask.long 0x0 0.--31. 1. "SRC_ADDR_REG_LOW,Source Address Register (Lower 32 bits). Indicates the next address to be read from. The DMA increments the SAR as the DMA transfer progresses. In LL mode the DMA overwrites this with the corresponding dword of the LL element. - DMA.." repeat.end repeat 8. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 )(list 0x0 0x200 0x400 0x600 0x800 0xA00 0xC00 0xE00 ) group.long ($2+0x310+0xC8000)++0x3 line.long 0x0 "DMA_SAR_HIGH_OFF_RDCH_$1,DMA Read SAR High Register." hexmask.long 0x0 0.--31. 1. "SRC_ADDR_REG_HIGH,Source Address Register (Higher 32 bits). In LL mode the DMA overwrites this with the corresponding dword of the LL element. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" repeat.end repeat 8. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 )(list 0x0 0x200 0x400 0x600 0x800 0xA00 0xC00 0xE00 ) group.long ($2+0x314+0xC8000)++0x3 line.long 0x0 "DMA_DAR_LOW_OFF_RDCH_$1,DMA Read DAR Low Register." hexmask.long 0x0 0.--31. 1. "DST_ADDR_REG_LOW,Destination Address Register (Lower 32 bits). Indicates the next address to be written to. The DMA increments the DAR as the DMA transfer progresses. In LL mode the DMA overwrites this with the corresponding dword of the LL element. -.." repeat.end repeat 8. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 )(list 0x0 0x200 0x400 0x600 0x800 0xA00 0xC00 0xE00 ) group.long ($2+0x318+0xC8000)++0x3 line.long 0x0 "DMA_DAR_HIGH_OFF_RDCH_$1,DMA Read DAR High Register." hexmask.long 0x0 0.--31. 1. "DST_ADDR_REG_HIGH,Destination Address Register (Higher 32 bits). In LL mode the DMA overwrites this with the corresponding dword of the LL element. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" repeat.end repeat 8. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 )(list 0x0 0x200 0x400 0x600 0x800 0xA00 0xC00 0xE00 ) group.long ($2+0x31C+0xC8000)++0x3 line.long 0x0 "DMA_LLP_LOW_OFF_RDCH_$1,DMA Read Linked List Pointer Low Register." hexmask.long 0x0 0.--31. 1. "LLP_LOW,Lower bits of the address of the linked list transfer list in local memory. Used in linked list mode only. Updated by the DMA to point to the next element in the transfer list after the previous element is consumed. - When the current element is.." repeat.end repeat 8. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 )(list 0x0 0x200 0x400 0x600 0x800 0xA00 0xC00 0xE00 ) group.long ($2+0x320+0xC8000)++0x3 line.long 0x0 "DMA_LLP_HIGH_OFF_RDCH_$1,DMA Read Linked List Pointer High Register." hexmask.long 0x0 0.--31. 1. "LLP_HIGH,Upper 32 bits of the address of the linked list transfer list in local memory. Used in linked list mode only. Updated by the DMA to point to the next element in the transfer list as elements are consumed. Note: The access attributes of this.." repeat.end tree.end tree "PF0_ATU_CAP (ATU Por Logic Structure)" repeat 8. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 )(list 0x0 0x200 0x400 0x600 0x800 0xA00 0xC00 0xE00 ) group.long ($2+0xC0000)++0x3 line.long 0x0 "IATU_REGION_CTRL_1_OFF_OUTBOUND_$1,iATU Region Control 1 Register." bitfld.long 0x0 20. "CTRL_1_FUNC_NUM,Function Number. - When the address of an outbound TLP is matched to this region and the FUNC_BYPASS field in the 'iATU Control 2 Register' is '0' then the function number used in generating the function part of the requester ID (RID).." "0,1" newline bitfld.long 0x0 13. "INCREASE_REGION_SIZE,Increase the maximum ATU Region size. When set the maximum ATU Region size is determined by CX_ATU_MAX_REGION_SIZE. When clear the maximum ATU Region size is 4 GB (default). Note: This register field is sticky." "0,1" newline bitfld.long 0x0 9.--10. "ATTR,When the address of an outbound TLP is matched to this region then the ATTR field of the TLP is changed to the value in this register. Note: This register field is sticky." "0,1,2,3" newline bitfld.long 0x0 8. "TD,This is a reserved field. Do not use. Note: This register field is sticky." "0,1" newline bitfld.long 0x0 5.--7. "TC,When the address of an outbound TLP is matched to this region then the TC field of the TLP is changed to the value in this register. Note: This register field is sticky." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x0 0.--4. 1. "TYPE,When the address of an outbound TLP is matched to this region then the TYPE field of the TLP is changed to the value in this register. Note: This register field is sticky." repeat.end repeat 8. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 )(list 0x0 0x200 0x400 0x600 0x800 0xA00 0xC00 0xE00 ) group.long ($2+0x4+0xC0000)++0x3 line.long 0x0 "IATU_REGION_CTRL_2_OFF_OUTBOUND_$1,iATU Region Control 2 Register." bitfld.long 0x0 31. "REGION_EN,Region Enable. This bit must be set to '1' for address translation to take place. Note: This register field is sticky." "0,1" newline bitfld.long 0x0 29. "INVERT_MODE,Invert Mode. When set the address matching region is inverted. Therefore an address match occurs when the untranslated address is in the region outside the defined range (Base Address to Limit Address). Note: This register field is sticky." "0,1" newline bitfld.long 0x0 28. "CFG_SHIFT_MODE,CFG Shift Mode. The iATU uses bits [27:12] of the untranslated address (on the XALI0/1/2 interface or AXI slave interface address) to form the BDF number of the outgoing CFG TLP. This supports the Enhanced Configuration Address Mapping.." "0,1" newline bitfld.long 0x0 27. "DMA_BYPASS,DMA Bypass Mode. Allows request TLPs which are initiated by the DMA controller to pass through the iATU untranslated. Note: This field is reserved for the SW product. You must set it to '0'. Note: This register field is sticky." "0,1" newline bitfld.long 0x0 23. "HEADER_SUBSTITUTE_EN,Header Substitute Enable. When enabled and region address is matched the iATU fully substitutes bytes 8-11 (for 3 DWORD header) or bytes 12-15 (for 4 DWORD header) of the outbound TLP header with the contents of the LWR_TARGET_RW.." "LWR_TARGET_RW in the..,LWR_TARGET_RW in the.." newline bitfld.long 0x0 22. "INHIBIT_PAYLOAD,Inhibit TLP Payload Data for TLP's in Matched Region; assign iATU region to be TLP without data. When enabled and region address is matched the iATU marks all TLPs as having no payload data by forcing the TLP header Fmt[1] bit =0.." "Fmt[1] =0/1 so that TLPs with or without data..,Fmt[1] =0 so that only TLP type without data is.." newline bitfld.long 0x0 21. "TLP_HEADER_FIELDS_BYPASS,TLP Header Fields Translation Bypass. In this mode header fields of the translated TLP is taken from your application transmit interface or if AMBA is configured from the AMBA sideband bus (slv_awmisc_info) and not from the.." "0,1" newline bitfld.long 0x0 20. "SNP,Serialize Non-Posted Requests. In this mode when the AXI Bridge is populated same AXI ID Non-Posted Read/Write Requests are transmitted on the wire if there are no other same ID Non-Posted Requests outstanding. Note: This register field is sticky." "0,1" newline bitfld.long 0x0 19. "FUNC_BYPASS,Function Number Translation Bypass. In this mode the function number of the translated TLP is taken from your application transmit interface and not from the CTRL_1_FUNC_NUM field of the 'iATU Control 1 Register' or the VF_NUMBER field of.." "0,1" newline bitfld.long 0x0 16. "TAG_SUBSTITUTE_EN,TAG Substitute Enable. When enabled and region address is matched the iATU substitutes the TAG field of the outbound TLP header with the contents of the TAG field in this register. The expected usage scenario is translation from AXI.." "0,1" newline hexmask.long.byte 0x0 8.--15. 1. "TAG,TAG. The substituted TAG field (byte 6) in the outgoing TLP header when TAG_SUBSTITUTE_EN is set. Note: This register field is sticky." newline hexmask.long.byte 0x0 0.--7. 1. "MSG_CODE,MSG TLPs (Message Code). When the address of an outbound TLP is matched to this region and the translated TLP TYPE field is Msg or MsgD; then the message field of the TLP is changed to the value in this register. Memory TLPs: (ST;Steering Tag)." repeat.end repeat 8. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 )(list 0x0 0x200 0x400 0x600 0x800 0xA00 0xC00 0xE00 ) group.long ($2+0x8+0xC0000)++0x3 line.long 0x0 "IATU_LWR_BASE_ADDR_OFF_OUTBOUND_$1,iATU Lower Base Address Register. The CX_ATU_MIN_REGION_SIZE configuration parameter (Value Range: 4 kB. 8 kB. 16 kB. 32 kB. 64 kB defaults to 64 kB) specifies the minimum size of an address translation region. For.." hexmask.long.tbyte 0x0 12.--31. 1. "LWR_BASE_RW,Forms bits [31:n] of the start address of the address region to be translated. n is log2(CX_ATU_MIN_REGION_SIZE) Note: This register field is sticky." newline hexmask.long.word 0x0 0.--11. 1. "LWR_BASE_HW,Forms bits [n-1:0] of the start address of the address region to be translated. The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary so these bits are always 0. A write to this location is ignored by the PCIe controller." repeat.end repeat 8. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 )(list 0x0 0x200 0x400 0x600 0x800 0xA00 0xC00 0xE00 ) group.long ($2+0xC+0xC0000)++0x3 line.long 0x0 "IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_$1,iATU Upper Base Address Register." hexmask.long 0x0 0.--31. 1. "UPPER_BASE_RW,Forms bits [63:32] of the start (and end) address of the address region to be translated. In systems with a 32-bit address space this register is not used and therefore writing to this register has no effect. Note: This register field is.." repeat.end repeat 8. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 )(list 0x0 0x200 0x400 0x600 0x800 0xA00 0xC00 0xE00 ) group.long ($2+0x10+0xC0000)++0x3 line.long 0x0 "IATU_LIMIT_ADDR_OFF_OUTBOUND_$1,iATU Limit Address Register." hexmask.long.tbyte 0x0 12.--31. 1. "LIMIT_ADDR_RW,Forms upper bits of the end address of the address region to be translated. Note: This register field is sticky." newline hexmask.long.word 0x0 0.--11. 1. "LIMIT_ADDR_HW,Forms lower bits of the end address of the address region to be translated. The end address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary so these bits are always all ones. A write to this location is ignored by the PCIe.." repeat.end repeat 8. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 )(list 0x0 0x200 0x400 0x600 0x800 0xA00 0xC00 0xE00 ) group.long ($2+0x14+0xC0000)++0x3 line.long 0x0 "IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_$1,iATU Lower Target Address Register." hexmask.long 0x0 0.--31. 1. "LWR_TARGET_RW_OUTBOUND,When HEADER_SUBSTITUTE_EN in IATU_REGION_CTRL_2_OFF_OUTBOUND_ is '0' (normal operation): - LWR_TARGET_RW[31:n] forms MSB's of the Lower Target part of the new address of the translated region; - LWR_TARGET_RW[n-1:0] are not used." repeat.end repeat 8. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 )(list 0x0 0x200 0x400 0x600 0x800 0xA00 0xC00 0xE00 ) group.long ($2+0x18+0xC0000)++0x3 line.long 0x0 "IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_$1,iATU Upper Target Address Register." hexmask.long 0x0 0.--31. 1. "UPPER_TARGET_RW,Forms bits [63:32] of the start address (Upper Target part) of the new address of the translated region. Note: This register field is sticky." repeat.end repeat 8. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 )(list 0x0 0x200 0x400 0x600 0x800 0xA00 0xC00 0xE00 ) group.long ($2+0x1C+0xC0000)++0x3 line.long 0x0 "IATU_REGION_CTRL_3_OFF_OUTBOUND_$1,iATU Region Control 3 Register." bitfld.long 0x0 31. "VF_ACTIVE,Virtual Function Active. Indicates that all of the outbound accesses are from virtual functions. For more details see VF_ACTIVE field. Note: This register field is sticky." "0,1" newline hexmask.long 0x0 3.--30. 1. "RSVDP_VF_NUMBER,Reserved for future use." newline bitfld.long 0x0 0.--2. "VF_NUMBER,Virtual Function Number. When the address of an outbound TLP is matched to this region and the FUNC_BYPASS field in the 'iATU Control 2 Register' is '0' then this field used in generating the Function part of the requester ID (RID) field of.." "0,1,2,3,4,5,6,7" repeat.end repeat 8. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 )(list 0x0 0x200 0x400 0x600 0x800 0xA00 0xC00 0xE00 ) group.long ($2+0x100+0xC0000)++0x3 line.long 0x0 "IATU_REGION_CTRL_1_OFF_INBOUND_$1,iATU Region Control 1 Register." bitfld.long 0x0 20. "CTRL_1_FUNC_NUM,Function Number. - MEM-I/O: When the Address and BAR matching logic in the controller indicate that a MEM-I/O transaction matches a BAR in the function corresponding to this value then address translation proceeds. This check is only.." "?,When the destination function number as.." newline bitfld.long 0x0 13. "INCREASE_REGION_SIZE,Increase the maximum ATU Region size. When set the maximum ATU Region size is determined by CX_ATU_MAX_REGION_SIZE. When clear the maximum ATU Region size is 4 GB (default). Note: This register field is sticky." "0,1" newline bitfld.long 0x0 9.--10. "ATTR,When the ATTR field of an inbound TLP is matched to this value then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the 'ATTR Match Enable' bit of the 'iATU Control 2 Register' is.." "0,1,2,3" newline bitfld.long 0x0 8. "TD,When the TD field of an inbound TLP is matched to this value then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the 'TD Match Enable' bit of the 'iATU Control 2 Register' is set." "0,1" newline bitfld.long 0x0 5.--7. "TC,When the TC field of an inbound TLP is matched to this value then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the 'TC Match Enable' bit of the 'iATU Control 2 Register' is set." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x0 0.--4. 1. "TYPE,When the TYPE field of an inbound TLP is matched to this value then address translation proceeds (when all other enabled field-matches are successful). Note: This register field is sticky." repeat.end repeat 8. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 )(list 0x0 0x200 0x400 0x600 0x800 0xA00 0xC00 0xE00 ) group.long ($2+0x104+0xC0000)++0x3 line.long 0x0 "IATU_REGION_CTRL_2_OFF_INBOUND_$1,iATU Region Control 2 Register." bitfld.long 0x0 31. "REGION_EN,Region Enable. This bit must be set to '1' for address translation to take place. Note: This register field is sticky." "0,1" newline bitfld.long 0x0 30. "MATCH_MODE,Match Mode. Determines Inbound matching mode for TLPs. The mode depends on the type of TLP that is received as follows: For MEM-I/O TLPs this field is interpreted as follows: - 0: Address Match Mode. The iATU operates using addresses as in.." "Address Match Mode,Vendor ID Match Mode" newline bitfld.long 0x0 29. "INVERT_MODE,Invert Mode. When set the address matching region is inverted. Therefore an address match occurs when the untranslated address is in the region outside the defined range (Base Address to Limit Address). Note: This register field is sticky." "0,1" newline bitfld.long 0x0 28. "CFG_SHIFT_MODE,CFG Shift Mode. This is useful for CFG transactions where the PCIe configuration mechanism maps bits [27:12] of the address to the bus/device and function number. This allows a CFG configuration space to be located in any 256MB window of.." "0,1" newline bitfld.long 0x0 27. "FUZZY_TYPE_MATCH_CODE,Fuzzy Type Match Mode. When enabled the iATU relaxes the matching of the TLP TYPE field against the expected TYPE field so that - CfgRd0 and CfgRd1 TLPs are seen as identical. Similarly with CfgWr0 and CfgWr1. - MWr MRd and MRdLk.." "0,1" newline bitfld.long 0x0 26. "VFBAR_MATCH_MODE_EN,VF BAR Match Mode enable. When set Virtual Function BAR matching is used which allows all VFs in a PF which match a BAR to be matched with a single ATU region. Note: This register field is sticky." "0,1" newline bitfld.long 0x0 24.--25. "RESPONSE_CODE,Response Code. Defines the type of response to give for accesses matching this region. This overrides the normal RADM filter response. Note that this feature is not available for any region where Single Address Location Translate is.." "Normal RADM filter response is used,Unsupported request,?,?" newline bitfld.long 0x0 23. "SINGLE_ADDR_LOC_TRANS_EN,Single Address Location Translate Enable. When enabled Rx TLPs can be translated to a single address location as determined by the target address register of the iATU region. The main usage scenario is translation of Messages.." "0,1" newline bitfld.long 0x0 21. "MSG_CODE_MATCH_EN,Message Code Match Enable (Msg TLPS). Ensures that a successful message Code TLP field comparison match (see Message Code field of the 'iATU Control 2 Register') occurs (in MSG transactions) for address translation to proceed. ST Match.." "0,1" newline bitfld.long 0x0 20. "VF_MATCH_EN,Virtual Function Number Match Enable. Ensures that a successful Virtual Function Number TLP field comparison match (see Virtual Function Number field of the 'iATU Control 3 Register') occurs (in MEM-I/O transactions) for address translation.." "0,1" newline bitfld.long 0x0 19. "FUNC_NUM_MATCH_EN,Function Number Match Enable. Ensures that a successful Function Number TLP field comparison match (see Function Number field of the 'iATU Control 1 Register') occurs (in MEM-I/O and CFG0/CFG1 transactions) for address translation to.." "0,1" newline bitfld.long 0x0 16. "ATTR_MATCH_EN,ATTR Match Enable. Ensures that a successful ATTR TLP field comparison match (see ATTR field of the 'iATU Control 1 Register') occurs for address translation to proceed. Note: This register field is sticky." "0,1" newline bitfld.long 0x0 15. "TD_MATCH_EN,TD Match Enable. Ensures that a successful TD TLP field comparison match (see TD field of the 'iATU Control 1 Register') occurs for address translation to proceed. Note: This register field is sticky." "0,1" newline bitfld.long 0x0 14. "TC_MATCH_EN,TC Match Enable. Ensures that a successful TC TLP field comparison match (see TC field of the 'iATU Control 1 Register') occurs for address translation to proceed. Note: This register field is sticky." "0,1" newline bitfld.long 0x0 13. "MSG_TYPE_MATCH_MODE,Message Type Match Mode. When enabled and if single address location translate enable is set then inbound TLPs of type MSG/MSGd which match the type field of the iatu_region_ctrl_1_OFF_inbound register (=>TYPE[4:3]=2'b10) will be.." "0,1" newline bitfld.long 0x0 8.--10. "BAR_NUM,BAR Number. When the BAR number of an inbound MEM or IO TLP ' that is matched by the normal internal BAR address matching mechanism ' is the same as this field address translation proceeds (when all other enabled field-matches are successful)." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x0 0.--7. 1. "MSG_CODE,MSG TLPs: (Message Code). When the TYPE field of an inbound Msg/MsgD TLP is matched to this value then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the 'Message Code Match.." repeat.end repeat 8. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 )(list 0x0 0x200 0x400 0x600 0x800 0xA00 0xC00 0xE00 ) group.long ($2+0x108+0xC0000)++0x3 line.long 0x0 "IATU_LWR_BASE_ADDR_OFF_INBOUND_$1,iATU Lower Base Address Register. The CX_ATU_MIN_REGION_SIZE configuration parameter (Value Range: 4 kB. 8 kB. 16 kB. 32 kB. 64 kB defaults to 64 kB) specifies the minimum size of an address translation region. For.." hexmask.long.tbyte 0x0 12.--31. 1. "LWR_BASE_RW,Forms bits [31:n] of the start address of the address region to be translated. n is log2(CX_ATU_MIN_REGION_SIZE) Note: This register field is sticky." newline hexmask.long.word 0x0 0.--11. 1. "LWR_BASE_HW,Forms bits [n-1:0] of the start address of the address region to be translated. The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary so these bits are always 0. A write to this location is ignored by the PCIe controller." repeat.end repeat 8. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 )(list 0x0 0x200 0x400 0x600 0x800 0xA00 0xC00 0xE00 ) group.long ($2+0x10C+0xC0000)++0x3 line.long 0x0 "IATU_UPPER_BASE_ADDR_OFF_INBOUND_$1,iATU Upper Base Address Register." hexmask.long 0x0 0.--31. 1. "UPPER_BASE_RW,Forms bits [63:32] of the start (and end) address of the address region to be translated. Note: This register field is sticky." repeat.end repeat 8. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 )(list 0x0 0x200 0x400 0x600 0x800 0xA00 0xC00 0xE00 ) group.long ($2+0x110+0xC0000)++0x3 line.long 0x0 "IATU_LIMIT_ADDR_OFF_INBOUND_$1,iATU Limit Address Register." hexmask.long.tbyte 0x0 12.--31. 1. "LIMIT_ADDR_RW,Forms upper bits of the end address of the address region to be translated. Note: This register field is sticky." newline hexmask.long.word 0x0 0.--11. 1. "LIMIT_ADDR_HW,Forms lower bits of the end address of the address region to be translated. The end address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary so these bits are always all ones. A write to this location is ignored by the PCIe.." repeat.end repeat 8. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 )(list 0x0 0x200 0x400 0x600 0x800 0xA00 0xC00 0xE00 ) group.long ($2+0x114+0xC0000)++0x3 line.long 0x0 "IATU_LWR_TARGET_ADDR_OFF_INBOUND_$1,iATU Lower Target Address Register." hexmask.long.tbyte 0x0 12.--31. 1. "LWR_TARGET_RW,Forms MSB's of the Lower Target part of the new address of the translated region. These bits are always '0'. - Field size depends on log2(CX_ATU_MIN_REGION_SIZE) in address match mode. - Field size depends on log2(BAR_MASK+1) in BAR match.." newline hexmask.long.word 0x0 0.--11. 1. "LWR_TARGET_HW,Forms the LSB's of the Lower Target part of the new address of the translated region. The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary (in address match mode); and to the Bar size boundary (in BAR match mode) so.." repeat.end repeat 8. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 )(list 0x0 0x200 0x400 0x600 0x800 0xA00 0xC00 0xE00 ) group.long ($2+0x118+0xC0000)++0x3 line.long 0x0 "IATU_UPPER_TARGET_ADDR_OFF_INBOUND_$1,iATU Upper Target Address Register." hexmask.long 0x0 0.--31. 1. "UPPER_TARGET_RW,Forms bits [63:32] of the start address (Upper Target part) of the new address of the translated region. In systems with a 32-bit address space this register is not used and therefore writing to this register has no effect. Note: This.." repeat.end repeat 8. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 )(list 0x0 0x200 0x400 0x600 0x800 0xA00 0xC00 0xE00 ) group.long ($2+0x11C+0xC0000)++0x3 line.long 0x0 "IATU_REGION_CTRL_3_OFF_INBOUND_$1,iATU Region Control 3 Register." rbitfld.long 0x0 31. "VF_ACTIVE,Reserved. Not used." "0,1" newline hexmask.long 0x0 3.--30. 1. "RSVDP_VF_NUMBER,Reserved for future use." newline bitfld.long 0x0 0.--2. "VF_NUMBER,Virtual Function Number. When the Address and BAR matching logic in the controller indicates that a MEM-I/O transaction matches a BAR in the virtual function corresponding to this value then address translation proceeds. This check is only.." "0,1,2,3,4,5,6,7" repeat.end tree.end tree "PF0_PORT_LOGIC (Port Logic)" group.long (0x0+0x700)++0x27 line.long 0x0 "ACK_LATENCY_TIMER_OFF,Ack Latency Timer and Replay Timer Register." hexmask.long.word 0x0 16.--31. 1. "REPLAY_TIME_LIMIT,Replay Timer Limit. The replay timer expires when it reaches this limit. The controller initiates a replay upon reception of a NAK or when the replay timer expires. For more details see 'Transmit Replay'. You can modify the effective.." newline hexmask.long.word 0x0 0.--15. 1. "ROUND_TRIP_LATENCY_TIME_LIMIT,Ack Latency Timer Limit. The Ack latency timer expires when it reaches this limit. For more details see 'Ack Scheduling'. You can modify the effective timer limit with the TIMER_MOD_ACK_NAK field of the.." line.long 0x4 "VENDOR_SPEC_DLLP_OFF,Vendor Specific DLLP Register." hexmask.long 0x4 0.--31. 1. "VENDOR_SPEC_DLLP,Vendor Specific DLLP Register. Used to send a specific PCI Express DLLP. Your application writes the 8-bit DLLP Type and 24-bits of Payload data into this register then sets the field VENDOR_SPECIFIC_DLLP_REQ of PORT_LINK_CTRL_OFF to.." line.long 0x8 "PORT_FORCE_OFF,Port Force Link Register." hexmask.long.byte 0x8 24.--31. 1. "RSVDP_24,Reserved for future use." newline bitfld.long 0x8 23. "DO_DESKEW_FOR_SRIS,Use the transitions from TS2 to Logical Idle Symbol SKP OS to Logical Idle Symbol EIEOS to Logical Idle Symbol and FTS Sequence to SKP OS to do deskew instead of using received SKP OS or TS1 to TS2 transition if DO_DESKEW_FOR_SRIS.." "0,1" newline rbitfld.long 0x8 22. "RSVDP_22,Reserved for future use." "0,1" newline hexmask.long.byte 0x8 16.--21. 1. "LINK_STATE,Forced LTSSM State. The LTSSM state that the controller is forced to when you set the FORCE_EN bit (Force Link). LTSSM state encoding is defined by the lts_state variable in workspace/src/Layer1/smlh_ltssm.v. Note: This register field is sticky." newline bitfld.long 0x8 15. "FORCE_EN,Force Link. The controller supports a testing and debug capability to allow your software to force the LTSSM state machine into a specific state and to force the controller to transmit a specific Link Command. Asserting this bit triggers the.." "0,1" newline rbitfld.long 0x8 12.--14. "RSVDP_12,Reserved for future use." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x8 8.--11. 1. "FORCED_LTSSM,Forced Link Command. The link command that the controller is forced to transmit when you set FORCE_EN bit (Force Link). Link command encoding is defined by the ltssm_cmd variable in workspace/src/Layer1/smlh_ltssm.v. Note: This register.." newline hexmask.long.byte 0x8 0.--7. 1. "LINK_NUM,Link Number. Not used for endpoint. Not used for M-PCIe. Note: This register field is sticky." line.long 0xC "ACK_F_ASPM_CTRL_OFF,Ack Frequency and L0-L1 ASPM Control Register." rbitfld.long 0xC 31. "RSVDP_31,Reserved for future use." "0,1" newline bitfld.long 0xC 30. "ENTER_ASPM,ASPM L1 Entry Control. - 1: Controller enters ASPM L1 after a period in which it has been idle. - 0: Controller enters ASPM L1 only after idle period during which both receive and transmit are in L0s. Note: This register field is sticky." "Controller enters ASPM L1 only after idle period..,Controller enters ASPM L1 after a period in.." newline bitfld.long 0xC 27.--29. "L1_ENTRANCE_LATENCY,L1 Entrance Latency. Value range is: - 000: 1 us - 001: 2 us - 010: 4 us - 011: 8 us - 100: 16 us - 101: 32 us - 110 or 111: 64 us Note: Programming this timer with a value greater that 32us has no effect unless extended sync is used.." "0,1,2,3,4,5,6,7" newline bitfld.long 0xC 24.--26. "L0S_ENTRANCE_LATENCY,L0s Entrance Latency. Values correspond to: - 000: 1 us - 001: 2 us - 010: 3 us - 011: 4 us - 100: 5 us - 101: 6 us - 110 or 111: 7 us This field is applicable to STALL while in L0 for M-PCIe. Note: This register field is sticky." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0xC 16.--23. 1. "COMMON_CLK_N_FTS,Common Clock N_FTS. This is the N_FTS when common clock is used. The number of Fast Training Sequence ordered sets to be transmitted when transitioning from L0s to L0. The maximum number of FTS ordered-sets that a component can request.." newline hexmask.long.byte 0xC 8.--15. 1. "ACK_N_FTS,N_FTS. The number of Fast Training Sequence ordered sets to be transmitted when transitioning from L0s to L0. The maximum number of FTS ordered-sets that a component can request is 255. The controller does not support a value of zero; a value.." newline hexmask.long.byte 0xC 0.--7. 1. "ACK_FREQ,Ack Frequency. The controller accumulates the number of pending ACKs specified here (up to 255) before scheduling an ACK DLLP. - 0: Indicates that this Ack Frequency Counter feature is turned off. The controller generates a low-priority ACK.." line.long 0x10 "PORT_LINK_CTRL_OFF,Port Link Control Register." hexmask.long.byte 0x10 28.--31. 1. "RSVDP_28,Reserved for future use." newline bitfld.long 0x10 27. "TRANSMIT_LANE_REVERSALE_ENABLE,TRANSMIT_LANE_REVERSALE_ENABLE is an internally reserved field. Do not use. Note: This register field is sticky." "0,1" newline bitfld.long 0x10 26. "EXTENDED_SYNCH,EXTENDED_SYNCH is an internally reserved field. Do not use. Note: This register field is sticky." "0,1" newline bitfld.long 0x10 25. "CORRUPT_LCRC_ENABLE,CORRUPT_LCRC_ENABLE is an internally reserved field. Do not use. Note: This register field is sticky." "0,1" newline bitfld.long 0x10 24. "BEACON_ENABLE,BEACON_ENABLE is an internally reserved field. Do not use. Note: This register field is sticky." "0,1" newline hexmask.long.byte 0x10 16.--21. 1. "LINK_CAPABLE,Link Mode Enable. Sets the number of lanes in the link that you want to connect to the link partner. When you have unused lanes in your system then you must change the value in this register to reflect the number of lanes. You must also.." newline hexmask.long.byte 0x10 12.--15. 1. "RSVDP_12,Reserved for future use." newline hexmask.long.byte 0x10 8.--11. 1. "LINK_RATE,LINK_RATE is an internally reserved field. Do not use. Note: This register field is sticky." newline bitfld.long 0x10 7. "FAST_LINK_MODE,Fast Link Mode. Sets all internal LTSSM millisecond timers to Fast Mode for speeding up simulation. Forces the LTSSM training (link initialization) to use shorter time-outs and to link up faster. The default scaling factor can be changed.." "0,1" newline bitfld.long 0x10 6. "LINK_DISABLE,LINK_DISABLE is an internally reserved field. Do not use. Note: This register field is sticky." "0,1" newline bitfld.long 0x10 5. "DLL_LINK_EN,DLL Link Enable. Enables link initialization. When DLL Link Enable =0 the controller does not transmit InitFC DLLPs and does not establish a link. Note: This register field is sticky." "0,1" newline rbitfld.long 0x10 4. "RSVDP_4,Reserved for future use." "0,1" newline bitfld.long 0x10 3. "RESET_ASSERT,Reset Assert. Triggers a recovery and forces the LTSSM to the hot reset state (downstream port only). Note: This register field is sticky." "0,1" newline bitfld.long 0x10 2. "LOOPBACK_ENABLE,Loopback Enable. Turns on loopback. For more details see 'Loopback'. For M-PCIe to force the master to enter Digital Loopback mode you must set this field to '1' during Configuration.start state(initial discovery/configuration). M-PCIe.." "0,1" newline bitfld.long 0x10 1. "SCRAMBLE_DISABLE,Scramble Disable. Turns off data scrambling. Note: This register field is sticky." "0,1" newline bitfld.long 0x10 0. "VENDOR_SPECIFIC_DLLP_REQ,Vendor Specific DLLP Request. When software writes a '1' to this bit the controller transmits the DLLP contained in the VENDOR_SPEC_DLLP field of VENDOR_SPEC_DLLP_OFF. Reading from this self-clearing register field always.." "0,1" line.long 0x14 "LANE_SKEW_OFF,Lane Skew Register." bitfld.long 0x14 31. "DISABLE_LANE_TO_LANE_DESKEW,Disable Lane-to-Lane Deskew. Causes the controller to disable the internal Lane-to-Lane deskew logic. Note: This register field is sticky." "0,1" newline hexmask.long.byte 0x14 27.--30. 1. "IMPLEMENT_NUM_LANES,Implementation-specific Number of Lanes. Set the implementation-specific number of lanes. Allowed values are: - 4'b0000: 1 lane - 4'b0001: 2 lanes - 4'b0011: 4 lanes - 4'b0111: 8 lanes - 4'b1111: 16 lanes The number of lanes to be.." newline bitfld.long 0x14 26. "ELASTIC_BUFFER_MODE,Selects Elasticity Buffer operating mode: 0: Nominal Half Full Buffer mode 1: Nominal Empty Buffer Mode Note: This register field is sticky." "Nominal Half Full Buffer mode,Nominal Empty Buffer Mode" newline bitfld.long 0x14 25. "ACK_NAK_DISABLE,Ack/Nak Disable. Prevents the controller from sending ACK and NAK DLLPs. Note: This register field is sticky." "0,1" newline bitfld.long 0x14 24. "FLOW_CTRL_DISABLE,Flow Control Disable. Prevents the controller from sending FC DLLPs. Note: This register field is sticky." "0,1" newline hexmask.long.tbyte 0x14 0.--23. 1. "INSERT_LANE_SKEW,INSERT_LANE_SKEW is an internally reserved field. Do not use. Note: This register field is sticky." line.long 0x18 "TIMER_CTRL_MAX_FUNC_NUM_OFF,Timer Control and Max Function Number Register." rbitfld.long 0x18 31. "RSVDP_31,Reserved for future use." "0,1" newline bitfld.long 0x18 29.--30. "FAST_LINK_SCALING_FACTOR,Fast Link Timer Scaling Factor. Sets the scaling factor of LTSSM timer when FAST_LINK_MODE field in PORT_LINK_CTRL_OFF is set to '1'. - 0: Scaling Factor is 1024 (1ms is 1us *a) - 1: Scaling Factor is 256 (1ms is 4us) - 2:.." "Scaling Factor is 1024,Scaling Factor is 256,Scaling Factor is 64,Scaling Factor is 16" newline hexmask.long.byte 0x18 24.--28. 1. "UPDATE_FREQ_TIMER,UPDATE_FREQ_TIMER is an internally reserved field. Do not use. Note: This register field is sticky." newline hexmask.long.byte 0x18 19.--23. 1. "TIMER_MOD_ACK_NAK,Ack Latency Timer Modifier. Increases the timer value for the Ack latency timer in increments of 64 clock cycles. A value of '0' represents no modification to the timer value. For more details see the ROUND_TRIP_LATENCY_TIME_LIMIT.." newline hexmask.long.byte 0x18 14.--18. 1. "TIMER_MOD_REPLAY_TIMER,Replay Timer Limit Modifier. Increases the time-out value for the replay timer in increments of 64 clock cycles at Gen1 or Gen2 speed and in increments of 256 clock cycles at Gen3 speed. A value of '0' represents no modification.." newline hexmask.long.byte 0x18 8.--13. 1. "RSVDP_8,Reserved for future use." newline hexmask.long.byte 0x18 0.--7. 1. "MAX_FUNC_NUM,Maximum function number that can be used in a request. Configuration requests targeted at function numbers above this value are returned with UR (unsupported request). Note: This register field is sticky." line.long 0x1C "SYMBOL_TIMER_FILTER_1_OFF,Symbol Timer Register and Filter Mask 1 Register. The Filter Mask 1 Register modifies the RADM filtering and error handling rules. For more details. see the 'Receive Filtering' section. In each case. '0' applies the associated.." hexmask.long.word 0x1C 16.--31. 1. "MASK_RADM_1,Filter Mask 1. The Filter Mask 1 Register modifies the RADM filtering and error handling rules. For more details see the 'Receive Filtering' section. In each case '0' applies the associated filtering rule and '1' masks the associated.." newline bitfld.long 0x1C 15. "DISABLE_FC_WD_TIMER,Disable FC Watchdog Timer. Note: This register field is sticky." "0,1" newline hexmask.long.byte 0x1C 11.--14. 1. "EIDLE_TIMER,EIDLE_TIMER is an internally reserved field. Do not use. Note: This register field is sticky." newline hexmask.long.word 0x1C 0.--10. 1. "SKP_INT_VAL,SKP Interval Value. The number of symbol times to wait between transmitting SKP ordered sets. Note that the controller actually waits the number of symbol times in this register plus 1 between transmitting SKP ordered sets. Your application.." line.long 0x20 "FILTER_MASK_2_OFF,Filter Mask 2 Register. This register modifies the RADM filtering and error handling rules. For more details. see the 'Receive Filtering' section. In each case. '0' applies the associated filtering rule and '1' masks the associated.." hexmask.long 0x20 0.--31. 1. "MASK_RADM_2,Filter Mask 2. This field modifies the RADM filtering and error handling rules. For more details see the 'Receive Filtering' section. In each case '0' applies the associated filtering rule and '1' masks the associated filtering rule." line.long 0x24 "AMBA_MUL_OB_DECOMP_NP_SUB_REQ_CTRL_OFF,AMBA Multiple Outbound Decomposed NP SubRequests Control Register." hexmask.long 0x24 1.--31. 1. "RSVDP_1,Reserved for future use." newline bitfld.long 0x24 0. "OB_RD_SPLIT_BURST_EN,Enable AMBA Multiple Outbound Decomposed NP SubRequests. This bit when set to '0' disables the possibility of having multiple outstanding non-posted requests that were derived from decomposition of an outbound AMBA request. For more.." "0,1" rgroup.long (0x28+0x700)++0x13 line.long 0x0 "PL_DEBUG0_OFF,Debug Register 0" hexmask.long 0x0 0.--31. 1. "DEB_REG_0,The value on cxpl_debug_info[31:0]." line.long 0x4 "PL_DEBUG1_OFF,Debug Register 1" hexmask.long 0x4 0.--31. 1. "DEB_REG_1,The value on cxpl_debug_info[63:32]." line.long 0x8 "TX_P_FC_CREDIT_STATUS_OFF,Transmit Posted FC Credit Status" hexmask.long.word 0x8 20.--31. 1. "RSVDP_TX_P_FC_CREDIT_STATUS,Reserved for future use." newline hexmask.long.byte 0x8 12.--19. 1. "TX_P_HEADER_FC_CREDIT,Transmit Posted Header FC Credits. The posted Header credits advertised by the receiver at the other end of the link updated with each UpdateFC DLLP. Default value depends on the number of advertised credits for header and data.." newline hexmask.long.word 0x8 0.--11. 1. "TX_P_DATA_FC_CREDIT,Transmit Posted Data FC Credits. The posted Data credits advertised by the receiver at the other end of the link updated with each UpdateFC DLLP. Default value depends on the number of advertised credits for header and data Scaled.." line.long 0xC "TX_NP_FC_CREDIT_STATUS_OFF,Transmit Non-Posted FC Credit Status" hexmask.long.word 0xC 20.--31. 1. "RSVDP_TX_NP_FC_CREDIT_STATUS,Reserved for future use." newline hexmask.long.byte 0xC 12.--19. 1. "TX_NP_HEADER_FC_CREDIT,Transmit Non-Posted Header FC Credits. The non-posted Header credits advertised by the receiver at the other end of the link updated with each UpdateFC DLLP. Default value depends on the number of advertised credits for header and.." newline hexmask.long.word 0xC 0.--11. 1. "TX_NP_DATA_FC_CREDIT,Transmit Non-Posted Data FC Credits. The non-posted Data credits advertised by the receiver at the other end of the link updated with each UpdateFC DLLP. Default value depends on the number of advertised credits for header and data.." line.long 0x10 "TX_CPL_FC_CREDIT_STATUS_OFF,Transmit Completion FC Credit Status" hexmask.long.word 0x10 20.--31. 1. "RSVDP_TX_CPL_FC_CREDIT_STATUS,Reserved for future use." newline hexmask.long.byte 0x10 12.--19. 1. "TX_CPL_HEADER_FC_CREDIT,Transmit Completion Header FC Credits. The Completion Header credits advertised by the receiver at the other end of the link updated with each UpdateFC DLLP. Default value depends on the number of advertised credits for header.." newline hexmask.long.word 0x10 0.--11. 1. "TX_CPL_DATA_FC_CREDIT,Transmit Completion Data FC Credits. The Completion Data credits advertised by the receiver at the other end of the link updated with each UpdateFC DLLP. Default value depends on the number of advertised credits for header and data.." group.long (0x3C+0x700)++0x3 line.long 0x0 "QUEUE_STATUS_OFF,Queue Status" bitfld.long 0x0 31. "TIMER_MOD_FLOW_CONTROL_EN,FC Latency Timer Override Enable. When this bit is set the value from the 'FC Latency Timer Override Value' field in this register will override the FC latency timer value that the controller calculates according to the PCIe.." "0,1" newline rbitfld.long 0x0 29.--30. "RSVDP_29,Reserved for future use." "0,1,2,3" newline hexmask.long.word 0x0 16.--28. 1. "TIMER_MOD_FLOW_CONTROL,FC Latency Timer Override Value. When you set the 'FC Latency Timer Override Enable' in this register the value in this field will override the FC latency timer value that the controller calculates according to the PCIe.." newline rbitfld.long 0x0 13. "RX_SERIALIZATION_Q_NON_EMPTY,Receive Serialization Queue Not Empty. Indicates there is data in the serialization queue." "0,1" newline hexmask.long.word 0x0 4.--12. 1. "RSVDP_4,Reserved for future use." newline bitfld.long 0x0 3. "RX_QUEUE_OVERFLOW,Receive Credit Queue Overflow. Indicates insufficient buffer space available to write to the P/NP/CPL credit queue." "0,1" newline rbitfld.long 0x0 2. "RX_QUEUE_NON_EMPTY,Receive Credit Queue Not Empty. Indicates there is data in one or more of the receive buffers." "0,1" newline rbitfld.long 0x0 1. "TX_RETRY_BUFFER_NE,Transmit Retry Buffer Not Empty. Indicates that there is data in the transmit retry buffer." "0,1" newline rbitfld.long 0x0 0. "RX_TLP_FC_CREDIT_NON_RETURN,Received TLP FC Credits Not Returned. Indicates that the controller has received a TLP but has not yet sent an UpdateFC DLLP indicating that the credits for that TLP have been restored by the receiver at the other end of the.." "0,1" rgroup.long (0x40+0x700)++0x7 line.long 0x0 "VC_TX_ARBI_1_OFF,VC Transmit Arbitration Register 1" hexmask.long.byte 0x0 24.--31. 1. "WRR_WEIGHT_VC_3,WRR Weight for VC3. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R" newline hexmask.long.byte 0x0 16.--23. 1. "WRR_WEIGHT_VC_2,WRR Weight for VC2. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R" newline hexmask.long.byte 0x0 8.--15. 1. "WRR_WEIGHT_VC_1,WRR Weight for VC1. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R" newline hexmask.long.byte 0x0 0.--7. 1. "WRR_WEIGHT_VC_0,WRR Weight for VC0. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R" line.long 0x4 "VC_TX_ARBI_2_OFF,VC Transmit Arbitration Register 2" hexmask.long.byte 0x4 24.--31. 1. "WRR_WEIGHT_VC_7,WRR Weight for VC7. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R" newline hexmask.long.byte 0x4 16.--23. 1. "WRR_WEIGHT_VC_6,WRR Weight for VC6. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R" newline hexmask.long.byte 0x4 8.--15. 1. "WRR_WEIGHT_VC_5,WRR Weight for VC5. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R" newline hexmask.long.byte 0x4 0.--7. 1. "WRR_WEIGHT_VC_4,WRR Weight for VC4. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R" group.long (0x48+0x700)++0xB line.long 0x0 "VC0_P_RX_Q_CTRL_OFF,Segmented-Buffer VC0 Posted Receive Queue Control." bitfld.long 0x0 31. "VC_ORDERING_RX_Q,VC Ordering for Receive Queues. Determines the VC ordering rule for the receive queues used only in the segmented-buffer configuration: - 1: Strict ordering higher numbered VCs have higher priority - 0: Round robin Note: This register.." "Round robin,Strict ordering" newline bitfld.long 0x0 30. "TLP_TYPE_ORDERING_VC0,TLP Type Ordering for VC0. Determines the TLP type ordering rule for VC0 receive queues used only in the segmented-buffer configuration: - 1: PCIe ordering rules (recommended) - 0: Strict ordering: posted completion then.." "Strict ordering: posted,PCIe ordering rules" newline bitfld.long 0x0 28.--29. "RESERVED5,Reserved. Note: This register field is sticky." "0,1,2,3" newline bitfld.long 0x0 26.--27. "VC0_P_DATA_SCALE,VC0 Scale Posted Data Credites. Note: This register field is sticky." "0,1,2,3" newline bitfld.long 0x0 24.--25. "VC0_P_HDR_SCALE,VC0 Scale Posted Header Credites. Note: This register field is sticky." "0,1,2,3" newline bitfld.long 0x0 21.--23. "VC0_P_TLP_Q_MODE,Reserved. Note: This register field is sticky." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 20. "RESERVED4,Reserved. Note: This register field is sticky." "0,1" newline hexmask.long.byte 0x0 12.--19. 1. "VC0_P_HEADER_CREDIT,VC0 Posted Header Credits. The number of initial posted header credits for VC0 used only in the segmented-buffer configuration. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R (sticky) Note: This.." newline hexmask.long.word 0x0 0.--11. 1. "VC0_P_DATA_CREDIT,VC0 Posted Data Credits. The number of initial posted data credits for VC0 used only in the segmented-buffer configuration. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R (sticky) Note: This.." line.long 0x4 "VC0_NP_RX_Q_CTRL_OFF,Segmented-Buffer VC0 Non-Posted Receive Queue Control." hexmask.long.byte 0x4 28.--31. 1. "RESERVED7,Reserved. Note: This register field is sticky." newline bitfld.long 0x4 26.--27. "VC0_NP_DATA_SCALE,VC0 Scale Non-Posted Data Credites. Note: This register field is sticky." "0,1,2,3" newline bitfld.long 0x4 24.--25. "VC0_NP_HDR_SCALE,VC0 Scale Non-Posted Header Credites. Note: This register field is sticky." "0,1,2,3" newline bitfld.long 0x4 21.--23. "VC0_NP_TLP_Q_MODE,Reserved. Note: This register field is sticky." "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 20. "RESERVED6,Reserved. Note: This register field is sticky." "0,1" newline hexmask.long.byte 0x4 12.--19. 1. "VC0_NP_HEADER_CREDIT,VC0 Non-Posted Header Credits. The number of initial non-posted header credits for VC0 used only in the segmented-buffer configuration. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R (sticky).." newline hexmask.long.word 0x4 0.--11. 1. "VC0_NP_DATA_CREDIT,VC0 Non-Posted Data Credits. The number of initial non-posted data credits for VC0 used only in the segmented-buffer configuration. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R (sticky) Note:.." line.long 0x8 "VC0_CPL_RX_Q_CTRL_OFF,Segmented-Buffer VC0 Completion Receive Queue Control." hexmask.long.byte 0x8 28.--31. 1. "RESERVED9,Reserved. Note: This register field is sticky." newline bitfld.long 0x8 26.--27. "VC0_CPL_DATA_SCALE,VC0 Scale CPL Data Credites. Note: This register field is sticky." "0,1,2,3" newline bitfld.long 0x8 24.--25. "VC0_CPL_HDR_SCALE,VC0 Scale CPL Header Credites. Note: This register field is sticky." "0,1,2,3" newline bitfld.long 0x8 21.--23. "VC0_CPL_TLP_Q_MODE,Reserved. Note: This register field is sticky." "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 20. "RESERVED8,Reserved. Note: This register field is sticky." "0,1" newline hexmask.long.byte 0x8 12.--19. 1. "VC0_CPL_HEADER_CREDIT,VC0 Completion Header Credits. The number of initial Completion header credits for VC0 used only in the segmented-buffer configuration. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R (sticky).." newline hexmask.long.word 0x8 0.--11. 1. "VC0_CPL_DATA_CREDIT,VC0 Completion Data Credits. The number of initial Completion data credits for VC0 used only in the segmented-buffer configuration. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R (sticky) Note:.." group.long (0x10C+0x700)++0x3 line.long 0x0 "GEN2_CTRL_OFF,This register is used to control various functions of the controller related to link training. lane reversal. and equalization." rbitfld.long 0x0 31. "RSVDP_31,Reserved for future use." "0,1" newline bitfld.long 0x0 30. "FORCE_LANE_FLIP,Enable to force the LANE_UNDER_TEST physical lane flips to logical lane 0. All the other physical lanes are turned off. The LINK_CAPABLE register must be set to 1 and only x1 link can be formed if the FORCE_LANE_FLIP register is set to 1." "0,1" newline hexmask.long.byte 0x0 24.--27. 1. "LANE_UNDER_TEST,The Lane Under Test is the lane for Forced Lane Flip or for Loopback Eq. The value is from 0 to CX_NL. Only one lane is configured each time. The default of this field is the CX_DEFAULT_LANE_UNDER_TEST configuration parameter. This field.." newline rbitfld.long 0x0 22.--23. "RSVDP_22,Reserved for future use." "0,1,2,3" newline bitfld.long 0x0 21. "GEN1_EI_INFERENCE,Electrical Idle Inference Mode at Gen1 Rate. Programmable mode to determine inferred electrical idle (EI) in Recovery.Speed or Loopback.Active (as slave) state at Gen1 speed by looking for a '1' value on RxElecIdle instead of looking.." "Use RxElecIdle signal to infer Electrical Idle,Use RxValid signal to infer Electrical Idle" newline bitfld.long 0x0 20. "SEL_DEEMPHASIS,Used to set the de-emphasis level for upstream ports. This bit selects the level of de-emphasis the link operates at. - 0: -6 dB - 1: -3.5 dB This field is reserved (fixed to '0') for M-PCIe. Note: The access attributes of this field are.." "0,1" newline bitfld.long 0x0 19. "CONFIG_TX_COMP_RX,Config Tx Compliance Receive Bit. When set to 1 signals LTSSM to transmit TS ordered sets with the compliance receive bit assert (equal to '1'). This field is reserved (fixed to '0') for M-PCIe. Note: The access attributes of this.." "0,1" newline bitfld.long 0x0 18. "CONFIG_PHY_TX_CHANGE,Config PHY Tx Swing. Controls the PHY transmitter voltage swing level. The controller drives the mac_phy_txswing output from this register bit field. - 0: Full Swing - 1: Low Swing This field is reserved (fixed to '0') for M-PCIe." "Full Swing,Low Swing" newline bitfld.long 0x0 17. "DIRECT_SPEED_CHANGE,Directed Speed Change. Writing '1' to this field instructs the LTSSM to initiate a speed change to Gen2 or Gen3 after the link is initialized at Gen1 speed. When the speed change occurs the controller will clear the contents of this.." "0,1" newline bitfld.long 0x0 16. "AUTO_LANE_FLIP_CTRL_EN,Enable Auto flipping of the lanes. You must set the CX_AUTO_LANE_FLIP_CTRL_EN configuration parameter to include the hardware for this feature in the controller. For more details see the 'Lane Reversal' appendix in the Databook." "0,1" newline bitfld.long 0x0 13.--15. "PRE_DET_LANE,Predetermined Lane for Auto Flip. This field defines which physical lane is connected to logical Lane0 by the flip operation performed in Detect. This field is used to restrict the receiver detect procedure to a particular lane when the.." "LANE0,LANE1,LANE3,LANE7,LANE15,?,?,?" newline hexmask.long.byte 0x0 8.--12. 1. "NUM_OF_LANES,Predetermined Number of Lanes. Defines the number of lanes which are connected and not bad. Used to limit the effective link width to ignore 'broken' or 'unused' lanes that detect a receiver. Indicates the number of lanes to check for exit.." newline hexmask.long.byte 0x0 0.--7. 1. "FAST_TRAINING_SEQ,Sets the Number of Fast Training Sequences (N_FTS) that the controller advertises as its N_FTS during Gen2 or Gen3 link training. This value is used to inform the link partner about the PHY's ability to recover synchronization after a.." rgroup.long (0x110+0x700)++0x3 line.long 0x0 "PHY_STATUS_OFF,PHY Status Register. Memory mapped register from phy_cfg_status GPIO input pins." hexmask.long 0x0 0.--31. 1. "PHY_STATUS,PHY Status. Data received directly from the phy_cfg_status bus. These is a GPIO register reflecting the values on the static phy_cfg_status input signals. The usage is left completely to the user and does not in any way influence controller.." group.long (0x114+0x700)++0x3 line.long 0x0 "PHY_CONTROL_OFF,PHY Control Register. Memory mapped register to cfg_phy_control GPIO output pins." hexmask.long 0x0 0.--31. 1. "PHY_CONTROL,PHY Control. Data sent directly to the cfg_phy_control bus. These is a GPIO register driving the values on the static cfg_phy_control output signals. The usage is left completely to the user and does not in any way influence controller.." group.long (0x11C+0x700)++0x77 line.long 0x0 "TRGT_MAP_CTRL_OFF,Programmable Target Map Control Register." hexmask.long.word 0x0 21.--31. 1. "TARGET_MAP_RESERVED_21_31,Reserved. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R (sticky)" newline hexmask.long.byte 0x0 16.--20. 1. "TARGET_MAP_INDEX,The number of the PF Function on which the Target Values are set. This register does not respect the Byte Enable setting. any write will affect all register bits." newline rbitfld.long 0x0 13.--15. "TARGET_MAP_RESERVED_13_15,Reserved. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R (sticky)" "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x0 7.--12. 1. "TARGET_MAP_VF,Target Values for each BAR on the VF Function selected by the index number. This register does not respect the Byte Enable setting. any write will affect all register bits." newline bitfld.long 0x0 6. "TARGET_MAP_ROM,Target Value for the ROM page of the PF Function selected by the index number. This register does not respect the Byte Enable setting. any write will affect all register bits." "0,1" newline hexmask.long.byte 0x0 0.--5. 1. "TARGET_MAP_PF,Target Values for each BAR on the PF Function selected by the index number. This register does not respect the Byte Enable setting. any write will affect all register bits." line.long 0x4 "MSI_CTRL_ADDR_OFF,Integrated MSI Reception Module (iMRM) Address Register." hexmask.long 0x4 0.--31. 1. "MSI_CTRL_ADDR,Integrated MSI Reception Module Address. System specified address for MSI memory write transaction termination. Within the AXI Bridge every received Memory Write request is examined to see if it targets the MSI Address that has been.." line.long 0x8 "MSI_CTRL_UPPER_ADDR_OFF,Integrated MSI Reception Module Upper Address Register." hexmask.long 0x8 0.--31. 1. "MSI_CTRL_UPPER_ADDR,Integrated MSI Reception Module Upper Address. System specified upper address for MSI memory write transaction termination. Allows functions to support a 64-bit MSI address. Note: This register field is sticky." line.long 0xC "MSI_CTRL_INT_0_EN_OFF,Integrated MSI Reception Module Interrupt#i Enable Register." hexmask.long 0xC 0.--31. 1. "MSI_CTRL_INT_0_EN,MSI Interrupt#i Enable. Specifies which interrupts are enabled. When an MSI is received from a disabled interrupt no status bit gets set in MSI controller interrupt status register. Each bit corresponds to a single MSI Interrupt.." line.long 0x10 "MSI_CTRL_INT_0_MASK_OFF,Integrated MSI Reception Module Interrupt#i Mask Register." hexmask.long 0x10 0.--31. 1. "MSI_CTRL_INT_0_MASK,MSI Interrupt#i Mask. Allows enabled interrupts to be masked. When an MSI is received for a masked interrupt the corresponding status bit gets set in the interrupt status register but the msi_ctrl_int output is not set HIGH. Each bit.." line.long 0x14 "MSI_CTRL_INT_0_STATUS_OFF,Integrated MSI Reception Module Interrupt#i Status Register." hexmask.long 0x14 0.--31. 1. "MSI_CTRL_INT_0_STATUS,MSI Interrupt#i Status. When an MSI is detected for EP#i one bit in this register is set. The decoding of the data payload of the MSI Memory Write request determines which bit gets set. A status is bit is cleared by writing a 1 to.." line.long 0x18 "MSI_CTRL_INT_1_EN_OFF,Integrated MSI Reception Module Interrupt#i Enable Register." hexmask.long 0x18 0.--31. 1. "MSI_CTRL_INT_1_EN,MSI Interrupt#i Enable. Specifies which interrupts are enabled. When an MSI is received from a disabled interrupt no status bit gets set in MSI controller interrupt status register. Each bit corresponds to a single MSI Interrupt.." line.long 0x1C "MSI_CTRL_INT_1_MASK_OFF,Integrated MSI Reception Module Interrupt#i Mask Register." hexmask.long 0x1C 0.--31. 1. "MSI_CTRL_INT_1_MASK,MSI Interrupt#i Mask. Allows enabled interrupts to be masked. When an MSI is received for a masked interrupt the corresponding status bit gets set in the interrupt status register but the msi_ctrl_int output is not set HIGH. Each bit.." line.long 0x20 "MSI_CTRL_INT_1_STATUS_OFF,Integrated MSI Reception Module Interrupt#i Status Register." hexmask.long 0x20 0.--31. 1. "MSI_CTRL_INT_1_STATUS,MSI Interrupt#i Status. When an MSI is detected for EP#i one bit in this register is set. The decoding of the data payload of the MSI Memory Write request determines which bit gets set. A status is bit is cleared by writing a 1 to.." line.long 0x24 "MSI_CTRL_INT_2_EN_OFF,Integrated MSI Reception Module Interrupt#i Enable Register." hexmask.long 0x24 0.--31. 1. "MSI_CTRL_INT_2_EN,MSI Interrupt#i Enable. Specifies which interrupts are enabled. When an MSI is received from a disabled interrupt no status bit gets set in MSI controller interrupt status register. Each bit corresponds to a single MSI Interrupt.." line.long 0x28 "MSI_CTRL_INT_2_MASK_OFF,Integrated MSI Reception Module Interrupt#i Mask Register." hexmask.long 0x28 0.--31. 1. "MSI_CTRL_INT_2_MASK,MSI Interrupt#i Mask. Allows enabled interrupts to be masked. When an MSI is received for a masked interrupt the corresponding status bit gets set in the interrupt status register but the msi_ctrl_int output is not set HIGH. Each bit.." line.long 0x2C "MSI_CTRL_INT_2_STATUS_OFF,Integrated MSI Reception Module Interrupt#i Status Register." hexmask.long 0x2C 0.--31. 1. "MSI_CTRL_INT_2_STATUS,MSI Interrupt#i Status. When an MSI is detected for EP#i one bit in this register is set. The decoding of the data payload of the MSI Memory Write request determines which bit gets set. A status is bit is cleared by writing a 1 to.." line.long 0x30 "MSI_CTRL_INT_3_EN_OFF,Integrated MSI Reception Module Interrupt#i Enable Register." hexmask.long 0x30 0.--31. 1. "MSI_CTRL_INT_3_EN,MSI Interrupt#i Enable. Specifies which interrupts are enabled. When an MSI is received from a disabled interrupt no status bit gets set in MSI controller interrupt status register. Each bit corresponds to a single MSI Interrupt.." line.long 0x34 "MSI_CTRL_INT_3_MASK_OFF,Integrated MSI Reception Module Interrupt#i Mask Register." hexmask.long 0x34 0.--31. 1. "MSI_CTRL_INT_3_MASK,MSI Interrupt#i Mask. Allows enabled interrupts to be masked. When an MSI is received for a masked interrupt the corresponding status bit gets set in the interrupt status register but the msi_ctrl_int output is not set HIGH. Each bit.." line.long 0x38 "MSI_CTRL_INT_3_STATUS_OFF,Integrated MSI Reception Module Interrupt#i Status Register." hexmask.long 0x38 0.--31. 1. "MSI_CTRL_INT_3_STATUS,MSI Interrupt#i Status. When an MSI is detected for EP#i one bit in this register is set. The decoding of the data payload of the MSI Memory Write request determines which bit gets set. A status is bit is cleared by writing a 1 to.." line.long 0x3C "MSI_CTRL_INT_4_EN_OFF,Integrated MSI Reception Module Interrupt#i Enable Register." hexmask.long 0x3C 0.--31. 1. "MSI_CTRL_INT_4_EN,MSI Interrupt#i Enable. Specifies which interrupts are enabled. When an MSI is received from a disabled interrupt no status bit gets set in MSI controller interrupt status register. Each bit corresponds to a single MSI Interrupt.." line.long 0x40 "MSI_CTRL_INT_4_MASK_OFF,Integrated MSI Reception Module Interrupt#i Mask Register." hexmask.long 0x40 0.--31. 1. "MSI_CTRL_INT_4_MASK,MSI Interrupt#i Mask. Allows enabled interrupts to be masked. When an MSI is received for a masked interrupt the corresponding status bit gets set in the interrupt status register but the msi_ctrl_int output is not set HIGH. Each bit.." line.long 0x44 "MSI_CTRL_INT_4_STATUS_OFF,Integrated MSI Reception Module Interrupt#i Status Register." hexmask.long 0x44 0.--31. 1. "MSI_CTRL_INT_4_STATUS,MSI Interrupt#i Status. When an MSI is detected for EP#i one bit in this register is set. The decoding of the data payload of the MSI Memory Write request determines which bit gets set. A status is bit is cleared by writing a 1 to.." line.long 0x48 "MSI_CTRL_INT_5_EN_OFF,Integrated MSI Reception Module Interrupt#i Enable Register." hexmask.long 0x48 0.--31. 1. "MSI_CTRL_INT_5_EN,MSI Interrupt#i Enable. Specifies which interrupts are enabled. When an MSI is received from a disabled interrupt no status bit gets set in MSI controller interrupt status register. Each bit corresponds to a single MSI Interrupt.." line.long 0x4C "MSI_CTRL_INT_5_MASK_OFF,Integrated MSI Reception Module Interrupt#i Mask Register." hexmask.long 0x4C 0.--31. 1. "MSI_CTRL_INT_5_MASK,MSI Interrupt#i Mask. Allows enabled interrupts to be masked. When an MSI is received for a masked interrupt the corresponding status bit gets set in the interrupt status register but the msi_ctrl_int output is not set HIGH. Each bit.." line.long 0x50 "MSI_CTRL_INT_5_STATUS_OFF,Integrated MSI Reception Module Interrupt#i Status Register." hexmask.long 0x50 0.--31. 1. "MSI_CTRL_INT_5_STATUS,MSI Interrupt#i Status. When an MSI is detected for EP#i one bit in this register is set. The decoding of the data payload of the MSI Memory Write request determines which bit gets set. A status is bit is cleared by writing a 1 to.." line.long 0x54 "MSI_CTRL_INT_6_EN_OFF,Integrated MSI Reception Module Interrupt#i Enable Register." hexmask.long 0x54 0.--31. 1. "MSI_CTRL_INT_6_EN,MSI Interrupt#i Enable. Specifies which interrupts are enabled. When an MSI is received from a disabled interrupt no status bit gets set in MSI controller interrupt status register. Each bit corresponds to a single MSI Interrupt.." line.long 0x58 "MSI_CTRL_INT_6_MASK_OFF,Integrated MSI Reception Module Interrupt#i Mask Register." hexmask.long 0x58 0.--31. 1. "MSI_CTRL_INT_6_MASK,MSI Interrupt#i Mask. Allows enabled interrupts to be masked. When an MSI is received for a masked interrupt the corresponding status bit gets set in the interrupt status register but the msi_ctrl_int output is not set HIGH. Each bit.." line.long 0x5C "MSI_CTRL_INT_6_STATUS_OFF,Integrated MSI Reception Module Interrupt#i Status Register." hexmask.long 0x5C 0.--31. 1. "MSI_CTRL_INT_6_STATUS,MSI Interrupt#i Status. When an MSI is detected for EP#i one bit in this register is set. The decoding of the data payload of the MSI Memory Write request determines which bit gets set. A status is bit is cleared by writing a 1 to.." line.long 0x60 "MSI_CTRL_INT_7_EN_OFF,Integrated MSI Reception Module Interrupt#i Enable Register." hexmask.long 0x60 0.--31. 1. "MSI_CTRL_INT_7_EN,MSI Interrupt#i Enable. Specifies which interrupts are enabled. When an MSI is received from a disabled interrupt no status bit gets set in MSI controller interrupt status register. Each bit corresponds to a single MSI Interrupt.." line.long 0x64 "MSI_CTRL_INT_7_MASK_OFF,Integrated MSI Reception Module Interrupt#i Mask Register." hexmask.long 0x64 0.--31. 1. "MSI_CTRL_INT_7_MASK,MSI Interrupt#i Mask. Allows enabled interrupts to be masked. When an MSI is received for a masked interrupt the corresponding status bit gets set in the interrupt status register but the msi_ctrl_int output is not set HIGH. Each bit.." line.long 0x68 "MSI_CTRL_INT_7_STATUS_OFF,Integrated MSI Reception Module Interrupt#i Status Register." hexmask.long 0x68 0.--31. 1. "MSI_CTRL_INT_7_STATUS,MSI Interrupt#i Status. When an MSI is detected for EP#i one bit in this register is set. The decoding of the data payload of the MSI Memory Write request determines which bit gets set. A status is bit is cleared by writing a 1 to.." line.long 0x6C "MSI_GPIO_IO_OFF,Integrated MSI Reception Module General Purpose IO Register." hexmask.long 0x6C 0.--31. 1. "MSI_GPIO_REG,MSI GPIO Register. The contents of this register drives the top-level GPIO msi_ctrl_io[31:0] Note: This register field is sticky." line.long 0x70 "CLOCK_GATING_CTRL_OFF,This register enables you to disable dynamic clock gating. By default dynamic clock gating is on. allowing the controller to autonomously enable and disable its clocks. The clock gating is performed in the clock and reset module." hexmask.long 0x70 2.--31. 1. "RSVDP_2,Reserved for future use." newline bitfld.long 0x70 1. "AXI_CLK_GATING_EN,AXI Clock Gating Enable. This register enables the AXI Bridge to autonomously enable and disable the AXI Master clock the AXI Slave clock and the AXI DBI slave clock. The DWC_pcie_clk_rst.v module provides the gated clock.." "Disable,Enable" newline bitfld.long 0x70 0. "RADM_CLK_GATING_EN,RADM Clock Gating Enable. This register if set enables the RADM to autonomously enable and disable its clock. The DWC_pcie_clk_rst.v module provides the gated clock radm_clk_g to the RADM and is enabled when the controllers clock.." "Disable,Enable" line.long 0x74 "GEN3_RELATED_OFF,Gen3 Control Register. There is no Gen3-specific N_FTS field. The N_FTS field in the 'Link Width and Speed Change Control Register' is used for both Gen2 and Gen3 speed modes. There is no Gen3-specific 'Directed Speed Change' field. The.." hexmask.long.byte 0x74 26.--31. 1. "RSVDP_26,Reserved for future use." newline bitfld.long 0x74 23. "GEN3_EQ_INVREQ_EVAL_DIFF_DISABLE,Eq InvalidRequest and RxEqEval Different Time Assertion Disable. Disable the assertion of Eq InvalidRequest and RxEqEval at different time. Note: When CX_GEN4_SPEED/CX_GEN5_SPEED this register is shared for Gen3 and.." "0,1" newline rbitfld.long 0x74 19.--20. "RSVDP_19,Reserved for future use." "0,1,2,3" newline bitfld.long 0x74 18. "GEN3_DC_BALANCE_DISABLE,DC Balance Disable. Disable DC Balance feature. Note: When CX_GEN4_SPEED/CX_GEN5_SPEED this register is shared for Gen3 and Gen4/Gen5 data rate. Note: This register field is sticky." "0,1" newline bitfld.long 0x74 17. "GEN3_DLLP_XMT_DELAY_DISABLE,DLLP Transmission Delay Disable. Disable delay transmission of DLLPs before equalization. Note: When CX_GEN4_SPEED/CX_GEN5_SPEED this register is shared for Gen3 and Gen4/Gen5 data rate. Note: This register field is sticky." "0,1" newline bitfld.long 0x74 16. "GEN3_EQUALIZATION_DISABLE,Equalization Disable. Disable equalization feature. This bit cannot be changed once the LTSSM starts link training. Note: When CX_GEN4_SPEED/CX_GEN5_SPEED this register is shared for Gen3 and Gen4/Gen5 data rate. Note: This.." "0,1" newline rbitfld.long 0x74 14.--15. "RSVDP_14,Reserved for future use." "0,1,2,3" newline bitfld.long 0x74 13. "RXEQ_RGRDLESS_RXTS,When set to '1' the controller as Gen3 EQ master asserts RxEqEval to instruct the PHY to do Rx adaptation and evaluation after a 500ns timeout from a new preset request. - 0: mac_phy_rxeqeval asserts after 1us and 2 TS1 received from.." "mac_phy_rxeqeval asserts after 1us and 2 TS1..,mac_phy_rxeqeval asserts after 500ns regardless.." newline bitfld.long 0x74 12. "RXEQ_PH01_EN,Rx Equalization Phase 0/Phase 1 Hold Enable. When this bit is set the upstream port holds phase 0 (the downstream port holds phase 1) for 10ms. Holding phase 0 or phase 1 can be used to allow sufficient time for Rx Equalization to be.." "Tx equalization only in phase 2/3,No Tx equalization" newline bitfld.long 0x74 11. "EQ_REDO,Equalization Redo Disable. Disable autonomous mechanism for requesting to redo the equalization process. The received presets or coefficients mismatch in Recovery.RcvrLock after Recovery EQ phases causes the EQ redo requests. If the EQ redo is.." "0,1" newline bitfld.long 0x74 10. "EQ_EIEOS_CNT,Equalization EIEOS Count Reset Disable. Disable requesting reset of EIEOS count during equalization. Note: When CX_GEN4_SPEED/CX_GEN5_SPEED this register is shared for Gen3 and Gen4/Gen5 data rate. Note: This register field is sticky." "0,1" newline bitfld.long 0x74 9. "EQ_PHASE_2_3,Equalization Phase 2 and Phase 3 Disable. This applies to downstream ports only. Note: When CX_GEN4_SPEED/CX_GEN5_SPEED this register is shadow register for Gen3 and Gen4/Gen5 data rate. If RATE_SHADOW_SEL==00b this register is for Gen3.." "0,1" newline bitfld.long 0x74 8. "DISABLE_SCRAMBLER_GEN_3,Disable Scrambler for Gen3 and Gen4 Data Rate. The Gen3 and Gen4 scrambler/descrambler within the controller needs to be disabled when the scrambling function is implemented outside of the controller (for example within the PHY)." "0,1" newline hexmask.long.byte 0x74 1.--7. 1. "RSVDP_1,Reserved for future use." newline bitfld.long 0x74 0. "GEN3_ZRXDC_NONCOMPL,Gen3 Receiver Impedance ZRX-DC Not Compliant. Receivers that operate at 8.0 GT/s with an impedance other than the range defined by the ZRX-DC parameter for 2.5 GT/s (40-60 Ohms) must meet additional behavior requirements in the.." "The receiver complies with the ZRX-DC parameter..,The receiver does not comply with the ZRX-DC.." group.long (0x1A8+0x700)++0x7 line.long 0x0 "GEN3_EQ_CONTROL_OFF,Gen3 EQ Control Register. This register controls equalization for Phase2 in an upstream port (USP). or Phase3 in a downstream port (DSP). M-PCIe doesn't have Conventional PCIe Gen3 feature. The registers of this section do not exist." hexmask.long.byte 0x0 27.--31. 1. "RSVDP_27,Reserved for future use." newline bitfld.long 0x0 26. "GEN3_REQ_SEND_CONSEC_EIEOS_FOR_PSET_MAP,Request controller to send back-to-back EIEOS in Recovery.RcvrLock state until presets to coefficients mapping is complete. - 0: Do not request - 1: request Note: Gen3 and Gen4 share the same register bit and have.." "Do not request,request" newline bitfld.long 0x0 25. "GEN3_EQ_PSET_REQ_AS_COEF,GEN3_EQ_PSET_REQ_AS_COEF is an internally reserved field. Do not use. Note: This register field is sticky." "0,1" newline bitfld.long 0x0 24. "GEN3_EQ_FOM_INC_INITIAL_EVAL,Include Initial FOM. Include or not the FOM feedback from the initial preset evaluation performed in the EQ Master when finding the highest FOM among all preset evaluations. - 0: Do not include - 1: Include Note: When.." "Do not include,Include" newline hexmask.long.word 0x0 8.--23. 1. "GEN3_EQ_PSET_REQ_VEC,Preset Request Vector. Requesting of Presets during the initial part of the EQ Master Phase. Encoding scheme is as follows: Bit [15:0] =0x0: No preset is requested and evaluated in EQ Master Phase. Bit [i] =1: 'Preset=i' is requested.." newline rbitfld.long 0x0 7. "RSVDP_7,Reserved for future use." "0,1" newline bitfld.long 0x0 6. "GEN3_LOWER_RATE_EQ_REDO_ENABLE,Support EQ redo and lower rate change: - 0: not support - 1: support Note: Gen3 and Gen4 share the same register bit and have the same feature. Note: This register field is sticky." "not support,support" newline bitfld.long 0x0 5. "GEN3_EQ_EVAL_2MS_DISABLE,Phase2_3 2 ms Timeout Disable. Determine behavior in Phase2 for USP (Phase3 if DSP) when the PHY does not respond within 2ms to the assertion of RxEqEval: - 0: abort the current evaluation stop any attempt to modify the remote.." "abort the current evaluation,ignore the 2ms timeout and continue as normal" newline bitfld.long 0x0 4. "GEN3_EQ_PHASE23_EXIT_MODE,Behavior After 24 ms Timeout (when optimal settings are not found). For a USP: Determine next LTSSM state from Phase2 after 24ms Timeout - 0: Recovery.Speed - 1: Recovery.Equalization.Phase3 When optimal settings are not found.." "Equalization Phase 3 Successful status bit is..,Recovery" newline hexmask.long.byte 0x0 0.--3. 1. "GEN3_EQ_FB_MODE,Feedback Mode. - 0000b: Direction Change - 0001b: Figure Of Merit - 0010b: Reserved - .....: Reserved - 1111b: Reserved Note: When CX_GEN4_SPEED/CX_GEN5_SPEED this register is a shadow register for Gen3 and Gen4/Gen5 data rate. If.." line.long 0x4 "GEN3_EQ_FB_MODE_DIR_CHANGE_OFF,Gen3 EQ Direction Change Feedback Mode Control Register. Equalization controls to be used in Phase2 (USP) or Phase 3 (DSP). when you set the Feedback Mode in 'Gen3 EQ Control Register' to 'Direction Change.' These fields.." hexmask.long.word 0x4 18.--31. 1. "RSVDP_18,Reserved for future use." newline hexmask.long.byte 0x4 14.--17. 1. "GEN3_EQ_FMDC_MAX_POST_CUSROR_DELTA,Convergence Window Aperture for C+1. Post-cursor coefficients maximum delta within the convergence window depth. Allowed range: 0 1 2 ..15. Note: When CX_GEN4_SPEED/CX_GEN5_SPEED this register is shadow register for.." newline hexmask.long.byte 0x4 10.--13. 1. "GEN3_EQ_FMDC_MAX_PRE_CUSROR_DELTA,Convergence Window Aperture for C-1. Pre-cursor coefficients maximum delta within the convergence window depth. Allowed range: 0 1 2 ..15. Note: When CX_GEN4_SPEED/CX_GEN5_SPEED this register is shadow register for Gen3.." newline hexmask.long.byte 0x4 5.--9. 1. "GEN3_EQ_FMDC_N_EVALS,Convergence Window Depth. Number of consecutive evaluations considered in Phase 2/3 when determining if optimal coefficients have been found. Allowed range: 0 1 2 ..16 up to a maximum of CX_GEN3_EQ_COEFQ_DEPTH. When set to 0 EQ.." newline hexmask.long.byte 0x4 0.--4. 1. "GEN3_EQ_FMDC_T_MIN_PHASE23,Minimum Time (in ms) To Remain in EQ Master Phase. The LTSSM stays in EQ Master phase for at least this amount of time before starting to check for convergence of the coefficients. Allowed values 0 1 ... 24. Note: When.." group.long (0x1B4+0x700)++0x27 line.long 0x0 "ORDER_RULE_CTRL_OFF,Order Rule Control Register." hexmask.long.word 0x0 16.--31. 1. "RSVDP_16,Reserved for future use." newline hexmask.long.byte 0x0 8.--15. 1. "CPL_PASS_P,Completion Passing Posted Ordering Rule Control. Determines if CPL can pass halted P queue. - 0: CPL can not pass P (recommended) - 1: CPL can pass P" newline hexmask.long.byte 0x0 0.--7. 1. "NP_PASS_P,Non-Posted Passing Posted Ordering Rule Control. Determines if NP can pass halted P queue. - 0 : NP can not pass P (recommended). - 1 : NP can pass P" line.long 0x4 "PIPE_LOOPBACK_CONTROL_OFF,PIPE Loopback Control Register." bitfld.long 0x4 31. "PIPE_LOOPBACK,PIPE Loopback Enable. Indicates RMMI Loopback if M-PCIe. Note: This register field is sticky." "0,1" newline hexmask.long.byte 0x4 27.--30. 1. "RSVDP_27,Reserved for future use." newline bitfld.long 0x4 24.--26. "RXSTATUS_VALUE,RXSTATUS_VALUE is an internally reserved field. Do not use." "0,1,2,3,4,5,6,7" newline rbitfld.long 0x4 22.--23. "RSVDP_22,Reserved for future use." "0,1,2,3" newline hexmask.long.byte 0x4 16.--21. 1. "RXSTATUS_LANE,RXSTATUS_LANE is an internally reserved field. Do not use. Note: This register field is sticky." newline hexmask.long.word 0x4 0.--15. 1. "LPBK_RXVALID,LPBK_RXVALID is an internally reserved field. Do not use. Note: This register field is sticky." line.long 0x8 "MISC_CONTROL_1_OFF,DBI Read-Only Write Enable Register." hexmask.long.word 0x8 22.--31. 1. "RSVDP_22,Reserved for future use." newline bitfld.long 0x8 21. "P2P_ERR_RPT_CTRL,Determines whether to track completion of transmitted Non-Posted TLPs in P2P mode. - 0: Do not track completion - 1: Track completion Note: This register field is sticky." "Do not track completion,Track completion" newline bitfld.long 0x8 20. "P2P_TRACK_CPL_TO_REG,Determines whether to enable Peer to Peer (P2P) error reporting. - 0: Disable P2P error reporting - 1: Enable P2P error reporting Note: This register field is sticky." "Disable P2P error reporting,Enable P2P error reporting" newline bitfld.long 0x8 18.--19. "TARGET_ABOVE_CONFIG_LIMIT_REG,Configuration requests with an address greater than CONFIG_LIMIT_REG are directed to either ELBI or TRGT1 interface based on the setting of this field. This field can have the following values: - 1: ELBI - 2: TRGT1 Note:.." "?,ELBI,TRGT1,?" newline hexmask.long.word 0x8 8.--17. 1. "CONFIG_LIMIT_REG,Configuration requests are directed either to CDM or ELBI/RTRGT1 based on the value of this field. - Configuration requests with an address less CONFIG_LIMIT_REG are directed to the CDM - Configuration requests with an address greater.." newline bitfld.long 0x8 7. "CFG_TLP_BYPASS_EN_REG,Setting of this field defines which field TARGET_ABOVE_CONFIG_LIMIT_REG or CONFIG_LIMIT_REG decides the destination of Configuration requests. This field can have the following values: - 0: Configuration TLPs are routed according to.." "Configuration TLPs are routed according to the..,Configuration TLPs are routed according to the.." newline bitfld.long 0x8 6. "CPLQ_MNG_EN,This field enables the Completion Queue Management feature. Note: This register field is sticky." "0,1" newline bitfld.long 0x8 5. "ARI_DEVICE_NUMBER,When ARI is enabled this field enables use of the device ID. Note: This register field is sticky." "0,1" newline bitfld.long 0x8 4. "DISABLE_AUTO_LTR_CLR_MSG,Disable the autonomous generation of LTR clear message in upstream port. This field can have the following values: - 0: Allow the autonomous generation of LTR clear message. - 1: Disable the autonomous generation of LTR clear.." "Allow the autonomous generation of LTR clear..,Disable the autonomous generation of LTR clear.." newline bitfld.long 0x8 3. "SIMPLIFIED_REPLAY_TIMER,Enables Simplified Replay Timer (Gen4). For more details see 'Transmit Replay' in 'Transmit TLP Processing' section in the 'Controller Operations' chapter of the Databook. Simplified Replay Timer can have the following Values: -.." "0,1" newline bitfld.long 0x8 2. "UR_CA_MASK_4_TRGT1,When this field is set to '1' the controller suppresses error logging error message generation and CPL generation for non-posted requests TLPs (with UR filtering status) forwarded to your application (that is when DEFAULT_TARGET.." "0,1" newline bitfld.long 0x8 1. "DEFAULT_TARGET,Default target for an IO or MEM request with UR/CA/CRS received. Based on the value of this field the controller either drops or forwards these requests to your application. - 0: The controller drops all incoming I/O or MEM requests (after.." "The controller drops all incoming I/O or MEM..,The controller forwards all incoming I/O or MEM.." newline bitfld.long 0x8 0. "DBI_RO_WR_EN,Write to RO Registers Using DBI. Your application can write to some RO and HwInit register fields through the DBI when you set this field to '1'. For more details see 'Writing to Read-Only Registers' in 'Register Module LBC and DBI'.." "0,1" line.long 0xC "MULTI_LANE_CONTROL_OFF,UpConfigure Multi-lane Control Register. Used when upsizing or downsizing the link width through Configuration state without bringing the link down. For more details. see the 'Link Establishment' section in the 'Controller.." hexmask.long.tbyte 0xC 8.--31. 1. "RSVDP_8,Reserved for future use." newline bitfld.long 0xC 7. "UPCONFIGURE_SUPPORT,Upconfigure Support. The controller sends this value as the Link Upconfigure Capability in TS2 Ordered Sets in Configuration.Complete state. This field is reserved (fixed to '0') for M-PCIe. Note: This register field is sticky." "0,1" newline bitfld.long 0xC 6. "DIRECT_LINK_WIDTH_CHANGE,Directed Link Width Change. The controller always moves to Configuration state through Recovery state when this bit is set to '1'. - If the upconfigure_capable variable is '1' and the PCIE_CAP_HW_AUTO_WIDTH_DISABLE bit in.." "0,1" newline hexmask.long.byte 0xC 0.--5. 1. "TARGET_LINK_WIDTH,Target Link Width. Values correspond to: - 6'b000000: Controller does not start upconfigure or autonomous width downsizing in the Configuration state. - 6'b000001: x1 - 6'b000010: x2 - 6'b000100: x4 - 6'b001000: x8 - 6'b010000: x16 -.." line.long 0x10 "PHY_INTEROP_CTRL_OFF,PHY Interoperability Control Register." hexmask.long.tbyte 0x10 12.--31. 1. "RSVDP_12,Reserved for future use." newline bitfld.long 0x10 10. "L1_CLK_SEL,L1 Clock control bit. This field is reserved for internal use. You should not write to this field and change the default unless specifically instructed by Synopsys support. - 1: Controller does not request aux_clk switch and core_clk gating in.." "Controller requests aux_clk switch and core_clk..,Controller does not request aux_clk switch and.." newline rbitfld.long 0x10 9. "L1_NOWAIT_P1,L1 entry control bit. This field is reserved for internal use. You should not write to this field and change the default unless specifically instructed by Synopsys support. - 1: Controller does not wait for PHY to acknowledge transition to.." "Controller waits for the PHY to acknowledge..,Controller does not wait for PHY to acknowledge.." newline bitfld.long 0x10 8. "L1SUB_EXIT_MODE,L1 Exit Control Using phy_mac_pclkack_n. This field is reserved for internal use. You should not write to this field and change the default unless specifically instructed by Synopsys support. - 1: Controller exits L1 without waiting for.." "Controller waits for the PHY to assert..,Controller exits L1 without waiting for the PHY.." newline rbitfld.long 0x10 7. "RSVDP_7,Reserved for future use." "0,1" newline hexmask.long.byte 0x10 0.--6. 1. "RXSTANDBY_CONTROL,Rxstandby Control. Bits 0..5 determine if the controller asserts the RxStandby signal (mac_phy_rxstandby) in the indicated condition. Bit 6 enables the controller to perform the RxStandby/RxStandbyStatus handshake. This field is.." line.long 0x14 "TRGT_CPL_LUT_DELETE_ENTRY_OFF,TRGT_CPL_LUT Delete Entry Control register. Using this register you can delete one entry in the target completion LUT. You should only use this register when you know that your application will never send the completion.." bitfld.long 0x14 31. "DELETE_EN,This is a one-shot bit. A '1' write to this bit triggers the deletion of the target completion LUT entry that is specified in the LOOK_UP_ID field. This is a self-clearing register field. Reading from this register field always returns a '0'." "0,1" newline hexmask.long 0x14 0.--30. 1. "LOOK_UP_ID,This number selects one entry to delete of the TRGT_CPL_LUT." line.long 0x18 "LINK_FLUSH_CONTROL_OFF,Link Reset Request Flush Control Register." hexmask.long.byte 0x18 24.--31. 1. "RSVD_I_8,This is an internally reserved field. Do not use. Note: This register field is sticky." newline hexmask.long.tbyte 0x18 1.--23. 1. "RSVDP_1,Reserved for future use." newline bitfld.long 0x18 0. "AUTO_FLUSH_EN,Enables automatic flushing of pending requests before sending the reset request to the application logic to reset the PCIe controller and the AXI Bridge. The flushing process is initiated if any of the following events occur: - Hot reset.." "0,1" line.long 0x1C "AMBA_ERROR_RESPONSE_DEFAULT_OFF,AXI Bridge Slave Error Response Register." hexmask.long.word 0x1C 16.--31. 1. "RSVDP_16,Reserved for future use." newline hexmask.long.byte 0x1C 10.--15. 1. "AMBA_ERROR_RESPONSE_MAP,AXI Slave Response Error Map. Allows you to selectively map the errors received from the PCIe completion (for non-posted requests) to the AXI slave responses slv_rresp or slv_bresp. The recommended setting is SLVERR. CRS is.." newline hexmask.long.byte 0x1C 5.--9. 1. "RSVDP_5,Reserved for future use." newline bitfld.long 0x1C 3.--4. "AMBA_ERROR_RESPONSE_CRS,CRS Slave Error Response Mapping. Determines the AXI slave response for CRS completions. For more details see 'Error Handling' in the AXI chapter of the Databook. AHB: - always returns OKAY AXI: - 00: OKAY - 01: OKAY with all.." "OKAY,OKAY with all FFFF_FFFF data for all CRS..,?,?" newline bitfld.long 0x1C 2. "AMBA_ERROR_RESPONSE_VENDORID,Vendor ID Non-existent Slave Error Response Mapping. Determines the AXI slave response for errors on reads to non-existent Vendor ID register. For more details see 'Error Handling' in the AXI chapter of the Databook. AHB: -.." "OKAY,SLVERR/DECERR" newline rbitfld.long 0x1C 1. "RSVDP_1,Reserved for future use." "0,1" newline bitfld.long 0x1C 0. "AMBA_ERROR_RESPONSE_GLOBAL,Global Slave Error Response Mapping. Determines the AXI slave response for all error scenarios on non-posted requests. For more details see 'Error Handling' in the AXI chapter of the Databook. AHB: - 0: OKAY (with FFFF data for.." "OKAY,SLVERR/DECERR" line.long 0x20 "AMBA_LINK_TIMEOUT_OFF,Link Down AXI Bridge Slave Timeout Register. If your application AXI master issues outbound requests to the AXI bridge slave interface before the PCIe link is operational. the controller starts a 'flush' timer. The timeout value of.." hexmask.long.tbyte 0x20 9.--31. 1. "RSVDP_9,Reserved for future use." newline bitfld.long 0x20 8. "LINK_TIMEOUT_ENABLE_DEFAULT,Disable Flush. You can disable the flush feature by setting this field to '1'. Note: This register field is sticky." "0,1" newline hexmask.long.byte 0x20 0.--7. 1. "LINK_TIMEOUT_PERIOD_DEFAULT,Timeout Value (ms). The timer will timeout and then flush the bridge TX request queues after this amount of time. The timer counts when there are pending outbound AXI slave interface requests and the PCIe TX link is not.." line.long 0x24 "AMBA_ORDERING_CTRL_OFF,AMBA Ordering Control." hexmask.long.tbyte 0x24 8.--31. 1. "RSVDP_8,Reserved for future use." newline bitfld.long 0x24 7. "AX_MSTR_ZEROLREAD_FW,AXI Master Zero Length Read Forward to the application. The DW PCIe controller AXI bridge is able to terminate in order with the Posted transactions the zero length read implementing the PCIe express flush semantics of the Posted.." "The zero length Read is terminated at the DW..,The zero length Read is forward to the application" newline rbitfld.long 0x24 5.--6. "RSVDP_5,Reserved for future use." "0,1,2,3" newline bitfld.long 0x24 3.--4. "AX_MSTR_ORDR_P_EVENT_SEL,AXI Master Posted Ordering Event Selector. This field selects how the master interface determines when a P write is completed when enforcing the PCIe ordering rule 'NP must not pass P' at the AXI Master Interface. The AXI.." "B'last event: wait for the all of the write..,AW'last event: wait until the complete Posted..,This setting will not affect:,?" newline rbitfld.long 0x24 2. "RSVDP_2,Reserved for future use." "0,1" newline bitfld.long 0x24 1. "AX_SNP_EN,AXI Serialize Non-Posted Requests Enable. This field enables the AXI Bridge to serialize same ID Non-Posted Read/Write Requests on the wire. Serialization implies one outstanding same ID NP Read or Write on the wire and used to avoid AXI RAR.." "0,1" newline rbitfld.long 0x24 0. "RSVDP_0,Reserved for future use." "0,1" group.long (0x1E0+0x700)++0xB line.long 0x0 "COHERENCY_CONTROL_1_OFF,ACE Cache Coherency Control Register 1" hexmask.long 0x0 2.--31. 1. "CFG_MEMTYPE_BOUNDARY_LOW_ADDR,Boundary Lower Address For Memory Type. Bits [31:0] of dword-aligned address of the boundary for Memory type. The two lower address LSBs are '00'. Addresses up to but not including this value are in the lower address space.." newline rbitfld.long 0x0 1. "RSVDP_1,Reserved for future use." "0,1" newline bitfld.long 0x0 0. "CFG_MEMTYPE_VALUE,Sets the memory type for the lower and upper parts of the address space: - 0: lower = Peripheral; upper = Memory - 1: lower = Memory type; upper = Peripheral Note: This register field is sticky." "lower = Peripheral; upper = Memory,lower = Memory type; upper = Peripheral" line.long 0x4 "COHERENCY_CONTROL_2_OFF,ACE Cache Coherency Control Register 2" hexmask.long 0x4 0.--31. 1. "CFG_MEMTYPE_BOUNDARY_HIGH_ADDR,Boundary Upper Address For Memory Type. Bits [63:32] of the 64-bit dword-aligned address of the boundary for Memory type. Note: This register field is sticky." line.long 0x8 "COHERENCY_CONTROL_3_OFF,ACE Cache Coherency Control Register 3" hexmask.long.byte 0x8 27.--30. 1. "CFG_MSTR_AWCACHE_VALUE,Master Write CACHE Signal Value. Value of the individual bits in mstr_awcache when CFG_MSTR_AWCACHE_MODE is '1'. Note: not applicable to message requests; for message requests the value of mstr_awcache is always '0000' Note: This.." newline hexmask.long.byte 0x8 19.--22. 1. "CFG_MSTR_ARCACHE_VALUE,Master Read CACHE Signal Value. Value of the individual bits in mstr_arcache when CFG_MSTR_ARCACHE_MODE is '1'. Note: This register field is sticky." newline hexmask.long.byte 0x8 11.--14. 1. "CFG_MSTR_AWCACHE_MODE,Master Write CACHE Signal Behavior. Defines how the individual bits in mstr_awcache are controlled: - 0: set automatically by the AXI master - 1: set by the value of the corresponding bit of the CFG_MSTR_AWCACHE_VALUE field Note:.." newline hexmask.long.byte 0x8 3.--6. 1. "CFG_MSTR_ARCACHE_MODE,Master Read CACHE Signal Behavior. Defines how the individual bits in mstr_arcache are controlled: - 0: set automatically by the AXI master - 1: set by the value of the corresponding bit of the CFG_MSTR_ARCACHE_VALUE field Note:.." group.long (0x1F0+0x700)++0x7 line.long 0x0 "AXI_MSTR_MSG_ADDR_LOW_OFF,Lower 20 bits of the programmable AXI address where Messages coming from wire are mapped to. Bits [11:0] of the register are tied to zero for the address to be 4k-aligned. In previous releases. the third and fourth DWORDs of a.." hexmask.long.tbyte 0x0 12.--31. 1. "CFG_AXIMSTR_MSG_ADDR_LOW,Lower 20 bits of the programmable AXI address for Messages. Note: This register field is sticky." newline hexmask.long.word 0x0 0.--11. 1. "CFG_AXIMSTR_MSG_ADDR_LOW_RESERVED,Reserved for future use. Note: This register field is sticky." line.long 0x4 "AXI_MSTR_MSG_ADDR_HIGH_OFF,Upper 32 bits of the programmable AXI address where Messages coming from wire are mapped to." hexmask.long 0x4 0.--31. 1. "CFG_AXIMSTR_MSG_ADDR_HIGH,Upper 32 bits of the programmable AXI address for Messages. Note: This register field is sticky." rgroup.long (0x1F8+0x700)++0x7 line.long 0x0 "PCIE_VERSION_NUMBER_OFF,PCIe Controller IIP Release Version Number. The version number is given in hex format. You should convert each pair of hex characters to ASCII to interpret. Using 4.70a (GA) as an example: - VERSION_NUMBER = 0x3437302a which.." hexmask.long 0x0 0.--31. 1. "VERSION_NUMBER,Version Number." line.long 0x4 "PCIE_VERSION_TYPE_OFF,PCIe Controller IIP Release Version Type. The type is given in hex format. You should convert each pair of hex characters to ASCII to interpret. Using 4.70a (GA) as an example: - VERSION_NUMBER = 0x3437302a which translates to 470*.." hexmask.long 0x4 0.--31. 1. "VERSION_TYPE,Version Type." group.long (0x240+0x700)++0x7 line.long 0x0 "MSIX_ADDRESS_MATCH_LOW_OFF,MSI-X Address Match Low Register. When you enable the MSI-X Table RAM feature (MSIX_TABLE_EN=1). the controller implements the logic and RAM required to generate MSI-X requests. For more details. see the Interrupts section in.." hexmask.long 0x0 2.--31. 1. "MSIX_ADDRESS_MATCH_LOW,MSI-X Address Match Low Address. Note: This register field is sticky." newline rbitfld.long 0x0 1. "MSIX_ADDRESS_MATCH_RESERVED_1,Reserved. Note: This register field is sticky." "0,1" newline bitfld.long 0x0 0. "MSIX_ADDRESS_MATCH_EN,MSI-X Match Enable. Enable the MSI-X Address Match feature when the AXI bridge is present. Note: This register field is sticky." "0,1" line.long 0x4 "MSIX_ADDRESS_MATCH_HIGH_OFF,MSI-X Address Match High Register. When you enable the MSI-X Table RAM feature (MSIX_TABLE_EN=1). the controller implements the logic and RAM required to generate MSI-X requests. For more details. see the Interrupts section in.." hexmask.long 0x4 0.--31. 1. "MSIX_ADDRESS_MATCH_HIGH,MSI-X Address Match High Address. Note: This register field is sticky." wgroup.long (0x248+0x700)++0x3 line.long 0x0 "MSIX_DOORBELL_OFF,MSI-X Doorbell Register. When you enable the MSI-X Table RAM feature (MSIX_TABLE_EN=1). the controller implements the logic and RAM required to generate MSI-X requests. For more details. see the Interrupts section in the 'Controller.." bitfld.long 0x0 29.--31. "MSIX_DOORBELL_RESERVED_29_31,Reserved." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x0 24.--28. 1. "MSIX_DOORBELL_PF,MSIX Doorbell Physical Function. This register determines the Physical Function for the MSI-X transaction." newline hexmask.long.byte 0x0 16.--23. 1. "MSIX_DOORBELL_VF,MSIX Doorbell Virtual Function. This register determines the Virtual Function for the MSI-X transaction." newline bitfld.long 0x0 15. "MSIX_DOORBELL_VF_ACTIVE,MSIX Doorbell Virtual Function Active. This register determines whether a Virtual Function is used to generate the MSI-X transaction." "0,1" newline bitfld.long 0x0 12.--14. "MSIX_DOORBELL_TC,MSIX Doorbell Traffic Class. This register determines which traffic class to generate the MSI-X transaction with." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 11. "MSIX_DOORBELL_RESERVED_11,Reserved." "0,1" newline hexmask.long.word 0x0 0.--10. 1. "MSIX_DOORBELL_VECTOR,MSI-X Doorbell Vector. This register determines which vector to generate the MSI-X transaction for." group.long (0x24C+0x700)++0x3 line.long 0x0 "MSIX_RAM_CTRL_OFF,MSI-X RAM power mode and debug control register. When you enable the MSI-X Table RAM feature (MSIX_TABLE_EN=1). the controller implements the logic and RAM required to generate MSI-X requests. For more details. see the Interrupts.." hexmask.long.byte 0x0 26.--31. 1. "MSIX_RAM_CTRL_RESERVED_26_31,Reserved. Note: This register field is sticky." newline bitfld.long 0x0 25. "MSIX_RAM_CTRL_DBG_PBA,MSIX PBA RAM Debug Mode. Use this bit to activate the debug mode and allow direct read/write access to the PBA. Use can also use the dbg_pba input to activate debug mode. Debug mode turns off the PF/VF/Offset-based addressing into.." "0,1" newline bitfld.long 0x0 24. "MSIX_RAM_CTRL_DBG_TABLE,MSIX Table RAM Debug Mode. Use this bit to activate the debug mode and allow direct read/write access to the Table. Use can also use the dbg_table input to activate debug mode. Debug mode turns off the PF/VF/Offset-based.." "0,1" newline hexmask.long.byte 0x0 17.--23. 1. "MSIX_RAM_CTRL_RESERVED_17_23,Reserved. Note: This register field is sticky." newline bitfld.long 0x0 16. "MSIX_RAM_CTRL_BYPASS,MSIX RAM Control Bypass. The bypass field when set disables the internal generation of low power signals for both RAMs. It is up to the application to ensure the RAMs are in the proper power state before trying to access them." "0,1" newline hexmask.long.byte 0x0 10.--15. 1. "MSIX_RAM_CTRL_RESERVED_10_15,Reserved. Note: This register field is sticky." newline bitfld.long 0x0 9. "MSIX_RAM_CTRL_PBA_SD,MSIX PBA RAM Shut Down. Set this bit to drive the cfg_msix_pba_sd output to signal your external logic to place the MSIX PBA RAM in Shut Down low-power mode. Note: This register field is sticky." "0,1" newline bitfld.long 0x0 8. "MSIX_RAM_CTRL_PBA_DS,MSIX PBA RAM Deep Sleep. Set this bit to drive the cfg_msix_pba_ds output to signal your external logic to place the MSIX PBA RAM in Deep Sleep low-power mode. Note: This register field is sticky." "0,1" newline hexmask.long.byte 0x0 2.--7. 1. "MSIX_RAM_CTRL_RESERVED_2_7,Reserved. Note: This register field is sticky." newline bitfld.long 0x0 1. "MSIX_RAM_CTRL_TABLE_SD,MSIX Table RAM Shut Down. Set this bit to drive the cfg_msix_table_sd output to signal your external logic to place the MSIX Table RAM in Shut Down low-power mode. Note: This register field is sticky." "0,1" newline bitfld.long 0x0 0. "MSIX_RAM_CTRL_TABLE_DS,MSIX Table RAM Deep Sleep. Set this bit to drive the cfg_msix_table_ds output to signal your external logic to place the MSIX Table RAM in Deep Sleep low-power mode. Note: This register field is sticky." "0,1" group.long (0x430+0x700)++0x3 line.long 0x0 "PL_LTR_LATENCY_OFF,LTR Latency Register. The function of this register field (and all other fields in this register) differs between an upstream port and a downstream port. For an upstream port. the register fields capture the corresponding fields in the.." bitfld.long 0x0 31. "NO_SNOOP_LATENCY_REQUIRE,No Snoop Latency Requirement. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" "0,1" newline rbitfld.long 0x0 29.--30. "RSVDP_29,Reserved for future use." "0,1,2,3" newline bitfld.long 0x0 26.--28. "NO_SNOOP_LATENCY_SCALE,No Snoop Latency Scale. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" "0,1,2,3,4,5,6,7" newline hexmask.long.word 0x0 16.--25. 1. "NO_SNOOP_LATENCY_VALUE,No Snoop Latency Value. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" newline bitfld.long 0x0 15. "SNOOP_LATENCY_REQUIRE,Snoop Latency Requirement. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" "0,1" newline rbitfld.long 0x0 13.--14. "RSVDP_13,Reserved for future use." "0,1,2,3" newline bitfld.long 0x0 10.--12. "SNOOP_LATENCY_SCALE,Snoop Latency Scale. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" "0,1,2,3,4,5,6,7" newline hexmask.long.word 0x0 0.--9. 1. "SNOOP_LATENCY_VALUE,Snoop Latency Value. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" group.long (0x440+0x700)++0xB line.long 0x0 "AUX_CLK_FREQ_OFF,Auxiliary Clock Frequency Control Register." hexmask.long.tbyte 0x0 10.--31. 1. "RSVDP_10,Reserved for future use." newline hexmask.long.word 0x0 0.--9. 1. "AUX_CLK_FREQ,The aux_clk frequency in MHz. This value is used to provide a 1 us reference for counting time during low-power states with aux_clk when the PHY has removed the pipe_clk. Frequencies lower than 1 MHz are possible but with a loss of accuracy.." line.long 0x4 "L1_SUBSTATES_OFF,L1 Substates Timing Register." hexmask.long.tbyte 0x4 9.--31. 1. "RSVDP_9,Reserved for future use." newline bitfld.long 0x4 8. "L1SUB_LOW_POWER_CLOCK_SWITCH_MODE,If this bit is set to 1'b1 the reference clock will be running regardless of the CLKREQ# setting. If this bit is set to 1'b0 the reference clock may be gated off when CLKREQ# is de-asserted. If the bit is set to 1'b1 the.." "0,1" newline bitfld.long 0x4 6.--7. "L1SUB_T_PCLKACK,Max delay (in 1us units) between a MAC request to remove the clock on mac_phy_pclkreq_n and a PHY response on phy_mac_pclkack_n. If the PHY does not respond within this time the request is aborted.The actual timeout value will be.." "0,1,2,3" newline hexmask.long.byte 0x4 2.--5. 1. "L1SUB_T_L1_2,Duration (in 1us units) of L1.2. The actual timeout value will be L1SUB_T_L1_2 + 1. Range is 0.15. Note: This register field is sticky." newline bitfld.long 0x4 0.--1. "L1SUB_T_POWER_OFF,Duration (in 1us units) of L1.2.Entry. The actual timeout value will be L1SUB_T_POWER_OFF + 1. Range is 0.3. Note: This register field is sticky." "0,1,2,3" line.long 0x8 "POWERDOWN_CTRL_STATUS_OFF,Powerdown Control and Status Register." hexmask.long.tbyte 0x8 12.--31. 1. "RSVDP_12,Reserved for future use." newline hexmask.long.byte 0x8 8.--11. 1. "POWERDOWN_PHY_POWERDOWN,This field represents the Powerdown value that has been acknowledged by the PHY. It is updated with the value of Powerdown driven by the controller when the PHY has returned the Phystatus acknowledgment for the Powerdown.." newline hexmask.long.byte 0x8 4.--7. 1. "POWERDOWN_MAC_POWERDOWN,This field represents the Powerdown value driven by the controller to the PHY." newline rbitfld.long 0x8 1.--3. "RSVDP_1,Reserved for future use." "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 0. "POWERDOWN_FORCE,This field is a one shot field. Writing a value of 1 to this field causes the controller to complete the P2 Powerdown handshake regardless of whether the PHY has returned Phystatus. This field could be used for debug purposes in event.." "0,1" group.long (0x470+0x700)++0x7 line.long 0x0 "PHY_VIEWPORT_CTLSTS_OFF,PHY Register Viewport Control and Status Register." rbitfld.long 0x0 31. "PHY_VIEWPORT_PENDING,PHY viewport pending. Indicates the access is pending. - 1 : Pending - 0 : Idle This bit is set to 1 when the read/write access has been initiated. This bit is cleared when the access is completed. If phy_reg_clk_g is never activated.." "Idle,Pending" newline rbitfld.long 0x0 30. "PHY_VIEWPORT_STATUS,PHY viewport status. Indicates the status of the latest access. - 1 : Timeout - 0 : No errors If the timeout is detected this bit is set to 1 and PHY_VIEWPORT_PENDING is cleared. This bit is cleared when the read/write access is.." "No errors,Timeout" newline hexmask.long.byte 0x0 23.--29. 1. "RSVDP_23,Reserved for future use." newline bitfld.long 0x0 22. "PHY_VIEWPORT_TIMEOUT_DISABLE,PHY viewport timeout disable. Disables the PHY register access timeout structure. When the timeout is disabled you must ensure that the PHY register accesses are always acknowledged by cr_para_ack. Otherwise.." "0,1" newline bitfld.long 0x0 21. "PHY_VIEWPORT_BCWR,Broadcast write access to all xN sub-blocks. If you need to broadcast the write accesses into all lanes both PHY_VIEWPORT_ADDR[15] and this bit should be 1. Note: This register field is sticky." "0,1" newline bitfld.long 0x0 20. "PHY_VIEWPORT_READ,PHY viewport read. If set a read access is initiated. The value is always 0 when this bit is read. Note: This register field is sticky." "0,1" newline hexmask.long.byte 0x0 16.--19. 1. "PHY_VIEWPORT_NUM,PHY viewport xN sub-block number. Selects one of xN sub-blocks. This register is not used when the write access is initiated with PHY_VIEWPORT_BCWR==1. Note: This register field is sticky." newline hexmask.long.word 0x0 0.--15. 1. "PHY_VIEWPORT_ADDR,PHY viewport address. Indicates the PHY's register address. Please refer to the PHY databook for the address map definition. Note: This register field is sticky." line.long 0x4 "PHY_VIEWPORT_DATA_OFF,PHY Register Viewport Data Register." hexmask.long.word 0x4 16.--31. 1. "RSVDP_16,Reserved for future use." newline hexmask.long.word 0x4 0.--15. 1. "PHY_VIEWPORT_DATA,PHY viewport data. A write access to this register initiates the PHY register write access. By a read access to this register this field returns the latest read data from the PHY register. Note: This register field is sticky." group.long (0x490+0x700)++0x3 line.long 0x0 "PIPE_RELATED_OFF,PIPE Related Register. This register controls the pipe's capabitity. control. and status parameters." hexmask.long.tbyte 0x0 9.--31. 1. "RSVDP_9,Reserved for future use." newline bitfld.long 0x0 8. "PIPE_GARBAGE_DATA_MODE,PIPE Garbage Data Mode. - 0: PIPE Spec compliant mode: The MAC discards any symbols received after the electrical idle ordered-set until RxValid is deasserted. - 1: Special PHY Support mode: The MAC discards any symbols received.." "PIPE Spec compliant mode: The MAC discards any..,Special PHY Support mode: The MAC discards any.." tree.end tree.end tree "PCIE1_VF01" base ad:0xF1020000 tree "PF0_TYPE1_HDR (PCI-Compatible Configuration Space Header Type1)" group.long 0x0++0x2F line.long 0x0 "TYPE1_DEV_ID_VEND_ID_REG,Device ID and Vendor ID Register." hexmask.long.word 0x0 16.--31. 1. "DEVICE_ID,Device ID. The Device ID register identifies the particular Function. This identifier is allocated by the vendor. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else.." newline hexmask.long.word 0x0 0.--15. 1. "VENDOR_ID,Vendor ID. The Vendor ID register identifies the manufacturer of the Function. Valid vendor identifiers are allocated by the PCI-SIG to ensure uniqueness. It is not permitted to populate this register with a value of FFFFh which is an invalid.." line.long 0x4 "TYPE1_STATUS_COMMAND_REG,Status and Command Register." bitfld.long 0x4 31. "DETECTED_PARITY_ERROR,Detected Parity Error. This bit is set by a Function whenever it receives a Poisoned TLP regardless of the state the Parity Error Response bit in the Command register. The bit is set when the Poisoned TLP is received by a.." "0,1" newline bitfld.long 0x4 30. "SIGNALED_SYS_ERROR,Signaled System Error. This bit is set when a Function sends an ERR_FATAL or ERR_NONFATAL Message and the SERR# Enable bit in the Command register is 1b." "0,1" newline bitfld.long 0x4 29. "RCVD_MASTER_ABORT,Received Master Abort. This bit is set when a Requester receives a Completion with Unsupported Request Completion status. The bit is set when the Unsupported Request is received by a Function's primary side." "0,1" newline bitfld.long 0x4 28. "RCVD_TARGET_ABORT,Received Target Abort. This bit is set when a Requester receives a Completion with Completer Abort Completion status. The bit is set when the Completer Abort is received by a Function's primary side." "0,1" newline bitfld.long 0x4 27. "SIGNALED_TARGET_ABORT,Signaled Target Abort. This bit is set when a Function completes a Posted or Non-Posted Request as a Completer Abort error. This applies to a Function when the Completer Abort was generated by its primary side." "0,1" newline rbitfld.long 0x4 25.--26. "DEV_SEL_TIMING,DEVSEL Timing. This field was originally described in the PCI Local Bus Specification. Its functionality does not apply to PCI Express. The controller hardwires it to 00b." "0,1,2,3" newline bitfld.long 0x4 24. "MASTER_DPE,Master Data Parity Error. This bit is set by a Function if the Parity Error Response bit in the Command register is 1b and either of the following two conditions occurs: - Port receives a Poisoned Completion going downstream - Port transmits a.." "0,1" newline rbitfld.long 0x4 23. "FAST_B2B_CAP,Fast Back-to-Back Transactions Capable. This bit was originally described in the PCI Local Bus Specification. Its functionality does not apply to PCI Express. The controller hardwires this bit to 0b." "0,1" newline rbitfld.long 0x4 22. "RSVDP_22,Reserved for future use." "0,1" newline rbitfld.long 0x4 21. "FAST_66MHZ_CAP,66 MHz Capable. This bit was originally described in the PCI Local Bus Specification. Its functionality does not apply to PCI Express. The controller hardwires this bit to 0b." "0,1" newline rbitfld.long 0x4 20. "CAP_LIST,Capabilities List. Indicates the presence of an Extended Capability list item. Since all PCI Express device Functions are required to implement the PCI Express Capability structure the controller hardwires this bit to 1b." "0,1" newline rbitfld.long 0x4 19. "INT_STATUS,Interrupt Status. When set indicates that an INTx emulation interrupt is pending internally in the Function. INTx emulation interrupts forwarded by Functions from the secondary side are not reflected in this bit. Setting the Interrupt Disable.." "0,1" newline rbitfld.long 0x4 17.--18. "RSVDP_17,Reserved for future use." "0,1,2,3" newline bitfld.long 0x4 16. "IMM_READINESS,Immediate Readiness. This optional bit when set indicates the Function is guaranteed to be ready to successfully complete valid configuration accesses at any time following any reset that the host is capable of issuing Configuration.." "0,1" newline hexmask.long.byte 0x4 11.--15. 1. "RESERV,Reserved." newline bitfld.long 0x4 10. "INT_EN,Interrupt Disable. Controls the ability of a Function to generate INTx emulation interrupts. When set Functions are prevented from asserting INTx interrupts. Note: - Any INTx emulation interrupts already asserted by the Function must be.." "0,1" newline rbitfld.long 0x4 9. "RSVDP_9,Reserved for future use." "0,1" newline bitfld.long 0x4 8. "SERREN,SERR# Enable. When set this bit enables reporting upstream of Non-fatal and Fatal errors detected by the Function. Note: The errors are reported if enabled either through this bit or through the PCI Express specific bits in the Device Control.." "0,1" newline rbitfld.long 0x4 7. "IDSEL,IDSEL Stepping/Wait Cycle Control. This bit was originally described in the PCI Local Bus Specification. Its functionality does not apply to PCI Express. The controller hardwires this bit to 0b." "0,1" newline bitfld.long 0x4 6. "PERREN,Parity Error Response. This bit controls the logging of poisoned TLPs in the Master Data Parity Error bit in the Status register. For more details see the 'Error Registers' section of the PCI Express Base Specification." "0,1" newline rbitfld.long 0x4 5. "VGAPS,VGA Palette Snoop. This bit was originally described in the PCI Local Bus Specification and the PCI-to-PCI Bridge Architecture Specification. Its functionality does not apply to PCI Express. The controller hardwires this bit to 0b." "0,1" newline rbitfld.long 0x4 4. "MWI_EN,Memory Write and Invalidate. This bit was originally described in the PCI Local Bus Specification and the PCI-to-PCI Bridge Architecture Specification. Its functionality does not apply to PCI Express. The controller hardwires this bit to 0b. For.." "0,1" newline rbitfld.long 0x4 3. "SCO,Special Cycle Enable. This bit was originally described in the PCI Local Bus Specification. Its functionality does not apply to PCI Express. The controller hardwires this bit to 0b." "0,1" newline bitfld.long 0x4 2. "BME,Bus Master Enable. This bit controls forwarding of Memory or I/O requests by a port in the Upstream direction. When this bit is 0b Memory and I/O Requests received at a Root Port must be handled as Unsupported Requests (UR) For Non-Posted Requests a.." "0,1" newline bitfld.long 0x4 1. "MSE,Memory Space Enable. This bit controls a Function's response to Memory Space accesses received on its primary side. - When set the Function is enabled to decode the address and further process Memory Space accesses. - When clear all received Memory.." "0,1" newline bitfld.long 0x4 0. "IO_EN,IO Space Enable. This bit controls a Function's response to I/O Space accesses received on its primary side. - When set the Function is enabled to decode the address and further process I/O Space accesses. - When clear all received I/O accesses.." "0,1" line.long 0x8 "TYPE1_CLASS_CODE_REV_ID_REG,Class Code and Revision ID Register." hexmask.long.byte 0x8 24.--31. 1. "BASE_CLASS_CODE,Base Class Code. A code that broadly classifies the type of operation the Function performs. Encodings for base class are provided in the PCI Code and ID Assignment Specification. All unspecified encodings are reserved. Note: The access.." newline hexmask.long.byte 0x8 16.--23. 1. "SUBCLASS_CODE,Sub-Class Code. Specifies a base class sub-class which identifies more specifically the operation of the Function. Encodings for sub-class are provided in the PCI Code and ID Assignment Specification. All unspecified encodings are.." newline hexmask.long.byte 0x8 8.--15. 1. "PROGRAM_INTERFACE,Programming Interface. This field identifies a specific register level programming interface (if any) so that device independent software can interact with the Function. Encodings for interface are provided in the PCI Code and ID.." newline hexmask.long.byte 0x8 0.--7. 1. "REVISION_ID,Revision ID. The value of this field specifies a Function specific revision identifier. The value is chosen by the vendor. Zero is an acceptable value. The Revision ID should be viewed as a vendor defined extension to the Device ID. Note: The.." line.long 0xC "TYPE1_BIST_HDR_TYPE_LAT_CACHE_LINE_SIZE_REG,BIST. Header Type. Latency Timer. and Cache Line Size Register." hexmask.long.byte 0xC 24.--31. 1. "BIST,BIST. This register is used for control and status of BIST. Functions that do not support BIST must hardwire the register to 00h. A Function whose BIST is invoked must not prevent normal operation of the PCI Express Link. Bit descriptions: - [31]:.." newline rbitfld.long 0xC 23. "MULTI_FUNC,Multi-Function Device. - When set indicates that the device may contain multiple Functions but not necessarily. Software is permitted to probe for Functions other than Function 0. - When clear software must not probe for Functions other.." "0,1" newline hexmask.long.byte 0xC 16.--22. 1. "HEADER_TYPE,Header Layout. This field identifies the layout of the second part of the predefined header. The controller uses 000 0001b encoding. The encoding 000 0010b is reserved. This encoding was originally described in the PC Card Standard Electrical.." newline hexmask.long.byte 0xC 8.--15. 1. "LATENCY_MASTER_TIMER,Latency Timer. This register is also referred to as Primary Latency Timer. The Latency Timer was originally described in the PCI Local Bus Specification and the PCI-to-PCI Bridge Architecture Specification. Its functionality does not.." newline hexmask.long.byte 0xC 0.--7. 1. "CACHE_LINE_SIZE,Cache Line Size. The Cache Line Size register is programmed by the system firmware or the operating system to system cache line size. However legacy conventional PCI software may not always be able to program this register correctly.." line.long 0x10 "BAR0_REG,BAR0 Register. System software must build a consistent address map before booting the machine to an operating system. This means it has to determine how much memory is in the system. and how much address space the Functions in the system.." hexmask.long 0x10 4.--31. 1. "BAR0_START,BAR0 Base Address. - Memory Space: Base Address. - IO Space: bits[31:2] are used to map the function into IO space/Base. Address. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R(Sticky)/W(Sticky) if.." newline bitfld.long 0x10 3. "BAR0_PREFETCH,BAR0 Prefetchable. - Memory Space: Set to one if data is pre-fetchable. A Function is permitted to mark a range as prefetchable. If there are no side effects on reads the function returns all bytes on reads regardless of the byte enables.." "0,1" newline bitfld.long 0x10 1.--2. "BAR0_TYPE,BAR0 Type. - Memory Space: Base Address registers that map into Memory Space can be 32 bits or 64 bits wide (to support mapping into a 64-bit address space). The bit encoding is as follows: -- 00: Base register is 32 bits wide and can be mapped.." "Base register is 32 bits wide and can be mapped..,Reserved,?,?" newline bitfld.long 0x10 0. "BAR0_MEM_IO,BAR0 Memory Space Indicator. This bit is used to determine whether the register maps into Memory or I/O Space. Base Address registers that map to Memory Space must return a 0b. Base Address registers that map to I/O Space must return a 1b." "0,1" line.long 0x14 "BAR1_REG,BAR1 Register. System software must build a consistent address map before booting the machine to an operating system. This means it has to determine how much memory is in the system. and how much address space the Functions in the system.." hexmask.long 0x14 4.--31. 1. "BAR1_START,BAR1 Base Address. - Memory Space: Base Address. - IO Space: bits[31:2] are used to map the function into IO space/Base. Address. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R(Sticky)/W(Sticky) if.." newline bitfld.long 0x14 3. "BAR1_PREFETCH,BAR1 Prefetchable. - Memory Space: Set to one if data is pre-fetchable. A Function is permitted to mark a range as prefetchable. If there are no side effects on reads the function returns all bytes on reads regardless of the byte enables.." "0,1" newline bitfld.long 0x14 1.--2. "BAR1_TYPE,BAR1 Type. - Memory Space: Base Address registers that map into Memory Space can be 32 bits or 64 bits wide (to support mapping into a 64-bit address space). The bit encoding is as follows: -- 00: Base register is 32 bits wide and can be mapped.." "Base register is 32 bits wide and can be mapped..,Reserved,?,?" newline bitfld.long 0x14 0. "BAR1_MEM_IO,BAR1 Memory Space Indicator. This bit is used to determine whether the register maps into Memory or I/O Space. Base Address registers that map to Memory Space must return a 0b. Base Address registers that map to I/O Space must return a 1b." "0,1" line.long 0x18 "SEC_LAT_TIMER_SUB_BUS_SEC_BUS_PRI_BUS_REG,Secondary Latency Timer. Subordinate Bus Number. Secondary Bus Number. and Primary Bus Number Register." hexmask.long.byte 0x18 24.--31. 1. "SEC_LAT_TIMER,Secondary Latency Timer. This register does not apply to PCI Express. The controller hardwires it to 00h." newline hexmask.long.byte 0x18 16.--23. 1. "SUB_BUS,Subordinate Bus Number. The Subordinate Bus Number register is used to record the bus number of the highest numbered PCI bus segment which is behind (or subordinate to) the bridge. Configuration software programs the value in this register. The.." newline hexmask.long.byte 0x18 8.--15. 1. "SEC_BUS,Secondary Bus Number. The Secondary Bus Number register is used to record the bus number of the PCI bus segment to which the secondary interface of the bridge is connected. Configuration software programs the value in this register. The bridge.." newline hexmask.long.byte 0x18 0.--7. 1. "PRIM_BUS,Primary Bus Number. This register is not used by PCI Express Functions. It is implemented for compatibility with legacy software." line.long 0x1C "SEC_STAT_IO_LIMIT_IO_BASE_REG,Secondary Status. and I/O Limit and Base Register. The I/O Limit and I/O Base registers are optional and define an address range that is used by the bridge to determine when to forward I/O transactions from one interface to.." bitfld.long 0x1C 31. "SEC_STAT_DPE,Detected Parity Error. This bit is set by a Function when a Poisoned TLP is received by its secondary side regardless of the state the Parity Error Response Enable bit in the Bridge Control register." "0,1" newline bitfld.long 0x1C 30. "SEC_STAT_RCVD_SYS_ERR,Received System Error. This bit is set when the secondary side of a Function receives an ERR_FATAL or ERR_NONFATAL message." "0,1" newline bitfld.long 0x1C 29. "SEC_STAT_RCVD_MSTR_ABRT,Received Master Abort. This bit is set when the secondary side of a Function (for requests initiated by the Type 1 header Function itself) receives a Completion with Unsupported Request Completion status." "0,1" newline bitfld.long 0x1C 28. "SEC_STAT_RCVD_TRGT_ABRT,Received Target Abort. This bit is set when the secondary side of a Function (for requests initiated by the Type 1 header Function itself) receives a Completion with Completer Abort Completion status." "0,1" newline bitfld.long 0x1C 27. "SEC_STAT_SIG_TRGT_ABRT,Signaled Target Abort. This bit is set when the secondary side of the Function (for Requests completed by the Type 1 header Function itself) completes a Posted or Non-Posted request as a Completer Abort error." "0,1" newline rbitfld.long 0x1C 25.--26. "RSVDP_25,Reserved for future use." "0,1,2,3" newline bitfld.long 0x1C 24. "SEC_STAT_MDPE,Master Data Parity Error. This bit is set by a Function if the Parity Error Response Enable bit in the Bridge Control register is set and either of the following two conditions occurs: - Port receives a Poisoned Completion coming Upstream.." "0,1" newline rbitfld.long 0x1C 23. "RSVDP_23,Reserved for future use." "0,1" newline hexmask.long.byte 0x1C 16.--22. 1. "SEC_STAT_RESERV,Reserved." newline hexmask.long.byte 0x1C 12.--15. 1. "IO_LIMIT,I/O Limit Address. These bits correspond to the address[15:12] of IO address range. For the purpose of address decoding the bridge assumes that the lower 12 address bits address[11:0] of the I/O limit address (not implemented in the I/O Limit.." newline rbitfld.long 0x1C 9.--11. "IO_RESERV1,Reserved." "0,1,2,3,4,5,6,7" newline bitfld.long 0x1C 8. "IO_DECODE_BIT8,I/O Addressing Encode (IO Limit Address). This bit encodes the IO addressing capability of the bridge. IO_DECODE_BIT8 indicates the following: - 0h: The bridge supports only 16-bit I/O addressing (for ISA compatibility). For the purpose of.." "0,1" newline hexmask.long.byte 0x1C 4.--7. 1. "IO_BASE,I/O Base Address. These bits correspond to the address[15:12] of IO address range. For the purpose of address decoding the bridge assumes that the lower 12 address bits address[11:0] of the I/O base address (not implemented in the I/O Base.." newline rbitfld.long 0x1C 1.--3. "IO_RESERV,Reserved." "0,1,2,3,4,5,6,7" newline bitfld.long 0x1C 0. "IO_DECODE,I/O Addressing Encode (IO Base Address) This bit encodes the IO addressing capability of the bridge. IO_DECODE indicates the following: - 0h: The bridge supports only 16-bit I/O addressing (for ISA compatibility). For the purpose of address.." "0,1" line.long 0x20 "MEM_LIMIT_MEM_BASE_REG,Memory Limit and Base Register. The Memory Limit and Memory Base registers define a memory mapped address range which is used by the bridge to determine when to forward memory transactions from one interface to the other. If there.." hexmask.long.word 0x20 20.--31. 1. "MEM_LIMIT,Memory Limit Address. These bits correspond to the upper 12 address bits Address[31:20] of 32-bit addresses. For the purpose of address decoding the bridge assumes that the lower 20 address bits Address[19:0] of the memory limit address.." newline hexmask.long.byte 0x20 16.--19. 1. "MEM_LIMIT_RESERV,Reserved." newline hexmask.long.word 0x20 4.--15. 1. "MEM_BASE,Memory Base Address. These bits correspond to the upper 12 address bits Address[31:20] of 32-bit addresses. For the purpose of address decoding the bridge assumes that the lower 20 address bits Address[19:0] of the memory base address (not.." newline hexmask.long.byte 0x20 0.--3. 1. "MEM_BASE_RESERV,Reserved." line.long 0x24 "PREF_MEM_LIMIT_PREF_MEM_BASE_REG,Prefetchable Memory Limit and Base Register. The Prefetchable Memory Limit and Prefetchable Memory Base registers must indicate that 64-bit addresses are supported. as defined in PCI-to-PCI Bridge Architecture.." hexmask.long.word 0x24 20.--31. 1. "PREF_MEM_LIMIT,Prefetchable Memory Limit Address. If the Prefetchable Memory Limit register indicates support for 32-bit addressing then the Prefetchable Limit Upper 32 Bits register is implemented as a read-only register that returns zero when read. If.." newline rbitfld.long 0x24 17.--19. "PREF_RESERV1,Reserved." "0,1,2,3,4,5,6,7" newline rbitfld.long 0x24 16. "PREF_MEM_LIMIT_DECODE,Prefetchable Memory Limit Decode. This bit encodes whether or not the bridge supports 64-bit addresses. Note: This bit is a copy of the PREF_MEM_DECODE bit and always reflects the current value of that bit. The value of.." "0,1" newline hexmask.long.word 0x24 4.--15. 1. "PREF_MEM_BASE,Prefetchable Memory Base Address. If the Prefetchable Memory Base register indicates support for 32-bit addressing then the Prefetchable Base Upper 32 Bits register is implemented as a read-only register that returns zero when read. If the.." newline rbitfld.long 0x24 1.--3. "PREF_RESERV,Reserved." "0,1,2,3,4,5,6,7" newline bitfld.long 0x24 0. "PREF_MEM_DECODE,Prefetchable Memory Base Decode. This bit encodes whether or not the bridge supports 64-bit addresses. Note: By default the bit is set to 1'b1 indicating that 64-bit addresses are supported. If the bridge only supports 32-bit prefetchable.." "0,1" line.long 0x28 "PREF_BASE_UPPER_REG,Prefetchable Base Upper 32 Bits Register. The Prefetchable Base Upper 32 Bits register is an optional extension to the Prefetchable Memory Base register." hexmask.long 0x28 0.--31. 1. "PREF_MEM_BASE_UPPER,Prefetchable Base Upper 32 Bit. If the Prefetchable Memory Base register indicates support for 32-bit addressing then this register is implemented as read-only register that returns zero when read. If the Prefetchable Memory Base.." line.long 0x2C "PREF_LIMIT_UPPER_REG,Prefetchable Limit Upper 32 Bits Register. The Prefetchable Limit Upper 32 Bits register is an optional extension to the Prefetchable Memory Limit register." hexmask.long 0x2C 0.--31. 1. "PREF_MEM_LIMIT_UPPER,Prefetchable Limit Upper 32 Bit. If the Prefetchable Memory Limit register indicate support for 64-bit addressing then this register is implemented as read/write register which must be initialized by configuration software. This.." rgroup.long 0x30++0x3 line.long 0x0 "IO_LIMIT_UPPER_IO_BASE_UPPER_REG,I/O Limit and Base Upper 16 Bits Register. The I/O Limit Upper 16 Bits and I/O Base Upper 16 Bits registers are optional extensions to the I/O Limit and I/O Base registers." hexmask.long.word 0x0 16.--31. 1. "IO_LIMIT_UPPER,I/O Limit Upper 16 Bits. If the I/O Limit register indicates support for 16-bit I/O address decoding then this register is implemented as a read-only register which return zero when read. If the I/O Limit register indicates support for.." newline hexmask.long.word 0x0 0.--15. 1. "IO_BASE_UPPER,I/O Base Upper 16 Bits. If the I/O Base register indicates support for 16-bit I/O address decoding then this register is implemented as a read-only register which return zero when read. If the I/O base register indicates support for 32-bit.." group.long 0x34++0xB line.long 0x0 "TYPE1_CAP_PTR_REG,Capabilities Pointer Register." hexmask.long.tbyte 0x0 8.--31. 1. "RSVDP_8,Reserved for future use." newline hexmask.long.byte 0x0 0.--7. 1. "CAP_POINTER,Capabilities Pointer. This register is used to point to a linked list of capabilities implemented by this Function. Since all PCI Express Functions are required to implement the PCI Express Capability structure this register must point to a.." line.long 0x4 "TYPE1_EXP_ROM_BASE_REG,Expansion ROM Base Address Register. This register is defined to handle the base address and size information for this expansion ROM. The mask for this ROM BAR exists (if implemented) as a shadow register at this address. The.." hexmask.long.tbyte 0x4 11.--31. 1. "EXP_ROM_BASE_ADDRESS,Expansion ROM Base Address. Upper 21 bits of the Expansion ROM base address. The number of bits (out of these 21) that a Function actually implements depends on how much address space the Function requires. The mask for this ROM BAR.." newline hexmask.long.word 0x4 1.--10. 1. "RSVDP_1,Reserved for future use." newline bitfld.long 0x4 0. "ROM_BAR_ENABLE,Expansion ROM Enable. This bit controls whether or not the Function accepts accesses to its expansion ROM. When this bit is 0b the Function's expansion ROM address space is disabled. When the bit is 1b address decoding is enabled using.." "0,1" line.long 0x8 "BRIDGE_CTRL_INT_PIN_INT_LINE_REG,Bridge Control. Interrupt Pin. and Interrupt Line Register." hexmask.long.word 0x8 23.--31. 1. "BRIDGE_CTRL_RESERV,Reserved." newline bitfld.long 0x8 22. "SBR,Secondary Bus Reset. Setting this bit triggers a hot reset on the corresponding PCI Express Port. Software must ensure a minimum reset duration (Trst) as defined in the PCI Local Bus Specification. Software and systems must honor.." "0,1" newline rbitfld.long 0x8 21. "MSTR_ABORT_MODE,Master Abort Mode. This bit was originally described in the PCI-to-PCI Bridge Architecture Specification. Its functionality does not apply to PCI Express. The controller hardwires this bit to 0b. Note: The access attributes of this field.." "0,1" newline rbitfld.long 0x8 20. "VGA_16B_DEC,VGA 16 bit decode. This bit only has meaning if VGA Enable bit is set. This bit enables system configuration software to select between 10-bit and 16-bit I/O address decoding for all VGA I/O register accesses that are forwarded from primary.." "0,1" newline rbitfld.long 0x8 19. "VGA_EN,VGA Enable. Modifies the response by the bridge to VGA compatible addresses. If the VGA Enable bit is set the bridge will positively decode and forward the following accesses on the primary interface to the secondary interface (and conversely.." "0,1" newline bitfld.long 0x8 18. "ISA_EN,ISA Enable. Modifies the response by the bridge to ISA I/O addresses. This applies only to I/O addresses that are enabled by the I/O Base and I/O Limit registers and are in the first 64 KB of I/O address space (0000 0000h to 0000 FFFFh). If this.." "?,KB block" newline bitfld.long 0x8 17. "SERR_EN,SERR# Enable. This bit controls forwarding of ERR_COR ERR_NONFATAL and ERR_FATAL from secondary to primary." "0,1" newline bitfld.long 0x8 16. "PERE,Parity Error Response Enable. This bit controls the logging of poisoned TLPs in the Master Data Parity Error bit in the Secondary Status register." "0,1" newline hexmask.long.byte 0x8 8.--15. 1. "INT_PIN,Interrupt PIN. The Interrupt Pin register register that identifies the legacy interrupt Message(s) the Function uses. Valid values are: - 01h 02h 03h and 04h: map to legacy interrupt Messages for INTA INTB INTC and INTD respectively. - 00h:.." newline hexmask.long.byte 0x8 0.--7. 1. "INT_LINE,Interrupt Line. The Interrupt Line register communicates interrupt line routing information. The register must be implemented by any Function that uses an interrupt pin. Values in this register are programmed by system software and are system.." tree.end tree "PF0_SPCIE_CAP (Secondary PCI Express Capability Structure)" group.long (0x0+0x1A0)++0xF line.long 0x0 "SPCIE_CAP_HEADER_REG,SPCIE Capability Header. For a description of this standard PCIe register. see the PCI Express Specification." hexmask.long.word 0x0 20.--31. 1. "NEXT_OFFSET,Next Capability Offset. For a description of this standard PCIe register field see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky).." hexmask.long.byte 0x0 16.--19. 1. "CAP_VERSION,Capability Version. For a description of this standard PCIe register field see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else.." hexmask.long.word 0x0 0.--15. 1. "EXTENDED_CAP_ID,Secondary PCI Express Extended Capability ID. For a description of this standard PCIe register field see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN.." line.long 0x4 "LINK_CONTROL3_REG,Link Control 3 Register. For a description of this standard PCIe register. see the PCI Express Specification." hexmask.long 0x4 2.--31. 1. "RSVDP_2,Reserved for future use." bitfld.long 0x4 1. "EQ_REQ_INT_EN,Link Equalization Request Interrupt Enable. For a description of this standard PCIe register field see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" "0,1" bitfld.long 0x4 0. "PERFORM_EQ,Perform Equalization. For a description of this standard PCIe register field see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" "0,1" line.long 0x8 "LANE_ERR_STATUS_REG,Lane Error Status Register. For a description of this standard PCIe register. see the PCI Express Specification." hexmask.long 0x8 2.--31. 1. "RSVDP_LANE_ERR_STATUS,Reserved for future use." bitfld.long 0x8 0.--1. "LANE_ERR_STATUS,Lane Error Status Bits per Lane. For a description of this standard PCIe register field see the PCI Express Specification." "0,1,2,3" line.long 0xC "SPCIE_CAP_OFF_0CH_REG,Lane Equalization Control Register for lanes 1 and 0. For a description of this standard PCIe register. see the PCI Express Specification." rbitfld.long 0xC 31. "RSVDP_31,Reserved for future use." "0,1" bitfld.long 0xC 28.--30. "USP_RX_PRESET_HINT1,Upstream Port 8.0 GT/s Receiver Preset Hint 1. The write value is gated with the PCIE_CAP_CROSS_LINK_SUPPORT field of LINK_CAPABILITIES2_REG. For a description of this standard PCIe register field see the PCI Express Specification." "0,1,2,3,4,5,6,7" hexmask.long.byte 0xC 24.--27. 1. "USP_TX_PRESET1,Upstream Port 8.0 GT/s Transmitter Preset 1. The write value is gated with the PCIE_CAP_CROSS_LINK_SUPPORT field of LINK_CAPABILITIES2_REG. For a description of this standard PCIe register field see the PCI Express Specification. Note:.." rbitfld.long 0xC 23. "RSVDP_23,Reserved for future use." "0,1" newline bitfld.long 0xC 20.--22. "DSP_RX_PRESET_HINT1,Downstream Port 8.0 GT/s Receiver Preset Hint 1. For a description of this standard PCIe register field see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if.." "0,1,2,3,4,5,6,7" hexmask.long.byte 0xC 16.--19. 1. "DSP_TX_PRESET1,Downstream Port 8.0 GT/s Transmitter Preset 1. For a description of this standard PCIe register field see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN.." rbitfld.long 0xC 15. "RSVDP_15,Reserved for future use." "0,1" bitfld.long 0xC 12.--14. "USP_RX_PRESET_HINT0,Upstream Port 8.0 GT/s Receiver Preset Hint 0. The write value is gated with the PCIE_CAP_CROSS_LINK_SUPPORT field of LINK_CAPABILITIES2_REG. For a description of this standard PCIe register field see the PCI Express Specification." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0xC 8.--11. 1. "USP_TX_PRESET0,Upstream Port 8.0 GT/s Transmitter Preset 0. The write value is gated with the PCIE_CAP_CROSS_LINK_SUPPORT field of LINK_CAPABILITIES2_REG. For a description of this standard PCIe register field see the PCI Express Specification. Note:.." rbitfld.long 0xC 7. "RSVDP_7,Reserved for future use." "0,1" bitfld.long 0xC 4.--6. "DSP_RX_PRESET_HINT0,Downstream Port 8.0 GT/s Receiver Preset Hint 0. For a description of this standard PCIe register field see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if.." "0,1,2,3,4,5,6,7" hexmask.long.byte 0xC 0.--3. 1. "DSP_TX_PRESET0,Downstream Port 8.0 GT/s Transmitter Preset 0. For a description of this standard PCIe register field see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN.." tree.end tree "PF0_L1SUB_CAP (L1 Substates Capability Structure)" group.long (0x0+0x2E8)++0xF line.long 0x0 "L1SUB_CAP_HEADER_REG,L1 Substates Extended Capability Header. This register provides capbility ID. capability version and next offset value for L1 Substates." hexmask.long.word 0x0 20.--31. 1. "NEXT_OFFSET,Next Capability Offset. This field contains the offset to the next PCI Express Capability structure or 000h if no other items exist in the linked list of Capabilities. For Extended Capabilities implemented in Configuration Space this offset.." hexmask.long.byte 0x0 16.--19. 1. "CAP_VERSION,Capability Version. This field is a PCI-SIG defined version number that indicates the version of the Capability structure present. This field is depends on version of the specification. Note: The access attributes of this field are as.." hexmask.long.word 0x0 0.--15. 1. "EXTENDED_CAP_ID,L1SUB Extended Capability ID. This field is a PCI-SIG defined ID number that indicates the nature and format of the Extended Capability. Extended Capability ID for L1 PM Substates is 001Eh. Note: The access attributes of this field are as.." line.long 0x4 "L1SUB_CAPABILITY_REG,L1 Substates Capability Register. This register provides extended capability of L1 Substates." hexmask.long.byte 0x4 24.--31. 1. "RSVDP_24,Reserved for future use." hexmask.long.byte 0x4 19.--23. 1. "PWR_ON_VALUE_SUPPORT,Port T Power On Value. Along with the Port T_POWER_ON Scale field in the L1 PM Substates Capabilities register sets the time (in us) that this Port requires the port on the opposite side of Link to wait in L1.2.Exit after sampling.." rbitfld.long 0x4 18. "RSVDP_18,Reserved for future use." "0,1" bitfld.long 0x4 16.--17. "PWR_ON_SCALE_SUPPORT,Port T Power On Scale. Specifies the scale used for the Port T_POWER_ON Value field in the L1 PM Substates Capabilities register. Range of values are given below. Required for all Ports for which either the PCI-PM L1.2 Supported bit.." "?,?,?,Reserved" newline hexmask.long.byte 0x4 8.--15. 1. "COMM_MODE_SUPPORT,Port Common Mode Restore Time. Time (in us) required for this Port to re-establish common mode. Required for all Ports for which either the PCI-PM L1.2 Supported bit is Set ASPM L1.2 Supported bit is Set or both are Set otherwise.." rbitfld.long 0x4 5.--7. "RSVDP_5,Reserved for future use." "0,1,2,3,4,5,6,7" bitfld.long 0x4 4. "L1_PMSUB_SUPPORT,L1 PM Substates ECN Supported. When Set this bit indicates that this Port supports L1 PM Substates. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W (sticky)" "0,1" bitfld.long 0x4 3. "L1_1_ASPM_SUPPORT,ASPM L11 Supported. When Set this bit indicates that ASPM L1.1 is supported. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W (sticky)" "0,1" newline bitfld.long 0x4 2. "L1_2_ASPM_SUPPORT,ASPM L12 Supported. When Set this bit indicates that ASPM L1.2 is supported. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W (sticky)" "0,1" bitfld.long 0x4 1. "L1_1_PCIPM_SUPPORT,PCI-PM L11 Supported. When Set this bit indicates that PCI-PM L1.1 is supported and must be Set by all Ports implementing L1 PM Substates. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W (sticky)" "0,1" bitfld.long 0x4 0. "L1_2_PCIPM_SUPPORT,PCI-PM L12 Supported. When Set this bit indicates that PCI-PM L1.2 is supported. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W (sticky)" "0,1" line.long 0x8 "L1SUB_CONTROL1_REG,L1 Substates Control 1 Register. This register provides Controls to extended capability." bitfld.long 0x8 29.--31. "L1_2_TH_SCA,LTR L12 Threshold Scale. This field provides a scale for the value contained within the LTR_L1.2_THRESHOLD_Value.The default value for this field is 000b.Hardware operation is undefined if software writes a Not-Permitted value to this field." "0,1,2,3,4,5,6,7" rbitfld.long 0x8 26.--28. "RSVDP_26,Reserved for future use." "0,1,2,3,4,5,6,7" hexmask.long.word 0x8 16.--25. 1. "L1_2_TH_VAL,LTR L12 Threshold Value. Along with the LTR_L1.2_THRESHOLD_Scale this field indicates the LTR threshold used to determine if entry into L1 results in L1.1 (if enabled) or L1.2 (if enabled). The default value for this field is 00 0000 0000b." hexmask.long.byte 0x8 8.--15. 1. "T_COMMON_MODE,Common Mode Restore Time. Sets value of TCOMMONMODE (in us) which must be used by the Downstream Ports for timing the re-establishment of common mode.This field is of type RsvdP for Upstream Ports. Default value is implementation.." newline hexmask.long.byte 0x8 4.--7. 1. "RSVDP_4,Reserved for future use." bitfld.long 0x8 3. "L1_1_ASPM_EN,ASPM L11 Enable. When Set this bit enables ASPM L1.1.For Ports for which the ASPM L1.1 Supported bit is Clear this bit is permitted to be hardwired to 0.Default value is 0b." "0,1" bitfld.long 0x8 2. "L1_2_ASPM_EN,ASPM L12 Enable. When Set this bit enables ASPM L1.2.For Ports for which the ASPM L1.2 Supported bit is Clear this bit is permitted to be hardwired to 0.Default value is 0b." "0,1" bitfld.long 0x8 1. "L1_1_PCIPM_EN,PCI-PM L11 Enable. When Set this bit enables PCI-PM L1.1. Default value is 0b." "0,1" newline bitfld.long 0x8 0. "L1_2_PCIPM_EN,PCI-PM L12 Enable. When Set this bit enables PCI-PM L1.2.For Ports for which the PCI-PM L1.2 Supported bit is Clear this bit is permitted to be hardwired to 0.Default value is 0b." "0,1" line.long 0xC "L1SUB_CONTROL2_REG,L1 Substates Control 2 Register. This register provides Controls to extended capability." hexmask.long.tbyte 0xC 8.--31. 1. "RSVDP_8,Reserved for future use." hexmask.long.byte 0xC 3.--7. 1. "T_POWER_ON_VALUE,T Power On Value. Along with the T_POWER_ON Scale sets the minimum amount of time (in us) that the Port must wait in L1.2.Exit after sampling CLKREQ# asserted before actively driving the interface.Default value is 00101b. T_POWER_ON is.." rbitfld.long 0xC 2. "RSVDP_2,Reserved for future use." "0,1" bitfld.long 0xC 0.--1. "T_POWER_ON_SCALE,T Power On Scale. Specifies the scale used for T_POWER_ON Value. Range of values are given below. Required for all Ports that support L1.2 otherwise this field is of type RsvdP. This field must only be modified when the ASPM L1.2 Enable.." "?,?,?,Reserved" tree.end tree "PF0_RAS_DES_CAP (RAS D.E.S. Capability Structure (VSEC))" group.long (0x0+0x30C)++0x3 line.long 0x0 "RAS_DES_CAP_HEADER_REG,Vendor-Specific Extended Capability Header. For a description of this standard PCIe register. see the PCI Express Specification." hexmask.long.word 0x0 20.--31. 1. "NEXT_OFFSET,Next Capability Offset. For a description of this standard PCIe register field see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky).." newline hexmask.long.byte 0x0 16.--19. 1. "CAP_VERSION,Capability Version. For a description of this standard PCIe register field see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else.." newline hexmask.long.word 0x0 0.--15. 1. "EXTENDED_CAP_ID,PCI Express Extended Capability ID. For a description of this standard PCIe register field see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then.." rgroup.long (0x4+0x30C)++0x3 line.long 0x0 "VENDOR_SPECIFIC_HEADER_REG,Vendor-Specific Header. For a description of this standard PCIe register. see the PCI Express Specification." hexmask.long.word 0x0 20.--31. 1. "VSEC_LENGTH,VSEC Length. For a description of this standard PCIe register field see the PCI Express Specification." newline hexmask.long.byte 0x0 16.--19. 1. "VSEC_REV,VSEC Rev. For a description of this standard PCIe register field see the PCI Express Specification." newline hexmask.long.word 0x0 0.--15. 1. "VSEC_ID,VSEC ID. For a description of this standard PCIe register field see the PCI Express Specification." group.long (0x8+0x30C)++0x3 line.long 0x0 "EVENT_COUNTER_CONTROL_REG,Event Counter Control. This is a viewport control register. - Setting the EVENT_COUNTER_EVENT_SELECT and EVENT_COUNTER_LANE_SELECT fields in this register determine the Event Counter data returned by the EVENT_COUNTER_DATA_REG.." hexmask.long.byte 0x0 28.--31. 1. "RSVDP_28,Reserved for future use." newline hexmask.long.word 0x0 16.--27. 1. "EVENT_COUNTER_EVENT_SELECT,Event Counter Data Select. This field in conjunction with the EVENT_COUNTER_LANE_SELECT field indexes the Event Counter data returned by the EVENT_COUNTER_DATA_REG register. - 27-24: Group number(4-bit: 0..0x7) - 23-16: Event.." newline hexmask.long.byte 0x0 12.--15. 1. "RSVDP_12,Reserved for future use." newline hexmask.long.byte 0x0 8.--11. 1. "EVENT_COUNTER_LANE_SELECT,Event Counter Lane Select. This field in conjunction with EVENT_COUNTER_EVENT_SELECT indexes the Event Counter data returned by the EVENT_COUNTER_DATA_REG register. - 0x0: Lane0 - 0x1: Lane1 - 0x2: Lane2 - .. - 0xF: Lane15 Note:.." newline rbitfld.long 0x0 7. "EVENT_COUNTER_STATUS,Event Counter Status. This register returns the current value of the Event Counter selected by the following fields: - EVENT_COUNTER_EVENT_SELECT - EVENT_COUNTER_LANE_SELECT Note: This register field is sticky." "0,1" newline rbitfld.long 0x0 5.--6. "RSVDP_5,Reserved for future use." "0,1,2,3" newline bitfld.long 0x0 2.--4. "EVENT_COUNTER_ENABLE,Event Counter Enable. Enables/disables the Event Counter selected by the EVENT_COUNTER_EVENT_SELECT and EVENT_COUNTER_LANE_SELECT fields in this register. By default all event counters are disabled. You can enable/disable a specific.." "no change,per event off,?,?,?,?,?,?" newline bitfld.long 0x0 0.--1. "EVENT_COUNTER_CLEAR,Event Counter Clear. Clears the Event Counter selected by the EVENT_COUNTER_EVENT_SELECT and EVENT_COUNTER_LANE_SELECT fields in this register. You can clear the value of a specific Event Counter by writing the 'per clear' code and.." "no change,per clear,?,?" rgroup.long (0xC+0x30C)++0x3 line.long 0x0 "EVENT_COUNTER_DATA_REG,Event Counter Data. This viewport register returns the data selected by the following fields: - EVENT_COUNTER_EVENT_SELECT in EVENT_COUNTER_CONTROL_REG - EVENT_COUNTER_LANE_SELECT in EVENT_COUNTER_CONTROL_REG For more details. see.." hexmask.long 0x0 0.--31. 1. "EVENT_COUNTER_DATA,Event Counter Data. This register returns the data selected by the following fields: - EVENT_COUNTER_EVENT_SELECT in EVENT_COUNTER_CONTROL_REG - EVENT_COUNTER_LANE_SELECT in EVENT_COUNTER_CONTROL_REG Note: This register field is sticky." group.long (0x10+0x30C)++0x3 line.long 0x0 "TIME_BASED_ANALYSIS_CONTROL_REG,Time-based Analysis Control. Used for controlling the measurement of RX/TX data throughput and time spent in each low-power LTSSM state. For more details. see the RAS DES section in the Core Operations chapter of the.." hexmask.long.byte 0x0 24.--31. 1. "TIME_BASED_REPORT_SELECT,Time-based Report Select. Selects what type of data is measured for the selected duration (TIME_BASED_DURATION_SELECT) and returned in TIME_BASED_ANALYSIS_DATA. Each type of data is measured using one of three types of units: -.." newline hexmask.long.byte 0x0 16.--23. 1. "RSVDP_16,Reserved for future use." newline hexmask.long.byte 0x0 8.--15. 1. "TIME_BASED_DURATION_SELECT,Time-based Duration Select. Selects the duration of time-based analysis. When 'manual control' is selected and TIMER_START is set to '1' this analysis never stops until TIMER_STOP is set to '0'. - 0x0: Manual control - 0x1:.." newline hexmask.long.byte 0x0 1.--7. 1. "RSVDP_1,Reserved for future use." newline bitfld.long 0x0 0. "TIMER_START,Timer Start. - 1: Start/Restart - 0: Stop This bit will be cleared automatically when the measurement is finished. Note: The app_ras_des_tba_ctrl input also sets the contents of this field and controls the measurement start/stop. Note: This.." "Stop,Start/Restart" rgroup.long (0x14+0x30C)++0x7 line.long 0x0 "TIME_BASED_ANALYSIS_DATA_REG,Time-based Analysis Data. Contains the measurement results of RX/TX data throughput and time spent in each low-power LTSSM state. This viewport register returns the data selected by the TIME_BASED_REPORT_SELECT field in.." hexmask.long 0x0 0.--31. 1. "TIME_BASED_ANALYSIS_DATA,Time Based Analysis Data. This register returns the data selected by the TIME_BASED_REPORT_SELECT field in TIME_BASED_ANALYSIS_CONTROL_REG. The results are cleared when next measurement starts. Note: This register field is sticky." line.long 0x4 "TIME_BASED_ANALYSIS_DATA_63_32_REG,Upper 32 bits of Time-based Analysis Data. This viewport register returns the data selected by the TIME_BASED_REPORT_SELECT field in TIME_BASED_ANALYSIS_CONTROL_REG. For more details. see the RAS DES section in the Core.." hexmask.long 0x4 0.--31. 1. "TIME_BASED_ANALYSIS_DATA_63_32,Upper 32 bits of Time Based Analysis Data. Note: This register field is sticky." group.long (0x30+0x30C)++0x5F line.long 0x0 "EINJ_ENABLE_REG,Error Injection Enable. Each type of error insertion is enabled by the corresponding bit in this register. The specific injection controls for each type of error are defined in the following registers: - 0: CRC Error: EINJ0_CRC_REG - 1:.." hexmask.long 0x0 7.--31. 1. "RSVDP_7,Reserved for future use." newline bitfld.long 0x0 6. "ERROR_INJECTION6_ENABLE,Error Injection6 Enable (Specific TLP Error). Enables insertion of errors into the packets that you select. You can set this bit to '1' when you have disabled RAS datapath protection (DP) by setting CX_RASDP = CX_RASDP_RAM_PROT.." "0,1" newline bitfld.long 0x0 5. "ERROR_INJECTION5_ENABLE,Error Injection5 Enable (TLP Duplicate/Nullify Error). Enables insertion of duplicate/nullified TLPs. For more details see the EINJ5_SP_TLP_REG register. Note: This register field is sticky." "0,1" newline bitfld.long 0x0 4. "ERROR_INJECTION4_ENABLE,Error Injection4 Enable (FC Credit Update Error). Enables insertion of errors into UpdateFCs. For more details see the EINJ4_FC_REG register. Note: This register field is sticky." "0,1" newline bitfld.long 0x0 3. "ERROR_INJECTION3_ENABLE,Error Injection3 Enable (Symbol DataK Mask Error or Sync Header Error). Enables DataK masking of special symbols or the breaking of the sync header. For more details see the EINJ3_SYMBOL_REG register. Note: This register field is.." "0,1" newline bitfld.long 0x0 2. "ERROR_INJECTION2_ENABLE,Error Injection2 Enable (DLLP Error). Enables insertion of DLLP errors. For more details see the EINJ2_DLLP_REG register. Note: This register field is sticky." "0,1" newline bitfld.long 0x0 1. "ERROR_INJECTION1_ENABLE,Error Injection1 Enable (Sequence Number Error). Enables insertion of errors into sequence numbers. For more details see the EINJ1_SEQNUM_REG register. Note: This register field is sticky." "0,1" newline bitfld.long 0x0 0. "ERROR_INJECTION0_ENABLE,Error Injection0 Enable (CRC Error). Enables insertion of errors into various CRC. For more details see the EINJ0_CRC_REG register. Note: This register field is sticky." "0,1" line.long 0x4 "EINJ0_CRC_REG,Error Injection Control 0 (CRC Error). Controls the insertion of errors into the CRC. and parity of ordered sets for the selected type of the packets as follows: - LCRC. Bad TLP will be detected at the receiver side; receiver responds with.." hexmask.long.tbyte 0x4 12.--31. 1. "RSVDP_12,Reserved for future use." newline hexmask.long.byte 0x4 8.--11. 1. "EINJ0_CRC_TYPE,Error injection type. Selects the type of CRC error to be inserted. Tx Path - 0000b: New TLP's LCRC error injection - 0001b: 16bCRC error injection of ACK/NAK DLLP - 0010b: 16bCRC error injection of Update-FC DLLP - 0011b: New TLP's ECRC.." newline hexmask.long.byte 0x4 0.--7. 1. "EINJ0_COUNT,Error injection count. Indicates the number of errors. This register is decremented when the errors have been inserted. - If the counter value is 0x01 and error is inserted ERROR_INJECTION0_ENABLE in EINJ_ENABLE_REG returns 0b. - If the.." line.long 0x8 "EINJ1_SEQNUM_REG,Error Injection Control 1 (Sequence Number Error). Controls the sequence number of the specific TLPs and ACK/NAK DLLPs. Data Link Protocol Error will be detected at the Rx side of ACK/NAL DLLPs when one of these conditions is true: -.." rbitfld.long 0x8 29.--31. "RSVDP_29,Reserved for future use." "0,1,2,3,4,5,6,7" newline hexmask.long.word 0x8 16.--28. 1. "EINJ1_BAD_SEQNUM,Bad sequence number. Indicates the value to add/subtract from the naturally-assigned sequence numbers. This value is represented by two's complement. - 0x0FFF: +4095 - .. - 0x0002: +2 - 0x0001: +1 - 0x0000: 0 - 0x1FFF: -1 - 0x1FFE: -2 -.." newline hexmask.long.byte 0x8 9.--15. 1. "RSVDP_9,Reserved for future use." newline bitfld.long 0x8 8. "EINJ1_SEQNUM_TYPE,Sequence number type. Selects the type of sequence number. - 0b: Insertion of New TLP's SEQ# error - 1b: Insertion of ACK/NAK DLLP's SEQ# Error Note: This register field is sticky." "0,1" newline hexmask.long.byte 0x8 0.--7. 1. "EINJ1_COUNT,Error injection count. Indicates the number of errors. This register is decremented as the errors are being inserted. - If the counter value is 0x01 and error is inserted ERROR_INJECTION1_ENABLE in EINJ_ENABLE_REG returns '0'. - If the.." line.long 0xC "EINJ2_DLLP_REG,Error Injection Control 2 (DLLP Error). Controls the transmission of DLLPs and inserts the following errors: - If 'ACK/NAK DLLP's transmission block' is selected. replay timeout error will occur at the transmitter of the TLPs and then Data.." hexmask.long.tbyte 0xC 10.--31. 1. "RSVDP_10,Reserved for future use." newline bitfld.long 0xC 8.--9. "EINJ2_DLLP_TYPE,DLLP Type. Selects the type of DLLP errors to be inserted. - 00b: ACK/NAK DLLP's transmission block - 01b: Update FC DLLP's transmission block - 10b: Always Transmission for NAK DLLP - 11b: Reserved Note: This register field is sticky." "0,1,2,3" newline hexmask.long.byte 0xC 0.--7. 1. "EINJ2_COUNT,Error injection count. Indicates the number of errors. This register is decremented as the errors are being inserted. - If the counter value is 0x01 and the error is inserted ERROR_INJECTION2_ENABLE in EINJ_ENABLE_REG returns '0'. - If the.." line.long 0x10 "EINJ3_SYMBOL_REG,Error Injection Control 3 (Symbol Error). When 8b/10b encoding is used. this register controls error insertion into the special (K code) symbols. - If TS1/TS2/FTS/E-Idle/SKP is selected. it affects whole of the ordered set. It might.." hexmask.long.tbyte 0x10 11.--31. 1. "RSVDP_11,Reserved for future use." newline bitfld.long 0x10 8.--10. "EINJ3_SYMBOL_TYPE,Error Type. 8b/10b encoding - Mask K symbol. It is not supported to insert errors into the first ordered-set after exiting from TxElecIdle when CX_FREQ_STEP_EN has been enabled. - 000b: Reserved - 001b: COM/PAD(TS1 Order set) - 010b:.." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x10 0.--7. 1. "EINJ3_COUNT,Error injection count. Indicates the number of errors. This register is decremented as the errors are being inserted. - If the counter value is 0x01 and error is inserted ERROR_INJECTION3_ENABLE in EINJ_ENABLE_REG returns '0'. - If the.." line.long 0x14 "EINJ4_FC_REG,Error Injection Control 4 (FC Credit Error). Controls error insertion into the credit value in the UpdateFCs. It is possible to insert errors for any of the following types: - Posted TLP Header credit - Non-Posted TLP Header credit -.." rbitfld.long 0x14 29.--31. "RSVDP_29,Reserved for future use." "0,1,2,3,4,5,6,7" newline hexmask.long.word 0x14 16.--28. 1. "EINJ4_BAD_UPDFC_VALUE,Bad update-FC credit value. Indicates the value to add/subtract from the UpdateFC credit. This value is represented by two's complement. - 0x0FFF: +4095 - .. - 0x0002: +2 - 0x0001: +1 - 0x0000: 0 - 0x1FFF: -1 - 0x1FFE: -2 - .. -.." newline rbitfld.long 0x14 15. "RSVDP_15,Reserved for future use." "0,1" newline bitfld.long 0x14 12.--14. "EINJ4_VC_NUMBER,VC Number. Indicates target VC Number. Note: This register field is sticky." "0,1,2,3,4,5,6,7" newline rbitfld.long 0x14 11. "RSVDP_11,Reserved for future use." "0,1" newline bitfld.long 0x14 8.--10. "EINJ4_UPDFC_TYPE,Update-FC type. Selects the credit type. - 000b: Posted TLP Header Credit value control - 001b: Non-Posted TLP Header Credit value control - 010b: Completion TLP Header Credit value control - 011b: Reserved - 100b: Posted TLP Data Credit.." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x14 0.--7. 1. "EINJ4_COUNT,Error injection count. Indicates the number of errors. This register is decremented as the errors are being inserted. - If the counter value is 0x01 and error is inserted ERROR_INJECTION4_ENABLE in EINJ_ENABLE_REG returns '0'. - If the.." line.long 0x18 "EINJ5_SP_TLP_REG,Error Injection Control 5 (Specific TLP Error). Controls the generation of specified TLPs. Correctable errors will occur which will be fixed by the PCIe protocol. - For Duplicate TLP. the controller initiates Data Link Retry by handling.." hexmask.long.tbyte 0x18 9.--31. 1. "RSVDP_9,Reserved for future use." newline bitfld.long 0x18 8. "EINJ5_SPECIFIED_TLP,Specified TLP. Selects the specified TLP to be inserted. - 0: Generates duplicate TLPs by handling ACK DLLP as NAK DLLP. - 1: Generates Nullified TLP (Original TLP will be stored in retry buffer). Note: This register field is sticky." "Generates duplicate TLPs by handling ACK DLLP as..,Generates Nullified TLP" newline hexmask.long.byte 0x18 0.--7. 1. "EINJ5_COUNT,Error injection count. Indicates the number of errors. This register is decremented as the errors are being inserted. - If the counter value is 0x01 and error is inserted ERROR_INJECTION5_ENABLE in EINJ_ENABLE_REG returns '0'. - If the.." line.long 0x1C "EINJ6_COMPARE_POINT_H0_REG,Error Injection Control 6 (Compare Point Header DWORD #0). Program this register for the 1st DWORD of TLP header/prefix. It is necessary to carefully consider the endianness when you program this register. Bits [31:0] =.." hexmask.long 0x1C 0.--31. 1. "EINJ6_COMPARE_POINT_H0,Packet Compare Point: 1st DWORD. Specifies which Tx TLP header DWORD#0 bits to compare with the corresponding bits in the Packet Compare Value registers (EINJ6_COMPARE_VALUE*). When all specified bits (in the Tx TLP header and.." line.long 0x20 "EINJ6_COMPARE_POINT_H1_REG,Error Injection Control 6 (Compare Point Header DWORD #1). Program this register for the 2nd DWORD of TLP header/prefix. It is necessary to carefully consider the endianness when you program this register. Bits [31:0] =.." hexmask.long 0x20 0.--31. 1. "EINJ6_COMPARE_POINT_H1,Packet Compare Point: 2nd DWORD. Specifies which Tx TLP header DWORD#1 bits to compare with the corresponding bits in the Packet Compare Value registers (EINJ6_COMPARE_VALUE*). When all specified bits (in the Tx TLP header and.." line.long 0x24 "EINJ6_COMPARE_POINT_H2_REG,Error Injection Control 6 (Compare Point Header DWORD #2). Program this register for the 3rd DWORD of TLP header/prefix. It is necessary to carefully consider the endianness when you program this register. Bits [31:0] =.." hexmask.long 0x24 0.--31. 1. "EINJ6_COMPARE_POINT_H2,Packet Compare Point: 3rd DWORD. Specifies which Tx TLP header DWORD#2 bits to compare with the corresponding bits in the Packet Compare Value registers (EINJ6_COMPARE_VALUE*). When all specified bits (in the Tx TLP header and.." line.long 0x28 "EINJ6_COMPARE_POINT_H3_REG,Error Injection Control 6 (Compare Point Header DWORD #3). Program this register for the 4th DWORD of TLP header/prefix. It is necessary to carefully consider the endianness when you program this register. Bits [31:0] =.." hexmask.long 0x28 0.--31. 1. "EINJ6_COMPARE_POINT_H3,Packet Compare Point: 4th DWORD. Specifies which Tx TLP header DWORD#3 bits to compare with the corresponding bits in the Packet Compare Value registers (EINJ6_COMPARE_VALUE*). When all specified bits (in the Tx TLP header and.." line.long 0x2C "EINJ6_COMPARE_VALUE_H0_REG,Error Injection Control 6 (Compare Value Header DWORD #0). Program this register for the 1st DWORD of TLP header/prefix. It is necessary to carefully consider the endianness when you program this register. Bits [31:0] =.." hexmask.long 0x2C 0.--31. 1. "EINJ6_COMPARE_VALUE_H0,Packet Compare Value: 1st DWORD. Specifies the value to compare against Tx the TLP header DWORD#0 bits specified in the Packet Compare Point registers (EINJ6_COMPARE_POINT*). Note: This register field is sticky." line.long 0x30 "EINJ6_COMPARE_VALUE_H1_REG,Error Injection Control 6 (Compare Value Header DWORD #1). Program this register for the 2nd DWORD of TLP header/prefix. It is necessary to carefully consider the endianness when you program this register. Bits [31:0] =.." hexmask.long 0x30 0.--31. 1. "EINJ6_COMPARE_VALUE_H1,Packet Compare Value: 2nd DWORD. Specifies the value to compare against Tx the TLP header DWORD#1 bits specified in the Packet Compare Point registers (EINJ6_COMPARE_POINT*). Note: This register field is sticky." line.long 0x34 "EINJ6_COMPARE_VALUE_H2_REG,Error Injection Control 6 (Compare Value Header DWORD #2). Program this register for the 3rd DWORD of TLP header/prefix. It is necessary to carefully consider the endianness when you program this register. Bits [31:0] =.." hexmask.long 0x34 0.--31. 1. "EINJ6_COMPARE_VALUE_H2,Packet Compare Value: 3rd DWORD. Specifies the value to compare against Tx the TLP header DWORD#2 bits specified in the Packet Compare Point registers (EINJ6_COMPARE_POINT*). Note: This register field is sticky." line.long 0x38 "EINJ6_COMPARE_VALUE_H3_REG,Error Injection Control 6 (Compare Value Header DWORD #3). Program this register for the 4th DWORD of TLP header/prefix. It is necessary to carefully consider the endianness when you program this register. Bits [31:0] =.." hexmask.long 0x38 0.--31. 1. "EINJ6_COMPARE_VALUE_H3,Packet Compare Value: 4th DWORD. Specifies the value to compare against Tx the TLP header DWORD#3 bits specified in the Packet Compare Point registers (EINJ6_COMPARE_POINT*). Note: This register field is sticky." line.long 0x3C "EINJ6_CHANGE_POINT_H0_REG,Error Injection Control 6 (Change Point Header DWORD #0). Program this register for the 1st DWORD of TLP header/prefix. It is necessary to carefully consider the endianness when you program this register. Bits [31:0] =.." hexmask.long 0x3C 0.--31. 1. "EINJ6_CHANGE_POINT_H0,Packet Change Point: 1st DWORD. Specifies which Tx TLP header DWORD#0 bits to replace with the corresponding bits in the Packet Change Value registers (EINJ6_CHANGE_VALUE*). Note: This register field is sticky." line.long 0x40 "EINJ6_CHANGE_POINT_H1_REG,Error Injection Control 6 (Change Point Header DWORD #1). Program this register for the 2nd DWORD of TLP header/prefix. It is necessary to carefully consider the endianness when you program this register. Bits [31:0] =.." hexmask.long 0x40 0.--31. 1. "EINJ6_CHANGE_POINT_H1,Packet Change Point: 2nd DWORD. Specifies which Tx TLP header DWORD#1 bits to replace with the corresponding bits in the Packet Change Value registers (EINJ6_CHANGE_VALUE*). Note: This register field is sticky." line.long 0x44 "EINJ6_CHANGE_POINT_H2_REG,Error Injection Control 6 (Change Point Header DWORD #2). Program this register for the 3rd DWORD of TLP header/prefix. It is necessary to carefully consider the endianness when you program this register. Bits [31:0] =.." hexmask.long 0x44 0.--31. 1. "EINJ6_CHANGE_POINT_H2,Packet Change Point: 3rd DWORD. Specifies which Tx TLP header DWORD#2 bits to replace with the corresponding bits in the Packet Change Value registers (EINJ6_CHANGE_VALUE*). Note: This register field is sticky." line.long 0x48 "EINJ6_CHANGE_POINT_H3_REG,Error Injection Control 6 (Change Point Header DWORD #3). Program this register for the 4th DWORD of TLP header/prefix. It is necessary to carefully consider the endianness when you program this register. Bits [31:0] =.." hexmask.long 0x48 0.--31. 1. "EINJ6_CHANGE_POINT_H3,Packet Change Point: 4th DWORD. Specifies which Tx TLP header DWORD#3 bits to replace with the corresponding bits in the Packet Change Value registers (EINJ6_CHANGE_VALUE*). Note: This register field is sticky." line.long 0x4C "EINJ6_CHANGE_VALUE_H0_REG,Error Injection Control 6 (Change Value Header DWORD #0). Program this register for the 1st DWORD of TLP header/prefix. It is necessary to carefully consider the endianness when you program this register. Bits [31:0] =.." hexmask.long 0x4C 0.--31. 1. "EINJ6_CHANGE_VALUE_H0,Packet Change Value: 1st DWORD. Specifies replacement values for the Tx TLP header DWORD#0 bits defined in the Packet Change Point registers (EINJ6_CHANGE_POINT*). Only applies when the EINJ6_INVERTED_CONTROL field in EINJ6_TLP_REG.." line.long 0x50 "EINJ6_CHANGE_VALUE_H1_REG,Error Injection Control 6 (Change Value Header DWORD #1). Program this register for the 2nd DWORD of TLP header/prefix. It is necessary to carefully consider the endianness when you program this register. Bits [31:0] =.." hexmask.long 0x50 0.--31. 1. "EINJ6_CHANGE_VALUE_H1,Packet Change Value: 2nd DWORD. Specifies replacement values for the Tx TLP header DWORD#1 bits defined in the Packet Change Point registers (EINJ6_CHANGE_POINT*). Only applies when the EINJ6_INVERTED_CONTROL field in EINJ6_TLP_REG.." line.long 0x54 "EINJ6_CHANGE_VALUE_H2_REG,Error Injection Control 6 (Change Value Header DWORD #2). Program this register for the 3rd DWORD of TLP header/prefix. It is necessary to carefully consider the endianness when you program this register. Bits [31:0] =.." hexmask.long 0x54 0.--31. 1. "EINJ6_CHANGE_VALUE_H2,Packet Change Value: 3rd DWORD. Specifies replacement values for the Tx TLP header DWORD#2 bits defined in the Packet Change Point registers (EINJ6_CHANGE_POINT*). Only applies when the EINJ6_INVERTED_CONTROL field in EINJ6_TLP_REG.." line.long 0x58 "EINJ6_CHANGE_VALUE_H3_REG,Error Injection Control 6 (Change Value Header DWORD #3). Program this register for the 4th DWORD of TLP header/prefix. It is necessary to carefully consider the endianness when you program this register. Bits [31:0] =.." hexmask.long 0x58 0.--31. 1. "EINJ6_CHANGE_VALUE_H3,Packet Change Value: 4th DWORD. Specifies replacement values for the Tx TLP header DWORD#3 bits defined in the Packet Change Point registers (EINJ6_CHANGE_POINT*). Only applies when the EINJ6_INVERTED_CONTROL field in EINJ6_TLP_REG.." line.long 0x5C "EINJ6_TLP_REG,Error Injection Control 6 (Packet Error). The Packet Compare Point registers (EINJ6_COMPARE_POINT*) specify which Tx TLP header bits to compare with the corresponding bits in the Packet Compare Value registers (EINJ6_COMPARE_VALUE*). When.." hexmask.long.tbyte 0x5C 12.--31. 1. "RSVDP_12,Reserved for future use." newline bitfld.long 0x5C 9.--11. "EINJ6_PACKET_TYPE,Packet type. Selects the TLP packets to inject errors into. - 0: TLP Header - 1: TLP Prefix 1st 4-DWORDs - 2: TLP Prefix 2nd -DWORDs - Else: Reserved Note: This register field is sticky." "TLP Header,TLP Prefix 1st 4-DWORDs,TLP Prefix 2nd -DWORDs,?,?,?,?,?" newline bitfld.long 0x5C 8. "EINJ6_INVERTED_CONTROL,Inverted Error Injection Control. - 0: EINJ6_CHANGE_VALUE_H[0/1/2/3] is used to replace bits specified by EINJ6_CHANGE_POINT_H[0/1/2/3]. - 1: EINJ6_CHANGE_VALUE_H[0/1/2/3] is ignored and inverts bits specified by.." "EINJ6_CHANGE_VALUE_H[0/1/2/3] is used to replace..,EINJ6_CHANGE_VALUE_H[0/1/2/3] is ignored and.." newline hexmask.long.byte 0x5C 0.--7. 1. "EINJ6_COUNT,Error Injection Count. Indicates the number of errors to insert. This counter is decremented while errors are been inserted. - If the counter value is 0x01 and error is inserted ERROR_INJECTION6_ENABLE in EINJ_ENABLE_REG returns '0'. - If.." group.long (0xA0+0x30C)++0x7 line.long 0x0 "SD_CONTROL1_REG,Silicon Debug Control 1. For more details. see the RAS DES section in the Core Operations chapter of the Databook." hexmask.long.byte 0x0 24.--31. 1. "RSVDP_24,Reserved for future use." newline bitfld.long 0x0 22.--23. "LOW_POWER_INTERVAL,Low Power Entry Interval Time. Interval Time that the controller starts monitoring RXELECIDLE signal after L0s/L1/L2 entry. You should set the value according to the latency from receiving EIOS to RXELECIDLE assertion at the PHY. -.." "0,1,2,3" newline bitfld.long 0x0 20.--21. "TX_EIOS_NUM,Number of Tx EIOS. This register sets the number of transmit EIOS for L0s/L1 entry and Disable/Loopback/Hot-reset exit. The controller selects the greater value between this register and the value defined by the PCI-SIG specification. 2.5GT/s.." "0,1,2,3" newline rbitfld.long 0x0 17.--19. "RSVDP_17,Reserved for future use." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 16. "FORCE_DETECT_LANE_EN,Force Detect Lane Enable. When this bit is set the controller ignores receiver detection from PHY during LTSSM Detect state and uses FORCE_DETECT_LANE. Note: This register field is sticky." "0,1" newline hexmask.long.word 0x0 0.--15. 1. "FORCE_DETECT_LANE,Force Detect Lane. When the FORCE_DETECT_LANE_EN field is set the controller ignores receiver detection from PHY during LTSSM Detect state and uses this value instead. - 0: Lane0 - 1: Lane1 - 2: Lane2 - .. - 15: Lane15 Note: This.." line.long 0x4 "SD_CONTROL2_REG,Silicon Debug Control 2. For more details. see the RAS DES section in the Core Operations chapter of the Databook." hexmask.long.word 0x4 17.--31. 1. "RSVDP_17,Reserved for future use." newline bitfld.long 0x4 16. "FRAMING_ERR_RECOVERY_DISABLE,Framing Error Recovery Disable. This bit disables a transition to Recovery state when a Framing Error is occurred. Note: This register field is sticky." "0,1" newline hexmask.long.byte 0x4 11.--15. 1. "RSVDP_11,Reserved for future use." newline bitfld.long 0x4 10. "DIRECT_LPBKSLV_TO_EXIT,Direct Loopback Slave To Exit. When this bit is set and the LTSSM is in Loopback Slave Active State the LTSSM transitions to Loopback Slave Exit state. Note: This register field is sticky." "0,1" newline bitfld.long 0x4 9. "DIRECT_POLCOMP_TO_DETECT,Direct Polling.Compliance to Detect. When this bit is set and the LTSSM is in Polling Compliance State the LTSSM transitions to Detect state. Note: This register field is sticky." "0,1" newline bitfld.long 0x4 8. "DIRECT_RECIDLE_TO_CONFIG,Direct Recovery.Idle to Configuration. When this bit is set and the LTSSM is in Recovery Idle State the LTSSM transitions to Configuration state. Note: This register field is sticky." "0,1" newline hexmask.long.byte 0x4 3.--7. 1. "RSVDP_3,Reserved for future use." newline bitfld.long 0x4 2. "NOACK_FORCE_LINKDOWN,Force LinkDown. When this bit is set and the controller detects REPLY_NUM rolling over 4 times the LTSSM transitions to Detect State. Note: This register field is sticky." "0,1" newline bitfld.long 0x4 1. "RECOVERY_REQUEST,Recovery Request. When this bit is set to '1' in L0 or L0s the LTSSM starts transitioning to Recovery State. This request does not cause a speed change or re-equalization." "0,1" newline bitfld.long 0x4 0. "HOLD_LTSSM,Hold and Release LTSSM. For as long as this register is '1' the controller stays in the current LTSSM. Note: This register field is sticky." "0,1" group.long (0xB0+0x30C)++0xB line.long 0x0 "SD_STATUS_L1LANE_REG,Silicon Debug Status(Layer1 Per-lane). This viewport register returns the data selected by the following field: - LANE_SELECT in SD_STATUS_L1LANE_REG For more details. see the RAS DES section in the Core Operations chapter of the.." hexmask.long.byte 0x0 24.--31. 1. "DESKEW_POINTER,Deskew Pointer. Indicates Deskew pointer of internal Deskew buffer of selected lane number(LANE_SELECT). Note: This register field is sticky." newline rbitfld.long 0x0 21.--23. "RSVDP_21,Reserved for future use." "0,1,2,3,4,5,6,7" newline rbitfld.long 0x0 20. "PIPE_TXELECIDLE,PIPE:TxElecIdle. Indicates PIPE TXELECIDLE signal of selected lane number(LANE_SELECT). Note: This register field is sticky." "0,1" newline rbitfld.long 0x0 19. "PIPE_RXELECIDLE,PIPE:RxElecIdle. Indicates PIPE RXELECIDLE signal of selected lane number(LANE_SELECT). Note: This register field is sticky." "0,1" newline rbitfld.long 0x0 18. "PIPE_RXVALID,PIPE:RxValid. Indicates PIPE RXVALID signal of selected lane number(LANE_SELECT). Note: This register field is sticky." "0,1" newline rbitfld.long 0x0 17. "PIPE_DETECT_LANE,PIPE:Detect Lane. Indicates whether PHY indicates receiver detection or not on selected lane number(LANE_SELECT). Note: This register field is sticky." "0,1" newline rbitfld.long 0x0 16. "PIPE_RXPOLARITY,PIPE:RxPolarity. Indicates PIPE RXPOLARITY signal of selected lane number(LANE_SELECT). Note: This register field is sticky." "0,1" newline hexmask.long.word 0x0 4.--15. 1. "RSVDP_4,Reserved for future use." newline hexmask.long.byte 0x0 0.--3. 1. "LANE_SELECT,Lane Select. Lane Select register for Silicon Debug Status Register of Layer1-PerLane. - 0x0: Lane0 - 0x1: Lane1 - 0x2: Lane2 - .. - 0xF: Lane15 Note: This register field is sticky." line.long 0x4 "SD_STATUS_L1LTSSM_REG,Silicon Debug Status(Layer1 LTSSM). For more details. see the RAS DES section in the Core Operations chapter of the Databook." hexmask.long.word 0x4 16.--31. 1. "LTSSM_VARIABLE,LTSSM Variable. Indicates internal LTSSM variables defined in the PCI Express Base Specification. C-PCIe Mode: - 0: directed_speed_change - 1: changed_speed_recovery - 2: successful_speed_negotiation - 3: upconfigure_capable; Set to '1' if.." newline rbitfld.long 0x4 15. "LANE_REVERSAL,Lane Reversal Operation. Receiver detected lane reversal. This field is only valid in the L0 LTSSM state. Note: This register field is sticky." "0,1" newline hexmask.long.byte 0x4 11.--14. 1. "RSVDP_11,Reserved for future use." newline rbitfld.long 0x4 8.--10. "PIPE_POWER_DOWN,PIPE:PowerDown. Indicates PIPE PowerDown signal. Note: This register field is sticky." "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 7. "FRAMING_ERR,Framing Error. Indicates Framing Error detection status." "0,1" newline hexmask.long.byte 0x4 0.--6. 1. "FRAMING_ERR_PTR,First Framing Error Pointer. Identifies the first Framing Error using the following encoding. The field contents are only valid value when FRAMING_ERR =1. Received Unexpected Framing Token - 01h: When non- STP/SDP/IDL Token was received.." line.long 0x8 "SD_STATUS_PM_REG,Silicon Debug Status(PM). For more details. see the RAS DES section in the Core Operations chapter of the Databook." hexmask.long.byte 0x8 24.--31. 1. "RSVDP_24,Reserved for future use." newline hexmask.long.byte 0x8 16.--23. 1. "LATCHED_NFTS,Latched N_FTS. Indicates the value of N_FTS in the received TS Ordered Sets from the Link Partner Note: This register field is sticky." newline rbitfld.long 0x8 13.--15. "L1SUB_STATE,L1Sub State. Indicates internal state machine of L1Sub state. - 0h: S_L1_U : idle state - 1h: S_L1_0 : wait for aux_clk_active - 2h: S_L1_0_WAIT4_ACK : wait for pclkack - 3h: S_L1_0_WAIT4_CLKREQ : wait for clkreq - 4h: S_L1_N_ENTRY : check.." "wait for aux_clk_active,?,?,?,?,?,?,?" newline bitfld.long 0x8 12. "PME_RESEND_FLAG,PME Re-send flag. When the DUT sends a PM_PME message TLP the DUT sets PME_Status bit. If host software does not clear PME_Status bit for 100ms(+50%/-5%) the DUT resends the PM_PME Message. This bit indicates that a PM_PME was resent." "0,1" newline hexmask.long.byte 0x8 8.--11. 1. "INTERNAL_PM_SSTATE,Internal PM State(Slave). Indicates internal state machine of Power Management Slave controller. - 0h: S_IDLE - 1h: S_RESPOND_NAK - 2h: S_BLOCK_TLP - 3h: S_WAIT_LAST_TLP_ACK - 4h: S_WAIT_EIDLE - 5h: S_LINK_ENTR_L1 - 6h: S_L1 - 7h:.." newline rbitfld.long 0x8 5.--7. "RSVDP_5,Reserved for future use." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x8 0.--4. 1. "INTERNAL_PM_MSTATE,Internal PM State(Master). Indicates internal state machine of Power Management Master controller. - 00h: IDLE - 01h: L0 - 02h: L0S - 03h: ENTER_L0S - 04h: L0S_EXIT - 05h: WAIT_PMCSR_CPL_SENT - 08h: L1 - 09h: L1_BLOCK_TLP - 0Ah:.." rgroup.long (0xBC+0x30C)++0x3 line.long 0x0 "SD_STATUS_L2_REG,Silicon Debug Status(Layer2). For more details. see the RAS DES section in the Core Operations chapter of the Databook." hexmask.long.byte 0x0 28.--31. 1. "RSVDP_28,Reserved for future use." newline bitfld.long 0x0 27. "FC_INIT2,FC_INIT2. Indicates the controller is in FC_INIT2(VC0) state. Note: This register field is sticky." "0,1" newline bitfld.long 0x0 26. "FC_INIT1,FC_INIT1. Indicates the controller is in FC_INIT1(VC0) state. Note: This register field is sticky." "0,1" newline bitfld.long 0x0 24.--25. "DLCMSM,DLCMSM. Indicates the current DLCMSM. - 00b: DL_INACTIVE - 01b: DL_FC_INIT - 11b: DL_ACTIVE Note: This register field is sticky." "0,1,2,3" newline hexmask.long.word 0x0 12.--23. 1. "RX_ACK_SEQ_NO,Tx Ack Sequence Number. Indicates ACKD_SEQ which is updated by receiving ACK/NAK DLLP. Note: This register field is sticky." newline hexmask.long.word 0x0 0.--11. 1. "TX_TLP_SEQ_NO,Tx Tlp Sequence Number. Indicates next transmit sequence number for transmit TLP. Note: This register field is sticky." group.long (0xC0+0x30C)++0x7 line.long 0x0 "SD_STATUS_L3FC_REG,Silicon Debug Status(Layer3 FC). The CREDIT_DATA[0/1] fields in this viewport register return the data for the VC and TLP Type selected by the following fields: - CREDIT_SEL_VC - CREDIT_SEL_CREDIT_TYPE - CREDIT_SEL_TLP_TYPE -.." hexmask.long.word 0x0 20.--31. 1. "CREDIT_DATA1,Credit Data1. Current FC credit data selected by the CREDIT_SEL_VC CREDIT_SEL_CREDIT_TYPE CREDIT_SEL_TLP_TYPE and CREDIT_SEL_HD viewport-select fields. - Rx: Credit Allocated Value - Tx: Credit Limit Value. This value is valid when.." newline hexmask.long.word 0x0 8.--19. 1. "CREDIT_DATA0,Credit Data0. Current FC credit data selected by the CREDIT_SEL_VC CREDIT_SEL_CREDIT_TYPE CREDIT_SEL_TLP_TYPE and CREDIT_SEL_HD viewport-select fields. - Rx: Credit Received Value - Tx: Credit Consumed Value Note: This register field is.." newline rbitfld.long 0x0 7. "RSVDP_7,Reserved for future use." "0,1" newline bitfld.long 0x0 6. "CREDIT_SEL_HD,Credit Select(HeaderData). This field in conjunction with the CREDIT_SEL_VC CREDIT_SEL_CREDIT_TYPE and CREDIT_SEL_TLP_TYPE viewport-select fields determines that data that is returned by the CREDIT_DATA0 and CREDIT_DATA1 data fields. -.." "Header Credit,Data Credit" newline bitfld.long 0x0 4.--5. "CREDIT_SEL_TLP_TYPE,Credit Select(TLP Type). This field in conjunction with the CREDIT_SEL_VC CREDIT_SEL_CREDIT_TYPE and CREDIT_SEL_HD viewport-select fields determines that data that is returned by the CREDIT_DATA0 and CREDIT_DATA1 data fields. - 0x0:.." "Posted,Non-Posted,Completion,?" newline bitfld.long 0x0 3. "CREDIT_SEL_CREDIT_TYPE,Credit Select(Credit Type). This field in conjunction with the CREDIT_SEL_VC CREDIT_SEL_TLP_TYPE and CREDIT_SEL_HD viewport-select fields determines that data that is returned by the CREDIT_DATA0 and CREDIT_DATA1 data fields. -.." "Rx,Tx" newline bitfld.long 0x0 0.--2. "CREDIT_SEL_VC,Credit Select(VC). This field in conjunction with the CREDIT_SEL_CREDIT_TYPE CREDIT_SEL_TLP_TYPE and CREDIT_SEL_HD viewport-select fields determines that data that is returned by the CREDIT_DATA0 and CREDIT_DATA1 data fields. - 0x0: VC0 -.." "VC0,VC1,VC2,?,?,?,?,VC7" line.long 0x4 "SD_STATUS_L3_REG,Silicon Debug Status(Layer3). For more details. see the RAS DES section in the Core Operations chapter of the Databook." hexmask.long.tbyte 0x4 8.--31. 1. "RSVDP_8,Reserved for future use." newline bitfld.long 0x4 7. "MFTLP_STATUS,Malformed TLP Status. Indicates malformed TLP has occurred." "0,1" newline hexmask.long.byte 0x4 0.--6. 1. "MFTLP_POINTER,First Malformed TLP Error Pointer. Indicates the element of the received first malformed TLP. This pointer is validated by MFTLP_STATUS. - 01h: AtomicOp address alignment - 02h: AtomicOp operand - 03h: AtomicOp byte enable - 04h: TLP length.." group.long (0xD0+0x30C)++0xB line.long 0x0 "SD_EQ_CONTROL1_REG,Silicon Debug EQ Control 1. This is a viewport control register. Setting the EQ_RATE_SEL and EQ_LANE_SEL fields in this register determine the per-lane Silicon Debug EQ Status data returned by the SD_EQ_STATUS[1/2/3] viewport.." hexmask.long.byte 0x0 24.--31. 1. "FOM_TARGET,FOM Target. Indicates figure of merit target criteria value of EQ Master(DSP in EQ Phase3/USP in EQ Phase2). This field is only valid when GEN3_EQ_FB_MODE is 0001b(Figure Of Merit). Note: This register field is sticky." newline bitfld.long 0x0 23. "FOM_TARGET_ENABLE,FOM Target Enable. Enables the FOM_TARGET fields. Note: This register field is sticky." "0,1" newline hexmask.long.byte 0x0 18.--22. 1. "RSVDP_18,Reserved for future use." newline bitfld.long 0x0 16.--17. "EVAL_INTERVAL_TIME,Eval Interval Time. Indicates interval time of RxEqEval assertion. - 00: 500ns - 01: 1us - 10: 2us - 11: 4us This field is used for EQ Master(DSP in EQ Phase3/USP in EQ Phase2). Note: This register field is sticky." "0,1,2,3" newline hexmask.long.byte 0x0 10.--15. 1. "RSVDP_10,Reserved for future use." newline bitfld.long 0x0 8.--9. "EXT_EQ_TIMEOUT,Extends EQ Phase2/3 Timeout. This field is used when the Ltssm is in Recovery.EQ2/3. When this field is set the value of EQ2/3 timeout is extended. EQ Master(DSP in EQ Phase3/USP in EQ Phase2). - 00: 24ms (default) - 01: 48ms (x2) - 10:.." "0,1,2,3" newline rbitfld.long 0x0 6.--7. "RSVDP_6,Reserved for future use." "0,1,2,3" newline bitfld.long 0x0 4.--5. "EQ_RATE_SEL,EQ Status Rate Select. Setting this field in conjunction with the EQ_LANE_SEL field determines the per-lane Silicon Debug EQ Status data returned by the SD_EQ_CONTROL[2/3] and SD_EQ_STATUS[1/2/3] viewport registers. - 0x0: 8.0GT/s Speed.." "0,1,2,3" newline hexmask.long.byte 0x0 0.--3. 1. "EQ_LANE_SEL,EQ Status Lane Select. Setting this field in conjunction with the EQ_RATE_SEL field determines the per-lane Silicon Debug EQ Status data returned by the SD_EQ_CONTROL[2/3] and SD_EQ_STATUS[1/2/3] viewport registers. - 0x0: Lane0 - 0x1: Lane1.." line.long 0x4 "SD_EQ_CONTROL2_REG,Silicon Debug EQ Control 2. This viewport register returns the value for the rate and lane selected by the EQ_RATE_SEL and EQ_LANE_SEL fields in the SD_EQ_CONTROL1_REG register. For more details. see the RAS DES section in the Core.." rbitfld.long 0x4 31. "RSVDP_31,Reserved for future use." "0,1" newline bitfld.long 0x4 30. "FORCE_LOCAL_TX_PRESET_ENABLE,Force Local Transmitter Preset Enable. Enables the FORCE_LOCAL_TX_PRESET field. If select rate in the EQ_RATE_SEL field is 32.0GT/s Speed this feature is not available. Note: This register field is sticky." "0,1" newline bitfld.long 0x4 29. "FORCE_LOCAL_RX_HINT_ENABLE,Force Local Receiver Preset Hint Enable. Enables the FORCE_LOCAL_RX_HINT field. If select rate in the EQ_RATE_SEL field is other than 8.0GT/s Speed this feature is not available. Note: This register field is sticky." "0,1" newline bitfld.long 0x4 28. "FORCE_LOCAL_TX_COEF_ENABLE,Force Local Transmitter Coefficient Enable. Enables the following fields: - FORCE_LOCAL_TX_PRE_CURSOR - FORCE_LOCAL_TX_CURSOR - FORCE_LOCAL_TX_POST_CURSOR Note: This register field is sticky." "0,1" newline hexmask.long.byte 0x4 24.--27. 1. "FORCE_LOCAL_TX_PRESET,Force Local Transmitter Preset. Indicates initial preset value of USP in EQ Slave(EQ Phase2) instead of receiving EQ TS2. If select rate in the EQ_RATE_SEL field is 32.0GT/s Speed this feature is not available. Note: This register.." newline rbitfld.long 0x4 21.--23. "RSVDP_21,Reserved for future use." "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 18.--20. "FORCE_LOCAL_RX_HINT,Force Local Receiver Preset Hint. Indicates the RxPresetHint value of EQ Slave(DSP in EQ Phase2/USP in EQ Phase3) instead of received or set value. If select rate in the EQ_RATE_SEL field is other than 8.0GT/s Speed this feature is.." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x4 12.--17. 1. "FORCE_LOCAL_TX_POST_CURSOR,Force Local Transmitter Post-Cursor. Indicates the coefficient value of EQ Slave(DSP in EQ Phase2/USP in EQ Phase3) instead of the value instructed from link partner. Note: This register field is sticky." newline hexmask.long.byte 0x4 6.--11. 1. "FORCE_LOCAL_TX_CURSOR,Force Local Transmitter Cursor. Indicates the coefficient value of EQ Slave(DSP in EQ Phase2/USP in EQ Phase3) instead of the value instructed from link partner. Note: This register field is sticky." newline hexmask.long.byte 0x4 0.--5. 1. "FORCE_LOCAL_TX_PRE_CURSOR,Force Local Transmitter Pre-cursor. Indicates the coefficient value of EQ Slave(DSP in EQ Phase2/USP in EQ Phase3) instead of the value instructed from link partner. Note: This register field is sticky." line.long 0x8 "SD_EQ_CONTROL3_REG,Silicon Debug EQ Control 3. This viewport register returns the value for the rate and lane selected by the EQ_RATE_SEL and EQ_LANE_SEL fields in the SD_EQ_CONTROL1_REG register. For more details. see the RAS DES section in the Core.." rbitfld.long 0x8 29.--31. "RSVDP_29,Reserved for future use." "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 28. "FORCE_REMOTE_TX_COEF_ENABLE,Force Remote Transmitter Coefficient Enable. Enables the following fields: - FORCE_REMOTE_TX_PRE_CURSOR - FORCE_REMOTE_TX_CURSOR - FORCE_REMOTE_TX_POST_CURSOR This function can only be used when GEN3_EQ_FB_MODE =.." "0,1" newline hexmask.long.word 0x8 18.--27. 1. "RSVDP_18,Reserved for future use." newline hexmask.long.byte 0x8 12.--17. 1. "FORCE_REMOTE_TX_POST_CURSOR,Force Remote Transmitter Post-Cursor. Indicates the coefficient value of EQ Master(DSP in EQ Phase3/USP in EQ Phase2) instead of the value instructed from local phy in dirchange mode. Note: This register field is sticky." newline hexmask.long.byte 0x8 6.--11. 1. "FORCE_REMOTE_TX_CURSOR,Force Remote Transmitter Cursor. Indicates the coefficient value of EQ Master(DSP in EQ Phase3/USP in EQ Phase2) instead of the value instructed from local phy in dirchange mode. Note: This register field is sticky." newline hexmask.long.byte 0x8 0.--5. 1. "FORCE_REMOTE_TX_PRE_CURSOR,Force Remote Transmitter Pre-Cursor. Indicates the coefficient value of EQ Master(DSP in EQ Phase3/USP in EQ Phase2) instead of the value instructed from local phy in dirchange mode. Note: This register field is sticky." rgroup.long (0xE0+0x30C)++0xB line.long 0x0 "SD_EQ_STATUS1_REG,Silicon Debug EQ Status 1. This viewport register returns the first of three words of Silicon Debug EQ Status data for the rate and lane selected by the EQ_RATE_SEL and EQ_LANE_SEL fields in the SD_EQ_CONTROL1_REG register. The.." hexmask.long.tbyte 0x0 8.--31. 1. "RSVDP_8,Reserved for future use." newline bitfld.long 0x0 7. "EQ_REJECT_EVENT,EQ Reject Event. Indicates that the controller receives two consecutive TS1 OS w/Reject=1b during EQ Master phase(DSP in EQ Phase3/USP in EQ Phase2). This bit is automatically cleared when the controller starts EQ Master phase again." "0,1" newline bitfld.long 0x0 6. "EQ_RULEC_VIOLATION,EQ Rule C Violation. Indicates that coefficients rule C violation is detected in the values provided by PHY using direction change method during EQ Master phase(DSP in EQ Phase3/USP in EQ Phase2). The coefficients rule C correspond to.." "0,1" newline bitfld.long 0x0 5. "EQ_RULEB_VIOLATION,EQ Rule B Violation. Indicates that coefficients rule B violation is detected in the values provided by PHY using direction change method during EQ Master phase(DSP in EQ Phase3/USP in EQ Phase2). The coefficients rules B correspond to.." "0,1" newline bitfld.long 0x0 4. "EQ_RULEA_VIOLATION,EQ Rule A Violation. Indicates that coefficients rule A violation is detected in the values provided by PHY using direction change method during EQ Master phase(DSP in EQ Phase3/USP in EQ Phase2). The coefficients rules A correspond to.." "0,1" newline bitfld.long 0x0 3. "RSVDP_3,Reserved for future use." "0,1" newline bitfld.long 0x0 1.--2. "EQ_CONVERGENCE_INFO,EQ Convergence Info. Indicates equalization convergence information. - 0x0: Equalization is not attempted - 0x1: Equalization finished successfully - 0x2: Equalization finished unsuccessfully - 0x3: Reserved This bit is automatically.." "Equalization is not attempted,Equalization finished successfully,Equalization finished unsuccessfully,Reserved" newline bitfld.long 0x0 0. "EQ_SEQUENCE,EQ Sequence. Indicates that the controller is starting the equalization sequence. Note: This register field is sticky." "0,1" line.long 0x4 "SD_EQ_STATUS2_REG,Silicon Debug EQ Status 2. This viewport register returns the second of three words of Silicon Debug EQ Status data for the rate and lane selected by the EQ_RATE_SEL and EQ_LANE_SEL fields in the SD_EQ_CONTROL1_REG register. Each field.." hexmask.long.byte 0x4 24.--31. 1. "EQ_LOCAL_FOM_VALUE,EQ Local Figure of Merit. Indicates Local maximum Figure of Merit value. Note: This register field is sticky." newline bitfld.long 0x4 21.--23. "RSVDP_21,Reserved for future use." "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 18.--20. "EQ_LOCAL_RX_HINT,EQ Local Receiver Preset Hint. Indicates Local Receiver Preset Hint value. If select rate in the EQ_RATE_SEL field is other than 8.0GT/s Speed this feature is not available. Note: This register field is sticky." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x4 12.--17. 1. "EQ_LOCAL_POST_CURSOR,EQ Local Post-Cursor. Indicates Local post cursor coefficient value. Note: This register field is sticky." newline hexmask.long.byte 0x4 6.--11. 1. "EQ_LOCAL_CURSOR,EQ Local Cursor. Indicates Local cursor coefficient value. Note: This register field is sticky." newline hexmask.long.byte 0x4 0.--5. 1. "EQ_LOCAL_PRE_CURSOR,EQ Local Pre-Cursor. Indicates Local pre cursor coefficient value. Note: This register field is sticky." line.long 0x8 "SD_EQ_STATUS3_REG,Silicon Debug EQ Status 3. This viewport register returns the third of three words of Silicon Debug EQ Status data for the rate and lane selected by the EQ_RATE_SEL and EQ_LANE_SEL fields in the SD_EQ_CONTROL1_REG register. Each field.." bitfld.long 0x8 30.--31. "RSVDP_30,Reserved for future use." "0,1,2,3" newline hexmask.long.byte 0x8 24.--29. 1. "EQ_REMOTE_FS,EQ Remote FS. Indicates Remote FS value. Note: This register field is sticky." newline hexmask.long.byte 0x8 18.--23. 1. "EQ_REMOTE_LF,EQ Remote LF. Indicates Remote LF value. Note: This register field is sticky." newline hexmask.long.byte 0x8 12.--17. 1. "EQ_REMOTE_POST_CURSOR,EQ Remote Post-Cursor. Indicates Remote post cursor coefficient value. Note: This register field is sticky." newline hexmask.long.byte 0x8 6.--11. 1. "EQ_REMOTE_CURSOR,EQ Remote Cursor. Indicates Remote cursor coefficient value. Note: This register field is sticky." newline hexmask.long.byte 0x8 0.--5. 1. "EQ_REMOTE_PRE_CURSOR,EQ Remote Pre-Cursor. Indicates Remote pre cursor coefficient value. Note: This register field is sticky." tree.end tree "PF0_SN_CAP (Device Serial Number Capability Structure)" group.long (0x0+0x170)++0xB line.long 0x0 "SN_BASE,Device Serial Number Extended Capability Header. For a description of this standard PCIe register. see the PCI Express Base Specification." hexmask.long.word 0x0 20.--31. 1. "SN_NEXT_OFFSET,Next Capability Offset. For a description of this standard PCIe register field see the PCI Express Base Specification. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then.." hexmask.long.byte 0x0 16.--19. 1. "SN_CAP_VERSION,Capability Version. For a description of this standard PCIe register field see the PCI Express Base Specification. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky).." hexmask.long.word 0x0 0.--15. 1. "SN_PCIE_EXTENDED_CAP_ID,Serial Number Extended Capability ID. For a description of this standard PCIe register field see the PCI Express Base Specification. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if.." line.long 0x4 "SER_NUM_REG_DW_1,Serial Number 1 Register. For a description of this standard PCIe register. see the PCI Express Base Specification." hexmask.long 0x4 0.--31. 1. "SN_SER_NUM_REG_1_DW,IEEE 64 bit Device Serial Number (DW 1). For a description of this standard PCIe register field see the PCI Express Base Specification. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if.." line.long 0x8 "SER_NUM_REG_DW_2,Serial Number 2 Register. For a description of this standard PCIe register. see the PCI Express Base Specification." hexmask.long 0x8 0.--31. 1. "SN_SER_NUM_REG_2_DW,IEEE 64 bit Device Serial Number (DW 2). For a description of this standard PCIe register field see the PCI Express Base Specification. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if.." tree.end tree "PF0_VSECRAS_CAP (PF RAS Datapath Protection Capability Structure (VSEC))" group.long (0x0+0x480)++0x3 line.long 0x0 "RASDP_EXT_CAP_HDR_OFF,PCIe Extended capability ID. Capability version and Next capability offset. For a description of this standard PCIe register. see the PCI Express Specification." hexmask.long.word 0x0 20.--31. 1. "NEXT_OFFSET,Next Capability Offset. For a description of this standard PCIe register see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else.." newline hexmask.long.byte 0x0 16.--19. 1. "CAP,Capability Version. For a description of this standard PCIe register see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note:.." newline hexmask.long.word 0x0 0.--15. 1. "ID,PCI Express Extended Capability ID. For a description of this standard PCIe register see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else.." rgroup.long (0x4+0x480)++0x3 line.long 0x0 "RASDP_VENDOR_SPECIFIC_HDR_OFF,Vendor Specific Header. For a description of this standard PCIe register. see the PCI Express Specification." hexmask.long.word 0x0 20.--31. 1. "VSEC_LENGTH,VSEC Length. For a description of this standard PCIe register see the PCI Express Specification. Note: This register field is sticky." newline hexmask.long.byte 0x0 16.--19. 1. "VSEC_REV,VSEC Rev. For a description of this standard PCIe register see the PCI Express Specification. Note: This register field is sticky." newline hexmask.long.word 0x0 0.--15. 1. "VSEC_ID,VSEC ID. For a description of this standard PCIe register see the PCI Express Specification. Note: This register field is sticky." group.long (0x8+0x480)++0x7 line.long 0x0 "RASDP_ERROR_PROT_CTRL_OFF,ECC error correction control. Allows you to disable ECC error correction for RAMs and datapath. When the AXI Bridge Module is implemented and the master / slave clocks are asynchronous to the PCIe native controller clock.." hexmask.long.byte 0x0 24.--31. 1. "RSVDP_24,Reserved for future use." newline bitfld.long 0x0 23. "ERROR_PROT_DISABLE_CXS_RX,Error correction disable for CXS Tx path (PCIe Rx path). Note: This register field is sticky." "0,1" newline bitfld.long 0x0 22. "ERROR_PROT_DISABLE_ADM_RX,Error correction disable for ADM Rx path. Note: This register field is sticky." "0,1" newline bitfld.long 0x0 21. "ERROR_PROT_DISABLE_LAYER3_RX,Error correction disable for layer 3 Rx path. Note: This register field is sticky." "0,1" newline bitfld.long 0x0 20. "ERROR_PROT_DISABLE_LAYER2_RX,Error correction disable for layer 2 Rx path. Note: This register field is sticky." "0,1" newline bitfld.long 0x0 19. "ERROR_PROT_DISABLE_DMA_READ,Error correction disable for DMA read engine. Note: This register field is sticky." "0,1" newline bitfld.long 0x0 18. "ERROR_PROT_DISABLE_AXI_BRIDGE_INBOUND_REQUEST,Error correction disable for AXI bridge inbound request path. Note: This register field is sticky." "0,1" newline bitfld.long 0x0 17. "ERROR_PROT_DISABLE_AXI_BRIDGE_INBOUND_COMPLETION,Error correction disable for AXI bridge inbound completion composer. Does not disable the error detection reporting for 1-bit and 2-bit ECC errors. Note: This register field is sticky." "?,bit and 2-bit ECC errors" newline bitfld.long 0x0 16. "ERROR_PROT_DISABLE_RX,Global error correction disable for all Rx layers. Note: This register field is sticky." "0,1" newline hexmask.long.byte 0x0 9.--15. 1. "RSVDP_9,Reserved for future use." newline bitfld.long 0x0 8. "ERROR_PROT_DISABLE_DTIM_TX,Error correction disable for DTIM Tx path. Note: This register field is sticky." "0,1" newline bitfld.long 0x0 7. "ERROR_PROT_DISABLE_CXS_TX,Error correction disable for CXS Rx path (PCIe Tx path). Note: This register field is sticky." "0,1" newline bitfld.long 0x0 6. "ERROR_PROT_DISABLE_ADM_TX,Error correction disable for Adm Tx path. Note: This register field is sticky." "0,1" newline bitfld.long 0x0 5. "ERROR_PROT_DISABLE_LAYER3_TX,Error correction disable for layer 3 Tx path. Note: This register field is sticky." "0,1" newline bitfld.long 0x0 4. "ERROR_PROT_DISABLE_LAYER2_TX,Error correction disable for layer 2 Tx path. Note: This register field is sticky." "0,1" newline bitfld.long 0x0 3. "ERROR_PROT_DISABLE_DMA_WRITE,Error correction disable for DMA write engine. Note: This register field is sticky." "0,1" newline bitfld.long 0x0 2. "ERROR_PROT_DISABLE_AXI_BRIDGE_OUTBOUND,Error correction disable for AXI bridge outbound request path. Note: This register field is sticky." "0,1" newline bitfld.long 0x0 1. "ERROR_PROT_DISABLE_AXI_BRIDGE_MASTER,Error correction disable for AXI bridge master completion buffer. Note: This register field is sticky." "0,1" newline bitfld.long 0x0 0. "ERROR_PROT_DISABLE_TX,Global error correction disable for all Tx layers. Does not disable the error detection reporting for 1-bit and 2-bit ECC errors. Note: This register field is sticky." "?,bit and 2-bit ECC errors" line.long 0x4 "RASDP_CORR_COUNTER_CTRL_OFF,Corrected error (1-bit ECC) counter selection and control. This is a viewport control register. Setting the CORR_COUNTER_SELECTION_REGION and CORR_COUNTER_SELECTION fields in this register determine the counter data returned.." hexmask.long.byte 0x4 24.--31. 1. "CORR_COUNTER_SELECTION,Counter selection. This field selects the counter ID (within the region defined by CORR_COUNTER_SELECTION_REGION) whose contents can be read from the RASDP_CORR_COUNT_REPORT_OFF register. You can cycle this field value from 0 to.." newline hexmask.long.byte 0x4 20.--23. 1. "CORR_COUNTER_SELECTION_REGION,Select correctable counter region: - 0x0: Region select for Adm Rx path - 0x1: Region select for layer 3 Rx path - 0x2: Region select for layer 2 Rx path - 0x3: Region select for DMA inbound path - 0x4: Region select for AXI.." newline hexmask.long.word 0x4 5.--19. 1. "RSVDP_5,Reserved for future use." newline bitfld.long 0x4 4. "CORR_EN_COUNTERS,Enable correctable errors counters. - 1: counters increment when the controller detects a correctable error - 0: counters are frozen The counters are enabled by default." "counters are frozen,counters increment when the controller detects a.." newline rbitfld.long 0x4 1.--3. "RSVDP_1,Reserved for future use." "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 0. "CORR_CLEAR_COUNTERS,Clear all correctable error counters." "0,1" rgroup.long (0x10+0x480)++0x3 line.long 0x0 "RASDP_CORR_COUNT_REPORT_OFF,Corrected error (1-bit ECC) counter data. This viewport register returns the counter data selected by the CORR_COUNTER_SELECTION_REGION and CORR_COUNTER_SELECTION fields in the RASDP_CORR_COUNTER_CTRL_OFF register." hexmask.long.byte 0x0 24.--31. 1. "CORR_COUNTER_SELECTED,Counter selection. Returns the value set in the CORR_COUNTER_SELECTION field of the RASDP_CORR_COUNTER_CTRL_OFF register." newline hexmask.long.byte 0x0 20.--23. 1. "CORR_COUNTER_SELECTED_REGION,Selected correctable counter region: - 0x0: Region select for Adm Rx path - 0x1: Region select for layer 3 Rx path - 0x2: Region select for layer 2 Rx path - 0x3: Region select for DMA inbound path - 0x4: Region select for.." newline hexmask.long.word 0x0 8.--19. 1. "RSVDP_8,Reserved for future use." newline hexmask.long.byte 0x0 0.--7. 1. "CORR_COUNTER,Current corrected error count for the selected counter." group.long (0x14+0x480)++0x3 line.long 0x0 "RASDP_UNCORR_COUNTER_CTRL_OFF,Uncorrected error (2-bit ECC and parity) counter selection and control. This is a viewport control register. Setting the UNCORR_COUNTER_SELECTION_REGION and UNCORR_COUNTER_SELECTION fields in this register determine the.." hexmask.long.byte 0x0 24.--31. 1. "UNCORR_COUNTER_SELECTION,Counter selection. This field selects the counter ID (within the region defined by UNCORR_COUNTER_SELECTION_REGION) whose contents can be read from the RASDP_UNCORR_COUNT_REPORT_OFF register. You can cycle this field value from 0.." newline hexmask.long.byte 0x0 20.--23. 1. "UNCORR_COUNTER_SELECTION_REGION,Select uncorrectable counter region: - 0x0: Region select for Adm Rx path - 0x1: Region select for layer 3 Rx path - 0x2: Region select for layer 2 Rx path - 0x3: Region select for DMA inbound path - 0x4: Region select for.." newline hexmask.long.word 0x0 5.--19. 1. "RSVDP_5,Reserved for future use." newline bitfld.long 0x0 4. "UNCORR_EN_COUNTERS,Enable uncorrectable errors counters. - 1: enables the counters to increment on detected correctable errors - 0: counters are frozen The counters are enabled by default." "counters are frozen,enables the counters to increment on detected.." newline rbitfld.long 0x0 1.--3. "RSVDP_1,Reserved for future use." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 0. "UNCORR_CLEAR_COUNTERS,Clear uncorrectable errors counters. When asserted causes all counters tracking the uncorrectable errors to be cleared." "0,1" rgroup.long (0x18+0x480)++0x3 line.long 0x0 "RASDP_UNCORR_COUNT_REPORT_OFF,Uncorrected error (2-bit ECC and parity) counter data. This viewport register returns the counter data selected by the UNCORR_COUNTER_SELECTION_REGION and UNCORR_COUNTER_SELECTION fields in the RASDP_UNCORR_COUNTER_CTRL_OFF.." hexmask.long.byte 0x0 24.--31. 1. "UNCORR_COUNTER_SELECTED,Counter selection. Returns the value set in the UNCORR_COUNTER_SELECTION field of the RASDP_UNCORR_COUNTER_CTRL_OFF register." newline hexmask.long.byte 0x0 20.--23. 1. "UNCORR_COUNTER_SELECTED_REGION,Selected uncorrectable counter region: - 0x0: Region select for Adm Rx path - 0x1: Region select for layer 3 Rx path - 0x2: Region select for layer 2 Rx path - 0x3: Region select for DMA inbound path - 0x4: Region select.." newline hexmask.long.word 0x0 8.--19. 1. "RSVDP_8,Reserved for future use." newline hexmask.long.byte 0x0 0.--7. 1. "UNCORR_COUNTER,Current uncorrected error count for the selected counter" group.long (0x1C+0x480)++0x3 line.long 0x0 "RASDP_ERROR_INJ_CTRL_OFF,Error injection control for the following features: - 1-bit or 2-bit injection - Continuous or fixed-number (n) injection modes - Global enable/disable - Selectable location where injection occurs" hexmask.long.byte 0x0 24.--31. 1. "RSVDP_24,Reserved for future use." newline hexmask.long.byte 0x0 16.--23. 1. "ERROR_INJ_LOC,Error injection location. Selects where error injection takes place. You can cycle this field value from 0 to 255 to access all locations according to the detailed report of check points at.." newline hexmask.long.byte 0x0 8.--15. 1. "ERROR_INJ_COUNT,Error injection count. - 0: errors are inserted in every TLP until you clear ERROR_INJ_EN. - 1: one errors injected - 2: two errors injected - n: amount of errors injected" newline rbitfld.long 0x0 6.--7. "RSVDP_6,Reserved for future use." "0,1,2,3" newline bitfld.long 0x0 4.--5. "ERROR_INJ_TYPE,Error injection type: - 0: none - 1: 1-bit - 2: 2-bit" "none,bit,bit,?" newline rbitfld.long 0x0 1.--3. "RSVDP_1,Reserved for future use." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 0. "ERROR_INJ_EN,Error injection global enable. When set enables the error insertion logic." "0,1" rgroup.long (0x20+0x480)++0x7 line.long 0x0 "RASDP_CORR_ERROR_LOCATION_OFF,Corrected errors locations. For more details. see the RAS Data Protection (DP) section in the Core Operations chapter of the Databook." hexmask.long.byte 0x0 24.--31. 1. "LOC_LAST_CORR_ERROR,Location/ID of the last corrected error within the region defined by REG_LAST_CORR_ERROR. You can cycle this field value from 0 to 255 to access all counters according to the detailed report of check points at.." newline hexmask.long.byte 0x0 20.--23. 1. "REG_LAST_CORR_ERROR,Region of the last corrected error: - 0x0: Region select for Adm Rx path - 0x1: Region select for layer 3 Rx path - 0x2: Region select for layer 2 Rx path - 0x3: Region select for DMA inbound path - 0x4: Region select for AXI bridge.." newline hexmask.long.byte 0x0 16.--19. 1. "RSVDP_16,Reserved for future use." newline hexmask.long.byte 0x0 8.--15. 1. "LOC_FIRST_CORR_ERROR,Location/ID of the first corrected error within the region defined by REG_FIRST_CORR_ERROR. You can cycle this field value from 0 to 255 to access all counters according to the detailed report of check points at.." newline hexmask.long.byte 0x0 4.--7. 1. "REG_FIRST_CORR_ERROR,Region of the first corrected error: - 0x0: Region select for Adm Rx path - 0x1: Region select for layer 3 Rx path - 0x2: Region select for layer 2 Rx path - 0x3: Region select for DMA inbound path - 0x4: Region select for AXI bridge.." newline hexmask.long.byte 0x0 0.--3. 1. "RSVDP_0,Reserved for future use." line.long 0x4 "RASDP_UNCORR_ERROR_LOCATION_OFF,Uncorrected errors locations. For more details. see the RAS Data Protection (DP) section in the Core Operations chapter of the Databook." hexmask.long.byte 0x4 24.--31. 1. "LOC_LAST_UNCORR_ERROR,Location/ID of the last uncorrected error within the region defined by REG_LAST_UNCORR_ERROR. You can cycle this field value from 0 to 255 to access all counters according to the detailed report of check points at.." newline hexmask.long.byte 0x4 20.--23. 1. "REG_LAST_UNCORR_ERROR,Region of the last uncorrected error: - 0x0: Region select for Adm Rx path - 0x1: Region select for layer 3 Rx path - 0x2: Region select for layer 2 Rx path - 0x3: Region select for DMA inbound path - 0x4: Region select for AXI.." newline hexmask.long.byte 0x4 16.--19. 1. "RSVDP_16,Reserved for future use." newline hexmask.long.byte 0x4 8.--15. 1. "LOC_FIRST_UNCORR_ERROR,Location/ID of the first uncorrected error within the region defined by REG_FIRST_UNCORR_ERROR. You can cycle this field value from 0 to 255 to access all counters according to the detailed report of check points at.." newline hexmask.long.byte 0x4 4.--7. 1. "REG_FIRST_UNCORR_ERROR,Region of the first uncorrected error: - 0x0: Region select for Adm Rx path - 0x1: Region select for layer 3 Rx path - 0x2: Region select for layer 2 Rx path - 0x3: Region select for DMA inbound path - 0x4: Region select for AXI.." newline hexmask.long.byte 0x4 0.--3. 1. "RSVDP_0,Reserved for future use." group.long (0x28+0x480)++0x7 line.long 0x0 "RASDP_ERROR_MODE_EN_OFF,RASDP error mode enable. The controller enters RASDP error mode (if ERROR_MODE_EN =1) upon detection of the first uncorrectable error. During this mode: - Rx TLPs that are forwarded to your application are not guaranteed to be.." hexmask.long 0x0 2.--31. 1. "RSVDP_2,Reserved for future use." newline bitfld.long 0x0 1. "AUTO_LINK_DOWN_EN,Write '1' to enable the controller to bring the link down when the controller enters RASDP error mode. Note: This register field is sticky." "0,1" newline bitfld.long 0x0 0. "ERROR_MODE_EN,Write '1' to enable the controller enter RASDP error mode when it detects an uncorrectable error. Note: This register field is sticky." "0,1" line.long 0x4 "RASDP_ERROR_MODE_CLEAR_OFF,Exit RASDP error mode. For more details. see the RAS Data Protection (DP) section in the Core Operations chapter of the Databook." hexmask.long 0x4 1.--31. 1. "RSVDP_1,Reserved for future use." newline bitfld.long 0x4 0. "ERROR_MODE_CLEAR,Write '1' to take the controller out of RASDP error mode. The controller will then report uncorrectable errors (through AER internal error reporting) and also stop nullifying/discarding TLPs." "0,1" rgroup.long (0x30+0x480)++0x7 line.long 0x0 "RASDP_RAM_ADDR_CORR_ERROR_OFF,RAM Address where a corrected error (1-bit ECC) has been detected. For more details. see the RAS Data Protection (DP) section in the Core Operations chapter of the Databook." hexmask.long.byte 0x0 28.--31. 1. "RAM_INDEX_CORR_ERROR,RAM index where a corrected error (1-bit ECC) has been detected." newline bitfld.long 0x0 27. "RSVDP_27,Reserved for future use." "0,1" newline hexmask.long 0x0 0.--26. 1. "RAM_ADDR_CORR_ERROR,RAM Address where a corrected error (1-bit ECC) has been detected." line.long 0x4 "RASDP_RAM_ADDR_UNCORR_ERROR_OFF,RAM Address where an uncorrected error (2-bit ECC) has been detected. For more details. see the RAS Data Protection (DP) section in the Core Operations chapter of the Databook." hexmask.long.byte 0x4 28.--31. 1. "RAM_INDEX_UNCORR_ERROR,RAM index where an uncorrected error (2-bit ECC) has been detected." newline bitfld.long 0x4 27. "RSVDP_27,Reserved for future use." "0,1" newline hexmask.long 0x4 0.--26. 1. "RAM_ADDR_UNCORR_ERROR,RAM Address where an uncorrected error (2-bit ECC) has been detected." tree.end tree "PF0_RTR_CAP (PF RTR Capability Structure)" group.long (0x0+0x2F8)++0xB line.long 0x0 "RTR_EXT_CAP_HDR_OFF,Readiness Time Reporting PCI Express Extended Capability Header. For a description of this standard PCIe register. see the PCI Express Specification." hexmask.long.word 0x0 20.--31. 1. "RTR_NEXT_OFFSET,Next Capability Offset. For a description of this standard PCIe register field see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky).." hexmask.long.byte 0x0 16.--19. 1. "RTR_CAP_VERSION,Capability Version. For a description of this standard PCIe register field see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky).." hexmask.long.word 0x0 0.--15. 1. "RTR_EXT_CAP_ID,PCI Express Extended Capability ID. For a description of this standard PCIe register field see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then.." line.long 0x4 "READI_TIME_REPORTING1_OFF,Readiness Time Reporting 1. For a description of this standard PCIe register. see the PCI Express Specification." bitfld.long 0x4 31. "RTR_TIME_VALID,Valid. For a description of this standard PCIe register field see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky)" "0,1" hexmask.long.byte 0x4 24.--30. 1. "RSVDP_24,Reserved for future use." hexmask.long.word 0x4 12.--23. 1. "DL_UP_TIME,DL_UP Time. For a description of this standard PCIe register field see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky)" hexmask.long.word 0x4 0.--11. 1. "RESET_TIME,Reset Time. For a description of this standard PCIe register field see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky)" line.long 0x8 "READI_TIME_REPORTING2_OFF,Readiness Time Reporting 2. For a description of this standard PCIe register. see the PCI Express Specification." hexmask.long.byte 0x8 24.--31. 1. "RSVDP_24,Reserved for future use." hexmask.long.word 0x8 12.--23. 1. "D3HOT_D0_TIME,D3hot to D0 Time. For a description of this standard PCIe register field see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else.." hexmask.long.word 0x8 0.--11. 1. "FLR_TIME,FLR Time. For a description of this standard PCIe register field see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky)" tree.end tree "PF0_RTR_CAP_DBI2 (DBI2 Shadow Block: PF RTR Capability Structure)" rgroup.long (0x4+0x12F8)++0x7 line.long 0x0 "SHADOW_READI_TIME_REPORTING1_OFF,Shadow Register Readiness Time Reporting 1. For a description of this standard PCIe register. see the PCI Express Specification." bitfld.long 0x0 31. "RTR_TIME_VALID,Shadow Valid in the shadow register. For a description of this standard PCIe register field see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access - Dbi: No access - Dbi2: if.." "0,1" hexmask.long.tbyte 0x0 12.--30. 1. "RSVDP_12,Reserved for future use." hexmask.long.word 0x0 0.--11. 1. "RESET_TIME,Shadow Reset Time in the shadow register. For a description of this standard PCIe register field see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access - Dbi: No access - Dbi2: if.." line.long 0x4 "SHADOW_READI_TIME_REPORTING2_OFF,Shadow Register Readiness Time Reporting 2. For a description of this standard PCIe register. see the PCI Express Specification." hexmask.long.byte 0x4 24.--31. 1. "RSVDP_24,Reserved for future use." hexmask.long.word 0x4 12.--23. 1. "D3HOT_D0_TIME,Shadow D3hot to D0 Time in the shadow register. For a description of this standard PCIe register field see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access - Dbi: No access - Dbi2:.." hexmask.long.word 0x4 0.--11. 1. "FLR_TIME,Shadow FLR Time in the shadow register. For a description of this standard PCIe register field see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access - Dbi: No access - Dbi2: if.." tree.end tree "PF0_FRSQ_CAP (PF FRSQ Capability Structure)" group.long (0x0+0x2E8)++0xB line.long 0x0 "FRSQ_EXT_CAP_HDR_OFF,FRS Queuing Extended Capability Header. For a description of this standard PCIe register. see the PCI Express Specification." hexmask.long.word 0x0 20.--31. 1. "FRSQ_NEXT_OFFSET,Next Capability Offset. For a description of this standard PCIe register field see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then.." hexmask.long.byte 0x0 16.--19. 1. "FRSQ_CAP_VERSION,Capability Version. For a description of this standard PCIe register field see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky).." hexmask.long.word 0x0 0.--15. 1. "FRSQ_EXT_CAP_ID,PCI Express Extended Capability ID. For a description of this standard PCIe register field see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then.." line.long 0x4 "FRSQ_CAP_OFF,FRS Queuing Capability Register. For a description of this standard PCIe register. see the PCI Express Specification." hexmask.long.word 0x4 21.--31. 1. "RSVDP_21,Reserved for future use." hexmask.long.byte 0x4 16.--20. 1. "FRS_INT_MESSAGE_NUMBER,FRS Interrupt Message Number. For a description of this standard PCIe register field see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1).." hexmask.long.byte 0x4 12.--15. 1. "RSVDP_12,Reserved for future use." hexmask.long.word 0x4 0.--11. 1. "FRSQ_MAX_DEPTH,FRS Queue Max Depth. For a description of this standard PCIe register field see the PCI Express Specification." line.long 0x8 "FRSQ_CONTROL_FRSQ_STATUS_OFF,FRS Queuing Status and Control Register. For a description of this standard PCIe register. see the PCI Express Specification." hexmask.long.word 0x8 17.--31. 1. "RSVDP_17,Reserved for future use." bitfld.long 0x8 16. "FRS_INTERRUPT_ENABLE,FRS Interrupt Enable. For a description of this standard PCIe register field see the PCI Express Specification." "0,1" hexmask.long.word 0x8 2.--15. 1. "RSVDP_2,Reserved for future use." bitfld.long 0x8 1. "FRS_MESSAGE_OVERFLOW,FRS Message Overflow. For a description of this standard PCIe register field see the PCI Express Specification." "0,1" newline bitfld.long 0x8 0. "FRS_MESSAGE_RECEIVED,FRS Message Received. For a description of this standard PCIe register field see the PCI Express Specification." "0,1" rgroup.long (0xC+0x2E8)++0x3 line.long 0x0 "FRS_MESSAGE_QUEUE_OFF,FRS Message Queue Register. For a description of this standard PCIe register. see the PCI Express Specification." hexmask.long.word 0x0 20.--31. 1. "FRS_MESSAGE_QUE_DEPTH,FRS Message Queue Depth. For a description of this standard PCIe register field see the PCI Express Specification." hexmask.long.byte 0x0 16.--19. 1. "FRS_MESSAGE_QUE_REASON,FRS Message Queue Reason. For a description of this standard PCIe register field see the PCI Express Specification." hexmask.long.word 0x0 0.--15. 1. "FRS_MESSAGE_QUE_FUNC_ID,FRS Message Queue Function ID. For a description of this standard PCIe register field see the PCI Express Specification." tree.end tree "PF0_PTM_CAP (PF PTM Capability Structure)" group.long (0x0+0x40C)++0xB line.long 0x0 "PTM_EXT_CAP_HDR_OFF,Precision Time Measurement Capability Header. For a description of this standard PCIe register. see the PCI Express Specification." hexmask.long.word 0x0 20.--31. 1. "PTM_NEXT_OFFSET,Precision Time Measurement PCI Express Extended Capability Next Offset. For a description of this standard PCIe register see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access. -.." hexmask.long.byte 0x0 16.--19. 1. "PTM_CAP_VERSION,Precision Time Measurement PCI Express Extended Capability Version. For a description of this standard PCIe register see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi:.." hexmask.long.word 0x0 0.--15. 1. "PTM_CAP_ID,Precision Time Measurement PCI Express Extended Capability ID. For a description of this standard PCIe register see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if.." line.long 0x4 "PTM_CAP_OFF,PTM Capability Register. For a description of this standard PCIe register. see the PCI Express Specification." hexmask.long.word 0x4 16.--31. 1. "RSVDP_16,Reserved for future use." hexmask.long.byte 0x4 8.--15. 1. "PTM_CLK_GRAN,PTM Local Clock Granularity. For a description of this standard PCIe register see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky).." hexmask.long.byte 0x4 3.--7. 1. "RSVDP_3,Reserved for future use." bitfld.long 0x4 2. "PTM_ROOT_CAPABLE,PTM Root Capable. For a description of this standard PCIe register see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else.." "0,1" bitfld.long 0x4 1. "PTM_RES_CAPABLE,PTM Responder Capable. For a description of this standard PCIe register see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else.." "0,1" newline bitfld.long 0x4 0. "PTM_REQ_CAPABLE,PTM Requester Capable. For a description of this standard PCIe register see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else.." "0,1" line.long 0x8 "PTM_CONTROL_OFF,PTM Control Register. For a description of this standard PCIe register. see the PCI Express Specification." hexmask.long.word 0x8 16.--31. 1. "RSVDP_16,Reserved for future use." hexmask.long.byte 0x8 8.--15. 1. "EFF_GRAN,PTM Effective Granularity. For a description of this standard PCIe register see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: HWINIT" hexmask.long.byte 0x8 2.--7. 1. "RSVDP_2,Reserved for future use." rbitfld.long 0x8 1. "ROOT_SELECT,PTM Root Select. When set this Time Source is the PTM Root. For a description of this standard PCIe register see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: HWINIT" "0,1" bitfld.long 0x8 0. "PTM_ENABLE,PTM Enable. When set this function is permitted to participate in the PTM mechanism. For a description of this standard PCIe register see the PCI Express Specification." "0,1" tree.end tree "PF0_PTM_RES_CAP (PF PTM Responder Capability Structure (VSEC))" group.long (0x0+0x418)++0xB line.long 0x0 "PTM_RES_CAP_HDR_OFF,Precision Time Measurement Responder Capability Header (VSEC). For more details. see the PTM section in the Databook." hexmask.long.word 0x0 20.--31. 1. "PTM_RES_EXT_CAP_NEXT_OFFS,Precision Time Measurement Responder VSEC Next Pointer. For more details see the PTM section in the Databook. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then.." hexmask.long.byte 0x0 16.--19. 1. "PTM_RES_EXT_CAP_VER,Precision Time Measurement Responder VSEC Version. For more details see the PTM section in the Databook. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else.." hexmask.long.word 0x0 0.--15. 1. "PTM_RES_EXT_CAP_ID,Precision Time Measurement Responder VSEC ID. For more details see the PTM section in the Databook. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else.." line.long 0x4 "PTM_RES_HDR_OFF,Precision Time Measurement Responder Vendor Specific Header. For more details. see the PTM section in the Databook." hexmask.long.word 0x4 20.--31. 1. "PTM_RES_VSEC_LENGTH,PTM Responder VSEC Length. For more details see the PTM section in the Databook. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This.." hexmask.long.byte 0x4 16.--19. 1. "PTM_RES_VSEC_REV,PTM Responder VSEC Revision. For more details see the PTM section in the Databook. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This.." hexmask.long.word 0x4 0.--15. 1. "PTM_RES_VSEC_ID,PTM Responder VSEC ID. For more details see the PTM section in the Databook. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register.." line.long 0x8 "PTM_RES_CONTROL_OFF,PTM Responder Control Register. For more details. see the PTM section in the Databook." hexmask.long 0x8 2.--31. 1. "RSVDP_2,Reserved for future use." bitfld.long 0x8 1. "PTM_RES_PDEL_BYTE_REV,PTM Requester Propagation Delay Byte Reversal - Reverse the order of bytes in the PTM Propagation Delay data word of the PTM ResponseD Message for compatibility with previous revisions. For more details see the PTM section in the.." "0,1" bitfld.long 0x8 0. "PTM_RES_CCONTEXT_VALID,PTM Responder Control Context Valid - PTM Local Timing is valid. This bit is set over the DBI. A speed change or aux_clk_active will set this bit low. For more details see the PTM section in the Databook. Note: The access.." "0,1" rgroup.long (0xC+0x418)++0x3 line.long 0x0 "PTM_RES_STATUS_OFF,PTM Responder Status Register. For more details. see the PTM section in the Databook." hexmask.long 0x0 2.--31. 1. "RSVDP_2,Reserved for future use." bitfld.long 0x0 1. "PTM_RES_REQUEST_RECEIVED,PTM 1st Request Received - PTM Responder has received the first PTM Request Message. Upon receipt of a second PTM Request Message a ResponseD message with timing information will be sent from the Responder if the context is.." "0,1" bitfld.long 0x0 0. "PTM_RES_CONTEXT_VALID,PTM Responder Status Context Valid - PTM Local Timing Context is Valid. Value set from upstream port Requester in a Switch. Shadows the same in the control register in all other products. For more details see the PTM section in the.." "0,1" group.long (0x10+0x418)++0x7 line.long 0x0 "PTM_RES_LOCAL_LSB_OFF,PTM Responder Local Clock LSB. For more details. see the PTM section in the Databook." hexmask.long 0x0 0.--31. 1. "PTM_RES_LOCAL_LSB,PTM Responder Local Clock LSB - Lower 32 bits of local timer value. For more details see the PTM section in the Databook. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then.." line.long 0x4 "PTM_RES_LOCAL_MSB_OFF,PTM Responder Local Clock MSB. For more details. see the PTM section in the Databook." hexmask.long 0x4 0.--31. 1. "PTM_RES_LOCAL_MSB,PTM Responder Local Clock MSB - Upper 32 bits of local timer value. For more details see the PTM section in the Databook. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then.." rgroup.long (0x18+0x418)++0x1F line.long 0x0 "PTM_RES_T2_LSB_OFF,PTM Responder T2 Timestamp LSB. For more details. see the PTM section in the Databook." hexmask.long 0x0 0.--31. 1. "PTM_RES_T2_LSB,PTM Responder T2 Timestamp LSB - Lower 32 bits of the T2 Timestamp value. For more details see the PTM section in the Databook. Note: This register field is sticky." line.long 0x4 "PTM_RES_T2_MSB_OFF,PTM Responder T2 Timestamp MSB. For more details. see the PTM section in the Databook." hexmask.long 0x4 0.--31. 1. "PTM_RES_T2_MSB,PTM Responder T2 Timestamp MSB - Upper 32 bits of the T2 Timestamp value. For more details see the PTM section in the Databook. Note: This register field is sticky." line.long 0x8 "PTM_RES_T2P_LSB_OFF,PTM Responder T2 Previous Timestamp LSB. For more details. see the PTM section in the Databook." hexmask.long 0x8 0.--31. 1. "PTM_RES_T2P_LSB,PTM Responder T2 Previous Timestamp LSB - Lower 32 bits of the previously stored T2 Timestamp value. For more details see the PTM section in the Databook. Note: This register field is sticky." line.long 0xC "PTM_RES_T2P_MSB_OFF,PTM Responder T2 Previous Timestamp MSB. For more details. see the PTM section in the Databook." hexmask.long 0xC 0.--31. 1. "PTM_RES_T2P_MSB,PTM Responder T2 Previous Timestamp MSB - Upper 32 bits of the previously stored T2 Timestamp value. For more details see the PTM section in the Databook. Note: This register field is sticky." line.long 0x10 "PTM_RES_T3_LSB_OFF,PTM Responder T3 Timestamp LSB. For more details. see the PTM section in the Databook." hexmask.long 0x10 0.--31. 1. "PTM_RES_T3_LSB,PTM Responder T3 Timestamp LSB - Lower 32 bits of the T3 Timestamp value. For more details see the PTM section in the Databook. Note: This register field is sticky." line.long 0x14 "PTM_RES_T3_MSB_OFF,PTM Responder T3 Timestamp MSB. For more details. see the PTM section in the Databook." hexmask.long 0x14 0.--31. 1. "PTM_RES_T3_MSB,PTM Responder T3 Timestamp MSB - Upper 32 bits of the T2 Timestamp value. For more details see the PTM section in the Databook. Note: This register field is sticky." line.long 0x18 "PTM_RES_T3P_LSB_OFF,PTM Responder T3 Previous Timestamp LSB. For more details. see the PTM section in the Databook." hexmask.long 0x18 0.--31. 1. "PTM_RES_T3P_LSB,PTM Responder T3 Previous Timestamp LSB - Lower 32 bits of the previously stored T3 Timestamp value. For more details see the PTM section in the Databook. Note: This register field is sticky." line.long 0x1C "PTM_RES_T3P_MSB_OFF,PTM Responder T3 Previous Timestamp MSB. For more details. see the PTM section in the Databook." hexmask.long 0x1C 0.--31. 1. "PTM_RES_T3P_MSB,PTM Responder T3 Previous Timestamp MSB - Upper 32 bits of the previously stored T3 Timestamp value. For more details see the PTM section in the Databook. Note: This register field is sticky." group.long (0x38+0x418)++0x7 line.long 0x0 "PTM_RES_TX_LATENCY_OFF,PTM Responder TX Latency. For more details. see the PTM section in the Databook." hexmask.long.tbyte 0x0 12.--31. 1. "RSVDP_12,Reserved for future use." hexmask.long.word 0x0 0.--11. 1. "PTM_RES_TX_LATENCY,PTM Responder TX Latency - Responder Transmit path latency (12 bit wide). For more details see the PTM section in the Databook. Note: This register field is sticky." line.long 0x4 "PTM_RES_RX_LATENCY_OFF,PTM Responder RX Latency. For more details. see the PTM section in the Databook." hexmask.long.tbyte 0x4 12.--31. 1. "RSVDP_12,Reserved for future use." hexmask.long.word 0x4 0.--11. 1. "PTM_RES_RX_LATENCY,PTM Responder RX Latency - Responder Receive path latency (12 bit wide). For more details see the PTM section in the Databook. Note: This register field is sticky." rgroup.long (0x40+0x418)++0x3 line.long 0x0 "PTM_RES_NOM_CLOCK_T_OFF,PTM Responder Nominal Clock Period. For more details. see the PTM section in the Databook." hexmask.long.byte 0x0 24.--31. 1. "RSVDP_24,Reserved for future use." hexmask.long.byte 0x0 16.--23. 1. "PTM_RES_NOM_CLOCK_T_INT,PTM Responder Nominal Clock Period Integral - Integral part of the nominal PTM local clock period in nanoseconds. For more details see the PTM section in the Databook. Note: This register field is sticky." hexmask.long.word 0x0 0.--15. 1. "PTM_RES_NOM_CLOCK_T_FRAC,PTM Responder Nominal Clock Period Fractional - Fractional part of the nominal PTM local clock period. LSB is 1/(2^16) nanoseconds. For more details see the PTM section in the Databook. Note: This register field is sticky." group.long (0x44+0x418)++0x3 line.long 0x0 "PTM_RES_SCALED_CLOCK_T_OFF,PTM Responder Scaled Clock Period. For more details. see the PTM section in the Databook." bitfld.long 0x0 31. "PTM_RES_SCALED_CLOCK_T_EN,PTM Responder Scaled Clock Period Enable - Use the programmed scaled PTM clock period rather than the nominal values. This bit is cleared when the core_clk rate starts to change and can only be set when the clock period change.." "0,1" hexmask.long.byte 0x0 24.--30. 1. "RSVDP_24,Reserved for future use." hexmask.long.byte 0x0 16.--23. 1. "PTM_RES_SCALED_CLOCK_T_INT,PTM Responder Scaled Clock Period Integral - Integral part of the nominal PTM local clock period in nanoseconds. For more details see the PTM section in the Databook. Note: This register field is sticky." newline hexmask.long.word 0x0 0.--15. 1. "PTM_RES_SCALED_CLOCK_T_FRAC,PTM Responder Scaled Clock Period Fractional - Fractional part of the nominal PTM local clock period. LSB is 1/(2^16) nanoseconds. For more details see the PTM section in the Databook. Note: This register field is sticky." tree.end tree "PF0_PM_CAP (PF PCI Power Management Capability Structure)" group.long (0x0+0x40)++0x7 line.long 0x0 "CAP_ID_NXT_PTR_REG,Power Management Capabilities Register." hexmask.long.byte 0x0 27.--31. 1. "PME_SUPPORT,PME_Support. This 5-bit field indicates the power states in which the function may generate a PME and/or forward PME messages. A value of 0b for any bit indicates that the function is not capable of asserting PME while in that power state. -.." bitfld.long 0x0 26. "D2_SUPPORT,D2_Support. If this bit is set this function supports the D2 Power Management state. Functions that do not support D2 must always return a value of 0b for this bit. Note: The access attributes of this field are as follows: - Wire: No access." "0,1" bitfld.long 0x0 25. "D1_SUPPORT,D1_Support. If this bit is set this function supports the D1 Power Management state. Functions that do not support D1 must always return a value of 0b for this bit. Note: The access attributes of this field are as follows: - Wire: No access." "0,1" bitfld.long 0x0 22.--24. "AUX_CURR,Aux_Current. This 3 bit field reports the Vaux auxiliary current requirements for the function. If this function implements the Data Register the controller hardwires this field to 000b. If PME_Support is 0 xxxxb (PME assertion from D3cold is.." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 21. "DSI,Device Specific Initialization. The DSI bit indicates whether special initialization of this function is required. When set indicates that the function requires a device specific initialization sequence following a transition to the D0uninitialized.." "0,1" bitfld.long 0x0 20. "PME_IMM_READI_RETURN_DO,Immediate_Readiness_on_Return_to_D0. - If this bit is a '1' this function is guaranteed to be ready to successfully complete valid accesses immediately after being set to D0. These accesses include configuration cycles and if.." "0,1" rbitfld.long 0x0 19. "PME_CLK,PME Clock. Does not apply to PCI Express the controller hardwires it to 0b. Note: This register field is sticky." "0,1" bitfld.long 0x0 16.--18. "PM_SPEC_VER,Version. This field provides the Power Management specification version. The controller hardwires this field to 011b for functions compliant to PCI Express Base Specification Revision 4.0 Version 1.0>. Note: The access attributes of this.." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x0 8.--15. 1. "PM_NEXT_POINTER,Next Capability Pointer. This field provides an offset into the function's configuration space pointing to the location of next item in the capabilities list. If there are no additional items in the capabilities list this field is set to.." hexmask.long.byte 0x0 0.--7. 1. "PM_CAP_ID,Capability ID. This field returns 01h to indicate that this is the PCI Power Management Capability. Each function may have only one item in its capability list with Capability ID set to 01h." line.long 0x4 "CON_STATUS_REG,Power Management Control and Status Register. This register is used to manage the PCI function's power management state as well as to enable/monitor PMEs." hexmask.long.byte 0x4 24.--31. 1. "DATA_REG_ADD_INFO,Data. This field is used to report the state dependent data requested by the Data_Select field. The value of this field is scaled by the value reported by the Data_Scale field." rbitfld.long 0x4 23. "BUS_PWR_CLK_CON_EN,Bus Power/Clock Control Enable. For a description of this standard PCIe register field see the PCI Express Base Specification." "0,1" rbitfld.long 0x4 22. "B2_B3_SUPPORT,B2B3 Support for D3hot. For a description of this standard PCIe register field see the PCI Express Base Specification." "0,1" hexmask.long.byte 0x4 16.--21. 1. "RSVDP_16,Reserved for future use." newline bitfld.long 0x4 15. "PME_STATUS,PME_Status. This bit is set when the function normally generates a PME signal. The value of this bit is not affected by the value of the PME_En bit. If PME_Support bit 31 of the Power Management Capabilities register is clear this bit is.." "0,1" rbitfld.long 0x4 13.--14. "DATA_SCALE,Data_Scale. This field indicates the scaling factor to be used when interpreting the value of the Data field. The value and meaning of this field varies depending on which data value has been selected by the Data_Select field. For more details.." "0,1,2,3" hexmask.long.byte 0x4 9.--12. 1. "DATA_SELECT,Data_Select. This 4-bit field is used to select which data is to be reported through the Data and Data_Scale field. If the Data field is not implemented this field must be hardwired to 0000b." bitfld.long 0x4 8. "PME_ENABLE,PME_En. - When set the function is permitted to generate a PME. - When clear the function is not permitted to generate a PME. If PME_Support is 1 xxxxb (PME generation from D3cold) or the function consumes Aux power and Aux power is.." "0,1" newline hexmask.long.byte 0x4 4.--7. 1. "RSVDP_4,Reserved for future use." bitfld.long 0x4 3. "NO_SOFT_RST,No_Soft_Reset. This bit indicates the state of the function after writing the PowerState field to transition the function from D3hot to D0. - When set this transition preserves internal function state. The function is in D0Active and no.." "0,1" rbitfld.long 0x4 2. "RSVDP_2,Reserved for future use." "0,1" bitfld.long 0x4 0.--1. "POWER_STATE,PowerState. This 2-bit field is used both to determine the current power state of a function and to set the function into a new power state. The definition of the field values is given below. You can write to this register; however the.." "D0,D1,D2,D3hot" tree.end tree "PF0_PCIE_CAP (PF PCI Express Capability Structure)" group.long (0x0+0x70)++0x33 line.long 0x0 "PCIE_CAP_ID_PCIE_NEXT_CAP_PTR_PCIE_CAP_REG,PCI Express Capabilities. ID. Next Pointer Register." rbitfld.long 0x0 31. "RSVDP_31,Reserved for future use." "0,1" rbitfld.long 0x0 30. "RSVD,Reserved." "0,1" newline hexmask.long.byte 0x0 25.--29. 1. "PCIE_INT_MSG_NUM,PCIE Interrupt Message Number. For a description of this standard PCIe register field see the PCI Express Base Specification. Interrupt Message Number. This field indicates which MSI/MSI-X vector is used for the interrupt message.." bitfld.long 0x0 24. "PCIE_SLOT_IMP,Slot Implemented. When set this bit indicates that the Link associated with this Port is connected to a slot (as compared to being connected to a system-integrated device or being disabled). This bit is valid for Downstream Ports. This bit.." "0,1" newline hexmask.long.byte 0x0 20.--23. 1. "PCIE_DEV_PORT_TYPE,Device/Port Type. Indicates the specific type of this PCI Express function. Note: Different functions in a Multi-Function Device can generally be of different types. Defined encodings for functions that implement a Type 00h PCI.." hexmask.long.byte 0x0 16.--19. 1. "PCIE_CAP_REG,Capability Version. Indicates PCI-SIG defined PCI Express Capability structure version number. A version of the specification that changes the PCI Express Capability structure in a way that is not otherwise identifiable (for example through.." newline hexmask.long.byte 0x0 8.--15. 1. "PCIE_CAP_NEXT_PTR,Next Capability Pointer. This field contains the offset to the next PCI Capability structure or 00h if no other items exist in the linked list of Capabilities. Note: The access attributes of this field are as follows: - Wire: No access." hexmask.long.byte 0x0 0.--7. 1. "PCIE_CAP_ID,Capability ID. Indicates the PCI Express Capability structure. This field must return a Capability ID of 10h indicating that this is a PCI Express Capability structure." line.long 0x4 "DEVICE_CAPABILITIES_REG,Device Capabilities Register. The Device Capabilities register identifies PCI Express device function specific capabilities." hexmask.long.word 0x4 16.--31. 1. "RSVDP_16,Reserved for future use." bitfld.long 0x4 15. "PCIE_CAP_ROLE_BASED_ERR_REPORT,Role-Based Error Reporting. When set this bit indicates that the function implements the functionality originally defined in the Error Reporting ECN for PCI Express Base Specification Revision 1.0a and later incorporated.." "0,1" newline hexmask.long.word 0x4 6.--14. 1. "RSVDP_6,Reserved for future use." bitfld.long 0x4 5. "PCIE_CAP_EXT_TAG_SUPP,Extended Tag Field Supported. This bit in combination with the 10-Bit Tag Requester Supported bit in the Device Capabilities 2 register indicates the maximum supported size of the Tag field as a Requester. This bit must be set if.." "0,1" newline bitfld.long 0x4 3.--4. "PCIE_CAP_PHANTOM_FUNC_SUPPORT,Phantom Functions Supported. This field indicates the support for use of unclaimed function numbers to extend the number of outstanding transactions allowed by logically combining unclaimed function numbers (called Phantom.." "0,1,2,3" bitfld.long 0x4 0.--2. "PCIE_CAP_MAX_PAYLOAD_SIZE,Max_Payload_Size Supported. This field indicates the maximum payload size that the function can support for TLPs. Defined encodings are: - 000b: 128 bytes max payload size - 001b: 256 bytes max payload size - 010b: 512 bytes max.." "0,1,2,3,4,5,6,7" line.long 0x8 "DEVICE_CONTROL_DEVICE_STATUS,Device Control and Device Status Register. This register controls PCI Express device specific parameters and provides information about PCI Express device (function) specific parameters." hexmask.long.word 0x8 22.--31. 1. "RSVDP_22,Reserved for future use." rbitfld.long 0x8 21. "PCIE_CAP_TRANS_PENDING,Transactions Pending. Endpoints: When set this bit indicates that the function has issued Non-Posted Requests that have not been completed. A Function reports this bit cleared only when all outstanding Non-Posted Requests have.." "0,1" newline rbitfld.long 0x8 20. "PCIE_CAP_AUX_POWER_DETECTED,AUX Power Detected. Functions that require Aux power report this bit as set if Aux power is detected by the function. This bit is derived by sampling the sys_aux_pwr_det input." "0,1" bitfld.long 0x8 19. "PCIE_CAP_UNSUPPORTED_REQ_DETECTED,Unsupported Request Detected. This bit indicates that the function received an Unsupported Request. Errors are logged in this register regardless of whether error reporting is enabled or not in the Device Control.." "0,1" newline bitfld.long 0x8 18. "PCIE_CAP_FATAL_ERR_DETECTED,Fatal Error Detected. This bit indicates status of Fatal errors detected. Errors are logged in this register regardless of whether error reporting is enabled or not in the Device Control register. For a Multi-Function device.." "0,1" bitfld.long 0x8 17. "PCIE_CAP_NON_FATAL_ERR_DETECTED,Non-Fatal Error Detected. This bit indicates status of Non-fatal errors detected. Errors are logged in this register regardless of whether error reporting is enabled or not in the Device Control register. For a.." "0,1" newline bitfld.long 0x8 16. "PCIE_CAP_CORR_ERR_DETECTED,Correctable Error Detected. This bit indicates status of correctable errors detected. Errors are logged in this register regardless of whether error reporting is enabled or not in the Device Control register. For a.." "0,1" bitfld.long 0x8 15. "PCIE_CAP_INITIATE_FLR,Initiate Function Level Reset (applicable to Endpoints with Function Level Reset Capability set to 1b). A write of 1b initiates Function Level Reset to the Function. The value read by software from this bit is always 0b." "0,1" newline bitfld.long 0x8 12.--14. "PCIE_CAP_MAX_READ_REQ_SIZE,Max_Read_Request_Size. This field sets the maximum Read Request size for the function as a Requester. The function must not generate Read Requests with a size exceeding the set value. Defined encodings for this field are: -.." "0,1,2,3,4,5,6,7" rbitfld.long 0x8 11. "PCIE_CAP_EN_NO_SNOOP,Enable No Snoop. If this bit is set the function is permitted to Set the No Snoop bit in the Requester Attributes of transactions it initiates that do not require hardware enforced cache coherency (see section 2.2.6.5 in PCI Express.." "0,1" newline bitfld.long 0x8 10. "PCIE_CAP_AUX_POWER_PM_EN,Aux Power PM Enable. This bit is derived by sampling the sys_aux_pwr_det input. When set this bit enables a function to draw Aux power independent of PME Aux power. Functions that require Aux power on legacy operating systems.." "0,1" rbitfld.long 0x8 9. "PCIE_CAP_PHANTOM_FUNC_EN,Phantom Functions Enable. This bit in combination with the 10-Bit Tag Requester Enable bit in the Device Control 2 register determines how many Tag field bits a Requester is permitted to use. When the 10-Bit Tag Requester.." "0,1" newline rbitfld.long 0x8 8. "PCIE_CAP_EXT_TAG_EN,Extended Tag Field Enable. This bit in combination with the 10-Bit Tag Requester Enable bit in the Device Control 2 register determines how many Tag field bits a Requester is permitted to use. When the 10-Bit Tag Requester Enable.." "0,1" bitfld.long 0x8 5.--7. "PCIE_CAP_MAX_PAYLOAD_SIZE_CS,Max_Payload_Size. This field sets maximum TLP payload size for the Function. As a Receiver the Function must handle TLPs as large as the set value. As a Transmitter the Function must not generate TLPs exceeding the set.." "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 4. "PCIE_CAP_EN_REL_ORDER,Enable Relaxed Ordering. If this bit is set the function is permitted to set the Relaxed Ordering bit in the Attributes field of transactions it initiates that do not require strong write ordering (for more details see section.." "0,1" bitfld.long 0x8 3. "PCIE_CAP_UNSUPPORT_REQ_REP_EN,Unsupported Request Reporting Enable. This bit in conjunction with other bits controls the signaling of Unsupported Request Errors by sending error Messages (for more details see section 6.2.5 and section 6.2.6 of PCI.." "0,1" newline bitfld.long 0x8 2. "PCIE_CAP_FATAL_ERR_REPORT_EN,Fatal Error Reporting Enable. This bit in conjunction with other bits controls sending ERR_FATAL Messages (for more details see section 6.2.5 and section 6.2.6 of of PCI Express Base Specification). For a Multi-Function.." "0,1" bitfld.long 0x8 1. "PCIE_CAP_NON_FATAL_ERR_REPORT_EN,Non-Fatal Error Reporting Enable. This bit in conjunction with other bits controls sending ERR_NONFATAL Messages (for more details see section 6.2.5 and Section 6.2.6 of PCI Express Base Specification). For a.." "0,1" newline bitfld.long 0x8 0. "PCIE_CAP_CORR_ERR_REPORT_EN,Correctable Error Reporting Enable. This bit in conjunction with other bits controls sending ERR_COR Messages (for more details see section 6.2.5 section 6.2.6 and section 6.2.10.2 of PCI Express Base Specification). For.." "0,1" line.long 0xC "LINK_CAPABILITIES_REG,Link Capabilities Register. The Link Capabilities register identifies PCI Express Link specific capabilities." hexmask.long.byte 0xC 24.--31. 1. "PCIE_CAP_PORT_NUM,Port Number. This field indicates the PCI Express Port number for the given PCI Express Link. Multi-Function Devices associated with an Upstream Port must report the same value in this field for all functions. Note: The access.." rbitfld.long 0xC 23. "RSVDP_23,Reserved for future use." "0,1" newline bitfld.long 0xC 22. "PCIE_CAP_ASPM_OPT_COMPLIANCE,ASPM Optionality Compliance. This bit must be set to 1b in all functions. Components implemented against certain earlier versions of this specification will have this bit set to 0b. Software is permitted to use the value of.." "0,1" bitfld.long 0xC 21. "PCIE_CAP_LINK_BW_NOT_CAP,Link Bandwidth Notification Capability. A value of 1b indicates support for the Link Bandwidth Notification status and interrupt mechanisms. This capability is required for all Root Ports and Switch Downstream Ports supporting.." "0,1" newline rbitfld.long 0xC 20. "PCIE_CAP_DLL_ACTIVE_REP_CAP,Data Link Layer Link Active Reporting Capable. For a Downstream Port the controller hardwires this bit to 1b if the component supports the optional capability of reporting the DL_Active state of the Data Link Control and.." "0,1" bitfld.long 0xC 19. "PCIE_CAP_SURPRISE_DOWN_ERR_REP_CAP,Surprise Down Error Reporting Capable. For a Downstream Port this bit must be set if the component supports the optional capability of detecting and reporting a Surprise Down error condition. For Upstream Ports and.." "0,1" newline rbitfld.long 0xC 18. "PCIE_CAP_CLOCK_POWER_MAN,Clock Power Management. For Upstream Ports a value of 1b in this bit indicates that the component tolerates the removal of any reference clock(s) via the 'clock request' (CLKREQ#) mechanism when the Link is in the L1 and L2/L3.." "0,1" bitfld.long 0xC 15.--17. "PCIE_CAP_L1_EXIT_LATENCY,L1 Exit Latency. This field indicates the L1 exit latency for the given PCI Express Link. The value reported indicates the length of time this Port requires to complete transition from ASPM L1 to L0. If ASPM L1 is not supported.." "0,1,2,3,4,5,6,7" newline bitfld.long 0xC 12.--14. "PCIE_CAP_L0S_EXIT_LATENCY,L0s Exit Latency. This field indicates the L0s exit latency for the given PCI Express Link. The value reported indicates the length of time this Port requires to complete transition from L0s to L0. If L0s is not supported the.." "0,1,2,3,4,5,6,7" bitfld.long 0xC 10.--11. "PCIE_CAP_ACTIVE_STATE_LINK_PM_SUPPORT,Active State Power Management (ASPM) Support. This field indicates the level of ASPM supported on the given PCI Express Link. For more details on ASPM support requirements see section 5.4.1 of PCI Express Base.." "0,1,2,3" newline hexmask.long.byte 0xC 4.--9. 1. "PCIE_CAP_MAX_LINK_WIDTH,Maximum Link Width. This field indicates the maximum Link width (xN - corresponding to N Lanes) implemented by the component. This value is permitted to exceed the number of Lanes routed to the slot (Downstream Port) adapter.." hexmask.long.byte 0xC 0.--3. 1. "PCIE_CAP_MAX_LINK_SPEED,Max Link Speed. This field indicates the maximum Link speed of the associated Port. The encoded value specifies a bit location in the Supported Link Speeds Vector (in the Link Capabilities 2 register) that corresponds to the.." line.long 0x10 "LINK_CONTROL_LINK_STATUS_REG,Link Control and Link Status Register. This register controls and provides information about PCI Express Link specific parameters." bitfld.long 0x10 31. "PCIE_CAP_LINK_AUTO_BW_STATUS,Link Autonomous Bandwidth Status. This bit is set by hardware to indicate that hardware has autonomously changed Link speed or width without the Port transitioning through DL_Down status for reasons other than to attempt to.." "0,1" bitfld.long 0x10 30. "PCIE_CAP_LINK_BW_MAN_STATUS,Link Bandwidth Management Status. This bit is set by hardware to indicate that either of the following has occurred without the Port transitioning through DL_Down status: - A Link retraining has completed following a write of.." "0,1" newline rbitfld.long 0x10 29. "PCIE_CAP_DLL_ACTIVE,Data Link Layer Link Active. This bit indicates the status of the Data Link Control and Management State Machine. It returns a 1b to indicate the DL_Active state 0b otherwise. This bit must be implemented if the Data Link Layer Link.." "0,1" bitfld.long 0x10 28. "PCIE_CAP_SLOT_CLK_CONFIG,Slot Clock Configuration. This bit indicates that the component uses the same physical reference clock that the platform provides on the connector. If the device uses an independent clock irrespective of the presence of a.." "0,1" newline rbitfld.long 0x10 27. "PCIE_CAP_LINK_TRAINING,Link Training. This read-only bit indicates that the Physical Layer LTSSM is in the Configuration or Recovery state or that 1b was written to the Retrain Link bit but Link training has not yet begun. Hardware clears this bit when.." "0,1" rbitfld.long 0x10 26. "RSVDP_26,Reserved for future use." "0,1" newline hexmask.long.byte 0x10 20.--25. 1. "PCIE_CAP_NEGO_LINK_WIDTH,Negotiated Link Width. This field indicates the negotiated width of the given PCI Express Link. Defined encodings are: -00 0001b: x1 -00 0010b: x2 -00 0100b: x4 -00 1000b: x8 -00 1100b: x12 -01 0000b: x16 -10 0000b: x32 All other.." hexmask.long.byte 0x10 16.--19. 1. "PCIE_CAP_LINK_SPEED,Current Link Speed. This field indicates the negotiated Link speed of the given PCI Express Link. The encoded value specifies a bit location in the Supported Link Speeds Vector (in the Link Capabilities 2 register) that corresponds to.." newline bitfld.long 0x10 14.--15. "PCIE_CAP_DRS_SIGNALING_CONTROL,DRS Signaling Control. Indicates the mechanism used to report reception of a DRS message. Must be implemented for Downstream Ports with the DRS Supported bit Set in the Link Capabilities 2 Register. Encodings are: - 00b:.." "0,1,2,3" rbitfld.long 0x10 12.--13. "RSVDP_12,Reserved for future use." "0,1,2,3" newline bitfld.long 0x10 11. "PCIE_CAP_LINK_AUTO_BW_INT_EN,Link Autonomous Bandwidth Management Interrupt Enable. When set this bit enables the generation of an interrupt to indicate that the Link Autonomous Bandwidth Status bit has been set. The write value is gated with the.." "0,1" bitfld.long 0x10 10. "PCIE_CAP_LINK_BW_MAN_INT_EN,Link Bandwidth Management Interrupt Enable. When set this bit enables the generation of an interrupt to indicate that the Link Bandwidth Management Status bit has been set. The write value is gated with the.." "0,1" newline bitfld.long 0x10 9. "PCIE_CAP_HW_AUTO_WIDTH_DISABLE,Hardware Autonomous Width Disable. When set this bit disables hardware from changing the Link width for reasons other than attempting to correct unreliable Link operation by reducing Link width. For a Multi-Function Device.." "0,1" bitfld.long 0x10 8. "PCIE_CAP_EN_CLK_POWER_MAN,Enable Clock Power Management. Applicable only for Upstream Ports and with form factors that support a 'Clock Request' (CLKREQ#) mechanism this bit operates as follows: - 0b: Clock power management is disabled and device must.." "0,1" newline bitfld.long 0x10 7. "PCIE_CAP_EXTENDED_SYNCH,Extended Synch. When set this bit forces the transmission of additional Ordered Sets when exiting the L0s state (see section 4.2.4.5 of PCI Express Base Specification) and when in the Recovery state (see section 4.2.6.4.1 of PCI.." "0,1" bitfld.long 0x10 6. "PCIE_CAP_COMMON_CLK_CONFIG,Common Clock Configuration. When set this bit indicates that this component and the component at the opposite end of this Link are operating with a distributed common reference clock. A value of 0b indicates that this.." "0,1" newline bitfld.long 0x10 5. "PCIE_CAP_RETRAIN_LINK,Retrain Link. A write of 1b to this bit initiates Link retraining by directing the Physical Layer LTSSM to the Recovery state. If the LTSSM is already in Recovery or Configuration re-entering Recovery is permitted but not required." "0,1" bitfld.long 0x10 4. "PCIE_CAP_LINK_DISABLE,Link Disable. This bit disables the Link by directing the LTSSM to the Disabled state when set; this bit is Reserved on Endpoints PCI Express to PCI/PCI-X bridges and Upstream Ports of Switches. Writes to this bit are immediately.." "0,1" newline bitfld.long 0x10 3. "PCIE_CAP_RCB,Read Completion Boundary (RCB). Root Ports: Indicates the RCB value for the Root Port. Refer to section 2.3.1.1 of PCI Express Base Specification for the definition of the parameter RCB. Defined encodings are: - 0b: 64 byte - 1b: 128 byte.." "0,1" rbitfld.long 0x10 2. "RSVDP_2,Reserved for future use." "0,1" newline bitfld.long 0x10 0.--1. "PCIE_CAP_ACTIVE_STATE_LINK_PM_CONTROL,Active State Power Management (ASPM) Control. This field controls the level of ASPM enabled on the given PCI Express Link. See section 5.4.1.3 of PCI Express Base Specification for requirements on when and how to.." "0,1,2,3" line.long 0x14 "SLOT_CAPABILITIES_REG,Slot Capabilities Register. The Slot Capabilities register identifies PCI Express slot specific capabilities." hexmask.long.word 0x14 19.--31. 1. "PCIE_CAP_PHY_SLOT_NUM,Physical Slot Number. This field indicates the physical slot number attached to this Port. This field must be hardware initialized to a value that assigns a slot number that is unique within the chassis regardless of the form.." bitfld.long 0x14 18. "PCIE_CAP_NO_CMD_CPL_SUPPORT,No Command Completed Support. When set this bit indicates that this slot does not generate software notification when an issued command is completed by the Hot-Plug Controller. This bit is only permitted to be set if the.." "0,1" newline bitfld.long 0x14 17. "PCIE_CAP_ELECTROMECH_INTERLOCK,Electromechanical Interlock Present. When set this bit indicates that an Electromechanical Interlock is implemented on the chassis for this slot. Note: The access attributes of this field are as follows: - Wire: No access." "0,1" bitfld.long 0x14 15.--16. "PCIE_CAP_SLOT_POWER_LIMIT_SCALE,Slot Power Limit Scale. Specifies the scale used for the Slot Power Limit Value (for more details see Section 6.9 of PCI Express Base Specification). Range of Values: - 00b: 1.0x - 01b: 0.1x - 10b: 0.01x - 11b: 0.001x.." "0,1,2,3" newline hexmask.long.byte 0x14 7.--14. 1. "PCIE_CAP_SLOT_POWER_LIMIT_VALUE,Slot Power Limit Value. In combination with the Slot Power Limit Scale value specifies the upper limit on power supplied by the slot (for more detais see Section 6.9 of PCI Express Base Specification) or by other means.." bitfld.long 0x14 6. "PCIE_CAP_HOT_PLUG_CAPABLE,Hot-Plug Capable. When set this bit indicates that this slot is capable of supporting hot-plug operations. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then R/W else R" "0,1" newline bitfld.long 0x14 5. "PCIE_CAP_HOT_PLUG_SURPRISE,Hot-Plug Surprise. When set this bit indicates that an adapter present in this slot might be removed from the system without any prior notification. This is a form factor specific capability. This bit is an indication to the.." "0,1" bitfld.long 0x14 4. "PCIE_CAP_POWER_INDICATOR,Power Indicator Present. When set this bit indicates that a Power Indicator is electrically controlled by the chassis for this slot. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if.." "0,1" newline bitfld.long 0x14 3. "PCIE_CAP_ATTENTION_INDICATOR,Attention Indicator Present. When set this bit indicates that an Attention Indicator is electrically controlled by the chassis. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if.." "0,1" bitfld.long 0x14 2. "PCIE_CAP_MRL_SENSOR,MRL Sensor Present. When set this bit indicates that an MRL Sensor is implemented on the chassis for this slot. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then R/W else R" "0,1" newline bitfld.long 0x14 1. "PCIE_CAP_POWER_CONTROLLER,Power Controller Present. When set this bit indicates that a software programmable Power Controller is implemented for this slot/adapter (depending on form factor). Note: The access attributes of this field are as follows: -.." "0,1" bitfld.long 0x14 0. "PCIE_CAP_ATTENTION_INDICATOR_BUTTON,Attention Button Present. When set this bit indicates that an Attention Button for this slot is electrically controlled by the chassis. Note: The access attributes of this field are as follows: - Wire: No access. -.." "0,1" line.long 0x18 "SLOT_CONTROL_SLOT_STATUS,Slot Control and Status Register. This register controls and provides information about PCI Express Slot specific parameters." hexmask.long.byte 0x18 25.--31. 1. "RSVDP_25,Reserved for future use." bitfld.long 0x18 24. "PCIE_CAP_DLL_STATE_CHANGED,Data Link Layer State Changed. This bit is set when the value reported in the Data Link Layer Link Active bit of the Link Status register is changed. In response to a Data Link Layer State Changed event software must read the.." "0,1" newline rbitfld.long 0x18 23. "PCIE_CAP_ELECTROMECH_INTERLOCK_STATUS,Electromechanical Interlock Status. If an Electromechanical Interlock is implemented this bit indicates the status of the Electromechanical Interlock. Defined encodings are: - 0b: Electromechanical Interlock.." "0,1" rbitfld.long 0x18 22. "PCIE_CAP_PRESENCE_DETECT_STATE,Presence Detect State. This bit indicates the presence of an adapter in the slot reflected by the logical 'OR' of the Physical Layer in-band presence detect mechanism and if present any out-of-band presence detect.." "0,1" newline rbitfld.long 0x18 21. "PCIE_CAP_MRL_SENSOR_STATE,MRL Sensor State. This bit reports the status of the MRL sensor if implemented. Defined encodings are: - 0b: MRL Closed - 1b: MRL Open" "0,1" bitfld.long 0x18 20. "PCIE_CAP_CMD_CPLD,Command Completed. If Command Completed notification is supported (if the No Command Completed Support bit in the Slot Capabilities register is 0b) this bit is set when a hot-plug command has completed and the Hot-Plug Controller is.." "0,1" newline bitfld.long 0x18 19. "PCIE_CAP_PRESENCE_DETECTED_CHANGED,Presence Detect Changed. This bit is set when the value reported in the Presence Detect State bit is changed." "0,1" bitfld.long 0x18 18. "PCIE_CAP_MRL_SENSOR_CHANGED,MRL Sensor Changed. If an MRL sensor is implemented this bit is set when a MRL Sensor state change is detected. If an MRL sensor is not implemented this bit must not be set." "0,1" newline bitfld.long 0x18 17. "PCIE_CAP_POWER_FAULT_DETECTED,Power Fault Detected. If a Power Controller that supports power fault detection is implemented this bit issSet when the Power Controller detects a power fault at this slot. Note: Depending on hardware capability it is.." "0,1" bitfld.long 0x18 16. "PCIE_CAP_ATTENTION_BUTTON_PRESSED,Attention Button Pressed. If an Attention Button is implemented this bit is set when the attention button is pressed. If an Attention Button is not supported this bit must not be set." "0,1" newline rbitfld.long 0x18 14.--15. "RSVDP_14,Reserved for future use." "0,1,2,3" bitfld.long 0x18 12. "PCIE_CAP_DLL_STATE_CHANGED_EN,Data Link Layer State Changed Enable. If the Data Link Layer Link Active Reporting capability is 1b this bit enables software notification when Data Link Layer Link Active bit is changed. If the Data Link Layer Link Active.." "0,1" newline bitfld.long 0x18 11. "PCIE_CAP_ELECTROMECH_INTERLOCK_CTRL,Electromechanical Interlock Control. If an Electromechanical Interlock is implemented a write of 1b to this bit causes the state of the interlock to toggle. A write of 0b to this bit has no effect. A read of this bit.." "0,1" bitfld.long 0x18 10. "PCIE_CAP_POWER_CONTROLLER_CTRL,Power Controller Control. If a Power Controller is implemented this bit when written sets the power state of the slot per the defined encodings. Reads of this bit must reflect the value from the latest write even if the.." "0,1" newline bitfld.long 0x18 8.--9. "PCIE_CAP_POWER_INDICATOR_CTRL,Power Indicator Control. If a Power Indicator is implemented writes to this field set the Power Indicator to the written state. Reads of this field must reflect the value from the latest write even if the corresponding.." "0,1,2,3" bitfld.long 0x18 6.--7. "PCIE_CAP_ATTENTION_INDICATOR_CTRL,Attention Indicator Control. If an Attention Indicator is implemented writes to this field set the Attention Indicator to the written state. Reads of this field must reflect the value from the latest write even if the.." "0,1,2,3" newline bitfld.long 0x18 5. "PCIE_CAP_HOT_PLUG_INT_EN,Hot-Plug Interrupt Enable. When set this bit enables generation of an interrupt on enabled hot-plug events. If the Hot Plug Capable bit in the Slot Capabilities register is clear this bit is permitted to be read-only with a.." "0,1" bitfld.long 0x18 4. "PCIE_CAP_CMD_CPL_INT_EN,Command Completed Interrupt Enable. If Command Completed notification is supported (if the No Command Completed Support bit in the Slot Capabilities register is 0b) when set this bit enables software notification when a hot-plug.." "0,1" newline bitfld.long 0x18 3. "PCIE_CAP_PRESENCE_DETECT_CHANGE_EN,Presence Detect Changed Enable. When set this bit enables software notification on a presence detect changed event (for more details see Section 6.7.3 of PCI Express Base Specification). If the Hot-Plug Capable bit in.." "0,1" bitfld.long 0x18 2. "PCIE_CAP_MRL_SENSOR_CHANGED_EN,MRL Sensor Changed Enable. When set this bit enables software notification on a MRL sensor changed event (for more details see Section 6.7.3 of PCI Express Base Specification). If the MRL Sensor Present bit in the Slot.." "0,1" newline bitfld.long 0x18 1. "PCIE_CAP_POWER_FAULT_DETECTED_EN,Power Fault Detected Enable. When set this bit enables software notification on a power fault event (for more details see Section 6.7.3 of PCI Express Base Specification). If a Power Controller that supports power fault.." "0,1" bitfld.long 0x18 0. "PCIE_CAP_ATTENTION_BUTTON_PRESSED_EN,Attention Button Pressed Enable. When set to 1b this bit enables software notification on an attention button pressed event (for more details see Section 6.7.3 of PCI Express Base Specification). If the Attention.." "0,1" line.long 0x1C "ROOT_CONTROL_ROOT_CAPABILITIES_REG,Root Control and Capabilities Register. This register controls PCI Express Root Complex specific parameters and identifies PCI Express Root Port specific capabilities." hexmask.long.word 0x1C 17.--31. 1. "RSVDP_17,Reserved for future use." bitfld.long 0x1C 16. "PCIE_CAP_CRS_SW_VISIBILITY,CRS Software Visibility Capable. For a description of this standard PCIe register field see the PCI Express Base Specification. CRS Software Visibility. When set this bit indicates that the Root Port is capable of returning.." "0,1" newline hexmask.long.word 0x1C 5.--15. 1. "RSVDP_5,Reserved for future use." bitfld.long 0x1C 4. "PCIE_CAP_CRS_SW_VISIBILITY_EN,CRS Software Visibility Enable. When set this bit enables the Root Port to return Configuration Request Retry Status (CRS) Completion Status to software (for more details see section 2.3.1 of PCI Express Base.." "0,1" newline bitfld.long 0x1C 3. "PCIE_CAP_PME_INT_EN,PME Interrupt Enable. When set this bit enables PME interrupt generation upon receipt of a PME Message as reflected in the PME Status bit (for more details see Table 7-29 of PCI Express Base Specification). A PME interrupt is also.." "0,1" bitfld.long 0x1C 2. "PCIE_CAP_SYS_ERR_ON_FATAL_ERR_EN,System Error on Fatal Error Enable. If set this bit indicates that a System Error should be generated if a Fatal error (ERR_FATAL) is reported by any of the devices in the Hierarchy Domain associated with this Root Port.." "0,1" newline bitfld.long 0x1C 1. "PCIE_CAP_SYS_ERR_ON_NON_FATAL_ERR_EN,System Error on Non-Fatal Error Enable. If set this bit indicates that a System Error should be generated if a Non-fatal error (ERR_NONFATAL) is reported by any of the devices in the Hierarchy Domain associated with.." "0,1" bitfld.long 0x1C 0. "PCIE_CAP_SYS_ERR_ON_CORR_ERR_EN,System Error on Correctable Error Enable. If set this bit indicates that a System Error should be generated if a correctable error (ERR_COR) is reported by any of the devices in the Hierarchy Domain associated with this.." "0,1" line.long 0x20 "ROOT_STATUS_REG,Root Status Register. The Root Status register provides information about PCI Express device specific parameters." hexmask.long.word 0x20 18.--31. 1. "RSVDP_18,Reserved for future use." rbitfld.long 0x20 17. "PCIE_CAP_PME_PENDING,PME Pending. This bit indicates that another PME is pending when the PME Status bit is s et. When the PME Status bit is cleared by software; the PME is delivered by hardware by setting the PME Status bit again and updating the PME.." "0,1" newline bitfld.long 0x20 16. "PCIE_CAP_PME_STATUS,PME Status. This bit indicates that PME was asserted by the PME Requester indicated in the PME Requester ID field. Subsequent PMEs are kept pending until the status register is cleared by software by writing a 1b." "0,1" hexmask.long.word 0x20 0.--15. 1. "PCIE_CAP_PME_REQ_ID,PME Requester ID. This field indicates the PCI Requester ID of the last PME Requester. This field is only valid when the PME Status bit is set." line.long 0x24 "DEVICE_CAPABILITIES2_REG,Device Capabilities 2 Register." bitfld.long 0x24 31. "PCIE_CAP_FRS_SUPPORTED,FRS Supported. When set indicates support for the optional Function Readiness Status (FRS) capability. Must be set for all Functions that support generation or reception capabilities of FRS Messages. Must not be set by Switch.." "0,1" hexmask.long.byte 0x24 24.--30. 1. "RSVDP_24,Reserved for future use." newline bitfld.long 0x24 22.--23. "PCIE_CAP2_CFG_MAX_END2END_TLP_PRFXS,Max End-End TLP Prefixes. Indicates the maximum number of End-End TLP Prefixes supported by this Function. For more details see Section 2.2.10.2 of PCI Express Base Specification. Values are: - 01b: 1 End-End TLP.." "0,1,2,3" bitfld.long 0x24 21. "PCIE_CAP2_CFG_END2END_TLP_PRFX_SUPPORT,End-End TLP Prefix Supported. Indicates whether End-End TLP Prefix support is offered by a Function. Values are: - 0b: No Support - 1b: Support is provided to receive TLPs containing End-End TLP Prefixes. All Ports.." "0,1" newline bitfld.long 0x24 20. "PCIE_CAP2_CFG_EXTND_FMT_SUPPORT,Extended Fmt Field Supported. If set the Function supports the 3-bit definition of the Fmt field. If clear the Function supports a 2-bit definition of the Fmt field. For more details see section 2.2 of PCI Express Base.." "0,1" rbitfld.long 0x24 17. "PCIE_CAP2_10_BIT_TAG_REQ_SUPPORT,10-Bit Tag Requester Supported. If this bit is set the Function supports 10-Bit Tag Requester capability; otherwise the Function does not. This bit must not be set if the 10-Bit Tag Completer Supported bit is clear." "0,1" newline rbitfld.long 0x24 16. "PCIE_CAP2_10_BIT_TAG_COMP_SUPPORT,10-Bit Tag Completer Supported. If this bit is set the Function supports 10-Bit Tag Completer capability; otherwise the Function does not. For more details see section 2.2.6.2. of PCI Express Base Specification." "0,1" rbitfld.long 0x24 13. "PCIE_CAP_TPH_CMPLT_SUPPORT_1,TPH Completer Supported Bit 1." "0,1" newline rbitfld.long 0x24 12. "PCIE_CAP_TPH_CMPLT_SUPPORT_0,TPH Completer Supported Bit 0. Value of this bit along with TPH Completer Supported Bit 1 indicates Completer support for TPH or Extended TPH. Applicable only to Root Ports and Endpoints. For all other Functions this field.." "0,1" bitfld.long 0x24 11. "PCIE_CAP_LTR_SUPP,LTR Mechanism Supported. A value of 1b indicates support for the optional Latency Tolerance Reporting (LTR) mechanism. Root Ports Switches and Endpoints are permitted to implement this capability. For a Multi-Function Device associated.." "0,1" newline rbitfld.long 0x24 10. "PCIE_CAP_NO_RO_EN_PR2PR_PAR,No RO-enabled PR-PR Passing. If this bit is set the routing element never carries out the passing permitted by Table 2-39 of PCI Express Base Specification entry A2b that is associated with the Relaxed Ordering Attribute.." "0,1" rbitfld.long 0x24 9. "PCIE_CAP_128_CAS_CPL_SUPP,128-bit CAS Completer Supported. Applicable to Functions with Memory Space BARs as well as all Root Ports; must be 0b otherwise. This bit must be set to 1b if the Function supports this optional capability. For more details see.." "0,1" newline rbitfld.long 0x24 8. "PCIE_CAP_64_ATOMIC_CPL_SUPP,64-bit AtomicOp Completer Supported. Applicable to Functions with Memory Space BARs as well as all Root Ports; must be 0b otherwise. Includes FetchAdd Swap and CAS AtomicOps. This bit must be set to 1b if the Function.." "0,1" rbitfld.long 0x24 7. "PCIE_CAP_32_ATOMIC_CPL_SUPP,32-bit AtomicOp Completer Supported. Applicable to Functions with Memory Space BARs as well as all Root Ports; must be 0b otherwise. Includes FetchAdd Swap and CAS AtomicOps. This bit must be set to 1b if the Function.." "0,1" newline rbitfld.long 0x24 6. "PCIE_CAP_ATOMIC_ROUTING_SUPP,AtomicOp Routing Supported. Applicable only to Switch Upstream Ports Switch Downstream Ports and Root Ports; must be 0b for other Function types. This bit must be set to 1b if the Port supports this optional capability. For.." "0,1" rbitfld.long 0x24 5. "PCIE_CAP_ARI_FORWARD_SUPPORT,ARI Forwarding Supported. Applicable only to Switch Downstream Ports and Root Ports; must be 0b for other Function types. This bit must be set to 1b if a Switch Downstream Port or Root Port supports this optional capability." "0,1" newline rbitfld.long 0x24 4. "PCIE_CAP_CPL_TIMEOUT_DISABLE_SUPPORT,Completion Timeout Disable Supported. A value of 1b indicates support for the Completion Timeout Disable mechanism. The Completion Timeout Disable mechanism is required for Endpoints that issue Requests on their own.." "0,1" hexmask.long.byte 0x24 0.--3. 1. "PCIE_CAP_CPL_TIMEOUT_RANGE,Completion Timeout Ranges Supported. This field indicates device Function support for the optional Completion Timeout programmability mechanism. This mechanism allows system software to modify the Completion Timeout value. This.." line.long 0x28 "DEVICE_CONTROL2_DEVICE_STATUS2_REG,Device Control 2 and Status 2 Register." hexmask.long.word 0x28 16.--31. 1. "RSVDP_16,Reserved for future use." bitfld.long 0x28 15. "PCIE_CTRL2_CFG_END2END_TLP_PFX_BLCK,End-End TLP Prefix Blocking. Controls whether the routing function is permitted to forward TLPs containing an End-End TLP Prefix. Values are: - 0b: Forwarding Enabled - Function is permitted to send TLPs with End-End.." "0,1" newline rbitfld.long 0x28 11. "RSVDP_11,Reserved for future use." "0,1" bitfld.long 0x28 10. "PCIE_CAP_LTR_EN,LTR Mechanism Enable. When set to 1b this bit enables Upstream Ports to send LTR messages and Downstream Ports to process LTR Messages. For a Multi-Function Device associated with an Upstream Port of a device that implements LTR the bit.." "0,1" newline rbitfld.long 0x28 5. "PCIE_CAP_ARI_FORWARD_SUPPORT_CS,ARI Forwarding Enable. When set the Downstream Port disables its traditional Device Number field being 0 enforcement when turning a Type 1 Configuration Request into a Type 0 Configuration Request permitting access to.." "0,1" bitfld.long 0x28 4. "PCIE_CAP_CPL_TIMEOUT_DISABLE,Completion Timeout Disable. When set this bit disables the Completion Timeout mechanism. This bit is required for all Functions that support the Completion Timeout Disable Capability. Functions that do not support this.." "0,1" newline hexmask.long.byte 0x28 0.--3. 1. "PCIE_CAP_CPL_TIMEOUT_VALUE,Completion Timeout Value. In device Functions that support Completion Timeout programmability this field allows system software to modify the Completion Timeout value. This field is applicable to Root Ports Endpoints that.." line.long 0x2C "LINK_CAPABILITIES2_REG,Link Capabilities 2 Register." bitfld.long 0x2C 31. "DRS_SUPPORTED,DRS Supported. When set indicates support for the optional Device Readiness Status (DRS) capability. Must be Set in Downstream Ports that support DRS. Must be Set in Downstream Ports that support FRS. For Upstream Ports that support DRS.." "0,1" hexmask.long.byte 0x2C 25.--30. 1. "RSVDP_25,Reserved for future use." newline hexmask.long.word 0x2C 9.--22. 1. "RSVDP_9,Reserved for future use." rbitfld.long 0x2C 8. "PCIE_CAP_CROSS_LINK_SUPPORT,Crosslink Supported. When set to 1b this bit indicates that the associated Port supports crosslinks (for more details see section 4.2.6.3.1 of PCI Express Base Specification). When set to 0b on a Port that supports Link.." "0,1" newline hexmask.long.byte 0x2C 1.--7. 1. "PCIE_CAP_SUPPORT_LINK_SPEED_VECTOR,Supported Link Speeds Vector. This field indicates the supported Link speed(s) of the associated Port. For each bit a value of 1b indicates that the corresponding Link speed is supported; otherwise the Link speed is.." rbitfld.long 0x2C 0. "RSVDP_0,Reserved for future use." "0,1" line.long 0x30 "LINK_CONTROL2_LINK_STATUS2_REG,Link Control 2 and Status 2 Register." bitfld.long 0x30 31. "DRS_MESSAGE_RECEIVED,DRS Message Received. This bit must be set whenever the Port receives a DRS Message. This bit must be cleared in DL_Down. This bit must be implemented in any Downstream Port where the DRS Supported bit is Set in the Link Capabilities.." "0,1" rbitfld.long 0x30 28.--30. "DOWNSTREAM_COMPO_PRESENCE,Downstream Component Presence. This field indicates the presence and DRS status for the Downstream Component if any connected to the Link; defined values are: - 000b: Link Down - Presence Not Determined - 001b: Link Down -.." "0,1,2,3,4,5,6,7" newline rbitfld.long 0x30 26.--27. "RSVDP_26,Reserved for future use." "0,1,2,3" bitfld.long 0x30 21. "PCIE_CAP_LINK_EQ_REQ,Link Equalization Request 8.0 GT/s. This bit is set by hardware to request the 8.0 GT/s Link equalization process to be performed on the Link. For more details see sections 4.2.3 and 4.2.6.4.2 of PCI Express Base Specification. For.." "0,1" newline rbitfld.long 0x30 20. "PCIE_CAP_EQ_CPL_P3,EEqualization 8.0 GT/s Phase 3 Successful. When set to 1b this bit indicates that Phase 3 of the 8.0 GT/s Transmitter Equalization procedure has successfully completed. Details of the Transmitter Equalization process and when this bit.." "0,1" rbitfld.long 0x30 19. "PCIE_CAP_EQ_CPL_P2,Equalization 8.0 GT/s Phase 2 Successful. When set to 1b this bit indicates that Phase 2 of the 8.0 GT/s Transmitter Equalization procedure has successfully completed. Details of the Transmitter Equalization process and when this bit.." "0,1" newline rbitfld.long 0x30 18. "PCIE_CAP_EQ_CPL_P1,Equalization 8.0 GT/s Phase 1 Successful. When set to 1b this bit indicates that Phase 1 of the 8.0 GT/s Transmitter Equalization procedure has successfully completed. Details of the Transmitter Equalization process and when this bit.." "0,1" rbitfld.long 0x30 17. "PCIE_CAP_EQ_CPL,Equalization 8.0 GT/s Complete. When set to 1b this bit indicates that the Transmitter Equalization procedure at the 8.0 GT/s data rate has completed. Details of the Transmitter Equalization process and when this bit needs to be set to.." "0,1" newline rbitfld.long 0x30 16. "PCIE_CAP_CURR_DEEMPHASIS,Current De-emphasis Level. When the Link is operating at 5.0 GT/s speed this bit reflects the level of de-emphasis. Encodings: - 1b: -3.5 dB - 0b: -6 dB The value in this bit is undefined when the Link is not operating at 5.0.." "0,1" hexmask.long.byte 0x30 12.--15. 1. "PCIE_CAP_COMPLIANCE_PRESET,Compliance Preset/De-emphasis. For 8.0 GT/s and higher Data Rate: This field sets the Transmitter Preset in Polling.Compliance state if the entry occurred due to the Enter Compliance bit being 1b. The encodings are defined in.." newline bitfld.long 0x30 11. "PCIE_CAP_COMPLIANCE_SOS,Compliance SOS. When set to 1b the LTSSM is required to send SKP Ordered Sets between sequences when sending the Compliance Pattern or Modified Compliance Pattern. For a Multi-Function Device associated with an Upstream Port the.." "0,1" bitfld.long 0x30 10. "PCIE_CAP_ENTER_MODIFIED_COMPLIANCE,Enter Modified Compliance. When this bit is set to 1b the device transmits Modified Compliance Pattern if the LTSSM enters Polling.Compliance substate. Components that support only the 2.5 GT/s speed are permitted to.." "0,1" newline bitfld.long 0x30 7.--9. "PCIE_CAP_TX_MARGIN,Transmit Margin - This field controls the value of the non-deemphasized voltage level at the Transmitter pins. This field is reset to 000b on entry to the LTSSM Polling.Configuration substate (see Chapter 4 of PCI Express Base.." "0,1,2,3,4,5,6,7" bitfld.long 0x30 6. "PCIE_CAP_SEL_DEEMPHASIS,Selectable De-emphasis. When the Link is operating at 5.0 GT/s speed this bit is used to control the transmit de-emphasis of the link in specific situations. For more details see section 4.2.6 of PCI Express Base Specification." "0,1" newline bitfld.long 0x30 5. "PCIE_CAP_HW_AUTO_SPEED_DISABLE,Hardware Autonomous Speed Disable. When set this bit disables hardware from changing the Link speed for device-specific reasons other than attempting to correct unreliable Link operation by reducing Link speed. Initial.." "0,1" bitfld.long 0x30 4. "PCIE_CAP_ENTER_COMPLIANCE,Enter Compliance. Software is permitted to force a Link to enter Compliance mode (at the speed indicated in the Target Link Speed field and the de-emphasis/preset level indicated by the Compliance Preset/De-emphasis field) by.." "0,1" newline hexmask.long.byte 0x30 0.--3. 1. "PCIE_CAP_TARGET_LINK_SPEED,Target Link Speed. For Downstream Ports this field sets an upper limit on Link operational speed by restricting the values advertised by the Upstream component in its training sequences. The encoded value specifies a bit.." tree.end tree "PF0_AER_CAP (PF Advanced Error Reporting Capability Structure)" group.long (0x0+0x100)++0x1B line.long 0x0 "AER_EXT_CAP_HDR_OFF,Advanced Error Reporting Extended Capability Header. For a description of this standard PCIe register. see the PCI Express Specification." hexmask.long.word 0x0 20.--31. 1. "NEXT_OFFSET,Next Capability Offset. For a description of this standard PCIe register field see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky).." hexmask.long.byte 0x0 16.--19. 1. "CAP_VERSION,Capability Version. For a description of this standard PCIe register field see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else.." hexmask.long.word 0x0 0.--15. 1. "CAP_ID,AER Extended Capability ID. For a description of this standard PCIe register field see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else.." line.long 0x4 "UNCORR_ERR_STATUS_OFF,Uncorrectable Error Status Register. For a description of this standard PCIe register. see the PCI Express Specification." hexmask.long.byte 0x4 27.--31. 1. "RSVDP_27,Reserved for future use." bitfld.long 0x4 25. "TLP_PRFX_BLOCKED_ERR_STATUS,TLP Prefix Blocked Error Status. For a description of this standard PCIe register field see the PCI Express Specification. Note: Not supported." "0,1" rbitfld.long 0x4 23. "RSVDP_23,Reserved for future use." "0,1" newline bitfld.long 0x4 22. "INTERNAL_ERR_STATUS,Uncorrectable Internal Error Status. For a description of this standard PCIe register field see the PCI Express Specification. The controller sets this bit when your application asserts app_err_bus[9]. It does not set this bit when.." "0,1" bitfld.long 0x4 20. "UNSUPPORTED_REQ_ERR_STATUS,Unsupported Request Error Status. For a description of this standard PCIe register field see the PCI Express Specification." "0,1" bitfld.long 0x4 19. "ECRC_ERR_STATUS,ECRC Error Status. For a description of this standard PCIe register field see the PCI Express Specification. Note:If CX_ECRC_ENABLE=0 the register field always reads 0." "0,1" newline bitfld.long 0x4 18. "MALF_TLP_ERR_STATUS,Malformed TLP Status. For a description of this standard PCIe register field see the PCI Express Specification." "0,1" bitfld.long 0x4 17. "REC_OVERFLOW_ERR_STATUS,Receiver Overflow Status. For a description of this standard PCIe register field see the PCI Express Specification." "0,1" bitfld.long 0x4 16. "UNEXP_CMPLT_ERR_STATUS,Unexpected Completion Status. For a description of this standard PCIe register field see the PCI Express Specification." "0,1" newline bitfld.long 0x4 15. "CMPLT_ABORT_ERR_STATUS,Completer Abort Status. For a description of this standard PCIe register field see the PCI Express Specification." "0,1" bitfld.long 0x4 14. "CMPLT_TIMEOUT_ERR_STATUS,Completion Timeout Status. For a description of this standard PCIe register field see the PCI Express Specification." "0,1" bitfld.long 0x4 13. "FC_PROTOCOL_ERR_STATUS,Flow Control Protocol Error Status. For a description of this standard PCIe register field see the PCI Express Specification." "0,1" newline bitfld.long 0x4 12. "POIS_TLP_ERR_STATUS,Poisoned TLP Status. For a description of this standard PCIe register field see the PCI Express Specification." "0,1" hexmask.long.byte 0x4 6.--11. 1. "RSVDP_6,Reserved for future use." bitfld.long 0x4 5. "SURPRISE_DOWN_ERR_STATUS,Surprise Down Error Status (Optional). For a description of this standard PCIe register field see the PCI Express Specification." "0,1" newline bitfld.long 0x4 4. "DL_PROTOCOL_ERR_STATUS,Data Link Protocol Error Status. For a description of this standard PCIe register field see the PCI Express Specification." "0,1" hexmask.long.byte 0x4 0.--3. 1. "RSVDP_0,Reserved for future use." line.long 0x8 "UNCORR_ERR_MASK_OFF,Uncorrectable Error Mask Register. For a description of this standard PCIe register. see the PCI Express Specification." hexmask.long.byte 0x8 27.--31. 1. "RSVDP_27,Reserved for future use." bitfld.long 0x8 25. "TLP_PRFX_BLOCKED_ERR_MASK,TLP Prefix Blocked Error Mask. For a description of this standard PCIe register field see the PCI Express Specification. Note: Not supported. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi:.." "0,1" rbitfld.long 0x8 23. "RSVDP_23,Reserved for future use." "0,1" newline bitfld.long 0x8 22. "INTERNAL_ERR_MASK,Uncorrectable Internal Error Mask (Optional). For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." "0,1" rbitfld.long 0x8 21. "ACS_VIOLATION_MASK,ACS Violation Mask. Setting the ACS Violation Mask bit disables error logging and signaling for ACS Violation errors. The bit is Read-Only Zero for upstream ports when ACS P2P Egress Control Enable is not set. For a description of.." "0,1" bitfld.long 0x8 20. "UNSUPPORTED_REQ_ERR_MASK,Unsupported Request Error Mask. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." "0,1" newline bitfld.long 0x8 19. "ECRC_ERR_MASK,ECRC Error Mask (Optional). For a description of this standard PCIe register field see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W (sticky) Note: This register.." "0,1" bitfld.long 0x8 18. "MALF_TLP_ERR_MASK,Malformed TLP Mask. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." "0,1" bitfld.long 0x8 17. "REC_OVERFLOW_ERR_MASK,Receiver Overflow Mask (Optional). For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." "0,1" newline bitfld.long 0x8 16. "UNEXP_CMPLT_ERR_MASK,Unexpected Completion Mask. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." "0,1" bitfld.long 0x8 15. "CMPLT_ABORT_ERR_MASK,Completer Abort Error Mask (Optional). For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." "0,1" bitfld.long 0x8 14. "CMPLT_TIMEOUT_ERR_MASK,Completion Timeout Error Mask. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." "0,1" newline bitfld.long 0x8 13. "FC_PROTOCOL_ERR_MASK,Flow Control Protocol Error Mask. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." "0,1" bitfld.long 0x8 12. "POIS_TLP_ERR_MASK,Poisoned TLP Error Mask. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." "0,1" hexmask.long.byte 0x8 6.--11. 1. "RSVDP_6,Reserved for future use." newline rbitfld.long 0x8 5. "SURPRISE_DOWN_ERR_MASK,Surprise Down Error Mask. For a description of this standard PCIe register field see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi:.." "0,1" bitfld.long 0x8 4. "DL_PROTOCOL_ERR_MASK,Data Link Protocol Error Mask. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." "0,1" hexmask.long.byte 0x8 0.--3. 1. "RSVDP_0,Reserved for future use." line.long 0xC "UNCORR_ERR_SEV_OFF,Uncorrectable Error Severity Register. For a description of this standard PCIe register. see the PCI Express Specification." hexmask.long.byte 0xC 27.--31. 1. "RSVDP_27,Reserved for future use." bitfld.long 0xC 25. "TLP_PRFX_BLOCKED_ERR_SEVERITY,TLP Prefix Blocked Error Severity (Optional). For a description of this standard PCIe register field see the PCI Express Specification. Note: Not supported. Note: The access attributes of this field are as follows: - Wire:.." "0,1" rbitfld.long 0xC 24. "ATOMIC_EGRESS_BLOCKED_ERR_SEVERITY,AtomicOp Egress Blocked Severity (Optional). For a description of this standard PCIe register field see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi:.." "0,1" newline rbitfld.long 0xC 23. "RSVDP_23,Reserved for future use." "0,1" bitfld.long 0xC 22. "INTERNAL_ERR_SEVERITY,Uncorrectable Internal Error Severity (Optional). For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." "0,1" bitfld.long 0xC 20. "UNSUPPORTED_REQ_ERR_SEVERITY,Unsupported Request Error Severity. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." "0,1" newline bitfld.long 0xC 19. "ECRC_ERR_SEVERITY,ECRC Error Severity (Optional). For a description of this standard PCIe register field see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W (sticky) Note: This.." "0,1" bitfld.long 0xC 18. "MALF_TLP_ERR_SEVERITY,Malformed TLP Severity. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." "0,1" bitfld.long 0xC 17. "REC_OVERFLOW_ERR_SEVERITY,Receiver Overflow Error Severity (Optional). For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." "0,1" newline bitfld.long 0xC 16. "UNEXP_CMPLT_ERR_SEVERITY,Unexpected Completion Error Severity. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." "0,1" bitfld.long 0xC 15. "CMPLT_ABORT_ERR_SEVERITY,Completer Abort Error Severity (Optional). For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." "0,1" bitfld.long 0xC 14. "CMPLT_TIMEOUT_ERR_SEVERITY,Completion Timeout Error Severity. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." "0,1" newline bitfld.long 0xC 13. "FC_PROTOCOL_ERR_SEVERITY,Flow Control Protocol Error Severity (Optional). For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." "0,1" bitfld.long 0xC 12. "POIS_TLP_ERR_SEVERITY,Poisoned TLP Severity. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." "0,1" hexmask.long.byte 0xC 6.--11. 1. "RSVDP_6,Reserved for future use." newline rbitfld.long 0xC 5. "SURPRISE_DOWN_ERR_SVRITY,Surprise Down Error Severity (Optional). For a description of this standard PCIe register field see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi:.." "0,1" bitfld.long 0xC 4. "DL_PROTOCOL_ERR_SEVERITY,Data Link Protocol Error Severity. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." "0,1" hexmask.long.byte 0xC 0.--3. 1. "RSVDP_0,Reserved for future use." line.long 0x10 "CORR_ERR_STATUS_OFF,Correctable Error Status Register. For a description of this standard PCIe register. see the PCI Express Specification." hexmask.long.word 0x10 16.--31. 1. "RSVDP_16,Reserved for future use." bitfld.long 0x10 15. "HEADER_LOG_OVERFLOW_STATUS,Header Log Overflow Error Status (Optional). For a description of this standard PCIe register field see the PCI Express Specification." "0,1" bitfld.long 0x10 14. "CORRECTED_INT_ERR_STATUS,Corrected Internal Error Status (Optional). For a description of this standard PCIe register field see the PCI Express Specification." "0,1" newline bitfld.long 0x10 13. "ADVISORY_NON_FATAL_ERR_STATUS,Advisory Non-Fatal Error Status. For a description of this standard PCIe register field see the PCI Express Specification." "0,1" bitfld.long 0x10 12. "RPL_TIMER_TIMEOUT_STATUS,Replay Timer Timeout Status. For a description of this standard PCIe register field see the PCI Express Specification." "0,1" rbitfld.long 0x10 9.--11. "RSVDP_9,Reserved for future use." "0,1,2,3,4,5,6,7" newline bitfld.long 0x10 8. "REPLAY_NO_ROLEOVER_STATUS,REPLAY_NUM Rollover Status. For a description of this standard PCIe register field see the PCI Express Specification." "0,1" bitfld.long 0x10 7. "BAD_DLLP_STATUS,Bad DLLP Status. For a description of this standard PCIe register field see the PCI Express Specification." "0,1" bitfld.long 0x10 6. "BAD_TLP_STATUS,Bad TLP Status. For a description of this standard PCIe register field see the PCI Express Specification." "0,1" newline hexmask.long.byte 0x10 1.--5. 1. "RSVDP_1,Reserved for future use." bitfld.long 0x10 0. "RX_ERR_STATUS,Receiver Error Status (Optional). For a description of this standard PCIe register field see the PCI Express Specification." "0,1" line.long 0x14 "CORR_ERR_MASK_OFF,Correctable Error Mask Register. For a description of this standard PCIe register. see the PCI Express Specification." hexmask.long.word 0x14 16.--31. 1. "RSVDP_16,Reserved for future use." bitfld.long 0x14 15. "HEADER_LOG_OVERFLOW_MASK,Header Log Overflow Error Mask (Optional). For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." "0,1" bitfld.long 0x14 14. "CORRECTED_INT_ERR_MASK,Corrected Internal Error Mask (Optional). For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." "0,1" newline bitfld.long 0x14 13. "ADVISORY_NON_FATAL_ERR_MASK,Advisory Non-Fatal Error Mask. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." "0,1" bitfld.long 0x14 12. "RPL_TIMER_TIMEOUT_MASK,Replay Timer Timeout Mask. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." "0,1" rbitfld.long 0x14 9.--11. "RSVDP_9,Reserved for future use." "0,1,2,3,4,5,6,7" newline bitfld.long 0x14 8. "REPLAY_NO_ROLEOVER_MASK,REPLAY_NUM Rollover Mask. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." "0,1" bitfld.long 0x14 7. "BAD_DLLP_MASK,Bad DLLP Mask. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." "0,1" bitfld.long 0x14 6. "BAD_TLP_MASK,Bad TLP Mask. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." "0,1" newline hexmask.long.byte 0x14 1.--5. 1. "RSVDP_1,Reserved for future use." bitfld.long 0x14 0. "RX_ERR_MASK,Receiver Error Mask (Optional). For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." "0,1" line.long 0x18 "ADV_ERR_CAP_CTRL_OFF,Advanced Error Capabilities and Control Register. For a description of this standard PCIe register. see the PCI Express Specification." hexmask.long.tbyte 0x18 13.--31. 1. "RSVDP_13,Reserved for future use." rbitfld.long 0x18 12. "CTO_PRFX_HDR_LOG_CAP,TLP Prefix Log Present. For a description of this standard PCIe register field see the PCI Express Specification." "0,1" rbitfld.long 0x18 11. "TLP_PRFX_LOG_PRESENT,Completion Timeout Prefix/Header Log Capable. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." "0,1" newline rbitfld.long 0x18 10. "MULTIPLE_HEADER_EN,Multiple Header Recording Enable. For a description of this standard PCIe register field see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R (sticky) Note: This.." "0,1" rbitfld.long 0x18 9. "MULTIPLE_HEADER_CAP,Multiple Header Recording Capable. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." "0,1" bitfld.long 0x18 8. "ECRC_CHECK_EN,ECRC Check Enable. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." "0,1" newline rbitfld.long 0x18 7. "ECRC_CHECK_CAP,ECRC Check Capable. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." "0,1" bitfld.long 0x18 6. "ECRC_GEN_EN,ECRC Generation Enable. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." "0,1" rbitfld.long 0x18 5. "ECRC_GEN_CAP,ECRC Generation Capable. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." "0,1" newline hexmask.long.byte 0x18 0.--4. 1. "FIRST_ERR_POINTER,First Error Pointer. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." rgroup.long (0x1C+0x100)++0xF line.long 0x0 "HDR_LOG_0_OFF,Header Log Register 0. For a description of this standard PCIe register. see the PCI Express Specification." hexmask.long.byte 0x0 24.--31. 1. "FIRST_DWORD_FOURTH_BYTE,Byte 3 of Header log register of First 32 bit Data Word. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." hexmask.long.byte 0x0 16.--23. 1. "FIRST_DWORD_THIRD_BYTE,Byte 2 of Header log register of First 32 bit Data Word. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." hexmask.long.byte 0x0 8.--15. 1. "FIRST_DWORD_SECOND_BYTE,Byte 1 of Header log register of First 32 bit Data Word. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." newline hexmask.long.byte 0x0 0.--7. 1. "FIRST_DWORD_FIRST_BYTE,Byte 0 of Header log register of First 32 bit Data Word. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." line.long 0x4 "HDR_LOG_1_OFF,Header Log Register 1. For a description of this standard PCIe register. see the PCI Express Specification." hexmask.long.byte 0x4 24.--31. 1. "SECOND_DWORD_FOURTH_BYTE,Byte 3 of Header log register of Second 32 bit Data Word. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." hexmask.long.byte 0x4 16.--23. 1. "SECOND_DWORD_THIRD_BYTE,Byte 2 of Header log register of Second 32 bit Data Word. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." hexmask.long.byte 0x4 8.--15. 1. "SECOND_DWORD_SECOND_BYTE,Byte 1 of Header log register of Second 32 bit Data Word. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." newline hexmask.long.byte 0x4 0.--7. 1. "SECOND_DWORD_FIRST_BYTE,Byte 0 of Header log register of Second 32 bit Data Word. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." line.long 0x8 "HDR_LOG_2_OFF,Header Log Register 2. For a description of this standard PCIe register. see the PCI Express Specification." hexmask.long.byte 0x8 24.--31. 1. "THIRD_DWORD_FOURTH_BYTE,Byte 3 of Header log register of Third 32 bit Data Word. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." hexmask.long.byte 0x8 16.--23. 1. "THIRD_DWORD_THIRD_BYTE,Byte 2 of Header log register of Third 32 bit Data Word. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." hexmask.long.byte 0x8 8.--15. 1. "THIRD_DWORD_SECOND_BYTE,Byte 1 of Header log register of Third 32 bit Data Word. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." newline hexmask.long.byte 0x8 0.--7. 1. "THIRD_DWORD_FIRST_BYTE,Byte 0 of Header log register of Third 32 bit Data Word. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." line.long 0xC "HDR_LOG_3_OFF,Header Log Register 3. For a description of this standard PCIe register. see the PCI Express Specification." hexmask.long.byte 0xC 24.--31. 1. "FOURTH_DWORD_FOURTH_BYTE,Byte 3 of Header log register of Fourth 32 bit Data Word. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." hexmask.long.byte 0xC 16.--23. 1. "FOURTH_DWORD_THIRD_BYTE,Byte 2 of Header log register of Fourth 32 bit Data Word. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." hexmask.long.byte 0xC 8.--15. 1. "FOURTH_DWORD_SECOND_BYTE,Byte 1 of Header log register of Fourth 32 bit Data Word. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." newline hexmask.long.byte 0xC 0.--7. 1. "FOURTH_DWORD_FIRST_BYTE,Byte 0 of Header log register of Fourth 32 bit Data Word. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." group.long (0x2C+0x100)++0x7 line.long 0x0 "ROOT_ERR_CMD_OFF,Root Error Command Register. For a description of this standard PCIe register. see the PCI Express Specification." hexmask.long 0x0 3.--31. 1. "RSVDP_3,Reserved for future use." bitfld.long 0x0 2. "FATAL_ERR_REPORTING_EN,Fatal Error Reporting Enable. For a description of this standard PCIe register field see the PCI Express Specification." "0,1" bitfld.long 0x0 1. "NON_FATAL_ERR_REPORTING_EN,Non-Fatal Error Reporting Enable. For a description of this standard PCIe register field see the PCI Express Specification." "0,1" newline bitfld.long 0x0 0. "CORR_ERR_REPORTING_EN,Correctable Error Reporting Enable. For a description of this standard PCIe register field see the PCI Express Specification." "0,1" line.long 0x4 "ROOT_ERR_STATUS_OFF,Root Error Status Register. For a description of this standard PCIe register. see the PCI Express Specification." hexmask.long.byte 0x4 27.--31. 1. "ADV_ERR_INT_MSG_NUM,Advanced Error Interrupt Message Number. For a description of this standard PCIe register field see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN.." hexmask.long.tbyte 0x4 7.--26. 1. "RSVDP_7,Reserved for future use." bitfld.long 0x4 6. "FATAL_ERR_MSG_RX,One or more Fatal Error Messages Received. For a description of this standard PCIe register field see the PCI Express Specification." "0,1" newline bitfld.long 0x4 5. "NON_FATAL_ERR_MSG_RX,One or more Non-Fatal Error Messages Received. For a description of this standard PCIe register field see the PCI Express Specification." "0,1" bitfld.long 0x4 4. "FIRST_UNCORR_FATAL,First Uncorrectable Error is Fatal. For a description of this standard PCIe register field see the PCI Express Specification." "0,1" bitfld.long 0x4 3. "MUL_ERR_FATAL_NON_FATAL_RX,Multiple Fatal or Non-Fatal Errors Received. For a description of this standard PCIe register field see the PCI Express Specification." "0,1" newline bitfld.long 0x4 2. "ERR_FATAL_NON_FATAL_RX,Fatal or Non-Fatal Error Received. For a description of this standard PCIe register field see the PCI Express Specification." "0,1" bitfld.long 0x4 1. "MUL_ERR_COR_RX,Multiple Correctable Errors Received. For a description of this standard PCIe register field see the PCI Express Specification." "0,1" bitfld.long 0x4 0. "ERR_COR_RX,Correctable Error Received. For a description of this standard PCIe register field see the PCI Express Specification." "0,1" rgroup.long (0x34+0x100)++0x13 line.long 0x0 "ERR_SRC_ID_OFF,Error Source Identification Register. For a description of this standard PCIe register. see the PCI Express Specification." hexmask.long.word 0x0 16.--31. 1. "ERR_FATAL_NON_FATAL_SOURCE_ID,Source of Fatal/Non-Fatal Error. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." hexmask.long.word 0x0 0.--15. 1. "ERR_COR_SOURCE_ID,Source of Correctable Error. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." line.long 0x4 "TLP_PREFIX_LOG_1_OFF,TLP Prefix Log Register 1. For a description of this standard PCIe register. see the PCI Express Specification." hexmask.long.byte 0x4 24.--31. 1. "CFG_TLP_PFX_LOG_1_FOURTH_BYTE,Byte 3 of Error TLP Prefix Log 1. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." hexmask.long.byte 0x4 16.--23. 1. "CFG_TLP_PFX_LOG_1_THIRD_BYTE,Byte 2 of Error TLP Prefix Log 1. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." hexmask.long.byte 0x4 8.--15. 1. "CFG_TLP_PFX_LOG_1_SECOND_BYTE,Byte 1 of Error TLP Prefix Log 1. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." newline hexmask.long.byte 0x4 0.--7. 1. "CFG_TLP_PFX_LOG_1_FIRST_BYTE,Byte 0 of Error TLP Prefix Log 1. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." line.long 0x8 "TLP_PREFIX_LOG_2_OFF,TLP Prefix Log Register 2. For a description of this standard PCIe register. see the PCI Express Specification." hexmask.long.byte 0x8 24.--31. 1. "CFG_TLP_PFX_LOG_2_FOURTH_BYTE,Byte 3 Error TLP Prefix Log 2. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." hexmask.long.byte 0x8 16.--23. 1. "CFG_TLP_PFX_LOG_2_THIRD_BYTE,Byte 2 Error TLP Prefix Log 2. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." hexmask.long.byte 0x8 8.--15. 1. "CFG_TLP_PFX_LOG_2_SECOND_BYTE,Byte 1 Error TLP Prefix Log 2. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." newline hexmask.long.byte 0x8 0.--7. 1. "CFG_TLP_PFX_LOG_2_FIRST_BYTE,Byte 0 Error TLP Prefix Log 2. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." line.long 0xC "TLP_PREFIX_LOG_3_OFF,TLP Prefix Log Register 3. For a description of this standard PCIe register. see the PCI Express Specification." hexmask.long.byte 0xC 24.--31. 1. "CFG_TLP_PFX_LOG_3_FOURTH_BYTE,Byte 3 Error TLP Prefix Log 3. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." hexmask.long.byte 0xC 16.--23. 1. "CFG_TLP_PFX_LOG_3_THIRD_BYTE,Byte 2 Error TLP Prefix Log 3. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." hexmask.long.byte 0xC 8.--15. 1. "CFG_TLP_PFX_LOG_3_SECOND_BYTE,Byte 1 Error TLP Prefix Log 3. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." newline hexmask.long.byte 0xC 0.--7. 1. "CFG_TLP_PFX_LOG_3_FIRST_BYTE,Byte 0 Error TLP Prefix Log 3. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." line.long 0x10 "TLP_PREFIX_LOG_4_OFF,TLP Prefix Log Register 4. For a description of this standard PCIe register. see the PCI Express Specification." hexmask.long.byte 0x10 24.--31. 1. "CFG_TLP_PFX_LOG_4_FOURTH_BYTE,Byte 3 Error TLP Prefix Log 4. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." hexmask.long.byte 0x10 16.--23. 1. "CFG_TLP_PFX_LOG_4_THIRD_BYTE,Byte 2 Error TLP Prefix Log 4. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." hexmask.long.byte 0x10 8.--15. 1. "CFG_TLP_PFX_LOG_4_SECOND_BYTE,Byte 1 Error TLP Prefix Log 4. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." newline hexmask.long.byte 0x10 0.--7. 1. "CFG_TLP_PFX_LOG_4_FIRST_BYTE,Byte 0 Error TLP Prefix Log 4. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." tree.end tree "PF0_MSI_CAP (PF MSI Capability Structure)" group.long (0x0+0x50)++0x13 line.long 0x0 "PCI_MSI_CAP_ID_NEXT_CTRL_REG,MSI Capability Header and Message Control Register." hexmask.long.byte 0x0 27.--31. 1. "RSVDP_27,Reserved for future use." bitfld.long 0x0 26. "PCI_MSI_EXT_DATA_EN,Extended Message Data Enable. - If set the function is enabled to provide Extended Message Data. - If clear the function is not enabled to provide Extended Message Data. Note: The access attributes of this field are as follows: -.." "0,1" bitfld.long 0x0 25. "PCI_MSI_EXT_DATA_CAP,Extended Message Data Capable. - If set the function is capable of providing Extended Message Data. - If clear the function does not support providing Extended Message Data. Note: The access attributes of this field are as follows:.." "0,1" newline rbitfld.long 0x0 24. "PCI_PVM_SUPPORT,Per-Vector Masking Capable. - If set the function supports MSI Per-Vector Masking. - If clear the function does not support MSI Per-Vector Masking. This bit must be set if the function is a PF or VF within an SR-IOV Device." "0,1" bitfld.long 0x0 23. "PCI_MSI_64_BIT_ADDR_CAP,64 bit address capable. - If set the function is capable of sending a 64-bit message address. - If clear the function is not capable of sending a 64-bit message address. This bit must be set if the function is a PCI Express.." "0,1" bitfld.long 0x0 20.--22. "PCI_MSI_MULTIPLE_MSG_EN,Multiple Message Enable. Software writes to this field to indicate the number of allocated vectors (equal to or less than the number of requested vectors). The number of allocated vectors is aligned to a power of two. If a.." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 17.--19. "PCI_MSI_MULTIPLE_MSG_CAP,Multiple Message Capable. System software reads this field to determine the number of requested vectors. The number of requested vectors must be aligned to a power of two (if a function requires three vectors it requests four by.." "0,1,2,3,4,5,6,7" bitfld.long 0x0 16. "PCI_MSI_ENABLE,MSI Enable. - If set and the MSI-X Enable bit in the MSI-X Message Control register is clear the function is permitted to use MSI to request service and is prohibited from using INTx interrupts. System configuration software sets this bit.." "0,1" hexmask.long.byte 0x0 8.--15. 1. "PCI_MSI_CAP_NEXT_OFFSET,Next Capability Pointer. This field contains the offset to the next PCI Capability structure or 00h if no other items exist in the linked list of Capabilities. Note: The access attributes of this field are as follows: - Wire: No.." newline hexmask.long.byte 0x0 0.--7. 1. "PCI_MSI_CAP_ID,Capability ID. Indicates the MSI Capability structure. This field returns a Capability ID of 05h indicating that this is an MSI Capability structure." line.long 0x4 "MSI_CAP_OFF_04H_REG,Message Address Register for MSI (Offset 04h)." hexmask.long 0x4 2.--31. 1. "PCI_MSI_CAP_OFF_04H,Message Address - System-specified message address. If the Message Enable bit (bit 16 of the PCI_MSI_CAP_ID_NEXT_CTRL_REG register) is set the contents of this field specify the DWORD-aligned address (Address[31:02]) for the MSI.." rbitfld.long 0x4 0.--1. "RSVDP_0,Reserved for future use." "0,1,2,3" line.long 0x8 "MSI_CAP_OFF_08H_REG,For a function that supports a 32-bit message address. - bits[31:16] of this register represent the Extended Message Data. and - bits[15:0] of this register represent the Message Data For a function that supports a 64-bit message.." hexmask.long.word 0x8 16.--31. 1. "PCI_MSI_CAP_OFF_0AH,For a function that supports a 32-bit message address this field contains Extended Message Data (System-specified message data). For the MSI Capability structures without per-vector masking it must be implemented if the Extended.." hexmask.long.word 0x8 0.--15. 1. "PCI_MSI_CAP_OFF_08H,For a function that supports a 32-bit message address this field contains Message Data (System-specified message data). If the Message Enable bit (bit 16 of the PCI_MSI_CAP_ID_NEXT_CTRL_REG) is set the function sends a DWORD Memory.." line.long 0xC "MSI_CAP_OFF_0CH_REG,For a function that supports a 32-bit message address. this register contains the Mask Bits when the Per-Vector Masking Capable bit (bit 24 of PCI_MSI_CAP_ID_NEXT_CTRL_REG) is set. For a function that supports a 64-bit message.." hexmask.long.word 0xC 16.--31. 1. "PCI_MSI_CAP_OFF_0EH,For a function that supports a 32-bit message address this field contains the upper Mask Bits when the Per Vector Masking Capable bit (PCI_MSI_CAP_ID_NEXT_CTRL_REG.PCI_PVM_SUPPORT) is set. For a function that supports a 64-bit.." hexmask.long.word 0xC 0.--15. 1. "PCI_MSI_CAP_OFF_0CH,For a function that supports a 32-bit message address this field contains the lower Mask Bits when the Per Vector Masking Capable bit (PCI_MSI_CAP_ID_NEXT_CTRL_REG.PCI_PVM_SUPPORT) is set. For a function that supports a 64-bit.." line.long 0x10 "MSI_CAP_OFF_10H_REG,For a function that supports a 32-bit message address. this register contains the Pending Bits when the Per-Vector Masking Capable bit (bit 24 of PCI_MSI_CAP_ID_NEXT_CTRL_REG) is set. For a function that supports a 64-bit message.." hexmask.long 0x10 0.--31. 1. "PCI_MSI_CAP_OFF_10H,Used for MSI when the Per Vector Masking Capable bit (PCI_MSI_CAP_ID_NEXT_CTRL_REG.PCI_PVM_SUPPORT) is set. For 32-bit contains Pending Bits. For 64-bit contains Mask Bits. For a description of this standard PCIe register field see.." rgroup.long (0x14+0x50)++0x3 line.long 0x0 "MSI_CAP_OFF_14H_REG,Pending Bits Register for MSI. This register is used for a function that supports a 64-bit message address when the Per-Vector Masking Capable bit (bit 24 of PCI_MSI_CAP_ID_NEXT_CTRL_REG) is set." hexmask.long 0x0 0.--31. 1. "PCI_MSI_CAP_OFF_14H,Pending Bits. For each pending bit that is set the function has a pending associated message." tree.end tree "PF0_MSIX_CAP (PF MSI-X Capability Structure)" group.long (0x0+0xB0)++0xB line.long 0x0 "PCI_MSIX_CAP_ID_NEXT_CTRL_REG,MSI-X Capability ID. Next Pointer. Control Registers. For a description of this standard PCIe register. see the PCI Express Base Specification." bitfld.long 0x0 31. "PCI_MSIX_ENABLE,MSI-X Enable. For a description of this standard PCIe register field see the PCI Express Base Specification." "0,1" bitfld.long 0x0 30. "PCI_MSIX_FUNCTION_MASK,Function Mask. For a description of this standard PCIe register field see the PCI Express Base Specification. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" "0,1" rbitfld.long 0x0 27.--29. "RSVDP_27,Reserved for future use." "0,1,2,3,4,5,6,7" newline hexmask.long.word 0x0 16.--26. 1. "PCI_MSIX_TABLE_SIZE,MSI-X Table Size. For a description of this standard PCIe register field see the PCI Express Base Specification. SRIOV Note: All VFs in a single PF have the same value for 'MSI-X Table Size' (PCI_MSIX_TABLE_SIZE field in.." hexmask.long.byte 0x0 8.--15. 1. "PCI_MSIX_CAP_NEXT_OFFSET,MSI-X Next Capability Pointer. For a description of this standard PCIe register field see the PCI Express Base Specification. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN.." hexmask.long.byte 0x0 0.--7. 1. "PCI_MSIX_CAP_ID,MSI-X Capability ID. For a description of this standard PCIe register field see the PCI Express Base Specification." line.long 0x4 "MSIX_TABLE_OFFSET_REG,MSI-X Table Offset and BIR Register. For a description of this standard PCIe register. see the PCI Express Base Specification." hexmask.long 0x4 3.--31. 1. "PCI_MSIX_TABLE_OFFSET,MSI-X Table Offset. For a description of this standard PCIe register field see the PCI Express Base Specification. SRIOV Note: All VFs in a single PF have the same value for 'MSI-X Table Offset' (PCI_MSIX_TABLE_OFFSET field in.." bitfld.long 0x4 0.--2. "PCI_MSIX_BIR,MSI-X Table BAR Indicator Register Field. For a description of this standard PCIe register field see the PCI Express Base Specification. SRIOV Note: All VFs in a single PF have the same value for 'MSI-X Table BAR Indicator Register'.." "0,1,2,3,4,5,6,7" line.long 0x8 "MSIX_PBA_OFFSET_REG,MSI-X PBA Offset and BIR Register. For a description of this standard PCIe register. see the PCI Express Base Specification." hexmask.long 0x8 3.--31. 1. "PCI_MSIX_PBA_OFFSET,MSI-X PBA Offset. For a description of this standard PCIe register field see the PCI Express Base Specification. SRIOV Note: All VFs in a single PF have the same value for 'MSI-X PBA Offset' (PCI_MSIX_PBA_OFFSET field in.." bitfld.long 0x8 0.--2. "PCI_MSIX_PBA_BIR,MSI-X PBA BIR. For a description of this standard PCIe register field see the PCI Express Base Specification. SRIOV Note: All VFs in a single PF have the same value for 'MSI-X PBA BIR' (PCI_MSIX_PBA_BIR field in.." "0,1,2,3,4,5,6,7" tree.end tree "PF0_MSIX_CAP_DBI2 (DBI2 Shadow Block: PF MSI-X Capability Structure)" rgroup.long (0x0+0x10B0)++0x3 line.long 0x0 "SHADOW_PCI_MSIX_CAP_ID_NEXT_CTRL_REG,MSI-X Capability ID. Next Pointer. Control Registers. For a description of this standard PCIe register. see the PCI Express Base Specification." hexmask.long.byte 0x0 27.--31. 1. "RSVDP_27,Reserved for future use." hexmask.long.word 0x0 16.--26. 1. "PCI_MSIX_TABLE_SIZE,MSI-X Table Size in the shadow register. Note: The access attributes of this field are as follows: - Wire: No access - Dbi: No access - Dbi2: if (DBI_RO_WR_EN == 1) then R/W else R Note: This register field is sticky." hexmask.long.word 0x0 0.--15. 1. "RSVDP_0,Reserved for future use." group.long 0x4++0x7 line.long 0x0 "SHADOW_MSIX_TABLE_OFFSET_REG,MSI-X Table Offset and BIR Register. For a description of this standard PCIe register. see the PCI Express Base Specification." hexmask.long 0x0 3.--31. 1. "PCI_MSIX_TABLE_OFFSET,MSI-X Table Offset. For a description of this standard PCIe register field see the PCI Express Base Specification. Note: The access attributes of this field are as follows: - Wire: No access - Dbi: No access - Dbi2: if.." bitfld.long 0x0 0.--2. "PCI_MSIX_BIR,MSI-X Table BAR Indicator Register Field. For a description of this standard PCIe register field see the PCI Express Base Specification. Note: The access attributes of this field are as follows: - Wire: No access - Dbi: No access - Dbi2: if.." "?,?,if,?,?,?,?,?" line.long 0x4 "SHADOW_MSIX_PBA_OFFSET_REG,MSI-X PBA Offset and BIR Register. For a description of this standard PCIe register. see the PCI Express Base Specification." hexmask.long 0x4 3.--31. 1. "PCI_MSIX_PBA_OFFSET,MSI-X PBA Offset. For a description of this standard PCIe register field see the PCI Express Base Specification. Note: The access attributes of this field are as follows: - Wire: No access - Dbi: No access - Dbi2: if (DBI_RO_WR_EN ==.." bitfld.long 0x4 0.--2. "PCI_MSIX_PBA_BIR,MSI-X PBA BIR. For a description of this standard PCIe register field see the PCI Express Base Specification. Note: The access attributes of this field are as follows: - Wire: No access - Dbi: No access - Dbi2: if (DBI_RO_WR_EN == 1 &&.." "?,?,if,?,?,?,?,?" tree.end tree "PF0_DMA_CAP (DMA Port Logic Structure)" group.long (0x0+0xC8000)++0x3 line.long 0x0 "DMA_CTRL_DATA_ARB_PRIOR_OFF,DMA Arbitration Scheme for TRGT1 Interface. This register is used to control traffic priorities among various sources that are delivered to your application through TRGT1 where 0x0 represents the highest priority. - Non-DMA Rx.." hexmask.long.tbyte 0x0 12.--31. 1. "RSVDP_12,Reserved for future use." bitfld.long 0x0 9.--11. "RDBUFF_TRGT_WEIGHT,DMA Read Channel MWr Requests. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 6.--8. "RD_CTRL_TRGT_WEIGHT,DMA Read Channel MRd Requests. For LL element/descriptor access. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" "0,1,2,3,4,5,6,7" bitfld.long 0x0 3.--5. "WR_CTRL_TRGT_WEIGHT,DMA Write Channel MRd Requests. For DMA data requests and LL element/descriptor access. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 0.--2. "RTRGT1_WEIGHT,Non-DMA Rx Requests. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" "0,1,2,3,4,5,6,7" group.long (0x8+0xC8000)++0xB line.long 0x0 "DMA_CTRL_OFF,DMA Number of Channels Register." hexmask.long.byte 0x0 26.--31. 1. "RSVDP_26,Reserved for future use." bitfld.long 0x0 25. "DIS_C2W_CACHE_RD,Disable DMA Read Channels 'completion to memory write' context cache pre-fetch function. Note: For internal debugging only. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" "0,1" newline bitfld.long 0x0 24. "DIS_C2W_CACHE_WR,Disable DMA Write Channels 'completion to memory write' context cache pre-fetch function. Note: For internal debugging only. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" "0,1" hexmask.long.byte 0x0 20.--23. 1. "RSVDP_20,Reserved for future use." newline hexmask.long.byte 0x0 16.--19. 1. "NUM_DMA_RD_CHAN,Number of Read Channels. You can read this register to determine the number of read channels the DMA controller has been configured to support." hexmask.long.word 0x0 4.--15. 1. "RSVDP_4,Reserved for future use." newline hexmask.long.byte 0x0 0.--3. 1. "NUM_DMA_WR_CHAN,Number of Write Channels. You can read this register to determine the number of write channels the DMA controller has been configured to support." line.long 0x4 "DMA_WRITE_ENGINE_EN_OFF,DMA Write Engine Enable Register." hexmask.long.byte 0x4 24.--31. 1. "RSVDP_24,Reserved for future use." bitfld.long 0x4 23. "DMA_WRITE_ENGINE_EN_HSHAKE_CH7,Enable Handshake for DMA Write Engine Channel 7. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" "0,1" newline bitfld.long 0x4 22. "DMA_WRITE_ENGINE_EN_HSHAKE_CH6,Enable Handshake for DMA Write Engine Channel 6. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" "0,1" bitfld.long 0x4 21. "DMA_WRITE_ENGINE_EN_HSHAKE_CH5,Enable Handshake for DMA Write Engine Channel 5. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" "0,1" newline bitfld.long 0x4 20. "DMA_WRITE_ENGINE_EN_HSHAKE_CH4,Enable Handshake for DMA Write Engine Channel 4. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" "0,1" bitfld.long 0x4 19. "DMA_WRITE_ENGINE_EN_HSHAKE_CH3,Enable Handshake for DMA Write Engine Channel 3. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" "0,1" newline bitfld.long 0x4 18. "DMA_WRITE_ENGINE_EN_HSHAKE_CH2,Enable Handshake for DMA Write Engine Channel 2. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" "0,1" bitfld.long 0x4 17. "DMA_WRITE_ENGINE_EN_HSHAKE_CH1,Enable Handshake for DMA Write Engine Channel 1. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" "0,1" newline bitfld.long 0x4 16. "DMA_WRITE_ENGINE_EN_HSHAKE_CH0,Enable Handshake for DMA Write Engine Channel 0. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" "0,1" hexmask.long.word 0x4 1.--15. 1. "RSVDP_1,Reserved for future use." newline bitfld.long 0x4 0. "DMA_WRITE_ENGINE,DMA Write Engine Enable. - 1: Enable - 0: Disable (Soft Reset) For normal operation you must initially set this bit to '1' before any other software setup actions. You do not need to toggle or rewrite to this bit during normal.." "Disable,Enable" line.long 0x8 "DMA_WRITE_DOORBELL_OFF,DMA Write Doorbell Register." bitfld.long 0x8 31. "WR_STOP,Stop. Set in conjunction with the Doorbell Number field. The DMA write channel stops issuing requests sets the channel status to 'Stopped' and asserts the 'Abort' interrupt if it is enabled. Before setting the Stop bit you must read the.." "0,1" hexmask.long 0x8 3.--30. 1. "RSVDP_3,Reserved for future use." newline bitfld.long 0x8 0.--2. "WR_DOORBELL_NUM,Doorbell Number. You must write the channel number to this register to start the DMA write transfer for that channel. The DMA detects a write to this register field even if the value of this field does not change. You do not need to.." "0,1,2,3,4,5,6,7" group.long (0x18+0xC8000)++0x7 line.long 0x0 "DMA_WRITE_CHANNEL_ARB_WEIGHT_LOW_OFF,DMA Write Engine Channel Arbitration Weight Low Register. The 5-bit channel weight (for write channels 0-3) specifies the maximum number of TLP requests that the DMA can issue for that channel before it must return to.." hexmask.long.word 0x0 20.--31. 1. "RSVDP_20,Reserved for future use." hexmask.long.byte 0x0 15.--19. 1. "WRITE_CHANNEL3_WEIGHT,Channel 3 Weight. The weight is initialized by software before ringing the doorbell. The value is used by the channel weighted round robin arbiter to select the next channel read request. A value of '0' means that one TLP is issued.." newline hexmask.long.byte 0x0 10.--14. 1. "WRITE_CHANNEL2_WEIGHT,Channel 2 Weight. The weight is initialized by software before ringing the doorbell. The value is used by the channel weighted round robin arbiter to select the next channel read request. A value of '0' means that one TLP is issued.." hexmask.long.byte 0x0 5.--9. 1. "WRITE_CHANNEL1_WEIGHT,Channel 1 Weight. The weight is initialized by software before ringing the doorbell. The value is used by the channel weighted round robin arbiter to select the next channel read request. A value of '0' means that one TLP is issued.." newline hexmask.long.byte 0x0 0.--4. 1. "WRITE_CHANNEL0_WEIGHT,Channel 0 Weight. The weight is initialized by software before ringing the doorbell. The value is used by the channel weighted round robin arbiter to select the next channel read request. A value of '0' means that one TLP is issued.." line.long 0x4 "DMA_WRITE_CHANNEL_ARB_WEIGHT_HIGH_OFF,DMA Write Engine Channel Arbitration Weight High Register. The 5-bit channel weight (for write channels 4-7) specifies the maximum number of TLP requests that the DMA can issue for that channel before it must return.." hexmask.long.word 0x4 20.--31. 1. "RSVDP_20,Reserved for future use." hexmask.long.byte 0x4 15.--19. 1. "WRITE_CHANNEL7_WEIGHT,Channel 7 Weight. The weight is initialized by software before ringing the doorbell. The value is used by the channel weighted round robin arbiter to select the next channel read request. A value of '0' means that one TLP is issued.." newline hexmask.long.byte 0x4 10.--14. 1. "WRITE_CHANNEL6_WEIGHT,Channel 6 Weight. The weight is initialized by software before ringing the doorbell. The value is used by the channel weighted round robin arbiter to select the next channel read request. A value of '0' means that one TLP is issued.." hexmask.long.byte 0x4 5.--9. 1. "WRITE_CHANNEL5_WEIGHT,Channel 5 Weight. The weight is initialized by software before ringing the doorbell. The value is used by the channel weighted round robin arbiter to select the next channel read request. A value of '0' means that one TLP is issued.." newline hexmask.long.byte 0x4 0.--4. 1. "WRITE_CHANNEL4_WEIGHT,Channel 4 Weight. The weight is initialized by software before ringing the doorbell. The value is used by the channel weighted round robin arbiter to select the next channel read request. A value of '0' means that one TLP is issued.." group.long (0x2C+0xC8000)++0x7 line.long 0x0 "DMA_READ_ENGINE_EN_OFF,DMA Read Engine Enable Register." hexmask.long.byte 0x0 24.--31. 1. "RSVDP_24,Reserved for future use." bitfld.long 0x0 23. "DMA_READ_ENGINE_EN_HSHAKE_CH7,Enable Handshake for DMA Read Engine Channel 7. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" "0,1" newline bitfld.long 0x0 22. "DMA_READ_ENGINE_EN_HSHAKE_CH6,Enable Handshake for DMA Read Engine Channel 6. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" "0,1" bitfld.long 0x0 21. "DMA_READ_ENGINE_EN_HSHAKE_CH5,Enable Handshake for DMA Read Engine Channel 5. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" "0,1" newline bitfld.long 0x0 20. "DMA_READ_ENGINE_EN_HSHAKE_CH4,Enable Handshake for DMA Read Engine Channel 4. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" "0,1" bitfld.long 0x0 19. "DMA_READ_ENGINE_EN_HSHAKE_CH3,Enable Handshake for DMA Read Engine Channel 3. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" "0,1" newline bitfld.long 0x0 18. "DMA_READ_ENGINE_EN_HSHAKE_CH2,Enable Handshake for DMA Read Engine Channel 2. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" "0,1" bitfld.long 0x0 17. "DMA_READ_ENGINE_EN_HSHAKE_CH1,Enable Handshake for DMA Read Engine Channel 1. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" "0,1" newline bitfld.long 0x0 16. "DMA_READ_ENGINE_EN_HSHAKE_CH0,Enable Handshake for DMA Read Engine Channel 0. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" "0,1" hexmask.long.word 0x0 1.--15. 1. "RSVDP_1,Reserved for future use." newline bitfld.long 0x0 0. "DMA_READ_ENGINE,DMA Read Engine Enable. - 1: Enable - 0: Disable (Soft Reset) For normal operation you must initially set this bit to '1' before any other software setup actions. You do not need to toggle or rewrite to this bit during normal operation." "Disable,Enable" line.long 0x4 "DMA_READ_DOORBELL_OFF,DMA Read Doorbell Register." bitfld.long 0x4 31. "RD_STOP,Stop. Set in conjunction with the Doorbell Number field. The DMA read channel stops issuing requests sets the channel status to 'Stopped' and asserts the 'Abort' interrupt if it is enabled. Before setting the Stop bit you must read the channel.." "0,1" hexmask.long 0x4 3.--30. 1. "RSVDP_3,Reserved for future use." newline bitfld.long 0x4 0.--2. "RD_DOORBELL_NUM,Doorbell Number. You must write 0x0 to this register to start the DMA read transfer for that channel. The DMA detects a write to this register field even if the value of this field does not change. The range of this field is 0x0 to 0x7.." "0,1,2,3,4,5,6,7" group.long (0x38+0xC8000)++0x7 line.long 0x0 "DMA_READ_CHANNEL_ARB_WEIGHT_LOW_OFF,DMA Read Engine Channel Arbitration Weight Low Register. The 5-bit channel weight (for read channels 0-3) specifies the maximum number of TLP requests that the DMA can issue for that channel before it must return to.." hexmask.long.word 0x0 20.--31. 1. "RSVDP_20,Reserved for future use." hexmask.long.byte 0x0 15.--19. 1. "READ_CHANNEL3_WEIGHT,Channel 3 Weight. The weight is initialized by software before ringing the doorbell. The value is used by the channel weighted round robin arbiter to select the next channel read request. Note: The access attributes of this field are.." newline hexmask.long.byte 0x0 10.--14. 1. "READ_CHANNEL2_WEIGHT,Channel 2 Weight. The weight is initialized by software before ringing the doorbell. The value is used by the channel weighted round robin arbiter to select the next channel read request. Note: The access attributes of this field are.." hexmask.long.byte 0x0 5.--9. 1. "READ_CHANNEL1_WEIGHT,Channel 1 Weight. The weight is initialized by software before ringing the doorbell. The value is used by the channel weighted round robin arbiter to select the next channel read request. Note: The access attributes of this field are.." newline hexmask.long.byte 0x0 0.--4. 1. "READ_CHANNEL0_WEIGHT,Channel 0 Weight. The weight is initialized by software before ringing the doorbell. The value is used by the channel weighted round robin arbiter to select the next channel read request. Note: The access attributes of this field are.." line.long 0x4 "DMA_READ_CHANNEL_ARB_WEIGHT_HIGH_OFF,DMA Read Engine Channel Arbitration Weight High Register. The 5-bit channel weight (for read channels 4-7) specifies the maximum number of TLP requests that the DMA can issue for that channel before it must return to.." hexmask.long.word 0x4 20.--31. 1. "RSVDP_20,Reserved for future use." hexmask.long.byte 0x4 15.--19. 1. "READ_CHANNEL7_WEIGHT,Channel 7 Weight. The weight is initialized by software before ringing the doorbell. The value is used by the channel weighted round robin arbiter to select the next channel read request. Note: The access attributes of this field are.." newline hexmask.long.byte 0x4 10.--14. 1. "READ_CHANNEL6_WEIGHT,Channel 6 Weight. The weight is initialized by software before ringing the doorbell. The value is used by the channel weighted round robin arbiter to select the next channel read request. Note: The access attributes of this field are.." hexmask.long.byte 0x4 5.--9. 1. "READ_CHANNEL5_WEIGHT,Channel 5 Weight. The weight is initialized by software before ringing the doorbell. The value is used by the channel weighted round robin arbiter to select the next channel read request. Note: The access attributes of this field are.." newline hexmask.long.byte 0x4 0.--4. 1. "READ_CHANNEL4_WEIGHT,Channel 4 Weight. The weight is initialized by software before ringing the doorbell. The value is used by the channel weighted round robin arbiter to select the next channel read request. Note: The access attributes of this field are.." group.long (0x4C+0xC8000)++0x3 line.long 0x0 "DMA_WRITE_INT_STATUS_OFF,DMA Write Interrupt Status Register." hexmask.long.byte 0x0 24.--31. 1. "RSVDP_24,Reserved for future use." hexmask.long.byte 0x0 16.--23. 1. "WR_ABORT_INT_STATUS,Abort Interrupt Status. The DMA write channel has detected an error or you manually stopped the transfer as described in 'Error Handling Assistance by Remote Software'. Each bit corresponds to a DMA channel. Bit [0] corresponds to.." newline hexmask.long.byte 0x0 8.--15. 1. "RSVDP_8,Reserved for future use." hexmask.long.byte 0x0 0.--7. 1. "WR_DONE_INT_STATUS,Done Interrupt Status. The DMA write channel has successfully completed the DMA transfer. For more details see 'Interrupts and Error Handling'. Each bit corresponds to a DMA channel. Bit [0] corresponds to channel 0. - Enabling: For.." group.long (0x54+0xC8000)++0x7 line.long 0x0 "DMA_WRITE_INT_MASK_OFF,DMA Write Interrupt Mask Register." hexmask.long.byte 0x0 24.--31. 1. "RSVDP_24,Reserved for future use." hexmask.long.byte 0x0 16.--23. 1. "WR_ABORT_INT_MASK,Abort Interrupt Mask. Prevents the Abort interrupt status field in the DMA write interrupt status register from asserting the edma_int output. Each bit corresponds to a DMA channel. Bit [0] corresponds to channel 0. Note: The access.." newline hexmask.long.byte 0x0 8.--15. 1. "RSVDP_8,Reserved for future use." hexmask.long.byte 0x0 0.--7. 1. "WR_DONE_INT_MASK,Done Interrupt Mask. Prevents the Done interrupt status field in the DMA write interrupt status register from asserting the edma_int output. Each bit corresponds to a DMA channel. Bit [0] corresponds to channel 0. Note: The access.." line.long 0x4 "DMA_WRITE_INT_CLEAR_OFF,DMA Write Interrupt Clear Register." hexmask.long.byte 0x4 24.--31. 1. "RSVDP_24,Reserved for future use." hexmask.long.byte 0x4 16.--23. 1. "WR_ABORT_INT_CLEAR,Abort Interrupt Clear. You must write a 1'b1 to clear the corresponding bit in the Abort interrupt status field of the DMA write interrupt status register. Each bit corresponds to a DMA channel. Bit [0] corresponds to channel 0. Note:.." newline hexmask.long.byte 0x4 8.--15. 1. "RSVDP_8,Reserved for future use." hexmask.long.byte 0x4 0.--7. 1. "WR_DONE_INT_CLEAR,Done Interrupt Clear. You must write a 1'b1 to clear the corresponding bit in the Done interrupt status field of the DMA write interrupt status register. Each bit corresponds to a DMA channel. Bit [0] corresponds to channel 0. Note:.." rgroup.long (0x5C+0xC8000)++0x3 line.long 0x0 "DMA_WRITE_ERR_STATUS_OFF,DMA Write Error Status Register" hexmask.long.byte 0x0 24.--31. 1. "RSVDP_24,Reserved for future use." hexmask.long.byte 0x0 16.--23. 1. "LINKLIST_ELEMENT_FETCH_ERR_DETECT,Linked List Element Fetch Error Detected. The DMA write channel has received an error response from the AXI bus (or TRGT1 interface when the AXI Bridge is not used) while reading a linked list element from local memory." newline hexmask.long.byte 0x0 8.--15. 1. "RSVDP_8,Reserved for future use." hexmask.long.byte 0x0 0.--7. 1. "APP_READ_ERR_DETECT,Application Read Error Detected. The DMA write channel has received an error response from the AXI bus (or TRGT1 interface when the AXI Bridge is not used) while reading data from it. Each bit corresponds to a DMA channel. Bit [0].." group.long (0x60+0xC8000)++0x1F line.long 0x0 "DMA_WRITE_DONE_IMWR_LOW_OFF,DMA Write Done IMWr Address Low Register." hexmask.long 0x0 0.--31. 1. "DMA_WRITE_DONE_LOW_REG,The DMA uses this field to generate bits [31:0] of the address field for the Done IMWr TLP. Bits [1:0] must be '00' as this address must be dword aligned. Note: The access attributes of this field are as follows: - Wire: No access." line.long 0x4 "DMA_WRITE_DONE_IMWR_HIGH_OFF,DMA Write Done IMWr Interrupt Address High Register." hexmask.long 0x4 0.--31. 1. "DMA_WRITE_DONE_HIGH_REG,The DMA uses this field to generate bits [63:32] of the address field for the Done IMWr TLP. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" line.long 0x8 "DMA_WRITE_ABORT_IMWR_LOW_OFF,DMA Write Abort IMWr Address Low Register." hexmask.long 0x8 0.--31. 1. "DMA_WRITE_ABORT_LOW_REG,The DMA uses this field to generate bits [31:0] of the address field for the Abort IMWr TLP it generates. Bits [1:0] must be '00' as this address must be dword aligned. Note: The access attributes of this field are as follows: -.." line.long 0xC "DMA_WRITE_ABORT_IMWR_HIGH_OFF,DMA Write Abort IMWr Address High Register." hexmask.long 0xC 0.--31. 1. "DMA_WRITE_ABORT_HIGH_REG,The DMA uses this field to generate bits [63:32] of the address field for the Abort IMWr TLP. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" line.long 0x10 "DMA_WRITE_CH01_IMWR_DATA_OFF,DMA Write Channel 1 and 0 IMWr Data Register." hexmask.long.word 0x10 16.--31. 1. "WR_CHANNEL_1_DATA,The DMA uses this field to generate the data field for the Done or Abort IMWr TLPs it generates for write channel 1. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" hexmask.long.word 0x10 0.--15. 1. "WR_CHANNEL_0_DATA,The DMA uses this field to generate the data field for the Done or Abort IMWr TLPs it generates for write channel 0. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" line.long 0x14 "DMA_WRITE_CH23_IMWR_DATA_OFF,DMA Write Channel 3 and 2 IMWr Data Register." hexmask.long.word 0x14 16.--31. 1. "WR_CHANNEL_3_DATA,The DMA uses this field to generate the data field for the Done or Abort IMWr TLPs it generates for write channel 3. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" hexmask.long.word 0x14 0.--15. 1. "WR_CHANNEL_2_DATA,The DMA uses this field to generate the data field for the Done or Abort IMWr TLPs it generates for write channel 2. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" line.long 0x18 "DMA_WRITE_CH45_IMWR_DATA_OFF,DMA Write Channel 5 and 4 IMWr Data Register." hexmask.long.word 0x18 16.--31. 1. "WR_CHANNEL_5_DATA,The DMA uses this field to generate the data field for the Done or Abort IMWr TLPs it generates for write channel 5. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" hexmask.long.word 0x18 0.--15. 1. "WR_CHANNEL_4_DATA,The DMA uses this field to generate the data field for the Done or Abort IMWr TLPs it generates for write channel 4. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" line.long 0x1C "DMA_WRITE_CH67_IMWR_DATA_OFF,DMA Write Channel 7 and 6 IMWr Data Register." hexmask.long.word 0x1C 16.--31. 1. "WR_CHANNEL_7_DATA,The DMA uses this field to generate the data field for the Done or Abort IMWr TLPs it generates for write channel 7. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" hexmask.long.word 0x1C 0.--15. 1. "WR_CHANNEL_6_DATA,The DMA uses this field to generate the data field for the Done or Abort IMWr TLPs it generates for write channel 6. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" group.long (0x90+0xC8000)++0x3 line.long 0x0 "DMA_WRITE_LINKED_LIST_ERR_EN_OFF,DMA Write Linked List Error Enable Register. The LIE and RIE bits in the LL element enable the channel 'done' interrupts (local and remote). The LLLAIE and LLRAIE bits enable the channel 'abort' interrupts (local and.." hexmask.long.byte 0x0 24.--31. 1. "RSVDP_24,Reserved for future use." hexmask.long.byte 0x0 16.--23. 1. "WR_CHANNEL_LLLAIE,Write Channel LL Local Abort Interrupt Enable (LLLAIE). You enable the write channel local abort interrupt through this bit. The LIE and RIE bits in the LL element enable the write channel done interrupts. Each bit corresponds to a DMA.." newline hexmask.long.byte 0x0 8.--15. 1. "RSVDP_8,Reserved for future use." hexmask.long.byte 0x0 0.--7. 1. "WR_CHANNEL_LLRAIE,Write Channel LL Remote Abort Interrupt Enable (LLRAIE). You enable the write channel remote abort interrupt through this bit. The LIE and RIE bits in the LL element enable the write channel done interrupts. Each bit corresponds to a.." group.long (0xA0+0xC8000)++0x3 line.long 0x0 "DMA_READ_INT_STATUS_OFF,DMA Read Interrupt Status Register." hexmask.long.byte 0x0 24.--31. 1. "RSVDP_24,Reserved for future use." hexmask.long.byte 0x0 16.--23. 1. "RD_ABORT_INT_STATUS,Abort Interrupt Status. The DMA read channel has detected an error or you manually stopped the transfer as described in 'Stopping the DMA Transfer (Software Stop)'. Each bit corresponds to a DMA channel. Bit [0] corresponds to.." newline hexmask.long.byte 0x0 8.--15. 1. "RSVDP_8,Reserved for future use." hexmask.long.byte 0x0 0.--7. 1. "RD_DONE_INT_STATUS,Done Interrupt Status. The DMA read channel has successfully completed the DMA read transfer. Each bit corresponds to a DMA channel. Bit [0] corresponds to channel 0. - Enabling: For details see 'Interrupts and Error Handling'. -.." group.long (0xA8+0xC8000)++0x7 line.long 0x0 "DMA_READ_INT_MASK_OFF,DMA Read Interrupt Mask Register." hexmask.long.byte 0x0 24.--31. 1. "RSVDP_24,Reserved for future use." hexmask.long.byte 0x0 16.--23. 1. "RD_ABORT_INT_MASK,Abort Interrupt Mask. Prevents the Abort interrupt status field in the DMA read interrupt status register from asserting the edma_int output. Each bit corresponds to a DMA channel. Bit [0] corresponds to channel 0. Note: The access.." newline hexmask.long.byte 0x0 8.--15. 1. "RSVDP_8,Reserved for future use." hexmask.long.byte 0x0 0.--7. 1. "RD_DONE_INT_MASK,Done Interrupt Mask. Prevents the Done interrupt status field in the DMA read interrupt status register from asserting the edma_int output. Each bit corresponds to a DMA channel. Bit [0] corresponds to channel 0. Note: The access.." line.long 0x4 "DMA_READ_INT_CLEAR_OFF,DMA Read Interrupt Clear Register." hexmask.long.byte 0x4 24.--31. 1. "RSVDP_24,Reserved for future use." hexmask.long.byte 0x4 16.--23. 1. "RD_ABORT_INT_CLEAR,Abort Interrupt Clear. You must write a 1'b1 to clear the corresponding bit in the Abort interrupt status field of the DMA read interrupt status register. Each bit corresponds to a DMA channel. Bit [0] corresponds to channel 0. Note:.." newline hexmask.long.byte 0x4 8.--15. 1. "RSVDP_8,Reserved for future use." hexmask.long.byte 0x4 0.--7. 1. "RD_DONE_INT_CLEAR,Done Interrupt Clear. You must write a 1'b1 to clear the corresponding bit in the Done interrupt status field of the DMA read interrupt status register. Each bit corresponds to a DMA channel. Bit [0] corresponds to channel 0. Note:.." rgroup.long (0xB4+0xC8000)++0x7 line.long 0x0 "DMA_READ_ERR_STATUS_LOW_OFF,DMA Read Error Status Low Register." hexmask.long.byte 0x0 24.--31. 1. "RSVDP_24,Reserved for future use." hexmask.long.byte 0x0 16.--23. 1. "LINK_LIST_ELEMENT_FETCH_ERR_DETECT,Linked List Element Fetch Error Detected. - The DMA read channel has received an error response from the AXI bus while reading a linked list element from local memory. Each bit corresponds to a DMA channel. Bit [0].." newline hexmask.long.byte 0x0 8.--15. 1. "RSVDP_8,Reserved for future use." hexmask.long.byte 0x0 0.--7. 1. "APP_WR_ERR_DETECT,Application Write Error Detected. The DMA read channel has received an error response from the AXI bus (or TRGT1 interface when the AXI Bridge is not used) while writing data to it. This error is fatal. You must restart the transfer.." line.long 0x4 "DMA_READ_ERR_STATUS_HIGH_OFF,DMA Read Error Status High Register." hexmask.long.byte 0x4 24.--31. 1. "DATA_POISIONING,Data Poisoning. The DMA read channel has detected data poisoning in the completion from the remote device (in response to the MRd request). The DMA read channel will drop the completion and then be halted. The CX_FLT_MASK_UR_POIS filter.." hexmask.long.byte 0x4 16.--23. 1. "CPL_TIMEOUT,Completion Time Out. The DMA read channel has timed-out while waiting for the remote device to respond to the MRd request or a malformed CplD has been received. For more details see 'Linked List Mode'. Each bit corresponds to a DMA channel." newline hexmask.long.byte 0x4 8.--15. 1. "CPL_ABORT,Completer Abort. The DMA read channel has received a PCIe completer abort completion status from the remote device in response to the MRd request. For more details see 'Linked List Mode'. Each bit corresponds to a DMA channel. Bit [0].." hexmask.long.byte 0x4 0.--7. 1. "UNSUPPORTED_REQ,Unsupported Request. The DMA read channel has received a PCIe unsupported request completion status from the remote device in response to the MRd request. For more details see 'Linked List Mode'. Each bit corresponds to a DMA channel." group.long (0xC4+0xC8000)++0x3 line.long 0x0 "DMA_READ_LINKED_LIST_ERR_EN_OFF,DMA Read Linked List Error Enable Register. The LIE and RIE bits in the LL element enable the channel 'done' interrupts (local and remote). The LLLAIE and LLRAIE bits enable the channel 'abort' interrupts (local and remote)." hexmask.long.byte 0x0 24.--31. 1. "RSVDP_24,Reserved for future use." hexmask.long.byte 0x0 16.--23. 1. "RD_CHANNEL_LLLAIE,Read Channel LL Local Abort Interrupt Enable (LLLAIE). You enable the read channel Local Abort interrupt through this bit. The LIE and RIE bits in the LL element enable the read channel done interrupts. Each bit corresponds to a DMA.." newline hexmask.long.byte 0x0 8.--15. 1. "RSVDP_8,Reserved for future use." hexmask.long.byte 0x0 0.--7. 1. "RD_CHANNEL_LLRAIE,Read Channel LL Remote Abort Interrupt Enable (LLRAIE). You enable the read channel Remote Abort interrupt through this bit. The LIE and RIE bits in the LL element enable the read channel done interrupts. Each bit corresponds to a DMA.." group.long (0xCC+0xC8000)++0x1F line.long 0x0 "DMA_READ_DONE_IMWR_LOW_OFF,DMA Read Done IMWr Address Low Register." hexmask.long 0x0 0.--31. 1. "DMA_READ_DONE_LOW_REG,The DMA uses this field to generate bits [31:0] of the address field for the Done IMWr TLP. Bits [1:0] must be '00' as this address must be dword aligned. Note: The access attributes of this field are as follows: - Wire: No access." line.long 0x4 "DMA_READ_DONE_IMWR_HIGH_OFF,DMA Read Done IMWr Address High Register." hexmask.long 0x4 0.--31. 1. "DMA_READ_DONE_HIGH_REG,The DMA uses this field to generate bits [63:32] of the address field for the Done IMWr TLP. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" line.long 0x8 "DMA_READ_ABORT_IMWR_LOW_OFF,DMA Read Abort IMWr Address Low Register." hexmask.long 0x8 0.--31. 1. "DMA_READ_ABORT_LOW_REG,The DMA uses this field to generate bits [31:0] of the address field for the Abort IMWr TLP. Bits [1:0] must be '00' as this address must be dword aligned. Note: The access attributes of this field are as follows: - Wire: No.." line.long 0xC "DMA_READ_ABORT_IMWR_HIGH_OFF,DMA Read Abort IMWr Address High Register." hexmask.long 0xC 0.--31. 1. "DMA_READ_ABORT_HIGH_REG,The DMA uses this field to generate bits [63:32] of the address field for the Abort IMWr TLP. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" line.long 0x10 "DMA_READ_CH01_IMWR_DATA_OFF,DMA Read Channel 1 and 0 IMWr Data Register." hexmask.long.word 0x10 16.--31. 1. "RD_CHANNEL_1_DATA,The DMA uses this field to generate the data field for the Done or Abort IMWr TLPs it generates for read channel 1. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" hexmask.long.word 0x10 0.--15. 1. "RD_CHANNEL_0_DATA,The DMA uses this field to generate the data field for the Done or Abort IMWr TLPs it generates for read channel 0. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" line.long 0x14 "DMA_READ_CH23_IMWR_DATA_OFF,DMA Read Channel 3 and 2 IMWr Data Register." hexmask.long.word 0x14 16.--31. 1. "RD_CHANNEL_3_DATA,The DMA uses this field to generate the data field for the Done or Abort IMWr TLPs it generates for read channel 3. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" hexmask.long.word 0x14 0.--15. 1. "RD_CHANNEL_2_DATA,The DMA uses this field to generate the data field for the Done or Abort IMWr TLPs it generates for read channel 2. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" line.long 0x18 "DMA_READ_CH45_IMWR_DATA_OFF,DMA Read Channel 5 and 4 IMWr Data Register." hexmask.long.word 0x18 16.--31. 1. "RD_CHANNEL_5_DATA,The DMA uses this field to generate the data field for the Done or Abort IMWr TLPs it generates for read channel 5. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" hexmask.long.word 0x18 0.--15. 1. "RD_CHANNEL_4_DATA,The DMA uses this field to generate the data field for the Done or Abort IMWr TLPs it generates for read channel 4. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" line.long 0x1C "DMA_READ_CH67_IMWR_DATA_OFF,DMA Read Channel 7 and 6 IMWr Data Register." hexmask.long.word 0x1C 16.--31. 1. "RD_CHANNEL_7_DATA,The DMA uses this field to generate the data field for the Done or Abort IMWr TLPs it generates for read channel 7. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" hexmask.long.word 0x1C 0.--15. 1. "RD_CHANNEL_6_DATA,The DMA uses this field to generate the data field for the Done or Abort IMWr TLPs it generates for read channel 6. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" rgroup.long (0x108+0xC8000)++0x7 line.long 0x0 "DMA_WRITE_ENGINE_HSHAKE_CNT_LOW_OFF,DMA Write Engine Handshake Counter Channel 0/1/2/3 Register." bitfld.long 0x0 29.--31. "RSVDP_29,Reserved for future use." "0,1,2,3,4,5,6,7" hexmask.long.byte 0x0 24.--28. 1. "DMA_WRITE_ENGINE_HSHAKE_CNT_CH3,DMA handshake counter for DMA Write Engine Channel 3. If CC_DMA_HSHAKE =1 the data transfer in Linked List mode starts only when the counter is non-zero." newline bitfld.long 0x0 21.--23. "RSVDP_21,Reserved for future use." "0,1,2,3,4,5,6,7" hexmask.long.byte 0x0 16.--20. 1. "DMA_WRITE_ENGINE_HSHAKE_CNT_CH2,DMA handshake counter for DMA Write Engine Channel 2. If CC_DMA_HSHAKE =1 the data transfer in Linked List mode starts only when the counter is non-zero." newline bitfld.long 0x0 13.--15. "RSVDP_13,Reserved for future use." "0,1,2,3,4,5,6,7" hexmask.long.byte 0x0 8.--12. 1. "DMA_WRITE_ENGINE_HSHAKE_CNT_CH1,DMA handshake counter for DMA Write Engine Channel 1. If CC_DMA_HSHAKE =1 the data transfer in Linked List mode starts only when the counter is non-zero." newline bitfld.long 0x0 5.--7. "RSVDP_5,Reserved for future use." "0,1,2,3,4,5,6,7" hexmask.long.byte 0x0 0.--4. 1. "DMA_WRITE_ENGINE_HSHAKE_CNT_CH0,DMA handshake counter for DMA Write Engine Channel 0. If CC_DMA_HSHAKE =1 the data transfer in Linked List mode starts only when the counter is non-zero." line.long 0x4 "DMA_WRITE_ENGINE_HSHAKE_CNT_HIGH_OFF,DMA Write Engine Handshake Counter Channel 4/5/6/7 Register." bitfld.long 0x4 29.--31. "RSVDP_29,Reserved for future use." "0,1,2,3,4,5,6,7" hexmask.long.byte 0x4 24.--28. 1. "DMA_WRITE_ENGINE_HSHAKE_CNT_CH7,DMA handshake counter for DMA Write Engine Channel 7. If CC_DMA_HSHAKE =1 the data transfer in Linked List mode starts only when the counter is non-zero." newline bitfld.long 0x4 21.--23. "RSVDP_21,Reserved for future use." "0,1,2,3,4,5,6,7" hexmask.long.byte 0x4 16.--20. 1. "DMA_WRITE_ENGINE_HSHAKE_CNT_CH6,DMA handshake counter for DMA Write Engine Channel 6. If CC_DMA_HSHAKE =1 the data transfer in Linked List mode starts only when the counter is non-zero." newline bitfld.long 0x4 13.--15. "RSVDP_13,Reserved for future use." "0,1,2,3,4,5,6,7" hexmask.long.byte 0x4 8.--12. 1. "DMA_WRITE_ENGINE_HSHAKE_CNT_CH5,DMA handshake counter for DMA Write Engine Channel 5. If CC_DMA_HSHAKE =1 the data transfer in Linked List mode starts only when the counter is non-zero." newline bitfld.long 0x4 5.--7. "RSVDP_5,Reserved for future use." "0,1,2,3,4,5,6,7" hexmask.long.byte 0x4 0.--4. 1. "DMA_WRITE_ENGINE_HSHAKE_CNT_CH4,DMA handshake counter for DMA Write Engine Channel 4. If CC_DMA_HSHAKE =1 the data transfer in Linked List mode starts only when the counter is non-zero." rgroup.long (0x118+0xC8000)++0x7 line.long 0x0 "DMA_READ_ENGINE_HSHAKE_CNT_LOW_OFF,DMA Read Engine Handshake Counter Channel 0/1/2/3 Register." bitfld.long 0x0 29.--31. "RSVDP_29,Reserved for future use." "0,1,2,3,4,5,6,7" hexmask.long.byte 0x0 24.--28. 1. "DMA_READ_ENGINE_HSHAKE_CNT_CH3,DMA handshake counter for DMA Read Engine Channel 3. If CC_DMA_HSHAKE =1 the data transfer in Linked List mode starts only when the counter is non-zero." newline bitfld.long 0x0 21.--23. "RSVDP_21,Reserved for future use." "0,1,2,3,4,5,6,7" hexmask.long.byte 0x0 16.--20. 1. "DMA_READ_ENGINE_HSHAKE_CNT_CH2,DMA handshake counter for DMA Read Engine Channel 2. If CC_DMA_HSHAKE =1 the data transfer in Linked List mode starts only when the counter is non-zero." newline bitfld.long 0x0 13.--15. "RSVDP_13,Reserved for future use." "0,1,2,3,4,5,6,7" hexmask.long.byte 0x0 8.--12. 1. "DMA_READ_ENGINE_HSHAKE_CNT_CH1,DMA handshake counter for DMA Read Engine Channel 1. If CC_DMA_HSHAKE =1 the data transfer in Linked List mode starts only when the counter is non-zero." newline bitfld.long 0x0 5.--7. "RSVDP_5,Reserved for future use." "0,1,2,3,4,5,6,7" hexmask.long.byte 0x0 0.--4. 1. "DMA_READ_ENGINE_HSHAKE_CNT_CH0,DMA handshake counter for DMA Read Engine Channel 0. If CC_DMA_HSHAKE =1 the data transfer in Linked List mode starts only when the counter is non-zero." line.long 0x4 "DMA_READ_ENGINE_HSHAKE_CNT_HIGH_OFF,DMA Read Engine Handshake Counter Channel 4/5/6/7 Register." bitfld.long 0x4 29.--31. "RSVDP_29,Reserved for future use." "0,1,2,3,4,5,6,7" hexmask.long.byte 0x4 24.--28. 1. "DMA_READ_ENGINE_HSHAKE_CNT_CH7,DMA handshake counter for DMA Read Engine Channel 7. If CC_DMA_HSHAKE =1 the data transfer in Linked List mode starts only when the counter is non-zero." newline bitfld.long 0x4 21.--23. "RSVDP_21,Reserved for future use." "0,1,2,3,4,5,6,7" hexmask.long.byte 0x4 16.--20. 1. "DMA_READ_ENGINE_HSHAKE_CNT_CH6,DMA handshake counter for DMA Read Engine Channel 6. If CC_DMA_HSHAKE =1 the data transfer in Linked List mode starts only when the counter is non-zero." newline bitfld.long 0x4 13.--15. "RSVDP_13,Reserved for future use." "0,1,2,3,4,5,6,7" hexmask.long.byte 0x4 8.--12. 1. "DMA_READ_ENGINE_HSHAKE_CNT_CH5,DMA handshake counter for DMA Read Engine Channel 5. If CC_DMA_HSHAKE =1 the data transfer in Linked List mode starts only when the counter is non-zero." newline bitfld.long 0x4 5.--7. "RSVDP_5,Reserved for future use." "0,1,2,3,4,5,6,7" hexmask.long.byte 0x4 0.--4. 1. "DMA_READ_ENGINE_HSHAKE_CNT_CH4,DMA handshake counter for DMA Read Engine Channel 4. If CC_DMA_HSHAKE =1 the data transfer in Linked List mode starts only when the counter is non-zero." repeat 8. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 )(list 0x0 0x200 0x400 0x600 0x800 0xA00 0xC00 0xE00 ) group.long ($2+0x200+0xC8000)++0x3 line.long 0x0 "DMA_CH_CONTROL1_OFF_WRCH_$1,DMA Write Channel Control 1 Register." bitfld.long 0x0 30.--31. "DMA_AT,Address Translation TLP Header Bit (AT) The DMA uses this TLP header field when generating MRd/MWr (not IMWr) TLPs. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" "0,1,2,3" bitfld.long 0x0 27.--29. "DMA_TC,Traffic Class TLP Header Bit (TC) The DMA uses this TLP header field when generating MRd/MWr (not IMWr) TLPs. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 26. "DMA_RESERVED5,Reserved. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" "0,1" bitfld.long 0x0 25. "DMA_RO,Relaxed Ordering TLP Header Bit (RO) The DMA uses this TLP header field when generating MRd/MWr (not IMWr) TLPs. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" "0,1" newline bitfld.long 0x0 24. "DMA_NS_SRC,Source No Snoop TLP Header Bit (DMA_NS_SRC). The DMA uses this TLP header field when generating MRd (SAR addressing space) (not IMWr) TLPs. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" "0,1" bitfld.long 0x0 23. "DMA_NS_DST,Destination No Snoop TLP Header Bit (DMA_NS_DST). The DMA uses this TLP header field when generating MWr (DAR addressing space) (not IMWr) TLPs. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" "0,1" newline bitfld.long 0x0 22. "DMA_MEM_TYPE,Master AXI ACE-Lite Cache Coherency Control. This field sets the DMA channel memory type of the address space of the data transfer as follows: - 0x0:peripheral type - 0x1:memory type For more details see 'ACE-Lite Features and Limitations'.." "peripheral type,memory type" hexmask.long.byte 0x0 17.--21. 1. "DMA_RESERVED2,Reserved. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" newline hexmask.long.byte 0x0 12.--16. 1. "DMA_FUNC_NUM,Function Number (FN). The controller uses this field when generating the requester ID for the MRd/MWr DMA TLP. When you have enabled SR-IOV then this field is ignored if you have set the VFE field in the 'DMA Write Channel Control 2.." bitfld.long 0x0 10.--11. "DMA_RESERVED1,Reserved. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" "0,1,2,3" newline bitfld.long 0x0 9. "LLE,Linked List Enable (LLE). - 0: Disable linked list operation - 1: Enable linked list operation Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" "Disable linked list operation,Enable linked list operation" bitfld.long 0x0 8. "CCS,Consumer Cycle State (CCS). Used in linked list mode only. It is used to synchronize the producer (software) and the consumer (DMA). For more details see 'PCS-CCS-CB-TCB Producer-Consumer Synchronization'. You must initialize this bit. The DMA.." "0,1" newline bitfld.long 0x0 7. "DMA_RESERVED0,Reserved. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" "0,1" bitfld.long 0x0 5.--6. "CS,Channel Status (CS). The channel status bits identify the current operational state of the DMA channel. The operation state encoding for each DMA channel is a s follows: - 00: Reserved - 01: Running. This channel is active and transferring data. - 10:.." "Reserved,Running,?,?" newline bitfld.long 0x0 4. "RIE,Remote Interrupt Enable (RIE). You must set this bit to enable the generation of the Done or Abort Remote interrupts. For more details see 'Interrupts and Error Handling'. In LL mode the DMA overwrites this with the RIE of the LL element. The RIE.." "0,1" bitfld.long 0x0 3. "LIE,Local Interrupt Enable (LIE). You must set this bit to enable the generation of the Done or Abort Local interrupts. For more details see 'Interrupts and Error Handling'. In LL mode the DMA overwrites this with the LIE of the LL element. The LIE bit.." "0,1" newline bitfld.long 0x0 2. "LLP,Load Link Pointer (LLP). Used in linked list mode only. Indicates that this linked list element is a link element and its LL element pointer dwords are pointing to the next (non-contiguous) element. The DMA loads this field with the LLP of the.." "0,1" bitfld.long 0x0 1. "TCB,Toggle Cycle Bit (TCB). Indicates to the DMA to toggle its interpretation of the CB. Used in linked list mode only. It is used to synchronize the producer (software) and the consumer (DMA). For more details see 'PCS-CCS-CB-TCB Producer-Consumer.." "0,1" newline bitfld.long 0x0 0. "CB,Cycle Bit (CB). Used in linked list mode only. It is used to synchronize the producer (software) and the consumer (DMA). For more details see 'PCS-CCS-CB-TCB Producer-Consumer Synchronization'. The DMA loads this field with the CB of the linked list.." "0,1" repeat.end repeat 8. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 )(list 0x0 0x200 0x400 0x600 0x800 0xA00 0xC00 0xE00 ) group.long ($2+0x208+0xC8000)++0x3 line.long 0x0 "DMA_TRANSFER_SIZE_OFF_WRCH_$1,DMA Write Transfer Size Register." hexmask.long 0x0 0.--31. 1. "DMA_TRANSFER_SIZE,DMA Transfer Size. You program this register with the size of the DMA transfer. The maximum DMA transfer size is 4Gbytes. The minimum transfer size is one byte (0x1). This field is automatically decremented by the DMA as the DMA write.." repeat.end repeat 8. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 )(list 0x0 0x200 0x400 0x600 0x800 0xA00 0xC00 0xE00 ) group.long ($2+0x20C+0xC8000)++0x3 line.long 0x0 "DMA_SAR_LOW_OFF_WRCH_$1,DMA Write SAR Low Register." hexmask.long 0x0 0.--31. 1. "SRC_ADDR_REG_LOW,Source Address Register (Lower 32 bits). Indicates the next address to be read from. The DMA increments the SAR as the DMA transfer progresses. In LL mode the DMA overwrites this with the corresponding dword of the LL element. - DMA.." repeat.end repeat 8. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 )(list 0x0 0x200 0x400 0x600 0x800 0xA00 0xC00 0xE00 ) group.long ($2+0x210+0xC8000)++0x3 line.long 0x0 "DMA_SAR_HIGH_OFF_WRCH_$1,DMA Write SAR High Register." hexmask.long 0x0 0.--31. 1. "SRC_ADDR_REG_HIGH,Source Address Register (Higher 32 bits). In LL mode the DMA overwrites this with the corresponding dword of the LL element. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" repeat.end repeat 8. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 )(list 0x0 0x200 0x400 0x600 0x800 0xA00 0xC00 0xE00 ) group.long ($2+0x214+0xC8000)++0x3 line.long 0x0 "DMA_DAR_LOW_OFF_WRCH_$1,DMA Write DAR Low Register." hexmask.long 0x0 0.--31. 1. "DST_ADDR_REG_LOW,Destination Address Register (Lower 32 bits). Indicates the next address to be written to. The DMA increments the DAR as the DMA transfer progresses. In LL mode the DMA overwrites this with the corresponding dword of the LL element. -.." repeat.end repeat 8. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 )(list 0x0 0x200 0x400 0x600 0x800 0xA00 0xC00 0xE00 ) group.long ($2+0x218+0xC8000)++0x3 line.long 0x0 "DMA_DAR_HIGH_OFF_WRCH_$1,DMA Write DAR High Register." hexmask.long 0x0 0.--31. 1. "DST_ADDR_REG_HIGH,Destination Address Register (Higher 32 bits). In LL mode the DMA overwrites this with the corresponding dword of the LL element. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" repeat.end repeat 8. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 )(list 0x0 0x200 0x400 0x600 0x800 0xA00 0xC00 0xE00 ) group.long ($2+0x21C+0xC8000)++0x3 line.long 0x0 "DMA_LLP_LOW_OFF_WRCH_$1,DMA Write Linked List Pointer Low Register." hexmask.long 0x0 0.--31. 1. "LLP_LOW,Lower bits of the address of the linked list transfer list in local memory. Used in linked list mode only. Updated by the DMA to point to the next element in the transfer list after the previous element is consumed. - When the current element is.." repeat.end repeat 8. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 )(list 0x0 0x200 0x400 0x600 0x800 0xA00 0xC00 0xE00 ) group.long ($2+0x220+0xC8000)++0x3 line.long 0x0 "DMA_LLP_HIGH_OFF_WRCH_$1,DMA Write Linked List Pointer High Register." hexmask.long 0x0 0.--31. 1. "LLP_HIGH,Upper 32 bits of the address of the linked list transfer list in local memory. Used in linked list mode only. Updated by the DMA to point to the next element in the transfer list as elements are consumed. Note: The access attributes of this.." repeat.end repeat 8. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 )(list 0x0 0x200 0x400 0x600 0x800 0xA00 0xC00 0xE00 ) group.long ($2+0x300+0xC8000)++0x3 line.long 0x0 "DMA_CH_CONTROL1_OFF_RDCH_$1,DMA Read Channel Control 1 Register." bitfld.long 0x0 30.--31. "DMA_AT,Address Translation TLP Header Bit (AT) The DMA uses this TLP header field when generating MRd/MWr (not IMWr) TLPs. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" "0,1,2,3" bitfld.long 0x0 27.--29. "DMA_TC,Traffic Class TLP Header Bit (TC) The DMA uses this TLP header field when generating MRd/MWr (not IMWr) TLPs. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 26. "DMA_RESERVED5,Reserved. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" "0,1" bitfld.long 0x0 25. "DMA_RO,Relaxed Ordering TLP Header Bit (RO) The DMA uses this TLP header field when generating MRd/MWr (not IMWr) TLPs. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" "0,1" newline bitfld.long 0x0 24. "DMA_NS_SRC,Source No Snoop TLP Header Bit (DMA_NS_SRC). The DMA uses this TLP header field when generating MRd (SAR addressing space) (not IMWr) TLPs. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" "0,1" bitfld.long 0x0 23. "DMA_NS_DST,Destination No Snoop TLP Header Bit (DMA_NS_DST). The DMA uses this TLP header field when generating MWr (DAR addressing space) (not IMWr) TLPs. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" "0,1" newline bitfld.long 0x0 22. "DMA_MEM_TYPE,Master AXI ACE-Lite Cache Coherency Control. This field sets the DMA channel memory type of the address space of the data transfer as follows: - 0x0:peripheral type - 0x1:memory type For more details see 'ACE-Lite Features and Limitations'.." "peripheral type,memory type" hexmask.long.byte 0x0 17.--21. 1. "DMA_RESERVED2,Reserved. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" newline hexmask.long.byte 0x0 12.--16. 1. "DMA_FUNC_NUM,Function Number (FN). The controller uses this field when generating the requester ID for the MRd/MWr DMA TLP. When you have enabled SR-IOV then this field is ignored if you have set the VFE field in the 'DMA Read Channel Control 2.." bitfld.long 0x0 10.--11. "DMA_RESERVED1,Reserved. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" "0,1,2,3" newline bitfld.long 0x0 9. "LLE,Linked List Enable (LLE). - 0: Disable linked list operation - 1: Enable linked list operation Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" "Disable linked list operation,Enable linked list operation" bitfld.long 0x0 8. "CCS,Consumer Cycle State (CCS). Used in linked list mode only. It is used to synchronize the producer (software) and the consumer (DMA). For more details see 'PCS-CCS-CB-TCB Producer-Consumer Synchronization'. You must initialize this bit. The DMA.." "0,1" newline bitfld.long 0x0 7. "DMA_RESERVED0,Reserved. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" "0,1" bitfld.long 0x0 5.--6. "CS,Channel Status (CS). The channel status bits identify the current operational state of the DMA channel. The operation state encoding for each DMA channel is a s follows: - 00: Reserved - 01: Running. This channel is active and transferring data. - 10:.." "Reserved,Running,?,?" newline bitfld.long 0x0 4. "RIE,Remote Interrupt Enable (RIE). You must set this bit to enable the generation of the Done or Abort Remote interrupts. For more details see 'Interrupts and Error Handling'. In LL mode the DMA overwrites this with the RIE of the LL element. The RIE.." "0,1" bitfld.long 0x0 3. "LIE,Local Interrupt Enable (LIE). You must set this bit to enable the generation of the Done or Abort Local interrupts. For more details see 'Interrupts and Error Handling'. In LL mode the DMA overwrites this with the LIE of the LL element. The LIE bit.." "0,1" newline bitfld.long 0x0 2. "LLP,Load Link Pointer (LLP). Used in linked list mode only. Indicates that this linked list element is a link element and its LL element pointer dwords are pointing to the next (non-contiguous) element. The DMA loads this field with the LLP of the.." "0,1" bitfld.long 0x0 1. "TCB,Toggle Cycle Bit (TCB). Indicates to the DMA to toggle its interpretation of the CB. Used in linked list mode only. It is used to synchronize the producer (software) and the consumer (DMA). For more details see 'PCS-CCS-CB-TCB Producer-Consumer.." "0,1" newline bitfld.long 0x0 0. "CB,Cycle Bit (CB). Used in linked list mode only. It is used to synchronize the producer (software) and the consumer (DMA). For more details see 'PCS-CCS-CB-TCB Producer-Consumer Synchronization'. The DMA loads this field with the CB of the linked list.." "0,1" repeat.end repeat 8. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 )(list 0x0 0x200 0x400 0x600 0x800 0xA00 0xC00 0xE00 ) group.long ($2+0x308+0xC8000)++0x3 line.long 0x0 "DMA_TRANSFER_SIZE_OFF_RDCH_$1,DMA Read Transfer Size Register." hexmask.long 0x0 0.--31. 1. "DMA_TRANSFER_SIZE,DMA Transfer Size. You program this register with the size of the DMA transfer. The maximum DMA transfer size is 4Gbytes. The minimum transfer size is one byte (0x1). This field is automatically decremented by the DMA as the DMA read.." repeat.end repeat 8. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 )(list 0x0 0x200 0x400 0x600 0x800 0xA00 0xC00 0xE00 ) group.long ($2+0x30C+0xC8000)++0x3 line.long 0x0 "DMA_SAR_LOW_OFF_RDCH_$1,DMA Read SAR Low Register." hexmask.long 0x0 0.--31. 1. "SRC_ADDR_REG_LOW,Source Address Register (Lower 32 bits). Indicates the next address to be read from. The DMA increments the SAR as the DMA transfer progresses. In LL mode the DMA overwrites this with the corresponding dword of the LL element. - DMA.." repeat.end repeat 8. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 )(list 0x0 0x200 0x400 0x600 0x800 0xA00 0xC00 0xE00 ) group.long ($2+0x310+0xC8000)++0x3 line.long 0x0 "DMA_SAR_HIGH_OFF_RDCH_$1,DMA Read SAR High Register." hexmask.long 0x0 0.--31. 1. "SRC_ADDR_REG_HIGH,Source Address Register (Higher 32 bits). In LL mode the DMA overwrites this with the corresponding dword of the LL element. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" repeat.end repeat 8. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 )(list 0x0 0x200 0x400 0x600 0x800 0xA00 0xC00 0xE00 ) group.long ($2+0x314+0xC8000)++0x3 line.long 0x0 "DMA_DAR_LOW_OFF_RDCH_$1,DMA Read DAR Low Register." hexmask.long 0x0 0.--31. 1. "DST_ADDR_REG_LOW,Destination Address Register (Lower 32 bits). Indicates the next address to be written to. The DMA increments the DAR as the DMA transfer progresses. In LL mode the DMA overwrites this with the corresponding dword of the LL element. -.." repeat.end repeat 8. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 )(list 0x0 0x200 0x400 0x600 0x800 0xA00 0xC00 0xE00 ) group.long ($2+0x318+0xC8000)++0x3 line.long 0x0 "DMA_DAR_HIGH_OFF_RDCH_$1,DMA Read DAR High Register." hexmask.long 0x0 0.--31. 1. "DST_ADDR_REG_HIGH,Destination Address Register (Higher 32 bits). In LL mode the DMA overwrites this with the corresponding dword of the LL element. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" repeat.end repeat 8. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 )(list 0x0 0x200 0x400 0x600 0x800 0xA00 0xC00 0xE00 ) group.long ($2+0x31C+0xC8000)++0x3 line.long 0x0 "DMA_LLP_LOW_OFF_RDCH_$1,DMA Read Linked List Pointer Low Register." hexmask.long 0x0 0.--31. 1. "LLP_LOW,Lower bits of the address of the linked list transfer list in local memory. Used in linked list mode only. Updated by the DMA to point to the next element in the transfer list after the previous element is consumed. - When the current element is.." repeat.end repeat 8. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 )(list 0x0 0x200 0x400 0x600 0x800 0xA00 0xC00 0xE00 ) group.long ($2+0x320+0xC8000)++0x3 line.long 0x0 "DMA_LLP_HIGH_OFF_RDCH_$1,DMA Read Linked List Pointer High Register." hexmask.long 0x0 0.--31. 1. "LLP_HIGH,Upper 32 bits of the address of the linked list transfer list in local memory. Used in linked list mode only. Updated by the DMA to point to the next element in the transfer list as elements are consumed. Note: The access attributes of this.." repeat.end tree.end tree "PF0_ATU_CAP (ATU Por Logic Structure)" repeat 8. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 )(list 0x0 0x200 0x400 0x600 0x800 0xA00 0xC00 0xE00 ) group.long ($2+0xC0000)++0x3 line.long 0x0 "IATU_REGION_CTRL_1_OFF_OUTBOUND_$1,iATU Region Control 1 Register." bitfld.long 0x0 20. "CTRL_1_FUNC_NUM,Function Number. - When the address of an outbound TLP is matched to this region and the FUNC_BYPASS field in the 'iATU Control 2 Register' is '0' then the function number used in generating the function part of the requester ID (RID).." "0,1" newline bitfld.long 0x0 13. "INCREASE_REGION_SIZE,Increase the maximum ATU Region size. When set the maximum ATU Region size is determined by CX_ATU_MAX_REGION_SIZE. When clear the maximum ATU Region size is 4 GB (default). Note: This register field is sticky." "0,1" newline bitfld.long 0x0 9.--10. "ATTR,When the address of an outbound TLP is matched to this region then the ATTR field of the TLP is changed to the value in this register. Note: This register field is sticky." "0,1,2,3" newline bitfld.long 0x0 8. "TD,This is a reserved field. Do not use. Note: This register field is sticky." "0,1" newline bitfld.long 0x0 5.--7. "TC,When the address of an outbound TLP is matched to this region then the TC field of the TLP is changed to the value in this register. Note: This register field is sticky." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x0 0.--4. 1. "TYPE,When the address of an outbound TLP is matched to this region then the TYPE field of the TLP is changed to the value in this register. Note: This register field is sticky." repeat.end repeat 8. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 )(list 0x0 0x200 0x400 0x600 0x800 0xA00 0xC00 0xE00 ) group.long ($2+0x4+0xC0000)++0x3 line.long 0x0 "IATU_REGION_CTRL_2_OFF_OUTBOUND_$1,iATU Region Control 2 Register." bitfld.long 0x0 31. "REGION_EN,Region Enable. This bit must be set to '1' for address translation to take place. Note: This register field is sticky." "0,1" newline bitfld.long 0x0 29. "INVERT_MODE,Invert Mode. When set the address matching region is inverted. Therefore an address match occurs when the untranslated address is in the region outside the defined range (Base Address to Limit Address). Note: This register field is sticky." "0,1" newline bitfld.long 0x0 28. "CFG_SHIFT_MODE,CFG Shift Mode. The iATU uses bits [27:12] of the untranslated address (on the XALI0/1/2 interface or AXI slave interface address) to form the BDF number of the outgoing CFG TLP. This supports the Enhanced Configuration Address Mapping.." "0,1" newline bitfld.long 0x0 27. "DMA_BYPASS,DMA Bypass Mode. Allows request TLPs which are initiated by the DMA controller to pass through the iATU untranslated. Note: This field is reserved for the SW product. You must set it to '0'. Note: This register field is sticky." "0,1" newline bitfld.long 0x0 23. "HEADER_SUBSTITUTE_EN,Header Substitute Enable. When enabled and region address is matched the iATU fully substitutes bytes 8-11 (for 3 DWORD header) or bytes 12-15 (for 4 DWORD header) of the outbound TLP header with the contents of the LWR_TARGET_RW.." "LWR_TARGET_RW in the..,LWR_TARGET_RW in the.." newline bitfld.long 0x0 22. "INHIBIT_PAYLOAD,Inhibit TLP Payload Data for TLP's in Matched Region; assign iATU region to be TLP without data. When enabled and region address is matched the iATU marks all TLPs as having no payload data by forcing the TLP header Fmt[1] bit =0.." "Fmt[1] =0/1 so that TLPs with or without data..,Fmt[1] =0 so that only TLP type without data is.." newline bitfld.long 0x0 21. "TLP_HEADER_FIELDS_BYPASS,TLP Header Fields Translation Bypass. In this mode header fields of the translated TLP is taken from your application transmit interface or if AMBA is configured from the AMBA sideband bus (slv_awmisc_info) and not from the.." "0,1" newline bitfld.long 0x0 20. "SNP,Serialize Non-Posted Requests. In this mode when the AXI Bridge is populated same AXI ID Non-Posted Read/Write Requests are transmitted on the wire if there are no other same ID Non-Posted Requests outstanding. Note: This register field is sticky." "0,1" newline bitfld.long 0x0 19. "FUNC_BYPASS,Function Number Translation Bypass. In this mode the function number of the translated TLP is taken from your application transmit interface and not from the CTRL_1_FUNC_NUM field of the 'iATU Control 1 Register' or the VF_NUMBER field of.." "0,1" newline bitfld.long 0x0 16. "TAG_SUBSTITUTE_EN,TAG Substitute Enable. When enabled and region address is matched the iATU substitutes the TAG field of the outbound TLP header with the contents of the TAG field in this register. The expected usage scenario is translation from AXI.." "0,1" newline hexmask.long.byte 0x0 8.--15. 1. "TAG,TAG. The substituted TAG field (byte 6) in the outgoing TLP header when TAG_SUBSTITUTE_EN is set. Note: This register field is sticky." newline hexmask.long.byte 0x0 0.--7. 1. "MSG_CODE,MSG TLPs (Message Code). When the address of an outbound TLP is matched to this region and the translated TLP TYPE field is Msg or MsgD; then the message field of the TLP is changed to the value in this register. Memory TLPs: (ST;Steering Tag)." repeat.end repeat 8. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 )(list 0x0 0x200 0x400 0x600 0x800 0xA00 0xC00 0xE00 ) group.long ($2+0x8+0xC0000)++0x3 line.long 0x0 "IATU_LWR_BASE_ADDR_OFF_OUTBOUND_$1,iATU Lower Base Address Register. The CX_ATU_MIN_REGION_SIZE configuration parameter (Value Range: 4 kB. 8 kB. 16 kB. 32 kB. 64 kB defaults to 64 kB) specifies the minimum size of an address translation region. For.." hexmask.long.tbyte 0x0 12.--31. 1. "LWR_BASE_RW,Forms bits [31:n] of the start address of the address region to be translated. n is log2(CX_ATU_MIN_REGION_SIZE) Note: This register field is sticky." newline hexmask.long.word 0x0 0.--11. 1. "LWR_BASE_HW,Forms bits [n-1:0] of the start address of the address region to be translated. The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary so these bits are always 0. A write to this location is ignored by the PCIe controller." repeat.end repeat 8. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 )(list 0x0 0x200 0x400 0x600 0x800 0xA00 0xC00 0xE00 ) group.long ($2+0xC+0xC0000)++0x3 line.long 0x0 "IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_$1,iATU Upper Base Address Register." hexmask.long 0x0 0.--31. 1. "UPPER_BASE_RW,Forms bits [63:32] of the start (and end) address of the address region to be translated. In systems with a 32-bit address space this register is not used and therefore writing to this register has no effect. Note: This register field is.." repeat.end repeat 8. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 )(list 0x0 0x200 0x400 0x600 0x800 0xA00 0xC00 0xE00 ) group.long ($2+0x10+0xC0000)++0x3 line.long 0x0 "IATU_LIMIT_ADDR_OFF_OUTBOUND_$1,iATU Limit Address Register." hexmask.long.tbyte 0x0 12.--31. 1. "LIMIT_ADDR_RW,Forms upper bits of the end address of the address region to be translated. Note: This register field is sticky." newline hexmask.long.word 0x0 0.--11. 1. "LIMIT_ADDR_HW,Forms lower bits of the end address of the address region to be translated. The end address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary so these bits are always all ones. A write to this location is ignored by the PCIe.." repeat.end repeat 8. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 )(list 0x0 0x200 0x400 0x600 0x800 0xA00 0xC00 0xE00 ) group.long ($2+0x14+0xC0000)++0x3 line.long 0x0 "IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_$1,iATU Lower Target Address Register." hexmask.long 0x0 0.--31. 1. "LWR_TARGET_RW_OUTBOUND,When HEADER_SUBSTITUTE_EN in IATU_REGION_CTRL_2_OFF_OUTBOUND_ is '0' (normal operation): - LWR_TARGET_RW[31:n] forms MSB's of the Lower Target part of the new address of the translated region; - LWR_TARGET_RW[n-1:0] are not used." repeat.end repeat 8. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 )(list 0x0 0x200 0x400 0x600 0x800 0xA00 0xC00 0xE00 ) group.long ($2+0x18+0xC0000)++0x3 line.long 0x0 "IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_$1,iATU Upper Target Address Register." hexmask.long 0x0 0.--31. 1. "UPPER_TARGET_RW,Forms bits [63:32] of the start address (Upper Target part) of the new address of the translated region. Note: This register field is sticky." repeat.end repeat 8. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 )(list 0x0 0x200 0x400 0x600 0x800 0xA00 0xC00 0xE00 ) group.long ($2+0x1C+0xC0000)++0x3 line.long 0x0 "IATU_REGION_CTRL_3_OFF_OUTBOUND_$1,iATU Region Control 3 Register." bitfld.long 0x0 31. "VF_ACTIVE,Virtual Function Active. Indicates that all of the outbound accesses are from virtual functions. For more details see VF_ACTIVE field. Note: This register field is sticky." "0,1" newline hexmask.long 0x0 3.--30. 1. "RSVDP_VF_NUMBER,Reserved for future use." newline bitfld.long 0x0 0.--2. "VF_NUMBER,Virtual Function Number. When the address of an outbound TLP is matched to this region and the FUNC_BYPASS field in the 'iATU Control 2 Register' is '0' then this field used in generating the Function part of the requester ID (RID) field of.." "0,1,2,3,4,5,6,7" repeat.end repeat 8. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 )(list 0x0 0x200 0x400 0x600 0x800 0xA00 0xC00 0xE00 ) group.long ($2+0x100+0xC0000)++0x3 line.long 0x0 "IATU_REGION_CTRL_1_OFF_INBOUND_$1,iATU Region Control 1 Register." bitfld.long 0x0 20. "CTRL_1_FUNC_NUM,Function Number. - MEM-I/O: When the Address and BAR matching logic in the controller indicate that a MEM-I/O transaction matches a BAR in the function corresponding to this value then address translation proceeds. This check is only.." "?,When the destination function number as.." newline bitfld.long 0x0 13. "INCREASE_REGION_SIZE,Increase the maximum ATU Region size. When set the maximum ATU Region size is determined by CX_ATU_MAX_REGION_SIZE. When clear the maximum ATU Region size is 4 GB (default). Note: This register field is sticky." "0,1" newline bitfld.long 0x0 9.--10. "ATTR,When the ATTR field of an inbound TLP is matched to this value then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the 'ATTR Match Enable' bit of the 'iATU Control 2 Register' is.." "0,1,2,3" newline bitfld.long 0x0 8. "TD,When the TD field of an inbound TLP is matched to this value then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the 'TD Match Enable' bit of the 'iATU Control 2 Register' is set." "0,1" newline bitfld.long 0x0 5.--7. "TC,When the TC field of an inbound TLP is matched to this value then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the 'TC Match Enable' bit of the 'iATU Control 2 Register' is set." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x0 0.--4. 1. "TYPE,When the TYPE field of an inbound TLP is matched to this value then address translation proceeds (when all other enabled field-matches are successful). Note: This register field is sticky." repeat.end repeat 8. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 )(list 0x0 0x200 0x400 0x600 0x800 0xA00 0xC00 0xE00 ) group.long ($2+0x104+0xC0000)++0x3 line.long 0x0 "IATU_REGION_CTRL_2_OFF_INBOUND_$1,iATU Region Control 2 Register." bitfld.long 0x0 31. "REGION_EN,Region Enable. This bit must be set to '1' for address translation to take place. Note: This register field is sticky." "0,1" newline bitfld.long 0x0 30. "MATCH_MODE,Match Mode. Determines Inbound matching mode for TLPs. The mode depends on the type of TLP that is received as follows: For MEM-I/O TLPs this field is interpreted as follows: - 0: Address Match Mode. The iATU operates using addresses as in.." "Address Match Mode,Vendor ID Match Mode" newline bitfld.long 0x0 29. "INVERT_MODE,Invert Mode. When set the address matching region is inverted. Therefore an address match occurs when the untranslated address is in the region outside the defined range (Base Address to Limit Address). Note: This register field is sticky." "0,1" newline bitfld.long 0x0 28. "CFG_SHIFT_MODE,CFG Shift Mode. This is useful for CFG transactions where the PCIe configuration mechanism maps bits [27:12] of the address to the bus/device and function number. This allows a CFG configuration space to be located in any 256MB window of.." "0,1" newline bitfld.long 0x0 27. "FUZZY_TYPE_MATCH_CODE,Fuzzy Type Match Mode. When enabled the iATU relaxes the matching of the TLP TYPE field against the expected TYPE field so that - CfgRd0 and CfgRd1 TLPs are seen as identical. Similarly with CfgWr0 and CfgWr1. - MWr MRd and MRdLk.." "0,1" newline bitfld.long 0x0 26. "VFBAR_MATCH_MODE_EN,VF BAR Match Mode enable. When set Virtual Function BAR matching is used which allows all VFs in a PF which match a BAR to be matched with a single ATU region. Note: This register field is sticky." "0,1" newline bitfld.long 0x0 24.--25. "RESPONSE_CODE,Response Code. Defines the type of response to give for accesses matching this region. This overrides the normal RADM filter response. Note that this feature is not available for any region where Single Address Location Translate is.." "Normal RADM filter response is used,Unsupported request,?,?" newline bitfld.long 0x0 23. "SINGLE_ADDR_LOC_TRANS_EN,Single Address Location Translate Enable. When enabled Rx TLPs can be translated to a single address location as determined by the target address register of the iATU region. The main usage scenario is translation of Messages.." "0,1" newline bitfld.long 0x0 21. "MSG_CODE_MATCH_EN,Message Code Match Enable (Msg TLPS). Ensures that a successful message Code TLP field comparison match (see Message Code field of the 'iATU Control 2 Register') occurs (in MSG transactions) for address translation to proceed. ST Match.." "0,1" newline bitfld.long 0x0 20. "VF_MATCH_EN,Virtual Function Number Match Enable. Ensures that a successful Virtual Function Number TLP field comparison match (see Virtual Function Number field of the 'iATU Control 3 Register') occurs (in MEM-I/O transactions) for address translation.." "0,1" newline bitfld.long 0x0 19. "FUNC_NUM_MATCH_EN,Function Number Match Enable. Ensures that a successful Function Number TLP field comparison match (see Function Number field of the 'iATU Control 1 Register') occurs (in MEM-I/O and CFG0/CFG1 transactions) for address translation to.." "0,1" newline bitfld.long 0x0 16. "ATTR_MATCH_EN,ATTR Match Enable. Ensures that a successful ATTR TLP field comparison match (see ATTR field of the 'iATU Control 1 Register') occurs for address translation to proceed. Note: This register field is sticky." "0,1" newline bitfld.long 0x0 15. "TD_MATCH_EN,TD Match Enable. Ensures that a successful TD TLP field comparison match (see TD field of the 'iATU Control 1 Register') occurs for address translation to proceed. Note: This register field is sticky." "0,1" newline bitfld.long 0x0 14. "TC_MATCH_EN,TC Match Enable. Ensures that a successful TC TLP field comparison match (see TC field of the 'iATU Control 1 Register') occurs for address translation to proceed. Note: This register field is sticky." "0,1" newline bitfld.long 0x0 13. "MSG_TYPE_MATCH_MODE,Message Type Match Mode. When enabled and if single address location translate enable is set then inbound TLPs of type MSG/MSGd which match the type field of the iatu_region_ctrl_1_OFF_inbound register (=>TYPE[4:3]=2'b10) will be.." "0,1" newline bitfld.long 0x0 8.--10. "BAR_NUM,BAR Number. When the BAR number of an inbound MEM or IO TLP ' that is matched by the normal internal BAR address matching mechanism ' is the same as this field address translation proceeds (when all other enabled field-matches are successful)." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x0 0.--7. 1. "MSG_CODE,MSG TLPs: (Message Code). When the TYPE field of an inbound Msg/MsgD TLP is matched to this value then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the 'Message Code Match.." repeat.end repeat 8. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 )(list 0x0 0x200 0x400 0x600 0x800 0xA00 0xC00 0xE00 ) group.long ($2+0x108+0xC0000)++0x3 line.long 0x0 "IATU_LWR_BASE_ADDR_OFF_INBOUND_$1,iATU Lower Base Address Register. The CX_ATU_MIN_REGION_SIZE configuration parameter (Value Range: 4 kB. 8 kB. 16 kB. 32 kB. 64 kB defaults to 64 kB) specifies the minimum size of an address translation region. For.." hexmask.long.tbyte 0x0 12.--31. 1. "LWR_BASE_RW,Forms bits [31:n] of the start address of the address region to be translated. n is log2(CX_ATU_MIN_REGION_SIZE) Note: This register field is sticky." newline hexmask.long.word 0x0 0.--11. 1. "LWR_BASE_HW,Forms bits [n-1:0] of the start address of the address region to be translated. The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary so these bits are always 0. A write to this location is ignored by the PCIe controller." repeat.end repeat 8. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 )(list 0x0 0x200 0x400 0x600 0x800 0xA00 0xC00 0xE00 ) group.long ($2+0x10C+0xC0000)++0x3 line.long 0x0 "IATU_UPPER_BASE_ADDR_OFF_INBOUND_$1,iATU Upper Base Address Register." hexmask.long 0x0 0.--31. 1. "UPPER_BASE_RW,Forms bits [63:32] of the start (and end) address of the address region to be translated. Note: This register field is sticky." repeat.end repeat 8. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 )(list 0x0 0x200 0x400 0x600 0x800 0xA00 0xC00 0xE00 ) group.long ($2+0x110+0xC0000)++0x3 line.long 0x0 "IATU_LIMIT_ADDR_OFF_INBOUND_$1,iATU Limit Address Register." hexmask.long.tbyte 0x0 12.--31. 1. "LIMIT_ADDR_RW,Forms upper bits of the end address of the address region to be translated. Note: This register field is sticky." newline hexmask.long.word 0x0 0.--11. 1. "LIMIT_ADDR_HW,Forms lower bits of the end address of the address region to be translated. The end address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary so these bits are always all ones. A write to this location is ignored by the PCIe.." repeat.end repeat 8. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 )(list 0x0 0x200 0x400 0x600 0x800 0xA00 0xC00 0xE00 ) group.long ($2+0x114+0xC0000)++0x3 line.long 0x0 "IATU_LWR_TARGET_ADDR_OFF_INBOUND_$1,iATU Lower Target Address Register." hexmask.long.tbyte 0x0 12.--31. 1. "LWR_TARGET_RW,Forms MSB's of the Lower Target part of the new address of the translated region. These bits are always '0'. - Field size depends on log2(CX_ATU_MIN_REGION_SIZE) in address match mode. - Field size depends on log2(BAR_MASK+1) in BAR match.." newline hexmask.long.word 0x0 0.--11. 1. "LWR_TARGET_HW,Forms the LSB's of the Lower Target part of the new address of the translated region. The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary (in address match mode); and to the Bar size boundary (in BAR match mode) so.." repeat.end repeat 8. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 )(list 0x0 0x200 0x400 0x600 0x800 0xA00 0xC00 0xE00 ) group.long ($2+0x118+0xC0000)++0x3 line.long 0x0 "IATU_UPPER_TARGET_ADDR_OFF_INBOUND_$1,iATU Upper Target Address Register." hexmask.long 0x0 0.--31. 1. "UPPER_TARGET_RW,Forms bits [63:32] of the start address (Upper Target part) of the new address of the translated region. In systems with a 32-bit address space this register is not used and therefore writing to this register has no effect. Note: This.." repeat.end repeat 8. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 )(list 0x0 0x200 0x400 0x600 0x800 0xA00 0xC00 0xE00 ) group.long ($2+0x11C+0xC0000)++0x3 line.long 0x0 "IATU_REGION_CTRL_3_OFF_INBOUND_$1,iATU Region Control 3 Register." rbitfld.long 0x0 31. "VF_ACTIVE,Reserved. Not used." "0,1" newline hexmask.long 0x0 3.--30. 1. "RSVDP_VF_NUMBER,Reserved for future use." newline bitfld.long 0x0 0.--2. "VF_NUMBER,Virtual Function Number. When the Address and BAR matching logic in the controller indicates that a MEM-I/O transaction matches a BAR in the virtual function corresponding to this value then address translation proceeds. This check is only.." "0,1,2,3,4,5,6,7" repeat.end tree.end tree "PF0_PORT_LOGIC (Port Logic)" group.long (0x0+0x700)++0x27 line.long 0x0 "ACK_LATENCY_TIMER_OFF,Ack Latency Timer and Replay Timer Register." hexmask.long.word 0x0 16.--31. 1. "REPLAY_TIME_LIMIT,Replay Timer Limit. The replay timer expires when it reaches this limit. The controller initiates a replay upon reception of a NAK or when the replay timer expires. For more details see 'Transmit Replay'. You can modify the effective.." newline hexmask.long.word 0x0 0.--15. 1. "ROUND_TRIP_LATENCY_TIME_LIMIT,Ack Latency Timer Limit. The Ack latency timer expires when it reaches this limit. For more details see 'Ack Scheduling'. You can modify the effective timer limit with the TIMER_MOD_ACK_NAK field of the.." line.long 0x4 "VENDOR_SPEC_DLLP_OFF,Vendor Specific DLLP Register." hexmask.long 0x4 0.--31. 1. "VENDOR_SPEC_DLLP,Vendor Specific DLLP Register. Used to send a specific PCI Express DLLP. Your application writes the 8-bit DLLP Type and 24-bits of Payload data into this register then sets the field VENDOR_SPECIFIC_DLLP_REQ of PORT_LINK_CTRL_OFF to.." line.long 0x8 "PORT_FORCE_OFF,Port Force Link Register." hexmask.long.byte 0x8 24.--31. 1. "RSVDP_24,Reserved for future use." newline bitfld.long 0x8 23. "DO_DESKEW_FOR_SRIS,Use the transitions from TS2 to Logical Idle Symbol SKP OS to Logical Idle Symbol EIEOS to Logical Idle Symbol and FTS Sequence to SKP OS to do deskew instead of using received SKP OS or TS1 to TS2 transition if DO_DESKEW_FOR_SRIS.." "0,1" newline rbitfld.long 0x8 22. "RSVDP_22,Reserved for future use." "0,1" newline hexmask.long.byte 0x8 16.--21. 1. "LINK_STATE,Forced LTSSM State. The LTSSM state that the controller is forced to when you set the FORCE_EN bit (Force Link). LTSSM state encoding is defined by the lts_state variable in workspace/src/Layer1/smlh_ltssm.v. Note: This register field is sticky." newline bitfld.long 0x8 15. "FORCE_EN,Force Link. The controller supports a testing and debug capability to allow your software to force the LTSSM state machine into a specific state and to force the controller to transmit a specific Link Command. Asserting this bit triggers the.." "0,1" newline rbitfld.long 0x8 12.--14. "RSVDP_12,Reserved for future use." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x8 8.--11. 1. "FORCED_LTSSM,Forced Link Command. The link command that the controller is forced to transmit when you set FORCE_EN bit (Force Link). Link command encoding is defined by the ltssm_cmd variable in workspace/src/Layer1/smlh_ltssm.v. Note: This register.." newline hexmask.long.byte 0x8 0.--7. 1. "LINK_NUM,Link Number. Not used for endpoint. Not used for M-PCIe. Note: This register field is sticky." line.long 0xC "ACK_F_ASPM_CTRL_OFF,Ack Frequency and L0-L1 ASPM Control Register." rbitfld.long 0xC 31. "RSVDP_31,Reserved for future use." "0,1" newline bitfld.long 0xC 30. "ENTER_ASPM,ASPM L1 Entry Control. - 1: Controller enters ASPM L1 after a period in which it has been idle. - 0: Controller enters ASPM L1 only after idle period during which both receive and transmit are in L0s. Note: This register field is sticky." "Controller enters ASPM L1 only after idle period..,Controller enters ASPM L1 after a period in.." newline bitfld.long 0xC 27.--29. "L1_ENTRANCE_LATENCY,L1 Entrance Latency. Value range is: - 000: 1 us - 001: 2 us - 010: 4 us - 011: 8 us - 100: 16 us - 101: 32 us - 110 or 111: 64 us Note: Programming this timer with a value greater that 32us has no effect unless extended sync is used.." "0,1,2,3,4,5,6,7" newline bitfld.long 0xC 24.--26. "L0S_ENTRANCE_LATENCY,L0s Entrance Latency. Values correspond to: - 000: 1 us - 001: 2 us - 010: 3 us - 011: 4 us - 100: 5 us - 101: 6 us - 110 or 111: 7 us This field is applicable to STALL while in L0 for M-PCIe. Note: This register field is sticky." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0xC 16.--23. 1. "COMMON_CLK_N_FTS,Common Clock N_FTS. This is the N_FTS when common clock is used. The number of Fast Training Sequence ordered sets to be transmitted when transitioning from L0s to L0. The maximum number of FTS ordered-sets that a component can request.." newline hexmask.long.byte 0xC 8.--15. 1. "ACK_N_FTS,N_FTS. The number of Fast Training Sequence ordered sets to be transmitted when transitioning from L0s to L0. The maximum number of FTS ordered-sets that a component can request is 255. The controller does not support a value of zero; a value.." newline hexmask.long.byte 0xC 0.--7. 1. "ACK_FREQ,Ack Frequency. The controller accumulates the number of pending ACKs specified here (up to 255) before scheduling an ACK DLLP. - 0: Indicates that this Ack Frequency Counter feature is turned off. The controller generates a low-priority ACK.." line.long 0x10 "PORT_LINK_CTRL_OFF,Port Link Control Register." hexmask.long.byte 0x10 28.--31. 1. "RSVDP_28,Reserved for future use." newline bitfld.long 0x10 27. "TRANSMIT_LANE_REVERSALE_ENABLE,TRANSMIT_LANE_REVERSALE_ENABLE is an internally reserved field. Do not use. Note: This register field is sticky." "0,1" newline bitfld.long 0x10 26. "EXTENDED_SYNCH,EXTENDED_SYNCH is an internally reserved field. Do not use. Note: This register field is sticky." "0,1" newline bitfld.long 0x10 25. "CORRUPT_LCRC_ENABLE,CORRUPT_LCRC_ENABLE is an internally reserved field. Do not use. Note: This register field is sticky." "0,1" newline bitfld.long 0x10 24. "BEACON_ENABLE,BEACON_ENABLE is an internally reserved field. Do not use. Note: This register field is sticky." "0,1" newline hexmask.long.byte 0x10 16.--21. 1. "LINK_CAPABLE,Link Mode Enable. Sets the number of lanes in the link that you want to connect to the link partner. When you have unused lanes in your system then you must change the value in this register to reflect the number of lanes. You must also.." newline hexmask.long.byte 0x10 12.--15. 1. "RSVDP_12,Reserved for future use." newline hexmask.long.byte 0x10 8.--11. 1. "LINK_RATE,LINK_RATE is an internally reserved field. Do not use. Note: This register field is sticky." newline bitfld.long 0x10 7. "FAST_LINK_MODE,Fast Link Mode. Sets all internal LTSSM millisecond timers to Fast Mode for speeding up simulation. Forces the LTSSM training (link initialization) to use shorter time-outs and to link up faster. The default scaling factor can be changed.." "0,1" newline bitfld.long 0x10 6. "LINK_DISABLE,LINK_DISABLE is an internally reserved field. Do not use. Note: This register field is sticky." "0,1" newline bitfld.long 0x10 5. "DLL_LINK_EN,DLL Link Enable. Enables link initialization. When DLL Link Enable =0 the controller does not transmit InitFC DLLPs and does not establish a link. Note: This register field is sticky." "0,1" newline rbitfld.long 0x10 4. "RSVDP_4,Reserved for future use." "0,1" newline bitfld.long 0x10 3. "RESET_ASSERT,Reset Assert. Triggers a recovery and forces the LTSSM to the hot reset state (downstream port only). Note: This register field is sticky." "0,1" newline bitfld.long 0x10 2. "LOOPBACK_ENABLE,Loopback Enable. Turns on loopback. For more details see 'Loopback'. For M-PCIe to force the master to enter Digital Loopback mode you must set this field to '1' during Configuration.start state(initial discovery/configuration). M-PCIe.." "0,1" newline bitfld.long 0x10 1. "SCRAMBLE_DISABLE,Scramble Disable. Turns off data scrambling. Note: This register field is sticky." "0,1" newline bitfld.long 0x10 0. "VENDOR_SPECIFIC_DLLP_REQ,Vendor Specific DLLP Request. When software writes a '1' to this bit the controller transmits the DLLP contained in the VENDOR_SPEC_DLLP field of VENDOR_SPEC_DLLP_OFF. Reading from this self-clearing register field always.." "0,1" line.long 0x14 "LANE_SKEW_OFF,Lane Skew Register." bitfld.long 0x14 31. "DISABLE_LANE_TO_LANE_DESKEW,Disable Lane-to-Lane Deskew. Causes the controller to disable the internal Lane-to-Lane deskew logic. Note: This register field is sticky." "0,1" newline hexmask.long.byte 0x14 27.--30. 1. "IMPLEMENT_NUM_LANES,Implementation-specific Number of Lanes. Set the implementation-specific number of lanes. Allowed values are: - 4'b0000: 1 lane - 4'b0001: 2 lanes - 4'b0011: 4 lanes - 4'b0111: 8 lanes - 4'b1111: 16 lanes The number of lanes to be.." newline bitfld.long 0x14 26. "ELASTIC_BUFFER_MODE,Selects Elasticity Buffer operating mode: 0: Nominal Half Full Buffer mode 1: Nominal Empty Buffer Mode Note: This register field is sticky." "Nominal Half Full Buffer mode,Nominal Empty Buffer Mode" newline bitfld.long 0x14 25. "ACK_NAK_DISABLE,Ack/Nak Disable. Prevents the controller from sending ACK and NAK DLLPs. Note: This register field is sticky." "0,1" newline bitfld.long 0x14 24. "FLOW_CTRL_DISABLE,Flow Control Disable. Prevents the controller from sending FC DLLPs. Note: This register field is sticky." "0,1" newline hexmask.long.tbyte 0x14 0.--23. 1. "INSERT_LANE_SKEW,INSERT_LANE_SKEW is an internally reserved field. Do not use. Note: This register field is sticky." line.long 0x18 "TIMER_CTRL_MAX_FUNC_NUM_OFF,Timer Control and Max Function Number Register." rbitfld.long 0x18 31. "RSVDP_31,Reserved for future use." "0,1" newline bitfld.long 0x18 29.--30. "FAST_LINK_SCALING_FACTOR,Fast Link Timer Scaling Factor. Sets the scaling factor of LTSSM timer when FAST_LINK_MODE field in PORT_LINK_CTRL_OFF is set to '1'. - 0: Scaling Factor is 1024 (1ms is 1us *a) - 1: Scaling Factor is 256 (1ms is 4us) - 2:.." "Scaling Factor is 1024,Scaling Factor is 256,Scaling Factor is 64,Scaling Factor is 16" newline hexmask.long.byte 0x18 24.--28. 1. "UPDATE_FREQ_TIMER,UPDATE_FREQ_TIMER is an internally reserved field. Do not use. Note: This register field is sticky." newline hexmask.long.byte 0x18 19.--23. 1. "TIMER_MOD_ACK_NAK,Ack Latency Timer Modifier. Increases the timer value for the Ack latency timer in increments of 64 clock cycles. A value of '0' represents no modification to the timer value. For more details see the ROUND_TRIP_LATENCY_TIME_LIMIT.." newline hexmask.long.byte 0x18 14.--18. 1. "TIMER_MOD_REPLAY_TIMER,Replay Timer Limit Modifier. Increases the time-out value for the replay timer in increments of 64 clock cycles at Gen1 or Gen2 speed and in increments of 256 clock cycles at Gen3 speed. A value of '0' represents no modification.." newline hexmask.long.byte 0x18 8.--13. 1. "RSVDP_8,Reserved for future use." newline hexmask.long.byte 0x18 0.--7. 1. "MAX_FUNC_NUM,Maximum function number that can be used in a request. Configuration requests targeted at function numbers above this value are returned with UR (unsupported request). Note: This register field is sticky." line.long 0x1C "SYMBOL_TIMER_FILTER_1_OFF,Symbol Timer Register and Filter Mask 1 Register. The Filter Mask 1 Register modifies the RADM filtering and error handling rules. For more details. see the 'Receive Filtering' section. In each case. '0' applies the associated.." hexmask.long.word 0x1C 16.--31. 1. "MASK_RADM_1,Filter Mask 1. The Filter Mask 1 Register modifies the RADM filtering and error handling rules. For more details see the 'Receive Filtering' section. In each case '0' applies the associated filtering rule and '1' masks the associated.." newline bitfld.long 0x1C 15. "DISABLE_FC_WD_TIMER,Disable FC Watchdog Timer. Note: This register field is sticky." "0,1" newline hexmask.long.byte 0x1C 11.--14. 1. "EIDLE_TIMER,EIDLE_TIMER is an internally reserved field. Do not use. Note: This register field is sticky." newline hexmask.long.word 0x1C 0.--10. 1. "SKP_INT_VAL,SKP Interval Value. The number of symbol times to wait between transmitting SKP ordered sets. Note that the controller actually waits the number of symbol times in this register plus 1 between transmitting SKP ordered sets. Your application.." line.long 0x20 "FILTER_MASK_2_OFF,Filter Mask 2 Register. This register modifies the RADM filtering and error handling rules. For more details. see the 'Receive Filtering' section. In each case. '0' applies the associated filtering rule and '1' masks the associated.." hexmask.long 0x20 0.--31. 1. "MASK_RADM_2,Filter Mask 2. This field modifies the RADM filtering and error handling rules. For more details see the 'Receive Filtering' section. In each case '0' applies the associated filtering rule and '1' masks the associated filtering rule." line.long 0x24 "AMBA_MUL_OB_DECOMP_NP_SUB_REQ_CTRL_OFF,AMBA Multiple Outbound Decomposed NP SubRequests Control Register." hexmask.long 0x24 1.--31. 1. "RSVDP_1,Reserved for future use." newline bitfld.long 0x24 0. "OB_RD_SPLIT_BURST_EN,Enable AMBA Multiple Outbound Decomposed NP SubRequests. This bit when set to '0' disables the possibility of having multiple outstanding non-posted requests that were derived from decomposition of an outbound AMBA request. For more.." "0,1" rgroup.long (0x28+0x700)++0x13 line.long 0x0 "PL_DEBUG0_OFF,Debug Register 0" hexmask.long 0x0 0.--31. 1. "DEB_REG_0,The value on cxpl_debug_info[31:0]." line.long 0x4 "PL_DEBUG1_OFF,Debug Register 1" hexmask.long 0x4 0.--31. 1. "DEB_REG_1,The value on cxpl_debug_info[63:32]." line.long 0x8 "TX_P_FC_CREDIT_STATUS_OFF,Transmit Posted FC Credit Status" hexmask.long.word 0x8 20.--31. 1. "RSVDP_TX_P_FC_CREDIT_STATUS,Reserved for future use." newline hexmask.long.byte 0x8 12.--19. 1. "TX_P_HEADER_FC_CREDIT,Transmit Posted Header FC Credits. The posted Header credits advertised by the receiver at the other end of the link updated with each UpdateFC DLLP. Default value depends on the number of advertised credits for header and data.." newline hexmask.long.word 0x8 0.--11. 1. "TX_P_DATA_FC_CREDIT,Transmit Posted Data FC Credits. The posted Data credits advertised by the receiver at the other end of the link updated with each UpdateFC DLLP. Default value depends on the number of advertised credits for header and data Scaled.." line.long 0xC "TX_NP_FC_CREDIT_STATUS_OFF,Transmit Non-Posted FC Credit Status" hexmask.long.word 0xC 20.--31. 1. "RSVDP_TX_NP_FC_CREDIT_STATUS,Reserved for future use." newline hexmask.long.byte 0xC 12.--19. 1. "TX_NP_HEADER_FC_CREDIT,Transmit Non-Posted Header FC Credits. The non-posted Header credits advertised by the receiver at the other end of the link updated with each UpdateFC DLLP. Default value depends on the number of advertised credits for header and.." newline hexmask.long.word 0xC 0.--11. 1. "TX_NP_DATA_FC_CREDIT,Transmit Non-Posted Data FC Credits. The non-posted Data credits advertised by the receiver at the other end of the link updated with each UpdateFC DLLP. Default value depends on the number of advertised credits for header and data.." line.long 0x10 "TX_CPL_FC_CREDIT_STATUS_OFF,Transmit Completion FC Credit Status" hexmask.long.word 0x10 20.--31. 1. "RSVDP_TX_CPL_FC_CREDIT_STATUS,Reserved for future use." newline hexmask.long.byte 0x10 12.--19. 1. "TX_CPL_HEADER_FC_CREDIT,Transmit Completion Header FC Credits. The Completion Header credits advertised by the receiver at the other end of the link updated with each UpdateFC DLLP. Default value depends on the number of advertised credits for header.." newline hexmask.long.word 0x10 0.--11. 1. "TX_CPL_DATA_FC_CREDIT,Transmit Completion Data FC Credits. The Completion Data credits advertised by the receiver at the other end of the link updated with each UpdateFC DLLP. Default value depends on the number of advertised credits for header and data.." group.long (0x3C+0x700)++0x3 line.long 0x0 "QUEUE_STATUS_OFF,Queue Status" bitfld.long 0x0 31. "TIMER_MOD_FLOW_CONTROL_EN,FC Latency Timer Override Enable. When this bit is set the value from the 'FC Latency Timer Override Value' field in this register will override the FC latency timer value that the controller calculates according to the PCIe.." "0,1" newline rbitfld.long 0x0 29.--30. "RSVDP_29,Reserved for future use." "0,1,2,3" newline hexmask.long.word 0x0 16.--28. 1. "TIMER_MOD_FLOW_CONTROL,FC Latency Timer Override Value. When you set the 'FC Latency Timer Override Enable' in this register the value in this field will override the FC latency timer value that the controller calculates according to the PCIe.." newline rbitfld.long 0x0 13. "RX_SERIALIZATION_Q_NON_EMPTY,Receive Serialization Queue Not Empty. Indicates there is data in the serialization queue." "0,1" newline hexmask.long.word 0x0 4.--12. 1. "RSVDP_4,Reserved for future use." newline bitfld.long 0x0 3. "RX_QUEUE_OVERFLOW,Receive Credit Queue Overflow. Indicates insufficient buffer space available to write to the P/NP/CPL credit queue." "0,1" newline rbitfld.long 0x0 2. "RX_QUEUE_NON_EMPTY,Receive Credit Queue Not Empty. Indicates there is data in one or more of the receive buffers." "0,1" newline rbitfld.long 0x0 1. "TX_RETRY_BUFFER_NE,Transmit Retry Buffer Not Empty. Indicates that there is data in the transmit retry buffer." "0,1" newline rbitfld.long 0x0 0. "RX_TLP_FC_CREDIT_NON_RETURN,Received TLP FC Credits Not Returned. Indicates that the controller has received a TLP but has not yet sent an UpdateFC DLLP indicating that the credits for that TLP have been restored by the receiver at the other end of the.." "0,1" rgroup.long (0x40+0x700)++0x7 line.long 0x0 "VC_TX_ARBI_1_OFF,VC Transmit Arbitration Register 1" hexmask.long.byte 0x0 24.--31. 1. "WRR_WEIGHT_VC_3,WRR Weight for VC3. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R" newline hexmask.long.byte 0x0 16.--23. 1. "WRR_WEIGHT_VC_2,WRR Weight for VC2. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R" newline hexmask.long.byte 0x0 8.--15. 1. "WRR_WEIGHT_VC_1,WRR Weight for VC1. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R" newline hexmask.long.byte 0x0 0.--7. 1. "WRR_WEIGHT_VC_0,WRR Weight for VC0. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R" line.long 0x4 "VC_TX_ARBI_2_OFF,VC Transmit Arbitration Register 2" hexmask.long.byte 0x4 24.--31. 1. "WRR_WEIGHT_VC_7,WRR Weight for VC7. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R" newline hexmask.long.byte 0x4 16.--23. 1. "WRR_WEIGHT_VC_6,WRR Weight for VC6. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R" newline hexmask.long.byte 0x4 8.--15. 1. "WRR_WEIGHT_VC_5,WRR Weight for VC5. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R" newline hexmask.long.byte 0x4 0.--7. 1. "WRR_WEIGHT_VC_4,WRR Weight for VC4. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R" group.long (0x48+0x700)++0xB line.long 0x0 "VC0_P_RX_Q_CTRL_OFF,Segmented-Buffer VC0 Posted Receive Queue Control." bitfld.long 0x0 31. "VC_ORDERING_RX_Q,VC Ordering for Receive Queues. Determines the VC ordering rule for the receive queues used only in the segmented-buffer configuration: - 1: Strict ordering higher numbered VCs have higher priority - 0: Round robin Note: This register.." "Round robin,Strict ordering" newline bitfld.long 0x0 30. "TLP_TYPE_ORDERING_VC0,TLP Type Ordering for VC0. Determines the TLP type ordering rule for VC0 receive queues used only in the segmented-buffer configuration: - 1: PCIe ordering rules (recommended) - 0: Strict ordering: posted completion then.." "Strict ordering: posted,PCIe ordering rules" newline bitfld.long 0x0 28.--29. "RESERVED5,Reserved. Note: This register field is sticky." "0,1,2,3" newline bitfld.long 0x0 26.--27. "VC0_P_DATA_SCALE,VC0 Scale Posted Data Credites. Note: This register field is sticky." "0,1,2,3" newline bitfld.long 0x0 24.--25. "VC0_P_HDR_SCALE,VC0 Scale Posted Header Credites. Note: This register field is sticky." "0,1,2,3" newline bitfld.long 0x0 21.--23. "VC0_P_TLP_Q_MODE,Reserved. Note: This register field is sticky." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 20. "RESERVED4,Reserved. Note: This register field is sticky." "0,1" newline hexmask.long.byte 0x0 12.--19. 1. "VC0_P_HEADER_CREDIT,VC0 Posted Header Credits. The number of initial posted header credits for VC0 used only in the segmented-buffer configuration. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R (sticky) Note: This.." newline hexmask.long.word 0x0 0.--11. 1. "VC0_P_DATA_CREDIT,VC0 Posted Data Credits. The number of initial posted data credits for VC0 used only in the segmented-buffer configuration. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R (sticky) Note: This.." line.long 0x4 "VC0_NP_RX_Q_CTRL_OFF,Segmented-Buffer VC0 Non-Posted Receive Queue Control." hexmask.long.byte 0x4 28.--31. 1. "RESERVED7,Reserved. Note: This register field is sticky." newline bitfld.long 0x4 26.--27. "VC0_NP_DATA_SCALE,VC0 Scale Non-Posted Data Credites. Note: This register field is sticky." "0,1,2,3" newline bitfld.long 0x4 24.--25. "VC0_NP_HDR_SCALE,VC0 Scale Non-Posted Header Credites. Note: This register field is sticky." "0,1,2,3" newline bitfld.long 0x4 21.--23. "VC0_NP_TLP_Q_MODE,Reserved. Note: This register field is sticky." "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 20. "RESERVED6,Reserved. Note: This register field is sticky." "0,1" newline hexmask.long.byte 0x4 12.--19. 1. "VC0_NP_HEADER_CREDIT,VC0 Non-Posted Header Credits. The number of initial non-posted header credits for VC0 used only in the segmented-buffer configuration. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R (sticky).." newline hexmask.long.word 0x4 0.--11. 1. "VC0_NP_DATA_CREDIT,VC0 Non-Posted Data Credits. The number of initial non-posted data credits for VC0 used only in the segmented-buffer configuration. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R (sticky) Note:.." line.long 0x8 "VC0_CPL_RX_Q_CTRL_OFF,Segmented-Buffer VC0 Completion Receive Queue Control." hexmask.long.byte 0x8 28.--31. 1. "RESERVED9,Reserved. Note: This register field is sticky." newline bitfld.long 0x8 26.--27. "VC0_CPL_DATA_SCALE,VC0 Scale CPL Data Credites. Note: This register field is sticky." "0,1,2,3" newline bitfld.long 0x8 24.--25. "VC0_CPL_HDR_SCALE,VC0 Scale CPL Header Credites. Note: This register field is sticky." "0,1,2,3" newline bitfld.long 0x8 21.--23. "VC0_CPL_TLP_Q_MODE,Reserved. Note: This register field is sticky." "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 20. "RESERVED8,Reserved. Note: This register field is sticky." "0,1" newline hexmask.long.byte 0x8 12.--19. 1. "VC0_CPL_HEADER_CREDIT,VC0 Completion Header Credits. The number of initial Completion header credits for VC0 used only in the segmented-buffer configuration. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R (sticky).." newline hexmask.long.word 0x8 0.--11. 1. "VC0_CPL_DATA_CREDIT,VC0 Completion Data Credits. The number of initial Completion data credits for VC0 used only in the segmented-buffer configuration. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R (sticky) Note:.." group.long (0x10C+0x700)++0x3 line.long 0x0 "GEN2_CTRL_OFF,This register is used to control various functions of the controller related to link training. lane reversal. and equalization." rbitfld.long 0x0 31. "RSVDP_31,Reserved for future use." "0,1" newline bitfld.long 0x0 30. "FORCE_LANE_FLIP,Enable to force the LANE_UNDER_TEST physical lane flips to logical lane 0. All the other physical lanes are turned off. The LINK_CAPABLE register must be set to 1 and only x1 link can be formed if the FORCE_LANE_FLIP register is set to 1." "0,1" newline hexmask.long.byte 0x0 24.--27. 1. "LANE_UNDER_TEST,The Lane Under Test is the lane for Forced Lane Flip or for Loopback Eq. The value is from 0 to CX_NL. Only one lane is configured each time. The default of this field is the CX_DEFAULT_LANE_UNDER_TEST configuration parameter. This field.." newline rbitfld.long 0x0 22.--23. "RSVDP_22,Reserved for future use." "0,1,2,3" newline bitfld.long 0x0 21. "GEN1_EI_INFERENCE,Electrical Idle Inference Mode at Gen1 Rate. Programmable mode to determine inferred electrical idle (EI) in Recovery.Speed or Loopback.Active (as slave) state at Gen1 speed by looking for a '1' value on RxElecIdle instead of looking.." "Use RxElecIdle signal to infer Electrical Idle,Use RxValid signal to infer Electrical Idle" newline bitfld.long 0x0 20. "SEL_DEEMPHASIS,Used to set the de-emphasis level for upstream ports. This bit selects the level of de-emphasis the link operates at. - 0: -6 dB - 1: -3.5 dB This field is reserved (fixed to '0') for M-PCIe. Note: The access attributes of this field are.." "0,1" newline bitfld.long 0x0 19. "CONFIG_TX_COMP_RX,Config Tx Compliance Receive Bit. When set to 1 signals LTSSM to transmit TS ordered sets with the compliance receive bit assert (equal to '1'). This field is reserved (fixed to '0') for M-PCIe. Note: The access attributes of this.." "0,1" newline bitfld.long 0x0 18. "CONFIG_PHY_TX_CHANGE,Config PHY Tx Swing. Controls the PHY transmitter voltage swing level. The controller drives the mac_phy_txswing output from this register bit field. - 0: Full Swing - 1: Low Swing This field is reserved (fixed to '0') for M-PCIe." "Full Swing,Low Swing" newline bitfld.long 0x0 17. "DIRECT_SPEED_CHANGE,Directed Speed Change. Writing '1' to this field instructs the LTSSM to initiate a speed change to Gen2 or Gen3 after the link is initialized at Gen1 speed. When the speed change occurs the controller will clear the contents of this.." "0,1" newline bitfld.long 0x0 16. "AUTO_LANE_FLIP_CTRL_EN,Enable Auto flipping of the lanes. You must set the CX_AUTO_LANE_FLIP_CTRL_EN configuration parameter to include the hardware for this feature in the controller. For more details see the 'Lane Reversal' appendix in the Databook." "0,1" newline bitfld.long 0x0 13.--15. "PRE_DET_LANE,Predetermined Lane for Auto Flip. This field defines which physical lane is connected to logical Lane0 by the flip operation performed in Detect. This field is used to restrict the receiver detect procedure to a particular lane when the.." "LANE0,LANE1,LANE3,LANE7,LANE15,?,?,?" newline hexmask.long.byte 0x0 8.--12. 1. "NUM_OF_LANES,Predetermined Number of Lanes. Defines the number of lanes which are connected and not bad. Used to limit the effective link width to ignore 'broken' or 'unused' lanes that detect a receiver. Indicates the number of lanes to check for exit.." newline hexmask.long.byte 0x0 0.--7. 1. "FAST_TRAINING_SEQ,Sets the Number of Fast Training Sequences (N_FTS) that the controller advertises as its N_FTS during Gen2 or Gen3 link training. This value is used to inform the link partner about the PHY's ability to recover synchronization after a.." rgroup.long (0x110+0x700)++0x3 line.long 0x0 "PHY_STATUS_OFF,PHY Status Register. Memory mapped register from phy_cfg_status GPIO input pins." hexmask.long 0x0 0.--31. 1. "PHY_STATUS,PHY Status. Data received directly from the phy_cfg_status bus. These is a GPIO register reflecting the values on the static phy_cfg_status input signals. The usage is left completely to the user and does not in any way influence controller.." group.long (0x114+0x700)++0x3 line.long 0x0 "PHY_CONTROL_OFF,PHY Control Register. Memory mapped register to cfg_phy_control GPIO output pins." hexmask.long 0x0 0.--31. 1. "PHY_CONTROL,PHY Control. Data sent directly to the cfg_phy_control bus. These is a GPIO register driving the values on the static cfg_phy_control output signals. The usage is left completely to the user and does not in any way influence controller.." group.long (0x11C+0x700)++0x77 line.long 0x0 "TRGT_MAP_CTRL_OFF,Programmable Target Map Control Register." hexmask.long.word 0x0 21.--31. 1. "TARGET_MAP_RESERVED_21_31,Reserved. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R (sticky)" newline hexmask.long.byte 0x0 16.--20. 1. "TARGET_MAP_INDEX,The number of the PF Function on which the Target Values are set. This register does not respect the Byte Enable setting. any write will affect all register bits." newline rbitfld.long 0x0 13.--15. "TARGET_MAP_RESERVED_13_15,Reserved. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R (sticky)" "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x0 7.--12. 1. "TARGET_MAP_VF,Target Values for each BAR on the VF Function selected by the index number. This register does not respect the Byte Enable setting. any write will affect all register bits." newline bitfld.long 0x0 6. "TARGET_MAP_ROM,Target Value for the ROM page of the PF Function selected by the index number. This register does not respect the Byte Enable setting. any write will affect all register bits." "0,1" newline hexmask.long.byte 0x0 0.--5. 1. "TARGET_MAP_PF,Target Values for each BAR on the PF Function selected by the index number. This register does not respect the Byte Enable setting. any write will affect all register bits." line.long 0x4 "MSI_CTRL_ADDR_OFF,Integrated MSI Reception Module (iMRM) Address Register." hexmask.long 0x4 0.--31. 1. "MSI_CTRL_ADDR,Integrated MSI Reception Module Address. System specified address for MSI memory write transaction termination. Within the AXI Bridge every received Memory Write request is examined to see if it targets the MSI Address that has been.." line.long 0x8 "MSI_CTRL_UPPER_ADDR_OFF,Integrated MSI Reception Module Upper Address Register." hexmask.long 0x8 0.--31. 1. "MSI_CTRL_UPPER_ADDR,Integrated MSI Reception Module Upper Address. System specified upper address for MSI memory write transaction termination. Allows functions to support a 64-bit MSI address. Note: This register field is sticky." line.long 0xC "MSI_CTRL_INT_0_EN_OFF,Integrated MSI Reception Module Interrupt#i Enable Register." hexmask.long 0xC 0.--31. 1. "MSI_CTRL_INT_0_EN,MSI Interrupt#i Enable. Specifies which interrupts are enabled. When an MSI is received from a disabled interrupt no status bit gets set in MSI controller interrupt status register. Each bit corresponds to a single MSI Interrupt.." line.long 0x10 "MSI_CTRL_INT_0_MASK_OFF,Integrated MSI Reception Module Interrupt#i Mask Register." hexmask.long 0x10 0.--31. 1. "MSI_CTRL_INT_0_MASK,MSI Interrupt#i Mask. Allows enabled interrupts to be masked. When an MSI is received for a masked interrupt the corresponding status bit gets set in the interrupt status register but the msi_ctrl_int output is not set HIGH. Each bit.." line.long 0x14 "MSI_CTRL_INT_0_STATUS_OFF,Integrated MSI Reception Module Interrupt#i Status Register." hexmask.long 0x14 0.--31. 1. "MSI_CTRL_INT_0_STATUS,MSI Interrupt#i Status. When an MSI is detected for EP#i one bit in this register is set. The decoding of the data payload of the MSI Memory Write request determines which bit gets set. A status is bit is cleared by writing a 1 to.." line.long 0x18 "MSI_CTRL_INT_1_EN_OFF,Integrated MSI Reception Module Interrupt#i Enable Register." hexmask.long 0x18 0.--31. 1. "MSI_CTRL_INT_1_EN,MSI Interrupt#i Enable. Specifies which interrupts are enabled. When an MSI is received from a disabled interrupt no status bit gets set in MSI controller interrupt status register. Each bit corresponds to a single MSI Interrupt.." line.long 0x1C "MSI_CTRL_INT_1_MASK_OFF,Integrated MSI Reception Module Interrupt#i Mask Register." hexmask.long 0x1C 0.--31. 1. "MSI_CTRL_INT_1_MASK,MSI Interrupt#i Mask. Allows enabled interrupts to be masked. When an MSI is received for a masked interrupt the corresponding status bit gets set in the interrupt status register but the msi_ctrl_int output is not set HIGH. Each bit.." line.long 0x20 "MSI_CTRL_INT_1_STATUS_OFF,Integrated MSI Reception Module Interrupt#i Status Register." hexmask.long 0x20 0.--31. 1. "MSI_CTRL_INT_1_STATUS,MSI Interrupt#i Status. When an MSI is detected for EP#i one bit in this register is set. The decoding of the data payload of the MSI Memory Write request determines which bit gets set. A status is bit is cleared by writing a 1 to.." line.long 0x24 "MSI_CTRL_INT_2_EN_OFF,Integrated MSI Reception Module Interrupt#i Enable Register." hexmask.long 0x24 0.--31. 1. "MSI_CTRL_INT_2_EN,MSI Interrupt#i Enable. Specifies which interrupts are enabled. When an MSI is received from a disabled interrupt no status bit gets set in MSI controller interrupt status register. Each bit corresponds to a single MSI Interrupt.." line.long 0x28 "MSI_CTRL_INT_2_MASK_OFF,Integrated MSI Reception Module Interrupt#i Mask Register." hexmask.long 0x28 0.--31. 1. "MSI_CTRL_INT_2_MASK,MSI Interrupt#i Mask. Allows enabled interrupts to be masked. When an MSI is received for a masked interrupt the corresponding status bit gets set in the interrupt status register but the msi_ctrl_int output is not set HIGH. Each bit.." line.long 0x2C "MSI_CTRL_INT_2_STATUS_OFF,Integrated MSI Reception Module Interrupt#i Status Register." hexmask.long 0x2C 0.--31. 1. "MSI_CTRL_INT_2_STATUS,MSI Interrupt#i Status. When an MSI is detected for EP#i one bit in this register is set. The decoding of the data payload of the MSI Memory Write request determines which bit gets set. A status is bit is cleared by writing a 1 to.." line.long 0x30 "MSI_CTRL_INT_3_EN_OFF,Integrated MSI Reception Module Interrupt#i Enable Register." hexmask.long 0x30 0.--31. 1. "MSI_CTRL_INT_3_EN,MSI Interrupt#i Enable. Specifies which interrupts are enabled. When an MSI is received from a disabled interrupt no status bit gets set in MSI controller interrupt status register. Each bit corresponds to a single MSI Interrupt.." line.long 0x34 "MSI_CTRL_INT_3_MASK_OFF,Integrated MSI Reception Module Interrupt#i Mask Register." hexmask.long 0x34 0.--31. 1. "MSI_CTRL_INT_3_MASK,MSI Interrupt#i Mask. Allows enabled interrupts to be masked. When an MSI is received for a masked interrupt the corresponding status bit gets set in the interrupt status register but the msi_ctrl_int output is not set HIGH. Each bit.." line.long 0x38 "MSI_CTRL_INT_3_STATUS_OFF,Integrated MSI Reception Module Interrupt#i Status Register." hexmask.long 0x38 0.--31. 1. "MSI_CTRL_INT_3_STATUS,MSI Interrupt#i Status. When an MSI is detected for EP#i one bit in this register is set. The decoding of the data payload of the MSI Memory Write request determines which bit gets set. A status is bit is cleared by writing a 1 to.." line.long 0x3C "MSI_CTRL_INT_4_EN_OFF,Integrated MSI Reception Module Interrupt#i Enable Register." hexmask.long 0x3C 0.--31. 1. "MSI_CTRL_INT_4_EN,MSI Interrupt#i Enable. Specifies which interrupts are enabled. When an MSI is received from a disabled interrupt no status bit gets set in MSI controller interrupt status register. Each bit corresponds to a single MSI Interrupt.." line.long 0x40 "MSI_CTRL_INT_4_MASK_OFF,Integrated MSI Reception Module Interrupt#i Mask Register." hexmask.long 0x40 0.--31. 1. "MSI_CTRL_INT_4_MASK,MSI Interrupt#i Mask. Allows enabled interrupts to be masked. When an MSI is received for a masked interrupt the corresponding status bit gets set in the interrupt status register but the msi_ctrl_int output is not set HIGH. Each bit.." line.long 0x44 "MSI_CTRL_INT_4_STATUS_OFF,Integrated MSI Reception Module Interrupt#i Status Register." hexmask.long 0x44 0.--31. 1. "MSI_CTRL_INT_4_STATUS,MSI Interrupt#i Status. When an MSI is detected for EP#i one bit in this register is set. The decoding of the data payload of the MSI Memory Write request determines which bit gets set. A status is bit is cleared by writing a 1 to.." line.long 0x48 "MSI_CTRL_INT_5_EN_OFF,Integrated MSI Reception Module Interrupt#i Enable Register." hexmask.long 0x48 0.--31. 1. "MSI_CTRL_INT_5_EN,MSI Interrupt#i Enable. Specifies which interrupts are enabled. When an MSI is received from a disabled interrupt no status bit gets set in MSI controller interrupt status register. Each bit corresponds to a single MSI Interrupt.." line.long 0x4C "MSI_CTRL_INT_5_MASK_OFF,Integrated MSI Reception Module Interrupt#i Mask Register." hexmask.long 0x4C 0.--31. 1. "MSI_CTRL_INT_5_MASK,MSI Interrupt#i Mask. Allows enabled interrupts to be masked. When an MSI is received for a masked interrupt the corresponding status bit gets set in the interrupt status register but the msi_ctrl_int output is not set HIGH. Each bit.." line.long 0x50 "MSI_CTRL_INT_5_STATUS_OFF,Integrated MSI Reception Module Interrupt#i Status Register." hexmask.long 0x50 0.--31. 1. "MSI_CTRL_INT_5_STATUS,MSI Interrupt#i Status. When an MSI is detected for EP#i one bit in this register is set. The decoding of the data payload of the MSI Memory Write request determines which bit gets set. A status is bit is cleared by writing a 1 to.." line.long 0x54 "MSI_CTRL_INT_6_EN_OFF,Integrated MSI Reception Module Interrupt#i Enable Register." hexmask.long 0x54 0.--31. 1. "MSI_CTRL_INT_6_EN,MSI Interrupt#i Enable. Specifies which interrupts are enabled. When an MSI is received from a disabled interrupt no status bit gets set in MSI controller interrupt status register. Each bit corresponds to a single MSI Interrupt.." line.long 0x58 "MSI_CTRL_INT_6_MASK_OFF,Integrated MSI Reception Module Interrupt#i Mask Register." hexmask.long 0x58 0.--31. 1. "MSI_CTRL_INT_6_MASK,MSI Interrupt#i Mask. Allows enabled interrupts to be masked. When an MSI is received for a masked interrupt the corresponding status bit gets set in the interrupt status register but the msi_ctrl_int output is not set HIGH. Each bit.." line.long 0x5C "MSI_CTRL_INT_6_STATUS_OFF,Integrated MSI Reception Module Interrupt#i Status Register." hexmask.long 0x5C 0.--31. 1. "MSI_CTRL_INT_6_STATUS,MSI Interrupt#i Status. When an MSI is detected for EP#i one bit in this register is set. The decoding of the data payload of the MSI Memory Write request determines which bit gets set. A status is bit is cleared by writing a 1 to.." line.long 0x60 "MSI_CTRL_INT_7_EN_OFF,Integrated MSI Reception Module Interrupt#i Enable Register." hexmask.long 0x60 0.--31. 1. "MSI_CTRL_INT_7_EN,MSI Interrupt#i Enable. Specifies which interrupts are enabled. When an MSI is received from a disabled interrupt no status bit gets set in MSI controller interrupt status register. Each bit corresponds to a single MSI Interrupt.." line.long 0x64 "MSI_CTRL_INT_7_MASK_OFF,Integrated MSI Reception Module Interrupt#i Mask Register." hexmask.long 0x64 0.--31. 1. "MSI_CTRL_INT_7_MASK,MSI Interrupt#i Mask. Allows enabled interrupts to be masked. When an MSI is received for a masked interrupt the corresponding status bit gets set in the interrupt status register but the msi_ctrl_int output is not set HIGH. Each bit.." line.long 0x68 "MSI_CTRL_INT_7_STATUS_OFF,Integrated MSI Reception Module Interrupt#i Status Register." hexmask.long 0x68 0.--31. 1. "MSI_CTRL_INT_7_STATUS,MSI Interrupt#i Status. When an MSI is detected for EP#i one bit in this register is set. The decoding of the data payload of the MSI Memory Write request determines which bit gets set. A status is bit is cleared by writing a 1 to.." line.long 0x6C "MSI_GPIO_IO_OFF,Integrated MSI Reception Module General Purpose IO Register." hexmask.long 0x6C 0.--31. 1. "MSI_GPIO_REG,MSI GPIO Register. The contents of this register drives the top-level GPIO msi_ctrl_io[31:0] Note: This register field is sticky." line.long 0x70 "CLOCK_GATING_CTRL_OFF,This register enables you to disable dynamic clock gating. By default dynamic clock gating is on. allowing the controller to autonomously enable and disable its clocks. The clock gating is performed in the clock and reset module." hexmask.long 0x70 2.--31. 1. "RSVDP_2,Reserved for future use." newline bitfld.long 0x70 1. "AXI_CLK_GATING_EN,AXI Clock Gating Enable. This register enables the AXI Bridge to autonomously enable and disable the AXI Master clock the AXI Slave clock and the AXI DBI slave clock. The DWC_pcie_clk_rst.v module provides the gated clock.." "Disable,Enable" newline bitfld.long 0x70 0. "RADM_CLK_GATING_EN,RADM Clock Gating Enable. This register if set enables the RADM to autonomously enable and disable its clock. The DWC_pcie_clk_rst.v module provides the gated clock radm_clk_g to the RADM and is enabled when the controllers clock.." "Disable,Enable" line.long 0x74 "GEN3_RELATED_OFF,Gen3 Control Register. There is no Gen3-specific N_FTS field. The N_FTS field in the 'Link Width and Speed Change Control Register' is used for both Gen2 and Gen3 speed modes. There is no Gen3-specific 'Directed Speed Change' field. The.." hexmask.long.byte 0x74 26.--31. 1. "RSVDP_26,Reserved for future use." newline bitfld.long 0x74 23. "GEN3_EQ_INVREQ_EVAL_DIFF_DISABLE,Eq InvalidRequest and RxEqEval Different Time Assertion Disable. Disable the assertion of Eq InvalidRequest and RxEqEval at different time. Note: When CX_GEN4_SPEED/CX_GEN5_SPEED this register is shared for Gen3 and.." "0,1" newline rbitfld.long 0x74 19.--20. "RSVDP_19,Reserved for future use." "0,1,2,3" newline bitfld.long 0x74 18. "GEN3_DC_BALANCE_DISABLE,DC Balance Disable. Disable DC Balance feature. Note: When CX_GEN4_SPEED/CX_GEN5_SPEED this register is shared for Gen3 and Gen4/Gen5 data rate. Note: This register field is sticky." "0,1" newline bitfld.long 0x74 17. "GEN3_DLLP_XMT_DELAY_DISABLE,DLLP Transmission Delay Disable. Disable delay transmission of DLLPs before equalization. Note: When CX_GEN4_SPEED/CX_GEN5_SPEED this register is shared for Gen3 and Gen4/Gen5 data rate. Note: This register field is sticky." "0,1" newline bitfld.long 0x74 16. "GEN3_EQUALIZATION_DISABLE,Equalization Disable. Disable equalization feature. This bit cannot be changed once the LTSSM starts link training. Note: When CX_GEN4_SPEED/CX_GEN5_SPEED this register is shared for Gen3 and Gen4/Gen5 data rate. Note: This.." "0,1" newline rbitfld.long 0x74 14.--15. "RSVDP_14,Reserved for future use." "0,1,2,3" newline bitfld.long 0x74 13. "RXEQ_RGRDLESS_RXTS,When set to '1' the controller as Gen3 EQ master asserts RxEqEval to instruct the PHY to do Rx adaptation and evaluation after a 500ns timeout from a new preset request. - 0: mac_phy_rxeqeval asserts after 1us and 2 TS1 received from.." "mac_phy_rxeqeval asserts after 1us and 2 TS1..,mac_phy_rxeqeval asserts after 500ns regardless.." newline bitfld.long 0x74 12. "RXEQ_PH01_EN,Rx Equalization Phase 0/Phase 1 Hold Enable. When this bit is set the upstream port holds phase 0 (the downstream port holds phase 1) for 10ms. Holding phase 0 or phase 1 can be used to allow sufficient time for Rx Equalization to be.." "Tx equalization only in phase 2/3,No Tx equalization" newline bitfld.long 0x74 11. "EQ_REDO,Equalization Redo Disable. Disable autonomous mechanism for requesting to redo the equalization process. The received presets or coefficients mismatch in Recovery.RcvrLock after Recovery EQ phases causes the EQ redo requests. If the EQ redo is.." "0,1" newline bitfld.long 0x74 10. "EQ_EIEOS_CNT,Equalization EIEOS Count Reset Disable. Disable requesting reset of EIEOS count during equalization. Note: When CX_GEN4_SPEED/CX_GEN5_SPEED this register is shared for Gen3 and Gen4/Gen5 data rate. Note: This register field is sticky." "0,1" newline bitfld.long 0x74 9. "EQ_PHASE_2_3,Equalization Phase 2 and Phase 3 Disable. This applies to downstream ports only. Note: When CX_GEN4_SPEED/CX_GEN5_SPEED this register is shadow register for Gen3 and Gen4/Gen5 data rate. If RATE_SHADOW_SEL==00b this register is for Gen3.." "0,1" newline bitfld.long 0x74 8. "DISABLE_SCRAMBLER_GEN_3,Disable Scrambler for Gen3 and Gen4 Data Rate. The Gen3 and Gen4 scrambler/descrambler within the controller needs to be disabled when the scrambling function is implemented outside of the controller (for example within the PHY)." "0,1" newline hexmask.long.byte 0x74 1.--7. 1. "RSVDP_1,Reserved for future use." newline bitfld.long 0x74 0. "GEN3_ZRXDC_NONCOMPL,Gen3 Receiver Impedance ZRX-DC Not Compliant. Receivers that operate at 8.0 GT/s with an impedance other than the range defined by the ZRX-DC parameter for 2.5 GT/s (40-60 Ohms) must meet additional behavior requirements in the.." "The receiver complies with the ZRX-DC parameter..,The receiver does not comply with the ZRX-DC.." group.long (0x1A8+0x700)++0x7 line.long 0x0 "GEN3_EQ_CONTROL_OFF,Gen3 EQ Control Register. This register controls equalization for Phase2 in an upstream port (USP). or Phase3 in a downstream port (DSP). M-PCIe doesn't have Conventional PCIe Gen3 feature. The registers of this section do not exist." hexmask.long.byte 0x0 27.--31. 1. "RSVDP_27,Reserved for future use." newline bitfld.long 0x0 26. "GEN3_REQ_SEND_CONSEC_EIEOS_FOR_PSET_MAP,Request controller to send back-to-back EIEOS in Recovery.RcvrLock state until presets to coefficients mapping is complete. - 0: Do not request - 1: request Note: Gen3 and Gen4 share the same register bit and have.." "Do not request,request" newline bitfld.long 0x0 25. "GEN3_EQ_PSET_REQ_AS_COEF,GEN3_EQ_PSET_REQ_AS_COEF is an internally reserved field. Do not use. Note: This register field is sticky." "0,1" newline bitfld.long 0x0 24. "GEN3_EQ_FOM_INC_INITIAL_EVAL,Include Initial FOM. Include or not the FOM feedback from the initial preset evaluation performed in the EQ Master when finding the highest FOM among all preset evaluations. - 0: Do not include - 1: Include Note: When.." "Do not include,Include" newline hexmask.long.word 0x0 8.--23. 1. "GEN3_EQ_PSET_REQ_VEC,Preset Request Vector. Requesting of Presets during the initial part of the EQ Master Phase. Encoding scheme is as follows: Bit [15:0] =0x0: No preset is requested and evaluated in EQ Master Phase. Bit [i] =1: 'Preset=i' is requested.." newline rbitfld.long 0x0 7. "RSVDP_7,Reserved for future use." "0,1" newline bitfld.long 0x0 6. "GEN3_LOWER_RATE_EQ_REDO_ENABLE,Support EQ redo and lower rate change: - 0: not support - 1: support Note: Gen3 and Gen4 share the same register bit and have the same feature. Note: This register field is sticky." "not support,support" newline bitfld.long 0x0 5. "GEN3_EQ_EVAL_2MS_DISABLE,Phase2_3 2 ms Timeout Disable. Determine behavior in Phase2 for USP (Phase3 if DSP) when the PHY does not respond within 2ms to the assertion of RxEqEval: - 0: abort the current evaluation stop any attempt to modify the remote.." "abort the current evaluation,ignore the 2ms timeout and continue as normal" newline bitfld.long 0x0 4. "GEN3_EQ_PHASE23_EXIT_MODE,Behavior After 24 ms Timeout (when optimal settings are not found). For a USP: Determine next LTSSM state from Phase2 after 24ms Timeout - 0: Recovery.Speed - 1: Recovery.Equalization.Phase3 When optimal settings are not found.." "Equalization Phase 3 Successful status bit is..,Recovery" newline hexmask.long.byte 0x0 0.--3. 1. "GEN3_EQ_FB_MODE,Feedback Mode. - 0000b: Direction Change - 0001b: Figure Of Merit - 0010b: Reserved - .....: Reserved - 1111b: Reserved Note: When CX_GEN4_SPEED/CX_GEN5_SPEED this register is a shadow register for Gen3 and Gen4/Gen5 data rate. If.." line.long 0x4 "GEN3_EQ_FB_MODE_DIR_CHANGE_OFF,Gen3 EQ Direction Change Feedback Mode Control Register. Equalization controls to be used in Phase2 (USP) or Phase 3 (DSP). when you set the Feedback Mode in 'Gen3 EQ Control Register' to 'Direction Change.' These fields.." hexmask.long.word 0x4 18.--31. 1. "RSVDP_18,Reserved for future use." newline hexmask.long.byte 0x4 14.--17. 1. "GEN3_EQ_FMDC_MAX_POST_CUSROR_DELTA,Convergence Window Aperture for C+1. Post-cursor coefficients maximum delta within the convergence window depth. Allowed range: 0 1 2 ..15. Note: When CX_GEN4_SPEED/CX_GEN5_SPEED this register is shadow register for.." newline hexmask.long.byte 0x4 10.--13. 1. "GEN3_EQ_FMDC_MAX_PRE_CUSROR_DELTA,Convergence Window Aperture for C-1. Pre-cursor coefficients maximum delta within the convergence window depth. Allowed range: 0 1 2 ..15. Note: When CX_GEN4_SPEED/CX_GEN5_SPEED this register is shadow register for Gen3.." newline hexmask.long.byte 0x4 5.--9. 1. "GEN3_EQ_FMDC_N_EVALS,Convergence Window Depth. Number of consecutive evaluations considered in Phase 2/3 when determining if optimal coefficients have been found. Allowed range: 0 1 2 ..16 up to a maximum of CX_GEN3_EQ_COEFQ_DEPTH. When set to 0 EQ.." newline hexmask.long.byte 0x4 0.--4. 1. "GEN3_EQ_FMDC_T_MIN_PHASE23,Minimum Time (in ms) To Remain in EQ Master Phase. The LTSSM stays in EQ Master phase for at least this amount of time before starting to check for convergence of the coefficients. Allowed values 0 1 ... 24. Note: When.." group.long (0x1B4+0x700)++0x27 line.long 0x0 "ORDER_RULE_CTRL_OFF,Order Rule Control Register." hexmask.long.word 0x0 16.--31. 1. "RSVDP_16,Reserved for future use." newline hexmask.long.byte 0x0 8.--15. 1. "CPL_PASS_P,Completion Passing Posted Ordering Rule Control. Determines if CPL can pass halted P queue. - 0: CPL can not pass P (recommended) - 1: CPL can pass P" newline hexmask.long.byte 0x0 0.--7. 1. "NP_PASS_P,Non-Posted Passing Posted Ordering Rule Control. Determines if NP can pass halted P queue. - 0 : NP can not pass P (recommended). - 1 : NP can pass P" line.long 0x4 "PIPE_LOOPBACK_CONTROL_OFF,PIPE Loopback Control Register." bitfld.long 0x4 31. "PIPE_LOOPBACK,PIPE Loopback Enable. Indicates RMMI Loopback if M-PCIe. Note: This register field is sticky." "0,1" newline hexmask.long.byte 0x4 27.--30. 1. "RSVDP_27,Reserved for future use." newline bitfld.long 0x4 24.--26. "RXSTATUS_VALUE,RXSTATUS_VALUE is an internally reserved field. Do not use." "0,1,2,3,4,5,6,7" newline rbitfld.long 0x4 22.--23. "RSVDP_22,Reserved for future use." "0,1,2,3" newline hexmask.long.byte 0x4 16.--21. 1. "RXSTATUS_LANE,RXSTATUS_LANE is an internally reserved field. Do not use. Note: This register field is sticky." newline hexmask.long.word 0x4 0.--15. 1. "LPBK_RXVALID,LPBK_RXVALID is an internally reserved field. Do not use. Note: This register field is sticky." line.long 0x8 "MISC_CONTROL_1_OFF,DBI Read-Only Write Enable Register." hexmask.long.word 0x8 22.--31. 1. "RSVDP_22,Reserved for future use." newline bitfld.long 0x8 21. "P2P_ERR_RPT_CTRL,Determines whether to track completion of transmitted Non-Posted TLPs in P2P mode. - 0: Do not track completion - 1: Track completion Note: This register field is sticky." "Do not track completion,Track completion" newline bitfld.long 0x8 20. "P2P_TRACK_CPL_TO_REG,Determines whether to enable Peer to Peer (P2P) error reporting. - 0: Disable P2P error reporting - 1: Enable P2P error reporting Note: This register field is sticky." "Disable P2P error reporting,Enable P2P error reporting" newline bitfld.long 0x8 18.--19. "TARGET_ABOVE_CONFIG_LIMIT_REG,Configuration requests with an address greater than CONFIG_LIMIT_REG are directed to either ELBI or TRGT1 interface based on the setting of this field. This field can have the following values: - 1: ELBI - 2: TRGT1 Note:.." "?,ELBI,TRGT1,?" newline hexmask.long.word 0x8 8.--17. 1. "CONFIG_LIMIT_REG,Configuration requests are directed either to CDM or ELBI/RTRGT1 based on the value of this field. - Configuration requests with an address less CONFIG_LIMIT_REG are directed to the CDM - Configuration requests with an address greater.." newline bitfld.long 0x8 7. "CFG_TLP_BYPASS_EN_REG,Setting of this field defines which field TARGET_ABOVE_CONFIG_LIMIT_REG or CONFIG_LIMIT_REG decides the destination of Configuration requests. This field can have the following values: - 0: Configuration TLPs are routed according to.." "Configuration TLPs are routed according to the..,Configuration TLPs are routed according to the.." newline bitfld.long 0x8 6. "CPLQ_MNG_EN,This field enables the Completion Queue Management feature. Note: This register field is sticky." "0,1" newline bitfld.long 0x8 5. "ARI_DEVICE_NUMBER,When ARI is enabled this field enables use of the device ID. Note: This register field is sticky." "0,1" newline bitfld.long 0x8 4. "DISABLE_AUTO_LTR_CLR_MSG,Disable the autonomous generation of LTR clear message in upstream port. This field can have the following values: - 0: Allow the autonomous generation of LTR clear message. - 1: Disable the autonomous generation of LTR clear.." "Allow the autonomous generation of LTR clear..,Disable the autonomous generation of LTR clear.." newline bitfld.long 0x8 3. "SIMPLIFIED_REPLAY_TIMER,Enables Simplified Replay Timer (Gen4). For more details see 'Transmit Replay' in 'Transmit TLP Processing' section in the 'Controller Operations' chapter of the Databook. Simplified Replay Timer can have the following Values: -.." "0,1" newline bitfld.long 0x8 2. "UR_CA_MASK_4_TRGT1,When this field is set to '1' the controller suppresses error logging error message generation and CPL generation for non-posted requests TLPs (with UR filtering status) forwarded to your application (that is when DEFAULT_TARGET.." "0,1" newline bitfld.long 0x8 1. "DEFAULT_TARGET,Default target for an IO or MEM request with UR/CA/CRS received. Based on the value of this field the controller either drops or forwards these requests to your application. - 0: The controller drops all incoming I/O or MEM requests (after.." "The controller drops all incoming I/O or MEM..,The controller forwards all incoming I/O or MEM.." newline bitfld.long 0x8 0. "DBI_RO_WR_EN,Write to RO Registers Using DBI. Your application can write to some RO and HwInit register fields through the DBI when you set this field to '1'. For more details see 'Writing to Read-Only Registers' in 'Register Module LBC and DBI'.." "0,1" line.long 0xC "MULTI_LANE_CONTROL_OFF,UpConfigure Multi-lane Control Register. Used when upsizing or downsizing the link width through Configuration state without bringing the link down. For more details. see the 'Link Establishment' section in the 'Controller.." hexmask.long.tbyte 0xC 8.--31. 1. "RSVDP_8,Reserved for future use." newline bitfld.long 0xC 7. "UPCONFIGURE_SUPPORT,Upconfigure Support. The controller sends this value as the Link Upconfigure Capability in TS2 Ordered Sets in Configuration.Complete state. This field is reserved (fixed to '0') for M-PCIe. Note: This register field is sticky." "0,1" newline bitfld.long 0xC 6. "DIRECT_LINK_WIDTH_CHANGE,Directed Link Width Change. The controller always moves to Configuration state through Recovery state when this bit is set to '1'. - If the upconfigure_capable variable is '1' and the PCIE_CAP_HW_AUTO_WIDTH_DISABLE bit in.." "0,1" newline hexmask.long.byte 0xC 0.--5. 1. "TARGET_LINK_WIDTH,Target Link Width. Values correspond to: - 6'b000000: Controller does not start upconfigure or autonomous width downsizing in the Configuration state. - 6'b000001: x1 - 6'b000010: x2 - 6'b000100: x4 - 6'b001000: x8 - 6'b010000: x16 -.." line.long 0x10 "PHY_INTEROP_CTRL_OFF,PHY Interoperability Control Register." hexmask.long.tbyte 0x10 12.--31. 1. "RSVDP_12,Reserved for future use." newline bitfld.long 0x10 10. "L1_CLK_SEL,L1 Clock control bit. This field is reserved for internal use. You should not write to this field and change the default unless specifically instructed by Synopsys support. - 1: Controller does not request aux_clk switch and core_clk gating in.." "Controller requests aux_clk switch and core_clk..,Controller does not request aux_clk switch and.." newline rbitfld.long 0x10 9. "L1_NOWAIT_P1,L1 entry control bit. This field is reserved for internal use. You should not write to this field and change the default unless specifically instructed by Synopsys support. - 1: Controller does not wait for PHY to acknowledge transition to.." "Controller waits for the PHY to acknowledge..,Controller does not wait for PHY to acknowledge.." newline bitfld.long 0x10 8. "L1SUB_EXIT_MODE,L1 Exit Control Using phy_mac_pclkack_n. This field is reserved for internal use. You should not write to this field and change the default unless specifically instructed by Synopsys support. - 1: Controller exits L1 without waiting for.." "Controller waits for the PHY to assert..,Controller exits L1 without waiting for the PHY.." newline rbitfld.long 0x10 7. "RSVDP_7,Reserved for future use." "0,1" newline hexmask.long.byte 0x10 0.--6. 1. "RXSTANDBY_CONTROL,Rxstandby Control. Bits 0..5 determine if the controller asserts the RxStandby signal (mac_phy_rxstandby) in the indicated condition. Bit 6 enables the controller to perform the RxStandby/RxStandbyStatus handshake. This field is.." line.long 0x14 "TRGT_CPL_LUT_DELETE_ENTRY_OFF,TRGT_CPL_LUT Delete Entry Control register. Using this register you can delete one entry in the target completion LUT. You should only use this register when you know that your application will never send the completion.." bitfld.long 0x14 31. "DELETE_EN,This is a one-shot bit. A '1' write to this bit triggers the deletion of the target completion LUT entry that is specified in the LOOK_UP_ID field. This is a self-clearing register field. Reading from this register field always returns a '0'." "0,1" newline hexmask.long 0x14 0.--30. 1. "LOOK_UP_ID,This number selects one entry to delete of the TRGT_CPL_LUT." line.long 0x18 "LINK_FLUSH_CONTROL_OFF,Link Reset Request Flush Control Register." hexmask.long.byte 0x18 24.--31. 1. "RSVD_I_8,This is an internally reserved field. Do not use. Note: This register field is sticky." newline hexmask.long.tbyte 0x18 1.--23. 1. "RSVDP_1,Reserved for future use." newline bitfld.long 0x18 0. "AUTO_FLUSH_EN,Enables automatic flushing of pending requests before sending the reset request to the application logic to reset the PCIe controller and the AXI Bridge. The flushing process is initiated if any of the following events occur: - Hot reset.." "0,1" line.long 0x1C "AMBA_ERROR_RESPONSE_DEFAULT_OFF,AXI Bridge Slave Error Response Register." hexmask.long.word 0x1C 16.--31. 1. "RSVDP_16,Reserved for future use." newline hexmask.long.byte 0x1C 10.--15. 1. "AMBA_ERROR_RESPONSE_MAP,AXI Slave Response Error Map. Allows you to selectively map the errors received from the PCIe completion (for non-posted requests) to the AXI slave responses slv_rresp or slv_bresp. The recommended setting is SLVERR. CRS is.." newline hexmask.long.byte 0x1C 5.--9. 1. "RSVDP_5,Reserved for future use." newline bitfld.long 0x1C 3.--4. "AMBA_ERROR_RESPONSE_CRS,CRS Slave Error Response Mapping. Determines the AXI slave response for CRS completions. For more details see 'Error Handling' in the AXI chapter of the Databook. AHB: - always returns OKAY AXI: - 00: OKAY - 01: OKAY with all.." "OKAY,OKAY with all FFFF_FFFF data for all CRS..,?,?" newline bitfld.long 0x1C 2. "AMBA_ERROR_RESPONSE_VENDORID,Vendor ID Non-existent Slave Error Response Mapping. Determines the AXI slave response for errors on reads to non-existent Vendor ID register. For more details see 'Error Handling' in the AXI chapter of the Databook. AHB: -.." "OKAY,SLVERR/DECERR" newline rbitfld.long 0x1C 1. "RSVDP_1,Reserved for future use." "0,1" newline bitfld.long 0x1C 0. "AMBA_ERROR_RESPONSE_GLOBAL,Global Slave Error Response Mapping. Determines the AXI slave response for all error scenarios on non-posted requests. For more details see 'Error Handling' in the AXI chapter of the Databook. AHB: - 0: OKAY (with FFFF data for.." "OKAY,SLVERR/DECERR" line.long 0x20 "AMBA_LINK_TIMEOUT_OFF,Link Down AXI Bridge Slave Timeout Register. If your application AXI master issues outbound requests to the AXI bridge slave interface before the PCIe link is operational. the controller starts a 'flush' timer. The timeout value of.." hexmask.long.tbyte 0x20 9.--31. 1. "RSVDP_9,Reserved for future use." newline bitfld.long 0x20 8. "LINK_TIMEOUT_ENABLE_DEFAULT,Disable Flush. You can disable the flush feature by setting this field to '1'. Note: This register field is sticky." "0,1" newline hexmask.long.byte 0x20 0.--7. 1. "LINK_TIMEOUT_PERIOD_DEFAULT,Timeout Value (ms). The timer will timeout and then flush the bridge TX request queues after this amount of time. The timer counts when there are pending outbound AXI slave interface requests and the PCIe TX link is not.." line.long 0x24 "AMBA_ORDERING_CTRL_OFF,AMBA Ordering Control." hexmask.long.tbyte 0x24 8.--31. 1. "RSVDP_8,Reserved for future use." newline bitfld.long 0x24 7. "AX_MSTR_ZEROLREAD_FW,AXI Master Zero Length Read Forward to the application. The DW PCIe controller AXI bridge is able to terminate in order with the Posted transactions the zero length read implementing the PCIe express flush semantics of the Posted.." "The zero length Read is terminated at the DW..,The zero length Read is forward to the application" newline rbitfld.long 0x24 5.--6. "RSVDP_5,Reserved for future use." "0,1,2,3" newline bitfld.long 0x24 3.--4. "AX_MSTR_ORDR_P_EVENT_SEL,AXI Master Posted Ordering Event Selector. This field selects how the master interface determines when a P write is completed when enforcing the PCIe ordering rule 'NP must not pass P' at the AXI Master Interface. The AXI.." "B'last event: wait for the all of the write..,AW'last event: wait until the complete Posted..,This setting will not affect:,?" newline rbitfld.long 0x24 2. "RSVDP_2,Reserved for future use." "0,1" newline bitfld.long 0x24 1. "AX_SNP_EN,AXI Serialize Non-Posted Requests Enable. This field enables the AXI Bridge to serialize same ID Non-Posted Read/Write Requests on the wire. Serialization implies one outstanding same ID NP Read or Write on the wire and used to avoid AXI RAR.." "0,1" newline rbitfld.long 0x24 0. "RSVDP_0,Reserved for future use." "0,1" group.long (0x1E0+0x700)++0xB line.long 0x0 "COHERENCY_CONTROL_1_OFF,ACE Cache Coherency Control Register 1" hexmask.long 0x0 2.--31. 1. "CFG_MEMTYPE_BOUNDARY_LOW_ADDR,Boundary Lower Address For Memory Type. Bits [31:0] of dword-aligned address of the boundary for Memory type. The two lower address LSBs are '00'. Addresses up to but not including this value are in the lower address space.." newline rbitfld.long 0x0 1. "RSVDP_1,Reserved for future use." "0,1" newline bitfld.long 0x0 0. "CFG_MEMTYPE_VALUE,Sets the memory type for the lower and upper parts of the address space: - 0: lower = Peripheral; upper = Memory - 1: lower = Memory type; upper = Peripheral Note: This register field is sticky." "lower = Peripheral; upper = Memory,lower = Memory type; upper = Peripheral" line.long 0x4 "COHERENCY_CONTROL_2_OFF,ACE Cache Coherency Control Register 2" hexmask.long 0x4 0.--31. 1. "CFG_MEMTYPE_BOUNDARY_HIGH_ADDR,Boundary Upper Address For Memory Type. Bits [63:32] of the 64-bit dword-aligned address of the boundary for Memory type. Note: This register field is sticky." line.long 0x8 "COHERENCY_CONTROL_3_OFF,ACE Cache Coherency Control Register 3" hexmask.long.byte 0x8 27.--30. 1. "CFG_MSTR_AWCACHE_VALUE,Master Write CACHE Signal Value. Value of the individual bits in mstr_awcache when CFG_MSTR_AWCACHE_MODE is '1'. Note: not applicable to message requests; for message requests the value of mstr_awcache is always '0000' Note: This.." newline hexmask.long.byte 0x8 19.--22. 1. "CFG_MSTR_ARCACHE_VALUE,Master Read CACHE Signal Value. Value of the individual bits in mstr_arcache when CFG_MSTR_ARCACHE_MODE is '1'. Note: This register field is sticky." newline hexmask.long.byte 0x8 11.--14. 1. "CFG_MSTR_AWCACHE_MODE,Master Write CACHE Signal Behavior. Defines how the individual bits in mstr_awcache are controlled: - 0: set automatically by the AXI master - 1: set by the value of the corresponding bit of the CFG_MSTR_AWCACHE_VALUE field Note:.." newline hexmask.long.byte 0x8 3.--6. 1. "CFG_MSTR_ARCACHE_MODE,Master Read CACHE Signal Behavior. Defines how the individual bits in mstr_arcache are controlled: - 0: set automatically by the AXI master - 1: set by the value of the corresponding bit of the CFG_MSTR_ARCACHE_VALUE field Note:.." group.long (0x1F0+0x700)++0x7 line.long 0x0 "AXI_MSTR_MSG_ADDR_LOW_OFF,Lower 20 bits of the programmable AXI address where Messages coming from wire are mapped to. Bits [11:0] of the register are tied to zero for the address to be 4k-aligned. In previous releases. the third and fourth DWORDs of a.." hexmask.long.tbyte 0x0 12.--31. 1. "CFG_AXIMSTR_MSG_ADDR_LOW,Lower 20 bits of the programmable AXI address for Messages. Note: This register field is sticky." newline hexmask.long.word 0x0 0.--11. 1. "CFG_AXIMSTR_MSG_ADDR_LOW_RESERVED,Reserved for future use. Note: This register field is sticky." line.long 0x4 "AXI_MSTR_MSG_ADDR_HIGH_OFF,Upper 32 bits of the programmable AXI address where Messages coming from wire are mapped to." hexmask.long 0x4 0.--31. 1. "CFG_AXIMSTR_MSG_ADDR_HIGH,Upper 32 bits of the programmable AXI address for Messages. Note: This register field is sticky." rgroup.long (0x1F8+0x700)++0x7 line.long 0x0 "PCIE_VERSION_NUMBER_OFF,PCIe Controller IIP Release Version Number. The version number is given in hex format. You should convert each pair of hex characters to ASCII to interpret. Using 4.70a (GA) as an example: - VERSION_NUMBER = 0x3437302a which.." hexmask.long 0x0 0.--31. 1. "VERSION_NUMBER,Version Number." line.long 0x4 "PCIE_VERSION_TYPE_OFF,PCIe Controller IIP Release Version Type. The type is given in hex format. You should convert each pair of hex characters to ASCII to interpret. Using 4.70a (GA) as an example: - VERSION_NUMBER = 0x3437302a which translates to 470*.." hexmask.long 0x4 0.--31. 1. "VERSION_TYPE,Version Type." group.long (0x240+0x700)++0x7 line.long 0x0 "MSIX_ADDRESS_MATCH_LOW_OFF,MSI-X Address Match Low Register. When you enable the MSI-X Table RAM feature (MSIX_TABLE_EN=1). the controller implements the logic and RAM required to generate MSI-X requests. For more details. see the Interrupts section in.." hexmask.long 0x0 2.--31. 1. "MSIX_ADDRESS_MATCH_LOW,MSI-X Address Match Low Address. Note: This register field is sticky." newline rbitfld.long 0x0 1. "MSIX_ADDRESS_MATCH_RESERVED_1,Reserved. Note: This register field is sticky." "0,1" newline bitfld.long 0x0 0. "MSIX_ADDRESS_MATCH_EN,MSI-X Match Enable. Enable the MSI-X Address Match feature when the AXI bridge is present. Note: This register field is sticky." "0,1" line.long 0x4 "MSIX_ADDRESS_MATCH_HIGH_OFF,MSI-X Address Match High Register. When you enable the MSI-X Table RAM feature (MSIX_TABLE_EN=1). the controller implements the logic and RAM required to generate MSI-X requests. For more details. see the Interrupts section in.." hexmask.long 0x4 0.--31. 1. "MSIX_ADDRESS_MATCH_HIGH,MSI-X Address Match High Address. Note: This register field is sticky." wgroup.long (0x248+0x700)++0x3 line.long 0x0 "MSIX_DOORBELL_OFF,MSI-X Doorbell Register. When you enable the MSI-X Table RAM feature (MSIX_TABLE_EN=1). the controller implements the logic and RAM required to generate MSI-X requests. For more details. see the Interrupts section in the 'Controller.." bitfld.long 0x0 29.--31. "MSIX_DOORBELL_RESERVED_29_31,Reserved." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x0 24.--28. 1. "MSIX_DOORBELL_PF,MSIX Doorbell Physical Function. This register determines the Physical Function for the MSI-X transaction." newline hexmask.long.byte 0x0 16.--23. 1. "MSIX_DOORBELL_VF,MSIX Doorbell Virtual Function. This register determines the Virtual Function for the MSI-X transaction." newline bitfld.long 0x0 15. "MSIX_DOORBELL_VF_ACTIVE,MSIX Doorbell Virtual Function Active. This register determines whether a Virtual Function is used to generate the MSI-X transaction." "0,1" newline bitfld.long 0x0 12.--14. "MSIX_DOORBELL_TC,MSIX Doorbell Traffic Class. This register determines which traffic class to generate the MSI-X transaction with." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 11. "MSIX_DOORBELL_RESERVED_11,Reserved." "0,1" newline hexmask.long.word 0x0 0.--10. 1. "MSIX_DOORBELL_VECTOR,MSI-X Doorbell Vector. This register determines which vector to generate the MSI-X transaction for." group.long (0x24C+0x700)++0x3 line.long 0x0 "MSIX_RAM_CTRL_OFF,MSI-X RAM power mode and debug control register. When you enable the MSI-X Table RAM feature (MSIX_TABLE_EN=1). the controller implements the logic and RAM required to generate MSI-X requests. For more details. see the Interrupts.." hexmask.long.byte 0x0 26.--31. 1. "MSIX_RAM_CTRL_RESERVED_26_31,Reserved. Note: This register field is sticky." newline bitfld.long 0x0 25. "MSIX_RAM_CTRL_DBG_PBA,MSIX PBA RAM Debug Mode. Use this bit to activate the debug mode and allow direct read/write access to the PBA. Use can also use the dbg_pba input to activate debug mode. Debug mode turns off the PF/VF/Offset-based addressing into.." "0,1" newline bitfld.long 0x0 24. "MSIX_RAM_CTRL_DBG_TABLE,MSIX Table RAM Debug Mode. Use this bit to activate the debug mode and allow direct read/write access to the Table. Use can also use the dbg_table input to activate debug mode. Debug mode turns off the PF/VF/Offset-based.." "0,1" newline hexmask.long.byte 0x0 17.--23. 1. "MSIX_RAM_CTRL_RESERVED_17_23,Reserved. Note: This register field is sticky." newline bitfld.long 0x0 16. "MSIX_RAM_CTRL_BYPASS,MSIX RAM Control Bypass. The bypass field when set disables the internal generation of low power signals for both RAMs. It is up to the application to ensure the RAMs are in the proper power state before trying to access them." "0,1" newline hexmask.long.byte 0x0 10.--15. 1. "MSIX_RAM_CTRL_RESERVED_10_15,Reserved. Note: This register field is sticky." newline bitfld.long 0x0 9. "MSIX_RAM_CTRL_PBA_SD,MSIX PBA RAM Shut Down. Set this bit to drive the cfg_msix_pba_sd output to signal your external logic to place the MSIX PBA RAM in Shut Down low-power mode. Note: This register field is sticky." "0,1" newline bitfld.long 0x0 8. "MSIX_RAM_CTRL_PBA_DS,MSIX PBA RAM Deep Sleep. Set this bit to drive the cfg_msix_pba_ds output to signal your external logic to place the MSIX PBA RAM in Deep Sleep low-power mode. Note: This register field is sticky." "0,1" newline hexmask.long.byte 0x0 2.--7. 1. "MSIX_RAM_CTRL_RESERVED_2_7,Reserved. Note: This register field is sticky." newline bitfld.long 0x0 1. "MSIX_RAM_CTRL_TABLE_SD,MSIX Table RAM Shut Down. Set this bit to drive the cfg_msix_table_sd output to signal your external logic to place the MSIX Table RAM in Shut Down low-power mode. Note: This register field is sticky." "0,1" newline bitfld.long 0x0 0. "MSIX_RAM_CTRL_TABLE_DS,MSIX Table RAM Deep Sleep. Set this bit to drive the cfg_msix_table_ds output to signal your external logic to place the MSIX Table RAM in Deep Sleep low-power mode. Note: This register field is sticky." "0,1" group.long (0x430+0x700)++0x3 line.long 0x0 "PL_LTR_LATENCY_OFF,LTR Latency Register. The function of this register field (and all other fields in this register) differs between an upstream port and a downstream port. For an upstream port. the register fields capture the corresponding fields in the.." bitfld.long 0x0 31. "NO_SNOOP_LATENCY_REQUIRE,No Snoop Latency Requirement. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" "0,1" newline rbitfld.long 0x0 29.--30. "RSVDP_29,Reserved for future use." "0,1,2,3" newline bitfld.long 0x0 26.--28. "NO_SNOOP_LATENCY_SCALE,No Snoop Latency Scale. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" "0,1,2,3,4,5,6,7" newline hexmask.long.word 0x0 16.--25. 1. "NO_SNOOP_LATENCY_VALUE,No Snoop Latency Value. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" newline bitfld.long 0x0 15. "SNOOP_LATENCY_REQUIRE,Snoop Latency Requirement. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" "0,1" newline rbitfld.long 0x0 13.--14. "RSVDP_13,Reserved for future use." "0,1,2,3" newline bitfld.long 0x0 10.--12. "SNOOP_LATENCY_SCALE,Snoop Latency Scale. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" "0,1,2,3,4,5,6,7" newline hexmask.long.word 0x0 0.--9. 1. "SNOOP_LATENCY_VALUE,Snoop Latency Value. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" group.long (0x440+0x700)++0xB line.long 0x0 "AUX_CLK_FREQ_OFF,Auxiliary Clock Frequency Control Register." hexmask.long.tbyte 0x0 10.--31. 1. "RSVDP_10,Reserved for future use." newline hexmask.long.word 0x0 0.--9. 1. "AUX_CLK_FREQ,The aux_clk frequency in MHz. This value is used to provide a 1 us reference for counting time during low-power states with aux_clk when the PHY has removed the pipe_clk. Frequencies lower than 1 MHz are possible but with a loss of accuracy.." line.long 0x4 "L1_SUBSTATES_OFF,L1 Substates Timing Register." hexmask.long.tbyte 0x4 9.--31. 1. "RSVDP_9,Reserved for future use." newline bitfld.long 0x4 8. "L1SUB_LOW_POWER_CLOCK_SWITCH_MODE,If this bit is set to 1'b1 the reference clock will be running regardless of the CLKREQ# setting. If this bit is set to 1'b0 the reference clock may be gated off when CLKREQ# is de-asserted. If the bit is set to 1'b1 the.." "0,1" newline bitfld.long 0x4 6.--7. "L1SUB_T_PCLKACK,Max delay (in 1us units) between a MAC request to remove the clock on mac_phy_pclkreq_n and a PHY response on phy_mac_pclkack_n. If the PHY does not respond within this time the request is aborted.The actual timeout value will be.." "0,1,2,3" newline hexmask.long.byte 0x4 2.--5. 1. "L1SUB_T_L1_2,Duration (in 1us units) of L1.2. The actual timeout value will be L1SUB_T_L1_2 + 1. Range is 0.15. Note: This register field is sticky." newline bitfld.long 0x4 0.--1. "L1SUB_T_POWER_OFF,Duration (in 1us units) of L1.2.Entry. The actual timeout value will be L1SUB_T_POWER_OFF + 1. Range is 0.3. Note: This register field is sticky." "0,1,2,3" line.long 0x8 "POWERDOWN_CTRL_STATUS_OFF,Powerdown Control and Status Register." hexmask.long.tbyte 0x8 12.--31. 1. "RSVDP_12,Reserved for future use." newline hexmask.long.byte 0x8 8.--11. 1. "POWERDOWN_PHY_POWERDOWN,This field represents the Powerdown value that has been acknowledged by the PHY. It is updated with the value of Powerdown driven by the controller when the PHY has returned the Phystatus acknowledgment for the Powerdown.." newline hexmask.long.byte 0x8 4.--7. 1. "POWERDOWN_MAC_POWERDOWN,This field represents the Powerdown value driven by the controller to the PHY." newline rbitfld.long 0x8 1.--3. "RSVDP_1,Reserved for future use." "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 0. "POWERDOWN_FORCE,This field is a one shot field. Writing a value of 1 to this field causes the controller to complete the P2 Powerdown handshake regardless of whether the PHY has returned Phystatus. This field could be used for debug purposes in event.." "0,1" group.long (0x470+0x700)++0x7 line.long 0x0 "PHY_VIEWPORT_CTLSTS_OFF,PHY Register Viewport Control and Status Register." rbitfld.long 0x0 31. "PHY_VIEWPORT_PENDING,PHY viewport pending. Indicates the access is pending. - 1 : Pending - 0 : Idle This bit is set to 1 when the read/write access has been initiated. This bit is cleared when the access is completed. If phy_reg_clk_g is never activated.." "Idle,Pending" newline rbitfld.long 0x0 30. "PHY_VIEWPORT_STATUS,PHY viewport status. Indicates the status of the latest access. - 1 : Timeout - 0 : No errors If the timeout is detected this bit is set to 1 and PHY_VIEWPORT_PENDING is cleared. This bit is cleared when the read/write access is.." "No errors,Timeout" newline hexmask.long.byte 0x0 23.--29. 1. "RSVDP_23,Reserved for future use." newline bitfld.long 0x0 22. "PHY_VIEWPORT_TIMEOUT_DISABLE,PHY viewport timeout disable. Disables the PHY register access timeout structure. When the timeout is disabled you must ensure that the PHY register accesses are always acknowledged by cr_para_ack. Otherwise.." "0,1" newline bitfld.long 0x0 21. "PHY_VIEWPORT_BCWR,Broadcast write access to all xN sub-blocks. If you need to broadcast the write accesses into all lanes both PHY_VIEWPORT_ADDR[15] and this bit should be 1. Note: This register field is sticky." "0,1" newline bitfld.long 0x0 20. "PHY_VIEWPORT_READ,PHY viewport read. If set a read access is initiated. The value is always 0 when this bit is read. Note: This register field is sticky." "0,1" newline hexmask.long.byte 0x0 16.--19. 1. "PHY_VIEWPORT_NUM,PHY viewport xN sub-block number. Selects one of xN sub-blocks. This register is not used when the write access is initiated with PHY_VIEWPORT_BCWR==1. Note: This register field is sticky." newline hexmask.long.word 0x0 0.--15. 1. "PHY_VIEWPORT_ADDR,PHY viewport address. Indicates the PHY's register address. Please refer to the PHY databook for the address map definition. Note: This register field is sticky." line.long 0x4 "PHY_VIEWPORT_DATA_OFF,PHY Register Viewport Data Register." hexmask.long.word 0x4 16.--31. 1. "RSVDP_16,Reserved for future use." newline hexmask.long.word 0x4 0.--15. 1. "PHY_VIEWPORT_DATA,PHY viewport data. A write access to this register initiates the PHY register write access. By a read access to this register this field returns the latest read data from the PHY register. Note: This register field is sticky." group.long (0x490+0x700)++0x3 line.long 0x0 "PIPE_RELATED_OFF,PIPE Related Register. This register controls the pipe's capabitity. control. and status parameters." hexmask.long.tbyte 0x0 9.--31. 1. "RSVDP_9,Reserved for future use." newline bitfld.long 0x0 8. "PIPE_GARBAGE_DATA_MODE,PIPE Garbage Data Mode. - 0: PIPE Spec compliant mode: The MAC discards any symbols received after the electrical idle ordered-set until RxValid is deasserted. - 1: Special PHY Support mode: The MAC discards any symbols received.." "PIPE Spec compliant mode: The MAC discards any..,Special PHY Support mode: The MAC discards any.." tree.end tree.end tree "PCIE1_VF23" base ad:0xF1040000 tree "PF0_TYPE1_HDR (PCI-Compatible Configuration Space Header Type1)" group.long 0x0++0x2F line.long 0x0 "TYPE1_DEV_ID_VEND_ID_REG,Device ID and Vendor ID Register." hexmask.long.word 0x0 16.--31. 1. "DEVICE_ID,Device ID. The Device ID register identifies the particular Function. This identifier is allocated by the vendor. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else.." newline hexmask.long.word 0x0 0.--15. 1. "VENDOR_ID,Vendor ID. The Vendor ID register identifies the manufacturer of the Function. Valid vendor identifiers are allocated by the PCI-SIG to ensure uniqueness. It is not permitted to populate this register with a value of FFFFh which is an invalid.." line.long 0x4 "TYPE1_STATUS_COMMAND_REG,Status and Command Register." bitfld.long 0x4 31. "DETECTED_PARITY_ERROR,Detected Parity Error. This bit is set by a Function whenever it receives a Poisoned TLP regardless of the state the Parity Error Response bit in the Command register. The bit is set when the Poisoned TLP is received by a.." "0,1" newline bitfld.long 0x4 30. "SIGNALED_SYS_ERROR,Signaled System Error. This bit is set when a Function sends an ERR_FATAL or ERR_NONFATAL Message and the SERR# Enable bit in the Command register is 1b." "0,1" newline bitfld.long 0x4 29. "RCVD_MASTER_ABORT,Received Master Abort. This bit is set when a Requester receives a Completion with Unsupported Request Completion status. The bit is set when the Unsupported Request is received by a Function's primary side." "0,1" newline bitfld.long 0x4 28. "RCVD_TARGET_ABORT,Received Target Abort. This bit is set when a Requester receives a Completion with Completer Abort Completion status. The bit is set when the Completer Abort is received by a Function's primary side." "0,1" newline bitfld.long 0x4 27. "SIGNALED_TARGET_ABORT,Signaled Target Abort. This bit is set when a Function completes a Posted or Non-Posted Request as a Completer Abort error. This applies to a Function when the Completer Abort was generated by its primary side." "0,1" newline rbitfld.long 0x4 25.--26. "DEV_SEL_TIMING,DEVSEL Timing. This field was originally described in the PCI Local Bus Specification. Its functionality does not apply to PCI Express. The controller hardwires it to 00b." "0,1,2,3" newline bitfld.long 0x4 24. "MASTER_DPE,Master Data Parity Error. This bit is set by a Function if the Parity Error Response bit in the Command register is 1b and either of the following two conditions occurs: - Port receives a Poisoned Completion going downstream - Port transmits a.." "0,1" newline rbitfld.long 0x4 23. "FAST_B2B_CAP,Fast Back-to-Back Transactions Capable. This bit was originally described in the PCI Local Bus Specification. Its functionality does not apply to PCI Express. The controller hardwires this bit to 0b." "0,1" newline rbitfld.long 0x4 22. "RSVDP_22,Reserved for future use." "0,1" newline rbitfld.long 0x4 21. "FAST_66MHZ_CAP,66 MHz Capable. This bit was originally described in the PCI Local Bus Specification. Its functionality does not apply to PCI Express. The controller hardwires this bit to 0b." "0,1" newline rbitfld.long 0x4 20. "CAP_LIST,Capabilities List. Indicates the presence of an Extended Capability list item. Since all PCI Express device Functions are required to implement the PCI Express Capability structure the controller hardwires this bit to 1b." "0,1" newline rbitfld.long 0x4 19. "INT_STATUS,Interrupt Status. When set indicates that an INTx emulation interrupt is pending internally in the Function. INTx emulation interrupts forwarded by Functions from the secondary side are not reflected in this bit. Setting the Interrupt Disable.." "0,1" newline rbitfld.long 0x4 17.--18. "RSVDP_17,Reserved for future use." "0,1,2,3" newline bitfld.long 0x4 16. "IMM_READINESS,Immediate Readiness. This optional bit when set indicates the Function is guaranteed to be ready to successfully complete valid configuration accesses at any time following any reset that the host is capable of issuing Configuration.." "0,1" newline hexmask.long.byte 0x4 11.--15. 1. "RESERV,Reserved." newline bitfld.long 0x4 10. "INT_EN,Interrupt Disable. Controls the ability of a Function to generate INTx emulation interrupts. When set Functions are prevented from asserting INTx interrupts. Note: - Any INTx emulation interrupts already asserted by the Function must be.." "0,1" newline rbitfld.long 0x4 9. "RSVDP_9,Reserved for future use." "0,1" newline bitfld.long 0x4 8. "SERREN,SERR# Enable. When set this bit enables reporting upstream of Non-fatal and Fatal errors detected by the Function. Note: The errors are reported if enabled either through this bit or through the PCI Express specific bits in the Device Control.." "0,1" newline rbitfld.long 0x4 7. "IDSEL,IDSEL Stepping/Wait Cycle Control. This bit was originally described in the PCI Local Bus Specification. Its functionality does not apply to PCI Express. The controller hardwires this bit to 0b." "0,1" newline bitfld.long 0x4 6. "PERREN,Parity Error Response. This bit controls the logging of poisoned TLPs in the Master Data Parity Error bit in the Status register. For more details see the 'Error Registers' section of the PCI Express Base Specification." "0,1" newline rbitfld.long 0x4 5. "VGAPS,VGA Palette Snoop. This bit was originally described in the PCI Local Bus Specification and the PCI-to-PCI Bridge Architecture Specification. Its functionality does not apply to PCI Express. The controller hardwires this bit to 0b." "0,1" newline rbitfld.long 0x4 4. "MWI_EN,Memory Write and Invalidate. This bit was originally described in the PCI Local Bus Specification and the PCI-to-PCI Bridge Architecture Specification. Its functionality does not apply to PCI Express. The controller hardwires this bit to 0b. For.." "0,1" newline rbitfld.long 0x4 3. "SCO,Special Cycle Enable. This bit was originally described in the PCI Local Bus Specification. Its functionality does not apply to PCI Express. The controller hardwires this bit to 0b." "0,1" newline bitfld.long 0x4 2. "BME,Bus Master Enable. This bit controls forwarding of Memory or I/O requests by a port in the Upstream direction. When this bit is 0b Memory and I/O Requests received at a Root Port must be handled as Unsupported Requests (UR) For Non-Posted Requests a.." "0,1" newline bitfld.long 0x4 1. "MSE,Memory Space Enable. This bit controls a Function's response to Memory Space accesses received on its primary side. - When set the Function is enabled to decode the address and further process Memory Space accesses. - When clear all received Memory.." "0,1" newline bitfld.long 0x4 0. "IO_EN,IO Space Enable. This bit controls a Function's response to I/O Space accesses received on its primary side. - When set the Function is enabled to decode the address and further process I/O Space accesses. - When clear all received I/O accesses.." "0,1" line.long 0x8 "TYPE1_CLASS_CODE_REV_ID_REG,Class Code and Revision ID Register." hexmask.long.byte 0x8 24.--31. 1. "BASE_CLASS_CODE,Base Class Code. A code that broadly classifies the type of operation the Function performs. Encodings for base class are provided in the PCI Code and ID Assignment Specification. All unspecified encodings are reserved. Note: The access.." newline hexmask.long.byte 0x8 16.--23. 1. "SUBCLASS_CODE,Sub-Class Code. Specifies a base class sub-class which identifies more specifically the operation of the Function. Encodings for sub-class are provided in the PCI Code and ID Assignment Specification. All unspecified encodings are.." newline hexmask.long.byte 0x8 8.--15. 1. "PROGRAM_INTERFACE,Programming Interface. This field identifies a specific register level programming interface (if any) so that device independent software can interact with the Function. Encodings for interface are provided in the PCI Code and ID.." newline hexmask.long.byte 0x8 0.--7. 1. "REVISION_ID,Revision ID. The value of this field specifies a Function specific revision identifier. The value is chosen by the vendor. Zero is an acceptable value. The Revision ID should be viewed as a vendor defined extension to the Device ID. Note: The.." line.long 0xC "TYPE1_BIST_HDR_TYPE_LAT_CACHE_LINE_SIZE_REG,BIST. Header Type. Latency Timer. and Cache Line Size Register." hexmask.long.byte 0xC 24.--31. 1. "BIST,BIST. This register is used for control and status of BIST. Functions that do not support BIST must hardwire the register to 00h. A Function whose BIST is invoked must not prevent normal operation of the PCI Express Link. Bit descriptions: - [31]:.." newline rbitfld.long 0xC 23. "MULTI_FUNC,Multi-Function Device. - When set indicates that the device may contain multiple Functions but not necessarily. Software is permitted to probe for Functions other than Function 0. - When clear software must not probe for Functions other.." "0,1" newline hexmask.long.byte 0xC 16.--22. 1. "HEADER_TYPE,Header Layout. This field identifies the layout of the second part of the predefined header. The controller uses 000 0001b encoding. The encoding 000 0010b is reserved. This encoding was originally described in the PC Card Standard Electrical.." newline hexmask.long.byte 0xC 8.--15. 1. "LATENCY_MASTER_TIMER,Latency Timer. This register is also referred to as Primary Latency Timer. The Latency Timer was originally described in the PCI Local Bus Specification and the PCI-to-PCI Bridge Architecture Specification. Its functionality does not.." newline hexmask.long.byte 0xC 0.--7. 1. "CACHE_LINE_SIZE,Cache Line Size. The Cache Line Size register is programmed by the system firmware or the operating system to system cache line size. However legacy conventional PCI software may not always be able to program this register correctly.." line.long 0x10 "BAR0_REG,BAR0 Register. System software must build a consistent address map before booting the machine to an operating system. This means it has to determine how much memory is in the system. and how much address space the Functions in the system.." hexmask.long 0x10 4.--31. 1. "BAR0_START,BAR0 Base Address. - Memory Space: Base Address. - IO Space: bits[31:2] are used to map the function into IO space/Base. Address. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R(Sticky)/W(Sticky) if.." newline bitfld.long 0x10 3. "BAR0_PREFETCH,BAR0 Prefetchable. - Memory Space: Set to one if data is pre-fetchable. A Function is permitted to mark a range as prefetchable. If there are no side effects on reads the function returns all bytes on reads regardless of the byte enables.." "0,1" newline bitfld.long 0x10 1.--2. "BAR0_TYPE,BAR0 Type. - Memory Space: Base Address registers that map into Memory Space can be 32 bits or 64 bits wide (to support mapping into a 64-bit address space). The bit encoding is as follows: -- 00: Base register is 32 bits wide and can be mapped.." "Base register is 32 bits wide and can be mapped..,Reserved,?,?" newline bitfld.long 0x10 0. "BAR0_MEM_IO,BAR0 Memory Space Indicator. This bit is used to determine whether the register maps into Memory or I/O Space. Base Address registers that map to Memory Space must return a 0b. Base Address registers that map to I/O Space must return a 1b." "0,1" line.long 0x14 "BAR1_REG,BAR1 Register. System software must build a consistent address map before booting the machine to an operating system. This means it has to determine how much memory is in the system. and how much address space the Functions in the system.." hexmask.long 0x14 4.--31. 1. "BAR1_START,BAR1 Base Address. - Memory Space: Base Address. - IO Space: bits[31:2] are used to map the function into IO space/Base. Address. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R(Sticky)/W(Sticky) if.." newline bitfld.long 0x14 3. "BAR1_PREFETCH,BAR1 Prefetchable. - Memory Space: Set to one if data is pre-fetchable. A Function is permitted to mark a range as prefetchable. If there are no side effects on reads the function returns all bytes on reads regardless of the byte enables.." "0,1" newline bitfld.long 0x14 1.--2. "BAR1_TYPE,BAR1 Type. - Memory Space: Base Address registers that map into Memory Space can be 32 bits or 64 bits wide (to support mapping into a 64-bit address space). The bit encoding is as follows: -- 00: Base register is 32 bits wide and can be mapped.." "Base register is 32 bits wide and can be mapped..,Reserved,?,?" newline bitfld.long 0x14 0. "BAR1_MEM_IO,BAR1 Memory Space Indicator. This bit is used to determine whether the register maps into Memory or I/O Space. Base Address registers that map to Memory Space must return a 0b. Base Address registers that map to I/O Space must return a 1b." "0,1" line.long 0x18 "SEC_LAT_TIMER_SUB_BUS_SEC_BUS_PRI_BUS_REG,Secondary Latency Timer. Subordinate Bus Number. Secondary Bus Number. and Primary Bus Number Register." hexmask.long.byte 0x18 24.--31. 1. "SEC_LAT_TIMER,Secondary Latency Timer. This register does not apply to PCI Express. The controller hardwires it to 00h." newline hexmask.long.byte 0x18 16.--23. 1. "SUB_BUS,Subordinate Bus Number. The Subordinate Bus Number register is used to record the bus number of the highest numbered PCI bus segment which is behind (or subordinate to) the bridge. Configuration software programs the value in this register. The.." newline hexmask.long.byte 0x18 8.--15. 1. "SEC_BUS,Secondary Bus Number. The Secondary Bus Number register is used to record the bus number of the PCI bus segment to which the secondary interface of the bridge is connected. Configuration software programs the value in this register. The bridge.." newline hexmask.long.byte 0x18 0.--7. 1. "PRIM_BUS,Primary Bus Number. This register is not used by PCI Express Functions. It is implemented for compatibility with legacy software." line.long 0x1C "SEC_STAT_IO_LIMIT_IO_BASE_REG,Secondary Status. and I/O Limit and Base Register. The I/O Limit and I/O Base registers are optional and define an address range that is used by the bridge to determine when to forward I/O transactions from one interface to.." bitfld.long 0x1C 31. "SEC_STAT_DPE,Detected Parity Error. This bit is set by a Function when a Poisoned TLP is received by its secondary side regardless of the state the Parity Error Response Enable bit in the Bridge Control register." "0,1" newline bitfld.long 0x1C 30. "SEC_STAT_RCVD_SYS_ERR,Received System Error. This bit is set when the secondary side of a Function receives an ERR_FATAL or ERR_NONFATAL message." "0,1" newline bitfld.long 0x1C 29. "SEC_STAT_RCVD_MSTR_ABRT,Received Master Abort. This bit is set when the secondary side of a Function (for requests initiated by the Type 1 header Function itself) receives a Completion with Unsupported Request Completion status." "0,1" newline bitfld.long 0x1C 28. "SEC_STAT_RCVD_TRGT_ABRT,Received Target Abort. This bit is set when the secondary side of a Function (for requests initiated by the Type 1 header Function itself) receives a Completion with Completer Abort Completion status." "0,1" newline bitfld.long 0x1C 27. "SEC_STAT_SIG_TRGT_ABRT,Signaled Target Abort. This bit is set when the secondary side of the Function (for Requests completed by the Type 1 header Function itself) completes a Posted or Non-Posted request as a Completer Abort error." "0,1" newline rbitfld.long 0x1C 25.--26. "RSVDP_25,Reserved for future use." "0,1,2,3" newline bitfld.long 0x1C 24. "SEC_STAT_MDPE,Master Data Parity Error. This bit is set by a Function if the Parity Error Response Enable bit in the Bridge Control register is set and either of the following two conditions occurs: - Port receives a Poisoned Completion coming Upstream.." "0,1" newline rbitfld.long 0x1C 23. "RSVDP_23,Reserved for future use." "0,1" newline hexmask.long.byte 0x1C 16.--22. 1. "SEC_STAT_RESERV,Reserved." newline hexmask.long.byte 0x1C 12.--15. 1. "IO_LIMIT,I/O Limit Address. These bits correspond to the address[15:12] of IO address range. For the purpose of address decoding the bridge assumes that the lower 12 address bits address[11:0] of the I/O limit address (not implemented in the I/O Limit.." newline rbitfld.long 0x1C 9.--11. "IO_RESERV1,Reserved." "0,1,2,3,4,5,6,7" newline bitfld.long 0x1C 8. "IO_DECODE_BIT8,I/O Addressing Encode (IO Limit Address). This bit encodes the IO addressing capability of the bridge. IO_DECODE_BIT8 indicates the following: - 0h: The bridge supports only 16-bit I/O addressing (for ISA compatibility). For the purpose of.." "0,1" newline hexmask.long.byte 0x1C 4.--7. 1. "IO_BASE,I/O Base Address. These bits correspond to the address[15:12] of IO address range. For the purpose of address decoding the bridge assumes that the lower 12 address bits address[11:0] of the I/O base address (not implemented in the I/O Base.." newline rbitfld.long 0x1C 1.--3. "IO_RESERV,Reserved." "0,1,2,3,4,5,6,7" newline bitfld.long 0x1C 0. "IO_DECODE,I/O Addressing Encode (IO Base Address) This bit encodes the IO addressing capability of the bridge. IO_DECODE indicates the following: - 0h: The bridge supports only 16-bit I/O addressing (for ISA compatibility). For the purpose of address.." "0,1" line.long 0x20 "MEM_LIMIT_MEM_BASE_REG,Memory Limit and Base Register. The Memory Limit and Memory Base registers define a memory mapped address range which is used by the bridge to determine when to forward memory transactions from one interface to the other. If there.." hexmask.long.word 0x20 20.--31. 1. "MEM_LIMIT,Memory Limit Address. These bits correspond to the upper 12 address bits Address[31:20] of 32-bit addresses. For the purpose of address decoding the bridge assumes that the lower 20 address bits Address[19:0] of the memory limit address.." newline hexmask.long.byte 0x20 16.--19. 1. "MEM_LIMIT_RESERV,Reserved." newline hexmask.long.word 0x20 4.--15. 1. "MEM_BASE,Memory Base Address. These bits correspond to the upper 12 address bits Address[31:20] of 32-bit addresses. For the purpose of address decoding the bridge assumes that the lower 20 address bits Address[19:0] of the memory base address (not.." newline hexmask.long.byte 0x20 0.--3. 1. "MEM_BASE_RESERV,Reserved." line.long 0x24 "PREF_MEM_LIMIT_PREF_MEM_BASE_REG,Prefetchable Memory Limit and Base Register. The Prefetchable Memory Limit and Prefetchable Memory Base registers must indicate that 64-bit addresses are supported. as defined in PCI-to-PCI Bridge Architecture.." hexmask.long.word 0x24 20.--31. 1. "PREF_MEM_LIMIT,Prefetchable Memory Limit Address. If the Prefetchable Memory Limit register indicates support for 32-bit addressing then the Prefetchable Limit Upper 32 Bits register is implemented as a read-only register that returns zero when read. If.." newline rbitfld.long 0x24 17.--19. "PREF_RESERV1,Reserved." "0,1,2,3,4,5,6,7" newline rbitfld.long 0x24 16. "PREF_MEM_LIMIT_DECODE,Prefetchable Memory Limit Decode. This bit encodes whether or not the bridge supports 64-bit addresses. Note: This bit is a copy of the PREF_MEM_DECODE bit and always reflects the current value of that bit. The value of.." "0,1" newline hexmask.long.word 0x24 4.--15. 1. "PREF_MEM_BASE,Prefetchable Memory Base Address. If the Prefetchable Memory Base register indicates support for 32-bit addressing then the Prefetchable Base Upper 32 Bits register is implemented as a read-only register that returns zero when read. If the.." newline rbitfld.long 0x24 1.--3. "PREF_RESERV,Reserved." "0,1,2,3,4,5,6,7" newline bitfld.long 0x24 0. "PREF_MEM_DECODE,Prefetchable Memory Base Decode. This bit encodes whether or not the bridge supports 64-bit addresses. Note: By default the bit is set to 1'b1 indicating that 64-bit addresses are supported. If the bridge only supports 32-bit prefetchable.." "0,1" line.long 0x28 "PREF_BASE_UPPER_REG,Prefetchable Base Upper 32 Bits Register. The Prefetchable Base Upper 32 Bits register is an optional extension to the Prefetchable Memory Base register." hexmask.long 0x28 0.--31. 1. "PREF_MEM_BASE_UPPER,Prefetchable Base Upper 32 Bit. If the Prefetchable Memory Base register indicates support for 32-bit addressing then this register is implemented as read-only register that returns zero when read. If the Prefetchable Memory Base.." line.long 0x2C "PREF_LIMIT_UPPER_REG,Prefetchable Limit Upper 32 Bits Register. The Prefetchable Limit Upper 32 Bits register is an optional extension to the Prefetchable Memory Limit register." hexmask.long 0x2C 0.--31. 1. "PREF_MEM_LIMIT_UPPER,Prefetchable Limit Upper 32 Bit. If the Prefetchable Memory Limit register indicate support for 64-bit addressing then this register is implemented as read/write register which must be initialized by configuration software. This.." rgroup.long 0x30++0x3 line.long 0x0 "IO_LIMIT_UPPER_IO_BASE_UPPER_REG,I/O Limit and Base Upper 16 Bits Register. The I/O Limit Upper 16 Bits and I/O Base Upper 16 Bits registers are optional extensions to the I/O Limit and I/O Base registers." hexmask.long.word 0x0 16.--31. 1. "IO_LIMIT_UPPER,I/O Limit Upper 16 Bits. If the I/O Limit register indicates support for 16-bit I/O address decoding then this register is implemented as a read-only register which return zero when read. If the I/O Limit register indicates support for.." newline hexmask.long.word 0x0 0.--15. 1. "IO_BASE_UPPER,I/O Base Upper 16 Bits. If the I/O Base register indicates support for 16-bit I/O address decoding then this register is implemented as a read-only register which return zero when read. If the I/O base register indicates support for 32-bit.." group.long 0x34++0xB line.long 0x0 "TYPE1_CAP_PTR_REG,Capabilities Pointer Register." hexmask.long.tbyte 0x0 8.--31. 1. "RSVDP_8,Reserved for future use." newline hexmask.long.byte 0x0 0.--7. 1. "CAP_POINTER,Capabilities Pointer. This register is used to point to a linked list of capabilities implemented by this Function. Since all PCI Express Functions are required to implement the PCI Express Capability structure this register must point to a.." line.long 0x4 "TYPE1_EXP_ROM_BASE_REG,Expansion ROM Base Address Register. This register is defined to handle the base address and size information for this expansion ROM. The mask for this ROM BAR exists (if implemented) as a shadow register at this address. The.." hexmask.long.tbyte 0x4 11.--31. 1. "EXP_ROM_BASE_ADDRESS,Expansion ROM Base Address. Upper 21 bits of the Expansion ROM base address. The number of bits (out of these 21) that a Function actually implements depends on how much address space the Function requires. The mask for this ROM BAR.." newline hexmask.long.word 0x4 1.--10. 1. "RSVDP_1,Reserved for future use." newline bitfld.long 0x4 0. "ROM_BAR_ENABLE,Expansion ROM Enable. This bit controls whether or not the Function accepts accesses to its expansion ROM. When this bit is 0b the Function's expansion ROM address space is disabled. When the bit is 1b address decoding is enabled using.." "0,1" line.long 0x8 "BRIDGE_CTRL_INT_PIN_INT_LINE_REG,Bridge Control. Interrupt Pin. and Interrupt Line Register." hexmask.long.word 0x8 23.--31. 1. "BRIDGE_CTRL_RESERV,Reserved." newline bitfld.long 0x8 22. "SBR,Secondary Bus Reset. Setting this bit triggers a hot reset on the corresponding PCI Express Port. Software must ensure a minimum reset duration (Trst) as defined in the PCI Local Bus Specification. Software and systems must honor.." "0,1" newline rbitfld.long 0x8 21. "MSTR_ABORT_MODE,Master Abort Mode. This bit was originally described in the PCI-to-PCI Bridge Architecture Specification. Its functionality does not apply to PCI Express. The controller hardwires this bit to 0b. Note: The access attributes of this field.." "0,1" newline rbitfld.long 0x8 20. "VGA_16B_DEC,VGA 16 bit decode. This bit only has meaning if VGA Enable bit is set. This bit enables system configuration software to select between 10-bit and 16-bit I/O address decoding for all VGA I/O register accesses that are forwarded from primary.." "0,1" newline rbitfld.long 0x8 19. "VGA_EN,VGA Enable. Modifies the response by the bridge to VGA compatible addresses. If the VGA Enable bit is set the bridge will positively decode and forward the following accesses on the primary interface to the secondary interface (and conversely.." "0,1" newline bitfld.long 0x8 18. "ISA_EN,ISA Enable. Modifies the response by the bridge to ISA I/O addresses. This applies only to I/O addresses that are enabled by the I/O Base and I/O Limit registers and are in the first 64 KB of I/O address space (0000 0000h to 0000 FFFFh). If this.." "?,KB block" newline bitfld.long 0x8 17. "SERR_EN,SERR# Enable. This bit controls forwarding of ERR_COR ERR_NONFATAL and ERR_FATAL from secondary to primary." "0,1" newline bitfld.long 0x8 16. "PERE,Parity Error Response Enable. This bit controls the logging of poisoned TLPs in the Master Data Parity Error bit in the Secondary Status register." "0,1" newline hexmask.long.byte 0x8 8.--15. 1. "INT_PIN,Interrupt PIN. The Interrupt Pin register register that identifies the legacy interrupt Message(s) the Function uses. Valid values are: - 01h 02h 03h and 04h: map to legacy interrupt Messages for INTA INTB INTC and INTD respectively. - 00h:.." newline hexmask.long.byte 0x8 0.--7. 1. "INT_LINE,Interrupt Line. The Interrupt Line register communicates interrupt line routing information. The register must be implemented by any Function that uses an interrupt pin. Values in this register are programmed by system software and are system.." tree.end tree "PF0_SPCIE_CAP (Secondary PCI Express Capability Structure)" group.long (0x0+0x1A0)++0xF line.long 0x0 "SPCIE_CAP_HEADER_REG,SPCIE Capability Header. For a description of this standard PCIe register. see the PCI Express Specification." hexmask.long.word 0x0 20.--31. 1. "NEXT_OFFSET,Next Capability Offset. For a description of this standard PCIe register field see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky).." hexmask.long.byte 0x0 16.--19. 1. "CAP_VERSION,Capability Version. For a description of this standard PCIe register field see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else.." hexmask.long.word 0x0 0.--15. 1. "EXTENDED_CAP_ID,Secondary PCI Express Extended Capability ID. For a description of this standard PCIe register field see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN.." line.long 0x4 "LINK_CONTROL3_REG,Link Control 3 Register. For a description of this standard PCIe register. see the PCI Express Specification." hexmask.long 0x4 2.--31. 1. "RSVDP_2,Reserved for future use." bitfld.long 0x4 1. "EQ_REQ_INT_EN,Link Equalization Request Interrupt Enable. For a description of this standard PCIe register field see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" "0,1" bitfld.long 0x4 0. "PERFORM_EQ,Perform Equalization. For a description of this standard PCIe register field see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" "0,1" line.long 0x8 "LANE_ERR_STATUS_REG,Lane Error Status Register. For a description of this standard PCIe register. see the PCI Express Specification." hexmask.long 0x8 2.--31. 1. "RSVDP_LANE_ERR_STATUS,Reserved for future use." bitfld.long 0x8 0.--1. "LANE_ERR_STATUS,Lane Error Status Bits per Lane. For a description of this standard PCIe register field see the PCI Express Specification." "0,1,2,3" line.long 0xC "SPCIE_CAP_OFF_0CH_REG,Lane Equalization Control Register for lanes 1 and 0. For a description of this standard PCIe register. see the PCI Express Specification." rbitfld.long 0xC 31. "RSVDP_31,Reserved for future use." "0,1" bitfld.long 0xC 28.--30. "USP_RX_PRESET_HINT1,Upstream Port 8.0 GT/s Receiver Preset Hint 1. The write value is gated with the PCIE_CAP_CROSS_LINK_SUPPORT field of LINK_CAPABILITIES2_REG. For a description of this standard PCIe register field see the PCI Express Specification." "0,1,2,3,4,5,6,7" hexmask.long.byte 0xC 24.--27. 1. "USP_TX_PRESET1,Upstream Port 8.0 GT/s Transmitter Preset 1. The write value is gated with the PCIE_CAP_CROSS_LINK_SUPPORT field of LINK_CAPABILITIES2_REG. For a description of this standard PCIe register field see the PCI Express Specification. Note:.." rbitfld.long 0xC 23. "RSVDP_23,Reserved for future use." "0,1" newline bitfld.long 0xC 20.--22. "DSP_RX_PRESET_HINT1,Downstream Port 8.0 GT/s Receiver Preset Hint 1. For a description of this standard PCIe register field see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if.." "0,1,2,3,4,5,6,7" hexmask.long.byte 0xC 16.--19. 1. "DSP_TX_PRESET1,Downstream Port 8.0 GT/s Transmitter Preset 1. For a description of this standard PCIe register field see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN.." rbitfld.long 0xC 15. "RSVDP_15,Reserved for future use." "0,1" bitfld.long 0xC 12.--14. "USP_RX_PRESET_HINT0,Upstream Port 8.0 GT/s Receiver Preset Hint 0. The write value is gated with the PCIE_CAP_CROSS_LINK_SUPPORT field of LINK_CAPABILITIES2_REG. For a description of this standard PCIe register field see the PCI Express Specification." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0xC 8.--11. 1. "USP_TX_PRESET0,Upstream Port 8.0 GT/s Transmitter Preset 0. The write value is gated with the PCIE_CAP_CROSS_LINK_SUPPORT field of LINK_CAPABILITIES2_REG. For a description of this standard PCIe register field see the PCI Express Specification. Note:.." rbitfld.long 0xC 7. "RSVDP_7,Reserved for future use." "0,1" bitfld.long 0xC 4.--6. "DSP_RX_PRESET_HINT0,Downstream Port 8.0 GT/s Receiver Preset Hint 0. For a description of this standard PCIe register field see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if.." "0,1,2,3,4,5,6,7" hexmask.long.byte 0xC 0.--3. 1. "DSP_TX_PRESET0,Downstream Port 8.0 GT/s Transmitter Preset 0. For a description of this standard PCIe register field see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN.." tree.end tree "PF0_L1SUB_CAP (L1 Substates Capability Structure)" group.long (0x0+0x2E8)++0xF line.long 0x0 "L1SUB_CAP_HEADER_REG,L1 Substates Extended Capability Header. This register provides capbility ID. capability version and next offset value for L1 Substates." hexmask.long.word 0x0 20.--31. 1. "NEXT_OFFSET,Next Capability Offset. This field contains the offset to the next PCI Express Capability structure or 000h if no other items exist in the linked list of Capabilities. For Extended Capabilities implemented in Configuration Space this offset.." hexmask.long.byte 0x0 16.--19. 1. "CAP_VERSION,Capability Version. This field is a PCI-SIG defined version number that indicates the version of the Capability structure present. This field is depends on version of the specification. Note: The access attributes of this field are as.." hexmask.long.word 0x0 0.--15. 1. "EXTENDED_CAP_ID,L1SUB Extended Capability ID. This field is a PCI-SIG defined ID number that indicates the nature and format of the Extended Capability. Extended Capability ID for L1 PM Substates is 001Eh. Note: The access attributes of this field are as.." line.long 0x4 "L1SUB_CAPABILITY_REG,L1 Substates Capability Register. This register provides extended capability of L1 Substates." hexmask.long.byte 0x4 24.--31. 1. "RSVDP_24,Reserved for future use." hexmask.long.byte 0x4 19.--23. 1. "PWR_ON_VALUE_SUPPORT,Port T Power On Value. Along with the Port T_POWER_ON Scale field in the L1 PM Substates Capabilities register sets the time (in us) that this Port requires the port on the opposite side of Link to wait in L1.2.Exit after sampling.." rbitfld.long 0x4 18. "RSVDP_18,Reserved for future use." "0,1" bitfld.long 0x4 16.--17. "PWR_ON_SCALE_SUPPORT,Port T Power On Scale. Specifies the scale used for the Port T_POWER_ON Value field in the L1 PM Substates Capabilities register. Range of values are given below. Required for all Ports for which either the PCI-PM L1.2 Supported bit.." "?,?,?,Reserved" newline hexmask.long.byte 0x4 8.--15. 1. "COMM_MODE_SUPPORT,Port Common Mode Restore Time. Time (in us) required for this Port to re-establish common mode. Required for all Ports for which either the PCI-PM L1.2 Supported bit is Set ASPM L1.2 Supported bit is Set or both are Set otherwise.." rbitfld.long 0x4 5.--7. "RSVDP_5,Reserved for future use." "0,1,2,3,4,5,6,7" bitfld.long 0x4 4. "L1_PMSUB_SUPPORT,L1 PM Substates ECN Supported. When Set this bit indicates that this Port supports L1 PM Substates. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W (sticky)" "0,1" bitfld.long 0x4 3. "L1_1_ASPM_SUPPORT,ASPM L11 Supported. When Set this bit indicates that ASPM L1.1 is supported. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W (sticky)" "0,1" newline bitfld.long 0x4 2. "L1_2_ASPM_SUPPORT,ASPM L12 Supported. When Set this bit indicates that ASPM L1.2 is supported. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W (sticky)" "0,1" bitfld.long 0x4 1. "L1_1_PCIPM_SUPPORT,PCI-PM L11 Supported. When Set this bit indicates that PCI-PM L1.1 is supported and must be Set by all Ports implementing L1 PM Substates. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W (sticky)" "0,1" bitfld.long 0x4 0. "L1_2_PCIPM_SUPPORT,PCI-PM L12 Supported. When Set this bit indicates that PCI-PM L1.2 is supported. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W (sticky)" "0,1" line.long 0x8 "L1SUB_CONTROL1_REG,L1 Substates Control 1 Register. This register provides Controls to extended capability." bitfld.long 0x8 29.--31. "L1_2_TH_SCA,LTR L12 Threshold Scale. This field provides a scale for the value contained within the LTR_L1.2_THRESHOLD_Value.The default value for this field is 000b.Hardware operation is undefined if software writes a Not-Permitted value to this field." "0,1,2,3,4,5,6,7" rbitfld.long 0x8 26.--28. "RSVDP_26,Reserved for future use." "0,1,2,3,4,5,6,7" hexmask.long.word 0x8 16.--25. 1. "L1_2_TH_VAL,LTR L12 Threshold Value. Along with the LTR_L1.2_THRESHOLD_Scale this field indicates the LTR threshold used to determine if entry into L1 results in L1.1 (if enabled) or L1.2 (if enabled). The default value for this field is 00 0000 0000b." hexmask.long.byte 0x8 8.--15. 1. "T_COMMON_MODE,Common Mode Restore Time. Sets value of TCOMMONMODE (in us) which must be used by the Downstream Ports for timing the re-establishment of common mode.This field is of type RsvdP for Upstream Ports. Default value is implementation.." newline hexmask.long.byte 0x8 4.--7. 1. "RSVDP_4,Reserved for future use." bitfld.long 0x8 3. "L1_1_ASPM_EN,ASPM L11 Enable. When Set this bit enables ASPM L1.1.For Ports for which the ASPM L1.1 Supported bit is Clear this bit is permitted to be hardwired to 0.Default value is 0b." "0,1" bitfld.long 0x8 2. "L1_2_ASPM_EN,ASPM L12 Enable. When Set this bit enables ASPM L1.2.For Ports for which the ASPM L1.2 Supported bit is Clear this bit is permitted to be hardwired to 0.Default value is 0b." "0,1" bitfld.long 0x8 1. "L1_1_PCIPM_EN,PCI-PM L11 Enable. When Set this bit enables PCI-PM L1.1. Default value is 0b." "0,1" newline bitfld.long 0x8 0. "L1_2_PCIPM_EN,PCI-PM L12 Enable. When Set this bit enables PCI-PM L1.2.For Ports for which the PCI-PM L1.2 Supported bit is Clear this bit is permitted to be hardwired to 0.Default value is 0b." "0,1" line.long 0xC "L1SUB_CONTROL2_REG,L1 Substates Control 2 Register. This register provides Controls to extended capability." hexmask.long.tbyte 0xC 8.--31. 1. "RSVDP_8,Reserved for future use." hexmask.long.byte 0xC 3.--7. 1. "T_POWER_ON_VALUE,T Power On Value. Along with the T_POWER_ON Scale sets the minimum amount of time (in us) that the Port must wait in L1.2.Exit after sampling CLKREQ# asserted before actively driving the interface.Default value is 00101b. T_POWER_ON is.." rbitfld.long 0xC 2. "RSVDP_2,Reserved for future use." "0,1" bitfld.long 0xC 0.--1. "T_POWER_ON_SCALE,T Power On Scale. Specifies the scale used for T_POWER_ON Value. Range of values are given below. Required for all Ports that support L1.2 otherwise this field is of type RsvdP. This field must only be modified when the ASPM L1.2 Enable.." "?,?,?,Reserved" tree.end tree "PF0_RAS_DES_CAP (RAS D.E.S. Capability Structure (VSEC))" group.long (0x0+0x30C)++0x3 line.long 0x0 "RAS_DES_CAP_HEADER_REG,Vendor-Specific Extended Capability Header. For a description of this standard PCIe register. see the PCI Express Specification." hexmask.long.word 0x0 20.--31. 1. "NEXT_OFFSET,Next Capability Offset. For a description of this standard PCIe register field see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky).." newline hexmask.long.byte 0x0 16.--19. 1. "CAP_VERSION,Capability Version. For a description of this standard PCIe register field see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else.." newline hexmask.long.word 0x0 0.--15. 1. "EXTENDED_CAP_ID,PCI Express Extended Capability ID. For a description of this standard PCIe register field see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then.." rgroup.long (0x4+0x30C)++0x3 line.long 0x0 "VENDOR_SPECIFIC_HEADER_REG,Vendor-Specific Header. For a description of this standard PCIe register. see the PCI Express Specification." hexmask.long.word 0x0 20.--31. 1. "VSEC_LENGTH,VSEC Length. For a description of this standard PCIe register field see the PCI Express Specification." newline hexmask.long.byte 0x0 16.--19. 1. "VSEC_REV,VSEC Rev. For a description of this standard PCIe register field see the PCI Express Specification." newline hexmask.long.word 0x0 0.--15. 1. "VSEC_ID,VSEC ID. For a description of this standard PCIe register field see the PCI Express Specification." group.long (0x8+0x30C)++0x3 line.long 0x0 "EVENT_COUNTER_CONTROL_REG,Event Counter Control. This is a viewport control register. - Setting the EVENT_COUNTER_EVENT_SELECT and EVENT_COUNTER_LANE_SELECT fields in this register determine the Event Counter data returned by the EVENT_COUNTER_DATA_REG.." hexmask.long.byte 0x0 28.--31. 1. "RSVDP_28,Reserved for future use." newline hexmask.long.word 0x0 16.--27. 1. "EVENT_COUNTER_EVENT_SELECT,Event Counter Data Select. This field in conjunction with the EVENT_COUNTER_LANE_SELECT field indexes the Event Counter data returned by the EVENT_COUNTER_DATA_REG register. - 27-24: Group number(4-bit: 0..0x7) - 23-16: Event.." newline hexmask.long.byte 0x0 12.--15. 1. "RSVDP_12,Reserved for future use." newline hexmask.long.byte 0x0 8.--11. 1. "EVENT_COUNTER_LANE_SELECT,Event Counter Lane Select. This field in conjunction with EVENT_COUNTER_EVENT_SELECT indexes the Event Counter data returned by the EVENT_COUNTER_DATA_REG register. - 0x0: Lane0 - 0x1: Lane1 - 0x2: Lane2 - .. - 0xF: Lane15 Note:.." newline rbitfld.long 0x0 7. "EVENT_COUNTER_STATUS,Event Counter Status. This register returns the current value of the Event Counter selected by the following fields: - EVENT_COUNTER_EVENT_SELECT - EVENT_COUNTER_LANE_SELECT Note: This register field is sticky." "0,1" newline rbitfld.long 0x0 5.--6. "RSVDP_5,Reserved for future use." "0,1,2,3" newline bitfld.long 0x0 2.--4. "EVENT_COUNTER_ENABLE,Event Counter Enable. Enables/disables the Event Counter selected by the EVENT_COUNTER_EVENT_SELECT and EVENT_COUNTER_LANE_SELECT fields in this register. By default all event counters are disabled. You can enable/disable a specific.." "no change,per event off,?,?,?,?,?,?" newline bitfld.long 0x0 0.--1. "EVENT_COUNTER_CLEAR,Event Counter Clear. Clears the Event Counter selected by the EVENT_COUNTER_EVENT_SELECT and EVENT_COUNTER_LANE_SELECT fields in this register. You can clear the value of a specific Event Counter by writing the 'per clear' code and.." "no change,per clear,?,?" rgroup.long (0xC+0x30C)++0x3 line.long 0x0 "EVENT_COUNTER_DATA_REG,Event Counter Data. This viewport register returns the data selected by the following fields: - EVENT_COUNTER_EVENT_SELECT in EVENT_COUNTER_CONTROL_REG - EVENT_COUNTER_LANE_SELECT in EVENT_COUNTER_CONTROL_REG For more details. see.." hexmask.long 0x0 0.--31. 1. "EVENT_COUNTER_DATA,Event Counter Data. This register returns the data selected by the following fields: - EVENT_COUNTER_EVENT_SELECT in EVENT_COUNTER_CONTROL_REG - EVENT_COUNTER_LANE_SELECT in EVENT_COUNTER_CONTROL_REG Note: This register field is sticky." group.long (0x10+0x30C)++0x3 line.long 0x0 "TIME_BASED_ANALYSIS_CONTROL_REG,Time-based Analysis Control. Used for controlling the measurement of RX/TX data throughput and time spent in each low-power LTSSM state. For more details. see the RAS DES section in the Core Operations chapter of the.." hexmask.long.byte 0x0 24.--31. 1. "TIME_BASED_REPORT_SELECT,Time-based Report Select. Selects what type of data is measured for the selected duration (TIME_BASED_DURATION_SELECT) and returned in TIME_BASED_ANALYSIS_DATA. Each type of data is measured using one of three types of units: -.." newline hexmask.long.byte 0x0 16.--23. 1. "RSVDP_16,Reserved for future use." newline hexmask.long.byte 0x0 8.--15. 1. "TIME_BASED_DURATION_SELECT,Time-based Duration Select. Selects the duration of time-based analysis. When 'manual control' is selected and TIMER_START is set to '1' this analysis never stops until TIMER_STOP is set to '0'. - 0x0: Manual control - 0x1:.." newline hexmask.long.byte 0x0 1.--7. 1. "RSVDP_1,Reserved for future use." newline bitfld.long 0x0 0. "TIMER_START,Timer Start. - 1: Start/Restart - 0: Stop This bit will be cleared automatically when the measurement is finished. Note: The app_ras_des_tba_ctrl input also sets the contents of this field and controls the measurement start/stop. Note: This.." "Stop,Start/Restart" rgroup.long (0x14+0x30C)++0x7 line.long 0x0 "TIME_BASED_ANALYSIS_DATA_REG,Time-based Analysis Data. Contains the measurement results of RX/TX data throughput and time spent in each low-power LTSSM state. This viewport register returns the data selected by the TIME_BASED_REPORT_SELECT field in.." hexmask.long 0x0 0.--31. 1. "TIME_BASED_ANALYSIS_DATA,Time Based Analysis Data. This register returns the data selected by the TIME_BASED_REPORT_SELECT field in TIME_BASED_ANALYSIS_CONTROL_REG. The results are cleared when next measurement starts. Note: This register field is sticky." line.long 0x4 "TIME_BASED_ANALYSIS_DATA_63_32_REG,Upper 32 bits of Time-based Analysis Data. This viewport register returns the data selected by the TIME_BASED_REPORT_SELECT field in TIME_BASED_ANALYSIS_CONTROL_REG. For more details. see the RAS DES section in the Core.." hexmask.long 0x4 0.--31. 1. "TIME_BASED_ANALYSIS_DATA_63_32,Upper 32 bits of Time Based Analysis Data. Note: This register field is sticky." group.long (0x30+0x30C)++0x5F line.long 0x0 "EINJ_ENABLE_REG,Error Injection Enable. Each type of error insertion is enabled by the corresponding bit in this register. The specific injection controls for each type of error are defined in the following registers: - 0: CRC Error: EINJ0_CRC_REG - 1:.." hexmask.long 0x0 7.--31. 1. "RSVDP_7,Reserved for future use." newline bitfld.long 0x0 6. "ERROR_INJECTION6_ENABLE,Error Injection6 Enable (Specific TLP Error). Enables insertion of errors into the packets that you select. You can set this bit to '1' when you have disabled RAS datapath protection (DP) by setting CX_RASDP = CX_RASDP_RAM_PROT.." "0,1" newline bitfld.long 0x0 5. "ERROR_INJECTION5_ENABLE,Error Injection5 Enable (TLP Duplicate/Nullify Error). Enables insertion of duplicate/nullified TLPs. For more details see the EINJ5_SP_TLP_REG register. Note: This register field is sticky." "0,1" newline bitfld.long 0x0 4. "ERROR_INJECTION4_ENABLE,Error Injection4 Enable (FC Credit Update Error). Enables insertion of errors into UpdateFCs. For more details see the EINJ4_FC_REG register. Note: This register field is sticky." "0,1" newline bitfld.long 0x0 3. "ERROR_INJECTION3_ENABLE,Error Injection3 Enable (Symbol DataK Mask Error or Sync Header Error). Enables DataK masking of special symbols or the breaking of the sync header. For more details see the EINJ3_SYMBOL_REG register. Note: This register field is.." "0,1" newline bitfld.long 0x0 2. "ERROR_INJECTION2_ENABLE,Error Injection2 Enable (DLLP Error). Enables insertion of DLLP errors. For more details see the EINJ2_DLLP_REG register. Note: This register field is sticky." "0,1" newline bitfld.long 0x0 1. "ERROR_INJECTION1_ENABLE,Error Injection1 Enable (Sequence Number Error). Enables insertion of errors into sequence numbers. For more details see the EINJ1_SEQNUM_REG register. Note: This register field is sticky." "0,1" newline bitfld.long 0x0 0. "ERROR_INJECTION0_ENABLE,Error Injection0 Enable (CRC Error). Enables insertion of errors into various CRC. For more details see the EINJ0_CRC_REG register. Note: This register field is sticky." "0,1" line.long 0x4 "EINJ0_CRC_REG,Error Injection Control 0 (CRC Error). Controls the insertion of errors into the CRC. and parity of ordered sets for the selected type of the packets as follows: - LCRC. Bad TLP will be detected at the receiver side; receiver responds with.." hexmask.long.tbyte 0x4 12.--31. 1. "RSVDP_12,Reserved for future use." newline hexmask.long.byte 0x4 8.--11. 1. "EINJ0_CRC_TYPE,Error injection type. Selects the type of CRC error to be inserted. Tx Path - 0000b: New TLP's LCRC error injection - 0001b: 16bCRC error injection of ACK/NAK DLLP - 0010b: 16bCRC error injection of Update-FC DLLP - 0011b: New TLP's ECRC.." newline hexmask.long.byte 0x4 0.--7. 1. "EINJ0_COUNT,Error injection count. Indicates the number of errors. This register is decremented when the errors have been inserted. - If the counter value is 0x01 and error is inserted ERROR_INJECTION0_ENABLE in EINJ_ENABLE_REG returns 0b. - If the.." line.long 0x8 "EINJ1_SEQNUM_REG,Error Injection Control 1 (Sequence Number Error). Controls the sequence number of the specific TLPs and ACK/NAK DLLPs. Data Link Protocol Error will be detected at the Rx side of ACK/NAL DLLPs when one of these conditions is true: -.." rbitfld.long 0x8 29.--31. "RSVDP_29,Reserved for future use." "0,1,2,3,4,5,6,7" newline hexmask.long.word 0x8 16.--28. 1. "EINJ1_BAD_SEQNUM,Bad sequence number. Indicates the value to add/subtract from the naturally-assigned sequence numbers. This value is represented by two's complement. - 0x0FFF: +4095 - .. - 0x0002: +2 - 0x0001: +1 - 0x0000: 0 - 0x1FFF: -1 - 0x1FFE: -2 -.." newline hexmask.long.byte 0x8 9.--15. 1. "RSVDP_9,Reserved for future use." newline bitfld.long 0x8 8. "EINJ1_SEQNUM_TYPE,Sequence number type. Selects the type of sequence number. - 0b: Insertion of New TLP's SEQ# error - 1b: Insertion of ACK/NAK DLLP's SEQ# Error Note: This register field is sticky." "0,1" newline hexmask.long.byte 0x8 0.--7. 1. "EINJ1_COUNT,Error injection count. Indicates the number of errors. This register is decremented as the errors are being inserted. - If the counter value is 0x01 and error is inserted ERROR_INJECTION1_ENABLE in EINJ_ENABLE_REG returns '0'. - If the.." line.long 0xC "EINJ2_DLLP_REG,Error Injection Control 2 (DLLP Error). Controls the transmission of DLLPs and inserts the following errors: - If 'ACK/NAK DLLP's transmission block' is selected. replay timeout error will occur at the transmitter of the TLPs and then Data.." hexmask.long.tbyte 0xC 10.--31. 1. "RSVDP_10,Reserved for future use." newline bitfld.long 0xC 8.--9. "EINJ2_DLLP_TYPE,DLLP Type. Selects the type of DLLP errors to be inserted. - 00b: ACK/NAK DLLP's transmission block - 01b: Update FC DLLP's transmission block - 10b: Always Transmission for NAK DLLP - 11b: Reserved Note: This register field is sticky." "0,1,2,3" newline hexmask.long.byte 0xC 0.--7. 1. "EINJ2_COUNT,Error injection count. Indicates the number of errors. This register is decremented as the errors are being inserted. - If the counter value is 0x01 and the error is inserted ERROR_INJECTION2_ENABLE in EINJ_ENABLE_REG returns '0'. - If the.." line.long 0x10 "EINJ3_SYMBOL_REG,Error Injection Control 3 (Symbol Error). When 8b/10b encoding is used. this register controls error insertion into the special (K code) symbols. - If TS1/TS2/FTS/E-Idle/SKP is selected. it affects whole of the ordered set. It might.." hexmask.long.tbyte 0x10 11.--31. 1. "RSVDP_11,Reserved for future use." newline bitfld.long 0x10 8.--10. "EINJ3_SYMBOL_TYPE,Error Type. 8b/10b encoding - Mask K symbol. It is not supported to insert errors into the first ordered-set after exiting from TxElecIdle when CX_FREQ_STEP_EN has been enabled. - 000b: Reserved - 001b: COM/PAD(TS1 Order set) - 010b:.." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x10 0.--7. 1. "EINJ3_COUNT,Error injection count. Indicates the number of errors. This register is decremented as the errors are being inserted. - If the counter value is 0x01 and error is inserted ERROR_INJECTION3_ENABLE in EINJ_ENABLE_REG returns '0'. - If the.." line.long 0x14 "EINJ4_FC_REG,Error Injection Control 4 (FC Credit Error). Controls error insertion into the credit value in the UpdateFCs. It is possible to insert errors for any of the following types: - Posted TLP Header credit - Non-Posted TLP Header credit -.." rbitfld.long 0x14 29.--31. "RSVDP_29,Reserved for future use." "0,1,2,3,4,5,6,7" newline hexmask.long.word 0x14 16.--28. 1. "EINJ4_BAD_UPDFC_VALUE,Bad update-FC credit value. Indicates the value to add/subtract from the UpdateFC credit. This value is represented by two's complement. - 0x0FFF: +4095 - .. - 0x0002: +2 - 0x0001: +1 - 0x0000: 0 - 0x1FFF: -1 - 0x1FFE: -2 - .. -.." newline rbitfld.long 0x14 15. "RSVDP_15,Reserved for future use." "0,1" newline bitfld.long 0x14 12.--14. "EINJ4_VC_NUMBER,VC Number. Indicates target VC Number. Note: This register field is sticky." "0,1,2,3,4,5,6,7" newline rbitfld.long 0x14 11. "RSVDP_11,Reserved for future use." "0,1" newline bitfld.long 0x14 8.--10. "EINJ4_UPDFC_TYPE,Update-FC type. Selects the credit type. - 000b: Posted TLP Header Credit value control - 001b: Non-Posted TLP Header Credit value control - 010b: Completion TLP Header Credit value control - 011b: Reserved - 100b: Posted TLP Data Credit.." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x14 0.--7. 1. "EINJ4_COUNT,Error injection count. Indicates the number of errors. This register is decremented as the errors are being inserted. - If the counter value is 0x01 and error is inserted ERROR_INJECTION4_ENABLE in EINJ_ENABLE_REG returns '0'. - If the.." line.long 0x18 "EINJ5_SP_TLP_REG,Error Injection Control 5 (Specific TLP Error). Controls the generation of specified TLPs. Correctable errors will occur which will be fixed by the PCIe protocol. - For Duplicate TLP. the controller initiates Data Link Retry by handling.." hexmask.long.tbyte 0x18 9.--31. 1. "RSVDP_9,Reserved for future use." newline bitfld.long 0x18 8. "EINJ5_SPECIFIED_TLP,Specified TLP. Selects the specified TLP to be inserted. - 0: Generates duplicate TLPs by handling ACK DLLP as NAK DLLP. - 1: Generates Nullified TLP (Original TLP will be stored in retry buffer). Note: This register field is sticky." "Generates duplicate TLPs by handling ACK DLLP as..,Generates Nullified TLP" newline hexmask.long.byte 0x18 0.--7. 1. "EINJ5_COUNT,Error injection count. Indicates the number of errors. This register is decremented as the errors are being inserted. - If the counter value is 0x01 and error is inserted ERROR_INJECTION5_ENABLE in EINJ_ENABLE_REG returns '0'. - If the.." line.long 0x1C "EINJ6_COMPARE_POINT_H0_REG,Error Injection Control 6 (Compare Point Header DWORD #0). Program this register for the 1st DWORD of TLP header/prefix. It is necessary to carefully consider the endianness when you program this register. Bits [31:0] =.." hexmask.long 0x1C 0.--31. 1. "EINJ6_COMPARE_POINT_H0,Packet Compare Point: 1st DWORD. Specifies which Tx TLP header DWORD#0 bits to compare with the corresponding bits in the Packet Compare Value registers (EINJ6_COMPARE_VALUE*). When all specified bits (in the Tx TLP header and.." line.long 0x20 "EINJ6_COMPARE_POINT_H1_REG,Error Injection Control 6 (Compare Point Header DWORD #1). Program this register for the 2nd DWORD of TLP header/prefix. It is necessary to carefully consider the endianness when you program this register. Bits [31:0] =.." hexmask.long 0x20 0.--31. 1. "EINJ6_COMPARE_POINT_H1,Packet Compare Point: 2nd DWORD. Specifies which Tx TLP header DWORD#1 bits to compare with the corresponding bits in the Packet Compare Value registers (EINJ6_COMPARE_VALUE*). When all specified bits (in the Tx TLP header and.." line.long 0x24 "EINJ6_COMPARE_POINT_H2_REG,Error Injection Control 6 (Compare Point Header DWORD #2). Program this register for the 3rd DWORD of TLP header/prefix. It is necessary to carefully consider the endianness when you program this register. Bits [31:0] =.." hexmask.long 0x24 0.--31. 1. "EINJ6_COMPARE_POINT_H2,Packet Compare Point: 3rd DWORD. Specifies which Tx TLP header DWORD#2 bits to compare with the corresponding bits in the Packet Compare Value registers (EINJ6_COMPARE_VALUE*). When all specified bits (in the Tx TLP header and.." line.long 0x28 "EINJ6_COMPARE_POINT_H3_REG,Error Injection Control 6 (Compare Point Header DWORD #3). Program this register for the 4th DWORD of TLP header/prefix. It is necessary to carefully consider the endianness when you program this register. Bits [31:0] =.." hexmask.long 0x28 0.--31. 1. "EINJ6_COMPARE_POINT_H3,Packet Compare Point: 4th DWORD. Specifies which Tx TLP header DWORD#3 bits to compare with the corresponding bits in the Packet Compare Value registers (EINJ6_COMPARE_VALUE*). When all specified bits (in the Tx TLP header and.." line.long 0x2C "EINJ6_COMPARE_VALUE_H0_REG,Error Injection Control 6 (Compare Value Header DWORD #0). Program this register for the 1st DWORD of TLP header/prefix. It is necessary to carefully consider the endianness when you program this register. Bits [31:0] =.." hexmask.long 0x2C 0.--31. 1. "EINJ6_COMPARE_VALUE_H0,Packet Compare Value: 1st DWORD. Specifies the value to compare against Tx the TLP header DWORD#0 bits specified in the Packet Compare Point registers (EINJ6_COMPARE_POINT*). Note: This register field is sticky." line.long 0x30 "EINJ6_COMPARE_VALUE_H1_REG,Error Injection Control 6 (Compare Value Header DWORD #1). Program this register for the 2nd DWORD of TLP header/prefix. It is necessary to carefully consider the endianness when you program this register. Bits [31:0] =.." hexmask.long 0x30 0.--31. 1. "EINJ6_COMPARE_VALUE_H1,Packet Compare Value: 2nd DWORD. Specifies the value to compare against Tx the TLP header DWORD#1 bits specified in the Packet Compare Point registers (EINJ6_COMPARE_POINT*). Note: This register field is sticky." line.long 0x34 "EINJ6_COMPARE_VALUE_H2_REG,Error Injection Control 6 (Compare Value Header DWORD #2). Program this register for the 3rd DWORD of TLP header/prefix. It is necessary to carefully consider the endianness when you program this register. Bits [31:0] =.." hexmask.long 0x34 0.--31. 1. "EINJ6_COMPARE_VALUE_H2,Packet Compare Value: 3rd DWORD. Specifies the value to compare against Tx the TLP header DWORD#2 bits specified in the Packet Compare Point registers (EINJ6_COMPARE_POINT*). Note: This register field is sticky." line.long 0x38 "EINJ6_COMPARE_VALUE_H3_REG,Error Injection Control 6 (Compare Value Header DWORD #3). Program this register for the 4th DWORD of TLP header/prefix. It is necessary to carefully consider the endianness when you program this register. Bits [31:0] =.." hexmask.long 0x38 0.--31. 1. "EINJ6_COMPARE_VALUE_H3,Packet Compare Value: 4th DWORD. Specifies the value to compare against Tx the TLP header DWORD#3 bits specified in the Packet Compare Point registers (EINJ6_COMPARE_POINT*). Note: This register field is sticky." line.long 0x3C "EINJ6_CHANGE_POINT_H0_REG,Error Injection Control 6 (Change Point Header DWORD #0). Program this register for the 1st DWORD of TLP header/prefix. It is necessary to carefully consider the endianness when you program this register. Bits [31:0] =.." hexmask.long 0x3C 0.--31. 1. "EINJ6_CHANGE_POINT_H0,Packet Change Point: 1st DWORD. Specifies which Tx TLP header DWORD#0 bits to replace with the corresponding bits in the Packet Change Value registers (EINJ6_CHANGE_VALUE*). Note: This register field is sticky." line.long 0x40 "EINJ6_CHANGE_POINT_H1_REG,Error Injection Control 6 (Change Point Header DWORD #1). Program this register for the 2nd DWORD of TLP header/prefix. It is necessary to carefully consider the endianness when you program this register. Bits [31:0] =.." hexmask.long 0x40 0.--31. 1. "EINJ6_CHANGE_POINT_H1,Packet Change Point: 2nd DWORD. Specifies which Tx TLP header DWORD#1 bits to replace with the corresponding bits in the Packet Change Value registers (EINJ6_CHANGE_VALUE*). Note: This register field is sticky." line.long 0x44 "EINJ6_CHANGE_POINT_H2_REG,Error Injection Control 6 (Change Point Header DWORD #2). Program this register for the 3rd DWORD of TLP header/prefix. It is necessary to carefully consider the endianness when you program this register. Bits [31:0] =.." hexmask.long 0x44 0.--31. 1. "EINJ6_CHANGE_POINT_H2,Packet Change Point: 3rd DWORD. Specifies which Tx TLP header DWORD#2 bits to replace with the corresponding bits in the Packet Change Value registers (EINJ6_CHANGE_VALUE*). Note: This register field is sticky." line.long 0x48 "EINJ6_CHANGE_POINT_H3_REG,Error Injection Control 6 (Change Point Header DWORD #3). Program this register for the 4th DWORD of TLP header/prefix. It is necessary to carefully consider the endianness when you program this register. Bits [31:0] =.." hexmask.long 0x48 0.--31. 1. "EINJ6_CHANGE_POINT_H3,Packet Change Point: 4th DWORD. Specifies which Tx TLP header DWORD#3 bits to replace with the corresponding bits in the Packet Change Value registers (EINJ6_CHANGE_VALUE*). Note: This register field is sticky." line.long 0x4C "EINJ6_CHANGE_VALUE_H0_REG,Error Injection Control 6 (Change Value Header DWORD #0). Program this register for the 1st DWORD of TLP header/prefix. It is necessary to carefully consider the endianness when you program this register. Bits [31:0] =.." hexmask.long 0x4C 0.--31. 1. "EINJ6_CHANGE_VALUE_H0,Packet Change Value: 1st DWORD. Specifies replacement values for the Tx TLP header DWORD#0 bits defined in the Packet Change Point registers (EINJ6_CHANGE_POINT*). Only applies when the EINJ6_INVERTED_CONTROL field in EINJ6_TLP_REG.." line.long 0x50 "EINJ6_CHANGE_VALUE_H1_REG,Error Injection Control 6 (Change Value Header DWORD #1). Program this register for the 2nd DWORD of TLP header/prefix. It is necessary to carefully consider the endianness when you program this register. Bits [31:0] =.." hexmask.long 0x50 0.--31. 1. "EINJ6_CHANGE_VALUE_H1,Packet Change Value: 2nd DWORD. Specifies replacement values for the Tx TLP header DWORD#1 bits defined in the Packet Change Point registers (EINJ6_CHANGE_POINT*). Only applies when the EINJ6_INVERTED_CONTROL field in EINJ6_TLP_REG.." line.long 0x54 "EINJ6_CHANGE_VALUE_H2_REG,Error Injection Control 6 (Change Value Header DWORD #2). Program this register for the 3rd DWORD of TLP header/prefix. It is necessary to carefully consider the endianness when you program this register. Bits [31:0] =.." hexmask.long 0x54 0.--31. 1. "EINJ6_CHANGE_VALUE_H2,Packet Change Value: 3rd DWORD. Specifies replacement values for the Tx TLP header DWORD#2 bits defined in the Packet Change Point registers (EINJ6_CHANGE_POINT*). Only applies when the EINJ6_INVERTED_CONTROL field in EINJ6_TLP_REG.." line.long 0x58 "EINJ6_CHANGE_VALUE_H3_REG,Error Injection Control 6 (Change Value Header DWORD #3). Program this register for the 4th DWORD of TLP header/prefix. It is necessary to carefully consider the endianness when you program this register. Bits [31:0] =.." hexmask.long 0x58 0.--31. 1. "EINJ6_CHANGE_VALUE_H3,Packet Change Value: 4th DWORD. Specifies replacement values for the Tx TLP header DWORD#3 bits defined in the Packet Change Point registers (EINJ6_CHANGE_POINT*). Only applies when the EINJ6_INVERTED_CONTROL field in EINJ6_TLP_REG.." line.long 0x5C "EINJ6_TLP_REG,Error Injection Control 6 (Packet Error). The Packet Compare Point registers (EINJ6_COMPARE_POINT*) specify which Tx TLP header bits to compare with the corresponding bits in the Packet Compare Value registers (EINJ6_COMPARE_VALUE*). When.." hexmask.long.tbyte 0x5C 12.--31. 1. "RSVDP_12,Reserved for future use." newline bitfld.long 0x5C 9.--11. "EINJ6_PACKET_TYPE,Packet type. Selects the TLP packets to inject errors into. - 0: TLP Header - 1: TLP Prefix 1st 4-DWORDs - 2: TLP Prefix 2nd -DWORDs - Else: Reserved Note: This register field is sticky." "TLP Header,TLP Prefix 1st 4-DWORDs,TLP Prefix 2nd -DWORDs,?,?,?,?,?" newline bitfld.long 0x5C 8. "EINJ6_INVERTED_CONTROL,Inverted Error Injection Control. - 0: EINJ6_CHANGE_VALUE_H[0/1/2/3] is used to replace bits specified by EINJ6_CHANGE_POINT_H[0/1/2/3]. - 1: EINJ6_CHANGE_VALUE_H[0/1/2/3] is ignored and inverts bits specified by.." "EINJ6_CHANGE_VALUE_H[0/1/2/3] is used to replace..,EINJ6_CHANGE_VALUE_H[0/1/2/3] is ignored and.." newline hexmask.long.byte 0x5C 0.--7. 1. "EINJ6_COUNT,Error Injection Count. Indicates the number of errors to insert. This counter is decremented while errors are been inserted. - If the counter value is 0x01 and error is inserted ERROR_INJECTION6_ENABLE in EINJ_ENABLE_REG returns '0'. - If.." group.long (0xA0+0x30C)++0x7 line.long 0x0 "SD_CONTROL1_REG,Silicon Debug Control 1. For more details. see the RAS DES section in the Core Operations chapter of the Databook." hexmask.long.byte 0x0 24.--31. 1. "RSVDP_24,Reserved for future use." newline bitfld.long 0x0 22.--23. "LOW_POWER_INTERVAL,Low Power Entry Interval Time. Interval Time that the controller starts monitoring RXELECIDLE signal after L0s/L1/L2 entry. You should set the value according to the latency from receiving EIOS to RXELECIDLE assertion at the PHY. -.." "0,1,2,3" newline bitfld.long 0x0 20.--21. "TX_EIOS_NUM,Number of Tx EIOS. This register sets the number of transmit EIOS for L0s/L1 entry and Disable/Loopback/Hot-reset exit. The controller selects the greater value between this register and the value defined by the PCI-SIG specification. 2.5GT/s.." "0,1,2,3" newline rbitfld.long 0x0 17.--19. "RSVDP_17,Reserved for future use." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 16. "FORCE_DETECT_LANE_EN,Force Detect Lane Enable. When this bit is set the controller ignores receiver detection from PHY during LTSSM Detect state and uses FORCE_DETECT_LANE. Note: This register field is sticky." "0,1" newline hexmask.long.word 0x0 0.--15. 1. "FORCE_DETECT_LANE,Force Detect Lane. When the FORCE_DETECT_LANE_EN field is set the controller ignores receiver detection from PHY during LTSSM Detect state and uses this value instead. - 0: Lane0 - 1: Lane1 - 2: Lane2 - .. - 15: Lane15 Note: This.." line.long 0x4 "SD_CONTROL2_REG,Silicon Debug Control 2. For more details. see the RAS DES section in the Core Operations chapter of the Databook." hexmask.long.word 0x4 17.--31. 1. "RSVDP_17,Reserved for future use." newline bitfld.long 0x4 16. "FRAMING_ERR_RECOVERY_DISABLE,Framing Error Recovery Disable. This bit disables a transition to Recovery state when a Framing Error is occurred. Note: This register field is sticky." "0,1" newline hexmask.long.byte 0x4 11.--15. 1. "RSVDP_11,Reserved for future use." newline bitfld.long 0x4 10. "DIRECT_LPBKSLV_TO_EXIT,Direct Loopback Slave To Exit. When this bit is set and the LTSSM is in Loopback Slave Active State the LTSSM transitions to Loopback Slave Exit state. Note: This register field is sticky." "0,1" newline bitfld.long 0x4 9. "DIRECT_POLCOMP_TO_DETECT,Direct Polling.Compliance to Detect. When this bit is set and the LTSSM is in Polling Compliance State the LTSSM transitions to Detect state. Note: This register field is sticky." "0,1" newline bitfld.long 0x4 8. "DIRECT_RECIDLE_TO_CONFIG,Direct Recovery.Idle to Configuration. When this bit is set and the LTSSM is in Recovery Idle State the LTSSM transitions to Configuration state. Note: This register field is sticky." "0,1" newline hexmask.long.byte 0x4 3.--7. 1. "RSVDP_3,Reserved for future use." newline bitfld.long 0x4 2. "NOACK_FORCE_LINKDOWN,Force LinkDown. When this bit is set and the controller detects REPLY_NUM rolling over 4 times the LTSSM transitions to Detect State. Note: This register field is sticky." "0,1" newline bitfld.long 0x4 1. "RECOVERY_REQUEST,Recovery Request. When this bit is set to '1' in L0 or L0s the LTSSM starts transitioning to Recovery State. This request does not cause a speed change or re-equalization." "0,1" newline bitfld.long 0x4 0. "HOLD_LTSSM,Hold and Release LTSSM. For as long as this register is '1' the controller stays in the current LTSSM. Note: This register field is sticky." "0,1" group.long (0xB0+0x30C)++0xB line.long 0x0 "SD_STATUS_L1LANE_REG,Silicon Debug Status(Layer1 Per-lane). This viewport register returns the data selected by the following field: - LANE_SELECT in SD_STATUS_L1LANE_REG For more details. see the RAS DES section in the Core Operations chapter of the.." hexmask.long.byte 0x0 24.--31. 1. "DESKEW_POINTER,Deskew Pointer. Indicates Deskew pointer of internal Deskew buffer of selected lane number(LANE_SELECT). Note: This register field is sticky." newline rbitfld.long 0x0 21.--23. "RSVDP_21,Reserved for future use." "0,1,2,3,4,5,6,7" newline rbitfld.long 0x0 20. "PIPE_TXELECIDLE,PIPE:TxElecIdle. Indicates PIPE TXELECIDLE signal of selected lane number(LANE_SELECT). Note: This register field is sticky." "0,1" newline rbitfld.long 0x0 19. "PIPE_RXELECIDLE,PIPE:RxElecIdle. Indicates PIPE RXELECIDLE signal of selected lane number(LANE_SELECT). Note: This register field is sticky." "0,1" newline rbitfld.long 0x0 18. "PIPE_RXVALID,PIPE:RxValid. Indicates PIPE RXVALID signal of selected lane number(LANE_SELECT). Note: This register field is sticky." "0,1" newline rbitfld.long 0x0 17. "PIPE_DETECT_LANE,PIPE:Detect Lane. Indicates whether PHY indicates receiver detection or not on selected lane number(LANE_SELECT). Note: This register field is sticky." "0,1" newline rbitfld.long 0x0 16. "PIPE_RXPOLARITY,PIPE:RxPolarity. Indicates PIPE RXPOLARITY signal of selected lane number(LANE_SELECT). Note: This register field is sticky." "0,1" newline hexmask.long.word 0x0 4.--15. 1. "RSVDP_4,Reserved for future use." newline hexmask.long.byte 0x0 0.--3. 1. "LANE_SELECT,Lane Select. Lane Select register for Silicon Debug Status Register of Layer1-PerLane. - 0x0: Lane0 - 0x1: Lane1 - 0x2: Lane2 - .. - 0xF: Lane15 Note: This register field is sticky." line.long 0x4 "SD_STATUS_L1LTSSM_REG,Silicon Debug Status(Layer1 LTSSM). For more details. see the RAS DES section in the Core Operations chapter of the Databook." hexmask.long.word 0x4 16.--31. 1. "LTSSM_VARIABLE,LTSSM Variable. Indicates internal LTSSM variables defined in the PCI Express Base Specification. C-PCIe Mode: - 0: directed_speed_change - 1: changed_speed_recovery - 2: successful_speed_negotiation - 3: upconfigure_capable; Set to '1' if.." newline rbitfld.long 0x4 15. "LANE_REVERSAL,Lane Reversal Operation. Receiver detected lane reversal. This field is only valid in the L0 LTSSM state. Note: This register field is sticky." "0,1" newline hexmask.long.byte 0x4 11.--14. 1. "RSVDP_11,Reserved for future use." newline rbitfld.long 0x4 8.--10. "PIPE_POWER_DOWN,PIPE:PowerDown. Indicates PIPE PowerDown signal. Note: This register field is sticky." "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 7. "FRAMING_ERR,Framing Error. Indicates Framing Error detection status." "0,1" newline hexmask.long.byte 0x4 0.--6. 1. "FRAMING_ERR_PTR,First Framing Error Pointer. Identifies the first Framing Error using the following encoding. The field contents are only valid value when FRAMING_ERR =1. Received Unexpected Framing Token - 01h: When non- STP/SDP/IDL Token was received.." line.long 0x8 "SD_STATUS_PM_REG,Silicon Debug Status(PM). For more details. see the RAS DES section in the Core Operations chapter of the Databook." hexmask.long.byte 0x8 24.--31. 1. "RSVDP_24,Reserved for future use." newline hexmask.long.byte 0x8 16.--23. 1. "LATCHED_NFTS,Latched N_FTS. Indicates the value of N_FTS in the received TS Ordered Sets from the Link Partner Note: This register field is sticky." newline rbitfld.long 0x8 13.--15. "L1SUB_STATE,L1Sub State. Indicates internal state machine of L1Sub state. - 0h: S_L1_U : idle state - 1h: S_L1_0 : wait for aux_clk_active - 2h: S_L1_0_WAIT4_ACK : wait for pclkack - 3h: S_L1_0_WAIT4_CLKREQ : wait for clkreq - 4h: S_L1_N_ENTRY : check.." "wait for aux_clk_active,?,?,?,?,?,?,?" newline bitfld.long 0x8 12. "PME_RESEND_FLAG,PME Re-send flag. When the DUT sends a PM_PME message TLP the DUT sets PME_Status bit. If host software does not clear PME_Status bit for 100ms(+50%/-5%) the DUT resends the PM_PME Message. This bit indicates that a PM_PME was resent." "0,1" newline hexmask.long.byte 0x8 8.--11. 1. "INTERNAL_PM_SSTATE,Internal PM State(Slave). Indicates internal state machine of Power Management Slave controller. - 0h: S_IDLE - 1h: S_RESPOND_NAK - 2h: S_BLOCK_TLP - 3h: S_WAIT_LAST_TLP_ACK - 4h: S_WAIT_EIDLE - 5h: S_LINK_ENTR_L1 - 6h: S_L1 - 7h:.." newline rbitfld.long 0x8 5.--7. "RSVDP_5,Reserved for future use." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x8 0.--4. 1. "INTERNAL_PM_MSTATE,Internal PM State(Master). Indicates internal state machine of Power Management Master controller. - 00h: IDLE - 01h: L0 - 02h: L0S - 03h: ENTER_L0S - 04h: L0S_EXIT - 05h: WAIT_PMCSR_CPL_SENT - 08h: L1 - 09h: L1_BLOCK_TLP - 0Ah:.." rgroup.long (0xBC+0x30C)++0x3 line.long 0x0 "SD_STATUS_L2_REG,Silicon Debug Status(Layer2). For more details. see the RAS DES section in the Core Operations chapter of the Databook." hexmask.long.byte 0x0 28.--31. 1. "RSVDP_28,Reserved for future use." newline bitfld.long 0x0 27. "FC_INIT2,FC_INIT2. Indicates the controller is in FC_INIT2(VC0) state. Note: This register field is sticky." "0,1" newline bitfld.long 0x0 26. "FC_INIT1,FC_INIT1. Indicates the controller is in FC_INIT1(VC0) state. Note: This register field is sticky." "0,1" newline bitfld.long 0x0 24.--25. "DLCMSM,DLCMSM. Indicates the current DLCMSM. - 00b: DL_INACTIVE - 01b: DL_FC_INIT - 11b: DL_ACTIVE Note: This register field is sticky." "0,1,2,3" newline hexmask.long.word 0x0 12.--23. 1. "RX_ACK_SEQ_NO,Tx Ack Sequence Number. Indicates ACKD_SEQ which is updated by receiving ACK/NAK DLLP. Note: This register field is sticky." newline hexmask.long.word 0x0 0.--11. 1. "TX_TLP_SEQ_NO,Tx Tlp Sequence Number. Indicates next transmit sequence number for transmit TLP. Note: This register field is sticky." group.long (0xC0+0x30C)++0x7 line.long 0x0 "SD_STATUS_L3FC_REG,Silicon Debug Status(Layer3 FC). The CREDIT_DATA[0/1] fields in this viewport register return the data for the VC and TLP Type selected by the following fields: - CREDIT_SEL_VC - CREDIT_SEL_CREDIT_TYPE - CREDIT_SEL_TLP_TYPE -.." hexmask.long.word 0x0 20.--31. 1. "CREDIT_DATA1,Credit Data1. Current FC credit data selected by the CREDIT_SEL_VC CREDIT_SEL_CREDIT_TYPE CREDIT_SEL_TLP_TYPE and CREDIT_SEL_HD viewport-select fields. - Rx: Credit Allocated Value - Tx: Credit Limit Value. This value is valid when.." newline hexmask.long.word 0x0 8.--19. 1. "CREDIT_DATA0,Credit Data0. Current FC credit data selected by the CREDIT_SEL_VC CREDIT_SEL_CREDIT_TYPE CREDIT_SEL_TLP_TYPE and CREDIT_SEL_HD viewport-select fields. - Rx: Credit Received Value - Tx: Credit Consumed Value Note: This register field is.." newline rbitfld.long 0x0 7. "RSVDP_7,Reserved for future use." "0,1" newline bitfld.long 0x0 6. "CREDIT_SEL_HD,Credit Select(HeaderData). This field in conjunction with the CREDIT_SEL_VC CREDIT_SEL_CREDIT_TYPE and CREDIT_SEL_TLP_TYPE viewport-select fields determines that data that is returned by the CREDIT_DATA0 and CREDIT_DATA1 data fields. -.." "Header Credit,Data Credit" newline bitfld.long 0x0 4.--5. "CREDIT_SEL_TLP_TYPE,Credit Select(TLP Type). This field in conjunction with the CREDIT_SEL_VC CREDIT_SEL_CREDIT_TYPE and CREDIT_SEL_HD viewport-select fields determines that data that is returned by the CREDIT_DATA0 and CREDIT_DATA1 data fields. - 0x0:.." "Posted,Non-Posted,Completion,?" newline bitfld.long 0x0 3. "CREDIT_SEL_CREDIT_TYPE,Credit Select(Credit Type). This field in conjunction with the CREDIT_SEL_VC CREDIT_SEL_TLP_TYPE and CREDIT_SEL_HD viewport-select fields determines that data that is returned by the CREDIT_DATA0 and CREDIT_DATA1 data fields. -.." "Rx,Tx" newline bitfld.long 0x0 0.--2. "CREDIT_SEL_VC,Credit Select(VC). This field in conjunction with the CREDIT_SEL_CREDIT_TYPE CREDIT_SEL_TLP_TYPE and CREDIT_SEL_HD viewport-select fields determines that data that is returned by the CREDIT_DATA0 and CREDIT_DATA1 data fields. - 0x0: VC0 -.." "VC0,VC1,VC2,?,?,?,?,VC7" line.long 0x4 "SD_STATUS_L3_REG,Silicon Debug Status(Layer3). For more details. see the RAS DES section in the Core Operations chapter of the Databook." hexmask.long.tbyte 0x4 8.--31. 1. "RSVDP_8,Reserved for future use." newline bitfld.long 0x4 7. "MFTLP_STATUS,Malformed TLP Status. Indicates malformed TLP has occurred." "0,1" newline hexmask.long.byte 0x4 0.--6. 1. "MFTLP_POINTER,First Malformed TLP Error Pointer. Indicates the element of the received first malformed TLP. This pointer is validated by MFTLP_STATUS. - 01h: AtomicOp address alignment - 02h: AtomicOp operand - 03h: AtomicOp byte enable - 04h: TLP length.." group.long (0xD0+0x30C)++0xB line.long 0x0 "SD_EQ_CONTROL1_REG,Silicon Debug EQ Control 1. This is a viewport control register. Setting the EQ_RATE_SEL and EQ_LANE_SEL fields in this register determine the per-lane Silicon Debug EQ Status data returned by the SD_EQ_STATUS[1/2/3] viewport.." hexmask.long.byte 0x0 24.--31. 1. "FOM_TARGET,FOM Target. Indicates figure of merit target criteria value of EQ Master(DSP in EQ Phase3/USP in EQ Phase2). This field is only valid when GEN3_EQ_FB_MODE is 0001b(Figure Of Merit). Note: This register field is sticky." newline bitfld.long 0x0 23. "FOM_TARGET_ENABLE,FOM Target Enable. Enables the FOM_TARGET fields. Note: This register field is sticky." "0,1" newline hexmask.long.byte 0x0 18.--22. 1. "RSVDP_18,Reserved for future use." newline bitfld.long 0x0 16.--17. "EVAL_INTERVAL_TIME,Eval Interval Time. Indicates interval time of RxEqEval assertion. - 00: 500ns - 01: 1us - 10: 2us - 11: 4us This field is used for EQ Master(DSP in EQ Phase3/USP in EQ Phase2). Note: This register field is sticky." "0,1,2,3" newline hexmask.long.byte 0x0 10.--15. 1. "RSVDP_10,Reserved for future use." newline bitfld.long 0x0 8.--9. "EXT_EQ_TIMEOUT,Extends EQ Phase2/3 Timeout. This field is used when the Ltssm is in Recovery.EQ2/3. When this field is set the value of EQ2/3 timeout is extended. EQ Master(DSP in EQ Phase3/USP in EQ Phase2). - 00: 24ms (default) - 01: 48ms (x2) - 10:.." "0,1,2,3" newline rbitfld.long 0x0 6.--7. "RSVDP_6,Reserved for future use." "0,1,2,3" newline bitfld.long 0x0 4.--5. "EQ_RATE_SEL,EQ Status Rate Select. Setting this field in conjunction with the EQ_LANE_SEL field determines the per-lane Silicon Debug EQ Status data returned by the SD_EQ_CONTROL[2/3] and SD_EQ_STATUS[1/2/3] viewport registers. - 0x0: 8.0GT/s Speed.." "0,1,2,3" newline hexmask.long.byte 0x0 0.--3. 1. "EQ_LANE_SEL,EQ Status Lane Select. Setting this field in conjunction with the EQ_RATE_SEL field determines the per-lane Silicon Debug EQ Status data returned by the SD_EQ_CONTROL[2/3] and SD_EQ_STATUS[1/2/3] viewport registers. - 0x0: Lane0 - 0x1: Lane1.." line.long 0x4 "SD_EQ_CONTROL2_REG,Silicon Debug EQ Control 2. This viewport register returns the value for the rate and lane selected by the EQ_RATE_SEL and EQ_LANE_SEL fields in the SD_EQ_CONTROL1_REG register. For more details. see the RAS DES section in the Core.." rbitfld.long 0x4 31. "RSVDP_31,Reserved for future use." "0,1" newline bitfld.long 0x4 30. "FORCE_LOCAL_TX_PRESET_ENABLE,Force Local Transmitter Preset Enable. Enables the FORCE_LOCAL_TX_PRESET field. If select rate in the EQ_RATE_SEL field is 32.0GT/s Speed this feature is not available. Note: This register field is sticky." "0,1" newline bitfld.long 0x4 29. "FORCE_LOCAL_RX_HINT_ENABLE,Force Local Receiver Preset Hint Enable. Enables the FORCE_LOCAL_RX_HINT field. If select rate in the EQ_RATE_SEL field is other than 8.0GT/s Speed this feature is not available. Note: This register field is sticky." "0,1" newline bitfld.long 0x4 28. "FORCE_LOCAL_TX_COEF_ENABLE,Force Local Transmitter Coefficient Enable. Enables the following fields: - FORCE_LOCAL_TX_PRE_CURSOR - FORCE_LOCAL_TX_CURSOR - FORCE_LOCAL_TX_POST_CURSOR Note: This register field is sticky." "0,1" newline hexmask.long.byte 0x4 24.--27. 1. "FORCE_LOCAL_TX_PRESET,Force Local Transmitter Preset. Indicates initial preset value of USP in EQ Slave(EQ Phase2) instead of receiving EQ TS2. If select rate in the EQ_RATE_SEL field is 32.0GT/s Speed this feature is not available. Note: This register.." newline rbitfld.long 0x4 21.--23. "RSVDP_21,Reserved for future use." "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 18.--20. "FORCE_LOCAL_RX_HINT,Force Local Receiver Preset Hint. Indicates the RxPresetHint value of EQ Slave(DSP in EQ Phase2/USP in EQ Phase3) instead of received or set value. If select rate in the EQ_RATE_SEL field is other than 8.0GT/s Speed this feature is.." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x4 12.--17. 1. "FORCE_LOCAL_TX_POST_CURSOR,Force Local Transmitter Post-Cursor. Indicates the coefficient value of EQ Slave(DSP in EQ Phase2/USP in EQ Phase3) instead of the value instructed from link partner. Note: This register field is sticky." newline hexmask.long.byte 0x4 6.--11. 1. "FORCE_LOCAL_TX_CURSOR,Force Local Transmitter Cursor. Indicates the coefficient value of EQ Slave(DSP in EQ Phase2/USP in EQ Phase3) instead of the value instructed from link partner. Note: This register field is sticky." newline hexmask.long.byte 0x4 0.--5. 1. "FORCE_LOCAL_TX_PRE_CURSOR,Force Local Transmitter Pre-cursor. Indicates the coefficient value of EQ Slave(DSP in EQ Phase2/USP in EQ Phase3) instead of the value instructed from link partner. Note: This register field is sticky." line.long 0x8 "SD_EQ_CONTROL3_REG,Silicon Debug EQ Control 3. This viewport register returns the value for the rate and lane selected by the EQ_RATE_SEL and EQ_LANE_SEL fields in the SD_EQ_CONTROL1_REG register. For more details. see the RAS DES section in the Core.." rbitfld.long 0x8 29.--31. "RSVDP_29,Reserved for future use." "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 28. "FORCE_REMOTE_TX_COEF_ENABLE,Force Remote Transmitter Coefficient Enable. Enables the following fields: - FORCE_REMOTE_TX_PRE_CURSOR - FORCE_REMOTE_TX_CURSOR - FORCE_REMOTE_TX_POST_CURSOR This function can only be used when GEN3_EQ_FB_MODE =.." "0,1" newline hexmask.long.word 0x8 18.--27. 1. "RSVDP_18,Reserved for future use." newline hexmask.long.byte 0x8 12.--17. 1. "FORCE_REMOTE_TX_POST_CURSOR,Force Remote Transmitter Post-Cursor. Indicates the coefficient value of EQ Master(DSP in EQ Phase3/USP in EQ Phase2) instead of the value instructed from local phy in dirchange mode. Note: This register field is sticky." newline hexmask.long.byte 0x8 6.--11. 1. "FORCE_REMOTE_TX_CURSOR,Force Remote Transmitter Cursor. Indicates the coefficient value of EQ Master(DSP in EQ Phase3/USP in EQ Phase2) instead of the value instructed from local phy in dirchange mode. Note: This register field is sticky." newline hexmask.long.byte 0x8 0.--5. 1. "FORCE_REMOTE_TX_PRE_CURSOR,Force Remote Transmitter Pre-Cursor. Indicates the coefficient value of EQ Master(DSP in EQ Phase3/USP in EQ Phase2) instead of the value instructed from local phy in dirchange mode. Note: This register field is sticky." rgroup.long (0xE0+0x30C)++0xB line.long 0x0 "SD_EQ_STATUS1_REG,Silicon Debug EQ Status 1. This viewport register returns the first of three words of Silicon Debug EQ Status data for the rate and lane selected by the EQ_RATE_SEL and EQ_LANE_SEL fields in the SD_EQ_CONTROL1_REG register. The.." hexmask.long.tbyte 0x0 8.--31. 1. "RSVDP_8,Reserved for future use." newline bitfld.long 0x0 7. "EQ_REJECT_EVENT,EQ Reject Event. Indicates that the controller receives two consecutive TS1 OS w/Reject=1b during EQ Master phase(DSP in EQ Phase3/USP in EQ Phase2). This bit is automatically cleared when the controller starts EQ Master phase again." "0,1" newline bitfld.long 0x0 6. "EQ_RULEC_VIOLATION,EQ Rule C Violation. Indicates that coefficients rule C violation is detected in the values provided by PHY using direction change method during EQ Master phase(DSP in EQ Phase3/USP in EQ Phase2). The coefficients rule C correspond to.." "0,1" newline bitfld.long 0x0 5. "EQ_RULEB_VIOLATION,EQ Rule B Violation. Indicates that coefficients rule B violation is detected in the values provided by PHY using direction change method during EQ Master phase(DSP in EQ Phase3/USP in EQ Phase2). The coefficients rules B correspond to.." "0,1" newline bitfld.long 0x0 4. "EQ_RULEA_VIOLATION,EQ Rule A Violation. Indicates that coefficients rule A violation is detected in the values provided by PHY using direction change method during EQ Master phase(DSP in EQ Phase3/USP in EQ Phase2). The coefficients rules A correspond to.." "0,1" newline bitfld.long 0x0 3. "RSVDP_3,Reserved for future use." "0,1" newline bitfld.long 0x0 1.--2. "EQ_CONVERGENCE_INFO,EQ Convergence Info. Indicates equalization convergence information. - 0x0: Equalization is not attempted - 0x1: Equalization finished successfully - 0x2: Equalization finished unsuccessfully - 0x3: Reserved This bit is automatically.." "Equalization is not attempted,Equalization finished successfully,Equalization finished unsuccessfully,Reserved" newline bitfld.long 0x0 0. "EQ_SEQUENCE,EQ Sequence. Indicates that the controller is starting the equalization sequence. Note: This register field is sticky." "0,1" line.long 0x4 "SD_EQ_STATUS2_REG,Silicon Debug EQ Status 2. This viewport register returns the second of three words of Silicon Debug EQ Status data for the rate and lane selected by the EQ_RATE_SEL and EQ_LANE_SEL fields in the SD_EQ_CONTROL1_REG register. Each field.." hexmask.long.byte 0x4 24.--31. 1. "EQ_LOCAL_FOM_VALUE,EQ Local Figure of Merit. Indicates Local maximum Figure of Merit value. Note: This register field is sticky." newline bitfld.long 0x4 21.--23. "RSVDP_21,Reserved for future use." "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 18.--20. "EQ_LOCAL_RX_HINT,EQ Local Receiver Preset Hint. Indicates Local Receiver Preset Hint value. If select rate in the EQ_RATE_SEL field is other than 8.0GT/s Speed this feature is not available. Note: This register field is sticky." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x4 12.--17. 1. "EQ_LOCAL_POST_CURSOR,EQ Local Post-Cursor. Indicates Local post cursor coefficient value. Note: This register field is sticky." newline hexmask.long.byte 0x4 6.--11. 1. "EQ_LOCAL_CURSOR,EQ Local Cursor. Indicates Local cursor coefficient value. Note: This register field is sticky." newline hexmask.long.byte 0x4 0.--5. 1. "EQ_LOCAL_PRE_CURSOR,EQ Local Pre-Cursor. Indicates Local pre cursor coefficient value. Note: This register field is sticky." line.long 0x8 "SD_EQ_STATUS3_REG,Silicon Debug EQ Status 3. This viewport register returns the third of three words of Silicon Debug EQ Status data for the rate and lane selected by the EQ_RATE_SEL and EQ_LANE_SEL fields in the SD_EQ_CONTROL1_REG register. Each field.." bitfld.long 0x8 30.--31. "RSVDP_30,Reserved for future use." "0,1,2,3" newline hexmask.long.byte 0x8 24.--29. 1. "EQ_REMOTE_FS,EQ Remote FS. Indicates Remote FS value. Note: This register field is sticky." newline hexmask.long.byte 0x8 18.--23. 1. "EQ_REMOTE_LF,EQ Remote LF. Indicates Remote LF value. Note: This register field is sticky." newline hexmask.long.byte 0x8 12.--17. 1. "EQ_REMOTE_POST_CURSOR,EQ Remote Post-Cursor. Indicates Remote post cursor coefficient value. Note: This register field is sticky." newline hexmask.long.byte 0x8 6.--11. 1. "EQ_REMOTE_CURSOR,EQ Remote Cursor. Indicates Remote cursor coefficient value. Note: This register field is sticky." newline hexmask.long.byte 0x8 0.--5. 1. "EQ_REMOTE_PRE_CURSOR,EQ Remote Pre-Cursor. Indicates Remote pre cursor coefficient value. Note: This register field is sticky." tree.end tree "PF0_SN_CAP (Device Serial Number Capability Structure)" group.long (0x0+0x170)++0xB line.long 0x0 "SN_BASE,Device Serial Number Extended Capability Header. For a description of this standard PCIe register. see the PCI Express Base Specification." hexmask.long.word 0x0 20.--31. 1. "SN_NEXT_OFFSET,Next Capability Offset. For a description of this standard PCIe register field see the PCI Express Base Specification. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then.." hexmask.long.byte 0x0 16.--19. 1. "SN_CAP_VERSION,Capability Version. For a description of this standard PCIe register field see the PCI Express Base Specification. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky).." hexmask.long.word 0x0 0.--15. 1. "SN_PCIE_EXTENDED_CAP_ID,Serial Number Extended Capability ID. For a description of this standard PCIe register field see the PCI Express Base Specification. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if.." line.long 0x4 "SER_NUM_REG_DW_1,Serial Number 1 Register. For a description of this standard PCIe register. see the PCI Express Base Specification." hexmask.long 0x4 0.--31. 1. "SN_SER_NUM_REG_1_DW,IEEE 64 bit Device Serial Number (DW 1). For a description of this standard PCIe register field see the PCI Express Base Specification. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if.." line.long 0x8 "SER_NUM_REG_DW_2,Serial Number 2 Register. For a description of this standard PCIe register. see the PCI Express Base Specification." hexmask.long 0x8 0.--31. 1. "SN_SER_NUM_REG_2_DW,IEEE 64 bit Device Serial Number (DW 2). For a description of this standard PCIe register field see the PCI Express Base Specification. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if.." tree.end tree "PF0_VSECRAS_CAP (PF RAS Datapath Protection Capability Structure (VSEC))" group.long (0x0+0x480)++0x3 line.long 0x0 "RASDP_EXT_CAP_HDR_OFF,PCIe Extended capability ID. Capability version and Next capability offset. For a description of this standard PCIe register. see the PCI Express Specification." hexmask.long.word 0x0 20.--31. 1. "NEXT_OFFSET,Next Capability Offset. For a description of this standard PCIe register see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else.." newline hexmask.long.byte 0x0 16.--19. 1. "CAP,Capability Version. For a description of this standard PCIe register see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note:.." newline hexmask.long.word 0x0 0.--15. 1. "ID,PCI Express Extended Capability ID. For a description of this standard PCIe register see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else.." rgroup.long (0x4+0x480)++0x3 line.long 0x0 "RASDP_VENDOR_SPECIFIC_HDR_OFF,Vendor Specific Header. For a description of this standard PCIe register. see the PCI Express Specification." hexmask.long.word 0x0 20.--31. 1. "VSEC_LENGTH,VSEC Length. For a description of this standard PCIe register see the PCI Express Specification. Note: This register field is sticky." newline hexmask.long.byte 0x0 16.--19. 1. "VSEC_REV,VSEC Rev. For a description of this standard PCIe register see the PCI Express Specification. Note: This register field is sticky." newline hexmask.long.word 0x0 0.--15. 1. "VSEC_ID,VSEC ID. For a description of this standard PCIe register see the PCI Express Specification. Note: This register field is sticky." group.long (0x8+0x480)++0x7 line.long 0x0 "RASDP_ERROR_PROT_CTRL_OFF,ECC error correction control. Allows you to disable ECC error correction for RAMs and datapath. When the AXI Bridge Module is implemented and the master / slave clocks are asynchronous to the PCIe native controller clock.." hexmask.long.byte 0x0 24.--31. 1. "RSVDP_24,Reserved for future use." newline bitfld.long 0x0 23. "ERROR_PROT_DISABLE_CXS_RX,Error correction disable for CXS Tx path (PCIe Rx path). Note: This register field is sticky." "0,1" newline bitfld.long 0x0 22. "ERROR_PROT_DISABLE_ADM_RX,Error correction disable for ADM Rx path. Note: This register field is sticky." "0,1" newline bitfld.long 0x0 21. "ERROR_PROT_DISABLE_LAYER3_RX,Error correction disable for layer 3 Rx path. Note: This register field is sticky." "0,1" newline bitfld.long 0x0 20. "ERROR_PROT_DISABLE_LAYER2_RX,Error correction disable for layer 2 Rx path. Note: This register field is sticky." "0,1" newline bitfld.long 0x0 19. "ERROR_PROT_DISABLE_DMA_READ,Error correction disable for DMA read engine. Note: This register field is sticky." "0,1" newline bitfld.long 0x0 18. "ERROR_PROT_DISABLE_AXI_BRIDGE_INBOUND_REQUEST,Error correction disable for AXI bridge inbound request path. Note: This register field is sticky." "0,1" newline bitfld.long 0x0 17. "ERROR_PROT_DISABLE_AXI_BRIDGE_INBOUND_COMPLETION,Error correction disable for AXI bridge inbound completion composer. Does not disable the error detection reporting for 1-bit and 2-bit ECC errors. Note: This register field is sticky." "?,bit and 2-bit ECC errors" newline bitfld.long 0x0 16. "ERROR_PROT_DISABLE_RX,Global error correction disable for all Rx layers. Note: This register field is sticky." "0,1" newline hexmask.long.byte 0x0 9.--15. 1. "RSVDP_9,Reserved for future use." newline bitfld.long 0x0 8. "ERROR_PROT_DISABLE_DTIM_TX,Error correction disable for DTIM Tx path. Note: This register field is sticky." "0,1" newline bitfld.long 0x0 7. "ERROR_PROT_DISABLE_CXS_TX,Error correction disable for CXS Rx path (PCIe Tx path). Note: This register field is sticky." "0,1" newline bitfld.long 0x0 6. "ERROR_PROT_DISABLE_ADM_TX,Error correction disable for Adm Tx path. Note: This register field is sticky." "0,1" newline bitfld.long 0x0 5. "ERROR_PROT_DISABLE_LAYER3_TX,Error correction disable for layer 3 Tx path. Note: This register field is sticky." "0,1" newline bitfld.long 0x0 4. "ERROR_PROT_DISABLE_LAYER2_TX,Error correction disable for layer 2 Tx path. Note: This register field is sticky." "0,1" newline bitfld.long 0x0 3. "ERROR_PROT_DISABLE_DMA_WRITE,Error correction disable for DMA write engine. Note: This register field is sticky." "0,1" newline bitfld.long 0x0 2. "ERROR_PROT_DISABLE_AXI_BRIDGE_OUTBOUND,Error correction disable for AXI bridge outbound request path. Note: This register field is sticky." "0,1" newline bitfld.long 0x0 1. "ERROR_PROT_DISABLE_AXI_BRIDGE_MASTER,Error correction disable for AXI bridge master completion buffer. Note: This register field is sticky." "0,1" newline bitfld.long 0x0 0. "ERROR_PROT_DISABLE_TX,Global error correction disable for all Tx layers. Does not disable the error detection reporting for 1-bit and 2-bit ECC errors. Note: This register field is sticky." "?,bit and 2-bit ECC errors" line.long 0x4 "RASDP_CORR_COUNTER_CTRL_OFF,Corrected error (1-bit ECC) counter selection and control. This is a viewport control register. Setting the CORR_COUNTER_SELECTION_REGION and CORR_COUNTER_SELECTION fields in this register determine the counter data returned.." hexmask.long.byte 0x4 24.--31. 1. "CORR_COUNTER_SELECTION,Counter selection. This field selects the counter ID (within the region defined by CORR_COUNTER_SELECTION_REGION) whose contents can be read from the RASDP_CORR_COUNT_REPORT_OFF register. You can cycle this field value from 0 to.." newline hexmask.long.byte 0x4 20.--23. 1. "CORR_COUNTER_SELECTION_REGION,Select correctable counter region: - 0x0: Region select for Adm Rx path - 0x1: Region select for layer 3 Rx path - 0x2: Region select for layer 2 Rx path - 0x3: Region select for DMA inbound path - 0x4: Region select for AXI.." newline hexmask.long.word 0x4 5.--19. 1. "RSVDP_5,Reserved for future use." newline bitfld.long 0x4 4. "CORR_EN_COUNTERS,Enable correctable errors counters. - 1: counters increment when the controller detects a correctable error - 0: counters are frozen The counters are enabled by default." "counters are frozen,counters increment when the controller detects a.." newline rbitfld.long 0x4 1.--3. "RSVDP_1,Reserved for future use." "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 0. "CORR_CLEAR_COUNTERS,Clear all correctable error counters." "0,1" rgroup.long (0x10+0x480)++0x3 line.long 0x0 "RASDP_CORR_COUNT_REPORT_OFF,Corrected error (1-bit ECC) counter data. This viewport register returns the counter data selected by the CORR_COUNTER_SELECTION_REGION and CORR_COUNTER_SELECTION fields in the RASDP_CORR_COUNTER_CTRL_OFF register." hexmask.long.byte 0x0 24.--31. 1. "CORR_COUNTER_SELECTED,Counter selection. Returns the value set in the CORR_COUNTER_SELECTION field of the RASDP_CORR_COUNTER_CTRL_OFF register." newline hexmask.long.byte 0x0 20.--23. 1. "CORR_COUNTER_SELECTED_REGION,Selected correctable counter region: - 0x0: Region select for Adm Rx path - 0x1: Region select for layer 3 Rx path - 0x2: Region select for layer 2 Rx path - 0x3: Region select for DMA inbound path - 0x4: Region select for.." newline hexmask.long.word 0x0 8.--19. 1. "RSVDP_8,Reserved for future use." newline hexmask.long.byte 0x0 0.--7. 1. "CORR_COUNTER,Current corrected error count for the selected counter." group.long (0x14+0x480)++0x3 line.long 0x0 "RASDP_UNCORR_COUNTER_CTRL_OFF,Uncorrected error (2-bit ECC and parity) counter selection and control. This is a viewport control register. Setting the UNCORR_COUNTER_SELECTION_REGION and UNCORR_COUNTER_SELECTION fields in this register determine the.." hexmask.long.byte 0x0 24.--31. 1. "UNCORR_COUNTER_SELECTION,Counter selection. This field selects the counter ID (within the region defined by UNCORR_COUNTER_SELECTION_REGION) whose contents can be read from the RASDP_UNCORR_COUNT_REPORT_OFF register. You can cycle this field value from 0.." newline hexmask.long.byte 0x0 20.--23. 1. "UNCORR_COUNTER_SELECTION_REGION,Select uncorrectable counter region: - 0x0: Region select for Adm Rx path - 0x1: Region select for layer 3 Rx path - 0x2: Region select for layer 2 Rx path - 0x3: Region select for DMA inbound path - 0x4: Region select for.." newline hexmask.long.word 0x0 5.--19. 1. "RSVDP_5,Reserved for future use." newline bitfld.long 0x0 4. "UNCORR_EN_COUNTERS,Enable uncorrectable errors counters. - 1: enables the counters to increment on detected correctable errors - 0: counters are frozen The counters are enabled by default." "counters are frozen,enables the counters to increment on detected.." newline rbitfld.long 0x0 1.--3. "RSVDP_1,Reserved for future use." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 0. "UNCORR_CLEAR_COUNTERS,Clear uncorrectable errors counters. When asserted causes all counters tracking the uncorrectable errors to be cleared." "0,1" rgroup.long (0x18+0x480)++0x3 line.long 0x0 "RASDP_UNCORR_COUNT_REPORT_OFF,Uncorrected error (2-bit ECC and parity) counter data. This viewport register returns the counter data selected by the UNCORR_COUNTER_SELECTION_REGION and UNCORR_COUNTER_SELECTION fields in the RASDP_UNCORR_COUNTER_CTRL_OFF.." hexmask.long.byte 0x0 24.--31. 1. "UNCORR_COUNTER_SELECTED,Counter selection. Returns the value set in the UNCORR_COUNTER_SELECTION field of the RASDP_UNCORR_COUNTER_CTRL_OFF register." newline hexmask.long.byte 0x0 20.--23. 1. "UNCORR_COUNTER_SELECTED_REGION,Selected uncorrectable counter region: - 0x0: Region select for Adm Rx path - 0x1: Region select for layer 3 Rx path - 0x2: Region select for layer 2 Rx path - 0x3: Region select for DMA inbound path - 0x4: Region select.." newline hexmask.long.word 0x0 8.--19. 1. "RSVDP_8,Reserved for future use." newline hexmask.long.byte 0x0 0.--7. 1. "UNCORR_COUNTER,Current uncorrected error count for the selected counter" group.long (0x1C+0x480)++0x3 line.long 0x0 "RASDP_ERROR_INJ_CTRL_OFF,Error injection control for the following features: - 1-bit or 2-bit injection - Continuous or fixed-number (n) injection modes - Global enable/disable - Selectable location where injection occurs" hexmask.long.byte 0x0 24.--31. 1. "RSVDP_24,Reserved for future use." newline hexmask.long.byte 0x0 16.--23. 1. "ERROR_INJ_LOC,Error injection location. Selects where error injection takes place. You can cycle this field value from 0 to 255 to access all locations according to the detailed report of check points at.." newline hexmask.long.byte 0x0 8.--15. 1. "ERROR_INJ_COUNT,Error injection count. - 0: errors are inserted in every TLP until you clear ERROR_INJ_EN. - 1: one errors injected - 2: two errors injected - n: amount of errors injected" newline rbitfld.long 0x0 6.--7. "RSVDP_6,Reserved for future use." "0,1,2,3" newline bitfld.long 0x0 4.--5. "ERROR_INJ_TYPE,Error injection type: - 0: none - 1: 1-bit - 2: 2-bit" "none,bit,bit,?" newline rbitfld.long 0x0 1.--3. "RSVDP_1,Reserved for future use." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 0. "ERROR_INJ_EN,Error injection global enable. When set enables the error insertion logic." "0,1" rgroup.long (0x20+0x480)++0x7 line.long 0x0 "RASDP_CORR_ERROR_LOCATION_OFF,Corrected errors locations. For more details. see the RAS Data Protection (DP) section in the Core Operations chapter of the Databook." hexmask.long.byte 0x0 24.--31. 1. "LOC_LAST_CORR_ERROR,Location/ID of the last corrected error within the region defined by REG_LAST_CORR_ERROR. You can cycle this field value from 0 to 255 to access all counters according to the detailed report of check points at.." newline hexmask.long.byte 0x0 20.--23. 1. "REG_LAST_CORR_ERROR,Region of the last corrected error: - 0x0: Region select for Adm Rx path - 0x1: Region select for layer 3 Rx path - 0x2: Region select for layer 2 Rx path - 0x3: Region select for DMA inbound path - 0x4: Region select for AXI bridge.." newline hexmask.long.byte 0x0 16.--19. 1. "RSVDP_16,Reserved for future use." newline hexmask.long.byte 0x0 8.--15. 1. "LOC_FIRST_CORR_ERROR,Location/ID of the first corrected error within the region defined by REG_FIRST_CORR_ERROR. You can cycle this field value from 0 to 255 to access all counters according to the detailed report of check points at.." newline hexmask.long.byte 0x0 4.--7. 1. "REG_FIRST_CORR_ERROR,Region of the first corrected error: - 0x0: Region select for Adm Rx path - 0x1: Region select for layer 3 Rx path - 0x2: Region select for layer 2 Rx path - 0x3: Region select for DMA inbound path - 0x4: Region select for AXI bridge.." newline hexmask.long.byte 0x0 0.--3. 1. "RSVDP_0,Reserved for future use." line.long 0x4 "RASDP_UNCORR_ERROR_LOCATION_OFF,Uncorrected errors locations. For more details. see the RAS Data Protection (DP) section in the Core Operations chapter of the Databook." hexmask.long.byte 0x4 24.--31. 1. "LOC_LAST_UNCORR_ERROR,Location/ID of the last uncorrected error within the region defined by REG_LAST_UNCORR_ERROR. You can cycle this field value from 0 to 255 to access all counters according to the detailed report of check points at.." newline hexmask.long.byte 0x4 20.--23. 1. "REG_LAST_UNCORR_ERROR,Region of the last uncorrected error: - 0x0: Region select for Adm Rx path - 0x1: Region select for layer 3 Rx path - 0x2: Region select for layer 2 Rx path - 0x3: Region select for DMA inbound path - 0x4: Region select for AXI.." newline hexmask.long.byte 0x4 16.--19. 1. "RSVDP_16,Reserved for future use." newline hexmask.long.byte 0x4 8.--15. 1. "LOC_FIRST_UNCORR_ERROR,Location/ID of the first uncorrected error within the region defined by REG_FIRST_UNCORR_ERROR. You can cycle this field value from 0 to 255 to access all counters according to the detailed report of check points at.." newline hexmask.long.byte 0x4 4.--7. 1. "REG_FIRST_UNCORR_ERROR,Region of the first uncorrected error: - 0x0: Region select for Adm Rx path - 0x1: Region select for layer 3 Rx path - 0x2: Region select for layer 2 Rx path - 0x3: Region select for DMA inbound path - 0x4: Region select for AXI.." newline hexmask.long.byte 0x4 0.--3. 1. "RSVDP_0,Reserved for future use." group.long (0x28+0x480)++0x7 line.long 0x0 "RASDP_ERROR_MODE_EN_OFF,RASDP error mode enable. The controller enters RASDP error mode (if ERROR_MODE_EN =1) upon detection of the first uncorrectable error. During this mode: - Rx TLPs that are forwarded to your application are not guaranteed to be.." hexmask.long 0x0 2.--31. 1. "RSVDP_2,Reserved for future use." newline bitfld.long 0x0 1. "AUTO_LINK_DOWN_EN,Write '1' to enable the controller to bring the link down when the controller enters RASDP error mode. Note: This register field is sticky." "0,1" newline bitfld.long 0x0 0. "ERROR_MODE_EN,Write '1' to enable the controller enter RASDP error mode when it detects an uncorrectable error. Note: This register field is sticky." "0,1" line.long 0x4 "RASDP_ERROR_MODE_CLEAR_OFF,Exit RASDP error mode. For more details. see the RAS Data Protection (DP) section in the Core Operations chapter of the Databook." hexmask.long 0x4 1.--31. 1. "RSVDP_1,Reserved for future use." newline bitfld.long 0x4 0. "ERROR_MODE_CLEAR,Write '1' to take the controller out of RASDP error mode. The controller will then report uncorrectable errors (through AER internal error reporting) and also stop nullifying/discarding TLPs." "0,1" rgroup.long (0x30+0x480)++0x7 line.long 0x0 "RASDP_RAM_ADDR_CORR_ERROR_OFF,RAM Address where a corrected error (1-bit ECC) has been detected. For more details. see the RAS Data Protection (DP) section in the Core Operations chapter of the Databook." hexmask.long.byte 0x0 28.--31. 1. "RAM_INDEX_CORR_ERROR,RAM index where a corrected error (1-bit ECC) has been detected." newline bitfld.long 0x0 27. "RSVDP_27,Reserved for future use." "0,1" newline hexmask.long 0x0 0.--26. 1. "RAM_ADDR_CORR_ERROR,RAM Address where a corrected error (1-bit ECC) has been detected." line.long 0x4 "RASDP_RAM_ADDR_UNCORR_ERROR_OFF,RAM Address where an uncorrected error (2-bit ECC) has been detected. For more details. see the RAS Data Protection (DP) section in the Core Operations chapter of the Databook." hexmask.long.byte 0x4 28.--31. 1. "RAM_INDEX_UNCORR_ERROR,RAM index where an uncorrected error (2-bit ECC) has been detected." newline bitfld.long 0x4 27. "RSVDP_27,Reserved for future use." "0,1" newline hexmask.long 0x4 0.--26. 1. "RAM_ADDR_UNCORR_ERROR,RAM Address where an uncorrected error (2-bit ECC) has been detected." tree.end tree "PF0_RTR_CAP (PF RTR Capability Structure)" group.long (0x0+0x2F8)++0xB line.long 0x0 "RTR_EXT_CAP_HDR_OFF,Readiness Time Reporting PCI Express Extended Capability Header. For a description of this standard PCIe register. see the PCI Express Specification." hexmask.long.word 0x0 20.--31. 1. "RTR_NEXT_OFFSET,Next Capability Offset. For a description of this standard PCIe register field see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky).." hexmask.long.byte 0x0 16.--19. 1. "RTR_CAP_VERSION,Capability Version. For a description of this standard PCIe register field see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky).." hexmask.long.word 0x0 0.--15. 1. "RTR_EXT_CAP_ID,PCI Express Extended Capability ID. For a description of this standard PCIe register field see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then.." line.long 0x4 "READI_TIME_REPORTING1_OFF,Readiness Time Reporting 1. For a description of this standard PCIe register. see the PCI Express Specification." bitfld.long 0x4 31. "RTR_TIME_VALID,Valid. For a description of this standard PCIe register field see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky)" "0,1" hexmask.long.byte 0x4 24.--30. 1. "RSVDP_24,Reserved for future use." hexmask.long.word 0x4 12.--23. 1. "DL_UP_TIME,DL_UP Time. For a description of this standard PCIe register field see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky)" hexmask.long.word 0x4 0.--11. 1. "RESET_TIME,Reset Time. For a description of this standard PCIe register field see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky)" line.long 0x8 "READI_TIME_REPORTING2_OFF,Readiness Time Reporting 2. For a description of this standard PCIe register. see the PCI Express Specification." hexmask.long.byte 0x8 24.--31. 1. "RSVDP_24,Reserved for future use." hexmask.long.word 0x8 12.--23. 1. "D3HOT_D0_TIME,D3hot to D0 Time. For a description of this standard PCIe register field see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else.." hexmask.long.word 0x8 0.--11. 1. "FLR_TIME,FLR Time. For a description of this standard PCIe register field see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky)" tree.end tree "PF0_RTR_CAP_DBI2 (DBI2 Shadow Block: PF RTR Capability Structure)" rgroup.long (0x4+0x12F8)++0x7 line.long 0x0 "SHADOW_READI_TIME_REPORTING1_OFF,Shadow Register Readiness Time Reporting 1. For a description of this standard PCIe register. see the PCI Express Specification." bitfld.long 0x0 31. "RTR_TIME_VALID,Shadow Valid in the shadow register. For a description of this standard PCIe register field see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access - Dbi: No access - Dbi2: if.." "0,1" hexmask.long.tbyte 0x0 12.--30. 1. "RSVDP_12,Reserved for future use." hexmask.long.word 0x0 0.--11. 1. "RESET_TIME,Shadow Reset Time in the shadow register. For a description of this standard PCIe register field see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access - Dbi: No access - Dbi2: if.." line.long 0x4 "SHADOW_READI_TIME_REPORTING2_OFF,Shadow Register Readiness Time Reporting 2. For a description of this standard PCIe register. see the PCI Express Specification." hexmask.long.byte 0x4 24.--31. 1. "RSVDP_24,Reserved for future use." hexmask.long.word 0x4 12.--23. 1. "D3HOT_D0_TIME,Shadow D3hot to D0 Time in the shadow register. For a description of this standard PCIe register field see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access - Dbi: No access - Dbi2:.." hexmask.long.word 0x4 0.--11. 1. "FLR_TIME,Shadow FLR Time in the shadow register. For a description of this standard PCIe register field see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access - Dbi: No access - Dbi2: if.." tree.end tree "PF0_FRSQ_CAP (PF FRSQ Capability Structure)" group.long (0x0+0x2E8)++0xB line.long 0x0 "FRSQ_EXT_CAP_HDR_OFF,FRS Queuing Extended Capability Header. For a description of this standard PCIe register. see the PCI Express Specification." hexmask.long.word 0x0 20.--31. 1. "FRSQ_NEXT_OFFSET,Next Capability Offset. For a description of this standard PCIe register field see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then.." hexmask.long.byte 0x0 16.--19. 1. "FRSQ_CAP_VERSION,Capability Version. For a description of this standard PCIe register field see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky).." hexmask.long.word 0x0 0.--15. 1. "FRSQ_EXT_CAP_ID,PCI Express Extended Capability ID. For a description of this standard PCIe register field see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then.." line.long 0x4 "FRSQ_CAP_OFF,FRS Queuing Capability Register. For a description of this standard PCIe register. see the PCI Express Specification." hexmask.long.word 0x4 21.--31. 1. "RSVDP_21,Reserved for future use." hexmask.long.byte 0x4 16.--20. 1. "FRS_INT_MESSAGE_NUMBER,FRS Interrupt Message Number. For a description of this standard PCIe register field see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1).." hexmask.long.byte 0x4 12.--15. 1. "RSVDP_12,Reserved for future use." hexmask.long.word 0x4 0.--11. 1. "FRSQ_MAX_DEPTH,FRS Queue Max Depth. For a description of this standard PCIe register field see the PCI Express Specification." line.long 0x8 "FRSQ_CONTROL_FRSQ_STATUS_OFF,FRS Queuing Status and Control Register. For a description of this standard PCIe register. see the PCI Express Specification." hexmask.long.word 0x8 17.--31. 1. "RSVDP_17,Reserved for future use." bitfld.long 0x8 16. "FRS_INTERRUPT_ENABLE,FRS Interrupt Enable. For a description of this standard PCIe register field see the PCI Express Specification." "0,1" hexmask.long.word 0x8 2.--15. 1. "RSVDP_2,Reserved for future use." bitfld.long 0x8 1. "FRS_MESSAGE_OVERFLOW,FRS Message Overflow. For a description of this standard PCIe register field see the PCI Express Specification." "0,1" newline bitfld.long 0x8 0. "FRS_MESSAGE_RECEIVED,FRS Message Received. For a description of this standard PCIe register field see the PCI Express Specification." "0,1" rgroup.long (0xC+0x2E8)++0x3 line.long 0x0 "FRS_MESSAGE_QUEUE_OFF,FRS Message Queue Register. For a description of this standard PCIe register. see the PCI Express Specification." hexmask.long.word 0x0 20.--31. 1. "FRS_MESSAGE_QUE_DEPTH,FRS Message Queue Depth. For a description of this standard PCIe register field see the PCI Express Specification." hexmask.long.byte 0x0 16.--19. 1. "FRS_MESSAGE_QUE_REASON,FRS Message Queue Reason. For a description of this standard PCIe register field see the PCI Express Specification." hexmask.long.word 0x0 0.--15. 1. "FRS_MESSAGE_QUE_FUNC_ID,FRS Message Queue Function ID. For a description of this standard PCIe register field see the PCI Express Specification." tree.end tree "PF0_PTM_CAP (PF PTM Capability Structure)" group.long (0x0+0x40C)++0xB line.long 0x0 "PTM_EXT_CAP_HDR_OFF,Precision Time Measurement Capability Header. For a description of this standard PCIe register. see the PCI Express Specification." hexmask.long.word 0x0 20.--31. 1. "PTM_NEXT_OFFSET,Precision Time Measurement PCI Express Extended Capability Next Offset. For a description of this standard PCIe register see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access. -.." hexmask.long.byte 0x0 16.--19. 1. "PTM_CAP_VERSION,Precision Time Measurement PCI Express Extended Capability Version. For a description of this standard PCIe register see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi:.." hexmask.long.word 0x0 0.--15. 1. "PTM_CAP_ID,Precision Time Measurement PCI Express Extended Capability ID. For a description of this standard PCIe register see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if.." line.long 0x4 "PTM_CAP_OFF,PTM Capability Register. For a description of this standard PCIe register. see the PCI Express Specification." hexmask.long.word 0x4 16.--31. 1. "RSVDP_16,Reserved for future use." hexmask.long.byte 0x4 8.--15. 1. "PTM_CLK_GRAN,PTM Local Clock Granularity. For a description of this standard PCIe register see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky).." hexmask.long.byte 0x4 3.--7. 1. "RSVDP_3,Reserved for future use." bitfld.long 0x4 2. "PTM_ROOT_CAPABLE,PTM Root Capable. For a description of this standard PCIe register see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else.." "0,1" bitfld.long 0x4 1. "PTM_RES_CAPABLE,PTM Responder Capable. For a description of this standard PCIe register see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else.." "0,1" newline bitfld.long 0x4 0. "PTM_REQ_CAPABLE,PTM Requester Capable. For a description of this standard PCIe register see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else.." "0,1" line.long 0x8 "PTM_CONTROL_OFF,PTM Control Register. For a description of this standard PCIe register. see the PCI Express Specification." hexmask.long.word 0x8 16.--31. 1. "RSVDP_16,Reserved for future use." hexmask.long.byte 0x8 8.--15. 1. "EFF_GRAN,PTM Effective Granularity. For a description of this standard PCIe register see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: HWINIT" hexmask.long.byte 0x8 2.--7. 1. "RSVDP_2,Reserved for future use." rbitfld.long 0x8 1. "ROOT_SELECT,PTM Root Select. When set this Time Source is the PTM Root. For a description of this standard PCIe register see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: HWINIT" "0,1" bitfld.long 0x8 0. "PTM_ENABLE,PTM Enable. When set this function is permitted to participate in the PTM mechanism. For a description of this standard PCIe register see the PCI Express Specification." "0,1" tree.end tree "PF0_PTM_RES_CAP (PF PTM Responder Capability Structure (VSEC))" group.long (0x0+0x418)++0xB line.long 0x0 "PTM_RES_CAP_HDR_OFF,Precision Time Measurement Responder Capability Header (VSEC). For more details. see the PTM section in the Databook." hexmask.long.word 0x0 20.--31. 1. "PTM_RES_EXT_CAP_NEXT_OFFS,Precision Time Measurement Responder VSEC Next Pointer. For more details see the PTM section in the Databook. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then.." hexmask.long.byte 0x0 16.--19. 1. "PTM_RES_EXT_CAP_VER,Precision Time Measurement Responder VSEC Version. For more details see the PTM section in the Databook. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else.." hexmask.long.word 0x0 0.--15. 1. "PTM_RES_EXT_CAP_ID,Precision Time Measurement Responder VSEC ID. For more details see the PTM section in the Databook. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else.." line.long 0x4 "PTM_RES_HDR_OFF,Precision Time Measurement Responder Vendor Specific Header. For more details. see the PTM section in the Databook." hexmask.long.word 0x4 20.--31. 1. "PTM_RES_VSEC_LENGTH,PTM Responder VSEC Length. For more details see the PTM section in the Databook. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This.." hexmask.long.byte 0x4 16.--19. 1. "PTM_RES_VSEC_REV,PTM Responder VSEC Revision. For more details see the PTM section in the Databook. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This.." hexmask.long.word 0x4 0.--15. 1. "PTM_RES_VSEC_ID,PTM Responder VSEC ID. For more details see the PTM section in the Databook. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register.." line.long 0x8 "PTM_RES_CONTROL_OFF,PTM Responder Control Register. For more details. see the PTM section in the Databook." hexmask.long 0x8 2.--31. 1. "RSVDP_2,Reserved for future use." bitfld.long 0x8 1. "PTM_RES_PDEL_BYTE_REV,PTM Requester Propagation Delay Byte Reversal - Reverse the order of bytes in the PTM Propagation Delay data word of the PTM ResponseD Message for compatibility with previous revisions. For more details see the PTM section in the.." "0,1" bitfld.long 0x8 0. "PTM_RES_CCONTEXT_VALID,PTM Responder Control Context Valid - PTM Local Timing is valid. This bit is set over the DBI. A speed change or aux_clk_active will set this bit low. For more details see the PTM section in the Databook. Note: The access.." "0,1" rgroup.long (0xC+0x418)++0x3 line.long 0x0 "PTM_RES_STATUS_OFF,PTM Responder Status Register. For more details. see the PTM section in the Databook." hexmask.long 0x0 2.--31. 1. "RSVDP_2,Reserved for future use." bitfld.long 0x0 1. "PTM_RES_REQUEST_RECEIVED,PTM 1st Request Received - PTM Responder has received the first PTM Request Message. Upon receipt of a second PTM Request Message a ResponseD message with timing information will be sent from the Responder if the context is.." "0,1" bitfld.long 0x0 0. "PTM_RES_CONTEXT_VALID,PTM Responder Status Context Valid - PTM Local Timing Context is Valid. Value set from upstream port Requester in a Switch. Shadows the same in the control register in all other products. For more details see the PTM section in the.." "0,1" group.long (0x10+0x418)++0x7 line.long 0x0 "PTM_RES_LOCAL_LSB_OFF,PTM Responder Local Clock LSB. For more details. see the PTM section in the Databook." hexmask.long 0x0 0.--31. 1. "PTM_RES_LOCAL_LSB,PTM Responder Local Clock LSB - Lower 32 bits of local timer value. For more details see the PTM section in the Databook. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then.." line.long 0x4 "PTM_RES_LOCAL_MSB_OFF,PTM Responder Local Clock MSB. For more details. see the PTM section in the Databook." hexmask.long 0x4 0.--31. 1. "PTM_RES_LOCAL_MSB,PTM Responder Local Clock MSB - Upper 32 bits of local timer value. For more details see the PTM section in the Databook. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then.." rgroup.long (0x18+0x418)++0x1F line.long 0x0 "PTM_RES_T2_LSB_OFF,PTM Responder T2 Timestamp LSB. For more details. see the PTM section in the Databook." hexmask.long 0x0 0.--31. 1. "PTM_RES_T2_LSB,PTM Responder T2 Timestamp LSB - Lower 32 bits of the T2 Timestamp value. For more details see the PTM section in the Databook. Note: This register field is sticky." line.long 0x4 "PTM_RES_T2_MSB_OFF,PTM Responder T2 Timestamp MSB. For more details. see the PTM section in the Databook." hexmask.long 0x4 0.--31. 1. "PTM_RES_T2_MSB,PTM Responder T2 Timestamp MSB - Upper 32 bits of the T2 Timestamp value. For more details see the PTM section in the Databook. Note: This register field is sticky." line.long 0x8 "PTM_RES_T2P_LSB_OFF,PTM Responder T2 Previous Timestamp LSB. For more details. see the PTM section in the Databook." hexmask.long 0x8 0.--31. 1. "PTM_RES_T2P_LSB,PTM Responder T2 Previous Timestamp LSB - Lower 32 bits of the previously stored T2 Timestamp value. For more details see the PTM section in the Databook. Note: This register field is sticky." line.long 0xC "PTM_RES_T2P_MSB_OFF,PTM Responder T2 Previous Timestamp MSB. For more details. see the PTM section in the Databook." hexmask.long 0xC 0.--31. 1. "PTM_RES_T2P_MSB,PTM Responder T2 Previous Timestamp MSB - Upper 32 bits of the previously stored T2 Timestamp value. For more details see the PTM section in the Databook. Note: This register field is sticky." line.long 0x10 "PTM_RES_T3_LSB_OFF,PTM Responder T3 Timestamp LSB. For more details. see the PTM section in the Databook." hexmask.long 0x10 0.--31. 1. "PTM_RES_T3_LSB,PTM Responder T3 Timestamp LSB - Lower 32 bits of the T3 Timestamp value. For more details see the PTM section in the Databook. Note: This register field is sticky." line.long 0x14 "PTM_RES_T3_MSB_OFF,PTM Responder T3 Timestamp MSB. For more details. see the PTM section in the Databook." hexmask.long 0x14 0.--31. 1. "PTM_RES_T3_MSB,PTM Responder T3 Timestamp MSB - Upper 32 bits of the T2 Timestamp value. For more details see the PTM section in the Databook. Note: This register field is sticky." line.long 0x18 "PTM_RES_T3P_LSB_OFF,PTM Responder T3 Previous Timestamp LSB. For more details. see the PTM section in the Databook." hexmask.long 0x18 0.--31. 1. "PTM_RES_T3P_LSB,PTM Responder T3 Previous Timestamp LSB - Lower 32 bits of the previously stored T3 Timestamp value. For more details see the PTM section in the Databook. Note: This register field is sticky." line.long 0x1C "PTM_RES_T3P_MSB_OFF,PTM Responder T3 Previous Timestamp MSB. For more details. see the PTM section in the Databook." hexmask.long 0x1C 0.--31. 1. "PTM_RES_T3P_MSB,PTM Responder T3 Previous Timestamp MSB - Upper 32 bits of the previously stored T3 Timestamp value. For more details see the PTM section in the Databook. Note: This register field is sticky." group.long (0x38+0x418)++0x7 line.long 0x0 "PTM_RES_TX_LATENCY_OFF,PTM Responder TX Latency. For more details. see the PTM section in the Databook." hexmask.long.tbyte 0x0 12.--31. 1. "RSVDP_12,Reserved for future use." hexmask.long.word 0x0 0.--11. 1. "PTM_RES_TX_LATENCY,PTM Responder TX Latency - Responder Transmit path latency (12 bit wide). For more details see the PTM section in the Databook. Note: This register field is sticky." line.long 0x4 "PTM_RES_RX_LATENCY_OFF,PTM Responder RX Latency. For more details. see the PTM section in the Databook." hexmask.long.tbyte 0x4 12.--31. 1. "RSVDP_12,Reserved for future use." hexmask.long.word 0x4 0.--11. 1. "PTM_RES_RX_LATENCY,PTM Responder RX Latency - Responder Receive path latency (12 bit wide). For more details see the PTM section in the Databook. Note: This register field is sticky." rgroup.long (0x40+0x418)++0x3 line.long 0x0 "PTM_RES_NOM_CLOCK_T_OFF,PTM Responder Nominal Clock Period. For more details. see the PTM section in the Databook." hexmask.long.byte 0x0 24.--31. 1. "RSVDP_24,Reserved for future use." hexmask.long.byte 0x0 16.--23. 1. "PTM_RES_NOM_CLOCK_T_INT,PTM Responder Nominal Clock Period Integral - Integral part of the nominal PTM local clock period in nanoseconds. For more details see the PTM section in the Databook. Note: This register field is sticky." hexmask.long.word 0x0 0.--15. 1. "PTM_RES_NOM_CLOCK_T_FRAC,PTM Responder Nominal Clock Period Fractional - Fractional part of the nominal PTM local clock period. LSB is 1/(2^16) nanoseconds. For more details see the PTM section in the Databook. Note: This register field is sticky." group.long (0x44+0x418)++0x3 line.long 0x0 "PTM_RES_SCALED_CLOCK_T_OFF,PTM Responder Scaled Clock Period. For more details. see the PTM section in the Databook." bitfld.long 0x0 31. "PTM_RES_SCALED_CLOCK_T_EN,PTM Responder Scaled Clock Period Enable - Use the programmed scaled PTM clock period rather than the nominal values. This bit is cleared when the core_clk rate starts to change and can only be set when the clock period change.." "0,1" hexmask.long.byte 0x0 24.--30. 1. "RSVDP_24,Reserved for future use." hexmask.long.byte 0x0 16.--23. 1. "PTM_RES_SCALED_CLOCK_T_INT,PTM Responder Scaled Clock Period Integral - Integral part of the nominal PTM local clock period in nanoseconds. For more details see the PTM section in the Databook. Note: This register field is sticky." newline hexmask.long.word 0x0 0.--15. 1. "PTM_RES_SCALED_CLOCK_T_FRAC,PTM Responder Scaled Clock Period Fractional - Fractional part of the nominal PTM local clock period. LSB is 1/(2^16) nanoseconds. For more details see the PTM section in the Databook. Note: This register field is sticky." tree.end tree "PF0_PM_CAP (PF PCI Power Management Capability Structure)" group.long (0x0+0x40)++0x7 line.long 0x0 "CAP_ID_NXT_PTR_REG,Power Management Capabilities Register." hexmask.long.byte 0x0 27.--31. 1. "PME_SUPPORT,PME_Support. This 5-bit field indicates the power states in which the function may generate a PME and/or forward PME messages. A value of 0b for any bit indicates that the function is not capable of asserting PME while in that power state. -.." bitfld.long 0x0 26. "D2_SUPPORT,D2_Support. If this bit is set this function supports the D2 Power Management state. Functions that do not support D2 must always return a value of 0b for this bit. Note: The access attributes of this field are as follows: - Wire: No access." "0,1" bitfld.long 0x0 25. "D1_SUPPORT,D1_Support. If this bit is set this function supports the D1 Power Management state. Functions that do not support D1 must always return a value of 0b for this bit. Note: The access attributes of this field are as follows: - Wire: No access." "0,1" bitfld.long 0x0 22.--24. "AUX_CURR,Aux_Current. This 3 bit field reports the Vaux auxiliary current requirements for the function. If this function implements the Data Register the controller hardwires this field to 000b. If PME_Support is 0 xxxxb (PME assertion from D3cold is.." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 21. "DSI,Device Specific Initialization. The DSI bit indicates whether special initialization of this function is required. When set indicates that the function requires a device specific initialization sequence following a transition to the D0uninitialized.." "0,1" bitfld.long 0x0 20. "PME_IMM_READI_RETURN_DO,Immediate_Readiness_on_Return_to_D0. - If this bit is a '1' this function is guaranteed to be ready to successfully complete valid accesses immediately after being set to D0. These accesses include configuration cycles and if.." "0,1" rbitfld.long 0x0 19. "PME_CLK,PME Clock. Does not apply to PCI Express the controller hardwires it to 0b. Note: This register field is sticky." "0,1" bitfld.long 0x0 16.--18. "PM_SPEC_VER,Version. This field provides the Power Management specification version. The controller hardwires this field to 011b for functions compliant to PCI Express Base Specification Revision 4.0 Version 1.0>. Note: The access attributes of this.." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x0 8.--15. 1. "PM_NEXT_POINTER,Next Capability Pointer. This field provides an offset into the function's configuration space pointing to the location of next item in the capabilities list. If there are no additional items in the capabilities list this field is set to.." hexmask.long.byte 0x0 0.--7. 1. "PM_CAP_ID,Capability ID. This field returns 01h to indicate that this is the PCI Power Management Capability. Each function may have only one item in its capability list with Capability ID set to 01h." line.long 0x4 "CON_STATUS_REG,Power Management Control and Status Register. This register is used to manage the PCI function's power management state as well as to enable/monitor PMEs." hexmask.long.byte 0x4 24.--31. 1. "DATA_REG_ADD_INFO,Data. This field is used to report the state dependent data requested by the Data_Select field. The value of this field is scaled by the value reported by the Data_Scale field." rbitfld.long 0x4 23. "BUS_PWR_CLK_CON_EN,Bus Power/Clock Control Enable. For a description of this standard PCIe register field see the PCI Express Base Specification." "0,1" rbitfld.long 0x4 22. "B2_B3_SUPPORT,B2B3 Support for D3hot. For a description of this standard PCIe register field see the PCI Express Base Specification." "0,1" hexmask.long.byte 0x4 16.--21. 1. "RSVDP_16,Reserved for future use." newline bitfld.long 0x4 15. "PME_STATUS,PME_Status. This bit is set when the function normally generates a PME signal. The value of this bit is not affected by the value of the PME_En bit. If PME_Support bit 31 of the Power Management Capabilities register is clear this bit is.." "0,1" rbitfld.long 0x4 13.--14. "DATA_SCALE,Data_Scale. This field indicates the scaling factor to be used when interpreting the value of the Data field. The value and meaning of this field varies depending on which data value has been selected by the Data_Select field. For more details.." "0,1,2,3" hexmask.long.byte 0x4 9.--12. 1. "DATA_SELECT,Data_Select. This 4-bit field is used to select which data is to be reported through the Data and Data_Scale field. If the Data field is not implemented this field must be hardwired to 0000b." bitfld.long 0x4 8. "PME_ENABLE,PME_En. - When set the function is permitted to generate a PME. - When clear the function is not permitted to generate a PME. If PME_Support is 1 xxxxb (PME generation from D3cold) or the function consumes Aux power and Aux power is.." "0,1" newline hexmask.long.byte 0x4 4.--7. 1. "RSVDP_4,Reserved for future use." bitfld.long 0x4 3. "NO_SOFT_RST,No_Soft_Reset. This bit indicates the state of the function after writing the PowerState field to transition the function from D3hot to D0. - When set this transition preserves internal function state. The function is in D0Active and no.." "0,1" rbitfld.long 0x4 2. "RSVDP_2,Reserved for future use." "0,1" bitfld.long 0x4 0.--1. "POWER_STATE,PowerState. This 2-bit field is used both to determine the current power state of a function and to set the function into a new power state. The definition of the field values is given below. You can write to this register; however the.." "D0,D1,D2,D3hot" tree.end tree "PF0_PCIE_CAP (PF PCI Express Capability Structure)" group.long (0x0+0x70)++0x33 line.long 0x0 "PCIE_CAP_ID_PCIE_NEXT_CAP_PTR_PCIE_CAP_REG,PCI Express Capabilities. ID. Next Pointer Register." rbitfld.long 0x0 31. "RSVDP_31,Reserved for future use." "0,1" rbitfld.long 0x0 30. "RSVD,Reserved." "0,1" newline hexmask.long.byte 0x0 25.--29. 1. "PCIE_INT_MSG_NUM,PCIE Interrupt Message Number. For a description of this standard PCIe register field see the PCI Express Base Specification. Interrupt Message Number. This field indicates which MSI/MSI-X vector is used for the interrupt message.." bitfld.long 0x0 24. "PCIE_SLOT_IMP,Slot Implemented. When set this bit indicates that the Link associated with this Port is connected to a slot (as compared to being connected to a system-integrated device or being disabled). This bit is valid for Downstream Ports. This bit.." "0,1" newline hexmask.long.byte 0x0 20.--23. 1. "PCIE_DEV_PORT_TYPE,Device/Port Type. Indicates the specific type of this PCI Express function. Note: Different functions in a Multi-Function Device can generally be of different types. Defined encodings for functions that implement a Type 00h PCI.." hexmask.long.byte 0x0 16.--19. 1. "PCIE_CAP_REG,Capability Version. Indicates PCI-SIG defined PCI Express Capability structure version number. A version of the specification that changes the PCI Express Capability structure in a way that is not otherwise identifiable (for example through.." newline hexmask.long.byte 0x0 8.--15. 1. "PCIE_CAP_NEXT_PTR,Next Capability Pointer. This field contains the offset to the next PCI Capability structure or 00h if no other items exist in the linked list of Capabilities. Note: The access attributes of this field are as follows: - Wire: No access." hexmask.long.byte 0x0 0.--7. 1. "PCIE_CAP_ID,Capability ID. Indicates the PCI Express Capability structure. This field must return a Capability ID of 10h indicating that this is a PCI Express Capability structure." line.long 0x4 "DEVICE_CAPABILITIES_REG,Device Capabilities Register. The Device Capabilities register identifies PCI Express device function specific capabilities." hexmask.long.word 0x4 16.--31. 1. "RSVDP_16,Reserved for future use." bitfld.long 0x4 15. "PCIE_CAP_ROLE_BASED_ERR_REPORT,Role-Based Error Reporting. When set this bit indicates that the function implements the functionality originally defined in the Error Reporting ECN for PCI Express Base Specification Revision 1.0a and later incorporated.." "0,1" newline hexmask.long.word 0x4 6.--14. 1. "RSVDP_6,Reserved for future use." bitfld.long 0x4 5. "PCIE_CAP_EXT_TAG_SUPP,Extended Tag Field Supported. This bit in combination with the 10-Bit Tag Requester Supported bit in the Device Capabilities 2 register indicates the maximum supported size of the Tag field as a Requester. This bit must be set if.." "0,1" newline bitfld.long 0x4 3.--4. "PCIE_CAP_PHANTOM_FUNC_SUPPORT,Phantom Functions Supported. This field indicates the support for use of unclaimed function numbers to extend the number of outstanding transactions allowed by logically combining unclaimed function numbers (called Phantom.." "0,1,2,3" bitfld.long 0x4 0.--2. "PCIE_CAP_MAX_PAYLOAD_SIZE,Max_Payload_Size Supported. This field indicates the maximum payload size that the function can support for TLPs. Defined encodings are: - 000b: 128 bytes max payload size - 001b: 256 bytes max payload size - 010b: 512 bytes max.." "0,1,2,3,4,5,6,7" line.long 0x8 "DEVICE_CONTROL_DEVICE_STATUS,Device Control and Device Status Register. This register controls PCI Express device specific parameters and provides information about PCI Express device (function) specific parameters." hexmask.long.word 0x8 22.--31. 1. "RSVDP_22,Reserved for future use." rbitfld.long 0x8 21. "PCIE_CAP_TRANS_PENDING,Transactions Pending. Endpoints: When set this bit indicates that the function has issued Non-Posted Requests that have not been completed. A Function reports this bit cleared only when all outstanding Non-Posted Requests have.." "0,1" newline rbitfld.long 0x8 20. "PCIE_CAP_AUX_POWER_DETECTED,AUX Power Detected. Functions that require Aux power report this bit as set if Aux power is detected by the function. This bit is derived by sampling the sys_aux_pwr_det input." "0,1" bitfld.long 0x8 19. "PCIE_CAP_UNSUPPORTED_REQ_DETECTED,Unsupported Request Detected. This bit indicates that the function received an Unsupported Request. Errors are logged in this register regardless of whether error reporting is enabled or not in the Device Control.." "0,1" newline bitfld.long 0x8 18. "PCIE_CAP_FATAL_ERR_DETECTED,Fatal Error Detected. This bit indicates status of Fatal errors detected. Errors are logged in this register regardless of whether error reporting is enabled or not in the Device Control register. For a Multi-Function device.." "0,1" bitfld.long 0x8 17. "PCIE_CAP_NON_FATAL_ERR_DETECTED,Non-Fatal Error Detected. This bit indicates status of Non-fatal errors detected. Errors are logged in this register regardless of whether error reporting is enabled or not in the Device Control register. For a.." "0,1" newline bitfld.long 0x8 16. "PCIE_CAP_CORR_ERR_DETECTED,Correctable Error Detected. This bit indicates status of correctable errors detected. Errors are logged in this register regardless of whether error reporting is enabled or not in the Device Control register. For a.." "0,1" bitfld.long 0x8 15. "PCIE_CAP_INITIATE_FLR,Initiate Function Level Reset (applicable to Endpoints with Function Level Reset Capability set to 1b). A write of 1b initiates Function Level Reset to the Function. The value read by software from this bit is always 0b." "0,1" newline bitfld.long 0x8 12.--14. "PCIE_CAP_MAX_READ_REQ_SIZE,Max_Read_Request_Size. This field sets the maximum Read Request size for the function as a Requester. The function must not generate Read Requests with a size exceeding the set value. Defined encodings for this field are: -.." "0,1,2,3,4,5,6,7" rbitfld.long 0x8 11. "PCIE_CAP_EN_NO_SNOOP,Enable No Snoop. If this bit is set the function is permitted to Set the No Snoop bit in the Requester Attributes of transactions it initiates that do not require hardware enforced cache coherency (see section 2.2.6.5 in PCI Express.." "0,1" newline bitfld.long 0x8 10. "PCIE_CAP_AUX_POWER_PM_EN,Aux Power PM Enable. This bit is derived by sampling the sys_aux_pwr_det input. When set this bit enables a function to draw Aux power independent of PME Aux power. Functions that require Aux power on legacy operating systems.." "0,1" rbitfld.long 0x8 9. "PCIE_CAP_PHANTOM_FUNC_EN,Phantom Functions Enable. This bit in combination with the 10-Bit Tag Requester Enable bit in the Device Control 2 register determines how many Tag field bits a Requester is permitted to use. When the 10-Bit Tag Requester.." "0,1" newline rbitfld.long 0x8 8. "PCIE_CAP_EXT_TAG_EN,Extended Tag Field Enable. This bit in combination with the 10-Bit Tag Requester Enable bit in the Device Control 2 register determines how many Tag field bits a Requester is permitted to use. When the 10-Bit Tag Requester Enable.." "0,1" bitfld.long 0x8 5.--7. "PCIE_CAP_MAX_PAYLOAD_SIZE_CS,Max_Payload_Size. This field sets maximum TLP payload size for the Function. As a Receiver the Function must handle TLPs as large as the set value. As a Transmitter the Function must not generate TLPs exceeding the set.." "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 4. "PCIE_CAP_EN_REL_ORDER,Enable Relaxed Ordering. If this bit is set the function is permitted to set the Relaxed Ordering bit in the Attributes field of transactions it initiates that do not require strong write ordering (for more details see section.." "0,1" bitfld.long 0x8 3. "PCIE_CAP_UNSUPPORT_REQ_REP_EN,Unsupported Request Reporting Enable. This bit in conjunction with other bits controls the signaling of Unsupported Request Errors by sending error Messages (for more details see section 6.2.5 and section 6.2.6 of PCI.." "0,1" newline bitfld.long 0x8 2. "PCIE_CAP_FATAL_ERR_REPORT_EN,Fatal Error Reporting Enable. This bit in conjunction with other bits controls sending ERR_FATAL Messages (for more details see section 6.2.5 and section 6.2.6 of of PCI Express Base Specification). For a Multi-Function.." "0,1" bitfld.long 0x8 1. "PCIE_CAP_NON_FATAL_ERR_REPORT_EN,Non-Fatal Error Reporting Enable. This bit in conjunction with other bits controls sending ERR_NONFATAL Messages (for more details see section 6.2.5 and Section 6.2.6 of PCI Express Base Specification). For a.." "0,1" newline bitfld.long 0x8 0. "PCIE_CAP_CORR_ERR_REPORT_EN,Correctable Error Reporting Enable. This bit in conjunction with other bits controls sending ERR_COR Messages (for more details see section 6.2.5 section 6.2.6 and section 6.2.10.2 of PCI Express Base Specification). For.." "0,1" line.long 0xC "LINK_CAPABILITIES_REG,Link Capabilities Register. The Link Capabilities register identifies PCI Express Link specific capabilities." hexmask.long.byte 0xC 24.--31. 1. "PCIE_CAP_PORT_NUM,Port Number. This field indicates the PCI Express Port number for the given PCI Express Link. Multi-Function Devices associated with an Upstream Port must report the same value in this field for all functions. Note: The access.." rbitfld.long 0xC 23. "RSVDP_23,Reserved for future use." "0,1" newline bitfld.long 0xC 22. "PCIE_CAP_ASPM_OPT_COMPLIANCE,ASPM Optionality Compliance. This bit must be set to 1b in all functions. Components implemented against certain earlier versions of this specification will have this bit set to 0b. Software is permitted to use the value of.." "0,1" bitfld.long 0xC 21. "PCIE_CAP_LINK_BW_NOT_CAP,Link Bandwidth Notification Capability. A value of 1b indicates support for the Link Bandwidth Notification status and interrupt mechanisms. This capability is required for all Root Ports and Switch Downstream Ports supporting.." "0,1" newline rbitfld.long 0xC 20. "PCIE_CAP_DLL_ACTIVE_REP_CAP,Data Link Layer Link Active Reporting Capable. For a Downstream Port the controller hardwires this bit to 1b if the component supports the optional capability of reporting the DL_Active state of the Data Link Control and.." "0,1" bitfld.long 0xC 19. "PCIE_CAP_SURPRISE_DOWN_ERR_REP_CAP,Surprise Down Error Reporting Capable. For a Downstream Port this bit must be set if the component supports the optional capability of detecting and reporting a Surprise Down error condition. For Upstream Ports and.." "0,1" newline rbitfld.long 0xC 18. "PCIE_CAP_CLOCK_POWER_MAN,Clock Power Management. For Upstream Ports a value of 1b in this bit indicates that the component tolerates the removal of any reference clock(s) via the 'clock request' (CLKREQ#) mechanism when the Link is in the L1 and L2/L3.." "0,1" bitfld.long 0xC 15.--17. "PCIE_CAP_L1_EXIT_LATENCY,L1 Exit Latency. This field indicates the L1 exit latency for the given PCI Express Link. The value reported indicates the length of time this Port requires to complete transition from ASPM L1 to L0. If ASPM L1 is not supported.." "0,1,2,3,4,5,6,7" newline bitfld.long 0xC 12.--14. "PCIE_CAP_L0S_EXIT_LATENCY,L0s Exit Latency. This field indicates the L0s exit latency for the given PCI Express Link. The value reported indicates the length of time this Port requires to complete transition from L0s to L0. If L0s is not supported the.." "0,1,2,3,4,5,6,7" bitfld.long 0xC 10.--11. "PCIE_CAP_ACTIVE_STATE_LINK_PM_SUPPORT,Active State Power Management (ASPM) Support. This field indicates the level of ASPM supported on the given PCI Express Link. For more details on ASPM support requirements see section 5.4.1 of PCI Express Base.." "0,1,2,3" newline hexmask.long.byte 0xC 4.--9. 1. "PCIE_CAP_MAX_LINK_WIDTH,Maximum Link Width. This field indicates the maximum Link width (xN - corresponding to N Lanes) implemented by the component. This value is permitted to exceed the number of Lanes routed to the slot (Downstream Port) adapter.." hexmask.long.byte 0xC 0.--3. 1. "PCIE_CAP_MAX_LINK_SPEED,Max Link Speed. This field indicates the maximum Link speed of the associated Port. The encoded value specifies a bit location in the Supported Link Speeds Vector (in the Link Capabilities 2 register) that corresponds to the.." line.long 0x10 "LINK_CONTROL_LINK_STATUS_REG,Link Control and Link Status Register. This register controls and provides information about PCI Express Link specific parameters." bitfld.long 0x10 31. "PCIE_CAP_LINK_AUTO_BW_STATUS,Link Autonomous Bandwidth Status. This bit is set by hardware to indicate that hardware has autonomously changed Link speed or width without the Port transitioning through DL_Down status for reasons other than to attempt to.." "0,1" bitfld.long 0x10 30. "PCIE_CAP_LINK_BW_MAN_STATUS,Link Bandwidth Management Status. This bit is set by hardware to indicate that either of the following has occurred without the Port transitioning through DL_Down status: - A Link retraining has completed following a write of.." "0,1" newline rbitfld.long 0x10 29. "PCIE_CAP_DLL_ACTIVE,Data Link Layer Link Active. This bit indicates the status of the Data Link Control and Management State Machine. It returns a 1b to indicate the DL_Active state 0b otherwise. This bit must be implemented if the Data Link Layer Link.." "0,1" bitfld.long 0x10 28. "PCIE_CAP_SLOT_CLK_CONFIG,Slot Clock Configuration. This bit indicates that the component uses the same physical reference clock that the platform provides on the connector. If the device uses an independent clock irrespective of the presence of a.." "0,1" newline rbitfld.long 0x10 27. "PCIE_CAP_LINK_TRAINING,Link Training. This read-only bit indicates that the Physical Layer LTSSM is in the Configuration or Recovery state or that 1b was written to the Retrain Link bit but Link training has not yet begun. Hardware clears this bit when.." "0,1" rbitfld.long 0x10 26. "RSVDP_26,Reserved for future use." "0,1" newline hexmask.long.byte 0x10 20.--25. 1. "PCIE_CAP_NEGO_LINK_WIDTH,Negotiated Link Width. This field indicates the negotiated width of the given PCI Express Link. Defined encodings are: -00 0001b: x1 -00 0010b: x2 -00 0100b: x4 -00 1000b: x8 -00 1100b: x12 -01 0000b: x16 -10 0000b: x32 All other.." hexmask.long.byte 0x10 16.--19. 1. "PCIE_CAP_LINK_SPEED,Current Link Speed. This field indicates the negotiated Link speed of the given PCI Express Link. The encoded value specifies a bit location in the Supported Link Speeds Vector (in the Link Capabilities 2 register) that corresponds to.." newline bitfld.long 0x10 14.--15. "PCIE_CAP_DRS_SIGNALING_CONTROL,DRS Signaling Control. Indicates the mechanism used to report reception of a DRS message. Must be implemented for Downstream Ports with the DRS Supported bit Set in the Link Capabilities 2 Register. Encodings are: - 00b:.." "0,1,2,3" rbitfld.long 0x10 12.--13. "RSVDP_12,Reserved for future use." "0,1,2,3" newline bitfld.long 0x10 11. "PCIE_CAP_LINK_AUTO_BW_INT_EN,Link Autonomous Bandwidth Management Interrupt Enable. When set this bit enables the generation of an interrupt to indicate that the Link Autonomous Bandwidth Status bit has been set. The write value is gated with the.." "0,1" bitfld.long 0x10 10. "PCIE_CAP_LINK_BW_MAN_INT_EN,Link Bandwidth Management Interrupt Enable. When set this bit enables the generation of an interrupt to indicate that the Link Bandwidth Management Status bit has been set. The write value is gated with the.." "0,1" newline bitfld.long 0x10 9. "PCIE_CAP_HW_AUTO_WIDTH_DISABLE,Hardware Autonomous Width Disable. When set this bit disables hardware from changing the Link width for reasons other than attempting to correct unreliable Link operation by reducing Link width. For a Multi-Function Device.." "0,1" bitfld.long 0x10 8. "PCIE_CAP_EN_CLK_POWER_MAN,Enable Clock Power Management. Applicable only for Upstream Ports and with form factors that support a 'Clock Request' (CLKREQ#) mechanism this bit operates as follows: - 0b: Clock power management is disabled and device must.." "0,1" newline bitfld.long 0x10 7. "PCIE_CAP_EXTENDED_SYNCH,Extended Synch. When set this bit forces the transmission of additional Ordered Sets when exiting the L0s state (see section 4.2.4.5 of PCI Express Base Specification) and when in the Recovery state (see section 4.2.6.4.1 of PCI.." "0,1" bitfld.long 0x10 6. "PCIE_CAP_COMMON_CLK_CONFIG,Common Clock Configuration. When set this bit indicates that this component and the component at the opposite end of this Link are operating with a distributed common reference clock. A value of 0b indicates that this.." "0,1" newline bitfld.long 0x10 5. "PCIE_CAP_RETRAIN_LINK,Retrain Link. A write of 1b to this bit initiates Link retraining by directing the Physical Layer LTSSM to the Recovery state. If the LTSSM is already in Recovery or Configuration re-entering Recovery is permitted but not required." "0,1" bitfld.long 0x10 4. "PCIE_CAP_LINK_DISABLE,Link Disable. This bit disables the Link by directing the LTSSM to the Disabled state when set; this bit is Reserved on Endpoints PCI Express to PCI/PCI-X bridges and Upstream Ports of Switches. Writes to this bit are immediately.." "0,1" newline bitfld.long 0x10 3. "PCIE_CAP_RCB,Read Completion Boundary (RCB). Root Ports: Indicates the RCB value for the Root Port. Refer to section 2.3.1.1 of PCI Express Base Specification for the definition of the parameter RCB. Defined encodings are: - 0b: 64 byte - 1b: 128 byte.." "0,1" rbitfld.long 0x10 2. "RSVDP_2,Reserved for future use." "0,1" newline bitfld.long 0x10 0.--1. "PCIE_CAP_ACTIVE_STATE_LINK_PM_CONTROL,Active State Power Management (ASPM) Control. This field controls the level of ASPM enabled on the given PCI Express Link. See section 5.4.1.3 of PCI Express Base Specification for requirements on when and how to.." "0,1,2,3" line.long 0x14 "SLOT_CAPABILITIES_REG,Slot Capabilities Register. The Slot Capabilities register identifies PCI Express slot specific capabilities." hexmask.long.word 0x14 19.--31. 1. "PCIE_CAP_PHY_SLOT_NUM,Physical Slot Number. This field indicates the physical slot number attached to this Port. This field must be hardware initialized to a value that assigns a slot number that is unique within the chassis regardless of the form.." bitfld.long 0x14 18. "PCIE_CAP_NO_CMD_CPL_SUPPORT,No Command Completed Support. When set this bit indicates that this slot does not generate software notification when an issued command is completed by the Hot-Plug Controller. This bit is only permitted to be set if the.." "0,1" newline bitfld.long 0x14 17. "PCIE_CAP_ELECTROMECH_INTERLOCK,Electromechanical Interlock Present. When set this bit indicates that an Electromechanical Interlock is implemented on the chassis for this slot. Note: The access attributes of this field are as follows: - Wire: No access." "0,1" bitfld.long 0x14 15.--16. "PCIE_CAP_SLOT_POWER_LIMIT_SCALE,Slot Power Limit Scale. Specifies the scale used for the Slot Power Limit Value (for more details see Section 6.9 of PCI Express Base Specification). Range of Values: - 00b: 1.0x - 01b: 0.1x - 10b: 0.01x - 11b: 0.001x.." "0,1,2,3" newline hexmask.long.byte 0x14 7.--14. 1. "PCIE_CAP_SLOT_POWER_LIMIT_VALUE,Slot Power Limit Value. In combination with the Slot Power Limit Scale value specifies the upper limit on power supplied by the slot (for more detais see Section 6.9 of PCI Express Base Specification) or by other means.." bitfld.long 0x14 6. "PCIE_CAP_HOT_PLUG_CAPABLE,Hot-Plug Capable. When set this bit indicates that this slot is capable of supporting hot-plug operations. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then R/W else R" "0,1" newline bitfld.long 0x14 5. "PCIE_CAP_HOT_PLUG_SURPRISE,Hot-Plug Surprise. When set this bit indicates that an adapter present in this slot might be removed from the system without any prior notification. This is a form factor specific capability. This bit is an indication to the.." "0,1" bitfld.long 0x14 4. "PCIE_CAP_POWER_INDICATOR,Power Indicator Present. When set this bit indicates that a Power Indicator is electrically controlled by the chassis for this slot. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if.." "0,1" newline bitfld.long 0x14 3. "PCIE_CAP_ATTENTION_INDICATOR,Attention Indicator Present. When set this bit indicates that an Attention Indicator is electrically controlled by the chassis. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if.." "0,1" bitfld.long 0x14 2. "PCIE_CAP_MRL_SENSOR,MRL Sensor Present. When set this bit indicates that an MRL Sensor is implemented on the chassis for this slot. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then R/W else R" "0,1" newline bitfld.long 0x14 1. "PCIE_CAP_POWER_CONTROLLER,Power Controller Present. When set this bit indicates that a software programmable Power Controller is implemented for this slot/adapter (depending on form factor). Note: The access attributes of this field are as follows: -.." "0,1" bitfld.long 0x14 0. "PCIE_CAP_ATTENTION_INDICATOR_BUTTON,Attention Button Present. When set this bit indicates that an Attention Button for this slot is electrically controlled by the chassis. Note: The access attributes of this field are as follows: - Wire: No access. -.." "0,1" line.long 0x18 "SLOT_CONTROL_SLOT_STATUS,Slot Control and Status Register. This register controls and provides information about PCI Express Slot specific parameters." hexmask.long.byte 0x18 25.--31. 1. "RSVDP_25,Reserved for future use." bitfld.long 0x18 24. "PCIE_CAP_DLL_STATE_CHANGED,Data Link Layer State Changed. This bit is set when the value reported in the Data Link Layer Link Active bit of the Link Status register is changed. In response to a Data Link Layer State Changed event software must read the.." "0,1" newline rbitfld.long 0x18 23. "PCIE_CAP_ELECTROMECH_INTERLOCK_STATUS,Electromechanical Interlock Status. If an Electromechanical Interlock is implemented this bit indicates the status of the Electromechanical Interlock. Defined encodings are: - 0b: Electromechanical Interlock.." "0,1" rbitfld.long 0x18 22. "PCIE_CAP_PRESENCE_DETECT_STATE,Presence Detect State. This bit indicates the presence of an adapter in the slot reflected by the logical 'OR' of the Physical Layer in-band presence detect mechanism and if present any out-of-band presence detect.." "0,1" newline rbitfld.long 0x18 21. "PCIE_CAP_MRL_SENSOR_STATE,MRL Sensor State. This bit reports the status of the MRL sensor if implemented. Defined encodings are: - 0b: MRL Closed - 1b: MRL Open" "0,1" bitfld.long 0x18 20. "PCIE_CAP_CMD_CPLD,Command Completed. If Command Completed notification is supported (if the No Command Completed Support bit in the Slot Capabilities register is 0b) this bit is set when a hot-plug command has completed and the Hot-Plug Controller is.." "0,1" newline bitfld.long 0x18 19. "PCIE_CAP_PRESENCE_DETECTED_CHANGED,Presence Detect Changed. This bit is set when the value reported in the Presence Detect State bit is changed." "0,1" bitfld.long 0x18 18. "PCIE_CAP_MRL_SENSOR_CHANGED,MRL Sensor Changed. If an MRL sensor is implemented this bit is set when a MRL Sensor state change is detected. If an MRL sensor is not implemented this bit must not be set." "0,1" newline bitfld.long 0x18 17. "PCIE_CAP_POWER_FAULT_DETECTED,Power Fault Detected. If a Power Controller that supports power fault detection is implemented this bit issSet when the Power Controller detects a power fault at this slot. Note: Depending on hardware capability it is.." "0,1" bitfld.long 0x18 16. "PCIE_CAP_ATTENTION_BUTTON_PRESSED,Attention Button Pressed. If an Attention Button is implemented this bit is set when the attention button is pressed. If an Attention Button is not supported this bit must not be set." "0,1" newline rbitfld.long 0x18 14.--15. "RSVDP_14,Reserved for future use." "0,1,2,3" bitfld.long 0x18 12. "PCIE_CAP_DLL_STATE_CHANGED_EN,Data Link Layer State Changed Enable. If the Data Link Layer Link Active Reporting capability is 1b this bit enables software notification when Data Link Layer Link Active bit is changed. If the Data Link Layer Link Active.." "0,1" newline bitfld.long 0x18 11. "PCIE_CAP_ELECTROMECH_INTERLOCK_CTRL,Electromechanical Interlock Control. If an Electromechanical Interlock is implemented a write of 1b to this bit causes the state of the interlock to toggle. A write of 0b to this bit has no effect. A read of this bit.." "0,1" bitfld.long 0x18 10. "PCIE_CAP_POWER_CONTROLLER_CTRL,Power Controller Control. If a Power Controller is implemented this bit when written sets the power state of the slot per the defined encodings. Reads of this bit must reflect the value from the latest write even if the.." "0,1" newline bitfld.long 0x18 8.--9. "PCIE_CAP_POWER_INDICATOR_CTRL,Power Indicator Control. If a Power Indicator is implemented writes to this field set the Power Indicator to the written state. Reads of this field must reflect the value from the latest write even if the corresponding.." "0,1,2,3" bitfld.long 0x18 6.--7. "PCIE_CAP_ATTENTION_INDICATOR_CTRL,Attention Indicator Control. If an Attention Indicator is implemented writes to this field set the Attention Indicator to the written state. Reads of this field must reflect the value from the latest write even if the.." "0,1,2,3" newline bitfld.long 0x18 5. "PCIE_CAP_HOT_PLUG_INT_EN,Hot-Plug Interrupt Enable. When set this bit enables generation of an interrupt on enabled hot-plug events. If the Hot Plug Capable bit in the Slot Capabilities register is clear this bit is permitted to be read-only with a.." "0,1" bitfld.long 0x18 4. "PCIE_CAP_CMD_CPL_INT_EN,Command Completed Interrupt Enable. If Command Completed notification is supported (if the No Command Completed Support bit in the Slot Capabilities register is 0b) when set this bit enables software notification when a hot-plug.." "0,1" newline bitfld.long 0x18 3. "PCIE_CAP_PRESENCE_DETECT_CHANGE_EN,Presence Detect Changed Enable. When set this bit enables software notification on a presence detect changed event (for more details see Section 6.7.3 of PCI Express Base Specification). If the Hot-Plug Capable bit in.." "0,1" bitfld.long 0x18 2. "PCIE_CAP_MRL_SENSOR_CHANGED_EN,MRL Sensor Changed Enable. When set this bit enables software notification on a MRL sensor changed event (for more details see Section 6.7.3 of PCI Express Base Specification). If the MRL Sensor Present bit in the Slot.." "0,1" newline bitfld.long 0x18 1. "PCIE_CAP_POWER_FAULT_DETECTED_EN,Power Fault Detected Enable. When set this bit enables software notification on a power fault event (for more details see Section 6.7.3 of PCI Express Base Specification). If a Power Controller that supports power fault.." "0,1" bitfld.long 0x18 0. "PCIE_CAP_ATTENTION_BUTTON_PRESSED_EN,Attention Button Pressed Enable. When set to 1b this bit enables software notification on an attention button pressed event (for more details see Section 6.7.3 of PCI Express Base Specification). If the Attention.." "0,1" line.long 0x1C "ROOT_CONTROL_ROOT_CAPABILITIES_REG,Root Control and Capabilities Register. This register controls PCI Express Root Complex specific parameters and identifies PCI Express Root Port specific capabilities." hexmask.long.word 0x1C 17.--31. 1. "RSVDP_17,Reserved for future use." bitfld.long 0x1C 16. "PCIE_CAP_CRS_SW_VISIBILITY,CRS Software Visibility Capable. For a description of this standard PCIe register field see the PCI Express Base Specification. CRS Software Visibility. When set this bit indicates that the Root Port is capable of returning.." "0,1" newline hexmask.long.word 0x1C 5.--15. 1. "RSVDP_5,Reserved for future use." bitfld.long 0x1C 4. "PCIE_CAP_CRS_SW_VISIBILITY_EN,CRS Software Visibility Enable. When set this bit enables the Root Port to return Configuration Request Retry Status (CRS) Completion Status to software (for more details see section 2.3.1 of PCI Express Base.." "0,1" newline bitfld.long 0x1C 3. "PCIE_CAP_PME_INT_EN,PME Interrupt Enable. When set this bit enables PME interrupt generation upon receipt of a PME Message as reflected in the PME Status bit (for more details see Table 7-29 of PCI Express Base Specification). A PME interrupt is also.." "0,1" bitfld.long 0x1C 2. "PCIE_CAP_SYS_ERR_ON_FATAL_ERR_EN,System Error on Fatal Error Enable. If set this bit indicates that a System Error should be generated if a Fatal error (ERR_FATAL) is reported by any of the devices in the Hierarchy Domain associated with this Root Port.." "0,1" newline bitfld.long 0x1C 1. "PCIE_CAP_SYS_ERR_ON_NON_FATAL_ERR_EN,System Error on Non-Fatal Error Enable. If set this bit indicates that a System Error should be generated if a Non-fatal error (ERR_NONFATAL) is reported by any of the devices in the Hierarchy Domain associated with.." "0,1" bitfld.long 0x1C 0. "PCIE_CAP_SYS_ERR_ON_CORR_ERR_EN,System Error on Correctable Error Enable. If set this bit indicates that a System Error should be generated if a correctable error (ERR_COR) is reported by any of the devices in the Hierarchy Domain associated with this.." "0,1" line.long 0x20 "ROOT_STATUS_REG,Root Status Register. The Root Status register provides information about PCI Express device specific parameters." hexmask.long.word 0x20 18.--31. 1. "RSVDP_18,Reserved for future use." rbitfld.long 0x20 17. "PCIE_CAP_PME_PENDING,PME Pending. This bit indicates that another PME is pending when the PME Status bit is s et. When the PME Status bit is cleared by software; the PME is delivered by hardware by setting the PME Status bit again and updating the PME.." "0,1" newline bitfld.long 0x20 16. "PCIE_CAP_PME_STATUS,PME Status. This bit indicates that PME was asserted by the PME Requester indicated in the PME Requester ID field. Subsequent PMEs are kept pending until the status register is cleared by software by writing a 1b." "0,1" hexmask.long.word 0x20 0.--15. 1. "PCIE_CAP_PME_REQ_ID,PME Requester ID. This field indicates the PCI Requester ID of the last PME Requester. This field is only valid when the PME Status bit is set." line.long 0x24 "DEVICE_CAPABILITIES2_REG,Device Capabilities 2 Register." bitfld.long 0x24 31. "PCIE_CAP_FRS_SUPPORTED,FRS Supported. When set indicates support for the optional Function Readiness Status (FRS) capability. Must be set for all Functions that support generation or reception capabilities of FRS Messages. Must not be set by Switch.." "0,1" hexmask.long.byte 0x24 24.--30. 1. "RSVDP_24,Reserved for future use." newline bitfld.long 0x24 22.--23. "PCIE_CAP2_CFG_MAX_END2END_TLP_PRFXS,Max End-End TLP Prefixes. Indicates the maximum number of End-End TLP Prefixes supported by this Function. For more details see Section 2.2.10.2 of PCI Express Base Specification. Values are: - 01b: 1 End-End TLP.." "0,1,2,3" bitfld.long 0x24 21. "PCIE_CAP2_CFG_END2END_TLP_PRFX_SUPPORT,End-End TLP Prefix Supported. Indicates whether End-End TLP Prefix support is offered by a Function. Values are: - 0b: No Support - 1b: Support is provided to receive TLPs containing End-End TLP Prefixes. All Ports.." "0,1" newline bitfld.long 0x24 20. "PCIE_CAP2_CFG_EXTND_FMT_SUPPORT,Extended Fmt Field Supported. If set the Function supports the 3-bit definition of the Fmt field. If clear the Function supports a 2-bit definition of the Fmt field. For more details see section 2.2 of PCI Express Base.." "0,1" rbitfld.long 0x24 17. "PCIE_CAP2_10_BIT_TAG_REQ_SUPPORT,10-Bit Tag Requester Supported. If this bit is set the Function supports 10-Bit Tag Requester capability; otherwise the Function does not. This bit must not be set if the 10-Bit Tag Completer Supported bit is clear." "0,1" newline rbitfld.long 0x24 16. "PCIE_CAP2_10_BIT_TAG_COMP_SUPPORT,10-Bit Tag Completer Supported. If this bit is set the Function supports 10-Bit Tag Completer capability; otherwise the Function does not. For more details see section 2.2.6.2. of PCI Express Base Specification." "0,1" rbitfld.long 0x24 13. "PCIE_CAP_TPH_CMPLT_SUPPORT_1,TPH Completer Supported Bit 1." "0,1" newline rbitfld.long 0x24 12. "PCIE_CAP_TPH_CMPLT_SUPPORT_0,TPH Completer Supported Bit 0. Value of this bit along with TPH Completer Supported Bit 1 indicates Completer support for TPH or Extended TPH. Applicable only to Root Ports and Endpoints. For all other Functions this field.." "0,1" bitfld.long 0x24 11. "PCIE_CAP_LTR_SUPP,LTR Mechanism Supported. A value of 1b indicates support for the optional Latency Tolerance Reporting (LTR) mechanism. Root Ports Switches and Endpoints are permitted to implement this capability. For a Multi-Function Device associated.." "0,1" newline rbitfld.long 0x24 10. "PCIE_CAP_NO_RO_EN_PR2PR_PAR,No RO-enabled PR-PR Passing. If this bit is set the routing element never carries out the passing permitted by Table 2-39 of PCI Express Base Specification entry A2b that is associated with the Relaxed Ordering Attribute.." "0,1" rbitfld.long 0x24 9. "PCIE_CAP_128_CAS_CPL_SUPP,128-bit CAS Completer Supported. Applicable to Functions with Memory Space BARs as well as all Root Ports; must be 0b otherwise. This bit must be set to 1b if the Function supports this optional capability. For more details see.." "0,1" newline rbitfld.long 0x24 8. "PCIE_CAP_64_ATOMIC_CPL_SUPP,64-bit AtomicOp Completer Supported. Applicable to Functions with Memory Space BARs as well as all Root Ports; must be 0b otherwise. Includes FetchAdd Swap and CAS AtomicOps. This bit must be set to 1b if the Function.." "0,1" rbitfld.long 0x24 7. "PCIE_CAP_32_ATOMIC_CPL_SUPP,32-bit AtomicOp Completer Supported. Applicable to Functions with Memory Space BARs as well as all Root Ports; must be 0b otherwise. Includes FetchAdd Swap and CAS AtomicOps. This bit must be set to 1b if the Function.." "0,1" newline rbitfld.long 0x24 6. "PCIE_CAP_ATOMIC_ROUTING_SUPP,AtomicOp Routing Supported. Applicable only to Switch Upstream Ports Switch Downstream Ports and Root Ports; must be 0b for other Function types. This bit must be set to 1b if the Port supports this optional capability. For.." "0,1" rbitfld.long 0x24 5. "PCIE_CAP_ARI_FORWARD_SUPPORT,ARI Forwarding Supported. Applicable only to Switch Downstream Ports and Root Ports; must be 0b for other Function types. This bit must be set to 1b if a Switch Downstream Port or Root Port supports this optional capability." "0,1" newline rbitfld.long 0x24 4. "PCIE_CAP_CPL_TIMEOUT_DISABLE_SUPPORT,Completion Timeout Disable Supported. A value of 1b indicates support for the Completion Timeout Disable mechanism. The Completion Timeout Disable mechanism is required for Endpoints that issue Requests on their own.." "0,1" hexmask.long.byte 0x24 0.--3. 1. "PCIE_CAP_CPL_TIMEOUT_RANGE,Completion Timeout Ranges Supported. This field indicates device Function support for the optional Completion Timeout programmability mechanism. This mechanism allows system software to modify the Completion Timeout value. This.." line.long 0x28 "DEVICE_CONTROL2_DEVICE_STATUS2_REG,Device Control 2 and Status 2 Register." hexmask.long.word 0x28 16.--31. 1. "RSVDP_16,Reserved for future use." bitfld.long 0x28 15. "PCIE_CTRL2_CFG_END2END_TLP_PFX_BLCK,End-End TLP Prefix Blocking. Controls whether the routing function is permitted to forward TLPs containing an End-End TLP Prefix. Values are: - 0b: Forwarding Enabled - Function is permitted to send TLPs with End-End.." "0,1" newline rbitfld.long 0x28 11. "RSVDP_11,Reserved for future use." "0,1" bitfld.long 0x28 10. "PCIE_CAP_LTR_EN,LTR Mechanism Enable. When set to 1b this bit enables Upstream Ports to send LTR messages and Downstream Ports to process LTR Messages. For a Multi-Function Device associated with an Upstream Port of a device that implements LTR the bit.." "0,1" newline rbitfld.long 0x28 5. "PCIE_CAP_ARI_FORWARD_SUPPORT_CS,ARI Forwarding Enable. When set the Downstream Port disables its traditional Device Number field being 0 enforcement when turning a Type 1 Configuration Request into a Type 0 Configuration Request permitting access to.." "0,1" bitfld.long 0x28 4. "PCIE_CAP_CPL_TIMEOUT_DISABLE,Completion Timeout Disable. When set this bit disables the Completion Timeout mechanism. This bit is required for all Functions that support the Completion Timeout Disable Capability. Functions that do not support this.." "0,1" newline hexmask.long.byte 0x28 0.--3. 1. "PCIE_CAP_CPL_TIMEOUT_VALUE,Completion Timeout Value. In device Functions that support Completion Timeout programmability this field allows system software to modify the Completion Timeout value. This field is applicable to Root Ports Endpoints that.." line.long 0x2C "LINK_CAPABILITIES2_REG,Link Capabilities 2 Register." bitfld.long 0x2C 31. "DRS_SUPPORTED,DRS Supported. When set indicates support for the optional Device Readiness Status (DRS) capability. Must be Set in Downstream Ports that support DRS. Must be Set in Downstream Ports that support FRS. For Upstream Ports that support DRS.." "0,1" hexmask.long.byte 0x2C 25.--30. 1. "RSVDP_25,Reserved for future use." newline hexmask.long.word 0x2C 9.--22. 1. "RSVDP_9,Reserved for future use." rbitfld.long 0x2C 8. "PCIE_CAP_CROSS_LINK_SUPPORT,Crosslink Supported. When set to 1b this bit indicates that the associated Port supports crosslinks (for more details see section 4.2.6.3.1 of PCI Express Base Specification). When set to 0b on a Port that supports Link.." "0,1" newline hexmask.long.byte 0x2C 1.--7. 1. "PCIE_CAP_SUPPORT_LINK_SPEED_VECTOR,Supported Link Speeds Vector. This field indicates the supported Link speed(s) of the associated Port. For each bit a value of 1b indicates that the corresponding Link speed is supported; otherwise the Link speed is.." rbitfld.long 0x2C 0. "RSVDP_0,Reserved for future use." "0,1" line.long 0x30 "LINK_CONTROL2_LINK_STATUS2_REG,Link Control 2 and Status 2 Register." bitfld.long 0x30 31. "DRS_MESSAGE_RECEIVED,DRS Message Received. This bit must be set whenever the Port receives a DRS Message. This bit must be cleared in DL_Down. This bit must be implemented in any Downstream Port where the DRS Supported bit is Set in the Link Capabilities.." "0,1" rbitfld.long 0x30 28.--30. "DOWNSTREAM_COMPO_PRESENCE,Downstream Component Presence. This field indicates the presence and DRS status for the Downstream Component if any connected to the Link; defined values are: - 000b: Link Down - Presence Not Determined - 001b: Link Down -.." "0,1,2,3,4,5,6,7" newline rbitfld.long 0x30 26.--27. "RSVDP_26,Reserved for future use." "0,1,2,3" bitfld.long 0x30 21. "PCIE_CAP_LINK_EQ_REQ,Link Equalization Request 8.0 GT/s. This bit is set by hardware to request the 8.0 GT/s Link equalization process to be performed on the Link. For more details see sections 4.2.3 and 4.2.6.4.2 of PCI Express Base Specification. For.." "0,1" newline rbitfld.long 0x30 20. "PCIE_CAP_EQ_CPL_P3,EEqualization 8.0 GT/s Phase 3 Successful. When set to 1b this bit indicates that Phase 3 of the 8.0 GT/s Transmitter Equalization procedure has successfully completed. Details of the Transmitter Equalization process and when this bit.." "0,1" rbitfld.long 0x30 19. "PCIE_CAP_EQ_CPL_P2,Equalization 8.0 GT/s Phase 2 Successful. When set to 1b this bit indicates that Phase 2 of the 8.0 GT/s Transmitter Equalization procedure has successfully completed. Details of the Transmitter Equalization process and when this bit.." "0,1" newline rbitfld.long 0x30 18. "PCIE_CAP_EQ_CPL_P1,Equalization 8.0 GT/s Phase 1 Successful. When set to 1b this bit indicates that Phase 1 of the 8.0 GT/s Transmitter Equalization procedure has successfully completed. Details of the Transmitter Equalization process and when this bit.." "0,1" rbitfld.long 0x30 17. "PCIE_CAP_EQ_CPL,Equalization 8.0 GT/s Complete. When set to 1b this bit indicates that the Transmitter Equalization procedure at the 8.0 GT/s data rate has completed. Details of the Transmitter Equalization process and when this bit needs to be set to.." "0,1" newline rbitfld.long 0x30 16. "PCIE_CAP_CURR_DEEMPHASIS,Current De-emphasis Level. When the Link is operating at 5.0 GT/s speed this bit reflects the level of de-emphasis. Encodings: - 1b: -3.5 dB - 0b: -6 dB The value in this bit is undefined when the Link is not operating at 5.0.." "0,1" hexmask.long.byte 0x30 12.--15. 1. "PCIE_CAP_COMPLIANCE_PRESET,Compliance Preset/De-emphasis. For 8.0 GT/s and higher Data Rate: This field sets the Transmitter Preset in Polling.Compliance state if the entry occurred due to the Enter Compliance bit being 1b. The encodings are defined in.." newline bitfld.long 0x30 11. "PCIE_CAP_COMPLIANCE_SOS,Compliance SOS. When set to 1b the LTSSM is required to send SKP Ordered Sets between sequences when sending the Compliance Pattern or Modified Compliance Pattern. For a Multi-Function Device associated with an Upstream Port the.." "0,1" bitfld.long 0x30 10. "PCIE_CAP_ENTER_MODIFIED_COMPLIANCE,Enter Modified Compliance. When this bit is set to 1b the device transmits Modified Compliance Pattern if the LTSSM enters Polling.Compliance substate. Components that support only the 2.5 GT/s speed are permitted to.." "0,1" newline bitfld.long 0x30 7.--9. "PCIE_CAP_TX_MARGIN,Transmit Margin - This field controls the value of the non-deemphasized voltage level at the Transmitter pins. This field is reset to 000b on entry to the LTSSM Polling.Configuration substate (see Chapter 4 of PCI Express Base.." "0,1,2,3,4,5,6,7" bitfld.long 0x30 6. "PCIE_CAP_SEL_DEEMPHASIS,Selectable De-emphasis. When the Link is operating at 5.0 GT/s speed this bit is used to control the transmit de-emphasis of the link in specific situations. For more details see section 4.2.6 of PCI Express Base Specification." "0,1" newline bitfld.long 0x30 5. "PCIE_CAP_HW_AUTO_SPEED_DISABLE,Hardware Autonomous Speed Disable. When set this bit disables hardware from changing the Link speed for device-specific reasons other than attempting to correct unreliable Link operation by reducing Link speed. Initial.." "0,1" bitfld.long 0x30 4. "PCIE_CAP_ENTER_COMPLIANCE,Enter Compliance. Software is permitted to force a Link to enter Compliance mode (at the speed indicated in the Target Link Speed field and the de-emphasis/preset level indicated by the Compliance Preset/De-emphasis field) by.." "0,1" newline hexmask.long.byte 0x30 0.--3. 1. "PCIE_CAP_TARGET_LINK_SPEED,Target Link Speed. For Downstream Ports this field sets an upper limit on Link operational speed by restricting the values advertised by the Upstream component in its training sequences. The encoded value specifies a bit.." tree.end tree "PF0_AER_CAP (PF Advanced Error Reporting Capability Structure)" group.long (0x0+0x100)++0x1B line.long 0x0 "AER_EXT_CAP_HDR_OFF,Advanced Error Reporting Extended Capability Header. For a description of this standard PCIe register. see the PCI Express Specification." hexmask.long.word 0x0 20.--31. 1. "NEXT_OFFSET,Next Capability Offset. For a description of this standard PCIe register field see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky).." hexmask.long.byte 0x0 16.--19. 1. "CAP_VERSION,Capability Version. For a description of this standard PCIe register field see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else.." hexmask.long.word 0x0 0.--15. 1. "CAP_ID,AER Extended Capability ID. For a description of this standard PCIe register field see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else.." line.long 0x4 "UNCORR_ERR_STATUS_OFF,Uncorrectable Error Status Register. For a description of this standard PCIe register. see the PCI Express Specification." hexmask.long.byte 0x4 27.--31. 1. "RSVDP_27,Reserved for future use." bitfld.long 0x4 25. "TLP_PRFX_BLOCKED_ERR_STATUS,TLP Prefix Blocked Error Status. For a description of this standard PCIe register field see the PCI Express Specification. Note: Not supported." "0,1" rbitfld.long 0x4 23. "RSVDP_23,Reserved for future use." "0,1" newline bitfld.long 0x4 22. "INTERNAL_ERR_STATUS,Uncorrectable Internal Error Status. For a description of this standard PCIe register field see the PCI Express Specification. The controller sets this bit when your application asserts app_err_bus[9]. It does not set this bit when.." "0,1" bitfld.long 0x4 20. "UNSUPPORTED_REQ_ERR_STATUS,Unsupported Request Error Status. For a description of this standard PCIe register field see the PCI Express Specification." "0,1" bitfld.long 0x4 19. "ECRC_ERR_STATUS,ECRC Error Status. For a description of this standard PCIe register field see the PCI Express Specification. Note:If CX_ECRC_ENABLE=0 the register field always reads 0." "0,1" newline bitfld.long 0x4 18. "MALF_TLP_ERR_STATUS,Malformed TLP Status. For a description of this standard PCIe register field see the PCI Express Specification." "0,1" bitfld.long 0x4 17. "REC_OVERFLOW_ERR_STATUS,Receiver Overflow Status. For a description of this standard PCIe register field see the PCI Express Specification." "0,1" bitfld.long 0x4 16. "UNEXP_CMPLT_ERR_STATUS,Unexpected Completion Status. For a description of this standard PCIe register field see the PCI Express Specification." "0,1" newline bitfld.long 0x4 15. "CMPLT_ABORT_ERR_STATUS,Completer Abort Status. For a description of this standard PCIe register field see the PCI Express Specification." "0,1" bitfld.long 0x4 14. "CMPLT_TIMEOUT_ERR_STATUS,Completion Timeout Status. For a description of this standard PCIe register field see the PCI Express Specification." "0,1" bitfld.long 0x4 13. "FC_PROTOCOL_ERR_STATUS,Flow Control Protocol Error Status. For a description of this standard PCIe register field see the PCI Express Specification." "0,1" newline bitfld.long 0x4 12. "POIS_TLP_ERR_STATUS,Poisoned TLP Status. For a description of this standard PCIe register field see the PCI Express Specification." "0,1" hexmask.long.byte 0x4 6.--11. 1. "RSVDP_6,Reserved for future use." bitfld.long 0x4 5. "SURPRISE_DOWN_ERR_STATUS,Surprise Down Error Status (Optional). For a description of this standard PCIe register field see the PCI Express Specification." "0,1" newline bitfld.long 0x4 4. "DL_PROTOCOL_ERR_STATUS,Data Link Protocol Error Status. For a description of this standard PCIe register field see the PCI Express Specification." "0,1" hexmask.long.byte 0x4 0.--3. 1. "RSVDP_0,Reserved for future use." line.long 0x8 "UNCORR_ERR_MASK_OFF,Uncorrectable Error Mask Register. For a description of this standard PCIe register. see the PCI Express Specification." hexmask.long.byte 0x8 27.--31. 1. "RSVDP_27,Reserved for future use." bitfld.long 0x8 25. "TLP_PRFX_BLOCKED_ERR_MASK,TLP Prefix Blocked Error Mask. For a description of this standard PCIe register field see the PCI Express Specification. Note: Not supported. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi:.." "0,1" rbitfld.long 0x8 23. "RSVDP_23,Reserved for future use." "0,1" newline bitfld.long 0x8 22. "INTERNAL_ERR_MASK,Uncorrectable Internal Error Mask (Optional). For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." "0,1" rbitfld.long 0x8 21. "ACS_VIOLATION_MASK,ACS Violation Mask. Setting the ACS Violation Mask bit disables error logging and signaling for ACS Violation errors. The bit is Read-Only Zero for upstream ports when ACS P2P Egress Control Enable is not set. For a description of.." "0,1" bitfld.long 0x8 20. "UNSUPPORTED_REQ_ERR_MASK,Unsupported Request Error Mask. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." "0,1" newline bitfld.long 0x8 19. "ECRC_ERR_MASK,ECRC Error Mask (Optional). For a description of this standard PCIe register field see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W (sticky) Note: This register.." "0,1" bitfld.long 0x8 18. "MALF_TLP_ERR_MASK,Malformed TLP Mask. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." "0,1" bitfld.long 0x8 17. "REC_OVERFLOW_ERR_MASK,Receiver Overflow Mask (Optional). For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." "0,1" newline bitfld.long 0x8 16. "UNEXP_CMPLT_ERR_MASK,Unexpected Completion Mask. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." "0,1" bitfld.long 0x8 15. "CMPLT_ABORT_ERR_MASK,Completer Abort Error Mask (Optional). For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." "0,1" bitfld.long 0x8 14. "CMPLT_TIMEOUT_ERR_MASK,Completion Timeout Error Mask. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." "0,1" newline bitfld.long 0x8 13. "FC_PROTOCOL_ERR_MASK,Flow Control Protocol Error Mask. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." "0,1" bitfld.long 0x8 12. "POIS_TLP_ERR_MASK,Poisoned TLP Error Mask. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." "0,1" hexmask.long.byte 0x8 6.--11. 1. "RSVDP_6,Reserved for future use." newline rbitfld.long 0x8 5. "SURPRISE_DOWN_ERR_MASK,Surprise Down Error Mask. For a description of this standard PCIe register field see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi:.." "0,1" bitfld.long 0x8 4. "DL_PROTOCOL_ERR_MASK,Data Link Protocol Error Mask. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." "0,1" hexmask.long.byte 0x8 0.--3. 1. "RSVDP_0,Reserved for future use." line.long 0xC "UNCORR_ERR_SEV_OFF,Uncorrectable Error Severity Register. For a description of this standard PCIe register. see the PCI Express Specification." hexmask.long.byte 0xC 27.--31. 1. "RSVDP_27,Reserved for future use." bitfld.long 0xC 25. "TLP_PRFX_BLOCKED_ERR_SEVERITY,TLP Prefix Blocked Error Severity (Optional). For a description of this standard PCIe register field see the PCI Express Specification. Note: Not supported. Note: The access attributes of this field are as follows: - Wire:.." "0,1" rbitfld.long 0xC 24. "ATOMIC_EGRESS_BLOCKED_ERR_SEVERITY,AtomicOp Egress Blocked Severity (Optional). For a description of this standard PCIe register field see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi:.." "0,1" newline rbitfld.long 0xC 23. "RSVDP_23,Reserved for future use." "0,1" bitfld.long 0xC 22. "INTERNAL_ERR_SEVERITY,Uncorrectable Internal Error Severity (Optional). For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." "0,1" bitfld.long 0xC 20. "UNSUPPORTED_REQ_ERR_SEVERITY,Unsupported Request Error Severity. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." "0,1" newline bitfld.long 0xC 19. "ECRC_ERR_SEVERITY,ECRC Error Severity (Optional). For a description of this standard PCIe register field see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W (sticky) Note: This.." "0,1" bitfld.long 0xC 18. "MALF_TLP_ERR_SEVERITY,Malformed TLP Severity. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." "0,1" bitfld.long 0xC 17. "REC_OVERFLOW_ERR_SEVERITY,Receiver Overflow Error Severity (Optional). For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." "0,1" newline bitfld.long 0xC 16. "UNEXP_CMPLT_ERR_SEVERITY,Unexpected Completion Error Severity. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." "0,1" bitfld.long 0xC 15. "CMPLT_ABORT_ERR_SEVERITY,Completer Abort Error Severity (Optional). For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." "0,1" bitfld.long 0xC 14. "CMPLT_TIMEOUT_ERR_SEVERITY,Completion Timeout Error Severity. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." "0,1" newline bitfld.long 0xC 13. "FC_PROTOCOL_ERR_SEVERITY,Flow Control Protocol Error Severity (Optional). For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." "0,1" bitfld.long 0xC 12. "POIS_TLP_ERR_SEVERITY,Poisoned TLP Severity. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." "0,1" hexmask.long.byte 0xC 6.--11. 1. "RSVDP_6,Reserved for future use." newline rbitfld.long 0xC 5. "SURPRISE_DOWN_ERR_SVRITY,Surprise Down Error Severity (Optional). For a description of this standard PCIe register field see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi:.." "0,1" bitfld.long 0xC 4. "DL_PROTOCOL_ERR_SEVERITY,Data Link Protocol Error Severity. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." "0,1" hexmask.long.byte 0xC 0.--3. 1. "RSVDP_0,Reserved for future use." line.long 0x10 "CORR_ERR_STATUS_OFF,Correctable Error Status Register. For a description of this standard PCIe register. see the PCI Express Specification." hexmask.long.word 0x10 16.--31. 1. "RSVDP_16,Reserved for future use." bitfld.long 0x10 15. "HEADER_LOG_OVERFLOW_STATUS,Header Log Overflow Error Status (Optional). For a description of this standard PCIe register field see the PCI Express Specification." "0,1" bitfld.long 0x10 14. "CORRECTED_INT_ERR_STATUS,Corrected Internal Error Status (Optional). For a description of this standard PCIe register field see the PCI Express Specification." "0,1" newline bitfld.long 0x10 13. "ADVISORY_NON_FATAL_ERR_STATUS,Advisory Non-Fatal Error Status. For a description of this standard PCIe register field see the PCI Express Specification." "0,1" bitfld.long 0x10 12. "RPL_TIMER_TIMEOUT_STATUS,Replay Timer Timeout Status. For a description of this standard PCIe register field see the PCI Express Specification." "0,1" rbitfld.long 0x10 9.--11. "RSVDP_9,Reserved for future use." "0,1,2,3,4,5,6,7" newline bitfld.long 0x10 8. "REPLAY_NO_ROLEOVER_STATUS,REPLAY_NUM Rollover Status. For a description of this standard PCIe register field see the PCI Express Specification." "0,1" bitfld.long 0x10 7. "BAD_DLLP_STATUS,Bad DLLP Status. For a description of this standard PCIe register field see the PCI Express Specification." "0,1" bitfld.long 0x10 6. "BAD_TLP_STATUS,Bad TLP Status. For a description of this standard PCIe register field see the PCI Express Specification." "0,1" newline hexmask.long.byte 0x10 1.--5. 1. "RSVDP_1,Reserved for future use." bitfld.long 0x10 0. "RX_ERR_STATUS,Receiver Error Status (Optional). For a description of this standard PCIe register field see the PCI Express Specification." "0,1" line.long 0x14 "CORR_ERR_MASK_OFF,Correctable Error Mask Register. For a description of this standard PCIe register. see the PCI Express Specification." hexmask.long.word 0x14 16.--31. 1. "RSVDP_16,Reserved for future use." bitfld.long 0x14 15. "HEADER_LOG_OVERFLOW_MASK,Header Log Overflow Error Mask (Optional). For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." "0,1" bitfld.long 0x14 14. "CORRECTED_INT_ERR_MASK,Corrected Internal Error Mask (Optional). For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." "0,1" newline bitfld.long 0x14 13. "ADVISORY_NON_FATAL_ERR_MASK,Advisory Non-Fatal Error Mask. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." "0,1" bitfld.long 0x14 12. "RPL_TIMER_TIMEOUT_MASK,Replay Timer Timeout Mask. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." "0,1" rbitfld.long 0x14 9.--11. "RSVDP_9,Reserved for future use." "0,1,2,3,4,5,6,7" newline bitfld.long 0x14 8. "REPLAY_NO_ROLEOVER_MASK,REPLAY_NUM Rollover Mask. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." "0,1" bitfld.long 0x14 7. "BAD_DLLP_MASK,Bad DLLP Mask. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." "0,1" bitfld.long 0x14 6. "BAD_TLP_MASK,Bad TLP Mask. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." "0,1" newline hexmask.long.byte 0x14 1.--5. 1. "RSVDP_1,Reserved for future use." bitfld.long 0x14 0. "RX_ERR_MASK,Receiver Error Mask (Optional). For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." "0,1" line.long 0x18 "ADV_ERR_CAP_CTRL_OFF,Advanced Error Capabilities and Control Register. For a description of this standard PCIe register. see the PCI Express Specification." hexmask.long.tbyte 0x18 13.--31. 1. "RSVDP_13,Reserved for future use." rbitfld.long 0x18 12. "CTO_PRFX_HDR_LOG_CAP,TLP Prefix Log Present. For a description of this standard PCIe register field see the PCI Express Specification." "0,1" rbitfld.long 0x18 11. "TLP_PRFX_LOG_PRESENT,Completion Timeout Prefix/Header Log Capable. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." "0,1" newline rbitfld.long 0x18 10. "MULTIPLE_HEADER_EN,Multiple Header Recording Enable. For a description of this standard PCIe register field see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R (sticky) Note: This.." "0,1" rbitfld.long 0x18 9. "MULTIPLE_HEADER_CAP,Multiple Header Recording Capable. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." "0,1" bitfld.long 0x18 8. "ECRC_CHECK_EN,ECRC Check Enable. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." "0,1" newline rbitfld.long 0x18 7. "ECRC_CHECK_CAP,ECRC Check Capable. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." "0,1" bitfld.long 0x18 6. "ECRC_GEN_EN,ECRC Generation Enable. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." "0,1" rbitfld.long 0x18 5. "ECRC_GEN_CAP,ECRC Generation Capable. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." "0,1" newline hexmask.long.byte 0x18 0.--4. 1. "FIRST_ERR_POINTER,First Error Pointer. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." rgroup.long (0x1C+0x100)++0xF line.long 0x0 "HDR_LOG_0_OFF,Header Log Register 0. For a description of this standard PCIe register. see the PCI Express Specification." hexmask.long.byte 0x0 24.--31. 1. "FIRST_DWORD_FOURTH_BYTE,Byte 3 of Header log register of First 32 bit Data Word. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." hexmask.long.byte 0x0 16.--23. 1. "FIRST_DWORD_THIRD_BYTE,Byte 2 of Header log register of First 32 bit Data Word. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." hexmask.long.byte 0x0 8.--15. 1. "FIRST_DWORD_SECOND_BYTE,Byte 1 of Header log register of First 32 bit Data Word. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." newline hexmask.long.byte 0x0 0.--7. 1. "FIRST_DWORD_FIRST_BYTE,Byte 0 of Header log register of First 32 bit Data Word. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." line.long 0x4 "HDR_LOG_1_OFF,Header Log Register 1. For a description of this standard PCIe register. see the PCI Express Specification." hexmask.long.byte 0x4 24.--31. 1. "SECOND_DWORD_FOURTH_BYTE,Byte 3 of Header log register of Second 32 bit Data Word. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." hexmask.long.byte 0x4 16.--23. 1. "SECOND_DWORD_THIRD_BYTE,Byte 2 of Header log register of Second 32 bit Data Word. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." hexmask.long.byte 0x4 8.--15. 1. "SECOND_DWORD_SECOND_BYTE,Byte 1 of Header log register of Second 32 bit Data Word. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." newline hexmask.long.byte 0x4 0.--7. 1. "SECOND_DWORD_FIRST_BYTE,Byte 0 of Header log register of Second 32 bit Data Word. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." line.long 0x8 "HDR_LOG_2_OFF,Header Log Register 2. For a description of this standard PCIe register. see the PCI Express Specification." hexmask.long.byte 0x8 24.--31. 1. "THIRD_DWORD_FOURTH_BYTE,Byte 3 of Header log register of Third 32 bit Data Word. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." hexmask.long.byte 0x8 16.--23. 1. "THIRD_DWORD_THIRD_BYTE,Byte 2 of Header log register of Third 32 bit Data Word. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." hexmask.long.byte 0x8 8.--15. 1. "THIRD_DWORD_SECOND_BYTE,Byte 1 of Header log register of Third 32 bit Data Word. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." newline hexmask.long.byte 0x8 0.--7. 1. "THIRD_DWORD_FIRST_BYTE,Byte 0 of Header log register of Third 32 bit Data Word. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." line.long 0xC "HDR_LOG_3_OFF,Header Log Register 3. For a description of this standard PCIe register. see the PCI Express Specification." hexmask.long.byte 0xC 24.--31. 1. "FOURTH_DWORD_FOURTH_BYTE,Byte 3 of Header log register of Fourth 32 bit Data Word. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." hexmask.long.byte 0xC 16.--23. 1. "FOURTH_DWORD_THIRD_BYTE,Byte 2 of Header log register of Fourth 32 bit Data Word. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." hexmask.long.byte 0xC 8.--15. 1. "FOURTH_DWORD_SECOND_BYTE,Byte 1 of Header log register of Fourth 32 bit Data Word. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." newline hexmask.long.byte 0xC 0.--7. 1. "FOURTH_DWORD_FIRST_BYTE,Byte 0 of Header log register of Fourth 32 bit Data Word. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." group.long (0x2C+0x100)++0x7 line.long 0x0 "ROOT_ERR_CMD_OFF,Root Error Command Register. For a description of this standard PCIe register. see the PCI Express Specification." hexmask.long 0x0 3.--31. 1. "RSVDP_3,Reserved for future use." bitfld.long 0x0 2. "FATAL_ERR_REPORTING_EN,Fatal Error Reporting Enable. For a description of this standard PCIe register field see the PCI Express Specification." "0,1" bitfld.long 0x0 1. "NON_FATAL_ERR_REPORTING_EN,Non-Fatal Error Reporting Enable. For a description of this standard PCIe register field see the PCI Express Specification." "0,1" newline bitfld.long 0x0 0. "CORR_ERR_REPORTING_EN,Correctable Error Reporting Enable. For a description of this standard PCIe register field see the PCI Express Specification." "0,1" line.long 0x4 "ROOT_ERR_STATUS_OFF,Root Error Status Register. For a description of this standard PCIe register. see the PCI Express Specification." hexmask.long.byte 0x4 27.--31. 1. "ADV_ERR_INT_MSG_NUM,Advanced Error Interrupt Message Number. For a description of this standard PCIe register field see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN.." hexmask.long.tbyte 0x4 7.--26. 1. "RSVDP_7,Reserved for future use." bitfld.long 0x4 6. "FATAL_ERR_MSG_RX,One or more Fatal Error Messages Received. For a description of this standard PCIe register field see the PCI Express Specification." "0,1" newline bitfld.long 0x4 5. "NON_FATAL_ERR_MSG_RX,One or more Non-Fatal Error Messages Received. For a description of this standard PCIe register field see the PCI Express Specification." "0,1" bitfld.long 0x4 4. "FIRST_UNCORR_FATAL,First Uncorrectable Error is Fatal. For a description of this standard PCIe register field see the PCI Express Specification." "0,1" bitfld.long 0x4 3. "MUL_ERR_FATAL_NON_FATAL_RX,Multiple Fatal or Non-Fatal Errors Received. For a description of this standard PCIe register field see the PCI Express Specification." "0,1" newline bitfld.long 0x4 2. "ERR_FATAL_NON_FATAL_RX,Fatal or Non-Fatal Error Received. For a description of this standard PCIe register field see the PCI Express Specification." "0,1" bitfld.long 0x4 1. "MUL_ERR_COR_RX,Multiple Correctable Errors Received. For a description of this standard PCIe register field see the PCI Express Specification." "0,1" bitfld.long 0x4 0. "ERR_COR_RX,Correctable Error Received. For a description of this standard PCIe register field see the PCI Express Specification." "0,1" rgroup.long (0x34+0x100)++0x13 line.long 0x0 "ERR_SRC_ID_OFF,Error Source Identification Register. For a description of this standard PCIe register. see the PCI Express Specification." hexmask.long.word 0x0 16.--31. 1. "ERR_FATAL_NON_FATAL_SOURCE_ID,Source of Fatal/Non-Fatal Error. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." hexmask.long.word 0x0 0.--15. 1. "ERR_COR_SOURCE_ID,Source of Correctable Error. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." line.long 0x4 "TLP_PREFIX_LOG_1_OFF,TLP Prefix Log Register 1. For a description of this standard PCIe register. see the PCI Express Specification." hexmask.long.byte 0x4 24.--31. 1. "CFG_TLP_PFX_LOG_1_FOURTH_BYTE,Byte 3 of Error TLP Prefix Log 1. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." hexmask.long.byte 0x4 16.--23. 1. "CFG_TLP_PFX_LOG_1_THIRD_BYTE,Byte 2 of Error TLP Prefix Log 1. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." hexmask.long.byte 0x4 8.--15. 1. "CFG_TLP_PFX_LOG_1_SECOND_BYTE,Byte 1 of Error TLP Prefix Log 1. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." newline hexmask.long.byte 0x4 0.--7. 1. "CFG_TLP_PFX_LOG_1_FIRST_BYTE,Byte 0 of Error TLP Prefix Log 1. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." line.long 0x8 "TLP_PREFIX_LOG_2_OFF,TLP Prefix Log Register 2. For a description of this standard PCIe register. see the PCI Express Specification." hexmask.long.byte 0x8 24.--31. 1. "CFG_TLP_PFX_LOG_2_FOURTH_BYTE,Byte 3 Error TLP Prefix Log 2. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." hexmask.long.byte 0x8 16.--23. 1. "CFG_TLP_PFX_LOG_2_THIRD_BYTE,Byte 2 Error TLP Prefix Log 2. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." hexmask.long.byte 0x8 8.--15. 1. "CFG_TLP_PFX_LOG_2_SECOND_BYTE,Byte 1 Error TLP Prefix Log 2. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." newline hexmask.long.byte 0x8 0.--7. 1. "CFG_TLP_PFX_LOG_2_FIRST_BYTE,Byte 0 Error TLP Prefix Log 2. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." line.long 0xC "TLP_PREFIX_LOG_3_OFF,TLP Prefix Log Register 3. For a description of this standard PCIe register. see the PCI Express Specification." hexmask.long.byte 0xC 24.--31. 1. "CFG_TLP_PFX_LOG_3_FOURTH_BYTE,Byte 3 Error TLP Prefix Log 3. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." hexmask.long.byte 0xC 16.--23. 1. "CFG_TLP_PFX_LOG_3_THIRD_BYTE,Byte 2 Error TLP Prefix Log 3. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." hexmask.long.byte 0xC 8.--15. 1. "CFG_TLP_PFX_LOG_3_SECOND_BYTE,Byte 1 Error TLP Prefix Log 3. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." newline hexmask.long.byte 0xC 0.--7. 1. "CFG_TLP_PFX_LOG_3_FIRST_BYTE,Byte 0 Error TLP Prefix Log 3. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." line.long 0x10 "TLP_PREFIX_LOG_4_OFF,TLP Prefix Log Register 4. For a description of this standard PCIe register. see the PCI Express Specification." hexmask.long.byte 0x10 24.--31. 1. "CFG_TLP_PFX_LOG_4_FOURTH_BYTE,Byte 3 Error TLP Prefix Log 4. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." hexmask.long.byte 0x10 16.--23. 1. "CFG_TLP_PFX_LOG_4_THIRD_BYTE,Byte 2 Error TLP Prefix Log 4. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." hexmask.long.byte 0x10 8.--15. 1. "CFG_TLP_PFX_LOG_4_SECOND_BYTE,Byte 1 Error TLP Prefix Log 4. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." newline hexmask.long.byte 0x10 0.--7. 1. "CFG_TLP_PFX_LOG_4_FIRST_BYTE,Byte 0 Error TLP Prefix Log 4. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." tree.end tree "PF0_MSI_CAP (PF MSI Capability Structure)" group.long (0x0+0x50)++0x13 line.long 0x0 "PCI_MSI_CAP_ID_NEXT_CTRL_REG,MSI Capability Header and Message Control Register." hexmask.long.byte 0x0 27.--31. 1. "RSVDP_27,Reserved for future use." bitfld.long 0x0 26. "PCI_MSI_EXT_DATA_EN,Extended Message Data Enable. - If set the function is enabled to provide Extended Message Data. - If clear the function is not enabled to provide Extended Message Data. Note: The access attributes of this field are as follows: -.." "0,1" bitfld.long 0x0 25. "PCI_MSI_EXT_DATA_CAP,Extended Message Data Capable. - If set the function is capable of providing Extended Message Data. - If clear the function does not support providing Extended Message Data. Note: The access attributes of this field are as follows:.." "0,1" newline rbitfld.long 0x0 24. "PCI_PVM_SUPPORT,Per-Vector Masking Capable. - If set the function supports MSI Per-Vector Masking. - If clear the function does not support MSI Per-Vector Masking. This bit must be set if the function is a PF or VF within an SR-IOV Device." "0,1" bitfld.long 0x0 23. "PCI_MSI_64_BIT_ADDR_CAP,64 bit address capable. - If set the function is capable of sending a 64-bit message address. - If clear the function is not capable of sending a 64-bit message address. This bit must be set if the function is a PCI Express.." "0,1" bitfld.long 0x0 20.--22. "PCI_MSI_MULTIPLE_MSG_EN,Multiple Message Enable. Software writes to this field to indicate the number of allocated vectors (equal to or less than the number of requested vectors). The number of allocated vectors is aligned to a power of two. If a.." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 17.--19. "PCI_MSI_MULTIPLE_MSG_CAP,Multiple Message Capable. System software reads this field to determine the number of requested vectors. The number of requested vectors must be aligned to a power of two (if a function requires three vectors it requests four by.." "0,1,2,3,4,5,6,7" bitfld.long 0x0 16. "PCI_MSI_ENABLE,MSI Enable. - If set and the MSI-X Enable bit in the MSI-X Message Control register is clear the function is permitted to use MSI to request service and is prohibited from using INTx interrupts. System configuration software sets this bit.." "0,1" hexmask.long.byte 0x0 8.--15. 1. "PCI_MSI_CAP_NEXT_OFFSET,Next Capability Pointer. This field contains the offset to the next PCI Capability structure or 00h if no other items exist in the linked list of Capabilities. Note: The access attributes of this field are as follows: - Wire: No.." newline hexmask.long.byte 0x0 0.--7. 1. "PCI_MSI_CAP_ID,Capability ID. Indicates the MSI Capability structure. This field returns a Capability ID of 05h indicating that this is an MSI Capability structure." line.long 0x4 "MSI_CAP_OFF_04H_REG,Message Address Register for MSI (Offset 04h)." hexmask.long 0x4 2.--31. 1. "PCI_MSI_CAP_OFF_04H,Message Address - System-specified message address. If the Message Enable bit (bit 16 of the PCI_MSI_CAP_ID_NEXT_CTRL_REG register) is set the contents of this field specify the DWORD-aligned address (Address[31:02]) for the MSI.." rbitfld.long 0x4 0.--1. "RSVDP_0,Reserved for future use." "0,1,2,3" line.long 0x8 "MSI_CAP_OFF_08H_REG,For a function that supports a 32-bit message address. - bits[31:16] of this register represent the Extended Message Data. and - bits[15:0] of this register represent the Message Data For a function that supports a 64-bit message.." hexmask.long.word 0x8 16.--31. 1. "PCI_MSI_CAP_OFF_0AH,For a function that supports a 32-bit message address this field contains Extended Message Data (System-specified message data). For the MSI Capability structures without per-vector masking it must be implemented if the Extended.." hexmask.long.word 0x8 0.--15. 1. "PCI_MSI_CAP_OFF_08H,For a function that supports a 32-bit message address this field contains Message Data (System-specified message data). If the Message Enable bit (bit 16 of the PCI_MSI_CAP_ID_NEXT_CTRL_REG) is set the function sends a DWORD Memory.." line.long 0xC "MSI_CAP_OFF_0CH_REG,For a function that supports a 32-bit message address. this register contains the Mask Bits when the Per-Vector Masking Capable bit (bit 24 of PCI_MSI_CAP_ID_NEXT_CTRL_REG) is set. For a function that supports a 64-bit message.." hexmask.long.word 0xC 16.--31. 1. "PCI_MSI_CAP_OFF_0EH,For a function that supports a 32-bit message address this field contains the upper Mask Bits when the Per Vector Masking Capable bit (PCI_MSI_CAP_ID_NEXT_CTRL_REG.PCI_PVM_SUPPORT) is set. For a function that supports a 64-bit.." hexmask.long.word 0xC 0.--15. 1. "PCI_MSI_CAP_OFF_0CH,For a function that supports a 32-bit message address this field contains the lower Mask Bits when the Per Vector Masking Capable bit (PCI_MSI_CAP_ID_NEXT_CTRL_REG.PCI_PVM_SUPPORT) is set. For a function that supports a 64-bit.." line.long 0x10 "MSI_CAP_OFF_10H_REG,For a function that supports a 32-bit message address. this register contains the Pending Bits when the Per-Vector Masking Capable bit (bit 24 of PCI_MSI_CAP_ID_NEXT_CTRL_REG) is set. For a function that supports a 64-bit message.." hexmask.long 0x10 0.--31. 1. "PCI_MSI_CAP_OFF_10H,Used for MSI when the Per Vector Masking Capable bit (PCI_MSI_CAP_ID_NEXT_CTRL_REG.PCI_PVM_SUPPORT) is set. For 32-bit contains Pending Bits. For 64-bit contains Mask Bits. For a description of this standard PCIe register field see.." rgroup.long (0x14+0x50)++0x3 line.long 0x0 "MSI_CAP_OFF_14H_REG,Pending Bits Register for MSI. This register is used for a function that supports a 64-bit message address when the Per-Vector Masking Capable bit (bit 24 of PCI_MSI_CAP_ID_NEXT_CTRL_REG) is set." hexmask.long 0x0 0.--31. 1. "PCI_MSI_CAP_OFF_14H,Pending Bits. For each pending bit that is set the function has a pending associated message." tree.end tree "PF0_MSIX_CAP (PF MSI-X Capability Structure)" group.long (0x0+0xB0)++0xB line.long 0x0 "PCI_MSIX_CAP_ID_NEXT_CTRL_REG,MSI-X Capability ID. Next Pointer. Control Registers. For a description of this standard PCIe register. see the PCI Express Base Specification." bitfld.long 0x0 31. "PCI_MSIX_ENABLE,MSI-X Enable. For a description of this standard PCIe register field see the PCI Express Base Specification." "0,1" bitfld.long 0x0 30. "PCI_MSIX_FUNCTION_MASK,Function Mask. For a description of this standard PCIe register field see the PCI Express Base Specification. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" "0,1" rbitfld.long 0x0 27.--29. "RSVDP_27,Reserved for future use." "0,1,2,3,4,5,6,7" newline hexmask.long.word 0x0 16.--26. 1. "PCI_MSIX_TABLE_SIZE,MSI-X Table Size. For a description of this standard PCIe register field see the PCI Express Base Specification. SRIOV Note: All VFs in a single PF have the same value for 'MSI-X Table Size' (PCI_MSIX_TABLE_SIZE field in.." hexmask.long.byte 0x0 8.--15. 1. "PCI_MSIX_CAP_NEXT_OFFSET,MSI-X Next Capability Pointer. For a description of this standard PCIe register field see the PCI Express Base Specification. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN.." hexmask.long.byte 0x0 0.--7. 1. "PCI_MSIX_CAP_ID,MSI-X Capability ID. For a description of this standard PCIe register field see the PCI Express Base Specification." line.long 0x4 "MSIX_TABLE_OFFSET_REG,MSI-X Table Offset and BIR Register. For a description of this standard PCIe register. see the PCI Express Base Specification." hexmask.long 0x4 3.--31. 1. "PCI_MSIX_TABLE_OFFSET,MSI-X Table Offset. For a description of this standard PCIe register field see the PCI Express Base Specification. SRIOV Note: All VFs in a single PF have the same value for 'MSI-X Table Offset' (PCI_MSIX_TABLE_OFFSET field in.." bitfld.long 0x4 0.--2. "PCI_MSIX_BIR,MSI-X Table BAR Indicator Register Field. For a description of this standard PCIe register field see the PCI Express Base Specification. SRIOV Note: All VFs in a single PF have the same value for 'MSI-X Table BAR Indicator Register'.." "0,1,2,3,4,5,6,7" line.long 0x8 "MSIX_PBA_OFFSET_REG,MSI-X PBA Offset and BIR Register. For a description of this standard PCIe register. see the PCI Express Base Specification." hexmask.long 0x8 3.--31. 1. "PCI_MSIX_PBA_OFFSET,MSI-X PBA Offset. For a description of this standard PCIe register field see the PCI Express Base Specification. SRIOV Note: All VFs in a single PF have the same value for 'MSI-X PBA Offset' (PCI_MSIX_PBA_OFFSET field in.." bitfld.long 0x8 0.--2. "PCI_MSIX_PBA_BIR,MSI-X PBA BIR. For a description of this standard PCIe register field see the PCI Express Base Specification. SRIOV Note: All VFs in a single PF have the same value for 'MSI-X PBA BIR' (PCI_MSIX_PBA_BIR field in.." "0,1,2,3,4,5,6,7" tree.end tree "PF0_MSIX_CAP_DBI2 (DBI2 Shadow Block: PF MSI-X Capability Structure)" rgroup.long (0x0+0x10B0)++0x3 line.long 0x0 "SHADOW_PCI_MSIX_CAP_ID_NEXT_CTRL_REG,MSI-X Capability ID. Next Pointer. Control Registers. For a description of this standard PCIe register. see the PCI Express Base Specification." hexmask.long.byte 0x0 27.--31. 1. "RSVDP_27,Reserved for future use." hexmask.long.word 0x0 16.--26. 1. "PCI_MSIX_TABLE_SIZE,MSI-X Table Size in the shadow register. Note: The access attributes of this field are as follows: - Wire: No access - Dbi: No access - Dbi2: if (DBI_RO_WR_EN == 1) then R/W else R Note: This register field is sticky." hexmask.long.word 0x0 0.--15. 1. "RSVDP_0,Reserved for future use." group.long 0x4++0x7 line.long 0x0 "SHADOW_MSIX_TABLE_OFFSET_REG,MSI-X Table Offset and BIR Register. For a description of this standard PCIe register. see the PCI Express Base Specification." hexmask.long 0x0 3.--31. 1. "PCI_MSIX_TABLE_OFFSET,MSI-X Table Offset. For a description of this standard PCIe register field see the PCI Express Base Specification. Note: The access attributes of this field are as follows: - Wire: No access - Dbi: No access - Dbi2: if.." bitfld.long 0x0 0.--2. "PCI_MSIX_BIR,MSI-X Table BAR Indicator Register Field. For a description of this standard PCIe register field see the PCI Express Base Specification. Note: The access attributes of this field are as follows: - Wire: No access - Dbi: No access - Dbi2: if.." "?,?,if,?,?,?,?,?" line.long 0x4 "SHADOW_MSIX_PBA_OFFSET_REG,MSI-X PBA Offset and BIR Register. For a description of this standard PCIe register. see the PCI Express Base Specification." hexmask.long 0x4 3.--31. 1. "PCI_MSIX_PBA_OFFSET,MSI-X PBA Offset. For a description of this standard PCIe register field see the PCI Express Base Specification. Note: The access attributes of this field are as follows: - Wire: No access - Dbi: No access - Dbi2: if (DBI_RO_WR_EN ==.." bitfld.long 0x4 0.--2. "PCI_MSIX_PBA_BIR,MSI-X PBA BIR. For a description of this standard PCIe register field see the PCI Express Base Specification. Note: The access attributes of this field are as follows: - Wire: No access - Dbi: No access - Dbi2: if (DBI_RO_WR_EN == 1 &&.." "?,?,if,?,?,?,?,?" tree.end tree "PF0_DMA_CAP (DMA Port Logic Structure)" group.long (0x0+0xC8000)++0x3 line.long 0x0 "DMA_CTRL_DATA_ARB_PRIOR_OFF,DMA Arbitration Scheme for TRGT1 Interface. This register is used to control traffic priorities among various sources that are delivered to your application through TRGT1 where 0x0 represents the highest priority. - Non-DMA Rx.." hexmask.long.tbyte 0x0 12.--31. 1. "RSVDP_12,Reserved for future use." bitfld.long 0x0 9.--11. "RDBUFF_TRGT_WEIGHT,DMA Read Channel MWr Requests. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 6.--8. "RD_CTRL_TRGT_WEIGHT,DMA Read Channel MRd Requests. For LL element/descriptor access. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" "0,1,2,3,4,5,6,7" bitfld.long 0x0 3.--5. "WR_CTRL_TRGT_WEIGHT,DMA Write Channel MRd Requests. For DMA data requests and LL element/descriptor access. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 0.--2. "RTRGT1_WEIGHT,Non-DMA Rx Requests. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" "0,1,2,3,4,5,6,7" group.long (0x8+0xC8000)++0xB line.long 0x0 "DMA_CTRL_OFF,DMA Number of Channels Register." hexmask.long.byte 0x0 26.--31. 1. "RSVDP_26,Reserved for future use." bitfld.long 0x0 25. "DIS_C2W_CACHE_RD,Disable DMA Read Channels 'completion to memory write' context cache pre-fetch function. Note: For internal debugging only. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" "0,1" newline bitfld.long 0x0 24. "DIS_C2W_CACHE_WR,Disable DMA Write Channels 'completion to memory write' context cache pre-fetch function. Note: For internal debugging only. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" "0,1" hexmask.long.byte 0x0 20.--23. 1. "RSVDP_20,Reserved for future use." newline hexmask.long.byte 0x0 16.--19. 1. "NUM_DMA_RD_CHAN,Number of Read Channels. You can read this register to determine the number of read channels the DMA controller has been configured to support." hexmask.long.word 0x0 4.--15. 1. "RSVDP_4,Reserved for future use." newline hexmask.long.byte 0x0 0.--3. 1. "NUM_DMA_WR_CHAN,Number of Write Channels. You can read this register to determine the number of write channels the DMA controller has been configured to support." line.long 0x4 "DMA_WRITE_ENGINE_EN_OFF,DMA Write Engine Enable Register." hexmask.long.byte 0x4 24.--31. 1. "RSVDP_24,Reserved for future use." bitfld.long 0x4 23. "DMA_WRITE_ENGINE_EN_HSHAKE_CH7,Enable Handshake for DMA Write Engine Channel 7. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" "0,1" newline bitfld.long 0x4 22. "DMA_WRITE_ENGINE_EN_HSHAKE_CH6,Enable Handshake for DMA Write Engine Channel 6. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" "0,1" bitfld.long 0x4 21. "DMA_WRITE_ENGINE_EN_HSHAKE_CH5,Enable Handshake for DMA Write Engine Channel 5. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" "0,1" newline bitfld.long 0x4 20. "DMA_WRITE_ENGINE_EN_HSHAKE_CH4,Enable Handshake for DMA Write Engine Channel 4. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" "0,1" bitfld.long 0x4 19. "DMA_WRITE_ENGINE_EN_HSHAKE_CH3,Enable Handshake for DMA Write Engine Channel 3. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" "0,1" newline bitfld.long 0x4 18. "DMA_WRITE_ENGINE_EN_HSHAKE_CH2,Enable Handshake for DMA Write Engine Channel 2. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" "0,1" bitfld.long 0x4 17. "DMA_WRITE_ENGINE_EN_HSHAKE_CH1,Enable Handshake for DMA Write Engine Channel 1. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" "0,1" newline bitfld.long 0x4 16. "DMA_WRITE_ENGINE_EN_HSHAKE_CH0,Enable Handshake for DMA Write Engine Channel 0. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" "0,1" hexmask.long.word 0x4 1.--15. 1. "RSVDP_1,Reserved for future use." newline bitfld.long 0x4 0. "DMA_WRITE_ENGINE,DMA Write Engine Enable. - 1: Enable - 0: Disable (Soft Reset) For normal operation you must initially set this bit to '1' before any other software setup actions. You do not need to toggle or rewrite to this bit during normal.." "Disable,Enable" line.long 0x8 "DMA_WRITE_DOORBELL_OFF,DMA Write Doorbell Register." bitfld.long 0x8 31. "WR_STOP,Stop. Set in conjunction with the Doorbell Number field. The DMA write channel stops issuing requests sets the channel status to 'Stopped' and asserts the 'Abort' interrupt if it is enabled. Before setting the Stop bit you must read the.." "0,1" hexmask.long 0x8 3.--30. 1. "RSVDP_3,Reserved for future use." newline bitfld.long 0x8 0.--2. "WR_DOORBELL_NUM,Doorbell Number. You must write the channel number to this register to start the DMA write transfer for that channel. The DMA detects a write to this register field even if the value of this field does not change. You do not need to.." "0,1,2,3,4,5,6,7" group.long (0x18+0xC8000)++0x7 line.long 0x0 "DMA_WRITE_CHANNEL_ARB_WEIGHT_LOW_OFF,DMA Write Engine Channel Arbitration Weight Low Register. The 5-bit channel weight (for write channels 0-3) specifies the maximum number of TLP requests that the DMA can issue for that channel before it must return to.." hexmask.long.word 0x0 20.--31. 1. "RSVDP_20,Reserved for future use." hexmask.long.byte 0x0 15.--19. 1. "WRITE_CHANNEL3_WEIGHT,Channel 3 Weight. The weight is initialized by software before ringing the doorbell. The value is used by the channel weighted round robin arbiter to select the next channel read request. A value of '0' means that one TLP is issued.." newline hexmask.long.byte 0x0 10.--14. 1. "WRITE_CHANNEL2_WEIGHT,Channel 2 Weight. The weight is initialized by software before ringing the doorbell. The value is used by the channel weighted round robin arbiter to select the next channel read request. A value of '0' means that one TLP is issued.." hexmask.long.byte 0x0 5.--9. 1. "WRITE_CHANNEL1_WEIGHT,Channel 1 Weight. The weight is initialized by software before ringing the doorbell. The value is used by the channel weighted round robin arbiter to select the next channel read request. A value of '0' means that one TLP is issued.." newline hexmask.long.byte 0x0 0.--4. 1. "WRITE_CHANNEL0_WEIGHT,Channel 0 Weight. The weight is initialized by software before ringing the doorbell. The value is used by the channel weighted round robin arbiter to select the next channel read request. A value of '0' means that one TLP is issued.." line.long 0x4 "DMA_WRITE_CHANNEL_ARB_WEIGHT_HIGH_OFF,DMA Write Engine Channel Arbitration Weight High Register. The 5-bit channel weight (for write channels 4-7) specifies the maximum number of TLP requests that the DMA can issue for that channel before it must return.." hexmask.long.word 0x4 20.--31. 1. "RSVDP_20,Reserved for future use." hexmask.long.byte 0x4 15.--19. 1. "WRITE_CHANNEL7_WEIGHT,Channel 7 Weight. The weight is initialized by software before ringing the doorbell. The value is used by the channel weighted round robin arbiter to select the next channel read request. A value of '0' means that one TLP is issued.." newline hexmask.long.byte 0x4 10.--14. 1. "WRITE_CHANNEL6_WEIGHT,Channel 6 Weight. The weight is initialized by software before ringing the doorbell. The value is used by the channel weighted round robin arbiter to select the next channel read request. A value of '0' means that one TLP is issued.." hexmask.long.byte 0x4 5.--9. 1. "WRITE_CHANNEL5_WEIGHT,Channel 5 Weight. The weight is initialized by software before ringing the doorbell. The value is used by the channel weighted round robin arbiter to select the next channel read request. A value of '0' means that one TLP is issued.." newline hexmask.long.byte 0x4 0.--4. 1. "WRITE_CHANNEL4_WEIGHT,Channel 4 Weight. The weight is initialized by software before ringing the doorbell. The value is used by the channel weighted round robin arbiter to select the next channel read request. A value of '0' means that one TLP is issued.." group.long (0x2C+0xC8000)++0x7 line.long 0x0 "DMA_READ_ENGINE_EN_OFF,DMA Read Engine Enable Register." hexmask.long.byte 0x0 24.--31. 1. "RSVDP_24,Reserved for future use." bitfld.long 0x0 23. "DMA_READ_ENGINE_EN_HSHAKE_CH7,Enable Handshake for DMA Read Engine Channel 7. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" "0,1" newline bitfld.long 0x0 22. "DMA_READ_ENGINE_EN_HSHAKE_CH6,Enable Handshake for DMA Read Engine Channel 6. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" "0,1" bitfld.long 0x0 21. "DMA_READ_ENGINE_EN_HSHAKE_CH5,Enable Handshake for DMA Read Engine Channel 5. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" "0,1" newline bitfld.long 0x0 20. "DMA_READ_ENGINE_EN_HSHAKE_CH4,Enable Handshake for DMA Read Engine Channel 4. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" "0,1" bitfld.long 0x0 19. "DMA_READ_ENGINE_EN_HSHAKE_CH3,Enable Handshake for DMA Read Engine Channel 3. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" "0,1" newline bitfld.long 0x0 18. "DMA_READ_ENGINE_EN_HSHAKE_CH2,Enable Handshake for DMA Read Engine Channel 2. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" "0,1" bitfld.long 0x0 17. "DMA_READ_ENGINE_EN_HSHAKE_CH1,Enable Handshake for DMA Read Engine Channel 1. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" "0,1" newline bitfld.long 0x0 16. "DMA_READ_ENGINE_EN_HSHAKE_CH0,Enable Handshake for DMA Read Engine Channel 0. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" "0,1" hexmask.long.word 0x0 1.--15. 1. "RSVDP_1,Reserved for future use." newline bitfld.long 0x0 0. "DMA_READ_ENGINE,DMA Read Engine Enable. - 1: Enable - 0: Disable (Soft Reset) For normal operation you must initially set this bit to '1' before any other software setup actions. You do not need to toggle or rewrite to this bit during normal operation." "Disable,Enable" line.long 0x4 "DMA_READ_DOORBELL_OFF,DMA Read Doorbell Register." bitfld.long 0x4 31. "RD_STOP,Stop. Set in conjunction with the Doorbell Number field. The DMA read channel stops issuing requests sets the channel status to 'Stopped' and asserts the 'Abort' interrupt if it is enabled. Before setting the Stop bit you must read the channel.." "0,1" hexmask.long 0x4 3.--30. 1. "RSVDP_3,Reserved for future use." newline bitfld.long 0x4 0.--2. "RD_DOORBELL_NUM,Doorbell Number. You must write 0x0 to this register to start the DMA read transfer for that channel. The DMA detects a write to this register field even if the value of this field does not change. The range of this field is 0x0 to 0x7.." "0,1,2,3,4,5,6,7" group.long (0x38+0xC8000)++0x7 line.long 0x0 "DMA_READ_CHANNEL_ARB_WEIGHT_LOW_OFF,DMA Read Engine Channel Arbitration Weight Low Register. The 5-bit channel weight (for read channels 0-3) specifies the maximum number of TLP requests that the DMA can issue for that channel before it must return to.." hexmask.long.word 0x0 20.--31. 1. "RSVDP_20,Reserved for future use." hexmask.long.byte 0x0 15.--19. 1. "READ_CHANNEL3_WEIGHT,Channel 3 Weight. The weight is initialized by software before ringing the doorbell. The value is used by the channel weighted round robin arbiter to select the next channel read request. Note: The access attributes of this field are.." newline hexmask.long.byte 0x0 10.--14. 1. "READ_CHANNEL2_WEIGHT,Channel 2 Weight. The weight is initialized by software before ringing the doorbell. The value is used by the channel weighted round robin arbiter to select the next channel read request. Note: The access attributes of this field are.." hexmask.long.byte 0x0 5.--9. 1. "READ_CHANNEL1_WEIGHT,Channel 1 Weight. The weight is initialized by software before ringing the doorbell. The value is used by the channel weighted round robin arbiter to select the next channel read request. Note: The access attributes of this field are.." newline hexmask.long.byte 0x0 0.--4. 1. "READ_CHANNEL0_WEIGHT,Channel 0 Weight. The weight is initialized by software before ringing the doorbell. The value is used by the channel weighted round robin arbiter to select the next channel read request. Note: The access attributes of this field are.." line.long 0x4 "DMA_READ_CHANNEL_ARB_WEIGHT_HIGH_OFF,DMA Read Engine Channel Arbitration Weight High Register. The 5-bit channel weight (for read channels 4-7) specifies the maximum number of TLP requests that the DMA can issue for that channel before it must return to.." hexmask.long.word 0x4 20.--31. 1. "RSVDP_20,Reserved for future use." hexmask.long.byte 0x4 15.--19. 1. "READ_CHANNEL7_WEIGHT,Channel 7 Weight. The weight is initialized by software before ringing the doorbell. The value is used by the channel weighted round robin arbiter to select the next channel read request. Note: The access attributes of this field are.." newline hexmask.long.byte 0x4 10.--14. 1. "READ_CHANNEL6_WEIGHT,Channel 6 Weight. The weight is initialized by software before ringing the doorbell. The value is used by the channel weighted round robin arbiter to select the next channel read request. Note: The access attributes of this field are.." hexmask.long.byte 0x4 5.--9. 1. "READ_CHANNEL5_WEIGHT,Channel 5 Weight. The weight is initialized by software before ringing the doorbell. The value is used by the channel weighted round robin arbiter to select the next channel read request. Note: The access attributes of this field are.." newline hexmask.long.byte 0x4 0.--4. 1. "READ_CHANNEL4_WEIGHT,Channel 4 Weight. The weight is initialized by software before ringing the doorbell. The value is used by the channel weighted round robin arbiter to select the next channel read request. Note: The access attributes of this field are.." group.long (0x4C+0xC8000)++0x3 line.long 0x0 "DMA_WRITE_INT_STATUS_OFF,DMA Write Interrupt Status Register." hexmask.long.byte 0x0 24.--31. 1. "RSVDP_24,Reserved for future use." hexmask.long.byte 0x0 16.--23. 1. "WR_ABORT_INT_STATUS,Abort Interrupt Status. The DMA write channel has detected an error or you manually stopped the transfer as described in 'Error Handling Assistance by Remote Software'. Each bit corresponds to a DMA channel. Bit [0] corresponds to.." newline hexmask.long.byte 0x0 8.--15. 1. "RSVDP_8,Reserved for future use." hexmask.long.byte 0x0 0.--7. 1. "WR_DONE_INT_STATUS,Done Interrupt Status. The DMA write channel has successfully completed the DMA transfer. For more details see 'Interrupts and Error Handling'. Each bit corresponds to a DMA channel. Bit [0] corresponds to channel 0. - Enabling: For.." group.long (0x54+0xC8000)++0x7 line.long 0x0 "DMA_WRITE_INT_MASK_OFF,DMA Write Interrupt Mask Register." hexmask.long.byte 0x0 24.--31. 1. "RSVDP_24,Reserved for future use." hexmask.long.byte 0x0 16.--23. 1. "WR_ABORT_INT_MASK,Abort Interrupt Mask. Prevents the Abort interrupt status field in the DMA write interrupt status register from asserting the edma_int output. Each bit corresponds to a DMA channel. Bit [0] corresponds to channel 0. Note: The access.." newline hexmask.long.byte 0x0 8.--15. 1. "RSVDP_8,Reserved for future use." hexmask.long.byte 0x0 0.--7. 1. "WR_DONE_INT_MASK,Done Interrupt Mask. Prevents the Done interrupt status field in the DMA write interrupt status register from asserting the edma_int output. Each bit corresponds to a DMA channel. Bit [0] corresponds to channel 0. Note: The access.." line.long 0x4 "DMA_WRITE_INT_CLEAR_OFF,DMA Write Interrupt Clear Register." hexmask.long.byte 0x4 24.--31. 1. "RSVDP_24,Reserved for future use." hexmask.long.byte 0x4 16.--23. 1. "WR_ABORT_INT_CLEAR,Abort Interrupt Clear. You must write a 1'b1 to clear the corresponding bit in the Abort interrupt status field of the DMA write interrupt status register. Each bit corresponds to a DMA channel. Bit [0] corresponds to channel 0. Note:.." newline hexmask.long.byte 0x4 8.--15. 1. "RSVDP_8,Reserved for future use." hexmask.long.byte 0x4 0.--7. 1. "WR_DONE_INT_CLEAR,Done Interrupt Clear. You must write a 1'b1 to clear the corresponding bit in the Done interrupt status field of the DMA write interrupt status register. Each bit corresponds to a DMA channel. Bit [0] corresponds to channel 0. Note:.." rgroup.long (0x5C+0xC8000)++0x3 line.long 0x0 "DMA_WRITE_ERR_STATUS_OFF,DMA Write Error Status Register" hexmask.long.byte 0x0 24.--31. 1. "RSVDP_24,Reserved for future use." hexmask.long.byte 0x0 16.--23. 1. "LINKLIST_ELEMENT_FETCH_ERR_DETECT,Linked List Element Fetch Error Detected. The DMA write channel has received an error response from the AXI bus (or TRGT1 interface when the AXI Bridge is not used) while reading a linked list element from local memory." newline hexmask.long.byte 0x0 8.--15. 1. "RSVDP_8,Reserved for future use." hexmask.long.byte 0x0 0.--7. 1. "APP_READ_ERR_DETECT,Application Read Error Detected. The DMA write channel has received an error response from the AXI bus (or TRGT1 interface when the AXI Bridge is not used) while reading data from it. Each bit corresponds to a DMA channel. Bit [0].." group.long (0x60+0xC8000)++0x1F line.long 0x0 "DMA_WRITE_DONE_IMWR_LOW_OFF,DMA Write Done IMWr Address Low Register." hexmask.long 0x0 0.--31. 1. "DMA_WRITE_DONE_LOW_REG,The DMA uses this field to generate bits [31:0] of the address field for the Done IMWr TLP. Bits [1:0] must be '00' as this address must be dword aligned. Note: The access attributes of this field are as follows: - Wire: No access." line.long 0x4 "DMA_WRITE_DONE_IMWR_HIGH_OFF,DMA Write Done IMWr Interrupt Address High Register." hexmask.long 0x4 0.--31. 1. "DMA_WRITE_DONE_HIGH_REG,The DMA uses this field to generate bits [63:32] of the address field for the Done IMWr TLP. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" line.long 0x8 "DMA_WRITE_ABORT_IMWR_LOW_OFF,DMA Write Abort IMWr Address Low Register." hexmask.long 0x8 0.--31. 1. "DMA_WRITE_ABORT_LOW_REG,The DMA uses this field to generate bits [31:0] of the address field for the Abort IMWr TLP it generates. Bits [1:0] must be '00' as this address must be dword aligned. Note: The access attributes of this field are as follows: -.." line.long 0xC "DMA_WRITE_ABORT_IMWR_HIGH_OFF,DMA Write Abort IMWr Address High Register." hexmask.long 0xC 0.--31. 1. "DMA_WRITE_ABORT_HIGH_REG,The DMA uses this field to generate bits [63:32] of the address field for the Abort IMWr TLP. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" line.long 0x10 "DMA_WRITE_CH01_IMWR_DATA_OFF,DMA Write Channel 1 and 0 IMWr Data Register." hexmask.long.word 0x10 16.--31. 1. "WR_CHANNEL_1_DATA,The DMA uses this field to generate the data field for the Done or Abort IMWr TLPs it generates for write channel 1. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" hexmask.long.word 0x10 0.--15. 1. "WR_CHANNEL_0_DATA,The DMA uses this field to generate the data field for the Done or Abort IMWr TLPs it generates for write channel 0. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" line.long 0x14 "DMA_WRITE_CH23_IMWR_DATA_OFF,DMA Write Channel 3 and 2 IMWr Data Register." hexmask.long.word 0x14 16.--31. 1. "WR_CHANNEL_3_DATA,The DMA uses this field to generate the data field for the Done or Abort IMWr TLPs it generates for write channel 3. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" hexmask.long.word 0x14 0.--15. 1. "WR_CHANNEL_2_DATA,The DMA uses this field to generate the data field for the Done or Abort IMWr TLPs it generates for write channel 2. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" line.long 0x18 "DMA_WRITE_CH45_IMWR_DATA_OFF,DMA Write Channel 5 and 4 IMWr Data Register." hexmask.long.word 0x18 16.--31. 1. "WR_CHANNEL_5_DATA,The DMA uses this field to generate the data field for the Done or Abort IMWr TLPs it generates for write channel 5. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" hexmask.long.word 0x18 0.--15. 1. "WR_CHANNEL_4_DATA,The DMA uses this field to generate the data field for the Done or Abort IMWr TLPs it generates for write channel 4. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" line.long 0x1C "DMA_WRITE_CH67_IMWR_DATA_OFF,DMA Write Channel 7 and 6 IMWr Data Register." hexmask.long.word 0x1C 16.--31. 1. "WR_CHANNEL_7_DATA,The DMA uses this field to generate the data field for the Done or Abort IMWr TLPs it generates for write channel 7. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" hexmask.long.word 0x1C 0.--15. 1. "WR_CHANNEL_6_DATA,The DMA uses this field to generate the data field for the Done or Abort IMWr TLPs it generates for write channel 6. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" group.long (0x90+0xC8000)++0x3 line.long 0x0 "DMA_WRITE_LINKED_LIST_ERR_EN_OFF,DMA Write Linked List Error Enable Register. The LIE and RIE bits in the LL element enable the channel 'done' interrupts (local and remote). The LLLAIE and LLRAIE bits enable the channel 'abort' interrupts (local and.." hexmask.long.byte 0x0 24.--31. 1. "RSVDP_24,Reserved for future use." hexmask.long.byte 0x0 16.--23. 1. "WR_CHANNEL_LLLAIE,Write Channel LL Local Abort Interrupt Enable (LLLAIE). You enable the write channel local abort interrupt through this bit. The LIE and RIE bits in the LL element enable the write channel done interrupts. Each bit corresponds to a DMA.." newline hexmask.long.byte 0x0 8.--15. 1. "RSVDP_8,Reserved for future use." hexmask.long.byte 0x0 0.--7. 1. "WR_CHANNEL_LLRAIE,Write Channel LL Remote Abort Interrupt Enable (LLRAIE). You enable the write channel remote abort interrupt through this bit. The LIE and RIE bits in the LL element enable the write channel done interrupts. Each bit corresponds to a.." group.long (0xA0+0xC8000)++0x3 line.long 0x0 "DMA_READ_INT_STATUS_OFF,DMA Read Interrupt Status Register." hexmask.long.byte 0x0 24.--31. 1. "RSVDP_24,Reserved for future use." hexmask.long.byte 0x0 16.--23. 1. "RD_ABORT_INT_STATUS,Abort Interrupt Status. The DMA read channel has detected an error or you manually stopped the transfer as described in 'Stopping the DMA Transfer (Software Stop)'. Each bit corresponds to a DMA channel. Bit [0] corresponds to.." newline hexmask.long.byte 0x0 8.--15. 1. "RSVDP_8,Reserved for future use." hexmask.long.byte 0x0 0.--7. 1. "RD_DONE_INT_STATUS,Done Interrupt Status. The DMA read channel has successfully completed the DMA read transfer. Each bit corresponds to a DMA channel. Bit [0] corresponds to channel 0. - Enabling: For details see 'Interrupts and Error Handling'. -.." group.long (0xA8+0xC8000)++0x7 line.long 0x0 "DMA_READ_INT_MASK_OFF,DMA Read Interrupt Mask Register." hexmask.long.byte 0x0 24.--31. 1. "RSVDP_24,Reserved for future use." hexmask.long.byte 0x0 16.--23. 1. "RD_ABORT_INT_MASK,Abort Interrupt Mask. Prevents the Abort interrupt status field in the DMA read interrupt status register from asserting the edma_int output. Each bit corresponds to a DMA channel. Bit [0] corresponds to channel 0. Note: The access.." newline hexmask.long.byte 0x0 8.--15. 1. "RSVDP_8,Reserved for future use." hexmask.long.byte 0x0 0.--7. 1. "RD_DONE_INT_MASK,Done Interrupt Mask. Prevents the Done interrupt status field in the DMA read interrupt status register from asserting the edma_int output. Each bit corresponds to a DMA channel. Bit [0] corresponds to channel 0. Note: The access.." line.long 0x4 "DMA_READ_INT_CLEAR_OFF,DMA Read Interrupt Clear Register." hexmask.long.byte 0x4 24.--31. 1. "RSVDP_24,Reserved for future use." hexmask.long.byte 0x4 16.--23. 1. "RD_ABORT_INT_CLEAR,Abort Interrupt Clear. You must write a 1'b1 to clear the corresponding bit in the Abort interrupt status field of the DMA read interrupt status register. Each bit corresponds to a DMA channel. Bit [0] corresponds to channel 0. Note:.." newline hexmask.long.byte 0x4 8.--15. 1. "RSVDP_8,Reserved for future use." hexmask.long.byte 0x4 0.--7. 1. "RD_DONE_INT_CLEAR,Done Interrupt Clear. You must write a 1'b1 to clear the corresponding bit in the Done interrupt status field of the DMA read interrupt status register. Each bit corresponds to a DMA channel. Bit [0] corresponds to channel 0. Note:.." rgroup.long (0xB4+0xC8000)++0x7 line.long 0x0 "DMA_READ_ERR_STATUS_LOW_OFF,DMA Read Error Status Low Register." hexmask.long.byte 0x0 24.--31. 1. "RSVDP_24,Reserved for future use." hexmask.long.byte 0x0 16.--23. 1. "LINK_LIST_ELEMENT_FETCH_ERR_DETECT,Linked List Element Fetch Error Detected. - The DMA read channel has received an error response from the AXI bus while reading a linked list element from local memory. Each bit corresponds to a DMA channel. Bit [0].." newline hexmask.long.byte 0x0 8.--15. 1. "RSVDP_8,Reserved for future use." hexmask.long.byte 0x0 0.--7. 1. "APP_WR_ERR_DETECT,Application Write Error Detected. The DMA read channel has received an error response from the AXI bus (or TRGT1 interface when the AXI Bridge is not used) while writing data to it. This error is fatal. You must restart the transfer.." line.long 0x4 "DMA_READ_ERR_STATUS_HIGH_OFF,DMA Read Error Status High Register." hexmask.long.byte 0x4 24.--31. 1. "DATA_POISIONING,Data Poisoning. The DMA read channel has detected data poisoning in the completion from the remote device (in response to the MRd request). The DMA read channel will drop the completion and then be halted. The CX_FLT_MASK_UR_POIS filter.." hexmask.long.byte 0x4 16.--23. 1. "CPL_TIMEOUT,Completion Time Out. The DMA read channel has timed-out while waiting for the remote device to respond to the MRd request or a malformed CplD has been received. For more details see 'Linked List Mode'. Each bit corresponds to a DMA channel." newline hexmask.long.byte 0x4 8.--15. 1. "CPL_ABORT,Completer Abort. The DMA read channel has received a PCIe completer abort completion status from the remote device in response to the MRd request. For more details see 'Linked List Mode'. Each bit corresponds to a DMA channel. Bit [0].." hexmask.long.byte 0x4 0.--7. 1. "UNSUPPORTED_REQ,Unsupported Request. The DMA read channel has received a PCIe unsupported request completion status from the remote device in response to the MRd request. For more details see 'Linked List Mode'. Each bit corresponds to a DMA channel." group.long (0xC4+0xC8000)++0x3 line.long 0x0 "DMA_READ_LINKED_LIST_ERR_EN_OFF,DMA Read Linked List Error Enable Register. The LIE and RIE bits in the LL element enable the channel 'done' interrupts (local and remote). The LLLAIE and LLRAIE bits enable the channel 'abort' interrupts (local and remote)." hexmask.long.byte 0x0 24.--31. 1. "RSVDP_24,Reserved for future use." hexmask.long.byte 0x0 16.--23. 1. "RD_CHANNEL_LLLAIE,Read Channel LL Local Abort Interrupt Enable (LLLAIE). You enable the read channel Local Abort interrupt through this bit. The LIE and RIE bits in the LL element enable the read channel done interrupts. Each bit corresponds to a DMA.." newline hexmask.long.byte 0x0 8.--15. 1. "RSVDP_8,Reserved for future use." hexmask.long.byte 0x0 0.--7. 1. "RD_CHANNEL_LLRAIE,Read Channel LL Remote Abort Interrupt Enable (LLRAIE). You enable the read channel Remote Abort interrupt through this bit. The LIE and RIE bits in the LL element enable the read channel done interrupts. Each bit corresponds to a DMA.." group.long (0xCC+0xC8000)++0x1F line.long 0x0 "DMA_READ_DONE_IMWR_LOW_OFF,DMA Read Done IMWr Address Low Register." hexmask.long 0x0 0.--31. 1. "DMA_READ_DONE_LOW_REG,The DMA uses this field to generate bits [31:0] of the address field for the Done IMWr TLP. Bits [1:0] must be '00' as this address must be dword aligned. Note: The access attributes of this field are as follows: - Wire: No access." line.long 0x4 "DMA_READ_DONE_IMWR_HIGH_OFF,DMA Read Done IMWr Address High Register." hexmask.long 0x4 0.--31. 1. "DMA_READ_DONE_HIGH_REG,The DMA uses this field to generate bits [63:32] of the address field for the Done IMWr TLP. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" line.long 0x8 "DMA_READ_ABORT_IMWR_LOW_OFF,DMA Read Abort IMWr Address Low Register." hexmask.long 0x8 0.--31. 1. "DMA_READ_ABORT_LOW_REG,The DMA uses this field to generate bits [31:0] of the address field for the Abort IMWr TLP. Bits [1:0] must be '00' as this address must be dword aligned. Note: The access attributes of this field are as follows: - Wire: No.." line.long 0xC "DMA_READ_ABORT_IMWR_HIGH_OFF,DMA Read Abort IMWr Address High Register." hexmask.long 0xC 0.--31. 1. "DMA_READ_ABORT_HIGH_REG,The DMA uses this field to generate bits [63:32] of the address field for the Abort IMWr TLP. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" line.long 0x10 "DMA_READ_CH01_IMWR_DATA_OFF,DMA Read Channel 1 and 0 IMWr Data Register." hexmask.long.word 0x10 16.--31. 1. "RD_CHANNEL_1_DATA,The DMA uses this field to generate the data field for the Done or Abort IMWr TLPs it generates for read channel 1. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" hexmask.long.word 0x10 0.--15. 1. "RD_CHANNEL_0_DATA,The DMA uses this field to generate the data field for the Done or Abort IMWr TLPs it generates for read channel 0. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" line.long 0x14 "DMA_READ_CH23_IMWR_DATA_OFF,DMA Read Channel 3 and 2 IMWr Data Register." hexmask.long.word 0x14 16.--31. 1. "RD_CHANNEL_3_DATA,The DMA uses this field to generate the data field for the Done or Abort IMWr TLPs it generates for read channel 3. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" hexmask.long.word 0x14 0.--15. 1. "RD_CHANNEL_2_DATA,The DMA uses this field to generate the data field for the Done or Abort IMWr TLPs it generates for read channel 2. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" line.long 0x18 "DMA_READ_CH45_IMWR_DATA_OFF,DMA Read Channel 5 and 4 IMWr Data Register." hexmask.long.word 0x18 16.--31. 1. "RD_CHANNEL_5_DATA,The DMA uses this field to generate the data field for the Done or Abort IMWr TLPs it generates for read channel 5. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" hexmask.long.word 0x18 0.--15. 1. "RD_CHANNEL_4_DATA,The DMA uses this field to generate the data field for the Done or Abort IMWr TLPs it generates for read channel 4. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" line.long 0x1C "DMA_READ_CH67_IMWR_DATA_OFF,DMA Read Channel 7 and 6 IMWr Data Register." hexmask.long.word 0x1C 16.--31. 1. "RD_CHANNEL_7_DATA,The DMA uses this field to generate the data field for the Done or Abort IMWr TLPs it generates for read channel 7. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" hexmask.long.word 0x1C 0.--15. 1. "RD_CHANNEL_6_DATA,The DMA uses this field to generate the data field for the Done or Abort IMWr TLPs it generates for read channel 6. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" rgroup.long (0x108+0xC8000)++0x7 line.long 0x0 "DMA_WRITE_ENGINE_HSHAKE_CNT_LOW_OFF,DMA Write Engine Handshake Counter Channel 0/1/2/3 Register." bitfld.long 0x0 29.--31. "RSVDP_29,Reserved for future use." "0,1,2,3,4,5,6,7" hexmask.long.byte 0x0 24.--28. 1. "DMA_WRITE_ENGINE_HSHAKE_CNT_CH3,DMA handshake counter for DMA Write Engine Channel 3. If CC_DMA_HSHAKE =1 the data transfer in Linked List mode starts only when the counter is non-zero." newline bitfld.long 0x0 21.--23. "RSVDP_21,Reserved for future use." "0,1,2,3,4,5,6,7" hexmask.long.byte 0x0 16.--20. 1. "DMA_WRITE_ENGINE_HSHAKE_CNT_CH2,DMA handshake counter for DMA Write Engine Channel 2. If CC_DMA_HSHAKE =1 the data transfer in Linked List mode starts only when the counter is non-zero." newline bitfld.long 0x0 13.--15. "RSVDP_13,Reserved for future use." "0,1,2,3,4,5,6,7" hexmask.long.byte 0x0 8.--12. 1. "DMA_WRITE_ENGINE_HSHAKE_CNT_CH1,DMA handshake counter for DMA Write Engine Channel 1. If CC_DMA_HSHAKE =1 the data transfer in Linked List mode starts only when the counter is non-zero." newline bitfld.long 0x0 5.--7. "RSVDP_5,Reserved for future use." "0,1,2,3,4,5,6,7" hexmask.long.byte 0x0 0.--4. 1. "DMA_WRITE_ENGINE_HSHAKE_CNT_CH0,DMA handshake counter for DMA Write Engine Channel 0. If CC_DMA_HSHAKE =1 the data transfer in Linked List mode starts only when the counter is non-zero." line.long 0x4 "DMA_WRITE_ENGINE_HSHAKE_CNT_HIGH_OFF,DMA Write Engine Handshake Counter Channel 4/5/6/7 Register." bitfld.long 0x4 29.--31. "RSVDP_29,Reserved for future use." "0,1,2,3,4,5,6,7" hexmask.long.byte 0x4 24.--28. 1. "DMA_WRITE_ENGINE_HSHAKE_CNT_CH7,DMA handshake counter for DMA Write Engine Channel 7. If CC_DMA_HSHAKE =1 the data transfer in Linked List mode starts only when the counter is non-zero." newline bitfld.long 0x4 21.--23. "RSVDP_21,Reserved for future use." "0,1,2,3,4,5,6,7" hexmask.long.byte 0x4 16.--20. 1. "DMA_WRITE_ENGINE_HSHAKE_CNT_CH6,DMA handshake counter for DMA Write Engine Channel 6. If CC_DMA_HSHAKE =1 the data transfer in Linked List mode starts only when the counter is non-zero." newline bitfld.long 0x4 13.--15. "RSVDP_13,Reserved for future use." "0,1,2,3,4,5,6,7" hexmask.long.byte 0x4 8.--12. 1. "DMA_WRITE_ENGINE_HSHAKE_CNT_CH5,DMA handshake counter for DMA Write Engine Channel 5. If CC_DMA_HSHAKE =1 the data transfer in Linked List mode starts only when the counter is non-zero." newline bitfld.long 0x4 5.--7. "RSVDP_5,Reserved for future use." "0,1,2,3,4,5,6,7" hexmask.long.byte 0x4 0.--4. 1. "DMA_WRITE_ENGINE_HSHAKE_CNT_CH4,DMA handshake counter for DMA Write Engine Channel 4. If CC_DMA_HSHAKE =1 the data transfer in Linked List mode starts only when the counter is non-zero." rgroup.long (0x118+0xC8000)++0x7 line.long 0x0 "DMA_READ_ENGINE_HSHAKE_CNT_LOW_OFF,DMA Read Engine Handshake Counter Channel 0/1/2/3 Register." bitfld.long 0x0 29.--31. "RSVDP_29,Reserved for future use." "0,1,2,3,4,5,6,7" hexmask.long.byte 0x0 24.--28. 1. "DMA_READ_ENGINE_HSHAKE_CNT_CH3,DMA handshake counter for DMA Read Engine Channel 3. If CC_DMA_HSHAKE =1 the data transfer in Linked List mode starts only when the counter is non-zero." newline bitfld.long 0x0 21.--23. "RSVDP_21,Reserved for future use." "0,1,2,3,4,5,6,7" hexmask.long.byte 0x0 16.--20. 1. "DMA_READ_ENGINE_HSHAKE_CNT_CH2,DMA handshake counter for DMA Read Engine Channel 2. If CC_DMA_HSHAKE =1 the data transfer in Linked List mode starts only when the counter is non-zero." newline bitfld.long 0x0 13.--15. "RSVDP_13,Reserved for future use." "0,1,2,3,4,5,6,7" hexmask.long.byte 0x0 8.--12. 1. "DMA_READ_ENGINE_HSHAKE_CNT_CH1,DMA handshake counter for DMA Read Engine Channel 1. If CC_DMA_HSHAKE =1 the data transfer in Linked List mode starts only when the counter is non-zero." newline bitfld.long 0x0 5.--7. "RSVDP_5,Reserved for future use." "0,1,2,3,4,5,6,7" hexmask.long.byte 0x0 0.--4. 1. "DMA_READ_ENGINE_HSHAKE_CNT_CH0,DMA handshake counter for DMA Read Engine Channel 0. If CC_DMA_HSHAKE =1 the data transfer in Linked List mode starts only when the counter is non-zero." line.long 0x4 "DMA_READ_ENGINE_HSHAKE_CNT_HIGH_OFF,DMA Read Engine Handshake Counter Channel 4/5/6/7 Register." bitfld.long 0x4 29.--31. "RSVDP_29,Reserved for future use." "0,1,2,3,4,5,6,7" hexmask.long.byte 0x4 24.--28. 1. "DMA_READ_ENGINE_HSHAKE_CNT_CH7,DMA handshake counter for DMA Read Engine Channel 7. If CC_DMA_HSHAKE =1 the data transfer in Linked List mode starts only when the counter is non-zero." newline bitfld.long 0x4 21.--23. "RSVDP_21,Reserved for future use." "0,1,2,3,4,5,6,7" hexmask.long.byte 0x4 16.--20. 1. "DMA_READ_ENGINE_HSHAKE_CNT_CH6,DMA handshake counter for DMA Read Engine Channel 6. If CC_DMA_HSHAKE =1 the data transfer in Linked List mode starts only when the counter is non-zero." newline bitfld.long 0x4 13.--15. "RSVDP_13,Reserved for future use." "0,1,2,3,4,5,6,7" hexmask.long.byte 0x4 8.--12. 1. "DMA_READ_ENGINE_HSHAKE_CNT_CH5,DMA handshake counter for DMA Read Engine Channel 5. If CC_DMA_HSHAKE =1 the data transfer in Linked List mode starts only when the counter is non-zero." newline bitfld.long 0x4 5.--7. "RSVDP_5,Reserved for future use." "0,1,2,3,4,5,6,7" hexmask.long.byte 0x4 0.--4. 1. "DMA_READ_ENGINE_HSHAKE_CNT_CH4,DMA handshake counter for DMA Read Engine Channel 4. If CC_DMA_HSHAKE =1 the data transfer in Linked List mode starts only when the counter is non-zero." repeat 8. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 )(list 0x0 0x200 0x400 0x600 0x800 0xA00 0xC00 0xE00 ) group.long ($2+0x200+0xC8000)++0x3 line.long 0x0 "DMA_CH_CONTROL1_OFF_WRCH_$1,DMA Write Channel Control 1 Register." bitfld.long 0x0 30.--31. "DMA_AT,Address Translation TLP Header Bit (AT) The DMA uses this TLP header field when generating MRd/MWr (not IMWr) TLPs. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" "0,1,2,3" bitfld.long 0x0 27.--29. "DMA_TC,Traffic Class TLP Header Bit (TC) The DMA uses this TLP header field when generating MRd/MWr (not IMWr) TLPs. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 26. "DMA_RESERVED5,Reserved. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" "0,1" bitfld.long 0x0 25. "DMA_RO,Relaxed Ordering TLP Header Bit (RO) The DMA uses this TLP header field when generating MRd/MWr (not IMWr) TLPs. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" "0,1" newline bitfld.long 0x0 24. "DMA_NS_SRC,Source No Snoop TLP Header Bit (DMA_NS_SRC). The DMA uses this TLP header field when generating MRd (SAR addressing space) (not IMWr) TLPs. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" "0,1" bitfld.long 0x0 23. "DMA_NS_DST,Destination No Snoop TLP Header Bit (DMA_NS_DST). The DMA uses this TLP header field when generating MWr (DAR addressing space) (not IMWr) TLPs. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" "0,1" newline bitfld.long 0x0 22. "DMA_MEM_TYPE,Master AXI ACE-Lite Cache Coherency Control. This field sets the DMA channel memory type of the address space of the data transfer as follows: - 0x0:peripheral type - 0x1:memory type For more details see 'ACE-Lite Features and Limitations'.." "peripheral type,memory type" hexmask.long.byte 0x0 17.--21. 1. "DMA_RESERVED2,Reserved. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" newline hexmask.long.byte 0x0 12.--16. 1. "DMA_FUNC_NUM,Function Number (FN). The controller uses this field when generating the requester ID for the MRd/MWr DMA TLP. When you have enabled SR-IOV then this field is ignored if you have set the VFE field in the 'DMA Write Channel Control 2.." bitfld.long 0x0 10.--11. "DMA_RESERVED1,Reserved. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" "0,1,2,3" newline bitfld.long 0x0 9. "LLE,Linked List Enable (LLE). - 0: Disable linked list operation - 1: Enable linked list operation Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" "Disable linked list operation,Enable linked list operation" bitfld.long 0x0 8. "CCS,Consumer Cycle State (CCS). Used in linked list mode only. It is used to synchronize the producer (software) and the consumer (DMA). For more details see 'PCS-CCS-CB-TCB Producer-Consumer Synchronization'. You must initialize this bit. The DMA.." "0,1" newline bitfld.long 0x0 7. "DMA_RESERVED0,Reserved. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" "0,1" bitfld.long 0x0 5.--6. "CS,Channel Status (CS). The channel status bits identify the current operational state of the DMA channel. The operation state encoding for each DMA channel is a s follows: - 00: Reserved - 01: Running. This channel is active and transferring data. - 10:.." "Reserved,Running,?,?" newline bitfld.long 0x0 4. "RIE,Remote Interrupt Enable (RIE). You must set this bit to enable the generation of the Done or Abort Remote interrupts. For more details see 'Interrupts and Error Handling'. In LL mode the DMA overwrites this with the RIE of the LL element. The RIE.." "0,1" bitfld.long 0x0 3. "LIE,Local Interrupt Enable (LIE). You must set this bit to enable the generation of the Done or Abort Local interrupts. For more details see 'Interrupts and Error Handling'. In LL mode the DMA overwrites this with the LIE of the LL element. The LIE bit.." "0,1" newline bitfld.long 0x0 2. "LLP,Load Link Pointer (LLP). Used in linked list mode only. Indicates that this linked list element is a link element and its LL element pointer dwords are pointing to the next (non-contiguous) element. The DMA loads this field with the LLP of the.." "0,1" bitfld.long 0x0 1. "TCB,Toggle Cycle Bit (TCB). Indicates to the DMA to toggle its interpretation of the CB. Used in linked list mode only. It is used to synchronize the producer (software) and the consumer (DMA). For more details see 'PCS-CCS-CB-TCB Producer-Consumer.." "0,1" newline bitfld.long 0x0 0. "CB,Cycle Bit (CB). Used in linked list mode only. It is used to synchronize the producer (software) and the consumer (DMA). For more details see 'PCS-CCS-CB-TCB Producer-Consumer Synchronization'. The DMA loads this field with the CB of the linked list.." "0,1" repeat.end repeat 8. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 )(list 0x0 0x200 0x400 0x600 0x800 0xA00 0xC00 0xE00 ) group.long ($2+0x208+0xC8000)++0x3 line.long 0x0 "DMA_TRANSFER_SIZE_OFF_WRCH_$1,DMA Write Transfer Size Register." hexmask.long 0x0 0.--31. 1. "DMA_TRANSFER_SIZE,DMA Transfer Size. You program this register with the size of the DMA transfer. The maximum DMA transfer size is 4Gbytes. The minimum transfer size is one byte (0x1). This field is automatically decremented by the DMA as the DMA write.." repeat.end repeat 8. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 )(list 0x0 0x200 0x400 0x600 0x800 0xA00 0xC00 0xE00 ) group.long ($2+0x20C+0xC8000)++0x3 line.long 0x0 "DMA_SAR_LOW_OFF_WRCH_$1,DMA Write SAR Low Register." hexmask.long 0x0 0.--31. 1. "SRC_ADDR_REG_LOW,Source Address Register (Lower 32 bits). Indicates the next address to be read from. The DMA increments the SAR as the DMA transfer progresses. In LL mode the DMA overwrites this with the corresponding dword of the LL element. - DMA.." repeat.end repeat 8. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 )(list 0x0 0x200 0x400 0x600 0x800 0xA00 0xC00 0xE00 ) group.long ($2+0x210+0xC8000)++0x3 line.long 0x0 "DMA_SAR_HIGH_OFF_WRCH_$1,DMA Write SAR High Register." hexmask.long 0x0 0.--31. 1. "SRC_ADDR_REG_HIGH,Source Address Register (Higher 32 bits). In LL mode the DMA overwrites this with the corresponding dword of the LL element. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" repeat.end repeat 8. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 )(list 0x0 0x200 0x400 0x600 0x800 0xA00 0xC00 0xE00 ) group.long ($2+0x214+0xC8000)++0x3 line.long 0x0 "DMA_DAR_LOW_OFF_WRCH_$1,DMA Write DAR Low Register." hexmask.long 0x0 0.--31. 1. "DST_ADDR_REG_LOW,Destination Address Register (Lower 32 bits). Indicates the next address to be written to. The DMA increments the DAR as the DMA transfer progresses. In LL mode the DMA overwrites this with the corresponding dword of the LL element. -.." repeat.end repeat 8. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 )(list 0x0 0x200 0x400 0x600 0x800 0xA00 0xC00 0xE00 ) group.long ($2+0x218+0xC8000)++0x3 line.long 0x0 "DMA_DAR_HIGH_OFF_WRCH_$1,DMA Write DAR High Register." hexmask.long 0x0 0.--31. 1. "DST_ADDR_REG_HIGH,Destination Address Register (Higher 32 bits). In LL mode the DMA overwrites this with the corresponding dword of the LL element. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" repeat.end repeat 8. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 )(list 0x0 0x200 0x400 0x600 0x800 0xA00 0xC00 0xE00 ) group.long ($2+0x21C+0xC8000)++0x3 line.long 0x0 "DMA_LLP_LOW_OFF_WRCH_$1,DMA Write Linked List Pointer Low Register." hexmask.long 0x0 0.--31. 1. "LLP_LOW,Lower bits of the address of the linked list transfer list in local memory. Used in linked list mode only. Updated by the DMA to point to the next element in the transfer list after the previous element is consumed. - When the current element is.." repeat.end repeat 8. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 )(list 0x0 0x200 0x400 0x600 0x800 0xA00 0xC00 0xE00 ) group.long ($2+0x220+0xC8000)++0x3 line.long 0x0 "DMA_LLP_HIGH_OFF_WRCH_$1,DMA Write Linked List Pointer High Register." hexmask.long 0x0 0.--31. 1. "LLP_HIGH,Upper 32 bits of the address of the linked list transfer list in local memory. Used in linked list mode only. Updated by the DMA to point to the next element in the transfer list as elements are consumed. Note: The access attributes of this.." repeat.end repeat 8. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 )(list 0x0 0x200 0x400 0x600 0x800 0xA00 0xC00 0xE00 ) group.long ($2+0x300+0xC8000)++0x3 line.long 0x0 "DMA_CH_CONTROL1_OFF_RDCH_$1,DMA Read Channel Control 1 Register." bitfld.long 0x0 30.--31. "DMA_AT,Address Translation TLP Header Bit (AT) The DMA uses this TLP header field when generating MRd/MWr (not IMWr) TLPs. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" "0,1,2,3" bitfld.long 0x0 27.--29. "DMA_TC,Traffic Class TLP Header Bit (TC) The DMA uses this TLP header field when generating MRd/MWr (not IMWr) TLPs. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 26. "DMA_RESERVED5,Reserved. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" "0,1" bitfld.long 0x0 25. "DMA_RO,Relaxed Ordering TLP Header Bit (RO) The DMA uses this TLP header field when generating MRd/MWr (not IMWr) TLPs. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" "0,1" newline bitfld.long 0x0 24. "DMA_NS_SRC,Source No Snoop TLP Header Bit (DMA_NS_SRC). The DMA uses this TLP header field when generating MRd (SAR addressing space) (not IMWr) TLPs. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" "0,1" bitfld.long 0x0 23. "DMA_NS_DST,Destination No Snoop TLP Header Bit (DMA_NS_DST). The DMA uses this TLP header field when generating MWr (DAR addressing space) (not IMWr) TLPs. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" "0,1" newline bitfld.long 0x0 22. "DMA_MEM_TYPE,Master AXI ACE-Lite Cache Coherency Control. This field sets the DMA channel memory type of the address space of the data transfer as follows: - 0x0:peripheral type - 0x1:memory type For more details see 'ACE-Lite Features and Limitations'.." "peripheral type,memory type" hexmask.long.byte 0x0 17.--21. 1. "DMA_RESERVED2,Reserved. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" newline hexmask.long.byte 0x0 12.--16. 1. "DMA_FUNC_NUM,Function Number (FN). The controller uses this field when generating the requester ID for the MRd/MWr DMA TLP. When you have enabled SR-IOV then this field is ignored if you have set the VFE field in the 'DMA Read Channel Control 2.." bitfld.long 0x0 10.--11. "DMA_RESERVED1,Reserved. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" "0,1,2,3" newline bitfld.long 0x0 9. "LLE,Linked List Enable (LLE). - 0: Disable linked list operation - 1: Enable linked list operation Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" "Disable linked list operation,Enable linked list operation" bitfld.long 0x0 8. "CCS,Consumer Cycle State (CCS). Used in linked list mode only. It is used to synchronize the producer (software) and the consumer (DMA). For more details see 'PCS-CCS-CB-TCB Producer-Consumer Synchronization'. You must initialize this bit. The DMA.." "0,1" newline bitfld.long 0x0 7. "DMA_RESERVED0,Reserved. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" "0,1" bitfld.long 0x0 5.--6. "CS,Channel Status (CS). The channel status bits identify the current operational state of the DMA channel. The operation state encoding for each DMA channel is a s follows: - 00: Reserved - 01: Running. This channel is active and transferring data. - 10:.." "Reserved,Running,?,?" newline bitfld.long 0x0 4. "RIE,Remote Interrupt Enable (RIE). You must set this bit to enable the generation of the Done or Abort Remote interrupts. For more details see 'Interrupts and Error Handling'. In LL mode the DMA overwrites this with the RIE of the LL element. The RIE.." "0,1" bitfld.long 0x0 3. "LIE,Local Interrupt Enable (LIE). You must set this bit to enable the generation of the Done or Abort Local interrupts. For more details see 'Interrupts and Error Handling'. In LL mode the DMA overwrites this with the LIE of the LL element. The LIE bit.." "0,1" newline bitfld.long 0x0 2. "LLP,Load Link Pointer (LLP). Used in linked list mode only. Indicates that this linked list element is a link element and its LL element pointer dwords are pointing to the next (non-contiguous) element. The DMA loads this field with the LLP of the.." "0,1" bitfld.long 0x0 1. "TCB,Toggle Cycle Bit (TCB). Indicates to the DMA to toggle its interpretation of the CB. Used in linked list mode only. It is used to synchronize the producer (software) and the consumer (DMA). For more details see 'PCS-CCS-CB-TCB Producer-Consumer.." "0,1" newline bitfld.long 0x0 0. "CB,Cycle Bit (CB). Used in linked list mode only. It is used to synchronize the producer (software) and the consumer (DMA). For more details see 'PCS-CCS-CB-TCB Producer-Consumer Synchronization'. The DMA loads this field with the CB of the linked list.." "0,1" repeat.end repeat 8. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 )(list 0x0 0x200 0x400 0x600 0x800 0xA00 0xC00 0xE00 ) group.long ($2+0x308+0xC8000)++0x3 line.long 0x0 "DMA_TRANSFER_SIZE_OFF_RDCH_$1,DMA Read Transfer Size Register." hexmask.long 0x0 0.--31. 1. "DMA_TRANSFER_SIZE,DMA Transfer Size. You program this register with the size of the DMA transfer. The maximum DMA transfer size is 4Gbytes. The minimum transfer size is one byte (0x1). This field is automatically decremented by the DMA as the DMA read.." repeat.end repeat 8. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 )(list 0x0 0x200 0x400 0x600 0x800 0xA00 0xC00 0xE00 ) group.long ($2+0x30C+0xC8000)++0x3 line.long 0x0 "DMA_SAR_LOW_OFF_RDCH_$1,DMA Read SAR Low Register." hexmask.long 0x0 0.--31. 1. "SRC_ADDR_REG_LOW,Source Address Register (Lower 32 bits). Indicates the next address to be read from. The DMA increments the SAR as the DMA transfer progresses. In LL mode the DMA overwrites this with the corresponding dword of the LL element. - DMA.." repeat.end repeat 8. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 )(list 0x0 0x200 0x400 0x600 0x800 0xA00 0xC00 0xE00 ) group.long ($2+0x310+0xC8000)++0x3 line.long 0x0 "DMA_SAR_HIGH_OFF_RDCH_$1,DMA Read SAR High Register." hexmask.long 0x0 0.--31. 1. "SRC_ADDR_REG_HIGH,Source Address Register (Higher 32 bits). In LL mode the DMA overwrites this with the corresponding dword of the LL element. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" repeat.end repeat 8. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 )(list 0x0 0x200 0x400 0x600 0x800 0xA00 0xC00 0xE00 ) group.long ($2+0x314+0xC8000)++0x3 line.long 0x0 "DMA_DAR_LOW_OFF_RDCH_$1,DMA Read DAR Low Register." hexmask.long 0x0 0.--31. 1. "DST_ADDR_REG_LOW,Destination Address Register (Lower 32 bits). Indicates the next address to be written to. The DMA increments the DAR as the DMA transfer progresses. In LL mode the DMA overwrites this with the corresponding dword of the LL element. -.." repeat.end repeat 8. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 )(list 0x0 0x200 0x400 0x600 0x800 0xA00 0xC00 0xE00 ) group.long ($2+0x318+0xC8000)++0x3 line.long 0x0 "DMA_DAR_HIGH_OFF_RDCH_$1,DMA Read DAR High Register." hexmask.long 0x0 0.--31. 1. "DST_ADDR_REG_HIGH,Destination Address Register (Higher 32 bits). In LL mode the DMA overwrites this with the corresponding dword of the LL element. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" repeat.end repeat 8. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 )(list 0x0 0x200 0x400 0x600 0x800 0xA00 0xC00 0xE00 ) group.long ($2+0x31C+0xC8000)++0x3 line.long 0x0 "DMA_LLP_LOW_OFF_RDCH_$1,DMA Read Linked List Pointer Low Register." hexmask.long 0x0 0.--31. 1. "LLP_LOW,Lower bits of the address of the linked list transfer list in local memory. Used in linked list mode only. Updated by the DMA to point to the next element in the transfer list after the previous element is consumed. - When the current element is.." repeat.end repeat 8. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 )(list 0x0 0x200 0x400 0x600 0x800 0xA00 0xC00 0xE00 ) group.long ($2+0x320+0xC8000)++0x3 line.long 0x0 "DMA_LLP_HIGH_OFF_RDCH_$1,DMA Read Linked List Pointer High Register." hexmask.long 0x0 0.--31. 1. "LLP_HIGH,Upper 32 bits of the address of the linked list transfer list in local memory. Used in linked list mode only. Updated by the DMA to point to the next element in the transfer list as elements are consumed. Note: The access attributes of this.." repeat.end tree.end tree "PF0_ATU_CAP (ATU Por Logic Structure)" repeat 8. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 )(list 0x0 0x200 0x400 0x600 0x800 0xA00 0xC00 0xE00 ) group.long ($2+0xC0000)++0x3 line.long 0x0 "IATU_REGION_CTRL_1_OFF_OUTBOUND_$1,iATU Region Control 1 Register." bitfld.long 0x0 20. "CTRL_1_FUNC_NUM,Function Number. - When the address of an outbound TLP is matched to this region and the FUNC_BYPASS field in the 'iATU Control 2 Register' is '0' then the function number used in generating the function part of the requester ID (RID).." "0,1" newline bitfld.long 0x0 13. "INCREASE_REGION_SIZE,Increase the maximum ATU Region size. When set the maximum ATU Region size is determined by CX_ATU_MAX_REGION_SIZE. When clear the maximum ATU Region size is 4 GB (default). Note: This register field is sticky." "0,1" newline bitfld.long 0x0 9.--10. "ATTR,When the address of an outbound TLP is matched to this region then the ATTR field of the TLP is changed to the value in this register. Note: This register field is sticky." "0,1,2,3" newline bitfld.long 0x0 8. "TD,This is a reserved field. Do not use. Note: This register field is sticky." "0,1" newline bitfld.long 0x0 5.--7. "TC,When the address of an outbound TLP is matched to this region then the TC field of the TLP is changed to the value in this register. Note: This register field is sticky." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x0 0.--4. 1. "TYPE,When the address of an outbound TLP is matched to this region then the TYPE field of the TLP is changed to the value in this register. Note: This register field is sticky." repeat.end repeat 8. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 )(list 0x0 0x200 0x400 0x600 0x800 0xA00 0xC00 0xE00 ) group.long ($2+0x4+0xC0000)++0x3 line.long 0x0 "IATU_REGION_CTRL_2_OFF_OUTBOUND_$1,iATU Region Control 2 Register." bitfld.long 0x0 31. "REGION_EN,Region Enable. This bit must be set to '1' for address translation to take place. Note: This register field is sticky." "0,1" newline bitfld.long 0x0 29. "INVERT_MODE,Invert Mode. When set the address matching region is inverted. Therefore an address match occurs when the untranslated address is in the region outside the defined range (Base Address to Limit Address). Note: This register field is sticky." "0,1" newline bitfld.long 0x0 28. "CFG_SHIFT_MODE,CFG Shift Mode. The iATU uses bits [27:12] of the untranslated address (on the XALI0/1/2 interface or AXI slave interface address) to form the BDF number of the outgoing CFG TLP. This supports the Enhanced Configuration Address Mapping.." "0,1" newline bitfld.long 0x0 27. "DMA_BYPASS,DMA Bypass Mode. Allows request TLPs which are initiated by the DMA controller to pass through the iATU untranslated. Note: This field is reserved for the SW product. You must set it to '0'. Note: This register field is sticky." "0,1" newline bitfld.long 0x0 23. "HEADER_SUBSTITUTE_EN,Header Substitute Enable. When enabled and region address is matched the iATU fully substitutes bytes 8-11 (for 3 DWORD header) or bytes 12-15 (for 4 DWORD header) of the outbound TLP header with the contents of the LWR_TARGET_RW.." "LWR_TARGET_RW in the..,LWR_TARGET_RW in the.." newline bitfld.long 0x0 22. "INHIBIT_PAYLOAD,Inhibit TLP Payload Data for TLP's in Matched Region; assign iATU region to be TLP without data. When enabled and region address is matched the iATU marks all TLPs as having no payload data by forcing the TLP header Fmt[1] bit =0.." "Fmt[1] =0/1 so that TLPs with or without data..,Fmt[1] =0 so that only TLP type without data is.." newline bitfld.long 0x0 21. "TLP_HEADER_FIELDS_BYPASS,TLP Header Fields Translation Bypass. In this mode header fields of the translated TLP is taken from your application transmit interface or if AMBA is configured from the AMBA sideband bus (slv_awmisc_info) and not from the.." "0,1" newline bitfld.long 0x0 20. "SNP,Serialize Non-Posted Requests. In this mode when the AXI Bridge is populated same AXI ID Non-Posted Read/Write Requests are transmitted on the wire if there are no other same ID Non-Posted Requests outstanding. Note: This register field is sticky." "0,1" newline bitfld.long 0x0 19. "FUNC_BYPASS,Function Number Translation Bypass. In this mode the function number of the translated TLP is taken from your application transmit interface and not from the CTRL_1_FUNC_NUM field of the 'iATU Control 1 Register' or the VF_NUMBER field of.." "0,1" newline bitfld.long 0x0 16. "TAG_SUBSTITUTE_EN,TAG Substitute Enable. When enabled and region address is matched the iATU substitutes the TAG field of the outbound TLP header with the contents of the TAG field in this register. The expected usage scenario is translation from AXI.." "0,1" newline hexmask.long.byte 0x0 8.--15. 1. "TAG,TAG. The substituted TAG field (byte 6) in the outgoing TLP header when TAG_SUBSTITUTE_EN is set. Note: This register field is sticky." newline hexmask.long.byte 0x0 0.--7. 1. "MSG_CODE,MSG TLPs (Message Code). When the address of an outbound TLP is matched to this region and the translated TLP TYPE field is Msg or MsgD; then the message field of the TLP is changed to the value in this register. Memory TLPs: (ST;Steering Tag)." repeat.end repeat 8. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 )(list 0x0 0x200 0x400 0x600 0x800 0xA00 0xC00 0xE00 ) group.long ($2+0x8+0xC0000)++0x3 line.long 0x0 "IATU_LWR_BASE_ADDR_OFF_OUTBOUND_$1,iATU Lower Base Address Register. The CX_ATU_MIN_REGION_SIZE configuration parameter (Value Range: 4 kB. 8 kB. 16 kB. 32 kB. 64 kB defaults to 64 kB) specifies the minimum size of an address translation region. For.." hexmask.long.tbyte 0x0 12.--31. 1. "LWR_BASE_RW,Forms bits [31:n] of the start address of the address region to be translated. n is log2(CX_ATU_MIN_REGION_SIZE) Note: This register field is sticky." newline hexmask.long.word 0x0 0.--11. 1. "LWR_BASE_HW,Forms bits [n-1:0] of the start address of the address region to be translated. The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary so these bits are always 0. A write to this location is ignored by the PCIe controller." repeat.end repeat 8. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 )(list 0x0 0x200 0x400 0x600 0x800 0xA00 0xC00 0xE00 ) group.long ($2+0xC+0xC0000)++0x3 line.long 0x0 "IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_$1,iATU Upper Base Address Register." hexmask.long 0x0 0.--31. 1. "UPPER_BASE_RW,Forms bits [63:32] of the start (and end) address of the address region to be translated. In systems with a 32-bit address space this register is not used and therefore writing to this register has no effect. Note: This register field is.." repeat.end repeat 8. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 )(list 0x0 0x200 0x400 0x600 0x800 0xA00 0xC00 0xE00 ) group.long ($2+0x10+0xC0000)++0x3 line.long 0x0 "IATU_LIMIT_ADDR_OFF_OUTBOUND_$1,iATU Limit Address Register." hexmask.long.tbyte 0x0 12.--31. 1. "LIMIT_ADDR_RW,Forms upper bits of the end address of the address region to be translated. Note: This register field is sticky." newline hexmask.long.word 0x0 0.--11. 1. "LIMIT_ADDR_HW,Forms lower bits of the end address of the address region to be translated. The end address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary so these bits are always all ones. A write to this location is ignored by the PCIe.." repeat.end repeat 8. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 )(list 0x0 0x200 0x400 0x600 0x800 0xA00 0xC00 0xE00 ) group.long ($2+0x14+0xC0000)++0x3 line.long 0x0 "IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_$1,iATU Lower Target Address Register." hexmask.long 0x0 0.--31. 1. "LWR_TARGET_RW_OUTBOUND,When HEADER_SUBSTITUTE_EN in IATU_REGION_CTRL_2_OFF_OUTBOUND_ is '0' (normal operation): - LWR_TARGET_RW[31:n] forms MSB's of the Lower Target part of the new address of the translated region; - LWR_TARGET_RW[n-1:0] are not used." repeat.end repeat 8. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 )(list 0x0 0x200 0x400 0x600 0x800 0xA00 0xC00 0xE00 ) group.long ($2+0x18+0xC0000)++0x3 line.long 0x0 "IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_$1,iATU Upper Target Address Register." hexmask.long 0x0 0.--31. 1. "UPPER_TARGET_RW,Forms bits [63:32] of the start address (Upper Target part) of the new address of the translated region. Note: This register field is sticky." repeat.end repeat 8. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 )(list 0x0 0x200 0x400 0x600 0x800 0xA00 0xC00 0xE00 ) group.long ($2+0x1C+0xC0000)++0x3 line.long 0x0 "IATU_REGION_CTRL_3_OFF_OUTBOUND_$1,iATU Region Control 3 Register." bitfld.long 0x0 31. "VF_ACTIVE,Virtual Function Active. Indicates that all of the outbound accesses are from virtual functions. For more details see VF_ACTIVE field. Note: This register field is sticky." "0,1" newline hexmask.long 0x0 3.--30. 1. "RSVDP_VF_NUMBER,Reserved for future use." newline bitfld.long 0x0 0.--2. "VF_NUMBER,Virtual Function Number. When the address of an outbound TLP is matched to this region and the FUNC_BYPASS field in the 'iATU Control 2 Register' is '0' then this field used in generating the Function part of the requester ID (RID) field of.." "0,1,2,3,4,5,6,7" repeat.end repeat 8. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 )(list 0x0 0x200 0x400 0x600 0x800 0xA00 0xC00 0xE00 ) group.long ($2+0x100+0xC0000)++0x3 line.long 0x0 "IATU_REGION_CTRL_1_OFF_INBOUND_$1,iATU Region Control 1 Register." bitfld.long 0x0 20. "CTRL_1_FUNC_NUM,Function Number. - MEM-I/O: When the Address and BAR matching logic in the controller indicate that a MEM-I/O transaction matches a BAR in the function corresponding to this value then address translation proceeds. This check is only.." "?,When the destination function number as.." newline bitfld.long 0x0 13. "INCREASE_REGION_SIZE,Increase the maximum ATU Region size. When set the maximum ATU Region size is determined by CX_ATU_MAX_REGION_SIZE. When clear the maximum ATU Region size is 4 GB (default). Note: This register field is sticky." "0,1" newline bitfld.long 0x0 9.--10. "ATTR,When the ATTR field of an inbound TLP is matched to this value then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the 'ATTR Match Enable' bit of the 'iATU Control 2 Register' is.." "0,1,2,3" newline bitfld.long 0x0 8. "TD,When the TD field of an inbound TLP is matched to this value then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the 'TD Match Enable' bit of the 'iATU Control 2 Register' is set." "0,1" newline bitfld.long 0x0 5.--7. "TC,When the TC field of an inbound TLP is matched to this value then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the 'TC Match Enable' bit of the 'iATU Control 2 Register' is set." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x0 0.--4. 1. "TYPE,When the TYPE field of an inbound TLP is matched to this value then address translation proceeds (when all other enabled field-matches are successful). Note: This register field is sticky." repeat.end repeat 8. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 )(list 0x0 0x200 0x400 0x600 0x800 0xA00 0xC00 0xE00 ) group.long ($2+0x104+0xC0000)++0x3 line.long 0x0 "IATU_REGION_CTRL_2_OFF_INBOUND_$1,iATU Region Control 2 Register." bitfld.long 0x0 31. "REGION_EN,Region Enable. This bit must be set to '1' for address translation to take place. Note: This register field is sticky." "0,1" newline bitfld.long 0x0 30. "MATCH_MODE,Match Mode. Determines Inbound matching mode for TLPs. The mode depends on the type of TLP that is received as follows: For MEM-I/O TLPs this field is interpreted as follows: - 0: Address Match Mode. The iATU operates using addresses as in.." "Address Match Mode,Vendor ID Match Mode" newline bitfld.long 0x0 29. "INVERT_MODE,Invert Mode. When set the address matching region is inverted. Therefore an address match occurs when the untranslated address is in the region outside the defined range (Base Address to Limit Address). Note: This register field is sticky." "0,1" newline bitfld.long 0x0 28. "CFG_SHIFT_MODE,CFG Shift Mode. This is useful for CFG transactions where the PCIe configuration mechanism maps bits [27:12] of the address to the bus/device and function number. This allows a CFG configuration space to be located in any 256MB window of.." "0,1" newline bitfld.long 0x0 27. "FUZZY_TYPE_MATCH_CODE,Fuzzy Type Match Mode. When enabled the iATU relaxes the matching of the TLP TYPE field against the expected TYPE field so that - CfgRd0 and CfgRd1 TLPs are seen as identical. Similarly with CfgWr0 and CfgWr1. - MWr MRd and MRdLk.." "0,1" newline bitfld.long 0x0 26. "VFBAR_MATCH_MODE_EN,VF BAR Match Mode enable. When set Virtual Function BAR matching is used which allows all VFs in a PF which match a BAR to be matched with a single ATU region. Note: This register field is sticky." "0,1" newline bitfld.long 0x0 24.--25. "RESPONSE_CODE,Response Code. Defines the type of response to give for accesses matching this region. This overrides the normal RADM filter response. Note that this feature is not available for any region where Single Address Location Translate is.." "Normal RADM filter response is used,Unsupported request,?,?" newline bitfld.long 0x0 23. "SINGLE_ADDR_LOC_TRANS_EN,Single Address Location Translate Enable. When enabled Rx TLPs can be translated to a single address location as determined by the target address register of the iATU region. The main usage scenario is translation of Messages.." "0,1" newline bitfld.long 0x0 21. "MSG_CODE_MATCH_EN,Message Code Match Enable (Msg TLPS). Ensures that a successful message Code TLP field comparison match (see Message Code field of the 'iATU Control 2 Register') occurs (in MSG transactions) for address translation to proceed. ST Match.." "0,1" newline bitfld.long 0x0 20. "VF_MATCH_EN,Virtual Function Number Match Enable. Ensures that a successful Virtual Function Number TLP field comparison match (see Virtual Function Number field of the 'iATU Control 3 Register') occurs (in MEM-I/O transactions) for address translation.." "0,1" newline bitfld.long 0x0 19. "FUNC_NUM_MATCH_EN,Function Number Match Enable. Ensures that a successful Function Number TLP field comparison match (see Function Number field of the 'iATU Control 1 Register') occurs (in MEM-I/O and CFG0/CFG1 transactions) for address translation to.." "0,1" newline bitfld.long 0x0 16. "ATTR_MATCH_EN,ATTR Match Enable. Ensures that a successful ATTR TLP field comparison match (see ATTR field of the 'iATU Control 1 Register') occurs for address translation to proceed. Note: This register field is sticky." "0,1" newline bitfld.long 0x0 15. "TD_MATCH_EN,TD Match Enable. Ensures that a successful TD TLP field comparison match (see TD field of the 'iATU Control 1 Register') occurs for address translation to proceed. Note: This register field is sticky." "0,1" newline bitfld.long 0x0 14. "TC_MATCH_EN,TC Match Enable. Ensures that a successful TC TLP field comparison match (see TC field of the 'iATU Control 1 Register') occurs for address translation to proceed. Note: This register field is sticky." "0,1" newline bitfld.long 0x0 13. "MSG_TYPE_MATCH_MODE,Message Type Match Mode. When enabled and if single address location translate enable is set then inbound TLPs of type MSG/MSGd which match the type field of the iatu_region_ctrl_1_OFF_inbound register (=>TYPE[4:3]=2'b10) will be.." "0,1" newline bitfld.long 0x0 8.--10. "BAR_NUM,BAR Number. When the BAR number of an inbound MEM or IO TLP ' that is matched by the normal internal BAR address matching mechanism ' is the same as this field address translation proceeds (when all other enabled field-matches are successful)." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x0 0.--7. 1. "MSG_CODE,MSG TLPs: (Message Code). When the TYPE field of an inbound Msg/MsgD TLP is matched to this value then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the 'Message Code Match.." repeat.end repeat 8. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 )(list 0x0 0x200 0x400 0x600 0x800 0xA00 0xC00 0xE00 ) group.long ($2+0x108+0xC0000)++0x3 line.long 0x0 "IATU_LWR_BASE_ADDR_OFF_INBOUND_$1,iATU Lower Base Address Register. The CX_ATU_MIN_REGION_SIZE configuration parameter (Value Range: 4 kB. 8 kB. 16 kB. 32 kB. 64 kB defaults to 64 kB) specifies the minimum size of an address translation region. For.." hexmask.long.tbyte 0x0 12.--31. 1. "LWR_BASE_RW,Forms bits [31:n] of the start address of the address region to be translated. n is log2(CX_ATU_MIN_REGION_SIZE) Note: This register field is sticky." newline hexmask.long.word 0x0 0.--11. 1. "LWR_BASE_HW,Forms bits [n-1:0] of the start address of the address region to be translated. The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary so these bits are always 0. A write to this location is ignored by the PCIe controller." repeat.end repeat 8. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 )(list 0x0 0x200 0x400 0x600 0x800 0xA00 0xC00 0xE00 ) group.long ($2+0x10C+0xC0000)++0x3 line.long 0x0 "IATU_UPPER_BASE_ADDR_OFF_INBOUND_$1,iATU Upper Base Address Register." hexmask.long 0x0 0.--31. 1. "UPPER_BASE_RW,Forms bits [63:32] of the start (and end) address of the address region to be translated. Note: This register field is sticky." repeat.end repeat 8. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 )(list 0x0 0x200 0x400 0x600 0x800 0xA00 0xC00 0xE00 ) group.long ($2+0x110+0xC0000)++0x3 line.long 0x0 "IATU_LIMIT_ADDR_OFF_INBOUND_$1,iATU Limit Address Register." hexmask.long.tbyte 0x0 12.--31. 1. "LIMIT_ADDR_RW,Forms upper bits of the end address of the address region to be translated. Note: This register field is sticky." newline hexmask.long.word 0x0 0.--11. 1. "LIMIT_ADDR_HW,Forms lower bits of the end address of the address region to be translated. The end address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary so these bits are always all ones. A write to this location is ignored by the PCIe.." repeat.end repeat 8. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 )(list 0x0 0x200 0x400 0x600 0x800 0xA00 0xC00 0xE00 ) group.long ($2+0x114+0xC0000)++0x3 line.long 0x0 "IATU_LWR_TARGET_ADDR_OFF_INBOUND_$1,iATU Lower Target Address Register." hexmask.long.tbyte 0x0 12.--31. 1. "LWR_TARGET_RW,Forms MSB's of the Lower Target part of the new address of the translated region. These bits are always '0'. - Field size depends on log2(CX_ATU_MIN_REGION_SIZE) in address match mode. - Field size depends on log2(BAR_MASK+1) in BAR match.." newline hexmask.long.word 0x0 0.--11. 1. "LWR_TARGET_HW,Forms the LSB's of the Lower Target part of the new address of the translated region. The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary (in address match mode); and to the Bar size boundary (in BAR match mode) so.." repeat.end repeat 8. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 )(list 0x0 0x200 0x400 0x600 0x800 0xA00 0xC00 0xE00 ) group.long ($2+0x118+0xC0000)++0x3 line.long 0x0 "IATU_UPPER_TARGET_ADDR_OFF_INBOUND_$1,iATU Upper Target Address Register." hexmask.long 0x0 0.--31. 1. "UPPER_TARGET_RW,Forms bits [63:32] of the start address (Upper Target part) of the new address of the translated region. In systems with a 32-bit address space this register is not used and therefore writing to this register has no effect. Note: This.." repeat.end repeat 8. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 )(list 0x0 0x200 0x400 0x600 0x800 0xA00 0xC00 0xE00 ) group.long ($2+0x11C+0xC0000)++0x3 line.long 0x0 "IATU_REGION_CTRL_3_OFF_INBOUND_$1,iATU Region Control 3 Register." rbitfld.long 0x0 31. "VF_ACTIVE,Reserved. Not used." "0,1" newline hexmask.long 0x0 3.--30. 1. "RSVDP_VF_NUMBER,Reserved for future use." newline bitfld.long 0x0 0.--2. "VF_NUMBER,Virtual Function Number. When the Address and BAR matching logic in the controller indicates that a MEM-I/O transaction matches a BAR in the virtual function corresponding to this value then address translation proceeds. This check is only.." "0,1,2,3,4,5,6,7" repeat.end tree.end tree "PF0_PORT_LOGIC (Port Logic)" group.long (0x0+0x700)++0x27 line.long 0x0 "ACK_LATENCY_TIMER_OFF,Ack Latency Timer and Replay Timer Register." hexmask.long.word 0x0 16.--31. 1. "REPLAY_TIME_LIMIT,Replay Timer Limit. The replay timer expires when it reaches this limit. The controller initiates a replay upon reception of a NAK or when the replay timer expires. For more details see 'Transmit Replay'. You can modify the effective.." newline hexmask.long.word 0x0 0.--15. 1. "ROUND_TRIP_LATENCY_TIME_LIMIT,Ack Latency Timer Limit. The Ack latency timer expires when it reaches this limit. For more details see 'Ack Scheduling'. You can modify the effective timer limit with the TIMER_MOD_ACK_NAK field of the.." line.long 0x4 "VENDOR_SPEC_DLLP_OFF,Vendor Specific DLLP Register." hexmask.long 0x4 0.--31. 1. "VENDOR_SPEC_DLLP,Vendor Specific DLLP Register. Used to send a specific PCI Express DLLP. Your application writes the 8-bit DLLP Type and 24-bits of Payload data into this register then sets the field VENDOR_SPECIFIC_DLLP_REQ of PORT_LINK_CTRL_OFF to.." line.long 0x8 "PORT_FORCE_OFF,Port Force Link Register." hexmask.long.byte 0x8 24.--31. 1. "RSVDP_24,Reserved for future use." newline bitfld.long 0x8 23. "DO_DESKEW_FOR_SRIS,Use the transitions from TS2 to Logical Idle Symbol SKP OS to Logical Idle Symbol EIEOS to Logical Idle Symbol and FTS Sequence to SKP OS to do deskew instead of using received SKP OS or TS1 to TS2 transition if DO_DESKEW_FOR_SRIS.." "0,1" newline rbitfld.long 0x8 22. "RSVDP_22,Reserved for future use." "0,1" newline hexmask.long.byte 0x8 16.--21. 1. "LINK_STATE,Forced LTSSM State. The LTSSM state that the controller is forced to when you set the FORCE_EN bit (Force Link). LTSSM state encoding is defined by the lts_state variable in workspace/src/Layer1/smlh_ltssm.v. Note: This register field is sticky." newline bitfld.long 0x8 15. "FORCE_EN,Force Link. The controller supports a testing and debug capability to allow your software to force the LTSSM state machine into a specific state and to force the controller to transmit a specific Link Command. Asserting this bit triggers the.." "0,1" newline rbitfld.long 0x8 12.--14. "RSVDP_12,Reserved for future use." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x8 8.--11. 1. "FORCED_LTSSM,Forced Link Command. The link command that the controller is forced to transmit when you set FORCE_EN bit (Force Link). Link command encoding is defined by the ltssm_cmd variable in workspace/src/Layer1/smlh_ltssm.v. Note: This register.." newline hexmask.long.byte 0x8 0.--7. 1. "LINK_NUM,Link Number. Not used for endpoint. Not used for M-PCIe. Note: This register field is sticky." line.long 0xC "ACK_F_ASPM_CTRL_OFF,Ack Frequency and L0-L1 ASPM Control Register." rbitfld.long 0xC 31. "RSVDP_31,Reserved for future use." "0,1" newline bitfld.long 0xC 30. "ENTER_ASPM,ASPM L1 Entry Control. - 1: Controller enters ASPM L1 after a period in which it has been idle. - 0: Controller enters ASPM L1 only after idle period during which both receive and transmit are in L0s. Note: This register field is sticky." "Controller enters ASPM L1 only after idle period..,Controller enters ASPM L1 after a period in.." newline bitfld.long 0xC 27.--29. "L1_ENTRANCE_LATENCY,L1 Entrance Latency. Value range is: - 000: 1 us - 001: 2 us - 010: 4 us - 011: 8 us - 100: 16 us - 101: 32 us - 110 or 111: 64 us Note: Programming this timer with a value greater that 32us has no effect unless extended sync is used.." "0,1,2,3,4,5,6,7" newline bitfld.long 0xC 24.--26. "L0S_ENTRANCE_LATENCY,L0s Entrance Latency. Values correspond to: - 000: 1 us - 001: 2 us - 010: 3 us - 011: 4 us - 100: 5 us - 101: 6 us - 110 or 111: 7 us This field is applicable to STALL while in L0 for M-PCIe. Note: This register field is sticky." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0xC 16.--23. 1. "COMMON_CLK_N_FTS,Common Clock N_FTS. This is the N_FTS when common clock is used. The number of Fast Training Sequence ordered sets to be transmitted when transitioning from L0s to L0. The maximum number of FTS ordered-sets that a component can request.." newline hexmask.long.byte 0xC 8.--15. 1. "ACK_N_FTS,N_FTS. The number of Fast Training Sequence ordered sets to be transmitted when transitioning from L0s to L0. The maximum number of FTS ordered-sets that a component can request is 255. The controller does not support a value of zero; a value.." newline hexmask.long.byte 0xC 0.--7. 1. "ACK_FREQ,Ack Frequency. The controller accumulates the number of pending ACKs specified here (up to 255) before scheduling an ACK DLLP. - 0: Indicates that this Ack Frequency Counter feature is turned off. The controller generates a low-priority ACK.." line.long 0x10 "PORT_LINK_CTRL_OFF,Port Link Control Register." hexmask.long.byte 0x10 28.--31. 1. "RSVDP_28,Reserved for future use." newline bitfld.long 0x10 27. "TRANSMIT_LANE_REVERSALE_ENABLE,TRANSMIT_LANE_REVERSALE_ENABLE is an internally reserved field. Do not use. Note: This register field is sticky." "0,1" newline bitfld.long 0x10 26. "EXTENDED_SYNCH,EXTENDED_SYNCH is an internally reserved field. Do not use. Note: This register field is sticky." "0,1" newline bitfld.long 0x10 25. "CORRUPT_LCRC_ENABLE,CORRUPT_LCRC_ENABLE is an internally reserved field. Do not use. Note: This register field is sticky." "0,1" newline bitfld.long 0x10 24. "BEACON_ENABLE,BEACON_ENABLE is an internally reserved field. Do not use. Note: This register field is sticky." "0,1" newline hexmask.long.byte 0x10 16.--21. 1. "LINK_CAPABLE,Link Mode Enable. Sets the number of lanes in the link that you want to connect to the link partner. When you have unused lanes in your system then you must change the value in this register to reflect the number of lanes. You must also.." newline hexmask.long.byte 0x10 12.--15. 1. "RSVDP_12,Reserved for future use." newline hexmask.long.byte 0x10 8.--11. 1. "LINK_RATE,LINK_RATE is an internally reserved field. Do not use. Note: This register field is sticky." newline bitfld.long 0x10 7. "FAST_LINK_MODE,Fast Link Mode. Sets all internal LTSSM millisecond timers to Fast Mode for speeding up simulation. Forces the LTSSM training (link initialization) to use shorter time-outs and to link up faster. The default scaling factor can be changed.." "0,1" newline bitfld.long 0x10 6. "LINK_DISABLE,LINK_DISABLE is an internally reserved field. Do not use. Note: This register field is sticky." "0,1" newline bitfld.long 0x10 5. "DLL_LINK_EN,DLL Link Enable. Enables link initialization. When DLL Link Enable =0 the controller does not transmit InitFC DLLPs and does not establish a link. Note: This register field is sticky." "0,1" newline rbitfld.long 0x10 4. "RSVDP_4,Reserved for future use." "0,1" newline bitfld.long 0x10 3. "RESET_ASSERT,Reset Assert. Triggers a recovery and forces the LTSSM to the hot reset state (downstream port only). Note: This register field is sticky." "0,1" newline bitfld.long 0x10 2. "LOOPBACK_ENABLE,Loopback Enable. Turns on loopback. For more details see 'Loopback'. For M-PCIe to force the master to enter Digital Loopback mode you must set this field to '1' during Configuration.start state(initial discovery/configuration). M-PCIe.." "0,1" newline bitfld.long 0x10 1. "SCRAMBLE_DISABLE,Scramble Disable. Turns off data scrambling. Note: This register field is sticky." "0,1" newline bitfld.long 0x10 0. "VENDOR_SPECIFIC_DLLP_REQ,Vendor Specific DLLP Request. When software writes a '1' to this bit the controller transmits the DLLP contained in the VENDOR_SPEC_DLLP field of VENDOR_SPEC_DLLP_OFF. Reading from this self-clearing register field always.." "0,1" line.long 0x14 "LANE_SKEW_OFF,Lane Skew Register." bitfld.long 0x14 31. "DISABLE_LANE_TO_LANE_DESKEW,Disable Lane-to-Lane Deskew. Causes the controller to disable the internal Lane-to-Lane deskew logic. Note: This register field is sticky." "0,1" newline hexmask.long.byte 0x14 27.--30. 1. "IMPLEMENT_NUM_LANES,Implementation-specific Number of Lanes. Set the implementation-specific number of lanes. Allowed values are: - 4'b0000: 1 lane - 4'b0001: 2 lanes - 4'b0011: 4 lanes - 4'b0111: 8 lanes - 4'b1111: 16 lanes The number of lanes to be.." newline bitfld.long 0x14 26. "ELASTIC_BUFFER_MODE,Selects Elasticity Buffer operating mode: 0: Nominal Half Full Buffer mode 1: Nominal Empty Buffer Mode Note: This register field is sticky." "Nominal Half Full Buffer mode,Nominal Empty Buffer Mode" newline bitfld.long 0x14 25. "ACK_NAK_DISABLE,Ack/Nak Disable. Prevents the controller from sending ACK and NAK DLLPs. Note: This register field is sticky." "0,1" newline bitfld.long 0x14 24. "FLOW_CTRL_DISABLE,Flow Control Disable. Prevents the controller from sending FC DLLPs. Note: This register field is sticky." "0,1" newline hexmask.long.tbyte 0x14 0.--23. 1. "INSERT_LANE_SKEW,INSERT_LANE_SKEW is an internally reserved field. Do not use. Note: This register field is sticky." line.long 0x18 "TIMER_CTRL_MAX_FUNC_NUM_OFF,Timer Control and Max Function Number Register." rbitfld.long 0x18 31. "RSVDP_31,Reserved for future use." "0,1" newline bitfld.long 0x18 29.--30. "FAST_LINK_SCALING_FACTOR,Fast Link Timer Scaling Factor. Sets the scaling factor of LTSSM timer when FAST_LINK_MODE field in PORT_LINK_CTRL_OFF is set to '1'. - 0: Scaling Factor is 1024 (1ms is 1us *a) - 1: Scaling Factor is 256 (1ms is 4us) - 2:.." "Scaling Factor is 1024,Scaling Factor is 256,Scaling Factor is 64,Scaling Factor is 16" newline hexmask.long.byte 0x18 24.--28. 1. "UPDATE_FREQ_TIMER,UPDATE_FREQ_TIMER is an internally reserved field. Do not use. Note: This register field is sticky." newline hexmask.long.byte 0x18 19.--23. 1. "TIMER_MOD_ACK_NAK,Ack Latency Timer Modifier. Increases the timer value for the Ack latency timer in increments of 64 clock cycles. A value of '0' represents no modification to the timer value. For more details see the ROUND_TRIP_LATENCY_TIME_LIMIT.." newline hexmask.long.byte 0x18 14.--18. 1. "TIMER_MOD_REPLAY_TIMER,Replay Timer Limit Modifier. Increases the time-out value for the replay timer in increments of 64 clock cycles at Gen1 or Gen2 speed and in increments of 256 clock cycles at Gen3 speed. A value of '0' represents no modification.." newline hexmask.long.byte 0x18 8.--13. 1. "RSVDP_8,Reserved for future use." newline hexmask.long.byte 0x18 0.--7. 1. "MAX_FUNC_NUM,Maximum function number that can be used in a request. Configuration requests targeted at function numbers above this value are returned with UR (unsupported request). Note: This register field is sticky." line.long 0x1C "SYMBOL_TIMER_FILTER_1_OFF,Symbol Timer Register and Filter Mask 1 Register. The Filter Mask 1 Register modifies the RADM filtering and error handling rules. For more details. see the 'Receive Filtering' section. In each case. '0' applies the associated.." hexmask.long.word 0x1C 16.--31. 1. "MASK_RADM_1,Filter Mask 1. The Filter Mask 1 Register modifies the RADM filtering and error handling rules. For more details see the 'Receive Filtering' section. In each case '0' applies the associated filtering rule and '1' masks the associated.." newline bitfld.long 0x1C 15. "DISABLE_FC_WD_TIMER,Disable FC Watchdog Timer. Note: This register field is sticky." "0,1" newline hexmask.long.byte 0x1C 11.--14. 1. "EIDLE_TIMER,EIDLE_TIMER is an internally reserved field. Do not use. Note: This register field is sticky." newline hexmask.long.word 0x1C 0.--10. 1. "SKP_INT_VAL,SKP Interval Value. The number of symbol times to wait between transmitting SKP ordered sets. Note that the controller actually waits the number of symbol times in this register plus 1 between transmitting SKP ordered sets. Your application.." line.long 0x20 "FILTER_MASK_2_OFF,Filter Mask 2 Register. This register modifies the RADM filtering and error handling rules. For more details. see the 'Receive Filtering' section. In each case. '0' applies the associated filtering rule and '1' masks the associated.." hexmask.long 0x20 0.--31. 1. "MASK_RADM_2,Filter Mask 2. This field modifies the RADM filtering and error handling rules. For more details see the 'Receive Filtering' section. In each case '0' applies the associated filtering rule and '1' masks the associated filtering rule." line.long 0x24 "AMBA_MUL_OB_DECOMP_NP_SUB_REQ_CTRL_OFF,AMBA Multiple Outbound Decomposed NP SubRequests Control Register." hexmask.long 0x24 1.--31. 1. "RSVDP_1,Reserved for future use." newline bitfld.long 0x24 0. "OB_RD_SPLIT_BURST_EN,Enable AMBA Multiple Outbound Decomposed NP SubRequests. This bit when set to '0' disables the possibility of having multiple outstanding non-posted requests that were derived from decomposition of an outbound AMBA request. For more.." "0,1" rgroup.long (0x28+0x700)++0x13 line.long 0x0 "PL_DEBUG0_OFF,Debug Register 0" hexmask.long 0x0 0.--31. 1. "DEB_REG_0,The value on cxpl_debug_info[31:0]." line.long 0x4 "PL_DEBUG1_OFF,Debug Register 1" hexmask.long 0x4 0.--31. 1. "DEB_REG_1,The value on cxpl_debug_info[63:32]." line.long 0x8 "TX_P_FC_CREDIT_STATUS_OFF,Transmit Posted FC Credit Status" hexmask.long.word 0x8 20.--31. 1. "RSVDP_TX_P_FC_CREDIT_STATUS,Reserved for future use." newline hexmask.long.byte 0x8 12.--19. 1. "TX_P_HEADER_FC_CREDIT,Transmit Posted Header FC Credits. The posted Header credits advertised by the receiver at the other end of the link updated with each UpdateFC DLLP. Default value depends on the number of advertised credits for header and data.." newline hexmask.long.word 0x8 0.--11. 1. "TX_P_DATA_FC_CREDIT,Transmit Posted Data FC Credits. The posted Data credits advertised by the receiver at the other end of the link updated with each UpdateFC DLLP. Default value depends on the number of advertised credits for header and data Scaled.." line.long 0xC "TX_NP_FC_CREDIT_STATUS_OFF,Transmit Non-Posted FC Credit Status" hexmask.long.word 0xC 20.--31. 1. "RSVDP_TX_NP_FC_CREDIT_STATUS,Reserved for future use." newline hexmask.long.byte 0xC 12.--19. 1. "TX_NP_HEADER_FC_CREDIT,Transmit Non-Posted Header FC Credits. The non-posted Header credits advertised by the receiver at the other end of the link updated with each UpdateFC DLLP. Default value depends on the number of advertised credits for header and.." newline hexmask.long.word 0xC 0.--11. 1. "TX_NP_DATA_FC_CREDIT,Transmit Non-Posted Data FC Credits. The non-posted Data credits advertised by the receiver at the other end of the link updated with each UpdateFC DLLP. Default value depends on the number of advertised credits for header and data.." line.long 0x10 "TX_CPL_FC_CREDIT_STATUS_OFF,Transmit Completion FC Credit Status" hexmask.long.word 0x10 20.--31. 1. "RSVDP_TX_CPL_FC_CREDIT_STATUS,Reserved for future use." newline hexmask.long.byte 0x10 12.--19. 1. "TX_CPL_HEADER_FC_CREDIT,Transmit Completion Header FC Credits. The Completion Header credits advertised by the receiver at the other end of the link updated with each UpdateFC DLLP. Default value depends on the number of advertised credits for header.." newline hexmask.long.word 0x10 0.--11. 1. "TX_CPL_DATA_FC_CREDIT,Transmit Completion Data FC Credits. The Completion Data credits advertised by the receiver at the other end of the link updated with each UpdateFC DLLP. Default value depends on the number of advertised credits for header and data.." group.long (0x3C+0x700)++0x3 line.long 0x0 "QUEUE_STATUS_OFF,Queue Status" bitfld.long 0x0 31. "TIMER_MOD_FLOW_CONTROL_EN,FC Latency Timer Override Enable. When this bit is set the value from the 'FC Latency Timer Override Value' field in this register will override the FC latency timer value that the controller calculates according to the PCIe.." "0,1" newline rbitfld.long 0x0 29.--30. "RSVDP_29,Reserved for future use." "0,1,2,3" newline hexmask.long.word 0x0 16.--28. 1. "TIMER_MOD_FLOW_CONTROL,FC Latency Timer Override Value. When you set the 'FC Latency Timer Override Enable' in this register the value in this field will override the FC latency timer value that the controller calculates according to the PCIe.." newline rbitfld.long 0x0 13. "RX_SERIALIZATION_Q_NON_EMPTY,Receive Serialization Queue Not Empty. Indicates there is data in the serialization queue." "0,1" newline hexmask.long.word 0x0 4.--12. 1. "RSVDP_4,Reserved for future use." newline bitfld.long 0x0 3. "RX_QUEUE_OVERFLOW,Receive Credit Queue Overflow. Indicates insufficient buffer space available to write to the P/NP/CPL credit queue." "0,1" newline rbitfld.long 0x0 2. "RX_QUEUE_NON_EMPTY,Receive Credit Queue Not Empty. Indicates there is data in one or more of the receive buffers." "0,1" newline rbitfld.long 0x0 1. "TX_RETRY_BUFFER_NE,Transmit Retry Buffer Not Empty. Indicates that there is data in the transmit retry buffer." "0,1" newline rbitfld.long 0x0 0. "RX_TLP_FC_CREDIT_NON_RETURN,Received TLP FC Credits Not Returned. Indicates that the controller has received a TLP but has not yet sent an UpdateFC DLLP indicating that the credits for that TLP have been restored by the receiver at the other end of the.." "0,1" rgroup.long (0x40+0x700)++0x7 line.long 0x0 "VC_TX_ARBI_1_OFF,VC Transmit Arbitration Register 1" hexmask.long.byte 0x0 24.--31. 1. "WRR_WEIGHT_VC_3,WRR Weight for VC3. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R" newline hexmask.long.byte 0x0 16.--23. 1. "WRR_WEIGHT_VC_2,WRR Weight for VC2. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R" newline hexmask.long.byte 0x0 8.--15. 1. "WRR_WEIGHT_VC_1,WRR Weight for VC1. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R" newline hexmask.long.byte 0x0 0.--7. 1. "WRR_WEIGHT_VC_0,WRR Weight for VC0. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R" line.long 0x4 "VC_TX_ARBI_2_OFF,VC Transmit Arbitration Register 2" hexmask.long.byte 0x4 24.--31. 1. "WRR_WEIGHT_VC_7,WRR Weight for VC7. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R" newline hexmask.long.byte 0x4 16.--23. 1. "WRR_WEIGHT_VC_6,WRR Weight for VC6. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R" newline hexmask.long.byte 0x4 8.--15. 1. "WRR_WEIGHT_VC_5,WRR Weight for VC5. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R" newline hexmask.long.byte 0x4 0.--7. 1. "WRR_WEIGHT_VC_4,WRR Weight for VC4. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R" group.long (0x48+0x700)++0xB line.long 0x0 "VC0_P_RX_Q_CTRL_OFF,Segmented-Buffer VC0 Posted Receive Queue Control." bitfld.long 0x0 31. "VC_ORDERING_RX_Q,VC Ordering for Receive Queues. Determines the VC ordering rule for the receive queues used only in the segmented-buffer configuration: - 1: Strict ordering higher numbered VCs have higher priority - 0: Round robin Note: This register.." "Round robin,Strict ordering" newline bitfld.long 0x0 30. "TLP_TYPE_ORDERING_VC0,TLP Type Ordering for VC0. Determines the TLP type ordering rule for VC0 receive queues used only in the segmented-buffer configuration: - 1: PCIe ordering rules (recommended) - 0: Strict ordering: posted completion then.." "Strict ordering: posted,PCIe ordering rules" newline bitfld.long 0x0 28.--29. "RESERVED5,Reserved. Note: This register field is sticky." "0,1,2,3" newline bitfld.long 0x0 26.--27. "VC0_P_DATA_SCALE,VC0 Scale Posted Data Credites. Note: This register field is sticky." "0,1,2,3" newline bitfld.long 0x0 24.--25. "VC0_P_HDR_SCALE,VC0 Scale Posted Header Credites. Note: This register field is sticky." "0,1,2,3" newline bitfld.long 0x0 21.--23. "VC0_P_TLP_Q_MODE,Reserved. Note: This register field is sticky." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 20. "RESERVED4,Reserved. Note: This register field is sticky." "0,1" newline hexmask.long.byte 0x0 12.--19. 1. "VC0_P_HEADER_CREDIT,VC0 Posted Header Credits. The number of initial posted header credits for VC0 used only in the segmented-buffer configuration. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R (sticky) Note: This.." newline hexmask.long.word 0x0 0.--11. 1. "VC0_P_DATA_CREDIT,VC0 Posted Data Credits. The number of initial posted data credits for VC0 used only in the segmented-buffer configuration. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R (sticky) Note: This.." line.long 0x4 "VC0_NP_RX_Q_CTRL_OFF,Segmented-Buffer VC0 Non-Posted Receive Queue Control." hexmask.long.byte 0x4 28.--31. 1. "RESERVED7,Reserved. Note: This register field is sticky." newline bitfld.long 0x4 26.--27. "VC0_NP_DATA_SCALE,VC0 Scale Non-Posted Data Credites. Note: This register field is sticky." "0,1,2,3" newline bitfld.long 0x4 24.--25. "VC0_NP_HDR_SCALE,VC0 Scale Non-Posted Header Credites. Note: This register field is sticky." "0,1,2,3" newline bitfld.long 0x4 21.--23. "VC0_NP_TLP_Q_MODE,Reserved. Note: This register field is sticky." "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 20. "RESERVED6,Reserved. Note: This register field is sticky." "0,1" newline hexmask.long.byte 0x4 12.--19. 1. "VC0_NP_HEADER_CREDIT,VC0 Non-Posted Header Credits. The number of initial non-posted header credits for VC0 used only in the segmented-buffer configuration. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R (sticky).." newline hexmask.long.word 0x4 0.--11. 1. "VC0_NP_DATA_CREDIT,VC0 Non-Posted Data Credits. The number of initial non-posted data credits for VC0 used only in the segmented-buffer configuration. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R (sticky) Note:.." line.long 0x8 "VC0_CPL_RX_Q_CTRL_OFF,Segmented-Buffer VC0 Completion Receive Queue Control." hexmask.long.byte 0x8 28.--31. 1. "RESERVED9,Reserved. Note: This register field is sticky." newline bitfld.long 0x8 26.--27. "VC0_CPL_DATA_SCALE,VC0 Scale CPL Data Credites. Note: This register field is sticky." "0,1,2,3" newline bitfld.long 0x8 24.--25. "VC0_CPL_HDR_SCALE,VC0 Scale CPL Header Credites. Note: This register field is sticky." "0,1,2,3" newline bitfld.long 0x8 21.--23. "VC0_CPL_TLP_Q_MODE,Reserved. Note: This register field is sticky." "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 20. "RESERVED8,Reserved. Note: This register field is sticky." "0,1" newline hexmask.long.byte 0x8 12.--19. 1. "VC0_CPL_HEADER_CREDIT,VC0 Completion Header Credits. The number of initial Completion header credits for VC0 used only in the segmented-buffer configuration. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R (sticky).." newline hexmask.long.word 0x8 0.--11. 1. "VC0_CPL_DATA_CREDIT,VC0 Completion Data Credits. The number of initial Completion data credits for VC0 used only in the segmented-buffer configuration. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R (sticky) Note:.." group.long (0x10C+0x700)++0x3 line.long 0x0 "GEN2_CTRL_OFF,This register is used to control various functions of the controller related to link training. lane reversal. and equalization." rbitfld.long 0x0 31. "RSVDP_31,Reserved for future use." "0,1" newline bitfld.long 0x0 30. "FORCE_LANE_FLIP,Enable to force the LANE_UNDER_TEST physical lane flips to logical lane 0. All the other physical lanes are turned off. The LINK_CAPABLE register must be set to 1 and only x1 link can be formed if the FORCE_LANE_FLIP register is set to 1." "0,1" newline hexmask.long.byte 0x0 24.--27. 1. "LANE_UNDER_TEST,The Lane Under Test is the lane for Forced Lane Flip or for Loopback Eq. The value is from 0 to CX_NL. Only one lane is configured each time. The default of this field is the CX_DEFAULT_LANE_UNDER_TEST configuration parameter. This field.." newline rbitfld.long 0x0 22.--23. "RSVDP_22,Reserved for future use." "0,1,2,3" newline bitfld.long 0x0 21. "GEN1_EI_INFERENCE,Electrical Idle Inference Mode at Gen1 Rate. Programmable mode to determine inferred electrical idle (EI) in Recovery.Speed or Loopback.Active (as slave) state at Gen1 speed by looking for a '1' value on RxElecIdle instead of looking.." "Use RxElecIdle signal to infer Electrical Idle,Use RxValid signal to infer Electrical Idle" newline bitfld.long 0x0 20. "SEL_DEEMPHASIS,Used to set the de-emphasis level for upstream ports. This bit selects the level of de-emphasis the link operates at. - 0: -6 dB - 1: -3.5 dB This field is reserved (fixed to '0') for M-PCIe. Note: The access attributes of this field are.." "0,1" newline bitfld.long 0x0 19. "CONFIG_TX_COMP_RX,Config Tx Compliance Receive Bit. When set to 1 signals LTSSM to transmit TS ordered sets with the compliance receive bit assert (equal to '1'). This field is reserved (fixed to '0') for M-PCIe. Note: The access attributes of this.." "0,1" newline bitfld.long 0x0 18. "CONFIG_PHY_TX_CHANGE,Config PHY Tx Swing. Controls the PHY transmitter voltage swing level. The controller drives the mac_phy_txswing output from this register bit field. - 0: Full Swing - 1: Low Swing This field is reserved (fixed to '0') for M-PCIe." "Full Swing,Low Swing" newline bitfld.long 0x0 17. "DIRECT_SPEED_CHANGE,Directed Speed Change. Writing '1' to this field instructs the LTSSM to initiate a speed change to Gen2 or Gen3 after the link is initialized at Gen1 speed. When the speed change occurs the controller will clear the contents of this.." "0,1" newline bitfld.long 0x0 16. "AUTO_LANE_FLIP_CTRL_EN,Enable Auto flipping of the lanes. You must set the CX_AUTO_LANE_FLIP_CTRL_EN configuration parameter to include the hardware for this feature in the controller. For more details see the 'Lane Reversal' appendix in the Databook." "0,1" newline bitfld.long 0x0 13.--15. "PRE_DET_LANE,Predetermined Lane for Auto Flip. This field defines which physical lane is connected to logical Lane0 by the flip operation performed in Detect. This field is used to restrict the receiver detect procedure to a particular lane when the.." "LANE0,LANE1,LANE3,LANE7,LANE15,?,?,?" newline hexmask.long.byte 0x0 8.--12. 1. "NUM_OF_LANES,Predetermined Number of Lanes. Defines the number of lanes which are connected and not bad. Used to limit the effective link width to ignore 'broken' or 'unused' lanes that detect a receiver. Indicates the number of lanes to check for exit.." newline hexmask.long.byte 0x0 0.--7. 1. "FAST_TRAINING_SEQ,Sets the Number of Fast Training Sequences (N_FTS) that the controller advertises as its N_FTS during Gen2 or Gen3 link training. This value is used to inform the link partner about the PHY's ability to recover synchronization after a.." rgroup.long (0x110+0x700)++0x3 line.long 0x0 "PHY_STATUS_OFF,PHY Status Register. Memory mapped register from phy_cfg_status GPIO input pins." hexmask.long 0x0 0.--31. 1. "PHY_STATUS,PHY Status. Data received directly from the phy_cfg_status bus. These is a GPIO register reflecting the values on the static phy_cfg_status input signals. The usage is left completely to the user and does not in any way influence controller.." group.long (0x114+0x700)++0x3 line.long 0x0 "PHY_CONTROL_OFF,PHY Control Register. Memory mapped register to cfg_phy_control GPIO output pins." hexmask.long 0x0 0.--31. 1. "PHY_CONTROL,PHY Control. Data sent directly to the cfg_phy_control bus. These is a GPIO register driving the values on the static cfg_phy_control output signals. The usage is left completely to the user and does not in any way influence controller.." group.long (0x11C+0x700)++0x77 line.long 0x0 "TRGT_MAP_CTRL_OFF,Programmable Target Map Control Register." hexmask.long.word 0x0 21.--31. 1. "TARGET_MAP_RESERVED_21_31,Reserved. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R (sticky)" newline hexmask.long.byte 0x0 16.--20. 1. "TARGET_MAP_INDEX,The number of the PF Function on which the Target Values are set. This register does not respect the Byte Enable setting. any write will affect all register bits." newline rbitfld.long 0x0 13.--15. "TARGET_MAP_RESERVED_13_15,Reserved. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R (sticky)" "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x0 7.--12. 1. "TARGET_MAP_VF,Target Values for each BAR on the VF Function selected by the index number. This register does not respect the Byte Enable setting. any write will affect all register bits." newline bitfld.long 0x0 6. "TARGET_MAP_ROM,Target Value for the ROM page of the PF Function selected by the index number. This register does not respect the Byte Enable setting. any write will affect all register bits." "0,1" newline hexmask.long.byte 0x0 0.--5. 1. "TARGET_MAP_PF,Target Values for each BAR on the PF Function selected by the index number. This register does not respect the Byte Enable setting. any write will affect all register bits." line.long 0x4 "MSI_CTRL_ADDR_OFF,Integrated MSI Reception Module (iMRM) Address Register." hexmask.long 0x4 0.--31. 1. "MSI_CTRL_ADDR,Integrated MSI Reception Module Address. System specified address for MSI memory write transaction termination. Within the AXI Bridge every received Memory Write request is examined to see if it targets the MSI Address that has been.." line.long 0x8 "MSI_CTRL_UPPER_ADDR_OFF,Integrated MSI Reception Module Upper Address Register." hexmask.long 0x8 0.--31. 1. "MSI_CTRL_UPPER_ADDR,Integrated MSI Reception Module Upper Address. System specified upper address for MSI memory write transaction termination. Allows functions to support a 64-bit MSI address. Note: This register field is sticky." line.long 0xC "MSI_CTRL_INT_0_EN_OFF,Integrated MSI Reception Module Interrupt#i Enable Register." hexmask.long 0xC 0.--31. 1. "MSI_CTRL_INT_0_EN,MSI Interrupt#i Enable. Specifies which interrupts are enabled. When an MSI is received from a disabled interrupt no status bit gets set in MSI controller interrupt status register. Each bit corresponds to a single MSI Interrupt.." line.long 0x10 "MSI_CTRL_INT_0_MASK_OFF,Integrated MSI Reception Module Interrupt#i Mask Register." hexmask.long 0x10 0.--31. 1. "MSI_CTRL_INT_0_MASK,MSI Interrupt#i Mask. Allows enabled interrupts to be masked. When an MSI is received for a masked interrupt the corresponding status bit gets set in the interrupt status register but the msi_ctrl_int output is not set HIGH. Each bit.." line.long 0x14 "MSI_CTRL_INT_0_STATUS_OFF,Integrated MSI Reception Module Interrupt#i Status Register." hexmask.long 0x14 0.--31. 1. "MSI_CTRL_INT_0_STATUS,MSI Interrupt#i Status. When an MSI is detected for EP#i one bit in this register is set. The decoding of the data payload of the MSI Memory Write request determines which bit gets set. A status is bit is cleared by writing a 1 to.." line.long 0x18 "MSI_CTRL_INT_1_EN_OFF,Integrated MSI Reception Module Interrupt#i Enable Register." hexmask.long 0x18 0.--31. 1. "MSI_CTRL_INT_1_EN,MSI Interrupt#i Enable. Specifies which interrupts are enabled. When an MSI is received from a disabled interrupt no status bit gets set in MSI controller interrupt status register. Each bit corresponds to a single MSI Interrupt.." line.long 0x1C "MSI_CTRL_INT_1_MASK_OFF,Integrated MSI Reception Module Interrupt#i Mask Register." hexmask.long 0x1C 0.--31. 1. "MSI_CTRL_INT_1_MASK,MSI Interrupt#i Mask. Allows enabled interrupts to be masked. When an MSI is received for a masked interrupt the corresponding status bit gets set in the interrupt status register but the msi_ctrl_int output is not set HIGH. Each bit.." line.long 0x20 "MSI_CTRL_INT_1_STATUS_OFF,Integrated MSI Reception Module Interrupt#i Status Register." hexmask.long 0x20 0.--31. 1. "MSI_CTRL_INT_1_STATUS,MSI Interrupt#i Status. When an MSI is detected for EP#i one bit in this register is set. The decoding of the data payload of the MSI Memory Write request determines which bit gets set. A status is bit is cleared by writing a 1 to.." line.long 0x24 "MSI_CTRL_INT_2_EN_OFF,Integrated MSI Reception Module Interrupt#i Enable Register." hexmask.long 0x24 0.--31. 1. "MSI_CTRL_INT_2_EN,MSI Interrupt#i Enable. Specifies which interrupts are enabled. When an MSI is received from a disabled interrupt no status bit gets set in MSI controller interrupt status register. Each bit corresponds to a single MSI Interrupt.." line.long 0x28 "MSI_CTRL_INT_2_MASK_OFF,Integrated MSI Reception Module Interrupt#i Mask Register." hexmask.long 0x28 0.--31. 1. "MSI_CTRL_INT_2_MASK,MSI Interrupt#i Mask. Allows enabled interrupts to be masked. When an MSI is received for a masked interrupt the corresponding status bit gets set in the interrupt status register but the msi_ctrl_int output is not set HIGH. Each bit.." line.long 0x2C "MSI_CTRL_INT_2_STATUS_OFF,Integrated MSI Reception Module Interrupt#i Status Register." hexmask.long 0x2C 0.--31. 1. "MSI_CTRL_INT_2_STATUS,MSI Interrupt#i Status. When an MSI is detected for EP#i one bit in this register is set. The decoding of the data payload of the MSI Memory Write request determines which bit gets set. A status is bit is cleared by writing a 1 to.." line.long 0x30 "MSI_CTRL_INT_3_EN_OFF,Integrated MSI Reception Module Interrupt#i Enable Register." hexmask.long 0x30 0.--31. 1. "MSI_CTRL_INT_3_EN,MSI Interrupt#i Enable. Specifies which interrupts are enabled. When an MSI is received from a disabled interrupt no status bit gets set in MSI controller interrupt status register. Each bit corresponds to a single MSI Interrupt.." line.long 0x34 "MSI_CTRL_INT_3_MASK_OFF,Integrated MSI Reception Module Interrupt#i Mask Register." hexmask.long 0x34 0.--31. 1. "MSI_CTRL_INT_3_MASK,MSI Interrupt#i Mask. Allows enabled interrupts to be masked. When an MSI is received for a masked interrupt the corresponding status bit gets set in the interrupt status register but the msi_ctrl_int output is not set HIGH. Each bit.." line.long 0x38 "MSI_CTRL_INT_3_STATUS_OFF,Integrated MSI Reception Module Interrupt#i Status Register." hexmask.long 0x38 0.--31. 1. "MSI_CTRL_INT_3_STATUS,MSI Interrupt#i Status. When an MSI is detected for EP#i one bit in this register is set. The decoding of the data payload of the MSI Memory Write request determines which bit gets set. A status is bit is cleared by writing a 1 to.." line.long 0x3C "MSI_CTRL_INT_4_EN_OFF,Integrated MSI Reception Module Interrupt#i Enable Register." hexmask.long 0x3C 0.--31. 1. "MSI_CTRL_INT_4_EN,MSI Interrupt#i Enable. Specifies which interrupts are enabled. When an MSI is received from a disabled interrupt no status bit gets set in MSI controller interrupt status register. Each bit corresponds to a single MSI Interrupt.." line.long 0x40 "MSI_CTRL_INT_4_MASK_OFF,Integrated MSI Reception Module Interrupt#i Mask Register." hexmask.long 0x40 0.--31. 1. "MSI_CTRL_INT_4_MASK,MSI Interrupt#i Mask. Allows enabled interrupts to be masked. When an MSI is received for a masked interrupt the corresponding status bit gets set in the interrupt status register but the msi_ctrl_int output is not set HIGH. Each bit.." line.long 0x44 "MSI_CTRL_INT_4_STATUS_OFF,Integrated MSI Reception Module Interrupt#i Status Register." hexmask.long 0x44 0.--31. 1. "MSI_CTRL_INT_4_STATUS,MSI Interrupt#i Status. When an MSI is detected for EP#i one bit in this register is set. The decoding of the data payload of the MSI Memory Write request determines which bit gets set. A status is bit is cleared by writing a 1 to.." line.long 0x48 "MSI_CTRL_INT_5_EN_OFF,Integrated MSI Reception Module Interrupt#i Enable Register." hexmask.long 0x48 0.--31. 1. "MSI_CTRL_INT_5_EN,MSI Interrupt#i Enable. Specifies which interrupts are enabled. When an MSI is received from a disabled interrupt no status bit gets set in MSI controller interrupt status register. Each bit corresponds to a single MSI Interrupt.." line.long 0x4C "MSI_CTRL_INT_5_MASK_OFF,Integrated MSI Reception Module Interrupt#i Mask Register." hexmask.long 0x4C 0.--31. 1. "MSI_CTRL_INT_5_MASK,MSI Interrupt#i Mask. Allows enabled interrupts to be masked. When an MSI is received for a masked interrupt the corresponding status bit gets set in the interrupt status register but the msi_ctrl_int output is not set HIGH. Each bit.." line.long 0x50 "MSI_CTRL_INT_5_STATUS_OFF,Integrated MSI Reception Module Interrupt#i Status Register." hexmask.long 0x50 0.--31. 1. "MSI_CTRL_INT_5_STATUS,MSI Interrupt#i Status. When an MSI is detected for EP#i one bit in this register is set. The decoding of the data payload of the MSI Memory Write request determines which bit gets set. A status is bit is cleared by writing a 1 to.." line.long 0x54 "MSI_CTRL_INT_6_EN_OFF,Integrated MSI Reception Module Interrupt#i Enable Register." hexmask.long 0x54 0.--31. 1. "MSI_CTRL_INT_6_EN,MSI Interrupt#i Enable. Specifies which interrupts are enabled. When an MSI is received from a disabled interrupt no status bit gets set in MSI controller interrupt status register. Each bit corresponds to a single MSI Interrupt.." line.long 0x58 "MSI_CTRL_INT_6_MASK_OFF,Integrated MSI Reception Module Interrupt#i Mask Register." hexmask.long 0x58 0.--31. 1. "MSI_CTRL_INT_6_MASK,MSI Interrupt#i Mask. Allows enabled interrupts to be masked. When an MSI is received for a masked interrupt the corresponding status bit gets set in the interrupt status register but the msi_ctrl_int output is not set HIGH. Each bit.." line.long 0x5C "MSI_CTRL_INT_6_STATUS_OFF,Integrated MSI Reception Module Interrupt#i Status Register." hexmask.long 0x5C 0.--31. 1. "MSI_CTRL_INT_6_STATUS,MSI Interrupt#i Status. When an MSI is detected for EP#i one bit in this register is set. The decoding of the data payload of the MSI Memory Write request determines which bit gets set. A status is bit is cleared by writing a 1 to.." line.long 0x60 "MSI_CTRL_INT_7_EN_OFF,Integrated MSI Reception Module Interrupt#i Enable Register." hexmask.long 0x60 0.--31. 1. "MSI_CTRL_INT_7_EN,MSI Interrupt#i Enable. Specifies which interrupts are enabled. When an MSI is received from a disabled interrupt no status bit gets set in MSI controller interrupt status register. Each bit corresponds to a single MSI Interrupt.." line.long 0x64 "MSI_CTRL_INT_7_MASK_OFF,Integrated MSI Reception Module Interrupt#i Mask Register." hexmask.long 0x64 0.--31. 1. "MSI_CTRL_INT_7_MASK,MSI Interrupt#i Mask. Allows enabled interrupts to be masked. When an MSI is received for a masked interrupt the corresponding status bit gets set in the interrupt status register but the msi_ctrl_int output is not set HIGH. Each bit.." line.long 0x68 "MSI_CTRL_INT_7_STATUS_OFF,Integrated MSI Reception Module Interrupt#i Status Register." hexmask.long 0x68 0.--31. 1. "MSI_CTRL_INT_7_STATUS,MSI Interrupt#i Status. When an MSI is detected for EP#i one bit in this register is set. The decoding of the data payload of the MSI Memory Write request determines which bit gets set. A status is bit is cleared by writing a 1 to.." line.long 0x6C "MSI_GPIO_IO_OFF,Integrated MSI Reception Module General Purpose IO Register." hexmask.long 0x6C 0.--31. 1. "MSI_GPIO_REG,MSI GPIO Register. The contents of this register drives the top-level GPIO msi_ctrl_io[31:0] Note: This register field is sticky." line.long 0x70 "CLOCK_GATING_CTRL_OFF,This register enables you to disable dynamic clock gating. By default dynamic clock gating is on. allowing the controller to autonomously enable and disable its clocks. The clock gating is performed in the clock and reset module." hexmask.long 0x70 2.--31. 1. "RSVDP_2,Reserved for future use." newline bitfld.long 0x70 1. "AXI_CLK_GATING_EN,AXI Clock Gating Enable. This register enables the AXI Bridge to autonomously enable and disable the AXI Master clock the AXI Slave clock and the AXI DBI slave clock. The DWC_pcie_clk_rst.v module provides the gated clock.." "Disable,Enable" newline bitfld.long 0x70 0. "RADM_CLK_GATING_EN,RADM Clock Gating Enable. This register if set enables the RADM to autonomously enable and disable its clock. The DWC_pcie_clk_rst.v module provides the gated clock radm_clk_g to the RADM and is enabled when the controllers clock.." "Disable,Enable" line.long 0x74 "GEN3_RELATED_OFF,Gen3 Control Register. There is no Gen3-specific N_FTS field. The N_FTS field in the 'Link Width and Speed Change Control Register' is used for both Gen2 and Gen3 speed modes. There is no Gen3-specific 'Directed Speed Change' field. The.." hexmask.long.byte 0x74 26.--31. 1. "RSVDP_26,Reserved for future use." newline bitfld.long 0x74 23. "GEN3_EQ_INVREQ_EVAL_DIFF_DISABLE,Eq InvalidRequest and RxEqEval Different Time Assertion Disable. Disable the assertion of Eq InvalidRequest and RxEqEval at different time. Note: When CX_GEN4_SPEED/CX_GEN5_SPEED this register is shared for Gen3 and.." "0,1" newline rbitfld.long 0x74 19.--20. "RSVDP_19,Reserved for future use." "0,1,2,3" newline bitfld.long 0x74 18. "GEN3_DC_BALANCE_DISABLE,DC Balance Disable. Disable DC Balance feature. Note: When CX_GEN4_SPEED/CX_GEN5_SPEED this register is shared for Gen3 and Gen4/Gen5 data rate. Note: This register field is sticky." "0,1" newline bitfld.long 0x74 17. "GEN3_DLLP_XMT_DELAY_DISABLE,DLLP Transmission Delay Disable. Disable delay transmission of DLLPs before equalization. Note: When CX_GEN4_SPEED/CX_GEN5_SPEED this register is shared for Gen3 and Gen4/Gen5 data rate. Note: This register field is sticky." "0,1" newline bitfld.long 0x74 16. "GEN3_EQUALIZATION_DISABLE,Equalization Disable. Disable equalization feature. This bit cannot be changed once the LTSSM starts link training. Note: When CX_GEN4_SPEED/CX_GEN5_SPEED this register is shared for Gen3 and Gen4/Gen5 data rate. Note: This.." "0,1" newline rbitfld.long 0x74 14.--15. "RSVDP_14,Reserved for future use." "0,1,2,3" newline bitfld.long 0x74 13. "RXEQ_RGRDLESS_RXTS,When set to '1' the controller as Gen3 EQ master asserts RxEqEval to instruct the PHY to do Rx adaptation and evaluation after a 500ns timeout from a new preset request. - 0: mac_phy_rxeqeval asserts after 1us and 2 TS1 received from.." "mac_phy_rxeqeval asserts after 1us and 2 TS1..,mac_phy_rxeqeval asserts after 500ns regardless.." newline bitfld.long 0x74 12. "RXEQ_PH01_EN,Rx Equalization Phase 0/Phase 1 Hold Enable. When this bit is set the upstream port holds phase 0 (the downstream port holds phase 1) for 10ms. Holding phase 0 or phase 1 can be used to allow sufficient time for Rx Equalization to be.." "Tx equalization only in phase 2/3,No Tx equalization" newline bitfld.long 0x74 11. "EQ_REDO,Equalization Redo Disable. Disable autonomous mechanism for requesting to redo the equalization process. The received presets or coefficients mismatch in Recovery.RcvrLock after Recovery EQ phases causes the EQ redo requests. If the EQ redo is.." "0,1" newline bitfld.long 0x74 10. "EQ_EIEOS_CNT,Equalization EIEOS Count Reset Disable. Disable requesting reset of EIEOS count during equalization. Note: When CX_GEN4_SPEED/CX_GEN5_SPEED this register is shared for Gen3 and Gen4/Gen5 data rate. Note: This register field is sticky." "0,1" newline bitfld.long 0x74 9. "EQ_PHASE_2_3,Equalization Phase 2 and Phase 3 Disable. This applies to downstream ports only. Note: When CX_GEN4_SPEED/CX_GEN5_SPEED this register is shadow register for Gen3 and Gen4/Gen5 data rate. If RATE_SHADOW_SEL==00b this register is for Gen3.." "0,1" newline bitfld.long 0x74 8. "DISABLE_SCRAMBLER_GEN_3,Disable Scrambler for Gen3 and Gen4 Data Rate. The Gen3 and Gen4 scrambler/descrambler within the controller needs to be disabled when the scrambling function is implemented outside of the controller (for example within the PHY)." "0,1" newline hexmask.long.byte 0x74 1.--7. 1. "RSVDP_1,Reserved for future use." newline bitfld.long 0x74 0. "GEN3_ZRXDC_NONCOMPL,Gen3 Receiver Impedance ZRX-DC Not Compliant. Receivers that operate at 8.0 GT/s with an impedance other than the range defined by the ZRX-DC parameter for 2.5 GT/s (40-60 Ohms) must meet additional behavior requirements in the.." "The receiver complies with the ZRX-DC parameter..,The receiver does not comply with the ZRX-DC.." group.long (0x1A8+0x700)++0x7 line.long 0x0 "GEN3_EQ_CONTROL_OFF,Gen3 EQ Control Register. This register controls equalization for Phase2 in an upstream port (USP). or Phase3 in a downstream port (DSP). M-PCIe doesn't have Conventional PCIe Gen3 feature. The registers of this section do not exist." hexmask.long.byte 0x0 27.--31. 1. "RSVDP_27,Reserved for future use." newline bitfld.long 0x0 26. "GEN3_REQ_SEND_CONSEC_EIEOS_FOR_PSET_MAP,Request controller to send back-to-back EIEOS in Recovery.RcvrLock state until presets to coefficients mapping is complete. - 0: Do not request - 1: request Note: Gen3 and Gen4 share the same register bit and have.." "Do not request,request" newline bitfld.long 0x0 25. "GEN3_EQ_PSET_REQ_AS_COEF,GEN3_EQ_PSET_REQ_AS_COEF is an internally reserved field. Do not use. Note: This register field is sticky." "0,1" newline bitfld.long 0x0 24. "GEN3_EQ_FOM_INC_INITIAL_EVAL,Include Initial FOM. Include or not the FOM feedback from the initial preset evaluation performed in the EQ Master when finding the highest FOM among all preset evaluations. - 0: Do not include - 1: Include Note: When.." "Do not include,Include" newline hexmask.long.word 0x0 8.--23. 1. "GEN3_EQ_PSET_REQ_VEC,Preset Request Vector. Requesting of Presets during the initial part of the EQ Master Phase. Encoding scheme is as follows: Bit [15:0] =0x0: No preset is requested and evaluated in EQ Master Phase. Bit [i] =1: 'Preset=i' is requested.." newline rbitfld.long 0x0 7. "RSVDP_7,Reserved for future use." "0,1" newline bitfld.long 0x0 6. "GEN3_LOWER_RATE_EQ_REDO_ENABLE,Support EQ redo and lower rate change: - 0: not support - 1: support Note: Gen3 and Gen4 share the same register bit and have the same feature. Note: This register field is sticky." "not support,support" newline bitfld.long 0x0 5. "GEN3_EQ_EVAL_2MS_DISABLE,Phase2_3 2 ms Timeout Disable. Determine behavior in Phase2 for USP (Phase3 if DSP) when the PHY does not respond within 2ms to the assertion of RxEqEval: - 0: abort the current evaluation stop any attempt to modify the remote.." "abort the current evaluation,ignore the 2ms timeout and continue as normal" newline bitfld.long 0x0 4. "GEN3_EQ_PHASE23_EXIT_MODE,Behavior After 24 ms Timeout (when optimal settings are not found). For a USP: Determine next LTSSM state from Phase2 after 24ms Timeout - 0: Recovery.Speed - 1: Recovery.Equalization.Phase3 When optimal settings are not found.." "Equalization Phase 3 Successful status bit is..,Recovery" newline hexmask.long.byte 0x0 0.--3. 1. "GEN3_EQ_FB_MODE,Feedback Mode. - 0000b: Direction Change - 0001b: Figure Of Merit - 0010b: Reserved - .....: Reserved - 1111b: Reserved Note: When CX_GEN4_SPEED/CX_GEN5_SPEED this register is a shadow register for Gen3 and Gen4/Gen5 data rate. If.." line.long 0x4 "GEN3_EQ_FB_MODE_DIR_CHANGE_OFF,Gen3 EQ Direction Change Feedback Mode Control Register. Equalization controls to be used in Phase2 (USP) or Phase 3 (DSP). when you set the Feedback Mode in 'Gen3 EQ Control Register' to 'Direction Change.' These fields.." hexmask.long.word 0x4 18.--31. 1. "RSVDP_18,Reserved for future use." newline hexmask.long.byte 0x4 14.--17. 1. "GEN3_EQ_FMDC_MAX_POST_CUSROR_DELTA,Convergence Window Aperture for C+1. Post-cursor coefficients maximum delta within the convergence window depth. Allowed range: 0 1 2 ..15. Note: When CX_GEN4_SPEED/CX_GEN5_SPEED this register is shadow register for.." newline hexmask.long.byte 0x4 10.--13. 1. "GEN3_EQ_FMDC_MAX_PRE_CUSROR_DELTA,Convergence Window Aperture for C-1. Pre-cursor coefficients maximum delta within the convergence window depth. Allowed range: 0 1 2 ..15. Note: When CX_GEN4_SPEED/CX_GEN5_SPEED this register is shadow register for Gen3.." newline hexmask.long.byte 0x4 5.--9. 1. "GEN3_EQ_FMDC_N_EVALS,Convergence Window Depth. Number of consecutive evaluations considered in Phase 2/3 when determining if optimal coefficients have been found. Allowed range: 0 1 2 ..16 up to a maximum of CX_GEN3_EQ_COEFQ_DEPTH. When set to 0 EQ.." newline hexmask.long.byte 0x4 0.--4. 1. "GEN3_EQ_FMDC_T_MIN_PHASE23,Minimum Time (in ms) To Remain in EQ Master Phase. The LTSSM stays in EQ Master phase for at least this amount of time before starting to check for convergence of the coefficients. Allowed values 0 1 ... 24. Note: When.." group.long (0x1B4+0x700)++0x27 line.long 0x0 "ORDER_RULE_CTRL_OFF,Order Rule Control Register." hexmask.long.word 0x0 16.--31. 1. "RSVDP_16,Reserved for future use." newline hexmask.long.byte 0x0 8.--15. 1. "CPL_PASS_P,Completion Passing Posted Ordering Rule Control. Determines if CPL can pass halted P queue. - 0: CPL can not pass P (recommended) - 1: CPL can pass P" newline hexmask.long.byte 0x0 0.--7. 1. "NP_PASS_P,Non-Posted Passing Posted Ordering Rule Control. Determines if NP can pass halted P queue. - 0 : NP can not pass P (recommended). - 1 : NP can pass P" line.long 0x4 "PIPE_LOOPBACK_CONTROL_OFF,PIPE Loopback Control Register." bitfld.long 0x4 31. "PIPE_LOOPBACK,PIPE Loopback Enable. Indicates RMMI Loopback if M-PCIe. Note: This register field is sticky." "0,1" newline hexmask.long.byte 0x4 27.--30. 1. "RSVDP_27,Reserved for future use." newline bitfld.long 0x4 24.--26. "RXSTATUS_VALUE,RXSTATUS_VALUE is an internally reserved field. Do not use." "0,1,2,3,4,5,6,7" newline rbitfld.long 0x4 22.--23. "RSVDP_22,Reserved for future use." "0,1,2,3" newline hexmask.long.byte 0x4 16.--21. 1. "RXSTATUS_LANE,RXSTATUS_LANE is an internally reserved field. Do not use. Note: This register field is sticky." newline hexmask.long.word 0x4 0.--15. 1. "LPBK_RXVALID,LPBK_RXVALID is an internally reserved field. Do not use. Note: This register field is sticky." line.long 0x8 "MISC_CONTROL_1_OFF,DBI Read-Only Write Enable Register." hexmask.long.word 0x8 22.--31. 1. "RSVDP_22,Reserved for future use." newline bitfld.long 0x8 21. "P2P_ERR_RPT_CTRL,Determines whether to track completion of transmitted Non-Posted TLPs in P2P mode. - 0: Do not track completion - 1: Track completion Note: This register field is sticky." "Do not track completion,Track completion" newline bitfld.long 0x8 20. "P2P_TRACK_CPL_TO_REG,Determines whether to enable Peer to Peer (P2P) error reporting. - 0: Disable P2P error reporting - 1: Enable P2P error reporting Note: This register field is sticky." "Disable P2P error reporting,Enable P2P error reporting" newline bitfld.long 0x8 18.--19. "TARGET_ABOVE_CONFIG_LIMIT_REG,Configuration requests with an address greater than CONFIG_LIMIT_REG are directed to either ELBI or TRGT1 interface based on the setting of this field. This field can have the following values: - 1: ELBI - 2: TRGT1 Note:.." "?,ELBI,TRGT1,?" newline hexmask.long.word 0x8 8.--17. 1. "CONFIG_LIMIT_REG,Configuration requests are directed either to CDM or ELBI/RTRGT1 based on the value of this field. - Configuration requests with an address less CONFIG_LIMIT_REG are directed to the CDM - Configuration requests with an address greater.." newline bitfld.long 0x8 7. "CFG_TLP_BYPASS_EN_REG,Setting of this field defines which field TARGET_ABOVE_CONFIG_LIMIT_REG or CONFIG_LIMIT_REG decides the destination of Configuration requests. This field can have the following values: - 0: Configuration TLPs are routed according to.." "Configuration TLPs are routed according to the..,Configuration TLPs are routed according to the.." newline bitfld.long 0x8 6. "CPLQ_MNG_EN,This field enables the Completion Queue Management feature. Note: This register field is sticky." "0,1" newline bitfld.long 0x8 5. "ARI_DEVICE_NUMBER,When ARI is enabled this field enables use of the device ID. Note: This register field is sticky." "0,1" newline bitfld.long 0x8 4. "DISABLE_AUTO_LTR_CLR_MSG,Disable the autonomous generation of LTR clear message in upstream port. This field can have the following values: - 0: Allow the autonomous generation of LTR clear message. - 1: Disable the autonomous generation of LTR clear.." "Allow the autonomous generation of LTR clear..,Disable the autonomous generation of LTR clear.." newline bitfld.long 0x8 3. "SIMPLIFIED_REPLAY_TIMER,Enables Simplified Replay Timer (Gen4). For more details see 'Transmit Replay' in 'Transmit TLP Processing' section in the 'Controller Operations' chapter of the Databook. Simplified Replay Timer can have the following Values: -.." "0,1" newline bitfld.long 0x8 2. "UR_CA_MASK_4_TRGT1,When this field is set to '1' the controller suppresses error logging error message generation and CPL generation for non-posted requests TLPs (with UR filtering status) forwarded to your application (that is when DEFAULT_TARGET.." "0,1" newline bitfld.long 0x8 1. "DEFAULT_TARGET,Default target for an IO or MEM request with UR/CA/CRS received. Based on the value of this field the controller either drops or forwards these requests to your application. - 0: The controller drops all incoming I/O or MEM requests (after.." "The controller drops all incoming I/O or MEM..,The controller forwards all incoming I/O or MEM.." newline bitfld.long 0x8 0. "DBI_RO_WR_EN,Write to RO Registers Using DBI. Your application can write to some RO and HwInit register fields through the DBI when you set this field to '1'. For more details see 'Writing to Read-Only Registers' in 'Register Module LBC and DBI'.." "0,1" line.long 0xC "MULTI_LANE_CONTROL_OFF,UpConfigure Multi-lane Control Register. Used when upsizing or downsizing the link width through Configuration state without bringing the link down. For more details. see the 'Link Establishment' section in the 'Controller.." hexmask.long.tbyte 0xC 8.--31. 1. "RSVDP_8,Reserved for future use." newline bitfld.long 0xC 7. "UPCONFIGURE_SUPPORT,Upconfigure Support. The controller sends this value as the Link Upconfigure Capability in TS2 Ordered Sets in Configuration.Complete state. This field is reserved (fixed to '0') for M-PCIe. Note: This register field is sticky." "0,1" newline bitfld.long 0xC 6. "DIRECT_LINK_WIDTH_CHANGE,Directed Link Width Change. The controller always moves to Configuration state through Recovery state when this bit is set to '1'. - If the upconfigure_capable variable is '1' and the PCIE_CAP_HW_AUTO_WIDTH_DISABLE bit in.." "0,1" newline hexmask.long.byte 0xC 0.--5. 1. "TARGET_LINK_WIDTH,Target Link Width. Values correspond to: - 6'b000000: Controller does not start upconfigure or autonomous width downsizing in the Configuration state. - 6'b000001: x1 - 6'b000010: x2 - 6'b000100: x4 - 6'b001000: x8 - 6'b010000: x16 -.." line.long 0x10 "PHY_INTEROP_CTRL_OFF,PHY Interoperability Control Register." hexmask.long.tbyte 0x10 12.--31. 1. "RSVDP_12,Reserved for future use." newline bitfld.long 0x10 10. "L1_CLK_SEL,L1 Clock control bit. This field is reserved for internal use. You should not write to this field and change the default unless specifically instructed by Synopsys support. - 1: Controller does not request aux_clk switch and core_clk gating in.." "Controller requests aux_clk switch and core_clk..,Controller does not request aux_clk switch and.." newline rbitfld.long 0x10 9. "L1_NOWAIT_P1,L1 entry control bit. This field is reserved for internal use. You should not write to this field and change the default unless specifically instructed by Synopsys support. - 1: Controller does not wait for PHY to acknowledge transition to.." "Controller waits for the PHY to acknowledge..,Controller does not wait for PHY to acknowledge.." newline bitfld.long 0x10 8. "L1SUB_EXIT_MODE,L1 Exit Control Using phy_mac_pclkack_n. This field is reserved for internal use. You should not write to this field and change the default unless specifically instructed by Synopsys support. - 1: Controller exits L1 without waiting for.." "Controller waits for the PHY to assert..,Controller exits L1 without waiting for the PHY.." newline rbitfld.long 0x10 7. "RSVDP_7,Reserved for future use." "0,1" newline hexmask.long.byte 0x10 0.--6. 1. "RXSTANDBY_CONTROL,Rxstandby Control. Bits 0..5 determine if the controller asserts the RxStandby signal (mac_phy_rxstandby) in the indicated condition. Bit 6 enables the controller to perform the RxStandby/RxStandbyStatus handshake. This field is.." line.long 0x14 "TRGT_CPL_LUT_DELETE_ENTRY_OFF,TRGT_CPL_LUT Delete Entry Control register. Using this register you can delete one entry in the target completion LUT. You should only use this register when you know that your application will never send the completion.." bitfld.long 0x14 31. "DELETE_EN,This is a one-shot bit. A '1' write to this bit triggers the deletion of the target completion LUT entry that is specified in the LOOK_UP_ID field. This is a self-clearing register field. Reading from this register field always returns a '0'." "0,1" newline hexmask.long 0x14 0.--30. 1. "LOOK_UP_ID,This number selects one entry to delete of the TRGT_CPL_LUT." line.long 0x18 "LINK_FLUSH_CONTROL_OFF,Link Reset Request Flush Control Register." hexmask.long.byte 0x18 24.--31. 1. "RSVD_I_8,This is an internally reserved field. Do not use. Note: This register field is sticky." newline hexmask.long.tbyte 0x18 1.--23. 1. "RSVDP_1,Reserved for future use." newline bitfld.long 0x18 0. "AUTO_FLUSH_EN,Enables automatic flushing of pending requests before sending the reset request to the application logic to reset the PCIe controller and the AXI Bridge. The flushing process is initiated if any of the following events occur: - Hot reset.." "0,1" line.long 0x1C "AMBA_ERROR_RESPONSE_DEFAULT_OFF,AXI Bridge Slave Error Response Register." hexmask.long.word 0x1C 16.--31. 1. "RSVDP_16,Reserved for future use." newline hexmask.long.byte 0x1C 10.--15. 1. "AMBA_ERROR_RESPONSE_MAP,AXI Slave Response Error Map. Allows you to selectively map the errors received from the PCIe completion (for non-posted requests) to the AXI slave responses slv_rresp or slv_bresp. The recommended setting is SLVERR. CRS is.." newline hexmask.long.byte 0x1C 5.--9. 1. "RSVDP_5,Reserved for future use." newline bitfld.long 0x1C 3.--4. "AMBA_ERROR_RESPONSE_CRS,CRS Slave Error Response Mapping. Determines the AXI slave response for CRS completions. For more details see 'Error Handling' in the AXI chapter of the Databook. AHB: - always returns OKAY AXI: - 00: OKAY - 01: OKAY with all.." "OKAY,OKAY with all FFFF_FFFF data for all CRS..,?,?" newline bitfld.long 0x1C 2. "AMBA_ERROR_RESPONSE_VENDORID,Vendor ID Non-existent Slave Error Response Mapping. Determines the AXI slave response for errors on reads to non-existent Vendor ID register. For more details see 'Error Handling' in the AXI chapter of the Databook. AHB: -.." "OKAY,SLVERR/DECERR" newline rbitfld.long 0x1C 1. "RSVDP_1,Reserved for future use." "0,1" newline bitfld.long 0x1C 0. "AMBA_ERROR_RESPONSE_GLOBAL,Global Slave Error Response Mapping. Determines the AXI slave response for all error scenarios on non-posted requests. For more details see 'Error Handling' in the AXI chapter of the Databook. AHB: - 0: OKAY (with FFFF data for.." "OKAY,SLVERR/DECERR" line.long 0x20 "AMBA_LINK_TIMEOUT_OFF,Link Down AXI Bridge Slave Timeout Register. If your application AXI master issues outbound requests to the AXI bridge slave interface before the PCIe link is operational. the controller starts a 'flush' timer. The timeout value of.." hexmask.long.tbyte 0x20 9.--31. 1. "RSVDP_9,Reserved for future use." newline bitfld.long 0x20 8. "LINK_TIMEOUT_ENABLE_DEFAULT,Disable Flush. You can disable the flush feature by setting this field to '1'. Note: This register field is sticky." "0,1" newline hexmask.long.byte 0x20 0.--7. 1. "LINK_TIMEOUT_PERIOD_DEFAULT,Timeout Value (ms). The timer will timeout and then flush the bridge TX request queues after this amount of time. The timer counts when there are pending outbound AXI slave interface requests and the PCIe TX link is not.." line.long 0x24 "AMBA_ORDERING_CTRL_OFF,AMBA Ordering Control." hexmask.long.tbyte 0x24 8.--31. 1. "RSVDP_8,Reserved for future use." newline bitfld.long 0x24 7. "AX_MSTR_ZEROLREAD_FW,AXI Master Zero Length Read Forward to the application. The DW PCIe controller AXI bridge is able to terminate in order with the Posted transactions the zero length read implementing the PCIe express flush semantics of the Posted.." "The zero length Read is terminated at the DW..,The zero length Read is forward to the application" newline rbitfld.long 0x24 5.--6. "RSVDP_5,Reserved for future use." "0,1,2,3" newline bitfld.long 0x24 3.--4. "AX_MSTR_ORDR_P_EVENT_SEL,AXI Master Posted Ordering Event Selector. This field selects how the master interface determines when a P write is completed when enforcing the PCIe ordering rule 'NP must not pass P' at the AXI Master Interface. The AXI.." "B'last event: wait for the all of the write..,AW'last event: wait until the complete Posted..,This setting will not affect:,?" newline rbitfld.long 0x24 2. "RSVDP_2,Reserved for future use." "0,1" newline bitfld.long 0x24 1. "AX_SNP_EN,AXI Serialize Non-Posted Requests Enable. This field enables the AXI Bridge to serialize same ID Non-Posted Read/Write Requests on the wire. Serialization implies one outstanding same ID NP Read or Write on the wire and used to avoid AXI RAR.." "0,1" newline rbitfld.long 0x24 0. "RSVDP_0,Reserved for future use." "0,1" group.long (0x1E0+0x700)++0xB line.long 0x0 "COHERENCY_CONTROL_1_OFF,ACE Cache Coherency Control Register 1" hexmask.long 0x0 2.--31. 1. "CFG_MEMTYPE_BOUNDARY_LOW_ADDR,Boundary Lower Address For Memory Type. Bits [31:0] of dword-aligned address of the boundary for Memory type. The two lower address LSBs are '00'. Addresses up to but not including this value are in the lower address space.." newline rbitfld.long 0x0 1. "RSVDP_1,Reserved for future use." "0,1" newline bitfld.long 0x0 0. "CFG_MEMTYPE_VALUE,Sets the memory type for the lower and upper parts of the address space: - 0: lower = Peripheral; upper = Memory - 1: lower = Memory type; upper = Peripheral Note: This register field is sticky." "lower = Peripheral; upper = Memory,lower = Memory type; upper = Peripheral" line.long 0x4 "COHERENCY_CONTROL_2_OFF,ACE Cache Coherency Control Register 2" hexmask.long 0x4 0.--31. 1. "CFG_MEMTYPE_BOUNDARY_HIGH_ADDR,Boundary Upper Address For Memory Type. Bits [63:32] of the 64-bit dword-aligned address of the boundary for Memory type. Note: This register field is sticky." line.long 0x8 "COHERENCY_CONTROL_3_OFF,ACE Cache Coherency Control Register 3" hexmask.long.byte 0x8 27.--30. 1. "CFG_MSTR_AWCACHE_VALUE,Master Write CACHE Signal Value. Value of the individual bits in mstr_awcache when CFG_MSTR_AWCACHE_MODE is '1'. Note: not applicable to message requests; for message requests the value of mstr_awcache is always '0000' Note: This.." newline hexmask.long.byte 0x8 19.--22. 1. "CFG_MSTR_ARCACHE_VALUE,Master Read CACHE Signal Value. Value of the individual bits in mstr_arcache when CFG_MSTR_ARCACHE_MODE is '1'. Note: This register field is sticky." newline hexmask.long.byte 0x8 11.--14. 1. "CFG_MSTR_AWCACHE_MODE,Master Write CACHE Signal Behavior. Defines how the individual bits in mstr_awcache are controlled: - 0: set automatically by the AXI master - 1: set by the value of the corresponding bit of the CFG_MSTR_AWCACHE_VALUE field Note:.." newline hexmask.long.byte 0x8 3.--6. 1. "CFG_MSTR_ARCACHE_MODE,Master Read CACHE Signal Behavior. Defines how the individual bits in mstr_arcache are controlled: - 0: set automatically by the AXI master - 1: set by the value of the corresponding bit of the CFG_MSTR_ARCACHE_VALUE field Note:.." group.long (0x1F0+0x700)++0x7 line.long 0x0 "AXI_MSTR_MSG_ADDR_LOW_OFF,Lower 20 bits of the programmable AXI address where Messages coming from wire are mapped to. Bits [11:0] of the register are tied to zero for the address to be 4k-aligned. In previous releases. the third and fourth DWORDs of a.." hexmask.long.tbyte 0x0 12.--31. 1. "CFG_AXIMSTR_MSG_ADDR_LOW,Lower 20 bits of the programmable AXI address for Messages. Note: This register field is sticky." newline hexmask.long.word 0x0 0.--11. 1. "CFG_AXIMSTR_MSG_ADDR_LOW_RESERVED,Reserved for future use. Note: This register field is sticky." line.long 0x4 "AXI_MSTR_MSG_ADDR_HIGH_OFF,Upper 32 bits of the programmable AXI address where Messages coming from wire are mapped to." hexmask.long 0x4 0.--31. 1. "CFG_AXIMSTR_MSG_ADDR_HIGH,Upper 32 bits of the programmable AXI address for Messages. Note: This register field is sticky." rgroup.long (0x1F8+0x700)++0x7 line.long 0x0 "PCIE_VERSION_NUMBER_OFF,PCIe Controller IIP Release Version Number. The version number is given in hex format. You should convert each pair of hex characters to ASCII to interpret. Using 4.70a (GA) as an example: - VERSION_NUMBER = 0x3437302a which.." hexmask.long 0x0 0.--31. 1. "VERSION_NUMBER,Version Number." line.long 0x4 "PCIE_VERSION_TYPE_OFF,PCIe Controller IIP Release Version Type. The type is given in hex format. You should convert each pair of hex characters to ASCII to interpret. Using 4.70a (GA) as an example: - VERSION_NUMBER = 0x3437302a which translates to 470*.." hexmask.long 0x4 0.--31. 1. "VERSION_TYPE,Version Type." group.long (0x240+0x700)++0x7 line.long 0x0 "MSIX_ADDRESS_MATCH_LOW_OFF,MSI-X Address Match Low Register. When you enable the MSI-X Table RAM feature (MSIX_TABLE_EN=1). the controller implements the logic and RAM required to generate MSI-X requests. For more details. see the Interrupts section in.." hexmask.long 0x0 2.--31. 1. "MSIX_ADDRESS_MATCH_LOW,MSI-X Address Match Low Address. Note: This register field is sticky." newline rbitfld.long 0x0 1. "MSIX_ADDRESS_MATCH_RESERVED_1,Reserved. Note: This register field is sticky." "0,1" newline bitfld.long 0x0 0. "MSIX_ADDRESS_MATCH_EN,MSI-X Match Enable. Enable the MSI-X Address Match feature when the AXI bridge is present. Note: This register field is sticky." "0,1" line.long 0x4 "MSIX_ADDRESS_MATCH_HIGH_OFF,MSI-X Address Match High Register. When you enable the MSI-X Table RAM feature (MSIX_TABLE_EN=1). the controller implements the logic and RAM required to generate MSI-X requests. For more details. see the Interrupts section in.." hexmask.long 0x4 0.--31. 1. "MSIX_ADDRESS_MATCH_HIGH,MSI-X Address Match High Address. Note: This register field is sticky." wgroup.long (0x248+0x700)++0x3 line.long 0x0 "MSIX_DOORBELL_OFF,MSI-X Doorbell Register. When you enable the MSI-X Table RAM feature (MSIX_TABLE_EN=1). the controller implements the logic and RAM required to generate MSI-X requests. For more details. see the Interrupts section in the 'Controller.." bitfld.long 0x0 29.--31. "MSIX_DOORBELL_RESERVED_29_31,Reserved." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x0 24.--28. 1. "MSIX_DOORBELL_PF,MSIX Doorbell Physical Function. This register determines the Physical Function for the MSI-X transaction." newline hexmask.long.byte 0x0 16.--23. 1. "MSIX_DOORBELL_VF,MSIX Doorbell Virtual Function. This register determines the Virtual Function for the MSI-X transaction." newline bitfld.long 0x0 15. "MSIX_DOORBELL_VF_ACTIVE,MSIX Doorbell Virtual Function Active. This register determines whether a Virtual Function is used to generate the MSI-X transaction." "0,1" newline bitfld.long 0x0 12.--14. "MSIX_DOORBELL_TC,MSIX Doorbell Traffic Class. This register determines which traffic class to generate the MSI-X transaction with." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 11. "MSIX_DOORBELL_RESERVED_11,Reserved." "0,1" newline hexmask.long.word 0x0 0.--10. 1. "MSIX_DOORBELL_VECTOR,MSI-X Doorbell Vector. This register determines which vector to generate the MSI-X transaction for." group.long (0x24C+0x700)++0x3 line.long 0x0 "MSIX_RAM_CTRL_OFF,MSI-X RAM power mode and debug control register. When you enable the MSI-X Table RAM feature (MSIX_TABLE_EN=1). the controller implements the logic and RAM required to generate MSI-X requests. For more details. see the Interrupts.." hexmask.long.byte 0x0 26.--31. 1. "MSIX_RAM_CTRL_RESERVED_26_31,Reserved. Note: This register field is sticky." newline bitfld.long 0x0 25. "MSIX_RAM_CTRL_DBG_PBA,MSIX PBA RAM Debug Mode. Use this bit to activate the debug mode and allow direct read/write access to the PBA. Use can also use the dbg_pba input to activate debug mode. Debug mode turns off the PF/VF/Offset-based addressing into.." "0,1" newline bitfld.long 0x0 24. "MSIX_RAM_CTRL_DBG_TABLE,MSIX Table RAM Debug Mode. Use this bit to activate the debug mode and allow direct read/write access to the Table. Use can also use the dbg_table input to activate debug mode. Debug mode turns off the PF/VF/Offset-based.." "0,1" newline hexmask.long.byte 0x0 17.--23. 1. "MSIX_RAM_CTRL_RESERVED_17_23,Reserved. Note: This register field is sticky." newline bitfld.long 0x0 16. "MSIX_RAM_CTRL_BYPASS,MSIX RAM Control Bypass. The bypass field when set disables the internal generation of low power signals for both RAMs. It is up to the application to ensure the RAMs are in the proper power state before trying to access them." "0,1" newline hexmask.long.byte 0x0 10.--15. 1. "MSIX_RAM_CTRL_RESERVED_10_15,Reserved. Note: This register field is sticky." newline bitfld.long 0x0 9. "MSIX_RAM_CTRL_PBA_SD,MSIX PBA RAM Shut Down. Set this bit to drive the cfg_msix_pba_sd output to signal your external logic to place the MSIX PBA RAM in Shut Down low-power mode. Note: This register field is sticky." "0,1" newline bitfld.long 0x0 8. "MSIX_RAM_CTRL_PBA_DS,MSIX PBA RAM Deep Sleep. Set this bit to drive the cfg_msix_pba_ds output to signal your external logic to place the MSIX PBA RAM in Deep Sleep low-power mode. Note: This register field is sticky." "0,1" newline hexmask.long.byte 0x0 2.--7. 1. "MSIX_RAM_CTRL_RESERVED_2_7,Reserved. Note: This register field is sticky." newline bitfld.long 0x0 1. "MSIX_RAM_CTRL_TABLE_SD,MSIX Table RAM Shut Down. Set this bit to drive the cfg_msix_table_sd output to signal your external logic to place the MSIX Table RAM in Shut Down low-power mode. Note: This register field is sticky." "0,1" newline bitfld.long 0x0 0. "MSIX_RAM_CTRL_TABLE_DS,MSIX Table RAM Deep Sleep. Set this bit to drive the cfg_msix_table_ds output to signal your external logic to place the MSIX Table RAM in Deep Sleep low-power mode. Note: This register field is sticky." "0,1" group.long (0x430+0x700)++0x3 line.long 0x0 "PL_LTR_LATENCY_OFF,LTR Latency Register. The function of this register field (and all other fields in this register) differs between an upstream port and a downstream port. For an upstream port. the register fields capture the corresponding fields in the.." bitfld.long 0x0 31. "NO_SNOOP_LATENCY_REQUIRE,No Snoop Latency Requirement. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" "0,1" newline rbitfld.long 0x0 29.--30. "RSVDP_29,Reserved for future use." "0,1,2,3" newline bitfld.long 0x0 26.--28. "NO_SNOOP_LATENCY_SCALE,No Snoop Latency Scale. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" "0,1,2,3,4,5,6,7" newline hexmask.long.word 0x0 16.--25. 1. "NO_SNOOP_LATENCY_VALUE,No Snoop Latency Value. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" newline bitfld.long 0x0 15. "SNOOP_LATENCY_REQUIRE,Snoop Latency Requirement. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" "0,1" newline rbitfld.long 0x0 13.--14. "RSVDP_13,Reserved for future use." "0,1,2,3" newline bitfld.long 0x0 10.--12. "SNOOP_LATENCY_SCALE,Snoop Latency Scale. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" "0,1,2,3,4,5,6,7" newline hexmask.long.word 0x0 0.--9. 1. "SNOOP_LATENCY_VALUE,Snoop Latency Value. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" group.long (0x440+0x700)++0xB line.long 0x0 "AUX_CLK_FREQ_OFF,Auxiliary Clock Frequency Control Register." hexmask.long.tbyte 0x0 10.--31. 1. "RSVDP_10,Reserved for future use." newline hexmask.long.word 0x0 0.--9. 1. "AUX_CLK_FREQ,The aux_clk frequency in MHz. This value is used to provide a 1 us reference for counting time during low-power states with aux_clk when the PHY has removed the pipe_clk. Frequencies lower than 1 MHz are possible but with a loss of accuracy.." line.long 0x4 "L1_SUBSTATES_OFF,L1 Substates Timing Register." hexmask.long.tbyte 0x4 9.--31. 1. "RSVDP_9,Reserved for future use." newline bitfld.long 0x4 8. "L1SUB_LOW_POWER_CLOCK_SWITCH_MODE,If this bit is set to 1'b1 the reference clock will be running regardless of the CLKREQ# setting. If this bit is set to 1'b0 the reference clock may be gated off when CLKREQ# is de-asserted. If the bit is set to 1'b1 the.." "0,1" newline bitfld.long 0x4 6.--7. "L1SUB_T_PCLKACK,Max delay (in 1us units) between a MAC request to remove the clock on mac_phy_pclkreq_n and a PHY response on phy_mac_pclkack_n. If the PHY does not respond within this time the request is aborted.The actual timeout value will be.." "0,1,2,3" newline hexmask.long.byte 0x4 2.--5. 1. "L1SUB_T_L1_2,Duration (in 1us units) of L1.2. The actual timeout value will be L1SUB_T_L1_2 + 1. Range is 0.15. Note: This register field is sticky." newline bitfld.long 0x4 0.--1. "L1SUB_T_POWER_OFF,Duration (in 1us units) of L1.2.Entry. The actual timeout value will be L1SUB_T_POWER_OFF + 1. Range is 0.3. Note: This register field is sticky." "0,1,2,3" line.long 0x8 "POWERDOWN_CTRL_STATUS_OFF,Powerdown Control and Status Register." hexmask.long.tbyte 0x8 12.--31. 1. "RSVDP_12,Reserved for future use." newline hexmask.long.byte 0x8 8.--11. 1. "POWERDOWN_PHY_POWERDOWN,This field represents the Powerdown value that has been acknowledged by the PHY. It is updated with the value of Powerdown driven by the controller when the PHY has returned the Phystatus acknowledgment for the Powerdown.." newline hexmask.long.byte 0x8 4.--7. 1. "POWERDOWN_MAC_POWERDOWN,This field represents the Powerdown value driven by the controller to the PHY." newline rbitfld.long 0x8 1.--3. "RSVDP_1,Reserved for future use." "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 0. "POWERDOWN_FORCE,This field is a one shot field. Writing a value of 1 to this field causes the controller to complete the P2 Powerdown handshake regardless of whether the PHY has returned Phystatus. This field could be used for debug purposes in event.." "0,1" group.long (0x470+0x700)++0x7 line.long 0x0 "PHY_VIEWPORT_CTLSTS_OFF,PHY Register Viewport Control and Status Register." rbitfld.long 0x0 31. "PHY_VIEWPORT_PENDING,PHY viewport pending. Indicates the access is pending. - 1 : Pending - 0 : Idle This bit is set to 1 when the read/write access has been initiated. This bit is cleared when the access is completed. If phy_reg_clk_g is never activated.." "Idle,Pending" newline rbitfld.long 0x0 30. "PHY_VIEWPORT_STATUS,PHY viewport status. Indicates the status of the latest access. - 1 : Timeout - 0 : No errors If the timeout is detected this bit is set to 1 and PHY_VIEWPORT_PENDING is cleared. This bit is cleared when the read/write access is.." "No errors,Timeout" newline hexmask.long.byte 0x0 23.--29. 1. "RSVDP_23,Reserved for future use." newline bitfld.long 0x0 22. "PHY_VIEWPORT_TIMEOUT_DISABLE,PHY viewport timeout disable. Disables the PHY register access timeout structure. When the timeout is disabled you must ensure that the PHY register accesses are always acknowledged by cr_para_ack. Otherwise.." "0,1" newline bitfld.long 0x0 21. "PHY_VIEWPORT_BCWR,Broadcast write access to all xN sub-blocks. If you need to broadcast the write accesses into all lanes both PHY_VIEWPORT_ADDR[15] and this bit should be 1. Note: This register field is sticky." "0,1" newline bitfld.long 0x0 20. "PHY_VIEWPORT_READ,PHY viewport read. If set a read access is initiated. The value is always 0 when this bit is read. Note: This register field is sticky." "0,1" newline hexmask.long.byte 0x0 16.--19. 1. "PHY_VIEWPORT_NUM,PHY viewport xN sub-block number. Selects one of xN sub-blocks. This register is not used when the write access is initiated with PHY_VIEWPORT_BCWR==1. Note: This register field is sticky." newline hexmask.long.word 0x0 0.--15. 1. "PHY_VIEWPORT_ADDR,PHY viewport address. Indicates the PHY's register address. Please refer to the PHY databook for the address map definition. Note: This register field is sticky." line.long 0x4 "PHY_VIEWPORT_DATA_OFF,PHY Register Viewport Data Register." hexmask.long.word 0x4 16.--31. 1. "RSVDP_16,Reserved for future use." newline hexmask.long.word 0x4 0.--15. 1. "PHY_VIEWPORT_DATA,PHY viewport data. A write access to this register initiates the PHY register write access. By a read access to this register this field returns the latest read data from the PHY register. Note: This register field is sticky." group.long (0x490+0x700)++0x3 line.long 0x0 "PIPE_RELATED_OFF,PIPE Related Register. This register controls the pipe's capabitity. control. and status parameters." hexmask.long.tbyte 0x0 9.--31. 1. "RSVDP_9,Reserved for future use." newline bitfld.long 0x0 8. "PIPE_GARBAGE_DATA_MODE,PIPE Garbage Data Mode. - 0: PIPE Spec compliant mode: The MAC discards any symbols received after the electrical idle ordered-set until RxValid is deasserted. - 1: Special PHY Support mode: The MAC discards any symbols received.." "PIPE Spec compliant mode: The MAC discards any..,Special PHY Support mode: The MAC discards any.." tree.end tree.end tree "PCIE1_PF1" base ad:0xF1060000 tree "PF0_TYPE1_HDR (PCI-Compatible Configuration Space Header Type1)" group.long 0x0++0x2F line.long 0x0 "TYPE1_DEV_ID_VEND_ID_REG,Device ID and Vendor ID Register." hexmask.long.word 0x0 16.--31. 1. "DEVICE_ID,Device ID. The Device ID register identifies the particular Function. This identifier is allocated by the vendor. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else.." newline hexmask.long.word 0x0 0.--15. 1. "VENDOR_ID,Vendor ID. The Vendor ID register identifies the manufacturer of the Function. Valid vendor identifiers are allocated by the PCI-SIG to ensure uniqueness. It is not permitted to populate this register with a value of FFFFh which is an invalid.." line.long 0x4 "TYPE1_STATUS_COMMAND_REG,Status and Command Register." bitfld.long 0x4 31. "DETECTED_PARITY_ERROR,Detected Parity Error. This bit is set by a Function whenever it receives a Poisoned TLP regardless of the state the Parity Error Response bit in the Command register. The bit is set when the Poisoned TLP is received by a.." "0,1" newline bitfld.long 0x4 30. "SIGNALED_SYS_ERROR,Signaled System Error. This bit is set when a Function sends an ERR_FATAL or ERR_NONFATAL Message and the SERR# Enable bit in the Command register is 1b." "0,1" newline bitfld.long 0x4 29. "RCVD_MASTER_ABORT,Received Master Abort. This bit is set when a Requester receives a Completion with Unsupported Request Completion status. The bit is set when the Unsupported Request is received by a Function's primary side." "0,1" newline bitfld.long 0x4 28. "RCVD_TARGET_ABORT,Received Target Abort. This bit is set when a Requester receives a Completion with Completer Abort Completion status. The bit is set when the Completer Abort is received by a Function's primary side." "0,1" newline bitfld.long 0x4 27. "SIGNALED_TARGET_ABORT,Signaled Target Abort. This bit is set when a Function completes a Posted or Non-Posted Request as a Completer Abort error. This applies to a Function when the Completer Abort was generated by its primary side." "0,1" newline rbitfld.long 0x4 25.--26. "DEV_SEL_TIMING,DEVSEL Timing. This field was originally described in the PCI Local Bus Specification. Its functionality does not apply to PCI Express. The controller hardwires it to 00b." "0,1,2,3" newline bitfld.long 0x4 24. "MASTER_DPE,Master Data Parity Error. This bit is set by a Function if the Parity Error Response bit in the Command register is 1b and either of the following two conditions occurs: - Port receives a Poisoned Completion going downstream - Port transmits a.." "0,1" newline rbitfld.long 0x4 23. "FAST_B2B_CAP,Fast Back-to-Back Transactions Capable. This bit was originally described in the PCI Local Bus Specification. Its functionality does not apply to PCI Express. The controller hardwires this bit to 0b." "0,1" newline rbitfld.long 0x4 22. "RSVDP_22,Reserved for future use." "0,1" newline rbitfld.long 0x4 21. "FAST_66MHZ_CAP,66 MHz Capable. This bit was originally described in the PCI Local Bus Specification. Its functionality does not apply to PCI Express. The controller hardwires this bit to 0b." "0,1" newline rbitfld.long 0x4 20. "CAP_LIST,Capabilities List. Indicates the presence of an Extended Capability list item. Since all PCI Express device Functions are required to implement the PCI Express Capability structure the controller hardwires this bit to 1b." "0,1" newline rbitfld.long 0x4 19. "INT_STATUS,Interrupt Status. When set indicates that an INTx emulation interrupt is pending internally in the Function. INTx emulation interrupts forwarded by Functions from the secondary side are not reflected in this bit. Setting the Interrupt Disable.." "0,1" newline rbitfld.long 0x4 17.--18. "RSVDP_17,Reserved for future use." "0,1,2,3" newline bitfld.long 0x4 16. "IMM_READINESS,Immediate Readiness. This optional bit when set indicates the Function is guaranteed to be ready to successfully complete valid configuration accesses at any time following any reset that the host is capable of issuing Configuration.." "0,1" newline hexmask.long.byte 0x4 11.--15. 1. "RESERV,Reserved." newline bitfld.long 0x4 10. "INT_EN,Interrupt Disable. Controls the ability of a Function to generate INTx emulation interrupts. When set Functions are prevented from asserting INTx interrupts. Note: - Any INTx emulation interrupts already asserted by the Function must be.." "0,1" newline rbitfld.long 0x4 9. "RSVDP_9,Reserved for future use." "0,1" newline bitfld.long 0x4 8. "SERREN,SERR# Enable. When set this bit enables reporting upstream of Non-fatal and Fatal errors detected by the Function. Note: The errors are reported if enabled either through this bit or through the PCI Express specific bits in the Device Control.." "0,1" newline rbitfld.long 0x4 7. "IDSEL,IDSEL Stepping/Wait Cycle Control. This bit was originally described in the PCI Local Bus Specification. Its functionality does not apply to PCI Express. The controller hardwires this bit to 0b." "0,1" newline bitfld.long 0x4 6. "PERREN,Parity Error Response. This bit controls the logging of poisoned TLPs in the Master Data Parity Error bit in the Status register. For more details see the 'Error Registers' section of the PCI Express Base Specification." "0,1" newline rbitfld.long 0x4 5. "VGAPS,VGA Palette Snoop. This bit was originally described in the PCI Local Bus Specification and the PCI-to-PCI Bridge Architecture Specification. Its functionality does not apply to PCI Express. The controller hardwires this bit to 0b." "0,1" newline rbitfld.long 0x4 4. "MWI_EN,Memory Write and Invalidate. This bit was originally described in the PCI Local Bus Specification and the PCI-to-PCI Bridge Architecture Specification. Its functionality does not apply to PCI Express. The controller hardwires this bit to 0b. For.." "0,1" newline rbitfld.long 0x4 3. "SCO,Special Cycle Enable. This bit was originally described in the PCI Local Bus Specification. Its functionality does not apply to PCI Express. The controller hardwires this bit to 0b." "0,1" newline bitfld.long 0x4 2. "BME,Bus Master Enable. This bit controls forwarding of Memory or I/O requests by a port in the Upstream direction. When this bit is 0b Memory and I/O Requests received at a Root Port must be handled as Unsupported Requests (UR) For Non-Posted Requests a.." "0,1" newline bitfld.long 0x4 1. "MSE,Memory Space Enable. This bit controls a Function's response to Memory Space accesses received on its primary side. - When set the Function is enabled to decode the address and further process Memory Space accesses. - When clear all received Memory.." "0,1" newline bitfld.long 0x4 0. "IO_EN,IO Space Enable. This bit controls a Function's response to I/O Space accesses received on its primary side. - When set the Function is enabled to decode the address and further process I/O Space accesses. - When clear all received I/O accesses.." "0,1" line.long 0x8 "TYPE1_CLASS_CODE_REV_ID_REG,Class Code and Revision ID Register." hexmask.long.byte 0x8 24.--31. 1. "BASE_CLASS_CODE,Base Class Code. A code that broadly classifies the type of operation the Function performs. Encodings for base class are provided in the PCI Code and ID Assignment Specification. All unspecified encodings are reserved. Note: The access.." newline hexmask.long.byte 0x8 16.--23. 1. "SUBCLASS_CODE,Sub-Class Code. Specifies a base class sub-class which identifies more specifically the operation of the Function. Encodings for sub-class are provided in the PCI Code and ID Assignment Specification. All unspecified encodings are.." newline hexmask.long.byte 0x8 8.--15. 1. "PROGRAM_INTERFACE,Programming Interface. This field identifies a specific register level programming interface (if any) so that device independent software can interact with the Function. Encodings for interface are provided in the PCI Code and ID.." newline hexmask.long.byte 0x8 0.--7. 1. "REVISION_ID,Revision ID. The value of this field specifies a Function specific revision identifier. The value is chosen by the vendor. Zero is an acceptable value. The Revision ID should be viewed as a vendor defined extension to the Device ID. Note: The.." line.long 0xC "TYPE1_BIST_HDR_TYPE_LAT_CACHE_LINE_SIZE_REG,BIST. Header Type. Latency Timer. and Cache Line Size Register." hexmask.long.byte 0xC 24.--31. 1. "BIST,BIST. This register is used for control and status of BIST. Functions that do not support BIST must hardwire the register to 00h. A Function whose BIST is invoked must not prevent normal operation of the PCI Express Link. Bit descriptions: - [31]:.." newline rbitfld.long 0xC 23. "MULTI_FUNC,Multi-Function Device. - When set indicates that the device may contain multiple Functions but not necessarily. Software is permitted to probe for Functions other than Function 0. - When clear software must not probe for Functions other.." "0,1" newline hexmask.long.byte 0xC 16.--22. 1. "HEADER_TYPE,Header Layout. This field identifies the layout of the second part of the predefined header. The controller uses 000 0001b encoding. The encoding 000 0010b is reserved. This encoding was originally described in the PC Card Standard Electrical.." newline hexmask.long.byte 0xC 8.--15. 1. "LATENCY_MASTER_TIMER,Latency Timer. This register is also referred to as Primary Latency Timer. The Latency Timer was originally described in the PCI Local Bus Specification and the PCI-to-PCI Bridge Architecture Specification. Its functionality does not.." newline hexmask.long.byte 0xC 0.--7. 1. "CACHE_LINE_SIZE,Cache Line Size. The Cache Line Size register is programmed by the system firmware or the operating system to system cache line size. However legacy conventional PCI software may not always be able to program this register correctly.." line.long 0x10 "BAR0_REG,BAR0 Register. System software must build a consistent address map before booting the machine to an operating system. This means it has to determine how much memory is in the system. and how much address space the Functions in the system.." hexmask.long 0x10 4.--31. 1. "BAR0_START,BAR0 Base Address. - Memory Space: Base Address. - IO Space: bits[31:2] are used to map the function into IO space/Base. Address. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R(Sticky)/W(Sticky) if.." newline bitfld.long 0x10 3. "BAR0_PREFETCH,BAR0 Prefetchable. - Memory Space: Set to one if data is pre-fetchable. A Function is permitted to mark a range as prefetchable. If there are no side effects on reads the function returns all bytes on reads regardless of the byte enables.." "0,1" newline bitfld.long 0x10 1.--2. "BAR0_TYPE,BAR0 Type. - Memory Space: Base Address registers that map into Memory Space can be 32 bits or 64 bits wide (to support mapping into a 64-bit address space). The bit encoding is as follows: -- 00: Base register is 32 bits wide and can be mapped.." "Base register is 32 bits wide and can be mapped..,Reserved,?,?" newline bitfld.long 0x10 0. "BAR0_MEM_IO,BAR0 Memory Space Indicator. This bit is used to determine whether the register maps into Memory or I/O Space. Base Address registers that map to Memory Space must return a 0b. Base Address registers that map to I/O Space must return a 1b." "0,1" line.long 0x14 "BAR1_REG,BAR1 Register. System software must build a consistent address map before booting the machine to an operating system. This means it has to determine how much memory is in the system. and how much address space the Functions in the system.." hexmask.long 0x14 4.--31. 1. "BAR1_START,BAR1 Base Address. - Memory Space: Base Address. - IO Space: bits[31:2] are used to map the function into IO space/Base. Address. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R(Sticky)/W(Sticky) if.." newline bitfld.long 0x14 3. "BAR1_PREFETCH,BAR1 Prefetchable. - Memory Space: Set to one if data is pre-fetchable. A Function is permitted to mark a range as prefetchable. If there are no side effects on reads the function returns all bytes on reads regardless of the byte enables.." "0,1" newline bitfld.long 0x14 1.--2. "BAR1_TYPE,BAR1 Type. - Memory Space: Base Address registers that map into Memory Space can be 32 bits or 64 bits wide (to support mapping into a 64-bit address space). The bit encoding is as follows: -- 00: Base register is 32 bits wide and can be mapped.." "Base register is 32 bits wide and can be mapped..,Reserved,?,?" newline bitfld.long 0x14 0. "BAR1_MEM_IO,BAR1 Memory Space Indicator. This bit is used to determine whether the register maps into Memory or I/O Space. Base Address registers that map to Memory Space must return a 0b. Base Address registers that map to I/O Space must return a 1b." "0,1" line.long 0x18 "SEC_LAT_TIMER_SUB_BUS_SEC_BUS_PRI_BUS_REG,Secondary Latency Timer. Subordinate Bus Number. Secondary Bus Number. and Primary Bus Number Register." hexmask.long.byte 0x18 24.--31. 1. "SEC_LAT_TIMER,Secondary Latency Timer. This register does not apply to PCI Express. The controller hardwires it to 00h." newline hexmask.long.byte 0x18 16.--23. 1. "SUB_BUS,Subordinate Bus Number. The Subordinate Bus Number register is used to record the bus number of the highest numbered PCI bus segment which is behind (or subordinate to) the bridge. Configuration software programs the value in this register. The.." newline hexmask.long.byte 0x18 8.--15. 1. "SEC_BUS,Secondary Bus Number. The Secondary Bus Number register is used to record the bus number of the PCI bus segment to which the secondary interface of the bridge is connected. Configuration software programs the value in this register. The bridge.." newline hexmask.long.byte 0x18 0.--7. 1. "PRIM_BUS,Primary Bus Number. This register is not used by PCI Express Functions. It is implemented for compatibility with legacy software." line.long 0x1C "SEC_STAT_IO_LIMIT_IO_BASE_REG,Secondary Status. and I/O Limit and Base Register. The I/O Limit and I/O Base registers are optional and define an address range that is used by the bridge to determine when to forward I/O transactions from one interface to.." bitfld.long 0x1C 31. "SEC_STAT_DPE,Detected Parity Error. This bit is set by a Function when a Poisoned TLP is received by its secondary side regardless of the state the Parity Error Response Enable bit in the Bridge Control register." "0,1" newline bitfld.long 0x1C 30. "SEC_STAT_RCVD_SYS_ERR,Received System Error. This bit is set when the secondary side of a Function receives an ERR_FATAL or ERR_NONFATAL message." "0,1" newline bitfld.long 0x1C 29. "SEC_STAT_RCVD_MSTR_ABRT,Received Master Abort. This bit is set when the secondary side of a Function (for requests initiated by the Type 1 header Function itself) receives a Completion with Unsupported Request Completion status." "0,1" newline bitfld.long 0x1C 28. "SEC_STAT_RCVD_TRGT_ABRT,Received Target Abort. This bit is set when the secondary side of a Function (for requests initiated by the Type 1 header Function itself) receives a Completion with Completer Abort Completion status." "0,1" newline bitfld.long 0x1C 27. "SEC_STAT_SIG_TRGT_ABRT,Signaled Target Abort. This bit is set when the secondary side of the Function (for Requests completed by the Type 1 header Function itself) completes a Posted or Non-Posted request as a Completer Abort error." "0,1" newline rbitfld.long 0x1C 25.--26. "RSVDP_25,Reserved for future use." "0,1,2,3" newline bitfld.long 0x1C 24. "SEC_STAT_MDPE,Master Data Parity Error. This bit is set by a Function if the Parity Error Response Enable bit in the Bridge Control register is set and either of the following two conditions occurs: - Port receives a Poisoned Completion coming Upstream.." "0,1" newline rbitfld.long 0x1C 23. "RSVDP_23,Reserved for future use." "0,1" newline hexmask.long.byte 0x1C 16.--22. 1. "SEC_STAT_RESERV,Reserved." newline hexmask.long.byte 0x1C 12.--15. 1. "IO_LIMIT,I/O Limit Address. These bits correspond to the address[15:12] of IO address range. For the purpose of address decoding the bridge assumes that the lower 12 address bits address[11:0] of the I/O limit address (not implemented in the I/O Limit.." newline rbitfld.long 0x1C 9.--11. "IO_RESERV1,Reserved." "0,1,2,3,4,5,6,7" newline bitfld.long 0x1C 8. "IO_DECODE_BIT8,I/O Addressing Encode (IO Limit Address). This bit encodes the IO addressing capability of the bridge. IO_DECODE_BIT8 indicates the following: - 0h: The bridge supports only 16-bit I/O addressing (for ISA compatibility). For the purpose of.." "0,1" newline hexmask.long.byte 0x1C 4.--7. 1. "IO_BASE,I/O Base Address. These bits correspond to the address[15:12] of IO address range. For the purpose of address decoding the bridge assumes that the lower 12 address bits address[11:0] of the I/O base address (not implemented in the I/O Base.." newline rbitfld.long 0x1C 1.--3. "IO_RESERV,Reserved." "0,1,2,3,4,5,6,7" newline bitfld.long 0x1C 0. "IO_DECODE,I/O Addressing Encode (IO Base Address) This bit encodes the IO addressing capability of the bridge. IO_DECODE indicates the following: - 0h: The bridge supports only 16-bit I/O addressing (for ISA compatibility). For the purpose of address.." "0,1" line.long 0x20 "MEM_LIMIT_MEM_BASE_REG,Memory Limit and Base Register. The Memory Limit and Memory Base registers define a memory mapped address range which is used by the bridge to determine when to forward memory transactions from one interface to the other. If there.." hexmask.long.word 0x20 20.--31. 1. "MEM_LIMIT,Memory Limit Address. These bits correspond to the upper 12 address bits Address[31:20] of 32-bit addresses. For the purpose of address decoding the bridge assumes that the lower 20 address bits Address[19:0] of the memory limit address.." newline hexmask.long.byte 0x20 16.--19. 1. "MEM_LIMIT_RESERV,Reserved." newline hexmask.long.word 0x20 4.--15. 1. "MEM_BASE,Memory Base Address. These bits correspond to the upper 12 address bits Address[31:20] of 32-bit addresses. For the purpose of address decoding the bridge assumes that the lower 20 address bits Address[19:0] of the memory base address (not.." newline hexmask.long.byte 0x20 0.--3. 1. "MEM_BASE_RESERV,Reserved." line.long 0x24 "PREF_MEM_LIMIT_PREF_MEM_BASE_REG,Prefetchable Memory Limit and Base Register. The Prefetchable Memory Limit and Prefetchable Memory Base registers must indicate that 64-bit addresses are supported. as defined in PCI-to-PCI Bridge Architecture.." hexmask.long.word 0x24 20.--31. 1. "PREF_MEM_LIMIT,Prefetchable Memory Limit Address. If the Prefetchable Memory Limit register indicates support for 32-bit addressing then the Prefetchable Limit Upper 32 Bits register is implemented as a read-only register that returns zero when read. If.." newline rbitfld.long 0x24 17.--19. "PREF_RESERV1,Reserved." "0,1,2,3,4,5,6,7" newline rbitfld.long 0x24 16. "PREF_MEM_LIMIT_DECODE,Prefetchable Memory Limit Decode. This bit encodes whether or not the bridge supports 64-bit addresses. Note: This bit is a copy of the PREF_MEM_DECODE bit and always reflects the current value of that bit. The value of.." "0,1" newline hexmask.long.word 0x24 4.--15. 1. "PREF_MEM_BASE,Prefetchable Memory Base Address. If the Prefetchable Memory Base register indicates support for 32-bit addressing then the Prefetchable Base Upper 32 Bits register is implemented as a read-only register that returns zero when read. If the.." newline rbitfld.long 0x24 1.--3. "PREF_RESERV,Reserved." "0,1,2,3,4,5,6,7" newline bitfld.long 0x24 0. "PREF_MEM_DECODE,Prefetchable Memory Base Decode. This bit encodes whether or not the bridge supports 64-bit addresses. Note: By default the bit is set to 1'b1 indicating that 64-bit addresses are supported. If the bridge only supports 32-bit prefetchable.." "0,1" line.long 0x28 "PREF_BASE_UPPER_REG,Prefetchable Base Upper 32 Bits Register. The Prefetchable Base Upper 32 Bits register is an optional extension to the Prefetchable Memory Base register." hexmask.long 0x28 0.--31. 1. "PREF_MEM_BASE_UPPER,Prefetchable Base Upper 32 Bit. If the Prefetchable Memory Base register indicates support for 32-bit addressing then this register is implemented as read-only register that returns zero when read. If the Prefetchable Memory Base.." line.long 0x2C "PREF_LIMIT_UPPER_REG,Prefetchable Limit Upper 32 Bits Register. The Prefetchable Limit Upper 32 Bits register is an optional extension to the Prefetchable Memory Limit register." hexmask.long 0x2C 0.--31. 1. "PREF_MEM_LIMIT_UPPER,Prefetchable Limit Upper 32 Bit. If the Prefetchable Memory Limit register indicate support for 64-bit addressing then this register is implemented as read/write register which must be initialized by configuration software. This.." rgroup.long 0x30++0x3 line.long 0x0 "IO_LIMIT_UPPER_IO_BASE_UPPER_REG,I/O Limit and Base Upper 16 Bits Register. The I/O Limit Upper 16 Bits and I/O Base Upper 16 Bits registers are optional extensions to the I/O Limit and I/O Base registers." hexmask.long.word 0x0 16.--31. 1. "IO_LIMIT_UPPER,I/O Limit Upper 16 Bits. If the I/O Limit register indicates support for 16-bit I/O address decoding then this register is implemented as a read-only register which return zero when read. If the I/O Limit register indicates support for.." newline hexmask.long.word 0x0 0.--15. 1. "IO_BASE_UPPER,I/O Base Upper 16 Bits. If the I/O Base register indicates support for 16-bit I/O address decoding then this register is implemented as a read-only register which return zero when read. If the I/O base register indicates support for 32-bit.." group.long 0x34++0xB line.long 0x0 "TYPE1_CAP_PTR_REG,Capabilities Pointer Register." hexmask.long.tbyte 0x0 8.--31. 1. "RSVDP_8,Reserved for future use." newline hexmask.long.byte 0x0 0.--7. 1. "CAP_POINTER,Capabilities Pointer. This register is used to point to a linked list of capabilities implemented by this Function. Since all PCI Express Functions are required to implement the PCI Express Capability structure this register must point to a.." line.long 0x4 "TYPE1_EXP_ROM_BASE_REG,Expansion ROM Base Address Register. This register is defined to handle the base address and size information for this expansion ROM. The mask for this ROM BAR exists (if implemented) as a shadow register at this address. The.." hexmask.long.tbyte 0x4 11.--31. 1. "EXP_ROM_BASE_ADDRESS,Expansion ROM Base Address. Upper 21 bits of the Expansion ROM base address. The number of bits (out of these 21) that a Function actually implements depends on how much address space the Function requires. The mask for this ROM BAR.." newline hexmask.long.word 0x4 1.--10. 1. "RSVDP_1,Reserved for future use." newline bitfld.long 0x4 0. "ROM_BAR_ENABLE,Expansion ROM Enable. This bit controls whether or not the Function accepts accesses to its expansion ROM. When this bit is 0b the Function's expansion ROM address space is disabled. When the bit is 1b address decoding is enabled using.." "0,1" line.long 0x8 "BRIDGE_CTRL_INT_PIN_INT_LINE_REG,Bridge Control. Interrupt Pin. and Interrupt Line Register." hexmask.long.word 0x8 23.--31. 1. "BRIDGE_CTRL_RESERV,Reserved." newline bitfld.long 0x8 22. "SBR,Secondary Bus Reset. Setting this bit triggers a hot reset on the corresponding PCI Express Port. Software must ensure a minimum reset duration (Trst) as defined in the PCI Local Bus Specification. Software and systems must honor.." "0,1" newline rbitfld.long 0x8 21. "MSTR_ABORT_MODE,Master Abort Mode. This bit was originally described in the PCI-to-PCI Bridge Architecture Specification. Its functionality does not apply to PCI Express. The controller hardwires this bit to 0b. Note: The access attributes of this field.." "0,1" newline rbitfld.long 0x8 20. "VGA_16B_DEC,VGA 16 bit decode. This bit only has meaning if VGA Enable bit is set. This bit enables system configuration software to select between 10-bit and 16-bit I/O address decoding for all VGA I/O register accesses that are forwarded from primary.." "0,1" newline rbitfld.long 0x8 19. "VGA_EN,VGA Enable. Modifies the response by the bridge to VGA compatible addresses. If the VGA Enable bit is set the bridge will positively decode and forward the following accesses on the primary interface to the secondary interface (and conversely.." "0,1" newline bitfld.long 0x8 18. "ISA_EN,ISA Enable. Modifies the response by the bridge to ISA I/O addresses. This applies only to I/O addresses that are enabled by the I/O Base and I/O Limit registers and are in the first 64 KB of I/O address space (0000 0000h to 0000 FFFFh). If this.." "?,KB block" newline bitfld.long 0x8 17. "SERR_EN,SERR# Enable. This bit controls forwarding of ERR_COR ERR_NONFATAL and ERR_FATAL from secondary to primary." "0,1" newline bitfld.long 0x8 16. "PERE,Parity Error Response Enable. This bit controls the logging of poisoned TLPs in the Master Data Parity Error bit in the Secondary Status register." "0,1" newline hexmask.long.byte 0x8 8.--15. 1. "INT_PIN,Interrupt PIN. The Interrupt Pin register register that identifies the legacy interrupt Message(s) the Function uses. Valid values are: - 01h 02h 03h and 04h: map to legacy interrupt Messages for INTA INTB INTC and INTD respectively. - 00h:.." newline hexmask.long.byte 0x8 0.--7. 1. "INT_LINE,Interrupt Line. The Interrupt Line register communicates interrupt line routing information. The register must be implemented by any Function that uses an interrupt pin. Values in this register are programmed by system software and are system.." tree.end tree "PF0_SPCIE_CAP (Secondary PCI Express Capability Structure)" group.long (0x0+0x1A0)++0xF line.long 0x0 "SPCIE_CAP_HEADER_REG,SPCIE Capability Header. For a description of this standard PCIe register. see the PCI Express Specification." hexmask.long.word 0x0 20.--31. 1. "NEXT_OFFSET,Next Capability Offset. For a description of this standard PCIe register field see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky).." hexmask.long.byte 0x0 16.--19. 1. "CAP_VERSION,Capability Version. For a description of this standard PCIe register field see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else.." hexmask.long.word 0x0 0.--15. 1. "EXTENDED_CAP_ID,Secondary PCI Express Extended Capability ID. For a description of this standard PCIe register field see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN.." line.long 0x4 "LINK_CONTROL3_REG,Link Control 3 Register. For a description of this standard PCIe register. see the PCI Express Specification." hexmask.long 0x4 2.--31. 1. "RSVDP_2,Reserved for future use." bitfld.long 0x4 1. "EQ_REQ_INT_EN,Link Equalization Request Interrupt Enable. For a description of this standard PCIe register field see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" "0,1" bitfld.long 0x4 0. "PERFORM_EQ,Perform Equalization. For a description of this standard PCIe register field see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" "0,1" line.long 0x8 "LANE_ERR_STATUS_REG,Lane Error Status Register. For a description of this standard PCIe register. see the PCI Express Specification." hexmask.long 0x8 2.--31. 1. "RSVDP_LANE_ERR_STATUS,Reserved for future use." bitfld.long 0x8 0.--1. "LANE_ERR_STATUS,Lane Error Status Bits per Lane. For a description of this standard PCIe register field see the PCI Express Specification." "0,1,2,3" line.long 0xC "SPCIE_CAP_OFF_0CH_REG,Lane Equalization Control Register for lanes 1 and 0. For a description of this standard PCIe register. see the PCI Express Specification." rbitfld.long 0xC 31. "RSVDP_31,Reserved for future use." "0,1" bitfld.long 0xC 28.--30. "USP_RX_PRESET_HINT1,Upstream Port 8.0 GT/s Receiver Preset Hint 1. The write value is gated with the PCIE_CAP_CROSS_LINK_SUPPORT field of LINK_CAPABILITIES2_REG. For a description of this standard PCIe register field see the PCI Express Specification." "0,1,2,3,4,5,6,7" hexmask.long.byte 0xC 24.--27. 1. "USP_TX_PRESET1,Upstream Port 8.0 GT/s Transmitter Preset 1. The write value is gated with the PCIE_CAP_CROSS_LINK_SUPPORT field of LINK_CAPABILITIES2_REG. For a description of this standard PCIe register field see the PCI Express Specification. Note:.." rbitfld.long 0xC 23. "RSVDP_23,Reserved for future use." "0,1" newline bitfld.long 0xC 20.--22. "DSP_RX_PRESET_HINT1,Downstream Port 8.0 GT/s Receiver Preset Hint 1. For a description of this standard PCIe register field see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if.." "0,1,2,3,4,5,6,7" hexmask.long.byte 0xC 16.--19. 1. "DSP_TX_PRESET1,Downstream Port 8.0 GT/s Transmitter Preset 1. For a description of this standard PCIe register field see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN.." rbitfld.long 0xC 15. "RSVDP_15,Reserved for future use." "0,1" bitfld.long 0xC 12.--14. "USP_RX_PRESET_HINT0,Upstream Port 8.0 GT/s Receiver Preset Hint 0. The write value is gated with the PCIE_CAP_CROSS_LINK_SUPPORT field of LINK_CAPABILITIES2_REG. For a description of this standard PCIe register field see the PCI Express Specification." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0xC 8.--11. 1. "USP_TX_PRESET0,Upstream Port 8.0 GT/s Transmitter Preset 0. The write value is gated with the PCIE_CAP_CROSS_LINK_SUPPORT field of LINK_CAPABILITIES2_REG. For a description of this standard PCIe register field see the PCI Express Specification. Note:.." rbitfld.long 0xC 7. "RSVDP_7,Reserved for future use." "0,1" bitfld.long 0xC 4.--6. "DSP_RX_PRESET_HINT0,Downstream Port 8.0 GT/s Receiver Preset Hint 0. For a description of this standard PCIe register field see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if.." "0,1,2,3,4,5,6,7" hexmask.long.byte 0xC 0.--3. 1. "DSP_TX_PRESET0,Downstream Port 8.0 GT/s Transmitter Preset 0. For a description of this standard PCIe register field see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN.." tree.end tree "PF0_L1SUB_CAP (L1 Substates Capability Structure)" group.long (0x0+0x2E8)++0xF line.long 0x0 "L1SUB_CAP_HEADER_REG,L1 Substates Extended Capability Header. This register provides capbility ID. capability version and next offset value for L1 Substates." hexmask.long.word 0x0 20.--31. 1. "NEXT_OFFSET,Next Capability Offset. This field contains the offset to the next PCI Express Capability structure or 000h if no other items exist in the linked list of Capabilities. For Extended Capabilities implemented in Configuration Space this offset.." hexmask.long.byte 0x0 16.--19. 1. "CAP_VERSION,Capability Version. This field is a PCI-SIG defined version number that indicates the version of the Capability structure present. This field is depends on version of the specification. Note: The access attributes of this field are as.." hexmask.long.word 0x0 0.--15. 1. "EXTENDED_CAP_ID,L1SUB Extended Capability ID. This field is a PCI-SIG defined ID number that indicates the nature and format of the Extended Capability. Extended Capability ID for L1 PM Substates is 001Eh. Note: The access attributes of this field are as.." line.long 0x4 "L1SUB_CAPABILITY_REG,L1 Substates Capability Register. This register provides extended capability of L1 Substates." hexmask.long.byte 0x4 24.--31. 1. "RSVDP_24,Reserved for future use." hexmask.long.byte 0x4 19.--23. 1. "PWR_ON_VALUE_SUPPORT,Port T Power On Value. Along with the Port T_POWER_ON Scale field in the L1 PM Substates Capabilities register sets the time (in us) that this Port requires the port on the opposite side of Link to wait in L1.2.Exit after sampling.." rbitfld.long 0x4 18. "RSVDP_18,Reserved for future use." "0,1" bitfld.long 0x4 16.--17. "PWR_ON_SCALE_SUPPORT,Port T Power On Scale. Specifies the scale used for the Port T_POWER_ON Value field in the L1 PM Substates Capabilities register. Range of values are given below. Required for all Ports for which either the PCI-PM L1.2 Supported bit.." "?,?,?,Reserved" newline hexmask.long.byte 0x4 8.--15. 1. "COMM_MODE_SUPPORT,Port Common Mode Restore Time. Time (in us) required for this Port to re-establish common mode. Required for all Ports for which either the PCI-PM L1.2 Supported bit is Set ASPM L1.2 Supported bit is Set or both are Set otherwise.." rbitfld.long 0x4 5.--7. "RSVDP_5,Reserved for future use." "0,1,2,3,4,5,6,7" bitfld.long 0x4 4. "L1_PMSUB_SUPPORT,L1 PM Substates ECN Supported. When Set this bit indicates that this Port supports L1 PM Substates. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W (sticky)" "0,1" bitfld.long 0x4 3. "L1_1_ASPM_SUPPORT,ASPM L11 Supported. When Set this bit indicates that ASPM L1.1 is supported. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W (sticky)" "0,1" newline bitfld.long 0x4 2. "L1_2_ASPM_SUPPORT,ASPM L12 Supported. When Set this bit indicates that ASPM L1.2 is supported. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W (sticky)" "0,1" bitfld.long 0x4 1. "L1_1_PCIPM_SUPPORT,PCI-PM L11 Supported. When Set this bit indicates that PCI-PM L1.1 is supported and must be Set by all Ports implementing L1 PM Substates. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W (sticky)" "0,1" bitfld.long 0x4 0. "L1_2_PCIPM_SUPPORT,PCI-PM L12 Supported. When Set this bit indicates that PCI-PM L1.2 is supported. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W (sticky)" "0,1" line.long 0x8 "L1SUB_CONTROL1_REG,L1 Substates Control 1 Register. This register provides Controls to extended capability." bitfld.long 0x8 29.--31. "L1_2_TH_SCA,LTR L12 Threshold Scale. This field provides a scale for the value contained within the LTR_L1.2_THRESHOLD_Value.The default value for this field is 000b.Hardware operation is undefined if software writes a Not-Permitted value to this field." "0,1,2,3,4,5,6,7" rbitfld.long 0x8 26.--28. "RSVDP_26,Reserved for future use." "0,1,2,3,4,5,6,7" hexmask.long.word 0x8 16.--25. 1. "L1_2_TH_VAL,LTR L12 Threshold Value. Along with the LTR_L1.2_THRESHOLD_Scale this field indicates the LTR threshold used to determine if entry into L1 results in L1.1 (if enabled) or L1.2 (if enabled). The default value for this field is 00 0000 0000b." hexmask.long.byte 0x8 8.--15. 1. "T_COMMON_MODE,Common Mode Restore Time. Sets value of TCOMMONMODE (in us) which must be used by the Downstream Ports for timing the re-establishment of common mode.This field is of type RsvdP for Upstream Ports. Default value is implementation.." newline hexmask.long.byte 0x8 4.--7. 1. "RSVDP_4,Reserved for future use." bitfld.long 0x8 3. "L1_1_ASPM_EN,ASPM L11 Enable. When Set this bit enables ASPM L1.1.For Ports for which the ASPM L1.1 Supported bit is Clear this bit is permitted to be hardwired to 0.Default value is 0b." "0,1" bitfld.long 0x8 2. "L1_2_ASPM_EN,ASPM L12 Enable. When Set this bit enables ASPM L1.2.For Ports for which the ASPM L1.2 Supported bit is Clear this bit is permitted to be hardwired to 0.Default value is 0b." "0,1" bitfld.long 0x8 1. "L1_1_PCIPM_EN,PCI-PM L11 Enable. When Set this bit enables PCI-PM L1.1. Default value is 0b." "0,1" newline bitfld.long 0x8 0. "L1_2_PCIPM_EN,PCI-PM L12 Enable. When Set this bit enables PCI-PM L1.2.For Ports for which the PCI-PM L1.2 Supported bit is Clear this bit is permitted to be hardwired to 0.Default value is 0b." "0,1" line.long 0xC "L1SUB_CONTROL2_REG,L1 Substates Control 2 Register. This register provides Controls to extended capability." hexmask.long.tbyte 0xC 8.--31. 1. "RSVDP_8,Reserved for future use." hexmask.long.byte 0xC 3.--7. 1. "T_POWER_ON_VALUE,T Power On Value. Along with the T_POWER_ON Scale sets the minimum amount of time (in us) that the Port must wait in L1.2.Exit after sampling CLKREQ# asserted before actively driving the interface.Default value is 00101b. T_POWER_ON is.." rbitfld.long 0xC 2. "RSVDP_2,Reserved for future use." "0,1" bitfld.long 0xC 0.--1. "T_POWER_ON_SCALE,T Power On Scale. Specifies the scale used for T_POWER_ON Value. Range of values are given below. Required for all Ports that support L1.2 otherwise this field is of type RsvdP. This field must only be modified when the ASPM L1.2 Enable.." "?,?,?,Reserved" tree.end tree "PF0_RAS_DES_CAP (RAS D.E.S. Capability Structure (VSEC))" group.long (0x0+0x30C)++0x3 line.long 0x0 "RAS_DES_CAP_HEADER_REG,Vendor-Specific Extended Capability Header. For a description of this standard PCIe register. see the PCI Express Specification." hexmask.long.word 0x0 20.--31. 1. "NEXT_OFFSET,Next Capability Offset. For a description of this standard PCIe register field see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky).." newline hexmask.long.byte 0x0 16.--19. 1. "CAP_VERSION,Capability Version. For a description of this standard PCIe register field see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else.." newline hexmask.long.word 0x0 0.--15. 1. "EXTENDED_CAP_ID,PCI Express Extended Capability ID. For a description of this standard PCIe register field see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then.." rgroup.long (0x4+0x30C)++0x3 line.long 0x0 "VENDOR_SPECIFIC_HEADER_REG,Vendor-Specific Header. For a description of this standard PCIe register. see the PCI Express Specification." hexmask.long.word 0x0 20.--31. 1. "VSEC_LENGTH,VSEC Length. For a description of this standard PCIe register field see the PCI Express Specification." newline hexmask.long.byte 0x0 16.--19. 1. "VSEC_REV,VSEC Rev. For a description of this standard PCIe register field see the PCI Express Specification." newline hexmask.long.word 0x0 0.--15. 1. "VSEC_ID,VSEC ID. For a description of this standard PCIe register field see the PCI Express Specification." group.long (0x8+0x30C)++0x3 line.long 0x0 "EVENT_COUNTER_CONTROL_REG,Event Counter Control. This is a viewport control register. - Setting the EVENT_COUNTER_EVENT_SELECT and EVENT_COUNTER_LANE_SELECT fields in this register determine the Event Counter data returned by the EVENT_COUNTER_DATA_REG.." hexmask.long.byte 0x0 28.--31. 1. "RSVDP_28,Reserved for future use." newline hexmask.long.word 0x0 16.--27. 1. "EVENT_COUNTER_EVENT_SELECT,Event Counter Data Select. This field in conjunction with the EVENT_COUNTER_LANE_SELECT field indexes the Event Counter data returned by the EVENT_COUNTER_DATA_REG register. - 27-24: Group number(4-bit: 0..0x7) - 23-16: Event.." newline hexmask.long.byte 0x0 12.--15. 1. "RSVDP_12,Reserved for future use." newline hexmask.long.byte 0x0 8.--11. 1. "EVENT_COUNTER_LANE_SELECT,Event Counter Lane Select. This field in conjunction with EVENT_COUNTER_EVENT_SELECT indexes the Event Counter data returned by the EVENT_COUNTER_DATA_REG register. - 0x0: Lane0 - 0x1: Lane1 - 0x2: Lane2 - .. - 0xF: Lane15 Note:.." newline rbitfld.long 0x0 7. "EVENT_COUNTER_STATUS,Event Counter Status. This register returns the current value of the Event Counter selected by the following fields: - EVENT_COUNTER_EVENT_SELECT - EVENT_COUNTER_LANE_SELECT Note: This register field is sticky." "0,1" newline rbitfld.long 0x0 5.--6. "RSVDP_5,Reserved for future use." "0,1,2,3" newline bitfld.long 0x0 2.--4. "EVENT_COUNTER_ENABLE,Event Counter Enable. Enables/disables the Event Counter selected by the EVENT_COUNTER_EVENT_SELECT and EVENT_COUNTER_LANE_SELECT fields in this register. By default all event counters are disabled. You can enable/disable a specific.." "no change,per event off,?,?,?,?,?,?" newline bitfld.long 0x0 0.--1. "EVENT_COUNTER_CLEAR,Event Counter Clear. Clears the Event Counter selected by the EVENT_COUNTER_EVENT_SELECT and EVENT_COUNTER_LANE_SELECT fields in this register. You can clear the value of a specific Event Counter by writing the 'per clear' code and.." "no change,per clear,?,?" rgroup.long (0xC+0x30C)++0x3 line.long 0x0 "EVENT_COUNTER_DATA_REG,Event Counter Data. This viewport register returns the data selected by the following fields: - EVENT_COUNTER_EVENT_SELECT in EVENT_COUNTER_CONTROL_REG - EVENT_COUNTER_LANE_SELECT in EVENT_COUNTER_CONTROL_REG For more details. see.." hexmask.long 0x0 0.--31. 1. "EVENT_COUNTER_DATA,Event Counter Data. This register returns the data selected by the following fields: - EVENT_COUNTER_EVENT_SELECT in EVENT_COUNTER_CONTROL_REG - EVENT_COUNTER_LANE_SELECT in EVENT_COUNTER_CONTROL_REG Note: This register field is sticky." group.long (0x10+0x30C)++0x3 line.long 0x0 "TIME_BASED_ANALYSIS_CONTROL_REG,Time-based Analysis Control. Used for controlling the measurement of RX/TX data throughput and time spent in each low-power LTSSM state. For more details. see the RAS DES section in the Core Operations chapter of the.." hexmask.long.byte 0x0 24.--31. 1. "TIME_BASED_REPORT_SELECT,Time-based Report Select. Selects what type of data is measured for the selected duration (TIME_BASED_DURATION_SELECT) and returned in TIME_BASED_ANALYSIS_DATA. Each type of data is measured using one of three types of units: -.." newline hexmask.long.byte 0x0 16.--23. 1. "RSVDP_16,Reserved for future use." newline hexmask.long.byte 0x0 8.--15. 1. "TIME_BASED_DURATION_SELECT,Time-based Duration Select. Selects the duration of time-based analysis. When 'manual control' is selected and TIMER_START is set to '1' this analysis never stops until TIMER_STOP is set to '0'. - 0x0: Manual control - 0x1:.." newline hexmask.long.byte 0x0 1.--7. 1. "RSVDP_1,Reserved for future use." newline bitfld.long 0x0 0. "TIMER_START,Timer Start. - 1: Start/Restart - 0: Stop This bit will be cleared automatically when the measurement is finished. Note: The app_ras_des_tba_ctrl input also sets the contents of this field and controls the measurement start/stop. Note: This.." "Stop,Start/Restart" rgroup.long (0x14+0x30C)++0x7 line.long 0x0 "TIME_BASED_ANALYSIS_DATA_REG,Time-based Analysis Data. Contains the measurement results of RX/TX data throughput and time spent in each low-power LTSSM state. This viewport register returns the data selected by the TIME_BASED_REPORT_SELECT field in.." hexmask.long 0x0 0.--31. 1. "TIME_BASED_ANALYSIS_DATA,Time Based Analysis Data. This register returns the data selected by the TIME_BASED_REPORT_SELECT field in TIME_BASED_ANALYSIS_CONTROL_REG. The results are cleared when next measurement starts. Note: This register field is sticky." line.long 0x4 "TIME_BASED_ANALYSIS_DATA_63_32_REG,Upper 32 bits of Time-based Analysis Data. This viewport register returns the data selected by the TIME_BASED_REPORT_SELECT field in TIME_BASED_ANALYSIS_CONTROL_REG. For more details. see the RAS DES section in the Core.." hexmask.long 0x4 0.--31. 1. "TIME_BASED_ANALYSIS_DATA_63_32,Upper 32 bits of Time Based Analysis Data. Note: This register field is sticky." group.long (0x30+0x30C)++0x5F line.long 0x0 "EINJ_ENABLE_REG,Error Injection Enable. Each type of error insertion is enabled by the corresponding bit in this register. The specific injection controls for each type of error are defined in the following registers: - 0: CRC Error: EINJ0_CRC_REG - 1:.." hexmask.long 0x0 7.--31. 1. "RSVDP_7,Reserved for future use." newline bitfld.long 0x0 6. "ERROR_INJECTION6_ENABLE,Error Injection6 Enable (Specific TLP Error). Enables insertion of errors into the packets that you select. You can set this bit to '1' when you have disabled RAS datapath protection (DP) by setting CX_RASDP = CX_RASDP_RAM_PROT.." "0,1" newline bitfld.long 0x0 5. "ERROR_INJECTION5_ENABLE,Error Injection5 Enable (TLP Duplicate/Nullify Error). Enables insertion of duplicate/nullified TLPs. For more details see the EINJ5_SP_TLP_REG register. Note: This register field is sticky." "0,1" newline bitfld.long 0x0 4. "ERROR_INJECTION4_ENABLE,Error Injection4 Enable (FC Credit Update Error). Enables insertion of errors into UpdateFCs. For more details see the EINJ4_FC_REG register. Note: This register field is sticky." "0,1" newline bitfld.long 0x0 3. "ERROR_INJECTION3_ENABLE,Error Injection3 Enable (Symbol DataK Mask Error or Sync Header Error). Enables DataK masking of special symbols or the breaking of the sync header. For more details see the EINJ3_SYMBOL_REG register. Note: This register field is.." "0,1" newline bitfld.long 0x0 2. "ERROR_INJECTION2_ENABLE,Error Injection2 Enable (DLLP Error). Enables insertion of DLLP errors. For more details see the EINJ2_DLLP_REG register. Note: This register field is sticky." "0,1" newline bitfld.long 0x0 1. "ERROR_INJECTION1_ENABLE,Error Injection1 Enable (Sequence Number Error). Enables insertion of errors into sequence numbers. For more details see the EINJ1_SEQNUM_REG register. Note: This register field is sticky." "0,1" newline bitfld.long 0x0 0. "ERROR_INJECTION0_ENABLE,Error Injection0 Enable (CRC Error). Enables insertion of errors into various CRC. For more details see the EINJ0_CRC_REG register. Note: This register field is sticky." "0,1" line.long 0x4 "EINJ0_CRC_REG,Error Injection Control 0 (CRC Error). Controls the insertion of errors into the CRC. and parity of ordered sets for the selected type of the packets as follows: - LCRC. Bad TLP will be detected at the receiver side; receiver responds with.." hexmask.long.tbyte 0x4 12.--31. 1. "RSVDP_12,Reserved for future use." newline hexmask.long.byte 0x4 8.--11. 1. "EINJ0_CRC_TYPE,Error injection type. Selects the type of CRC error to be inserted. Tx Path - 0000b: New TLP's LCRC error injection - 0001b: 16bCRC error injection of ACK/NAK DLLP - 0010b: 16bCRC error injection of Update-FC DLLP - 0011b: New TLP's ECRC.." newline hexmask.long.byte 0x4 0.--7. 1. "EINJ0_COUNT,Error injection count. Indicates the number of errors. This register is decremented when the errors have been inserted. - If the counter value is 0x01 and error is inserted ERROR_INJECTION0_ENABLE in EINJ_ENABLE_REG returns 0b. - If the.." line.long 0x8 "EINJ1_SEQNUM_REG,Error Injection Control 1 (Sequence Number Error). Controls the sequence number of the specific TLPs and ACK/NAK DLLPs. Data Link Protocol Error will be detected at the Rx side of ACK/NAL DLLPs when one of these conditions is true: -.." rbitfld.long 0x8 29.--31. "RSVDP_29,Reserved for future use." "0,1,2,3,4,5,6,7" newline hexmask.long.word 0x8 16.--28. 1. "EINJ1_BAD_SEQNUM,Bad sequence number. Indicates the value to add/subtract from the naturally-assigned sequence numbers. This value is represented by two's complement. - 0x0FFF: +4095 - .. - 0x0002: +2 - 0x0001: +1 - 0x0000: 0 - 0x1FFF: -1 - 0x1FFE: -2 -.." newline hexmask.long.byte 0x8 9.--15. 1. "RSVDP_9,Reserved for future use." newline bitfld.long 0x8 8. "EINJ1_SEQNUM_TYPE,Sequence number type. Selects the type of sequence number. - 0b: Insertion of New TLP's SEQ# error - 1b: Insertion of ACK/NAK DLLP's SEQ# Error Note: This register field is sticky." "0,1" newline hexmask.long.byte 0x8 0.--7. 1. "EINJ1_COUNT,Error injection count. Indicates the number of errors. This register is decremented as the errors are being inserted. - If the counter value is 0x01 and error is inserted ERROR_INJECTION1_ENABLE in EINJ_ENABLE_REG returns '0'. - If the.." line.long 0xC "EINJ2_DLLP_REG,Error Injection Control 2 (DLLP Error). Controls the transmission of DLLPs and inserts the following errors: - If 'ACK/NAK DLLP's transmission block' is selected. replay timeout error will occur at the transmitter of the TLPs and then Data.." hexmask.long.tbyte 0xC 10.--31. 1. "RSVDP_10,Reserved for future use." newline bitfld.long 0xC 8.--9. "EINJ2_DLLP_TYPE,DLLP Type. Selects the type of DLLP errors to be inserted. - 00b: ACK/NAK DLLP's transmission block - 01b: Update FC DLLP's transmission block - 10b: Always Transmission for NAK DLLP - 11b: Reserved Note: This register field is sticky." "0,1,2,3" newline hexmask.long.byte 0xC 0.--7. 1. "EINJ2_COUNT,Error injection count. Indicates the number of errors. This register is decremented as the errors are being inserted. - If the counter value is 0x01 and the error is inserted ERROR_INJECTION2_ENABLE in EINJ_ENABLE_REG returns '0'. - If the.." line.long 0x10 "EINJ3_SYMBOL_REG,Error Injection Control 3 (Symbol Error). When 8b/10b encoding is used. this register controls error insertion into the special (K code) symbols. - If TS1/TS2/FTS/E-Idle/SKP is selected. it affects whole of the ordered set. It might.." hexmask.long.tbyte 0x10 11.--31. 1. "RSVDP_11,Reserved for future use." newline bitfld.long 0x10 8.--10. "EINJ3_SYMBOL_TYPE,Error Type. 8b/10b encoding - Mask K symbol. It is not supported to insert errors into the first ordered-set after exiting from TxElecIdle when CX_FREQ_STEP_EN has been enabled. - 000b: Reserved - 001b: COM/PAD(TS1 Order set) - 010b:.." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x10 0.--7. 1. "EINJ3_COUNT,Error injection count. Indicates the number of errors. This register is decremented as the errors are being inserted. - If the counter value is 0x01 and error is inserted ERROR_INJECTION3_ENABLE in EINJ_ENABLE_REG returns '0'. - If the.." line.long 0x14 "EINJ4_FC_REG,Error Injection Control 4 (FC Credit Error). Controls error insertion into the credit value in the UpdateFCs. It is possible to insert errors for any of the following types: - Posted TLP Header credit - Non-Posted TLP Header credit -.." rbitfld.long 0x14 29.--31. "RSVDP_29,Reserved for future use." "0,1,2,3,4,5,6,7" newline hexmask.long.word 0x14 16.--28. 1. "EINJ4_BAD_UPDFC_VALUE,Bad update-FC credit value. Indicates the value to add/subtract from the UpdateFC credit. This value is represented by two's complement. - 0x0FFF: +4095 - .. - 0x0002: +2 - 0x0001: +1 - 0x0000: 0 - 0x1FFF: -1 - 0x1FFE: -2 - .. -.." newline rbitfld.long 0x14 15. "RSVDP_15,Reserved for future use." "0,1" newline bitfld.long 0x14 12.--14. "EINJ4_VC_NUMBER,VC Number. Indicates target VC Number. Note: This register field is sticky." "0,1,2,3,4,5,6,7" newline rbitfld.long 0x14 11. "RSVDP_11,Reserved for future use." "0,1" newline bitfld.long 0x14 8.--10. "EINJ4_UPDFC_TYPE,Update-FC type. Selects the credit type. - 000b: Posted TLP Header Credit value control - 001b: Non-Posted TLP Header Credit value control - 010b: Completion TLP Header Credit value control - 011b: Reserved - 100b: Posted TLP Data Credit.." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x14 0.--7. 1. "EINJ4_COUNT,Error injection count. Indicates the number of errors. This register is decremented as the errors are being inserted. - If the counter value is 0x01 and error is inserted ERROR_INJECTION4_ENABLE in EINJ_ENABLE_REG returns '0'. - If the.." line.long 0x18 "EINJ5_SP_TLP_REG,Error Injection Control 5 (Specific TLP Error). Controls the generation of specified TLPs. Correctable errors will occur which will be fixed by the PCIe protocol. - For Duplicate TLP. the controller initiates Data Link Retry by handling.." hexmask.long.tbyte 0x18 9.--31. 1. "RSVDP_9,Reserved for future use." newline bitfld.long 0x18 8. "EINJ5_SPECIFIED_TLP,Specified TLP. Selects the specified TLP to be inserted. - 0: Generates duplicate TLPs by handling ACK DLLP as NAK DLLP. - 1: Generates Nullified TLP (Original TLP will be stored in retry buffer). Note: This register field is sticky." "Generates duplicate TLPs by handling ACK DLLP as..,Generates Nullified TLP" newline hexmask.long.byte 0x18 0.--7. 1. "EINJ5_COUNT,Error injection count. Indicates the number of errors. This register is decremented as the errors are being inserted. - If the counter value is 0x01 and error is inserted ERROR_INJECTION5_ENABLE in EINJ_ENABLE_REG returns '0'. - If the.." line.long 0x1C "EINJ6_COMPARE_POINT_H0_REG,Error Injection Control 6 (Compare Point Header DWORD #0). Program this register for the 1st DWORD of TLP header/prefix. It is necessary to carefully consider the endianness when you program this register. Bits [31:0] =.." hexmask.long 0x1C 0.--31. 1. "EINJ6_COMPARE_POINT_H0,Packet Compare Point: 1st DWORD. Specifies which Tx TLP header DWORD#0 bits to compare with the corresponding bits in the Packet Compare Value registers (EINJ6_COMPARE_VALUE*). When all specified bits (in the Tx TLP header and.." line.long 0x20 "EINJ6_COMPARE_POINT_H1_REG,Error Injection Control 6 (Compare Point Header DWORD #1). Program this register for the 2nd DWORD of TLP header/prefix. It is necessary to carefully consider the endianness when you program this register. Bits [31:0] =.." hexmask.long 0x20 0.--31. 1. "EINJ6_COMPARE_POINT_H1,Packet Compare Point: 2nd DWORD. Specifies which Tx TLP header DWORD#1 bits to compare with the corresponding bits in the Packet Compare Value registers (EINJ6_COMPARE_VALUE*). When all specified bits (in the Tx TLP header and.." line.long 0x24 "EINJ6_COMPARE_POINT_H2_REG,Error Injection Control 6 (Compare Point Header DWORD #2). Program this register for the 3rd DWORD of TLP header/prefix. It is necessary to carefully consider the endianness when you program this register. Bits [31:0] =.." hexmask.long 0x24 0.--31. 1. "EINJ6_COMPARE_POINT_H2,Packet Compare Point: 3rd DWORD. Specifies which Tx TLP header DWORD#2 bits to compare with the corresponding bits in the Packet Compare Value registers (EINJ6_COMPARE_VALUE*). When all specified bits (in the Tx TLP header and.." line.long 0x28 "EINJ6_COMPARE_POINT_H3_REG,Error Injection Control 6 (Compare Point Header DWORD #3). Program this register for the 4th DWORD of TLP header/prefix. It is necessary to carefully consider the endianness when you program this register. Bits [31:0] =.." hexmask.long 0x28 0.--31. 1. "EINJ6_COMPARE_POINT_H3,Packet Compare Point: 4th DWORD. Specifies which Tx TLP header DWORD#3 bits to compare with the corresponding bits in the Packet Compare Value registers (EINJ6_COMPARE_VALUE*). When all specified bits (in the Tx TLP header and.." line.long 0x2C "EINJ6_COMPARE_VALUE_H0_REG,Error Injection Control 6 (Compare Value Header DWORD #0). Program this register for the 1st DWORD of TLP header/prefix. It is necessary to carefully consider the endianness when you program this register. Bits [31:0] =.." hexmask.long 0x2C 0.--31. 1. "EINJ6_COMPARE_VALUE_H0,Packet Compare Value: 1st DWORD. Specifies the value to compare against Tx the TLP header DWORD#0 bits specified in the Packet Compare Point registers (EINJ6_COMPARE_POINT*). Note: This register field is sticky." line.long 0x30 "EINJ6_COMPARE_VALUE_H1_REG,Error Injection Control 6 (Compare Value Header DWORD #1). Program this register for the 2nd DWORD of TLP header/prefix. It is necessary to carefully consider the endianness when you program this register. Bits [31:0] =.." hexmask.long 0x30 0.--31. 1. "EINJ6_COMPARE_VALUE_H1,Packet Compare Value: 2nd DWORD. Specifies the value to compare against Tx the TLP header DWORD#1 bits specified in the Packet Compare Point registers (EINJ6_COMPARE_POINT*). Note: This register field is sticky." line.long 0x34 "EINJ6_COMPARE_VALUE_H2_REG,Error Injection Control 6 (Compare Value Header DWORD #2). Program this register for the 3rd DWORD of TLP header/prefix. It is necessary to carefully consider the endianness when you program this register. Bits [31:0] =.." hexmask.long 0x34 0.--31. 1. "EINJ6_COMPARE_VALUE_H2,Packet Compare Value: 3rd DWORD. Specifies the value to compare against Tx the TLP header DWORD#2 bits specified in the Packet Compare Point registers (EINJ6_COMPARE_POINT*). Note: This register field is sticky." line.long 0x38 "EINJ6_COMPARE_VALUE_H3_REG,Error Injection Control 6 (Compare Value Header DWORD #3). Program this register for the 4th DWORD of TLP header/prefix. It is necessary to carefully consider the endianness when you program this register. Bits [31:0] =.." hexmask.long 0x38 0.--31. 1. "EINJ6_COMPARE_VALUE_H3,Packet Compare Value: 4th DWORD. Specifies the value to compare against Tx the TLP header DWORD#3 bits specified in the Packet Compare Point registers (EINJ6_COMPARE_POINT*). Note: This register field is sticky." line.long 0x3C "EINJ6_CHANGE_POINT_H0_REG,Error Injection Control 6 (Change Point Header DWORD #0). Program this register for the 1st DWORD of TLP header/prefix. It is necessary to carefully consider the endianness when you program this register. Bits [31:0] =.." hexmask.long 0x3C 0.--31. 1. "EINJ6_CHANGE_POINT_H0,Packet Change Point: 1st DWORD. Specifies which Tx TLP header DWORD#0 bits to replace with the corresponding bits in the Packet Change Value registers (EINJ6_CHANGE_VALUE*). Note: This register field is sticky." line.long 0x40 "EINJ6_CHANGE_POINT_H1_REG,Error Injection Control 6 (Change Point Header DWORD #1). Program this register for the 2nd DWORD of TLP header/prefix. It is necessary to carefully consider the endianness when you program this register. Bits [31:0] =.." hexmask.long 0x40 0.--31. 1. "EINJ6_CHANGE_POINT_H1,Packet Change Point: 2nd DWORD. Specifies which Tx TLP header DWORD#1 bits to replace with the corresponding bits in the Packet Change Value registers (EINJ6_CHANGE_VALUE*). Note: This register field is sticky." line.long 0x44 "EINJ6_CHANGE_POINT_H2_REG,Error Injection Control 6 (Change Point Header DWORD #2). Program this register for the 3rd DWORD of TLP header/prefix. It is necessary to carefully consider the endianness when you program this register. Bits [31:0] =.." hexmask.long 0x44 0.--31. 1. "EINJ6_CHANGE_POINT_H2,Packet Change Point: 3rd DWORD. Specifies which Tx TLP header DWORD#2 bits to replace with the corresponding bits in the Packet Change Value registers (EINJ6_CHANGE_VALUE*). Note: This register field is sticky." line.long 0x48 "EINJ6_CHANGE_POINT_H3_REG,Error Injection Control 6 (Change Point Header DWORD #3). Program this register for the 4th DWORD of TLP header/prefix. It is necessary to carefully consider the endianness when you program this register. Bits [31:0] =.." hexmask.long 0x48 0.--31. 1. "EINJ6_CHANGE_POINT_H3,Packet Change Point: 4th DWORD. Specifies which Tx TLP header DWORD#3 bits to replace with the corresponding bits in the Packet Change Value registers (EINJ6_CHANGE_VALUE*). Note: This register field is sticky." line.long 0x4C "EINJ6_CHANGE_VALUE_H0_REG,Error Injection Control 6 (Change Value Header DWORD #0). Program this register for the 1st DWORD of TLP header/prefix. It is necessary to carefully consider the endianness when you program this register. Bits [31:0] =.." hexmask.long 0x4C 0.--31. 1. "EINJ6_CHANGE_VALUE_H0,Packet Change Value: 1st DWORD. Specifies replacement values for the Tx TLP header DWORD#0 bits defined in the Packet Change Point registers (EINJ6_CHANGE_POINT*). Only applies when the EINJ6_INVERTED_CONTROL field in EINJ6_TLP_REG.." line.long 0x50 "EINJ6_CHANGE_VALUE_H1_REG,Error Injection Control 6 (Change Value Header DWORD #1). Program this register for the 2nd DWORD of TLP header/prefix. It is necessary to carefully consider the endianness when you program this register. Bits [31:0] =.." hexmask.long 0x50 0.--31. 1. "EINJ6_CHANGE_VALUE_H1,Packet Change Value: 2nd DWORD. Specifies replacement values for the Tx TLP header DWORD#1 bits defined in the Packet Change Point registers (EINJ6_CHANGE_POINT*). Only applies when the EINJ6_INVERTED_CONTROL field in EINJ6_TLP_REG.." line.long 0x54 "EINJ6_CHANGE_VALUE_H2_REG,Error Injection Control 6 (Change Value Header DWORD #2). Program this register for the 3rd DWORD of TLP header/prefix. It is necessary to carefully consider the endianness when you program this register. Bits [31:0] =.." hexmask.long 0x54 0.--31. 1. "EINJ6_CHANGE_VALUE_H2,Packet Change Value: 3rd DWORD. Specifies replacement values for the Tx TLP header DWORD#2 bits defined in the Packet Change Point registers (EINJ6_CHANGE_POINT*). Only applies when the EINJ6_INVERTED_CONTROL field in EINJ6_TLP_REG.." line.long 0x58 "EINJ6_CHANGE_VALUE_H3_REG,Error Injection Control 6 (Change Value Header DWORD #3). Program this register for the 4th DWORD of TLP header/prefix. It is necessary to carefully consider the endianness when you program this register. Bits [31:0] =.." hexmask.long 0x58 0.--31. 1. "EINJ6_CHANGE_VALUE_H3,Packet Change Value: 4th DWORD. Specifies replacement values for the Tx TLP header DWORD#3 bits defined in the Packet Change Point registers (EINJ6_CHANGE_POINT*). Only applies when the EINJ6_INVERTED_CONTROL field in EINJ6_TLP_REG.." line.long 0x5C "EINJ6_TLP_REG,Error Injection Control 6 (Packet Error). The Packet Compare Point registers (EINJ6_COMPARE_POINT*) specify which Tx TLP header bits to compare with the corresponding bits in the Packet Compare Value registers (EINJ6_COMPARE_VALUE*). When.." hexmask.long.tbyte 0x5C 12.--31. 1. "RSVDP_12,Reserved for future use." newline bitfld.long 0x5C 9.--11. "EINJ6_PACKET_TYPE,Packet type. Selects the TLP packets to inject errors into. - 0: TLP Header - 1: TLP Prefix 1st 4-DWORDs - 2: TLP Prefix 2nd -DWORDs - Else: Reserved Note: This register field is sticky." "TLP Header,TLP Prefix 1st 4-DWORDs,TLP Prefix 2nd -DWORDs,?,?,?,?,?" newline bitfld.long 0x5C 8. "EINJ6_INVERTED_CONTROL,Inverted Error Injection Control. - 0: EINJ6_CHANGE_VALUE_H[0/1/2/3] is used to replace bits specified by EINJ6_CHANGE_POINT_H[0/1/2/3]. - 1: EINJ6_CHANGE_VALUE_H[0/1/2/3] is ignored and inverts bits specified by.." "EINJ6_CHANGE_VALUE_H[0/1/2/3] is used to replace..,EINJ6_CHANGE_VALUE_H[0/1/2/3] is ignored and.." newline hexmask.long.byte 0x5C 0.--7. 1. "EINJ6_COUNT,Error Injection Count. Indicates the number of errors to insert. This counter is decremented while errors are been inserted. - If the counter value is 0x01 and error is inserted ERROR_INJECTION6_ENABLE in EINJ_ENABLE_REG returns '0'. - If.." group.long (0xA0+0x30C)++0x7 line.long 0x0 "SD_CONTROL1_REG,Silicon Debug Control 1. For more details. see the RAS DES section in the Core Operations chapter of the Databook." hexmask.long.byte 0x0 24.--31. 1. "RSVDP_24,Reserved for future use." newline bitfld.long 0x0 22.--23. "LOW_POWER_INTERVAL,Low Power Entry Interval Time. Interval Time that the controller starts monitoring RXELECIDLE signal after L0s/L1/L2 entry. You should set the value according to the latency from receiving EIOS to RXELECIDLE assertion at the PHY. -.." "0,1,2,3" newline bitfld.long 0x0 20.--21. "TX_EIOS_NUM,Number of Tx EIOS. This register sets the number of transmit EIOS for L0s/L1 entry and Disable/Loopback/Hot-reset exit. The controller selects the greater value between this register and the value defined by the PCI-SIG specification. 2.5GT/s.." "0,1,2,3" newline rbitfld.long 0x0 17.--19. "RSVDP_17,Reserved for future use." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 16. "FORCE_DETECT_LANE_EN,Force Detect Lane Enable. When this bit is set the controller ignores receiver detection from PHY during LTSSM Detect state and uses FORCE_DETECT_LANE. Note: This register field is sticky." "0,1" newline hexmask.long.word 0x0 0.--15. 1. "FORCE_DETECT_LANE,Force Detect Lane. When the FORCE_DETECT_LANE_EN field is set the controller ignores receiver detection from PHY during LTSSM Detect state and uses this value instead. - 0: Lane0 - 1: Lane1 - 2: Lane2 - .. - 15: Lane15 Note: This.." line.long 0x4 "SD_CONTROL2_REG,Silicon Debug Control 2. For more details. see the RAS DES section in the Core Operations chapter of the Databook." hexmask.long.word 0x4 17.--31. 1. "RSVDP_17,Reserved for future use." newline bitfld.long 0x4 16. "FRAMING_ERR_RECOVERY_DISABLE,Framing Error Recovery Disable. This bit disables a transition to Recovery state when a Framing Error is occurred. Note: This register field is sticky." "0,1" newline hexmask.long.byte 0x4 11.--15. 1. "RSVDP_11,Reserved for future use." newline bitfld.long 0x4 10. "DIRECT_LPBKSLV_TO_EXIT,Direct Loopback Slave To Exit. When this bit is set and the LTSSM is in Loopback Slave Active State the LTSSM transitions to Loopback Slave Exit state. Note: This register field is sticky." "0,1" newline bitfld.long 0x4 9. "DIRECT_POLCOMP_TO_DETECT,Direct Polling.Compliance to Detect. When this bit is set and the LTSSM is in Polling Compliance State the LTSSM transitions to Detect state. Note: This register field is sticky." "0,1" newline bitfld.long 0x4 8. "DIRECT_RECIDLE_TO_CONFIG,Direct Recovery.Idle to Configuration. When this bit is set and the LTSSM is in Recovery Idle State the LTSSM transitions to Configuration state. Note: This register field is sticky." "0,1" newline hexmask.long.byte 0x4 3.--7. 1. "RSVDP_3,Reserved for future use." newline bitfld.long 0x4 2. "NOACK_FORCE_LINKDOWN,Force LinkDown. When this bit is set and the controller detects REPLY_NUM rolling over 4 times the LTSSM transitions to Detect State. Note: This register field is sticky." "0,1" newline bitfld.long 0x4 1. "RECOVERY_REQUEST,Recovery Request. When this bit is set to '1' in L0 or L0s the LTSSM starts transitioning to Recovery State. This request does not cause a speed change or re-equalization." "0,1" newline bitfld.long 0x4 0. "HOLD_LTSSM,Hold and Release LTSSM. For as long as this register is '1' the controller stays in the current LTSSM. Note: This register field is sticky." "0,1" group.long (0xB0+0x30C)++0xB line.long 0x0 "SD_STATUS_L1LANE_REG,Silicon Debug Status(Layer1 Per-lane). This viewport register returns the data selected by the following field: - LANE_SELECT in SD_STATUS_L1LANE_REG For more details. see the RAS DES section in the Core Operations chapter of the.." hexmask.long.byte 0x0 24.--31. 1. "DESKEW_POINTER,Deskew Pointer. Indicates Deskew pointer of internal Deskew buffer of selected lane number(LANE_SELECT). Note: This register field is sticky." newline rbitfld.long 0x0 21.--23. "RSVDP_21,Reserved for future use." "0,1,2,3,4,5,6,7" newline rbitfld.long 0x0 20. "PIPE_TXELECIDLE,PIPE:TxElecIdle. Indicates PIPE TXELECIDLE signal of selected lane number(LANE_SELECT). Note: This register field is sticky." "0,1" newline rbitfld.long 0x0 19. "PIPE_RXELECIDLE,PIPE:RxElecIdle. Indicates PIPE RXELECIDLE signal of selected lane number(LANE_SELECT). Note: This register field is sticky." "0,1" newline rbitfld.long 0x0 18. "PIPE_RXVALID,PIPE:RxValid. Indicates PIPE RXVALID signal of selected lane number(LANE_SELECT). Note: This register field is sticky." "0,1" newline rbitfld.long 0x0 17. "PIPE_DETECT_LANE,PIPE:Detect Lane. Indicates whether PHY indicates receiver detection or not on selected lane number(LANE_SELECT). Note: This register field is sticky." "0,1" newline rbitfld.long 0x0 16. "PIPE_RXPOLARITY,PIPE:RxPolarity. Indicates PIPE RXPOLARITY signal of selected lane number(LANE_SELECT). Note: This register field is sticky." "0,1" newline hexmask.long.word 0x0 4.--15. 1. "RSVDP_4,Reserved for future use." newline hexmask.long.byte 0x0 0.--3. 1. "LANE_SELECT,Lane Select. Lane Select register for Silicon Debug Status Register of Layer1-PerLane. - 0x0: Lane0 - 0x1: Lane1 - 0x2: Lane2 - .. - 0xF: Lane15 Note: This register field is sticky." line.long 0x4 "SD_STATUS_L1LTSSM_REG,Silicon Debug Status(Layer1 LTSSM). For more details. see the RAS DES section in the Core Operations chapter of the Databook." hexmask.long.word 0x4 16.--31. 1. "LTSSM_VARIABLE,LTSSM Variable. Indicates internal LTSSM variables defined in the PCI Express Base Specification. C-PCIe Mode: - 0: directed_speed_change - 1: changed_speed_recovery - 2: successful_speed_negotiation - 3: upconfigure_capable; Set to '1' if.." newline rbitfld.long 0x4 15. "LANE_REVERSAL,Lane Reversal Operation. Receiver detected lane reversal. This field is only valid in the L0 LTSSM state. Note: This register field is sticky." "0,1" newline hexmask.long.byte 0x4 11.--14. 1. "RSVDP_11,Reserved for future use." newline rbitfld.long 0x4 8.--10. "PIPE_POWER_DOWN,PIPE:PowerDown. Indicates PIPE PowerDown signal. Note: This register field is sticky." "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 7. "FRAMING_ERR,Framing Error. Indicates Framing Error detection status." "0,1" newline hexmask.long.byte 0x4 0.--6. 1. "FRAMING_ERR_PTR,First Framing Error Pointer. Identifies the first Framing Error using the following encoding. The field contents are only valid value when FRAMING_ERR =1. Received Unexpected Framing Token - 01h: When non- STP/SDP/IDL Token was received.." line.long 0x8 "SD_STATUS_PM_REG,Silicon Debug Status(PM). For more details. see the RAS DES section in the Core Operations chapter of the Databook." hexmask.long.byte 0x8 24.--31. 1. "RSVDP_24,Reserved for future use." newline hexmask.long.byte 0x8 16.--23. 1. "LATCHED_NFTS,Latched N_FTS. Indicates the value of N_FTS in the received TS Ordered Sets from the Link Partner Note: This register field is sticky." newline rbitfld.long 0x8 13.--15. "L1SUB_STATE,L1Sub State. Indicates internal state machine of L1Sub state. - 0h: S_L1_U : idle state - 1h: S_L1_0 : wait for aux_clk_active - 2h: S_L1_0_WAIT4_ACK : wait for pclkack - 3h: S_L1_0_WAIT4_CLKREQ : wait for clkreq - 4h: S_L1_N_ENTRY : check.." "wait for aux_clk_active,?,?,?,?,?,?,?" newline bitfld.long 0x8 12. "PME_RESEND_FLAG,PME Re-send flag. When the DUT sends a PM_PME message TLP the DUT sets PME_Status bit. If host software does not clear PME_Status bit for 100ms(+50%/-5%) the DUT resends the PM_PME Message. This bit indicates that a PM_PME was resent." "0,1" newline hexmask.long.byte 0x8 8.--11. 1. "INTERNAL_PM_SSTATE,Internal PM State(Slave). Indicates internal state machine of Power Management Slave controller. - 0h: S_IDLE - 1h: S_RESPOND_NAK - 2h: S_BLOCK_TLP - 3h: S_WAIT_LAST_TLP_ACK - 4h: S_WAIT_EIDLE - 5h: S_LINK_ENTR_L1 - 6h: S_L1 - 7h:.." newline rbitfld.long 0x8 5.--7. "RSVDP_5,Reserved for future use." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x8 0.--4. 1. "INTERNAL_PM_MSTATE,Internal PM State(Master). Indicates internal state machine of Power Management Master controller. - 00h: IDLE - 01h: L0 - 02h: L0S - 03h: ENTER_L0S - 04h: L0S_EXIT - 05h: WAIT_PMCSR_CPL_SENT - 08h: L1 - 09h: L1_BLOCK_TLP - 0Ah:.." rgroup.long (0xBC+0x30C)++0x3 line.long 0x0 "SD_STATUS_L2_REG,Silicon Debug Status(Layer2). For more details. see the RAS DES section in the Core Operations chapter of the Databook." hexmask.long.byte 0x0 28.--31. 1. "RSVDP_28,Reserved for future use." newline bitfld.long 0x0 27. "FC_INIT2,FC_INIT2. Indicates the controller is in FC_INIT2(VC0) state. Note: This register field is sticky." "0,1" newline bitfld.long 0x0 26. "FC_INIT1,FC_INIT1. Indicates the controller is in FC_INIT1(VC0) state. Note: This register field is sticky." "0,1" newline bitfld.long 0x0 24.--25. "DLCMSM,DLCMSM. Indicates the current DLCMSM. - 00b: DL_INACTIVE - 01b: DL_FC_INIT - 11b: DL_ACTIVE Note: This register field is sticky." "0,1,2,3" newline hexmask.long.word 0x0 12.--23. 1. "RX_ACK_SEQ_NO,Tx Ack Sequence Number. Indicates ACKD_SEQ which is updated by receiving ACK/NAK DLLP. Note: This register field is sticky." newline hexmask.long.word 0x0 0.--11. 1. "TX_TLP_SEQ_NO,Tx Tlp Sequence Number. Indicates next transmit sequence number for transmit TLP. Note: This register field is sticky." group.long (0xC0+0x30C)++0x7 line.long 0x0 "SD_STATUS_L3FC_REG,Silicon Debug Status(Layer3 FC). The CREDIT_DATA[0/1] fields in this viewport register return the data for the VC and TLP Type selected by the following fields: - CREDIT_SEL_VC - CREDIT_SEL_CREDIT_TYPE - CREDIT_SEL_TLP_TYPE -.." hexmask.long.word 0x0 20.--31. 1. "CREDIT_DATA1,Credit Data1. Current FC credit data selected by the CREDIT_SEL_VC CREDIT_SEL_CREDIT_TYPE CREDIT_SEL_TLP_TYPE and CREDIT_SEL_HD viewport-select fields. - Rx: Credit Allocated Value - Tx: Credit Limit Value. This value is valid when.." newline hexmask.long.word 0x0 8.--19. 1. "CREDIT_DATA0,Credit Data0. Current FC credit data selected by the CREDIT_SEL_VC CREDIT_SEL_CREDIT_TYPE CREDIT_SEL_TLP_TYPE and CREDIT_SEL_HD viewport-select fields. - Rx: Credit Received Value - Tx: Credit Consumed Value Note: This register field is.." newline rbitfld.long 0x0 7. "RSVDP_7,Reserved for future use." "0,1" newline bitfld.long 0x0 6. "CREDIT_SEL_HD,Credit Select(HeaderData). This field in conjunction with the CREDIT_SEL_VC CREDIT_SEL_CREDIT_TYPE and CREDIT_SEL_TLP_TYPE viewport-select fields determines that data that is returned by the CREDIT_DATA0 and CREDIT_DATA1 data fields. -.." "Header Credit,Data Credit" newline bitfld.long 0x0 4.--5. "CREDIT_SEL_TLP_TYPE,Credit Select(TLP Type). This field in conjunction with the CREDIT_SEL_VC CREDIT_SEL_CREDIT_TYPE and CREDIT_SEL_HD viewport-select fields determines that data that is returned by the CREDIT_DATA0 and CREDIT_DATA1 data fields. - 0x0:.." "Posted,Non-Posted,Completion,?" newline bitfld.long 0x0 3. "CREDIT_SEL_CREDIT_TYPE,Credit Select(Credit Type). This field in conjunction with the CREDIT_SEL_VC CREDIT_SEL_TLP_TYPE and CREDIT_SEL_HD viewport-select fields determines that data that is returned by the CREDIT_DATA0 and CREDIT_DATA1 data fields. -.." "Rx,Tx" newline bitfld.long 0x0 0.--2. "CREDIT_SEL_VC,Credit Select(VC). This field in conjunction with the CREDIT_SEL_CREDIT_TYPE CREDIT_SEL_TLP_TYPE and CREDIT_SEL_HD viewport-select fields determines that data that is returned by the CREDIT_DATA0 and CREDIT_DATA1 data fields. - 0x0: VC0 -.." "VC0,VC1,VC2,?,?,?,?,VC7" line.long 0x4 "SD_STATUS_L3_REG,Silicon Debug Status(Layer3). For more details. see the RAS DES section in the Core Operations chapter of the Databook." hexmask.long.tbyte 0x4 8.--31. 1. "RSVDP_8,Reserved for future use." newline bitfld.long 0x4 7. "MFTLP_STATUS,Malformed TLP Status. Indicates malformed TLP has occurred." "0,1" newline hexmask.long.byte 0x4 0.--6. 1. "MFTLP_POINTER,First Malformed TLP Error Pointer. Indicates the element of the received first malformed TLP. This pointer is validated by MFTLP_STATUS. - 01h: AtomicOp address alignment - 02h: AtomicOp operand - 03h: AtomicOp byte enable - 04h: TLP length.." group.long (0xD0+0x30C)++0xB line.long 0x0 "SD_EQ_CONTROL1_REG,Silicon Debug EQ Control 1. This is a viewport control register. Setting the EQ_RATE_SEL and EQ_LANE_SEL fields in this register determine the per-lane Silicon Debug EQ Status data returned by the SD_EQ_STATUS[1/2/3] viewport.." hexmask.long.byte 0x0 24.--31. 1. "FOM_TARGET,FOM Target. Indicates figure of merit target criteria value of EQ Master(DSP in EQ Phase3/USP in EQ Phase2). This field is only valid when GEN3_EQ_FB_MODE is 0001b(Figure Of Merit). Note: This register field is sticky." newline bitfld.long 0x0 23. "FOM_TARGET_ENABLE,FOM Target Enable. Enables the FOM_TARGET fields. Note: This register field is sticky." "0,1" newline hexmask.long.byte 0x0 18.--22. 1. "RSVDP_18,Reserved for future use." newline bitfld.long 0x0 16.--17. "EVAL_INTERVAL_TIME,Eval Interval Time. Indicates interval time of RxEqEval assertion. - 00: 500ns - 01: 1us - 10: 2us - 11: 4us This field is used for EQ Master(DSP in EQ Phase3/USP in EQ Phase2). Note: This register field is sticky." "0,1,2,3" newline hexmask.long.byte 0x0 10.--15. 1. "RSVDP_10,Reserved for future use." newline bitfld.long 0x0 8.--9. "EXT_EQ_TIMEOUT,Extends EQ Phase2/3 Timeout. This field is used when the Ltssm is in Recovery.EQ2/3. When this field is set the value of EQ2/3 timeout is extended. EQ Master(DSP in EQ Phase3/USP in EQ Phase2). - 00: 24ms (default) - 01: 48ms (x2) - 10:.." "0,1,2,3" newline rbitfld.long 0x0 6.--7. "RSVDP_6,Reserved for future use." "0,1,2,3" newline bitfld.long 0x0 4.--5. "EQ_RATE_SEL,EQ Status Rate Select. Setting this field in conjunction with the EQ_LANE_SEL field determines the per-lane Silicon Debug EQ Status data returned by the SD_EQ_CONTROL[2/3] and SD_EQ_STATUS[1/2/3] viewport registers. - 0x0: 8.0GT/s Speed.." "0,1,2,3" newline hexmask.long.byte 0x0 0.--3. 1. "EQ_LANE_SEL,EQ Status Lane Select. Setting this field in conjunction with the EQ_RATE_SEL field determines the per-lane Silicon Debug EQ Status data returned by the SD_EQ_CONTROL[2/3] and SD_EQ_STATUS[1/2/3] viewport registers. - 0x0: Lane0 - 0x1: Lane1.." line.long 0x4 "SD_EQ_CONTROL2_REG,Silicon Debug EQ Control 2. This viewport register returns the value for the rate and lane selected by the EQ_RATE_SEL and EQ_LANE_SEL fields in the SD_EQ_CONTROL1_REG register. For more details. see the RAS DES section in the Core.." rbitfld.long 0x4 31. "RSVDP_31,Reserved for future use." "0,1" newline bitfld.long 0x4 30. "FORCE_LOCAL_TX_PRESET_ENABLE,Force Local Transmitter Preset Enable. Enables the FORCE_LOCAL_TX_PRESET field. If select rate in the EQ_RATE_SEL field is 32.0GT/s Speed this feature is not available. Note: This register field is sticky." "0,1" newline bitfld.long 0x4 29. "FORCE_LOCAL_RX_HINT_ENABLE,Force Local Receiver Preset Hint Enable. Enables the FORCE_LOCAL_RX_HINT field. If select rate in the EQ_RATE_SEL field is other than 8.0GT/s Speed this feature is not available. Note: This register field is sticky." "0,1" newline bitfld.long 0x4 28. "FORCE_LOCAL_TX_COEF_ENABLE,Force Local Transmitter Coefficient Enable. Enables the following fields: - FORCE_LOCAL_TX_PRE_CURSOR - FORCE_LOCAL_TX_CURSOR - FORCE_LOCAL_TX_POST_CURSOR Note: This register field is sticky." "0,1" newline hexmask.long.byte 0x4 24.--27. 1. "FORCE_LOCAL_TX_PRESET,Force Local Transmitter Preset. Indicates initial preset value of USP in EQ Slave(EQ Phase2) instead of receiving EQ TS2. If select rate in the EQ_RATE_SEL field is 32.0GT/s Speed this feature is not available. Note: This register.." newline rbitfld.long 0x4 21.--23. "RSVDP_21,Reserved for future use." "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 18.--20. "FORCE_LOCAL_RX_HINT,Force Local Receiver Preset Hint. Indicates the RxPresetHint value of EQ Slave(DSP in EQ Phase2/USP in EQ Phase3) instead of received or set value. If select rate in the EQ_RATE_SEL field is other than 8.0GT/s Speed this feature is.." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x4 12.--17. 1. "FORCE_LOCAL_TX_POST_CURSOR,Force Local Transmitter Post-Cursor. Indicates the coefficient value of EQ Slave(DSP in EQ Phase2/USP in EQ Phase3) instead of the value instructed from link partner. Note: This register field is sticky." newline hexmask.long.byte 0x4 6.--11. 1. "FORCE_LOCAL_TX_CURSOR,Force Local Transmitter Cursor. Indicates the coefficient value of EQ Slave(DSP in EQ Phase2/USP in EQ Phase3) instead of the value instructed from link partner. Note: This register field is sticky." newline hexmask.long.byte 0x4 0.--5. 1. "FORCE_LOCAL_TX_PRE_CURSOR,Force Local Transmitter Pre-cursor. Indicates the coefficient value of EQ Slave(DSP in EQ Phase2/USP in EQ Phase3) instead of the value instructed from link partner. Note: This register field is sticky." line.long 0x8 "SD_EQ_CONTROL3_REG,Silicon Debug EQ Control 3. This viewport register returns the value for the rate and lane selected by the EQ_RATE_SEL and EQ_LANE_SEL fields in the SD_EQ_CONTROL1_REG register. For more details. see the RAS DES section in the Core.." rbitfld.long 0x8 29.--31. "RSVDP_29,Reserved for future use." "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 28. "FORCE_REMOTE_TX_COEF_ENABLE,Force Remote Transmitter Coefficient Enable. Enables the following fields: - FORCE_REMOTE_TX_PRE_CURSOR - FORCE_REMOTE_TX_CURSOR - FORCE_REMOTE_TX_POST_CURSOR This function can only be used when GEN3_EQ_FB_MODE =.." "0,1" newline hexmask.long.word 0x8 18.--27. 1. "RSVDP_18,Reserved for future use." newline hexmask.long.byte 0x8 12.--17. 1. "FORCE_REMOTE_TX_POST_CURSOR,Force Remote Transmitter Post-Cursor. Indicates the coefficient value of EQ Master(DSP in EQ Phase3/USP in EQ Phase2) instead of the value instructed from local phy in dirchange mode. Note: This register field is sticky." newline hexmask.long.byte 0x8 6.--11. 1. "FORCE_REMOTE_TX_CURSOR,Force Remote Transmitter Cursor. Indicates the coefficient value of EQ Master(DSP in EQ Phase3/USP in EQ Phase2) instead of the value instructed from local phy in dirchange mode. Note: This register field is sticky." newline hexmask.long.byte 0x8 0.--5. 1. "FORCE_REMOTE_TX_PRE_CURSOR,Force Remote Transmitter Pre-Cursor. Indicates the coefficient value of EQ Master(DSP in EQ Phase3/USP in EQ Phase2) instead of the value instructed from local phy in dirchange mode. Note: This register field is sticky." rgroup.long (0xE0+0x30C)++0xB line.long 0x0 "SD_EQ_STATUS1_REG,Silicon Debug EQ Status 1. This viewport register returns the first of three words of Silicon Debug EQ Status data for the rate and lane selected by the EQ_RATE_SEL and EQ_LANE_SEL fields in the SD_EQ_CONTROL1_REG register. The.." hexmask.long.tbyte 0x0 8.--31. 1. "RSVDP_8,Reserved for future use." newline bitfld.long 0x0 7. "EQ_REJECT_EVENT,EQ Reject Event. Indicates that the controller receives two consecutive TS1 OS w/Reject=1b during EQ Master phase(DSP in EQ Phase3/USP in EQ Phase2). This bit is automatically cleared when the controller starts EQ Master phase again." "0,1" newline bitfld.long 0x0 6. "EQ_RULEC_VIOLATION,EQ Rule C Violation. Indicates that coefficients rule C violation is detected in the values provided by PHY using direction change method during EQ Master phase(DSP in EQ Phase3/USP in EQ Phase2). The coefficients rule C correspond to.." "0,1" newline bitfld.long 0x0 5. "EQ_RULEB_VIOLATION,EQ Rule B Violation. Indicates that coefficients rule B violation is detected in the values provided by PHY using direction change method during EQ Master phase(DSP in EQ Phase3/USP in EQ Phase2). The coefficients rules B correspond to.." "0,1" newline bitfld.long 0x0 4. "EQ_RULEA_VIOLATION,EQ Rule A Violation. Indicates that coefficients rule A violation is detected in the values provided by PHY using direction change method during EQ Master phase(DSP in EQ Phase3/USP in EQ Phase2). The coefficients rules A correspond to.." "0,1" newline bitfld.long 0x0 3. "RSVDP_3,Reserved for future use." "0,1" newline bitfld.long 0x0 1.--2. "EQ_CONVERGENCE_INFO,EQ Convergence Info. Indicates equalization convergence information. - 0x0: Equalization is not attempted - 0x1: Equalization finished successfully - 0x2: Equalization finished unsuccessfully - 0x3: Reserved This bit is automatically.." "Equalization is not attempted,Equalization finished successfully,Equalization finished unsuccessfully,Reserved" newline bitfld.long 0x0 0. "EQ_SEQUENCE,EQ Sequence. Indicates that the controller is starting the equalization sequence. Note: This register field is sticky." "0,1" line.long 0x4 "SD_EQ_STATUS2_REG,Silicon Debug EQ Status 2. This viewport register returns the second of three words of Silicon Debug EQ Status data for the rate and lane selected by the EQ_RATE_SEL and EQ_LANE_SEL fields in the SD_EQ_CONTROL1_REG register. Each field.." hexmask.long.byte 0x4 24.--31. 1. "EQ_LOCAL_FOM_VALUE,EQ Local Figure of Merit. Indicates Local maximum Figure of Merit value. Note: This register field is sticky." newline bitfld.long 0x4 21.--23. "RSVDP_21,Reserved for future use." "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 18.--20. "EQ_LOCAL_RX_HINT,EQ Local Receiver Preset Hint. Indicates Local Receiver Preset Hint value. If select rate in the EQ_RATE_SEL field is other than 8.0GT/s Speed this feature is not available. Note: This register field is sticky." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x4 12.--17. 1. "EQ_LOCAL_POST_CURSOR,EQ Local Post-Cursor. Indicates Local post cursor coefficient value. Note: This register field is sticky." newline hexmask.long.byte 0x4 6.--11. 1. "EQ_LOCAL_CURSOR,EQ Local Cursor. Indicates Local cursor coefficient value. Note: This register field is sticky." newline hexmask.long.byte 0x4 0.--5. 1. "EQ_LOCAL_PRE_CURSOR,EQ Local Pre-Cursor. Indicates Local pre cursor coefficient value. Note: This register field is sticky." line.long 0x8 "SD_EQ_STATUS3_REG,Silicon Debug EQ Status 3. This viewport register returns the third of three words of Silicon Debug EQ Status data for the rate and lane selected by the EQ_RATE_SEL and EQ_LANE_SEL fields in the SD_EQ_CONTROL1_REG register. Each field.." bitfld.long 0x8 30.--31. "RSVDP_30,Reserved for future use." "0,1,2,3" newline hexmask.long.byte 0x8 24.--29. 1. "EQ_REMOTE_FS,EQ Remote FS. Indicates Remote FS value. Note: This register field is sticky." newline hexmask.long.byte 0x8 18.--23. 1. "EQ_REMOTE_LF,EQ Remote LF. Indicates Remote LF value. Note: This register field is sticky." newline hexmask.long.byte 0x8 12.--17. 1. "EQ_REMOTE_POST_CURSOR,EQ Remote Post-Cursor. Indicates Remote post cursor coefficient value. Note: This register field is sticky." newline hexmask.long.byte 0x8 6.--11. 1. "EQ_REMOTE_CURSOR,EQ Remote Cursor. Indicates Remote cursor coefficient value. Note: This register field is sticky." newline hexmask.long.byte 0x8 0.--5. 1. "EQ_REMOTE_PRE_CURSOR,EQ Remote Pre-Cursor. Indicates Remote pre cursor coefficient value. Note: This register field is sticky." tree.end tree "PF0_SN_CAP (Device Serial Number Capability Structure)" group.long (0x0+0x170)++0xB line.long 0x0 "SN_BASE,Device Serial Number Extended Capability Header. For a description of this standard PCIe register. see the PCI Express Base Specification." hexmask.long.word 0x0 20.--31. 1. "SN_NEXT_OFFSET,Next Capability Offset. For a description of this standard PCIe register field see the PCI Express Base Specification. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then.." hexmask.long.byte 0x0 16.--19. 1. "SN_CAP_VERSION,Capability Version. For a description of this standard PCIe register field see the PCI Express Base Specification. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky).." hexmask.long.word 0x0 0.--15. 1. "SN_PCIE_EXTENDED_CAP_ID,Serial Number Extended Capability ID. For a description of this standard PCIe register field see the PCI Express Base Specification. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if.." line.long 0x4 "SER_NUM_REG_DW_1,Serial Number 1 Register. For a description of this standard PCIe register. see the PCI Express Base Specification." hexmask.long 0x4 0.--31. 1. "SN_SER_NUM_REG_1_DW,IEEE 64 bit Device Serial Number (DW 1). For a description of this standard PCIe register field see the PCI Express Base Specification. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if.." line.long 0x8 "SER_NUM_REG_DW_2,Serial Number 2 Register. For a description of this standard PCIe register. see the PCI Express Base Specification." hexmask.long 0x8 0.--31. 1. "SN_SER_NUM_REG_2_DW,IEEE 64 bit Device Serial Number (DW 2). For a description of this standard PCIe register field see the PCI Express Base Specification. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if.." tree.end tree "PF0_VSECRAS_CAP (PF RAS Datapath Protection Capability Structure (VSEC))" group.long (0x0+0x480)++0x3 line.long 0x0 "RASDP_EXT_CAP_HDR_OFF,PCIe Extended capability ID. Capability version and Next capability offset. For a description of this standard PCIe register. see the PCI Express Specification." hexmask.long.word 0x0 20.--31. 1. "NEXT_OFFSET,Next Capability Offset. For a description of this standard PCIe register see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else.." newline hexmask.long.byte 0x0 16.--19. 1. "CAP,Capability Version. For a description of this standard PCIe register see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note:.." newline hexmask.long.word 0x0 0.--15. 1. "ID,PCI Express Extended Capability ID. For a description of this standard PCIe register see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else.." rgroup.long (0x4+0x480)++0x3 line.long 0x0 "RASDP_VENDOR_SPECIFIC_HDR_OFF,Vendor Specific Header. For a description of this standard PCIe register. see the PCI Express Specification." hexmask.long.word 0x0 20.--31. 1. "VSEC_LENGTH,VSEC Length. For a description of this standard PCIe register see the PCI Express Specification. Note: This register field is sticky." newline hexmask.long.byte 0x0 16.--19. 1. "VSEC_REV,VSEC Rev. For a description of this standard PCIe register see the PCI Express Specification. Note: This register field is sticky." newline hexmask.long.word 0x0 0.--15. 1. "VSEC_ID,VSEC ID. For a description of this standard PCIe register see the PCI Express Specification. Note: This register field is sticky." group.long (0x8+0x480)++0x7 line.long 0x0 "RASDP_ERROR_PROT_CTRL_OFF,ECC error correction control. Allows you to disable ECC error correction for RAMs and datapath. When the AXI Bridge Module is implemented and the master / slave clocks are asynchronous to the PCIe native controller clock.." hexmask.long.byte 0x0 24.--31. 1. "RSVDP_24,Reserved for future use." newline bitfld.long 0x0 23. "ERROR_PROT_DISABLE_CXS_RX,Error correction disable for CXS Tx path (PCIe Rx path). Note: This register field is sticky." "0,1" newline bitfld.long 0x0 22. "ERROR_PROT_DISABLE_ADM_RX,Error correction disable for ADM Rx path. Note: This register field is sticky." "0,1" newline bitfld.long 0x0 21. "ERROR_PROT_DISABLE_LAYER3_RX,Error correction disable for layer 3 Rx path. Note: This register field is sticky." "0,1" newline bitfld.long 0x0 20. "ERROR_PROT_DISABLE_LAYER2_RX,Error correction disable for layer 2 Rx path. Note: This register field is sticky." "0,1" newline bitfld.long 0x0 19. "ERROR_PROT_DISABLE_DMA_READ,Error correction disable for DMA read engine. Note: This register field is sticky." "0,1" newline bitfld.long 0x0 18. "ERROR_PROT_DISABLE_AXI_BRIDGE_INBOUND_REQUEST,Error correction disable for AXI bridge inbound request path. Note: This register field is sticky." "0,1" newline bitfld.long 0x0 17. "ERROR_PROT_DISABLE_AXI_BRIDGE_INBOUND_COMPLETION,Error correction disable for AXI bridge inbound completion composer. Does not disable the error detection reporting for 1-bit and 2-bit ECC errors. Note: This register field is sticky." "?,bit and 2-bit ECC errors" newline bitfld.long 0x0 16. "ERROR_PROT_DISABLE_RX,Global error correction disable for all Rx layers. Note: This register field is sticky." "0,1" newline hexmask.long.byte 0x0 9.--15. 1. "RSVDP_9,Reserved for future use." newline bitfld.long 0x0 8. "ERROR_PROT_DISABLE_DTIM_TX,Error correction disable for DTIM Tx path. Note: This register field is sticky." "0,1" newline bitfld.long 0x0 7. "ERROR_PROT_DISABLE_CXS_TX,Error correction disable for CXS Rx path (PCIe Tx path). Note: This register field is sticky." "0,1" newline bitfld.long 0x0 6. "ERROR_PROT_DISABLE_ADM_TX,Error correction disable for Adm Tx path. Note: This register field is sticky." "0,1" newline bitfld.long 0x0 5. "ERROR_PROT_DISABLE_LAYER3_TX,Error correction disable for layer 3 Tx path. Note: This register field is sticky." "0,1" newline bitfld.long 0x0 4. "ERROR_PROT_DISABLE_LAYER2_TX,Error correction disable for layer 2 Tx path. Note: This register field is sticky." "0,1" newline bitfld.long 0x0 3. "ERROR_PROT_DISABLE_DMA_WRITE,Error correction disable for DMA write engine. Note: This register field is sticky." "0,1" newline bitfld.long 0x0 2. "ERROR_PROT_DISABLE_AXI_BRIDGE_OUTBOUND,Error correction disable for AXI bridge outbound request path. Note: This register field is sticky." "0,1" newline bitfld.long 0x0 1. "ERROR_PROT_DISABLE_AXI_BRIDGE_MASTER,Error correction disable for AXI bridge master completion buffer. Note: This register field is sticky." "0,1" newline bitfld.long 0x0 0. "ERROR_PROT_DISABLE_TX,Global error correction disable for all Tx layers. Does not disable the error detection reporting for 1-bit and 2-bit ECC errors. Note: This register field is sticky." "?,bit and 2-bit ECC errors" line.long 0x4 "RASDP_CORR_COUNTER_CTRL_OFF,Corrected error (1-bit ECC) counter selection and control. This is a viewport control register. Setting the CORR_COUNTER_SELECTION_REGION and CORR_COUNTER_SELECTION fields in this register determine the counter data returned.." hexmask.long.byte 0x4 24.--31. 1. "CORR_COUNTER_SELECTION,Counter selection. This field selects the counter ID (within the region defined by CORR_COUNTER_SELECTION_REGION) whose contents can be read from the RASDP_CORR_COUNT_REPORT_OFF register. You can cycle this field value from 0 to.." newline hexmask.long.byte 0x4 20.--23. 1. "CORR_COUNTER_SELECTION_REGION,Select correctable counter region: - 0x0: Region select for Adm Rx path - 0x1: Region select for layer 3 Rx path - 0x2: Region select for layer 2 Rx path - 0x3: Region select for DMA inbound path - 0x4: Region select for AXI.." newline hexmask.long.word 0x4 5.--19. 1. "RSVDP_5,Reserved for future use." newline bitfld.long 0x4 4. "CORR_EN_COUNTERS,Enable correctable errors counters. - 1: counters increment when the controller detects a correctable error - 0: counters are frozen The counters are enabled by default." "counters are frozen,counters increment when the controller detects a.." newline rbitfld.long 0x4 1.--3. "RSVDP_1,Reserved for future use." "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 0. "CORR_CLEAR_COUNTERS,Clear all correctable error counters." "0,1" rgroup.long (0x10+0x480)++0x3 line.long 0x0 "RASDP_CORR_COUNT_REPORT_OFF,Corrected error (1-bit ECC) counter data. This viewport register returns the counter data selected by the CORR_COUNTER_SELECTION_REGION and CORR_COUNTER_SELECTION fields in the RASDP_CORR_COUNTER_CTRL_OFF register." hexmask.long.byte 0x0 24.--31. 1. "CORR_COUNTER_SELECTED,Counter selection. Returns the value set in the CORR_COUNTER_SELECTION field of the RASDP_CORR_COUNTER_CTRL_OFF register." newline hexmask.long.byte 0x0 20.--23. 1. "CORR_COUNTER_SELECTED_REGION,Selected correctable counter region: - 0x0: Region select for Adm Rx path - 0x1: Region select for layer 3 Rx path - 0x2: Region select for layer 2 Rx path - 0x3: Region select for DMA inbound path - 0x4: Region select for.." newline hexmask.long.word 0x0 8.--19. 1. "RSVDP_8,Reserved for future use." newline hexmask.long.byte 0x0 0.--7. 1. "CORR_COUNTER,Current corrected error count for the selected counter." group.long (0x14+0x480)++0x3 line.long 0x0 "RASDP_UNCORR_COUNTER_CTRL_OFF,Uncorrected error (2-bit ECC and parity) counter selection and control. This is a viewport control register. Setting the UNCORR_COUNTER_SELECTION_REGION and UNCORR_COUNTER_SELECTION fields in this register determine the.." hexmask.long.byte 0x0 24.--31. 1. "UNCORR_COUNTER_SELECTION,Counter selection. This field selects the counter ID (within the region defined by UNCORR_COUNTER_SELECTION_REGION) whose contents can be read from the RASDP_UNCORR_COUNT_REPORT_OFF register. You can cycle this field value from 0.." newline hexmask.long.byte 0x0 20.--23. 1. "UNCORR_COUNTER_SELECTION_REGION,Select uncorrectable counter region: - 0x0: Region select for Adm Rx path - 0x1: Region select for layer 3 Rx path - 0x2: Region select for layer 2 Rx path - 0x3: Region select for DMA inbound path - 0x4: Region select for.." newline hexmask.long.word 0x0 5.--19. 1. "RSVDP_5,Reserved for future use." newline bitfld.long 0x0 4. "UNCORR_EN_COUNTERS,Enable uncorrectable errors counters. - 1: enables the counters to increment on detected correctable errors - 0: counters are frozen The counters are enabled by default." "counters are frozen,enables the counters to increment on detected.." newline rbitfld.long 0x0 1.--3. "RSVDP_1,Reserved for future use." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 0. "UNCORR_CLEAR_COUNTERS,Clear uncorrectable errors counters. When asserted causes all counters tracking the uncorrectable errors to be cleared." "0,1" rgroup.long (0x18+0x480)++0x3 line.long 0x0 "RASDP_UNCORR_COUNT_REPORT_OFF,Uncorrected error (2-bit ECC and parity) counter data. This viewport register returns the counter data selected by the UNCORR_COUNTER_SELECTION_REGION and UNCORR_COUNTER_SELECTION fields in the RASDP_UNCORR_COUNTER_CTRL_OFF.." hexmask.long.byte 0x0 24.--31. 1. "UNCORR_COUNTER_SELECTED,Counter selection. Returns the value set in the UNCORR_COUNTER_SELECTION field of the RASDP_UNCORR_COUNTER_CTRL_OFF register." newline hexmask.long.byte 0x0 20.--23. 1. "UNCORR_COUNTER_SELECTED_REGION,Selected uncorrectable counter region: - 0x0: Region select for Adm Rx path - 0x1: Region select for layer 3 Rx path - 0x2: Region select for layer 2 Rx path - 0x3: Region select for DMA inbound path - 0x4: Region select.." newline hexmask.long.word 0x0 8.--19. 1. "RSVDP_8,Reserved for future use." newline hexmask.long.byte 0x0 0.--7. 1. "UNCORR_COUNTER,Current uncorrected error count for the selected counter" group.long (0x1C+0x480)++0x3 line.long 0x0 "RASDP_ERROR_INJ_CTRL_OFF,Error injection control for the following features: - 1-bit or 2-bit injection - Continuous or fixed-number (n) injection modes - Global enable/disable - Selectable location where injection occurs" hexmask.long.byte 0x0 24.--31. 1. "RSVDP_24,Reserved for future use." newline hexmask.long.byte 0x0 16.--23. 1. "ERROR_INJ_LOC,Error injection location. Selects where error injection takes place. You can cycle this field value from 0 to 255 to access all locations according to the detailed report of check points at.." newline hexmask.long.byte 0x0 8.--15. 1. "ERROR_INJ_COUNT,Error injection count. - 0: errors are inserted in every TLP until you clear ERROR_INJ_EN. - 1: one errors injected - 2: two errors injected - n: amount of errors injected" newline rbitfld.long 0x0 6.--7. "RSVDP_6,Reserved for future use." "0,1,2,3" newline bitfld.long 0x0 4.--5. "ERROR_INJ_TYPE,Error injection type: - 0: none - 1: 1-bit - 2: 2-bit" "none,bit,bit,?" newline rbitfld.long 0x0 1.--3. "RSVDP_1,Reserved for future use." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 0. "ERROR_INJ_EN,Error injection global enable. When set enables the error insertion logic." "0,1" rgroup.long (0x20+0x480)++0x7 line.long 0x0 "RASDP_CORR_ERROR_LOCATION_OFF,Corrected errors locations. For more details. see the RAS Data Protection (DP) section in the Core Operations chapter of the Databook." hexmask.long.byte 0x0 24.--31. 1. "LOC_LAST_CORR_ERROR,Location/ID of the last corrected error within the region defined by REG_LAST_CORR_ERROR. You can cycle this field value from 0 to 255 to access all counters according to the detailed report of check points at.." newline hexmask.long.byte 0x0 20.--23. 1. "REG_LAST_CORR_ERROR,Region of the last corrected error: - 0x0: Region select for Adm Rx path - 0x1: Region select for layer 3 Rx path - 0x2: Region select for layer 2 Rx path - 0x3: Region select for DMA inbound path - 0x4: Region select for AXI bridge.." newline hexmask.long.byte 0x0 16.--19. 1. "RSVDP_16,Reserved for future use." newline hexmask.long.byte 0x0 8.--15. 1. "LOC_FIRST_CORR_ERROR,Location/ID of the first corrected error within the region defined by REG_FIRST_CORR_ERROR. You can cycle this field value from 0 to 255 to access all counters according to the detailed report of check points at.." newline hexmask.long.byte 0x0 4.--7. 1. "REG_FIRST_CORR_ERROR,Region of the first corrected error: - 0x0: Region select for Adm Rx path - 0x1: Region select for layer 3 Rx path - 0x2: Region select for layer 2 Rx path - 0x3: Region select for DMA inbound path - 0x4: Region select for AXI bridge.." newline hexmask.long.byte 0x0 0.--3. 1. "RSVDP_0,Reserved for future use." line.long 0x4 "RASDP_UNCORR_ERROR_LOCATION_OFF,Uncorrected errors locations. For more details. see the RAS Data Protection (DP) section in the Core Operations chapter of the Databook." hexmask.long.byte 0x4 24.--31. 1. "LOC_LAST_UNCORR_ERROR,Location/ID of the last uncorrected error within the region defined by REG_LAST_UNCORR_ERROR. You can cycle this field value from 0 to 255 to access all counters according to the detailed report of check points at.." newline hexmask.long.byte 0x4 20.--23. 1. "REG_LAST_UNCORR_ERROR,Region of the last uncorrected error: - 0x0: Region select for Adm Rx path - 0x1: Region select for layer 3 Rx path - 0x2: Region select for layer 2 Rx path - 0x3: Region select for DMA inbound path - 0x4: Region select for AXI.." newline hexmask.long.byte 0x4 16.--19. 1. "RSVDP_16,Reserved for future use." newline hexmask.long.byte 0x4 8.--15. 1. "LOC_FIRST_UNCORR_ERROR,Location/ID of the first uncorrected error within the region defined by REG_FIRST_UNCORR_ERROR. You can cycle this field value from 0 to 255 to access all counters according to the detailed report of check points at.." newline hexmask.long.byte 0x4 4.--7. 1. "REG_FIRST_UNCORR_ERROR,Region of the first uncorrected error: - 0x0: Region select for Adm Rx path - 0x1: Region select for layer 3 Rx path - 0x2: Region select for layer 2 Rx path - 0x3: Region select for DMA inbound path - 0x4: Region select for AXI.." newline hexmask.long.byte 0x4 0.--3. 1. "RSVDP_0,Reserved for future use." group.long (0x28+0x480)++0x7 line.long 0x0 "RASDP_ERROR_MODE_EN_OFF,RASDP error mode enable. The controller enters RASDP error mode (if ERROR_MODE_EN =1) upon detection of the first uncorrectable error. During this mode: - Rx TLPs that are forwarded to your application are not guaranteed to be.." hexmask.long 0x0 2.--31. 1. "RSVDP_2,Reserved for future use." newline bitfld.long 0x0 1. "AUTO_LINK_DOWN_EN,Write '1' to enable the controller to bring the link down when the controller enters RASDP error mode. Note: This register field is sticky." "0,1" newline bitfld.long 0x0 0. "ERROR_MODE_EN,Write '1' to enable the controller enter RASDP error mode when it detects an uncorrectable error. Note: This register field is sticky." "0,1" line.long 0x4 "RASDP_ERROR_MODE_CLEAR_OFF,Exit RASDP error mode. For more details. see the RAS Data Protection (DP) section in the Core Operations chapter of the Databook." hexmask.long 0x4 1.--31. 1. "RSVDP_1,Reserved for future use." newline bitfld.long 0x4 0. "ERROR_MODE_CLEAR,Write '1' to take the controller out of RASDP error mode. The controller will then report uncorrectable errors (through AER internal error reporting) and also stop nullifying/discarding TLPs." "0,1" rgroup.long (0x30+0x480)++0x7 line.long 0x0 "RASDP_RAM_ADDR_CORR_ERROR_OFF,RAM Address where a corrected error (1-bit ECC) has been detected. For more details. see the RAS Data Protection (DP) section in the Core Operations chapter of the Databook." hexmask.long.byte 0x0 28.--31. 1. "RAM_INDEX_CORR_ERROR,RAM index where a corrected error (1-bit ECC) has been detected." newline bitfld.long 0x0 27. "RSVDP_27,Reserved for future use." "0,1" newline hexmask.long 0x0 0.--26. 1. "RAM_ADDR_CORR_ERROR,RAM Address where a corrected error (1-bit ECC) has been detected." line.long 0x4 "RASDP_RAM_ADDR_UNCORR_ERROR_OFF,RAM Address where an uncorrected error (2-bit ECC) has been detected. For more details. see the RAS Data Protection (DP) section in the Core Operations chapter of the Databook." hexmask.long.byte 0x4 28.--31. 1. "RAM_INDEX_UNCORR_ERROR,RAM index where an uncorrected error (2-bit ECC) has been detected." newline bitfld.long 0x4 27. "RSVDP_27,Reserved for future use." "0,1" newline hexmask.long 0x4 0.--26. 1. "RAM_ADDR_UNCORR_ERROR,RAM Address where an uncorrected error (2-bit ECC) has been detected." tree.end tree "PF0_RTR_CAP (PF RTR Capability Structure)" group.long (0x0+0x2F8)++0xB line.long 0x0 "RTR_EXT_CAP_HDR_OFF,Readiness Time Reporting PCI Express Extended Capability Header. For a description of this standard PCIe register. see the PCI Express Specification." hexmask.long.word 0x0 20.--31. 1. "RTR_NEXT_OFFSET,Next Capability Offset. For a description of this standard PCIe register field see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky).." hexmask.long.byte 0x0 16.--19. 1. "RTR_CAP_VERSION,Capability Version. For a description of this standard PCIe register field see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky).." hexmask.long.word 0x0 0.--15. 1. "RTR_EXT_CAP_ID,PCI Express Extended Capability ID. For a description of this standard PCIe register field see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then.." line.long 0x4 "READI_TIME_REPORTING1_OFF,Readiness Time Reporting 1. For a description of this standard PCIe register. see the PCI Express Specification." bitfld.long 0x4 31. "RTR_TIME_VALID,Valid. For a description of this standard PCIe register field see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky)" "0,1" hexmask.long.byte 0x4 24.--30. 1. "RSVDP_24,Reserved for future use." hexmask.long.word 0x4 12.--23. 1. "DL_UP_TIME,DL_UP Time. For a description of this standard PCIe register field see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky)" hexmask.long.word 0x4 0.--11. 1. "RESET_TIME,Reset Time. For a description of this standard PCIe register field see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky)" line.long 0x8 "READI_TIME_REPORTING2_OFF,Readiness Time Reporting 2. For a description of this standard PCIe register. see the PCI Express Specification." hexmask.long.byte 0x8 24.--31. 1. "RSVDP_24,Reserved for future use." hexmask.long.word 0x8 12.--23. 1. "D3HOT_D0_TIME,D3hot to D0 Time. For a description of this standard PCIe register field see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else.." hexmask.long.word 0x8 0.--11. 1. "FLR_TIME,FLR Time. For a description of this standard PCIe register field see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky)" tree.end tree "PF0_RTR_CAP_DBI2 (DBI2 Shadow Block: PF RTR Capability Structure)" rgroup.long (0x4+0x12F8)++0x7 line.long 0x0 "SHADOW_READI_TIME_REPORTING1_OFF,Shadow Register Readiness Time Reporting 1. For a description of this standard PCIe register. see the PCI Express Specification." bitfld.long 0x0 31. "RTR_TIME_VALID,Shadow Valid in the shadow register. For a description of this standard PCIe register field see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access - Dbi: No access - Dbi2: if.." "0,1" hexmask.long.tbyte 0x0 12.--30. 1. "RSVDP_12,Reserved for future use." hexmask.long.word 0x0 0.--11. 1. "RESET_TIME,Shadow Reset Time in the shadow register. For a description of this standard PCIe register field see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access - Dbi: No access - Dbi2: if.." line.long 0x4 "SHADOW_READI_TIME_REPORTING2_OFF,Shadow Register Readiness Time Reporting 2. For a description of this standard PCIe register. see the PCI Express Specification." hexmask.long.byte 0x4 24.--31. 1. "RSVDP_24,Reserved for future use." hexmask.long.word 0x4 12.--23. 1. "D3HOT_D0_TIME,Shadow D3hot to D0 Time in the shadow register. For a description of this standard PCIe register field see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access - Dbi: No access - Dbi2:.." hexmask.long.word 0x4 0.--11. 1. "FLR_TIME,Shadow FLR Time in the shadow register. For a description of this standard PCIe register field see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access - Dbi: No access - Dbi2: if.." tree.end tree "PF0_FRSQ_CAP (PF FRSQ Capability Structure)" group.long (0x0+0x2E8)++0xB line.long 0x0 "FRSQ_EXT_CAP_HDR_OFF,FRS Queuing Extended Capability Header. For a description of this standard PCIe register. see the PCI Express Specification." hexmask.long.word 0x0 20.--31. 1. "FRSQ_NEXT_OFFSET,Next Capability Offset. For a description of this standard PCIe register field see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then.." hexmask.long.byte 0x0 16.--19. 1. "FRSQ_CAP_VERSION,Capability Version. For a description of this standard PCIe register field see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky).." hexmask.long.word 0x0 0.--15. 1. "FRSQ_EXT_CAP_ID,PCI Express Extended Capability ID. For a description of this standard PCIe register field see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then.." line.long 0x4 "FRSQ_CAP_OFF,FRS Queuing Capability Register. For a description of this standard PCIe register. see the PCI Express Specification." hexmask.long.word 0x4 21.--31. 1. "RSVDP_21,Reserved for future use." hexmask.long.byte 0x4 16.--20. 1. "FRS_INT_MESSAGE_NUMBER,FRS Interrupt Message Number. For a description of this standard PCIe register field see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1).." hexmask.long.byte 0x4 12.--15. 1. "RSVDP_12,Reserved for future use." hexmask.long.word 0x4 0.--11. 1. "FRSQ_MAX_DEPTH,FRS Queue Max Depth. For a description of this standard PCIe register field see the PCI Express Specification." line.long 0x8 "FRSQ_CONTROL_FRSQ_STATUS_OFF,FRS Queuing Status and Control Register. For a description of this standard PCIe register. see the PCI Express Specification." hexmask.long.word 0x8 17.--31. 1. "RSVDP_17,Reserved for future use." bitfld.long 0x8 16. "FRS_INTERRUPT_ENABLE,FRS Interrupt Enable. For a description of this standard PCIe register field see the PCI Express Specification." "0,1" hexmask.long.word 0x8 2.--15. 1. "RSVDP_2,Reserved for future use." bitfld.long 0x8 1. "FRS_MESSAGE_OVERFLOW,FRS Message Overflow. For a description of this standard PCIe register field see the PCI Express Specification." "0,1" newline bitfld.long 0x8 0. "FRS_MESSAGE_RECEIVED,FRS Message Received. For a description of this standard PCIe register field see the PCI Express Specification." "0,1" rgroup.long (0xC+0x2E8)++0x3 line.long 0x0 "FRS_MESSAGE_QUEUE_OFF,FRS Message Queue Register. For a description of this standard PCIe register. see the PCI Express Specification." hexmask.long.word 0x0 20.--31. 1. "FRS_MESSAGE_QUE_DEPTH,FRS Message Queue Depth. For a description of this standard PCIe register field see the PCI Express Specification." hexmask.long.byte 0x0 16.--19. 1. "FRS_MESSAGE_QUE_REASON,FRS Message Queue Reason. For a description of this standard PCIe register field see the PCI Express Specification." hexmask.long.word 0x0 0.--15. 1. "FRS_MESSAGE_QUE_FUNC_ID,FRS Message Queue Function ID. For a description of this standard PCIe register field see the PCI Express Specification." tree.end tree "PF0_PTM_CAP (PF PTM Capability Structure)" group.long (0x0+0x40C)++0xB line.long 0x0 "PTM_EXT_CAP_HDR_OFF,Precision Time Measurement Capability Header. For a description of this standard PCIe register. see the PCI Express Specification." hexmask.long.word 0x0 20.--31. 1. "PTM_NEXT_OFFSET,Precision Time Measurement PCI Express Extended Capability Next Offset. For a description of this standard PCIe register see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access. -.." hexmask.long.byte 0x0 16.--19. 1. "PTM_CAP_VERSION,Precision Time Measurement PCI Express Extended Capability Version. For a description of this standard PCIe register see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi:.." hexmask.long.word 0x0 0.--15. 1. "PTM_CAP_ID,Precision Time Measurement PCI Express Extended Capability ID. For a description of this standard PCIe register see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if.." line.long 0x4 "PTM_CAP_OFF,PTM Capability Register. For a description of this standard PCIe register. see the PCI Express Specification." hexmask.long.word 0x4 16.--31. 1. "RSVDP_16,Reserved for future use." hexmask.long.byte 0x4 8.--15. 1. "PTM_CLK_GRAN,PTM Local Clock Granularity. For a description of this standard PCIe register see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky).." hexmask.long.byte 0x4 3.--7. 1. "RSVDP_3,Reserved for future use." bitfld.long 0x4 2. "PTM_ROOT_CAPABLE,PTM Root Capable. For a description of this standard PCIe register see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else.." "0,1" bitfld.long 0x4 1. "PTM_RES_CAPABLE,PTM Responder Capable. For a description of this standard PCIe register see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else.." "0,1" newline bitfld.long 0x4 0. "PTM_REQ_CAPABLE,PTM Requester Capable. For a description of this standard PCIe register see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else.." "0,1" line.long 0x8 "PTM_CONTROL_OFF,PTM Control Register. For a description of this standard PCIe register. see the PCI Express Specification." hexmask.long.word 0x8 16.--31. 1. "RSVDP_16,Reserved for future use." hexmask.long.byte 0x8 8.--15. 1. "EFF_GRAN,PTM Effective Granularity. For a description of this standard PCIe register see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: HWINIT" hexmask.long.byte 0x8 2.--7. 1. "RSVDP_2,Reserved for future use." rbitfld.long 0x8 1. "ROOT_SELECT,PTM Root Select. When set this Time Source is the PTM Root. For a description of this standard PCIe register see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: HWINIT" "0,1" bitfld.long 0x8 0. "PTM_ENABLE,PTM Enable. When set this function is permitted to participate in the PTM mechanism. For a description of this standard PCIe register see the PCI Express Specification." "0,1" tree.end tree "PF0_PTM_RES_CAP (PF PTM Responder Capability Structure (VSEC))" group.long (0x0+0x418)++0xB line.long 0x0 "PTM_RES_CAP_HDR_OFF,Precision Time Measurement Responder Capability Header (VSEC). For more details. see the PTM section in the Databook." hexmask.long.word 0x0 20.--31. 1. "PTM_RES_EXT_CAP_NEXT_OFFS,Precision Time Measurement Responder VSEC Next Pointer. For more details see the PTM section in the Databook. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then.." hexmask.long.byte 0x0 16.--19. 1. "PTM_RES_EXT_CAP_VER,Precision Time Measurement Responder VSEC Version. For more details see the PTM section in the Databook. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else.." hexmask.long.word 0x0 0.--15. 1. "PTM_RES_EXT_CAP_ID,Precision Time Measurement Responder VSEC ID. For more details see the PTM section in the Databook. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else.." line.long 0x4 "PTM_RES_HDR_OFF,Precision Time Measurement Responder Vendor Specific Header. For more details. see the PTM section in the Databook." hexmask.long.word 0x4 20.--31. 1. "PTM_RES_VSEC_LENGTH,PTM Responder VSEC Length. For more details see the PTM section in the Databook. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This.." hexmask.long.byte 0x4 16.--19. 1. "PTM_RES_VSEC_REV,PTM Responder VSEC Revision. For more details see the PTM section in the Databook. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This.." hexmask.long.word 0x4 0.--15. 1. "PTM_RES_VSEC_ID,PTM Responder VSEC ID. For more details see the PTM section in the Databook. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register.." line.long 0x8 "PTM_RES_CONTROL_OFF,PTM Responder Control Register. For more details. see the PTM section in the Databook." hexmask.long 0x8 2.--31. 1. "RSVDP_2,Reserved for future use." bitfld.long 0x8 1. "PTM_RES_PDEL_BYTE_REV,PTM Requester Propagation Delay Byte Reversal - Reverse the order of bytes in the PTM Propagation Delay data word of the PTM ResponseD Message for compatibility with previous revisions. For more details see the PTM section in the.." "0,1" bitfld.long 0x8 0. "PTM_RES_CCONTEXT_VALID,PTM Responder Control Context Valid - PTM Local Timing is valid. This bit is set over the DBI. A speed change or aux_clk_active will set this bit low. For more details see the PTM section in the Databook. Note: The access.." "0,1" rgroup.long (0xC+0x418)++0x3 line.long 0x0 "PTM_RES_STATUS_OFF,PTM Responder Status Register. For more details. see the PTM section in the Databook." hexmask.long 0x0 2.--31. 1. "RSVDP_2,Reserved for future use." bitfld.long 0x0 1. "PTM_RES_REQUEST_RECEIVED,PTM 1st Request Received - PTM Responder has received the first PTM Request Message. Upon receipt of a second PTM Request Message a ResponseD message with timing information will be sent from the Responder if the context is.." "0,1" bitfld.long 0x0 0. "PTM_RES_CONTEXT_VALID,PTM Responder Status Context Valid - PTM Local Timing Context is Valid. Value set from upstream port Requester in a Switch. Shadows the same in the control register in all other products. For more details see the PTM section in the.." "0,1" group.long (0x10+0x418)++0x7 line.long 0x0 "PTM_RES_LOCAL_LSB_OFF,PTM Responder Local Clock LSB. For more details. see the PTM section in the Databook." hexmask.long 0x0 0.--31. 1. "PTM_RES_LOCAL_LSB,PTM Responder Local Clock LSB - Lower 32 bits of local timer value. For more details see the PTM section in the Databook. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then.." line.long 0x4 "PTM_RES_LOCAL_MSB_OFF,PTM Responder Local Clock MSB. For more details. see the PTM section in the Databook." hexmask.long 0x4 0.--31. 1. "PTM_RES_LOCAL_MSB,PTM Responder Local Clock MSB - Upper 32 bits of local timer value. For more details see the PTM section in the Databook. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then.." rgroup.long (0x18+0x418)++0x1F line.long 0x0 "PTM_RES_T2_LSB_OFF,PTM Responder T2 Timestamp LSB. For more details. see the PTM section in the Databook." hexmask.long 0x0 0.--31. 1. "PTM_RES_T2_LSB,PTM Responder T2 Timestamp LSB - Lower 32 bits of the T2 Timestamp value. For more details see the PTM section in the Databook. Note: This register field is sticky." line.long 0x4 "PTM_RES_T2_MSB_OFF,PTM Responder T2 Timestamp MSB. For more details. see the PTM section in the Databook." hexmask.long 0x4 0.--31. 1. "PTM_RES_T2_MSB,PTM Responder T2 Timestamp MSB - Upper 32 bits of the T2 Timestamp value. For more details see the PTM section in the Databook. Note: This register field is sticky." line.long 0x8 "PTM_RES_T2P_LSB_OFF,PTM Responder T2 Previous Timestamp LSB. For more details. see the PTM section in the Databook." hexmask.long 0x8 0.--31. 1. "PTM_RES_T2P_LSB,PTM Responder T2 Previous Timestamp LSB - Lower 32 bits of the previously stored T2 Timestamp value. For more details see the PTM section in the Databook. Note: This register field is sticky." line.long 0xC "PTM_RES_T2P_MSB_OFF,PTM Responder T2 Previous Timestamp MSB. For more details. see the PTM section in the Databook." hexmask.long 0xC 0.--31. 1. "PTM_RES_T2P_MSB,PTM Responder T2 Previous Timestamp MSB - Upper 32 bits of the previously stored T2 Timestamp value. For more details see the PTM section in the Databook. Note: This register field is sticky." line.long 0x10 "PTM_RES_T3_LSB_OFF,PTM Responder T3 Timestamp LSB. For more details. see the PTM section in the Databook." hexmask.long 0x10 0.--31. 1. "PTM_RES_T3_LSB,PTM Responder T3 Timestamp LSB - Lower 32 bits of the T3 Timestamp value. For more details see the PTM section in the Databook. Note: This register field is sticky." line.long 0x14 "PTM_RES_T3_MSB_OFF,PTM Responder T3 Timestamp MSB. For more details. see the PTM section in the Databook." hexmask.long 0x14 0.--31. 1. "PTM_RES_T3_MSB,PTM Responder T3 Timestamp MSB - Upper 32 bits of the T2 Timestamp value. For more details see the PTM section in the Databook. Note: This register field is sticky." line.long 0x18 "PTM_RES_T3P_LSB_OFF,PTM Responder T3 Previous Timestamp LSB. For more details. see the PTM section in the Databook." hexmask.long 0x18 0.--31. 1. "PTM_RES_T3P_LSB,PTM Responder T3 Previous Timestamp LSB - Lower 32 bits of the previously stored T3 Timestamp value. For more details see the PTM section in the Databook. Note: This register field is sticky." line.long 0x1C "PTM_RES_T3P_MSB_OFF,PTM Responder T3 Previous Timestamp MSB. For more details. see the PTM section in the Databook." hexmask.long 0x1C 0.--31. 1. "PTM_RES_T3P_MSB,PTM Responder T3 Previous Timestamp MSB - Upper 32 bits of the previously stored T3 Timestamp value. For more details see the PTM section in the Databook. Note: This register field is sticky." group.long (0x38+0x418)++0x7 line.long 0x0 "PTM_RES_TX_LATENCY_OFF,PTM Responder TX Latency. For more details. see the PTM section in the Databook." hexmask.long.tbyte 0x0 12.--31. 1. "RSVDP_12,Reserved for future use." hexmask.long.word 0x0 0.--11. 1. "PTM_RES_TX_LATENCY,PTM Responder TX Latency - Responder Transmit path latency (12 bit wide). For more details see the PTM section in the Databook. Note: This register field is sticky." line.long 0x4 "PTM_RES_RX_LATENCY_OFF,PTM Responder RX Latency. For more details. see the PTM section in the Databook." hexmask.long.tbyte 0x4 12.--31. 1. "RSVDP_12,Reserved for future use." hexmask.long.word 0x4 0.--11. 1. "PTM_RES_RX_LATENCY,PTM Responder RX Latency - Responder Receive path latency (12 bit wide). For more details see the PTM section in the Databook. Note: This register field is sticky." rgroup.long (0x40+0x418)++0x3 line.long 0x0 "PTM_RES_NOM_CLOCK_T_OFF,PTM Responder Nominal Clock Period. For more details. see the PTM section in the Databook." hexmask.long.byte 0x0 24.--31. 1. "RSVDP_24,Reserved for future use." hexmask.long.byte 0x0 16.--23. 1. "PTM_RES_NOM_CLOCK_T_INT,PTM Responder Nominal Clock Period Integral - Integral part of the nominal PTM local clock period in nanoseconds. For more details see the PTM section in the Databook. Note: This register field is sticky." hexmask.long.word 0x0 0.--15. 1. "PTM_RES_NOM_CLOCK_T_FRAC,PTM Responder Nominal Clock Period Fractional - Fractional part of the nominal PTM local clock period. LSB is 1/(2^16) nanoseconds. For more details see the PTM section in the Databook. Note: This register field is sticky." group.long (0x44+0x418)++0x3 line.long 0x0 "PTM_RES_SCALED_CLOCK_T_OFF,PTM Responder Scaled Clock Period. For more details. see the PTM section in the Databook." bitfld.long 0x0 31. "PTM_RES_SCALED_CLOCK_T_EN,PTM Responder Scaled Clock Period Enable - Use the programmed scaled PTM clock period rather than the nominal values. This bit is cleared when the core_clk rate starts to change and can only be set when the clock period change.." "0,1" hexmask.long.byte 0x0 24.--30. 1. "RSVDP_24,Reserved for future use." hexmask.long.byte 0x0 16.--23. 1. "PTM_RES_SCALED_CLOCK_T_INT,PTM Responder Scaled Clock Period Integral - Integral part of the nominal PTM local clock period in nanoseconds. For more details see the PTM section in the Databook. Note: This register field is sticky." newline hexmask.long.word 0x0 0.--15. 1. "PTM_RES_SCALED_CLOCK_T_FRAC,PTM Responder Scaled Clock Period Fractional - Fractional part of the nominal PTM local clock period. LSB is 1/(2^16) nanoseconds. For more details see the PTM section in the Databook. Note: This register field is sticky." tree.end tree "PF0_PM_CAP (PF PCI Power Management Capability Structure)" group.long (0x0+0x40)++0x7 line.long 0x0 "CAP_ID_NXT_PTR_REG,Power Management Capabilities Register." hexmask.long.byte 0x0 27.--31. 1. "PME_SUPPORT,PME_Support. This 5-bit field indicates the power states in which the function may generate a PME and/or forward PME messages. A value of 0b for any bit indicates that the function is not capable of asserting PME while in that power state. -.." bitfld.long 0x0 26. "D2_SUPPORT,D2_Support. If this bit is set this function supports the D2 Power Management state. Functions that do not support D2 must always return a value of 0b for this bit. Note: The access attributes of this field are as follows: - Wire: No access." "0,1" bitfld.long 0x0 25. "D1_SUPPORT,D1_Support. If this bit is set this function supports the D1 Power Management state. Functions that do not support D1 must always return a value of 0b for this bit. Note: The access attributes of this field are as follows: - Wire: No access." "0,1" bitfld.long 0x0 22.--24. "AUX_CURR,Aux_Current. This 3 bit field reports the Vaux auxiliary current requirements for the function. If this function implements the Data Register the controller hardwires this field to 000b. If PME_Support is 0 xxxxb (PME assertion from D3cold is.." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 21. "DSI,Device Specific Initialization. The DSI bit indicates whether special initialization of this function is required. When set indicates that the function requires a device specific initialization sequence following a transition to the D0uninitialized.." "0,1" bitfld.long 0x0 20. "PME_IMM_READI_RETURN_DO,Immediate_Readiness_on_Return_to_D0. - If this bit is a '1' this function is guaranteed to be ready to successfully complete valid accesses immediately after being set to D0. These accesses include configuration cycles and if.." "0,1" rbitfld.long 0x0 19. "PME_CLK,PME Clock. Does not apply to PCI Express the controller hardwires it to 0b. Note: This register field is sticky." "0,1" bitfld.long 0x0 16.--18. "PM_SPEC_VER,Version. This field provides the Power Management specification version. The controller hardwires this field to 011b for functions compliant to PCI Express Base Specification Revision 4.0 Version 1.0>. Note: The access attributes of this.." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x0 8.--15. 1. "PM_NEXT_POINTER,Next Capability Pointer. This field provides an offset into the function's configuration space pointing to the location of next item in the capabilities list. If there are no additional items in the capabilities list this field is set to.." hexmask.long.byte 0x0 0.--7. 1. "PM_CAP_ID,Capability ID. This field returns 01h to indicate that this is the PCI Power Management Capability. Each function may have only one item in its capability list with Capability ID set to 01h." line.long 0x4 "CON_STATUS_REG,Power Management Control and Status Register. This register is used to manage the PCI function's power management state as well as to enable/monitor PMEs." hexmask.long.byte 0x4 24.--31. 1. "DATA_REG_ADD_INFO,Data. This field is used to report the state dependent data requested by the Data_Select field. The value of this field is scaled by the value reported by the Data_Scale field." rbitfld.long 0x4 23. "BUS_PWR_CLK_CON_EN,Bus Power/Clock Control Enable. For a description of this standard PCIe register field see the PCI Express Base Specification." "0,1" rbitfld.long 0x4 22. "B2_B3_SUPPORT,B2B3 Support for D3hot. For a description of this standard PCIe register field see the PCI Express Base Specification." "0,1" hexmask.long.byte 0x4 16.--21. 1. "RSVDP_16,Reserved for future use." newline bitfld.long 0x4 15. "PME_STATUS,PME_Status. This bit is set when the function normally generates a PME signal. The value of this bit is not affected by the value of the PME_En bit. If PME_Support bit 31 of the Power Management Capabilities register is clear this bit is.." "0,1" rbitfld.long 0x4 13.--14. "DATA_SCALE,Data_Scale. This field indicates the scaling factor to be used when interpreting the value of the Data field. The value and meaning of this field varies depending on which data value has been selected by the Data_Select field. For more details.." "0,1,2,3" hexmask.long.byte 0x4 9.--12. 1. "DATA_SELECT,Data_Select. This 4-bit field is used to select which data is to be reported through the Data and Data_Scale field. If the Data field is not implemented this field must be hardwired to 0000b." bitfld.long 0x4 8. "PME_ENABLE,PME_En. - When set the function is permitted to generate a PME. - When clear the function is not permitted to generate a PME. If PME_Support is 1 xxxxb (PME generation from D3cold) or the function consumes Aux power and Aux power is.." "0,1" newline hexmask.long.byte 0x4 4.--7. 1. "RSVDP_4,Reserved for future use." bitfld.long 0x4 3. "NO_SOFT_RST,No_Soft_Reset. This bit indicates the state of the function after writing the PowerState field to transition the function from D3hot to D0. - When set this transition preserves internal function state. The function is in D0Active and no.." "0,1" rbitfld.long 0x4 2. "RSVDP_2,Reserved for future use." "0,1" bitfld.long 0x4 0.--1. "POWER_STATE,PowerState. This 2-bit field is used both to determine the current power state of a function and to set the function into a new power state. The definition of the field values is given below. You can write to this register; however the.." "D0,D1,D2,D3hot" tree.end tree "PF0_PCIE_CAP (PF PCI Express Capability Structure)" group.long (0x0+0x70)++0x33 line.long 0x0 "PCIE_CAP_ID_PCIE_NEXT_CAP_PTR_PCIE_CAP_REG,PCI Express Capabilities. ID. Next Pointer Register." rbitfld.long 0x0 31. "RSVDP_31,Reserved for future use." "0,1" rbitfld.long 0x0 30. "RSVD,Reserved." "0,1" newline hexmask.long.byte 0x0 25.--29. 1. "PCIE_INT_MSG_NUM,PCIE Interrupt Message Number. For a description of this standard PCIe register field see the PCI Express Base Specification. Interrupt Message Number. This field indicates which MSI/MSI-X vector is used for the interrupt message.." bitfld.long 0x0 24. "PCIE_SLOT_IMP,Slot Implemented. When set this bit indicates that the Link associated with this Port is connected to a slot (as compared to being connected to a system-integrated device or being disabled). This bit is valid for Downstream Ports. This bit.." "0,1" newline hexmask.long.byte 0x0 20.--23. 1. "PCIE_DEV_PORT_TYPE,Device/Port Type. Indicates the specific type of this PCI Express function. Note: Different functions in a Multi-Function Device can generally be of different types. Defined encodings for functions that implement a Type 00h PCI.." hexmask.long.byte 0x0 16.--19. 1. "PCIE_CAP_REG,Capability Version. Indicates PCI-SIG defined PCI Express Capability structure version number. A version of the specification that changes the PCI Express Capability structure in a way that is not otherwise identifiable (for example through.." newline hexmask.long.byte 0x0 8.--15. 1. "PCIE_CAP_NEXT_PTR,Next Capability Pointer. This field contains the offset to the next PCI Capability structure or 00h if no other items exist in the linked list of Capabilities. Note: The access attributes of this field are as follows: - Wire: No access." hexmask.long.byte 0x0 0.--7. 1. "PCIE_CAP_ID,Capability ID. Indicates the PCI Express Capability structure. This field must return a Capability ID of 10h indicating that this is a PCI Express Capability structure." line.long 0x4 "DEVICE_CAPABILITIES_REG,Device Capabilities Register. The Device Capabilities register identifies PCI Express device function specific capabilities." hexmask.long.word 0x4 16.--31. 1. "RSVDP_16,Reserved for future use." bitfld.long 0x4 15. "PCIE_CAP_ROLE_BASED_ERR_REPORT,Role-Based Error Reporting. When set this bit indicates that the function implements the functionality originally defined in the Error Reporting ECN for PCI Express Base Specification Revision 1.0a and later incorporated.." "0,1" newline hexmask.long.word 0x4 6.--14. 1. "RSVDP_6,Reserved for future use." bitfld.long 0x4 5. "PCIE_CAP_EXT_TAG_SUPP,Extended Tag Field Supported. This bit in combination with the 10-Bit Tag Requester Supported bit in the Device Capabilities 2 register indicates the maximum supported size of the Tag field as a Requester. This bit must be set if.." "0,1" newline bitfld.long 0x4 3.--4. "PCIE_CAP_PHANTOM_FUNC_SUPPORT,Phantom Functions Supported. This field indicates the support for use of unclaimed function numbers to extend the number of outstanding transactions allowed by logically combining unclaimed function numbers (called Phantom.." "0,1,2,3" bitfld.long 0x4 0.--2. "PCIE_CAP_MAX_PAYLOAD_SIZE,Max_Payload_Size Supported. This field indicates the maximum payload size that the function can support for TLPs. Defined encodings are: - 000b: 128 bytes max payload size - 001b: 256 bytes max payload size - 010b: 512 bytes max.." "0,1,2,3,4,5,6,7" line.long 0x8 "DEVICE_CONTROL_DEVICE_STATUS,Device Control and Device Status Register. This register controls PCI Express device specific parameters and provides information about PCI Express device (function) specific parameters." hexmask.long.word 0x8 22.--31. 1. "RSVDP_22,Reserved for future use." rbitfld.long 0x8 21. "PCIE_CAP_TRANS_PENDING,Transactions Pending. Endpoints: When set this bit indicates that the function has issued Non-Posted Requests that have not been completed. A Function reports this bit cleared only when all outstanding Non-Posted Requests have.." "0,1" newline rbitfld.long 0x8 20. "PCIE_CAP_AUX_POWER_DETECTED,AUX Power Detected. Functions that require Aux power report this bit as set if Aux power is detected by the function. This bit is derived by sampling the sys_aux_pwr_det input." "0,1" bitfld.long 0x8 19. "PCIE_CAP_UNSUPPORTED_REQ_DETECTED,Unsupported Request Detected. This bit indicates that the function received an Unsupported Request. Errors are logged in this register regardless of whether error reporting is enabled or not in the Device Control.." "0,1" newline bitfld.long 0x8 18. "PCIE_CAP_FATAL_ERR_DETECTED,Fatal Error Detected. This bit indicates status of Fatal errors detected. Errors are logged in this register regardless of whether error reporting is enabled or not in the Device Control register. For a Multi-Function device.." "0,1" bitfld.long 0x8 17. "PCIE_CAP_NON_FATAL_ERR_DETECTED,Non-Fatal Error Detected. This bit indicates status of Non-fatal errors detected. Errors are logged in this register regardless of whether error reporting is enabled or not in the Device Control register. For a.." "0,1" newline bitfld.long 0x8 16. "PCIE_CAP_CORR_ERR_DETECTED,Correctable Error Detected. This bit indicates status of correctable errors detected. Errors are logged in this register regardless of whether error reporting is enabled or not in the Device Control register. For a.." "0,1" bitfld.long 0x8 15. "PCIE_CAP_INITIATE_FLR,Initiate Function Level Reset (applicable to Endpoints with Function Level Reset Capability set to 1b). A write of 1b initiates Function Level Reset to the Function. The value read by software from this bit is always 0b." "0,1" newline bitfld.long 0x8 12.--14. "PCIE_CAP_MAX_READ_REQ_SIZE,Max_Read_Request_Size. This field sets the maximum Read Request size for the function as a Requester. The function must not generate Read Requests with a size exceeding the set value. Defined encodings for this field are: -.." "0,1,2,3,4,5,6,7" rbitfld.long 0x8 11. "PCIE_CAP_EN_NO_SNOOP,Enable No Snoop. If this bit is set the function is permitted to Set the No Snoop bit in the Requester Attributes of transactions it initiates that do not require hardware enforced cache coherency (see section 2.2.6.5 in PCI Express.." "0,1" newline bitfld.long 0x8 10. "PCIE_CAP_AUX_POWER_PM_EN,Aux Power PM Enable. This bit is derived by sampling the sys_aux_pwr_det input. When set this bit enables a function to draw Aux power independent of PME Aux power. Functions that require Aux power on legacy operating systems.." "0,1" rbitfld.long 0x8 9. "PCIE_CAP_PHANTOM_FUNC_EN,Phantom Functions Enable. This bit in combination with the 10-Bit Tag Requester Enable bit in the Device Control 2 register determines how many Tag field bits a Requester is permitted to use. When the 10-Bit Tag Requester.." "0,1" newline rbitfld.long 0x8 8. "PCIE_CAP_EXT_TAG_EN,Extended Tag Field Enable. This bit in combination with the 10-Bit Tag Requester Enable bit in the Device Control 2 register determines how many Tag field bits a Requester is permitted to use. When the 10-Bit Tag Requester Enable.." "0,1" bitfld.long 0x8 5.--7. "PCIE_CAP_MAX_PAYLOAD_SIZE_CS,Max_Payload_Size. This field sets maximum TLP payload size for the Function. As a Receiver the Function must handle TLPs as large as the set value. As a Transmitter the Function must not generate TLPs exceeding the set.." "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 4. "PCIE_CAP_EN_REL_ORDER,Enable Relaxed Ordering. If this bit is set the function is permitted to set the Relaxed Ordering bit in the Attributes field of transactions it initiates that do not require strong write ordering (for more details see section.." "0,1" bitfld.long 0x8 3. "PCIE_CAP_UNSUPPORT_REQ_REP_EN,Unsupported Request Reporting Enable. This bit in conjunction with other bits controls the signaling of Unsupported Request Errors by sending error Messages (for more details see section 6.2.5 and section 6.2.6 of PCI.." "0,1" newline bitfld.long 0x8 2. "PCIE_CAP_FATAL_ERR_REPORT_EN,Fatal Error Reporting Enable. This bit in conjunction with other bits controls sending ERR_FATAL Messages (for more details see section 6.2.5 and section 6.2.6 of of PCI Express Base Specification). For a Multi-Function.." "0,1" bitfld.long 0x8 1. "PCIE_CAP_NON_FATAL_ERR_REPORT_EN,Non-Fatal Error Reporting Enable. This bit in conjunction with other bits controls sending ERR_NONFATAL Messages (for more details see section 6.2.5 and Section 6.2.6 of PCI Express Base Specification). For a.." "0,1" newline bitfld.long 0x8 0. "PCIE_CAP_CORR_ERR_REPORT_EN,Correctable Error Reporting Enable. This bit in conjunction with other bits controls sending ERR_COR Messages (for more details see section 6.2.5 section 6.2.6 and section 6.2.10.2 of PCI Express Base Specification). For.." "0,1" line.long 0xC "LINK_CAPABILITIES_REG,Link Capabilities Register. The Link Capabilities register identifies PCI Express Link specific capabilities." hexmask.long.byte 0xC 24.--31. 1. "PCIE_CAP_PORT_NUM,Port Number. This field indicates the PCI Express Port number for the given PCI Express Link. Multi-Function Devices associated with an Upstream Port must report the same value in this field for all functions. Note: The access.." rbitfld.long 0xC 23. "RSVDP_23,Reserved for future use." "0,1" newline bitfld.long 0xC 22. "PCIE_CAP_ASPM_OPT_COMPLIANCE,ASPM Optionality Compliance. This bit must be set to 1b in all functions. Components implemented against certain earlier versions of this specification will have this bit set to 0b. Software is permitted to use the value of.." "0,1" bitfld.long 0xC 21. "PCIE_CAP_LINK_BW_NOT_CAP,Link Bandwidth Notification Capability. A value of 1b indicates support for the Link Bandwidth Notification status and interrupt mechanisms. This capability is required for all Root Ports and Switch Downstream Ports supporting.." "0,1" newline rbitfld.long 0xC 20. "PCIE_CAP_DLL_ACTIVE_REP_CAP,Data Link Layer Link Active Reporting Capable. For a Downstream Port the controller hardwires this bit to 1b if the component supports the optional capability of reporting the DL_Active state of the Data Link Control and.." "0,1" bitfld.long 0xC 19. "PCIE_CAP_SURPRISE_DOWN_ERR_REP_CAP,Surprise Down Error Reporting Capable. For a Downstream Port this bit must be set if the component supports the optional capability of detecting and reporting a Surprise Down error condition. For Upstream Ports and.." "0,1" newline rbitfld.long 0xC 18. "PCIE_CAP_CLOCK_POWER_MAN,Clock Power Management. For Upstream Ports a value of 1b in this bit indicates that the component tolerates the removal of any reference clock(s) via the 'clock request' (CLKREQ#) mechanism when the Link is in the L1 and L2/L3.." "0,1" bitfld.long 0xC 15.--17. "PCIE_CAP_L1_EXIT_LATENCY,L1 Exit Latency. This field indicates the L1 exit latency for the given PCI Express Link. The value reported indicates the length of time this Port requires to complete transition from ASPM L1 to L0. If ASPM L1 is not supported.." "0,1,2,3,4,5,6,7" newline bitfld.long 0xC 12.--14. "PCIE_CAP_L0S_EXIT_LATENCY,L0s Exit Latency. This field indicates the L0s exit latency for the given PCI Express Link. The value reported indicates the length of time this Port requires to complete transition from L0s to L0. If L0s is not supported the.." "0,1,2,3,4,5,6,7" bitfld.long 0xC 10.--11. "PCIE_CAP_ACTIVE_STATE_LINK_PM_SUPPORT,Active State Power Management (ASPM) Support. This field indicates the level of ASPM supported on the given PCI Express Link. For more details on ASPM support requirements see section 5.4.1 of PCI Express Base.." "0,1,2,3" newline hexmask.long.byte 0xC 4.--9. 1. "PCIE_CAP_MAX_LINK_WIDTH,Maximum Link Width. This field indicates the maximum Link width (xN - corresponding to N Lanes) implemented by the component. This value is permitted to exceed the number of Lanes routed to the slot (Downstream Port) adapter.." hexmask.long.byte 0xC 0.--3. 1. "PCIE_CAP_MAX_LINK_SPEED,Max Link Speed. This field indicates the maximum Link speed of the associated Port. The encoded value specifies a bit location in the Supported Link Speeds Vector (in the Link Capabilities 2 register) that corresponds to the.." line.long 0x10 "LINK_CONTROL_LINK_STATUS_REG,Link Control and Link Status Register. This register controls and provides information about PCI Express Link specific parameters." bitfld.long 0x10 31. "PCIE_CAP_LINK_AUTO_BW_STATUS,Link Autonomous Bandwidth Status. This bit is set by hardware to indicate that hardware has autonomously changed Link speed or width without the Port transitioning through DL_Down status for reasons other than to attempt to.." "0,1" bitfld.long 0x10 30. "PCIE_CAP_LINK_BW_MAN_STATUS,Link Bandwidth Management Status. This bit is set by hardware to indicate that either of the following has occurred without the Port transitioning through DL_Down status: - A Link retraining has completed following a write of.." "0,1" newline rbitfld.long 0x10 29. "PCIE_CAP_DLL_ACTIVE,Data Link Layer Link Active. This bit indicates the status of the Data Link Control and Management State Machine. It returns a 1b to indicate the DL_Active state 0b otherwise. This bit must be implemented if the Data Link Layer Link.." "0,1" bitfld.long 0x10 28. "PCIE_CAP_SLOT_CLK_CONFIG,Slot Clock Configuration. This bit indicates that the component uses the same physical reference clock that the platform provides on the connector. If the device uses an independent clock irrespective of the presence of a.." "0,1" newline rbitfld.long 0x10 27. "PCIE_CAP_LINK_TRAINING,Link Training. This read-only bit indicates that the Physical Layer LTSSM is in the Configuration or Recovery state or that 1b was written to the Retrain Link bit but Link training has not yet begun. Hardware clears this bit when.." "0,1" rbitfld.long 0x10 26. "RSVDP_26,Reserved for future use." "0,1" newline hexmask.long.byte 0x10 20.--25. 1. "PCIE_CAP_NEGO_LINK_WIDTH,Negotiated Link Width. This field indicates the negotiated width of the given PCI Express Link. Defined encodings are: -00 0001b: x1 -00 0010b: x2 -00 0100b: x4 -00 1000b: x8 -00 1100b: x12 -01 0000b: x16 -10 0000b: x32 All other.." hexmask.long.byte 0x10 16.--19. 1. "PCIE_CAP_LINK_SPEED,Current Link Speed. This field indicates the negotiated Link speed of the given PCI Express Link. The encoded value specifies a bit location in the Supported Link Speeds Vector (in the Link Capabilities 2 register) that corresponds to.." newline bitfld.long 0x10 14.--15. "PCIE_CAP_DRS_SIGNALING_CONTROL,DRS Signaling Control. Indicates the mechanism used to report reception of a DRS message. Must be implemented for Downstream Ports with the DRS Supported bit Set in the Link Capabilities 2 Register. Encodings are: - 00b:.." "0,1,2,3" rbitfld.long 0x10 12.--13. "RSVDP_12,Reserved for future use." "0,1,2,3" newline bitfld.long 0x10 11. "PCIE_CAP_LINK_AUTO_BW_INT_EN,Link Autonomous Bandwidth Management Interrupt Enable. When set this bit enables the generation of an interrupt to indicate that the Link Autonomous Bandwidth Status bit has been set. The write value is gated with the.." "0,1" bitfld.long 0x10 10. "PCIE_CAP_LINK_BW_MAN_INT_EN,Link Bandwidth Management Interrupt Enable. When set this bit enables the generation of an interrupt to indicate that the Link Bandwidth Management Status bit has been set. The write value is gated with the.." "0,1" newline bitfld.long 0x10 9. "PCIE_CAP_HW_AUTO_WIDTH_DISABLE,Hardware Autonomous Width Disable. When set this bit disables hardware from changing the Link width for reasons other than attempting to correct unreliable Link operation by reducing Link width. For a Multi-Function Device.." "0,1" bitfld.long 0x10 8. "PCIE_CAP_EN_CLK_POWER_MAN,Enable Clock Power Management. Applicable only for Upstream Ports and with form factors that support a 'Clock Request' (CLKREQ#) mechanism this bit operates as follows: - 0b: Clock power management is disabled and device must.." "0,1" newline bitfld.long 0x10 7. "PCIE_CAP_EXTENDED_SYNCH,Extended Synch. When set this bit forces the transmission of additional Ordered Sets when exiting the L0s state (see section 4.2.4.5 of PCI Express Base Specification) and when in the Recovery state (see section 4.2.6.4.1 of PCI.." "0,1" bitfld.long 0x10 6. "PCIE_CAP_COMMON_CLK_CONFIG,Common Clock Configuration. When set this bit indicates that this component and the component at the opposite end of this Link are operating with a distributed common reference clock. A value of 0b indicates that this.." "0,1" newline bitfld.long 0x10 5. "PCIE_CAP_RETRAIN_LINK,Retrain Link. A write of 1b to this bit initiates Link retraining by directing the Physical Layer LTSSM to the Recovery state. If the LTSSM is already in Recovery or Configuration re-entering Recovery is permitted but not required." "0,1" bitfld.long 0x10 4. "PCIE_CAP_LINK_DISABLE,Link Disable. This bit disables the Link by directing the LTSSM to the Disabled state when set; this bit is Reserved on Endpoints PCI Express to PCI/PCI-X bridges and Upstream Ports of Switches. Writes to this bit are immediately.." "0,1" newline bitfld.long 0x10 3. "PCIE_CAP_RCB,Read Completion Boundary (RCB). Root Ports: Indicates the RCB value for the Root Port. Refer to section 2.3.1.1 of PCI Express Base Specification for the definition of the parameter RCB. Defined encodings are: - 0b: 64 byte - 1b: 128 byte.." "0,1" rbitfld.long 0x10 2. "RSVDP_2,Reserved for future use." "0,1" newline bitfld.long 0x10 0.--1. "PCIE_CAP_ACTIVE_STATE_LINK_PM_CONTROL,Active State Power Management (ASPM) Control. This field controls the level of ASPM enabled on the given PCI Express Link. See section 5.4.1.3 of PCI Express Base Specification for requirements on when and how to.." "0,1,2,3" line.long 0x14 "SLOT_CAPABILITIES_REG,Slot Capabilities Register. The Slot Capabilities register identifies PCI Express slot specific capabilities." hexmask.long.word 0x14 19.--31. 1. "PCIE_CAP_PHY_SLOT_NUM,Physical Slot Number. This field indicates the physical slot number attached to this Port. This field must be hardware initialized to a value that assigns a slot number that is unique within the chassis regardless of the form.." bitfld.long 0x14 18. "PCIE_CAP_NO_CMD_CPL_SUPPORT,No Command Completed Support. When set this bit indicates that this slot does not generate software notification when an issued command is completed by the Hot-Plug Controller. This bit is only permitted to be set if the.." "0,1" newline bitfld.long 0x14 17. "PCIE_CAP_ELECTROMECH_INTERLOCK,Electromechanical Interlock Present. When set this bit indicates that an Electromechanical Interlock is implemented on the chassis for this slot. Note: The access attributes of this field are as follows: - Wire: No access." "0,1" bitfld.long 0x14 15.--16. "PCIE_CAP_SLOT_POWER_LIMIT_SCALE,Slot Power Limit Scale. Specifies the scale used for the Slot Power Limit Value (for more details see Section 6.9 of PCI Express Base Specification). Range of Values: - 00b: 1.0x - 01b: 0.1x - 10b: 0.01x - 11b: 0.001x.." "0,1,2,3" newline hexmask.long.byte 0x14 7.--14. 1. "PCIE_CAP_SLOT_POWER_LIMIT_VALUE,Slot Power Limit Value. In combination with the Slot Power Limit Scale value specifies the upper limit on power supplied by the slot (for more detais see Section 6.9 of PCI Express Base Specification) or by other means.." bitfld.long 0x14 6. "PCIE_CAP_HOT_PLUG_CAPABLE,Hot-Plug Capable. When set this bit indicates that this slot is capable of supporting hot-plug operations. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then R/W else R" "0,1" newline bitfld.long 0x14 5. "PCIE_CAP_HOT_PLUG_SURPRISE,Hot-Plug Surprise. When set this bit indicates that an adapter present in this slot might be removed from the system without any prior notification. This is a form factor specific capability. This bit is an indication to the.." "0,1" bitfld.long 0x14 4. "PCIE_CAP_POWER_INDICATOR,Power Indicator Present. When set this bit indicates that a Power Indicator is electrically controlled by the chassis for this slot. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if.." "0,1" newline bitfld.long 0x14 3. "PCIE_CAP_ATTENTION_INDICATOR,Attention Indicator Present. When set this bit indicates that an Attention Indicator is electrically controlled by the chassis. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if.." "0,1" bitfld.long 0x14 2. "PCIE_CAP_MRL_SENSOR,MRL Sensor Present. When set this bit indicates that an MRL Sensor is implemented on the chassis for this slot. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then R/W else R" "0,1" newline bitfld.long 0x14 1. "PCIE_CAP_POWER_CONTROLLER,Power Controller Present. When set this bit indicates that a software programmable Power Controller is implemented for this slot/adapter (depending on form factor). Note: The access attributes of this field are as follows: -.." "0,1" bitfld.long 0x14 0. "PCIE_CAP_ATTENTION_INDICATOR_BUTTON,Attention Button Present. When set this bit indicates that an Attention Button for this slot is electrically controlled by the chassis. Note: The access attributes of this field are as follows: - Wire: No access. -.." "0,1" line.long 0x18 "SLOT_CONTROL_SLOT_STATUS,Slot Control and Status Register. This register controls and provides information about PCI Express Slot specific parameters." hexmask.long.byte 0x18 25.--31. 1. "RSVDP_25,Reserved for future use." bitfld.long 0x18 24. "PCIE_CAP_DLL_STATE_CHANGED,Data Link Layer State Changed. This bit is set when the value reported in the Data Link Layer Link Active bit of the Link Status register is changed. In response to a Data Link Layer State Changed event software must read the.." "0,1" newline rbitfld.long 0x18 23. "PCIE_CAP_ELECTROMECH_INTERLOCK_STATUS,Electromechanical Interlock Status. If an Electromechanical Interlock is implemented this bit indicates the status of the Electromechanical Interlock. Defined encodings are: - 0b: Electromechanical Interlock.." "0,1" rbitfld.long 0x18 22. "PCIE_CAP_PRESENCE_DETECT_STATE,Presence Detect State. This bit indicates the presence of an adapter in the slot reflected by the logical 'OR' of the Physical Layer in-band presence detect mechanism and if present any out-of-band presence detect.." "0,1" newline rbitfld.long 0x18 21. "PCIE_CAP_MRL_SENSOR_STATE,MRL Sensor State. This bit reports the status of the MRL sensor if implemented. Defined encodings are: - 0b: MRL Closed - 1b: MRL Open" "0,1" bitfld.long 0x18 20. "PCIE_CAP_CMD_CPLD,Command Completed. If Command Completed notification is supported (if the No Command Completed Support bit in the Slot Capabilities register is 0b) this bit is set when a hot-plug command has completed and the Hot-Plug Controller is.." "0,1" newline bitfld.long 0x18 19. "PCIE_CAP_PRESENCE_DETECTED_CHANGED,Presence Detect Changed. This bit is set when the value reported in the Presence Detect State bit is changed." "0,1" bitfld.long 0x18 18. "PCIE_CAP_MRL_SENSOR_CHANGED,MRL Sensor Changed. If an MRL sensor is implemented this bit is set when a MRL Sensor state change is detected. If an MRL sensor is not implemented this bit must not be set." "0,1" newline bitfld.long 0x18 17. "PCIE_CAP_POWER_FAULT_DETECTED,Power Fault Detected. If a Power Controller that supports power fault detection is implemented this bit issSet when the Power Controller detects a power fault at this slot. Note: Depending on hardware capability it is.." "0,1" bitfld.long 0x18 16. "PCIE_CAP_ATTENTION_BUTTON_PRESSED,Attention Button Pressed. If an Attention Button is implemented this bit is set when the attention button is pressed. If an Attention Button is not supported this bit must not be set." "0,1" newline rbitfld.long 0x18 14.--15. "RSVDP_14,Reserved for future use." "0,1,2,3" bitfld.long 0x18 12. "PCIE_CAP_DLL_STATE_CHANGED_EN,Data Link Layer State Changed Enable. If the Data Link Layer Link Active Reporting capability is 1b this bit enables software notification when Data Link Layer Link Active bit is changed. If the Data Link Layer Link Active.." "0,1" newline bitfld.long 0x18 11. "PCIE_CAP_ELECTROMECH_INTERLOCK_CTRL,Electromechanical Interlock Control. If an Electromechanical Interlock is implemented a write of 1b to this bit causes the state of the interlock to toggle. A write of 0b to this bit has no effect. A read of this bit.." "0,1" bitfld.long 0x18 10. "PCIE_CAP_POWER_CONTROLLER_CTRL,Power Controller Control. If a Power Controller is implemented this bit when written sets the power state of the slot per the defined encodings. Reads of this bit must reflect the value from the latest write even if the.." "0,1" newline bitfld.long 0x18 8.--9. "PCIE_CAP_POWER_INDICATOR_CTRL,Power Indicator Control. If a Power Indicator is implemented writes to this field set the Power Indicator to the written state. Reads of this field must reflect the value from the latest write even if the corresponding.." "0,1,2,3" bitfld.long 0x18 6.--7. "PCIE_CAP_ATTENTION_INDICATOR_CTRL,Attention Indicator Control. If an Attention Indicator is implemented writes to this field set the Attention Indicator to the written state. Reads of this field must reflect the value from the latest write even if the.." "0,1,2,3" newline bitfld.long 0x18 5. "PCIE_CAP_HOT_PLUG_INT_EN,Hot-Plug Interrupt Enable. When set this bit enables generation of an interrupt on enabled hot-plug events. If the Hot Plug Capable bit in the Slot Capabilities register is clear this bit is permitted to be read-only with a.." "0,1" bitfld.long 0x18 4. "PCIE_CAP_CMD_CPL_INT_EN,Command Completed Interrupt Enable. If Command Completed notification is supported (if the No Command Completed Support bit in the Slot Capabilities register is 0b) when set this bit enables software notification when a hot-plug.." "0,1" newline bitfld.long 0x18 3. "PCIE_CAP_PRESENCE_DETECT_CHANGE_EN,Presence Detect Changed Enable. When set this bit enables software notification on a presence detect changed event (for more details see Section 6.7.3 of PCI Express Base Specification). If the Hot-Plug Capable bit in.." "0,1" bitfld.long 0x18 2. "PCIE_CAP_MRL_SENSOR_CHANGED_EN,MRL Sensor Changed Enable. When set this bit enables software notification on a MRL sensor changed event (for more details see Section 6.7.3 of PCI Express Base Specification). If the MRL Sensor Present bit in the Slot.." "0,1" newline bitfld.long 0x18 1. "PCIE_CAP_POWER_FAULT_DETECTED_EN,Power Fault Detected Enable. When set this bit enables software notification on a power fault event (for more details see Section 6.7.3 of PCI Express Base Specification). If a Power Controller that supports power fault.." "0,1" bitfld.long 0x18 0. "PCIE_CAP_ATTENTION_BUTTON_PRESSED_EN,Attention Button Pressed Enable. When set to 1b this bit enables software notification on an attention button pressed event (for more details see Section 6.7.3 of PCI Express Base Specification). If the Attention.." "0,1" line.long 0x1C "ROOT_CONTROL_ROOT_CAPABILITIES_REG,Root Control and Capabilities Register. This register controls PCI Express Root Complex specific parameters and identifies PCI Express Root Port specific capabilities." hexmask.long.word 0x1C 17.--31. 1. "RSVDP_17,Reserved for future use." bitfld.long 0x1C 16. "PCIE_CAP_CRS_SW_VISIBILITY,CRS Software Visibility Capable. For a description of this standard PCIe register field see the PCI Express Base Specification. CRS Software Visibility. When set this bit indicates that the Root Port is capable of returning.." "0,1" newline hexmask.long.word 0x1C 5.--15. 1. "RSVDP_5,Reserved for future use." bitfld.long 0x1C 4. "PCIE_CAP_CRS_SW_VISIBILITY_EN,CRS Software Visibility Enable. When set this bit enables the Root Port to return Configuration Request Retry Status (CRS) Completion Status to software (for more details see section 2.3.1 of PCI Express Base.." "0,1" newline bitfld.long 0x1C 3. "PCIE_CAP_PME_INT_EN,PME Interrupt Enable. When set this bit enables PME interrupt generation upon receipt of a PME Message as reflected in the PME Status bit (for more details see Table 7-29 of PCI Express Base Specification). A PME interrupt is also.." "0,1" bitfld.long 0x1C 2. "PCIE_CAP_SYS_ERR_ON_FATAL_ERR_EN,System Error on Fatal Error Enable. If set this bit indicates that a System Error should be generated if a Fatal error (ERR_FATAL) is reported by any of the devices in the Hierarchy Domain associated with this Root Port.." "0,1" newline bitfld.long 0x1C 1. "PCIE_CAP_SYS_ERR_ON_NON_FATAL_ERR_EN,System Error on Non-Fatal Error Enable. If set this bit indicates that a System Error should be generated if a Non-fatal error (ERR_NONFATAL) is reported by any of the devices in the Hierarchy Domain associated with.." "0,1" bitfld.long 0x1C 0. "PCIE_CAP_SYS_ERR_ON_CORR_ERR_EN,System Error on Correctable Error Enable. If set this bit indicates that a System Error should be generated if a correctable error (ERR_COR) is reported by any of the devices in the Hierarchy Domain associated with this.." "0,1" line.long 0x20 "ROOT_STATUS_REG,Root Status Register. The Root Status register provides information about PCI Express device specific parameters." hexmask.long.word 0x20 18.--31. 1. "RSVDP_18,Reserved for future use." rbitfld.long 0x20 17. "PCIE_CAP_PME_PENDING,PME Pending. This bit indicates that another PME is pending when the PME Status bit is s et. When the PME Status bit is cleared by software; the PME is delivered by hardware by setting the PME Status bit again and updating the PME.." "0,1" newline bitfld.long 0x20 16. "PCIE_CAP_PME_STATUS,PME Status. This bit indicates that PME was asserted by the PME Requester indicated in the PME Requester ID field. Subsequent PMEs are kept pending until the status register is cleared by software by writing a 1b." "0,1" hexmask.long.word 0x20 0.--15. 1. "PCIE_CAP_PME_REQ_ID,PME Requester ID. This field indicates the PCI Requester ID of the last PME Requester. This field is only valid when the PME Status bit is set." line.long 0x24 "DEVICE_CAPABILITIES2_REG,Device Capabilities 2 Register." bitfld.long 0x24 31. "PCIE_CAP_FRS_SUPPORTED,FRS Supported. When set indicates support for the optional Function Readiness Status (FRS) capability. Must be set for all Functions that support generation or reception capabilities of FRS Messages. Must not be set by Switch.." "0,1" hexmask.long.byte 0x24 24.--30. 1. "RSVDP_24,Reserved for future use." newline bitfld.long 0x24 22.--23. "PCIE_CAP2_CFG_MAX_END2END_TLP_PRFXS,Max End-End TLP Prefixes. Indicates the maximum number of End-End TLP Prefixes supported by this Function. For more details see Section 2.2.10.2 of PCI Express Base Specification. Values are: - 01b: 1 End-End TLP.." "0,1,2,3" bitfld.long 0x24 21. "PCIE_CAP2_CFG_END2END_TLP_PRFX_SUPPORT,End-End TLP Prefix Supported. Indicates whether End-End TLP Prefix support is offered by a Function. Values are: - 0b: No Support - 1b: Support is provided to receive TLPs containing End-End TLP Prefixes. All Ports.." "0,1" newline bitfld.long 0x24 20. "PCIE_CAP2_CFG_EXTND_FMT_SUPPORT,Extended Fmt Field Supported. If set the Function supports the 3-bit definition of the Fmt field. If clear the Function supports a 2-bit definition of the Fmt field. For more details see section 2.2 of PCI Express Base.." "0,1" rbitfld.long 0x24 17. "PCIE_CAP2_10_BIT_TAG_REQ_SUPPORT,10-Bit Tag Requester Supported. If this bit is set the Function supports 10-Bit Tag Requester capability; otherwise the Function does not. This bit must not be set if the 10-Bit Tag Completer Supported bit is clear." "0,1" newline rbitfld.long 0x24 16. "PCIE_CAP2_10_BIT_TAG_COMP_SUPPORT,10-Bit Tag Completer Supported. If this bit is set the Function supports 10-Bit Tag Completer capability; otherwise the Function does not. For more details see section 2.2.6.2. of PCI Express Base Specification." "0,1" rbitfld.long 0x24 13. "PCIE_CAP_TPH_CMPLT_SUPPORT_1,TPH Completer Supported Bit 1." "0,1" newline rbitfld.long 0x24 12. "PCIE_CAP_TPH_CMPLT_SUPPORT_0,TPH Completer Supported Bit 0. Value of this bit along with TPH Completer Supported Bit 1 indicates Completer support for TPH or Extended TPH. Applicable only to Root Ports and Endpoints. For all other Functions this field.." "0,1" bitfld.long 0x24 11. "PCIE_CAP_LTR_SUPP,LTR Mechanism Supported. A value of 1b indicates support for the optional Latency Tolerance Reporting (LTR) mechanism. Root Ports Switches and Endpoints are permitted to implement this capability. For a Multi-Function Device associated.." "0,1" newline rbitfld.long 0x24 10. "PCIE_CAP_NO_RO_EN_PR2PR_PAR,No RO-enabled PR-PR Passing. If this bit is set the routing element never carries out the passing permitted by Table 2-39 of PCI Express Base Specification entry A2b that is associated with the Relaxed Ordering Attribute.." "0,1" rbitfld.long 0x24 9. "PCIE_CAP_128_CAS_CPL_SUPP,128-bit CAS Completer Supported. Applicable to Functions with Memory Space BARs as well as all Root Ports; must be 0b otherwise. This bit must be set to 1b if the Function supports this optional capability. For more details see.." "0,1" newline rbitfld.long 0x24 8. "PCIE_CAP_64_ATOMIC_CPL_SUPP,64-bit AtomicOp Completer Supported. Applicable to Functions with Memory Space BARs as well as all Root Ports; must be 0b otherwise. Includes FetchAdd Swap and CAS AtomicOps. This bit must be set to 1b if the Function.." "0,1" rbitfld.long 0x24 7. "PCIE_CAP_32_ATOMIC_CPL_SUPP,32-bit AtomicOp Completer Supported. Applicable to Functions with Memory Space BARs as well as all Root Ports; must be 0b otherwise. Includes FetchAdd Swap and CAS AtomicOps. This bit must be set to 1b if the Function.." "0,1" newline rbitfld.long 0x24 6. "PCIE_CAP_ATOMIC_ROUTING_SUPP,AtomicOp Routing Supported. Applicable only to Switch Upstream Ports Switch Downstream Ports and Root Ports; must be 0b for other Function types. This bit must be set to 1b if the Port supports this optional capability. For.." "0,1" rbitfld.long 0x24 5. "PCIE_CAP_ARI_FORWARD_SUPPORT,ARI Forwarding Supported. Applicable only to Switch Downstream Ports and Root Ports; must be 0b for other Function types. This bit must be set to 1b if a Switch Downstream Port or Root Port supports this optional capability." "0,1" newline rbitfld.long 0x24 4. "PCIE_CAP_CPL_TIMEOUT_DISABLE_SUPPORT,Completion Timeout Disable Supported. A value of 1b indicates support for the Completion Timeout Disable mechanism. The Completion Timeout Disable mechanism is required for Endpoints that issue Requests on their own.." "0,1" hexmask.long.byte 0x24 0.--3. 1. "PCIE_CAP_CPL_TIMEOUT_RANGE,Completion Timeout Ranges Supported. This field indicates device Function support for the optional Completion Timeout programmability mechanism. This mechanism allows system software to modify the Completion Timeout value. This.." line.long 0x28 "DEVICE_CONTROL2_DEVICE_STATUS2_REG,Device Control 2 and Status 2 Register." hexmask.long.word 0x28 16.--31. 1. "RSVDP_16,Reserved for future use." bitfld.long 0x28 15. "PCIE_CTRL2_CFG_END2END_TLP_PFX_BLCK,End-End TLP Prefix Blocking. Controls whether the routing function is permitted to forward TLPs containing an End-End TLP Prefix. Values are: - 0b: Forwarding Enabled - Function is permitted to send TLPs with End-End.." "0,1" newline rbitfld.long 0x28 11. "RSVDP_11,Reserved for future use." "0,1" bitfld.long 0x28 10. "PCIE_CAP_LTR_EN,LTR Mechanism Enable. When set to 1b this bit enables Upstream Ports to send LTR messages and Downstream Ports to process LTR Messages. For a Multi-Function Device associated with an Upstream Port of a device that implements LTR the bit.." "0,1" newline rbitfld.long 0x28 5. "PCIE_CAP_ARI_FORWARD_SUPPORT_CS,ARI Forwarding Enable. When set the Downstream Port disables its traditional Device Number field being 0 enforcement when turning a Type 1 Configuration Request into a Type 0 Configuration Request permitting access to.." "0,1" bitfld.long 0x28 4. "PCIE_CAP_CPL_TIMEOUT_DISABLE,Completion Timeout Disable. When set this bit disables the Completion Timeout mechanism. This bit is required for all Functions that support the Completion Timeout Disable Capability. Functions that do not support this.." "0,1" newline hexmask.long.byte 0x28 0.--3. 1. "PCIE_CAP_CPL_TIMEOUT_VALUE,Completion Timeout Value. In device Functions that support Completion Timeout programmability this field allows system software to modify the Completion Timeout value. This field is applicable to Root Ports Endpoints that.." line.long 0x2C "LINK_CAPABILITIES2_REG,Link Capabilities 2 Register." bitfld.long 0x2C 31. "DRS_SUPPORTED,DRS Supported. When set indicates support for the optional Device Readiness Status (DRS) capability. Must be Set in Downstream Ports that support DRS. Must be Set in Downstream Ports that support FRS. For Upstream Ports that support DRS.." "0,1" hexmask.long.byte 0x2C 25.--30. 1. "RSVDP_25,Reserved for future use." newline hexmask.long.word 0x2C 9.--22. 1. "RSVDP_9,Reserved for future use." rbitfld.long 0x2C 8. "PCIE_CAP_CROSS_LINK_SUPPORT,Crosslink Supported. When set to 1b this bit indicates that the associated Port supports crosslinks (for more details see section 4.2.6.3.1 of PCI Express Base Specification). When set to 0b on a Port that supports Link.." "0,1" newline hexmask.long.byte 0x2C 1.--7. 1. "PCIE_CAP_SUPPORT_LINK_SPEED_VECTOR,Supported Link Speeds Vector. This field indicates the supported Link speed(s) of the associated Port. For each bit a value of 1b indicates that the corresponding Link speed is supported; otherwise the Link speed is.." rbitfld.long 0x2C 0. "RSVDP_0,Reserved for future use." "0,1" line.long 0x30 "LINK_CONTROL2_LINK_STATUS2_REG,Link Control 2 and Status 2 Register." bitfld.long 0x30 31. "DRS_MESSAGE_RECEIVED,DRS Message Received. This bit must be set whenever the Port receives a DRS Message. This bit must be cleared in DL_Down. This bit must be implemented in any Downstream Port where the DRS Supported bit is Set in the Link Capabilities.." "0,1" rbitfld.long 0x30 28.--30. "DOWNSTREAM_COMPO_PRESENCE,Downstream Component Presence. This field indicates the presence and DRS status for the Downstream Component if any connected to the Link; defined values are: - 000b: Link Down - Presence Not Determined - 001b: Link Down -.." "0,1,2,3,4,5,6,7" newline rbitfld.long 0x30 26.--27. "RSVDP_26,Reserved for future use." "0,1,2,3" bitfld.long 0x30 21. "PCIE_CAP_LINK_EQ_REQ,Link Equalization Request 8.0 GT/s. This bit is set by hardware to request the 8.0 GT/s Link equalization process to be performed on the Link. For more details see sections 4.2.3 and 4.2.6.4.2 of PCI Express Base Specification. For.." "0,1" newline rbitfld.long 0x30 20. "PCIE_CAP_EQ_CPL_P3,EEqualization 8.0 GT/s Phase 3 Successful. When set to 1b this bit indicates that Phase 3 of the 8.0 GT/s Transmitter Equalization procedure has successfully completed. Details of the Transmitter Equalization process and when this bit.." "0,1" rbitfld.long 0x30 19. "PCIE_CAP_EQ_CPL_P2,Equalization 8.0 GT/s Phase 2 Successful. When set to 1b this bit indicates that Phase 2 of the 8.0 GT/s Transmitter Equalization procedure has successfully completed. Details of the Transmitter Equalization process and when this bit.." "0,1" newline rbitfld.long 0x30 18. "PCIE_CAP_EQ_CPL_P1,Equalization 8.0 GT/s Phase 1 Successful. When set to 1b this bit indicates that Phase 1 of the 8.0 GT/s Transmitter Equalization procedure has successfully completed. Details of the Transmitter Equalization process and when this bit.." "0,1" rbitfld.long 0x30 17. "PCIE_CAP_EQ_CPL,Equalization 8.0 GT/s Complete. When set to 1b this bit indicates that the Transmitter Equalization procedure at the 8.0 GT/s data rate has completed. Details of the Transmitter Equalization process and when this bit needs to be set to.." "0,1" newline rbitfld.long 0x30 16. "PCIE_CAP_CURR_DEEMPHASIS,Current De-emphasis Level. When the Link is operating at 5.0 GT/s speed this bit reflects the level of de-emphasis. Encodings: - 1b: -3.5 dB - 0b: -6 dB The value in this bit is undefined when the Link is not operating at 5.0.." "0,1" hexmask.long.byte 0x30 12.--15. 1. "PCIE_CAP_COMPLIANCE_PRESET,Compliance Preset/De-emphasis. For 8.0 GT/s and higher Data Rate: This field sets the Transmitter Preset in Polling.Compliance state if the entry occurred due to the Enter Compliance bit being 1b. The encodings are defined in.." newline bitfld.long 0x30 11. "PCIE_CAP_COMPLIANCE_SOS,Compliance SOS. When set to 1b the LTSSM is required to send SKP Ordered Sets between sequences when sending the Compliance Pattern or Modified Compliance Pattern. For a Multi-Function Device associated with an Upstream Port the.." "0,1" bitfld.long 0x30 10. "PCIE_CAP_ENTER_MODIFIED_COMPLIANCE,Enter Modified Compliance. When this bit is set to 1b the device transmits Modified Compliance Pattern if the LTSSM enters Polling.Compliance substate. Components that support only the 2.5 GT/s speed are permitted to.." "0,1" newline bitfld.long 0x30 7.--9. "PCIE_CAP_TX_MARGIN,Transmit Margin - This field controls the value of the non-deemphasized voltage level at the Transmitter pins. This field is reset to 000b on entry to the LTSSM Polling.Configuration substate (see Chapter 4 of PCI Express Base.." "0,1,2,3,4,5,6,7" bitfld.long 0x30 6. "PCIE_CAP_SEL_DEEMPHASIS,Selectable De-emphasis. When the Link is operating at 5.0 GT/s speed this bit is used to control the transmit de-emphasis of the link in specific situations. For more details see section 4.2.6 of PCI Express Base Specification." "0,1" newline bitfld.long 0x30 5. "PCIE_CAP_HW_AUTO_SPEED_DISABLE,Hardware Autonomous Speed Disable. When set this bit disables hardware from changing the Link speed for device-specific reasons other than attempting to correct unreliable Link operation by reducing Link speed. Initial.." "0,1" bitfld.long 0x30 4. "PCIE_CAP_ENTER_COMPLIANCE,Enter Compliance. Software is permitted to force a Link to enter Compliance mode (at the speed indicated in the Target Link Speed field and the de-emphasis/preset level indicated by the Compliance Preset/De-emphasis field) by.." "0,1" newline hexmask.long.byte 0x30 0.--3. 1. "PCIE_CAP_TARGET_LINK_SPEED,Target Link Speed. For Downstream Ports this field sets an upper limit on Link operational speed by restricting the values advertised by the Upstream component in its training sequences. The encoded value specifies a bit.." tree.end tree "PF0_AER_CAP (PF Advanced Error Reporting Capability Structure)" group.long (0x0+0x100)++0x1B line.long 0x0 "AER_EXT_CAP_HDR_OFF,Advanced Error Reporting Extended Capability Header. For a description of this standard PCIe register. see the PCI Express Specification." hexmask.long.word 0x0 20.--31. 1. "NEXT_OFFSET,Next Capability Offset. For a description of this standard PCIe register field see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky).." hexmask.long.byte 0x0 16.--19. 1. "CAP_VERSION,Capability Version. For a description of this standard PCIe register field see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else.." hexmask.long.word 0x0 0.--15. 1. "CAP_ID,AER Extended Capability ID. For a description of this standard PCIe register field see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else.." line.long 0x4 "UNCORR_ERR_STATUS_OFF,Uncorrectable Error Status Register. For a description of this standard PCIe register. see the PCI Express Specification." hexmask.long.byte 0x4 27.--31. 1. "RSVDP_27,Reserved for future use." bitfld.long 0x4 25. "TLP_PRFX_BLOCKED_ERR_STATUS,TLP Prefix Blocked Error Status. For a description of this standard PCIe register field see the PCI Express Specification. Note: Not supported." "0,1" rbitfld.long 0x4 23. "RSVDP_23,Reserved for future use." "0,1" newline bitfld.long 0x4 22. "INTERNAL_ERR_STATUS,Uncorrectable Internal Error Status. For a description of this standard PCIe register field see the PCI Express Specification. The controller sets this bit when your application asserts app_err_bus[9]. It does not set this bit when.." "0,1" bitfld.long 0x4 20. "UNSUPPORTED_REQ_ERR_STATUS,Unsupported Request Error Status. For a description of this standard PCIe register field see the PCI Express Specification." "0,1" bitfld.long 0x4 19. "ECRC_ERR_STATUS,ECRC Error Status. For a description of this standard PCIe register field see the PCI Express Specification. Note:If CX_ECRC_ENABLE=0 the register field always reads 0." "0,1" newline bitfld.long 0x4 18. "MALF_TLP_ERR_STATUS,Malformed TLP Status. For a description of this standard PCIe register field see the PCI Express Specification." "0,1" bitfld.long 0x4 17. "REC_OVERFLOW_ERR_STATUS,Receiver Overflow Status. For a description of this standard PCIe register field see the PCI Express Specification." "0,1" bitfld.long 0x4 16. "UNEXP_CMPLT_ERR_STATUS,Unexpected Completion Status. For a description of this standard PCIe register field see the PCI Express Specification." "0,1" newline bitfld.long 0x4 15. "CMPLT_ABORT_ERR_STATUS,Completer Abort Status. For a description of this standard PCIe register field see the PCI Express Specification." "0,1" bitfld.long 0x4 14. "CMPLT_TIMEOUT_ERR_STATUS,Completion Timeout Status. For a description of this standard PCIe register field see the PCI Express Specification." "0,1" bitfld.long 0x4 13. "FC_PROTOCOL_ERR_STATUS,Flow Control Protocol Error Status. For a description of this standard PCIe register field see the PCI Express Specification." "0,1" newline bitfld.long 0x4 12. "POIS_TLP_ERR_STATUS,Poisoned TLP Status. For a description of this standard PCIe register field see the PCI Express Specification." "0,1" hexmask.long.byte 0x4 6.--11. 1. "RSVDP_6,Reserved for future use." bitfld.long 0x4 5. "SURPRISE_DOWN_ERR_STATUS,Surprise Down Error Status (Optional). For a description of this standard PCIe register field see the PCI Express Specification." "0,1" newline bitfld.long 0x4 4. "DL_PROTOCOL_ERR_STATUS,Data Link Protocol Error Status. For a description of this standard PCIe register field see the PCI Express Specification." "0,1" hexmask.long.byte 0x4 0.--3. 1. "RSVDP_0,Reserved for future use." line.long 0x8 "UNCORR_ERR_MASK_OFF,Uncorrectable Error Mask Register. For a description of this standard PCIe register. see the PCI Express Specification." hexmask.long.byte 0x8 27.--31. 1. "RSVDP_27,Reserved for future use." bitfld.long 0x8 25. "TLP_PRFX_BLOCKED_ERR_MASK,TLP Prefix Blocked Error Mask. For a description of this standard PCIe register field see the PCI Express Specification. Note: Not supported. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi:.." "0,1" rbitfld.long 0x8 23. "RSVDP_23,Reserved for future use." "0,1" newline bitfld.long 0x8 22. "INTERNAL_ERR_MASK,Uncorrectable Internal Error Mask (Optional). For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." "0,1" rbitfld.long 0x8 21. "ACS_VIOLATION_MASK,ACS Violation Mask. Setting the ACS Violation Mask bit disables error logging and signaling for ACS Violation errors. The bit is Read-Only Zero for upstream ports when ACS P2P Egress Control Enable is not set. For a description of.." "0,1" bitfld.long 0x8 20. "UNSUPPORTED_REQ_ERR_MASK,Unsupported Request Error Mask. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." "0,1" newline bitfld.long 0x8 19. "ECRC_ERR_MASK,ECRC Error Mask (Optional). For a description of this standard PCIe register field see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W (sticky) Note: This register.." "0,1" bitfld.long 0x8 18. "MALF_TLP_ERR_MASK,Malformed TLP Mask. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." "0,1" bitfld.long 0x8 17. "REC_OVERFLOW_ERR_MASK,Receiver Overflow Mask (Optional). For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." "0,1" newline bitfld.long 0x8 16. "UNEXP_CMPLT_ERR_MASK,Unexpected Completion Mask. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." "0,1" bitfld.long 0x8 15. "CMPLT_ABORT_ERR_MASK,Completer Abort Error Mask (Optional). For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." "0,1" bitfld.long 0x8 14. "CMPLT_TIMEOUT_ERR_MASK,Completion Timeout Error Mask. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." "0,1" newline bitfld.long 0x8 13. "FC_PROTOCOL_ERR_MASK,Flow Control Protocol Error Mask. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." "0,1" bitfld.long 0x8 12. "POIS_TLP_ERR_MASK,Poisoned TLP Error Mask. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." "0,1" hexmask.long.byte 0x8 6.--11. 1. "RSVDP_6,Reserved for future use." newline rbitfld.long 0x8 5. "SURPRISE_DOWN_ERR_MASK,Surprise Down Error Mask. For a description of this standard PCIe register field see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi:.." "0,1" bitfld.long 0x8 4. "DL_PROTOCOL_ERR_MASK,Data Link Protocol Error Mask. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." "0,1" hexmask.long.byte 0x8 0.--3. 1. "RSVDP_0,Reserved for future use." line.long 0xC "UNCORR_ERR_SEV_OFF,Uncorrectable Error Severity Register. For a description of this standard PCIe register. see the PCI Express Specification." hexmask.long.byte 0xC 27.--31. 1. "RSVDP_27,Reserved for future use." bitfld.long 0xC 25. "TLP_PRFX_BLOCKED_ERR_SEVERITY,TLP Prefix Blocked Error Severity (Optional). For a description of this standard PCIe register field see the PCI Express Specification. Note: Not supported. Note: The access attributes of this field are as follows: - Wire:.." "0,1" rbitfld.long 0xC 24. "ATOMIC_EGRESS_BLOCKED_ERR_SEVERITY,AtomicOp Egress Blocked Severity (Optional). For a description of this standard PCIe register field see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi:.." "0,1" newline rbitfld.long 0xC 23. "RSVDP_23,Reserved for future use." "0,1" bitfld.long 0xC 22. "INTERNAL_ERR_SEVERITY,Uncorrectable Internal Error Severity (Optional). For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." "0,1" bitfld.long 0xC 20. "UNSUPPORTED_REQ_ERR_SEVERITY,Unsupported Request Error Severity. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." "0,1" newline bitfld.long 0xC 19. "ECRC_ERR_SEVERITY,ECRC Error Severity (Optional). For a description of this standard PCIe register field see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W (sticky) Note: This.." "0,1" bitfld.long 0xC 18. "MALF_TLP_ERR_SEVERITY,Malformed TLP Severity. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." "0,1" bitfld.long 0xC 17. "REC_OVERFLOW_ERR_SEVERITY,Receiver Overflow Error Severity (Optional). For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." "0,1" newline bitfld.long 0xC 16. "UNEXP_CMPLT_ERR_SEVERITY,Unexpected Completion Error Severity. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." "0,1" bitfld.long 0xC 15. "CMPLT_ABORT_ERR_SEVERITY,Completer Abort Error Severity (Optional). For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." "0,1" bitfld.long 0xC 14. "CMPLT_TIMEOUT_ERR_SEVERITY,Completion Timeout Error Severity. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." "0,1" newline bitfld.long 0xC 13. "FC_PROTOCOL_ERR_SEVERITY,Flow Control Protocol Error Severity (Optional). For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." "0,1" bitfld.long 0xC 12. "POIS_TLP_ERR_SEVERITY,Poisoned TLP Severity. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." "0,1" hexmask.long.byte 0xC 6.--11. 1. "RSVDP_6,Reserved for future use." newline rbitfld.long 0xC 5. "SURPRISE_DOWN_ERR_SVRITY,Surprise Down Error Severity (Optional). For a description of this standard PCIe register field see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi:.." "0,1" bitfld.long 0xC 4. "DL_PROTOCOL_ERR_SEVERITY,Data Link Protocol Error Severity. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." "0,1" hexmask.long.byte 0xC 0.--3. 1. "RSVDP_0,Reserved for future use." line.long 0x10 "CORR_ERR_STATUS_OFF,Correctable Error Status Register. For a description of this standard PCIe register. see the PCI Express Specification." hexmask.long.word 0x10 16.--31. 1. "RSVDP_16,Reserved for future use." bitfld.long 0x10 15. "HEADER_LOG_OVERFLOW_STATUS,Header Log Overflow Error Status (Optional). For a description of this standard PCIe register field see the PCI Express Specification." "0,1" bitfld.long 0x10 14. "CORRECTED_INT_ERR_STATUS,Corrected Internal Error Status (Optional). For a description of this standard PCIe register field see the PCI Express Specification." "0,1" newline bitfld.long 0x10 13. "ADVISORY_NON_FATAL_ERR_STATUS,Advisory Non-Fatal Error Status. For a description of this standard PCIe register field see the PCI Express Specification." "0,1" bitfld.long 0x10 12. "RPL_TIMER_TIMEOUT_STATUS,Replay Timer Timeout Status. For a description of this standard PCIe register field see the PCI Express Specification." "0,1" rbitfld.long 0x10 9.--11. "RSVDP_9,Reserved for future use." "0,1,2,3,4,5,6,7" newline bitfld.long 0x10 8. "REPLAY_NO_ROLEOVER_STATUS,REPLAY_NUM Rollover Status. For a description of this standard PCIe register field see the PCI Express Specification." "0,1" bitfld.long 0x10 7. "BAD_DLLP_STATUS,Bad DLLP Status. For a description of this standard PCIe register field see the PCI Express Specification." "0,1" bitfld.long 0x10 6. "BAD_TLP_STATUS,Bad TLP Status. For a description of this standard PCIe register field see the PCI Express Specification." "0,1" newline hexmask.long.byte 0x10 1.--5. 1. "RSVDP_1,Reserved for future use." bitfld.long 0x10 0. "RX_ERR_STATUS,Receiver Error Status (Optional). For a description of this standard PCIe register field see the PCI Express Specification." "0,1" line.long 0x14 "CORR_ERR_MASK_OFF,Correctable Error Mask Register. For a description of this standard PCIe register. see the PCI Express Specification." hexmask.long.word 0x14 16.--31. 1. "RSVDP_16,Reserved for future use." bitfld.long 0x14 15. "HEADER_LOG_OVERFLOW_MASK,Header Log Overflow Error Mask (Optional). For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." "0,1" bitfld.long 0x14 14. "CORRECTED_INT_ERR_MASK,Corrected Internal Error Mask (Optional). For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." "0,1" newline bitfld.long 0x14 13. "ADVISORY_NON_FATAL_ERR_MASK,Advisory Non-Fatal Error Mask. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." "0,1" bitfld.long 0x14 12. "RPL_TIMER_TIMEOUT_MASK,Replay Timer Timeout Mask. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." "0,1" rbitfld.long 0x14 9.--11. "RSVDP_9,Reserved for future use." "0,1,2,3,4,5,6,7" newline bitfld.long 0x14 8. "REPLAY_NO_ROLEOVER_MASK,REPLAY_NUM Rollover Mask. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." "0,1" bitfld.long 0x14 7. "BAD_DLLP_MASK,Bad DLLP Mask. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." "0,1" bitfld.long 0x14 6. "BAD_TLP_MASK,Bad TLP Mask. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." "0,1" newline hexmask.long.byte 0x14 1.--5. 1. "RSVDP_1,Reserved for future use." bitfld.long 0x14 0. "RX_ERR_MASK,Receiver Error Mask (Optional). For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." "0,1" line.long 0x18 "ADV_ERR_CAP_CTRL_OFF,Advanced Error Capabilities and Control Register. For a description of this standard PCIe register. see the PCI Express Specification." hexmask.long.tbyte 0x18 13.--31. 1. "RSVDP_13,Reserved for future use." rbitfld.long 0x18 12. "CTO_PRFX_HDR_LOG_CAP,TLP Prefix Log Present. For a description of this standard PCIe register field see the PCI Express Specification." "0,1" rbitfld.long 0x18 11. "TLP_PRFX_LOG_PRESENT,Completion Timeout Prefix/Header Log Capable. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." "0,1" newline rbitfld.long 0x18 10. "MULTIPLE_HEADER_EN,Multiple Header Recording Enable. For a description of this standard PCIe register field see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R (sticky) Note: This.." "0,1" rbitfld.long 0x18 9. "MULTIPLE_HEADER_CAP,Multiple Header Recording Capable. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." "0,1" bitfld.long 0x18 8. "ECRC_CHECK_EN,ECRC Check Enable. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." "0,1" newline rbitfld.long 0x18 7. "ECRC_CHECK_CAP,ECRC Check Capable. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." "0,1" bitfld.long 0x18 6. "ECRC_GEN_EN,ECRC Generation Enable. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." "0,1" rbitfld.long 0x18 5. "ECRC_GEN_CAP,ECRC Generation Capable. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." "0,1" newline hexmask.long.byte 0x18 0.--4. 1. "FIRST_ERR_POINTER,First Error Pointer. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." rgroup.long (0x1C+0x100)++0xF line.long 0x0 "HDR_LOG_0_OFF,Header Log Register 0. For a description of this standard PCIe register. see the PCI Express Specification." hexmask.long.byte 0x0 24.--31. 1. "FIRST_DWORD_FOURTH_BYTE,Byte 3 of Header log register of First 32 bit Data Word. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." hexmask.long.byte 0x0 16.--23. 1. "FIRST_DWORD_THIRD_BYTE,Byte 2 of Header log register of First 32 bit Data Word. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." hexmask.long.byte 0x0 8.--15. 1. "FIRST_DWORD_SECOND_BYTE,Byte 1 of Header log register of First 32 bit Data Word. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." newline hexmask.long.byte 0x0 0.--7. 1. "FIRST_DWORD_FIRST_BYTE,Byte 0 of Header log register of First 32 bit Data Word. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." line.long 0x4 "HDR_LOG_1_OFF,Header Log Register 1. For a description of this standard PCIe register. see the PCI Express Specification." hexmask.long.byte 0x4 24.--31. 1. "SECOND_DWORD_FOURTH_BYTE,Byte 3 of Header log register of Second 32 bit Data Word. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." hexmask.long.byte 0x4 16.--23. 1. "SECOND_DWORD_THIRD_BYTE,Byte 2 of Header log register of Second 32 bit Data Word. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." hexmask.long.byte 0x4 8.--15. 1. "SECOND_DWORD_SECOND_BYTE,Byte 1 of Header log register of Second 32 bit Data Word. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." newline hexmask.long.byte 0x4 0.--7. 1. "SECOND_DWORD_FIRST_BYTE,Byte 0 of Header log register of Second 32 bit Data Word. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." line.long 0x8 "HDR_LOG_2_OFF,Header Log Register 2. For a description of this standard PCIe register. see the PCI Express Specification." hexmask.long.byte 0x8 24.--31. 1. "THIRD_DWORD_FOURTH_BYTE,Byte 3 of Header log register of Third 32 bit Data Word. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." hexmask.long.byte 0x8 16.--23. 1. "THIRD_DWORD_THIRD_BYTE,Byte 2 of Header log register of Third 32 bit Data Word. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." hexmask.long.byte 0x8 8.--15. 1. "THIRD_DWORD_SECOND_BYTE,Byte 1 of Header log register of Third 32 bit Data Word. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." newline hexmask.long.byte 0x8 0.--7. 1. "THIRD_DWORD_FIRST_BYTE,Byte 0 of Header log register of Third 32 bit Data Word. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." line.long 0xC "HDR_LOG_3_OFF,Header Log Register 3. For a description of this standard PCIe register. see the PCI Express Specification." hexmask.long.byte 0xC 24.--31. 1. "FOURTH_DWORD_FOURTH_BYTE,Byte 3 of Header log register of Fourth 32 bit Data Word. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." hexmask.long.byte 0xC 16.--23. 1. "FOURTH_DWORD_THIRD_BYTE,Byte 2 of Header log register of Fourth 32 bit Data Word. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." hexmask.long.byte 0xC 8.--15. 1. "FOURTH_DWORD_SECOND_BYTE,Byte 1 of Header log register of Fourth 32 bit Data Word. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." newline hexmask.long.byte 0xC 0.--7. 1. "FOURTH_DWORD_FIRST_BYTE,Byte 0 of Header log register of Fourth 32 bit Data Word. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." group.long (0x2C+0x100)++0x7 line.long 0x0 "ROOT_ERR_CMD_OFF,Root Error Command Register. For a description of this standard PCIe register. see the PCI Express Specification." hexmask.long 0x0 3.--31. 1. "RSVDP_3,Reserved for future use." bitfld.long 0x0 2. "FATAL_ERR_REPORTING_EN,Fatal Error Reporting Enable. For a description of this standard PCIe register field see the PCI Express Specification." "0,1" bitfld.long 0x0 1. "NON_FATAL_ERR_REPORTING_EN,Non-Fatal Error Reporting Enable. For a description of this standard PCIe register field see the PCI Express Specification." "0,1" newline bitfld.long 0x0 0. "CORR_ERR_REPORTING_EN,Correctable Error Reporting Enable. For a description of this standard PCIe register field see the PCI Express Specification." "0,1" line.long 0x4 "ROOT_ERR_STATUS_OFF,Root Error Status Register. For a description of this standard PCIe register. see the PCI Express Specification." hexmask.long.byte 0x4 27.--31. 1. "ADV_ERR_INT_MSG_NUM,Advanced Error Interrupt Message Number. For a description of this standard PCIe register field see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN.." hexmask.long.tbyte 0x4 7.--26. 1. "RSVDP_7,Reserved for future use." bitfld.long 0x4 6. "FATAL_ERR_MSG_RX,One or more Fatal Error Messages Received. For a description of this standard PCIe register field see the PCI Express Specification." "0,1" newline bitfld.long 0x4 5. "NON_FATAL_ERR_MSG_RX,One or more Non-Fatal Error Messages Received. For a description of this standard PCIe register field see the PCI Express Specification." "0,1" bitfld.long 0x4 4. "FIRST_UNCORR_FATAL,First Uncorrectable Error is Fatal. For a description of this standard PCIe register field see the PCI Express Specification." "0,1" bitfld.long 0x4 3. "MUL_ERR_FATAL_NON_FATAL_RX,Multiple Fatal or Non-Fatal Errors Received. For a description of this standard PCIe register field see the PCI Express Specification." "0,1" newline bitfld.long 0x4 2. "ERR_FATAL_NON_FATAL_RX,Fatal or Non-Fatal Error Received. For a description of this standard PCIe register field see the PCI Express Specification." "0,1" bitfld.long 0x4 1. "MUL_ERR_COR_RX,Multiple Correctable Errors Received. For a description of this standard PCIe register field see the PCI Express Specification." "0,1" bitfld.long 0x4 0. "ERR_COR_RX,Correctable Error Received. For a description of this standard PCIe register field see the PCI Express Specification." "0,1" rgroup.long (0x34+0x100)++0x13 line.long 0x0 "ERR_SRC_ID_OFF,Error Source Identification Register. For a description of this standard PCIe register. see the PCI Express Specification." hexmask.long.word 0x0 16.--31. 1. "ERR_FATAL_NON_FATAL_SOURCE_ID,Source of Fatal/Non-Fatal Error. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." hexmask.long.word 0x0 0.--15. 1. "ERR_COR_SOURCE_ID,Source of Correctable Error. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." line.long 0x4 "TLP_PREFIX_LOG_1_OFF,TLP Prefix Log Register 1. For a description of this standard PCIe register. see the PCI Express Specification." hexmask.long.byte 0x4 24.--31. 1. "CFG_TLP_PFX_LOG_1_FOURTH_BYTE,Byte 3 of Error TLP Prefix Log 1. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." hexmask.long.byte 0x4 16.--23. 1. "CFG_TLP_PFX_LOG_1_THIRD_BYTE,Byte 2 of Error TLP Prefix Log 1. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." hexmask.long.byte 0x4 8.--15. 1. "CFG_TLP_PFX_LOG_1_SECOND_BYTE,Byte 1 of Error TLP Prefix Log 1. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." newline hexmask.long.byte 0x4 0.--7. 1. "CFG_TLP_PFX_LOG_1_FIRST_BYTE,Byte 0 of Error TLP Prefix Log 1. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." line.long 0x8 "TLP_PREFIX_LOG_2_OFF,TLP Prefix Log Register 2. For a description of this standard PCIe register. see the PCI Express Specification." hexmask.long.byte 0x8 24.--31. 1. "CFG_TLP_PFX_LOG_2_FOURTH_BYTE,Byte 3 Error TLP Prefix Log 2. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." hexmask.long.byte 0x8 16.--23. 1. "CFG_TLP_PFX_LOG_2_THIRD_BYTE,Byte 2 Error TLP Prefix Log 2. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." hexmask.long.byte 0x8 8.--15. 1. "CFG_TLP_PFX_LOG_2_SECOND_BYTE,Byte 1 Error TLP Prefix Log 2. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." newline hexmask.long.byte 0x8 0.--7. 1. "CFG_TLP_PFX_LOG_2_FIRST_BYTE,Byte 0 Error TLP Prefix Log 2. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." line.long 0xC "TLP_PREFIX_LOG_3_OFF,TLP Prefix Log Register 3. For a description of this standard PCIe register. see the PCI Express Specification." hexmask.long.byte 0xC 24.--31. 1. "CFG_TLP_PFX_LOG_3_FOURTH_BYTE,Byte 3 Error TLP Prefix Log 3. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." hexmask.long.byte 0xC 16.--23. 1. "CFG_TLP_PFX_LOG_3_THIRD_BYTE,Byte 2 Error TLP Prefix Log 3. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." hexmask.long.byte 0xC 8.--15. 1. "CFG_TLP_PFX_LOG_3_SECOND_BYTE,Byte 1 Error TLP Prefix Log 3. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." newline hexmask.long.byte 0xC 0.--7. 1. "CFG_TLP_PFX_LOG_3_FIRST_BYTE,Byte 0 Error TLP Prefix Log 3. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." line.long 0x10 "TLP_PREFIX_LOG_4_OFF,TLP Prefix Log Register 4. For a description of this standard PCIe register. see the PCI Express Specification." hexmask.long.byte 0x10 24.--31. 1. "CFG_TLP_PFX_LOG_4_FOURTH_BYTE,Byte 3 Error TLP Prefix Log 4. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." hexmask.long.byte 0x10 16.--23. 1. "CFG_TLP_PFX_LOG_4_THIRD_BYTE,Byte 2 Error TLP Prefix Log 4. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." hexmask.long.byte 0x10 8.--15. 1. "CFG_TLP_PFX_LOG_4_SECOND_BYTE,Byte 1 Error TLP Prefix Log 4. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." newline hexmask.long.byte 0x10 0.--7. 1. "CFG_TLP_PFX_LOG_4_FIRST_BYTE,Byte 0 Error TLP Prefix Log 4. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." tree.end tree "PF0_MSI_CAP (PF MSI Capability Structure)" group.long (0x0+0x50)++0x13 line.long 0x0 "PCI_MSI_CAP_ID_NEXT_CTRL_REG,MSI Capability Header and Message Control Register." hexmask.long.byte 0x0 27.--31. 1. "RSVDP_27,Reserved for future use." bitfld.long 0x0 26. "PCI_MSI_EXT_DATA_EN,Extended Message Data Enable. - If set the function is enabled to provide Extended Message Data. - If clear the function is not enabled to provide Extended Message Data. Note: The access attributes of this field are as follows: -.." "0,1" bitfld.long 0x0 25. "PCI_MSI_EXT_DATA_CAP,Extended Message Data Capable. - If set the function is capable of providing Extended Message Data. - If clear the function does not support providing Extended Message Data. Note: The access attributes of this field are as follows:.." "0,1" newline rbitfld.long 0x0 24. "PCI_PVM_SUPPORT,Per-Vector Masking Capable. - If set the function supports MSI Per-Vector Masking. - If clear the function does not support MSI Per-Vector Masking. This bit must be set if the function is a PF or VF within an SR-IOV Device." "0,1" bitfld.long 0x0 23. "PCI_MSI_64_BIT_ADDR_CAP,64 bit address capable. - If set the function is capable of sending a 64-bit message address. - If clear the function is not capable of sending a 64-bit message address. This bit must be set if the function is a PCI Express.." "0,1" bitfld.long 0x0 20.--22. "PCI_MSI_MULTIPLE_MSG_EN,Multiple Message Enable. Software writes to this field to indicate the number of allocated vectors (equal to or less than the number of requested vectors). The number of allocated vectors is aligned to a power of two. If a.." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 17.--19. "PCI_MSI_MULTIPLE_MSG_CAP,Multiple Message Capable. System software reads this field to determine the number of requested vectors. The number of requested vectors must be aligned to a power of two (if a function requires three vectors it requests four by.." "0,1,2,3,4,5,6,7" bitfld.long 0x0 16. "PCI_MSI_ENABLE,MSI Enable. - If set and the MSI-X Enable bit in the MSI-X Message Control register is clear the function is permitted to use MSI to request service and is prohibited from using INTx interrupts. System configuration software sets this bit.." "0,1" hexmask.long.byte 0x0 8.--15. 1. "PCI_MSI_CAP_NEXT_OFFSET,Next Capability Pointer. This field contains the offset to the next PCI Capability structure or 00h if no other items exist in the linked list of Capabilities. Note: The access attributes of this field are as follows: - Wire: No.." newline hexmask.long.byte 0x0 0.--7. 1. "PCI_MSI_CAP_ID,Capability ID. Indicates the MSI Capability structure. This field returns a Capability ID of 05h indicating that this is an MSI Capability structure." line.long 0x4 "MSI_CAP_OFF_04H_REG,Message Address Register for MSI (Offset 04h)." hexmask.long 0x4 2.--31. 1. "PCI_MSI_CAP_OFF_04H,Message Address - System-specified message address. If the Message Enable bit (bit 16 of the PCI_MSI_CAP_ID_NEXT_CTRL_REG register) is set the contents of this field specify the DWORD-aligned address (Address[31:02]) for the MSI.." rbitfld.long 0x4 0.--1. "RSVDP_0,Reserved for future use." "0,1,2,3" line.long 0x8 "MSI_CAP_OFF_08H_REG,For a function that supports a 32-bit message address. - bits[31:16] of this register represent the Extended Message Data. and - bits[15:0] of this register represent the Message Data For a function that supports a 64-bit message.." hexmask.long.word 0x8 16.--31. 1. "PCI_MSI_CAP_OFF_0AH,For a function that supports a 32-bit message address this field contains Extended Message Data (System-specified message data). For the MSI Capability structures without per-vector masking it must be implemented if the Extended.." hexmask.long.word 0x8 0.--15. 1. "PCI_MSI_CAP_OFF_08H,For a function that supports a 32-bit message address this field contains Message Data (System-specified message data). If the Message Enable bit (bit 16 of the PCI_MSI_CAP_ID_NEXT_CTRL_REG) is set the function sends a DWORD Memory.." line.long 0xC "MSI_CAP_OFF_0CH_REG,For a function that supports a 32-bit message address. this register contains the Mask Bits when the Per-Vector Masking Capable bit (bit 24 of PCI_MSI_CAP_ID_NEXT_CTRL_REG) is set. For a function that supports a 64-bit message.." hexmask.long.word 0xC 16.--31. 1. "PCI_MSI_CAP_OFF_0EH,For a function that supports a 32-bit message address this field contains the upper Mask Bits when the Per Vector Masking Capable bit (PCI_MSI_CAP_ID_NEXT_CTRL_REG.PCI_PVM_SUPPORT) is set. For a function that supports a 64-bit.." hexmask.long.word 0xC 0.--15. 1. "PCI_MSI_CAP_OFF_0CH,For a function that supports a 32-bit message address this field contains the lower Mask Bits when the Per Vector Masking Capable bit (PCI_MSI_CAP_ID_NEXT_CTRL_REG.PCI_PVM_SUPPORT) is set. For a function that supports a 64-bit.." line.long 0x10 "MSI_CAP_OFF_10H_REG,For a function that supports a 32-bit message address. this register contains the Pending Bits when the Per-Vector Masking Capable bit (bit 24 of PCI_MSI_CAP_ID_NEXT_CTRL_REG) is set. For a function that supports a 64-bit message.." hexmask.long 0x10 0.--31. 1. "PCI_MSI_CAP_OFF_10H,Used for MSI when the Per Vector Masking Capable bit (PCI_MSI_CAP_ID_NEXT_CTRL_REG.PCI_PVM_SUPPORT) is set. For 32-bit contains Pending Bits. For 64-bit contains Mask Bits. For a description of this standard PCIe register field see.." rgroup.long (0x14+0x50)++0x3 line.long 0x0 "MSI_CAP_OFF_14H_REG,Pending Bits Register for MSI. This register is used for a function that supports a 64-bit message address when the Per-Vector Masking Capable bit (bit 24 of PCI_MSI_CAP_ID_NEXT_CTRL_REG) is set." hexmask.long 0x0 0.--31. 1. "PCI_MSI_CAP_OFF_14H,Pending Bits. For each pending bit that is set the function has a pending associated message." tree.end tree "PF0_MSIX_CAP (PF MSI-X Capability Structure)" group.long (0x0+0xB0)++0xB line.long 0x0 "PCI_MSIX_CAP_ID_NEXT_CTRL_REG,MSI-X Capability ID. Next Pointer. Control Registers. For a description of this standard PCIe register. see the PCI Express Base Specification." bitfld.long 0x0 31. "PCI_MSIX_ENABLE,MSI-X Enable. For a description of this standard PCIe register field see the PCI Express Base Specification." "0,1" bitfld.long 0x0 30. "PCI_MSIX_FUNCTION_MASK,Function Mask. For a description of this standard PCIe register field see the PCI Express Base Specification. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" "0,1" rbitfld.long 0x0 27.--29. "RSVDP_27,Reserved for future use." "0,1,2,3,4,5,6,7" newline hexmask.long.word 0x0 16.--26. 1. "PCI_MSIX_TABLE_SIZE,MSI-X Table Size. For a description of this standard PCIe register field see the PCI Express Base Specification. SRIOV Note: All VFs in a single PF have the same value for 'MSI-X Table Size' (PCI_MSIX_TABLE_SIZE field in.." hexmask.long.byte 0x0 8.--15. 1. "PCI_MSIX_CAP_NEXT_OFFSET,MSI-X Next Capability Pointer. For a description of this standard PCIe register field see the PCI Express Base Specification. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN.." hexmask.long.byte 0x0 0.--7. 1. "PCI_MSIX_CAP_ID,MSI-X Capability ID. For a description of this standard PCIe register field see the PCI Express Base Specification." line.long 0x4 "MSIX_TABLE_OFFSET_REG,MSI-X Table Offset and BIR Register. For a description of this standard PCIe register. see the PCI Express Base Specification." hexmask.long 0x4 3.--31. 1. "PCI_MSIX_TABLE_OFFSET,MSI-X Table Offset. For a description of this standard PCIe register field see the PCI Express Base Specification. SRIOV Note: All VFs in a single PF have the same value for 'MSI-X Table Offset' (PCI_MSIX_TABLE_OFFSET field in.." bitfld.long 0x4 0.--2. "PCI_MSIX_BIR,MSI-X Table BAR Indicator Register Field. For a description of this standard PCIe register field see the PCI Express Base Specification. SRIOV Note: All VFs in a single PF have the same value for 'MSI-X Table BAR Indicator Register'.." "0,1,2,3,4,5,6,7" line.long 0x8 "MSIX_PBA_OFFSET_REG,MSI-X PBA Offset and BIR Register. For a description of this standard PCIe register. see the PCI Express Base Specification." hexmask.long 0x8 3.--31. 1. "PCI_MSIX_PBA_OFFSET,MSI-X PBA Offset. For a description of this standard PCIe register field see the PCI Express Base Specification. SRIOV Note: All VFs in a single PF have the same value for 'MSI-X PBA Offset' (PCI_MSIX_PBA_OFFSET field in.." bitfld.long 0x8 0.--2. "PCI_MSIX_PBA_BIR,MSI-X PBA BIR. For a description of this standard PCIe register field see the PCI Express Base Specification. SRIOV Note: All VFs in a single PF have the same value for 'MSI-X PBA BIR' (PCI_MSIX_PBA_BIR field in.." "0,1,2,3,4,5,6,7" tree.end tree "PF0_MSIX_CAP_DBI2 (DBI2 Shadow Block: PF MSI-X Capability Structure)" rgroup.long (0x0+0x10B0)++0x3 line.long 0x0 "SHADOW_PCI_MSIX_CAP_ID_NEXT_CTRL_REG,MSI-X Capability ID. Next Pointer. Control Registers. For a description of this standard PCIe register. see the PCI Express Base Specification." hexmask.long.byte 0x0 27.--31. 1. "RSVDP_27,Reserved for future use." hexmask.long.word 0x0 16.--26. 1. "PCI_MSIX_TABLE_SIZE,MSI-X Table Size in the shadow register. Note: The access attributes of this field are as follows: - Wire: No access - Dbi: No access - Dbi2: if (DBI_RO_WR_EN == 1) then R/W else R Note: This register field is sticky." hexmask.long.word 0x0 0.--15. 1. "RSVDP_0,Reserved for future use." group.long 0x4++0x7 line.long 0x0 "SHADOW_MSIX_TABLE_OFFSET_REG,MSI-X Table Offset and BIR Register. For a description of this standard PCIe register. see the PCI Express Base Specification." hexmask.long 0x0 3.--31. 1. "PCI_MSIX_TABLE_OFFSET,MSI-X Table Offset. For a description of this standard PCIe register field see the PCI Express Base Specification. Note: The access attributes of this field are as follows: - Wire: No access - Dbi: No access - Dbi2: if.." bitfld.long 0x0 0.--2. "PCI_MSIX_BIR,MSI-X Table BAR Indicator Register Field. For a description of this standard PCIe register field see the PCI Express Base Specification. Note: The access attributes of this field are as follows: - Wire: No access - Dbi: No access - Dbi2: if.." "?,?,if,?,?,?,?,?" line.long 0x4 "SHADOW_MSIX_PBA_OFFSET_REG,MSI-X PBA Offset and BIR Register. For a description of this standard PCIe register. see the PCI Express Base Specification." hexmask.long 0x4 3.--31. 1. "PCI_MSIX_PBA_OFFSET,MSI-X PBA Offset. For a description of this standard PCIe register field see the PCI Express Base Specification. Note: The access attributes of this field are as follows: - Wire: No access - Dbi: No access - Dbi2: if (DBI_RO_WR_EN ==.." bitfld.long 0x4 0.--2. "PCI_MSIX_PBA_BIR,MSI-X PBA BIR. For a description of this standard PCIe register field see the PCI Express Base Specification. Note: The access attributes of this field are as follows: - Wire: No access - Dbi: No access - Dbi2: if (DBI_RO_WR_EN == 1 &&.." "?,?,if,?,?,?,?,?" tree.end tree "PF0_DMA_CAP (DMA Port Logic Structure)" group.long (0x0+0xC8000)++0x3 line.long 0x0 "DMA_CTRL_DATA_ARB_PRIOR_OFF,DMA Arbitration Scheme for TRGT1 Interface. This register is used to control traffic priorities among various sources that are delivered to your application through TRGT1 where 0x0 represents the highest priority. - Non-DMA Rx.." hexmask.long.tbyte 0x0 12.--31. 1. "RSVDP_12,Reserved for future use." bitfld.long 0x0 9.--11. "RDBUFF_TRGT_WEIGHT,DMA Read Channel MWr Requests. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 6.--8. "RD_CTRL_TRGT_WEIGHT,DMA Read Channel MRd Requests. For LL element/descriptor access. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" "0,1,2,3,4,5,6,7" bitfld.long 0x0 3.--5. "WR_CTRL_TRGT_WEIGHT,DMA Write Channel MRd Requests. For DMA data requests and LL element/descriptor access. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 0.--2. "RTRGT1_WEIGHT,Non-DMA Rx Requests. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" "0,1,2,3,4,5,6,7" group.long (0x8+0xC8000)++0xB line.long 0x0 "DMA_CTRL_OFF,DMA Number of Channels Register." hexmask.long.byte 0x0 26.--31. 1. "RSVDP_26,Reserved for future use." bitfld.long 0x0 25. "DIS_C2W_CACHE_RD,Disable DMA Read Channels 'completion to memory write' context cache pre-fetch function. Note: For internal debugging only. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" "0,1" newline bitfld.long 0x0 24. "DIS_C2W_CACHE_WR,Disable DMA Write Channels 'completion to memory write' context cache pre-fetch function. Note: For internal debugging only. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" "0,1" hexmask.long.byte 0x0 20.--23. 1. "RSVDP_20,Reserved for future use." newline hexmask.long.byte 0x0 16.--19. 1. "NUM_DMA_RD_CHAN,Number of Read Channels. You can read this register to determine the number of read channels the DMA controller has been configured to support." hexmask.long.word 0x0 4.--15. 1. "RSVDP_4,Reserved for future use." newline hexmask.long.byte 0x0 0.--3. 1. "NUM_DMA_WR_CHAN,Number of Write Channels. You can read this register to determine the number of write channels the DMA controller has been configured to support." line.long 0x4 "DMA_WRITE_ENGINE_EN_OFF,DMA Write Engine Enable Register." hexmask.long.byte 0x4 24.--31. 1. "RSVDP_24,Reserved for future use." bitfld.long 0x4 23. "DMA_WRITE_ENGINE_EN_HSHAKE_CH7,Enable Handshake for DMA Write Engine Channel 7. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" "0,1" newline bitfld.long 0x4 22. "DMA_WRITE_ENGINE_EN_HSHAKE_CH6,Enable Handshake for DMA Write Engine Channel 6. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" "0,1" bitfld.long 0x4 21. "DMA_WRITE_ENGINE_EN_HSHAKE_CH5,Enable Handshake for DMA Write Engine Channel 5. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" "0,1" newline bitfld.long 0x4 20. "DMA_WRITE_ENGINE_EN_HSHAKE_CH4,Enable Handshake for DMA Write Engine Channel 4. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" "0,1" bitfld.long 0x4 19. "DMA_WRITE_ENGINE_EN_HSHAKE_CH3,Enable Handshake for DMA Write Engine Channel 3. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" "0,1" newline bitfld.long 0x4 18. "DMA_WRITE_ENGINE_EN_HSHAKE_CH2,Enable Handshake for DMA Write Engine Channel 2. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" "0,1" bitfld.long 0x4 17. "DMA_WRITE_ENGINE_EN_HSHAKE_CH1,Enable Handshake for DMA Write Engine Channel 1. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" "0,1" newline bitfld.long 0x4 16. "DMA_WRITE_ENGINE_EN_HSHAKE_CH0,Enable Handshake for DMA Write Engine Channel 0. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" "0,1" hexmask.long.word 0x4 1.--15. 1. "RSVDP_1,Reserved for future use." newline bitfld.long 0x4 0. "DMA_WRITE_ENGINE,DMA Write Engine Enable. - 1: Enable - 0: Disable (Soft Reset) For normal operation you must initially set this bit to '1' before any other software setup actions. You do not need to toggle or rewrite to this bit during normal.." "Disable,Enable" line.long 0x8 "DMA_WRITE_DOORBELL_OFF,DMA Write Doorbell Register." bitfld.long 0x8 31. "WR_STOP,Stop. Set in conjunction with the Doorbell Number field. The DMA write channel stops issuing requests sets the channel status to 'Stopped' and asserts the 'Abort' interrupt if it is enabled. Before setting the Stop bit you must read the.." "0,1" hexmask.long 0x8 3.--30. 1. "RSVDP_3,Reserved for future use." newline bitfld.long 0x8 0.--2. "WR_DOORBELL_NUM,Doorbell Number. You must write the channel number to this register to start the DMA write transfer for that channel. The DMA detects a write to this register field even if the value of this field does not change. You do not need to.." "0,1,2,3,4,5,6,7" group.long (0x18+0xC8000)++0x7 line.long 0x0 "DMA_WRITE_CHANNEL_ARB_WEIGHT_LOW_OFF,DMA Write Engine Channel Arbitration Weight Low Register. The 5-bit channel weight (for write channels 0-3) specifies the maximum number of TLP requests that the DMA can issue for that channel before it must return to.." hexmask.long.word 0x0 20.--31. 1. "RSVDP_20,Reserved for future use." hexmask.long.byte 0x0 15.--19. 1. "WRITE_CHANNEL3_WEIGHT,Channel 3 Weight. The weight is initialized by software before ringing the doorbell. The value is used by the channel weighted round robin arbiter to select the next channel read request. A value of '0' means that one TLP is issued.." newline hexmask.long.byte 0x0 10.--14. 1. "WRITE_CHANNEL2_WEIGHT,Channel 2 Weight. The weight is initialized by software before ringing the doorbell. The value is used by the channel weighted round robin arbiter to select the next channel read request. A value of '0' means that one TLP is issued.." hexmask.long.byte 0x0 5.--9. 1. "WRITE_CHANNEL1_WEIGHT,Channel 1 Weight. The weight is initialized by software before ringing the doorbell. The value is used by the channel weighted round robin arbiter to select the next channel read request. A value of '0' means that one TLP is issued.." newline hexmask.long.byte 0x0 0.--4. 1. "WRITE_CHANNEL0_WEIGHT,Channel 0 Weight. The weight is initialized by software before ringing the doorbell. The value is used by the channel weighted round robin arbiter to select the next channel read request. A value of '0' means that one TLP is issued.." line.long 0x4 "DMA_WRITE_CHANNEL_ARB_WEIGHT_HIGH_OFF,DMA Write Engine Channel Arbitration Weight High Register. The 5-bit channel weight (for write channels 4-7) specifies the maximum number of TLP requests that the DMA can issue for that channel before it must return.." hexmask.long.word 0x4 20.--31. 1. "RSVDP_20,Reserved for future use." hexmask.long.byte 0x4 15.--19. 1. "WRITE_CHANNEL7_WEIGHT,Channel 7 Weight. The weight is initialized by software before ringing the doorbell. The value is used by the channel weighted round robin arbiter to select the next channel read request. A value of '0' means that one TLP is issued.." newline hexmask.long.byte 0x4 10.--14. 1. "WRITE_CHANNEL6_WEIGHT,Channel 6 Weight. The weight is initialized by software before ringing the doorbell. The value is used by the channel weighted round robin arbiter to select the next channel read request. A value of '0' means that one TLP is issued.." hexmask.long.byte 0x4 5.--9. 1. "WRITE_CHANNEL5_WEIGHT,Channel 5 Weight. The weight is initialized by software before ringing the doorbell. The value is used by the channel weighted round robin arbiter to select the next channel read request. A value of '0' means that one TLP is issued.." newline hexmask.long.byte 0x4 0.--4. 1. "WRITE_CHANNEL4_WEIGHT,Channel 4 Weight. The weight is initialized by software before ringing the doorbell. The value is used by the channel weighted round robin arbiter to select the next channel read request. A value of '0' means that one TLP is issued.." group.long (0x2C+0xC8000)++0x7 line.long 0x0 "DMA_READ_ENGINE_EN_OFF,DMA Read Engine Enable Register." hexmask.long.byte 0x0 24.--31. 1. "RSVDP_24,Reserved for future use." bitfld.long 0x0 23. "DMA_READ_ENGINE_EN_HSHAKE_CH7,Enable Handshake for DMA Read Engine Channel 7. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" "0,1" newline bitfld.long 0x0 22. "DMA_READ_ENGINE_EN_HSHAKE_CH6,Enable Handshake for DMA Read Engine Channel 6. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" "0,1" bitfld.long 0x0 21. "DMA_READ_ENGINE_EN_HSHAKE_CH5,Enable Handshake for DMA Read Engine Channel 5. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" "0,1" newline bitfld.long 0x0 20. "DMA_READ_ENGINE_EN_HSHAKE_CH4,Enable Handshake for DMA Read Engine Channel 4. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" "0,1" bitfld.long 0x0 19. "DMA_READ_ENGINE_EN_HSHAKE_CH3,Enable Handshake for DMA Read Engine Channel 3. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" "0,1" newline bitfld.long 0x0 18. "DMA_READ_ENGINE_EN_HSHAKE_CH2,Enable Handshake for DMA Read Engine Channel 2. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" "0,1" bitfld.long 0x0 17. "DMA_READ_ENGINE_EN_HSHAKE_CH1,Enable Handshake for DMA Read Engine Channel 1. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" "0,1" newline bitfld.long 0x0 16. "DMA_READ_ENGINE_EN_HSHAKE_CH0,Enable Handshake for DMA Read Engine Channel 0. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" "0,1" hexmask.long.word 0x0 1.--15. 1. "RSVDP_1,Reserved for future use." newline bitfld.long 0x0 0. "DMA_READ_ENGINE,DMA Read Engine Enable. - 1: Enable - 0: Disable (Soft Reset) For normal operation you must initially set this bit to '1' before any other software setup actions. You do not need to toggle or rewrite to this bit during normal operation." "Disable,Enable" line.long 0x4 "DMA_READ_DOORBELL_OFF,DMA Read Doorbell Register." bitfld.long 0x4 31. "RD_STOP,Stop. Set in conjunction with the Doorbell Number field. The DMA read channel stops issuing requests sets the channel status to 'Stopped' and asserts the 'Abort' interrupt if it is enabled. Before setting the Stop bit you must read the channel.." "0,1" hexmask.long 0x4 3.--30. 1. "RSVDP_3,Reserved for future use." newline bitfld.long 0x4 0.--2. "RD_DOORBELL_NUM,Doorbell Number. You must write 0x0 to this register to start the DMA read transfer for that channel. The DMA detects a write to this register field even if the value of this field does not change. The range of this field is 0x0 to 0x7.." "0,1,2,3,4,5,6,7" group.long (0x38+0xC8000)++0x7 line.long 0x0 "DMA_READ_CHANNEL_ARB_WEIGHT_LOW_OFF,DMA Read Engine Channel Arbitration Weight Low Register. The 5-bit channel weight (for read channels 0-3) specifies the maximum number of TLP requests that the DMA can issue for that channel before it must return to.." hexmask.long.word 0x0 20.--31. 1. "RSVDP_20,Reserved for future use." hexmask.long.byte 0x0 15.--19. 1. "READ_CHANNEL3_WEIGHT,Channel 3 Weight. The weight is initialized by software before ringing the doorbell. The value is used by the channel weighted round robin arbiter to select the next channel read request. Note: The access attributes of this field are.." newline hexmask.long.byte 0x0 10.--14. 1. "READ_CHANNEL2_WEIGHT,Channel 2 Weight. The weight is initialized by software before ringing the doorbell. The value is used by the channel weighted round robin arbiter to select the next channel read request. Note: The access attributes of this field are.." hexmask.long.byte 0x0 5.--9. 1. "READ_CHANNEL1_WEIGHT,Channel 1 Weight. The weight is initialized by software before ringing the doorbell. The value is used by the channel weighted round robin arbiter to select the next channel read request. Note: The access attributes of this field are.." newline hexmask.long.byte 0x0 0.--4. 1. "READ_CHANNEL0_WEIGHT,Channel 0 Weight. The weight is initialized by software before ringing the doorbell. The value is used by the channel weighted round robin arbiter to select the next channel read request. Note: The access attributes of this field are.." line.long 0x4 "DMA_READ_CHANNEL_ARB_WEIGHT_HIGH_OFF,DMA Read Engine Channel Arbitration Weight High Register. The 5-bit channel weight (for read channels 4-7) specifies the maximum number of TLP requests that the DMA can issue for that channel before it must return to.." hexmask.long.word 0x4 20.--31. 1. "RSVDP_20,Reserved for future use." hexmask.long.byte 0x4 15.--19. 1. "READ_CHANNEL7_WEIGHT,Channel 7 Weight. The weight is initialized by software before ringing the doorbell. The value is used by the channel weighted round robin arbiter to select the next channel read request. Note: The access attributes of this field are.." newline hexmask.long.byte 0x4 10.--14. 1. "READ_CHANNEL6_WEIGHT,Channel 6 Weight. The weight is initialized by software before ringing the doorbell. The value is used by the channel weighted round robin arbiter to select the next channel read request. Note: The access attributes of this field are.." hexmask.long.byte 0x4 5.--9. 1. "READ_CHANNEL5_WEIGHT,Channel 5 Weight. The weight is initialized by software before ringing the doorbell. The value is used by the channel weighted round robin arbiter to select the next channel read request. Note: The access attributes of this field are.." newline hexmask.long.byte 0x4 0.--4. 1. "READ_CHANNEL4_WEIGHT,Channel 4 Weight. The weight is initialized by software before ringing the doorbell. The value is used by the channel weighted round robin arbiter to select the next channel read request. Note: The access attributes of this field are.." group.long (0x4C+0xC8000)++0x3 line.long 0x0 "DMA_WRITE_INT_STATUS_OFF,DMA Write Interrupt Status Register." hexmask.long.byte 0x0 24.--31. 1. "RSVDP_24,Reserved for future use." hexmask.long.byte 0x0 16.--23. 1. "WR_ABORT_INT_STATUS,Abort Interrupt Status. The DMA write channel has detected an error or you manually stopped the transfer as described in 'Error Handling Assistance by Remote Software'. Each bit corresponds to a DMA channel. Bit [0] corresponds to.." newline hexmask.long.byte 0x0 8.--15. 1. "RSVDP_8,Reserved for future use." hexmask.long.byte 0x0 0.--7. 1. "WR_DONE_INT_STATUS,Done Interrupt Status. The DMA write channel has successfully completed the DMA transfer. For more details see 'Interrupts and Error Handling'. Each bit corresponds to a DMA channel. Bit [0] corresponds to channel 0. - Enabling: For.." group.long (0x54+0xC8000)++0x7 line.long 0x0 "DMA_WRITE_INT_MASK_OFF,DMA Write Interrupt Mask Register." hexmask.long.byte 0x0 24.--31. 1. "RSVDP_24,Reserved for future use." hexmask.long.byte 0x0 16.--23. 1. "WR_ABORT_INT_MASK,Abort Interrupt Mask. Prevents the Abort interrupt status field in the DMA write interrupt status register from asserting the edma_int output. Each bit corresponds to a DMA channel. Bit [0] corresponds to channel 0. Note: The access.." newline hexmask.long.byte 0x0 8.--15. 1. "RSVDP_8,Reserved for future use." hexmask.long.byte 0x0 0.--7. 1. "WR_DONE_INT_MASK,Done Interrupt Mask. Prevents the Done interrupt status field in the DMA write interrupt status register from asserting the edma_int output. Each bit corresponds to a DMA channel. Bit [0] corresponds to channel 0. Note: The access.." line.long 0x4 "DMA_WRITE_INT_CLEAR_OFF,DMA Write Interrupt Clear Register." hexmask.long.byte 0x4 24.--31. 1. "RSVDP_24,Reserved for future use." hexmask.long.byte 0x4 16.--23. 1. "WR_ABORT_INT_CLEAR,Abort Interrupt Clear. You must write a 1'b1 to clear the corresponding bit in the Abort interrupt status field of the DMA write interrupt status register. Each bit corresponds to a DMA channel. Bit [0] corresponds to channel 0. Note:.." newline hexmask.long.byte 0x4 8.--15. 1. "RSVDP_8,Reserved for future use." hexmask.long.byte 0x4 0.--7. 1. "WR_DONE_INT_CLEAR,Done Interrupt Clear. You must write a 1'b1 to clear the corresponding bit in the Done interrupt status field of the DMA write interrupt status register. Each bit corresponds to a DMA channel. Bit [0] corresponds to channel 0. Note:.." rgroup.long (0x5C+0xC8000)++0x3 line.long 0x0 "DMA_WRITE_ERR_STATUS_OFF,DMA Write Error Status Register" hexmask.long.byte 0x0 24.--31. 1. "RSVDP_24,Reserved for future use." hexmask.long.byte 0x0 16.--23. 1. "LINKLIST_ELEMENT_FETCH_ERR_DETECT,Linked List Element Fetch Error Detected. The DMA write channel has received an error response from the AXI bus (or TRGT1 interface when the AXI Bridge is not used) while reading a linked list element from local memory." newline hexmask.long.byte 0x0 8.--15. 1. "RSVDP_8,Reserved for future use." hexmask.long.byte 0x0 0.--7. 1. "APP_READ_ERR_DETECT,Application Read Error Detected. The DMA write channel has received an error response from the AXI bus (or TRGT1 interface when the AXI Bridge is not used) while reading data from it. Each bit corresponds to a DMA channel. Bit [0].." group.long (0x60+0xC8000)++0x1F line.long 0x0 "DMA_WRITE_DONE_IMWR_LOW_OFF,DMA Write Done IMWr Address Low Register." hexmask.long 0x0 0.--31. 1. "DMA_WRITE_DONE_LOW_REG,The DMA uses this field to generate bits [31:0] of the address field for the Done IMWr TLP. Bits [1:0] must be '00' as this address must be dword aligned. Note: The access attributes of this field are as follows: - Wire: No access." line.long 0x4 "DMA_WRITE_DONE_IMWR_HIGH_OFF,DMA Write Done IMWr Interrupt Address High Register." hexmask.long 0x4 0.--31. 1. "DMA_WRITE_DONE_HIGH_REG,The DMA uses this field to generate bits [63:32] of the address field for the Done IMWr TLP. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" line.long 0x8 "DMA_WRITE_ABORT_IMWR_LOW_OFF,DMA Write Abort IMWr Address Low Register." hexmask.long 0x8 0.--31. 1. "DMA_WRITE_ABORT_LOW_REG,The DMA uses this field to generate bits [31:0] of the address field for the Abort IMWr TLP it generates. Bits [1:0] must be '00' as this address must be dword aligned. Note: The access attributes of this field are as follows: -.." line.long 0xC "DMA_WRITE_ABORT_IMWR_HIGH_OFF,DMA Write Abort IMWr Address High Register." hexmask.long 0xC 0.--31. 1. "DMA_WRITE_ABORT_HIGH_REG,The DMA uses this field to generate bits [63:32] of the address field for the Abort IMWr TLP. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" line.long 0x10 "DMA_WRITE_CH01_IMWR_DATA_OFF,DMA Write Channel 1 and 0 IMWr Data Register." hexmask.long.word 0x10 16.--31. 1. "WR_CHANNEL_1_DATA,The DMA uses this field to generate the data field for the Done or Abort IMWr TLPs it generates for write channel 1. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" hexmask.long.word 0x10 0.--15. 1. "WR_CHANNEL_0_DATA,The DMA uses this field to generate the data field for the Done or Abort IMWr TLPs it generates for write channel 0. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" line.long 0x14 "DMA_WRITE_CH23_IMWR_DATA_OFF,DMA Write Channel 3 and 2 IMWr Data Register." hexmask.long.word 0x14 16.--31. 1. "WR_CHANNEL_3_DATA,The DMA uses this field to generate the data field for the Done or Abort IMWr TLPs it generates for write channel 3. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" hexmask.long.word 0x14 0.--15. 1. "WR_CHANNEL_2_DATA,The DMA uses this field to generate the data field for the Done or Abort IMWr TLPs it generates for write channel 2. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" line.long 0x18 "DMA_WRITE_CH45_IMWR_DATA_OFF,DMA Write Channel 5 and 4 IMWr Data Register." hexmask.long.word 0x18 16.--31. 1. "WR_CHANNEL_5_DATA,The DMA uses this field to generate the data field for the Done or Abort IMWr TLPs it generates for write channel 5. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" hexmask.long.word 0x18 0.--15. 1. "WR_CHANNEL_4_DATA,The DMA uses this field to generate the data field for the Done or Abort IMWr TLPs it generates for write channel 4. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" line.long 0x1C "DMA_WRITE_CH67_IMWR_DATA_OFF,DMA Write Channel 7 and 6 IMWr Data Register." hexmask.long.word 0x1C 16.--31. 1. "WR_CHANNEL_7_DATA,The DMA uses this field to generate the data field for the Done or Abort IMWr TLPs it generates for write channel 7. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" hexmask.long.word 0x1C 0.--15. 1. "WR_CHANNEL_6_DATA,The DMA uses this field to generate the data field for the Done or Abort IMWr TLPs it generates for write channel 6. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" group.long (0x90+0xC8000)++0x3 line.long 0x0 "DMA_WRITE_LINKED_LIST_ERR_EN_OFF,DMA Write Linked List Error Enable Register. The LIE and RIE bits in the LL element enable the channel 'done' interrupts (local and remote). The LLLAIE and LLRAIE bits enable the channel 'abort' interrupts (local and.." hexmask.long.byte 0x0 24.--31. 1. "RSVDP_24,Reserved for future use." hexmask.long.byte 0x0 16.--23. 1. "WR_CHANNEL_LLLAIE,Write Channel LL Local Abort Interrupt Enable (LLLAIE). You enable the write channel local abort interrupt through this bit. The LIE and RIE bits in the LL element enable the write channel done interrupts. Each bit corresponds to a DMA.." newline hexmask.long.byte 0x0 8.--15. 1. "RSVDP_8,Reserved for future use." hexmask.long.byte 0x0 0.--7. 1. "WR_CHANNEL_LLRAIE,Write Channel LL Remote Abort Interrupt Enable (LLRAIE). You enable the write channel remote abort interrupt through this bit. The LIE and RIE bits in the LL element enable the write channel done interrupts. Each bit corresponds to a.." group.long (0xA0+0xC8000)++0x3 line.long 0x0 "DMA_READ_INT_STATUS_OFF,DMA Read Interrupt Status Register." hexmask.long.byte 0x0 24.--31. 1. "RSVDP_24,Reserved for future use." hexmask.long.byte 0x0 16.--23. 1. "RD_ABORT_INT_STATUS,Abort Interrupt Status. The DMA read channel has detected an error or you manually stopped the transfer as described in 'Stopping the DMA Transfer (Software Stop)'. Each bit corresponds to a DMA channel. Bit [0] corresponds to.." newline hexmask.long.byte 0x0 8.--15. 1. "RSVDP_8,Reserved for future use." hexmask.long.byte 0x0 0.--7. 1. "RD_DONE_INT_STATUS,Done Interrupt Status. The DMA read channel has successfully completed the DMA read transfer. Each bit corresponds to a DMA channel. Bit [0] corresponds to channel 0. - Enabling: For details see 'Interrupts and Error Handling'. -.." group.long (0xA8+0xC8000)++0x7 line.long 0x0 "DMA_READ_INT_MASK_OFF,DMA Read Interrupt Mask Register." hexmask.long.byte 0x0 24.--31. 1. "RSVDP_24,Reserved for future use." hexmask.long.byte 0x0 16.--23. 1. "RD_ABORT_INT_MASK,Abort Interrupt Mask. Prevents the Abort interrupt status field in the DMA read interrupt status register from asserting the edma_int output. Each bit corresponds to a DMA channel. Bit [0] corresponds to channel 0. Note: The access.." newline hexmask.long.byte 0x0 8.--15. 1. "RSVDP_8,Reserved for future use." hexmask.long.byte 0x0 0.--7. 1. "RD_DONE_INT_MASK,Done Interrupt Mask. Prevents the Done interrupt status field in the DMA read interrupt status register from asserting the edma_int output. Each bit corresponds to a DMA channel. Bit [0] corresponds to channel 0. Note: The access.." line.long 0x4 "DMA_READ_INT_CLEAR_OFF,DMA Read Interrupt Clear Register." hexmask.long.byte 0x4 24.--31. 1. "RSVDP_24,Reserved for future use." hexmask.long.byte 0x4 16.--23. 1. "RD_ABORT_INT_CLEAR,Abort Interrupt Clear. You must write a 1'b1 to clear the corresponding bit in the Abort interrupt status field of the DMA read interrupt status register. Each bit corresponds to a DMA channel. Bit [0] corresponds to channel 0. Note:.." newline hexmask.long.byte 0x4 8.--15. 1. "RSVDP_8,Reserved for future use." hexmask.long.byte 0x4 0.--7. 1. "RD_DONE_INT_CLEAR,Done Interrupt Clear. You must write a 1'b1 to clear the corresponding bit in the Done interrupt status field of the DMA read interrupt status register. Each bit corresponds to a DMA channel. Bit [0] corresponds to channel 0. Note:.." rgroup.long (0xB4+0xC8000)++0x7 line.long 0x0 "DMA_READ_ERR_STATUS_LOW_OFF,DMA Read Error Status Low Register." hexmask.long.byte 0x0 24.--31. 1. "RSVDP_24,Reserved for future use." hexmask.long.byte 0x0 16.--23. 1. "LINK_LIST_ELEMENT_FETCH_ERR_DETECT,Linked List Element Fetch Error Detected. - The DMA read channel has received an error response from the AXI bus while reading a linked list element from local memory. Each bit corresponds to a DMA channel. Bit [0].." newline hexmask.long.byte 0x0 8.--15. 1. "RSVDP_8,Reserved for future use." hexmask.long.byte 0x0 0.--7. 1. "APP_WR_ERR_DETECT,Application Write Error Detected. The DMA read channel has received an error response from the AXI bus (or TRGT1 interface when the AXI Bridge is not used) while writing data to it. This error is fatal. You must restart the transfer.." line.long 0x4 "DMA_READ_ERR_STATUS_HIGH_OFF,DMA Read Error Status High Register." hexmask.long.byte 0x4 24.--31. 1. "DATA_POISIONING,Data Poisoning. The DMA read channel has detected data poisoning in the completion from the remote device (in response to the MRd request). The DMA read channel will drop the completion and then be halted. The CX_FLT_MASK_UR_POIS filter.." hexmask.long.byte 0x4 16.--23. 1. "CPL_TIMEOUT,Completion Time Out. The DMA read channel has timed-out while waiting for the remote device to respond to the MRd request or a malformed CplD has been received. For more details see 'Linked List Mode'. Each bit corresponds to a DMA channel." newline hexmask.long.byte 0x4 8.--15. 1. "CPL_ABORT,Completer Abort. The DMA read channel has received a PCIe completer abort completion status from the remote device in response to the MRd request. For more details see 'Linked List Mode'. Each bit corresponds to a DMA channel. Bit [0].." hexmask.long.byte 0x4 0.--7. 1. "UNSUPPORTED_REQ,Unsupported Request. The DMA read channel has received a PCIe unsupported request completion status from the remote device in response to the MRd request. For more details see 'Linked List Mode'. Each bit corresponds to a DMA channel." group.long (0xC4+0xC8000)++0x3 line.long 0x0 "DMA_READ_LINKED_LIST_ERR_EN_OFF,DMA Read Linked List Error Enable Register. The LIE and RIE bits in the LL element enable the channel 'done' interrupts (local and remote). The LLLAIE and LLRAIE bits enable the channel 'abort' interrupts (local and remote)." hexmask.long.byte 0x0 24.--31. 1. "RSVDP_24,Reserved for future use." hexmask.long.byte 0x0 16.--23. 1. "RD_CHANNEL_LLLAIE,Read Channel LL Local Abort Interrupt Enable (LLLAIE). You enable the read channel Local Abort interrupt through this bit. The LIE and RIE bits in the LL element enable the read channel done interrupts. Each bit corresponds to a DMA.." newline hexmask.long.byte 0x0 8.--15. 1. "RSVDP_8,Reserved for future use." hexmask.long.byte 0x0 0.--7. 1. "RD_CHANNEL_LLRAIE,Read Channel LL Remote Abort Interrupt Enable (LLRAIE). You enable the read channel Remote Abort interrupt through this bit. The LIE and RIE bits in the LL element enable the read channel done interrupts. Each bit corresponds to a DMA.." group.long (0xCC+0xC8000)++0x1F line.long 0x0 "DMA_READ_DONE_IMWR_LOW_OFF,DMA Read Done IMWr Address Low Register." hexmask.long 0x0 0.--31. 1. "DMA_READ_DONE_LOW_REG,The DMA uses this field to generate bits [31:0] of the address field for the Done IMWr TLP. Bits [1:0] must be '00' as this address must be dword aligned. Note: The access attributes of this field are as follows: - Wire: No access." line.long 0x4 "DMA_READ_DONE_IMWR_HIGH_OFF,DMA Read Done IMWr Address High Register." hexmask.long 0x4 0.--31. 1. "DMA_READ_DONE_HIGH_REG,The DMA uses this field to generate bits [63:32] of the address field for the Done IMWr TLP. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" line.long 0x8 "DMA_READ_ABORT_IMWR_LOW_OFF,DMA Read Abort IMWr Address Low Register." hexmask.long 0x8 0.--31. 1. "DMA_READ_ABORT_LOW_REG,The DMA uses this field to generate bits [31:0] of the address field for the Abort IMWr TLP. Bits [1:0] must be '00' as this address must be dword aligned. Note: The access attributes of this field are as follows: - Wire: No.." line.long 0xC "DMA_READ_ABORT_IMWR_HIGH_OFF,DMA Read Abort IMWr Address High Register." hexmask.long 0xC 0.--31. 1. "DMA_READ_ABORT_HIGH_REG,The DMA uses this field to generate bits [63:32] of the address field for the Abort IMWr TLP. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" line.long 0x10 "DMA_READ_CH01_IMWR_DATA_OFF,DMA Read Channel 1 and 0 IMWr Data Register." hexmask.long.word 0x10 16.--31. 1. "RD_CHANNEL_1_DATA,The DMA uses this field to generate the data field for the Done or Abort IMWr TLPs it generates for read channel 1. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" hexmask.long.word 0x10 0.--15. 1. "RD_CHANNEL_0_DATA,The DMA uses this field to generate the data field for the Done or Abort IMWr TLPs it generates for read channel 0. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" line.long 0x14 "DMA_READ_CH23_IMWR_DATA_OFF,DMA Read Channel 3 and 2 IMWr Data Register." hexmask.long.word 0x14 16.--31. 1. "RD_CHANNEL_3_DATA,The DMA uses this field to generate the data field for the Done or Abort IMWr TLPs it generates for read channel 3. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" hexmask.long.word 0x14 0.--15. 1. "RD_CHANNEL_2_DATA,The DMA uses this field to generate the data field for the Done or Abort IMWr TLPs it generates for read channel 2. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" line.long 0x18 "DMA_READ_CH45_IMWR_DATA_OFF,DMA Read Channel 5 and 4 IMWr Data Register." hexmask.long.word 0x18 16.--31. 1. "RD_CHANNEL_5_DATA,The DMA uses this field to generate the data field for the Done or Abort IMWr TLPs it generates for read channel 5. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" hexmask.long.word 0x18 0.--15. 1. "RD_CHANNEL_4_DATA,The DMA uses this field to generate the data field for the Done or Abort IMWr TLPs it generates for read channel 4. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" line.long 0x1C "DMA_READ_CH67_IMWR_DATA_OFF,DMA Read Channel 7 and 6 IMWr Data Register." hexmask.long.word 0x1C 16.--31. 1. "RD_CHANNEL_7_DATA,The DMA uses this field to generate the data field for the Done or Abort IMWr TLPs it generates for read channel 7. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" hexmask.long.word 0x1C 0.--15. 1. "RD_CHANNEL_6_DATA,The DMA uses this field to generate the data field for the Done or Abort IMWr TLPs it generates for read channel 6. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" rgroup.long (0x108+0xC8000)++0x7 line.long 0x0 "DMA_WRITE_ENGINE_HSHAKE_CNT_LOW_OFF,DMA Write Engine Handshake Counter Channel 0/1/2/3 Register." bitfld.long 0x0 29.--31. "RSVDP_29,Reserved for future use." "0,1,2,3,4,5,6,7" hexmask.long.byte 0x0 24.--28. 1. "DMA_WRITE_ENGINE_HSHAKE_CNT_CH3,DMA handshake counter for DMA Write Engine Channel 3. If CC_DMA_HSHAKE =1 the data transfer in Linked List mode starts only when the counter is non-zero." newline bitfld.long 0x0 21.--23. "RSVDP_21,Reserved for future use." "0,1,2,3,4,5,6,7" hexmask.long.byte 0x0 16.--20. 1. "DMA_WRITE_ENGINE_HSHAKE_CNT_CH2,DMA handshake counter for DMA Write Engine Channel 2. If CC_DMA_HSHAKE =1 the data transfer in Linked List mode starts only when the counter is non-zero." newline bitfld.long 0x0 13.--15. "RSVDP_13,Reserved for future use." "0,1,2,3,4,5,6,7" hexmask.long.byte 0x0 8.--12. 1. "DMA_WRITE_ENGINE_HSHAKE_CNT_CH1,DMA handshake counter for DMA Write Engine Channel 1. If CC_DMA_HSHAKE =1 the data transfer in Linked List mode starts only when the counter is non-zero." newline bitfld.long 0x0 5.--7. "RSVDP_5,Reserved for future use." "0,1,2,3,4,5,6,7" hexmask.long.byte 0x0 0.--4. 1. "DMA_WRITE_ENGINE_HSHAKE_CNT_CH0,DMA handshake counter for DMA Write Engine Channel 0. If CC_DMA_HSHAKE =1 the data transfer in Linked List mode starts only when the counter is non-zero." line.long 0x4 "DMA_WRITE_ENGINE_HSHAKE_CNT_HIGH_OFF,DMA Write Engine Handshake Counter Channel 4/5/6/7 Register." bitfld.long 0x4 29.--31. "RSVDP_29,Reserved for future use." "0,1,2,3,4,5,6,7" hexmask.long.byte 0x4 24.--28. 1. "DMA_WRITE_ENGINE_HSHAKE_CNT_CH7,DMA handshake counter for DMA Write Engine Channel 7. If CC_DMA_HSHAKE =1 the data transfer in Linked List mode starts only when the counter is non-zero." newline bitfld.long 0x4 21.--23. "RSVDP_21,Reserved for future use." "0,1,2,3,4,5,6,7" hexmask.long.byte 0x4 16.--20. 1. "DMA_WRITE_ENGINE_HSHAKE_CNT_CH6,DMA handshake counter for DMA Write Engine Channel 6. If CC_DMA_HSHAKE =1 the data transfer in Linked List mode starts only when the counter is non-zero." newline bitfld.long 0x4 13.--15. "RSVDP_13,Reserved for future use." "0,1,2,3,4,5,6,7" hexmask.long.byte 0x4 8.--12. 1. "DMA_WRITE_ENGINE_HSHAKE_CNT_CH5,DMA handshake counter for DMA Write Engine Channel 5. If CC_DMA_HSHAKE =1 the data transfer in Linked List mode starts only when the counter is non-zero." newline bitfld.long 0x4 5.--7. "RSVDP_5,Reserved for future use." "0,1,2,3,4,5,6,7" hexmask.long.byte 0x4 0.--4. 1. "DMA_WRITE_ENGINE_HSHAKE_CNT_CH4,DMA handshake counter for DMA Write Engine Channel 4. If CC_DMA_HSHAKE =1 the data transfer in Linked List mode starts only when the counter is non-zero." rgroup.long (0x118+0xC8000)++0x7 line.long 0x0 "DMA_READ_ENGINE_HSHAKE_CNT_LOW_OFF,DMA Read Engine Handshake Counter Channel 0/1/2/3 Register." bitfld.long 0x0 29.--31. "RSVDP_29,Reserved for future use." "0,1,2,3,4,5,6,7" hexmask.long.byte 0x0 24.--28. 1. "DMA_READ_ENGINE_HSHAKE_CNT_CH3,DMA handshake counter for DMA Read Engine Channel 3. If CC_DMA_HSHAKE =1 the data transfer in Linked List mode starts only when the counter is non-zero." newline bitfld.long 0x0 21.--23. "RSVDP_21,Reserved for future use." "0,1,2,3,4,5,6,7" hexmask.long.byte 0x0 16.--20. 1. "DMA_READ_ENGINE_HSHAKE_CNT_CH2,DMA handshake counter for DMA Read Engine Channel 2. If CC_DMA_HSHAKE =1 the data transfer in Linked List mode starts only when the counter is non-zero." newline bitfld.long 0x0 13.--15. "RSVDP_13,Reserved for future use." "0,1,2,3,4,5,6,7" hexmask.long.byte 0x0 8.--12. 1. "DMA_READ_ENGINE_HSHAKE_CNT_CH1,DMA handshake counter for DMA Read Engine Channel 1. If CC_DMA_HSHAKE =1 the data transfer in Linked List mode starts only when the counter is non-zero." newline bitfld.long 0x0 5.--7. "RSVDP_5,Reserved for future use." "0,1,2,3,4,5,6,7" hexmask.long.byte 0x0 0.--4. 1. "DMA_READ_ENGINE_HSHAKE_CNT_CH0,DMA handshake counter for DMA Read Engine Channel 0. If CC_DMA_HSHAKE =1 the data transfer in Linked List mode starts only when the counter is non-zero." line.long 0x4 "DMA_READ_ENGINE_HSHAKE_CNT_HIGH_OFF,DMA Read Engine Handshake Counter Channel 4/5/6/7 Register." bitfld.long 0x4 29.--31. "RSVDP_29,Reserved for future use." "0,1,2,3,4,5,6,7" hexmask.long.byte 0x4 24.--28. 1. "DMA_READ_ENGINE_HSHAKE_CNT_CH7,DMA handshake counter for DMA Read Engine Channel 7. If CC_DMA_HSHAKE =1 the data transfer in Linked List mode starts only when the counter is non-zero." newline bitfld.long 0x4 21.--23. "RSVDP_21,Reserved for future use." "0,1,2,3,4,5,6,7" hexmask.long.byte 0x4 16.--20. 1. "DMA_READ_ENGINE_HSHAKE_CNT_CH6,DMA handshake counter for DMA Read Engine Channel 6. If CC_DMA_HSHAKE =1 the data transfer in Linked List mode starts only when the counter is non-zero." newline bitfld.long 0x4 13.--15. "RSVDP_13,Reserved for future use." "0,1,2,3,4,5,6,7" hexmask.long.byte 0x4 8.--12. 1. "DMA_READ_ENGINE_HSHAKE_CNT_CH5,DMA handshake counter for DMA Read Engine Channel 5. If CC_DMA_HSHAKE =1 the data transfer in Linked List mode starts only when the counter is non-zero." newline bitfld.long 0x4 5.--7. "RSVDP_5,Reserved for future use." "0,1,2,3,4,5,6,7" hexmask.long.byte 0x4 0.--4. 1. "DMA_READ_ENGINE_HSHAKE_CNT_CH4,DMA handshake counter for DMA Read Engine Channel 4. If CC_DMA_HSHAKE =1 the data transfer in Linked List mode starts only when the counter is non-zero." repeat 8. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 )(list 0x0 0x200 0x400 0x600 0x800 0xA00 0xC00 0xE00 ) group.long ($2+0x200+0xC8000)++0x3 line.long 0x0 "DMA_CH_CONTROL1_OFF_WRCH_$1,DMA Write Channel Control 1 Register." bitfld.long 0x0 30.--31. "DMA_AT,Address Translation TLP Header Bit (AT) The DMA uses this TLP header field when generating MRd/MWr (not IMWr) TLPs. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" "0,1,2,3" bitfld.long 0x0 27.--29. "DMA_TC,Traffic Class TLP Header Bit (TC) The DMA uses this TLP header field when generating MRd/MWr (not IMWr) TLPs. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 26. "DMA_RESERVED5,Reserved. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" "0,1" bitfld.long 0x0 25. "DMA_RO,Relaxed Ordering TLP Header Bit (RO) The DMA uses this TLP header field when generating MRd/MWr (not IMWr) TLPs. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" "0,1" newline bitfld.long 0x0 24. "DMA_NS_SRC,Source No Snoop TLP Header Bit (DMA_NS_SRC). The DMA uses this TLP header field when generating MRd (SAR addressing space) (not IMWr) TLPs. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" "0,1" bitfld.long 0x0 23. "DMA_NS_DST,Destination No Snoop TLP Header Bit (DMA_NS_DST). The DMA uses this TLP header field when generating MWr (DAR addressing space) (not IMWr) TLPs. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" "0,1" newline bitfld.long 0x0 22. "DMA_MEM_TYPE,Master AXI ACE-Lite Cache Coherency Control. This field sets the DMA channel memory type of the address space of the data transfer as follows: - 0x0:peripheral type - 0x1:memory type For more details see 'ACE-Lite Features and Limitations'.." "peripheral type,memory type" hexmask.long.byte 0x0 17.--21. 1. "DMA_RESERVED2,Reserved. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" newline hexmask.long.byte 0x0 12.--16. 1. "DMA_FUNC_NUM,Function Number (FN). The controller uses this field when generating the requester ID for the MRd/MWr DMA TLP. When you have enabled SR-IOV then this field is ignored if you have set the VFE field in the 'DMA Write Channel Control 2.." bitfld.long 0x0 10.--11. "DMA_RESERVED1,Reserved. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" "0,1,2,3" newline bitfld.long 0x0 9. "LLE,Linked List Enable (LLE). - 0: Disable linked list operation - 1: Enable linked list operation Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" "Disable linked list operation,Enable linked list operation" bitfld.long 0x0 8. "CCS,Consumer Cycle State (CCS). Used in linked list mode only. It is used to synchronize the producer (software) and the consumer (DMA). For more details see 'PCS-CCS-CB-TCB Producer-Consumer Synchronization'. You must initialize this bit. The DMA.." "0,1" newline bitfld.long 0x0 7. "DMA_RESERVED0,Reserved. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" "0,1" bitfld.long 0x0 5.--6. "CS,Channel Status (CS). The channel status bits identify the current operational state of the DMA channel. The operation state encoding for each DMA channel is a s follows: - 00: Reserved - 01: Running. This channel is active and transferring data. - 10:.." "Reserved,Running,?,?" newline bitfld.long 0x0 4. "RIE,Remote Interrupt Enable (RIE). You must set this bit to enable the generation of the Done or Abort Remote interrupts. For more details see 'Interrupts and Error Handling'. In LL mode the DMA overwrites this with the RIE of the LL element. The RIE.." "0,1" bitfld.long 0x0 3. "LIE,Local Interrupt Enable (LIE). You must set this bit to enable the generation of the Done or Abort Local interrupts. For more details see 'Interrupts and Error Handling'. In LL mode the DMA overwrites this with the LIE of the LL element. The LIE bit.." "0,1" newline bitfld.long 0x0 2. "LLP,Load Link Pointer (LLP). Used in linked list mode only. Indicates that this linked list element is a link element and its LL element pointer dwords are pointing to the next (non-contiguous) element. The DMA loads this field with the LLP of the.." "0,1" bitfld.long 0x0 1. "TCB,Toggle Cycle Bit (TCB). Indicates to the DMA to toggle its interpretation of the CB. Used in linked list mode only. It is used to synchronize the producer (software) and the consumer (DMA). For more details see 'PCS-CCS-CB-TCB Producer-Consumer.." "0,1" newline bitfld.long 0x0 0. "CB,Cycle Bit (CB). Used in linked list mode only. It is used to synchronize the producer (software) and the consumer (DMA). For more details see 'PCS-CCS-CB-TCB Producer-Consumer Synchronization'. The DMA loads this field with the CB of the linked list.." "0,1" repeat.end repeat 8. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 )(list 0x0 0x200 0x400 0x600 0x800 0xA00 0xC00 0xE00 ) group.long ($2+0x208+0xC8000)++0x3 line.long 0x0 "DMA_TRANSFER_SIZE_OFF_WRCH_$1,DMA Write Transfer Size Register." hexmask.long 0x0 0.--31. 1. "DMA_TRANSFER_SIZE,DMA Transfer Size. You program this register with the size of the DMA transfer. The maximum DMA transfer size is 4Gbytes. The minimum transfer size is one byte (0x1). This field is automatically decremented by the DMA as the DMA write.." repeat.end repeat 8. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 )(list 0x0 0x200 0x400 0x600 0x800 0xA00 0xC00 0xE00 ) group.long ($2+0x20C+0xC8000)++0x3 line.long 0x0 "DMA_SAR_LOW_OFF_WRCH_$1,DMA Write SAR Low Register." hexmask.long 0x0 0.--31. 1. "SRC_ADDR_REG_LOW,Source Address Register (Lower 32 bits). Indicates the next address to be read from. The DMA increments the SAR as the DMA transfer progresses. In LL mode the DMA overwrites this with the corresponding dword of the LL element. - DMA.." repeat.end repeat 8. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 )(list 0x0 0x200 0x400 0x600 0x800 0xA00 0xC00 0xE00 ) group.long ($2+0x210+0xC8000)++0x3 line.long 0x0 "DMA_SAR_HIGH_OFF_WRCH_$1,DMA Write SAR High Register." hexmask.long 0x0 0.--31. 1. "SRC_ADDR_REG_HIGH,Source Address Register (Higher 32 bits). In LL mode the DMA overwrites this with the corresponding dword of the LL element. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" repeat.end repeat 8. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 )(list 0x0 0x200 0x400 0x600 0x800 0xA00 0xC00 0xE00 ) group.long ($2+0x214+0xC8000)++0x3 line.long 0x0 "DMA_DAR_LOW_OFF_WRCH_$1,DMA Write DAR Low Register." hexmask.long 0x0 0.--31. 1. "DST_ADDR_REG_LOW,Destination Address Register (Lower 32 bits). Indicates the next address to be written to. The DMA increments the DAR as the DMA transfer progresses. In LL mode the DMA overwrites this with the corresponding dword of the LL element. -.." repeat.end repeat 8. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 )(list 0x0 0x200 0x400 0x600 0x800 0xA00 0xC00 0xE00 ) group.long ($2+0x218+0xC8000)++0x3 line.long 0x0 "DMA_DAR_HIGH_OFF_WRCH_$1,DMA Write DAR High Register." hexmask.long 0x0 0.--31. 1. "DST_ADDR_REG_HIGH,Destination Address Register (Higher 32 bits). In LL mode the DMA overwrites this with the corresponding dword of the LL element. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" repeat.end repeat 8. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 )(list 0x0 0x200 0x400 0x600 0x800 0xA00 0xC00 0xE00 ) group.long ($2+0x21C+0xC8000)++0x3 line.long 0x0 "DMA_LLP_LOW_OFF_WRCH_$1,DMA Write Linked List Pointer Low Register." hexmask.long 0x0 0.--31. 1. "LLP_LOW,Lower bits of the address of the linked list transfer list in local memory. Used in linked list mode only. Updated by the DMA to point to the next element in the transfer list after the previous element is consumed. - When the current element is.." repeat.end repeat 8. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 )(list 0x0 0x200 0x400 0x600 0x800 0xA00 0xC00 0xE00 ) group.long ($2+0x220+0xC8000)++0x3 line.long 0x0 "DMA_LLP_HIGH_OFF_WRCH_$1,DMA Write Linked List Pointer High Register." hexmask.long 0x0 0.--31. 1. "LLP_HIGH,Upper 32 bits of the address of the linked list transfer list in local memory. Used in linked list mode only. Updated by the DMA to point to the next element in the transfer list as elements are consumed. Note: The access attributes of this.." repeat.end repeat 8. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 )(list 0x0 0x200 0x400 0x600 0x800 0xA00 0xC00 0xE00 ) group.long ($2+0x300+0xC8000)++0x3 line.long 0x0 "DMA_CH_CONTROL1_OFF_RDCH_$1,DMA Read Channel Control 1 Register." bitfld.long 0x0 30.--31. "DMA_AT,Address Translation TLP Header Bit (AT) The DMA uses this TLP header field when generating MRd/MWr (not IMWr) TLPs. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" "0,1,2,3" bitfld.long 0x0 27.--29. "DMA_TC,Traffic Class TLP Header Bit (TC) The DMA uses this TLP header field when generating MRd/MWr (not IMWr) TLPs. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 26. "DMA_RESERVED5,Reserved. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" "0,1" bitfld.long 0x0 25. "DMA_RO,Relaxed Ordering TLP Header Bit (RO) The DMA uses this TLP header field when generating MRd/MWr (not IMWr) TLPs. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" "0,1" newline bitfld.long 0x0 24. "DMA_NS_SRC,Source No Snoop TLP Header Bit (DMA_NS_SRC). The DMA uses this TLP header field when generating MRd (SAR addressing space) (not IMWr) TLPs. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" "0,1" bitfld.long 0x0 23. "DMA_NS_DST,Destination No Snoop TLP Header Bit (DMA_NS_DST). The DMA uses this TLP header field when generating MWr (DAR addressing space) (not IMWr) TLPs. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" "0,1" newline bitfld.long 0x0 22. "DMA_MEM_TYPE,Master AXI ACE-Lite Cache Coherency Control. This field sets the DMA channel memory type of the address space of the data transfer as follows: - 0x0:peripheral type - 0x1:memory type For more details see 'ACE-Lite Features and Limitations'.." "peripheral type,memory type" hexmask.long.byte 0x0 17.--21. 1. "DMA_RESERVED2,Reserved. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" newline hexmask.long.byte 0x0 12.--16. 1. "DMA_FUNC_NUM,Function Number (FN). The controller uses this field when generating the requester ID for the MRd/MWr DMA TLP. When you have enabled SR-IOV then this field is ignored if you have set the VFE field in the 'DMA Read Channel Control 2.." bitfld.long 0x0 10.--11. "DMA_RESERVED1,Reserved. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" "0,1,2,3" newline bitfld.long 0x0 9. "LLE,Linked List Enable (LLE). - 0: Disable linked list operation - 1: Enable linked list operation Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" "Disable linked list operation,Enable linked list operation" bitfld.long 0x0 8. "CCS,Consumer Cycle State (CCS). Used in linked list mode only. It is used to synchronize the producer (software) and the consumer (DMA). For more details see 'PCS-CCS-CB-TCB Producer-Consumer Synchronization'. You must initialize this bit. The DMA.." "0,1" newline bitfld.long 0x0 7. "DMA_RESERVED0,Reserved. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" "0,1" bitfld.long 0x0 5.--6. "CS,Channel Status (CS). The channel status bits identify the current operational state of the DMA channel. The operation state encoding for each DMA channel is a s follows: - 00: Reserved - 01: Running. This channel is active and transferring data. - 10:.." "Reserved,Running,?,?" newline bitfld.long 0x0 4. "RIE,Remote Interrupt Enable (RIE). You must set this bit to enable the generation of the Done or Abort Remote interrupts. For more details see 'Interrupts and Error Handling'. In LL mode the DMA overwrites this with the RIE of the LL element. The RIE.." "0,1" bitfld.long 0x0 3. "LIE,Local Interrupt Enable (LIE). You must set this bit to enable the generation of the Done or Abort Local interrupts. For more details see 'Interrupts and Error Handling'. In LL mode the DMA overwrites this with the LIE of the LL element. The LIE bit.." "0,1" newline bitfld.long 0x0 2. "LLP,Load Link Pointer (LLP). Used in linked list mode only. Indicates that this linked list element is a link element and its LL element pointer dwords are pointing to the next (non-contiguous) element. The DMA loads this field with the LLP of the.." "0,1" bitfld.long 0x0 1. "TCB,Toggle Cycle Bit (TCB). Indicates to the DMA to toggle its interpretation of the CB. Used in linked list mode only. It is used to synchronize the producer (software) and the consumer (DMA). For more details see 'PCS-CCS-CB-TCB Producer-Consumer.." "0,1" newline bitfld.long 0x0 0. "CB,Cycle Bit (CB). Used in linked list mode only. It is used to synchronize the producer (software) and the consumer (DMA). For more details see 'PCS-CCS-CB-TCB Producer-Consumer Synchronization'. The DMA loads this field with the CB of the linked list.." "0,1" repeat.end repeat 8. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 )(list 0x0 0x200 0x400 0x600 0x800 0xA00 0xC00 0xE00 ) group.long ($2+0x308+0xC8000)++0x3 line.long 0x0 "DMA_TRANSFER_SIZE_OFF_RDCH_$1,DMA Read Transfer Size Register." hexmask.long 0x0 0.--31. 1. "DMA_TRANSFER_SIZE,DMA Transfer Size. You program this register with the size of the DMA transfer. The maximum DMA transfer size is 4Gbytes. The minimum transfer size is one byte (0x1). This field is automatically decremented by the DMA as the DMA read.." repeat.end repeat 8. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 )(list 0x0 0x200 0x400 0x600 0x800 0xA00 0xC00 0xE00 ) group.long ($2+0x30C+0xC8000)++0x3 line.long 0x0 "DMA_SAR_LOW_OFF_RDCH_$1,DMA Read SAR Low Register." hexmask.long 0x0 0.--31. 1. "SRC_ADDR_REG_LOW,Source Address Register (Lower 32 bits). Indicates the next address to be read from. The DMA increments the SAR as the DMA transfer progresses. In LL mode the DMA overwrites this with the corresponding dword of the LL element. - DMA.." repeat.end repeat 8. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 )(list 0x0 0x200 0x400 0x600 0x800 0xA00 0xC00 0xE00 ) group.long ($2+0x310+0xC8000)++0x3 line.long 0x0 "DMA_SAR_HIGH_OFF_RDCH_$1,DMA Read SAR High Register." hexmask.long 0x0 0.--31. 1. "SRC_ADDR_REG_HIGH,Source Address Register (Higher 32 bits). In LL mode the DMA overwrites this with the corresponding dword of the LL element. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" repeat.end repeat 8. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 )(list 0x0 0x200 0x400 0x600 0x800 0xA00 0xC00 0xE00 ) group.long ($2+0x314+0xC8000)++0x3 line.long 0x0 "DMA_DAR_LOW_OFF_RDCH_$1,DMA Read DAR Low Register." hexmask.long 0x0 0.--31. 1. "DST_ADDR_REG_LOW,Destination Address Register (Lower 32 bits). Indicates the next address to be written to. The DMA increments the DAR as the DMA transfer progresses. In LL mode the DMA overwrites this with the corresponding dword of the LL element. -.." repeat.end repeat 8. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 )(list 0x0 0x200 0x400 0x600 0x800 0xA00 0xC00 0xE00 ) group.long ($2+0x318+0xC8000)++0x3 line.long 0x0 "DMA_DAR_HIGH_OFF_RDCH_$1,DMA Read DAR High Register." hexmask.long 0x0 0.--31. 1. "DST_ADDR_REG_HIGH,Destination Address Register (Higher 32 bits). In LL mode the DMA overwrites this with the corresponding dword of the LL element. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" repeat.end repeat 8. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 )(list 0x0 0x200 0x400 0x600 0x800 0xA00 0xC00 0xE00 ) group.long ($2+0x31C+0xC8000)++0x3 line.long 0x0 "DMA_LLP_LOW_OFF_RDCH_$1,DMA Read Linked List Pointer Low Register." hexmask.long 0x0 0.--31. 1. "LLP_LOW,Lower bits of the address of the linked list transfer list in local memory. Used in linked list mode only. Updated by the DMA to point to the next element in the transfer list after the previous element is consumed. - When the current element is.." repeat.end repeat 8. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 )(list 0x0 0x200 0x400 0x600 0x800 0xA00 0xC00 0xE00 ) group.long ($2+0x320+0xC8000)++0x3 line.long 0x0 "DMA_LLP_HIGH_OFF_RDCH_$1,DMA Read Linked List Pointer High Register." hexmask.long 0x0 0.--31. 1. "LLP_HIGH,Upper 32 bits of the address of the linked list transfer list in local memory. Used in linked list mode only. Updated by the DMA to point to the next element in the transfer list as elements are consumed. Note: The access attributes of this.." repeat.end tree.end tree "PF0_ATU_CAP (ATU Por Logic Structure)" repeat 8. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 )(list 0x0 0x200 0x400 0x600 0x800 0xA00 0xC00 0xE00 ) group.long ($2+0xC0000)++0x3 line.long 0x0 "IATU_REGION_CTRL_1_OFF_OUTBOUND_$1,iATU Region Control 1 Register." bitfld.long 0x0 20. "CTRL_1_FUNC_NUM,Function Number. - When the address of an outbound TLP is matched to this region and the FUNC_BYPASS field in the 'iATU Control 2 Register' is '0' then the function number used in generating the function part of the requester ID (RID).." "0,1" newline bitfld.long 0x0 13. "INCREASE_REGION_SIZE,Increase the maximum ATU Region size. When set the maximum ATU Region size is determined by CX_ATU_MAX_REGION_SIZE. When clear the maximum ATU Region size is 4 GB (default). Note: This register field is sticky." "0,1" newline bitfld.long 0x0 9.--10. "ATTR,When the address of an outbound TLP is matched to this region then the ATTR field of the TLP is changed to the value in this register. Note: This register field is sticky." "0,1,2,3" newline bitfld.long 0x0 8. "TD,This is a reserved field. Do not use. Note: This register field is sticky." "0,1" newline bitfld.long 0x0 5.--7. "TC,When the address of an outbound TLP is matched to this region then the TC field of the TLP is changed to the value in this register. Note: This register field is sticky." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x0 0.--4. 1. "TYPE,When the address of an outbound TLP is matched to this region then the TYPE field of the TLP is changed to the value in this register. Note: This register field is sticky." repeat.end repeat 8. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 )(list 0x0 0x200 0x400 0x600 0x800 0xA00 0xC00 0xE00 ) group.long ($2+0x4+0xC0000)++0x3 line.long 0x0 "IATU_REGION_CTRL_2_OFF_OUTBOUND_$1,iATU Region Control 2 Register." bitfld.long 0x0 31. "REGION_EN,Region Enable. This bit must be set to '1' for address translation to take place. Note: This register field is sticky." "0,1" newline bitfld.long 0x0 29. "INVERT_MODE,Invert Mode. When set the address matching region is inverted. Therefore an address match occurs when the untranslated address is in the region outside the defined range (Base Address to Limit Address). Note: This register field is sticky." "0,1" newline bitfld.long 0x0 28. "CFG_SHIFT_MODE,CFG Shift Mode. The iATU uses bits [27:12] of the untranslated address (on the XALI0/1/2 interface or AXI slave interface address) to form the BDF number of the outgoing CFG TLP. This supports the Enhanced Configuration Address Mapping.." "0,1" newline bitfld.long 0x0 27. "DMA_BYPASS,DMA Bypass Mode. Allows request TLPs which are initiated by the DMA controller to pass through the iATU untranslated. Note: This field is reserved for the SW product. You must set it to '0'. Note: This register field is sticky." "0,1" newline bitfld.long 0x0 23. "HEADER_SUBSTITUTE_EN,Header Substitute Enable. When enabled and region address is matched the iATU fully substitutes bytes 8-11 (for 3 DWORD header) or bytes 12-15 (for 4 DWORD header) of the outbound TLP header with the contents of the LWR_TARGET_RW.." "LWR_TARGET_RW in the..,LWR_TARGET_RW in the.." newline bitfld.long 0x0 22. "INHIBIT_PAYLOAD,Inhibit TLP Payload Data for TLP's in Matched Region; assign iATU region to be TLP without data. When enabled and region address is matched the iATU marks all TLPs as having no payload data by forcing the TLP header Fmt[1] bit =0.." "Fmt[1] =0/1 so that TLPs with or without data..,Fmt[1] =0 so that only TLP type without data is.." newline bitfld.long 0x0 21. "TLP_HEADER_FIELDS_BYPASS,TLP Header Fields Translation Bypass. In this mode header fields of the translated TLP is taken from your application transmit interface or if AMBA is configured from the AMBA sideband bus (slv_awmisc_info) and not from the.." "0,1" newline bitfld.long 0x0 20. "SNP,Serialize Non-Posted Requests. In this mode when the AXI Bridge is populated same AXI ID Non-Posted Read/Write Requests are transmitted on the wire if there are no other same ID Non-Posted Requests outstanding. Note: This register field is sticky." "0,1" newline bitfld.long 0x0 19. "FUNC_BYPASS,Function Number Translation Bypass. In this mode the function number of the translated TLP is taken from your application transmit interface and not from the CTRL_1_FUNC_NUM field of the 'iATU Control 1 Register' or the VF_NUMBER field of.." "0,1" newline bitfld.long 0x0 16. "TAG_SUBSTITUTE_EN,TAG Substitute Enable. When enabled and region address is matched the iATU substitutes the TAG field of the outbound TLP header with the contents of the TAG field in this register. The expected usage scenario is translation from AXI.." "0,1" newline hexmask.long.byte 0x0 8.--15. 1. "TAG,TAG. The substituted TAG field (byte 6) in the outgoing TLP header when TAG_SUBSTITUTE_EN is set. Note: This register field is sticky." newline hexmask.long.byte 0x0 0.--7. 1. "MSG_CODE,MSG TLPs (Message Code). When the address of an outbound TLP is matched to this region and the translated TLP TYPE field is Msg or MsgD; then the message field of the TLP is changed to the value in this register. Memory TLPs: (ST;Steering Tag)." repeat.end repeat 8. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 )(list 0x0 0x200 0x400 0x600 0x800 0xA00 0xC00 0xE00 ) group.long ($2+0x8+0xC0000)++0x3 line.long 0x0 "IATU_LWR_BASE_ADDR_OFF_OUTBOUND_$1,iATU Lower Base Address Register. The CX_ATU_MIN_REGION_SIZE configuration parameter (Value Range: 4 kB. 8 kB. 16 kB. 32 kB. 64 kB defaults to 64 kB) specifies the minimum size of an address translation region. For.." hexmask.long.tbyte 0x0 12.--31. 1. "LWR_BASE_RW,Forms bits [31:n] of the start address of the address region to be translated. n is log2(CX_ATU_MIN_REGION_SIZE) Note: This register field is sticky." newline hexmask.long.word 0x0 0.--11. 1. "LWR_BASE_HW,Forms bits [n-1:0] of the start address of the address region to be translated. The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary so these bits are always 0. A write to this location is ignored by the PCIe controller." repeat.end repeat 8. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 )(list 0x0 0x200 0x400 0x600 0x800 0xA00 0xC00 0xE00 ) group.long ($2+0xC+0xC0000)++0x3 line.long 0x0 "IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_$1,iATU Upper Base Address Register." hexmask.long 0x0 0.--31. 1. "UPPER_BASE_RW,Forms bits [63:32] of the start (and end) address of the address region to be translated. In systems with a 32-bit address space this register is not used and therefore writing to this register has no effect. Note: This register field is.." repeat.end repeat 8. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 )(list 0x0 0x200 0x400 0x600 0x800 0xA00 0xC00 0xE00 ) group.long ($2+0x10+0xC0000)++0x3 line.long 0x0 "IATU_LIMIT_ADDR_OFF_OUTBOUND_$1,iATU Limit Address Register." hexmask.long.tbyte 0x0 12.--31. 1. "LIMIT_ADDR_RW,Forms upper bits of the end address of the address region to be translated. Note: This register field is sticky." newline hexmask.long.word 0x0 0.--11. 1. "LIMIT_ADDR_HW,Forms lower bits of the end address of the address region to be translated. The end address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary so these bits are always all ones. A write to this location is ignored by the PCIe.." repeat.end repeat 8. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 )(list 0x0 0x200 0x400 0x600 0x800 0xA00 0xC00 0xE00 ) group.long ($2+0x14+0xC0000)++0x3 line.long 0x0 "IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_$1,iATU Lower Target Address Register." hexmask.long 0x0 0.--31. 1. "LWR_TARGET_RW_OUTBOUND,When HEADER_SUBSTITUTE_EN in IATU_REGION_CTRL_2_OFF_OUTBOUND_ is '0' (normal operation): - LWR_TARGET_RW[31:n] forms MSB's of the Lower Target part of the new address of the translated region; - LWR_TARGET_RW[n-1:0] are not used." repeat.end repeat 8. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 )(list 0x0 0x200 0x400 0x600 0x800 0xA00 0xC00 0xE00 ) group.long ($2+0x18+0xC0000)++0x3 line.long 0x0 "IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_$1,iATU Upper Target Address Register." hexmask.long 0x0 0.--31. 1. "UPPER_TARGET_RW,Forms bits [63:32] of the start address (Upper Target part) of the new address of the translated region. Note: This register field is sticky." repeat.end repeat 8. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 )(list 0x0 0x200 0x400 0x600 0x800 0xA00 0xC00 0xE00 ) group.long ($2+0x1C+0xC0000)++0x3 line.long 0x0 "IATU_REGION_CTRL_3_OFF_OUTBOUND_$1,iATU Region Control 3 Register." bitfld.long 0x0 31. "VF_ACTIVE,Virtual Function Active. Indicates that all of the outbound accesses are from virtual functions. For more details see VF_ACTIVE field. Note: This register field is sticky." "0,1" newline hexmask.long 0x0 3.--30. 1. "RSVDP_VF_NUMBER,Reserved for future use." newline bitfld.long 0x0 0.--2. "VF_NUMBER,Virtual Function Number. When the address of an outbound TLP is matched to this region and the FUNC_BYPASS field in the 'iATU Control 2 Register' is '0' then this field used in generating the Function part of the requester ID (RID) field of.." "0,1,2,3,4,5,6,7" repeat.end repeat 8. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 )(list 0x0 0x200 0x400 0x600 0x800 0xA00 0xC00 0xE00 ) group.long ($2+0x100+0xC0000)++0x3 line.long 0x0 "IATU_REGION_CTRL_1_OFF_INBOUND_$1,iATU Region Control 1 Register." bitfld.long 0x0 20. "CTRL_1_FUNC_NUM,Function Number. - MEM-I/O: When the Address and BAR matching logic in the controller indicate that a MEM-I/O transaction matches a BAR in the function corresponding to this value then address translation proceeds. This check is only.." "?,When the destination function number as.." newline bitfld.long 0x0 13. "INCREASE_REGION_SIZE,Increase the maximum ATU Region size. When set the maximum ATU Region size is determined by CX_ATU_MAX_REGION_SIZE. When clear the maximum ATU Region size is 4 GB (default). Note: This register field is sticky." "0,1" newline bitfld.long 0x0 9.--10. "ATTR,When the ATTR field of an inbound TLP is matched to this value then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the 'ATTR Match Enable' bit of the 'iATU Control 2 Register' is.." "0,1,2,3" newline bitfld.long 0x0 8. "TD,When the TD field of an inbound TLP is matched to this value then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the 'TD Match Enable' bit of the 'iATU Control 2 Register' is set." "0,1" newline bitfld.long 0x0 5.--7. "TC,When the TC field of an inbound TLP is matched to this value then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the 'TC Match Enable' bit of the 'iATU Control 2 Register' is set." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x0 0.--4. 1. "TYPE,When the TYPE field of an inbound TLP is matched to this value then address translation proceeds (when all other enabled field-matches are successful). Note: This register field is sticky." repeat.end repeat 8. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 )(list 0x0 0x200 0x400 0x600 0x800 0xA00 0xC00 0xE00 ) group.long ($2+0x104+0xC0000)++0x3 line.long 0x0 "IATU_REGION_CTRL_2_OFF_INBOUND_$1,iATU Region Control 2 Register." bitfld.long 0x0 31. "REGION_EN,Region Enable. This bit must be set to '1' for address translation to take place. Note: This register field is sticky." "0,1" newline bitfld.long 0x0 30. "MATCH_MODE,Match Mode. Determines Inbound matching mode for TLPs. The mode depends on the type of TLP that is received as follows: For MEM-I/O TLPs this field is interpreted as follows: - 0: Address Match Mode. The iATU operates using addresses as in.." "Address Match Mode,Vendor ID Match Mode" newline bitfld.long 0x0 29. "INVERT_MODE,Invert Mode. When set the address matching region is inverted. Therefore an address match occurs when the untranslated address is in the region outside the defined range (Base Address to Limit Address). Note: This register field is sticky." "0,1" newline bitfld.long 0x0 28. "CFG_SHIFT_MODE,CFG Shift Mode. This is useful for CFG transactions where the PCIe configuration mechanism maps bits [27:12] of the address to the bus/device and function number. This allows a CFG configuration space to be located in any 256MB window of.." "0,1" newline bitfld.long 0x0 27. "FUZZY_TYPE_MATCH_CODE,Fuzzy Type Match Mode. When enabled the iATU relaxes the matching of the TLP TYPE field against the expected TYPE field so that - CfgRd0 and CfgRd1 TLPs are seen as identical. Similarly with CfgWr0 and CfgWr1. - MWr MRd and MRdLk.." "0,1" newline bitfld.long 0x0 26. "VFBAR_MATCH_MODE_EN,VF BAR Match Mode enable. When set Virtual Function BAR matching is used which allows all VFs in a PF which match a BAR to be matched with a single ATU region. Note: This register field is sticky." "0,1" newline bitfld.long 0x0 24.--25. "RESPONSE_CODE,Response Code. Defines the type of response to give for accesses matching this region. This overrides the normal RADM filter response. Note that this feature is not available for any region where Single Address Location Translate is.." "Normal RADM filter response is used,Unsupported request,?,?" newline bitfld.long 0x0 23. "SINGLE_ADDR_LOC_TRANS_EN,Single Address Location Translate Enable. When enabled Rx TLPs can be translated to a single address location as determined by the target address register of the iATU region. The main usage scenario is translation of Messages.." "0,1" newline bitfld.long 0x0 21. "MSG_CODE_MATCH_EN,Message Code Match Enable (Msg TLPS). Ensures that a successful message Code TLP field comparison match (see Message Code field of the 'iATU Control 2 Register') occurs (in MSG transactions) for address translation to proceed. ST Match.." "0,1" newline bitfld.long 0x0 20. "VF_MATCH_EN,Virtual Function Number Match Enable. Ensures that a successful Virtual Function Number TLP field comparison match (see Virtual Function Number field of the 'iATU Control 3 Register') occurs (in MEM-I/O transactions) for address translation.." "0,1" newline bitfld.long 0x0 19. "FUNC_NUM_MATCH_EN,Function Number Match Enable. Ensures that a successful Function Number TLP field comparison match (see Function Number field of the 'iATU Control 1 Register') occurs (in MEM-I/O and CFG0/CFG1 transactions) for address translation to.." "0,1" newline bitfld.long 0x0 16. "ATTR_MATCH_EN,ATTR Match Enable. Ensures that a successful ATTR TLP field comparison match (see ATTR field of the 'iATU Control 1 Register') occurs for address translation to proceed. Note: This register field is sticky." "0,1" newline bitfld.long 0x0 15. "TD_MATCH_EN,TD Match Enable. Ensures that a successful TD TLP field comparison match (see TD field of the 'iATU Control 1 Register') occurs for address translation to proceed. Note: This register field is sticky." "0,1" newline bitfld.long 0x0 14. "TC_MATCH_EN,TC Match Enable. Ensures that a successful TC TLP field comparison match (see TC field of the 'iATU Control 1 Register') occurs for address translation to proceed. Note: This register field is sticky." "0,1" newline bitfld.long 0x0 13. "MSG_TYPE_MATCH_MODE,Message Type Match Mode. When enabled and if single address location translate enable is set then inbound TLPs of type MSG/MSGd which match the type field of the iatu_region_ctrl_1_OFF_inbound register (=>TYPE[4:3]=2'b10) will be.." "0,1" newline bitfld.long 0x0 8.--10. "BAR_NUM,BAR Number. When the BAR number of an inbound MEM or IO TLP ' that is matched by the normal internal BAR address matching mechanism ' is the same as this field address translation proceeds (when all other enabled field-matches are successful)." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x0 0.--7. 1. "MSG_CODE,MSG TLPs: (Message Code). When the TYPE field of an inbound Msg/MsgD TLP is matched to this value then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the 'Message Code Match.." repeat.end repeat 8. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 )(list 0x0 0x200 0x400 0x600 0x800 0xA00 0xC00 0xE00 ) group.long ($2+0x108+0xC0000)++0x3 line.long 0x0 "IATU_LWR_BASE_ADDR_OFF_INBOUND_$1,iATU Lower Base Address Register. The CX_ATU_MIN_REGION_SIZE configuration parameter (Value Range: 4 kB. 8 kB. 16 kB. 32 kB. 64 kB defaults to 64 kB) specifies the minimum size of an address translation region. For.." hexmask.long.tbyte 0x0 12.--31. 1. "LWR_BASE_RW,Forms bits [31:n] of the start address of the address region to be translated. n is log2(CX_ATU_MIN_REGION_SIZE) Note: This register field is sticky." newline hexmask.long.word 0x0 0.--11. 1. "LWR_BASE_HW,Forms bits [n-1:0] of the start address of the address region to be translated. The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary so these bits are always 0. A write to this location is ignored by the PCIe controller." repeat.end repeat 8. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 )(list 0x0 0x200 0x400 0x600 0x800 0xA00 0xC00 0xE00 ) group.long ($2+0x10C+0xC0000)++0x3 line.long 0x0 "IATU_UPPER_BASE_ADDR_OFF_INBOUND_$1,iATU Upper Base Address Register." hexmask.long 0x0 0.--31. 1. "UPPER_BASE_RW,Forms bits [63:32] of the start (and end) address of the address region to be translated. Note: This register field is sticky." repeat.end repeat 8. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 )(list 0x0 0x200 0x400 0x600 0x800 0xA00 0xC00 0xE00 ) group.long ($2+0x110+0xC0000)++0x3 line.long 0x0 "IATU_LIMIT_ADDR_OFF_INBOUND_$1,iATU Limit Address Register." hexmask.long.tbyte 0x0 12.--31. 1. "LIMIT_ADDR_RW,Forms upper bits of the end address of the address region to be translated. Note: This register field is sticky." newline hexmask.long.word 0x0 0.--11. 1. "LIMIT_ADDR_HW,Forms lower bits of the end address of the address region to be translated. The end address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary so these bits are always all ones. A write to this location is ignored by the PCIe.." repeat.end repeat 8. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 )(list 0x0 0x200 0x400 0x600 0x800 0xA00 0xC00 0xE00 ) group.long ($2+0x114+0xC0000)++0x3 line.long 0x0 "IATU_LWR_TARGET_ADDR_OFF_INBOUND_$1,iATU Lower Target Address Register." hexmask.long.tbyte 0x0 12.--31. 1. "LWR_TARGET_RW,Forms MSB's of the Lower Target part of the new address of the translated region. These bits are always '0'. - Field size depends on log2(CX_ATU_MIN_REGION_SIZE) in address match mode. - Field size depends on log2(BAR_MASK+1) in BAR match.." newline hexmask.long.word 0x0 0.--11. 1. "LWR_TARGET_HW,Forms the LSB's of the Lower Target part of the new address of the translated region. The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary (in address match mode); and to the Bar size boundary (in BAR match mode) so.." repeat.end repeat 8. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 )(list 0x0 0x200 0x400 0x600 0x800 0xA00 0xC00 0xE00 ) group.long ($2+0x118+0xC0000)++0x3 line.long 0x0 "IATU_UPPER_TARGET_ADDR_OFF_INBOUND_$1,iATU Upper Target Address Register." hexmask.long 0x0 0.--31. 1. "UPPER_TARGET_RW,Forms bits [63:32] of the start address (Upper Target part) of the new address of the translated region. In systems with a 32-bit address space this register is not used and therefore writing to this register has no effect. Note: This.." repeat.end repeat 8. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 )(list 0x0 0x200 0x400 0x600 0x800 0xA00 0xC00 0xE00 ) group.long ($2+0x11C+0xC0000)++0x3 line.long 0x0 "IATU_REGION_CTRL_3_OFF_INBOUND_$1,iATU Region Control 3 Register." rbitfld.long 0x0 31. "VF_ACTIVE,Reserved. Not used." "0,1" newline hexmask.long 0x0 3.--30. 1. "RSVDP_VF_NUMBER,Reserved for future use." newline bitfld.long 0x0 0.--2. "VF_NUMBER,Virtual Function Number. When the Address and BAR matching logic in the controller indicates that a MEM-I/O transaction matches a BAR in the virtual function corresponding to this value then address translation proceeds. This check is only.." "0,1,2,3,4,5,6,7" repeat.end tree.end tree "PF0_PORT_LOGIC (Port Logic)" group.long (0x0+0x700)++0x27 line.long 0x0 "ACK_LATENCY_TIMER_OFF,Ack Latency Timer and Replay Timer Register." hexmask.long.word 0x0 16.--31. 1. "REPLAY_TIME_LIMIT,Replay Timer Limit. The replay timer expires when it reaches this limit. The controller initiates a replay upon reception of a NAK or when the replay timer expires. For more details see 'Transmit Replay'. You can modify the effective.." newline hexmask.long.word 0x0 0.--15. 1. "ROUND_TRIP_LATENCY_TIME_LIMIT,Ack Latency Timer Limit. The Ack latency timer expires when it reaches this limit. For more details see 'Ack Scheduling'. You can modify the effective timer limit with the TIMER_MOD_ACK_NAK field of the.." line.long 0x4 "VENDOR_SPEC_DLLP_OFF,Vendor Specific DLLP Register." hexmask.long 0x4 0.--31. 1. "VENDOR_SPEC_DLLP,Vendor Specific DLLP Register. Used to send a specific PCI Express DLLP. Your application writes the 8-bit DLLP Type and 24-bits of Payload data into this register then sets the field VENDOR_SPECIFIC_DLLP_REQ of PORT_LINK_CTRL_OFF to.." line.long 0x8 "PORT_FORCE_OFF,Port Force Link Register." hexmask.long.byte 0x8 24.--31. 1. "RSVDP_24,Reserved for future use." newline bitfld.long 0x8 23. "DO_DESKEW_FOR_SRIS,Use the transitions from TS2 to Logical Idle Symbol SKP OS to Logical Idle Symbol EIEOS to Logical Idle Symbol and FTS Sequence to SKP OS to do deskew instead of using received SKP OS or TS1 to TS2 transition if DO_DESKEW_FOR_SRIS.." "0,1" newline rbitfld.long 0x8 22. "RSVDP_22,Reserved for future use." "0,1" newline hexmask.long.byte 0x8 16.--21. 1. "LINK_STATE,Forced LTSSM State. The LTSSM state that the controller is forced to when you set the FORCE_EN bit (Force Link). LTSSM state encoding is defined by the lts_state variable in workspace/src/Layer1/smlh_ltssm.v. Note: This register field is sticky." newline bitfld.long 0x8 15. "FORCE_EN,Force Link. The controller supports a testing and debug capability to allow your software to force the LTSSM state machine into a specific state and to force the controller to transmit a specific Link Command. Asserting this bit triggers the.." "0,1" newline rbitfld.long 0x8 12.--14. "RSVDP_12,Reserved for future use." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x8 8.--11. 1. "FORCED_LTSSM,Forced Link Command. The link command that the controller is forced to transmit when you set FORCE_EN bit (Force Link). Link command encoding is defined by the ltssm_cmd variable in workspace/src/Layer1/smlh_ltssm.v. Note: This register.." newline hexmask.long.byte 0x8 0.--7. 1. "LINK_NUM,Link Number. Not used for endpoint. Not used for M-PCIe. Note: This register field is sticky." line.long 0xC "ACK_F_ASPM_CTRL_OFF,Ack Frequency and L0-L1 ASPM Control Register." rbitfld.long 0xC 31. "RSVDP_31,Reserved for future use." "0,1" newline bitfld.long 0xC 30. "ENTER_ASPM,ASPM L1 Entry Control. - 1: Controller enters ASPM L1 after a period in which it has been idle. - 0: Controller enters ASPM L1 only after idle period during which both receive and transmit are in L0s. Note: This register field is sticky." "Controller enters ASPM L1 only after idle period..,Controller enters ASPM L1 after a period in.." newline bitfld.long 0xC 27.--29. "L1_ENTRANCE_LATENCY,L1 Entrance Latency. Value range is: - 000: 1 us - 001: 2 us - 010: 4 us - 011: 8 us - 100: 16 us - 101: 32 us - 110 or 111: 64 us Note: Programming this timer with a value greater that 32us has no effect unless extended sync is used.." "0,1,2,3,4,5,6,7" newline bitfld.long 0xC 24.--26. "L0S_ENTRANCE_LATENCY,L0s Entrance Latency. Values correspond to: - 000: 1 us - 001: 2 us - 010: 3 us - 011: 4 us - 100: 5 us - 101: 6 us - 110 or 111: 7 us This field is applicable to STALL while in L0 for M-PCIe. Note: This register field is sticky." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0xC 16.--23. 1. "COMMON_CLK_N_FTS,Common Clock N_FTS. This is the N_FTS when common clock is used. The number of Fast Training Sequence ordered sets to be transmitted when transitioning from L0s to L0. The maximum number of FTS ordered-sets that a component can request.." newline hexmask.long.byte 0xC 8.--15. 1. "ACK_N_FTS,N_FTS. The number of Fast Training Sequence ordered sets to be transmitted when transitioning from L0s to L0. The maximum number of FTS ordered-sets that a component can request is 255. The controller does not support a value of zero; a value.." newline hexmask.long.byte 0xC 0.--7. 1. "ACK_FREQ,Ack Frequency. The controller accumulates the number of pending ACKs specified here (up to 255) before scheduling an ACK DLLP. - 0: Indicates that this Ack Frequency Counter feature is turned off. The controller generates a low-priority ACK.." line.long 0x10 "PORT_LINK_CTRL_OFF,Port Link Control Register." hexmask.long.byte 0x10 28.--31. 1. "RSVDP_28,Reserved for future use." newline bitfld.long 0x10 27. "TRANSMIT_LANE_REVERSALE_ENABLE,TRANSMIT_LANE_REVERSALE_ENABLE is an internally reserved field. Do not use. Note: This register field is sticky." "0,1" newline bitfld.long 0x10 26. "EXTENDED_SYNCH,EXTENDED_SYNCH is an internally reserved field. Do not use. Note: This register field is sticky." "0,1" newline bitfld.long 0x10 25. "CORRUPT_LCRC_ENABLE,CORRUPT_LCRC_ENABLE is an internally reserved field. Do not use. Note: This register field is sticky." "0,1" newline bitfld.long 0x10 24. "BEACON_ENABLE,BEACON_ENABLE is an internally reserved field. Do not use. Note: This register field is sticky." "0,1" newline hexmask.long.byte 0x10 16.--21. 1. "LINK_CAPABLE,Link Mode Enable. Sets the number of lanes in the link that you want to connect to the link partner. When you have unused lanes in your system then you must change the value in this register to reflect the number of lanes. You must also.." newline hexmask.long.byte 0x10 12.--15. 1. "RSVDP_12,Reserved for future use." newline hexmask.long.byte 0x10 8.--11. 1. "LINK_RATE,LINK_RATE is an internally reserved field. Do not use. Note: This register field is sticky." newline bitfld.long 0x10 7. "FAST_LINK_MODE,Fast Link Mode. Sets all internal LTSSM millisecond timers to Fast Mode for speeding up simulation. Forces the LTSSM training (link initialization) to use shorter time-outs and to link up faster. The default scaling factor can be changed.." "0,1" newline bitfld.long 0x10 6. "LINK_DISABLE,LINK_DISABLE is an internally reserved field. Do not use. Note: This register field is sticky." "0,1" newline bitfld.long 0x10 5. "DLL_LINK_EN,DLL Link Enable. Enables link initialization. When DLL Link Enable =0 the controller does not transmit InitFC DLLPs and does not establish a link. Note: This register field is sticky." "0,1" newline rbitfld.long 0x10 4. "RSVDP_4,Reserved for future use." "0,1" newline bitfld.long 0x10 3. "RESET_ASSERT,Reset Assert. Triggers a recovery and forces the LTSSM to the hot reset state (downstream port only). Note: This register field is sticky." "0,1" newline bitfld.long 0x10 2. "LOOPBACK_ENABLE,Loopback Enable. Turns on loopback. For more details see 'Loopback'. For M-PCIe to force the master to enter Digital Loopback mode you must set this field to '1' during Configuration.start state(initial discovery/configuration). M-PCIe.." "0,1" newline bitfld.long 0x10 1. "SCRAMBLE_DISABLE,Scramble Disable. Turns off data scrambling. Note: This register field is sticky." "0,1" newline bitfld.long 0x10 0. "VENDOR_SPECIFIC_DLLP_REQ,Vendor Specific DLLP Request. When software writes a '1' to this bit the controller transmits the DLLP contained in the VENDOR_SPEC_DLLP field of VENDOR_SPEC_DLLP_OFF. Reading from this self-clearing register field always.." "0,1" line.long 0x14 "LANE_SKEW_OFF,Lane Skew Register." bitfld.long 0x14 31. "DISABLE_LANE_TO_LANE_DESKEW,Disable Lane-to-Lane Deskew. Causes the controller to disable the internal Lane-to-Lane deskew logic. Note: This register field is sticky." "0,1" newline hexmask.long.byte 0x14 27.--30. 1. "IMPLEMENT_NUM_LANES,Implementation-specific Number of Lanes. Set the implementation-specific number of lanes. Allowed values are: - 4'b0000: 1 lane - 4'b0001: 2 lanes - 4'b0011: 4 lanes - 4'b0111: 8 lanes - 4'b1111: 16 lanes The number of lanes to be.." newline bitfld.long 0x14 26. "ELASTIC_BUFFER_MODE,Selects Elasticity Buffer operating mode: 0: Nominal Half Full Buffer mode 1: Nominal Empty Buffer Mode Note: This register field is sticky." "Nominal Half Full Buffer mode,Nominal Empty Buffer Mode" newline bitfld.long 0x14 25. "ACK_NAK_DISABLE,Ack/Nak Disable. Prevents the controller from sending ACK and NAK DLLPs. Note: This register field is sticky." "0,1" newline bitfld.long 0x14 24. "FLOW_CTRL_DISABLE,Flow Control Disable. Prevents the controller from sending FC DLLPs. Note: This register field is sticky." "0,1" newline hexmask.long.tbyte 0x14 0.--23. 1. "INSERT_LANE_SKEW,INSERT_LANE_SKEW is an internally reserved field. Do not use. Note: This register field is sticky." line.long 0x18 "TIMER_CTRL_MAX_FUNC_NUM_OFF,Timer Control and Max Function Number Register." rbitfld.long 0x18 31. "RSVDP_31,Reserved for future use." "0,1" newline bitfld.long 0x18 29.--30. "FAST_LINK_SCALING_FACTOR,Fast Link Timer Scaling Factor. Sets the scaling factor of LTSSM timer when FAST_LINK_MODE field in PORT_LINK_CTRL_OFF is set to '1'. - 0: Scaling Factor is 1024 (1ms is 1us *a) - 1: Scaling Factor is 256 (1ms is 4us) - 2:.." "Scaling Factor is 1024,Scaling Factor is 256,Scaling Factor is 64,Scaling Factor is 16" newline hexmask.long.byte 0x18 24.--28. 1. "UPDATE_FREQ_TIMER,UPDATE_FREQ_TIMER is an internally reserved field. Do not use. Note: This register field is sticky." newline hexmask.long.byte 0x18 19.--23. 1. "TIMER_MOD_ACK_NAK,Ack Latency Timer Modifier. Increases the timer value for the Ack latency timer in increments of 64 clock cycles. A value of '0' represents no modification to the timer value. For more details see the ROUND_TRIP_LATENCY_TIME_LIMIT.." newline hexmask.long.byte 0x18 14.--18. 1. "TIMER_MOD_REPLAY_TIMER,Replay Timer Limit Modifier. Increases the time-out value for the replay timer in increments of 64 clock cycles at Gen1 or Gen2 speed and in increments of 256 clock cycles at Gen3 speed. A value of '0' represents no modification.." newline hexmask.long.byte 0x18 8.--13. 1. "RSVDP_8,Reserved for future use." newline hexmask.long.byte 0x18 0.--7. 1. "MAX_FUNC_NUM,Maximum function number that can be used in a request. Configuration requests targeted at function numbers above this value are returned with UR (unsupported request). Note: This register field is sticky." line.long 0x1C "SYMBOL_TIMER_FILTER_1_OFF,Symbol Timer Register and Filter Mask 1 Register. The Filter Mask 1 Register modifies the RADM filtering and error handling rules. For more details. see the 'Receive Filtering' section. In each case. '0' applies the associated.." hexmask.long.word 0x1C 16.--31. 1. "MASK_RADM_1,Filter Mask 1. The Filter Mask 1 Register modifies the RADM filtering and error handling rules. For more details see the 'Receive Filtering' section. In each case '0' applies the associated filtering rule and '1' masks the associated.." newline bitfld.long 0x1C 15. "DISABLE_FC_WD_TIMER,Disable FC Watchdog Timer. Note: This register field is sticky." "0,1" newline hexmask.long.byte 0x1C 11.--14. 1. "EIDLE_TIMER,EIDLE_TIMER is an internally reserved field. Do not use. Note: This register field is sticky." newline hexmask.long.word 0x1C 0.--10. 1. "SKP_INT_VAL,SKP Interval Value. The number of symbol times to wait between transmitting SKP ordered sets. Note that the controller actually waits the number of symbol times in this register plus 1 between transmitting SKP ordered sets. Your application.." line.long 0x20 "FILTER_MASK_2_OFF,Filter Mask 2 Register. This register modifies the RADM filtering and error handling rules. For more details. see the 'Receive Filtering' section. In each case. '0' applies the associated filtering rule and '1' masks the associated.." hexmask.long 0x20 0.--31. 1. "MASK_RADM_2,Filter Mask 2. This field modifies the RADM filtering and error handling rules. For more details see the 'Receive Filtering' section. In each case '0' applies the associated filtering rule and '1' masks the associated filtering rule." line.long 0x24 "AMBA_MUL_OB_DECOMP_NP_SUB_REQ_CTRL_OFF,AMBA Multiple Outbound Decomposed NP SubRequests Control Register." hexmask.long 0x24 1.--31. 1. "RSVDP_1,Reserved for future use." newline bitfld.long 0x24 0. "OB_RD_SPLIT_BURST_EN,Enable AMBA Multiple Outbound Decomposed NP SubRequests. This bit when set to '0' disables the possibility of having multiple outstanding non-posted requests that were derived from decomposition of an outbound AMBA request. For more.." "0,1" rgroup.long (0x28+0x700)++0x13 line.long 0x0 "PL_DEBUG0_OFF,Debug Register 0" hexmask.long 0x0 0.--31. 1. "DEB_REG_0,The value on cxpl_debug_info[31:0]." line.long 0x4 "PL_DEBUG1_OFF,Debug Register 1" hexmask.long 0x4 0.--31. 1. "DEB_REG_1,The value on cxpl_debug_info[63:32]." line.long 0x8 "TX_P_FC_CREDIT_STATUS_OFF,Transmit Posted FC Credit Status" hexmask.long.word 0x8 20.--31. 1. "RSVDP_TX_P_FC_CREDIT_STATUS,Reserved for future use." newline hexmask.long.byte 0x8 12.--19. 1. "TX_P_HEADER_FC_CREDIT,Transmit Posted Header FC Credits. The posted Header credits advertised by the receiver at the other end of the link updated with each UpdateFC DLLP. Default value depends on the number of advertised credits for header and data.." newline hexmask.long.word 0x8 0.--11. 1. "TX_P_DATA_FC_CREDIT,Transmit Posted Data FC Credits. The posted Data credits advertised by the receiver at the other end of the link updated with each UpdateFC DLLP. Default value depends on the number of advertised credits for header and data Scaled.." line.long 0xC "TX_NP_FC_CREDIT_STATUS_OFF,Transmit Non-Posted FC Credit Status" hexmask.long.word 0xC 20.--31. 1. "RSVDP_TX_NP_FC_CREDIT_STATUS,Reserved for future use." newline hexmask.long.byte 0xC 12.--19. 1. "TX_NP_HEADER_FC_CREDIT,Transmit Non-Posted Header FC Credits. The non-posted Header credits advertised by the receiver at the other end of the link updated with each UpdateFC DLLP. Default value depends on the number of advertised credits for header and.." newline hexmask.long.word 0xC 0.--11. 1. "TX_NP_DATA_FC_CREDIT,Transmit Non-Posted Data FC Credits. The non-posted Data credits advertised by the receiver at the other end of the link updated with each UpdateFC DLLP. Default value depends on the number of advertised credits for header and data.." line.long 0x10 "TX_CPL_FC_CREDIT_STATUS_OFF,Transmit Completion FC Credit Status" hexmask.long.word 0x10 20.--31. 1. "RSVDP_TX_CPL_FC_CREDIT_STATUS,Reserved for future use." newline hexmask.long.byte 0x10 12.--19. 1. "TX_CPL_HEADER_FC_CREDIT,Transmit Completion Header FC Credits. The Completion Header credits advertised by the receiver at the other end of the link updated with each UpdateFC DLLP. Default value depends on the number of advertised credits for header.." newline hexmask.long.word 0x10 0.--11. 1. "TX_CPL_DATA_FC_CREDIT,Transmit Completion Data FC Credits. The Completion Data credits advertised by the receiver at the other end of the link updated with each UpdateFC DLLP. Default value depends on the number of advertised credits for header and data.." group.long (0x3C+0x700)++0x3 line.long 0x0 "QUEUE_STATUS_OFF,Queue Status" bitfld.long 0x0 31. "TIMER_MOD_FLOW_CONTROL_EN,FC Latency Timer Override Enable. When this bit is set the value from the 'FC Latency Timer Override Value' field in this register will override the FC latency timer value that the controller calculates according to the PCIe.." "0,1" newline rbitfld.long 0x0 29.--30. "RSVDP_29,Reserved for future use." "0,1,2,3" newline hexmask.long.word 0x0 16.--28. 1. "TIMER_MOD_FLOW_CONTROL,FC Latency Timer Override Value. When you set the 'FC Latency Timer Override Enable' in this register the value in this field will override the FC latency timer value that the controller calculates according to the PCIe.." newline rbitfld.long 0x0 13. "RX_SERIALIZATION_Q_NON_EMPTY,Receive Serialization Queue Not Empty. Indicates there is data in the serialization queue." "0,1" newline hexmask.long.word 0x0 4.--12. 1. "RSVDP_4,Reserved for future use." newline bitfld.long 0x0 3. "RX_QUEUE_OVERFLOW,Receive Credit Queue Overflow. Indicates insufficient buffer space available to write to the P/NP/CPL credit queue." "0,1" newline rbitfld.long 0x0 2. "RX_QUEUE_NON_EMPTY,Receive Credit Queue Not Empty. Indicates there is data in one or more of the receive buffers." "0,1" newline rbitfld.long 0x0 1. "TX_RETRY_BUFFER_NE,Transmit Retry Buffer Not Empty. Indicates that there is data in the transmit retry buffer." "0,1" newline rbitfld.long 0x0 0. "RX_TLP_FC_CREDIT_NON_RETURN,Received TLP FC Credits Not Returned. Indicates that the controller has received a TLP but has not yet sent an UpdateFC DLLP indicating that the credits for that TLP have been restored by the receiver at the other end of the.." "0,1" rgroup.long (0x40+0x700)++0x7 line.long 0x0 "VC_TX_ARBI_1_OFF,VC Transmit Arbitration Register 1" hexmask.long.byte 0x0 24.--31. 1. "WRR_WEIGHT_VC_3,WRR Weight for VC3. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R" newline hexmask.long.byte 0x0 16.--23. 1. "WRR_WEIGHT_VC_2,WRR Weight for VC2. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R" newline hexmask.long.byte 0x0 8.--15. 1. "WRR_WEIGHT_VC_1,WRR Weight for VC1. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R" newline hexmask.long.byte 0x0 0.--7. 1. "WRR_WEIGHT_VC_0,WRR Weight for VC0. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R" line.long 0x4 "VC_TX_ARBI_2_OFF,VC Transmit Arbitration Register 2" hexmask.long.byte 0x4 24.--31. 1. "WRR_WEIGHT_VC_7,WRR Weight for VC7. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R" newline hexmask.long.byte 0x4 16.--23. 1. "WRR_WEIGHT_VC_6,WRR Weight for VC6. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R" newline hexmask.long.byte 0x4 8.--15. 1. "WRR_WEIGHT_VC_5,WRR Weight for VC5. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R" newline hexmask.long.byte 0x4 0.--7. 1. "WRR_WEIGHT_VC_4,WRR Weight for VC4. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R" group.long (0x48+0x700)++0xB line.long 0x0 "VC0_P_RX_Q_CTRL_OFF,Segmented-Buffer VC0 Posted Receive Queue Control." bitfld.long 0x0 31. "VC_ORDERING_RX_Q,VC Ordering for Receive Queues. Determines the VC ordering rule for the receive queues used only in the segmented-buffer configuration: - 1: Strict ordering higher numbered VCs have higher priority - 0: Round robin Note: This register.." "Round robin,Strict ordering" newline bitfld.long 0x0 30. "TLP_TYPE_ORDERING_VC0,TLP Type Ordering for VC0. Determines the TLP type ordering rule for VC0 receive queues used only in the segmented-buffer configuration: - 1: PCIe ordering rules (recommended) - 0: Strict ordering: posted completion then.." "Strict ordering: posted,PCIe ordering rules" newline bitfld.long 0x0 28.--29. "RESERVED5,Reserved. Note: This register field is sticky." "0,1,2,3" newline bitfld.long 0x0 26.--27. "VC0_P_DATA_SCALE,VC0 Scale Posted Data Credites. Note: This register field is sticky." "0,1,2,3" newline bitfld.long 0x0 24.--25. "VC0_P_HDR_SCALE,VC0 Scale Posted Header Credites. Note: This register field is sticky." "0,1,2,3" newline bitfld.long 0x0 21.--23. "VC0_P_TLP_Q_MODE,Reserved. Note: This register field is sticky." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 20. "RESERVED4,Reserved. Note: This register field is sticky." "0,1" newline hexmask.long.byte 0x0 12.--19. 1. "VC0_P_HEADER_CREDIT,VC0 Posted Header Credits. The number of initial posted header credits for VC0 used only in the segmented-buffer configuration. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R (sticky) Note: This.." newline hexmask.long.word 0x0 0.--11. 1. "VC0_P_DATA_CREDIT,VC0 Posted Data Credits. The number of initial posted data credits for VC0 used only in the segmented-buffer configuration. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R (sticky) Note: This.." line.long 0x4 "VC0_NP_RX_Q_CTRL_OFF,Segmented-Buffer VC0 Non-Posted Receive Queue Control." hexmask.long.byte 0x4 28.--31. 1. "RESERVED7,Reserved. Note: This register field is sticky." newline bitfld.long 0x4 26.--27. "VC0_NP_DATA_SCALE,VC0 Scale Non-Posted Data Credites. Note: This register field is sticky." "0,1,2,3" newline bitfld.long 0x4 24.--25. "VC0_NP_HDR_SCALE,VC0 Scale Non-Posted Header Credites. Note: This register field is sticky." "0,1,2,3" newline bitfld.long 0x4 21.--23. "VC0_NP_TLP_Q_MODE,Reserved. Note: This register field is sticky." "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 20. "RESERVED6,Reserved. Note: This register field is sticky." "0,1" newline hexmask.long.byte 0x4 12.--19. 1. "VC0_NP_HEADER_CREDIT,VC0 Non-Posted Header Credits. The number of initial non-posted header credits for VC0 used only in the segmented-buffer configuration. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R (sticky).." newline hexmask.long.word 0x4 0.--11. 1. "VC0_NP_DATA_CREDIT,VC0 Non-Posted Data Credits. The number of initial non-posted data credits for VC0 used only in the segmented-buffer configuration. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R (sticky) Note:.." line.long 0x8 "VC0_CPL_RX_Q_CTRL_OFF,Segmented-Buffer VC0 Completion Receive Queue Control." hexmask.long.byte 0x8 28.--31. 1. "RESERVED9,Reserved. Note: This register field is sticky." newline bitfld.long 0x8 26.--27. "VC0_CPL_DATA_SCALE,VC0 Scale CPL Data Credites. Note: This register field is sticky." "0,1,2,3" newline bitfld.long 0x8 24.--25. "VC0_CPL_HDR_SCALE,VC0 Scale CPL Header Credites. Note: This register field is sticky." "0,1,2,3" newline bitfld.long 0x8 21.--23. "VC0_CPL_TLP_Q_MODE,Reserved. Note: This register field is sticky." "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 20. "RESERVED8,Reserved. Note: This register field is sticky." "0,1" newline hexmask.long.byte 0x8 12.--19. 1. "VC0_CPL_HEADER_CREDIT,VC0 Completion Header Credits. The number of initial Completion header credits for VC0 used only in the segmented-buffer configuration. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R (sticky).." newline hexmask.long.word 0x8 0.--11. 1. "VC0_CPL_DATA_CREDIT,VC0 Completion Data Credits. The number of initial Completion data credits for VC0 used only in the segmented-buffer configuration. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R (sticky) Note:.." group.long (0x10C+0x700)++0x3 line.long 0x0 "GEN2_CTRL_OFF,This register is used to control various functions of the controller related to link training. lane reversal. and equalization." rbitfld.long 0x0 31. "RSVDP_31,Reserved for future use." "0,1" newline bitfld.long 0x0 30. "FORCE_LANE_FLIP,Enable to force the LANE_UNDER_TEST physical lane flips to logical lane 0. All the other physical lanes are turned off. The LINK_CAPABLE register must be set to 1 and only x1 link can be formed if the FORCE_LANE_FLIP register is set to 1." "0,1" newline hexmask.long.byte 0x0 24.--27. 1. "LANE_UNDER_TEST,The Lane Under Test is the lane for Forced Lane Flip or for Loopback Eq. The value is from 0 to CX_NL. Only one lane is configured each time. The default of this field is the CX_DEFAULT_LANE_UNDER_TEST configuration parameter. This field.." newline rbitfld.long 0x0 22.--23. "RSVDP_22,Reserved for future use." "0,1,2,3" newline bitfld.long 0x0 21. "GEN1_EI_INFERENCE,Electrical Idle Inference Mode at Gen1 Rate. Programmable mode to determine inferred electrical idle (EI) in Recovery.Speed or Loopback.Active (as slave) state at Gen1 speed by looking for a '1' value on RxElecIdle instead of looking.." "Use RxElecIdle signal to infer Electrical Idle,Use RxValid signal to infer Electrical Idle" newline bitfld.long 0x0 20. "SEL_DEEMPHASIS,Used to set the de-emphasis level for upstream ports. This bit selects the level of de-emphasis the link operates at. - 0: -6 dB - 1: -3.5 dB This field is reserved (fixed to '0') for M-PCIe. Note: The access attributes of this field are.." "0,1" newline bitfld.long 0x0 19. "CONFIG_TX_COMP_RX,Config Tx Compliance Receive Bit. When set to 1 signals LTSSM to transmit TS ordered sets with the compliance receive bit assert (equal to '1'). This field is reserved (fixed to '0') for M-PCIe. Note: The access attributes of this.." "0,1" newline bitfld.long 0x0 18. "CONFIG_PHY_TX_CHANGE,Config PHY Tx Swing. Controls the PHY transmitter voltage swing level. The controller drives the mac_phy_txswing output from this register bit field. - 0: Full Swing - 1: Low Swing This field is reserved (fixed to '0') for M-PCIe." "Full Swing,Low Swing" newline bitfld.long 0x0 17. "DIRECT_SPEED_CHANGE,Directed Speed Change. Writing '1' to this field instructs the LTSSM to initiate a speed change to Gen2 or Gen3 after the link is initialized at Gen1 speed. When the speed change occurs the controller will clear the contents of this.." "0,1" newline bitfld.long 0x0 16. "AUTO_LANE_FLIP_CTRL_EN,Enable Auto flipping of the lanes. You must set the CX_AUTO_LANE_FLIP_CTRL_EN configuration parameter to include the hardware for this feature in the controller. For more details see the 'Lane Reversal' appendix in the Databook." "0,1" newline bitfld.long 0x0 13.--15. "PRE_DET_LANE,Predetermined Lane for Auto Flip. This field defines which physical lane is connected to logical Lane0 by the flip operation performed in Detect. This field is used to restrict the receiver detect procedure to a particular lane when the.." "LANE0,LANE1,LANE3,LANE7,LANE15,?,?,?" newline hexmask.long.byte 0x0 8.--12. 1. "NUM_OF_LANES,Predetermined Number of Lanes. Defines the number of lanes which are connected and not bad. Used to limit the effective link width to ignore 'broken' or 'unused' lanes that detect a receiver. Indicates the number of lanes to check for exit.." newline hexmask.long.byte 0x0 0.--7. 1. "FAST_TRAINING_SEQ,Sets the Number of Fast Training Sequences (N_FTS) that the controller advertises as its N_FTS during Gen2 or Gen3 link training. This value is used to inform the link partner about the PHY's ability to recover synchronization after a.." rgroup.long (0x110+0x700)++0x3 line.long 0x0 "PHY_STATUS_OFF,PHY Status Register. Memory mapped register from phy_cfg_status GPIO input pins." hexmask.long 0x0 0.--31. 1. "PHY_STATUS,PHY Status. Data received directly from the phy_cfg_status bus. These is a GPIO register reflecting the values on the static phy_cfg_status input signals. The usage is left completely to the user and does not in any way influence controller.." group.long (0x114+0x700)++0x3 line.long 0x0 "PHY_CONTROL_OFF,PHY Control Register. Memory mapped register to cfg_phy_control GPIO output pins." hexmask.long 0x0 0.--31. 1. "PHY_CONTROL,PHY Control. Data sent directly to the cfg_phy_control bus. These is a GPIO register driving the values on the static cfg_phy_control output signals. The usage is left completely to the user and does not in any way influence controller.." group.long (0x11C+0x700)++0x77 line.long 0x0 "TRGT_MAP_CTRL_OFF,Programmable Target Map Control Register." hexmask.long.word 0x0 21.--31. 1. "TARGET_MAP_RESERVED_21_31,Reserved. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R (sticky)" newline hexmask.long.byte 0x0 16.--20. 1. "TARGET_MAP_INDEX,The number of the PF Function on which the Target Values are set. This register does not respect the Byte Enable setting. any write will affect all register bits." newline rbitfld.long 0x0 13.--15. "TARGET_MAP_RESERVED_13_15,Reserved. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R (sticky)" "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x0 7.--12. 1. "TARGET_MAP_VF,Target Values for each BAR on the VF Function selected by the index number. This register does not respect the Byte Enable setting. any write will affect all register bits." newline bitfld.long 0x0 6. "TARGET_MAP_ROM,Target Value for the ROM page of the PF Function selected by the index number. This register does not respect the Byte Enable setting. any write will affect all register bits." "0,1" newline hexmask.long.byte 0x0 0.--5. 1. "TARGET_MAP_PF,Target Values for each BAR on the PF Function selected by the index number. This register does not respect the Byte Enable setting. any write will affect all register bits." line.long 0x4 "MSI_CTRL_ADDR_OFF,Integrated MSI Reception Module (iMRM) Address Register." hexmask.long 0x4 0.--31. 1. "MSI_CTRL_ADDR,Integrated MSI Reception Module Address. System specified address for MSI memory write transaction termination. Within the AXI Bridge every received Memory Write request is examined to see if it targets the MSI Address that has been.." line.long 0x8 "MSI_CTRL_UPPER_ADDR_OFF,Integrated MSI Reception Module Upper Address Register." hexmask.long 0x8 0.--31. 1. "MSI_CTRL_UPPER_ADDR,Integrated MSI Reception Module Upper Address. System specified upper address for MSI memory write transaction termination. Allows functions to support a 64-bit MSI address. Note: This register field is sticky." line.long 0xC "MSI_CTRL_INT_0_EN_OFF,Integrated MSI Reception Module Interrupt#i Enable Register." hexmask.long 0xC 0.--31. 1. "MSI_CTRL_INT_0_EN,MSI Interrupt#i Enable. Specifies which interrupts are enabled. When an MSI is received from a disabled interrupt no status bit gets set in MSI controller interrupt status register. Each bit corresponds to a single MSI Interrupt.." line.long 0x10 "MSI_CTRL_INT_0_MASK_OFF,Integrated MSI Reception Module Interrupt#i Mask Register." hexmask.long 0x10 0.--31. 1. "MSI_CTRL_INT_0_MASK,MSI Interrupt#i Mask. Allows enabled interrupts to be masked. When an MSI is received for a masked interrupt the corresponding status bit gets set in the interrupt status register but the msi_ctrl_int output is not set HIGH. Each bit.." line.long 0x14 "MSI_CTRL_INT_0_STATUS_OFF,Integrated MSI Reception Module Interrupt#i Status Register." hexmask.long 0x14 0.--31. 1. "MSI_CTRL_INT_0_STATUS,MSI Interrupt#i Status. When an MSI is detected for EP#i one bit in this register is set. The decoding of the data payload of the MSI Memory Write request determines which bit gets set. A status is bit is cleared by writing a 1 to.." line.long 0x18 "MSI_CTRL_INT_1_EN_OFF,Integrated MSI Reception Module Interrupt#i Enable Register." hexmask.long 0x18 0.--31. 1. "MSI_CTRL_INT_1_EN,MSI Interrupt#i Enable. Specifies which interrupts are enabled. When an MSI is received from a disabled interrupt no status bit gets set in MSI controller interrupt status register. Each bit corresponds to a single MSI Interrupt.." line.long 0x1C "MSI_CTRL_INT_1_MASK_OFF,Integrated MSI Reception Module Interrupt#i Mask Register." hexmask.long 0x1C 0.--31. 1. "MSI_CTRL_INT_1_MASK,MSI Interrupt#i Mask. Allows enabled interrupts to be masked. When an MSI is received for a masked interrupt the corresponding status bit gets set in the interrupt status register but the msi_ctrl_int output is not set HIGH. Each bit.." line.long 0x20 "MSI_CTRL_INT_1_STATUS_OFF,Integrated MSI Reception Module Interrupt#i Status Register." hexmask.long 0x20 0.--31. 1. "MSI_CTRL_INT_1_STATUS,MSI Interrupt#i Status. When an MSI is detected for EP#i one bit in this register is set. The decoding of the data payload of the MSI Memory Write request determines which bit gets set. A status is bit is cleared by writing a 1 to.." line.long 0x24 "MSI_CTRL_INT_2_EN_OFF,Integrated MSI Reception Module Interrupt#i Enable Register." hexmask.long 0x24 0.--31. 1. "MSI_CTRL_INT_2_EN,MSI Interrupt#i Enable. Specifies which interrupts are enabled. When an MSI is received from a disabled interrupt no status bit gets set in MSI controller interrupt status register. Each bit corresponds to a single MSI Interrupt.." line.long 0x28 "MSI_CTRL_INT_2_MASK_OFF,Integrated MSI Reception Module Interrupt#i Mask Register." hexmask.long 0x28 0.--31. 1. "MSI_CTRL_INT_2_MASK,MSI Interrupt#i Mask. Allows enabled interrupts to be masked. When an MSI is received for a masked interrupt the corresponding status bit gets set in the interrupt status register but the msi_ctrl_int output is not set HIGH. Each bit.." line.long 0x2C "MSI_CTRL_INT_2_STATUS_OFF,Integrated MSI Reception Module Interrupt#i Status Register." hexmask.long 0x2C 0.--31. 1. "MSI_CTRL_INT_2_STATUS,MSI Interrupt#i Status. When an MSI is detected for EP#i one bit in this register is set. The decoding of the data payload of the MSI Memory Write request determines which bit gets set. A status is bit is cleared by writing a 1 to.." line.long 0x30 "MSI_CTRL_INT_3_EN_OFF,Integrated MSI Reception Module Interrupt#i Enable Register." hexmask.long 0x30 0.--31. 1. "MSI_CTRL_INT_3_EN,MSI Interrupt#i Enable. Specifies which interrupts are enabled. When an MSI is received from a disabled interrupt no status bit gets set in MSI controller interrupt status register. Each bit corresponds to a single MSI Interrupt.." line.long 0x34 "MSI_CTRL_INT_3_MASK_OFF,Integrated MSI Reception Module Interrupt#i Mask Register." hexmask.long 0x34 0.--31. 1. "MSI_CTRL_INT_3_MASK,MSI Interrupt#i Mask. Allows enabled interrupts to be masked. When an MSI is received for a masked interrupt the corresponding status bit gets set in the interrupt status register but the msi_ctrl_int output is not set HIGH. Each bit.." line.long 0x38 "MSI_CTRL_INT_3_STATUS_OFF,Integrated MSI Reception Module Interrupt#i Status Register." hexmask.long 0x38 0.--31. 1. "MSI_CTRL_INT_3_STATUS,MSI Interrupt#i Status. When an MSI is detected for EP#i one bit in this register is set. The decoding of the data payload of the MSI Memory Write request determines which bit gets set. A status is bit is cleared by writing a 1 to.." line.long 0x3C "MSI_CTRL_INT_4_EN_OFF,Integrated MSI Reception Module Interrupt#i Enable Register." hexmask.long 0x3C 0.--31. 1. "MSI_CTRL_INT_4_EN,MSI Interrupt#i Enable. Specifies which interrupts are enabled. When an MSI is received from a disabled interrupt no status bit gets set in MSI controller interrupt status register. Each bit corresponds to a single MSI Interrupt.." line.long 0x40 "MSI_CTRL_INT_4_MASK_OFF,Integrated MSI Reception Module Interrupt#i Mask Register." hexmask.long 0x40 0.--31. 1. "MSI_CTRL_INT_4_MASK,MSI Interrupt#i Mask. Allows enabled interrupts to be masked. When an MSI is received for a masked interrupt the corresponding status bit gets set in the interrupt status register but the msi_ctrl_int output is not set HIGH. Each bit.." line.long 0x44 "MSI_CTRL_INT_4_STATUS_OFF,Integrated MSI Reception Module Interrupt#i Status Register." hexmask.long 0x44 0.--31. 1. "MSI_CTRL_INT_4_STATUS,MSI Interrupt#i Status. When an MSI is detected for EP#i one bit in this register is set. The decoding of the data payload of the MSI Memory Write request determines which bit gets set. A status is bit is cleared by writing a 1 to.." line.long 0x48 "MSI_CTRL_INT_5_EN_OFF,Integrated MSI Reception Module Interrupt#i Enable Register." hexmask.long 0x48 0.--31. 1. "MSI_CTRL_INT_5_EN,MSI Interrupt#i Enable. Specifies which interrupts are enabled. When an MSI is received from a disabled interrupt no status bit gets set in MSI controller interrupt status register. Each bit corresponds to a single MSI Interrupt.." line.long 0x4C "MSI_CTRL_INT_5_MASK_OFF,Integrated MSI Reception Module Interrupt#i Mask Register." hexmask.long 0x4C 0.--31. 1. "MSI_CTRL_INT_5_MASK,MSI Interrupt#i Mask. Allows enabled interrupts to be masked. When an MSI is received for a masked interrupt the corresponding status bit gets set in the interrupt status register but the msi_ctrl_int output is not set HIGH. Each bit.." line.long 0x50 "MSI_CTRL_INT_5_STATUS_OFF,Integrated MSI Reception Module Interrupt#i Status Register." hexmask.long 0x50 0.--31. 1. "MSI_CTRL_INT_5_STATUS,MSI Interrupt#i Status. When an MSI is detected for EP#i one bit in this register is set. The decoding of the data payload of the MSI Memory Write request determines which bit gets set. A status is bit is cleared by writing a 1 to.." line.long 0x54 "MSI_CTRL_INT_6_EN_OFF,Integrated MSI Reception Module Interrupt#i Enable Register." hexmask.long 0x54 0.--31. 1. "MSI_CTRL_INT_6_EN,MSI Interrupt#i Enable. Specifies which interrupts are enabled. When an MSI is received from a disabled interrupt no status bit gets set in MSI controller interrupt status register. Each bit corresponds to a single MSI Interrupt.." line.long 0x58 "MSI_CTRL_INT_6_MASK_OFF,Integrated MSI Reception Module Interrupt#i Mask Register." hexmask.long 0x58 0.--31. 1. "MSI_CTRL_INT_6_MASK,MSI Interrupt#i Mask. Allows enabled interrupts to be masked. When an MSI is received for a masked interrupt the corresponding status bit gets set in the interrupt status register but the msi_ctrl_int output is not set HIGH. Each bit.." line.long 0x5C "MSI_CTRL_INT_6_STATUS_OFF,Integrated MSI Reception Module Interrupt#i Status Register." hexmask.long 0x5C 0.--31. 1. "MSI_CTRL_INT_6_STATUS,MSI Interrupt#i Status. When an MSI is detected for EP#i one bit in this register is set. The decoding of the data payload of the MSI Memory Write request determines which bit gets set. A status is bit is cleared by writing a 1 to.." line.long 0x60 "MSI_CTRL_INT_7_EN_OFF,Integrated MSI Reception Module Interrupt#i Enable Register." hexmask.long 0x60 0.--31. 1. "MSI_CTRL_INT_7_EN,MSI Interrupt#i Enable. Specifies which interrupts are enabled. When an MSI is received from a disabled interrupt no status bit gets set in MSI controller interrupt status register. Each bit corresponds to a single MSI Interrupt.." line.long 0x64 "MSI_CTRL_INT_7_MASK_OFF,Integrated MSI Reception Module Interrupt#i Mask Register." hexmask.long 0x64 0.--31. 1. "MSI_CTRL_INT_7_MASK,MSI Interrupt#i Mask. Allows enabled interrupts to be masked. When an MSI is received for a masked interrupt the corresponding status bit gets set in the interrupt status register but the msi_ctrl_int output is not set HIGH. Each bit.." line.long 0x68 "MSI_CTRL_INT_7_STATUS_OFF,Integrated MSI Reception Module Interrupt#i Status Register." hexmask.long 0x68 0.--31. 1. "MSI_CTRL_INT_7_STATUS,MSI Interrupt#i Status. When an MSI is detected for EP#i one bit in this register is set. The decoding of the data payload of the MSI Memory Write request determines which bit gets set. A status is bit is cleared by writing a 1 to.." line.long 0x6C "MSI_GPIO_IO_OFF,Integrated MSI Reception Module General Purpose IO Register." hexmask.long 0x6C 0.--31. 1. "MSI_GPIO_REG,MSI GPIO Register. The contents of this register drives the top-level GPIO msi_ctrl_io[31:0] Note: This register field is sticky." line.long 0x70 "CLOCK_GATING_CTRL_OFF,This register enables you to disable dynamic clock gating. By default dynamic clock gating is on. allowing the controller to autonomously enable and disable its clocks. The clock gating is performed in the clock and reset module." hexmask.long 0x70 2.--31. 1. "RSVDP_2,Reserved for future use." newline bitfld.long 0x70 1. "AXI_CLK_GATING_EN,AXI Clock Gating Enable. This register enables the AXI Bridge to autonomously enable and disable the AXI Master clock the AXI Slave clock and the AXI DBI slave clock. The DWC_pcie_clk_rst.v module provides the gated clock.." "Disable,Enable" newline bitfld.long 0x70 0. "RADM_CLK_GATING_EN,RADM Clock Gating Enable. This register if set enables the RADM to autonomously enable and disable its clock. The DWC_pcie_clk_rst.v module provides the gated clock radm_clk_g to the RADM and is enabled when the controllers clock.." "Disable,Enable" line.long 0x74 "GEN3_RELATED_OFF,Gen3 Control Register. There is no Gen3-specific N_FTS field. The N_FTS field in the 'Link Width and Speed Change Control Register' is used for both Gen2 and Gen3 speed modes. There is no Gen3-specific 'Directed Speed Change' field. The.." hexmask.long.byte 0x74 26.--31. 1. "RSVDP_26,Reserved for future use." newline bitfld.long 0x74 23. "GEN3_EQ_INVREQ_EVAL_DIFF_DISABLE,Eq InvalidRequest and RxEqEval Different Time Assertion Disable. Disable the assertion of Eq InvalidRequest and RxEqEval at different time. Note: When CX_GEN4_SPEED/CX_GEN5_SPEED this register is shared for Gen3 and.." "0,1" newline rbitfld.long 0x74 19.--20. "RSVDP_19,Reserved for future use." "0,1,2,3" newline bitfld.long 0x74 18. "GEN3_DC_BALANCE_DISABLE,DC Balance Disable. Disable DC Balance feature. Note: When CX_GEN4_SPEED/CX_GEN5_SPEED this register is shared for Gen3 and Gen4/Gen5 data rate. Note: This register field is sticky." "0,1" newline bitfld.long 0x74 17. "GEN3_DLLP_XMT_DELAY_DISABLE,DLLP Transmission Delay Disable. Disable delay transmission of DLLPs before equalization. Note: When CX_GEN4_SPEED/CX_GEN5_SPEED this register is shared for Gen3 and Gen4/Gen5 data rate. Note: This register field is sticky." "0,1" newline bitfld.long 0x74 16. "GEN3_EQUALIZATION_DISABLE,Equalization Disable. Disable equalization feature. This bit cannot be changed once the LTSSM starts link training. Note: When CX_GEN4_SPEED/CX_GEN5_SPEED this register is shared for Gen3 and Gen4/Gen5 data rate. Note: This.." "0,1" newline rbitfld.long 0x74 14.--15. "RSVDP_14,Reserved for future use." "0,1,2,3" newline bitfld.long 0x74 13. "RXEQ_RGRDLESS_RXTS,When set to '1' the controller as Gen3 EQ master asserts RxEqEval to instruct the PHY to do Rx adaptation and evaluation after a 500ns timeout from a new preset request. - 0: mac_phy_rxeqeval asserts after 1us and 2 TS1 received from.." "mac_phy_rxeqeval asserts after 1us and 2 TS1..,mac_phy_rxeqeval asserts after 500ns regardless.." newline bitfld.long 0x74 12. "RXEQ_PH01_EN,Rx Equalization Phase 0/Phase 1 Hold Enable. When this bit is set the upstream port holds phase 0 (the downstream port holds phase 1) for 10ms. Holding phase 0 or phase 1 can be used to allow sufficient time for Rx Equalization to be.." "Tx equalization only in phase 2/3,No Tx equalization" newline bitfld.long 0x74 11. "EQ_REDO,Equalization Redo Disable. Disable autonomous mechanism for requesting to redo the equalization process. The received presets or coefficients mismatch in Recovery.RcvrLock after Recovery EQ phases causes the EQ redo requests. If the EQ redo is.." "0,1" newline bitfld.long 0x74 10. "EQ_EIEOS_CNT,Equalization EIEOS Count Reset Disable. Disable requesting reset of EIEOS count during equalization. Note: When CX_GEN4_SPEED/CX_GEN5_SPEED this register is shared for Gen3 and Gen4/Gen5 data rate. Note: This register field is sticky." "0,1" newline bitfld.long 0x74 9. "EQ_PHASE_2_3,Equalization Phase 2 and Phase 3 Disable. This applies to downstream ports only. Note: When CX_GEN4_SPEED/CX_GEN5_SPEED this register is shadow register for Gen3 and Gen4/Gen5 data rate. If RATE_SHADOW_SEL==00b this register is for Gen3.." "0,1" newline bitfld.long 0x74 8. "DISABLE_SCRAMBLER_GEN_3,Disable Scrambler for Gen3 and Gen4 Data Rate. The Gen3 and Gen4 scrambler/descrambler within the controller needs to be disabled when the scrambling function is implemented outside of the controller (for example within the PHY)." "0,1" newline hexmask.long.byte 0x74 1.--7. 1. "RSVDP_1,Reserved for future use." newline bitfld.long 0x74 0. "GEN3_ZRXDC_NONCOMPL,Gen3 Receiver Impedance ZRX-DC Not Compliant. Receivers that operate at 8.0 GT/s with an impedance other than the range defined by the ZRX-DC parameter for 2.5 GT/s (40-60 Ohms) must meet additional behavior requirements in the.." "The receiver complies with the ZRX-DC parameter..,The receiver does not comply with the ZRX-DC.." group.long (0x1A8+0x700)++0x7 line.long 0x0 "GEN3_EQ_CONTROL_OFF,Gen3 EQ Control Register. This register controls equalization for Phase2 in an upstream port (USP). or Phase3 in a downstream port (DSP). M-PCIe doesn't have Conventional PCIe Gen3 feature. The registers of this section do not exist." hexmask.long.byte 0x0 27.--31. 1. "RSVDP_27,Reserved for future use." newline bitfld.long 0x0 26. "GEN3_REQ_SEND_CONSEC_EIEOS_FOR_PSET_MAP,Request controller to send back-to-back EIEOS in Recovery.RcvrLock state until presets to coefficients mapping is complete. - 0: Do not request - 1: request Note: Gen3 and Gen4 share the same register bit and have.." "Do not request,request" newline bitfld.long 0x0 25. "GEN3_EQ_PSET_REQ_AS_COEF,GEN3_EQ_PSET_REQ_AS_COEF is an internally reserved field. Do not use. Note: This register field is sticky." "0,1" newline bitfld.long 0x0 24. "GEN3_EQ_FOM_INC_INITIAL_EVAL,Include Initial FOM. Include or not the FOM feedback from the initial preset evaluation performed in the EQ Master when finding the highest FOM among all preset evaluations. - 0: Do not include - 1: Include Note: When.." "Do not include,Include" newline hexmask.long.word 0x0 8.--23. 1. "GEN3_EQ_PSET_REQ_VEC,Preset Request Vector. Requesting of Presets during the initial part of the EQ Master Phase. Encoding scheme is as follows: Bit [15:0] =0x0: No preset is requested and evaluated in EQ Master Phase. Bit [i] =1: 'Preset=i' is requested.." newline rbitfld.long 0x0 7. "RSVDP_7,Reserved for future use." "0,1" newline bitfld.long 0x0 6. "GEN3_LOWER_RATE_EQ_REDO_ENABLE,Support EQ redo and lower rate change: - 0: not support - 1: support Note: Gen3 and Gen4 share the same register bit and have the same feature. Note: This register field is sticky." "not support,support" newline bitfld.long 0x0 5. "GEN3_EQ_EVAL_2MS_DISABLE,Phase2_3 2 ms Timeout Disable. Determine behavior in Phase2 for USP (Phase3 if DSP) when the PHY does not respond within 2ms to the assertion of RxEqEval: - 0: abort the current evaluation stop any attempt to modify the remote.." "abort the current evaluation,ignore the 2ms timeout and continue as normal" newline bitfld.long 0x0 4. "GEN3_EQ_PHASE23_EXIT_MODE,Behavior After 24 ms Timeout (when optimal settings are not found). For a USP: Determine next LTSSM state from Phase2 after 24ms Timeout - 0: Recovery.Speed - 1: Recovery.Equalization.Phase3 When optimal settings are not found.." "Equalization Phase 3 Successful status bit is..,Recovery" newline hexmask.long.byte 0x0 0.--3. 1. "GEN3_EQ_FB_MODE,Feedback Mode. - 0000b: Direction Change - 0001b: Figure Of Merit - 0010b: Reserved - .....: Reserved - 1111b: Reserved Note: When CX_GEN4_SPEED/CX_GEN5_SPEED this register is a shadow register for Gen3 and Gen4/Gen5 data rate. If.." line.long 0x4 "GEN3_EQ_FB_MODE_DIR_CHANGE_OFF,Gen3 EQ Direction Change Feedback Mode Control Register. Equalization controls to be used in Phase2 (USP) or Phase 3 (DSP). when you set the Feedback Mode in 'Gen3 EQ Control Register' to 'Direction Change.' These fields.." hexmask.long.word 0x4 18.--31. 1. "RSVDP_18,Reserved for future use." newline hexmask.long.byte 0x4 14.--17. 1. "GEN3_EQ_FMDC_MAX_POST_CUSROR_DELTA,Convergence Window Aperture for C+1. Post-cursor coefficients maximum delta within the convergence window depth. Allowed range: 0 1 2 ..15. Note: When CX_GEN4_SPEED/CX_GEN5_SPEED this register is shadow register for.." newline hexmask.long.byte 0x4 10.--13. 1. "GEN3_EQ_FMDC_MAX_PRE_CUSROR_DELTA,Convergence Window Aperture for C-1. Pre-cursor coefficients maximum delta within the convergence window depth. Allowed range: 0 1 2 ..15. Note: When CX_GEN4_SPEED/CX_GEN5_SPEED this register is shadow register for Gen3.." newline hexmask.long.byte 0x4 5.--9. 1. "GEN3_EQ_FMDC_N_EVALS,Convergence Window Depth. Number of consecutive evaluations considered in Phase 2/3 when determining if optimal coefficients have been found. Allowed range: 0 1 2 ..16 up to a maximum of CX_GEN3_EQ_COEFQ_DEPTH. When set to 0 EQ.." newline hexmask.long.byte 0x4 0.--4. 1. "GEN3_EQ_FMDC_T_MIN_PHASE23,Minimum Time (in ms) To Remain in EQ Master Phase. The LTSSM stays in EQ Master phase for at least this amount of time before starting to check for convergence of the coefficients. Allowed values 0 1 ... 24. Note: When.." group.long (0x1B4+0x700)++0x27 line.long 0x0 "ORDER_RULE_CTRL_OFF,Order Rule Control Register." hexmask.long.word 0x0 16.--31. 1. "RSVDP_16,Reserved for future use." newline hexmask.long.byte 0x0 8.--15. 1. "CPL_PASS_P,Completion Passing Posted Ordering Rule Control. Determines if CPL can pass halted P queue. - 0: CPL can not pass P (recommended) - 1: CPL can pass P" newline hexmask.long.byte 0x0 0.--7. 1. "NP_PASS_P,Non-Posted Passing Posted Ordering Rule Control. Determines if NP can pass halted P queue. - 0 : NP can not pass P (recommended). - 1 : NP can pass P" line.long 0x4 "PIPE_LOOPBACK_CONTROL_OFF,PIPE Loopback Control Register." bitfld.long 0x4 31. "PIPE_LOOPBACK,PIPE Loopback Enable. Indicates RMMI Loopback if M-PCIe. Note: This register field is sticky." "0,1" newline hexmask.long.byte 0x4 27.--30. 1. "RSVDP_27,Reserved for future use." newline bitfld.long 0x4 24.--26. "RXSTATUS_VALUE,RXSTATUS_VALUE is an internally reserved field. Do not use." "0,1,2,3,4,5,6,7" newline rbitfld.long 0x4 22.--23. "RSVDP_22,Reserved for future use." "0,1,2,3" newline hexmask.long.byte 0x4 16.--21. 1. "RXSTATUS_LANE,RXSTATUS_LANE is an internally reserved field. Do not use. Note: This register field is sticky." newline hexmask.long.word 0x4 0.--15. 1. "LPBK_RXVALID,LPBK_RXVALID is an internally reserved field. Do not use. Note: This register field is sticky." line.long 0x8 "MISC_CONTROL_1_OFF,DBI Read-Only Write Enable Register." hexmask.long.word 0x8 22.--31. 1. "RSVDP_22,Reserved for future use." newline bitfld.long 0x8 21. "P2P_ERR_RPT_CTRL,Determines whether to track completion of transmitted Non-Posted TLPs in P2P mode. - 0: Do not track completion - 1: Track completion Note: This register field is sticky." "Do not track completion,Track completion" newline bitfld.long 0x8 20. "P2P_TRACK_CPL_TO_REG,Determines whether to enable Peer to Peer (P2P) error reporting. - 0: Disable P2P error reporting - 1: Enable P2P error reporting Note: This register field is sticky." "Disable P2P error reporting,Enable P2P error reporting" newline bitfld.long 0x8 18.--19. "TARGET_ABOVE_CONFIG_LIMIT_REG,Configuration requests with an address greater than CONFIG_LIMIT_REG are directed to either ELBI or TRGT1 interface based on the setting of this field. This field can have the following values: - 1: ELBI - 2: TRGT1 Note:.." "?,ELBI,TRGT1,?" newline hexmask.long.word 0x8 8.--17. 1. "CONFIG_LIMIT_REG,Configuration requests are directed either to CDM or ELBI/RTRGT1 based on the value of this field. - Configuration requests with an address less CONFIG_LIMIT_REG are directed to the CDM - Configuration requests with an address greater.." newline bitfld.long 0x8 7. "CFG_TLP_BYPASS_EN_REG,Setting of this field defines which field TARGET_ABOVE_CONFIG_LIMIT_REG or CONFIG_LIMIT_REG decides the destination of Configuration requests. This field can have the following values: - 0: Configuration TLPs are routed according to.." "Configuration TLPs are routed according to the..,Configuration TLPs are routed according to the.." newline bitfld.long 0x8 6. "CPLQ_MNG_EN,This field enables the Completion Queue Management feature. Note: This register field is sticky." "0,1" newline bitfld.long 0x8 5. "ARI_DEVICE_NUMBER,When ARI is enabled this field enables use of the device ID. Note: This register field is sticky." "0,1" newline bitfld.long 0x8 4. "DISABLE_AUTO_LTR_CLR_MSG,Disable the autonomous generation of LTR clear message in upstream port. This field can have the following values: - 0: Allow the autonomous generation of LTR clear message. - 1: Disable the autonomous generation of LTR clear.." "Allow the autonomous generation of LTR clear..,Disable the autonomous generation of LTR clear.." newline bitfld.long 0x8 3. "SIMPLIFIED_REPLAY_TIMER,Enables Simplified Replay Timer (Gen4). For more details see 'Transmit Replay' in 'Transmit TLP Processing' section in the 'Controller Operations' chapter of the Databook. Simplified Replay Timer can have the following Values: -.." "0,1" newline bitfld.long 0x8 2. "UR_CA_MASK_4_TRGT1,When this field is set to '1' the controller suppresses error logging error message generation and CPL generation for non-posted requests TLPs (with UR filtering status) forwarded to your application (that is when DEFAULT_TARGET.." "0,1" newline bitfld.long 0x8 1. "DEFAULT_TARGET,Default target for an IO or MEM request with UR/CA/CRS received. Based on the value of this field the controller either drops or forwards these requests to your application. - 0: The controller drops all incoming I/O or MEM requests (after.." "The controller drops all incoming I/O or MEM..,The controller forwards all incoming I/O or MEM.." newline bitfld.long 0x8 0. "DBI_RO_WR_EN,Write to RO Registers Using DBI. Your application can write to some RO and HwInit register fields through the DBI when you set this field to '1'. For more details see 'Writing to Read-Only Registers' in 'Register Module LBC and DBI'.." "0,1" line.long 0xC "MULTI_LANE_CONTROL_OFF,UpConfigure Multi-lane Control Register. Used when upsizing or downsizing the link width through Configuration state without bringing the link down. For more details. see the 'Link Establishment' section in the 'Controller.." hexmask.long.tbyte 0xC 8.--31. 1. "RSVDP_8,Reserved for future use." newline bitfld.long 0xC 7. "UPCONFIGURE_SUPPORT,Upconfigure Support. The controller sends this value as the Link Upconfigure Capability in TS2 Ordered Sets in Configuration.Complete state. This field is reserved (fixed to '0') for M-PCIe. Note: This register field is sticky." "0,1" newline bitfld.long 0xC 6. "DIRECT_LINK_WIDTH_CHANGE,Directed Link Width Change. The controller always moves to Configuration state through Recovery state when this bit is set to '1'. - If the upconfigure_capable variable is '1' and the PCIE_CAP_HW_AUTO_WIDTH_DISABLE bit in.." "0,1" newline hexmask.long.byte 0xC 0.--5. 1. "TARGET_LINK_WIDTH,Target Link Width. Values correspond to: - 6'b000000: Controller does not start upconfigure or autonomous width downsizing in the Configuration state. - 6'b000001: x1 - 6'b000010: x2 - 6'b000100: x4 - 6'b001000: x8 - 6'b010000: x16 -.." line.long 0x10 "PHY_INTEROP_CTRL_OFF,PHY Interoperability Control Register." hexmask.long.tbyte 0x10 12.--31. 1. "RSVDP_12,Reserved for future use." newline bitfld.long 0x10 10. "L1_CLK_SEL,L1 Clock control bit. This field is reserved for internal use. You should not write to this field and change the default unless specifically instructed by Synopsys support. - 1: Controller does not request aux_clk switch and core_clk gating in.." "Controller requests aux_clk switch and core_clk..,Controller does not request aux_clk switch and.." newline rbitfld.long 0x10 9. "L1_NOWAIT_P1,L1 entry control bit. This field is reserved for internal use. You should not write to this field and change the default unless specifically instructed by Synopsys support. - 1: Controller does not wait for PHY to acknowledge transition to.." "Controller waits for the PHY to acknowledge..,Controller does not wait for PHY to acknowledge.." newline bitfld.long 0x10 8. "L1SUB_EXIT_MODE,L1 Exit Control Using phy_mac_pclkack_n. This field is reserved for internal use. You should not write to this field and change the default unless specifically instructed by Synopsys support. - 1: Controller exits L1 without waiting for.." "Controller waits for the PHY to assert..,Controller exits L1 without waiting for the PHY.." newline rbitfld.long 0x10 7. "RSVDP_7,Reserved for future use." "0,1" newline hexmask.long.byte 0x10 0.--6. 1. "RXSTANDBY_CONTROL,Rxstandby Control. Bits 0..5 determine if the controller asserts the RxStandby signal (mac_phy_rxstandby) in the indicated condition. Bit 6 enables the controller to perform the RxStandby/RxStandbyStatus handshake. This field is.." line.long 0x14 "TRGT_CPL_LUT_DELETE_ENTRY_OFF,TRGT_CPL_LUT Delete Entry Control register. Using this register you can delete one entry in the target completion LUT. You should only use this register when you know that your application will never send the completion.." bitfld.long 0x14 31. "DELETE_EN,This is a one-shot bit. A '1' write to this bit triggers the deletion of the target completion LUT entry that is specified in the LOOK_UP_ID field. This is a self-clearing register field. Reading from this register field always returns a '0'." "0,1" newline hexmask.long 0x14 0.--30. 1. "LOOK_UP_ID,This number selects one entry to delete of the TRGT_CPL_LUT." line.long 0x18 "LINK_FLUSH_CONTROL_OFF,Link Reset Request Flush Control Register." hexmask.long.byte 0x18 24.--31. 1. "RSVD_I_8,This is an internally reserved field. Do not use. Note: This register field is sticky." newline hexmask.long.tbyte 0x18 1.--23. 1. "RSVDP_1,Reserved for future use." newline bitfld.long 0x18 0. "AUTO_FLUSH_EN,Enables automatic flushing of pending requests before sending the reset request to the application logic to reset the PCIe controller and the AXI Bridge. The flushing process is initiated if any of the following events occur: - Hot reset.." "0,1" line.long 0x1C "AMBA_ERROR_RESPONSE_DEFAULT_OFF,AXI Bridge Slave Error Response Register." hexmask.long.word 0x1C 16.--31. 1. "RSVDP_16,Reserved for future use." newline hexmask.long.byte 0x1C 10.--15. 1. "AMBA_ERROR_RESPONSE_MAP,AXI Slave Response Error Map. Allows you to selectively map the errors received from the PCIe completion (for non-posted requests) to the AXI slave responses slv_rresp or slv_bresp. The recommended setting is SLVERR. CRS is.." newline hexmask.long.byte 0x1C 5.--9. 1. "RSVDP_5,Reserved for future use." newline bitfld.long 0x1C 3.--4. "AMBA_ERROR_RESPONSE_CRS,CRS Slave Error Response Mapping. Determines the AXI slave response for CRS completions. For more details see 'Error Handling' in the AXI chapter of the Databook. AHB: - always returns OKAY AXI: - 00: OKAY - 01: OKAY with all.." "OKAY,OKAY with all FFFF_FFFF data for all CRS..,?,?" newline bitfld.long 0x1C 2. "AMBA_ERROR_RESPONSE_VENDORID,Vendor ID Non-existent Slave Error Response Mapping. Determines the AXI slave response for errors on reads to non-existent Vendor ID register. For more details see 'Error Handling' in the AXI chapter of the Databook. AHB: -.." "OKAY,SLVERR/DECERR" newline rbitfld.long 0x1C 1. "RSVDP_1,Reserved for future use." "0,1" newline bitfld.long 0x1C 0. "AMBA_ERROR_RESPONSE_GLOBAL,Global Slave Error Response Mapping. Determines the AXI slave response for all error scenarios on non-posted requests. For more details see 'Error Handling' in the AXI chapter of the Databook. AHB: - 0: OKAY (with FFFF data for.." "OKAY,SLVERR/DECERR" line.long 0x20 "AMBA_LINK_TIMEOUT_OFF,Link Down AXI Bridge Slave Timeout Register. If your application AXI master issues outbound requests to the AXI bridge slave interface before the PCIe link is operational. the controller starts a 'flush' timer. The timeout value of.." hexmask.long.tbyte 0x20 9.--31. 1. "RSVDP_9,Reserved for future use." newline bitfld.long 0x20 8. "LINK_TIMEOUT_ENABLE_DEFAULT,Disable Flush. You can disable the flush feature by setting this field to '1'. Note: This register field is sticky." "0,1" newline hexmask.long.byte 0x20 0.--7. 1. "LINK_TIMEOUT_PERIOD_DEFAULT,Timeout Value (ms). The timer will timeout and then flush the bridge TX request queues after this amount of time. The timer counts when there are pending outbound AXI slave interface requests and the PCIe TX link is not.." line.long 0x24 "AMBA_ORDERING_CTRL_OFF,AMBA Ordering Control." hexmask.long.tbyte 0x24 8.--31. 1. "RSVDP_8,Reserved for future use." newline bitfld.long 0x24 7. "AX_MSTR_ZEROLREAD_FW,AXI Master Zero Length Read Forward to the application. The DW PCIe controller AXI bridge is able to terminate in order with the Posted transactions the zero length read implementing the PCIe express flush semantics of the Posted.." "The zero length Read is terminated at the DW..,The zero length Read is forward to the application" newline rbitfld.long 0x24 5.--6. "RSVDP_5,Reserved for future use." "0,1,2,3" newline bitfld.long 0x24 3.--4. "AX_MSTR_ORDR_P_EVENT_SEL,AXI Master Posted Ordering Event Selector. This field selects how the master interface determines when a P write is completed when enforcing the PCIe ordering rule 'NP must not pass P' at the AXI Master Interface. The AXI.." "B'last event: wait for the all of the write..,AW'last event: wait until the complete Posted..,This setting will not affect:,?" newline rbitfld.long 0x24 2. "RSVDP_2,Reserved for future use." "0,1" newline bitfld.long 0x24 1. "AX_SNP_EN,AXI Serialize Non-Posted Requests Enable. This field enables the AXI Bridge to serialize same ID Non-Posted Read/Write Requests on the wire. Serialization implies one outstanding same ID NP Read or Write on the wire and used to avoid AXI RAR.." "0,1" newline rbitfld.long 0x24 0. "RSVDP_0,Reserved for future use." "0,1" group.long (0x1E0+0x700)++0xB line.long 0x0 "COHERENCY_CONTROL_1_OFF,ACE Cache Coherency Control Register 1" hexmask.long 0x0 2.--31. 1. "CFG_MEMTYPE_BOUNDARY_LOW_ADDR,Boundary Lower Address For Memory Type. Bits [31:0] of dword-aligned address of the boundary for Memory type. The two lower address LSBs are '00'. Addresses up to but not including this value are in the lower address space.." newline rbitfld.long 0x0 1. "RSVDP_1,Reserved for future use." "0,1" newline bitfld.long 0x0 0. "CFG_MEMTYPE_VALUE,Sets the memory type for the lower and upper parts of the address space: - 0: lower = Peripheral; upper = Memory - 1: lower = Memory type; upper = Peripheral Note: This register field is sticky." "lower = Peripheral; upper = Memory,lower = Memory type; upper = Peripheral" line.long 0x4 "COHERENCY_CONTROL_2_OFF,ACE Cache Coherency Control Register 2" hexmask.long 0x4 0.--31. 1. "CFG_MEMTYPE_BOUNDARY_HIGH_ADDR,Boundary Upper Address For Memory Type. Bits [63:32] of the 64-bit dword-aligned address of the boundary for Memory type. Note: This register field is sticky." line.long 0x8 "COHERENCY_CONTROL_3_OFF,ACE Cache Coherency Control Register 3" hexmask.long.byte 0x8 27.--30. 1. "CFG_MSTR_AWCACHE_VALUE,Master Write CACHE Signal Value. Value of the individual bits in mstr_awcache when CFG_MSTR_AWCACHE_MODE is '1'. Note: not applicable to message requests; for message requests the value of mstr_awcache is always '0000' Note: This.." newline hexmask.long.byte 0x8 19.--22. 1. "CFG_MSTR_ARCACHE_VALUE,Master Read CACHE Signal Value. Value of the individual bits in mstr_arcache when CFG_MSTR_ARCACHE_MODE is '1'. Note: This register field is sticky." newline hexmask.long.byte 0x8 11.--14. 1. "CFG_MSTR_AWCACHE_MODE,Master Write CACHE Signal Behavior. Defines how the individual bits in mstr_awcache are controlled: - 0: set automatically by the AXI master - 1: set by the value of the corresponding bit of the CFG_MSTR_AWCACHE_VALUE field Note:.." newline hexmask.long.byte 0x8 3.--6. 1. "CFG_MSTR_ARCACHE_MODE,Master Read CACHE Signal Behavior. Defines how the individual bits in mstr_arcache are controlled: - 0: set automatically by the AXI master - 1: set by the value of the corresponding bit of the CFG_MSTR_ARCACHE_VALUE field Note:.." group.long (0x1F0+0x700)++0x7 line.long 0x0 "AXI_MSTR_MSG_ADDR_LOW_OFF,Lower 20 bits of the programmable AXI address where Messages coming from wire are mapped to. Bits [11:0] of the register are tied to zero for the address to be 4k-aligned. In previous releases. the third and fourth DWORDs of a.." hexmask.long.tbyte 0x0 12.--31. 1. "CFG_AXIMSTR_MSG_ADDR_LOW,Lower 20 bits of the programmable AXI address for Messages. Note: This register field is sticky." newline hexmask.long.word 0x0 0.--11. 1. "CFG_AXIMSTR_MSG_ADDR_LOW_RESERVED,Reserved for future use. Note: This register field is sticky." line.long 0x4 "AXI_MSTR_MSG_ADDR_HIGH_OFF,Upper 32 bits of the programmable AXI address where Messages coming from wire are mapped to." hexmask.long 0x4 0.--31. 1. "CFG_AXIMSTR_MSG_ADDR_HIGH,Upper 32 bits of the programmable AXI address for Messages. Note: This register field is sticky." rgroup.long (0x1F8+0x700)++0x7 line.long 0x0 "PCIE_VERSION_NUMBER_OFF,PCIe Controller IIP Release Version Number. The version number is given in hex format. You should convert each pair of hex characters to ASCII to interpret. Using 4.70a (GA) as an example: - VERSION_NUMBER = 0x3437302a which.." hexmask.long 0x0 0.--31. 1. "VERSION_NUMBER,Version Number." line.long 0x4 "PCIE_VERSION_TYPE_OFF,PCIe Controller IIP Release Version Type. The type is given in hex format. You should convert each pair of hex characters to ASCII to interpret. Using 4.70a (GA) as an example: - VERSION_NUMBER = 0x3437302a which translates to 470*.." hexmask.long 0x4 0.--31. 1. "VERSION_TYPE,Version Type." group.long (0x240+0x700)++0x7 line.long 0x0 "MSIX_ADDRESS_MATCH_LOW_OFF,MSI-X Address Match Low Register. When you enable the MSI-X Table RAM feature (MSIX_TABLE_EN=1). the controller implements the logic and RAM required to generate MSI-X requests. For more details. see the Interrupts section in.." hexmask.long 0x0 2.--31. 1. "MSIX_ADDRESS_MATCH_LOW,MSI-X Address Match Low Address. Note: This register field is sticky." newline rbitfld.long 0x0 1. "MSIX_ADDRESS_MATCH_RESERVED_1,Reserved. Note: This register field is sticky." "0,1" newline bitfld.long 0x0 0. "MSIX_ADDRESS_MATCH_EN,MSI-X Match Enable. Enable the MSI-X Address Match feature when the AXI bridge is present. Note: This register field is sticky." "0,1" line.long 0x4 "MSIX_ADDRESS_MATCH_HIGH_OFF,MSI-X Address Match High Register. When you enable the MSI-X Table RAM feature (MSIX_TABLE_EN=1). the controller implements the logic and RAM required to generate MSI-X requests. For more details. see the Interrupts section in.." hexmask.long 0x4 0.--31. 1. "MSIX_ADDRESS_MATCH_HIGH,MSI-X Address Match High Address. Note: This register field is sticky." wgroup.long (0x248+0x700)++0x3 line.long 0x0 "MSIX_DOORBELL_OFF,MSI-X Doorbell Register. When you enable the MSI-X Table RAM feature (MSIX_TABLE_EN=1). the controller implements the logic and RAM required to generate MSI-X requests. For more details. see the Interrupts section in the 'Controller.." bitfld.long 0x0 29.--31. "MSIX_DOORBELL_RESERVED_29_31,Reserved." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x0 24.--28. 1. "MSIX_DOORBELL_PF,MSIX Doorbell Physical Function. This register determines the Physical Function for the MSI-X transaction." newline hexmask.long.byte 0x0 16.--23. 1. "MSIX_DOORBELL_VF,MSIX Doorbell Virtual Function. This register determines the Virtual Function for the MSI-X transaction." newline bitfld.long 0x0 15. "MSIX_DOORBELL_VF_ACTIVE,MSIX Doorbell Virtual Function Active. This register determines whether a Virtual Function is used to generate the MSI-X transaction." "0,1" newline bitfld.long 0x0 12.--14. "MSIX_DOORBELL_TC,MSIX Doorbell Traffic Class. This register determines which traffic class to generate the MSI-X transaction with." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 11. "MSIX_DOORBELL_RESERVED_11,Reserved." "0,1" newline hexmask.long.word 0x0 0.--10. 1. "MSIX_DOORBELL_VECTOR,MSI-X Doorbell Vector. This register determines which vector to generate the MSI-X transaction for." group.long (0x24C+0x700)++0x3 line.long 0x0 "MSIX_RAM_CTRL_OFF,MSI-X RAM power mode and debug control register. When you enable the MSI-X Table RAM feature (MSIX_TABLE_EN=1). the controller implements the logic and RAM required to generate MSI-X requests. For more details. see the Interrupts.." hexmask.long.byte 0x0 26.--31. 1. "MSIX_RAM_CTRL_RESERVED_26_31,Reserved. Note: This register field is sticky." newline bitfld.long 0x0 25. "MSIX_RAM_CTRL_DBG_PBA,MSIX PBA RAM Debug Mode. Use this bit to activate the debug mode and allow direct read/write access to the PBA. Use can also use the dbg_pba input to activate debug mode. Debug mode turns off the PF/VF/Offset-based addressing into.." "0,1" newline bitfld.long 0x0 24. "MSIX_RAM_CTRL_DBG_TABLE,MSIX Table RAM Debug Mode. Use this bit to activate the debug mode and allow direct read/write access to the Table. Use can also use the dbg_table input to activate debug mode. Debug mode turns off the PF/VF/Offset-based.." "0,1" newline hexmask.long.byte 0x0 17.--23. 1. "MSIX_RAM_CTRL_RESERVED_17_23,Reserved. Note: This register field is sticky." newline bitfld.long 0x0 16. "MSIX_RAM_CTRL_BYPASS,MSIX RAM Control Bypass. The bypass field when set disables the internal generation of low power signals for both RAMs. It is up to the application to ensure the RAMs are in the proper power state before trying to access them." "0,1" newline hexmask.long.byte 0x0 10.--15. 1. "MSIX_RAM_CTRL_RESERVED_10_15,Reserved. Note: This register field is sticky." newline bitfld.long 0x0 9. "MSIX_RAM_CTRL_PBA_SD,MSIX PBA RAM Shut Down. Set this bit to drive the cfg_msix_pba_sd output to signal your external logic to place the MSIX PBA RAM in Shut Down low-power mode. Note: This register field is sticky." "0,1" newline bitfld.long 0x0 8. "MSIX_RAM_CTRL_PBA_DS,MSIX PBA RAM Deep Sleep. Set this bit to drive the cfg_msix_pba_ds output to signal your external logic to place the MSIX PBA RAM in Deep Sleep low-power mode. Note: This register field is sticky." "0,1" newline hexmask.long.byte 0x0 2.--7. 1. "MSIX_RAM_CTRL_RESERVED_2_7,Reserved. Note: This register field is sticky." newline bitfld.long 0x0 1. "MSIX_RAM_CTRL_TABLE_SD,MSIX Table RAM Shut Down. Set this bit to drive the cfg_msix_table_sd output to signal your external logic to place the MSIX Table RAM in Shut Down low-power mode. Note: This register field is sticky." "0,1" newline bitfld.long 0x0 0. "MSIX_RAM_CTRL_TABLE_DS,MSIX Table RAM Deep Sleep. Set this bit to drive the cfg_msix_table_ds output to signal your external logic to place the MSIX Table RAM in Deep Sleep low-power mode. Note: This register field is sticky." "0,1" group.long (0x430+0x700)++0x3 line.long 0x0 "PL_LTR_LATENCY_OFF,LTR Latency Register. The function of this register field (and all other fields in this register) differs between an upstream port and a downstream port. For an upstream port. the register fields capture the corresponding fields in the.." bitfld.long 0x0 31. "NO_SNOOP_LATENCY_REQUIRE,No Snoop Latency Requirement. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" "0,1" newline rbitfld.long 0x0 29.--30. "RSVDP_29,Reserved for future use." "0,1,2,3" newline bitfld.long 0x0 26.--28. "NO_SNOOP_LATENCY_SCALE,No Snoop Latency Scale. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" "0,1,2,3,4,5,6,7" newline hexmask.long.word 0x0 16.--25. 1. "NO_SNOOP_LATENCY_VALUE,No Snoop Latency Value. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" newline bitfld.long 0x0 15. "SNOOP_LATENCY_REQUIRE,Snoop Latency Requirement. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" "0,1" newline rbitfld.long 0x0 13.--14. "RSVDP_13,Reserved for future use." "0,1,2,3" newline bitfld.long 0x0 10.--12. "SNOOP_LATENCY_SCALE,Snoop Latency Scale. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" "0,1,2,3,4,5,6,7" newline hexmask.long.word 0x0 0.--9. 1. "SNOOP_LATENCY_VALUE,Snoop Latency Value. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" group.long (0x440+0x700)++0xB line.long 0x0 "AUX_CLK_FREQ_OFF,Auxiliary Clock Frequency Control Register." hexmask.long.tbyte 0x0 10.--31. 1. "RSVDP_10,Reserved for future use." newline hexmask.long.word 0x0 0.--9. 1. "AUX_CLK_FREQ,The aux_clk frequency in MHz. This value is used to provide a 1 us reference for counting time during low-power states with aux_clk when the PHY has removed the pipe_clk. Frequencies lower than 1 MHz are possible but with a loss of accuracy.." line.long 0x4 "L1_SUBSTATES_OFF,L1 Substates Timing Register." hexmask.long.tbyte 0x4 9.--31. 1. "RSVDP_9,Reserved for future use." newline bitfld.long 0x4 8. "L1SUB_LOW_POWER_CLOCK_SWITCH_MODE,If this bit is set to 1'b1 the reference clock will be running regardless of the CLKREQ# setting. If this bit is set to 1'b0 the reference clock may be gated off when CLKREQ# is de-asserted. If the bit is set to 1'b1 the.." "0,1" newline bitfld.long 0x4 6.--7. "L1SUB_T_PCLKACK,Max delay (in 1us units) between a MAC request to remove the clock on mac_phy_pclkreq_n and a PHY response on phy_mac_pclkack_n. If the PHY does not respond within this time the request is aborted.The actual timeout value will be.." "0,1,2,3" newline hexmask.long.byte 0x4 2.--5. 1. "L1SUB_T_L1_2,Duration (in 1us units) of L1.2. The actual timeout value will be L1SUB_T_L1_2 + 1. Range is 0.15. Note: This register field is sticky." newline bitfld.long 0x4 0.--1. "L1SUB_T_POWER_OFF,Duration (in 1us units) of L1.2.Entry. The actual timeout value will be L1SUB_T_POWER_OFF + 1. Range is 0.3. Note: This register field is sticky." "0,1,2,3" line.long 0x8 "POWERDOWN_CTRL_STATUS_OFF,Powerdown Control and Status Register." hexmask.long.tbyte 0x8 12.--31. 1. "RSVDP_12,Reserved for future use." newline hexmask.long.byte 0x8 8.--11. 1. "POWERDOWN_PHY_POWERDOWN,This field represents the Powerdown value that has been acknowledged by the PHY. It is updated with the value of Powerdown driven by the controller when the PHY has returned the Phystatus acknowledgment for the Powerdown.." newline hexmask.long.byte 0x8 4.--7. 1. "POWERDOWN_MAC_POWERDOWN,This field represents the Powerdown value driven by the controller to the PHY." newline rbitfld.long 0x8 1.--3. "RSVDP_1,Reserved for future use." "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 0. "POWERDOWN_FORCE,This field is a one shot field. Writing a value of 1 to this field causes the controller to complete the P2 Powerdown handshake regardless of whether the PHY has returned Phystatus. This field could be used for debug purposes in event.." "0,1" group.long (0x470+0x700)++0x7 line.long 0x0 "PHY_VIEWPORT_CTLSTS_OFF,PHY Register Viewport Control and Status Register." rbitfld.long 0x0 31. "PHY_VIEWPORT_PENDING,PHY viewport pending. Indicates the access is pending. - 1 : Pending - 0 : Idle This bit is set to 1 when the read/write access has been initiated. This bit is cleared when the access is completed. If phy_reg_clk_g is never activated.." "Idle,Pending" newline rbitfld.long 0x0 30. "PHY_VIEWPORT_STATUS,PHY viewport status. Indicates the status of the latest access. - 1 : Timeout - 0 : No errors If the timeout is detected this bit is set to 1 and PHY_VIEWPORT_PENDING is cleared. This bit is cleared when the read/write access is.." "No errors,Timeout" newline hexmask.long.byte 0x0 23.--29. 1. "RSVDP_23,Reserved for future use." newline bitfld.long 0x0 22. "PHY_VIEWPORT_TIMEOUT_DISABLE,PHY viewport timeout disable. Disables the PHY register access timeout structure. When the timeout is disabled you must ensure that the PHY register accesses are always acknowledged by cr_para_ack. Otherwise.." "0,1" newline bitfld.long 0x0 21. "PHY_VIEWPORT_BCWR,Broadcast write access to all xN sub-blocks. If you need to broadcast the write accesses into all lanes both PHY_VIEWPORT_ADDR[15] and this bit should be 1. Note: This register field is sticky." "0,1" newline bitfld.long 0x0 20. "PHY_VIEWPORT_READ,PHY viewport read. If set a read access is initiated. The value is always 0 when this bit is read. Note: This register field is sticky." "0,1" newline hexmask.long.byte 0x0 16.--19. 1. "PHY_VIEWPORT_NUM,PHY viewport xN sub-block number. Selects one of xN sub-blocks. This register is not used when the write access is initiated with PHY_VIEWPORT_BCWR==1. Note: This register field is sticky." newline hexmask.long.word 0x0 0.--15. 1. "PHY_VIEWPORT_ADDR,PHY viewport address. Indicates the PHY's register address. Please refer to the PHY databook for the address map definition. Note: This register field is sticky." line.long 0x4 "PHY_VIEWPORT_DATA_OFF,PHY Register Viewport Data Register." hexmask.long.word 0x4 16.--31. 1. "RSVDP_16,Reserved for future use." newline hexmask.long.word 0x4 0.--15. 1. "PHY_VIEWPORT_DATA,PHY viewport data. A write access to this register initiates the PHY register write access. By a read access to this register this field returns the latest read data from the PHY register. Note: This register field is sticky." group.long (0x490+0x700)++0x3 line.long 0x0 "PIPE_RELATED_OFF,PIPE Related Register. This register controls the pipe's capabitity. control. and status parameters." hexmask.long.tbyte 0x0 9.--31. 1. "RSVDP_9,Reserved for future use." newline bitfld.long 0x0 8. "PIPE_GARBAGE_DATA_MODE,PIPE Garbage Data Mode. - 0: PIPE Spec compliant mode: The MAC discards any symbols received after the electrical idle ordered-set until RxValid is deasserted. - 1: Special PHY Support mode: The MAC discards any symbols received.." "PIPE Spec compliant mode: The MAC discards any..,Special PHY Support mode: The MAC discards any.." tree.end tree.end tree "PCIE1_VF45" base ad:0xF1080000 tree "PF0_TYPE1_HDR (PCI-Compatible Configuration Space Header Type1)" group.long 0x0++0x2F line.long 0x0 "TYPE1_DEV_ID_VEND_ID_REG,Device ID and Vendor ID Register." hexmask.long.word 0x0 16.--31. 1. "DEVICE_ID,Device ID. The Device ID register identifies the particular Function. This identifier is allocated by the vendor. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else.." newline hexmask.long.word 0x0 0.--15. 1. "VENDOR_ID,Vendor ID. The Vendor ID register identifies the manufacturer of the Function. Valid vendor identifiers are allocated by the PCI-SIG to ensure uniqueness. It is not permitted to populate this register with a value of FFFFh which is an invalid.." line.long 0x4 "TYPE1_STATUS_COMMAND_REG,Status and Command Register." bitfld.long 0x4 31. "DETECTED_PARITY_ERROR,Detected Parity Error. This bit is set by a Function whenever it receives a Poisoned TLP regardless of the state the Parity Error Response bit in the Command register. The bit is set when the Poisoned TLP is received by a.." "0,1" newline bitfld.long 0x4 30. "SIGNALED_SYS_ERROR,Signaled System Error. This bit is set when a Function sends an ERR_FATAL or ERR_NONFATAL Message and the SERR# Enable bit in the Command register is 1b." "0,1" newline bitfld.long 0x4 29. "RCVD_MASTER_ABORT,Received Master Abort. This bit is set when a Requester receives a Completion with Unsupported Request Completion status. The bit is set when the Unsupported Request is received by a Function's primary side." "0,1" newline bitfld.long 0x4 28. "RCVD_TARGET_ABORT,Received Target Abort. This bit is set when a Requester receives a Completion with Completer Abort Completion status. The bit is set when the Completer Abort is received by a Function's primary side." "0,1" newline bitfld.long 0x4 27. "SIGNALED_TARGET_ABORT,Signaled Target Abort. This bit is set when a Function completes a Posted or Non-Posted Request as a Completer Abort error. This applies to a Function when the Completer Abort was generated by its primary side." "0,1" newline rbitfld.long 0x4 25.--26. "DEV_SEL_TIMING,DEVSEL Timing. This field was originally described in the PCI Local Bus Specification. Its functionality does not apply to PCI Express. The controller hardwires it to 00b." "0,1,2,3" newline bitfld.long 0x4 24. "MASTER_DPE,Master Data Parity Error. This bit is set by a Function if the Parity Error Response bit in the Command register is 1b and either of the following two conditions occurs: - Port receives a Poisoned Completion going downstream - Port transmits a.." "0,1" newline rbitfld.long 0x4 23. "FAST_B2B_CAP,Fast Back-to-Back Transactions Capable. This bit was originally described in the PCI Local Bus Specification. Its functionality does not apply to PCI Express. The controller hardwires this bit to 0b." "0,1" newline rbitfld.long 0x4 22. "RSVDP_22,Reserved for future use." "0,1" newline rbitfld.long 0x4 21. "FAST_66MHZ_CAP,66 MHz Capable. This bit was originally described in the PCI Local Bus Specification. Its functionality does not apply to PCI Express. The controller hardwires this bit to 0b." "0,1" newline rbitfld.long 0x4 20. "CAP_LIST,Capabilities List. Indicates the presence of an Extended Capability list item. Since all PCI Express device Functions are required to implement the PCI Express Capability structure the controller hardwires this bit to 1b." "0,1" newline rbitfld.long 0x4 19. "INT_STATUS,Interrupt Status. When set indicates that an INTx emulation interrupt is pending internally in the Function. INTx emulation interrupts forwarded by Functions from the secondary side are not reflected in this bit. Setting the Interrupt Disable.." "0,1" newline rbitfld.long 0x4 17.--18. "RSVDP_17,Reserved for future use." "0,1,2,3" newline bitfld.long 0x4 16. "IMM_READINESS,Immediate Readiness. This optional bit when set indicates the Function is guaranteed to be ready to successfully complete valid configuration accesses at any time following any reset that the host is capable of issuing Configuration.." "0,1" newline hexmask.long.byte 0x4 11.--15. 1. "RESERV,Reserved." newline bitfld.long 0x4 10. "INT_EN,Interrupt Disable. Controls the ability of a Function to generate INTx emulation interrupts. When set Functions are prevented from asserting INTx interrupts. Note: - Any INTx emulation interrupts already asserted by the Function must be.." "0,1" newline rbitfld.long 0x4 9. "RSVDP_9,Reserved for future use." "0,1" newline bitfld.long 0x4 8. "SERREN,SERR# Enable. When set this bit enables reporting upstream of Non-fatal and Fatal errors detected by the Function. Note: The errors are reported if enabled either through this bit or through the PCI Express specific bits in the Device Control.." "0,1" newline rbitfld.long 0x4 7. "IDSEL,IDSEL Stepping/Wait Cycle Control. This bit was originally described in the PCI Local Bus Specification. Its functionality does not apply to PCI Express. The controller hardwires this bit to 0b." "0,1" newline bitfld.long 0x4 6. "PERREN,Parity Error Response. This bit controls the logging of poisoned TLPs in the Master Data Parity Error bit in the Status register. For more details see the 'Error Registers' section of the PCI Express Base Specification." "0,1" newline rbitfld.long 0x4 5. "VGAPS,VGA Palette Snoop. This bit was originally described in the PCI Local Bus Specification and the PCI-to-PCI Bridge Architecture Specification. Its functionality does not apply to PCI Express. The controller hardwires this bit to 0b." "0,1" newline rbitfld.long 0x4 4. "MWI_EN,Memory Write and Invalidate. This bit was originally described in the PCI Local Bus Specification and the PCI-to-PCI Bridge Architecture Specification. Its functionality does not apply to PCI Express. The controller hardwires this bit to 0b. For.." "0,1" newline rbitfld.long 0x4 3. "SCO,Special Cycle Enable. This bit was originally described in the PCI Local Bus Specification. Its functionality does not apply to PCI Express. The controller hardwires this bit to 0b." "0,1" newline bitfld.long 0x4 2. "BME,Bus Master Enable. This bit controls forwarding of Memory or I/O requests by a port in the Upstream direction. When this bit is 0b Memory and I/O Requests received at a Root Port must be handled as Unsupported Requests (UR) For Non-Posted Requests a.." "0,1" newline bitfld.long 0x4 1. "MSE,Memory Space Enable. This bit controls a Function's response to Memory Space accesses received on its primary side. - When set the Function is enabled to decode the address and further process Memory Space accesses. - When clear all received Memory.." "0,1" newline bitfld.long 0x4 0. "IO_EN,IO Space Enable. This bit controls a Function's response to I/O Space accesses received on its primary side. - When set the Function is enabled to decode the address and further process I/O Space accesses. - When clear all received I/O accesses.." "0,1" line.long 0x8 "TYPE1_CLASS_CODE_REV_ID_REG,Class Code and Revision ID Register." hexmask.long.byte 0x8 24.--31. 1. "BASE_CLASS_CODE,Base Class Code. A code that broadly classifies the type of operation the Function performs. Encodings for base class are provided in the PCI Code and ID Assignment Specification. All unspecified encodings are reserved. Note: The access.." newline hexmask.long.byte 0x8 16.--23. 1. "SUBCLASS_CODE,Sub-Class Code. Specifies a base class sub-class which identifies more specifically the operation of the Function. Encodings for sub-class are provided in the PCI Code and ID Assignment Specification. All unspecified encodings are.." newline hexmask.long.byte 0x8 8.--15. 1. "PROGRAM_INTERFACE,Programming Interface. This field identifies a specific register level programming interface (if any) so that device independent software can interact with the Function. Encodings for interface are provided in the PCI Code and ID.." newline hexmask.long.byte 0x8 0.--7. 1. "REVISION_ID,Revision ID. The value of this field specifies a Function specific revision identifier. The value is chosen by the vendor. Zero is an acceptable value. The Revision ID should be viewed as a vendor defined extension to the Device ID. Note: The.." line.long 0xC "TYPE1_BIST_HDR_TYPE_LAT_CACHE_LINE_SIZE_REG,BIST. Header Type. Latency Timer. and Cache Line Size Register." hexmask.long.byte 0xC 24.--31. 1. "BIST,BIST. This register is used for control and status of BIST. Functions that do not support BIST must hardwire the register to 00h. A Function whose BIST is invoked must not prevent normal operation of the PCI Express Link. Bit descriptions: - [31]:.." newline rbitfld.long 0xC 23. "MULTI_FUNC,Multi-Function Device. - When set indicates that the device may contain multiple Functions but not necessarily. Software is permitted to probe for Functions other than Function 0. - When clear software must not probe for Functions other.." "0,1" newline hexmask.long.byte 0xC 16.--22. 1. "HEADER_TYPE,Header Layout. This field identifies the layout of the second part of the predefined header. The controller uses 000 0001b encoding. The encoding 000 0010b is reserved. This encoding was originally described in the PC Card Standard Electrical.." newline hexmask.long.byte 0xC 8.--15. 1. "LATENCY_MASTER_TIMER,Latency Timer. This register is also referred to as Primary Latency Timer. The Latency Timer was originally described in the PCI Local Bus Specification and the PCI-to-PCI Bridge Architecture Specification. Its functionality does not.." newline hexmask.long.byte 0xC 0.--7. 1. "CACHE_LINE_SIZE,Cache Line Size. The Cache Line Size register is programmed by the system firmware or the operating system to system cache line size. However legacy conventional PCI software may not always be able to program this register correctly.." line.long 0x10 "BAR0_REG,BAR0 Register. System software must build a consistent address map before booting the machine to an operating system. This means it has to determine how much memory is in the system. and how much address space the Functions in the system.." hexmask.long 0x10 4.--31. 1. "BAR0_START,BAR0 Base Address. - Memory Space: Base Address. - IO Space: bits[31:2] are used to map the function into IO space/Base. Address. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R(Sticky)/W(Sticky) if.." newline bitfld.long 0x10 3. "BAR0_PREFETCH,BAR0 Prefetchable. - Memory Space: Set to one if data is pre-fetchable. A Function is permitted to mark a range as prefetchable. If there are no side effects on reads the function returns all bytes on reads regardless of the byte enables.." "0,1" newline bitfld.long 0x10 1.--2. "BAR0_TYPE,BAR0 Type. - Memory Space: Base Address registers that map into Memory Space can be 32 bits or 64 bits wide (to support mapping into a 64-bit address space). The bit encoding is as follows: -- 00: Base register is 32 bits wide and can be mapped.." "Base register is 32 bits wide and can be mapped..,Reserved,?,?" newline bitfld.long 0x10 0. "BAR0_MEM_IO,BAR0 Memory Space Indicator. This bit is used to determine whether the register maps into Memory or I/O Space. Base Address registers that map to Memory Space must return a 0b. Base Address registers that map to I/O Space must return a 1b." "0,1" line.long 0x14 "BAR1_REG,BAR1 Register. System software must build a consistent address map before booting the machine to an operating system. This means it has to determine how much memory is in the system. and how much address space the Functions in the system.." hexmask.long 0x14 4.--31. 1. "BAR1_START,BAR1 Base Address. - Memory Space: Base Address. - IO Space: bits[31:2] are used to map the function into IO space/Base. Address. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R(Sticky)/W(Sticky) if.." newline bitfld.long 0x14 3. "BAR1_PREFETCH,BAR1 Prefetchable. - Memory Space: Set to one if data is pre-fetchable. A Function is permitted to mark a range as prefetchable. If there are no side effects on reads the function returns all bytes on reads regardless of the byte enables.." "0,1" newline bitfld.long 0x14 1.--2. "BAR1_TYPE,BAR1 Type. - Memory Space: Base Address registers that map into Memory Space can be 32 bits or 64 bits wide (to support mapping into a 64-bit address space). The bit encoding is as follows: -- 00: Base register is 32 bits wide and can be mapped.." "Base register is 32 bits wide and can be mapped..,Reserved,?,?" newline bitfld.long 0x14 0. "BAR1_MEM_IO,BAR1 Memory Space Indicator. This bit is used to determine whether the register maps into Memory or I/O Space. Base Address registers that map to Memory Space must return a 0b. Base Address registers that map to I/O Space must return a 1b." "0,1" line.long 0x18 "SEC_LAT_TIMER_SUB_BUS_SEC_BUS_PRI_BUS_REG,Secondary Latency Timer. Subordinate Bus Number. Secondary Bus Number. and Primary Bus Number Register." hexmask.long.byte 0x18 24.--31. 1. "SEC_LAT_TIMER,Secondary Latency Timer. This register does not apply to PCI Express. The controller hardwires it to 00h." newline hexmask.long.byte 0x18 16.--23. 1. "SUB_BUS,Subordinate Bus Number. The Subordinate Bus Number register is used to record the bus number of the highest numbered PCI bus segment which is behind (or subordinate to) the bridge. Configuration software programs the value in this register. The.." newline hexmask.long.byte 0x18 8.--15. 1. "SEC_BUS,Secondary Bus Number. The Secondary Bus Number register is used to record the bus number of the PCI bus segment to which the secondary interface of the bridge is connected. Configuration software programs the value in this register. The bridge.." newline hexmask.long.byte 0x18 0.--7. 1. "PRIM_BUS,Primary Bus Number. This register is not used by PCI Express Functions. It is implemented for compatibility with legacy software." line.long 0x1C "SEC_STAT_IO_LIMIT_IO_BASE_REG,Secondary Status. and I/O Limit and Base Register. The I/O Limit and I/O Base registers are optional and define an address range that is used by the bridge to determine when to forward I/O transactions from one interface to.." bitfld.long 0x1C 31. "SEC_STAT_DPE,Detected Parity Error. This bit is set by a Function when a Poisoned TLP is received by its secondary side regardless of the state the Parity Error Response Enable bit in the Bridge Control register." "0,1" newline bitfld.long 0x1C 30. "SEC_STAT_RCVD_SYS_ERR,Received System Error. This bit is set when the secondary side of a Function receives an ERR_FATAL or ERR_NONFATAL message." "0,1" newline bitfld.long 0x1C 29. "SEC_STAT_RCVD_MSTR_ABRT,Received Master Abort. This bit is set when the secondary side of a Function (for requests initiated by the Type 1 header Function itself) receives a Completion with Unsupported Request Completion status." "0,1" newline bitfld.long 0x1C 28. "SEC_STAT_RCVD_TRGT_ABRT,Received Target Abort. This bit is set when the secondary side of a Function (for requests initiated by the Type 1 header Function itself) receives a Completion with Completer Abort Completion status." "0,1" newline bitfld.long 0x1C 27. "SEC_STAT_SIG_TRGT_ABRT,Signaled Target Abort. This bit is set when the secondary side of the Function (for Requests completed by the Type 1 header Function itself) completes a Posted or Non-Posted request as a Completer Abort error." "0,1" newline rbitfld.long 0x1C 25.--26. "RSVDP_25,Reserved for future use." "0,1,2,3" newline bitfld.long 0x1C 24. "SEC_STAT_MDPE,Master Data Parity Error. This bit is set by a Function if the Parity Error Response Enable bit in the Bridge Control register is set and either of the following two conditions occurs: - Port receives a Poisoned Completion coming Upstream.." "0,1" newline rbitfld.long 0x1C 23. "RSVDP_23,Reserved for future use." "0,1" newline hexmask.long.byte 0x1C 16.--22. 1. "SEC_STAT_RESERV,Reserved." newline hexmask.long.byte 0x1C 12.--15. 1. "IO_LIMIT,I/O Limit Address. These bits correspond to the address[15:12] of IO address range. For the purpose of address decoding the bridge assumes that the lower 12 address bits address[11:0] of the I/O limit address (not implemented in the I/O Limit.." newline rbitfld.long 0x1C 9.--11. "IO_RESERV1,Reserved." "0,1,2,3,4,5,6,7" newline bitfld.long 0x1C 8. "IO_DECODE_BIT8,I/O Addressing Encode (IO Limit Address). This bit encodes the IO addressing capability of the bridge. IO_DECODE_BIT8 indicates the following: - 0h: The bridge supports only 16-bit I/O addressing (for ISA compatibility). For the purpose of.." "0,1" newline hexmask.long.byte 0x1C 4.--7. 1. "IO_BASE,I/O Base Address. These bits correspond to the address[15:12] of IO address range. For the purpose of address decoding the bridge assumes that the lower 12 address bits address[11:0] of the I/O base address (not implemented in the I/O Base.." newline rbitfld.long 0x1C 1.--3. "IO_RESERV,Reserved." "0,1,2,3,4,5,6,7" newline bitfld.long 0x1C 0. "IO_DECODE,I/O Addressing Encode (IO Base Address) This bit encodes the IO addressing capability of the bridge. IO_DECODE indicates the following: - 0h: The bridge supports only 16-bit I/O addressing (for ISA compatibility). For the purpose of address.." "0,1" line.long 0x20 "MEM_LIMIT_MEM_BASE_REG,Memory Limit and Base Register. The Memory Limit and Memory Base registers define a memory mapped address range which is used by the bridge to determine when to forward memory transactions from one interface to the other. If there.." hexmask.long.word 0x20 20.--31. 1. "MEM_LIMIT,Memory Limit Address. These bits correspond to the upper 12 address bits Address[31:20] of 32-bit addresses. For the purpose of address decoding the bridge assumes that the lower 20 address bits Address[19:0] of the memory limit address.." newline hexmask.long.byte 0x20 16.--19. 1. "MEM_LIMIT_RESERV,Reserved." newline hexmask.long.word 0x20 4.--15. 1. "MEM_BASE,Memory Base Address. These bits correspond to the upper 12 address bits Address[31:20] of 32-bit addresses. For the purpose of address decoding the bridge assumes that the lower 20 address bits Address[19:0] of the memory base address (not.." newline hexmask.long.byte 0x20 0.--3. 1. "MEM_BASE_RESERV,Reserved." line.long 0x24 "PREF_MEM_LIMIT_PREF_MEM_BASE_REG,Prefetchable Memory Limit and Base Register. The Prefetchable Memory Limit and Prefetchable Memory Base registers must indicate that 64-bit addresses are supported. as defined in PCI-to-PCI Bridge Architecture.." hexmask.long.word 0x24 20.--31. 1. "PREF_MEM_LIMIT,Prefetchable Memory Limit Address. If the Prefetchable Memory Limit register indicates support for 32-bit addressing then the Prefetchable Limit Upper 32 Bits register is implemented as a read-only register that returns zero when read. If.." newline rbitfld.long 0x24 17.--19. "PREF_RESERV1,Reserved." "0,1,2,3,4,5,6,7" newline rbitfld.long 0x24 16. "PREF_MEM_LIMIT_DECODE,Prefetchable Memory Limit Decode. This bit encodes whether or not the bridge supports 64-bit addresses. Note: This bit is a copy of the PREF_MEM_DECODE bit and always reflects the current value of that bit. The value of.." "0,1" newline hexmask.long.word 0x24 4.--15. 1. "PREF_MEM_BASE,Prefetchable Memory Base Address. If the Prefetchable Memory Base register indicates support for 32-bit addressing then the Prefetchable Base Upper 32 Bits register is implemented as a read-only register that returns zero when read. If the.." newline rbitfld.long 0x24 1.--3. "PREF_RESERV,Reserved." "0,1,2,3,4,5,6,7" newline bitfld.long 0x24 0. "PREF_MEM_DECODE,Prefetchable Memory Base Decode. This bit encodes whether or not the bridge supports 64-bit addresses. Note: By default the bit is set to 1'b1 indicating that 64-bit addresses are supported. If the bridge only supports 32-bit prefetchable.." "0,1" line.long 0x28 "PREF_BASE_UPPER_REG,Prefetchable Base Upper 32 Bits Register. The Prefetchable Base Upper 32 Bits register is an optional extension to the Prefetchable Memory Base register." hexmask.long 0x28 0.--31. 1. "PREF_MEM_BASE_UPPER,Prefetchable Base Upper 32 Bit. If the Prefetchable Memory Base register indicates support for 32-bit addressing then this register is implemented as read-only register that returns zero when read. If the Prefetchable Memory Base.." line.long 0x2C "PREF_LIMIT_UPPER_REG,Prefetchable Limit Upper 32 Bits Register. The Prefetchable Limit Upper 32 Bits register is an optional extension to the Prefetchable Memory Limit register." hexmask.long 0x2C 0.--31. 1. "PREF_MEM_LIMIT_UPPER,Prefetchable Limit Upper 32 Bit. If the Prefetchable Memory Limit register indicate support for 64-bit addressing then this register is implemented as read/write register which must be initialized by configuration software. This.." rgroup.long 0x30++0x3 line.long 0x0 "IO_LIMIT_UPPER_IO_BASE_UPPER_REG,I/O Limit and Base Upper 16 Bits Register. The I/O Limit Upper 16 Bits and I/O Base Upper 16 Bits registers are optional extensions to the I/O Limit and I/O Base registers." hexmask.long.word 0x0 16.--31. 1. "IO_LIMIT_UPPER,I/O Limit Upper 16 Bits. If the I/O Limit register indicates support for 16-bit I/O address decoding then this register is implemented as a read-only register which return zero when read. If the I/O Limit register indicates support for.." newline hexmask.long.word 0x0 0.--15. 1. "IO_BASE_UPPER,I/O Base Upper 16 Bits. If the I/O Base register indicates support for 16-bit I/O address decoding then this register is implemented as a read-only register which return zero when read. If the I/O base register indicates support for 32-bit.." group.long 0x34++0xB line.long 0x0 "TYPE1_CAP_PTR_REG,Capabilities Pointer Register." hexmask.long.tbyte 0x0 8.--31. 1. "RSVDP_8,Reserved for future use." newline hexmask.long.byte 0x0 0.--7. 1. "CAP_POINTER,Capabilities Pointer. This register is used to point to a linked list of capabilities implemented by this Function. Since all PCI Express Functions are required to implement the PCI Express Capability structure this register must point to a.." line.long 0x4 "TYPE1_EXP_ROM_BASE_REG,Expansion ROM Base Address Register. This register is defined to handle the base address and size information for this expansion ROM. The mask for this ROM BAR exists (if implemented) as a shadow register at this address. The.." hexmask.long.tbyte 0x4 11.--31. 1. "EXP_ROM_BASE_ADDRESS,Expansion ROM Base Address. Upper 21 bits of the Expansion ROM base address. The number of bits (out of these 21) that a Function actually implements depends on how much address space the Function requires. The mask for this ROM BAR.." newline hexmask.long.word 0x4 1.--10. 1. "RSVDP_1,Reserved for future use." newline bitfld.long 0x4 0. "ROM_BAR_ENABLE,Expansion ROM Enable. This bit controls whether or not the Function accepts accesses to its expansion ROM. When this bit is 0b the Function's expansion ROM address space is disabled. When the bit is 1b address decoding is enabled using.." "0,1" line.long 0x8 "BRIDGE_CTRL_INT_PIN_INT_LINE_REG,Bridge Control. Interrupt Pin. and Interrupt Line Register." hexmask.long.word 0x8 23.--31. 1. "BRIDGE_CTRL_RESERV,Reserved." newline bitfld.long 0x8 22. "SBR,Secondary Bus Reset. Setting this bit triggers a hot reset on the corresponding PCI Express Port. Software must ensure a minimum reset duration (Trst) as defined in the PCI Local Bus Specification. Software and systems must honor.." "0,1" newline rbitfld.long 0x8 21. "MSTR_ABORT_MODE,Master Abort Mode. This bit was originally described in the PCI-to-PCI Bridge Architecture Specification. Its functionality does not apply to PCI Express. The controller hardwires this bit to 0b. Note: The access attributes of this field.." "0,1" newline rbitfld.long 0x8 20. "VGA_16B_DEC,VGA 16 bit decode. This bit only has meaning if VGA Enable bit is set. This bit enables system configuration software to select between 10-bit and 16-bit I/O address decoding for all VGA I/O register accesses that are forwarded from primary.." "0,1" newline rbitfld.long 0x8 19. "VGA_EN,VGA Enable. Modifies the response by the bridge to VGA compatible addresses. If the VGA Enable bit is set the bridge will positively decode and forward the following accesses on the primary interface to the secondary interface (and conversely.." "0,1" newline bitfld.long 0x8 18. "ISA_EN,ISA Enable. Modifies the response by the bridge to ISA I/O addresses. This applies only to I/O addresses that are enabled by the I/O Base and I/O Limit registers and are in the first 64 KB of I/O address space (0000 0000h to 0000 FFFFh). If this.." "?,KB block" newline bitfld.long 0x8 17. "SERR_EN,SERR# Enable. This bit controls forwarding of ERR_COR ERR_NONFATAL and ERR_FATAL from secondary to primary." "0,1" newline bitfld.long 0x8 16. "PERE,Parity Error Response Enable. This bit controls the logging of poisoned TLPs in the Master Data Parity Error bit in the Secondary Status register." "0,1" newline hexmask.long.byte 0x8 8.--15. 1. "INT_PIN,Interrupt PIN. The Interrupt Pin register register that identifies the legacy interrupt Message(s) the Function uses. Valid values are: - 01h 02h 03h and 04h: map to legacy interrupt Messages for INTA INTB INTC and INTD respectively. - 00h:.." newline hexmask.long.byte 0x8 0.--7. 1. "INT_LINE,Interrupt Line. The Interrupt Line register communicates interrupt line routing information. The register must be implemented by any Function that uses an interrupt pin. Values in this register are programmed by system software and are system.." tree.end tree "PF0_SPCIE_CAP (Secondary PCI Express Capability Structure)" group.long (0x0+0x1A0)++0xF line.long 0x0 "SPCIE_CAP_HEADER_REG,SPCIE Capability Header. For a description of this standard PCIe register. see the PCI Express Specification." hexmask.long.word 0x0 20.--31. 1. "NEXT_OFFSET,Next Capability Offset. For a description of this standard PCIe register field see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky).." hexmask.long.byte 0x0 16.--19. 1. "CAP_VERSION,Capability Version. For a description of this standard PCIe register field see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else.." hexmask.long.word 0x0 0.--15. 1. "EXTENDED_CAP_ID,Secondary PCI Express Extended Capability ID. For a description of this standard PCIe register field see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN.." line.long 0x4 "LINK_CONTROL3_REG,Link Control 3 Register. For a description of this standard PCIe register. see the PCI Express Specification." hexmask.long 0x4 2.--31. 1. "RSVDP_2,Reserved for future use." bitfld.long 0x4 1. "EQ_REQ_INT_EN,Link Equalization Request Interrupt Enable. For a description of this standard PCIe register field see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" "0,1" bitfld.long 0x4 0. "PERFORM_EQ,Perform Equalization. For a description of this standard PCIe register field see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" "0,1" line.long 0x8 "LANE_ERR_STATUS_REG,Lane Error Status Register. For a description of this standard PCIe register. see the PCI Express Specification." hexmask.long 0x8 2.--31. 1. "RSVDP_LANE_ERR_STATUS,Reserved for future use." bitfld.long 0x8 0.--1. "LANE_ERR_STATUS,Lane Error Status Bits per Lane. For a description of this standard PCIe register field see the PCI Express Specification." "0,1,2,3" line.long 0xC "SPCIE_CAP_OFF_0CH_REG,Lane Equalization Control Register for lanes 1 and 0. For a description of this standard PCIe register. see the PCI Express Specification." rbitfld.long 0xC 31. "RSVDP_31,Reserved for future use." "0,1" bitfld.long 0xC 28.--30. "USP_RX_PRESET_HINT1,Upstream Port 8.0 GT/s Receiver Preset Hint 1. The write value is gated with the PCIE_CAP_CROSS_LINK_SUPPORT field of LINK_CAPABILITIES2_REG. For a description of this standard PCIe register field see the PCI Express Specification." "0,1,2,3,4,5,6,7" hexmask.long.byte 0xC 24.--27. 1. "USP_TX_PRESET1,Upstream Port 8.0 GT/s Transmitter Preset 1. The write value is gated with the PCIE_CAP_CROSS_LINK_SUPPORT field of LINK_CAPABILITIES2_REG. For a description of this standard PCIe register field see the PCI Express Specification. Note:.." rbitfld.long 0xC 23. "RSVDP_23,Reserved for future use." "0,1" newline bitfld.long 0xC 20.--22. "DSP_RX_PRESET_HINT1,Downstream Port 8.0 GT/s Receiver Preset Hint 1. For a description of this standard PCIe register field see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if.." "0,1,2,3,4,5,6,7" hexmask.long.byte 0xC 16.--19. 1. "DSP_TX_PRESET1,Downstream Port 8.0 GT/s Transmitter Preset 1. For a description of this standard PCIe register field see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN.." rbitfld.long 0xC 15. "RSVDP_15,Reserved for future use." "0,1" bitfld.long 0xC 12.--14. "USP_RX_PRESET_HINT0,Upstream Port 8.0 GT/s Receiver Preset Hint 0. The write value is gated with the PCIE_CAP_CROSS_LINK_SUPPORT field of LINK_CAPABILITIES2_REG. For a description of this standard PCIe register field see the PCI Express Specification." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0xC 8.--11. 1. "USP_TX_PRESET0,Upstream Port 8.0 GT/s Transmitter Preset 0. The write value is gated with the PCIE_CAP_CROSS_LINK_SUPPORT field of LINK_CAPABILITIES2_REG. For a description of this standard PCIe register field see the PCI Express Specification. Note:.." rbitfld.long 0xC 7. "RSVDP_7,Reserved for future use." "0,1" bitfld.long 0xC 4.--6. "DSP_RX_PRESET_HINT0,Downstream Port 8.0 GT/s Receiver Preset Hint 0. For a description of this standard PCIe register field see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if.." "0,1,2,3,4,5,6,7" hexmask.long.byte 0xC 0.--3. 1. "DSP_TX_PRESET0,Downstream Port 8.0 GT/s Transmitter Preset 0. For a description of this standard PCIe register field see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN.." tree.end tree "PF0_L1SUB_CAP (L1 Substates Capability Structure)" group.long (0x0+0x2E8)++0xF line.long 0x0 "L1SUB_CAP_HEADER_REG,L1 Substates Extended Capability Header. This register provides capbility ID. capability version and next offset value for L1 Substates." hexmask.long.word 0x0 20.--31. 1. "NEXT_OFFSET,Next Capability Offset. This field contains the offset to the next PCI Express Capability structure or 000h if no other items exist in the linked list of Capabilities. For Extended Capabilities implemented in Configuration Space this offset.." hexmask.long.byte 0x0 16.--19. 1. "CAP_VERSION,Capability Version. This field is a PCI-SIG defined version number that indicates the version of the Capability structure present. This field is depends on version of the specification. Note: The access attributes of this field are as.." hexmask.long.word 0x0 0.--15. 1. "EXTENDED_CAP_ID,L1SUB Extended Capability ID. This field is a PCI-SIG defined ID number that indicates the nature and format of the Extended Capability. Extended Capability ID for L1 PM Substates is 001Eh. Note: The access attributes of this field are as.." line.long 0x4 "L1SUB_CAPABILITY_REG,L1 Substates Capability Register. This register provides extended capability of L1 Substates." hexmask.long.byte 0x4 24.--31. 1. "RSVDP_24,Reserved for future use." hexmask.long.byte 0x4 19.--23. 1. "PWR_ON_VALUE_SUPPORT,Port T Power On Value. Along with the Port T_POWER_ON Scale field in the L1 PM Substates Capabilities register sets the time (in us) that this Port requires the port on the opposite side of Link to wait in L1.2.Exit after sampling.." rbitfld.long 0x4 18. "RSVDP_18,Reserved for future use." "0,1" bitfld.long 0x4 16.--17. "PWR_ON_SCALE_SUPPORT,Port T Power On Scale. Specifies the scale used for the Port T_POWER_ON Value field in the L1 PM Substates Capabilities register. Range of values are given below. Required for all Ports for which either the PCI-PM L1.2 Supported bit.." "?,?,?,Reserved" newline hexmask.long.byte 0x4 8.--15. 1. "COMM_MODE_SUPPORT,Port Common Mode Restore Time. Time (in us) required for this Port to re-establish common mode. Required for all Ports for which either the PCI-PM L1.2 Supported bit is Set ASPM L1.2 Supported bit is Set or both are Set otherwise.." rbitfld.long 0x4 5.--7. "RSVDP_5,Reserved for future use." "0,1,2,3,4,5,6,7" bitfld.long 0x4 4. "L1_PMSUB_SUPPORT,L1 PM Substates ECN Supported. When Set this bit indicates that this Port supports L1 PM Substates. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W (sticky)" "0,1" bitfld.long 0x4 3. "L1_1_ASPM_SUPPORT,ASPM L11 Supported. When Set this bit indicates that ASPM L1.1 is supported. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W (sticky)" "0,1" newline bitfld.long 0x4 2. "L1_2_ASPM_SUPPORT,ASPM L12 Supported. When Set this bit indicates that ASPM L1.2 is supported. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W (sticky)" "0,1" bitfld.long 0x4 1. "L1_1_PCIPM_SUPPORT,PCI-PM L11 Supported. When Set this bit indicates that PCI-PM L1.1 is supported and must be Set by all Ports implementing L1 PM Substates. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W (sticky)" "0,1" bitfld.long 0x4 0. "L1_2_PCIPM_SUPPORT,PCI-PM L12 Supported. When Set this bit indicates that PCI-PM L1.2 is supported. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W (sticky)" "0,1" line.long 0x8 "L1SUB_CONTROL1_REG,L1 Substates Control 1 Register. This register provides Controls to extended capability." bitfld.long 0x8 29.--31. "L1_2_TH_SCA,LTR L12 Threshold Scale. This field provides a scale for the value contained within the LTR_L1.2_THRESHOLD_Value.The default value for this field is 000b.Hardware operation is undefined if software writes a Not-Permitted value to this field." "0,1,2,3,4,5,6,7" rbitfld.long 0x8 26.--28. "RSVDP_26,Reserved for future use." "0,1,2,3,4,5,6,7" hexmask.long.word 0x8 16.--25. 1. "L1_2_TH_VAL,LTR L12 Threshold Value. Along with the LTR_L1.2_THRESHOLD_Scale this field indicates the LTR threshold used to determine if entry into L1 results in L1.1 (if enabled) or L1.2 (if enabled). The default value for this field is 00 0000 0000b." hexmask.long.byte 0x8 8.--15. 1. "T_COMMON_MODE,Common Mode Restore Time. Sets value of TCOMMONMODE (in us) which must be used by the Downstream Ports for timing the re-establishment of common mode.This field is of type RsvdP for Upstream Ports. Default value is implementation.." newline hexmask.long.byte 0x8 4.--7. 1. "RSVDP_4,Reserved for future use." bitfld.long 0x8 3. "L1_1_ASPM_EN,ASPM L11 Enable. When Set this bit enables ASPM L1.1.For Ports for which the ASPM L1.1 Supported bit is Clear this bit is permitted to be hardwired to 0.Default value is 0b." "0,1" bitfld.long 0x8 2. "L1_2_ASPM_EN,ASPM L12 Enable. When Set this bit enables ASPM L1.2.For Ports for which the ASPM L1.2 Supported bit is Clear this bit is permitted to be hardwired to 0.Default value is 0b." "0,1" bitfld.long 0x8 1. "L1_1_PCIPM_EN,PCI-PM L11 Enable. When Set this bit enables PCI-PM L1.1. Default value is 0b." "0,1" newline bitfld.long 0x8 0. "L1_2_PCIPM_EN,PCI-PM L12 Enable. When Set this bit enables PCI-PM L1.2.For Ports for which the PCI-PM L1.2 Supported bit is Clear this bit is permitted to be hardwired to 0.Default value is 0b." "0,1" line.long 0xC "L1SUB_CONTROL2_REG,L1 Substates Control 2 Register. This register provides Controls to extended capability." hexmask.long.tbyte 0xC 8.--31. 1. "RSVDP_8,Reserved for future use." hexmask.long.byte 0xC 3.--7. 1. "T_POWER_ON_VALUE,T Power On Value. Along with the T_POWER_ON Scale sets the minimum amount of time (in us) that the Port must wait in L1.2.Exit after sampling CLKREQ# asserted before actively driving the interface.Default value is 00101b. T_POWER_ON is.." rbitfld.long 0xC 2. "RSVDP_2,Reserved for future use." "0,1" bitfld.long 0xC 0.--1. "T_POWER_ON_SCALE,T Power On Scale. Specifies the scale used for T_POWER_ON Value. Range of values are given below. Required for all Ports that support L1.2 otherwise this field is of type RsvdP. This field must only be modified when the ASPM L1.2 Enable.." "?,?,?,Reserved" tree.end tree "PF0_RAS_DES_CAP (RAS D.E.S. Capability Structure (VSEC))" group.long (0x0+0x30C)++0x3 line.long 0x0 "RAS_DES_CAP_HEADER_REG,Vendor-Specific Extended Capability Header. For a description of this standard PCIe register. see the PCI Express Specification." hexmask.long.word 0x0 20.--31. 1. "NEXT_OFFSET,Next Capability Offset. For a description of this standard PCIe register field see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky).." newline hexmask.long.byte 0x0 16.--19. 1. "CAP_VERSION,Capability Version. For a description of this standard PCIe register field see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else.." newline hexmask.long.word 0x0 0.--15. 1. "EXTENDED_CAP_ID,PCI Express Extended Capability ID. For a description of this standard PCIe register field see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then.." rgroup.long (0x4+0x30C)++0x3 line.long 0x0 "VENDOR_SPECIFIC_HEADER_REG,Vendor-Specific Header. For a description of this standard PCIe register. see the PCI Express Specification." hexmask.long.word 0x0 20.--31. 1. "VSEC_LENGTH,VSEC Length. For a description of this standard PCIe register field see the PCI Express Specification." newline hexmask.long.byte 0x0 16.--19. 1. "VSEC_REV,VSEC Rev. For a description of this standard PCIe register field see the PCI Express Specification." newline hexmask.long.word 0x0 0.--15. 1. "VSEC_ID,VSEC ID. For a description of this standard PCIe register field see the PCI Express Specification." group.long (0x8+0x30C)++0x3 line.long 0x0 "EVENT_COUNTER_CONTROL_REG,Event Counter Control. This is a viewport control register. - Setting the EVENT_COUNTER_EVENT_SELECT and EVENT_COUNTER_LANE_SELECT fields in this register determine the Event Counter data returned by the EVENT_COUNTER_DATA_REG.." hexmask.long.byte 0x0 28.--31. 1. "RSVDP_28,Reserved for future use." newline hexmask.long.word 0x0 16.--27. 1. "EVENT_COUNTER_EVENT_SELECT,Event Counter Data Select. This field in conjunction with the EVENT_COUNTER_LANE_SELECT field indexes the Event Counter data returned by the EVENT_COUNTER_DATA_REG register. - 27-24: Group number(4-bit: 0..0x7) - 23-16: Event.." newline hexmask.long.byte 0x0 12.--15. 1. "RSVDP_12,Reserved for future use." newline hexmask.long.byte 0x0 8.--11. 1. "EVENT_COUNTER_LANE_SELECT,Event Counter Lane Select. This field in conjunction with EVENT_COUNTER_EVENT_SELECT indexes the Event Counter data returned by the EVENT_COUNTER_DATA_REG register. - 0x0: Lane0 - 0x1: Lane1 - 0x2: Lane2 - .. - 0xF: Lane15 Note:.." newline rbitfld.long 0x0 7. "EVENT_COUNTER_STATUS,Event Counter Status. This register returns the current value of the Event Counter selected by the following fields: - EVENT_COUNTER_EVENT_SELECT - EVENT_COUNTER_LANE_SELECT Note: This register field is sticky." "0,1" newline rbitfld.long 0x0 5.--6. "RSVDP_5,Reserved for future use." "0,1,2,3" newline bitfld.long 0x0 2.--4. "EVENT_COUNTER_ENABLE,Event Counter Enable. Enables/disables the Event Counter selected by the EVENT_COUNTER_EVENT_SELECT and EVENT_COUNTER_LANE_SELECT fields in this register. By default all event counters are disabled. You can enable/disable a specific.." "no change,per event off,?,?,?,?,?,?" newline bitfld.long 0x0 0.--1. "EVENT_COUNTER_CLEAR,Event Counter Clear. Clears the Event Counter selected by the EVENT_COUNTER_EVENT_SELECT and EVENT_COUNTER_LANE_SELECT fields in this register. You can clear the value of a specific Event Counter by writing the 'per clear' code and.." "no change,per clear,?,?" rgroup.long (0xC+0x30C)++0x3 line.long 0x0 "EVENT_COUNTER_DATA_REG,Event Counter Data. This viewport register returns the data selected by the following fields: - EVENT_COUNTER_EVENT_SELECT in EVENT_COUNTER_CONTROL_REG - EVENT_COUNTER_LANE_SELECT in EVENT_COUNTER_CONTROL_REG For more details. see.." hexmask.long 0x0 0.--31. 1. "EVENT_COUNTER_DATA,Event Counter Data. This register returns the data selected by the following fields: - EVENT_COUNTER_EVENT_SELECT in EVENT_COUNTER_CONTROL_REG - EVENT_COUNTER_LANE_SELECT in EVENT_COUNTER_CONTROL_REG Note: This register field is sticky." group.long (0x10+0x30C)++0x3 line.long 0x0 "TIME_BASED_ANALYSIS_CONTROL_REG,Time-based Analysis Control. Used for controlling the measurement of RX/TX data throughput and time spent in each low-power LTSSM state. For more details. see the RAS DES section in the Core Operations chapter of the.." hexmask.long.byte 0x0 24.--31. 1. "TIME_BASED_REPORT_SELECT,Time-based Report Select. Selects what type of data is measured for the selected duration (TIME_BASED_DURATION_SELECT) and returned in TIME_BASED_ANALYSIS_DATA. Each type of data is measured using one of three types of units: -.." newline hexmask.long.byte 0x0 16.--23. 1. "RSVDP_16,Reserved for future use." newline hexmask.long.byte 0x0 8.--15. 1. "TIME_BASED_DURATION_SELECT,Time-based Duration Select. Selects the duration of time-based analysis. When 'manual control' is selected and TIMER_START is set to '1' this analysis never stops until TIMER_STOP is set to '0'. - 0x0: Manual control - 0x1:.." newline hexmask.long.byte 0x0 1.--7. 1. "RSVDP_1,Reserved for future use." newline bitfld.long 0x0 0. "TIMER_START,Timer Start. - 1: Start/Restart - 0: Stop This bit will be cleared automatically when the measurement is finished. Note: The app_ras_des_tba_ctrl input also sets the contents of this field and controls the measurement start/stop. Note: This.." "Stop,Start/Restart" rgroup.long (0x14+0x30C)++0x7 line.long 0x0 "TIME_BASED_ANALYSIS_DATA_REG,Time-based Analysis Data. Contains the measurement results of RX/TX data throughput and time spent in each low-power LTSSM state. This viewport register returns the data selected by the TIME_BASED_REPORT_SELECT field in.." hexmask.long 0x0 0.--31. 1. "TIME_BASED_ANALYSIS_DATA,Time Based Analysis Data. This register returns the data selected by the TIME_BASED_REPORT_SELECT field in TIME_BASED_ANALYSIS_CONTROL_REG. The results are cleared when next measurement starts. Note: This register field is sticky." line.long 0x4 "TIME_BASED_ANALYSIS_DATA_63_32_REG,Upper 32 bits of Time-based Analysis Data. This viewport register returns the data selected by the TIME_BASED_REPORT_SELECT field in TIME_BASED_ANALYSIS_CONTROL_REG. For more details. see the RAS DES section in the Core.." hexmask.long 0x4 0.--31. 1. "TIME_BASED_ANALYSIS_DATA_63_32,Upper 32 bits of Time Based Analysis Data. Note: This register field is sticky." group.long (0x30+0x30C)++0x5F line.long 0x0 "EINJ_ENABLE_REG,Error Injection Enable. Each type of error insertion is enabled by the corresponding bit in this register. The specific injection controls for each type of error are defined in the following registers: - 0: CRC Error: EINJ0_CRC_REG - 1:.." hexmask.long 0x0 7.--31. 1. "RSVDP_7,Reserved for future use." newline bitfld.long 0x0 6. "ERROR_INJECTION6_ENABLE,Error Injection6 Enable (Specific TLP Error). Enables insertion of errors into the packets that you select. You can set this bit to '1' when you have disabled RAS datapath protection (DP) by setting CX_RASDP = CX_RASDP_RAM_PROT.." "0,1" newline bitfld.long 0x0 5. "ERROR_INJECTION5_ENABLE,Error Injection5 Enable (TLP Duplicate/Nullify Error). Enables insertion of duplicate/nullified TLPs. For more details see the EINJ5_SP_TLP_REG register. Note: This register field is sticky." "0,1" newline bitfld.long 0x0 4. "ERROR_INJECTION4_ENABLE,Error Injection4 Enable (FC Credit Update Error). Enables insertion of errors into UpdateFCs. For more details see the EINJ4_FC_REG register. Note: This register field is sticky." "0,1" newline bitfld.long 0x0 3. "ERROR_INJECTION3_ENABLE,Error Injection3 Enable (Symbol DataK Mask Error or Sync Header Error). Enables DataK masking of special symbols or the breaking of the sync header. For more details see the EINJ3_SYMBOL_REG register. Note: This register field is.." "0,1" newline bitfld.long 0x0 2. "ERROR_INJECTION2_ENABLE,Error Injection2 Enable (DLLP Error). Enables insertion of DLLP errors. For more details see the EINJ2_DLLP_REG register. Note: This register field is sticky." "0,1" newline bitfld.long 0x0 1. "ERROR_INJECTION1_ENABLE,Error Injection1 Enable (Sequence Number Error). Enables insertion of errors into sequence numbers. For more details see the EINJ1_SEQNUM_REG register. Note: This register field is sticky." "0,1" newline bitfld.long 0x0 0. "ERROR_INJECTION0_ENABLE,Error Injection0 Enable (CRC Error). Enables insertion of errors into various CRC. For more details see the EINJ0_CRC_REG register. Note: This register field is sticky." "0,1" line.long 0x4 "EINJ0_CRC_REG,Error Injection Control 0 (CRC Error). Controls the insertion of errors into the CRC. and parity of ordered sets for the selected type of the packets as follows: - LCRC. Bad TLP will be detected at the receiver side; receiver responds with.." hexmask.long.tbyte 0x4 12.--31. 1. "RSVDP_12,Reserved for future use." newline hexmask.long.byte 0x4 8.--11. 1. "EINJ0_CRC_TYPE,Error injection type. Selects the type of CRC error to be inserted. Tx Path - 0000b: New TLP's LCRC error injection - 0001b: 16bCRC error injection of ACK/NAK DLLP - 0010b: 16bCRC error injection of Update-FC DLLP - 0011b: New TLP's ECRC.." newline hexmask.long.byte 0x4 0.--7. 1. "EINJ0_COUNT,Error injection count. Indicates the number of errors. This register is decremented when the errors have been inserted. - If the counter value is 0x01 and error is inserted ERROR_INJECTION0_ENABLE in EINJ_ENABLE_REG returns 0b. - If the.." line.long 0x8 "EINJ1_SEQNUM_REG,Error Injection Control 1 (Sequence Number Error). Controls the sequence number of the specific TLPs and ACK/NAK DLLPs. Data Link Protocol Error will be detected at the Rx side of ACK/NAL DLLPs when one of these conditions is true: -.." rbitfld.long 0x8 29.--31. "RSVDP_29,Reserved for future use." "0,1,2,3,4,5,6,7" newline hexmask.long.word 0x8 16.--28. 1. "EINJ1_BAD_SEQNUM,Bad sequence number. Indicates the value to add/subtract from the naturally-assigned sequence numbers. This value is represented by two's complement. - 0x0FFF: +4095 - .. - 0x0002: +2 - 0x0001: +1 - 0x0000: 0 - 0x1FFF: -1 - 0x1FFE: -2 -.." newline hexmask.long.byte 0x8 9.--15. 1. "RSVDP_9,Reserved for future use." newline bitfld.long 0x8 8. "EINJ1_SEQNUM_TYPE,Sequence number type. Selects the type of sequence number. - 0b: Insertion of New TLP's SEQ# error - 1b: Insertion of ACK/NAK DLLP's SEQ# Error Note: This register field is sticky." "0,1" newline hexmask.long.byte 0x8 0.--7. 1. "EINJ1_COUNT,Error injection count. Indicates the number of errors. This register is decremented as the errors are being inserted. - If the counter value is 0x01 and error is inserted ERROR_INJECTION1_ENABLE in EINJ_ENABLE_REG returns '0'. - If the.." line.long 0xC "EINJ2_DLLP_REG,Error Injection Control 2 (DLLP Error). Controls the transmission of DLLPs and inserts the following errors: - If 'ACK/NAK DLLP's transmission block' is selected. replay timeout error will occur at the transmitter of the TLPs and then Data.." hexmask.long.tbyte 0xC 10.--31. 1. "RSVDP_10,Reserved for future use." newline bitfld.long 0xC 8.--9. "EINJ2_DLLP_TYPE,DLLP Type. Selects the type of DLLP errors to be inserted. - 00b: ACK/NAK DLLP's transmission block - 01b: Update FC DLLP's transmission block - 10b: Always Transmission for NAK DLLP - 11b: Reserved Note: This register field is sticky." "0,1,2,3" newline hexmask.long.byte 0xC 0.--7. 1. "EINJ2_COUNT,Error injection count. Indicates the number of errors. This register is decremented as the errors are being inserted. - If the counter value is 0x01 and the error is inserted ERROR_INJECTION2_ENABLE in EINJ_ENABLE_REG returns '0'. - If the.." line.long 0x10 "EINJ3_SYMBOL_REG,Error Injection Control 3 (Symbol Error). When 8b/10b encoding is used. this register controls error insertion into the special (K code) symbols. - If TS1/TS2/FTS/E-Idle/SKP is selected. it affects whole of the ordered set. It might.." hexmask.long.tbyte 0x10 11.--31. 1. "RSVDP_11,Reserved for future use." newline bitfld.long 0x10 8.--10. "EINJ3_SYMBOL_TYPE,Error Type. 8b/10b encoding - Mask K symbol. It is not supported to insert errors into the first ordered-set after exiting from TxElecIdle when CX_FREQ_STEP_EN has been enabled. - 000b: Reserved - 001b: COM/PAD(TS1 Order set) - 010b:.." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x10 0.--7. 1. "EINJ3_COUNT,Error injection count. Indicates the number of errors. This register is decremented as the errors are being inserted. - If the counter value is 0x01 and error is inserted ERROR_INJECTION3_ENABLE in EINJ_ENABLE_REG returns '0'. - If the.." line.long 0x14 "EINJ4_FC_REG,Error Injection Control 4 (FC Credit Error). Controls error insertion into the credit value in the UpdateFCs. It is possible to insert errors for any of the following types: - Posted TLP Header credit - Non-Posted TLP Header credit -.." rbitfld.long 0x14 29.--31. "RSVDP_29,Reserved for future use." "0,1,2,3,4,5,6,7" newline hexmask.long.word 0x14 16.--28. 1. "EINJ4_BAD_UPDFC_VALUE,Bad update-FC credit value. Indicates the value to add/subtract from the UpdateFC credit. This value is represented by two's complement. - 0x0FFF: +4095 - .. - 0x0002: +2 - 0x0001: +1 - 0x0000: 0 - 0x1FFF: -1 - 0x1FFE: -2 - .. -.." newline rbitfld.long 0x14 15. "RSVDP_15,Reserved for future use." "0,1" newline bitfld.long 0x14 12.--14. "EINJ4_VC_NUMBER,VC Number. Indicates target VC Number. Note: This register field is sticky." "0,1,2,3,4,5,6,7" newline rbitfld.long 0x14 11. "RSVDP_11,Reserved for future use." "0,1" newline bitfld.long 0x14 8.--10. "EINJ4_UPDFC_TYPE,Update-FC type. Selects the credit type. - 000b: Posted TLP Header Credit value control - 001b: Non-Posted TLP Header Credit value control - 010b: Completion TLP Header Credit value control - 011b: Reserved - 100b: Posted TLP Data Credit.." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x14 0.--7. 1. "EINJ4_COUNT,Error injection count. Indicates the number of errors. This register is decremented as the errors are being inserted. - If the counter value is 0x01 and error is inserted ERROR_INJECTION4_ENABLE in EINJ_ENABLE_REG returns '0'. - If the.." line.long 0x18 "EINJ5_SP_TLP_REG,Error Injection Control 5 (Specific TLP Error). Controls the generation of specified TLPs. Correctable errors will occur which will be fixed by the PCIe protocol. - For Duplicate TLP. the controller initiates Data Link Retry by handling.." hexmask.long.tbyte 0x18 9.--31. 1. "RSVDP_9,Reserved for future use." newline bitfld.long 0x18 8. "EINJ5_SPECIFIED_TLP,Specified TLP. Selects the specified TLP to be inserted. - 0: Generates duplicate TLPs by handling ACK DLLP as NAK DLLP. - 1: Generates Nullified TLP (Original TLP will be stored in retry buffer). Note: This register field is sticky." "Generates duplicate TLPs by handling ACK DLLP as..,Generates Nullified TLP" newline hexmask.long.byte 0x18 0.--7. 1. "EINJ5_COUNT,Error injection count. Indicates the number of errors. This register is decremented as the errors are being inserted. - If the counter value is 0x01 and error is inserted ERROR_INJECTION5_ENABLE in EINJ_ENABLE_REG returns '0'. - If the.." line.long 0x1C "EINJ6_COMPARE_POINT_H0_REG,Error Injection Control 6 (Compare Point Header DWORD #0). Program this register for the 1st DWORD of TLP header/prefix. It is necessary to carefully consider the endianness when you program this register. Bits [31:0] =.." hexmask.long 0x1C 0.--31. 1. "EINJ6_COMPARE_POINT_H0,Packet Compare Point: 1st DWORD. Specifies which Tx TLP header DWORD#0 bits to compare with the corresponding bits in the Packet Compare Value registers (EINJ6_COMPARE_VALUE*). When all specified bits (in the Tx TLP header and.." line.long 0x20 "EINJ6_COMPARE_POINT_H1_REG,Error Injection Control 6 (Compare Point Header DWORD #1). Program this register for the 2nd DWORD of TLP header/prefix. It is necessary to carefully consider the endianness when you program this register. Bits [31:0] =.." hexmask.long 0x20 0.--31. 1. "EINJ6_COMPARE_POINT_H1,Packet Compare Point: 2nd DWORD. Specifies which Tx TLP header DWORD#1 bits to compare with the corresponding bits in the Packet Compare Value registers (EINJ6_COMPARE_VALUE*). When all specified bits (in the Tx TLP header and.." line.long 0x24 "EINJ6_COMPARE_POINT_H2_REG,Error Injection Control 6 (Compare Point Header DWORD #2). Program this register for the 3rd DWORD of TLP header/prefix. It is necessary to carefully consider the endianness when you program this register. Bits [31:0] =.." hexmask.long 0x24 0.--31. 1. "EINJ6_COMPARE_POINT_H2,Packet Compare Point: 3rd DWORD. Specifies which Tx TLP header DWORD#2 bits to compare with the corresponding bits in the Packet Compare Value registers (EINJ6_COMPARE_VALUE*). When all specified bits (in the Tx TLP header and.." line.long 0x28 "EINJ6_COMPARE_POINT_H3_REG,Error Injection Control 6 (Compare Point Header DWORD #3). Program this register for the 4th DWORD of TLP header/prefix. It is necessary to carefully consider the endianness when you program this register. Bits [31:0] =.." hexmask.long 0x28 0.--31. 1. "EINJ6_COMPARE_POINT_H3,Packet Compare Point: 4th DWORD. Specifies which Tx TLP header DWORD#3 bits to compare with the corresponding bits in the Packet Compare Value registers (EINJ6_COMPARE_VALUE*). When all specified bits (in the Tx TLP header and.." line.long 0x2C "EINJ6_COMPARE_VALUE_H0_REG,Error Injection Control 6 (Compare Value Header DWORD #0). Program this register for the 1st DWORD of TLP header/prefix. It is necessary to carefully consider the endianness when you program this register. Bits [31:0] =.." hexmask.long 0x2C 0.--31. 1. "EINJ6_COMPARE_VALUE_H0,Packet Compare Value: 1st DWORD. Specifies the value to compare against Tx the TLP header DWORD#0 bits specified in the Packet Compare Point registers (EINJ6_COMPARE_POINT*). Note: This register field is sticky." line.long 0x30 "EINJ6_COMPARE_VALUE_H1_REG,Error Injection Control 6 (Compare Value Header DWORD #1). Program this register for the 2nd DWORD of TLP header/prefix. It is necessary to carefully consider the endianness when you program this register. Bits [31:0] =.." hexmask.long 0x30 0.--31. 1. "EINJ6_COMPARE_VALUE_H1,Packet Compare Value: 2nd DWORD. Specifies the value to compare against Tx the TLP header DWORD#1 bits specified in the Packet Compare Point registers (EINJ6_COMPARE_POINT*). Note: This register field is sticky." line.long 0x34 "EINJ6_COMPARE_VALUE_H2_REG,Error Injection Control 6 (Compare Value Header DWORD #2). Program this register for the 3rd DWORD of TLP header/prefix. It is necessary to carefully consider the endianness when you program this register. Bits [31:0] =.." hexmask.long 0x34 0.--31. 1. "EINJ6_COMPARE_VALUE_H2,Packet Compare Value: 3rd DWORD. Specifies the value to compare against Tx the TLP header DWORD#2 bits specified in the Packet Compare Point registers (EINJ6_COMPARE_POINT*). Note: This register field is sticky." line.long 0x38 "EINJ6_COMPARE_VALUE_H3_REG,Error Injection Control 6 (Compare Value Header DWORD #3). Program this register for the 4th DWORD of TLP header/prefix. It is necessary to carefully consider the endianness when you program this register. Bits [31:0] =.." hexmask.long 0x38 0.--31. 1. "EINJ6_COMPARE_VALUE_H3,Packet Compare Value: 4th DWORD. Specifies the value to compare against Tx the TLP header DWORD#3 bits specified in the Packet Compare Point registers (EINJ6_COMPARE_POINT*). Note: This register field is sticky." line.long 0x3C "EINJ6_CHANGE_POINT_H0_REG,Error Injection Control 6 (Change Point Header DWORD #0). Program this register for the 1st DWORD of TLP header/prefix. It is necessary to carefully consider the endianness when you program this register. Bits [31:0] =.." hexmask.long 0x3C 0.--31. 1. "EINJ6_CHANGE_POINT_H0,Packet Change Point: 1st DWORD. Specifies which Tx TLP header DWORD#0 bits to replace with the corresponding bits in the Packet Change Value registers (EINJ6_CHANGE_VALUE*). Note: This register field is sticky." line.long 0x40 "EINJ6_CHANGE_POINT_H1_REG,Error Injection Control 6 (Change Point Header DWORD #1). Program this register for the 2nd DWORD of TLP header/prefix. It is necessary to carefully consider the endianness when you program this register. Bits [31:0] =.." hexmask.long 0x40 0.--31. 1. "EINJ6_CHANGE_POINT_H1,Packet Change Point: 2nd DWORD. Specifies which Tx TLP header DWORD#1 bits to replace with the corresponding bits in the Packet Change Value registers (EINJ6_CHANGE_VALUE*). Note: This register field is sticky." line.long 0x44 "EINJ6_CHANGE_POINT_H2_REG,Error Injection Control 6 (Change Point Header DWORD #2). Program this register for the 3rd DWORD of TLP header/prefix. It is necessary to carefully consider the endianness when you program this register. Bits [31:0] =.." hexmask.long 0x44 0.--31. 1. "EINJ6_CHANGE_POINT_H2,Packet Change Point: 3rd DWORD. Specifies which Tx TLP header DWORD#2 bits to replace with the corresponding bits in the Packet Change Value registers (EINJ6_CHANGE_VALUE*). Note: This register field is sticky." line.long 0x48 "EINJ6_CHANGE_POINT_H3_REG,Error Injection Control 6 (Change Point Header DWORD #3). Program this register for the 4th DWORD of TLP header/prefix. It is necessary to carefully consider the endianness when you program this register. Bits [31:0] =.." hexmask.long 0x48 0.--31. 1. "EINJ6_CHANGE_POINT_H3,Packet Change Point: 4th DWORD. Specifies which Tx TLP header DWORD#3 bits to replace with the corresponding bits in the Packet Change Value registers (EINJ6_CHANGE_VALUE*). Note: This register field is sticky." line.long 0x4C "EINJ6_CHANGE_VALUE_H0_REG,Error Injection Control 6 (Change Value Header DWORD #0). Program this register for the 1st DWORD of TLP header/prefix. It is necessary to carefully consider the endianness when you program this register. Bits [31:0] =.." hexmask.long 0x4C 0.--31. 1. "EINJ6_CHANGE_VALUE_H0,Packet Change Value: 1st DWORD. Specifies replacement values for the Tx TLP header DWORD#0 bits defined in the Packet Change Point registers (EINJ6_CHANGE_POINT*). Only applies when the EINJ6_INVERTED_CONTROL field in EINJ6_TLP_REG.." line.long 0x50 "EINJ6_CHANGE_VALUE_H1_REG,Error Injection Control 6 (Change Value Header DWORD #1). Program this register for the 2nd DWORD of TLP header/prefix. It is necessary to carefully consider the endianness when you program this register. Bits [31:0] =.." hexmask.long 0x50 0.--31. 1. "EINJ6_CHANGE_VALUE_H1,Packet Change Value: 2nd DWORD. Specifies replacement values for the Tx TLP header DWORD#1 bits defined in the Packet Change Point registers (EINJ6_CHANGE_POINT*). Only applies when the EINJ6_INVERTED_CONTROL field in EINJ6_TLP_REG.." line.long 0x54 "EINJ6_CHANGE_VALUE_H2_REG,Error Injection Control 6 (Change Value Header DWORD #2). Program this register for the 3rd DWORD of TLP header/prefix. It is necessary to carefully consider the endianness when you program this register. Bits [31:0] =.." hexmask.long 0x54 0.--31. 1. "EINJ6_CHANGE_VALUE_H2,Packet Change Value: 3rd DWORD. Specifies replacement values for the Tx TLP header DWORD#2 bits defined in the Packet Change Point registers (EINJ6_CHANGE_POINT*). Only applies when the EINJ6_INVERTED_CONTROL field in EINJ6_TLP_REG.." line.long 0x58 "EINJ6_CHANGE_VALUE_H3_REG,Error Injection Control 6 (Change Value Header DWORD #3). Program this register for the 4th DWORD of TLP header/prefix. It is necessary to carefully consider the endianness when you program this register. Bits [31:0] =.." hexmask.long 0x58 0.--31. 1. "EINJ6_CHANGE_VALUE_H3,Packet Change Value: 4th DWORD. Specifies replacement values for the Tx TLP header DWORD#3 bits defined in the Packet Change Point registers (EINJ6_CHANGE_POINT*). Only applies when the EINJ6_INVERTED_CONTROL field in EINJ6_TLP_REG.." line.long 0x5C "EINJ6_TLP_REG,Error Injection Control 6 (Packet Error). The Packet Compare Point registers (EINJ6_COMPARE_POINT*) specify which Tx TLP header bits to compare with the corresponding bits in the Packet Compare Value registers (EINJ6_COMPARE_VALUE*). When.." hexmask.long.tbyte 0x5C 12.--31. 1. "RSVDP_12,Reserved for future use." newline bitfld.long 0x5C 9.--11. "EINJ6_PACKET_TYPE,Packet type. Selects the TLP packets to inject errors into. - 0: TLP Header - 1: TLP Prefix 1st 4-DWORDs - 2: TLP Prefix 2nd -DWORDs - Else: Reserved Note: This register field is sticky." "TLP Header,TLP Prefix 1st 4-DWORDs,TLP Prefix 2nd -DWORDs,?,?,?,?,?" newline bitfld.long 0x5C 8. "EINJ6_INVERTED_CONTROL,Inverted Error Injection Control. - 0: EINJ6_CHANGE_VALUE_H[0/1/2/3] is used to replace bits specified by EINJ6_CHANGE_POINT_H[0/1/2/3]. - 1: EINJ6_CHANGE_VALUE_H[0/1/2/3] is ignored and inverts bits specified by.." "EINJ6_CHANGE_VALUE_H[0/1/2/3] is used to replace..,EINJ6_CHANGE_VALUE_H[0/1/2/3] is ignored and.." newline hexmask.long.byte 0x5C 0.--7. 1. "EINJ6_COUNT,Error Injection Count. Indicates the number of errors to insert. This counter is decremented while errors are been inserted. - If the counter value is 0x01 and error is inserted ERROR_INJECTION6_ENABLE in EINJ_ENABLE_REG returns '0'. - If.." group.long (0xA0+0x30C)++0x7 line.long 0x0 "SD_CONTROL1_REG,Silicon Debug Control 1. For more details. see the RAS DES section in the Core Operations chapter of the Databook." hexmask.long.byte 0x0 24.--31. 1. "RSVDP_24,Reserved for future use." newline bitfld.long 0x0 22.--23. "LOW_POWER_INTERVAL,Low Power Entry Interval Time. Interval Time that the controller starts monitoring RXELECIDLE signal after L0s/L1/L2 entry. You should set the value according to the latency from receiving EIOS to RXELECIDLE assertion at the PHY. -.." "0,1,2,3" newline bitfld.long 0x0 20.--21. "TX_EIOS_NUM,Number of Tx EIOS. This register sets the number of transmit EIOS for L0s/L1 entry and Disable/Loopback/Hot-reset exit. The controller selects the greater value between this register and the value defined by the PCI-SIG specification. 2.5GT/s.." "0,1,2,3" newline rbitfld.long 0x0 17.--19. "RSVDP_17,Reserved for future use." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 16. "FORCE_DETECT_LANE_EN,Force Detect Lane Enable. When this bit is set the controller ignores receiver detection from PHY during LTSSM Detect state and uses FORCE_DETECT_LANE. Note: This register field is sticky." "0,1" newline hexmask.long.word 0x0 0.--15. 1. "FORCE_DETECT_LANE,Force Detect Lane. When the FORCE_DETECT_LANE_EN field is set the controller ignores receiver detection from PHY during LTSSM Detect state and uses this value instead. - 0: Lane0 - 1: Lane1 - 2: Lane2 - .. - 15: Lane15 Note: This.." line.long 0x4 "SD_CONTROL2_REG,Silicon Debug Control 2. For more details. see the RAS DES section in the Core Operations chapter of the Databook." hexmask.long.word 0x4 17.--31. 1. "RSVDP_17,Reserved for future use." newline bitfld.long 0x4 16. "FRAMING_ERR_RECOVERY_DISABLE,Framing Error Recovery Disable. This bit disables a transition to Recovery state when a Framing Error is occurred. Note: This register field is sticky." "0,1" newline hexmask.long.byte 0x4 11.--15. 1. "RSVDP_11,Reserved for future use." newline bitfld.long 0x4 10. "DIRECT_LPBKSLV_TO_EXIT,Direct Loopback Slave To Exit. When this bit is set and the LTSSM is in Loopback Slave Active State the LTSSM transitions to Loopback Slave Exit state. Note: This register field is sticky." "0,1" newline bitfld.long 0x4 9. "DIRECT_POLCOMP_TO_DETECT,Direct Polling.Compliance to Detect. When this bit is set and the LTSSM is in Polling Compliance State the LTSSM transitions to Detect state. Note: This register field is sticky." "0,1" newline bitfld.long 0x4 8. "DIRECT_RECIDLE_TO_CONFIG,Direct Recovery.Idle to Configuration. When this bit is set and the LTSSM is in Recovery Idle State the LTSSM transitions to Configuration state. Note: This register field is sticky." "0,1" newline hexmask.long.byte 0x4 3.--7. 1. "RSVDP_3,Reserved for future use." newline bitfld.long 0x4 2. "NOACK_FORCE_LINKDOWN,Force LinkDown. When this bit is set and the controller detects REPLY_NUM rolling over 4 times the LTSSM transitions to Detect State. Note: This register field is sticky." "0,1" newline bitfld.long 0x4 1. "RECOVERY_REQUEST,Recovery Request. When this bit is set to '1' in L0 or L0s the LTSSM starts transitioning to Recovery State. This request does not cause a speed change or re-equalization." "0,1" newline bitfld.long 0x4 0. "HOLD_LTSSM,Hold and Release LTSSM. For as long as this register is '1' the controller stays in the current LTSSM. Note: This register field is sticky." "0,1" group.long (0xB0+0x30C)++0xB line.long 0x0 "SD_STATUS_L1LANE_REG,Silicon Debug Status(Layer1 Per-lane). This viewport register returns the data selected by the following field: - LANE_SELECT in SD_STATUS_L1LANE_REG For more details. see the RAS DES section in the Core Operations chapter of the.." hexmask.long.byte 0x0 24.--31. 1. "DESKEW_POINTER,Deskew Pointer. Indicates Deskew pointer of internal Deskew buffer of selected lane number(LANE_SELECT). Note: This register field is sticky." newline rbitfld.long 0x0 21.--23. "RSVDP_21,Reserved for future use." "0,1,2,3,4,5,6,7" newline rbitfld.long 0x0 20. "PIPE_TXELECIDLE,PIPE:TxElecIdle. Indicates PIPE TXELECIDLE signal of selected lane number(LANE_SELECT). Note: This register field is sticky." "0,1" newline rbitfld.long 0x0 19. "PIPE_RXELECIDLE,PIPE:RxElecIdle. Indicates PIPE RXELECIDLE signal of selected lane number(LANE_SELECT). Note: This register field is sticky." "0,1" newline rbitfld.long 0x0 18. "PIPE_RXVALID,PIPE:RxValid. Indicates PIPE RXVALID signal of selected lane number(LANE_SELECT). Note: This register field is sticky." "0,1" newline rbitfld.long 0x0 17. "PIPE_DETECT_LANE,PIPE:Detect Lane. Indicates whether PHY indicates receiver detection or not on selected lane number(LANE_SELECT). Note: This register field is sticky." "0,1" newline rbitfld.long 0x0 16. "PIPE_RXPOLARITY,PIPE:RxPolarity. Indicates PIPE RXPOLARITY signal of selected lane number(LANE_SELECT). Note: This register field is sticky." "0,1" newline hexmask.long.word 0x0 4.--15. 1. "RSVDP_4,Reserved for future use." newline hexmask.long.byte 0x0 0.--3. 1. "LANE_SELECT,Lane Select. Lane Select register for Silicon Debug Status Register of Layer1-PerLane. - 0x0: Lane0 - 0x1: Lane1 - 0x2: Lane2 - .. - 0xF: Lane15 Note: This register field is sticky." line.long 0x4 "SD_STATUS_L1LTSSM_REG,Silicon Debug Status(Layer1 LTSSM). For more details. see the RAS DES section in the Core Operations chapter of the Databook." hexmask.long.word 0x4 16.--31. 1. "LTSSM_VARIABLE,LTSSM Variable. Indicates internal LTSSM variables defined in the PCI Express Base Specification. C-PCIe Mode: - 0: directed_speed_change - 1: changed_speed_recovery - 2: successful_speed_negotiation - 3: upconfigure_capable; Set to '1' if.." newline rbitfld.long 0x4 15. "LANE_REVERSAL,Lane Reversal Operation. Receiver detected lane reversal. This field is only valid in the L0 LTSSM state. Note: This register field is sticky." "0,1" newline hexmask.long.byte 0x4 11.--14. 1. "RSVDP_11,Reserved for future use." newline rbitfld.long 0x4 8.--10. "PIPE_POWER_DOWN,PIPE:PowerDown. Indicates PIPE PowerDown signal. Note: This register field is sticky." "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 7. "FRAMING_ERR,Framing Error. Indicates Framing Error detection status." "0,1" newline hexmask.long.byte 0x4 0.--6. 1. "FRAMING_ERR_PTR,First Framing Error Pointer. Identifies the first Framing Error using the following encoding. The field contents are only valid value when FRAMING_ERR =1. Received Unexpected Framing Token - 01h: When non- STP/SDP/IDL Token was received.." line.long 0x8 "SD_STATUS_PM_REG,Silicon Debug Status(PM). For more details. see the RAS DES section in the Core Operations chapter of the Databook." hexmask.long.byte 0x8 24.--31. 1. "RSVDP_24,Reserved for future use." newline hexmask.long.byte 0x8 16.--23. 1. "LATCHED_NFTS,Latched N_FTS. Indicates the value of N_FTS in the received TS Ordered Sets from the Link Partner Note: This register field is sticky." newline rbitfld.long 0x8 13.--15. "L1SUB_STATE,L1Sub State. Indicates internal state machine of L1Sub state. - 0h: S_L1_U : idle state - 1h: S_L1_0 : wait for aux_clk_active - 2h: S_L1_0_WAIT4_ACK : wait for pclkack - 3h: S_L1_0_WAIT4_CLKREQ : wait for clkreq - 4h: S_L1_N_ENTRY : check.." "wait for aux_clk_active,?,?,?,?,?,?,?" newline bitfld.long 0x8 12. "PME_RESEND_FLAG,PME Re-send flag. When the DUT sends a PM_PME message TLP the DUT sets PME_Status bit. If host software does not clear PME_Status bit for 100ms(+50%/-5%) the DUT resends the PM_PME Message. This bit indicates that a PM_PME was resent." "0,1" newline hexmask.long.byte 0x8 8.--11. 1. "INTERNAL_PM_SSTATE,Internal PM State(Slave). Indicates internal state machine of Power Management Slave controller. - 0h: S_IDLE - 1h: S_RESPOND_NAK - 2h: S_BLOCK_TLP - 3h: S_WAIT_LAST_TLP_ACK - 4h: S_WAIT_EIDLE - 5h: S_LINK_ENTR_L1 - 6h: S_L1 - 7h:.." newline rbitfld.long 0x8 5.--7. "RSVDP_5,Reserved for future use." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x8 0.--4. 1. "INTERNAL_PM_MSTATE,Internal PM State(Master). Indicates internal state machine of Power Management Master controller. - 00h: IDLE - 01h: L0 - 02h: L0S - 03h: ENTER_L0S - 04h: L0S_EXIT - 05h: WAIT_PMCSR_CPL_SENT - 08h: L1 - 09h: L1_BLOCK_TLP - 0Ah:.." rgroup.long (0xBC+0x30C)++0x3 line.long 0x0 "SD_STATUS_L2_REG,Silicon Debug Status(Layer2). For more details. see the RAS DES section in the Core Operations chapter of the Databook." hexmask.long.byte 0x0 28.--31. 1. "RSVDP_28,Reserved for future use." newline bitfld.long 0x0 27. "FC_INIT2,FC_INIT2. Indicates the controller is in FC_INIT2(VC0) state. Note: This register field is sticky." "0,1" newline bitfld.long 0x0 26. "FC_INIT1,FC_INIT1. Indicates the controller is in FC_INIT1(VC0) state. Note: This register field is sticky." "0,1" newline bitfld.long 0x0 24.--25. "DLCMSM,DLCMSM. Indicates the current DLCMSM. - 00b: DL_INACTIVE - 01b: DL_FC_INIT - 11b: DL_ACTIVE Note: This register field is sticky." "0,1,2,3" newline hexmask.long.word 0x0 12.--23. 1. "RX_ACK_SEQ_NO,Tx Ack Sequence Number. Indicates ACKD_SEQ which is updated by receiving ACK/NAK DLLP. Note: This register field is sticky." newline hexmask.long.word 0x0 0.--11. 1. "TX_TLP_SEQ_NO,Tx Tlp Sequence Number. Indicates next transmit sequence number for transmit TLP. Note: This register field is sticky." group.long (0xC0+0x30C)++0x7 line.long 0x0 "SD_STATUS_L3FC_REG,Silicon Debug Status(Layer3 FC). The CREDIT_DATA[0/1] fields in this viewport register return the data for the VC and TLP Type selected by the following fields: - CREDIT_SEL_VC - CREDIT_SEL_CREDIT_TYPE - CREDIT_SEL_TLP_TYPE -.." hexmask.long.word 0x0 20.--31. 1. "CREDIT_DATA1,Credit Data1. Current FC credit data selected by the CREDIT_SEL_VC CREDIT_SEL_CREDIT_TYPE CREDIT_SEL_TLP_TYPE and CREDIT_SEL_HD viewport-select fields. - Rx: Credit Allocated Value - Tx: Credit Limit Value. This value is valid when.." newline hexmask.long.word 0x0 8.--19. 1. "CREDIT_DATA0,Credit Data0. Current FC credit data selected by the CREDIT_SEL_VC CREDIT_SEL_CREDIT_TYPE CREDIT_SEL_TLP_TYPE and CREDIT_SEL_HD viewport-select fields. - Rx: Credit Received Value - Tx: Credit Consumed Value Note: This register field is.." newline rbitfld.long 0x0 7. "RSVDP_7,Reserved for future use." "0,1" newline bitfld.long 0x0 6. "CREDIT_SEL_HD,Credit Select(HeaderData). This field in conjunction with the CREDIT_SEL_VC CREDIT_SEL_CREDIT_TYPE and CREDIT_SEL_TLP_TYPE viewport-select fields determines that data that is returned by the CREDIT_DATA0 and CREDIT_DATA1 data fields. -.." "Header Credit,Data Credit" newline bitfld.long 0x0 4.--5. "CREDIT_SEL_TLP_TYPE,Credit Select(TLP Type). This field in conjunction with the CREDIT_SEL_VC CREDIT_SEL_CREDIT_TYPE and CREDIT_SEL_HD viewport-select fields determines that data that is returned by the CREDIT_DATA0 and CREDIT_DATA1 data fields. - 0x0:.." "Posted,Non-Posted,Completion,?" newline bitfld.long 0x0 3. "CREDIT_SEL_CREDIT_TYPE,Credit Select(Credit Type). This field in conjunction with the CREDIT_SEL_VC CREDIT_SEL_TLP_TYPE and CREDIT_SEL_HD viewport-select fields determines that data that is returned by the CREDIT_DATA0 and CREDIT_DATA1 data fields. -.." "Rx,Tx" newline bitfld.long 0x0 0.--2. "CREDIT_SEL_VC,Credit Select(VC). This field in conjunction with the CREDIT_SEL_CREDIT_TYPE CREDIT_SEL_TLP_TYPE and CREDIT_SEL_HD viewport-select fields determines that data that is returned by the CREDIT_DATA0 and CREDIT_DATA1 data fields. - 0x0: VC0 -.." "VC0,VC1,VC2,?,?,?,?,VC7" line.long 0x4 "SD_STATUS_L3_REG,Silicon Debug Status(Layer3). For more details. see the RAS DES section in the Core Operations chapter of the Databook." hexmask.long.tbyte 0x4 8.--31. 1. "RSVDP_8,Reserved for future use." newline bitfld.long 0x4 7. "MFTLP_STATUS,Malformed TLP Status. Indicates malformed TLP has occurred." "0,1" newline hexmask.long.byte 0x4 0.--6. 1. "MFTLP_POINTER,First Malformed TLP Error Pointer. Indicates the element of the received first malformed TLP. This pointer is validated by MFTLP_STATUS. - 01h: AtomicOp address alignment - 02h: AtomicOp operand - 03h: AtomicOp byte enable - 04h: TLP length.." group.long (0xD0+0x30C)++0xB line.long 0x0 "SD_EQ_CONTROL1_REG,Silicon Debug EQ Control 1. This is a viewport control register. Setting the EQ_RATE_SEL and EQ_LANE_SEL fields in this register determine the per-lane Silicon Debug EQ Status data returned by the SD_EQ_STATUS[1/2/3] viewport.." hexmask.long.byte 0x0 24.--31. 1. "FOM_TARGET,FOM Target. Indicates figure of merit target criteria value of EQ Master(DSP in EQ Phase3/USP in EQ Phase2). This field is only valid when GEN3_EQ_FB_MODE is 0001b(Figure Of Merit). Note: This register field is sticky." newline bitfld.long 0x0 23. "FOM_TARGET_ENABLE,FOM Target Enable. Enables the FOM_TARGET fields. Note: This register field is sticky." "0,1" newline hexmask.long.byte 0x0 18.--22. 1. "RSVDP_18,Reserved for future use." newline bitfld.long 0x0 16.--17. "EVAL_INTERVAL_TIME,Eval Interval Time. Indicates interval time of RxEqEval assertion. - 00: 500ns - 01: 1us - 10: 2us - 11: 4us This field is used for EQ Master(DSP in EQ Phase3/USP in EQ Phase2). Note: This register field is sticky." "0,1,2,3" newline hexmask.long.byte 0x0 10.--15. 1. "RSVDP_10,Reserved for future use." newline bitfld.long 0x0 8.--9. "EXT_EQ_TIMEOUT,Extends EQ Phase2/3 Timeout. This field is used when the Ltssm is in Recovery.EQ2/3. When this field is set the value of EQ2/3 timeout is extended. EQ Master(DSP in EQ Phase3/USP in EQ Phase2). - 00: 24ms (default) - 01: 48ms (x2) - 10:.." "0,1,2,3" newline rbitfld.long 0x0 6.--7. "RSVDP_6,Reserved for future use." "0,1,2,3" newline bitfld.long 0x0 4.--5. "EQ_RATE_SEL,EQ Status Rate Select. Setting this field in conjunction with the EQ_LANE_SEL field determines the per-lane Silicon Debug EQ Status data returned by the SD_EQ_CONTROL[2/3] and SD_EQ_STATUS[1/2/3] viewport registers. - 0x0: 8.0GT/s Speed.." "0,1,2,3" newline hexmask.long.byte 0x0 0.--3. 1. "EQ_LANE_SEL,EQ Status Lane Select. Setting this field in conjunction with the EQ_RATE_SEL field determines the per-lane Silicon Debug EQ Status data returned by the SD_EQ_CONTROL[2/3] and SD_EQ_STATUS[1/2/3] viewport registers. - 0x0: Lane0 - 0x1: Lane1.." line.long 0x4 "SD_EQ_CONTROL2_REG,Silicon Debug EQ Control 2. This viewport register returns the value for the rate and lane selected by the EQ_RATE_SEL and EQ_LANE_SEL fields in the SD_EQ_CONTROL1_REG register. For more details. see the RAS DES section in the Core.." rbitfld.long 0x4 31. "RSVDP_31,Reserved for future use." "0,1" newline bitfld.long 0x4 30. "FORCE_LOCAL_TX_PRESET_ENABLE,Force Local Transmitter Preset Enable. Enables the FORCE_LOCAL_TX_PRESET field. If select rate in the EQ_RATE_SEL field is 32.0GT/s Speed this feature is not available. Note: This register field is sticky." "0,1" newline bitfld.long 0x4 29. "FORCE_LOCAL_RX_HINT_ENABLE,Force Local Receiver Preset Hint Enable. Enables the FORCE_LOCAL_RX_HINT field. If select rate in the EQ_RATE_SEL field is other than 8.0GT/s Speed this feature is not available. Note: This register field is sticky." "0,1" newline bitfld.long 0x4 28. "FORCE_LOCAL_TX_COEF_ENABLE,Force Local Transmitter Coefficient Enable. Enables the following fields: - FORCE_LOCAL_TX_PRE_CURSOR - FORCE_LOCAL_TX_CURSOR - FORCE_LOCAL_TX_POST_CURSOR Note: This register field is sticky." "0,1" newline hexmask.long.byte 0x4 24.--27. 1. "FORCE_LOCAL_TX_PRESET,Force Local Transmitter Preset. Indicates initial preset value of USP in EQ Slave(EQ Phase2) instead of receiving EQ TS2. If select rate in the EQ_RATE_SEL field is 32.0GT/s Speed this feature is not available. Note: This register.." newline rbitfld.long 0x4 21.--23. "RSVDP_21,Reserved for future use." "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 18.--20. "FORCE_LOCAL_RX_HINT,Force Local Receiver Preset Hint. Indicates the RxPresetHint value of EQ Slave(DSP in EQ Phase2/USP in EQ Phase3) instead of received or set value. If select rate in the EQ_RATE_SEL field is other than 8.0GT/s Speed this feature is.." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x4 12.--17. 1. "FORCE_LOCAL_TX_POST_CURSOR,Force Local Transmitter Post-Cursor. Indicates the coefficient value of EQ Slave(DSP in EQ Phase2/USP in EQ Phase3) instead of the value instructed from link partner. Note: This register field is sticky." newline hexmask.long.byte 0x4 6.--11. 1. "FORCE_LOCAL_TX_CURSOR,Force Local Transmitter Cursor. Indicates the coefficient value of EQ Slave(DSP in EQ Phase2/USP in EQ Phase3) instead of the value instructed from link partner. Note: This register field is sticky." newline hexmask.long.byte 0x4 0.--5. 1. "FORCE_LOCAL_TX_PRE_CURSOR,Force Local Transmitter Pre-cursor. Indicates the coefficient value of EQ Slave(DSP in EQ Phase2/USP in EQ Phase3) instead of the value instructed from link partner. Note: This register field is sticky." line.long 0x8 "SD_EQ_CONTROL3_REG,Silicon Debug EQ Control 3. This viewport register returns the value for the rate and lane selected by the EQ_RATE_SEL and EQ_LANE_SEL fields in the SD_EQ_CONTROL1_REG register. For more details. see the RAS DES section in the Core.." rbitfld.long 0x8 29.--31. "RSVDP_29,Reserved for future use." "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 28. "FORCE_REMOTE_TX_COEF_ENABLE,Force Remote Transmitter Coefficient Enable. Enables the following fields: - FORCE_REMOTE_TX_PRE_CURSOR - FORCE_REMOTE_TX_CURSOR - FORCE_REMOTE_TX_POST_CURSOR This function can only be used when GEN3_EQ_FB_MODE =.." "0,1" newline hexmask.long.word 0x8 18.--27. 1. "RSVDP_18,Reserved for future use." newline hexmask.long.byte 0x8 12.--17. 1. "FORCE_REMOTE_TX_POST_CURSOR,Force Remote Transmitter Post-Cursor. Indicates the coefficient value of EQ Master(DSP in EQ Phase3/USP in EQ Phase2) instead of the value instructed from local phy in dirchange mode. Note: This register field is sticky." newline hexmask.long.byte 0x8 6.--11. 1. "FORCE_REMOTE_TX_CURSOR,Force Remote Transmitter Cursor. Indicates the coefficient value of EQ Master(DSP in EQ Phase3/USP in EQ Phase2) instead of the value instructed from local phy in dirchange mode. Note: This register field is sticky." newline hexmask.long.byte 0x8 0.--5. 1. "FORCE_REMOTE_TX_PRE_CURSOR,Force Remote Transmitter Pre-Cursor. Indicates the coefficient value of EQ Master(DSP in EQ Phase3/USP in EQ Phase2) instead of the value instructed from local phy in dirchange mode. Note: This register field is sticky." rgroup.long (0xE0+0x30C)++0xB line.long 0x0 "SD_EQ_STATUS1_REG,Silicon Debug EQ Status 1. This viewport register returns the first of three words of Silicon Debug EQ Status data for the rate and lane selected by the EQ_RATE_SEL and EQ_LANE_SEL fields in the SD_EQ_CONTROL1_REG register. The.." hexmask.long.tbyte 0x0 8.--31. 1. "RSVDP_8,Reserved for future use." newline bitfld.long 0x0 7. "EQ_REJECT_EVENT,EQ Reject Event. Indicates that the controller receives two consecutive TS1 OS w/Reject=1b during EQ Master phase(DSP in EQ Phase3/USP in EQ Phase2). This bit is automatically cleared when the controller starts EQ Master phase again." "0,1" newline bitfld.long 0x0 6. "EQ_RULEC_VIOLATION,EQ Rule C Violation. Indicates that coefficients rule C violation is detected in the values provided by PHY using direction change method during EQ Master phase(DSP in EQ Phase3/USP in EQ Phase2). The coefficients rule C correspond to.." "0,1" newline bitfld.long 0x0 5. "EQ_RULEB_VIOLATION,EQ Rule B Violation. Indicates that coefficients rule B violation is detected in the values provided by PHY using direction change method during EQ Master phase(DSP in EQ Phase3/USP in EQ Phase2). The coefficients rules B correspond to.." "0,1" newline bitfld.long 0x0 4. "EQ_RULEA_VIOLATION,EQ Rule A Violation. Indicates that coefficients rule A violation is detected in the values provided by PHY using direction change method during EQ Master phase(DSP in EQ Phase3/USP in EQ Phase2). The coefficients rules A correspond to.." "0,1" newline bitfld.long 0x0 3. "RSVDP_3,Reserved for future use." "0,1" newline bitfld.long 0x0 1.--2. "EQ_CONVERGENCE_INFO,EQ Convergence Info. Indicates equalization convergence information. - 0x0: Equalization is not attempted - 0x1: Equalization finished successfully - 0x2: Equalization finished unsuccessfully - 0x3: Reserved This bit is automatically.." "Equalization is not attempted,Equalization finished successfully,Equalization finished unsuccessfully,Reserved" newline bitfld.long 0x0 0. "EQ_SEQUENCE,EQ Sequence. Indicates that the controller is starting the equalization sequence. Note: This register field is sticky." "0,1" line.long 0x4 "SD_EQ_STATUS2_REG,Silicon Debug EQ Status 2. This viewport register returns the second of three words of Silicon Debug EQ Status data for the rate and lane selected by the EQ_RATE_SEL and EQ_LANE_SEL fields in the SD_EQ_CONTROL1_REG register. Each field.." hexmask.long.byte 0x4 24.--31. 1. "EQ_LOCAL_FOM_VALUE,EQ Local Figure of Merit. Indicates Local maximum Figure of Merit value. Note: This register field is sticky." newline bitfld.long 0x4 21.--23. "RSVDP_21,Reserved for future use." "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 18.--20. "EQ_LOCAL_RX_HINT,EQ Local Receiver Preset Hint. Indicates Local Receiver Preset Hint value. If select rate in the EQ_RATE_SEL field is other than 8.0GT/s Speed this feature is not available. Note: This register field is sticky." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x4 12.--17. 1. "EQ_LOCAL_POST_CURSOR,EQ Local Post-Cursor. Indicates Local post cursor coefficient value. Note: This register field is sticky." newline hexmask.long.byte 0x4 6.--11. 1. "EQ_LOCAL_CURSOR,EQ Local Cursor. Indicates Local cursor coefficient value. Note: This register field is sticky." newline hexmask.long.byte 0x4 0.--5. 1. "EQ_LOCAL_PRE_CURSOR,EQ Local Pre-Cursor. Indicates Local pre cursor coefficient value. Note: This register field is sticky." line.long 0x8 "SD_EQ_STATUS3_REG,Silicon Debug EQ Status 3. This viewport register returns the third of three words of Silicon Debug EQ Status data for the rate and lane selected by the EQ_RATE_SEL and EQ_LANE_SEL fields in the SD_EQ_CONTROL1_REG register. Each field.." bitfld.long 0x8 30.--31. "RSVDP_30,Reserved for future use." "0,1,2,3" newline hexmask.long.byte 0x8 24.--29. 1. "EQ_REMOTE_FS,EQ Remote FS. Indicates Remote FS value. Note: This register field is sticky." newline hexmask.long.byte 0x8 18.--23. 1. "EQ_REMOTE_LF,EQ Remote LF. Indicates Remote LF value. Note: This register field is sticky." newline hexmask.long.byte 0x8 12.--17. 1. "EQ_REMOTE_POST_CURSOR,EQ Remote Post-Cursor. Indicates Remote post cursor coefficient value. Note: This register field is sticky." newline hexmask.long.byte 0x8 6.--11. 1. "EQ_REMOTE_CURSOR,EQ Remote Cursor. Indicates Remote cursor coefficient value. Note: This register field is sticky." newline hexmask.long.byte 0x8 0.--5. 1. "EQ_REMOTE_PRE_CURSOR,EQ Remote Pre-Cursor. Indicates Remote pre cursor coefficient value. Note: This register field is sticky." tree.end tree "PF0_SN_CAP (Device Serial Number Capability Structure)" group.long (0x0+0x170)++0xB line.long 0x0 "SN_BASE,Device Serial Number Extended Capability Header. For a description of this standard PCIe register. see the PCI Express Base Specification." hexmask.long.word 0x0 20.--31. 1. "SN_NEXT_OFFSET,Next Capability Offset. For a description of this standard PCIe register field see the PCI Express Base Specification. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then.." hexmask.long.byte 0x0 16.--19. 1. "SN_CAP_VERSION,Capability Version. For a description of this standard PCIe register field see the PCI Express Base Specification. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky).." hexmask.long.word 0x0 0.--15. 1. "SN_PCIE_EXTENDED_CAP_ID,Serial Number Extended Capability ID. For a description of this standard PCIe register field see the PCI Express Base Specification. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if.." line.long 0x4 "SER_NUM_REG_DW_1,Serial Number 1 Register. For a description of this standard PCIe register. see the PCI Express Base Specification." hexmask.long 0x4 0.--31. 1. "SN_SER_NUM_REG_1_DW,IEEE 64 bit Device Serial Number (DW 1). For a description of this standard PCIe register field see the PCI Express Base Specification. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if.." line.long 0x8 "SER_NUM_REG_DW_2,Serial Number 2 Register. For a description of this standard PCIe register. see the PCI Express Base Specification." hexmask.long 0x8 0.--31. 1. "SN_SER_NUM_REG_2_DW,IEEE 64 bit Device Serial Number (DW 2). For a description of this standard PCIe register field see the PCI Express Base Specification. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if.." tree.end tree "PF0_VSECRAS_CAP (PF RAS Datapath Protection Capability Structure (VSEC))" group.long (0x0+0x480)++0x3 line.long 0x0 "RASDP_EXT_CAP_HDR_OFF,PCIe Extended capability ID. Capability version and Next capability offset. For a description of this standard PCIe register. see the PCI Express Specification." hexmask.long.word 0x0 20.--31. 1. "NEXT_OFFSET,Next Capability Offset. For a description of this standard PCIe register see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else.." newline hexmask.long.byte 0x0 16.--19. 1. "CAP,Capability Version. For a description of this standard PCIe register see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note:.." newline hexmask.long.word 0x0 0.--15. 1. "ID,PCI Express Extended Capability ID. For a description of this standard PCIe register see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else.." rgroup.long (0x4+0x480)++0x3 line.long 0x0 "RASDP_VENDOR_SPECIFIC_HDR_OFF,Vendor Specific Header. For a description of this standard PCIe register. see the PCI Express Specification." hexmask.long.word 0x0 20.--31. 1. "VSEC_LENGTH,VSEC Length. For a description of this standard PCIe register see the PCI Express Specification. Note: This register field is sticky." newline hexmask.long.byte 0x0 16.--19. 1. "VSEC_REV,VSEC Rev. For a description of this standard PCIe register see the PCI Express Specification. Note: This register field is sticky." newline hexmask.long.word 0x0 0.--15. 1. "VSEC_ID,VSEC ID. For a description of this standard PCIe register see the PCI Express Specification. Note: This register field is sticky." group.long (0x8+0x480)++0x7 line.long 0x0 "RASDP_ERROR_PROT_CTRL_OFF,ECC error correction control. Allows you to disable ECC error correction for RAMs and datapath. When the AXI Bridge Module is implemented and the master / slave clocks are asynchronous to the PCIe native controller clock.." hexmask.long.byte 0x0 24.--31. 1. "RSVDP_24,Reserved for future use." newline bitfld.long 0x0 23. "ERROR_PROT_DISABLE_CXS_RX,Error correction disable for CXS Tx path (PCIe Rx path). Note: This register field is sticky." "0,1" newline bitfld.long 0x0 22. "ERROR_PROT_DISABLE_ADM_RX,Error correction disable for ADM Rx path. Note: This register field is sticky." "0,1" newline bitfld.long 0x0 21. "ERROR_PROT_DISABLE_LAYER3_RX,Error correction disable for layer 3 Rx path. Note: This register field is sticky." "0,1" newline bitfld.long 0x0 20. "ERROR_PROT_DISABLE_LAYER2_RX,Error correction disable for layer 2 Rx path. Note: This register field is sticky." "0,1" newline bitfld.long 0x0 19. "ERROR_PROT_DISABLE_DMA_READ,Error correction disable for DMA read engine. Note: This register field is sticky." "0,1" newline bitfld.long 0x0 18. "ERROR_PROT_DISABLE_AXI_BRIDGE_INBOUND_REQUEST,Error correction disable for AXI bridge inbound request path. Note: This register field is sticky." "0,1" newline bitfld.long 0x0 17. "ERROR_PROT_DISABLE_AXI_BRIDGE_INBOUND_COMPLETION,Error correction disable for AXI bridge inbound completion composer. Does not disable the error detection reporting for 1-bit and 2-bit ECC errors. Note: This register field is sticky." "?,bit and 2-bit ECC errors" newline bitfld.long 0x0 16. "ERROR_PROT_DISABLE_RX,Global error correction disable for all Rx layers. Note: This register field is sticky." "0,1" newline hexmask.long.byte 0x0 9.--15. 1. "RSVDP_9,Reserved for future use." newline bitfld.long 0x0 8. "ERROR_PROT_DISABLE_DTIM_TX,Error correction disable for DTIM Tx path. Note: This register field is sticky." "0,1" newline bitfld.long 0x0 7. "ERROR_PROT_DISABLE_CXS_TX,Error correction disable for CXS Rx path (PCIe Tx path). Note: This register field is sticky." "0,1" newline bitfld.long 0x0 6. "ERROR_PROT_DISABLE_ADM_TX,Error correction disable for Adm Tx path. Note: This register field is sticky." "0,1" newline bitfld.long 0x0 5. "ERROR_PROT_DISABLE_LAYER3_TX,Error correction disable for layer 3 Tx path. Note: This register field is sticky." "0,1" newline bitfld.long 0x0 4. "ERROR_PROT_DISABLE_LAYER2_TX,Error correction disable for layer 2 Tx path. Note: This register field is sticky." "0,1" newline bitfld.long 0x0 3. "ERROR_PROT_DISABLE_DMA_WRITE,Error correction disable for DMA write engine. Note: This register field is sticky." "0,1" newline bitfld.long 0x0 2. "ERROR_PROT_DISABLE_AXI_BRIDGE_OUTBOUND,Error correction disable for AXI bridge outbound request path. Note: This register field is sticky." "0,1" newline bitfld.long 0x0 1. "ERROR_PROT_DISABLE_AXI_BRIDGE_MASTER,Error correction disable for AXI bridge master completion buffer. Note: This register field is sticky." "0,1" newline bitfld.long 0x0 0. "ERROR_PROT_DISABLE_TX,Global error correction disable for all Tx layers. Does not disable the error detection reporting for 1-bit and 2-bit ECC errors. Note: This register field is sticky." "?,bit and 2-bit ECC errors" line.long 0x4 "RASDP_CORR_COUNTER_CTRL_OFF,Corrected error (1-bit ECC) counter selection and control. This is a viewport control register. Setting the CORR_COUNTER_SELECTION_REGION and CORR_COUNTER_SELECTION fields in this register determine the counter data returned.." hexmask.long.byte 0x4 24.--31. 1. "CORR_COUNTER_SELECTION,Counter selection. This field selects the counter ID (within the region defined by CORR_COUNTER_SELECTION_REGION) whose contents can be read from the RASDP_CORR_COUNT_REPORT_OFF register. You can cycle this field value from 0 to.." newline hexmask.long.byte 0x4 20.--23. 1. "CORR_COUNTER_SELECTION_REGION,Select correctable counter region: - 0x0: Region select for Adm Rx path - 0x1: Region select for layer 3 Rx path - 0x2: Region select for layer 2 Rx path - 0x3: Region select for DMA inbound path - 0x4: Region select for AXI.." newline hexmask.long.word 0x4 5.--19. 1. "RSVDP_5,Reserved for future use." newline bitfld.long 0x4 4. "CORR_EN_COUNTERS,Enable correctable errors counters. - 1: counters increment when the controller detects a correctable error - 0: counters are frozen The counters are enabled by default." "counters are frozen,counters increment when the controller detects a.." newline rbitfld.long 0x4 1.--3. "RSVDP_1,Reserved for future use." "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 0. "CORR_CLEAR_COUNTERS,Clear all correctable error counters." "0,1" rgroup.long (0x10+0x480)++0x3 line.long 0x0 "RASDP_CORR_COUNT_REPORT_OFF,Corrected error (1-bit ECC) counter data. This viewport register returns the counter data selected by the CORR_COUNTER_SELECTION_REGION and CORR_COUNTER_SELECTION fields in the RASDP_CORR_COUNTER_CTRL_OFF register." hexmask.long.byte 0x0 24.--31. 1. "CORR_COUNTER_SELECTED,Counter selection. Returns the value set in the CORR_COUNTER_SELECTION field of the RASDP_CORR_COUNTER_CTRL_OFF register." newline hexmask.long.byte 0x0 20.--23. 1. "CORR_COUNTER_SELECTED_REGION,Selected correctable counter region: - 0x0: Region select for Adm Rx path - 0x1: Region select for layer 3 Rx path - 0x2: Region select for layer 2 Rx path - 0x3: Region select for DMA inbound path - 0x4: Region select for.." newline hexmask.long.word 0x0 8.--19. 1. "RSVDP_8,Reserved for future use." newline hexmask.long.byte 0x0 0.--7. 1. "CORR_COUNTER,Current corrected error count for the selected counter." group.long (0x14+0x480)++0x3 line.long 0x0 "RASDP_UNCORR_COUNTER_CTRL_OFF,Uncorrected error (2-bit ECC and parity) counter selection and control. This is a viewport control register. Setting the UNCORR_COUNTER_SELECTION_REGION and UNCORR_COUNTER_SELECTION fields in this register determine the.." hexmask.long.byte 0x0 24.--31. 1. "UNCORR_COUNTER_SELECTION,Counter selection. This field selects the counter ID (within the region defined by UNCORR_COUNTER_SELECTION_REGION) whose contents can be read from the RASDP_UNCORR_COUNT_REPORT_OFF register. You can cycle this field value from 0.." newline hexmask.long.byte 0x0 20.--23. 1. "UNCORR_COUNTER_SELECTION_REGION,Select uncorrectable counter region: - 0x0: Region select for Adm Rx path - 0x1: Region select for layer 3 Rx path - 0x2: Region select for layer 2 Rx path - 0x3: Region select for DMA inbound path - 0x4: Region select for.." newline hexmask.long.word 0x0 5.--19. 1. "RSVDP_5,Reserved for future use." newline bitfld.long 0x0 4. "UNCORR_EN_COUNTERS,Enable uncorrectable errors counters. - 1: enables the counters to increment on detected correctable errors - 0: counters are frozen The counters are enabled by default." "counters are frozen,enables the counters to increment on detected.." newline rbitfld.long 0x0 1.--3. "RSVDP_1,Reserved for future use." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 0. "UNCORR_CLEAR_COUNTERS,Clear uncorrectable errors counters. When asserted causes all counters tracking the uncorrectable errors to be cleared." "0,1" rgroup.long (0x18+0x480)++0x3 line.long 0x0 "RASDP_UNCORR_COUNT_REPORT_OFF,Uncorrected error (2-bit ECC and parity) counter data. This viewport register returns the counter data selected by the UNCORR_COUNTER_SELECTION_REGION and UNCORR_COUNTER_SELECTION fields in the RASDP_UNCORR_COUNTER_CTRL_OFF.." hexmask.long.byte 0x0 24.--31. 1. "UNCORR_COUNTER_SELECTED,Counter selection. Returns the value set in the UNCORR_COUNTER_SELECTION field of the RASDP_UNCORR_COUNTER_CTRL_OFF register." newline hexmask.long.byte 0x0 20.--23. 1. "UNCORR_COUNTER_SELECTED_REGION,Selected uncorrectable counter region: - 0x0: Region select for Adm Rx path - 0x1: Region select for layer 3 Rx path - 0x2: Region select for layer 2 Rx path - 0x3: Region select for DMA inbound path - 0x4: Region select.." newline hexmask.long.word 0x0 8.--19. 1. "RSVDP_8,Reserved for future use." newline hexmask.long.byte 0x0 0.--7. 1. "UNCORR_COUNTER,Current uncorrected error count for the selected counter" group.long (0x1C+0x480)++0x3 line.long 0x0 "RASDP_ERROR_INJ_CTRL_OFF,Error injection control for the following features: - 1-bit or 2-bit injection - Continuous or fixed-number (n) injection modes - Global enable/disable - Selectable location where injection occurs" hexmask.long.byte 0x0 24.--31. 1. "RSVDP_24,Reserved for future use." newline hexmask.long.byte 0x0 16.--23. 1. "ERROR_INJ_LOC,Error injection location. Selects where error injection takes place. You can cycle this field value from 0 to 255 to access all locations according to the detailed report of check points at.." newline hexmask.long.byte 0x0 8.--15. 1. "ERROR_INJ_COUNT,Error injection count. - 0: errors are inserted in every TLP until you clear ERROR_INJ_EN. - 1: one errors injected - 2: two errors injected - n: amount of errors injected" newline rbitfld.long 0x0 6.--7. "RSVDP_6,Reserved for future use." "0,1,2,3" newline bitfld.long 0x0 4.--5. "ERROR_INJ_TYPE,Error injection type: - 0: none - 1: 1-bit - 2: 2-bit" "none,bit,bit,?" newline rbitfld.long 0x0 1.--3. "RSVDP_1,Reserved for future use." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 0. "ERROR_INJ_EN,Error injection global enable. When set enables the error insertion logic." "0,1" rgroup.long (0x20+0x480)++0x7 line.long 0x0 "RASDP_CORR_ERROR_LOCATION_OFF,Corrected errors locations. For more details. see the RAS Data Protection (DP) section in the Core Operations chapter of the Databook." hexmask.long.byte 0x0 24.--31. 1. "LOC_LAST_CORR_ERROR,Location/ID of the last corrected error within the region defined by REG_LAST_CORR_ERROR. You can cycle this field value from 0 to 255 to access all counters according to the detailed report of check points at.." newline hexmask.long.byte 0x0 20.--23. 1. "REG_LAST_CORR_ERROR,Region of the last corrected error: - 0x0: Region select for Adm Rx path - 0x1: Region select for layer 3 Rx path - 0x2: Region select for layer 2 Rx path - 0x3: Region select for DMA inbound path - 0x4: Region select for AXI bridge.." newline hexmask.long.byte 0x0 16.--19. 1. "RSVDP_16,Reserved for future use." newline hexmask.long.byte 0x0 8.--15. 1. "LOC_FIRST_CORR_ERROR,Location/ID of the first corrected error within the region defined by REG_FIRST_CORR_ERROR. You can cycle this field value from 0 to 255 to access all counters according to the detailed report of check points at.." newline hexmask.long.byte 0x0 4.--7. 1. "REG_FIRST_CORR_ERROR,Region of the first corrected error: - 0x0: Region select for Adm Rx path - 0x1: Region select for layer 3 Rx path - 0x2: Region select for layer 2 Rx path - 0x3: Region select for DMA inbound path - 0x4: Region select for AXI bridge.." newline hexmask.long.byte 0x0 0.--3. 1. "RSVDP_0,Reserved for future use." line.long 0x4 "RASDP_UNCORR_ERROR_LOCATION_OFF,Uncorrected errors locations. For more details. see the RAS Data Protection (DP) section in the Core Operations chapter of the Databook." hexmask.long.byte 0x4 24.--31. 1. "LOC_LAST_UNCORR_ERROR,Location/ID of the last uncorrected error within the region defined by REG_LAST_UNCORR_ERROR. You can cycle this field value from 0 to 255 to access all counters according to the detailed report of check points at.." newline hexmask.long.byte 0x4 20.--23. 1. "REG_LAST_UNCORR_ERROR,Region of the last uncorrected error: - 0x0: Region select for Adm Rx path - 0x1: Region select for layer 3 Rx path - 0x2: Region select for layer 2 Rx path - 0x3: Region select for DMA inbound path - 0x4: Region select for AXI.." newline hexmask.long.byte 0x4 16.--19. 1. "RSVDP_16,Reserved for future use." newline hexmask.long.byte 0x4 8.--15. 1. "LOC_FIRST_UNCORR_ERROR,Location/ID of the first uncorrected error within the region defined by REG_FIRST_UNCORR_ERROR. You can cycle this field value from 0 to 255 to access all counters according to the detailed report of check points at.." newline hexmask.long.byte 0x4 4.--7. 1. "REG_FIRST_UNCORR_ERROR,Region of the first uncorrected error: - 0x0: Region select for Adm Rx path - 0x1: Region select for layer 3 Rx path - 0x2: Region select for layer 2 Rx path - 0x3: Region select for DMA inbound path - 0x4: Region select for AXI.." newline hexmask.long.byte 0x4 0.--3. 1. "RSVDP_0,Reserved for future use." group.long (0x28+0x480)++0x7 line.long 0x0 "RASDP_ERROR_MODE_EN_OFF,RASDP error mode enable. The controller enters RASDP error mode (if ERROR_MODE_EN =1) upon detection of the first uncorrectable error. During this mode: - Rx TLPs that are forwarded to your application are not guaranteed to be.." hexmask.long 0x0 2.--31. 1. "RSVDP_2,Reserved for future use." newline bitfld.long 0x0 1. "AUTO_LINK_DOWN_EN,Write '1' to enable the controller to bring the link down when the controller enters RASDP error mode. Note: This register field is sticky." "0,1" newline bitfld.long 0x0 0. "ERROR_MODE_EN,Write '1' to enable the controller enter RASDP error mode when it detects an uncorrectable error. Note: This register field is sticky." "0,1" line.long 0x4 "RASDP_ERROR_MODE_CLEAR_OFF,Exit RASDP error mode. For more details. see the RAS Data Protection (DP) section in the Core Operations chapter of the Databook." hexmask.long 0x4 1.--31. 1. "RSVDP_1,Reserved for future use." newline bitfld.long 0x4 0. "ERROR_MODE_CLEAR,Write '1' to take the controller out of RASDP error mode. The controller will then report uncorrectable errors (through AER internal error reporting) and also stop nullifying/discarding TLPs." "0,1" rgroup.long (0x30+0x480)++0x7 line.long 0x0 "RASDP_RAM_ADDR_CORR_ERROR_OFF,RAM Address where a corrected error (1-bit ECC) has been detected. For more details. see the RAS Data Protection (DP) section in the Core Operations chapter of the Databook." hexmask.long.byte 0x0 28.--31. 1. "RAM_INDEX_CORR_ERROR,RAM index where a corrected error (1-bit ECC) has been detected." newline bitfld.long 0x0 27. "RSVDP_27,Reserved for future use." "0,1" newline hexmask.long 0x0 0.--26. 1. "RAM_ADDR_CORR_ERROR,RAM Address where a corrected error (1-bit ECC) has been detected." line.long 0x4 "RASDP_RAM_ADDR_UNCORR_ERROR_OFF,RAM Address where an uncorrected error (2-bit ECC) has been detected. For more details. see the RAS Data Protection (DP) section in the Core Operations chapter of the Databook." hexmask.long.byte 0x4 28.--31. 1. "RAM_INDEX_UNCORR_ERROR,RAM index where an uncorrected error (2-bit ECC) has been detected." newline bitfld.long 0x4 27. "RSVDP_27,Reserved for future use." "0,1" newline hexmask.long 0x4 0.--26. 1. "RAM_ADDR_UNCORR_ERROR,RAM Address where an uncorrected error (2-bit ECC) has been detected." tree.end tree "PF0_RTR_CAP (PF RTR Capability Structure)" group.long (0x0+0x2F8)++0xB line.long 0x0 "RTR_EXT_CAP_HDR_OFF,Readiness Time Reporting PCI Express Extended Capability Header. For a description of this standard PCIe register. see the PCI Express Specification." hexmask.long.word 0x0 20.--31. 1. "RTR_NEXT_OFFSET,Next Capability Offset. For a description of this standard PCIe register field see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky).." hexmask.long.byte 0x0 16.--19. 1. "RTR_CAP_VERSION,Capability Version. For a description of this standard PCIe register field see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky).." hexmask.long.word 0x0 0.--15. 1. "RTR_EXT_CAP_ID,PCI Express Extended Capability ID. For a description of this standard PCIe register field see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then.." line.long 0x4 "READI_TIME_REPORTING1_OFF,Readiness Time Reporting 1. For a description of this standard PCIe register. see the PCI Express Specification." bitfld.long 0x4 31. "RTR_TIME_VALID,Valid. For a description of this standard PCIe register field see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky)" "0,1" hexmask.long.byte 0x4 24.--30. 1. "RSVDP_24,Reserved for future use." hexmask.long.word 0x4 12.--23. 1. "DL_UP_TIME,DL_UP Time. For a description of this standard PCIe register field see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky)" hexmask.long.word 0x4 0.--11. 1. "RESET_TIME,Reset Time. For a description of this standard PCIe register field see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky)" line.long 0x8 "READI_TIME_REPORTING2_OFF,Readiness Time Reporting 2. For a description of this standard PCIe register. see the PCI Express Specification." hexmask.long.byte 0x8 24.--31. 1. "RSVDP_24,Reserved for future use." hexmask.long.word 0x8 12.--23. 1. "D3HOT_D0_TIME,D3hot to D0 Time. For a description of this standard PCIe register field see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else.." hexmask.long.word 0x8 0.--11. 1. "FLR_TIME,FLR Time. For a description of this standard PCIe register field see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky)" tree.end tree "PF0_RTR_CAP_DBI2 (DBI2 Shadow Block: PF RTR Capability Structure)" rgroup.long (0x4+0x12F8)++0x7 line.long 0x0 "SHADOW_READI_TIME_REPORTING1_OFF,Shadow Register Readiness Time Reporting 1. For a description of this standard PCIe register. see the PCI Express Specification." bitfld.long 0x0 31. "RTR_TIME_VALID,Shadow Valid in the shadow register. For a description of this standard PCIe register field see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access - Dbi: No access - Dbi2: if.." "0,1" hexmask.long.tbyte 0x0 12.--30. 1. "RSVDP_12,Reserved for future use." hexmask.long.word 0x0 0.--11. 1. "RESET_TIME,Shadow Reset Time in the shadow register. For a description of this standard PCIe register field see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access - Dbi: No access - Dbi2: if.." line.long 0x4 "SHADOW_READI_TIME_REPORTING2_OFF,Shadow Register Readiness Time Reporting 2. For a description of this standard PCIe register. see the PCI Express Specification." hexmask.long.byte 0x4 24.--31. 1. "RSVDP_24,Reserved for future use." hexmask.long.word 0x4 12.--23. 1. "D3HOT_D0_TIME,Shadow D3hot to D0 Time in the shadow register. For a description of this standard PCIe register field see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access - Dbi: No access - Dbi2:.." hexmask.long.word 0x4 0.--11. 1. "FLR_TIME,Shadow FLR Time in the shadow register. For a description of this standard PCIe register field see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access - Dbi: No access - Dbi2: if.." tree.end tree "PF0_FRSQ_CAP (PF FRSQ Capability Structure)" group.long (0x0+0x2E8)++0xB line.long 0x0 "FRSQ_EXT_CAP_HDR_OFF,FRS Queuing Extended Capability Header. For a description of this standard PCIe register. see the PCI Express Specification." hexmask.long.word 0x0 20.--31. 1. "FRSQ_NEXT_OFFSET,Next Capability Offset. For a description of this standard PCIe register field see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then.." hexmask.long.byte 0x0 16.--19. 1. "FRSQ_CAP_VERSION,Capability Version. For a description of this standard PCIe register field see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky).." hexmask.long.word 0x0 0.--15. 1. "FRSQ_EXT_CAP_ID,PCI Express Extended Capability ID. For a description of this standard PCIe register field see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then.." line.long 0x4 "FRSQ_CAP_OFF,FRS Queuing Capability Register. For a description of this standard PCIe register. see the PCI Express Specification." hexmask.long.word 0x4 21.--31. 1. "RSVDP_21,Reserved for future use." hexmask.long.byte 0x4 16.--20. 1. "FRS_INT_MESSAGE_NUMBER,FRS Interrupt Message Number. For a description of this standard PCIe register field see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1).." hexmask.long.byte 0x4 12.--15. 1. "RSVDP_12,Reserved for future use." hexmask.long.word 0x4 0.--11. 1. "FRSQ_MAX_DEPTH,FRS Queue Max Depth. For a description of this standard PCIe register field see the PCI Express Specification." line.long 0x8 "FRSQ_CONTROL_FRSQ_STATUS_OFF,FRS Queuing Status and Control Register. For a description of this standard PCIe register. see the PCI Express Specification." hexmask.long.word 0x8 17.--31. 1. "RSVDP_17,Reserved for future use." bitfld.long 0x8 16. "FRS_INTERRUPT_ENABLE,FRS Interrupt Enable. For a description of this standard PCIe register field see the PCI Express Specification." "0,1" hexmask.long.word 0x8 2.--15. 1. "RSVDP_2,Reserved for future use." bitfld.long 0x8 1. "FRS_MESSAGE_OVERFLOW,FRS Message Overflow. For a description of this standard PCIe register field see the PCI Express Specification." "0,1" newline bitfld.long 0x8 0. "FRS_MESSAGE_RECEIVED,FRS Message Received. For a description of this standard PCIe register field see the PCI Express Specification." "0,1" rgroup.long (0xC+0x2E8)++0x3 line.long 0x0 "FRS_MESSAGE_QUEUE_OFF,FRS Message Queue Register. For a description of this standard PCIe register. see the PCI Express Specification." hexmask.long.word 0x0 20.--31. 1. "FRS_MESSAGE_QUE_DEPTH,FRS Message Queue Depth. For a description of this standard PCIe register field see the PCI Express Specification." hexmask.long.byte 0x0 16.--19. 1. "FRS_MESSAGE_QUE_REASON,FRS Message Queue Reason. For a description of this standard PCIe register field see the PCI Express Specification." hexmask.long.word 0x0 0.--15. 1. "FRS_MESSAGE_QUE_FUNC_ID,FRS Message Queue Function ID. For a description of this standard PCIe register field see the PCI Express Specification." tree.end tree "PF0_PTM_CAP (PF PTM Capability Structure)" group.long (0x0+0x40C)++0xB line.long 0x0 "PTM_EXT_CAP_HDR_OFF,Precision Time Measurement Capability Header. For a description of this standard PCIe register. see the PCI Express Specification." hexmask.long.word 0x0 20.--31. 1. "PTM_NEXT_OFFSET,Precision Time Measurement PCI Express Extended Capability Next Offset. For a description of this standard PCIe register see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access. -.." hexmask.long.byte 0x0 16.--19. 1. "PTM_CAP_VERSION,Precision Time Measurement PCI Express Extended Capability Version. For a description of this standard PCIe register see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi:.." hexmask.long.word 0x0 0.--15. 1. "PTM_CAP_ID,Precision Time Measurement PCI Express Extended Capability ID. For a description of this standard PCIe register see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if.." line.long 0x4 "PTM_CAP_OFF,PTM Capability Register. For a description of this standard PCIe register. see the PCI Express Specification." hexmask.long.word 0x4 16.--31. 1. "RSVDP_16,Reserved for future use." hexmask.long.byte 0x4 8.--15. 1. "PTM_CLK_GRAN,PTM Local Clock Granularity. For a description of this standard PCIe register see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky).." hexmask.long.byte 0x4 3.--7. 1. "RSVDP_3,Reserved for future use." bitfld.long 0x4 2. "PTM_ROOT_CAPABLE,PTM Root Capable. For a description of this standard PCIe register see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else.." "0,1" bitfld.long 0x4 1. "PTM_RES_CAPABLE,PTM Responder Capable. For a description of this standard PCIe register see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else.." "0,1" newline bitfld.long 0x4 0. "PTM_REQ_CAPABLE,PTM Requester Capable. For a description of this standard PCIe register see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else.." "0,1" line.long 0x8 "PTM_CONTROL_OFF,PTM Control Register. For a description of this standard PCIe register. see the PCI Express Specification." hexmask.long.word 0x8 16.--31. 1. "RSVDP_16,Reserved for future use." hexmask.long.byte 0x8 8.--15. 1. "EFF_GRAN,PTM Effective Granularity. For a description of this standard PCIe register see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: HWINIT" hexmask.long.byte 0x8 2.--7. 1. "RSVDP_2,Reserved for future use." rbitfld.long 0x8 1. "ROOT_SELECT,PTM Root Select. When set this Time Source is the PTM Root. For a description of this standard PCIe register see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: HWINIT" "0,1" bitfld.long 0x8 0. "PTM_ENABLE,PTM Enable. When set this function is permitted to participate in the PTM mechanism. For a description of this standard PCIe register see the PCI Express Specification." "0,1" tree.end tree "PF0_PTM_RES_CAP (PF PTM Responder Capability Structure (VSEC))" group.long (0x0+0x418)++0xB line.long 0x0 "PTM_RES_CAP_HDR_OFF,Precision Time Measurement Responder Capability Header (VSEC). For more details. see the PTM section in the Databook." hexmask.long.word 0x0 20.--31. 1. "PTM_RES_EXT_CAP_NEXT_OFFS,Precision Time Measurement Responder VSEC Next Pointer. For more details see the PTM section in the Databook. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then.." hexmask.long.byte 0x0 16.--19. 1. "PTM_RES_EXT_CAP_VER,Precision Time Measurement Responder VSEC Version. For more details see the PTM section in the Databook. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else.." hexmask.long.word 0x0 0.--15. 1. "PTM_RES_EXT_CAP_ID,Precision Time Measurement Responder VSEC ID. For more details see the PTM section in the Databook. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else.." line.long 0x4 "PTM_RES_HDR_OFF,Precision Time Measurement Responder Vendor Specific Header. For more details. see the PTM section in the Databook." hexmask.long.word 0x4 20.--31. 1. "PTM_RES_VSEC_LENGTH,PTM Responder VSEC Length. For more details see the PTM section in the Databook. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This.." hexmask.long.byte 0x4 16.--19. 1. "PTM_RES_VSEC_REV,PTM Responder VSEC Revision. For more details see the PTM section in the Databook. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This.." hexmask.long.word 0x4 0.--15. 1. "PTM_RES_VSEC_ID,PTM Responder VSEC ID. For more details see the PTM section in the Databook. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register.." line.long 0x8 "PTM_RES_CONTROL_OFF,PTM Responder Control Register. For more details. see the PTM section in the Databook." hexmask.long 0x8 2.--31. 1. "RSVDP_2,Reserved for future use." bitfld.long 0x8 1. "PTM_RES_PDEL_BYTE_REV,PTM Requester Propagation Delay Byte Reversal - Reverse the order of bytes in the PTM Propagation Delay data word of the PTM ResponseD Message for compatibility with previous revisions. For more details see the PTM section in the.." "0,1" bitfld.long 0x8 0. "PTM_RES_CCONTEXT_VALID,PTM Responder Control Context Valid - PTM Local Timing is valid. This bit is set over the DBI. A speed change or aux_clk_active will set this bit low. For more details see the PTM section in the Databook. Note: The access.." "0,1" rgroup.long (0xC+0x418)++0x3 line.long 0x0 "PTM_RES_STATUS_OFF,PTM Responder Status Register. For more details. see the PTM section in the Databook." hexmask.long 0x0 2.--31. 1. "RSVDP_2,Reserved for future use." bitfld.long 0x0 1. "PTM_RES_REQUEST_RECEIVED,PTM 1st Request Received - PTM Responder has received the first PTM Request Message. Upon receipt of a second PTM Request Message a ResponseD message with timing information will be sent from the Responder if the context is.." "0,1" bitfld.long 0x0 0. "PTM_RES_CONTEXT_VALID,PTM Responder Status Context Valid - PTM Local Timing Context is Valid. Value set from upstream port Requester in a Switch. Shadows the same in the control register in all other products. For more details see the PTM section in the.." "0,1" group.long (0x10+0x418)++0x7 line.long 0x0 "PTM_RES_LOCAL_LSB_OFF,PTM Responder Local Clock LSB. For more details. see the PTM section in the Databook." hexmask.long 0x0 0.--31. 1. "PTM_RES_LOCAL_LSB,PTM Responder Local Clock LSB - Lower 32 bits of local timer value. For more details see the PTM section in the Databook. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then.." line.long 0x4 "PTM_RES_LOCAL_MSB_OFF,PTM Responder Local Clock MSB. For more details. see the PTM section in the Databook." hexmask.long 0x4 0.--31. 1. "PTM_RES_LOCAL_MSB,PTM Responder Local Clock MSB - Upper 32 bits of local timer value. For more details see the PTM section in the Databook. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then.." rgroup.long (0x18+0x418)++0x1F line.long 0x0 "PTM_RES_T2_LSB_OFF,PTM Responder T2 Timestamp LSB. For more details. see the PTM section in the Databook." hexmask.long 0x0 0.--31. 1. "PTM_RES_T2_LSB,PTM Responder T2 Timestamp LSB - Lower 32 bits of the T2 Timestamp value. For more details see the PTM section in the Databook. Note: This register field is sticky." line.long 0x4 "PTM_RES_T2_MSB_OFF,PTM Responder T2 Timestamp MSB. For more details. see the PTM section in the Databook." hexmask.long 0x4 0.--31. 1. "PTM_RES_T2_MSB,PTM Responder T2 Timestamp MSB - Upper 32 bits of the T2 Timestamp value. For more details see the PTM section in the Databook. Note: This register field is sticky." line.long 0x8 "PTM_RES_T2P_LSB_OFF,PTM Responder T2 Previous Timestamp LSB. For more details. see the PTM section in the Databook." hexmask.long 0x8 0.--31. 1. "PTM_RES_T2P_LSB,PTM Responder T2 Previous Timestamp LSB - Lower 32 bits of the previously stored T2 Timestamp value. For more details see the PTM section in the Databook. Note: This register field is sticky." line.long 0xC "PTM_RES_T2P_MSB_OFF,PTM Responder T2 Previous Timestamp MSB. For more details. see the PTM section in the Databook." hexmask.long 0xC 0.--31. 1. "PTM_RES_T2P_MSB,PTM Responder T2 Previous Timestamp MSB - Upper 32 bits of the previously stored T2 Timestamp value. For more details see the PTM section in the Databook. Note: This register field is sticky." line.long 0x10 "PTM_RES_T3_LSB_OFF,PTM Responder T3 Timestamp LSB. For more details. see the PTM section in the Databook." hexmask.long 0x10 0.--31. 1. "PTM_RES_T3_LSB,PTM Responder T3 Timestamp LSB - Lower 32 bits of the T3 Timestamp value. For more details see the PTM section in the Databook. Note: This register field is sticky." line.long 0x14 "PTM_RES_T3_MSB_OFF,PTM Responder T3 Timestamp MSB. For more details. see the PTM section in the Databook." hexmask.long 0x14 0.--31. 1. "PTM_RES_T3_MSB,PTM Responder T3 Timestamp MSB - Upper 32 bits of the T2 Timestamp value. For more details see the PTM section in the Databook. Note: This register field is sticky." line.long 0x18 "PTM_RES_T3P_LSB_OFF,PTM Responder T3 Previous Timestamp LSB. For more details. see the PTM section in the Databook." hexmask.long 0x18 0.--31. 1. "PTM_RES_T3P_LSB,PTM Responder T3 Previous Timestamp LSB - Lower 32 bits of the previously stored T3 Timestamp value. For more details see the PTM section in the Databook. Note: This register field is sticky." line.long 0x1C "PTM_RES_T3P_MSB_OFF,PTM Responder T3 Previous Timestamp MSB. For more details. see the PTM section in the Databook." hexmask.long 0x1C 0.--31. 1. "PTM_RES_T3P_MSB,PTM Responder T3 Previous Timestamp MSB - Upper 32 bits of the previously stored T3 Timestamp value. For more details see the PTM section in the Databook. Note: This register field is sticky." group.long (0x38+0x418)++0x7 line.long 0x0 "PTM_RES_TX_LATENCY_OFF,PTM Responder TX Latency. For more details. see the PTM section in the Databook." hexmask.long.tbyte 0x0 12.--31. 1. "RSVDP_12,Reserved for future use." hexmask.long.word 0x0 0.--11. 1. "PTM_RES_TX_LATENCY,PTM Responder TX Latency - Responder Transmit path latency (12 bit wide). For more details see the PTM section in the Databook. Note: This register field is sticky." line.long 0x4 "PTM_RES_RX_LATENCY_OFF,PTM Responder RX Latency. For more details. see the PTM section in the Databook." hexmask.long.tbyte 0x4 12.--31. 1. "RSVDP_12,Reserved for future use." hexmask.long.word 0x4 0.--11. 1. "PTM_RES_RX_LATENCY,PTM Responder RX Latency - Responder Receive path latency (12 bit wide). For more details see the PTM section in the Databook. Note: This register field is sticky." rgroup.long (0x40+0x418)++0x3 line.long 0x0 "PTM_RES_NOM_CLOCK_T_OFF,PTM Responder Nominal Clock Period. For more details. see the PTM section in the Databook." hexmask.long.byte 0x0 24.--31. 1. "RSVDP_24,Reserved for future use." hexmask.long.byte 0x0 16.--23. 1. "PTM_RES_NOM_CLOCK_T_INT,PTM Responder Nominal Clock Period Integral - Integral part of the nominal PTM local clock period in nanoseconds. For more details see the PTM section in the Databook. Note: This register field is sticky." hexmask.long.word 0x0 0.--15. 1. "PTM_RES_NOM_CLOCK_T_FRAC,PTM Responder Nominal Clock Period Fractional - Fractional part of the nominal PTM local clock period. LSB is 1/(2^16) nanoseconds. For more details see the PTM section in the Databook. Note: This register field is sticky." group.long (0x44+0x418)++0x3 line.long 0x0 "PTM_RES_SCALED_CLOCK_T_OFF,PTM Responder Scaled Clock Period. For more details. see the PTM section in the Databook." bitfld.long 0x0 31. "PTM_RES_SCALED_CLOCK_T_EN,PTM Responder Scaled Clock Period Enable - Use the programmed scaled PTM clock period rather than the nominal values. This bit is cleared when the core_clk rate starts to change and can only be set when the clock period change.." "0,1" hexmask.long.byte 0x0 24.--30. 1. "RSVDP_24,Reserved for future use." hexmask.long.byte 0x0 16.--23. 1. "PTM_RES_SCALED_CLOCK_T_INT,PTM Responder Scaled Clock Period Integral - Integral part of the nominal PTM local clock period in nanoseconds. For more details see the PTM section in the Databook. Note: This register field is sticky." newline hexmask.long.word 0x0 0.--15. 1. "PTM_RES_SCALED_CLOCK_T_FRAC,PTM Responder Scaled Clock Period Fractional - Fractional part of the nominal PTM local clock period. LSB is 1/(2^16) nanoseconds. For more details see the PTM section in the Databook. Note: This register field is sticky." tree.end tree "PF0_PM_CAP (PF PCI Power Management Capability Structure)" group.long (0x0+0x40)++0x7 line.long 0x0 "CAP_ID_NXT_PTR_REG,Power Management Capabilities Register." hexmask.long.byte 0x0 27.--31. 1. "PME_SUPPORT,PME_Support. This 5-bit field indicates the power states in which the function may generate a PME and/or forward PME messages. A value of 0b for any bit indicates that the function is not capable of asserting PME while in that power state. -.." bitfld.long 0x0 26. "D2_SUPPORT,D2_Support. If this bit is set this function supports the D2 Power Management state. Functions that do not support D2 must always return a value of 0b for this bit. Note: The access attributes of this field are as follows: - Wire: No access." "0,1" bitfld.long 0x0 25. "D1_SUPPORT,D1_Support. If this bit is set this function supports the D1 Power Management state. Functions that do not support D1 must always return a value of 0b for this bit. Note: The access attributes of this field are as follows: - Wire: No access." "0,1" bitfld.long 0x0 22.--24. "AUX_CURR,Aux_Current. This 3 bit field reports the Vaux auxiliary current requirements for the function. If this function implements the Data Register the controller hardwires this field to 000b. If PME_Support is 0 xxxxb (PME assertion from D3cold is.." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 21. "DSI,Device Specific Initialization. The DSI bit indicates whether special initialization of this function is required. When set indicates that the function requires a device specific initialization sequence following a transition to the D0uninitialized.." "0,1" bitfld.long 0x0 20. "PME_IMM_READI_RETURN_DO,Immediate_Readiness_on_Return_to_D0. - If this bit is a '1' this function is guaranteed to be ready to successfully complete valid accesses immediately after being set to D0. These accesses include configuration cycles and if.." "0,1" rbitfld.long 0x0 19. "PME_CLK,PME Clock. Does not apply to PCI Express the controller hardwires it to 0b. Note: This register field is sticky." "0,1" bitfld.long 0x0 16.--18. "PM_SPEC_VER,Version. This field provides the Power Management specification version. The controller hardwires this field to 011b for functions compliant to PCI Express Base Specification Revision 4.0 Version 1.0>. Note: The access attributes of this.." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x0 8.--15. 1. "PM_NEXT_POINTER,Next Capability Pointer. This field provides an offset into the function's configuration space pointing to the location of next item in the capabilities list. If there are no additional items in the capabilities list this field is set to.." hexmask.long.byte 0x0 0.--7. 1. "PM_CAP_ID,Capability ID. This field returns 01h to indicate that this is the PCI Power Management Capability. Each function may have only one item in its capability list with Capability ID set to 01h." line.long 0x4 "CON_STATUS_REG,Power Management Control and Status Register. This register is used to manage the PCI function's power management state as well as to enable/monitor PMEs." hexmask.long.byte 0x4 24.--31. 1. "DATA_REG_ADD_INFO,Data. This field is used to report the state dependent data requested by the Data_Select field. The value of this field is scaled by the value reported by the Data_Scale field." rbitfld.long 0x4 23. "BUS_PWR_CLK_CON_EN,Bus Power/Clock Control Enable. For a description of this standard PCIe register field see the PCI Express Base Specification." "0,1" rbitfld.long 0x4 22. "B2_B3_SUPPORT,B2B3 Support for D3hot. For a description of this standard PCIe register field see the PCI Express Base Specification." "0,1" hexmask.long.byte 0x4 16.--21. 1. "RSVDP_16,Reserved for future use." newline bitfld.long 0x4 15. "PME_STATUS,PME_Status. This bit is set when the function normally generates a PME signal. The value of this bit is not affected by the value of the PME_En bit. If PME_Support bit 31 of the Power Management Capabilities register is clear this bit is.." "0,1" rbitfld.long 0x4 13.--14. "DATA_SCALE,Data_Scale. This field indicates the scaling factor to be used when interpreting the value of the Data field. The value and meaning of this field varies depending on which data value has been selected by the Data_Select field. For more details.." "0,1,2,3" hexmask.long.byte 0x4 9.--12. 1. "DATA_SELECT,Data_Select. This 4-bit field is used to select which data is to be reported through the Data and Data_Scale field. If the Data field is not implemented this field must be hardwired to 0000b." bitfld.long 0x4 8. "PME_ENABLE,PME_En. - When set the function is permitted to generate a PME. - When clear the function is not permitted to generate a PME. If PME_Support is 1 xxxxb (PME generation from D3cold) or the function consumes Aux power and Aux power is.." "0,1" newline hexmask.long.byte 0x4 4.--7. 1. "RSVDP_4,Reserved for future use." bitfld.long 0x4 3. "NO_SOFT_RST,No_Soft_Reset. This bit indicates the state of the function after writing the PowerState field to transition the function from D3hot to D0. - When set this transition preserves internal function state. The function is in D0Active and no.." "0,1" rbitfld.long 0x4 2. "RSVDP_2,Reserved for future use." "0,1" bitfld.long 0x4 0.--1. "POWER_STATE,PowerState. This 2-bit field is used both to determine the current power state of a function and to set the function into a new power state. The definition of the field values is given below. You can write to this register; however the.." "D0,D1,D2,D3hot" tree.end tree "PF0_PCIE_CAP (PF PCI Express Capability Structure)" group.long (0x0+0x70)++0x33 line.long 0x0 "PCIE_CAP_ID_PCIE_NEXT_CAP_PTR_PCIE_CAP_REG,PCI Express Capabilities. ID. Next Pointer Register." rbitfld.long 0x0 31. "RSVDP_31,Reserved for future use." "0,1" rbitfld.long 0x0 30. "RSVD,Reserved." "0,1" newline hexmask.long.byte 0x0 25.--29. 1. "PCIE_INT_MSG_NUM,PCIE Interrupt Message Number. For a description of this standard PCIe register field see the PCI Express Base Specification. Interrupt Message Number. This field indicates which MSI/MSI-X vector is used for the interrupt message.." bitfld.long 0x0 24. "PCIE_SLOT_IMP,Slot Implemented. When set this bit indicates that the Link associated with this Port is connected to a slot (as compared to being connected to a system-integrated device or being disabled). This bit is valid for Downstream Ports. This bit.." "0,1" newline hexmask.long.byte 0x0 20.--23. 1. "PCIE_DEV_PORT_TYPE,Device/Port Type. Indicates the specific type of this PCI Express function. Note: Different functions in a Multi-Function Device can generally be of different types. Defined encodings for functions that implement a Type 00h PCI.." hexmask.long.byte 0x0 16.--19. 1. "PCIE_CAP_REG,Capability Version. Indicates PCI-SIG defined PCI Express Capability structure version number. A version of the specification that changes the PCI Express Capability structure in a way that is not otherwise identifiable (for example through.." newline hexmask.long.byte 0x0 8.--15. 1. "PCIE_CAP_NEXT_PTR,Next Capability Pointer. This field contains the offset to the next PCI Capability structure or 00h if no other items exist in the linked list of Capabilities. Note: The access attributes of this field are as follows: - Wire: No access." hexmask.long.byte 0x0 0.--7. 1. "PCIE_CAP_ID,Capability ID. Indicates the PCI Express Capability structure. This field must return a Capability ID of 10h indicating that this is a PCI Express Capability structure." line.long 0x4 "DEVICE_CAPABILITIES_REG,Device Capabilities Register. The Device Capabilities register identifies PCI Express device function specific capabilities." hexmask.long.word 0x4 16.--31. 1. "RSVDP_16,Reserved for future use." bitfld.long 0x4 15. "PCIE_CAP_ROLE_BASED_ERR_REPORT,Role-Based Error Reporting. When set this bit indicates that the function implements the functionality originally defined in the Error Reporting ECN for PCI Express Base Specification Revision 1.0a and later incorporated.." "0,1" newline hexmask.long.word 0x4 6.--14. 1. "RSVDP_6,Reserved for future use." bitfld.long 0x4 5. "PCIE_CAP_EXT_TAG_SUPP,Extended Tag Field Supported. This bit in combination with the 10-Bit Tag Requester Supported bit in the Device Capabilities 2 register indicates the maximum supported size of the Tag field as a Requester. This bit must be set if.." "0,1" newline bitfld.long 0x4 3.--4. "PCIE_CAP_PHANTOM_FUNC_SUPPORT,Phantom Functions Supported. This field indicates the support for use of unclaimed function numbers to extend the number of outstanding transactions allowed by logically combining unclaimed function numbers (called Phantom.." "0,1,2,3" bitfld.long 0x4 0.--2. "PCIE_CAP_MAX_PAYLOAD_SIZE,Max_Payload_Size Supported. This field indicates the maximum payload size that the function can support for TLPs. Defined encodings are: - 000b: 128 bytes max payload size - 001b: 256 bytes max payload size - 010b: 512 bytes max.." "0,1,2,3,4,5,6,7" line.long 0x8 "DEVICE_CONTROL_DEVICE_STATUS,Device Control and Device Status Register. This register controls PCI Express device specific parameters and provides information about PCI Express device (function) specific parameters." hexmask.long.word 0x8 22.--31. 1. "RSVDP_22,Reserved for future use." rbitfld.long 0x8 21. "PCIE_CAP_TRANS_PENDING,Transactions Pending. Endpoints: When set this bit indicates that the function has issued Non-Posted Requests that have not been completed. A Function reports this bit cleared only when all outstanding Non-Posted Requests have.." "0,1" newline rbitfld.long 0x8 20. "PCIE_CAP_AUX_POWER_DETECTED,AUX Power Detected. Functions that require Aux power report this bit as set if Aux power is detected by the function. This bit is derived by sampling the sys_aux_pwr_det input." "0,1" bitfld.long 0x8 19. "PCIE_CAP_UNSUPPORTED_REQ_DETECTED,Unsupported Request Detected. This bit indicates that the function received an Unsupported Request. Errors are logged in this register regardless of whether error reporting is enabled or not in the Device Control.." "0,1" newline bitfld.long 0x8 18. "PCIE_CAP_FATAL_ERR_DETECTED,Fatal Error Detected. This bit indicates status of Fatal errors detected. Errors are logged in this register regardless of whether error reporting is enabled or not in the Device Control register. For a Multi-Function device.." "0,1" bitfld.long 0x8 17. "PCIE_CAP_NON_FATAL_ERR_DETECTED,Non-Fatal Error Detected. This bit indicates status of Non-fatal errors detected. Errors are logged in this register regardless of whether error reporting is enabled or not in the Device Control register. For a.." "0,1" newline bitfld.long 0x8 16. "PCIE_CAP_CORR_ERR_DETECTED,Correctable Error Detected. This bit indicates status of correctable errors detected. Errors are logged in this register regardless of whether error reporting is enabled or not in the Device Control register. For a.." "0,1" bitfld.long 0x8 15. "PCIE_CAP_INITIATE_FLR,Initiate Function Level Reset (applicable to Endpoints with Function Level Reset Capability set to 1b). A write of 1b initiates Function Level Reset to the Function. The value read by software from this bit is always 0b." "0,1" newline bitfld.long 0x8 12.--14. "PCIE_CAP_MAX_READ_REQ_SIZE,Max_Read_Request_Size. This field sets the maximum Read Request size for the function as a Requester. The function must not generate Read Requests with a size exceeding the set value. Defined encodings for this field are: -.." "0,1,2,3,4,5,6,7" rbitfld.long 0x8 11. "PCIE_CAP_EN_NO_SNOOP,Enable No Snoop. If this bit is set the function is permitted to Set the No Snoop bit in the Requester Attributes of transactions it initiates that do not require hardware enforced cache coherency (see section 2.2.6.5 in PCI Express.." "0,1" newline bitfld.long 0x8 10. "PCIE_CAP_AUX_POWER_PM_EN,Aux Power PM Enable. This bit is derived by sampling the sys_aux_pwr_det input. When set this bit enables a function to draw Aux power independent of PME Aux power. Functions that require Aux power on legacy operating systems.." "0,1" rbitfld.long 0x8 9. "PCIE_CAP_PHANTOM_FUNC_EN,Phantom Functions Enable. This bit in combination with the 10-Bit Tag Requester Enable bit in the Device Control 2 register determines how many Tag field bits a Requester is permitted to use. When the 10-Bit Tag Requester.." "0,1" newline rbitfld.long 0x8 8. "PCIE_CAP_EXT_TAG_EN,Extended Tag Field Enable. This bit in combination with the 10-Bit Tag Requester Enable bit in the Device Control 2 register determines how many Tag field bits a Requester is permitted to use. When the 10-Bit Tag Requester Enable.." "0,1" bitfld.long 0x8 5.--7. "PCIE_CAP_MAX_PAYLOAD_SIZE_CS,Max_Payload_Size. This field sets maximum TLP payload size for the Function. As a Receiver the Function must handle TLPs as large as the set value. As a Transmitter the Function must not generate TLPs exceeding the set.." "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 4. "PCIE_CAP_EN_REL_ORDER,Enable Relaxed Ordering. If this bit is set the function is permitted to set the Relaxed Ordering bit in the Attributes field of transactions it initiates that do not require strong write ordering (for more details see section.." "0,1" bitfld.long 0x8 3. "PCIE_CAP_UNSUPPORT_REQ_REP_EN,Unsupported Request Reporting Enable. This bit in conjunction with other bits controls the signaling of Unsupported Request Errors by sending error Messages (for more details see section 6.2.5 and section 6.2.6 of PCI.." "0,1" newline bitfld.long 0x8 2. "PCIE_CAP_FATAL_ERR_REPORT_EN,Fatal Error Reporting Enable. This bit in conjunction with other bits controls sending ERR_FATAL Messages (for more details see section 6.2.5 and section 6.2.6 of of PCI Express Base Specification). For a Multi-Function.." "0,1" bitfld.long 0x8 1. "PCIE_CAP_NON_FATAL_ERR_REPORT_EN,Non-Fatal Error Reporting Enable. This bit in conjunction with other bits controls sending ERR_NONFATAL Messages (for more details see section 6.2.5 and Section 6.2.6 of PCI Express Base Specification). For a.." "0,1" newline bitfld.long 0x8 0. "PCIE_CAP_CORR_ERR_REPORT_EN,Correctable Error Reporting Enable. This bit in conjunction with other bits controls sending ERR_COR Messages (for more details see section 6.2.5 section 6.2.6 and section 6.2.10.2 of PCI Express Base Specification). For.." "0,1" line.long 0xC "LINK_CAPABILITIES_REG,Link Capabilities Register. The Link Capabilities register identifies PCI Express Link specific capabilities." hexmask.long.byte 0xC 24.--31. 1. "PCIE_CAP_PORT_NUM,Port Number. This field indicates the PCI Express Port number for the given PCI Express Link. Multi-Function Devices associated with an Upstream Port must report the same value in this field for all functions. Note: The access.." rbitfld.long 0xC 23. "RSVDP_23,Reserved for future use." "0,1" newline bitfld.long 0xC 22. "PCIE_CAP_ASPM_OPT_COMPLIANCE,ASPM Optionality Compliance. This bit must be set to 1b in all functions. Components implemented against certain earlier versions of this specification will have this bit set to 0b. Software is permitted to use the value of.." "0,1" bitfld.long 0xC 21. "PCIE_CAP_LINK_BW_NOT_CAP,Link Bandwidth Notification Capability. A value of 1b indicates support for the Link Bandwidth Notification status and interrupt mechanisms. This capability is required for all Root Ports and Switch Downstream Ports supporting.." "0,1" newline rbitfld.long 0xC 20. "PCIE_CAP_DLL_ACTIVE_REP_CAP,Data Link Layer Link Active Reporting Capable. For a Downstream Port the controller hardwires this bit to 1b if the component supports the optional capability of reporting the DL_Active state of the Data Link Control and.." "0,1" bitfld.long 0xC 19. "PCIE_CAP_SURPRISE_DOWN_ERR_REP_CAP,Surprise Down Error Reporting Capable. For a Downstream Port this bit must be set if the component supports the optional capability of detecting and reporting a Surprise Down error condition. For Upstream Ports and.." "0,1" newline rbitfld.long 0xC 18. "PCIE_CAP_CLOCK_POWER_MAN,Clock Power Management. For Upstream Ports a value of 1b in this bit indicates that the component tolerates the removal of any reference clock(s) via the 'clock request' (CLKREQ#) mechanism when the Link is in the L1 and L2/L3.." "0,1" bitfld.long 0xC 15.--17. "PCIE_CAP_L1_EXIT_LATENCY,L1 Exit Latency. This field indicates the L1 exit latency for the given PCI Express Link. The value reported indicates the length of time this Port requires to complete transition from ASPM L1 to L0. If ASPM L1 is not supported.." "0,1,2,3,4,5,6,7" newline bitfld.long 0xC 12.--14. "PCIE_CAP_L0S_EXIT_LATENCY,L0s Exit Latency. This field indicates the L0s exit latency for the given PCI Express Link. The value reported indicates the length of time this Port requires to complete transition from L0s to L0. If L0s is not supported the.." "0,1,2,3,4,5,6,7" bitfld.long 0xC 10.--11. "PCIE_CAP_ACTIVE_STATE_LINK_PM_SUPPORT,Active State Power Management (ASPM) Support. This field indicates the level of ASPM supported on the given PCI Express Link. For more details on ASPM support requirements see section 5.4.1 of PCI Express Base.." "0,1,2,3" newline hexmask.long.byte 0xC 4.--9. 1. "PCIE_CAP_MAX_LINK_WIDTH,Maximum Link Width. This field indicates the maximum Link width (xN - corresponding to N Lanes) implemented by the component. This value is permitted to exceed the number of Lanes routed to the slot (Downstream Port) adapter.." hexmask.long.byte 0xC 0.--3. 1. "PCIE_CAP_MAX_LINK_SPEED,Max Link Speed. This field indicates the maximum Link speed of the associated Port. The encoded value specifies a bit location in the Supported Link Speeds Vector (in the Link Capabilities 2 register) that corresponds to the.." line.long 0x10 "LINK_CONTROL_LINK_STATUS_REG,Link Control and Link Status Register. This register controls and provides information about PCI Express Link specific parameters." bitfld.long 0x10 31. "PCIE_CAP_LINK_AUTO_BW_STATUS,Link Autonomous Bandwidth Status. This bit is set by hardware to indicate that hardware has autonomously changed Link speed or width without the Port transitioning through DL_Down status for reasons other than to attempt to.." "0,1" bitfld.long 0x10 30. "PCIE_CAP_LINK_BW_MAN_STATUS,Link Bandwidth Management Status. This bit is set by hardware to indicate that either of the following has occurred without the Port transitioning through DL_Down status: - A Link retraining has completed following a write of.." "0,1" newline rbitfld.long 0x10 29. "PCIE_CAP_DLL_ACTIVE,Data Link Layer Link Active. This bit indicates the status of the Data Link Control and Management State Machine. It returns a 1b to indicate the DL_Active state 0b otherwise. This bit must be implemented if the Data Link Layer Link.." "0,1" bitfld.long 0x10 28. "PCIE_CAP_SLOT_CLK_CONFIG,Slot Clock Configuration. This bit indicates that the component uses the same physical reference clock that the platform provides on the connector. If the device uses an independent clock irrespective of the presence of a.." "0,1" newline rbitfld.long 0x10 27. "PCIE_CAP_LINK_TRAINING,Link Training. This read-only bit indicates that the Physical Layer LTSSM is in the Configuration or Recovery state or that 1b was written to the Retrain Link bit but Link training has not yet begun. Hardware clears this bit when.." "0,1" rbitfld.long 0x10 26. "RSVDP_26,Reserved for future use." "0,1" newline hexmask.long.byte 0x10 20.--25. 1. "PCIE_CAP_NEGO_LINK_WIDTH,Negotiated Link Width. This field indicates the negotiated width of the given PCI Express Link. Defined encodings are: -00 0001b: x1 -00 0010b: x2 -00 0100b: x4 -00 1000b: x8 -00 1100b: x12 -01 0000b: x16 -10 0000b: x32 All other.." hexmask.long.byte 0x10 16.--19. 1. "PCIE_CAP_LINK_SPEED,Current Link Speed. This field indicates the negotiated Link speed of the given PCI Express Link. The encoded value specifies a bit location in the Supported Link Speeds Vector (in the Link Capabilities 2 register) that corresponds to.." newline bitfld.long 0x10 14.--15. "PCIE_CAP_DRS_SIGNALING_CONTROL,DRS Signaling Control. Indicates the mechanism used to report reception of a DRS message. Must be implemented for Downstream Ports with the DRS Supported bit Set in the Link Capabilities 2 Register. Encodings are: - 00b:.." "0,1,2,3" rbitfld.long 0x10 12.--13. "RSVDP_12,Reserved for future use." "0,1,2,3" newline bitfld.long 0x10 11. "PCIE_CAP_LINK_AUTO_BW_INT_EN,Link Autonomous Bandwidth Management Interrupt Enable. When set this bit enables the generation of an interrupt to indicate that the Link Autonomous Bandwidth Status bit has been set. The write value is gated with the.." "0,1" bitfld.long 0x10 10. "PCIE_CAP_LINK_BW_MAN_INT_EN,Link Bandwidth Management Interrupt Enable. When set this bit enables the generation of an interrupt to indicate that the Link Bandwidth Management Status bit has been set. The write value is gated with the.." "0,1" newline bitfld.long 0x10 9. "PCIE_CAP_HW_AUTO_WIDTH_DISABLE,Hardware Autonomous Width Disable. When set this bit disables hardware from changing the Link width for reasons other than attempting to correct unreliable Link operation by reducing Link width. For a Multi-Function Device.." "0,1" bitfld.long 0x10 8. "PCIE_CAP_EN_CLK_POWER_MAN,Enable Clock Power Management. Applicable only for Upstream Ports and with form factors that support a 'Clock Request' (CLKREQ#) mechanism this bit operates as follows: - 0b: Clock power management is disabled and device must.." "0,1" newline bitfld.long 0x10 7. "PCIE_CAP_EXTENDED_SYNCH,Extended Synch. When set this bit forces the transmission of additional Ordered Sets when exiting the L0s state (see section 4.2.4.5 of PCI Express Base Specification) and when in the Recovery state (see section 4.2.6.4.1 of PCI.." "0,1" bitfld.long 0x10 6. "PCIE_CAP_COMMON_CLK_CONFIG,Common Clock Configuration. When set this bit indicates that this component and the component at the opposite end of this Link are operating with a distributed common reference clock. A value of 0b indicates that this.." "0,1" newline bitfld.long 0x10 5. "PCIE_CAP_RETRAIN_LINK,Retrain Link. A write of 1b to this bit initiates Link retraining by directing the Physical Layer LTSSM to the Recovery state. If the LTSSM is already in Recovery or Configuration re-entering Recovery is permitted but not required." "0,1" bitfld.long 0x10 4. "PCIE_CAP_LINK_DISABLE,Link Disable. This bit disables the Link by directing the LTSSM to the Disabled state when set; this bit is Reserved on Endpoints PCI Express to PCI/PCI-X bridges and Upstream Ports of Switches. Writes to this bit are immediately.." "0,1" newline bitfld.long 0x10 3. "PCIE_CAP_RCB,Read Completion Boundary (RCB). Root Ports: Indicates the RCB value for the Root Port. Refer to section 2.3.1.1 of PCI Express Base Specification for the definition of the parameter RCB. Defined encodings are: - 0b: 64 byte - 1b: 128 byte.." "0,1" rbitfld.long 0x10 2. "RSVDP_2,Reserved for future use." "0,1" newline bitfld.long 0x10 0.--1. "PCIE_CAP_ACTIVE_STATE_LINK_PM_CONTROL,Active State Power Management (ASPM) Control. This field controls the level of ASPM enabled on the given PCI Express Link. See section 5.4.1.3 of PCI Express Base Specification for requirements on when and how to.." "0,1,2,3" line.long 0x14 "SLOT_CAPABILITIES_REG,Slot Capabilities Register. The Slot Capabilities register identifies PCI Express slot specific capabilities." hexmask.long.word 0x14 19.--31. 1. "PCIE_CAP_PHY_SLOT_NUM,Physical Slot Number. This field indicates the physical slot number attached to this Port. This field must be hardware initialized to a value that assigns a slot number that is unique within the chassis regardless of the form.." bitfld.long 0x14 18. "PCIE_CAP_NO_CMD_CPL_SUPPORT,No Command Completed Support. When set this bit indicates that this slot does not generate software notification when an issued command is completed by the Hot-Plug Controller. This bit is only permitted to be set if the.." "0,1" newline bitfld.long 0x14 17. "PCIE_CAP_ELECTROMECH_INTERLOCK,Electromechanical Interlock Present. When set this bit indicates that an Electromechanical Interlock is implemented on the chassis for this slot. Note: The access attributes of this field are as follows: - Wire: No access." "0,1" bitfld.long 0x14 15.--16. "PCIE_CAP_SLOT_POWER_LIMIT_SCALE,Slot Power Limit Scale. Specifies the scale used for the Slot Power Limit Value (for more details see Section 6.9 of PCI Express Base Specification). Range of Values: - 00b: 1.0x - 01b: 0.1x - 10b: 0.01x - 11b: 0.001x.." "0,1,2,3" newline hexmask.long.byte 0x14 7.--14. 1. "PCIE_CAP_SLOT_POWER_LIMIT_VALUE,Slot Power Limit Value. In combination with the Slot Power Limit Scale value specifies the upper limit on power supplied by the slot (for more detais see Section 6.9 of PCI Express Base Specification) or by other means.." bitfld.long 0x14 6. "PCIE_CAP_HOT_PLUG_CAPABLE,Hot-Plug Capable. When set this bit indicates that this slot is capable of supporting hot-plug operations. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then R/W else R" "0,1" newline bitfld.long 0x14 5. "PCIE_CAP_HOT_PLUG_SURPRISE,Hot-Plug Surprise. When set this bit indicates that an adapter present in this slot might be removed from the system without any prior notification. This is a form factor specific capability. This bit is an indication to the.." "0,1" bitfld.long 0x14 4. "PCIE_CAP_POWER_INDICATOR,Power Indicator Present. When set this bit indicates that a Power Indicator is electrically controlled by the chassis for this slot. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if.." "0,1" newline bitfld.long 0x14 3. "PCIE_CAP_ATTENTION_INDICATOR,Attention Indicator Present. When set this bit indicates that an Attention Indicator is electrically controlled by the chassis. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if.." "0,1" bitfld.long 0x14 2. "PCIE_CAP_MRL_SENSOR,MRL Sensor Present. When set this bit indicates that an MRL Sensor is implemented on the chassis for this slot. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then R/W else R" "0,1" newline bitfld.long 0x14 1. "PCIE_CAP_POWER_CONTROLLER,Power Controller Present. When set this bit indicates that a software programmable Power Controller is implemented for this slot/adapter (depending on form factor). Note: The access attributes of this field are as follows: -.." "0,1" bitfld.long 0x14 0. "PCIE_CAP_ATTENTION_INDICATOR_BUTTON,Attention Button Present. When set this bit indicates that an Attention Button for this slot is electrically controlled by the chassis. Note: The access attributes of this field are as follows: - Wire: No access. -.." "0,1" line.long 0x18 "SLOT_CONTROL_SLOT_STATUS,Slot Control and Status Register. This register controls and provides information about PCI Express Slot specific parameters." hexmask.long.byte 0x18 25.--31. 1. "RSVDP_25,Reserved for future use." bitfld.long 0x18 24. "PCIE_CAP_DLL_STATE_CHANGED,Data Link Layer State Changed. This bit is set when the value reported in the Data Link Layer Link Active bit of the Link Status register is changed. In response to a Data Link Layer State Changed event software must read the.." "0,1" newline rbitfld.long 0x18 23. "PCIE_CAP_ELECTROMECH_INTERLOCK_STATUS,Electromechanical Interlock Status. If an Electromechanical Interlock is implemented this bit indicates the status of the Electromechanical Interlock. Defined encodings are: - 0b: Electromechanical Interlock.." "0,1" rbitfld.long 0x18 22. "PCIE_CAP_PRESENCE_DETECT_STATE,Presence Detect State. This bit indicates the presence of an adapter in the slot reflected by the logical 'OR' of the Physical Layer in-band presence detect mechanism and if present any out-of-band presence detect.." "0,1" newline rbitfld.long 0x18 21. "PCIE_CAP_MRL_SENSOR_STATE,MRL Sensor State. This bit reports the status of the MRL sensor if implemented. Defined encodings are: - 0b: MRL Closed - 1b: MRL Open" "0,1" bitfld.long 0x18 20. "PCIE_CAP_CMD_CPLD,Command Completed. If Command Completed notification is supported (if the No Command Completed Support bit in the Slot Capabilities register is 0b) this bit is set when a hot-plug command has completed and the Hot-Plug Controller is.." "0,1" newline bitfld.long 0x18 19. "PCIE_CAP_PRESENCE_DETECTED_CHANGED,Presence Detect Changed. This bit is set when the value reported in the Presence Detect State bit is changed." "0,1" bitfld.long 0x18 18. "PCIE_CAP_MRL_SENSOR_CHANGED,MRL Sensor Changed. If an MRL sensor is implemented this bit is set when a MRL Sensor state change is detected. If an MRL sensor is not implemented this bit must not be set." "0,1" newline bitfld.long 0x18 17. "PCIE_CAP_POWER_FAULT_DETECTED,Power Fault Detected. If a Power Controller that supports power fault detection is implemented this bit issSet when the Power Controller detects a power fault at this slot. Note: Depending on hardware capability it is.." "0,1" bitfld.long 0x18 16. "PCIE_CAP_ATTENTION_BUTTON_PRESSED,Attention Button Pressed. If an Attention Button is implemented this bit is set when the attention button is pressed. If an Attention Button is not supported this bit must not be set." "0,1" newline rbitfld.long 0x18 14.--15. "RSVDP_14,Reserved for future use." "0,1,2,3" bitfld.long 0x18 12. "PCIE_CAP_DLL_STATE_CHANGED_EN,Data Link Layer State Changed Enable. If the Data Link Layer Link Active Reporting capability is 1b this bit enables software notification when Data Link Layer Link Active bit is changed. If the Data Link Layer Link Active.." "0,1" newline bitfld.long 0x18 11. "PCIE_CAP_ELECTROMECH_INTERLOCK_CTRL,Electromechanical Interlock Control. If an Electromechanical Interlock is implemented a write of 1b to this bit causes the state of the interlock to toggle. A write of 0b to this bit has no effect. A read of this bit.." "0,1" bitfld.long 0x18 10. "PCIE_CAP_POWER_CONTROLLER_CTRL,Power Controller Control. If a Power Controller is implemented this bit when written sets the power state of the slot per the defined encodings. Reads of this bit must reflect the value from the latest write even if the.." "0,1" newline bitfld.long 0x18 8.--9. "PCIE_CAP_POWER_INDICATOR_CTRL,Power Indicator Control. If a Power Indicator is implemented writes to this field set the Power Indicator to the written state. Reads of this field must reflect the value from the latest write even if the corresponding.." "0,1,2,3" bitfld.long 0x18 6.--7. "PCIE_CAP_ATTENTION_INDICATOR_CTRL,Attention Indicator Control. If an Attention Indicator is implemented writes to this field set the Attention Indicator to the written state. Reads of this field must reflect the value from the latest write even if the.." "0,1,2,3" newline bitfld.long 0x18 5. "PCIE_CAP_HOT_PLUG_INT_EN,Hot-Plug Interrupt Enable. When set this bit enables generation of an interrupt on enabled hot-plug events. If the Hot Plug Capable bit in the Slot Capabilities register is clear this bit is permitted to be read-only with a.." "0,1" bitfld.long 0x18 4. "PCIE_CAP_CMD_CPL_INT_EN,Command Completed Interrupt Enable. If Command Completed notification is supported (if the No Command Completed Support bit in the Slot Capabilities register is 0b) when set this bit enables software notification when a hot-plug.." "0,1" newline bitfld.long 0x18 3. "PCIE_CAP_PRESENCE_DETECT_CHANGE_EN,Presence Detect Changed Enable. When set this bit enables software notification on a presence detect changed event (for more details see Section 6.7.3 of PCI Express Base Specification). If the Hot-Plug Capable bit in.." "0,1" bitfld.long 0x18 2. "PCIE_CAP_MRL_SENSOR_CHANGED_EN,MRL Sensor Changed Enable. When set this bit enables software notification on a MRL sensor changed event (for more details see Section 6.7.3 of PCI Express Base Specification). If the MRL Sensor Present bit in the Slot.." "0,1" newline bitfld.long 0x18 1. "PCIE_CAP_POWER_FAULT_DETECTED_EN,Power Fault Detected Enable. When set this bit enables software notification on a power fault event (for more details see Section 6.7.3 of PCI Express Base Specification). If a Power Controller that supports power fault.." "0,1" bitfld.long 0x18 0. "PCIE_CAP_ATTENTION_BUTTON_PRESSED_EN,Attention Button Pressed Enable. When set to 1b this bit enables software notification on an attention button pressed event (for more details see Section 6.7.3 of PCI Express Base Specification). If the Attention.." "0,1" line.long 0x1C "ROOT_CONTROL_ROOT_CAPABILITIES_REG,Root Control and Capabilities Register. This register controls PCI Express Root Complex specific parameters and identifies PCI Express Root Port specific capabilities." hexmask.long.word 0x1C 17.--31. 1. "RSVDP_17,Reserved for future use." bitfld.long 0x1C 16. "PCIE_CAP_CRS_SW_VISIBILITY,CRS Software Visibility Capable. For a description of this standard PCIe register field see the PCI Express Base Specification. CRS Software Visibility. When set this bit indicates that the Root Port is capable of returning.." "0,1" newline hexmask.long.word 0x1C 5.--15. 1. "RSVDP_5,Reserved for future use." bitfld.long 0x1C 4. "PCIE_CAP_CRS_SW_VISIBILITY_EN,CRS Software Visibility Enable. When set this bit enables the Root Port to return Configuration Request Retry Status (CRS) Completion Status to software (for more details see section 2.3.1 of PCI Express Base.." "0,1" newline bitfld.long 0x1C 3. "PCIE_CAP_PME_INT_EN,PME Interrupt Enable. When set this bit enables PME interrupt generation upon receipt of a PME Message as reflected in the PME Status bit (for more details see Table 7-29 of PCI Express Base Specification). A PME interrupt is also.." "0,1" bitfld.long 0x1C 2. "PCIE_CAP_SYS_ERR_ON_FATAL_ERR_EN,System Error on Fatal Error Enable. If set this bit indicates that a System Error should be generated if a Fatal error (ERR_FATAL) is reported by any of the devices in the Hierarchy Domain associated with this Root Port.." "0,1" newline bitfld.long 0x1C 1. "PCIE_CAP_SYS_ERR_ON_NON_FATAL_ERR_EN,System Error on Non-Fatal Error Enable. If set this bit indicates that a System Error should be generated if a Non-fatal error (ERR_NONFATAL) is reported by any of the devices in the Hierarchy Domain associated with.." "0,1" bitfld.long 0x1C 0. "PCIE_CAP_SYS_ERR_ON_CORR_ERR_EN,System Error on Correctable Error Enable. If set this bit indicates that a System Error should be generated if a correctable error (ERR_COR) is reported by any of the devices in the Hierarchy Domain associated with this.." "0,1" line.long 0x20 "ROOT_STATUS_REG,Root Status Register. The Root Status register provides information about PCI Express device specific parameters." hexmask.long.word 0x20 18.--31. 1. "RSVDP_18,Reserved for future use." rbitfld.long 0x20 17. "PCIE_CAP_PME_PENDING,PME Pending. This bit indicates that another PME is pending when the PME Status bit is s et. When the PME Status bit is cleared by software; the PME is delivered by hardware by setting the PME Status bit again and updating the PME.." "0,1" newline bitfld.long 0x20 16. "PCIE_CAP_PME_STATUS,PME Status. This bit indicates that PME was asserted by the PME Requester indicated in the PME Requester ID field. Subsequent PMEs are kept pending until the status register is cleared by software by writing a 1b." "0,1" hexmask.long.word 0x20 0.--15. 1. "PCIE_CAP_PME_REQ_ID,PME Requester ID. This field indicates the PCI Requester ID of the last PME Requester. This field is only valid when the PME Status bit is set." line.long 0x24 "DEVICE_CAPABILITIES2_REG,Device Capabilities 2 Register." bitfld.long 0x24 31. "PCIE_CAP_FRS_SUPPORTED,FRS Supported. When set indicates support for the optional Function Readiness Status (FRS) capability. Must be set for all Functions that support generation or reception capabilities of FRS Messages. Must not be set by Switch.." "0,1" hexmask.long.byte 0x24 24.--30. 1. "RSVDP_24,Reserved for future use." newline bitfld.long 0x24 22.--23. "PCIE_CAP2_CFG_MAX_END2END_TLP_PRFXS,Max End-End TLP Prefixes. Indicates the maximum number of End-End TLP Prefixes supported by this Function. For more details see Section 2.2.10.2 of PCI Express Base Specification. Values are: - 01b: 1 End-End TLP.." "0,1,2,3" bitfld.long 0x24 21. "PCIE_CAP2_CFG_END2END_TLP_PRFX_SUPPORT,End-End TLP Prefix Supported. Indicates whether End-End TLP Prefix support is offered by a Function. Values are: - 0b: No Support - 1b: Support is provided to receive TLPs containing End-End TLP Prefixes. All Ports.." "0,1" newline bitfld.long 0x24 20. "PCIE_CAP2_CFG_EXTND_FMT_SUPPORT,Extended Fmt Field Supported. If set the Function supports the 3-bit definition of the Fmt field. If clear the Function supports a 2-bit definition of the Fmt field. For more details see section 2.2 of PCI Express Base.." "0,1" rbitfld.long 0x24 17. "PCIE_CAP2_10_BIT_TAG_REQ_SUPPORT,10-Bit Tag Requester Supported. If this bit is set the Function supports 10-Bit Tag Requester capability; otherwise the Function does not. This bit must not be set if the 10-Bit Tag Completer Supported bit is clear." "0,1" newline rbitfld.long 0x24 16. "PCIE_CAP2_10_BIT_TAG_COMP_SUPPORT,10-Bit Tag Completer Supported. If this bit is set the Function supports 10-Bit Tag Completer capability; otherwise the Function does not. For more details see section 2.2.6.2. of PCI Express Base Specification." "0,1" rbitfld.long 0x24 13. "PCIE_CAP_TPH_CMPLT_SUPPORT_1,TPH Completer Supported Bit 1." "0,1" newline rbitfld.long 0x24 12. "PCIE_CAP_TPH_CMPLT_SUPPORT_0,TPH Completer Supported Bit 0. Value of this bit along with TPH Completer Supported Bit 1 indicates Completer support for TPH or Extended TPH. Applicable only to Root Ports and Endpoints. For all other Functions this field.." "0,1" bitfld.long 0x24 11. "PCIE_CAP_LTR_SUPP,LTR Mechanism Supported. A value of 1b indicates support for the optional Latency Tolerance Reporting (LTR) mechanism. Root Ports Switches and Endpoints are permitted to implement this capability. For a Multi-Function Device associated.." "0,1" newline rbitfld.long 0x24 10. "PCIE_CAP_NO_RO_EN_PR2PR_PAR,No RO-enabled PR-PR Passing. If this bit is set the routing element never carries out the passing permitted by Table 2-39 of PCI Express Base Specification entry A2b that is associated with the Relaxed Ordering Attribute.." "0,1" rbitfld.long 0x24 9. "PCIE_CAP_128_CAS_CPL_SUPP,128-bit CAS Completer Supported. Applicable to Functions with Memory Space BARs as well as all Root Ports; must be 0b otherwise. This bit must be set to 1b if the Function supports this optional capability. For more details see.." "0,1" newline rbitfld.long 0x24 8. "PCIE_CAP_64_ATOMIC_CPL_SUPP,64-bit AtomicOp Completer Supported. Applicable to Functions with Memory Space BARs as well as all Root Ports; must be 0b otherwise. Includes FetchAdd Swap and CAS AtomicOps. This bit must be set to 1b if the Function.." "0,1" rbitfld.long 0x24 7. "PCIE_CAP_32_ATOMIC_CPL_SUPP,32-bit AtomicOp Completer Supported. Applicable to Functions with Memory Space BARs as well as all Root Ports; must be 0b otherwise. Includes FetchAdd Swap and CAS AtomicOps. This bit must be set to 1b if the Function.." "0,1" newline rbitfld.long 0x24 6. "PCIE_CAP_ATOMIC_ROUTING_SUPP,AtomicOp Routing Supported. Applicable only to Switch Upstream Ports Switch Downstream Ports and Root Ports; must be 0b for other Function types. This bit must be set to 1b if the Port supports this optional capability. For.." "0,1" rbitfld.long 0x24 5. "PCIE_CAP_ARI_FORWARD_SUPPORT,ARI Forwarding Supported. Applicable only to Switch Downstream Ports and Root Ports; must be 0b for other Function types. This bit must be set to 1b if a Switch Downstream Port or Root Port supports this optional capability." "0,1" newline rbitfld.long 0x24 4. "PCIE_CAP_CPL_TIMEOUT_DISABLE_SUPPORT,Completion Timeout Disable Supported. A value of 1b indicates support for the Completion Timeout Disable mechanism. The Completion Timeout Disable mechanism is required for Endpoints that issue Requests on their own.." "0,1" hexmask.long.byte 0x24 0.--3. 1. "PCIE_CAP_CPL_TIMEOUT_RANGE,Completion Timeout Ranges Supported. This field indicates device Function support for the optional Completion Timeout programmability mechanism. This mechanism allows system software to modify the Completion Timeout value. This.." line.long 0x28 "DEVICE_CONTROL2_DEVICE_STATUS2_REG,Device Control 2 and Status 2 Register." hexmask.long.word 0x28 16.--31. 1. "RSVDP_16,Reserved for future use." bitfld.long 0x28 15. "PCIE_CTRL2_CFG_END2END_TLP_PFX_BLCK,End-End TLP Prefix Blocking. Controls whether the routing function is permitted to forward TLPs containing an End-End TLP Prefix. Values are: - 0b: Forwarding Enabled - Function is permitted to send TLPs with End-End.." "0,1" newline rbitfld.long 0x28 11. "RSVDP_11,Reserved for future use." "0,1" bitfld.long 0x28 10. "PCIE_CAP_LTR_EN,LTR Mechanism Enable. When set to 1b this bit enables Upstream Ports to send LTR messages and Downstream Ports to process LTR Messages. For a Multi-Function Device associated with an Upstream Port of a device that implements LTR the bit.." "0,1" newline rbitfld.long 0x28 5. "PCIE_CAP_ARI_FORWARD_SUPPORT_CS,ARI Forwarding Enable. When set the Downstream Port disables its traditional Device Number field being 0 enforcement when turning a Type 1 Configuration Request into a Type 0 Configuration Request permitting access to.." "0,1" bitfld.long 0x28 4. "PCIE_CAP_CPL_TIMEOUT_DISABLE,Completion Timeout Disable. When set this bit disables the Completion Timeout mechanism. This bit is required for all Functions that support the Completion Timeout Disable Capability. Functions that do not support this.." "0,1" newline hexmask.long.byte 0x28 0.--3. 1. "PCIE_CAP_CPL_TIMEOUT_VALUE,Completion Timeout Value. In device Functions that support Completion Timeout programmability this field allows system software to modify the Completion Timeout value. This field is applicable to Root Ports Endpoints that.." line.long 0x2C "LINK_CAPABILITIES2_REG,Link Capabilities 2 Register." bitfld.long 0x2C 31. "DRS_SUPPORTED,DRS Supported. When set indicates support for the optional Device Readiness Status (DRS) capability. Must be Set in Downstream Ports that support DRS. Must be Set in Downstream Ports that support FRS. For Upstream Ports that support DRS.." "0,1" hexmask.long.byte 0x2C 25.--30. 1. "RSVDP_25,Reserved for future use." newline hexmask.long.word 0x2C 9.--22. 1. "RSVDP_9,Reserved for future use." rbitfld.long 0x2C 8. "PCIE_CAP_CROSS_LINK_SUPPORT,Crosslink Supported. When set to 1b this bit indicates that the associated Port supports crosslinks (for more details see section 4.2.6.3.1 of PCI Express Base Specification). When set to 0b on a Port that supports Link.." "0,1" newline hexmask.long.byte 0x2C 1.--7. 1. "PCIE_CAP_SUPPORT_LINK_SPEED_VECTOR,Supported Link Speeds Vector. This field indicates the supported Link speed(s) of the associated Port. For each bit a value of 1b indicates that the corresponding Link speed is supported; otherwise the Link speed is.." rbitfld.long 0x2C 0. "RSVDP_0,Reserved for future use." "0,1" line.long 0x30 "LINK_CONTROL2_LINK_STATUS2_REG,Link Control 2 and Status 2 Register." bitfld.long 0x30 31. "DRS_MESSAGE_RECEIVED,DRS Message Received. This bit must be set whenever the Port receives a DRS Message. This bit must be cleared in DL_Down. This bit must be implemented in any Downstream Port where the DRS Supported bit is Set in the Link Capabilities.." "0,1" rbitfld.long 0x30 28.--30. "DOWNSTREAM_COMPO_PRESENCE,Downstream Component Presence. This field indicates the presence and DRS status for the Downstream Component if any connected to the Link; defined values are: - 000b: Link Down - Presence Not Determined - 001b: Link Down -.." "0,1,2,3,4,5,6,7" newline rbitfld.long 0x30 26.--27. "RSVDP_26,Reserved for future use." "0,1,2,3" bitfld.long 0x30 21. "PCIE_CAP_LINK_EQ_REQ,Link Equalization Request 8.0 GT/s. This bit is set by hardware to request the 8.0 GT/s Link equalization process to be performed on the Link. For more details see sections 4.2.3 and 4.2.6.4.2 of PCI Express Base Specification. For.." "0,1" newline rbitfld.long 0x30 20. "PCIE_CAP_EQ_CPL_P3,EEqualization 8.0 GT/s Phase 3 Successful. When set to 1b this bit indicates that Phase 3 of the 8.0 GT/s Transmitter Equalization procedure has successfully completed. Details of the Transmitter Equalization process and when this bit.." "0,1" rbitfld.long 0x30 19. "PCIE_CAP_EQ_CPL_P2,Equalization 8.0 GT/s Phase 2 Successful. When set to 1b this bit indicates that Phase 2 of the 8.0 GT/s Transmitter Equalization procedure has successfully completed. Details of the Transmitter Equalization process and when this bit.." "0,1" newline rbitfld.long 0x30 18. "PCIE_CAP_EQ_CPL_P1,Equalization 8.0 GT/s Phase 1 Successful. When set to 1b this bit indicates that Phase 1 of the 8.0 GT/s Transmitter Equalization procedure has successfully completed. Details of the Transmitter Equalization process and when this bit.." "0,1" rbitfld.long 0x30 17. "PCIE_CAP_EQ_CPL,Equalization 8.0 GT/s Complete. When set to 1b this bit indicates that the Transmitter Equalization procedure at the 8.0 GT/s data rate has completed. Details of the Transmitter Equalization process and when this bit needs to be set to.." "0,1" newline rbitfld.long 0x30 16. "PCIE_CAP_CURR_DEEMPHASIS,Current De-emphasis Level. When the Link is operating at 5.0 GT/s speed this bit reflects the level of de-emphasis. Encodings: - 1b: -3.5 dB - 0b: -6 dB The value in this bit is undefined when the Link is not operating at 5.0.." "0,1" hexmask.long.byte 0x30 12.--15. 1. "PCIE_CAP_COMPLIANCE_PRESET,Compliance Preset/De-emphasis. For 8.0 GT/s and higher Data Rate: This field sets the Transmitter Preset in Polling.Compliance state if the entry occurred due to the Enter Compliance bit being 1b. The encodings are defined in.." newline bitfld.long 0x30 11. "PCIE_CAP_COMPLIANCE_SOS,Compliance SOS. When set to 1b the LTSSM is required to send SKP Ordered Sets between sequences when sending the Compliance Pattern or Modified Compliance Pattern. For a Multi-Function Device associated with an Upstream Port the.." "0,1" bitfld.long 0x30 10. "PCIE_CAP_ENTER_MODIFIED_COMPLIANCE,Enter Modified Compliance. When this bit is set to 1b the device transmits Modified Compliance Pattern if the LTSSM enters Polling.Compliance substate. Components that support only the 2.5 GT/s speed are permitted to.." "0,1" newline bitfld.long 0x30 7.--9. "PCIE_CAP_TX_MARGIN,Transmit Margin - This field controls the value of the non-deemphasized voltage level at the Transmitter pins. This field is reset to 000b on entry to the LTSSM Polling.Configuration substate (see Chapter 4 of PCI Express Base.." "0,1,2,3,4,5,6,7" bitfld.long 0x30 6. "PCIE_CAP_SEL_DEEMPHASIS,Selectable De-emphasis. When the Link is operating at 5.0 GT/s speed this bit is used to control the transmit de-emphasis of the link in specific situations. For more details see section 4.2.6 of PCI Express Base Specification." "0,1" newline bitfld.long 0x30 5. "PCIE_CAP_HW_AUTO_SPEED_DISABLE,Hardware Autonomous Speed Disable. When set this bit disables hardware from changing the Link speed for device-specific reasons other than attempting to correct unreliable Link operation by reducing Link speed. Initial.." "0,1" bitfld.long 0x30 4. "PCIE_CAP_ENTER_COMPLIANCE,Enter Compliance. Software is permitted to force a Link to enter Compliance mode (at the speed indicated in the Target Link Speed field and the de-emphasis/preset level indicated by the Compliance Preset/De-emphasis field) by.." "0,1" newline hexmask.long.byte 0x30 0.--3. 1. "PCIE_CAP_TARGET_LINK_SPEED,Target Link Speed. For Downstream Ports this field sets an upper limit on Link operational speed by restricting the values advertised by the Upstream component in its training sequences. The encoded value specifies a bit.." tree.end tree "PF0_AER_CAP (PF Advanced Error Reporting Capability Structure)" group.long (0x0+0x100)++0x1B line.long 0x0 "AER_EXT_CAP_HDR_OFF,Advanced Error Reporting Extended Capability Header. For a description of this standard PCIe register. see the PCI Express Specification." hexmask.long.word 0x0 20.--31. 1. "NEXT_OFFSET,Next Capability Offset. For a description of this standard PCIe register field see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky).." hexmask.long.byte 0x0 16.--19. 1. "CAP_VERSION,Capability Version. For a description of this standard PCIe register field see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else.." hexmask.long.word 0x0 0.--15. 1. "CAP_ID,AER Extended Capability ID. For a description of this standard PCIe register field see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else.." line.long 0x4 "UNCORR_ERR_STATUS_OFF,Uncorrectable Error Status Register. For a description of this standard PCIe register. see the PCI Express Specification." hexmask.long.byte 0x4 27.--31. 1. "RSVDP_27,Reserved for future use." bitfld.long 0x4 25. "TLP_PRFX_BLOCKED_ERR_STATUS,TLP Prefix Blocked Error Status. For a description of this standard PCIe register field see the PCI Express Specification. Note: Not supported." "0,1" rbitfld.long 0x4 23. "RSVDP_23,Reserved for future use." "0,1" newline bitfld.long 0x4 22. "INTERNAL_ERR_STATUS,Uncorrectable Internal Error Status. For a description of this standard PCIe register field see the PCI Express Specification. The controller sets this bit when your application asserts app_err_bus[9]. It does not set this bit when.." "0,1" bitfld.long 0x4 20. "UNSUPPORTED_REQ_ERR_STATUS,Unsupported Request Error Status. For a description of this standard PCIe register field see the PCI Express Specification." "0,1" bitfld.long 0x4 19. "ECRC_ERR_STATUS,ECRC Error Status. For a description of this standard PCIe register field see the PCI Express Specification. Note:If CX_ECRC_ENABLE=0 the register field always reads 0." "0,1" newline bitfld.long 0x4 18. "MALF_TLP_ERR_STATUS,Malformed TLP Status. For a description of this standard PCIe register field see the PCI Express Specification." "0,1" bitfld.long 0x4 17. "REC_OVERFLOW_ERR_STATUS,Receiver Overflow Status. For a description of this standard PCIe register field see the PCI Express Specification." "0,1" bitfld.long 0x4 16. "UNEXP_CMPLT_ERR_STATUS,Unexpected Completion Status. For a description of this standard PCIe register field see the PCI Express Specification." "0,1" newline bitfld.long 0x4 15. "CMPLT_ABORT_ERR_STATUS,Completer Abort Status. For a description of this standard PCIe register field see the PCI Express Specification." "0,1" bitfld.long 0x4 14. "CMPLT_TIMEOUT_ERR_STATUS,Completion Timeout Status. For a description of this standard PCIe register field see the PCI Express Specification." "0,1" bitfld.long 0x4 13. "FC_PROTOCOL_ERR_STATUS,Flow Control Protocol Error Status. For a description of this standard PCIe register field see the PCI Express Specification." "0,1" newline bitfld.long 0x4 12. "POIS_TLP_ERR_STATUS,Poisoned TLP Status. For a description of this standard PCIe register field see the PCI Express Specification." "0,1" hexmask.long.byte 0x4 6.--11. 1. "RSVDP_6,Reserved for future use." bitfld.long 0x4 5. "SURPRISE_DOWN_ERR_STATUS,Surprise Down Error Status (Optional). For a description of this standard PCIe register field see the PCI Express Specification." "0,1" newline bitfld.long 0x4 4. "DL_PROTOCOL_ERR_STATUS,Data Link Protocol Error Status. For a description of this standard PCIe register field see the PCI Express Specification." "0,1" hexmask.long.byte 0x4 0.--3. 1. "RSVDP_0,Reserved for future use." line.long 0x8 "UNCORR_ERR_MASK_OFF,Uncorrectable Error Mask Register. For a description of this standard PCIe register. see the PCI Express Specification." hexmask.long.byte 0x8 27.--31. 1. "RSVDP_27,Reserved for future use." bitfld.long 0x8 25. "TLP_PRFX_BLOCKED_ERR_MASK,TLP Prefix Blocked Error Mask. For a description of this standard PCIe register field see the PCI Express Specification. Note: Not supported. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi:.." "0,1" rbitfld.long 0x8 23. "RSVDP_23,Reserved for future use." "0,1" newline bitfld.long 0x8 22. "INTERNAL_ERR_MASK,Uncorrectable Internal Error Mask (Optional). For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." "0,1" rbitfld.long 0x8 21. "ACS_VIOLATION_MASK,ACS Violation Mask. Setting the ACS Violation Mask bit disables error logging and signaling for ACS Violation errors. The bit is Read-Only Zero for upstream ports when ACS P2P Egress Control Enable is not set. For a description of.." "0,1" bitfld.long 0x8 20. "UNSUPPORTED_REQ_ERR_MASK,Unsupported Request Error Mask. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." "0,1" newline bitfld.long 0x8 19. "ECRC_ERR_MASK,ECRC Error Mask (Optional). For a description of this standard PCIe register field see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W (sticky) Note: This register.." "0,1" bitfld.long 0x8 18. "MALF_TLP_ERR_MASK,Malformed TLP Mask. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." "0,1" bitfld.long 0x8 17. "REC_OVERFLOW_ERR_MASK,Receiver Overflow Mask (Optional). For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." "0,1" newline bitfld.long 0x8 16. "UNEXP_CMPLT_ERR_MASK,Unexpected Completion Mask. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." "0,1" bitfld.long 0x8 15. "CMPLT_ABORT_ERR_MASK,Completer Abort Error Mask (Optional). For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." "0,1" bitfld.long 0x8 14. "CMPLT_TIMEOUT_ERR_MASK,Completion Timeout Error Mask. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." "0,1" newline bitfld.long 0x8 13. "FC_PROTOCOL_ERR_MASK,Flow Control Protocol Error Mask. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." "0,1" bitfld.long 0x8 12. "POIS_TLP_ERR_MASK,Poisoned TLP Error Mask. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." "0,1" hexmask.long.byte 0x8 6.--11. 1. "RSVDP_6,Reserved for future use." newline rbitfld.long 0x8 5. "SURPRISE_DOWN_ERR_MASK,Surprise Down Error Mask. For a description of this standard PCIe register field see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi:.." "0,1" bitfld.long 0x8 4. "DL_PROTOCOL_ERR_MASK,Data Link Protocol Error Mask. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." "0,1" hexmask.long.byte 0x8 0.--3. 1. "RSVDP_0,Reserved for future use." line.long 0xC "UNCORR_ERR_SEV_OFF,Uncorrectable Error Severity Register. For a description of this standard PCIe register. see the PCI Express Specification." hexmask.long.byte 0xC 27.--31. 1. "RSVDP_27,Reserved for future use." bitfld.long 0xC 25. "TLP_PRFX_BLOCKED_ERR_SEVERITY,TLP Prefix Blocked Error Severity (Optional). For a description of this standard PCIe register field see the PCI Express Specification. Note: Not supported. Note: The access attributes of this field are as follows: - Wire:.." "0,1" rbitfld.long 0xC 24. "ATOMIC_EGRESS_BLOCKED_ERR_SEVERITY,AtomicOp Egress Blocked Severity (Optional). For a description of this standard PCIe register field see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi:.." "0,1" newline rbitfld.long 0xC 23. "RSVDP_23,Reserved for future use." "0,1" bitfld.long 0xC 22. "INTERNAL_ERR_SEVERITY,Uncorrectable Internal Error Severity (Optional). For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." "0,1" bitfld.long 0xC 20. "UNSUPPORTED_REQ_ERR_SEVERITY,Unsupported Request Error Severity. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." "0,1" newline bitfld.long 0xC 19. "ECRC_ERR_SEVERITY,ECRC Error Severity (Optional). For a description of this standard PCIe register field see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W (sticky) Note: This.." "0,1" bitfld.long 0xC 18. "MALF_TLP_ERR_SEVERITY,Malformed TLP Severity. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." "0,1" bitfld.long 0xC 17. "REC_OVERFLOW_ERR_SEVERITY,Receiver Overflow Error Severity (Optional). For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." "0,1" newline bitfld.long 0xC 16. "UNEXP_CMPLT_ERR_SEVERITY,Unexpected Completion Error Severity. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." "0,1" bitfld.long 0xC 15. "CMPLT_ABORT_ERR_SEVERITY,Completer Abort Error Severity (Optional). For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." "0,1" bitfld.long 0xC 14. "CMPLT_TIMEOUT_ERR_SEVERITY,Completion Timeout Error Severity. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." "0,1" newline bitfld.long 0xC 13. "FC_PROTOCOL_ERR_SEVERITY,Flow Control Protocol Error Severity (Optional). For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." "0,1" bitfld.long 0xC 12. "POIS_TLP_ERR_SEVERITY,Poisoned TLP Severity. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." "0,1" hexmask.long.byte 0xC 6.--11. 1. "RSVDP_6,Reserved for future use." newline rbitfld.long 0xC 5. "SURPRISE_DOWN_ERR_SVRITY,Surprise Down Error Severity (Optional). For a description of this standard PCIe register field see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi:.." "0,1" bitfld.long 0xC 4. "DL_PROTOCOL_ERR_SEVERITY,Data Link Protocol Error Severity. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." "0,1" hexmask.long.byte 0xC 0.--3. 1. "RSVDP_0,Reserved for future use." line.long 0x10 "CORR_ERR_STATUS_OFF,Correctable Error Status Register. For a description of this standard PCIe register. see the PCI Express Specification." hexmask.long.word 0x10 16.--31. 1. "RSVDP_16,Reserved for future use." bitfld.long 0x10 15. "HEADER_LOG_OVERFLOW_STATUS,Header Log Overflow Error Status (Optional). For a description of this standard PCIe register field see the PCI Express Specification." "0,1" bitfld.long 0x10 14. "CORRECTED_INT_ERR_STATUS,Corrected Internal Error Status (Optional). For a description of this standard PCIe register field see the PCI Express Specification." "0,1" newline bitfld.long 0x10 13. "ADVISORY_NON_FATAL_ERR_STATUS,Advisory Non-Fatal Error Status. For a description of this standard PCIe register field see the PCI Express Specification." "0,1" bitfld.long 0x10 12. "RPL_TIMER_TIMEOUT_STATUS,Replay Timer Timeout Status. For a description of this standard PCIe register field see the PCI Express Specification." "0,1" rbitfld.long 0x10 9.--11. "RSVDP_9,Reserved for future use." "0,1,2,3,4,5,6,7" newline bitfld.long 0x10 8. "REPLAY_NO_ROLEOVER_STATUS,REPLAY_NUM Rollover Status. For a description of this standard PCIe register field see the PCI Express Specification." "0,1" bitfld.long 0x10 7. "BAD_DLLP_STATUS,Bad DLLP Status. For a description of this standard PCIe register field see the PCI Express Specification." "0,1" bitfld.long 0x10 6. "BAD_TLP_STATUS,Bad TLP Status. For a description of this standard PCIe register field see the PCI Express Specification." "0,1" newline hexmask.long.byte 0x10 1.--5. 1. "RSVDP_1,Reserved for future use." bitfld.long 0x10 0. "RX_ERR_STATUS,Receiver Error Status (Optional). For a description of this standard PCIe register field see the PCI Express Specification." "0,1" line.long 0x14 "CORR_ERR_MASK_OFF,Correctable Error Mask Register. For a description of this standard PCIe register. see the PCI Express Specification." hexmask.long.word 0x14 16.--31. 1. "RSVDP_16,Reserved for future use." bitfld.long 0x14 15. "HEADER_LOG_OVERFLOW_MASK,Header Log Overflow Error Mask (Optional). For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." "0,1" bitfld.long 0x14 14. "CORRECTED_INT_ERR_MASK,Corrected Internal Error Mask (Optional). For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." "0,1" newline bitfld.long 0x14 13. "ADVISORY_NON_FATAL_ERR_MASK,Advisory Non-Fatal Error Mask. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." "0,1" bitfld.long 0x14 12. "RPL_TIMER_TIMEOUT_MASK,Replay Timer Timeout Mask. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." "0,1" rbitfld.long 0x14 9.--11. "RSVDP_9,Reserved for future use." "0,1,2,3,4,5,6,7" newline bitfld.long 0x14 8. "REPLAY_NO_ROLEOVER_MASK,REPLAY_NUM Rollover Mask. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." "0,1" bitfld.long 0x14 7. "BAD_DLLP_MASK,Bad DLLP Mask. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." "0,1" bitfld.long 0x14 6. "BAD_TLP_MASK,Bad TLP Mask. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." "0,1" newline hexmask.long.byte 0x14 1.--5. 1. "RSVDP_1,Reserved for future use." bitfld.long 0x14 0. "RX_ERR_MASK,Receiver Error Mask (Optional). For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." "0,1" line.long 0x18 "ADV_ERR_CAP_CTRL_OFF,Advanced Error Capabilities and Control Register. For a description of this standard PCIe register. see the PCI Express Specification." hexmask.long.tbyte 0x18 13.--31. 1. "RSVDP_13,Reserved for future use." rbitfld.long 0x18 12. "CTO_PRFX_HDR_LOG_CAP,TLP Prefix Log Present. For a description of this standard PCIe register field see the PCI Express Specification." "0,1" rbitfld.long 0x18 11. "TLP_PRFX_LOG_PRESENT,Completion Timeout Prefix/Header Log Capable. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." "0,1" newline rbitfld.long 0x18 10. "MULTIPLE_HEADER_EN,Multiple Header Recording Enable. For a description of this standard PCIe register field see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R (sticky) Note: This.." "0,1" rbitfld.long 0x18 9. "MULTIPLE_HEADER_CAP,Multiple Header Recording Capable. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." "0,1" bitfld.long 0x18 8. "ECRC_CHECK_EN,ECRC Check Enable. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." "0,1" newline rbitfld.long 0x18 7. "ECRC_CHECK_CAP,ECRC Check Capable. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." "0,1" bitfld.long 0x18 6. "ECRC_GEN_EN,ECRC Generation Enable. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." "0,1" rbitfld.long 0x18 5. "ECRC_GEN_CAP,ECRC Generation Capable. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." "0,1" newline hexmask.long.byte 0x18 0.--4. 1. "FIRST_ERR_POINTER,First Error Pointer. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." rgroup.long (0x1C+0x100)++0xF line.long 0x0 "HDR_LOG_0_OFF,Header Log Register 0. For a description of this standard PCIe register. see the PCI Express Specification." hexmask.long.byte 0x0 24.--31. 1. "FIRST_DWORD_FOURTH_BYTE,Byte 3 of Header log register of First 32 bit Data Word. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." hexmask.long.byte 0x0 16.--23. 1. "FIRST_DWORD_THIRD_BYTE,Byte 2 of Header log register of First 32 bit Data Word. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." hexmask.long.byte 0x0 8.--15. 1. "FIRST_DWORD_SECOND_BYTE,Byte 1 of Header log register of First 32 bit Data Word. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." newline hexmask.long.byte 0x0 0.--7. 1. "FIRST_DWORD_FIRST_BYTE,Byte 0 of Header log register of First 32 bit Data Word. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." line.long 0x4 "HDR_LOG_1_OFF,Header Log Register 1. For a description of this standard PCIe register. see the PCI Express Specification." hexmask.long.byte 0x4 24.--31. 1. "SECOND_DWORD_FOURTH_BYTE,Byte 3 of Header log register of Second 32 bit Data Word. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." hexmask.long.byte 0x4 16.--23. 1. "SECOND_DWORD_THIRD_BYTE,Byte 2 of Header log register of Second 32 bit Data Word. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." hexmask.long.byte 0x4 8.--15. 1. "SECOND_DWORD_SECOND_BYTE,Byte 1 of Header log register of Second 32 bit Data Word. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." newline hexmask.long.byte 0x4 0.--7. 1. "SECOND_DWORD_FIRST_BYTE,Byte 0 of Header log register of Second 32 bit Data Word. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." line.long 0x8 "HDR_LOG_2_OFF,Header Log Register 2. For a description of this standard PCIe register. see the PCI Express Specification." hexmask.long.byte 0x8 24.--31. 1. "THIRD_DWORD_FOURTH_BYTE,Byte 3 of Header log register of Third 32 bit Data Word. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." hexmask.long.byte 0x8 16.--23. 1. "THIRD_DWORD_THIRD_BYTE,Byte 2 of Header log register of Third 32 bit Data Word. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." hexmask.long.byte 0x8 8.--15. 1. "THIRD_DWORD_SECOND_BYTE,Byte 1 of Header log register of Third 32 bit Data Word. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." newline hexmask.long.byte 0x8 0.--7. 1. "THIRD_DWORD_FIRST_BYTE,Byte 0 of Header log register of Third 32 bit Data Word. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." line.long 0xC "HDR_LOG_3_OFF,Header Log Register 3. For a description of this standard PCIe register. see the PCI Express Specification." hexmask.long.byte 0xC 24.--31. 1. "FOURTH_DWORD_FOURTH_BYTE,Byte 3 of Header log register of Fourth 32 bit Data Word. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." hexmask.long.byte 0xC 16.--23. 1. "FOURTH_DWORD_THIRD_BYTE,Byte 2 of Header log register of Fourth 32 bit Data Word. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." hexmask.long.byte 0xC 8.--15. 1. "FOURTH_DWORD_SECOND_BYTE,Byte 1 of Header log register of Fourth 32 bit Data Word. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." newline hexmask.long.byte 0xC 0.--7. 1. "FOURTH_DWORD_FIRST_BYTE,Byte 0 of Header log register of Fourth 32 bit Data Word. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." group.long (0x2C+0x100)++0x7 line.long 0x0 "ROOT_ERR_CMD_OFF,Root Error Command Register. For a description of this standard PCIe register. see the PCI Express Specification." hexmask.long 0x0 3.--31. 1. "RSVDP_3,Reserved for future use." bitfld.long 0x0 2. "FATAL_ERR_REPORTING_EN,Fatal Error Reporting Enable. For a description of this standard PCIe register field see the PCI Express Specification." "0,1" bitfld.long 0x0 1. "NON_FATAL_ERR_REPORTING_EN,Non-Fatal Error Reporting Enable. For a description of this standard PCIe register field see the PCI Express Specification." "0,1" newline bitfld.long 0x0 0. "CORR_ERR_REPORTING_EN,Correctable Error Reporting Enable. For a description of this standard PCIe register field see the PCI Express Specification." "0,1" line.long 0x4 "ROOT_ERR_STATUS_OFF,Root Error Status Register. For a description of this standard PCIe register. see the PCI Express Specification." hexmask.long.byte 0x4 27.--31. 1. "ADV_ERR_INT_MSG_NUM,Advanced Error Interrupt Message Number. For a description of this standard PCIe register field see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN.." hexmask.long.tbyte 0x4 7.--26. 1. "RSVDP_7,Reserved for future use." bitfld.long 0x4 6. "FATAL_ERR_MSG_RX,One or more Fatal Error Messages Received. For a description of this standard PCIe register field see the PCI Express Specification." "0,1" newline bitfld.long 0x4 5. "NON_FATAL_ERR_MSG_RX,One or more Non-Fatal Error Messages Received. For a description of this standard PCIe register field see the PCI Express Specification." "0,1" bitfld.long 0x4 4. "FIRST_UNCORR_FATAL,First Uncorrectable Error is Fatal. For a description of this standard PCIe register field see the PCI Express Specification." "0,1" bitfld.long 0x4 3. "MUL_ERR_FATAL_NON_FATAL_RX,Multiple Fatal or Non-Fatal Errors Received. For a description of this standard PCIe register field see the PCI Express Specification." "0,1" newline bitfld.long 0x4 2. "ERR_FATAL_NON_FATAL_RX,Fatal or Non-Fatal Error Received. For a description of this standard PCIe register field see the PCI Express Specification." "0,1" bitfld.long 0x4 1. "MUL_ERR_COR_RX,Multiple Correctable Errors Received. For a description of this standard PCIe register field see the PCI Express Specification." "0,1" bitfld.long 0x4 0. "ERR_COR_RX,Correctable Error Received. For a description of this standard PCIe register field see the PCI Express Specification." "0,1" rgroup.long (0x34+0x100)++0x13 line.long 0x0 "ERR_SRC_ID_OFF,Error Source Identification Register. For a description of this standard PCIe register. see the PCI Express Specification." hexmask.long.word 0x0 16.--31. 1. "ERR_FATAL_NON_FATAL_SOURCE_ID,Source of Fatal/Non-Fatal Error. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." hexmask.long.word 0x0 0.--15. 1. "ERR_COR_SOURCE_ID,Source of Correctable Error. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." line.long 0x4 "TLP_PREFIX_LOG_1_OFF,TLP Prefix Log Register 1. For a description of this standard PCIe register. see the PCI Express Specification." hexmask.long.byte 0x4 24.--31. 1. "CFG_TLP_PFX_LOG_1_FOURTH_BYTE,Byte 3 of Error TLP Prefix Log 1. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." hexmask.long.byte 0x4 16.--23. 1. "CFG_TLP_PFX_LOG_1_THIRD_BYTE,Byte 2 of Error TLP Prefix Log 1. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." hexmask.long.byte 0x4 8.--15. 1. "CFG_TLP_PFX_LOG_1_SECOND_BYTE,Byte 1 of Error TLP Prefix Log 1. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." newline hexmask.long.byte 0x4 0.--7. 1. "CFG_TLP_PFX_LOG_1_FIRST_BYTE,Byte 0 of Error TLP Prefix Log 1. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." line.long 0x8 "TLP_PREFIX_LOG_2_OFF,TLP Prefix Log Register 2. For a description of this standard PCIe register. see the PCI Express Specification." hexmask.long.byte 0x8 24.--31. 1. "CFG_TLP_PFX_LOG_2_FOURTH_BYTE,Byte 3 Error TLP Prefix Log 2. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." hexmask.long.byte 0x8 16.--23. 1. "CFG_TLP_PFX_LOG_2_THIRD_BYTE,Byte 2 Error TLP Prefix Log 2. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." hexmask.long.byte 0x8 8.--15. 1. "CFG_TLP_PFX_LOG_2_SECOND_BYTE,Byte 1 Error TLP Prefix Log 2. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." newline hexmask.long.byte 0x8 0.--7. 1. "CFG_TLP_PFX_LOG_2_FIRST_BYTE,Byte 0 Error TLP Prefix Log 2. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." line.long 0xC "TLP_PREFIX_LOG_3_OFF,TLP Prefix Log Register 3. For a description of this standard PCIe register. see the PCI Express Specification." hexmask.long.byte 0xC 24.--31. 1. "CFG_TLP_PFX_LOG_3_FOURTH_BYTE,Byte 3 Error TLP Prefix Log 3. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." hexmask.long.byte 0xC 16.--23. 1. "CFG_TLP_PFX_LOG_3_THIRD_BYTE,Byte 2 Error TLP Prefix Log 3. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." hexmask.long.byte 0xC 8.--15. 1. "CFG_TLP_PFX_LOG_3_SECOND_BYTE,Byte 1 Error TLP Prefix Log 3. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." newline hexmask.long.byte 0xC 0.--7. 1. "CFG_TLP_PFX_LOG_3_FIRST_BYTE,Byte 0 Error TLP Prefix Log 3. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." line.long 0x10 "TLP_PREFIX_LOG_4_OFF,TLP Prefix Log Register 4. For a description of this standard PCIe register. see the PCI Express Specification." hexmask.long.byte 0x10 24.--31. 1. "CFG_TLP_PFX_LOG_4_FOURTH_BYTE,Byte 3 Error TLP Prefix Log 4. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." hexmask.long.byte 0x10 16.--23. 1. "CFG_TLP_PFX_LOG_4_THIRD_BYTE,Byte 2 Error TLP Prefix Log 4. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." hexmask.long.byte 0x10 8.--15. 1. "CFG_TLP_PFX_LOG_4_SECOND_BYTE,Byte 1 Error TLP Prefix Log 4. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." newline hexmask.long.byte 0x10 0.--7. 1. "CFG_TLP_PFX_LOG_4_FIRST_BYTE,Byte 0 Error TLP Prefix Log 4. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." tree.end tree "PF0_MSI_CAP (PF MSI Capability Structure)" group.long (0x0+0x50)++0x13 line.long 0x0 "PCI_MSI_CAP_ID_NEXT_CTRL_REG,MSI Capability Header and Message Control Register." hexmask.long.byte 0x0 27.--31. 1. "RSVDP_27,Reserved for future use." bitfld.long 0x0 26. "PCI_MSI_EXT_DATA_EN,Extended Message Data Enable. - If set the function is enabled to provide Extended Message Data. - If clear the function is not enabled to provide Extended Message Data. Note: The access attributes of this field are as follows: -.." "0,1" bitfld.long 0x0 25. "PCI_MSI_EXT_DATA_CAP,Extended Message Data Capable. - If set the function is capable of providing Extended Message Data. - If clear the function does not support providing Extended Message Data. Note: The access attributes of this field are as follows:.." "0,1" newline rbitfld.long 0x0 24. "PCI_PVM_SUPPORT,Per-Vector Masking Capable. - If set the function supports MSI Per-Vector Masking. - If clear the function does not support MSI Per-Vector Masking. This bit must be set if the function is a PF or VF within an SR-IOV Device." "0,1" bitfld.long 0x0 23. "PCI_MSI_64_BIT_ADDR_CAP,64 bit address capable. - If set the function is capable of sending a 64-bit message address. - If clear the function is not capable of sending a 64-bit message address. This bit must be set if the function is a PCI Express.." "0,1" bitfld.long 0x0 20.--22. "PCI_MSI_MULTIPLE_MSG_EN,Multiple Message Enable. Software writes to this field to indicate the number of allocated vectors (equal to or less than the number of requested vectors). The number of allocated vectors is aligned to a power of two. If a.." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 17.--19. "PCI_MSI_MULTIPLE_MSG_CAP,Multiple Message Capable. System software reads this field to determine the number of requested vectors. The number of requested vectors must be aligned to a power of two (if a function requires three vectors it requests four by.." "0,1,2,3,4,5,6,7" bitfld.long 0x0 16. "PCI_MSI_ENABLE,MSI Enable. - If set and the MSI-X Enable bit in the MSI-X Message Control register is clear the function is permitted to use MSI to request service and is prohibited from using INTx interrupts. System configuration software sets this bit.." "0,1" hexmask.long.byte 0x0 8.--15. 1. "PCI_MSI_CAP_NEXT_OFFSET,Next Capability Pointer. This field contains the offset to the next PCI Capability structure or 00h if no other items exist in the linked list of Capabilities. Note: The access attributes of this field are as follows: - Wire: No.." newline hexmask.long.byte 0x0 0.--7. 1. "PCI_MSI_CAP_ID,Capability ID. Indicates the MSI Capability structure. This field returns a Capability ID of 05h indicating that this is an MSI Capability structure." line.long 0x4 "MSI_CAP_OFF_04H_REG,Message Address Register for MSI (Offset 04h)." hexmask.long 0x4 2.--31. 1. "PCI_MSI_CAP_OFF_04H,Message Address - System-specified message address. If the Message Enable bit (bit 16 of the PCI_MSI_CAP_ID_NEXT_CTRL_REG register) is set the contents of this field specify the DWORD-aligned address (Address[31:02]) for the MSI.." rbitfld.long 0x4 0.--1. "RSVDP_0,Reserved for future use." "0,1,2,3" line.long 0x8 "MSI_CAP_OFF_08H_REG,For a function that supports a 32-bit message address. - bits[31:16] of this register represent the Extended Message Data. and - bits[15:0] of this register represent the Message Data For a function that supports a 64-bit message.." hexmask.long.word 0x8 16.--31. 1. "PCI_MSI_CAP_OFF_0AH,For a function that supports a 32-bit message address this field contains Extended Message Data (System-specified message data). For the MSI Capability structures without per-vector masking it must be implemented if the Extended.." hexmask.long.word 0x8 0.--15. 1. "PCI_MSI_CAP_OFF_08H,For a function that supports a 32-bit message address this field contains Message Data (System-specified message data). If the Message Enable bit (bit 16 of the PCI_MSI_CAP_ID_NEXT_CTRL_REG) is set the function sends a DWORD Memory.." line.long 0xC "MSI_CAP_OFF_0CH_REG,For a function that supports a 32-bit message address. this register contains the Mask Bits when the Per-Vector Masking Capable bit (bit 24 of PCI_MSI_CAP_ID_NEXT_CTRL_REG) is set. For a function that supports a 64-bit message.." hexmask.long.word 0xC 16.--31. 1. "PCI_MSI_CAP_OFF_0EH,For a function that supports a 32-bit message address this field contains the upper Mask Bits when the Per Vector Masking Capable bit (PCI_MSI_CAP_ID_NEXT_CTRL_REG.PCI_PVM_SUPPORT) is set. For a function that supports a 64-bit.." hexmask.long.word 0xC 0.--15. 1. "PCI_MSI_CAP_OFF_0CH,For a function that supports a 32-bit message address this field contains the lower Mask Bits when the Per Vector Masking Capable bit (PCI_MSI_CAP_ID_NEXT_CTRL_REG.PCI_PVM_SUPPORT) is set. For a function that supports a 64-bit.." line.long 0x10 "MSI_CAP_OFF_10H_REG,For a function that supports a 32-bit message address. this register contains the Pending Bits when the Per-Vector Masking Capable bit (bit 24 of PCI_MSI_CAP_ID_NEXT_CTRL_REG) is set. For a function that supports a 64-bit message.." hexmask.long 0x10 0.--31. 1. "PCI_MSI_CAP_OFF_10H,Used for MSI when the Per Vector Masking Capable bit (PCI_MSI_CAP_ID_NEXT_CTRL_REG.PCI_PVM_SUPPORT) is set. For 32-bit contains Pending Bits. For 64-bit contains Mask Bits. For a description of this standard PCIe register field see.." rgroup.long (0x14+0x50)++0x3 line.long 0x0 "MSI_CAP_OFF_14H_REG,Pending Bits Register for MSI. This register is used for a function that supports a 64-bit message address when the Per-Vector Masking Capable bit (bit 24 of PCI_MSI_CAP_ID_NEXT_CTRL_REG) is set." hexmask.long 0x0 0.--31. 1. "PCI_MSI_CAP_OFF_14H,Pending Bits. For each pending bit that is set the function has a pending associated message." tree.end tree "PF0_MSIX_CAP (PF MSI-X Capability Structure)" group.long (0x0+0xB0)++0xB line.long 0x0 "PCI_MSIX_CAP_ID_NEXT_CTRL_REG,MSI-X Capability ID. Next Pointer. Control Registers. For a description of this standard PCIe register. see the PCI Express Base Specification." bitfld.long 0x0 31. "PCI_MSIX_ENABLE,MSI-X Enable. For a description of this standard PCIe register field see the PCI Express Base Specification." "0,1" bitfld.long 0x0 30. "PCI_MSIX_FUNCTION_MASK,Function Mask. For a description of this standard PCIe register field see the PCI Express Base Specification. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" "0,1" rbitfld.long 0x0 27.--29. "RSVDP_27,Reserved for future use." "0,1,2,3,4,5,6,7" newline hexmask.long.word 0x0 16.--26. 1. "PCI_MSIX_TABLE_SIZE,MSI-X Table Size. For a description of this standard PCIe register field see the PCI Express Base Specification. SRIOV Note: All VFs in a single PF have the same value for 'MSI-X Table Size' (PCI_MSIX_TABLE_SIZE field in.." hexmask.long.byte 0x0 8.--15. 1. "PCI_MSIX_CAP_NEXT_OFFSET,MSI-X Next Capability Pointer. For a description of this standard PCIe register field see the PCI Express Base Specification. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN.." hexmask.long.byte 0x0 0.--7. 1. "PCI_MSIX_CAP_ID,MSI-X Capability ID. For a description of this standard PCIe register field see the PCI Express Base Specification." line.long 0x4 "MSIX_TABLE_OFFSET_REG,MSI-X Table Offset and BIR Register. For a description of this standard PCIe register. see the PCI Express Base Specification." hexmask.long 0x4 3.--31. 1. "PCI_MSIX_TABLE_OFFSET,MSI-X Table Offset. For a description of this standard PCIe register field see the PCI Express Base Specification. SRIOV Note: All VFs in a single PF have the same value for 'MSI-X Table Offset' (PCI_MSIX_TABLE_OFFSET field in.." bitfld.long 0x4 0.--2. "PCI_MSIX_BIR,MSI-X Table BAR Indicator Register Field. For a description of this standard PCIe register field see the PCI Express Base Specification. SRIOV Note: All VFs in a single PF have the same value for 'MSI-X Table BAR Indicator Register'.." "0,1,2,3,4,5,6,7" line.long 0x8 "MSIX_PBA_OFFSET_REG,MSI-X PBA Offset and BIR Register. For a description of this standard PCIe register. see the PCI Express Base Specification." hexmask.long 0x8 3.--31. 1. "PCI_MSIX_PBA_OFFSET,MSI-X PBA Offset. For a description of this standard PCIe register field see the PCI Express Base Specification. SRIOV Note: All VFs in a single PF have the same value for 'MSI-X PBA Offset' (PCI_MSIX_PBA_OFFSET field in.." bitfld.long 0x8 0.--2. "PCI_MSIX_PBA_BIR,MSI-X PBA BIR. For a description of this standard PCIe register field see the PCI Express Base Specification. SRIOV Note: All VFs in a single PF have the same value for 'MSI-X PBA BIR' (PCI_MSIX_PBA_BIR field in.." "0,1,2,3,4,5,6,7" tree.end tree "PF0_MSIX_CAP_DBI2 (DBI2 Shadow Block: PF MSI-X Capability Structure)" rgroup.long (0x0+0x10B0)++0x3 line.long 0x0 "SHADOW_PCI_MSIX_CAP_ID_NEXT_CTRL_REG,MSI-X Capability ID. Next Pointer. Control Registers. For a description of this standard PCIe register. see the PCI Express Base Specification." hexmask.long.byte 0x0 27.--31. 1. "RSVDP_27,Reserved for future use." hexmask.long.word 0x0 16.--26. 1. "PCI_MSIX_TABLE_SIZE,MSI-X Table Size in the shadow register. Note: The access attributes of this field are as follows: - Wire: No access - Dbi: No access - Dbi2: if (DBI_RO_WR_EN == 1) then R/W else R Note: This register field is sticky." hexmask.long.word 0x0 0.--15. 1. "RSVDP_0,Reserved for future use." group.long 0x4++0x7 line.long 0x0 "SHADOW_MSIX_TABLE_OFFSET_REG,MSI-X Table Offset and BIR Register. For a description of this standard PCIe register. see the PCI Express Base Specification." hexmask.long 0x0 3.--31. 1. "PCI_MSIX_TABLE_OFFSET,MSI-X Table Offset. For a description of this standard PCIe register field see the PCI Express Base Specification. Note: The access attributes of this field are as follows: - Wire: No access - Dbi: No access - Dbi2: if.." bitfld.long 0x0 0.--2. "PCI_MSIX_BIR,MSI-X Table BAR Indicator Register Field. For a description of this standard PCIe register field see the PCI Express Base Specification. Note: The access attributes of this field are as follows: - Wire: No access - Dbi: No access - Dbi2: if.." "?,?,if,?,?,?,?,?" line.long 0x4 "SHADOW_MSIX_PBA_OFFSET_REG,MSI-X PBA Offset and BIR Register. For a description of this standard PCIe register. see the PCI Express Base Specification." hexmask.long 0x4 3.--31. 1. "PCI_MSIX_PBA_OFFSET,MSI-X PBA Offset. For a description of this standard PCIe register field see the PCI Express Base Specification. Note: The access attributes of this field are as follows: - Wire: No access - Dbi: No access - Dbi2: if (DBI_RO_WR_EN ==.." bitfld.long 0x4 0.--2. "PCI_MSIX_PBA_BIR,MSI-X PBA BIR. For a description of this standard PCIe register field see the PCI Express Base Specification. Note: The access attributes of this field are as follows: - Wire: No access - Dbi: No access - Dbi2: if (DBI_RO_WR_EN == 1 &&.." "?,?,if,?,?,?,?,?" tree.end tree "PF0_DMA_CAP (DMA Port Logic Structure)" group.long (0x0+0xC8000)++0x3 line.long 0x0 "DMA_CTRL_DATA_ARB_PRIOR_OFF,DMA Arbitration Scheme for TRGT1 Interface. This register is used to control traffic priorities among various sources that are delivered to your application through TRGT1 where 0x0 represents the highest priority. - Non-DMA Rx.." hexmask.long.tbyte 0x0 12.--31. 1. "RSVDP_12,Reserved for future use." bitfld.long 0x0 9.--11. "RDBUFF_TRGT_WEIGHT,DMA Read Channel MWr Requests. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 6.--8. "RD_CTRL_TRGT_WEIGHT,DMA Read Channel MRd Requests. For LL element/descriptor access. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" "0,1,2,3,4,5,6,7" bitfld.long 0x0 3.--5. "WR_CTRL_TRGT_WEIGHT,DMA Write Channel MRd Requests. For DMA data requests and LL element/descriptor access. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 0.--2. "RTRGT1_WEIGHT,Non-DMA Rx Requests. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" "0,1,2,3,4,5,6,7" group.long (0x8+0xC8000)++0xB line.long 0x0 "DMA_CTRL_OFF,DMA Number of Channels Register." hexmask.long.byte 0x0 26.--31. 1. "RSVDP_26,Reserved for future use." bitfld.long 0x0 25. "DIS_C2W_CACHE_RD,Disable DMA Read Channels 'completion to memory write' context cache pre-fetch function. Note: For internal debugging only. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" "0,1" newline bitfld.long 0x0 24. "DIS_C2W_CACHE_WR,Disable DMA Write Channels 'completion to memory write' context cache pre-fetch function. Note: For internal debugging only. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" "0,1" hexmask.long.byte 0x0 20.--23. 1. "RSVDP_20,Reserved for future use." newline hexmask.long.byte 0x0 16.--19. 1. "NUM_DMA_RD_CHAN,Number of Read Channels. You can read this register to determine the number of read channels the DMA controller has been configured to support." hexmask.long.word 0x0 4.--15. 1. "RSVDP_4,Reserved for future use." newline hexmask.long.byte 0x0 0.--3. 1. "NUM_DMA_WR_CHAN,Number of Write Channels. You can read this register to determine the number of write channels the DMA controller has been configured to support." line.long 0x4 "DMA_WRITE_ENGINE_EN_OFF,DMA Write Engine Enable Register." hexmask.long.byte 0x4 24.--31. 1. "RSVDP_24,Reserved for future use." bitfld.long 0x4 23. "DMA_WRITE_ENGINE_EN_HSHAKE_CH7,Enable Handshake for DMA Write Engine Channel 7. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" "0,1" newline bitfld.long 0x4 22. "DMA_WRITE_ENGINE_EN_HSHAKE_CH6,Enable Handshake for DMA Write Engine Channel 6. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" "0,1" bitfld.long 0x4 21. "DMA_WRITE_ENGINE_EN_HSHAKE_CH5,Enable Handshake for DMA Write Engine Channel 5. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" "0,1" newline bitfld.long 0x4 20. "DMA_WRITE_ENGINE_EN_HSHAKE_CH4,Enable Handshake for DMA Write Engine Channel 4. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" "0,1" bitfld.long 0x4 19. "DMA_WRITE_ENGINE_EN_HSHAKE_CH3,Enable Handshake for DMA Write Engine Channel 3. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" "0,1" newline bitfld.long 0x4 18. "DMA_WRITE_ENGINE_EN_HSHAKE_CH2,Enable Handshake for DMA Write Engine Channel 2. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" "0,1" bitfld.long 0x4 17. "DMA_WRITE_ENGINE_EN_HSHAKE_CH1,Enable Handshake for DMA Write Engine Channel 1. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" "0,1" newline bitfld.long 0x4 16. "DMA_WRITE_ENGINE_EN_HSHAKE_CH0,Enable Handshake for DMA Write Engine Channel 0. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" "0,1" hexmask.long.word 0x4 1.--15. 1. "RSVDP_1,Reserved for future use." newline bitfld.long 0x4 0. "DMA_WRITE_ENGINE,DMA Write Engine Enable. - 1: Enable - 0: Disable (Soft Reset) For normal operation you must initially set this bit to '1' before any other software setup actions. You do not need to toggle or rewrite to this bit during normal.." "Disable,Enable" line.long 0x8 "DMA_WRITE_DOORBELL_OFF,DMA Write Doorbell Register." bitfld.long 0x8 31. "WR_STOP,Stop. Set in conjunction with the Doorbell Number field. The DMA write channel stops issuing requests sets the channel status to 'Stopped' and asserts the 'Abort' interrupt if it is enabled. Before setting the Stop bit you must read the.." "0,1" hexmask.long 0x8 3.--30. 1. "RSVDP_3,Reserved for future use." newline bitfld.long 0x8 0.--2. "WR_DOORBELL_NUM,Doorbell Number. You must write the channel number to this register to start the DMA write transfer for that channel. The DMA detects a write to this register field even if the value of this field does not change. You do not need to.." "0,1,2,3,4,5,6,7" group.long (0x18+0xC8000)++0x7 line.long 0x0 "DMA_WRITE_CHANNEL_ARB_WEIGHT_LOW_OFF,DMA Write Engine Channel Arbitration Weight Low Register. The 5-bit channel weight (for write channels 0-3) specifies the maximum number of TLP requests that the DMA can issue for that channel before it must return to.." hexmask.long.word 0x0 20.--31. 1. "RSVDP_20,Reserved for future use." hexmask.long.byte 0x0 15.--19. 1. "WRITE_CHANNEL3_WEIGHT,Channel 3 Weight. The weight is initialized by software before ringing the doorbell. The value is used by the channel weighted round robin arbiter to select the next channel read request. A value of '0' means that one TLP is issued.." newline hexmask.long.byte 0x0 10.--14. 1. "WRITE_CHANNEL2_WEIGHT,Channel 2 Weight. The weight is initialized by software before ringing the doorbell. The value is used by the channel weighted round robin arbiter to select the next channel read request. A value of '0' means that one TLP is issued.." hexmask.long.byte 0x0 5.--9. 1. "WRITE_CHANNEL1_WEIGHT,Channel 1 Weight. The weight is initialized by software before ringing the doorbell. The value is used by the channel weighted round robin arbiter to select the next channel read request. A value of '0' means that one TLP is issued.." newline hexmask.long.byte 0x0 0.--4. 1. "WRITE_CHANNEL0_WEIGHT,Channel 0 Weight. The weight is initialized by software before ringing the doorbell. The value is used by the channel weighted round robin arbiter to select the next channel read request. A value of '0' means that one TLP is issued.." line.long 0x4 "DMA_WRITE_CHANNEL_ARB_WEIGHT_HIGH_OFF,DMA Write Engine Channel Arbitration Weight High Register. The 5-bit channel weight (for write channels 4-7) specifies the maximum number of TLP requests that the DMA can issue for that channel before it must return.." hexmask.long.word 0x4 20.--31. 1. "RSVDP_20,Reserved for future use." hexmask.long.byte 0x4 15.--19. 1. "WRITE_CHANNEL7_WEIGHT,Channel 7 Weight. The weight is initialized by software before ringing the doorbell. The value is used by the channel weighted round robin arbiter to select the next channel read request. A value of '0' means that one TLP is issued.." newline hexmask.long.byte 0x4 10.--14. 1. "WRITE_CHANNEL6_WEIGHT,Channel 6 Weight. The weight is initialized by software before ringing the doorbell. The value is used by the channel weighted round robin arbiter to select the next channel read request. A value of '0' means that one TLP is issued.." hexmask.long.byte 0x4 5.--9. 1. "WRITE_CHANNEL5_WEIGHT,Channel 5 Weight. The weight is initialized by software before ringing the doorbell. The value is used by the channel weighted round robin arbiter to select the next channel read request. A value of '0' means that one TLP is issued.." newline hexmask.long.byte 0x4 0.--4. 1. "WRITE_CHANNEL4_WEIGHT,Channel 4 Weight. The weight is initialized by software before ringing the doorbell. The value is used by the channel weighted round robin arbiter to select the next channel read request. A value of '0' means that one TLP is issued.." group.long (0x2C+0xC8000)++0x7 line.long 0x0 "DMA_READ_ENGINE_EN_OFF,DMA Read Engine Enable Register." hexmask.long.byte 0x0 24.--31. 1. "RSVDP_24,Reserved for future use." bitfld.long 0x0 23. "DMA_READ_ENGINE_EN_HSHAKE_CH7,Enable Handshake for DMA Read Engine Channel 7. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" "0,1" newline bitfld.long 0x0 22. "DMA_READ_ENGINE_EN_HSHAKE_CH6,Enable Handshake for DMA Read Engine Channel 6. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" "0,1" bitfld.long 0x0 21. "DMA_READ_ENGINE_EN_HSHAKE_CH5,Enable Handshake for DMA Read Engine Channel 5. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" "0,1" newline bitfld.long 0x0 20. "DMA_READ_ENGINE_EN_HSHAKE_CH4,Enable Handshake for DMA Read Engine Channel 4. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" "0,1" bitfld.long 0x0 19. "DMA_READ_ENGINE_EN_HSHAKE_CH3,Enable Handshake for DMA Read Engine Channel 3. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" "0,1" newline bitfld.long 0x0 18. "DMA_READ_ENGINE_EN_HSHAKE_CH2,Enable Handshake for DMA Read Engine Channel 2. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" "0,1" bitfld.long 0x0 17. "DMA_READ_ENGINE_EN_HSHAKE_CH1,Enable Handshake for DMA Read Engine Channel 1. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" "0,1" newline bitfld.long 0x0 16. "DMA_READ_ENGINE_EN_HSHAKE_CH0,Enable Handshake for DMA Read Engine Channel 0. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" "0,1" hexmask.long.word 0x0 1.--15. 1. "RSVDP_1,Reserved for future use." newline bitfld.long 0x0 0. "DMA_READ_ENGINE,DMA Read Engine Enable. - 1: Enable - 0: Disable (Soft Reset) For normal operation you must initially set this bit to '1' before any other software setup actions. You do not need to toggle or rewrite to this bit during normal operation." "Disable,Enable" line.long 0x4 "DMA_READ_DOORBELL_OFF,DMA Read Doorbell Register." bitfld.long 0x4 31. "RD_STOP,Stop. Set in conjunction with the Doorbell Number field. The DMA read channel stops issuing requests sets the channel status to 'Stopped' and asserts the 'Abort' interrupt if it is enabled. Before setting the Stop bit you must read the channel.." "0,1" hexmask.long 0x4 3.--30. 1. "RSVDP_3,Reserved for future use." newline bitfld.long 0x4 0.--2. "RD_DOORBELL_NUM,Doorbell Number. You must write 0x0 to this register to start the DMA read transfer for that channel. The DMA detects a write to this register field even if the value of this field does not change. The range of this field is 0x0 to 0x7.." "0,1,2,3,4,5,6,7" group.long (0x38+0xC8000)++0x7 line.long 0x0 "DMA_READ_CHANNEL_ARB_WEIGHT_LOW_OFF,DMA Read Engine Channel Arbitration Weight Low Register. The 5-bit channel weight (for read channels 0-3) specifies the maximum number of TLP requests that the DMA can issue for that channel before it must return to.." hexmask.long.word 0x0 20.--31. 1. "RSVDP_20,Reserved for future use." hexmask.long.byte 0x0 15.--19. 1. "READ_CHANNEL3_WEIGHT,Channel 3 Weight. The weight is initialized by software before ringing the doorbell. The value is used by the channel weighted round robin arbiter to select the next channel read request. Note: The access attributes of this field are.." newline hexmask.long.byte 0x0 10.--14. 1. "READ_CHANNEL2_WEIGHT,Channel 2 Weight. The weight is initialized by software before ringing the doorbell. The value is used by the channel weighted round robin arbiter to select the next channel read request. Note: The access attributes of this field are.." hexmask.long.byte 0x0 5.--9. 1. "READ_CHANNEL1_WEIGHT,Channel 1 Weight. The weight is initialized by software before ringing the doorbell. The value is used by the channel weighted round robin arbiter to select the next channel read request. Note: The access attributes of this field are.." newline hexmask.long.byte 0x0 0.--4. 1. "READ_CHANNEL0_WEIGHT,Channel 0 Weight. The weight is initialized by software before ringing the doorbell. The value is used by the channel weighted round robin arbiter to select the next channel read request. Note: The access attributes of this field are.." line.long 0x4 "DMA_READ_CHANNEL_ARB_WEIGHT_HIGH_OFF,DMA Read Engine Channel Arbitration Weight High Register. The 5-bit channel weight (for read channels 4-7) specifies the maximum number of TLP requests that the DMA can issue for that channel before it must return to.." hexmask.long.word 0x4 20.--31. 1. "RSVDP_20,Reserved for future use." hexmask.long.byte 0x4 15.--19. 1. "READ_CHANNEL7_WEIGHT,Channel 7 Weight. The weight is initialized by software before ringing the doorbell. The value is used by the channel weighted round robin arbiter to select the next channel read request. Note: The access attributes of this field are.." newline hexmask.long.byte 0x4 10.--14. 1. "READ_CHANNEL6_WEIGHT,Channel 6 Weight. The weight is initialized by software before ringing the doorbell. The value is used by the channel weighted round robin arbiter to select the next channel read request. Note: The access attributes of this field are.." hexmask.long.byte 0x4 5.--9. 1. "READ_CHANNEL5_WEIGHT,Channel 5 Weight. The weight is initialized by software before ringing the doorbell. The value is used by the channel weighted round robin arbiter to select the next channel read request. Note: The access attributes of this field are.." newline hexmask.long.byte 0x4 0.--4. 1. "READ_CHANNEL4_WEIGHT,Channel 4 Weight. The weight is initialized by software before ringing the doorbell. The value is used by the channel weighted round robin arbiter to select the next channel read request. Note: The access attributes of this field are.." group.long (0x4C+0xC8000)++0x3 line.long 0x0 "DMA_WRITE_INT_STATUS_OFF,DMA Write Interrupt Status Register." hexmask.long.byte 0x0 24.--31. 1. "RSVDP_24,Reserved for future use." hexmask.long.byte 0x0 16.--23. 1. "WR_ABORT_INT_STATUS,Abort Interrupt Status. The DMA write channel has detected an error or you manually stopped the transfer as described in 'Error Handling Assistance by Remote Software'. Each bit corresponds to a DMA channel. Bit [0] corresponds to.." newline hexmask.long.byte 0x0 8.--15. 1. "RSVDP_8,Reserved for future use." hexmask.long.byte 0x0 0.--7. 1. "WR_DONE_INT_STATUS,Done Interrupt Status. The DMA write channel has successfully completed the DMA transfer. For more details see 'Interrupts and Error Handling'. Each bit corresponds to a DMA channel. Bit [0] corresponds to channel 0. - Enabling: For.." group.long (0x54+0xC8000)++0x7 line.long 0x0 "DMA_WRITE_INT_MASK_OFF,DMA Write Interrupt Mask Register." hexmask.long.byte 0x0 24.--31. 1. "RSVDP_24,Reserved for future use." hexmask.long.byte 0x0 16.--23. 1. "WR_ABORT_INT_MASK,Abort Interrupt Mask. Prevents the Abort interrupt status field in the DMA write interrupt status register from asserting the edma_int output. Each bit corresponds to a DMA channel. Bit [0] corresponds to channel 0. Note: The access.." newline hexmask.long.byte 0x0 8.--15. 1. "RSVDP_8,Reserved for future use." hexmask.long.byte 0x0 0.--7. 1. "WR_DONE_INT_MASK,Done Interrupt Mask. Prevents the Done interrupt status field in the DMA write interrupt status register from asserting the edma_int output. Each bit corresponds to a DMA channel. Bit [0] corresponds to channel 0. Note: The access.." line.long 0x4 "DMA_WRITE_INT_CLEAR_OFF,DMA Write Interrupt Clear Register." hexmask.long.byte 0x4 24.--31. 1. "RSVDP_24,Reserved for future use." hexmask.long.byte 0x4 16.--23. 1. "WR_ABORT_INT_CLEAR,Abort Interrupt Clear. You must write a 1'b1 to clear the corresponding bit in the Abort interrupt status field of the DMA write interrupt status register. Each bit corresponds to a DMA channel. Bit [0] corresponds to channel 0. Note:.." newline hexmask.long.byte 0x4 8.--15. 1. "RSVDP_8,Reserved for future use." hexmask.long.byte 0x4 0.--7. 1. "WR_DONE_INT_CLEAR,Done Interrupt Clear. You must write a 1'b1 to clear the corresponding bit in the Done interrupt status field of the DMA write interrupt status register. Each bit corresponds to a DMA channel. Bit [0] corresponds to channel 0. Note:.." rgroup.long (0x5C+0xC8000)++0x3 line.long 0x0 "DMA_WRITE_ERR_STATUS_OFF,DMA Write Error Status Register" hexmask.long.byte 0x0 24.--31. 1. "RSVDP_24,Reserved for future use." hexmask.long.byte 0x0 16.--23. 1. "LINKLIST_ELEMENT_FETCH_ERR_DETECT,Linked List Element Fetch Error Detected. The DMA write channel has received an error response from the AXI bus (or TRGT1 interface when the AXI Bridge is not used) while reading a linked list element from local memory." newline hexmask.long.byte 0x0 8.--15. 1. "RSVDP_8,Reserved for future use." hexmask.long.byte 0x0 0.--7. 1. "APP_READ_ERR_DETECT,Application Read Error Detected. The DMA write channel has received an error response from the AXI bus (or TRGT1 interface when the AXI Bridge is not used) while reading data from it. Each bit corresponds to a DMA channel. Bit [0].." group.long (0x60+0xC8000)++0x1F line.long 0x0 "DMA_WRITE_DONE_IMWR_LOW_OFF,DMA Write Done IMWr Address Low Register." hexmask.long 0x0 0.--31. 1. "DMA_WRITE_DONE_LOW_REG,The DMA uses this field to generate bits [31:0] of the address field for the Done IMWr TLP. Bits [1:0] must be '00' as this address must be dword aligned. Note: The access attributes of this field are as follows: - Wire: No access." line.long 0x4 "DMA_WRITE_DONE_IMWR_HIGH_OFF,DMA Write Done IMWr Interrupt Address High Register." hexmask.long 0x4 0.--31. 1. "DMA_WRITE_DONE_HIGH_REG,The DMA uses this field to generate bits [63:32] of the address field for the Done IMWr TLP. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" line.long 0x8 "DMA_WRITE_ABORT_IMWR_LOW_OFF,DMA Write Abort IMWr Address Low Register." hexmask.long 0x8 0.--31. 1. "DMA_WRITE_ABORT_LOW_REG,The DMA uses this field to generate bits [31:0] of the address field for the Abort IMWr TLP it generates. Bits [1:0] must be '00' as this address must be dword aligned. Note: The access attributes of this field are as follows: -.." line.long 0xC "DMA_WRITE_ABORT_IMWR_HIGH_OFF,DMA Write Abort IMWr Address High Register." hexmask.long 0xC 0.--31. 1. "DMA_WRITE_ABORT_HIGH_REG,The DMA uses this field to generate bits [63:32] of the address field for the Abort IMWr TLP. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" line.long 0x10 "DMA_WRITE_CH01_IMWR_DATA_OFF,DMA Write Channel 1 and 0 IMWr Data Register." hexmask.long.word 0x10 16.--31. 1. "WR_CHANNEL_1_DATA,The DMA uses this field to generate the data field for the Done or Abort IMWr TLPs it generates for write channel 1. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" hexmask.long.word 0x10 0.--15. 1. "WR_CHANNEL_0_DATA,The DMA uses this field to generate the data field for the Done or Abort IMWr TLPs it generates for write channel 0. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" line.long 0x14 "DMA_WRITE_CH23_IMWR_DATA_OFF,DMA Write Channel 3 and 2 IMWr Data Register." hexmask.long.word 0x14 16.--31. 1. "WR_CHANNEL_3_DATA,The DMA uses this field to generate the data field for the Done or Abort IMWr TLPs it generates for write channel 3. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" hexmask.long.word 0x14 0.--15. 1. "WR_CHANNEL_2_DATA,The DMA uses this field to generate the data field for the Done or Abort IMWr TLPs it generates for write channel 2. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" line.long 0x18 "DMA_WRITE_CH45_IMWR_DATA_OFF,DMA Write Channel 5 and 4 IMWr Data Register." hexmask.long.word 0x18 16.--31. 1. "WR_CHANNEL_5_DATA,The DMA uses this field to generate the data field for the Done or Abort IMWr TLPs it generates for write channel 5. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" hexmask.long.word 0x18 0.--15. 1. "WR_CHANNEL_4_DATA,The DMA uses this field to generate the data field for the Done or Abort IMWr TLPs it generates for write channel 4. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" line.long 0x1C "DMA_WRITE_CH67_IMWR_DATA_OFF,DMA Write Channel 7 and 6 IMWr Data Register." hexmask.long.word 0x1C 16.--31. 1. "WR_CHANNEL_7_DATA,The DMA uses this field to generate the data field for the Done or Abort IMWr TLPs it generates for write channel 7. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" hexmask.long.word 0x1C 0.--15. 1. "WR_CHANNEL_6_DATA,The DMA uses this field to generate the data field for the Done or Abort IMWr TLPs it generates for write channel 6. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" group.long (0x90+0xC8000)++0x3 line.long 0x0 "DMA_WRITE_LINKED_LIST_ERR_EN_OFF,DMA Write Linked List Error Enable Register. The LIE and RIE bits in the LL element enable the channel 'done' interrupts (local and remote). The LLLAIE and LLRAIE bits enable the channel 'abort' interrupts (local and.." hexmask.long.byte 0x0 24.--31. 1. "RSVDP_24,Reserved for future use." hexmask.long.byte 0x0 16.--23. 1. "WR_CHANNEL_LLLAIE,Write Channel LL Local Abort Interrupt Enable (LLLAIE). You enable the write channel local abort interrupt through this bit. The LIE and RIE bits in the LL element enable the write channel done interrupts. Each bit corresponds to a DMA.." newline hexmask.long.byte 0x0 8.--15. 1. "RSVDP_8,Reserved for future use." hexmask.long.byte 0x0 0.--7. 1. "WR_CHANNEL_LLRAIE,Write Channel LL Remote Abort Interrupt Enable (LLRAIE). You enable the write channel remote abort interrupt through this bit. The LIE and RIE bits in the LL element enable the write channel done interrupts. Each bit corresponds to a.." group.long (0xA0+0xC8000)++0x3 line.long 0x0 "DMA_READ_INT_STATUS_OFF,DMA Read Interrupt Status Register." hexmask.long.byte 0x0 24.--31. 1. "RSVDP_24,Reserved for future use." hexmask.long.byte 0x0 16.--23. 1. "RD_ABORT_INT_STATUS,Abort Interrupt Status. The DMA read channel has detected an error or you manually stopped the transfer as described in 'Stopping the DMA Transfer (Software Stop)'. Each bit corresponds to a DMA channel. Bit [0] corresponds to.." newline hexmask.long.byte 0x0 8.--15. 1. "RSVDP_8,Reserved for future use." hexmask.long.byte 0x0 0.--7. 1. "RD_DONE_INT_STATUS,Done Interrupt Status. The DMA read channel has successfully completed the DMA read transfer. Each bit corresponds to a DMA channel. Bit [0] corresponds to channel 0. - Enabling: For details see 'Interrupts and Error Handling'. -.." group.long (0xA8+0xC8000)++0x7 line.long 0x0 "DMA_READ_INT_MASK_OFF,DMA Read Interrupt Mask Register." hexmask.long.byte 0x0 24.--31. 1. "RSVDP_24,Reserved for future use." hexmask.long.byte 0x0 16.--23. 1. "RD_ABORT_INT_MASK,Abort Interrupt Mask. Prevents the Abort interrupt status field in the DMA read interrupt status register from asserting the edma_int output. Each bit corresponds to a DMA channel. Bit [0] corresponds to channel 0. Note: The access.." newline hexmask.long.byte 0x0 8.--15. 1. "RSVDP_8,Reserved for future use." hexmask.long.byte 0x0 0.--7. 1. "RD_DONE_INT_MASK,Done Interrupt Mask. Prevents the Done interrupt status field in the DMA read interrupt status register from asserting the edma_int output. Each bit corresponds to a DMA channel. Bit [0] corresponds to channel 0. Note: The access.." line.long 0x4 "DMA_READ_INT_CLEAR_OFF,DMA Read Interrupt Clear Register." hexmask.long.byte 0x4 24.--31. 1. "RSVDP_24,Reserved for future use." hexmask.long.byte 0x4 16.--23. 1. "RD_ABORT_INT_CLEAR,Abort Interrupt Clear. You must write a 1'b1 to clear the corresponding bit in the Abort interrupt status field of the DMA read interrupt status register. Each bit corresponds to a DMA channel. Bit [0] corresponds to channel 0. Note:.." newline hexmask.long.byte 0x4 8.--15. 1. "RSVDP_8,Reserved for future use." hexmask.long.byte 0x4 0.--7. 1. "RD_DONE_INT_CLEAR,Done Interrupt Clear. You must write a 1'b1 to clear the corresponding bit in the Done interrupt status field of the DMA read interrupt status register. Each bit corresponds to a DMA channel. Bit [0] corresponds to channel 0. Note:.." rgroup.long (0xB4+0xC8000)++0x7 line.long 0x0 "DMA_READ_ERR_STATUS_LOW_OFF,DMA Read Error Status Low Register." hexmask.long.byte 0x0 24.--31. 1. "RSVDP_24,Reserved for future use." hexmask.long.byte 0x0 16.--23. 1. "LINK_LIST_ELEMENT_FETCH_ERR_DETECT,Linked List Element Fetch Error Detected. - The DMA read channel has received an error response from the AXI bus while reading a linked list element from local memory. Each bit corresponds to a DMA channel. Bit [0].." newline hexmask.long.byte 0x0 8.--15. 1. "RSVDP_8,Reserved for future use." hexmask.long.byte 0x0 0.--7. 1. "APP_WR_ERR_DETECT,Application Write Error Detected. The DMA read channel has received an error response from the AXI bus (or TRGT1 interface when the AXI Bridge is not used) while writing data to it. This error is fatal. You must restart the transfer.." line.long 0x4 "DMA_READ_ERR_STATUS_HIGH_OFF,DMA Read Error Status High Register." hexmask.long.byte 0x4 24.--31. 1. "DATA_POISIONING,Data Poisoning. The DMA read channel has detected data poisoning in the completion from the remote device (in response to the MRd request). The DMA read channel will drop the completion and then be halted. The CX_FLT_MASK_UR_POIS filter.." hexmask.long.byte 0x4 16.--23. 1. "CPL_TIMEOUT,Completion Time Out. The DMA read channel has timed-out while waiting for the remote device to respond to the MRd request or a malformed CplD has been received. For more details see 'Linked List Mode'. Each bit corresponds to a DMA channel." newline hexmask.long.byte 0x4 8.--15. 1. "CPL_ABORT,Completer Abort. The DMA read channel has received a PCIe completer abort completion status from the remote device in response to the MRd request. For more details see 'Linked List Mode'. Each bit corresponds to a DMA channel. Bit [0].." hexmask.long.byte 0x4 0.--7. 1. "UNSUPPORTED_REQ,Unsupported Request. The DMA read channel has received a PCIe unsupported request completion status from the remote device in response to the MRd request. For more details see 'Linked List Mode'. Each bit corresponds to a DMA channel." group.long (0xC4+0xC8000)++0x3 line.long 0x0 "DMA_READ_LINKED_LIST_ERR_EN_OFF,DMA Read Linked List Error Enable Register. The LIE and RIE bits in the LL element enable the channel 'done' interrupts (local and remote). The LLLAIE and LLRAIE bits enable the channel 'abort' interrupts (local and remote)." hexmask.long.byte 0x0 24.--31. 1. "RSVDP_24,Reserved for future use." hexmask.long.byte 0x0 16.--23. 1. "RD_CHANNEL_LLLAIE,Read Channel LL Local Abort Interrupt Enable (LLLAIE). You enable the read channel Local Abort interrupt through this bit. The LIE and RIE bits in the LL element enable the read channel done interrupts. Each bit corresponds to a DMA.." newline hexmask.long.byte 0x0 8.--15. 1. "RSVDP_8,Reserved for future use." hexmask.long.byte 0x0 0.--7. 1. "RD_CHANNEL_LLRAIE,Read Channel LL Remote Abort Interrupt Enable (LLRAIE). You enable the read channel Remote Abort interrupt through this bit. The LIE and RIE bits in the LL element enable the read channel done interrupts. Each bit corresponds to a DMA.." group.long (0xCC+0xC8000)++0x1F line.long 0x0 "DMA_READ_DONE_IMWR_LOW_OFF,DMA Read Done IMWr Address Low Register." hexmask.long 0x0 0.--31. 1. "DMA_READ_DONE_LOW_REG,The DMA uses this field to generate bits [31:0] of the address field for the Done IMWr TLP. Bits [1:0] must be '00' as this address must be dword aligned. Note: The access attributes of this field are as follows: - Wire: No access." line.long 0x4 "DMA_READ_DONE_IMWR_HIGH_OFF,DMA Read Done IMWr Address High Register." hexmask.long 0x4 0.--31. 1. "DMA_READ_DONE_HIGH_REG,The DMA uses this field to generate bits [63:32] of the address field for the Done IMWr TLP. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" line.long 0x8 "DMA_READ_ABORT_IMWR_LOW_OFF,DMA Read Abort IMWr Address Low Register." hexmask.long 0x8 0.--31. 1. "DMA_READ_ABORT_LOW_REG,The DMA uses this field to generate bits [31:0] of the address field for the Abort IMWr TLP. Bits [1:0] must be '00' as this address must be dword aligned. Note: The access attributes of this field are as follows: - Wire: No.." line.long 0xC "DMA_READ_ABORT_IMWR_HIGH_OFF,DMA Read Abort IMWr Address High Register." hexmask.long 0xC 0.--31. 1. "DMA_READ_ABORT_HIGH_REG,The DMA uses this field to generate bits [63:32] of the address field for the Abort IMWr TLP. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" line.long 0x10 "DMA_READ_CH01_IMWR_DATA_OFF,DMA Read Channel 1 and 0 IMWr Data Register." hexmask.long.word 0x10 16.--31. 1. "RD_CHANNEL_1_DATA,The DMA uses this field to generate the data field for the Done or Abort IMWr TLPs it generates for read channel 1. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" hexmask.long.word 0x10 0.--15. 1. "RD_CHANNEL_0_DATA,The DMA uses this field to generate the data field for the Done or Abort IMWr TLPs it generates for read channel 0. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" line.long 0x14 "DMA_READ_CH23_IMWR_DATA_OFF,DMA Read Channel 3 and 2 IMWr Data Register." hexmask.long.word 0x14 16.--31. 1. "RD_CHANNEL_3_DATA,The DMA uses this field to generate the data field for the Done or Abort IMWr TLPs it generates for read channel 3. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" hexmask.long.word 0x14 0.--15. 1. "RD_CHANNEL_2_DATA,The DMA uses this field to generate the data field for the Done or Abort IMWr TLPs it generates for read channel 2. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" line.long 0x18 "DMA_READ_CH45_IMWR_DATA_OFF,DMA Read Channel 5 and 4 IMWr Data Register." hexmask.long.word 0x18 16.--31. 1. "RD_CHANNEL_5_DATA,The DMA uses this field to generate the data field for the Done or Abort IMWr TLPs it generates for read channel 5. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" hexmask.long.word 0x18 0.--15. 1. "RD_CHANNEL_4_DATA,The DMA uses this field to generate the data field for the Done or Abort IMWr TLPs it generates for read channel 4. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" line.long 0x1C "DMA_READ_CH67_IMWR_DATA_OFF,DMA Read Channel 7 and 6 IMWr Data Register." hexmask.long.word 0x1C 16.--31. 1. "RD_CHANNEL_7_DATA,The DMA uses this field to generate the data field for the Done or Abort IMWr TLPs it generates for read channel 7. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" hexmask.long.word 0x1C 0.--15. 1. "RD_CHANNEL_6_DATA,The DMA uses this field to generate the data field for the Done or Abort IMWr TLPs it generates for read channel 6. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" rgroup.long (0x108+0xC8000)++0x7 line.long 0x0 "DMA_WRITE_ENGINE_HSHAKE_CNT_LOW_OFF,DMA Write Engine Handshake Counter Channel 0/1/2/3 Register." bitfld.long 0x0 29.--31. "RSVDP_29,Reserved for future use." "0,1,2,3,4,5,6,7" hexmask.long.byte 0x0 24.--28. 1. "DMA_WRITE_ENGINE_HSHAKE_CNT_CH3,DMA handshake counter for DMA Write Engine Channel 3. If CC_DMA_HSHAKE =1 the data transfer in Linked List mode starts only when the counter is non-zero." newline bitfld.long 0x0 21.--23. "RSVDP_21,Reserved for future use." "0,1,2,3,4,5,6,7" hexmask.long.byte 0x0 16.--20. 1. "DMA_WRITE_ENGINE_HSHAKE_CNT_CH2,DMA handshake counter for DMA Write Engine Channel 2. If CC_DMA_HSHAKE =1 the data transfer in Linked List mode starts only when the counter is non-zero." newline bitfld.long 0x0 13.--15. "RSVDP_13,Reserved for future use." "0,1,2,3,4,5,6,7" hexmask.long.byte 0x0 8.--12. 1. "DMA_WRITE_ENGINE_HSHAKE_CNT_CH1,DMA handshake counter for DMA Write Engine Channel 1. If CC_DMA_HSHAKE =1 the data transfer in Linked List mode starts only when the counter is non-zero." newline bitfld.long 0x0 5.--7. "RSVDP_5,Reserved for future use." "0,1,2,3,4,5,6,7" hexmask.long.byte 0x0 0.--4. 1. "DMA_WRITE_ENGINE_HSHAKE_CNT_CH0,DMA handshake counter for DMA Write Engine Channel 0. If CC_DMA_HSHAKE =1 the data transfer in Linked List mode starts only when the counter is non-zero." line.long 0x4 "DMA_WRITE_ENGINE_HSHAKE_CNT_HIGH_OFF,DMA Write Engine Handshake Counter Channel 4/5/6/7 Register." bitfld.long 0x4 29.--31. "RSVDP_29,Reserved for future use." "0,1,2,3,4,5,6,7" hexmask.long.byte 0x4 24.--28. 1. "DMA_WRITE_ENGINE_HSHAKE_CNT_CH7,DMA handshake counter for DMA Write Engine Channel 7. If CC_DMA_HSHAKE =1 the data transfer in Linked List mode starts only when the counter is non-zero." newline bitfld.long 0x4 21.--23. "RSVDP_21,Reserved for future use." "0,1,2,3,4,5,6,7" hexmask.long.byte 0x4 16.--20. 1. "DMA_WRITE_ENGINE_HSHAKE_CNT_CH6,DMA handshake counter for DMA Write Engine Channel 6. If CC_DMA_HSHAKE =1 the data transfer in Linked List mode starts only when the counter is non-zero." newline bitfld.long 0x4 13.--15. "RSVDP_13,Reserved for future use." "0,1,2,3,4,5,6,7" hexmask.long.byte 0x4 8.--12. 1. "DMA_WRITE_ENGINE_HSHAKE_CNT_CH5,DMA handshake counter for DMA Write Engine Channel 5. If CC_DMA_HSHAKE =1 the data transfer in Linked List mode starts only when the counter is non-zero." newline bitfld.long 0x4 5.--7. "RSVDP_5,Reserved for future use." "0,1,2,3,4,5,6,7" hexmask.long.byte 0x4 0.--4. 1. "DMA_WRITE_ENGINE_HSHAKE_CNT_CH4,DMA handshake counter for DMA Write Engine Channel 4. If CC_DMA_HSHAKE =1 the data transfer in Linked List mode starts only when the counter is non-zero." rgroup.long (0x118+0xC8000)++0x7 line.long 0x0 "DMA_READ_ENGINE_HSHAKE_CNT_LOW_OFF,DMA Read Engine Handshake Counter Channel 0/1/2/3 Register." bitfld.long 0x0 29.--31. "RSVDP_29,Reserved for future use." "0,1,2,3,4,5,6,7" hexmask.long.byte 0x0 24.--28. 1. "DMA_READ_ENGINE_HSHAKE_CNT_CH3,DMA handshake counter for DMA Read Engine Channel 3. If CC_DMA_HSHAKE =1 the data transfer in Linked List mode starts only when the counter is non-zero." newline bitfld.long 0x0 21.--23. "RSVDP_21,Reserved for future use." "0,1,2,3,4,5,6,7" hexmask.long.byte 0x0 16.--20. 1. "DMA_READ_ENGINE_HSHAKE_CNT_CH2,DMA handshake counter for DMA Read Engine Channel 2. If CC_DMA_HSHAKE =1 the data transfer in Linked List mode starts only when the counter is non-zero." newline bitfld.long 0x0 13.--15. "RSVDP_13,Reserved for future use." "0,1,2,3,4,5,6,7" hexmask.long.byte 0x0 8.--12. 1. "DMA_READ_ENGINE_HSHAKE_CNT_CH1,DMA handshake counter for DMA Read Engine Channel 1. If CC_DMA_HSHAKE =1 the data transfer in Linked List mode starts only when the counter is non-zero." newline bitfld.long 0x0 5.--7. "RSVDP_5,Reserved for future use." "0,1,2,3,4,5,6,7" hexmask.long.byte 0x0 0.--4. 1. "DMA_READ_ENGINE_HSHAKE_CNT_CH0,DMA handshake counter for DMA Read Engine Channel 0. If CC_DMA_HSHAKE =1 the data transfer in Linked List mode starts only when the counter is non-zero." line.long 0x4 "DMA_READ_ENGINE_HSHAKE_CNT_HIGH_OFF,DMA Read Engine Handshake Counter Channel 4/5/6/7 Register." bitfld.long 0x4 29.--31. "RSVDP_29,Reserved for future use." "0,1,2,3,4,5,6,7" hexmask.long.byte 0x4 24.--28. 1. "DMA_READ_ENGINE_HSHAKE_CNT_CH7,DMA handshake counter for DMA Read Engine Channel 7. If CC_DMA_HSHAKE =1 the data transfer in Linked List mode starts only when the counter is non-zero." newline bitfld.long 0x4 21.--23. "RSVDP_21,Reserved for future use." "0,1,2,3,4,5,6,7" hexmask.long.byte 0x4 16.--20. 1. "DMA_READ_ENGINE_HSHAKE_CNT_CH6,DMA handshake counter for DMA Read Engine Channel 6. If CC_DMA_HSHAKE =1 the data transfer in Linked List mode starts only when the counter is non-zero." newline bitfld.long 0x4 13.--15. "RSVDP_13,Reserved for future use." "0,1,2,3,4,5,6,7" hexmask.long.byte 0x4 8.--12. 1. "DMA_READ_ENGINE_HSHAKE_CNT_CH5,DMA handshake counter for DMA Read Engine Channel 5. If CC_DMA_HSHAKE =1 the data transfer in Linked List mode starts only when the counter is non-zero." newline bitfld.long 0x4 5.--7. "RSVDP_5,Reserved for future use." "0,1,2,3,4,5,6,7" hexmask.long.byte 0x4 0.--4. 1. "DMA_READ_ENGINE_HSHAKE_CNT_CH4,DMA handshake counter for DMA Read Engine Channel 4. If CC_DMA_HSHAKE =1 the data transfer in Linked List mode starts only when the counter is non-zero." repeat 8. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 )(list 0x0 0x200 0x400 0x600 0x800 0xA00 0xC00 0xE00 ) group.long ($2+0x200+0xC8000)++0x3 line.long 0x0 "DMA_CH_CONTROL1_OFF_WRCH_$1,DMA Write Channel Control 1 Register." bitfld.long 0x0 30.--31. "DMA_AT,Address Translation TLP Header Bit (AT) The DMA uses this TLP header field when generating MRd/MWr (not IMWr) TLPs. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" "0,1,2,3" bitfld.long 0x0 27.--29. "DMA_TC,Traffic Class TLP Header Bit (TC) The DMA uses this TLP header field when generating MRd/MWr (not IMWr) TLPs. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 26. "DMA_RESERVED5,Reserved. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" "0,1" bitfld.long 0x0 25. "DMA_RO,Relaxed Ordering TLP Header Bit (RO) The DMA uses this TLP header field when generating MRd/MWr (not IMWr) TLPs. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" "0,1" newline bitfld.long 0x0 24. "DMA_NS_SRC,Source No Snoop TLP Header Bit (DMA_NS_SRC). The DMA uses this TLP header field when generating MRd (SAR addressing space) (not IMWr) TLPs. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" "0,1" bitfld.long 0x0 23. "DMA_NS_DST,Destination No Snoop TLP Header Bit (DMA_NS_DST). The DMA uses this TLP header field when generating MWr (DAR addressing space) (not IMWr) TLPs. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" "0,1" newline bitfld.long 0x0 22. "DMA_MEM_TYPE,Master AXI ACE-Lite Cache Coherency Control. This field sets the DMA channel memory type of the address space of the data transfer as follows: - 0x0:peripheral type - 0x1:memory type For more details see 'ACE-Lite Features and Limitations'.." "peripheral type,memory type" hexmask.long.byte 0x0 17.--21. 1. "DMA_RESERVED2,Reserved. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" newline hexmask.long.byte 0x0 12.--16. 1. "DMA_FUNC_NUM,Function Number (FN). The controller uses this field when generating the requester ID for the MRd/MWr DMA TLP. When you have enabled SR-IOV then this field is ignored if you have set the VFE field in the 'DMA Write Channel Control 2.." bitfld.long 0x0 10.--11. "DMA_RESERVED1,Reserved. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" "0,1,2,3" newline bitfld.long 0x0 9. "LLE,Linked List Enable (LLE). - 0: Disable linked list operation - 1: Enable linked list operation Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" "Disable linked list operation,Enable linked list operation" bitfld.long 0x0 8. "CCS,Consumer Cycle State (CCS). Used in linked list mode only. It is used to synchronize the producer (software) and the consumer (DMA). For more details see 'PCS-CCS-CB-TCB Producer-Consumer Synchronization'. You must initialize this bit. The DMA.." "0,1" newline bitfld.long 0x0 7. "DMA_RESERVED0,Reserved. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" "0,1" bitfld.long 0x0 5.--6. "CS,Channel Status (CS). The channel status bits identify the current operational state of the DMA channel. The operation state encoding for each DMA channel is a s follows: - 00: Reserved - 01: Running. This channel is active and transferring data. - 10:.." "Reserved,Running,?,?" newline bitfld.long 0x0 4. "RIE,Remote Interrupt Enable (RIE). You must set this bit to enable the generation of the Done or Abort Remote interrupts. For more details see 'Interrupts and Error Handling'. In LL mode the DMA overwrites this with the RIE of the LL element. The RIE.." "0,1" bitfld.long 0x0 3. "LIE,Local Interrupt Enable (LIE). You must set this bit to enable the generation of the Done or Abort Local interrupts. For more details see 'Interrupts and Error Handling'. In LL mode the DMA overwrites this with the LIE of the LL element. The LIE bit.." "0,1" newline bitfld.long 0x0 2. "LLP,Load Link Pointer (LLP). Used in linked list mode only. Indicates that this linked list element is a link element and its LL element pointer dwords are pointing to the next (non-contiguous) element. The DMA loads this field with the LLP of the.." "0,1" bitfld.long 0x0 1. "TCB,Toggle Cycle Bit (TCB). Indicates to the DMA to toggle its interpretation of the CB. Used in linked list mode only. It is used to synchronize the producer (software) and the consumer (DMA). For more details see 'PCS-CCS-CB-TCB Producer-Consumer.." "0,1" newline bitfld.long 0x0 0. "CB,Cycle Bit (CB). Used in linked list mode only. It is used to synchronize the producer (software) and the consumer (DMA). For more details see 'PCS-CCS-CB-TCB Producer-Consumer Synchronization'. The DMA loads this field with the CB of the linked list.." "0,1" repeat.end repeat 8. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 )(list 0x0 0x200 0x400 0x600 0x800 0xA00 0xC00 0xE00 ) group.long ($2+0x208+0xC8000)++0x3 line.long 0x0 "DMA_TRANSFER_SIZE_OFF_WRCH_$1,DMA Write Transfer Size Register." hexmask.long 0x0 0.--31. 1. "DMA_TRANSFER_SIZE,DMA Transfer Size. You program this register with the size of the DMA transfer. The maximum DMA transfer size is 4Gbytes. The minimum transfer size is one byte (0x1). This field is automatically decremented by the DMA as the DMA write.." repeat.end repeat 8. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 )(list 0x0 0x200 0x400 0x600 0x800 0xA00 0xC00 0xE00 ) group.long ($2+0x20C+0xC8000)++0x3 line.long 0x0 "DMA_SAR_LOW_OFF_WRCH_$1,DMA Write SAR Low Register." hexmask.long 0x0 0.--31. 1. "SRC_ADDR_REG_LOW,Source Address Register (Lower 32 bits). Indicates the next address to be read from. The DMA increments the SAR as the DMA transfer progresses. In LL mode the DMA overwrites this with the corresponding dword of the LL element. - DMA.." repeat.end repeat 8. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 )(list 0x0 0x200 0x400 0x600 0x800 0xA00 0xC00 0xE00 ) group.long ($2+0x210+0xC8000)++0x3 line.long 0x0 "DMA_SAR_HIGH_OFF_WRCH_$1,DMA Write SAR High Register." hexmask.long 0x0 0.--31. 1. "SRC_ADDR_REG_HIGH,Source Address Register (Higher 32 bits). In LL mode the DMA overwrites this with the corresponding dword of the LL element. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" repeat.end repeat 8. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 )(list 0x0 0x200 0x400 0x600 0x800 0xA00 0xC00 0xE00 ) group.long ($2+0x214+0xC8000)++0x3 line.long 0x0 "DMA_DAR_LOW_OFF_WRCH_$1,DMA Write DAR Low Register." hexmask.long 0x0 0.--31. 1. "DST_ADDR_REG_LOW,Destination Address Register (Lower 32 bits). Indicates the next address to be written to. The DMA increments the DAR as the DMA transfer progresses. In LL mode the DMA overwrites this with the corresponding dword of the LL element. -.." repeat.end repeat 8. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 )(list 0x0 0x200 0x400 0x600 0x800 0xA00 0xC00 0xE00 ) group.long ($2+0x218+0xC8000)++0x3 line.long 0x0 "DMA_DAR_HIGH_OFF_WRCH_$1,DMA Write DAR High Register." hexmask.long 0x0 0.--31. 1. "DST_ADDR_REG_HIGH,Destination Address Register (Higher 32 bits). In LL mode the DMA overwrites this with the corresponding dword of the LL element. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" repeat.end repeat 8. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 )(list 0x0 0x200 0x400 0x600 0x800 0xA00 0xC00 0xE00 ) group.long ($2+0x21C+0xC8000)++0x3 line.long 0x0 "DMA_LLP_LOW_OFF_WRCH_$1,DMA Write Linked List Pointer Low Register." hexmask.long 0x0 0.--31. 1. "LLP_LOW,Lower bits of the address of the linked list transfer list in local memory. Used in linked list mode only. Updated by the DMA to point to the next element in the transfer list after the previous element is consumed. - When the current element is.." repeat.end repeat 8. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 )(list 0x0 0x200 0x400 0x600 0x800 0xA00 0xC00 0xE00 ) group.long ($2+0x220+0xC8000)++0x3 line.long 0x0 "DMA_LLP_HIGH_OFF_WRCH_$1,DMA Write Linked List Pointer High Register." hexmask.long 0x0 0.--31. 1. "LLP_HIGH,Upper 32 bits of the address of the linked list transfer list in local memory. Used in linked list mode only. Updated by the DMA to point to the next element in the transfer list as elements are consumed. Note: The access attributes of this.." repeat.end repeat 8. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 )(list 0x0 0x200 0x400 0x600 0x800 0xA00 0xC00 0xE00 ) group.long ($2+0x300+0xC8000)++0x3 line.long 0x0 "DMA_CH_CONTROL1_OFF_RDCH_$1,DMA Read Channel Control 1 Register." bitfld.long 0x0 30.--31. "DMA_AT,Address Translation TLP Header Bit (AT) The DMA uses this TLP header field when generating MRd/MWr (not IMWr) TLPs. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" "0,1,2,3" bitfld.long 0x0 27.--29. "DMA_TC,Traffic Class TLP Header Bit (TC) The DMA uses this TLP header field when generating MRd/MWr (not IMWr) TLPs. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 26. "DMA_RESERVED5,Reserved. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" "0,1" bitfld.long 0x0 25. "DMA_RO,Relaxed Ordering TLP Header Bit (RO) The DMA uses this TLP header field when generating MRd/MWr (not IMWr) TLPs. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" "0,1" newline bitfld.long 0x0 24. "DMA_NS_SRC,Source No Snoop TLP Header Bit (DMA_NS_SRC). The DMA uses this TLP header field when generating MRd (SAR addressing space) (not IMWr) TLPs. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" "0,1" bitfld.long 0x0 23. "DMA_NS_DST,Destination No Snoop TLP Header Bit (DMA_NS_DST). The DMA uses this TLP header field when generating MWr (DAR addressing space) (not IMWr) TLPs. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" "0,1" newline bitfld.long 0x0 22. "DMA_MEM_TYPE,Master AXI ACE-Lite Cache Coherency Control. This field sets the DMA channel memory type of the address space of the data transfer as follows: - 0x0:peripheral type - 0x1:memory type For more details see 'ACE-Lite Features and Limitations'.." "peripheral type,memory type" hexmask.long.byte 0x0 17.--21. 1. "DMA_RESERVED2,Reserved. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" newline hexmask.long.byte 0x0 12.--16. 1. "DMA_FUNC_NUM,Function Number (FN). The controller uses this field when generating the requester ID for the MRd/MWr DMA TLP. When you have enabled SR-IOV then this field is ignored if you have set the VFE field in the 'DMA Read Channel Control 2.." bitfld.long 0x0 10.--11. "DMA_RESERVED1,Reserved. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" "0,1,2,3" newline bitfld.long 0x0 9. "LLE,Linked List Enable (LLE). - 0: Disable linked list operation - 1: Enable linked list operation Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" "Disable linked list operation,Enable linked list operation" bitfld.long 0x0 8. "CCS,Consumer Cycle State (CCS). Used in linked list mode only. It is used to synchronize the producer (software) and the consumer (DMA). For more details see 'PCS-CCS-CB-TCB Producer-Consumer Synchronization'. You must initialize this bit. The DMA.." "0,1" newline bitfld.long 0x0 7. "DMA_RESERVED0,Reserved. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" "0,1" bitfld.long 0x0 5.--6. "CS,Channel Status (CS). The channel status bits identify the current operational state of the DMA channel. The operation state encoding for each DMA channel is a s follows: - 00: Reserved - 01: Running. This channel is active and transferring data. - 10:.." "Reserved,Running,?,?" newline bitfld.long 0x0 4. "RIE,Remote Interrupt Enable (RIE). You must set this bit to enable the generation of the Done or Abort Remote interrupts. For more details see 'Interrupts and Error Handling'. In LL mode the DMA overwrites this with the RIE of the LL element. The RIE.." "0,1" bitfld.long 0x0 3. "LIE,Local Interrupt Enable (LIE). You must set this bit to enable the generation of the Done or Abort Local interrupts. For more details see 'Interrupts and Error Handling'. In LL mode the DMA overwrites this with the LIE of the LL element. The LIE bit.." "0,1" newline bitfld.long 0x0 2. "LLP,Load Link Pointer (LLP). Used in linked list mode only. Indicates that this linked list element is a link element and its LL element pointer dwords are pointing to the next (non-contiguous) element. The DMA loads this field with the LLP of the.." "0,1" bitfld.long 0x0 1. "TCB,Toggle Cycle Bit (TCB). Indicates to the DMA to toggle its interpretation of the CB. Used in linked list mode only. It is used to synchronize the producer (software) and the consumer (DMA). For more details see 'PCS-CCS-CB-TCB Producer-Consumer.." "0,1" newline bitfld.long 0x0 0. "CB,Cycle Bit (CB). Used in linked list mode only. It is used to synchronize the producer (software) and the consumer (DMA). For more details see 'PCS-CCS-CB-TCB Producer-Consumer Synchronization'. The DMA loads this field with the CB of the linked list.." "0,1" repeat.end repeat 8. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 )(list 0x0 0x200 0x400 0x600 0x800 0xA00 0xC00 0xE00 ) group.long ($2+0x308+0xC8000)++0x3 line.long 0x0 "DMA_TRANSFER_SIZE_OFF_RDCH_$1,DMA Read Transfer Size Register." hexmask.long 0x0 0.--31. 1. "DMA_TRANSFER_SIZE,DMA Transfer Size. You program this register with the size of the DMA transfer. The maximum DMA transfer size is 4Gbytes. The minimum transfer size is one byte (0x1). This field is automatically decremented by the DMA as the DMA read.." repeat.end repeat 8. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 )(list 0x0 0x200 0x400 0x600 0x800 0xA00 0xC00 0xE00 ) group.long ($2+0x30C+0xC8000)++0x3 line.long 0x0 "DMA_SAR_LOW_OFF_RDCH_$1,DMA Read SAR Low Register." hexmask.long 0x0 0.--31. 1. "SRC_ADDR_REG_LOW,Source Address Register (Lower 32 bits). Indicates the next address to be read from. The DMA increments the SAR as the DMA transfer progresses. In LL mode the DMA overwrites this with the corresponding dword of the LL element. - DMA.." repeat.end repeat 8. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 )(list 0x0 0x200 0x400 0x600 0x800 0xA00 0xC00 0xE00 ) group.long ($2+0x310+0xC8000)++0x3 line.long 0x0 "DMA_SAR_HIGH_OFF_RDCH_$1,DMA Read SAR High Register." hexmask.long 0x0 0.--31. 1. "SRC_ADDR_REG_HIGH,Source Address Register (Higher 32 bits). In LL mode the DMA overwrites this with the corresponding dword of the LL element. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" repeat.end repeat 8. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 )(list 0x0 0x200 0x400 0x600 0x800 0xA00 0xC00 0xE00 ) group.long ($2+0x314+0xC8000)++0x3 line.long 0x0 "DMA_DAR_LOW_OFF_RDCH_$1,DMA Read DAR Low Register." hexmask.long 0x0 0.--31. 1. "DST_ADDR_REG_LOW,Destination Address Register (Lower 32 bits). Indicates the next address to be written to. The DMA increments the DAR as the DMA transfer progresses. In LL mode the DMA overwrites this with the corresponding dword of the LL element. -.." repeat.end repeat 8. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 )(list 0x0 0x200 0x400 0x600 0x800 0xA00 0xC00 0xE00 ) group.long ($2+0x318+0xC8000)++0x3 line.long 0x0 "DMA_DAR_HIGH_OFF_RDCH_$1,DMA Read DAR High Register." hexmask.long 0x0 0.--31. 1. "DST_ADDR_REG_HIGH,Destination Address Register (Higher 32 bits). In LL mode the DMA overwrites this with the corresponding dword of the LL element. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" repeat.end repeat 8. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 )(list 0x0 0x200 0x400 0x600 0x800 0xA00 0xC00 0xE00 ) group.long ($2+0x31C+0xC8000)++0x3 line.long 0x0 "DMA_LLP_LOW_OFF_RDCH_$1,DMA Read Linked List Pointer Low Register." hexmask.long 0x0 0.--31. 1. "LLP_LOW,Lower bits of the address of the linked list transfer list in local memory. Used in linked list mode only. Updated by the DMA to point to the next element in the transfer list after the previous element is consumed. - When the current element is.." repeat.end repeat 8. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 )(list 0x0 0x200 0x400 0x600 0x800 0xA00 0xC00 0xE00 ) group.long ($2+0x320+0xC8000)++0x3 line.long 0x0 "DMA_LLP_HIGH_OFF_RDCH_$1,DMA Read Linked List Pointer High Register." hexmask.long 0x0 0.--31. 1. "LLP_HIGH,Upper 32 bits of the address of the linked list transfer list in local memory. Used in linked list mode only. Updated by the DMA to point to the next element in the transfer list as elements are consumed. Note: The access attributes of this.." repeat.end tree.end tree "PF0_ATU_CAP (ATU Por Logic Structure)" repeat 8. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 )(list 0x0 0x200 0x400 0x600 0x800 0xA00 0xC00 0xE00 ) group.long ($2+0xC0000)++0x3 line.long 0x0 "IATU_REGION_CTRL_1_OFF_OUTBOUND_$1,iATU Region Control 1 Register." bitfld.long 0x0 20. "CTRL_1_FUNC_NUM,Function Number. - When the address of an outbound TLP is matched to this region and the FUNC_BYPASS field in the 'iATU Control 2 Register' is '0' then the function number used in generating the function part of the requester ID (RID).." "0,1" newline bitfld.long 0x0 13. "INCREASE_REGION_SIZE,Increase the maximum ATU Region size. When set the maximum ATU Region size is determined by CX_ATU_MAX_REGION_SIZE. When clear the maximum ATU Region size is 4 GB (default). Note: This register field is sticky." "0,1" newline bitfld.long 0x0 9.--10. "ATTR,When the address of an outbound TLP is matched to this region then the ATTR field of the TLP is changed to the value in this register. Note: This register field is sticky." "0,1,2,3" newline bitfld.long 0x0 8. "TD,This is a reserved field. Do not use. Note: This register field is sticky." "0,1" newline bitfld.long 0x0 5.--7. "TC,When the address of an outbound TLP is matched to this region then the TC field of the TLP is changed to the value in this register. Note: This register field is sticky." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x0 0.--4. 1. "TYPE,When the address of an outbound TLP is matched to this region then the TYPE field of the TLP is changed to the value in this register. Note: This register field is sticky." repeat.end repeat 8. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 )(list 0x0 0x200 0x400 0x600 0x800 0xA00 0xC00 0xE00 ) group.long ($2+0x4+0xC0000)++0x3 line.long 0x0 "IATU_REGION_CTRL_2_OFF_OUTBOUND_$1,iATU Region Control 2 Register." bitfld.long 0x0 31. "REGION_EN,Region Enable. This bit must be set to '1' for address translation to take place. Note: This register field is sticky." "0,1" newline bitfld.long 0x0 29. "INVERT_MODE,Invert Mode. When set the address matching region is inverted. Therefore an address match occurs when the untranslated address is in the region outside the defined range (Base Address to Limit Address). Note: This register field is sticky." "0,1" newline bitfld.long 0x0 28. "CFG_SHIFT_MODE,CFG Shift Mode. The iATU uses bits [27:12] of the untranslated address (on the XALI0/1/2 interface or AXI slave interface address) to form the BDF number of the outgoing CFG TLP. This supports the Enhanced Configuration Address Mapping.." "0,1" newline bitfld.long 0x0 27. "DMA_BYPASS,DMA Bypass Mode. Allows request TLPs which are initiated by the DMA controller to pass through the iATU untranslated. Note: This field is reserved for the SW product. You must set it to '0'. Note: This register field is sticky." "0,1" newline bitfld.long 0x0 23. "HEADER_SUBSTITUTE_EN,Header Substitute Enable. When enabled and region address is matched the iATU fully substitutes bytes 8-11 (for 3 DWORD header) or bytes 12-15 (for 4 DWORD header) of the outbound TLP header with the contents of the LWR_TARGET_RW.." "LWR_TARGET_RW in the..,LWR_TARGET_RW in the.." newline bitfld.long 0x0 22. "INHIBIT_PAYLOAD,Inhibit TLP Payload Data for TLP's in Matched Region; assign iATU region to be TLP without data. When enabled and region address is matched the iATU marks all TLPs as having no payload data by forcing the TLP header Fmt[1] bit =0.." "Fmt[1] =0/1 so that TLPs with or without data..,Fmt[1] =0 so that only TLP type without data is.." newline bitfld.long 0x0 21. "TLP_HEADER_FIELDS_BYPASS,TLP Header Fields Translation Bypass. In this mode header fields of the translated TLP is taken from your application transmit interface or if AMBA is configured from the AMBA sideband bus (slv_awmisc_info) and not from the.." "0,1" newline bitfld.long 0x0 20. "SNP,Serialize Non-Posted Requests. In this mode when the AXI Bridge is populated same AXI ID Non-Posted Read/Write Requests are transmitted on the wire if there are no other same ID Non-Posted Requests outstanding. Note: This register field is sticky." "0,1" newline bitfld.long 0x0 19. "FUNC_BYPASS,Function Number Translation Bypass. In this mode the function number of the translated TLP is taken from your application transmit interface and not from the CTRL_1_FUNC_NUM field of the 'iATU Control 1 Register' or the VF_NUMBER field of.." "0,1" newline bitfld.long 0x0 16. "TAG_SUBSTITUTE_EN,TAG Substitute Enable. When enabled and region address is matched the iATU substitutes the TAG field of the outbound TLP header with the contents of the TAG field in this register. The expected usage scenario is translation from AXI.." "0,1" newline hexmask.long.byte 0x0 8.--15. 1. "TAG,TAG. The substituted TAG field (byte 6) in the outgoing TLP header when TAG_SUBSTITUTE_EN is set. Note: This register field is sticky." newline hexmask.long.byte 0x0 0.--7. 1. "MSG_CODE,MSG TLPs (Message Code). When the address of an outbound TLP is matched to this region and the translated TLP TYPE field is Msg or MsgD; then the message field of the TLP is changed to the value in this register. Memory TLPs: (ST;Steering Tag)." repeat.end repeat 8. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 )(list 0x0 0x200 0x400 0x600 0x800 0xA00 0xC00 0xE00 ) group.long ($2+0x8+0xC0000)++0x3 line.long 0x0 "IATU_LWR_BASE_ADDR_OFF_OUTBOUND_$1,iATU Lower Base Address Register. The CX_ATU_MIN_REGION_SIZE configuration parameter (Value Range: 4 kB. 8 kB. 16 kB. 32 kB. 64 kB defaults to 64 kB) specifies the minimum size of an address translation region. For.." hexmask.long.tbyte 0x0 12.--31. 1. "LWR_BASE_RW,Forms bits [31:n] of the start address of the address region to be translated. n is log2(CX_ATU_MIN_REGION_SIZE) Note: This register field is sticky." newline hexmask.long.word 0x0 0.--11. 1. "LWR_BASE_HW,Forms bits [n-1:0] of the start address of the address region to be translated. The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary so these bits are always 0. A write to this location is ignored by the PCIe controller." repeat.end repeat 8. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 )(list 0x0 0x200 0x400 0x600 0x800 0xA00 0xC00 0xE00 ) group.long ($2+0xC+0xC0000)++0x3 line.long 0x0 "IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_$1,iATU Upper Base Address Register." hexmask.long 0x0 0.--31. 1. "UPPER_BASE_RW,Forms bits [63:32] of the start (and end) address of the address region to be translated. In systems with a 32-bit address space this register is not used and therefore writing to this register has no effect. Note: This register field is.." repeat.end repeat 8. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 )(list 0x0 0x200 0x400 0x600 0x800 0xA00 0xC00 0xE00 ) group.long ($2+0x10+0xC0000)++0x3 line.long 0x0 "IATU_LIMIT_ADDR_OFF_OUTBOUND_$1,iATU Limit Address Register." hexmask.long.tbyte 0x0 12.--31. 1. "LIMIT_ADDR_RW,Forms upper bits of the end address of the address region to be translated. Note: This register field is sticky." newline hexmask.long.word 0x0 0.--11. 1. "LIMIT_ADDR_HW,Forms lower bits of the end address of the address region to be translated. The end address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary so these bits are always all ones. A write to this location is ignored by the PCIe.." repeat.end repeat 8. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 )(list 0x0 0x200 0x400 0x600 0x800 0xA00 0xC00 0xE00 ) group.long ($2+0x14+0xC0000)++0x3 line.long 0x0 "IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_$1,iATU Lower Target Address Register." hexmask.long 0x0 0.--31. 1. "LWR_TARGET_RW_OUTBOUND,When HEADER_SUBSTITUTE_EN in IATU_REGION_CTRL_2_OFF_OUTBOUND_ is '0' (normal operation): - LWR_TARGET_RW[31:n] forms MSB's of the Lower Target part of the new address of the translated region; - LWR_TARGET_RW[n-1:0] are not used." repeat.end repeat 8. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 )(list 0x0 0x200 0x400 0x600 0x800 0xA00 0xC00 0xE00 ) group.long ($2+0x18+0xC0000)++0x3 line.long 0x0 "IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_$1,iATU Upper Target Address Register." hexmask.long 0x0 0.--31. 1. "UPPER_TARGET_RW,Forms bits [63:32] of the start address (Upper Target part) of the new address of the translated region. Note: This register field is sticky." repeat.end repeat 8. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 )(list 0x0 0x200 0x400 0x600 0x800 0xA00 0xC00 0xE00 ) group.long ($2+0x1C+0xC0000)++0x3 line.long 0x0 "IATU_REGION_CTRL_3_OFF_OUTBOUND_$1,iATU Region Control 3 Register." bitfld.long 0x0 31. "VF_ACTIVE,Virtual Function Active. Indicates that all of the outbound accesses are from virtual functions. For more details see VF_ACTIVE field. Note: This register field is sticky." "0,1" newline hexmask.long 0x0 3.--30. 1. "RSVDP_VF_NUMBER,Reserved for future use." newline bitfld.long 0x0 0.--2. "VF_NUMBER,Virtual Function Number. When the address of an outbound TLP is matched to this region and the FUNC_BYPASS field in the 'iATU Control 2 Register' is '0' then this field used in generating the Function part of the requester ID (RID) field of.." "0,1,2,3,4,5,6,7" repeat.end repeat 8. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 )(list 0x0 0x200 0x400 0x600 0x800 0xA00 0xC00 0xE00 ) group.long ($2+0x100+0xC0000)++0x3 line.long 0x0 "IATU_REGION_CTRL_1_OFF_INBOUND_$1,iATU Region Control 1 Register." bitfld.long 0x0 20. "CTRL_1_FUNC_NUM,Function Number. - MEM-I/O: When the Address and BAR matching logic in the controller indicate that a MEM-I/O transaction matches a BAR in the function corresponding to this value then address translation proceeds. This check is only.." "?,When the destination function number as.." newline bitfld.long 0x0 13. "INCREASE_REGION_SIZE,Increase the maximum ATU Region size. When set the maximum ATU Region size is determined by CX_ATU_MAX_REGION_SIZE. When clear the maximum ATU Region size is 4 GB (default). Note: This register field is sticky." "0,1" newline bitfld.long 0x0 9.--10. "ATTR,When the ATTR field of an inbound TLP is matched to this value then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the 'ATTR Match Enable' bit of the 'iATU Control 2 Register' is.." "0,1,2,3" newline bitfld.long 0x0 8. "TD,When the TD field of an inbound TLP is matched to this value then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the 'TD Match Enable' bit of the 'iATU Control 2 Register' is set." "0,1" newline bitfld.long 0x0 5.--7. "TC,When the TC field of an inbound TLP is matched to this value then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the 'TC Match Enable' bit of the 'iATU Control 2 Register' is set." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x0 0.--4. 1. "TYPE,When the TYPE field of an inbound TLP is matched to this value then address translation proceeds (when all other enabled field-matches are successful). Note: This register field is sticky." repeat.end repeat 8. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 )(list 0x0 0x200 0x400 0x600 0x800 0xA00 0xC00 0xE00 ) group.long ($2+0x104+0xC0000)++0x3 line.long 0x0 "IATU_REGION_CTRL_2_OFF_INBOUND_$1,iATU Region Control 2 Register." bitfld.long 0x0 31. "REGION_EN,Region Enable. This bit must be set to '1' for address translation to take place. Note: This register field is sticky." "0,1" newline bitfld.long 0x0 30. "MATCH_MODE,Match Mode. Determines Inbound matching mode for TLPs. The mode depends on the type of TLP that is received as follows: For MEM-I/O TLPs this field is interpreted as follows: - 0: Address Match Mode. The iATU operates using addresses as in.." "Address Match Mode,Vendor ID Match Mode" newline bitfld.long 0x0 29. "INVERT_MODE,Invert Mode. When set the address matching region is inverted. Therefore an address match occurs when the untranslated address is in the region outside the defined range (Base Address to Limit Address). Note: This register field is sticky." "0,1" newline bitfld.long 0x0 28. "CFG_SHIFT_MODE,CFG Shift Mode. This is useful for CFG transactions where the PCIe configuration mechanism maps bits [27:12] of the address to the bus/device and function number. This allows a CFG configuration space to be located in any 256MB window of.." "0,1" newline bitfld.long 0x0 27. "FUZZY_TYPE_MATCH_CODE,Fuzzy Type Match Mode. When enabled the iATU relaxes the matching of the TLP TYPE field against the expected TYPE field so that - CfgRd0 and CfgRd1 TLPs are seen as identical. Similarly with CfgWr0 and CfgWr1. - MWr MRd and MRdLk.." "0,1" newline bitfld.long 0x0 26. "VFBAR_MATCH_MODE_EN,VF BAR Match Mode enable. When set Virtual Function BAR matching is used which allows all VFs in a PF which match a BAR to be matched with a single ATU region. Note: This register field is sticky." "0,1" newline bitfld.long 0x0 24.--25. "RESPONSE_CODE,Response Code. Defines the type of response to give for accesses matching this region. This overrides the normal RADM filter response. Note that this feature is not available for any region where Single Address Location Translate is.." "Normal RADM filter response is used,Unsupported request,?,?" newline bitfld.long 0x0 23. "SINGLE_ADDR_LOC_TRANS_EN,Single Address Location Translate Enable. When enabled Rx TLPs can be translated to a single address location as determined by the target address register of the iATU region. The main usage scenario is translation of Messages.." "0,1" newline bitfld.long 0x0 21. "MSG_CODE_MATCH_EN,Message Code Match Enable (Msg TLPS). Ensures that a successful message Code TLP field comparison match (see Message Code field of the 'iATU Control 2 Register') occurs (in MSG transactions) for address translation to proceed. ST Match.." "0,1" newline bitfld.long 0x0 20. "VF_MATCH_EN,Virtual Function Number Match Enable. Ensures that a successful Virtual Function Number TLP field comparison match (see Virtual Function Number field of the 'iATU Control 3 Register') occurs (in MEM-I/O transactions) for address translation.." "0,1" newline bitfld.long 0x0 19. "FUNC_NUM_MATCH_EN,Function Number Match Enable. Ensures that a successful Function Number TLP field comparison match (see Function Number field of the 'iATU Control 1 Register') occurs (in MEM-I/O and CFG0/CFG1 transactions) for address translation to.." "0,1" newline bitfld.long 0x0 16. "ATTR_MATCH_EN,ATTR Match Enable. Ensures that a successful ATTR TLP field comparison match (see ATTR field of the 'iATU Control 1 Register') occurs for address translation to proceed. Note: This register field is sticky." "0,1" newline bitfld.long 0x0 15. "TD_MATCH_EN,TD Match Enable. Ensures that a successful TD TLP field comparison match (see TD field of the 'iATU Control 1 Register') occurs for address translation to proceed. Note: This register field is sticky." "0,1" newline bitfld.long 0x0 14. "TC_MATCH_EN,TC Match Enable. Ensures that a successful TC TLP field comparison match (see TC field of the 'iATU Control 1 Register') occurs for address translation to proceed. Note: This register field is sticky." "0,1" newline bitfld.long 0x0 13. "MSG_TYPE_MATCH_MODE,Message Type Match Mode. When enabled and if single address location translate enable is set then inbound TLPs of type MSG/MSGd which match the type field of the iatu_region_ctrl_1_OFF_inbound register (=>TYPE[4:3]=2'b10) will be.." "0,1" newline bitfld.long 0x0 8.--10. "BAR_NUM,BAR Number. When the BAR number of an inbound MEM or IO TLP ' that is matched by the normal internal BAR address matching mechanism ' is the same as this field address translation proceeds (when all other enabled field-matches are successful)." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x0 0.--7. 1. "MSG_CODE,MSG TLPs: (Message Code). When the TYPE field of an inbound Msg/MsgD TLP is matched to this value then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the 'Message Code Match.." repeat.end repeat 8. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 )(list 0x0 0x200 0x400 0x600 0x800 0xA00 0xC00 0xE00 ) group.long ($2+0x108+0xC0000)++0x3 line.long 0x0 "IATU_LWR_BASE_ADDR_OFF_INBOUND_$1,iATU Lower Base Address Register. The CX_ATU_MIN_REGION_SIZE configuration parameter (Value Range: 4 kB. 8 kB. 16 kB. 32 kB. 64 kB defaults to 64 kB) specifies the minimum size of an address translation region. For.." hexmask.long.tbyte 0x0 12.--31. 1. "LWR_BASE_RW,Forms bits [31:n] of the start address of the address region to be translated. n is log2(CX_ATU_MIN_REGION_SIZE) Note: This register field is sticky." newline hexmask.long.word 0x0 0.--11. 1. "LWR_BASE_HW,Forms bits [n-1:0] of the start address of the address region to be translated. The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary so these bits are always 0. A write to this location is ignored by the PCIe controller." repeat.end repeat 8. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 )(list 0x0 0x200 0x400 0x600 0x800 0xA00 0xC00 0xE00 ) group.long ($2+0x10C+0xC0000)++0x3 line.long 0x0 "IATU_UPPER_BASE_ADDR_OFF_INBOUND_$1,iATU Upper Base Address Register." hexmask.long 0x0 0.--31. 1. "UPPER_BASE_RW,Forms bits [63:32] of the start (and end) address of the address region to be translated. Note: This register field is sticky." repeat.end repeat 8. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 )(list 0x0 0x200 0x400 0x600 0x800 0xA00 0xC00 0xE00 ) group.long ($2+0x110+0xC0000)++0x3 line.long 0x0 "IATU_LIMIT_ADDR_OFF_INBOUND_$1,iATU Limit Address Register." hexmask.long.tbyte 0x0 12.--31. 1. "LIMIT_ADDR_RW,Forms upper bits of the end address of the address region to be translated. Note: This register field is sticky." newline hexmask.long.word 0x0 0.--11. 1. "LIMIT_ADDR_HW,Forms lower bits of the end address of the address region to be translated. The end address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary so these bits are always all ones. A write to this location is ignored by the PCIe.." repeat.end repeat 8. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 )(list 0x0 0x200 0x400 0x600 0x800 0xA00 0xC00 0xE00 ) group.long ($2+0x114+0xC0000)++0x3 line.long 0x0 "IATU_LWR_TARGET_ADDR_OFF_INBOUND_$1,iATU Lower Target Address Register." hexmask.long.tbyte 0x0 12.--31. 1. "LWR_TARGET_RW,Forms MSB's of the Lower Target part of the new address of the translated region. These bits are always '0'. - Field size depends on log2(CX_ATU_MIN_REGION_SIZE) in address match mode. - Field size depends on log2(BAR_MASK+1) in BAR match.." newline hexmask.long.word 0x0 0.--11. 1. "LWR_TARGET_HW,Forms the LSB's of the Lower Target part of the new address of the translated region. The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary (in address match mode); and to the Bar size boundary (in BAR match mode) so.." repeat.end repeat 8. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 )(list 0x0 0x200 0x400 0x600 0x800 0xA00 0xC00 0xE00 ) group.long ($2+0x118+0xC0000)++0x3 line.long 0x0 "IATU_UPPER_TARGET_ADDR_OFF_INBOUND_$1,iATU Upper Target Address Register." hexmask.long 0x0 0.--31. 1. "UPPER_TARGET_RW,Forms bits [63:32] of the start address (Upper Target part) of the new address of the translated region. In systems with a 32-bit address space this register is not used and therefore writing to this register has no effect. Note: This.." repeat.end repeat 8. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 )(list 0x0 0x200 0x400 0x600 0x800 0xA00 0xC00 0xE00 ) group.long ($2+0x11C+0xC0000)++0x3 line.long 0x0 "IATU_REGION_CTRL_3_OFF_INBOUND_$1,iATU Region Control 3 Register." rbitfld.long 0x0 31. "VF_ACTIVE,Reserved. Not used." "0,1" newline hexmask.long 0x0 3.--30. 1. "RSVDP_VF_NUMBER,Reserved for future use." newline bitfld.long 0x0 0.--2. "VF_NUMBER,Virtual Function Number. When the Address and BAR matching logic in the controller indicates that a MEM-I/O transaction matches a BAR in the virtual function corresponding to this value then address translation proceeds. This check is only.." "0,1,2,3,4,5,6,7" repeat.end tree.end tree "PF0_PORT_LOGIC (Port Logic)" group.long (0x0+0x700)++0x27 line.long 0x0 "ACK_LATENCY_TIMER_OFF,Ack Latency Timer and Replay Timer Register." hexmask.long.word 0x0 16.--31. 1. "REPLAY_TIME_LIMIT,Replay Timer Limit. The replay timer expires when it reaches this limit. The controller initiates a replay upon reception of a NAK or when the replay timer expires. For more details see 'Transmit Replay'. You can modify the effective.." newline hexmask.long.word 0x0 0.--15. 1. "ROUND_TRIP_LATENCY_TIME_LIMIT,Ack Latency Timer Limit. The Ack latency timer expires when it reaches this limit. For more details see 'Ack Scheduling'. You can modify the effective timer limit with the TIMER_MOD_ACK_NAK field of the.." line.long 0x4 "VENDOR_SPEC_DLLP_OFF,Vendor Specific DLLP Register." hexmask.long 0x4 0.--31. 1. "VENDOR_SPEC_DLLP,Vendor Specific DLLP Register. Used to send a specific PCI Express DLLP. Your application writes the 8-bit DLLP Type and 24-bits of Payload data into this register then sets the field VENDOR_SPECIFIC_DLLP_REQ of PORT_LINK_CTRL_OFF to.." line.long 0x8 "PORT_FORCE_OFF,Port Force Link Register." hexmask.long.byte 0x8 24.--31. 1. "RSVDP_24,Reserved for future use." newline bitfld.long 0x8 23. "DO_DESKEW_FOR_SRIS,Use the transitions from TS2 to Logical Idle Symbol SKP OS to Logical Idle Symbol EIEOS to Logical Idle Symbol and FTS Sequence to SKP OS to do deskew instead of using received SKP OS or TS1 to TS2 transition if DO_DESKEW_FOR_SRIS.." "0,1" newline rbitfld.long 0x8 22. "RSVDP_22,Reserved for future use." "0,1" newline hexmask.long.byte 0x8 16.--21. 1. "LINK_STATE,Forced LTSSM State. The LTSSM state that the controller is forced to when you set the FORCE_EN bit (Force Link). LTSSM state encoding is defined by the lts_state variable in workspace/src/Layer1/smlh_ltssm.v. Note: This register field is sticky." newline bitfld.long 0x8 15. "FORCE_EN,Force Link. The controller supports a testing and debug capability to allow your software to force the LTSSM state machine into a specific state and to force the controller to transmit a specific Link Command. Asserting this bit triggers the.." "0,1" newline rbitfld.long 0x8 12.--14. "RSVDP_12,Reserved for future use." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x8 8.--11. 1. "FORCED_LTSSM,Forced Link Command. The link command that the controller is forced to transmit when you set FORCE_EN bit (Force Link). Link command encoding is defined by the ltssm_cmd variable in workspace/src/Layer1/smlh_ltssm.v. Note: This register.." newline hexmask.long.byte 0x8 0.--7. 1. "LINK_NUM,Link Number. Not used for endpoint. Not used for M-PCIe. Note: This register field is sticky." line.long 0xC "ACK_F_ASPM_CTRL_OFF,Ack Frequency and L0-L1 ASPM Control Register." rbitfld.long 0xC 31. "RSVDP_31,Reserved for future use." "0,1" newline bitfld.long 0xC 30. "ENTER_ASPM,ASPM L1 Entry Control. - 1: Controller enters ASPM L1 after a period in which it has been idle. - 0: Controller enters ASPM L1 only after idle period during which both receive and transmit are in L0s. Note: This register field is sticky." "Controller enters ASPM L1 only after idle period..,Controller enters ASPM L1 after a period in.." newline bitfld.long 0xC 27.--29. "L1_ENTRANCE_LATENCY,L1 Entrance Latency. Value range is: - 000: 1 us - 001: 2 us - 010: 4 us - 011: 8 us - 100: 16 us - 101: 32 us - 110 or 111: 64 us Note: Programming this timer with a value greater that 32us has no effect unless extended sync is used.." "0,1,2,3,4,5,6,7" newline bitfld.long 0xC 24.--26. "L0S_ENTRANCE_LATENCY,L0s Entrance Latency. Values correspond to: - 000: 1 us - 001: 2 us - 010: 3 us - 011: 4 us - 100: 5 us - 101: 6 us - 110 or 111: 7 us This field is applicable to STALL while in L0 for M-PCIe. Note: This register field is sticky." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0xC 16.--23. 1. "COMMON_CLK_N_FTS,Common Clock N_FTS. This is the N_FTS when common clock is used. The number of Fast Training Sequence ordered sets to be transmitted when transitioning from L0s to L0. The maximum number of FTS ordered-sets that a component can request.." newline hexmask.long.byte 0xC 8.--15. 1. "ACK_N_FTS,N_FTS. The number of Fast Training Sequence ordered sets to be transmitted when transitioning from L0s to L0. The maximum number of FTS ordered-sets that a component can request is 255. The controller does not support a value of zero; a value.." newline hexmask.long.byte 0xC 0.--7. 1. "ACK_FREQ,Ack Frequency. The controller accumulates the number of pending ACKs specified here (up to 255) before scheduling an ACK DLLP. - 0: Indicates that this Ack Frequency Counter feature is turned off. The controller generates a low-priority ACK.." line.long 0x10 "PORT_LINK_CTRL_OFF,Port Link Control Register." hexmask.long.byte 0x10 28.--31. 1. "RSVDP_28,Reserved for future use." newline bitfld.long 0x10 27. "TRANSMIT_LANE_REVERSALE_ENABLE,TRANSMIT_LANE_REVERSALE_ENABLE is an internally reserved field. Do not use. Note: This register field is sticky." "0,1" newline bitfld.long 0x10 26. "EXTENDED_SYNCH,EXTENDED_SYNCH is an internally reserved field. Do not use. Note: This register field is sticky." "0,1" newline bitfld.long 0x10 25. "CORRUPT_LCRC_ENABLE,CORRUPT_LCRC_ENABLE is an internally reserved field. Do not use. Note: This register field is sticky." "0,1" newline bitfld.long 0x10 24. "BEACON_ENABLE,BEACON_ENABLE is an internally reserved field. Do not use. Note: This register field is sticky." "0,1" newline hexmask.long.byte 0x10 16.--21. 1. "LINK_CAPABLE,Link Mode Enable. Sets the number of lanes in the link that you want to connect to the link partner. When you have unused lanes in your system then you must change the value in this register to reflect the number of lanes. You must also.." newline hexmask.long.byte 0x10 12.--15. 1. "RSVDP_12,Reserved for future use." newline hexmask.long.byte 0x10 8.--11. 1. "LINK_RATE,LINK_RATE is an internally reserved field. Do not use. Note: This register field is sticky." newline bitfld.long 0x10 7. "FAST_LINK_MODE,Fast Link Mode. Sets all internal LTSSM millisecond timers to Fast Mode for speeding up simulation. Forces the LTSSM training (link initialization) to use shorter time-outs and to link up faster. The default scaling factor can be changed.." "0,1" newline bitfld.long 0x10 6. "LINK_DISABLE,LINK_DISABLE is an internally reserved field. Do not use. Note: This register field is sticky." "0,1" newline bitfld.long 0x10 5. "DLL_LINK_EN,DLL Link Enable. Enables link initialization. When DLL Link Enable =0 the controller does not transmit InitFC DLLPs and does not establish a link. Note: This register field is sticky." "0,1" newline rbitfld.long 0x10 4. "RSVDP_4,Reserved for future use." "0,1" newline bitfld.long 0x10 3. "RESET_ASSERT,Reset Assert. Triggers a recovery and forces the LTSSM to the hot reset state (downstream port only). Note: This register field is sticky." "0,1" newline bitfld.long 0x10 2. "LOOPBACK_ENABLE,Loopback Enable. Turns on loopback. For more details see 'Loopback'. For M-PCIe to force the master to enter Digital Loopback mode you must set this field to '1' during Configuration.start state(initial discovery/configuration). M-PCIe.." "0,1" newline bitfld.long 0x10 1. "SCRAMBLE_DISABLE,Scramble Disable. Turns off data scrambling. Note: This register field is sticky." "0,1" newline bitfld.long 0x10 0. "VENDOR_SPECIFIC_DLLP_REQ,Vendor Specific DLLP Request. When software writes a '1' to this bit the controller transmits the DLLP contained in the VENDOR_SPEC_DLLP field of VENDOR_SPEC_DLLP_OFF. Reading from this self-clearing register field always.." "0,1" line.long 0x14 "LANE_SKEW_OFF,Lane Skew Register." bitfld.long 0x14 31. "DISABLE_LANE_TO_LANE_DESKEW,Disable Lane-to-Lane Deskew. Causes the controller to disable the internal Lane-to-Lane deskew logic. Note: This register field is sticky." "0,1" newline hexmask.long.byte 0x14 27.--30. 1. "IMPLEMENT_NUM_LANES,Implementation-specific Number of Lanes. Set the implementation-specific number of lanes. Allowed values are: - 4'b0000: 1 lane - 4'b0001: 2 lanes - 4'b0011: 4 lanes - 4'b0111: 8 lanes - 4'b1111: 16 lanes The number of lanes to be.." newline bitfld.long 0x14 26. "ELASTIC_BUFFER_MODE,Selects Elasticity Buffer operating mode: 0: Nominal Half Full Buffer mode 1: Nominal Empty Buffer Mode Note: This register field is sticky." "Nominal Half Full Buffer mode,Nominal Empty Buffer Mode" newline bitfld.long 0x14 25. "ACK_NAK_DISABLE,Ack/Nak Disable. Prevents the controller from sending ACK and NAK DLLPs. Note: This register field is sticky." "0,1" newline bitfld.long 0x14 24. "FLOW_CTRL_DISABLE,Flow Control Disable. Prevents the controller from sending FC DLLPs. Note: This register field is sticky." "0,1" newline hexmask.long.tbyte 0x14 0.--23. 1. "INSERT_LANE_SKEW,INSERT_LANE_SKEW is an internally reserved field. Do not use. Note: This register field is sticky." line.long 0x18 "TIMER_CTRL_MAX_FUNC_NUM_OFF,Timer Control and Max Function Number Register." rbitfld.long 0x18 31. "RSVDP_31,Reserved for future use." "0,1" newline bitfld.long 0x18 29.--30. "FAST_LINK_SCALING_FACTOR,Fast Link Timer Scaling Factor. Sets the scaling factor of LTSSM timer when FAST_LINK_MODE field in PORT_LINK_CTRL_OFF is set to '1'. - 0: Scaling Factor is 1024 (1ms is 1us *a) - 1: Scaling Factor is 256 (1ms is 4us) - 2:.." "Scaling Factor is 1024,Scaling Factor is 256,Scaling Factor is 64,Scaling Factor is 16" newline hexmask.long.byte 0x18 24.--28. 1. "UPDATE_FREQ_TIMER,UPDATE_FREQ_TIMER is an internally reserved field. Do not use. Note: This register field is sticky." newline hexmask.long.byte 0x18 19.--23. 1. "TIMER_MOD_ACK_NAK,Ack Latency Timer Modifier. Increases the timer value for the Ack latency timer in increments of 64 clock cycles. A value of '0' represents no modification to the timer value. For more details see the ROUND_TRIP_LATENCY_TIME_LIMIT.." newline hexmask.long.byte 0x18 14.--18. 1. "TIMER_MOD_REPLAY_TIMER,Replay Timer Limit Modifier. Increases the time-out value for the replay timer in increments of 64 clock cycles at Gen1 or Gen2 speed and in increments of 256 clock cycles at Gen3 speed. A value of '0' represents no modification.." newline hexmask.long.byte 0x18 8.--13. 1. "RSVDP_8,Reserved for future use." newline hexmask.long.byte 0x18 0.--7. 1. "MAX_FUNC_NUM,Maximum function number that can be used in a request. Configuration requests targeted at function numbers above this value are returned with UR (unsupported request). Note: This register field is sticky." line.long 0x1C "SYMBOL_TIMER_FILTER_1_OFF,Symbol Timer Register and Filter Mask 1 Register. The Filter Mask 1 Register modifies the RADM filtering and error handling rules. For more details. see the 'Receive Filtering' section. In each case. '0' applies the associated.." hexmask.long.word 0x1C 16.--31. 1. "MASK_RADM_1,Filter Mask 1. The Filter Mask 1 Register modifies the RADM filtering and error handling rules. For more details see the 'Receive Filtering' section. In each case '0' applies the associated filtering rule and '1' masks the associated.." newline bitfld.long 0x1C 15. "DISABLE_FC_WD_TIMER,Disable FC Watchdog Timer. Note: This register field is sticky." "0,1" newline hexmask.long.byte 0x1C 11.--14. 1. "EIDLE_TIMER,EIDLE_TIMER is an internally reserved field. Do not use. Note: This register field is sticky." newline hexmask.long.word 0x1C 0.--10. 1. "SKP_INT_VAL,SKP Interval Value. The number of symbol times to wait between transmitting SKP ordered sets. Note that the controller actually waits the number of symbol times in this register plus 1 between transmitting SKP ordered sets. Your application.." line.long 0x20 "FILTER_MASK_2_OFF,Filter Mask 2 Register. This register modifies the RADM filtering and error handling rules. For more details. see the 'Receive Filtering' section. In each case. '0' applies the associated filtering rule and '1' masks the associated.." hexmask.long 0x20 0.--31. 1. "MASK_RADM_2,Filter Mask 2. This field modifies the RADM filtering and error handling rules. For more details see the 'Receive Filtering' section. In each case '0' applies the associated filtering rule and '1' masks the associated filtering rule." line.long 0x24 "AMBA_MUL_OB_DECOMP_NP_SUB_REQ_CTRL_OFF,AMBA Multiple Outbound Decomposed NP SubRequests Control Register." hexmask.long 0x24 1.--31. 1. "RSVDP_1,Reserved for future use." newline bitfld.long 0x24 0. "OB_RD_SPLIT_BURST_EN,Enable AMBA Multiple Outbound Decomposed NP SubRequests. This bit when set to '0' disables the possibility of having multiple outstanding non-posted requests that were derived from decomposition of an outbound AMBA request. For more.." "0,1" rgroup.long (0x28+0x700)++0x13 line.long 0x0 "PL_DEBUG0_OFF,Debug Register 0" hexmask.long 0x0 0.--31. 1. "DEB_REG_0,The value on cxpl_debug_info[31:0]." line.long 0x4 "PL_DEBUG1_OFF,Debug Register 1" hexmask.long 0x4 0.--31. 1. "DEB_REG_1,The value on cxpl_debug_info[63:32]." line.long 0x8 "TX_P_FC_CREDIT_STATUS_OFF,Transmit Posted FC Credit Status" hexmask.long.word 0x8 20.--31. 1. "RSVDP_TX_P_FC_CREDIT_STATUS,Reserved for future use." newline hexmask.long.byte 0x8 12.--19. 1. "TX_P_HEADER_FC_CREDIT,Transmit Posted Header FC Credits. The posted Header credits advertised by the receiver at the other end of the link updated with each UpdateFC DLLP. Default value depends on the number of advertised credits for header and data.." newline hexmask.long.word 0x8 0.--11. 1. "TX_P_DATA_FC_CREDIT,Transmit Posted Data FC Credits. The posted Data credits advertised by the receiver at the other end of the link updated with each UpdateFC DLLP. Default value depends on the number of advertised credits for header and data Scaled.." line.long 0xC "TX_NP_FC_CREDIT_STATUS_OFF,Transmit Non-Posted FC Credit Status" hexmask.long.word 0xC 20.--31. 1. "RSVDP_TX_NP_FC_CREDIT_STATUS,Reserved for future use." newline hexmask.long.byte 0xC 12.--19. 1. "TX_NP_HEADER_FC_CREDIT,Transmit Non-Posted Header FC Credits. The non-posted Header credits advertised by the receiver at the other end of the link updated with each UpdateFC DLLP. Default value depends on the number of advertised credits for header and.." newline hexmask.long.word 0xC 0.--11. 1. "TX_NP_DATA_FC_CREDIT,Transmit Non-Posted Data FC Credits. The non-posted Data credits advertised by the receiver at the other end of the link updated with each UpdateFC DLLP. Default value depends on the number of advertised credits for header and data.." line.long 0x10 "TX_CPL_FC_CREDIT_STATUS_OFF,Transmit Completion FC Credit Status" hexmask.long.word 0x10 20.--31. 1. "RSVDP_TX_CPL_FC_CREDIT_STATUS,Reserved for future use." newline hexmask.long.byte 0x10 12.--19. 1. "TX_CPL_HEADER_FC_CREDIT,Transmit Completion Header FC Credits. The Completion Header credits advertised by the receiver at the other end of the link updated with each UpdateFC DLLP. Default value depends on the number of advertised credits for header.." newline hexmask.long.word 0x10 0.--11. 1. "TX_CPL_DATA_FC_CREDIT,Transmit Completion Data FC Credits. The Completion Data credits advertised by the receiver at the other end of the link updated with each UpdateFC DLLP. Default value depends on the number of advertised credits for header and data.." group.long (0x3C+0x700)++0x3 line.long 0x0 "QUEUE_STATUS_OFF,Queue Status" bitfld.long 0x0 31. "TIMER_MOD_FLOW_CONTROL_EN,FC Latency Timer Override Enable. When this bit is set the value from the 'FC Latency Timer Override Value' field in this register will override the FC latency timer value that the controller calculates according to the PCIe.." "0,1" newline rbitfld.long 0x0 29.--30. "RSVDP_29,Reserved for future use." "0,1,2,3" newline hexmask.long.word 0x0 16.--28. 1. "TIMER_MOD_FLOW_CONTROL,FC Latency Timer Override Value. When you set the 'FC Latency Timer Override Enable' in this register the value in this field will override the FC latency timer value that the controller calculates according to the PCIe.." newline rbitfld.long 0x0 13. "RX_SERIALIZATION_Q_NON_EMPTY,Receive Serialization Queue Not Empty. Indicates there is data in the serialization queue." "0,1" newline hexmask.long.word 0x0 4.--12. 1. "RSVDP_4,Reserved for future use." newline bitfld.long 0x0 3. "RX_QUEUE_OVERFLOW,Receive Credit Queue Overflow. Indicates insufficient buffer space available to write to the P/NP/CPL credit queue." "0,1" newline rbitfld.long 0x0 2. "RX_QUEUE_NON_EMPTY,Receive Credit Queue Not Empty. Indicates there is data in one or more of the receive buffers." "0,1" newline rbitfld.long 0x0 1. "TX_RETRY_BUFFER_NE,Transmit Retry Buffer Not Empty. Indicates that there is data in the transmit retry buffer." "0,1" newline rbitfld.long 0x0 0. "RX_TLP_FC_CREDIT_NON_RETURN,Received TLP FC Credits Not Returned. Indicates that the controller has received a TLP but has not yet sent an UpdateFC DLLP indicating that the credits for that TLP have been restored by the receiver at the other end of the.." "0,1" rgroup.long (0x40+0x700)++0x7 line.long 0x0 "VC_TX_ARBI_1_OFF,VC Transmit Arbitration Register 1" hexmask.long.byte 0x0 24.--31. 1. "WRR_WEIGHT_VC_3,WRR Weight for VC3. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R" newline hexmask.long.byte 0x0 16.--23. 1. "WRR_WEIGHT_VC_2,WRR Weight for VC2. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R" newline hexmask.long.byte 0x0 8.--15. 1. "WRR_WEIGHT_VC_1,WRR Weight for VC1. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R" newline hexmask.long.byte 0x0 0.--7. 1. "WRR_WEIGHT_VC_0,WRR Weight for VC0. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R" line.long 0x4 "VC_TX_ARBI_2_OFF,VC Transmit Arbitration Register 2" hexmask.long.byte 0x4 24.--31. 1. "WRR_WEIGHT_VC_7,WRR Weight for VC7. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R" newline hexmask.long.byte 0x4 16.--23. 1. "WRR_WEIGHT_VC_6,WRR Weight for VC6. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R" newline hexmask.long.byte 0x4 8.--15. 1. "WRR_WEIGHT_VC_5,WRR Weight for VC5. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R" newline hexmask.long.byte 0x4 0.--7. 1. "WRR_WEIGHT_VC_4,WRR Weight for VC4. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R" group.long (0x48+0x700)++0xB line.long 0x0 "VC0_P_RX_Q_CTRL_OFF,Segmented-Buffer VC0 Posted Receive Queue Control." bitfld.long 0x0 31. "VC_ORDERING_RX_Q,VC Ordering for Receive Queues. Determines the VC ordering rule for the receive queues used only in the segmented-buffer configuration: - 1: Strict ordering higher numbered VCs have higher priority - 0: Round robin Note: This register.." "Round robin,Strict ordering" newline bitfld.long 0x0 30. "TLP_TYPE_ORDERING_VC0,TLP Type Ordering for VC0. Determines the TLP type ordering rule for VC0 receive queues used only in the segmented-buffer configuration: - 1: PCIe ordering rules (recommended) - 0: Strict ordering: posted completion then.." "Strict ordering: posted,PCIe ordering rules" newline bitfld.long 0x0 28.--29. "RESERVED5,Reserved. Note: This register field is sticky." "0,1,2,3" newline bitfld.long 0x0 26.--27. "VC0_P_DATA_SCALE,VC0 Scale Posted Data Credites. Note: This register field is sticky." "0,1,2,3" newline bitfld.long 0x0 24.--25. "VC0_P_HDR_SCALE,VC0 Scale Posted Header Credites. Note: This register field is sticky." "0,1,2,3" newline bitfld.long 0x0 21.--23. "VC0_P_TLP_Q_MODE,Reserved. Note: This register field is sticky." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 20. "RESERVED4,Reserved. Note: This register field is sticky." "0,1" newline hexmask.long.byte 0x0 12.--19. 1. "VC0_P_HEADER_CREDIT,VC0 Posted Header Credits. The number of initial posted header credits for VC0 used only in the segmented-buffer configuration. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R (sticky) Note: This.." newline hexmask.long.word 0x0 0.--11. 1. "VC0_P_DATA_CREDIT,VC0 Posted Data Credits. The number of initial posted data credits for VC0 used only in the segmented-buffer configuration. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R (sticky) Note: This.." line.long 0x4 "VC0_NP_RX_Q_CTRL_OFF,Segmented-Buffer VC0 Non-Posted Receive Queue Control." hexmask.long.byte 0x4 28.--31. 1. "RESERVED7,Reserved. Note: This register field is sticky." newline bitfld.long 0x4 26.--27. "VC0_NP_DATA_SCALE,VC0 Scale Non-Posted Data Credites. Note: This register field is sticky." "0,1,2,3" newline bitfld.long 0x4 24.--25. "VC0_NP_HDR_SCALE,VC0 Scale Non-Posted Header Credites. Note: This register field is sticky." "0,1,2,3" newline bitfld.long 0x4 21.--23. "VC0_NP_TLP_Q_MODE,Reserved. Note: This register field is sticky." "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 20. "RESERVED6,Reserved. Note: This register field is sticky." "0,1" newline hexmask.long.byte 0x4 12.--19. 1. "VC0_NP_HEADER_CREDIT,VC0 Non-Posted Header Credits. The number of initial non-posted header credits for VC0 used only in the segmented-buffer configuration. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R (sticky).." newline hexmask.long.word 0x4 0.--11. 1. "VC0_NP_DATA_CREDIT,VC0 Non-Posted Data Credits. The number of initial non-posted data credits for VC0 used only in the segmented-buffer configuration. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R (sticky) Note:.." line.long 0x8 "VC0_CPL_RX_Q_CTRL_OFF,Segmented-Buffer VC0 Completion Receive Queue Control." hexmask.long.byte 0x8 28.--31. 1. "RESERVED9,Reserved. Note: This register field is sticky." newline bitfld.long 0x8 26.--27. "VC0_CPL_DATA_SCALE,VC0 Scale CPL Data Credites. Note: This register field is sticky." "0,1,2,3" newline bitfld.long 0x8 24.--25. "VC0_CPL_HDR_SCALE,VC0 Scale CPL Header Credites. Note: This register field is sticky." "0,1,2,3" newline bitfld.long 0x8 21.--23. "VC0_CPL_TLP_Q_MODE,Reserved. Note: This register field is sticky." "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 20. "RESERVED8,Reserved. Note: This register field is sticky." "0,1" newline hexmask.long.byte 0x8 12.--19. 1. "VC0_CPL_HEADER_CREDIT,VC0 Completion Header Credits. The number of initial Completion header credits for VC0 used only in the segmented-buffer configuration. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R (sticky).." newline hexmask.long.word 0x8 0.--11. 1. "VC0_CPL_DATA_CREDIT,VC0 Completion Data Credits. The number of initial Completion data credits for VC0 used only in the segmented-buffer configuration. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R (sticky) Note:.." group.long (0x10C+0x700)++0x3 line.long 0x0 "GEN2_CTRL_OFF,This register is used to control various functions of the controller related to link training. lane reversal. and equalization." rbitfld.long 0x0 31. "RSVDP_31,Reserved for future use." "0,1" newline bitfld.long 0x0 30. "FORCE_LANE_FLIP,Enable to force the LANE_UNDER_TEST physical lane flips to logical lane 0. All the other physical lanes are turned off. The LINK_CAPABLE register must be set to 1 and only x1 link can be formed if the FORCE_LANE_FLIP register is set to 1." "0,1" newline hexmask.long.byte 0x0 24.--27. 1. "LANE_UNDER_TEST,The Lane Under Test is the lane for Forced Lane Flip or for Loopback Eq. The value is from 0 to CX_NL. Only one lane is configured each time. The default of this field is the CX_DEFAULT_LANE_UNDER_TEST configuration parameter. This field.." newline rbitfld.long 0x0 22.--23. "RSVDP_22,Reserved for future use." "0,1,2,3" newline bitfld.long 0x0 21. "GEN1_EI_INFERENCE,Electrical Idle Inference Mode at Gen1 Rate. Programmable mode to determine inferred electrical idle (EI) in Recovery.Speed or Loopback.Active (as slave) state at Gen1 speed by looking for a '1' value on RxElecIdle instead of looking.." "Use RxElecIdle signal to infer Electrical Idle,Use RxValid signal to infer Electrical Idle" newline bitfld.long 0x0 20. "SEL_DEEMPHASIS,Used to set the de-emphasis level for upstream ports. This bit selects the level of de-emphasis the link operates at. - 0: -6 dB - 1: -3.5 dB This field is reserved (fixed to '0') for M-PCIe. Note: The access attributes of this field are.." "0,1" newline bitfld.long 0x0 19. "CONFIG_TX_COMP_RX,Config Tx Compliance Receive Bit. When set to 1 signals LTSSM to transmit TS ordered sets with the compliance receive bit assert (equal to '1'). This field is reserved (fixed to '0') for M-PCIe. Note: The access attributes of this.." "0,1" newline bitfld.long 0x0 18. "CONFIG_PHY_TX_CHANGE,Config PHY Tx Swing. Controls the PHY transmitter voltage swing level. The controller drives the mac_phy_txswing output from this register bit field. - 0: Full Swing - 1: Low Swing This field is reserved (fixed to '0') for M-PCIe." "Full Swing,Low Swing" newline bitfld.long 0x0 17. "DIRECT_SPEED_CHANGE,Directed Speed Change. Writing '1' to this field instructs the LTSSM to initiate a speed change to Gen2 or Gen3 after the link is initialized at Gen1 speed. When the speed change occurs the controller will clear the contents of this.." "0,1" newline bitfld.long 0x0 16. "AUTO_LANE_FLIP_CTRL_EN,Enable Auto flipping of the lanes. You must set the CX_AUTO_LANE_FLIP_CTRL_EN configuration parameter to include the hardware for this feature in the controller. For more details see the 'Lane Reversal' appendix in the Databook." "0,1" newline bitfld.long 0x0 13.--15. "PRE_DET_LANE,Predetermined Lane for Auto Flip. This field defines which physical lane is connected to logical Lane0 by the flip operation performed in Detect. This field is used to restrict the receiver detect procedure to a particular lane when the.." "LANE0,LANE1,LANE3,LANE7,LANE15,?,?,?" newline hexmask.long.byte 0x0 8.--12. 1. "NUM_OF_LANES,Predetermined Number of Lanes. Defines the number of lanes which are connected and not bad. Used to limit the effective link width to ignore 'broken' or 'unused' lanes that detect a receiver. Indicates the number of lanes to check for exit.." newline hexmask.long.byte 0x0 0.--7. 1. "FAST_TRAINING_SEQ,Sets the Number of Fast Training Sequences (N_FTS) that the controller advertises as its N_FTS during Gen2 or Gen3 link training. This value is used to inform the link partner about the PHY's ability to recover synchronization after a.." rgroup.long (0x110+0x700)++0x3 line.long 0x0 "PHY_STATUS_OFF,PHY Status Register. Memory mapped register from phy_cfg_status GPIO input pins." hexmask.long 0x0 0.--31. 1. "PHY_STATUS,PHY Status. Data received directly from the phy_cfg_status bus. These is a GPIO register reflecting the values on the static phy_cfg_status input signals. The usage is left completely to the user and does not in any way influence controller.." group.long (0x114+0x700)++0x3 line.long 0x0 "PHY_CONTROL_OFF,PHY Control Register. Memory mapped register to cfg_phy_control GPIO output pins." hexmask.long 0x0 0.--31. 1. "PHY_CONTROL,PHY Control. Data sent directly to the cfg_phy_control bus. These is a GPIO register driving the values on the static cfg_phy_control output signals. The usage is left completely to the user and does not in any way influence controller.." group.long (0x11C+0x700)++0x77 line.long 0x0 "TRGT_MAP_CTRL_OFF,Programmable Target Map Control Register." hexmask.long.word 0x0 21.--31. 1. "TARGET_MAP_RESERVED_21_31,Reserved. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R (sticky)" newline hexmask.long.byte 0x0 16.--20. 1. "TARGET_MAP_INDEX,The number of the PF Function on which the Target Values are set. This register does not respect the Byte Enable setting. any write will affect all register bits." newline rbitfld.long 0x0 13.--15. "TARGET_MAP_RESERVED_13_15,Reserved. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R (sticky)" "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x0 7.--12. 1. "TARGET_MAP_VF,Target Values for each BAR on the VF Function selected by the index number. This register does not respect the Byte Enable setting. any write will affect all register bits." newline bitfld.long 0x0 6. "TARGET_MAP_ROM,Target Value for the ROM page of the PF Function selected by the index number. This register does not respect the Byte Enable setting. any write will affect all register bits." "0,1" newline hexmask.long.byte 0x0 0.--5. 1. "TARGET_MAP_PF,Target Values for each BAR on the PF Function selected by the index number. This register does not respect the Byte Enable setting. any write will affect all register bits." line.long 0x4 "MSI_CTRL_ADDR_OFF,Integrated MSI Reception Module (iMRM) Address Register." hexmask.long 0x4 0.--31. 1. "MSI_CTRL_ADDR,Integrated MSI Reception Module Address. System specified address for MSI memory write transaction termination. Within the AXI Bridge every received Memory Write request is examined to see if it targets the MSI Address that has been.." line.long 0x8 "MSI_CTRL_UPPER_ADDR_OFF,Integrated MSI Reception Module Upper Address Register." hexmask.long 0x8 0.--31. 1. "MSI_CTRL_UPPER_ADDR,Integrated MSI Reception Module Upper Address. System specified upper address for MSI memory write transaction termination. Allows functions to support a 64-bit MSI address. Note: This register field is sticky." line.long 0xC "MSI_CTRL_INT_0_EN_OFF,Integrated MSI Reception Module Interrupt#i Enable Register." hexmask.long 0xC 0.--31. 1. "MSI_CTRL_INT_0_EN,MSI Interrupt#i Enable. Specifies which interrupts are enabled. When an MSI is received from a disabled interrupt no status bit gets set in MSI controller interrupt status register. Each bit corresponds to a single MSI Interrupt.." line.long 0x10 "MSI_CTRL_INT_0_MASK_OFF,Integrated MSI Reception Module Interrupt#i Mask Register." hexmask.long 0x10 0.--31. 1. "MSI_CTRL_INT_0_MASK,MSI Interrupt#i Mask. Allows enabled interrupts to be masked. When an MSI is received for a masked interrupt the corresponding status bit gets set in the interrupt status register but the msi_ctrl_int output is not set HIGH. Each bit.." line.long 0x14 "MSI_CTRL_INT_0_STATUS_OFF,Integrated MSI Reception Module Interrupt#i Status Register." hexmask.long 0x14 0.--31. 1. "MSI_CTRL_INT_0_STATUS,MSI Interrupt#i Status. When an MSI is detected for EP#i one bit in this register is set. The decoding of the data payload of the MSI Memory Write request determines which bit gets set. A status is bit is cleared by writing a 1 to.." line.long 0x18 "MSI_CTRL_INT_1_EN_OFF,Integrated MSI Reception Module Interrupt#i Enable Register." hexmask.long 0x18 0.--31. 1. "MSI_CTRL_INT_1_EN,MSI Interrupt#i Enable. Specifies which interrupts are enabled. When an MSI is received from a disabled interrupt no status bit gets set in MSI controller interrupt status register. Each bit corresponds to a single MSI Interrupt.." line.long 0x1C "MSI_CTRL_INT_1_MASK_OFF,Integrated MSI Reception Module Interrupt#i Mask Register." hexmask.long 0x1C 0.--31. 1. "MSI_CTRL_INT_1_MASK,MSI Interrupt#i Mask. Allows enabled interrupts to be masked. When an MSI is received for a masked interrupt the corresponding status bit gets set in the interrupt status register but the msi_ctrl_int output is not set HIGH. Each bit.." line.long 0x20 "MSI_CTRL_INT_1_STATUS_OFF,Integrated MSI Reception Module Interrupt#i Status Register." hexmask.long 0x20 0.--31. 1. "MSI_CTRL_INT_1_STATUS,MSI Interrupt#i Status. When an MSI is detected for EP#i one bit in this register is set. The decoding of the data payload of the MSI Memory Write request determines which bit gets set. A status is bit is cleared by writing a 1 to.." line.long 0x24 "MSI_CTRL_INT_2_EN_OFF,Integrated MSI Reception Module Interrupt#i Enable Register." hexmask.long 0x24 0.--31. 1. "MSI_CTRL_INT_2_EN,MSI Interrupt#i Enable. Specifies which interrupts are enabled. When an MSI is received from a disabled interrupt no status bit gets set in MSI controller interrupt status register. Each bit corresponds to a single MSI Interrupt.." line.long 0x28 "MSI_CTRL_INT_2_MASK_OFF,Integrated MSI Reception Module Interrupt#i Mask Register." hexmask.long 0x28 0.--31. 1. "MSI_CTRL_INT_2_MASK,MSI Interrupt#i Mask. Allows enabled interrupts to be masked. When an MSI is received for a masked interrupt the corresponding status bit gets set in the interrupt status register but the msi_ctrl_int output is not set HIGH. Each bit.." line.long 0x2C "MSI_CTRL_INT_2_STATUS_OFF,Integrated MSI Reception Module Interrupt#i Status Register." hexmask.long 0x2C 0.--31. 1. "MSI_CTRL_INT_2_STATUS,MSI Interrupt#i Status. When an MSI is detected for EP#i one bit in this register is set. The decoding of the data payload of the MSI Memory Write request determines which bit gets set. A status is bit is cleared by writing a 1 to.." line.long 0x30 "MSI_CTRL_INT_3_EN_OFF,Integrated MSI Reception Module Interrupt#i Enable Register." hexmask.long 0x30 0.--31. 1. "MSI_CTRL_INT_3_EN,MSI Interrupt#i Enable. Specifies which interrupts are enabled. When an MSI is received from a disabled interrupt no status bit gets set in MSI controller interrupt status register. Each bit corresponds to a single MSI Interrupt.." line.long 0x34 "MSI_CTRL_INT_3_MASK_OFF,Integrated MSI Reception Module Interrupt#i Mask Register." hexmask.long 0x34 0.--31. 1. "MSI_CTRL_INT_3_MASK,MSI Interrupt#i Mask. Allows enabled interrupts to be masked. When an MSI is received for a masked interrupt the corresponding status bit gets set in the interrupt status register but the msi_ctrl_int output is not set HIGH. Each bit.." line.long 0x38 "MSI_CTRL_INT_3_STATUS_OFF,Integrated MSI Reception Module Interrupt#i Status Register." hexmask.long 0x38 0.--31. 1. "MSI_CTRL_INT_3_STATUS,MSI Interrupt#i Status. When an MSI is detected for EP#i one bit in this register is set. The decoding of the data payload of the MSI Memory Write request determines which bit gets set. A status is bit is cleared by writing a 1 to.." line.long 0x3C "MSI_CTRL_INT_4_EN_OFF,Integrated MSI Reception Module Interrupt#i Enable Register." hexmask.long 0x3C 0.--31. 1. "MSI_CTRL_INT_4_EN,MSI Interrupt#i Enable. Specifies which interrupts are enabled. When an MSI is received from a disabled interrupt no status bit gets set in MSI controller interrupt status register. Each bit corresponds to a single MSI Interrupt.." line.long 0x40 "MSI_CTRL_INT_4_MASK_OFF,Integrated MSI Reception Module Interrupt#i Mask Register." hexmask.long 0x40 0.--31. 1. "MSI_CTRL_INT_4_MASK,MSI Interrupt#i Mask. Allows enabled interrupts to be masked. When an MSI is received for a masked interrupt the corresponding status bit gets set in the interrupt status register but the msi_ctrl_int output is not set HIGH. Each bit.." line.long 0x44 "MSI_CTRL_INT_4_STATUS_OFF,Integrated MSI Reception Module Interrupt#i Status Register." hexmask.long 0x44 0.--31. 1. "MSI_CTRL_INT_4_STATUS,MSI Interrupt#i Status. When an MSI is detected for EP#i one bit in this register is set. The decoding of the data payload of the MSI Memory Write request determines which bit gets set. A status is bit is cleared by writing a 1 to.." line.long 0x48 "MSI_CTRL_INT_5_EN_OFF,Integrated MSI Reception Module Interrupt#i Enable Register." hexmask.long 0x48 0.--31. 1. "MSI_CTRL_INT_5_EN,MSI Interrupt#i Enable. Specifies which interrupts are enabled. When an MSI is received from a disabled interrupt no status bit gets set in MSI controller interrupt status register. Each bit corresponds to a single MSI Interrupt.." line.long 0x4C "MSI_CTRL_INT_5_MASK_OFF,Integrated MSI Reception Module Interrupt#i Mask Register." hexmask.long 0x4C 0.--31. 1. "MSI_CTRL_INT_5_MASK,MSI Interrupt#i Mask. Allows enabled interrupts to be masked. When an MSI is received for a masked interrupt the corresponding status bit gets set in the interrupt status register but the msi_ctrl_int output is not set HIGH. Each bit.." line.long 0x50 "MSI_CTRL_INT_5_STATUS_OFF,Integrated MSI Reception Module Interrupt#i Status Register." hexmask.long 0x50 0.--31. 1. "MSI_CTRL_INT_5_STATUS,MSI Interrupt#i Status. When an MSI is detected for EP#i one bit in this register is set. The decoding of the data payload of the MSI Memory Write request determines which bit gets set. A status is bit is cleared by writing a 1 to.." line.long 0x54 "MSI_CTRL_INT_6_EN_OFF,Integrated MSI Reception Module Interrupt#i Enable Register." hexmask.long 0x54 0.--31. 1. "MSI_CTRL_INT_6_EN,MSI Interrupt#i Enable. Specifies which interrupts are enabled. When an MSI is received from a disabled interrupt no status bit gets set in MSI controller interrupt status register. Each bit corresponds to a single MSI Interrupt.." line.long 0x58 "MSI_CTRL_INT_6_MASK_OFF,Integrated MSI Reception Module Interrupt#i Mask Register." hexmask.long 0x58 0.--31. 1. "MSI_CTRL_INT_6_MASK,MSI Interrupt#i Mask. Allows enabled interrupts to be masked. When an MSI is received for a masked interrupt the corresponding status bit gets set in the interrupt status register but the msi_ctrl_int output is not set HIGH. Each bit.." line.long 0x5C "MSI_CTRL_INT_6_STATUS_OFF,Integrated MSI Reception Module Interrupt#i Status Register." hexmask.long 0x5C 0.--31. 1. "MSI_CTRL_INT_6_STATUS,MSI Interrupt#i Status. When an MSI is detected for EP#i one bit in this register is set. The decoding of the data payload of the MSI Memory Write request determines which bit gets set. A status is bit is cleared by writing a 1 to.." line.long 0x60 "MSI_CTRL_INT_7_EN_OFF,Integrated MSI Reception Module Interrupt#i Enable Register." hexmask.long 0x60 0.--31. 1. "MSI_CTRL_INT_7_EN,MSI Interrupt#i Enable. Specifies which interrupts are enabled. When an MSI is received from a disabled interrupt no status bit gets set in MSI controller interrupt status register. Each bit corresponds to a single MSI Interrupt.." line.long 0x64 "MSI_CTRL_INT_7_MASK_OFF,Integrated MSI Reception Module Interrupt#i Mask Register." hexmask.long 0x64 0.--31. 1. "MSI_CTRL_INT_7_MASK,MSI Interrupt#i Mask. Allows enabled interrupts to be masked. When an MSI is received for a masked interrupt the corresponding status bit gets set in the interrupt status register but the msi_ctrl_int output is not set HIGH. Each bit.." line.long 0x68 "MSI_CTRL_INT_7_STATUS_OFF,Integrated MSI Reception Module Interrupt#i Status Register." hexmask.long 0x68 0.--31. 1. "MSI_CTRL_INT_7_STATUS,MSI Interrupt#i Status. When an MSI is detected for EP#i one bit in this register is set. The decoding of the data payload of the MSI Memory Write request determines which bit gets set. A status is bit is cleared by writing a 1 to.." line.long 0x6C "MSI_GPIO_IO_OFF,Integrated MSI Reception Module General Purpose IO Register." hexmask.long 0x6C 0.--31. 1. "MSI_GPIO_REG,MSI GPIO Register. The contents of this register drives the top-level GPIO msi_ctrl_io[31:0] Note: This register field is sticky." line.long 0x70 "CLOCK_GATING_CTRL_OFF,This register enables you to disable dynamic clock gating. By default dynamic clock gating is on. allowing the controller to autonomously enable and disable its clocks. The clock gating is performed in the clock and reset module." hexmask.long 0x70 2.--31. 1. "RSVDP_2,Reserved for future use." newline bitfld.long 0x70 1. "AXI_CLK_GATING_EN,AXI Clock Gating Enable. This register enables the AXI Bridge to autonomously enable and disable the AXI Master clock the AXI Slave clock and the AXI DBI slave clock. The DWC_pcie_clk_rst.v module provides the gated clock.." "Disable,Enable" newline bitfld.long 0x70 0. "RADM_CLK_GATING_EN,RADM Clock Gating Enable. This register if set enables the RADM to autonomously enable and disable its clock. The DWC_pcie_clk_rst.v module provides the gated clock radm_clk_g to the RADM and is enabled when the controllers clock.." "Disable,Enable" line.long 0x74 "GEN3_RELATED_OFF,Gen3 Control Register. There is no Gen3-specific N_FTS field. The N_FTS field in the 'Link Width and Speed Change Control Register' is used for both Gen2 and Gen3 speed modes. There is no Gen3-specific 'Directed Speed Change' field. The.." hexmask.long.byte 0x74 26.--31. 1. "RSVDP_26,Reserved for future use." newline bitfld.long 0x74 23. "GEN3_EQ_INVREQ_EVAL_DIFF_DISABLE,Eq InvalidRequest and RxEqEval Different Time Assertion Disable. Disable the assertion of Eq InvalidRequest and RxEqEval at different time. Note: When CX_GEN4_SPEED/CX_GEN5_SPEED this register is shared for Gen3 and.." "0,1" newline rbitfld.long 0x74 19.--20. "RSVDP_19,Reserved for future use." "0,1,2,3" newline bitfld.long 0x74 18. "GEN3_DC_BALANCE_DISABLE,DC Balance Disable. Disable DC Balance feature. Note: When CX_GEN4_SPEED/CX_GEN5_SPEED this register is shared for Gen3 and Gen4/Gen5 data rate. Note: This register field is sticky." "0,1" newline bitfld.long 0x74 17. "GEN3_DLLP_XMT_DELAY_DISABLE,DLLP Transmission Delay Disable. Disable delay transmission of DLLPs before equalization. Note: When CX_GEN4_SPEED/CX_GEN5_SPEED this register is shared for Gen3 and Gen4/Gen5 data rate. Note: This register field is sticky." "0,1" newline bitfld.long 0x74 16. "GEN3_EQUALIZATION_DISABLE,Equalization Disable. Disable equalization feature. This bit cannot be changed once the LTSSM starts link training. Note: When CX_GEN4_SPEED/CX_GEN5_SPEED this register is shared for Gen3 and Gen4/Gen5 data rate. Note: This.." "0,1" newline rbitfld.long 0x74 14.--15. "RSVDP_14,Reserved for future use." "0,1,2,3" newline bitfld.long 0x74 13. "RXEQ_RGRDLESS_RXTS,When set to '1' the controller as Gen3 EQ master asserts RxEqEval to instruct the PHY to do Rx adaptation and evaluation after a 500ns timeout from a new preset request. - 0: mac_phy_rxeqeval asserts after 1us and 2 TS1 received from.." "mac_phy_rxeqeval asserts after 1us and 2 TS1..,mac_phy_rxeqeval asserts after 500ns regardless.." newline bitfld.long 0x74 12. "RXEQ_PH01_EN,Rx Equalization Phase 0/Phase 1 Hold Enable. When this bit is set the upstream port holds phase 0 (the downstream port holds phase 1) for 10ms. Holding phase 0 or phase 1 can be used to allow sufficient time for Rx Equalization to be.." "Tx equalization only in phase 2/3,No Tx equalization" newline bitfld.long 0x74 11. "EQ_REDO,Equalization Redo Disable. Disable autonomous mechanism for requesting to redo the equalization process. The received presets or coefficients mismatch in Recovery.RcvrLock after Recovery EQ phases causes the EQ redo requests. If the EQ redo is.." "0,1" newline bitfld.long 0x74 10. "EQ_EIEOS_CNT,Equalization EIEOS Count Reset Disable. Disable requesting reset of EIEOS count during equalization. Note: When CX_GEN4_SPEED/CX_GEN5_SPEED this register is shared for Gen3 and Gen4/Gen5 data rate. Note: This register field is sticky." "0,1" newline bitfld.long 0x74 9. "EQ_PHASE_2_3,Equalization Phase 2 and Phase 3 Disable. This applies to downstream ports only. Note: When CX_GEN4_SPEED/CX_GEN5_SPEED this register is shadow register for Gen3 and Gen4/Gen5 data rate. If RATE_SHADOW_SEL==00b this register is for Gen3.." "0,1" newline bitfld.long 0x74 8. "DISABLE_SCRAMBLER_GEN_3,Disable Scrambler for Gen3 and Gen4 Data Rate. The Gen3 and Gen4 scrambler/descrambler within the controller needs to be disabled when the scrambling function is implemented outside of the controller (for example within the PHY)." "0,1" newline hexmask.long.byte 0x74 1.--7. 1. "RSVDP_1,Reserved for future use." newline bitfld.long 0x74 0. "GEN3_ZRXDC_NONCOMPL,Gen3 Receiver Impedance ZRX-DC Not Compliant. Receivers that operate at 8.0 GT/s with an impedance other than the range defined by the ZRX-DC parameter for 2.5 GT/s (40-60 Ohms) must meet additional behavior requirements in the.." "The receiver complies with the ZRX-DC parameter..,The receiver does not comply with the ZRX-DC.." group.long (0x1A8+0x700)++0x7 line.long 0x0 "GEN3_EQ_CONTROL_OFF,Gen3 EQ Control Register. This register controls equalization for Phase2 in an upstream port (USP). or Phase3 in a downstream port (DSP). M-PCIe doesn't have Conventional PCIe Gen3 feature. The registers of this section do not exist." hexmask.long.byte 0x0 27.--31. 1. "RSVDP_27,Reserved for future use." newline bitfld.long 0x0 26. "GEN3_REQ_SEND_CONSEC_EIEOS_FOR_PSET_MAP,Request controller to send back-to-back EIEOS in Recovery.RcvrLock state until presets to coefficients mapping is complete. - 0: Do not request - 1: request Note: Gen3 and Gen4 share the same register bit and have.." "Do not request,request" newline bitfld.long 0x0 25. "GEN3_EQ_PSET_REQ_AS_COEF,GEN3_EQ_PSET_REQ_AS_COEF is an internally reserved field. Do not use. Note: This register field is sticky." "0,1" newline bitfld.long 0x0 24. "GEN3_EQ_FOM_INC_INITIAL_EVAL,Include Initial FOM. Include or not the FOM feedback from the initial preset evaluation performed in the EQ Master when finding the highest FOM among all preset evaluations. - 0: Do not include - 1: Include Note: When.." "Do not include,Include" newline hexmask.long.word 0x0 8.--23. 1. "GEN3_EQ_PSET_REQ_VEC,Preset Request Vector. Requesting of Presets during the initial part of the EQ Master Phase. Encoding scheme is as follows: Bit [15:0] =0x0: No preset is requested and evaluated in EQ Master Phase. Bit [i] =1: 'Preset=i' is requested.." newline rbitfld.long 0x0 7. "RSVDP_7,Reserved for future use." "0,1" newline bitfld.long 0x0 6. "GEN3_LOWER_RATE_EQ_REDO_ENABLE,Support EQ redo and lower rate change: - 0: not support - 1: support Note: Gen3 and Gen4 share the same register bit and have the same feature. Note: This register field is sticky." "not support,support" newline bitfld.long 0x0 5. "GEN3_EQ_EVAL_2MS_DISABLE,Phase2_3 2 ms Timeout Disable. Determine behavior in Phase2 for USP (Phase3 if DSP) when the PHY does not respond within 2ms to the assertion of RxEqEval: - 0: abort the current evaluation stop any attempt to modify the remote.." "abort the current evaluation,ignore the 2ms timeout and continue as normal" newline bitfld.long 0x0 4. "GEN3_EQ_PHASE23_EXIT_MODE,Behavior After 24 ms Timeout (when optimal settings are not found). For a USP: Determine next LTSSM state from Phase2 after 24ms Timeout - 0: Recovery.Speed - 1: Recovery.Equalization.Phase3 When optimal settings are not found.." "Equalization Phase 3 Successful status bit is..,Recovery" newline hexmask.long.byte 0x0 0.--3. 1. "GEN3_EQ_FB_MODE,Feedback Mode. - 0000b: Direction Change - 0001b: Figure Of Merit - 0010b: Reserved - .....: Reserved - 1111b: Reserved Note: When CX_GEN4_SPEED/CX_GEN5_SPEED this register is a shadow register for Gen3 and Gen4/Gen5 data rate. If.." line.long 0x4 "GEN3_EQ_FB_MODE_DIR_CHANGE_OFF,Gen3 EQ Direction Change Feedback Mode Control Register. Equalization controls to be used in Phase2 (USP) or Phase 3 (DSP). when you set the Feedback Mode in 'Gen3 EQ Control Register' to 'Direction Change.' These fields.." hexmask.long.word 0x4 18.--31. 1. "RSVDP_18,Reserved for future use." newline hexmask.long.byte 0x4 14.--17. 1. "GEN3_EQ_FMDC_MAX_POST_CUSROR_DELTA,Convergence Window Aperture for C+1. Post-cursor coefficients maximum delta within the convergence window depth. Allowed range: 0 1 2 ..15. Note: When CX_GEN4_SPEED/CX_GEN5_SPEED this register is shadow register for.." newline hexmask.long.byte 0x4 10.--13. 1. "GEN3_EQ_FMDC_MAX_PRE_CUSROR_DELTA,Convergence Window Aperture for C-1. Pre-cursor coefficients maximum delta within the convergence window depth. Allowed range: 0 1 2 ..15. Note: When CX_GEN4_SPEED/CX_GEN5_SPEED this register is shadow register for Gen3.." newline hexmask.long.byte 0x4 5.--9. 1. "GEN3_EQ_FMDC_N_EVALS,Convergence Window Depth. Number of consecutive evaluations considered in Phase 2/3 when determining if optimal coefficients have been found. Allowed range: 0 1 2 ..16 up to a maximum of CX_GEN3_EQ_COEFQ_DEPTH. When set to 0 EQ.." newline hexmask.long.byte 0x4 0.--4. 1. "GEN3_EQ_FMDC_T_MIN_PHASE23,Minimum Time (in ms) To Remain in EQ Master Phase. The LTSSM stays in EQ Master phase for at least this amount of time before starting to check for convergence of the coefficients. Allowed values 0 1 ... 24. Note: When.." group.long (0x1B4+0x700)++0x27 line.long 0x0 "ORDER_RULE_CTRL_OFF,Order Rule Control Register." hexmask.long.word 0x0 16.--31. 1. "RSVDP_16,Reserved for future use." newline hexmask.long.byte 0x0 8.--15. 1. "CPL_PASS_P,Completion Passing Posted Ordering Rule Control. Determines if CPL can pass halted P queue. - 0: CPL can not pass P (recommended) - 1: CPL can pass P" newline hexmask.long.byte 0x0 0.--7. 1. "NP_PASS_P,Non-Posted Passing Posted Ordering Rule Control. Determines if NP can pass halted P queue. - 0 : NP can not pass P (recommended). - 1 : NP can pass P" line.long 0x4 "PIPE_LOOPBACK_CONTROL_OFF,PIPE Loopback Control Register." bitfld.long 0x4 31. "PIPE_LOOPBACK,PIPE Loopback Enable. Indicates RMMI Loopback if M-PCIe. Note: This register field is sticky." "0,1" newline hexmask.long.byte 0x4 27.--30. 1. "RSVDP_27,Reserved for future use." newline bitfld.long 0x4 24.--26. "RXSTATUS_VALUE,RXSTATUS_VALUE is an internally reserved field. Do not use." "0,1,2,3,4,5,6,7" newline rbitfld.long 0x4 22.--23. "RSVDP_22,Reserved for future use." "0,1,2,3" newline hexmask.long.byte 0x4 16.--21. 1. "RXSTATUS_LANE,RXSTATUS_LANE is an internally reserved field. Do not use. Note: This register field is sticky." newline hexmask.long.word 0x4 0.--15. 1. "LPBK_RXVALID,LPBK_RXVALID is an internally reserved field. Do not use. Note: This register field is sticky." line.long 0x8 "MISC_CONTROL_1_OFF,DBI Read-Only Write Enable Register." hexmask.long.word 0x8 22.--31. 1. "RSVDP_22,Reserved for future use." newline bitfld.long 0x8 21. "P2P_ERR_RPT_CTRL,Determines whether to track completion of transmitted Non-Posted TLPs in P2P mode. - 0: Do not track completion - 1: Track completion Note: This register field is sticky." "Do not track completion,Track completion" newline bitfld.long 0x8 20. "P2P_TRACK_CPL_TO_REG,Determines whether to enable Peer to Peer (P2P) error reporting. - 0: Disable P2P error reporting - 1: Enable P2P error reporting Note: This register field is sticky." "Disable P2P error reporting,Enable P2P error reporting" newline bitfld.long 0x8 18.--19. "TARGET_ABOVE_CONFIG_LIMIT_REG,Configuration requests with an address greater than CONFIG_LIMIT_REG are directed to either ELBI or TRGT1 interface based on the setting of this field. This field can have the following values: - 1: ELBI - 2: TRGT1 Note:.." "?,ELBI,TRGT1,?" newline hexmask.long.word 0x8 8.--17. 1. "CONFIG_LIMIT_REG,Configuration requests are directed either to CDM or ELBI/RTRGT1 based on the value of this field. - Configuration requests with an address less CONFIG_LIMIT_REG are directed to the CDM - Configuration requests with an address greater.." newline bitfld.long 0x8 7. "CFG_TLP_BYPASS_EN_REG,Setting of this field defines which field TARGET_ABOVE_CONFIG_LIMIT_REG or CONFIG_LIMIT_REG decides the destination of Configuration requests. This field can have the following values: - 0: Configuration TLPs are routed according to.." "Configuration TLPs are routed according to the..,Configuration TLPs are routed according to the.." newline bitfld.long 0x8 6. "CPLQ_MNG_EN,This field enables the Completion Queue Management feature. Note: This register field is sticky." "0,1" newline bitfld.long 0x8 5. "ARI_DEVICE_NUMBER,When ARI is enabled this field enables use of the device ID. Note: This register field is sticky." "0,1" newline bitfld.long 0x8 4. "DISABLE_AUTO_LTR_CLR_MSG,Disable the autonomous generation of LTR clear message in upstream port. This field can have the following values: - 0: Allow the autonomous generation of LTR clear message. - 1: Disable the autonomous generation of LTR clear.." "Allow the autonomous generation of LTR clear..,Disable the autonomous generation of LTR clear.." newline bitfld.long 0x8 3. "SIMPLIFIED_REPLAY_TIMER,Enables Simplified Replay Timer (Gen4). For more details see 'Transmit Replay' in 'Transmit TLP Processing' section in the 'Controller Operations' chapter of the Databook. Simplified Replay Timer can have the following Values: -.." "0,1" newline bitfld.long 0x8 2. "UR_CA_MASK_4_TRGT1,When this field is set to '1' the controller suppresses error logging error message generation and CPL generation for non-posted requests TLPs (with UR filtering status) forwarded to your application (that is when DEFAULT_TARGET.." "0,1" newline bitfld.long 0x8 1. "DEFAULT_TARGET,Default target for an IO or MEM request with UR/CA/CRS received. Based on the value of this field the controller either drops or forwards these requests to your application. - 0: The controller drops all incoming I/O or MEM requests (after.." "The controller drops all incoming I/O or MEM..,The controller forwards all incoming I/O or MEM.." newline bitfld.long 0x8 0. "DBI_RO_WR_EN,Write to RO Registers Using DBI. Your application can write to some RO and HwInit register fields through the DBI when you set this field to '1'. For more details see 'Writing to Read-Only Registers' in 'Register Module LBC and DBI'.." "0,1" line.long 0xC "MULTI_LANE_CONTROL_OFF,UpConfigure Multi-lane Control Register. Used when upsizing or downsizing the link width through Configuration state without bringing the link down. For more details. see the 'Link Establishment' section in the 'Controller.." hexmask.long.tbyte 0xC 8.--31. 1. "RSVDP_8,Reserved for future use." newline bitfld.long 0xC 7. "UPCONFIGURE_SUPPORT,Upconfigure Support. The controller sends this value as the Link Upconfigure Capability in TS2 Ordered Sets in Configuration.Complete state. This field is reserved (fixed to '0') for M-PCIe. Note: This register field is sticky." "0,1" newline bitfld.long 0xC 6. "DIRECT_LINK_WIDTH_CHANGE,Directed Link Width Change. The controller always moves to Configuration state through Recovery state when this bit is set to '1'. - If the upconfigure_capable variable is '1' and the PCIE_CAP_HW_AUTO_WIDTH_DISABLE bit in.." "0,1" newline hexmask.long.byte 0xC 0.--5. 1. "TARGET_LINK_WIDTH,Target Link Width. Values correspond to: - 6'b000000: Controller does not start upconfigure or autonomous width downsizing in the Configuration state. - 6'b000001: x1 - 6'b000010: x2 - 6'b000100: x4 - 6'b001000: x8 - 6'b010000: x16 -.." line.long 0x10 "PHY_INTEROP_CTRL_OFF,PHY Interoperability Control Register." hexmask.long.tbyte 0x10 12.--31. 1. "RSVDP_12,Reserved for future use." newline bitfld.long 0x10 10. "L1_CLK_SEL,L1 Clock control bit. This field is reserved for internal use. You should not write to this field and change the default unless specifically instructed by Synopsys support. - 1: Controller does not request aux_clk switch and core_clk gating in.." "Controller requests aux_clk switch and core_clk..,Controller does not request aux_clk switch and.." newline rbitfld.long 0x10 9. "L1_NOWAIT_P1,L1 entry control bit. This field is reserved for internal use. You should not write to this field and change the default unless specifically instructed by Synopsys support. - 1: Controller does not wait for PHY to acknowledge transition to.." "Controller waits for the PHY to acknowledge..,Controller does not wait for PHY to acknowledge.." newline bitfld.long 0x10 8. "L1SUB_EXIT_MODE,L1 Exit Control Using phy_mac_pclkack_n. This field is reserved for internal use. You should not write to this field and change the default unless specifically instructed by Synopsys support. - 1: Controller exits L1 without waiting for.." "Controller waits for the PHY to assert..,Controller exits L1 without waiting for the PHY.." newline rbitfld.long 0x10 7. "RSVDP_7,Reserved for future use." "0,1" newline hexmask.long.byte 0x10 0.--6. 1. "RXSTANDBY_CONTROL,Rxstandby Control. Bits 0..5 determine if the controller asserts the RxStandby signal (mac_phy_rxstandby) in the indicated condition. Bit 6 enables the controller to perform the RxStandby/RxStandbyStatus handshake. This field is.." line.long 0x14 "TRGT_CPL_LUT_DELETE_ENTRY_OFF,TRGT_CPL_LUT Delete Entry Control register. Using this register you can delete one entry in the target completion LUT. You should only use this register when you know that your application will never send the completion.." bitfld.long 0x14 31. "DELETE_EN,This is a one-shot bit. A '1' write to this bit triggers the deletion of the target completion LUT entry that is specified in the LOOK_UP_ID field. This is a self-clearing register field. Reading from this register field always returns a '0'." "0,1" newline hexmask.long 0x14 0.--30. 1. "LOOK_UP_ID,This number selects one entry to delete of the TRGT_CPL_LUT." line.long 0x18 "LINK_FLUSH_CONTROL_OFF,Link Reset Request Flush Control Register." hexmask.long.byte 0x18 24.--31. 1. "RSVD_I_8,This is an internally reserved field. Do not use. Note: This register field is sticky." newline hexmask.long.tbyte 0x18 1.--23. 1. "RSVDP_1,Reserved for future use." newline bitfld.long 0x18 0. "AUTO_FLUSH_EN,Enables automatic flushing of pending requests before sending the reset request to the application logic to reset the PCIe controller and the AXI Bridge. The flushing process is initiated if any of the following events occur: - Hot reset.." "0,1" line.long 0x1C "AMBA_ERROR_RESPONSE_DEFAULT_OFF,AXI Bridge Slave Error Response Register." hexmask.long.word 0x1C 16.--31. 1. "RSVDP_16,Reserved for future use." newline hexmask.long.byte 0x1C 10.--15. 1. "AMBA_ERROR_RESPONSE_MAP,AXI Slave Response Error Map. Allows you to selectively map the errors received from the PCIe completion (for non-posted requests) to the AXI slave responses slv_rresp or slv_bresp. The recommended setting is SLVERR. CRS is.." newline hexmask.long.byte 0x1C 5.--9. 1. "RSVDP_5,Reserved for future use." newline bitfld.long 0x1C 3.--4. "AMBA_ERROR_RESPONSE_CRS,CRS Slave Error Response Mapping. Determines the AXI slave response for CRS completions. For more details see 'Error Handling' in the AXI chapter of the Databook. AHB: - always returns OKAY AXI: - 00: OKAY - 01: OKAY with all.." "OKAY,OKAY with all FFFF_FFFF data for all CRS..,?,?" newline bitfld.long 0x1C 2. "AMBA_ERROR_RESPONSE_VENDORID,Vendor ID Non-existent Slave Error Response Mapping. Determines the AXI slave response for errors on reads to non-existent Vendor ID register. For more details see 'Error Handling' in the AXI chapter of the Databook. AHB: -.." "OKAY,SLVERR/DECERR" newline rbitfld.long 0x1C 1. "RSVDP_1,Reserved for future use." "0,1" newline bitfld.long 0x1C 0. "AMBA_ERROR_RESPONSE_GLOBAL,Global Slave Error Response Mapping. Determines the AXI slave response for all error scenarios on non-posted requests. For more details see 'Error Handling' in the AXI chapter of the Databook. AHB: - 0: OKAY (with FFFF data for.." "OKAY,SLVERR/DECERR" line.long 0x20 "AMBA_LINK_TIMEOUT_OFF,Link Down AXI Bridge Slave Timeout Register. If your application AXI master issues outbound requests to the AXI bridge slave interface before the PCIe link is operational. the controller starts a 'flush' timer. The timeout value of.." hexmask.long.tbyte 0x20 9.--31. 1. "RSVDP_9,Reserved for future use." newline bitfld.long 0x20 8. "LINK_TIMEOUT_ENABLE_DEFAULT,Disable Flush. You can disable the flush feature by setting this field to '1'. Note: This register field is sticky." "0,1" newline hexmask.long.byte 0x20 0.--7. 1. "LINK_TIMEOUT_PERIOD_DEFAULT,Timeout Value (ms). The timer will timeout and then flush the bridge TX request queues after this amount of time. The timer counts when there are pending outbound AXI slave interface requests and the PCIe TX link is not.." line.long 0x24 "AMBA_ORDERING_CTRL_OFF,AMBA Ordering Control." hexmask.long.tbyte 0x24 8.--31. 1. "RSVDP_8,Reserved for future use." newline bitfld.long 0x24 7. "AX_MSTR_ZEROLREAD_FW,AXI Master Zero Length Read Forward to the application. The DW PCIe controller AXI bridge is able to terminate in order with the Posted transactions the zero length read implementing the PCIe express flush semantics of the Posted.." "The zero length Read is terminated at the DW..,The zero length Read is forward to the application" newline rbitfld.long 0x24 5.--6. "RSVDP_5,Reserved for future use." "0,1,2,3" newline bitfld.long 0x24 3.--4. "AX_MSTR_ORDR_P_EVENT_SEL,AXI Master Posted Ordering Event Selector. This field selects how the master interface determines when a P write is completed when enforcing the PCIe ordering rule 'NP must not pass P' at the AXI Master Interface. The AXI.." "B'last event: wait for the all of the write..,AW'last event: wait until the complete Posted..,This setting will not affect:,?" newline rbitfld.long 0x24 2. "RSVDP_2,Reserved for future use." "0,1" newline bitfld.long 0x24 1. "AX_SNP_EN,AXI Serialize Non-Posted Requests Enable. This field enables the AXI Bridge to serialize same ID Non-Posted Read/Write Requests on the wire. Serialization implies one outstanding same ID NP Read or Write on the wire and used to avoid AXI RAR.." "0,1" newline rbitfld.long 0x24 0. "RSVDP_0,Reserved for future use." "0,1" group.long (0x1E0+0x700)++0xB line.long 0x0 "COHERENCY_CONTROL_1_OFF,ACE Cache Coherency Control Register 1" hexmask.long 0x0 2.--31. 1. "CFG_MEMTYPE_BOUNDARY_LOW_ADDR,Boundary Lower Address For Memory Type. Bits [31:0] of dword-aligned address of the boundary for Memory type. The two lower address LSBs are '00'. Addresses up to but not including this value are in the lower address space.." newline rbitfld.long 0x0 1. "RSVDP_1,Reserved for future use." "0,1" newline bitfld.long 0x0 0. "CFG_MEMTYPE_VALUE,Sets the memory type for the lower and upper parts of the address space: - 0: lower = Peripheral; upper = Memory - 1: lower = Memory type; upper = Peripheral Note: This register field is sticky." "lower = Peripheral; upper = Memory,lower = Memory type; upper = Peripheral" line.long 0x4 "COHERENCY_CONTROL_2_OFF,ACE Cache Coherency Control Register 2" hexmask.long 0x4 0.--31. 1. "CFG_MEMTYPE_BOUNDARY_HIGH_ADDR,Boundary Upper Address For Memory Type. Bits [63:32] of the 64-bit dword-aligned address of the boundary for Memory type. Note: This register field is sticky." line.long 0x8 "COHERENCY_CONTROL_3_OFF,ACE Cache Coherency Control Register 3" hexmask.long.byte 0x8 27.--30. 1. "CFG_MSTR_AWCACHE_VALUE,Master Write CACHE Signal Value. Value of the individual bits in mstr_awcache when CFG_MSTR_AWCACHE_MODE is '1'. Note: not applicable to message requests; for message requests the value of mstr_awcache is always '0000' Note: This.." newline hexmask.long.byte 0x8 19.--22. 1. "CFG_MSTR_ARCACHE_VALUE,Master Read CACHE Signal Value. Value of the individual bits in mstr_arcache when CFG_MSTR_ARCACHE_MODE is '1'. Note: This register field is sticky." newline hexmask.long.byte 0x8 11.--14. 1. "CFG_MSTR_AWCACHE_MODE,Master Write CACHE Signal Behavior. Defines how the individual bits in mstr_awcache are controlled: - 0: set automatically by the AXI master - 1: set by the value of the corresponding bit of the CFG_MSTR_AWCACHE_VALUE field Note:.." newline hexmask.long.byte 0x8 3.--6. 1. "CFG_MSTR_ARCACHE_MODE,Master Read CACHE Signal Behavior. Defines how the individual bits in mstr_arcache are controlled: - 0: set automatically by the AXI master - 1: set by the value of the corresponding bit of the CFG_MSTR_ARCACHE_VALUE field Note:.." group.long (0x1F0+0x700)++0x7 line.long 0x0 "AXI_MSTR_MSG_ADDR_LOW_OFF,Lower 20 bits of the programmable AXI address where Messages coming from wire are mapped to. Bits [11:0] of the register are tied to zero for the address to be 4k-aligned. In previous releases. the third and fourth DWORDs of a.." hexmask.long.tbyte 0x0 12.--31. 1. "CFG_AXIMSTR_MSG_ADDR_LOW,Lower 20 bits of the programmable AXI address for Messages. Note: This register field is sticky." newline hexmask.long.word 0x0 0.--11. 1. "CFG_AXIMSTR_MSG_ADDR_LOW_RESERVED,Reserved for future use. Note: This register field is sticky." line.long 0x4 "AXI_MSTR_MSG_ADDR_HIGH_OFF,Upper 32 bits of the programmable AXI address where Messages coming from wire are mapped to." hexmask.long 0x4 0.--31. 1. "CFG_AXIMSTR_MSG_ADDR_HIGH,Upper 32 bits of the programmable AXI address for Messages. Note: This register field is sticky." rgroup.long (0x1F8+0x700)++0x7 line.long 0x0 "PCIE_VERSION_NUMBER_OFF,PCIe Controller IIP Release Version Number. The version number is given in hex format. You should convert each pair of hex characters to ASCII to interpret. Using 4.70a (GA) as an example: - VERSION_NUMBER = 0x3437302a which.." hexmask.long 0x0 0.--31. 1. "VERSION_NUMBER,Version Number." line.long 0x4 "PCIE_VERSION_TYPE_OFF,PCIe Controller IIP Release Version Type. The type is given in hex format. You should convert each pair of hex characters to ASCII to interpret. Using 4.70a (GA) as an example: - VERSION_NUMBER = 0x3437302a which translates to 470*.." hexmask.long 0x4 0.--31. 1. "VERSION_TYPE,Version Type." group.long (0x240+0x700)++0x7 line.long 0x0 "MSIX_ADDRESS_MATCH_LOW_OFF,MSI-X Address Match Low Register. When you enable the MSI-X Table RAM feature (MSIX_TABLE_EN=1). the controller implements the logic and RAM required to generate MSI-X requests. For more details. see the Interrupts section in.." hexmask.long 0x0 2.--31. 1. "MSIX_ADDRESS_MATCH_LOW,MSI-X Address Match Low Address. Note: This register field is sticky." newline rbitfld.long 0x0 1. "MSIX_ADDRESS_MATCH_RESERVED_1,Reserved. Note: This register field is sticky." "0,1" newline bitfld.long 0x0 0. "MSIX_ADDRESS_MATCH_EN,MSI-X Match Enable. Enable the MSI-X Address Match feature when the AXI bridge is present. Note: This register field is sticky." "0,1" line.long 0x4 "MSIX_ADDRESS_MATCH_HIGH_OFF,MSI-X Address Match High Register. When you enable the MSI-X Table RAM feature (MSIX_TABLE_EN=1). the controller implements the logic and RAM required to generate MSI-X requests. For more details. see the Interrupts section in.." hexmask.long 0x4 0.--31. 1. "MSIX_ADDRESS_MATCH_HIGH,MSI-X Address Match High Address. Note: This register field is sticky." wgroup.long (0x248+0x700)++0x3 line.long 0x0 "MSIX_DOORBELL_OFF,MSI-X Doorbell Register. When you enable the MSI-X Table RAM feature (MSIX_TABLE_EN=1). the controller implements the logic and RAM required to generate MSI-X requests. For more details. see the Interrupts section in the 'Controller.." bitfld.long 0x0 29.--31. "MSIX_DOORBELL_RESERVED_29_31,Reserved." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x0 24.--28. 1. "MSIX_DOORBELL_PF,MSIX Doorbell Physical Function. This register determines the Physical Function for the MSI-X transaction." newline hexmask.long.byte 0x0 16.--23. 1. "MSIX_DOORBELL_VF,MSIX Doorbell Virtual Function. This register determines the Virtual Function for the MSI-X transaction." newline bitfld.long 0x0 15. "MSIX_DOORBELL_VF_ACTIVE,MSIX Doorbell Virtual Function Active. This register determines whether a Virtual Function is used to generate the MSI-X transaction." "0,1" newline bitfld.long 0x0 12.--14. "MSIX_DOORBELL_TC,MSIX Doorbell Traffic Class. This register determines which traffic class to generate the MSI-X transaction with." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 11. "MSIX_DOORBELL_RESERVED_11,Reserved." "0,1" newline hexmask.long.word 0x0 0.--10. 1. "MSIX_DOORBELL_VECTOR,MSI-X Doorbell Vector. This register determines which vector to generate the MSI-X transaction for." group.long (0x24C+0x700)++0x3 line.long 0x0 "MSIX_RAM_CTRL_OFF,MSI-X RAM power mode and debug control register. When you enable the MSI-X Table RAM feature (MSIX_TABLE_EN=1). the controller implements the logic and RAM required to generate MSI-X requests. For more details. see the Interrupts.." hexmask.long.byte 0x0 26.--31. 1. "MSIX_RAM_CTRL_RESERVED_26_31,Reserved. Note: This register field is sticky." newline bitfld.long 0x0 25. "MSIX_RAM_CTRL_DBG_PBA,MSIX PBA RAM Debug Mode. Use this bit to activate the debug mode and allow direct read/write access to the PBA. Use can also use the dbg_pba input to activate debug mode. Debug mode turns off the PF/VF/Offset-based addressing into.." "0,1" newline bitfld.long 0x0 24. "MSIX_RAM_CTRL_DBG_TABLE,MSIX Table RAM Debug Mode. Use this bit to activate the debug mode and allow direct read/write access to the Table. Use can also use the dbg_table input to activate debug mode. Debug mode turns off the PF/VF/Offset-based.." "0,1" newline hexmask.long.byte 0x0 17.--23. 1. "MSIX_RAM_CTRL_RESERVED_17_23,Reserved. Note: This register field is sticky." newline bitfld.long 0x0 16. "MSIX_RAM_CTRL_BYPASS,MSIX RAM Control Bypass. The bypass field when set disables the internal generation of low power signals for both RAMs. It is up to the application to ensure the RAMs are in the proper power state before trying to access them." "0,1" newline hexmask.long.byte 0x0 10.--15. 1. "MSIX_RAM_CTRL_RESERVED_10_15,Reserved. Note: This register field is sticky." newline bitfld.long 0x0 9. "MSIX_RAM_CTRL_PBA_SD,MSIX PBA RAM Shut Down. Set this bit to drive the cfg_msix_pba_sd output to signal your external logic to place the MSIX PBA RAM in Shut Down low-power mode. Note: This register field is sticky." "0,1" newline bitfld.long 0x0 8. "MSIX_RAM_CTRL_PBA_DS,MSIX PBA RAM Deep Sleep. Set this bit to drive the cfg_msix_pba_ds output to signal your external logic to place the MSIX PBA RAM in Deep Sleep low-power mode. Note: This register field is sticky." "0,1" newline hexmask.long.byte 0x0 2.--7. 1. "MSIX_RAM_CTRL_RESERVED_2_7,Reserved. Note: This register field is sticky." newline bitfld.long 0x0 1. "MSIX_RAM_CTRL_TABLE_SD,MSIX Table RAM Shut Down. Set this bit to drive the cfg_msix_table_sd output to signal your external logic to place the MSIX Table RAM in Shut Down low-power mode. Note: This register field is sticky." "0,1" newline bitfld.long 0x0 0. "MSIX_RAM_CTRL_TABLE_DS,MSIX Table RAM Deep Sleep. Set this bit to drive the cfg_msix_table_ds output to signal your external logic to place the MSIX Table RAM in Deep Sleep low-power mode. Note: This register field is sticky." "0,1" group.long (0x430+0x700)++0x3 line.long 0x0 "PL_LTR_LATENCY_OFF,LTR Latency Register. The function of this register field (and all other fields in this register) differs between an upstream port and a downstream port. For an upstream port. the register fields capture the corresponding fields in the.." bitfld.long 0x0 31. "NO_SNOOP_LATENCY_REQUIRE,No Snoop Latency Requirement. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" "0,1" newline rbitfld.long 0x0 29.--30. "RSVDP_29,Reserved for future use." "0,1,2,3" newline bitfld.long 0x0 26.--28. "NO_SNOOP_LATENCY_SCALE,No Snoop Latency Scale. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" "0,1,2,3,4,5,6,7" newline hexmask.long.word 0x0 16.--25. 1. "NO_SNOOP_LATENCY_VALUE,No Snoop Latency Value. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" newline bitfld.long 0x0 15. "SNOOP_LATENCY_REQUIRE,Snoop Latency Requirement. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" "0,1" newline rbitfld.long 0x0 13.--14. "RSVDP_13,Reserved for future use." "0,1,2,3" newline bitfld.long 0x0 10.--12. "SNOOP_LATENCY_SCALE,Snoop Latency Scale. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" "0,1,2,3,4,5,6,7" newline hexmask.long.word 0x0 0.--9. 1. "SNOOP_LATENCY_VALUE,Snoop Latency Value. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" group.long (0x440+0x700)++0xB line.long 0x0 "AUX_CLK_FREQ_OFF,Auxiliary Clock Frequency Control Register." hexmask.long.tbyte 0x0 10.--31. 1. "RSVDP_10,Reserved for future use." newline hexmask.long.word 0x0 0.--9. 1. "AUX_CLK_FREQ,The aux_clk frequency in MHz. This value is used to provide a 1 us reference for counting time during low-power states with aux_clk when the PHY has removed the pipe_clk. Frequencies lower than 1 MHz are possible but with a loss of accuracy.." line.long 0x4 "L1_SUBSTATES_OFF,L1 Substates Timing Register." hexmask.long.tbyte 0x4 9.--31. 1. "RSVDP_9,Reserved for future use." newline bitfld.long 0x4 8. "L1SUB_LOW_POWER_CLOCK_SWITCH_MODE,If this bit is set to 1'b1 the reference clock will be running regardless of the CLKREQ# setting. If this bit is set to 1'b0 the reference clock may be gated off when CLKREQ# is de-asserted. If the bit is set to 1'b1 the.." "0,1" newline bitfld.long 0x4 6.--7. "L1SUB_T_PCLKACK,Max delay (in 1us units) between a MAC request to remove the clock on mac_phy_pclkreq_n and a PHY response on phy_mac_pclkack_n. If the PHY does not respond within this time the request is aborted.The actual timeout value will be.." "0,1,2,3" newline hexmask.long.byte 0x4 2.--5. 1. "L1SUB_T_L1_2,Duration (in 1us units) of L1.2. The actual timeout value will be L1SUB_T_L1_2 + 1. Range is 0.15. Note: This register field is sticky." newline bitfld.long 0x4 0.--1. "L1SUB_T_POWER_OFF,Duration (in 1us units) of L1.2.Entry. The actual timeout value will be L1SUB_T_POWER_OFF + 1. Range is 0.3. Note: This register field is sticky." "0,1,2,3" line.long 0x8 "POWERDOWN_CTRL_STATUS_OFF,Powerdown Control and Status Register." hexmask.long.tbyte 0x8 12.--31. 1. "RSVDP_12,Reserved for future use." newline hexmask.long.byte 0x8 8.--11. 1. "POWERDOWN_PHY_POWERDOWN,This field represents the Powerdown value that has been acknowledged by the PHY. It is updated with the value of Powerdown driven by the controller when the PHY has returned the Phystatus acknowledgment for the Powerdown.." newline hexmask.long.byte 0x8 4.--7. 1. "POWERDOWN_MAC_POWERDOWN,This field represents the Powerdown value driven by the controller to the PHY." newline rbitfld.long 0x8 1.--3. "RSVDP_1,Reserved for future use." "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 0. "POWERDOWN_FORCE,This field is a one shot field. Writing a value of 1 to this field causes the controller to complete the P2 Powerdown handshake regardless of whether the PHY has returned Phystatus. This field could be used for debug purposes in event.." "0,1" group.long (0x470+0x700)++0x7 line.long 0x0 "PHY_VIEWPORT_CTLSTS_OFF,PHY Register Viewport Control and Status Register." rbitfld.long 0x0 31. "PHY_VIEWPORT_PENDING,PHY viewport pending. Indicates the access is pending. - 1 : Pending - 0 : Idle This bit is set to 1 when the read/write access has been initiated. This bit is cleared when the access is completed. If phy_reg_clk_g is never activated.." "Idle,Pending" newline rbitfld.long 0x0 30. "PHY_VIEWPORT_STATUS,PHY viewport status. Indicates the status of the latest access. - 1 : Timeout - 0 : No errors If the timeout is detected this bit is set to 1 and PHY_VIEWPORT_PENDING is cleared. This bit is cleared when the read/write access is.." "No errors,Timeout" newline hexmask.long.byte 0x0 23.--29. 1. "RSVDP_23,Reserved for future use." newline bitfld.long 0x0 22. "PHY_VIEWPORT_TIMEOUT_DISABLE,PHY viewport timeout disable. Disables the PHY register access timeout structure. When the timeout is disabled you must ensure that the PHY register accesses are always acknowledged by cr_para_ack. Otherwise.." "0,1" newline bitfld.long 0x0 21. "PHY_VIEWPORT_BCWR,Broadcast write access to all xN sub-blocks. If you need to broadcast the write accesses into all lanes both PHY_VIEWPORT_ADDR[15] and this bit should be 1. Note: This register field is sticky." "0,1" newline bitfld.long 0x0 20. "PHY_VIEWPORT_READ,PHY viewport read. If set a read access is initiated. The value is always 0 when this bit is read. Note: This register field is sticky." "0,1" newline hexmask.long.byte 0x0 16.--19. 1. "PHY_VIEWPORT_NUM,PHY viewport xN sub-block number. Selects one of xN sub-blocks. This register is not used when the write access is initiated with PHY_VIEWPORT_BCWR==1. Note: This register field is sticky." newline hexmask.long.word 0x0 0.--15. 1. "PHY_VIEWPORT_ADDR,PHY viewport address. Indicates the PHY's register address. Please refer to the PHY databook for the address map definition. Note: This register field is sticky." line.long 0x4 "PHY_VIEWPORT_DATA_OFF,PHY Register Viewport Data Register." hexmask.long.word 0x4 16.--31. 1. "RSVDP_16,Reserved for future use." newline hexmask.long.word 0x4 0.--15. 1. "PHY_VIEWPORT_DATA,PHY viewport data. A write access to this register initiates the PHY register write access. By a read access to this register this field returns the latest read data from the PHY register. Note: This register field is sticky." group.long (0x490+0x700)++0x3 line.long 0x0 "PIPE_RELATED_OFF,PIPE Related Register. This register controls the pipe's capabitity. control. and status parameters." hexmask.long.tbyte 0x0 9.--31. 1. "RSVDP_9,Reserved for future use." newline bitfld.long 0x0 8. "PIPE_GARBAGE_DATA_MODE,PIPE Garbage Data Mode. - 0: PIPE Spec compliant mode: The MAC discards any symbols received after the electrical idle ordered-set until RxValid is deasserted. - 1: Special PHY Support mode: The MAC discards any symbols received.." "PIPE Spec compliant mode: The MAC discards any..,Special PHY Support mode: The MAC discards any.." tree.end tree.end tree "PCIE1_VF67" base ad:0xF10A0000 tree "PF0_TYPE1_HDR (PCI-Compatible Configuration Space Header Type1)" group.long 0x0++0x2F line.long 0x0 "TYPE1_DEV_ID_VEND_ID_REG,Device ID and Vendor ID Register." hexmask.long.word 0x0 16.--31. 1. "DEVICE_ID,Device ID. The Device ID register identifies the particular Function. This identifier is allocated by the vendor. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else.." newline hexmask.long.word 0x0 0.--15. 1. "VENDOR_ID,Vendor ID. The Vendor ID register identifies the manufacturer of the Function. Valid vendor identifiers are allocated by the PCI-SIG to ensure uniqueness. It is not permitted to populate this register with a value of FFFFh which is an invalid.." line.long 0x4 "TYPE1_STATUS_COMMAND_REG,Status and Command Register." bitfld.long 0x4 31. "DETECTED_PARITY_ERROR,Detected Parity Error. This bit is set by a Function whenever it receives a Poisoned TLP regardless of the state the Parity Error Response bit in the Command register. The bit is set when the Poisoned TLP is received by a.." "0,1" newline bitfld.long 0x4 30. "SIGNALED_SYS_ERROR,Signaled System Error. This bit is set when a Function sends an ERR_FATAL or ERR_NONFATAL Message and the SERR# Enable bit in the Command register is 1b." "0,1" newline bitfld.long 0x4 29. "RCVD_MASTER_ABORT,Received Master Abort. This bit is set when a Requester receives a Completion with Unsupported Request Completion status. The bit is set when the Unsupported Request is received by a Function's primary side." "0,1" newline bitfld.long 0x4 28. "RCVD_TARGET_ABORT,Received Target Abort. This bit is set when a Requester receives a Completion with Completer Abort Completion status. The bit is set when the Completer Abort is received by a Function's primary side." "0,1" newline bitfld.long 0x4 27. "SIGNALED_TARGET_ABORT,Signaled Target Abort. This bit is set when a Function completes a Posted or Non-Posted Request as a Completer Abort error. This applies to a Function when the Completer Abort was generated by its primary side." "0,1" newline rbitfld.long 0x4 25.--26. "DEV_SEL_TIMING,DEVSEL Timing. This field was originally described in the PCI Local Bus Specification. Its functionality does not apply to PCI Express. The controller hardwires it to 00b." "0,1,2,3" newline bitfld.long 0x4 24. "MASTER_DPE,Master Data Parity Error. This bit is set by a Function if the Parity Error Response bit in the Command register is 1b and either of the following two conditions occurs: - Port receives a Poisoned Completion going downstream - Port transmits a.." "0,1" newline rbitfld.long 0x4 23. "FAST_B2B_CAP,Fast Back-to-Back Transactions Capable. This bit was originally described in the PCI Local Bus Specification. Its functionality does not apply to PCI Express. The controller hardwires this bit to 0b." "0,1" newline rbitfld.long 0x4 22. "RSVDP_22,Reserved for future use." "0,1" newline rbitfld.long 0x4 21. "FAST_66MHZ_CAP,66 MHz Capable. This bit was originally described in the PCI Local Bus Specification. Its functionality does not apply to PCI Express. The controller hardwires this bit to 0b." "0,1" newline rbitfld.long 0x4 20. "CAP_LIST,Capabilities List. Indicates the presence of an Extended Capability list item. Since all PCI Express device Functions are required to implement the PCI Express Capability structure the controller hardwires this bit to 1b." "0,1" newline rbitfld.long 0x4 19. "INT_STATUS,Interrupt Status. When set indicates that an INTx emulation interrupt is pending internally in the Function. INTx emulation interrupts forwarded by Functions from the secondary side are not reflected in this bit. Setting the Interrupt Disable.." "0,1" newline rbitfld.long 0x4 17.--18. "RSVDP_17,Reserved for future use." "0,1,2,3" newline bitfld.long 0x4 16. "IMM_READINESS,Immediate Readiness. This optional bit when set indicates the Function is guaranteed to be ready to successfully complete valid configuration accesses at any time following any reset that the host is capable of issuing Configuration.." "0,1" newline hexmask.long.byte 0x4 11.--15. 1. "RESERV,Reserved." newline bitfld.long 0x4 10. "INT_EN,Interrupt Disable. Controls the ability of a Function to generate INTx emulation interrupts. When set Functions are prevented from asserting INTx interrupts. Note: - Any INTx emulation interrupts already asserted by the Function must be.." "0,1" newline rbitfld.long 0x4 9. "RSVDP_9,Reserved for future use." "0,1" newline bitfld.long 0x4 8. "SERREN,SERR# Enable. When set this bit enables reporting upstream of Non-fatal and Fatal errors detected by the Function. Note: The errors are reported if enabled either through this bit or through the PCI Express specific bits in the Device Control.." "0,1" newline rbitfld.long 0x4 7. "IDSEL,IDSEL Stepping/Wait Cycle Control. This bit was originally described in the PCI Local Bus Specification. Its functionality does not apply to PCI Express. The controller hardwires this bit to 0b." "0,1" newline bitfld.long 0x4 6. "PERREN,Parity Error Response. This bit controls the logging of poisoned TLPs in the Master Data Parity Error bit in the Status register. For more details see the 'Error Registers' section of the PCI Express Base Specification." "0,1" newline rbitfld.long 0x4 5. "VGAPS,VGA Palette Snoop. This bit was originally described in the PCI Local Bus Specification and the PCI-to-PCI Bridge Architecture Specification. Its functionality does not apply to PCI Express. The controller hardwires this bit to 0b." "0,1" newline rbitfld.long 0x4 4. "MWI_EN,Memory Write and Invalidate. This bit was originally described in the PCI Local Bus Specification and the PCI-to-PCI Bridge Architecture Specification. Its functionality does not apply to PCI Express. The controller hardwires this bit to 0b. For.." "0,1" newline rbitfld.long 0x4 3. "SCO,Special Cycle Enable. This bit was originally described in the PCI Local Bus Specification. Its functionality does not apply to PCI Express. The controller hardwires this bit to 0b." "0,1" newline bitfld.long 0x4 2. "BME,Bus Master Enable. This bit controls forwarding of Memory or I/O requests by a port in the Upstream direction. When this bit is 0b Memory and I/O Requests received at a Root Port must be handled as Unsupported Requests (UR) For Non-Posted Requests a.." "0,1" newline bitfld.long 0x4 1. "MSE,Memory Space Enable. This bit controls a Function's response to Memory Space accesses received on its primary side. - When set the Function is enabled to decode the address and further process Memory Space accesses. - When clear all received Memory.." "0,1" newline bitfld.long 0x4 0. "IO_EN,IO Space Enable. This bit controls a Function's response to I/O Space accesses received on its primary side. - When set the Function is enabled to decode the address and further process I/O Space accesses. - When clear all received I/O accesses.." "0,1" line.long 0x8 "TYPE1_CLASS_CODE_REV_ID_REG,Class Code and Revision ID Register." hexmask.long.byte 0x8 24.--31. 1. "BASE_CLASS_CODE,Base Class Code. A code that broadly classifies the type of operation the Function performs. Encodings for base class are provided in the PCI Code and ID Assignment Specification. All unspecified encodings are reserved. Note: The access.." newline hexmask.long.byte 0x8 16.--23. 1. "SUBCLASS_CODE,Sub-Class Code. Specifies a base class sub-class which identifies more specifically the operation of the Function. Encodings for sub-class are provided in the PCI Code and ID Assignment Specification. All unspecified encodings are.." newline hexmask.long.byte 0x8 8.--15. 1. "PROGRAM_INTERFACE,Programming Interface. This field identifies a specific register level programming interface (if any) so that device independent software can interact with the Function. Encodings for interface are provided in the PCI Code and ID.." newline hexmask.long.byte 0x8 0.--7. 1. "REVISION_ID,Revision ID. The value of this field specifies a Function specific revision identifier. The value is chosen by the vendor. Zero is an acceptable value. The Revision ID should be viewed as a vendor defined extension to the Device ID. Note: The.." line.long 0xC "TYPE1_BIST_HDR_TYPE_LAT_CACHE_LINE_SIZE_REG,BIST. Header Type. Latency Timer. and Cache Line Size Register." hexmask.long.byte 0xC 24.--31. 1. "BIST,BIST. This register is used for control and status of BIST. Functions that do not support BIST must hardwire the register to 00h. A Function whose BIST is invoked must not prevent normal operation of the PCI Express Link. Bit descriptions: - [31]:.." newline rbitfld.long 0xC 23. "MULTI_FUNC,Multi-Function Device. - When set indicates that the device may contain multiple Functions but not necessarily. Software is permitted to probe for Functions other than Function 0. - When clear software must not probe for Functions other.." "0,1" newline hexmask.long.byte 0xC 16.--22. 1. "HEADER_TYPE,Header Layout. This field identifies the layout of the second part of the predefined header. The controller uses 000 0001b encoding. The encoding 000 0010b is reserved. This encoding was originally described in the PC Card Standard Electrical.." newline hexmask.long.byte 0xC 8.--15. 1. "LATENCY_MASTER_TIMER,Latency Timer. This register is also referred to as Primary Latency Timer. The Latency Timer was originally described in the PCI Local Bus Specification and the PCI-to-PCI Bridge Architecture Specification. Its functionality does not.." newline hexmask.long.byte 0xC 0.--7. 1. "CACHE_LINE_SIZE,Cache Line Size. The Cache Line Size register is programmed by the system firmware or the operating system to system cache line size. However legacy conventional PCI software may not always be able to program this register correctly.." line.long 0x10 "BAR0_REG,BAR0 Register. System software must build a consistent address map before booting the machine to an operating system. This means it has to determine how much memory is in the system. and how much address space the Functions in the system.." hexmask.long 0x10 4.--31. 1. "BAR0_START,BAR0 Base Address. - Memory Space: Base Address. - IO Space: bits[31:2] are used to map the function into IO space/Base. Address. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R(Sticky)/W(Sticky) if.." newline bitfld.long 0x10 3. "BAR0_PREFETCH,BAR0 Prefetchable. - Memory Space: Set to one if data is pre-fetchable. A Function is permitted to mark a range as prefetchable. If there are no side effects on reads the function returns all bytes on reads regardless of the byte enables.." "0,1" newline bitfld.long 0x10 1.--2. "BAR0_TYPE,BAR0 Type. - Memory Space: Base Address registers that map into Memory Space can be 32 bits or 64 bits wide (to support mapping into a 64-bit address space). The bit encoding is as follows: -- 00: Base register is 32 bits wide and can be mapped.." "Base register is 32 bits wide and can be mapped..,Reserved,?,?" newline bitfld.long 0x10 0. "BAR0_MEM_IO,BAR0 Memory Space Indicator. This bit is used to determine whether the register maps into Memory or I/O Space. Base Address registers that map to Memory Space must return a 0b. Base Address registers that map to I/O Space must return a 1b." "0,1" line.long 0x14 "BAR1_REG,BAR1 Register. System software must build a consistent address map before booting the machine to an operating system. This means it has to determine how much memory is in the system. and how much address space the Functions in the system.." hexmask.long 0x14 4.--31. 1. "BAR1_START,BAR1 Base Address. - Memory Space: Base Address. - IO Space: bits[31:2] are used to map the function into IO space/Base. Address. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R(Sticky)/W(Sticky) if.." newline bitfld.long 0x14 3. "BAR1_PREFETCH,BAR1 Prefetchable. - Memory Space: Set to one if data is pre-fetchable. A Function is permitted to mark a range as prefetchable. If there are no side effects on reads the function returns all bytes on reads regardless of the byte enables.." "0,1" newline bitfld.long 0x14 1.--2. "BAR1_TYPE,BAR1 Type. - Memory Space: Base Address registers that map into Memory Space can be 32 bits or 64 bits wide (to support mapping into a 64-bit address space). The bit encoding is as follows: -- 00: Base register is 32 bits wide and can be mapped.." "Base register is 32 bits wide and can be mapped..,Reserved,?,?" newline bitfld.long 0x14 0. "BAR1_MEM_IO,BAR1 Memory Space Indicator. This bit is used to determine whether the register maps into Memory or I/O Space. Base Address registers that map to Memory Space must return a 0b. Base Address registers that map to I/O Space must return a 1b." "0,1" line.long 0x18 "SEC_LAT_TIMER_SUB_BUS_SEC_BUS_PRI_BUS_REG,Secondary Latency Timer. Subordinate Bus Number. Secondary Bus Number. and Primary Bus Number Register." hexmask.long.byte 0x18 24.--31. 1. "SEC_LAT_TIMER,Secondary Latency Timer. This register does not apply to PCI Express. The controller hardwires it to 00h." newline hexmask.long.byte 0x18 16.--23. 1. "SUB_BUS,Subordinate Bus Number. The Subordinate Bus Number register is used to record the bus number of the highest numbered PCI bus segment which is behind (or subordinate to) the bridge. Configuration software programs the value in this register. The.." newline hexmask.long.byte 0x18 8.--15. 1. "SEC_BUS,Secondary Bus Number. The Secondary Bus Number register is used to record the bus number of the PCI bus segment to which the secondary interface of the bridge is connected. Configuration software programs the value in this register. The bridge.." newline hexmask.long.byte 0x18 0.--7. 1. "PRIM_BUS,Primary Bus Number. This register is not used by PCI Express Functions. It is implemented for compatibility with legacy software." line.long 0x1C "SEC_STAT_IO_LIMIT_IO_BASE_REG,Secondary Status. and I/O Limit and Base Register. The I/O Limit and I/O Base registers are optional and define an address range that is used by the bridge to determine when to forward I/O transactions from one interface to.." bitfld.long 0x1C 31. "SEC_STAT_DPE,Detected Parity Error. This bit is set by a Function when a Poisoned TLP is received by its secondary side regardless of the state the Parity Error Response Enable bit in the Bridge Control register." "0,1" newline bitfld.long 0x1C 30. "SEC_STAT_RCVD_SYS_ERR,Received System Error. This bit is set when the secondary side of a Function receives an ERR_FATAL or ERR_NONFATAL message." "0,1" newline bitfld.long 0x1C 29. "SEC_STAT_RCVD_MSTR_ABRT,Received Master Abort. This bit is set when the secondary side of a Function (for requests initiated by the Type 1 header Function itself) receives a Completion with Unsupported Request Completion status." "0,1" newline bitfld.long 0x1C 28. "SEC_STAT_RCVD_TRGT_ABRT,Received Target Abort. This bit is set when the secondary side of a Function (for requests initiated by the Type 1 header Function itself) receives a Completion with Completer Abort Completion status." "0,1" newline bitfld.long 0x1C 27. "SEC_STAT_SIG_TRGT_ABRT,Signaled Target Abort. This bit is set when the secondary side of the Function (for Requests completed by the Type 1 header Function itself) completes a Posted or Non-Posted request as a Completer Abort error." "0,1" newline rbitfld.long 0x1C 25.--26. "RSVDP_25,Reserved for future use." "0,1,2,3" newline bitfld.long 0x1C 24. "SEC_STAT_MDPE,Master Data Parity Error. This bit is set by a Function if the Parity Error Response Enable bit in the Bridge Control register is set and either of the following two conditions occurs: - Port receives a Poisoned Completion coming Upstream.." "0,1" newline rbitfld.long 0x1C 23. "RSVDP_23,Reserved for future use." "0,1" newline hexmask.long.byte 0x1C 16.--22. 1. "SEC_STAT_RESERV,Reserved." newline hexmask.long.byte 0x1C 12.--15. 1. "IO_LIMIT,I/O Limit Address. These bits correspond to the address[15:12] of IO address range. For the purpose of address decoding the bridge assumes that the lower 12 address bits address[11:0] of the I/O limit address (not implemented in the I/O Limit.." newline rbitfld.long 0x1C 9.--11. "IO_RESERV1,Reserved." "0,1,2,3,4,5,6,7" newline bitfld.long 0x1C 8. "IO_DECODE_BIT8,I/O Addressing Encode (IO Limit Address). This bit encodes the IO addressing capability of the bridge. IO_DECODE_BIT8 indicates the following: - 0h: The bridge supports only 16-bit I/O addressing (for ISA compatibility). For the purpose of.." "0,1" newline hexmask.long.byte 0x1C 4.--7. 1. "IO_BASE,I/O Base Address. These bits correspond to the address[15:12] of IO address range. For the purpose of address decoding the bridge assumes that the lower 12 address bits address[11:0] of the I/O base address (not implemented in the I/O Base.." newline rbitfld.long 0x1C 1.--3. "IO_RESERV,Reserved." "0,1,2,3,4,5,6,7" newline bitfld.long 0x1C 0. "IO_DECODE,I/O Addressing Encode (IO Base Address) This bit encodes the IO addressing capability of the bridge. IO_DECODE indicates the following: - 0h: The bridge supports only 16-bit I/O addressing (for ISA compatibility). For the purpose of address.." "0,1" line.long 0x20 "MEM_LIMIT_MEM_BASE_REG,Memory Limit and Base Register. The Memory Limit and Memory Base registers define a memory mapped address range which is used by the bridge to determine when to forward memory transactions from one interface to the other. If there.." hexmask.long.word 0x20 20.--31. 1. "MEM_LIMIT,Memory Limit Address. These bits correspond to the upper 12 address bits Address[31:20] of 32-bit addresses. For the purpose of address decoding the bridge assumes that the lower 20 address bits Address[19:0] of the memory limit address.." newline hexmask.long.byte 0x20 16.--19. 1. "MEM_LIMIT_RESERV,Reserved." newline hexmask.long.word 0x20 4.--15. 1. "MEM_BASE,Memory Base Address. These bits correspond to the upper 12 address bits Address[31:20] of 32-bit addresses. For the purpose of address decoding the bridge assumes that the lower 20 address bits Address[19:0] of the memory base address (not.." newline hexmask.long.byte 0x20 0.--3. 1. "MEM_BASE_RESERV,Reserved." line.long 0x24 "PREF_MEM_LIMIT_PREF_MEM_BASE_REG,Prefetchable Memory Limit and Base Register. The Prefetchable Memory Limit and Prefetchable Memory Base registers must indicate that 64-bit addresses are supported. as defined in PCI-to-PCI Bridge Architecture.." hexmask.long.word 0x24 20.--31. 1. "PREF_MEM_LIMIT,Prefetchable Memory Limit Address. If the Prefetchable Memory Limit register indicates support for 32-bit addressing then the Prefetchable Limit Upper 32 Bits register is implemented as a read-only register that returns zero when read. If.." newline rbitfld.long 0x24 17.--19. "PREF_RESERV1,Reserved." "0,1,2,3,4,5,6,7" newline rbitfld.long 0x24 16. "PREF_MEM_LIMIT_DECODE,Prefetchable Memory Limit Decode. This bit encodes whether or not the bridge supports 64-bit addresses. Note: This bit is a copy of the PREF_MEM_DECODE bit and always reflects the current value of that bit. The value of.." "0,1" newline hexmask.long.word 0x24 4.--15. 1. "PREF_MEM_BASE,Prefetchable Memory Base Address. If the Prefetchable Memory Base register indicates support for 32-bit addressing then the Prefetchable Base Upper 32 Bits register is implemented as a read-only register that returns zero when read. If the.." newline rbitfld.long 0x24 1.--3. "PREF_RESERV,Reserved." "0,1,2,3,4,5,6,7" newline bitfld.long 0x24 0. "PREF_MEM_DECODE,Prefetchable Memory Base Decode. This bit encodes whether or not the bridge supports 64-bit addresses. Note: By default the bit is set to 1'b1 indicating that 64-bit addresses are supported. If the bridge only supports 32-bit prefetchable.." "0,1" line.long 0x28 "PREF_BASE_UPPER_REG,Prefetchable Base Upper 32 Bits Register. The Prefetchable Base Upper 32 Bits register is an optional extension to the Prefetchable Memory Base register." hexmask.long 0x28 0.--31. 1. "PREF_MEM_BASE_UPPER,Prefetchable Base Upper 32 Bit. If the Prefetchable Memory Base register indicates support for 32-bit addressing then this register is implemented as read-only register that returns zero when read. If the Prefetchable Memory Base.." line.long 0x2C "PREF_LIMIT_UPPER_REG,Prefetchable Limit Upper 32 Bits Register. The Prefetchable Limit Upper 32 Bits register is an optional extension to the Prefetchable Memory Limit register." hexmask.long 0x2C 0.--31. 1. "PREF_MEM_LIMIT_UPPER,Prefetchable Limit Upper 32 Bit. If the Prefetchable Memory Limit register indicate support for 64-bit addressing then this register is implemented as read/write register which must be initialized by configuration software. This.." rgroup.long 0x30++0x3 line.long 0x0 "IO_LIMIT_UPPER_IO_BASE_UPPER_REG,I/O Limit and Base Upper 16 Bits Register. The I/O Limit Upper 16 Bits and I/O Base Upper 16 Bits registers are optional extensions to the I/O Limit and I/O Base registers." hexmask.long.word 0x0 16.--31. 1. "IO_LIMIT_UPPER,I/O Limit Upper 16 Bits. If the I/O Limit register indicates support for 16-bit I/O address decoding then this register is implemented as a read-only register which return zero when read. If the I/O Limit register indicates support for.." newline hexmask.long.word 0x0 0.--15. 1. "IO_BASE_UPPER,I/O Base Upper 16 Bits. If the I/O Base register indicates support for 16-bit I/O address decoding then this register is implemented as a read-only register which return zero when read. If the I/O base register indicates support for 32-bit.." group.long 0x34++0xB line.long 0x0 "TYPE1_CAP_PTR_REG,Capabilities Pointer Register." hexmask.long.tbyte 0x0 8.--31. 1. "RSVDP_8,Reserved for future use." newline hexmask.long.byte 0x0 0.--7. 1. "CAP_POINTER,Capabilities Pointer. This register is used to point to a linked list of capabilities implemented by this Function. Since all PCI Express Functions are required to implement the PCI Express Capability structure this register must point to a.." line.long 0x4 "TYPE1_EXP_ROM_BASE_REG,Expansion ROM Base Address Register. This register is defined to handle the base address and size information for this expansion ROM. The mask for this ROM BAR exists (if implemented) as a shadow register at this address. The.." hexmask.long.tbyte 0x4 11.--31. 1. "EXP_ROM_BASE_ADDRESS,Expansion ROM Base Address. Upper 21 bits of the Expansion ROM base address. The number of bits (out of these 21) that a Function actually implements depends on how much address space the Function requires. The mask for this ROM BAR.." newline hexmask.long.word 0x4 1.--10. 1. "RSVDP_1,Reserved for future use." newline bitfld.long 0x4 0. "ROM_BAR_ENABLE,Expansion ROM Enable. This bit controls whether or not the Function accepts accesses to its expansion ROM. When this bit is 0b the Function's expansion ROM address space is disabled. When the bit is 1b address decoding is enabled using.." "0,1" line.long 0x8 "BRIDGE_CTRL_INT_PIN_INT_LINE_REG,Bridge Control. Interrupt Pin. and Interrupt Line Register." hexmask.long.word 0x8 23.--31. 1. "BRIDGE_CTRL_RESERV,Reserved." newline bitfld.long 0x8 22. "SBR,Secondary Bus Reset. Setting this bit triggers a hot reset on the corresponding PCI Express Port. Software must ensure a minimum reset duration (Trst) as defined in the PCI Local Bus Specification. Software and systems must honor.." "0,1" newline rbitfld.long 0x8 21. "MSTR_ABORT_MODE,Master Abort Mode. This bit was originally described in the PCI-to-PCI Bridge Architecture Specification. Its functionality does not apply to PCI Express. The controller hardwires this bit to 0b. Note: The access attributes of this field.." "0,1" newline rbitfld.long 0x8 20. "VGA_16B_DEC,VGA 16 bit decode. This bit only has meaning if VGA Enable bit is set. This bit enables system configuration software to select between 10-bit and 16-bit I/O address decoding for all VGA I/O register accesses that are forwarded from primary.." "0,1" newline rbitfld.long 0x8 19. "VGA_EN,VGA Enable. Modifies the response by the bridge to VGA compatible addresses. If the VGA Enable bit is set the bridge will positively decode and forward the following accesses on the primary interface to the secondary interface (and conversely.." "0,1" newline bitfld.long 0x8 18. "ISA_EN,ISA Enable. Modifies the response by the bridge to ISA I/O addresses. This applies only to I/O addresses that are enabled by the I/O Base and I/O Limit registers and are in the first 64 KB of I/O address space (0000 0000h to 0000 FFFFh). If this.." "?,KB block" newline bitfld.long 0x8 17. "SERR_EN,SERR# Enable. This bit controls forwarding of ERR_COR ERR_NONFATAL and ERR_FATAL from secondary to primary." "0,1" newline bitfld.long 0x8 16. "PERE,Parity Error Response Enable. This bit controls the logging of poisoned TLPs in the Master Data Parity Error bit in the Secondary Status register." "0,1" newline hexmask.long.byte 0x8 8.--15. 1. "INT_PIN,Interrupt PIN. The Interrupt Pin register register that identifies the legacy interrupt Message(s) the Function uses. Valid values are: - 01h 02h 03h and 04h: map to legacy interrupt Messages for INTA INTB INTC and INTD respectively. - 00h:.." newline hexmask.long.byte 0x8 0.--7. 1. "INT_LINE,Interrupt Line. The Interrupt Line register communicates interrupt line routing information. The register must be implemented by any Function that uses an interrupt pin. Values in this register are programmed by system software and are system.." tree.end tree "PF0_SPCIE_CAP (Secondary PCI Express Capability Structure)" group.long (0x0+0x1A0)++0xF line.long 0x0 "SPCIE_CAP_HEADER_REG,SPCIE Capability Header. For a description of this standard PCIe register. see the PCI Express Specification." hexmask.long.word 0x0 20.--31. 1. "NEXT_OFFSET,Next Capability Offset. For a description of this standard PCIe register field see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky).." hexmask.long.byte 0x0 16.--19. 1. "CAP_VERSION,Capability Version. For a description of this standard PCIe register field see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else.." hexmask.long.word 0x0 0.--15. 1. "EXTENDED_CAP_ID,Secondary PCI Express Extended Capability ID. For a description of this standard PCIe register field see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN.." line.long 0x4 "LINK_CONTROL3_REG,Link Control 3 Register. For a description of this standard PCIe register. see the PCI Express Specification." hexmask.long 0x4 2.--31. 1. "RSVDP_2,Reserved for future use." bitfld.long 0x4 1. "EQ_REQ_INT_EN,Link Equalization Request Interrupt Enable. For a description of this standard PCIe register field see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" "0,1" bitfld.long 0x4 0. "PERFORM_EQ,Perform Equalization. For a description of this standard PCIe register field see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" "0,1" line.long 0x8 "LANE_ERR_STATUS_REG,Lane Error Status Register. For a description of this standard PCIe register. see the PCI Express Specification." hexmask.long 0x8 2.--31. 1. "RSVDP_LANE_ERR_STATUS,Reserved for future use." bitfld.long 0x8 0.--1. "LANE_ERR_STATUS,Lane Error Status Bits per Lane. For a description of this standard PCIe register field see the PCI Express Specification." "0,1,2,3" line.long 0xC "SPCIE_CAP_OFF_0CH_REG,Lane Equalization Control Register for lanes 1 and 0. For a description of this standard PCIe register. see the PCI Express Specification." rbitfld.long 0xC 31. "RSVDP_31,Reserved for future use." "0,1" bitfld.long 0xC 28.--30. "USP_RX_PRESET_HINT1,Upstream Port 8.0 GT/s Receiver Preset Hint 1. The write value is gated with the PCIE_CAP_CROSS_LINK_SUPPORT field of LINK_CAPABILITIES2_REG. For a description of this standard PCIe register field see the PCI Express Specification." "0,1,2,3,4,5,6,7" hexmask.long.byte 0xC 24.--27. 1. "USP_TX_PRESET1,Upstream Port 8.0 GT/s Transmitter Preset 1. The write value is gated with the PCIE_CAP_CROSS_LINK_SUPPORT field of LINK_CAPABILITIES2_REG. For a description of this standard PCIe register field see the PCI Express Specification. Note:.." rbitfld.long 0xC 23. "RSVDP_23,Reserved for future use." "0,1" newline bitfld.long 0xC 20.--22. "DSP_RX_PRESET_HINT1,Downstream Port 8.0 GT/s Receiver Preset Hint 1. For a description of this standard PCIe register field see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if.." "0,1,2,3,4,5,6,7" hexmask.long.byte 0xC 16.--19. 1. "DSP_TX_PRESET1,Downstream Port 8.0 GT/s Transmitter Preset 1. For a description of this standard PCIe register field see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN.." rbitfld.long 0xC 15. "RSVDP_15,Reserved for future use." "0,1" bitfld.long 0xC 12.--14. "USP_RX_PRESET_HINT0,Upstream Port 8.0 GT/s Receiver Preset Hint 0. The write value is gated with the PCIE_CAP_CROSS_LINK_SUPPORT field of LINK_CAPABILITIES2_REG. For a description of this standard PCIe register field see the PCI Express Specification." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0xC 8.--11. 1. "USP_TX_PRESET0,Upstream Port 8.0 GT/s Transmitter Preset 0. The write value is gated with the PCIE_CAP_CROSS_LINK_SUPPORT field of LINK_CAPABILITIES2_REG. For a description of this standard PCIe register field see the PCI Express Specification. Note:.." rbitfld.long 0xC 7. "RSVDP_7,Reserved for future use." "0,1" bitfld.long 0xC 4.--6. "DSP_RX_PRESET_HINT0,Downstream Port 8.0 GT/s Receiver Preset Hint 0. For a description of this standard PCIe register field see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if.." "0,1,2,3,4,5,6,7" hexmask.long.byte 0xC 0.--3. 1. "DSP_TX_PRESET0,Downstream Port 8.0 GT/s Transmitter Preset 0. For a description of this standard PCIe register field see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN.." tree.end tree "PF0_L1SUB_CAP (L1 Substates Capability Structure)" group.long (0x0+0x2E8)++0xF line.long 0x0 "L1SUB_CAP_HEADER_REG,L1 Substates Extended Capability Header. This register provides capbility ID. capability version and next offset value for L1 Substates." hexmask.long.word 0x0 20.--31. 1. "NEXT_OFFSET,Next Capability Offset. This field contains the offset to the next PCI Express Capability structure or 000h if no other items exist in the linked list of Capabilities. For Extended Capabilities implemented in Configuration Space this offset.." hexmask.long.byte 0x0 16.--19. 1. "CAP_VERSION,Capability Version. This field is a PCI-SIG defined version number that indicates the version of the Capability structure present. This field is depends on version of the specification. Note: The access attributes of this field are as.." hexmask.long.word 0x0 0.--15. 1. "EXTENDED_CAP_ID,L1SUB Extended Capability ID. This field is a PCI-SIG defined ID number that indicates the nature and format of the Extended Capability. Extended Capability ID for L1 PM Substates is 001Eh. Note: The access attributes of this field are as.." line.long 0x4 "L1SUB_CAPABILITY_REG,L1 Substates Capability Register. This register provides extended capability of L1 Substates." hexmask.long.byte 0x4 24.--31. 1. "RSVDP_24,Reserved for future use." hexmask.long.byte 0x4 19.--23. 1. "PWR_ON_VALUE_SUPPORT,Port T Power On Value. Along with the Port T_POWER_ON Scale field in the L1 PM Substates Capabilities register sets the time (in us) that this Port requires the port on the opposite side of Link to wait in L1.2.Exit after sampling.." rbitfld.long 0x4 18. "RSVDP_18,Reserved for future use." "0,1" bitfld.long 0x4 16.--17. "PWR_ON_SCALE_SUPPORT,Port T Power On Scale. Specifies the scale used for the Port T_POWER_ON Value field in the L1 PM Substates Capabilities register. Range of values are given below. Required for all Ports for which either the PCI-PM L1.2 Supported bit.." "?,?,?,Reserved" newline hexmask.long.byte 0x4 8.--15. 1. "COMM_MODE_SUPPORT,Port Common Mode Restore Time. Time (in us) required for this Port to re-establish common mode. Required for all Ports for which either the PCI-PM L1.2 Supported bit is Set ASPM L1.2 Supported bit is Set or both are Set otherwise.." rbitfld.long 0x4 5.--7. "RSVDP_5,Reserved for future use." "0,1,2,3,4,5,6,7" bitfld.long 0x4 4. "L1_PMSUB_SUPPORT,L1 PM Substates ECN Supported. When Set this bit indicates that this Port supports L1 PM Substates. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W (sticky)" "0,1" bitfld.long 0x4 3. "L1_1_ASPM_SUPPORT,ASPM L11 Supported. When Set this bit indicates that ASPM L1.1 is supported. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W (sticky)" "0,1" newline bitfld.long 0x4 2. "L1_2_ASPM_SUPPORT,ASPM L12 Supported. When Set this bit indicates that ASPM L1.2 is supported. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W (sticky)" "0,1" bitfld.long 0x4 1. "L1_1_PCIPM_SUPPORT,PCI-PM L11 Supported. When Set this bit indicates that PCI-PM L1.1 is supported and must be Set by all Ports implementing L1 PM Substates. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W (sticky)" "0,1" bitfld.long 0x4 0. "L1_2_PCIPM_SUPPORT,PCI-PM L12 Supported. When Set this bit indicates that PCI-PM L1.2 is supported. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W (sticky)" "0,1" line.long 0x8 "L1SUB_CONTROL1_REG,L1 Substates Control 1 Register. This register provides Controls to extended capability." bitfld.long 0x8 29.--31. "L1_2_TH_SCA,LTR L12 Threshold Scale. This field provides a scale for the value contained within the LTR_L1.2_THRESHOLD_Value.The default value for this field is 000b.Hardware operation is undefined if software writes a Not-Permitted value to this field." "0,1,2,3,4,5,6,7" rbitfld.long 0x8 26.--28. "RSVDP_26,Reserved for future use." "0,1,2,3,4,5,6,7" hexmask.long.word 0x8 16.--25. 1. "L1_2_TH_VAL,LTR L12 Threshold Value. Along with the LTR_L1.2_THRESHOLD_Scale this field indicates the LTR threshold used to determine if entry into L1 results in L1.1 (if enabled) or L1.2 (if enabled). The default value for this field is 00 0000 0000b." hexmask.long.byte 0x8 8.--15. 1. "T_COMMON_MODE,Common Mode Restore Time. Sets value of TCOMMONMODE (in us) which must be used by the Downstream Ports for timing the re-establishment of common mode.This field is of type RsvdP for Upstream Ports. Default value is implementation.." newline hexmask.long.byte 0x8 4.--7. 1. "RSVDP_4,Reserved for future use." bitfld.long 0x8 3. "L1_1_ASPM_EN,ASPM L11 Enable. When Set this bit enables ASPM L1.1.For Ports for which the ASPM L1.1 Supported bit is Clear this bit is permitted to be hardwired to 0.Default value is 0b." "0,1" bitfld.long 0x8 2. "L1_2_ASPM_EN,ASPM L12 Enable. When Set this bit enables ASPM L1.2.For Ports for which the ASPM L1.2 Supported bit is Clear this bit is permitted to be hardwired to 0.Default value is 0b." "0,1" bitfld.long 0x8 1. "L1_1_PCIPM_EN,PCI-PM L11 Enable. When Set this bit enables PCI-PM L1.1. Default value is 0b." "0,1" newline bitfld.long 0x8 0. "L1_2_PCIPM_EN,PCI-PM L12 Enable. When Set this bit enables PCI-PM L1.2.For Ports for which the PCI-PM L1.2 Supported bit is Clear this bit is permitted to be hardwired to 0.Default value is 0b." "0,1" line.long 0xC "L1SUB_CONTROL2_REG,L1 Substates Control 2 Register. This register provides Controls to extended capability." hexmask.long.tbyte 0xC 8.--31. 1. "RSVDP_8,Reserved for future use." hexmask.long.byte 0xC 3.--7. 1. "T_POWER_ON_VALUE,T Power On Value. Along with the T_POWER_ON Scale sets the minimum amount of time (in us) that the Port must wait in L1.2.Exit after sampling CLKREQ# asserted before actively driving the interface.Default value is 00101b. T_POWER_ON is.." rbitfld.long 0xC 2. "RSVDP_2,Reserved for future use." "0,1" bitfld.long 0xC 0.--1. "T_POWER_ON_SCALE,T Power On Scale. Specifies the scale used for T_POWER_ON Value. Range of values are given below. Required for all Ports that support L1.2 otherwise this field is of type RsvdP. This field must only be modified when the ASPM L1.2 Enable.." "?,?,?,Reserved" tree.end tree "PF0_RAS_DES_CAP (RAS D.E.S. Capability Structure (VSEC))" group.long (0x0+0x30C)++0x3 line.long 0x0 "RAS_DES_CAP_HEADER_REG,Vendor-Specific Extended Capability Header. For a description of this standard PCIe register. see the PCI Express Specification." hexmask.long.word 0x0 20.--31. 1. "NEXT_OFFSET,Next Capability Offset. For a description of this standard PCIe register field see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky).." newline hexmask.long.byte 0x0 16.--19. 1. "CAP_VERSION,Capability Version. For a description of this standard PCIe register field see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else.." newline hexmask.long.word 0x0 0.--15. 1. "EXTENDED_CAP_ID,PCI Express Extended Capability ID. For a description of this standard PCIe register field see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then.." rgroup.long (0x4+0x30C)++0x3 line.long 0x0 "VENDOR_SPECIFIC_HEADER_REG,Vendor-Specific Header. For a description of this standard PCIe register. see the PCI Express Specification." hexmask.long.word 0x0 20.--31. 1. "VSEC_LENGTH,VSEC Length. For a description of this standard PCIe register field see the PCI Express Specification." newline hexmask.long.byte 0x0 16.--19. 1. "VSEC_REV,VSEC Rev. For a description of this standard PCIe register field see the PCI Express Specification." newline hexmask.long.word 0x0 0.--15. 1. "VSEC_ID,VSEC ID. For a description of this standard PCIe register field see the PCI Express Specification." group.long (0x8+0x30C)++0x3 line.long 0x0 "EVENT_COUNTER_CONTROL_REG,Event Counter Control. This is a viewport control register. - Setting the EVENT_COUNTER_EVENT_SELECT and EVENT_COUNTER_LANE_SELECT fields in this register determine the Event Counter data returned by the EVENT_COUNTER_DATA_REG.." hexmask.long.byte 0x0 28.--31. 1. "RSVDP_28,Reserved for future use." newline hexmask.long.word 0x0 16.--27. 1. "EVENT_COUNTER_EVENT_SELECT,Event Counter Data Select. This field in conjunction with the EVENT_COUNTER_LANE_SELECT field indexes the Event Counter data returned by the EVENT_COUNTER_DATA_REG register. - 27-24: Group number(4-bit: 0..0x7) - 23-16: Event.." newline hexmask.long.byte 0x0 12.--15. 1. "RSVDP_12,Reserved for future use." newline hexmask.long.byte 0x0 8.--11. 1. "EVENT_COUNTER_LANE_SELECT,Event Counter Lane Select. This field in conjunction with EVENT_COUNTER_EVENT_SELECT indexes the Event Counter data returned by the EVENT_COUNTER_DATA_REG register. - 0x0: Lane0 - 0x1: Lane1 - 0x2: Lane2 - .. - 0xF: Lane15 Note:.." newline rbitfld.long 0x0 7. "EVENT_COUNTER_STATUS,Event Counter Status. This register returns the current value of the Event Counter selected by the following fields: - EVENT_COUNTER_EVENT_SELECT - EVENT_COUNTER_LANE_SELECT Note: This register field is sticky." "0,1" newline rbitfld.long 0x0 5.--6. "RSVDP_5,Reserved for future use." "0,1,2,3" newline bitfld.long 0x0 2.--4. "EVENT_COUNTER_ENABLE,Event Counter Enable. Enables/disables the Event Counter selected by the EVENT_COUNTER_EVENT_SELECT and EVENT_COUNTER_LANE_SELECT fields in this register. By default all event counters are disabled. You can enable/disable a specific.." "no change,per event off,?,?,?,?,?,?" newline bitfld.long 0x0 0.--1. "EVENT_COUNTER_CLEAR,Event Counter Clear. Clears the Event Counter selected by the EVENT_COUNTER_EVENT_SELECT and EVENT_COUNTER_LANE_SELECT fields in this register. You can clear the value of a specific Event Counter by writing the 'per clear' code and.." "no change,per clear,?,?" rgroup.long (0xC+0x30C)++0x3 line.long 0x0 "EVENT_COUNTER_DATA_REG,Event Counter Data. This viewport register returns the data selected by the following fields: - EVENT_COUNTER_EVENT_SELECT in EVENT_COUNTER_CONTROL_REG - EVENT_COUNTER_LANE_SELECT in EVENT_COUNTER_CONTROL_REG For more details. see.." hexmask.long 0x0 0.--31. 1. "EVENT_COUNTER_DATA,Event Counter Data. This register returns the data selected by the following fields: - EVENT_COUNTER_EVENT_SELECT in EVENT_COUNTER_CONTROL_REG - EVENT_COUNTER_LANE_SELECT in EVENT_COUNTER_CONTROL_REG Note: This register field is sticky." group.long (0x10+0x30C)++0x3 line.long 0x0 "TIME_BASED_ANALYSIS_CONTROL_REG,Time-based Analysis Control. Used for controlling the measurement of RX/TX data throughput and time spent in each low-power LTSSM state. For more details. see the RAS DES section in the Core Operations chapter of the.." hexmask.long.byte 0x0 24.--31. 1. "TIME_BASED_REPORT_SELECT,Time-based Report Select. Selects what type of data is measured for the selected duration (TIME_BASED_DURATION_SELECT) and returned in TIME_BASED_ANALYSIS_DATA. Each type of data is measured using one of three types of units: -.." newline hexmask.long.byte 0x0 16.--23. 1. "RSVDP_16,Reserved for future use." newline hexmask.long.byte 0x0 8.--15. 1. "TIME_BASED_DURATION_SELECT,Time-based Duration Select. Selects the duration of time-based analysis. When 'manual control' is selected and TIMER_START is set to '1' this analysis never stops until TIMER_STOP is set to '0'. - 0x0: Manual control - 0x1:.." newline hexmask.long.byte 0x0 1.--7. 1. "RSVDP_1,Reserved for future use." newline bitfld.long 0x0 0. "TIMER_START,Timer Start. - 1: Start/Restart - 0: Stop This bit will be cleared automatically when the measurement is finished. Note: The app_ras_des_tba_ctrl input also sets the contents of this field and controls the measurement start/stop. Note: This.." "Stop,Start/Restart" rgroup.long (0x14+0x30C)++0x7 line.long 0x0 "TIME_BASED_ANALYSIS_DATA_REG,Time-based Analysis Data. Contains the measurement results of RX/TX data throughput and time spent in each low-power LTSSM state. This viewport register returns the data selected by the TIME_BASED_REPORT_SELECT field in.." hexmask.long 0x0 0.--31. 1. "TIME_BASED_ANALYSIS_DATA,Time Based Analysis Data. This register returns the data selected by the TIME_BASED_REPORT_SELECT field in TIME_BASED_ANALYSIS_CONTROL_REG. The results are cleared when next measurement starts. Note: This register field is sticky." line.long 0x4 "TIME_BASED_ANALYSIS_DATA_63_32_REG,Upper 32 bits of Time-based Analysis Data. This viewport register returns the data selected by the TIME_BASED_REPORT_SELECT field in TIME_BASED_ANALYSIS_CONTROL_REG. For more details. see the RAS DES section in the Core.." hexmask.long 0x4 0.--31. 1. "TIME_BASED_ANALYSIS_DATA_63_32,Upper 32 bits of Time Based Analysis Data. Note: This register field is sticky." group.long (0x30+0x30C)++0x5F line.long 0x0 "EINJ_ENABLE_REG,Error Injection Enable. Each type of error insertion is enabled by the corresponding bit in this register. The specific injection controls for each type of error are defined in the following registers: - 0: CRC Error: EINJ0_CRC_REG - 1:.." hexmask.long 0x0 7.--31. 1. "RSVDP_7,Reserved for future use." newline bitfld.long 0x0 6. "ERROR_INJECTION6_ENABLE,Error Injection6 Enable (Specific TLP Error). Enables insertion of errors into the packets that you select. You can set this bit to '1' when you have disabled RAS datapath protection (DP) by setting CX_RASDP = CX_RASDP_RAM_PROT.." "0,1" newline bitfld.long 0x0 5. "ERROR_INJECTION5_ENABLE,Error Injection5 Enable (TLP Duplicate/Nullify Error). Enables insertion of duplicate/nullified TLPs. For more details see the EINJ5_SP_TLP_REG register. Note: This register field is sticky." "0,1" newline bitfld.long 0x0 4. "ERROR_INJECTION4_ENABLE,Error Injection4 Enable (FC Credit Update Error). Enables insertion of errors into UpdateFCs. For more details see the EINJ4_FC_REG register. Note: This register field is sticky." "0,1" newline bitfld.long 0x0 3. "ERROR_INJECTION3_ENABLE,Error Injection3 Enable (Symbol DataK Mask Error or Sync Header Error). Enables DataK masking of special symbols or the breaking of the sync header. For more details see the EINJ3_SYMBOL_REG register. Note: This register field is.." "0,1" newline bitfld.long 0x0 2. "ERROR_INJECTION2_ENABLE,Error Injection2 Enable (DLLP Error). Enables insertion of DLLP errors. For more details see the EINJ2_DLLP_REG register. Note: This register field is sticky." "0,1" newline bitfld.long 0x0 1. "ERROR_INJECTION1_ENABLE,Error Injection1 Enable (Sequence Number Error). Enables insertion of errors into sequence numbers. For more details see the EINJ1_SEQNUM_REG register. Note: This register field is sticky." "0,1" newline bitfld.long 0x0 0. "ERROR_INJECTION0_ENABLE,Error Injection0 Enable (CRC Error). Enables insertion of errors into various CRC. For more details see the EINJ0_CRC_REG register. Note: This register field is sticky." "0,1" line.long 0x4 "EINJ0_CRC_REG,Error Injection Control 0 (CRC Error). Controls the insertion of errors into the CRC. and parity of ordered sets for the selected type of the packets as follows: - LCRC. Bad TLP will be detected at the receiver side; receiver responds with.." hexmask.long.tbyte 0x4 12.--31. 1. "RSVDP_12,Reserved for future use." newline hexmask.long.byte 0x4 8.--11. 1. "EINJ0_CRC_TYPE,Error injection type. Selects the type of CRC error to be inserted. Tx Path - 0000b: New TLP's LCRC error injection - 0001b: 16bCRC error injection of ACK/NAK DLLP - 0010b: 16bCRC error injection of Update-FC DLLP - 0011b: New TLP's ECRC.." newline hexmask.long.byte 0x4 0.--7. 1. "EINJ0_COUNT,Error injection count. Indicates the number of errors. This register is decremented when the errors have been inserted. - If the counter value is 0x01 and error is inserted ERROR_INJECTION0_ENABLE in EINJ_ENABLE_REG returns 0b. - If the.." line.long 0x8 "EINJ1_SEQNUM_REG,Error Injection Control 1 (Sequence Number Error). Controls the sequence number of the specific TLPs and ACK/NAK DLLPs. Data Link Protocol Error will be detected at the Rx side of ACK/NAL DLLPs when one of these conditions is true: -.." rbitfld.long 0x8 29.--31. "RSVDP_29,Reserved for future use." "0,1,2,3,4,5,6,7" newline hexmask.long.word 0x8 16.--28. 1. "EINJ1_BAD_SEQNUM,Bad sequence number. Indicates the value to add/subtract from the naturally-assigned sequence numbers. This value is represented by two's complement. - 0x0FFF: +4095 - .. - 0x0002: +2 - 0x0001: +1 - 0x0000: 0 - 0x1FFF: -1 - 0x1FFE: -2 -.." newline hexmask.long.byte 0x8 9.--15. 1. "RSVDP_9,Reserved for future use." newline bitfld.long 0x8 8. "EINJ1_SEQNUM_TYPE,Sequence number type. Selects the type of sequence number. - 0b: Insertion of New TLP's SEQ# error - 1b: Insertion of ACK/NAK DLLP's SEQ# Error Note: This register field is sticky." "0,1" newline hexmask.long.byte 0x8 0.--7. 1. "EINJ1_COUNT,Error injection count. Indicates the number of errors. This register is decremented as the errors are being inserted. - If the counter value is 0x01 and error is inserted ERROR_INJECTION1_ENABLE in EINJ_ENABLE_REG returns '0'. - If the.." line.long 0xC "EINJ2_DLLP_REG,Error Injection Control 2 (DLLP Error). Controls the transmission of DLLPs and inserts the following errors: - If 'ACK/NAK DLLP's transmission block' is selected. replay timeout error will occur at the transmitter of the TLPs and then Data.." hexmask.long.tbyte 0xC 10.--31. 1. "RSVDP_10,Reserved for future use." newline bitfld.long 0xC 8.--9. "EINJ2_DLLP_TYPE,DLLP Type. Selects the type of DLLP errors to be inserted. - 00b: ACK/NAK DLLP's transmission block - 01b: Update FC DLLP's transmission block - 10b: Always Transmission for NAK DLLP - 11b: Reserved Note: This register field is sticky." "0,1,2,3" newline hexmask.long.byte 0xC 0.--7. 1. "EINJ2_COUNT,Error injection count. Indicates the number of errors. This register is decremented as the errors are being inserted. - If the counter value is 0x01 and the error is inserted ERROR_INJECTION2_ENABLE in EINJ_ENABLE_REG returns '0'. - If the.." line.long 0x10 "EINJ3_SYMBOL_REG,Error Injection Control 3 (Symbol Error). When 8b/10b encoding is used. this register controls error insertion into the special (K code) symbols. - If TS1/TS2/FTS/E-Idle/SKP is selected. it affects whole of the ordered set. It might.." hexmask.long.tbyte 0x10 11.--31. 1. "RSVDP_11,Reserved for future use." newline bitfld.long 0x10 8.--10. "EINJ3_SYMBOL_TYPE,Error Type. 8b/10b encoding - Mask K symbol. It is not supported to insert errors into the first ordered-set after exiting from TxElecIdle when CX_FREQ_STEP_EN has been enabled. - 000b: Reserved - 001b: COM/PAD(TS1 Order set) - 010b:.." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x10 0.--7. 1. "EINJ3_COUNT,Error injection count. Indicates the number of errors. This register is decremented as the errors are being inserted. - If the counter value is 0x01 and error is inserted ERROR_INJECTION3_ENABLE in EINJ_ENABLE_REG returns '0'. - If the.." line.long 0x14 "EINJ4_FC_REG,Error Injection Control 4 (FC Credit Error). Controls error insertion into the credit value in the UpdateFCs. It is possible to insert errors for any of the following types: - Posted TLP Header credit - Non-Posted TLP Header credit -.." rbitfld.long 0x14 29.--31. "RSVDP_29,Reserved for future use." "0,1,2,3,4,5,6,7" newline hexmask.long.word 0x14 16.--28. 1. "EINJ4_BAD_UPDFC_VALUE,Bad update-FC credit value. Indicates the value to add/subtract from the UpdateFC credit. This value is represented by two's complement. - 0x0FFF: +4095 - .. - 0x0002: +2 - 0x0001: +1 - 0x0000: 0 - 0x1FFF: -1 - 0x1FFE: -2 - .. -.." newline rbitfld.long 0x14 15. "RSVDP_15,Reserved for future use." "0,1" newline bitfld.long 0x14 12.--14. "EINJ4_VC_NUMBER,VC Number. Indicates target VC Number. Note: This register field is sticky." "0,1,2,3,4,5,6,7" newline rbitfld.long 0x14 11. "RSVDP_11,Reserved for future use." "0,1" newline bitfld.long 0x14 8.--10. "EINJ4_UPDFC_TYPE,Update-FC type. Selects the credit type. - 000b: Posted TLP Header Credit value control - 001b: Non-Posted TLP Header Credit value control - 010b: Completion TLP Header Credit value control - 011b: Reserved - 100b: Posted TLP Data Credit.." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x14 0.--7. 1. "EINJ4_COUNT,Error injection count. Indicates the number of errors. This register is decremented as the errors are being inserted. - If the counter value is 0x01 and error is inserted ERROR_INJECTION4_ENABLE in EINJ_ENABLE_REG returns '0'. - If the.." line.long 0x18 "EINJ5_SP_TLP_REG,Error Injection Control 5 (Specific TLP Error). Controls the generation of specified TLPs. Correctable errors will occur which will be fixed by the PCIe protocol. - For Duplicate TLP. the controller initiates Data Link Retry by handling.." hexmask.long.tbyte 0x18 9.--31. 1. "RSVDP_9,Reserved for future use." newline bitfld.long 0x18 8. "EINJ5_SPECIFIED_TLP,Specified TLP. Selects the specified TLP to be inserted. - 0: Generates duplicate TLPs by handling ACK DLLP as NAK DLLP. - 1: Generates Nullified TLP (Original TLP will be stored in retry buffer). Note: This register field is sticky." "Generates duplicate TLPs by handling ACK DLLP as..,Generates Nullified TLP" newline hexmask.long.byte 0x18 0.--7. 1. "EINJ5_COUNT,Error injection count. Indicates the number of errors. This register is decremented as the errors are being inserted. - If the counter value is 0x01 and error is inserted ERROR_INJECTION5_ENABLE in EINJ_ENABLE_REG returns '0'. - If the.." line.long 0x1C "EINJ6_COMPARE_POINT_H0_REG,Error Injection Control 6 (Compare Point Header DWORD #0). Program this register for the 1st DWORD of TLP header/prefix. It is necessary to carefully consider the endianness when you program this register. Bits [31:0] =.." hexmask.long 0x1C 0.--31. 1. "EINJ6_COMPARE_POINT_H0,Packet Compare Point: 1st DWORD. Specifies which Tx TLP header DWORD#0 bits to compare with the corresponding bits in the Packet Compare Value registers (EINJ6_COMPARE_VALUE*). When all specified bits (in the Tx TLP header and.." line.long 0x20 "EINJ6_COMPARE_POINT_H1_REG,Error Injection Control 6 (Compare Point Header DWORD #1). Program this register for the 2nd DWORD of TLP header/prefix. It is necessary to carefully consider the endianness when you program this register. Bits [31:0] =.." hexmask.long 0x20 0.--31. 1. "EINJ6_COMPARE_POINT_H1,Packet Compare Point: 2nd DWORD. Specifies which Tx TLP header DWORD#1 bits to compare with the corresponding bits in the Packet Compare Value registers (EINJ6_COMPARE_VALUE*). When all specified bits (in the Tx TLP header and.." line.long 0x24 "EINJ6_COMPARE_POINT_H2_REG,Error Injection Control 6 (Compare Point Header DWORD #2). Program this register for the 3rd DWORD of TLP header/prefix. It is necessary to carefully consider the endianness when you program this register. Bits [31:0] =.." hexmask.long 0x24 0.--31. 1. "EINJ6_COMPARE_POINT_H2,Packet Compare Point: 3rd DWORD. Specifies which Tx TLP header DWORD#2 bits to compare with the corresponding bits in the Packet Compare Value registers (EINJ6_COMPARE_VALUE*). When all specified bits (in the Tx TLP header and.." line.long 0x28 "EINJ6_COMPARE_POINT_H3_REG,Error Injection Control 6 (Compare Point Header DWORD #3). Program this register for the 4th DWORD of TLP header/prefix. It is necessary to carefully consider the endianness when you program this register. Bits [31:0] =.." hexmask.long 0x28 0.--31. 1. "EINJ6_COMPARE_POINT_H3,Packet Compare Point: 4th DWORD. Specifies which Tx TLP header DWORD#3 bits to compare with the corresponding bits in the Packet Compare Value registers (EINJ6_COMPARE_VALUE*). When all specified bits (in the Tx TLP header and.." line.long 0x2C "EINJ6_COMPARE_VALUE_H0_REG,Error Injection Control 6 (Compare Value Header DWORD #0). Program this register for the 1st DWORD of TLP header/prefix. It is necessary to carefully consider the endianness when you program this register. Bits [31:0] =.." hexmask.long 0x2C 0.--31. 1. "EINJ6_COMPARE_VALUE_H0,Packet Compare Value: 1st DWORD. Specifies the value to compare against Tx the TLP header DWORD#0 bits specified in the Packet Compare Point registers (EINJ6_COMPARE_POINT*). Note: This register field is sticky." line.long 0x30 "EINJ6_COMPARE_VALUE_H1_REG,Error Injection Control 6 (Compare Value Header DWORD #1). Program this register for the 2nd DWORD of TLP header/prefix. It is necessary to carefully consider the endianness when you program this register. Bits [31:0] =.." hexmask.long 0x30 0.--31. 1. "EINJ6_COMPARE_VALUE_H1,Packet Compare Value: 2nd DWORD. Specifies the value to compare against Tx the TLP header DWORD#1 bits specified in the Packet Compare Point registers (EINJ6_COMPARE_POINT*). Note: This register field is sticky." line.long 0x34 "EINJ6_COMPARE_VALUE_H2_REG,Error Injection Control 6 (Compare Value Header DWORD #2). Program this register for the 3rd DWORD of TLP header/prefix. It is necessary to carefully consider the endianness when you program this register. Bits [31:0] =.." hexmask.long 0x34 0.--31. 1. "EINJ6_COMPARE_VALUE_H2,Packet Compare Value: 3rd DWORD. Specifies the value to compare against Tx the TLP header DWORD#2 bits specified in the Packet Compare Point registers (EINJ6_COMPARE_POINT*). Note: This register field is sticky." line.long 0x38 "EINJ6_COMPARE_VALUE_H3_REG,Error Injection Control 6 (Compare Value Header DWORD #3). Program this register for the 4th DWORD of TLP header/prefix. It is necessary to carefully consider the endianness when you program this register. Bits [31:0] =.." hexmask.long 0x38 0.--31. 1. "EINJ6_COMPARE_VALUE_H3,Packet Compare Value: 4th DWORD. Specifies the value to compare against Tx the TLP header DWORD#3 bits specified in the Packet Compare Point registers (EINJ6_COMPARE_POINT*). Note: This register field is sticky." line.long 0x3C "EINJ6_CHANGE_POINT_H0_REG,Error Injection Control 6 (Change Point Header DWORD #0). Program this register for the 1st DWORD of TLP header/prefix. It is necessary to carefully consider the endianness when you program this register. Bits [31:0] =.." hexmask.long 0x3C 0.--31. 1. "EINJ6_CHANGE_POINT_H0,Packet Change Point: 1st DWORD. Specifies which Tx TLP header DWORD#0 bits to replace with the corresponding bits in the Packet Change Value registers (EINJ6_CHANGE_VALUE*). Note: This register field is sticky." line.long 0x40 "EINJ6_CHANGE_POINT_H1_REG,Error Injection Control 6 (Change Point Header DWORD #1). Program this register for the 2nd DWORD of TLP header/prefix. It is necessary to carefully consider the endianness when you program this register. Bits [31:0] =.." hexmask.long 0x40 0.--31. 1. "EINJ6_CHANGE_POINT_H1,Packet Change Point: 2nd DWORD. Specifies which Tx TLP header DWORD#1 bits to replace with the corresponding bits in the Packet Change Value registers (EINJ6_CHANGE_VALUE*). Note: This register field is sticky." line.long 0x44 "EINJ6_CHANGE_POINT_H2_REG,Error Injection Control 6 (Change Point Header DWORD #2). Program this register for the 3rd DWORD of TLP header/prefix. It is necessary to carefully consider the endianness when you program this register. Bits [31:0] =.." hexmask.long 0x44 0.--31. 1. "EINJ6_CHANGE_POINT_H2,Packet Change Point: 3rd DWORD. Specifies which Tx TLP header DWORD#2 bits to replace with the corresponding bits in the Packet Change Value registers (EINJ6_CHANGE_VALUE*). Note: This register field is sticky." line.long 0x48 "EINJ6_CHANGE_POINT_H3_REG,Error Injection Control 6 (Change Point Header DWORD #3). Program this register for the 4th DWORD of TLP header/prefix. It is necessary to carefully consider the endianness when you program this register. Bits [31:0] =.." hexmask.long 0x48 0.--31. 1. "EINJ6_CHANGE_POINT_H3,Packet Change Point: 4th DWORD. Specifies which Tx TLP header DWORD#3 bits to replace with the corresponding bits in the Packet Change Value registers (EINJ6_CHANGE_VALUE*). Note: This register field is sticky." line.long 0x4C "EINJ6_CHANGE_VALUE_H0_REG,Error Injection Control 6 (Change Value Header DWORD #0). Program this register for the 1st DWORD of TLP header/prefix. It is necessary to carefully consider the endianness when you program this register. Bits [31:0] =.." hexmask.long 0x4C 0.--31. 1. "EINJ6_CHANGE_VALUE_H0,Packet Change Value: 1st DWORD. Specifies replacement values for the Tx TLP header DWORD#0 bits defined in the Packet Change Point registers (EINJ6_CHANGE_POINT*). Only applies when the EINJ6_INVERTED_CONTROL field in EINJ6_TLP_REG.." line.long 0x50 "EINJ6_CHANGE_VALUE_H1_REG,Error Injection Control 6 (Change Value Header DWORD #1). Program this register for the 2nd DWORD of TLP header/prefix. It is necessary to carefully consider the endianness when you program this register. Bits [31:0] =.." hexmask.long 0x50 0.--31. 1. "EINJ6_CHANGE_VALUE_H1,Packet Change Value: 2nd DWORD. Specifies replacement values for the Tx TLP header DWORD#1 bits defined in the Packet Change Point registers (EINJ6_CHANGE_POINT*). Only applies when the EINJ6_INVERTED_CONTROL field in EINJ6_TLP_REG.." line.long 0x54 "EINJ6_CHANGE_VALUE_H2_REG,Error Injection Control 6 (Change Value Header DWORD #2). Program this register for the 3rd DWORD of TLP header/prefix. It is necessary to carefully consider the endianness when you program this register. Bits [31:0] =.." hexmask.long 0x54 0.--31. 1. "EINJ6_CHANGE_VALUE_H2,Packet Change Value: 3rd DWORD. Specifies replacement values for the Tx TLP header DWORD#2 bits defined in the Packet Change Point registers (EINJ6_CHANGE_POINT*). Only applies when the EINJ6_INVERTED_CONTROL field in EINJ6_TLP_REG.." line.long 0x58 "EINJ6_CHANGE_VALUE_H3_REG,Error Injection Control 6 (Change Value Header DWORD #3). Program this register for the 4th DWORD of TLP header/prefix. It is necessary to carefully consider the endianness when you program this register. Bits [31:0] =.." hexmask.long 0x58 0.--31. 1. "EINJ6_CHANGE_VALUE_H3,Packet Change Value: 4th DWORD. Specifies replacement values for the Tx TLP header DWORD#3 bits defined in the Packet Change Point registers (EINJ6_CHANGE_POINT*). Only applies when the EINJ6_INVERTED_CONTROL field in EINJ6_TLP_REG.." line.long 0x5C "EINJ6_TLP_REG,Error Injection Control 6 (Packet Error). The Packet Compare Point registers (EINJ6_COMPARE_POINT*) specify which Tx TLP header bits to compare with the corresponding bits in the Packet Compare Value registers (EINJ6_COMPARE_VALUE*). When.." hexmask.long.tbyte 0x5C 12.--31. 1. "RSVDP_12,Reserved for future use." newline bitfld.long 0x5C 9.--11. "EINJ6_PACKET_TYPE,Packet type. Selects the TLP packets to inject errors into. - 0: TLP Header - 1: TLP Prefix 1st 4-DWORDs - 2: TLP Prefix 2nd -DWORDs - Else: Reserved Note: This register field is sticky." "TLP Header,TLP Prefix 1st 4-DWORDs,TLP Prefix 2nd -DWORDs,?,?,?,?,?" newline bitfld.long 0x5C 8. "EINJ6_INVERTED_CONTROL,Inverted Error Injection Control. - 0: EINJ6_CHANGE_VALUE_H[0/1/2/3] is used to replace bits specified by EINJ6_CHANGE_POINT_H[0/1/2/3]. - 1: EINJ6_CHANGE_VALUE_H[0/1/2/3] is ignored and inverts bits specified by.." "EINJ6_CHANGE_VALUE_H[0/1/2/3] is used to replace..,EINJ6_CHANGE_VALUE_H[0/1/2/3] is ignored and.." newline hexmask.long.byte 0x5C 0.--7. 1. "EINJ6_COUNT,Error Injection Count. Indicates the number of errors to insert. This counter is decremented while errors are been inserted. - If the counter value is 0x01 and error is inserted ERROR_INJECTION6_ENABLE in EINJ_ENABLE_REG returns '0'. - If.." group.long (0xA0+0x30C)++0x7 line.long 0x0 "SD_CONTROL1_REG,Silicon Debug Control 1. For more details. see the RAS DES section in the Core Operations chapter of the Databook." hexmask.long.byte 0x0 24.--31. 1. "RSVDP_24,Reserved for future use." newline bitfld.long 0x0 22.--23. "LOW_POWER_INTERVAL,Low Power Entry Interval Time. Interval Time that the controller starts monitoring RXELECIDLE signal after L0s/L1/L2 entry. You should set the value according to the latency from receiving EIOS to RXELECIDLE assertion at the PHY. -.." "0,1,2,3" newline bitfld.long 0x0 20.--21. "TX_EIOS_NUM,Number of Tx EIOS. This register sets the number of transmit EIOS for L0s/L1 entry and Disable/Loopback/Hot-reset exit. The controller selects the greater value between this register and the value defined by the PCI-SIG specification. 2.5GT/s.." "0,1,2,3" newline rbitfld.long 0x0 17.--19. "RSVDP_17,Reserved for future use." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 16. "FORCE_DETECT_LANE_EN,Force Detect Lane Enable. When this bit is set the controller ignores receiver detection from PHY during LTSSM Detect state and uses FORCE_DETECT_LANE. Note: This register field is sticky." "0,1" newline hexmask.long.word 0x0 0.--15. 1. "FORCE_DETECT_LANE,Force Detect Lane. When the FORCE_DETECT_LANE_EN field is set the controller ignores receiver detection from PHY during LTSSM Detect state and uses this value instead. - 0: Lane0 - 1: Lane1 - 2: Lane2 - .. - 15: Lane15 Note: This.." line.long 0x4 "SD_CONTROL2_REG,Silicon Debug Control 2. For more details. see the RAS DES section in the Core Operations chapter of the Databook." hexmask.long.word 0x4 17.--31. 1. "RSVDP_17,Reserved for future use." newline bitfld.long 0x4 16. "FRAMING_ERR_RECOVERY_DISABLE,Framing Error Recovery Disable. This bit disables a transition to Recovery state when a Framing Error is occurred. Note: This register field is sticky." "0,1" newline hexmask.long.byte 0x4 11.--15. 1. "RSVDP_11,Reserved for future use." newline bitfld.long 0x4 10. "DIRECT_LPBKSLV_TO_EXIT,Direct Loopback Slave To Exit. When this bit is set and the LTSSM is in Loopback Slave Active State the LTSSM transitions to Loopback Slave Exit state. Note: This register field is sticky." "0,1" newline bitfld.long 0x4 9. "DIRECT_POLCOMP_TO_DETECT,Direct Polling.Compliance to Detect. When this bit is set and the LTSSM is in Polling Compliance State the LTSSM transitions to Detect state. Note: This register field is sticky." "0,1" newline bitfld.long 0x4 8. "DIRECT_RECIDLE_TO_CONFIG,Direct Recovery.Idle to Configuration. When this bit is set and the LTSSM is in Recovery Idle State the LTSSM transitions to Configuration state. Note: This register field is sticky." "0,1" newline hexmask.long.byte 0x4 3.--7. 1. "RSVDP_3,Reserved for future use." newline bitfld.long 0x4 2. "NOACK_FORCE_LINKDOWN,Force LinkDown. When this bit is set and the controller detects REPLY_NUM rolling over 4 times the LTSSM transitions to Detect State. Note: This register field is sticky." "0,1" newline bitfld.long 0x4 1. "RECOVERY_REQUEST,Recovery Request. When this bit is set to '1' in L0 or L0s the LTSSM starts transitioning to Recovery State. This request does not cause a speed change or re-equalization." "0,1" newline bitfld.long 0x4 0. "HOLD_LTSSM,Hold and Release LTSSM. For as long as this register is '1' the controller stays in the current LTSSM. Note: This register field is sticky." "0,1" group.long (0xB0+0x30C)++0xB line.long 0x0 "SD_STATUS_L1LANE_REG,Silicon Debug Status(Layer1 Per-lane). This viewport register returns the data selected by the following field: - LANE_SELECT in SD_STATUS_L1LANE_REG For more details. see the RAS DES section in the Core Operations chapter of the.." hexmask.long.byte 0x0 24.--31. 1. "DESKEW_POINTER,Deskew Pointer. Indicates Deskew pointer of internal Deskew buffer of selected lane number(LANE_SELECT). Note: This register field is sticky." newline rbitfld.long 0x0 21.--23. "RSVDP_21,Reserved for future use." "0,1,2,3,4,5,6,7" newline rbitfld.long 0x0 20. "PIPE_TXELECIDLE,PIPE:TxElecIdle. Indicates PIPE TXELECIDLE signal of selected lane number(LANE_SELECT). Note: This register field is sticky." "0,1" newline rbitfld.long 0x0 19. "PIPE_RXELECIDLE,PIPE:RxElecIdle. Indicates PIPE RXELECIDLE signal of selected lane number(LANE_SELECT). Note: This register field is sticky." "0,1" newline rbitfld.long 0x0 18. "PIPE_RXVALID,PIPE:RxValid. Indicates PIPE RXVALID signal of selected lane number(LANE_SELECT). Note: This register field is sticky." "0,1" newline rbitfld.long 0x0 17. "PIPE_DETECT_LANE,PIPE:Detect Lane. Indicates whether PHY indicates receiver detection or not on selected lane number(LANE_SELECT). Note: This register field is sticky." "0,1" newline rbitfld.long 0x0 16. "PIPE_RXPOLARITY,PIPE:RxPolarity. Indicates PIPE RXPOLARITY signal of selected lane number(LANE_SELECT). Note: This register field is sticky." "0,1" newline hexmask.long.word 0x0 4.--15. 1. "RSVDP_4,Reserved for future use." newline hexmask.long.byte 0x0 0.--3. 1. "LANE_SELECT,Lane Select. Lane Select register for Silicon Debug Status Register of Layer1-PerLane. - 0x0: Lane0 - 0x1: Lane1 - 0x2: Lane2 - .. - 0xF: Lane15 Note: This register field is sticky." line.long 0x4 "SD_STATUS_L1LTSSM_REG,Silicon Debug Status(Layer1 LTSSM). For more details. see the RAS DES section in the Core Operations chapter of the Databook." hexmask.long.word 0x4 16.--31. 1. "LTSSM_VARIABLE,LTSSM Variable. Indicates internal LTSSM variables defined in the PCI Express Base Specification. C-PCIe Mode: - 0: directed_speed_change - 1: changed_speed_recovery - 2: successful_speed_negotiation - 3: upconfigure_capable; Set to '1' if.." newline rbitfld.long 0x4 15. "LANE_REVERSAL,Lane Reversal Operation. Receiver detected lane reversal. This field is only valid in the L0 LTSSM state. Note: This register field is sticky." "0,1" newline hexmask.long.byte 0x4 11.--14. 1. "RSVDP_11,Reserved for future use." newline rbitfld.long 0x4 8.--10. "PIPE_POWER_DOWN,PIPE:PowerDown. Indicates PIPE PowerDown signal. Note: This register field is sticky." "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 7. "FRAMING_ERR,Framing Error. Indicates Framing Error detection status." "0,1" newline hexmask.long.byte 0x4 0.--6. 1. "FRAMING_ERR_PTR,First Framing Error Pointer. Identifies the first Framing Error using the following encoding. The field contents are only valid value when FRAMING_ERR =1. Received Unexpected Framing Token - 01h: When non- STP/SDP/IDL Token was received.." line.long 0x8 "SD_STATUS_PM_REG,Silicon Debug Status(PM). For more details. see the RAS DES section in the Core Operations chapter of the Databook." hexmask.long.byte 0x8 24.--31. 1. "RSVDP_24,Reserved for future use." newline hexmask.long.byte 0x8 16.--23. 1. "LATCHED_NFTS,Latched N_FTS. Indicates the value of N_FTS in the received TS Ordered Sets from the Link Partner Note: This register field is sticky." newline rbitfld.long 0x8 13.--15. "L1SUB_STATE,L1Sub State. Indicates internal state machine of L1Sub state. - 0h: S_L1_U : idle state - 1h: S_L1_0 : wait for aux_clk_active - 2h: S_L1_0_WAIT4_ACK : wait for pclkack - 3h: S_L1_0_WAIT4_CLKREQ : wait for clkreq - 4h: S_L1_N_ENTRY : check.." "wait for aux_clk_active,?,?,?,?,?,?,?" newline bitfld.long 0x8 12. "PME_RESEND_FLAG,PME Re-send flag. When the DUT sends a PM_PME message TLP the DUT sets PME_Status bit. If host software does not clear PME_Status bit for 100ms(+50%/-5%) the DUT resends the PM_PME Message. This bit indicates that a PM_PME was resent." "0,1" newline hexmask.long.byte 0x8 8.--11. 1. "INTERNAL_PM_SSTATE,Internal PM State(Slave). Indicates internal state machine of Power Management Slave controller. - 0h: S_IDLE - 1h: S_RESPOND_NAK - 2h: S_BLOCK_TLP - 3h: S_WAIT_LAST_TLP_ACK - 4h: S_WAIT_EIDLE - 5h: S_LINK_ENTR_L1 - 6h: S_L1 - 7h:.." newline rbitfld.long 0x8 5.--7. "RSVDP_5,Reserved for future use." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x8 0.--4. 1. "INTERNAL_PM_MSTATE,Internal PM State(Master). Indicates internal state machine of Power Management Master controller. - 00h: IDLE - 01h: L0 - 02h: L0S - 03h: ENTER_L0S - 04h: L0S_EXIT - 05h: WAIT_PMCSR_CPL_SENT - 08h: L1 - 09h: L1_BLOCK_TLP - 0Ah:.." rgroup.long (0xBC+0x30C)++0x3 line.long 0x0 "SD_STATUS_L2_REG,Silicon Debug Status(Layer2). For more details. see the RAS DES section in the Core Operations chapter of the Databook." hexmask.long.byte 0x0 28.--31. 1. "RSVDP_28,Reserved for future use." newline bitfld.long 0x0 27. "FC_INIT2,FC_INIT2. Indicates the controller is in FC_INIT2(VC0) state. Note: This register field is sticky." "0,1" newline bitfld.long 0x0 26. "FC_INIT1,FC_INIT1. Indicates the controller is in FC_INIT1(VC0) state. Note: This register field is sticky." "0,1" newline bitfld.long 0x0 24.--25. "DLCMSM,DLCMSM. Indicates the current DLCMSM. - 00b: DL_INACTIVE - 01b: DL_FC_INIT - 11b: DL_ACTIVE Note: This register field is sticky." "0,1,2,3" newline hexmask.long.word 0x0 12.--23. 1. "RX_ACK_SEQ_NO,Tx Ack Sequence Number. Indicates ACKD_SEQ which is updated by receiving ACK/NAK DLLP. Note: This register field is sticky." newline hexmask.long.word 0x0 0.--11. 1. "TX_TLP_SEQ_NO,Tx Tlp Sequence Number. Indicates next transmit sequence number for transmit TLP. Note: This register field is sticky." group.long (0xC0+0x30C)++0x7 line.long 0x0 "SD_STATUS_L3FC_REG,Silicon Debug Status(Layer3 FC). The CREDIT_DATA[0/1] fields in this viewport register return the data for the VC and TLP Type selected by the following fields: - CREDIT_SEL_VC - CREDIT_SEL_CREDIT_TYPE - CREDIT_SEL_TLP_TYPE -.." hexmask.long.word 0x0 20.--31. 1. "CREDIT_DATA1,Credit Data1. Current FC credit data selected by the CREDIT_SEL_VC CREDIT_SEL_CREDIT_TYPE CREDIT_SEL_TLP_TYPE and CREDIT_SEL_HD viewport-select fields. - Rx: Credit Allocated Value - Tx: Credit Limit Value. This value is valid when.." newline hexmask.long.word 0x0 8.--19. 1. "CREDIT_DATA0,Credit Data0. Current FC credit data selected by the CREDIT_SEL_VC CREDIT_SEL_CREDIT_TYPE CREDIT_SEL_TLP_TYPE and CREDIT_SEL_HD viewport-select fields. - Rx: Credit Received Value - Tx: Credit Consumed Value Note: This register field is.." newline rbitfld.long 0x0 7. "RSVDP_7,Reserved for future use." "0,1" newline bitfld.long 0x0 6. "CREDIT_SEL_HD,Credit Select(HeaderData). This field in conjunction with the CREDIT_SEL_VC CREDIT_SEL_CREDIT_TYPE and CREDIT_SEL_TLP_TYPE viewport-select fields determines that data that is returned by the CREDIT_DATA0 and CREDIT_DATA1 data fields. -.." "Header Credit,Data Credit" newline bitfld.long 0x0 4.--5. "CREDIT_SEL_TLP_TYPE,Credit Select(TLP Type). This field in conjunction with the CREDIT_SEL_VC CREDIT_SEL_CREDIT_TYPE and CREDIT_SEL_HD viewport-select fields determines that data that is returned by the CREDIT_DATA0 and CREDIT_DATA1 data fields. - 0x0:.." "Posted,Non-Posted,Completion,?" newline bitfld.long 0x0 3. "CREDIT_SEL_CREDIT_TYPE,Credit Select(Credit Type). This field in conjunction with the CREDIT_SEL_VC CREDIT_SEL_TLP_TYPE and CREDIT_SEL_HD viewport-select fields determines that data that is returned by the CREDIT_DATA0 and CREDIT_DATA1 data fields. -.." "Rx,Tx" newline bitfld.long 0x0 0.--2. "CREDIT_SEL_VC,Credit Select(VC). This field in conjunction with the CREDIT_SEL_CREDIT_TYPE CREDIT_SEL_TLP_TYPE and CREDIT_SEL_HD viewport-select fields determines that data that is returned by the CREDIT_DATA0 and CREDIT_DATA1 data fields. - 0x0: VC0 -.." "VC0,VC1,VC2,?,?,?,?,VC7" line.long 0x4 "SD_STATUS_L3_REG,Silicon Debug Status(Layer3). For more details. see the RAS DES section in the Core Operations chapter of the Databook." hexmask.long.tbyte 0x4 8.--31. 1. "RSVDP_8,Reserved for future use." newline bitfld.long 0x4 7. "MFTLP_STATUS,Malformed TLP Status. Indicates malformed TLP has occurred." "0,1" newline hexmask.long.byte 0x4 0.--6. 1. "MFTLP_POINTER,First Malformed TLP Error Pointer. Indicates the element of the received first malformed TLP. This pointer is validated by MFTLP_STATUS. - 01h: AtomicOp address alignment - 02h: AtomicOp operand - 03h: AtomicOp byte enable - 04h: TLP length.." group.long (0xD0+0x30C)++0xB line.long 0x0 "SD_EQ_CONTROL1_REG,Silicon Debug EQ Control 1. This is a viewport control register. Setting the EQ_RATE_SEL and EQ_LANE_SEL fields in this register determine the per-lane Silicon Debug EQ Status data returned by the SD_EQ_STATUS[1/2/3] viewport.." hexmask.long.byte 0x0 24.--31. 1. "FOM_TARGET,FOM Target. Indicates figure of merit target criteria value of EQ Master(DSP in EQ Phase3/USP in EQ Phase2). This field is only valid when GEN3_EQ_FB_MODE is 0001b(Figure Of Merit). Note: This register field is sticky." newline bitfld.long 0x0 23. "FOM_TARGET_ENABLE,FOM Target Enable. Enables the FOM_TARGET fields. Note: This register field is sticky." "0,1" newline hexmask.long.byte 0x0 18.--22. 1. "RSVDP_18,Reserved for future use." newline bitfld.long 0x0 16.--17. "EVAL_INTERVAL_TIME,Eval Interval Time. Indicates interval time of RxEqEval assertion. - 00: 500ns - 01: 1us - 10: 2us - 11: 4us This field is used for EQ Master(DSP in EQ Phase3/USP in EQ Phase2). Note: This register field is sticky." "0,1,2,3" newline hexmask.long.byte 0x0 10.--15. 1. "RSVDP_10,Reserved for future use." newline bitfld.long 0x0 8.--9. "EXT_EQ_TIMEOUT,Extends EQ Phase2/3 Timeout. This field is used when the Ltssm is in Recovery.EQ2/3. When this field is set the value of EQ2/3 timeout is extended. EQ Master(DSP in EQ Phase3/USP in EQ Phase2). - 00: 24ms (default) - 01: 48ms (x2) - 10:.." "0,1,2,3" newline rbitfld.long 0x0 6.--7. "RSVDP_6,Reserved for future use." "0,1,2,3" newline bitfld.long 0x0 4.--5. "EQ_RATE_SEL,EQ Status Rate Select. Setting this field in conjunction with the EQ_LANE_SEL field determines the per-lane Silicon Debug EQ Status data returned by the SD_EQ_CONTROL[2/3] and SD_EQ_STATUS[1/2/3] viewport registers. - 0x0: 8.0GT/s Speed.." "0,1,2,3" newline hexmask.long.byte 0x0 0.--3. 1. "EQ_LANE_SEL,EQ Status Lane Select. Setting this field in conjunction with the EQ_RATE_SEL field determines the per-lane Silicon Debug EQ Status data returned by the SD_EQ_CONTROL[2/3] and SD_EQ_STATUS[1/2/3] viewport registers. - 0x0: Lane0 - 0x1: Lane1.." line.long 0x4 "SD_EQ_CONTROL2_REG,Silicon Debug EQ Control 2. This viewport register returns the value for the rate and lane selected by the EQ_RATE_SEL and EQ_LANE_SEL fields in the SD_EQ_CONTROL1_REG register. For more details. see the RAS DES section in the Core.." rbitfld.long 0x4 31. "RSVDP_31,Reserved for future use." "0,1" newline bitfld.long 0x4 30. "FORCE_LOCAL_TX_PRESET_ENABLE,Force Local Transmitter Preset Enable. Enables the FORCE_LOCAL_TX_PRESET field. If select rate in the EQ_RATE_SEL field is 32.0GT/s Speed this feature is not available. Note: This register field is sticky." "0,1" newline bitfld.long 0x4 29. "FORCE_LOCAL_RX_HINT_ENABLE,Force Local Receiver Preset Hint Enable. Enables the FORCE_LOCAL_RX_HINT field. If select rate in the EQ_RATE_SEL field is other than 8.0GT/s Speed this feature is not available. Note: This register field is sticky." "0,1" newline bitfld.long 0x4 28. "FORCE_LOCAL_TX_COEF_ENABLE,Force Local Transmitter Coefficient Enable. Enables the following fields: - FORCE_LOCAL_TX_PRE_CURSOR - FORCE_LOCAL_TX_CURSOR - FORCE_LOCAL_TX_POST_CURSOR Note: This register field is sticky." "0,1" newline hexmask.long.byte 0x4 24.--27. 1. "FORCE_LOCAL_TX_PRESET,Force Local Transmitter Preset. Indicates initial preset value of USP in EQ Slave(EQ Phase2) instead of receiving EQ TS2. If select rate in the EQ_RATE_SEL field is 32.0GT/s Speed this feature is not available. Note: This register.." newline rbitfld.long 0x4 21.--23. "RSVDP_21,Reserved for future use." "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 18.--20. "FORCE_LOCAL_RX_HINT,Force Local Receiver Preset Hint. Indicates the RxPresetHint value of EQ Slave(DSP in EQ Phase2/USP in EQ Phase3) instead of received or set value. If select rate in the EQ_RATE_SEL field is other than 8.0GT/s Speed this feature is.." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x4 12.--17. 1. "FORCE_LOCAL_TX_POST_CURSOR,Force Local Transmitter Post-Cursor. Indicates the coefficient value of EQ Slave(DSP in EQ Phase2/USP in EQ Phase3) instead of the value instructed from link partner. Note: This register field is sticky." newline hexmask.long.byte 0x4 6.--11. 1. "FORCE_LOCAL_TX_CURSOR,Force Local Transmitter Cursor. Indicates the coefficient value of EQ Slave(DSP in EQ Phase2/USP in EQ Phase3) instead of the value instructed from link partner. Note: This register field is sticky." newline hexmask.long.byte 0x4 0.--5. 1. "FORCE_LOCAL_TX_PRE_CURSOR,Force Local Transmitter Pre-cursor. Indicates the coefficient value of EQ Slave(DSP in EQ Phase2/USP in EQ Phase3) instead of the value instructed from link partner. Note: This register field is sticky." line.long 0x8 "SD_EQ_CONTROL3_REG,Silicon Debug EQ Control 3. This viewport register returns the value for the rate and lane selected by the EQ_RATE_SEL and EQ_LANE_SEL fields in the SD_EQ_CONTROL1_REG register. For more details. see the RAS DES section in the Core.." rbitfld.long 0x8 29.--31. "RSVDP_29,Reserved for future use." "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 28. "FORCE_REMOTE_TX_COEF_ENABLE,Force Remote Transmitter Coefficient Enable. Enables the following fields: - FORCE_REMOTE_TX_PRE_CURSOR - FORCE_REMOTE_TX_CURSOR - FORCE_REMOTE_TX_POST_CURSOR This function can only be used when GEN3_EQ_FB_MODE =.." "0,1" newline hexmask.long.word 0x8 18.--27. 1. "RSVDP_18,Reserved for future use." newline hexmask.long.byte 0x8 12.--17. 1. "FORCE_REMOTE_TX_POST_CURSOR,Force Remote Transmitter Post-Cursor. Indicates the coefficient value of EQ Master(DSP in EQ Phase3/USP in EQ Phase2) instead of the value instructed from local phy in dirchange mode. Note: This register field is sticky." newline hexmask.long.byte 0x8 6.--11. 1. "FORCE_REMOTE_TX_CURSOR,Force Remote Transmitter Cursor. Indicates the coefficient value of EQ Master(DSP in EQ Phase3/USP in EQ Phase2) instead of the value instructed from local phy in dirchange mode. Note: This register field is sticky." newline hexmask.long.byte 0x8 0.--5. 1. "FORCE_REMOTE_TX_PRE_CURSOR,Force Remote Transmitter Pre-Cursor. Indicates the coefficient value of EQ Master(DSP in EQ Phase3/USP in EQ Phase2) instead of the value instructed from local phy in dirchange mode. Note: This register field is sticky." rgroup.long (0xE0+0x30C)++0xB line.long 0x0 "SD_EQ_STATUS1_REG,Silicon Debug EQ Status 1. This viewport register returns the first of three words of Silicon Debug EQ Status data for the rate and lane selected by the EQ_RATE_SEL and EQ_LANE_SEL fields in the SD_EQ_CONTROL1_REG register. The.." hexmask.long.tbyte 0x0 8.--31. 1. "RSVDP_8,Reserved for future use." newline bitfld.long 0x0 7. "EQ_REJECT_EVENT,EQ Reject Event. Indicates that the controller receives two consecutive TS1 OS w/Reject=1b during EQ Master phase(DSP in EQ Phase3/USP in EQ Phase2). This bit is automatically cleared when the controller starts EQ Master phase again." "0,1" newline bitfld.long 0x0 6. "EQ_RULEC_VIOLATION,EQ Rule C Violation. Indicates that coefficients rule C violation is detected in the values provided by PHY using direction change method during EQ Master phase(DSP in EQ Phase3/USP in EQ Phase2). The coefficients rule C correspond to.." "0,1" newline bitfld.long 0x0 5. "EQ_RULEB_VIOLATION,EQ Rule B Violation. Indicates that coefficients rule B violation is detected in the values provided by PHY using direction change method during EQ Master phase(DSP in EQ Phase3/USP in EQ Phase2). The coefficients rules B correspond to.." "0,1" newline bitfld.long 0x0 4. "EQ_RULEA_VIOLATION,EQ Rule A Violation. Indicates that coefficients rule A violation is detected in the values provided by PHY using direction change method during EQ Master phase(DSP in EQ Phase3/USP in EQ Phase2). The coefficients rules A correspond to.." "0,1" newline bitfld.long 0x0 3. "RSVDP_3,Reserved for future use." "0,1" newline bitfld.long 0x0 1.--2. "EQ_CONVERGENCE_INFO,EQ Convergence Info. Indicates equalization convergence information. - 0x0: Equalization is not attempted - 0x1: Equalization finished successfully - 0x2: Equalization finished unsuccessfully - 0x3: Reserved This bit is automatically.." "Equalization is not attempted,Equalization finished successfully,Equalization finished unsuccessfully,Reserved" newline bitfld.long 0x0 0. "EQ_SEQUENCE,EQ Sequence. Indicates that the controller is starting the equalization sequence. Note: This register field is sticky." "0,1" line.long 0x4 "SD_EQ_STATUS2_REG,Silicon Debug EQ Status 2. This viewport register returns the second of three words of Silicon Debug EQ Status data for the rate and lane selected by the EQ_RATE_SEL and EQ_LANE_SEL fields in the SD_EQ_CONTROL1_REG register. Each field.." hexmask.long.byte 0x4 24.--31. 1. "EQ_LOCAL_FOM_VALUE,EQ Local Figure of Merit. Indicates Local maximum Figure of Merit value. Note: This register field is sticky." newline bitfld.long 0x4 21.--23. "RSVDP_21,Reserved for future use." "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 18.--20. "EQ_LOCAL_RX_HINT,EQ Local Receiver Preset Hint. Indicates Local Receiver Preset Hint value. If select rate in the EQ_RATE_SEL field is other than 8.0GT/s Speed this feature is not available. Note: This register field is sticky." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x4 12.--17. 1. "EQ_LOCAL_POST_CURSOR,EQ Local Post-Cursor. Indicates Local post cursor coefficient value. Note: This register field is sticky." newline hexmask.long.byte 0x4 6.--11. 1. "EQ_LOCAL_CURSOR,EQ Local Cursor. Indicates Local cursor coefficient value. Note: This register field is sticky." newline hexmask.long.byte 0x4 0.--5. 1. "EQ_LOCAL_PRE_CURSOR,EQ Local Pre-Cursor. Indicates Local pre cursor coefficient value. Note: This register field is sticky." line.long 0x8 "SD_EQ_STATUS3_REG,Silicon Debug EQ Status 3. This viewport register returns the third of three words of Silicon Debug EQ Status data for the rate and lane selected by the EQ_RATE_SEL and EQ_LANE_SEL fields in the SD_EQ_CONTROL1_REG register. Each field.." bitfld.long 0x8 30.--31. "RSVDP_30,Reserved for future use." "0,1,2,3" newline hexmask.long.byte 0x8 24.--29. 1. "EQ_REMOTE_FS,EQ Remote FS. Indicates Remote FS value. Note: This register field is sticky." newline hexmask.long.byte 0x8 18.--23. 1. "EQ_REMOTE_LF,EQ Remote LF. Indicates Remote LF value. Note: This register field is sticky." newline hexmask.long.byte 0x8 12.--17. 1. "EQ_REMOTE_POST_CURSOR,EQ Remote Post-Cursor. Indicates Remote post cursor coefficient value. Note: This register field is sticky." newline hexmask.long.byte 0x8 6.--11. 1. "EQ_REMOTE_CURSOR,EQ Remote Cursor. Indicates Remote cursor coefficient value. Note: This register field is sticky." newline hexmask.long.byte 0x8 0.--5. 1. "EQ_REMOTE_PRE_CURSOR,EQ Remote Pre-Cursor. Indicates Remote pre cursor coefficient value. Note: This register field is sticky." tree.end tree "PF0_SN_CAP (Device Serial Number Capability Structure)" group.long (0x0+0x170)++0xB line.long 0x0 "SN_BASE,Device Serial Number Extended Capability Header. For a description of this standard PCIe register. see the PCI Express Base Specification." hexmask.long.word 0x0 20.--31. 1. "SN_NEXT_OFFSET,Next Capability Offset. For a description of this standard PCIe register field see the PCI Express Base Specification. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then.." hexmask.long.byte 0x0 16.--19. 1. "SN_CAP_VERSION,Capability Version. For a description of this standard PCIe register field see the PCI Express Base Specification. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky).." hexmask.long.word 0x0 0.--15. 1. "SN_PCIE_EXTENDED_CAP_ID,Serial Number Extended Capability ID. For a description of this standard PCIe register field see the PCI Express Base Specification. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if.." line.long 0x4 "SER_NUM_REG_DW_1,Serial Number 1 Register. For a description of this standard PCIe register. see the PCI Express Base Specification." hexmask.long 0x4 0.--31. 1. "SN_SER_NUM_REG_1_DW,IEEE 64 bit Device Serial Number (DW 1). For a description of this standard PCIe register field see the PCI Express Base Specification. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if.." line.long 0x8 "SER_NUM_REG_DW_2,Serial Number 2 Register. For a description of this standard PCIe register. see the PCI Express Base Specification." hexmask.long 0x8 0.--31. 1. "SN_SER_NUM_REG_2_DW,IEEE 64 bit Device Serial Number (DW 2). For a description of this standard PCIe register field see the PCI Express Base Specification. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if.." tree.end tree "PF0_VSECRAS_CAP (PF RAS Datapath Protection Capability Structure (VSEC))" group.long (0x0+0x480)++0x3 line.long 0x0 "RASDP_EXT_CAP_HDR_OFF,PCIe Extended capability ID. Capability version and Next capability offset. For a description of this standard PCIe register. see the PCI Express Specification." hexmask.long.word 0x0 20.--31. 1. "NEXT_OFFSET,Next Capability Offset. For a description of this standard PCIe register see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else.." newline hexmask.long.byte 0x0 16.--19. 1. "CAP,Capability Version. For a description of this standard PCIe register see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note:.." newline hexmask.long.word 0x0 0.--15. 1. "ID,PCI Express Extended Capability ID. For a description of this standard PCIe register see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else.." rgroup.long (0x4+0x480)++0x3 line.long 0x0 "RASDP_VENDOR_SPECIFIC_HDR_OFF,Vendor Specific Header. For a description of this standard PCIe register. see the PCI Express Specification." hexmask.long.word 0x0 20.--31. 1. "VSEC_LENGTH,VSEC Length. For a description of this standard PCIe register see the PCI Express Specification. Note: This register field is sticky." newline hexmask.long.byte 0x0 16.--19. 1. "VSEC_REV,VSEC Rev. For a description of this standard PCIe register see the PCI Express Specification. Note: This register field is sticky." newline hexmask.long.word 0x0 0.--15. 1. "VSEC_ID,VSEC ID. For a description of this standard PCIe register see the PCI Express Specification. Note: This register field is sticky." group.long (0x8+0x480)++0x7 line.long 0x0 "RASDP_ERROR_PROT_CTRL_OFF,ECC error correction control. Allows you to disable ECC error correction for RAMs and datapath. When the AXI Bridge Module is implemented and the master / slave clocks are asynchronous to the PCIe native controller clock.." hexmask.long.byte 0x0 24.--31. 1. "RSVDP_24,Reserved for future use." newline bitfld.long 0x0 23. "ERROR_PROT_DISABLE_CXS_RX,Error correction disable for CXS Tx path (PCIe Rx path). Note: This register field is sticky." "0,1" newline bitfld.long 0x0 22. "ERROR_PROT_DISABLE_ADM_RX,Error correction disable for ADM Rx path. Note: This register field is sticky." "0,1" newline bitfld.long 0x0 21. "ERROR_PROT_DISABLE_LAYER3_RX,Error correction disable for layer 3 Rx path. Note: This register field is sticky." "0,1" newline bitfld.long 0x0 20. "ERROR_PROT_DISABLE_LAYER2_RX,Error correction disable for layer 2 Rx path. Note: This register field is sticky." "0,1" newline bitfld.long 0x0 19. "ERROR_PROT_DISABLE_DMA_READ,Error correction disable for DMA read engine. Note: This register field is sticky." "0,1" newline bitfld.long 0x0 18. "ERROR_PROT_DISABLE_AXI_BRIDGE_INBOUND_REQUEST,Error correction disable for AXI bridge inbound request path. Note: This register field is sticky." "0,1" newline bitfld.long 0x0 17. "ERROR_PROT_DISABLE_AXI_BRIDGE_INBOUND_COMPLETION,Error correction disable for AXI bridge inbound completion composer. Does not disable the error detection reporting for 1-bit and 2-bit ECC errors. Note: This register field is sticky." "?,bit and 2-bit ECC errors" newline bitfld.long 0x0 16. "ERROR_PROT_DISABLE_RX,Global error correction disable for all Rx layers. Note: This register field is sticky." "0,1" newline hexmask.long.byte 0x0 9.--15. 1. "RSVDP_9,Reserved for future use." newline bitfld.long 0x0 8. "ERROR_PROT_DISABLE_DTIM_TX,Error correction disable for DTIM Tx path. Note: This register field is sticky." "0,1" newline bitfld.long 0x0 7. "ERROR_PROT_DISABLE_CXS_TX,Error correction disable for CXS Rx path (PCIe Tx path). Note: This register field is sticky." "0,1" newline bitfld.long 0x0 6. "ERROR_PROT_DISABLE_ADM_TX,Error correction disable for Adm Tx path. Note: This register field is sticky." "0,1" newline bitfld.long 0x0 5. "ERROR_PROT_DISABLE_LAYER3_TX,Error correction disable for layer 3 Tx path. Note: This register field is sticky." "0,1" newline bitfld.long 0x0 4. "ERROR_PROT_DISABLE_LAYER2_TX,Error correction disable for layer 2 Tx path. Note: This register field is sticky." "0,1" newline bitfld.long 0x0 3. "ERROR_PROT_DISABLE_DMA_WRITE,Error correction disable for DMA write engine. Note: This register field is sticky." "0,1" newline bitfld.long 0x0 2. "ERROR_PROT_DISABLE_AXI_BRIDGE_OUTBOUND,Error correction disable for AXI bridge outbound request path. Note: This register field is sticky." "0,1" newline bitfld.long 0x0 1. "ERROR_PROT_DISABLE_AXI_BRIDGE_MASTER,Error correction disable for AXI bridge master completion buffer. Note: This register field is sticky." "0,1" newline bitfld.long 0x0 0. "ERROR_PROT_DISABLE_TX,Global error correction disable for all Tx layers. Does not disable the error detection reporting for 1-bit and 2-bit ECC errors. Note: This register field is sticky." "?,bit and 2-bit ECC errors" line.long 0x4 "RASDP_CORR_COUNTER_CTRL_OFF,Corrected error (1-bit ECC) counter selection and control. This is a viewport control register. Setting the CORR_COUNTER_SELECTION_REGION and CORR_COUNTER_SELECTION fields in this register determine the counter data returned.." hexmask.long.byte 0x4 24.--31. 1. "CORR_COUNTER_SELECTION,Counter selection. This field selects the counter ID (within the region defined by CORR_COUNTER_SELECTION_REGION) whose contents can be read from the RASDP_CORR_COUNT_REPORT_OFF register. You can cycle this field value from 0 to.." newline hexmask.long.byte 0x4 20.--23. 1. "CORR_COUNTER_SELECTION_REGION,Select correctable counter region: - 0x0: Region select for Adm Rx path - 0x1: Region select for layer 3 Rx path - 0x2: Region select for layer 2 Rx path - 0x3: Region select for DMA inbound path - 0x4: Region select for AXI.." newline hexmask.long.word 0x4 5.--19. 1. "RSVDP_5,Reserved for future use." newline bitfld.long 0x4 4. "CORR_EN_COUNTERS,Enable correctable errors counters. - 1: counters increment when the controller detects a correctable error - 0: counters are frozen The counters are enabled by default." "counters are frozen,counters increment when the controller detects a.." newline rbitfld.long 0x4 1.--3. "RSVDP_1,Reserved for future use." "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 0. "CORR_CLEAR_COUNTERS,Clear all correctable error counters." "0,1" rgroup.long (0x10+0x480)++0x3 line.long 0x0 "RASDP_CORR_COUNT_REPORT_OFF,Corrected error (1-bit ECC) counter data. This viewport register returns the counter data selected by the CORR_COUNTER_SELECTION_REGION and CORR_COUNTER_SELECTION fields in the RASDP_CORR_COUNTER_CTRL_OFF register." hexmask.long.byte 0x0 24.--31. 1. "CORR_COUNTER_SELECTED,Counter selection. Returns the value set in the CORR_COUNTER_SELECTION field of the RASDP_CORR_COUNTER_CTRL_OFF register." newline hexmask.long.byte 0x0 20.--23. 1. "CORR_COUNTER_SELECTED_REGION,Selected correctable counter region: - 0x0: Region select for Adm Rx path - 0x1: Region select for layer 3 Rx path - 0x2: Region select for layer 2 Rx path - 0x3: Region select for DMA inbound path - 0x4: Region select for.." newline hexmask.long.word 0x0 8.--19. 1. "RSVDP_8,Reserved for future use." newline hexmask.long.byte 0x0 0.--7. 1. "CORR_COUNTER,Current corrected error count for the selected counter." group.long (0x14+0x480)++0x3 line.long 0x0 "RASDP_UNCORR_COUNTER_CTRL_OFF,Uncorrected error (2-bit ECC and parity) counter selection and control. This is a viewport control register. Setting the UNCORR_COUNTER_SELECTION_REGION and UNCORR_COUNTER_SELECTION fields in this register determine the.." hexmask.long.byte 0x0 24.--31. 1. "UNCORR_COUNTER_SELECTION,Counter selection. This field selects the counter ID (within the region defined by UNCORR_COUNTER_SELECTION_REGION) whose contents can be read from the RASDP_UNCORR_COUNT_REPORT_OFF register. You can cycle this field value from 0.." newline hexmask.long.byte 0x0 20.--23. 1. "UNCORR_COUNTER_SELECTION_REGION,Select uncorrectable counter region: - 0x0: Region select for Adm Rx path - 0x1: Region select for layer 3 Rx path - 0x2: Region select for layer 2 Rx path - 0x3: Region select for DMA inbound path - 0x4: Region select for.." newline hexmask.long.word 0x0 5.--19. 1. "RSVDP_5,Reserved for future use." newline bitfld.long 0x0 4. "UNCORR_EN_COUNTERS,Enable uncorrectable errors counters. - 1: enables the counters to increment on detected correctable errors - 0: counters are frozen The counters are enabled by default." "counters are frozen,enables the counters to increment on detected.." newline rbitfld.long 0x0 1.--3. "RSVDP_1,Reserved for future use." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 0. "UNCORR_CLEAR_COUNTERS,Clear uncorrectable errors counters. When asserted causes all counters tracking the uncorrectable errors to be cleared." "0,1" rgroup.long (0x18+0x480)++0x3 line.long 0x0 "RASDP_UNCORR_COUNT_REPORT_OFF,Uncorrected error (2-bit ECC and parity) counter data. This viewport register returns the counter data selected by the UNCORR_COUNTER_SELECTION_REGION and UNCORR_COUNTER_SELECTION fields in the RASDP_UNCORR_COUNTER_CTRL_OFF.." hexmask.long.byte 0x0 24.--31. 1. "UNCORR_COUNTER_SELECTED,Counter selection. Returns the value set in the UNCORR_COUNTER_SELECTION field of the RASDP_UNCORR_COUNTER_CTRL_OFF register." newline hexmask.long.byte 0x0 20.--23. 1. "UNCORR_COUNTER_SELECTED_REGION,Selected uncorrectable counter region: - 0x0: Region select for Adm Rx path - 0x1: Region select for layer 3 Rx path - 0x2: Region select for layer 2 Rx path - 0x3: Region select for DMA inbound path - 0x4: Region select.." newline hexmask.long.word 0x0 8.--19. 1. "RSVDP_8,Reserved for future use." newline hexmask.long.byte 0x0 0.--7. 1. "UNCORR_COUNTER,Current uncorrected error count for the selected counter" group.long (0x1C+0x480)++0x3 line.long 0x0 "RASDP_ERROR_INJ_CTRL_OFF,Error injection control for the following features: - 1-bit or 2-bit injection - Continuous or fixed-number (n) injection modes - Global enable/disable - Selectable location where injection occurs" hexmask.long.byte 0x0 24.--31. 1. "RSVDP_24,Reserved for future use." newline hexmask.long.byte 0x0 16.--23. 1. "ERROR_INJ_LOC,Error injection location. Selects where error injection takes place. You can cycle this field value from 0 to 255 to access all locations according to the detailed report of check points at.." newline hexmask.long.byte 0x0 8.--15. 1. "ERROR_INJ_COUNT,Error injection count. - 0: errors are inserted in every TLP until you clear ERROR_INJ_EN. - 1: one errors injected - 2: two errors injected - n: amount of errors injected" newline rbitfld.long 0x0 6.--7. "RSVDP_6,Reserved for future use." "0,1,2,3" newline bitfld.long 0x0 4.--5. "ERROR_INJ_TYPE,Error injection type: - 0: none - 1: 1-bit - 2: 2-bit" "none,bit,bit,?" newline rbitfld.long 0x0 1.--3. "RSVDP_1,Reserved for future use." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 0. "ERROR_INJ_EN,Error injection global enable. When set enables the error insertion logic." "0,1" rgroup.long (0x20+0x480)++0x7 line.long 0x0 "RASDP_CORR_ERROR_LOCATION_OFF,Corrected errors locations. For more details. see the RAS Data Protection (DP) section in the Core Operations chapter of the Databook." hexmask.long.byte 0x0 24.--31. 1. "LOC_LAST_CORR_ERROR,Location/ID of the last corrected error within the region defined by REG_LAST_CORR_ERROR. You can cycle this field value from 0 to 255 to access all counters according to the detailed report of check points at.." newline hexmask.long.byte 0x0 20.--23. 1. "REG_LAST_CORR_ERROR,Region of the last corrected error: - 0x0: Region select for Adm Rx path - 0x1: Region select for layer 3 Rx path - 0x2: Region select for layer 2 Rx path - 0x3: Region select for DMA inbound path - 0x4: Region select for AXI bridge.." newline hexmask.long.byte 0x0 16.--19. 1. "RSVDP_16,Reserved for future use." newline hexmask.long.byte 0x0 8.--15. 1. "LOC_FIRST_CORR_ERROR,Location/ID of the first corrected error within the region defined by REG_FIRST_CORR_ERROR. You can cycle this field value from 0 to 255 to access all counters according to the detailed report of check points at.." newline hexmask.long.byte 0x0 4.--7. 1. "REG_FIRST_CORR_ERROR,Region of the first corrected error: - 0x0: Region select for Adm Rx path - 0x1: Region select for layer 3 Rx path - 0x2: Region select for layer 2 Rx path - 0x3: Region select for DMA inbound path - 0x4: Region select for AXI bridge.." newline hexmask.long.byte 0x0 0.--3. 1. "RSVDP_0,Reserved for future use." line.long 0x4 "RASDP_UNCORR_ERROR_LOCATION_OFF,Uncorrected errors locations. For more details. see the RAS Data Protection (DP) section in the Core Operations chapter of the Databook." hexmask.long.byte 0x4 24.--31. 1. "LOC_LAST_UNCORR_ERROR,Location/ID of the last uncorrected error within the region defined by REG_LAST_UNCORR_ERROR. You can cycle this field value from 0 to 255 to access all counters according to the detailed report of check points at.." newline hexmask.long.byte 0x4 20.--23. 1. "REG_LAST_UNCORR_ERROR,Region of the last uncorrected error: - 0x0: Region select for Adm Rx path - 0x1: Region select for layer 3 Rx path - 0x2: Region select for layer 2 Rx path - 0x3: Region select for DMA inbound path - 0x4: Region select for AXI.." newline hexmask.long.byte 0x4 16.--19. 1. "RSVDP_16,Reserved for future use." newline hexmask.long.byte 0x4 8.--15. 1. "LOC_FIRST_UNCORR_ERROR,Location/ID of the first uncorrected error within the region defined by REG_FIRST_UNCORR_ERROR. You can cycle this field value from 0 to 255 to access all counters according to the detailed report of check points at.." newline hexmask.long.byte 0x4 4.--7. 1. "REG_FIRST_UNCORR_ERROR,Region of the first uncorrected error: - 0x0: Region select for Adm Rx path - 0x1: Region select for layer 3 Rx path - 0x2: Region select for layer 2 Rx path - 0x3: Region select for DMA inbound path - 0x4: Region select for AXI.." newline hexmask.long.byte 0x4 0.--3. 1. "RSVDP_0,Reserved for future use." group.long (0x28+0x480)++0x7 line.long 0x0 "RASDP_ERROR_MODE_EN_OFF,RASDP error mode enable. The controller enters RASDP error mode (if ERROR_MODE_EN =1) upon detection of the first uncorrectable error. During this mode: - Rx TLPs that are forwarded to your application are not guaranteed to be.." hexmask.long 0x0 2.--31. 1. "RSVDP_2,Reserved for future use." newline bitfld.long 0x0 1. "AUTO_LINK_DOWN_EN,Write '1' to enable the controller to bring the link down when the controller enters RASDP error mode. Note: This register field is sticky." "0,1" newline bitfld.long 0x0 0. "ERROR_MODE_EN,Write '1' to enable the controller enter RASDP error mode when it detects an uncorrectable error. Note: This register field is sticky." "0,1" line.long 0x4 "RASDP_ERROR_MODE_CLEAR_OFF,Exit RASDP error mode. For more details. see the RAS Data Protection (DP) section in the Core Operations chapter of the Databook." hexmask.long 0x4 1.--31. 1. "RSVDP_1,Reserved for future use." newline bitfld.long 0x4 0. "ERROR_MODE_CLEAR,Write '1' to take the controller out of RASDP error mode. The controller will then report uncorrectable errors (through AER internal error reporting) and also stop nullifying/discarding TLPs." "0,1" rgroup.long (0x30+0x480)++0x7 line.long 0x0 "RASDP_RAM_ADDR_CORR_ERROR_OFF,RAM Address where a corrected error (1-bit ECC) has been detected. For more details. see the RAS Data Protection (DP) section in the Core Operations chapter of the Databook." hexmask.long.byte 0x0 28.--31. 1. "RAM_INDEX_CORR_ERROR,RAM index where a corrected error (1-bit ECC) has been detected." newline bitfld.long 0x0 27. "RSVDP_27,Reserved for future use." "0,1" newline hexmask.long 0x0 0.--26. 1. "RAM_ADDR_CORR_ERROR,RAM Address where a corrected error (1-bit ECC) has been detected." line.long 0x4 "RASDP_RAM_ADDR_UNCORR_ERROR_OFF,RAM Address where an uncorrected error (2-bit ECC) has been detected. For more details. see the RAS Data Protection (DP) section in the Core Operations chapter of the Databook." hexmask.long.byte 0x4 28.--31. 1. "RAM_INDEX_UNCORR_ERROR,RAM index where an uncorrected error (2-bit ECC) has been detected." newline bitfld.long 0x4 27. "RSVDP_27,Reserved for future use." "0,1" newline hexmask.long 0x4 0.--26. 1. "RAM_ADDR_UNCORR_ERROR,RAM Address where an uncorrected error (2-bit ECC) has been detected." tree.end tree "PF0_RTR_CAP (PF RTR Capability Structure)" group.long (0x0+0x2F8)++0xB line.long 0x0 "RTR_EXT_CAP_HDR_OFF,Readiness Time Reporting PCI Express Extended Capability Header. For a description of this standard PCIe register. see the PCI Express Specification." hexmask.long.word 0x0 20.--31. 1. "RTR_NEXT_OFFSET,Next Capability Offset. For a description of this standard PCIe register field see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky).." hexmask.long.byte 0x0 16.--19. 1. "RTR_CAP_VERSION,Capability Version. For a description of this standard PCIe register field see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky).." hexmask.long.word 0x0 0.--15. 1. "RTR_EXT_CAP_ID,PCI Express Extended Capability ID. For a description of this standard PCIe register field see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then.." line.long 0x4 "READI_TIME_REPORTING1_OFF,Readiness Time Reporting 1. For a description of this standard PCIe register. see the PCI Express Specification." bitfld.long 0x4 31. "RTR_TIME_VALID,Valid. For a description of this standard PCIe register field see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky)" "0,1" hexmask.long.byte 0x4 24.--30. 1. "RSVDP_24,Reserved for future use." hexmask.long.word 0x4 12.--23. 1. "DL_UP_TIME,DL_UP Time. For a description of this standard PCIe register field see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky)" hexmask.long.word 0x4 0.--11. 1. "RESET_TIME,Reset Time. For a description of this standard PCIe register field see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky)" line.long 0x8 "READI_TIME_REPORTING2_OFF,Readiness Time Reporting 2. For a description of this standard PCIe register. see the PCI Express Specification." hexmask.long.byte 0x8 24.--31. 1. "RSVDP_24,Reserved for future use." hexmask.long.word 0x8 12.--23. 1. "D3HOT_D0_TIME,D3hot to D0 Time. For a description of this standard PCIe register field see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else.." hexmask.long.word 0x8 0.--11. 1. "FLR_TIME,FLR Time. For a description of this standard PCIe register field see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky)" tree.end tree "PF0_RTR_CAP_DBI2 (DBI2 Shadow Block: PF RTR Capability Structure)" rgroup.long (0x4+0x12F8)++0x7 line.long 0x0 "SHADOW_READI_TIME_REPORTING1_OFF,Shadow Register Readiness Time Reporting 1. For a description of this standard PCIe register. see the PCI Express Specification." bitfld.long 0x0 31. "RTR_TIME_VALID,Shadow Valid in the shadow register. For a description of this standard PCIe register field see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access - Dbi: No access - Dbi2: if.." "0,1" hexmask.long.tbyte 0x0 12.--30. 1. "RSVDP_12,Reserved for future use." hexmask.long.word 0x0 0.--11. 1. "RESET_TIME,Shadow Reset Time in the shadow register. For a description of this standard PCIe register field see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access - Dbi: No access - Dbi2: if.." line.long 0x4 "SHADOW_READI_TIME_REPORTING2_OFF,Shadow Register Readiness Time Reporting 2. For a description of this standard PCIe register. see the PCI Express Specification." hexmask.long.byte 0x4 24.--31. 1. "RSVDP_24,Reserved for future use." hexmask.long.word 0x4 12.--23. 1. "D3HOT_D0_TIME,Shadow D3hot to D0 Time in the shadow register. For a description of this standard PCIe register field see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access - Dbi: No access - Dbi2:.." hexmask.long.word 0x4 0.--11. 1. "FLR_TIME,Shadow FLR Time in the shadow register. For a description of this standard PCIe register field see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access - Dbi: No access - Dbi2: if.." tree.end tree "PF0_FRSQ_CAP (PF FRSQ Capability Structure)" group.long (0x0+0x2E8)++0xB line.long 0x0 "FRSQ_EXT_CAP_HDR_OFF,FRS Queuing Extended Capability Header. For a description of this standard PCIe register. see the PCI Express Specification." hexmask.long.word 0x0 20.--31. 1. "FRSQ_NEXT_OFFSET,Next Capability Offset. For a description of this standard PCIe register field see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then.." hexmask.long.byte 0x0 16.--19. 1. "FRSQ_CAP_VERSION,Capability Version. For a description of this standard PCIe register field see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky).." hexmask.long.word 0x0 0.--15. 1. "FRSQ_EXT_CAP_ID,PCI Express Extended Capability ID. For a description of this standard PCIe register field see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then.." line.long 0x4 "FRSQ_CAP_OFF,FRS Queuing Capability Register. For a description of this standard PCIe register. see the PCI Express Specification." hexmask.long.word 0x4 21.--31. 1. "RSVDP_21,Reserved for future use." hexmask.long.byte 0x4 16.--20. 1. "FRS_INT_MESSAGE_NUMBER,FRS Interrupt Message Number. For a description of this standard PCIe register field see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1).." hexmask.long.byte 0x4 12.--15. 1. "RSVDP_12,Reserved for future use." hexmask.long.word 0x4 0.--11. 1. "FRSQ_MAX_DEPTH,FRS Queue Max Depth. For a description of this standard PCIe register field see the PCI Express Specification." line.long 0x8 "FRSQ_CONTROL_FRSQ_STATUS_OFF,FRS Queuing Status and Control Register. For a description of this standard PCIe register. see the PCI Express Specification." hexmask.long.word 0x8 17.--31. 1. "RSVDP_17,Reserved for future use." bitfld.long 0x8 16. "FRS_INTERRUPT_ENABLE,FRS Interrupt Enable. For a description of this standard PCIe register field see the PCI Express Specification." "0,1" hexmask.long.word 0x8 2.--15. 1. "RSVDP_2,Reserved for future use." bitfld.long 0x8 1. "FRS_MESSAGE_OVERFLOW,FRS Message Overflow. For a description of this standard PCIe register field see the PCI Express Specification." "0,1" newline bitfld.long 0x8 0. "FRS_MESSAGE_RECEIVED,FRS Message Received. For a description of this standard PCIe register field see the PCI Express Specification." "0,1" rgroup.long (0xC+0x2E8)++0x3 line.long 0x0 "FRS_MESSAGE_QUEUE_OFF,FRS Message Queue Register. For a description of this standard PCIe register. see the PCI Express Specification." hexmask.long.word 0x0 20.--31. 1. "FRS_MESSAGE_QUE_DEPTH,FRS Message Queue Depth. For a description of this standard PCIe register field see the PCI Express Specification." hexmask.long.byte 0x0 16.--19. 1. "FRS_MESSAGE_QUE_REASON,FRS Message Queue Reason. For a description of this standard PCIe register field see the PCI Express Specification." hexmask.long.word 0x0 0.--15. 1. "FRS_MESSAGE_QUE_FUNC_ID,FRS Message Queue Function ID. For a description of this standard PCIe register field see the PCI Express Specification." tree.end tree "PF0_PTM_CAP (PF PTM Capability Structure)" group.long (0x0+0x40C)++0xB line.long 0x0 "PTM_EXT_CAP_HDR_OFF,Precision Time Measurement Capability Header. For a description of this standard PCIe register. see the PCI Express Specification." hexmask.long.word 0x0 20.--31. 1. "PTM_NEXT_OFFSET,Precision Time Measurement PCI Express Extended Capability Next Offset. For a description of this standard PCIe register see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access. -.." hexmask.long.byte 0x0 16.--19. 1. "PTM_CAP_VERSION,Precision Time Measurement PCI Express Extended Capability Version. For a description of this standard PCIe register see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi:.." hexmask.long.word 0x0 0.--15. 1. "PTM_CAP_ID,Precision Time Measurement PCI Express Extended Capability ID. For a description of this standard PCIe register see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if.." line.long 0x4 "PTM_CAP_OFF,PTM Capability Register. For a description of this standard PCIe register. see the PCI Express Specification." hexmask.long.word 0x4 16.--31. 1. "RSVDP_16,Reserved for future use." hexmask.long.byte 0x4 8.--15. 1. "PTM_CLK_GRAN,PTM Local Clock Granularity. For a description of this standard PCIe register see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky).." hexmask.long.byte 0x4 3.--7. 1. "RSVDP_3,Reserved for future use." bitfld.long 0x4 2. "PTM_ROOT_CAPABLE,PTM Root Capable. For a description of this standard PCIe register see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else.." "0,1" bitfld.long 0x4 1. "PTM_RES_CAPABLE,PTM Responder Capable. For a description of this standard PCIe register see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else.." "0,1" newline bitfld.long 0x4 0. "PTM_REQ_CAPABLE,PTM Requester Capable. For a description of this standard PCIe register see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else.." "0,1" line.long 0x8 "PTM_CONTROL_OFF,PTM Control Register. For a description of this standard PCIe register. see the PCI Express Specification." hexmask.long.word 0x8 16.--31. 1. "RSVDP_16,Reserved for future use." hexmask.long.byte 0x8 8.--15. 1. "EFF_GRAN,PTM Effective Granularity. For a description of this standard PCIe register see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: HWINIT" hexmask.long.byte 0x8 2.--7. 1. "RSVDP_2,Reserved for future use." rbitfld.long 0x8 1. "ROOT_SELECT,PTM Root Select. When set this Time Source is the PTM Root. For a description of this standard PCIe register see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: HWINIT" "0,1" bitfld.long 0x8 0. "PTM_ENABLE,PTM Enable. When set this function is permitted to participate in the PTM mechanism. For a description of this standard PCIe register see the PCI Express Specification." "0,1" tree.end tree "PF0_PTM_RES_CAP (PF PTM Responder Capability Structure (VSEC))" group.long (0x0+0x418)++0xB line.long 0x0 "PTM_RES_CAP_HDR_OFF,Precision Time Measurement Responder Capability Header (VSEC). For more details. see the PTM section in the Databook." hexmask.long.word 0x0 20.--31. 1. "PTM_RES_EXT_CAP_NEXT_OFFS,Precision Time Measurement Responder VSEC Next Pointer. For more details see the PTM section in the Databook. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then.." hexmask.long.byte 0x0 16.--19. 1. "PTM_RES_EXT_CAP_VER,Precision Time Measurement Responder VSEC Version. For more details see the PTM section in the Databook. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else.." hexmask.long.word 0x0 0.--15. 1. "PTM_RES_EXT_CAP_ID,Precision Time Measurement Responder VSEC ID. For more details see the PTM section in the Databook. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else.." line.long 0x4 "PTM_RES_HDR_OFF,Precision Time Measurement Responder Vendor Specific Header. For more details. see the PTM section in the Databook." hexmask.long.word 0x4 20.--31. 1. "PTM_RES_VSEC_LENGTH,PTM Responder VSEC Length. For more details see the PTM section in the Databook. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This.." hexmask.long.byte 0x4 16.--19. 1. "PTM_RES_VSEC_REV,PTM Responder VSEC Revision. For more details see the PTM section in the Databook. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This.." hexmask.long.word 0x4 0.--15. 1. "PTM_RES_VSEC_ID,PTM Responder VSEC ID. For more details see the PTM section in the Databook. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register.." line.long 0x8 "PTM_RES_CONTROL_OFF,PTM Responder Control Register. For more details. see the PTM section in the Databook." hexmask.long 0x8 2.--31. 1. "RSVDP_2,Reserved for future use." bitfld.long 0x8 1. "PTM_RES_PDEL_BYTE_REV,PTM Requester Propagation Delay Byte Reversal - Reverse the order of bytes in the PTM Propagation Delay data word of the PTM ResponseD Message for compatibility with previous revisions. For more details see the PTM section in the.." "0,1" bitfld.long 0x8 0. "PTM_RES_CCONTEXT_VALID,PTM Responder Control Context Valid - PTM Local Timing is valid. This bit is set over the DBI. A speed change or aux_clk_active will set this bit low. For more details see the PTM section in the Databook. Note: The access.." "0,1" rgroup.long (0xC+0x418)++0x3 line.long 0x0 "PTM_RES_STATUS_OFF,PTM Responder Status Register. For more details. see the PTM section in the Databook." hexmask.long 0x0 2.--31. 1. "RSVDP_2,Reserved for future use." bitfld.long 0x0 1. "PTM_RES_REQUEST_RECEIVED,PTM 1st Request Received - PTM Responder has received the first PTM Request Message. Upon receipt of a second PTM Request Message a ResponseD message with timing information will be sent from the Responder if the context is.." "0,1" bitfld.long 0x0 0. "PTM_RES_CONTEXT_VALID,PTM Responder Status Context Valid - PTM Local Timing Context is Valid. Value set from upstream port Requester in a Switch. Shadows the same in the control register in all other products. For more details see the PTM section in the.." "0,1" group.long (0x10+0x418)++0x7 line.long 0x0 "PTM_RES_LOCAL_LSB_OFF,PTM Responder Local Clock LSB. For more details. see the PTM section in the Databook." hexmask.long 0x0 0.--31. 1. "PTM_RES_LOCAL_LSB,PTM Responder Local Clock LSB - Lower 32 bits of local timer value. For more details see the PTM section in the Databook. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then.." line.long 0x4 "PTM_RES_LOCAL_MSB_OFF,PTM Responder Local Clock MSB. For more details. see the PTM section in the Databook." hexmask.long 0x4 0.--31. 1. "PTM_RES_LOCAL_MSB,PTM Responder Local Clock MSB - Upper 32 bits of local timer value. For more details see the PTM section in the Databook. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then.." rgroup.long (0x18+0x418)++0x1F line.long 0x0 "PTM_RES_T2_LSB_OFF,PTM Responder T2 Timestamp LSB. For more details. see the PTM section in the Databook." hexmask.long 0x0 0.--31. 1. "PTM_RES_T2_LSB,PTM Responder T2 Timestamp LSB - Lower 32 bits of the T2 Timestamp value. For more details see the PTM section in the Databook. Note: This register field is sticky." line.long 0x4 "PTM_RES_T2_MSB_OFF,PTM Responder T2 Timestamp MSB. For more details. see the PTM section in the Databook." hexmask.long 0x4 0.--31. 1. "PTM_RES_T2_MSB,PTM Responder T2 Timestamp MSB - Upper 32 bits of the T2 Timestamp value. For more details see the PTM section in the Databook. Note: This register field is sticky." line.long 0x8 "PTM_RES_T2P_LSB_OFF,PTM Responder T2 Previous Timestamp LSB. For more details. see the PTM section in the Databook." hexmask.long 0x8 0.--31. 1. "PTM_RES_T2P_LSB,PTM Responder T2 Previous Timestamp LSB - Lower 32 bits of the previously stored T2 Timestamp value. For more details see the PTM section in the Databook. Note: This register field is sticky." line.long 0xC "PTM_RES_T2P_MSB_OFF,PTM Responder T2 Previous Timestamp MSB. For more details. see the PTM section in the Databook." hexmask.long 0xC 0.--31. 1. "PTM_RES_T2P_MSB,PTM Responder T2 Previous Timestamp MSB - Upper 32 bits of the previously stored T2 Timestamp value. For more details see the PTM section in the Databook. Note: This register field is sticky." line.long 0x10 "PTM_RES_T3_LSB_OFF,PTM Responder T3 Timestamp LSB. For more details. see the PTM section in the Databook." hexmask.long 0x10 0.--31. 1. "PTM_RES_T3_LSB,PTM Responder T3 Timestamp LSB - Lower 32 bits of the T3 Timestamp value. For more details see the PTM section in the Databook. Note: This register field is sticky." line.long 0x14 "PTM_RES_T3_MSB_OFF,PTM Responder T3 Timestamp MSB. For more details. see the PTM section in the Databook." hexmask.long 0x14 0.--31. 1. "PTM_RES_T3_MSB,PTM Responder T3 Timestamp MSB - Upper 32 bits of the T2 Timestamp value. For more details see the PTM section in the Databook. Note: This register field is sticky." line.long 0x18 "PTM_RES_T3P_LSB_OFF,PTM Responder T3 Previous Timestamp LSB. For more details. see the PTM section in the Databook." hexmask.long 0x18 0.--31. 1. "PTM_RES_T3P_LSB,PTM Responder T3 Previous Timestamp LSB - Lower 32 bits of the previously stored T3 Timestamp value. For more details see the PTM section in the Databook. Note: This register field is sticky." line.long 0x1C "PTM_RES_T3P_MSB_OFF,PTM Responder T3 Previous Timestamp MSB. For more details. see the PTM section in the Databook." hexmask.long 0x1C 0.--31. 1. "PTM_RES_T3P_MSB,PTM Responder T3 Previous Timestamp MSB - Upper 32 bits of the previously stored T3 Timestamp value. For more details see the PTM section in the Databook. Note: This register field is sticky." group.long (0x38+0x418)++0x7 line.long 0x0 "PTM_RES_TX_LATENCY_OFF,PTM Responder TX Latency. For more details. see the PTM section in the Databook." hexmask.long.tbyte 0x0 12.--31. 1. "RSVDP_12,Reserved for future use." hexmask.long.word 0x0 0.--11. 1. "PTM_RES_TX_LATENCY,PTM Responder TX Latency - Responder Transmit path latency (12 bit wide). For more details see the PTM section in the Databook. Note: This register field is sticky." line.long 0x4 "PTM_RES_RX_LATENCY_OFF,PTM Responder RX Latency. For more details. see the PTM section in the Databook." hexmask.long.tbyte 0x4 12.--31. 1. "RSVDP_12,Reserved for future use." hexmask.long.word 0x4 0.--11. 1. "PTM_RES_RX_LATENCY,PTM Responder RX Latency - Responder Receive path latency (12 bit wide). For more details see the PTM section in the Databook. Note: This register field is sticky." rgroup.long (0x40+0x418)++0x3 line.long 0x0 "PTM_RES_NOM_CLOCK_T_OFF,PTM Responder Nominal Clock Period. For more details. see the PTM section in the Databook." hexmask.long.byte 0x0 24.--31. 1. "RSVDP_24,Reserved for future use." hexmask.long.byte 0x0 16.--23. 1. "PTM_RES_NOM_CLOCK_T_INT,PTM Responder Nominal Clock Period Integral - Integral part of the nominal PTM local clock period in nanoseconds. For more details see the PTM section in the Databook. Note: This register field is sticky." hexmask.long.word 0x0 0.--15. 1. "PTM_RES_NOM_CLOCK_T_FRAC,PTM Responder Nominal Clock Period Fractional - Fractional part of the nominal PTM local clock period. LSB is 1/(2^16) nanoseconds. For more details see the PTM section in the Databook. Note: This register field is sticky." group.long (0x44+0x418)++0x3 line.long 0x0 "PTM_RES_SCALED_CLOCK_T_OFF,PTM Responder Scaled Clock Period. For more details. see the PTM section in the Databook." bitfld.long 0x0 31. "PTM_RES_SCALED_CLOCK_T_EN,PTM Responder Scaled Clock Period Enable - Use the programmed scaled PTM clock period rather than the nominal values. This bit is cleared when the core_clk rate starts to change and can only be set when the clock period change.." "0,1" hexmask.long.byte 0x0 24.--30. 1. "RSVDP_24,Reserved for future use." hexmask.long.byte 0x0 16.--23. 1. "PTM_RES_SCALED_CLOCK_T_INT,PTM Responder Scaled Clock Period Integral - Integral part of the nominal PTM local clock period in nanoseconds. For more details see the PTM section in the Databook. Note: This register field is sticky." newline hexmask.long.word 0x0 0.--15. 1. "PTM_RES_SCALED_CLOCK_T_FRAC,PTM Responder Scaled Clock Period Fractional - Fractional part of the nominal PTM local clock period. LSB is 1/(2^16) nanoseconds. For more details see the PTM section in the Databook. Note: This register field is sticky." tree.end tree "PF0_PM_CAP (PF PCI Power Management Capability Structure)" group.long (0x0+0x40)++0x7 line.long 0x0 "CAP_ID_NXT_PTR_REG,Power Management Capabilities Register." hexmask.long.byte 0x0 27.--31. 1. "PME_SUPPORT,PME_Support. This 5-bit field indicates the power states in which the function may generate a PME and/or forward PME messages. A value of 0b for any bit indicates that the function is not capable of asserting PME while in that power state. -.." bitfld.long 0x0 26. "D2_SUPPORT,D2_Support. If this bit is set this function supports the D2 Power Management state. Functions that do not support D2 must always return a value of 0b for this bit. Note: The access attributes of this field are as follows: - Wire: No access." "0,1" bitfld.long 0x0 25. "D1_SUPPORT,D1_Support. If this bit is set this function supports the D1 Power Management state. Functions that do not support D1 must always return a value of 0b for this bit. Note: The access attributes of this field are as follows: - Wire: No access." "0,1" bitfld.long 0x0 22.--24. "AUX_CURR,Aux_Current. This 3 bit field reports the Vaux auxiliary current requirements for the function. If this function implements the Data Register the controller hardwires this field to 000b. If PME_Support is 0 xxxxb (PME assertion from D3cold is.." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 21. "DSI,Device Specific Initialization. The DSI bit indicates whether special initialization of this function is required. When set indicates that the function requires a device specific initialization sequence following a transition to the D0uninitialized.." "0,1" bitfld.long 0x0 20. "PME_IMM_READI_RETURN_DO,Immediate_Readiness_on_Return_to_D0. - If this bit is a '1' this function is guaranteed to be ready to successfully complete valid accesses immediately after being set to D0. These accesses include configuration cycles and if.." "0,1" rbitfld.long 0x0 19. "PME_CLK,PME Clock. Does not apply to PCI Express the controller hardwires it to 0b. Note: This register field is sticky." "0,1" bitfld.long 0x0 16.--18. "PM_SPEC_VER,Version. This field provides the Power Management specification version. The controller hardwires this field to 011b for functions compliant to PCI Express Base Specification Revision 4.0 Version 1.0>. Note: The access attributes of this.." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x0 8.--15. 1. "PM_NEXT_POINTER,Next Capability Pointer. This field provides an offset into the function's configuration space pointing to the location of next item in the capabilities list. If there are no additional items in the capabilities list this field is set to.." hexmask.long.byte 0x0 0.--7. 1. "PM_CAP_ID,Capability ID. This field returns 01h to indicate that this is the PCI Power Management Capability. Each function may have only one item in its capability list with Capability ID set to 01h." line.long 0x4 "CON_STATUS_REG,Power Management Control and Status Register. This register is used to manage the PCI function's power management state as well as to enable/monitor PMEs." hexmask.long.byte 0x4 24.--31. 1. "DATA_REG_ADD_INFO,Data. This field is used to report the state dependent data requested by the Data_Select field. The value of this field is scaled by the value reported by the Data_Scale field." rbitfld.long 0x4 23. "BUS_PWR_CLK_CON_EN,Bus Power/Clock Control Enable. For a description of this standard PCIe register field see the PCI Express Base Specification." "0,1" rbitfld.long 0x4 22. "B2_B3_SUPPORT,B2B3 Support for D3hot. For a description of this standard PCIe register field see the PCI Express Base Specification." "0,1" hexmask.long.byte 0x4 16.--21. 1. "RSVDP_16,Reserved for future use." newline bitfld.long 0x4 15. "PME_STATUS,PME_Status. This bit is set when the function normally generates a PME signal. The value of this bit is not affected by the value of the PME_En bit. If PME_Support bit 31 of the Power Management Capabilities register is clear this bit is.." "0,1" rbitfld.long 0x4 13.--14. "DATA_SCALE,Data_Scale. This field indicates the scaling factor to be used when interpreting the value of the Data field. The value and meaning of this field varies depending on which data value has been selected by the Data_Select field. For more details.." "0,1,2,3" hexmask.long.byte 0x4 9.--12. 1. "DATA_SELECT,Data_Select. This 4-bit field is used to select which data is to be reported through the Data and Data_Scale field. If the Data field is not implemented this field must be hardwired to 0000b." bitfld.long 0x4 8. "PME_ENABLE,PME_En. - When set the function is permitted to generate a PME. - When clear the function is not permitted to generate a PME. If PME_Support is 1 xxxxb (PME generation from D3cold) or the function consumes Aux power and Aux power is.." "0,1" newline hexmask.long.byte 0x4 4.--7. 1. "RSVDP_4,Reserved for future use." bitfld.long 0x4 3. "NO_SOFT_RST,No_Soft_Reset. This bit indicates the state of the function after writing the PowerState field to transition the function from D3hot to D0. - When set this transition preserves internal function state. The function is in D0Active and no.." "0,1" rbitfld.long 0x4 2. "RSVDP_2,Reserved for future use." "0,1" bitfld.long 0x4 0.--1. "POWER_STATE,PowerState. This 2-bit field is used both to determine the current power state of a function and to set the function into a new power state. The definition of the field values is given below. You can write to this register; however the.." "D0,D1,D2,D3hot" tree.end tree "PF0_PCIE_CAP (PF PCI Express Capability Structure)" group.long (0x0+0x70)++0x33 line.long 0x0 "PCIE_CAP_ID_PCIE_NEXT_CAP_PTR_PCIE_CAP_REG,PCI Express Capabilities. ID. Next Pointer Register." rbitfld.long 0x0 31. "RSVDP_31,Reserved for future use." "0,1" rbitfld.long 0x0 30. "RSVD,Reserved." "0,1" newline hexmask.long.byte 0x0 25.--29. 1. "PCIE_INT_MSG_NUM,PCIE Interrupt Message Number. For a description of this standard PCIe register field see the PCI Express Base Specification. Interrupt Message Number. This field indicates which MSI/MSI-X vector is used for the interrupt message.." bitfld.long 0x0 24. "PCIE_SLOT_IMP,Slot Implemented. When set this bit indicates that the Link associated with this Port is connected to a slot (as compared to being connected to a system-integrated device or being disabled). This bit is valid for Downstream Ports. This bit.." "0,1" newline hexmask.long.byte 0x0 20.--23. 1. "PCIE_DEV_PORT_TYPE,Device/Port Type. Indicates the specific type of this PCI Express function. Note: Different functions in a Multi-Function Device can generally be of different types. Defined encodings for functions that implement a Type 00h PCI.." hexmask.long.byte 0x0 16.--19. 1. "PCIE_CAP_REG,Capability Version. Indicates PCI-SIG defined PCI Express Capability structure version number. A version of the specification that changes the PCI Express Capability structure in a way that is not otherwise identifiable (for example through.." newline hexmask.long.byte 0x0 8.--15. 1. "PCIE_CAP_NEXT_PTR,Next Capability Pointer. This field contains the offset to the next PCI Capability structure or 00h if no other items exist in the linked list of Capabilities. Note: The access attributes of this field are as follows: - Wire: No access." hexmask.long.byte 0x0 0.--7. 1. "PCIE_CAP_ID,Capability ID. Indicates the PCI Express Capability structure. This field must return a Capability ID of 10h indicating that this is a PCI Express Capability structure." line.long 0x4 "DEVICE_CAPABILITIES_REG,Device Capabilities Register. The Device Capabilities register identifies PCI Express device function specific capabilities." hexmask.long.word 0x4 16.--31. 1. "RSVDP_16,Reserved for future use." bitfld.long 0x4 15. "PCIE_CAP_ROLE_BASED_ERR_REPORT,Role-Based Error Reporting. When set this bit indicates that the function implements the functionality originally defined in the Error Reporting ECN for PCI Express Base Specification Revision 1.0a and later incorporated.." "0,1" newline hexmask.long.word 0x4 6.--14. 1. "RSVDP_6,Reserved for future use." bitfld.long 0x4 5. "PCIE_CAP_EXT_TAG_SUPP,Extended Tag Field Supported. This bit in combination with the 10-Bit Tag Requester Supported bit in the Device Capabilities 2 register indicates the maximum supported size of the Tag field as a Requester. This bit must be set if.." "0,1" newline bitfld.long 0x4 3.--4. "PCIE_CAP_PHANTOM_FUNC_SUPPORT,Phantom Functions Supported. This field indicates the support for use of unclaimed function numbers to extend the number of outstanding transactions allowed by logically combining unclaimed function numbers (called Phantom.." "0,1,2,3" bitfld.long 0x4 0.--2. "PCIE_CAP_MAX_PAYLOAD_SIZE,Max_Payload_Size Supported. This field indicates the maximum payload size that the function can support for TLPs. Defined encodings are: - 000b: 128 bytes max payload size - 001b: 256 bytes max payload size - 010b: 512 bytes max.." "0,1,2,3,4,5,6,7" line.long 0x8 "DEVICE_CONTROL_DEVICE_STATUS,Device Control and Device Status Register. This register controls PCI Express device specific parameters and provides information about PCI Express device (function) specific parameters." hexmask.long.word 0x8 22.--31. 1. "RSVDP_22,Reserved for future use." rbitfld.long 0x8 21. "PCIE_CAP_TRANS_PENDING,Transactions Pending. Endpoints: When set this bit indicates that the function has issued Non-Posted Requests that have not been completed. A Function reports this bit cleared only when all outstanding Non-Posted Requests have.." "0,1" newline rbitfld.long 0x8 20. "PCIE_CAP_AUX_POWER_DETECTED,AUX Power Detected. Functions that require Aux power report this bit as set if Aux power is detected by the function. This bit is derived by sampling the sys_aux_pwr_det input." "0,1" bitfld.long 0x8 19. "PCIE_CAP_UNSUPPORTED_REQ_DETECTED,Unsupported Request Detected. This bit indicates that the function received an Unsupported Request. Errors are logged in this register regardless of whether error reporting is enabled or not in the Device Control.." "0,1" newline bitfld.long 0x8 18. "PCIE_CAP_FATAL_ERR_DETECTED,Fatal Error Detected. This bit indicates status of Fatal errors detected. Errors are logged in this register regardless of whether error reporting is enabled or not in the Device Control register. For a Multi-Function device.." "0,1" bitfld.long 0x8 17. "PCIE_CAP_NON_FATAL_ERR_DETECTED,Non-Fatal Error Detected. This bit indicates status of Non-fatal errors detected. Errors are logged in this register regardless of whether error reporting is enabled or not in the Device Control register. For a.." "0,1" newline bitfld.long 0x8 16. "PCIE_CAP_CORR_ERR_DETECTED,Correctable Error Detected. This bit indicates status of correctable errors detected. Errors are logged in this register regardless of whether error reporting is enabled or not in the Device Control register. For a.." "0,1" bitfld.long 0x8 15. "PCIE_CAP_INITIATE_FLR,Initiate Function Level Reset (applicable to Endpoints with Function Level Reset Capability set to 1b). A write of 1b initiates Function Level Reset to the Function. The value read by software from this bit is always 0b." "0,1" newline bitfld.long 0x8 12.--14. "PCIE_CAP_MAX_READ_REQ_SIZE,Max_Read_Request_Size. This field sets the maximum Read Request size for the function as a Requester. The function must not generate Read Requests with a size exceeding the set value. Defined encodings for this field are: -.." "0,1,2,3,4,5,6,7" rbitfld.long 0x8 11. "PCIE_CAP_EN_NO_SNOOP,Enable No Snoop. If this bit is set the function is permitted to Set the No Snoop bit in the Requester Attributes of transactions it initiates that do not require hardware enforced cache coherency (see section 2.2.6.5 in PCI Express.." "0,1" newline bitfld.long 0x8 10. "PCIE_CAP_AUX_POWER_PM_EN,Aux Power PM Enable. This bit is derived by sampling the sys_aux_pwr_det input. When set this bit enables a function to draw Aux power independent of PME Aux power. Functions that require Aux power on legacy operating systems.." "0,1" rbitfld.long 0x8 9. "PCIE_CAP_PHANTOM_FUNC_EN,Phantom Functions Enable. This bit in combination with the 10-Bit Tag Requester Enable bit in the Device Control 2 register determines how many Tag field bits a Requester is permitted to use. When the 10-Bit Tag Requester.." "0,1" newline rbitfld.long 0x8 8. "PCIE_CAP_EXT_TAG_EN,Extended Tag Field Enable. This bit in combination with the 10-Bit Tag Requester Enable bit in the Device Control 2 register determines how many Tag field bits a Requester is permitted to use. When the 10-Bit Tag Requester Enable.." "0,1" bitfld.long 0x8 5.--7. "PCIE_CAP_MAX_PAYLOAD_SIZE_CS,Max_Payload_Size. This field sets maximum TLP payload size for the Function. As a Receiver the Function must handle TLPs as large as the set value. As a Transmitter the Function must not generate TLPs exceeding the set.." "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 4. "PCIE_CAP_EN_REL_ORDER,Enable Relaxed Ordering. If this bit is set the function is permitted to set the Relaxed Ordering bit in the Attributes field of transactions it initiates that do not require strong write ordering (for more details see section.." "0,1" bitfld.long 0x8 3. "PCIE_CAP_UNSUPPORT_REQ_REP_EN,Unsupported Request Reporting Enable. This bit in conjunction with other bits controls the signaling of Unsupported Request Errors by sending error Messages (for more details see section 6.2.5 and section 6.2.6 of PCI.." "0,1" newline bitfld.long 0x8 2. "PCIE_CAP_FATAL_ERR_REPORT_EN,Fatal Error Reporting Enable. This bit in conjunction with other bits controls sending ERR_FATAL Messages (for more details see section 6.2.5 and section 6.2.6 of of PCI Express Base Specification). For a Multi-Function.." "0,1" bitfld.long 0x8 1. "PCIE_CAP_NON_FATAL_ERR_REPORT_EN,Non-Fatal Error Reporting Enable. This bit in conjunction with other bits controls sending ERR_NONFATAL Messages (for more details see section 6.2.5 and Section 6.2.6 of PCI Express Base Specification). For a.." "0,1" newline bitfld.long 0x8 0. "PCIE_CAP_CORR_ERR_REPORT_EN,Correctable Error Reporting Enable. This bit in conjunction with other bits controls sending ERR_COR Messages (for more details see section 6.2.5 section 6.2.6 and section 6.2.10.2 of PCI Express Base Specification). For.." "0,1" line.long 0xC "LINK_CAPABILITIES_REG,Link Capabilities Register. The Link Capabilities register identifies PCI Express Link specific capabilities." hexmask.long.byte 0xC 24.--31. 1. "PCIE_CAP_PORT_NUM,Port Number. This field indicates the PCI Express Port number for the given PCI Express Link. Multi-Function Devices associated with an Upstream Port must report the same value in this field for all functions. Note: The access.." rbitfld.long 0xC 23. "RSVDP_23,Reserved for future use." "0,1" newline bitfld.long 0xC 22. "PCIE_CAP_ASPM_OPT_COMPLIANCE,ASPM Optionality Compliance. This bit must be set to 1b in all functions. Components implemented against certain earlier versions of this specification will have this bit set to 0b. Software is permitted to use the value of.." "0,1" bitfld.long 0xC 21. "PCIE_CAP_LINK_BW_NOT_CAP,Link Bandwidth Notification Capability. A value of 1b indicates support for the Link Bandwidth Notification status and interrupt mechanisms. This capability is required for all Root Ports and Switch Downstream Ports supporting.." "0,1" newline rbitfld.long 0xC 20. "PCIE_CAP_DLL_ACTIVE_REP_CAP,Data Link Layer Link Active Reporting Capable. For a Downstream Port the controller hardwires this bit to 1b if the component supports the optional capability of reporting the DL_Active state of the Data Link Control and.." "0,1" bitfld.long 0xC 19. "PCIE_CAP_SURPRISE_DOWN_ERR_REP_CAP,Surprise Down Error Reporting Capable. For a Downstream Port this bit must be set if the component supports the optional capability of detecting and reporting a Surprise Down error condition. For Upstream Ports and.." "0,1" newline rbitfld.long 0xC 18. "PCIE_CAP_CLOCK_POWER_MAN,Clock Power Management. For Upstream Ports a value of 1b in this bit indicates that the component tolerates the removal of any reference clock(s) via the 'clock request' (CLKREQ#) mechanism when the Link is in the L1 and L2/L3.." "0,1" bitfld.long 0xC 15.--17. "PCIE_CAP_L1_EXIT_LATENCY,L1 Exit Latency. This field indicates the L1 exit latency for the given PCI Express Link. The value reported indicates the length of time this Port requires to complete transition from ASPM L1 to L0. If ASPM L1 is not supported.." "0,1,2,3,4,5,6,7" newline bitfld.long 0xC 12.--14. "PCIE_CAP_L0S_EXIT_LATENCY,L0s Exit Latency. This field indicates the L0s exit latency for the given PCI Express Link. The value reported indicates the length of time this Port requires to complete transition from L0s to L0. If L0s is not supported the.." "0,1,2,3,4,5,6,7" bitfld.long 0xC 10.--11. "PCIE_CAP_ACTIVE_STATE_LINK_PM_SUPPORT,Active State Power Management (ASPM) Support. This field indicates the level of ASPM supported on the given PCI Express Link. For more details on ASPM support requirements see section 5.4.1 of PCI Express Base.." "0,1,2,3" newline hexmask.long.byte 0xC 4.--9. 1. "PCIE_CAP_MAX_LINK_WIDTH,Maximum Link Width. This field indicates the maximum Link width (xN - corresponding to N Lanes) implemented by the component. This value is permitted to exceed the number of Lanes routed to the slot (Downstream Port) adapter.." hexmask.long.byte 0xC 0.--3. 1. "PCIE_CAP_MAX_LINK_SPEED,Max Link Speed. This field indicates the maximum Link speed of the associated Port. The encoded value specifies a bit location in the Supported Link Speeds Vector (in the Link Capabilities 2 register) that corresponds to the.." line.long 0x10 "LINK_CONTROL_LINK_STATUS_REG,Link Control and Link Status Register. This register controls and provides information about PCI Express Link specific parameters." bitfld.long 0x10 31. "PCIE_CAP_LINK_AUTO_BW_STATUS,Link Autonomous Bandwidth Status. This bit is set by hardware to indicate that hardware has autonomously changed Link speed or width without the Port transitioning through DL_Down status for reasons other than to attempt to.." "0,1" bitfld.long 0x10 30. "PCIE_CAP_LINK_BW_MAN_STATUS,Link Bandwidth Management Status. This bit is set by hardware to indicate that either of the following has occurred without the Port transitioning through DL_Down status: - A Link retraining has completed following a write of.." "0,1" newline rbitfld.long 0x10 29. "PCIE_CAP_DLL_ACTIVE,Data Link Layer Link Active. This bit indicates the status of the Data Link Control and Management State Machine. It returns a 1b to indicate the DL_Active state 0b otherwise. This bit must be implemented if the Data Link Layer Link.." "0,1" bitfld.long 0x10 28. "PCIE_CAP_SLOT_CLK_CONFIG,Slot Clock Configuration. This bit indicates that the component uses the same physical reference clock that the platform provides on the connector. If the device uses an independent clock irrespective of the presence of a.." "0,1" newline rbitfld.long 0x10 27. "PCIE_CAP_LINK_TRAINING,Link Training. This read-only bit indicates that the Physical Layer LTSSM is in the Configuration or Recovery state or that 1b was written to the Retrain Link bit but Link training has not yet begun. Hardware clears this bit when.." "0,1" rbitfld.long 0x10 26. "RSVDP_26,Reserved for future use." "0,1" newline hexmask.long.byte 0x10 20.--25. 1. "PCIE_CAP_NEGO_LINK_WIDTH,Negotiated Link Width. This field indicates the negotiated width of the given PCI Express Link. Defined encodings are: -00 0001b: x1 -00 0010b: x2 -00 0100b: x4 -00 1000b: x8 -00 1100b: x12 -01 0000b: x16 -10 0000b: x32 All other.." hexmask.long.byte 0x10 16.--19. 1. "PCIE_CAP_LINK_SPEED,Current Link Speed. This field indicates the negotiated Link speed of the given PCI Express Link. The encoded value specifies a bit location in the Supported Link Speeds Vector (in the Link Capabilities 2 register) that corresponds to.." newline bitfld.long 0x10 14.--15. "PCIE_CAP_DRS_SIGNALING_CONTROL,DRS Signaling Control. Indicates the mechanism used to report reception of a DRS message. Must be implemented for Downstream Ports with the DRS Supported bit Set in the Link Capabilities 2 Register. Encodings are: - 00b:.." "0,1,2,3" rbitfld.long 0x10 12.--13. "RSVDP_12,Reserved for future use." "0,1,2,3" newline bitfld.long 0x10 11. "PCIE_CAP_LINK_AUTO_BW_INT_EN,Link Autonomous Bandwidth Management Interrupt Enable. When set this bit enables the generation of an interrupt to indicate that the Link Autonomous Bandwidth Status bit has been set. The write value is gated with the.." "0,1" bitfld.long 0x10 10. "PCIE_CAP_LINK_BW_MAN_INT_EN,Link Bandwidth Management Interrupt Enable. When set this bit enables the generation of an interrupt to indicate that the Link Bandwidth Management Status bit has been set. The write value is gated with the.." "0,1" newline bitfld.long 0x10 9. "PCIE_CAP_HW_AUTO_WIDTH_DISABLE,Hardware Autonomous Width Disable. When set this bit disables hardware from changing the Link width for reasons other than attempting to correct unreliable Link operation by reducing Link width. For a Multi-Function Device.." "0,1" bitfld.long 0x10 8. "PCIE_CAP_EN_CLK_POWER_MAN,Enable Clock Power Management. Applicable only for Upstream Ports and with form factors that support a 'Clock Request' (CLKREQ#) mechanism this bit operates as follows: - 0b: Clock power management is disabled and device must.." "0,1" newline bitfld.long 0x10 7. "PCIE_CAP_EXTENDED_SYNCH,Extended Synch. When set this bit forces the transmission of additional Ordered Sets when exiting the L0s state (see section 4.2.4.5 of PCI Express Base Specification) and when in the Recovery state (see section 4.2.6.4.1 of PCI.." "0,1" bitfld.long 0x10 6. "PCIE_CAP_COMMON_CLK_CONFIG,Common Clock Configuration. When set this bit indicates that this component and the component at the opposite end of this Link are operating with a distributed common reference clock. A value of 0b indicates that this.." "0,1" newline bitfld.long 0x10 5. "PCIE_CAP_RETRAIN_LINK,Retrain Link. A write of 1b to this bit initiates Link retraining by directing the Physical Layer LTSSM to the Recovery state. If the LTSSM is already in Recovery or Configuration re-entering Recovery is permitted but not required." "0,1" bitfld.long 0x10 4. "PCIE_CAP_LINK_DISABLE,Link Disable. This bit disables the Link by directing the LTSSM to the Disabled state when set; this bit is Reserved on Endpoints PCI Express to PCI/PCI-X bridges and Upstream Ports of Switches. Writes to this bit are immediately.." "0,1" newline bitfld.long 0x10 3. "PCIE_CAP_RCB,Read Completion Boundary (RCB). Root Ports: Indicates the RCB value for the Root Port. Refer to section 2.3.1.1 of PCI Express Base Specification for the definition of the parameter RCB. Defined encodings are: - 0b: 64 byte - 1b: 128 byte.." "0,1" rbitfld.long 0x10 2. "RSVDP_2,Reserved for future use." "0,1" newline bitfld.long 0x10 0.--1. "PCIE_CAP_ACTIVE_STATE_LINK_PM_CONTROL,Active State Power Management (ASPM) Control. This field controls the level of ASPM enabled on the given PCI Express Link. See section 5.4.1.3 of PCI Express Base Specification for requirements on when and how to.." "0,1,2,3" line.long 0x14 "SLOT_CAPABILITIES_REG,Slot Capabilities Register. The Slot Capabilities register identifies PCI Express slot specific capabilities." hexmask.long.word 0x14 19.--31. 1. "PCIE_CAP_PHY_SLOT_NUM,Physical Slot Number. This field indicates the physical slot number attached to this Port. This field must be hardware initialized to a value that assigns a slot number that is unique within the chassis regardless of the form.." bitfld.long 0x14 18. "PCIE_CAP_NO_CMD_CPL_SUPPORT,No Command Completed Support. When set this bit indicates that this slot does not generate software notification when an issued command is completed by the Hot-Plug Controller. This bit is only permitted to be set if the.." "0,1" newline bitfld.long 0x14 17. "PCIE_CAP_ELECTROMECH_INTERLOCK,Electromechanical Interlock Present. When set this bit indicates that an Electromechanical Interlock is implemented on the chassis for this slot. Note: The access attributes of this field are as follows: - Wire: No access." "0,1" bitfld.long 0x14 15.--16. "PCIE_CAP_SLOT_POWER_LIMIT_SCALE,Slot Power Limit Scale. Specifies the scale used for the Slot Power Limit Value (for more details see Section 6.9 of PCI Express Base Specification). Range of Values: - 00b: 1.0x - 01b: 0.1x - 10b: 0.01x - 11b: 0.001x.." "0,1,2,3" newline hexmask.long.byte 0x14 7.--14. 1. "PCIE_CAP_SLOT_POWER_LIMIT_VALUE,Slot Power Limit Value. In combination with the Slot Power Limit Scale value specifies the upper limit on power supplied by the slot (for more detais see Section 6.9 of PCI Express Base Specification) or by other means.." bitfld.long 0x14 6. "PCIE_CAP_HOT_PLUG_CAPABLE,Hot-Plug Capable. When set this bit indicates that this slot is capable of supporting hot-plug operations. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then R/W else R" "0,1" newline bitfld.long 0x14 5. "PCIE_CAP_HOT_PLUG_SURPRISE,Hot-Plug Surprise. When set this bit indicates that an adapter present in this slot might be removed from the system without any prior notification. This is a form factor specific capability. This bit is an indication to the.." "0,1" bitfld.long 0x14 4. "PCIE_CAP_POWER_INDICATOR,Power Indicator Present. When set this bit indicates that a Power Indicator is electrically controlled by the chassis for this slot. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if.." "0,1" newline bitfld.long 0x14 3. "PCIE_CAP_ATTENTION_INDICATOR,Attention Indicator Present. When set this bit indicates that an Attention Indicator is electrically controlled by the chassis. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if.." "0,1" bitfld.long 0x14 2. "PCIE_CAP_MRL_SENSOR,MRL Sensor Present. When set this bit indicates that an MRL Sensor is implemented on the chassis for this slot. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then R/W else R" "0,1" newline bitfld.long 0x14 1. "PCIE_CAP_POWER_CONTROLLER,Power Controller Present. When set this bit indicates that a software programmable Power Controller is implemented for this slot/adapter (depending on form factor). Note: The access attributes of this field are as follows: -.." "0,1" bitfld.long 0x14 0. "PCIE_CAP_ATTENTION_INDICATOR_BUTTON,Attention Button Present. When set this bit indicates that an Attention Button for this slot is electrically controlled by the chassis. Note: The access attributes of this field are as follows: - Wire: No access. -.." "0,1" line.long 0x18 "SLOT_CONTROL_SLOT_STATUS,Slot Control and Status Register. This register controls and provides information about PCI Express Slot specific parameters." hexmask.long.byte 0x18 25.--31. 1. "RSVDP_25,Reserved for future use." bitfld.long 0x18 24. "PCIE_CAP_DLL_STATE_CHANGED,Data Link Layer State Changed. This bit is set when the value reported in the Data Link Layer Link Active bit of the Link Status register is changed. In response to a Data Link Layer State Changed event software must read the.." "0,1" newline rbitfld.long 0x18 23. "PCIE_CAP_ELECTROMECH_INTERLOCK_STATUS,Electromechanical Interlock Status. If an Electromechanical Interlock is implemented this bit indicates the status of the Electromechanical Interlock. Defined encodings are: - 0b: Electromechanical Interlock.." "0,1" rbitfld.long 0x18 22. "PCIE_CAP_PRESENCE_DETECT_STATE,Presence Detect State. This bit indicates the presence of an adapter in the slot reflected by the logical 'OR' of the Physical Layer in-band presence detect mechanism and if present any out-of-band presence detect.." "0,1" newline rbitfld.long 0x18 21. "PCIE_CAP_MRL_SENSOR_STATE,MRL Sensor State. This bit reports the status of the MRL sensor if implemented. Defined encodings are: - 0b: MRL Closed - 1b: MRL Open" "0,1" bitfld.long 0x18 20. "PCIE_CAP_CMD_CPLD,Command Completed. If Command Completed notification is supported (if the No Command Completed Support bit in the Slot Capabilities register is 0b) this bit is set when a hot-plug command has completed and the Hot-Plug Controller is.." "0,1" newline bitfld.long 0x18 19. "PCIE_CAP_PRESENCE_DETECTED_CHANGED,Presence Detect Changed. This bit is set when the value reported in the Presence Detect State bit is changed." "0,1" bitfld.long 0x18 18. "PCIE_CAP_MRL_SENSOR_CHANGED,MRL Sensor Changed. If an MRL sensor is implemented this bit is set when a MRL Sensor state change is detected. If an MRL sensor is not implemented this bit must not be set." "0,1" newline bitfld.long 0x18 17. "PCIE_CAP_POWER_FAULT_DETECTED,Power Fault Detected. If a Power Controller that supports power fault detection is implemented this bit issSet when the Power Controller detects a power fault at this slot. Note: Depending on hardware capability it is.." "0,1" bitfld.long 0x18 16. "PCIE_CAP_ATTENTION_BUTTON_PRESSED,Attention Button Pressed. If an Attention Button is implemented this bit is set when the attention button is pressed. If an Attention Button is not supported this bit must not be set." "0,1" newline rbitfld.long 0x18 14.--15. "RSVDP_14,Reserved for future use." "0,1,2,3" bitfld.long 0x18 12. "PCIE_CAP_DLL_STATE_CHANGED_EN,Data Link Layer State Changed Enable. If the Data Link Layer Link Active Reporting capability is 1b this bit enables software notification when Data Link Layer Link Active bit is changed. If the Data Link Layer Link Active.." "0,1" newline bitfld.long 0x18 11. "PCIE_CAP_ELECTROMECH_INTERLOCK_CTRL,Electromechanical Interlock Control. If an Electromechanical Interlock is implemented a write of 1b to this bit causes the state of the interlock to toggle. A write of 0b to this bit has no effect. A read of this bit.." "0,1" bitfld.long 0x18 10. "PCIE_CAP_POWER_CONTROLLER_CTRL,Power Controller Control. If a Power Controller is implemented this bit when written sets the power state of the slot per the defined encodings. Reads of this bit must reflect the value from the latest write even if the.." "0,1" newline bitfld.long 0x18 8.--9. "PCIE_CAP_POWER_INDICATOR_CTRL,Power Indicator Control. If a Power Indicator is implemented writes to this field set the Power Indicator to the written state. Reads of this field must reflect the value from the latest write even if the corresponding.." "0,1,2,3" bitfld.long 0x18 6.--7. "PCIE_CAP_ATTENTION_INDICATOR_CTRL,Attention Indicator Control. If an Attention Indicator is implemented writes to this field set the Attention Indicator to the written state. Reads of this field must reflect the value from the latest write even if the.." "0,1,2,3" newline bitfld.long 0x18 5. "PCIE_CAP_HOT_PLUG_INT_EN,Hot-Plug Interrupt Enable. When set this bit enables generation of an interrupt on enabled hot-plug events. If the Hot Plug Capable bit in the Slot Capabilities register is clear this bit is permitted to be read-only with a.." "0,1" bitfld.long 0x18 4. "PCIE_CAP_CMD_CPL_INT_EN,Command Completed Interrupt Enable. If Command Completed notification is supported (if the No Command Completed Support bit in the Slot Capabilities register is 0b) when set this bit enables software notification when a hot-plug.." "0,1" newline bitfld.long 0x18 3. "PCIE_CAP_PRESENCE_DETECT_CHANGE_EN,Presence Detect Changed Enable. When set this bit enables software notification on a presence detect changed event (for more details see Section 6.7.3 of PCI Express Base Specification). If the Hot-Plug Capable bit in.." "0,1" bitfld.long 0x18 2. "PCIE_CAP_MRL_SENSOR_CHANGED_EN,MRL Sensor Changed Enable. When set this bit enables software notification on a MRL sensor changed event (for more details see Section 6.7.3 of PCI Express Base Specification). If the MRL Sensor Present bit in the Slot.." "0,1" newline bitfld.long 0x18 1. "PCIE_CAP_POWER_FAULT_DETECTED_EN,Power Fault Detected Enable. When set this bit enables software notification on a power fault event (for more details see Section 6.7.3 of PCI Express Base Specification). If a Power Controller that supports power fault.." "0,1" bitfld.long 0x18 0. "PCIE_CAP_ATTENTION_BUTTON_PRESSED_EN,Attention Button Pressed Enable. When set to 1b this bit enables software notification on an attention button pressed event (for more details see Section 6.7.3 of PCI Express Base Specification). If the Attention.." "0,1" line.long 0x1C "ROOT_CONTROL_ROOT_CAPABILITIES_REG,Root Control and Capabilities Register. This register controls PCI Express Root Complex specific parameters and identifies PCI Express Root Port specific capabilities." hexmask.long.word 0x1C 17.--31. 1. "RSVDP_17,Reserved for future use." bitfld.long 0x1C 16. "PCIE_CAP_CRS_SW_VISIBILITY,CRS Software Visibility Capable. For a description of this standard PCIe register field see the PCI Express Base Specification. CRS Software Visibility. When set this bit indicates that the Root Port is capable of returning.." "0,1" newline hexmask.long.word 0x1C 5.--15. 1. "RSVDP_5,Reserved for future use." bitfld.long 0x1C 4. "PCIE_CAP_CRS_SW_VISIBILITY_EN,CRS Software Visibility Enable. When set this bit enables the Root Port to return Configuration Request Retry Status (CRS) Completion Status to software (for more details see section 2.3.1 of PCI Express Base.." "0,1" newline bitfld.long 0x1C 3. "PCIE_CAP_PME_INT_EN,PME Interrupt Enable. When set this bit enables PME interrupt generation upon receipt of a PME Message as reflected in the PME Status bit (for more details see Table 7-29 of PCI Express Base Specification). A PME interrupt is also.." "0,1" bitfld.long 0x1C 2. "PCIE_CAP_SYS_ERR_ON_FATAL_ERR_EN,System Error on Fatal Error Enable. If set this bit indicates that a System Error should be generated if a Fatal error (ERR_FATAL) is reported by any of the devices in the Hierarchy Domain associated with this Root Port.." "0,1" newline bitfld.long 0x1C 1. "PCIE_CAP_SYS_ERR_ON_NON_FATAL_ERR_EN,System Error on Non-Fatal Error Enable. If set this bit indicates that a System Error should be generated if a Non-fatal error (ERR_NONFATAL) is reported by any of the devices in the Hierarchy Domain associated with.." "0,1" bitfld.long 0x1C 0. "PCIE_CAP_SYS_ERR_ON_CORR_ERR_EN,System Error on Correctable Error Enable. If set this bit indicates that a System Error should be generated if a correctable error (ERR_COR) is reported by any of the devices in the Hierarchy Domain associated with this.." "0,1" line.long 0x20 "ROOT_STATUS_REG,Root Status Register. The Root Status register provides information about PCI Express device specific parameters." hexmask.long.word 0x20 18.--31. 1. "RSVDP_18,Reserved for future use." rbitfld.long 0x20 17. "PCIE_CAP_PME_PENDING,PME Pending. This bit indicates that another PME is pending when the PME Status bit is s et. When the PME Status bit is cleared by software; the PME is delivered by hardware by setting the PME Status bit again and updating the PME.." "0,1" newline bitfld.long 0x20 16. "PCIE_CAP_PME_STATUS,PME Status. This bit indicates that PME was asserted by the PME Requester indicated in the PME Requester ID field. Subsequent PMEs are kept pending until the status register is cleared by software by writing a 1b." "0,1" hexmask.long.word 0x20 0.--15. 1. "PCIE_CAP_PME_REQ_ID,PME Requester ID. This field indicates the PCI Requester ID of the last PME Requester. This field is only valid when the PME Status bit is set." line.long 0x24 "DEVICE_CAPABILITIES2_REG,Device Capabilities 2 Register." bitfld.long 0x24 31. "PCIE_CAP_FRS_SUPPORTED,FRS Supported. When set indicates support for the optional Function Readiness Status (FRS) capability. Must be set for all Functions that support generation or reception capabilities of FRS Messages. Must not be set by Switch.." "0,1" hexmask.long.byte 0x24 24.--30. 1. "RSVDP_24,Reserved for future use." newline bitfld.long 0x24 22.--23. "PCIE_CAP2_CFG_MAX_END2END_TLP_PRFXS,Max End-End TLP Prefixes. Indicates the maximum number of End-End TLP Prefixes supported by this Function. For more details see Section 2.2.10.2 of PCI Express Base Specification. Values are: - 01b: 1 End-End TLP.." "0,1,2,3" bitfld.long 0x24 21. "PCIE_CAP2_CFG_END2END_TLP_PRFX_SUPPORT,End-End TLP Prefix Supported. Indicates whether End-End TLP Prefix support is offered by a Function. Values are: - 0b: No Support - 1b: Support is provided to receive TLPs containing End-End TLP Prefixes. All Ports.." "0,1" newline bitfld.long 0x24 20. "PCIE_CAP2_CFG_EXTND_FMT_SUPPORT,Extended Fmt Field Supported. If set the Function supports the 3-bit definition of the Fmt field. If clear the Function supports a 2-bit definition of the Fmt field. For more details see section 2.2 of PCI Express Base.." "0,1" rbitfld.long 0x24 17. "PCIE_CAP2_10_BIT_TAG_REQ_SUPPORT,10-Bit Tag Requester Supported. If this bit is set the Function supports 10-Bit Tag Requester capability; otherwise the Function does not. This bit must not be set if the 10-Bit Tag Completer Supported bit is clear." "0,1" newline rbitfld.long 0x24 16. "PCIE_CAP2_10_BIT_TAG_COMP_SUPPORT,10-Bit Tag Completer Supported. If this bit is set the Function supports 10-Bit Tag Completer capability; otherwise the Function does not. For more details see section 2.2.6.2. of PCI Express Base Specification." "0,1" rbitfld.long 0x24 13. "PCIE_CAP_TPH_CMPLT_SUPPORT_1,TPH Completer Supported Bit 1." "0,1" newline rbitfld.long 0x24 12. "PCIE_CAP_TPH_CMPLT_SUPPORT_0,TPH Completer Supported Bit 0. Value of this bit along with TPH Completer Supported Bit 1 indicates Completer support for TPH or Extended TPH. Applicable only to Root Ports and Endpoints. For all other Functions this field.." "0,1" bitfld.long 0x24 11. "PCIE_CAP_LTR_SUPP,LTR Mechanism Supported. A value of 1b indicates support for the optional Latency Tolerance Reporting (LTR) mechanism. Root Ports Switches and Endpoints are permitted to implement this capability. For a Multi-Function Device associated.." "0,1" newline rbitfld.long 0x24 10. "PCIE_CAP_NO_RO_EN_PR2PR_PAR,No RO-enabled PR-PR Passing. If this bit is set the routing element never carries out the passing permitted by Table 2-39 of PCI Express Base Specification entry A2b that is associated with the Relaxed Ordering Attribute.." "0,1" rbitfld.long 0x24 9. "PCIE_CAP_128_CAS_CPL_SUPP,128-bit CAS Completer Supported. Applicable to Functions with Memory Space BARs as well as all Root Ports; must be 0b otherwise. This bit must be set to 1b if the Function supports this optional capability. For more details see.." "0,1" newline rbitfld.long 0x24 8. "PCIE_CAP_64_ATOMIC_CPL_SUPP,64-bit AtomicOp Completer Supported. Applicable to Functions with Memory Space BARs as well as all Root Ports; must be 0b otherwise. Includes FetchAdd Swap and CAS AtomicOps. This bit must be set to 1b if the Function.." "0,1" rbitfld.long 0x24 7. "PCIE_CAP_32_ATOMIC_CPL_SUPP,32-bit AtomicOp Completer Supported. Applicable to Functions with Memory Space BARs as well as all Root Ports; must be 0b otherwise. Includes FetchAdd Swap and CAS AtomicOps. This bit must be set to 1b if the Function.." "0,1" newline rbitfld.long 0x24 6. "PCIE_CAP_ATOMIC_ROUTING_SUPP,AtomicOp Routing Supported. Applicable only to Switch Upstream Ports Switch Downstream Ports and Root Ports; must be 0b for other Function types. This bit must be set to 1b if the Port supports this optional capability. For.." "0,1" rbitfld.long 0x24 5. "PCIE_CAP_ARI_FORWARD_SUPPORT,ARI Forwarding Supported. Applicable only to Switch Downstream Ports and Root Ports; must be 0b for other Function types. This bit must be set to 1b if a Switch Downstream Port or Root Port supports this optional capability." "0,1" newline rbitfld.long 0x24 4. "PCIE_CAP_CPL_TIMEOUT_DISABLE_SUPPORT,Completion Timeout Disable Supported. A value of 1b indicates support for the Completion Timeout Disable mechanism. The Completion Timeout Disable mechanism is required for Endpoints that issue Requests on their own.." "0,1" hexmask.long.byte 0x24 0.--3. 1. "PCIE_CAP_CPL_TIMEOUT_RANGE,Completion Timeout Ranges Supported. This field indicates device Function support for the optional Completion Timeout programmability mechanism. This mechanism allows system software to modify the Completion Timeout value. This.." line.long 0x28 "DEVICE_CONTROL2_DEVICE_STATUS2_REG,Device Control 2 and Status 2 Register." hexmask.long.word 0x28 16.--31. 1. "RSVDP_16,Reserved for future use." bitfld.long 0x28 15. "PCIE_CTRL2_CFG_END2END_TLP_PFX_BLCK,End-End TLP Prefix Blocking. Controls whether the routing function is permitted to forward TLPs containing an End-End TLP Prefix. Values are: - 0b: Forwarding Enabled - Function is permitted to send TLPs with End-End.." "0,1" newline rbitfld.long 0x28 11. "RSVDP_11,Reserved for future use." "0,1" bitfld.long 0x28 10. "PCIE_CAP_LTR_EN,LTR Mechanism Enable. When set to 1b this bit enables Upstream Ports to send LTR messages and Downstream Ports to process LTR Messages. For a Multi-Function Device associated with an Upstream Port of a device that implements LTR the bit.." "0,1" newline rbitfld.long 0x28 5. "PCIE_CAP_ARI_FORWARD_SUPPORT_CS,ARI Forwarding Enable. When set the Downstream Port disables its traditional Device Number field being 0 enforcement when turning a Type 1 Configuration Request into a Type 0 Configuration Request permitting access to.." "0,1" bitfld.long 0x28 4. "PCIE_CAP_CPL_TIMEOUT_DISABLE,Completion Timeout Disable. When set this bit disables the Completion Timeout mechanism. This bit is required for all Functions that support the Completion Timeout Disable Capability. Functions that do not support this.." "0,1" newline hexmask.long.byte 0x28 0.--3. 1. "PCIE_CAP_CPL_TIMEOUT_VALUE,Completion Timeout Value. In device Functions that support Completion Timeout programmability this field allows system software to modify the Completion Timeout value. This field is applicable to Root Ports Endpoints that.." line.long 0x2C "LINK_CAPABILITIES2_REG,Link Capabilities 2 Register." bitfld.long 0x2C 31. "DRS_SUPPORTED,DRS Supported. When set indicates support for the optional Device Readiness Status (DRS) capability. Must be Set in Downstream Ports that support DRS. Must be Set in Downstream Ports that support FRS. For Upstream Ports that support DRS.." "0,1" hexmask.long.byte 0x2C 25.--30. 1. "RSVDP_25,Reserved for future use." newline hexmask.long.word 0x2C 9.--22. 1. "RSVDP_9,Reserved for future use." rbitfld.long 0x2C 8. "PCIE_CAP_CROSS_LINK_SUPPORT,Crosslink Supported. When set to 1b this bit indicates that the associated Port supports crosslinks (for more details see section 4.2.6.3.1 of PCI Express Base Specification). When set to 0b on a Port that supports Link.." "0,1" newline hexmask.long.byte 0x2C 1.--7. 1. "PCIE_CAP_SUPPORT_LINK_SPEED_VECTOR,Supported Link Speeds Vector. This field indicates the supported Link speed(s) of the associated Port. For each bit a value of 1b indicates that the corresponding Link speed is supported; otherwise the Link speed is.." rbitfld.long 0x2C 0. "RSVDP_0,Reserved for future use." "0,1" line.long 0x30 "LINK_CONTROL2_LINK_STATUS2_REG,Link Control 2 and Status 2 Register." bitfld.long 0x30 31. "DRS_MESSAGE_RECEIVED,DRS Message Received. This bit must be set whenever the Port receives a DRS Message. This bit must be cleared in DL_Down. This bit must be implemented in any Downstream Port where the DRS Supported bit is Set in the Link Capabilities.." "0,1" rbitfld.long 0x30 28.--30. "DOWNSTREAM_COMPO_PRESENCE,Downstream Component Presence. This field indicates the presence and DRS status for the Downstream Component if any connected to the Link; defined values are: - 000b: Link Down - Presence Not Determined - 001b: Link Down -.." "0,1,2,3,4,5,6,7" newline rbitfld.long 0x30 26.--27. "RSVDP_26,Reserved for future use." "0,1,2,3" bitfld.long 0x30 21. "PCIE_CAP_LINK_EQ_REQ,Link Equalization Request 8.0 GT/s. This bit is set by hardware to request the 8.0 GT/s Link equalization process to be performed on the Link. For more details see sections 4.2.3 and 4.2.6.4.2 of PCI Express Base Specification. For.." "0,1" newline rbitfld.long 0x30 20. "PCIE_CAP_EQ_CPL_P3,EEqualization 8.0 GT/s Phase 3 Successful. When set to 1b this bit indicates that Phase 3 of the 8.0 GT/s Transmitter Equalization procedure has successfully completed. Details of the Transmitter Equalization process and when this bit.." "0,1" rbitfld.long 0x30 19. "PCIE_CAP_EQ_CPL_P2,Equalization 8.0 GT/s Phase 2 Successful. When set to 1b this bit indicates that Phase 2 of the 8.0 GT/s Transmitter Equalization procedure has successfully completed. Details of the Transmitter Equalization process and when this bit.." "0,1" newline rbitfld.long 0x30 18. "PCIE_CAP_EQ_CPL_P1,Equalization 8.0 GT/s Phase 1 Successful. When set to 1b this bit indicates that Phase 1 of the 8.0 GT/s Transmitter Equalization procedure has successfully completed. Details of the Transmitter Equalization process and when this bit.." "0,1" rbitfld.long 0x30 17. "PCIE_CAP_EQ_CPL,Equalization 8.0 GT/s Complete. When set to 1b this bit indicates that the Transmitter Equalization procedure at the 8.0 GT/s data rate has completed. Details of the Transmitter Equalization process and when this bit needs to be set to.." "0,1" newline rbitfld.long 0x30 16. "PCIE_CAP_CURR_DEEMPHASIS,Current De-emphasis Level. When the Link is operating at 5.0 GT/s speed this bit reflects the level of de-emphasis. Encodings: - 1b: -3.5 dB - 0b: -6 dB The value in this bit is undefined when the Link is not operating at 5.0.." "0,1" hexmask.long.byte 0x30 12.--15. 1. "PCIE_CAP_COMPLIANCE_PRESET,Compliance Preset/De-emphasis. For 8.0 GT/s and higher Data Rate: This field sets the Transmitter Preset in Polling.Compliance state if the entry occurred due to the Enter Compliance bit being 1b. The encodings are defined in.." newline bitfld.long 0x30 11. "PCIE_CAP_COMPLIANCE_SOS,Compliance SOS. When set to 1b the LTSSM is required to send SKP Ordered Sets between sequences when sending the Compliance Pattern or Modified Compliance Pattern. For a Multi-Function Device associated with an Upstream Port the.." "0,1" bitfld.long 0x30 10. "PCIE_CAP_ENTER_MODIFIED_COMPLIANCE,Enter Modified Compliance. When this bit is set to 1b the device transmits Modified Compliance Pattern if the LTSSM enters Polling.Compliance substate. Components that support only the 2.5 GT/s speed are permitted to.." "0,1" newline bitfld.long 0x30 7.--9. "PCIE_CAP_TX_MARGIN,Transmit Margin - This field controls the value of the non-deemphasized voltage level at the Transmitter pins. This field is reset to 000b on entry to the LTSSM Polling.Configuration substate (see Chapter 4 of PCI Express Base.." "0,1,2,3,4,5,6,7" bitfld.long 0x30 6. "PCIE_CAP_SEL_DEEMPHASIS,Selectable De-emphasis. When the Link is operating at 5.0 GT/s speed this bit is used to control the transmit de-emphasis of the link in specific situations. For more details see section 4.2.6 of PCI Express Base Specification." "0,1" newline bitfld.long 0x30 5. "PCIE_CAP_HW_AUTO_SPEED_DISABLE,Hardware Autonomous Speed Disable. When set this bit disables hardware from changing the Link speed for device-specific reasons other than attempting to correct unreliable Link operation by reducing Link speed. Initial.." "0,1" bitfld.long 0x30 4. "PCIE_CAP_ENTER_COMPLIANCE,Enter Compliance. Software is permitted to force a Link to enter Compliance mode (at the speed indicated in the Target Link Speed field and the de-emphasis/preset level indicated by the Compliance Preset/De-emphasis field) by.." "0,1" newline hexmask.long.byte 0x30 0.--3. 1. "PCIE_CAP_TARGET_LINK_SPEED,Target Link Speed. For Downstream Ports this field sets an upper limit on Link operational speed by restricting the values advertised by the Upstream component in its training sequences. The encoded value specifies a bit.." tree.end tree "PF0_AER_CAP (PF Advanced Error Reporting Capability Structure)" group.long (0x0+0x100)++0x1B line.long 0x0 "AER_EXT_CAP_HDR_OFF,Advanced Error Reporting Extended Capability Header. For a description of this standard PCIe register. see the PCI Express Specification." hexmask.long.word 0x0 20.--31. 1. "NEXT_OFFSET,Next Capability Offset. For a description of this standard PCIe register field see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky).." hexmask.long.byte 0x0 16.--19. 1. "CAP_VERSION,Capability Version. For a description of this standard PCIe register field see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else.." hexmask.long.word 0x0 0.--15. 1. "CAP_ID,AER Extended Capability ID. For a description of this standard PCIe register field see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else.." line.long 0x4 "UNCORR_ERR_STATUS_OFF,Uncorrectable Error Status Register. For a description of this standard PCIe register. see the PCI Express Specification." hexmask.long.byte 0x4 27.--31. 1. "RSVDP_27,Reserved for future use." bitfld.long 0x4 25. "TLP_PRFX_BLOCKED_ERR_STATUS,TLP Prefix Blocked Error Status. For a description of this standard PCIe register field see the PCI Express Specification. Note: Not supported." "0,1" rbitfld.long 0x4 23. "RSVDP_23,Reserved for future use." "0,1" newline bitfld.long 0x4 22. "INTERNAL_ERR_STATUS,Uncorrectable Internal Error Status. For a description of this standard PCIe register field see the PCI Express Specification. The controller sets this bit when your application asserts app_err_bus[9]. It does not set this bit when.." "0,1" bitfld.long 0x4 20. "UNSUPPORTED_REQ_ERR_STATUS,Unsupported Request Error Status. For a description of this standard PCIe register field see the PCI Express Specification." "0,1" bitfld.long 0x4 19. "ECRC_ERR_STATUS,ECRC Error Status. For a description of this standard PCIe register field see the PCI Express Specification. Note:If CX_ECRC_ENABLE=0 the register field always reads 0." "0,1" newline bitfld.long 0x4 18. "MALF_TLP_ERR_STATUS,Malformed TLP Status. For a description of this standard PCIe register field see the PCI Express Specification." "0,1" bitfld.long 0x4 17. "REC_OVERFLOW_ERR_STATUS,Receiver Overflow Status. For a description of this standard PCIe register field see the PCI Express Specification." "0,1" bitfld.long 0x4 16. "UNEXP_CMPLT_ERR_STATUS,Unexpected Completion Status. For a description of this standard PCIe register field see the PCI Express Specification." "0,1" newline bitfld.long 0x4 15. "CMPLT_ABORT_ERR_STATUS,Completer Abort Status. For a description of this standard PCIe register field see the PCI Express Specification." "0,1" bitfld.long 0x4 14. "CMPLT_TIMEOUT_ERR_STATUS,Completion Timeout Status. For a description of this standard PCIe register field see the PCI Express Specification." "0,1" bitfld.long 0x4 13. "FC_PROTOCOL_ERR_STATUS,Flow Control Protocol Error Status. For a description of this standard PCIe register field see the PCI Express Specification." "0,1" newline bitfld.long 0x4 12. "POIS_TLP_ERR_STATUS,Poisoned TLP Status. For a description of this standard PCIe register field see the PCI Express Specification." "0,1" hexmask.long.byte 0x4 6.--11. 1. "RSVDP_6,Reserved for future use." bitfld.long 0x4 5. "SURPRISE_DOWN_ERR_STATUS,Surprise Down Error Status (Optional). For a description of this standard PCIe register field see the PCI Express Specification." "0,1" newline bitfld.long 0x4 4. "DL_PROTOCOL_ERR_STATUS,Data Link Protocol Error Status. For a description of this standard PCIe register field see the PCI Express Specification." "0,1" hexmask.long.byte 0x4 0.--3. 1. "RSVDP_0,Reserved for future use." line.long 0x8 "UNCORR_ERR_MASK_OFF,Uncorrectable Error Mask Register. For a description of this standard PCIe register. see the PCI Express Specification." hexmask.long.byte 0x8 27.--31. 1. "RSVDP_27,Reserved for future use." bitfld.long 0x8 25. "TLP_PRFX_BLOCKED_ERR_MASK,TLP Prefix Blocked Error Mask. For a description of this standard PCIe register field see the PCI Express Specification. Note: Not supported. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi:.." "0,1" rbitfld.long 0x8 23. "RSVDP_23,Reserved for future use." "0,1" newline bitfld.long 0x8 22. "INTERNAL_ERR_MASK,Uncorrectable Internal Error Mask (Optional). For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." "0,1" rbitfld.long 0x8 21. "ACS_VIOLATION_MASK,ACS Violation Mask. Setting the ACS Violation Mask bit disables error logging and signaling for ACS Violation errors. The bit is Read-Only Zero for upstream ports when ACS P2P Egress Control Enable is not set. For a description of.." "0,1" bitfld.long 0x8 20. "UNSUPPORTED_REQ_ERR_MASK,Unsupported Request Error Mask. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." "0,1" newline bitfld.long 0x8 19. "ECRC_ERR_MASK,ECRC Error Mask (Optional). For a description of this standard PCIe register field see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W (sticky) Note: This register.." "0,1" bitfld.long 0x8 18. "MALF_TLP_ERR_MASK,Malformed TLP Mask. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." "0,1" bitfld.long 0x8 17. "REC_OVERFLOW_ERR_MASK,Receiver Overflow Mask (Optional). For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." "0,1" newline bitfld.long 0x8 16. "UNEXP_CMPLT_ERR_MASK,Unexpected Completion Mask. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." "0,1" bitfld.long 0x8 15. "CMPLT_ABORT_ERR_MASK,Completer Abort Error Mask (Optional). For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." "0,1" bitfld.long 0x8 14. "CMPLT_TIMEOUT_ERR_MASK,Completion Timeout Error Mask. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." "0,1" newline bitfld.long 0x8 13. "FC_PROTOCOL_ERR_MASK,Flow Control Protocol Error Mask. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." "0,1" bitfld.long 0x8 12. "POIS_TLP_ERR_MASK,Poisoned TLP Error Mask. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." "0,1" hexmask.long.byte 0x8 6.--11. 1. "RSVDP_6,Reserved for future use." newline rbitfld.long 0x8 5. "SURPRISE_DOWN_ERR_MASK,Surprise Down Error Mask. For a description of this standard PCIe register field see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi:.." "0,1" bitfld.long 0x8 4. "DL_PROTOCOL_ERR_MASK,Data Link Protocol Error Mask. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." "0,1" hexmask.long.byte 0x8 0.--3. 1. "RSVDP_0,Reserved for future use." line.long 0xC "UNCORR_ERR_SEV_OFF,Uncorrectable Error Severity Register. For a description of this standard PCIe register. see the PCI Express Specification." hexmask.long.byte 0xC 27.--31. 1. "RSVDP_27,Reserved for future use." bitfld.long 0xC 25. "TLP_PRFX_BLOCKED_ERR_SEVERITY,TLP Prefix Blocked Error Severity (Optional). For a description of this standard PCIe register field see the PCI Express Specification. Note: Not supported. Note: The access attributes of this field are as follows: - Wire:.." "0,1" rbitfld.long 0xC 24. "ATOMIC_EGRESS_BLOCKED_ERR_SEVERITY,AtomicOp Egress Blocked Severity (Optional). For a description of this standard PCIe register field see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi:.." "0,1" newline rbitfld.long 0xC 23. "RSVDP_23,Reserved for future use." "0,1" bitfld.long 0xC 22. "INTERNAL_ERR_SEVERITY,Uncorrectable Internal Error Severity (Optional). For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." "0,1" bitfld.long 0xC 20. "UNSUPPORTED_REQ_ERR_SEVERITY,Unsupported Request Error Severity. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." "0,1" newline bitfld.long 0xC 19. "ECRC_ERR_SEVERITY,ECRC Error Severity (Optional). For a description of this standard PCIe register field see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W (sticky) Note: This.." "0,1" bitfld.long 0xC 18. "MALF_TLP_ERR_SEVERITY,Malformed TLP Severity. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." "0,1" bitfld.long 0xC 17. "REC_OVERFLOW_ERR_SEVERITY,Receiver Overflow Error Severity (Optional). For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." "0,1" newline bitfld.long 0xC 16. "UNEXP_CMPLT_ERR_SEVERITY,Unexpected Completion Error Severity. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." "0,1" bitfld.long 0xC 15. "CMPLT_ABORT_ERR_SEVERITY,Completer Abort Error Severity (Optional). For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." "0,1" bitfld.long 0xC 14. "CMPLT_TIMEOUT_ERR_SEVERITY,Completion Timeout Error Severity. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." "0,1" newline bitfld.long 0xC 13. "FC_PROTOCOL_ERR_SEVERITY,Flow Control Protocol Error Severity (Optional). For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." "0,1" bitfld.long 0xC 12. "POIS_TLP_ERR_SEVERITY,Poisoned TLP Severity. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." "0,1" hexmask.long.byte 0xC 6.--11. 1. "RSVDP_6,Reserved for future use." newline rbitfld.long 0xC 5. "SURPRISE_DOWN_ERR_SVRITY,Surprise Down Error Severity (Optional). For a description of this standard PCIe register field see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi:.." "0,1" bitfld.long 0xC 4. "DL_PROTOCOL_ERR_SEVERITY,Data Link Protocol Error Severity. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." "0,1" hexmask.long.byte 0xC 0.--3. 1. "RSVDP_0,Reserved for future use." line.long 0x10 "CORR_ERR_STATUS_OFF,Correctable Error Status Register. For a description of this standard PCIe register. see the PCI Express Specification." hexmask.long.word 0x10 16.--31. 1. "RSVDP_16,Reserved for future use." bitfld.long 0x10 15. "HEADER_LOG_OVERFLOW_STATUS,Header Log Overflow Error Status (Optional). For a description of this standard PCIe register field see the PCI Express Specification." "0,1" bitfld.long 0x10 14. "CORRECTED_INT_ERR_STATUS,Corrected Internal Error Status (Optional). For a description of this standard PCIe register field see the PCI Express Specification." "0,1" newline bitfld.long 0x10 13. "ADVISORY_NON_FATAL_ERR_STATUS,Advisory Non-Fatal Error Status. For a description of this standard PCIe register field see the PCI Express Specification." "0,1" bitfld.long 0x10 12. "RPL_TIMER_TIMEOUT_STATUS,Replay Timer Timeout Status. For a description of this standard PCIe register field see the PCI Express Specification." "0,1" rbitfld.long 0x10 9.--11. "RSVDP_9,Reserved for future use." "0,1,2,3,4,5,6,7" newline bitfld.long 0x10 8. "REPLAY_NO_ROLEOVER_STATUS,REPLAY_NUM Rollover Status. For a description of this standard PCIe register field see the PCI Express Specification." "0,1" bitfld.long 0x10 7. "BAD_DLLP_STATUS,Bad DLLP Status. For a description of this standard PCIe register field see the PCI Express Specification." "0,1" bitfld.long 0x10 6. "BAD_TLP_STATUS,Bad TLP Status. For a description of this standard PCIe register field see the PCI Express Specification." "0,1" newline hexmask.long.byte 0x10 1.--5. 1. "RSVDP_1,Reserved for future use." bitfld.long 0x10 0. "RX_ERR_STATUS,Receiver Error Status (Optional). For a description of this standard PCIe register field see the PCI Express Specification." "0,1" line.long 0x14 "CORR_ERR_MASK_OFF,Correctable Error Mask Register. For a description of this standard PCIe register. see the PCI Express Specification." hexmask.long.word 0x14 16.--31. 1. "RSVDP_16,Reserved for future use." bitfld.long 0x14 15. "HEADER_LOG_OVERFLOW_MASK,Header Log Overflow Error Mask (Optional). For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." "0,1" bitfld.long 0x14 14. "CORRECTED_INT_ERR_MASK,Corrected Internal Error Mask (Optional). For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." "0,1" newline bitfld.long 0x14 13. "ADVISORY_NON_FATAL_ERR_MASK,Advisory Non-Fatal Error Mask. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." "0,1" bitfld.long 0x14 12. "RPL_TIMER_TIMEOUT_MASK,Replay Timer Timeout Mask. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." "0,1" rbitfld.long 0x14 9.--11. "RSVDP_9,Reserved for future use." "0,1,2,3,4,5,6,7" newline bitfld.long 0x14 8. "REPLAY_NO_ROLEOVER_MASK,REPLAY_NUM Rollover Mask. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." "0,1" bitfld.long 0x14 7. "BAD_DLLP_MASK,Bad DLLP Mask. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." "0,1" bitfld.long 0x14 6. "BAD_TLP_MASK,Bad TLP Mask. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." "0,1" newline hexmask.long.byte 0x14 1.--5. 1. "RSVDP_1,Reserved for future use." bitfld.long 0x14 0. "RX_ERR_MASK,Receiver Error Mask (Optional). For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." "0,1" line.long 0x18 "ADV_ERR_CAP_CTRL_OFF,Advanced Error Capabilities and Control Register. For a description of this standard PCIe register. see the PCI Express Specification." hexmask.long.tbyte 0x18 13.--31. 1. "RSVDP_13,Reserved for future use." rbitfld.long 0x18 12. "CTO_PRFX_HDR_LOG_CAP,TLP Prefix Log Present. For a description of this standard PCIe register field see the PCI Express Specification." "0,1" rbitfld.long 0x18 11. "TLP_PRFX_LOG_PRESENT,Completion Timeout Prefix/Header Log Capable. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." "0,1" newline rbitfld.long 0x18 10. "MULTIPLE_HEADER_EN,Multiple Header Recording Enable. For a description of this standard PCIe register field see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R (sticky) Note: This.." "0,1" rbitfld.long 0x18 9. "MULTIPLE_HEADER_CAP,Multiple Header Recording Capable. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." "0,1" bitfld.long 0x18 8. "ECRC_CHECK_EN,ECRC Check Enable. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." "0,1" newline rbitfld.long 0x18 7. "ECRC_CHECK_CAP,ECRC Check Capable. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." "0,1" bitfld.long 0x18 6. "ECRC_GEN_EN,ECRC Generation Enable. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." "0,1" rbitfld.long 0x18 5. "ECRC_GEN_CAP,ECRC Generation Capable. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." "0,1" newline hexmask.long.byte 0x18 0.--4. 1. "FIRST_ERR_POINTER,First Error Pointer. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." rgroup.long (0x1C+0x100)++0xF line.long 0x0 "HDR_LOG_0_OFF,Header Log Register 0. For a description of this standard PCIe register. see the PCI Express Specification." hexmask.long.byte 0x0 24.--31. 1. "FIRST_DWORD_FOURTH_BYTE,Byte 3 of Header log register of First 32 bit Data Word. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." hexmask.long.byte 0x0 16.--23. 1. "FIRST_DWORD_THIRD_BYTE,Byte 2 of Header log register of First 32 bit Data Word. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." hexmask.long.byte 0x0 8.--15. 1. "FIRST_DWORD_SECOND_BYTE,Byte 1 of Header log register of First 32 bit Data Word. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." newline hexmask.long.byte 0x0 0.--7. 1. "FIRST_DWORD_FIRST_BYTE,Byte 0 of Header log register of First 32 bit Data Word. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." line.long 0x4 "HDR_LOG_1_OFF,Header Log Register 1. For a description of this standard PCIe register. see the PCI Express Specification." hexmask.long.byte 0x4 24.--31. 1. "SECOND_DWORD_FOURTH_BYTE,Byte 3 of Header log register of Second 32 bit Data Word. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." hexmask.long.byte 0x4 16.--23. 1. "SECOND_DWORD_THIRD_BYTE,Byte 2 of Header log register of Second 32 bit Data Word. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." hexmask.long.byte 0x4 8.--15. 1. "SECOND_DWORD_SECOND_BYTE,Byte 1 of Header log register of Second 32 bit Data Word. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." newline hexmask.long.byte 0x4 0.--7. 1. "SECOND_DWORD_FIRST_BYTE,Byte 0 of Header log register of Second 32 bit Data Word. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." line.long 0x8 "HDR_LOG_2_OFF,Header Log Register 2. For a description of this standard PCIe register. see the PCI Express Specification." hexmask.long.byte 0x8 24.--31. 1. "THIRD_DWORD_FOURTH_BYTE,Byte 3 of Header log register of Third 32 bit Data Word. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." hexmask.long.byte 0x8 16.--23. 1. "THIRD_DWORD_THIRD_BYTE,Byte 2 of Header log register of Third 32 bit Data Word. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." hexmask.long.byte 0x8 8.--15. 1. "THIRD_DWORD_SECOND_BYTE,Byte 1 of Header log register of Third 32 bit Data Word. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." newline hexmask.long.byte 0x8 0.--7. 1. "THIRD_DWORD_FIRST_BYTE,Byte 0 of Header log register of Third 32 bit Data Word. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." line.long 0xC "HDR_LOG_3_OFF,Header Log Register 3. For a description of this standard PCIe register. see the PCI Express Specification." hexmask.long.byte 0xC 24.--31. 1. "FOURTH_DWORD_FOURTH_BYTE,Byte 3 of Header log register of Fourth 32 bit Data Word. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." hexmask.long.byte 0xC 16.--23. 1. "FOURTH_DWORD_THIRD_BYTE,Byte 2 of Header log register of Fourth 32 bit Data Word. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." hexmask.long.byte 0xC 8.--15. 1. "FOURTH_DWORD_SECOND_BYTE,Byte 1 of Header log register of Fourth 32 bit Data Word. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." newline hexmask.long.byte 0xC 0.--7. 1. "FOURTH_DWORD_FIRST_BYTE,Byte 0 of Header log register of Fourth 32 bit Data Word. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." group.long (0x2C+0x100)++0x7 line.long 0x0 "ROOT_ERR_CMD_OFF,Root Error Command Register. For a description of this standard PCIe register. see the PCI Express Specification." hexmask.long 0x0 3.--31. 1. "RSVDP_3,Reserved for future use." bitfld.long 0x0 2. "FATAL_ERR_REPORTING_EN,Fatal Error Reporting Enable. For a description of this standard PCIe register field see the PCI Express Specification." "0,1" bitfld.long 0x0 1. "NON_FATAL_ERR_REPORTING_EN,Non-Fatal Error Reporting Enable. For a description of this standard PCIe register field see the PCI Express Specification." "0,1" newline bitfld.long 0x0 0. "CORR_ERR_REPORTING_EN,Correctable Error Reporting Enable. For a description of this standard PCIe register field see the PCI Express Specification." "0,1" line.long 0x4 "ROOT_ERR_STATUS_OFF,Root Error Status Register. For a description of this standard PCIe register. see the PCI Express Specification." hexmask.long.byte 0x4 27.--31. 1. "ADV_ERR_INT_MSG_NUM,Advanced Error Interrupt Message Number. For a description of this standard PCIe register field see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN.." hexmask.long.tbyte 0x4 7.--26. 1. "RSVDP_7,Reserved for future use." bitfld.long 0x4 6. "FATAL_ERR_MSG_RX,One or more Fatal Error Messages Received. For a description of this standard PCIe register field see the PCI Express Specification." "0,1" newline bitfld.long 0x4 5. "NON_FATAL_ERR_MSG_RX,One or more Non-Fatal Error Messages Received. For a description of this standard PCIe register field see the PCI Express Specification." "0,1" bitfld.long 0x4 4. "FIRST_UNCORR_FATAL,First Uncorrectable Error is Fatal. For a description of this standard PCIe register field see the PCI Express Specification." "0,1" bitfld.long 0x4 3. "MUL_ERR_FATAL_NON_FATAL_RX,Multiple Fatal or Non-Fatal Errors Received. For a description of this standard PCIe register field see the PCI Express Specification." "0,1" newline bitfld.long 0x4 2. "ERR_FATAL_NON_FATAL_RX,Fatal or Non-Fatal Error Received. For a description of this standard PCIe register field see the PCI Express Specification." "0,1" bitfld.long 0x4 1. "MUL_ERR_COR_RX,Multiple Correctable Errors Received. For a description of this standard PCIe register field see the PCI Express Specification." "0,1" bitfld.long 0x4 0. "ERR_COR_RX,Correctable Error Received. For a description of this standard PCIe register field see the PCI Express Specification." "0,1" rgroup.long (0x34+0x100)++0x13 line.long 0x0 "ERR_SRC_ID_OFF,Error Source Identification Register. For a description of this standard PCIe register. see the PCI Express Specification." hexmask.long.word 0x0 16.--31. 1. "ERR_FATAL_NON_FATAL_SOURCE_ID,Source of Fatal/Non-Fatal Error. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." hexmask.long.word 0x0 0.--15. 1. "ERR_COR_SOURCE_ID,Source of Correctable Error. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." line.long 0x4 "TLP_PREFIX_LOG_1_OFF,TLP Prefix Log Register 1. For a description of this standard PCIe register. see the PCI Express Specification." hexmask.long.byte 0x4 24.--31. 1. "CFG_TLP_PFX_LOG_1_FOURTH_BYTE,Byte 3 of Error TLP Prefix Log 1. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." hexmask.long.byte 0x4 16.--23. 1. "CFG_TLP_PFX_LOG_1_THIRD_BYTE,Byte 2 of Error TLP Prefix Log 1. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." hexmask.long.byte 0x4 8.--15. 1. "CFG_TLP_PFX_LOG_1_SECOND_BYTE,Byte 1 of Error TLP Prefix Log 1. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." newline hexmask.long.byte 0x4 0.--7. 1. "CFG_TLP_PFX_LOG_1_FIRST_BYTE,Byte 0 of Error TLP Prefix Log 1. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." line.long 0x8 "TLP_PREFIX_LOG_2_OFF,TLP Prefix Log Register 2. For a description of this standard PCIe register. see the PCI Express Specification." hexmask.long.byte 0x8 24.--31. 1. "CFG_TLP_PFX_LOG_2_FOURTH_BYTE,Byte 3 Error TLP Prefix Log 2. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." hexmask.long.byte 0x8 16.--23. 1. "CFG_TLP_PFX_LOG_2_THIRD_BYTE,Byte 2 Error TLP Prefix Log 2. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." hexmask.long.byte 0x8 8.--15. 1. "CFG_TLP_PFX_LOG_2_SECOND_BYTE,Byte 1 Error TLP Prefix Log 2. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." newline hexmask.long.byte 0x8 0.--7. 1. "CFG_TLP_PFX_LOG_2_FIRST_BYTE,Byte 0 Error TLP Prefix Log 2. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." line.long 0xC "TLP_PREFIX_LOG_3_OFF,TLP Prefix Log Register 3. For a description of this standard PCIe register. see the PCI Express Specification." hexmask.long.byte 0xC 24.--31. 1. "CFG_TLP_PFX_LOG_3_FOURTH_BYTE,Byte 3 Error TLP Prefix Log 3. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." hexmask.long.byte 0xC 16.--23. 1. "CFG_TLP_PFX_LOG_3_THIRD_BYTE,Byte 2 Error TLP Prefix Log 3. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." hexmask.long.byte 0xC 8.--15. 1. "CFG_TLP_PFX_LOG_3_SECOND_BYTE,Byte 1 Error TLP Prefix Log 3. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." newline hexmask.long.byte 0xC 0.--7. 1. "CFG_TLP_PFX_LOG_3_FIRST_BYTE,Byte 0 Error TLP Prefix Log 3. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." line.long 0x10 "TLP_PREFIX_LOG_4_OFF,TLP Prefix Log Register 4. For a description of this standard PCIe register. see the PCI Express Specification." hexmask.long.byte 0x10 24.--31. 1. "CFG_TLP_PFX_LOG_4_FOURTH_BYTE,Byte 3 Error TLP Prefix Log 4. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." hexmask.long.byte 0x10 16.--23. 1. "CFG_TLP_PFX_LOG_4_THIRD_BYTE,Byte 2 Error TLP Prefix Log 4. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." hexmask.long.byte 0x10 8.--15. 1. "CFG_TLP_PFX_LOG_4_SECOND_BYTE,Byte 1 Error TLP Prefix Log 4. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." newline hexmask.long.byte 0x10 0.--7. 1. "CFG_TLP_PFX_LOG_4_FIRST_BYTE,Byte 0 Error TLP Prefix Log 4. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." tree.end tree "PF0_MSI_CAP (PF MSI Capability Structure)" group.long (0x0+0x50)++0x13 line.long 0x0 "PCI_MSI_CAP_ID_NEXT_CTRL_REG,MSI Capability Header and Message Control Register." hexmask.long.byte 0x0 27.--31. 1. "RSVDP_27,Reserved for future use." bitfld.long 0x0 26. "PCI_MSI_EXT_DATA_EN,Extended Message Data Enable. - If set the function is enabled to provide Extended Message Data. - If clear the function is not enabled to provide Extended Message Data. Note: The access attributes of this field are as follows: -.." "0,1" bitfld.long 0x0 25. "PCI_MSI_EXT_DATA_CAP,Extended Message Data Capable. - If set the function is capable of providing Extended Message Data. - If clear the function does not support providing Extended Message Data. Note: The access attributes of this field are as follows:.." "0,1" newline rbitfld.long 0x0 24. "PCI_PVM_SUPPORT,Per-Vector Masking Capable. - If set the function supports MSI Per-Vector Masking. - If clear the function does not support MSI Per-Vector Masking. This bit must be set if the function is a PF or VF within an SR-IOV Device." "0,1" bitfld.long 0x0 23. "PCI_MSI_64_BIT_ADDR_CAP,64 bit address capable. - If set the function is capable of sending a 64-bit message address. - If clear the function is not capable of sending a 64-bit message address. This bit must be set if the function is a PCI Express.." "0,1" bitfld.long 0x0 20.--22. "PCI_MSI_MULTIPLE_MSG_EN,Multiple Message Enable. Software writes to this field to indicate the number of allocated vectors (equal to or less than the number of requested vectors). The number of allocated vectors is aligned to a power of two. If a.." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 17.--19. "PCI_MSI_MULTIPLE_MSG_CAP,Multiple Message Capable. System software reads this field to determine the number of requested vectors. The number of requested vectors must be aligned to a power of two (if a function requires three vectors it requests four by.." "0,1,2,3,4,5,6,7" bitfld.long 0x0 16. "PCI_MSI_ENABLE,MSI Enable. - If set and the MSI-X Enable bit in the MSI-X Message Control register is clear the function is permitted to use MSI to request service and is prohibited from using INTx interrupts. System configuration software sets this bit.." "0,1" hexmask.long.byte 0x0 8.--15. 1. "PCI_MSI_CAP_NEXT_OFFSET,Next Capability Pointer. This field contains the offset to the next PCI Capability structure or 00h if no other items exist in the linked list of Capabilities. Note: The access attributes of this field are as follows: - Wire: No.." newline hexmask.long.byte 0x0 0.--7. 1. "PCI_MSI_CAP_ID,Capability ID. Indicates the MSI Capability structure. This field returns a Capability ID of 05h indicating that this is an MSI Capability structure." line.long 0x4 "MSI_CAP_OFF_04H_REG,Message Address Register for MSI (Offset 04h)." hexmask.long 0x4 2.--31. 1. "PCI_MSI_CAP_OFF_04H,Message Address - System-specified message address. If the Message Enable bit (bit 16 of the PCI_MSI_CAP_ID_NEXT_CTRL_REG register) is set the contents of this field specify the DWORD-aligned address (Address[31:02]) for the MSI.." rbitfld.long 0x4 0.--1. "RSVDP_0,Reserved for future use." "0,1,2,3" line.long 0x8 "MSI_CAP_OFF_08H_REG,For a function that supports a 32-bit message address. - bits[31:16] of this register represent the Extended Message Data. and - bits[15:0] of this register represent the Message Data For a function that supports a 64-bit message.." hexmask.long.word 0x8 16.--31. 1. "PCI_MSI_CAP_OFF_0AH,For a function that supports a 32-bit message address this field contains Extended Message Data (System-specified message data). For the MSI Capability structures without per-vector masking it must be implemented if the Extended.." hexmask.long.word 0x8 0.--15. 1. "PCI_MSI_CAP_OFF_08H,For a function that supports a 32-bit message address this field contains Message Data (System-specified message data). If the Message Enable bit (bit 16 of the PCI_MSI_CAP_ID_NEXT_CTRL_REG) is set the function sends a DWORD Memory.." line.long 0xC "MSI_CAP_OFF_0CH_REG,For a function that supports a 32-bit message address. this register contains the Mask Bits when the Per-Vector Masking Capable bit (bit 24 of PCI_MSI_CAP_ID_NEXT_CTRL_REG) is set. For a function that supports a 64-bit message.." hexmask.long.word 0xC 16.--31. 1. "PCI_MSI_CAP_OFF_0EH,For a function that supports a 32-bit message address this field contains the upper Mask Bits when the Per Vector Masking Capable bit (PCI_MSI_CAP_ID_NEXT_CTRL_REG.PCI_PVM_SUPPORT) is set. For a function that supports a 64-bit.." hexmask.long.word 0xC 0.--15. 1. "PCI_MSI_CAP_OFF_0CH,For a function that supports a 32-bit message address this field contains the lower Mask Bits when the Per Vector Masking Capable bit (PCI_MSI_CAP_ID_NEXT_CTRL_REG.PCI_PVM_SUPPORT) is set. For a function that supports a 64-bit.." line.long 0x10 "MSI_CAP_OFF_10H_REG,For a function that supports a 32-bit message address. this register contains the Pending Bits when the Per-Vector Masking Capable bit (bit 24 of PCI_MSI_CAP_ID_NEXT_CTRL_REG) is set. For a function that supports a 64-bit message.." hexmask.long 0x10 0.--31. 1. "PCI_MSI_CAP_OFF_10H,Used for MSI when the Per Vector Masking Capable bit (PCI_MSI_CAP_ID_NEXT_CTRL_REG.PCI_PVM_SUPPORT) is set. For 32-bit contains Pending Bits. For 64-bit contains Mask Bits. For a description of this standard PCIe register field see.." rgroup.long (0x14+0x50)++0x3 line.long 0x0 "MSI_CAP_OFF_14H_REG,Pending Bits Register for MSI. This register is used for a function that supports a 64-bit message address when the Per-Vector Masking Capable bit (bit 24 of PCI_MSI_CAP_ID_NEXT_CTRL_REG) is set." hexmask.long 0x0 0.--31. 1. "PCI_MSI_CAP_OFF_14H,Pending Bits. For each pending bit that is set the function has a pending associated message." tree.end tree "PF0_MSIX_CAP (PF MSI-X Capability Structure)" group.long (0x0+0xB0)++0xB line.long 0x0 "PCI_MSIX_CAP_ID_NEXT_CTRL_REG,MSI-X Capability ID. Next Pointer. Control Registers. For a description of this standard PCIe register. see the PCI Express Base Specification." bitfld.long 0x0 31. "PCI_MSIX_ENABLE,MSI-X Enable. For a description of this standard PCIe register field see the PCI Express Base Specification." "0,1" bitfld.long 0x0 30. "PCI_MSIX_FUNCTION_MASK,Function Mask. For a description of this standard PCIe register field see the PCI Express Base Specification. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" "0,1" rbitfld.long 0x0 27.--29. "RSVDP_27,Reserved for future use." "0,1,2,3,4,5,6,7" newline hexmask.long.word 0x0 16.--26. 1. "PCI_MSIX_TABLE_SIZE,MSI-X Table Size. For a description of this standard PCIe register field see the PCI Express Base Specification. SRIOV Note: All VFs in a single PF have the same value for 'MSI-X Table Size' (PCI_MSIX_TABLE_SIZE field in.." hexmask.long.byte 0x0 8.--15. 1. "PCI_MSIX_CAP_NEXT_OFFSET,MSI-X Next Capability Pointer. For a description of this standard PCIe register field see the PCI Express Base Specification. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN.." hexmask.long.byte 0x0 0.--7. 1. "PCI_MSIX_CAP_ID,MSI-X Capability ID. For a description of this standard PCIe register field see the PCI Express Base Specification." line.long 0x4 "MSIX_TABLE_OFFSET_REG,MSI-X Table Offset and BIR Register. For a description of this standard PCIe register. see the PCI Express Base Specification." hexmask.long 0x4 3.--31. 1. "PCI_MSIX_TABLE_OFFSET,MSI-X Table Offset. For a description of this standard PCIe register field see the PCI Express Base Specification. SRIOV Note: All VFs in a single PF have the same value for 'MSI-X Table Offset' (PCI_MSIX_TABLE_OFFSET field in.." bitfld.long 0x4 0.--2. "PCI_MSIX_BIR,MSI-X Table BAR Indicator Register Field. For a description of this standard PCIe register field see the PCI Express Base Specification. SRIOV Note: All VFs in a single PF have the same value for 'MSI-X Table BAR Indicator Register'.." "0,1,2,3,4,5,6,7" line.long 0x8 "MSIX_PBA_OFFSET_REG,MSI-X PBA Offset and BIR Register. For a description of this standard PCIe register. see the PCI Express Base Specification." hexmask.long 0x8 3.--31. 1. "PCI_MSIX_PBA_OFFSET,MSI-X PBA Offset. For a description of this standard PCIe register field see the PCI Express Base Specification. SRIOV Note: All VFs in a single PF have the same value for 'MSI-X PBA Offset' (PCI_MSIX_PBA_OFFSET field in.." bitfld.long 0x8 0.--2. "PCI_MSIX_PBA_BIR,MSI-X PBA BIR. For a description of this standard PCIe register field see the PCI Express Base Specification. SRIOV Note: All VFs in a single PF have the same value for 'MSI-X PBA BIR' (PCI_MSIX_PBA_BIR field in.." "0,1,2,3,4,5,6,7" tree.end tree "PF0_MSIX_CAP_DBI2 (DBI2 Shadow Block: PF MSI-X Capability Structure)" rgroup.long (0x0+0x10B0)++0x3 line.long 0x0 "SHADOW_PCI_MSIX_CAP_ID_NEXT_CTRL_REG,MSI-X Capability ID. Next Pointer. Control Registers. For a description of this standard PCIe register. see the PCI Express Base Specification." hexmask.long.byte 0x0 27.--31. 1. "RSVDP_27,Reserved for future use." hexmask.long.word 0x0 16.--26. 1. "PCI_MSIX_TABLE_SIZE,MSI-X Table Size in the shadow register. Note: The access attributes of this field are as follows: - Wire: No access - Dbi: No access - Dbi2: if (DBI_RO_WR_EN == 1) then R/W else R Note: This register field is sticky." hexmask.long.word 0x0 0.--15. 1. "RSVDP_0,Reserved for future use." group.long 0x4++0x7 line.long 0x0 "SHADOW_MSIX_TABLE_OFFSET_REG,MSI-X Table Offset and BIR Register. For a description of this standard PCIe register. see the PCI Express Base Specification." hexmask.long 0x0 3.--31. 1. "PCI_MSIX_TABLE_OFFSET,MSI-X Table Offset. For a description of this standard PCIe register field see the PCI Express Base Specification. Note: The access attributes of this field are as follows: - Wire: No access - Dbi: No access - Dbi2: if.." bitfld.long 0x0 0.--2. "PCI_MSIX_BIR,MSI-X Table BAR Indicator Register Field. For a description of this standard PCIe register field see the PCI Express Base Specification. Note: The access attributes of this field are as follows: - Wire: No access - Dbi: No access - Dbi2: if.." "?,?,if,?,?,?,?,?" line.long 0x4 "SHADOW_MSIX_PBA_OFFSET_REG,MSI-X PBA Offset and BIR Register. For a description of this standard PCIe register. see the PCI Express Base Specification." hexmask.long 0x4 3.--31. 1. "PCI_MSIX_PBA_OFFSET,MSI-X PBA Offset. For a description of this standard PCIe register field see the PCI Express Base Specification. Note: The access attributes of this field are as follows: - Wire: No access - Dbi: No access - Dbi2: if (DBI_RO_WR_EN ==.." bitfld.long 0x4 0.--2. "PCI_MSIX_PBA_BIR,MSI-X PBA BIR. For a description of this standard PCIe register field see the PCI Express Base Specification. Note: The access attributes of this field are as follows: - Wire: No access - Dbi: No access - Dbi2: if (DBI_RO_WR_EN == 1 &&.." "?,?,if,?,?,?,?,?" tree.end tree "PF0_DMA_CAP (DMA Port Logic Structure)" group.long (0x0+0xC8000)++0x3 line.long 0x0 "DMA_CTRL_DATA_ARB_PRIOR_OFF,DMA Arbitration Scheme for TRGT1 Interface. This register is used to control traffic priorities among various sources that are delivered to your application through TRGT1 where 0x0 represents the highest priority. - Non-DMA Rx.." hexmask.long.tbyte 0x0 12.--31. 1. "RSVDP_12,Reserved for future use." bitfld.long 0x0 9.--11. "RDBUFF_TRGT_WEIGHT,DMA Read Channel MWr Requests. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 6.--8. "RD_CTRL_TRGT_WEIGHT,DMA Read Channel MRd Requests. For LL element/descriptor access. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" "0,1,2,3,4,5,6,7" bitfld.long 0x0 3.--5. "WR_CTRL_TRGT_WEIGHT,DMA Write Channel MRd Requests. For DMA data requests and LL element/descriptor access. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 0.--2. "RTRGT1_WEIGHT,Non-DMA Rx Requests. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" "0,1,2,3,4,5,6,7" group.long (0x8+0xC8000)++0xB line.long 0x0 "DMA_CTRL_OFF,DMA Number of Channels Register." hexmask.long.byte 0x0 26.--31. 1. "RSVDP_26,Reserved for future use." bitfld.long 0x0 25. "DIS_C2W_CACHE_RD,Disable DMA Read Channels 'completion to memory write' context cache pre-fetch function. Note: For internal debugging only. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" "0,1" newline bitfld.long 0x0 24. "DIS_C2W_CACHE_WR,Disable DMA Write Channels 'completion to memory write' context cache pre-fetch function. Note: For internal debugging only. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" "0,1" hexmask.long.byte 0x0 20.--23. 1. "RSVDP_20,Reserved for future use." newline hexmask.long.byte 0x0 16.--19. 1. "NUM_DMA_RD_CHAN,Number of Read Channels. You can read this register to determine the number of read channels the DMA controller has been configured to support." hexmask.long.word 0x0 4.--15. 1. "RSVDP_4,Reserved for future use." newline hexmask.long.byte 0x0 0.--3. 1. "NUM_DMA_WR_CHAN,Number of Write Channels. You can read this register to determine the number of write channels the DMA controller has been configured to support." line.long 0x4 "DMA_WRITE_ENGINE_EN_OFF,DMA Write Engine Enable Register." hexmask.long.byte 0x4 24.--31. 1. "RSVDP_24,Reserved for future use." bitfld.long 0x4 23. "DMA_WRITE_ENGINE_EN_HSHAKE_CH7,Enable Handshake for DMA Write Engine Channel 7. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" "0,1" newline bitfld.long 0x4 22. "DMA_WRITE_ENGINE_EN_HSHAKE_CH6,Enable Handshake for DMA Write Engine Channel 6. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" "0,1" bitfld.long 0x4 21. "DMA_WRITE_ENGINE_EN_HSHAKE_CH5,Enable Handshake for DMA Write Engine Channel 5. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" "0,1" newline bitfld.long 0x4 20. "DMA_WRITE_ENGINE_EN_HSHAKE_CH4,Enable Handshake for DMA Write Engine Channel 4. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" "0,1" bitfld.long 0x4 19. "DMA_WRITE_ENGINE_EN_HSHAKE_CH3,Enable Handshake for DMA Write Engine Channel 3. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" "0,1" newline bitfld.long 0x4 18. "DMA_WRITE_ENGINE_EN_HSHAKE_CH2,Enable Handshake for DMA Write Engine Channel 2. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" "0,1" bitfld.long 0x4 17. "DMA_WRITE_ENGINE_EN_HSHAKE_CH1,Enable Handshake for DMA Write Engine Channel 1. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" "0,1" newline bitfld.long 0x4 16. "DMA_WRITE_ENGINE_EN_HSHAKE_CH0,Enable Handshake for DMA Write Engine Channel 0. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" "0,1" hexmask.long.word 0x4 1.--15. 1. "RSVDP_1,Reserved for future use." newline bitfld.long 0x4 0. "DMA_WRITE_ENGINE,DMA Write Engine Enable. - 1: Enable - 0: Disable (Soft Reset) For normal operation you must initially set this bit to '1' before any other software setup actions. You do not need to toggle or rewrite to this bit during normal.." "Disable,Enable" line.long 0x8 "DMA_WRITE_DOORBELL_OFF,DMA Write Doorbell Register." bitfld.long 0x8 31. "WR_STOP,Stop. Set in conjunction with the Doorbell Number field. The DMA write channel stops issuing requests sets the channel status to 'Stopped' and asserts the 'Abort' interrupt if it is enabled. Before setting the Stop bit you must read the.." "0,1" hexmask.long 0x8 3.--30. 1. "RSVDP_3,Reserved for future use." newline bitfld.long 0x8 0.--2. "WR_DOORBELL_NUM,Doorbell Number. You must write the channel number to this register to start the DMA write transfer for that channel. The DMA detects a write to this register field even if the value of this field does not change. You do not need to.." "0,1,2,3,4,5,6,7" group.long (0x18+0xC8000)++0x7 line.long 0x0 "DMA_WRITE_CHANNEL_ARB_WEIGHT_LOW_OFF,DMA Write Engine Channel Arbitration Weight Low Register. The 5-bit channel weight (for write channels 0-3) specifies the maximum number of TLP requests that the DMA can issue for that channel before it must return to.." hexmask.long.word 0x0 20.--31. 1. "RSVDP_20,Reserved for future use." hexmask.long.byte 0x0 15.--19. 1. "WRITE_CHANNEL3_WEIGHT,Channel 3 Weight. The weight is initialized by software before ringing the doorbell. The value is used by the channel weighted round robin arbiter to select the next channel read request. A value of '0' means that one TLP is issued.." newline hexmask.long.byte 0x0 10.--14. 1. "WRITE_CHANNEL2_WEIGHT,Channel 2 Weight. The weight is initialized by software before ringing the doorbell. The value is used by the channel weighted round robin arbiter to select the next channel read request. A value of '0' means that one TLP is issued.." hexmask.long.byte 0x0 5.--9. 1. "WRITE_CHANNEL1_WEIGHT,Channel 1 Weight. The weight is initialized by software before ringing the doorbell. The value is used by the channel weighted round robin arbiter to select the next channel read request. A value of '0' means that one TLP is issued.." newline hexmask.long.byte 0x0 0.--4. 1. "WRITE_CHANNEL0_WEIGHT,Channel 0 Weight. The weight is initialized by software before ringing the doorbell. The value is used by the channel weighted round robin arbiter to select the next channel read request. A value of '0' means that one TLP is issued.." line.long 0x4 "DMA_WRITE_CHANNEL_ARB_WEIGHT_HIGH_OFF,DMA Write Engine Channel Arbitration Weight High Register. The 5-bit channel weight (for write channels 4-7) specifies the maximum number of TLP requests that the DMA can issue for that channel before it must return.." hexmask.long.word 0x4 20.--31. 1. "RSVDP_20,Reserved for future use." hexmask.long.byte 0x4 15.--19. 1. "WRITE_CHANNEL7_WEIGHT,Channel 7 Weight. The weight is initialized by software before ringing the doorbell. The value is used by the channel weighted round robin arbiter to select the next channel read request. A value of '0' means that one TLP is issued.." newline hexmask.long.byte 0x4 10.--14. 1. "WRITE_CHANNEL6_WEIGHT,Channel 6 Weight. The weight is initialized by software before ringing the doorbell. The value is used by the channel weighted round robin arbiter to select the next channel read request. A value of '0' means that one TLP is issued.." hexmask.long.byte 0x4 5.--9. 1. "WRITE_CHANNEL5_WEIGHT,Channel 5 Weight. The weight is initialized by software before ringing the doorbell. The value is used by the channel weighted round robin arbiter to select the next channel read request. A value of '0' means that one TLP is issued.." newline hexmask.long.byte 0x4 0.--4. 1. "WRITE_CHANNEL4_WEIGHT,Channel 4 Weight. The weight is initialized by software before ringing the doorbell. The value is used by the channel weighted round robin arbiter to select the next channel read request. A value of '0' means that one TLP is issued.." group.long (0x2C+0xC8000)++0x7 line.long 0x0 "DMA_READ_ENGINE_EN_OFF,DMA Read Engine Enable Register." hexmask.long.byte 0x0 24.--31. 1. "RSVDP_24,Reserved for future use." bitfld.long 0x0 23. "DMA_READ_ENGINE_EN_HSHAKE_CH7,Enable Handshake for DMA Read Engine Channel 7. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" "0,1" newline bitfld.long 0x0 22. "DMA_READ_ENGINE_EN_HSHAKE_CH6,Enable Handshake for DMA Read Engine Channel 6. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" "0,1" bitfld.long 0x0 21. "DMA_READ_ENGINE_EN_HSHAKE_CH5,Enable Handshake for DMA Read Engine Channel 5. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" "0,1" newline bitfld.long 0x0 20. "DMA_READ_ENGINE_EN_HSHAKE_CH4,Enable Handshake for DMA Read Engine Channel 4. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" "0,1" bitfld.long 0x0 19. "DMA_READ_ENGINE_EN_HSHAKE_CH3,Enable Handshake for DMA Read Engine Channel 3. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" "0,1" newline bitfld.long 0x0 18. "DMA_READ_ENGINE_EN_HSHAKE_CH2,Enable Handshake for DMA Read Engine Channel 2. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" "0,1" bitfld.long 0x0 17. "DMA_READ_ENGINE_EN_HSHAKE_CH1,Enable Handshake for DMA Read Engine Channel 1. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" "0,1" newline bitfld.long 0x0 16. "DMA_READ_ENGINE_EN_HSHAKE_CH0,Enable Handshake for DMA Read Engine Channel 0. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" "0,1" hexmask.long.word 0x0 1.--15. 1. "RSVDP_1,Reserved for future use." newline bitfld.long 0x0 0. "DMA_READ_ENGINE,DMA Read Engine Enable. - 1: Enable - 0: Disable (Soft Reset) For normal operation you must initially set this bit to '1' before any other software setup actions. You do not need to toggle or rewrite to this bit during normal operation." "Disable,Enable" line.long 0x4 "DMA_READ_DOORBELL_OFF,DMA Read Doorbell Register." bitfld.long 0x4 31. "RD_STOP,Stop. Set in conjunction with the Doorbell Number field. The DMA read channel stops issuing requests sets the channel status to 'Stopped' and asserts the 'Abort' interrupt if it is enabled. Before setting the Stop bit you must read the channel.." "0,1" hexmask.long 0x4 3.--30. 1. "RSVDP_3,Reserved for future use." newline bitfld.long 0x4 0.--2. "RD_DOORBELL_NUM,Doorbell Number. You must write 0x0 to this register to start the DMA read transfer for that channel. The DMA detects a write to this register field even if the value of this field does not change. The range of this field is 0x0 to 0x7.." "0,1,2,3,4,5,6,7" group.long (0x38+0xC8000)++0x7 line.long 0x0 "DMA_READ_CHANNEL_ARB_WEIGHT_LOW_OFF,DMA Read Engine Channel Arbitration Weight Low Register. The 5-bit channel weight (for read channels 0-3) specifies the maximum number of TLP requests that the DMA can issue for that channel before it must return to.." hexmask.long.word 0x0 20.--31. 1. "RSVDP_20,Reserved for future use." hexmask.long.byte 0x0 15.--19. 1. "READ_CHANNEL3_WEIGHT,Channel 3 Weight. The weight is initialized by software before ringing the doorbell. The value is used by the channel weighted round robin arbiter to select the next channel read request. Note: The access attributes of this field are.." newline hexmask.long.byte 0x0 10.--14. 1. "READ_CHANNEL2_WEIGHT,Channel 2 Weight. The weight is initialized by software before ringing the doorbell. The value is used by the channel weighted round robin arbiter to select the next channel read request. Note: The access attributes of this field are.." hexmask.long.byte 0x0 5.--9. 1. "READ_CHANNEL1_WEIGHT,Channel 1 Weight. The weight is initialized by software before ringing the doorbell. The value is used by the channel weighted round robin arbiter to select the next channel read request. Note: The access attributes of this field are.." newline hexmask.long.byte 0x0 0.--4. 1. "READ_CHANNEL0_WEIGHT,Channel 0 Weight. The weight is initialized by software before ringing the doorbell. The value is used by the channel weighted round robin arbiter to select the next channel read request. Note: The access attributes of this field are.." line.long 0x4 "DMA_READ_CHANNEL_ARB_WEIGHT_HIGH_OFF,DMA Read Engine Channel Arbitration Weight High Register. The 5-bit channel weight (for read channels 4-7) specifies the maximum number of TLP requests that the DMA can issue for that channel before it must return to.." hexmask.long.word 0x4 20.--31. 1. "RSVDP_20,Reserved for future use." hexmask.long.byte 0x4 15.--19. 1. "READ_CHANNEL7_WEIGHT,Channel 7 Weight. The weight is initialized by software before ringing the doorbell. The value is used by the channel weighted round robin arbiter to select the next channel read request. Note: The access attributes of this field are.." newline hexmask.long.byte 0x4 10.--14. 1. "READ_CHANNEL6_WEIGHT,Channel 6 Weight. The weight is initialized by software before ringing the doorbell. The value is used by the channel weighted round robin arbiter to select the next channel read request. Note: The access attributes of this field are.." hexmask.long.byte 0x4 5.--9. 1. "READ_CHANNEL5_WEIGHT,Channel 5 Weight. The weight is initialized by software before ringing the doorbell. The value is used by the channel weighted round robin arbiter to select the next channel read request. Note: The access attributes of this field are.." newline hexmask.long.byte 0x4 0.--4. 1. "READ_CHANNEL4_WEIGHT,Channel 4 Weight. The weight is initialized by software before ringing the doorbell. The value is used by the channel weighted round robin arbiter to select the next channel read request. Note: The access attributes of this field are.." group.long (0x4C+0xC8000)++0x3 line.long 0x0 "DMA_WRITE_INT_STATUS_OFF,DMA Write Interrupt Status Register." hexmask.long.byte 0x0 24.--31. 1. "RSVDP_24,Reserved for future use." hexmask.long.byte 0x0 16.--23. 1. "WR_ABORT_INT_STATUS,Abort Interrupt Status. The DMA write channel has detected an error or you manually stopped the transfer as described in 'Error Handling Assistance by Remote Software'. Each bit corresponds to a DMA channel. Bit [0] corresponds to.." newline hexmask.long.byte 0x0 8.--15. 1. "RSVDP_8,Reserved for future use." hexmask.long.byte 0x0 0.--7. 1. "WR_DONE_INT_STATUS,Done Interrupt Status. The DMA write channel has successfully completed the DMA transfer. For more details see 'Interrupts and Error Handling'. Each bit corresponds to a DMA channel. Bit [0] corresponds to channel 0. - Enabling: For.." group.long (0x54+0xC8000)++0x7 line.long 0x0 "DMA_WRITE_INT_MASK_OFF,DMA Write Interrupt Mask Register." hexmask.long.byte 0x0 24.--31. 1. "RSVDP_24,Reserved for future use." hexmask.long.byte 0x0 16.--23. 1. "WR_ABORT_INT_MASK,Abort Interrupt Mask. Prevents the Abort interrupt status field in the DMA write interrupt status register from asserting the edma_int output. Each bit corresponds to a DMA channel. Bit [0] corresponds to channel 0. Note: The access.." newline hexmask.long.byte 0x0 8.--15. 1. "RSVDP_8,Reserved for future use." hexmask.long.byte 0x0 0.--7. 1. "WR_DONE_INT_MASK,Done Interrupt Mask. Prevents the Done interrupt status field in the DMA write interrupt status register from asserting the edma_int output. Each bit corresponds to a DMA channel. Bit [0] corresponds to channel 0. Note: The access.." line.long 0x4 "DMA_WRITE_INT_CLEAR_OFF,DMA Write Interrupt Clear Register." hexmask.long.byte 0x4 24.--31. 1. "RSVDP_24,Reserved for future use." hexmask.long.byte 0x4 16.--23. 1. "WR_ABORT_INT_CLEAR,Abort Interrupt Clear. You must write a 1'b1 to clear the corresponding bit in the Abort interrupt status field of the DMA write interrupt status register. Each bit corresponds to a DMA channel. Bit [0] corresponds to channel 0. Note:.." newline hexmask.long.byte 0x4 8.--15. 1. "RSVDP_8,Reserved for future use." hexmask.long.byte 0x4 0.--7. 1. "WR_DONE_INT_CLEAR,Done Interrupt Clear. You must write a 1'b1 to clear the corresponding bit in the Done interrupt status field of the DMA write interrupt status register. Each bit corresponds to a DMA channel. Bit [0] corresponds to channel 0. Note:.." rgroup.long (0x5C+0xC8000)++0x3 line.long 0x0 "DMA_WRITE_ERR_STATUS_OFF,DMA Write Error Status Register" hexmask.long.byte 0x0 24.--31. 1. "RSVDP_24,Reserved for future use." hexmask.long.byte 0x0 16.--23. 1. "LINKLIST_ELEMENT_FETCH_ERR_DETECT,Linked List Element Fetch Error Detected. The DMA write channel has received an error response from the AXI bus (or TRGT1 interface when the AXI Bridge is not used) while reading a linked list element from local memory." newline hexmask.long.byte 0x0 8.--15. 1. "RSVDP_8,Reserved for future use." hexmask.long.byte 0x0 0.--7. 1. "APP_READ_ERR_DETECT,Application Read Error Detected. The DMA write channel has received an error response from the AXI bus (or TRGT1 interface when the AXI Bridge is not used) while reading data from it. Each bit corresponds to a DMA channel. Bit [0].." group.long (0x60+0xC8000)++0x1F line.long 0x0 "DMA_WRITE_DONE_IMWR_LOW_OFF,DMA Write Done IMWr Address Low Register." hexmask.long 0x0 0.--31. 1. "DMA_WRITE_DONE_LOW_REG,The DMA uses this field to generate bits [31:0] of the address field for the Done IMWr TLP. Bits [1:0] must be '00' as this address must be dword aligned. Note: The access attributes of this field are as follows: - Wire: No access." line.long 0x4 "DMA_WRITE_DONE_IMWR_HIGH_OFF,DMA Write Done IMWr Interrupt Address High Register." hexmask.long 0x4 0.--31. 1. "DMA_WRITE_DONE_HIGH_REG,The DMA uses this field to generate bits [63:32] of the address field for the Done IMWr TLP. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" line.long 0x8 "DMA_WRITE_ABORT_IMWR_LOW_OFF,DMA Write Abort IMWr Address Low Register." hexmask.long 0x8 0.--31. 1. "DMA_WRITE_ABORT_LOW_REG,The DMA uses this field to generate bits [31:0] of the address field for the Abort IMWr TLP it generates. Bits [1:0] must be '00' as this address must be dword aligned. Note: The access attributes of this field are as follows: -.." line.long 0xC "DMA_WRITE_ABORT_IMWR_HIGH_OFF,DMA Write Abort IMWr Address High Register." hexmask.long 0xC 0.--31. 1. "DMA_WRITE_ABORT_HIGH_REG,The DMA uses this field to generate bits [63:32] of the address field for the Abort IMWr TLP. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" line.long 0x10 "DMA_WRITE_CH01_IMWR_DATA_OFF,DMA Write Channel 1 and 0 IMWr Data Register." hexmask.long.word 0x10 16.--31. 1. "WR_CHANNEL_1_DATA,The DMA uses this field to generate the data field for the Done or Abort IMWr TLPs it generates for write channel 1. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" hexmask.long.word 0x10 0.--15. 1. "WR_CHANNEL_0_DATA,The DMA uses this field to generate the data field for the Done or Abort IMWr TLPs it generates for write channel 0. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" line.long 0x14 "DMA_WRITE_CH23_IMWR_DATA_OFF,DMA Write Channel 3 and 2 IMWr Data Register." hexmask.long.word 0x14 16.--31. 1. "WR_CHANNEL_3_DATA,The DMA uses this field to generate the data field for the Done or Abort IMWr TLPs it generates for write channel 3. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" hexmask.long.word 0x14 0.--15. 1. "WR_CHANNEL_2_DATA,The DMA uses this field to generate the data field for the Done or Abort IMWr TLPs it generates for write channel 2. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" line.long 0x18 "DMA_WRITE_CH45_IMWR_DATA_OFF,DMA Write Channel 5 and 4 IMWr Data Register." hexmask.long.word 0x18 16.--31. 1. "WR_CHANNEL_5_DATA,The DMA uses this field to generate the data field for the Done or Abort IMWr TLPs it generates for write channel 5. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" hexmask.long.word 0x18 0.--15. 1. "WR_CHANNEL_4_DATA,The DMA uses this field to generate the data field for the Done or Abort IMWr TLPs it generates for write channel 4. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" line.long 0x1C "DMA_WRITE_CH67_IMWR_DATA_OFF,DMA Write Channel 7 and 6 IMWr Data Register." hexmask.long.word 0x1C 16.--31. 1. "WR_CHANNEL_7_DATA,The DMA uses this field to generate the data field for the Done or Abort IMWr TLPs it generates for write channel 7. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" hexmask.long.word 0x1C 0.--15. 1. "WR_CHANNEL_6_DATA,The DMA uses this field to generate the data field for the Done or Abort IMWr TLPs it generates for write channel 6. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" group.long (0x90+0xC8000)++0x3 line.long 0x0 "DMA_WRITE_LINKED_LIST_ERR_EN_OFF,DMA Write Linked List Error Enable Register. The LIE and RIE bits in the LL element enable the channel 'done' interrupts (local and remote). The LLLAIE and LLRAIE bits enable the channel 'abort' interrupts (local and.." hexmask.long.byte 0x0 24.--31. 1. "RSVDP_24,Reserved for future use." hexmask.long.byte 0x0 16.--23. 1. "WR_CHANNEL_LLLAIE,Write Channel LL Local Abort Interrupt Enable (LLLAIE). You enable the write channel local abort interrupt through this bit. The LIE and RIE bits in the LL element enable the write channel done interrupts. Each bit corresponds to a DMA.." newline hexmask.long.byte 0x0 8.--15. 1. "RSVDP_8,Reserved for future use." hexmask.long.byte 0x0 0.--7. 1. "WR_CHANNEL_LLRAIE,Write Channel LL Remote Abort Interrupt Enable (LLRAIE). You enable the write channel remote abort interrupt through this bit. The LIE and RIE bits in the LL element enable the write channel done interrupts. Each bit corresponds to a.." group.long (0xA0+0xC8000)++0x3 line.long 0x0 "DMA_READ_INT_STATUS_OFF,DMA Read Interrupt Status Register." hexmask.long.byte 0x0 24.--31. 1. "RSVDP_24,Reserved for future use." hexmask.long.byte 0x0 16.--23. 1. "RD_ABORT_INT_STATUS,Abort Interrupt Status. The DMA read channel has detected an error or you manually stopped the transfer as described in 'Stopping the DMA Transfer (Software Stop)'. Each bit corresponds to a DMA channel. Bit [0] corresponds to.." newline hexmask.long.byte 0x0 8.--15. 1. "RSVDP_8,Reserved for future use." hexmask.long.byte 0x0 0.--7. 1. "RD_DONE_INT_STATUS,Done Interrupt Status. The DMA read channel has successfully completed the DMA read transfer. Each bit corresponds to a DMA channel. Bit [0] corresponds to channel 0. - Enabling: For details see 'Interrupts and Error Handling'. -.." group.long (0xA8+0xC8000)++0x7 line.long 0x0 "DMA_READ_INT_MASK_OFF,DMA Read Interrupt Mask Register." hexmask.long.byte 0x0 24.--31. 1. "RSVDP_24,Reserved for future use." hexmask.long.byte 0x0 16.--23. 1. "RD_ABORT_INT_MASK,Abort Interrupt Mask. Prevents the Abort interrupt status field in the DMA read interrupt status register from asserting the edma_int output. Each bit corresponds to a DMA channel. Bit [0] corresponds to channel 0. Note: The access.." newline hexmask.long.byte 0x0 8.--15. 1. "RSVDP_8,Reserved for future use." hexmask.long.byte 0x0 0.--7. 1. "RD_DONE_INT_MASK,Done Interrupt Mask. Prevents the Done interrupt status field in the DMA read interrupt status register from asserting the edma_int output. Each bit corresponds to a DMA channel. Bit [0] corresponds to channel 0. Note: The access.." line.long 0x4 "DMA_READ_INT_CLEAR_OFF,DMA Read Interrupt Clear Register." hexmask.long.byte 0x4 24.--31. 1. "RSVDP_24,Reserved for future use." hexmask.long.byte 0x4 16.--23. 1. "RD_ABORT_INT_CLEAR,Abort Interrupt Clear. You must write a 1'b1 to clear the corresponding bit in the Abort interrupt status field of the DMA read interrupt status register. Each bit corresponds to a DMA channel. Bit [0] corresponds to channel 0. Note:.." newline hexmask.long.byte 0x4 8.--15. 1. "RSVDP_8,Reserved for future use." hexmask.long.byte 0x4 0.--7. 1. "RD_DONE_INT_CLEAR,Done Interrupt Clear. You must write a 1'b1 to clear the corresponding bit in the Done interrupt status field of the DMA read interrupt status register. Each bit corresponds to a DMA channel. Bit [0] corresponds to channel 0. Note:.." rgroup.long (0xB4+0xC8000)++0x7 line.long 0x0 "DMA_READ_ERR_STATUS_LOW_OFF,DMA Read Error Status Low Register." hexmask.long.byte 0x0 24.--31. 1. "RSVDP_24,Reserved for future use." hexmask.long.byte 0x0 16.--23. 1. "LINK_LIST_ELEMENT_FETCH_ERR_DETECT,Linked List Element Fetch Error Detected. - The DMA read channel has received an error response from the AXI bus while reading a linked list element from local memory. Each bit corresponds to a DMA channel. Bit [0].." newline hexmask.long.byte 0x0 8.--15. 1. "RSVDP_8,Reserved for future use." hexmask.long.byte 0x0 0.--7. 1. "APP_WR_ERR_DETECT,Application Write Error Detected. The DMA read channel has received an error response from the AXI bus (or TRGT1 interface when the AXI Bridge is not used) while writing data to it. This error is fatal. You must restart the transfer.." line.long 0x4 "DMA_READ_ERR_STATUS_HIGH_OFF,DMA Read Error Status High Register." hexmask.long.byte 0x4 24.--31. 1. "DATA_POISIONING,Data Poisoning. The DMA read channel has detected data poisoning in the completion from the remote device (in response to the MRd request). The DMA read channel will drop the completion and then be halted. The CX_FLT_MASK_UR_POIS filter.." hexmask.long.byte 0x4 16.--23. 1. "CPL_TIMEOUT,Completion Time Out. The DMA read channel has timed-out while waiting for the remote device to respond to the MRd request or a malformed CplD has been received. For more details see 'Linked List Mode'. Each bit corresponds to a DMA channel." newline hexmask.long.byte 0x4 8.--15. 1. "CPL_ABORT,Completer Abort. The DMA read channel has received a PCIe completer abort completion status from the remote device in response to the MRd request. For more details see 'Linked List Mode'. Each bit corresponds to a DMA channel. Bit [0].." hexmask.long.byte 0x4 0.--7. 1. "UNSUPPORTED_REQ,Unsupported Request. The DMA read channel has received a PCIe unsupported request completion status from the remote device in response to the MRd request. For more details see 'Linked List Mode'. Each bit corresponds to a DMA channel." group.long (0xC4+0xC8000)++0x3 line.long 0x0 "DMA_READ_LINKED_LIST_ERR_EN_OFF,DMA Read Linked List Error Enable Register. The LIE and RIE bits in the LL element enable the channel 'done' interrupts (local and remote). The LLLAIE and LLRAIE bits enable the channel 'abort' interrupts (local and remote)." hexmask.long.byte 0x0 24.--31. 1. "RSVDP_24,Reserved for future use." hexmask.long.byte 0x0 16.--23. 1. "RD_CHANNEL_LLLAIE,Read Channel LL Local Abort Interrupt Enable (LLLAIE). You enable the read channel Local Abort interrupt through this bit. The LIE and RIE bits in the LL element enable the read channel done interrupts. Each bit corresponds to a DMA.." newline hexmask.long.byte 0x0 8.--15. 1. "RSVDP_8,Reserved for future use." hexmask.long.byte 0x0 0.--7. 1. "RD_CHANNEL_LLRAIE,Read Channel LL Remote Abort Interrupt Enable (LLRAIE). You enable the read channel Remote Abort interrupt through this bit. The LIE and RIE bits in the LL element enable the read channel done interrupts. Each bit corresponds to a DMA.." group.long (0xCC+0xC8000)++0x1F line.long 0x0 "DMA_READ_DONE_IMWR_LOW_OFF,DMA Read Done IMWr Address Low Register." hexmask.long 0x0 0.--31. 1. "DMA_READ_DONE_LOW_REG,The DMA uses this field to generate bits [31:0] of the address field for the Done IMWr TLP. Bits [1:0] must be '00' as this address must be dword aligned. Note: The access attributes of this field are as follows: - Wire: No access." line.long 0x4 "DMA_READ_DONE_IMWR_HIGH_OFF,DMA Read Done IMWr Address High Register." hexmask.long 0x4 0.--31. 1. "DMA_READ_DONE_HIGH_REG,The DMA uses this field to generate bits [63:32] of the address field for the Done IMWr TLP. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" line.long 0x8 "DMA_READ_ABORT_IMWR_LOW_OFF,DMA Read Abort IMWr Address Low Register." hexmask.long 0x8 0.--31. 1. "DMA_READ_ABORT_LOW_REG,The DMA uses this field to generate bits [31:0] of the address field for the Abort IMWr TLP. Bits [1:0] must be '00' as this address must be dword aligned. Note: The access attributes of this field are as follows: - Wire: No.." line.long 0xC "DMA_READ_ABORT_IMWR_HIGH_OFF,DMA Read Abort IMWr Address High Register." hexmask.long 0xC 0.--31. 1. "DMA_READ_ABORT_HIGH_REG,The DMA uses this field to generate bits [63:32] of the address field for the Abort IMWr TLP. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" line.long 0x10 "DMA_READ_CH01_IMWR_DATA_OFF,DMA Read Channel 1 and 0 IMWr Data Register." hexmask.long.word 0x10 16.--31. 1. "RD_CHANNEL_1_DATA,The DMA uses this field to generate the data field for the Done or Abort IMWr TLPs it generates for read channel 1. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" hexmask.long.word 0x10 0.--15. 1. "RD_CHANNEL_0_DATA,The DMA uses this field to generate the data field for the Done or Abort IMWr TLPs it generates for read channel 0. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" line.long 0x14 "DMA_READ_CH23_IMWR_DATA_OFF,DMA Read Channel 3 and 2 IMWr Data Register." hexmask.long.word 0x14 16.--31. 1. "RD_CHANNEL_3_DATA,The DMA uses this field to generate the data field for the Done or Abort IMWr TLPs it generates for read channel 3. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" hexmask.long.word 0x14 0.--15. 1. "RD_CHANNEL_2_DATA,The DMA uses this field to generate the data field for the Done or Abort IMWr TLPs it generates for read channel 2. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" line.long 0x18 "DMA_READ_CH45_IMWR_DATA_OFF,DMA Read Channel 5 and 4 IMWr Data Register." hexmask.long.word 0x18 16.--31. 1. "RD_CHANNEL_5_DATA,The DMA uses this field to generate the data field for the Done or Abort IMWr TLPs it generates for read channel 5. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" hexmask.long.word 0x18 0.--15. 1. "RD_CHANNEL_4_DATA,The DMA uses this field to generate the data field for the Done or Abort IMWr TLPs it generates for read channel 4. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" line.long 0x1C "DMA_READ_CH67_IMWR_DATA_OFF,DMA Read Channel 7 and 6 IMWr Data Register." hexmask.long.word 0x1C 16.--31. 1. "RD_CHANNEL_7_DATA,The DMA uses this field to generate the data field for the Done or Abort IMWr TLPs it generates for read channel 7. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" hexmask.long.word 0x1C 0.--15. 1. "RD_CHANNEL_6_DATA,The DMA uses this field to generate the data field for the Done or Abort IMWr TLPs it generates for read channel 6. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" rgroup.long (0x108+0xC8000)++0x7 line.long 0x0 "DMA_WRITE_ENGINE_HSHAKE_CNT_LOW_OFF,DMA Write Engine Handshake Counter Channel 0/1/2/3 Register." bitfld.long 0x0 29.--31. "RSVDP_29,Reserved for future use." "0,1,2,3,4,5,6,7" hexmask.long.byte 0x0 24.--28. 1. "DMA_WRITE_ENGINE_HSHAKE_CNT_CH3,DMA handshake counter for DMA Write Engine Channel 3. If CC_DMA_HSHAKE =1 the data transfer in Linked List mode starts only when the counter is non-zero." newline bitfld.long 0x0 21.--23. "RSVDP_21,Reserved for future use." "0,1,2,3,4,5,6,7" hexmask.long.byte 0x0 16.--20. 1. "DMA_WRITE_ENGINE_HSHAKE_CNT_CH2,DMA handshake counter for DMA Write Engine Channel 2. If CC_DMA_HSHAKE =1 the data transfer in Linked List mode starts only when the counter is non-zero." newline bitfld.long 0x0 13.--15. "RSVDP_13,Reserved for future use." "0,1,2,3,4,5,6,7" hexmask.long.byte 0x0 8.--12. 1. "DMA_WRITE_ENGINE_HSHAKE_CNT_CH1,DMA handshake counter for DMA Write Engine Channel 1. If CC_DMA_HSHAKE =1 the data transfer in Linked List mode starts only when the counter is non-zero." newline bitfld.long 0x0 5.--7. "RSVDP_5,Reserved for future use." "0,1,2,3,4,5,6,7" hexmask.long.byte 0x0 0.--4. 1. "DMA_WRITE_ENGINE_HSHAKE_CNT_CH0,DMA handshake counter for DMA Write Engine Channel 0. If CC_DMA_HSHAKE =1 the data transfer in Linked List mode starts only when the counter is non-zero." line.long 0x4 "DMA_WRITE_ENGINE_HSHAKE_CNT_HIGH_OFF,DMA Write Engine Handshake Counter Channel 4/5/6/7 Register." bitfld.long 0x4 29.--31. "RSVDP_29,Reserved for future use." "0,1,2,3,4,5,6,7" hexmask.long.byte 0x4 24.--28. 1. "DMA_WRITE_ENGINE_HSHAKE_CNT_CH7,DMA handshake counter for DMA Write Engine Channel 7. If CC_DMA_HSHAKE =1 the data transfer in Linked List mode starts only when the counter is non-zero." newline bitfld.long 0x4 21.--23. "RSVDP_21,Reserved for future use." "0,1,2,3,4,5,6,7" hexmask.long.byte 0x4 16.--20. 1. "DMA_WRITE_ENGINE_HSHAKE_CNT_CH6,DMA handshake counter for DMA Write Engine Channel 6. If CC_DMA_HSHAKE =1 the data transfer in Linked List mode starts only when the counter is non-zero." newline bitfld.long 0x4 13.--15. "RSVDP_13,Reserved for future use." "0,1,2,3,4,5,6,7" hexmask.long.byte 0x4 8.--12. 1. "DMA_WRITE_ENGINE_HSHAKE_CNT_CH5,DMA handshake counter for DMA Write Engine Channel 5. If CC_DMA_HSHAKE =1 the data transfer in Linked List mode starts only when the counter is non-zero." newline bitfld.long 0x4 5.--7. "RSVDP_5,Reserved for future use." "0,1,2,3,4,5,6,7" hexmask.long.byte 0x4 0.--4. 1. "DMA_WRITE_ENGINE_HSHAKE_CNT_CH4,DMA handshake counter for DMA Write Engine Channel 4. If CC_DMA_HSHAKE =1 the data transfer in Linked List mode starts only when the counter is non-zero." rgroup.long (0x118+0xC8000)++0x7 line.long 0x0 "DMA_READ_ENGINE_HSHAKE_CNT_LOW_OFF,DMA Read Engine Handshake Counter Channel 0/1/2/3 Register." bitfld.long 0x0 29.--31. "RSVDP_29,Reserved for future use." "0,1,2,3,4,5,6,7" hexmask.long.byte 0x0 24.--28. 1. "DMA_READ_ENGINE_HSHAKE_CNT_CH3,DMA handshake counter for DMA Read Engine Channel 3. If CC_DMA_HSHAKE =1 the data transfer in Linked List mode starts only when the counter is non-zero." newline bitfld.long 0x0 21.--23. "RSVDP_21,Reserved for future use." "0,1,2,3,4,5,6,7" hexmask.long.byte 0x0 16.--20. 1. "DMA_READ_ENGINE_HSHAKE_CNT_CH2,DMA handshake counter for DMA Read Engine Channel 2. If CC_DMA_HSHAKE =1 the data transfer in Linked List mode starts only when the counter is non-zero." newline bitfld.long 0x0 13.--15. "RSVDP_13,Reserved for future use." "0,1,2,3,4,5,6,7" hexmask.long.byte 0x0 8.--12. 1. "DMA_READ_ENGINE_HSHAKE_CNT_CH1,DMA handshake counter for DMA Read Engine Channel 1. If CC_DMA_HSHAKE =1 the data transfer in Linked List mode starts only when the counter is non-zero." newline bitfld.long 0x0 5.--7. "RSVDP_5,Reserved for future use." "0,1,2,3,4,5,6,7" hexmask.long.byte 0x0 0.--4. 1. "DMA_READ_ENGINE_HSHAKE_CNT_CH0,DMA handshake counter for DMA Read Engine Channel 0. If CC_DMA_HSHAKE =1 the data transfer in Linked List mode starts only when the counter is non-zero." line.long 0x4 "DMA_READ_ENGINE_HSHAKE_CNT_HIGH_OFF,DMA Read Engine Handshake Counter Channel 4/5/6/7 Register." bitfld.long 0x4 29.--31. "RSVDP_29,Reserved for future use." "0,1,2,3,4,5,6,7" hexmask.long.byte 0x4 24.--28. 1. "DMA_READ_ENGINE_HSHAKE_CNT_CH7,DMA handshake counter for DMA Read Engine Channel 7. If CC_DMA_HSHAKE =1 the data transfer in Linked List mode starts only when the counter is non-zero." newline bitfld.long 0x4 21.--23. "RSVDP_21,Reserved for future use." "0,1,2,3,4,5,6,7" hexmask.long.byte 0x4 16.--20. 1. "DMA_READ_ENGINE_HSHAKE_CNT_CH6,DMA handshake counter for DMA Read Engine Channel 6. If CC_DMA_HSHAKE =1 the data transfer in Linked List mode starts only when the counter is non-zero." newline bitfld.long 0x4 13.--15. "RSVDP_13,Reserved for future use." "0,1,2,3,4,5,6,7" hexmask.long.byte 0x4 8.--12. 1. "DMA_READ_ENGINE_HSHAKE_CNT_CH5,DMA handshake counter for DMA Read Engine Channel 5. If CC_DMA_HSHAKE =1 the data transfer in Linked List mode starts only when the counter is non-zero." newline bitfld.long 0x4 5.--7. "RSVDP_5,Reserved for future use." "0,1,2,3,4,5,6,7" hexmask.long.byte 0x4 0.--4. 1. "DMA_READ_ENGINE_HSHAKE_CNT_CH4,DMA handshake counter for DMA Read Engine Channel 4. If CC_DMA_HSHAKE =1 the data transfer in Linked List mode starts only when the counter is non-zero." repeat 8. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 )(list 0x0 0x200 0x400 0x600 0x800 0xA00 0xC00 0xE00 ) group.long ($2+0x200+0xC8000)++0x3 line.long 0x0 "DMA_CH_CONTROL1_OFF_WRCH_$1,DMA Write Channel Control 1 Register." bitfld.long 0x0 30.--31. "DMA_AT,Address Translation TLP Header Bit (AT) The DMA uses this TLP header field when generating MRd/MWr (not IMWr) TLPs. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" "0,1,2,3" bitfld.long 0x0 27.--29. "DMA_TC,Traffic Class TLP Header Bit (TC) The DMA uses this TLP header field when generating MRd/MWr (not IMWr) TLPs. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 26. "DMA_RESERVED5,Reserved. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" "0,1" bitfld.long 0x0 25. "DMA_RO,Relaxed Ordering TLP Header Bit (RO) The DMA uses this TLP header field when generating MRd/MWr (not IMWr) TLPs. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" "0,1" newline bitfld.long 0x0 24. "DMA_NS_SRC,Source No Snoop TLP Header Bit (DMA_NS_SRC). The DMA uses this TLP header field when generating MRd (SAR addressing space) (not IMWr) TLPs. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" "0,1" bitfld.long 0x0 23. "DMA_NS_DST,Destination No Snoop TLP Header Bit (DMA_NS_DST). The DMA uses this TLP header field when generating MWr (DAR addressing space) (not IMWr) TLPs. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" "0,1" newline bitfld.long 0x0 22. "DMA_MEM_TYPE,Master AXI ACE-Lite Cache Coherency Control. This field sets the DMA channel memory type of the address space of the data transfer as follows: - 0x0:peripheral type - 0x1:memory type For more details see 'ACE-Lite Features and Limitations'.." "peripheral type,memory type" hexmask.long.byte 0x0 17.--21. 1. "DMA_RESERVED2,Reserved. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" newline hexmask.long.byte 0x0 12.--16. 1. "DMA_FUNC_NUM,Function Number (FN). The controller uses this field when generating the requester ID for the MRd/MWr DMA TLP. When you have enabled SR-IOV then this field is ignored if you have set the VFE field in the 'DMA Write Channel Control 2.." bitfld.long 0x0 10.--11. "DMA_RESERVED1,Reserved. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" "0,1,2,3" newline bitfld.long 0x0 9. "LLE,Linked List Enable (LLE). - 0: Disable linked list operation - 1: Enable linked list operation Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" "Disable linked list operation,Enable linked list operation" bitfld.long 0x0 8. "CCS,Consumer Cycle State (CCS). Used in linked list mode only. It is used to synchronize the producer (software) and the consumer (DMA). For more details see 'PCS-CCS-CB-TCB Producer-Consumer Synchronization'. You must initialize this bit. The DMA.." "0,1" newline bitfld.long 0x0 7. "DMA_RESERVED0,Reserved. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" "0,1" bitfld.long 0x0 5.--6. "CS,Channel Status (CS). The channel status bits identify the current operational state of the DMA channel. The operation state encoding for each DMA channel is a s follows: - 00: Reserved - 01: Running. This channel is active and transferring data. - 10:.." "Reserved,Running,?,?" newline bitfld.long 0x0 4. "RIE,Remote Interrupt Enable (RIE). You must set this bit to enable the generation of the Done or Abort Remote interrupts. For more details see 'Interrupts and Error Handling'. In LL mode the DMA overwrites this with the RIE of the LL element. The RIE.." "0,1" bitfld.long 0x0 3. "LIE,Local Interrupt Enable (LIE). You must set this bit to enable the generation of the Done or Abort Local interrupts. For more details see 'Interrupts and Error Handling'. In LL mode the DMA overwrites this with the LIE of the LL element. The LIE bit.." "0,1" newline bitfld.long 0x0 2. "LLP,Load Link Pointer (LLP). Used in linked list mode only. Indicates that this linked list element is a link element and its LL element pointer dwords are pointing to the next (non-contiguous) element. The DMA loads this field with the LLP of the.." "0,1" bitfld.long 0x0 1. "TCB,Toggle Cycle Bit (TCB). Indicates to the DMA to toggle its interpretation of the CB. Used in linked list mode only. It is used to synchronize the producer (software) and the consumer (DMA). For more details see 'PCS-CCS-CB-TCB Producer-Consumer.." "0,1" newline bitfld.long 0x0 0. "CB,Cycle Bit (CB). Used in linked list mode only. It is used to synchronize the producer (software) and the consumer (DMA). For more details see 'PCS-CCS-CB-TCB Producer-Consumer Synchronization'. The DMA loads this field with the CB of the linked list.." "0,1" repeat.end repeat 8. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 )(list 0x0 0x200 0x400 0x600 0x800 0xA00 0xC00 0xE00 ) group.long ($2+0x208+0xC8000)++0x3 line.long 0x0 "DMA_TRANSFER_SIZE_OFF_WRCH_$1,DMA Write Transfer Size Register." hexmask.long 0x0 0.--31. 1. "DMA_TRANSFER_SIZE,DMA Transfer Size. You program this register with the size of the DMA transfer. The maximum DMA transfer size is 4Gbytes. The minimum transfer size is one byte (0x1). This field is automatically decremented by the DMA as the DMA write.." repeat.end repeat 8. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 )(list 0x0 0x200 0x400 0x600 0x800 0xA00 0xC00 0xE00 ) group.long ($2+0x20C+0xC8000)++0x3 line.long 0x0 "DMA_SAR_LOW_OFF_WRCH_$1,DMA Write SAR Low Register." hexmask.long 0x0 0.--31. 1. "SRC_ADDR_REG_LOW,Source Address Register (Lower 32 bits). Indicates the next address to be read from. The DMA increments the SAR as the DMA transfer progresses. In LL mode the DMA overwrites this with the corresponding dword of the LL element. - DMA.." repeat.end repeat 8. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 )(list 0x0 0x200 0x400 0x600 0x800 0xA00 0xC00 0xE00 ) group.long ($2+0x210+0xC8000)++0x3 line.long 0x0 "DMA_SAR_HIGH_OFF_WRCH_$1,DMA Write SAR High Register." hexmask.long 0x0 0.--31. 1. "SRC_ADDR_REG_HIGH,Source Address Register (Higher 32 bits). In LL mode the DMA overwrites this with the corresponding dword of the LL element. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" repeat.end repeat 8. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 )(list 0x0 0x200 0x400 0x600 0x800 0xA00 0xC00 0xE00 ) group.long ($2+0x214+0xC8000)++0x3 line.long 0x0 "DMA_DAR_LOW_OFF_WRCH_$1,DMA Write DAR Low Register." hexmask.long 0x0 0.--31. 1. "DST_ADDR_REG_LOW,Destination Address Register (Lower 32 bits). Indicates the next address to be written to. The DMA increments the DAR as the DMA transfer progresses. In LL mode the DMA overwrites this with the corresponding dword of the LL element. -.." repeat.end repeat 8. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 )(list 0x0 0x200 0x400 0x600 0x800 0xA00 0xC00 0xE00 ) group.long ($2+0x218+0xC8000)++0x3 line.long 0x0 "DMA_DAR_HIGH_OFF_WRCH_$1,DMA Write DAR High Register." hexmask.long 0x0 0.--31. 1. "DST_ADDR_REG_HIGH,Destination Address Register (Higher 32 bits). In LL mode the DMA overwrites this with the corresponding dword of the LL element. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" repeat.end repeat 8. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 )(list 0x0 0x200 0x400 0x600 0x800 0xA00 0xC00 0xE00 ) group.long ($2+0x21C+0xC8000)++0x3 line.long 0x0 "DMA_LLP_LOW_OFF_WRCH_$1,DMA Write Linked List Pointer Low Register." hexmask.long 0x0 0.--31. 1. "LLP_LOW,Lower bits of the address of the linked list transfer list in local memory. Used in linked list mode only. Updated by the DMA to point to the next element in the transfer list after the previous element is consumed. - When the current element is.." repeat.end repeat 8. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 )(list 0x0 0x200 0x400 0x600 0x800 0xA00 0xC00 0xE00 ) group.long ($2+0x220+0xC8000)++0x3 line.long 0x0 "DMA_LLP_HIGH_OFF_WRCH_$1,DMA Write Linked List Pointer High Register." hexmask.long 0x0 0.--31. 1. "LLP_HIGH,Upper 32 bits of the address of the linked list transfer list in local memory. Used in linked list mode only. Updated by the DMA to point to the next element in the transfer list as elements are consumed. Note: The access attributes of this.." repeat.end repeat 8. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 )(list 0x0 0x200 0x400 0x600 0x800 0xA00 0xC00 0xE00 ) group.long ($2+0x300+0xC8000)++0x3 line.long 0x0 "DMA_CH_CONTROL1_OFF_RDCH_$1,DMA Read Channel Control 1 Register." bitfld.long 0x0 30.--31. "DMA_AT,Address Translation TLP Header Bit (AT) The DMA uses this TLP header field when generating MRd/MWr (not IMWr) TLPs. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" "0,1,2,3" bitfld.long 0x0 27.--29. "DMA_TC,Traffic Class TLP Header Bit (TC) The DMA uses this TLP header field when generating MRd/MWr (not IMWr) TLPs. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 26. "DMA_RESERVED5,Reserved. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" "0,1" bitfld.long 0x0 25. "DMA_RO,Relaxed Ordering TLP Header Bit (RO) The DMA uses this TLP header field when generating MRd/MWr (not IMWr) TLPs. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" "0,1" newline bitfld.long 0x0 24. "DMA_NS_SRC,Source No Snoop TLP Header Bit (DMA_NS_SRC). The DMA uses this TLP header field when generating MRd (SAR addressing space) (not IMWr) TLPs. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" "0,1" bitfld.long 0x0 23. "DMA_NS_DST,Destination No Snoop TLP Header Bit (DMA_NS_DST). The DMA uses this TLP header field when generating MWr (DAR addressing space) (not IMWr) TLPs. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" "0,1" newline bitfld.long 0x0 22. "DMA_MEM_TYPE,Master AXI ACE-Lite Cache Coherency Control. This field sets the DMA channel memory type of the address space of the data transfer as follows: - 0x0:peripheral type - 0x1:memory type For more details see 'ACE-Lite Features and Limitations'.." "peripheral type,memory type" hexmask.long.byte 0x0 17.--21. 1. "DMA_RESERVED2,Reserved. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" newline hexmask.long.byte 0x0 12.--16. 1. "DMA_FUNC_NUM,Function Number (FN). The controller uses this field when generating the requester ID for the MRd/MWr DMA TLP. When you have enabled SR-IOV then this field is ignored if you have set the VFE field in the 'DMA Read Channel Control 2.." bitfld.long 0x0 10.--11. "DMA_RESERVED1,Reserved. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" "0,1,2,3" newline bitfld.long 0x0 9. "LLE,Linked List Enable (LLE). - 0: Disable linked list operation - 1: Enable linked list operation Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" "Disable linked list operation,Enable linked list operation" bitfld.long 0x0 8. "CCS,Consumer Cycle State (CCS). Used in linked list mode only. It is used to synchronize the producer (software) and the consumer (DMA). For more details see 'PCS-CCS-CB-TCB Producer-Consumer Synchronization'. You must initialize this bit. The DMA.." "0,1" newline bitfld.long 0x0 7. "DMA_RESERVED0,Reserved. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" "0,1" bitfld.long 0x0 5.--6. "CS,Channel Status (CS). The channel status bits identify the current operational state of the DMA channel. The operation state encoding for each DMA channel is a s follows: - 00: Reserved - 01: Running. This channel is active and transferring data. - 10:.." "Reserved,Running,?,?" newline bitfld.long 0x0 4. "RIE,Remote Interrupt Enable (RIE). You must set this bit to enable the generation of the Done or Abort Remote interrupts. For more details see 'Interrupts and Error Handling'. In LL mode the DMA overwrites this with the RIE of the LL element. The RIE.." "0,1" bitfld.long 0x0 3. "LIE,Local Interrupt Enable (LIE). You must set this bit to enable the generation of the Done or Abort Local interrupts. For more details see 'Interrupts and Error Handling'. In LL mode the DMA overwrites this with the LIE of the LL element. The LIE bit.." "0,1" newline bitfld.long 0x0 2. "LLP,Load Link Pointer (LLP). Used in linked list mode only. Indicates that this linked list element is a link element and its LL element pointer dwords are pointing to the next (non-contiguous) element. The DMA loads this field with the LLP of the.." "0,1" bitfld.long 0x0 1. "TCB,Toggle Cycle Bit (TCB). Indicates to the DMA to toggle its interpretation of the CB. Used in linked list mode only. It is used to synchronize the producer (software) and the consumer (DMA). For more details see 'PCS-CCS-CB-TCB Producer-Consumer.." "0,1" newline bitfld.long 0x0 0. "CB,Cycle Bit (CB). Used in linked list mode only. It is used to synchronize the producer (software) and the consumer (DMA). For more details see 'PCS-CCS-CB-TCB Producer-Consumer Synchronization'. The DMA loads this field with the CB of the linked list.." "0,1" repeat.end repeat 8. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 )(list 0x0 0x200 0x400 0x600 0x800 0xA00 0xC00 0xE00 ) group.long ($2+0x308+0xC8000)++0x3 line.long 0x0 "DMA_TRANSFER_SIZE_OFF_RDCH_$1,DMA Read Transfer Size Register." hexmask.long 0x0 0.--31. 1. "DMA_TRANSFER_SIZE,DMA Transfer Size. You program this register with the size of the DMA transfer. The maximum DMA transfer size is 4Gbytes. The minimum transfer size is one byte (0x1). This field is automatically decremented by the DMA as the DMA read.." repeat.end repeat 8. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 )(list 0x0 0x200 0x400 0x600 0x800 0xA00 0xC00 0xE00 ) group.long ($2+0x30C+0xC8000)++0x3 line.long 0x0 "DMA_SAR_LOW_OFF_RDCH_$1,DMA Read SAR Low Register." hexmask.long 0x0 0.--31. 1. "SRC_ADDR_REG_LOW,Source Address Register (Lower 32 bits). Indicates the next address to be read from. The DMA increments the SAR as the DMA transfer progresses. In LL mode the DMA overwrites this with the corresponding dword of the LL element. - DMA.." repeat.end repeat 8. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 )(list 0x0 0x200 0x400 0x600 0x800 0xA00 0xC00 0xE00 ) group.long ($2+0x310+0xC8000)++0x3 line.long 0x0 "DMA_SAR_HIGH_OFF_RDCH_$1,DMA Read SAR High Register." hexmask.long 0x0 0.--31. 1. "SRC_ADDR_REG_HIGH,Source Address Register (Higher 32 bits). In LL mode the DMA overwrites this with the corresponding dword of the LL element. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" repeat.end repeat 8. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 )(list 0x0 0x200 0x400 0x600 0x800 0xA00 0xC00 0xE00 ) group.long ($2+0x314+0xC8000)++0x3 line.long 0x0 "DMA_DAR_LOW_OFF_RDCH_$1,DMA Read DAR Low Register." hexmask.long 0x0 0.--31. 1. "DST_ADDR_REG_LOW,Destination Address Register (Lower 32 bits). Indicates the next address to be written to. The DMA increments the DAR as the DMA transfer progresses. In LL mode the DMA overwrites this with the corresponding dword of the LL element. -.." repeat.end repeat 8. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 )(list 0x0 0x200 0x400 0x600 0x800 0xA00 0xC00 0xE00 ) group.long ($2+0x318+0xC8000)++0x3 line.long 0x0 "DMA_DAR_HIGH_OFF_RDCH_$1,DMA Read DAR High Register." hexmask.long 0x0 0.--31. 1. "DST_ADDR_REG_HIGH,Destination Address Register (Higher 32 bits). In LL mode the DMA overwrites this with the corresponding dword of the LL element. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" repeat.end repeat 8. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 )(list 0x0 0x200 0x400 0x600 0x800 0xA00 0xC00 0xE00 ) group.long ($2+0x31C+0xC8000)++0x3 line.long 0x0 "DMA_LLP_LOW_OFF_RDCH_$1,DMA Read Linked List Pointer Low Register." hexmask.long 0x0 0.--31. 1. "LLP_LOW,Lower bits of the address of the linked list transfer list in local memory. Used in linked list mode only. Updated by the DMA to point to the next element in the transfer list after the previous element is consumed. - When the current element is.." repeat.end repeat 8. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 )(list 0x0 0x200 0x400 0x600 0x800 0xA00 0xC00 0xE00 ) group.long ($2+0x320+0xC8000)++0x3 line.long 0x0 "DMA_LLP_HIGH_OFF_RDCH_$1,DMA Read Linked List Pointer High Register." hexmask.long 0x0 0.--31. 1. "LLP_HIGH,Upper 32 bits of the address of the linked list transfer list in local memory. Used in linked list mode only. Updated by the DMA to point to the next element in the transfer list as elements are consumed. Note: The access attributes of this.." repeat.end tree.end tree "PF0_ATU_CAP (ATU Por Logic Structure)" repeat 8. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 )(list 0x0 0x200 0x400 0x600 0x800 0xA00 0xC00 0xE00 ) group.long ($2+0xC0000)++0x3 line.long 0x0 "IATU_REGION_CTRL_1_OFF_OUTBOUND_$1,iATU Region Control 1 Register." bitfld.long 0x0 20. "CTRL_1_FUNC_NUM,Function Number. - When the address of an outbound TLP is matched to this region and the FUNC_BYPASS field in the 'iATU Control 2 Register' is '0' then the function number used in generating the function part of the requester ID (RID).." "0,1" newline bitfld.long 0x0 13. "INCREASE_REGION_SIZE,Increase the maximum ATU Region size. When set the maximum ATU Region size is determined by CX_ATU_MAX_REGION_SIZE. When clear the maximum ATU Region size is 4 GB (default). Note: This register field is sticky." "0,1" newline bitfld.long 0x0 9.--10. "ATTR,When the address of an outbound TLP is matched to this region then the ATTR field of the TLP is changed to the value in this register. Note: This register field is sticky." "0,1,2,3" newline bitfld.long 0x0 8. "TD,This is a reserved field. Do not use. Note: This register field is sticky." "0,1" newline bitfld.long 0x0 5.--7. "TC,When the address of an outbound TLP is matched to this region then the TC field of the TLP is changed to the value in this register. Note: This register field is sticky." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x0 0.--4. 1. "TYPE,When the address of an outbound TLP is matched to this region then the TYPE field of the TLP is changed to the value in this register. Note: This register field is sticky." repeat.end repeat 8. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 )(list 0x0 0x200 0x400 0x600 0x800 0xA00 0xC00 0xE00 ) group.long ($2+0x4+0xC0000)++0x3 line.long 0x0 "IATU_REGION_CTRL_2_OFF_OUTBOUND_$1,iATU Region Control 2 Register." bitfld.long 0x0 31. "REGION_EN,Region Enable. This bit must be set to '1' for address translation to take place. Note: This register field is sticky." "0,1" newline bitfld.long 0x0 29. "INVERT_MODE,Invert Mode. When set the address matching region is inverted. Therefore an address match occurs when the untranslated address is in the region outside the defined range (Base Address to Limit Address). Note: This register field is sticky." "0,1" newline bitfld.long 0x0 28. "CFG_SHIFT_MODE,CFG Shift Mode. The iATU uses bits [27:12] of the untranslated address (on the XALI0/1/2 interface or AXI slave interface address) to form the BDF number of the outgoing CFG TLP. This supports the Enhanced Configuration Address Mapping.." "0,1" newline bitfld.long 0x0 27. "DMA_BYPASS,DMA Bypass Mode. Allows request TLPs which are initiated by the DMA controller to pass through the iATU untranslated. Note: This field is reserved for the SW product. You must set it to '0'. Note: This register field is sticky." "0,1" newline bitfld.long 0x0 23. "HEADER_SUBSTITUTE_EN,Header Substitute Enable. When enabled and region address is matched the iATU fully substitutes bytes 8-11 (for 3 DWORD header) or bytes 12-15 (for 4 DWORD header) of the outbound TLP header with the contents of the LWR_TARGET_RW.." "LWR_TARGET_RW in the..,LWR_TARGET_RW in the.." newline bitfld.long 0x0 22. "INHIBIT_PAYLOAD,Inhibit TLP Payload Data for TLP's in Matched Region; assign iATU region to be TLP without data. When enabled and region address is matched the iATU marks all TLPs as having no payload data by forcing the TLP header Fmt[1] bit =0.." "Fmt[1] =0/1 so that TLPs with or without data..,Fmt[1] =0 so that only TLP type without data is.." newline bitfld.long 0x0 21. "TLP_HEADER_FIELDS_BYPASS,TLP Header Fields Translation Bypass. In this mode header fields of the translated TLP is taken from your application transmit interface or if AMBA is configured from the AMBA sideband bus (slv_awmisc_info) and not from the.." "0,1" newline bitfld.long 0x0 20. "SNP,Serialize Non-Posted Requests. In this mode when the AXI Bridge is populated same AXI ID Non-Posted Read/Write Requests are transmitted on the wire if there are no other same ID Non-Posted Requests outstanding. Note: This register field is sticky." "0,1" newline bitfld.long 0x0 19. "FUNC_BYPASS,Function Number Translation Bypass. In this mode the function number of the translated TLP is taken from your application transmit interface and not from the CTRL_1_FUNC_NUM field of the 'iATU Control 1 Register' or the VF_NUMBER field of.." "0,1" newline bitfld.long 0x0 16. "TAG_SUBSTITUTE_EN,TAG Substitute Enable. When enabled and region address is matched the iATU substitutes the TAG field of the outbound TLP header with the contents of the TAG field in this register. The expected usage scenario is translation from AXI.." "0,1" newline hexmask.long.byte 0x0 8.--15. 1. "TAG,TAG. The substituted TAG field (byte 6) in the outgoing TLP header when TAG_SUBSTITUTE_EN is set. Note: This register field is sticky." newline hexmask.long.byte 0x0 0.--7. 1. "MSG_CODE,MSG TLPs (Message Code). When the address of an outbound TLP is matched to this region and the translated TLP TYPE field is Msg or MsgD; then the message field of the TLP is changed to the value in this register. Memory TLPs: (ST;Steering Tag)." repeat.end repeat 8. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 )(list 0x0 0x200 0x400 0x600 0x800 0xA00 0xC00 0xE00 ) group.long ($2+0x8+0xC0000)++0x3 line.long 0x0 "IATU_LWR_BASE_ADDR_OFF_OUTBOUND_$1,iATU Lower Base Address Register. The CX_ATU_MIN_REGION_SIZE configuration parameter (Value Range: 4 kB. 8 kB. 16 kB. 32 kB. 64 kB defaults to 64 kB) specifies the minimum size of an address translation region. For.." hexmask.long.tbyte 0x0 12.--31. 1. "LWR_BASE_RW,Forms bits [31:n] of the start address of the address region to be translated. n is log2(CX_ATU_MIN_REGION_SIZE) Note: This register field is sticky." newline hexmask.long.word 0x0 0.--11. 1. "LWR_BASE_HW,Forms bits [n-1:0] of the start address of the address region to be translated. The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary so these bits are always 0. A write to this location is ignored by the PCIe controller." repeat.end repeat 8. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 )(list 0x0 0x200 0x400 0x600 0x800 0xA00 0xC00 0xE00 ) group.long ($2+0xC+0xC0000)++0x3 line.long 0x0 "IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_$1,iATU Upper Base Address Register." hexmask.long 0x0 0.--31. 1. "UPPER_BASE_RW,Forms bits [63:32] of the start (and end) address of the address region to be translated. In systems with a 32-bit address space this register is not used and therefore writing to this register has no effect. Note: This register field is.." repeat.end repeat 8. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 )(list 0x0 0x200 0x400 0x600 0x800 0xA00 0xC00 0xE00 ) group.long ($2+0x10+0xC0000)++0x3 line.long 0x0 "IATU_LIMIT_ADDR_OFF_OUTBOUND_$1,iATU Limit Address Register." hexmask.long.tbyte 0x0 12.--31. 1. "LIMIT_ADDR_RW,Forms upper bits of the end address of the address region to be translated. Note: This register field is sticky." newline hexmask.long.word 0x0 0.--11. 1. "LIMIT_ADDR_HW,Forms lower bits of the end address of the address region to be translated. The end address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary so these bits are always all ones. A write to this location is ignored by the PCIe.." repeat.end repeat 8. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 )(list 0x0 0x200 0x400 0x600 0x800 0xA00 0xC00 0xE00 ) group.long ($2+0x14+0xC0000)++0x3 line.long 0x0 "IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_$1,iATU Lower Target Address Register." hexmask.long 0x0 0.--31. 1. "LWR_TARGET_RW_OUTBOUND,When HEADER_SUBSTITUTE_EN in IATU_REGION_CTRL_2_OFF_OUTBOUND_ is '0' (normal operation): - LWR_TARGET_RW[31:n] forms MSB's of the Lower Target part of the new address of the translated region; - LWR_TARGET_RW[n-1:0] are not used." repeat.end repeat 8. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 )(list 0x0 0x200 0x400 0x600 0x800 0xA00 0xC00 0xE00 ) group.long ($2+0x18+0xC0000)++0x3 line.long 0x0 "IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_$1,iATU Upper Target Address Register." hexmask.long 0x0 0.--31. 1. "UPPER_TARGET_RW,Forms bits [63:32] of the start address (Upper Target part) of the new address of the translated region. Note: This register field is sticky." repeat.end repeat 8. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 )(list 0x0 0x200 0x400 0x600 0x800 0xA00 0xC00 0xE00 ) group.long ($2+0x1C+0xC0000)++0x3 line.long 0x0 "IATU_REGION_CTRL_3_OFF_OUTBOUND_$1,iATU Region Control 3 Register." bitfld.long 0x0 31. "VF_ACTIVE,Virtual Function Active. Indicates that all of the outbound accesses are from virtual functions. For more details see VF_ACTIVE field. Note: This register field is sticky." "0,1" newline hexmask.long 0x0 3.--30. 1. "RSVDP_VF_NUMBER,Reserved for future use." newline bitfld.long 0x0 0.--2. "VF_NUMBER,Virtual Function Number. When the address of an outbound TLP is matched to this region and the FUNC_BYPASS field in the 'iATU Control 2 Register' is '0' then this field used in generating the Function part of the requester ID (RID) field of.." "0,1,2,3,4,5,6,7" repeat.end repeat 8. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 )(list 0x0 0x200 0x400 0x600 0x800 0xA00 0xC00 0xE00 ) group.long ($2+0x100+0xC0000)++0x3 line.long 0x0 "IATU_REGION_CTRL_1_OFF_INBOUND_$1,iATU Region Control 1 Register." bitfld.long 0x0 20. "CTRL_1_FUNC_NUM,Function Number. - MEM-I/O: When the Address and BAR matching logic in the controller indicate that a MEM-I/O transaction matches a BAR in the function corresponding to this value then address translation proceeds. This check is only.." "?,When the destination function number as.." newline bitfld.long 0x0 13. "INCREASE_REGION_SIZE,Increase the maximum ATU Region size. When set the maximum ATU Region size is determined by CX_ATU_MAX_REGION_SIZE. When clear the maximum ATU Region size is 4 GB (default). Note: This register field is sticky." "0,1" newline bitfld.long 0x0 9.--10. "ATTR,When the ATTR field of an inbound TLP is matched to this value then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the 'ATTR Match Enable' bit of the 'iATU Control 2 Register' is.." "0,1,2,3" newline bitfld.long 0x0 8. "TD,When the TD field of an inbound TLP is matched to this value then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the 'TD Match Enable' bit of the 'iATU Control 2 Register' is set." "0,1" newline bitfld.long 0x0 5.--7. "TC,When the TC field of an inbound TLP is matched to this value then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the 'TC Match Enable' bit of the 'iATU Control 2 Register' is set." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x0 0.--4. 1. "TYPE,When the TYPE field of an inbound TLP is matched to this value then address translation proceeds (when all other enabled field-matches are successful). Note: This register field is sticky." repeat.end repeat 8. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 )(list 0x0 0x200 0x400 0x600 0x800 0xA00 0xC00 0xE00 ) group.long ($2+0x104+0xC0000)++0x3 line.long 0x0 "IATU_REGION_CTRL_2_OFF_INBOUND_$1,iATU Region Control 2 Register." bitfld.long 0x0 31. "REGION_EN,Region Enable. This bit must be set to '1' for address translation to take place. Note: This register field is sticky." "0,1" newline bitfld.long 0x0 30. "MATCH_MODE,Match Mode. Determines Inbound matching mode for TLPs. The mode depends on the type of TLP that is received as follows: For MEM-I/O TLPs this field is interpreted as follows: - 0: Address Match Mode. The iATU operates using addresses as in.." "Address Match Mode,Vendor ID Match Mode" newline bitfld.long 0x0 29. "INVERT_MODE,Invert Mode. When set the address matching region is inverted. Therefore an address match occurs when the untranslated address is in the region outside the defined range (Base Address to Limit Address). Note: This register field is sticky." "0,1" newline bitfld.long 0x0 28. "CFG_SHIFT_MODE,CFG Shift Mode. This is useful for CFG transactions where the PCIe configuration mechanism maps bits [27:12] of the address to the bus/device and function number. This allows a CFG configuration space to be located in any 256MB window of.." "0,1" newline bitfld.long 0x0 27. "FUZZY_TYPE_MATCH_CODE,Fuzzy Type Match Mode. When enabled the iATU relaxes the matching of the TLP TYPE field against the expected TYPE field so that - CfgRd0 and CfgRd1 TLPs are seen as identical. Similarly with CfgWr0 and CfgWr1. - MWr MRd and MRdLk.." "0,1" newline bitfld.long 0x0 26. "VFBAR_MATCH_MODE_EN,VF BAR Match Mode enable. When set Virtual Function BAR matching is used which allows all VFs in a PF which match a BAR to be matched with a single ATU region. Note: This register field is sticky." "0,1" newline bitfld.long 0x0 24.--25. "RESPONSE_CODE,Response Code. Defines the type of response to give for accesses matching this region. This overrides the normal RADM filter response. Note that this feature is not available for any region where Single Address Location Translate is.." "Normal RADM filter response is used,Unsupported request,?,?" newline bitfld.long 0x0 23. "SINGLE_ADDR_LOC_TRANS_EN,Single Address Location Translate Enable. When enabled Rx TLPs can be translated to a single address location as determined by the target address register of the iATU region. The main usage scenario is translation of Messages.." "0,1" newline bitfld.long 0x0 21. "MSG_CODE_MATCH_EN,Message Code Match Enable (Msg TLPS). Ensures that a successful message Code TLP field comparison match (see Message Code field of the 'iATU Control 2 Register') occurs (in MSG transactions) for address translation to proceed. ST Match.." "0,1" newline bitfld.long 0x0 20. "VF_MATCH_EN,Virtual Function Number Match Enable. Ensures that a successful Virtual Function Number TLP field comparison match (see Virtual Function Number field of the 'iATU Control 3 Register') occurs (in MEM-I/O transactions) for address translation.." "0,1" newline bitfld.long 0x0 19. "FUNC_NUM_MATCH_EN,Function Number Match Enable. Ensures that a successful Function Number TLP field comparison match (see Function Number field of the 'iATU Control 1 Register') occurs (in MEM-I/O and CFG0/CFG1 transactions) for address translation to.." "0,1" newline bitfld.long 0x0 16. "ATTR_MATCH_EN,ATTR Match Enable. Ensures that a successful ATTR TLP field comparison match (see ATTR field of the 'iATU Control 1 Register') occurs for address translation to proceed. Note: This register field is sticky." "0,1" newline bitfld.long 0x0 15. "TD_MATCH_EN,TD Match Enable. Ensures that a successful TD TLP field comparison match (see TD field of the 'iATU Control 1 Register') occurs for address translation to proceed. Note: This register field is sticky." "0,1" newline bitfld.long 0x0 14. "TC_MATCH_EN,TC Match Enable. Ensures that a successful TC TLP field comparison match (see TC field of the 'iATU Control 1 Register') occurs for address translation to proceed. Note: This register field is sticky." "0,1" newline bitfld.long 0x0 13. "MSG_TYPE_MATCH_MODE,Message Type Match Mode. When enabled and if single address location translate enable is set then inbound TLPs of type MSG/MSGd which match the type field of the iatu_region_ctrl_1_OFF_inbound register (=>TYPE[4:3]=2'b10) will be.." "0,1" newline bitfld.long 0x0 8.--10. "BAR_NUM,BAR Number. When the BAR number of an inbound MEM or IO TLP ' that is matched by the normal internal BAR address matching mechanism ' is the same as this field address translation proceeds (when all other enabled field-matches are successful)." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x0 0.--7. 1. "MSG_CODE,MSG TLPs: (Message Code). When the TYPE field of an inbound Msg/MsgD TLP is matched to this value then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the 'Message Code Match.." repeat.end repeat 8. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 )(list 0x0 0x200 0x400 0x600 0x800 0xA00 0xC00 0xE00 ) group.long ($2+0x108+0xC0000)++0x3 line.long 0x0 "IATU_LWR_BASE_ADDR_OFF_INBOUND_$1,iATU Lower Base Address Register. The CX_ATU_MIN_REGION_SIZE configuration parameter (Value Range: 4 kB. 8 kB. 16 kB. 32 kB. 64 kB defaults to 64 kB) specifies the minimum size of an address translation region. For.." hexmask.long.tbyte 0x0 12.--31. 1. "LWR_BASE_RW,Forms bits [31:n] of the start address of the address region to be translated. n is log2(CX_ATU_MIN_REGION_SIZE) Note: This register field is sticky." newline hexmask.long.word 0x0 0.--11. 1. "LWR_BASE_HW,Forms bits [n-1:0] of the start address of the address region to be translated. The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary so these bits are always 0. A write to this location is ignored by the PCIe controller." repeat.end repeat 8. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 )(list 0x0 0x200 0x400 0x600 0x800 0xA00 0xC00 0xE00 ) group.long ($2+0x10C+0xC0000)++0x3 line.long 0x0 "IATU_UPPER_BASE_ADDR_OFF_INBOUND_$1,iATU Upper Base Address Register." hexmask.long 0x0 0.--31. 1. "UPPER_BASE_RW,Forms bits [63:32] of the start (and end) address of the address region to be translated. Note: This register field is sticky." repeat.end repeat 8. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 )(list 0x0 0x200 0x400 0x600 0x800 0xA00 0xC00 0xE00 ) group.long ($2+0x110+0xC0000)++0x3 line.long 0x0 "IATU_LIMIT_ADDR_OFF_INBOUND_$1,iATU Limit Address Register." hexmask.long.tbyte 0x0 12.--31. 1. "LIMIT_ADDR_RW,Forms upper bits of the end address of the address region to be translated. Note: This register field is sticky." newline hexmask.long.word 0x0 0.--11. 1. "LIMIT_ADDR_HW,Forms lower bits of the end address of the address region to be translated. The end address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary so these bits are always all ones. A write to this location is ignored by the PCIe.." repeat.end repeat 8. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 )(list 0x0 0x200 0x400 0x600 0x800 0xA00 0xC00 0xE00 ) group.long ($2+0x114+0xC0000)++0x3 line.long 0x0 "IATU_LWR_TARGET_ADDR_OFF_INBOUND_$1,iATU Lower Target Address Register." hexmask.long.tbyte 0x0 12.--31. 1. "LWR_TARGET_RW,Forms MSB's of the Lower Target part of the new address of the translated region. These bits are always '0'. - Field size depends on log2(CX_ATU_MIN_REGION_SIZE) in address match mode. - Field size depends on log2(BAR_MASK+1) in BAR match.." newline hexmask.long.word 0x0 0.--11. 1. "LWR_TARGET_HW,Forms the LSB's of the Lower Target part of the new address of the translated region. The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary (in address match mode); and to the Bar size boundary (in BAR match mode) so.." repeat.end repeat 8. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 )(list 0x0 0x200 0x400 0x600 0x800 0xA00 0xC00 0xE00 ) group.long ($2+0x118+0xC0000)++0x3 line.long 0x0 "IATU_UPPER_TARGET_ADDR_OFF_INBOUND_$1,iATU Upper Target Address Register." hexmask.long 0x0 0.--31. 1. "UPPER_TARGET_RW,Forms bits [63:32] of the start address (Upper Target part) of the new address of the translated region. In systems with a 32-bit address space this register is not used and therefore writing to this register has no effect. Note: This.." repeat.end repeat 8. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 )(list 0x0 0x200 0x400 0x600 0x800 0xA00 0xC00 0xE00 ) group.long ($2+0x11C+0xC0000)++0x3 line.long 0x0 "IATU_REGION_CTRL_3_OFF_INBOUND_$1,iATU Region Control 3 Register." rbitfld.long 0x0 31. "VF_ACTIVE,Reserved. Not used." "0,1" newline hexmask.long 0x0 3.--30. 1. "RSVDP_VF_NUMBER,Reserved for future use." newline bitfld.long 0x0 0.--2. "VF_NUMBER,Virtual Function Number. When the Address and BAR matching logic in the controller indicates that a MEM-I/O transaction matches a BAR in the virtual function corresponding to this value then address translation proceeds. This check is only.." "0,1,2,3,4,5,6,7" repeat.end tree.end tree "PF0_PORT_LOGIC (Port Logic)" group.long (0x0+0x700)++0x27 line.long 0x0 "ACK_LATENCY_TIMER_OFF,Ack Latency Timer and Replay Timer Register." hexmask.long.word 0x0 16.--31. 1. "REPLAY_TIME_LIMIT,Replay Timer Limit. The replay timer expires when it reaches this limit. The controller initiates a replay upon reception of a NAK or when the replay timer expires. For more details see 'Transmit Replay'. You can modify the effective.." newline hexmask.long.word 0x0 0.--15. 1. "ROUND_TRIP_LATENCY_TIME_LIMIT,Ack Latency Timer Limit. The Ack latency timer expires when it reaches this limit. For more details see 'Ack Scheduling'. You can modify the effective timer limit with the TIMER_MOD_ACK_NAK field of the.." line.long 0x4 "VENDOR_SPEC_DLLP_OFF,Vendor Specific DLLP Register." hexmask.long 0x4 0.--31. 1. "VENDOR_SPEC_DLLP,Vendor Specific DLLP Register. Used to send a specific PCI Express DLLP. Your application writes the 8-bit DLLP Type and 24-bits of Payload data into this register then sets the field VENDOR_SPECIFIC_DLLP_REQ of PORT_LINK_CTRL_OFF to.." line.long 0x8 "PORT_FORCE_OFF,Port Force Link Register." hexmask.long.byte 0x8 24.--31. 1. "RSVDP_24,Reserved for future use." newline bitfld.long 0x8 23. "DO_DESKEW_FOR_SRIS,Use the transitions from TS2 to Logical Idle Symbol SKP OS to Logical Idle Symbol EIEOS to Logical Idle Symbol and FTS Sequence to SKP OS to do deskew instead of using received SKP OS or TS1 to TS2 transition if DO_DESKEW_FOR_SRIS.." "0,1" newline rbitfld.long 0x8 22. "RSVDP_22,Reserved for future use." "0,1" newline hexmask.long.byte 0x8 16.--21. 1. "LINK_STATE,Forced LTSSM State. The LTSSM state that the controller is forced to when you set the FORCE_EN bit (Force Link). LTSSM state encoding is defined by the lts_state variable in workspace/src/Layer1/smlh_ltssm.v. Note: This register field is sticky." newline bitfld.long 0x8 15. "FORCE_EN,Force Link. The controller supports a testing and debug capability to allow your software to force the LTSSM state machine into a specific state and to force the controller to transmit a specific Link Command. Asserting this bit triggers the.." "0,1" newline rbitfld.long 0x8 12.--14. "RSVDP_12,Reserved for future use." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x8 8.--11. 1. "FORCED_LTSSM,Forced Link Command. The link command that the controller is forced to transmit when you set FORCE_EN bit (Force Link). Link command encoding is defined by the ltssm_cmd variable in workspace/src/Layer1/smlh_ltssm.v. Note: This register.." newline hexmask.long.byte 0x8 0.--7. 1. "LINK_NUM,Link Number. Not used for endpoint. Not used for M-PCIe. Note: This register field is sticky." line.long 0xC "ACK_F_ASPM_CTRL_OFF,Ack Frequency and L0-L1 ASPM Control Register." rbitfld.long 0xC 31. "RSVDP_31,Reserved for future use." "0,1" newline bitfld.long 0xC 30. "ENTER_ASPM,ASPM L1 Entry Control. - 1: Controller enters ASPM L1 after a period in which it has been idle. - 0: Controller enters ASPM L1 only after idle period during which both receive and transmit are in L0s. Note: This register field is sticky." "Controller enters ASPM L1 only after idle period..,Controller enters ASPM L1 after a period in.." newline bitfld.long 0xC 27.--29. "L1_ENTRANCE_LATENCY,L1 Entrance Latency. Value range is: - 000: 1 us - 001: 2 us - 010: 4 us - 011: 8 us - 100: 16 us - 101: 32 us - 110 or 111: 64 us Note: Programming this timer with a value greater that 32us has no effect unless extended sync is used.." "0,1,2,3,4,5,6,7" newline bitfld.long 0xC 24.--26. "L0S_ENTRANCE_LATENCY,L0s Entrance Latency. Values correspond to: - 000: 1 us - 001: 2 us - 010: 3 us - 011: 4 us - 100: 5 us - 101: 6 us - 110 or 111: 7 us This field is applicable to STALL while in L0 for M-PCIe. Note: This register field is sticky." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0xC 16.--23. 1. "COMMON_CLK_N_FTS,Common Clock N_FTS. This is the N_FTS when common clock is used. The number of Fast Training Sequence ordered sets to be transmitted when transitioning from L0s to L0. The maximum number of FTS ordered-sets that a component can request.." newline hexmask.long.byte 0xC 8.--15. 1. "ACK_N_FTS,N_FTS. The number of Fast Training Sequence ordered sets to be transmitted when transitioning from L0s to L0. The maximum number of FTS ordered-sets that a component can request is 255. The controller does not support a value of zero; a value.." newline hexmask.long.byte 0xC 0.--7. 1. "ACK_FREQ,Ack Frequency. The controller accumulates the number of pending ACKs specified here (up to 255) before scheduling an ACK DLLP. - 0: Indicates that this Ack Frequency Counter feature is turned off. The controller generates a low-priority ACK.." line.long 0x10 "PORT_LINK_CTRL_OFF,Port Link Control Register." hexmask.long.byte 0x10 28.--31. 1. "RSVDP_28,Reserved for future use." newline bitfld.long 0x10 27. "TRANSMIT_LANE_REVERSALE_ENABLE,TRANSMIT_LANE_REVERSALE_ENABLE is an internally reserved field. Do not use. Note: This register field is sticky." "0,1" newline bitfld.long 0x10 26. "EXTENDED_SYNCH,EXTENDED_SYNCH is an internally reserved field. Do not use. Note: This register field is sticky." "0,1" newline bitfld.long 0x10 25. "CORRUPT_LCRC_ENABLE,CORRUPT_LCRC_ENABLE is an internally reserved field. Do not use. Note: This register field is sticky." "0,1" newline bitfld.long 0x10 24. "BEACON_ENABLE,BEACON_ENABLE is an internally reserved field. Do not use. Note: This register field is sticky." "0,1" newline hexmask.long.byte 0x10 16.--21. 1. "LINK_CAPABLE,Link Mode Enable. Sets the number of lanes in the link that you want to connect to the link partner. When you have unused lanes in your system then you must change the value in this register to reflect the number of lanes. You must also.." newline hexmask.long.byte 0x10 12.--15. 1. "RSVDP_12,Reserved for future use." newline hexmask.long.byte 0x10 8.--11. 1. "LINK_RATE,LINK_RATE is an internally reserved field. Do not use. Note: This register field is sticky." newline bitfld.long 0x10 7. "FAST_LINK_MODE,Fast Link Mode. Sets all internal LTSSM millisecond timers to Fast Mode for speeding up simulation. Forces the LTSSM training (link initialization) to use shorter time-outs and to link up faster. The default scaling factor can be changed.." "0,1" newline bitfld.long 0x10 6. "LINK_DISABLE,LINK_DISABLE is an internally reserved field. Do not use. Note: This register field is sticky." "0,1" newline bitfld.long 0x10 5. "DLL_LINK_EN,DLL Link Enable. Enables link initialization. When DLL Link Enable =0 the controller does not transmit InitFC DLLPs and does not establish a link. Note: This register field is sticky." "0,1" newline rbitfld.long 0x10 4. "RSVDP_4,Reserved for future use." "0,1" newline bitfld.long 0x10 3. "RESET_ASSERT,Reset Assert. Triggers a recovery and forces the LTSSM to the hot reset state (downstream port only). Note: This register field is sticky." "0,1" newline bitfld.long 0x10 2. "LOOPBACK_ENABLE,Loopback Enable. Turns on loopback. For more details see 'Loopback'. For M-PCIe to force the master to enter Digital Loopback mode you must set this field to '1' during Configuration.start state(initial discovery/configuration). M-PCIe.." "0,1" newline bitfld.long 0x10 1. "SCRAMBLE_DISABLE,Scramble Disable. Turns off data scrambling. Note: This register field is sticky." "0,1" newline bitfld.long 0x10 0. "VENDOR_SPECIFIC_DLLP_REQ,Vendor Specific DLLP Request. When software writes a '1' to this bit the controller transmits the DLLP contained in the VENDOR_SPEC_DLLP field of VENDOR_SPEC_DLLP_OFF. Reading from this self-clearing register field always.." "0,1" line.long 0x14 "LANE_SKEW_OFF,Lane Skew Register." bitfld.long 0x14 31. "DISABLE_LANE_TO_LANE_DESKEW,Disable Lane-to-Lane Deskew. Causes the controller to disable the internal Lane-to-Lane deskew logic. Note: This register field is sticky." "0,1" newline hexmask.long.byte 0x14 27.--30. 1. "IMPLEMENT_NUM_LANES,Implementation-specific Number of Lanes. Set the implementation-specific number of lanes. Allowed values are: - 4'b0000: 1 lane - 4'b0001: 2 lanes - 4'b0011: 4 lanes - 4'b0111: 8 lanes - 4'b1111: 16 lanes The number of lanes to be.." newline bitfld.long 0x14 26. "ELASTIC_BUFFER_MODE,Selects Elasticity Buffer operating mode: 0: Nominal Half Full Buffer mode 1: Nominal Empty Buffer Mode Note: This register field is sticky." "Nominal Half Full Buffer mode,Nominal Empty Buffer Mode" newline bitfld.long 0x14 25. "ACK_NAK_DISABLE,Ack/Nak Disable. Prevents the controller from sending ACK and NAK DLLPs. Note: This register field is sticky." "0,1" newline bitfld.long 0x14 24. "FLOW_CTRL_DISABLE,Flow Control Disable. Prevents the controller from sending FC DLLPs. Note: This register field is sticky." "0,1" newline hexmask.long.tbyte 0x14 0.--23. 1. "INSERT_LANE_SKEW,INSERT_LANE_SKEW is an internally reserved field. Do not use. Note: This register field is sticky." line.long 0x18 "TIMER_CTRL_MAX_FUNC_NUM_OFF,Timer Control and Max Function Number Register." rbitfld.long 0x18 31. "RSVDP_31,Reserved for future use." "0,1" newline bitfld.long 0x18 29.--30. "FAST_LINK_SCALING_FACTOR,Fast Link Timer Scaling Factor. Sets the scaling factor of LTSSM timer when FAST_LINK_MODE field in PORT_LINK_CTRL_OFF is set to '1'. - 0: Scaling Factor is 1024 (1ms is 1us *a) - 1: Scaling Factor is 256 (1ms is 4us) - 2:.." "Scaling Factor is 1024,Scaling Factor is 256,Scaling Factor is 64,Scaling Factor is 16" newline hexmask.long.byte 0x18 24.--28. 1. "UPDATE_FREQ_TIMER,UPDATE_FREQ_TIMER is an internally reserved field. Do not use. Note: This register field is sticky." newline hexmask.long.byte 0x18 19.--23. 1. "TIMER_MOD_ACK_NAK,Ack Latency Timer Modifier. Increases the timer value for the Ack latency timer in increments of 64 clock cycles. A value of '0' represents no modification to the timer value. For more details see the ROUND_TRIP_LATENCY_TIME_LIMIT.." newline hexmask.long.byte 0x18 14.--18. 1. "TIMER_MOD_REPLAY_TIMER,Replay Timer Limit Modifier. Increases the time-out value for the replay timer in increments of 64 clock cycles at Gen1 or Gen2 speed and in increments of 256 clock cycles at Gen3 speed. A value of '0' represents no modification.." newline hexmask.long.byte 0x18 8.--13. 1. "RSVDP_8,Reserved for future use." newline hexmask.long.byte 0x18 0.--7. 1. "MAX_FUNC_NUM,Maximum function number that can be used in a request. Configuration requests targeted at function numbers above this value are returned with UR (unsupported request). Note: This register field is sticky." line.long 0x1C "SYMBOL_TIMER_FILTER_1_OFF,Symbol Timer Register and Filter Mask 1 Register. The Filter Mask 1 Register modifies the RADM filtering and error handling rules. For more details. see the 'Receive Filtering' section. In each case. '0' applies the associated.." hexmask.long.word 0x1C 16.--31. 1. "MASK_RADM_1,Filter Mask 1. The Filter Mask 1 Register modifies the RADM filtering and error handling rules. For more details see the 'Receive Filtering' section. In each case '0' applies the associated filtering rule and '1' masks the associated.." newline bitfld.long 0x1C 15. "DISABLE_FC_WD_TIMER,Disable FC Watchdog Timer. Note: This register field is sticky." "0,1" newline hexmask.long.byte 0x1C 11.--14. 1. "EIDLE_TIMER,EIDLE_TIMER is an internally reserved field. Do not use. Note: This register field is sticky." newline hexmask.long.word 0x1C 0.--10. 1. "SKP_INT_VAL,SKP Interval Value. The number of symbol times to wait between transmitting SKP ordered sets. Note that the controller actually waits the number of symbol times in this register plus 1 between transmitting SKP ordered sets. Your application.." line.long 0x20 "FILTER_MASK_2_OFF,Filter Mask 2 Register. This register modifies the RADM filtering and error handling rules. For more details. see the 'Receive Filtering' section. In each case. '0' applies the associated filtering rule and '1' masks the associated.." hexmask.long 0x20 0.--31. 1. "MASK_RADM_2,Filter Mask 2. This field modifies the RADM filtering and error handling rules. For more details see the 'Receive Filtering' section. In each case '0' applies the associated filtering rule and '1' masks the associated filtering rule." line.long 0x24 "AMBA_MUL_OB_DECOMP_NP_SUB_REQ_CTRL_OFF,AMBA Multiple Outbound Decomposed NP SubRequests Control Register." hexmask.long 0x24 1.--31. 1. "RSVDP_1,Reserved for future use." newline bitfld.long 0x24 0. "OB_RD_SPLIT_BURST_EN,Enable AMBA Multiple Outbound Decomposed NP SubRequests. This bit when set to '0' disables the possibility of having multiple outstanding non-posted requests that were derived from decomposition of an outbound AMBA request. For more.." "0,1" rgroup.long (0x28+0x700)++0x13 line.long 0x0 "PL_DEBUG0_OFF,Debug Register 0" hexmask.long 0x0 0.--31. 1. "DEB_REG_0,The value on cxpl_debug_info[31:0]." line.long 0x4 "PL_DEBUG1_OFF,Debug Register 1" hexmask.long 0x4 0.--31. 1. "DEB_REG_1,The value on cxpl_debug_info[63:32]." line.long 0x8 "TX_P_FC_CREDIT_STATUS_OFF,Transmit Posted FC Credit Status" hexmask.long.word 0x8 20.--31. 1. "RSVDP_TX_P_FC_CREDIT_STATUS,Reserved for future use." newline hexmask.long.byte 0x8 12.--19. 1. "TX_P_HEADER_FC_CREDIT,Transmit Posted Header FC Credits. The posted Header credits advertised by the receiver at the other end of the link updated with each UpdateFC DLLP. Default value depends on the number of advertised credits for header and data.." newline hexmask.long.word 0x8 0.--11. 1. "TX_P_DATA_FC_CREDIT,Transmit Posted Data FC Credits. The posted Data credits advertised by the receiver at the other end of the link updated with each UpdateFC DLLP. Default value depends on the number of advertised credits for header and data Scaled.." line.long 0xC "TX_NP_FC_CREDIT_STATUS_OFF,Transmit Non-Posted FC Credit Status" hexmask.long.word 0xC 20.--31. 1. "RSVDP_TX_NP_FC_CREDIT_STATUS,Reserved for future use." newline hexmask.long.byte 0xC 12.--19. 1. "TX_NP_HEADER_FC_CREDIT,Transmit Non-Posted Header FC Credits. The non-posted Header credits advertised by the receiver at the other end of the link updated with each UpdateFC DLLP. Default value depends on the number of advertised credits for header and.." newline hexmask.long.word 0xC 0.--11. 1. "TX_NP_DATA_FC_CREDIT,Transmit Non-Posted Data FC Credits. The non-posted Data credits advertised by the receiver at the other end of the link updated with each UpdateFC DLLP. Default value depends on the number of advertised credits for header and data.." line.long 0x10 "TX_CPL_FC_CREDIT_STATUS_OFF,Transmit Completion FC Credit Status" hexmask.long.word 0x10 20.--31. 1. "RSVDP_TX_CPL_FC_CREDIT_STATUS,Reserved for future use." newline hexmask.long.byte 0x10 12.--19. 1. "TX_CPL_HEADER_FC_CREDIT,Transmit Completion Header FC Credits. The Completion Header credits advertised by the receiver at the other end of the link updated with each UpdateFC DLLP. Default value depends on the number of advertised credits for header.." newline hexmask.long.word 0x10 0.--11. 1. "TX_CPL_DATA_FC_CREDIT,Transmit Completion Data FC Credits. The Completion Data credits advertised by the receiver at the other end of the link updated with each UpdateFC DLLP. Default value depends on the number of advertised credits for header and data.." group.long (0x3C+0x700)++0x3 line.long 0x0 "QUEUE_STATUS_OFF,Queue Status" bitfld.long 0x0 31. "TIMER_MOD_FLOW_CONTROL_EN,FC Latency Timer Override Enable. When this bit is set the value from the 'FC Latency Timer Override Value' field in this register will override the FC latency timer value that the controller calculates according to the PCIe.." "0,1" newline rbitfld.long 0x0 29.--30. "RSVDP_29,Reserved for future use." "0,1,2,3" newline hexmask.long.word 0x0 16.--28. 1. "TIMER_MOD_FLOW_CONTROL,FC Latency Timer Override Value. When you set the 'FC Latency Timer Override Enable' in this register the value in this field will override the FC latency timer value that the controller calculates according to the PCIe.." newline rbitfld.long 0x0 13. "RX_SERIALIZATION_Q_NON_EMPTY,Receive Serialization Queue Not Empty. Indicates there is data in the serialization queue." "0,1" newline hexmask.long.word 0x0 4.--12. 1. "RSVDP_4,Reserved for future use." newline bitfld.long 0x0 3. "RX_QUEUE_OVERFLOW,Receive Credit Queue Overflow. Indicates insufficient buffer space available to write to the P/NP/CPL credit queue." "0,1" newline rbitfld.long 0x0 2. "RX_QUEUE_NON_EMPTY,Receive Credit Queue Not Empty. Indicates there is data in one or more of the receive buffers." "0,1" newline rbitfld.long 0x0 1. "TX_RETRY_BUFFER_NE,Transmit Retry Buffer Not Empty. Indicates that there is data in the transmit retry buffer." "0,1" newline rbitfld.long 0x0 0. "RX_TLP_FC_CREDIT_NON_RETURN,Received TLP FC Credits Not Returned. Indicates that the controller has received a TLP but has not yet sent an UpdateFC DLLP indicating that the credits for that TLP have been restored by the receiver at the other end of the.." "0,1" rgroup.long (0x40+0x700)++0x7 line.long 0x0 "VC_TX_ARBI_1_OFF,VC Transmit Arbitration Register 1" hexmask.long.byte 0x0 24.--31. 1. "WRR_WEIGHT_VC_3,WRR Weight for VC3. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R" newline hexmask.long.byte 0x0 16.--23. 1. "WRR_WEIGHT_VC_2,WRR Weight for VC2. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R" newline hexmask.long.byte 0x0 8.--15. 1. "WRR_WEIGHT_VC_1,WRR Weight for VC1. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R" newline hexmask.long.byte 0x0 0.--7. 1. "WRR_WEIGHT_VC_0,WRR Weight for VC0. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R" line.long 0x4 "VC_TX_ARBI_2_OFF,VC Transmit Arbitration Register 2" hexmask.long.byte 0x4 24.--31. 1. "WRR_WEIGHT_VC_7,WRR Weight for VC7. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R" newline hexmask.long.byte 0x4 16.--23. 1. "WRR_WEIGHT_VC_6,WRR Weight for VC6. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R" newline hexmask.long.byte 0x4 8.--15. 1. "WRR_WEIGHT_VC_5,WRR Weight for VC5. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R" newline hexmask.long.byte 0x4 0.--7. 1. "WRR_WEIGHT_VC_4,WRR Weight for VC4. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R" group.long (0x48+0x700)++0xB line.long 0x0 "VC0_P_RX_Q_CTRL_OFF,Segmented-Buffer VC0 Posted Receive Queue Control." bitfld.long 0x0 31. "VC_ORDERING_RX_Q,VC Ordering for Receive Queues. Determines the VC ordering rule for the receive queues used only in the segmented-buffer configuration: - 1: Strict ordering higher numbered VCs have higher priority - 0: Round robin Note: This register.." "Round robin,Strict ordering" newline bitfld.long 0x0 30. "TLP_TYPE_ORDERING_VC0,TLP Type Ordering for VC0. Determines the TLP type ordering rule for VC0 receive queues used only in the segmented-buffer configuration: - 1: PCIe ordering rules (recommended) - 0: Strict ordering: posted completion then.." "Strict ordering: posted,PCIe ordering rules" newline bitfld.long 0x0 28.--29. "RESERVED5,Reserved. Note: This register field is sticky." "0,1,2,3" newline bitfld.long 0x0 26.--27. "VC0_P_DATA_SCALE,VC0 Scale Posted Data Credites. Note: This register field is sticky." "0,1,2,3" newline bitfld.long 0x0 24.--25. "VC0_P_HDR_SCALE,VC0 Scale Posted Header Credites. Note: This register field is sticky." "0,1,2,3" newline bitfld.long 0x0 21.--23. "VC0_P_TLP_Q_MODE,Reserved. Note: This register field is sticky." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 20. "RESERVED4,Reserved. Note: This register field is sticky." "0,1" newline hexmask.long.byte 0x0 12.--19. 1. "VC0_P_HEADER_CREDIT,VC0 Posted Header Credits. The number of initial posted header credits for VC0 used only in the segmented-buffer configuration. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R (sticky) Note: This.." newline hexmask.long.word 0x0 0.--11. 1. "VC0_P_DATA_CREDIT,VC0 Posted Data Credits. The number of initial posted data credits for VC0 used only in the segmented-buffer configuration. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R (sticky) Note: This.." line.long 0x4 "VC0_NP_RX_Q_CTRL_OFF,Segmented-Buffer VC0 Non-Posted Receive Queue Control." hexmask.long.byte 0x4 28.--31. 1. "RESERVED7,Reserved. Note: This register field is sticky." newline bitfld.long 0x4 26.--27. "VC0_NP_DATA_SCALE,VC0 Scale Non-Posted Data Credites. Note: This register field is sticky." "0,1,2,3" newline bitfld.long 0x4 24.--25. "VC0_NP_HDR_SCALE,VC0 Scale Non-Posted Header Credites. Note: This register field is sticky." "0,1,2,3" newline bitfld.long 0x4 21.--23. "VC0_NP_TLP_Q_MODE,Reserved. Note: This register field is sticky." "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 20. "RESERVED6,Reserved. Note: This register field is sticky." "0,1" newline hexmask.long.byte 0x4 12.--19. 1. "VC0_NP_HEADER_CREDIT,VC0 Non-Posted Header Credits. The number of initial non-posted header credits for VC0 used only in the segmented-buffer configuration. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R (sticky).." newline hexmask.long.word 0x4 0.--11. 1. "VC0_NP_DATA_CREDIT,VC0 Non-Posted Data Credits. The number of initial non-posted data credits for VC0 used only in the segmented-buffer configuration. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R (sticky) Note:.." line.long 0x8 "VC0_CPL_RX_Q_CTRL_OFF,Segmented-Buffer VC0 Completion Receive Queue Control." hexmask.long.byte 0x8 28.--31. 1. "RESERVED9,Reserved. Note: This register field is sticky." newline bitfld.long 0x8 26.--27. "VC0_CPL_DATA_SCALE,VC0 Scale CPL Data Credites. Note: This register field is sticky." "0,1,2,3" newline bitfld.long 0x8 24.--25. "VC0_CPL_HDR_SCALE,VC0 Scale CPL Header Credites. Note: This register field is sticky." "0,1,2,3" newline bitfld.long 0x8 21.--23. "VC0_CPL_TLP_Q_MODE,Reserved. Note: This register field is sticky." "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 20. "RESERVED8,Reserved. Note: This register field is sticky." "0,1" newline hexmask.long.byte 0x8 12.--19. 1. "VC0_CPL_HEADER_CREDIT,VC0 Completion Header Credits. The number of initial Completion header credits for VC0 used only in the segmented-buffer configuration. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R (sticky).." newline hexmask.long.word 0x8 0.--11. 1. "VC0_CPL_DATA_CREDIT,VC0 Completion Data Credits. The number of initial Completion data credits for VC0 used only in the segmented-buffer configuration. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R (sticky) Note:.." group.long (0x10C+0x700)++0x3 line.long 0x0 "GEN2_CTRL_OFF,This register is used to control various functions of the controller related to link training. lane reversal. and equalization." rbitfld.long 0x0 31. "RSVDP_31,Reserved for future use." "0,1" newline bitfld.long 0x0 30. "FORCE_LANE_FLIP,Enable to force the LANE_UNDER_TEST physical lane flips to logical lane 0. All the other physical lanes are turned off. The LINK_CAPABLE register must be set to 1 and only x1 link can be formed if the FORCE_LANE_FLIP register is set to 1." "0,1" newline hexmask.long.byte 0x0 24.--27. 1. "LANE_UNDER_TEST,The Lane Under Test is the lane for Forced Lane Flip or for Loopback Eq. The value is from 0 to CX_NL. Only one lane is configured each time. The default of this field is the CX_DEFAULT_LANE_UNDER_TEST configuration parameter. This field.." newline rbitfld.long 0x0 22.--23. "RSVDP_22,Reserved for future use." "0,1,2,3" newline bitfld.long 0x0 21. "GEN1_EI_INFERENCE,Electrical Idle Inference Mode at Gen1 Rate. Programmable mode to determine inferred electrical idle (EI) in Recovery.Speed or Loopback.Active (as slave) state at Gen1 speed by looking for a '1' value on RxElecIdle instead of looking.." "Use RxElecIdle signal to infer Electrical Idle,Use RxValid signal to infer Electrical Idle" newline bitfld.long 0x0 20. "SEL_DEEMPHASIS,Used to set the de-emphasis level for upstream ports. This bit selects the level of de-emphasis the link operates at. - 0: -6 dB - 1: -3.5 dB This field is reserved (fixed to '0') for M-PCIe. Note: The access attributes of this field are.." "0,1" newline bitfld.long 0x0 19. "CONFIG_TX_COMP_RX,Config Tx Compliance Receive Bit. When set to 1 signals LTSSM to transmit TS ordered sets with the compliance receive bit assert (equal to '1'). This field is reserved (fixed to '0') for M-PCIe. Note: The access attributes of this.." "0,1" newline bitfld.long 0x0 18. "CONFIG_PHY_TX_CHANGE,Config PHY Tx Swing. Controls the PHY transmitter voltage swing level. The controller drives the mac_phy_txswing output from this register bit field. - 0: Full Swing - 1: Low Swing This field is reserved (fixed to '0') for M-PCIe." "Full Swing,Low Swing" newline bitfld.long 0x0 17. "DIRECT_SPEED_CHANGE,Directed Speed Change. Writing '1' to this field instructs the LTSSM to initiate a speed change to Gen2 or Gen3 after the link is initialized at Gen1 speed. When the speed change occurs the controller will clear the contents of this.." "0,1" newline bitfld.long 0x0 16. "AUTO_LANE_FLIP_CTRL_EN,Enable Auto flipping of the lanes. You must set the CX_AUTO_LANE_FLIP_CTRL_EN configuration parameter to include the hardware for this feature in the controller. For more details see the 'Lane Reversal' appendix in the Databook." "0,1" newline bitfld.long 0x0 13.--15. "PRE_DET_LANE,Predetermined Lane for Auto Flip. This field defines which physical lane is connected to logical Lane0 by the flip operation performed in Detect. This field is used to restrict the receiver detect procedure to a particular lane when the.." "LANE0,LANE1,LANE3,LANE7,LANE15,?,?,?" newline hexmask.long.byte 0x0 8.--12. 1. "NUM_OF_LANES,Predetermined Number of Lanes. Defines the number of lanes which are connected and not bad. Used to limit the effective link width to ignore 'broken' or 'unused' lanes that detect a receiver. Indicates the number of lanes to check for exit.." newline hexmask.long.byte 0x0 0.--7. 1. "FAST_TRAINING_SEQ,Sets the Number of Fast Training Sequences (N_FTS) that the controller advertises as its N_FTS during Gen2 or Gen3 link training. This value is used to inform the link partner about the PHY's ability to recover synchronization after a.." rgroup.long (0x110+0x700)++0x3 line.long 0x0 "PHY_STATUS_OFF,PHY Status Register. Memory mapped register from phy_cfg_status GPIO input pins." hexmask.long 0x0 0.--31. 1. "PHY_STATUS,PHY Status. Data received directly from the phy_cfg_status bus. These is a GPIO register reflecting the values on the static phy_cfg_status input signals. The usage is left completely to the user and does not in any way influence controller.." group.long (0x114+0x700)++0x3 line.long 0x0 "PHY_CONTROL_OFF,PHY Control Register. Memory mapped register to cfg_phy_control GPIO output pins." hexmask.long 0x0 0.--31. 1. "PHY_CONTROL,PHY Control. Data sent directly to the cfg_phy_control bus. These is a GPIO register driving the values on the static cfg_phy_control output signals. The usage is left completely to the user and does not in any way influence controller.." group.long (0x11C+0x700)++0x77 line.long 0x0 "TRGT_MAP_CTRL_OFF,Programmable Target Map Control Register." hexmask.long.word 0x0 21.--31. 1. "TARGET_MAP_RESERVED_21_31,Reserved. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R (sticky)" newline hexmask.long.byte 0x0 16.--20. 1. "TARGET_MAP_INDEX,The number of the PF Function on which the Target Values are set. This register does not respect the Byte Enable setting. any write will affect all register bits." newline rbitfld.long 0x0 13.--15. "TARGET_MAP_RESERVED_13_15,Reserved. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R (sticky)" "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x0 7.--12. 1. "TARGET_MAP_VF,Target Values for each BAR on the VF Function selected by the index number. This register does not respect the Byte Enable setting. any write will affect all register bits." newline bitfld.long 0x0 6. "TARGET_MAP_ROM,Target Value for the ROM page of the PF Function selected by the index number. This register does not respect the Byte Enable setting. any write will affect all register bits." "0,1" newline hexmask.long.byte 0x0 0.--5. 1. "TARGET_MAP_PF,Target Values for each BAR on the PF Function selected by the index number. This register does not respect the Byte Enable setting. any write will affect all register bits." line.long 0x4 "MSI_CTRL_ADDR_OFF,Integrated MSI Reception Module (iMRM) Address Register." hexmask.long 0x4 0.--31. 1. "MSI_CTRL_ADDR,Integrated MSI Reception Module Address. System specified address for MSI memory write transaction termination. Within the AXI Bridge every received Memory Write request is examined to see if it targets the MSI Address that has been.." line.long 0x8 "MSI_CTRL_UPPER_ADDR_OFF,Integrated MSI Reception Module Upper Address Register." hexmask.long 0x8 0.--31. 1. "MSI_CTRL_UPPER_ADDR,Integrated MSI Reception Module Upper Address. System specified upper address for MSI memory write transaction termination. Allows functions to support a 64-bit MSI address. Note: This register field is sticky." line.long 0xC "MSI_CTRL_INT_0_EN_OFF,Integrated MSI Reception Module Interrupt#i Enable Register." hexmask.long 0xC 0.--31. 1. "MSI_CTRL_INT_0_EN,MSI Interrupt#i Enable. Specifies which interrupts are enabled. When an MSI is received from a disabled interrupt no status bit gets set in MSI controller interrupt status register. Each bit corresponds to a single MSI Interrupt.." line.long 0x10 "MSI_CTRL_INT_0_MASK_OFF,Integrated MSI Reception Module Interrupt#i Mask Register." hexmask.long 0x10 0.--31. 1. "MSI_CTRL_INT_0_MASK,MSI Interrupt#i Mask. Allows enabled interrupts to be masked. When an MSI is received for a masked interrupt the corresponding status bit gets set in the interrupt status register but the msi_ctrl_int output is not set HIGH. Each bit.." line.long 0x14 "MSI_CTRL_INT_0_STATUS_OFF,Integrated MSI Reception Module Interrupt#i Status Register." hexmask.long 0x14 0.--31. 1. "MSI_CTRL_INT_0_STATUS,MSI Interrupt#i Status. When an MSI is detected for EP#i one bit in this register is set. The decoding of the data payload of the MSI Memory Write request determines which bit gets set. A status is bit is cleared by writing a 1 to.." line.long 0x18 "MSI_CTRL_INT_1_EN_OFF,Integrated MSI Reception Module Interrupt#i Enable Register." hexmask.long 0x18 0.--31. 1. "MSI_CTRL_INT_1_EN,MSI Interrupt#i Enable. Specifies which interrupts are enabled. When an MSI is received from a disabled interrupt no status bit gets set in MSI controller interrupt status register. Each bit corresponds to a single MSI Interrupt.." line.long 0x1C "MSI_CTRL_INT_1_MASK_OFF,Integrated MSI Reception Module Interrupt#i Mask Register." hexmask.long 0x1C 0.--31. 1. "MSI_CTRL_INT_1_MASK,MSI Interrupt#i Mask. Allows enabled interrupts to be masked. When an MSI is received for a masked interrupt the corresponding status bit gets set in the interrupt status register but the msi_ctrl_int output is not set HIGH. Each bit.." line.long 0x20 "MSI_CTRL_INT_1_STATUS_OFF,Integrated MSI Reception Module Interrupt#i Status Register." hexmask.long 0x20 0.--31. 1. "MSI_CTRL_INT_1_STATUS,MSI Interrupt#i Status. When an MSI is detected for EP#i one bit in this register is set. The decoding of the data payload of the MSI Memory Write request determines which bit gets set. A status is bit is cleared by writing a 1 to.." line.long 0x24 "MSI_CTRL_INT_2_EN_OFF,Integrated MSI Reception Module Interrupt#i Enable Register." hexmask.long 0x24 0.--31. 1. "MSI_CTRL_INT_2_EN,MSI Interrupt#i Enable. Specifies which interrupts are enabled. When an MSI is received from a disabled interrupt no status bit gets set in MSI controller interrupt status register. Each bit corresponds to a single MSI Interrupt.." line.long 0x28 "MSI_CTRL_INT_2_MASK_OFF,Integrated MSI Reception Module Interrupt#i Mask Register." hexmask.long 0x28 0.--31. 1. "MSI_CTRL_INT_2_MASK,MSI Interrupt#i Mask. Allows enabled interrupts to be masked. When an MSI is received for a masked interrupt the corresponding status bit gets set in the interrupt status register but the msi_ctrl_int output is not set HIGH. Each bit.." line.long 0x2C "MSI_CTRL_INT_2_STATUS_OFF,Integrated MSI Reception Module Interrupt#i Status Register." hexmask.long 0x2C 0.--31. 1. "MSI_CTRL_INT_2_STATUS,MSI Interrupt#i Status. When an MSI is detected for EP#i one bit in this register is set. The decoding of the data payload of the MSI Memory Write request determines which bit gets set. A status is bit is cleared by writing a 1 to.." line.long 0x30 "MSI_CTRL_INT_3_EN_OFF,Integrated MSI Reception Module Interrupt#i Enable Register." hexmask.long 0x30 0.--31. 1. "MSI_CTRL_INT_3_EN,MSI Interrupt#i Enable. Specifies which interrupts are enabled. When an MSI is received from a disabled interrupt no status bit gets set in MSI controller interrupt status register. Each bit corresponds to a single MSI Interrupt.." line.long 0x34 "MSI_CTRL_INT_3_MASK_OFF,Integrated MSI Reception Module Interrupt#i Mask Register." hexmask.long 0x34 0.--31. 1. "MSI_CTRL_INT_3_MASK,MSI Interrupt#i Mask. Allows enabled interrupts to be masked. When an MSI is received for a masked interrupt the corresponding status bit gets set in the interrupt status register but the msi_ctrl_int output is not set HIGH. Each bit.." line.long 0x38 "MSI_CTRL_INT_3_STATUS_OFF,Integrated MSI Reception Module Interrupt#i Status Register." hexmask.long 0x38 0.--31. 1. "MSI_CTRL_INT_3_STATUS,MSI Interrupt#i Status. When an MSI is detected for EP#i one bit in this register is set. The decoding of the data payload of the MSI Memory Write request determines which bit gets set. A status is bit is cleared by writing a 1 to.." line.long 0x3C "MSI_CTRL_INT_4_EN_OFF,Integrated MSI Reception Module Interrupt#i Enable Register." hexmask.long 0x3C 0.--31. 1. "MSI_CTRL_INT_4_EN,MSI Interrupt#i Enable. Specifies which interrupts are enabled. When an MSI is received from a disabled interrupt no status bit gets set in MSI controller interrupt status register. Each bit corresponds to a single MSI Interrupt.." line.long 0x40 "MSI_CTRL_INT_4_MASK_OFF,Integrated MSI Reception Module Interrupt#i Mask Register." hexmask.long 0x40 0.--31. 1. "MSI_CTRL_INT_4_MASK,MSI Interrupt#i Mask. Allows enabled interrupts to be masked. When an MSI is received for a masked interrupt the corresponding status bit gets set in the interrupt status register but the msi_ctrl_int output is not set HIGH. Each bit.." line.long 0x44 "MSI_CTRL_INT_4_STATUS_OFF,Integrated MSI Reception Module Interrupt#i Status Register." hexmask.long 0x44 0.--31. 1. "MSI_CTRL_INT_4_STATUS,MSI Interrupt#i Status. When an MSI is detected for EP#i one bit in this register is set. The decoding of the data payload of the MSI Memory Write request determines which bit gets set. A status is bit is cleared by writing a 1 to.." line.long 0x48 "MSI_CTRL_INT_5_EN_OFF,Integrated MSI Reception Module Interrupt#i Enable Register." hexmask.long 0x48 0.--31. 1. "MSI_CTRL_INT_5_EN,MSI Interrupt#i Enable. Specifies which interrupts are enabled. When an MSI is received from a disabled interrupt no status bit gets set in MSI controller interrupt status register. Each bit corresponds to a single MSI Interrupt.." line.long 0x4C "MSI_CTRL_INT_5_MASK_OFF,Integrated MSI Reception Module Interrupt#i Mask Register." hexmask.long 0x4C 0.--31. 1. "MSI_CTRL_INT_5_MASK,MSI Interrupt#i Mask. Allows enabled interrupts to be masked. When an MSI is received for a masked interrupt the corresponding status bit gets set in the interrupt status register but the msi_ctrl_int output is not set HIGH. Each bit.." line.long 0x50 "MSI_CTRL_INT_5_STATUS_OFF,Integrated MSI Reception Module Interrupt#i Status Register." hexmask.long 0x50 0.--31. 1. "MSI_CTRL_INT_5_STATUS,MSI Interrupt#i Status. When an MSI is detected for EP#i one bit in this register is set. The decoding of the data payload of the MSI Memory Write request determines which bit gets set. A status is bit is cleared by writing a 1 to.." line.long 0x54 "MSI_CTRL_INT_6_EN_OFF,Integrated MSI Reception Module Interrupt#i Enable Register." hexmask.long 0x54 0.--31. 1. "MSI_CTRL_INT_6_EN,MSI Interrupt#i Enable. Specifies which interrupts are enabled. When an MSI is received from a disabled interrupt no status bit gets set in MSI controller interrupt status register. Each bit corresponds to a single MSI Interrupt.." line.long 0x58 "MSI_CTRL_INT_6_MASK_OFF,Integrated MSI Reception Module Interrupt#i Mask Register." hexmask.long 0x58 0.--31. 1. "MSI_CTRL_INT_6_MASK,MSI Interrupt#i Mask. Allows enabled interrupts to be masked. When an MSI is received for a masked interrupt the corresponding status bit gets set in the interrupt status register but the msi_ctrl_int output is not set HIGH. Each bit.." line.long 0x5C "MSI_CTRL_INT_6_STATUS_OFF,Integrated MSI Reception Module Interrupt#i Status Register." hexmask.long 0x5C 0.--31. 1. "MSI_CTRL_INT_6_STATUS,MSI Interrupt#i Status. When an MSI is detected for EP#i one bit in this register is set. The decoding of the data payload of the MSI Memory Write request determines which bit gets set. A status is bit is cleared by writing a 1 to.." line.long 0x60 "MSI_CTRL_INT_7_EN_OFF,Integrated MSI Reception Module Interrupt#i Enable Register." hexmask.long 0x60 0.--31. 1. "MSI_CTRL_INT_7_EN,MSI Interrupt#i Enable. Specifies which interrupts are enabled. When an MSI is received from a disabled interrupt no status bit gets set in MSI controller interrupt status register. Each bit corresponds to a single MSI Interrupt.." line.long 0x64 "MSI_CTRL_INT_7_MASK_OFF,Integrated MSI Reception Module Interrupt#i Mask Register." hexmask.long 0x64 0.--31. 1. "MSI_CTRL_INT_7_MASK,MSI Interrupt#i Mask. Allows enabled interrupts to be masked. When an MSI is received for a masked interrupt the corresponding status bit gets set in the interrupt status register but the msi_ctrl_int output is not set HIGH. Each bit.." line.long 0x68 "MSI_CTRL_INT_7_STATUS_OFF,Integrated MSI Reception Module Interrupt#i Status Register." hexmask.long 0x68 0.--31. 1. "MSI_CTRL_INT_7_STATUS,MSI Interrupt#i Status. When an MSI is detected for EP#i one bit in this register is set. The decoding of the data payload of the MSI Memory Write request determines which bit gets set. A status is bit is cleared by writing a 1 to.." line.long 0x6C "MSI_GPIO_IO_OFF,Integrated MSI Reception Module General Purpose IO Register." hexmask.long 0x6C 0.--31. 1. "MSI_GPIO_REG,MSI GPIO Register. The contents of this register drives the top-level GPIO msi_ctrl_io[31:0] Note: This register field is sticky." line.long 0x70 "CLOCK_GATING_CTRL_OFF,This register enables you to disable dynamic clock gating. By default dynamic clock gating is on. allowing the controller to autonomously enable and disable its clocks. The clock gating is performed in the clock and reset module." hexmask.long 0x70 2.--31. 1. "RSVDP_2,Reserved for future use." newline bitfld.long 0x70 1. "AXI_CLK_GATING_EN,AXI Clock Gating Enable. This register enables the AXI Bridge to autonomously enable and disable the AXI Master clock the AXI Slave clock and the AXI DBI slave clock. The DWC_pcie_clk_rst.v module provides the gated clock.." "Disable,Enable" newline bitfld.long 0x70 0. "RADM_CLK_GATING_EN,RADM Clock Gating Enable. This register if set enables the RADM to autonomously enable and disable its clock. The DWC_pcie_clk_rst.v module provides the gated clock radm_clk_g to the RADM and is enabled when the controllers clock.." "Disable,Enable" line.long 0x74 "GEN3_RELATED_OFF,Gen3 Control Register. There is no Gen3-specific N_FTS field. The N_FTS field in the 'Link Width and Speed Change Control Register' is used for both Gen2 and Gen3 speed modes. There is no Gen3-specific 'Directed Speed Change' field. The.." hexmask.long.byte 0x74 26.--31. 1. "RSVDP_26,Reserved for future use." newline bitfld.long 0x74 23. "GEN3_EQ_INVREQ_EVAL_DIFF_DISABLE,Eq InvalidRequest and RxEqEval Different Time Assertion Disable. Disable the assertion of Eq InvalidRequest and RxEqEval at different time. Note: When CX_GEN4_SPEED/CX_GEN5_SPEED this register is shared for Gen3 and.." "0,1" newline rbitfld.long 0x74 19.--20. "RSVDP_19,Reserved for future use." "0,1,2,3" newline bitfld.long 0x74 18. "GEN3_DC_BALANCE_DISABLE,DC Balance Disable. Disable DC Balance feature. Note: When CX_GEN4_SPEED/CX_GEN5_SPEED this register is shared for Gen3 and Gen4/Gen5 data rate. Note: This register field is sticky." "0,1" newline bitfld.long 0x74 17. "GEN3_DLLP_XMT_DELAY_DISABLE,DLLP Transmission Delay Disable. Disable delay transmission of DLLPs before equalization. Note: When CX_GEN4_SPEED/CX_GEN5_SPEED this register is shared for Gen3 and Gen4/Gen5 data rate. Note: This register field is sticky." "0,1" newline bitfld.long 0x74 16. "GEN3_EQUALIZATION_DISABLE,Equalization Disable. Disable equalization feature. This bit cannot be changed once the LTSSM starts link training. Note: When CX_GEN4_SPEED/CX_GEN5_SPEED this register is shared for Gen3 and Gen4/Gen5 data rate. Note: This.." "0,1" newline rbitfld.long 0x74 14.--15. "RSVDP_14,Reserved for future use." "0,1,2,3" newline bitfld.long 0x74 13. "RXEQ_RGRDLESS_RXTS,When set to '1' the controller as Gen3 EQ master asserts RxEqEval to instruct the PHY to do Rx adaptation and evaluation after a 500ns timeout from a new preset request. - 0: mac_phy_rxeqeval asserts after 1us and 2 TS1 received from.." "mac_phy_rxeqeval asserts after 1us and 2 TS1..,mac_phy_rxeqeval asserts after 500ns regardless.." newline bitfld.long 0x74 12. "RXEQ_PH01_EN,Rx Equalization Phase 0/Phase 1 Hold Enable. When this bit is set the upstream port holds phase 0 (the downstream port holds phase 1) for 10ms. Holding phase 0 or phase 1 can be used to allow sufficient time for Rx Equalization to be.." "Tx equalization only in phase 2/3,No Tx equalization" newline bitfld.long 0x74 11. "EQ_REDO,Equalization Redo Disable. Disable autonomous mechanism for requesting to redo the equalization process. The received presets or coefficients mismatch in Recovery.RcvrLock after Recovery EQ phases causes the EQ redo requests. If the EQ redo is.." "0,1" newline bitfld.long 0x74 10. "EQ_EIEOS_CNT,Equalization EIEOS Count Reset Disable. Disable requesting reset of EIEOS count during equalization. Note: When CX_GEN4_SPEED/CX_GEN5_SPEED this register is shared for Gen3 and Gen4/Gen5 data rate. Note: This register field is sticky." "0,1" newline bitfld.long 0x74 9. "EQ_PHASE_2_3,Equalization Phase 2 and Phase 3 Disable. This applies to downstream ports only. Note: When CX_GEN4_SPEED/CX_GEN5_SPEED this register is shadow register for Gen3 and Gen4/Gen5 data rate. If RATE_SHADOW_SEL==00b this register is for Gen3.." "0,1" newline bitfld.long 0x74 8. "DISABLE_SCRAMBLER_GEN_3,Disable Scrambler for Gen3 and Gen4 Data Rate. The Gen3 and Gen4 scrambler/descrambler within the controller needs to be disabled when the scrambling function is implemented outside of the controller (for example within the PHY)." "0,1" newline hexmask.long.byte 0x74 1.--7. 1. "RSVDP_1,Reserved for future use." newline bitfld.long 0x74 0. "GEN3_ZRXDC_NONCOMPL,Gen3 Receiver Impedance ZRX-DC Not Compliant. Receivers that operate at 8.0 GT/s with an impedance other than the range defined by the ZRX-DC parameter for 2.5 GT/s (40-60 Ohms) must meet additional behavior requirements in the.." "The receiver complies with the ZRX-DC parameter..,The receiver does not comply with the ZRX-DC.." group.long (0x1A8+0x700)++0x7 line.long 0x0 "GEN3_EQ_CONTROL_OFF,Gen3 EQ Control Register. This register controls equalization for Phase2 in an upstream port (USP). or Phase3 in a downstream port (DSP). M-PCIe doesn't have Conventional PCIe Gen3 feature. The registers of this section do not exist." hexmask.long.byte 0x0 27.--31. 1. "RSVDP_27,Reserved for future use." newline bitfld.long 0x0 26. "GEN3_REQ_SEND_CONSEC_EIEOS_FOR_PSET_MAP,Request controller to send back-to-back EIEOS in Recovery.RcvrLock state until presets to coefficients mapping is complete. - 0: Do not request - 1: request Note: Gen3 and Gen4 share the same register bit and have.." "Do not request,request" newline bitfld.long 0x0 25. "GEN3_EQ_PSET_REQ_AS_COEF,GEN3_EQ_PSET_REQ_AS_COEF is an internally reserved field. Do not use. Note: This register field is sticky." "0,1" newline bitfld.long 0x0 24. "GEN3_EQ_FOM_INC_INITIAL_EVAL,Include Initial FOM. Include or not the FOM feedback from the initial preset evaluation performed in the EQ Master when finding the highest FOM among all preset evaluations. - 0: Do not include - 1: Include Note: When.." "Do not include,Include" newline hexmask.long.word 0x0 8.--23. 1. "GEN3_EQ_PSET_REQ_VEC,Preset Request Vector. Requesting of Presets during the initial part of the EQ Master Phase. Encoding scheme is as follows: Bit [15:0] =0x0: No preset is requested and evaluated in EQ Master Phase. Bit [i] =1: 'Preset=i' is requested.." newline rbitfld.long 0x0 7. "RSVDP_7,Reserved for future use." "0,1" newline bitfld.long 0x0 6. "GEN3_LOWER_RATE_EQ_REDO_ENABLE,Support EQ redo and lower rate change: - 0: not support - 1: support Note: Gen3 and Gen4 share the same register bit and have the same feature. Note: This register field is sticky." "not support,support" newline bitfld.long 0x0 5. "GEN3_EQ_EVAL_2MS_DISABLE,Phase2_3 2 ms Timeout Disable. Determine behavior in Phase2 for USP (Phase3 if DSP) when the PHY does not respond within 2ms to the assertion of RxEqEval: - 0: abort the current evaluation stop any attempt to modify the remote.." "abort the current evaluation,ignore the 2ms timeout and continue as normal" newline bitfld.long 0x0 4. "GEN3_EQ_PHASE23_EXIT_MODE,Behavior After 24 ms Timeout (when optimal settings are not found). For a USP: Determine next LTSSM state from Phase2 after 24ms Timeout - 0: Recovery.Speed - 1: Recovery.Equalization.Phase3 When optimal settings are not found.." "Equalization Phase 3 Successful status bit is..,Recovery" newline hexmask.long.byte 0x0 0.--3. 1. "GEN3_EQ_FB_MODE,Feedback Mode. - 0000b: Direction Change - 0001b: Figure Of Merit - 0010b: Reserved - .....: Reserved - 1111b: Reserved Note: When CX_GEN4_SPEED/CX_GEN5_SPEED this register is a shadow register for Gen3 and Gen4/Gen5 data rate. If.." line.long 0x4 "GEN3_EQ_FB_MODE_DIR_CHANGE_OFF,Gen3 EQ Direction Change Feedback Mode Control Register. Equalization controls to be used in Phase2 (USP) or Phase 3 (DSP). when you set the Feedback Mode in 'Gen3 EQ Control Register' to 'Direction Change.' These fields.." hexmask.long.word 0x4 18.--31. 1. "RSVDP_18,Reserved for future use." newline hexmask.long.byte 0x4 14.--17. 1. "GEN3_EQ_FMDC_MAX_POST_CUSROR_DELTA,Convergence Window Aperture for C+1. Post-cursor coefficients maximum delta within the convergence window depth. Allowed range: 0 1 2 ..15. Note: When CX_GEN4_SPEED/CX_GEN5_SPEED this register is shadow register for.." newline hexmask.long.byte 0x4 10.--13. 1. "GEN3_EQ_FMDC_MAX_PRE_CUSROR_DELTA,Convergence Window Aperture for C-1. Pre-cursor coefficients maximum delta within the convergence window depth. Allowed range: 0 1 2 ..15. Note: When CX_GEN4_SPEED/CX_GEN5_SPEED this register is shadow register for Gen3.." newline hexmask.long.byte 0x4 5.--9. 1. "GEN3_EQ_FMDC_N_EVALS,Convergence Window Depth. Number of consecutive evaluations considered in Phase 2/3 when determining if optimal coefficients have been found. Allowed range: 0 1 2 ..16 up to a maximum of CX_GEN3_EQ_COEFQ_DEPTH. When set to 0 EQ.." newline hexmask.long.byte 0x4 0.--4. 1. "GEN3_EQ_FMDC_T_MIN_PHASE23,Minimum Time (in ms) To Remain in EQ Master Phase. The LTSSM stays in EQ Master phase for at least this amount of time before starting to check for convergence of the coefficients. Allowed values 0 1 ... 24. Note: When.." group.long (0x1B4+0x700)++0x27 line.long 0x0 "ORDER_RULE_CTRL_OFF,Order Rule Control Register." hexmask.long.word 0x0 16.--31. 1. "RSVDP_16,Reserved for future use." newline hexmask.long.byte 0x0 8.--15. 1. "CPL_PASS_P,Completion Passing Posted Ordering Rule Control. Determines if CPL can pass halted P queue. - 0: CPL can not pass P (recommended) - 1: CPL can pass P" newline hexmask.long.byte 0x0 0.--7. 1. "NP_PASS_P,Non-Posted Passing Posted Ordering Rule Control. Determines if NP can pass halted P queue. - 0 : NP can not pass P (recommended). - 1 : NP can pass P" line.long 0x4 "PIPE_LOOPBACK_CONTROL_OFF,PIPE Loopback Control Register." bitfld.long 0x4 31. "PIPE_LOOPBACK,PIPE Loopback Enable. Indicates RMMI Loopback if M-PCIe. Note: This register field is sticky." "0,1" newline hexmask.long.byte 0x4 27.--30. 1. "RSVDP_27,Reserved for future use." newline bitfld.long 0x4 24.--26. "RXSTATUS_VALUE,RXSTATUS_VALUE is an internally reserved field. Do not use." "0,1,2,3,4,5,6,7" newline rbitfld.long 0x4 22.--23. "RSVDP_22,Reserved for future use." "0,1,2,3" newline hexmask.long.byte 0x4 16.--21. 1. "RXSTATUS_LANE,RXSTATUS_LANE is an internally reserved field. Do not use. Note: This register field is sticky." newline hexmask.long.word 0x4 0.--15. 1. "LPBK_RXVALID,LPBK_RXVALID is an internally reserved field. Do not use. Note: This register field is sticky." line.long 0x8 "MISC_CONTROL_1_OFF,DBI Read-Only Write Enable Register." hexmask.long.word 0x8 22.--31. 1. "RSVDP_22,Reserved for future use." newline bitfld.long 0x8 21. "P2P_ERR_RPT_CTRL,Determines whether to track completion of transmitted Non-Posted TLPs in P2P mode. - 0: Do not track completion - 1: Track completion Note: This register field is sticky." "Do not track completion,Track completion" newline bitfld.long 0x8 20. "P2P_TRACK_CPL_TO_REG,Determines whether to enable Peer to Peer (P2P) error reporting. - 0: Disable P2P error reporting - 1: Enable P2P error reporting Note: This register field is sticky." "Disable P2P error reporting,Enable P2P error reporting" newline bitfld.long 0x8 18.--19. "TARGET_ABOVE_CONFIG_LIMIT_REG,Configuration requests with an address greater than CONFIG_LIMIT_REG are directed to either ELBI or TRGT1 interface based on the setting of this field. This field can have the following values: - 1: ELBI - 2: TRGT1 Note:.." "?,ELBI,TRGT1,?" newline hexmask.long.word 0x8 8.--17. 1. "CONFIG_LIMIT_REG,Configuration requests are directed either to CDM or ELBI/RTRGT1 based on the value of this field. - Configuration requests with an address less CONFIG_LIMIT_REG are directed to the CDM - Configuration requests with an address greater.." newline bitfld.long 0x8 7. "CFG_TLP_BYPASS_EN_REG,Setting of this field defines which field TARGET_ABOVE_CONFIG_LIMIT_REG or CONFIG_LIMIT_REG decides the destination of Configuration requests. This field can have the following values: - 0: Configuration TLPs are routed according to.." "Configuration TLPs are routed according to the..,Configuration TLPs are routed according to the.." newline bitfld.long 0x8 6. "CPLQ_MNG_EN,This field enables the Completion Queue Management feature. Note: This register field is sticky." "0,1" newline bitfld.long 0x8 5. "ARI_DEVICE_NUMBER,When ARI is enabled this field enables use of the device ID. Note: This register field is sticky." "0,1" newline bitfld.long 0x8 4. "DISABLE_AUTO_LTR_CLR_MSG,Disable the autonomous generation of LTR clear message in upstream port. This field can have the following values: - 0: Allow the autonomous generation of LTR clear message. - 1: Disable the autonomous generation of LTR clear.." "Allow the autonomous generation of LTR clear..,Disable the autonomous generation of LTR clear.." newline bitfld.long 0x8 3. "SIMPLIFIED_REPLAY_TIMER,Enables Simplified Replay Timer (Gen4). For more details see 'Transmit Replay' in 'Transmit TLP Processing' section in the 'Controller Operations' chapter of the Databook. Simplified Replay Timer can have the following Values: -.." "0,1" newline bitfld.long 0x8 2. "UR_CA_MASK_4_TRGT1,When this field is set to '1' the controller suppresses error logging error message generation and CPL generation for non-posted requests TLPs (with UR filtering status) forwarded to your application (that is when DEFAULT_TARGET.." "0,1" newline bitfld.long 0x8 1. "DEFAULT_TARGET,Default target for an IO or MEM request with UR/CA/CRS received. Based on the value of this field the controller either drops or forwards these requests to your application. - 0: The controller drops all incoming I/O or MEM requests (after.." "The controller drops all incoming I/O or MEM..,The controller forwards all incoming I/O or MEM.." newline bitfld.long 0x8 0. "DBI_RO_WR_EN,Write to RO Registers Using DBI. Your application can write to some RO and HwInit register fields through the DBI when you set this field to '1'. For more details see 'Writing to Read-Only Registers' in 'Register Module LBC and DBI'.." "0,1" line.long 0xC "MULTI_LANE_CONTROL_OFF,UpConfigure Multi-lane Control Register. Used when upsizing or downsizing the link width through Configuration state without bringing the link down. For more details. see the 'Link Establishment' section in the 'Controller.." hexmask.long.tbyte 0xC 8.--31. 1. "RSVDP_8,Reserved for future use." newline bitfld.long 0xC 7. "UPCONFIGURE_SUPPORT,Upconfigure Support. The controller sends this value as the Link Upconfigure Capability in TS2 Ordered Sets in Configuration.Complete state. This field is reserved (fixed to '0') for M-PCIe. Note: This register field is sticky." "0,1" newline bitfld.long 0xC 6. "DIRECT_LINK_WIDTH_CHANGE,Directed Link Width Change. The controller always moves to Configuration state through Recovery state when this bit is set to '1'. - If the upconfigure_capable variable is '1' and the PCIE_CAP_HW_AUTO_WIDTH_DISABLE bit in.." "0,1" newline hexmask.long.byte 0xC 0.--5. 1. "TARGET_LINK_WIDTH,Target Link Width. Values correspond to: - 6'b000000: Controller does not start upconfigure or autonomous width downsizing in the Configuration state. - 6'b000001: x1 - 6'b000010: x2 - 6'b000100: x4 - 6'b001000: x8 - 6'b010000: x16 -.." line.long 0x10 "PHY_INTEROP_CTRL_OFF,PHY Interoperability Control Register." hexmask.long.tbyte 0x10 12.--31. 1. "RSVDP_12,Reserved for future use." newline bitfld.long 0x10 10. "L1_CLK_SEL,L1 Clock control bit. This field is reserved for internal use. You should not write to this field and change the default unless specifically instructed by Synopsys support. - 1: Controller does not request aux_clk switch and core_clk gating in.." "Controller requests aux_clk switch and core_clk..,Controller does not request aux_clk switch and.." newline rbitfld.long 0x10 9. "L1_NOWAIT_P1,L1 entry control bit. This field is reserved for internal use. You should not write to this field and change the default unless specifically instructed by Synopsys support. - 1: Controller does not wait for PHY to acknowledge transition to.." "Controller waits for the PHY to acknowledge..,Controller does not wait for PHY to acknowledge.." newline bitfld.long 0x10 8. "L1SUB_EXIT_MODE,L1 Exit Control Using phy_mac_pclkack_n. This field is reserved for internal use. You should not write to this field and change the default unless specifically instructed by Synopsys support. - 1: Controller exits L1 without waiting for.." "Controller waits for the PHY to assert..,Controller exits L1 without waiting for the PHY.." newline rbitfld.long 0x10 7. "RSVDP_7,Reserved for future use." "0,1" newline hexmask.long.byte 0x10 0.--6. 1. "RXSTANDBY_CONTROL,Rxstandby Control. Bits 0..5 determine if the controller asserts the RxStandby signal (mac_phy_rxstandby) in the indicated condition. Bit 6 enables the controller to perform the RxStandby/RxStandbyStatus handshake. This field is.." line.long 0x14 "TRGT_CPL_LUT_DELETE_ENTRY_OFF,TRGT_CPL_LUT Delete Entry Control register. Using this register you can delete one entry in the target completion LUT. You should only use this register when you know that your application will never send the completion.." bitfld.long 0x14 31. "DELETE_EN,This is a one-shot bit. A '1' write to this bit triggers the deletion of the target completion LUT entry that is specified in the LOOK_UP_ID field. This is a self-clearing register field. Reading from this register field always returns a '0'." "0,1" newline hexmask.long 0x14 0.--30. 1. "LOOK_UP_ID,This number selects one entry to delete of the TRGT_CPL_LUT." line.long 0x18 "LINK_FLUSH_CONTROL_OFF,Link Reset Request Flush Control Register." hexmask.long.byte 0x18 24.--31. 1. "RSVD_I_8,This is an internally reserved field. Do not use. Note: This register field is sticky." newline hexmask.long.tbyte 0x18 1.--23. 1. "RSVDP_1,Reserved for future use." newline bitfld.long 0x18 0. "AUTO_FLUSH_EN,Enables automatic flushing of pending requests before sending the reset request to the application logic to reset the PCIe controller and the AXI Bridge. The flushing process is initiated if any of the following events occur: - Hot reset.." "0,1" line.long 0x1C "AMBA_ERROR_RESPONSE_DEFAULT_OFF,AXI Bridge Slave Error Response Register." hexmask.long.word 0x1C 16.--31. 1. "RSVDP_16,Reserved for future use." newline hexmask.long.byte 0x1C 10.--15. 1. "AMBA_ERROR_RESPONSE_MAP,AXI Slave Response Error Map. Allows you to selectively map the errors received from the PCIe completion (for non-posted requests) to the AXI slave responses slv_rresp or slv_bresp. The recommended setting is SLVERR. CRS is.." newline hexmask.long.byte 0x1C 5.--9. 1. "RSVDP_5,Reserved for future use." newline bitfld.long 0x1C 3.--4. "AMBA_ERROR_RESPONSE_CRS,CRS Slave Error Response Mapping. Determines the AXI slave response for CRS completions. For more details see 'Error Handling' in the AXI chapter of the Databook. AHB: - always returns OKAY AXI: - 00: OKAY - 01: OKAY with all.." "OKAY,OKAY with all FFFF_FFFF data for all CRS..,?,?" newline bitfld.long 0x1C 2. "AMBA_ERROR_RESPONSE_VENDORID,Vendor ID Non-existent Slave Error Response Mapping. Determines the AXI slave response for errors on reads to non-existent Vendor ID register. For more details see 'Error Handling' in the AXI chapter of the Databook. AHB: -.." "OKAY,SLVERR/DECERR" newline rbitfld.long 0x1C 1. "RSVDP_1,Reserved for future use." "0,1" newline bitfld.long 0x1C 0. "AMBA_ERROR_RESPONSE_GLOBAL,Global Slave Error Response Mapping. Determines the AXI slave response for all error scenarios on non-posted requests. For more details see 'Error Handling' in the AXI chapter of the Databook. AHB: - 0: OKAY (with FFFF data for.." "OKAY,SLVERR/DECERR" line.long 0x20 "AMBA_LINK_TIMEOUT_OFF,Link Down AXI Bridge Slave Timeout Register. If your application AXI master issues outbound requests to the AXI bridge slave interface before the PCIe link is operational. the controller starts a 'flush' timer. The timeout value of.." hexmask.long.tbyte 0x20 9.--31. 1. "RSVDP_9,Reserved for future use." newline bitfld.long 0x20 8. "LINK_TIMEOUT_ENABLE_DEFAULT,Disable Flush. You can disable the flush feature by setting this field to '1'. Note: This register field is sticky." "0,1" newline hexmask.long.byte 0x20 0.--7. 1. "LINK_TIMEOUT_PERIOD_DEFAULT,Timeout Value (ms). The timer will timeout and then flush the bridge TX request queues after this amount of time. The timer counts when there are pending outbound AXI slave interface requests and the PCIe TX link is not.." line.long 0x24 "AMBA_ORDERING_CTRL_OFF,AMBA Ordering Control." hexmask.long.tbyte 0x24 8.--31. 1. "RSVDP_8,Reserved for future use." newline bitfld.long 0x24 7. "AX_MSTR_ZEROLREAD_FW,AXI Master Zero Length Read Forward to the application. The DW PCIe controller AXI bridge is able to terminate in order with the Posted transactions the zero length read implementing the PCIe express flush semantics of the Posted.." "The zero length Read is terminated at the DW..,The zero length Read is forward to the application" newline rbitfld.long 0x24 5.--6. "RSVDP_5,Reserved for future use." "0,1,2,3" newline bitfld.long 0x24 3.--4. "AX_MSTR_ORDR_P_EVENT_SEL,AXI Master Posted Ordering Event Selector. This field selects how the master interface determines when a P write is completed when enforcing the PCIe ordering rule 'NP must not pass P' at the AXI Master Interface. The AXI.." "B'last event: wait for the all of the write..,AW'last event: wait until the complete Posted..,This setting will not affect:,?" newline rbitfld.long 0x24 2. "RSVDP_2,Reserved for future use." "0,1" newline bitfld.long 0x24 1. "AX_SNP_EN,AXI Serialize Non-Posted Requests Enable. This field enables the AXI Bridge to serialize same ID Non-Posted Read/Write Requests on the wire. Serialization implies one outstanding same ID NP Read or Write on the wire and used to avoid AXI RAR.." "0,1" newline rbitfld.long 0x24 0. "RSVDP_0,Reserved for future use." "0,1" group.long (0x1E0+0x700)++0xB line.long 0x0 "COHERENCY_CONTROL_1_OFF,ACE Cache Coherency Control Register 1" hexmask.long 0x0 2.--31. 1. "CFG_MEMTYPE_BOUNDARY_LOW_ADDR,Boundary Lower Address For Memory Type. Bits [31:0] of dword-aligned address of the boundary for Memory type. The two lower address LSBs are '00'. Addresses up to but not including this value are in the lower address space.." newline rbitfld.long 0x0 1. "RSVDP_1,Reserved for future use." "0,1" newline bitfld.long 0x0 0. "CFG_MEMTYPE_VALUE,Sets the memory type for the lower and upper parts of the address space: - 0: lower = Peripheral; upper = Memory - 1: lower = Memory type; upper = Peripheral Note: This register field is sticky." "lower = Peripheral; upper = Memory,lower = Memory type; upper = Peripheral" line.long 0x4 "COHERENCY_CONTROL_2_OFF,ACE Cache Coherency Control Register 2" hexmask.long 0x4 0.--31. 1. "CFG_MEMTYPE_BOUNDARY_HIGH_ADDR,Boundary Upper Address For Memory Type. Bits [63:32] of the 64-bit dword-aligned address of the boundary for Memory type. Note: This register field is sticky." line.long 0x8 "COHERENCY_CONTROL_3_OFF,ACE Cache Coherency Control Register 3" hexmask.long.byte 0x8 27.--30. 1. "CFG_MSTR_AWCACHE_VALUE,Master Write CACHE Signal Value. Value of the individual bits in mstr_awcache when CFG_MSTR_AWCACHE_MODE is '1'. Note: not applicable to message requests; for message requests the value of mstr_awcache is always '0000' Note: This.." newline hexmask.long.byte 0x8 19.--22. 1. "CFG_MSTR_ARCACHE_VALUE,Master Read CACHE Signal Value. Value of the individual bits in mstr_arcache when CFG_MSTR_ARCACHE_MODE is '1'. Note: This register field is sticky." newline hexmask.long.byte 0x8 11.--14. 1. "CFG_MSTR_AWCACHE_MODE,Master Write CACHE Signal Behavior. Defines how the individual bits in mstr_awcache are controlled: - 0: set automatically by the AXI master - 1: set by the value of the corresponding bit of the CFG_MSTR_AWCACHE_VALUE field Note:.." newline hexmask.long.byte 0x8 3.--6. 1. "CFG_MSTR_ARCACHE_MODE,Master Read CACHE Signal Behavior. Defines how the individual bits in mstr_arcache are controlled: - 0: set automatically by the AXI master - 1: set by the value of the corresponding bit of the CFG_MSTR_ARCACHE_VALUE field Note:.." group.long (0x1F0+0x700)++0x7 line.long 0x0 "AXI_MSTR_MSG_ADDR_LOW_OFF,Lower 20 bits of the programmable AXI address where Messages coming from wire are mapped to. Bits [11:0] of the register are tied to zero for the address to be 4k-aligned. In previous releases. the third and fourth DWORDs of a.." hexmask.long.tbyte 0x0 12.--31. 1. "CFG_AXIMSTR_MSG_ADDR_LOW,Lower 20 bits of the programmable AXI address for Messages. Note: This register field is sticky." newline hexmask.long.word 0x0 0.--11. 1. "CFG_AXIMSTR_MSG_ADDR_LOW_RESERVED,Reserved for future use. Note: This register field is sticky." line.long 0x4 "AXI_MSTR_MSG_ADDR_HIGH_OFF,Upper 32 bits of the programmable AXI address where Messages coming from wire are mapped to." hexmask.long 0x4 0.--31. 1. "CFG_AXIMSTR_MSG_ADDR_HIGH,Upper 32 bits of the programmable AXI address for Messages. Note: This register field is sticky." rgroup.long (0x1F8+0x700)++0x7 line.long 0x0 "PCIE_VERSION_NUMBER_OFF,PCIe Controller IIP Release Version Number. The version number is given in hex format. You should convert each pair of hex characters to ASCII to interpret. Using 4.70a (GA) as an example: - VERSION_NUMBER = 0x3437302a which.." hexmask.long 0x0 0.--31. 1. "VERSION_NUMBER,Version Number." line.long 0x4 "PCIE_VERSION_TYPE_OFF,PCIe Controller IIP Release Version Type. The type is given in hex format. You should convert each pair of hex characters to ASCII to interpret. Using 4.70a (GA) as an example: - VERSION_NUMBER = 0x3437302a which translates to 470*.." hexmask.long 0x4 0.--31. 1. "VERSION_TYPE,Version Type." group.long (0x240+0x700)++0x7 line.long 0x0 "MSIX_ADDRESS_MATCH_LOW_OFF,MSI-X Address Match Low Register. When you enable the MSI-X Table RAM feature (MSIX_TABLE_EN=1). the controller implements the logic and RAM required to generate MSI-X requests. For more details. see the Interrupts section in.." hexmask.long 0x0 2.--31. 1. "MSIX_ADDRESS_MATCH_LOW,MSI-X Address Match Low Address. Note: This register field is sticky." newline rbitfld.long 0x0 1. "MSIX_ADDRESS_MATCH_RESERVED_1,Reserved. Note: This register field is sticky." "0,1" newline bitfld.long 0x0 0. "MSIX_ADDRESS_MATCH_EN,MSI-X Match Enable. Enable the MSI-X Address Match feature when the AXI bridge is present. Note: This register field is sticky." "0,1" line.long 0x4 "MSIX_ADDRESS_MATCH_HIGH_OFF,MSI-X Address Match High Register. When you enable the MSI-X Table RAM feature (MSIX_TABLE_EN=1). the controller implements the logic and RAM required to generate MSI-X requests. For more details. see the Interrupts section in.." hexmask.long 0x4 0.--31. 1. "MSIX_ADDRESS_MATCH_HIGH,MSI-X Address Match High Address. Note: This register field is sticky." wgroup.long (0x248+0x700)++0x3 line.long 0x0 "MSIX_DOORBELL_OFF,MSI-X Doorbell Register. When you enable the MSI-X Table RAM feature (MSIX_TABLE_EN=1). the controller implements the logic and RAM required to generate MSI-X requests. For more details. see the Interrupts section in the 'Controller.." bitfld.long 0x0 29.--31. "MSIX_DOORBELL_RESERVED_29_31,Reserved." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x0 24.--28. 1. "MSIX_DOORBELL_PF,MSIX Doorbell Physical Function. This register determines the Physical Function for the MSI-X transaction." newline hexmask.long.byte 0x0 16.--23. 1. "MSIX_DOORBELL_VF,MSIX Doorbell Virtual Function. This register determines the Virtual Function for the MSI-X transaction." newline bitfld.long 0x0 15. "MSIX_DOORBELL_VF_ACTIVE,MSIX Doorbell Virtual Function Active. This register determines whether a Virtual Function is used to generate the MSI-X transaction." "0,1" newline bitfld.long 0x0 12.--14. "MSIX_DOORBELL_TC,MSIX Doorbell Traffic Class. This register determines which traffic class to generate the MSI-X transaction with." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 11. "MSIX_DOORBELL_RESERVED_11,Reserved." "0,1" newline hexmask.long.word 0x0 0.--10. 1. "MSIX_DOORBELL_VECTOR,MSI-X Doorbell Vector. This register determines which vector to generate the MSI-X transaction for." group.long (0x24C+0x700)++0x3 line.long 0x0 "MSIX_RAM_CTRL_OFF,MSI-X RAM power mode and debug control register. When you enable the MSI-X Table RAM feature (MSIX_TABLE_EN=1). the controller implements the logic and RAM required to generate MSI-X requests. For more details. see the Interrupts.." hexmask.long.byte 0x0 26.--31. 1. "MSIX_RAM_CTRL_RESERVED_26_31,Reserved. Note: This register field is sticky." newline bitfld.long 0x0 25. "MSIX_RAM_CTRL_DBG_PBA,MSIX PBA RAM Debug Mode. Use this bit to activate the debug mode and allow direct read/write access to the PBA. Use can also use the dbg_pba input to activate debug mode. Debug mode turns off the PF/VF/Offset-based addressing into.." "0,1" newline bitfld.long 0x0 24. "MSIX_RAM_CTRL_DBG_TABLE,MSIX Table RAM Debug Mode. Use this bit to activate the debug mode and allow direct read/write access to the Table. Use can also use the dbg_table input to activate debug mode. Debug mode turns off the PF/VF/Offset-based.." "0,1" newline hexmask.long.byte 0x0 17.--23. 1. "MSIX_RAM_CTRL_RESERVED_17_23,Reserved. Note: This register field is sticky." newline bitfld.long 0x0 16. "MSIX_RAM_CTRL_BYPASS,MSIX RAM Control Bypass. The bypass field when set disables the internal generation of low power signals for both RAMs. It is up to the application to ensure the RAMs are in the proper power state before trying to access them." "0,1" newline hexmask.long.byte 0x0 10.--15. 1. "MSIX_RAM_CTRL_RESERVED_10_15,Reserved. Note: This register field is sticky." newline bitfld.long 0x0 9. "MSIX_RAM_CTRL_PBA_SD,MSIX PBA RAM Shut Down. Set this bit to drive the cfg_msix_pba_sd output to signal your external logic to place the MSIX PBA RAM in Shut Down low-power mode. Note: This register field is sticky." "0,1" newline bitfld.long 0x0 8. "MSIX_RAM_CTRL_PBA_DS,MSIX PBA RAM Deep Sleep. Set this bit to drive the cfg_msix_pba_ds output to signal your external logic to place the MSIX PBA RAM in Deep Sleep low-power mode. Note: This register field is sticky." "0,1" newline hexmask.long.byte 0x0 2.--7. 1. "MSIX_RAM_CTRL_RESERVED_2_7,Reserved. Note: This register field is sticky." newline bitfld.long 0x0 1. "MSIX_RAM_CTRL_TABLE_SD,MSIX Table RAM Shut Down. Set this bit to drive the cfg_msix_table_sd output to signal your external logic to place the MSIX Table RAM in Shut Down low-power mode. Note: This register field is sticky." "0,1" newline bitfld.long 0x0 0. "MSIX_RAM_CTRL_TABLE_DS,MSIX Table RAM Deep Sleep. Set this bit to drive the cfg_msix_table_ds output to signal your external logic to place the MSIX Table RAM in Deep Sleep low-power mode. Note: This register field is sticky." "0,1" group.long (0x430+0x700)++0x3 line.long 0x0 "PL_LTR_LATENCY_OFF,LTR Latency Register. The function of this register field (and all other fields in this register) differs between an upstream port and a downstream port. For an upstream port. the register fields capture the corresponding fields in the.." bitfld.long 0x0 31. "NO_SNOOP_LATENCY_REQUIRE,No Snoop Latency Requirement. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" "0,1" newline rbitfld.long 0x0 29.--30. "RSVDP_29,Reserved for future use." "0,1,2,3" newline bitfld.long 0x0 26.--28. "NO_SNOOP_LATENCY_SCALE,No Snoop Latency Scale. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" "0,1,2,3,4,5,6,7" newline hexmask.long.word 0x0 16.--25. 1. "NO_SNOOP_LATENCY_VALUE,No Snoop Latency Value. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" newline bitfld.long 0x0 15. "SNOOP_LATENCY_REQUIRE,Snoop Latency Requirement. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" "0,1" newline rbitfld.long 0x0 13.--14. "RSVDP_13,Reserved for future use." "0,1,2,3" newline bitfld.long 0x0 10.--12. "SNOOP_LATENCY_SCALE,Snoop Latency Scale. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" "0,1,2,3,4,5,6,7" newline hexmask.long.word 0x0 0.--9. 1. "SNOOP_LATENCY_VALUE,Snoop Latency Value. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" group.long (0x440+0x700)++0xB line.long 0x0 "AUX_CLK_FREQ_OFF,Auxiliary Clock Frequency Control Register." hexmask.long.tbyte 0x0 10.--31. 1. "RSVDP_10,Reserved for future use." newline hexmask.long.word 0x0 0.--9. 1. "AUX_CLK_FREQ,The aux_clk frequency in MHz. This value is used to provide a 1 us reference for counting time during low-power states with aux_clk when the PHY has removed the pipe_clk. Frequencies lower than 1 MHz are possible but with a loss of accuracy.." line.long 0x4 "L1_SUBSTATES_OFF,L1 Substates Timing Register." hexmask.long.tbyte 0x4 9.--31. 1. "RSVDP_9,Reserved for future use." newline bitfld.long 0x4 8. "L1SUB_LOW_POWER_CLOCK_SWITCH_MODE,If this bit is set to 1'b1 the reference clock will be running regardless of the CLKREQ# setting. If this bit is set to 1'b0 the reference clock may be gated off when CLKREQ# is de-asserted. If the bit is set to 1'b1 the.." "0,1" newline bitfld.long 0x4 6.--7. "L1SUB_T_PCLKACK,Max delay (in 1us units) between a MAC request to remove the clock on mac_phy_pclkreq_n and a PHY response on phy_mac_pclkack_n. If the PHY does not respond within this time the request is aborted.The actual timeout value will be.." "0,1,2,3" newline hexmask.long.byte 0x4 2.--5. 1. "L1SUB_T_L1_2,Duration (in 1us units) of L1.2. The actual timeout value will be L1SUB_T_L1_2 + 1. Range is 0.15. Note: This register field is sticky." newline bitfld.long 0x4 0.--1. "L1SUB_T_POWER_OFF,Duration (in 1us units) of L1.2.Entry. The actual timeout value will be L1SUB_T_POWER_OFF + 1. Range is 0.3. Note: This register field is sticky." "0,1,2,3" line.long 0x8 "POWERDOWN_CTRL_STATUS_OFF,Powerdown Control and Status Register." hexmask.long.tbyte 0x8 12.--31. 1. "RSVDP_12,Reserved for future use." newline hexmask.long.byte 0x8 8.--11. 1. "POWERDOWN_PHY_POWERDOWN,This field represents the Powerdown value that has been acknowledged by the PHY. It is updated with the value of Powerdown driven by the controller when the PHY has returned the Phystatus acknowledgment for the Powerdown.." newline hexmask.long.byte 0x8 4.--7. 1. "POWERDOWN_MAC_POWERDOWN,This field represents the Powerdown value driven by the controller to the PHY." newline rbitfld.long 0x8 1.--3. "RSVDP_1,Reserved for future use." "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 0. "POWERDOWN_FORCE,This field is a one shot field. Writing a value of 1 to this field causes the controller to complete the P2 Powerdown handshake regardless of whether the PHY has returned Phystatus. This field could be used for debug purposes in event.." "0,1" group.long (0x470+0x700)++0x7 line.long 0x0 "PHY_VIEWPORT_CTLSTS_OFF,PHY Register Viewport Control and Status Register." rbitfld.long 0x0 31. "PHY_VIEWPORT_PENDING,PHY viewport pending. Indicates the access is pending. - 1 : Pending - 0 : Idle This bit is set to 1 when the read/write access has been initiated. This bit is cleared when the access is completed. If phy_reg_clk_g is never activated.." "Idle,Pending" newline rbitfld.long 0x0 30. "PHY_VIEWPORT_STATUS,PHY viewport status. Indicates the status of the latest access. - 1 : Timeout - 0 : No errors If the timeout is detected this bit is set to 1 and PHY_VIEWPORT_PENDING is cleared. This bit is cleared when the read/write access is.." "No errors,Timeout" newline hexmask.long.byte 0x0 23.--29. 1. "RSVDP_23,Reserved for future use." newline bitfld.long 0x0 22. "PHY_VIEWPORT_TIMEOUT_DISABLE,PHY viewport timeout disable. Disables the PHY register access timeout structure. When the timeout is disabled you must ensure that the PHY register accesses are always acknowledged by cr_para_ack. Otherwise.." "0,1" newline bitfld.long 0x0 21. "PHY_VIEWPORT_BCWR,Broadcast write access to all xN sub-blocks. If you need to broadcast the write accesses into all lanes both PHY_VIEWPORT_ADDR[15] and this bit should be 1. Note: This register field is sticky." "0,1" newline bitfld.long 0x0 20. "PHY_VIEWPORT_READ,PHY viewport read. If set a read access is initiated. The value is always 0 when this bit is read. Note: This register field is sticky." "0,1" newline hexmask.long.byte 0x0 16.--19. 1. "PHY_VIEWPORT_NUM,PHY viewport xN sub-block number. Selects one of xN sub-blocks. This register is not used when the write access is initiated with PHY_VIEWPORT_BCWR==1. Note: This register field is sticky." newline hexmask.long.word 0x0 0.--15. 1. "PHY_VIEWPORT_ADDR,PHY viewport address. Indicates the PHY's register address. Please refer to the PHY databook for the address map definition. Note: This register field is sticky." line.long 0x4 "PHY_VIEWPORT_DATA_OFF,PHY Register Viewport Data Register." hexmask.long.word 0x4 16.--31. 1. "RSVDP_16,Reserved for future use." newline hexmask.long.word 0x4 0.--15. 1. "PHY_VIEWPORT_DATA,PHY viewport data. A write access to this register initiates the PHY register write access. By a read access to this register this field returns the latest read data from the PHY register. Note: This register field is sticky." group.long (0x490+0x700)++0x3 line.long 0x0 "PIPE_RELATED_OFF,PIPE Related Register. This register controls the pipe's capabitity. control. and status parameters." hexmask.long.tbyte 0x0 9.--31. 1. "RSVDP_9,Reserved for future use." newline bitfld.long 0x0 8. "PIPE_GARBAGE_DATA_MODE,PIPE Garbage Data Mode. - 0: PIPE Spec compliant mode: The MAC discards any symbols received after the electrical idle ordered-set until RxValid is deasserted. - 1: Special PHY Support mode: The MAC discards any symbols received.." "PIPE Spec compliant mode: The MAC discards any..,Special PHY Support mode: The MAC discards any.." tree.end tree.end tree "PCIE1_ATU_DMA" base ad:0xF10C0000 tree "PF0_TYPE1_HDR (PCI-Compatible Configuration Space Header Type1)" group.long 0x0++0x2F line.long 0x0 "TYPE1_DEV_ID_VEND_ID_REG,Device ID and Vendor ID Register." hexmask.long.word 0x0 16.--31. 1. "DEVICE_ID,Device ID. The Device ID register identifies the particular Function. This identifier is allocated by the vendor. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else.." newline hexmask.long.word 0x0 0.--15. 1. "VENDOR_ID,Vendor ID. The Vendor ID register identifies the manufacturer of the Function. Valid vendor identifiers are allocated by the PCI-SIG to ensure uniqueness. It is not permitted to populate this register with a value of FFFFh which is an invalid.." line.long 0x4 "TYPE1_STATUS_COMMAND_REG,Status and Command Register." bitfld.long 0x4 31. "DETECTED_PARITY_ERROR,Detected Parity Error. This bit is set by a Function whenever it receives a Poisoned TLP regardless of the state the Parity Error Response bit in the Command register. The bit is set when the Poisoned TLP is received by a.." "0,1" newline bitfld.long 0x4 30. "SIGNALED_SYS_ERROR,Signaled System Error. This bit is set when a Function sends an ERR_FATAL or ERR_NONFATAL Message and the SERR# Enable bit in the Command register is 1b." "0,1" newline bitfld.long 0x4 29. "RCVD_MASTER_ABORT,Received Master Abort. This bit is set when a Requester receives a Completion with Unsupported Request Completion status. The bit is set when the Unsupported Request is received by a Function's primary side." "0,1" newline bitfld.long 0x4 28. "RCVD_TARGET_ABORT,Received Target Abort. This bit is set when a Requester receives a Completion with Completer Abort Completion status. The bit is set when the Completer Abort is received by a Function's primary side." "0,1" newline bitfld.long 0x4 27. "SIGNALED_TARGET_ABORT,Signaled Target Abort. This bit is set when a Function completes a Posted or Non-Posted Request as a Completer Abort error. This applies to a Function when the Completer Abort was generated by its primary side." "0,1" newline rbitfld.long 0x4 25.--26. "DEV_SEL_TIMING,DEVSEL Timing. This field was originally described in the PCI Local Bus Specification. Its functionality does not apply to PCI Express. The controller hardwires it to 00b." "0,1,2,3" newline bitfld.long 0x4 24. "MASTER_DPE,Master Data Parity Error. This bit is set by a Function if the Parity Error Response bit in the Command register is 1b and either of the following two conditions occurs: - Port receives a Poisoned Completion going downstream - Port transmits a.." "0,1" newline rbitfld.long 0x4 23. "FAST_B2B_CAP,Fast Back-to-Back Transactions Capable. This bit was originally described in the PCI Local Bus Specification. Its functionality does not apply to PCI Express. The controller hardwires this bit to 0b." "0,1" newline rbitfld.long 0x4 22. "RSVDP_22,Reserved for future use." "0,1" newline rbitfld.long 0x4 21. "FAST_66MHZ_CAP,66 MHz Capable. This bit was originally described in the PCI Local Bus Specification. Its functionality does not apply to PCI Express. The controller hardwires this bit to 0b." "0,1" newline rbitfld.long 0x4 20. "CAP_LIST,Capabilities List. Indicates the presence of an Extended Capability list item. Since all PCI Express device Functions are required to implement the PCI Express Capability structure the controller hardwires this bit to 1b." "0,1" newline rbitfld.long 0x4 19. "INT_STATUS,Interrupt Status. When set indicates that an INTx emulation interrupt is pending internally in the Function. INTx emulation interrupts forwarded by Functions from the secondary side are not reflected in this bit. Setting the Interrupt Disable.." "0,1" newline rbitfld.long 0x4 17.--18. "RSVDP_17,Reserved for future use." "0,1,2,3" newline bitfld.long 0x4 16. "IMM_READINESS,Immediate Readiness. This optional bit when set indicates the Function is guaranteed to be ready to successfully complete valid configuration accesses at any time following any reset that the host is capable of issuing Configuration.." "0,1" newline hexmask.long.byte 0x4 11.--15. 1. "RESERV,Reserved." newline bitfld.long 0x4 10. "INT_EN,Interrupt Disable. Controls the ability of a Function to generate INTx emulation interrupts. When set Functions are prevented from asserting INTx interrupts. Note: - Any INTx emulation interrupts already asserted by the Function must be.." "0,1" newline rbitfld.long 0x4 9. "RSVDP_9,Reserved for future use." "0,1" newline bitfld.long 0x4 8. "SERREN,SERR# Enable. When set this bit enables reporting upstream of Non-fatal and Fatal errors detected by the Function. Note: The errors are reported if enabled either through this bit or through the PCI Express specific bits in the Device Control.." "0,1" newline rbitfld.long 0x4 7. "IDSEL,IDSEL Stepping/Wait Cycle Control. This bit was originally described in the PCI Local Bus Specification. Its functionality does not apply to PCI Express. The controller hardwires this bit to 0b." "0,1" newline bitfld.long 0x4 6. "PERREN,Parity Error Response. This bit controls the logging of poisoned TLPs in the Master Data Parity Error bit in the Status register. For more details see the 'Error Registers' section of the PCI Express Base Specification." "0,1" newline rbitfld.long 0x4 5. "VGAPS,VGA Palette Snoop. This bit was originally described in the PCI Local Bus Specification and the PCI-to-PCI Bridge Architecture Specification. Its functionality does not apply to PCI Express. The controller hardwires this bit to 0b." "0,1" newline rbitfld.long 0x4 4. "MWI_EN,Memory Write and Invalidate. This bit was originally described in the PCI Local Bus Specification and the PCI-to-PCI Bridge Architecture Specification. Its functionality does not apply to PCI Express. The controller hardwires this bit to 0b. For.." "0,1" newline rbitfld.long 0x4 3. "SCO,Special Cycle Enable. This bit was originally described in the PCI Local Bus Specification. Its functionality does not apply to PCI Express. The controller hardwires this bit to 0b." "0,1" newline bitfld.long 0x4 2. "BME,Bus Master Enable. This bit controls forwarding of Memory or I/O requests by a port in the Upstream direction. When this bit is 0b Memory and I/O Requests received at a Root Port must be handled as Unsupported Requests (UR) For Non-Posted Requests a.." "0,1" newline bitfld.long 0x4 1. "MSE,Memory Space Enable. This bit controls a Function's response to Memory Space accesses received on its primary side. - When set the Function is enabled to decode the address and further process Memory Space accesses. - When clear all received Memory.." "0,1" newline bitfld.long 0x4 0. "IO_EN,IO Space Enable. This bit controls a Function's response to I/O Space accesses received on its primary side. - When set the Function is enabled to decode the address and further process I/O Space accesses. - When clear all received I/O accesses.." "0,1" line.long 0x8 "TYPE1_CLASS_CODE_REV_ID_REG,Class Code and Revision ID Register." hexmask.long.byte 0x8 24.--31. 1. "BASE_CLASS_CODE,Base Class Code. A code that broadly classifies the type of operation the Function performs. Encodings for base class are provided in the PCI Code and ID Assignment Specification. All unspecified encodings are reserved. Note: The access.." newline hexmask.long.byte 0x8 16.--23. 1. "SUBCLASS_CODE,Sub-Class Code. Specifies a base class sub-class which identifies more specifically the operation of the Function. Encodings for sub-class are provided in the PCI Code and ID Assignment Specification. All unspecified encodings are.." newline hexmask.long.byte 0x8 8.--15. 1. "PROGRAM_INTERFACE,Programming Interface. This field identifies a specific register level programming interface (if any) so that device independent software can interact with the Function. Encodings for interface are provided in the PCI Code and ID.." newline hexmask.long.byte 0x8 0.--7. 1. "REVISION_ID,Revision ID. The value of this field specifies a Function specific revision identifier. The value is chosen by the vendor. Zero is an acceptable value. The Revision ID should be viewed as a vendor defined extension to the Device ID. Note: The.." line.long 0xC "TYPE1_BIST_HDR_TYPE_LAT_CACHE_LINE_SIZE_REG,BIST. Header Type. Latency Timer. and Cache Line Size Register." hexmask.long.byte 0xC 24.--31. 1. "BIST,BIST. This register is used for control and status of BIST. Functions that do not support BIST must hardwire the register to 00h. A Function whose BIST is invoked must not prevent normal operation of the PCI Express Link. Bit descriptions: - [31]:.." newline rbitfld.long 0xC 23. "MULTI_FUNC,Multi-Function Device. - When set indicates that the device may contain multiple Functions but not necessarily. Software is permitted to probe for Functions other than Function 0. - When clear software must not probe for Functions other.." "0,1" newline hexmask.long.byte 0xC 16.--22. 1. "HEADER_TYPE,Header Layout. This field identifies the layout of the second part of the predefined header. The controller uses 000 0001b encoding. The encoding 000 0010b is reserved. This encoding was originally described in the PC Card Standard Electrical.." newline hexmask.long.byte 0xC 8.--15. 1. "LATENCY_MASTER_TIMER,Latency Timer. This register is also referred to as Primary Latency Timer. The Latency Timer was originally described in the PCI Local Bus Specification and the PCI-to-PCI Bridge Architecture Specification. Its functionality does not.." newline hexmask.long.byte 0xC 0.--7. 1. "CACHE_LINE_SIZE,Cache Line Size. The Cache Line Size register is programmed by the system firmware or the operating system to system cache line size. However legacy conventional PCI software may not always be able to program this register correctly.." line.long 0x10 "BAR0_REG,BAR0 Register. System software must build a consistent address map before booting the machine to an operating system. This means it has to determine how much memory is in the system. and how much address space the Functions in the system.." hexmask.long 0x10 4.--31. 1. "BAR0_START,BAR0 Base Address. - Memory Space: Base Address. - IO Space: bits[31:2] are used to map the function into IO space/Base. Address. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R(Sticky)/W(Sticky) if.." newline bitfld.long 0x10 3. "BAR0_PREFETCH,BAR0 Prefetchable. - Memory Space: Set to one if data is pre-fetchable. A Function is permitted to mark a range as prefetchable. If there are no side effects on reads the function returns all bytes on reads regardless of the byte enables.." "0,1" newline bitfld.long 0x10 1.--2. "BAR0_TYPE,BAR0 Type. - Memory Space: Base Address registers that map into Memory Space can be 32 bits or 64 bits wide (to support mapping into a 64-bit address space). The bit encoding is as follows: -- 00: Base register is 32 bits wide and can be mapped.." "Base register is 32 bits wide and can be mapped..,Reserved,?,?" newline bitfld.long 0x10 0. "BAR0_MEM_IO,BAR0 Memory Space Indicator. This bit is used to determine whether the register maps into Memory or I/O Space. Base Address registers that map to Memory Space must return a 0b. Base Address registers that map to I/O Space must return a 1b." "0,1" line.long 0x14 "BAR1_REG,BAR1 Register. System software must build a consistent address map before booting the machine to an operating system. This means it has to determine how much memory is in the system. and how much address space the Functions in the system.." hexmask.long 0x14 4.--31. 1. "BAR1_START,BAR1 Base Address. - Memory Space: Base Address. - IO Space: bits[31:2] are used to map the function into IO space/Base. Address. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R(Sticky)/W(Sticky) if.." newline bitfld.long 0x14 3. "BAR1_PREFETCH,BAR1 Prefetchable. - Memory Space: Set to one if data is pre-fetchable. A Function is permitted to mark a range as prefetchable. If there are no side effects on reads the function returns all bytes on reads regardless of the byte enables.." "0,1" newline bitfld.long 0x14 1.--2. "BAR1_TYPE,BAR1 Type. - Memory Space: Base Address registers that map into Memory Space can be 32 bits or 64 bits wide (to support mapping into a 64-bit address space). The bit encoding is as follows: -- 00: Base register is 32 bits wide and can be mapped.." "Base register is 32 bits wide and can be mapped..,Reserved,?,?" newline bitfld.long 0x14 0. "BAR1_MEM_IO,BAR1 Memory Space Indicator. This bit is used to determine whether the register maps into Memory or I/O Space. Base Address registers that map to Memory Space must return a 0b. Base Address registers that map to I/O Space must return a 1b." "0,1" line.long 0x18 "SEC_LAT_TIMER_SUB_BUS_SEC_BUS_PRI_BUS_REG,Secondary Latency Timer. Subordinate Bus Number. Secondary Bus Number. and Primary Bus Number Register." hexmask.long.byte 0x18 24.--31. 1. "SEC_LAT_TIMER,Secondary Latency Timer. This register does not apply to PCI Express. The controller hardwires it to 00h." newline hexmask.long.byte 0x18 16.--23. 1. "SUB_BUS,Subordinate Bus Number. The Subordinate Bus Number register is used to record the bus number of the highest numbered PCI bus segment which is behind (or subordinate to) the bridge. Configuration software programs the value in this register. The.." newline hexmask.long.byte 0x18 8.--15. 1. "SEC_BUS,Secondary Bus Number. The Secondary Bus Number register is used to record the bus number of the PCI bus segment to which the secondary interface of the bridge is connected. Configuration software programs the value in this register. The bridge.." newline hexmask.long.byte 0x18 0.--7. 1. "PRIM_BUS,Primary Bus Number. This register is not used by PCI Express Functions. It is implemented for compatibility with legacy software." line.long 0x1C "SEC_STAT_IO_LIMIT_IO_BASE_REG,Secondary Status. and I/O Limit and Base Register. The I/O Limit and I/O Base registers are optional and define an address range that is used by the bridge to determine when to forward I/O transactions from one interface to.." bitfld.long 0x1C 31. "SEC_STAT_DPE,Detected Parity Error. This bit is set by a Function when a Poisoned TLP is received by its secondary side regardless of the state the Parity Error Response Enable bit in the Bridge Control register." "0,1" newline bitfld.long 0x1C 30. "SEC_STAT_RCVD_SYS_ERR,Received System Error. This bit is set when the secondary side of a Function receives an ERR_FATAL or ERR_NONFATAL message." "0,1" newline bitfld.long 0x1C 29. "SEC_STAT_RCVD_MSTR_ABRT,Received Master Abort. This bit is set when the secondary side of a Function (for requests initiated by the Type 1 header Function itself) receives a Completion with Unsupported Request Completion status." "0,1" newline bitfld.long 0x1C 28. "SEC_STAT_RCVD_TRGT_ABRT,Received Target Abort. This bit is set when the secondary side of a Function (for requests initiated by the Type 1 header Function itself) receives a Completion with Completer Abort Completion status." "0,1" newline bitfld.long 0x1C 27. "SEC_STAT_SIG_TRGT_ABRT,Signaled Target Abort. This bit is set when the secondary side of the Function (for Requests completed by the Type 1 header Function itself) completes a Posted or Non-Posted request as a Completer Abort error." "0,1" newline rbitfld.long 0x1C 25.--26. "RSVDP_25,Reserved for future use." "0,1,2,3" newline bitfld.long 0x1C 24. "SEC_STAT_MDPE,Master Data Parity Error. This bit is set by a Function if the Parity Error Response Enable bit in the Bridge Control register is set and either of the following two conditions occurs: - Port receives a Poisoned Completion coming Upstream.." "0,1" newline rbitfld.long 0x1C 23. "RSVDP_23,Reserved for future use." "0,1" newline hexmask.long.byte 0x1C 16.--22. 1. "SEC_STAT_RESERV,Reserved." newline hexmask.long.byte 0x1C 12.--15. 1. "IO_LIMIT,I/O Limit Address. These bits correspond to the address[15:12] of IO address range. For the purpose of address decoding the bridge assumes that the lower 12 address bits address[11:0] of the I/O limit address (not implemented in the I/O Limit.." newline rbitfld.long 0x1C 9.--11. "IO_RESERV1,Reserved." "0,1,2,3,4,5,6,7" newline bitfld.long 0x1C 8. "IO_DECODE_BIT8,I/O Addressing Encode (IO Limit Address). This bit encodes the IO addressing capability of the bridge. IO_DECODE_BIT8 indicates the following: - 0h: The bridge supports only 16-bit I/O addressing (for ISA compatibility). For the purpose of.." "0,1" newline hexmask.long.byte 0x1C 4.--7. 1. "IO_BASE,I/O Base Address. These bits correspond to the address[15:12] of IO address range. For the purpose of address decoding the bridge assumes that the lower 12 address bits address[11:0] of the I/O base address (not implemented in the I/O Base.." newline rbitfld.long 0x1C 1.--3. "IO_RESERV,Reserved." "0,1,2,3,4,5,6,7" newline bitfld.long 0x1C 0. "IO_DECODE,I/O Addressing Encode (IO Base Address) This bit encodes the IO addressing capability of the bridge. IO_DECODE indicates the following: - 0h: The bridge supports only 16-bit I/O addressing (for ISA compatibility). For the purpose of address.." "0,1" line.long 0x20 "MEM_LIMIT_MEM_BASE_REG,Memory Limit and Base Register. The Memory Limit and Memory Base registers define a memory mapped address range which is used by the bridge to determine when to forward memory transactions from one interface to the other. If there.." hexmask.long.word 0x20 20.--31. 1. "MEM_LIMIT,Memory Limit Address. These bits correspond to the upper 12 address bits Address[31:20] of 32-bit addresses. For the purpose of address decoding the bridge assumes that the lower 20 address bits Address[19:0] of the memory limit address.." newline hexmask.long.byte 0x20 16.--19. 1. "MEM_LIMIT_RESERV,Reserved." newline hexmask.long.word 0x20 4.--15. 1. "MEM_BASE,Memory Base Address. These bits correspond to the upper 12 address bits Address[31:20] of 32-bit addresses. For the purpose of address decoding the bridge assumes that the lower 20 address bits Address[19:0] of the memory base address (not.." newline hexmask.long.byte 0x20 0.--3. 1. "MEM_BASE_RESERV,Reserved." line.long 0x24 "PREF_MEM_LIMIT_PREF_MEM_BASE_REG,Prefetchable Memory Limit and Base Register. The Prefetchable Memory Limit and Prefetchable Memory Base registers must indicate that 64-bit addresses are supported. as defined in PCI-to-PCI Bridge Architecture.." hexmask.long.word 0x24 20.--31. 1. "PREF_MEM_LIMIT,Prefetchable Memory Limit Address. If the Prefetchable Memory Limit register indicates support for 32-bit addressing then the Prefetchable Limit Upper 32 Bits register is implemented as a read-only register that returns zero when read. If.." newline rbitfld.long 0x24 17.--19. "PREF_RESERV1,Reserved." "0,1,2,3,4,5,6,7" newline rbitfld.long 0x24 16. "PREF_MEM_LIMIT_DECODE,Prefetchable Memory Limit Decode. This bit encodes whether or not the bridge supports 64-bit addresses. Note: This bit is a copy of the PREF_MEM_DECODE bit and always reflects the current value of that bit. The value of.." "0,1" newline hexmask.long.word 0x24 4.--15. 1. "PREF_MEM_BASE,Prefetchable Memory Base Address. If the Prefetchable Memory Base register indicates support for 32-bit addressing then the Prefetchable Base Upper 32 Bits register is implemented as a read-only register that returns zero when read. If the.." newline rbitfld.long 0x24 1.--3. "PREF_RESERV,Reserved." "0,1,2,3,4,5,6,7" newline bitfld.long 0x24 0. "PREF_MEM_DECODE,Prefetchable Memory Base Decode. This bit encodes whether or not the bridge supports 64-bit addresses. Note: By default the bit is set to 1'b1 indicating that 64-bit addresses are supported. If the bridge only supports 32-bit prefetchable.." "0,1" line.long 0x28 "PREF_BASE_UPPER_REG,Prefetchable Base Upper 32 Bits Register. The Prefetchable Base Upper 32 Bits register is an optional extension to the Prefetchable Memory Base register." hexmask.long 0x28 0.--31. 1. "PREF_MEM_BASE_UPPER,Prefetchable Base Upper 32 Bit. If the Prefetchable Memory Base register indicates support for 32-bit addressing then this register is implemented as read-only register that returns zero when read. If the Prefetchable Memory Base.." line.long 0x2C "PREF_LIMIT_UPPER_REG,Prefetchable Limit Upper 32 Bits Register. The Prefetchable Limit Upper 32 Bits register is an optional extension to the Prefetchable Memory Limit register." hexmask.long 0x2C 0.--31. 1. "PREF_MEM_LIMIT_UPPER,Prefetchable Limit Upper 32 Bit. If the Prefetchable Memory Limit register indicate support for 64-bit addressing then this register is implemented as read/write register which must be initialized by configuration software. This.." rgroup.long 0x30++0x3 line.long 0x0 "IO_LIMIT_UPPER_IO_BASE_UPPER_REG,I/O Limit and Base Upper 16 Bits Register. The I/O Limit Upper 16 Bits and I/O Base Upper 16 Bits registers are optional extensions to the I/O Limit and I/O Base registers." hexmask.long.word 0x0 16.--31. 1. "IO_LIMIT_UPPER,I/O Limit Upper 16 Bits. If the I/O Limit register indicates support for 16-bit I/O address decoding then this register is implemented as a read-only register which return zero when read. If the I/O Limit register indicates support for.." newline hexmask.long.word 0x0 0.--15. 1. "IO_BASE_UPPER,I/O Base Upper 16 Bits. If the I/O Base register indicates support for 16-bit I/O address decoding then this register is implemented as a read-only register which return zero when read. If the I/O base register indicates support for 32-bit.." group.long 0x34++0xB line.long 0x0 "TYPE1_CAP_PTR_REG,Capabilities Pointer Register." hexmask.long.tbyte 0x0 8.--31. 1. "RSVDP_8,Reserved for future use." newline hexmask.long.byte 0x0 0.--7. 1. "CAP_POINTER,Capabilities Pointer. This register is used to point to a linked list of capabilities implemented by this Function. Since all PCI Express Functions are required to implement the PCI Express Capability structure this register must point to a.." line.long 0x4 "TYPE1_EXP_ROM_BASE_REG,Expansion ROM Base Address Register. This register is defined to handle the base address and size information for this expansion ROM. The mask for this ROM BAR exists (if implemented) as a shadow register at this address. The.." hexmask.long.tbyte 0x4 11.--31. 1. "EXP_ROM_BASE_ADDRESS,Expansion ROM Base Address. Upper 21 bits of the Expansion ROM base address. The number of bits (out of these 21) that a Function actually implements depends on how much address space the Function requires. The mask for this ROM BAR.." newline hexmask.long.word 0x4 1.--10. 1. "RSVDP_1,Reserved for future use." newline bitfld.long 0x4 0. "ROM_BAR_ENABLE,Expansion ROM Enable. This bit controls whether or not the Function accepts accesses to its expansion ROM. When this bit is 0b the Function's expansion ROM address space is disabled. When the bit is 1b address decoding is enabled using.." "0,1" line.long 0x8 "BRIDGE_CTRL_INT_PIN_INT_LINE_REG,Bridge Control. Interrupt Pin. and Interrupt Line Register." hexmask.long.word 0x8 23.--31. 1. "BRIDGE_CTRL_RESERV,Reserved." newline bitfld.long 0x8 22. "SBR,Secondary Bus Reset. Setting this bit triggers a hot reset on the corresponding PCI Express Port. Software must ensure a minimum reset duration (Trst) as defined in the PCI Local Bus Specification. Software and systems must honor.." "0,1" newline rbitfld.long 0x8 21. "MSTR_ABORT_MODE,Master Abort Mode. This bit was originally described in the PCI-to-PCI Bridge Architecture Specification. Its functionality does not apply to PCI Express. The controller hardwires this bit to 0b. Note: The access attributes of this field.." "0,1" newline rbitfld.long 0x8 20. "VGA_16B_DEC,VGA 16 bit decode. This bit only has meaning if VGA Enable bit is set. This bit enables system configuration software to select between 10-bit and 16-bit I/O address decoding for all VGA I/O register accesses that are forwarded from primary.." "0,1" newline rbitfld.long 0x8 19. "VGA_EN,VGA Enable. Modifies the response by the bridge to VGA compatible addresses. If the VGA Enable bit is set the bridge will positively decode and forward the following accesses on the primary interface to the secondary interface (and conversely.." "0,1" newline bitfld.long 0x8 18. "ISA_EN,ISA Enable. Modifies the response by the bridge to ISA I/O addresses. This applies only to I/O addresses that are enabled by the I/O Base and I/O Limit registers and are in the first 64 KB of I/O address space (0000 0000h to 0000 FFFFh). If this.." "?,KB block" newline bitfld.long 0x8 17. "SERR_EN,SERR# Enable. This bit controls forwarding of ERR_COR ERR_NONFATAL and ERR_FATAL from secondary to primary." "0,1" newline bitfld.long 0x8 16. "PERE,Parity Error Response Enable. This bit controls the logging of poisoned TLPs in the Master Data Parity Error bit in the Secondary Status register." "0,1" newline hexmask.long.byte 0x8 8.--15. 1. "INT_PIN,Interrupt PIN. The Interrupt Pin register register that identifies the legacy interrupt Message(s) the Function uses. Valid values are: - 01h 02h 03h and 04h: map to legacy interrupt Messages for INTA INTB INTC and INTD respectively. - 00h:.." newline hexmask.long.byte 0x8 0.--7. 1. "INT_LINE,Interrupt Line. The Interrupt Line register communicates interrupt line routing information. The register must be implemented by any Function that uses an interrupt pin. Values in this register are programmed by system software and are system.." tree.end tree "PF0_SPCIE_CAP (Secondary PCI Express Capability Structure)" group.long (0x0+0x1A0)++0xF line.long 0x0 "SPCIE_CAP_HEADER_REG,SPCIE Capability Header. For a description of this standard PCIe register. see the PCI Express Specification." hexmask.long.word 0x0 20.--31. 1. "NEXT_OFFSET,Next Capability Offset. For a description of this standard PCIe register field see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky).." hexmask.long.byte 0x0 16.--19. 1. "CAP_VERSION,Capability Version. For a description of this standard PCIe register field see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else.." hexmask.long.word 0x0 0.--15. 1. "EXTENDED_CAP_ID,Secondary PCI Express Extended Capability ID. For a description of this standard PCIe register field see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN.." line.long 0x4 "LINK_CONTROL3_REG,Link Control 3 Register. For a description of this standard PCIe register. see the PCI Express Specification." hexmask.long 0x4 2.--31. 1. "RSVDP_2,Reserved for future use." bitfld.long 0x4 1. "EQ_REQ_INT_EN,Link Equalization Request Interrupt Enable. For a description of this standard PCIe register field see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" "0,1" bitfld.long 0x4 0. "PERFORM_EQ,Perform Equalization. For a description of this standard PCIe register field see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" "0,1" line.long 0x8 "LANE_ERR_STATUS_REG,Lane Error Status Register. For a description of this standard PCIe register. see the PCI Express Specification." hexmask.long 0x8 2.--31. 1. "RSVDP_LANE_ERR_STATUS,Reserved for future use." bitfld.long 0x8 0.--1. "LANE_ERR_STATUS,Lane Error Status Bits per Lane. For a description of this standard PCIe register field see the PCI Express Specification." "0,1,2,3" line.long 0xC "SPCIE_CAP_OFF_0CH_REG,Lane Equalization Control Register for lanes 1 and 0. For a description of this standard PCIe register. see the PCI Express Specification." rbitfld.long 0xC 31. "RSVDP_31,Reserved for future use." "0,1" bitfld.long 0xC 28.--30. "USP_RX_PRESET_HINT1,Upstream Port 8.0 GT/s Receiver Preset Hint 1. The write value is gated with the PCIE_CAP_CROSS_LINK_SUPPORT field of LINK_CAPABILITIES2_REG. For a description of this standard PCIe register field see the PCI Express Specification." "0,1,2,3,4,5,6,7" hexmask.long.byte 0xC 24.--27. 1. "USP_TX_PRESET1,Upstream Port 8.0 GT/s Transmitter Preset 1. The write value is gated with the PCIE_CAP_CROSS_LINK_SUPPORT field of LINK_CAPABILITIES2_REG. For a description of this standard PCIe register field see the PCI Express Specification. Note:.." rbitfld.long 0xC 23. "RSVDP_23,Reserved for future use." "0,1" newline bitfld.long 0xC 20.--22. "DSP_RX_PRESET_HINT1,Downstream Port 8.0 GT/s Receiver Preset Hint 1. For a description of this standard PCIe register field see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if.." "0,1,2,3,4,5,6,7" hexmask.long.byte 0xC 16.--19. 1. "DSP_TX_PRESET1,Downstream Port 8.0 GT/s Transmitter Preset 1. For a description of this standard PCIe register field see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN.." rbitfld.long 0xC 15. "RSVDP_15,Reserved for future use." "0,1" bitfld.long 0xC 12.--14. "USP_RX_PRESET_HINT0,Upstream Port 8.0 GT/s Receiver Preset Hint 0. The write value is gated with the PCIE_CAP_CROSS_LINK_SUPPORT field of LINK_CAPABILITIES2_REG. For a description of this standard PCIe register field see the PCI Express Specification." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0xC 8.--11. 1. "USP_TX_PRESET0,Upstream Port 8.0 GT/s Transmitter Preset 0. The write value is gated with the PCIE_CAP_CROSS_LINK_SUPPORT field of LINK_CAPABILITIES2_REG. For a description of this standard PCIe register field see the PCI Express Specification. Note:.." rbitfld.long 0xC 7. "RSVDP_7,Reserved for future use." "0,1" bitfld.long 0xC 4.--6. "DSP_RX_PRESET_HINT0,Downstream Port 8.0 GT/s Receiver Preset Hint 0. For a description of this standard PCIe register field see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if.." "0,1,2,3,4,5,6,7" hexmask.long.byte 0xC 0.--3. 1. "DSP_TX_PRESET0,Downstream Port 8.0 GT/s Transmitter Preset 0. For a description of this standard PCIe register field see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN.." tree.end tree "PF0_L1SUB_CAP (L1 Substates Capability Structure)" group.long (0x0+0x2E8)++0xF line.long 0x0 "L1SUB_CAP_HEADER_REG,L1 Substates Extended Capability Header. This register provides capbility ID. capability version and next offset value for L1 Substates." hexmask.long.word 0x0 20.--31. 1. "NEXT_OFFSET,Next Capability Offset. This field contains the offset to the next PCI Express Capability structure or 000h if no other items exist in the linked list of Capabilities. For Extended Capabilities implemented in Configuration Space this offset.." hexmask.long.byte 0x0 16.--19. 1. "CAP_VERSION,Capability Version. This field is a PCI-SIG defined version number that indicates the version of the Capability structure present. This field is depends on version of the specification. Note: The access attributes of this field are as.." hexmask.long.word 0x0 0.--15. 1. "EXTENDED_CAP_ID,L1SUB Extended Capability ID. This field is a PCI-SIG defined ID number that indicates the nature and format of the Extended Capability. Extended Capability ID for L1 PM Substates is 001Eh. Note: The access attributes of this field are as.." line.long 0x4 "L1SUB_CAPABILITY_REG,L1 Substates Capability Register. This register provides extended capability of L1 Substates." hexmask.long.byte 0x4 24.--31. 1. "RSVDP_24,Reserved for future use." hexmask.long.byte 0x4 19.--23. 1. "PWR_ON_VALUE_SUPPORT,Port T Power On Value. Along with the Port T_POWER_ON Scale field in the L1 PM Substates Capabilities register sets the time (in us) that this Port requires the port on the opposite side of Link to wait in L1.2.Exit after sampling.." rbitfld.long 0x4 18. "RSVDP_18,Reserved for future use." "0,1" bitfld.long 0x4 16.--17. "PWR_ON_SCALE_SUPPORT,Port T Power On Scale. Specifies the scale used for the Port T_POWER_ON Value field in the L1 PM Substates Capabilities register. Range of values are given below. Required for all Ports for which either the PCI-PM L1.2 Supported bit.." "?,?,?,Reserved" newline hexmask.long.byte 0x4 8.--15. 1. "COMM_MODE_SUPPORT,Port Common Mode Restore Time. Time (in us) required for this Port to re-establish common mode. Required for all Ports for which either the PCI-PM L1.2 Supported bit is Set ASPM L1.2 Supported bit is Set or both are Set otherwise.." rbitfld.long 0x4 5.--7. "RSVDP_5,Reserved for future use." "0,1,2,3,4,5,6,7" bitfld.long 0x4 4. "L1_PMSUB_SUPPORT,L1 PM Substates ECN Supported. When Set this bit indicates that this Port supports L1 PM Substates. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W (sticky)" "0,1" bitfld.long 0x4 3. "L1_1_ASPM_SUPPORT,ASPM L11 Supported. When Set this bit indicates that ASPM L1.1 is supported. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W (sticky)" "0,1" newline bitfld.long 0x4 2. "L1_2_ASPM_SUPPORT,ASPM L12 Supported. When Set this bit indicates that ASPM L1.2 is supported. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W (sticky)" "0,1" bitfld.long 0x4 1. "L1_1_PCIPM_SUPPORT,PCI-PM L11 Supported. When Set this bit indicates that PCI-PM L1.1 is supported and must be Set by all Ports implementing L1 PM Substates. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W (sticky)" "0,1" bitfld.long 0x4 0. "L1_2_PCIPM_SUPPORT,PCI-PM L12 Supported. When Set this bit indicates that PCI-PM L1.2 is supported. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W (sticky)" "0,1" line.long 0x8 "L1SUB_CONTROL1_REG,L1 Substates Control 1 Register. This register provides Controls to extended capability." bitfld.long 0x8 29.--31. "L1_2_TH_SCA,LTR L12 Threshold Scale. This field provides a scale for the value contained within the LTR_L1.2_THRESHOLD_Value.The default value for this field is 000b.Hardware operation is undefined if software writes a Not-Permitted value to this field." "0,1,2,3,4,5,6,7" rbitfld.long 0x8 26.--28. "RSVDP_26,Reserved for future use." "0,1,2,3,4,5,6,7" hexmask.long.word 0x8 16.--25. 1. "L1_2_TH_VAL,LTR L12 Threshold Value. Along with the LTR_L1.2_THRESHOLD_Scale this field indicates the LTR threshold used to determine if entry into L1 results in L1.1 (if enabled) or L1.2 (if enabled). The default value for this field is 00 0000 0000b." hexmask.long.byte 0x8 8.--15. 1. "T_COMMON_MODE,Common Mode Restore Time. Sets value of TCOMMONMODE (in us) which must be used by the Downstream Ports for timing the re-establishment of common mode.This field is of type RsvdP for Upstream Ports. Default value is implementation.." newline hexmask.long.byte 0x8 4.--7. 1. "RSVDP_4,Reserved for future use." bitfld.long 0x8 3. "L1_1_ASPM_EN,ASPM L11 Enable. When Set this bit enables ASPM L1.1.For Ports for which the ASPM L1.1 Supported bit is Clear this bit is permitted to be hardwired to 0.Default value is 0b." "0,1" bitfld.long 0x8 2. "L1_2_ASPM_EN,ASPM L12 Enable. When Set this bit enables ASPM L1.2.For Ports for which the ASPM L1.2 Supported bit is Clear this bit is permitted to be hardwired to 0.Default value is 0b." "0,1" bitfld.long 0x8 1. "L1_1_PCIPM_EN,PCI-PM L11 Enable. When Set this bit enables PCI-PM L1.1. Default value is 0b." "0,1" newline bitfld.long 0x8 0. "L1_2_PCIPM_EN,PCI-PM L12 Enable. When Set this bit enables PCI-PM L1.2.For Ports for which the PCI-PM L1.2 Supported bit is Clear this bit is permitted to be hardwired to 0.Default value is 0b." "0,1" line.long 0xC "L1SUB_CONTROL2_REG,L1 Substates Control 2 Register. This register provides Controls to extended capability." hexmask.long.tbyte 0xC 8.--31. 1. "RSVDP_8,Reserved for future use." hexmask.long.byte 0xC 3.--7. 1. "T_POWER_ON_VALUE,T Power On Value. Along with the T_POWER_ON Scale sets the minimum amount of time (in us) that the Port must wait in L1.2.Exit after sampling CLKREQ# asserted before actively driving the interface.Default value is 00101b. T_POWER_ON is.." rbitfld.long 0xC 2. "RSVDP_2,Reserved for future use." "0,1" bitfld.long 0xC 0.--1. "T_POWER_ON_SCALE,T Power On Scale. Specifies the scale used for T_POWER_ON Value. Range of values are given below. Required for all Ports that support L1.2 otherwise this field is of type RsvdP. This field must only be modified when the ASPM L1.2 Enable.." "?,?,?,Reserved" tree.end tree "PF0_RAS_DES_CAP (RAS D.E.S. Capability Structure (VSEC))" group.long (0x0+0x30C)++0x3 line.long 0x0 "RAS_DES_CAP_HEADER_REG,Vendor-Specific Extended Capability Header. For a description of this standard PCIe register. see the PCI Express Specification." hexmask.long.word 0x0 20.--31. 1. "NEXT_OFFSET,Next Capability Offset. For a description of this standard PCIe register field see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky).." newline hexmask.long.byte 0x0 16.--19. 1. "CAP_VERSION,Capability Version. For a description of this standard PCIe register field see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else.." newline hexmask.long.word 0x0 0.--15. 1. "EXTENDED_CAP_ID,PCI Express Extended Capability ID. For a description of this standard PCIe register field see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then.." rgroup.long (0x4+0x30C)++0x3 line.long 0x0 "VENDOR_SPECIFIC_HEADER_REG,Vendor-Specific Header. For a description of this standard PCIe register. see the PCI Express Specification." hexmask.long.word 0x0 20.--31. 1. "VSEC_LENGTH,VSEC Length. For a description of this standard PCIe register field see the PCI Express Specification." newline hexmask.long.byte 0x0 16.--19. 1. "VSEC_REV,VSEC Rev. For a description of this standard PCIe register field see the PCI Express Specification." newline hexmask.long.word 0x0 0.--15. 1. "VSEC_ID,VSEC ID. For a description of this standard PCIe register field see the PCI Express Specification." group.long (0x8+0x30C)++0x3 line.long 0x0 "EVENT_COUNTER_CONTROL_REG,Event Counter Control. This is a viewport control register. - Setting the EVENT_COUNTER_EVENT_SELECT and EVENT_COUNTER_LANE_SELECT fields in this register determine the Event Counter data returned by the EVENT_COUNTER_DATA_REG.." hexmask.long.byte 0x0 28.--31. 1. "RSVDP_28,Reserved for future use." newline hexmask.long.word 0x0 16.--27. 1. "EVENT_COUNTER_EVENT_SELECT,Event Counter Data Select. This field in conjunction with the EVENT_COUNTER_LANE_SELECT field indexes the Event Counter data returned by the EVENT_COUNTER_DATA_REG register. - 27-24: Group number(4-bit: 0..0x7) - 23-16: Event.." newline hexmask.long.byte 0x0 12.--15. 1. "RSVDP_12,Reserved for future use." newline hexmask.long.byte 0x0 8.--11. 1. "EVENT_COUNTER_LANE_SELECT,Event Counter Lane Select. This field in conjunction with EVENT_COUNTER_EVENT_SELECT indexes the Event Counter data returned by the EVENT_COUNTER_DATA_REG register. - 0x0: Lane0 - 0x1: Lane1 - 0x2: Lane2 - .. - 0xF: Lane15 Note:.." newline rbitfld.long 0x0 7. "EVENT_COUNTER_STATUS,Event Counter Status. This register returns the current value of the Event Counter selected by the following fields: - EVENT_COUNTER_EVENT_SELECT - EVENT_COUNTER_LANE_SELECT Note: This register field is sticky." "0,1" newline rbitfld.long 0x0 5.--6. "RSVDP_5,Reserved for future use." "0,1,2,3" newline bitfld.long 0x0 2.--4. "EVENT_COUNTER_ENABLE,Event Counter Enable. Enables/disables the Event Counter selected by the EVENT_COUNTER_EVENT_SELECT and EVENT_COUNTER_LANE_SELECT fields in this register. By default all event counters are disabled. You can enable/disable a specific.." "no change,per event off,?,?,?,?,?,?" newline bitfld.long 0x0 0.--1. "EVENT_COUNTER_CLEAR,Event Counter Clear. Clears the Event Counter selected by the EVENT_COUNTER_EVENT_SELECT and EVENT_COUNTER_LANE_SELECT fields in this register. You can clear the value of a specific Event Counter by writing the 'per clear' code and.." "no change,per clear,?,?" rgroup.long (0xC+0x30C)++0x3 line.long 0x0 "EVENT_COUNTER_DATA_REG,Event Counter Data. This viewport register returns the data selected by the following fields: - EVENT_COUNTER_EVENT_SELECT in EVENT_COUNTER_CONTROL_REG - EVENT_COUNTER_LANE_SELECT in EVENT_COUNTER_CONTROL_REG For more details. see.." hexmask.long 0x0 0.--31. 1. "EVENT_COUNTER_DATA,Event Counter Data. This register returns the data selected by the following fields: - EVENT_COUNTER_EVENT_SELECT in EVENT_COUNTER_CONTROL_REG - EVENT_COUNTER_LANE_SELECT in EVENT_COUNTER_CONTROL_REG Note: This register field is sticky." group.long (0x10+0x30C)++0x3 line.long 0x0 "TIME_BASED_ANALYSIS_CONTROL_REG,Time-based Analysis Control. Used for controlling the measurement of RX/TX data throughput and time spent in each low-power LTSSM state. For more details. see the RAS DES section in the Core Operations chapter of the.." hexmask.long.byte 0x0 24.--31. 1. "TIME_BASED_REPORT_SELECT,Time-based Report Select. Selects what type of data is measured for the selected duration (TIME_BASED_DURATION_SELECT) and returned in TIME_BASED_ANALYSIS_DATA. Each type of data is measured using one of three types of units: -.." newline hexmask.long.byte 0x0 16.--23. 1. "RSVDP_16,Reserved for future use." newline hexmask.long.byte 0x0 8.--15. 1. "TIME_BASED_DURATION_SELECT,Time-based Duration Select. Selects the duration of time-based analysis. When 'manual control' is selected and TIMER_START is set to '1' this analysis never stops until TIMER_STOP is set to '0'. - 0x0: Manual control - 0x1:.." newline hexmask.long.byte 0x0 1.--7. 1. "RSVDP_1,Reserved for future use." newline bitfld.long 0x0 0. "TIMER_START,Timer Start. - 1: Start/Restart - 0: Stop This bit will be cleared automatically when the measurement is finished. Note: The app_ras_des_tba_ctrl input also sets the contents of this field and controls the measurement start/stop. Note: This.." "Stop,Start/Restart" rgroup.long (0x14+0x30C)++0x7 line.long 0x0 "TIME_BASED_ANALYSIS_DATA_REG,Time-based Analysis Data. Contains the measurement results of RX/TX data throughput and time spent in each low-power LTSSM state. This viewport register returns the data selected by the TIME_BASED_REPORT_SELECT field in.." hexmask.long 0x0 0.--31. 1. "TIME_BASED_ANALYSIS_DATA,Time Based Analysis Data. This register returns the data selected by the TIME_BASED_REPORT_SELECT field in TIME_BASED_ANALYSIS_CONTROL_REG. The results are cleared when next measurement starts. Note: This register field is sticky." line.long 0x4 "TIME_BASED_ANALYSIS_DATA_63_32_REG,Upper 32 bits of Time-based Analysis Data. This viewport register returns the data selected by the TIME_BASED_REPORT_SELECT field in TIME_BASED_ANALYSIS_CONTROL_REG. For more details. see the RAS DES section in the Core.." hexmask.long 0x4 0.--31. 1. "TIME_BASED_ANALYSIS_DATA_63_32,Upper 32 bits of Time Based Analysis Data. Note: This register field is sticky." group.long (0x30+0x30C)++0x5F line.long 0x0 "EINJ_ENABLE_REG,Error Injection Enable. Each type of error insertion is enabled by the corresponding bit in this register. The specific injection controls for each type of error are defined in the following registers: - 0: CRC Error: EINJ0_CRC_REG - 1:.." hexmask.long 0x0 7.--31. 1. "RSVDP_7,Reserved for future use." newline bitfld.long 0x0 6. "ERROR_INJECTION6_ENABLE,Error Injection6 Enable (Specific TLP Error). Enables insertion of errors into the packets that you select. You can set this bit to '1' when you have disabled RAS datapath protection (DP) by setting CX_RASDP = CX_RASDP_RAM_PROT.." "0,1" newline bitfld.long 0x0 5. "ERROR_INJECTION5_ENABLE,Error Injection5 Enable (TLP Duplicate/Nullify Error). Enables insertion of duplicate/nullified TLPs. For more details see the EINJ5_SP_TLP_REG register. Note: This register field is sticky." "0,1" newline bitfld.long 0x0 4. "ERROR_INJECTION4_ENABLE,Error Injection4 Enable (FC Credit Update Error). Enables insertion of errors into UpdateFCs. For more details see the EINJ4_FC_REG register. Note: This register field is sticky." "0,1" newline bitfld.long 0x0 3. "ERROR_INJECTION3_ENABLE,Error Injection3 Enable (Symbol DataK Mask Error or Sync Header Error). Enables DataK masking of special symbols or the breaking of the sync header. For more details see the EINJ3_SYMBOL_REG register. Note: This register field is.." "0,1" newline bitfld.long 0x0 2. "ERROR_INJECTION2_ENABLE,Error Injection2 Enable (DLLP Error). Enables insertion of DLLP errors. For more details see the EINJ2_DLLP_REG register. Note: This register field is sticky." "0,1" newline bitfld.long 0x0 1. "ERROR_INJECTION1_ENABLE,Error Injection1 Enable (Sequence Number Error). Enables insertion of errors into sequence numbers. For more details see the EINJ1_SEQNUM_REG register. Note: This register field is sticky." "0,1" newline bitfld.long 0x0 0. "ERROR_INJECTION0_ENABLE,Error Injection0 Enable (CRC Error). Enables insertion of errors into various CRC. For more details see the EINJ0_CRC_REG register. Note: This register field is sticky." "0,1" line.long 0x4 "EINJ0_CRC_REG,Error Injection Control 0 (CRC Error). Controls the insertion of errors into the CRC. and parity of ordered sets for the selected type of the packets as follows: - LCRC. Bad TLP will be detected at the receiver side; receiver responds with.." hexmask.long.tbyte 0x4 12.--31. 1. "RSVDP_12,Reserved for future use." newline hexmask.long.byte 0x4 8.--11. 1. "EINJ0_CRC_TYPE,Error injection type. Selects the type of CRC error to be inserted. Tx Path - 0000b: New TLP's LCRC error injection - 0001b: 16bCRC error injection of ACK/NAK DLLP - 0010b: 16bCRC error injection of Update-FC DLLP - 0011b: New TLP's ECRC.." newline hexmask.long.byte 0x4 0.--7. 1. "EINJ0_COUNT,Error injection count. Indicates the number of errors. This register is decremented when the errors have been inserted. - If the counter value is 0x01 and error is inserted ERROR_INJECTION0_ENABLE in EINJ_ENABLE_REG returns 0b. - If the.." line.long 0x8 "EINJ1_SEQNUM_REG,Error Injection Control 1 (Sequence Number Error). Controls the sequence number of the specific TLPs and ACK/NAK DLLPs. Data Link Protocol Error will be detected at the Rx side of ACK/NAL DLLPs when one of these conditions is true: -.." rbitfld.long 0x8 29.--31. "RSVDP_29,Reserved for future use." "0,1,2,3,4,5,6,7" newline hexmask.long.word 0x8 16.--28. 1. "EINJ1_BAD_SEQNUM,Bad sequence number. Indicates the value to add/subtract from the naturally-assigned sequence numbers. This value is represented by two's complement. - 0x0FFF: +4095 - .. - 0x0002: +2 - 0x0001: +1 - 0x0000: 0 - 0x1FFF: -1 - 0x1FFE: -2 -.." newline hexmask.long.byte 0x8 9.--15. 1. "RSVDP_9,Reserved for future use." newline bitfld.long 0x8 8. "EINJ1_SEQNUM_TYPE,Sequence number type. Selects the type of sequence number. - 0b: Insertion of New TLP's SEQ# error - 1b: Insertion of ACK/NAK DLLP's SEQ# Error Note: This register field is sticky." "0,1" newline hexmask.long.byte 0x8 0.--7. 1. "EINJ1_COUNT,Error injection count. Indicates the number of errors. This register is decremented as the errors are being inserted. - If the counter value is 0x01 and error is inserted ERROR_INJECTION1_ENABLE in EINJ_ENABLE_REG returns '0'. - If the.." line.long 0xC "EINJ2_DLLP_REG,Error Injection Control 2 (DLLP Error). Controls the transmission of DLLPs and inserts the following errors: - If 'ACK/NAK DLLP's transmission block' is selected. replay timeout error will occur at the transmitter of the TLPs and then Data.." hexmask.long.tbyte 0xC 10.--31. 1. "RSVDP_10,Reserved for future use." newline bitfld.long 0xC 8.--9. "EINJ2_DLLP_TYPE,DLLP Type. Selects the type of DLLP errors to be inserted. - 00b: ACK/NAK DLLP's transmission block - 01b: Update FC DLLP's transmission block - 10b: Always Transmission for NAK DLLP - 11b: Reserved Note: This register field is sticky." "0,1,2,3" newline hexmask.long.byte 0xC 0.--7. 1. "EINJ2_COUNT,Error injection count. Indicates the number of errors. This register is decremented as the errors are being inserted. - If the counter value is 0x01 and the error is inserted ERROR_INJECTION2_ENABLE in EINJ_ENABLE_REG returns '0'. - If the.." line.long 0x10 "EINJ3_SYMBOL_REG,Error Injection Control 3 (Symbol Error). When 8b/10b encoding is used. this register controls error insertion into the special (K code) symbols. - If TS1/TS2/FTS/E-Idle/SKP is selected. it affects whole of the ordered set. It might.." hexmask.long.tbyte 0x10 11.--31. 1. "RSVDP_11,Reserved for future use." newline bitfld.long 0x10 8.--10. "EINJ3_SYMBOL_TYPE,Error Type. 8b/10b encoding - Mask K symbol. It is not supported to insert errors into the first ordered-set after exiting from TxElecIdle when CX_FREQ_STEP_EN has been enabled. - 000b: Reserved - 001b: COM/PAD(TS1 Order set) - 010b:.." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x10 0.--7. 1. "EINJ3_COUNT,Error injection count. Indicates the number of errors. This register is decremented as the errors are being inserted. - If the counter value is 0x01 and error is inserted ERROR_INJECTION3_ENABLE in EINJ_ENABLE_REG returns '0'. - If the.." line.long 0x14 "EINJ4_FC_REG,Error Injection Control 4 (FC Credit Error). Controls error insertion into the credit value in the UpdateFCs. It is possible to insert errors for any of the following types: - Posted TLP Header credit - Non-Posted TLP Header credit -.." rbitfld.long 0x14 29.--31. "RSVDP_29,Reserved for future use." "0,1,2,3,4,5,6,7" newline hexmask.long.word 0x14 16.--28. 1. "EINJ4_BAD_UPDFC_VALUE,Bad update-FC credit value. Indicates the value to add/subtract from the UpdateFC credit. This value is represented by two's complement. - 0x0FFF: +4095 - .. - 0x0002: +2 - 0x0001: +1 - 0x0000: 0 - 0x1FFF: -1 - 0x1FFE: -2 - .. -.." newline rbitfld.long 0x14 15. "RSVDP_15,Reserved for future use." "0,1" newline bitfld.long 0x14 12.--14. "EINJ4_VC_NUMBER,VC Number. Indicates target VC Number. Note: This register field is sticky." "0,1,2,3,4,5,6,7" newline rbitfld.long 0x14 11. "RSVDP_11,Reserved for future use." "0,1" newline bitfld.long 0x14 8.--10. "EINJ4_UPDFC_TYPE,Update-FC type. Selects the credit type. - 000b: Posted TLP Header Credit value control - 001b: Non-Posted TLP Header Credit value control - 010b: Completion TLP Header Credit value control - 011b: Reserved - 100b: Posted TLP Data Credit.." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x14 0.--7. 1. "EINJ4_COUNT,Error injection count. Indicates the number of errors. This register is decremented as the errors are being inserted. - If the counter value is 0x01 and error is inserted ERROR_INJECTION4_ENABLE in EINJ_ENABLE_REG returns '0'. - If the.." line.long 0x18 "EINJ5_SP_TLP_REG,Error Injection Control 5 (Specific TLP Error). Controls the generation of specified TLPs. Correctable errors will occur which will be fixed by the PCIe protocol. - For Duplicate TLP. the controller initiates Data Link Retry by handling.." hexmask.long.tbyte 0x18 9.--31. 1. "RSVDP_9,Reserved for future use." newline bitfld.long 0x18 8. "EINJ5_SPECIFIED_TLP,Specified TLP. Selects the specified TLP to be inserted. - 0: Generates duplicate TLPs by handling ACK DLLP as NAK DLLP. - 1: Generates Nullified TLP (Original TLP will be stored in retry buffer). Note: This register field is sticky." "Generates duplicate TLPs by handling ACK DLLP as..,Generates Nullified TLP" newline hexmask.long.byte 0x18 0.--7. 1. "EINJ5_COUNT,Error injection count. Indicates the number of errors. This register is decremented as the errors are being inserted. - If the counter value is 0x01 and error is inserted ERROR_INJECTION5_ENABLE in EINJ_ENABLE_REG returns '0'. - If the.." line.long 0x1C "EINJ6_COMPARE_POINT_H0_REG,Error Injection Control 6 (Compare Point Header DWORD #0). Program this register for the 1st DWORD of TLP header/prefix. It is necessary to carefully consider the endianness when you program this register. Bits [31:0] =.." hexmask.long 0x1C 0.--31. 1. "EINJ6_COMPARE_POINT_H0,Packet Compare Point: 1st DWORD. Specifies which Tx TLP header DWORD#0 bits to compare with the corresponding bits in the Packet Compare Value registers (EINJ6_COMPARE_VALUE*). When all specified bits (in the Tx TLP header and.." line.long 0x20 "EINJ6_COMPARE_POINT_H1_REG,Error Injection Control 6 (Compare Point Header DWORD #1). Program this register for the 2nd DWORD of TLP header/prefix. It is necessary to carefully consider the endianness when you program this register. Bits [31:0] =.." hexmask.long 0x20 0.--31. 1. "EINJ6_COMPARE_POINT_H1,Packet Compare Point: 2nd DWORD. Specifies which Tx TLP header DWORD#1 bits to compare with the corresponding bits in the Packet Compare Value registers (EINJ6_COMPARE_VALUE*). When all specified bits (in the Tx TLP header and.." line.long 0x24 "EINJ6_COMPARE_POINT_H2_REG,Error Injection Control 6 (Compare Point Header DWORD #2). Program this register for the 3rd DWORD of TLP header/prefix. It is necessary to carefully consider the endianness when you program this register. Bits [31:0] =.." hexmask.long 0x24 0.--31. 1. "EINJ6_COMPARE_POINT_H2,Packet Compare Point: 3rd DWORD. Specifies which Tx TLP header DWORD#2 bits to compare with the corresponding bits in the Packet Compare Value registers (EINJ6_COMPARE_VALUE*). When all specified bits (in the Tx TLP header and.." line.long 0x28 "EINJ6_COMPARE_POINT_H3_REG,Error Injection Control 6 (Compare Point Header DWORD #3). Program this register for the 4th DWORD of TLP header/prefix. It is necessary to carefully consider the endianness when you program this register. Bits [31:0] =.." hexmask.long 0x28 0.--31. 1. "EINJ6_COMPARE_POINT_H3,Packet Compare Point: 4th DWORD. Specifies which Tx TLP header DWORD#3 bits to compare with the corresponding bits in the Packet Compare Value registers (EINJ6_COMPARE_VALUE*). When all specified bits (in the Tx TLP header and.." line.long 0x2C "EINJ6_COMPARE_VALUE_H0_REG,Error Injection Control 6 (Compare Value Header DWORD #0). Program this register for the 1st DWORD of TLP header/prefix. It is necessary to carefully consider the endianness when you program this register. Bits [31:0] =.." hexmask.long 0x2C 0.--31. 1. "EINJ6_COMPARE_VALUE_H0,Packet Compare Value: 1st DWORD. Specifies the value to compare against Tx the TLP header DWORD#0 bits specified in the Packet Compare Point registers (EINJ6_COMPARE_POINT*). Note: This register field is sticky." line.long 0x30 "EINJ6_COMPARE_VALUE_H1_REG,Error Injection Control 6 (Compare Value Header DWORD #1). Program this register for the 2nd DWORD of TLP header/prefix. It is necessary to carefully consider the endianness when you program this register. Bits [31:0] =.." hexmask.long 0x30 0.--31. 1. "EINJ6_COMPARE_VALUE_H1,Packet Compare Value: 2nd DWORD. Specifies the value to compare against Tx the TLP header DWORD#1 bits specified in the Packet Compare Point registers (EINJ6_COMPARE_POINT*). Note: This register field is sticky." line.long 0x34 "EINJ6_COMPARE_VALUE_H2_REG,Error Injection Control 6 (Compare Value Header DWORD #2). Program this register for the 3rd DWORD of TLP header/prefix. It is necessary to carefully consider the endianness when you program this register. Bits [31:0] =.." hexmask.long 0x34 0.--31. 1. "EINJ6_COMPARE_VALUE_H2,Packet Compare Value: 3rd DWORD. Specifies the value to compare against Tx the TLP header DWORD#2 bits specified in the Packet Compare Point registers (EINJ6_COMPARE_POINT*). Note: This register field is sticky." line.long 0x38 "EINJ6_COMPARE_VALUE_H3_REG,Error Injection Control 6 (Compare Value Header DWORD #3). Program this register for the 4th DWORD of TLP header/prefix. It is necessary to carefully consider the endianness when you program this register. Bits [31:0] =.." hexmask.long 0x38 0.--31. 1. "EINJ6_COMPARE_VALUE_H3,Packet Compare Value: 4th DWORD. Specifies the value to compare against Tx the TLP header DWORD#3 bits specified in the Packet Compare Point registers (EINJ6_COMPARE_POINT*). Note: This register field is sticky." line.long 0x3C "EINJ6_CHANGE_POINT_H0_REG,Error Injection Control 6 (Change Point Header DWORD #0). Program this register for the 1st DWORD of TLP header/prefix. It is necessary to carefully consider the endianness when you program this register. Bits [31:0] =.." hexmask.long 0x3C 0.--31. 1. "EINJ6_CHANGE_POINT_H0,Packet Change Point: 1st DWORD. Specifies which Tx TLP header DWORD#0 bits to replace with the corresponding bits in the Packet Change Value registers (EINJ6_CHANGE_VALUE*). Note: This register field is sticky." line.long 0x40 "EINJ6_CHANGE_POINT_H1_REG,Error Injection Control 6 (Change Point Header DWORD #1). Program this register for the 2nd DWORD of TLP header/prefix. It is necessary to carefully consider the endianness when you program this register. Bits [31:0] =.." hexmask.long 0x40 0.--31. 1. "EINJ6_CHANGE_POINT_H1,Packet Change Point: 2nd DWORD. Specifies which Tx TLP header DWORD#1 bits to replace with the corresponding bits in the Packet Change Value registers (EINJ6_CHANGE_VALUE*). Note: This register field is sticky." line.long 0x44 "EINJ6_CHANGE_POINT_H2_REG,Error Injection Control 6 (Change Point Header DWORD #2). Program this register for the 3rd DWORD of TLP header/prefix. It is necessary to carefully consider the endianness when you program this register. Bits [31:0] =.." hexmask.long 0x44 0.--31. 1. "EINJ6_CHANGE_POINT_H2,Packet Change Point: 3rd DWORD. Specifies which Tx TLP header DWORD#2 bits to replace with the corresponding bits in the Packet Change Value registers (EINJ6_CHANGE_VALUE*). Note: This register field is sticky." line.long 0x48 "EINJ6_CHANGE_POINT_H3_REG,Error Injection Control 6 (Change Point Header DWORD #3). Program this register for the 4th DWORD of TLP header/prefix. It is necessary to carefully consider the endianness when you program this register. Bits [31:0] =.." hexmask.long 0x48 0.--31. 1. "EINJ6_CHANGE_POINT_H3,Packet Change Point: 4th DWORD. Specifies which Tx TLP header DWORD#3 bits to replace with the corresponding bits in the Packet Change Value registers (EINJ6_CHANGE_VALUE*). Note: This register field is sticky." line.long 0x4C "EINJ6_CHANGE_VALUE_H0_REG,Error Injection Control 6 (Change Value Header DWORD #0). Program this register for the 1st DWORD of TLP header/prefix. It is necessary to carefully consider the endianness when you program this register. Bits [31:0] =.." hexmask.long 0x4C 0.--31. 1. "EINJ6_CHANGE_VALUE_H0,Packet Change Value: 1st DWORD. Specifies replacement values for the Tx TLP header DWORD#0 bits defined in the Packet Change Point registers (EINJ6_CHANGE_POINT*). Only applies when the EINJ6_INVERTED_CONTROL field in EINJ6_TLP_REG.." line.long 0x50 "EINJ6_CHANGE_VALUE_H1_REG,Error Injection Control 6 (Change Value Header DWORD #1). Program this register for the 2nd DWORD of TLP header/prefix. It is necessary to carefully consider the endianness when you program this register. Bits [31:0] =.." hexmask.long 0x50 0.--31. 1. "EINJ6_CHANGE_VALUE_H1,Packet Change Value: 2nd DWORD. Specifies replacement values for the Tx TLP header DWORD#1 bits defined in the Packet Change Point registers (EINJ6_CHANGE_POINT*). Only applies when the EINJ6_INVERTED_CONTROL field in EINJ6_TLP_REG.." line.long 0x54 "EINJ6_CHANGE_VALUE_H2_REG,Error Injection Control 6 (Change Value Header DWORD #2). Program this register for the 3rd DWORD of TLP header/prefix. It is necessary to carefully consider the endianness when you program this register. Bits [31:0] =.." hexmask.long 0x54 0.--31. 1. "EINJ6_CHANGE_VALUE_H2,Packet Change Value: 3rd DWORD. Specifies replacement values for the Tx TLP header DWORD#2 bits defined in the Packet Change Point registers (EINJ6_CHANGE_POINT*). Only applies when the EINJ6_INVERTED_CONTROL field in EINJ6_TLP_REG.." line.long 0x58 "EINJ6_CHANGE_VALUE_H3_REG,Error Injection Control 6 (Change Value Header DWORD #3). Program this register for the 4th DWORD of TLP header/prefix. It is necessary to carefully consider the endianness when you program this register. Bits [31:0] =.." hexmask.long 0x58 0.--31. 1. "EINJ6_CHANGE_VALUE_H3,Packet Change Value: 4th DWORD. Specifies replacement values for the Tx TLP header DWORD#3 bits defined in the Packet Change Point registers (EINJ6_CHANGE_POINT*). Only applies when the EINJ6_INVERTED_CONTROL field in EINJ6_TLP_REG.." line.long 0x5C "EINJ6_TLP_REG,Error Injection Control 6 (Packet Error). The Packet Compare Point registers (EINJ6_COMPARE_POINT*) specify which Tx TLP header bits to compare with the corresponding bits in the Packet Compare Value registers (EINJ6_COMPARE_VALUE*). When.." hexmask.long.tbyte 0x5C 12.--31. 1. "RSVDP_12,Reserved for future use." newline bitfld.long 0x5C 9.--11. "EINJ6_PACKET_TYPE,Packet type. Selects the TLP packets to inject errors into. - 0: TLP Header - 1: TLP Prefix 1st 4-DWORDs - 2: TLP Prefix 2nd -DWORDs - Else: Reserved Note: This register field is sticky." "TLP Header,TLP Prefix 1st 4-DWORDs,TLP Prefix 2nd -DWORDs,?,?,?,?,?" newline bitfld.long 0x5C 8. "EINJ6_INVERTED_CONTROL,Inverted Error Injection Control. - 0: EINJ6_CHANGE_VALUE_H[0/1/2/3] is used to replace bits specified by EINJ6_CHANGE_POINT_H[0/1/2/3]. - 1: EINJ6_CHANGE_VALUE_H[0/1/2/3] is ignored and inverts bits specified by.." "EINJ6_CHANGE_VALUE_H[0/1/2/3] is used to replace..,EINJ6_CHANGE_VALUE_H[0/1/2/3] is ignored and.." newline hexmask.long.byte 0x5C 0.--7. 1. "EINJ6_COUNT,Error Injection Count. Indicates the number of errors to insert. This counter is decremented while errors are been inserted. - If the counter value is 0x01 and error is inserted ERROR_INJECTION6_ENABLE in EINJ_ENABLE_REG returns '0'. - If.." group.long (0xA0+0x30C)++0x7 line.long 0x0 "SD_CONTROL1_REG,Silicon Debug Control 1. For more details. see the RAS DES section in the Core Operations chapter of the Databook." hexmask.long.byte 0x0 24.--31. 1. "RSVDP_24,Reserved for future use." newline bitfld.long 0x0 22.--23. "LOW_POWER_INTERVAL,Low Power Entry Interval Time. Interval Time that the controller starts monitoring RXELECIDLE signal after L0s/L1/L2 entry. You should set the value according to the latency from receiving EIOS to RXELECIDLE assertion at the PHY. -.." "0,1,2,3" newline bitfld.long 0x0 20.--21. "TX_EIOS_NUM,Number of Tx EIOS. This register sets the number of transmit EIOS for L0s/L1 entry and Disable/Loopback/Hot-reset exit. The controller selects the greater value between this register and the value defined by the PCI-SIG specification. 2.5GT/s.." "0,1,2,3" newline rbitfld.long 0x0 17.--19. "RSVDP_17,Reserved for future use." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 16. "FORCE_DETECT_LANE_EN,Force Detect Lane Enable. When this bit is set the controller ignores receiver detection from PHY during LTSSM Detect state and uses FORCE_DETECT_LANE. Note: This register field is sticky." "0,1" newline hexmask.long.word 0x0 0.--15. 1. "FORCE_DETECT_LANE,Force Detect Lane. When the FORCE_DETECT_LANE_EN field is set the controller ignores receiver detection from PHY during LTSSM Detect state and uses this value instead. - 0: Lane0 - 1: Lane1 - 2: Lane2 - .. - 15: Lane15 Note: This.." line.long 0x4 "SD_CONTROL2_REG,Silicon Debug Control 2. For more details. see the RAS DES section in the Core Operations chapter of the Databook." hexmask.long.word 0x4 17.--31. 1. "RSVDP_17,Reserved for future use." newline bitfld.long 0x4 16. "FRAMING_ERR_RECOVERY_DISABLE,Framing Error Recovery Disable. This bit disables a transition to Recovery state when a Framing Error is occurred. Note: This register field is sticky." "0,1" newline hexmask.long.byte 0x4 11.--15. 1. "RSVDP_11,Reserved for future use." newline bitfld.long 0x4 10. "DIRECT_LPBKSLV_TO_EXIT,Direct Loopback Slave To Exit. When this bit is set and the LTSSM is in Loopback Slave Active State the LTSSM transitions to Loopback Slave Exit state. Note: This register field is sticky." "0,1" newline bitfld.long 0x4 9. "DIRECT_POLCOMP_TO_DETECT,Direct Polling.Compliance to Detect. When this bit is set and the LTSSM is in Polling Compliance State the LTSSM transitions to Detect state. Note: This register field is sticky." "0,1" newline bitfld.long 0x4 8. "DIRECT_RECIDLE_TO_CONFIG,Direct Recovery.Idle to Configuration. When this bit is set and the LTSSM is in Recovery Idle State the LTSSM transitions to Configuration state. Note: This register field is sticky." "0,1" newline hexmask.long.byte 0x4 3.--7. 1. "RSVDP_3,Reserved for future use." newline bitfld.long 0x4 2. "NOACK_FORCE_LINKDOWN,Force LinkDown. When this bit is set and the controller detects REPLY_NUM rolling over 4 times the LTSSM transitions to Detect State. Note: This register field is sticky." "0,1" newline bitfld.long 0x4 1. "RECOVERY_REQUEST,Recovery Request. When this bit is set to '1' in L0 or L0s the LTSSM starts transitioning to Recovery State. This request does not cause a speed change or re-equalization." "0,1" newline bitfld.long 0x4 0. "HOLD_LTSSM,Hold and Release LTSSM. For as long as this register is '1' the controller stays in the current LTSSM. Note: This register field is sticky." "0,1" group.long (0xB0+0x30C)++0xB line.long 0x0 "SD_STATUS_L1LANE_REG,Silicon Debug Status(Layer1 Per-lane). This viewport register returns the data selected by the following field: - LANE_SELECT in SD_STATUS_L1LANE_REG For more details. see the RAS DES section in the Core Operations chapter of the.." hexmask.long.byte 0x0 24.--31. 1. "DESKEW_POINTER,Deskew Pointer. Indicates Deskew pointer of internal Deskew buffer of selected lane number(LANE_SELECT). Note: This register field is sticky." newline rbitfld.long 0x0 21.--23. "RSVDP_21,Reserved for future use." "0,1,2,3,4,5,6,7" newline rbitfld.long 0x0 20. "PIPE_TXELECIDLE,PIPE:TxElecIdle. Indicates PIPE TXELECIDLE signal of selected lane number(LANE_SELECT). Note: This register field is sticky." "0,1" newline rbitfld.long 0x0 19. "PIPE_RXELECIDLE,PIPE:RxElecIdle. Indicates PIPE RXELECIDLE signal of selected lane number(LANE_SELECT). Note: This register field is sticky." "0,1" newline rbitfld.long 0x0 18. "PIPE_RXVALID,PIPE:RxValid. Indicates PIPE RXVALID signal of selected lane number(LANE_SELECT). Note: This register field is sticky." "0,1" newline rbitfld.long 0x0 17. "PIPE_DETECT_LANE,PIPE:Detect Lane. Indicates whether PHY indicates receiver detection or not on selected lane number(LANE_SELECT). Note: This register field is sticky." "0,1" newline rbitfld.long 0x0 16. "PIPE_RXPOLARITY,PIPE:RxPolarity. Indicates PIPE RXPOLARITY signal of selected lane number(LANE_SELECT). Note: This register field is sticky." "0,1" newline hexmask.long.word 0x0 4.--15. 1. "RSVDP_4,Reserved for future use." newline hexmask.long.byte 0x0 0.--3. 1. "LANE_SELECT,Lane Select. Lane Select register for Silicon Debug Status Register of Layer1-PerLane. - 0x0: Lane0 - 0x1: Lane1 - 0x2: Lane2 - .. - 0xF: Lane15 Note: This register field is sticky." line.long 0x4 "SD_STATUS_L1LTSSM_REG,Silicon Debug Status(Layer1 LTSSM). For more details. see the RAS DES section in the Core Operations chapter of the Databook." hexmask.long.word 0x4 16.--31. 1. "LTSSM_VARIABLE,LTSSM Variable. Indicates internal LTSSM variables defined in the PCI Express Base Specification. C-PCIe Mode: - 0: directed_speed_change - 1: changed_speed_recovery - 2: successful_speed_negotiation - 3: upconfigure_capable; Set to '1' if.." newline rbitfld.long 0x4 15. "LANE_REVERSAL,Lane Reversal Operation. Receiver detected lane reversal. This field is only valid in the L0 LTSSM state. Note: This register field is sticky." "0,1" newline hexmask.long.byte 0x4 11.--14. 1. "RSVDP_11,Reserved for future use." newline rbitfld.long 0x4 8.--10. "PIPE_POWER_DOWN,PIPE:PowerDown. Indicates PIPE PowerDown signal. Note: This register field is sticky." "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 7. "FRAMING_ERR,Framing Error. Indicates Framing Error detection status." "0,1" newline hexmask.long.byte 0x4 0.--6. 1. "FRAMING_ERR_PTR,First Framing Error Pointer. Identifies the first Framing Error using the following encoding. The field contents are only valid value when FRAMING_ERR =1. Received Unexpected Framing Token - 01h: When non- STP/SDP/IDL Token was received.." line.long 0x8 "SD_STATUS_PM_REG,Silicon Debug Status(PM). For more details. see the RAS DES section in the Core Operations chapter of the Databook." hexmask.long.byte 0x8 24.--31. 1. "RSVDP_24,Reserved for future use." newline hexmask.long.byte 0x8 16.--23. 1. "LATCHED_NFTS,Latched N_FTS. Indicates the value of N_FTS in the received TS Ordered Sets from the Link Partner Note: This register field is sticky." newline rbitfld.long 0x8 13.--15. "L1SUB_STATE,L1Sub State. Indicates internal state machine of L1Sub state. - 0h: S_L1_U : idle state - 1h: S_L1_0 : wait for aux_clk_active - 2h: S_L1_0_WAIT4_ACK : wait for pclkack - 3h: S_L1_0_WAIT4_CLKREQ : wait for clkreq - 4h: S_L1_N_ENTRY : check.." "wait for aux_clk_active,?,?,?,?,?,?,?" newline bitfld.long 0x8 12. "PME_RESEND_FLAG,PME Re-send flag. When the DUT sends a PM_PME message TLP the DUT sets PME_Status bit. If host software does not clear PME_Status bit for 100ms(+50%/-5%) the DUT resends the PM_PME Message. This bit indicates that a PM_PME was resent." "0,1" newline hexmask.long.byte 0x8 8.--11. 1. "INTERNAL_PM_SSTATE,Internal PM State(Slave). Indicates internal state machine of Power Management Slave controller. - 0h: S_IDLE - 1h: S_RESPOND_NAK - 2h: S_BLOCK_TLP - 3h: S_WAIT_LAST_TLP_ACK - 4h: S_WAIT_EIDLE - 5h: S_LINK_ENTR_L1 - 6h: S_L1 - 7h:.." newline rbitfld.long 0x8 5.--7. "RSVDP_5,Reserved for future use." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x8 0.--4. 1. "INTERNAL_PM_MSTATE,Internal PM State(Master). Indicates internal state machine of Power Management Master controller. - 00h: IDLE - 01h: L0 - 02h: L0S - 03h: ENTER_L0S - 04h: L0S_EXIT - 05h: WAIT_PMCSR_CPL_SENT - 08h: L1 - 09h: L1_BLOCK_TLP - 0Ah:.." rgroup.long (0xBC+0x30C)++0x3 line.long 0x0 "SD_STATUS_L2_REG,Silicon Debug Status(Layer2). For more details. see the RAS DES section in the Core Operations chapter of the Databook." hexmask.long.byte 0x0 28.--31. 1. "RSVDP_28,Reserved for future use." newline bitfld.long 0x0 27. "FC_INIT2,FC_INIT2. Indicates the controller is in FC_INIT2(VC0) state. Note: This register field is sticky." "0,1" newline bitfld.long 0x0 26. "FC_INIT1,FC_INIT1. Indicates the controller is in FC_INIT1(VC0) state. Note: This register field is sticky." "0,1" newline bitfld.long 0x0 24.--25. "DLCMSM,DLCMSM. Indicates the current DLCMSM. - 00b: DL_INACTIVE - 01b: DL_FC_INIT - 11b: DL_ACTIVE Note: This register field is sticky." "0,1,2,3" newline hexmask.long.word 0x0 12.--23. 1. "RX_ACK_SEQ_NO,Tx Ack Sequence Number. Indicates ACKD_SEQ which is updated by receiving ACK/NAK DLLP. Note: This register field is sticky." newline hexmask.long.word 0x0 0.--11. 1. "TX_TLP_SEQ_NO,Tx Tlp Sequence Number. Indicates next transmit sequence number for transmit TLP. Note: This register field is sticky." group.long (0xC0+0x30C)++0x7 line.long 0x0 "SD_STATUS_L3FC_REG,Silicon Debug Status(Layer3 FC). The CREDIT_DATA[0/1] fields in this viewport register return the data for the VC and TLP Type selected by the following fields: - CREDIT_SEL_VC - CREDIT_SEL_CREDIT_TYPE - CREDIT_SEL_TLP_TYPE -.." hexmask.long.word 0x0 20.--31. 1. "CREDIT_DATA1,Credit Data1. Current FC credit data selected by the CREDIT_SEL_VC CREDIT_SEL_CREDIT_TYPE CREDIT_SEL_TLP_TYPE and CREDIT_SEL_HD viewport-select fields. - Rx: Credit Allocated Value - Tx: Credit Limit Value. This value is valid when.." newline hexmask.long.word 0x0 8.--19. 1. "CREDIT_DATA0,Credit Data0. Current FC credit data selected by the CREDIT_SEL_VC CREDIT_SEL_CREDIT_TYPE CREDIT_SEL_TLP_TYPE and CREDIT_SEL_HD viewport-select fields. - Rx: Credit Received Value - Tx: Credit Consumed Value Note: This register field is.." newline rbitfld.long 0x0 7. "RSVDP_7,Reserved for future use." "0,1" newline bitfld.long 0x0 6. "CREDIT_SEL_HD,Credit Select(HeaderData). This field in conjunction with the CREDIT_SEL_VC CREDIT_SEL_CREDIT_TYPE and CREDIT_SEL_TLP_TYPE viewport-select fields determines that data that is returned by the CREDIT_DATA0 and CREDIT_DATA1 data fields. -.." "Header Credit,Data Credit" newline bitfld.long 0x0 4.--5. "CREDIT_SEL_TLP_TYPE,Credit Select(TLP Type). This field in conjunction with the CREDIT_SEL_VC CREDIT_SEL_CREDIT_TYPE and CREDIT_SEL_HD viewport-select fields determines that data that is returned by the CREDIT_DATA0 and CREDIT_DATA1 data fields. - 0x0:.." "Posted,Non-Posted,Completion,?" newline bitfld.long 0x0 3. "CREDIT_SEL_CREDIT_TYPE,Credit Select(Credit Type). This field in conjunction with the CREDIT_SEL_VC CREDIT_SEL_TLP_TYPE and CREDIT_SEL_HD viewport-select fields determines that data that is returned by the CREDIT_DATA0 and CREDIT_DATA1 data fields. -.." "Rx,Tx" newline bitfld.long 0x0 0.--2. "CREDIT_SEL_VC,Credit Select(VC). This field in conjunction with the CREDIT_SEL_CREDIT_TYPE CREDIT_SEL_TLP_TYPE and CREDIT_SEL_HD viewport-select fields determines that data that is returned by the CREDIT_DATA0 and CREDIT_DATA1 data fields. - 0x0: VC0 -.." "VC0,VC1,VC2,?,?,?,?,VC7" line.long 0x4 "SD_STATUS_L3_REG,Silicon Debug Status(Layer3). For more details. see the RAS DES section in the Core Operations chapter of the Databook." hexmask.long.tbyte 0x4 8.--31. 1. "RSVDP_8,Reserved for future use." newline bitfld.long 0x4 7. "MFTLP_STATUS,Malformed TLP Status. Indicates malformed TLP has occurred." "0,1" newline hexmask.long.byte 0x4 0.--6. 1. "MFTLP_POINTER,First Malformed TLP Error Pointer. Indicates the element of the received first malformed TLP. This pointer is validated by MFTLP_STATUS. - 01h: AtomicOp address alignment - 02h: AtomicOp operand - 03h: AtomicOp byte enable - 04h: TLP length.." group.long (0xD0+0x30C)++0xB line.long 0x0 "SD_EQ_CONTROL1_REG,Silicon Debug EQ Control 1. This is a viewport control register. Setting the EQ_RATE_SEL and EQ_LANE_SEL fields in this register determine the per-lane Silicon Debug EQ Status data returned by the SD_EQ_STATUS[1/2/3] viewport.." hexmask.long.byte 0x0 24.--31. 1. "FOM_TARGET,FOM Target. Indicates figure of merit target criteria value of EQ Master(DSP in EQ Phase3/USP in EQ Phase2). This field is only valid when GEN3_EQ_FB_MODE is 0001b(Figure Of Merit). Note: This register field is sticky." newline bitfld.long 0x0 23. "FOM_TARGET_ENABLE,FOM Target Enable. Enables the FOM_TARGET fields. Note: This register field is sticky." "0,1" newline hexmask.long.byte 0x0 18.--22. 1. "RSVDP_18,Reserved for future use." newline bitfld.long 0x0 16.--17. "EVAL_INTERVAL_TIME,Eval Interval Time. Indicates interval time of RxEqEval assertion. - 00: 500ns - 01: 1us - 10: 2us - 11: 4us This field is used for EQ Master(DSP in EQ Phase3/USP in EQ Phase2). Note: This register field is sticky." "0,1,2,3" newline hexmask.long.byte 0x0 10.--15. 1. "RSVDP_10,Reserved for future use." newline bitfld.long 0x0 8.--9. "EXT_EQ_TIMEOUT,Extends EQ Phase2/3 Timeout. This field is used when the Ltssm is in Recovery.EQ2/3. When this field is set the value of EQ2/3 timeout is extended. EQ Master(DSP in EQ Phase3/USP in EQ Phase2). - 00: 24ms (default) - 01: 48ms (x2) - 10:.." "0,1,2,3" newline rbitfld.long 0x0 6.--7. "RSVDP_6,Reserved for future use." "0,1,2,3" newline bitfld.long 0x0 4.--5. "EQ_RATE_SEL,EQ Status Rate Select. Setting this field in conjunction with the EQ_LANE_SEL field determines the per-lane Silicon Debug EQ Status data returned by the SD_EQ_CONTROL[2/3] and SD_EQ_STATUS[1/2/3] viewport registers. - 0x0: 8.0GT/s Speed.." "0,1,2,3" newline hexmask.long.byte 0x0 0.--3. 1. "EQ_LANE_SEL,EQ Status Lane Select. Setting this field in conjunction with the EQ_RATE_SEL field determines the per-lane Silicon Debug EQ Status data returned by the SD_EQ_CONTROL[2/3] and SD_EQ_STATUS[1/2/3] viewport registers. - 0x0: Lane0 - 0x1: Lane1.." line.long 0x4 "SD_EQ_CONTROL2_REG,Silicon Debug EQ Control 2. This viewport register returns the value for the rate and lane selected by the EQ_RATE_SEL and EQ_LANE_SEL fields in the SD_EQ_CONTROL1_REG register. For more details. see the RAS DES section in the Core.." rbitfld.long 0x4 31. "RSVDP_31,Reserved for future use." "0,1" newline bitfld.long 0x4 30. "FORCE_LOCAL_TX_PRESET_ENABLE,Force Local Transmitter Preset Enable. Enables the FORCE_LOCAL_TX_PRESET field. If select rate in the EQ_RATE_SEL field is 32.0GT/s Speed this feature is not available. Note: This register field is sticky." "0,1" newline bitfld.long 0x4 29. "FORCE_LOCAL_RX_HINT_ENABLE,Force Local Receiver Preset Hint Enable. Enables the FORCE_LOCAL_RX_HINT field. If select rate in the EQ_RATE_SEL field is other than 8.0GT/s Speed this feature is not available. Note: This register field is sticky." "0,1" newline bitfld.long 0x4 28. "FORCE_LOCAL_TX_COEF_ENABLE,Force Local Transmitter Coefficient Enable. Enables the following fields: - FORCE_LOCAL_TX_PRE_CURSOR - FORCE_LOCAL_TX_CURSOR - FORCE_LOCAL_TX_POST_CURSOR Note: This register field is sticky." "0,1" newline hexmask.long.byte 0x4 24.--27. 1. "FORCE_LOCAL_TX_PRESET,Force Local Transmitter Preset. Indicates initial preset value of USP in EQ Slave(EQ Phase2) instead of receiving EQ TS2. If select rate in the EQ_RATE_SEL field is 32.0GT/s Speed this feature is not available. Note: This register.." newline rbitfld.long 0x4 21.--23. "RSVDP_21,Reserved for future use." "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 18.--20. "FORCE_LOCAL_RX_HINT,Force Local Receiver Preset Hint. Indicates the RxPresetHint value of EQ Slave(DSP in EQ Phase2/USP in EQ Phase3) instead of received or set value. If select rate in the EQ_RATE_SEL field is other than 8.0GT/s Speed this feature is.." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x4 12.--17. 1. "FORCE_LOCAL_TX_POST_CURSOR,Force Local Transmitter Post-Cursor. Indicates the coefficient value of EQ Slave(DSP in EQ Phase2/USP in EQ Phase3) instead of the value instructed from link partner. Note: This register field is sticky." newline hexmask.long.byte 0x4 6.--11. 1. "FORCE_LOCAL_TX_CURSOR,Force Local Transmitter Cursor. Indicates the coefficient value of EQ Slave(DSP in EQ Phase2/USP in EQ Phase3) instead of the value instructed from link partner. Note: This register field is sticky." newline hexmask.long.byte 0x4 0.--5. 1. "FORCE_LOCAL_TX_PRE_CURSOR,Force Local Transmitter Pre-cursor. Indicates the coefficient value of EQ Slave(DSP in EQ Phase2/USP in EQ Phase3) instead of the value instructed from link partner. Note: This register field is sticky." line.long 0x8 "SD_EQ_CONTROL3_REG,Silicon Debug EQ Control 3. This viewport register returns the value for the rate and lane selected by the EQ_RATE_SEL and EQ_LANE_SEL fields in the SD_EQ_CONTROL1_REG register. For more details. see the RAS DES section in the Core.." rbitfld.long 0x8 29.--31. "RSVDP_29,Reserved for future use." "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 28. "FORCE_REMOTE_TX_COEF_ENABLE,Force Remote Transmitter Coefficient Enable. Enables the following fields: - FORCE_REMOTE_TX_PRE_CURSOR - FORCE_REMOTE_TX_CURSOR - FORCE_REMOTE_TX_POST_CURSOR This function can only be used when GEN3_EQ_FB_MODE =.." "0,1" newline hexmask.long.word 0x8 18.--27. 1. "RSVDP_18,Reserved for future use." newline hexmask.long.byte 0x8 12.--17. 1. "FORCE_REMOTE_TX_POST_CURSOR,Force Remote Transmitter Post-Cursor. Indicates the coefficient value of EQ Master(DSP in EQ Phase3/USP in EQ Phase2) instead of the value instructed from local phy in dirchange mode. Note: This register field is sticky." newline hexmask.long.byte 0x8 6.--11. 1. "FORCE_REMOTE_TX_CURSOR,Force Remote Transmitter Cursor. Indicates the coefficient value of EQ Master(DSP in EQ Phase3/USP in EQ Phase2) instead of the value instructed from local phy in dirchange mode. Note: This register field is sticky." newline hexmask.long.byte 0x8 0.--5. 1. "FORCE_REMOTE_TX_PRE_CURSOR,Force Remote Transmitter Pre-Cursor. Indicates the coefficient value of EQ Master(DSP in EQ Phase3/USP in EQ Phase2) instead of the value instructed from local phy in dirchange mode. Note: This register field is sticky." rgroup.long (0xE0+0x30C)++0xB line.long 0x0 "SD_EQ_STATUS1_REG,Silicon Debug EQ Status 1. This viewport register returns the first of three words of Silicon Debug EQ Status data for the rate and lane selected by the EQ_RATE_SEL and EQ_LANE_SEL fields in the SD_EQ_CONTROL1_REG register. The.." hexmask.long.tbyte 0x0 8.--31. 1. "RSVDP_8,Reserved for future use." newline bitfld.long 0x0 7. "EQ_REJECT_EVENT,EQ Reject Event. Indicates that the controller receives two consecutive TS1 OS w/Reject=1b during EQ Master phase(DSP in EQ Phase3/USP in EQ Phase2). This bit is automatically cleared when the controller starts EQ Master phase again." "0,1" newline bitfld.long 0x0 6. "EQ_RULEC_VIOLATION,EQ Rule C Violation. Indicates that coefficients rule C violation is detected in the values provided by PHY using direction change method during EQ Master phase(DSP in EQ Phase3/USP in EQ Phase2). The coefficients rule C correspond to.." "0,1" newline bitfld.long 0x0 5. "EQ_RULEB_VIOLATION,EQ Rule B Violation. Indicates that coefficients rule B violation is detected in the values provided by PHY using direction change method during EQ Master phase(DSP in EQ Phase3/USP in EQ Phase2). The coefficients rules B correspond to.." "0,1" newline bitfld.long 0x0 4. "EQ_RULEA_VIOLATION,EQ Rule A Violation. Indicates that coefficients rule A violation is detected in the values provided by PHY using direction change method during EQ Master phase(DSP in EQ Phase3/USP in EQ Phase2). The coefficients rules A correspond to.." "0,1" newline bitfld.long 0x0 3. "RSVDP_3,Reserved for future use." "0,1" newline bitfld.long 0x0 1.--2. "EQ_CONVERGENCE_INFO,EQ Convergence Info. Indicates equalization convergence information. - 0x0: Equalization is not attempted - 0x1: Equalization finished successfully - 0x2: Equalization finished unsuccessfully - 0x3: Reserved This bit is automatically.." "Equalization is not attempted,Equalization finished successfully,Equalization finished unsuccessfully,Reserved" newline bitfld.long 0x0 0. "EQ_SEQUENCE,EQ Sequence. Indicates that the controller is starting the equalization sequence. Note: This register field is sticky." "0,1" line.long 0x4 "SD_EQ_STATUS2_REG,Silicon Debug EQ Status 2. This viewport register returns the second of three words of Silicon Debug EQ Status data for the rate and lane selected by the EQ_RATE_SEL and EQ_LANE_SEL fields in the SD_EQ_CONTROL1_REG register. Each field.." hexmask.long.byte 0x4 24.--31. 1. "EQ_LOCAL_FOM_VALUE,EQ Local Figure of Merit. Indicates Local maximum Figure of Merit value. Note: This register field is sticky." newline bitfld.long 0x4 21.--23. "RSVDP_21,Reserved for future use." "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 18.--20. "EQ_LOCAL_RX_HINT,EQ Local Receiver Preset Hint. Indicates Local Receiver Preset Hint value. If select rate in the EQ_RATE_SEL field is other than 8.0GT/s Speed this feature is not available. Note: This register field is sticky." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x4 12.--17. 1. "EQ_LOCAL_POST_CURSOR,EQ Local Post-Cursor. Indicates Local post cursor coefficient value. Note: This register field is sticky." newline hexmask.long.byte 0x4 6.--11. 1. "EQ_LOCAL_CURSOR,EQ Local Cursor. Indicates Local cursor coefficient value. Note: This register field is sticky." newline hexmask.long.byte 0x4 0.--5. 1. "EQ_LOCAL_PRE_CURSOR,EQ Local Pre-Cursor. Indicates Local pre cursor coefficient value. Note: This register field is sticky." line.long 0x8 "SD_EQ_STATUS3_REG,Silicon Debug EQ Status 3. This viewport register returns the third of three words of Silicon Debug EQ Status data for the rate and lane selected by the EQ_RATE_SEL and EQ_LANE_SEL fields in the SD_EQ_CONTROL1_REG register. Each field.." bitfld.long 0x8 30.--31. "RSVDP_30,Reserved for future use." "0,1,2,3" newline hexmask.long.byte 0x8 24.--29. 1. "EQ_REMOTE_FS,EQ Remote FS. Indicates Remote FS value. Note: This register field is sticky." newline hexmask.long.byte 0x8 18.--23. 1. "EQ_REMOTE_LF,EQ Remote LF. Indicates Remote LF value. Note: This register field is sticky." newline hexmask.long.byte 0x8 12.--17. 1. "EQ_REMOTE_POST_CURSOR,EQ Remote Post-Cursor. Indicates Remote post cursor coefficient value. Note: This register field is sticky." newline hexmask.long.byte 0x8 6.--11. 1. "EQ_REMOTE_CURSOR,EQ Remote Cursor. Indicates Remote cursor coefficient value. Note: This register field is sticky." newline hexmask.long.byte 0x8 0.--5. 1. "EQ_REMOTE_PRE_CURSOR,EQ Remote Pre-Cursor. Indicates Remote pre cursor coefficient value. Note: This register field is sticky." tree.end tree "PF0_SN_CAP (Device Serial Number Capability Structure)" group.long (0x0+0x170)++0xB line.long 0x0 "SN_BASE,Device Serial Number Extended Capability Header. For a description of this standard PCIe register. see the PCI Express Base Specification." hexmask.long.word 0x0 20.--31. 1. "SN_NEXT_OFFSET,Next Capability Offset. For a description of this standard PCIe register field see the PCI Express Base Specification. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then.." hexmask.long.byte 0x0 16.--19. 1. "SN_CAP_VERSION,Capability Version. For a description of this standard PCIe register field see the PCI Express Base Specification. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky).." hexmask.long.word 0x0 0.--15. 1. "SN_PCIE_EXTENDED_CAP_ID,Serial Number Extended Capability ID. For a description of this standard PCIe register field see the PCI Express Base Specification. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if.." line.long 0x4 "SER_NUM_REG_DW_1,Serial Number 1 Register. For a description of this standard PCIe register. see the PCI Express Base Specification." hexmask.long 0x4 0.--31. 1. "SN_SER_NUM_REG_1_DW,IEEE 64 bit Device Serial Number (DW 1). For a description of this standard PCIe register field see the PCI Express Base Specification. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if.." line.long 0x8 "SER_NUM_REG_DW_2,Serial Number 2 Register. For a description of this standard PCIe register. see the PCI Express Base Specification." hexmask.long 0x8 0.--31. 1. "SN_SER_NUM_REG_2_DW,IEEE 64 bit Device Serial Number (DW 2). For a description of this standard PCIe register field see the PCI Express Base Specification. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if.." tree.end tree "PF0_VSECRAS_CAP (PF RAS Datapath Protection Capability Structure (VSEC))" group.long (0x0+0x480)++0x3 line.long 0x0 "RASDP_EXT_CAP_HDR_OFF,PCIe Extended capability ID. Capability version and Next capability offset. For a description of this standard PCIe register. see the PCI Express Specification." hexmask.long.word 0x0 20.--31. 1. "NEXT_OFFSET,Next Capability Offset. For a description of this standard PCIe register see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else.." newline hexmask.long.byte 0x0 16.--19. 1. "CAP,Capability Version. For a description of this standard PCIe register see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note:.." newline hexmask.long.word 0x0 0.--15. 1. "ID,PCI Express Extended Capability ID. For a description of this standard PCIe register see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else.." rgroup.long (0x4+0x480)++0x3 line.long 0x0 "RASDP_VENDOR_SPECIFIC_HDR_OFF,Vendor Specific Header. For a description of this standard PCIe register. see the PCI Express Specification." hexmask.long.word 0x0 20.--31. 1. "VSEC_LENGTH,VSEC Length. For a description of this standard PCIe register see the PCI Express Specification. Note: This register field is sticky." newline hexmask.long.byte 0x0 16.--19. 1. "VSEC_REV,VSEC Rev. For a description of this standard PCIe register see the PCI Express Specification. Note: This register field is sticky." newline hexmask.long.word 0x0 0.--15. 1. "VSEC_ID,VSEC ID. For a description of this standard PCIe register see the PCI Express Specification. Note: This register field is sticky." group.long (0x8+0x480)++0x7 line.long 0x0 "RASDP_ERROR_PROT_CTRL_OFF,ECC error correction control. Allows you to disable ECC error correction for RAMs and datapath. When the AXI Bridge Module is implemented and the master / slave clocks are asynchronous to the PCIe native controller clock.." hexmask.long.byte 0x0 24.--31. 1. "RSVDP_24,Reserved for future use." newline bitfld.long 0x0 23. "ERROR_PROT_DISABLE_CXS_RX,Error correction disable for CXS Tx path (PCIe Rx path). Note: This register field is sticky." "0,1" newline bitfld.long 0x0 22. "ERROR_PROT_DISABLE_ADM_RX,Error correction disable for ADM Rx path. Note: This register field is sticky." "0,1" newline bitfld.long 0x0 21. "ERROR_PROT_DISABLE_LAYER3_RX,Error correction disable for layer 3 Rx path. Note: This register field is sticky." "0,1" newline bitfld.long 0x0 20. "ERROR_PROT_DISABLE_LAYER2_RX,Error correction disable for layer 2 Rx path. Note: This register field is sticky." "0,1" newline bitfld.long 0x0 19. "ERROR_PROT_DISABLE_DMA_READ,Error correction disable for DMA read engine. Note: This register field is sticky." "0,1" newline bitfld.long 0x0 18. "ERROR_PROT_DISABLE_AXI_BRIDGE_INBOUND_REQUEST,Error correction disable for AXI bridge inbound request path. Note: This register field is sticky." "0,1" newline bitfld.long 0x0 17. "ERROR_PROT_DISABLE_AXI_BRIDGE_INBOUND_COMPLETION,Error correction disable for AXI bridge inbound completion composer. Does not disable the error detection reporting for 1-bit and 2-bit ECC errors. Note: This register field is sticky." "?,bit and 2-bit ECC errors" newline bitfld.long 0x0 16. "ERROR_PROT_DISABLE_RX,Global error correction disable for all Rx layers. Note: This register field is sticky." "0,1" newline hexmask.long.byte 0x0 9.--15. 1. "RSVDP_9,Reserved for future use." newline bitfld.long 0x0 8. "ERROR_PROT_DISABLE_DTIM_TX,Error correction disable for DTIM Tx path. Note: This register field is sticky." "0,1" newline bitfld.long 0x0 7. "ERROR_PROT_DISABLE_CXS_TX,Error correction disable for CXS Rx path (PCIe Tx path). Note: This register field is sticky." "0,1" newline bitfld.long 0x0 6. "ERROR_PROT_DISABLE_ADM_TX,Error correction disable for Adm Tx path. Note: This register field is sticky." "0,1" newline bitfld.long 0x0 5. "ERROR_PROT_DISABLE_LAYER3_TX,Error correction disable for layer 3 Tx path. Note: This register field is sticky." "0,1" newline bitfld.long 0x0 4. "ERROR_PROT_DISABLE_LAYER2_TX,Error correction disable for layer 2 Tx path. Note: This register field is sticky." "0,1" newline bitfld.long 0x0 3. "ERROR_PROT_DISABLE_DMA_WRITE,Error correction disable for DMA write engine. Note: This register field is sticky." "0,1" newline bitfld.long 0x0 2. "ERROR_PROT_DISABLE_AXI_BRIDGE_OUTBOUND,Error correction disable for AXI bridge outbound request path. Note: This register field is sticky." "0,1" newline bitfld.long 0x0 1. "ERROR_PROT_DISABLE_AXI_BRIDGE_MASTER,Error correction disable for AXI bridge master completion buffer. Note: This register field is sticky." "0,1" newline bitfld.long 0x0 0. "ERROR_PROT_DISABLE_TX,Global error correction disable for all Tx layers. Does not disable the error detection reporting for 1-bit and 2-bit ECC errors. Note: This register field is sticky." "?,bit and 2-bit ECC errors" line.long 0x4 "RASDP_CORR_COUNTER_CTRL_OFF,Corrected error (1-bit ECC) counter selection and control. This is a viewport control register. Setting the CORR_COUNTER_SELECTION_REGION and CORR_COUNTER_SELECTION fields in this register determine the counter data returned.." hexmask.long.byte 0x4 24.--31. 1. "CORR_COUNTER_SELECTION,Counter selection. This field selects the counter ID (within the region defined by CORR_COUNTER_SELECTION_REGION) whose contents can be read from the RASDP_CORR_COUNT_REPORT_OFF register. You can cycle this field value from 0 to.." newline hexmask.long.byte 0x4 20.--23. 1. "CORR_COUNTER_SELECTION_REGION,Select correctable counter region: - 0x0: Region select for Adm Rx path - 0x1: Region select for layer 3 Rx path - 0x2: Region select for layer 2 Rx path - 0x3: Region select for DMA inbound path - 0x4: Region select for AXI.." newline hexmask.long.word 0x4 5.--19. 1. "RSVDP_5,Reserved for future use." newline bitfld.long 0x4 4. "CORR_EN_COUNTERS,Enable correctable errors counters. - 1: counters increment when the controller detects a correctable error - 0: counters are frozen The counters are enabled by default." "counters are frozen,counters increment when the controller detects a.." newline rbitfld.long 0x4 1.--3. "RSVDP_1,Reserved for future use." "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 0. "CORR_CLEAR_COUNTERS,Clear all correctable error counters." "0,1" rgroup.long (0x10+0x480)++0x3 line.long 0x0 "RASDP_CORR_COUNT_REPORT_OFF,Corrected error (1-bit ECC) counter data. This viewport register returns the counter data selected by the CORR_COUNTER_SELECTION_REGION and CORR_COUNTER_SELECTION fields in the RASDP_CORR_COUNTER_CTRL_OFF register." hexmask.long.byte 0x0 24.--31. 1. "CORR_COUNTER_SELECTED,Counter selection. Returns the value set in the CORR_COUNTER_SELECTION field of the RASDP_CORR_COUNTER_CTRL_OFF register." newline hexmask.long.byte 0x0 20.--23. 1. "CORR_COUNTER_SELECTED_REGION,Selected correctable counter region: - 0x0: Region select for Adm Rx path - 0x1: Region select for layer 3 Rx path - 0x2: Region select for layer 2 Rx path - 0x3: Region select for DMA inbound path - 0x4: Region select for.." newline hexmask.long.word 0x0 8.--19. 1. "RSVDP_8,Reserved for future use." newline hexmask.long.byte 0x0 0.--7. 1. "CORR_COUNTER,Current corrected error count for the selected counter." group.long (0x14+0x480)++0x3 line.long 0x0 "RASDP_UNCORR_COUNTER_CTRL_OFF,Uncorrected error (2-bit ECC and parity) counter selection and control. This is a viewport control register. Setting the UNCORR_COUNTER_SELECTION_REGION and UNCORR_COUNTER_SELECTION fields in this register determine the.." hexmask.long.byte 0x0 24.--31. 1. "UNCORR_COUNTER_SELECTION,Counter selection. This field selects the counter ID (within the region defined by UNCORR_COUNTER_SELECTION_REGION) whose contents can be read from the RASDP_UNCORR_COUNT_REPORT_OFF register. You can cycle this field value from 0.." newline hexmask.long.byte 0x0 20.--23. 1. "UNCORR_COUNTER_SELECTION_REGION,Select uncorrectable counter region: - 0x0: Region select for Adm Rx path - 0x1: Region select for layer 3 Rx path - 0x2: Region select for layer 2 Rx path - 0x3: Region select for DMA inbound path - 0x4: Region select for.." newline hexmask.long.word 0x0 5.--19. 1. "RSVDP_5,Reserved for future use." newline bitfld.long 0x0 4. "UNCORR_EN_COUNTERS,Enable uncorrectable errors counters. - 1: enables the counters to increment on detected correctable errors - 0: counters are frozen The counters are enabled by default." "counters are frozen,enables the counters to increment on detected.." newline rbitfld.long 0x0 1.--3. "RSVDP_1,Reserved for future use." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 0. "UNCORR_CLEAR_COUNTERS,Clear uncorrectable errors counters. When asserted causes all counters tracking the uncorrectable errors to be cleared." "0,1" rgroup.long (0x18+0x480)++0x3 line.long 0x0 "RASDP_UNCORR_COUNT_REPORT_OFF,Uncorrected error (2-bit ECC and parity) counter data. This viewport register returns the counter data selected by the UNCORR_COUNTER_SELECTION_REGION and UNCORR_COUNTER_SELECTION fields in the RASDP_UNCORR_COUNTER_CTRL_OFF.." hexmask.long.byte 0x0 24.--31. 1. "UNCORR_COUNTER_SELECTED,Counter selection. Returns the value set in the UNCORR_COUNTER_SELECTION field of the RASDP_UNCORR_COUNTER_CTRL_OFF register." newline hexmask.long.byte 0x0 20.--23. 1. "UNCORR_COUNTER_SELECTED_REGION,Selected uncorrectable counter region: - 0x0: Region select for Adm Rx path - 0x1: Region select for layer 3 Rx path - 0x2: Region select for layer 2 Rx path - 0x3: Region select for DMA inbound path - 0x4: Region select.." newline hexmask.long.word 0x0 8.--19. 1. "RSVDP_8,Reserved for future use." newline hexmask.long.byte 0x0 0.--7. 1. "UNCORR_COUNTER,Current uncorrected error count for the selected counter" group.long (0x1C+0x480)++0x3 line.long 0x0 "RASDP_ERROR_INJ_CTRL_OFF,Error injection control for the following features: - 1-bit or 2-bit injection - Continuous or fixed-number (n) injection modes - Global enable/disable - Selectable location where injection occurs" hexmask.long.byte 0x0 24.--31. 1. "RSVDP_24,Reserved for future use." newline hexmask.long.byte 0x0 16.--23. 1. "ERROR_INJ_LOC,Error injection location. Selects where error injection takes place. You can cycle this field value from 0 to 255 to access all locations according to the detailed report of check points at.." newline hexmask.long.byte 0x0 8.--15. 1. "ERROR_INJ_COUNT,Error injection count. - 0: errors are inserted in every TLP until you clear ERROR_INJ_EN. - 1: one errors injected - 2: two errors injected - n: amount of errors injected" newline rbitfld.long 0x0 6.--7. "RSVDP_6,Reserved for future use." "0,1,2,3" newline bitfld.long 0x0 4.--5. "ERROR_INJ_TYPE,Error injection type: - 0: none - 1: 1-bit - 2: 2-bit" "none,bit,bit,?" newline rbitfld.long 0x0 1.--3. "RSVDP_1,Reserved for future use." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 0. "ERROR_INJ_EN,Error injection global enable. When set enables the error insertion logic." "0,1" rgroup.long (0x20+0x480)++0x7 line.long 0x0 "RASDP_CORR_ERROR_LOCATION_OFF,Corrected errors locations. For more details. see the RAS Data Protection (DP) section in the Core Operations chapter of the Databook." hexmask.long.byte 0x0 24.--31. 1. "LOC_LAST_CORR_ERROR,Location/ID of the last corrected error within the region defined by REG_LAST_CORR_ERROR. You can cycle this field value from 0 to 255 to access all counters according to the detailed report of check points at.." newline hexmask.long.byte 0x0 20.--23. 1. "REG_LAST_CORR_ERROR,Region of the last corrected error: - 0x0: Region select for Adm Rx path - 0x1: Region select for layer 3 Rx path - 0x2: Region select for layer 2 Rx path - 0x3: Region select for DMA inbound path - 0x4: Region select for AXI bridge.." newline hexmask.long.byte 0x0 16.--19. 1. "RSVDP_16,Reserved for future use." newline hexmask.long.byte 0x0 8.--15. 1. "LOC_FIRST_CORR_ERROR,Location/ID of the first corrected error within the region defined by REG_FIRST_CORR_ERROR. You can cycle this field value from 0 to 255 to access all counters according to the detailed report of check points at.." newline hexmask.long.byte 0x0 4.--7. 1. "REG_FIRST_CORR_ERROR,Region of the first corrected error: - 0x0: Region select for Adm Rx path - 0x1: Region select for layer 3 Rx path - 0x2: Region select for layer 2 Rx path - 0x3: Region select for DMA inbound path - 0x4: Region select for AXI bridge.." newline hexmask.long.byte 0x0 0.--3. 1. "RSVDP_0,Reserved for future use." line.long 0x4 "RASDP_UNCORR_ERROR_LOCATION_OFF,Uncorrected errors locations. For more details. see the RAS Data Protection (DP) section in the Core Operations chapter of the Databook." hexmask.long.byte 0x4 24.--31. 1. "LOC_LAST_UNCORR_ERROR,Location/ID of the last uncorrected error within the region defined by REG_LAST_UNCORR_ERROR. You can cycle this field value from 0 to 255 to access all counters according to the detailed report of check points at.." newline hexmask.long.byte 0x4 20.--23. 1. "REG_LAST_UNCORR_ERROR,Region of the last uncorrected error: - 0x0: Region select for Adm Rx path - 0x1: Region select for layer 3 Rx path - 0x2: Region select for layer 2 Rx path - 0x3: Region select for DMA inbound path - 0x4: Region select for AXI.." newline hexmask.long.byte 0x4 16.--19. 1. "RSVDP_16,Reserved for future use." newline hexmask.long.byte 0x4 8.--15. 1. "LOC_FIRST_UNCORR_ERROR,Location/ID of the first uncorrected error within the region defined by REG_FIRST_UNCORR_ERROR. You can cycle this field value from 0 to 255 to access all counters according to the detailed report of check points at.." newline hexmask.long.byte 0x4 4.--7. 1. "REG_FIRST_UNCORR_ERROR,Region of the first uncorrected error: - 0x0: Region select for Adm Rx path - 0x1: Region select for layer 3 Rx path - 0x2: Region select for layer 2 Rx path - 0x3: Region select for DMA inbound path - 0x4: Region select for AXI.." newline hexmask.long.byte 0x4 0.--3. 1. "RSVDP_0,Reserved for future use." group.long (0x28+0x480)++0x7 line.long 0x0 "RASDP_ERROR_MODE_EN_OFF,RASDP error mode enable. The controller enters RASDP error mode (if ERROR_MODE_EN =1) upon detection of the first uncorrectable error. During this mode: - Rx TLPs that are forwarded to your application are not guaranteed to be.." hexmask.long 0x0 2.--31. 1. "RSVDP_2,Reserved for future use." newline bitfld.long 0x0 1. "AUTO_LINK_DOWN_EN,Write '1' to enable the controller to bring the link down when the controller enters RASDP error mode. Note: This register field is sticky." "0,1" newline bitfld.long 0x0 0. "ERROR_MODE_EN,Write '1' to enable the controller enter RASDP error mode when it detects an uncorrectable error. Note: This register field is sticky." "0,1" line.long 0x4 "RASDP_ERROR_MODE_CLEAR_OFF,Exit RASDP error mode. For more details. see the RAS Data Protection (DP) section in the Core Operations chapter of the Databook." hexmask.long 0x4 1.--31. 1. "RSVDP_1,Reserved for future use." newline bitfld.long 0x4 0. "ERROR_MODE_CLEAR,Write '1' to take the controller out of RASDP error mode. The controller will then report uncorrectable errors (through AER internal error reporting) and also stop nullifying/discarding TLPs." "0,1" rgroup.long (0x30+0x480)++0x7 line.long 0x0 "RASDP_RAM_ADDR_CORR_ERROR_OFF,RAM Address where a corrected error (1-bit ECC) has been detected. For more details. see the RAS Data Protection (DP) section in the Core Operations chapter of the Databook." hexmask.long.byte 0x0 28.--31. 1. "RAM_INDEX_CORR_ERROR,RAM index where a corrected error (1-bit ECC) has been detected." newline bitfld.long 0x0 27. "RSVDP_27,Reserved for future use." "0,1" newline hexmask.long 0x0 0.--26. 1. "RAM_ADDR_CORR_ERROR,RAM Address where a corrected error (1-bit ECC) has been detected." line.long 0x4 "RASDP_RAM_ADDR_UNCORR_ERROR_OFF,RAM Address where an uncorrected error (2-bit ECC) has been detected. For more details. see the RAS Data Protection (DP) section in the Core Operations chapter of the Databook." hexmask.long.byte 0x4 28.--31. 1. "RAM_INDEX_UNCORR_ERROR,RAM index where an uncorrected error (2-bit ECC) has been detected." newline bitfld.long 0x4 27. "RSVDP_27,Reserved for future use." "0,1" newline hexmask.long 0x4 0.--26. 1. "RAM_ADDR_UNCORR_ERROR,RAM Address where an uncorrected error (2-bit ECC) has been detected." tree.end tree "PF0_RTR_CAP (PF RTR Capability Structure)" group.long (0x0+0x2F8)++0xB line.long 0x0 "RTR_EXT_CAP_HDR_OFF,Readiness Time Reporting PCI Express Extended Capability Header. For a description of this standard PCIe register. see the PCI Express Specification." hexmask.long.word 0x0 20.--31. 1. "RTR_NEXT_OFFSET,Next Capability Offset. For a description of this standard PCIe register field see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky).." hexmask.long.byte 0x0 16.--19. 1. "RTR_CAP_VERSION,Capability Version. For a description of this standard PCIe register field see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky).." hexmask.long.word 0x0 0.--15. 1. "RTR_EXT_CAP_ID,PCI Express Extended Capability ID. For a description of this standard PCIe register field see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then.." line.long 0x4 "READI_TIME_REPORTING1_OFF,Readiness Time Reporting 1. For a description of this standard PCIe register. see the PCI Express Specification." bitfld.long 0x4 31. "RTR_TIME_VALID,Valid. For a description of this standard PCIe register field see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky)" "0,1" hexmask.long.byte 0x4 24.--30. 1. "RSVDP_24,Reserved for future use." hexmask.long.word 0x4 12.--23. 1. "DL_UP_TIME,DL_UP Time. For a description of this standard PCIe register field see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky)" hexmask.long.word 0x4 0.--11. 1. "RESET_TIME,Reset Time. For a description of this standard PCIe register field see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky)" line.long 0x8 "READI_TIME_REPORTING2_OFF,Readiness Time Reporting 2. For a description of this standard PCIe register. see the PCI Express Specification." hexmask.long.byte 0x8 24.--31. 1. "RSVDP_24,Reserved for future use." hexmask.long.word 0x8 12.--23. 1. "D3HOT_D0_TIME,D3hot to D0 Time. For a description of this standard PCIe register field see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else.." hexmask.long.word 0x8 0.--11. 1. "FLR_TIME,FLR Time. For a description of this standard PCIe register field see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky)" tree.end tree "PF0_RTR_CAP_DBI2 (DBI2 Shadow Block: PF RTR Capability Structure)" rgroup.long (0x4+0x12F8)++0x7 line.long 0x0 "SHADOW_READI_TIME_REPORTING1_OFF,Shadow Register Readiness Time Reporting 1. For a description of this standard PCIe register. see the PCI Express Specification." bitfld.long 0x0 31. "RTR_TIME_VALID,Shadow Valid in the shadow register. For a description of this standard PCIe register field see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access - Dbi: No access - Dbi2: if.." "0,1" hexmask.long.tbyte 0x0 12.--30. 1. "RSVDP_12,Reserved for future use." hexmask.long.word 0x0 0.--11. 1. "RESET_TIME,Shadow Reset Time in the shadow register. For a description of this standard PCIe register field see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access - Dbi: No access - Dbi2: if.." line.long 0x4 "SHADOW_READI_TIME_REPORTING2_OFF,Shadow Register Readiness Time Reporting 2. For a description of this standard PCIe register. see the PCI Express Specification." hexmask.long.byte 0x4 24.--31. 1. "RSVDP_24,Reserved for future use." hexmask.long.word 0x4 12.--23. 1. "D3HOT_D0_TIME,Shadow D3hot to D0 Time in the shadow register. For a description of this standard PCIe register field see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access - Dbi: No access - Dbi2:.." hexmask.long.word 0x4 0.--11. 1. "FLR_TIME,Shadow FLR Time in the shadow register. For a description of this standard PCIe register field see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access - Dbi: No access - Dbi2: if.." tree.end tree "PF0_FRSQ_CAP (PF FRSQ Capability Structure)" group.long (0x0+0x2E8)++0xB line.long 0x0 "FRSQ_EXT_CAP_HDR_OFF,FRS Queuing Extended Capability Header. For a description of this standard PCIe register. see the PCI Express Specification." hexmask.long.word 0x0 20.--31. 1. "FRSQ_NEXT_OFFSET,Next Capability Offset. For a description of this standard PCIe register field see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then.." hexmask.long.byte 0x0 16.--19. 1. "FRSQ_CAP_VERSION,Capability Version. For a description of this standard PCIe register field see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky).." hexmask.long.word 0x0 0.--15. 1. "FRSQ_EXT_CAP_ID,PCI Express Extended Capability ID. For a description of this standard PCIe register field see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then.." line.long 0x4 "FRSQ_CAP_OFF,FRS Queuing Capability Register. For a description of this standard PCIe register. see the PCI Express Specification." hexmask.long.word 0x4 21.--31. 1. "RSVDP_21,Reserved for future use." hexmask.long.byte 0x4 16.--20. 1. "FRS_INT_MESSAGE_NUMBER,FRS Interrupt Message Number. For a description of this standard PCIe register field see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1).." hexmask.long.byte 0x4 12.--15. 1. "RSVDP_12,Reserved for future use." hexmask.long.word 0x4 0.--11. 1. "FRSQ_MAX_DEPTH,FRS Queue Max Depth. For a description of this standard PCIe register field see the PCI Express Specification." line.long 0x8 "FRSQ_CONTROL_FRSQ_STATUS_OFF,FRS Queuing Status and Control Register. For a description of this standard PCIe register. see the PCI Express Specification." hexmask.long.word 0x8 17.--31. 1. "RSVDP_17,Reserved for future use." bitfld.long 0x8 16. "FRS_INTERRUPT_ENABLE,FRS Interrupt Enable. For a description of this standard PCIe register field see the PCI Express Specification." "0,1" hexmask.long.word 0x8 2.--15. 1. "RSVDP_2,Reserved for future use." bitfld.long 0x8 1. "FRS_MESSAGE_OVERFLOW,FRS Message Overflow. For a description of this standard PCIe register field see the PCI Express Specification." "0,1" newline bitfld.long 0x8 0. "FRS_MESSAGE_RECEIVED,FRS Message Received. For a description of this standard PCIe register field see the PCI Express Specification." "0,1" rgroup.long (0xC+0x2E8)++0x3 line.long 0x0 "FRS_MESSAGE_QUEUE_OFF,FRS Message Queue Register. For a description of this standard PCIe register. see the PCI Express Specification." hexmask.long.word 0x0 20.--31. 1. "FRS_MESSAGE_QUE_DEPTH,FRS Message Queue Depth. For a description of this standard PCIe register field see the PCI Express Specification." hexmask.long.byte 0x0 16.--19. 1. "FRS_MESSAGE_QUE_REASON,FRS Message Queue Reason. For a description of this standard PCIe register field see the PCI Express Specification." hexmask.long.word 0x0 0.--15. 1. "FRS_MESSAGE_QUE_FUNC_ID,FRS Message Queue Function ID. For a description of this standard PCIe register field see the PCI Express Specification." tree.end tree "PF0_PTM_CAP (PF PTM Capability Structure)" group.long (0x0+0x40C)++0xB line.long 0x0 "PTM_EXT_CAP_HDR_OFF,Precision Time Measurement Capability Header. For a description of this standard PCIe register. see the PCI Express Specification." hexmask.long.word 0x0 20.--31. 1. "PTM_NEXT_OFFSET,Precision Time Measurement PCI Express Extended Capability Next Offset. For a description of this standard PCIe register see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access. -.." hexmask.long.byte 0x0 16.--19. 1. "PTM_CAP_VERSION,Precision Time Measurement PCI Express Extended Capability Version. For a description of this standard PCIe register see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi:.." hexmask.long.word 0x0 0.--15. 1. "PTM_CAP_ID,Precision Time Measurement PCI Express Extended Capability ID. For a description of this standard PCIe register see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if.." line.long 0x4 "PTM_CAP_OFF,PTM Capability Register. For a description of this standard PCIe register. see the PCI Express Specification." hexmask.long.word 0x4 16.--31. 1. "RSVDP_16,Reserved for future use." hexmask.long.byte 0x4 8.--15. 1. "PTM_CLK_GRAN,PTM Local Clock Granularity. For a description of this standard PCIe register see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky).." hexmask.long.byte 0x4 3.--7. 1. "RSVDP_3,Reserved for future use." bitfld.long 0x4 2. "PTM_ROOT_CAPABLE,PTM Root Capable. For a description of this standard PCIe register see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else.." "0,1" bitfld.long 0x4 1. "PTM_RES_CAPABLE,PTM Responder Capable. For a description of this standard PCIe register see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else.." "0,1" newline bitfld.long 0x4 0. "PTM_REQ_CAPABLE,PTM Requester Capable. For a description of this standard PCIe register see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else.." "0,1" line.long 0x8 "PTM_CONTROL_OFF,PTM Control Register. For a description of this standard PCIe register. see the PCI Express Specification." hexmask.long.word 0x8 16.--31. 1. "RSVDP_16,Reserved for future use." hexmask.long.byte 0x8 8.--15. 1. "EFF_GRAN,PTM Effective Granularity. For a description of this standard PCIe register see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: HWINIT" hexmask.long.byte 0x8 2.--7. 1. "RSVDP_2,Reserved for future use." rbitfld.long 0x8 1. "ROOT_SELECT,PTM Root Select. When set this Time Source is the PTM Root. For a description of this standard PCIe register see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: HWINIT" "0,1" bitfld.long 0x8 0. "PTM_ENABLE,PTM Enable. When set this function is permitted to participate in the PTM mechanism. For a description of this standard PCIe register see the PCI Express Specification." "0,1" tree.end tree "PF0_PTM_RES_CAP (PF PTM Responder Capability Structure (VSEC))" group.long (0x0+0x418)++0xB line.long 0x0 "PTM_RES_CAP_HDR_OFF,Precision Time Measurement Responder Capability Header (VSEC). For more details. see the PTM section in the Databook." hexmask.long.word 0x0 20.--31. 1. "PTM_RES_EXT_CAP_NEXT_OFFS,Precision Time Measurement Responder VSEC Next Pointer. For more details see the PTM section in the Databook. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then.." hexmask.long.byte 0x0 16.--19. 1. "PTM_RES_EXT_CAP_VER,Precision Time Measurement Responder VSEC Version. For more details see the PTM section in the Databook. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else.." hexmask.long.word 0x0 0.--15. 1. "PTM_RES_EXT_CAP_ID,Precision Time Measurement Responder VSEC ID. For more details see the PTM section in the Databook. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else.." line.long 0x4 "PTM_RES_HDR_OFF,Precision Time Measurement Responder Vendor Specific Header. For more details. see the PTM section in the Databook." hexmask.long.word 0x4 20.--31. 1. "PTM_RES_VSEC_LENGTH,PTM Responder VSEC Length. For more details see the PTM section in the Databook. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This.." hexmask.long.byte 0x4 16.--19. 1. "PTM_RES_VSEC_REV,PTM Responder VSEC Revision. For more details see the PTM section in the Databook. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This.." hexmask.long.word 0x4 0.--15. 1. "PTM_RES_VSEC_ID,PTM Responder VSEC ID. For more details see the PTM section in the Databook. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register.." line.long 0x8 "PTM_RES_CONTROL_OFF,PTM Responder Control Register. For more details. see the PTM section in the Databook." hexmask.long 0x8 2.--31. 1. "RSVDP_2,Reserved for future use." bitfld.long 0x8 1. "PTM_RES_PDEL_BYTE_REV,PTM Requester Propagation Delay Byte Reversal - Reverse the order of bytes in the PTM Propagation Delay data word of the PTM ResponseD Message for compatibility with previous revisions. For more details see the PTM section in the.." "0,1" bitfld.long 0x8 0. "PTM_RES_CCONTEXT_VALID,PTM Responder Control Context Valid - PTM Local Timing is valid. This bit is set over the DBI. A speed change or aux_clk_active will set this bit low. For more details see the PTM section in the Databook. Note: The access.." "0,1" rgroup.long (0xC+0x418)++0x3 line.long 0x0 "PTM_RES_STATUS_OFF,PTM Responder Status Register. For more details. see the PTM section in the Databook." hexmask.long 0x0 2.--31. 1. "RSVDP_2,Reserved for future use." bitfld.long 0x0 1. "PTM_RES_REQUEST_RECEIVED,PTM 1st Request Received - PTM Responder has received the first PTM Request Message. Upon receipt of a second PTM Request Message a ResponseD message with timing information will be sent from the Responder if the context is.." "0,1" bitfld.long 0x0 0. "PTM_RES_CONTEXT_VALID,PTM Responder Status Context Valid - PTM Local Timing Context is Valid. Value set from upstream port Requester in a Switch. Shadows the same in the control register in all other products. For more details see the PTM section in the.." "0,1" group.long (0x10+0x418)++0x7 line.long 0x0 "PTM_RES_LOCAL_LSB_OFF,PTM Responder Local Clock LSB. For more details. see the PTM section in the Databook." hexmask.long 0x0 0.--31. 1. "PTM_RES_LOCAL_LSB,PTM Responder Local Clock LSB - Lower 32 bits of local timer value. For more details see the PTM section in the Databook. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then.." line.long 0x4 "PTM_RES_LOCAL_MSB_OFF,PTM Responder Local Clock MSB. For more details. see the PTM section in the Databook." hexmask.long 0x4 0.--31. 1. "PTM_RES_LOCAL_MSB,PTM Responder Local Clock MSB - Upper 32 bits of local timer value. For more details see the PTM section in the Databook. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then.." rgroup.long (0x18+0x418)++0x1F line.long 0x0 "PTM_RES_T2_LSB_OFF,PTM Responder T2 Timestamp LSB. For more details. see the PTM section in the Databook." hexmask.long 0x0 0.--31. 1. "PTM_RES_T2_LSB,PTM Responder T2 Timestamp LSB - Lower 32 bits of the T2 Timestamp value. For more details see the PTM section in the Databook. Note: This register field is sticky." line.long 0x4 "PTM_RES_T2_MSB_OFF,PTM Responder T2 Timestamp MSB. For more details. see the PTM section in the Databook." hexmask.long 0x4 0.--31. 1. "PTM_RES_T2_MSB,PTM Responder T2 Timestamp MSB - Upper 32 bits of the T2 Timestamp value. For more details see the PTM section in the Databook. Note: This register field is sticky." line.long 0x8 "PTM_RES_T2P_LSB_OFF,PTM Responder T2 Previous Timestamp LSB. For more details. see the PTM section in the Databook." hexmask.long 0x8 0.--31. 1. "PTM_RES_T2P_LSB,PTM Responder T2 Previous Timestamp LSB - Lower 32 bits of the previously stored T2 Timestamp value. For more details see the PTM section in the Databook. Note: This register field is sticky." line.long 0xC "PTM_RES_T2P_MSB_OFF,PTM Responder T2 Previous Timestamp MSB. For more details. see the PTM section in the Databook." hexmask.long 0xC 0.--31. 1. "PTM_RES_T2P_MSB,PTM Responder T2 Previous Timestamp MSB - Upper 32 bits of the previously stored T2 Timestamp value. For more details see the PTM section in the Databook. Note: This register field is sticky." line.long 0x10 "PTM_RES_T3_LSB_OFF,PTM Responder T3 Timestamp LSB. For more details. see the PTM section in the Databook." hexmask.long 0x10 0.--31. 1. "PTM_RES_T3_LSB,PTM Responder T3 Timestamp LSB - Lower 32 bits of the T3 Timestamp value. For more details see the PTM section in the Databook. Note: This register field is sticky." line.long 0x14 "PTM_RES_T3_MSB_OFF,PTM Responder T3 Timestamp MSB. For more details. see the PTM section in the Databook." hexmask.long 0x14 0.--31. 1. "PTM_RES_T3_MSB,PTM Responder T3 Timestamp MSB - Upper 32 bits of the T2 Timestamp value. For more details see the PTM section in the Databook. Note: This register field is sticky." line.long 0x18 "PTM_RES_T3P_LSB_OFF,PTM Responder T3 Previous Timestamp LSB. For more details. see the PTM section in the Databook." hexmask.long 0x18 0.--31. 1. "PTM_RES_T3P_LSB,PTM Responder T3 Previous Timestamp LSB - Lower 32 bits of the previously stored T3 Timestamp value. For more details see the PTM section in the Databook. Note: This register field is sticky." line.long 0x1C "PTM_RES_T3P_MSB_OFF,PTM Responder T3 Previous Timestamp MSB. For more details. see the PTM section in the Databook." hexmask.long 0x1C 0.--31. 1. "PTM_RES_T3P_MSB,PTM Responder T3 Previous Timestamp MSB - Upper 32 bits of the previously stored T3 Timestamp value. For more details see the PTM section in the Databook. Note: This register field is sticky." group.long (0x38+0x418)++0x7 line.long 0x0 "PTM_RES_TX_LATENCY_OFF,PTM Responder TX Latency. For more details. see the PTM section in the Databook." hexmask.long.tbyte 0x0 12.--31. 1. "RSVDP_12,Reserved for future use." hexmask.long.word 0x0 0.--11. 1. "PTM_RES_TX_LATENCY,PTM Responder TX Latency - Responder Transmit path latency (12 bit wide). For more details see the PTM section in the Databook. Note: This register field is sticky." line.long 0x4 "PTM_RES_RX_LATENCY_OFF,PTM Responder RX Latency. For more details. see the PTM section in the Databook." hexmask.long.tbyte 0x4 12.--31. 1. "RSVDP_12,Reserved for future use." hexmask.long.word 0x4 0.--11. 1. "PTM_RES_RX_LATENCY,PTM Responder RX Latency - Responder Receive path latency (12 bit wide). For more details see the PTM section in the Databook. Note: This register field is sticky." rgroup.long (0x40+0x418)++0x3 line.long 0x0 "PTM_RES_NOM_CLOCK_T_OFF,PTM Responder Nominal Clock Period. For more details. see the PTM section in the Databook." hexmask.long.byte 0x0 24.--31. 1. "RSVDP_24,Reserved for future use." hexmask.long.byte 0x0 16.--23. 1. "PTM_RES_NOM_CLOCK_T_INT,PTM Responder Nominal Clock Period Integral - Integral part of the nominal PTM local clock period in nanoseconds. For more details see the PTM section in the Databook. Note: This register field is sticky." hexmask.long.word 0x0 0.--15. 1. "PTM_RES_NOM_CLOCK_T_FRAC,PTM Responder Nominal Clock Period Fractional - Fractional part of the nominal PTM local clock period. LSB is 1/(2^16) nanoseconds. For more details see the PTM section in the Databook. Note: This register field is sticky." group.long (0x44+0x418)++0x3 line.long 0x0 "PTM_RES_SCALED_CLOCK_T_OFF,PTM Responder Scaled Clock Period. For more details. see the PTM section in the Databook." bitfld.long 0x0 31. "PTM_RES_SCALED_CLOCK_T_EN,PTM Responder Scaled Clock Period Enable - Use the programmed scaled PTM clock period rather than the nominal values. This bit is cleared when the core_clk rate starts to change and can only be set when the clock period change.." "0,1" hexmask.long.byte 0x0 24.--30. 1. "RSVDP_24,Reserved for future use." hexmask.long.byte 0x0 16.--23. 1. "PTM_RES_SCALED_CLOCK_T_INT,PTM Responder Scaled Clock Period Integral - Integral part of the nominal PTM local clock period in nanoseconds. For more details see the PTM section in the Databook. Note: This register field is sticky." newline hexmask.long.word 0x0 0.--15. 1. "PTM_RES_SCALED_CLOCK_T_FRAC,PTM Responder Scaled Clock Period Fractional - Fractional part of the nominal PTM local clock period. LSB is 1/(2^16) nanoseconds. For more details see the PTM section in the Databook. Note: This register field is sticky." tree.end tree "PF0_PM_CAP (PF PCI Power Management Capability Structure)" group.long (0x0+0x40)++0x7 line.long 0x0 "CAP_ID_NXT_PTR_REG,Power Management Capabilities Register." hexmask.long.byte 0x0 27.--31. 1. "PME_SUPPORT,PME_Support. This 5-bit field indicates the power states in which the function may generate a PME and/or forward PME messages. A value of 0b for any bit indicates that the function is not capable of asserting PME while in that power state. -.." bitfld.long 0x0 26. "D2_SUPPORT,D2_Support. If this bit is set this function supports the D2 Power Management state. Functions that do not support D2 must always return a value of 0b for this bit. Note: The access attributes of this field are as follows: - Wire: No access." "0,1" bitfld.long 0x0 25. "D1_SUPPORT,D1_Support. If this bit is set this function supports the D1 Power Management state. Functions that do not support D1 must always return a value of 0b for this bit. Note: The access attributes of this field are as follows: - Wire: No access." "0,1" bitfld.long 0x0 22.--24. "AUX_CURR,Aux_Current. This 3 bit field reports the Vaux auxiliary current requirements for the function. If this function implements the Data Register the controller hardwires this field to 000b. If PME_Support is 0 xxxxb (PME assertion from D3cold is.." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 21. "DSI,Device Specific Initialization. The DSI bit indicates whether special initialization of this function is required. When set indicates that the function requires a device specific initialization sequence following a transition to the D0uninitialized.." "0,1" bitfld.long 0x0 20. "PME_IMM_READI_RETURN_DO,Immediate_Readiness_on_Return_to_D0. - If this bit is a '1' this function is guaranteed to be ready to successfully complete valid accesses immediately after being set to D0. These accesses include configuration cycles and if.." "0,1" rbitfld.long 0x0 19. "PME_CLK,PME Clock. Does not apply to PCI Express the controller hardwires it to 0b. Note: This register field is sticky." "0,1" bitfld.long 0x0 16.--18. "PM_SPEC_VER,Version. This field provides the Power Management specification version. The controller hardwires this field to 011b for functions compliant to PCI Express Base Specification Revision 4.0 Version 1.0>. Note: The access attributes of this.." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x0 8.--15. 1. "PM_NEXT_POINTER,Next Capability Pointer. This field provides an offset into the function's configuration space pointing to the location of next item in the capabilities list. If there are no additional items in the capabilities list this field is set to.." hexmask.long.byte 0x0 0.--7. 1. "PM_CAP_ID,Capability ID. This field returns 01h to indicate that this is the PCI Power Management Capability. Each function may have only one item in its capability list with Capability ID set to 01h." line.long 0x4 "CON_STATUS_REG,Power Management Control and Status Register. This register is used to manage the PCI function's power management state as well as to enable/monitor PMEs." hexmask.long.byte 0x4 24.--31. 1. "DATA_REG_ADD_INFO,Data. This field is used to report the state dependent data requested by the Data_Select field. The value of this field is scaled by the value reported by the Data_Scale field." rbitfld.long 0x4 23. "BUS_PWR_CLK_CON_EN,Bus Power/Clock Control Enable. For a description of this standard PCIe register field see the PCI Express Base Specification." "0,1" rbitfld.long 0x4 22. "B2_B3_SUPPORT,B2B3 Support for D3hot. For a description of this standard PCIe register field see the PCI Express Base Specification." "0,1" hexmask.long.byte 0x4 16.--21. 1. "RSVDP_16,Reserved for future use." newline bitfld.long 0x4 15. "PME_STATUS,PME_Status. This bit is set when the function normally generates a PME signal. The value of this bit is not affected by the value of the PME_En bit. If PME_Support bit 31 of the Power Management Capabilities register is clear this bit is.." "0,1" rbitfld.long 0x4 13.--14. "DATA_SCALE,Data_Scale. This field indicates the scaling factor to be used when interpreting the value of the Data field. The value and meaning of this field varies depending on which data value has been selected by the Data_Select field. For more details.." "0,1,2,3" hexmask.long.byte 0x4 9.--12. 1. "DATA_SELECT,Data_Select. This 4-bit field is used to select which data is to be reported through the Data and Data_Scale field. If the Data field is not implemented this field must be hardwired to 0000b." bitfld.long 0x4 8. "PME_ENABLE,PME_En. - When set the function is permitted to generate a PME. - When clear the function is not permitted to generate a PME. If PME_Support is 1 xxxxb (PME generation from D3cold) or the function consumes Aux power and Aux power is.." "0,1" newline hexmask.long.byte 0x4 4.--7. 1. "RSVDP_4,Reserved for future use." bitfld.long 0x4 3. "NO_SOFT_RST,No_Soft_Reset. This bit indicates the state of the function after writing the PowerState field to transition the function from D3hot to D0. - When set this transition preserves internal function state. The function is in D0Active and no.." "0,1" rbitfld.long 0x4 2. "RSVDP_2,Reserved for future use." "0,1" bitfld.long 0x4 0.--1. "POWER_STATE,PowerState. This 2-bit field is used both to determine the current power state of a function and to set the function into a new power state. The definition of the field values is given below. You can write to this register; however the.." "D0,D1,D2,D3hot" tree.end tree "PF0_PCIE_CAP (PF PCI Express Capability Structure)" group.long (0x0+0x70)++0x33 line.long 0x0 "PCIE_CAP_ID_PCIE_NEXT_CAP_PTR_PCIE_CAP_REG,PCI Express Capabilities. ID. Next Pointer Register." rbitfld.long 0x0 31. "RSVDP_31,Reserved for future use." "0,1" rbitfld.long 0x0 30. "RSVD,Reserved." "0,1" newline hexmask.long.byte 0x0 25.--29. 1. "PCIE_INT_MSG_NUM,PCIE Interrupt Message Number. For a description of this standard PCIe register field see the PCI Express Base Specification. Interrupt Message Number. This field indicates which MSI/MSI-X vector is used for the interrupt message.." bitfld.long 0x0 24. "PCIE_SLOT_IMP,Slot Implemented. When set this bit indicates that the Link associated with this Port is connected to a slot (as compared to being connected to a system-integrated device or being disabled). This bit is valid for Downstream Ports. This bit.." "0,1" newline hexmask.long.byte 0x0 20.--23. 1. "PCIE_DEV_PORT_TYPE,Device/Port Type. Indicates the specific type of this PCI Express function. Note: Different functions in a Multi-Function Device can generally be of different types. Defined encodings for functions that implement a Type 00h PCI.." hexmask.long.byte 0x0 16.--19. 1. "PCIE_CAP_REG,Capability Version. Indicates PCI-SIG defined PCI Express Capability structure version number. A version of the specification that changes the PCI Express Capability structure in a way that is not otherwise identifiable (for example through.." newline hexmask.long.byte 0x0 8.--15. 1. "PCIE_CAP_NEXT_PTR,Next Capability Pointer. This field contains the offset to the next PCI Capability structure or 00h if no other items exist in the linked list of Capabilities. Note: The access attributes of this field are as follows: - Wire: No access." hexmask.long.byte 0x0 0.--7. 1. "PCIE_CAP_ID,Capability ID. Indicates the PCI Express Capability structure. This field must return a Capability ID of 10h indicating that this is a PCI Express Capability structure." line.long 0x4 "DEVICE_CAPABILITIES_REG,Device Capabilities Register. The Device Capabilities register identifies PCI Express device function specific capabilities." hexmask.long.word 0x4 16.--31. 1. "RSVDP_16,Reserved for future use." bitfld.long 0x4 15. "PCIE_CAP_ROLE_BASED_ERR_REPORT,Role-Based Error Reporting. When set this bit indicates that the function implements the functionality originally defined in the Error Reporting ECN for PCI Express Base Specification Revision 1.0a and later incorporated.." "0,1" newline hexmask.long.word 0x4 6.--14. 1. "RSVDP_6,Reserved for future use." bitfld.long 0x4 5. "PCIE_CAP_EXT_TAG_SUPP,Extended Tag Field Supported. This bit in combination with the 10-Bit Tag Requester Supported bit in the Device Capabilities 2 register indicates the maximum supported size of the Tag field as a Requester. This bit must be set if.." "0,1" newline bitfld.long 0x4 3.--4. "PCIE_CAP_PHANTOM_FUNC_SUPPORT,Phantom Functions Supported. This field indicates the support for use of unclaimed function numbers to extend the number of outstanding transactions allowed by logically combining unclaimed function numbers (called Phantom.." "0,1,2,3" bitfld.long 0x4 0.--2. "PCIE_CAP_MAX_PAYLOAD_SIZE,Max_Payload_Size Supported. This field indicates the maximum payload size that the function can support for TLPs. Defined encodings are: - 000b: 128 bytes max payload size - 001b: 256 bytes max payload size - 010b: 512 bytes max.." "0,1,2,3,4,5,6,7" line.long 0x8 "DEVICE_CONTROL_DEVICE_STATUS,Device Control and Device Status Register. This register controls PCI Express device specific parameters and provides information about PCI Express device (function) specific parameters." hexmask.long.word 0x8 22.--31. 1. "RSVDP_22,Reserved for future use." rbitfld.long 0x8 21. "PCIE_CAP_TRANS_PENDING,Transactions Pending. Endpoints: When set this bit indicates that the function has issued Non-Posted Requests that have not been completed. A Function reports this bit cleared only when all outstanding Non-Posted Requests have.." "0,1" newline rbitfld.long 0x8 20. "PCIE_CAP_AUX_POWER_DETECTED,AUX Power Detected. Functions that require Aux power report this bit as set if Aux power is detected by the function. This bit is derived by sampling the sys_aux_pwr_det input." "0,1" bitfld.long 0x8 19. "PCIE_CAP_UNSUPPORTED_REQ_DETECTED,Unsupported Request Detected. This bit indicates that the function received an Unsupported Request. Errors are logged in this register regardless of whether error reporting is enabled or not in the Device Control.." "0,1" newline bitfld.long 0x8 18. "PCIE_CAP_FATAL_ERR_DETECTED,Fatal Error Detected. This bit indicates status of Fatal errors detected. Errors are logged in this register regardless of whether error reporting is enabled or not in the Device Control register. For a Multi-Function device.." "0,1" bitfld.long 0x8 17. "PCIE_CAP_NON_FATAL_ERR_DETECTED,Non-Fatal Error Detected. This bit indicates status of Non-fatal errors detected. Errors are logged in this register regardless of whether error reporting is enabled or not in the Device Control register. For a.." "0,1" newline bitfld.long 0x8 16. "PCIE_CAP_CORR_ERR_DETECTED,Correctable Error Detected. This bit indicates status of correctable errors detected. Errors are logged in this register regardless of whether error reporting is enabled or not in the Device Control register. For a.." "0,1" bitfld.long 0x8 15. "PCIE_CAP_INITIATE_FLR,Initiate Function Level Reset (applicable to Endpoints with Function Level Reset Capability set to 1b). A write of 1b initiates Function Level Reset to the Function. The value read by software from this bit is always 0b." "0,1" newline bitfld.long 0x8 12.--14. "PCIE_CAP_MAX_READ_REQ_SIZE,Max_Read_Request_Size. This field sets the maximum Read Request size for the function as a Requester. The function must not generate Read Requests with a size exceeding the set value. Defined encodings for this field are: -.." "0,1,2,3,4,5,6,7" rbitfld.long 0x8 11. "PCIE_CAP_EN_NO_SNOOP,Enable No Snoop. If this bit is set the function is permitted to Set the No Snoop bit in the Requester Attributes of transactions it initiates that do not require hardware enforced cache coherency (see section 2.2.6.5 in PCI Express.." "0,1" newline bitfld.long 0x8 10. "PCIE_CAP_AUX_POWER_PM_EN,Aux Power PM Enable. This bit is derived by sampling the sys_aux_pwr_det input. When set this bit enables a function to draw Aux power independent of PME Aux power. Functions that require Aux power on legacy operating systems.." "0,1" rbitfld.long 0x8 9. "PCIE_CAP_PHANTOM_FUNC_EN,Phantom Functions Enable. This bit in combination with the 10-Bit Tag Requester Enable bit in the Device Control 2 register determines how many Tag field bits a Requester is permitted to use. When the 10-Bit Tag Requester.." "0,1" newline rbitfld.long 0x8 8. "PCIE_CAP_EXT_TAG_EN,Extended Tag Field Enable. This bit in combination with the 10-Bit Tag Requester Enable bit in the Device Control 2 register determines how many Tag field bits a Requester is permitted to use. When the 10-Bit Tag Requester Enable.." "0,1" bitfld.long 0x8 5.--7. "PCIE_CAP_MAX_PAYLOAD_SIZE_CS,Max_Payload_Size. This field sets maximum TLP payload size for the Function. As a Receiver the Function must handle TLPs as large as the set value. As a Transmitter the Function must not generate TLPs exceeding the set.." "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 4. "PCIE_CAP_EN_REL_ORDER,Enable Relaxed Ordering. If this bit is set the function is permitted to set the Relaxed Ordering bit in the Attributes field of transactions it initiates that do not require strong write ordering (for more details see section.." "0,1" bitfld.long 0x8 3. "PCIE_CAP_UNSUPPORT_REQ_REP_EN,Unsupported Request Reporting Enable. This bit in conjunction with other bits controls the signaling of Unsupported Request Errors by sending error Messages (for more details see section 6.2.5 and section 6.2.6 of PCI.." "0,1" newline bitfld.long 0x8 2. "PCIE_CAP_FATAL_ERR_REPORT_EN,Fatal Error Reporting Enable. This bit in conjunction with other bits controls sending ERR_FATAL Messages (for more details see section 6.2.5 and section 6.2.6 of of PCI Express Base Specification). For a Multi-Function.." "0,1" bitfld.long 0x8 1. "PCIE_CAP_NON_FATAL_ERR_REPORT_EN,Non-Fatal Error Reporting Enable. This bit in conjunction with other bits controls sending ERR_NONFATAL Messages (for more details see section 6.2.5 and Section 6.2.6 of PCI Express Base Specification). For a.." "0,1" newline bitfld.long 0x8 0. "PCIE_CAP_CORR_ERR_REPORT_EN,Correctable Error Reporting Enable. This bit in conjunction with other bits controls sending ERR_COR Messages (for more details see section 6.2.5 section 6.2.6 and section 6.2.10.2 of PCI Express Base Specification). For.." "0,1" line.long 0xC "LINK_CAPABILITIES_REG,Link Capabilities Register. The Link Capabilities register identifies PCI Express Link specific capabilities." hexmask.long.byte 0xC 24.--31. 1. "PCIE_CAP_PORT_NUM,Port Number. This field indicates the PCI Express Port number for the given PCI Express Link. Multi-Function Devices associated with an Upstream Port must report the same value in this field for all functions. Note: The access.." rbitfld.long 0xC 23. "RSVDP_23,Reserved for future use." "0,1" newline bitfld.long 0xC 22. "PCIE_CAP_ASPM_OPT_COMPLIANCE,ASPM Optionality Compliance. This bit must be set to 1b in all functions. Components implemented against certain earlier versions of this specification will have this bit set to 0b. Software is permitted to use the value of.." "0,1" bitfld.long 0xC 21. "PCIE_CAP_LINK_BW_NOT_CAP,Link Bandwidth Notification Capability. A value of 1b indicates support for the Link Bandwidth Notification status and interrupt mechanisms. This capability is required for all Root Ports and Switch Downstream Ports supporting.." "0,1" newline rbitfld.long 0xC 20. "PCIE_CAP_DLL_ACTIVE_REP_CAP,Data Link Layer Link Active Reporting Capable. For a Downstream Port the controller hardwires this bit to 1b if the component supports the optional capability of reporting the DL_Active state of the Data Link Control and.." "0,1" bitfld.long 0xC 19. "PCIE_CAP_SURPRISE_DOWN_ERR_REP_CAP,Surprise Down Error Reporting Capable. For a Downstream Port this bit must be set if the component supports the optional capability of detecting and reporting a Surprise Down error condition. For Upstream Ports and.." "0,1" newline rbitfld.long 0xC 18. "PCIE_CAP_CLOCK_POWER_MAN,Clock Power Management. For Upstream Ports a value of 1b in this bit indicates that the component tolerates the removal of any reference clock(s) via the 'clock request' (CLKREQ#) mechanism when the Link is in the L1 and L2/L3.." "0,1" bitfld.long 0xC 15.--17. "PCIE_CAP_L1_EXIT_LATENCY,L1 Exit Latency. This field indicates the L1 exit latency for the given PCI Express Link. The value reported indicates the length of time this Port requires to complete transition from ASPM L1 to L0. If ASPM L1 is not supported.." "0,1,2,3,4,5,6,7" newline bitfld.long 0xC 12.--14. "PCIE_CAP_L0S_EXIT_LATENCY,L0s Exit Latency. This field indicates the L0s exit latency for the given PCI Express Link. The value reported indicates the length of time this Port requires to complete transition from L0s to L0. If L0s is not supported the.." "0,1,2,3,4,5,6,7" bitfld.long 0xC 10.--11. "PCIE_CAP_ACTIVE_STATE_LINK_PM_SUPPORT,Active State Power Management (ASPM) Support. This field indicates the level of ASPM supported on the given PCI Express Link. For more details on ASPM support requirements see section 5.4.1 of PCI Express Base.." "0,1,2,3" newline hexmask.long.byte 0xC 4.--9. 1. "PCIE_CAP_MAX_LINK_WIDTH,Maximum Link Width. This field indicates the maximum Link width (xN - corresponding to N Lanes) implemented by the component. This value is permitted to exceed the number of Lanes routed to the slot (Downstream Port) adapter.." hexmask.long.byte 0xC 0.--3. 1. "PCIE_CAP_MAX_LINK_SPEED,Max Link Speed. This field indicates the maximum Link speed of the associated Port. The encoded value specifies a bit location in the Supported Link Speeds Vector (in the Link Capabilities 2 register) that corresponds to the.." line.long 0x10 "LINK_CONTROL_LINK_STATUS_REG,Link Control and Link Status Register. This register controls and provides information about PCI Express Link specific parameters." bitfld.long 0x10 31. "PCIE_CAP_LINK_AUTO_BW_STATUS,Link Autonomous Bandwidth Status. This bit is set by hardware to indicate that hardware has autonomously changed Link speed or width without the Port transitioning through DL_Down status for reasons other than to attempt to.." "0,1" bitfld.long 0x10 30. "PCIE_CAP_LINK_BW_MAN_STATUS,Link Bandwidth Management Status. This bit is set by hardware to indicate that either of the following has occurred without the Port transitioning through DL_Down status: - A Link retraining has completed following a write of.." "0,1" newline rbitfld.long 0x10 29. "PCIE_CAP_DLL_ACTIVE,Data Link Layer Link Active. This bit indicates the status of the Data Link Control and Management State Machine. It returns a 1b to indicate the DL_Active state 0b otherwise. This bit must be implemented if the Data Link Layer Link.." "0,1" bitfld.long 0x10 28. "PCIE_CAP_SLOT_CLK_CONFIG,Slot Clock Configuration. This bit indicates that the component uses the same physical reference clock that the platform provides on the connector. If the device uses an independent clock irrespective of the presence of a.." "0,1" newline rbitfld.long 0x10 27. "PCIE_CAP_LINK_TRAINING,Link Training. This read-only bit indicates that the Physical Layer LTSSM is in the Configuration or Recovery state or that 1b was written to the Retrain Link bit but Link training has not yet begun. Hardware clears this bit when.." "0,1" rbitfld.long 0x10 26. "RSVDP_26,Reserved for future use." "0,1" newline hexmask.long.byte 0x10 20.--25. 1. "PCIE_CAP_NEGO_LINK_WIDTH,Negotiated Link Width. This field indicates the negotiated width of the given PCI Express Link. Defined encodings are: -00 0001b: x1 -00 0010b: x2 -00 0100b: x4 -00 1000b: x8 -00 1100b: x12 -01 0000b: x16 -10 0000b: x32 All other.." hexmask.long.byte 0x10 16.--19. 1. "PCIE_CAP_LINK_SPEED,Current Link Speed. This field indicates the negotiated Link speed of the given PCI Express Link. The encoded value specifies a bit location in the Supported Link Speeds Vector (in the Link Capabilities 2 register) that corresponds to.." newline bitfld.long 0x10 14.--15. "PCIE_CAP_DRS_SIGNALING_CONTROL,DRS Signaling Control. Indicates the mechanism used to report reception of a DRS message. Must be implemented for Downstream Ports with the DRS Supported bit Set in the Link Capabilities 2 Register. Encodings are: - 00b:.." "0,1,2,3" rbitfld.long 0x10 12.--13. "RSVDP_12,Reserved for future use." "0,1,2,3" newline bitfld.long 0x10 11. "PCIE_CAP_LINK_AUTO_BW_INT_EN,Link Autonomous Bandwidth Management Interrupt Enable. When set this bit enables the generation of an interrupt to indicate that the Link Autonomous Bandwidth Status bit has been set. The write value is gated with the.." "0,1" bitfld.long 0x10 10. "PCIE_CAP_LINK_BW_MAN_INT_EN,Link Bandwidth Management Interrupt Enable. When set this bit enables the generation of an interrupt to indicate that the Link Bandwidth Management Status bit has been set. The write value is gated with the.." "0,1" newline bitfld.long 0x10 9. "PCIE_CAP_HW_AUTO_WIDTH_DISABLE,Hardware Autonomous Width Disable. When set this bit disables hardware from changing the Link width for reasons other than attempting to correct unreliable Link operation by reducing Link width. For a Multi-Function Device.." "0,1" bitfld.long 0x10 8. "PCIE_CAP_EN_CLK_POWER_MAN,Enable Clock Power Management. Applicable only for Upstream Ports and with form factors that support a 'Clock Request' (CLKREQ#) mechanism this bit operates as follows: - 0b: Clock power management is disabled and device must.." "0,1" newline bitfld.long 0x10 7. "PCIE_CAP_EXTENDED_SYNCH,Extended Synch. When set this bit forces the transmission of additional Ordered Sets when exiting the L0s state (see section 4.2.4.5 of PCI Express Base Specification) and when in the Recovery state (see section 4.2.6.4.1 of PCI.." "0,1" bitfld.long 0x10 6. "PCIE_CAP_COMMON_CLK_CONFIG,Common Clock Configuration. When set this bit indicates that this component and the component at the opposite end of this Link are operating with a distributed common reference clock. A value of 0b indicates that this.." "0,1" newline bitfld.long 0x10 5. "PCIE_CAP_RETRAIN_LINK,Retrain Link. A write of 1b to this bit initiates Link retraining by directing the Physical Layer LTSSM to the Recovery state. If the LTSSM is already in Recovery or Configuration re-entering Recovery is permitted but not required." "0,1" bitfld.long 0x10 4. "PCIE_CAP_LINK_DISABLE,Link Disable. This bit disables the Link by directing the LTSSM to the Disabled state when set; this bit is Reserved on Endpoints PCI Express to PCI/PCI-X bridges and Upstream Ports of Switches. Writes to this bit are immediately.." "0,1" newline bitfld.long 0x10 3. "PCIE_CAP_RCB,Read Completion Boundary (RCB). Root Ports: Indicates the RCB value for the Root Port. Refer to section 2.3.1.1 of PCI Express Base Specification for the definition of the parameter RCB. Defined encodings are: - 0b: 64 byte - 1b: 128 byte.." "0,1" rbitfld.long 0x10 2. "RSVDP_2,Reserved for future use." "0,1" newline bitfld.long 0x10 0.--1. "PCIE_CAP_ACTIVE_STATE_LINK_PM_CONTROL,Active State Power Management (ASPM) Control. This field controls the level of ASPM enabled on the given PCI Express Link. See section 5.4.1.3 of PCI Express Base Specification for requirements on when and how to.." "0,1,2,3" line.long 0x14 "SLOT_CAPABILITIES_REG,Slot Capabilities Register. The Slot Capabilities register identifies PCI Express slot specific capabilities." hexmask.long.word 0x14 19.--31. 1. "PCIE_CAP_PHY_SLOT_NUM,Physical Slot Number. This field indicates the physical slot number attached to this Port. This field must be hardware initialized to a value that assigns a slot number that is unique within the chassis regardless of the form.." bitfld.long 0x14 18. "PCIE_CAP_NO_CMD_CPL_SUPPORT,No Command Completed Support. When set this bit indicates that this slot does not generate software notification when an issued command is completed by the Hot-Plug Controller. This bit is only permitted to be set if the.." "0,1" newline bitfld.long 0x14 17. "PCIE_CAP_ELECTROMECH_INTERLOCK,Electromechanical Interlock Present. When set this bit indicates that an Electromechanical Interlock is implemented on the chassis for this slot. Note: The access attributes of this field are as follows: - Wire: No access." "0,1" bitfld.long 0x14 15.--16. "PCIE_CAP_SLOT_POWER_LIMIT_SCALE,Slot Power Limit Scale. Specifies the scale used for the Slot Power Limit Value (for more details see Section 6.9 of PCI Express Base Specification). Range of Values: - 00b: 1.0x - 01b: 0.1x - 10b: 0.01x - 11b: 0.001x.." "0,1,2,3" newline hexmask.long.byte 0x14 7.--14. 1. "PCIE_CAP_SLOT_POWER_LIMIT_VALUE,Slot Power Limit Value. In combination with the Slot Power Limit Scale value specifies the upper limit on power supplied by the slot (for more detais see Section 6.9 of PCI Express Base Specification) or by other means.." bitfld.long 0x14 6. "PCIE_CAP_HOT_PLUG_CAPABLE,Hot-Plug Capable. When set this bit indicates that this slot is capable of supporting hot-plug operations. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then R/W else R" "0,1" newline bitfld.long 0x14 5. "PCIE_CAP_HOT_PLUG_SURPRISE,Hot-Plug Surprise. When set this bit indicates that an adapter present in this slot might be removed from the system without any prior notification. This is a form factor specific capability. This bit is an indication to the.." "0,1" bitfld.long 0x14 4. "PCIE_CAP_POWER_INDICATOR,Power Indicator Present. When set this bit indicates that a Power Indicator is electrically controlled by the chassis for this slot. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if.." "0,1" newline bitfld.long 0x14 3. "PCIE_CAP_ATTENTION_INDICATOR,Attention Indicator Present. When set this bit indicates that an Attention Indicator is electrically controlled by the chassis. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if.." "0,1" bitfld.long 0x14 2. "PCIE_CAP_MRL_SENSOR,MRL Sensor Present. When set this bit indicates that an MRL Sensor is implemented on the chassis for this slot. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then R/W else R" "0,1" newline bitfld.long 0x14 1. "PCIE_CAP_POWER_CONTROLLER,Power Controller Present. When set this bit indicates that a software programmable Power Controller is implemented for this slot/adapter (depending on form factor). Note: The access attributes of this field are as follows: -.." "0,1" bitfld.long 0x14 0. "PCIE_CAP_ATTENTION_INDICATOR_BUTTON,Attention Button Present. When set this bit indicates that an Attention Button for this slot is electrically controlled by the chassis. Note: The access attributes of this field are as follows: - Wire: No access. -.." "0,1" line.long 0x18 "SLOT_CONTROL_SLOT_STATUS,Slot Control and Status Register. This register controls and provides information about PCI Express Slot specific parameters." hexmask.long.byte 0x18 25.--31. 1. "RSVDP_25,Reserved for future use." bitfld.long 0x18 24. "PCIE_CAP_DLL_STATE_CHANGED,Data Link Layer State Changed. This bit is set when the value reported in the Data Link Layer Link Active bit of the Link Status register is changed. In response to a Data Link Layer State Changed event software must read the.." "0,1" newline rbitfld.long 0x18 23. "PCIE_CAP_ELECTROMECH_INTERLOCK_STATUS,Electromechanical Interlock Status. If an Electromechanical Interlock is implemented this bit indicates the status of the Electromechanical Interlock. Defined encodings are: - 0b: Electromechanical Interlock.." "0,1" rbitfld.long 0x18 22. "PCIE_CAP_PRESENCE_DETECT_STATE,Presence Detect State. This bit indicates the presence of an adapter in the slot reflected by the logical 'OR' of the Physical Layer in-band presence detect mechanism and if present any out-of-band presence detect.." "0,1" newline rbitfld.long 0x18 21. "PCIE_CAP_MRL_SENSOR_STATE,MRL Sensor State. This bit reports the status of the MRL sensor if implemented. Defined encodings are: - 0b: MRL Closed - 1b: MRL Open" "0,1" bitfld.long 0x18 20. "PCIE_CAP_CMD_CPLD,Command Completed. If Command Completed notification is supported (if the No Command Completed Support bit in the Slot Capabilities register is 0b) this bit is set when a hot-plug command has completed and the Hot-Plug Controller is.." "0,1" newline bitfld.long 0x18 19. "PCIE_CAP_PRESENCE_DETECTED_CHANGED,Presence Detect Changed. This bit is set when the value reported in the Presence Detect State bit is changed." "0,1" bitfld.long 0x18 18. "PCIE_CAP_MRL_SENSOR_CHANGED,MRL Sensor Changed. If an MRL sensor is implemented this bit is set when a MRL Sensor state change is detected. If an MRL sensor is not implemented this bit must not be set." "0,1" newline bitfld.long 0x18 17. "PCIE_CAP_POWER_FAULT_DETECTED,Power Fault Detected. If a Power Controller that supports power fault detection is implemented this bit issSet when the Power Controller detects a power fault at this slot. Note: Depending on hardware capability it is.." "0,1" bitfld.long 0x18 16. "PCIE_CAP_ATTENTION_BUTTON_PRESSED,Attention Button Pressed. If an Attention Button is implemented this bit is set when the attention button is pressed. If an Attention Button is not supported this bit must not be set." "0,1" newline rbitfld.long 0x18 14.--15. "RSVDP_14,Reserved for future use." "0,1,2,3" bitfld.long 0x18 12. "PCIE_CAP_DLL_STATE_CHANGED_EN,Data Link Layer State Changed Enable. If the Data Link Layer Link Active Reporting capability is 1b this bit enables software notification when Data Link Layer Link Active bit is changed. If the Data Link Layer Link Active.." "0,1" newline bitfld.long 0x18 11. "PCIE_CAP_ELECTROMECH_INTERLOCK_CTRL,Electromechanical Interlock Control. If an Electromechanical Interlock is implemented a write of 1b to this bit causes the state of the interlock to toggle. A write of 0b to this bit has no effect. A read of this bit.." "0,1" bitfld.long 0x18 10. "PCIE_CAP_POWER_CONTROLLER_CTRL,Power Controller Control. If a Power Controller is implemented this bit when written sets the power state of the slot per the defined encodings. Reads of this bit must reflect the value from the latest write even if the.." "0,1" newline bitfld.long 0x18 8.--9. "PCIE_CAP_POWER_INDICATOR_CTRL,Power Indicator Control. If a Power Indicator is implemented writes to this field set the Power Indicator to the written state. Reads of this field must reflect the value from the latest write even if the corresponding.." "0,1,2,3" bitfld.long 0x18 6.--7. "PCIE_CAP_ATTENTION_INDICATOR_CTRL,Attention Indicator Control. If an Attention Indicator is implemented writes to this field set the Attention Indicator to the written state. Reads of this field must reflect the value from the latest write even if the.." "0,1,2,3" newline bitfld.long 0x18 5. "PCIE_CAP_HOT_PLUG_INT_EN,Hot-Plug Interrupt Enable. When set this bit enables generation of an interrupt on enabled hot-plug events. If the Hot Plug Capable bit in the Slot Capabilities register is clear this bit is permitted to be read-only with a.." "0,1" bitfld.long 0x18 4. "PCIE_CAP_CMD_CPL_INT_EN,Command Completed Interrupt Enable. If Command Completed notification is supported (if the No Command Completed Support bit in the Slot Capabilities register is 0b) when set this bit enables software notification when a hot-plug.." "0,1" newline bitfld.long 0x18 3. "PCIE_CAP_PRESENCE_DETECT_CHANGE_EN,Presence Detect Changed Enable. When set this bit enables software notification on a presence detect changed event (for more details see Section 6.7.3 of PCI Express Base Specification). If the Hot-Plug Capable bit in.." "0,1" bitfld.long 0x18 2. "PCIE_CAP_MRL_SENSOR_CHANGED_EN,MRL Sensor Changed Enable. When set this bit enables software notification on a MRL sensor changed event (for more details see Section 6.7.3 of PCI Express Base Specification). If the MRL Sensor Present bit in the Slot.." "0,1" newline bitfld.long 0x18 1. "PCIE_CAP_POWER_FAULT_DETECTED_EN,Power Fault Detected Enable. When set this bit enables software notification on a power fault event (for more details see Section 6.7.3 of PCI Express Base Specification). If a Power Controller that supports power fault.." "0,1" bitfld.long 0x18 0. "PCIE_CAP_ATTENTION_BUTTON_PRESSED_EN,Attention Button Pressed Enable. When set to 1b this bit enables software notification on an attention button pressed event (for more details see Section 6.7.3 of PCI Express Base Specification). If the Attention.." "0,1" line.long 0x1C "ROOT_CONTROL_ROOT_CAPABILITIES_REG,Root Control and Capabilities Register. This register controls PCI Express Root Complex specific parameters and identifies PCI Express Root Port specific capabilities." hexmask.long.word 0x1C 17.--31. 1. "RSVDP_17,Reserved for future use." bitfld.long 0x1C 16. "PCIE_CAP_CRS_SW_VISIBILITY,CRS Software Visibility Capable. For a description of this standard PCIe register field see the PCI Express Base Specification. CRS Software Visibility. When set this bit indicates that the Root Port is capable of returning.." "0,1" newline hexmask.long.word 0x1C 5.--15. 1. "RSVDP_5,Reserved for future use." bitfld.long 0x1C 4. "PCIE_CAP_CRS_SW_VISIBILITY_EN,CRS Software Visibility Enable. When set this bit enables the Root Port to return Configuration Request Retry Status (CRS) Completion Status to software (for more details see section 2.3.1 of PCI Express Base.." "0,1" newline bitfld.long 0x1C 3. "PCIE_CAP_PME_INT_EN,PME Interrupt Enable. When set this bit enables PME interrupt generation upon receipt of a PME Message as reflected in the PME Status bit (for more details see Table 7-29 of PCI Express Base Specification). A PME interrupt is also.." "0,1" bitfld.long 0x1C 2. "PCIE_CAP_SYS_ERR_ON_FATAL_ERR_EN,System Error on Fatal Error Enable. If set this bit indicates that a System Error should be generated if a Fatal error (ERR_FATAL) is reported by any of the devices in the Hierarchy Domain associated with this Root Port.." "0,1" newline bitfld.long 0x1C 1. "PCIE_CAP_SYS_ERR_ON_NON_FATAL_ERR_EN,System Error on Non-Fatal Error Enable. If set this bit indicates that a System Error should be generated if a Non-fatal error (ERR_NONFATAL) is reported by any of the devices in the Hierarchy Domain associated with.." "0,1" bitfld.long 0x1C 0. "PCIE_CAP_SYS_ERR_ON_CORR_ERR_EN,System Error on Correctable Error Enable. If set this bit indicates that a System Error should be generated if a correctable error (ERR_COR) is reported by any of the devices in the Hierarchy Domain associated with this.." "0,1" line.long 0x20 "ROOT_STATUS_REG,Root Status Register. The Root Status register provides information about PCI Express device specific parameters." hexmask.long.word 0x20 18.--31. 1. "RSVDP_18,Reserved for future use." rbitfld.long 0x20 17. "PCIE_CAP_PME_PENDING,PME Pending. This bit indicates that another PME is pending when the PME Status bit is s et. When the PME Status bit is cleared by software; the PME is delivered by hardware by setting the PME Status bit again and updating the PME.." "0,1" newline bitfld.long 0x20 16. "PCIE_CAP_PME_STATUS,PME Status. This bit indicates that PME was asserted by the PME Requester indicated in the PME Requester ID field. Subsequent PMEs are kept pending until the status register is cleared by software by writing a 1b." "0,1" hexmask.long.word 0x20 0.--15. 1. "PCIE_CAP_PME_REQ_ID,PME Requester ID. This field indicates the PCI Requester ID of the last PME Requester. This field is only valid when the PME Status bit is set." line.long 0x24 "DEVICE_CAPABILITIES2_REG,Device Capabilities 2 Register." bitfld.long 0x24 31. "PCIE_CAP_FRS_SUPPORTED,FRS Supported. When set indicates support for the optional Function Readiness Status (FRS) capability. Must be set for all Functions that support generation or reception capabilities of FRS Messages. Must not be set by Switch.." "0,1" hexmask.long.byte 0x24 24.--30. 1. "RSVDP_24,Reserved for future use." newline bitfld.long 0x24 22.--23. "PCIE_CAP2_CFG_MAX_END2END_TLP_PRFXS,Max End-End TLP Prefixes. Indicates the maximum number of End-End TLP Prefixes supported by this Function. For more details see Section 2.2.10.2 of PCI Express Base Specification. Values are: - 01b: 1 End-End TLP.." "0,1,2,3" bitfld.long 0x24 21. "PCIE_CAP2_CFG_END2END_TLP_PRFX_SUPPORT,End-End TLP Prefix Supported. Indicates whether End-End TLP Prefix support is offered by a Function. Values are: - 0b: No Support - 1b: Support is provided to receive TLPs containing End-End TLP Prefixes. All Ports.." "0,1" newline bitfld.long 0x24 20. "PCIE_CAP2_CFG_EXTND_FMT_SUPPORT,Extended Fmt Field Supported. If set the Function supports the 3-bit definition of the Fmt field. If clear the Function supports a 2-bit definition of the Fmt field. For more details see section 2.2 of PCI Express Base.." "0,1" rbitfld.long 0x24 17. "PCIE_CAP2_10_BIT_TAG_REQ_SUPPORT,10-Bit Tag Requester Supported. If this bit is set the Function supports 10-Bit Tag Requester capability; otherwise the Function does not. This bit must not be set if the 10-Bit Tag Completer Supported bit is clear." "0,1" newline rbitfld.long 0x24 16. "PCIE_CAP2_10_BIT_TAG_COMP_SUPPORT,10-Bit Tag Completer Supported. If this bit is set the Function supports 10-Bit Tag Completer capability; otherwise the Function does not. For more details see section 2.2.6.2. of PCI Express Base Specification." "0,1" rbitfld.long 0x24 13. "PCIE_CAP_TPH_CMPLT_SUPPORT_1,TPH Completer Supported Bit 1." "0,1" newline rbitfld.long 0x24 12. "PCIE_CAP_TPH_CMPLT_SUPPORT_0,TPH Completer Supported Bit 0. Value of this bit along with TPH Completer Supported Bit 1 indicates Completer support for TPH or Extended TPH. Applicable only to Root Ports and Endpoints. For all other Functions this field.." "0,1" bitfld.long 0x24 11. "PCIE_CAP_LTR_SUPP,LTR Mechanism Supported. A value of 1b indicates support for the optional Latency Tolerance Reporting (LTR) mechanism. Root Ports Switches and Endpoints are permitted to implement this capability. For a Multi-Function Device associated.." "0,1" newline rbitfld.long 0x24 10. "PCIE_CAP_NO_RO_EN_PR2PR_PAR,No RO-enabled PR-PR Passing. If this bit is set the routing element never carries out the passing permitted by Table 2-39 of PCI Express Base Specification entry A2b that is associated with the Relaxed Ordering Attribute.." "0,1" rbitfld.long 0x24 9. "PCIE_CAP_128_CAS_CPL_SUPP,128-bit CAS Completer Supported. Applicable to Functions with Memory Space BARs as well as all Root Ports; must be 0b otherwise. This bit must be set to 1b if the Function supports this optional capability. For more details see.." "0,1" newline rbitfld.long 0x24 8. "PCIE_CAP_64_ATOMIC_CPL_SUPP,64-bit AtomicOp Completer Supported. Applicable to Functions with Memory Space BARs as well as all Root Ports; must be 0b otherwise. Includes FetchAdd Swap and CAS AtomicOps. This bit must be set to 1b if the Function.." "0,1" rbitfld.long 0x24 7. "PCIE_CAP_32_ATOMIC_CPL_SUPP,32-bit AtomicOp Completer Supported. Applicable to Functions with Memory Space BARs as well as all Root Ports; must be 0b otherwise. Includes FetchAdd Swap and CAS AtomicOps. This bit must be set to 1b if the Function.." "0,1" newline rbitfld.long 0x24 6. "PCIE_CAP_ATOMIC_ROUTING_SUPP,AtomicOp Routing Supported. Applicable only to Switch Upstream Ports Switch Downstream Ports and Root Ports; must be 0b for other Function types. This bit must be set to 1b if the Port supports this optional capability. For.." "0,1" rbitfld.long 0x24 5. "PCIE_CAP_ARI_FORWARD_SUPPORT,ARI Forwarding Supported. Applicable only to Switch Downstream Ports and Root Ports; must be 0b for other Function types. This bit must be set to 1b if a Switch Downstream Port or Root Port supports this optional capability." "0,1" newline rbitfld.long 0x24 4. "PCIE_CAP_CPL_TIMEOUT_DISABLE_SUPPORT,Completion Timeout Disable Supported. A value of 1b indicates support for the Completion Timeout Disable mechanism. The Completion Timeout Disable mechanism is required for Endpoints that issue Requests on their own.." "0,1" hexmask.long.byte 0x24 0.--3. 1. "PCIE_CAP_CPL_TIMEOUT_RANGE,Completion Timeout Ranges Supported. This field indicates device Function support for the optional Completion Timeout programmability mechanism. This mechanism allows system software to modify the Completion Timeout value. This.." line.long 0x28 "DEVICE_CONTROL2_DEVICE_STATUS2_REG,Device Control 2 and Status 2 Register." hexmask.long.word 0x28 16.--31. 1. "RSVDP_16,Reserved for future use." bitfld.long 0x28 15. "PCIE_CTRL2_CFG_END2END_TLP_PFX_BLCK,End-End TLP Prefix Blocking. Controls whether the routing function is permitted to forward TLPs containing an End-End TLP Prefix. Values are: - 0b: Forwarding Enabled - Function is permitted to send TLPs with End-End.." "0,1" newline rbitfld.long 0x28 11. "RSVDP_11,Reserved for future use." "0,1" bitfld.long 0x28 10. "PCIE_CAP_LTR_EN,LTR Mechanism Enable. When set to 1b this bit enables Upstream Ports to send LTR messages and Downstream Ports to process LTR Messages. For a Multi-Function Device associated with an Upstream Port of a device that implements LTR the bit.." "0,1" newline rbitfld.long 0x28 5. "PCIE_CAP_ARI_FORWARD_SUPPORT_CS,ARI Forwarding Enable. When set the Downstream Port disables its traditional Device Number field being 0 enforcement when turning a Type 1 Configuration Request into a Type 0 Configuration Request permitting access to.." "0,1" bitfld.long 0x28 4. "PCIE_CAP_CPL_TIMEOUT_DISABLE,Completion Timeout Disable. When set this bit disables the Completion Timeout mechanism. This bit is required for all Functions that support the Completion Timeout Disable Capability. Functions that do not support this.." "0,1" newline hexmask.long.byte 0x28 0.--3. 1. "PCIE_CAP_CPL_TIMEOUT_VALUE,Completion Timeout Value. In device Functions that support Completion Timeout programmability this field allows system software to modify the Completion Timeout value. This field is applicable to Root Ports Endpoints that.." line.long 0x2C "LINK_CAPABILITIES2_REG,Link Capabilities 2 Register." bitfld.long 0x2C 31. "DRS_SUPPORTED,DRS Supported. When set indicates support for the optional Device Readiness Status (DRS) capability. Must be Set in Downstream Ports that support DRS. Must be Set in Downstream Ports that support FRS. For Upstream Ports that support DRS.." "0,1" hexmask.long.byte 0x2C 25.--30. 1. "RSVDP_25,Reserved for future use." newline hexmask.long.word 0x2C 9.--22. 1. "RSVDP_9,Reserved for future use." rbitfld.long 0x2C 8. "PCIE_CAP_CROSS_LINK_SUPPORT,Crosslink Supported. When set to 1b this bit indicates that the associated Port supports crosslinks (for more details see section 4.2.6.3.1 of PCI Express Base Specification). When set to 0b on a Port that supports Link.." "0,1" newline hexmask.long.byte 0x2C 1.--7. 1. "PCIE_CAP_SUPPORT_LINK_SPEED_VECTOR,Supported Link Speeds Vector. This field indicates the supported Link speed(s) of the associated Port. For each bit a value of 1b indicates that the corresponding Link speed is supported; otherwise the Link speed is.." rbitfld.long 0x2C 0. "RSVDP_0,Reserved for future use." "0,1" line.long 0x30 "LINK_CONTROL2_LINK_STATUS2_REG,Link Control 2 and Status 2 Register." bitfld.long 0x30 31. "DRS_MESSAGE_RECEIVED,DRS Message Received. This bit must be set whenever the Port receives a DRS Message. This bit must be cleared in DL_Down. This bit must be implemented in any Downstream Port where the DRS Supported bit is Set in the Link Capabilities.." "0,1" rbitfld.long 0x30 28.--30. "DOWNSTREAM_COMPO_PRESENCE,Downstream Component Presence. This field indicates the presence and DRS status for the Downstream Component if any connected to the Link; defined values are: - 000b: Link Down - Presence Not Determined - 001b: Link Down -.." "0,1,2,3,4,5,6,7" newline rbitfld.long 0x30 26.--27. "RSVDP_26,Reserved for future use." "0,1,2,3" bitfld.long 0x30 21. "PCIE_CAP_LINK_EQ_REQ,Link Equalization Request 8.0 GT/s. This bit is set by hardware to request the 8.0 GT/s Link equalization process to be performed on the Link. For more details see sections 4.2.3 and 4.2.6.4.2 of PCI Express Base Specification. For.." "0,1" newline rbitfld.long 0x30 20. "PCIE_CAP_EQ_CPL_P3,EEqualization 8.0 GT/s Phase 3 Successful. When set to 1b this bit indicates that Phase 3 of the 8.0 GT/s Transmitter Equalization procedure has successfully completed. Details of the Transmitter Equalization process and when this bit.." "0,1" rbitfld.long 0x30 19. "PCIE_CAP_EQ_CPL_P2,Equalization 8.0 GT/s Phase 2 Successful. When set to 1b this bit indicates that Phase 2 of the 8.0 GT/s Transmitter Equalization procedure has successfully completed. Details of the Transmitter Equalization process and when this bit.." "0,1" newline rbitfld.long 0x30 18. "PCIE_CAP_EQ_CPL_P1,Equalization 8.0 GT/s Phase 1 Successful. When set to 1b this bit indicates that Phase 1 of the 8.0 GT/s Transmitter Equalization procedure has successfully completed. Details of the Transmitter Equalization process and when this bit.." "0,1" rbitfld.long 0x30 17. "PCIE_CAP_EQ_CPL,Equalization 8.0 GT/s Complete. When set to 1b this bit indicates that the Transmitter Equalization procedure at the 8.0 GT/s data rate has completed. Details of the Transmitter Equalization process and when this bit needs to be set to.." "0,1" newline rbitfld.long 0x30 16. "PCIE_CAP_CURR_DEEMPHASIS,Current De-emphasis Level. When the Link is operating at 5.0 GT/s speed this bit reflects the level of de-emphasis. Encodings: - 1b: -3.5 dB - 0b: -6 dB The value in this bit is undefined when the Link is not operating at 5.0.." "0,1" hexmask.long.byte 0x30 12.--15. 1. "PCIE_CAP_COMPLIANCE_PRESET,Compliance Preset/De-emphasis. For 8.0 GT/s and higher Data Rate: This field sets the Transmitter Preset in Polling.Compliance state if the entry occurred due to the Enter Compliance bit being 1b. The encodings are defined in.." newline bitfld.long 0x30 11. "PCIE_CAP_COMPLIANCE_SOS,Compliance SOS. When set to 1b the LTSSM is required to send SKP Ordered Sets between sequences when sending the Compliance Pattern or Modified Compliance Pattern. For a Multi-Function Device associated with an Upstream Port the.." "0,1" bitfld.long 0x30 10. "PCIE_CAP_ENTER_MODIFIED_COMPLIANCE,Enter Modified Compliance. When this bit is set to 1b the device transmits Modified Compliance Pattern if the LTSSM enters Polling.Compliance substate. Components that support only the 2.5 GT/s speed are permitted to.." "0,1" newline bitfld.long 0x30 7.--9. "PCIE_CAP_TX_MARGIN,Transmit Margin - This field controls the value of the non-deemphasized voltage level at the Transmitter pins. This field is reset to 000b on entry to the LTSSM Polling.Configuration substate (see Chapter 4 of PCI Express Base.." "0,1,2,3,4,5,6,7" bitfld.long 0x30 6. "PCIE_CAP_SEL_DEEMPHASIS,Selectable De-emphasis. When the Link is operating at 5.0 GT/s speed this bit is used to control the transmit de-emphasis of the link in specific situations. For more details see section 4.2.6 of PCI Express Base Specification." "0,1" newline bitfld.long 0x30 5. "PCIE_CAP_HW_AUTO_SPEED_DISABLE,Hardware Autonomous Speed Disable. When set this bit disables hardware from changing the Link speed for device-specific reasons other than attempting to correct unreliable Link operation by reducing Link speed. Initial.." "0,1" bitfld.long 0x30 4. "PCIE_CAP_ENTER_COMPLIANCE,Enter Compliance. Software is permitted to force a Link to enter Compliance mode (at the speed indicated in the Target Link Speed field and the de-emphasis/preset level indicated by the Compliance Preset/De-emphasis field) by.." "0,1" newline hexmask.long.byte 0x30 0.--3. 1. "PCIE_CAP_TARGET_LINK_SPEED,Target Link Speed. For Downstream Ports this field sets an upper limit on Link operational speed by restricting the values advertised by the Upstream component in its training sequences. The encoded value specifies a bit.." tree.end tree "PF0_AER_CAP (PF Advanced Error Reporting Capability Structure)" group.long (0x0+0x100)++0x1B line.long 0x0 "AER_EXT_CAP_HDR_OFF,Advanced Error Reporting Extended Capability Header. For a description of this standard PCIe register. see the PCI Express Specification." hexmask.long.word 0x0 20.--31. 1. "NEXT_OFFSET,Next Capability Offset. For a description of this standard PCIe register field see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky).." hexmask.long.byte 0x0 16.--19. 1. "CAP_VERSION,Capability Version. For a description of this standard PCIe register field see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else.." hexmask.long.word 0x0 0.--15. 1. "CAP_ID,AER Extended Capability ID. For a description of this standard PCIe register field see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else.." line.long 0x4 "UNCORR_ERR_STATUS_OFF,Uncorrectable Error Status Register. For a description of this standard PCIe register. see the PCI Express Specification." hexmask.long.byte 0x4 27.--31. 1. "RSVDP_27,Reserved for future use." bitfld.long 0x4 25. "TLP_PRFX_BLOCKED_ERR_STATUS,TLP Prefix Blocked Error Status. For a description of this standard PCIe register field see the PCI Express Specification. Note: Not supported." "0,1" rbitfld.long 0x4 23. "RSVDP_23,Reserved for future use." "0,1" newline bitfld.long 0x4 22. "INTERNAL_ERR_STATUS,Uncorrectable Internal Error Status. For a description of this standard PCIe register field see the PCI Express Specification. The controller sets this bit when your application asserts app_err_bus[9]. It does not set this bit when.." "0,1" bitfld.long 0x4 20. "UNSUPPORTED_REQ_ERR_STATUS,Unsupported Request Error Status. For a description of this standard PCIe register field see the PCI Express Specification." "0,1" bitfld.long 0x4 19. "ECRC_ERR_STATUS,ECRC Error Status. For a description of this standard PCIe register field see the PCI Express Specification. Note:If CX_ECRC_ENABLE=0 the register field always reads 0." "0,1" newline bitfld.long 0x4 18. "MALF_TLP_ERR_STATUS,Malformed TLP Status. For a description of this standard PCIe register field see the PCI Express Specification." "0,1" bitfld.long 0x4 17. "REC_OVERFLOW_ERR_STATUS,Receiver Overflow Status. For a description of this standard PCIe register field see the PCI Express Specification." "0,1" bitfld.long 0x4 16. "UNEXP_CMPLT_ERR_STATUS,Unexpected Completion Status. For a description of this standard PCIe register field see the PCI Express Specification." "0,1" newline bitfld.long 0x4 15. "CMPLT_ABORT_ERR_STATUS,Completer Abort Status. For a description of this standard PCIe register field see the PCI Express Specification." "0,1" bitfld.long 0x4 14. "CMPLT_TIMEOUT_ERR_STATUS,Completion Timeout Status. For a description of this standard PCIe register field see the PCI Express Specification." "0,1" bitfld.long 0x4 13. "FC_PROTOCOL_ERR_STATUS,Flow Control Protocol Error Status. For a description of this standard PCIe register field see the PCI Express Specification." "0,1" newline bitfld.long 0x4 12. "POIS_TLP_ERR_STATUS,Poisoned TLP Status. For a description of this standard PCIe register field see the PCI Express Specification." "0,1" hexmask.long.byte 0x4 6.--11. 1. "RSVDP_6,Reserved for future use." bitfld.long 0x4 5. "SURPRISE_DOWN_ERR_STATUS,Surprise Down Error Status (Optional). For a description of this standard PCIe register field see the PCI Express Specification." "0,1" newline bitfld.long 0x4 4. "DL_PROTOCOL_ERR_STATUS,Data Link Protocol Error Status. For a description of this standard PCIe register field see the PCI Express Specification." "0,1" hexmask.long.byte 0x4 0.--3. 1. "RSVDP_0,Reserved for future use." line.long 0x8 "UNCORR_ERR_MASK_OFF,Uncorrectable Error Mask Register. For a description of this standard PCIe register. see the PCI Express Specification." hexmask.long.byte 0x8 27.--31. 1. "RSVDP_27,Reserved for future use." bitfld.long 0x8 25. "TLP_PRFX_BLOCKED_ERR_MASK,TLP Prefix Blocked Error Mask. For a description of this standard PCIe register field see the PCI Express Specification. Note: Not supported. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi:.." "0,1" rbitfld.long 0x8 23. "RSVDP_23,Reserved for future use." "0,1" newline bitfld.long 0x8 22. "INTERNAL_ERR_MASK,Uncorrectable Internal Error Mask (Optional). For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." "0,1" rbitfld.long 0x8 21. "ACS_VIOLATION_MASK,ACS Violation Mask. Setting the ACS Violation Mask bit disables error logging and signaling for ACS Violation errors. The bit is Read-Only Zero for upstream ports when ACS P2P Egress Control Enable is not set. For a description of.." "0,1" bitfld.long 0x8 20. "UNSUPPORTED_REQ_ERR_MASK,Unsupported Request Error Mask. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." "0,1" newline bitfld.long 0x8 19. "ECRC_ERR_MASK,ECRC Error Mask (Optional). For a description of this standard PCIe register field see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W (sticky) Note: This register.." "0,1" bitfld.long 0x8 18. "MALF_TLP_ERR_MASK,Malformed TLP Mask. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." "0,1" bitfld.long 0x8 17. "REC_OVERFLOW_ERR_MASK,Receiver Overflow Mask (Optional). For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." "0,1" newline bitfld.long 0x8 16. "UNEXP_CMPLT_ERR_MASK,Unexpected Completion Mask. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." "0,1" bitfld.long 0x8 15. "CMPLT_ABORT_ERR_MASK,Completer Abort Error Mask (Optional). For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." "0,1" bitfld.long 0x8 14. "CMPLT_TIMEOUT_ERR_MASK,Completion Timeout Error Mask. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." "0,1" newline bitfld.long 0x8 13. "FC_PROTOCOL_ERR_MASK,Flow Control Protocol Error Mask. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." "0,1" bitfld.long 0x8 12. "POIS_TLP_ERR_MASK,Poisoned TLP Error Mask. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." "0,1" hexmask.long.byte 0x8 6.--11. 1. "RSVDP_6,Reserved for future use." newline rbitfld.long 0x8 5. "SURPRISE_DOWN_ERR_MASK,Surprise Down Error Mask. For a description of this standard PCIe register field see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi:.." "0,1" bitfld.long 0x8 4. "DL_PROTOCOL_ERR_MASK,Data Link Protocol Error Mask. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." "0,1" hexmask.long.byte 0x8 0.--3. 1. "RSVDP_0,Reserved for future use." line.long 0xC "UNCORR_ERR_SEV_OFF,Uncorrectable Error Severity Register. For a description of this standard PCIe register. see the PCI Express Specification." hexmask.long.byte 0xC 27.--31. 1. "RSVDP_27,Reserved for future use." bitfld.long 0xC 25. "TLP_PRFX_BLOCKED_ERR_SEVERITY,TLP Prefix Blocked Error Severity (Optional). For a description of this standard PCIe register field see the PCI Express Specification. Note: Not supported. Note: The access attributes of this field are as follows: - Wire:.." "0,1" rbitfld.long 0xC 24. "ATOMIC_EGRESS_BLOCKED_ERR_SEVERITY,AtomicOp Egress Blocked Severity (Optional). For a description of this standard PCIe register field see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi:.." "0,1" newline rbitfld.long 0xC 23. "RSVDP_23,Reserved for future use." "0,1" bitfld.long 0xC 22. "INTERNAL_ERR_SEVERITY,Uncorrectable Internal Error Severity (Optional). For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." "0,1" bitfld.long 0xC 20. "UNSUPPORTED_REQ_ERR_SEVERITY,Unsupported Request Error Severity. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." "0,1" newline bitfld.long 0xC 19. "ECRC_ERR_SEVERITY,ECRC Error Severity (Optional). For a description of this standard PCIe register field see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W (sticky) Note: This.." "0,1" bitfld.long 0xC 18. "MALF_TLP_ERR_SEVERITY,Malformed TLP Severity. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." "0,1" bitfld.long 0xC 17. "REC_OVERFLOW_ERR_SEVERITY,Receiver Overflow Error Severity (Optional). For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." "0,1" newline bitfld.long 0xC 16. "UNEXP_CMPLT_ERR_SEVERITY,Unexpected Completion Error Severity. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." "0,1" bitfld.long 0xC 15. "CMPLT_ABORT_ERR_SEVERITY,Completer Abort Error Severity (Optional). For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." "0,1" bitfld.long 0xC 14. "CMPLT_TIMEOUT_ERR_SEVERITY,Completion Timeout Error Severity. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." "0,1" newline bitfld.long 0xC 13. "FC_PROTOCOL_ERR_SEVERITY,Flow Control Protocol Error Severity (Optional). For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." "0,1" bitfld.long 0xC 12. "POIS_TLP_ERR_SEVERITY,Poisoned TLP Severity. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." "0,1" hexmask.long.byte 0xC 6.--11. 1. "RSVDP_6,Reserved for future use." newline rbitfld.long 0xC 5. "SURPRISE_DOWN_ERR_SVRITY,Surprise Down Error Severity (Optional). For a description of this standard PCIe register field see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi:.." "0,1" bitfld.long 0xC 4. "DL_PROTOCOL_ERR_SEVERITY,Data Link Protocol Error Severity. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." "0,1" hexmask.long.byte 0xC 0.--3. 1. "RSVDP_0,Reserved for future use." line.long 0x10 "CORR_ERR_STATUS_OFF,Correctable Error Status Register. For a description of this standard PCIe register. see the PCI Express Specification." hexmask.long.word 0x10 16.--31. 1. "RSVDP_16,Reserved for future use." bitfld.long 0x10 15. "HEADER_LOG_OVERFLOW_STATUS,Header Log Overflow Error Status (Optional). For a description of this standard PCIe register field see the PCI Express Specification." "0,1" bitfld.long 0x10 14. "CORRECTED_INT_ERR_STATUS,Corrected Internal Error Status (Optional). For a description of this standard PCIe register field see the PCI Express Specification." "0,1" newline bitfld.long 0x10 13. "ADVISORY_NON_FATAL_ERR_STATUS,Advisory Non-Fatal Error Status. For a description of this standard PCIe register field see the PCI Express Specification." "0,1" bitfld.long 0x10 12. "RPL_TIMER_TIMEOUT_STATUS,Replay Timer Timeout Status. For a description of this standard PCIe register field see the PCI Express Specification." "0,1" rbitfld.long 0x10 9.--11. "RSVDP_9,Reserved for future use." "0,1,2,3,4,5,6,7" newline bitfld.long 0x10 8. "REPLAY_NO_ROLEOVER_STATUS,REPLAY_NUM Rollover Status. For a description of this standard PCIe register field see the PCI Express Specification." "0,1" bitfld.long 0x10 7. "BAD_DLLP_STATUS,Bad DLLP Status. For a description of this standard PCIe register field see the PCI Express Specification." "0,1" bitfld.long 0x10 6. "BAD_TLP_STATUS,Bad TLP Status. For a description of this standard PCIe register field see the PCI Express Specification." "0,1" newline hexmask.long.byte 0x10 1.--5. 1. "RSVDP_1,Reserved for future use." bitfld.long 0x10 0. "RX_ERR_STATUS,Receiver Error Status (Optional). For a description of this standard PCIe register field see the PCI Express Specification." "0,1" line.long 0x14 "CORR_ERR_MASK_OFF,Correctable Error Mask Register. For a description of this standard PCIe register. see the PCI Express Specification." hexmask.long.word 0x14 16.--31. 1. "RSVDP_16,Reserved for future use." bitfld.long 0x14 15. "HEADER_LOG_OVERFLOW_MASK,Header Log Overflow Error Mask (Optional). For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." "0,1" bitfld.long 0x14 14. "CORRECTED_INT_ERR_MASK,Corrected Internal Error Mask (Optional). For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." "0,1" newline bitfld.long 0x14 13. "ADVISORY_NON_FATAL_ERR_MASK,Advisory Non-Fatal Error Mask. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." "0,1" bitfld.long 0x14 12. "RPL_TIMER_TIMEOUT_MASK,Replay Timer Timeout Mask. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." "0,1" rbitfld.long 0x14 9.--11. "RSVDP_9,Reserved for future use." "0,1,2,3,4,5,6,7" newline bitfld.long 0x14 8. "REPLAY_NO_ROLEOVER_MASK,REPLAY_NUM Rollover Mask. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." "0,1" bitfld.long 0x14 7. "BAD_DLLP_MASK,Bad DLLP Mask. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." "0,1" bitfld.long 0x14 6. "BAD_TLP_MASK,Bad TLP Mask. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." "0,1" newline hexmask.long.byte 0x14 1.--5. 1. "RSVDP_1,Reserved for future use." bitfld.long 0x14 0. "RX_ERR_MASK,Receiver Error Mask (Optional). For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." "0,1" line.long 0x18 "ADV_ERR_CAP_CTRL_OFF,Advanced Error Capabilities and Control Register. For a description of this standard PCIe register. see the PCI Express Specification." hexmask.long.tbyte 0x18 13.--31. 1. "RSVDP_13,Reserved for future use." rbitfld.long 0x18 12. "CTO_PRFX_HDR_LOG_CAP,TLP Prefix Log Present. For a description of this standard PCIe register field see the PCI Express Specification." "0,1" rbitfld.long 0x18 11. "TLP_PRFX_LOG_PRESENT,Completion Timeout Prefix/Header Log Capable. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." "0,1" newline rbitfld.long 0x18 10. "MULTIPLE_HEADER_EN,Multiple Header Recording Enable. For a description of this standard PCIe register field see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R (sticky) Note: This.." "0,1" rbitfld.long 0x18 9. "MULTIPLE_HEADER_CAP,Multiple Header Recording Capable. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." "0,1" bitfld.long 0x18 8. "ECRC_CHECK_EN,ECRC Check Enable. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." "0,1" newline rbitfld.long 0x18 7. "ECRC_CHECK_CAP,ECRC Check Capable. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." "0,1" bitfld.long 0x18 6. "ECRC_GEN_EN,ECRC Generation Enable. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." "0,1" rbitfld.long 0x18 5. "ECRC_GEN_CAP,ECRC Generation Capable. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." "0,1" newline hexmask.long.byte 0x18 0.--4. 1. "FIRST_ERR_POINTER,First Error Pointer. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." rgroup.long (0x1C+0x100)++0xF line.long 0x0 "HDR_LOG_0_OFF,Header Log Register 0. For a description of this standard PCIe register. see the PCI Express Specification." hexmask.long.byte 0x0 24.--31. 1. "FIRST_DWORD_FOURTH_BYTE,Byte 3 of Header log register of First 32 bit Data Word. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." hexmask.long.byte 0x0 16.--23. 1. "FIRST_DWORD_THIRD_BYTE,Byte 2 of Header log register of First 32 bit Data Word. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." hexmask.long.byte 0x0 8.--15. 1. "FIRST_DWORD_SECOND_BYTE,Byte 1 of Header log register of First 32 bit Data Word. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." newline hexmask.long.byte 0x0 0.--7. 1. "FIRST_DWORD_FIRST_BYTE,Byte 0 of Header log register of First 32 bit Data Word. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." line.long 0x4 "HDR_LOG_1_OFF,Header Log Register 1. For a description of this standard PCIe register. see the PCI Express Specification." hexmask.long.byte 0x4 24.--31. 1. "SECOND_DWORD_FOURTH_BYTE,Byte 3 of Header log register of Second 32 bit Data Word. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." hexmask.long.byte 0x4 16.--23. 1. "SECOND_DWORD_THIRD_BYTE,Byte 2 of Header log register of Second 32 bit Data Word. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." hexmask.long.byte 0x4 8.--15. 1. "SECOND_DWORD_SECOND_BYTE,Byte 1 of Header log register of Second 32 bit Data Word. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." newline hexmask.long.byte 0x4 0.--7. 1. "SECOND_DWORD_FIRST_BYTE,Byte 0 of Header log register of Second 32 bit Data Word. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." line.long 0x8 "HDR_LOG_2_OFF,Header Log Register 2. For a description of this standard PCIe register. see the PCI Express Specification." hexmask.long.byte 0x8 24.--31. 1. "THIRD_DWORD_FOURTH_BYTE,Byte 3 of Header log register of Third 32 bit Data Word. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." hexmask.long.byte 0x8 16.--23. 1. "THIRD_DWORD_THIRD_BYTE,Byte 2 of Header log register of Third 32 bit Data Word. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." hexmask.long.byte 0x8 8.--15. 1. "THIRD_DWORD_SECOND_BYTE,Byte 1 of Header log register of Third 32 bit Data Word. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." newline hexmask.long.byte 0x8 0.--7. 1. "THIRD_DWORD_FIRST_BYTE,Byte 0 of Header log register of Third 32 bit Data Word. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." line.long 0xC "HDR_LOG_3_OFF,Header Log Register 3. For a description of this standard PCIe register. see the PCI Express Specification." hexmask.long.byte 0xC 24.--31. 1. "FOURTH_DWORD_FOURTH_BYTE,Byte 3 of Header log register of Fourth 32 bit Data Word. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." hexmask.long.byte 0xC 16.--23. 1. "FOURTH_DWORD_THIRD_BYTE,Byte 2 of Header log register of Fourth 32 bit Data Word. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." hexmask.long.byte 0xC 8.--15. 1. "FOURTH_DWORD_SECOND_BYTE,Byte 1 of Header log register of Fourth 32 bit Data Word. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." newline hexmask.long.byte 0xC 0.--7. 1. "FOURTH_DWORD_FIRST_BYTE,Byte 0 of Header log register of Fourth 32 bit Data Word. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." group.long (0x2C+0x100)++0x7 line.long 0x0 "ROOT_ERR_CMD_OFF,Root Error Command Register. For a description of this standard PCIe register. see the PCI Express Specification." hexmask.long 0x0 3.--31. 1. "RSVDP_3,Reserved for future use." bitfld.long 0x0 2. "FATAL_ERR_REPORTING_EN,Fatal Error Reporting Enable. For a description of this standard PCIe register field see the PCI Express Specification." "0,1" bitfld.long 0x0 1. "NON_FATAL_ERR_REPORTING_EN,Non-Fatal Error Reporting Enable. For a description of this standard PCIe register field see the PCI Express Specification." "0,1" newline bitfld.long 0x0 0. "CORR_ERR_REPORTING_EN,Correctable Error Reporting Enable. For a description of this standard PCIe register field see the PCI Express Specification." "0,1" line.long 0x4 "ROOT_ERR_STATUS_OFF,Root Error Status Register. For a description of this standard PCIe register. see the PCI Express Specification." hexmask.long.byte 0x4 27.--31. 1. "ADV_ERR_INT_MSG_NUM,Advanced Error Interrupt Message Number. For a description of this standard PCIe register field see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN.." hexmask.long.tbyte 0x4 7.--26. 1. "RSVDP_7,Reserved for future use." bitfld.long 0x4 6. "FATAL_ERR_MSG_RX,One or more Fatal Error Messages Received. For a description of this standard PCIe register field see the PCI Express Specification." "0,1" newline bitfld.long 0x4 5. "NON_FATAL_ERR_MSG_RX,One or more Non-Fatal Error Messages Received. For a description of this standard PCIe register field see the PCI Express Specification." "0,1" bitfld.long 0x4 4. "FIRST_UNCORR_FATAL,First Uncorrectable Error is Fatal. For a description of this standard PCIe register field see the PCI Express Specification." "0,1" bitfld.long 0x4 3. "MUL_ERR_FATAL_NON_FATAL_RX,Multiple Fatal or Non-Fatal Errors Received. For a description of this standard PCIe register field see the PCI Express Specification." "0,1" newline bitfld.long 0x4 2. "ERR_FATAL_NON_FATAL_RX,Fatal or Non-Fatal Error Received. For a description of this standard PCIe register field see the PCI Express Specification." "0,1" bitfld.long 0x4 1. "MUL_ERR_COR_RX,Multiple Correctable Errors Received. For a description of this standard PCIe register field see the PCI Express Specification." "0,1" bitfld.long 0x4 0. "ERR_COR_RX,Correctable Error Received. For a description of this standard PCIe register field see the PCI Express Specification." "0,1" rgroup.long (0x34+0x100)++0x13 line.long 0x0 "ERR_SRC_ID_OFF,Error Source Identification Register. For a description of this standard PCIe register. see the PCI Express Specification." hexmask.long.word 0x0 16.--31. 1. "ERR_FATAL_NON_FATAL_SOURCE_ID,Source of Fatal/Non-Fatal Error. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." hexmask.long.word 0x0 0.--15. 1. "ERR_COR_SOURCE_ID,Source of Correctable Error. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." line.long 0x4 "TLP_PREFIX_LOG_1_OFF,TLP Prefix Log Register 1. For a description of this standard PCIe register. see the PCI Express Specification." hexmask.long.byte 0x4 24.--31. 1. "CFG_TLP_PFX_LOG_1_FOURTH_BYTE,Byte 3 of Error TLP Prefix Log 1. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." hexmask.long.byte 0x4 16.--23. 1. "CFG_TLP_PFX_LOG_1_THIRD_BYTE,Byte 2 of Error TLP Prefix Log 1. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." hexmask.long.byte 0x4 8.--15. 1. "CFG_TLP_PFX_LOG_1_SECOND_BYTE,Byte 1 of Error TLP Prefix Log 1. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." newline hexmask.long.byte 0x4 0.--7. 1. "CFG_TLP_PFX_LOG_1_FIRST_BYTE,Byte 0 of Error TLP Prefix Log 1. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." line.long 0x8 "TLP_PREFIX_LOG_2_OFF,TLP Prefix Log Register 2. For a description of this standard PCIe register. see the PCI Express Specification." hexmask.long.byte 0x8 24.--31. 1. "CFG_TLP_PFX_LOG_2_FOURTH_BYTE,Byte 3 Error TLP Prefix Log 2. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." hexmask.long.byte 0x8 16.--23. 1. "CFG_TLP_PFX_LOG_2_THIRD_BYTE,Byte 2 Error TLP Prefix Log 2. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." hexmask.long.byte 0x8 8.--15. 1. "CFG_TLP_PFX_LOG_2_SECOND_BYTE,Byte 1 Error TLP Prefix Log 2. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." newline hexmask.long.byte 0x8 0.--7. 1. "CFG_TLP_PFX_LOG_2_FIRST_BYTE,Byte 0 Error TLP Prefix Log 2. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." line.long 0xC "TLP_PREFIX_LOG_3_OFF,TLP Prefix Log Register 3. For a description of this standard PCIe register. see the PCI Express Specification." hexmask.long.byte 0xC 24.--31. 1. "CFG_TLP_PFX_LOG_3_FOURTH_BYTE,Byte 3 Error TLP Prefix Log 3. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." hexmask.long.byte 0xC 16.--23. 1. "CFG_TLP_PFX_LOG_3_THIRD_BYTE,Byte 2 Error TLP Prefix Log 3. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." hexmask.long.byte 0xC 8.--15. 1. "CFG_TLP_PFX_LOG_3_SECOND_BYTE,Byte 1 Error TLP Prefix Log 3. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." newline hexmask.long.byte 0xC 0.--7. 1. "CFG_TLP_PFX_LOG_3_FIRST_BYTE,Byte 0 Error TLP Prefix Log 3. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." line.long 0x10 "TLP_PREFIX_LOG_4_OFF,TLP Prefix Log Register 4. For a description of this standard PCIe register. see the PCI Express Specification." hexmask.long.byte 0x10 24.--31. 1. "CFG_TLP_PFX_LOG_4_FOURTH_BYTE,Byte 3 Error TLP Prefix Log 4. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." hexmask.long.byte 0x10 16.--23. 1. "CFG_TLP_PFX_LOG_4_THIRD_BYTE,Byte 2 Error TLP Prefix Log 4. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." hexmask.long.byte 0x10 8.--15. 1. "CFG_TLP_PFX_LOG_4_SECOND_BYTE,Byte 1 Error TLP Prefix Log 4. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." newline hexmask.long.byte 0x10 0.--7. 1. "CFG_TLP_PFX_LOG_4_FIRST_BYTE,Byte 0 Error TLP Prefix Log 4. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." tree.end tree "PF0_MSI_CAP (PF MSI Capability Structure)" group.long (0x0+0x50)++0x13 line.long 0x0 "PCI_MSI_CAP_ID_NEXT_CTRL_REG,MSI Capability Header and Message Control Register." hexmask.long.byte 0x0 27.--31. 1. "RSVDP_27,Reserved for future use." bitfld.long 0x0 26. "PCI_MSI_EXT_DATA_EN,Extended Message Data Enable. - If set the function is enabled to provide Extended Message Data. - If clear the function is not enabled to provide Extended Message Data. Note: The access attributes of this field are as follows: -.." "0,1" bitfld.long 0x0 25. "PCI_MSI_EXT_DATA_CAP,Extended Message Data Capable. - If set the function is capable of providing Extended Message Data. - If clear the function does not support providing Extended Message Data. Note: The access attributes of this field are as follows:.." "0,1" newline rbitfld.long 0x0 24. "PCI_PVM_SUPPORT,Per-Vector Masking Capable. - If set the function supports MSI Per-Vector Masking. - If clear the function does not support MSI Per-Vector Masking. This bit must be set if the function is a PF or VF within an SR-IOV Device." "0,1" bitfld.long 0x0 23. "PCI_MSI_64_BIT_ADDR_CAP,64 bit address capable. - If set the function is capable of sending a 64-bit message address. - If clear the function is not capable of sending a 64-bit message address. This bit must be set if the function is a PCI Express.." "0,1" bitfld.long 0x0 20.--22. "PCI_MSI_MULTIPLE_MSG_EN,Multiple Message Enable. Software writes to this field to indicate the number of allocated vectors (equal to or less than the number of requested vectors). The number of allocated vectors is aligned to a power of two. If a.." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 17.--19. "PCI_MSI_MULTIPLE_MSG_CAP,Multiple Message Capable. System software reads this field to determine the number of requested vectors. The number of requested vectors must be aligned to a power of two (if a function requires three vectors it requests four by.." "0,1,2,3,4,5,6,7" bitfld.long 0x0 16. "PCI_MSI_ENABLE,MSI Enable. - If set and the MSI-X Enable bit in the MSI-X Message Control register is clear the function is permitted to use MSI to request service and is prohibited from using INTx interrupts. System configuration software sets this bit.." "0,1" hexmask.long.byte 0x0 8.--15. 1. "PCI_MSI_CAP_NEXT_OFFSET,Next Capability Pointer. This field contains the offset to the next PCI Capability structure or 00h if no other items exist in the linked list of Capabilities. Note: The access attributes of this field are as follows: - Wire: No.." newline hexmask.long.byte 0x0 0.--7. 1. "PCI_MSI_CAP_ID,Capability ID. Indicates the MSI Capability structure. This field returns a Capability ID of 05h indicating that this is an MSI Capability structure." line.long 0x4 "MSI_CAP_OFF_04H_REG,Message Address Register for MSI (Offset 04h)." hexmask.long 0x4 2.--31. 1. "PCI_MSI_CAP_OFF_04H,Message Address - System-specified message address. If the Message Enable bit (bit 16 of the PCI_MSI_CAP_ID_NEXT_CTRL_REG register) is set the contents of this field specify the DWORD-aligned address (Address[31:02]) for the MSI.." rbitfld.long 0x4 0.--1. "RSVDP_0,Reserved for future use." "0,1,2,3" line.long 0x8 "MSI_CAP_OFF_08H_REG,For a function that supports a 32-bit message address. - bits[31:16] of this register represent the Extended Message Data. and - bits[15:0] of this register represent the Message Data For a function that supports a 64-bit message.." hexmask.long.word 0x8 16.--31. 1. "PCI_MSI_CAP_OFF_0AH,For a function that supports a 32-bit message address this field contains Extended Message Data (System-specified message data). For the MSI Capability structures without per-vector masking it must be implemented if the Extended.." hexmask.long.word 0x8 0.--15. 1. "PCI_MSI_CAP_OFF_08H,For a function that supports a 32-bit message address this field contains Message Data (System-specified message data). If the Message Enable bit (bit 16 of the PCI_MSI_CAP_ID_NEXT_CTRL_REG) is set the function sends a DWORD Memory.." line.long 0xC "MSI_CAP_OFF_0CH_REG,For a function that supports a 32-bit message address. this register contains the Mask Bits when the Per-Vector Masking Capable bit (bit 24 of PCI_MSI_CAP_ID_NEXT_CTRL_REG) is set. For a function that supports a 64-bit message.." hexmask.long.word 0xC 16.--31. 1. "PCI_MSI_CAP_OFF_0EH,For a function that supports a 32-bit message address this field contains the upper Mask Bits when the Per Vector Masking Capable bit (PCI_MSI_CAP_ID_NEXT_CTRL_REG.PCI_PVM_SUPPORT) is set. For a function that supports a 64-bit.." hexmask.long.word 0xC 0.--15. 1. "PCI_MSI_CAP_OFF_0CH,For a function that supports a 32-bit message address this field contains the lower Mask Bits when the Per Vector Masking Capable bit (PCI_MSI_CAP_ID_NEXT_CTRL_REG.PCI_PVM_SUPPORT) is set. For a function that supports a 64-bit.." line.long 0x10 "MSI_CAP_OFF_10H_REG,For a function that supports a 32-bit message address. this register contains the Pending Bits when the Per-Vector Masking Capable bit (bit 24 of PCI_MSI_CAP_ID_NEXT_CTRL_REG) is set. For a function that supports a 64-bit message.." hexmask.long 0x10 0.--31. 1. "PCI_MSI_CAP_OFF_10H,Used for MSI when the Per Vector Masking Capable bit (PCI_MSI_CAP_ID_NEXT_CTRL_REG.PCI_PVM_SUPPORT) is set. For 32-bit contains Pending Bits. For 64-bit contains Mask Bits. For a description of this standard PCIe register field see.." rgroup.long (0x14+0x50)++0x3 line.long 0x0 "MSI_CAP_OFF_14H_REG,Pending Bits Register for MSI. This register is used for a function that supports a 64-bit message address when the Per-Vector Masking Capable bit (bit 24 of PCI_MSI_CAP_ID_NEXT_CTRL_REG) is set." hexmask.long 0x0 0.--31. 1. "PCI_MSI_CAP_OFF_14H,Pending Bits. For each pending bit that is set the function has a pending associated message." tree.end tree "PF0_MSIX_CAP (PF MSI-X Capability Structure)" group.long (0x0+0xB0)++0xB line.long 0x0 "PCI_MSIX_CAP_ID_NEXT_CTRL_REG,MSI-X Capability ID. Next Pointer. Control Registers. For a description of this standard PCIe register. see the PCI Express Base Specification." bitfld.long 0x0 31. "PCI_MSIX_ENABLE,MSI-X Enable. For a description of this standard PCIe register field see the PCI Express Base Specification." "0,1" bitfld.long 0x0 30. "PCI_MSIX_FUNCTION_MASK,Function Mask. For a description of this standard PCIe register field see the PCI Express Base Specification. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" "0,1" rbitfld.long 0x0 27.--29. "RSVDP_27,Reserved for future use." "0,1,2,3,4,5,6,7" newline hexmask.long.word 0x0 16.--26. 1. "PCI_MSIX_TABLE_SIZE,MSI-X Table Size. For a description of this standard PCIe register field see the PCI Express Base Specification. SRIOV Note: All VFs in a single PF have the same value for 'MSI-X Table Size' (PCI_MSIX_TABLE_SIZE field in.." hexmask.long.byte 0x0 8.--15. 1. "PCI_MSIX_CAP_NEXT_OFFSET,MSI-X Next Capability Pointer. For a description of this standard PCIe register field see the PCI Express Base Specification. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN.." hexmask.long.byte 0x0 0.--7. 1. "PCI_MSIX_CAP_ID,MSI-X Capability ID. For a description of this standard PCIe register field see the PCI Express Base Specification." line.long 0x4 "MSIX_TABLE_OFFSET_REG,MSI-X Table Offset and BIR Register. For a description of this standard PCIe register. see the PCI Express Base Specification." hexmask.long 0x4 3.--31. 1. "PCI_MSIX_TABLE_OFFSET,MSI-X Table Offset. For a description of this standard PCIe register field see the PCI Express Base Specification. SRIOV Note: All VFs in a single PF have the same value for 'MSI-X Table Offset' (PCI_MSIX_TABLE_OFFSET field in.." bitfld.long 0x4 0.--2. "PCI_MSIX_BIR,MSI-X Table BAR Indicator Register Field. For a description of this standard PCIe register field see the PCI Express Base Specification. SRIOV Note: All VFs in a single PF have the same value for 'MSI-X Table BAR Indicator Register'.." "0,1,2,3,4,5,6,7" line.long 0x8 "MSIX_PBA_OFFSET_REG,MSI-X PBA Offset and BIR Register. For a description of this standard PCIe register. see the PCI Express Base Specification." hexmask.long 0x8 3.--31. 1. "PCI_MSIX_PBA_OFFSET,MSI-X PBA Offset. For a description of this standard PCIe register field see the PCI Express Base Specification. SRIOV Note: All VFs in a single PF have the same value for 'MSI-X PBA Offset' (PCI_MSIX_PBA_OFFSET field in.." bitfld.long 0x8 0.--2. "PCI_MSIX_PBA_BIR,MSI-X PBA BIR. For a description of this standard PCIe register field see the PCI Express Base Specification. SRIOV Note: All VFs in a single PF have the same value for 'MSI-X PBA BIR' (PCI_MSIX_PBA_BIR field in.." "0,1,2,3,4,5,6,7" tree.end tree "PF0_MSIX_CAP_DBI2 (DBI2 Shadow Block: PF MSI-X Capability Structure)" rgroup.long (0x0+0x10B0)++0x3 line.long 0x0 "SHADOW_PCI_MSIX_CAP_ID_NEXT_CTRL_REG,MSI-X Capability ID. Next Pointer. Control Registers. For a description of this standard PCIe register. see the PCI Express Base Specification." hexmask.long.byte 0x0 27.--31. 1. "RSVDP_27,Reserved for future use." hexmask.long.word 0x0 16.--26. 1. "PCI_MSIX_TABLE_SIZE,MSI-X Table Size in the shadow register. Note: The access attributes of this field are as follows: - Wire: No access - Dbi: No access - Dbi2: if (DBI_RO_WR_EN == 1) then R/W else R Note: This register field is sticky." hexmask.long.word 0x0 0.--15. 1. "RSVDP_0,Reserved for future use." group.long 0x4++0x7 line.long 0x0 "SHADOW_MSIX_TABLE_OFFSET_REG,MSI-X Table Offset and BIR Register. For a description of this standard PCIe register. see the PCI Express Base Specification." hexmask.long 0x0 3.--31. 1. "PCI_MSIX_TABLE_OFFSET,MSI-X Table Offset. For a description of this standard PCIe register field see the PCI Express Base Specification. Note: The access attributes of this field are as follows: - Wire: No access - Dbi: No access - Dbi2: if.." bitfld.long 0x0 0.--2. "PCI_MSIX_BIR,MSI-X Table BAR Indicator Register Field. For a description of this standard PCIe register field see the PCI Express Base Specification. Note: The access attributes of this field are as follows: - Wire: No access - Dbi: No access - Dbi2: if.." "?,?,if,?,?,?,?,?" line.long 0x4 "SHADOW_MSIX_PBA_OFFSET_REG,MSI-X PBA Offset and BIR Register. For a description of this standard PCIe register. see the PCI Express Base Specification." hexmask.long 0x4 3.--31. 1. "PCI_MSIX_PBA_OFFSET,MSI-X PBA Offset. For a description of this standard PCIe register field see the PCI Express Base Specification. Note: The access attributes of this field are as follows: - Wire: No access - Dbi: No access - Dbi2: if (DBI_RO_WR_EN ==.." bitfld.long 0x4 0.--2. "PCI_MSIX_PBA_BIR,MSI-X PBA BIR. For a description of this standard PCIe register field see the PCI Express Base Specification. Note: The access attributes of this field are as follows: - Wire: No access - Dbi: No access - Dbi2: if (DBI_RO_WR_EN == 1 &&.." "?,?,if,?,?,?,?,?" tree.end tree "PF0_DMA_CAP (DMA Port Logic Structure)" group.long (0x0+0xC8000)++0x3 line.long 0x0 "DMA_CTRL_DATA_ARB_PRIOR_OFF,DMA Arbitration Scheme for TRGT1 Interface. This register is used to control traffic priorities among various sources that are delivered to your application through TRGT1 where 0x0 represents the highest priority. - Non-DMA Rx.." hexmask.long.tbyte 0x0 12.--31. 1. "RSVDP_12,Reserved for future use." bitfld.long 0x0 9.--11. "RDBUFF_TRGT_WEIGHT,DMA Read Channel MWr Requests. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 6.--8. "RD_CTRL_TRGT_WEIGHT,DMA Read Channel MRd Requests. For LL element/descriptor access. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" "0,1,2,3,4,5,6,7" bitfld.long 0x0 3.--5. "WR_CTRL_TRGT_WEIGHT,DMA Write Channel MRd Requests. For DMA data requests and LL element/descriptor access. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 0.--2. "RTRGT1_WEIGHT,Non-DMA Rx Requests. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" "0,1,2,3,4,5,6,7" group.long (0x8+0xC8000)++0xB line.long 0x0 "DMA_CTRL_OFF,DMA Number of Channels Register." hexmask.long.byte 0x0 26.--31. 1. "RSVDP_26,Reserved for future use." bitfld.long 0x0 25. "DIS_C2W_CACHE_RD,Disable DMA Read Channels 'completion to memory write' context cache pre-fetch function. Note: For internal debugging only. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" "0,1" newline bitfld.long 0x0 24. "DIS_C2W_CACHE_WR,Disable DMA Write Channels 'completion to memory write' context cache pre-fetch function. Note: For internal debugging only. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" "0,1" hexmask.long.byte 0x0 20.--23. 1. "RSVDP_20,Reserved for future use." newline hexmask.long.byte 0x0 16.--19. 1. "NUM_DMA_RD_CHAN,Number of Read Channels. You can read this register to determine the number of read channels the DMA controller has been configured to support." hexmask.long.word 0x0 4.--15. 1. "RSVDP_4,Reserved for future use." newline hexmask.long.byte 0x0 0.--3. 1. "NUM_DMA_WR_CHAN,Number of Write Channels. You can read this register to determine the number of write channels the DMA controller has been configured to support." line.long 0x4 "DMA_WRITE_ENGINE_EN_OFF,DMA Write Engine Enable Register." hexmask.long.byte 0x4 24.--31. 1. "RSVDP_24,Reserved for future use." bitfld.long 0x4 23. "DMA_WRITE_ENGINE_EN_HSHAKE_CH7,Enable Handshake for DMA Write Engine Channel 7. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" "0,1" newline bitfld.long 0x4 22. "DMA_WRITE_ENGINE_EN_HSHAKE_CH6,Enable Handshake for DMA Write Engine Channel 6. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" "0,1" bitfld.long 0x4 21. "DMA_WRITE_ENGINE_EN_HSHAKE_CH5,Enable Handshake for DMA Write Engine Channel 5. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" "0,1" newline bitfld.long 0x4 20. "DMA_WRITE_ENGINE_EN_HSHAKE_CH4,Enable Handshake for DMA Write Engine Channel 4. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" "0,1" bitfld.long 0x4 19. "DMA_WRITE_ENGINE_EN_HSHAKE_CH3,Enable Handshake for DMA Write Engine Channel 3. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" "0,1" newline bitfld.long 0x4 18. "DMA_WRITE_ENGINE_EN_HSHAKE_CH2,Enable Handshake for DMA Write Engine Channel 2. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" "0,1" bitfld.long 0x4 17. "DMA_WRITE_ENGINE_EN_HSHAKE_CH1,Enable Handshake for DMA Write Engine Channel 1. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" "0,1" newline bitfld.long 0x4 16. "DMA_WRITE_ENGINE_EN_HSHAKE_CH0,Enable Handshake for DMA Write Engine Channel 0. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" "0,1" hexmask.long.word 0x4 1.--15. 1. "RSVDP_1,Reserved for future use." newline bitfld.long 0x4 0. "DMA_WRITE_ENGINE,DMA Write Engine Enable. - 1: Enable - 0: Disable (Soft Reset) For normal operation you must initially set this bit to '1' before any other software setup actions. You do not need to toggle or rewrite to this bit during normal.." "Disable,Enable" line.long 0x8 "DMA_WRITE_DOORBELL_OFF,DMA Write Doorbell Register." bitfld.long 0x8 31. "WR_STOP,Stop. Set in conjunction with the Doorbell Number field. The DMA write channel stops issuing requests sets the channel status to 'Stopped' and asserts the 'Abort' interrupt if it is enabled. Before setting the Stop bit you must read the.." "0,1" hexmask.long 0x8 3.--30. 1. "RSVDP_3,Reserved for future use." newline bitfld.long 0x8 0.--2. "WR_DOORBELL_NUM,Doorbell Number. You must write the channel number to this register to start the DMA write transfer for that channel. The DMA detects a write to this register field even if the value of this field does not change. You do not need to.." "0,1,2,3,4,5,6,7" group.long (0x18+0xC8000)++0x7 line.long 0x0 "DMA_WRITE_CHANNEL_ARB_WEIGHT_LOW_OFF,DMA Write Engine Channel Arbitration Weight Low Register. The 5-bit channel weight (for write channels 0-3) specifies the maximum number of TLP requests that the DMA can issue for that channel before it must return to.." hexmask.long.word 0x0 20.--31. 1. "RSVDP_20,Reserved for future use." hexmask.long.byte 0x0 15.--19. 1. "WRITE_CHANNEL3_WEIGHT,Channel 3 Weight. The weight is initialized by software before ringing the doorbell. The value is used by the channel weighted round robin arbiter to select the next channel read request. A value of '0' means that one TLP is issued.." newline hexmask.long.byte 0x0 10.--14. 1. "WRITE_CHANNEL2_WEIGHT,Channel 2 Weight. The weight is initialized by software before ringing the doorbell. The value is used by the channel weighted round robin arbiter to select the next channel read request. A value of '0' means that one TLP is issued.." hexmask.long.byte 0x0 5.--9. 1. "WRITE_CHANNEL1_WEIGHT,Channel 1 Weight. The weight is initialized by software before ringing the doorbell. The value is used by the channel weighted round robin arbiter to select the next channel read request. A value of '0' means that one TLP is issued.." newline hexmask.long.byte 0x0 0.--4. 1. "WRITE_CHANNEL0_WEIGHT,Channel 0 Weight. The weight is initialized by software before ringing the doorbell. The value is used by the channel weighted round robin arbiter to select the next channel read request. A value of '0' means that one TLP is issued.." line.long 0x4 "DMA_WRITE_CHANNEL_ARB_WEIGHT_HIGH_OFF,DMA Write Engine Channel Arbitration Weight High Register. The 5-bit channel weight (for write channels 4-7) specifies the maximum number of TLP requests that the DMA can issue for that channel before it must return.." hexmask.long.word 0x4 20.--31. 1. "RSVDP_20,Reserved for future use." hexmask.long.byte 0x4 15.--19. 1. "WRITE_CHANNEL7_WEIGHT,Channel 7 Weight. The weight is initialized by software before ringing the doorbell. The value is used by the channel weighted round robin arbiter to select the next channel read request. A value of '0' means that one TLP is issued.." newline hexmask.long.byte 0x4 10.--14. 1. "WRITE_CHANNEL6_WEIGHT,Channel 6 Weight. The weight is initialized by software before ringing the doorbell. The value is used by the channel weighted round robin arbiter to select the next channel read request. A value of '0' means that one TLP is issued.." hexmask.long.byte 0x4 5.--9. 1. "WRITE_CHANNEL5_WEIGHT,Channel 5 Weight. The weight is initialized by software before ringing the doorbell. The value is used by the channel weighted round robin arbiter to select the next channel read request. A value of '0' means that one TLP is issued.." newline hexmask.long.byte 0x4 0.--4. 1. "WRITE_CHANNEL4_WEIGHT,Channel 4 Weight. The weight is initialized by software before ringing the doorbell. The value is used by the channel weighted round robin arbiter to select the next channel read request. A value of '0' means that one TLP is issued.." group.long (0x2C+0xC8000)++0x7 line.long 0x0 "DMA_READ_ENGINE_EN_OFF,DMA Read Engine Enable Register." hexmask.long.byte 0x0 24.--31. 1. "RSVDP_24,Reserved for future use." bitfld.long 0x0 23. "DMA_READ_ENGINE_EN_HSHAKE_CH7,Enable Handshake for DMA Read Engine Channel 7. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" "0,1" newline bitfld.long 0x0 22. "DMA_READ_ENGINE_EN_HSHAKE_CH6,Enable Handshake for DMA Read Engine Channel 6. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" "0,1" bitfld.long 0x0 21. "DMA_READ_ENGINE_EN_HSHAKE_CH5,Enable Handshake for DMA Read Engine Channel 5. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" "0,1" newline bitfld.long 0x0 20. "DMA_READ_ENGINE_EN_HSHAKE_CH4,Enable Handshake for DMA Read Engine Channel 4. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" "0,1" bitfld.long 0x0 19. "DMA_READ_ENGINE_EN_HSHAKE_CH3,Enable Handshake for DMA Read Engine Channel 3. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" "0,1" newline bitfld.long 0x0 18. "DMA_READ_ENGINE_EN_HSHAKE_CH2,Enable Handshake for DMA Read Engine Channel 2. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" "0,1" bitfld.long 0x0 17. "DMA_READ_ENGINE_EN_HSHAKE_CH1,Enable Handshake for DMA Read Engine Channel 1. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" "0,1" newline bitfld.long 0x0 16. "DMA_READ_ENGINE_EN_HSHAKE_CH0,Enable Handshake for DMA Read Engine Channel 0. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" "0,1" hexmask.long.word 0x0 1.--15. 1. "RSVDP_1,Reserved for future use." newline bitfld.long 0x0 0. "DMA_READ_ENGINE,DMA Read Engine Enable. - 1: Enable - 0: Disable (Soft Reset) For normal operation you must initially set this bit to '1' before any other software setup actions. You do not need to toggle or rewrite to this bit during normal operation." "Disable,Enable" line.long 0x4 "DMA_READ_DOORBELL_OFF,DMA Read Doorbell Register." bitfld.long 0x4 31. "RD_STOP,Stop. Set in conjunction with the Doorbell Number field. The DMA read channel stops issuing requests sets the channel status to 'Stopped' and asserts the 'Abort' interrupt if it is enabled. Before setting the Stop bit you must read the channel.." "0,1" hexmask.long 0x4 3.--30. 1. "RSVDP_3,Reserved for future use." newline bitfld.long 0x4 0.--2. "RD_DOORBELL_NUM,Doorbell Number. You must write 0x0 to this register to start the DMA read transfer for that channel. The DMA detects a write to this register field even if the value of this field does not change. The range of this field is 0x0 to 0x7.." "0,1,2,3,4,5,6,7" group.long (0x38+0xC8000)++0x7 line.long 0x0 "DMA_READ_CHANNEL_ARB_WEIGHT_LOW_OFF,DMA Read Engine Channel Arbitration Weight Low Register. The 5-bit channel weight (for read channels 0-3) specifies the maximum number of TLP requests that the DMA can issue for that channel before it must return to.." hexmask.long.word 0x0 20.--31. 1. "RSVDP_20,Reserved for future use." hexmask.long.byte 0x0 15.--19. 1. "READ_CHANNEL3_WEIGHT,Channel 3 Weight. The weight is initialized by software before ringing the doorbell. The value is used by the channel weighted round robin arbiter to select the next channel read request. Note: The access attributes of this field are.." newline hexmask.long.byte 0x0 10.--14. 1. "READ_CHANNEL2_WEIGHT,Channel 2 Weight. The weight is initialized by software before ringing the doorbell. The value is used by the channel weighted round robin arbiter to select the next channel read request. Note: The access attributes of this field are.." hexmask.long.byte 0x0 5.--9. 1. "READ_CHANNEL1_WEIGHT,Channel 1 Weight. The weight is initialized by software before ringing the doorbell. The value is used by the channel weighted round robin arbiter to select the next channel read request. Note: The access attributes of this field are.." newline hexmask.long.byte 0x0 0.--4. 1. "READ_CHANNEL0_WEIGHT,Channel 0 Weight. The weight is initialized by software before ringing the doorbell. The value is used by the channel weighted round robin arbiter to select the next channel read request. Note: The access attributes of this field are.." line.long 0x4 "DMA_READ_CHANNEL_ARB_WEIGHT_HIGH_OFF,DMA Read Engine Channel Arbitration Weight High Register. The 5-bit channel weight (for read channels 4-7) specifies the maximum number of TLP requests that the DMA can issue for that channel before it must return to.." hexmask.long.word 0x4 20.--31. 1. "RSVDP_20,Reserved for future use." hexmask.long.byte 0x4 15.--19. 1. "READ_CHANNEL7_WEIGHT,Channel 7 Weight. The weight is initialized by software before ringing the doorbell. The value is used by the channel weighted round robin arbiter to select the next channel read request. Note: The access attributes of this field are.." newline hexmask.long.byte 0x4 10.--14. 1. "READ_CHANNEL6_WEIGHT,Channel 6 Weight. The weight is initialized by software before ringing the doorbell. The value is used by the channel weighted round robin arbiter to select the next channel read request. Note: The access attributes of this field are.." hexmask.long.byte 0x4 5.--9. 1. "READ_CHANNEL5_WEIGHT,Channel 5 Weight. The weight is initialized by software before ringing the doorbell. The value is used by the channel weighted round robin arbiter to select the next channel read request. Note: The access attributes of this field are.." newline hexmask.long.byte 0x4 0.--4. 1. "READ_CHANNEL4_WEIGHT,Channel 4 Weight. The weight is initialized by software before ringing the doorbell. The value is used by the channel weighted round robin arbiter to select the next channel read request. Note: The access attributes of this field are.." group.long (0x4C+0xC8000)++0x3 line.long 0x0 "DMA_WRITE_INT_STATUS_OFF,DMA Write Interrupt Status Register." hexmask.long.byte 0x0 24.--31. 1. "RSVDP_24,Reserved for future use." hexmask.long.byte 0x0 16.--23. 1. "WR_ABORT_INT_STATUS,Abort Interrupt Status. The DMA write channel has detected an error or you manually stopped the transfer as described in 'Error Handling Assistance by Remote Software'. Each bit corresponds to a DMA channel. Bit [0] corresponds to.." newline hexmask.long.byte 0x0 8.--15. 1. "RSVDP_8,Reserved for future use." hexmask.long.byte 0x0 0.--7. 1. "WR_DONE_INT_STATUS,Done Interrupt Status. The DMA write channel has successfully completed the DMA transfer. For more details see 'Interrupts and Error Handling'. Each bit corresponds to a DMA channel. Bit [0] corresponds to channel 0. - Enabling: For.." group.long (0x54+0xC8000)++0x7 line.long 0x0 "DMA_WRITE_INT_MASK_OFF,DMA Write Interrupt Mask Register." hexmask.long.byte 0x0 24.--31. 1. "RSVDP_24,Reserved for future use." hexmask.long.byte 0x0 16.--23. 1. "WR_ABORT_INT_MASK,Abort Interrupt Mask. Prevents the Abort interrupt status field in the DMA write interrupt status register from asserting the edma_int output. Each bit corresponds to a DMA channel. Bit [0] corresponds to channel 0. Note: The access.." newline hexmask.long.byte 0x0 8.--15. 1. "RSVDP_8,Reserved for future use." hexmask.long.byte 0x0 0.--7. 1. "WR_DONE_INT_MASK,Done Interrupt Mask. Prevents the Done interrupt status field in the DMA write interrupt status register from asserting the edma_int output. Each bit corresponds to a DMA channel. Bit [0] corresponds to channel 0. Note: The access.." line.long 0x4 "DMA_WRITE_INT_CLEAR_OFF,DMA Write Interrupt Clear Register." hexmask.long.byte 0x4 24.--31. 1. "RSVDP_24,Reserved for future use." hexmask.long.byte 0x4 16.--23. 1. "WR_ABORT_INT_CLEAR,Abort Interrupt Clear. You must write a 1'b1 to clear the corresponding bit in the Abort interrupt status field of the DMA write interrupt status register. Each bit corresponds to a DMA channel. Bit [0] corresponds to channel 0. Note:.." newline hexmask.long.byte 0x4 8.--15. 1. "RSVDP_8,Reserved for future use." hexmask.long.byte 0x4 0.--7. 1. "WR_DONE_INT_CLEAR,Done Interrupt Clear. You must write a 1'b1 to clear the corresponding bit in the Done interrupt status field of the DMA write interrupt status register. Each bit corresponds to a DMA channel. Bit [0] corresponds to channel 0. Note:.." rgroup.long (0x5C+0xC8000)++0x3 line.long 0x0 "DMA_WRITE_ERR_STATUS_OFF,DMA Write Error Status Register" hexmask.long.byte 0x0 24.--31. 1. "RSVDP_24,Reserved for future use." hexmask.long.byte 0x0 16.--23. 1. "LINKLIST_ELEMENT_FETCH_ERR_DETECT,Linked List Element Fetch Error Detected. The DMA write channel has received an error response from the AXI bus (or TRGT1 interface when the AXI Bridge is not used) while reading a linked list element from local memory." newline hexmask.long.byte 0x0 8.--15. 1. "RSVDP_8,Reserved for future use." hexmask.long.byte 0x0 0.--7. 1. "APP_READ_ERR_DETECT,Application Read Error Detected. The DMA write channel has received an error response from the AXI bus (or TRGT1 interface when the AXI Bridge is not used) while reading data from it. Each bit corresponds to a DMA channel. Bit [0].." group.long (0x60+0xC8000)++0x1F line.long 0x0 "DMA_WRITE_DONE_IMWR_LOW_OFF,DMA Write Done IMWr Address Low Register." hexmask.long 0x0 0.--31. 1. "DMA_WRITE_DONE_LOW_REG,The DMA uses this field to generate bits [31:0] of the address field for the Done IMWr TLP. Bits [1:0] must be '00' as this address must be dword aligned. Note: The access attributes of this field are as follows: - Wire: No access." line.long 0x4 "DMA_WRITE_DONE_IMWR_HIGH_OFF,DMA Write Done IMWr Interrupt Address High Register." hexmask.long 0x4 0.--31. 1. "DMA_WRITE_DONE_HIGH_REG,The DMA uses this field to generate bits [63:32] of the address field for the Done IMWr TLP. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" line.long 0x8 "DMA_WRITE_ABORT_IMWR_LOW_OFF,DMA Write Abort IMWr Address Low Register." hexmask.long 0x8 0.--31. 1. "DMA_WRITE_ABORT_LOW_REG,The DMA uses this field to generate bits [31:0] of the address field for the Abort IMWr TLP it generates. Bits [1:0] must be '00' as this address must be dword aligned. Note: The access attributes of this field are as follows: -.." line.long 0xC "DMA_WRITE_ABORT_IMWR_HIGH_OFF,DMA Write Abort IMWr Address High Register." hexmask.long 0xC 0.--31. 1. "DMA_WRITE_ABORT_HIGH_REG,The DMA uses this field to generate bits [63:32] of the address field for the Abort IMWr TLP. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" line.long 0x10 "DMA_WRITE_CH01_IMWR_DATA_OFF,DMA Write Channel 1 and 0 IMWr Data Register." hexmask.long.word 0x10 16.--31. 1. "WR_CHANNEL_1_DATA,The DMA uses this field to generate the data field for the Done or Abort IMWr TLPs it generates for write channel 1. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" hexmask.long.word 0x10 0.--15. 1. "WR_CHANNEL_0_DATA,The DMA uses this field to generate the data field for the Done or Abort IMWr TLPs it generates for write channel 0. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" line.long 0x14 "DMA_WRITE_CH23_IMWR_DATA_OFF,DMA Write Channel 3 and 2 IMWr Data Register." hexmask.long.word 0x14 16.--31. 1. "WR_CHANNEL_3_DATA,The DMA uses this field to generate the data field for the Done or Abort IMWr TLPs it generates for write channel 3. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" hexmask.long.word 0x14 0.--15. 1. "WR_CHANNEL_2_DATA,The DMA uses this field to generate the data field for the Done or Abort IMWr TLPs it generates for write channel 2. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" line.long 0x18 "DMA_WRITE_CH45_IMWR_DATA_OFF,DMA Write Channel 5 and 4 IMWr Data Register." hexmask.long.word 0x18 16.--31. 1. "WR_CHANNEL_5_DATA,The DMA uses this field to generate the data field for the Done or Abort IMWr TLPs it generates for write channel 5. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" hexmask.long.word 0x18 0.--15. 1. "WR_CHANNEL_4_DATA,The DMA uses this field to generate the data field for the Done or Abort IMWr TLPs it generates for write channel 4. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" line.long 0x1C "DMA_WRITE_CH67_IMWR_DATA_OFF,DMA Write Channel 7 and 6 IMWr Data Register." hexmask.long.word 0x1C 16.--31. 1. "WR_CHANNEL_7_DATA,The DMA uses this field to generate the data field for the Done or Abort IMWr TLPs it generates for write channel 7. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" hexmask.long.word 0x1C 0.--15. 1. "WR_CHANNEL_6_DATA,The DMA uses this field to generate the data field for the Done or Abort IMWr TLPs it generates for write channel 6. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" group.long (0x90+0xC8000)++0x3 line.long 0x0 "DMA_WRITE_LINKED_LIST_ERR_EN_OFF,DMA Write Linked List Error Enable Register. The LIE and RIE bits in the LL element enable the channel 'done' interrupts (local and remote). The LLLAIE and LLRAIE bits enable the channel 'abort' interrupts (local and.." hexmask.long.byte 0x0 24.--31. 1. "RSVDP_24,Reserved for future use." hexmask.long.byte 0x0 16.--23. 1. "WR_CHANNEL_LLLAIE,Write Channel LL Local Abort Interrupt Enable (LLLAIE). You enable the write channel local abort interrupt through this bit. The LIE and RIE bits in the LL element enable the write channel done interrupts. Each bit corresponds to a DMA.." newline hexmask.long.byte 0x0 8.--15. 1. "RSVDP_8,Reserved for future use." hexmask.long.byte 0x0 0.--7. 1. "WR_CHANNEL_LLRAIE,Write Channel LL Remote Abort Interrupt Enable (LLRAIE). You enable the write channel remote abort interrupt through this bit. The LIE and RIE bits in the LL element enable the write channel done interrupts. Each bit corresponds to a.." group.long (0xA0+0xC8000)++0x3 line.long 0x0 "DMA_READ_INT_STATUS_OFF,DMA Read Interrupt Status Register." hexmask.long.byte 0x0 24.--31. 1. "RSVDP_24,Reserved for future use." hexmask.long.byte 0x0 16.--23. 1. "RD_ABORT_INT_STATUS,Abort Interrupt Status. The DMA read channel has detected an error or you manually stopped the transfer as described in 'Stopping the DMA Transfer (Software Stop)'. Each bit corresponds to a DMA channel. Bit [0] corresponds to.." newline hexmask.long.byte 0x0 8.--15. 1. "RSVDP_8,Reserved for future use." hexmask.long.byte 0x0 0.--7. 1. "RD_DONE_INT_STATUS,Done Interrupt Status. The DMA read channel has successfully completed the DMA read transfer. Each bit corresponds to a DMA channel. Bit [0] corresponds to channel 0. - Enabling: For details see 'Interrupts and Error Handling'. -.." group.long (0xA8+0xC8000)++0x7 line.long 0x0 "DMA_READ_INT_MASK_OFF,DMA Read Interrupt Mask Register." hexmask.long.byte 0x0 24.--31. 1. "RSVDP_24,Reserved for future use." hexmask.long.byte 0x0 16.--23. 1. "RD_ABORT_INT_MASK,Abort Interrupt Mask. Prevents the Abort interrupt status field in the DMA read interrupt status register from asserting the edma_int output. Each bit corresponds to a DMA channel. Bit [0] corresponds to channel 0. Note: The access.." newline hexmask.long.byte 0x0 8.--15. 1. "RSVDP_8,Reserved for future use." hexmask.long.byte 0x0 0.--7. 1. "RD_DONE_INT_MASK,Done Interrupt Mask. Prevents the Done interrupt status field in the DMA read interrupt status register from asserting the edma_int output. Each bit corresponds to a DMA channel. Bit [0] corresponds to channel 0. Note: The access.." line.long 0x4 "DMA_READ_INT_CLEAR_OFF,DMA Read Interrupt Clear Register." hexmask.long.byte 0x4 24.--31. 1. "RSVDP_24,Reserved for future use." hexmask.long.byte 0x4 16.--23. 1. "RD_ABORT_INT_CLEAR,Abort Interrupt Clear. You must write a 1'b1 to clear the corresponding bit in the Abort interrupt status field of the DMA read interrupt status register. Each bit corresponds to a DMA channel. Bit [0] corresponds to channel 0. Note:.." newline hexmask.long.byte 0x4 8.--15. 1. "RSVDP_8,Reserved for future use." hexmask.long.byte 0x4 0.--7. 1. "RD_DONE_INT_CLEAR,Done Interrupt Clear. You must write a 1'b1 to clear the corresponding bit in the Done interrupt status field of the DMA read interrupt status register. Each bit corresponds to a DMA channel. Bit [0] corresponds to channel 0. Note:.." rgroup.long (0xB4+0xC8000)++0x7 line.long 0x0 "DMA_READ_ERR_STATUS_LOW_OFF,DMA Read Error Status Low Register." hexmask.long.byte 0x0 24.--31. 1. "RSVDP_24,Reserved for future use." hexmask.long.byte 0x0 16.--23. 1. "LINK_LIST_ELEMENT_FETCH_ERR_DETECT,Linked List Element Fetch Error Detected. - The DMA read channel has received an error response from the AXI bus while reading a linked list element from local memory. Each bit corresponds to a DMA channel. Bit [0].." newline hexmask.long.byte 0x0 8.--15. 1. "RSVDP_8,Reserved for future use." hexmask.long.byte 0x0 0.--7. 1. "APP_WR_ERR_DETECT,Application Write Error Detected. The DMA read channel has received an error response from the AXI bus (or TRGT1 interface when the AXI Bridge is not used) while writing data to it. This error is fatal. You must restart the transfer.." line.long 0x4 "DMA_READ_ERR_STATUS_HIGH_OFF,DMA Read Error Status High Register." hexmask.long.byte 0x4 24.--31. 1. "DATA_POISIONING,Data Poisoning. The DMA read channel has detected data poisoning in the completion from the remote device (in response to the MRd request). The DMA read channel will drop the completion and then be halted. The CX_FLT_MASK_UR_POIS filter.." hexmask.long.byte 0x4 16.--23. 1. "CPL_TIMEOUT,Completion Time Out. The DMA read channel has timed-out while waiting for the remote device to respond to the MRd request or a malformed CplD has been received. For more details see 'Linked List Mode'. Each bit corresponds to a DMA channel." newline hexmask.long.byte 0x4 8.--15. 1. "CPL_ABORT,Completer Abort. The DMA read channel has received a PCIe completer abort completion status from the remote device in response to the MRd request. For more details see 'Linked List Mode'. Each bit corresponds to a DMA channel. Bit [0].." hexmask.long.byte 0x4 0.--7. 1. "UNSUPPORTED_REQ,Unsupported Request. The DMA read channel has received a PCIe unsupported request completion status from the remote device in response to the MRd request. For more details see 'Linked List Mode'. Each bit corresponds to a DMA channel." group.long (0xC4+0xC8000)++0x3 line.long 0x0 "DMA_READ_LINKED_LIST_ERR_EN_OFF,DMA Read Linked List Error Enable Register. The LIE and RIE bits in the LL element enable the channel 'done' interrupts (local and remote). The LLLAIE and LLRAIE bits enable the channel 'abort' interrupts (local and remote)." hexmask.long.byte 0x0 24.--31. 1. "RSVDP_24,Reserved for future use." hexmask.long.byte 0x0 16.--23. 1. "RD_CHANNEL_LLLAIE,Read Channel LL Local Abort Interrupt Enable (LLLAIE). You enable the read channel Local Abort interrupt through this bit. The LIE and RIE bits in the LL element enable the read channel done interrupts. Each bit corresponds to a DMA.." newline hexmask.long.byte 0x0 8.--15. 1. "RSVDP_8,Reserved for future use." hexmask.long.byte 0x0 0.--7. 1. "RD_CHANNEL_LLRAIE,Read Channel LL Remote Abort Interrupt Enable (LLRAIE). You enable the read channel Remote Abort interrupt through this bit. The LIE and RIE bits in the LL element enable the read channel done interrupts. Each bit corresponds to a DMA.." group.long (0xCC+0xC8000)++0x1F line.long 0x0 "DMA_READ_DONE_IMWR_LOW_OFF,DMA Read Done IMWr Address Low Register." hexmask.long 0x0 0.--31. 1. "DMA_READ_DONE_LOW_REG,The DMA uses this field to generate bits [31:0] of the address field for the Done IMWr TLP. Bits [1:0] must be '00' as this address must be dword aligned. Note: The access attributes of this field are as follows: - Wire: No access." line.long 0x4 "DMA_READ_DONE_IMWR_HIGH_OFF,DMA Read Done IMWr Address High Register." hexmask.long 0x4 0.--31. 1. "DMA_READ_DONE_HIGH_REG,The DMA uses this field to generate bits [63:32] of the address field for the Done IMWr TLP. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" line.long 0x8 "DMA_READ_ABORT_IMWR_LOW_OFF,DMA Read Abort IMWr Address Low Register." hexmask.long 0x8 0.--31. 1. "DMA_READ_ABORT_LOW_REG,The DMA uses this field to generate bits [31:0] of the address field for the Abort IMWr TLP. Bits [1:0] must be '00' as this address must be dword aligned. Note: The access attributes of this field are as follows: - Wire: No.." line.long 0xC "DMA_READ_ABORT_IMWR_HIGH_OFF,DMA Read Abort IMWr Address High Register." hexmask.long 0xC 0.--31. 1. "DMA_READ_ABORT_HIGH_REG,The DMA uses this field to generate bits [63:32] of the address field for the Abort IMWr TLP. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" line.long 0x10 "DMA_READ_CH01_IMWR_DATA_OFF,DMA Read Channel 1 and 0 IMWr Data Register." hexmask.long.word 0x10 16.--31. 1. "RD_CHANNEL_1_DATA,The DMA uses this field to generate the data field for the Done or Abort IMWr TLPs it generates for read channel 1. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" hexmask.long.word 0x10 0.--15. 1. "RD_CHANNEL_0_DATA,The DMA uses this field to generate the data field for the Done or Abort IMWr TLPs it generates for read channel 0. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" line.long 0x14 "DMA_READ_CH23_IMWR_DATA_OFF,DMA Read Channel 3 and 2 IMWr Data Register." hexmask.long.word 0x14 16.--31. 1. "RD_CHANNEL_3_DATA,The DMA uses this field to generate the data field for the Done or Abort IMWr TLPs it generates for read channel 3. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" hexmask.long.word 0x14 0.--15. 1. "RD_CHANNEL_2_DATA,The DMA uses this field to generate the data field for the Done or Abort IMWr TLPs it generates for read channel 2. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" line.long 0x18 "DMA_READ_CH45_IMWR_DATA_OFF,DMA Read Channel 5 and 4 IMWr Data Register." hexmask.long.word 0x18 16.--31. 1. "RD_CHANNEL_5_DATA,The DMA uses this field to generate the data field for the Done or Abort IMWr TLPs it generates for read channel 5. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" hexmask.long.word 0x18 0.--15. 1. "RD_CHANNEL_4_DATA,The DMA uses this field to generate the data field for the Done or Abort IMWr TLPs it generates for read channel 4. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" line.long 0x1C "DMA_READ_CH67_IMWR_DATA_OFF,DMA Read Channel 7 and 6 IMWr Data Register." hexmask.long.word 0x1C 16.--31. 1. "RD_CHANNEL_7_DATA,The DMA uses this field to generate the data field for the Done or Abort IMWr TLPs it generates for read channel 7. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" hexmask.long.word 0x1C 0.--15. 1. "RD_CHANNEL_6_DATA,The DMA uses this field to generate the data field for the Done or Abort IMWr TLPs it generates for read channel 6. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" rgroup.long (0x108+0xC8000)++0x7 line.long 0x0 "DMA_WRITE_ENGINE_HSHAKE_CNT_LOW_OFF,DMA Write Engine Handshake Counter Channel 0/1/2/3 Register." bitfld.long 0x0 29.--31. "RSVDP_29,Reserved for future use." "0,1,2,3,4,5,6,7" hexmask.long.byte 0x0 24.--28. 1. "DMA_WRITE_ENGINE_HSHAKE_CNT_CH3,DMA handshake counter for DMA Write Engine Channel 3. If CC_DMA_HSHAKE =1 the data transfer in Linked List mode starts only when the counter is non-zero." newline bitfld.long 0x0 21.--23. "RSVDP_21,Reserved for future use." "0,1,2,3,4,5,6,7" hexmask.long.byte 0x0 16.--20. 1. "DMA_WRITE_ENGINE_HSHAKE_CNT_CH2,DMA handshake counter for DMA Write Engine Channel 2. If CC_DMA_HSHAKE =1 the data transfer in Linked List mode starts only when the counter is non-zero." newline bitfld.long 0x0 13.--15. "RSVDP_13,Reserved for future use." "0,1,2,3,4,5,6,7" hexmask.long.byte 0x0 8.--12. 1. "DMA_WRITE_ENGINE_HSHAKE_CNT_CH1,DMA handshake counter for DMA Write Engine Channel 1. If CC_DMA_HSHAKE =1 the data transfer in Linked List mode starts only when the counter is non-zero." newline bitfld.long 0x0 5.--7. "RSVDP_5,Reserved for future use." "0,1,2,3,4,5,6,7" hexmask.long.byte 0x0 0.--4. 1. "DMA_WRITE_ENGINE_HSHAKE_CNT_CH0,DMA handshake counter for DMA Write Engine Channel 0. If CC_DMA_HSHAKE =1 the data transfer in Linked List mode starts only when the counter is non-zero." line.long 0x4 "DMA_WRITE_ENGINE_HSHAKE_CNT_HIGH_OFF,DMA Write Engine Handshake Counter Channel 4/5/6/7 Register." bitfld.long 0x4 29.--31. "RSVDP_29,Reserved for future use." "0,1,2,3,4,5,6,7" hexmask.long.byte 0x4 24.--28. 1. "DMA_WRITE_ENGINE_HSHAKE_CNT_CH7,DMA handshake counter for DMA Write Engine Channel 7. If CC_DMA_HSHAKE =1 the data transfer in Linked List mode starts only when the counter is non-zero." newline bitfld.long 0x4 21.--23. "RSVDP_21,Reserved for future use." "0,1,2,3,4,5,6,7" hexmask.long.byte 0x4 16.--20. 1. "DMA_WRITE_ENGINE_HSHAKE_CNT_CH6,DMA handshake counter for DMA Write Engine Channel 6. If CC_DMA_HSHAKE =1 the data transfer in Linked List mode starts only when the counter is non-zero." newline bitfld.long 0x4 13.--15. "RSVDP_13,Reserved for future use." "0,1,2,3,4,5,6,7" hexmask.long.byte 0x4 8.--12. 1. "DMA_WRITE_ENGINE_HSHAKE_CNT_CH5,DMA handshake counter for DMA Write Engine Channel 5. If CC_DMA_HSHAKE =1 the data transfer in Linked List mode starts only when the counter is non-zero." newline bitfld.long 0x4 5.--7. "RSVDP_5,Reserved for future use." "0,1,2,3,4,5,6,7" hexmask.long.byte 0x4 0.--4. 1. "DMA_WRITE_ENGINE_HSHAKE_CNT_CH4,DMA handshake counter for DMA Write Engine Channel 4. If CC_DMA_HSHAKE =1 the data transfer in Linked List mode starts only when the counter is non-zero." rgroup.long (0x118+0xC8000)++0x7 line.long 0x0 "DMA_READ_ENGINE_HSHAKE_CNT_LOW_OFF,DMA Read Engine Handshake Counter Channel 0/1/2/3 Register." bitfld.long 0x0 29.--31. "RSVDP_29,Reserved for future use." "0,1,2,3,4,5,6,7" hexmask.long.byte 0x0 24.--28. 1. "DMA_READ_ENGINE_HSHAKE_CNT_CH3,DMA handshake counter for DMA Read Engine Channel 3. If CC_DMA_HSHAKE =1 the data transfer in Linked List mode starts only when the counter is non-zero." newline bitfld.long 0x0 21.--23. "RSVDP_21,Reserved for future use." "0,1,2,3,4,5,6,7" hexmask.long.byte 0x0 16.--20. 1. "DMA_READ_ENGINE_HSHAKE_CNT_CH2,DMA handshake counter for DMA Read Engine Channel 2. If CC_DMA_HSHAKE =1 the data transfer in Linked List mode starts only when the counter is non-zero." newline bitfld.long 0x0 13.--15. "RSVDP_13,Reserved for future use." "0,1,2,3,4,5,6,7" hexmask.long.byte 0x0 8.--12. 1. "DMA_READ_ENGINE_HSHAKE_CNT_CH1,DMA handshake counter for DMA Read Engine Channel 1. If CC_DMA_HSHAKE =1 the data transfer in Linked List mode starts only when the counter is non-zero." newline bitfld.long 0x0 5.--7. "RSVDP_5,Reserved for future use." "0,1,2,3,4,5,6,7" hexmask.long.byte 0x0 0.--4. 1. "DMA_READ_ENGINE_HSHAKE_CNT_CH0,DMA handshake counter for DMA Read Engine Channel 0. If CC_DMA_HSHAKE =1 the data transfer in Linked List mode starts only when the counter is non-zero." line.long 0x4 "DMA_READ_ENGINE_HSHAKE_CNT_HIGH_OFF,DMA Read Engine Handshake Counter Channel 4/5/6/7 Register." bitfld.long 0x4 29.--31. "RSVDP_29,Reserved for future use." "0,1,2,3,4,5,6,7" hexmask.long.byte 0x4 24.--28. 1. "DMA_READ_ENGINE_HSHAKE_CNT_CH7,DMA handshake counter for DMA Read Engine Channel 7. If CC_DMA_HSHAKE =1 the data transfer in Linked List mode starts only when the counter is non-zero." newline bitfld.long 0x4 21.--23. "RSVDP_21,Reserved for future use." "0,1,2,3,4,5,6,7" hexmask.long.byte 0x4 16.--20. 1. "DMA_READ_ENGINE_HSHAKE_CNT_CH6,DMA handshake counter for DMA Read Engine Channel 6. If CC_DMA_HSHAKE =1 the data transfer in Linked List mode starts only when the counter is non-zero." newline bitfld.long 0x4 13.--15. "RSVDP_13,Reserved for future use." "0,1,2,3,4,5,6,7" hexmask.long.byte 0x4 8.--12. 1. "DMA_READ_ENGINE_HSHAKE_CNT_CH5,DMA handshake counter for DMA Read Engine Channel 5. If CC_DMA_HSHAKE =1 the data transfer in Linked List mode starts only when the counter is non-zero." newline bitfld.long 0x4 5.--7. "RSVDP_5,Reserved for future use." "0,1,2,3,4,5,6,7" hexmask.long.byte 0x4 0.--4. 1. "DMA_READ_ENGINE_HSHAKE_CNT_CH4,DMA handshake counter for DMA Read Engine Channel 4. If CC_DMA_HSHAKE =1 the data transfer in Linked List mode starts only when the counter is non-zero." repeat 8. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 )(list 0x0 0x200 0x400 0x600 0x800 0xA00 0xC00 0xE00 ) group.long ($2+0x200+0xC8000)++0x3 line.long 0x0 "DMA_CH_CONTROL1_OFF_WRCH_$1,DMA Write Channel Control 1 Register." bitfld.long 0x0 30.--31. "DMA_AT,Address Translation TLP Header Bit (AT) The DMA uses this TLP header field when generating MRd/MWr (not IMWr) TLPs. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" "0,1,2,3" bitfld.long 0x0 27.--29. "DMA_TC,Traffic Class TLP Header Bit (TC) The DMA uses this TLP header field when generating MRd/MWr (not IMWr) TLPs. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 26. "DMA_RESERVED5,Reserved. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" "0,1" bitfld.long 0x0 25. "DMA_RO,Relaxed Ordering TLP Header Bit (RO) The DMA uses this TLP header field when generating MRd/MWr (not IMWr) TLPs. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" "0,1" newline bitfld.long 0x0 24. "DMA_NS_SRC,Source No Snoop TLP Header Bit (DMA_NS_SRC). The DMA uses this TLP header field when generating MRd (SAR addressing space) (not IMWr) TLPs. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" "0,1" bitfld.long 0x0 23. "DMA_NS_DST,Destination No Snoop TLP Header Bit (DMA_NS_DST). The DMA uses this TLP header field when generating MWr (DAR addressing space) (not IMWr) TLPs. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" "0,1" newline bitfld.long 0x0 22. "DMA_MEM_TYPE,Master AXI ACE-Lite Cache Coherency Control. This field sets the DMA channel memory type of the address space of the data transfer as follows: - 0x0:peripheral type - 0x1:memory type For more details see 'ACE-Lite Features and Limitations'.." "peripheral type,memory type" hexmask.long.byte 0x0 17.--21. 1. "DMA_RESERVED2,Reserved. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" newline hexmask.long.byte 0x0 12.--16. 1. "DMA_FUNC_NUM,Function Number (FN). The controller uses this field when generating the requester ID for the MRd/MWr DMA TLP. When you have enabled SR-IOV then this field is ignored if you have set the VFE field in the 'DMA Write Channel Control 2.." bitfld.long 0x0 10.--11. "DMA_RESERVED1,Reserved. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" "0,1,2,3" newline bitfld.long 0x0 9. "LLE,Linked List Enable (LLE). - 0: Disable linked list operation - 1: Enable linked list operation Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" "Disable linked list operation,Enable linked list operation" bitfld.long 0x0 8. "CCS,Consumer Cycle State (CCS). Used in linked list mode only. It is used to synchronize the producer (software) and the consumer (DMA). For more details see 'PCS-CCS-CB-TCB Producer-Consumer Synchronization'. You must initialize this bit. The DMA.." "0,1" newline bitfld.long 0x0 7. "DMA_RESERVED0,Reserved. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" "0,1" bitfld.long 0x0 5.--6. "CS,Channel Status (CS). The channel status bits identify the current operational state of the DMA channel. The operation state encoding for each DMA channel is a s follows: - 00: Reserved - 01: Running. This channel is active and transferring data. - 10:.." "Reserved,Running,?,?" newline bitfld.long 0x0 4. "RIE,Remote Interrupt Enable (RIE). You must set this bit to enable the generation of the Done or Abort Remote interrupts. For more details see 'Interrupts and Error Handling'. In LL mode the DMA overwrites this with the RIE of the LL element. The RIE.." "0,1" bitfld.long 0x0 3. "LIE,Local Interrupt Enable (LIE). You must set this bit to enable the generation of the Done or Abort Local interrupts. For more details see 'Interrupts and Error Handling'. In LL mode the DMA overwrites this with the LIE of the LL element. The LIE bit.." "0,1" newline bitfld.long 0x0 2. "LLP,Load Link Pointer (LLP). Used in linked list mode only. Indicates that this linked list element is a link element and its LL element pointer dwords are pointing to the next (non-contiguous) element. The DMA loads this field with the LLP of the.." "0,1" bitfld.long 0x0 1. "TCB,Toggle Cycle Bit (TCB). Indicates to the DMA to toggle its interpretation of the CB. Used in linked list mode only. It is used to synchronize the producer (software) and the consumer (DMA). For more details see 'PCS-CCS-CB-TCB Producer-Consumer.." "0,1" newline bitfld.long 0x0 0. "CB,Cycle Bit (CB). Used in linked list mode only. It is used to synchronize the producer (software) and the consumer (DMA). For more details see 'PCS-CCS-CB-TCB Producer-Consumer Synchronization'. The DMA loads this field with the CB of the linked list.." "0,1" repeat.end repeat 8. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 )(list 0x0 0x200 0x400 0x600 0x800 0xA00 0xC00 0xE00 ) group.long ($2+0x208+0xC8000)++0x3 line.long 0x0 "DMA_TRANSFER_SIZE_OFF_WRCH_$1,DMA Write Transfer Size Register." hexmask.long 0x0 0.--31. 1. "DMA_TRANSFER_SIZE,DMA Transfer Size. You program this register with the size of the DMA transfer. The maximum DMA transfer size is 4Gbytes. The minimum transfer size is one byte (0x1). This field is automatically decremented by the DMA as the DMA write.." repeat.end repeat 8. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 )(list 0x0 0x200 0x400 0x600 0x800 0xA00 0xC00 0xE00 ) group.long ($2+0x20C+0xC8000)++0x3 line.long 0x0 "DMA_SAR_LOW_OFF_WRCH_$1,DMA Write SAR Low Register." hexmask.long 0x0 0.--31. 1. "SRC_ADDR_REG_LOW,Source Address Register (Lower 32 bits). Indicates the next address to be read from. The DMA increments the SAR as the DMA transfer progresses. In LL mode the DMA overwrites this with the corresponding dword of the LL element. - DMA.." repeat.end repeat 8. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 )(list 0x0 0x200 0x400 0x600 0x800 0xA00 0xC00 0xE00 ) group.long ($2+0x210+0xC8000)++0x3 line.long 0x0 "DMA_SAR_HIGH_OFF_WRCH_$1,DMA Write SAR High Register." hexmask.long 0x0 0.--31. 1. "SRC_ADDR_REG_HIGH,Source Address Register (Higher 32 bits). In LL mode the DMA overwrites this with the corresponding dword of the LL element. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" repeat.end repeat 8. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 )(list 0x0 0x200 0x400 0x600 0x800 0xA00 0xC00 0xE00 ) group.long ($2+0x214+0xC8000)++0x3 line.long 0x0 "DMA_DAR_LOW_OFF_WRCH_$1,DMA Write DAR Low Register." hexmask.long 0x0 0.--31. 1. "DST_ADDR_REG_LOW,Destination Address Register (Lower 32 bits). Indicates the next address to be written to. The DMA increments the DAR as the DMA transfer progresses. In LL mode the DMA overwrites this with the corresponding dword of the LL element. -.." repeat.end repeat 8. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 )(list 0x0 0x200 0x400 0x600 0x800 0xA00 0xC00 0xE00 ) group.long ($2+0x218+0xC8000)++0x3 line.long 0x0 "DMA_DAR_HIGH_OFF_WRCH_$1,DMA Write DAR High Register." hexmask.long 0x0 0.--31. 1. "DST_ADDR_REG_HIGH,Destination Address Register (Higher 32 bits). In LL mode the DMA overwrites this with the corresponding dword of the LL element. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" repeat.end repeat 8. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 )(list 0x0 0x200 0x400 0x600 0x800 0xA00 0xC00 0xE00 ) group.long ($2+0x21C+0xC8000)++0x3 line.long 0x0 "DMA_LLP_LOW_OFF_WRCH_$1,DMA Write Linked List Pointer Low Register." hexmask.long 0x0 0.--31. 1. "LLP_LOW,Lower bits of the address of the linked list transfer list in local memory. Used in linked list mode only. Updated by the DMA to point to the next element in the transfer list after the previous element is consumed. - When the current element is.." repeat.end repeat 8. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 )(list 0x0 0x200 0x400 0x600 0x800 0xA00 0xC00 0xE00 ) group.long ($2+0x220+0xC8000)++0x3 line.long 0x0 "DMA_LLP_HIGH_OFF_WRCH_$1,DMA Write Linked List Pointer High Register." hexmask.long 0x0 0.--31. 1. "LLP_HIGH,Upper 32 bits of the address of the linked list transfer list in local memory. Used in linked list mode only. Updated by the DMA to point to the next element in the transfer list as elements are consumed. Note: The access attributes of this.." repeat.end repeat 8. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 )(list 0x0 0x200 0x400 0x600 0x800 0xA00 0xC00 0xE00 ) group.long ($2+0x300+0xC8000)++0x3 line.long 0x0 "DMA_CH_CONTROL1_OFF_RDCH_$1,DMA Read Channel Control 1 Register." bitfld.long 0x0 30.--31. "DMA_AT,Address Translation TLP Header Bit (AT) The DMA uses this TLP header field when generating MRd/MWr (not IMWr) TLPs. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" "0,1,2,3" bitfld.long 0x0 27.--29. "DMA_TC,Traffic Class TLP Header Bit (TC) The DMA uses this TLP header field when generating MRd/MWr (not IMWr) TLPs. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 26. "DMA_RESERVED5,Reserved. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" "0,1" bitfld.long 0x0 25. "DMA_RO,Relaxed Ordering TLP Header Bit (RO) The DMA uses this TLP header field when generating MRd/MWr (not IMWr) TLPs. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" "0,1" newline bitfld.long 0x0 24. "DMA_NS_SRC,Source No Snoop TLP Header Bit (DMA_NS_SRC). The DMA uses this TLP header field when generating MRd (SAR addressing space) (not IMWr) TLPs. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" "0,1" bitfld.long 0x0 23. "DMA_NS_DST,Destination No Snoop TLP Header Bit (DMA_NS_DST). The DMA uses this TLP header field when generating MWr (DAR addressing space) (not IMWr) TLPs. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" "0,1" newline bitfld.long 0x0 22. "DMA_MEM_TYPE,Master AXI ACE-Lite Cache Coherency Control. This field sets the DMA channel memory type of the address space of the data transfer as follows: - 0x0:peripheral type - 0x1:memory type For more details see 'ACE-Lite Features and Limitations'.." "peripheral type,memory type" hexmask.long.byte 0x0 17.--21. 1. "DMA_RESERVED2,Reserved. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" newline hexmask.long.byte 0x0 12.--16. 1. "DMA_FUNC_NUM,Function Number (FN). The controller uses this field when generating the requester ID for the MRd/MWr DMA TLP. When you have enabled SR-IOV then this field is ignored if you have set the VFE field in the 'DMA Read Channel Control 2.." bitfld.long 0x0 10.--11. "DMA_RESERVED1,Reserved. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" "0,1,2,3" newline bitfld.long 0x0 9. "LLE,Linked List Enable (LLE). - 0: Disable linked list operation - 1: Enable linked list operation Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" "Disable linked list operation,Enable linked list operation" bitfld.long 0x0 8. "CCS,Consumer Cycle State (CCS). Used in linked list mode only. It is used to synchronize the producer (software) and the consumer (DMA). For more details see 'PCS-CCS-CB-TCB Producer-Consumer Synchronization'. You must initialize this bit. The DMA.." "0,1" newline bitfld.long 0x0 7. "DMA_RESERVED0,Reserved. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" "0,1" bitfld.long 0x0 5.--6. "CS,Channel Status (CS). The channel status bits identify the current operational state of the DMA channel. The operation state encoding for each DMA channel is a s follows: - 00: Reserved - 01: Running. This channel is active and transferring data. - 10:.." "Reserved,Running,?,?" newline bitfld.long 0x0 4. "RIE,Remote Interrupt Enable (RIE). You must set this bit to enable the generation of the Done or Abort Remote interrupts. For more details see 'Interrupts and Error Handling'. In LL mode the DMA overwrites this with the RIE of the LL element. The RIE.." "0,1" bitfld.long 0x0 3. "LIE,Local Interrupt Enable (LIE). You must set this bit to enable the generation of the Done or Abort Local interrupts. For more details see 'Interrupts and Error Handling'. In LL mode the DMA overwrites this with the LIE of the LL element. The LIE bit.." "0,1" newline bitfld.long 0x0 2. "LLP,Load Link Pointer (LLP). Used in linked list mode only. Indicates that this linked list element is a link element and its LL element pointer dwords are pointing to the next (non-contiguous) element. The DMA loads this field with the LLP of the.." "0,1" bitfld.long 0x0 1. "TCB,Toggle Cycle Bit (TCB). Indicates to the DMA to toggle its interpretation of the CB. Used in linked list mode only. It is used to synchronize the producer (software) and the consumer (DMA). For more details see 'PCS-CCS-CB-TCB Producer-Consumer.." "0,1" newline bitfld.long 0x0 0. "CB,Cycle Bit (CB). Used in linked list mode only. It is used to synchronize the producer (software) and the consumer (DMA). For more details see 'PCS-CCS-CB-TCB Producer-Consumer Synchronization'. The DMA loads this field with the CB of the linked list.." "0,1" repeat.end repeat 8. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 )(list 0x0 0x200 0x400 0x600 0x800 0xA00 0xC00 0xE00 ) group.long ($2+0x308+0xC8000)++0x3 line.long 0x0 "DMA_TRANSFER_SIZE_OFF_RDCH_$1,DMA Read Transfer Size Register." hexmask.long 0x0 0.--31. 1. "DMA_TRANSFER_SIZE,DMA Transfer Size. You program this register with the size of the DMA transfer. The maximum DMA transfer size is 4Gbytes. The minimum transfer size is one byte (0x1). This field is automatically decremented by the DMA as the DMA read.." repeat.end repeat 8. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 )(list 0x0 0x200 0x400 0x600 0x800 0xA00 0xC00 0xE00 ) group.long ($2+0x30C+0xC8000)++0x3 line.long 0x0 "DMA_SAR_LOW_OFF_RDCH_$1,DMA Read SAR Low Register." hexmask.long 0x0 0.--31. 1. "SRC_ADDR_REG_LOW,Source Address Register (Lower 32 bits). Indicates the next address to be read from. The DMA increments the SAR as the DMA transfer progresses. In LL mode the DMA overwrites this with the corresponding dword of the LL element. - DMA.." repeat.end repeat 8. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 )(list 0x0 0x200 0x400 0x600 0x800 0xA00 0xC00 0xE00 ) group.long ($2+0x310+0xC8000)++0x3 line.long 0x0 "DMA_SAR_HIGH_OFF_RDCH_$1,DMA Read SAR High Register." hexmask.long 0x0 0.--31. 1. "SRC_ADDR_REG_HIGH,Source Address Register (Higher 32 bits). In LL mode the DMA overwrites this with the corresponding dword of the LL element. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" repeat.end repeat 8. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 )(list 0x0 0x200 0x400 0x600 0x800 0xA00 0xC00 0xE00 ) group.long ($2+0x314+0xC8000)++0x3 line.long 0x0 "DMA_DAR_LOW_OFF_RDCH_$1,DMA Read DAR Low Register." hexmask.long 0x0 0.--31. 1. "DST_ADDR_REG_LOW,Destination Address Register (Lower 32 bits). Indicates the next address to be written to. The DMA increments the DAR as the DMA transfer progresses. In LL mode the DMA overwrites this with the corresponding dword of the LL element. -.." repeat.end repeat 8. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 )(list 0x0 0x200 0x400 0x600 0x800 0xA00 0xC00 0xE00 ) group.long ($2+0x318+0xC8000)++0x3 line.long 0x0 "DMA_DAR_HIGH_OFF_RDCH_$1,DMA Read DAR High Register." hexmask.long 0x0 0.--31. 1. "DST_ADDR_REG_HIGH,Destination Address Register (Higher 32 bits). In LL mode the DMA overwrites this with the corresponding dword of the LL element. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" repeat.end repeat 8. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 )(list 0x0 0x200 0x400 0x600 0x800 0xA00 0xC00 0xE00 ) group.long ($2+0x31C+0xC8000)++0x3 line.long 0x0 "DMA_LLP_LOW_OFF_RDCH_$1,DMA Read Linked List Pointer Low Register." hexmask.long 0x0 0.--31. 1. "LLP_LOW,Lower bits of the address of the linked list transfer list in local memory. Used in linked list mode only. Updated by the DMA to point to the next element in the transfer list after the previous element is consumed. - When the current element is.." repeat.end repeat 8. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 )(list 0x0 0x200 0x400 0x600 0x800 0xA00 0xC00 0xE00 ) group.long ($2+0x320+0xC8000)++0x3 line.long 0x0 "DMA_LLP_HIGH_OFF_RDCH_$1,DMA Read Linked List Pointer High Register." hexmask.long 0x0 0.--31. 1. "LLP_HIGH,Upper 32 bits of the address of the linked list transfer list in local memory. Used in linked list mode only. Updated by the DMA to point to the next element in the transfer list as elements are consumed. Note: The access attributes of this.." repeat.end tree.end tree "PF0_ATU_CAP (ATU Por Logic Structure)" repeat 8. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 )(list 0x0 0x200 0x400 0x600 0x800 0xA00 0xC00 0xE00 ) group.long ($2+0xC0000)++0x3 line.long 0x0 "IATU_REGION_CTRL_1_OFF_OUTBOUND_$1,iATU Region Control 1 Register." bitfld.long 0x0 20. "CTRL_1_FUNC_NUM,Function Number. - When the address of an outbound TLP is matched to this region and the FUNC_BYPASS field in the 'iATU Control 2 Register' is '0' then the function number used in generating the function part of the requester ID (RID).." "0,1" newline bitfld.long 0x0 13. "INCREASE_REGION_SIZE,Increase the maximum ATU Region size. When set the maximum ATU Region size is determined by CX_ATU_MAX_REGION_SIZE. When clear the maximum ATU Region size is 4 GB (default). Note: This register field is sticky." "0,1" newline bitfld.long 0x0 9.--10. "ATTR,When the address of an outbound TLP is matched to this region then the ATTR field of the TLP is changed to the value in this register. Note: This register field is sticky." "0,1,2,3" newline bitfld.long 0x0 8. "TD,This is a reserved field. Do not use. Note: This register field is sticky." "0,1" newline bitfld.long 0x0 5.--7. "TC,When the address of an outbound TLP is matched to this region then the TC field of the TLP is changed to the value in this register. Note: This register field is sticky." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x0 0.--4. 1. "TYPE,When the address of an outbound TLP is matched to this region then the TYPE field of the TLP is changed to the value in this register. Note: This register field is sticky." repeat.end repeat 8. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 )(list 0x0 0x200 0x400 0x600 0x800 0xA00 0xC00 0xE00 ) group.long ($2+0x4+0xC0000)++0x3 line.long 0x0 "IATU_REGION_CTRL_2_OFF_OUTBOUND_$1,iATU Region Control 2 Register." bitfld.long 0x0 31. "REGION_EN,Region Enable. This bit must be set to '1' for address translation to take place. Note: This register field is sticky." "0,1" newline bitfld.long 0x0 29. "INVERT_MODE,Invert Mode. When set the address matching region is inverted. Therefore an address match occurs when the untranslated address is in the region outside the defined range (Base Address to Limit Address). Note: This register field is sticky." "0,1" newline bitfld.long 0x0 28. "CFG_SHIFT_MODE,CFG Shift Mode. The iATU uses bits [27:12] of the untranslated address (on the XALI0/1/2 interface or AXI slave interface address) to form the BDF number of the outgoing CFG TLP. This supports the Enhanced Configuration Address Mapping.." "0,1" newline bitfld.long 0x0 27. "DMA_BYPASS,DMA Bypass Mode. Allows request TLPs which are initiated by the DMA controller to pass through the iATU untranslated. Note: This field is reserved for the SW product. You must set it to '0'. Note: This register field is sticky." "0,1" newline bitfld.long 0x0 23. "HEADER_SUBSTITUTE_EN,Header Substitute Enable. When enabled and region address is matched the iATU fully substitutes bytes 8-11 (for 3 DWORD header) or bytes 12-15 (for 4 DWORD header) of the outbound TLP header with the contents of the LWR_TARGET_RW.." "LWR_TARGET_RW in the..,LWR_TARGET_RW in the.." newline bitfld.long 0x0 22. "INHIBIT_PAYLOAD,Inhibit TLP Payload Data for TLP's in Matched Region; assign iATU region to be TLP without data. When enabled and region address is matched the iATU marks all TLPs as having no payload data by forcing the TLP header Fmt[1] bit =0.." "Fmt[1] =0/1 so that TLPs with or without data..,Fmt[1] =0 so that only TLP type without data is.." newline bitfld.long 0x0 21. "TLP_HEADER_FIELDS_BYPASS,TLP Header Fields Translation Bypass. In this mode header fields of the translated TLP is taken from your application transmit interface or if AMBA is configured from the AMBA sideband bus (slv_awmisc_info) and not from the.." "0,1" newline bitfld.long 0x0 20. "SNP,Serialize Non-Posted Requests. In this mode when the AXI Bridge is populated same AXI ID Non-Posted Read/Write Requests are transmitted on the wire if there are no other same ID Non-Posted Requests outstanding. Note: This register field is sticky." "0,1" newline bitfld.long 0x0 19. "FUNC_BYPASS,Function Number Translation Bypass. In this mode the function number of the translated TLP is taken from your application transmit interface and not from the CTRL_1_FUNC_NUM field of the 'iATU Control 1 Register' or the VF_NUMBER field of.." "0,1" newline bitfld.long 0x0 16. "TAG_SUBSTITUTE_EN,TAG Substitute Enable. When enabled and region address is matched the iATU substitutes the TAG field of the outbound TLP header with the contents of the TAG field in this register. The expected usage scenario is translation from AXI.." "0,1" newline hexmask.long.byte 0x0 8.--15. 1. "TAG,TAG. The substituted TAG field (byte 6) in the outgoing TLP header when TAG_SUBSTITUTE_EN is set. Note: This register field is sticky." newline hexmask.long.byte 0x0 0.--7. 1. "MSG_CODE,MSG TLPs (Message Code). When the address of an outbound TLP is matched to this region and the translated TLP TYPE field is Msg or MsgD; then the message field of the TLP is changed to the value in this register. Memory TLPs: (ST;Steering Tag)." repeat.end repeat 8. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 )(list 0x0 0x200 0x400 0x600 0x800 0xA00 0xC00 0xE00 ) group.long ($2+0x8+0xC0000)++0x3 line.long 0x0 "IATU_LWR_BASE_ADDR_OFF_OUTBOUND_$1,iATU Lower Base Address Register. The CX_ATU_MIN_REGION_SIZE configuration parameter (Value Range: 4 kB. 8 kB. 16 kB. 32 kB. 64 kB defaults to 64 kB) specifies the minimum size of an address translation region. For.." hexmask.long.tbyte 0x0 12.--31. 1. "LWR_BASE_RW,Forms bits [31:n] of the start address of the address region to be translated. n is log2(CX_ATU_MIN_REGION_SIZE) Note: This register field is sticky." newline hexmask.long.word 0x0 0.--11. 1. "LWR_BASE_HW,Forms bits [n-1:0] of the start address of the address region to be translated. The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary so these bits are always 0. A write to this location is ignored by the PCIe controller." repeat.end repeat 8. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 )(list 0x0 0x200 0x400 0x600 0x800 0xA00 0xC00 0xE00 ) group.long ($2+0xC+0xC0000)++0x3 line.long 0x0 "IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_$1,iATU Upper Base Address Register." hexmask.long 0x0 0.--31. 1. "UPPER_BASE_RW,Forms bits [63:32] of the start (and end) address of the address region to be translated. In systems with a 32-bit address space this register is not used and therefore writing to this register has no effect. Note: This register field is.." repeat.end repeat 8. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 )(list 0x0 0x200 0x400 0x600 0x800 0xA00 0xC00 0xE00 ) group.long ($2+0x10+0xC0000)++0x3 line.long 0x0 "IATU_LIMIT_ADDR_OFF_OUTBOUND_$1,iATU Limit Address Register." hexmask.long.tbyte 0x0 12.--31. 1. "LIMIT_ADDR_RW,Forms upper bits of the end address of the address region to be translated. Note: This register field is sticky." newline hexmask.long.word 0x0 0.--11. 1. "LIMIT_ADDR_HW,Forms lower bits of the end address of the address region to be translated. The end address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary so these bits are always all ones. A write to this location is ignored by the PCIe.." repeat.end repeat 8. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 )(list 0x0 0x200 0x400 0x600 0x800 0xA00 0xC00 0xE00 ) group.long ($2+0x14+0xC0000)++0x3 line.long 0x0 "IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_$1,iATU Lower Target Address Register." hexmask.long 0x0 0.--31. 1. "LWR_TARGET_RW_OUTBOUND,When HEADER_SUBSTITUTE_EN in IATU_REGION_CTRL_2_OFF_OUTBOUND_ is '0' (normal operation): - LWR_TARGET_RW[31:n] forms MSB's of the Lower Target part of the new address of the translated region; - LWR_TARGET_RW[n-1:0] are not used." repeat.end repeat 8. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 )(list 0x0 0x200 0x400 0x600 0x800 0xA00 0xC00 0xE00 ) group.long ($2+0x18+0xC0000)++0x3 line.long 0x0 "IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_$1,iATU Upper Target Address Register." hexmask.long 0x0 0.--31. 1. "UPPER_TARGET_RW,Forms bits [63:32] of the start address (Upper Target part) of the new address of the translated region. Note: This register field is sticky." repeat.end repeat 8. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 )(list 0x0 0x200 0x400 0x600 0x800 0xA00 0xC00 0xE00 ) group.long ($2+0x1C+0xC0000)++0x3 line.long 0x0 "IATU_REGION_CTRL_3_OFF_OUTBOUND_$1,iATU Region Control 3 Register." bitfld.long 0x0 31. "VF_ACTIVE,Virtual Function Active. Indicates that all of the outbound accesses are from virtual functions. For more details see VF_ACTIVE field. Note: This register field is sticky." "0,1" newline hexmask.long 0x0 3.--30. 1. "RSVDP_VF_NUMBER,Reserved for future use." newline bitfld.long 0x0 0.--2. "VF_NUMBER,Virtual Function Number. When the address of an outbound TLP is matched to this region and the FUNC_BYPASS field in the 'iATU Control 2 Register' is '0' then this field used in generating the Function part of the requester ID (RID) field of.." "0,1,2,3,4,5,6,7" repeat.end repeat 8. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 )(list 0x0 0x200 0x400 0x600 0x800 0xA00 0xC00 0xE00 ) group.long ($2+0x100+0xC0000)++0x3 line.long 0x0 "IATU_REGION_CTRL_1_OFF_INBOUND_$1,iATU Region Control 1 Register." bitfld.long 0x0 20. "CTRL_1_FUNC_NUM,Function Number. - MEM-I/O: When the Address and BAR matching logic in the controller indicate that a MEM-I/O transaction matches a BAR in the function corresponding to this value then address translation proceeds. This check is only.." "?,When the destination function number as.." newline bitfld.long 0x0 13. "INCREASE_REGION_SIZE,Increase the maximum ATU Region size. When set the maximum ATU Region size is determined by CX_ATU_MAX_REGION_SIZE. When clear the maximum ATU Region size is 4 GB (default). Note: This register field is sticky." "0,1" newline bitfld.long 0x0 9.--10. "ATTR,When the ATTR field of an inbound TLP is matched to this value then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the 'ATTR Match Enable' bit of the 'iATU Control 2 Register' is.." "0,1,2,3" newline bitfld.long 0x0 8. "TD,When the TD field of an inbound TLP is matched to this value then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the 'TD Match Enable' bit of the 'iATU Control 2 Register' is set." "0,1" newline bitfld.long 0x0 5.--7. "TC,When the TC field of an inbound TLP is matched to this value then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the 'TC Match Enable' bit of the 'iATU Control 2 Register' is set." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x0 0.--4. 1. "TYPE,When the TYPE field of an inbound TLP is matched to this value then address translation proceeds (when all other enabled field-matches are successful). Note: This register field is sticky." repeat.end repeat 8. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 )(list 0x0 0x200 0x400 0x600 0x800 0xA00 0xC00 0xE00 ) group.long ($2+0x104+0xC0000)++0x3 line.long 0x0 "IATU_REGION_CTRL_2_OFF_INBOUND_$1,iATU Region Control 2 Register." bitfld.long 0x0 31. "REGION_EN,Region Enable. This bit must be set to '1' for address translation to take place. Note: This register field is sticky." "0,1" newline bitfld.long 0x0 30. "MATCH_MODE,Match Mode. Determines Inbound matching mode for TLPs. The mode depends on the type of TLP that is received as follows: For MEM-I/O TLPs this field is interpreted as follows: - 0: Address Match Mode. The iATU operates using addresses as in.." "Address Match Mode,Vendor ID Match Mode" newline bitfld.long 0x0 29. "INVERT_MODE,Invert Mode. When set the address matching region is inverted. Therefore an address match occurs when the untranslated address is in the region outside the defined range (Base Address to Limit Address). Note: This register field is sticky." "0,1" newline bitfld.long 0x0 28. "CFG_SHIFT_MODE,CFG Shift Mode. This is useful for CFG transactions where the PCIe configuration mechanism maps bits [27:12] of the address to the bus/device and function number. This allows a CFG configuration space to be located in any 256MB window of.." "0,1" newline bitfld.long 0x0 27. "FUZZY_TYPE_MATCH_CODE,Fuzzy Type Match Mode. When enabled the iATU relaxes the matching of the TLP TYPE field against the expected TYPE field so that - CfgRd0 and CfgRd1 TLPs are seen as identical. Similarly with CfgWr0 and CfgWr1. - MWr MRd and MRdLk.." "0,1" newline bitfld.long 0x0 26. "VFBAR_MATCH_MODE_EN,VF BAR Match Mode enable. When set Virtual Function BAR matching is used which allows all VFs in a PF which match a BAR to be matched with a single ATU region. Note: This register field is sticky." "0,1" newline bitfld.long 0x0 24.--25. "RESPONSE_CODE,Response Code. Defines the type of response to give for accesses matching this region. This overrides the normal RADM filter response. Note that this feature is not available for any region where Single Address Location Translate is.." "Normal RADM filter response is used,Unsupported request,?,?" newline bitfld.long 0x0 23. "SINGLE_ADDR_LOC_TRANS_EN,Single Address Location Translate Enable. When enabled Rx TLPs can be translated to a single address location as determined by the target address register of the iATU region. The main usage scenario is translation of Messages.." "0,1" newline bitfld.long 0x0 21. "MSG_CODE_MATCH_EN,Message Code Match Enable (Msg TLPS). Ensures that a successful message Code TLP field comparison match (see Message Code field of the 'iATU Control 2 Register') occurs (in MSG transactions) for address translation to proceed. ST Match.." "0,1" newline bitfld.long 0x0 20. "VF_MATCH_EN,Virtual Function Number Match Enable. Ensures that a successful Virtual Function Number TLP field comparison match (see Virtual Function Number field of the 'iATU Control 3 Register') occurs (in MEM-I/O transactions) for address translation.." "0,1" newline bitfld.long 0x0 19. "FUNC_NUM_MATCH_EN,Function Number Match Enable. Ensures that a successful Function Number TLP field comparison match (see Function Number field of the 'iATU Control 1 Register') occurs (in MEM-I/O and CFG0/CFG1 transactions) for address translation to.." "0,1" newline bitfld.long 0x0 16. "ATTR_MATCH_EN,ATTR Match Enable. Ensures that a successful ATTR TLP field comparison match (see ATTR field of the 'iATU Control 1 Register') occurs for address translation to proceed. Note: This register field is sticky." "0,1" newline bitfld.long 0x0 15. "TD_MATCH_EN,TD Match Enable. Ensures that a successful TD TLP field comparison match (see TD field of the 'iATU Control 1 Register') occurs for address translation to proceed. Note: This register field is sticky." "0,1" newline bitfld.long 0x0 14. "TC_MATCH_EN,TC Match Enable. Ensures that a successful TC TLP field comparison match (see TC field of the 'iATU Control 1 Register') occurs for address translation to proceed. Note: This register field is sticky." "0,1" newline bitfld.long 0x0 13. "MSG_TYPE_MATCH_MODE,Message Type Match Mode. When enabled and if single address location translate enable is set then inbound TLPs of type MSG/MSGd which match the type field of the iatu_region_ctrl_1_OFF_inbound register (=>TYPE[4:3]=2'b10) will be.." "0,1" newline bitfld.long 0x0 8.--10. "BAR_NUM,BAR Number. When the BAR number of an inbound MEM or IO TLP ' that is matched by the normal internal BAR address matching mechanism ' is the same as this field address translation proceeds (when all other enabled field-matches are successful)." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x0 0.--7. 1. "MSG_CODE,MSG TLPs: (Message Code). When the TYPE field of an inbound Msg/MsgD TLP is matched to this value then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the 'Message Code Match.." repeat.end repeat 8. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 )(list 0x0 0x200 0x400 0x600 0x800 0xA00 0xC00 0xE00 ) group.long ($2+0x108+0xC0000)++0x3 line.long 0x0 "IATU_LWR_BASE_ADDR_OFF_INBOUND_$1,iATU Lower Base Address Register. The CX_ATU_MIN_REGION_SIZE configuration parameter (Value Range: 4 kB. 8 kB. 16 kB. 32 kB. 64 kB defaults to 64 kB) specifies the minimum size of an address translation region. For.." hexmask.long.tbyte 0x0 12.--31. 1. "LWR_BASE_RW,Forms bits [31:n] of the start address of the address region to be translated. n is log2(CX_ATU_MIN_REGION_SIZE) Note: This register field is sticky." newline hexmask.long.word 0x0 0.--11. 1. "LWR_BASE_HW,Forms bits [n-1:0] of the start address of the address region to be translated. The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary so these bits are always 0. A write to this location is ignored by the PCIe controller." repeat.end repeat 8. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 )(list 0x0 0x200 0x400 0x600 0x800 0xA00 0xC00 0xE00 ) group.long ($2+0x10C+0xC0000)++0x3 line.long 0x0 "IATU_UPPER_BASE_ADDR_OFF_INBOUND_$1,iATU Upper Base Address Register." hexmask.long 0x0 0.--31. 1. "UPPER_BASE_RW,Forms bits [63:32] of the start (and end) address of the address region to be translated. Note: This register field is sticky." repeat.end repeat 8. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 )(list 0x0 0x200 0x400 0x600 0x800 0xA00 0xC00 0xE00 ) group.long ($2+0x110+0xC0000)++0x3 line.long 0x0 "IATU_LIMIT_ADDR_OFF_INBOUND_$1,iATU Limit Address Register." hexmask.long.tbyte 0x0 12.--31. 1. "LIMIT_ADDR_RW,Forms upper bits of the end address of the address region to be translated. Note: This register field is sticky." newline hexmask.long.word 0x0 0.--11. 1. "LIMIT_ADDR_HW,Forms lower bits of the end address of the address region to be translated. The end address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary so these bits are always all ones. A write to this location is ignored by the PCIe.." repeat.end repeat 8. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 )(list 0x0 0x200 0x400 0x600 0x800 0xA00 0xC00 0xE00 ) group.long ($2+0x114+0xC0000)++0x3 line.long 0x0 "IATU_LWR_TARGET_ADDR_OFF_INBOUND_$1,iATU Lower Target Address Register." hexmask.long.tbyte 0x0 12.--31. 1. "LWR_TARGET_RW,Forms MSB's of the Lower Target part of the new address of the translated region. These bits are always '0'. - Field size depends on log2(CX_ATU_MIN_REGION_SIZE) in address match mode. - Field size depends on log2(BAR_MASK+1) in BAR match.." newline hexmask.long.word 0x0 0.--11. 1. "LWR_TARGET_HW,Forms the LSB's of the Lower Target part of the new address of the translated region. The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary (in address match mode); and to the Bar size boundary (in BAR match mode) so.." repeat.end repeat 8. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 )(list 0x0 0x200 0x400 0x600 0x800 0xA00 0xC00 0xE00 ) group.long ($2+0x118+0xC0000)++0x3 line.long 0x0 "IATU_UPPER_TARGET_ADDR_OFF_INBOUND_$1,iATU Upper Target Address Register." hexmask.long 0x0 0.--31. 1. "UPPER_TARGET_RW,Forms bits [63:32] of the start address (Upper Target part) of the new address of the translated region. In systems with a 32-bit address space this register is not used and therefore writing to this register has no effect. Note: This.." repeat.end repeat 8. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 )(list 0x0 0x200 0x400 0x600 0x800 0xA00 0xC00 0xE00 ) group.long ($2+0x11C+0xC0000)++0x3 line.long 0x0 "IATU_REGION_CTRL_3_OFF_INBOUND_$1,iATU Region Control 3 Register." rbitfld.long 0x0 31. "VF_ACTIVE,Reserved. Not used." "0,1" newline hexmask.long 0x0 3.--30. 1. "RSVDP_VF_NUMBER,Reserved for future use." newline bitfld.long 0x0 0.--2. "VF_NUMBER,Virtual Function Number. When the Address and BAR matching logic in the controller indicates that a MEM-I/O transaction matches a BAR in the virtual function corresponding to this value then address translation proceeds. This check is only.." "0,1,2,3,4,5,6,7" repeat.end tree.end tree "PF0_PORT_LOGIC (Port Logic)" group.long (0x0+0x700)++0x27 line.long 0x0 "ACK_LATENCY_TIMER_OFF,Ack Latency Timer and Replay Timer Register." hexmask.long.word 0x0 16.--31. 1. "REPLAY_TIME_LIMIT,Replay Timer Limit. The replay timer expires when it reaches this limit. The controller initiates a replay upon reception of a NAK or when the replay timer expires. For more details see 'Transmit Replay'. You can modify the effective.." newline hexmask.long.word 0x0 0.--15. 1. "ROUND_TRIP_LATENCY_TIME_LIMIT,Ack Latency Timer Limit. The Ack latency timer expires when it reaches this limit. For more details see 'Ack Scheduling'. You can modify the effective timer limit with the TIMER_MOD_ACK_NAK field of the.." line.long 0x4 "VENDOR_SPEC_DLLP_OFF,Vendor Specific DLLP Register." hexmask.long 0x4 0.--31. 1. "VENDOR_SPEC_DLLP,Vendor Specific DLLP Register. Used to send a specific PCI Express DLLP. Your application writes the 8-bit DLLP Type and 24-bits of Payload data into this register then sets the field VENDOR_SPECIFIC_DLLP_REQ of PORT_LINK_CTRL_OFF to.." line.long 0x8 "PORT_FORCE_OFF,Port Force Link Register." hexmask.long.byte 0x8 24.--31. 1. "RSVDP_24,Reserved for future use." newline bitfld.long 0x8 23. "DO_DESKEW_FOR_SRIS,Use the transitions from TS2 to Logical Idle Symbol SKP OS to Logical Idle Symbol EIEOS to Logical Idle Symbol and FTS Sequence to SKP OS to do deskew instead of using received SKP OS or TS1 to TS2 transition if DO_DESKEW_FOR_SRIS.." "0,1" newline rbitfld.long 0x8 22. "RSVDP_22,Reserved for future use." "0,1" newline hexmask.long.byte 0x8 16.--21. 1. "LINK_STATE,Forced LTSSM State. The LTSSM state that the controller is forced to when you set the FORCE_EN bit (Force Link). LTSSM state encoding is defined by the lts_state variable in workspace/src/Layer1/smlh_ltssm.v. Note: This register field is sticky." newline bitfld.long 0x8 15. "FORCE_EN,Force Link. The controller supports a testing and debug capability to allow your software to force the LTSSM state machine into a specific state and to force the controller to transmit a specific Link Command. Asserting this bit triggers the.." "0,1" newline rbitfld.long 0x8 12.--14. "RSVDP_12,Reserved for future use." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x8 8.--11. 1. "FORCED_LTSSM,Forced Link Command. The link command that the controller is forced to transmit when you set FORCE_EN bit (Force Link). Link command encoding is defined by the ltssm_cmd variable in workspace/src/Layer1/smlh_ltssm.v. Note: This register.." newline hexmask.long.byte 0x8 0.--7. 1. "LINK_NUM,Link Number. Not used for endpoint. Not used for M-PCIe. Note: This register field is sticky." line.long 0xC "ACK_F_ASPM_CTRL_OFF,Ack Frequency and L0-L1 ASPM Control Register." rbitfld.long 0xC 31. "RSVDP_31,Reserved for future use." "0,1" newline bitfld.long 0xC 30. "ENTER_ASPM,ASPM L1 Entry Control. - 1: Controller enters ASPM L1 after a period in which it has been idle. - 0: Controller enters ASPM L1 only after idle period during which both receive and transmit are in L0s. Note: This register field is sticky." "Controller enters ASPM L1 only after idle period..,Controller enters ASPM L1 after a period in.." newline bitfld.long 0xC 27.--29. "L1_ENTRANCE_LATENCY,L1 Entrance Latency. Value range is: - 000: 1 us - 001: 2 us - 010: 4 us - 011: 8 us - 100: 16 us - 101: 32 us - 110 or 111: 64 us Note: Programming this timer with a value greater that 32us has no effect unless extended sync is used.." "0,1,2,3,4,5,6,7" newline bitfld.long 0xC 24.--26. "L0S_ENTRANCE_LATENCY,L0s Entrance Latency. Values correspond to: - 000: 1 us - 001: 2 us - 010: 3 us - 011: 4 us - 100: 5 us - 101: 6 us - 110 or 111: 7 us This field is applicable to STALL while in L0 for M-PCIe. Note: This register field is sticky." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0xC 16.--23. 1. "COMMON_CLK_N_FTS,Common Clock N_FTS. This is the N_FTS when common clock is used. The number of Fast Training Sequence ordered sets to be transmitted when transitioning from L0s to L0. The maximum number of FTS ordered-sets that a component can request.." newline hexmask.long.byte 0xC 8.--15. 1. "ACK_N_FTS,N_FTS. The number of Fast Training Sequence ordered sets to be transmitted when transitioning from L0s to L0. The maximum number of FTS ordered-sets that a component can request is 255. The controller does not support a value of zero; a value.." newline hexmask.long.byte 0xC 0.--7. 1. "ACK_FREQ,Ack Frequency. The controller accumulates the number of pending ACKs specified here (up to 255) before scheduling an ACK DLLP. - 0: Indicates that this Ack Frequency Counter feature is turned off. The controller generates a low-priority ACK.." line.long 0x10 "PORT_LINK_CTRL_OFF,Port Link Control Register." hexmask.long.byte 0x10 28.--31. 1. "RSVDP_28,Reserved for future use." newline bitfld.long 0x10 27. "TRANSMIT_LANE_REVERSALE_ENABLE,TRANSMIT_LANE_REVERSALE_ENABLE is an internally reserved field. Do not use. Note: This register field is sticky." "0,1" newline bitfld.long 0x10 26. "EXTENDED_SYNCH,EXTENDED_SYNCH is an internally reserved field. Do not use. Note: This register field is sticky." "0,1" newline bitfld.long 0x10 25. "CORRUPT_LCRC_ENABLE,CORRUPT_LCRC_ENABLE is an internally reserved field. Do not use. Note: This register field is sticky." "0,1" newline bitfld.long 0x10 24. "BEACON_ENABLE,BEACON_ENABLE is an internally reserved field. Do not use. Note: This register field is sticky." "0,1" newline hexmask.long.byte 0x10 16.--21. 1. "LINK_CAPABLE,Link Mode Enable. Sets the number of lanes in the link that you want to connect to the link partner. When you have unused lanes in your system then you must change the value in this register to reflect the number of lanes. You must also.." newline hexmask.long.byte 0x10 12.--15. 1. "RSVDP_12,Reserved for future use." newline hexmask.long.byte 0x10 8.--11. 1. "LINK_RATE,LINK_RATE is an internally reserved field. Do not use. Note: This register field is sticky." newline bitfld.long 0x10 7. "FAST_LINK_MODE,Fast Link Mode. Sets all internal LTSSM millisecond timers to Fast Mode for speeding up simulation. Forces the LTSSM training (link initialization) to use shorter time-outs and to link up faster. The default scaling factor can be changed.." "0,1" newline bitfld.long 0x10 6. "LINK_DISABLE,LINK_DISABLE is an internally reserved field. Do not use. Note: This register field is sticky." "0,1" newline bitfld.long 0x10 5. "DLL_LINK_EN,DLL Link Enable. Enables link initialization. When DLL Link Enable =0 the controller does not transmit InitFC DLLPs and does not establish a link. Note: This register field is sticky." "0,1" newline rbitfld.long 0x10 4. "RSVDP_4,Reserved for future use." "0,1" newline bitfld.long 0x10 3. "RESET_ASSERT,Reset Assert. Triggers a recovery and forces the LTSSM to the hot reset state (downstream port only). Note: This register field is sticky." "0,1" newline bitfld.long 0x10 2. "LOOPBACK_ENABLE,Loopback Enable. Turns on loopback. For more details see 'Loopback'. For M-PCIe to force the master to enter Digital Loopback mode you must set this field to '1' during Configuration.start state(initial discovery/configuration). M-PCIe.." "0,1" newline bitfld.long 0x10 1. "SCRAMBLE_DISABLE,Scramble Disable. Turns off data scrambling. Note: This register field is sticky." "0,1" newline bitfld.long 0x10 0. "VENDOR_SPECIFIC_DLLP_REQ,Vendor Specific DLLP Request. When software writes a '1' to this bit the controller transmits the DLLP contained in the VENDOR_SPEC_DLLP field of VENDOR_SPEC_DLLP_OFF. Reading from this self-clearing register field always.." "0,1" line.long 0x14 "LANE_SKEW_OFF,Lane Skew Register." bitfld.long 0x14 31. "DISABLE_LANE_TO_LANE_DESKEW,Disable Lane-to-Lane Deskew. Causes the controller to disable the internal Lane-to-Lane deskew logic. Note: This register field is sticky." "0,1" newline hexmask.long.byte 0x14 27.--30. 1. "IMPLEMENT_NUM_LANES,Implementation-specific Number of Lanes. Set the implementation-specific number of lanes. Allowed values are: - 4'b0000: 1 lane - 4'b0001: 2 lanes - 4'b0011: 4 lanes - 4'b0111: 8 lanes - 4'b1111: 16 lanes The number of lanes to be.." newline bitfld.long 0x14 26. "ELASTIC_BUFFER_MODE,Selects Elasticity Buffer operating mode: 0: Nominal Half Full Buffer mode 1: Nominal Empty Buffer Mode Note: This register field is sticky." "Nominal Half Full Buffer mode,Nominal Empty Buffer Mode" newline bitfld.long 0x14 25. "ACK_NAK_DISABLE,Ack/Nak Disable. Prevents the controller from sending ACK and NAK DLLPs. Note: This register field is sticky." "0,1" newline bitfld.long 0x14 24. "FLOW_CTRL_DISABLE,Flow Control Disable. Prevents the controller from sending FC DLLPs. Note: This register field is sticky." "0,1" newline hexmask.long.tbyte 0x14 0.--23. 1. "INSERT_LANE_SKEW,INSERT_LANE_SKEW is an internally reserved field. Do not use. Note: This register field is sticky." line.long 0x18 "TIMER_CTRL_MAX_FUNC_NUM_OFF,Timer Control and Max Function Number Register." rbitfld.long 0x18 31. "RSVDP_31,Reserved for future use." "0,1" newline bitfld.long 0x18 29.--30. "FAST_LINK_SCALING_FACTOR,Fast Link Timer Scaling Factor. Sets the scaling factor of LTSSM timer when FAST_LINK_MODE field in PORT_LINK_CTRL_OFF is set to '1'. - 0: Scaling Factor is 1024 (1ms is 1us *a) - 1: Scaling Factor is 256 (1ms is 4us) - 2:.." "Scaling Factor is 1024,Scaling Factor is 256,Scaling Factor is 64,Scaling Factor is 16" newline hexmask.long.byte 0x18 24.--28. 1. "UPDATE_FREQ_TIMER,UPDATE_FREQ_TIMER is an internally reserved field. Do not use. Note: This register field is sticky." newline hexmask.long.byte 0x18 19.--23. 1. "TIMER_MOD_ACK_NAK,Ack Latency Timer Modifier. Increases the timer value for the Ack latency timer in increments of 64 clock cycles. A value of '0' represents no modification to the timer value. For more details see the ROUND_TRIP_LATENCY_TIME_LIMIT.." newline hexmask.long.byte 0x18 14.--18. 1. "TIMER_MOD_REPLAY_TIMER,Replay Timer Limit Modifier. Increases the time-out value for the replay timer in increments of 64 clock cycles at Gen1 or Gen2 speed and in increments of 256 clock cycles at Gen3 speed. A value of '0' represents no modification.." newline hexmask.long.byte 0x18 8.--13. 1. "RSVDP_8,Reserved for future use." newline hexmask.long.byte 0x18 0.--7. 1. "MAX_FUNC_NUM,Maximum function number that can be used in a request. Configuration requests targeted at function numbers above this value are returned with UR (unsupported request). Note: This register field is sticky." line.long 0x1C "SYMBOL_TIMER_FILTER_1_OFF,Symbol Timer Register and Filter Mask 1 Register. The Filter Mask 1 Register modifies the RADM filtering and error handling rules. For more details. see the 'Receive Filtering' section. In each case. '0' applies the associated.." hexmask.long.word 0x1C 16.--31. 1. "MASK_RADM_1,Filter Mask 1. The Filter Mask 1 Register modifies the RADM filtering and error handling rules. For more details see the 'Receive Filtering' section. In each case '0' applies the associated filtering rule and '1' masks the associated.." newline bitfld.long 0x1C 15. "DISABLE_FC_WD_TIMER,Disable FC Watchdog Timer. Note: This register field is sticky." "0,1" newline hexmask.long.byte 0x1C 11.--14. 1. "EIDLE_TIMER,EIDLE_TIMER is an internally reserved field. Do not use. Note: This register field is sticky." newline hexmask.long.word 0x1C 0.--10. 1. "SKP_INT_VAL,SKP Interval Value. The number of symbol times to wait between transmitting SKP ordered sets. Note that the controller actually waits the number of symbol times in this register plus 1 between transmitting SKP ordered sets. Your application.." line.long 0x20 "FILTER_MASK_2_OFF,Filter Mask 2 Register. This register modifies the RADM filtering and error handling rules. For more details. see the 'Receive Filtering' section. In each case. '0' applies the associated filtering rule and '1' masks the associated.." hexmask.long 0x20 0.--31. 1. "MASK_RADM_2,Filter Mask 2. This field modifies the RADM filtering and error handling rules. For more details see the 'Receive Filtering' section. In each case '0' applies the associated filtering rule and '1' masks the associated filtering rule." line.long 0x24 "AMBA_MUL_OB_DECOMP_NP_SUB_REQ_CTRL_OFF,AMBA Multiple Outbound Decomposed NP SubRequests Control Register." hexmask.long 0x24 1.--31. 1. "RSVDP_1,Reserved for future use." newline bitfld.long 0x24 0. "OB_RD_SPLIT_BURST_EN,Enable AMBA Multiple Outbound Decomposed NP SubRequests. This bit when set to '0' disables the possibility of having multiple outstanding non-posted requests that were derived from decomposition of an outbound AMBA request. For more.." "0,1" rgroup.long (0x28+0x700)++0x13 line.long 0x0 "PL_DEBUG0_OFF,Debug Register 0" hexmask.long 0x0 0.--31. 1. "DEB_REG_0,The value on cxpl_debug_info[31:0]." line.long 0x4 "PL_DEBUG1_OFF,Debug Register 1" hexmask.long 0x4 0.--31. 1. "DEB_REG_1,The value on cxpl_debug_info[63:32]." line.long 0x8 "TX_P_FC_CREDIT_STATUS_OFF,Transmit Posted FC Credit Status" hexmask.long.word 0x8 20.--31. 1. "RSVDP_TX_P_FC_CREDIT_STATUS,Reserved for future use." newline hexmask.long.byte 0x8 12.--19. 1. "TX_P_HEADER_FC_CREDIT,Transmit Posted Header FC Credits. The posted Header credits advertised by the receiver at the other end of the link updated with each UpdateFC DLLP. Default value depends on the number of advertised credits for header and data.." newline hexmask.long.word 0x8 0.--11. 1. "TX_P_DATA_FC_CREDIT,Transmit Posted Data FC Credits. The posted Data credits advertised by the receiver at the other end of the link updated with each UpdateFC DLLP. Default value depends on the number of advertised credits for header and data Scaled.." line.long 0xC "TX_NP_FC_CREDIT_STATUS_OFF,Transmit Non-Posted FC Credit Status" hexmask.long.word 0xC 20.--31. 1. "RSVDP_TX_NP_FC_CREDIT_STATUS,Reserved for future use." newline hexmask.long.byte 0xC 12.--19. 1. "TX_NP_HEADER_FC_CREDIT,Transmit Non-Posted Header FC Credits. The non-posted Header credits advertised by the receiver at the other end of the link updated with each UpdateFC DLLP. Default value depends on the number of advertised credits for header and.." newline hexmask.long.word 0xC 0.--11. 1. "TX_NP_DATA_FC_CREDIT,Transmit Non-Posted Data FC Credits. The non-posted Data credits advertised by the receiver at the other end of the link updated with each UpdateFC DLLP. Default value depends on the number of advertised credits for header and data.." line.long 0x10 "TX_CPL_FC_CREDIT_STATUS_OFF,Transmit Completion FC Credit Status" hexmask.long.word 0x10 20.--31. 1. "RSVDP_TX_CPL_FC_CREDIT_STATUS,Reserved for future use." newline hexmask.long.byte 0x10 12.--19. 1. "TX_CPL_HEADER_FC_CREDIT,Transmit Completion Header FC Credits. The Completion Header credits advertised by the receiver at the other end of the link updated with each UpdateFC DLLP. Default value depends on the number of advertised credits for header.." newline hexmask.long.word 0x10 0.--11. 1. "TX_CPL_DATA_FC_CREDIT,Transmit Completion Data FC Credits. The Completion Data credits advertised by the receiver at the other end of the link updated with each UpdateFC DLLP. Default value depends on the number of advertised credits for header and data.." group.long (0x3C+0x700)++0x3 line.long 0x0 "QUEUE_STATUS_OFF,Queue Status" bitfld.long 0x0 31. "TIMER_MOD_FLOW_CONTROL_EN,FC Latency Timer Override Enable. When this bit is set the value from the 'FC Latency Timer Override Value' field in this register will override the FC latency timer value that the controller calculates according to the PCIe.." "0,1" newline rbitfld.long 0x0 29.--30. "RSVDP_29,Reserved for future use." "0,1,2,3" newline hexmask.long.word 0x0 16.--28. 1. "TIMER_MOD_FLOW_CONTROL,FC Latency Timer Override Value. When you set the 'FC Latency Timer Override Enable' in this register the value in this field will override the FC latency timer value that the controller calculates according to the PCIe.." newline rbitfld.long 0x0 13. "RX_SERIALIZATION_Q_NON_EMPTY,Receive Serialization Queue Not Empty. Indicates there is data in the serialization queue." "0,1" newline hexmask.long.word 0x0 4.--12. 1. "RSVDP_4,Reserved for future use." newline bitfld.long 0x0 3. "RX_QUEUE_OVERFLOW,Receive Credit Queue Overflow. Indicates insufficient buffer space available to write to the P/NP/CPL credit queue." "0,1" newline rbitfld.long 0x0 2. "RX_QUEUE_NON_EMPTY,Receive Credit Queue Not Empty. Indicates there is data in one or more of the receive buffers." "0,1" newline rbitfld.long 0x0 1. "TX_RETRY_BUFFER_NE,Transmit Retry Buffer Not Empty. Indicates that there is data in the transmit retry buffer." "0,1" newline rbitfld.long 0x0 0. "RX_TLP_FC_CREDIT_NON_RETURN,Received TLP FC Credits Not Returned. Indicates that the controller has received a TLP but has not yet sent an UpdateFC DLLP indicating that the credits for that TLP have been restored by the receiver at the other end of the.." "0,1" rgroup.long (0x40+0x700)++0x7 line.long 0x0 "VC_TX_ARBI_1_OFF,VC Transmit Arbitration Register 1" hexmask.long.byte 0x0 24.--31. 1. "WRR_WEIGHT_VC_3,WRR Weight for VC3. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R" newline hexmask.long.byte 0x0 16.--23. 1. "WRR_WEIGHT_VC_2,WRR Weight for VC2. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R" newline hexmask.long.byte 0x0 8.--15. 1. "WRR_WEIGHT_VC_1,WRR Weight for VC1. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R" newline hexmask.long.byte 0x0 0.--7. 1. "WRR_WEIGHT_VC_0,WRR Weight for VC0. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R" line.long 0x4 "VC_TX_ARBI_2_OFF,VC Transmit Arbitration Register 2" hexmask.long.byte 0x4 24.--31. 1. "WRR_WEIGHT_VC_7,WRR Weight for VC7. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R" newline hexmask.long.byte 0x4 16.--23. 1. "WRR_WEIGHT_VC_6,WRR Weight for VC6. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R" newline hexmask.long.byte 0x4 8.--15. 1. "WRR_WEIGHT_VC_5,WRR Weight for VC5. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R" newline hexmask.long.byte 0x4 0.--7. 1. "WRR_WEIGHT_VC_4,WRR Weight for VC4. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R" group.long (0x48+0x700)++0xB line.long 0x0 "VC0_P_RX_Q_CTRL_OFF,Segmented-Buffer VC0 Posted Receive Queue Control." bitfld.long 0x0 31. "VC_ORDERING_RX_Q,VC Ordering for Receive Queues. Determines the VC ordering rule for the receive queues used only in the segmented-buffer configuration: - 1: Strict ordering higher numbered VCs have higher priority - 0: Round robin Note: This register.." "Round robin,Strict ordering" newline bitfld.long 0x0 30. "TLP_TYPE_ORDERING_VC0,TLP Type Ordering for VC0. Determines the TLP type ordering rule for VC0 receive queues used only in the segmented-buffer configuration: - 1: PCIe ordering rules (recommended) - 0: Strict ordering: posted completion then.." "Strict ordering: posted,PCIe ordering rules" newline bitfld.long 0x0 28.--29. "RESERVED5,Reserved. Note: This register field is sticky." "0,1,2,3" newline bitfld.long 0x0 26.--27. "VC0_P_DATA_SCALE,VC0 Scale Posted Data Credites. Note: This register field is sticky." "0,1,2,3" newline bitfld.long 0x0 24.--25. "VC0_P_HDR_SCALE,VC0 Scale Posted Header Credites. Note: This register field is sticky." "0,1,2,3" newline bitfld.long 0x0 21.--23. "VC0_P_TLP_Q_MODE,Reserved. Note: This register field is sticky." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 20. "RESERVED4,Reserved. Note: This register field is sticky." "0,1" newline hexmask.long.byte 0x0 12.--19. 1. "VC0_P_HEADER_CREDIT,VC0 Posted Header Credits. The number of initial posted header credits for VC0 used only in the segmented-buffer configuration. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R (sticky) Note: This.." newline hexmask.long.word 0x0 0.--11. 1. "VC0_P_DATA_CREDIT,VC0 Posted Data Credits. The number of initial posted data credits for VC0 used only in the segmented-buffer configuration. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R (sticky) Note: This.." line.long 0x4 "VC0_NP_RX_Q_CTRL_OFF,Segmented-Buffer VC0 Non-Posted Receive Queue Control." hexmask.long.byte 0x4 28.--31. 1. "RESERVED7,Reserved. Note: This register field is sticky." newline bitfld.long 0x4 26.--27. "VC0_NP_DATA_SCALE,VC0 Scale Non-Posted Data Credites. Note: This register field is sticky." "0,1,2,3" newline bitfld.long 0x4 24.--25. "VC0_NP_HDR_SCALE,VC0 Scale Non-Posted Header Credites. Note: This register field is sticky." "0,1,2,3" newline bitfld.long 0x4 21.--23. "VC0_NP_TLP_Q_MODE,Reserved. Note: This register field is sticky." "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 20. "RESERVED6,Reserved. Note: This register field is sticky." "0,1" newline hexmask.long.byte 0x4 12.--19. 1. "VC0_NP_HEADER_CREDIT,VC0 Non-Posted Header Credits. The number of initial non-posted header credits for VC0 used only in the segmented-buffer configuration. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R (sticky).." newline hexmask.long.word 0x4 0.--11. 1. "VC0_NP_DATA_CREDIT,VC0 Non-Posted Data Credits. The number of initial non-posted data credits for VC0 used only in the segmented-buffer configuration. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R (sticky) Note:.." line.long 0x8 "VC0_CPL_RX_Q_CTRL_OFF,Segmented-Buffer VC0 Completion Receive Queue Control." hexmask.long.byte 0x8 28.--31. 1. "RESERVED9,Reserved. Note: This register field is sticky." newline bitfld.long 0x8 26.--27. "VC0_CPL_DATA_SCALE,VC0 Scale CPL Data Credites. Note: This register field is sticky." "0,1,2,3" newline bitfld.long 0x8 24.--25. "VC0_CPL_HDR_SCALE,VC0 Scale CPL Header Credites. Note: This register field is sticky." "0,1,2,3" newline bitfld.long 0x8 21.--23. "VC0_CPL_TLP_Q_MODE,Reserved. Note: This register field is sticky." "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 20. "RESERVED8,Reserved. Note: This register field is sticky." "0,1" newline hexmask.long.byte 0x8 12.--19. 1. "VC0_CPL_HEADER_CREDIT,VC0 Completion Header Credits. The number of initial Completion header credits for VC0 used only in the segmented-buffer configuration. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R (sticky).." newline hexmask.long.word 0x8 0.--11. 1. "VC0_CPL_DATA_CREDIT,VC0 Completion Data Credits. The number of initial Completion data credits for VC0 used only in the segmented-buffer configuration. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R (sticky) Note:.." group.long (0x10C+0x700)++0x3 line.long 0x0 "GEN2_CTRL_OFF,This register is used to control various functions of the controller related to link training. lane reversal. and equalization." rbitfld.long 0x0 31. "RSVDP_31,Reserved for future use." "0,1" newline bitfld.long 0x0 30. "FORCE_LANE_FLIP,Enable to force the LANE_UNDER_TEST physical lane flips to logical lane 0. All the other physical lanes are turned off. The LINK_CAPABLE register must be set to 1 and only x1 link can be formed if the FORCE_LANE_FLIP register is set to 1." "0,1" newline hexmask.long.byte 0x0 24.--27. 1. "LANE_UNDER_TEST,The Lane Under Test is the lane for Forced Lane Flip or for Loopback Eq. The value is from 0 to CX_NL. Only one lane is configured each time. The default of this field is the CX_DEFAULT_LANE_UNDER_TEST configuration parameter. This field.." newline rbitfld.long 0x0 22.--23. "RSVDP_22,Reserved for future use." "0,1,2,3" newline bitfld.long 0x0 21. "GEN1_EI_INFERENCE,Electrical Idle Inference Mode at Gen1 Rate. Programmable mode to determine inferred electrical idle (EI) in Recovery.Speed or Loopback.Active (as slave) state at Gen1 speed by looking for a '1' value on RxElecIdle instead of looking.." "Use RxElecIdle signal to infer Electrical Idle,Use RxValid signal to infer Electrical Idle" newline bitfld.long 0x0 20. "SEL_DEEMPHASIS,Used to set the de-emphasis level for upstream ports. This bit selects the level of de-emphasis the link operates at. - 0: -6 dB - 1: -3.5 dB This field is reserved (fixed to '0') for M-PCIe. Note: The access attributes of this field are.." "0,1" newline bitfld.long 0x0 19. "CONFIG_TX_COMP_RX,Config Tx Compliance Receive Bit. When set to 1 signals LTSSM to transmit TS ordered sets with the compliance receive bit assert (equal to '1'). This field is reserved (fixed to '0') for M-PCIe. Note: The access attributes of this.." "0,1" newline bitfld.long 0x0 18. "CONFIG_PHY_TX_CHANGE,Config PHY Tx Swing. Controls the PHY transmitter voltage swing level. The controller drives the mac_phy_txswing output from this register bit field. - 0: Full Swing - 1: Low Swing This field is reserved (fixed to '0') for M-PCIe." "Full Swing,Low Swing" newline bitfld.long 0x0 17. "DIRECT_SPEED_CHANGE,Directed Speed Change. Writing '1' to this field instructs the LTSSM to initiate a speed change to Gen2 or Gen3 after the link is initialized at Gen1 speed. When the speed change occurs the controller will clear the contents of this.." "0,1" newline bitfld.long 0x0 16. "AUTO_LANE_FLIP_CTRL_EN,Enable Auto flipping of the lanes. You must set the CX_AUTO_LANE_FLIP_CTRL_EN configuration parameter to include the hardware for this feature in the controller. For more details see the 'Lane Reversal' appendix in the Databook." "0,1" newline bitfld.long 0x0 13.--15. "PRE_DET_LANE,Predetermined Lane for Auto Flip. This field defines which physical lane is connected to logical Lane0 by the flip operation performed in Detect. This field is used to restrict the receiver detect procedure to a particular lane when the.." "LANE0,LANE1,LANE3,LANE7,LANE15,?,?,?" newline hexmask.long.byte 0x0 8.--12. 1. "NUM_OF_LANES,Predetermined Number of Lanes. Defines the number of lanes which are connected and not bad. Used to limit the effective link width to ignore 'broken' or 'unused' lanes that detect a receiver. Indicates the number of lanes to check for exit.." newline hexmask.long.byte 0x0 0.--7. 1. "FAST_TRAINING_SEQ,Sets the Number of Fast Training Sequences (N_FTS) that the controller advertises as its N_FTS during Gen2 or Gen3 link training. This value is used to inform the link partner about the PHY's ability to recover synchronization after a.." rgroup.long (0x110+0x700)++0x3 line.long 0x0 "PHY_STATUS_OFF,PHY Status Register. Memory mapped register from phy_cfg_status GPIO input pins." hexmask.long 0x0 0.--31. 1. "PHY_STATUS,PHY Status. Data received directly from the phy_cfg_status bus. These is a GPIO register reflecting the values on the static phy_cfg_status input signals. The usage is left completely to the user and does not in any way influence controller.." group.long (0x114+0x700)++0x3 line.long 0x0 "PHY_CONTROL_OFF,PHY Control Register. Memory mapped register to cfg_phy_control GPIO output pins." hexmask.long 0x0 0.--31. 1. "PHY_CONTROL,PHY Control. Data sent directly to the cfg_phy_control bus. These is a GPIO register driving the values on the static cfg_phy_control output signals. The usage is left completely to the user and does not in any way influence controller.." group.long (0x11C+0x700)++0x77 line.long 0x0 "TRGT_MAP_CTRL_OFF,Programmable Target Map Control Register." hexmask.long.word 0x0 21.--31. 1. "TARGET_MAP_RESERVED_21_31,Reserved. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R (sticky)" newline hexmask.long.byte 0x0 16.--20. 1. "TARGET_MAP_INDEX,The number of the PF Function on which the Target Values are set. This register does not respect the Byte Enable setting. any write will affect all register bits." newline rbitfld.long 0x0 13.--15. "TARGET_MAP_RESERVED_13_15,Reserved. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R (sticky)" "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x0 7.--12. 1. "TARGET_MAP_VF,Target Values for each BAR on the VF Function selected by the index number. This register does not respect the Byte Enable setting. any write will affect all register bits." newline bitfld.long 0x0 6. "TARGET_MAP_ROM,Target Value for the ROM page of the PF Function selected by the index number. This register does not respect the Byte Enable setting. any write will affect all register bits." "0,1" newline hexmask.long.byte 0x0 0.--5. 1. "TARGET_MAP_PF,Target Values for each BAR on the PF Function selected by the index number. This register does not respect the Byte Enable setting. any write will affect all register bits." line.long 0x4 "MSI_CTRL_ADDR_OFF,Integrated MSI Reception Module (iMRM) Address Register." hexmask.long 0x4 0.--31. 1. "MSI_CTRL_ADDR,Integrated MSI Reception Module Address. System specified address for MSI memory write transaction termination. Within the AXI Bridge every received Memory Write request is examined to see if it targets the MSI Address that has been.." line.long 0x8 "MSI_CTRL_UPPER_ADDR_OFF,Integrated MSI Reception Module Upper Address Register." hexmask.long 0x8 0.--31. 1. "MSI_CTRL_UPPER_ADDR,Integrated MSI Reception Module Upper Address. System specified upper address for MSI memory write transaction termination. Allows functions to support a 64-bit MSI address. Note: This register field is sticky." line.long 0xC "MSI_CTRL_INT_0_EN_OFF,Integrated MSI Reception Module Interrupt#i Enable Register." hexmask.long 0xC 0.--31. 1. "MSI_CTRL_INT_0_EN,MSI Interrupt#i Enable. Specifies which interrupts are enabled. When an MSI is received from a disabled interrupt no status bit gets set in MSI controller interrupt status register. Each bit corresponds to a single MSI Interrupt.." line.long 0x10 "MSI_CTRL_INT_0_MASK_OFF,Integrated MSI Reception Module Interrupt#i Mask Register." hexmask.long 0x10 0.--31. 1. "MSI_CTRL_INT_0_MASK,MSI Interrupt#i Mask. Allows enabled interrupts to be masked. When an MSI is received for a masked interrupt the corresponding status bit gets set in the interrupt status register but the msi_ctrl_int output is not set HIGH. Each bit.." line.long 0x14 "MSI_CTRL_INT_0_STATUS_OFF,Integrated MSI Reception Module Interrupt#i Status Register." hexmask.long 0x14 0.--31. 1. "MSI_CTRL_INT_0_STATUS,MSI Interrupt#i Status. When an MSI is detected for EP#i one bit in this register is set. The decoding of the data payload of the MSI Memory Write request determines which bit gets set. A status is bit is cleared by writing a 1 to.." line.long 0x18 "MSI_CTRL_INT_1_EN_OFF,Integrated MSI Reception Module Interrupt#i Enable Register." hexmask.long 0x18 0.--31. 1. "MSI_CTRL_INT_1_EN,MSI Interrupt#i Enable. Specifies which interrupts are enabled. When an MSI is received from a disabled interrupt no status bit gets set in MSI controller interrupt status register. Each bit corresponds to a single MSI Interrupt.." line.long 0x1C "MSI_CTRL_INT_1_MASK_OFF,Integrated MSI Reception Module Interrupt#i Mask Register." hexmask.long 0x1C 0.--31. 1. "MSI_CTRL_INT_1_MASK,MSI Interrupt#i Mask. Allows enabled interrupts to be masked. When an MSI is received for a masked interrupt the corresponding status bit gets set in the interrupt status register but the msi_ctrl_int output is not set HIGH. Each bit.." line.long 0x20 "MSI_CTRL_INT_1_STATUS_OFF,Integrated MSI Reception Module Interrupt#i Status Register." hexmask.long 0x20 0.--31. 1. "MSI_CTRL_INT_1_STATUS,MSI Interrupt#i Status. When an MSI is detected for EP#i one bit in this register is set. The decoding of the data payload of the MSI Memory Write request determines which bit gets set. A status is bit is cleared by writing a 1 to.." line.long 0x24 "MSI_CTRL_INT_2_EN_OFF,Integrated MSI Reception Module Interrupt#i Enable Register." hexmask.long 0x24 0.--31. 1. "MSI_CTRL_INT_2_EN,MSI Interrupt#i Enable. Specifies which interrupts are enabled. When an MSI is received from a disabled interrupt no status bit gets set in MSI controller interrupt status register. Each bit corresponds to a single MSI Interrupt.." line.long 0x28 "MSI_CTRL_INT_2_MASK_OFF,Integrated MSI Reception Module Interrupt#i Mask Register." hexmask.long 0x28 0.--31. 1. "MSI_CTRL_INT_2_MASK,MSI Interrupt#i Mask. Allows enabled interrupts to be masked. When an MSI is received for a masked interrupt the corresponding status bit gets set in the interrupt status register but the msi_ctrl_int output is not set HIGH. Each bit.." line.long 0x2C "MSI_CTRL_INT_2_STATUS_OFF,Integrated MSI Reception Module Interrupt#i Status Register." hexmask.long 0x2C 0.--31. 1. "MSI_CTRL_INT_2_STATUS,MSI Interrupt#i Status. When an MSI is detected for EP#i one bit in this register is set. The decoding of the data payload of the MSI Memory Write request determines which bit gets set. A status is bit is cleared by writing a 1 to.." line.long 0x30 "MSI_CTRL_INT_3_EN_OFF,Integrated MSI Reception Module Interrupt#i Enable Register." hexmask.long 0x30 0.--31. 1. "MSI_CTRL_INT_3_EN,MSI Interrupt#i Enable. Specifies which interrupts are enabled. When an MSI is received from a disabled interrupt no status bit gets set in MSI controller interrupt status register. Each bit corresponds to a single MSI Interrupt.." line.long 0x34 "MSI_CTRL_INT_3_MASK_OFF,Integrated MSI Reception Module Interrupt#i Mask Register." hexmask.long 0x34 0.--31. 1. "MSI_CTRL_INT_3_MASK,MSI Interrupt#i Mask. Allows enabled interrupts to be masked. When an MSI is received for a masked interrupt the corresponding status bit gets set in the interrupt status register but the msi_ctrl_int output is not set HIGH. Each bit.." line.long 0x38 "MSI_CTRL_INT_3_STATUS_OFF,Integrated MSI Reception Module Interrupt#i Status Register." hexmask.long 0x38 0.--31. 1. "MSI_CTRL_INT_3_STATUS,MSI Interrupt#i Status. When an MSI is detected for EP#i one bit in this register is set. The decoding of the data payload of the MSI Memory Write request determines which bit gets set. A status is bit is cleared by writing a 1 to.." line.long 0x3C "MSI_CTRL_INT_4_EN_OFF,Integrated MSI Reception Module Interrupt#i Enable Register." hexmask.long 0x3C 0.--31. 1. "MSI_CTRL_INT_4_EN,MSI Interrupt#i Enable. Specifies which interrupts are enabled. When an MSI is received from a disabled interrupt no status bit gets set in MSI controller interrupt status register. Each bit corresponds to a single MSI Interrupt.." line.long 0x40 "MSI_CTRL_INT_4_MASK_OFF,Integrated MSI Reception Module Interrupt#i Mask Register." hexmask.long 0x40 0.--31. 1. "MSI_CTRL_INT_4_MASK,MSI Interrupt#i Mask. Allows enabled interrupts to be masked. When an MSI is received for a masked interrupt the corresponding status bit gets set in the interrupt status register but the msi_ctrl_int output is not set HIGH. Each bit.." line.long 0x44 "MSI_CTRL_INT_4_STATUS_OFF,Integrated MSI Reception Module Interrupt#i Status Register." hexmask.long 0x44 0.--31. 1. "MSI_CTRL_INT_4_STATUS,MSI Interrupt#i Status. When an MSI is detected for EP#i one bit in this register is set. The decoding of the data payload of the MSI Memory Write request determines which bit gets set. A status is bit is cleared by writing a 1 to.." line.long 0x48 "MSI_CTRL_INT_5_EN_OFF,Integrated MSI Reception Module Interrupt#i Enable Register." hexmask.long 0x48 0.--31. 1. "MSI_CTRL_INT_5_EN,MSI Interrupt#i Enable. Specifies which interrupts are enabled. When an MSI is received from a disabled interrupt no status bit gets set in MSI controller interrupt status register. Each bit corresponds to a single MSI Interrupt.." line.long 0x4C "MSI_CTRL_INT_5_MASK_OFF,Integrated MSI Reception Module Interrupt#i Mask Register." hexmask.long 0x4C 0.--31. 1. "MSI_CTRL_INT_5_MASK,MSI Interrupt#i Mask. Allows enabled interrupts to be masked. When an MSI is received for a masked interrupt the corresponding status bit gets set in the interrupt status register but the msi_ctrl_int output is not set HIGH. Each bit.." line.long 0x50 "MSI_CTRL_INT_5_STATUS_OFF,Integrated MSI Reception Module Interrupt#i Status Register." hexmask.long 0x50 0.--31. 1. "MSI_CTRL_INT_5_STATUS,MSI Interrupt#i Status. When an MSI is detected for EP#i one bit in this register is set. The decoding of the data payload of the MSI Memory Write request determines which bit gets set. A status is bit is cleared by writing a 1 to.." line.long 0x54 "MSI_CTRL_INT_6_EN_OFF,Integrated MSI Reception Module Interrupt#i Enable Register." hexmask.long 0x54 0.--31. 1. "MSI_CTRL_INT_6_EN,MSI Interrupt#i Enable. Specifies which interrupts are enabled. When an MSI is received from a disabled interrupt no status bit gets set in MSI controller interrupt status register. Each bit corresponds to a single MSI Interrupt.." line.long 0x58 "MSI_CTRL_INT_6_MASK_OFF,Integrated MSI Reception Module Interrupt#i Mask Register." hexmask.long 0x58 0.--31. 1. "MSI_CTRL_INT_6_MASK,MSI Interrupt#i Mask. Allows enabled interrupts to be masked. When an MSI is received for a masked interrupt the corresponding status bit gets set in the interrupt status register but the msi_ctrl_int output is not set HIGH. Each bit.." line.long 0x5C "MSI_CTRL_INT_6_STATUS_OFF,Integrated MSI Reception Module Interrupt#i Status Register." hexmask.long 0x5C 0.--31. 1. "MSI_CTRL_INT_6_STATUS,MSI Interrupt#i Status. When an MSI is detected for EP#i one bit in this register is set. The decoding of the data payload of the MSI Memory Write request determines which bit gets set. A status is bit is cleared by writing a 1 to.." line.long 0x60 "MSI_CTRL_INT_7_EN_OFF,Integrated MSI Reception Module Interrupt#i Enable Register." hexmask.long 0x60 0.--31. 1. "MSI_CTRL_INT_7_EN,MSI Interrupt#i Enable. Specifies which interrupts are enabled. When an MSI is received from a disabled interrupt no status bit gets set in MSI controller interrupt status register. Each bit corresponds to a single MSI Interrupt.." line.long 0x64 "MSI_CTRL_INT_7_MASK_OFF,Integrated MSI Reception Module Interrupt#i Mask Register." hexmask.long 0x64 0.--31. 1. "MSI_CTRL_INT_7_MASK,MSI Interrupt#i Mask. Allows enabled interrupts to be masked. When an MSI is received for a masked interrupt the corresponding status bit gets set in the interrupt status register but the msi_ctrl_int output is not set HIGH. Each bit.." line.long 0x68 "MSI_CTRL_INT_7_STATUS_OFF,Integrated MSI Reception Module Interrupt#i Status Register." hexmask.long 0x68 0.--31. 1. "MSI_CTRL_INT_7_STATUS,MSI Interrupt#i Status. When an MSI is detected for EP#i one bit in this register is set. The decoding of the data payload of the MSI Memory Write request determines which bit gets set. A status is bit is cleared by writing a 1 to.." line.long 0x6C "MSI_GPIO_IO_OFF,Integrated MSI Reception Module General Purpose IO Register." hexmask.long 0x6C 0.--31. 1. "MSI_GPIO_REG,MSI GPIO Register. The contents of this register drives the top-level GPIO msi_ctrl_io[31:0] Note: This register field is sticky." line.long 0x70 "CLOCK_GATING_CTRL_OFF,This register enables you to disable dynamic clock gating. By default dynamic clock gating is on. allowing the controller to autonomously enable and disable its clocks. The clock gating is performed in the clock and reset module." hexmask.long 0x70 2.--31. 1. "RSVDP_2,Reserved for future use." newline bitfld.long 0x70 1. "AXI_CLK_GATING_EN,AXI Clock Gating Enable. This register enables the AXI Bridge to autonomously enable and disable the AXI Master clock the AXI Slave clock and the AXI DBI slave clock. The DWC_pcie_clk_rst.v module provides the gated clock.." "Disable,Enable" newline bitfld.long 0x70 0. "RADM_CLK_GATING_EN,RADM Clock Gating Enable. This register if set enables the RADM to autonomously enable and disable its clock. The DWC_pcie_clk_rst.v module provides the gated clock radm_clk_g to the RADM and is enabled when the controllers clock.." "Disable,Enable" line.long 0x74 "GEN3_RELATED_OFF,Gen3 Control Register. There is no Gen3-specific N_FTS field. The N_FTS field in the 'Link Width and Speed Change Control Register' is used for both Gen2 and Gen3 speed modes. There is no Gen3-specific 'Directed Speed Change' field. The.." hexmask.long.byte 0x74 26.--31. 1. "RSVDP_26,Reserved for future use." newline bitfld.long 0x74 23. "GEN3_EQ_INVREQ_EVAL_DIFF_DISABLE,Eq InvalidRequest and RxEqEval Different Time Assertion Disable. Disable the assertion of Eq InvalidRequest and RxEqEval at different time. Note: When CX_GEN4_SPEED/CX_GEN5_SPEED this register is shared for Gen3 and.." "0,1" newline rbitfld.long 0x74 19.--20. "RSVDP_19,Reserved for future use." "0,1,2,3" newline bitfld.long 0x74 18. "GEN3_DC_BALANCE_DISABLE,DC Balance Disable. Disable DC Balance feature. Note: When CX_GEN4_SPEED/CX_GEN5_SPEED this register is shared for Gen3 and Gen4/Gen5 data rate. Note: This register field is sticky." "0,1" newline bitfld.long 0x74 17. "GEN3_DLLP_XMT_DELAY_DISABLE,DLLP Transmission Delay Disable. Disable delay transmission of DLLPs before equalization. Note: When CX_GEN4_SPEED/CX_GEN5_SPEED this register is shared for Gen3 and Gen4/Gen5 data rate. Note: This register field is sticky." "0,1" newline bitfld.long 0x74 16. "GEN3_EQUALIZATION_DISABLE,Equalization Disable. Disable equalization feature. This bit cannot be changed once the LTSSM starts link training. Note: When CX_GEN4_SPEED/CX_GEN5_SPEED this register is shared for Gen3 and Gen4/Gen5 data rate. Note: This.." "0,1" newline rbitfld.long 0x74 14.--15. "RSVDP_14,Reserved for future use." "0,1,2,3" newline bitfld.long 0x74 13. "RXEQ_RGRDLESS_RXTS,When set to '1' the controller as Gen3 EQ master asserts RxEqEval to instruct the PHY to do Rx adaptation and evaluation after a 500ns timeout from a new preset request. - 0: mac_phy_rxeqeval asserts after 1us and 2 TS1 received from.." "mac_phy_rxeqeval asserts after 1us and 2 TS1..,mac_phy_rxeqeval asserts after 500ns regardless.." newline bitfld.long 0x74 12. "RXEQ_PH01_EN,Rx Equalization Phase 0/Phase 1 Hold Enable. When this bit is set the upstream port holds phase 0 (the downstream port holds phase 1) for 10ms. Holding phase 0 or phase 1 can be used to allow sufficient time for Rx Equalization to be.." "Tx equalization only in phase 2/3,No Tx equalization" newline bitfld.long 0x74 11. "EQ_REDO,Equalization Redo Disable. Disable autonomous mechanism for requesting to redo the equalization process. The received presets or coefficients mismatch in Recovery.RcvrLock after Recovery EQ phases causes the EQ redo requests. If the EQ redo is.." "0,1" newline bitfld.long 0x74 10. "EQ_EIEOS_CNT,Equalization EIEOS Count Reset Disable. Disable requesting reset of EIEOS count during equalization. Note: When CX_GEN4_SPEED/CX_GEN5_SPEED this register is shared for Gen3 and Gen4/Gen5 data rate. Note: This register field is sticky." "0,1" newline bitfld.long 0x74 9. "EQ_PHASE_2_3,Equalization Phase 2 and Phase 3 Disable. This applies to downstream ports only. Note: When CX_GEN4_SPEED/CX_GEN5_SPEED this register is shadow register for Gen3 and Gen4/Gen5 data rate. If RATE_SHADOW_SEL==00b this register is for Gen3.." "0,1" newline bitfld.long 0x74 8. "DISABLE_SCRAMBLER_GEN_3,Disable Scrambler for Gen3 and Gen4 Data Rate. The Gen3 and Gen4 scrambler/descrambler within the controller needs to be disabled when the scrambling function is implemented outside of the controller (for example within the PHY)." "0,1" newline hexmask.long.byte 0x74 1.--7. 1. "RSVDP_1,Reserved for future use." newline bitfld.long 0x74 0. "GEN3_ZRXDC_NONCOMPL,Gen3 Receiver Impedance ZRX-DC Not Compliant. Receivers that operate at 8.0 GT/s with an impedance other than the range defined by the ZRX-DC parameter for 2.5 GT/s (40-60 Ohms) must meet additional behavior requirements in the.." "The receiver complies with the ZRX-DC parameter..,The receiver does not comply with the ZRX-DC.." group.long (0x1A8+0x700)++0x7 line.long 0x0 "GEN3_EQ_CONTROL_OFF,Gen3 EQ Control Register. This register controls equalization for Phase2 in an upstream port (USP). or Phase3 in a downstream port (DSP). M-PCIe doesn't have Conventional PCIe Gen3 feature. The registers of this section do not exist." hexmask.long.byte 0x0 27.--31. 1. "RSVDP_27,Reserved for future use." newline bitfld.long 0x0 26. "GEN3_REQ_SEND_CONSEC_EIEOS_FOR_PSET_MAP,Request controller to send back-to-back EIEOS in Recovery.RcvrLock state until presets to coefficients mapping is complete. - 0: Do not request - 1: request Note: Gen3 and Gen4 share the same register bit and have.." "Do not request,request" newline bitfld.long 0x0 25. "GEN3_EQ_PSET_REQ_AS_COEF,GEN3_EQ_PSET_REQ_AS_COEF is an internally reserved field. Do not use. Note: This register field is sticky." "0,1" newline bitfld.long 0x0 24. "GEN3_EQ_FOM_INC_INITIAL_EVAL,Include Initial FOM. Include or not the FOM feedback from the initial preset evaluation performed in the EQ Master when finding the highest FOM among all preset evaluations. - 0: Do not include - 1: Include Note: When.." "Do not include,Include" newline hexmask.long.word 0x0 8.--23. 1. "GEN3_EQ_PSET_REQ_VEC,Preset Request Vector. Requesting of Presets during the initial part of the EQ Master Phase. Encoding scheme is as follows: Bit [15:0] =0x0: No preset is requested and evaluated in EQ Master Phase. Bit [i] =1: 'Preset=i' is requested.." newline rbitfld.long 0x0 7. "RSVDP_7,Reserved for future use." "0,1" newline bitfld.long 0x0 6. "GEN3_LOWER_RATE_EQ_REDO_ENABLE,Support EQ redo and lower rate change: - 0: not support - 1: support Note: Gen3 and Gen4 share the same register bit and have the same feature. Note: This register field is sticky." "not support,support" newline bitfld.long 0x0 5. "GEN3_EQ_EVAL_2MS_DISABLE,Phase2_3 2 ms Timeout Disable. Determine behavior in Phase2 for USP (Phase3 if DSP) when the PHY does not respond within 2ms to the assertion of RxEqEval: - 0: abort the current evaluation stop any attempt to modify the remote.." "abort the current evaluation,ignore the 2ms timeout and continue as normal" newline bitfld.long 0x0 4. "GEN3_EQ_PHASE23_EXIT_MODE,Behavior After 24 ms Timeout (when optimal settings are not found). For a USP: Determine next LTSSM state from Phase2 after 24ms Timeout - 0: Recovery.Speed - 1: Recovery.Equalization.Phase3 When optimal settings are not found.." "Equalization Phase 3 Successful status bit is..,Recovery" newline hexmask.long.byte 0x0 0.--3. 1. "GEN3_EQ_FB_MODE,Feedback Mode. - 0000b: Direction Change - 0001b: Figure Of Merit - 0010b: Reserved - .....: Reserved - 1111b: Reserved Note: When CX_GEN4_SPEED/CX_GEN5_SPEED this register is a shadow register for Gen3 and Gen4/Gen5 data rate. If.." line.long 0x4 "GEN3_EQ_FB_MODE_DIR_CHANGE_OFF,Gen3 EQ Direction Change Feedback Mode Control Register. Equalization controls to be used in Phase2 (USP) or Phase 3 (DSP). when you set the Feedback Mode in 'Gen3 EQ Control Register' to 'Direction Change.' These fields.." hexmask.long.word 0x4 18.--31. 1. "RSVDP_18,Reserved for future use." newline hexmask.long.byte 0x4 14.--17. 1. "GEN3_EQ_FMDC_MAX_POST_CUSROR_DELTA,Convergence Window Aperture for C+1. Post-cursor coefficients maximum delta within the convergence window depth. Allowed range: 0 1 2 ..15. Note: When CX_GEN4_SPEED/CX_GEN5_SPEED this register is shadow register for.." newline hexmask.long.byte 0x4 10.--13. 1. "GEN3_EQ_FMDC_MAX_PRE_CUSROR_DELTA,Convergence Window Aperture for C-1. Pre-cursor coefficients maximum delta within the convergence window depth. Allowed range: 0 1 2 ..15. Note: When CX_GEN4_SPEED/CX_GEN5_SPEED this register is shadow register for Gen3.." newline hexmask.long.byte 0x4 5.--9. 1. "GEN3_EQ_FMDC_N_EVALS,Convergence Window Depth. Number of consecutive evaluations considered in Phase 2/3 when determining if optimal coefficients have been found. Allowed range: 0 1 2 ..16 up to a maximum of CX_GEN3_EQ_COEFQ_DEPTH. When set to 0 EQ.." newline hexmask.long.byte 0x4 0.--4. 1. "GEN3_EQ_FMDC_T_MIN_PHASE23,Minimum Time (in ms) To Remain in EQ Master Phase. The LTSSM stays in EQ Master phase for at least this amount of time before starting to check for convergence of the coefficients. Allowed values 0 1 ... 24. Note: When.." group.long (0x1B4+0x700)++0x27 line.long 0x0 "ORDER_RULE_CTRL_OFF,Order Rule Control Register." hexmask.long.word 0x0 16.--31. 1. "RSVDP_16,Reserved for future use." newline hexmask.long.byte 0x0 8.--15. 1. "CPL_PASS_P,Completion Passing Posted Ordering Rule Control. Determines if CPL can pass halted P queue. - 0: CPL can not pass P (recommended) - 1: CPL can pass P" newline hexmask.long.byte 0x0 0.--7. 1. "NP_PASS_P,Non-Posted Passing Posted Ordering Rule Control. Determines if NP can pass halted P queue. - 0 : NP can not pass P (recommended). - 1 : NP can pass P" line.long 0x4 "PIPE_LOOPBACK_CONTROL_OFF,PIPE Loopback Control Register." bitfld.long 0x4 31. "PIPE_LOOPBACK,PIPE Loopback Enable. Indicates RMMI Loopback if M-PCIe. Note: This register field is sticky." "0,1" newline hexmask.long.byte 0x4 27.--30. 1. "RSVDP_27,Reserved for future use." newline bitfld.long 0x4 24.--26. "RXSTATUS_VALUE,RXSTATUS_VALUE is an internally reserved field. Do not use." "0,1,2,3,4,5,6,7" newline rbitfld.long 0x4 22.--23. "RSVDP_22,Reserved for future use." "0,1,2,3" newline hexmask.long.byte 0x4 16.--21. 1. "RXSTATUS_LANE,RXSTATUS_LANE is an internally reserved field. Do not use. Note: This register field is sticky." newline hexmask.long.word 0x4 0.--15. 1. "LPBK_RXVALID,LPBK_RXVALID is an internally reserved field. Do not use. Note: This register field is sticky." line.long 0x8 "MISC_CONTROL_1_OFF,DBI Read-Only Write Enable Register." hexmask.long.word 0x8 22.--31. 1. "RSVDP_22,Reserved for future use." newline bitfld.long 0x8 21. "P2P_ERR_RPT_CTRL,Determines whether to track completion of transmitted Non-Posted TLPs in P2P mode. - 0: Do not track completion - 1: Track completion Note: This register field is sticky." "Do not track completion,Track completion" newline bitfld.long 0x8 20. "P2P_TRACK_CPL_TO_REG,Determines whether to enable Peer to Peer (P2P) error reporting. - 0: Disable P2P error reporting - 1: Enable P2P error reporting Note: This register field is sticky." "Disable P2P error reporting,Enable P2P error reporting" newline bitfld.long 0x8 18.--19. "TARGET_ABOVE_CONFIG_LIMIT_REG,Configuration requests with an address greater than CONFIG_LIMIT_REG are directed to either ELBI or TRGT1 interface based on the setting of this field. This field can have the following values: - 1: ELBI - 2: TRGT1 Note:.." "?,ELBI,TRGT1,?" newline hexmask.long.word 0x8 8.--17. 1. "CONFIG_LIMIT_REG,Configuration requests are directed either to CDM or ELBI/RTRGT1 based on the value of this field. - Configuration requests with an address less CONFIG_LIMIT_REG are directed to the CDM - Configuration requests with an address greater.." newline bitfld.long 0x8 7. "CFG_TLP_BYPASS_EN_REG,Setting of this field defines which field TARGET_ABOVE_CONFIG_LIMIT_REG or CONFIG_LIMIT_REG decides the destination of Configuration requests. This field can have the following values: - 0: Configuration TLPs are routed according to.." "Configuration TLPs are routed according to the..,Configuration TLPs are routed according to the.." newline bitfld.long 0x8 6. "CPLQ_MNG_EN,This field enables the Completion Queue Management feature. Note: This register field is sticky." "0,1" newline bitfld.long 0x8 5. "ARI_DEVICE_NUMBER,When ARI is enabled this field enables use of the device ID. Note: This register field is sticky." "0,1" newline bitfld.long 0x8 4. "DISABLE_AUTO_LTR_CLR_MSG,Disable the autonomous generation of LTR clear message in upstream port. This field can have the following values: - 0: Allow the autonomous generation of LTR clear message. - 1: Disable the autonomous generation of LTR clear.." "Allow the autonomous generation of LTR clear..,Disable the autonomous generation of LTR clear.." newline bitfld.long 0x8 3. "SIMPLIFIED_REPLAY_TIMER,Enables Simplified Replay Timer (Gen4). For more details see 'Transmit Replay' in 'Transmit TLP Processing' section in the 'Controller Operations' chapter of the Databook. Simplified Replay Timer can have the following Values: -.." "0,1" newline bitfld.long 0x8 2. "UR_CA_MASK_4_TRGT1,When this field is set to '1' the controller suppresses error logging error message generation and CPL generation for non-posted requests TLPs (with UR filtering status) forwarded to your application (that is when DEFAULT_TARGET.." "0,1" newline bitfld.long 0x8 1. "DEFAULT_TARGET,Default target for an IO or MEM request with UR/CA/CRS received. Based on the value of this field the controller either drops or forwards these requests to your application. - 0: The controller drops all incoming I/O or MEM requests (after.." "The controller drops all incoming I/O or MEM..,The controller forwards all incoming I/O or MEM.." newline bitfld.long 0x8 0. "DBI_RO_WR_EN,Write to RO Registers Using DBI. Your application can write to some RO and HwInit register fields through the DBI when you set this field to '1'. For more details see 'Writing to Read-Only Registers' in 'Register Module LBC and DBI'.." "0,1" line.long 0xC "MULTI_LANE_CONTROL_OFF,UpConfigure Multi-lane Control Register. Used when upsizing or downsizing the link width through Configuration state without bringing the link down. For more details. see the 'Link Establishment' section in the 'Controller.." hexmask.long.tbyte 0xC 8.--31. 1. "RSVDP_8,Reserved for future use." newline bitfld.long 0xC 7. "UPCONFIGURE_SUPPORT,Upconfigure Support. The controller sends this value as the Link Upconfigure Capability in TS2 Ordered Sets in Configuration.Complete state. This field is reserved (fixed to '0') for M-PCIe. Note: This register field is sticky." "0,1" newline bitfld.long 0xC 6. "DIRECT_LINK_WIDTH_CHANGE,Directed Link Width Change. The controller always moves to Configuration state through Recovery state when this bit is set to '1'. - If the upconfigure_capable variable is '1' and the PCIE_CAP_HW_AUTO_WIDTH_DISABLE bit in.." "0,1" newline hexmask.long.byte 0xC 0.--5. 1. "TARGET_LINK_WIDTH,Target Link Width. Values correspond to: - 6'b000000: Controller does not start upconfigure or autonomous width downsizing in the Configuration state. - 6'b000001: x1 - 6'b000010: x2 - 6'b000100: x4 - 6'b001000: x8 - 6'b010000: x16 -.." line.long 0x10 "PHY_INTEROP_CTRL_OFF,PHY Interoperability Control Register." hexmask.long.tbyte 0x10 12.--31. 1. "RSVDP_12,Reserved for future use." newline bitfld.long 0x10 10. "L1_CLK_SEL,L1 Clock control bit. This field is reserved for internal use. You should not write to this field and change the default unless specifically instructed by Synopsys support. - 1: Controller does not request aux_clk switch and core_clk gating in.." "Controller requests aux_clk switch and core_clk..,Controller does not request aux_clk switch and.." newline rbitfld.long 0x10 9. "L1_NOWAIT_P1,L1 entry control bit. This field is reserved for internal use. You should not write to this field and change the default unless specifically instructed by Synopsys support. - 1: Controller does not wait for PHY to acknowledge transition to.." "Controller waits for the PHY to acknowledge..,Controller does not wait for PHY to acknowledge.." newline bitfld.long 0x10 8. "L1SUB_EXIT_MODE,L1 Exit Control Using phy_mac_pclkack_n. This field is reserved for internal use. You should not write to this field and change the default unless specifically instructed by Synopsys support. - 1: Controller exits L1 without waiting for.." "Controller waits for the PHY to assert..,Controller exits L1 without waiting for the PHY.." newline rbitfld.long 0x10 7. "RSVDP_7,Reserved for future use." "0,1" newline hexmask.long.byte 0x10 0.--6. 1. "RXSTANDBY_CONTROL,Rxstandby Control. Bits 0..5 determine if the controller asserts the RxStandby signal (mac_phy_rxstandby) in the indicated condition. Bit 6 enables the controller to perform the RxStandby/RxStandbyStatus handshake. This field is.." line.long 0x14 "TRGT_CPL_LUT_DELETE_ENTRY_OFF,TRGT_CPL_LUT Delete Entry Control register. Using this register you can delete one entry in the target completion LUT. You should only use this register when you know that your application will never send the completion.." bitfld.long 0x14 31. "DELETE_EN,This is a one-shot bit. A '1' write to this bit triggers the deletion of the target completion LUT entry that is specified in the LOOK_UP_ID field. This is a self-clearing register field. Reading from this register field always returns a '0'." "0,1" newline hexmask.long 0x14 0.--30. 1. "LOOK_UP_ID,This number selects one entry to delete of the TRGT_CPL_LUT." line.long 0x18 "LINK_FLUSH_CONTROL_OFF,Link Reset Request Flush Control Register." hexmask.long.byte 0x18 24.--31. 1. "RSVD_I_8,This is an internally reserved field. Do not use. Note: This register field is sticky." newline hexmask.long.tbyte 0x18 1.--23. 1. "RSVDP_1,Reserved for future use." newline bitfld.long 0x18 0. "AUTO_FLUSH_EN,Enables automatic flushing of pending requests before sending the reset request to the application logic to reset the PCIe controller and the AXI Bridge. The flushing process is initiated if any of the following events occur: - Hot reset.." "0,1" line.long 0x1C "AMBA_ERROR_RESPONSE_DEFAULT_OFF,AXI Bridge Slave Error Response Register." hexmask.long.word 0x1C 16.--31. 1. "RSVDP_16,Reserved for future use." newline hexmask.long.byte 0x1C 10.--15. 1. "AMBA_ERROR_RESPONSE_MAP,AXI Slave Response Error Map. Allows you to selectively map the errors received from the PCIe completion (for non-posted requests) to the AXI slave responses slv_rresp or slv_bresp. The recommended setting is SLVERR. CRS is.." newline hexmask.long.byte 0x1C 5.--9. 1. "RSVDP_5,Reserved for future use." newline bitfld.long 0x1C 3.--4. "AMBA_ERROR_RESPONSE_CRS,CRS Slave Error Response Mapping. Determines the AXI slave response for CRS completions. For more details see 'Error Handling' in the AXI chapter of the Databook. AHB: - always returns OKAY AXI: - 00: OKAY - 01: OKAY with all.." "OKAY,OKAY with all FFFF_FFFF data for all CRS..,?,?" newline bitfld.long 0x1C 2. "AMBA_ERROR_RESPONSE_VENDORID,Vendor ID Non-existent Slave Error Response Mapping. Determines the AXI slave response for errors on reads to non-existent Vendor ID register. For more details see 'Error Handling' in the AXI chapter of the Databook. AHB: -.." "OKAY,SLVERR/DECERR" newline rbitfld.long 0x1C 1. "RSVDP_1,Reserved for future use." "0,1" newline bitfld.long 0x1C 0. "AMBA_ERROR_RESPONSE_GLOBAL,Global Slave Error Response Mapping. Determines the AXI slave response for all error scenarios on non-posted requests. For more details see 'Error Handling' in the AXI chapter of the Databook. AHB: - 0: OKAY (with FFFF data for.." "OKAY,SLVERR/DECERR" line.long 0x20 "AMBA_LINK_TIMEOUT_OFF,Link Down AXI Bridge Slave Timeout Register. If your application AXI master issues outbound requests to the AXI bridge slave interface before the PCIe link is operational. the controller starts a 'flush' timer. The timeout value of.." hexmask.long.tbyte 0x20 9.--31. 1. "RSVDP_9,Reserved for future use." newline bitfld.long 0x20 8. "LINK_TIMEOUT_ENABLE_DEFAULT,Disable Flush. You can disable the flush feature by setting this field to '1'. Note: This register field is sticky." "0,1" newline hexmask.long.byte 0x20 0.--7. 1. "LINK_TIMEOUT_PERIOD_DEFAULT,Timeout Value (ms). The timer will timeout and then flush the bridge TX request queues after this amount of time. The timer counts when there are pending outbound AXI slave interface requests and the PCIe TX link is not.." line.long 0x24 "AMBA_ORDERING_CTRL_OFF,AMBA Ordering Control." hexmask.long.tbyte 0x24 8.--31. 1. "RSVDP_8,Reserved for future use." newline bitfld.long 0x24 7. "AX_MSTR_ZEROLREAD_FW,AXI Master Zero Length Read Forward to the application. The DW PCIe controller AXI bridge is able to terminate in order with the Posted transactions the zero length read implementing the PCIe express flush semantics of the Posted.." "The zero length Read is terminated at the DW..,The zero length Read is forward to the application" newline rbitfld.long 0x24 5.--6. "RSVDP_5,Reserved for future use." "0,1,2,3" newline bitfld.long 0x24 3.--4. "AX_MSTR_ORDR_P_EVENT_SEL,AXI Master Posted Ordering Event Selector. This field selects how the master interface determines when a P write is completed when enforcing the PCIe ordering rule 'NP must not pass P' at the AXI Master Interface. The AXI.." "B'last event: wait for the all of the write..,AW'last event: wait until the complete Posted..,This setting will not affect:,?" newline rbitfld.long 0x24 2. "RSVDP_2,Reserved for future use." "0,1" newline bitfld.long 0x24 1. "AX_SNP_EN,AXI Serialize Non-Posted Requests Enable. This field enables the AXI Bridge to serialize same ID Non-Posted Read/Write Requests on the wire. Serialization implies one outstanding same ID NP Read or Write on the wire and used to avoid AXI RAR.." "0,1" newline rbitfld.long 0x24 0. "RSVDP_0,Reserved for future use." "0,1" group.long (0x1E0+0x700)++0xB line.long 0x0 "COHERENCY_CONTROL_1_OFF,ACE Cache Coherency Control Register 1" hexmask.long 0x0 2.--31. 1. "CFG_MEMTYPE_BOUNDARY_LOW_ADDR,Boundary Lower Address For Memory Type. Bits [31:0] of dword-aligned address of the boundary for Memory type. The two lower address LSBs are '00'. Addresses up to but not including this value are in the lower address space.." newline rbitfld.long 0x0 1. "RSVDP_1,Reserved for future use." "0,1" newline bitfld.long 0x0 0. "CFG_MEMTYPE_VALUE,Sets the memory type for the lower and upper parts of the address space: - 0: lower = Peripheral; upper = Memory - 1: lower = Memory type; upper = Peripheral Note: This register field is sticky." "lower = Peripheral; upper = Memory,lower = Memory type; upper = Peripheral" line.long 0x4 "COHERENCY_CONTROL_2_OFF,ACE Cache Coherency Control Register 2" hexmask.long 0x4 0.--31. 1. "CFG_MEMTYPE_BOUNDARY_HIGH_ADDR,Boundary Upper Address For Memory Type. Bits [63:32] of the 64-bit dword-aligned address of the boundary for Memory type. Note: This register field is sticky." line.long 0x8 "COHERENCY_CONTROL_3_OFF,ACE Cache Coherency Control Register 3" hexmask.long.byte 0x8 27.--30. 1. "CFG_MSTR_AWCACHE_VALUE,Master Write CACHE Signal Value. Value of the individual bits in mstr_awcache when CFG_MSTR_AWCACHE_MODE is '1'. Note: not applicable to message requests; for message requests the value of mstr_awcache is always '0000' Note: This.." newline hexmask.long.byte 0x8 19.--22. 1. "CFG_MSTR_ARCACHE_VALUE,Master Read CACHE Signal Value. Value of the individual bits in mstr_arcache when CFG_MSTR_ARCACHE_MODE is '1'. Note: This register field is sticky." newline hexmask.long.byte 0x8 11.--14. 1. "CFG_MSTR_AWCACHE_MODE,Master Write CACHE Signal Behavior. Defines how the individual bits in mstr_awcache are controlled: - 0: set automatically by the AXI master - 1: set by the value of the corresponding bit of the CFG_MSTR_AWCACHE_VALUE field Note:.." newline hexmask.long.byte 0x8 3.--6. 1. "CFG_MSTR_ARCACHE_MODE,Master Read CACHE Signal Behavior. Defines how the individual bits in mstr_arcache are controlled: - 0: set automatically by the AXI master - 1: set by the value of the corresponding bit of the CFG_MSTR_ARCACHE_VALUE field Note:.." group.long (0x1F0+0x700)++0x7 line.long 0x0 "AXI_MSTR_MSG_ADDR_LOW_OFF,Lower 20 bits of the programmable AXI address where Messages coming from wire are mapped to. Bits [11:0] of the register are tied to zero for the address to be 4k-aligned. In previous releases. the third and fourth DWORDs of a.." hexmask.long.tbyte 0x0 12.--31. 1. "CFG_AXIMSTR_MSG_ADDR_LOW,Lower 20 bits of the programmable AXI address for Messages. Note: This register field is sticky." newline hexmask.long.word 0x0 0.--11. 1. "CFG_AXIMSTR_MSG_ADDR_LOW_RESERVED,Reserved for future use. Note: This register field is sticky." line.long 0x4 "AXI_MSTR_MSG_ADDR_HIGH_OFF,Upper 32 bits of the programmable AXI address where Messages coming from wire are mapped to." hexmask.long 0x4 0.--31. 1. "CFG_AXIMSTR_MSG_ADDR_HIGH,Upper 32 bits of the programmable AXI address for Messages. Note: This register field is sticky." rgroup.long (0x1F8+0x700)++0x7 line.long 0x0 "PCIE_VERSION_NUMBER_OFF,PCIe Controller IIP Release Version Number. The version number is given in hex format. You should convert each pair of hex characters to ASCII to interpret. Using 4.70a (GA) as an example: - VERSION_NUMBER = 0x3437302a which.." hexmask.long 0x0 0.--31. 1. "VERSION_NUMBER,Version Number." line.long 0x4 "PCIE_VERSION_TYPE_OFF,PCIe Controller IIP Release Version Type. The type is given in hex format. You should convert each pair of hex characters to ASCII to interpret. Using 4.70a (GA) as an example: - VERSION_NUMBER = 0x3437302a which translates to 470*.." hexmask.long 0x4 0.--31. 1. "VERSION_TYPE,Version Type." group.long (0x240+0x700)++0x7 line.long 0x0 "MSIX_ADDRESS_MATCH_LOW_OFF,MSI-X Address Match Low Register. When you enable the MSI-X Table RAM feature (MSIX_TABLE_EN=1). the controller implements the logic and RAM required to generate MSI-X requests. For more details. see the Interrupts section in.." hexmask.long 0x0 2.--31. 1. "MSIX_ADDRESS_MATCH_LOW,MSI-X Address Match Low Address. Note: This register field is sticky." newline rbitfld.long 0x0 1. "MSIX_ADDRESS_MATCH_RESERVED_1,Reserved. Note: This register field is sticky." "0,1" newline bitfld.long 0x0 0. "MSIX_ADDRESS_MATCH_EN,MSI-X Match Enable. Enable the MSI-X Address Match feature when the AXI bridge is present. Note: This register field is sticky." "0,1" line.long 0x4 "MSIX_ADDRESS_MATCH_HIGH_OFF,MSI-X Address Match High Register. When you enable the MSI-X Table RAM feature (MSIX_TABLE_EN=1). the controller implements the logic and RAM required to generate MSI-X requests. For more details. see the Interrupts section in.." hexmask.long 0x4 0.--31. 1. "MSIX_ADDRESS_MATCH_HIGH,MSI-X Address Match High Address. Note: This register field is sticky." wgroup.long (0x248+0x700)++0x3 line.long 0x0 "MSIX_DOORBELL_OFF,MSI-X Doorbell Register. When you enable the MSI-X Table RAM feature (MSIX_TABLE_EN=1). the controller implements the logic and RAM required to generate MSI-X requests. For more details. see the Interrupts section in the 'Controller.." bitfld.long 0x0 29.--31. "MSIX_DOORBELL_RESERVED_29_31,Reserved." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x0 24.--28. 1. "MSIX_DOORBELL_PF,MSIX Doorbell Physical Function. This register determines the Physical Function for the MSI-X transaction." newline hexmask.long.byte 0x0 16.--23. 1. "MSIX_DOORBELL_VF,MSIX Doorbell Virtual Function. This register determines the Virtual Function for the MSI-X transaction." newline bitfld.long 0x0 15. "MSIX_DOORBELL_VF_ACTIVE,MSIX Doorbell Virtual Function Active. This register determines whether a Virtual Function is used to generate the MSI-X transaction." "0,1" newline bitfld.long 0x0 12.--14. "MSIX_DOORBELL_TC,MSIX Doorbell Traffic Class. This register determines which traffic class to generate the MSI-X transaction with." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 11. "MSIX_DOORBELL_RESERVED_11,Reserved." "0,1" newline hexmask.long.word 0x0 0.--10. 1. "MSIX_DOORBELL_VECTOR,MSI-X Doorbell Vector. This register determines which vector to generate the MSI-X transaction for." group.long (0x24C+0x700)++0x3 line.long 0x0 "MSIX_RAM_CTRL_OFF,MSI-X RAM power mode and debug control register. When you enable the MSI-X Table RAM feature (MSIX_TABLE_EN=1). the controller implements the logic and RAM required to generate MSI-X requests. For more details. see the Interrupts.." hexmask.long.byte 0x0 26.--31. 1. "MSIX_RAM_CTRL_RESERVED_26_31,Reserved. Note: This register field is sticky." newline bitfld.long 0x0 25. "MSIX_RAM_CTRL_DBG_PBA,MSIX PBA RAM Debug Mode. Use this bit to activate the debug mode and allow direct read/write access to the PBA. Use can also use the dbg_pba input to activate debug mode. Debug mode turns off the PF/VF/Offset-based addressing into.." "0,1" newline bitfld.long 0x0 24. "MSIX_RAM_CTRL_DBG_TABLE,MSIX Table RAM Debug Mode. Use this bit to activate the debug mode and allow direct read/write access to the Table. Use can also use the dbg_table input to activate debug mode. Debug mode turns off the PF/VF/Offset-based.." "0,1" newline hexmask.long.byte 0x0 17.--23. 1. "MSIX_RAM_CTRL_RESERVED_17_23,Reserved. Note: This register field is sticky." newline bitfld.long 0x0 16. "MSIX_RAM_CTRL_BYPASS,MSIX RAM Control Bypass. The bypass field when set disables the internal generation of low power signals for both RAMs. It is up to the application to ensure the RAMs are in the proper power state before trying to access them." "0,1" newline hexmask.long.byte 0x0 10.--15. 1. "MSIX_RAM_CTRL_RESERVED_10_15,Reserved. Note: This register field is sticky." newline bitfld.long 0x0 9. "MSIX_RAM_CTRL_PBA_SD,MSIX PBA RAM Shut Down. Set this bit to drive the cfg_msix_pba_sd output to signal your external logic to place the MSIX PBA RAM in Shut Down low-power mode. Note: This register field is sticky." "0,1" newline bitfld.long 0x0 8. "MSIX_RAM_CTRL_PBA_DS,MSIX PBA RAM Deep Sleep. Set this bit to drive the cfg_msix_pba_ds output to signal your external logic to place the MSIX PBA RAM in Deep Sleep low-power mode. Note: This register field is sticky." "0,1" newline hexmask.long.byte 0x0 2.--7. 1. "MSIX_RAM_CTRL_RESERVED_2_7,Reserved. Note: This register field is sticky." newline bitfld.long 0x0 1. "MSIX_RAM_CTRL_TABLE_SD,MSIX Table RAM Shut Down. Set this bit to drive the cfg_msix_table_sd output to signal your external logic to place the MSIX Table RAM in Shut Down low-power mode. Note: This register field is sticky." "0,1" newline bitfld.long 0x0 0. "MSIX_RAM_CTRL_TABLE_DS,MSIX Table RAM Deep Sleep. Set this bit to drive the cfg_msix_table_ds output to signal your external logic to place the MSIX Table RAM in Deep Sleep low-power mode. Note: This register field is sticky." "0,1" group.long (0x430+0x700)++0x3 line.long 0x0 "PL_LTR_LATENCY_OFF,LTR Latency Register. The function of this register field (and all other fields in this register) differs between an upstream port and a downstream port. For an upstream port. the register fields capture the corresponding fields in the.." bitfld.long 0x0 31. "NO_SNOOP_LATENCY_REQUIRE,No Snoop Latency Requirement. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" "0,1" newline rbitfld.long 0x0 29.--30. "RSVDP_29,Reserved for future use." "0,1,2,3" newline bitfld.long 0x0 26.--28. "NO_SNOOP_LATENCY_SCALE,No Snoop Latency Scale. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" "0,1,2,3,4,5,6,7" newline hexmask.long.word 0x0 16.--25. 1. "NO_SNOOP_LATENCY_VALUE,No Snoop Latency Value. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" newline bitfld.long 0x0 15. "SNOOP_LATENCY_REQUIRE,Snoop Latency Requirement. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" "0,1" newline rbitfld.long 0x0 13.--14. "RSVDP_13,Reserved for future use." "0,1,2,3" newline bitfld.long 0x0 10.--12. "SNOOP_LATENCY_SCALE,Snoop Latency Scale. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" "0,1,2,3,4,5,6,7" newline hexmask.long.word 0x0 0.--9. 1. "SNOOP_LATENCY_VALUE,Snoop Latency Value. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" group.long (0x440+0x700)++0xB line.long 0x0 "AUX_CLK_FREQ_OFF,Auxiliary Clock Frequency Control Register." hexmask.long.tbyte 0x0 10.--31. 1. "RSVDP_10,Reserved for future use." newline hexmask.long.word 0x0 0.--9. 1. "AUX_CLK_FREQ,The aux_clk frequency in MHz. This value is used to provide a 1 us reference for counting time during low-power states with aux_clk when the PHY has removed the pipe_clk. Frequencies lower than 1 MHz are possible but with a loss of accuracy.." line.long 0x4 "L1_SUBSTATES_OFF,L1 Substates Timing Register." hexmask.long.tbyte 0x4 9.--31. 1. "RSVDP_9,Reserved for future use." newline bitfld.long 0x4 8. "L1SUB_LOW_POWER_CLOCK_SWITCH_MODE,If this bit is set to 1'b1 the reference clock will be running regardless of the CLKREQ# setting. If this bit is set to 1'b0 the reference clock may be gated off when CLKREQ# is de-asserted. If the bit is set to 1'b1 the.." "0,1" newline bitfld.long 0x4 6.--7. "L1SUB_T_PCLKACK,Max delay (in 1us units) between a MAC request to remove the clock on mac_phy_pclkreq_n and a PHY response on phy_mac_pclkack_n. If the PHY does not respond within this time the request is aborted.The actual timeout value will be.." "0,1,2,3" newline hexmask.long.byte 0x4 2.--5. 1. "L1SUB_T_L1_2,Duration (in 1us units) of L1.2. The actual timeout value will be L1SUB_T_L1_2 + 1. Range is 0.15. Note: This register field is sticky." newline bitfld.long 0x4 0.--1. "L1SUB_T_POWER_OFF,Duration (in 1us units) of L1.2.Entry. The actual timeout value will be L1SUB_T_POWER_OFF + 1. Range is 0.3. Note: This register field is sticky." "0,1,2,3" line.long 0x8 "POWERDOWN_CTRL_STATUS_OFF,Powerdown Control and Status Register." hexmask.long.tbyte 0x8 12.--31. 1. "RSVDP_12,Reserved for future use." newline hexmask.long.byte 0x8 8.--11. 1. "POWERDOWN_PHY_POWERDOWN,This field represents the Powerdown value that has been acknowledged by the PHY. It is updated with the value of Powerdown driven by the controller when the PHY has returned the Phystatus acknowledgment for the Powerdown.." newline hexmask.long.byte 0x8 4.--7. 1. "POWERDOWN_MAC_POWERDOWN,This field represents the Powerdown value driven by the controller to the PHY." newline rbitfld.long 0x8 1.--3. "RSVDP_1,Reserved for future use." "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 0. "POWERDOWN_FORCE,This field is a one shot field. Writing a value of 1 to this field causes the controller to complete the P2 Powerdown handshake regardless of whether the PHY has returned Phystatus. This field could be used for debug purposes in event.." "0,1" group.long (0x470+0x700)++0x7 line.long 0x0 "PHY_VIEWPORT_CTLSTS_OFF,PHY Register Viewport Control and Status Register." rbitfld.long 0x0 31. "PHY_VIEWPORT_PENDING,PHY viewport pending. Indicates the access is pending. - 1 : Pending - 0 : Idle This bit is set to 1 when the read/write access has been initiated. This bit is cleared when the access is completed. If phy_reg_clk_g is never activated.." "Idle,Pending" newline rbitfld.long 0x0 30. "PHY_VIEWPORT_STATUS,PHY viewport status. Indicates the status of the latest access. - 1 : Timeout - 0 : No errors If the timeout is detected this bit is set to 1 and PHY_VIEWPORT_PENDING is cleared. This bit is cleared when the read/write access is.." "No errors,Timeout" newline hexmask.long.byte 0x0 23.--29. 1. "RSVDP_23,Reserved for future use." newline bitfld.long 0x0 22. "PHY_VIEWPORT_TIMEOUT_DISABLE,PHY viewport timeout disable. Disables the PHY register access timeout structure. When the timeout is disabled you must ensure that the PHY register accesses are always acknowledged by cr_para_ack. Otherwise.." "0,1" newline bitfld.long 0x0 21. "PHY_VIEWPORT_BCWR,Broadcast write access to all xN sub-blocks. If you need to broadcast the write accesses into all lanes both PHY_VIEWPORT_ADDR[15] and this bit should be 1. Note: This register field is sticky." "0,1" newline bitfld.long 0x0 20. "PHY_VIEWPORT_READ,PHY viewport read. If set a read access is initiated. The value is always 0 when this bit is read. Note: This register field is sticky." "0,1" newline hexmask.long.byte 0x0 16.--19. 1. "PHY_VIEWPORT_NUM,PHY viewport xN sub-block number. Selects one of xN sub-blocks. This register is not used when the write access is initiated with PHY_VIEWPORT_BCWR==1. Note: This register field is sticky." newline hexmask.long.word 0x0 0.--15. 1. "PHY_VIEWPORT_ADDR,PHY viewport address. Indicates the PHY's register address. Please refer to the PHY databook for the address map definition. Note: This register field is sticky." line.long 0x4 "PHY_VIEWPORT_DATA_OFF,PHY Register Viewport Data Register." hexmask.long.word 0x4 16.--31. 1. "RSVDP_16,Reserved for future use." newline hexmask.long.word 0x4 0.--15. 1. "PHY_VIEWPORT_DATA,PHY viewport data. A write access to this register initiates the PHY register write access. By a read access to this register this field returns the latest read data from the PHY register. Note: This register field is sticky." group.long (0x490+0x700)++0x3 line.long 0x0 "PIPE_RELATED_OFF,PIPE Related Register. This register controls the pipe's capabitity. control. and status parameters." hexmask.long.tbyte 0x0 9.--31. 1. "RSVDP_9,Reserved for future use." newline bitfld.long 0x0 8. "PIPE_GARBAGE_DATA_MODE,PIPE Garbage Data Mode. - 0: PIPE Spec compliant mode: The MAC discards any symbols received after the electrical idle ordered-set until RxValid is deasserted. - 1: Special PHY Support mode: The MAC discards any symbols received.." "PIPE Spec compliant mode: The MAC discards any..,Special PHY Support mode: The MAC discards any.." tree.end tree.end tree "PCIE1_NCR" base ad:0xF10E0000 group.long 0x0++0x7 line.long 0x0 "INTR_0,INTR_0" bitfld.long 0x0 31. "INTR_PM_XTLH_BLOCK_TLP,Indicates that your application must stop generating new outgoing request TLPs due to the current power management state. Your application can continue to generate completion TLPs." "0,1" newline bitfld.long 0x0 30. "INTR_LINK_REQ_RST_NOT,Reset request because the link has gone down or the controller received a hot-reset request. A low level indicates that the controller is requesting external logic to reset the controller because the PHY link is down. When the AXI.." "0,1" newline bitfld.long 0x0 29. "INTR_SMLH_REQ_RST_NOT,Early version of the link_req_rst_not signal." "0,1" newline bitfld.long 0x0 28. "INTR_SMLH_LINK_UP,PHY Link up/down indicator: 1: Link is up 0: Link is down" "Link is down,Link is up" newline bitfld.long 0x0 27. "INTR_RDLH_LINK_UP,Data link layer up/down indicator: This status from the flow control initialization state machine indicates that flow control has been initiated and the Data link layer is ready to transmit and receive packets. For multi-VC designs.." "Link is down,Link is up" newline bitfld.long 0x0 26. "INTR_VEN_MSI_GRANT,One-cycle pulse that indicates that the controller has accepted the request to send an MSI. After asserting ven_msi_grant for one cycle the controller does not wait for ven_msi_req to be de-asserted then reasserted to generate another.." "0,1" newline bitfld.long 0x0 25. "INTR_VEN_MSG_GRANT,One-cycle pulse that indicates that the controller has accepted the request to send the vendor-defined Message." "0,1" newline bitfld.long 0x0 23.--24. "INTR_CFG_UP_DRS_TO_FRS,DRS to FRS Pulse. The DSP controller asserts the cfg_up_drs_to_frs output and sends an FRS message with the reason code set to 'DRS Message Received' when: It receives a DRS message and PCIE_CAP_DRS_SIGNALING_CONTROL in.." "0,1,2,3" newline bitfld.long 0x0 21.--22. "INTR_CFG_DRS_MSI,DRS Message Received Interrupt Pulse. The DSP controller asserts the cfg_drs_msi output when all of the following are true: It receives a DRS message PCIE_CAP_DRS_SIGNALING_CONTROL in LINK_CONTROL_LINK_STATUS_REG is 2'b01 MSI or MSI-X is.." "0,1,2,3" newline bitfld.long 0x0 19.--20. "INTR_FRSQ_MSI,FRSQ Interrupt Pulse. The RC asserts this output when it receives an FRQ message or when the FRS queue overflows." "0,1,2,3" newline bitfld.long 0x0 17.--18. "INTR_CFG_PME_MSI,The controller asserts cfg_pme_msi (as a one-cycle pulse) when all of the following conditions are true: MSI or MSI-X is enabled. The PME Interrupt Enable bit in the Root Control register is set to 1. The PME Status bit in the Root.." "0,1,2,3" newline bitfld.long 0x0 15.--16. "INTR_HP_MSI,INTR_HP_MSI" "0,1,2,3" newline bitfld.long 0x0 14. "INTR_CFG_LINK_AUTO_BW_MSI,The controller sets this pin when following conditions are true: MSI or MSI-X is enabled. The Link Autonomous Bandwidth Status register (Link Status register bit 15) is updated. The Link Autonomous Bandwidth Interrupt Enable.." "0,1" newline bitfld.long 0x0 13. "INTR_CFG_BW_MGT_MSI,The controller sets this pin when following conditions are true: MSI or MSI-X is enabled. The Link Bandwidth Management Status register (Link Control Status register bit 14) is updated The Link Bandwidth Management Interrupt Enable.." "0,1" newline bitfld.long 0x0 11.--12. "INTR_HP_PME,The controller asserts hp_pme when all of the following conditions are true: The PME Enable bit in the Power Management Control and Status" "0,1,2,3" newline bitfld.long 0x0 10. "INTR_PTM_CLOCK_UPDATED,Indicates that the controller has updated the Local Clock." "0,1" newline bitfld.long 0x0 9. "INTR_PTM_REQ_DUP_RX,PTM Requester Duplicate Received. Single-cycle pulse indicating PTM Requester received a duplicate TLP while PTM Requester is in the process of updating PTM local clock or Following calculation of the update when the PTM context is.." "0,1" newline bitfld.long 0x0 8. "INTR_PTM_REQ_REPLAY_TX,PTM Requester Replay Sent. Single-cycle pulse indicating PTM Requester detected a TLP replay being sent when ResponseD messages are in use while PTM Requester is in the process of updating PTM local clock or Following calculation.." "0,1" newline bitfld.long 0x0 7. "INTR_RADM_MSG_LTR,One-clock-cycle pulse that indicates that the controller received an LTR message. The controller makes the message header available the radm_msg_payload output. It is also available the app_ltr_latency output. When RX_TLP > 1 and when.." "0,1" newline bitfld.long 0x0 6. "INTR_RADM_MSG_UNLOCK,One-cycle pulse that indicates that the controller received an Unlock message. When RX_TLP > 1 and when two messages of the same type are received in the same clock cycle (back-to-back) then no separate indication is given for the.." "0,1" newline bitfld.long 0x0 5. "INTR_RADM_PM_PME,One-clock-cycle pulse that indicates that the controller received a PM_PME message." "0,1" newline bitfld.long 0x0 4. "INTR_RADM_PM_TO_ACK,One-clock-cycle pulse that indicates that the controller received a PME_TO_Ack message. Upstream port: Reserved." "0,1" newline bitfld.long 0x0 3. "INTR_RADM_PM_TURNOFF,One-clock-cycle pulse that indicates that the controller received a PME Turnoff message. When RX_TLP > 1 and when two messages of the same type are received in the same clock cycle (back-to-back) then no indication is given for the.." "0,1" newline bitfld.long 0x0 2. "INTR_RADM_VENDOR_MSG,One-cycle pulse that indicates the controller received a vendor-defined message. The controller makes the message header available the radm_msg_payload output. When FX_TLP > 1 and when two messages of the same type are received in.." "0,1" newline bitfld.long 0x0 1. "INTR_PERSTN,INTR_PERSTN This interrupt status bit indicates PERST# pad input fall edge detected." "0,1" newline bitfld.long 0x0 0. "INTR_WAKEN,INTR_WAKEN This interrupt status bit indicates WAKE# pad input fall edge detected." "0,1" line.long 0x4 "INTR_1,INTR_1" bitfld.long 0x4 31. "INTR_TRGT_CPL_TIMEOUT,Indicates that the application has not generated a completion for an incoming request within the required time interval. Information about the timed out completion is available the trgt_timeout_* outputs listed later.When a.." "0,1" newline bitfld.long 0x4 30. "INTR_RADM_CPL_TIMEOUT,Indicates that the completion TLP for a request has not been received within the expected time window." "0,1" newline hexmask.long.byte 0x4 26.--29. 1. "INTR_INT_D_A,INTR_INT_D_A These Interrupt status bit indicates wheter Legacy A~D transmitted or received by controller. bit 29 : INT_D .. bit26 : INT_A" newline bitfld.long 0x4 24.--25. "INTR_CFG_SEND_F_ERR,Sent Fatal Error. Controller has sent a message towards the Root Complex indicating that an Rx TLP that contained a fatal error and that can not be corrected was received by the EndPoint" "0,1,2,3" newline bitfld.long 0x4 22.--23. "INTR_CFG_SEND_NF_ERR,Sent Non-Fatal Error. Controller has sent a message towards the Root Complex indicating that an Rx TLP that contained an non-fatal error and that can not be corrected was received by the EndPoint" "0,1,2,3" newline bitfld.long 0x4 20.--21. "INTR_CFG_SEND_COR_ERR,Sent Correctable Error. Core has sent a message towards the Root Complex indicating that an Rx TLP that contained an error and that can be corrected was received by the EndPoint" "0,1,2,3" newline bitfld.long 0x4 18.--19. "INTR_CFG_FLR_PF_ACTIVE,Set when the software initiates FLR a physical function by writing to the 'Initiate FLR' register bit of that function. This signal is held asserted until reset of both the application and controller logic has been completed." "0,1,2,3" newline bitfld.long 0x4 16.--17. "INTR_PF_FRS_GRANT,Indicator of when an FRS message for this function has been scheduled for transmission." "0,1,2,3" newline hexmask.long.byte 0x4 8.--15. 1. "INTR_CFG_FLR_VF_ACTIVE,Set when the software initiates FLR a virtual function by writing to the 'Initiate FLR' register bit of that function. This signal is held asserted until the reset of both the application and internal controller logic has been.." newline hexmask.long.byte 0x4 0.--7. 1. "INTR_VF_FRS_GRANT,Indicator of when an FRS message for this VF has been scheduled for transmission." repeat 10. (list 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB )(list 0x0 0x4 0x8 0xC 0x10 0x14 0x18 0x1C 0x20 0x24 ) group.long ($2+0x8)++0x3 line.long 0x0 "INTR_$1,INTR_2" hexmask.long 0x0 0.--31. 1. "INTR_MSI_PF0,INTR_MSI_PF0" repeat.end group.long 0x30++0xB line.long 0x0 "INTR_12,INTR_12" newline hexmask.long.byte 0x0 16.--23. 1. "INTR_RADM_TRGT1_ATU_CBUF_ERR,INTR_RADM_TRGT1_ATU_CBUF_ERR" newline hexmask.long.byte 0x0 8.--15. 1. "INTR_RADM_TRGT1_ATU_SLOC_MATCH,INTR_RADM_TRGT1_ATU_SLOC_MATCH" newline bitfld.long 0x0 7. "INTR_RADM_CORRECTABLE_ERR,INTR_RADM_CORRECTABLE_ERR" "0,1" newline bitfld.long 0x0 6. "INTR_RADM_NONFATAL_ERR,INTR_RADM_NONFATAL_ERR" "0,1" newline bitfld.long 0x0 5. "INTR_RADM_FATAL_ERR,INTR_RADM_FATAL_ERR" "0,1" newline bitfld.long 0x0 3.--4. "INTR_CFG_AER_RC_ERR_MSI,INTR_CFG_AER_RC_ERR_MSI" "0,1,2,3" newline bitfld.long 0x0 1.--2. "INTR_CFG_SYS_ERR_RC,INTR_CFG_SYS_ERR_RC" "0,1,2,3" newline bitfld.long 0x0 0. "INTR_MSTR_AWMISC_INFO_EP,INTR_MSTR_AWMISC_INFO_EP" "0,1" line.long 0x4 "INTEN_0,INTEN_0" bitfld.long 0x4 31. "INTEN_PM_XTLH_BLOCK_TLP,Indicates that your application must stop generating new outgoing request TLPs due to the current power management state. Your application can continue to generate completion TLPs.This output is not used in RC mode." "0,1" newline bitfld.long 0x4 30. "INTEN_LINK_REQ_RST_NOT,Reset request because the link has gone down or the controller received a hot-reset request. A low level indicates that the controller is requesting external logic to reset the controller because the PHY link is down. When the AXI.." "0,1" newline bitfld.long 0x4 29. "INTEN_SMLH_REQ_RST_NOT,Early version of the link_req_rst_not signal." "0,1" newline bitfld.long 0x4 28. "INTEN_SMLH_LINK_UP,PHY Link up/down indicator: 1: Link is up 0: Link is down" "Link is down,Link is up" newline bitfld.long 0x4 27. "INTEN_RDLH_LINK_UP,Data link layer up/down indicator: This status from the flow control initialization state machine indicates that flow control has been initiated and the Data link layer is ready to transmit and receive packets. For multi-VC designs.." "Link is down,Link is up" newline bitfld.long 0x4 26. "INTEN_VEN_MSI_GRANT,One-cycle pulse that indicates that the controller has accepted the request to send an MSI. After asserting ven_msi_grant for one cycle the controller does not wait for ven_msi_req to be de-asserted then reasserted to generate another.." "0,1" newline bitfld.long 0x4 25. "INTEN_VEN_MSG_GRANT,One-cycle pulse that indicates that the controller has accepted the request to send the vendor-defined Message." "0,1" newline bitfld.long 0x4 23.--24. "INTEN_CFG_UP_DRS_TO_FRS,DRS to FRS Pulse. The DSP controller asserts the cfg_up_drs_to_frs output and sends an FRS message with the reason code set to 'DRS Message Received' when: It receives a DRS message and PCIE_CAP_DRS_SIGNALING_CONTROL in.." "0,1,2,3" newline bitfld.long 0x4 21.--22. "INTEN_CFG_DRS_MSI,DRS Message Received Interrupt Pulse. The DSP controller asserts the cfg_drs_msi output when all of the following are true: It receives a DRS message PCIE_CAP_DRS_SIGNALING_CONTROL in LINK_CONTROL_LINK_STATUS_REG is 2'b01 MSI or MSI-X.." "0,1,2,3" newline bitfld.long 0x4 19.--20. "INTEN_FRSQ_MSI,FRSQ Interrupt Pulse. The RC asserts this output when it receives an FRQ message or when the FRS queue overflows." "0,1,2,3" newline bitfld.long 0x4 17.--18. "INTEN_CFG_PME_MSI,The controller asserts cfg_pme_msi (as a one-cycle pulse) when all of the following conditions are true: MSI or MSI-X is enabled. The PME Interrupt Enable bit in the Root Control register is set to 1. The PME Status bit in the Root.." "0,1,2,3" newline bitfld.long 0x4 15.--16. "INTEN_HP_MSI,The controller asserts hp_msi (as a one-cycle pulse) when the logical AND of the following conditions transitions from false to true: MSI or MSI-X is enabled. Hot-Plug interrupts are enabled in the Slot Control register. Any bit in the Slot.." "0,1,2,3" newline bitfld.long 0x4 14. "INTEN_CFG_LINK_AUTO_BW_MSI,The controller sets this pin when following conditions are true: MSI or MSI-X is enabled. The Link Autonomous Bandwidth Status register (Link Status register bit 15) is updated. The Link Autonomous Bandwidth Interrupt Enable.." "0,1" newline bitfld.long 0x4 13. "INTEN_CFG_BW_MGT_MSI,The controller sets this pin when following conditions are true: MSI or MSI-X is enabled. The Link Bandwidth Management Status register (Link Control Status register bit 14) is updated The Link Bandwidth Management Interrupt Enable.." "0,1" newline bitfld.long 0x4 11.--12. "INTEN_HP_PME,The controller asserts hp_pme when all of the following conditions are true: The PME Enable bit in the Power Management Control and Status register is set to 1. Any bit in the Slot Status register transitions from 0 to 1 and the associated.." "0,1,2,3" newline bitfld.long 0x4 10. "INTEN_PTM_CLOCK_UPDATED,Indicates that the controller has updated the Local Clock." "0,1" newline bitfld.long 0x4 9. "INTEN_PTM_REQ_DUP_RX,PTM Requester Duplicate Received. Single-cycle pulse indicating PTM Requester received a duplicate TLP while PTM Requester is in the process of updating PTM local clock or Following calculation of the update when the PTM context.." "0,1" newline bitfld.long 0x4 8. "INTEN_PTM_REQ_REPLAY_TX,PTM Requester Replay Sent. Single-cycle pulse indicating PTM Requester detected a TLP replay being sent when ResponseD messages are in use while PTM Requester is in the process of updating PTM local clock or Following.." "0,1" newline bitfld.long 0x4 7. "INTEN_RADM_MSG_LTR,One-clock-cycle pulse that indicates that the controller received an LTR message. The controller makes the message header available the radm_msg_payload output. It is also available the app_ltr_latency output. When RX_TLP > 1 and when.." "0,1" newline bitfld.long 0x4 6. "INTEN_RADM_MSG_UNLOCK,One-cycle pulse that indicates that the controller received an Unlock message. When RX_TLP > 1 and when two messages of the same type are received in the same clock cycle (back-to-back) then no separate indication is given for the.." "0,1" newline bitfld.long 0x4 5. "INTEN_RADM_PM_PME,One-clock-cycle pulse that indicates that the controller received a PM_PME message." "0,1" newline bitfld.long 0x4 4. "INTEN_RADM_PM_TO_ACK,One-clock-cycle pulse that indicates that the controller received a PME_TO_Ack message. Upstream port: Reserved." "0,1" newline bitfld.long 0x4 3. "INTEN_RADM_PM_TURNOFF,One-clock-cycle pulse that indicates that the controller received a PME Turnoff message. When RX_TLP > 1 and when two messages of the same type are received in the same clock cycle (back-to-back) then no indication is given for the.." "0,1" newline bitfld.long 0x4 2. "INTEN_RADM_VENDOR_MSG,One-cycle pulse that indicates the controller received a vendor-defined message. The controller makes the message header available the radm_msg_payload output. When FX_TLP > 1 and when two messages of the same type are received in.." "0,1" newline bitfld.long 0x4 1. "INTEN_PERSTN,INTEN_PERSTN Interrupt Enable bit for INTR_PERSTN." "0,1" newline bitfld.long 0x4 0. "INTEN_WAKEN,INTEN_WAKEN Interrupt Enable bit for INTR_WAKEN." "0,1" line.long 0x8 "INTEN_1,INTEN_1" bitfld.long 0x8 31. "INTEN_TRGT_CPL_TIMEOUT,Indicates that the application has not generated a completion for an incoming request within the required time interval. Information about the timed out completion is available the trgt_timeout_* outputs listed later.When a.." "0,1" newline bitfld.long 0x8 30. "INTEN_RADM_CPL_TIMEOUT,Indicates that the completion TLP for a request has not been received within the expected time window." "0,1" newline hexmask.long.byte 0x8 26.--29. 1. "INTEN_INT_D_A,INTEN_INT_D_A Interrupt Enable bit for INTR_D_A. Bit 29 : INT_D ... Bit26 : INT_A." newline bitfld.long 0x8 24.--25. "INTEN_CFG_SEND_F_ERR,Sent Fatal Error. Controller has sent a message towards the Root Complex indicating that an Rx TLP that contained a fatal error and that can not be corrected was received by the EndPoint" "0,1,2,3" newline bitfld.long 0x8 22.--23. "INTEN_CFG_SEND_NF_ERR,Sent Non-Fatal Error. Controller has sent a message towards the Root Complex indicating that an Rx TLP that contained an non-fatal error and that can not be corrected was received by the EndPoint" "0,1,2,3" newline bitfld.long 0x8 20.--21. "INTEN_CFG_SEND_COR_ERR,Sent Correctable Error. Core has sent a message towards the Root Complex indicating that an Rx TLP that contained an error and that can be corrected was received by the EndPoint" "0,1,2,3" newline bitfld.long 0x8 18.--19. "INTEN_CFG_FLR_PF_ACTIVE,Set when the software initiates FLR a physical function by writing to the 'Initiate FLR' register bit of that function. This signal is held asserted until reset of both the application and controller logic has been completed." "0,1,2,3" newline bitfld.long 0x8 16.--17. "INTEN_PF_FRS_GRANT,Indicator of when an FRS message for this function has been scheduled for transmission." "0,1,2,3" newline hexmask.long.byte 0x8 8.--15. 1. "INTEN_CFG_FLR_VF_ACTIVE,Set when the software initiates FLR a virtual function by writing to the 'Initiate FLR' register bit of that function. This signal is held asserted until the reset of both the application and internal controller logic has been.." newline hexmask.long.byte 0x8 0.--7. 1. "INTEN_VF_FRS_GRANT,Indicator of when an FRS message for this VF has been scheduled for transmission." repeat 10. (list 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB )(list 0x0 0x4 0x8 0xC 0x10 0x14 0x18 0x1C 0x20 0x24 ) group.long ($2+0x3C)++0x3 line.long 0x0 "INTEN_$1,INTEN_2" hexmask.long 0x0 0.--31. 1. "INTEN_MSI_PF0,INTEN_MSI_PF0" repeat.end group.long 0x64++0x13 line.long 0x0 "INTEN_12,INTEN_12" newline hexmask.long.byte 0x0 16.--23. 1. "INTEN_RADM_TRGT1_ATU_CBUF_ERR,INTEN_RADM_TRGT1_ATU_CBUF_ERR" newline hexmask.long.byte 0x0 8.--15. 1. "INTEN_RADM_TRGT1_ATU_SLOC_MATCH,INTEN_RADM_TRGT1_ATU_SLOC_MATCH" newline bitfld.long 0x0 7. "INTEN_RADM_CORRECTABLE_ERR,INTEN_RADM_CORRECTABLE_ERR" "0,1" newline bitfld.long 0x0 6. "INTEN_RADM_NONFATAL_ERR,INTEN_RADM_NONFATAL_ERR" "0,1" newline bitfld.long 0x0 5. "INTEN_RADM_FATAL_ERR,INTEN_RADM_FATAL_ERR" "0,1" newline bitfld.long 0x0 3.--4. "INTEN_CFG_AER_RC_ERR_MSI,INTEN_CFG_AER_RC_ERR_MSI" "0,1,2,3" newline bitfld.long 0x0 1.--2. "INTEN_CFG_SYS_ERR_RC,INTEN_CFG_SYS_ERR_RC" "0,1,2,3" newline bitfld.long 0x0 0. "INTEN_MSTR_AWMISC_INFO_EP,INTEN_MSTR_AWMISC_INFO_EP" "0,1" line.long 0x4 "CTRL_0,CTRL_0" bitfld.long 0x4 31. "APP_FLR_VF_DONE_7,Indicates that FLR a virtual function has been completed which means the application has completed initializing its data structures for the function and there are no more TLPs associated with this function in the application's transmit.." "0,1" newline bitfld.long 0x4 30. "APP_FLR_VF_DONE_6,Similar to above." "0,1" newline bitfld.long 0x4 29. "APP_FLR_VF_DONE_5,Similar to above." "0,1" newline bitfld.long 0x4 28. "APP_FLR_VF_DONE_4,Similar to above." "0,1" newline bitfld.long 0x4 27. "APP_FLR_VF_DONE_3,Similar to above." "0,1" newline bitfld.long 0x4 26. "APP_FLR_VF_DONE_2,Similar to above." "0,1" newline bitfld.long 0x4 25. "APP_FLR_VF_DONE_1,Similar to above." "0,1" newline bitfld.long 0x4 24. "APP_FLR_VF_DONE_0,Similar to above." "0,1" newline bitfld.long 0x4 23. "APP_FLR_PF_DONE_1,Indicates that FLR a physical function has been completed which means the application has completed initializing its data structures for the function and there are no more TLPs associated with this function in the application's.." "0,1" newline bitfld.long 0x4 22. "APP_FLR_PF_DONE_0,Similar to above." "0,1" newline bitfld.long 0x4 21. "OUTBAND_PWRUP_CMD_1,Wake Up. If PME is enabled and PME support is configured for current PMCSR D-state asserting this signal causes the controller to wake from either L1 or L2 state. When the controller has transitioned back to the L0 state it transmits.." "0,1" newline bitfld.long 0x4 20. "OUTBAND_PWRUP_CMD_0,Similar to above." "0,1" newline bitfld.long 0x4 19. "APP_REQ_EXIT_L1,Application request to Exit L1. Request from your application to exit L1.It is only effective when L1 is enabled." "0,1" newline bitfld.long 0x4 18. "APP_REQ_ENTR_L1,Application request to Enter L1 ASPM state. The app_req_entr_l1 signal is for use by applications that need to control L1 entry instead of using the L1 entry timer as defined in the PCI Express Specification. It is only effective when L1.." "0,1" newline bitfld.long 0x4 17. "APP_UNLOCK_MSG,Request from your application to generate an Unlock message. You must assert this signal for one clock cycle. The controller does not return an acknowledgment or grant signal. You must not pulse the same signal again until the previous.." "0,1" newline bitfld.long 0x4 16. "APP_PM_XMT_PME_1,Wake Up. If PME is enabled and PME support is configured for current PMCSR D-state asserting this signal causes the controller to wake from either L1 or L2 state. When the controller has transitioned back to the L0 state it transmits a.." "0,1" newline bitfld.long 0x4 15. "APP_PM_XMT_PME_0,Similar to above." "0,1" newline bitfld.long 0x4 14. "APP_PM_XMT_TURNOFF,Request from your application to generate a PM_Turn_Off message.You must assert this signal for one clock cycle. The controller does not return an acknowledgment or grant signal. You must not pulse the same signal again until the.." "0,1" newline bitfld.long 0x4 13. "APP_INIT_RST,Request from your application to send a hot reset to the upstream port.The hot reset request is sent when a single cycle pulse is applied to this pin. In an upstream port you should set this input to '0'." "0,1" newline bitfld.long 0x4 12. "APP_HDR_VALID,One-clock-cycle pulse indicating that the data app_hdr_log app_err_bus app_err_func_num and app_tlp_prfx_log is valid." "0,1" newline bitfld.long 0x4 11. "APP_L1SUB_DISABLE,The application can set this input to 1'b1 to prevent entry to L1 Sub-states. This pin is used to gate the L1 sub-state enable bits from the L1 PM Substates Control 1 Register." "0,1" newline bitfld.long 0x4 10. "APP_CLK_PM_EN,Clock PM feature enabled by application. Used to inhibit the programming of the Clock PM in Link Control Register. For more details see 'L1 with Clock PM (L1 with REFCLK removal/PLL Off)'." "0,1" newline bitfld.long 0x4 9. "APP_XFER_PENDING,Indicates that your application has transfers pending and prevents the controller from entering L1. If the entry into L1 is already in progress assertion of app_xfer_pending causes an exit from L1. This is a level signal used to inform.." "0,1" newline bitfld.long 0x4 8. "APP_READY_ENTR_L23,Application Ready to Enter L23. Indication from your application that it is ready to enter the L23 state. The app_ready_entr_l23 signal is provided for applications that must control L23 entry (in case certain tasks must be performed.." "0,1" newline bitfld.long 0x4 7. "APP_CLK_REQ_N,Indicates that the application logic is ready to have reference clock removed. In designs which support reference clock removal through either L1 PM Sub-states or L1 CPM the application should set this signal to 1'b when it is ready to.." "0,1" newline bitfld.long 0x4 6. "APP_HOLD_PHY_RST,Set this signal to one before the de-assertion of power on reset to hold the PHY in reset. This can be used to configure your PHY. Synopsys PHYs can be configured through the PHY Viewport if desired. Please tie this port to zero if your.." "0,1" newline bitfld.long 0x4 5. "APP_SRIS_MODE,SRIS operating mode: 0b: non-SRIS mode 1b: SRIS mode" "0,1" newline bitfld.long 0x4 4. "APP_DBI_RO_WR_DISABLE,DBI Read-only Write Disable 0: MISC_CONTROL_1_OFF.DBI_RO_WR_EN register field is read-write. 1: MISC_CONTROL_1_OFF.DBI_RO_WR_EN register field is forced to 0 and is read-only." "MISC_CONTROL_1_OFF,MISC_CONTROL_1_OFF" newline bitfld.long 0x4 3. "DEVICE_TYPE,Device/port type. Indicates the specific type of this PCI Express function. It is also used to set the 'Device/Port Type' field of the 'PCI Express Capabilities Register'. The controller uses this input to determine the operating mode of the.." "PCI Express endpoint,Legacy PCI Express endpoint" newline bitfld.long 0x4 2. "APP_LTSSM_ENABLE,To do otherwise (that is de-assert it outside of the Detect LTSSM state) causes the controller to be reset and the LTSSM moves immediately back to the Detect state. This transition is outside of the PCIe Specification and it might cause.." "0,1" newline bitfld.long 0x4 0. "APP_ERR_VFUNC_ACTIVE,Indicates the function number in app_err_vfunc_num is valid." "0,1" line.long 0x8 "CTRL_1,CTRL_1" bitfld.long 0x8 29.--31. "APP_ERR_VFUNC_NUM,The number of the virtual function that is reporting the error indicated app_err_bus valid when app_hdr_valid is asserted. Uncorrected Internal errors (app_err_bus[9]) are not recorded for virtual functions.The PCIe SR-IOV.." "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 28. "SLV_ARMISC_INFO_ATU_BYPASS,AXI Slave Read Request Internal ATU Bypass. When set it indicates that this request should not be processed by the internal address translation unit" "0,1" newline hexmask.long.word 0x8 15.--27. 1. "APP_ERR_BUS,The type of error that your application detected. The controller combines the values the app_err_bus bits with the internally-detected error signals to set the corresponding bit in the Uncorrectable or Correctable Error Status Registers:.." newline bitfld.long 0x8 14. "APP_REQ_RETRY_EN,Provides a capability to defer incoming configuration requests until initialization is complete. When app_req_retry_en is asserted the controller completes incoming configuration requests with a configuration request retry status. Other.." "0,1" newline hexmask.long.byte 0x8 6.--13. 1. "APP_VF_REQ_RETRY_EN,Provides a per Virtual Function (VF) capability to defer incoming configuration requests until initialization is complete. When app_vf_req_retry_en is asserted for a certain VF the controller completes incoming configuration requests.." newline bitfld.long 0x8 4.--5. "APP_PF_REQ_RETRY_EN,Provides a per Physical Function (PF) capability to defer incoming configuration requests until initialization is complete. When app_pf_req_retry_en is asserted for a certain PF the controller completes incoming configuration.." "0,1,2,3" newline bitfld.long 0x8 2.--3. "APP_RAS_DES_TBA_CTRL,Controls the start/end of time based analysis. You must only set the pins to the required value for the duration of one clock cycle. This signal must be 2'b00 while the TIMER_START field in TIME_BASED_ANALYSIS_CONTROL_REG register is.." "No action,Start,End,Reserved" newline bitfld.long 0x8 1. "APP_RAS_DES_SD_HOLD_LTSSM,Hold and release LTSSM. For as long as this signal is '1' thecontroller stays in the current LTSSM." "0,1" newline bitfld.long 0x8 0. "SYS_AUX_PWR_DET,Auxiliary Power Detected. Used to report to the host software that auxiliary power (Vaux) is present." "0,1" line.long 0xC "CTRL_2,CTRL_2" bitfld.long 0xC 30.--31. "SYS_PWR_FAULT_DET,Power Fault Detected. Indicates the power controller detected a power fault at this slot. There is a separate sys_pwr_fault_det input bit for each function in your controller configuration." "0,1,2,3" newline bitfld.long 0xC 28.--29. "SYS_MRL_SENSOR_STATE,MRL Sensor State. Indicates the state of the manually-operated retention latch (MRL) sensor: 0: MRL is closed 1: MRL is open There is a separate sys_mrl_sensor_state input bit for each function in your controller configuration." "MRL is closed,MRL is open,?,?" newline bitfld.long 0xC 26.--27. "SYS_PRE_DET_STATE,Presence Detect State. Indicates whether or not a card is present in the slot: 0: Slot is empty 1: Card is present in the slot" "Slot is empty,Card is present in the slot,?,?" newline bitfld.long 0xC 24.--25. "SYS_ATTEN_BUTTON_PRESSED,Attention Button Pressed. Indicates that the system attention button was pressed sets the Attention Button Pressed bit in the Slot Status Register." "0,1,2,3" newline bitfld.long 0xC 23. "TX_LANE_FLIP_EN,Performs manual lane reversal for transmit lanes. For use when automatic lane reversal does not occur because lane 0 is not detected.In most cases tx_lane_flip_en should be wired to a static value at the chip level." "0,1" newline bitfld.long 0xC 22. "RX_LANE_FLIP_EN,Performs manual lane reversal for receive lanes. For use when automatic lane reversal does not occur because lane 0 is not detected.In most cases rx_lane_flip_en should be wired to a static value at the chip level." "0,1" newline bitfld.long 0xC 21. "DBG_PBA,MSIX PBA RAM Debug Mode. Use this input to activate the debug mode and allow direct read/write access to the PBA. You can also use the MSIX_RAM_CTRL_DBG_PBA field in MSIX_RAM_CTRL_OFF to activate debug mode. Debug mode turns off the.." "0,1" newline bitfld.long 0xC 20. "DBG_TABLE,MSIX Table RAM Debug Mode. Use this input to activate the debug mode and allow direct read/write access to the Table." "0,1" newline bitfld.long 0xC 19. "APP_ERR_FUNC_NUM,The number of the function that is reporting the error indicated app_err_bus valid when app_hdr_valid is asserted. Correctable and Uncorrected Internal errors (app_err_bus[10:9]) are not function specific and are recorded for all.." "0,1" newline bitfld.long 0xC 18. "APP_ERR_ADVISORY,Indicates that your application error is an advisory error. Your application should assert app_err_advisory under either of the following conditions: The controller is configured to mask completion timeout errors your application is.." "0,1" newline bitfld.long 0xC 17. "WAKEN_DO_OVRDVAL,WAKEN_DO_OVRDVAL" "0,1" newline bitfld.long 0xC 16. "WAKEN_DO_OVRDEN,WAKEN_DO_OVRDEN" "0,1" newline bitfld.long 0xC 15. "WAKEN_OE_OVRDVAL,WAKEN_OE_OVRDVAL" "0,1" newline bitfld.long 0xC 14. "WAKEN_OE_OVRDEN,WAKEN_OE_OVRDEN" "0,1" newline bitfld.long 0xC 13. "WAKEN_IN_OVRDVAL,WAKEN_IN_OVRDVAL" "0,1" newline bitfld.long 0xC 12. "WAKEN_IN_OVRDEN,WAKEN_IN_OVRDEN" "0,1" newline bitfld.long 0xC 11. "PERSTN_DO_OVRDVAL,PERSTN_DO_OVRDVAL" "0,1" newline bitfld.long 0xC 10. "PERSTN_DO_OVRDEN,PERSTN_DO_OVRDEN" "0,1" newline bitfld.long 0xC 9. "PERSTN_OE_OVRDVAL,PERSTN_OE_OVRDVAL" "0,1" newline bitfld.long 0xC 8. "PERSTN_OE_OVRDEN,PERSTN_OE_OVRDEN" "0,1" newline bitfld.long 0xC 7. "PERSTN_IN_OVRDVAL,PERSTN_IN_OVRDVAL" "0,1" newline bitfld.long 0xC 6. "PERSTN_IN_OVRDEN,PERSTN_IN_OVRDEN" "0,1" newline bitfld.long 0xC 5. "CLKREQN_DO_OVRDVAL,CLKREQN_DO_OVRDVAL" "0,1" newline bitfld.long 0xC 4. "CLKREQN_DO_OVRDEN,CLKREQN_DO_OVRDEN" "0,1" newline bitfld.long 0xC 3. "CLKREQN_OE_OVRDVAL,CLKREQN_OE_OVRDVAL" "0,1" newline bitfld.long 0xC 2. "CLKREQN_OE_OVRDEN,CLKREQN_OE_OVRDEN" "0,1" newline bitfld.long 0xC 1. "CLKREQN_IN_OVRDVAL,CLKREQN_IN_OVRDVAL" "0,1" newline bitfld.long 0xC 0. "CLKREQN_IN_OVRDEN,CLKREQN_IN_OVRDEN" "0,1" line.long 0x10 "CTRL_3,CTRL_3" bitfld.long 0x10 30.--31. "SYS_MRL_SENSOR_CHGED,MRL Sensor Changed. Indicates that the state of MRL sensor has changed. There is a separate sys_mrl_sensor_chged input bit for each function in your controller configuration." "0,1,2,3" newline hexmask.long.word 0x10 20.--29. 1. "VEN_MSG_LEN,The Length field for the vendor-defined Message TLP (indicates length of data payload in dwords).Should be set to 0x0." newline hexmask.long.byte 0x10 15.--19. 1. "VEN_MSG_TYPE,The Type field for the vendor-defined Message TLP." newline bitfld.long 0x10 12.--14. "VEN_MSG_VFUNC_NUM,Number of the virtual function accessing the VMI interface. The PCIe SR-IOV specification starts numbering VFs at 1. To ease timing during synthesis the PCIe controller starts numbering VFs at 0. For example ven_msg_vfunc_num=0 refers.." "0,1,2,3,4,5,6,7" newline bitfld.long 0x10 9.--11. "VEN_MSG_TC,The Traffic Class field for the vendor-defined Message TLP." "0,1,2,3,4,5,6,7" newline bitfld.long 0x10 7.--8. "VEN_MSG_ATTR,The Attributes field for the vendor-defined Message TLP. - Width is three bits when CX_IDO_ENABLE =1 - Width is two bits when CX_IDO_ENABLE =0" "?,Width is two bits when CX_IDO_ENABLE =0,?,?" newline bitfld.long 0x10 5.--6. "VEN_MSG_FMT,The Format field for the vendor-defined Message TLP. Should be set to 0x1." "0,1,2,3" newline bitfld.long 0x10 4. "VEN_MSG_VFUNC_ACTIVE,Indicates that a VF is accessing the VMI. - 0: No VF is active and ven_msg_vfunc_num is invalid. A PF is valid and identified by ven_msg_func_num. - 1: A VF is active and is identified by ven_msg_vfunc_num." "No VF is active and ven_msg_vfunc_num is invalid,A VF is active and is identified by.." newline bitfld.long 0x10 3. "VEN_MSG_FUNC_NUM,Function Number for the vendor-defined Message TLP. Function numbering starts at '0'." "0,1" newline bitfld.long 0x10 2. "VEN_MSG_EP,The Poisoned TLP (EP) bit for the vendor-defined Message TLP." "0,1" newline bitfld.long 0x10 1. "VEN_MSG_TD,The TLP Digest (TD) bit for the vendor-defined Message TLP valid when ven_msg_req is asserted." "0,1" newline bitfld.long 0x10 0. "VEN_MSG_REQ,Request from your application to send a vendor-defined Message. Once asserted ven_msg_req must remain asserted until the controller asserts ven_msg_grant." "0,1" repeat 16. (list 0x4 0x5 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF 0x10 0x11 0x13 0x14 0x15 0x17 )(list 0x0 0x4 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x3C 0x40 0x44 0x4C ) group.long ($2+0x78)++0x3 line.long 0x0 "CTRL_$1,CTRL_4" hexmask.long 0x0 0.--31. 1. "VEN_MSG_DATA_31_0,Third and fourth dwords of the Vendor Defined Message header where: - Bytes 8-11 (third header dword) =ven_msg_data[63:32] - Bytes 12-15 (fourth header dword) =ven_msg_data[31:0] where ven_msg_data[7:0] =byte 15" repeat.end repeat 12. (list 0x19 0x1A 0x1B 0x1D 0x1E 0x1F 0x20 0x21 0x22 0x23 0x24 0x25 )(list 0x54 0x58 0x5C 0x64 0x68 0x6C 0x70 0x74 0x78 0x7C 0x80 0x84 ) group.long ($2+0x78)++0x3 line.long 0x0 "CTRL_$1,CTRL_4" hexmask.long 0x0 0.--31. 1. "VEN_MSG_DATA_31_0,Third and fourth dwords of the Vendor Defined Message header where: - Bytes 8-11 (third header dword) =ven_msg_data[63:32] - Bytes 12-15 (fourth header dword) =ven_msg_data[31:0] where ven_msg_data[7:0] =byte 15" repeat.end group.long 0x80++0x7 line.long 0x0 "CTRL_6,CTRL_6" bitfld.long 0x0 31. "MSI_FNSEL,MSI_FNSEL" "0,1" newline bitfld.long 0x0 30. "VEN_MSI_OVRDEN,VEN_MSI_OVRDEN" "0,1" newline bitfld.long 0x0 29. "VEN_MSI_REQ,Request from your application to send an MSI when MSI is enabled.When MSI-X is enabled instead of MSI assertion of ven_msi_req causes the controller to generate an MSI-X message. Once asserted ven_msi_req must remain asserted until the.." "0,1" newline hexmask.long.byte 0x0 24.--28. 1. "VEN_MSI_VECTOR,Used to modulate the lower five bits of the MSI Data register when multiple message mode is enabled." newline bitfld.long 0x0 21.--23. "VEN_MSI_TC,Traffic Class of the MSI request valid when ven_msi_req is asserted." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 20. "VEN_MSI_VFUNC_ACTIVE,Indicates that the MSI request is coming from a VF. - 0: No VF is active and ven_msi_vfunc_num is invalid. A PF is valid and identified by ven_msi_func_num. - 1: A VF is active and is identified by ven_msi_vfunc_num." "No VF is active and ven_msi_vfunc_num is invalid,A VF is active and is identified by.." newline bitfld.long 0x0 17.--19. "VEN_MSI_VFUNC_NUM,Identifies the VF which is making the MSI request. The PCIe SR-IOV specification starts numbering VFs at 1. To ease timing during synthesis the PCIe controller starts numbering VFs at 0. For example ven_msi_vfunc_num=0 refers to the.." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 16. "VEN_MSI_FUNC_NUM,The function number of the MSI request. Function numbering starts at '0'." "0,1" newline hexmask.long.byte 0x0 8.--15. 1. "VEN_MSG_CODE,The Message Code for the vendor-defined Message TLP." newline hexmask.long.byte 0x0 0.--7. 1. "VEN_MSG_TAG,Tag for the vendor-defined Message TLP." line.long 0x4 "CTRL_7,CTRL_7" hexmask.long.byte 0x4 24.--31. 1. "SLV_AWMISC_INFO_P_TAG,AXI Slave Write Request Tag. Sets the TAG number for output posted requests. It is expected that your application normally sets this to '0' except when generating ATS invalidate requests." newline bitfld.long 0x4 23. "SLV_WMISC_INFO_EP,AXI Slave Write Data transaction related misc information. This is an optional signal that your application can use to poison write requests.When asserted the controller sets the Poisoned TLP (EP) bit in the TLP header of the current.." "0,1" newline bitfld.long 0x4 22. "PTM_AUTO_UPDATE_SIGNAL,Indicates that the controller should update the PTM Requester Context and Clock automatically every 10ms." "0,1" newline bitfld.long 0x4 21. "PTM_MANUAL_UPDATE_PULSE,Indicates that the controller should update the PTM Requester Context and Clock now." "0,1" newline bitfld.long 0x4 20. "PTM_EXTERNAL_MASTER_STROBE,PTM External Master Time Strobe." "0,1" newline hexmask.long.byte 0x4 12.--19. 1. "APP_VF_FRS_READY,Defers FRS messaging for a VF when set to '0'." newline bitfld.long 0x4 10.--11. "APP_PF_FRS_READY,Defers FRS messaging when set to '0'." "0,1,2,3" newline bitfld.long 0x4 9. "APP_DRS_READY,Defers DRS messaging when set to '0'." "0,1" newline bitfld.long 0x4 7.--8. "SYS_EML_INTERLOCK_ENGAGED,System Electromechanical Interlock Engaged. Indicates whether the system electromechanical interlock is engaged and controls the state of the Electromechanical Interlock Status bit in the Slot Status register." "0,1,2,3" newline bitfld.long 0x4 5.--6. "SYS_CMD_CPLED_INT,Command completed Interrupt. Indicates that the Hot-Plug controller completed a command. There is a separate sys_cmd_cpled_int input bit for each function in your controller configuration." "0,1,2,3" newline bitfld.long 0x4 3.--4. "SYS_PRE_DET_CHGED,Presence Detect Changed. Indicates that the state of card present detector has changed. There is a separate sys_pre_det_chged input bit for each function in your controller configuration." "0,1,2,3" newline bitfld.long 0x4 0.--2. "DIAG_CTRL_BUS,Diagnostic Control Bus - x01: Insert LCRC error by inverting the LSB of LCRC - x10: Insert ECRC error by inverting the LSB of ECRC The rising edge of these two signals ([1:0]) enable the controller to assert an LCRC or ECRC to the packet.." "?,Insert LCRC error by inverting the LSB of LCRC,?,?,?,?,?,?" group.long 0xB0++0x3 line.long 0x0 "CTRL_18,CTRL_18" bitfld.long 0x0 31. "SLV_USER_SEL,SLV_USER_SEL" "0,1" newline bitfld.long 0x0 29.--30. "MSTR_ARUSER_OVRDVAL_33_32,MSTR_ARUSER_OVRDVAL_33_32" "0,1,2,3" newline bitfld.long 0x0 27.--28. "MSTR_AWUSER_OVRDVAL_33_32,MSTR_AWUSER_OVRDVAL_33_32" "0,1,2,3" newline bitfld.long 0x0 26. "APP_LTR_MSG_FUNC_NUM,APP_LTR_MSG_FUNC_NUM" "0,1" newline bitfld.long 0x0 25. "APP_LTR_MSG_REQ,APP_LTR_MSG_REQ" "0,1" newline bitfld.long 0x0 24. "APP_PM_VF_XMT_PME_7,APP_PM_VF_XMT_PME_7" "0,1" newline bitfld.long 0x0 23. "APP_PM_VF_XMT_PME_6,APP_PM_VF_XMT_PME_6" "0,1" newline bitfld.long 0x0 22. "APP_PM_VF_XMT_PME_5,APP_PM_VF_XMT_PME_5" "0,1" newline bitfld.long 0x0 21. "APP_PM_VF_XMT_PME_4,APP_PM_VF_XMT_PME_4" "0,1" newline bitfld.long 0x0 20. "APP_PM_VF_XMT_PME_3,APP_PM_VF_XMT_PME_3" "0,1" newline bitfld.long 0x0 19. "APP_PM_VF_XMT_PME_2,APP_PM_VF_XMT_PME_2" "0,1" newline bitfld.long 0x0 18. "APP_PM_VF_XMT_PME_1,APP_PM_VF_XMT_PME_1" "0,1" newline bitfld.long 0x0 17. "APP_PM_VF_XMT_PME_0,APP_PM_VF_XMT_PME_0" "0,1" newline hexmask.long.word 0x0 4.--16. 1. "MSTR_RMISC_INFO,MSTR_RMISC_INFO" newline bitfld.long 0x0 2.--3. "MSTR_RMISC_INFO_CPL_STAT,MSTR_RMISC_INFO_CPL_STAT" "0,1,2,3" newline bitfld.long 0x0 0.--1. "MSTR_BMISC_INFO_CPL_STAT,MSTR_BMISC_INFO_CPL_STAT" "0,1,2,3" group.long 0xC0++0x3 line.long 0x0 "CTRL_22,CTRL_22" bitfld.long 0x0 31. "SLV_WMISC_INFO_SILENTDROP,SLV_WMISC_INFO_SILENTDROP" "0,1" newline bitfld.long 0x0 28.--30. "SLV_AWMISC_INFO_VFUNC_NUM,SLV_AWMISC_INFO_VFUNC_NUM" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 27. "SLV_AWMISC_INFO_VFUNC_ACTIVE,SLV_AWMISC_INFO_VFUNC_ACTIVE" "0,1" newline bitfld.long 0x0 26. "SLV_AWMISC_INFO_FUNC_NUM,SLV_AWMISC_INFO_FUNC_NUM" "0,1" newline bitfld.long 0x0 25. "SLV_AWMISC_INFO_ATU_BYPASS,SLV_AWMISC_INFO_ATU_BYPASS" "0,1" newline hexmask.long 0x0 0.--24. 1. "SLV_AWMISC_INFO,SLV_AWMISC_INFO" group.long 0xC8++0x3 line.long 0x0 "CTRL_24,CTRL_24" bitfld.long 0x0 30.--31. "MSTR_USER_SEL,MSTR_USER_SEL" "0,1,2,3" newline bitfld.long 0x0 27.--29. "SLV_ARMISC_INFO_VFUNC_NUM,SLV_ARMISC_INFO_VFUNC_NUM" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 26. "SLV_ARMISC_INFO_VFUNC_ACTIVE,SLV_ARMISC_INFO_VFUNC_ACTIVE" "0,1" newline bitfld.long 0x0 25. "SLV_ARMISC_INFO_FUNC_NUM,SLV_ARMISC_INFO_FUNC_NUM" "0,1" newline hexmask.long 0x0 0.--24. 1. "SLV_ARMISC_INFO,SLV_ARMISC_INFO" group.long 0xD8++0x3 line.long 0x0 "CTRL_28,CTRL_28" hexmask.long.word 0x0 21.--31. 1. "RSVD0,RSVD0" newline hexmask.long.byte 0x0 13.--20. 1. "APP_BUS_NUM,APP_BUS_NUM" newline hexmask.long.byte 0x0 8.--12. 1. "APP_DEV_NUM,APP_DEV_NUM" newline bitfld.long 0x0 7. "APP_MSI_CTRL_EN,APP_MSI_CTRL_EN" "0,1" newline hexmask.long.byte 0x0 0.--6. 1. "STS_DEBUG_SEL,STS_DEBUG_SEL" repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x4 0x8 0xC 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C ) group.long ($2+0x100)++0x3 line.long 0x0 "MAP_$1,MAP_0" hexmask.long 0x0 0.--31. 1. "LUT_MAP_MID_31_0,LUT_MAP_MID_31_0" repeat.end repeat 16. (list 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1A 0x1B 0x1C 0x1D 0x1E 0x1F )(list 0x40 0x44 0x48 0x4C 0x50 0x54 0x58 0x5C 0x60 0x64 0x68 0x6C 0x70 0x74 0x78 0x7C ) group.long ($2+0x100)++0x3 line.long 0x0 "MAP_$1,MAP_0" hexmask.long 0x0 0.--31. 1. "LUT_MAP_MID_31_0,LUT_MAP_MID_31_0" repeat.end repeat 16. (list 0x20 0x21 0x22 0x23 0x24 0x25 0x26 0x27 0x28 0x29 0x2A 0x2B 0x2C 0x2D 0x2E 0x2F )(list 0x80 0x84 0x88 0x8C 0x90 0x94 0x98 0x9C 0xA0 0xA4 0xA8 0xAC 0xB0 0xB4 0xB8 0xBC ) group.long ($2+0x100)++0x3 line.long 0x0 "MAP_$1,MAP_0" hexmask.long 0x0 0.--31. 1. "LUT_MAP_MID_31_0,LUT_MAP_MID_31_0" repeat.end repeat 16. (list 0x30 0x31 0x32 0x33 0x34 0x35 0x36 0x37 0x38 0x39 0x3A 0x3B 0x3C 0x3D 0x3E 0x3F )(list 0xC0 0xC4 0xC8 0xCC 0xD0 0xD4 0xD8 0xDC 0xE0 0xE4 0xE8 0xEC 0xF0 0xF4 0xF8 0xFC ) group.long ($2+0x100)++0x3 line.long 0x0 "MAP_$1,MAP_0" hexmask.long 0x0 0.--31. 1. "LUT_MAP_MID_31_0,LUT_MAP_MID_31_0" repeat.end rgroup.long 0x200++0x3 line.long 0x0 "STS_0,STS_0" bitfld.long 0x0 29.--31. "PM_L1SUB_STATE,Power management L1 sub-states FSM state" "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x0 24.--28. 1. "PM_MASTER_STATE,Power management master FSM state." newline bitfld.long 0x0 22.--23. "PM_PME_EN,PME Enable bit in the PMCSR. There is 1 bit of pm_pme_en for each configured function." "0,1,2,3" newline hexmask.long.byte 0x0 16.--21. 1. "PM_DSTATE,The current power management D-state of the function: - 000b: D0 - 001b: D1 - 010b: D2 - 011b: D3 - 100b: Uninitialized - Other values: Not applicable" newline bitfld.long 0x0 13.--15. "PM_CURNT_STATE,Indicates the current power state. The pm_curnt_state output is intended for debugging purposes not for system operation." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 12. "PM_L1_ENTRY_STARTED,L1 entry process is in progress." "0,1" newline bitfld.long 0x0 11. "PM_LINKST_IN_L1SUB,Power management is in L1 substate. Indicates when the link has entered L1 substates." "0,1" newline bitfld.long 0x0 10. "PM_LINKST_L2_EXIT,Power management is exiting L2 state. Not applicable for downstream port." "0,1" newline bitfld.long 0x0 9. "PM_LINKST_IN_L2,Power management is in L2 state." "0,1" newline bitfld.long 0x0 8. "PM_LINKST_IN_L1,Power management is in L1 state." "0,1" newline bitfld.long 0x0 7. "PM_LINKST_IN_L0S,Power management is in L0s state. Indicates in L0_STALL state when M-PCIe" "0,1" newline hexmask.long.byte 0x0 1.--6. 1. "SMLH_LTSSM_STATE,Current state of the LTSSM. Encoding is defined as follows: 6'h00: S_DETECT_QUIET 6'h01: S_DETECT_ACT 6'h02: S_POLL_ACTIVE 6'h03: S_POLL_COMPLIANCE 6'h04: S_POLL_CONFIG 6'h05: S_PRE_DETECT_QUIET 6'h06: S_DETECT_WAIT 6'h07:.." newline bitfld.long 0x0 0. "RADM_IDLE,RADM activity status signal. The controller creates the en_radm_clk_g output by gating this signal with the output of the RADM_CLK_GATING_EN field in the CLOCK_GATING_CTRL_OFF register. For debug purposes only." "0,1" group.long 0x204++0xB line.long 0x0 "STS_1,STS_1" bitfld.long 0x0 30.--31. "TRGT_TIMEOUT_CPL_ATTR,The Attributes value of the timed out completion. - Width is three bits when CX_IDO_ENABLE =1 - Width is two bits when CX_IDO_ENABLE =0" "?,Width is two bits when CX_IDO_ENABLE =0,?,?" newline bitfld.long 0x0 27.--29. "TRGT_TIMEOUT_CPL_TC,The TC of the timed out completion." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 26. "TRGT_TIMEOUT_CPL_VFUNC_ACTIVE,Indicates that the timeout is coming from a VF (Virtual function). - 0: No VF is active and trgt_timeout_cpl_vfunc_num is invalid. A PF is valid and identified by trgt_timeout_cpl_func_num - 1: A VF is active and is.." "No VF is active and trgt_timeout_cpl_vfunc_num..,A VF is active and is identified by.." newline bitfld.long 0x0 23.--25. "TRGT_TIMEOUT_CPL_VFUNC_NUM,Indicates which virtual function (VF) timed out. The PCIe SR-IOV specification starts numbering VFs at 1. To ease timing during synthesis the PCIe controller starts numbering VFs at 0. For example trgt_timeout_cpl_ vfunc_num=0.." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 22. "TRGT_TIMEOUT_CPL_FUNC_NUM,TRGT_TIMEOUT_CPL_FUNC_NUM" "0,1" newline hexmask.long.byte 0x0 14.--21. 1. "CFG_FLR_VF_ACTIVE,Set when the software initiates FLR a virtual function by writing to the 'Initiate FLR' register bit of that function. This signal is held asserted until the reset of both the application and internal controller logic has been.." newline rbitfld.long 0x0 12.--13. "CFG_FLR_PF_ACTIVE,Set when the software initiates FLR a physical function by writing to the 'Initiate FLR' register bit of that function. This signal is held asserted until reset of both the application and controller logic has been completed." "0,1,2,3" newline rbitfld.long 0x0 10.--11. "CFG_EML_CONTROL,Electromechanical Interlock Control. The state of the Electromechanical Interlock Control bit in the Slot Control register." "0,1,2,3" newline rbitfld.long 0x0 9. "CFG_L1SUB_EN,Indicates that any of the L1 Substates are enabled in the L1 Substates Control 1 Register. Could be used by your application in a downstream port to determine when not to drive CLKREQ# such as when L1" "0,1" newline rbitfld.long 0x0 7.--8. "AUX_PM_EN,AUX_PM_EN" "0,1,2,3" newline rbitfld.long 0x0 5.--6. "PM_STATUS,PME Status bit from the PMCSR. There is 1 bit of pm_status for each configured function." "0,1,2,3" newline hexmask.long.byte 0x0 0.--4. 1. "PM_SLAVE_STATE,Power management slave FSM state." line.long 0x4 "STS_2,STS_2" bitfld.long 0x4 30.--31. "RADM_TIMEOUT_CPL_ATTR,The Attributes field of the timed out completion" "0,1,2,3" newline rbitfld.long 0x4 29. "RADM_QOVERFLOW,Pulse indicating that one or more of the P/NP/CPL receive queues have overflowed. There is a 1-bit indication for each configured virtual channel. You can connect this output to your internal error reporting mechanism." "?,bit indication for each configured virtual channel" newline rbitfld.long 0x4 28. "RADM_Q_NOT_EMPTY,Level indicating that the receive queues contain TLP header/data." "0,1" newline bitfld.long 0x4 27. "RADM_TIMEOUT_FUNC_NUM,The function Number of the timed out completion. Function numbering starts at '0'." "0,1" newline rbitfld.long 0x4 26. "RADM_XFER_PENDING,Receive request pending status. Indicates Receive TLP requests are pending that is requests sent to the RTRGT1 or RTRGT0 interfaces are awaiting a response from your application." "0,1" newline rbitfld.long 0x4 25. "EDMA_XFER_PENDING,eDMA transfer pending status. Indicates eDMA Write or Read Channel transfers are pending that is DMA Write or Read Channels have not finished transferring data." "0,1" newline rbitfld.long 0x4 24. "BRDG_DBI_XFER_PENDING,AXI Slave DBI transfer pending status. Indicates AXI DBI Slave Read or Write transfers are pending that is AXI Slave transfers are awaiting a response from the controller." "0,1" newline rbitfld.long 0x4 22.--23. "CFG_INT_DISABLE,When high a functions ability to generate INTx messages is Disabled" "0,1,2,3" newline rbitfld.long 0x4 20.--21. "CFG_CMD_CPLED_INT_EN,Slot Control Command Completed Interrupt Enable." "0,1,2,3" newline hexmask.long.byte 0x4 12.--19. 1. "TRGT_TIMEOUT_LOOKUP_ID,The target completion LUT lookup ID of the timed out completion" newline hexmask.long.word 0x4 0.--11. 1. "TRGT_TIMEOUT_CPL_LEN,The Length of the timed out completion." line.long 0x8 "STS_3,STS_3" rbitfld.long 0x8 30.--31. "CFG_PWR_CTRLER_CTRL,Controls the system power controller (from bit 10 of the Slot Control register) per function: - 0: Power On - 1: Power Off" "Power On,Power Off,?,?" newline rbitfld.long 0x8 28.--29. "CFG_END2END_TLP_PFX_BLCK,The value of the End-End TLP Prefix Blocking field in the Device Control 2 register." "0,1,2,3" newline hexmask.long.byte 0x8 23.--27. 1. "CFG_PBUS_DEV_NUM,The device number assigned to the function. The number of bits depends the value of MULTI_DEVICE_AND_BUS_PER_FUNC_EN: - If MULTI_DEVICE_AND_BUS_PER_FUNC_EN =0 there are five bits of cfg_pbus_dev_num ([4:0]) regardless of the number of.." newline hexmask.long.word 0x8 11.--22. 1. "RADM_TIMEOUT_CPL_LEN,Length (in bytes) of the timed out completion. For a split completion it indicates the number of bytes remaining to be delivered when the completion timed out." newline hexmask.long.byte 0x8 3.--10. 1. "RADM_TIMEOUT_CPL_TAG,The Tag field of the timed out completion." newline bitfld.long 0x8 0.--2. "RADM_TIMEOUT_VFUNC_NUM,Indicates which virtual function (VF) had a completion timeout. The PCIe SR-IOV specification starts numbering VFs at '1'. To ease timing during synthesis the PCIe controller starts numbering VFs at '0' ." "0,1,2,3,4,5,6,7" rgroup.long 0x210++0xB line.long 0x0 "STS_4,STS_4" bitfld.long 0x0 31. "SMLH_LTSSM_STATE_RCVRY_EQ,This status signal is asserted during all Recovery Equalization states." "0,1" newline bitfld.long 0x0 29.--30. "CFG_DLL_STATE_CHGED_EN,Slot Control DLL State Change Enable" "0,1,2,3" newline bitfld.long 0x0 27.--28. "CFG_HP_SLOT_CTRL_ACCESS,Slot Control Accessed." "0,1,2,3" newline bitfld.long 0x0 25.--26. "CFG_RELAX_ORDER_EN,Contents of the 'Enable Relaxed Ordering' field(PCIE_CAP_EN_REL_ORDER) in the 'Device Control and Status' register (DEVICE_CONTROL_DEVICE_STATUS) register." "0,1,2,3" newline bitfld.long 0x0 23.--24. "CFG_NO_SNOOP_EN,Contents of the 'Enable No Snoop' field (PCIE_CAP_EN_NO_SNOOP)in the 'Device Control and Status' register(DEVICE_CONTROL_DEVICE_STATUS) register." "0,1,2,3" newline hexmask.long.byte 0x0 15.--22. 1. "PM_VF_STATUS,PME Status bit from the VF PMCSR. There is 1 bit of pm_status for each configured function. Each bit field corresponds to one of the NVF virtual functions." newline bitfld.long 0x0 13.--14. "CFG_VF_EN,Identifies those physical functions that have virtual functions enabled." "0,1,2,3" newline bitfld.long 0x0 11.--12. "CFG_ATTEN_BUTTON_PRESSED_EN,Slot Control Attention Button Pressed Enable." "0,1,2,3" newline bitfld.long 0x0 9.--10. "CFG_PWR_FAULT_DET_EN,Slot Control Power Fault Detect Enable." "0,1,2,3" newline bitfld.long 0x0 7.--8. "CFG_MRL_SENSOR_CHGED_EN,Slot Control MRL Sensor Changed Enable." "0,1,2,3" newline bitfld.long 0x0 5.--6. "CFG_PRE_DET_CHGED_EN,Slot Control Presence Detect Changed Enable." "0,1,2,3" newline bitfld.long 0x0 4. "PTM_REQ_RESPONSE_TIMEOUT,PTM Requester Response Timeout. Single-cycle pulse indicating 100us timeout occurred while waiting for a PTM Response or PTM ResponseD message." "0,1" newline bitfld.long 0x0 3. "PTM_TRIGGER_ALLOWED,Indicates that a PTM Requester manual update trigger is allowed." "0,1" newline bitfld.long 0x0 2. "PTM_UPDATING,Indicates that a PTM update is in progress." "0,1" newline bitfld.long 0x0 1. "PTM_RESPONDER_RDY_TO_VALIDATE,PTM Responder Ready to Validate." "0,1" newline bitfld.long 0x0 0. "PTM_CONTEXT_VALID,O Context Valid." "0,1" line.long 0x4 "STS_5,STS_5" bitfld.long 0x4 30.--31. "CFG_HP_INT_EN,Slot Control Hot Plug Interrupt Enable." "0,1,2,3" newline bitfld.long 0x4 28.--29. "CFG_CRS_SW_VIS_EN,Indicates the value of the CRS Software Visibility enable bit in the Root Control register. Applicable only for RC devices." "0,1,2,3" newline bitfld.long 0x4 26.--27. "CFG_PM_NO_SOFT_RST,This is the value of the No Soft Reset bit in the Power Management Control and Status Register." "0,1,2,3" newline hexmask.long.word 0x4 16.--25. 1. "FRSQ_INT_MSG_NUM,FRSQ Interrupt Message Number." newline hexmask.long.byte 0x4 8.--15. 1. "CFG_PBUS_NUM,The primary bus number assigned to the function. The number of bits depends the value of MULTI_DEVICE_AND_BUS_PER_FUNC_EN: - If MULTI_DEVICE_AND_BUS_PER_FUNC_EN =0 there are eight bits of cfg_pbus_num ([7:0]) regardless of the number of.." newline bitfld.long 0x4 6.--7. "CFG_RCB,The value of the RCB bit in the Link Control register. There is 1 bit of cfg_rcb assigned to each configured function." "0,1,2,3" newline hexmask.long.byte 0x4 0.--5. 1. "CFG_MAX_PAYLOAD_SIZE,The value of the Max_Payload_Size field in the Device Control register.There are 3 bits of cfg_max_payload_size assigned to each configured function." line.long 0x8 "STS_6,STS_6" newline bitfld.long 0x8 2. "BRDG_SLV_XFER_PENDING,AXI Slave non-DBI transfer pending status. Indicates AXI non-DBI Slave Read or Write transfers are pending that is AXI Slave transfers are awaiting a response from the controller." "0,1" newline bitfld.long 0x8 1. "SMLH_LINK_UP,PHY Link up/down indicator: - 1: Link is up - 0: Link is down" "Link is down,Link is up" newline bitfld.long 0x8 0. "RDLH_LINK_UP,Data link layer up/down indicator: This status from the flow control initialization state machine indicates that flow control has been initiated and the Data link layer is ready to transmit and receive packets. For multi-VC designs this.." "Link is down,Link is up" group.long 0x21C++0x7 line.long 0x0 "STS_7,STS_7" bitfld.long 0x0 29.--31. "RADM_TIMEOUT_CPL_TC,The Traffic Class of the timed out completion." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 28. "RADM_TIMEOUT_VFUNC_ACTIVE,Indicates that a virtual function (VF) had a completion timeout. - 0: No VF is active and radm_timeout_vfunc_num is invalid. A PF is valid and identified by radm_timeout_func_num. - 1: A VF is active and is identified by.." "No VF is active and radm_timeout_vfunc_num is..,A VF is active and is identified by.." newline hexmask.long.word 0x0 18.--27. 1. "CFG_PCIE_CAP_INT_MSG_NUM,From bits [13:9] of the PCI Express Capabilities register used when MSI or MSI-X is enabled. Assertion of hp_msi or cfg_pme_msi along with a value cfg_pcie_cap_int_msg_num is equivalent to the controller receiving an MSI with.." newline hexmask.long.word 0x0 8.--17. 1. "CFG_AER_INT_MSG_NUM,From bits [31:27] of the Root Error Status register used when MSI or MSI-X is enabled. Assertion of cfg_aer_rc_err_msi along with a value cfg_aer_int_msg_num is equivalent to the controller receiving an MSI with the.." newline hexmask.long.byte 0x0 0.--7. 1. "CFG_VF_BME,Bus master enable bit from the Control Register in the PCI header of each VF. Each bit field corresponds to one of the NVF virtual functions." line.long 0x4 "STS_8,STS_8" hexmask.long.word 0x4 16.--31. 1. "RADM_MSG_REQ_ID,The requester ID of the received Message. - [15:8]: Bus number - [7:3]: Device number - [2:0]: Function number" newline hexmask.long.word 0x4 0.--15. 1. "CFG_INT_PIN,The cfg_int_pin indicates the configured value for the Interrupt Pin Register field in the BRIDGE_CTRL_INT_PIN_INT_LINE register." repeat 8. (list 0x9 0xA 0xF 0x10 0x11 0x12 0x15 0x16 )(list 0x0 0x4 0x18 0x1C 0x20 0x24 0x30 0x34 ) group.long ($2+0x224)++0x3 line.long 0x0 "STS_$1,STS_9" hexmask.long 0x0 0.--31. 1. "RADM_MSG_PAYLOAD_31_0,Received message header information. When a vendor-defined or ltr messageis received (radm_vendor_msg=1 or radm_ltr_msg=1) the controller maps radm_msg_payload to the Rx TLP header dwords as follows: When RX_TLP =1 - [31:0] = bytes.." repeat.end repeat 16. (list 0xB 0xC 0xD 0xE 0x14 0x17 0x18 0x1C 0x1D 0x1E 0x1F 0x20 0x21 0x22 0x23 0x24 )(list 0x0 0x4 0x8 0xC 0x24 0x30 0x34 0x44 0x48 0x4C 0x50 0x54 0x58 0x5C 0x60 0x64 ) rgroup.long ($2+0x22C)++0x3 line.long 0x0 "STS_$1,STS_11" hexmask.long 0x0 0.--31. 1. "PTM_LOCAL_CLOCK_31_0,PTM_LOCAL_CLOCK_31_0" repeat.end repeat 3. (list 0x25 0x26 0x27 )(list 0x68 0x6C 0x70 ) rgroup.long ($2+0x22C)++0x3 line.long 0x0 "STS_$1,STS_11" hexmask.long 0x0 0.--31. 1. "PTM_LOCAL_CLOCK_31_0,PTM_LOCAL_CLOCK_31_0" repeat.end group.long 0x24C++0x3 line.long 0x0 "STS_19,STS_19" hexmask.long.word 0x0 16.--31. 1. "MSTR_ARMISC_INFO_47_32,MSTR_ARMISC_INFO_47_32" newline hexmask.long.word 0x0 0.--15. 1. "MSTR_AWMISC_INFO_47_32,MSTR_AWMISC_INFO_47_32" rgroup.long 0x264++0xB line.long 0x0 "STS_25,STS_25" bitfld.long 0x0 30.--31. "CFG_MEM_SPACE_EN,CFG_MEM_SPACE_EN" "0,1,2,3" newline hexmask.long.byte 0x0 24.--29. 1. "CFG_MAX_RD_REQ_SIZE,CFG_MAX_RD_REQ_SIZE" newline bitfld.long 0x0 22.--23. "CFG_BUS_MASTER_EN,CFG_BUS_MASTER_EN" "0,1,2,3" newline bitfld.long 0x0 21. "CFG_DISABLE_LTR_CLR_MSG,CFG_DISABLE_LTR_CLR_MSG" "0,1" newline bitfld.long 0x0 20. "CFG_LTR_M_EN,CFG_LTR_M_EN" "0,1" newline hexmask.long.byte 0x0 16.--19. 1. "CFG_ATTEN_IND,CFG_ATTEN_IND" newline hexmask.long.byte 0x0 12.--15. 1. "CFG_PWR_IND,CFG_PWR_IND" newline bitfld.long 0x0 10.--11. "CFG_PF_PASID_PRIV_MODE_EN,CFG_PF_PASID_PRIV_MODE_EN" "0,1,2,3" newline bitfld.long 0x0 8.--9. "CFG_PF_PASID_EXECUTE_PERM_EN,CFG_PF_PASID_EXECUTE_PERM_EN" "0,1,2,3" newline bitfld.long 0x0 6.--7. "CFG_PF_PASID_EN,CFG_PF_PASID_EN" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "CFG_START_VFI,CFG_START_VFI" line.long 0x4 "STS_26,STS_26" hexmask.long.word 0x4 16.--31. 1. "CFG_SUBBUS_NUM,CFG_SUBBUS_NUM" newline hexmask.long.word 0x4 0.--15. 1. "CFG_2NDBUS_NUM,CFG_2NDBUS_NUM" line.long 0x8 "STS_27,STS_27" hexmask.long.byte 0x8 24.--31. 1. "PM_VF_PME_EN,PM_VF_PME_EN" newline hexmask.long.tbyte 0x8 0.--23. 1. "PM_VF_DSTATE,PM_VF_DSTATE" tree.end elif (CORENAME()=="CORTEXA55") tree "PCIE1_PF0" base ad:0x31000000 tree "PF0_TYPE1_HDR (PCI-Compatible Configuration Space Header Type1)" group.long 0x0++0x2F line.long 0x0 "TYPE1_DEV_ID_VEND_ID_REG,Device ID and Vendor ID Register." hexmask.long.word 0x0 16.--31. 1. "DEVICE_ID,Device ID. The Device ID register identifies the particular Function. This identifier is allocated by the vendor. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else.." newline hexmask.long.word 0x0 0.--15. 1. "VENDOR_ID,Vendor ID. The Vendor ID register identifies the manufacturer of the Function. Valid vendor identifiers are allocated by the PCI-SIG to ensure uniqueness. It is not permitted to populate this register with a value of FFFFh which is an invalid.." line.long 0x4 "TYPE1_STATUS_COMMAND_REG,Status and Command Register." bitfld.long 0x4 31. "DETECTED_PARITY_ERROR,Detected Parity Error. This bit is set by a Function whenever it receives a Poisoned TLP regardless of the state the Parity Error Response bit in the Command register. The bit is set when the Poisoned TLP is received by a.." "0,1" newline bitfld.long 0x4 30. "SIGNALED_SYS_ERROR,Signaled System Error. This bit is set when a Function sends an ERR_FATAL or ERR_NONFATAL Message and the SERR# Enable bit in the Command register is 1b." "0,1" newline bitfld.long 0x4 29. "RCVD_MASTER_ABORT,Received Master Abort. This bit is set when a Requester receives a Completion with Unsupported Request Completion status. The bit is set when the Unsupported Request is received by a Function's primary side." "0,1" newline bitfld.long 0x4 28. "RCVD_TARGET_ABORT,Received Target Abort. This bit is set when a Requester receives a Completion with Completer Abort Completion status. The bit is set when the Completer Abort is received by a Function's primary side." "0,1" newline bitfld.long 0x4 27. "SIGNALED_TARGET_ABORT,Signaled Target Abort. This bit is set when a Function completes a Posted or Non-Posted Request as a Completer Abort error. This applies to a Function when the Completer Abort was generated by its primary side." "0,1" newline rbitfld.long 0x4 25.--26. "DEV_SEL_TIMING,DEVSEL Timing. This field was originally described in the PCI Local Bus Specification. Its functionality does not apply to PCI Express. The controller hardwires it to 00b." "0,1,2,3" newline bitfld.long 0x4 24. "MASTER_DPE,Master Data Parity Error. This bit is set by a Function if the Parity Error Response bit in the Command register is 1b and either of the following two conditions occurs: - Port receives a Poisoned Completion going downstream - Port transmits a.." "0,1" newline rbitfld.long 0x4 23. "FAST_B2B_CAP,Fast Back-to-Back Transactions Capable. This bit was originally described in the PCI Local Bus Specification. Its functionality does not apply to PCI Express. The controller hardwires this bit to 0b." "0,1" newline rbitfld.long 0x4 22. "RSVDP_22,Reserved for future use." "0,1" newline rbitfld.long 0x4 21. "FAST_66MHZ_CAP,66 MHz Capable. This bit was originally described in the PCI Local Bus Specification. Its functionality does not apply to PCI Express. The controller hardwires this bit to 0b." "0,1" newline rbitfld.long 0x4 20. "CAP_LIST,Capabilities List. Indicates the presence of an Extended Capability list item. Since all PCI Express device Functions are required to implement the PCI Express Capability structure the controller hardwires this bit to 1b." "0,1" newline rbitfld.long 0x4 19. "INT_STATUS,Interrupt Status. When set indicates that an INTx emulation interrupt is pending internally in the Function. INTx emulation interrupts forwarded by Functions from the secondary side are not reflected in this bit. Setting the Interrupt Disable.." "0,1" newline rbitfld.long 0x4 17.--18. "RSVDP_17,Reserved for future use." "0,1,2,3" newline bitfld.long 0x4 16. "IMM_READINESS,Immediate Readiness. This optional bit when set indicates the Function is guaranteed to be ready to successfully complete valid configuration accesses at any time following any reset that the host is capable of issuing Configuration.." "0,1" newline hexmask.long.byte 0x4 11.--15. 1. "RESERV,Reserved." newline bitfld.long 0x4 10. "INT_EN,Interrupt Disable. Controls the ability of a Function to generate INTx emulation interrupts. When set Functions are prevented from asserting INTx interrupts. Note: - Any INTx emulation interrupts already asserted by the Function must be.." "0,1" newline rbitfld.long 0x4 9. "RSVDP_9,Reserved for future use." "0,1" newline bitfld.long 0x4 8. "SERREN,SERR# Enable. When set this bit enables reporting upstream of Non-fatal and Fatal errors detected by the Function. Note: The errors are reported if enabled either through this bit or through the PCI Express specific bits in the Device Control.." "0,1" newline rbitfld.long 0x4 7. "IDSEL,IDSEL Stepping/Wait Cycle Control. This bit was originally described in the PCI Local Bus Specification. Its functionality does not apply to PCI Express. The controller hardwires this bit to 0b." "0,1" newline bitfld.long 0x4 6. "PERREN,Parity Error Response. This bit controls the logging of poisoned TLPs in the Master Data Parity Error bit in the Status register. For more details see the 'Error Registers' section of the PCI Express Base Specification." "0,1" newline rbitfld.long 0x4 5. "VGAPS,VGA Palette Snoop. This bit was originally described in the PCI Local Bus Specification and the PCI-to-PCI Bridge Architecture Specification. Its functionality does not apply to PCI Express. The controller hardwires this bit to 0b." "0,1" newline rbitfld.long 0x4 4. "MWI_EN,Memory Write and Invalidate. This bit was originally described in the PCI Local Bus Specification and the PCI-to-PCI Bridge Architecture Specification. Its functionality does not apply to PCI Express. The controller hardwires this bit to 0b. For.." "0,1" newline rbitfld.long 0x4 3. "SCO,Special Cycle Enable. This bit was originally described in the PCI Local Bus Specification. Its functionality does not apply to PCI Express. The controller hardwires this bit to 0b." "0,1" newline bitfld.long 0x4 2. "BME,Bus Master Enable. This bit controls forwarding of Memory or I/O requests by a port in the Upstream direction. When this bit is 0b Memory and I/O Requests received at a Root Port must be handled as Unsupported Requests (UR) For Non-Posted Requests a.." "0,1" newline bitfld.long 0x4 1. "MSE,Memory Space Enable. This bit controls a Function's response to Memory Space accesses received on its primary side. - When set the Function is enabled to decode the address and further process Memory Space accesses. - When clear all received Memory.." "0,1" newline bitfld.long 0x4 0. "IO_EN,IO Space Enable. This bit controls a Function's response to I/O Space accesses received on its primary side. - When set the Function is enabled to decode the address and further process I/O Space accesses. - When clear all received I/O accesses.." "0,1" line.long 0x8 "TYPE1_CLASS_CODE_REV_ID_REG,Class Code and Revision ID Register." hexmask.long.byte 0x8 24.--31. 1. "BASE_CLASS_CODE,Base Class Code. A code that broadly classifies the type of operation the Function performs. Encodings for base class are provided in the PCI Code and ID Assignment Specification. All unspecified encodings are reserved. Note: The access.." newline hexmask.long.byte 0x8 16.--23. 1. "SUBCLASS_CODE,Sub-Class Code. Specifies a base class sub-class which identifies more specifically the operation of the Function. Encodings for sub-class are provided in the PCI Code and ID Assignment Specification. All unspecified encodings are.." newline hexmask.long.byte 0x8 8.--15. 1. "PROGRAM_INTERFACE,Programming Interface. This field identifies a specific register level programming interface (if any) so that device independent software can interact with the Function. Encodings for interface are provided in the PCI Code and ID.." newline hexmask.long.byte 0x8 0.--7. 1. "REVISION_ID,Revision ID. The value of this field specifies a Function specific revision identifier. The value is chosen by the vendor. Zero is an acceptable value. The Revision ID should be viewed as a vendor defined extension to the Device ID. Note: The.." line.long 0xC "TYPE1_BIST_HDR_TYPE_LAT_CACHE_LINE_SIZE_REG,BIST. Header Type. Latency Timer. and Cache Line Size Register." hexmask.long.byte 0xC 24.--31. 1. "BIST,BIST. This register is used for control and status of BIST. Functions that do not support BIST must hardwire the register to 00h. A Function whose BIST is invoked must not prevent normal operation of the PCI Express Link. Bit descriptions: - [31]:.." newline rbitfld.long 0xC 23. "MULTI_FUNC,Multi-Function Device. - When set indicates that the device may contain multiple Functions but not necessarily. Software is permitted to probe for Functions other than Function 0. - When clear software must not probe for Functions other.." "0,1" newline hexmask.long.byte 0xC 16.--22. 1. "HEADER_TYPE,Header Layout. This field identifies the layout of the second part of the predefined header. The controller uses 000 0001b encoding. The encoding 000 0010b is reserved. This encoding was originally described in the PC Card Standard Electrical.." newline hexmask.long.byte 0xC 8.--15. 1. "LATENCY_MASTER_TIMER,Latency Timer. This register is also referred to as Primary Latency Timer. The Latency Timer was originally described in the PCI Local Bus Specification and the PCI-to-PCI Bridge Architecture Specification. Its functionality does not.." newline hexmask.long.byte 0xC 0.--7. 1. "CACHE_LINE_SIZE,Cache Line Size. The Cache Line Size register is programmed by the system firmware or the operating system to system cache line size. However legacy conventional PCI software may not always be able to program this register correctly.." line.long 0x10 "BAR0_REG,BAR0 Register. System software must build a consistent address map before booting the machine to an operating system. This means it has to determine how much memory is in the system. and how much address space the Functions in the system.." hexmask.long 0x10 4.--31. 1. "BAR0_START,BAR0 Base Address. - Memory Space: Base Address. - IO Space: bits[31:2] are used to map the function into IO space/Base. Address. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R(Sticky)/W(Sticky) if.." newline bitfld.long 0x10 3. "BAR0_PREFETCH,BAR0 Prefetchable. - Memory Space: Set to one if data is pre-fetchable. A Function is permitted to mark a range as prefetchable. If there are no side effects on reads the function returns all bytes on reads regardless of the byte enables.." "0,1" newline bitfld.long 0x10 1.--2. "BAR0_TYPE,BAR0 Type. - Memory Space: Base Address registers that map into Memory Space can be 32 bits or 64 bits wide (to support mapping into a 64-bit address space). The bit encoding is as follows: -- 00: Base register is 32 bits wide and can be mapped.." "Base register is 32 bits wide and can be mapped..,Reserved,?,?" newline bitfld.long 0x10 0. "BAR0_MEM_IO,BAR0 Memory Space Indicator. This bit is used to determine whether the register maps into Memory or I/O Space. Base Address registers that map to Memory Space must return a 0b. Base Address registers that map to I/O Space must return a 1b." "0,1" line.long 0x14 "BAR1_REG,BAR1 Register. System software must build a consistent address map before booting the machine to an operating system. This means it has to determine how much memory is in the system. and how much address space the Functions in the system.." hexmask.long 0x14 4.--31. 1. "BAR1_START,BAR1 Base Address. - Memory Space: Base Address. - IO Space: bits[31:2] are used to map the function into IO space/Base. Address. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R(Sticky)/W(Sticky) if.." newline bitfld.long 0x14 3. "BAR1_PREFETCH,BAR1 Prefetchable. - Memory Space: Set to one if data is pre-fetchable. A Function is permitted to mark a range as prefetchable. If there are no side effects on reads the function returns all bytes on reads regardless of the byte enables.." "0,1" newline bitfld.long 0x14 1.--2. "BAR1_TYPE,BAR1 Type. - Memory Space: Base Address registers that map into Memory Space can be 32 bits or 64 bits wide (to support mapping into a 64-bit address space). The bit encoding is as follows: -- 00: Base register is 32 bits wide and can be mapped.." "Base register is 32 bits wide and can be mapped..,Reserved,?,?" newline bitfld.long 0x14 0. "BAR1_MEM_IO,BAR1 Memory Space Indicator. This bit is used to determine whether the register maps into Memory or I/O Space. Base Address registers that map to Memory Space must return a 0b. Base Address registers that map to I/O Space must return a 1b." "0,1" line.long 0x18 "SEC_LAT_TIMER_SUB_BUS_SEC_BUS_PRI_BUS_REG,Secondary Latency Timer. Subordinate Bus Number. Secondary Bus Number. and Primary Bus Number Register." hexmask.long.byte 0x18 24.--31. 1. "SEC_LAT_TIMER,Secondary Latency Timer. This register does not apply to PCI Express. The controller hardwires it to 00h." newline hexmask.long.byte 0x18 16.--23. 1. "SUB_BUS,Subordinate Bus Number. The Subordinate Bus Number register is used to record the bus number of the highest numbered PCI bus segment which is behind (or subordinate to) the bridge. Configuration software programs the value in this register. The.." newline hexmask.long.byte 0x18 8.--15. 1. "SEC_BUS,Secondary Bus Number. The Secondary Bus Number register is used to record the bus number of the PCI bus segment to which the secondary interface of the bridge is connected. Configuration software programs the value in this register. The bridge.." newline hexmask.long.byte 0x18 0.--7. 1. "PRIM_BUS,Primary Bus Number. This register is not used by PCI Express Functions. It is implemented for compatibility with legacy software." line.long 0x1C "SEC_STAT_IO_LIMIT_IO_BASE_REG,Secondary Status. and I/O Limit and Base Register. The I/O Limit and I/O Base registers are optional and define an address range that is used by the bridge to determine when to forward I/O transactions from one interface to.." bitfld.long 0x1C 31. "SEC_STAT_DPE,Detected Parity Error. This bit is set by a Function when a Poisoned TLP is received by its secondary side regardless of the state the Parity Error Response Enable bit in the Bridge Control register." "0,1" newline bitfld.long 0x1C 30. "SEC_STAT_RCVD_SYS_ERR,Received System Error. This bit is set when the secondary side of a Function receives an ERR_FATAL or ERR_NONFATAL message." "0,1" newline bitfld.long 0x1C 29. "SEC_STAT_RCVD_MSTR_ABRT,Received Master Abort. This bit is set when the secondary side of a Function (for requests initiated by the Type 1 header Function itself) receives a Completion with Unsupported Request Completion status." "0,1" newline bitfld.long 0x1C 28. "SEC_STAT_RCVD_TRGT_ABRT,Received Target Abort. This bit is set when the secondary side of a Function (for requests initiated by the Type 1 header Function itself) receives a Completion with Completer Abort Completion status." "0,1" newline bitfld.long 0x1C 27. "SEC_STAT_SIG_TRGT_ABRT,Signaled Target Abort. This bit is set when the secondary side of the Function (for Requests completed by the Type 1 header Function itself) completes a Posted or Non-Posted request as a Completer Abort error." "0,1" newline rbitfld.long 0x1C 25.--26. "RSVDP_25,Reserved for future use." "0,1,2,3" newline bitfld.long 0x1C 24. "SEC_STAT_MDPE,Master Data Parity Error. This bit is set by a Function if the Parity Error Response Enable bit in the Bridge Control register is set and either of the following two conditions occurs: - Port receives a Poisoned Completion coming Upstream.." "0,1" newline rbitfld.long 0x1C 23. "RSVDP_23,Reserved for future use." "0,1" newline hexmask.long.byte 0x1C 16.--22. 1. "SEC_STAT_RESERV,Reserved." newline hexmask.long.byte 0x1C 12.--15. 1. "IO_LIMIT,I/O Limit Address. These bits correspond to the address[15:12] of IO address range. For the purpose of address decoding the bridge assumes that the lower 12 address bits address[11:0] of the I/O limit address (not implemented in the I/O Limit.." newline rbitfld.long 0x1C 9.--11. "IO_RESERV1,Reserved." "0,1,2,3,4,5,6,7" newline bitfld.long 0x1C 8. "IO_DECODE_BIT8,I/O Addressing Encode (IO Limit Address). This bit encodes the IO addressing capability of the bridge. IO_DECODE_BIT8 indicates the following: - 0h: The bridge supports only 16-bit I/O addressing (for ISA compatibility). For the purpose of.." "0,1" newline hexmask.long.byte 0x1C 4.--7. 1. "IO_BASE,I/O Base Address. These bits correspond to the address[15:12] of IO address range. For the purpose of address decoding the bridge assumes that the lower 12 address bits address[11:0] of the I/O base address (not implemented in the I/O Base.." newline rbitfld.long 0x1C 1.--3. "IO_RESERV,Reserved." "0,1,2,3,4,5,6,7" newline bitfld.long 0x1C 0. "IO_DECODE,I/O Addressing Encode (IO Base Address) This bit encodes the IO addressing capability of the bridge. IO_DECODE indicates the following: - 0h: The bridge supports only 16-bit I/O addressing (for ISA compatibility). For the purpose of address.." "0,1" line.long 0x20 "MEM_LIMIT_MEM_BASE_REG,Memory Limit and Base Register. The Memory Limit and Memory Base registers define a memory mapped address range which is used by the bridge to determine when to forward memory transactions from one interface to the other. If there.." hexmask.long.word 0x20 20.--31. 1. "MEM_LIMIT,Memory Limit Address. These bits correspond to the upper 12 address bits Address[31:20] of 32-bit addresses. For the purpose of address decoding the bridge assumes that the lower 20 address bits Address[19:0] of the memory limit address.." newline hexmask.long.byte 0x20 16.--19. 1. "MEM_LIMIT_RESERV,Reserved." newline hexmask.long.word 0x20 4.--15. 1. "MEM_BASE,Memory Base Address. These bits correspond to the upper 12 address bits Address[31:20] of 32-bit addresses. For the purpose of address decoding the bridge assumes that the lower 20 address bits Address[19:0] of the memory base address (not.." newline hexmask.long.byte 0x20 0.--3. 1. "MEM_BASE_RESERV,Reserved." line.long 0x24 "PREF_MEM_LIMIT_PREF_MEM_BASE_REG,Prefetchable Memory Limit and Base Register. The Prefetchable Memory Limit and Prefetchable Memory Base registers must indicate that 64-bit addresses are supported. as defined in PCI-to-PCI Bridge Architecture.." hexmask.long.word 0x24 20.--31. 1. "PREF_MEM_LIMIT,Prefetchable Memory Limit Address. If the Prefetchable Memory Limit register indicates support for 32-bit addressing then the Prefetchable Limit Upper 32 Bits register is implemented as a read-only register that returns zero when read. If.." newline rbitfld.long 0x24 17.--19. "PREF_RESERV1,Reserved." "0,1,2,3,4,5,6,7" newline rbitfld.long 0x24 16. "PREF_MEM_LIMIT_DECODE,Prefetchable Memory Limit Decode. This bit encodes whether or not the bridge supports 64-bit addresses. Note: This bit is a copy of the PREF_MEM_DECODE bit and always reflects the current value of that bit. The value of.." "0,1" newline hexmask.long.word 0x24 4.--15. 1. "PREF_MEM_BASE,Prefetchable Memory Base Address. If the Prefetchable Memory Base register indicates support for 32-bit addressing then the Prefetchable Base Upper 32 Bits register is implemented as a read-only register that returns zero when read. If the.." newline rbitfld.long 0x24 1.--3. "PREF_RESERV,Reserved." "0,1,2,3,4,5,6,7" newline bitfld.long 0x24 0. "PREF_MEM_DECODE,Prefetchable Memory Base Decode. This bit encodes whether or not the bridge supports 64-bit addresses. Note: By default the bit is set to 1'b1 indicating that 64-bit addresses are supported. If the bridge only supports 32-bit prefetchable.." "0,1" line.long 0x28 "PREF_BASE_UPPER_REG,Prefetchable Base Upper 32 Bits Register. The Prefetchable Base Upper 32 Bits register is an optional extension to the Prefetchable Memory Base register." hexmask.long 0x28 0.--31. 1. "PREF_MEM_BASE_UPPER,Prefetchable Base Upper 32 Bit. If the Prefetchable Memory Base register indicates support for 32-bit addressing then this register is implemented as read-only register that returns zero when read. If the Prefetchable Memory Base.." line.long 0x2C "PREF_LIMIT_UPPER_REG,Prefetchable Limit Upper 32 Bits Register. The Prefetchable Limit Upper 32 Bits register is an optional extension to the Prefetchable Memory Limit register." hexmask.long 0x2C 0.--31. 1. "PREF_MEM_LIMIT_UPPER,Prefetchable Limit Upper 32 Bit. If the Prefetchable Memory Limit register indicate support for 64-bit addressing then this register is implemented as read/write register which must be initialized by configuration software. This.." rgroup.long 0x30++0x3 line.long 0x0 "IO_LIMIT_UPPER_IO_BASE_UPPER_REG,I/O Limit and Base Upper 16 Bits Register. The I/O Limit Upper 16 Bits and I/O Base Upper 16 Bits registers are optional extensions to the I/O Limit and I/O Base registers." hexmask.long.word 0x0 16.--31. 1. "IO_LIMIT_UPPER,I/O Limit Upper 16 Bits. If the I/O Limit register indicates support for 16-bit I/O address decoding then this register is implemented as a read-only register which return zero when read. If the I/O Limit register indicates support for.." newline hexmask.long.word 0x0 0.--15. 1. "IO_BASE_UPPER,I/O Base Upper 16 Bits. If the I/O Base register indicates support for 16-bit I/O address decoding then this register is implemented as a read-only register which return zero when read. If the I/O base register indicates support for 32-bit.." group.long 0x34++0xB line.long 0x0 "TYPE1_CAP_PTR_REG,Capabilities Pointer Register." hexmask.long.tbyte 0x0 8.--31. 1. "RSVDP_8,Reserved for future use." newline hexmask.long.byte 0x0 0.--7. 1. "CAP_POINTER,Capabilities Pointer. This register is used to point to a linked list of capabilities implemented by this Function. Since all PCI Express Functions are required to implement the PCI Express Capability structure this register must point to a.." line.long 0x4 "TYPE1_EXP_ROM_BASE_REG,Expansion ROM Base Address Register. This register is defined to handle the base address and size information for this expansion ROM. The mask for this ROM BAR exists (if implemented) as a shadow register at this address. The.." hexmask.long.tbyte 0x4 11.--31. 1. "EXP_ROM_BASE_ADDRESS,Expansion ROM Base Address. Upper 21 bits of the Expansion ROM base address. The number of bits (out of these 21) that a Function actually implements depends on how much address space the Function requires. The mask for this ROM BAR.." newline hexmask.long.word 0x4 1.--10. 1. "RSVDP_1,Reserved for future use." newline bitfld.long 0x4 0. "ROM_BAR_ENABLE,Expansion ROM Enable. This bit controls whether or not the Function accepts accesses to its expansion ROM. When this bit is 0b the Function's expansion ROM address space is disabled. When the bit is 1b address decoding is enabled using.." "0,1" line.long 0x8 "BRIDGE_CTRL_INT_PIN_INT_LINE_REG,Bridge Control. Interrupt Pin. and Interrupt Line Register." hexmask.long.word 0x8 23.--31. 1. "BRIDGE_CTRL_RESERV,Reserved." newline bitfld.long 0x8 22. "SBR,Secondary Bus Reset. Setting this bit triggers a hot reset on the corresponding PCI Express Port. Software must ensure a minimum reset duration (Trst) as defined in the PCI Local Bus Specification. Software and systems must honor.." "0,1" newline rbitfld.long 0x8 21. "MSTR_ABORT_MODE,Master Abort Mode. This bit was originally described in the PCI-to-PCI Bridge Architecture Specification. Its functionality does not apply to PCI Express. The controller hardwires this bit to 0b. Note: The access attributes of this field.." "0,1" newline rbitfld.long 0x8 20. "VGA_16B_DEC,VGA 16 bit decode. This bit only has meaning if VGA Enable bit is set. This bit enables system configuration software to select between 10-bit and 16-bit I/O address decoding for all VGA I/O register accesses that are forwarded from primary.." "0,1" newline rbitfld.long 0x8 19. "VGA_EN,VGA Enable. Modifies the response by the bridge to VGA compatible addresses. If the VGA Enable bit is set the bridge will positively decode and forward the following accesses on the primary interface to the secondary interface (and conversely.." "0,1" newline bitfld.long 0x8 18. "ISA_EN,ISA Enable. Modifies the response by the bridge to ISA I/O addresses. This applies only to I/O addresses that are enabled by the I/O Base and I/O Limit registers and are in the first 64 KB of I/O address space (0000 0000h to 0000 FFFFh). If this.." "?,KB block" newline bitfld.long 0x8 17. "SERR_EN,SERR# Enable. This bit controls forwarding of ERR_COR ERR_NONFATAL and ERR_FATAL from secondary to primary." "0,1" newline bitfld.long 0x8 16. "PERE,Parity Error Response Enable. This bit controls the logging of poisoned TLPs in the Master Data Parity Error bit in the Secondary Status register." "0,1" newline hexmask.long.byte 0x8 8.--15. 1. "INT_PIN,Interrupt PIN. The Interrupt Pin register register that identifies the legacy interrupt Message(s) the Function uses. Valid values are: - 01h 02h 03h and 04h: map to legacy interrupt Messages for INTA INTB INTC and INTD respectively. - 00h:.." newline hexmask.long.byte 0x8 0.--7. 1. "INT_LINE,Interrupt Line. The Interrupt Line register communicates interrupt line routing information. The register must be implemented by any Function that uses an interrupt pin. Values in this register are programmed by system software and are system.." tree.end tree "PF0_SPCIE_CAP (Secondary PCI Express Capability Structure)" group.long (0x0+0x1A0)++0xF line.long 0x0 "SPCIE_CAP_HEADER_REG,SPCIE Capability Header. For a description of this standard PCIe register. see the PCI Express Specification." hexmask.long.word 0x0 20.--31. 1. "NEXT_OFFSET,Next Capability Offset. For a description of this standard PCIe register field see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky).." hexmask.long.byte 0x0 16.--19. 1. "CAP_VERSION,Capability Version. For a description of this standard PCIe register field see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else.." hexmask.long.word 0x0 0.--15. 1. "EXTENDED_CAP_ID,Secondary PCI Express Extended Capability ID. For a description of this standard PCIe register field see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN.." line.long 0x4 "LINK_CONTROL3_REG,Link Control 3 Register. For a description of this standard PCIe register. see the PCI Express Specification." hexmask.long 0x4 2.--31. 1. "RSVDP_2,Reserved for future use." bitfld.long 0x4 1. "EQ_REQ_INT_EN,Link Equalization Request Interrupt Enable. For a description of this standard PCIe register field see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" "0,1" bitfld.long 0x4 0. "PERFORM_EQ,Perform Equalization. For a description of this standard PCIe register field see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" "0,1" line.long 0x8 "LANE_ERR_STATUS_REG,Lane Error Status Register. For a description of this standard PCIe register. see the PCI Express Specification." hexmask.long 0x8 2.--31. 1. "RSVDP_LANE_ERR_STATUS,Reserved for future use." bitfld.long 0x8 0.--1. "LANE_ERR_STATUS,Lane Error Status Bits per Lane. For a description of this standard PCIe register field see the PCI Express Specification." "0,1,2,3" line.long 0xC "SPCIE_CAP_OFF_0CH_REG,Lane Equalization Control Register for lanes 1 and 0. For a description of this standard PCIe register. see the PCI Express Specification." rbitfld.long 0xC 31. "RSVDP_31,Reserved for future use." "0,1" bitfld.long 0xC 28.--30. "USP_RX_PRESET_HINT1,Upstream Port 8.0 GT/s Receiver Preset Hint 1. The write value is gated with the PCIE_CAP_CROSS_LINK_SUPPORT field of LINK_CAPABILITIES2_REG. For a description of this standard PCIe register field see the PCI Express Specification." "0,1,2,3,4,5,6,7" hexmask.long.byte 0xC 24.--27. 1. "USP_TX_PRESET1,Upstream Port 8.0 GT/s Transmitter Preset 1. The write value is gated with the PCIE_CAP_CROSS_LINK_SUPPORT field of LINK_CAPABILITIES2_REG. For a description of this standard PCIe register field see the PCI Express Specification. Note:.." rbitfld.long 0xC 23. "RSVDP_23,Reserved for future use." "0,1" newline bitfld.long 0xC 20.--22. "DSP_RX_PRESET_HINT1,Downstream Port 8.0 GT/s Receiver Preset Hint 1. For a description of this standard PCIe register field see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if.." "0,1,2,3,4,5,6,7" hexmask.long.byte 0xC 16.--19. 1. "DSP_TX_PRESET1,Downstream Port 8.0 GT/s Transmitter Preset 1. For a description of this standard PCIe register field see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN.." rbitfld.long 0xC 15. "RSVDP_15,Reserved for future use." "0,1" bitfld.long 0xC 12.--14. "USP_RX_PRESET_HINT0,Upstream Port 8.0 GT/s Receiver Preset Hint 0. The write value is gated with the PCIE_CAP_CROSS_LINK_SUPPORT field of LINK_CAPABILITIES2_REG. For a description of this standard PCIe register field see the PCI Express Specification." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0xC 8.--11. 1. "USP_TX_PRESET0,Upstream Port 8.0 GT/s Transmitter Preset 0. The write value is gated with the PCIE_CAP_CROSS_LINK_SUPPORT field of LINK_CAPABILITIES2_REG. For a description of this standard PCIe register field see the PCI Express Specification. Note:.." rbitfld.long 0xC 7. "RSVDP_7,Reserved for future use." "0,1" bitfld.long 0xC 4.--6. "DSP_RX_PRESET_HINT0,Downstream Port 8.0 GT/s Receiver Preset Hint 0. For a description of this standard PCIe register field see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if.." "0,1,2,3,4,5,6,7" hexmask.long.byte 0xC 0.--3. 1. "DSP_TX_PRESET0,Downstream Port 8.0 GT/s Transmitter Preset 0. For a description of this standard PCIe register field see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN.." tree.end tree "PF0_L1SUB_CAP (L1 Substates Capability Structure)" group.long (0x0+0x2E8)++0xF line.long 0x0 "L1SUB_CAP_HEADER_REG,L1 Substates Extended Capability Header. This register provides capbility ID. capability version and next offset value for L1 Substates." hexmask.long.word 0x0 20.--31. 1. "NEXT_OFFSET,Next Capability Offset. This field contains the offset to the next PCI Express Capability structure or 000h if no other items exist in the linked list of Capabilities. For Extended Capabilities implemented in Configuration Space this offset.." hexmask.long.byte 0x0 16.--19. 1. "CAP_VERSION,Capability Version. This field is a PCI-SIG defined version number that indicates the version of the Capability structure present. This field is depends on version of the specification. Note: The access attributes of this field are as.." hexmask.long.word 0x0 0.--15. 1. "EXTENDED_CAP_ID,L1SUB Extended Capability ID. This field is a PCI-SIG defined ID number that indicates the nature and format of the Extended Capability. Extended Capability ID for L1 PM Substates is 001Eh. Note: The access attributes of this field are as.." line.long 0x4 "L1SUB_CAPABILITY_REG,L1 Substates Capability Register. This register provides extended capability of L1 Substates." hexmask.long.byte 0x4 24.--31. 1. "RSVDP_24,Reserved for future use." hexmask.long.byte 0x4 19.--23. 1. "PWR_ON_VALUE_SUPPORT,Port T Power On Value. Along with the Port T_POWER_ON Scale field in the L1 PM Substates Capabilities register sets the time (in us) that this Port requires the port on the opposite side of Link to wait in L1.2.Exit after sampling.." rbitfld.long 0x4 18. "RSVDP_18,Reserved for future use." "0,1" bitfld.long 0x4 16.--17. "PWR_ON_SCALE_SUPPORT,Port T Power On Scale. Specifies the scale used for the Port T_POWER_ON Value field in the L1 PM Substates Capabilities register. Range of values are given below. Required for all Ports for which either the PCI-PM L1.2 Supported bit.." "?,?,?,Reserved" newline hexmask.long.byte 0x4 8.--15. 1. "COMM_MODE_SUPPORT,Port Common Mode Restore Time. Time (in us) required for this Port to re-establish common mode. Required for all Ports for which either the PCI-PM L1.2 Supported bit is Set ASPM L1.2 Supported bit is Set or both are Set otherwise.." rbitfld.long 0x4 5.--7. "RSVDP_5,Reserved for future use." "0,1,2,3,4,5,6,7" bitfld.long 0x4 4. "L1_PMSUB_SUPPORT,L1 PM Substates ECN Supported. When Set this bit indicates that this Port supports L1 PM Substates. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W (sticky)" "0,1" bitfld.long 0x4 3. "L1_1_ASPM_SUPPORT,ASPM L11 Supported. When Set this bit indicates that ASPM L1.1 is supported. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W (sticky)" "0,1" newline bitfld.long 0x4 2. "L1_2_ASPM_SUPPORT,ASPM L12 Supported. When Set this bit indicates that ASPM L1.2 is supported. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W (sticky)" "0,1" bitfld.long 0x4 1. "L1_1_PCIPM_SUPPORT,PCI-PM L11 Supported. When Set this bit indicates that PCI-PM L1.1 is supported and must be Set by all Ports implementing L1 PM Substates. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W (sticky)" "0,1" bitfld.long 0x4 0. "L1_2_PCIPM_SUPPORT,PCI-PM L12 Supported. When Set this bit indicates that PCI-PM L1.2 is supported. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W (sticky)" "0,1" line.long 0x8 "L1SUB_CONTROL1_REG,L1 Substates Control 1 Register. This register provides Controls to extended capability." bitfld.long 0x8 29.--31. "L1_2_TH_SCA,LTR L12 Threshold Scale. This field provides a scale for the value contained within the LTR_L1.2_THRESHOLD_Value.The default value for this field is 000b.Hardware operation is undefined if software writes a Not-Permitted value to this field." "0,1,2,3,4,5,6,7" rbitfld.long 0x8 26.--28. "RSVDP_26,Reserved for future use." "0,1,2,3,4,5,6,7" hexmask.long.word 0x8 16.--25. 1. "L1_2_TH_VAL,LTR L12 Threshold Value. Along with the LTR_L1.2_THRESHOLD_Scale this field indicates the LTR threshold used to determine if entry into L1 results in L1.1 (if enabled) or L1.2 (if enabled). The default value for this field is 00 0000 0000b." hexmask.long.byte 0x8 8.--15. 1. "T_COMMON_MODE,Common Mode Restore Time. Sets value of TCOMMONMODE (in us) which must be used by the Downstream Ports for timing the re-establishment of common mode.This field is of type RsvdP for Upstream Ports. Default value is implementation.." newline hexmask.long.byte 0x8 4.--7. 1. "RSVDP_4,Reserved for future use." bitfld.long 0x8 3. "L1_1_ASPM_EN,ASPM L11 Enable. When Set this bit enables ASPM L1.1.For Ports for which the ASPM L1.1 Supported bit is Clear this bit is permitted to be hardwired to 0.Default value is 0b." "0,1" bitfld.long 0x8 2. "L1_2_ASPM_EN,ASPM L12 Enable. When Set this bit enables ASPM L1.2.For Ports for which the ASPM L1.2 Supported bit is Clear this bit is permitted to be hardwired to 0.Default value is 0b." "0,1" bitfld.long 0x8 1. "L1_1_PCIPM_EN,PCI-PM L11 Enable. When Set this bit enables PCI-PM L1.1. Default value is 0b." "0,1" newline bitfld.long 0x8 0. "L1_2_PCIPM_EN,PCI-PM L12 Enable. When Set this bit enables PCI-PM L1.2.For Ports for which the PCI-PM L1.2 Supported bit is Clear this bit is permitted to be hardwired to 0.Default value is 0b." "0,1" line.long 0xC "L1SUB_CONTROL2_REG,L1 Substates Control 2 Register. This register provides Controls to extended capability." hexmask.long.tbyte 0xC 8.--31. 1. "RSVDP_8,Reserved for future use." hexmask.long.byte 0xC 3.--7. 1. "T_POWER_ON_VALUE,T Power On Value. Along with the T_POWER_ON Scale sets the minimum amount of time (in us) that the Port must wait in L1.2.Exit after sampling CLKREQ# asserted before actively driving the interface.Default value is 00101b. T_POWER_ON is.." rbitfld.long 0xC 2. "RSVDP_2,Reserved for future use." "0,1" bitfld.long 0xC 0.--1. "T_POWER_ON_SCALE,T Power On Scale. Specifies the scale used for T_POWER_ON Value. Range of values are given below. Required for all Ports that support L1.2 otherwise this field is of type RsvdP. This field must only be modified when the ASPM L1.2 Enable.." "?,?,?,Reserved" tree.end tree "PF0_RAS_DES_CAP (RAS D.E.S. Capability Structure (VSEC))" group.long (0x0+0x30C)++0x3 line.long 0x0 "RAS_DES_CAP_HEADER_REG,Vendor-Specific Extended Capability Header. For a description of this standard PCIe register. see the PCI Express Specification." hexmask.long.word 0x0 20.--31. 1. "NEXT_OFFSET,Next Capability Offset. For a description of this standard PCIe register field see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky).." newline hexmask.long.byte 0x0 16.--19. 1. "CAP_VERSION,Capability Version. For a description of this standard PCIe register field see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else.." newline hexmask.long.word 0x0 0.--15. 1. "EXTENDED_CAP_ID,PCI Express Extended Capability ID. For a description of this standard PCIe register field see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then.." rgroup.long (0x4+0x30C)++0x3 line.long 0x0 "VENDOR_SPECIFIC_HEADER_REG,Vendor-Specific Header. For a description of this standard PCIe register. see the PCI Express Specification." hexmask.long.word 0x0 20.--31. 1. "VSEC_LENGTH,VSEC Length. For a description of this standard PCIe register field see the PCI Express Specification." newline hexmask.long.byte 0x0 16.--19. 1. "VSEC_REV,VSEC Rev. For a description of this standard PCIe register field see the PCI Express Specification." newline hexmask.long.word 0x0 0.--15. 1. "VSEC_ID,VSEC ID. For a description of this standard PCIe register field see the PCI Express Specification." group.long (0x8+0x30C)++0x3 line.long 0x0 "EVENT_COUNTER_CONTROL_REG,Event Counter Control. This is a viewport control register. - Setting the EVENT_COUNTER_EVENT_SELECT and EVENT_COUNTER_LANE_SELECT fields in this register determine the Event Counter data returned by the EVENT_COUNTER_DATA_REG.." hexmask.long.byte 0x0 28.--31. 1. "RSVDP_28,Reserved for future use." newline hexmask.long.word 0x0 16.--27. 1. "EVENT_COUNTER_EVENT_SELECT,Event Counter Data Select. This field in conjunction with the EVENT_COUNTER_LANE_SELECT field indexes the Event Counter data returned by the EVENT_COUNTER_DATA_REG register. - 27-24: Group number(4-bit: 0..0x7) - 23-16: Event.." newline hexmask.long.byte 0x0 12.--15. 1. "RSVDP_12,Reserved for future use." newline hexmask.long.byte 0x0 8.--11. 1. "EVENT_COUNTER_LANE_SELECT,Event Counter Lane Select. This field in conjunction with EVENT_COUNTER_EVENT_SELECT indexes the Event Counter data returned by the EVENT_COUNTER_DATA_REG register. - 0x0: Lane0 - 0x1: Lane1 - 0x2: Lane2 - .. - 0xF: Lane15 Note:.." newline rbitfld.long 0x0 7. "EVENT_COUNTER_STATUS,Event Counter Status. This register returns the current value of the Event Counter selected by the following fields: - EVENT_COUNTER_EVENT_SELECT - EVENT_COUNTER_LANE_SELECT Note: This register field is sticky." "0,1" newline rbitfld.long 0x0 5.--6. "RSVDP_5,Reserved for future use." "0,1,2,3" newline bitfld.long 0x0 2.--4. "EVENT_COUNTER_ENABLE,Event Counter Enable. Enables/disables the Event Counter selected by the EVENT_COUNTER_EVENT_SELECT and EVENT_COUNTER_LANE_SELECT fields in this register. By default all event counters are disabled. You can enable/disable a specific.." "no change,per event off,?,?,?,?,?,?" newline bitfld.long 0x0 0.--1. "EVENT_COUNTER_CLEAR,Event Counter Clear. Clears the Event Counter selected by the EVENT_COUNTER_EVENT_SELECT and EVENT_COUNTER_LANE_SELECT fields in this register. You can clear the value of a specific Event Counter by writing the 'per clear' code and.." "no change,per clear,?,?" rgroup.long (0xC+0x30C)++0x3 line.long 0x0 "EVENT_COUNTER_DATA_REG,Event Counter Data. This viewport register returns the data selected by the following fields: - EVENT_COUNTER_EVENT_SELECT in EVENT_COUNTER_CONTROL_REG - EVENT_COUNTER_LANE_SELECT in EVENT_COUNTER_CONTROL_REG For more details. see.." hexmask.long 0x0 0.--31. 1. "EVENT_COUNTER_DATA,Event Counter Data. This register returns the data selected by the following fields: - EVENT_COUNTER_EVENT_SELECT in EVENT_COUNTER_CONTROL_REG - EVENT_COUNTER_LANE_SELECT in EVENT_COUNTER_CONTROL_REG Note: This register field is sticky." group.long (0x10+0x30C)++0x3 line.long 0x0 "TIME_BASED_ANALYSIS_CONTROL_REG,Time-based Analysis Control. Used for controlling the measurement of RX/TX data throughput and time spent in each low-power LTSSM state. For more details. see the RAS DES section in the Core Operations chapter of the.." hexmask.long.byte 0x0 24.--31. 1. "TIME_BASED_REPORT_SELECT,Time-based Report Select. Selects what type of data is measured for the selected duration (TIME_BASED_DURATION_SELECT) and returned in TIME_BASED_ANALYSIS_DATA. Each type of data is measured using one of three types of units: -.." newline hexmask.long.byte 0x0 16.--23. 1. "RSVDP_16,Reserved for future use." newline hexmask.long.byte 0x0 8.--15. 1. "TIME_BASED_DURATION_SELECT,Time-based Duration Select. Selects the duration of time-based analysis. When 'manual control' is selected and TIMER_START is set to '1' this analysis never stops until TIMER_STOP is set to '0'. - 0x0: Manual control - 0x1:.." newline hexmask.long.byte 0x0 1.--7. 1. "RSVDP_1,Reserved for future use." newline bitfld.long 0x0 0. "TIMER_START,Timer Start. - 1: Start/Restart - 0: Stop This bit will be cleared automatically when the measurement is finished. Note: The app_ras_des_tba_ctrl input also sets the contents of this field and controls the measurement start/stop. Note: This.." "Stop,Start/Restart" rgroup.long (0x14+0x30C)++0x7 line.long 0x0 "TIME_BASED_ANALYSIS_DATA_REG,Time-based Analysis Data. Contains the measurement results of RX/TX data throughput and time spent in each low-power LTSSM state. This viewport register returns the data selected by the TIME_BASED_REPORT_SELECT field in.." hexmask.long 0x0 0.--31. 1. "TIME_BASED_ANALYSIS_DATA,Time Based Analysis Data. This register returns the data selected by the TIME_BASED_REPORT_SELECT field in TIME_BASED_ANALYSIS_CONTROL_REG. The results are cleared when next measurement starts. Note: This register field is sticky." line.long 0x4 "TIME_BASED_ANALYSIS_DATA_63_32_REG,Upper 32 bits of Time-based Analysis Data. This viewport register returns the data selected by the TIME_BASED_REPORT_SELECT field in TIME_BASED_ANALYSIS_CONTROL_REG. For more details. see the RAS DES section in the Core.." hexmask.long 0x4 0.--31. 1. "TIME_BASED_ANALYSIS_DATA_63_32,Upper 32 bits of Time Based Analysis Data. Note: This register field is sticky." group.long (0x30+0x30C)++0x5F line.long 0x0 "EINJ_ENABLE_REG,Error Injection Enable. Each type of error insertion is enabled by the corresponding bit in this register. The specific injection controls for each type of error are defined in the following registers: - 0: CRC Error: EINJ0_CRC_REG - 1:.." hexmask.long 0x0 7.--31. 1. "RSVDP_7,Reserved for future use." newline bitfld.long 0x0 6. "ERROR_INJECTION6_ENABLE,Error Injection6 Enable (Specific TLP Error). Enables insertion of errors into the packets that you select. You can set this bit to '1' when you have disabled RAS datapath protection (DP) by setting CX_RASDP = CX_RASDP_RAM_PROT.." "0,1" newline bitfld.long 0x0 5. "ERROR_INJECTION5_ENABLE,Error Injection5 Enable (TLP Duplicate/Nullify Error). Enables insertion of duplicate/nullified TLPs. For more details see the EINJ5_SP_TLP_REG register. Note: This register field is sticky." "0,1" newline bitfld.long 0x0 4. "ERROR_INJECTION4_ENABLE,Error Injection4 Enable (FC Credit Update Error). Enables insertion of errors into UpdateFCs. For more details see the EINJ4_FC_REG register. Note: This register field is sticky." "0,1" newline bitfld.long 0x0 3. "ERROR_INJECTION3_ENABLE,Error Injection3 Enable (Symbol DataK Mask Error or Sync Header Error). Enables DataK masking of special symbols or the breaking of the sync header. For more details see the EINJ3_SYMBOL_REG register. Note: This register field is.." "0,1" newline bitfld.long 0x0 2. "ERROR_INJECTION2_ENABLE,Error Injection2 Enable (DLLP Error). Enables insertion of DLLP errors. For more details see the EINJ2_DLLP_REG register. Note: This register field is sticky." "0,1" newline bitfld.long 0x0 1. "ERROR_INJECTION1_ENABLE,Error Injection1 Enable (Sequence Number Error). Enables insertion of errors into sequence numbers. For more details see the EINJ1_SEQNUM_REG register. Note: This register field is sticky." "0,1" newline bitfld.long 0x0 0. "ERROR_INJECTION0_ENABLE,Error Injection0 Enable (CRC Error). Enables insertion of errors into various CRC. For more details see the EINJ0_CRC_REG register. Note: This register field is sticky." "0,1" line.long 0x4 "EINJ0_CRC_REG,Error Injection Control 0 (CRC Error). Controls the insertion of errors into the CRC. and parity of ordered sets for the selected type of the packets as follows: - LCRC. Bad TLP will be detected at the receiver side; receiver responds with.." hexmask.long.tbyte 0x4 12.--31. 1. "RSVDP_12,Reserved for future use." newline hexmask.long.byte 0x4 8.--11. 1. "EINJ0_CRC_TYPE,Error injection type. Selects the type of CRC error to be inserted. Tx Path - 0000b: New TLP's LCRC error injection - 0001b: 16bCRC error injection of ACK/NAK DLLP - 0010b: 16bCRC error injection of Update-FC DLLP - 0011b: New TLP's ECRC.." newline hexmask.long.byte 0x4 0.--7. 1. "EINJ0_COUNT,Error injection count. Indicates the number of errors. This register is decremented when the errors have been inserted. - If the counter value is 0x01 and error is inserted ERROR_INJECTION0_ENABLE in EINJ_ENABLE_REG returns 0b. - If the.." line.long 0x8 "EINJ1_SEQNUM_REG,Error Injection Control 1 (Sequence Number Error). Controls the sequence number of the specific TLPs and ACK/NAK DLLPs. Data Link Protocol Error will be detected at the Rx side of ACK/NAL DLLPs when one of these conditions is true: -.." rbitfld.long 0x8 29.--31. "RSVDP_29,Reserved for future use." "0,1,2,3,4,5,6,7" newline hexmask.long.word 0x8 16.--28. 1. "EINJ1_BAD_SEQNUM,Bad sequence number. Indicates the value to add/subtract from the naturally-assigned sequence numbers. This value is represented by two's complement. - 0x0FFF: +4095 - .. - 0x0002: +2 - 0x0001: +1 - 0x0000: 0 - 0x1FFF: -1 - 0x1FFE: -2 -.." newline hexmask.long.byte 0x8 9.--15. 1. "RSVDP_9,Reserved for future use." newline bitfld.long 0x8 8. "EINJ1_SEQNUM_TYPE,Sequence number type. Selects the type of sequence number. - 0b: Insertion of New TLP's SEQ# error - 1b: Insertion of ACK/NAK DLLP's SEQ# Error Note: This register field is sticky." "0,1" newline hexmask.long.byte 0x8 0.--7. 1. "EINJ1_COUNT,Error injection count. Indicates the number of errors. This register is decremented as the errors are being inserted. - If the counter value is 0x01 and error is inserted ERROR_INJECTION1_ENABLE in EINJ_ENABLE_REG returns '0'. - If the.." line.long 0xC "EINJ2_DLLP_REG,Error Injection Control 2 (DLLP Error). Controls the transmission of DLLPs and inserts the following errors: - If 'ACK/NAK DLLP's transmission block' is selected. replay timeout error will occur at the transmitter of the TLPs and then Data.." hexmask.long.tbyte 0xC 10.--31. 1. "RSVDP_10,Reserved for future use." newline bitfld.long 0xC 8.--9. "EINJ2_DLLP_TYPE,DLLP Type. Selects the type of DLLP errors to be inserted. - 00b: ACK/NAK DLLP's transmission block - 01b: Update FC DLLP's transmission block - 10b: Always Transmission for NAK DLLP - 11b: Reserved Note: This register field is sticky." "0,1,2,3" newline hexmask.long.byte 0xC 0.--7. 1. "EINJ2_COUNT,Error injection count. Indicates the number of errors. This register is decremented as the errors are being inserted. - If the counter value is 0x01 and the error is inserted ERROR_INJECTION2_ENABLE in EINJ_ENABLE_REG returns '0'. - If the.." line.long 0x10 "EINJ3_SYMBOL_REG,Error Injection Control 3 (Symbol Error). When 8b/10b encoding is used. this register controls error insertion into the special (K code) symbols. - If TS1/TS2/FTS/E-Idle/SKP is selected. it affects whole of the ordered set. It might.." hexmask.long.tbyte 0x10 11.--31. 1. "RSVDP_11,Reserved for future use." newline bitfld.long 0x10 8.--10. "EINJ3_SYMBOL_TYPE,Error Type. 8b/10b encoding - Mask K symbol. It is not supported to insert errors into the first ordered-set after exiting from TxElecIdle when CX_FREQ_STEP_EN has been enabled. - 000b: Reserved - 001b: COM/PAD(TS1 Order set) - 010b:.." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x10 0.--7. 1. "EINJ3_COUNT,Error injection count. Indicates the number of errors. This register is decremented as the errors are being inserted. - If the counter value is 0x01 and error is inserted ERROR_INJECTION3_ENABLE in EINJ_ENABLE_REG returns '0'. - If the.." line.long 0x14 "EINJ4_FC_REG,Error Injection Control 4 (FC Credit Error). Controls error insertion into the credit value in the UpdateFCs. It is possible to insert errors for any of the following types: - Posted TLP Header credit - Non-Posted TLP Header credit -.." rbitfld.long 0x14 29.--31. "RSVDP_29,Reserved for future use." "0,1,2,3,4,5,6,7" newline hexmask.long.word 0x14 16.--28. 1. "EINJ4_BAD_UPDFC_VALUE,Bad update-FC credit value. Indicates the value to add/subtract from the UpdateFC credit. This value is represented by two's complement. - 0x0FFF: +4095 - .. - 0x0002: +2 - 0x0001: +1 - 0x0000: 0 - 0x1FFF: -1 - 0x1FFE: -2 - .. -.." newline rbitfld.long 0x14 15. "RSVDP_15,Reserved for future use." "0,1" newline bitfld.long 0x14 12.--14. "EINJ4_VC_NUMBER,VC Number. Indicates target VC Number. Note: This register field is sticky." "0,1,2,3,4,5,6,7" newline rbitfld.long 0x14 11. "RSVDP_11,Reserved for future use." "0,1" newline bitfld.long 0x14 8.--10. "EINJ4_UPDFC_TYPE,Update-FC type. Selects the credit type. - 000b: Posted TLP Header Credit value control - 001b: Non-Posted TLP Header Credit value control - 010b: Completion TLP Header Credit value control - 011b: Reserved - 100b: Posted TLP Data Credit.." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x14 0.--7. 1. "EINJ4_COUNT,Error injection count. Indicates the number of errors. This register is decremented as the errors are being inserted. - If the counter value is 0x01 and error is inserted ERROR_INJECTION4_ENABLE in EINJ_ENABLE_REG returns '0'. - If the.." line.long 0x18 "EINJ5_SP_TLP_REG,Error Injection Control 5 (Specific TLP Error). Controls the generation of specified TLPs. Correctable errors will occur which will be fixed by the PCIe protocol. - For Duplicate TLP. the controller initiates Data Link Retry by handling.." hexmask.long.tbyte 0x18 9.--31. 1. "RSVDP_9,Reserved for future use." newline bitfld.long 0x18 8. "EINJ5_SPECIFIED_TLP,Specified TLP. Selects the specified TLP to be inserted. - 0: Generates duplicate TLPs by handling ACK DLLP as NAK DLLP. - 1: Generates Nullified TLP (Original TLP will be stored in retry buffer). Note: This register field is sticky." "Generates duplicate TLPs by handling ACK DLLP as..,Generates Nullified TLP" newline hexmask.long.byte 0x18 0.--7. 1. "EINJ5_COUNT,Error injection count. Indicates the number of errors. This register is decremented as the errors are being inserted. - If the counter value is 0x01 and error is inserted ERROR_INJECTION5_ENABLE in EINJ_ENABLE_REG returns '0'. - If the.." line.long 0x1C "EINJ6_COMPARE_POINT_H0_REG,Error Injection Control 6 (Compare Point Header DWORD #0). Program this register for the 1st DWORD of TLP header/prefix. It is necessary to carefully consider the endianness when you program this register. Bits [31:0] =.." hexmask.long 0x1C 0.--31. 1. "EINJ6_COMPARE_POINT_H0,Packet Compare Point: 1st DWORD. Specifies which Tx TLP header DWORD#0 bits to compare with the corresponding bits in the Packet Compare Value registers (EINJ6_COMPARE_VALUE*). When all specified bits (in the Tx TLP header and.." line.long 0x20 "EINJ6_COMPARE_POINT_H1_REG,Error Injection Control 6 (Compare Point Header DWORD #1). Program this register for the 2nd DWORD of TLP header/prefix. It is necessary to carefully consider the endianness when you program this register. Bits [31:0] =.." hexmask.long 0x20 0.--31. 1. "EINJ6_COMPARE_POINT_H1,Packet Compare Point: 2nd DWORD. Specifies which Tx TLP header DWORD#1 bits to compare with the corresponding bits in the Packet Compare Value registers (EINJ6_COMPARE_VALUE*). When all specified bits (in the Tx TLP header and.." line.long 0x24 "EINJ6_COMPARE_POINT_H2_REG,Error Injection Control 6 (Compare Point Header DWORD #2). Program this register for the 3rd DWORD of TLP header/prefix. It is necessary to carefully consider the endianness when you program this register. Bits [31:0] =.." hexmask.long 0x24 0.--31. 1. "EINJ6_COMPARE_POINT_H2,Packet Compare Point: 3rd DWORD. Specifies which Tx TLP header DWORD#2 bits to compare with the corresponding bits in the Packet Compare Value registers (EINJ6_COMPARE_VALUE*). When all specified bits (in the Tx TLP header and.." line.long 0x28 "EINJ6_COMPARE_POINT_H3_REG,Error Injection Control 6 (Compare Point Header DWORD #3). Program this register for the 4th DWORD of TLP header/prefix. It is necessary to carefully consider the endianness when you program this register. Bits [31:0] =.." hexmask.long 0x28 0.--31. 1. "EINJ6_COMPARE_POINT_H3,Packet Compare Point: 4th DWORD. Specifies which Tx TLP header DWORD#3 bits to compare with the corresponding bits in the Packet Compare Value registers (EINJ6_COMPARE_VALUE*). When all specified bits (in the Tx TLP header and.." line.long 0x2C "EINJ6_COMPARE_VALUE_H0_REG,Error Injection Control 6 (Compare Value Header DWORD #0). Program this register for the 1st DWORD of TLP header/prefix. It is necessary to carefully consider the endianness when you program this register. Bits [31:0] =.." hexmask.long 0x2C 0.--31. 1. "EINJ6_COMPARE_VALUE_H0,Packet Compare Value: 1st DWORD. Specifies the value to compare against Tx the TLP header DWORD#0 bits specified in the Packet Compare Point registers (EINJ6_COMPARE_POINT*). Note: This register field is sticky." line.long 0x30 "EINJ6_COMPARE_VALUE_H1_REG,Error Injection Control 6 (Compare Value Header DWORD #1). Program this register for the 2nd DWORD of TLP header/prefix. It is necessary to carefully consider the endianness when you program this register. Bits [31:0] =.." hexmask.long 0x30 0.--31. 1. "EINJ6_COMPARE_VALUE_H1,Packet Compare Value: 2nd DWORD. Specifies the value to compare against Tx the TLP header DWORD#1 bits specified in the Packet Compare Point registers (EINJ6_COMPARE_POINT*). Note: This register field is sticky." line.long 0x34 "EINJ6_COMPARE_VALUE_H2_REG,Error Injection Control 6 (Compare Value Header DWORD #2). Program this register for the 3rd DWORD of TLP header/prefix. It is necessary to carefully consider the endianness when you program this register. Bits [31:0] =.." hexmask.long 0x34 0.--31. 1. "EINJ6_COMPARE_VALUE_H2,Packet Compare Value: 3rd DWORD. Specifies the value to compare against Tx the TLP header DWORD#2 bits specified in the Packet Compare Point registers (EINJ6_COMPARE_POINT*). Note: This register field is sticky." line.long 0x38 "EINJ6_COMPARE_VALUE_H3_REG,Error Injection Control 6 (Compare Value Header DWORD #3). Program this register for the 4th DWORD of TLP header/prefix. It is necessary to carefully consider the endianness when you program this register. Bits [31:0] =.." hexmask.long 0x38 0.--31. 1. "EINJ6_COMPARE_VALUE_H3,Packet Compare Value: 4th DWORD. Specifies the value to compare against Tx the TLP header DWORD#3 bits specified in the Packet Compare Point registers (EINJ6_COMPARE_POINT*). Note: This register field is sticky." line.long 0x3C "EINJ6_CHANGE_POINT_H0_REG,Error Injection Control 6 (Change Point Header DWORD #0). Program this register for the 1st DWORD of TLP header/prefix. It is necessary to carefully consider the endianness when you program this register. Bits [31:0] =.." hexmask.long 0x3C 0.--31. 1. "EINJ6_CHANGE_POINT_H0,Packet Change Point: 1st DWORD. Specifies which Tx TLP header DWORD#0 bits to replace with the corresponding bits in the Packet Change Value registers (EINJ6_CHANGE_VALUE*). Note: This register field is sticky." line.long 0x40 "EINJ6_CHANGE_POINT_H1_REG,Error Injection Control 6 (Change Point Header DWORD #1). Program this register for the 2nd DWORD of TLP header/prefix. It is necessary to carefully consider the endianness when you program this register. Bits [31:0] =.." hexmask.long 0x40 0.--31. 1. "EINJ6_CHANGE_POINT_H1,Packet Change Point: 2nd DWORD. Specifies which Tx TLP header DWORD#1 bits to replace with the corresponding bits in the Packet Change Value registers (EINJ6_CHANGE_VALUE*). Note: This register field is sticky." line.long 0x44 "EINJ6_CHANGE_POINT_H2_REG,Error Injection Control 6 (Change Point Header DWORD #2). Program this register for the 3rd DWORD of TLP header/prefix. It is necessary to carefully consider the endianness when you program this register. Bits [31:0] =.." hexmask.long 0x44 0.--31. 1. "EINJ6_CHANGE_POINT_H2,Packet Change Point: 3rd DWORD. Specifies which Tx TLP header DWORD#2 bits to replace with the corresponding bits in the Packet Change Value registers (EINJ6_CHANGE_VALUE*). Note: This register field is sticky." line.long 0x48 "EINJ6_CHANGE_POINT_H3_REG,Error Injection Control 6 (Change Point Header DWORD #3). Program this register for the 4th DWORD of TLP header/prefix. It is necessary to carefully consider the endianness when you program this register. Bits [31:0] =.." hexmask.long 0x48 0.--31. 1. "EINJ6_CHANGE_POINT_H3,Packet Change Point: 4th DWORD. Specifies which Tx TLP header DWORD#3 bits to replace with the corresponding bits in the Packet Change Value registers (EINJ6_CHANGE_VALUE*). Note: This register field is sticky." line.long 0x4C "EINJ6_CHANGE_VALUE_H0_REG,Error Injection Control 6 (Change Value Header DWORD #0). Program this register for the 1st DWORD of TLP header/prefix. It is necessary to carefully consider the endianness when you program this register. Bits [31:0] =.." hexmask.long 0x4C 0.--31. 1. "EINJ6_CHANGE_VALUE_H0,Packet Change Value: 1st DWORD. Specifies replacement values for the Tx TLP header DWORD#0 bits defined in the Packet Change Point registers (EINJ6_CHANGE_POINT*). Only applies when the EINJ6_INVERTED_CONTROL field in EINJ6_TLP_REG.." line.long 0x50 "EINJ6_CHANGE_VALUE_H1_REG,Error Injection Control 6 (Change Value Header DWORD #1). Program this register for the 2nd DWORD of TLP header/prefix. It is necessary to carefully consider the endianness when you program this register. Bits [31:0] =.." hexmask.long 0x50 0.--31. 1. "EINJ6_CHANGE_VALUE_H1,Packet Change Value: 2nd DWORD. Specifies replacement values for the Tx TLP header DWORD#1 bits defined in the Packet Change Point registers (EINJ6_CHANGE_POINT*). Only applies when the EINJ6_INVERTED_CONTROL field in EINJ6_TLP_REG.." line.long 0x54 "EINJ6_CHANGE_VALUE_H2_REG,Error Injection Control 6 (Change Value Header DWORD #2). Program this register for the 3rd DWORD of TLP header/prefix. It is necessary to carefully consider the endianness when you program this register. Bits [31:0] =.." hexmask.long 0x54 0.--31. 1. "EINJ6_CHANGE_VALUE_H2,Packet Change Value: 3rd DWORD. Specifies replacement values for the Tx TLP header DWORD#2 bits defined in the Packet Change Point registers (EINJ6_CHANGE_POINT*). Only applies when the EINJ6_INVERTED_CONTROL field in EINJ6_TLP_REG.." line.long 0x58 "EINJ6_CHANGE_VALUE_H3_REG,Error Injection Control 6 (Change Value Header DWORD #3). Program this register for the 4th DWORD of TLP header/prefix. It is necessary to carefully consider the endianness when you program this register. Bits [31:0] =.." hexmask.long 0x58 0.--31. 1. "EINJ6_CHANGE_VALUE_H3,Packet Change Value: 4th DWORD. Specifies replacement values for the Tx TLP header DWORD#3 bits defined in the Packet Change Point registers (EINJ6_CHANGE_POINT*). Only applies when the EINJ6_INVERTED_CONTROL field in EINJ6_TLP_REG.." line.long 0x5C "EINJ6_TLP_REG,Error Injection Control 6 (Packet Error). The Packet Compare Point registers (EINJ6_COMPARE_POINT*) specify which Tx TLP header bits to compare with the corresponding bits in the Packet Compare Value registers (EINJ6_COMPARE_VALUE*). When.." hexmask.long.tbyte 0x5C 12.--31. 1. "RSVDP_12,Reserved for future use." newline bitfld.long 0x5C 9.--11. "EINJ6_PACKET_TYPE,Packet type. Selects the TLP packets to inject errors into. - 0: TLP Header - 1: TLP Prefix 1st 4-DWORDs - 2: TLP Prefix 2nd -DWORDs - Else: Reserved Note: This register field is sticky." "TLP Header,TLP Prefix 1st 4-DWORDs,TLP Prefix 2nd -DWORDs,?,?,?,?,?" newline bitfld.long 0x5C 8. "EINJ6_INVERTED_CONTROL,Inverted Error Injection Control. - 0: EINJ6_CHANGE_VALUE_H[0/1/2/3] is used to replace bits specified by EINJ6_CHANGE_POINT_H[0/1/2/3]. - 1: EINJ6_CHANGE_VALUE_H[0/1/2/3] is ignored and inverts bits specified by.." "EINJ6_CHANGE_VALUE_H[0/1/2/3] is used to replace..,EINJ6_CHANGE_VALUE_H[0/1/2/3] is ignored and.." newline hexmask.long.byte 0x5C 0.--7. 1. "EINJ6_COUNT,Error Injection Count. Indicates the number of errors to insert. This counter is decremented while errors are been inserted. - If the counter value is 0x01 and error is inserted ERROR_INJECTION6_ENABLE in EINJ_ENABLE_REG returns '0'. - If.." group.long (0xA0+0x30C)++0x7 line.long 0x0 "SD_CONTROL1_REG,Silicon Debug Control 1. For more details. see the RAS DES section in the Core Operations chapter of the Databook." hexmask.long.byte 0x0 24.--31. 1. "RSVDP_24,Reserved for future use." newline bitfld.long 0x0 22.--23. "LOW_POWER_INTERVAL,Low Power Entry Interval Time. Interval Time that the controller starts monitoring RXELECIDLE signal after L0s/L1/L2 entry. You should set the value according to the latency from receiving EIOS to RXELECIDLE assertion at the PHY. -.." "0,1,2,3" newline bitfld.long 0x0 20.--21. "TX_EIOS_NUM,Number of Tx EIOS. This register sets the number of transmit EIOS for L0s/L1 entry and Disable/Loopback/Hot-reset exit. The controller selects the greater value between this register and the value defined by the PCI-SIG specification. 2.5GT/s.." "0,1,2,3" newline rbitfld.long 0x0 17.--19. "RSVDP_17,Reserved for future use." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 16. "FORCE_DETECT_LANE_EN,Force Detect Lane Enable. When this bit is set the controller ignores receiver detection from PHY during LTSSM Detect state and uses FORCE_DETECT_LANE. Note: This register field is sticky." "0,1" newline hexmask.long.word 0x0 0.--15. 1. "FORCE_DETECT_LANE,Force Detect Lane. When the FORCE_DETECT_LANE_EN field is set the controller ignores receiver detection from PHY during LTSSM Detect state and uses this value instead. - 0: Lane0 - 1: Lane1 - 2: Lane2 - .. - 15: Lane15 Note: This.." line.long 0x4 "SD_CONTROL2_REG,Silicon Debug Control 2. For more details. see the RAS DES section in the Core Operations chapter of the Databook." hexmask.long.word 0x4 17.--31. 1. "RSVDP_17,Reserved for future use." newline bitfld.long 0x4 16. "FRAMING_ERR_RECOVERY_DISABLE,Framing Error Recovery Disable. This bit disables a transition to Recovery state when a Framing Error is occurred. Note: This register field is sticky." "0,1" newline hexmask.long.byte 0x4 11.--15. 1. "RSVDP_11,Reserved for future use." newline bitfld.long 0x4 10. "DIRECT_LPBKSLV_TO_EXIT,Direct Loopback Slave To Exit. When this bit is set and the LTSSM is in Loopback Slave Active State the LTSSM transitions to Loopback Slave Exit state. Note: This register field is sticky." "0,1" newline bitfld.long 0x4 9. "DIRECT_POLCOMP_TO_DETECT,Direct Polling.Compliance to Detect. When this bit is set and the LTSSM is in Polling Compliance State the LTSSM transitions to Detect state. Note: This register field is sticky." "0,1" newline bitfld.long 0x4 8. "DIRECT_RECIDLE_TO_CONFIG,Direct Recovery.Idle to Configuration. When this bit is set and the LTSSM is in Recovery Idle State the LTSSM transitions to Configuration state. Note: This register field is sticky." "0,1" newline hexmask.long.byte 0x4 3.--7. 1. "RSVDP_3,Reserved for future use." newline bitfld.long 0x4 2. "NOACK_FORCE_LINKDOWN,Force LinkDown. When this bit is set and the controller detects REPLY_NUM rolling over 4 times the LTSSM transitions to Detect State. Note: This register field is sticky." "0,1" newline bitfld.long 0x4 1. "RECOVERY_REQUEST,Recovery Request. When this bit is set to '1' in L0 or L0s the LTSSM starts transitioning to Recovery State. This request does not cause a speed change or re-equalization." "0,1" newline bitfld.long 0x4 0. "HOLD_LTSSM,Hold and Release LTSSM. For as long as this register is '1' the controller stays in the current LTSSM. Note: This register field is sticky." "0,1" group.long (0xB0+0x30C)++0xB line.long 0x0 "SD_STATUS_L1LANE_REG,Silicon Debug Status(Layer1 Per-lane). This viewport register returns the data selected by the following field: - LANE_SELECT in SD_STATUS_L1LANE_REG For more details. see the RAS DES section in the Core Operations chapter of the.." hexmask.long.byte 0x0 24.--31. 1. "DESKEW_POINTER,Deskew Pointer. Indicates Deskew pointer of internal Deskew buffer of selected lane number(LANE_SELECT). Note: This register field is sticky." newline rbitfld.long 0x0 21.--23. "RSVDP_21,Reserved for future use." "0,1,2,3,4,5,6,7" newline rbitfld.long 0x0 20. "PIPE_TXELECIDLE,PIPE:TxElecIdle. Indicates PIPE TXELECIDLE signal of selected lane number(LANE_SELECT). Note: This register field is sticky." "0,1" newline rbitfld.long 0x0 19. "PIPE_RXELECIDLE,PIPE:RxElecIdle. Indicates PIPE RXELECIDLE signal of selected lane number(LANE_SELECT). Note: This register field is sticky." "0,1" newline rbitfld.long 0x0 18. "PIPE_RXVALID,PIPE:RxValid. Indicates PIPE RXVALID signal of selected lane number(LANE_SELECT). Note: This register field is sticky." "0,1" newline rbitfld.long 0x0 17. "PIPE_DETECT_LANE,PIPE:Detect Lane. Indicates whether PHY indicates receiver detection or not on selected lane number(LANE_SELECT). Note: This register field is sticky." "0,1" newline rbitfld.long 0x0 16. "PIPE_RXPOLARITY,PIPE:RxPolarity. Indicates PIPE RXPOLARITY signal of selected lane number(LANE_SELECT). Note: This register field is sticky." "0,1" newline hexmask.long.word 0x0 4.--15. 1. "RSVDP_4,Reserved for future use." newline hexmask.long.byte 0x0 0.--3. 1. "LANE_SELECT,Lane Select. Lane Select register for Silicon Debug Status Register of Layer1-PerLane. - 0x0: Lane0 - 0x1: Lane1 - 0x2: Lane2 - .. - 0xF: Lane15 Note: This register field is sticky." line.long 0x4 "SD_STATUS_L1LTSSM_REG,Silicon Debug Status(Layer1 LTSSM). For more details. see the RAS DES section in the Core Operations chapter of the Databook." hexmask.long.word 0x4 16.--31. 1. "LTSSM_VARIABLE,LTSSM Variable. Indicates internal LTSSM variables defined in the PCI Express Base Specification. C-PCIe Mode: - 0: directed_speed_change - 1: changed_speed_recovery - 2: successful_speed_negotiation - 3: upconfigure_capable; Set to '1' if.." newline rbitfld.long 0x4 15. "LANE_REVERSAL,Lane Reversal Operation. Receiver detected lane reversal. This field is only valid in the L0 LTSSM state. Note: This register field is sticky." "0,1" newline hexmask.long.byte 0x4 11.--14. 1. "RSVDP_11,Reserved for future use." newline rbitfld.long 0x4 8.--10. "PIPE_POWER_DOWN,PIPE:PowerDown. Indicates PIPE PowerDown signal. Note: This register field is sticky." "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 7. "FRAMING_ERR,Framing Error. Indicates Framing Error detection status." "0,1" newline hexmask.long.byte 0x4 0.--6. 1. "FRAMING_ERR_PTR,First Framing Error Pointer. Identifies the first Framing Error using the following encoding. The field contents are only valid value when FRAMING_ERR =1. Received Unexpected Framing Token - 01h: When non- STP/SDP/IDL Token was received.." line.long 0x8 "SD_STATUS_PM_REG,Silicon Debug Status(PM). For more details. see the RAS DES section in the Core Operations chapter of the Databook." hexmask.long.byte 0x8 24.--31. 1. "RSVDP_24,Reserved for future use." newline hexmask.long.byte 0x8 16.--23. 1. "LATCHED_NFTS,Latched N_FTS. Indicates the value of N_FTS in the received TS Ordered Sets from the Link Partner Note: This register field is sticky." newline rbitfld.long 0x8 13.--15. "L1SUB_STATE,L1Sub State. Indicates internal state machine of L1Sub state. - 0h: S_L1_U : idle state - 1h: S_L1_0 : wait for aux_clk_active - 2h: S_L1_0_WAIT4_ACK : wait for pclkack - 3h: S_L1_0_WAIT4_CLKREQ : wait for clkreq - 4h: S_L1_N_ENTRY : check.." "wait for aux_clk_active,?,?,?,?,?,?,?" newline bitfld.long 0x8 12. "PME_RESEND_FLAG,PME Re-send flag. When the DUT sends a PM_PME message TLP the DUT sets PME_Status bit. If host software does not clear PME_Status bit for 100ms(+50%/-5%) the DUT resends the PM_PME Message. This bit indicates that a PM_PME was resent." "0,1" newline hexmask.long.byte 0x8 8.--11. 1. "INTERNAL_PM_SSTATE,Internal PM State(Slave). Indicates internal state machine of Power Management Slave controller. - 0h: S_IDLE - 1h: S_RESPOND_NAK - 2h: S_BLOCK_TLP - 3h: S_WAIT_LAST_TLP_ACK - 4h: S_WAIT_EIDLE - 5h: S_LINK_ENTR_L1 - 6h: S_L1 - 7h:.." newline rbitfld.long 0x8 5.--7. "RSVDP_5,Reserved for future use." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x8 0.--4. 1. "INTERNAL_PM_MSTATE,Internal PM State(Master). Indicates internal state machine of Power Management Master controller. - 00h: IDLE - 01h: L0 - 02h: L0S - 03h: ENTER_L0S - 04h: L0S_EXIT - 05h: WAIT_PMCSR_CPL_SENT - 08h: L1 - 09h: L1_BLOCK_TLP - 0Ah:.." rgroup.long (0xBC+0x30C)++0x3 line.long 0x0 "SD_STATUS_L2_REG,Silicon Debug Status(Layer2). For more details. see the RAS DES section in the Core Operations chapter of the Databook." hexmask.long.byte 0x0 28.--31. 1. "RSVDP_28,Reserved for future use." newline bitfld.long 0x0 27. "FC_INIT2,FC_INIT2. Indicates the controller is in FC_INIT2(VC0) state. Note: This register field is sticky." "0,1" newline bitfld.long 0x0 26. "FC_INIT1,FC_INIT1. Indicates the controller is in FC_INIT1(VC0) state. Note: This register field is sticky." "0,1" newline bitfld.long 0x0 24.--25. "DLCMSM,DLCMSM. Indicates the current DLCMSM. - 00b: DL_INACTIVE - 01b: DL_FC_INIT - 11b: DL_ACTIVE Note: This register field is sticky." "0,1,2,3" newline hexmask.long.word 0x0 12.--23. 1. "RX_ACK_SEQ_NO,Tx Ack Sequence Number. Indicates ACKD_SEQ which is updated by receiving ACK/NAK DLLP. Note: This register field is sticky." newline hexmask.long.word 0x0 0.--11. 1. "TX_TLP_SEQ_NO,Tx Tlp Sequence Number. Indicates next transmit sequence number for transmit TLP. Note: This register field is sticky." group.long (0xC0+0x30C)++0x7 line.long 0x0 "SD_STATUS_L3FC_REG,Silicon Debug Status(Layer3 FC). The CREDIT_DATA[0/1] fields in this viewport register return the data for the VC and TLP Type selected by the following fields: - CREDIT_SEL_VC - CREDIT_SEL_CREDIT_TYPE - CREDIT_SEL_TLP_TYPE -.." hexmask.long.word 0x0 20.--31. 1. "CREDIT_DATA1,Credit Data1. Current FC credit data selected by the CREDIT_SEL_VC CREDIT_SEL_CREDIT_TYPE CREDIT_SEL_TLP_TYPE and CREDIT_SEL_HD viewport-select fields. - Rx: Credit Allocated Value - Tx: Credit Limit Value. This value is valid when.." newline hexmask.long.word 0x0 8.--19. 1. "CREDIT_DATA0,Credit Data0. Current FC credit data selected by the CREDIT_SEL_VC CREDIT_SEL_CREDIT_TYPE CREDIT_SEL_TLP_TYPE and CREDIT_SEL_HD viewport-select fields. - Rx: Credit Received Value - Tx: Credit Consumed Value Note: This register field is.." newline rbitfld.long 0x0 7. "RSVDP_7,Reserved for future use." "0,1" newline bitfld.long 0x0 6. "CREDIT_SEL_HD,Credit Select(HeaderData). This field in conjunction with the CREDIT_SEL_VC CREDIT_SEL_CREDIT_TYPE and CREDIT_SEL_TLP_TYPE viewport-select fields determines that data that is returned by the CREDIT_DATA0 and CREDIT_DATA1 data fields. -.." "Header Credit,Data Credit" newline bitfld.long 0x0 4.--5. "CREDIT_SEL_TLP_TYPE,Credit Select(TLP Type). This field in conjunction with the CREDIT_SEL_VC CREDIT_SEL_CREDIT_TYPE and CREDIT_SEL_HD viewport-select fields determines that data that is returned by the CREDIT_DATA0 and CREDIT_DATA1 data fields. - 0x0:.." "Posted,Non-Posted,Completion,?" newline bitfld.long 0x0 3. "CREDIT_SEL_CREDIT_TYPE,Credit Select(Credit Type). This field in conjunction with the CREDIT_SEL_VC CREDIT_SEL_TLP_TYPE and CREDIT_SEL_HD viewport-select fields determines that data that is returned by the CREDIT_DATA0 and CREDIT_DATA1 data fields. -.." "Rx,Tx" newline bitfld.long 0x0 0.--2. "CREDIT_SEL_VC,Credit Select(VC). This field in conjunction with the CREDIT_SEL_CREDIT_TYPE CREDIT_SEL_TLP_TYPE and CREDIT_SEL_HD viewport-select fields determines that data that is returned by the CREDIT_DATA0 and CREDIT_DATA1 data fields. - 0x0: VC0 -.." "VC0,VC1,VC2,?,?,?,?,VC7" line.long 0x4 "SD_STATUS_L3_REG,Silicon Debug Status(Layer3). For more details. see the RAS DES section in the Core Operations chapter of the Databook." hexmask.long.tbyte 0x4 8.--31. 1. "RSVDP_8,Reserved for future use." newline bitfld.long 0x4 7. "MFTLP_STATUS,Malformed TLP Status. Indicates malformed TLP has occurred." "0,1" newline hexmask.long.byte 0x4 0.--6. 1. "MFTLP_POINTER,First Malformed TLP Error Pointer. Indicates the element of the received first malformed TLP. This pointer is validated by MFTLP_STATUS. - 01h: AtomicOp address alignment - 02h: AtomicOp operand - 03h: AtomicOp byte enable - 04h: TLP length.." group.long (0xD0+0x30C)++0xB line.long 0x0 "SD_EQ_CONTROL1_REG,Silicon Debug EQ Control 1. This is a viewport control register. Setting the EQ_RATE_SEL and EQ_LANE_SEL fields in this register determine the per-lane Silicon Debug EQ Status data returned by the SD_EQ_STATUS[1/2/3] viewport.." hexmask.long.byte 0x0 24.--31. 1. "FOM_TARGET,FOM Target. Indicates figure of merit target criteria value of EQ Master(DSP in EQ Phase3/USP in EQ Phase2). This field is only valid when GEN3_EQ_FB_MODE is 0001b(Figure Of Merit). Note: This register field is sticky." newline bitfld.long 0x0 23. "FOM_TARGET_ENABLE,FOM Target Enable. Enables the FOM_TARGET fields. Note: This register field is sticky." "0,1" newline hexmask.long.byte 0x0 18.--22. 1. "RSVDP_18,Reserved for future use." newline bitfld.long 0x0 16.--17. "EVAL_INTERVAL_TIME,Eval Interval Time. Indicates interval time of RxEqEval assertion. - 00: 500ns - 01: 1us - 10: 2us - 11: 4us This field is used for EQ Master(DSP in EQ Phase3/USP in EQ Phase2). Note: This register field is sticky." "0,1,2,3" newline hexmask.long.byte 0x0 10.--15. 1. "RSVDP_10,Reserved for future use." newline bitfld.long 0x0 8.--9. "EXT_EQ_TIMEOUT,Extends EQ Phase2/3 Timeout. This field is used when the Ltssm is in Recovery.EQ2/3. When this field is set the value of EQ2/3 timeout is extended. EQ Master(DSP in EQ Phase3/USP in EQ Phase2). - 00: 24ms (default) - 01: 48ms (x2) - 10:.." "0,1,2,3" newline rbitfld.long 0x0 6.--7. "RSVDP_6,Reserved for future use." "0,1,2,3" newline bitfld.long 0x0 4.--5. "EQ_RATE_SEL,EQ Status Rate Select. Setting this field in conjunction with the EQ_LANE_SEL field determines the per-lane Silicon Debug EQ Status data returned by the SD_EQ_CONTROL[2/3] and SD_EQ_STATUS[1/2/3] viewport registers. - 0x0: 8.0GT/s Speed.." "0,1,2,3" newline hexmask.long.byte 0x0 0.--3. 1. "EQ_LANE_SEL,EQ Status Lane Select. Setting this field in conjunction with the EQ_RATE_SEL field determines the per-lane Silicon Debug EQ Status data returned by the SD_EQ_CONTROL[2/3] and SD_EQ_STATUS[1/2/3] viewport registers. - 0x0: Lane0 - 0x1: Lane1.." line.long 0x4 "SD_EQ_CONTROL2_REG,Silicon Debug EQ Control 2. This viewport register returns the value for the rate and lane selected by the EQ_RATE_SEL and EQ_LANE_SEL fields in the SD_EQ_CONTROL1_REG register. For more details. see the RAS DES section in the Core.." rbitfld.long 0x4 31. "RSVDP_31,Reserved for future use." "0,1" newline bitfld.long 0x4 30. "FORCE_LOCAL_TX_PRESET_ENABLE,Force Local Transmitter Preset Enable. Enables the FORCE_LOCAL_TX_PRESET field. If select rate in the EQ_RATE_SEL field is 32.0GT/s Speed this feature is not available. Note: This register field is sticky." "0,1" newline bitfld.long 0x4 29. "FORCE_LOCAL_RX_HINT_ENABLE,Force Local Receiver Preset Hint Enable. Enables the FORCE_LOCAL_RX_HINT field. If select rate in the EQ_RATE_SEL field is other than 8.0GT/s Speed this feature is not available. Note: This register field is sticky." "0,1" newline bitfld.long 0x4 28. "FORCE_LOCAL_TX_COEF_ENABLE,Force Local Transmitter Coefficient Enable. Enables the following fields: - FORCE_LOCAL_TX_PRE_CURSOR - FORCE_LOCAL_TX_CURSOR - FORCE_LOCAL_TX_POST_CURSOR Note: This register field is sticky." "0,1" newline hexmask.long.byte 0x4 24.--27. 1. "FORCE_LOCAL_TX_PRESET,Force Local Transmitter Preset. Indicates initial preset value of USP in EQ Slave(EQ Phase2) instead of receiving EQ TS2. If select rate in the EQ_RATE_SEL field is 32.0GT/s Speed this feature is not available. Note: This register.." newline rbitfld.long 0x4 21.--23. "RSVDP_21,Reserved for future use." "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 18.--20. "FORCE_LOCAL_RX_HINT,Force Local Receiver Preset Hint. Indicates the RxPresetHint value of EQ Slave(DSP in EQ Phase2/USP in EQ Phase3) instead of received or set value. If select rate in the EQ_RATE_SEL field is other than 8.0GT/s Speed this feature is.." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x4 12.--17. 1. "FORCE_LOCAL_TX_POST_CURSOR,Force Local Transmitter Post-Cursor. Indicates the coefficient value of EQ Slave(DSP in EQ Phase2/USP in EQ Phase3) instead of the value instructed from link partner. Note: This register field is sticky." newline hexmask.long.byte 0x4 6.--11. 1. "FORCE_LOCAL_TX_CURSOR,Force Local Transmitter Cursor. Indicates the coefficient value of EQ Slave(DSP in EQ Phase2/USP in EQ Phase3) instead of the value instructed from link partner. Note: This register field is sticky." newline hexmask.long.byte 0x4 0.--5. 1. "FORCE_LOCAL_TX_PRE_CURSOR,Force Local Transmitter Pre-cursor. Indicates the coefficient value of EQ Slave(DSP in EQ Phase2/USP in EQ Phase3) instead of the value instructed from link partner. Note: This register field is sticky." line.long 0x8 "SD_EQ_CONTROL3_REG,Silicon Debug EQ Control 3. This viewport register returns the value for the rate and lane selected by the EQ_RATE_SEL and EQ_LANE_SEL fields in the SD_EQ_CONTROL1_REG register. For more details. see the RAS DES section in the Core.." rbitfld.long 0x8 29.--31. "RSVDP_29,Reserved for future use." "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 28. "FORCE_REMOTE_TX_COEF_ENABLE,Force Remote Transmitter Coefficient Enable. Enables the following fields: - FORCE_REMOTE_TX_PRE_CURSOR - FORCE_REMOTE_TX_CURSOR - FORCE_REMOTE_TX_POST_CURSOR This function can only be used when GEN3_EQ_FB_MODE =.." "0,1" newline hexmask.long.word 0x8 18.--27. 1. "RSVDP_18,Reserved for future use." newline hexmask.long.byte 0x8 12.--17. 1. "FORCE_REMOTE_TX_POST_CURSOR,Force Remote Transmitter Post-Cursor. Indicates the coefficient value of EQ Master(DSP in EQ Phase3/USP in EQ Phase2) instead of the value instructed from local phy in dirchange mode. Note: This register field is sticky." newline hexmask.long.byte 0x8 6.--11. 1. "FORCE_REMOTE_TX_CURSOR,Force Remote Transmitter Cursor. Indicates the coefficient value of EQ Master(DSP in EQ Phase3/USP in EQ Phase2) instead of the value instructed from local phy in dirchange mode. Note: This register field is sticky." newline hexmask.long.byte 0x8 0.--5. 1. "FORCE_REMOTE_TX_PRE_CURSOR,Force Remote Transmitter Pre-Cursor. Indicates the coefficient value of EQ Master(DSP in EQ Phase3/USP in EQ Phase2) instead of the value instructed from local phy in dirchange mode. Note: This register field is sticky." rgroup.long (0xE0+0x30C)++0xB line.long 0x0 "SD_EQ_STATUS1_REG,Silicon Debug EQ Status 1. This viewport register returns the first of three words of Silicon Debug EQ Status data for the rate and lane selected by the EQ_RATE_SEL and EQ_LANE_SEL fields in the SD_EQ_CONTROL1_REG register. The.." hexmask.long.tbyte 0x0 8.--31. 1. "RSVDP_8,Reserved for future use." newline bitfld.long 0x0 7. "EQ_REJECT_EVENT,EQ Reject Event. Indicates that the controller receives two consecutive TS1 OS w/Reject=1b during EQ Master phase(DSP in EQ Phase3/USP in EQ Phase2). This bit is automatically cleared when the controller starts EQ Master phase again." "0,1" newline bitfld.long 0x0 6. "EQ_RULEC_VIOLATION,EQ Rule C Violation. Indicates that coefficients rule C violation is detected in the values provided by PHY using direction change method during EQ Master phase(DSP in EQ Phase3/USP in EQ Phase2). The coefficients rule C correspond to.." "0,1" newline bitfld.long 0x0 5. "EQ_RULEB_VIOLATION,EQ Rule B Violation. Indicates that coefficients rule B violation is detected in the values provided by PHY using direction change method during EQ Master phase(DSP in EQ Phase3/USP in EQ Phase2). The coefficients rules B correspond to.." "0,1" newline bitfld.long 0x0 4. "EQ_RULEA_VIOLATION,EQ Rule A Violation. Indicates that coefficients rule A violation is detected in the values provided by PHY using direction change method during EQ Master phase(DSP in EQ Phase3/USP in EQ Phase2). The coefficients rules A correspond to.." "0,1" newline bitfld.long 0x0 3. "RSVDP_3,Reserved for future use." "0,1" newline bitfld.long 0x0 1.--2. "EQ_CONVERGENCE_INFO,EQ Convergence Info. Indicates equalization convergence information. - 0x0: Equalization is not attempted - 0x1: Equalization finished successfully - 0x2: Equalization finished unsuccessfully - 0x3: Reserved This bit is automatically.." "Equalization is not attempted,Equalization finished successfully,Equalization finished unsuccessfully,Reserved" newline bitfld.long 0x0 0. "EQ_SEQUENCE,EQ Sequence. Indicates that the controller is starting the equalization sequence. Note: This register field is sticky." "0,1" line.long 0x4 "SD_EQ_STATUS2_REG,Silicon Debug EQ Status 2. This viewport register returns the second of three words of Silicon Debug EQ Status data for the rate and lane selected by the EQ_RATE_SEL and EQ_LANE_SEL fields in the SD_EQ_CONTROL1_REG register. Each field.." hexmask.long.byte 0x4 24.--31. 1. "EQ_LOCAL_FOM_VALUE,EQ Local Figure of Merit. Indicates Local maximum Figure of Merit value. Note: This register field is sticky." newline bitfld.long 0x4 21.--23. "RSVDP_21,Reserved for future use." "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 18.--20. "EQ_LOCAL_RX_HINT,EQ Local Receiver Preset Hint. Indicates Local Receiver Preset Hint value. If select rate in the EQ_RATE_SEL field is other than 8.0GT/s Speed this feature is not available. Note: This register field is sticky." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x4 12.--17. 1. "EQ_LOCAL_POST_CURSOR,EQ Local Post-Cursor. Indicates Local post cursor coefficient value. Note: This register field is sticky." newline hexmask.long.byte 0x4 6.--11. 1. "EQ_LOCAL_CURSOR,EQ Local Cursor. Indicates Local cursor coefficient value. Note: This register field is sticky." newline hexmask.long.byte 0x4 0.--5. 1. "EQ_LOCAL_PRE_CURSOR,EQ Local Pre-Cursor. Indicates Local pre cursor coefficient value. Note: This register field is sticky." line.long 0x8 "SD_EQ_STATUS3_REG,Silicon Debug EQ Status 3. This viewport register returns the third of three words of Silicon Debug EQ Status data for the rate and lane selected by the EQ_RATE_SEL and EQ_LANE_SEL fields in the SD_EQ_CONTROL1_REG register. Each field.." bitfld.long 0x8 30.--31. "RSVDP_30,Reserved for future use." "0,1,2,3" newline hexmask.long.byte 0x8 24.--29. 1. "EQ_REMOTE_FS,EQ Remote FS. Indicates Remote FS value. Note: This register field is sticky." newline hexmask.long.byte 0x8 18.--23. 1. "EQ_REMOTE_LF,EQ Remote LF. Indicates Remote LF value. Note: This register field is sticky." newline hexmask.long.byte 0x8 12.--17. 1. "EQ_REMOTE_POST_CURSOR,EQ Remote Post-Cursor. Indicates Remote post cursor coefficient value. Note: This register field is sticky." newline hexmask.long.byte 0x8 6.--11. 1. "EQ_REMOTE_CURSOR,EQ Remote Cursor. Indicates Remote cursor coefficient value. Note: This register field is sticky." newline hexmask.long.byte 0x8 0.--5. 1. "EQ_REMOTE_PRE_CURSOR,EQ Remote Pre-Cursor. Indicates Remote pre cursor coefficient value. Note: This register field is sticky." tree.end tree "PF0_SN_CAP (Device Serial Number Capability Structure)" group.long (0x0+0x170)++0xB line.long 0x0 "SN_BASE,Device Serial Number Extended Capability Header. For a description of this standard PCIe register. see the PCI Express Base Specification." hexmask.long.word 0x0 20.--31. 1. "SN_NEXT_OFFSET,Next Capability Offset. For a description of this standard PCIe register field see the PCI Express Base Specification. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then.." hexmask.long.byte 0x0 16.--19. 1. "SN_CAP_VERSION,Capability Version. For a description of this standard PCIe register field see the PCI Express Base Specification. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky).." hexmask.long.word 0x0 0.--15. 1. "SN_PCIE_EXTENDED_CAP_ID,Serial Number Extended Capability ID. For a description of this standard PCIe register field see the PCI Express Base Specification. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if.." line.long 0x4 "SER_NUM_REG_DW_1,Serial Number 1 Register. For a description of this standard PCIe register. see the PCI Express Base Specification." hexmask.long 0x4 0.--31. 1. "SN_SER_NUM_REG_1_DW,IEEE 64 bit Device Serial Number (DW 1). For a description of this standard PCIe register field see the PCI Express Base Specification. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if.." line.long 0x8 "SER_NUM_REG_DW_2,Serial Number 2 Register. For a description of this standard PCIe register. see the PCI Express Base Specification." hexmask.long 0x8 0.--31. 1. "SN_SER_NUM_REG_2_DW,IEEE 64 bit Device Serial Number (DW 2). For a description of this standard PCIe register field see the PCI Express Base Specification. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if.." tree.end tree "PF0_VSECRAS_CAP (PF RAS Datapath Protection Capability Structure (VSEC))" group.long (0x0+0x480)++0x3 line.long 0x0 "RASDP_EXT_CAP_HDR_OFF,PCIe Extended capability ID. Capability version and Next capability offset. For a description of this standard PCIe register. see the PCI Express Specification." hexmask.long.word 0x0 20.--31. 1. "NEXT_OFFSET,Next Capability Offset. For a description of this standard PCIe register see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else.." newline hexmask.long.byte 0x0 16.--19. 1. "CAP,Capability Version. For a description of this standard PCIe register see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note:.." newline hexmask.long.word 0x0 0.--15. 1. "ID,PCI Express Extended Capability ID. For a description of this standard PCIe register see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else.." rgroup.long (0x4+0x480)++0x3 line.long 0x0 "RASDP_VENDOR_SPECIFIC_HDR_OFF,Vendor Specific Header. For a description of this standard PCIe register. see the PCI Express Specification." hexmask.long.word 0x0 20.--31. 1. "VSEC_LENGTH,VSEC Length. For a description of this standard PCIe register see the PCI Express Specification. Note: This register field is sticky." newline hexmask.long.byte 0x0 16.--19. 1. "VSEC_REV,VSEC Rev. For a description of this standard PCIe register see the PCI Express Specification. Note: This register field is sticky." newline hexmask.long.word 0x0 0.--15. 1. "VSEC_ID,VSEC ID. For a description of this standard PCIe register see the PCI Express Specification. Note: This register field is sticky." group.long (0x8+0x480)++0x7 line.long 0x0 "RASDP_ERROR_PROT_CTRL_OFF,ECC error correction control. Allows you to disable ECC error correction for RAMs and datapath. When the AXI Bridge Module is implemented and the master / slave clocks are asynchronous to the PCIe native controller clock.." hexmask.long.byte 0x0 24.--31. 1. "RSVDP_24,Reserved for future use." newline bitfld.long 0x0 23. "ERROR_PROT_DISABLE_CXS_RX,Error correction disable for CXS Tx path (PCIe Rx path). Note: This register field is sticky." "0,1" newline bitfld.long 0x0 22. "ERROR_PROT_DISABLE_ADM_RX,Error correction disable for ADM Rx path. Note: This register field is sticky." "0,1" newline bitfld.long 0x0 21. "ERROR_PROT_DISABLE_LAYER3_RX,Error correction disable for layer 3 Rx path. Note: This register field is sticky." "0,1" newline bitfld.long 0x0 20. "ERROR_PROT_DISABLE_LAYER2_RX,Error correction disable for layer 2 Rx path. Note: This register field is sticky." "0,1" newline bitfld.long 0x0 19. "ERROR_PROT_DISABLE_DMA_READ,Error correction disable for DMA read engine. Note: This register field is sticky." "0,1" newline bitfld.long 0x0 18. "ERROR_PROT_DISABLE_AXI_BRIDGE_INBOUND_REQUEST,Error correction disable for AXI bridge inbound request path. Note: This register field is sticky." "0,1" newline bitfld.long 0x0 17. "ERROR_PROT_DISABLE_AXI_BRIDGE_INBOUND_COMPLETION,Error correction disable for AXI bridge inbound completion composer. Does not disable the error detection reporting for 1-bit and 2-bit ECC errors. Note: This register field is sticky." "?,bit and 2-bit ECC errors" newline bitfld.long 0x0 16. "ERROR_PROT_DISABLE_RX,Global error correction disable for all Rx layers. Note: This register field is sticky." "0,1" newline hexmask.long.byte 0x0 9.--15. 1. "RSVDP_9,Reserved for future use." newline bitfld.long 0x0 8. "ERROR_PROT_DISABLE_DTIM_TX,Error correction disable for DTIM Tx path. Note: This register field is sticky." "0,1" newline bitfld.long 0x0 7. "ERROR_PROT_DISABLE_CXS_TX,Error correction disable for CXS Rx path (PCIe Tx path). Note: This register field is sticky." "0,1" newline bitfld.long 0x0 6. "ERROR_PROT_DISABLE_ADM_TX,Error correction disable for Adm Tx path. Note: This register field is sticky." "0,1" newline bitfld.long 0x0 5. "ERROR_PROT_DISABLE_LAYER3_TX,Error correction disable for layer 3 Tx path. Note: This register field is sticky." "0,1" newline bitfld.long 0x0 4. "ERROR_PROT_DISABLE_LAYER2_TX,Error correction disable for layer 2 Tx path. Note: This register field is sticky." "0,1" newline bitfld.long 0x0 3. "ERROR_PROT_DISABLE_DMA_WRITE,Error correction disable for DMA write engine. Note: This register field is sticky." "0,1" newline bitfld.long 0x0 2. "ERROR_PROT_DISABLE_AXI_BRIDGE_OUTBOUND,Error correction disable for AXI bridge outbound request path. Note: This register field is sticky." "0,1" newline bitfld.long 0x0 1. "ERROR_PROT_DISABLE_AXI_BRIDGE_MASTER,Error correction disable for AXI bridge master completion buffer. Note: This register field is sticky." "0,1" newline bitfld.long 0x0 0. "ERROR_PROT_DISABLE_TX,Global error correction disable for all Tx layers. Does not disable the error detection reporting for 1-bit and 2-bit ECC errors. Note: This register field is sticky." "?,bit and 2-bit ECC errors" line.long 0x4 "RASDP_CORR_COUNTER_CTRL_OFF,Corrected error (1-bit ECC) counter selection and control. This is a viewport control register. Setting the CORR_COUNTER_SELECTION_REGION and CORR_COUNTER_SELECTION fields in this register determine the counter data returned.." hexmask.long.byte 0x4 24.--31. 1. "CORR_COUNTER_SELECTION,Counter selection. This field selects the counter ID (within the region defined by CORR_COUNTER_SELECTION_REGION) whose contents can be read from the RASDP_CORR_COUNT_REPORT_OFF register. You can cycle this field value from 0 to.." newline hexmask.long.byte 0x4 20.--23. 1. "CORR_COUNTER_SELECTION_REGION,Select correctable counter region: - 0x0: Region select for Adm Rx path - 0x1: Region select for layer 3 Rx path - 0x2: Region select for layer 2 Rx path - 0x3: Region select for DMA inbound path - 0x4: Region select for AXI.." newline hexmask.long.word 0x4 5.--19. 1. "RSVDP_5,Reserved for future use." newline bitfld.long 0x4 4. "CORR_EN_COUNTERS,Enable correctable errors counters. - 1: counters increment when the controller detects a correctable error - 0: counters are frozen The counters are enabled by default." "counters are frozen,counters increment when the controller detects a.." newline rbitfld.long 0x4 1.--3. "RSVDP_1,Reserved for future use." "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 0. "CORR_CLEAR_COUNTERS,Clear all correctable error counters." "0,1" rgroup.long (0x10+0x480)++0x3 line.long 0x0 "RASDP_CORR_COUNT_REPORT_OFF,Corrected error (1-bit ECC) counter data. This viewport register returns the counter data selected by the CORR_COUNTER_SELECTION_REGION and CORR_COUNTER_SELECTION fields in the RASDP_CORR_COUNTER_CTRL_OFF register." hexmask.long.byte 0x0 24.--31. 1. "CORR_COUNTER_SELECTED,Counter selection. Returns the value set in the CORR_COUNTER_SELECTION field of the RASDP_CORR_COUNTER_CTRL_OFF register." newline hexmask.long.byte 0x0 20.--23. 1. "CORR_COUNTER_SELECTED_REGION,Selected correctable counter region: - 0x0: Region select for Adm Rx path - 0x1: Region select for layer 3 Rx path - 0x2: Region select for layer 2 Rx path - 0x3: Region select for DMA inbound path - 0x4: Region select for.." newline hexmask.long.word 0x0 8.--19. 1. "RSVDP_8,Reserved for future use." newline hexmask.long.byte 0x0 0.--7. 1. "CORR_COUNTER,Current corrected error count for the selected counter." group.long (0x14+0x480)++0x3 line.long 0x0 "RASDP_UNCORR_COUNTER_CTRL_OFF,Uncorrected error (2-bit ECC and parity) counter selection and control. This is a viewport control register. Setting the UNCORR_COUNTER_SELECTION_REGION and UNCORR_COUNTER_SELECTION fields in this register determine the.." hexmask.long.byte 0x0 24.--31. 1. "UNCORR_COUNTER_SELECTION,Counter selection. This field selects the counter ID (within the region defined by UNCORR_COUNTER_SELECTION_REGION) whose contents can be read from the RASDP_UNCORR_COUNT_REPORT_OFF register. You can cycle this field value from 0.." newline hexmask.long.byte 0x0 20.--23. 1. "UNCORR_COUNTER_SELECTION_REGION,Select uncorrectable counter region: - 0x0: Region select for Adm Rx path - 0x1: Region select for layer 3 Rx path - 0x2: Region select for layer 2 Rx path - 0x3: Region select for DMA inbound path - 0x4: Region select for.." newline hexmask.long.word 0x0 5.--19. 1. "RSVDP_5,Reserved for future use." newline bitfld.long 0x0 4. "UNCORR_EN_COUNTERS,Enable uncorrectable errors counters. - 1: enables the counters to increment on detected correctable errors - 0: counters are frozen The counters are enabled by default." "counters are frozen,enables the counters to increment on detected.." newline rbitfld.long 0x0 1.--3. "RSVDP_1,Reserved for future use." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 0. "UNCORR_CLEAR_COUNTERS,Clear uncorrectable errors counters. When asserted causes all counters tracking the uncorrectable errors to be cleared." "0,1" rgroup.long (0x18+0x480)++0x3 line.long 0x0 "RASDP_UNCORR_COUNT_REPORT_OFF,Uncorrected error (2-bit ECC and parity) counter data. This viewport register returns the counter data selected by the UNCORR_COUNTER_SELECTION_REGION and UNCORR_COUNTER_SELECTION fields in the RASDP_UNCORR_COUNTER_CTRL_OFF.." hexmask.long.byte 0x0 24.--31. 1. "UNCORR_COUNTER_SELECTED,Counter selection. Returns the value set in the UNCORR_COUNTER_SELECTION field of the RASDP_UNCORR_COUNTER_CTRL_OFF register." newline hexmask.long.byte 0x0 20.--23. 1. "UNCORR_COUNTER_SELECTED_REGION,Selected uncorrectable counter region: - 0x0: Region select for Adm Rx path - 0x1: Region select for layer 3 Rx path - 0x2: Region select for layer 2 Rx path - 0x3: Region select for DMA inbound path - 0x4: Region select.." newline hexmask.long.word 0x0 8.--19. 1. "RSVDP_8,Reserved for future use." newline hexmask.long.byte 0x0 0.--7. 1. "UNCORR_COUNTER,Current uncorrected error count for the selected counter" group.long (0x1C+0x480)++0x3 line.long 0x0 "RASDP_ERROR_INJ_CTRL_OFF,Error injection control for the following features: - 1-bit or 2-bit injection - Continuous or fixed-number (n) injection modes - Global enable/disable - Selectable location where injection occurs" hexmask.long.byte 0x0 24.--31. 1. "RSVDP_24,Reserved for future use." newline hexmask.long.byte 0x0 16.--23. 1. "ERROR_INJ_LOC,Error injection location. Selects where error injection takes place. You can cycle this field value from 0 to 255 to access all locations according to the detailed report of check points at.." newline hexmask.long.byte 0x0 8.--15. 1. "ERROR_INJ_COUNT,Error injection count. - 0: errors are inserted in every TLP until you clear ERROR_INJ_EN. - 1: one errors injected - 2: two errors injected - n: amount of errors injected" newline rbitfld.long 0x0 6.--7. "RSVDP_6,Reserved for future use." "0,1,2,3" newline bitfld.long 0x0 4.--5. "ERROR_INJ_TYPE,Error injection type: - 0: none - 1: 1-bit - 2: 2-bit" "none,bit,bit,?" newline rbitfld.long 0x0 1.--3. "RSVDP_1,Reserved for future use." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 0. "ERROR_INJ_EN,Error injection global enable. When set enables the error insertion logic." "0,1" rgroup.long (0x20+0x480)++0x7 line.long 0x0 "RASDP_CORR_ERROR_LOCATION_OFF,Corrected errors locations. For more details. see the RAS Data Protection (DP) section in the Core Operations chapter of the Databook." hexmask.long.byte 0x0 24.--31. 1. "LOC_LAST_CORR_ERROR,Location/ID of the last corrected error within the region defined by REG_LAST_CORR_ERROR. You can cycle this field value from 0 to 255 to access all counters according to the detailed report of check points at.." newline hexmask.long.byte 0x0 20.--23. 1. "REG_LAST_CORR_ERROR,Region of the last corrected error: - 0x0: Region select for Adm Rx path - 0x1: Region select for layer 3 Rx path - 0x2: Region select for layer 2 Rx path - 0x3: Region select for DMA inbound path - 0x4: Region select for AXI bridge.." newline hexmask.long.byte 0x0 16.--19. 1. "RSVDP_16,Reserved for future use." newline hexmask.long.byte 0x0 8.--15. 1. "LOC_FIRST_CORR_ERROR,Location/ID of the first corrected error within the region defined by REG_FIRST_CORR_ERROR. You can cycle this field value from 0 to 255 to access all counters according to the detailed report of check points at.." newline hexmask.long.byte 0x0 4.--7. 1. "REG_FIRST_CORR_ERROR,Region of the first corrected error: - 0x0: Region select for Adm Rx path - 0x1: Region select for layer 3 Rx path - 0x2: Region select for layer 2 Rx path - 0x3: Region select for DMA inbound path - 0x4: Region select for AXI bridge.." newline hexmask.long.byte 0x0 0.--3. 1. "RSVDP_0,Reserved for future use." line.long 0x4 "RASDP_UNCORR_ERROR_LOCATION_OFF,Uncorrected errors locations. For more details. see the RAS Data Protection (DP) section in the Core Operations chapter of the Databook." hexmask.long.byte 0x4 24.--31. 1. "LOC_LAST_UNCORR_ERROR,Location/ID of the last uncorrected error within the region defined by REG_LAST_UNCORR_ERROR. You can cycle this field value from 0 to 255 to access all counters according to the detailed report of check points at.." newline hexmask.long.byte 0x4 20.--23. 1. "REG_LAST_UNCORR_ERROR,Region of the last uncorrected error: - 0x0: Region select for Adm Rx path - 0x1: Region select for layer 3 Rx path - 0x2: Region select for layer 2 Rx path - 0x3: Region select for DMA inbound path - 0x4: Region select for AXI.." newline hexmask.long.byte 0x4 16.--19. 1. "RSVDP_16,Reserved for future use." newline hexmask.long.byte 0x4 8.--15. 1. "LOC_FIRST_UNCORR_ERROR,Location/ID of the first uncorrected error within the region defined by REG_FIRST_UNCORR_ERROR. You can cycle this field value from 0 to 255 to access all counters according to the detailed report of check points at.." newline hexmask.long.byte 0x4 4.--7. 1. "REG_FIRST_UNCORR_ERROR,Region of the first uncorrected error: - 0x0: Region select for Adm Rx path - 0x1: Region select for layer 3 Rx path - 0x2: Region select for layer 2 Rx path - 0x3: Region select for DMA inbound path - 0x4: Region select for AXI.." newline hexmask.long.byte 0x4 0.--3. 1. "RSVDP_0,Reserved for future use." group.long (0x28+0x480)++0x7 line.long 0x0 "RASDP_ERROR_MODE_EN_OFF,RASDP error mode enable. The controller enters RASDP error mode (if ERROR_MODE_EN =1) upon detection of the first uncorrectable error. During this mode: - Rx TLPs that are forwarded to your application are not guaranteed to be.." hexmask.long 0x0 2.--31. 1. "RSVDP_2,Reserved for future use." newline bitfld.long 0x0 1. "AUTO_LINK_DOWN_EN,Write '1' to enable the controller to bring the link down when the controller enters RASDP error mode. Note: This register field is sticky." "0,1" newline bitfld.long 0x0 0. "ERROR_MODE_EN,Write '1' to enable the controller enter RASDP error mode when it detects an uncorrectable error. Note: This register field is sticky." "0,1" line.long 0x4 "RASDP_ERROR_MODE_CLEAR_OFF,Exit RASDP error mode. For more details. see the RAS Data Protection (DP) section in the Core Operations chapter of the Databook." hexmask.long 0x4 1.--31. 1. "RSVDP_1,Reserved for future use." newline bitfld.long 0x4 0. "ERROR_MODE_CLEAR,Write '1' to take the controller out of RASDP error mode. The controller will then report uncorrectable errors (through AER internal error reporting) and also stop nullifying/discarding TLPs." "0,1" rgroup.long (0x30+0x480)++0x7 line.long 0x0 "RASDP_RAM_ADDR_CORR_ERROR_OFF,RAM Address where a corrected error (1-bit ECC) has been detected. For more details. see the RAS Data Protection (DP) section in the Core Operations chapter of the Databook." hexmask.long.byte 0x0 28.--31. 1. "RAM_INDEX_CORR_ERROR,RAM index where a corrected error (1-bit ECC) has been detected." newline bitfld.long 0x0 27. "RSVDP_27,Reserved for future use." "0,1" newline hexmask.long 0x0 0.--26. 1. "RAM_ADDR_CORR_ERROR,RAM Address where a corrected error (1-bit ECC) has been detected." line.long 0x4 "RASDP_RAM_ADDR_UNCORR_ERROR_OFF,RAM Address where an uncorrected error (2-bit ECC) has been detected. For more details. see the RAS Data Protection (DP) section in the Core Operations chapter of the Databook." hexmask.long.byte 0x4 28.--31. 1. "RAM_INDEX_UNCORR_ERROR,RAM index where an uncorrected error (2-bit ECC) has been detected." newline bitfld.long 0x4 27. "RSVDP_27,Reserved for future use." "0,1" newline hexmask.long 0x4 0.--26. 1. "RAM_ADDR_UNCORR_ERROR,RAM Address where an uncorrected error (2-bit ECC) has been detected." tree.end tree "PF0_RTR_CAP (PF RTR Capability Structure)" group.long (0x0+0x2F8)++0xB line.long 0x0 "RTR_EXT_CAP_HDR_OFF,Readiness Time Reporting PCI Express Extended Capability Header. For a description of this standard PCIe register. see the PCI Express Specification." hexmask.long.word 0x0 20.--31. 1. "RTR_NEXT_OFFSET,Next Capability Offset. For a description of this standard PCIe register field see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky).." hexmask.long.byte 0x0 16.--19. 1. "RTR_CAP_VERSION,Capability Version. For a description of this standard PCIe register field see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky).." hexmask.long.word 0x0 0.--15. 1. "RTR_EXT_CAP_ID,PCI Express Extended Capability ID. For a description of this standard PCIe register field see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then.." line.long 0x4 "READI_TIME_REPORTING1_OFF,Readiness Time Reporting 1. For a description of this standard PCIe register. see the PCI Express Specification." bitfld.long 0x4 31. "RTR_TIME_VALID,Valid. For a description of this standard PCIe register field see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky)" "0,1" hexmask.long.byte 0x4 24.--30. 1. "RSVDP_24,Reserved for future use." hexmask.long.word 0x4 12.--23. 1. "DL_UP_TIME,DL_UP Time. For a description of this standard PCIe register field see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky)" hexmask.long.word 0x4 0.--11. 1. "RESET_TIME,Reset Time. For a description of this standard PCIe register field see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky)" line.long 0x8 "READI_TIME_REPORTING2_OFF,Readiness Time Reporting 2. For a description of this standard PCIe register. see the PCI Express Specification." hexmask.long.byte 0x8 24.--31. 1. "RSVDP_24,Reserved for future use." hexmask.long.word 0x8 12.--23. 1. "D3HOT_D0_TIME,D3hot to D0 Time. For a description of this standard PCIe register field see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else.." hexmask.long.word 0x8 0.--11. 1. "FLR_TIME,FLR Time. For a description of this standard PCIe register field see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky)" tree.end tree "PF0_RTR_CAP_DBI2 (DBI2 Shadow Block: PF RTR Capability Structure)" rgroup.long (0x4+0x12F8)++0x7 line.long 0x0 "SHADOW_READI_TIME_REPORTING1_OFF,Shadow Register Readiness Time Reporting 1. For a description of this standard PCIe register. see the PCI Express Specification." bitfld.long 0x0 31. "RTR_TIME_VALID,Shadow Valid in the shadow register. For a description of this standard PCIe register field see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access - Dbi: No access - Dbi2: if.." "0,1" hexmask.long.tbyte 0x0 12.--30. 1. "RSVDP_12,Reserved for future use." hexmask.long.word 0x0 0.--11. 1. "RESET_TIME,Shadow Reset Time in the shadow register. For a description of this standard PCIe register field see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access - Dbi: No access - Dbi2: if.." line.long 0x4 "SHADOW_READI_TIME_REPORTING2_OFF,Shadow Register Readiness Time Reporting 2. For a description of this standard PCIe register. see the PCI Express Specification." hexmask.long.byte 0x4 24.--31. 1. "RSVDP_24,Reserved for future use." hexmask.long.word 0x4 12.--23. 1. "D3HOT_D0_TIME,Shadow D3hot to D0 Time in the shadow register. For a description of this standard PCIe register field see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access - Dbi: No access - Dbi2:.." hexmask.long.word 0x4 0.--11. 1. "FLR_TIME,Shadow FLR Time in the shadow register. For a description of this standard PCIe register field see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access - Dbi: No access - Dbi2: if.." tree.end tree "PF0_FRSQ_CAP (PF FRSQ Capability Structure)" group.long (0x0+0x2E8)++0xB line.long 0x0 "FRSQ_EXT_CAP_HDR_OFF,FRS Queuing Extended Capability Header. For a description of this standard PCIe register. see the PCI Express Specification." hexmask.long.word 0x0 20.--31. 1. "FRSQ_NEXT_OFFSET,Next Capability Offset. For a description of this standard PCIe register field see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then.." hexmask.long.byte 0x0 16.--19. 1. "FRSQ_CAP_VERSION,Capability Version. For a description of this standard PCIe register field see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky).." hexmask.long.word 0x0 0.--15. 1. "FRSQ_EXT_CAP_ID,PCI Express Extended Capability ID. For a description of this standard PCIe register field see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then.." line.long 0x4 "FRSQ_CAP_OFF,FRS Queuing Capability Register. For a description of this standard PCIe register. see the PCI Express Specification." hexmask.long.word 0x4 21.--31. 1. "RSVDP_21,Reserved for future use." hexmask.long.byte 0x4 16.--20. 1. "FRS_INT_MESSAGE_NUMBER,FRS Interrupt Message Number. For a description of this standard PCIe register field see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1).." hexmask.long.byte 0x4 12.--15. 1. "RSVDP_12,Reserved for future use." hexmask.long.word 0x4 0.--11. 1. "FRSQ_MAX_DEPTH,FRS Queue Max Depth. For a description of this standard PCIe register field see the PCI Express Specification." line.long 0x8 "FRSQ_CONTROL_FRSQ_STATUS_OFF,FRS Queuing Status and Control Register. For a description of this standard PCIe register. see the PCI Express Specification." hexmask.long.word 0x8 17.--31. 1. "RSVDP_17,Reserved for future use." bitfld.long 0x8 16. "FRS_INTERRUPT_ENABLE,FRS Interrupt Enable. For a description of this standard PCIe register field see the PCI Express Specification." "0,1" hexmask.long.word 0x8 2.--15. 1. "RSVDP_2,Reserved for future use." bitfld.long 0x8 1. "FRS_MESSAGE_OVERFLOW,FRS Message Overflow. For a description of this standard PCIe register field see the PCI Express Specification." "0,1" newline bitfld.long 0x8 0. "FRS_MESSAGE_RECEIVED,FRS Message Received. For a description of this standard PCIe register field see the PCI Express Specification." "0,1" rgroup.long (0xC+0x2E8)++0x3 line.long 0x0 "FRS_MESSAGE_QUEUE_OFF,FRS Message Queue Register. For a description of this standard PCIe register. see the PCI Express Specification." hexmask.long.word 0x0 20.--31. 1. "FRS_MESSAGE_QUE_DEPTH,FRS Message Queue Depth. For a description of this standard PCIe register field see the PCI Express Specification." hexmask.long.byte 0x0 16.--19. 1. "FRS_MESSAGE_QUE_REASON,FRS Message Queue Reason. For a description of this standard PCIe register field see the PCI Express Specification." hexmask.long.word 0x0 0.--15. 1. "FRS_MESSAGE_QUE_FUNC_ID,FRS Message Queue Function ID. For a description of this standard PCIe register field see the PCI Express Specification." tree.end tree "PF0_PTM_CAP (PF PTM Capability Structure)" group.long (0x0+0x40C)++0xB line.long 0x0 "PTM_EXT_CAP_HDR_OFF,Precision Time Measurement Capability Header. For a description of this standard PCIe register. see the PCI Express Specification." hexmask.long.word 0x0 20.--31. 1. "PTM_NEXT_OFFSET,Precision Time Measurement PCI Express Extended Capability Next Offset. For a description of this standard PCIe register see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access. -.." hexmask.long.byte 0x0 16.--19. 1. "PTM_CAP_VERSION,Precision Time Measurement PCI Express Extended Capability Version. For a description of this standard PCIe register see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi:.." hexmask.long.word 0x0 0.--15. 1. "PTM_CAP_ID,Precision Time Measurement PCI Express Extended Capability ID. For a description of this standard PCIe register see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if.." line.long 0x4 "PTM_CAP_OFF,PTM Capability Register. For a description of this standard PCIe register. see the PCI Express Specification." hexmask.long.word 0x4 16.--31. 1. "RSVDP_16,Reserved for future use." hexmask.long.byte 0x4 8.--15. 1. "PTM_CLK_GRAN,PTM Local Clock Granularity. For a description of this standard PCIe register see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky).." hexmask.long.byte 0x4 3.--7. 1. "RSVDP_3,Reserved for future use." bitfld.long 0x4 2. "PTM_ROOT_CAPABLE,PTM Root Capable. For a description of this standard PCIe register see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else.." "0,1" bitfld.long 0x4 1. "PTM_RES_CAPABLE,PTM Responder Capable. For a description of this standard PCIe register see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else.." "0,1" newline bitfld.long 0x4 0. "PTM_REQ_CAPABLE,PTM Requester Capable. For a description of this standard PCIe register see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else.." "0,1" line.long 0x8 "PTM_CONTROL_OFF,PTM Control Register. For a description of this standard PCIe register. see the PCI Express Specification." hexmask.long.word 0x8 16.--31. 1. "RSVDP_16,Reserved for future use." hexmask.long.byte 0x8 8.--15. 1. "EFF_GRAN,PTM Effective Granularity. For a description of this standard PCIe register see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: HWINIT" hexmask.long.byte 0x8 2.--7. 1. "RSVDP_2,Reserved for future use." rbitfld.long 0x8 1. "ROOT_SELECT,PTM Root Select. When set this Time Source is the PTM Root. For a description of this standard PCIe register see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: HWINIT" "0,1" bitfld.long 0x8 0. "PTM_ENABLE,PTM Enable. When set this function is permitted to participate in the PTM mechanism. For a description of this standard PCIe register see the PCI Express Specification." "0,1" tree.end tree "PF0_PTM_RES_CAP (PF PTM Responder Capability Structure (VSEC))" group.long (0x0+0x418)++0xB line.long 0x0 "PTM_RES_CAP_HDR_OFF,Precision Time Measurement Responder Capability Header (VSEC). For more details. see the PTM section in the Databook." hexmask.long.word 0x0 20.--31. 1. "PTM_RES_EXT_CAP_NEXT_OFFS,Precision Time Measurement Responder VSEC Next Pointer. For more details see the PTM section in the Databook. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then.." hexmask.long.byte 0x0 16.--19. 1. "PTM_RES_EXT_CAP_VER,Precision Time Measurement Responder VSEC Version. For more details see the PTM section in the Databook. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else.." hexmask.long.word 0x0 0.--15. 1. "PTM_RES_EXT_CAP_ID,Precision Time Measurement Responder VSEC ID. For more details see the PTM section in the Databook. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else.." line.long 0x4 "PTM_RES_HDR_OFF,Precision Time Measurement Responder Vendor Specific Header. For more details. see the PTM section in the Databook." hexmask.long.word 0x4 20.--31. 1. "PTM_RES_VSEC_LENGTH,PTM Responder VSEC Length. For more details see the PTM section in the Databook. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This.." hexmask.long.byte 0x4 16.--19. 1. "PTM_RES_VSEC_REV,PTM Responder VSEC Revision. For more details see the PTM section in the Databook. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This.." hexmask.long.word 0x4 0.--15. 1. "PTM_RES_VSEC_ID,PTM Responder VSEC ID. For more details see the PTM section in the Databook. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register.." line.long 0x8 "PTM_RES_CONTROL_OFF,PTM Responder Control Register. For more details. see the PTM section in the Databook." hexmask.long 0x8 2.--31. 1. "RSVDP_2,Reserved for future use." bitfld.long 0x8 1. "PTM_RES_PDEL_BYTE_REV,PTM Requester Propagation Delay Byte Reversal - Reverse the order of bytes in the PTM Propagation Delay data word of the PTM ResponseD Message for compatibility with previous revisions. For more details see the PTM section in the.." "0,1" bitfld.long 0x8 0. "PTM_RES_CCONTEXT_VALID,PTM Responder Control Context Valid - PTM Local Timing is valid. This bit is set over the DBI. A speed change or aux_clk_active will set this bit low. For more details see the PTM section in the Databook. Note: The access.." "0,1" rgroup.long (0xC+0x418)++0x3 line.long 0x0 "PTM_RES_STATUS_OFF,PTM Responder Status Register. For more details. see the PTM section in the Databook." hexmask.long 0x0 2.--31. 1. "RSVDP_2,Reserved for future use." bitfld.long 0x0 1. "PTM_RES_REQUEST_RECEIVED,PTM 1st Request Received - PTM Responder has received the first PTM Request Message. Upon receipt of a second PTM Request Message a ResponseD message with timing information will be sent from the Responder if the context is.." "0,1" bitfld.long 0x0 0. "PTM_RES_CONTEXT_VALID,PTM Responder Status Context Valid - PTM Local Timing Context is Valid. Value set from upstream port Requester in a Switch. Shadows the same in the control register in all other products. For more details see the PTM section in the.." "0,1" group.long (0x10+0x418)++0x7 line.long 0x0 "PTM_RES_LOCAL_LSB_OFF,PTM Responder Local Clock LSB. For more details. see the PTM section in the Databook." hexmask.long 0x0 0.--31. 1. "PTM_RES_LOCAL_LSB,PTM Responder Local Clock LSB - Lower 32 bits of local timer value. For more details see the PTM section in the Databook. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then.." line.long 0x4 "PTM_RES_LOCAL_MSB_OFF,PTM Responder Local Clock MSB. For more details. see the PTM section in the Databook." hexmask.long 0x4 0.--31. 1. "PTM_RES_LOCAL_MSB,PTM Responder Local Clock MSB - Upper 32 bits of local timer value. For more details see the PTM section in the Databook. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then.." rgroup.long (0x18+0x418)++0x1F line.long 0x0 "PTM_RES_T2_LSB_OFF,PTM Responder T2 Timestamp LSB. For more details. see the PTM section in the Databook." hexmask.long 0x0 0.--31. 1. "PTM_RES_T2_LSB,PTM Responder T2 Timestamp LSB - Lower 32 bits of the T2 Timestamp value. For more details see the PTM section in the Databook. Note: This register field is sticky." line.long 0x4 "PTM_RES_T2_MSB_OFF,PTM Responder T2 Timestamp MSB. For more details. see the PTM section in the Databook." hexmask.long 0x4 0.--31. 1. "PTM_RES_T2_MSB,PTM Responder T2 Timestamp MSB - Upper 32 bits of the T2 Timestamp value. For more details see the PTM section in the Databook. Note: This register field is sticky." line.long 0x8 "PTM_RES_T2P_LSB_OFF,PTM Responder T2 Previous Timestamp LSB. For more details. see the PTM section in the Databook." hexmask.long 0x8 0.--31. 1. "PTM_RES_T2P_LSB,PTM Responder T2 Previous Timestamp LSB - Lower 32 bits of the previously stored T2 Timestamp value. For more details see the PTM section in the Databook. Note: This register field is sticky." line.long 0xC "PTM_RES_T2P_MSB_OFF,PTM Responder T2 Previous Timestamp MSB. For more details. see the PTM section in the Databook." hexmask.long 0xC 0.--31. 1. "PTM_RES_T2P_MSB,PTM Responder T2 Previous Timestamp MSB - Upper 32 bits of the previously stored T2 Timestamp value. For more details see the PTM section in the Databook. Note: This register field is sticky." line.long 0x10 "PTM_RES_T3_LSB_OFF,PTM Responder T3 Timestamp LSB. For more details. see the PTM section in the Databook." hexmask.long 0x10 0.--31. 1. "PTM_RES_T3_LSB,PTM Responder T3 Timestamp LSB - Lower 32 bits of the T3 Timestamp value. For more details see the PTM section in the Databook. Note: This register field is sticky." line.long 0x14 "PTM_RES_T3_MSB_OFF,PTM Responder T3 Timestamp MSB. For more details. see the PTM section in the Databook." hexmask.long 0x14 0.--31. 1. "PTM_RES_T3_MSB,PTM Responder T3 Timestamp MSB - Upper 32 bits of the T2 Timestamp value. For more details see the PTM section in the Databook. Note: This register field is sticky." line.long 0x18 "PTM_RES_T3P_LSB_OFF,PTM Responder T3 Previous Timestamp LSB. For more details. see the PTM section in the Databook." hexmask.long 0x18 0.--31. 1. "PTM_RES_T3P_LSB,PTM Responder T3 Previous Timestamp LSB - Lower 32 bits of the previously stored T3 Timestamp value. For more details see the PTM section in the Databook. Note: This register field is sticky." line.long 0x1C "PTM_RES_T3P_MSB_OFF,PTM Responder T3 Previous Timestamp MSB. For more details. see the PTM section in the Databook." hexmask.long 0x1C 0.--31. 1. "PTM_RES_T3P_MSB,PTM Responder T3 Previous Timestamp MSB - Upper 32 bits of the previously stored T3 Timestamp value. For more details see the PTM section in the Databook. Note: This register field is sticky." group.long (0x38+0x418)++0x7 line.long 0x0 "PTM_RES_TX_LATENCY_OFF,PTM Responder TX Latency. For more details. see the PTM section in the Databook." hexmask.long.tbyte 0x0 12.--31. 1. "RSVDP_12,Reserved for future use." hexmask.long.word 0x0 0.--11. 1. "PTM_RES_TX_LATENCY,PTM Responder TX Latency - Responder Transmit path latency (12 bit wide). For more details see the PTM section in the Databook. Note: This register field is sticky." line.long 0x4 "PTM_RES_RX_LATENCY_OFF,PTM Responder RX Latency. For more details. see the PTM section in the Databook." hexmask.long.tbyte 0x4 12.--31. 1. "RSVDP_12,Reserved for future use." hexmask.long.word 0x4 0.--11. 1. "PTM_RES_RX_LATENCY,PTM Responder RX Latency - Responder Receive path latency (12 bit wide). For more details see the PTM section in the Databook. Note: This register field is sticky." rgroup.long (0x40+0x418)++0x3 line.long 0x0 "PTM_RES_NOM_CLOCK_T_OFF,PTM Responder Nominal Clock Period. For more details. see the PTM section in the Databook." hexmask.long.byte 0x0 24.--31. 1. "RSVDP_24,Reserved for future use." hexmask.long.byte 0x0 16.--23. 1. "PTM_RES_NOM_CLOCK_T_INT,PTM Responder Nominal Clock Period Integral - Integral part of the nominal PTM local clock period in nanoseconds. For more details see the PTM section in the Databook. Note: This register field is sticky." hexmask.long.word 0x0 0.--15. 1. "PTM_RES_NOM_CLOCK_T_FRAC,PTM Responder Nominal Clock Period Fractional - Fractional part of the nominal PTM local clock period. LSB is 1/(2^16) nanoseconds. For more details see the PTM section in the Databook. Note: This register field is sticky." group.long (0x44+0x418)++0x3 line.long 0x0 "PTM_RES_SCALED_CLOCK_T_OFF,PTM Responder Scaled Clock Period. For more details. see the PTM section in the Databook." bitfld.long 0x0 31. "PTM_RES_SCALED_CLOCK_T_EN,PTM Responder Scaled Clock Period Enable - Use the programmed scaled PTM clock period rather than the nominal values. This bit is cleared when the core_clk rate starts to change and can only be set when the clock period change.." "0,1" hexmask.long.byte 0x0 24.--30. 1. "RSVDP_24,Reserved for future use." hexmask.long.byte 0x0 16.--23. 1. "PTM_RES_SCALED_CLOCK_T_INT,PTM Responder Scaled Clock Period Integral - Integral part of the nominal PTM local clock period in nanoseconds. For more details see the PTM section in the Databook. Note: This register field is sticky." newline hexmask.long.word 0x0 0.--15. 1. "PTM_RES_SCALED_CLOCK_T_FRAC,PTM Responder Scaled Clock Period Fractional - Fractional part of the nominal PTM local clock period. LSB is 1/(2^16) nanoseconds. For more details see the PTM section in the Databook. Note: This register field is sticky." tree.end tree "PF0_PM_CAP (PF PCI Power Management Capability Structure)" group.long (0x0+0x40)++0x7 line.long 0x0 "CAP_ID_NXT_PTR_REG,Power Management Capabilities Register." hexmask.long.byte 0x0 27.--31. 1. "PME_SUPPORT,PME_Support. This 5-bit field indicates the power states in which the function may generate a PME and/or forward PME messages. A value of 0b for any bit indicates that the function is not capable of asserting PME while in that power state. -.." bitfld.long 0x0 26. "D2_SUPPORT,D2_Support. If this bit is set this function supports the D2 Power Management state. Functions that do not support D2 must always return a value of 0b for this bit. Note: The access attributes of this field are as follows: - Wire: No access." "0,1" bitfld.long 0x0 25. "D1_SUPPORT,D1_Support. If this bit is set this function supports the D1 Power Management state. Functions that do not support D1 must always return a value of 0b for this bit. Note: The access attributes of this field are as follows: - Wire: No access." "0,1" bitfld.long 0x0 22.--24. "AUX_CURR,Aux_Current. This 3 bit field reports the Vaux auxiliary current requirements for the function. If this function implements the Data Register the controller hardwires this field to 000b. If PME_Support is 0 xxxxb (PME assertion from D3cold is.." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 21. "DSI,Device Specific Initialization. The DSI bit indicates whether special initialization of this function is required. When set indicates that the function requires a device specific initialization sequence following a transition to the D0uninitialized.." "0,1" bitfld.long 0x0 20. "PME_IMM_READI_RETURN_DO,Immediate_Readiness_on_Return_to_D0. - If this bit is a '1' this function is guaranteed to be ready to successfully complete valid accesses immediately after being set to D0. These accesses include configuration cycles and if.." "0,1" rbitfld.long 0x0 19. "PME_CLK,PME Clock. Does not apply to PCI Express the controller hardwires it to 0b. Note: This register field is sticky." "0,1" bitfld.long 0x0 16.--18. "PM_SPEC_VER,Version. This field provides the Power Management specification version. The controller hardwires this field to 011b for functions compliant to PCI Express Base Specification Revision 4.0 Version 1.0>. Note: The access attributes of this.." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x0 8.--15. 1. "PM_NEXT_POINTER,Next Capability Pointer. This field provides an offset into the function's configuration space pointing to the location of next item in the capabilities list. If there are no additional items in the capabilities list this field is set to.." hexmask.long.byte 0x0 0.--7. 1. "PM_CAP_ID,Capability ID. This field returns 01h to indicate that this is the PCI Power Management Capability. Each function may have only one item in its capability list with Capability ID set to 01h." line.long 0x4 "CON_STATUS_REG,Power Management Control and Status Register. This register is used to manage the PCI function's power management state as well as to enable/monitor PMEs." hexmask.long.byte 0x4 24.--31. 1. "DATA_REG_ADD_INFO,Data. This field is used to report the state dependent data requested by the Data_Select field. The value of this field is scaled by the value reported by the Data_Scale field." rbitfld.long 0x4 23. "BUS_PWR_CLK_CON_EN,Bus Power/Clock Control Enable. For a description of this standard PCIe register field see the PCI Express Base Specification." "0,1" rbitfld.long 0x4 22. "B2_B3_SUPPORT,B2B3 Support for D3hot. For a description of this standard PCIe register field see the PCI Express Base Specification." "0,1" hexmask.long.byte 0x4 16.--21. 1. "RSVDP_16,Reserved for future use." newline bitfld.long 0x4 15. "PME_STATUS,PME_Status. This bit is set when the function normally generates a PME signal. The value of this bit is not affected by the value of the PME_En bit. If PME_Support bit 31 of the Power Management Capabilities register is clear this bit is.." "0,1" rbitfld.long 0x4 13.--14. "DATA_SCALE,Data_Scale. This field indicates the scaling factor to be used when interpreting the value of the Data field. The value and meaning of this field varies depending on which data value has been selected by the Data_Select field. For more details.." "0,1,2,3" hexmask.long.byte 0x4 9.--12. 1. "DATA_SELECT,Data_Select. This 4-bit field is used to select which data is to be reported through the Data and Data_Scale field. If the Data field is not implemented this field must be hardwired to 0000b." bitfld.long 0x4 8. "PME_ENABLE,PME_En. - When set the function is permitted to generate a PME. - When clear the function is not permitted to generate a PME. If PME_Support is 1 xxxxb (PME generation from D3cold) or the function consumes Aux power and Aux power is.." "0,1" newline hexmask.long.byte 0x4 4.--7. 1. "RSVDP_4,Reserved for future use." bitfld.long 0x4 3. "NO_SOFT_RST,No_Soft_Reset. This bit indicates the state of the function after writing the PowerState field to transition the function from D3hot to D0. - When set this transition preserves internal function state. The function is in D0Active and no.." "0,1" rbitfld.long 0x4 2. "RSVDP_2,Reserved for future use." "0,1" bitfld.long 0x4 0.--1. "POWER_STATE,PowerState. This 2-bit field is used both to determine the current power state of a function and to set the function into a new power state. The definition of the field values is given below. You can write to this register; however the.." "D0,D1,D2,D3hot" tree.end tree "PF0_PCIE_CAP (PF PCI Express Capability Structure)" group.long (0x0+0x70)++0x33 line.long 0x0 "PCIE_CAP_ID_PCIE_NEXT_CAP_PTR_PCIE_CAP_REG,PCI Express Capabilities. ID. Next Pointer Register." rbitfld.long 0x0 31. "RSVDP_31,Reserved for future use." "0,1" rbitfld.long 0x0 30. "RSVD,Reserved." "0,1" newline hexmask.long.byte 0x0 25.--29. 1. "PCIE_INT_MSG_NUM,PCIE Interrupt Message Number. For a description of this standard PCIe register field see the PCI Express Base Specification. Interrupt Message Number. This field indicates which MSI/MSI-X vector is used for the interrupt message.." bitfld.long 0x0 24. "PCIE_SLOT_IMP,Slot Implemented. When set this bit indicates that the Link associated with this Port is connected to a slot (as compared to being connected to a system-integrated device or being disabled). This bit is valid for Downstream Ports. This bit.." "0,1" newline hexmask.long.byte 0x0 20.--23. 1. "PCIE_DEV_PORT_TYPE,Device/Port Type. Indicates the specific type of this PCI Express function. Note: Different functions in a Multi-Function Device can generally be of different types. Defined encodings for functions that implement a Type 00h PCI.." hexmask.long.byte 0x0 16.--19. 1. "PCIE_CAP_REG,Capability Version. Indicates PCI-SIG defined PCI Express Capability structure version number. A version of the specification that changes the PCI Express Capability structure in a way that is not otherwise identifiable (for example through.." newline hexmask.long.byte 0x0 8.--15. 1. "PCIE_CAP_NEXT_PTR,Next Capability Pointer. This field contains the offset to the next PCI Capability structure or 00h if no other items exist in the linked list of Capabilities. Note: The access attributes of this field are as follows: - Wire: No access." hexmask.long.byte 0x0 0.--7. 1. "PCIE_CAP_ID,Capability ID. Indicates the PCI Express Capability structure. This field must return a Capability ID of 10h indicating that this is a PCI Express Capability structure." line.long 0x4 "DEVICE_CAPABILITIES_REG,Device Capabilities Register. The Device Capabilities register identifies PCI Express device function specific capabilities." hexmask.long.word 0x4 16.--31. 1. "RSVDP_16,Reserved for future use." bitfld.long 0x4 15. "PCIE_CAP_ROLE_BASED_ERR_REPORT,Role-Based Error Reporting. When set this bit indicates that the function implements the functionality originally defined in the Error Reporting ECN for PCI Express Base Specification Revision 1.0a and later incorporated.." "0,1" newline hexmask.long.word 0x4 6.--14. 1. "RSVDP_6,Reserved for future use." bitfld.long 0x4 5. "PCIE_CAP_EXT_TAG_SUPP,Extended Tag Field Supported. This bit in combination with the 10-Bit Tag Requester Supported bit in the Device Capabilities 2 register indicates the maximum supported size of the Tag field as a Requester. This bit must be set if.." "0,1" newline bitfld.long 0x4 3.--4. "PCIE_CAP_PHANTOM_FUNC_SUPPORT,Phantom Functions Supported. This field indicates the support for use of unclaimed function numbers to extend the number of outstanding transactions allowed by logically combining unclaimed function numbers (called Phantom.." "0,1,2,3" bitfld.long 0x4 0.--2. "PCIE_CAP_MAX_PAYLOAD_SIZE,Max_Payload_Size Supported. This field indicates the maximum payload size that the function can support for TLPs. Defined encodings are: - 000b: 128 bytes max payload size - 001b: 256 bytes max payload size - 010b: 512 bytes max.." "0,1,2,3,4,5,6,7" line.long 0x8 "DEVICE_CONTROL_DEVICE_STATUS,Device Control and Device Status Register. This register controls PCI Express device specific parameters and provides information about PCI Express device (function) specific parameters." hexmask.long.word 0x8 22.--31. 1. "RSVDP_22,Reserved for future use." rbitfld.long 0x8 21. "PCIE_CAP_TRANS_PENDING,Transactions Pending. Endpoints: When set this bit indicates that the function has issued Non-Posted Requests that have not been completed. A Function reports this bit cleared only when all outstanding Non-Posted Requests have.." "0,1" newline rbitfld.long 0x8 20. "PCIE_CAP_AUX_POWER_DETECTED,AUX Power Detected. Functions that require Aux power report this bit as set if Aux power is detected by the function. This bit is derived by sampling the sys_aux_pwr_det input." "0,1" bitfld.long 0x8 19. "PCIE_CAP_UNSUPPORTED_REQ_DETECTED,Unsupported Request Detected. This bit indicates that the function received an Unsupported Request. Errors are logged in this register regardless of whether error reporting is enabled or not in the Device Control.." "0,1" newline bitfld.long 0x8 18. "PCIE_CAP_FATAL_ERR_DETECTED,Fatal Error Detected. This bit indicates status of Fatal errors detected. Errors are logged in this register regardless of whether error reporting is enabled or not in the Device Control register. For a Multi-Function device.." "0,1" bitfld.long 0x8 17. "PCIE_CAP_NON_FATAL_ERR_DETECTED,Non-Fatal Error Detected. This bit indicates status of Non-fatal errors detected. Errors are logged in this register regardless of whether error reporting is enabled or not in the Device Control register. For a.." "0,1" newline bitfld.long 0x8 16. "PCIE_CAP_CORR_ERR_DETECTED,Correctable Error Detected. This bit indicates status of correctable errors detected. Errors are logged in this register regardless of whether error reporting is enabled or not in the Device Control register. For a.." "0,1" bitfld.long 0x8 15. "PCIE_CAP_INITIATE_FLR,Initiate Function Level Reset (applicable to Endpoints with Function Level Reset Capability set to 1b). A write of 1b initiates Function Level Reset to the Function. The value read by software from this bit is always 0b." "0,1" newline bitfld.long 0x8 12.--14. "PCIE_CAP_MAX_READ_REQ_SIZE,Max_Read_Request_Size. This field sets the maximum Read Request size for the function as a Requester. The function must not generate Read Requests with a size exceeding the set value. Defined encodings for this field are: -.." "0,1,2,3,4,5,6,7" rbitfld.long 0x8 11. "PCIE_CAP_EN_NO_SNOOP,Enable No Snoop. If this bit is set the function is permitted to Set the No Snoop bit in the Requester Attributes of transactions it initiates that do not require hardware enforced cache coherency (see section 2.2.6.5 in PCI Express.." "0,1" newline bitfld.long 0x8 10. "PCIE_CAP_AUX_POWER_PM_EN,Aux Power PM Enable. This bit is derived by sampling the sys_aux_pwr_det input. When set this bit enables a function to draw Aux power independent of PME Aux power. Functions that require Aux power on legacy operating systems.." "0,1" rbitfld.long 0x8 9. "PCIE_CAP_PHANTOM_FUNC_EN,Phantom Functions Enable. This bit in combination with the 10-Bit Tag Requester Enable bit in the Device Control 2 register determines how many Tag field bits a Requester is permitted to use. When the 10-Bit Tag Requester.." "0,1" newline rbitfld.long 0x8 8. "PCIE_CAP_EXT_TAG_EN,Extended Tag Field Enable. This bit in combination with the 10-Bit Tag Requester Enable bit in the Device Control 2 register determines how many Tag field bits a Requester is permitted to use. When the 10-Bit Tag Requester Enable.." "0,1" bitfld.long 0x8 5.--7. "PCIE_CAP_MAX_PAYLOAD_SIZE_CS,Max_Payload_Size. This field sets maximum TLP payload size for the Function. As a Receiver the Function must handle TLPs as large as the set value. As a Transmitter the Function must not generate TLPs exceeding the set.." "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 4. "PCIE_CAP_EN_REL_ORDER,Enable Relaxed Ordering. If this bit is set the function is permitted to set the Relaxed Ordering bit in the Attributes field of transactions it initiates that do not require strong write ordering (for more details see section.." "0,1" bitfld.long 0x8 3. "PCIE_CAP_UNSUPPORT_REQ_REP_EN,Unsupported Request Reporting Enable. This bit in conjunction with other bits controls the signaling of Unsupported Request Errors by sending error Messages (for more details see section 6.2.5 and section 6.2.6 of PCI.." "0,1" newline bitfld.long 0x8 2. "PCIE_CAP_FATAL_ERR_REPORT_EN,Fatal Error Reporting Enable. This bit in conjunction with other bits controls sending ERR_FATAL Messages (for more details see section 6.2.5 and section 6.2.6 of of PCI Express Base Specification). For a Multi-Function.." "0,1" bitfld.long 0x8 1. "PCIE_CAP_NON_FATAL_ERR_REPORT_EN,Non-Fatal Error Reporting Enable. This bit in conjunction with other bits controls sending ERR_NONFATAL Messages (for more details see section 6.2.5 and Section 6.2.6 of PCI Express Base Specification). For a.." "0,1" newline bitfld.long 0x8 0. "PCIE_CAP_CORR_ERR_REPORT_EN,Correctable Error Reporting Enable. This bit in conjunction with other bits controls sending ERR_COR Messages (for more details see section 6.2.5 section 6.2.6 and section 6.2.10.2 of PCI Express Base Specification). For.." "0,1" line.long 0xC "LINK_CAPABILITIES_REG,Link Capabilities Register. The Link Capabilities register identifies PCI Express Link specific capabilities." hexmask.long.byte 0xC 24.--31. 1. "PCIE_CAP_PORT_NUM,Port Number. This field indicates the PCI Express Port number for the given PCI Express Link. Multi-Function Devices associated with an Upstream Port must report the same value in this field for all functions. Note: The access.." rbitfld.long 0xC 23. "RSVDP_23,Reserved for future use." "0,1" newline bitfld.long 0xC 22. "PCIE_CAP_ASPM_OPT_COMPLIANCE,ASPM Optionality Compliance. This bit must be set to 1b in all functions. Components implemented against certain earlier versions of this specification will have this bit set to 0b. Software is permitted to use the value of.." "0,1" bitfld.long 0xC 21. "PCIE_CAP_LINK_BW_NOT_CAP,Link Bandwidth Notification Capability. A value of 1b indicates support for the Link Bandwidth Notification status and interrupt mechanisms. This capability is required for all Root Ports and Switch Downstream Ports supporting.." "0,1" newline rbitfld.long 0xC 20. "PCIE_CAP_DLL_ACTIVE_REP_CAP,Data Link Layer Link Active Reporting Capable. For a Downstream Port the controller hardwires this bit to 1b if the component supports the optional capability of reporting the DL_Active state of the Data Link Control and.." "0,1" bitfld.long 0xC 19. "PCIE_CAP_SURPRISE_DOWN_ERR_REP_CAP,Surprise Down Error Reporting Capable. For a Downstream Port this bit must be set if the component supports the optional capability of detecting and reporting a Surprise Down error condition. For Upstream Ports and.." "0,1" newline rbitfld.long 0xC 18. "PCIE_CAP_CLOCK_POWER_MAN,Clock Power Management. For Upstream Ports a value of 1b in this bit indicates that the component tolerates the removal of any reference clock(s) via the 'clock request' (CLKREQ#) mechanism when the Link is in the L1 and L2/L3.." "0,1" bitfld.long 0xC 15.--17. "PCIE_CAP_L1_EXIT_LATENCY,L1 Exit Latency. This field indicates the L1 exit latency for the given PCI Express Link. The value reported indicates the length of time this Port requires to complete transition from ASPM L1 to L0. If ASPM L1 is not supported.." "0,1,2,3,4,5,6,7" newline bitfld.long 0xC 12.--14. "PCIE_CAP_L0S_EXIT_LATENCY,L0s Exit Latency. This field indicates the L0s exit latency for the given PCI Express Link. The value reported indicates the length of time this Port requires to complete transition from L0s to L0. If L0s is not supported the.." "0,1,2,3,4,5,6,7" bitfld.long 0xC 10.--11. "PCIE_CAP_ACTIVE_STATE_LINK_PM_SUPPORT,Active State Power Management (ASPM) Support. This field indicates the level of ASPM supported on the given PCI Express Link. For more details on ASPM support requirements see section 5.4.1 of PCI Express Base.." "0,1,2,3" newline hexmask.long.byte 0xC 4.--9. 1. "PCIE_CAP_MAX_LINK_WIDTH,Maximum Link Width. This field indicates the maximum Link width (xN - corresponding to N Lanes) implemented by the component. This value is permitted to exceed the number of Lanes routed to the slot (Downstream Port) adapter.." hexmask.long.byte 0xC 0.--3. 1. "PCIE_CAP_MAX_LINK_SPEED,Max Link Speed. This field indicates the maximum Link speed of the associated Port. The encoded value specifies a bit location in the Supported Link Speeds Vector (in the Link Capabilities 2 register) that corresponds to the.." line.long 0x10 "LINK_CONTROL_LINK_STATUS_REG,Link Control and Link Status Register. This register controls and provides information about PCI Express Link specific parameters." bitfld.long 0x10 31. "PCIE_CAP_LINK_AUTO_BW_STATUS,Link Autonomous Bandwidth Status. This bit is set by hardware to indicate that hardware has autonomously changed Link speed or width without the Port transitioning through DL_Down status for reasons other than to attempt to.." "0,1" bitfld.long 0x10 30. "PCIE_CAP_LINK_BW_MAN_STATUS,Link Bandwidth Management Status. This bit is set by hardware to indicate that either of the following has occurred without the Port transitioning through DL_Down status: - A Link retraining has completed following a write of.." "0,1" newline rbitfld.long 0x10 29. "PCIE_CAP_DLL_ACTIVE,Data Link Layer Link Active. This bit indicates the status of the Data Link Control and Management State Machine. It returns a 1b to indicate the DL_Active state 0b otherwise. This bit must be implemented if the Data Link Layer Link.." "0,1" bitfld.long 0x10 28. "PCIE_CAP_SLOT_CLK_CONFIG,Slot Clock Configuration. This bit indicates that the component uses the same physical reference clock that the platform provides on the connector. If the device uses an independent clock irrespective of the presence of a.." "0,1" newline rbitfld.long 0x10 27. "PCIE_CAP_LINK_TRAINING,Link Training. This read-only bit indicates that the Physical Layer LTSSM is in the Configuration or Recovery state or that 1b was written to the Retrain Link bit but Link training has not yet begun. Hardware clears this bit when.." "0,1" rbitfld.long 0x10 26. "RSVDP_26,Reserved for future use." "0,1" newline hexmask.long.byte 0x10 20.--25. 1. "PCIE_CAP_NEGO_LINK_WIDTH,Negotiated Link Width. This field indicates the negotiated width of the given PCI Express Link. Defined encodings are: -00 0001b: x1 -00 0010b: x2 -00 0100b: x4 -00 1000b: x8 -00 1100b: x12 -01 0000b: x16 -10 0000b: x32 All other.." hexmask.long.byte 0x10 16.--19. 1. "PCIE_CAP_LINK_SPEED,Current Link Speed. This field indicates the negotiated Link speed of the given PCI Express Link. The encoded value specifies a bit location in the Supported Link Speeds Vector (in the Link Capabilities 2 register) that corresponds to.." newline bitfld.long 0x10 14.--15. "PCIE_CAP_DRS_SIGNALING_CONTROL,DRS Signaling Control. Indicates the mechanism used to report reception of a DRS message. Must be implemented for Downstream Ports with the DRS Supported bit Set in the Link Capabilities 2 Register. Encodings are: - 00b:.." "0,1,2,3" rbitfld.long 0x10 12.--13. "RSVDP_12,Reserved for future use." "0,1,2,3" newline bitfld.long 0x10 11. "PCIE_CAP_LINK_AUTO_BW_INT_EN,Link Autonomous Bandwidth Management Interrupt Enable. When set this bit enables the generation of an interrupt to indicate that the Link Autonomous Bandwidth Status bit has been set. The write value is gated with the.." "0,1" bitfld.long 0x10 10. "PCIE_CAP_LINK_BW_MAN_INT_EN,Link Bandwidth Management Interrupt Enable. When set this bit enables the generation of an interrupt to indicate that the Link Bandwidth Management Status bit has been set. The write value is gated with the.." "0,1" newline bitfld.long 0x10 9. "PCIE_CAP_HW_AUTO_WIDTH_DISABLE,Hardware Autonomous Width Disable. When set this bit disables hardware from changing the Link width for reasons other than attempting to correct unreliable Link operation by reducing Link width. For a Multi-Function Device.." "0,1" bitfld.long 0x10 8. "PCIE_CAP_EN_CLK_POWER_MAN,Enable Clock Power Management. Applicable only for Upstream Ports and with form factors that support a 'Clock Request' (CLKREQ#) mechanism this bit operates as follows: - 0b: Clock power management is disabled and device must.." "0,1" newline bitfld.long 0x10 7. "PCIE_CAP_EXTENDED_SYNCH,Extended Synch. When set this bit forces the transmission of additional Ordered Sets when exiting the L0s state (see section 4.2.4.5 of PCI Express Base Specification) and when in the Recovery state (see section 4.2.6.4.1 of PCI.." "0,1" bitfld.long 0x10 6. "PCIE_CAP_COMMON_CLK_CONFIG,Common Clock Configuration. When set this bit indicates that this component and the component at the opposite end of this Link are operating with a distributed common reference clock. A value of 0b indicates that this.." "0,1" newline bitfld.long 0x10 5. "PCIE_CAP_RETRAIN_LINK,Retrain Link. A write of 1b to this bit initiates Link retraining by directing the Physical Layer LTSSM to the Recovery state. If the LTSSM is already in Recovery or Configuration re-entering Recovery is permitted but not required." "0,1" bitfld.long 0x10 4. "PCIE_CAP_LINK_DISABLE,Link Disable. This bit disables the Link by directing the LTSSM to the Disabled state when set; this bit is Reserved on Endpoints PCI Express to PCI/PCI-X bridges and Upstream Ports of Switches. Writes to this bit are immediately.." "0,1" newline bitfld.long 0x10 3. "PCIE_CAP_RCB,Read Completion Boundary (RCB). Root Ports: Indicates the RCB value for the Root Port. Refer to section 2.3.1.1 of PCI Express Base Specification for the definition of the parameter RCB. Defined encodings are: - 0b: 64 byte - 1b: 128 byte.." "0,1" rbitfld.long 0x10 2. "RSVDP_2,Reserved for future use." "0,1" newline bitfld.long 0x10 0.--1. "PCIE_CAP_ACTIVE_STATE_LINK_PM_CONTROL,Active State Power Management (ASPM) Control. This field controls the level of ASPM enabled on the given PCI Express Link. See section 5.4.1.3 of PCI Express Base Specification for requirements on when and how to.." "0,1,2,3" line.long 0x14 "SLOT_CAPABILITIES_REG,Slot Capabilities Register. The Slot Capabilities register identifies PCI Express slot specific capabilities." hexmask.long.word 0x14 19.--31. 1. "PCIE_CAP_PHY_SLOT_NUM,Physical Slot Number. This field indicates the physical slot number attached to this Port. This field must be hardware initialized to a value that assigns a slot number that is unique within the chassis regardless of the form.." bitfld.long 0x14 18. "PCIE_CAP_NO_CMD_CPL_SUPPORT,No Command Completed Support. When set this bit indicates that this slot does not generate software notification when an issued command is completed by the Hot-Plug Controller. This bit is only permitted to be set if the.." "0,1" newline bitfld.long 0x14 17. "PCIE_CAP_ELECTROMECH_INTERLOCK,Electromechanical Interlock Present. When set this bit indicates that an Electromechanical Interlock is implemented on the chassis for this slot. Note: The access attributes of this field are as follows: - Wire: No access." "0,1" bitfld.long 0x14 15.--16. "PCIE_CAP_SLOT_POWER_LIMIT_SCALE,Slot Power Limit Scale. Specifies the scale used for the Slot Power Limit Value (for more details see Section 6.9 of PCI Express Base Specification). Range of Values: - 00b: 1.0x - 01b: 0.1x - 10b: 0.01x - 11b: 0.001x.." "0,1,2,3" newline hexmask.long.byte 0x14 7.--14. 1. "PCIE_CAP_SLOT_POWER_LIMIT_VALUE,Slot Power Limit Value. In combination with the Slot Power Limit Scale value specifies the upper limit on power supplied by the slot (for more detais see Section 6.9 of PCI Express Base Specification) or by other means.." bitfld.long 0x14 6. "PCIE_CAP_HOT_PLUG_CAPABLE,Hot-Plug Capable. When set this bit indicates that this slot is capable of supporting hot-plug operations. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then R/W else R" "0,1" newline bitfld.long 0x14 5. "PCIE_CAP_HOT_PLUG_SURPRISE,Hot-Plug Surprise. When set this bit indicates that an adapter present in this slot might be removed from the system without any prior notification. This is a form factor specific capability. This bit is an indication to the.." "0,1" bitfld.long 0x14 4. "PCIE_CAP_POWER_INDICATOR,Power Indicator Present. When set this bit indicates that a Power Indicator is electrically controlled by the chassis for this slot. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if.." "0,1" newline bitfld.long 0x14 3. "PCIE_CAP_ATTENTION_INDICATOR,Attention Indicator Present. When set this bit indicates that an Attention Indicator is electrically controlled by the chassis. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if.." "0,1" bitfld.long 0x14 2. "PCIE_CAP_MRL_SENSOR,MRL Sensor Present. When set this bit indicates that an MRL Sensor is implemented on the chassis for this slot. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then R/W else R" "0,1" newline bitfld.long 0x14 1. "PCIE_CAP_POWER_CONTROLLER,Power Controller Present. When set this bit indicates that a software programmable Power Controller is implemented for this slot/adapter (depending on form factor). Note: The access attributes of this field are as follows: -.." "0,1" bitfld.long 0x14 0. "PCIE_CAP_ATTENTION_INDICATOR_BUTTON,Attention Button Present. When set this bit indicates that an Attention Button for this slot is electrically controlled by the chassis. Note: The access attributes of this field are as follows: - Wire: No access. -.." "0,1" line.long 0x18 "SLOT_CONTROL_SLOT_STATUS,Slot Control and Status Register. This register controls and provides information about PCI Express Slot specific parameters." hexmask.long.byte 0x18 25.--31. 1. "RSVDP_25,Reserved for future use." bitfld.long 0x18 24. "PCIE_CAP_DLL_STATE_CHANGED,Data Link Layer State Changed. This bit is set when the value reported in the Data Link Layer Link Active bit of the Link Status register is changed. In response to a Data Link Layer State Changed event software must read the.." "0,1" newline rbitfld.long 0x18 23. "PCIE_CAP_ELECTROMECH_INTERLOCK_STATUS,Electromechanical Interlock Status. If an Electromechanical Interlock is implemented this bit indicates the status of the Electromechanical Interlock. Defined encodings are: - 0b: Electromechanical Interlock.." "0,1" rbitfld.long 0x18 22. "PCIE_CAP_PRESENCE_DETECT_STATE,Presence Detect State. This bit indicates the presence of an adapter in the slot reflected by the logical 'OR' of the Physical Layer in-band presence detect mechanism and if present any out-of-band presence detect.." "0,1" newline rbitfld.long 0x18 21. "PCIE_CAP_MRL_SENSOR_STATE,MRL Sensor State. This bit reports the status of the MRL sensor if implemented. Defined encodings are: - 0b: MRL Closed - 1b: MRL Open" "0,1" bitfld.long 0x18 20. "PCIE_CAP_CMD_CPLD,Command Completed. If Command Completed notification is supported (if the No Command Completed Support bit in the Slot Capabilities register is 0b) this bit is set when a hot-plug command has completed and the Hot-Plug Controller is.." "0,1" newline bitfld.long 0x18 19. "PCIE_CAP_PRESENCE_DETECTED_CHANGED,Presence Detect Changed. This bit is set when the value reported in the Presence Detect State bit is changed." "0,1" bitfld.long 0x18 18. "PCIE_CAP_MRL_SENSOR_CHANGED,MRL Sensor Changed. If an MRL sensor is implemented this bit is set when a MRL Sensor state change is detected. If an MRL sensor is not implemented this bit must not be set." "0,1" newline bitfld.long 0x18 17. "PCIE_CAP_POWER_FAULT_DETECTED,Power Fault Detected. If a Power Controller that supports power fault detection is implemented this bit issSet when the Power Controller detects a power fault at this slot. Note: Depending on hardware capability it is.." "0,1" bitfld.long 0x18 16. "PCIE_CAP_ATTENTION_BUTTON_PRESSED,Attention Button Pressed. If an Attention Button is implemented this bit is set when the attention button is pressed. If an Attention Button is not supported this bit must not be set." "0,1" newline rbitfld.long 0x18 14.--15. "RSVDP_14,Reserved for future use." "0,1,2,3" bitfld.long 0x18 12. "PCIE_CAP_DLL_STATE_CHANGED_EN,Data Link Layer State Changed Enable. If the Data Link Layer Link Active Reporting capability is 1b this bit enables software notification when Data Link Layer Link Active bit is changed. If the Data Link Layer Link Active.." "0,1" newline bitfld.long 0x18 11. "PCIE_CAP_ELECTROMECH_INTERLOCK_CTRL,Electromechanical Interlock Control. If an Electromechanical Interlock is implemented a write of 1b to this bit causes the state of the interlock to toggle. A write of 0b to this bit has no effect. A read of this bit.." "0,1" bitfld.long 0x18 10. "PCIE_CAP_POWER_CONTROLLER_CTRL,Power Controller Control. If a Power Controller is implemented this bit when written sets the power state of the slot per the defined encodings. Reads of this bit must reflect the value from the latest write even if the.." "0,1" newline bitfld.long 0x18 8.--9. "PCIE_CAP_POWER_INDICATOR_CTRL,Power Indicator Control. If a Power Indicator is implemented writes to this field set the Power Indicator to the written state. Reads of this field must reflect the value from the latest write even if the corresponding.." "0,1,2,3" bitfld.long 0x18 6.--7. "PCIE_CAP_ATTENTION_INDICATOR_CTRL,Attention Indicator Control. If an Attention Indicator is implemented writes to this field set the Attention Indicator to the written state. Reads of this field must reflect the value from the latest write even if the.." "0,1,2,3" newline bitfld.long 0x18 5. "PCIE_CAP_HOT_PLUG_INT_EN,Hot-Plug Interrupt Enable. When set this bit enables generation of an interrupt on enabled hot-plug events. If the Hot Plug Capable bit in the Slot Capabilities register is clear this bit is permitted to be read-only with a.." "0,1" bitfld.long 0x18 4. "PCIE_CAP_CMD_CPL_INT_EN,Command Completed Interrupt Enable. If Command Completed notification is supported (if the No Command Completed Support bit in the Slot Capabilities register is 0b) when set this bit enables software notification when a hot-plug.." "0,1" newline bitfld.long 0x18 3. "PCIE_CAP_PRESENCE_DETECT_CHANGE_EN,Presence Detect Changed Enable. When set this bit enables software notification on a presence detect changed event (for more details see Section 6.7.3 of PCI Express Base Specification). If the Hot-Plug Capable bit in.." "0,1" bitfld.long 0x18 2. "PCIE_CAP_MRL_SENSOR_CHANGED_EN,MRL Sensor Changed Enable. When set this bit enables software notification on a MRL sensor changed event (for more details see Section 6.7.3 of PCI Express Base Specification). If the MRL Sensor Present bit in the Slot.." "0,1" newline bitfld.long 0x18 1. "PCIE_CAP_POWER_FAULT_DETECTED_EN,Power Fault Detected Enable. When set this bit enables software notification on a power fault event (for more details see Section 6.7.3 of PCI Express Base Specification). If a Power Controller that supports power fault.." "0,1" bitfld.long 0x18 0. "PCIE_CAP_ATTENTION_BUTTON_PRESSED_EN,Attention Button Pressed Enable. When set to 1b this bit enables software notification on an attention button pressed event (for more details see Section 6.7.3 of PCI Express Base Specification). If the Attention.." "0,1" line.long 0x1C "ROOT_CONTROL_ROOT_CAPABILITIES_REG,Root Control and Capabilities Register. This register controls PCI Express Root Complex specific parameters and identifies PCI Express Root Port specific capabilities." hexmask.long.word 0x1C 17.--31. 1. "RSVDP_17,Reserved for future use." bitfld.long 0x1C 16. "PCIE_CAP_CRS_SW_VISIBILITY,CRS Software Visibility Capable. For a description of this standard PCIe register field see the PCI Express Base Specification. CRS Software Visibility. When set this bit indicates that the Root Port is capable of returning.." "0,1" newline hexmask.long.word 0x1C 5.--15. 1. "RSVDP_5,Reserved for future use." bitfld.long 0x1C 4. "PCIE_CAP_CRS_SW_VISIBILITY_EN,CRS Software Visibility Enable. When set this bit enables the Root Port to return Configuration Request Retry Status (CRS) Completion Status to software (for more details see section 2.3.1 of PCI Express Base.." "0,1" newline bitfld.long 0x1C 3. "PCIE_CAP_PME_INT_EN,PME Interrupt Enable. When set this bit enables PME interrupt generation upon receipt of a PME Message as reflected in the PME Status bit (for more details see Table 7-29 of PCI Express Base Specification). A PME interrupt is also.." "0,1" bitfld.long 0x1C 2. "PCIE_CAP_SYS_ERR_ON_FATAL_ERR_EN,System Error on Fatal Error Enable. If set this bit indicates that a System Error should be generated if a Fatal error (ERR_FATAL) is reported by any of the devices in the Hierarchy Domain associated with this Root Port.." "0,1" newline bitfld.long 0x1C 1. "PCIE_CAP_SYS_ERR_ON_NON_FATAL_ERR_EN,System Error on Non-Fatal Error Enable. If set this bit indicates that a System Error should be generated if a Non-fatal error (ERR_NONFATAL) is reported by any of the devices in the Hierarchy Domain associated with.." "0,1" bitfld.long 0x1C 0. "PCIE_CAP_SYS_ERR_ON_CORR_ERR_EN,System Error on Correctable Error Enable. If set this bit indicates that a System Error should be generated if a correctable error (ERR_COR) is reported by any of the devices in the Hierarchy Domain associated with this.." "0,1" line.long 0x20 "ROOT_STATUS_REG,Root Status Register. The Root Status register provides information about PCI Express device specific parameters." hexmask.long.word 0x20 18.--31. 1. "RSVDP_18,Reserved for future use." rbitfld.long 0x20 17. "PCIE_CAP_PME_PENDING,PME Pending. This bit indicates that another PME is pending when the PME Status bit is s et. When the PME Status bit is cleared by software; the PME is delivered by hardware by setting the PME Status bit again and updating the PME.." "0,1" newline bitfld.long 0x20 16. "PCIE_CAP_PME_STATUS,PME Status. This bit indicates that PME was asserted by the PME Requester indicated in the PME Requester ID field. Subsequent PMEs are kept pending until the status register is cleared by software by writing a 1b." "0,1" hexmask.long.word 0x20 0.--15. 1. "PCIE_CAP_PME_REQ_ID,PME Requester ID. This field indicates the PCI Requester ID of the last PME Requester. This field is only valid when the PME Status bit is set." line.long 0x24 "DEVICE_CAPABILITIES2_REG,Device Capabilities 2 Register." bitfld.long 0x24 31. "PCIE_CAP_FRS_SUPPORTED,FRS Supported. When set indicates support for the optional Function Readiness Status (FRS) capability. Must be set for all Functions that support generation or reception capabilities of FRS Messages. Must not be set by Switch.." "0,1" hexmask.long.byte 0x24 24.--30. 1. "RSVDP_24,Reserved for future use." newline bitfld.long 0x24 22.--23. "PCIE_CAP2_CFG_MAX_END2END_TLP_PRFXS,Max End-End TLP Prefixes. Indicates the maximum number of End-End TLP Prefixes supported by this Function. For more details see Section 2.2.10.2 of PCI Express Base Specification. Values are: - 01b: 1 End-End TLP.." "0,1,2,3" bitfld.long 0x24 21. "PCIE_CAP2_CFG_END2END_TLP_PRFX_SUPPORT,End-End TLP Prefix Supported. Indicates whether End-End TLP Prefix support is offered by a Function. Values are: - 0b: No Support - 1b: Support is provided to receive TLPs containing End-End TLP Prefixes. All Ports.." "0,1" newline bitfld.long 0x24 20. "PCIE_CAP2_CFG_EXTND_FMT_SUPPORT,Extended Fmt Field Supported. If set the Function supports the 3-bit definition of the Fmt field. If clear the Function supports a 2-bit definition of the Fmt field. For more details see section 2.2 of PCI Express Base.." "0,1" rbitfld.long 0x24 17. "PCIE_CAP2_10_BIT_TAG_REQ_SUPPORT,10-Bit Tag Requester Supported. If this bit is set the Function supports 10-Bit Tag Requester capability; otherwise the Function does not. This bit must not be set if the 10-Bit Tag Completer Supported bit is clear." "0,1" newline rbitfld.long 0x24 16. "PCIE_CAP2_10_BIT_TAG_COMP_SUPPORT,10-Bit Tag Completer Supported. If this bit is set the Function supports 10-Bit Tag Completer capability; otherwise the Function does not. For more details see section 2.2.6.2. of PCI Express Base Specification." "0,1" rbitfld.long 0x24 13. "PCIE_CAP_TPH_CMPLT_SUPPORT_1,TPH Completer Supported Bit 1." "0,1" newline rbitfld.long 0x24 12. "PCIE_CAP_TPH_CMPLT_SUPPORT_0,TPH Completer Supported Bit 0. Value of this bit along with TPH Completer Supported Bit 1 indicates Completer support for TPH or Extended TPH. Applicable only to Root Ports and Endpoints. For all other Functions this field.." "0,1" bitfld.long 0x24 11. "PCIE_CAP_LTR_SUPP,LTR Mechanism Supported. A value of 1b indicates support for the optional Latency Tolerance Reporting (LTR) mechanism. Root Ports Switches and Endpoints are permitted to implement this capability. For a Multi-Function Device associated.." "0,1" newline rbitfld.long 0x24 10. "PCIE_CAP_NO_RO_EN_PR2PR_PAR,No RO-enabled PR-PR Passing. If this bit is set the routing element never carries out the passing permitted by Table 2-39 of PCI Express Base Specification entry A2b that is associated with the Relaxed Ordering Attribute.." "0,1" rbitfld.long 0x24 9. "PCIE_CAP_128_CAS_CPL_SUPP,128-bit CAS Completer Supported. Applicable to Functions with Memory Space BARs as well as all Root Ports; must be 0b otherwise. This bit must be set to 1b if the Function supports this optional capability. For more details see.." "0,1" newline rbitfld.long 0x24 8. "PCIE_CAP_64_ATOMIC_CPL_SUPP,64-bit AtomicOp Completer Supported. Applicable to Functions with Memory Space BARs as well as all Root Ports; must be 0b otherwise. Includes FetchAdd Swap and CAS AtomicOps. This bit must be set to 1b if the Function.." "0,1" rbitfld.long 0x24 7. "PCIE_CAP_32_ATOMIC_CPL_SUPP,32-bit AtomicOp Completer Supported. Applicable to Functions with Memory Space BARs as well as all Root Ports; must be 0b otherwise. Includes FetchAdd Swap and CAS AtomicOps. This bit must be set to 1b if the Function.." "0,1" newline rbitfld.long 0x24 6. "PCIE_CAP_ATOMIC_ROUTING_SUPP,AtomicOp Routing Supported. Applicable only to Switch Upstream Ports Switch Downstream Ports and Root Ports; must be 0b for other Function types. This bit must be set to 1b if the Port supports this optional capability. For.." "0,1" rbitfld.long 0x24 5. "PCIE_CAP_ARI_FORWARD_SUPPORT,ARI Forwarding Supported. Applicable only to Switch Downstream Ports and Root Ports; must be 0b for other Function types. This bit must be set to 1b if a Switch Downstream Port or Root Port supports this optional capability." "0,1" newline rbitfld.long 0x24 4. "PCIE_CAP_CPL_TIMEOUT_DISABLE_SUPPORT,Completion Timeout Disable Supported. A value of 1b indicates support for the Completion Timeout Disable mechanism. The Completion Timeout Disable mechanism is required for Endpoints that issue Requests on their own.." "0,1" hexmask.long.byte 0x24 0.--3. 1. "PCIE_CAP_CPL_TIMEOUT_RANGE,Completion Timeout Ranges Supported. This field indicates device Function support for the optional Completion Timeout programmability mechanism. This mechanism allows system software to modify the Completion Timeout value. This.." line.long 0x28 "DEVICE_CONTROL2_DEVICE_STATUS2_REG,Device Control 2 and Status 2 Register." hexmask.long.word 0x28 16.--31. 1. "RSVDP_16,Reserved for future use." bitfld.long 0x28 15. "PCIE_CTRL2_CFG_END2END_TLP_PFX_BLCK,End-End TLP Prefix Blocking. Controls whether the routing function is permitted to forward TLPs containing an End-End TLP Prefix. Values are: - 0b: Forwarding Enabled - Function is permitted to send TLPs with End-End.." "0,1" newline rbitfld.long 0x28 11. "RSVDP_11,Reserved for future use." "0,1" bitfld.long 0x28 10. "PCIE_CAP_LTR_EN,LTR Mechanism Enable. When set to 1b this bit enables Upstream Ports to send LTR messages and Downstream Ports to process LTR Messages. For a Multi-Function Device associated with an Upstream Port of a device that implements LTR the bit.." "0,1" newline rbitfld.long 0x28 5. "PCIE_CAP_ARI_FORWARD_SUPPORT_CS,ARI Forwarding Enable. When set the Downstream Port disables its traditional Device Number field being 0 enforcement when turning a Type 1 Configuration Request into a Type 0 Configuration Request permitting access to.." "0,1" bitfld.long 0x28 4. "PCIE_CAP_CPL_TIMEOUT_DISABLE,Completion Timeout Disable. When set this bit disables the Completion Timeout mechanism. This bit is required for all Functions that support the Completion Timeout Disable Capability. Functions that do not support this.." "0,1" newline hexmask.long.byte 0x28 0.--3. 1. "PCIE_CAP_CPL_TIMEOUT_VALUE,Completion Timeout Value. In device Functions that support Completion Timeout programmability this field allows system software to modify the Completion Timeout value. This field is applicable to Root Ports Endpoints that.." line.long 0x2C "LINK_CAPABILITIES2_REG,Link Capabilities 2 Register." bitfld.long 0x2C 31. "DRS_SUPPORTED,DRS Supported. When set indicates support for the optional Device Readiness Status (DRS) capability. Must be Set in Downstream Ports that support DRS. Must be Set in Downstream Ports that support FRS. For Upstream Ports that support DRS.." "0,1" hexmask.long.byte 0x2C 25.--30. 1. "RSVDP_25,Reserved for future use." newline hexmask.long.word 0x2C 9.--22. 1. "RSVDP_9,Reserved for future use." rbitfld.long 0x2C 8. "PCIE_CAP_CROSS_LINK_SUPPORT,Crosslink Supported. When set to 1b this bit indicates that the associated Port supports crosslinks (for more details see section 4.2.6.3.1 of PCI Express Base Specification). When set to 0b on a Port that supports Link.." "0,1" newline hexmask.long.byte 0x2C 1.--7. 1. "PCIE_CAP_SUPPORT_LINK_SPEED_VECTOR,Supported Link Speeds Vector. This field indicates the supported Link speed(s) of the associated Port. For each bit a value of 1b indicates that the corresponding Link speed is supported; otherwise the Link speed is.." rbitfld.long 0x2C 0. "RSVDP_0,Reserved for future use." "0,1" line.long 0x30 "LINK_CONTROL2_LINK_STATUS2_REG,Link Control 2 and Status 2 Register." bitfld.long 0x30 31. "DRS_MESSAGE_RECEIVED,DRS Message Received. This bit must be set whenever the Port receives a DRS Message. This bit must be cleared in DL_Down. This bit must be implemented in any Downstream Port where the DRS Supported bit is Set in the Link Capabilities.." "0,1" rbitfld.long 0x30 28.--30. "DOWNSTREAM_COMPO_PRESENCE,Downstream Component Presence. This field indicates the presence and DRS status for the Downstream Component if any connected to the Link; defined values are: - 000b: Link Down - Presence Not Determined - 001b: Link Down -.." "0,1,2,3,4,5,6,7" newline rbitfld.long 0x30 26.--27. "RSVDP_26,Reserved for future use." "0,1,2,3" bitfld.long 0x30 21. "PCIE_CAP_LINK_EQ_REQ,Link Equalization Request 8.0 GT/s. This bit is set by hardware to request the 8.0 GT/s Link equalization process to be performed on the Link. For more details see sections 4.2.3 and 4.2.6.4.2 of PCI Express Base Specification. For.." "0,1" newline rbitfld.long 0x30 20. "PCIE_CAP_EQ_CPL_P3,EEqualization 8.0 GT/s Phase 3 Successful. When set to 1b this bit indicates that Phase 3 of the 8.0 GT/s Transmitter Equalization procedure has successfully completed. Details of the Transmitter Equalization process and when this bit.." "0,1" rbitfld.long 0x30 19. "PCIE_CAP_EQ_CPL_P2,Equalization 8.0 GT/s Phase 2 Successful. When set to 1b this bit indicates that Phase 2 of the 8.0 GT/s Transmitter Equalization procedure has successfully completed. Details of the Transmitter Equalization process and when this bit.." "0,1" newline rbitfld.long 0x30 18. "PCIE_CAP_EQ_CPL_P1,Equalization 8.0 GT/s Phase 1 Successful. When set to 1b this bit indicates that Phase 1 of the 8.0 GT/s Transmitter Equalization procedure has successfully completed. Details of the Transmitter Equalization process and when this bit.." "0,1" rbitfld.long 0x30 17. "PCIE_CAP_EQ_CPL,Equalization 8.0 GT/s Complete. When set to 1b this bit indicates that the Transmitter Equalization procedure at the 8.0 GT/s data rate has completed. Details of the Transmitter Equalization process and when this bit needs to be set to.." "0,1" newline rbitfld.long 0x30 16. "PCIE_CAP_CURR_DEEMPHASIS,Current De-emphasis Level. When the Link is operating at 5.0 GT/s speed this bit reflects the level of de-emphasis. Encodings: - 1b: -3.5 dB - 0b: -6 dB The value in this bit is undefined when the Link is not operating at 5.0.." "0,1" hexmask.long.byte 0x30 12.--15. 1. "PCIE_CAP_COMPLIANCE_PRESET,Compliance Preset/De-emphasis. For 8.0 GT/s and higher Data Rate: This field sets the Transmitter Preset in Polling.Compliance state if the entry occurred due to the Enter Compliance bit being 1b. The encodings are defined in.." newline bitfld.long 0x30 11. "PCIE_CAP_COMPLIANCE_SOS,Compliance SOS. When set to 1b the LTSSM is required to send SKP Ordered Sets between sequences when sending the Compliance Pattern or Modified Compliance Pattern. For a Multi-Function Device associated with an Upstream Port the.." "0,1" bitfld.long 0x30 10. "PCIE_CAP_ENTER_MODIFIED_COMPLIANCE,Enter Modified Compliance. When this bit is set to 1b the device transmits Modified Compliance Pattern if the LTSSM enters Polling.Compliance substate. Components that support only the 2.5 GT/s speed are permitted to.." "0,1" newline bitfld.long 0x30 7.--9. "PCIE_CAP_TX_MARGIN,Transmit Margin - This field controls the value of the non-deemphasized voltage level at the Transmitter pins. This field is reset to 000b on entry to the LTSSM Polling.Configuration substate (see Chapter 4 of PCI Express Base.." "0,1,2,3,4,5,6,7" bitfld.long 0x30 6. "PCIE_CAP_SEL_DEEMPHASIS,Selectable De-emphasis. When the Link is operating at 5.0 GT/s speed this bit is used to control the transmit de-emphasis of the link in specific situations. For more details see section 4.2.6 of PCI Express Base Specification." "0,1" newline bitfld.long 0x30 5. "PCIE_CAP_HW_AUTO_SPEED_DISABLE,Hardware Autonomous Speed Disable. When set this bit disables hardware from changing the Link speed for device-specific reasons other than attempting to correct unreliable Link operation by reducing Link speed. Initial.." "0,1" bitfld.long 0x30 4. "PCIE_CAP_ENTER_COMPLIANCE,Enter Compliance. Software is permitted to force a Link to enter Compliance mode (at the speed indicated in the Target Link Speed field and the de-emphasis/preset level indicated by the Compliance Preset/De-emphasis field) by.." "0,1" newline hexmask.long.byte 0x30 0.--3. 1. "PCIE_CAP_TARGET_LINK_SPEED,Target Link Speed. For Downstream Ports this field sets an upper limit on Link operational speed by restricting the values advertised by the Upstream component in its training sequences. The encoded value specifies a bit.." tree.end tree "PF0_AER_CAP (PF Advanced Error Reporting Capability Structure)" group.long (0x0+0x100)++0x1B line.long 0x0 "AER_EXT_CAP_HDR_OFF,Advanced Error Reporting Extended Capability Header. For a description of this standard PCIe register. see the PCI Express Specification." hexmask.long.word 0x0 20.--31. 1. "NEXT_OFFSET,Next Capability Offset. For a description of this standard PCIe register field see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky).." hexmask.long.byte 0x0 16.--19. 1. "CAP_VERSION,Capability Version. For a description of this standard PCIe register field see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else.." hexmask.long.word 0x0 0.--15. 1. "CAP_ID,AER Extended Capability ID. For a description of this standard PCIe register field see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else.." line.long 0x4 "UNCORR_ERR_STATUS_OFF,Uncorrectable Error Status Register. For a description of this standard PCIe register. see the PCI Express Specification." hexmask.long.byte 0x4 27.--31. 1. "RSVDP_27,Reserved for future use." bitfld.long 0x4 25. "TLP_PRFX_BLOCKED_ERR_STATUS,TLP Prefix Blocked Error Status. For a description of this standard PCIe register field see the PCI Express Specification. Note: Not supported." "0,1" rbitfld.long 0x4 23. "RSVDP_23,Reserved for future use." "0,1" newline bitfld.long 0x4 22. "INTERNAL_ERR_STATUS,Uncorrectable Internal Error Status. For a description of this standard PCIe register field see the PCI Express Specification. The controller sets this bit when your application asserts app_err_bus[9]. It does not set this bit when.." "0,1" bitfld.long 0x4 20. "UNSUPPORTED_REQ_ERR_STATUS,Unsupported Request Error Status. For a description of this standard PCIe register field see the PCI Express Specification." "0,1" bitfld.long 0x4 19. "ECRC_ERR_STATUS,ECRC Error Status. For a description of this standard PCIe register field see the PCI Express Specification. Note:If CX_ECRC_ENABLE=0 the register field always reads 0." "0,1" newline bitfld.long 0x4 18. "MALF_TLP_ERR_STATUS,Malformed TLP Status. For a description of this standard PCIe register field see the PCI Express Specification." "0,1" bitfld.long 0x4 17. "REC_OVERFLOW_ERR_STATUS,Receiver Overflow Status. For a description of this standard PCIe register field see the PCI Express Specification." "0,1" bitfld.long 0x4 16. "UNEXP_CMPLT_ERR_STATUS,Unexpected Completion Status. For a description of this standard PCIe register field see the PCI Express Specification." "0,1" newline bitfld.long 0x4 15. "CMPLT_ABORT_ERR_STATUS,Completer Abort Status. For a description of this standard PCIe register field see the PCI Express Specification." "0,1" bitfld.long 0x4 14. "CMPLT_TIMEOUT_ERR_STATUS,Completion Timeout Status. For a description of this standard PCIe register field see the PCI Express Specification." "0,1" bitfld.long 0x4 13. "FC_PROTOCOL_ERR_STATUS,Flow Control Protocol Error Status. For a description of this standard PCIe register field see the PCI Express Specification." "0,1" newline bitfld.long 0x4 12. "POIS_TLP_ERR_STATUS,Poisoned TLP Status. For a description of this standard PCIe register field see the PCI Express Specification." "0,1" hexmask.long.byte 0x4 6.--11. 1. "RSVDP_6,Reserved for future use." bitfld.long 0x4 5. "SURPRISE_DOWN_ERR_STATUS,Surprise Down Error Status (Optional). For a description of this standard PCIe register field see the PCI Express Specification." "0,1" newline bitfld.long 0x4 4. "DL_PROTOCOL_ERR_STATUS,Data Link Protocol Error Status. For a description of this standard PCIe register field see the PCI Express Specification." "0,1" hexmask.long.byte 0x4 0.--3. 1. "RSVDP_0,Reserved for future use." line.long 0x8 "UNCORR_ERR_MASK_OFF,Uncorrectable Error Mask Register. For a description of this standard PCIe register. see the PCI Express Specification." hexmask.long.byte 0x8 27.--31. 1. "RSVDP_27,Reserved for future use." bitfld.long 0x8 25. "TLP_PRFX_BLOCKED_ERR_MASK,TLP Prefix Blocked Error Mask. For a description of this standard PCIe register field see the PCI Express Specification. Note: Not supported. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi:.." "0,1" rbitfld.long 0x8 23. "RSVDP_23,Reserved for future use." "0,1" newline bitfld.long 0x8 22. "INTERNAL_ERR_MASK,Uncorrectable Internal Error Mask (Optional). For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." "0,1" rbitfld.long 0x8 21. "ACS_VIOLATION_MASK,ACS Violation Mask. Setting the ACS Violation Mask bit disables error logging and signaling for ACS Violation errors. The bit is Read-Only Zero for upstream ports when ACS P2P Egress Control Enable is not set. For a description of.." "0,1" bitfld.long 0x8 20. "UNSUPPORTED_REQ_ERR_MASK,Unsupported Request Error Mask. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." "0,1" newline bitfld.long 0x8 19. "ECRC_ERR_MASK,ECRC Error Mask (Optional). For a description of this standard PCIe register field see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W (sticky) Note: This register.." "0,1" bitfld.long 0x8 18. "MALF_TLP_ERR_MASK,Malformed TLP Mask. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." "0,1" bitfld.long 0x8 17. "REC_OVERFLOW_ERR_MASK,Receiver Overflow Mask (Optional). For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." "0,1" newline bitfld.long 0x8 16. "UNEXP_CMPLT_ERR_MASK,Unexpected Completion Mask. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." "0,1" bitfld.long 0x8 15. "CMPLT_ABORT_ERR_MASK,Completer Abort Error Mask (Optional). For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." "0,1" bitfld.long 0x8 14. "CMPLT_TIMEOUT_ERR_MASK,Completion Timeout Error Mask. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." "0,1" newline bitfld.long 0x8 13. "FC_PROTOCOL_ERR_MASK,Flow Control Protocol Error Mask. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." "0,1" bitfld.long 0x8 12. "POIS_TLP_ERR_MASK,Poisoned TLP Error Mask. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." "0,1" hexmask.long.byte 0x8 6.--11. 1. "RSVDP_6,Reserved for future use." newline rbitfld.long 0x8 5. "SURPRISE_DOWN_ERR_MASK,Surprise Down Error Mask. For a description of this standard PCIe register field see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi:.." "0,1" bitfld.long 0x8 4. "DL_PROTOCOL_ERR_MASK,Data Link Protocol Error Mask. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." "0,1" hexmask.long.byte 0x8 0.--3. 1. "RSVDP_0,Reserved for future use." line.long 0xC "UNCORR_ERR_SEV_OFF,Uncorrectable Error Severity Register. For a description of this standard PCIe register. see the PCI Express Specification." hexmask.long.byte 0xC 27.--31. 1. "RSVDP_27,Reserved for future use." bitfld.long 0xC 25. "TLP_PRFX_BLOCKED_ERR_SEVERITY,TLP Prefix Blocked Error Severity (Optional). For a description of this standard PCIe register field see the PCI Express Specification. Note: Not supported. Note: The access attributes of this field are as follows: - Wire:.." "0,1" rbitfld.long 0xC 24. "ATOMIC_EGRESS_BLOCKED_ERR_SEVERITY,AtomicOp Egress Blocked Severity (Optional). For a description of this standard PCIe register field see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi:.." "0,1" newline rbitfld.long 0xC 23. "RSVDP_23,Reserved for future use." "0,1" bitfld.long 0xC 22. "INTERNAL_ERR_SEVERITY,Uncorrectable Internal Error Severity (Optional). For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." "0,1" bitfld.long 0xC 20. "UNSUPPORTED_REQ_ERR_SEVERITY,Unsupported Request Error Severity. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." "0,1" newline bitfld.long 0xC 19. "ECRC_ERR_SEVERITY,ECRC Error Severity (Optional). For a description of this standard PCIe register field see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W (sticky) Note: This.." "0,1" bitfld.long 0xC 18. "MALF_TLP_ERR_SEVERITY,Malformed TLP Severity. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." "0,1" bitfld.long 0xC 17. "REC_OVERFLOW_ERR_SEVERITY,Receiver Overflow Error Severity (Optional). For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." "0,1" newline bitfld.long 0xC 16. "UNEXP_CMPLT_ERR_SEVERITY,Unexpected Completion Error Severity. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." "0,1" bitfld.long 0xC 15. "CMPLT_ABORT_ERR_SEVERITY,Completer Abort Error Severity (Optional). For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." "0,1" bitfld.long 0xC 14. "CMPLT_TIMEOUT_ERR_SEVERITY,Completion Timeout Error Severity. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." "0,1" newline bitfld.long 0xC 13. "FC_PROTOCOL_ERR_SEVERITY,Flow Control Protocol Error Severity (Optional). For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." "0,1" bitfld.long 0xC 12. "POIS_TLP_ERR_SEVERITY,Poisoned TLP Severity. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." "0,1" hexmask.long.byte 0xC 6.--11. 1. "RSVDP_6,Reserved for future use." newline rbitfld.long 0xC 5. "SURPRISE_DOWN_ERR_SVRITY,Surprise Down Error Severity (Optional). For a description of this standard PCIe register field see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi:.." "0,1" bitfld.long 0xC 4. "DL_PROTOCOL_ERR_SEVERITY,Data Link Protocol Error Severity. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." "0,1" hexmask.long.byte 0xC 0.--3. 1. "RSVDP_0,Reserved for future use." line.long 0x10 "CORR_ERR_STATUS_OFF,Correctable Error Status Register. For a description of this standard PCIe register. see the PCI Express Specification." hexmask.long.word 0x10 16.--31. 1. "RSVDP_16,Reserved for future use." bitfld.long 0x10 15. "HEADER_LOG_OVERFLOW_STATUS,Header Log Overflow Error Status (Optional). For a description of this standard PCIe register field see the PCI Express Specification." "0,1" bitfld.long 0x10 14. "CORRECTED_INT_ERR_STATUS,Corrected Internal Error Status (Optional). For a description of this standard PCIe register field see the PCI Express Specification." "0,1" newline bitfld.long 0x10 13. "ADVISORY_NON_FATAL_ERR_STATUS,Advisory Non-Fatal Error Status. For a description of this standard PCIe register field see the PCI Express Specification." "0,1" bitfld.long 0x10 12. "RPL_TIMER_TIMEOUT_STATUS,Replay Timer Timeout Status. For a description of this standard PCIe register field see the PCI Express Specification." "0,1" rbitfld.long 0x10 9.--11. "RSVDP_9,Reserved for future use." "0,1,2,3,4,5,6,7" newline bitfld.long 0x10 8. "REPLAY_NO_ROLEOVER_STATUS,REPLAY_NUM Rollover Status. For a description of this standard PCIe register field see the PCI Express Specification." "0,1" bitfld.long 0x10 7. "BAD_DLLP_STATUS,Bad DLLP Status. For a description of this standard PCIe register field see the PCI Express Specification." "0,1" bitfld.long 0x10 6. "BAD_TLP_STATUS,Bad TLP Status. For a description of this standard PCIe register field see the PCI Express Specification." "0,1" newline hexmask.long.byte 0x10 1.--5. 1. "RSVDP_1,Reserved for future use." bitfld.long 0x10 0. "RX_ERR_STATUS,Receiver Error Status (Optional). For a description of this standard PCIe register field see the PCI Express Specification." "0,1" line.long 0x14 "CORR_ERR_MASK_OFF,Correctable Error Mask Register. For a description of this standard PCIe register. see the PCI Express Specification." hexmask.long.word 0x14 16.--31. 1. "RSVDP_16,Reserved for future use." bitfld.long 0x14 15. "HEADER_LOG_OVERFLOW_MASK,Header Log Overflow Error Mask (Optional). For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." "0,1" bitfld.long 0x14 14. "CORRECTED_INT_ERR_MASK,Corrected Internal Error Mask (Optional). For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." "0,1" newline bitfld.long 0x14 13. "ADVISORY_NON_FATAL_ERR_MASK,Advisory Non-Fatal Error Mask. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." "0,1" bitfld.long 0x14 12. "RPL_TIMER_TIMEOUT_MASK,Replay Timer Timeout Mask. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." "0,1" rbitfld.long 0x14 9.--11. "RSVDP_9,Reserved for future use." "0,1,2,3,4,5,6,7" newline bitfld.long 0x14 8. "REPLAY_NO_ROLEOVER_MASK,REPLAY_NUM Rollover Mask. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." "0,1" bitfld.long 0x14 7. "BAD_DLLP_MASK,Bad DLLP Mask. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." "0,1" bitfld.long 0x14 6. "BAD_TLP_MASK,Bad TLP Mask. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." "0,1" newline hexmask.long.byte 0x14 1.--5. 1. "RSVDP_1,Reserved for future use." bitfld.long 0x14 0. "RX_ERR_MASK,Receiver Error Mask (Optional). For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." "0,1" line.long 0x18 "ADV_ERR_CAP_CTRL_OFF,Advanced Error Capabilities and Control Register. For a description of this standard PCIe register. see the PCI Express Specification." hexmask.long.tbyte 0x18 13.--31. 1. "RSVDP_13,Reserved for future use." rbitfld.long 0x18 12. "CTO_PRFX_HDR_LOG_CAP,TLP Prefix Log Present. For a description of this standard PCIe register field see the PCI Express Specification." "0,1" rbitfld.long 0x18 11. "TLP_PRFX_LOG_PRESENT,Completion Timeout Prefix/Header Log Capable. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." "0,1" newline rbitfld.long 0x18 10. "MULTIPLE_HEADER_EN,Multiple Header Recording Enable. For a description of this standard PCIe register field see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R (sticky) Note: This.." "0,1" rbitfld.long 0x18 9. "MULTIPLE_HEADER_CAP,Multiple Header Recording Capable. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." "0,1" bitfld.long 0x18 8. "ECRC_CHECK_EN,ECRC Check Enable. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." "0,1" newline rbitfld.long 0x18 7. "ECRC_CHECK_CAP,ECRC Check Capable. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." "0,1" bitfld.long 0x18 6. "ECRC_GEN_EN,ECRC Generation Enable. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." "0,1" rbitfld.long 0x18 5. "ECRC_GEN_CAP,ECRC Generation Capable. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." "0,1" newline hexmask.long.byte 0x18 0.--4. 1. "FIRST_ERR_POINTER,First Error Pointer. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." rgroup.long (0x1C+0x100)++0xF line.long 0x0 "HDR_LOG_0_OFF,Header Log Register 0. For a description of this standard PCIe register. see the PCI Express Specification." hexmask.long.byte 0x0 24.--31. 1. "FIRST_DWORD_FOURTH_BYTE,Byte 3 of Header log register of First 32 bit Data Word. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." hexmask.long.byte 0x0 16.--23. 1. "FIRST_DWORD_THIRD_BYTE,Byte 2 of Header log register of First 32 bit Data Word. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." hexmask.long.byte 0x0 8.--15. 1. "FIRST_DWORD_SECOND_BYTE,Byte 1 of Header log register of First 32 bit Data Word. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." newline hexmask.long.byte 0x0 0.--7. 1. "FIRST_DWORD_FIRST_BYTE,Byte 0 of Header log register of First 32 bit Data Word. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." line.long 0x4 "HDR_LOG_1_OFF,Header Log Register 1. For a description of this standard PCIe register. see the PCI Express Specification." hexmask.long.byte 0x4 24.--31. 1. "SECOND_DWORD_FOURTH_BYTE,Byte 3 of Header log register of Second 32 bit Data Word. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." hexmask.long.byte 0x4 16.--23. 1. "SECOND_DWORD_THIRD_BYTE,Byte 2 of Header log register of Second 32 bit Data Word. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." hexmask.long.byte 0x4 8.--15. 1. "SECOND_DWORD_SECOND_BYTE,Byte 1 of Header log register of Second 32 bit Data Word. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." newline hexmask.long.byte 0x4 0.--7. 1. "SECOND_DWORD_FIRST_BYTE,Byte 0 of Header log register of Second 32 bit Data Word. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." line.long 0x8 "HDR_LOG_2_OFF,Header Log Register 2. For a description of this standard PCIe register. see the PCI Express Specification." hexmask.long.byte 0x8 24.--31. 1. "THIRD_DWORD_FOURTH_BYTE,Byte 3 of Header log register of Third 32 bit Data Word. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." hexmask.long.byte 0x8 16.--23. 1. "THIRD_DWORD_THIRD_BYTE,Byte 2 of Header log register of Third 32 bit Data Word. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." hexmask.long.byte 0x8 8.--15. 1. "THIRD_DWORD_SECOND_BYTE,Byte 1 of Header log register of Third 32 bit Data Word. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." newline hexmask.long.byte 0x8 0.--7. 1. "THIRD_DWORD_FIRST_BYTE,Byte 0 of Header log register of Third 32 bit Data Word. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." line.long 0xC "HDR_LOG_3_OFF,Header Log Register 3. For a description of this standard PCIe register. see the PCI Express Specification." hexmask.long.byte 0xC 24.--31. 1. "FOURTH_DWORD_FOURTH_BYTE,Byte 3 of Header log register of Fourth 32 bit Data Word. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." hexmask.long.byte 0xC 16.--23. 1. "FOURTH_DWORD_THIRD_BYTE,Byte 2 of Header log register of Fourth 32 bit Data Word. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." hexmask.long.byte 0xC 8.--15. 1. "FOURTH_DWORD_SECOND_BYTE,Byte 1 of Header log register of Fourth 32 bit Data Word. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." newline hexmask.long.byte 0xC 0.--7. 1. "FOURTH_DWORD_FIRST_BYTE,Byte 0 of Header log register of Fourth 32 bit Data Word. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." group.long (0x2C+0x100)++0x7 line.long 0x0 "ROOT_ERR_CMD_OFF,Root Error Command Register. For a description of this standard PCIe register. see the PCI Express Specification." hexmask.long 0x0 3.--31. 1. "RSVDP_3,Reserved for future use." bitfld.long 0x0 2. "FATAL_ERR_REPORTING_EN,Fatal Error Reporting Enable. For a description of this standard PCIe register field see the PCI Express Specification." "0,1" bitfld.long 0x0 1. "NON_FATAL_ERR_REPORTING_EN,Non-Fatal Error Reporting Enable. For a description of this standard PCIe register field see the PCI Express Specification." "0,1" newline bitfld.long 0x0 0. "CORR_ERR_REPORTING_EN,Correctable Error Reporting Enable. For a description of this standard PCIe register field see the PCI Express Specification." "0,1" line.long 0x4 "ROOT_ERR_STATUS_OFF,Root Error Status Register. For a description of this standard PCIe register. see the PCI Express Specification." hexmask.long.byte 0x4 27.--31. 1. "ADV_ERR_INT_MSG_NUM,Advanced Error Interrupt Message Number. For a description of this standard PCIe register field see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN.." hexmask.long.tbyte 0x4 7.--26. 1. "RSVDP_7,Reserved for future use." bitfld.long 0x4 6. "FATAL_ERR_MSG_RX,One or more Fatal Error Messages Received. For a description of this standard PCIe register field see the PCI Express Specification." "0,1" newline bitfld.long 0x4 5. "NON_FATAL_ERR_MSG_RX,One or more Non-Fatal Error Messages Received. For a description of this standard PCIe register field see the PCI Express Specification." "0,1" bitfld.long 0x4 4. "FIRST_UNCORR_FATAL,First Uncorrectable Error is Fatal. For a description of this standard PCIe register field see the PCI Express Specification." "0,1" bitfld.long 0x4 3. "MUL_ERR_FATAL_NON_FATAL_RX,Multiple Fatal or Non-Fatal Errors Received. For a description of this standard PCIe register field see the PCI Express Specification." "0,1" newline bitfld.long 0x4 2. "ERR_FATAL_NON_FATAL_RX,Fatal or Non-Fatal Error Received. For a description of this standard PCIe register field see the PCI Express Specification." "0,1" bitfld.long 0x4 1. "MUL_ERR_COR_RX,Multiple Correctable Errors Received. For a description of this standard PCIe register field see the PCI Express Specification." "0,1" bitfld.long 0x4 0. "ERR_COR_RX,Correctable Error Received. For a description of this standard PCIe register field see the PCI Express Specification." "0,1" rgroup.long (0x34+0x100)++0x13 line.long 0x0 "ERR_SRC_ID_OFF,Error Source Identification Register. For a description of this standard PCIe register. see the PCI Express Specification." hexmask.long.word 0x0 16.--31. 1. "ERR_FATAL_NON_FATAL_SOURCE_ID,Source of Fatal/Non-Fatal Error. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." hexmask.long.word 0x0 0.--15. 1. "ERR_COR_SOURCE_ID,Source of Correctable Error. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." line.long 0x4 "TLP_PREFIX_LOG_1_OFF,TLP Prefix Log Register 1. For a description of this standard PCIe register. see the PCI Express Specification." hexmask.long.byte 0x4 24.--31. 1. "CFG_TLP_PFX_LOG_1_FOURTH_BYTE,Byte 3 of Error TLP Prefix Log 1. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." hexmask.long.byte 0x4 16.--23. 1. "CFG_TLP_PFX_LOG_1_THIRD_BYTE,Byte 2 of Error TLP Prefix Log 1. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." hexmask.long.byte 0x4 8.--15. 1. "CFG_TLP_PFX_LOG_1_SECOND_BYTE,Byte 1 of Error TLP Prefix Log 1. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." newline hexmask.long.byte 0x4 0.--7. 1. "CFG_TLP_PFX_LOG_1_FIRST_BYTE,Byte 0 of Error TLP Prefix Log 1. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." line.long 0x8 "TLP_PREFIX_LOG_2_OFF,TLP Prefix Log Register 2. For a description of this standard PCIe register. see the PCI Express Specification." hexmask.long.byte 0x8 24.--31. 1. "CFG_TLP_PFX_LOG_2_FOURTH_BYTE,Byte 3 Error TLP Prefix Log 2. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." hexmask.long.byte 0x8 16.--23. 1. "CFG_TLP_PFX_LOG_2_THIRD_BYTE,Byte 2 Error TLP Prefix Log 2. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." hexmask.long.byte 0x8 8.--15. 1. "CFG_TLP_PFX_LOG_2_SECOND_BYTE,Byte 1 Error TLP Prefix Log 2. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." newline hexmask.long.byte 0x8 0.--7. 1. "CFG_TLP_PFX_LOG_2_FIRST_BYTE,Byte 0 Error TLP Prefix Log 2. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." line.long 0xC "TLP_PREFIX_LOG_3_OFF,TLP Prefix Log Register 3. For a description of this standard PCIe register. see the PCI Express Specification." hexmask.long.byte 0xC 24.--31. 1. "CFG_TLP_PFX_LOG_3_FOURTH_BYTE,Byte 3 Error TLP Prefix Log 3. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." hexmask.long.byte 0xC 16.--23. 1. "CFG_TLP_PFX_LOG_3_THIRD_BYTE,Byte 2 Error TLP Prefix Log 3. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." hexmask.long.byte 0xC 8.--15. 1. "CFG_TLP_PFX_LOG_3_SECOND_BYTE,Byte 1 Error TLP Prefix Log 3. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." newline hexmask.long.byte 0xC 0.--7. 1. "CFG_TLP_PFX_LOG_3_FIRST_BYTE,Byte 0 Error TLP Prefix Log 3. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." line.long 0x10 "TLP_PREFIX_LOG_4_OFF,TLP Prefix Log Register 4. For a description of this standard PCIe register. see the PCI Express Specification." hexmask.long.byte 0x10 24.--31. 1. "CFG_TLP_PFX_LOG_4_FOURTH_BYTE,Byte 3 Error TLP Prefix Log 4. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." hexmask.long.byte 0x10 16.--23. 1. "CFG_TLP_PFX_LOG_4_THIRD_BYTE,Byte 2 Error TLP Prefix Log 4. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." hexmask.long.byte 0x10 8.--15. 1. "CFG_TLP_PFX_LOG_4_SECOND_BYTE,Byte 1 Error TLP Prefix Log 4. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." newline hexmask.long.byte 0x10 0.--7. 1. "CFG_TLP_PFX_LOG_4_FIRST_BYTE,Byte 0 Error TLP Prefix Log 4. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." tree.end tree "PF0_MSI_CAP (PF MSI Capability Structure)" group.long (0x0+0x50)++0x13 line.long 0x0 "PCI_MSI_CAP_ID_NEXT_CTRL_REG,MSI Capability Header and Message Control Register." hexmask.long.byte 0x0 27.--31. 1. "RSVDP_27,Reserved for future use." bitfld.long 0x0 26. "PCI_MSI_EXT_DATA_EN,Extended Message Data Enable. - If set the function is enabled to provide Extended Message Data. - If clear the function is not enabled to provide Extended Message Data. Note: The access attributes of this field are as follows: -.." "0,1" bitfld.long 0x0 25. "PCI_MSI_EXT_DATA_CAP,Extended Message Data Capable. - If set the function is capable of providing Extended Message Data. - If clear the function does not support providing Extended Message Data. Note: The access attributes of this field are as follows:.." "0,1" newline rbitfld.long 0x0 24. "PCI_PVM_SUPPORT,Per-Vector Masking Capable. - If set the function supports MSI Per-Vector Masking. - If clear the function does not support MSI Per-Vector Masking. This bit must be set if the function is a PF or VF within an SR-IOV Device." "0,1" bitfld.long 0x0 23. "PCI_MSI_64_BIT_ADDR_CAP,64 bit address capable. - If set the function is capable of sending a 64-bit message address. - If clear the function is not capable of sending a 64-bit message address. This bit must be set if the function is a PCI Express.." "0,1" bitfld.long 0x0 20.--22. "PCI_MSI_MULTIPLE_MSG_EN,Multiple Message Enable. Software writes to this field to indicate the number of allocated vectors (equal to or less than the number of requested vectors). The number of allocated vectors is aligned to a power of two. If a.." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 17.--19. "PCI_MSI_MULTIPLE_MSG_CAP,Multiple Message Capable. System software reads this field to determine the number of requested vectors. The number of requested vectors must be aligned to a power of two (if a function requires three vectors it requests four by.." "0,1,2,3,4,5,6,7" bitfld.long 0x0 16. "PCI_MSI_ENABLE,MSI Enable. - If set and the MSI-X Enable bit in the MSI-X Message Control register is clear the function is permitted to use MSI to request service and is prohibited from using INTx interrupts. System configuration software sets this bit.." "0,1" hexmask.long.byte 0x0 8.--15. 1. "PCI_MSI_CAP_NEXT_OFFSET,Next Capability Pointer. This field contains the offset to the next PCI Capability structure or 00h if no other items exist in the linked list of Capabilities. Note: The access attributes of this field are as follows: - Wire: No.." newline hexmask.long.byte 0x0 0.--7. 1. "PCI_MSI_CAP_ID,Capability ID. Indicates the MSI Capability structure. This field returns a Capability ID of 05h indicating that this is an MSI Capability structure." line.long 0x4 "MSI_CAP_OFF_04H_REG,Message Address Register for MSI (Offset 04h)." hexmask.long 0x4 2.--31. 1. "PCI_MSI_CAP_OFF_04H,Message Address - System-specified message address. If the Message Enable bit (bit 16 of the PCI_MSI_CAP_ID_NEXT_CTRL_REG register) is set the contents of this field specify the DWORD-aligned address (Address[31:02]) for the MSI.." rbitfld.long 0x4 0.--1. "RSVDP_0,Reserved for future use." "0,1,2,3" line.long 0x8 "MSI_CAP_OFF_08H_REG,For a function that supports a 32-bit message address. - bits[31:16] of this register represent the Extended Message Data. and - bits[15:0] of this register represent the Message Data For a function that supports a 64-bit message.." hexmask.long.word 0x8 16.--31. 1. "PCI_MSI_CAP_OFF_0AH,For a function that supports a 32-bit message address this field contains Extended Message Data (System-specified message data). For the MSI Capability structures without per-vector masking it must be implemented if the Extended.." hexmask.long.word 0x8 0.--15. 1. "PCI_MSI_CAP_OFF_08H,For a function that supports a 32-bit message address this field contains Message Data (System-specified message data). If the Message Enable bit (bit 16 of the PCI_MSI_CAP_ID_NEXT_CTRL_REG) is set the function sends a DWORD Memory.." line.long 0xC "MSI_CAP_OFF_0CH_REG,For a function that supports a 32-bit message address. this register contains the Mask Bits when the Per-Vector Masking Capable bit (bit 24 of PCI_MSI_CAP_ID_NEXT_CTRL_REG) is set. For a function that supports a 64-bit message.." hexmask.long.word 0xC 16.--31. 1. "PCI_MSI_CAP_OFF_0EH,For a function that supports a 32-bit message address this field contains the upper Mask Bits when the Per Vector Masking Capable bit (PCI_MSI_CAP_ID_NEXT_CTRL_REG.PCI_PVM_SUPPORT) is set. For a function that supports a 64-bit.." hexmask.long.word 0xC 0.--15. 1. "PCI_MSI_CAP_OFF_0CH,For a function that supports a 32-bit message address this field contains the lower Mask Bits when the Per Vector Masking Capable bit (PCI_MSI_CAP_ID_NEXT_CTRL_REG.PCI_PVM_SUPPORT) is set. For a function that supports a 64-bit.." line.long 0x10 "MSI_CAP_OFF_10H_REG,For a function that supports a 32-bit message address. this register contains the Pending Bits when the Per-Vector Masking Capable bit (bit 24 of PCI_MSI_CAP_ID_NEXT_CTRL_REG) is set. For a function that supports a 64-bit message.." hexmask.long 0x10 0.--31. 1. "PCI_MSI_CAP_OFF_10H,Used for MSI when the Per Vector Masking Capable bit (PCI_MSI_CAP_ID_NEXT_CTRL_REG.PCI_PVM_SUPPORT) is set. For 32-bit contains Pending Bits. For 64-bit contains Mask Bits. For a description of this standard PCIe register field see.." rgroup.long (0x14+0x50)++0x3 line.long 0x0 "MSI_CAP_OFF_14H_REG,Pending Bits Register for MSI. This register is used for a function that supports a 64-bit message address when the Per-Vector Masking Capable bit (bit 24 of PCI_MSI_CAP_ID_NEXT_CTRL_REG) is set." hexmask.long 0x0 0.--31. 1. "PCI_MSI_CAP_OFF_14H,Pending Bits. For each pending bit that is set the function has a pending associated message." tree.end tree "PF0_MSIX_CAP (PF MSI-X Capability Structure)" group.long (0x0+0xB0)++0xB line.long 0x0 "PCI_MSIX_CAP_ID_NEXT_CTRL_REG,MSI-X Capability ID. Next Pointer. Control Registers. For a description of this standard PCIe register. see the PCI Express Base Specification." bitfld.long 0x0 31. "PCI_MSIX_ENABLE,MSI-X Enable. For a description of this standard PCIe register field see the PCI Express Base Specification." "0,1" bitfld.long 0x0 30. "PCI_MSIX_FUNCTION_MASK,Function Mask. For a description of this standard PCIe register field see the PCI Express Base Specification. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" "0,1" rbitfld.long 0x0 27.--29. "RSVDP_27,Reserved for future use." "0,1,2,3,4,5,6,7" newline hexmask.long.word 0x0 16.--26. 1. "PCI_MSIX_TABLE_SIZE,MSI-X Table Size. For a description of this standard PCIe register field see the PCI Express Base Specification. SRIOV Note: All VFs in a single PF have the same value for 'MSI-X Table Size' (PCI_MSIX_TABLE_SIZE field in.." hexmask.long.byte 0x0 8.--15. 1. "PCI_MSIX_CAP_NEXT_OFFSET,MSI-X Next Capability Pointer. For a description of this standard PCIe register field see the PCI Express Base Specification. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN.." hexmask.long.byte 0x0 0.--7. 1. "PCI_MSIX_CAP_ID,MSI-X Capability ID. For a description of this standard PCIe register field see the PCI Express Base Specification." line.long 0x4 "MSIX_TABLE_OFFSET_REG,MSI-X Table Offset and BIR Register. For a description of this standard PCIe register. see the PCI Express Base Specification." hexmask.long 0x4 3.--31. 1. "PCI_MSIX_TABLE_OFFSET,MSI-X Table Offset. For a description of this standard PCIe register field see the PCI Express Base Specification. SRIOV Note: All VFs in a single PF have the same value for 'MSI-X Table Offset' (PCI_MSIX_TABLE_OFFSET field in.." bitfld.long 0x4 0.--2. "PCI_MSIX_BIR,MSI-X Table BAR Indicator Register Field. For a description of this standard PCIe register field see the PCI Express Base Specification. SRIOV Note: All VFs in a single PF have the same value for 'MSI-X Table BAR Indicator Register'.." "0,1,2,3,4,5,6,7" line.long 0x8 "MSIX_PBA_OFFSET_REG,MSI-X PBA Offset and BIR Register. For a description of this standard PCIe register. see the PCI Express Base Specification." hexmask.long 0x8 3.--31. 1. "PCI_MSIX_PBA_OFFSET,MSI-X PBA Offset. For a description of this standard PCIe register field see the PCI Express Base Specification. SRIOV Note: All VFs in a single PF have the same value for 'MSI-X PBA Offset' (PCI_MSIX_PBA_OFFSET field in.." bitfld.long 0x8 0.--2. "PCI_MSIX_PBA_BIR,MSI-X PBA BIR. For a description of this standard PCIe register field see the PCI Express Base Specification. SRIOV Note: All VFs in a single PF have the same value for 'MSI-X PBA BIR' (PCI_MSIX_PBA_BIR field in.." "0,1,2,3,4,5,6,7" tree.end tree "PF0_MSIX_CAP_DBI2 (DBI2 Shadow Block: PF MSI-X Capability Structure)" rgroup.long (0x0+0x10B0)++0x3 line.long 0x0 "SHADOW_PCI_MSIX_CAP_ID_NEXT_CTRL_REG,MSI-X Capability ID. Next Pointer. Control Registers. For a description of this standard PCIe register. see the PCI Express Base Specification." hexmask.long.byte 0x0 27.--31. 1. "RSVDP_27,Reserved for future use." hexmask.long.word 0x0 16.--26. 1. "PCI_MSIX_TABLE_SIZE,MSI-X Table Size in the shadow register. Note: The access attributes of this field are as follows: - Wire: No access - Dbi: No access - Dbi2: if (DBI_RO_WR_EN == 1) then R/W else R Note: This register field is sticky." hexmask.long.word 0x0 0.--15. 1. "RSVDP_0,Reserved for future use." group.long 0x4++0x7 line.long 0x0 "SHADOW_MSIX_TABLE_OFFSET_REG,MSI-X Table Offset and BIR Register. For a description of this standard PCIe register. see the PCI Express Base Specification." hexmask.long 0x0 3.--31. 1. "PCI_MSIX_TABLE_OFFSET,MSI-X Table Offset. For a description of this standard PCIe register field see the PCI Express Base Specification. Note: The access attributes of this field are as follows: - Wire: No access - Dbi: No access - Dbi2: if.." bitfld.long 0x0 0.--2. "PCI_MSIX_BIR,MSI-X Table BAR Indicator Register Field. For a description of this standard PCIe register field see the PCI Express Base Specification. Note: The access attributes of this field are as follows: - Wire: No access - Dbi: No access - Dbi2: if.." "?,?,if,?,?,?,?,?" line.long 0x4 "SHADOW_MSIX_PBA_OFFSET_REG,MSI-X PBA Offset and BIR Register. For a description of this standard PCIe register. see the PCI Express Base Specification." hexmask.long 0x4 3.--31. 1. "PCI_MSIX_PBA_OFFSET,MSI-X PBA Offset. For a description of this standard PCIe register field see the PCI Express Base Specification. Note: The access attributes of this field are as follows: - Wire: No access - Dbi: No access - Dbi2: if (DBI_RO_WR_EN ==.." bitfld.long 0x4 0.--2. "PCI_MSIX_PBA_BIR,MSI-X PBA BIR. For a description of this standard PCIe register field see the PCI Express Base Specification. Note: The access attributes of this field are as follows: - Wire: No access - Dbi: No access - Dbi2: if (DBI_RO_WR_EN == 1 &&.." "?,?,if,?,?,?,?,?" tree.end tree "PF0_DMA_CAP (DMA Port Logic Structure)" group.long (0x0+0xC8000)++0x3 line.long 0x0 "DMA_CTRL_DATA_ARB_PRIOR_OFF,DMA Arbitration Scheme for TRGT1 Interface. This register is used to control traffic priorities among various sources that are delivered to your application through TRGT1 where 0x0 represents the highest priority. - Non-DMA Rx.." hexmask.long.tbyte 0x0 12.--31. 1. "RSVDP_12,Reserved for future use." bitfld.long 0x0 9.--11. "RDBUFF_TRGT_WEIGHT,DMA Read Channel MWr Requests. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 6.--8. "RD_CTRL_TRGT_WEIGHT,DMA Read Channel MRd Requests. For LL element/descriptor access. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" "0,1,2,3,4,5,6,7" bitfld.long 0x0 3.--5. "WR_CTRL_TRGT_WEIGHT,DMA Write Channel MRd Requests. For DMA data requests and LL element/descriptor access. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 0.--2. "RTRGT1_WEIGHT,Non-DMA Rx Requests. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" "0,1,2,3,4,5,6,7" group.long (0x8+0xC8000)++0xB line.long 0x0 "DMA_CTRL_OFF,DMA Number of Channels Register." hexmask.long.byte 0x0 26.--31. 1. "RSVDP_26,Reserved for future use." bitfld.long 0x0 25. "DIS_C2W_CACHE_RD,Disable DMA Read Channels 'completion to memory write' context cache pre-fetch function. Note: For internal debugging only. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" "0,1" newline bitfld.long 0x0 24. "DIS_C2W_CACHE_WR,Disable DMA Write Channels 'completion to memory write' context cache pre-fetch function. Note: For internal debugging only. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" "0,1" hexmask.long.byte 0x0 20.--23. 1. "RSVDP_20,Reserved for future use." newline hexmask.long.byte 0x0 16.--19. 1. "NUM_DMA_RD_CHAN,Number of Read Channels. You can read this register to determine the number of read channels the DMA controller has been configured to support." hexmask.long.word 0x0 4.--15. 1. "RSVDP_4,Reserved for future use." newline hexmask.long.byte 0x0 0.--3. 1. "NUM_DMA_WR_CHAN,Number of Write Channels. You can read this register to determine the number of write channels the DMA controller has been configured to support." line.long 0x4 "DMA_WRITE_ENGINE_EN_OFF,DMA Write Engine Enable Register." hexmask.long.byte 0x4 24.--31. 1. "RSVDP_24,Reserved for future use." bitfld.long 0x4 23. "DMA_WRITE_ENGINE_EN_HSHAKE_CH7,Enable Handshake for DMA Write Engine Channel 7. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" "0,1" newline bitfld.long 0x4 22. "DMA_WRITE_ENGINE_EN_HSHAKE_CH6,Enable Handshake for DMA Write Engine Channel 6. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" "0,1" bitfld.long 0x4 21. "DMA_WRITE_ENGINE_EN_HSHAKE_CH5,Enable Handshake for DMA Write Engine Channel 5. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" "0,1" newline bitfld.long 0x4 20. "DMA_WRITE_ENGINE_EN_HSHAKE_CH4,Enable Handshake for DMA Write Engine Channel 4. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" "0,1" bitfld.long 0x4 19. "DMA_WRITE_ENGINE_EN_HSHAKE_CH3,Enable Handshake for DMA Write Engine Channel 3. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" "0,1" newline bitfld.long 0x4 18. "DMA_WRITE_ENGINE_EN_HSHAKE_CH2,Enable Handshake for DMA Write Engine Channel 2. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" "0,1" bitfld.long 0x4 17. "DMA_WRITE_ENGINE_EN_HSHAKE_CH1,Enable Handshake for DMA Write Engine Channel 1. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" "0,1" newline bitfld.long 0x4 16. "DMA_WRITE_ENGINE_EN_HSHAKE_CH0,Enable Handshake for DMA Write Engine Channel 0. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" "0,1" hexmask.long.word 0x4 1.--15. 1. "RSVDP_1,Reserved for future use." newline bitfld.long 0x4 0. "DMA_WRITE_ENGINE,DMA Write Engine Enable. - 1: Enable - 0: Disable (Soft Reset) For normal operation you must initially set this bit to '1' before any other software setup actions. You do not need to toggle or rewrite to this bit during normal.." "Disable,Enable" line.long 0x8 "DMA_WRITE_DOORBELL_OFF,DMA Write Doorbell Register." bitfld.long 0x8 31. "WR_STOP,Stop. Set in conjunction with the Doorbell Number field. The DMA write channel stops issuing requests sets the channel status to 'Stopped' and asserts the 'Abort' interrupt if it is enabled. Before setting the Stop bit you must read the.." "0,1" hexmask.long 0x8 3.--30. 1. "RSVDP_3,Reserved for future use." newline bitfld.long 0x8 0.--2. "WR_DOORBELL_NUM,Doorbell Number. You must write the channel number to this register to start the DMA write transfer for that channel. The DMA detects a write to this register field even if the value of this field does not change. You do not need to.." "0,1,2,3,4,5,6,7" group.long (0x18+0xC8000)++0x7 line.long 0x0 "DMA_WRITE_CHANNEL_ARB_WEIGHT_LOW_OFF,DMA Write Engine Channel Arbitration Weight Low Register. The 5-bit channel weight (for write channels 0-3) specifies the maximum number of TLP requests that the DMA can issue for that channel before it must return to.." hexmask.long.word 0x0 20.--31. 1. "RSVDP_20,Reserved for future use." hexmask.long.byte 0x0 15.--19. 1. "WRITE_CHANNEL3_WEIGHT,Channel 3 Weight. The weight is initialized by software before ringing the doorbell. The value is used by the channel weighted round robin arbiter to select the next channel read request. A value of '0' means that one TLP is issued.." newline hexmask.long.byte 0x0 10.--14. 1. "WRITE_CHANNEL2_WEIGHT,Channel 2 Weight. The weight is initialized by software before ringing the doorbell. The value is used by the channel weighted round robin arbiter to select the next channel read request. A value of '0' means that one TLP is issued.." hexmask.long.byte 0x0 5.--9. 1. "WRITE_CHANNEL1_WEIGHT,Channel 1 Weight. The weight is initialized by software before ringing the doorbell. The value is used by the channel weighted round robin arbiter to select the next channel read request. A value of '0' means that one TLP is issued.." newline hexmask.long.byte 0x0 0.--4. 1. "WRITE_CHANNEL0_WEIGHT,Channel 0 Weight. The weight is initialized by software before ringing the doorbell. The value is used by the channel weighted round robin arbiter to select the next channel read request. A value of '0' means that one TLP is issued.." line.long 0x4 "DMA_WRITE_CHANNEL_ARB_WEIGHT_HIGH_OFF,DMA Write Engine Channel Arbitration Weight High Register. The 5-bit channel weight (for write channels 4-7) specifies the maximum number of TLP requests that the DMA can issue for that channel before it must return.." hexmask.long.word 0x4 20.--31. 1. "RSVDP_20,Reserved for future use." hexmask.long.byte 0x4 15.--19. 1. "WRITE_CHANNEL7_WEIGHT,Channel 7 Weight. The weight is initialized by software before ringing the doorbell. The value is used by the channel weighted round robin arbiter to select the next channel read request. A value of '0' means that one TLP is issued.." newline hexmask.long.byte 0x4 10.--14. 1. "WRITE_CHANNEL6_WEIGHT,Channel 6 Weight. The weight is initialized by software before ringing the doorbell. The value is used by the channel weighted round robin arbiter to select the next channel read request. A value of '0' means that one TLP is issued.." hexmask.long.byte 0x4 5.--9. 1. "WRITE_CHANNEL5_WEIGHT,Channel 5 Weight. The weight is initialized by software before ringing the doorbell. The value is used by the channel weighted round robin arbiter to select the next channel read request. A value of '0' means that one TLP is issued.." newline hexmask.long.byte 0x4 0.--4. 1. "WRITE_CHANNEL4_WEIGHT,Channel 4 Weight. The weight is initialized by software before ringing the doorbell. The value is used by the channel weighted round robin arbiter to select the next channel read request. A value of '0' means that one TLP is issued.." group.long (0x2C+0xC8000)++0x7 line.long 0x0 "DMA_READ_ENGINE_EN_OFF,DMA Read Engine Enable Register." hexmask.long.byte 0x0 24.--31. 1. "RSVDP_24,Reserved for future use." bitfld.long 0x0 23. "DMA_READ_ENGINE_EN_HSHAKE_CH7,Enable Handshake for DMA Read Engine Channel 7. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" "0,1" newline bitfld.long 0x0 22. "DMA_READ_ENGINE_EN_HSHAKE_CH6,Enable Handshake for DMA Read Engine Channel 6. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" "0,1" bitfld.long 0x0 21. "DMA_READ_ENGINE_EN_HSHAKE_CH5,Enable Handshake for DMA Read Engine Channel 5. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" "0,1" newline bitfld.long 0x0 20. "DMA_READ_ENGINE_EN_HSHAKE_CH4,Enable Handshake for DMA Read Engine Channel 4. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" "0,1" bitfld.long 0x0 19. "DMA_READ_ENGINE_EN_HSHAKE_CH3,Enable Handshake for DMA Read Engine Channel 3. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" "0,1" newline bitfld.long 0x0 18. "DMA_READ_ENGINE_EN_HSHAKE_CH2,Enable Handshake for DMA Read Engine Channel 2. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" "0,1" bitfld.long 0x0 17. "DMA_READ_ENGINE_EN_HSHAKE_CH1,Enable Handshake for DMA Read Engine Channel 1. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" "0,1" newline bitfld.long 0x0 16. "DMA_READ_ENGINE_EN_HSHAKE_CH0,Enable Handshake for DMA Read Engine Channel 0. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" "0,1" hexmask.long.word 0x0 1.--15. 1. "RSVDP_1,Reserved for future use." newline bitfld.long 0x0 0. "DMA_READ_ENGINE,DMA Read Engine Enable. - 1: Enable - 0: Disable (Soft Reset) For normal operation you must initially set this bit to '1' before any other software setup actions. You do not need to toggle or rewrite to this bit during normal operation." "Disable,Enable" line.long 0x4 "DMA_READ_DOORBELL_OFF,DMA Read Doorbell Register." bitfld.long 0x4 31. "RD_STOP,Stop. Set in conjunction with the Doorbell Number field. The DMA read channel stops issuing requests sets the channel status to 'Stopped' and asserts the 'Abort' interrupt if it is enabled. Before setting the Stop bit you must read the channel.." "0,1" hexmask.long 0x4 3.--30. 1. "RSVDP_3,Reserved for future use." newline bitfld.long 0x4 0.--2. "RD_DOORBELL_NUM,Doorbell Number. You must write 0x0 to this register to start the DMA read transfer for that channel. The DMA detects a write to this register field even if the value of this field does not change. The range of this field is 0x0 to 0x7.." "0,1,2,3,4,5,6,7" group.long (0x38+0xC8000)++0x7 line.long 0x0 "DMA_READ_CHANNEL_ARB_WEIGHT_LOW_OFF,DMA Read Engine Channel Arbitration Weight Low Register. The 5-bit channel weight (for read channels 0-3) specifies the maximum number of TLP requests that the DMA can issue for that channel before it must return to.." hexmask.long.word 0x0 20.--31. 1. "RSVDP_20,Reserved for future use." hexmask.long.byte 0x0 15.--19. 1. "READ_CHANNEL3_WEIGHT,Channel 3 Weight. The weight is initialized by software before ringing the doorbell. The value is used by the channel weighted round robin arbiter to select the next channel read request. Note: The access attributes of this field are.." newline hexmask.long.byte 0x0 10.--14. 1. "READ_CHANNEL2_WEIGHT,Channel 2 Weight. The weight is initialized by software before ringing the doorbell. The value is used by the channel weighted round robin arbiter to select the next channel read request. Note: The access attributes of this field are.." hexmask.long.byte 0x0 5.--9. 1. "READ_CHANNEL1_WEIGHT,Channel 1 Weight. The weight is initialized by software before ringing the doorbell. The value is used by the channel weighted round robin arbiter to select the next channel read request. Note: The access attributes of this field are.." newline hexmask.long.byte 0x0 0.--4. 1. "READ_CHANNEL0_WEIGHT,Channel 0 Weight. The weight is initialized by software before ringing the doorbell. The value is used by the channel weighted round robin arbiter to select the next channel read request. Note: The access attributes of this field are.." line.long 0x4 "DMA_READ_CHANNEL_ARB_WEIGHT_HIGH_OFF,DMA Read Engine Channel Arbitration Weight High Register. The 5-bit channel weight (for read channels 4-7) specifies the maximum number of TLP requests that the DMA can issue for that channel before it must return to.." hexmask.long.word 0x4 20.--31. 1. "RSVDP_20,Reserved for future use." hexmask.long.byte 0x4 15.--19. 1. "READ_CHANNEL7_WEIGHT,Channel 7 Weight. The weight is initialized by software before ringing the doorbell. The value is used by the channel weighted round robin arbiter to select the next channel read request. Note: The access attributes of this field are.." newline hexmask.long.byte 0x4 10.--14. 1. "READ_CHANNEL6_WEIGHT,Channel 6 Weight. The weight is initialized by software before ringing the doorbell. The value is used by the channel weighted round robin arbiter to select the next channel read request. Note: The access attributes of this field are.." hexmask.long.byte 0x4 5.--9. 1. "READ_CHANNEL5_WEIGHT,Channel 5 Weight. The weight is initialized by software before ringing the doorbell. The value is used by the channel weighted round robin arbiter to select the next channel read request. Note: The access attributes of this field are.." newline hexmask.long.byte 0x4 0.--4. 1. "READ_CHANNEL4_WEIGHT,Channel 4 Weight. The weight is initialized by software before ringing the doorbell. The value is used by the channel weighted round robin arbiter to select the next channel read request. Note: The access attributes of this field are.." group.long (0x4C+0xC8000)++0x3 line.long 0x0 "DMA_WRITE_INT_STATUS_OFF,DMA Write Interrupt Status Register." hexmask.long.byte 0x0 24.--31. 1. "RSVDP_24,Reserved for future use." hexmask.long.byte 0x0 16.--23. 1. "WR_ABORT_INT_STATUS,Abort Interrupt Status. The DMA write channel has detected an error or you manually stopped the transfer as described in 'Error Handling Assistance by Remote Software'. Each bit corresponds to a DMA channel. Bit [0] corresponds to.." newline hexmask.long.byte 0x0 8.--15. 1. "RSVDP_8,Reserved for future use." hexmask.long.byte 0x0 0.--7. 1. "WR_DONE_INT_STATUS,Done Interrupt Status. The DMA write channel has successfully completed the DMA transfer. For more details see 'Interrupts and Error Handling'. Each bit corresponds to a DMA channel. Bit [0] corresponds to channel 0. - Enabling: For.." group.long (0x54+0xC8000)++0x7 line.long 0x0 "DMA_WRITE_INT_MASK_OFF,DMA Write Interrupt Mask Register." hexmask.long.byte 0x0 24.--31. 1. "RSVDP_24,Reserved for future use." hexmask.long.byte 0x0 16.--23. 1. "WR_ABORT_INT_MASK,Abort Interrupt Mask. Prevents the Abort interrupt status field in the DMA write interrupt status register from asserting the edma_int output. Each bit corresponds to a DMA channel. Bit [0] corresponds to channel 0. Note: The access.." newline hexmask.long.byte 0x0 8.--15. 1. "RSVDP_8,Reserved for future use." hexmask.long.byte 0x0 0.--7. 1. "WR_DONE_INT_MASK,Done Interrupt Mask. Prevents the Done interrupt status field in the DMA write interrupt status register from asserting the edma_int output. Each bit corresponds to a DMA channel. Bit [0] corresponds to channel 0. Note: The access.." line.long 0x4 "DMA_WRITE_INT_CLEAR_OFF,DMA Write Interrupt Clear Register." hexmask.long.byte 0x4 24.--31. 1. "RSVDP_24,Reserved for future use." hexmask.long.byte 0x4 16.--23. 1. "WR_ABORT_INT_CLEAR,Abort Interrupt Clear. You must write a 1'b1 to clear the corresponding bit in the Abort interrupt status field of the DMA write interrupt status register. Each bit corresponds to a DMA channel. Bit [0] corresponds to channel 0. Note:.." newline hexmask.long.byte 0x4 8.--15. 1. "RSVDP_8,Reserved for future use." hexmask.long.byte 0x4 0.--7. 1. "WR_DONE_INT_CLEAR,Done Interrupt Clear. You must write a 1'b1 to clear the corresponding bit in the Done interrupt status field of the DMA write interrupt status register. Each bit corresponds to a DMA channel. Bit [0] corresponds to channel 0. Note:.." rgroup.long (0x5C+0xC8000)++0x3 line.long 0x0 "DMA_WRITE_ERR_STATUS_OFF,DMA Write Error Status Register" hexmask.long.byte 0x0 24.--31. 1. "RSVDP_24,Reserved for future use." hexmask.long.byte 0x0 16.--23. 1. "LINKLIST_ELEMENT_FETCH_ERR_DETECT,Linked List Element Fetch Error Detected. The DMA write channel has received an error response from the AXI bus (or TRGT1 interface when the AXI Bridge is not used) while reading a linked list element from local memory." newline hexmask.long.byte 0x0 8.--15. 1. "RSVDP_8,Reserved for future use." hexmask.long.byte 0x0 0.--7. 1. "APP_READ_ERR_DETECT,Application Read Error Detected. The DMA write channel has received an error response from the AXI bus (or TRGT1 interface when the AXI Bridge is not used) while reading data from it. Each bit corresponds to a DMA channel. Bit [0].." group.long (0x60+0xC8000)++0x1F line.long 0x0 "DMA_WRITE_DONE_IMWR_LOW_OFF,DMA Write Done IMWr Address Low Register." hexmask.long 0x0 0.--31. 1. "DMA_WRITE_DONE_LOW_REG,The DMA uses this field to generate bits [31:0] of the address field for the Done IMWr TLP. Bits [1:0] must be '00' as this address must be dword aligned. Note: The access attributes of this field are as follows: - Wire: No access." line.long 0x4 "DMA_WRITE_DONE_IMWR_HIGH_OFF,DMA Write Done IMWr Interrupt Address High Register." hexmask.long 0x4 0.--31. 1. "DMA_WRITE_DONE_HIGH_REG,The DMA uses this field to generate bits [63:32] of the address field for the Done IMWr TLP. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" line.long 0x8 "DMA_WRITE_ABORT_IMWR_LOW_OFF,DMA Write Abort IMWr Address Low Register." hexmask.long 0x8 0.--31. 1. "DMA_WRITE_ABORT_LOW_REG,The DMA uses this field to generate bits [31:0] of the address field for the Abort IMWr TLP it generates. Bits [1:0] must be '00' as this address must be dword aligned. Note: The access attributes of this field are as follows: -.." line.long 0xC "DMA_WRITE_ABORT_IMWR_HIGH_OFF,DMA Write Abort IMWr Address High Register." hexmask.long 0xC 0.--31. 1. "DMA_WRITE_ABORT_HIGH_REG,The DMA uses this field to generate bits [63:32] of the address field for the Abort IMWr TLP. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" line.long 0x10 "DMA_WRITE_CH01_IMWR_DATA_OFF,DMA Write Channel 1 and 0 IMWr Data Register." hexmask.long.word 0x10 16.--31. 1. "WR_CHANNEL_1_DATA,The DMA uses this field to generate the data field for the Done or Abort IMWr TLPs it generates for write channel 1. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" hexmask.long.word 0x10 0.--15. 1. "WR_CHANNEL_0_DATA,The DMA uses this field to generate the data field for the Done or Abort IMWr TLPs it generates for write channel 0. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" line.long 0x14 "DMA_WRITE_CH23_IMWR_DATA_OFF,DMA Write Channel 3 and 2 IMWr Data Register." hexmask.long.word 0x14 16.--31. 1. "WR_CHANNEL_3_DATA,The DMA uses this field to generate the data field for the Done or Abort IMWr TLPs it generates for write channel 3. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" hexmask.long.word 0x14 0.--15. 1. "WR_CHANNEL_2_DATA,The DMA uses this field to generate the data field for the Done or Abort IMWr TLPs it generates for write channel 2. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" line.long 0x18 "DMA_WRITE_CH45_IMWR_DATA_OFF,DMA Write Channel 5 and 4 IMWr Data Register." hexmask.long.word 0x18 16.--31. 1. "WR_CHANNEL_5_DATA,The DMA uses this field to generate the data field for the Done or Abort IMWr TLPs it generates for write channel 5. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" hexmask.long.word 0x18 0.--15. 1. "WR_CHANNEL_4_DATA,The DMA uses this field to generate the data field for the Done or Abort IMWr TLPs it generates for write channel 4. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" line.long 0x1C "DMA_WRITE_CH67_IMWR_DATA_OFF,DMA Write Channel 7 and 6 IMWr Data Register." hexmask.long.word 0x1C 16.--31. 1. "WR_CHANNEL_7_DATA,The DMA uses this field to generate the data field for the Done or Abort IMWr TLPs it generates for write channel 7. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" hexmask.long.word 0x1C 0.--15. 1. "WR_CHANNEL_6_DATA,The DMA uses this field to generate the data field for the Done or Abort IMWr TLPs it generates for write channel 6. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" group.long (0x90+0xC8000)++0x3 line.long 0x0 "DMA_WRITE_LINKED_LIST_ERR_EN_OFF,DMA Write Linked List Error Enable Register. The LIE and RIE bits in the LL element enable the channel 'done' interrupts (local and remote). The LLLAIE and LLRAIE bits enable the channel 'abort' interrupts (local and.." hexmask.long.byte 0x0 24.--31. 1. "RSVDP_24,Reserved for future use." hexmask.long.byte 0x0 16.--23. 1. "WR_CHANNEL_LLLAIE,Write Channel LL Local Abort Interrupt Enable (LLLAIE). You enable the write channel local abort interrupt through this bit. The LIE and RIE bits in the LL element enable the write channel done interrupts. Each bit corresponds to a DMA.." newline hexmask.long.byte 0x0 8.--15. 1. "RSVDP_8,Reserved for future use." hexmask.long.byte 0x0 0.--7. 1. "WR_CHANNEL_LLRAIE,Write Channel LL Remote Abort Interrupt Enable (LLRAIE). You enable the write channel remote abort interrupt through this bit. The LIE and RIE bits in the LL element enable the write channel done interrupts. Each bit corresponds to a.." group.long (0xA0+0xC8000)++0x3 line.long 0x0 "DMA_READ_INT_STATUS_OFF,DMA Read Interrupt Status Register." hexmask.long.byte 0x0 24.--31. 1. "RSVDP_24,Reserved for future use." hexmask.long.byte 0x0 16.--23. 1. "RD_ABORT_INT_STATUS,Abort Interrupt Status. The DMA read channel has detected an error or you manually stopped the transfer as described in 'Stopping the DMA Transfer (Software Stop)'. Each bit corresponds to a DMA channel. Bit [0] corresponds to.." newline hexmask.long.byte 0x0 8.--15. 1. "RSVDP_8,Reserved for future use." hexmask.long.byte 0x0 0.--7. 1. "RD_DONE_INT_STATUS,Done Interrupt Status. The DMA read channel has successfully completed the DMA read transfer. Each bit corresponds to a DMA channel. Bit [0] corresponds to channel 0. - Enabling: For details see 'Interrupts and Error Handling'. -.." group.long (0xA8+0xC8000)++0x7 line.long 0x0 "DMA_READ_INT_MASK_OFF,DMA Read Interrupt Mask Register." hexmask.long.byte 0x0 24.--31. 1. "RSVDP_24,Reserved for future use." hexmask.long.byte 0x0 16.--23. 1. "RD_ABORT_INT_MASK,Abort Interrupt Mask. Prevents the Abort interrupt status field in the DMA read interrupt status register from asserting the edma_int output. Each bit corresponds to a DMA channel. Bit [0] corresponds to channel 0. Note: The access.." newline hexmask.long.byte 0x0 8.--15. 1. "RSVDP_8,Reserved for future use." hexmask.long.byte 0x0 0.--7. 1. "RD_DONE_INT_MASK,Done Interrupt Mask. Prevents the Done interrupt status field in the DMA read interrupt status register from asserting the edma_int output. Each bit corresponds to a DMA channel. Bit [0] corresponds to channel 0. Note: The access.." line.long 0x4 "DMA_READ_INT_CLEAR_OFF,DMA Read Interrupt Clear Register." hexmask.long.byte 0x4 24.--31. 1. "RSVDP_24,Reserved for future use." hexmask.long.byte 0x4 16.--23. 1. "RD_ABORT_INT_CLEAR,Abort Interrupt Clear. You must write a 1'b1 to clear the corresponding bit in the Abort interrupt status field of the DMA read interrupt status register. Each bit corresponds to a DMA channel. Bit [0] corresponds to channel 0. Note:.." newline hexmask.long.byte 0x4 8.--15. 1. "RSVDP_8,Reserved for future use." hexmask.long.byte 0x4 0.--7. 1. "RD_DONE_INT_CLEAR,Done Interrupt Clear. You must write a 1'b1 to clear the corresponding bit in the Done interrupt status field of the DMA read interrupt status register. Each bit corresponds to a DMA channel. Bit [0] corresponds to channel 0. Note:.." rgroup.long (0xB4+0xC8000)++0x7 line.long 0x0 "DMA_READ_ERR_STATUS_LOW_OFF,DMA Read Error Status Low Register." hexmask.long.byte 0x0 24.--31. 1. "RSVDP_24,Reserved for future use." hexmask.long.byte 0x0 16.--23. 1. "LINK_LIST_ELEMENT_FETCH_ERR_DETECT,Linked List Element Fetch Error Detected. - The DMA read channel has received an error response from the AXI bus while reading a linked list element from local memory. Each bit corresponds to a DMA channel. Bit [0].." newline hexmask.long.byte 0x0 8.--15. 1. "RSVDP_8,Reserved for future use." hexmask.long.byte 0x0 0.--7. 1. "APP_WR_ERR_DETECT,Application Write Error Detected. The DMA read channel has received an error response from the AXI bus (or TRGT1 interface when the AXI Bridge is not used) while writing data to it. This error is fatal. You must restart the transfer.." line.long 0x4 "DMA_READ_ERR_STATUS_HIGH_OFF,DMA Read Error Status High Register." hexmask.long.byte 0x4 24.--31. 1. "DATA_POISIONING,Data Poisoning. The DMA read channel has detected data poisoning in the completion from the remote device (in response to the MRd request). The DMA read channel will drop the completion and then be halted. The CX_FLT_MASK_UR_POIS filter.." hexmask.long.byte 0x4 16.--23. 1. "CPL_TIMEOUT,Completion Time Out. The DMA read channel has timed-out while waiting for the remote device to respond to the MRd request or a malformed CplD has been received. For more details see 'Linked List Mode'. Each bit corresponds to a DMA channel." newline hexmask.long.byte 0x4 8.--15. 1. "CPL_ABORT,Completer Abort. The DMA read channel has received a PCIe completer abort completion status from the remote device in response to the MRd request. For more details see 'Linked List Mode'. Each bit corresponds to a DMA channel. Bit [0].." hexmask.long.byte 0x4 0.--7. 1. "UNSUPPORTED_REQ,Unsupported Request. The DMA read channel has received a PCIe unsupported request completion status from the remote device in response to the MRd request. For more details see 'Linked List Mode'. Each bit corresponds to a DMA channel." group.long (0xC4+0xC8000)++0x3 line.long 0x0 "DMA_READ_LINKED_LIST_ERR_EN_OFF,DMA Read Linked List Error Enable Register. The LIE and RIE bits in the LL element enable the channel 'done' interrupts (local and remote). The LLLAIE and LLRAIE bits enable the channel 'abort' interrupts (local and remote)." hexmask.long.byte 0x0 24.--31. 1. "RSVDP_24,Reserved for future use." hexmask.long.byte 0x0 16.--23. 1. "RD_CHANNEL_LLLAIE,Read Channel LL Local Abort Interrupt Enable (LLLAIE). You enable the read channel Local Abort interrupt through this bit. The LIE and RIE bits in the LL element enable the read channel done interrupts. Each bit corresponds to a DMA.." newline hexmask.long.byte 0x0 8.--15. 1. "RSVDP_8,Reserved for future use." hexmask.long.byte 0x0 0.--7. 1. "RD_CHANNEL_LLRAIE,Read Channel LL Remote Abort Interrupt Enable (LLRAIE). You enable the read channel Remote Abort interrupt through this bit. The LIE and RIE bits in the LL element enable the read channel done interrupts. Each bit corresponds to a DMA.." group.long (0xCC+0xC8000)++0x1F line.long 0x0 "DMA_READ_DONE_IMWR_LOW_OFF,DMA Read Done IMWr Address Low Register." hexmask.long 0x0 0.--31. 1. "DMA_READ_DONE_LOW_REG,The DMA uses this field to generate bits [31:0] of the address field for the Done IMWr TLP. Bits [1:0] must be '00' as this address must be dword aligned. Note: The access attributes of this field are as follows: - Wire: No access." line.long 0x4 "DMA_READ_DONE_IMWR_HIGH_OFF,DMA Read Done IMWr Address High Register." hexmask.long 0x4 0.--31. 1. "DMA_READ_DONE_HIGH_REG,The DMA uses this field to generate bits [63:32] of the address field for the Done IMWr TLP. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" line.long 0x8 "DMA_READ_ABORT_IMWR_LOW_OFF,DMA Read Abort IMWr Address Low Register." hexmask.long 0x8 0.--31. 1. "DMA_READ_ABORT_LOW_REG,The DMA uses this field to generate bits [31:0] of the address field for the Abort IMWr TLP. Bits [1:0] must be '00' as this address must be dword aligned. Note: The access attributes of this field are as follows: - Wire: No.." line.long 0xC "DMA_READ_ABORT_IMWR_HIGH_OFF,DMA Read Abort IMWr Address High Register." hexmask.long 0xC 0.--31. 1. "DMA_READ_ABORT_HIGH_REG,The DMA uses this field to generate bits [63:32] of the address field for the Abort IMWr TLP. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" line.long 0x10 "DMA_READ_CH01_IMWR_DATA_OFF,DMA Read Channel 1 and 0 IMWr Data Register." hexmask.long.word 0x10 16.--31. 1. "RD_CHANNEL_1_DATA,The DMA uses this field to generate the data field for the Done or Abort IMWr TLPs it generates for read channel 1. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" hexmask.long.word 0x10 0.--15. 1. "RD_CHANNEL_0_DATA,The DMA uses this field to generate the data field for the Done or Abort IMWr TLPs it generates for read channel 0. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" line.long 0x14 "DMA_READ_CH23_IMWR_DATA_OFF,DMA Read Channel 3 and 2 IMWr Data Register." hexmask.long.word 0x14 16.--31. 1. "RD_CHANNEL_3_DATA,The DMA uses this field to generate the data field for the Done or Abort IMWr TLPs it generates for read channel 3. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" hexmask.long.word 0x14 0.--15. 1. "RD_CHANNEL_2_DATA,The DMA uses this field to generate the data field for the Done or Abort IMWr TLPs it generates for read channel 2. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" line.long 0x18 "DMA_READ_CH45_IMWR_DATA_OFF,DMA Read Channel 5 and 4 IMWr Data Register." hexmask.long.word 0x18 16.--31. 1. "RD_CHANNEL_5_DATA,The DMA uses this field to generate the data field for the Done or Abort IMWr TLPs it generates for read channel 5. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" hexmask.long.word 0x18 0.--15. 1. "RD_CHANNEL_4_DATA,The DMA uses this field to generate the data field for the Done or Abort IMWr TLPs it generates for read channel 4. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" line.long 0x1C "DMA_READ_CH67_IMWR_DATA_OFF,DMA Read Channel 7 and 6 IMWr Data Register." hexmask.long.word 0x1C 16.--31. 1. "RD_CHANNEL_7_DATA,The DMA uses this field to generate the data field for the Done or Abort IMWr TLPs it generates for read channel 7. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" hexmask.long.word 0x1C 0.--15. 1. "RD_CHANNEL_6_DATA,The DMA uses this field to generate the data field for the Done or Abort IMWr TLPs it generates for read channel 6. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" rgroup.long (0x108+0xC8000)++0x7 line.long 0x0 "DMA_WRITE_ENGINE_HSHAKE_CNT_LOW_OFF,DMA Write Engine Handshake Counter Channel 0/1/2/3 Register." bitfld.long 0x0 29.--31. "RSVDP_29,Reserved for future use." "0,1,2,3,4,5,6,7" hexmask.long.byte 0x0 24.--28. 1. "DMA_WRITE_ENGINE_HSHAKE_CNT_CH3,DMA handshake counter for DMA Write Engine Channel 3. If CC_DMA_HSHAKE =1 the data transfer in Linked List mode starts only when the counter is non-zero." newline bitfld.long 0x0 21.--23. "RSVDP_21,Reserved for future use." "0,1,2,3,4,5,6,7" hexmask.long.byte 0x0 16.--20. 1. "DMA_WRITE_ENGINE_HSHAKE_CNT_CH2,DMA handshake counter for DMA Write Engine Channel 2. If CC_DMA_HSHAKE =1 the data transfer in Linked List mode starts only when the counter is non-zero." newline bitfld.long 0x0 13.--15. "RSVDP_13,Reserved for future use." "0,1,2,3,4,5,6,7" hexmask.long.byte 0x0 8.--12. 1. "DMA_WRITE_ENGINE_HSHAKE_CNT_CH1,DMA handshake counter for DMA Write Engine Channel 1. If CC_DMA_HSHAKE =1 the data transfer in Linked List mode starts only when the counter is non-zero." newline bitfld.long 0x0 5.--7. "RSVDP_5,Reserved for future use." "0,1,2,3,4,5,6,7" hexmask.long.byte 0x0 0.--4. 1. "DMA_WRITE_ENGINE_HSHAKE_CNT_CH0,DMA handshake counter for DMA Write Engine Channel 0. If CC_DMA_HSHAKE =1 the data transfer in Linked List mode starts only when the counter is non-zero." line.long 0x4 "DMA_WRITE_ENGINE_HSHAKE_CNT_HIGH_OFF,DMA Write Engine Handshake Counter Channel 4/5/6/7 Register." bitfld.long 0x4 29.--31. "RSVDP_29,Reserved for future use." "0,1,2,3,4,5,6,7" hexmask.long.byte 0x4 24.--28. 1. "DMA_WRITE_ENGINE_HSHAKE_CNT_CH7,DMA handshake counter for DMA Write Engine Channel 7. If CC_DMA_HSHAKE =1 the data transfer in Linked List mode starts only when the counter is non-zero." newline bitfld.long 0x4 21.--23. "RSVDP_21,Reserved for future use." "0,1,2,3,4,5,6,7" hexmask.long.byte 0x4 16.--20. 1. "DMA_WRITE_ENGINE_HSHAKE_CNT_CH6,DMA handshake counter for DMA Write Engine Channel 6. If CC_DMA_HSHAKE =1 the data transfer in Linked List mode starts only when the counter is non-zero." newline bitfld.long 0x4 13.--15. "RSVDP_13,Reserved for future use." "0,1,2,3,4,5,6,7" hexmask.long.byte 0x4 8.--12. 1. "DMA_WRITE_ENGINE_HSHAKE_CNT_CH5,DMA handshake counter for DMA Write Engine Channel 5. If CC_DMA_HSHAKE =1 the data transfer in Linked List mode starts only when the counter is non-zero." newline bitfld.long 0x4 5.--7. "RSVDP_5,Reserved for future use." "0,1,2,3,4,5,6,7" hexmask.long.byte 0x4 0.--4. 1. "DMA_WRITE_ENGINE_HSHAKE_CNT_CH4,DMA handshake counter for DMA Write Engine Channel 4. If CC_DMA_HSHAKE =1 the data transfer in Linked List mode starts only when the counter is non-zero." rgroup.long (0x118+0xC8000)++0x7 line.long 0x0 "DMA_READ_ENGINE_HSHAKE_CNT_LOW_OFF,DMA Read Engine Handshake Counter Channel 0/1/2/3 Register." bitfld.long 0x0 29.--31. "RSVDP_29,Reserved for future use." "0,1,2,3,4,5,6,7" hexmask.long.byte 0x0 24.--28. 1. "DMA_READ_ENGINE_HSHAKE_CNT_CH3,DMA handshake counter for DMA Read Engine Channel 3. If CC_DMA_HSHAKE =1 the data transfer in Linked List mode starts only when the counter is non-zero." newline bitfld.long 0x0 21.--23. "RSVDP_21,Reserved for future use." "0,1,2,3,4,5,6,7" hexmask.long.byte 0x0 16.--20. 1. "DMA_READ_ENGINE_HSHAKE_CNT_CH2,DMA handshake counter for DMA Read Engine Channel 2. If CC_DMA_HSHAKE =1 the data transfer in Linked List mode starts only when the counter is non-zero." newline bitfld.long 0x0 13.--15. "RSVDP_13,Reserved for future use." "0,1,2,3,4,5,6,7" hexmask.long.byte 0x0 8.--12. 1. "DMA_READ_ENGINE_HSHAKE_CNT_CH1,DMA handshake counter for DMA Read Engine Channel 1. If CC_DMA_HSHAKE =1 the data transfer in Linked List mode starts only when the counter is non-zero." newline bitfld.long 0x0 5.--7. "RSVDP_5,Reserved for future use." "0,1,2,3,4,5,6,7" hexmask.long.byte 0x0 0.--4. 1. "DMA_READ_ENGINE_HSHAKE_CNT_CH0,DMA handshake counter for DMA Read Engine Channel 0. If CC_DMA_HSHAKE =1 the data transfer in Linked List mode starts only when the counter is non-zero." line.long 0x4 "DMA_READ_ENGINE_HSHAKE_CNT_HIGH_OFF,DMA Read Engine Handshake Counter Channel 4/5/6/7 Register." bitfld.long 0x4 29.--31. "RSVDP_29,Reserved for future use." "0,1,2,3,4,5,6,7" hexmask.long.byte 0x4 24.--28. 1. "DMA_READ_ENGINE_HSHAKE_CNT_CH7,DMA handshake counter for DMA Read Engine Channel 7. If CC_DMA_HSHAKE =1 the data transfer in Linked List mode starts only when the counter is non-zero." newline bitfld.long 0x4 21.--23. "RSVDP_21,Reserved for future use." "0,1,2,3,4,5,6,7" hexmask.long.byte 0x4 16.--20. 1. "DMA_READ_ENGINE_HSHAKE_CNT_CH6,DMA handshake counter for DMA Read Engine Channel 6. If CC_DMA_HSHAKE =1 the data transfer in Linked List mode starts only when the counter is non-zero." newline bitfld.long 0x4 13.--15. "RSVDP_13,Reserved for future use." "0,1,2,3,4,5,6,7" hexmask.long.byte 0x4 8.--12. 1. "DMA_READ_ENGINE_HSHAKE_CNT_CH5,DMA handshake counter for DMA Read Engine Channel 5. If CC_DMA_HSHAKE =1 the data transfer in Linked List mode starts only when the counter is non-zero." newline bitfld.long 0x4 5.--7. "RSVDP_5,Reserved for future use." "0,1,2,3,4,5,6,7" hexmask.long.byte 0x4 0.--4. 1. "DMA_READ_ENGINE_HSHAKE_CNT_CH4,DMA handshake counter for DMA Read Engine Channel 4. If CC_DMA_HSHAKE =1 the data transfer in Linked List mode starts only when the counter is non-zero." repeat 8. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 )(list 0x0 0x200 0x400 0x600 0x800 0xA00 0xC00 0xE00 ) group.long ($2+0x200+0xC8000)++0x3 line.long 0x0 "DMA_CH_CONTROL1_OFF_WRCH_$1,DMA Write Channel Control 1 Register." bitfld.long 0x0 30.--31. "DMA_AT,Address Translation TLP Header Bit (AT) The DMA uses this TLP header field when generating MRd/MWr (not IMWr) TLPs. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" "0,1,2,3" bitfld.long 0x0 27.--29. "DMA_TC,Traffic Class TLP Header Bit (TC) The DMA uses this TLP header field when generating MRd/MWr (not IMWr) TLPs. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 26. "DMA_RESERVED5,Reserved. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" "0,1" bitfld.long 0x0 25. "DMA_RO,Relaxed Ordering TLP Header Bit (RO) The DMA uses this TLP header field when generating MRd/MWr (not IMWr) TLPs. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" "0,1" newline bitfld.long 0x0 24. "DMA_NS_SRC,Source No Snoop TLP Header Bit (DMA_NS_SRC). The DMA uses this TLP header field when generating MRd (SAR addressing space) (not IMWr) TLPs. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" "0,1" bitfld.long 0x0 23. "DMA_NS_DST,Destination No Snoop TLP Header Bit (DMA_NS_DST). The DMA uses this TLP header field when generating MWr (DAR addressing space) (not IMWr) TLPs. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" "0,1" newline bitfld.long 0x0 22. "DMA_MEM_TYPE,Master AXI ACE-Lite Cache Coherency Control. This field sets the DMA channel memory type of the address space of the data transfer as follows: - 0x0:peripheral type - 0x1:memory type For more details see 'ACE-Lite Features and Limitations'.." "peripheral type,memory type" hexmask.long.byte 0x0 17.--21. 1. "DMA_RESERVED2,Reserved. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" newline hexmask.long.byte 0x0 12.--16. 1. "DMA_FUNC_NUM,Function Number (FN). The controller uses this field when generating the requester ID for the MRd/MWr DMA TLP. When you have enabled SR-IOV then this field is ignored if you have set the VFE field in the 'DMA Write Channel Control 2.." bitfld.long 0x0 10.--11. "DMA_RESERVED1,Reserved. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" "0,1,2,3" newline bitfld.long 0x0 9. "LLE,Linked List Enable (LLE). - 0: Disable linked list operation - 1: Enable linked list operation Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" "Disable linked list operation,Enable linked list operation" bitfld.long 0x0 8. "CCS,Consumer Cycle State (CCS). Used in linked list mode only. It is used to synchronize the producer (software) and the consumer (DMA). For more details see 'PCS-CCS-CB-TCB Producer-Consumer Synchronization'. You must initialize this bit. The DMA.." "0,1" newline bitfld.long 0x0 7. "DMA_RESERVED0,Reserved. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" "0,1" bitfld.long 0x0 5.--6. "CS,Channel Status (CS). The channel status bits identify the current operational state of the DMA channel. The operation state encoding for each DMA channel is a s follows: - 00: Reserved - 01: Running. This channel is active and transferring data. - 10:.." "Reserved,Running,?,?" newline bitfld.long 0x0 4. "RIE,Remote Interrupt Enable (RIE). You must set this bit to enable the generation of the Done or Abort Remote interrupts. For more details see 'Interrupts and Error Handling'. In LL mode the DMA overwrites this with the RIE of the LL element. The RIE.." "0,1" bitfld.long 0x0 3. "LIE,Local Interrupt Enable (LIE). You must set this bit to enable the generation of the Done or Abort Local interrupts. For more details see 'Interrupts and Error Handling'. In LL mode the DMA overwrites this with the LIE of the LL element. The LIE bit.." "0,1" newline bitfld.long 0x0 2. "LLP,Load Link Pointer (LLP). Used in linked list mode only. Indicates that this linked list element is a link element and its LL element pointer dwords are pointing to the next (non-contiguous) element. The DMA loads this field with the LLP of the.." "0,1" bitfld.long 0x0 1. "TCB,Toggle Cycle Bit (TCB). Indicates to the DMA to toggle its interpretation of the CB. Used in linked list mode only. It is used to synchronize the producer (software) and the consumer (DMA). For more details see 'PCS-CCS-CB-TCB Producer-Consumer.." "0,1" newline bitfld.long 0x0 0. "CB,Cycle Bit (CB). Used in linked list mode only. It is used to synchronize the producer (software) and the consumer (DMA). For more details see 'PCS-CCS-CB-TCB Producer-Consumer Synchronization'. The DMA loads this field with the CB of the linked list.." "0,1" repeat.end repeat 8. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 )(list 0x0 0x200 0x400 0x600 0x800 0xA00 0xC00 0xE00 ) group.long ($2+0x208+0xC8000)++0x3 line.long 0x0 "DMA_TRANSFER_SIZE_OFF_WRCH_$1,DMA Write Transfer Size Register." hexmask.long 0x0 0.--31. 1. "DMA_TRANSFER_SIZE,DMA Transfer Size. You program this register with the size of the DMA transfer. The maximum DMA transfer size is 4Gbytes. The minimum transfer size is one byte (0x1). This field is automatically decremented by the DMA as the DMA write.." repeat.end repeat 8. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 )(list 0x0 0x200 0x400 0x600 0x800 0xA00 0xC00 0xE00 ) group.long ($2+0x20C+0xC8000)++0x3 line.long 0x0 "DMA_SAR_LOW_OFF_WRCH_$1,DMA Write SAR Low Register." hexmask.long 0x0 0.--31. 1. "SRC_ADDR_REG_LOW,Source Address Register (Lower 32 bits). Indicates the next address to be read from. The DMA increments the SAR as the DMA transfer progresses. In LL mode the DMA overwrites this with the corresponding dword of the LL element. - DMA.." repeat.end repeat 8. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 )(list 0x0 0x200 0x400 0x600 0x800 0xA00 0xC00 0xE00 ) group.long ($2+0x210+0xC8000)++0x3 line.long 0x0 "DMA_SAR_HIGH_OFF_WRCH_$1,DMA Write SAR High Register." hexmask.long 0x0 0.--31. 1. "SRC_ADDR_REG_HIGH,Source Address Register (Higher 32 bits). In LL mode the DMA overwrites this with the corresponding dword of the LL element. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" repeat.end repeat 8. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 )(list 0x0 0x200 0x400 0x600 0x800 0xA00 0xC00 0xE00 ) group.long ($2+0x214+0xC8000)++0x3 line.long 0x0 "DMA_DAR_LOW_OFF_WRCH_$1,DMA Write DAR Low Register." hexmask.long 0x0 0.--31. 1. "DST_ADDR_REG_LOW,Destination Address Register (Lower 32 bits). Indicates the next address to be written to. The DMA increments the DAR as the DMA transfer progresses. In LL mode the DMA overwrites this with the corresponding dword of the LL element. -.." repeat.end repeat 8. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 )(list 0x0 0x200 0x400 0x600 0x800 0xA00 0xC00 0xE00 ) group.long ($2+0x218+0xC8000)++0x3 line.long 0x0 "DMA_DAR_HIGH_OFF_WRCH_$1,DMA Write DAR High Register." hexmask.long 0x0 0.--31. 1. "DST_ADDR_REG_HIGH,Destination Address Register (Higher 32 bits). In LL mode the DMA overwrites this with the corresponding dword of the LL element. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" repeat.end repeat 8. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 )(list 0x0 0x200 0x400 0x600 0x800 0xA00 0xC00 0xE00 ) group.long ($2+0x21C+0xC8000)++0x3 line.long 0x0 "DMA_LLP_LOW_OFF_WRCH_$1,DMA Write Linked List Pointer Low Register." hexmask.long 0x0 0.--31. 1. "LLP_LOW,Lower bits of the address of the linked list transfer list in local memory. Used in linked list mode only. Updated by the DMA to point to the next element in the transfer list after the previous element is consumed. - When the current element is.." repeat.end repeat 8. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 )(list 0x0 0x200 0x400 0x600 0x800 0xA00 0xC00 0xE00 ) group.long ($2+0x220+0xC8000)++0x3 line.long 0x0 "DMA_LLP_HIGH_OFF_WRCH_$1,DMA Write Linked List Pointer High Register." hexmask.long 0x0 0.--31. 1. "LLP_HIGH,Upper 32 bits of the address of the linked list transfer list in local memory. Used in linked list mode only. Updated by the DMA to point to the next element in the transfer list as elements are consumed. Note: The access attributes of this.." repeat.end repeat 8. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 )(list 0x0 0x200 0x400 0x600 0x800 0xA00 0xC00 0xE00 ) group.long ($2+0x300+0xC8000)++0x3 line.long 0x0 "DMA_CH_CONTROL1_OFF_RDCH_$1,DMA Read Channel Control 1 Register." bitfld.long 0x0 30.--31. "DMA_AT,Address Translation TLP Header Bit (AT) The DMA uses this TLP header field when generating MRd/MWr (not IMWr) TLPs. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" "0,1,2,3" bitfld.long 0x0 27.--29. "DMA_TC,Traffic Class TLP Header Bit (TC) The DMA uses this TLP header field when generating MRd/MWr (not IMWr) TLPs. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 26. "DMA_RESERVED5,Reserved. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" "0,1" bitfld.long 0x0 25. "DMA_RO,Relaxed Ordering TLP Header Bit (RO) The DMA uses this TLP header field when generating MRd/MWr (not IMWr) TLPs. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" "0,1" newline bitfld.long 0x0 24. "DMA_NS_SRC,Source No Snoop TLP Header Bit (DMA_NS_SRC). The DMA uses this TLP header field when generating MRd (SAR addressing space) (not IMWr) TLPs. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" "0,1" bitfld.long 0x0 23. "DMA_NS_DST,Destination No Snoop TLP Header Bit (DMA_NS_DST). The DMA uses this TLP header field when generating MWr (DAR addressing space) (not IMWr) TLPs. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" "0,1" newline bitfld.long 0x0 22. "DMA_MEM_TYPE,Master AXI ACE-Lite Cache Coherency Control. This field sets the DMA channel memory type of the address space of the data transfer as follows: - 0x0:peripheral type - 0x1:memory type For more details see 'ACE-Lite Features and Limitations'.." "peripheral type,memory type" hexmask.long.byte 0x0 17.--21. 1. "DMA_RESERVED2,Reserved. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" newline hexmask.long.byte 0x0 12.--16. 1. "DMA_FUNC_NUM,Function Number (FN). The controller uses this field when generating the requester ID for the MRd/MWr DMA TLP. When you have enabled SR-IOV then this field is ignored if you have set the VFE field in the 'DMA Read Channel Control 2.." bitfld.long 0x0 10.--11. "DMA_RESERVED1,Reserved. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" "0,1,2,3" newline bitfld.long 0x0 9. "LLE,Linked List Enable (LLE). - 0: Disable linked list operation - 1: Enable linked list operation Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" "Disable linked list operation,Enable linked list operation" bitfld.long 0x0 8. "CCS,Consumer Cycle State (CCS). Used in linked list mode only. It is used to synchronize the producer (software) and the consumer (DMA). For more details see 'PCS-CCS-CB-TCB Producer-Consumer Synchronization'. You must initialize this bit. The DMA.." "0,1" newline bitfld.long 0x0 7. "DMA_RESERVED0,Reserved. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" "0,1" bitfld.long 0x0 5.--6. "CS,Channel Status (CS). The channel status bits identify the current operational state of the DMA channel. The operation state encoding for each DMA channel is a s follows: - 00: Reserved - 01: Running. This channel is active and transferring data. - 10:.." "Reserved,Running,?,?" newline bitfld.long 0x0 4. "RIE,Remote Interrupt Enable (RIE). You must set this bit to enable the generation of the Done or Abort Remote interrupts. For more details see 'Interrupts and Error Handling'. In LL mode the DMA overwrites this with the RIE of the LL element. The RIE.." "0,1" bitfld.long 0x0 3. "LIE,Local Interrupt Enable (LIE). You must set this bit to enable the generation of the Done or Abort Local interrupts. For more details see 'Interrupts and Error Handling'. In LL mode the DMA overwrites this with the LIE of the LL element. The LIE bit.." "0,1" newline bitfld.long 0x0 2. "LLP,Load Link Pointer (LLP). Used in linked list mode only. Indicates that this linked list element is a link element and its LL element pointer dwords are pointing to the next (non-contiguous) element. The DMA loads this field with the LLP of the.." "0,1" bitfld.long 0x0 1. "TCB,Toggle Cycle Bit (TCB). Indicates to the DMA to toggle its interpretation of the CB. Used in linked list mode only. It is used to synchronize the producer (software) and the consumer (DMA). For more details see 'PCS-CCS-CB-TCB Producer-Consumer.." "0,1" newline bitfld.long 0x0 0. "CB,Cycle Bit (CB). Used in linked list mode only. It is used to synchronize the producer (software) and the consumer (DMA). For more details see 'PCS-CCS-CB-TCB Producer-Consumer Synchronization'. The DMA loads this field with the CB of the linked list.." "0,1" repeat.end repeat 8. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 )(list 0x0 0x200 0x400 0x600 0x800 0xA00 0xC00 0xE00 ) group.long ($2+0x308+0xC8000)++0x3 line.long 0x0 "DMA_TRANSFER_SIZE_OFF_RDCH_$1,DMA Read Transfer Size Register." hexmask.long 0x0 0.--31. 1. "DMA_TRANSFER_SIZE,DMA Transfer Size. You program this register with the size of the DMA transfer. The maximum DMA transfer size is 4Gbytes. The minimum transfer size is one byte (0x1). This field is automatically decremented by the DMA as the DMA read.." repeat.end repeat 8. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 )(list 0x0 0x200 0x400 0x600 0x800 0xA00 0xC00 0xE00 ) group.long ($2+0x30C+0xC8000)++0x3 line.long 0x0 "DMA_SAR_LOW_OFF_RDCH_$1,DMA Read SAR Low Register." hexmask.long 0x0 0.--31. 1. "SRC_ADDR_REG_LOW,Source Address Register (Lower 32 bits). Indicates the next address to be read from. The DMA increments the SAR as the DMA transfer progresses. In LL mode the DMA overwrites this with the corresponding dword of the LL element. - DMA.." repeat.end repeat 8. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 )(list 0x0 0x200 0x400 0x600 0x800 0xA00 0xC00 0xE00 ) group.long ($2+0x310+0xC8000)++0x3 line.long 0x0 "DMA_SAR_HIGH_OFF_RDCH_$1,DMA Read SAR High Register." hexmask.long 0x0 0.--31. 1. "SRC_ADDR_REG_HIGH,Source Address Register (Higher 32 bits). In LL mode the DMA overwrites this with the corresponding dword of the LL element. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" repeat.end repeat 8. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 )(list 0x0 0x200 0x400 0x600 0x800 0xA00 0xC00 0xE00 ) group.long ($2+0x314+0xC8000)++0x3 line.long 0x0 "DMA_DAR_LOW_OFF_RDCH_$1,DMA Read DAR Low Register." hexmask.long 0x0 0.--31. 1. "DST_ADDR_REG_LOW,Destination Address Register (Lower 32 bits). Indicates the next address to be written to. The DMA increments the DAR as the DMA transfer progresses. In LL mode the DMA overwrites this with the corresponding dword of the LL element. -.." repeat.end repeat 8. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 )(list 0x0 0x200 0x400 0x600 0x800 0xA00 0xC00 0xE00 ) group.long ($2+0x318+0xC8000)++0x3 line.long 0x0 "DMA_DAR_HIGH_OFF_RDCH_$1,DMA Read DAR High Register." hexmask.long 0x0 0.--31. 1. "DST_ADDR_REG_HIGH,Destination Address Register (Higher 32 bits). In LL mode the DMA overwrites this with the corresponding dword of the LL element. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" repeat.end repeat 8. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 )(list 0x0 0x200 0x400 0x600 0x800 0xA00 0xC00 0xE00 ) group.long ($2+0x31C+0xC8000)++0x3 line.long 0x0 "DMA_LLP_LOW_OFF_RDCH_$1,DMA Read Linked List Pointer Low Register." hexmask.long 0x0 0.--31. 1. "LLP_LOW,Lower bits of the address of the linked list transfer list in local memory. Used in linked list mode only. Updated by the DMA to point to the next element in the transfer list after the previous element is consumed. - When the current element is.." repeat.end repeat 8. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 )(list 0x0 0x200 0x400 0x600 0x800 0xA00 0xC00 0xE00 ) group.long ($2+0x320+0xC8000)++0x3 line.long 0x0 "DMA_LLP_HIGH_OFF_RDCH_$1,DMA Read Linked List Pointer High Register." hexmask.long 0x0 0.--31. 1. "LLP_HIGH,Upper 32 bits of the address of the linked list transfer list in local memory. Used in linked list mode only. Updated by the DMA to point to the next element in the transfer list as elements are consumed. Note: The access attributes of this.." repeat.end tree.end tree "PF0_ATU_CAP (ATU Por Logic Structure)" repeat 8. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 )(list 0x0 0x200 0x400 0x600 0x800 0xA00 0xC00 0xE00 ) group.long ($2+0xC0000)++0x3 line.long 0x0 "IATU_REGION_CTRL_1_OFF_OUTBOUND_$1,iATU Region Control 1 Register." bitfld.long 0x0 20. "CTRL_1_FUNC_NUM,Function Number. - When the address of an outbound TLP is matched to this region and the FUNC_BYPASS field in the 'iATU Control 2 Register' is '0' then the function number used in generating the function part of the requester ID (RID).." "0,1" newline bitfld.long 0x0 13. "INCREASE_REGION_SIZE,Increase the maximum ATU Region size. When set the maximum ATU Region size is determined by CX_ATU_MAX_REGION_SIZE. When clear the maximum ATU Region size is 4 GB (default). Note: This register field is sticky." "0,1" newline bitfld.long 0x0 9.--10. "ATTR,When the address of an outbound TLP is matched to this region then the ATTR field of the TLP is changed to the value in this register. Note: This register field is sticky." "0,1,2,3" newline bitfld.long 0x0 8. "TD,This is a reserved field. Do not use. Note: This register field is sticky." "0,1" newline bitfld.long 0x0 5.--7. "TC,When the address of an outbound TLP is matched to this region then the TC field of the TLP is changed to the value in this register. Note: This register field is sticky." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x0 0.--4. 1. "TYPE,When the address of an outbound TLP is matched to this region then the TYPE field of the TLP is changed to the value in this register. Note: This register field is sticky." repeat.end repeat 8. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 )(list 0x0 0x200 0x400 0x600 0x800 0xA00 0xC00 0xE00 ) group.long ($2+0x4+0xC0000)++0x3 line.long 0x0 "IATU_REGION_CTRL_2_OFF_OUTBOUND_$1,iATU Region Control 2 Register." bitfld.long 0x0 31. "REGION_EN,Region Enable. This bit must be set to '1' for address translation to take place. Note: This register field is sticky." "0,1" newline bitfld.long 0x0 29. "INVERT_MODE,Invert Mode. When set the address matching region is inverted. Therefore an address match occurs when the untranslated address is in the region outside the defined range (Base Address to Limit Address). Note: This register field is sticky." "0,1" newline bitfld.long 0x0 28. "CFG_SHIFT_MODE,CFG Shift Mode. The iATU uses bits [27:12] of the untranslated address (on the XALI0/1/2 interface or AXI slave interface address) to form the BDF number of the outgoing CFG TLP. This supports the Enhanced Configuration Address Mapping.." "0,1" newline bitfld.long 0x0 27. "DMA_BYPASS,DMA Bypass Mode. Allows request TLPs which are initiated by the DMA controller to pass through the iATU untranslated. Note: This field is reserved for the SW product. You must set it to '0'. Note: This register field is sticky." "0,1" newline bitfld.long 0x0 23. "HEADER_SUBSTITUTE_EN,Header Substitute Enable. When enabled and region address is matched the iATU fully substitutes bytes 8-11 (for 3 DWORD header) or bytes 12-15 (for 4 DWORD header) of the outbound TLP header with the contents of the LWR_TARGET_RW.." "LWR_TARGET_RW in the..,LWR_TARGET_RW in the.." newline bitfld.long 0x0 22. "INHIBIT_PAYLOAD,Inhibit TLP Payload Data for TLP's in Matched Region; assign iATU region to be TLP without data. When enabled and region address is matched the iATU marks all TLPs as having no payload data by forcing the TLP header Fmt[1] bit =0.." "Fmt[1] =0/1 so that TLPs with or without data..,Fmt[1] =0 so that only TLP type without data is.." newline bitfld.long 0x0 21. "TLP_HEADER_FIELDS_BYPASS,TLP Header Fields Translation Bypass. In this mode header fields of the translated TLP is taken from your application transmit interface or if AMBA is configured from the AMBA sideband bus (slv_awmisc_info) and not from the.." "0,1" newline bitfld.long 0x0 20. "SNP,Serialize Non-Posted Requests. In this mode when the AXI Bridge is populated same AXI ID Non-Posted Read/Write Requests are transmitted on the wire if there are no other same ID Non-Posted Requests outstanding. Note: This register field is sticky." "0,1" newline bitfld.long 0x0 19. "FUNC_BYPASS,Function Number Translation Bypass. In this mode the function number of the translated TLP is taken from your application transmit interface and not from the CTRL_1_FUNC_NUM field of the 'iATU Control 1 Register' or the VF_NUMBER field of.." "0,1" newline bitfld.long 0x0 16. "TAG_SUBSTITUTE_EN,TAG Substitute Enable. When enabled and region address is matched the iATU substitutes the TAG field of the outbound TLP header with the contents of the TAG field in this register. The expected usage scenario is translation from AXI.." "0,1" newline hexmask.long.byte 0x0 8.--15. 1. "TAG,TAG. The substituted TAG field (byte 6) in the outgoing TLP header when TAG_SUBSTITUTE_EN is set. Note: This register field is sticky." newline hexmask.long.byte 0x0 0.--7. 1. "MSG_CODE,MSG TLPs (Message Code). When the address of an outbound TLP is matched to this region and the translated TLP TYPE field is Msg or MsgD; then the message field of the TLP is changed to the value in this register. Memory TLPs: (ST;Steering Tag)." repeat.end repeat 8. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 )(list 0x0 0x200 0x400 0x600 0x800 0xA00 0xC00 0xE00 ) group.long ($2+0x8+0xC0000)++0x3 line.long 0x0 "IATU_LWR_BASE_ADDR_OFF_OUTBOUND_$1,iATU Lower Base Address Register. The CX_ATU_MIN_REGION_SIZE configuration parameter (Value Range: 4 kB. 8 kB. 16 kB. 32 kB. 64 kB defaults to 64 kB) specifies the minimum size of an address translation region. For.." hexmask.long.tbyte 0x0 12.--31. 1. "LWR_BASE_RW,Forms bits [31:n] of the start address of the address region to be translated. n is log2(CX_ATU_MIN_REGION_SIZE) Note: This register field is sticky." newline hexmask.long.word 0x0 0.--11. 1. "LWR_BASE_HW,Forms bits [n-1:0] of the start address of the address region to be translated. The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary so these bits are always 0. A write to this location is ignored by the PCIe controller." repeat.end repeat 8. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 )(list 0x0 0x200 0x400 0x600 0x800 0xA00 0xC00 0xE00 ) group.long ($2+0xC+0xC0000)++0x3 line.long 0x0 "IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_$1,iATU Upper Base Address Register." hexmask.long 0x0 0.--31. 1. "UPPER_BASE_RW,Forms bits [63:32] of the start (and end) address of the address region to be translated. In systems with a 32-bit address space this register is not used and therefore writing to this register has no effect. Note: This register field is.." repeat.end repeat 8. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 )(list 0x0 0x200 0x400 0x600 0x800 0xA00 0xC00 0xE00 ) group.long ($2+0x10+0xC0000)++0x3 line.long 0x0 "IATU_LIMIT_ADDR_OFF_OUTBOUND_$1,iATU Limit Address Register." hexmask.long.tbyte 0x0 12.--31. 1. "LIMIT_ADDR_RW,Forms upper bits of the end address of the address region to be translated. Note: This register field is sticky." newline hexmask.long.word 0x0 0.--11. 1. "LIMIT_ADDR_HW,Forms lower bits of the end address of the address region to be translated. The end address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary so these bits are always all ones. A write to this location is ignored by the PCIe.." repeat.end repeat 8. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 )(list 0x0 0x200 0x400 0x600 0x800 0xA00 0xC00 0xE00 ) group.long ($2+0x14+0xC0000)++0x3 line.long 0x0 "IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_$1,iATU Lower Target Address Register." hexmask.long 0x0 0.--31. 1. "LWR_TARGET_RW_OUTBOUND,When HEADER_SUBSTITUTE_EN in IATU_REGION_CTRL_2_OFF_OUTBOUND_ is '0' (normal operation): - LWR_TARGET_RW[31:n] forms MSB's of the Lower Target part of the new address of the translated region; - LWR_TARGET_RW[n-1:0] are not used." repeat.end repeat 8. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 )(list 0x0 0x200 0x400 0x600 0x800 0xA00 0xC00 0xE00 ) group.long ($2+0x18+0xC0000)++0x3 line.long 0x0 "IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_$1,iATU Upper Target Address Register." hexmask.long 0x0 0.--31. 1. "UPPER_TARGET_RW,Forms bits [63:32] of the start address (Upper Target part) of the new address of the translated region. Note: This register field is sticky." repeat.end repeat 8. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 )(list 0x0 0x200 0x400 0x600 0x800 0xA00 0xC00 0xE00 ) group.long ($2+0x1C+0xC0000)++0x3 line.long 0x0 "IATU_REGION_CTRL_3_OFF_OUTBOUND_$1,iATU Region Control 3 Register." bitfld.long 0x0 31. "VF_ACTIVE,Virtual Function Active. Indicates that all of the outbound accesses are from virtual functions. For more details see VF_ACTIVE field. Note: This register field is sticky." "0,1" newline hexmask.long 0x0 3.--30. 1. "RSVDP_VF_NUMBER,Reserved for future use." newline bitfld.long 0x0 0.--2. "VF_NUMBER,Virtual Function Number. When the address of an outbound TLP is matched to this region and the FUNC_BYPASS field in the 'iATU Control 2 Register' is '0' then this field used in generating the Function part of the requester ID (RID) field of.." "0,1,2,3,4,5,6,7" repeat.end repeat 8. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 )(list 0x0 0x200 0x400 0x600 0x800 0xA00 0xC00 0xE00 ) group.long ($2+0x100+0xC0000)++0x3 line.long 0x0 "IATU_REGION_CTRL_1_OFF_INBOUND_$1,iATU Region Control 1 Register." bitfld.long 0x0 20. "CTRL_1_FUNC_NUM,Function Number. - MEM-I/O: When the Address and BAR matching logic in the controller indicate that a MEM-I/O transaction matches a BAR in the function corresponding to this value then address translation proceeds. This check is only.." "?,When the destination function number as.." newline bitfld.long 0x0 13. "INCREASE_REGION_SIZE,Increase the maximum ATU Region size. When set the maximum ATU Region size is determined by CX_ATU_MAX_REGION_SIZE. When clear the maximum ATU Region size is 4 GB (default). Note: This register field is sticky." "0,1" newline bitfld.long 0x0 9.--10. "ATTR,When the ATTR field of an inbound TLP is matched to this value then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the 'ATTR Match Enable' bit of the 'iATU Control 2 Register' is.." "0,1,2,3" newline bitfld.long 0x0 8. "TD,When the TD field of an inbound TLP is matched to this value then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the 'TD Match Enable' bit of the 'iATU Control 2 Register' is set." "0,1" newline bitfld.long 0x0 5.--7. "TC,When the TC field of an inbound TLP is matched to this value then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the 'TC Match Enable' bit of the 'iATU Control 2 Register' is set." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x0 0.--4. 1. "TYPE,When the TYPE field of an inbound TLP is matched to this value then address translation proceeds (when all other enabled field-matches are successful). Note: This register field is sticky." repeat.end repeat 8. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 )(list 0x0 0x200 0x400 0x600 0x800 0xA00 0xC00 0xE00 ) group.long ($2+0x104+0xC0000)++0x3 line.long 0x0 "IATU_REGION_CTRL_2_OFF_INBOUND_$1,iATU Region Control 2 Register." bitfld.long 0x0 31. "REGION_EN,Region Enable. This bit must be set to '1' for address translation to take place. Note: This register field is sticky." "0,1" newline bitfld.long 0x0 30. "MATCH_MODE,Match Mode. Determines Inbound matching mode for TLPs. The mode depends on the type of TLP that is received as follows: For MEM-I/O TLPs this field is interpreted as follows: - 0: Address Match Mode. The iATU operates using addresses as in.." "Address Match Mode,Vendor ID Match Mode" newline bitfld.long 0x0 29. "INVERT_MODE,Invert Mode. When set the address matching region is inverted. Therefore an address match occurs when the untranslated address is in the region outside the defined range (Base Address to Limit Address). Note: This register field is sticky." "0,1" newline bitfld.long 0x0 28. "CFG_SHIFT_MODE,CFG Shift Mode. This is useful for CFG transactions where the PCIe configuration mechanism maps bits [27:12] of the address to the bus/device and function number. This allows a CFG configuration space to be located in any 256MB window of.." "0,1" newline bitfld.long 0x0 27. "FUZZY_TYPE_MATCH_CODE,Fuzzy Type Match Mode. When enabled the iATU relaxes the matching of the TLP TYPE field against the expected TYPE field so that - CfgRd0 and CfgRd1 TLPs are seen as identical. Similarly with CfgWr0 and CfgWr1. - MWr MRd and MRdLk.." "0,1" newline bitfld.long 0x0 26. "VFBAR_MATCH_MODE_EN,VF BAR Match Mode enable. When set Virtual Function BAR matching is used which allows all VFs in a PF which match a BAR to be matched with a single ATU region. Note: This register field is sticky." "0,1" newline bitfld.long 0x0 24.--25. "RESPONSE_CODE,Response Code. Defines the type of response to give for accesses matching this region. This overrides the normal RADM filter response. Note that this feature is not available for any region where Single Address Location Translate is.." "Normal RADM filter response is used,Unsupported request,?,?" newline bitfld.long 0x0 23. "SINGLE_ADDR_LOC_TRANS_EN,Single Address Location Translate Enable. When enabled Rx TLPs can be translated to a single address location as determined by the target address register of the iATU region. The main usage scenario is translation of Messages.." "0,1" newline bitfld.long 0x0 21. "MSG_CODE_MATCH_EN,Message Code Match Enable (Msg TLPS). Ensures that a successful message Code TLP field comparison match (see Message Code field of the 'iATU Control 2 Register') occurs (in MSG transactions) for address translation to proceed. ST Match.." "0,1" newline bitfld.long 0x0 20. "VF_MATCH_EN,Virtual Function Number Match Enable. Ensures that a successful Virtual Function Number TLP field comparison match (see Virtual Function Number field of the 'iATU Control 3 Register') occurs (in MEM-I/O transactions) for address translation.." "0,1" newline bitfld.long 0x0 19. "FUNC_NUM_MATCH_EN,Function Number Match Enable. Ensures that a successful Function Number TLP field comparison match (see Function Number field of the 'iATU Control 1 Register') occurs (in MEM-I/O and CFG0/CFG1 transactions) for address translation to.." "0,1" newline bitfld.long 0x0 16. "ATTR_MATCH_EN,ATTR Match Enable. Ensures that a successful ATTR TLP field comparison match (see ATTR field of the 'iATU Control 1 Register') occurs for address translation to proceed. Note: This register field is sticky." "0,1" newline bitfld.long 0x0 15. "TD_MATCH_EN,TD Match Enable. Ensures that a successful TD TLP field comparison match (see TD field of the 'iATU Control 1 Register') occurs for address translation to proceed. Note: This register field is sticky." "0,1" newline bitfld.long 0x0 14. "TC_MATCH_EN,TC Match Enable. Ensures that a successful TC TLP field comparison match (see TC field of the 'iATU Control 1 Register') occurs for address translation to proceed. Note: This register field is sticky." "0,1" newline bitfld.long 0x0 13. "MSG_TYPE_MATCH_MODE,Message Type Match Mode. When enabled and if single address location translate enable is set then inbound TLPs of type MSG/MSGd which match the type field of the iatu_region_ctrl_1_OFF_inbound register (=>TYPE[4:3]=2'b10) will be.." "0,1" newline bitfld.long 0x0 8.--10. "BAR_NUM,BAR Number. When the BAR number of an inbound MEM or IO TLP ' that is matched by the normal internal BAR address matching mechanism ' is the same as this field address translation proceeds (when all other enabled field-matches are successful)." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x0 0.--7. 1. "MSG_CODE,MSG TLPs: (Message Code). When the TYPE field of an inbound Msg/MsgD TLP is matched to this value then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the 'Message Code Match.." repeat.end repeat 8. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 )(list 0x0 0x200 0x400 0x600 0x800 0xA00 0xC00 0xE00 ) group.long ($2+0x108+0xC0000)++0x3 line.long 0x0 "IATU_LWR_BASE_ADDR_OFF_INBOUND_$1,iATU Lower Base Address Register. The CX_ATU_MIN_REGION_SIZE configuration parameter (Value Range: 4 kB. 8 kB. 16 kB. 32 kB. 64 kB defaults to 64 kB) specifies the minimum size of an address translation region. For.." hexmask.long.tbyte 0x0 12.--31. 1. "LWR_BASE_RW,Forms bits [31:n] of the start address of the address region to be translated. n is log2(CX_ATU_MIN_REGION_SIZE) Note: This register field is sticky." newline hexmask.long.word 0x0 0.--11. 1. "LWR_BASE_HW,Forms bits [n-1:0] of the start address of the address region to be translated. The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary so these bits are always 0. A write to this location is ignored by the PCIe controller." repeat.end repeat 8. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 )(list 0x0 0x200 0x400 0x600 0x800 0xA00 0xC00 0xE00 ) group.long ($2+0x10C+0xC0000)++0x3 line.long 0x0 "IATU_UPPER_BASE_ADDR_OFF_INBOUND_$1,iATU Upper Base Address Register." hexmask.long 0x0 0.--31. 1. "UPPER_BASE_RW,Forms bits [63:32] of the start (and end) address of the address region to be translated. Note: This register field is sticky." repeat.end repeat 8. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 )(list 0x0 0x200 0x400 0x600 0x800 0xA00 0xC00 0xE00 ) group.long ($2+0x110+0xC0000)++0x3 line.long 0x0 "IATU_LIMIT_ADDR_OFF_INBOUND_$1,iATU Limit Address Register." hexmask.long.tbyte 0x0 12.--31. 1. "LIMIT_ADDR_RW,Forms upper bits of the end address of the address region to be translated. Note: This register field is sticky." newline hexmask.long.word 0x0 0.--11. 1. "LIMIT_ADDR_HW,Forms lower bits of the end address of the address region to be translated. The end address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary so these bits are always all ones. A write to this location is ignored by the PCIe.." repeat.end repeat 8. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 )(list 0x0 0x200 0x400 0x600 0x800 0xA00 0xC00 0xE00 ) group.long ($2+0x114+0xC0000)++0x3 line.long 0x0 "IATU_LWR_TARGET_ADDR_OFF_INBOUND_$1,iATU Lower Target Address Register." hexmask.long.tbyte 0x0 12.--31. 1. "LWR_TARGET_RW,Forms MSB's of the Lower Target part of the new address of the translated region. These bits are always '0'. - Field size depends on log2(CX_ATU_MIN_REGION_SIZE) in address match mode. - Field size depends on log2(BAR_MASK+1) in BAR match.." newline hexmask.long.word 0x0 0.--11. 1. "LWR_TARGET_HW,Forms the LSB's of the Lower Target part of the new address of the translated region. The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary (in address match mode); and to the Bar size boundary (in BAR match mode) so.." repeat.end repeat 8. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 )(list 0x0 0x200 0x400 0x600 0x800 0xA00 0xC00 0xE00 ) group.long ($2+0x118+0xC0000)++0x3 line.long 0x0 "IATU_UPPER_TARGET_ADDR_OFF_INBOUND_$1,iATU Upper Target Address Register." hexmask.long 0x0 0.--31. 1. "UPPER_TARGET_RW,Forms bits [63:32] of the start address (Upper Target part) of the new address of the translated region. In systems with a 32-bit address space this register is not used and therefore writing to this register has no effect. Note: This.." repeat.end repeat 8. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 )(list 0x0 0x200 0x400 0x600 0x800 0xA00 0xC00 0xE00 ) group.long ($2+0x11C+0xC0000)++0x3 line.long 0x0 "IATU_REGION_CTRL_3_OFF_INBOUND_$1,iATU Region Control 3 Register." rbitfld.long 0x0 31. "VF_ACTIVE,Reserved. Not used." "0,1" newline hexmask.long 0x0 3.--30. 1. "RSVDP_VF_NUMBER,Reserved for future use." newline bitfld.long 0x0 0.--2. "VF_NUMBER,Virtual Function Number. When the Address and BAR matching logic in the controller indicates that a MEM-I/O transaction matches a BAR in the virtual function corresponding to this value then address translation proceeds. This check is only.." "0,1,2,3,4,5,6,7" repeat.end tree.end tree "PF0_PORT_LOGIC (Port Logic)" group.long (0x0+0x700)++0x27 line.long 0x0 "ACK_LATENCY_TIMER_OFF,Ack Latency Timer and Replay Timer Register." hexmask.long.word 0x0 16.--31. 1. "REPLAY_TIME_LIMIT,Replay Timer Limit. The replay timer expires when it reaches this limit. The controller initiates a replay upon reception of a NAK or when the replay timer expires. For more details see 'Transmit Replay'. You can modify the effective.." newline hexmask.long.word 0x0 0.--15. 1. "ROUND_TRIP_LATENCY_TIME_LIMIT,Ack Latency Timer Limit. The Ack latency timer expires when it reaches this limit. For more details see 'Ack Scheduling'. You can modify the effective timer limit with the TIMER_MOD_ACK_NAK field of the.." line.long 0x4 "VENDOR_SPEC_DLLP_OFF,Vendor Specific DLLP Register." hexmask.long 0x4 0.--31. 1. "VENDOR_SPEC_DLLP,Vendor Specific DLLP Register. Used to send a specific PCI Express DLLP. Your application writes the 8-bit DLLP Type and 24-bits of Payload data into this register then sets the field VENDOR_SPECIFIC_DLLP_REQ of PORT_LINK_CTRL_OFF to.." line.long 0x8 "PORT_FORCE_OFF,Port Force Link Register." hexmask.long.byte 0x8 24.--31. 1. "RSVDP_24,Reserved for future use." newline bitfld.long 0x8 23. "DO_DESKEW_FOR_SRIS,Use the transitions from TS2 to Logical Idle Symbol SKP OS to Logical Idle Symbol EIEOS to Logical Idle Symbol and FTS Sequence to SKP OS to do deskew instead of using received SKP OS or TS1 to TS2 transition if DO_DESKEW_FOR_SRIS.." "0,1" newline rbitfld.long 0x8 22. "RSVDP_22,Reserved for future use." "0,1" newline hexmask.long.byte 0x8 16.--21. 1. "LINK_STATE,Forced LTSSM State. The LTSSM state that the controller is forced to when you set the FORCE_EN bit (Force Link). LTSSM state encoding is defined by the lts_state variable in workspace/src/Layer1/smlh_ltssm.v. Note: This register field is sticky." newline bitfld.long 0x8 15. "FORCE_EN,Force Link. The controller supports a testing and debug capability to allow your software to force the LTSSM state machine into a specific state and to force the controller to transmit a specific Link Command. Asserting this bit triggers the.." "0,1" newline rbitfld.long 0x8 12.--14. "RSVDP_12,Reserved for future use." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x8 8.--11. 1. "FORCED_LTSSM,Forced Link Command. The link command that the controller is forced to transmit when you set FORCE_EN bit (Force Link). Link command encoding is defined by the ltssm_cmd variable in workspace/src/Layer1/smlh_ltssm.v. Note: This register.." newline hexmask.long.byte 0x8 0.--7. 1. "LINK_NUM,Link Number. Not used for endpoint. Not used for M-PCIe. Note: This register field is sticky." line.long 0xC "ACK_F_ASPM_CTRL_OFF,Ack Frequency and L0-L1 ASPM Control Register." rbitfld.long 0xC 31. "RSVDP_31,Reserved for future use." "0,1" newline bitfld.long 0xC 30. "ENTER_ASPM,ASPM L1 Entry Control. - 1: Controller enters ASPM L1 after a period in which it has been idle. - 0: Controller enters ASPM L1 only after idle period during which both receive and transmit are in L0s. Note: This register field is sticky." "Controller enters ASPM L1 only after idle period..,Controller enters ASPM L1 after a period in.." newline bitfld.long 0xC 27.--29. "L1_ENTRANCE_LATENCY,L1 Entrance Latency. Value range is: - 000: 1 us - 001: 2 us - 010: 4 us - 011: 8 us - 100: 16 us - 101: 32 us - 110 or 111: 64 us Note: Programming this timer with a value greater that 32us has no effect unless extended sync is used.." "0,1,2,3,4,5,6,7" newline bitfld.long 0xC 24.--26. "L0S_ENTRANCE_LATENCY,L0s Entrance Latency. Values correspond to: - 000: 1 us - 001: 2 us - 010: 3 us - 011: 4 us - 100: 5 us - 101: 6 us - 110 or 111: 7 us This field is applicable to STALL while in L0 for M-PCIe. Note: This register field is sticky." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0xC 16.--23. 1. "COMMON_CLK_N_FTS,Common Clock N_FTS. This is the N_FTS when common clock is used. The number of Fast Training Sequence ordered sets to be transmitted when transitioning from L0s to L0. The maximum number of FTS ordered-sets that a component can request.." newline hexmask.long.byte 0xC 8.--15. 1. "ACK_N_FTS,N_FTS. The number of Fast Training Sequence ordered sets to be transmitted when transitioning from L0s to L0. The maximum number of FTS ordered-sets that a component can request is 255. The controller does not support a value of zero; a value.." newline hexmask.long.byte 0xC 0.--7. 1. "ACK_FREQ,Ack Frequency. The controller accumulates the number of pending ACKs specified here (up to 255) before scheduling an ACK DLLP. - 0: Indicates that this Ack Frequency Counter feature is turned off. The controller generates a low-priority ACK.." line.long 0x10 "PORT_LINK_CTRL_OFF,Port Link Control Register." hexmask.long.byte 0x10 28.--31. 1. "RSVDP_28,Reserved for future use." newline bitfld.long 0x10 27. "TRANSMIT_LANE_REVERSALE_ENABLE,TRANSMIT_LANE_REVERSALE_ENABLE is an internally reserved field. Do not use. Note: This register field is sticky." "0,1" newline bitfld.long 0x10 26. "EXTENDED_SYNCH,EXTENDED_SYNCH is an internally reserved field. Do not use. Note: This register field is sticky." "0,1" newline bitfld.long 0x10 25. "CORRUPT_LCRC_ENABLE,CORRUPT_LCRC_ENABLE is an internally reserved field. Do not use. Note: This register field is sticky." "0,1" newline bitfld.long 0x10 24. "BEACON_ENABLE,BEACON_ENABLE is an internally reserved field. Do not use. Note: This register field is sticky." "0,1" newline hexmask.long.byte 0x10 16.--21. 1. "LINK_CAPABLE,Link Mode Enable. Sets the number of lanes in the link that you want to connect to the link partner. When you have unused lanes in your system then you must change the value in this register to reflect the number of lanes. You must also.." newline hexmask.long.byte 0x10 12.--15. 1. "RSVDP_12,Reserved for future use." newline hexmask.long.byte 0x10 8.--11. 1. "LINK_RATE,LINK_RATE is an internally reserved field. Do not use. Note: This register field is sticky." newline bitfld.long 0x10 7. "FAST_LINK_MODE,Fast Link Mode. Sets all internal LTSSM millisecond timers to Fast Mode for speeding up simulation. Forces the LTSSM training (link initialization) to use shorter time-outs and to link up faster. The default scaling factor can be changed.." "0,1" newline bitfld.long 0x10 6. "LINK_DISABLE,LINK_DISABLE is an internally reserved field. Do not use. Note: This register field is sticky." "0,1" newline bitfld.long 0x10 5. "DLL_LINK_EN,DLL Link Enable. Enables link initialization. When DLL Link Enable =0 the controller does not transmit InitFC DLLPs and does not establish a link. Note: This register field is sticky." "0,1" newline rbitfld.long 0x10 4. "RSVDP_4,Reserved for future use." "0,1" newline bitfld.long 0x10 3. "RESET_ASSERT,Reset Assert. Triggers a recovery and forces the LTSSM to the hot reset state (downstream port only). Note: This register field is sticky." "0,1" newline bitfld.long 0x10 2. "LOOPBACK_ENABLE,Loopback Enable. Turns on loopback. For more details see 'Loopback'. For M-PCIe to force the master to enter Digital Loopback mode you must set this field to '1' during Configuration.start state(initial discovery/configuration). M-PCIe.." "0,1" newline bitfld.long 0x10 1. "SCRAMBLE_DISABLE,Scramble Disable. Turns off data scrambling. Note: This register field is sticky." "0,1" newline bitfld.long 0x10 0. "VENDOR_SPECIFIC_DLLP_REQ,Vendor Specific DLLP Request. When software writes a '1' to this bit the controller transmits the DLLP contained in the VENDOR_SPEC_DLLP field of VENDOR_SPEC_DLLP_OFF. Reading from this self-clearing register field always.." "0,1" line.long 0x14 "LANE_SKEW_OFF,Lane Skew Register." bitfld.long 0x14 31. "DISABLE_LANE_TO_LANE_DESKEW,Disable Lane-to-Lane Deskew. Causes the controller to disable the internal Lane-to-Lane deskew logic. Note: This register field is sticky." "0,1" newline hexmask.long.byte 0x14 27.--30. 1. "IMPLEMENT_NUM_LANES,Implementation-specific Number of Lanes. Set the implementation-specific number of lanes. Allowed values are: - 4'b0000: 1 lane - 4'b0001: 2 lanes - 4'b0011: 4 lanes - 4'b0111: 8 lanes - 4'b1111: 16 lanes The number of lanes to be.." newline bitfld.long 0x14 26. "ELASTIC_BUFFER_MODE,Selects Elasticity Buffer operating mode: 0: Nominal Half Full Buffer mode 1: Nominal Empty Buffer Mode Note: This register field is sticky." "Nominal Half Full Buffer mode,Nominal Empty Buffer Mode" newline bitfld.long 0x14 25. "ACK_NAK_DISABLE,Ack/Nak Disable. Prevents the controller from sending ACK and NAK DLLPs. Note: This register field is sticky." "0,1" newline bitfld.long 0x14 24. "FLOW_CTRL_DISABLE,Flow Control Disable. Prevents the controller from sending FC DLLPs. Note: This register field is sticky." "0,1" newline hexmask.long.tbyte 0x14 0.--23. 1. "INSERT_LANE_SKEW,INSERT_LANE_SKEW is an internally reserved field. Do not use. Note: This register field is sticky." line.long 0x18 "TIMER_CTRL_MAX_FUNC_NUM_OFF,Timer Control and Max Function Number Register." rbitfld.long 0x18 31. "RSVDP_31,Reserved for future use." "0,1" newline bitfld.long 0x18 29.--30. "FAST_LINK_SCALING_FACTOR,Fast Link Timer Scaling Factor. Sets the scaling factor of LTSSM timer when FAST_LINK_MODE field in PORT_LINK_CTRL_OFF is set to '1'. - 0: Scaling Factor is 1024 (1ms is 1us *a) - 1: Scaling Factor is 256 (1ms is 4us) - 2:.." "Scaling Factor is 1024,Scaling Factor is 256,Scaling Factor is 64,Scaling Factor is 16" newline hexmask.long.byte 0x18 24.--28. 1. "UPDATE_FREQ_TIMER,UPDATE_FREQ_TIMER is an internally reserved field. Do not use. Note: This register field is sticky." newline hexmask.long.byte 0x18 19.--23. 1. "TIMER_MOD_ACK_NAK,Ack Latency Timer Modifier. Increases the timer value for the Ack latency timer in increments of 64 clock cycles. A value of '0' represents no modification to the timer value. For more details see the ROUND_TRIP_LATENCY_TIME_LIMIT.." newline hexmask.long.byte 0x18 14.--18. 1. "TIMER_MOD_REPLAY_TIMER,Replay Timer Limit Modifier. Increases the time-out value for the replay timer in increments of 64 clock cycles at Gen1 or Gen2 speed and in increments of 256 clock cycles at Gen3 speed. A value of '0' represents no modification.." newline hexmask.long.byte 0x18 8.--13. 1. "RSVDP_8,Reserved for future use." newline hexmask.long.byte 0x18 0.--7. 1. "MAX_FUNC_NUM,Maximum function number that can be used in a request. Configuration requests targeted at function numbers above this value are returned with UR (unsupported request). Note: This register field is sticky." line.long 0x1C "SYMBOL_TIMER_FILTER_1_OFF,Symbol Timer Register and Filter Mask 1 Register. The Filter Mask 1 Register modifies the RADM filtering and error handling rules. For more details. see the 'Receive Filtering' section. In each case. '0' applies the associated.." hexmask.long.word 0x1C 16.--31. 1. "MASK_RADM_1,Filter Mask 1. The Filter Mask 1 Register modifies the RADM filtering and error handling rules. For more details see the 'Receive Filtering' section. In each case '0' applies the associated filtering rule and '1' masks the associated.." newline bitfld.long 0x1C 15. "DISABLE_FC_WD_TIMER,Disable FC Watchdog Timer. Note: This register field is sticky." "0,1" newline hexmask.long.byte 0x1C 11.--14. 1. "EIDLE_TIMER,EIDLE_TIMER is an internally reserved field. Do not use. Note: This register field is sticky." newline hexmask.long.word 0x1C 0.--10. 1. "SKP_INT_VAL,SKP Interval Value. The number of symbol times to wait between transmitting SKP ordered sets. Note that the controller actually waits the number of symbol times in this register plus 1 between transmitting SKP ordered sets. Your application.." line.long 0x20 "FILTER_MASK_2_OFF,Filter Mask 2 Register. This register modifies the RADM filtering and error handling rules. For more details. see the 'Receive Filtering' section. In each case. '0' applies the associated filtering rule and '1' masks the associated.." hexmask.long 0x20 0.--31. 1. "MASK_RADM_2,Filter Mask 2. This field modifies the RADM filtering and error handling rules. For more details see the 'Receive Filtering' section. In each case '0' applies the associated filtering rule and '1' masks the associated filtering rule." line.long 0x24 "AMBA_MUL_OB_DECOMP_NP_SUB_REQ_CTRL_OFF,AMBA Multiple Outbound Decomposed NP SubRequests Control Register." hexmask.long 0x24 1.--31. 1. "RSVDP_1,Reserved for future use." newline bitfld.long 0x24 0. "OB_RD_SPLIT_BURST_EN,Enable AMBA Multiple Outbound Decomposed NP SubRequests. This bit when set to '0' disables the possibility of having multiple outstanding non-posted requests that were derived from decomposition of an outbound AMBA request. For more.." "0,1" rgroup.long (0x28+0x700)++0x13 line.long 0x0 "PL_DEBUG0_OFF,Debug Register 0" hexmask.long 0x0 0.--31. 1. "DEB_REG_0,The value on cxpl_debug_info[31:0]." line.long 0x4 "PL_DEBUG1_OFF,Debug Register 1" hexmask.long 0x4 0.--31. 1. "DEB_REG_1,The value on cxpl_debug_info[63:32]." line.long 0x8 "TX_P_FC_CREDIT_STATUS_OFF,Transmit Posted FC Credit Status" hexmask.long.word 0x8 20.--31. 1. "RSVDP_TX_P_FC_CREDIT_STATUS,Reserved for future use." newline hexmask.long.byte 0x8 12.--19. 1. "TX_P_HEADER_FC_CREDIT,Transmit Posted Header FC Credits. The posted Header credits advertised by the receiver at the other end of the link updated with each UpdateFC DLLP. Default value depends on the number of advertised credits for header and data.." newline hexmask.long.word 0x8 0.--11. 1. "TX_P_DATA_FC_CREDIT,Transmit Posted Data FC Credits. The posted Data credits advertised by the receiver at the other end of the link updated with each UpdateFC DLLP. Default value depends on the number of advertised credits for header and data Scaled.." line.long 0xC "TX_NP_FC_CREDIT_STATUS_OFF,Transmit Non-Posted FC Credit Status" hexmask.long.word 0xC 20.--31. 1. "RSVDP_TX_NP_FC_CREDIT_STATUS,Reserved for future use." newline hexmask.long.byte 0xC 12.--19. 1. "TX_NP_HEADER_FC_CREDIT,Transmit Non-Posted Header FC Credits. The non-posted Header credits advertised by the receiver at the other end of the link updated with each UpdateFC DLLP. Default value depends on the number of advertised credits for header and.." newline hexmask.long.word 0xC 0.--11. 1. "TX_NP_DATA_FC_CREDIT,Transmit Non-Posted Data FC Credits. The non-posted Data credits advertised by the receiver at the other end of the link updated with each UpdateFC DLLP. Default value depends on the number of advertised credits for header and data.." line.long 0x10 "TX_CPL_FC_CREDIT_STATUS_OFF,Transmit Completion FC Credit Status" hexmask.long.word 0x10 20.--31. 1. "RSVDP_TX_CPL_FC_CREDIT_STATUS,Reserved for future use." newline hexmask.long.byte 0x10 12.--19. 1. "TX_CPL_HEADER_FC_CREDIT,Transmit Completion Header FC Credits. The Completion Header credits advertised by the receiver at the other end of the link updated with each UpdateFC DLLP. Default value depends on the number of advertised credits for header.." newline hexmask.long.word 0x10 0.--11. 1. "TX_CPL_DATA_FC_CREDIT,Transmit Completion Data FC Credits. The Completion Data credits advertised by the receiver at the other end of the link updated with each UpdateFC DLLP. Default value depends on the number of advertised credits for header and data.." group.long (0x3C+0x700)++0x3 line.long 0x0 "QUEUE_STATUS_OFF,Queue Status" bitfld.long 0x0 31. "TIMER_MOD_FLOW_CONTROL_EN,FC Latency Timer Override Enable. When this bit is set the value from the 'FC Latency Timer Override Value' field in this register will override the FC latency timer value that the controller calculates according to the PCIe.." "0,1" newline rbitfld.long 0x0 29.--30. "RSVDP_29,Reserved for future use." "0,1,2,3" newline hexmask.long.word 0x0 16.--28. 1. "TIMER_MOD_FLOW_CONTROL,FC Latency Timer Override Value. When you set the 'FC Latency Timer Override Enable' in this register the value in this field will override the FC latency timer value that the controller calculates according to the PCIe.." newline rbitfld.long 0x0 13. "RX_SERIALIZATION_Q_NON_EMPTY,Receive Serialization Queue Not Empty. Indicates there is data in the serialization queue." "0,1" newline hexmask.long.word 0x0 4.--12. 1. "RSVDP_4,Reserved for future use." newline bitfld.long 0x0 3. "RX_QUEUE_OVERFLOW,Receive Credit Queue Overflow. Indicates insufficient buffer space available to write to the P/NP/CPL credit queue." "0,1" newline rbitfld.long 0x0 2. "RX_QUEUE_NON_EMPTY,Receive Credit Queue Not Empty. Indicates there is data in one or more of the receive buffers." "0,1" newline rbitfld.long 0x0 1. "TX_RETRY_BUFFER_NE,Transmit Retry Buffer Not Empty. Indicates that there is data in the transmit retry buffer." "0,1" newline rbitfld.long 0x0 0. "RX_TLP_FC_CREDIT_NON_RETURN,Received TLP FC Credits Not Returned. Indicates that the controller has received a TLP but has not yet sent an UpdateFC DLLP indicating that the credits for that TLP have been restored by the receiver at the other end of the.." "0,1" rgroup.long (0x40+0x700)++0x7 line.long 0x0 "VC_TX_ARBI_1_OFF,VC Transmit Arbitration Register 1" hexmask.long.byte 0x0 24.--31. 1. "WRR_WEIGHT_VC_3,WRR Weight for VC3. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R" newline hexmask.long.byte 0x0 16.--23. 1. "WRR_WEIGHT_VC_2,WRR Weight for VC2. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R" newline hexmask.long.byte 0x0 8.--15. 1. "WRR_WEIGHT_VC_1,WRR Weight for VC1. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R" newline hexmask.long.byte 0x0 0.--7. 1. "WRR_WEIGHT_VC_0,WRR Weight for VC0. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R" line.long 0x4 "VC_TX_ARBI_2_OFF,VC Transmit Arbitration Register 2" hexmask.long.byte 0x4 24.--31. 1. "WRR_WEIGHT_VC_7,WRR Weight for VC7. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R" newline hexmask.long.byte 0x4 16.--23. 1. "WRR_WEIGHT_VC_6,WRR Weight for VC6. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R" newline hexmask.long.byte 0x4 8.--15. 1. "WRR_WEIGHT_VC_5,WRR Weight for VC5. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R" newline hexmask.long.byte 0x4 0.--7. 1. "WRR_WEIGHT_VC_4,WRR Weight for VC4. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R" group.long (0x48+0x700)++0xB line.long 0x0 "VC0_P_RX_Q_CTRL_OFF,Segmented-Buffer VC0 Posted Receive Queue Control." bitfld.long 0x0 31. "VC_ORDERING_RX_Q,VC Ordering for Receive Queues. Determines the VC ordering rule for the receive queues used only in the segmented-buffer configuration: - 1: Strict ordering higher numbered VCs have higher priority - 0: Round robin Note: This register.." "Round robin,Strict ordering" newline bitfld.long 0x0 30. "TLP_TYPE_ORDERING_VC0,TLP Type Ordering for VC0. Determines the TLP type ordering rule for VC0 receive queues used only in the segmented-buffer configuration: - 1: PCIe ordering rules (recommended) - 0: Strict ordering: posted completion then.." "Strict ordering: posted,PCIe ordering rules" newline bitfld.long 0x0 28.--29. "RESERVED5,Reserved. Note: This register field is sticky." "0,1,2,3" newline bitfld.long 0x0 26.--27. "VC0_P_DATA_SCALE,VC0 Scale Posted Data Credites. Note: This register field is sticky." "0,1,2,3" newline bitfld.long 0x0 24.--25. "VC0_P_HDR_SCALE,VC0 Scale Posted Header Credites. Note: This register field is sticky." "0,1,2,3" newline bitfld.long 0x0 21.--23. "VC0_P_TLP_Q_MODE,Reserved. Note: This register field is sticky." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 20. "RESERVED4,Reserved. Note: This register field is sticky." "0,1" newline hexmask.long.byte 0x0 12.--19. 1. "VC0_P_HEADER_CREDIT,VC0 Posted Header Credits. The number of initial posted header credits for VC0 used only in the segmented-buffer configuration. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R (sticky) Note: This.." newline hexmask.long.word 0x0 0.--11. 1. "VC0_P_DATA_CREDIT,VC0 Posted Data Credits. The number of initial posted data credits for VC0 used only in the segmented-buffer configuration. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R (sticky) Note: This.." line.long 0x4 "VC0_NP_RX_Q_CTRL_OFF,Segmented-Buffer VC0 Non-Posted Receive Queue Control." hexmask.long.byte 0x4 28.--31. 1. "RESERVED7,Reserved. Note: This register field is sticky." newline bitfld.long 0x4 26.--27. "VC0_NP_DATA_SCALE,VC0 Scale Non-Posted Data Credites. Note: This register field is sticky." "0,1,2,3" newline bitfld.long 0x4 24.--25. "VC0_NP_HDR_SCALE,VC0 Scale Non-Posted Header Credites. Note: This register field is sticky." "0,1,2,3" newline bitfld.long 0x4 21.--23. "VC0_NP_TLP_Q_MODE,Reserved. Note: This register field is sticky." "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 20. "RESERVED6,Reserved. Note: This register field is sticky." "0,1" newline hexmask.long.byte 0x4 12.--19. 1. "VC0_NP_HEADER_CREDIT,VC0 Non-Posted Header Credits. The number of initial non-posted header credits for VC0 used only in the segmented-buffer configuration. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R (sticky).." newline hexmask.long.word 0x4 0.--11. 1. "VC0_NP_DATA_CREDIT,VC0 Non-Posted Data Credits. The number of initial non-posted data credits for VC0 used only in the segmented-buffer configuration. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R (sticky) Note:.." line.long 0x8 "VC0_CPL_RX_Q_CTRL_OFF,Segmented-Buffer VC0 Completion Receive Queue Control." hexmask.long.byte 0x8 28.--31. 1. "RESERVED9,Reserved. Note: This register field is sticky." newline bitfld.long 0x8 26.--27. "VC0_CPL_DATA_SCALE,VC0 Scale CPL Data Credites. Note: This register field is sticky." "0,1,2,3" newline bitfld.long 0x8 24.--25. "VC0_CPL_HDR_SCALE,VC0 Scale CPL Header Credites. Note: This register field is sticky." "0,1,2,3" newline bitfld.long 0x8 21.--23. "VC0_CPL_TLP_Q_MODE,Reserved. Note: This register field is sticky." "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 20. "RESERVED8,Reserved. Note: This register field is sticky." "0,1" newline hexmask.long.byte 0x8 12.--19. 1. "VC0_CPL_HEADER_CREDIT,VC0 Completion Header Credits. The number of initial Completion header credits for VC0 used only in the segmented-buffer configuration. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R (sticky).." newline hexmask.long.word 0x8 0.--11. 1. "VC0_CPL_DATA_CREDIT,VC0 Completion Data Credits. The number of initial Completion data credits for VC0 used only in the segmented-buffer configuration. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R (sticky) Note:.." group.long (0x10C+0x700)++0x3 line.long 0x0 "GEN2_CTRL_OFF,This register is used to control various functions of the controller related to link training. lane reversal. and equalization." rbitfld.long 0x0 31. "RSVDP_31,Reserved for future use." "0,1" newline bitfld.long 0x0 30. "FORCE_LANE_FLIP,Enable to force the LANE_UNDER_TEST physical lane flips to logical lane 0. All the other physical lanes are turned off. The LINK_CAPABLE register must be set to 1 and only x1 link can be formed if the FORCE_LANE_FLIP register is set to 1." "0,1" newline hexmask.long.byte 0x0 24.--27. 1. "LANE_UNDER_TEST,The Lane Under Test is the lane for Forced Lane Flip or for Loopback Eq. The value is from 0 to CX_NL. Only one lane is configured each time. The default of this field is the CX_DEFAULT_LANE_UNDER_TEST configuration parameter. This field.." newline rbitfld.long 0x0 22.--23. "RSVDP_22,Reserved for future use." "0,1,2,3" newline bitfld.long 0x0 21. "GEN1_EI_INFERENCE,Electrical Idle Inference Mode at Gen1 Rate. Programmable mode to determine inferred electrical idle (EI) in Recovery.Speed or Loopback.Active (as slave) state at Gen1 speed by looking for a '1' value on RxElecIdle instead of looking.." "Use RxElecIdle signal to infer Electrical Idle,Use RxValid signal to infer Electrical Idle" newline bitfld.long 0x0 20. "SEL_DEEMPHASIS,Used to set the de-emphasis level for upstream ports. This bit selects the level of de-emphasis the link operates at. - 0: -6 dB - 1: -3.5 dB This field is reserved (fixed to '0') for M-PCIe. Note: The access attributes of this field are.." "0,1" newline bitfld.long 0x0 19. "CONFIG_TX_COMP_RX,Config Tx Compliance Receive Bit. When set to 1 signals LTSSM to transmit TS ordered sets with the compliance receive bit assert (equal to '1'). This field is reserved (fixed to '0') for M-PCIe. Note: The access attributes of this.." "0,1" newline bitfld.long 0x0 18. "CONFIG_PHY_TX_CHANGE,Config PHY Tx Swing. Controls the PHY transmitter voltage swing level. The controller drives the mac_phy_txswing output from this register bit field. - 0: Full Swing - 1: Low Swing This field is reserved (fixed to '0') for M-PCIe." "Full Swing,Low Swing" newline bitfld.long 0x0 17. "DIRECT_SPEED_CHANGE,Directed Speed Change. Writing '1' to this field instructs the LTSSM to initiate a speed change to Gen2 or Gen3 after the link is initialized at Gen1 speed. When the speed change occurs the controller will clear the contents of this.." "0,1" newline bitfld.long 0x0 16. "AUTO_LANE_FLIP_CTRL_EN,Enable Auto flipping of the lanes. You must set the CX_AUTO_LANE_FLIP_CTRL_EN configuration parameter to include the hardware for this feature in the controller. For more details see the 'Lane Reversal' appendix in the Databook." "0,1" newline bitfld.long 0x0 13.--15. "PRE_DET_LANE,Predetermined Lane for Auto Flip. This field defines which physical lane is connected to logical Lane0 by the flip operation performed in Detect. This field is used to restrict the receiver detect procedure to a particular lane when the.." "LANE0,LANE1,LANE3,LANE7,LANE15,?,?,?" newline hexmask.long.byte 0x0 8.--12. 1. "NUM_OF_LANES,Predetermined Number of Lanes. Defines the number of lanes which are connected and not bad. Used to limit the effective link width to ignore 'broken' or 'unused' lanes that detect a receiver. Indicates the number of lanes to check for exit.." newline hexmask.long.byte 0x0 0.--7. 1. "FAST_TRAINING_SEQ,Sets the Number of Fast Training Sequences (N_FTS) that the controller advertises as its N_FTS during Gen2 or Gen3 link training. This value is used to inform the link partner about the PHY's ability to recover synchronization after a.." rgroup.long (0x110+0x700)++0x3 line.long 0x0 "PHY_STATUS_OFF,PHY Status Register. Memory mapped register from phy_cfg_status GPIO input pins." hexmask.long 0x0 0.--31. 1. "PHY_STATUS,PHY Status. Data received directly from the phy_cfg_status bus. These is a GPIO register reflecting the values on the static phy_cfg_status input signals. The usage is left completely to the user and does not in any way influence controller.." group.long (0x114+0x700)++0x3 line.long 0x0 "PHY_CONTROL_OFF,PHY Control Register. Memory mapped register to cfg_phy_control GPIO output pins." hexmask.long 0x0 0.--31. 1. "PHY_CONTROL,PHY Control. Data sent directly to the cfg_phy_control bus. These is a GPIO register driving the values on the static cfg_phy_control output signals. The usage is left completely to the user and does not in any way influence controller.." group.long (0x11C+0x700)++0x77 line.long 0x0 "TRGT_MAP_CTRL_OFF,Programmable Target Map Control Register." hexmask.long.word 0x0 21.--31. 1. "TARGET_MAP_RESERVED_21_31,Reserved. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R (sticky)" newline hexmask.long.byte 0x0 16.--20. 1. "TARGET_MAP_INDEX,The number of the PF Function on which the Target Values are set. This register does not respect the Byte Enable setting. any write will affect all register bits." newline rbitfld.long 0x0 13.--15. "TARGET_MAP_RESERVED_13_15,Reserved. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R (sticky)" "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x0 7.--12. 1. "TARGET_MAP_VF,Target Values for each BAR on the VF Function selected by the index number. This register does not respect the Byte Enable setting. any write will affect all register bits." newline bitfld.long 0x0 6. "TARGET_MAP_ROM,Target Value for the ROM page of the PF Function selected by the index number. This register does not respect the Byte Enable setting. any write will affect all register bits." "0,1" newline hexmask.long.byte 0x0 0.--5. 1. "TARGET_MAP_PF,Target Values for each BAR on the PF Function selected by the index number. This register does not respect the Byte Enable setting. any write will affect all register bits." line.long 0x4 "MSI_CTRL_ADDR_OFF,Integrated MSI Reception Module (iMRM) Address Register." hexmask.long 0x4 0.--31. 1. "MSI_CTRL_ADDR,Integrated MSI Reception Module Address. System specified address for MSI memory write transaction termination. Within the AXI Bridge every received Memory Write request is examined to see if it targets the MSI Address that has been.." line.long 0x8 "MSI_CTRL_UPPER_ADDR_OFF,Integrated MSI Reception Module Upper Address Register." hexmask.long 0x8 0.--31. 1. "MSI_CTRL_UPPER_ADDR,Integrated MSI Reception Module Upper Address. System specified upper address for MSI memory write transaction termination. Allows functions to support a 64-bit MSI address. Note: This register field is sticky." line.long 0xC "MSI_CTRL_INT_0_EN_OFF,Integrated MSI Reception Module Interrupt#i Enable Register." hexmask.long 0xC 0.--31. 1. "MSI_CTRL_INT_0_EN,MSI Interrupt#i Enable. Specifies which interrupts are enabled. When an MSI is received from a disabled interrupt no status bit gets set in MSI controller interrupt status register. Each bit corresponds to a single MSI Interrupt.." line.long 0x10 "MSI_CTRL_INT_0_MASK_OFF,Integrated MSI Reception Module Interrupt#i Mask Register." hexmask.long 0x10 0.--31. 1. "MSI_CTRL_INT_0_MASK,MSI Interrupt#i Mask. Allows enabled interrupts to be masked. When an MSI is received for a masked interrupt the corresponding status bit gets set in the interrupt status register but the msi_ctrl_int output is not set HIGH. Each bit.." line.long 0x14 "MSI_CTRL_INT_0_STATUS_OFF,Integrated MSI Reception Module Interrupt#i Status Register." hexmask.long 0x14 0.--31. 1. "MSI_CTRL_INT_0_STATUS,MSI Interrupt#i Status. When an MSI is detected for EP#i one bit in this register is set. The decoding of the data payload of the MSI Memory Write request determines which bit gets set. A status is bit is cleared by writing a 1 to.." line.long 0x18 "MSI_CTRL_INT_1_EN_OFF,Integrated MSI Reception Module Interrupt#i Enable Register." hexmask.long 0x18 0.--31. 1. "MSI_CTRL_INT_1_EN,MSI Interrupt#i Enable. Specifies which interrupts are enabled. When an MSI is received from a disabled interrupt no status bit gets set in MSI controller interrupt status register. Each bit corresponds to a single MSI Interrupt.." line.long 0x1C "MSI_CTRL_INT_1_MASK_OFF,Integrated MSI Reception Module Interrupt#i Mask Register." hexmask.long 0x1C 0.--31. 1. "MSI_CTRL_INT_1_MASK,MSI Interrupt#i Mask. Allows enabled interrupts to be masked. When an MSI is received for a masked interrupt the corresponding status bit gets set in the interrupt status register but the msi_ctrl_int output is not set HIGH. Each bit.." line.long 0x20 "MSI_CTRL_INT_1_STATUS_OFF,Integrated MSI Reception Module Interrupt#i Status Register." hexmask.long 0x20 0.--31. 1. "MSI_CTRL_INT_1_STATUS,MSI Interrupt#i Status. When an MSI is detected for EP#i one bit in this register is set. The decoding of the data payload of the MSI Memory Write request determines which bit gets set. A status is bit is cleared by writing a 1 to.." line.long 0x24 "MSI_CTRL_INT_2_EN_OFF,Integrated MSI Reception Module Interrupt#i Enable Register." hexmask.long 0x24 0.--31. 1. "MSI_CTRL_INT_2_EN,MSI Interrupt#i Enable. Specifies which interrupts are enabled. When an MSI is received from a disabled interrupt no status bit gets set in MSI controller interrupt status register. Each bit corresponds to a single MSI Interrupt.." line.long 0x28 "MSI_CTRL_INT_2_MASK_OFF,Integrated MSI Reception Module Interrupt#i Mask Register." hexmask.long 0x28 0.--31. 1. "MSI_CTRL_INT_2_MASK,MSI Interrupt#i Mask. Allows enabled interrupts to be masked. When an MSI is received for a masked interrupt the corresponding status bit gets set in the interrupt status register but the msi_ctrl_int output is not set HIGH. Each bit.." line.long 0x2C "MSI_CTRL_INT_2_STATUS_OFF,Integrated MSI Reception Module Interrupt#i Status Register." hexmask.long 0x2C 0.--31. 1. "MSI_CTRL_INT_2_STATUS,MSI Interrupt#i Status. When an MSI is detected for EP#i one bit in this register is set. The decoding of the data payload of the MSI Memory Write request determines which bit gets set. A status is bit is cleared by writing a 1 to.." line.long 0x30 "MSI_CTRL_INT_3_EN_OFF,Integrated MSI Reception Module Interrupt#i Enable Register." hexmask.long 0x30 0.--31. 1. "MSI_CTRL_INT_3_EN,MSI Interrupt#i Enable. Specifies which interrupts are enabled. When an MSI is received from a disabled interrupt no status bit gets set in MSI controller interrupt status register. Each bit corresponds to a single MSI Interrupt.." line.long 0x34 "MSI_CTRL_INT_3_MASK_OFF,Integrated MSI Reception Module Interrupt#i Mask Register." hexmask.long 0x34 0.--31. 1. "MSI_CTRL_INT_3_MASK,MSI Interrupt#i Mask. Allows enabled interrupts to be masked. When an MSI is received for a masked interrupt the corresponding status bit gets set in the interrupt status register but the msi_ctrl_int output is not set HIGH. Each bit.." line.long 0x38 "MSI_CTRL_INT_3_STATUS_OFF,Integrated MSI Reception Module Interrupt#i Status Register." hexmask.long 0x38 0.--31. 1. "MSI_CTRL_INT_3_STATUS,MSI Interrupt#i Status. When an MSI is detected for EP#i one bit in this register is set. The decoding of the data payload of the MSI Memory Write request determines which bit gets set. A status is bit is cleared by writing a 1 to.." line.long 0x3C "MSI_CTRL_INT_4_EN_OFF,Integrated MSI Reception Module Interrupt#i Enable Register." hexmask.long 0x3C 0.--31. 1. "MSI_CTRL_INT_4_EN,MSI Interrupt#i Enable. Specifies which interrupts are enabled. When an MSI is received from a disabled interrupt no status bit gets set in MSI controller interrupt status register. Each bit corresponds to a single MSI Interrupt.." line.long 0x40 "MSI_CTRL_INT_4_MASK_OFF,Integrated MSI Reception Module Interrupt#i Mask Register." hexmask.long 0x40 0.--31. 1. "MSI_CTRL_INT_4_MASK,MSI Interrupt#i Mask. Allows enabled interrupts to be masked. When an MSI is received for a masked interrupt the corresponding status bit gets set in the interrupt status register but the msi_ctrl_int output is not set HIGH. Each bit.." line.long 0x44 "MSI_CTRL_INT_4_STATUS_OFF,Integrated MSI Reception Module Interrupt#i Status Register." hexmask.long 0x44 0.--31. 1. "MSI_CTRL_INT_4_STATUS,MSI Interrupt#i Status. When an MSI is detected for EP#i one bit in this register is set. The decoding of the data payload of the MSI Memory Write request determines which bit gets set. A status is bit is cleared by writing a 1 to.." line.long 0x48 "MSI_CTRL_INT_5_EN_OFF,Integrated MSI Reception Module Interrupt#i Enable Register." hexmask.long 0x48 0.--31. 1. "MSI_CTRL_INT_5_EN,MSI Interrupt#i Enable. Specifies which interrupts are enabled. When an MSI is received from a disabled interrupt no status bit gets set in MSI controller interrupt status register. Each bit corresponds to a single MSI Interrupt.." line.long 0x4C "MSI_CTRL_INT_5_MASK_OFF,Integrated MSI Reception Module Interrupt#i Mask Register." hexmask.long 0x4C 0.--31. 1. "MSI_CTRL_INT_5_MASK,MSI Interrupt#i Mask. Allows enabled interrupts to be masked. When an MSI is received for a masked interrupt the corresponding status bit gets set in the interrupt status register but the msi_ctrl_int output is not set HIGH. Each bit.." line.long 0x50 "MSI_CTRL_INT_5_STATUS_OFF,Integrated MSI Reception Module Interrupt#i Status Register." hexmask.long 0x50 0.--31. 1. "MSI_CTRL_INT_5_STATUS,MSI Interrupt#i Status. When an MSI is detected for EP#i one bit in this register is set. The decoding of the data payload of the MSI Memory Write request determines which bit gets set. A status is bit is cleared by writing a 1 to.." line.long 0x54 "MSI_CTRL_INT_6_EN_OFF,Integrated MSI Reception Module Interrupt#i Enable Register." hexmask.long 0x54 0.--31. 1. "MSI_CTRL_INT_6_EN,MSI Interrupt#i Enable. Specifies which interrupts are enabled. When an MSI is received from a disabled interrupt no status bit gets set in MSI controller interrupt status register. Each bit corresponds to a single MSI Interrupt.." line.long 0x58 "MSI_CTRL_INT_6_MASK_OFF,Integrated MSI Reception Module Interrupt#i Mask Register." hexmask.long 0x58 0.--31. 1. "MSI_CTRL_INT_6_MASK,MSI Interrupt#i Mask. Allows enabled interrupts to be masked. When an MSI is received for a masked interrupt the corresponding status bit gets set in the interrupt status register but the msi_ctrl_int output is not set HIGH. Each bit.." line.long 0x5C "MSI_CTRL_INT_6_STATUS_OFF,Integrated MSI Reception Module Interrupt#i Status Register." hexmask.long 0x5C 0.--31. 1. "MSI_CTRL_INT_6_STATUS,MSI Interrupt#i Status. When an MSI is detected for EP#i one bit in this register is set. The decoding of the data payload of the MSI Memory Write request determines which bit gets set. A status is bit is cleared by writing a 1 to.." line.long 0x60 "MSI_CTRL_INT_7_EN_OFF,Integrated MSI Reception Module Interrupt#i Enable Register." hexmask.long 0x60 0.--31. 1. "MSI_CTRL_INT_7_EN,MSI Interrupt#i Enable. Specifies which interrupts are enabled. When an MSI is received from a disabled interrupt no status bit gets set in MSI controller interrupt status register. Each bit corresponds to a single MSI Interrupt.." line.long 0x64 "MSI_CTRL_INT_7_MASK_OFF,Integrated MSI Reception Module Interrupt#i Mask Register." hexmask.long 0x64 0.--31. 1. "MSI_CTRL_INT_7_MASK,MSI Interrupt#i Mask. Allows enabled interrupts to be masked. When an MSI is received for a masked interrupt the corresponding status bit gets set in the interrupt status register but the msi_ctrl_int output is not set HIGH. Each bit.." line.long 0x68 "MSI_CTRL_INT_7_STATUS_OFF,Integrated MSI Reception Module Interrupt#i Status Register." hexmask.long 0x68 0.--31. 1. "MSI_CTRL_INT_7_STATUS,MSI Interrupt#i Status. When an MSI is detected for EP#i one bit in this register is set. The decoding of the data payload of the MSI Memory Write request determines which bit gets set. A status is bit is cleared by writing a 1 to.." line.long 0x6C "MSI_GPIO_IO_OFF,Integrated MSI Reception Module General Purpose IO Register." hexmask.long 0x6C 0.--31. 1. "MSI_GPIO_REG,MSI GPIO Register. The contents of this register drives the top-level GPIO msi_ctrl_io[31:0] Note: This register field is sticky." line.long 0x70 "CLOCK_GATING_CTRL_OFF,This register enables you to disable dynamic clock gating. By default dynamic clock gating is on. allowing the controller to autonomously enable and disable its clocks. The clock gating is performed in the clock and reset module." hexmask.long 0x70 2.--31. 1. "RSVDP_2,Reserved for future use." newline bitfld.long 0x70 1. "AXI_CLK_GATING_EN,AXI Clock Gating Enable. This register enables the AXI Bridge to autonomously enable and disable the AXI Master clock the AXI Slave clock and the AXI DBI slave clock. The DWC_pcie_clk_rst.v module provides the gated clock.." "Disable,Enable" newline bitfld.long 0x70 0. "RADM_CLK_GATING_EN,RADM Clock Gating Enable. This register if set enables the RADM to autonomously enable and disable its clock. The DWC_pcie_clk_rst.v module provides the gated clock radm_clk_g to the RADM and is enabled when the controllers clock.." "Disable,Enable" line.long 0x74 "GEN3_RELATED_OFF,Gen3 Control Register. There is no Gen3-specific N_FTS field. The N_FTS field in the 'Link Width and Speed Change Control Register' is used for both Gen2 and Gen3 speed modes. There is no Gen3-specific 'Directed Speed Change' field. The.." hexmask.long.byte 0x74 26.--31. 1. "RSVDP_26,Reserved for future use." newline bitfld.long 0x74 23. "GEN3_EQ_INVREQ_EVAL_DIFF_DISABLE,Eq InvalidRequest and RxEqEval Different Time Assertion Disable. Disable the assertion of Eq InvalidRequest and RxEqEval at different time. Note: When CX_GEN4_SPEED/CX_GEN5_SPEED this register is shared for Gen3 and.." "0,1" newline rbitfld.long 0x74 19.--20. "RSVDP_19,Reserved for future use." "0,1,2,3" newline bitfld.long 0x74 18. "GEN3_DC_BALANCE_DISABLE,DC Balance Disable. Disable DC Balance feature. Note: When CX_GEN4_SPEED/CX_GEN5_SPEED this register is shared for Gen3 and Gen4/Gen5 data rate. Note: This register field is sticky." "0,1" newline bitfld.long 0x74 17. "GEN3_DLLP_XMT_DELAY_DISABLE,DLLP Transmission Delay Disable. Disable delay transmission of DLLPs before equalization. Note: When CX_GEN4_SPEED/CX_GEN5_SPEED this register is shared for Gen3 and Gen4/Gen5 data rate. Note: This register field is sticky." "0,1" newline bitfld.long 0x74 16. "GEN3_EQUALIZATION_DISABLE,Equalization Disable. Disable equalization feature. This bit cannot be changed once the LTSSM starts link training. Note: When CX_GEN4_SPEED/CX_GEN5_SPEED this register is shared for Gen3 and Gen4/Gen5 data rate. Note: This.." "0,1" newline rbitfld.long 0x74 14.--15. "RSVDP_14,Reserved for future use." "0,1,2,3" newline bitfld.long 0x74 13. "RXEQ_RGRDLESS_RXTS,When set to '1' the controller as Gen3 EQ master asserts RxEqEval to instruct the PHY to do Rx adaptation and evaluation after a 500ns timeout from a new preset request. - 0: mac_phy_rxeqeval asserts after 1us and 2 TS1 received from.." "mac_phy_rxeqeval asserts after 1us and 2 TS1..,mac_phy_rxeqeval asserts after 500ns regardless.." newline bitfld.long 0x74 12. "RXEQ_PH01_EN,Rx Equalization Phase 0/Phase 1 Hold Enable. When this bit is set the upstream port holds phase 0 (the downstream port holds phase 1) for 10ms. Holding phase 0 or phase 1 can be used to allow sufficient time for Rx Equalization to be.." "Tx equalization only in phase 2/3,No Tx equalization" newline bitfld.long 0x74 11. "EQ_REDO,Equalization Redo Disable. Disable autonomous mechanism for requesting to redo the equalization process. The received presets or coefficients mismatch in Recovery.RcvrLock after Recovery EQ phases causes the EQ redo requests. If the EQ redo is.." "0,1" newline bitfld.long 0x74 10. "EQ_EIEOS_CNT,Equalization EIEOS Count Reset Disable. Disable requesting reset of EIEOS count during equalization. Note: When CX_GEN4_SPEED/CX_GEN5_SPEED this register is shared for Gen3 and Gen4/Gen5 data rate. Note: This register field is sticky." "0,1" newline bitfld.long 0x74 9. "EQ_PHASE_2_3,Equalization Phase 2 and Phase 3 Disable. This applies to downstream ports only. Note: When CX_GEN4_SPEED/CX_GEN5_SPEED this register is shadow register for Gen3 and Gen4/Gen5 data rate. If RATE_SHADOW_SEL==00b this register is for Gen3.." "0,1" newline bitfld.long 0x74 8. "DISABLE_SCRAMBLER_GEN_3,Disable Scrambler for Gen3 and Gen4 Data Rate. The Gen3 and Gen4 scrambler/descrambler within the controller needs to be disabled when the scrambling function is implemented outside of the controller (for example within the PHY)." "0,1" newline hexmask.long.byte 0x74 1.--7. 1. "RSVDP_1,Reserved for future use." newline bitfld.long 0x74 0. "GEN3_ZRXDC_NONCOMPL,Gen3 Receiver Impedance ZRX-DC Not Compliant. Receivers that operate at 8.0 GT/s with an impedance other than the range defined by the ZRX-DC parameter for 2.5 GT/s (40-60 Ohms) must meet additional behavior requirements in the.." "The receiver complies with the ZRX-DC parameter..,The receiver does not comply with the ZRX-DC.." group.long (0x1A8+0x700)++0x7 line.long 0x0 "GEN3_EQ_CONTROL_OFF,Gen3 EQ Control Register. This register controls equalization for Phase2 in an upstream port (USP). or Phase3 in a downstream port (DSP). M-PCIe doesn't have Conventional PCIe Gen3 feature. The registers of this section do not exist." hexmask.long.byte 0x0 27.--31. 1. "RSVDP_27,Reserved for future use." newline bitfld.long 0x0 26. "GEN3_REQ_SEND_CONSEC_EIEOS_FOR_PSET_MAP,Request controller to send back-to-back EIEOS in Recovery.RcvrLock state until presets to coefficients mapping is complete. - 0: Do not request - 1: request Note: Gen3 and Gen4 share the same register bit and have.." "Do not request,request" newline bitfld.long 0x0 25. "GEN3_EQ_PSET_REQ_AS_COEF,GEN3_EQ_PSET_REQ_AS_COEF is an internally reserved field. Do not use. Note: This register field is sticky." "0,1" newline bitfld.long 0x0 24. "GEN3_EQ_FOM_INC_INITIAL_EVAL,Include Initial FOM. Include or not the FOM feedback from the initial preset evaluation performed in the EQ Master when finding the highest FOM among all preset evaluations. - 0: Do not include - 1: Include Note: When.." "Do not include,Include" newline hexmask.long.word 0x0 8.--23. 1. "GEN3_EQ_PSET_REQ_VEC,Preset Request Vector. Requesting of Presets during the initial part of the EQ Master Phase. Encoding scheme is as follows: Bit [15:0] =0x0: No preset is requested and evaluated in EQ Master Phase. Bit [i] =1: 'Preset=i' is requested.." newline rbitfld.long 0x0 7. "RSVDP_7,Reserved for future use." "0,1" newline bitfld.long 0x0 6. "GEN3_LOWER_RATE_EQ_REDO_ENABLE,Support EQ redo and lower rate change: - 0: not support - 1: support Note: Gen3 and Gen4 share the same register bit and have the same feature. Note: This register field is sticky." "not support,support" newline bitfld.long 0x0 5. "GEN3_EQ_EVAL_2MS_DISABLE,Phase2_3 2 ms Timeout Disable. Determine behavior in Phase2 for USP (Phase3 if DSP) when the PHY does not respond within 2ms to the assertion of RxEqEval: - 0: abort the current evaluation stop any attempt to modify the remote.." "abort the current evaluation,ignore the 2ms timeout and continue as normal" newline bitfld.long 0x0 4. "GEN3_EQ_PHASE23_EXIT_MODE,Behavior After 24 ms Timeout (when optimal settings are not found). For a USP: Determine next LTSSM state from Phase2 after 24ms Timeout - 0: Recovery.Speed - 1: Recovery.Equalization.Phase3 When optimal settings are not found.." "Equalization Phase 3 Successful status bit is..,Recovery" newline hexmask.long.byte 0x0 0.--3. 1. "GEN3_EQ_FB_MODE,Feedback Mode. - 0000b: Direction Change - 0001b: Figure Of Merit - 0010b: Reserved - .....: Reserved - 1111b: Reserved Note: When CX_GEN4_SPEED/CX_GEN5_SPEED this register is a shadow register for Gen3 and Gen4/Gen5 data rate. If.." line.long 0x4 "GEN3_EQ_FB_MODE_DIR_CHANGE_OFF,Gen3 EQ Direction Change Feedback Mode Control Register. Equalization controls to be used in Phase2 (USP) or Phase 3 (DSP). when you set the Feedback Mode in 'Gen3 EQ Control Register' to 'Direction Change.' These fields.." hexmask.long.word 0x4 18.--31. 1. "RSVDP_18,Reserved for future use." newline hexmask.long.byte 0x4 14.--17. 1. "GEN3_EQ_FMDC_MAX_POST_CUSROR_DELTA,Convergence Window Aperture for C+1. Post-cursor coefficients maximum delta within the convergence window depth. Allowed range: 0 1 2 ..15. Note: When CX_GEN4_SPEED/CX_GEN5_SPEED this register is shadow register for.." newline hexmask.long.byte 0x4 10.--13. 1. "GEN3_EQ_FMDC_MAX_PRE_CUSROR_DELTA,Convergence Window Aperture for C-1. Pre-cursor coefficients maximum delta within the convergence window depth. Allowed range: 0 1 2 ..15. Note: When CX_GEN4_SPEED/CX_GEN5_SPEED this register is shadow register for Gen3.." newline hexmask.long.byte 0x4 5.--9. 1. "GEN3_EQ_FMDC_N_EVALS,Convergence Window Depth. Number of consecutive evaluations considered in Phase 2/3 when determining if optimal coefficients have been found. Allowed range: 0 1 2 ..16 up to a maximum of CX_GEN3_EQ_COEFQ_DEPTH. When set to 0 EQ.." newline hexmask.long.byte 0x4 0.--4. 1. "GEN3_EQ_FMDC_T_MIN_PHASE23,Minimum Time (in ms) To Remain in EQ Master Phase. The LTSSM stays in EQ Master phase for at least this amount of time before starting to check for convergence of the coefficients. Allowed values 0 1 ... 24. Note: When.." group.long (0x1B4+0x700)++0x27 line.long 0x0 "ORDER_RULE_CTRL_OFF,Order Rule Control Register." hexmask.long.word 0x0 16.--31. 1. "RSVDP_16,Reserved for future use." newline hexmask.long.byte 0x0 8.--15. 1. "CPL_PASS_P,Completion Passing Posted Ordering Rule Control. Determines if CPL can pass halted P queue. - 0: CPL can not pass P (recommended) - 1: CPL can pass P" newline hexmask.long.byte 0x0 0.--7. 1. "NP_PASS_P,Non-Posted Passing Posted Ordering Rule Control. Determines if NP can pass halted P queue. - 0 : NP can not pass P (recommended). - 1 : NP can pass P" line.long 0x4 "PIPE_LOOPBACK_CONTROL_OFF,PIPE Loopback Control Register." bitfld.long 0x4 31. "PIPE_LOOPBACK,PIPE Loopback Enable. Indicates RMMI Loopback if M-PCIe. Note: This register field is sticky." "0,1" newline hexmask.long.byte 0x4 27.--30. 1. "RSVDP_27,Reserved for future use." newline bitfld.long 0x4 24.--26. "RXSTATUS_VALUE,RXSTATUS_VALUE is an internally reserved field. Do not use." "0,1,2,3,4,5,6,7" newline rbitfld.long 0x4 22.--23. "RSVDP_22,Reserved for future use." "0,1,2,3" newline hexmask.long.byte 0x4 16.--21. 1. "RXSTATUS_LANE,RXSTATUS_LANE is an internally reserved field. Do not use. Note: This register field is sticky." newline hexmask.long.word 0x4 0.--15. 1. "LPBK_RXVALID,LPBK_RXVALID is an internally reserved field. Do not use. Note: This register field is sticky." line.long 0x8 "MISC_CONTROL_1_OFF,DBI Read-Only Write Enable Register." hexmask.long.word 0x8 22.--31. 1. "RSVDP_22,Reserved for future use." newline bitfld.long 0x8 21. "P2P_ERR_RPT_CTRL,Determines whether to track completion of transmitted Non-Posted TLPs in P2P mode. - 0: Do not track completion - 1: Track completion Note: This register field is sticky." "Do not track completion,Track completion" newline bitfld.long 0x8 20. "P2P_TRACK_CPL_TO_REG,Determines whether to enable Peer to Peer (P2P) error reporting. - 0: Disable P2P error reporting - 1: Enable P2P error reporting Note: This register field is sticky." "Disable P2P error reporting,Enable P2P error reporting" newline bitfld.long 0x8 18.--19. "TARGET_ABOVE_CONFIG_LIMIT_REG,Configuration requests with an address greater than CONFIG_LIMIT_REG are directed to either ELBI or TRGT1 interface based on the setting of this field. This field can have the following values: - 1: ELBI - 2: TRGT1 Note:.." "?,ELBI,TRGT1,?" newline hexmask.long.word 0x8 8.--17. 1. "CONFIG_LIMIT_REG,Configuration requests are directed either to CDM or ELBI/RTRGT1 based on the value of this field. - Configuration requests with an address less CONFIG_LIMIT_REG are directed to the CDM - Configuration requests with an address greater.." newline bitfld.long 0x8 7. "CFG_TLP_BYPASS_EN_REG,Setting of this field defines which field TARGET_ABOVE_CONFIG_LIMIT_REG or CONFIG_LIMIT_REG decides the destination of Configuration requests. This field can have the following values: - 0: Configuration TLPs are routed according to.." "Configuration TLPs are routed according to the..,Configuration TLPs are routed according to the.." newline bitfld.long 0x8 6. "CPLQ_MNG_EN,This field enables the Completion Queue Management feature. Note: This register field is sticky." "0,1" newline bitfld.long 0x8 5. "ARI_DEVICE_NUMBER,When ARI is enabled this field enables use of the device ID. Note: This register field is sticky." "0,1" newline bitfld.long 0x8 4. "DISABLE_AUTO_LTR_CLR_MSG,Disable the autonomous generation of LTR clear message in upstream port. This field can have the following values: - 0: Allow the autonomous generation of LTR clear message. - 1: Disable the autonomous generation of LTR clear.." "Allow the autonomous generation of LTR clear..,Disable the autonomous generation of LTR clear.." newline bitfld.long 0x8 3. "SIMPLIFIED_REPLAY_TIMER,Enables Simplified Replay Timer (Gen4). For more details see 'Transmit Replay' in 'Transmit TLP Processing' section in the 'Controller Operations' chapter of the Databook. Simplified Replay Timer can have the following Values: -.." "0,1" newline bitfld.long 0x8 2. "UR_CA_MASK_4_TRGT1,When this field is set to '1' the controller suppresses error logging error message generation and CPL generation for non-posted requests TLPs (with UR filtering status) forwarded to your application (that is when DEFAULT_TARGET.." "0,1" newline bitfld.long 0x8 1. "DEFAULT_TARGET,Default target for an IO or MEM request with UR/CA/CRS received. Based on the value of this field the controller either drops or forwards these requests to your application. - 0: The controller drops all incoming I/O or MEM requests (after.." "The controller drops all incoming I/O or MEM..,The controller forwards all incoming I/O or MEM.." newline bitfld.long 0x8 0. "DBI_RO_WR_EN,Write to RO Registers Using DBI. Your application can write to some RO and HwInit register fields through the DBI when you set this field to '1'. For more details see 'Writing to Read-Only Registers' in 'Register Module LBC and DBI'.." "0,1" line.long 0xC "MULTI_LANE_CONTROL_OFF,UpConfigure Multi-lane Control Register. Used when upsizing or downsizing the link width through Configuration state without bringing the link down. For more details. see the 'Link Establishment' section in the 'Controller.." hexmask.long.tbyte 0xC 8.--31. 1. "RSVDP_8,Reserved for future use." newline bitfld.long 0xC 7. "UPCONFIGURE_SUPPORT,Upconfigure Support. The controller sends this value as the Link Upconfigure Capability in TS2 Ordered Sets in Configuration.Complete state. This field is reserved (fixed to '0') for M-PCIe. Note: This register field is sticky." "0,1" newline bitfld.long 0xC 6. "DIRECT_LINK_WIDTH_CHANGE,Directed Link Width Change. The controller always moves to Configuration state through Recovery state when this bit is set to '1'. - If the upconfigure_capable variable is '1' and the PCIE_CAP_HW_AUTO_WIDTH_DISABLE bit in.." "0,1" newline hexmask.long.byte 0xC 0.--5. 1. "TARGET_LINK_WIDTH,Target Link Width. Values correspond to: - 6'b000000: Controller does not start upconfigure or autonomous width downsizing in the Configuration state. - 6'b000001: x1 - 6'b000010: x2 - 6'b000100: x4 - 6'b001000: x8 - 6'b010000: x16 -.." line.long 0x10 "PHY_INTEROP_CTRL_OFF,PHY Interoperability Control Register." hexmask.long.tbyte 0x10 12.--31. 1. "RSVDP_12,Reserved for future use." newline bitfld.long 0x10 10. "L1_CLK_SEL,L1 Clock control bit. This field is reserved for internal use. You should not write to this field and change the default unless specifically instructed by Synopsys support. - 1: Controller does not request aux_clk switch and core_clk gating in.." "Controller requests aux_clk switch and core_clk..,Controller does not request aux_clk switch and.." newline rbitfld.long 0x10 9. "L1_NOWAIT_P1,L1 entry control bit. This field is reserved for internal use. You should not write to this field and change the default unless specifically instructed by Synopsys support. - 1: Controller does not wait for PHY to acknowledge transition to.." "Controller waits for the PHY to acknowledge..,Controller does not wait for PHY to acknowledge.." newline bitfld.long 0x10 8. "L1SUB_EXIT_MODE,L1 Exit Control Using phy_mac_pclkack_n. This field is reserved for internal use. You should not write to this field and change the default unless specifically instructed by Synopsys support. - 1: Controller exits L1 without waiting for.." "Controller waits for the PHY to assert..,Controller exits L1 without waiting for the PHY.." newline rbitfld.long 0x10 7. "RSVDP_7,Reserved for future use." "0,1" newline hexmask.long.byte 0x10 0.--6. 1. "RXSTANDBY_CONTROL,Rxstandby Control. Bits 0..5 determine if the controller asserts the RxStandby signal (mac_phy_rxstandby) in the indicated condition. Bit 6 enables the controller to perform the RxStandby/RxStandbyStatus handshake. This field is.." line.long 0x14 "TRGT_CPL_LUT_DELETE_ENTRY_OFF,TRGT_CPL_LUT Delete Entry Control register. Using this register you can delete one entry in the target completion LUT. You should only use this register when you know that your application will never send the completion.." bitfld.long 0x14 31. "DELETE_EN,This is a one-shot bit. A '1' write to this bit triggers the deletion of the target completion LUT entry that is specified in the LOOK_UP_ID field. This is a self-clearing register field. Reading from this register field always returns a '0'." "0,1" newline hexmask.long 0x14 0.--30. 1. "LOOK_UP_ID,This number selects one entry to delete of the TRGT_CPL_LUT." line.long 0x18 "LINK_FLUSH_CONTROL_OFF,Link Reset Request Flush Control Register." hexmask.long.byte 0x18 24.--31. 1. "RSVD_I_8,This is an internally reserved field. Do not use. Note: This register field is sticky." newline hexmask.long.tbyte 0x18 1.--23. 1. "RSVDP_1,Reserved for future use." newline bitfld.long 0x18 0. "AUTO_FLUSH_EN,Enables automatic flushing of pending requests before sending the reset request to the application logic to reset the PCIe controller and the AXI Bridge. The flushing process is initiated if any of the following events occur: - Hot reset.." "0,1" line.long 0x1C "AMBA_ERROR_RESPONSE_DEFAULT_OFF,AXI Bridge Slave Error Response Register." hexmask.long.word 0x1C 16.--31. 1. "RSVDP_16,Reserved for future use." newline hexmask.long.byte 0x1C 10.--15. 1. "AMBA_ERROR_RESPONSE_MAP,AXI Slave Response Error Map. Allows you to selectively map the errors received from the PCIe completion (for non-posted requests) to the AXI slave responses slv_rresp or slv_bresp. The recommended setting is SLVERR. CRS is.." newline hexmask.long.byte 0x1C 5.--9. 1. "RSVDP_5,Reserved for future use." newline bitfld.long 0x1C 3.--4. "AMBA_ERROR_RESPONSE_CRS,CRS Slave Error Response Mapping. Determines the AXI slave response for CRS completions. For more details see 'Error Handling' in the AXI chapter of the Databook. AHB: - always returns OKAY AXI: - 00: OKAY - 01: OKAY with all.." "OKAY,OKAY with all FFFF_FFFF data for all CRS..,?,?" newline bitfld.long 0x1C 2. "AMBA_ERROR_RESPONSE_VENDORID,Vendor ID Non-existent Slave Error Response Mapping. Determines the AXI slave response for errors on reads to non-existent Vendor ID register. For more details see 'Error Handling' in the AXI chapter of the Databook. AHB: -.." "OKAY,SLVERR/DECERR" newline rbitfld.long 0x1C 1. "RSVDP_1,Reserved for future use." "0,1" newline bitfld.long 0x1C 0. "AMBA_ERROR_RESPONSE_GLOBAL,Global Slave Error Response Mapping. Determines the AXI slave response for all error scenarios on non-posted requests. For more details see 'Error Handling' in the AXI chapter of the Databook. AHB: - 0: OKAY (with FFFF data for.." "OKAY,SLVERR/DECERR" line.long 0x20 "AMBA_LINK_TIMEOUT_OFF,Link Down AXI Bridge Slave Timeout Register. If your application AXI master issues outbound requests to the AXI bridge slave interface before the PCIe link is operational. the controller starts a 'flush' timer. The timeout value of.." hexmask.long.tbyte 0x20 9.--31. 1. "RSVDP_9,Reserved for future use." newline bitfld.long 0x20 8. "LINK_TIMEOUT_ENABLE_DEFAULT,Disable Flush. You can disable the flush feature by setting this field to '1'. Note: This register field is sticky." "0,1" newline hexmask.long.byte 0x20 0.--7. 1. "LINK_TIMEOUT_PERIOD_DEFAULT,Timeout Value (ms). The timer will timeout and then flush the bridge TX request queues after this amount of time. The timer counts when there are pending outbound AXI slave interface requests and the PCIe TX link is not.." line.long 0x24 "AMBA_ORDERING_CTRL_OFF,AMBA Ordering Control." hexmask.long.tbyte 0x24 8.--31. 1. "RSVDP_8,Reserved for future use." newline bitfld.long 0x24 7. "AX_MSTR_ZEROLREAD_FW,AXI Master Zero Length Read Forward to the application. The DW PCIe controller AXI bridge is able to terminate in order with the Posted transactions the zero length read implementing the PCIe express flush semantics of the Posted.." "The zero length Read is terminated at the DW..,The zero length Read is forward to the application" newline rbitfld.long 0x24 5.--6. "RSVDP_5,Reserved for future use." "0,1,2,3" newline bitfld.long 0x24 3.--4. "AX_MSTR_ORDR_P_EVENT_SEL,AXI Master Posted Ordering Event Selector. This field selects how the master interface determines when a P write is completed when enforcing the PCIe ordering rule 'NP must not pass P' at the AXI Master Interface. The AXI.." "B'last event: wait for the all of the write..,AW'last event: wait until the complete Posted..,This setting will not affect:,?" newline rbitfld.long 0x24 2. "RSVDP_2,Reserved for future use." "0,1" newline bitfld.long 0x24 1. "AX_SNP_EN,AXI Serialize Non-Posted Requests Enable. This field enables the AXI Bridge to serialize same ID Non-Posted Read/Write Requests on the wire. Serialization implies one outstanding same ID NP Read or Write on the wire and used to avoid AXI RAR.." "0,1" newline rbitfld.long 0x24 0. "RSVDP_0,Reserved for future use." "0,1" group.long (0x1E0+0x700)++0xB line.long 0x0 "COHERENCY_CONTROL_1_OFF,ACE Cache Coherency Control Register 1" hexmask.long 0x0 2.--31. 1. "CFG_MEMTYPE_BOUNDARY_LOW_ADDR,Boundary Lower Address For Memory Type. Bits [31:0] of dword-aligned address of the boundary for Memory type. The two lower address LSBs are '00'. Addresses up to but not including this value are in the lower address space.." newline rbitfld.long 0x0 1. "RSVDP_1,Reserved for future use." "0,1" newline bitfld.long 0x0 0. "CFG_MEMTYPE_VALUE,Sets the memory type for the lower and upper parts of the address space: - 0: lower = Peripheral; upper = Memory - 1: lower = Memory type; upper = Peripheral Note: This register field is sticky." "lower = Peripheral; upper = Memory,lower = Memory type; upper = Peripheral" line.long 0x4 "COHERENCY_CONTROL_2_OFF,ACE Cache Coherency Control Register 2" hexmask.long 0x4 0.--31. 1. "CFG_MEMTYPE_BOUNDARY_HIGH_ADDR,Boundary Upper Address For Memory Type. Bits [63:32] of the 64-bit dword-aligned address of the boundary for Memory type. Note: This register field is sticky." line.long 0x8 "COHERENCY_CONTROL_3_OFF,ACE Cache Coherency Control Register 3" hexmask.long.byte 0x8 27.--30. 1. "CFG_MSTR_AWCACHE_VALUE,Master Write CACHE Signal Value. Value of the individual bits in mstr_awcache when CFG_MSTR_AWCACHE_MODE is '1'. Note: not applicable to message requests; for message requests the value of mstr_awcache is always '0000' Note: This.." newline hexmask.long.byte 0x8 19.--22. 1. "CFG_MSTR_ARCACHE_VALUE,Master Read CACHE Signal Value. Value of the individual bits in mstr_arcache when CFG_MSTR_ARCACHE_MODE is '1'. Note: This register field is sticky." newline hexmask.long.byte 0x8 11.--14. 1. "CFG_MSTR_AWCACHE_MODE,Master Write CACHE Signal Behavior. Defines how the individual bits in mstr_awcache are controlled: - 0: set automatically by the AXI master - 1: set by the value of the corresponding bit of the CFG_MSTR_AWCACHE_VALUE field Note:.." newline hexmask.long.byte 0x8 3.--6. 1. "CFG_MSTR_ARCACHE_MODE,Master Read CACHE Signal Behavior. Defines how the individual bits in mstr_arcache are controlled: - 0: set automatically by the AXI master - 1: set by the value of the corresponding bit of the CFG_MSTR_ARCACHE_VALUE field Note:.." group.long (0x1F0+0x700)++0x7 line.long 0x0 "AXI_MSTR_MSG_ADDR_LOW_OFF,Lower 20 bits of the programmable AXI address where Messages coming from wire are mapped to. Bits [11:0] of the register are tied to zero for the address to be 4k-aligned. In previous releases. the third and fourth DWORDs of a.." hexmask.long.tbyte 0x0 12.--31. 1. "CFG_AXIMSTR_MSG_ADDR_LOW,Lower 20 bits of the programmable AXI address for Messages. Note: This register field is sticky." newline hexmask.long.word 0x0 0.--11. 1. "CFG_AXIMSTR_MSG_ADDR_LOW_RESERVED,Reserved for future use. Note: This register field is sticky." line.long 0x4 "AXI_MSTR_MSG_ADDR_HIGH_OFF,Upper 32 bits of the programmable AXI address where Messages coming from wire are mapped to." hexmask.long 0x4 0.--31. 1. "CFG_AXIMSTR_MSG_ADDR_HIGH,Upper 32 bits of the programmable AXI address for Messages. Note: This register field is sticky." rgroup.long (0x1F8+0x700)++0x7 line.long 0x0 "PCIE_VERSION_NUMBER_OFF,PCIe Controller IIP Release Version Number. The version number is given in hex format. You should convert each pair of hex characters to ASCII to interpret. Using 4.70a (GA) as an example: - VERSION_NUMBER = 0x3437302a which.." hexmask.long 0x0 0.--31. 1. "VERSION_NUMBER,Version Number." line.long 0x4 "PCIE_VERSION_TYPE_OFF,PCIe Controller IIP Release Version Type. The type is given in hex format. You should convert each pair of hex characters to ASCII to interpret. Using 4.70a (GA) as an example: - VERSION_NUMBER = 0x3437302a which translates to 470*.." hexmask.long 0x4 0.--31. 1. "VERSION_TYPE,Version Type." group.long (0x240+0x700)++0x7 line.long 0x0 "MSIX_ADDRESS_MATCH_LOW_OFF,MSI-X Address Match Low Register. When you enable the MSI-X Table RAM feature (MSIX_TABLE_EN=1). the controller implements the logic and RAM required to generate MSI-X requests. For more details. see the Interrupts section in.." hexmask.long 0x0 2.--31. 1. "MSIX_ADDRESS_MATCH_LOW,MSI-X Address Match Low Address. Note: This register field is sticky." newline rbitfld.long 0x0 1. "MSIX_ADDRESS_MATCH_RESERVED_1,Reserved. Note: This register field is sticky." "0,1" newline bitfld.long 0x0 0. "MSIX_ADDRESS_MATCH_EN,MSI-X Match Enable. Enable the MSI-X Address Match feature when the AXI bridge is present. Note: This register field is sticky." "0,1" line.long 0x4 "MSIX_ADDRESS_MATCH_HIGH_OFF,MSI-X Address Match High Register. When you enable the MSI-X Table RAM feature (MSIX_TABLE_EN=1). the controller implements the logic and RAM required to generate MSI-X requests. For more details. see the Interrupts section in.." hexmask.long 0x4 0.--31. 1. "MSIX_ADDRESS_MATCH_HIGH,MSI-X Address Match High Address. Note: This register field is sticky." wgroup.long (0x248+0x700)++0x3 line.long 0x0 "MSIX_DOORBELL_OFF,MSI-X Doorbell Register. When you enable the MSI-X Table RAM feature (MSIX_TABLE_EN=1). the controller implements the logic and RAM required to generate MSI-X requests. For more details. see the Interrupts section in the 'Controller.." bitfld.long 0x0 29.--31. "MSIX_DOORBELL_RESERVED_29_31,Reserved." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x0 24.--28. 1. "MSIX_DOORBELL_PF,MSIX Doorbell Physical Function. This register determines the Physical Function for the MSI-X transaction." newline hexmask.long.byte 0x0 16.--23. 1. "MSIX_DOORBELL_VF,MSIX Doorbell Virtual Function. This register determines the Virtual Function for the MSI-X transaction." newline bitfld.long 0x0 15. "MSIX_DOORBELL_VF_ACTIVE,MSIX Doorbell Virtual Function Active. This register determines whether a Virtual Function is used to generate the MSI-X transaction." "0,1" newline bitfld.long 0x0 12.--14. "MSIX_DOORBELL_TC,MSIX Doorbell Traffic Class. This register determines which traffic class to generate the MSI-X transaction with." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 11. "MSIX_DOORBELL_RESERVED_11,Reserved." "0,1" newline hexmask.long.word 0x0 0.--10. 1. "MSIX_DOORBELL_VECTOR,MSI-X Doorbell Vector. This register determines which vector to generate the MSI-X transaction for." group.long (0x24C+0x700)++0x3 line.long 0x0 "MSIX_RAM_CTRL_OFF,MSI-X RAM power mode and debug control register. When you enable the MSI-X Table RAM feature (MSIX_TABLE_EN=1). the controller implements the logic and RAM required to generate MSI-X requests. For more details. see the Interrupts.." hexmask.long.byte 0x0 26.--31. 1. "MSIX_RAM_CTRL_RESERVED_26_31,Reserved. Note: This register field is sticky." newline bitfld.long 0x0 25. "MSIX_RAM_CTRL_DBG_PBA,MSIX PBA RAM Debug Mode. Use this bit to activate the debug mode and allow direct read/write access to the PBA. Use can also use the dbg_pba input to activate debug mode. Debug mode turns off the PF/VF/Offset-based addressing into.." "0,1" newline bitfld.long 0x0 24. "MSIX_RAM_CTRL_DBG_TABLE,MSIX Table RAM Debug Mode. Use this bit to activate the debug mode and allow direct read/write access to the Table. Use can also use the dbg_table input to activate debug mode. Debug mode turns off the PF/VF/Offset-based.." "0,1" newline hexmask.long.byte 0x0 17.--23. 1. "MSIX_RAM_CTRL_RESERVED_17_23,Reserved. Note: This register field is sticky." newline bitfld.long 0x0 16. "MSIX_RAM_CTRL_BYPASS,MSIX RAM Control Bypass. The bypass field when set disables the internal generation of low power signals for both RAMs. It is up to the application to ensure the RAMs are in the proper power state before trying to access them." "0,1" newline hexmask.long.byte 0x0 10.--15. 1. "MSIX_RAM_CTRL_RESERVED_10_15,Reserved. Note: This register field is sticky." newline bitfld.long 0x0 9. "MSIX_RAM_CTRL_PBA_SD,MSIX PBA RAM Shut Down. Set this bit to drive the cfg_msix_pba_sd output to signal your external logic to place the MSIX PBA RAM in Shut Down low-power mode. Note: This register field is sticky." "0,1" newline bitfld.long 0x0 8. "MSIX_RAM_CTRL_PBA_DS,MSIX PBA RAM Deep Sleep. Set this bit to drive the cfg_msix_pba_ds output to signal your external logic to place the MSIX PBA RAM in Deep Sleep low-power mode. Note: This register field is sticky." "0,1" newline hexmask.long.byte 0x0 2.--7. 1. "MSIX_RAM_CTRL_RESERVED_2_7,Reserved. Note: This register field is sticky." newline bitfld.long 0x0 1. "MSIX_RAM_CTRL_TABLE_SD,MSIX Table RAM Shut Down. Set this bit to drive the cfg_msix_table_sd output to signal your external logic to place the MSIX Table RAM in Shut Down low-power mode. Note: This register field is sticky." "0,1" newline bitfld.long 0x0 0. "MSIX_RAM_CTRL_TABLE_DS,MSIX Table RAM Deep Sleep. Set this bit to drive the cfg_msix_table_ds output to signal your external logic to place the MSIX Table RAM in Deep Sleep low-power mode. Note: This register field is sticky." "0,1" group.long (0x430+0x700)++0x3 line.long 0x0 "PL_LTR_LATENCY_OFF,LTR Latency Register. The function of this register field (and all other fields in this register) differs between an upstream port and a downstream port. For an upstream port. the register fields capture the corresponding fields in the.." bitfld.long 0x0 31. "NO_SNOOP_LATENCY_REQUIRE,No Snoop Latency Requirement. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" "0,1" newline rbitfld.long 0x0 29.--30. "RSVDP_29,Reserved for future use." "0,1,2,3" newline bitfld.long 0x0 26.--28. "NO_SNOOP_LATENCY_SCALE,No Snoop Latency Scale. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" "0,1,2,3,4,5,6,7" newline hexmask.long.word 0x0 16.--25. 1. "NO_SNOOP_LATENCY_VALUE,No Snoop Latency Value. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" newline bitfld.long 0x0 15. "SNOOP_LATENCY_REQUIRE,Snoop Latency Requirement. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" "0,1" newline rbitfld.long 0x0 13.--14. "RSVDP_13,Reserved for future use." "0,1,2,3" newline bitfld.long 0x0 10.--12. "SNOOP_LATENCY_SCALE,Snoop Latency Scale. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" "0,1,2,3,4,5,6,7" newline hexmask.long.word 0x0 0.--9. 1. "SNOOP_LATENCY_VALUE,Snoop Latency Value. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" group.long (0x440+0x700)++0xB line.long 0x0 "AUX_CLK_FREQ_OFF,Auxiliary Clock Frequency Control Register." hexmask.long.tbyte 0x0 10.--31. 1. "RSVDP_10,Reserved for future use." newline hexmask.long.word 0x0 0.--9. 1. "AUX_CLK_FREQ,The aux_clk frequency in MHz. This value is used to provide a 1 us reference for counting time during low-power states with aux_clk when the PHY has removed the pipe_clk. Frequencies lower than 1 MHz are possible but with a loss of accuracy.." line.long 0x4 "L1_SUBSTATES_OFF,L1 Substates Timing Register." hexmask.long.tbyte 0x4 9.--31. 1. "RSVDP_9,Reserved for future use." newline bitfld.long 0x4 8. "L1SUB_LOW_POWER_CLOCK_SWITCH_MODE,If this bit is set to 1'b1 the reference clock will be running regardless of the CLKREQ# setting. If this bit is set to 1'b0 the reference clock may be gated off when CLKREQ# is de-asserted. If the bit is set to 1'b1 the.." "0,1" newline bitfld.long 0x4 6.--7. "L1SUB_T_PCLKACK,Max delay (in 1us units) between a MAC request to remove the clock on mac_phy_pclkreq_n and a PHY response on phy_mac_pclkack_n. If the PHY does not respond within this time the request is aborted.The actual timeout value will be.." "0,1,2,3" newline hexmask.long.byte 0x4 2.--5. 1. "L1SUB_T_L1_2,Duration (in 1us units) of L1.2. The actual timeout value will be L1SUB_T_L1_2 + 1. Range is 0.15. Note: This register field is sticky." newline bitfld.long 0x4 0.--1. "L1SUB_T_POWER_OFF,Duration (in 1us units) of L1.2.Entry. The actual timeout value will be L1SUB_T_POWER_OFF + 1. Range is 0.3. Note: This register field is sticky." "0,1,2,3" line.long 0x8 "POWERDOWN_CTRL_STATUS_OFF,Powerdown Control and Status Register." hexmask.long.tbyte 0x8 12.--31. 1. "RSVDP_12,Reserved for future use." newline hexmask.long.byte 0x8 8.--11. 1. "POWERDOWN_PHY_POWERDOWN,This field represents the Powerdown value that has been acknowledged by the PHY. It is updated with the value of Powerdown driven by the controller when the PHY has returned the Phystatus acknowledgment for the Powerdown.." newline hexmask.long.byte 0x8 4.--7. 1. "POWERDOWN_MAC_POWERDOWN,This field represents the Powerdown value driven by the controller to the PHY." newline rbitfld.long 0x8 1.--3. "RSVDP_1,Reserved for future use." "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 0. "POWERDOWN_FORCE,This field is a one shot field. Writing a value of 1 to this field causes the controller to complete the P2 Powerdown handshake regardless of whether the PHY has returned Phystatus. This field could be used for debug purposes in event.." "0,1" group.long (0x470+0x700)++0x7 line.long 0x0 "PHY_VIEWPORT_CTLSTS_OFF,PHY Register Viewport Control and Status Register." rbitfld.long 0x0 31. "PHY_VIEWPORT_PENDING,PHY viewport pending. Indicates the access is pending. - 1 : Pending - 0 : Idle This bit is set to 1 when the read/write access has been initiated. This bit is cleared when the access is completed. If phy_reg_clk_g is never activated.." "Idle,Pending" newline rbitfld.long 0x0 30. "PHY_VIEWPORT_STATUS,PHY viewport status. Indicates the status of the latest access. - 1 : Timeout - 0 : No errors If the timeout is detected this bit is set to 1 and PHY_VIEWPORT_PENDING is cleared. This bit is cleared when the read/write access is.." "No errors,Timeout" newline hexmask.long.byte 0x0 23.--29. 1. "RSVDP_23,Reserved for future use." newline bitfld.long 0x0 22. "PHY_VIEWPORT_TIMEOUT_DISABLE,PHY viewport timeout disable. Disables the PHY register access timeout structure. When the timeout is disabled you must ensure that the PHY register accesses are always acknowledged by cr_para_ack. Otherwise.." "0,1" newline bitfld.long 0x0 21. "PHY_VIEWPORT_BCWR,Broadcast write access to all xN sub-blocks. If you need to broadcast the write accesses into all lanes both PHY_VIEWPORT_ADDR[15] and this bit should be 1. Note: This register field is sticky." "0,1" newline bitfld.long 0x0 20. "PHY_VIEWPORT_READ,PHY viewport read. If set a read access is initiated. The value is always 0 when this bit is read. Note: This register field is sticky." "0,1" newline hexmask.long.byte 0x0 16.--19. 1. "PHY_VIEWPORT_NUM,PHY viewport xN sub-block number. Selects one of xN sub-blocks. This register is not used when the write access is initiated with PHY_VIEWPORT_BCWR==1. Note: This register field is sticky." newline hexmask.long.word 0x0 0.--15. 1. "PHY_VIEWPORT_ADDR,PHY viewport address. Indicates the PHY's register address. Please refer to the PHY databook for the address map definition. Note: This register field is sticky." line.long 0x4 "PHY_VIEWPORT_DATA_OFF,PHY Register Viewport Data Register." hexmask.long.word 0x4 16.--31. 1. "RSVDP_16,Reserved for future use." newline hexmask.long.word 0x4 0.--15. 1. "PHY_VIEWPORT_DATA,PHY viewport data. A write access to this register initiates the PHY register write access. By a read access to this register this field returns the latest read data from the PHY register. Note: This register field is sticky." group.long (0x490+0x700)++0x3 line.long 0x0 "PIPE_RELATED_OFF,PIPE Related Register. This register controls the pipe's capabitity. control. and status parameters." hexmask.long.tbyte 0x0 9.--31. 1. "RSVDP_9,Reserved for future use." newline bitfld.long 0x0 8. "PIPE_GARBAGE_DATA_MODE,PIPE Garbage Data Mode. - 0: PIPE Spec compliant mode: The MAC discards any symbols received after the electrical idle ordered-set until RxValid is deasserted. - 1: Special PHY Support mode: The MAC discards any symbols received.." "PIPE Spec compliant mode: The MAC discards any..,Special PHY Support mode: The MAC discards any.." tree.end tree.end tree "PCIE1_VF01" base ad:0x31020000 tree "PF0_TYPE1_HDR (PCI-Compatible Configuration Space Header Type1)" group.long 0x0++0x2F line.long 0x0 "TYPE1_DEV_ID_VEND_ID_REG,Device ID and Vendor ID Register." hexmask.long.word 0x0 16.--31. 1. "DEVICE_ID,Device ID. The Device ID register identifies the particular Function. This identifier is allocated by the vendor. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else.." newline hexmask.long.word 0x0 0.--15. 1. "VENDOR_ID,Vendor ID. The Vendor ID register identifies the manufacturer of the Function. Valid vendor identifiers are allocated by the PCI-SIG to ensure uniqueness. It is not permitted to populate this register with a value of FFFFh which is an invalid.." line.long 0x4 "TYPE1_STATUS_COMMAND_REG,Status and Command Register." bitfld.long 0x4 31. "DETECTED_PARITY_ERROR,Detected Parity Error. This bit is set by a Function whenever it receives a Poisoned TLP regardless of the state the Parity Error Response bit in the Command register. The bit is set when the Poisoned TLP is received by a.." "0,1" newline bitfld.long 0x4 30. "SIGNALED_SYS_ERROR,Signaled System Error. This bit is set when a Function sends an ERR_FATAL or ERR_NONFATAL Message and the SERR# Enable bit in the Command register is 1b." "0,1" newline bitfld.long 0x4 29. "RCVD_MASTER_ABORT,Received Master Abort. This bit is set when a Requester receives a Completion with Unsupported Request Completion status. The bit is set when the Unsupported Request is received by a Function's primary side." "0,1" newline bitfld.long 0x4 28. "RCVD_TARGET_ABORT,Received Target Abort. This bit is set when a Requester receives a Completion with Completer Abort Completion status. The bit is set when the Completer Abort is received by a Function's primary side." "0,1" newline bitfld.long 0x4 27. "SIGNALED_TARGET_ABORT,Signaled Target Abort. This bit is set when a Function completes a Posted or Non-Posted Request as a Completer Abort error. This applies to a Function when the Completer Abort was generated by its primary side." "0,1" newline rbitfld.long 0x4 25.--26. "DEV_SEL_TIMING,DEVSEL Timing. This field was originally described in the PCI Local Bus Specification. Its functionality does not apply to PCI Express. The controller hardwires it to 00b." "0,1,2,3" newline bitfld.long 0x4 24. "MASTER_DPE,Master Data Parity Error. This bit is set by a Function if the Parity Error Response bit in the Command register is 1b and either of the following two conditions occurs: - Port receives a Poisoned Completion going downstream - Port transmits a.." "0,1" newline rbitfld.long 0x4 23. "FAST_B2B_CAP,Fast Back-to-Back Transactions Capable. This bit was originally described in the PCI Local Bus Specification. Its functionality does not apply to PCI Express. The controller hardwires this bit to 0b." "0,1" newline rbitfld.long 0x4 22. "RSVDP_22,Reserved for future use." "0,1" newline rbitfld.long 0x4 21. "FAST_66MHZ_CAP,66 MHz Capable. This bit was originally described in the PCI Local Bus Specification. Its functionality does not apply to PCI Express. The controller hardwires this bit to 0b." "0,1" newline rbitfld.long 0x4 20. "CAP_LIST,Capabilities List. Indicates the presence of an Extended Capability list item. Since all PCI Express device Functions are required to implement the PCI Express Capability structure the controller hardwires this bit to 1b." "0,1" newline rbitfld.long 0x4 19. "INT_STATUS,Interrupt Status. When set indicates that an INTx emulation interrupt is pending internally in the Function. INTx emulation interrupts forwarded by Functions from the secondary side are not reflected in this bit. Setting the Interrupt Disable.." "0,1" newline rbitfld.long 0x4 17.--18. "RSVDP_17,Reserved for future use." "0,1,2,3" newline bitfld.long 0x4 16. "IMM_READINESS,Immediate Readiness. This optional bit when set indicates the Function is guaranteed to be ready to successfully complete valid configuration accesses at any time following any reset that the host is capable of issuing Configuration.." "0,1" newline hexmask.long.byte 0x4 11.--15. 1. "RESERV,Reserved." newline bitfld.long 0x4 10. "INT_EN,Interrupt Disable. Controls the ability of a Function to generate INTx emulation interrupts. When set Functions are prevented from asserting INTx interrupts. Note: - Any INTx emulation interrupts already asserted by the Function must be.." "0,1" newline rbitfld.long 0x4 9. "RSVDP_9,Reserved for future use." "0,1" newline bitfld.long 0x4 8. "SERREN,SERR# Enable. When set this bit enables reporting upstream of Non-fatal and Fatal errors detected by the Function. Note: The errors are reported if enabled either through this bit or through the PCI Express specific bits in the Device Control.." "0,1" newline rbitfld.long 0x4 7. "IDSEL,IDSEL Stepping/Wait Cycle Control. This bit was originally described in the PCI Local Bus Specification. Its functionality does not apply to PCI Express. The controller hardwires this bit to 0b." "0,1" newline bitfld.long 0x4 6. "PERREN,Parity Error Response. This bit controls the logging of poisoned TLPs in the Master Data Parity Error bit in the Status register. For more details see the 'Error Registers' section of the PCI Express Base Specification." "0,1" newline rbitfld.long 0x4 5. "VGAPS,VGA Palette Snoop. This bit was originally described in the PCI Local Bus Specification and the PCI-to-PCI Bridge Architecture Specification. Its functionality does not apply to PCI Express. The controller hardwires this bit to 0b." "0,1" newline rbitfld.long 0x4 4. "MWI_EN,Memory Write and Invalidate. This bit was originally described in the PCI Local Bus Specification and the PCI-to-PCI Bridge Architecture Specification. Its functionality does not apply to PCI Express. The controller hardwires this bit to 0b. For.." "0,1" newline rbitfld.long 0x4 3. "SCO,Special Cycle Enable. This bit was originally described in the PCI Local Bus Specification. Its functionality does not apply to PCI Express. The controller hardwires this bit to 0b." "0,1" newline bitfld.long 0x4 2. "BME,Bus Master Enable. This bit controls forwarding of Memory or I/O requests by a port in the Upstream direction. When this bit is 0b Memory and I/O Requests received at a Root Port must be handled as Unsupported Requests (UR) For Non-Posted Requests a.." "0,1" newline bitfld.long 0x4 1. "MSE,Memory Space Enable. This bit controls a Function's response to Memory Space accesses received on its primary side. - When set the Function is enabled to decode the address and further process Memory Space accesses. - When clear all received Memory.." "0,1" newline bitfld.long 0x4 0. "IO_EN,IO Space Enable. This bit controls a Function's response to I/O Space accesses received on its primary side. - When set the Function is enabled to decode the address and further process I/O Space accesses. - When clear all received I/O accesses.." "0,1" line.long 0x8 "TYPE1_CLASS_CODE_REV_ID_REG,Class Code and Revision ID Register." hexmask.long.byte 0x8 24.--31. 1. "BASE_CLASS_CODE,Base Class Code. A code that broadly classifies the type of operation the Function performs. Encodings for base class are provided in the PCI Code and ID Assignment Specification. All unspecified encodings are reserved. Note: The access.." newline hexmask.long.byte 0x8 16.--23. 1. "SUBCLASS_CODE,Sub-Class Code. Specifies a base class sub-class which identifies more specifically the operation of the Function. Encodings for sub-class are provided in the PCI Code and ID Assignment Specification. All unspecified encodings are.." newline hexmask.long.byte 0x8 8.--15. 1. "PROGRAM_INTERFACE,Programming Interface. This field identifies a specific register level programming interface (if any) so that device independent software can interact with the Function. Encodings for interface are provided in the PCI Code and ID.." newline hexmask.long.byte 0x8 0.--7. 1. "REVISION_ID,Revision ID. The value of this field specifies a Function specific revision identifier. The value is chosen by the vendor. Zero is an acceptable value. The Revision ID should be viewed as a vendor defined extension to the Device ID. Note: The.." line.long 0xC "TYPE1_BIST_HDR_TYPE_LAT_CACHE_LINE_SIZE_REG,BIST. Header Type. Latency Timer. and Cache Line Size Register." hexmask.long.byte 0xC 24.--31. 1. "BIST,BIST. This register is used for control and status of BIST. Functions that do not support BIST must hardwire the register to 00h. A Function whose BIST is invoked must not prevent normal operation of the PCI Express Link. Bit descriptions: - [31]:.." newline rbitfld.long 0xC 23. "MULTI_FUNC,Multi-Function Device. - When set indicates that the device may contain multiple Functions but not necessarily. Software is permitted to probe for Functions other than Function 0. - When clear software must not probe for Functions other.." "0,1" newline hexmask.long.byte 0xC 16.--22. 1. "HEADER_TYPE,Header Layout. This field identifies the layout of the second part of the predefined header. The controller uses 000 0001b encoding. The encoding 000 0010b is reserved. This encoding was originally described in the PC Card Standard Electrical.." newline hexmask.long.byte 0xC 8.--15. 1. "LATENCY_MASTER_TIMER,Latency Timer. This register is also referred to as Primary Latency Timer. The Latency Timer was originally described in the PCI Local Bus Specification and the PCI-to-PCI Bridge Architecture Specification. Its functionality does not.." newline hexmask.long.byte 0xC 0.--7. 1. "CACHE_LINE_SIZE,Cache Line Size. The Cache Line Size register is programmed by the system firmware or the operating system to system cache line size. However legacy conventional PCI software may not always be able to program this register correctly.." line.long 0x10 "BAR0_REG,BAR0 Register. System software must build a consistent address map before booting the machine to an operating system. This means it has to determine how much memory is in the system. and how much address space the Functions in the system.." hexmask.long 0x10 4.--31. 1. "BAR0_START,BAR0 Base Address. - Memory Space: Base Address. - IO Space: bits[31:2] are used to map the function into IO space/Base. Address. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R(Sticky)/W(Sticky) if.." newline bitfld.long 0x10 3. "BAR0_PREFETCH,BAR0 Prefetchable. - Memory Space: Set to one if data is pre-fetchable. A Function is permitted to mark a range as prefetchable. If there are no side effects on reads the function returns all bytes on reads regardless of the byte enables.." "0,1" newline bitfld.long 0x10 1.--2. "BAR0_TYPE,BAR0 Type. - Memory Space: Base Address registers that map into Memory Space can be 32 bits or 64 bits wide (to support mapping into a 64-bit address space). The bit encoding is as follows: -- 00: Base register is 32 bits wide and can be mapped.." "Base register is 32 bits wide and can be mapped..,Reserved,?,?" newline bitfld.long 0x10 0. "BAR0_MEM_IO,BAR0 Memory Space Indicator. This bit is used to determine whether the register maps into Memory or I/O Space. Base Address registers that map to Memory Space must return a 0b. Base Address registers that map to I/O Space must return a 1b." "0,1" line.long 0x14 "BAR1_REG,BAR1 Register. System software must build a consistent address map before booting the machine to an operating system. This means it has to determine how much memory is in the system. and how much address space the Functions in the system.." hexmask.long 0x14 4.--31. 1. "BAR1_START,BAR1 Base Address. - Memory Space: Base Address. - IO Space: bits[31:2] are used to map the function into IO space/Base. Address. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R(Sticky)/W(Sticky) if.." newline bitfld.long 0x14 3. "BAR1_PREFETCH,BAR1 Prefetchable. - Memory Space: Set to one if data is pre-fetchable. A Function is permitted to mark a range as prefetchable. If there are no side effects on reads the function returns all bytes on reads regardless of the byte enables.." "0,1" newline bitfld.long 0x14 1.--2. "BAR1_TYPE,BAR1 Type. - Memory Space: Base Address registers that map into Memory Space can be 32 bits or 64 bits wide (to support mapping into a 64-bit address space). The bit encoding is as follows: -- 00: Base register is 32 bits wide and can be mapped.." "Base register is 32 bits wide and can be mapped..,Reserved,?,?" newline bitfld.long 0x14 0. "BAR1_MEM_IO,BAR1 Memory Space Indicator. This bit is used to determine whether the register maps into Memory or I/O Space. Base Address registers that map to Memory Space must return a 0b. Base Address registers that map to I/O Space must return a 1b." "0,1" line.long 0x18 "SEC_LAT_TIMER_SUB_BUS_SEC_BUS_PRI_BUS_REG,Secondary Latency Timer. Subordinate Bus Number. Secondary Bus Number. and Primary Bus Number Register." hexmask.long.byte 0x18 24.--31. 1. "SEC_LAT_TIMER,Secondary Latency Timer. This register does not apply to PCI Express. The controller hardwires it to 00h." newline hexmask.long.byte 0x18 16.--23. 1. "SUB_BUS,Subordinate Bus Number. The Subordinate Bus Number register is used to record the bus number of the highest numbered PCI bus segment which is behind (or subordinate to) the bridge. Configuration software programs the value in this register. The.." newline hexmask.long.byte 0x18 8.--15. 1. "SEC_BUS,Secondary Bus Number. The Secondary Bus Number register is used to record the bus number of the PCI bus segment to which the secondary interface of the bridge is connected. Configuration software programs the value in this register. The bridge.." newline hexmask.long.byte 0x18 0.--7. 1. "PRIM_BUS,Primary Bus Number. This register is not used by PCI Express Functions. It is implemented for compatibility with legacy software." line.long 0x1C "SEC_STAT_IO_LIMIT_IO_BASE_REG,Secondary Status. and I/O Limit and Base Register. The I/O Limit and I/O Base registers are optional and define an address range that is used by the bridge to determine when to forward I/O transactions from one interface to.." bitfld.long 0x1C 31. "SEC_STAT_DPE,Detected Parity Error. This bit is set by a Function when a Poisoned TLP is received by its secondary side regardless of the state the Parity Error Response Enable bit in the Bridge Control register." "0,1" newline bitfld.long 0x1C 30. "SEC_STAT_RCVD_SYS_ERR,Received System Error. This bit is set when the secondary side of a Function receives an ERR_FATAL or ERR_NONFATAL message." "0,1" newline bitfld.long 0x1C 29. "SEC_STAT_RCVD_MSTR_ABRT,Received Master Abort. This bit is set when the secondary side of a Function (for requests initiated by the Type 1 header Function itself) receives a Completion with Unsupported Request Completion status." "0,1" newline bitfld.long 0x1C 28. "SEC_STAT_RCVD_TRGT_ABRT,Received Target Abort. This bit is set when the secondary side of a Function (for requests initiated by the Type 1 header Function itself) receives a Completion with Completer Abort Completion status." "0,1" newline bitfld.long 0x1C 27. "SEC_STAT_SIG_TRGT_ABRT,Signaled Target Abort. This bit is set when the secondary side of the Function (for Requests completed by the Type 1 header Function itself) completes a Posted or Non-Posted request as a Completer Abort error." "0,1" newline rbitfld.long 0x1C 25.--26. "RSVDP_25,Reserved for future use." "0,1,2,3" newline bitfld.long 0x1C 24. "SEC_STAT_MDPE,Master Data Parity Error. This bit is set by a Function if the Parity Error Response Enable bit in the Bridge Control register is set and either of the following two conditions occurs: - Port receives a Poisoned Completion coming Upstream.." "0,1" newline rbitfld.long 0x1C 23. "RSVDP_23,Reserved for future use." "0,1" newline hexmask.long.byte 0x1C 16.--22. 1. "SEC_STAT_RESERV,Reserved." newline hexmask.long.byte 0x1C 12.--15. 1. "IO_LIMIT,I/O Limit Address. These bits correspond to the address[15:12] of IO address range. For the purpose of address decoding the bridge assumes that the lower 12 address bits address[11:0] of the I/O limit address (not implemented in the I/O Limit.." newline rbitfld.long 0x1C 9.--11. "IO_RESERV1,Reserved." "0,1,2,3,4,5,6,7" newline bitfld.long 0x1C 8. "IO_DECODE_BIT8,I/O Addressing Encode (IO Limit Address). This bit encodes the IO addressing capability of the bridge. IO_DECODE_BIT8 indicates the following: - 0h: The bridge supports only 16-bit I/O addressing (for ISA compatibility). For the purpose of.." "0,1" newline hexmask.long.byte 0x1C 4.--7. 1. "IO_BASE,I/O Base Address. These bits correspond to the address[15:12] of IO address range. For the purpose of address decoding the bridge assumes that the lower 12 address bits address[11:0] of the I/O base address (not implemented in the I/O Base.." newline rbitfld.long 0x1C 1.--3. "IO_RESERV,Reserved." "0,1,2,3,4,5,6,7" newline bitfld.long 0x1C 0. "IO_DECODE,I/O Addressing Encode (IO Base Address) This bit encodes the IO addressing capability of the bridge. IO_DECODE indicates the following: - 0h: The bridge supports only 16-bit I/O addressing (for ISA compatibility). For the purpose of address.." "0,1" line.long 0x20 "MEM_LIMIT_MEM_BASE_REG,Memory Limit and Base Register. The Memory Limit and Memory Base registers define a memory mapped address range which is used by the bridge to determine when to forward memory transactions from one interface to the other. If there.." hexmask.long.word 0x20 20.--31. 1. "MEM_LIMIT,Memory Limit Address. These bits correspond to the upper 12 address bits Address[31:20] of 32-bit addresses. For the purpose of address decoding the bridge assumes that the lower 20 address bits Address[19:0] of the memory limit address.." newline hexmask.long.byte 0x20 16.--19. 1. "MEM_LIMIT_RESERV,Reserved." newline hexmask.long.word 0x20 4.--15. 1. "MEM_BASE,Memory Base Address. These bits correspond to the upper 12 address bits Address[31:20] of 32-bit addresses. For the purpose of address decoding the bridge assumes that the lower 20 address bits Address[19:0] of the memory base address (not.." newline hexmask.long.byte 0x20 0.--3. 1. "MEM_BASE_RESERV,Reserved." line.long 0x24 "PREF_MEM_LIMIT_PREF_MEM_BASE_REG,Prefetchable Memory Limit and Base Register. The Prefetchable Memory Limit and Prefetchable Memory Base registers must indicate that 64-bit addresses are supported. as defined in PCI-to-PCI Bridge Architecture.." hexmask.long.word 0x24 20.--31. 1. "PREF_MEM_LIMIT,Prefetchable Memory Limit Address. If the Prefetchable Memory Limit register indicates support for 32-bit addressing then the Prefetchable Limit Upper 32 Bits register is implemented as a read-only register that returns zero when read. If.." newline rbitfld.long 0x24 17.--19. "PREF_RESERV1,Reserved." "0,1,2,3,4,5,6,7" newline rbitfld.long 0x24 16. "PREF_MEM_LIMIT_DECODE,Prefetchable Memory Limit Decode. This bit encodes whether or not the bridge supports 64-bit addresses. Note: This bit is a copy of the PREF_MEM_DECODE bit and always reflects the current value of that bit. The value of.." "0,1" newline hexmask.long.word 0x24 4.--15. 1. "PREF_MEM_BASE,Prefetchable Memory Base Address. If the Prefetchable Memory Base register indicates support for 32-bit addressing then the Prefetchable Base Upper 32 Bits register is implemented as a read-only register that returns zero when read. If the.." newline rbitfld.long 0x24 1.--3. "PREF_RESERV,Reserved." "0,1,2,3,4,5,6,7" newline bitfld.long 0x24 0. "PREF_MEM_DECODE,Prefetchable Memory Base Decode. This bit encodes whether or not the bridge supports 64-bit addresses. Note: By default the bit is set to 1'b1 indicating that 64-bit addresses are supported. If the bridge only supports 32-bit prefetchable.." "0,1" line.long 0x28 "PREF_BASE_UPPER_REG,Prefetchable Base Upper 32 Bits Register. The Prefetchable Base Upper 32 Bits register is an optional extension to the Prefetchable Memory Base register." hexmask.long 0x28 0.--31. 1. "PREF_MEM_BASE_UPPER,Prefetchable Base Upper 32 Bit. If the Prefetchable Memory Base register indicates support for 32-bit addressing then this register is implemented as read-only register that returns zero when read. If the Prefetchable Memory Base.." line.long 0x2C "PREF_LIMIT_UPPER_REG,Prefetchable Limit Upper 32 Bits Register. The Prefetchable Limit Upper 32 Bits register is an optional extension to the Prefetchable Memory Limit register." hexmask.long 0x2C 0.--31. 1. "PREF_MEM_LIMIT_UPPER,Prefetchable Limit Upper 32 Bit. If the Prefetchable Memory Limit register indicate support for 64-bit addressing then this register is implemented as read/write register which must be initialized by configuration software. This.." rgroup.long 0x30++0x3 line.long 0x0 "IO_LIMIT_UPPER_IO_BASE_UPPER_REG,I/O Limit and Base Upper 16 Bits Register. The I/O Limit Upper 16 Bits and I/O Base Upper 16 Bits registers are optional extensions to the I/O Limit and I/O Base registers." hexmask.long.word 0x0 16.--31. 1. "IO_LIMIT_UPPER,I/O Limit Upper 16 Bits. If the I/O Limit register indicates support for 16-bit I/O address decoding then this register is implemented as a read-only register which return zero when read. If the I/O Limit register indicates support for.." newline hexmask.long.word 0x0 0.--15. 1. "IO_BASE_UPPER,I/O Base Upper 16 Bits. If the I/O Base register indicates support for 16-bit I/O address decoding then this register is implemented as a read-only register which return zero when read. If the I/O base register indicates support for 32-bit.." group.long 0x34++0xB line.long 0x0 "TYPE1_CAP_PTR_REG,Capabilities Pointer Register." hexmask.long.tbyte 0x0 8.--31. 1. "RSVDP_8,Reserved for future use." newline hexmask.long.byte 0x0 0.--7. 1. "CAP_POINTER,Capabilities Pointer. This register is used to point to a linked list of capabilities implemented by this Function. Since all PCI Express Functions are required to implement the PCI Express Capability structure this register must point to a.." line.long 0x4 "TYPE1_EXP_ROM_BASE_REG,Expansion ROM Base Address Register. This register is defined to handle the base address and size information for this expansion ROM. The mask for this ROM BAR exists (if implemented) as a shadow register at this address. The.." hexmask.long.tbyte 0x4 11.--31. 1. "EXP_ROM_BASE_ADDRESS,Expansion ROM Base Address. Upper 21 bits of the Expansion ROM base address. The number of bits (out of these 21) that a Function actually implements depends on how much address space the Function requires. The mask for this ROM BAR.." newline hexmask.long.word 0x4 1.--10. 1. "RSVDP_1,Reserved for future use." newline bitfld.long 0x4 0. "ROM_BAR_ENABLE,Expansion ROM Enable. This bit controls whether or not the Function accepts accesses to its expansion ROM. When this bit is 0b the Function's expansion ROM address space is disabled. When the bit is 1b address decoding is enabled using.." "0,1" line.long 0x8 "BRIDGE_CTRL_INT_PIN_INT_LINE_REG,Bridge Control. Interrupt Pin. and Interrupt Line Register." hexmask.long.word 0x8 23.--31. 1. "BRIDGE_CTRL_RESERV,Reserved." newline bitfld.long 0x8 22. "SBR,Secondary Bus Reset. Setting this bit triggers a hot reset on the corresponding PCI Express Port. Software must ensure a minimum reset duration (Trst) as defined in the PCI Local Bus Specification. Software and systems must honor.." "0,1" newline rbitfld.long 0x8 21. "MSTR_ABORT_MODE,Master Abort Mode. This bit was originally described in the PCI-to-PCI Bridge Architecture Specification. Its functionality does not apply to PCI Express. The controller hardwires this bit to 0b. Note: The access attributes of this field.." "0,1" newline rbitfld.long 0x8 20. "VGA_16B_DEC,VGA 16 bit decode. This bit only has meaning if VGA Enable bit is set. This bit enables system configuration software to select between 10-bit and 16-bit I/O address decoding for all VGA I/O register accesses that are forwarded from primary.." "0,1" newline rbitfld.long 0x8 19. "VGA_EN,VGA Enable. Modifies the response by the bridge to VGA compatible addresses. If the VGA Enable bit is set the bridge will positively decode and forward the following accesses on the primary interface to the secondary interface (and conversely.." "0,1" newline bitfld.long 0x8 18. "ISA_EN,ISA Enable. Modifies the response by the bridge to ISA I/O addresses. This applies only to I/O addresses that are enabled by the I/O Base and I/O Limit registers and are in the first 64 KB of I/O address space (0000 0000h to 0000 FFFFh). If this.." "?,KB block" newline bitfld.long 0x8 17. "SERR_EN,SERR# Enable. This bit controls forwarding of ERR_COR ERR_NONFATAL and ERR_FATAL from secondary to primary." "0,1" newline bitfld.long 0x8 16. "PERE,Parity Error Response Enable. This bit controls the logging of poisoned TLPs in the Master Data Parity Error bit in the Secondary Status register." "0,1" newline hexmask.long.byte 0x8 8.--15. 1. "INT_PIN,Interrupt PIN. The Interrupt Pin register register that identifies the legacy interrupt Message(s) the Function uses. Valid values are: - 01h 02h 03h and 04h: map to legacy interrupt Messages for INTA INTB INTC and INTD respectively. - 00h:.." newline hexmask.long.byte 0x8 0.--7. 1. "INT_LINE,Interrupt Line. The Interrupt Line register communicates interrupt line routing information. The register must be implemented by any Function that uses an interrupt pin. Values in this register are programmed by system software and are system.." tree.end tree "PF0_SPCIE_CAP (Secondary PCI Express Capability Structure)" group.long (0x0+0x1A0)++0xF line.long 0x0 "SPCIE_CAP_HEADER_REG,SPCIE Capability Header. For a description of this standard PCIe register. see the PCI Express Specification." hexmask.long.word 0x0 20.--31. 1. "NEXT_OFFSET,Next Capability Offset. For a description of this standard PCIe register field see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky).." hexmask.long.byte 0x0 16.--19. 1. "CAP_VERSION,Capability Version. For a description of this standard PCIe register field see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else.." hexmask.long.word 0x0 0.--15. 1. "EXTENDED_CAP_ID,Secondary PCI Express Extended Capability ID. For a description of this standard PCIe register field see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN.." line.long 0x4 "LINK_CONTROL3_REG,Link Control 3 Register. For a description of this standard PCIe register. see the PCI Express Specification." hexmask.long 0x4 2.--31. 1. "RSVDP_2,Reserved for future use." bitfld.long 0x4 1. "EQ_REQ_INT_EN,Link Equalization Request Interrupt Enable. For a description of this standard PCIe register field see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" "0,1" bitfld.long 0x4 0. "PERFORM_EQ,Perform Equalization. For a description of this standard PCIe register field see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" "0,1" line.long 0x8 "LANE_ERR_STATUS_REG,Lane Error Status Register. For a description of this standard PCIe register. see the PCI Express Specification." hexmask.long 0x8 2.--31. 1. "RSVDP_LANE_ERR_STATUS,Reserved for future use." bitfld.long 0x8 0.--1. "LANE_ERR_STATUS,Lane Error Status Bits per Lane. For a description of this standard PCIe register field see the PCI Express Specification." "0,1,2,3" line.long 0xC "SPCIE_CAP_OFF_0CH_REG,Lane Equalization Control Register for lanes 1 and 0. For a description of this standard PCIe register. see the PCI Express Specification." rbitfld.long 0xC 31. "RSVDP_31,Reserved for future use." "0,1" bitfld.long 0xC 28.--30. "USP_RX_PRESET_HINT1,Upstream Port 8.0 GT/s Receiver Preset Hint 1. The write value is gated with the PCIE_CAP_CROSS_LINK_SUPPORT field of LINK_CAPABILITIES2_REG. For a description of this standard PCIe register field see the PCI Express Specification." "0,1,2,3,4,5,6,7" hexmask.long.byte 0xC 24.--27. 1. "USP_TX_PRESET1,Upstream Port 8.0 GT/s Transmitter Preset 1. The write value is gated with the PCIE_CAP_CROSS_LINK_SUPPORT field of LINK_CAPABILITIES2_REG. For a description of this standard PCIe register field see the PCI Express Specification. Note:.." rbitfld.long 0xC 23. "RSVDP_23,Reserved for future use." "0,1" newline bitfld.long 0xC 20.--22. "DSP_RX_PRESET_HINT1,Downstream Port 8.0 GT/s Receiver Preset Hint 1. For a description of this standard PCIe register field see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if.." "0,1,2,3,4,5,6,7" hexmask.long.byte 0xC 16.--19. 1. "DSP_TX_PRESET1,Downstream Port 8.0 GT/s Transmitter Preset 1. For a description of this standard PCIe register field see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN.." rbitfld.long 0xC 15. "RSVDP_15,Reserved for future use." "0,1" bitfld.long 0xC 12.--14. "USP_RX_PRESET_HINT0,Upstream Port 8.0 GT/s Receiver Preset Hint 0. The write value is gated with the PCIE_CAP_CROSS_LINK_SUPPORT field of LINK_CAPABILITIES2_REG. For a description of this standard PCIe register field see the PCI Express Specification." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0xC 8.--11. 1. "USP_TX_PRESET0,Upstream Port 8.0 GT/s Transmitter Preset 0. The write value is gated with the PCIE_CAP_CROSS_LINK_SUPPORT field of LINK_CAPABILITIES2_REG. For a description of this standard PCIe register field see the PCI Express Specification. Note:.." rbitfld.long 0xC 7. "RSVDP_7,Reserved for future use." "0,1" bitfld.long 0xC 4.--6. "DSP_RX_PRESET_HINT0,Downstream Port 8.0 GT/s Receiver Preset Hint 0. For a description of this standard PCIe register field see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if.." "0,1,2,3,4,5,6,7" hexmask.long.byte 0xC 0.--3. 1. "DSP_TX_PRESET0,Downstream Port 8.0 GT/s Transmitter Preset 0. For a description of this standard PCIe register field see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN.." tree.end tree "PF0_L1SUB_CAP (L1 Substates Capability Structure)" group.long (0x0+0x2E8)++0xF line.long 0x0 "L1SUB_CAP_HEADER_REG,L1 Substates Extended Capability Header. This register provides capbility ID. capability version and next offset value for L1 Substates." hexmask.long.word 0x0 20.--31. 1. "NEXT_OFFSET,Next Capability Offset. This field contains the offset to the next PCI Express Capability structure or 000h if no other items exist in the linked list of Capabilities. For Extended Capabilities implemented in Configuration Space this offset.." hexmask.long.byte 0x0 16.--19. 1. "CAP_VERSION,Capability Version. This field is a PCI-SIG defined version number that indicates the version of the Capability structure present. This field is depends on version of the specification. Note: The access attributes of this field are as.." hexmask.long.word 0x0 0.--15. 1. "EXTENDED_CAP_ID,L1SUB Extended Capability ID. This field is a PCI-SIG defined ID number that indicates the nature and format of the Extended Capability. Extended Capability ID for L1 PM Substates is 001Eh. Note: The access attributes of this field are as.." line.long 0x4 "L1SUB_CAPABILITY_REG,L1 Substates Capability Register. This register provides extended capability of L1 Substates." hexmask.long.byte 0x4 24.--31. 1. "RSVDP_24,Reserved for future use." hexmask.long.byte 0x4 19.--23. 1. "PWR_ON_VALUE_SUPPORT,Port T Power On Value. Along with the Port T_POWER_ON Scale field in the L1 PM Substates Capabilities register sets the time (in us) that this Port requires the port on the opposite side of Link to wait in L1.2.Exit after sampling.." rbitfld.long 0x4 18. "RSVDP_18,Reserved for future use." "0,1" bitfld.long 0x4 16.--17. "PWR_ON_SCALE_SUPPORT,Port T Power On Scale. Specifies the scale used for the Port T_POWER_ON Value field in the L1 PM Substates Capabilities register. Range of values are given below. Required for all Ports for which either the PCI-PM L1.2 Supported bit.." "?,?,?,Reserved" newline hexmask.long.byte 0x4 8.--15. 1. "COMM_MODE_SUPPORT,Port Common Mode Restore Time. Time (in us) required for this Port to re-establish common mode. Required for all Ports for which either the PCI-PM L1.2 Supported bit is Set ASPM L1.2 Supported bit is Set or both are Set otherwise.." rbitfld.long 0x4 5.--7. "RSVDP_5,Reserved for future use." "0,1,2,3,4,5,6,7" bitfld.long 0x4 4. "L1_PMSUB_SUPPORT,L1 PM Substates ECN Supported. When Set this bit indicates that this Port supports L1 PM Substates. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W (sticky)" "0,1" bitfld.long 0x4 3. "L1_1_ASPM_SUPPORT,ASPM L11 Supported. When Set this bit indicates that ASPM L1.1 is supported. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W (sticky)" "0,1" newline bitfld.long 0x4 2. "L1_2_ASPM_SUPPORT,ASPM L12 Supported. When Set this bit indicates that ASPM L1.2 is supported. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W (sticky)" "0,1" bitfld.long 0x4 1. "L1_1_PCIPM_SUPPORT,PCI-PM L11 Supported. When Set this bit indicates that PCI-PM L1.1 is supported and must be Set by all Ports implementing L1 PM Substates. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W (sticky)" "0,1" bitfld.long 0x4 0. "L1_2_PCIPM_SUPPORT,PCI-PM L12 Supported. When Set this bit indicates that PCI-PM L1.2 is supported. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W (sticky)" "0,1" line.long 0x8 "L1SUB_CONTROL1_REG,L1 Substates Control 1 Register. This register provides Controls to extended capability." bitfld.long 0x8 29.--31. "L1_2_TH_SCA,LTR L12 Threshold Scale. This field provides a scale for the value contained within the LTR_L1.2_THRESHOLD_Value.The default value for this field is 000b.Hardware operation is undefined if software writes a Not-Permitted value to this field." "0,1,2,3,4,5,6,7" rbitfld.long 0x8 26.--28. "RSVDP_26,Reserved for future use." "0,1,2,3,4,5,6,7" hexmask.long.word 0x8 16.--25. 1. "L1_2_TH_VAL,LTR L12 Threshold Value. Along with the LTR_L1.2_THRESHOLD_Scale this field indicates the LTR threshold used to determine if entry into L1 results in L1.1 (if enabled) or L1.2 (if enabled). The default value for this field is 00 0000 0000b." hexmask.long.byte 0x8 8.--15. 1. "T_COMMON_MODE,Common Mode Restore Time. Sets value of TCOMMONMODE (in us) which must be used by the Downstream Ports for timing the re-establishment of common mode.This field is of type RsvdP for Upstream Ports. Default value is implementation.." newline hexmask.long.byte 0x8 4.--7. 1. "RSVDP_4,Reserved for future use." bitfld.long 0x8 3. "L1_1_ASPM_EN,ASPM L11 Enable. When Set this bit enables ASPM L1.1.For Ports for which the ASPM L1.1 Supported bit is Clear this bit is permitted to be hardwired to 0.Default value is 0b." "0,1" bitfld.long 0x8 2. "L1_2_ASPM_EN,ASPM L12 Enable. When Set this bit enables ASPM L1.2.For Ports for which the ASPM L1.2 Supported bit is Clear this bit is permitted to be hardwired to 0.Default value is 0b." "0,1" bitfld.long 0x8 1. "L1_1_PCIPM_EN,PCI-PM L11 Enable. When Set this bit enables PCI-PM L1.1. Default value is 0b." "0,1" newline bitfld.long 0x8 0. "L1_2_PCIPM_EN,PCI-PM L12 Enable. When Set this bit enables PCI-PM L1.2.For Ports for which the PCI-PM L1.2 Supported bit is Clear this bit is permitted to be hardwired to 0.Default value is 0b." "0,1" line.long 0xC "L1SUB_CONTROL2_REG,L1 Substates Control 2 Register. This register provides Controls to extended capability." hexmask.long.tbyte 0xC 8.--31. 1. "RSVDP_8,Reserved for future use." hexmask.long.byte 0xC 3.--7. 1. "T_POWER_ON_VALUE,T Power On Value. Along with the T_POWER_ON Scale sets the minimum amount of time (in us) that the Port must wait in L1.2.Exit after sampling CLKREQ# asserted before actively driving the interface.Default value is 00101b. T_POWER_ON is.." rbitfld.long 0xC 2. "RSVDP_2,Reserved for future use." "0,1" bitfld.long 0xC 0.--1. "T_POWER_ON_SCALE,T Power On Scale. Specifies the scale used for T_POWER_ON Value. Range of values are given below. Required for all Ports that support L1.2 otherwise this field is of type RsvdP. This field must only be modified when the ASPM L1.2 Enable.." "?,?,?,Reserved" tree.end tree "PF0_RAS_DES_CAP (RAS D.E.S. Capability Structure (VSEC))" group.long (0x0+0x30C)++0x3 line.long 0x0 "RAS_DES_CAP_HEADER_REG,Vendor-Specific Extended Capability Header. For a description of this standard PCIe register. see the PCI Express Specification." hexmask.long.word 0x0 20.--31. 1. "NEXT_OFFSET,Next Capability Offset. For a description of this standard PCIe register field see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky).." newline hexmask.long.byte 0x0 16.--19. 1. "CAP_VERSION,Capability Version. For a description of this standard PCIe register field see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else.." newline hexmask.long.word 0x0 0.--15. 1. "EXTENDED_CAP_ID,PCI Express Extended Capability ID. For a description of this standard PCIe register field see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then.." rgroup.long (0x4+0x30C)++0x3 line.long 0x0 "VENDOR_SPECIFIC_HEADER_REG,Vendor-Specific Header. For a description of this standard PCIe register. see the PCI Express Specification." hexmask.long.word 0x0 20.--31. 1. "VSEC_LENGTH,VSEC Length. For a description of this standard PCIe register field see the PCI Express Specification." newline hexmask.long.byte 0x0 16.--19. 1. "VSEC_REV,VSEC Rev. For a description of this standard PCIe register field see the PCI Express Specification." newline hexmask.long.word 0x0 0.--15. 1. "VSEC_ID,VSEC ID. For a description of this standard PCIe register field see the PCI Express Specification." group.long (0x8+0x30C)++0x3 line.long 0x0 "EVENT_COUNTER_CONTROL_REG,Event Counter Control. This is a viewport control register. - Setting the EVENT_COUNTER_EVENT_SELECT and EVENT_COUNTER_LANE_SELECT fields in this register determine the Event Counter data returned by the EVENT_COUNTER_DATA_REG.." hexmask.long.byte 0x0 28.--31. 1. "RSVDP_28,Reserved for future use." newline hexmask.long.word 0x0 16.--27. 1. "EVENT_COUNTER_EVENT_SELECT,Event Counter Data Select. This field in conjunction with the EVENT_COUNTER_LANE_SELECT field indexes the Event Counter data returned by the EVENT_COUNTER_DATA_REG register. - 27-24: Group number(4-bit: 0..0x7) - 23-16: Event.." newline hexmask.long.byte 0x0 12.--15. 1. "RSVDP_12,Reserved for future use." newline hexmask.long.byte 0x0 8.--11. 1. "EVENT_COUNTER_LANE_SELECT,Event Counter Lane Select. This field in conjunction with EVENT_COUNTER_EVENT_SELECT indexes the Event Counter data returned by the EVENT_COUNTER_DATA_REG register. - 0x0: Lane0 - 0x1: Lane1 - 0x2: Lane2 - .. - 0xF: Lane15 Note:.." newline rbitfld.long 0x0 7. "EVENT_COUNTER_STATUS,Event Counter Status. This register returns the current value of the Event Counter selected by the following fields: - EVENT_COUNTER_EVENT_SELECT - EVENT_COUNTER_LANE_SELECT Note: This register field is sticky." "0,1" newline rbitfld.long 0x0 5.--6. "RSVDP_5,Reserved for future use." "0,1,2,3" newline bitfld.long 0x0 2.--4. "EVENT_COUNTER_ENABLE,Event Counter Enable. Enables/disables the Event Counter selected by the EVENT_COUNTER_EVENT_SELECT and EVENT_COUNTER_LANE_SELECT fields in this register. By default all event counters are disabled. You can enable/disable a specific.." "no change,per event off,?,?,?,?,?,?" newline bitfld.long 0x0 0.--1. "EVENT_COUNTER_CLEAR,Event Counter Clear. Clears the Event Counter selected by the EVENT_COUNTER_EVENT_SELECT and EVENT_COUNTER_LANE_SELECT fields in this register. You can clear the value of a specific Event Counter by writing the 'per clear' code and.." "no change,per clear,?,?" rgroup.long (0xC+0x30C)++0x3 line.long 0x0 "EVENT_COUNTER_DATA_REG,Event Counter Data. This viewport register returns the data selected by the following fields: - EVENT_COUNTER_EVENT_SELECT in EVENT_COUNTER_CONTROL_REG - EVENT_COUNTER_LANE_SELECT in EVENT_COUNTER_CONTROL_REG For more details. see.." hexmask.long 0x0 0.--31. 1. "EVENT_COUNTER_DATA,Event Counter Data. This register returns the data selected by the following fields: - EVENT_COUNTER_EVENT_SELECT in EVENT_COUNTER_CONTROL_REG - EVENT_COUNTER_LANE_SELECT in EVENT_COUNTER_CONTROL_REG Note: This register field is sticky." group.long (0x10+0x30C)++0x3 line.long 0x0 "TIME_BASED_ANALYSIS_CONTROL_REG,Time-based Analysis Control. Used for controlling the measurement of RX/TX data throughput and time spent in each low-power LTSSM state. For more details. see the RAS DES section in the Core Operations chapter of the.." hexmask.long.byte 0x0 24.--31. 1. "TIME_BASED_REPORT_SELECT,Time-based Report Select. Selects what type of data is measured for the selected duration (TIME_BASED_DURATION_SELECT) and returned in TIME_BASED_ANALYSIS_DATA. Each type of data is measured using one of three types of units: -.." newline hexmask.long.byte 0x0 16.--23. 1. "RSVDP_16,Reserved for future use." newline hexmask.long.byte 0x0 8.--15. 1. "TIME_BASED_DURATION_SELECT,Time-based Duration Select. Selects the duration of time-based analysis. When 'manual control' is selected and TIMER_START is set to '1' this analysis never stops until TIMER_STOP is set to '0'. - 0x0: Manual control - 0x1:.." newline hexmask.long.byte 0x0 1.--7. 1. "RSVDP_1,Reserved for future use." newline bitfld.long 0x0 0. "TIMER_START,Timer Start. - 1: Start/Restart - 0: Stop This bit will be cleared automatically when the measurement is finished. Note: The app_ras_des_tba_ctrl input also sets the contents of this field and controls the measurement start/stop. Note: This.." "Stop,Start/Restart" rgroup.long (0x14+0x30C)++0x7 line.long 0x0 "TIME_BASED_ANALYSIS_DATA_REG,Time-based Analysis Data. Contains the measurement results of RX/TX data throughput and time spent in each low-power LTSSM state. This viewport register returns the data selected by the TIME_BASED_REPORT_SELECT field in.." hexmask.long 0x0 0.--31. 1. "TIME_BASED_ANALYSIS_DATA,Time Based Analysis Data. This register returns the data selected by the TIME_BASED_REPORT_SELECT field in TIME_BASED_ANALYSIS_CONTROL_REG. The results are cleared when next measurement starts. Note: This register field is sticky." line.long 0x4 "TIME_BASED_ANALYSIS_DATA_63_32_REG,Upper 32 bits of Time-based Analysis Data. This viewport register returns the data selected by the TIME_BASED_REPORT_SELECT field in TIME_BASED_ANALYSIS_CONTROL_REG. For more details. see the RAS DES section in the Core.." hexmask.long 0x4 0.--31. 1. "TIME_BASED_ANALYSIS_DATA_63_32,Upper 32 bits of Time Based Analysis Data. Note: This register field is sticky." group.long (0x30+0x30C)++0x5F line.long 0x0 "EINJ_ENABLE_REG,Error Injection Enable. Each type of error insertion is enabled by the corresponding bit in this register. The specific injection controls for each type of error are defined in the following registers: - 0: CRC Error: EINJ0_CRC_REG - 1:.." hexmask.long 0x0 7.--31. 1. "RSVDP_7,Reserved for future use." newline bitfld.long 0x0 6. "ERROR_INJECTION6_ENABLE,Error Injection6 Enable (Specific TLP Error). Enables insertion of errors into the packets that you select. You can set this bit to '1' when you have disabled RAS datapath protection (DP) by setting CX_RASDP = CX_RASDP_RAM_PROT.." "0,1" newline bitfld.long 0x0 5. "ERROR_INJECTION5_ENABLE,Error Injection5 Enable (TLP Duplicate/Nullify Error). Enables insertion of duplicate/nullified TLPs. For more details see the EINJ5_SP_TLP_REG register. Note: This register field is sticky." "0,1" newline bitfld.long 0x0 4. "ERROR_INJECTION4_ENABLE,Error Injection4 Enable (FC Credit Update Error). Enables insertion of errors into UpdateFCs. For more details see the EINJ4_FC_REG register. Note: This register field is sticky." "0,1" newline bitfld.long 0x0 3. "ERROR_INJECTION3_ENABLE,Error Injection3 Enable (Symbol DataK Mask Error or Sync Header Error). Enables DataK masking of special symbols or the breaking of the sync header. For more details see the EINJ3_SYMBOL_REG register. Note: This register field is.." "0,1" newline bitfld.long 0x0 2. "ERROR_INJECTION2_ENABLE,Error Injection2 Enable (DLLP Error). Enables insertion of DLLP errors. For more details see the EINJ2_DLLP_REG register. Note: This register field is sticky." "0,1" newline bitfld.long 0x0 1. "ERROR_INJECTION1_ENABLE,Error Injection1 Enable (Sequence Number Error). Enables insertion of errors into sequence numbers. For more details see the EINJ1_SEQNUM_REG register. Note: This register field is sticky." "0,1" newline bitfld.long 0x0 0. "ERROR_INJECTION0_ENABLE,Error Injection0 Enable (CRC Error). Enables insertion of errors into various CRC. For more details see the EINJ0_CRC_REG register. Note: This register field is sticky." "0,1" line.long 0x4 "EINJ0_CRC_REG,Error Injection Control 0 (CRC Error). Controls the insertion of errors into the CRC. and parity of ordered sets for the selected type of the packets as follows: - LCRC. Bad TLP will be detected at the receiver side; receiver responds with.." hexmask.long.tbyte 0x4 12.--31. 1. "RSVDP_12,Reserved for future use." newline hexmask.long.byte 0x4 8.--11. 1. "EINJ0_CRC_TYPE,Error injection type. Selects the type of CRC error to be inserted. Tx Path - 0000b: New TLP's LCRC error injection - 0001b: 16bCRC error injection of ACK/NAK DLLP - 0010b: 16bCRC error injection of Update-FC DLLP - 0011b: New TLP's ECRC.." newline hexmask.long.byte 0x4 0.--7. 1. "EINJ0_COUNT,Error injection count. Indicates the number of errors. This register is decremented when the errors have been inserted. - If the counter value is 0x01 and error is inserted ERROR_INJECTION0_ENABLE in EINJ_ENABLE_REG returns 0b. - If the.." line.long 0x8 "EINJ1_SEQNUM_REG,Error Injection Control 1 (Sequence Number Error). Controls the sequence number of the specific TLPs and ACK/NAK DLLPs. Data Link Protocol Error will be detected at the Rx side of ACK/NAL DLLPs when one of these conditions is true: -.." rbitfld.long 0x8 29.--31. "RSVDP_29,Reserved for future use." "0,1,2,3,4,5,6,7" newline hexmask.long.word 0x8 16.--28. 1. "EINJ1_BAD_SEQNUM,Bad sequence number. Indicates the value to add/subtract from the naturally-assigned sequence numbers. This value is represented by two's complement. - 0x0FFF: +4095 - .. - 0x0002: +2 - 0x0001: +1 - 0x0000: 0 - 0x1FFF: -1 - 0x1FFE: -2 -.." newline hexmask.long.byte 0x8 9.--15. 1. "RSVDP_9,Reserved for future use." newline bitfld.long 0x8 8. "EINJ1_SEQNUM_TYPE,Sequence number type. Selects the type of sequence number. - 0b: Insertion of New TLP's SEQ# error - 1b: Insertion of ACK/NAK DLLP's SEQ# Error Note: This register field is sticky." "0,1" newline hexmask.long.byte 0x8 0.--7. 1. "EINJ1_COUNT,Error injection count. Indicates the number of errors. This register is decremented as the errors are being inserted. - If the counter value is 0x01 and error is inserted ERROR_INJECTION1_ENABLE in EINJ_ENABLE_REG returns '0'. - If the.." line.long 0xC "EINJ2_DLLP_REG,Error Injection Control 2 (DLLP Error). Controls the transmission of DLLPs and inserts the following errors: - If 'ACK/NAK DLLP's transmission block' is selected. replay timeout error will occur at the transmitter of the TLPs and then Data.." hexmask.long.tbyte 0xC 10.--31. 1. "RSVDP_10,Reserved for future use." newline bitfld.long 0xC 8.--9. "EINJ2_DLLP_TYPE,DLLP Type. Selects the type of DLLP errors to be inserted. - 00b: ACK/NAK DLLP's transmission block - 01b: Update FC DLLP's transmission block - 10b: Always Transmission for NAK DLLP - 11b: Reserved Note: This register field is sticky." "0,1,2,3" newline hexmask.long.byte 0xC 0.--7. 1. "EINJ2_COUNT,Error injection count. Indicates the number of errors. This register is decremented as the errors are being inserted. - If the counter value is 0x01 and the error is inserted ERROR_INJECTION2_ENABLE in EINJ_ENABLE_REG returns '0'. - If the.." line.long 0x10 "EINJ3_SYMBOL_REG,Error Injection Control 3 (Symbol Error). When 8b/10b encoding is used. this register controls error insertion into the special (K code) symbols. - If TS1/TS2/FTS/E-Idle/SKP is selected. it affects whole of the ordered set. It might.." hexmask.long.tbyte 0x10 11.--31. 1. "RSVDP_11,Reserved for future use." newline bitfld.long 0x10 8.--10. "EINJ3_SYMBOL_TYPE,Error Type. 8b/10b encoding - Mask K symbol. It is not supported to insert errors into the first ordered-set after exiting from TxElecIdle when CX_FREQ_STEP_EN has been enabled. - 000b: Reserved - 001b: COM/PAD(TS1 Order set) - 010b:.." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x10 0.--7. 1. "EINJ3_COUNT,Error injection count. Indicates the number of errors. This register is decremented as the errors are being inserted. - If the counter value is 0x01 and error is inserted ERROR_INJECTION3_ENABLE in EINJ_ENABLE_REG returns '0'. - If the.." line.long 0x14 "EINJ4_FC_REG,Error Injection Control 4 (FC Credit Error). Controls error insertion into the credit value in the UpdateFCs. It is possible to insert errors for any of the following types: - Posted TLP Header credit - Non-Posted TLP Header credit -.." rbitfld.long 0x14 29.--31. "RSVDP_29,Reserved for future use." "0,1,2,3,4,5,6,7" newline hexmask.long.word 0x14 16.--28. 1. "EINJ4_BAD_UPDFC_VALUE,Bad update-FC credit value. Indicates the value to add/subtract from the UpdateFC credit. This value is represented by two's complement. - 0x0FFF: +4095 - .. - 0x0002: +2 - 0x0001: +1 - 0x0000: 0 - 0x1FFF: -1 - 0x1FFE: -2 - .. -.." newline rbitfld.long 0x14 15. "RSVDP_15,Reserved for future use." "0,1" newline bitfld.long 0x14 12.--14. "EINJ4_VC_NUMBER,VC Number. Indicates target VC Number. Note: This register field is sticky." "0,1,2,3,4,5,6,7" newline rbitfld.long 0x14 11. "RSVDP_11,Reserved for future use." "0,1" newline bitfld.long 0x14 8.--10. "EINJ4_UPDFC_TYPE,Update-FC type. Selects the credit type. - 000b: Posted TLP Header Credit value control - 001b: Non-Posted TLP Header Credit value control - 010b: Completion TLP Header Credit value control - 011b: Reserved - 100b: Posted TLP Data Credit.." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x14 0.--7. 1. "EINJ4_COUNT,Error injection count. Indicates the number of errors. This register is decremented as the errors are being inserted. - If the counter value is 0x01 and error is inserted ERROR_INJECTION4_ENABLE in EINJ_ENABLE_REG returns '0'. - If the.." line.long 0x18 "EINJ5_SP_TLP_REG,Error Injection Control 5 (Specific TLP Error). Controls the generation of specified TLPs. Correctable errors will occur which will be fixed by the PCIe protocol. - For Duplicate TLP. the controller initiates Data Link Retry by handling.." hexmask.long.tbyte 0x18 9.--31. 1. "RSVDP_9,Reserved for future use." newline bitfld.long 0x18 8. "EINJ5_SPECIFIED_TLP,Specified TLP. Selects the specified TLP to be inserted. - 0: Generates duplicate TLPs by handling ACK DLLP as NAK DLLP. - 1: Generates Nullified TLP (Original TLP will be stored in retry buffer). Note: This register field is sticky." "Generates duplicate TLPs by handling ACK DLLP as..,Generates Nullified TLP" newline hexmask.long.byte 0x18 0.--7. 1. "EINJ5_COUNT,Error injection count. Indicates the number of errors. This register is decremented as the errors are being inserted. - If the counter value is 0x01 and error is inserted ERROR_INJECTION5_ENABLE in EINJ_ENABLE_REG returns '0'. - If the.." line.long 0x1C "EINJ6_COMPARE_POINT_H0_REG,Error Injection Control 6 (Compare Point Header DWORD #0). Program this register for the 1st DWORD of TLP header/prefix. It is necessary to carefully consider the endianness when you program this register. Bits [31:0] =.." hexmask.long 0x1C 0.--31. 1. "EINJ6_COMPARE_POINT_H0,Packet Compare Point: 1st DWORD. Specifies which Tx TLP header DWORD#0 bits to compare with the corresponding bits in the Packet Compare Value registers (EINJ6_COMPARE_VALUE*). When all specified bits (in the Tx TLP header and.." line.long 0x20 "EINJ6_COMPARE_POINT_H1_REG,Error Injection Control 6 (Compare Point Header DWORD #1). Program this register for the 2nd DWORD of TLP header/prefix. It is necessary to carefully consider the endianness when you program this register. Bits [31:0] =.." hexmask.long 0x20 0.--31. 1. "EINJ6_COMPARE_POINT_H1,Packet Compare Point: 2nd DWORD. Specifies which Tx TLP header DWORD#1 bits to compare with the corresponding bits in the Packet Compare Value registers (EINJ6_COMPARE_VALUE*). When all specified bits (in the Tx TLP header and.." line.long 0x24 "EINJ6_COMPARE_POINT_H2_REG,Error Injection Control 6 (Compare Point Header DWORD #2). Program this register for the 3rd DWORD of TLP header/prefix. It is necessary to carefully consider the endianness when you program this register. Bits [31:0] =.." hexmask.long 0x24 0.--31. 1. "EINJ6_COMPARE_POINT_H2,Packet Compare Point: 3rd DWORD. Specifies which Tx TLP header DWORD#2 bits to compare with the corresponding bits in the Packet Compare Value registers (EINJ6_COMPARE_VALUE*). When all specified bits (in the Tx TLP header and.." line.long 0x28 "EINJ6_COMPARE_POINT_H3_REG,Error Injection Control 6 (Compare Point Header DWORD #3). Program this register for the 4th DWORD of TLP header/prefix. It is necessary to carefully consider the endianness when you program this register. Bits [31:0] =.." hexmask.long 0x28 0.--31. 1. "EINJ6_COMPARE_POINT_H3,Packet Compare Point: 4th DWORD. Specifies which Tx TLP header DWORD#3 bits to compare with the corresponding bits in the Packet Compare Value registers (EINJ6_COMPARE_VALUE*). When all specified bits (in the Tx TLP header and.." line.long 0x2C "EINJ6_COMPARE_VALUE_H0_REG,Error Injection Control 6 (Compare Value Header DWORD #0). Program this register for the 1st DWORD of TLP header/prefix. It is necessary to carefully consider the endianness when you program this register. Bits [31:0] =.." hexmask.long 0x2C 0.--31. 1. "EINJ6_COMPARE_VALUE_H0,Packet Compare Value: 1st DWORD. Specifies the value to compare against Tx the TLP header DWORD#0 bits specified in the Packet Compare Point registers (EINJ6_COMPARE_POINT*). Note: This register field is sticky." line.long 0x30 "EINJ6_COMPARE_VALUE_H1_REG,Error Injection Control 6 (Compare Value Header DWORD #1). Program this register for the 2nd DWORD of TLP header/prefix. It is necessary to carefully consider the endianness when you program this register. Bits [31:0] =.." hexmask.long 0x30 0.--31. 1. "EINJ6_COMPARE_VALUE_H1,Packet Compare Value: 2nd DWORD. Specifies the value to compare against Tx the TLP header DWORD#1 bits specified in the Packet Compare Point registers (EINJ6_COMPARE_POINT*). Note: This register field is sticky." line.long 0x34 "EINJ6_COMPARE_VALUE_H2_REG,Error Injection Control 6 (Compare Value Header DWORD #2). Program this register for the 3rd DWORD of TLP header/prefix. It is necessary to carefully consider the endianness when you program this register. Bits [31:0] =.." hexmask.long 0x34 0.--31. 1. "EINJ6_COMPARE_VALUE_H2,Packet Compare Value: 3rd DWORD. Specifies the value to compare against Tx the TLP header DWORD#2 bits specified in the Packet Compare Point registers (EINJ6_COMPARE_POINT*). Note: This register field is sticky." line.long 0x38 "EINJ6_COMPARE_VALUE_H3_REG,Error Injection Control 6 (Compare Value Header DWORD #3). Program this register for the 4th DWORD of TLP header/prefix. It is necessary to carefully consider the endianness when you program this register. Bits [31:0] =.." hexmask.long 0x38 0.--31. 1. "EINJ6_COMPARE_VALUE_H3,Packet Compare Value: 4th DWORD. Specifies the value to compare against Tx the TLP header DWORD#3 bits specified in the Packet Compare Point registers (EINJ6_COMPARE_POINT*). Note: This register field is sticky." line.long 0x3C "EINJ6_CHANGE_POINT_H0_REG,Error Injection Control 6 (Change Point Header DWORD #0). Program this register for the 1st DWORD of TLP header/prefix. It is necessary to carefully consider the endianness when you program this register. Bits [31:0] =.." hexmask.long 0x3C 0.--31. 1. "EINJ6_CHANGE_POINT_H0,Packet Change Point: 1st DWORD. Specifies which Tx TLP header DWORD#0 bits to replace with the corresponding bits in the Packet Change Value registers (EINJ6_CHANGE_VALUE*). Note: This register field is sticky." line.long 0x40 "EINJ6_CHANGE_POINT_H1_REG,Error Injection Control 6 (Change Point Header DWORD #1). Program this register for the 2nd DWORD of TLP header/prefix. It is necessary to carefully consider the endianness when you program this register. Bits [31:0] =.." hexmask.long 0x40 0.--31. 1. "EINJ6_CHANGE_POINT_H1,Packet Change Point: 2nd DWORD. Specifies which Tx TLP header DWORD#1 bits to replace with the corresponding bits in the Packet Change Value registers (EINJ6_CHANGE_VALUE*). Note: This register field is sticky." line.long 0x44 "EINJ6_CHANGE_POINT_H2_REG,Error Injection Control 6 (Change Point Header DWORD #2). Program this register for the 3rd DWORD of TLP header/prefix. It is necessary to carefully consider the endianness when you program this register. Bits [31:0] =.." hexmask.long 0x44 0.--31. 1. "EINJ6_CHANGE_POINT_H2,Packet Change Point: 3rd DWORD. Specifies which Tx TLP header DWORD#2 bits to replace with the corresponding bits in the Packet Change Value registers (EINJ6_CHANGE_VALUE*). Note: This register field is sticky." line.long 0x48 "EINJ6_CHANGE_POINT_H3_REG,Error Injection Control 6 (Change Point Header DWORD #3). Program this register for the 4th DWORD of TLP header/prefix. It is necessary to carefully consider the endianness when you program this register. Bits [31:0] =.." hexmask.long 0x48 0.--31. 1. "EINJ6_CHANGE_POINT_H3,Packet Change Point: 4th DWORD. Specifies which Tx TLP header DWORD#3 bits to replace with the corresponding bits in the Packet Change Value registers (EINJ6_CHANGE_VALUE*). Note: This register field is sticky." line.long 0x4C "EINJ6_CHANGE_VALUE_H0_REG,Error Injection Control 6 (Change Value Header DWORD #0). Program this register for the 1st DWORD of TLP header/prefix. It is necessary to carefully consider the endianness when you program this register. Bits [31:0] =.." hexmask.long 0x4C 0.--31. 1. "EINJ6_CHANGE_VALUE_H0,Packet Change Value: 1st DWORD. Specifies replacement values for the Tx TLP header DWORD#0 bits defined in the Packet Change Point registers (EINJ6_CHANGE_POINT*). Only applies when the EINJ6_INVERTED_CONTROL field in EINJ6_TLP_REG.." line.long 0x50 "EINJ6_CHANGE_VALUE_H1_REG,Error Injection Control 6 (Change Value Header DWORD #1). Program this register for the 2nd DWORD of TLP header/prefix. It is necessary to carefully consider the endianness when you program this register. Bits [31:0] =.." hexmask.long 0x50 0.--31. 1. "EINJ6_CHANGE_VALUE_H1,Packet Change Value: 2nd DWORD. Specifies replacement values for the Tx TLP header DWORD#1 bits defined in the Packet Change Point registers (EINJ6_CHANGE_POINT*). Only applies when the EINJ6_INVERTED_CONTROL field in EINJ6_TLP_REG.." line.long 0x54 "EINJ6_CHANGE_VALUE_H2_REG,Error Injection Control 6 (Change Value Header DWORD #2). Program this register for the 3rd DWORD of TLP header/prefix. It is necessary to carefully consider the endianness when you program this register. Bits [31:0] =.." hexmask.long 0x54 0.--31. 1. "EINJ6_CHANGE_VALUE_H2,Packet Change Value: 3rd DWORD. Specifies replacement values for the Tx TLP header DWORD#2 bits defined in the Packet Change Point registers (EINJ6_CHANGE_POINT*). Only applies when the EINJ6_INVERTED_CONTROL field in EINJ6_TLP_REG.." line.long 0x58 "EINJ6_CHANGE_VALUE_H3_REG,Error Injection Control 6 (Change Value Header DWORD #3). Program this register for the 4th DWORD of TLP header/prefix. It is necessary to carefully consider the endianness when you program this register. Bits [31:0] =.." hexmask.long 0x58 0.--31. 1. "EINJ6_CHANGE_VALUE_H3,Packet Change Value: 4th DWORD. Specifies replacement values for the Tx TLP header DWORD#3 bits defined in the Packet Change Point registers (EINJ6_CHANGE_POINT*). Only applies when the EINJ6_INVERTED_CONTROL field in EINJ6_TLP_REG.." line.long 0x5C "EINJ6_TLP_REG,Error Injection Control 6 (Packet Error). The Packet Compare Point registers (EINJ6_COMPARE_POINT*) specify which Tx TLP header bits to compare with the corresponding bits in the Packet Compare Value registers (EINJ6_COMPARE_VALUE*). When.." hexmask.long.tbyte 0x5C 12.--31. 1. "RSVDP_12,Reserved for future use." newline bitfld.long 0x5C 9.--11. "EINJ6_PACKET_TYPE,Packet type. Selects the TLP packets to inject errors into. - 0: TLP Header - 1: TLP Prefix 1st 4-DWORDs - 2: TLP Prefix 2nd -DWORDs - Else: Reserved Note: This register field is sticky." "TLP Header,TLP Prefix 1st 4-DWORDs,TLP Prefix 2nd -DWORDs,?,?,?,?,?" newline bitfld.long 0x5C 8. "EINJ6_INVERTED_CONTROL,Inverted Error Injection Control. - 0: EINJ6_CHANGE_VALUE_H[0/1/2/3] is used to replace bits specified by EINJ6_CHANGE_POINT_H[0/1/2/3]. - 1: EINJ6_CHANGE_VALUE_H[0/1/2/3] is ignored and inverts bits specified by.." "EINJ6_CHANGE_VALUE_H[0/1/2/3] is used to replace..,EINJ6_CHANGE_VALUE_H[0/1/2/3] is ignored and.." newline hexmask.long.byte 0x5C 0.--7. 1. "EINJ6_COUNT,Error Injection Count. Indicates the number of errors to insert. This counter is decremented while errors are been inserted. - If the counter value is 0x01 and error is inserted ERROR_INJECTION6_ENABLE in EINJ_ENABLE_REG returns '0'. - If.." group.long (0xA0+0x30C)++0x7 line.long 0x0 "SD_CONTROL1_REG,Silicon Debug Control 1. For more details. see the RAS DES section in the Core Operations chapter of the Databook." hexmask.long.byte 0x0 24.--31. 1. "RSVDP_24,Reserved for future use." newline bitfld.long 0x0 22.--23. "LOW_POWER_INTERVAL,Low Power Entry Interval Time. Interval Time that the controller starts monitoring RXELECIDLE signal after L0s/L1/L2 entry. You should set the value according to the latency from receiving EIOS to RXELECIDLE assertion at the PHY. -.." "0,1,2,3" newline bitfld.long 0x0 20.--21. "TX_EIOS_NUM,Number of Tx EIOS. This register sets the number of transmit EIOS for L0s/L1 entry and Disable/Loopback/Hot-reset exit. The controller selects the greater value between this register and the value defined by the PCI-SIG specification. 2.5GT/s.." "0,1,2,3" newline rbitfld.long 0x0 17.--19. "RSVDP_17,Reserved for future use." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 16. "FORCE_DETECT_LANE_EN,Force Detect Lane Enable. When this bit is set the controller ignores receiver detection from PHY during LTSSM Detect state and uses FORCE_DETECT_LANE. Note: This register field is sticky." "0,1" newline hexmask.long.word 0x0 0.--15. 1. "FORCE_DETECT_LANE,Force Detect Lane. When the FORCE_DETECT_LANE_EN field is set the controller ignores receiver detection from PHY during LTSSM Detect state and uses this value instead. - 0: Lane0 - 1: Lane1 - 2: Lane2 - .. - 15: Lane15 Note: This.." line.long 0x4 "SD_CONTROL2_REG,Silicon Debug Control 2. For more details. see the RAS DES section in the Core Operations chapter of the Databook." hexmask.long.word 0x4 17.--31. 1. "RSVDP_17,Reserved for future use." newline bitfld.long 0x4 16. "FRAMING_ERR_RECOVERY_DISABLE,Framing Error Recovery Disable. This bit disables a transition to Recovery state when a Framing Error is occurred. Note: This register field is sticky." "0,1" newline hexmask.long.byte 0x4 11.--15. 1. "RSVDP_11,Reserved for future use." newline bitfld.long 0x4 10. "DIRECT_LPBKSLV_TO_EXIT,Direct Loopback Slave To Exit. When this bit is set and the LTSSM is in Loopback Slave Active State the LTSSM transitions to Loopback Slave Exit state. Note: This register field is sticky." "0,1" newline bitfld.long 0x4 9. "DIRECT_POLCOMP_TO_DETECT,Direct Polling.Compliance to Detect. When this bit is set and the LTSSM is in Polling Compliance State the LTSSM transitions to Detect state. Note: This register field is sticky." "0,1" newline bitfld.long 0x4 8. "DIRECT_RECIDLE_TO_CONFIG,Direct Recovery.Idle to Configuration. When this bit is set and the LTSSM is in Recovery Idle State the LTSSM transitions to Configuration state. Note: This register field is sticky." "0,1" newline hexmask.long.byte 0x4 3.--7. 1. "RSVDP_3,Reserved for future use." newline bitfld.long 0x4 2. "NOACK_FORCE_LINKDOWN,Force LinkDown. When this bit is set and the controller detects REPLY_NUM rolling over 4 times the LTSSM transitions to Detect State. Note: This register field is sticky." "0,1" newline bitfld.long 0x4 1. "RECOVERY_REQUEST,Recovery Request. When this bit is set to '1' in L0 or L0s the LTSSM starts transitioning to Recovery State. This request does not cause a speed change or re-equalization." "0,1" newline bitfld.long 0x4 0. "HOLD_LTSSM,Hold and Release LTSSM. For as long as this register is '1' the controller stays in the current LTSSM. Note: This register field is sticky." "0,1" group.long (0xB0+0x30C)++0xB line.long 0x0 "SD_STATUS_L1LANE_REG,Silicon Debug Status(Layer1 Per-lane). This viewport register returns the data selected by the following field: - LANE_SELECT in SD_STATUS_L1LANE_REG For more details. see the RAS DES section in the Core Operations chapter of the.." hexmask.long.byte 0x0 24.--31. 1. "DESKEW_POINTER,Deskew Pointer. Indicates Deskew pointer of internal Deskew buffer of selected lane number(LANE_SELECT). Note: This register field is sticky." newline rbitfld.long 0x0 21.--23. "RSVDP_21,Reserved for future use." "0,1,2,3,4,5,6,7" newline rbitfld.long 0x0 20. "PIPE_TXELECIDLE,PIPE:TxElecIdle. Indicates PIPE TXELECIDLE signal of selected lane number(LANE_SELECT). Note: This register field is sticky." "0,1" newline rbitfld.long 0x0 19. "PIPE_RXELECIDLE,PIPE:RxElecIdle. Indicates PIPE RXELECIDLE signal of selected lane number(LANE_SELECT). Note: This register field is sticky." "0,1" newline rbitfld.long 0x0 18. "PIPE_RXVALID,PIPE:RxValid. Indicates PIPE RXVALID signal of selected lane number(LANE_SELECT). Note: This register field is sticky." "0,1" newline rbitfld.long 0x0 17. "PIPE_DETECT_LANE,PIPE:Detect Lane. Indicates whether PHY indicates receiver detection or not on selected lane number(LANE_SELECT). Note: This register field is sticky." "0,1" newline rbitfld.long 0x0 16. "PIPE_RXPOLARITY,PIPE:RxPolarity. Indicates PIPE RXPOLARITY signal of selected lane number(LANE_SELECT). Note: This register field is sticky." "0,1" newline hexmask.long.word 0x0 4.--15. 1. "RSVDP_4,Reserved for future use." newline hexmask.long.byte 0x0 0.--3. 1. "LANE_SELECT,Lane Select. Lane Select register for Silicon Debug Status Register of Layer1-PerLane. - 0x0: Lane0 - 0x1: Lane1 - 0x2: Lane2 - .. - 0xF: Lane15 Note: This register field is sticky." line.long 0x4 "SD_STATUS_L1LTSSM_REG,Silicon Debug Status(Layer1 LTSSM). For more details. see the RAS DES section in the Core Operations chapter of the Databook." hexmask.long.word 0x4 16.--31. 1. "LTSSM_VARIABLE,LTSSM Variable. Indicates internal LTSSM variables defined in the PCI Express Base Specification. C-PCIe Mode: - 0: directed_speed_change - 1: changed_speed_recovery - 2: successful_speed_negotiation - 3: upconfigure_capable; Set to '1' if.." newline rbitfld.long 0x4 15. "LANE_REVERSAL,Lane Reversal Operation. Receiver detected lane reversal. This field is only valid in the L0 LTSSM state. Note: This register field is sticky." "0,1" newline hexmask.long.byte 0x4 11.--14. 1. "RSVDP_11,Reserved for future use." newline rbitfld.long 0x4 8.--10. "PIPE_POWER_DOWN,PIPE:PowerDown. Indicates PIPE PowerDown signal. Note: This register field is sticky." "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 7. "FRAMING_ERR,Framing Error. Indicates Framing Error detection status." "0,1" newline hexmask.long.byte 0x4 0.--6. 1. "FRAMING_ERR_PTR,First Framing Error Pointer. Identifies the first Framing Error using the following encoding. The field contents are only valid value when FRAMING_ERR =1. Received Unexpected Framing Token - 01h: When non- STP/SDP/IDL Token was received.." line.long 0x8 "SD_STATUS_PM_REG,Silicon Debug Status(PM). For more details. see the RAS DES section in the Core Operations chapter of the Databook." hexmask.long.byte 0x8 24.--31. 1. "RSVDP_24,Reserved for future use." newline hexmask.long.byte 0x8 16.--23. 1. "LATCHED_NFTS,Latched N_FTS. Indicates the value of N_FTS in the received TS Ordered Sets from the Link Partner Note: This register field is sticky." newline rbitfld.long 0x8 13.--15. "L1SUB_STATE,L1Sub State. Indicates internal state machine of L1Sub state. - 0h: S_L1_U : idle state - 1h: S_L1_0 : wait for aux_clk_active - 2h: S_L1_0_WAIT4_ACK : wait for pclkack - 3h: S_L1_0_WAIT4_CLKREQ : wait for clkreq - 4h: S_L1_N_ENTRY : check.." "wait for aux_clk_active,?,?,?,?,?,?,?" newline bitfld.long 0x8 12. "PME_RESEND_FLAG,PME Re-send flag. When the DUT sends a PM_PME message TLP the DUT sets PME_Status bit. If host software does not clear PME_Status bit for 100ms(+50%/-5%) the DUT resends the PM_PME Message. This bit indicates that a PM_PME was resent." "0,1" newline hexmask.long.byte 0x8 8.--11. 1. "INTERNAL_PM_SSTATE,Internal PM State(Slave). Indicates internal state machine of Power Management Slave controller. - 0h: S_IDLE - 1h: S_RESPOND_NAK - 2h: S_BLOCK_TLP - 3h: S_WAIT_LAST_TLP_ACK - 4h: S_WAIT_EIDLE - 5h: S_LINK_ENTR_L1 - 6h: S_L1 - 7h:.." newline rbitfld.long 0x8 5.--7. "RSVDP_5,Reserved for future use." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x8 0.--4. 1. "INTERNAL_PM_MSTATE,Internal PM State(Master). Indicates internal state machine of Power Management Master controller. - 00h: IDLE - 01h: L0 - 02h: L0S - 03h: ENTER_L0S - 04h: L0S_EXIT - 05h: WAIT_PMCSR_CPL_SENT - 08h: L1 - 09h: L1_BLOCK_TLP - 0Ah:.." rgroup.long (0xBC+0x30C)++0x3 line.long 0x0 "SD_STATUS_L2_REG,Silicon Debug Status(Layer2). For more details. see the RAS DES section in the Core Operations chapter of the Databook." hexmask.long.byte 0x0 28.--31. 1. "RSVDP_28,Reserved for future use." newline bitfld.long 0x0 27. "FC_INIT2,FC_INIT2. Indicates the controller is in FC_INIT2(VC0) state. Note: This register field is sticky." "0,1" newline bitfld.long 0x0 26. "FC_INIT1,FC_INIT1. Indicates the controller is in FC_INIT1(VC0) state. Note: This register field is sticky." "0,1" newline bitfld.long 0x0 24.--25. "DLCMSM,DLCMSM. Indicates the current DLCMSM. - 00b: DL_INACTIVE - 01b: DL_FC_INIT - 11b: DL_ACTIVE Note: This register field is sticky." "0,1,2,3" newline hexmask.long.word 0x0 12.--23. 1. "RX_ACK_SEQ_NO,Tx Ack Sequence Number. Indicates ACKD_SEQ which is updated by receiving ACK/NAK DLLP. Note: This register field is sticky." newline hexmask.long.word 0x0 0.--11. 1. "TX_TLP_SEQ_NO,Tx Tlp Sequence Number. Indicates next transmit sequence number for transmit TLP. Note: This register field is sticky." group.long (0xC0+0x30C)++0x7 line.long 0x0 "SD_STATUS_L3FC_REG,Silicon Debug Status(Layer3 FC). The CREDIT_DATA[0/1] fields in this viewport register return the data for the VC and TLP Type selected by the following fields: - CREDIT_SEL_VC - CREDIT_SEL_CREDIT_TYPE - CREDIT_SEL_TLP_TYPE -.." hexmask.long.word 0x0 20.--31. 1. "CREDIT_DATA1,Credit Data1. Current FC credit data selected by the CREDIT_SEL_VC CREDIT_SEL_CREDIT_TYPE CREDIT_SEL_TLP_TYPE and CREDIT_SEL_HD viewport-select fields. - Rx: Credit Allocated Value - Tx: Credit Limit Value. This value is valid when.." newline hexmask.long.word 0x0 8.--19. 1. "CREDIT_DATA0,Credit Data0. Current FC credit data selected by the CREDIT_SEL_VC CREDIT_SEL_CREDIT_TYPE CREDIT_SEL_TLP_TYPE and CREDIT_SEL_HD viewport-select fields. - Rx: Credit Received Value - Tx: Credit Consumed Value Note: This register field is.." newline rbitfld.long 0x0 7. "RSVDP_7,Reserved for future use." "0,1" newline bitfld.long 0x0 6. "CREDIT_SEL_HD,Credit Select(HeaderData). This field in conjunction with the CREDIT_SEL_VC CREDIT_SEL_CREDIT_TYPE and CREDIT_SEL_TLP_TYPE viewport-select fields determines that data that is returned by the CREDIT_DATA0 and CREDIT_DATA1 data fields. -.." "Header Credit,Data Credit" newline bitfld.long 0x0 4.--5. "CREDIT_SEL_TLP_TYPE,Credit Select(TLP Type). This field in conjunction with the CREDIT_SEL_VC CREDIT_SEL_CREDIT_TYPE and CREDIT_SEL_HD viewport-select fields determines that data that is returned by the CREDIT_DATA0 and CREDIT_DATA1 data fields. - 0x0:.." "Posted,Non-Posted,Completion,?" newline bitfld.long 0x0 3. "CREDIT_SEL_CREDIT_TYPE,Credit Select(Credit Type). This field in conjunction with the CREDIT_SEL_VC CREDIT_SEL_TLP_TYPE and CREDIT_SEL_HD viewport-select fields determines that data that is returned by the CREDIT_DATA0 and CREDIT_DATA1 data fields. -.." "Rx,Tx" newline bitfld.long 0x0 0.--2. "CREDIT_SEL_VC,Credit Select(VC). This field in conjunction with the CREDIT_SEL_CREDIT_TYPE CREDIT_SEL_TLP_TYPE and CREDIT_SEL_HD viewport-select fields determines that data that is returned by the CREDIT_DATA0 and CREDIT_DATA1 data fields. - 0x0: VC0 -.." "VC0,VC1,VC2,?,?,?,?,VC7" line.long 0x4 "SD_STATUS_L3_REG,Silicon Debug Status(Layer3). For more details. see the RAS DES section in the Core Operations chapter of the Databook." hexmask.long.tbyte 0x4 8.--31. 1. "RSVDP_8,Reserved for future use." newline bitfld.long 0x4 7. "MFTLP_STATUS,Malformed TLP Status. Indicates malformed TLP has occurred." "0,1" newline hexmask.long.byte 0x4 0.--6. 1. "MFTLP_POINTER,First Malformed TLP Error Pointer. Indicates the element of the received first malformed TLP. This pointer is validated by MFTLP_STATUS. - 01h: AtomicOp address alignment - 02h: AtomicOp operand - 03h: AtomicOp byte enable - 04h: TLP length.." group.long (0xD0+0x30C)++0xB line.long 0x0 "SD_EQ_CONTROL1_REG,Silicon Debug EQ Control 1. This is a viewport control register. Setting the EQ_RATE_SEL and EQ_LANE_SEL fields in this register determine the per-lane Silicon Debug EQ Status data returned by the SD_EQ_STATUS[1/2/3] viewport.." hexmask.long.byte 0x0 24.--31. 1. "FOM_TARGET,FOM Target. Indicates figure of merit target criteria value of EQ Master(DSP in EQ Phase3/USP in EQ Phase2). This field is only valid when GEN3_EQ_FB_MODE is 0001b(Figure Of Merit). Note: This register field is sticky." newline bitfld.long 0x0 23. "FOM_TARGET_ENABLE,FOM Target Enable. Enables the FOM_TARGET fields. Note: This register field is sticky." "0,1" newline hexmask.long.byte 0x0 18.--22. 1. "RSVDP_18,Reserved for future use." newline bitfld.long 0x0 16.--17. "EVAL_INTERVAL_TIME,Eval Interval Time. Indicates interval time of RxEqEval assertion. - 00: 500ns - 01: 1us - 10: 2us - 11: 4us This field is used for EQ Master(DSP in EQ Phase3/USP in EQ Phase2). Note: This register field is sticky." "0,1,2,3" newline hexmask.long.byte 0x0 10.--15. 1. "RSVDP_10,Reserved for future use." newline bitfld.long 0x0 8.--9. "EXT_EQ_TIMEOUT,Extends EQ Phase2/3 Timeout. This field is used when the Ltssm is in Recovery.EQ2/3. When this field is set the value of EQ2/3 timeout is extended. EQ Master(DSP in EQ Phase3/USP in EQ Phase2). - 00: 24ms (default) - 01: 48ms (x2) - 10:.." "0,1,2,3" newline rbitfld.long 0x0 6.--7. "RSVDP_6,Reserved for future use." "0,1,2,3" newline bitfld.long 0x0 4.--5. "EQ_RATE_SEL,EQ Status Rate Select. Setting this field in conjunction with the EQ_LANE_SEL field determines the per-lane Silicon Debug EQ Status data returned by the SD_EQ_CONTROL[2/3] and SD_EQ_STATUS[1/2/3] viewport registers. - 0x0: 8.0GT/s Speed.." "0,1,2,3" newline hexmask.long.byte 0x0 0.--3. 1. "EQ_LANE_SEL,EQ Status Lane Select. Setting this field in conjunction with the EQ_RATE_SEL field determines the per-lane Silicon Debug EQ Status data returned by the SD_EQ_CONTROL[2/3] and SD_EQ_STATUS[1/2/3] viewport registers. - 0x0: Lane0 - 0x1: Lane1.." line.long 0x4 "SD_EQ_CONTROL2_REG,Silicon Debug EQ Control 2. This viewport register returns the value for the rate and lane selected by the EQ_RATE_SEL and EQ_LANE_SEL fields in the SD_EQ_CONTROL1_REG register. For more details. see the RAS DES section in the Core.." rbitfld.long 0x4 31. "RSVDP_31,Reserved for future use." "0,1" newline bitfld.long 0x4 30. "FORCE_LOCAL_TX_PRESET_ENABLE,Force Local Transmitter Preset Enable. Enables the FORCE_LOCAL_TX_PRESET field. If select rate in the EQ_RATE_SEL field is 32.0GT/s Speed this feature is not available. Note: This register field is sticky." "0,1" newline bitfld.long 0x4 29. "FORCE_LOCAL_RX_HINT_ENABLE,Force Local Receiver Preset Hint Enable. Enables the FORCE_LOCAL_RX_HINT field. If select rate in the EQ_RATE_SEL field is other than 8.0GT/s Speed this feature is not available. Note: This register field is sticky." "0,1" newline bitfld.long 0x4 28. "FORCE_LOCAL_TX_COEF_ENABLE,Force Local Transmitter Coefficient Enable. Enables the following fields: - FORCE_LOCAL_TX_PRE_CURSOR - FORCE_LOCAL_TX_CURSOR - FORCE_LOCAL_TX_POST_CURSOR Note: This register field is sticky." "0,1" newline hexmask.long.byte 0x4 24.--27. 1. "FORCE_LOCAL_TX_PRESET,Force Local Transmitter Preset. Indicates initial preset value of USP in EQ Slave(EQ Phase2) instead of receiving EQ TS2. If select rate in the EQ_RATE_SEL field is 32.0GT/s Speed this feature is not available. Note: This register.." newline rbitfld.long 0x4 21.--23. "RSVDP_21,Reserved for future use." "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 18.--20. "FORCE_LOCAL_RX_HINT,Force Local Receiver Preset Hint. Indicates the RxPresetHint value of EQ Slave(DSP in EQ Phase2/USP in EQ Phase3) instead of received or set value. If select rate in the EQ_RATE_SEL field is other than 8.0GT/s Speed this feature is.." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x4 12.--17. 1. "FORCE_LOCAL_TX_POST_CURSOR,Force Local Transmitter Post-Cursor. Indicates the coefficient value of EQ Slave(DSP in EQ Phase2/USP in EQ Phase3) instead of the value instructed from link partner. Note: This register field is sticky." newline hexmask.long.byte 0x4 6.--11. 1. "FORCE_LOCAL_TX_CURSOR,Force Local Transmitter Cursor. Indicates the coefficient value of EQ Slave(DSP in EQ Phase2/USP in EQ Phase3) instead of the value instructed from link partner. Note: This register field is sticky." newline hexmask.long.byte 0x4 0.--5. 1. "FORCE_LOCAL_TX_PRE_CURSOR,Force Local Transmitter Pre-cursor. Indicates the coefficient value of EQ Slave(DSP in EQ Phase2/USP in EQ Phase3) instead of the value instructed from link partner. Note: This register field is sticky." line.long 0x8 "SD_EQ_CONTROL3_REG,Silicon Debug EQ Control 3. This viewport register returns the value for the rate and lane selected by the EQ_RATE_SEL and EQ_LANE_SEL fields in the SD_EQ_CONTROL1_REG register. For more details. see the RAS DES section in the Core.." rbitfld.long 0x8 29.--31. "RSVDP_29,Reserved for future use." "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 28. "FORCE_REMOTE_TX_COEF_ENABLE,Force Remote Transmitter Coefficient Enable. Enables the following fields: - FORCE_REMOTE_TX_PRE_CURSOR - FORCE_REMOTE_TX_CURSOR - FORCE_REMOTE_TX_POST_CURSOR This function can only be used when GEN3_EQ_FB_MODE =.." "0,1" newline hexmask.long.word 0x8 18.--27. 1. "RSVDP_18,Reserved for future use." newline hexmask.long.byte 0x8 12.--17. 1. "FORCE_REMOTE_TX_POST_CURSOR,Force Remote Transmitter Post-Cursor. Indicates the coefficient value of EQ Master(DSP in EQ Phase3/USP in EQ Phase2) instead of the value instructed from local phy in dirchange mode. Note: This register field is sticky." newline hexmask.long.byte 0x8 6.--11. 1. "FORCE_REMOTE_TX_CURSOR,Force Remote Transmitter Cursor. Indicates the coefficient value of EQ Master(DSP in EQ Phase3/USP in EQ Phase2) instead of the value instructed from local phy in dirchange mode. Note: This register field is sticky." newline hexmask.long.byte 0x8 0.--5. 1. "FORCE_REMOTE_TX_PRE_CURSOR,Force Remote Transmitter Pre-Cursor. Indicates the coefficient value of EQ Master(DSP in EQ Phase3/USP in EQ Phase2) instead of the value instructed from local phy in dirchange mode. Note: This register field is sticky." rgroup.long (0xE0+0x30C)++0xB line.long 0x0 "SD_EQ_STATUS1_REG,Silicon Debug EQ Status 1. This viewport register returns the first of three words of Silicon Debug EQ Status data for the rate and lane selected by the EQ_RATE_SEL and EQ_LANE_SEL fields in the SD_EQ_CONTROL1_REG register. The.." hexmask.long.tbyte 0x0 8.--31. 1. "RSVDP_8,Reserved for future use." newline bitfld.long 0x0 7. "EQ_REJECT_EVENT,EQ Reject Event. Indicates that the controller receives two consecutive TS1 OS w/Reject=1b during EQ Master phase(DSP in EQ Phase3/USP in EQ Phase2). This bit is automatically cleared when the controller starts EQ Master phase again." "0,1" newline bitfld.long 0x0 6. "EQ_RULEC_VIOLATION,EQ Rule C Violation. Indicates that coefficients rule C violation is detected in the values provided by PHY using direction change method during EQ Master phase(DSP in EQ Phase3/USP in EQ Phase2). The coefficients rule C correspond to.." "0,1" newline bitfld.long 0x0 5. "EQ_RULEB_VIOLATION,EQ Rule B Violation. Indicates that coefficients rule B violation is detected in the values provided by PHY using direction change method during EQ Master phase(DSP in EQ Phase3/USP in EQ Phase2). The coefficients rules B correspond to.." "0,1" newline bitfld.long 0x0 4. "EQ_RULEA_VIOLATION,EQ Rule A Violation. Indicates that coefficients rule A violation is detected in the values provided by PHY using direction change method during EQ Master phase(DSP in EQ Phase3/USP in EQ Phase2). The coefficients rules A correspond to.." "0,1" newline bitfld.long 0x0 3. "RSVDP_3,Reserved for future use." "0,1" newline bitfld.long 0x0 1.--2. "EQ_CONVERGENCE_INFO,EQ Convergence Info. Indicates equalization convergence information. - 0x0: Equalization is not attempted - 0x1: Equalization finished successfully - 0x2: Equalization finished unsuccessfully - 0x3: Reserved This bit is automatically.." "Equalization is not attempted,Equalization finished successfully,Equalization finished unsuccessfully,Reserved" newline bitfld.long 0x0 0. "EQ_SEQUENCE,EQ Sequence. Indicates that the controller is starting the equalization sequence. Note: This register field is sticky." "0,1" line.long 0x4 "SD_EQ_STATUS2_REG,Silicon Debug EQ Status 2. This viewport register returns the second of three words of Silicon Debug EQ Status data for the rate and lane selected by the EQ_RATE_SEL and EQ_LANE_SEL fields in the SD_EQ_CONTROL1_REG register. Each field.." hexmask.long.byte 0x4 24.--31. 1. "EQ_LOCAL_FOM_VALUE,EQ Local Figure of Merit. Indicates Local maximum Figure of Merit value. Note: This register field is sticky." newline bitfld.long 0x4 21.--23. "RSVDP_21,Reserved for future use." "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 18.--20. "EQ_LOCAL_RX_HINT,EQ Local Receiver Preset Hint. Indicates Local Receiver Preset Hint value. If select rate in the EQ_RATE_SEL field is other than 8.0GT/s Speed this feature is not available. Note: This register field is sticky." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x4 12.--17. 1. "EQ_LOCAL_POST_CURSOR,EQ Local Post-Cursor. Indicates Local post cursor coefficient value. Note: This register field is sticky." newline hexmask.long.byte 0x4 6.--11. 1. "EQ_LOCAL_CURSOR,EQ Local Cursor. Indicates Local cursor coefficient value. Note: This register field is sticky." newline hexmask.long.byte 0x4 0.--5. 1. "EQ_LOCAL_PRE_CURSOR,EQ Local Pre-Cursor. Indicates Local pre cursor coefficient value. Note: This register field is sticky." line.long 0x8 "SD_EQ_STATUS3_REG,Silicon Debug EQ Status 3. This viewport register returns the third of three words of Silicon Debug EQ Status data for the rate and lane selected by the EQ_RATE_SEL and EQ_LANE_SEL fields in the SD_EQ_CONTROL1_REG register. Each field.." bitfld.long 0x8 30.--31. "RSVDP_30,Reserved for future use." "0,1,2,3" newline hexmask.long.byte 0x8 24.--29. 1. "EQ_REMOTE_FS,EQ Remote FS. Indicates Remote FS value. Note: This register field is sticky." newline hexmask.long.byte 0x8 18.--23. 1. "EQ_REMOTE_LF,EQ Remote LF. Indicates Remote LF value. Note: This register field is sticky." newline hexmask.long.byte 0x8 12.--17. 1. "EQ_REMOTE_POST_CURSOR,EQ Remote Post-Cursor. Indicates Remote post cursor coefficient value. Note: This register field is sticky." newline hexmask.long.byte 0x8 6.--11. 1. "EQ_REMOTE_CURSOR,EQ Remote Cursor. Indicates Remote cursor coefficient value. Note: This register field is sticky." newline hexmask.long.byte 0x8 0.--5. 1. "EQ_REMOTE_PRE_CURSOR,EQ Remote Pre-Cursor. Indicates Remote pre cursor coefficient value. Note: This register field is sticky." tree.end tree "PF0_SN_CAP (Device Serial Number Capability Structure)" group.long (0x0+0x170)++0xB line.long 0x0 "SN_BASE,Device Serial Number Extended Capability Header. For a description of this standard PCIe register. see the PCI Express Base Specification." hexmask.long.word 0x0 20.--31. 1. "SN_NEXT_OFFSET,Next Capability Offset. For a description of this standard PCIe register field see the PCI Express Base Specification. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then.." hexmask.long.byte 0x0 16.--19. 1. "SN_CAP_VERSION,Capability Version. For a description of this standard PCIe register field see the PCI Express Base Specification. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky).." hexmask.long.word 0x0 0.--15. 1. "SN_PCIE_EXTENDED_CAP_ID,Serial Number Extended Capability ID. For a description of this standard PCIe register field see the PCI Express Base Specification. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if.." line.long 0x4 "SER_NUM_REG_DW_1,Serial Number 1 Register. For a description of this standard PCIe register. see the PCI Express Base Specification." hexmask.long 0x4 0.--31. 1. "SN_SER_NUM_REG_1_DW,IEEE 64 bit Device Serial Number (DW 1). For a description of this standard PCIe register field see the PCI Express Base Specification. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if.." line.long 0x8 "SER_NUM_REG_DW_2,Serial Number 2 Register. For a description of this standard PCIe register. see the PCI Express Base Specification." hexmask.long 0x8 0.--31. 1. "SN_SER_NUM_REG_2_DW,IEEE 64 bit Device Serial Number (DW 2). For a description of this standard PCIe register field see the PCI Express Base Specification. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if.." tree.end tree "PF0_VSECRAS_CAP (PF RAS Datapath Protection Capability Structure (VSEC))" group.long (0x0+0x480)++0x3 line.long 0x0 "RASDP_EXT_CAP_HDR_OFF,PCIe Extended capability ID. Capability version and Next capability offset. For a description of this standard PCIe register. see the PCI Express Specification." hexmask.long.word 0x0 20.--31. 1. "NEXT_OFFSET,Next Capability Offset. For a description of this standard PCIe register see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else.." newline hexmask.long.byte 0x0 16.--19. 1. "CAP,Capability Version. For a description of this standard PCIe register see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note:.." newline hexmask.long.word 0x0 0.--15. 1. "ID,PCI Express Extended Capability ID. For a description of this standard PCIe register see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else.." rgroup.long (0x4+0x480)++0x3 line.long 0x0 "RASDP_VENDOR_SPECIFIC_HDR_OFF,Vendor Specific Header. For a description of this standard PCIe register. see the PCI Express Specification." hexmask.long.word 0x0 20.--31. 1. "VSEC_LENGTH,VSEC Length. For a description of this standard PCIe register see the PCI Express Specification. Note: This register field is sticky." newline hexmask.long.byte 0x0 16.--19. 1. "VSEC_REV,VSEC Rev. For a description of this standard PCIe register see the PCI Express Specification. Note: This register field is sticky." newline hexmask.long.word 0x0 0.--15. 1. "VSEC_ID,VSEC ID. For a description of this standard PCIe register see the PCI Express Specification. Note: This register field is sticky." group.long (0x8+0x480)++0x7 line.long 0x0 "RASDP_ERROR_PROT_CTRL_OFF,ECC error correction control. Allows you to disable ECC error correction for RAMs and datapath. When the AXI Bridge Module is implemented and the master / slave clocks are asynchronous to the PCIe native controller clock.." hexmask.long.byte 0x0 24.--31. 1. "RSVDP_24,Reserved for future use." newline bitfld.long 0x0 23. "ERROR_PROT_DISABLE_CXS_RX,Error correction disable for CXS Tx path (PCIe Rx path). Note: This register field is sticky." "0,1" newline bitfld.long 0x0 22. "ERROR_PROT_DISABLE_ADM_RX,Error correction disable for ADM Rx path. Note: This register field is sticky." "0,1" newline bitfld.long 0x0 21. "ERROR_PROT_DISABLE_LAYER3_RX,Error correction disable for layer 3 Rx path. Note: This register field is sticky." "0,1" newline bitfld.long 0x0 20. "ERROR_PROT_DISABLE_LAYER2_RX,Error correction disable for layer 2 Rx path. Note: This register field is sticky." "0,1" newline bitfld.long 0x0 19. "ERROR_PROT_DISABLE_DMA_READ,Error correction disable for DMA read engine. Note: This register field is sticky." "0,1" newline bitfld.long 0x0 18. "ERROR_PROT_DISABLE_AXI_BRIDGE_INBOUND_REQUEST,Error correction disable for AXI bridge inbound request path. Note: This register field is sticky." "0,1" newline bitfld.long 0x0 17. "ERROR_PROT_DISABLE_AXI_BRIDGE_INBOUND_COMPLETION,Error correction disable for AXI bridge inbound completion composer. Does not disable the error detection reporting for 1-bit and 2-bit ECC errors. Note: This register field is sticky." "?,bit and 2-bit ECC errors" newline bitfld.long 0x0 16. "ERROR_PROT_DISABLE_RX,Global error correction disable for all Rx layers. Note: This register field is sticky." "0,1" newline hexmask.long.byte 0x0 9.--15. 1. "RSVDP_9,Reserved for future use." newline bitfld.long 0x0 8. "ERROR_PROT_DISABLE_DTIM_TX,Error correction disable for DTIM Tx path. Note: This register field is sticky." "0,1" newline bitfld.long 0x0 7. "ERROR_PROT_DISABLE_CXS_TX,Error correction disable for CXS Rx path (PCIe Tx path). Note: This register field is sticky." "0,1" newline bitfld.long 0x0 6. "ERROR_PROT_DISABLE_ADM_TX,Error correction disable for Adm Tx path. Note: This register field is sticky." "0,1" newline bitfld.long 0x0 5. "ERROR_PROT_DISABLE_LAYER3_TX,Error correction disable for layer 3 Tx path. Note: This register field is sticky." "0,1" newline bitfld.long 0x0 4. "ERROR_PROT_DISABLE_LAYER2_TX,Error correction disable for layer 2 Tx path. Note: This register field is sticky." "0,1" newline bitfld.long 0x0 3. "ERROR_PROT_DISABLE_DMA_WRITE,Error correction disable for DMA write engine. Note: This register field is sticky." "0,1" newline bitfld.long 0x0 2. "ERROR_PROT_DISABLE_AXI_BRIDGE_OUTBOUND,Error correction disable for AXI bridge outbound request path. Note: This register field is sticky." "0,1" newline bitfld.long 0x0 1. "ERROR_PROT_DISABLE_AXI_BRIDGE_MASTER,Error correction disable for AXI bridge master completion buffer. Note: This register field is sticky." "0,1" newline bitfld.long 0x0 0. "ERROR_PROT_DISABLE_TX,Global error correction disable for all Tx layers. Does not disable the error detection reporting for 1-bit and 2-bit ECC errors. Note: This register field is sticky." "?,bit and 2-bit ECC errors" line.long 0x4 "RASDP_CORR_COUNTER_CTRL_OFF,Corrected error (1-bit ECC) counter selection and control. This is a viewport control register. Setting the CORR_COUNTER_SELECTION_REGION and CORR_COUNTER_SELECTION fields in this register determine the counter data returned.." hexmask.long.byte 0x4 24.--31. 1. "CORR_COUNTER_SELECTION,Counter selection. This field selects the counter ID (within the region defined by CORR_COUNTER_SELECTION_REGION) whose contents can be read from the RASDP_CORR_COUNT_REPORT_OFF register. You can cycle this field value from 0 to.." newline hexmask.long.byte 0x4 20.--23. 1. "CORR_COUNTER_SELECTION_REGION,Select correctable counter region: - 0x0: Region select for Adm Rx path - 0x1: Region select for layer 3 Rx path - 0x2: Region select for layer 2 Rx path - 0x3: Region select for DMA inbound path - 0x4: Region select for AXI.." newline hexmask.long.word 0x4 5.--19. 1. "RSVDP_5,Reserved for future use." newline bitfld.long 0x4 4. "CORR_EN_COUNTERS,Enable correctable errors counters. - 1: counters increment when the controller detects a correctable error - 0: counters are frozen The counters are enabled by default." "counters are frozen,counters increment when the controller detects a.." newline rbitfld.long 0x4 1.--3. "RSVDP_1,Reserved for future use." "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 0. "CORR_CLEAR_COUNTERS,Clear all correctable error counters." "0,1" rgroup.long (0x10+0x480)++0x3 line.long 0x0 "RASDP_CORR_COUNT_REPORT_OFF,Corrected error (1-bit ECC) counter data. This viewport register returns the counter data selected by the CORR_COUNTER_SELECTION_REGION and CORR_COUNTER_SELECTION fields in the RASDP_CORR_COUNTER_CTRL_OFF register." hexmask.long.byte 0x0 24.--31. 1. "CORR_COUNTER_SELECTED,Counter selection. Returns the value set in the CORR_COUNTER_SELECTION field of the RASDP_CORR_COUNTER_CTRL_OFF register." newline hexmask.long.byte 0x0 20.--23. 1. "CORR_COUNTER_SELECTED_REGION,Selected correctable counter region: - 0x0: Region select for Adm Rx path - 0x1: Region select for layer 3 Rx path - 0x2: Region select for layer 2 Rx path - 0x3: Region select for DMA inbound path - 0x4: Region select for.." newline hexmask.long.word 0x0 8.--19. 1. "RSVDP_8,Reserved for future use." newline hexmask.long.byte 0x0 0.--7. 1. "CORR_COUNTER,Current corrected error count for the selected counter." group.long (0x14+0x480)++0x3 line.long 0x0 "RASDP_UNCORR_COUNTER_CTRL_OFF,Uncorrected error (2-bit ECC and parity) counter selection and control. This is a viewport control register. Setting the UNCORR_COUNTER_SELECTION_REGION and UNCORR_COUNTER_SELECTION fields in this register determine the.." hexmask.long.byte 0x0 24.--31. 1. "UNCORR_COUNTER_SELECTION,Counter selection. This field selects the counter ID (within the region defined by UNCORR_COUNTER_SELECTION_REGION) whose contents can be read from the RASDP_UNCORR_COUNT_REPORT_OFF register. You can cycle this field value from 0.." newline hexmask.long.byte 0x0 20.--23. 1. "UNCORR_COUNTER_SELECTION_REGION,Select uncorrectable counter region: - 0x0: Region select for Adm Rx path - 0x1: Region select for layer 3 Rx path - 0x2: Region select for layer 2 Rx path - 0x3: Region select for DMA inbound path - 0x4: Region select for.." newline hexmask.long.word 0x0 5.--19. 1. "RSVDP_5,Reserved for future use." newline bitfld.long 0x0 4. "UNCORR_EN_COUNTERS,Enable uncorrectable errors counters. - 1: enables the counters to increment on detected correctable errors - 0: counters are frozen The counters are enabled by default." "counters are frozen,enables the counters to increment on detected.." newline rbitfld.long 0x0 1.--3. "RSVDP_1,Reserved for future use." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 0. "UNCORR_CLEAR_COUNTERS,Clear uncorrectable errors counters. When asserted causes all counters tracking the uncorrectable errors to be cleared." "0,1" rgroup.long (0x18+0x480)++0x3 line.long 0x0 "RASDP_UNCORR_COUNT_REPORT_OFF,Uncorrected error (2-bit ECC and parity) counter data. This viewport register returns the counter data selected by the UNCORR_COUNTER_SELECTION_REGION and UNCORR_COUNTER_SELECTION fields in the RASDP_UNCORR_COUNTER_CTRL_OFF.." hexmask.long.byte 0x0 24.--31. 1. "UNCORR_COUNTER_SELECTED,Counter selection. Returns the value set in the UNCORR_COUNTER_SELECTION field of the RASDP_UNCORR_COUNTER_CTRL_OFF register." newline hexmask.long.byte 0x0 20.--23. 1. "UNCORR_COUNTER_SELECTED_REGION,Selected uncorrectable counter region: - 0x0: Region select for Adm Rx path - 0x1: Region select for layer 3 Rx path - 0x2: Region select for layer 2 Rx path - 0x3: Region select for DMA inbound path - 0x4: Region select.." newline hexmask.long.word 0x0 8.--19. 1. "RSVDP_8,Reserved for future use." newline hexmask.long.byte 0x0 0.--7. 1. "UNCORR_COUNTER,Current uncorrected error count for the selected counter" group.long (0x1C+0x480)++0x3 line.long 0x0 "RASDP_ERROR_INJ_CTRL_OFF,Error injection control for the following features: - 1-bit or 2-bit injection - Continuous or fixed-number (n) injection modes - Global enable/disable - Selectable location where injection occurs" hexmask.long.byte 0x0 24.--31. 1. "RSVDP_24,Reserved for future use." newline hexmask.long.byte 0x0 16.--23. 1. "ERROR_INJ_LOC,Error injection location. Selects where error injection takes place. You can cycle this field value from 0 to 255 to access all locations according to the detailed report of check points at.." newline hexmask.long.byte 0x0 8.--15. 1. "ERROR_INJ_COUNT,Error injection count. - 0: errors are inserted in every TLP until you clear ERROR_INJ_EN. - 1: one errors injected - 2: two errors injected - n: amount of errors injected" newline rbitfld.long 0x0 6.--7. "RSVDP_6,Reserved for future use." "0,1,2,3" newline bitfld.long 0x0 4.--5. "ERROR_INJ_TYPE,Error injection type: - 0: none - 1: 1-bit - 2: 2-bit" "none,bit,bit,?" newline rbitfld.long 0x0 1.--3. "RSVDP_1,Reserved for future use." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 0. "ERROR_INJ_EN,Error injection global enable. When set enables the error insertion logic." "0,1" rgroup.long (0x20+0x480)++0x7 line.long 0x0 "RASDP_CORR_ERROR_LOCATION_OFF,Corrected errors locations. For more details. see the RAS Data Protection (DP) section in the Core Operations chapter of the Databook." hexmask.long.byte 0x0 24.--31. 1. "LOC_LAST_CORR_ERROR,Location/ID of the last corrected error within the region defined by REG_LAST_CORR_ERROR. You can cycle this field value from 0 to 255 to access all counters according to the detailed report of check points at.." newline hexmask.long.byte 0x0 20.--23. 1. "REG_LAST_CORR_ERROR,Region of the last corrected error: - 0x0: Region select for Adm Rx path - 0x1: Region select for layer 3 Rx path - 0x2: Region select for layer 2 Rx path - 0x3: Region select for DMA inbound path - 0x4: Region select for AXI bridge.." newline hexmask.long.byte 0x0 16.--19. 1. "RSVDP_16,Reserved for future use." newline hexmask.long.byte 0x0 8.--15. 1. "LOC_FIRST_CORR_ERROR,Location/ID of the first corrected error within the region defined by REG_FIRST_CORR_ERROR. You can cycle this field value from 0 to 255 to access all counters according to the detailed report of check points at.." newline hexmask.long.byte 0x0 4.--7. 1. "REG_FIRST_CORR_ERROR,Region of the first corrected error: - 0x0: Region select for Adm Rx path - 0x1: Region select for layer 3 Rx path - 0x2: Region select for layer 2 Rx path - 0x3: Region select for DMA inbound path - 0x4: Region select for AXI bridge.." newline hexmask.long.byte 0x0 0.--3. 1. "RSVDP_0,Reserved for future use." line.long 0x4 "RASDP_UNCORR_ERROR_LOCATION_OFF,Uncorrected errors locations. For more details. see the RAS Data Protection (DP) section in the Core Operations chapter of the Databook." hexmask.long.byte 0x4 24.--31. 1. "LOC_LAST_UNCORR_ERROR,Location/ID of the last uncorrected error within the region defined by REG_LAST_UNCORR_ERROR. You can cycle this field value from 0 to 255 to access all counters according to the detailed report of check points at.." newline hexmask.long.byte 0x4 20.--23. 1. "REG_LAST_UNCORR_ERROR,Region of the last uncorrected error: - 0x0: Region select for Adm Rx path - 0x1: Region select for layer 3 Rx path - 0x2: Region select for layer 2 Rx path - 0x3: Region select for DMA inbound path - 0x4: Region select for AXI.." newline hexmask.long.byte 0x4 16.--19. 1. "RSVDP_16,Reserved for future use." newline hexmask.long.byte 0x4 8.--15. 1. "LOC_FIRST_UNCORR_ERROR,Location/ID of the first uncorrected error within the region defined by REG_FIRST_UNCORR_ERROR. You can cycle this field value from 0 to 255 to access all counters according to the detailed report of check points at.." newline hexmask.long.byte 0x4 4.--7. 1. "REG_FIRST_UNCORR_ERROR,Region of the first uncorrected error: - 0x0: Region select for Adm Rx path - 0x1: Region select for layer 3 Rx path - 0x2: Region select for layer 2 Rx path - 0x3: Region select for DMA inbound path - 0x4: Region select for AXI.." newline hexmask.long.byte 0x4 0.--3. 1. "RSVDP_0,Reserved for future use." group.long (0x28+0x480)++0x7 line.long 0x0 "RASDP_ERROR_MODE_EN_OFF,RASDP error mode enable. The controller enters RASDP error mode (if ERROR_MODE_EN =1) upon detection of the first uncorrectable error. During this mode: - Rx TLPs that are forwarded to your application are not guaranteed to be.." hexmask.long 0x0 2.--31. 1. "RSVDP_2,Reserved for future use." newline bitfld.long 0x0 1. "AUTO_LINK_DOWN_EN,Write '1' to enable the controller to bring the link down when the controller enters RASDP error mode. Note: This register field is sticky." "0,1" newline bitfld.long 0x0 0. "ERROR_MODE_EN,Write '1' to enable the controller enter RASDP error mode when it detects an uncorrectable error. Note: This register field is sticky." "0,1" line.long 0x4 "RASDP_ERROR_MODE_CLEAR_OFF,Exit RASDP error mode. For more details. see the RAS Data Protection (DP) section in the Core Operations chapter of the Databook." hexmask.long 0x4 1.--31. 1. "RSVDP_1,Reserved for future use." newline bitfld.long 0x4 0. "ERROR_MODE_CLEAR,Write '1' to take the controller out of RASDP error mode. The controller will then report uncorrectable errors (through AER internal error reporting) and also stop nullifying/discarding TLPs." "0,1" rgroup.long (0x30+0x480)++0x7 line.long 0x0 "RASDP_RAM_ADDR_CORR_ERROR_OFF,RAM Address where a corrected error (1-bit ECC) has been detected. For more details. see the RAS Data Protection (DP) section in the Core Operations chapter of the Databook." hexmask.long.byte 0x0 28.--31. 1. "RAM_INDEX_CORR_ERROR,RAM index where a corrected error (1-bit ECC) has been detected." newline bitfld.long 0x0 27. "RSVDP_27,Reserved for future use." "0,1" newline hexmask.long 0x0 0.--26. 1. "RAM_ADDR_CORR_ERROR,RAM Address where a corrected error (1-bit ECC) has been detected." line.long 0x4 "RASDP_RAM_ADDR_UNCORR_ERROR_OFF,RAM Address where an uncorrected error (2-bit ECC) has been detected. For more details. see the RAS Data Protection (DP) section in the Core Operations chapter of the Databook." hexmask.long.byte 0x4 28.--31. 1. "RAM_INDEX_UNCORR_ERROR,RAM index where an uncorrected error (2-bit ECC) has been detected." newline bitfld.long 0x4 27. "RSVDP_27,Reserved for future use." "0,1" newline hexmask.long 0x4 0.--26. 1. "RAM_ADDR_UNCORR_ERROR,RAM Address where an uncorrected error (2-bit ECC) has been detected." tree.end tree "PF0_RTR_CAP (PF RTR Capability Structure)" group.long (0x0+0x2F8)++0xB line.long 0x0 "RTR_EXT_CAP_HDR_OFF,Readiness Time Reporting PCI Express Extended Capability Header. For a description of this standard PCIe register. see the PCI Express Specification." hexmask.long.word 0x0 20.--31. 1. "RTR_NEXT_OFFSET,Next Capability Offset. For a description of this standard PCIe register field see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky).." hexmask.long.byte 0x0 16.--19. 1. "RTR_CAP_VERSION,Capability Version. For a description of this standard PCIe register field see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky).." hexmask.long.word 0x0 0.--15. 1. "RTR_EXT_CAP_ID,PCI Express Extended Capability ID. For a description of this standard PCIe register field see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then.." line.long 0x4 "READI_TIME_REPORTING1_OFF,Readiness Time Reporting 1. For a description of this standard PCIe register. see the PCI Express Specification." bitfld.long 0x4 31. "RTR_TIME_VALID,Valid. For a description of this standard PCIe register field see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky)" "0,1" hexmask.long.byte 0x4 24.--30. 1. "RSVDP_24,Reserved for future use." hexmask.long.word 0x4 12.--23. 1. "DL_UP_TIME,DL_UP Time. For a description of this standard PCIe register field see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky)" hexmask.long.word 0x4 0.--11. 1. "RESET_TIME,Reset Time. For a description of this standard PCIe register field see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky)" line.long 0x8 "READI_TIME_REPORTING2_OFF,Readiness Time Reporting 2. For a description of this standard PCIe register. see the PCI Express Specification." hexmask.long.byte 0x8 24.--31. 1. "RSVDP_24,Reserved for future use." hexmask.long.word 0x8 12.--23. 1. "D3HOT_D0_TIME,D3hot to D0 Time. For a description of this standard PCIe register field see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else.." hexmask.long.word 0x8 0.--11. 1. "FLR_TIME,FLR Time. For a description of this standard PCIe register field see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky)" tree.end tree "PF0_RTR_CAP_DBI2 (DBI2 Shadow Block: PF RTR Capability Structure)" rgroup.long (0x4+0x12F8)++0x7 line.long 0x0 "SHADOW_READI_TIME_REPORTING1_OFF,Shadow Register Readiness Time Reporting 1. For a description of this standard PCIe register. see the PCI Express Specification." bitfld.long 0x0 31. "RTR_TIME_VALID,Shadow Valid in the shadow register. For a description of this standard PCIe register field see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access - Dbi: No access - Dbi2: if.." "0,1" hexmask.long.tbyte 0x0 12.--30. 1. "RSVDP_12,Reserved for future use." hexmask.long.word 0x0 0.--11. 1. "RESET_TIME,Shadow Reset Time in the shadow register. For a description of this standard PCIe register field see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access - Dbi: No access - Dbi2: if.." line.long 0x4 "SHADOW_READI_TIME_REPORTING2_OFF,Shadow Register Readiness Time Reporting 2. For a description of this standard PCIe register. see the PCI Express Specification." hexmask.long.byte 0x4 24.--31. 1. "RSVDP_24,Reserved for future use." hexmask.long.word 0x4 12.--23. 1. "D3HOT_D0_TIME,Shadow D3hot to D0 Time in the shadow register. For a description of this standard PCIe register field see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access - Dbi: No access - Dbi2:.." hexmask.long.word 0x4 0.--11. 1. "FLR_TIME,Shadow FLR Time in the shadow register. For a description of this standard PCIe register field see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access - Dbi: No access - Dbi2: if.." tree.end tree "PF0_FRSQ_CAP (PF FRSQ Capability Structure)" group.long (0x0+0x2E8)++0xB line.long 0x0 "FRSQ_EXT_CAP_HDR_OFF,FRS Queuing Extended Capability Header. For a description of this standard PCIe register. see the PCI Express Specification." hexmask.long.word 0x0 20.--31. 1. "FRSQ_NEXT_OFFSET,Next Capability Offset. For a description of this standard PCIe register field see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then.." hexmask.long.byte 0x0 16.--19. 1. "FRSQ_CAP_VERSION,Capability Version. For a description of this standard PCIe register field see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky).." hexmask.long.word 0x0 0.--15. 1. "FRSQ_EXT_CAP_ID,PCI Express Extended Capability ID. For a description of this standard PCIe register field see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then.." line.long 0x4 "FRSQ_CAP_OFF,FRS Queuing Capability Register. For a description of this standard PCIe register. see the PCI Express Specification." hexmask.long.word 0x4 21.--31. 1. "RSVDP_21,Reserved for future use." hexmask.long.byte 0x4 16.--20. 1. "FRS_INT_MESSAGE_NUMBER,FRS Interrupt Message Number. For a description of this standard PCIe register field see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1).." hexmask.long.byte 0x4 12.--15. 1. "RSVDP_12,Reserved for future use." hexmask.long.word 0x4 0.--11. 1. "FRSQ_MAX_DEPTH,FRS Queue Max Depth. For a description of this standard PCIe register field see the PCI Express Specification." line.long 0x8 "FRSQ_CONTROL_FRSQ_STATUS_OFF,FRS Queuing Status and Control Register. For a description of this standard PCIe register. see the PCI Express Specification." hexmask.long.word 0x8 17.--31. 1. "RSVDP_17,Reserved for future use." bitfld.long 0x8 16. "FRS_INTERRUPT_ENABLE,FRS Interrupt Enable. For a description of this standard PCIe register field see the PCI Express Specification." "0,1" hexmask.long.word 0x8 2.--15. 1. "RSVDP_2,Reserved for future use." bitfld.long 0x8 1. "FRS_MESSAGE_OVERFLOW,FRS Message Overflow. For a description of this standard PCIe register field see the PCI Express Specification." "0,1" newline bitfld.long 0x8 0. "FRS_MESSAGE_RECEIVED,FRS Message Received. For a description of this standard PCIe register field see the PCI Express Specification." "0,1" rgroup.long (0xC+0x2E8)++0x3 line.long 0x0 "FRS_MESSAGE_QUEUE_OFF,FRS Message Queue Register. For a description of this standard PCIe register. see the PCI Express Specification." hexmask.long.word 0x0 20.--31. 1. "FRS_MESSAGE_QUE_DEPTH,FRS Message Queue Depth. For a description of this standard PCIe register field see the PCI Express Specification." hexmask.long.byte 0x0 16.--19. 1. "FRS_MESSAGE_QUE_REASON,FRS Message Queue Reason. For a description of this standard PCIe register field see the PCI Express Specification." hexmask.long.word 0x0 0.--15. 1. "FRS_MESSAGE_QUE_FUNC_ID,FRS Message Queue Function ID. For a description of this standard PCIe register field see the PCI Express Specification." tree.end tree "PF0_PTM_CAP (PF PTM Capability Structure)" group.long (0x0+0x40C)++0xB line.long 0x0 "PTM_EXT_CAP_HDR_OFF,Precision Time Measurement Capability Header. For a description of this standard PCIe register. see the PCI Express Specification." hexmask.long.word 0x0 20.--31. 1. "PTM_NEXT_OFFSET,Precision Time Measurement PCI Express Extended Capability Next Offset. For a description of this standard PCIe register see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access. -.." hexmask.long.byte 0x0 16.--19. 1. "PTM_CAP_VERSION,Precision Time Measurement PCI Express Extended Capability Version. For a description of this standard PCIe register see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi:.." hexmask.long.word 0x0 0.--15. 1. "PTM_CAP_ID,Precision Time Measurement PCI Express Extended Capability ID. For a description of this standard PCIe register see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if.." line.long 0x4 "PTM_CAP_OFF,PTM Capability Register. For a description of this standard PCIe register. see the PCI Express Specification." hexmask.long.word 0x4 16.--31. 1. "RSVDP_16,Reserved for future use." hexmask.long.byte 0x4 8.--15. 1. "PTM_CLK_GRAN,PTM Local Clock Granularity. For a description of this standard PCIe register see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky).." hexmask.long.byte 0x4 3.--7. 1. "RSVDP_3,Reserved for future use." bitfld.long 0x4 2. "PTM_ROOT_CAPABLE,PTM Root Capable. For a description of this standard PCIe register see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else.." "0,1" bitfld.long 0x4 1. "PTM_RES_CAPABLE,PTM Responder Capable. For a description of this standard PCIe register see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else.." "0,1" newline bitfld.long 0x4 0. "PTM_REQ_CAPABLE,PTM Requester Capable. For a description of this standard PCIe register see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else.." "0,1" line.long 0x8 "PTM_CONTROL_OFF,PTM Control Register. For a description of this standard PCIe register. see the PCI Express Specification." hexmask.long.word 0x8 16.--31. 1. "RSVDP_16,Reserved for future use." hexmask.long.byte 0x8 8.--15. 1. "EFF_GRAN,PTM Effective Granularity. For a description of this standard PCIe register see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: HWINIT" hexmask.long.byte 0x8 2.--7. 1. "RSVDP_2,Reserved for future use." rbitfld.long 0x8 1. "ROOT_SELECT,PTM Root Select. When set this Time Source is the PTM Root. For a description of this standard PCIe register see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: HWINIT" "0,1" bitfld.long 0x8 0. "PTM_ENABLE,PTM Enable. When set this function is permitted to participate in the PTM mechanism. For a description of this standard PCIe register see the PCI Express Specification." "0,1" tree.end tree "PF0_PTM_RES_CAP (PF PTM Responder Capability Structure (VSEC))" group.long (0x0+0x418)++0xB line.long 0x0 "PTM_RES_CAP_HDR_OFF,Precision Time Measurement Responder Capability Header (VSEC). For more details. see the PTM section in the Databook." hexmask.long.word 0x0 20.--31. 1. "PTM_RES_EXT_CAP_NEXT_OFFS,Precision Time Measurement Responder VSEC Next Pointer. For more details see the PTM section in the Databook. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then.." hexmask.long.byte 0x0 16.--19. 1. "PTM_RES_EXT_CAP_VER,Precision Time Measurement Responder VSEC Version. For more details see the PTM section in the Databook. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else.." hexmask.long.word 0x0 0.--15. 1. "PTM_RES_EXT_CAP_ID,Precision Time Measurement Responder VSEC ID. For more details see the PTM section in the Databook. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else.." line.long 0x4 "PTM_RES_HDR_OFF,Precision Time Measurement Responder Vendor Specific Header. For more details. see the PTM section in the Databook." hexmask.long.word 0x4 20.--31. 1. "PTM_RES_VSEC_LENGTH,PTM Responder VSEC Length. For more details see the PTM section in the Databook. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This.." hexmask.long.byte 0x4 16.--19. 1. "PTM_RES_VSEC_REV,PTM Responder VSEC Revision. For more details see the PTM section in the Databook. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This.." hexmask.long.word 0x4 0.--15. 1. "PTM_RES_VSEC_ID,PTM Responder VSEC ID. For more details see the PTM section in the Databook. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register.." line.long 0x8 "PTM_RES_CONTROL_OFF,PTM Responder Control Register. For more details. see the PTM section in the Databook." hexmask.long 0x8 2.--31. 1. "RSVDP_2,Reserved for future use." bitfld.long 0x8 1. "PTM_RES_PDEL_BYTE_REV,PTM Requester Propagation Delay Byte Reversal - Reverse the order of bytes in the PTM Propagation Delay data word of the PTM ResponseD Message for compatibility with previous revisions. For more details see the PTM section in the.." "0,1" bitfld.long 0x8 0. "PTM_RES_CCONTEXT_VALID,PTM Responder Control Context Valid - PTM Local Timing is valid. This bit is set over the DBI. A speed change or aux_clk_active will set this bit low. For more details see the PTM section in the Databook. Note: The access.." "0,1" rgroup.long (0xC+0x418)++0x3 line.long 0x0 "PTM_RES_STATUS_OFF,PTM Responder Status Register. For more details. see the PTM section in the Databook." hexmask.long 0x0 2.--31. 1. "RSVDP_2,Reserved for future use." bitfld.long 0x0 1. "PTM_RES_REQUEST_RECEIVED,PTM 1st Request Received - PTM Responder has received the first PTM Request Message. Upon receipt of a second PTM Request Message a ResponseD message with timing information will be sent from the Responder if the context is.." "0,1" bitfld.long 0x0 0. "PTM_RES_CONTEXT_VALID,PTM Responder Status Context Valid - PTM Local Timing Context is Valid. Value set from upstream port Requester in a Switch. Shadows the same in the control register in all other products. For more details see the PTM section in the.." "0,1" group.long (0x10+0x418)++0x7 line.long 0x0 "PTM_RES_LOCAL_LSB_OFF,PTM Responder Local Clock LSB. For more details. see the PTM section in the Databook." hexmask.long 0x0 0.--31. 1. "PTM_RES_LOCAL_LSB,PTM Responder Local Clock LSB - Lower 32 bits of local timer value. For more details see the PTM section in the Databook. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then.." line.long 0x4 "PTM_RES_LOCAL_MSB_OFF,PTM Responder Local Clock MSB. For more details. see the PTM section in the Databook." hexmask.long 0x4 0.--31. 1. "PTM_RES_LOCAL_MSB,PTM Responder Local Clock MSB - Upper 32 bits of local timer value. For more details see the PTM section in the Databook. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then.." rgroup.long (0x18+0x418)++0x1F line.long 0x0 "PTM_RES_T2_LSB_OFF,PTM Responder T2 Timestamp LSB. For more details. see the PTM section in the Databook." hexmask.long 0x0 0.--31. 1. "PTM_RES_T2_LSB,PTM Responder T2 Timestamp LSB - Lower 32 bits of the T2 Timestamp value. For more details see the PTM section in the Databook. Note: This register field is sticky." line.long 0x4 "PTM_RES_T2_MSB_OFF,PTM Responder T2 Timestamp MSB. For more details. see the PTM section in the Databook." hexmask.long 0x4 0.--31. 1. "PTM_RES_T2_MSB,PTM Responder T2 Timestamp MSB - Upper 32 bits of the T2 Timestamp value. For more details see the PTM section in the Databook. Note: This register field is sticky." line.long 0x8 "PTM_RES_T2P_LSB_OFF,PTM Responder T2 Previous Timestamp LSB. For more details. see the PTM section in the Databook." hexmask.long 0x8 0.--31. 1. "PTM_RES_T2P_LSB,PTM Responder T2 Previous Timestamp LSB - Lower 32 bits of the previously stored T2 Timestamp value. For more details see the PTM section in the Databook. Note: This register field is sticky." line.long 0xC "PTM_RES_T2P_MSB_OFF,PTM Responder T2 Previous Timestamp MSB. For more details. see the PTM section in the Databook." hexmask.long 0xC 0.--31. 1. "PTM_RES_T2P_MSB,PTM Responder T2 Previous Timestamp MSB - Upper 32 bits of the previously stored T2 Timestamp value. For more details see the PTM section in the Databook. Note: This register field is sticky." line.long 0x10 "PTM_RES_T3_LSB_OFF,PTM Responder T3 Timestamp LSB. For more details. see the PTM section in the Databook." hexmask.long 0x10 0.--31. 1. "PTM_RES_T3_LSB,PTM Responder T3 Timestamp LSB - Lower 32 bits of the T3 Timestamp value. For more details see the PTM section in the Databook. Note: This register field is sticky." line.long 0x14 "PTM_RES_T3_MSB_OFF,PTM Responder T3 Timestamp MSB. For more details. see the PTM section in the Databook." hexmask.long 0x14 0.--31. 1. "PTM_RES_T3_MSB,PTM Responder T3 Timestamp MSB - Upper 32 bits of the T2 Timestamp value. For more details see the PTM section in the Databook. Note: This register field is sticky." line.long 0x18 "PTM_RES_T3P_LSB_OFF,PTM Responder T3 Previous Timestamp LSB. For more details. see the PTM section in the Databook." hexmask.long 0x18 0.--31. 1. "PTM_RES_T3P_LSB,PTM Responder T3 Previous Timestamp LSB - Lower 32 bits of the previously stored T3 Timestamp value. For more details see the PTM section in the Databook. Note: This register field is sticky." line.long 0x1C "PTM_RES_T3P_MSB_OFF,PTM Responder T3 Previous Timestamp MSB. For more details. see the PTM section in the Databook." hexmask.long 0x1C 0.--31. 1. "PTM_RES_T3P_MSB,PTM Responder T3 Previous Timestamp MSB - Upper 32 bits of the previously stored T3 Timestamp value. For more details see the PTM section in the Databook. Note: This register field is sticky." group.long (0x38+0x418)++0x7 line.long 0x0 "PTM_RES_TX_LATENCY_OFF,PTM Responder TX Latency. For more details. see the PTM section in the Databook." hexmask.long.tbyte 0x0 12.--31. 1. "RSVDP_12,Reserved for future use." hexmask.long.word 0x0 0.--11. 1. "PTM_RES_TX_LATENCY,PTM Responder TX Latency - Responder Transmit path latency (12 bit wide). For more details see the PTM section in the Databook. Note: This register field is sticky." line.long 0x4 "PTM_RES_RX_LATENCY_OFF,PTM Responder RX Latency. For more details. see the PTM section in the Databook." hexmask.long.tbyte 0x4 12.--31. 1. "RSVDP_12,Reserved for future use." hexmask.long.word 0x4 0.--11. 1. "PTM_RES_RX_LATENCY,PTM Responder RX Latency - Responder Receive path latency (12 bit wide). For more details see the PTM section in the Databook. Note: This register field is sticky." rgroup.long (0x40+0x418)++0x3 line.long 0x0 "PTM_RES_NOM_CLOCK_T_OFF,PTM Responder Nominal Clock Period. For more details. see the PTM section in the Databook." hexmask.long.byte 0x0 24.--31. 1. "RSVDP_24,Reserved for future use." hexmask.long.byte 0x0 16.--23. 1. "PTM_RES_NOM_CLOCK_T_INT,PTM Responder Nominal Clock Period Integral - Integral part of the nominal PTM local clock period in nanoseconds. For more details see the PTM section in the Databook. Note: This register field is sticky." hexmask.long.word 0x0 0.--15. 1. "PTM_RES_NOM_CLOCK_T_FRAC,PTM Responder Nominal Clock Period Fractional - Fractional part of the nominal PTM local clock period. LSB is 1/(2^16) nanoseconds. For more details see the PTM section in the Databook. Note: This register field is sticky." group.long (0x44+0x418)++0x3 line.long 0x0 "PTM_RES_SCALED_CLOCK_T_OFF,PTM Responder Scaled Clock Period. For more details. see the PTM section in the Databook." bitfld.long 0x0 31. "PTM_RES_SCALED_CLOCK_T_EN,PTM Responder Scaled Clock Period Enable - Use the programmed scaled PTM clock period rather than the nominal values. This bit is cleared when the core_clk rate starts to change and can only be set when the clock period change.." "0,1" hexmask.long.byte 0x0 24.--30. 1. "RSVDP_24,Reserved for future use." hexmask.long.byte 0x0 16.--23. 1. "PTM_RES_SCALED_CLOCK_T_INT,PTM Responder Scaled Clock Period Integral - Integral part of the nominal PTM local clock period in nanoseconds. For more details see the PTM section in the Databook. Note: This register field is sticky." newline hexmask.long.word 0x0 0.--15. 1. "PTM_RES_SCALED_CLOCK_T_FRAC,PTM Responder Scaled Clock Period Fractional - Fractional part of the nominal PTM local clock period. LSB is 1/(2^16) nanoseconds. For more details see the PTM section in the Databook. Note: This register field is sticky." tree.end tree "PF0_PM_CAP (PF PCI Power Management Capability Structure)" group.long (0x0+0x40)++0x7 line.long 0x0 "CAP_ID_NXT_PTR_REG,Power Management Capabilities Register." hexmask.long.byte 0x0 27.--31. 1. "PME_SUPPORT,PME_Support. This 5-bit field indicates the power states in which the function may generate a PME and/or forward PME messages. A value of 0b for any bit indicates that the function is not capable of asserting PME while in that power state. -.." bitfld.long 0x0 26. "D2_SUPPORT,D2_Support. If this bit is set this function supports the D2 Power Management state. Functions that do not support D2 must always return a value of 0b for this bit. Note: The access attributes of this field are as follows: - Wire: No access." "0,1" bitfld.long 0x0 25. "D1_SUPPORT,D1_Support. If this bit is set this function supports the D1 Power Management state. Functions that do not support D1 must always return a value of 0b for this bit. Note: The access attributes of this field are as follows: - Wire: No access." "0,1" bitfld.long 0x0 22.--24. "AUX_CURR,Aux_Current. This 3 bit field reports the Vaux auxiliary current requirements for the function. If this function implements the Data Register the controller hardwires this field to 000b. If PME_Support is 0 xxxxb (PME assertion from D3cold is.." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 21. "DSI,Device Specific Initialization. The DSI bit indicates whether special initialization of this function is required. When set indicates that the function requires a device specific initialization sequence following a transition to the D0uninitialized.." "0,1" bitfld.long 0x0 20. "PME_IMM_READI_RETURN_DO,Immediate_Readiness_on_Return_to_D0. - If this bit is a '1' this function is guaranteed to be ready to successfully complete valid accesses immediately after being set to D0. These accesses include configuration cycles and if.." "0,1" rbitfld.long 0x0 19. "PME_CLK,PME Clock. Does not apply to PCI Express the controller hardwires it to 0b. Note: This register field is sticky." "0,1" bitfld.long 0x0 16.--18. "PM_SPEC_VER,Version. This field provides the Power Management specification version. The controller hardwires this field to 011b for functions compliant to PCI Express Base Specification Revision 4.0 Version 1.0>. Note: The access attributes of this.." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x0 8.--15. 1. "PM_NEXT_POINTER,Next Capability Pointer. This field provides an offset into the function's configuration space pointing to the location of next item in the capabilities list. If there are no additional items in the capabilities list this field is set to.." hexmask.long.byte 0x0 0.--7. 1. "PM_CAP_ID,Capability ID. This field returns 01h to indicate that this is the PCI Power Management Capability. Each function may have only one item in its capability list with Capability ID set to 01h." line.long 0x4 "CON_STATUS_REG,Power Management Control and Status Register. This register is used to manage the PCI function's power management state as well as to enable/monitor PMEs." hexmask.long.byte 0x4 24.--31. 1. "DATA_REG_ADD_INFO,Data. This field is used to report the state dependent data requested by the Data_Select field. The value of this field is scaled by the value reported by the Data_Scale field." rbitfld.long 0x4 23. "BUS_PWR_CLK_CON_EN,Bus Power/Clock Control Enable. For a description of this standard PCIe register field see the PCI Express Base Specification." "0,1" rbitfld.long 0x4 22. "B2_B3_SUPPORT,B2B3 Support for D3hot. For a description of this standard PCIe register field see the PCI Express Base Specification." "0,1" hexmask.long.byte 0x4 16.--21. 1. "RSVDP_16,Reserved for future use." newline bitfld.long 0x4 15. "PME_STATUS,PME_Status. This bit is set when the function normally generates a PME signal. The value of this bit is not affected by the value of the PME_En bit. If PME_Support bit 31 of the Power Management Capabilities register is clear this bit is.." "0,1" rbitfld.long 0x4 13.--14. "DATA_SCALE,Data_Scale. This field indicates the scaling factor to be used when interpreting the value of the Data field. The value and meaning of this field varies depending on which data value has been selected by the Data_Select field. For more details.." "0,1,2,3" hexmask.long.byte 0x4 9.--12. 1. "DATA_SELECT,Data_Select. This 4-bit field is used to select which data is to be reported through the Data and Data_Scale field. If the Data field is not implemented this field must be hardwired to 0000b." bitfld.long 0x4 8. "PME_ENABLE,PME_En. - When set the function is permitted to generate a PME. - When clear the function is not permitted to generate a PME. If PME_Support is 1 xxxxb (PME generation from D3cold) or the function consumes Aux power and Aux power is.." "0,1" newline hexmask.long.byte 0x4 4.--7. 1. "RSVDP_4,Reserved for future use." bitfld.long 0x4 3. "NO_SOFT_RST,No_Soft_Reset. This bit indicates the state of the function after writing the PowerState field to transition the function from D3hot to D0. - When set this transition preserves internal function state. The function is in D0Active and no.." "0,1" rbitfld.long 0x4 2. "RSVDP_2,Reserved for future use." "0,1" bitfld.long 0x4 0.--1. "POWER_STATE,PowerState. This 2-bit field is used both to determine the current power state of a function and to set the function into a new power state. The definition of the field values is given below. You can write to this register; however the.." "D0,D1,D2,D3hot" tree.end tree "PF0_PCIE_CAP (PF PCI Express Capability Structure)" group.long (0x0+0x70)++0x33 line.long 0x0 "PCIE_CAP_ID_PCIE_NEXT_CAP_PTR_PCIE_CAP_REG,PCI Express Capabilities. ID. Next Pointer Register." rbitfld.long 0x0 31. "RSVDP_31,Reserved for future use." "0,1" rbitfld.long 0x0 30. "RSVD,Reserved." "0,1" newline hexmask.long.byte 0x0 25.--29. 1. "PCIE_INT_MSG_NUM,PCIE Interrupt Message Number. For a description of this standard PCIe register field see the PCI Express Base Specification. Interrupt Message Number. This field indicates which MSI/MSI-X vector is used for the interrupt message.." bitfld.long 0x0 24. "PCIE_SLOT_IMP,Slot Implemented. When set this bit indicates that the Link associated with this Port is connected to a slot (as compared to being connected to a system-integrated device or being disabled). This bit is valid for Downstream Ports. This bit.." "0,1" newline hexmask.long.byte 0x0 20.--23. 1. "PCIE_DEV_PORT_TYPE,Device/Port Type. Indicates the specific type of this PCI Express function. Note: Different functions in a Multi-Function Device can generally be of different types. Defined encodings for functions that implement a Type 00h PCI.." hexmask.long.byte 0x0 16.--19. 1. "PCIE_CAP_REG,Capability Version. Indicates PCI-SIG defined PCI Express Capability structure version number. A version of the specification that changes the PCI Express Capability structure in a way that is not otherwise identifiable (for example through.." newline hexmask.long.byte 0x0 8.--15. 1. "PCIE_CAP_NEXT_PTR,Next Capability Pointer. This field contains the offset to the next PCI Capability structure or 00h if no other items exist in the linked list of Capabilities. Note: The access attributes of this field are as follows: - Wire: No access." hexmask.long.byte 0x0 0.--7. 1. "PCIE_CAP_ID,Capability ID. Indicates the PCI Express Capability structure. This field must return a Capability ID of 10h indicating that this is a PCI Express Capability structure." line.long 0x4 "DEVICE_CAPABILITIES_REG,Device Capabilities Register. The Device Capabilities register identifies PCI Express device function specific capabilities." hexmask.long.word 0x4 16.--31. 1. "RSVDP_16,Reserved for future use." bitfld.long 0x4 15. "PCIE_CAP_ROLE_BASED_ERR_REPORT,Role-Based Error Reporting. When set this bit indicates that the function implements the functionality originally defined in the Error Reporting ECN for PCI Express Base Specification Revision 1.0a and later incorporated.." "0,1" newline hexmask.long.word 0x4 6.--14. 1. "RSVDP_6,Reserved for future use." bitfld.long 0x4 5. "PCIE_CAP_EXT_TAG_SUPP,Extended Tag Field Supported. This bit in combination with the 10-Bit Tag Requester Supported bit in the Device Capabilities 2 register indicates the maximum supported size of the Tag field as a Requester. This bit must be set if.." "0,1" newline bitfld.long 0x4 3.--4. "PCIE_CAP_PHANTOM_FUNC_SUPPORT,Phantom Functions Supported. This field indicates the support for use of unclaimed function numbers to extend the number of outstanding transactions allowed by logically combining unclaimed function numbers (called Phantom.." "0,1,2,3" bitfld.long 0x4 0.--2. "PCIE_CAP_MAX_PAYLOAD_SIZE,Max_Payload_Size Supported. This field indicates the maximum payload size that the function can support for TLPs. Defined encodings are: - 000b: 128 bytes max payload size - 001b: 256 bytes max payload size - 010b: 512 bytes max.." "0,1,2,3,4,5,6,7" line.long 0x8 "DEVICE_CONTROL_DEVICE_STATUS,Device Control and Device Status Register. This register controls PCI Express device specific parameters and provides information about PCI Express device (function) specific parameters." hexmask.long.word 0x8 22.--31. 1. "RSVDP_22,Reserved for future use." rbitfld.long 0x8 21. "PCIE_CAP_TRANS_PENDING,Transactions Pending. Endpoints: When set this bit indicates that the function has issued Non-Posted Requests that have not been completed. A Function reports this bit cleared only when all outstanding Non-Posted Requests have.." "0,1" newline rbitfld.long 0x8 20. "PCIE_CAP_AUX_POWER_DETECTED,AUX Power Detected. Functions that require Aux power report this bit as set if Aux power is detected by the function. This bit is derived by sampling the sys_aux_pwr_det input." "0,1" bitfld.long 0x8 19. "PCIE_CAP_UNSUPPORTED_REQ_DETECTED,Unsupported Request Detected. This bit indicates that the function received an Unsupported Request. Errors are logged in this register regardless of whether error reporting is enabled or not in the Device Control.." "0,1" newline bitfld.long 0x8 18. "PCIE_CAP_FATAL_ERR_DETECTED,Fatal Error Detected. This bit indicates status of Fatal errors detected. Errors are logged in this register regardless of whether error reporting is enabled or not in the Device Control register. For a Multi-Function device.." "0,1" bitfld.long 0x8 17. "PCIE_CAP_NON_FATAL_ERR_DETECTED,Non-Fatal Error Detected. This bit indicates status of Non-fatal errors detected. Errors are logged in this register regardless of whether error reporting is enabled or not in the Device Control register. For a.." "0,1" newline bitfld.long 0x8 16. "PCIE_CAP_CORR_ERR_DETECTED,Correctable Error Detected. This bit indicates status of correctable errors detected. Errors are logged in this register regardless of whether error reporting is enabled or not in the Device Control register. For a.." "0,1" bitfld.long 0x8 15. "PCIE_CAP_INITIATE_FLR,Initiate Function Level Reset (applicable to Endpoints with Function Level Reset Capability set to 1b). A write of 1b initiates Function Level Reset to the Function. The value read by software from this bit is always 0b." "0,1" newline bitfld.long 0x8 12.--14. "PCIE_CAP_MAX_READ_REQ_SIZE,Max_Read_Request_Size. This field sets the maximum Read Request size for the function as a Requester. The function must not generate Read Requests with a size exceeding the set value. Defined encodings for this field are: -.." "0,1,2,3,4,5,6,7" rbitfld.long 0x8 11. "PCIE_CAP_EN_NO_SNOOP,Enable No Snoop. If this bit is set the function is permitted to Set the No Snoop bit in the Requester Attributes of transactions it initiates that do not require hardware enforced cache coherency (see section 2.2.6.5 in PCI Express.." "0,1" newline bitfld.long 0x8 10. "PCIE_CAP_AUX_POWER_PM_EN,Aux Power PM Enable. This bit is derived by sampling the sys_aux_pwr_det input. When set this bit enables a function to draw Aux power independent of PME Aux power. Functions that require Aux power on legacy operating systems.." "0,1" rbitfld.long 0x8 9. "PCIE_CAP_PHANTOM_FUNC_EN,Phantom Functions Enable. This bit in combination with the 10-Bit Tag Requester Enable bit in the Device Control 2 register determines how many Tag field bits a Requester is permitted to use. When the 10-Bit Tag Requester.." "0,1" newline rbitfld.long 0x8 8. "PCIE_CAP_EXT_TAG_EN,Extended Tag Field Enable. This bit in combination with the 10-Bit Tag Requester Enable bit in the Device Control 2 register determines how many Tag field bits a Requester is permitted to use. When the 10-Bit Tag Requester Enable.." "0,1" bitfld.long 0x8 5.--7. "PCIE_CAP_MAX_PAYLOAD_SIZE_CS,Max_Payload_Size. This field sets maximum TLP payload size for the Function. As a Receiver the Function must handle TLPs as large as the set value. As a Transmitter the Function must not generate TLPs exceeding the set.." "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 4. "PCIE_CAP_EN_REL_ORDER,Enable Relaxed Ordering. If this bit is set the function is permitted to set the Relaxed Ordering bit in the Attributes field of transactions it initiates that do not require strong write ordering (for more details see section.." "0,1" bitfld.long 0x8 3. "PCIE_CAP_UNSUPPORT_REQ_REP_EN,Unsupported Request Reporting Enable. This bit in conjunction with other bits controls the signaling of Unsupported Request Errors by sending error Messages (for more details see section 6.2.5 and section 6.2.6 of PCI.." "0,1" newline bitfld.long 0x8 2. "PCIE_CAP_FATAL_ERR_REPORT_EN,Fatal Error Reporting Enable. This bit in conjunction with other bits controls sending ERR_FATAL Messages (for more details see section 6.2.5 and section 6.2.6 of of PCI Express Base Specification). For a Multi-Function.." "0,1" bitfld.long 0x8 1. "PCIE_CAP_NON_FATAL_ERR_REPORT_EN,Non-Fatal Error Reporting Enable. This bit in conjunction with other bits controls sending ERR_NONFATAL Messages (for more details see section 6.2.5 and Section 6.2.6 of PCI Express Base Specification). For a.." "0,1" newline bitfld.long 0x8 0. "PCIE_CAP_CORR_ERR_REPORT_EN,Correctable Error Reporting Enable. This bit in conjunction with other bits controls sending ERR_COR Messages (for more details see section 6.2.5 section 6.2.6 and section 6.2.10.2 of PCI Express Base Specification). For.." "0,1" line.long 0xC "LINK_CAPABILITIES_REG,Link Capabilities Register. The Link Capabilities register identifies PCI Express Link specific capabilities." hexmask.long.byte 0xC 24.--31. 1. "PCIE_CAP_PORT_NUM,Port Number. This field indicates the PCI Express Port number for the given PCI Express Link. Multi-Function Devices associated with an Upstream Port must report the same value in this field for all functions. Note: The access.." rbitfld.long 0xC 23. "RSVDP_23,Reserved for future use." "0,1" newline bitfld.long 0xC 22. "PCIE_CAP_ASPM_OPT_COMPLIANCE,ASPM Optionality Compliance. This bit must be set to 1b in all functions. Components implemented against certain earlier versions of this specification will have this bit set to 0b. Software is permitted to use the value of.." "0,1" bitfld.long 0xC 21. "PCIE_CAP_LINK_BW_NOT_CAP,Link Bandwidth Notification Capability. A value of 1b indicates support for the Link Bandwidth Notification status and interrupt mechanisms. This capability is required for all Root Ports and Switch Downstream Ports supporting.." "0,1" newline rbitfld.long 0xC 20. "PCIE_CAP_DLL_ACTIVE_REP_CAP,Data Link Layer Link Active Reporting Capable. For a Downstream Port the controller hardwires this bit to 1b if the component supports the optional capability of reporting the DL_Active state of the Data Link Control and.." "0,1" bitfld.long 0xC 19. "PCIE_CAP_SURPRISE_DOWN_ERR_REP_CAP,Surprise Down Error Reporting Capable. For a Downstream Port this bit must be set if the component supports the optional capability of detecting and reporting a Surprise Down error condition. For Upstream Ports and.." "0,1" newline rbitfld.long 0xC 18. "PCIE_CAP_CLOCK_POWER_MAN,Clock Power Management. For Upstream Ports a value of 1b in this bit indicates that the component tolerates the removal of any reference clock(s) via the 'clock request' (CLKREQ#) mechanism when the Link is in the L1 and L2/L3.." "0,1" bitfld.long 0xC 15.--17. "PCIE_CAP_L1_EXIT_LATENCY,L1 Exit Latency. This field indicates the L1 exit latency for the given PCI Express Link. The value reported indicates the length of time this Port requires to complete transition from ASPM L1 to L0. If ASPM L1 is not supported.." "0,1,2,3,4,5,6,7" newline bitfld.long 0xC 12.--14. "PCIE_CAP_L0S_EXIT_LATENCY,L0s Exit Latency. This field indicates the L0s exit latency for the given PCI Express Link. The value reported indicates the length of time this Port requires to complete transition from L0s to L0. If L0s is not supported the.." "0,1,2,3,4,5,6,7" bitfld.long 0xC 10.--11. "PCIE_CAP_ACTIVE_STATE_LINK_PM_SUPPORT,Active State Power Management (ASPM) Support. This field indicates the level of ASPM supported on the given PCI Express Link. For more details on ASPM support requirements see section 5.4.1 of PCI Express Base.." "0,1,2,3" newline hexmask.long.byte 0xC 4.--9. 1. "PCIE_CAP_MAX_LINK_WIDTH,Maximum Link Width. This field indicates the maximum Link width (xN - corresponding to N Lanes) implemented by the component. This value is permitted to exceed the number of Lanes routed to the slot (Downstream Port) adapter.." hexmask.long.byte 0xC 0.--3. 1. "PCIE_CAP_MAX_LINK_SPEED,Max Link Speed. This field indicates the maximum Link speed of the associated Port. The encoded value specifies a bit location in the Supported Link Speeds Vector (in the Link Capabilities 2 register) that corresponds to the.." line.long 0x10 "LINK_CONTROL_LINK_STATUS_REG,Link Control and Link Status Register. This register controls and provides information about PCI Express Link specific parameters." bitfld.long 0x10 31. "PCIE_CAP_LINK_AUTO_BW_STATUS,Link Autonomous Bandwidth Status. This bit is set by hardware to indicate that hardware has autonomously changed Link speed or width without the Port transitioning through DL_Down status for reasons other than to attempt to.." "0,1" bitfld.long 0x10 30. "PCIE_CAP_LINK_BW_MAN_STATUS,Link Bandwidth Management Status. This bit is set by hardware to indicate that either of the following has occurred without the Port transitioning through DL_Down status: - A Link retraining has completed following a write of.." "0,1" newline rbitfld.long 0x10 29. "PCIE_CAP_DLL_ACTIVE,Data Link Layer Link Active. This bit indicates the status of the Data Link Control and Management State Machine. It returns a 1b to indicate the DL_Active state 0b otherwise. This bit must be implemented if the Data Link Layer Link.." "0,1" bitfld.long 0x10 28. "PCIE_CAP_SLOT_CLK_CONFIG,Slot Clock Configuration. This bit indicates that the component uses the same physical reference clock that the platform provides on the connector. If the device uses an independent clock irrespective of the presence of a.." "0,1" newline rbitfld.long 0x10 27. "PCIE_CAP_LINK_TRAINING,Link Training. This read-only bit indicates that the Physical Layer LTSSM is in the Configuration or Recovery state or that 1b was written to the Retrain Link bit but Link training has not yet begun. Hardware clears this bit when.." "0,1" rbitfld.long 0x10 26. "RSVDP_26,Reserved for future use." "0,1" newline hexmask.long.byte 0x10 20.--25. 1. "PCIE_CAP_NEGO_LINK_WIDTH,Negotiated Link Width. This field indicates the negotiated width of the given PCI Express Link. Defined encodings are: -00 0001b: x1 -00 0010b: x2 -00 0100b: x4 -00 1000b: x8 -00 1100b: x12 -01 0000b: x16 -10 0000b: x32 All other.." hexmask.long.byte 0x10 16.--19. 1. "PCIE_CAP_LINK_SPEED,Current Link Speed. This field indicates the negotiated Link speed of the given PCI Express Link. The encoded value specifies a bit location in the Supported Link Speeds Vector (in the Link Capabilities 2 register) that corresponds to.." newline bitfld.long 0x10 14.--15. "PCIE_CAP_DRS_SIGNALING_CONTROL,DRS Signaling Control. Indicates the mechanism used to report reception of a DRS message. Must be implemented for Downstream Ports with the DRS Supported bit Set in the Link Capabilities 2 Register. Encodings are: - 00b:.." "0,1,2,3" rbitfld.long 0x10 12.--13. "RSVDP_12,Reserved for future use." "0,1,2,3" newline bitfld.long 0x10 11. "PCIE_CAP_LINK_AUTO_BW_INT_EN,Link Autonomous Bandwidth Management Interrupt Enable. When set this bit enables the generation of an interrupt to indicate that the Link Autonomous Bandwidth Status bit has been set. The write value is gated with the.." "0,1" bitfld.long 0x10 10. "PCIE_CAP_LINK_BW_MAN_INT_EN,Link Bandwidth Management Interrupt Enable. When set this bit enables the generation of an interrupt to indicate that the Link Bandwidth Management Status bit has been set. The write value is gated with the.." "0,1" newline bitfld.long 0x10 9. "PCIE_CAP_HW_AUTO_WIDTH_DISABLE,Hardware Autonomous Width Disable. When set this bit disables hardware from changing the Link width for reasons other than attempting to correct unreliable Link operation by reducing Link width. For a Multi-Function Device.." "0,1" bitfld.long 0x10 8. "PCIE_CAP_EN_CLK_POWER_MAN,Enable Clock Power Management. Applicable only for Upstream Ports and with form factors that support a 'Clock Request' (CLKREQ#) mechanism this bit operates as follows: - 0b: Clock power management is disabled and device must.." "0,1" newline bitfld.long 0x10 7. "PCIE_CAP_EXTENDED_SYNCH,Extended Synch. When set this bit forces the transmission of additional Ordered Sets when exiting the L0s state (see section 4.2.4.5 of PCI Express Base Specification) and when in the Recovery state (see section 4.2.6.4.1 of PCI.." "0,1" bitfld.long 0x10 6. "PCIE_CAP_COMMON_CLK_CONFIG,Common Clock Configuration. When set this bit indicates that this component and the component at the opposite end of this Link are operating with a distributed common reference clock. A value of 0b indicates that this.." "0,1" newline bitfld.long 0x10 5. "PCIE_CAP_RETRAIN_LINK,Retrain Link. A write of 1b to this bit initiates Link retraining by directing the Physical Layer LTSSM to the Recovery state. If the LTSSM is already in Recovery or Configuration re-entering Recovery is permitted but not required." "0,1" bitfld.long 0x10 4. "PCIE_CAP_LINK_DISABLE,Link Disable. This bit disables the Link by directing the LTSSM to the Disabled state when set; this bit is Reserved on Endpoints PCI Express to PCI/PCI-X bridges and Upstream Ports of Switches. Writes to this bit are immediately.." "0,1" newline bitfld.long 0x10 3. "PCIE_CAP_RCB,Read Completion Boundary (RCB). Root Ports: Indicates the RCB value for the Root Port. Refer to section 2.3.1.1 of PCI Express Base Specification for the definition of the parameter RCB. Defined encodings are: - 0b: 64 byte - 1b: 128 byte.." "0,1" rbitfld.long 0x10 2. "RSVDP_2,Reserved for future use." "0,1" newline bitfld.long 0x10 0.--1. "PCIE_CAP_ACTIVE_STATE_LINK_PM_CONTROL,Active State Power Management (ASPM) Control. This field controls the level of ASPM enabled on the given PCI Express Link. See section 5.4.1.3 of PCI Express Base Specification for requirements on when and how to.." "0,1,2,3" line.long 0x14 "SLOT_CAPABILITIES_REG,Slot Capabilities Register. The Slot Capabilities register identifies PCI Express slot specific capabilities." hexmask.long.word 0x14 19.--31. 1. "PCIE_CAP_PHY_SLOT_NUM,Physical Slot Number. This field indicates the physical slot number attached to this Port. This field must be hardware initialized to a value that assigns a slot number that is unique within the chassis regardless of the form.." bitfld.long 0x14 18. "PCIE_CAP_NO_CMD_CPL_SUPPORT,No Command Completed Support. When set this bit indicates that this slot does not generate software notification when an issued command is completed by the Hot-Plug Controller. This bit is only permitted to be set if the.." "0,1" newline bitfld.long 0x14 17. "PCIE_CAP_ELECTROMECH_INTERLOCK,Electromechanical Interlock Present. When set this bit indicates that an Electromechanical Interlock is implemented on the chassis for this slot. Note: The access attributes of this field are as follows: - Wire: No access." "0,1" bitfld.long 0x14 15.--16. "PCIE_CAP_SLOT_POWER_LIMIT_SCALE,Slot Power Limit Scale. Specifies the scale used for the Slot Power Limit Value (for more details see Section 6.9 of PCI Express Base Specification). Range of Values: - 00b: 1.0x - 01b: 0.1x - 10b: 0.01x - 11b: 0.001x.." "0,1,2,3" newline hexmask.long.byte 0x14 7.--14. 1. "PCIE_CAP_SLOT_POWER_LIMIT_VALUE,Slot Power Limit Value. In combination with the Slot Power Limit Scale value specifies the upper limit on power supplied by the slot (for more detais see Section 6.9 of PCI Express Base Specification) or by other means.." bitfld.long 0x14 6. "PCIE_CAP_HOT_PLUG_CAPABLE,Hot-Plug Capable. When set this bit indicates that this slot is capable of supporting hot-plug operations. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then R/W else R" "0,1" newline bitfld.long 0x14 5. "PCIE_CAP_HOT_PLUG_SURPRISE,Hot-Plug Surprise. When set this bit indicates that an adapter present in this slot might be removed from the system without any prior notification. This is a form factor specific capability. This bit is an indication to the.." "0,1" bitfld.long 0x14 4. "PCIE_CAP_POWER_INDICATOR,Power Indicator Present. When set this bit indicates that a Power Indicator is electrically controlled by the chassis for this slot. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if.." "0,1" newline bitfld.long 0x14 3. "PCIE_CAP_ATTENTION_INDICATOR,Attention Indicator Present. When set this bit indicates that an Attention Indicator is electrically controlled by the chassis. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if.." "0,1" bitfld.long 0x14 2. "PCIE_CAP_MRL_SENSOR,MRL Sensor Present. When set this bit indicates that an MRL Sensor is implemented on the chassis for this slot. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then R/W else R" "0,1" newline bitfld.long 0x14 1. "PCIE_CAP_POWER_CONTROLLER,Power Controller Present. When set this bit indicates that a software programmable Power Controller is implemented for this slot/adapter (depending on form factor). Note: The access attributes of this field are as follows: -.." "0,1" bitfld.long 0x14 0. "PCIE_CAP_ATTENTION_INDICATOR_BUTTON,Attention Button Present. When set this bit indicates that an Attention Button for this slot is electrically controlled by the chassis. Note: The access attributes of this field are as follows: - Wire: No access. -.." "0,1" line.long 0x18 "SLOT_CONTROL_SLOT_STATUS,Slot Control and Status Register. This register controls and provides information about PCI Express Slot specific parameters." hexmask.long.byte 0x18 25.--31. 1. "RSVDP_25,Reserved for future use." bitfld.long 0x18 24. "PCIE_CAP_DLL_STATE_CHANGED,Data Link Layer State Changed. This bit is set when the value reported in the Data Link Layer Link Active bit of the Link Status register is changed. In response to a Data Link Layer State Changed event software must read the.." "0,1" newline rbitfld.long 0x18 23. "PCIE_CAP_ELECTROMECH_INTERLOCK_STATUS,Electromechanical Interlock Status. If an Electromechanical Interlock is implemented this bit indicates the status of the Electromechanical Interlock. Defined encodings are: - 0b: Electromechanical Interlock.." "0,1" rbitfld.long 0x18 22. "PCIE_CAP_PRESENCE_DETECT_STATE,Presence Detect State. This bit indicates the presence of an adapter in the slot reflected by the logical 'OR' of the Physical Layer in-band presence detect mechanism and if present any out-of-band presence detect.." "0,1" newline rbitfld.long 0x18 21. "PCIE_CAP_MRL_SENSOR_STATE,MRL Sensor State. This bit reports the status of the MRL sensor if implemented. Defined encodings are: - 0b: MRL Closed - 1b: MRL Open" "0,1" bitfld.long 0x18 20. "PCIE_CAP_CMD_CPLD,Command Completed. If Command Completed notification is supported (if the No Command Completed Support bit in the Slot Capabilities register is 0b) this bit is set when a hot-plug command has completed and the Hot-Plug Controller is.." "0,1" newline bitfld.long 0x18 19. "PCIE_CAP_PRESENCE_DETECTED_CHANGED,Presence Detect Changed. This bit is set when the value reported in the Presence Detect State bit is changed." "0,1" bitfld.long 0x18 18. "PCIE_CAP_MRL_SENSOR_CHANGED,MRL Sensor Changed. If an MRL sensor is implemented this bit is set when a MRL Sensor state change is detected. If an MRL sensor is not implemented this bit must not be set." "0,1" newline bitfld.long 0x18 17. "PCIE_CAP_POWER_FAULT_DETECTED,Power Fault Detected. If a Power Controller that supports power fault detection is implemented this bit issSet when the Power Controller detects a power fault at this slot. Note: Depending on hardware capability it is.." "0,1" bitfld.long 0x18 16. "PCIE_CAP_ATTENTION_BUTTON_PRESSED,Attention Button Pressed. If an Attention Button is implemented this bit is set when the attention button is pressed. If an Attention Button is not supported this bit must not be set." "0,1" newline rbitfld.long 0x18 14.--15. "RSVDP_14,Reserved for future use." "0,1,2,3" bitfld.long 0x18 12. "PCIE_CAP_DLL_STATE_CHANGED_EN,Data Link Layer State Changed Enable. If the Data Link Layer Link Active Reporting capability is 1b this bit enables software notification when Data Link Layer Link Active bit is changed. If the Data Link Layer Link Active.." "0,1" newline bitfld.long 0x18 11. "PCIE_CAP_ELECTROMECH_INTERLOCK_CTRL,Electromechanical Interlock Control. If an Electromechanical Interlock is implemented a write of 1b to this bit causes the state of the interlock to toggle. A write of 0b to this bit has no effect. A read of this bit.." "0,1" bitfld.long 0x18 10. "PCIE_CAP_POWER_CONTROLLER_CTRL,Power Controller Control. If a Power Controller is implemented this bit when written sets the power state of the slot per the defined encodings. Reads of this bit must reflect the value from the latest write even if the.." "0,1" newline bitfld.long 0x18 8.--9. "PCIE_CAP_POWER_INDICATOR_CTRL,Power Indicator Control. If a Power Indicator is implemented writes to this field set the Power Indicator to the written state. Reads of this field must reflect the value from the latest write even if the corresponding.." "0,1,2,3" bitfld.long 0x18 6.--7. "PCIE_CAP_ATTENTION_INDICATOR_CTRL,Attention Indicator Control. If an Attention Indicator is implemented writes to this field set the Attention Indicator to the written state. Reads of this field must reflect the value from the latest write even if the.." "0,1,2,3" newline bitfld.long 0x18 5. "PCIE_CAP_HOT_PLUG_INT_EN,Hot-Plug Interrupt Enable. When set this bit enables generation of an interrupt on enabled hot-plug events. If the Hot Plug Capable bit in the Slot Capabilities register is clear this bit is permitted to be read-only with a.." "0,1" bitfld.long 0x18 4. "PCIE_CAP_CMD_CPL_INT_EN,Command Completed Interrupt Enable. If Command Completed notification is supported (if the No Command Completed Support bit in the Slot Capabilities register is 0b) when set this bit enables software notification when a hot-plug.." "0,1" newline bitfld.long 0x18 3. "PCIE_CAP_PRESENCE_DETECT_CHANGE_EN,Presence Detect Changed Enable. When set this bit enables software notification on a presence detect changed event (for more details see Section 6.7.3 of PCI Express Base Specification). If the Hot-Plug Capable bit in.." "0,1" bitfld.long 0x18 2. "PCIE_CAP_MRL_SENSOR_CHANGED_EN,MRL Sensor Changed Enable. When set this bit enables software notification on a MRL sensor changed event (for more details see Section 6.7.3 of PCI Express Base Specification). If the MRL Sensor Present bit in the Slot.." "0,1" newline bitfld.long 0x18 1. "PCIE_CAP_POWER_FAULT_DETECTED_EN,Power Fault Detected Enable. When set this bit enables software notification on a power fault event (for more details see Section 6.7.3 of PCI Express Base Specification). If a Power Controller that supports power fault.." "0,1" bitfld.long 0x18 0. "PCIE_CAP_ATTENTION_BUTTON_PRESSED_EN,Attention Button Pressed Enable. When set to 1b this bit enables software notification on an attention button pressed event (for more details see Section 6.7.3 of PCI Express Base Specification). If the Attention.." "0,1" line.long 0x1C "ROOT_CONTROL_ROOT_CAPABILITIES_REG,Root Control and Capabilities Register. This register controls PCI Express Root Complex specific parameters and identifies PCI Express Root Port specific capabilities." hexmask.long.word 0x1C 17.--31. 1. "RSVDP_17,Reserved for future use." bitfld.long 0x1C 16. "PCIE_CAP_CRS_SW_VISIBILITY,CRS Software Visibility Capable. For a description of this standard PCIe register field see the PCI Express Base Specification. CRS Software Visibility. When set this bit indicates that the Root Port is capable of returning.." "0,1" newline hexmask.long.word 0x1C 5.--15. 1. "RSVDP_5,Reserved for future use." bitfld.long 0x1C 4. "PCIE_CAP_CRS_SW_VISIBILITY_EN,CRS Software Visibility Enable. When set this bit enables the Root Port to return Configuration Request Retry Status (CRS) Completion Status to software (for more details see section 2.3.1 of PCI Express Base.." "0,1" newline bitfld.long 0x1C 3. "PCIE_CAP_PME_INT_EN,PME Interrupt Enable. When set this bit enables PME interrupt generation upon receipt of a PME Message as reflected in the PME Status bit (for more details see Table 7-29 of PCI Express Base Specification). A PME interrupt is also.." "0,1" bitfld.long 0x1C 2. "PCIE_CAP_SYS_ERR_ON_FATAL_ERR_EN,System Error on Fatal Error Enable. If set this bit indicates that a System Error should be generated if a Fatal error (ERR_FATAL) is reported by any of the devices in the Hierarchy Domain associated with this Root Port.." "0,1" newline bitfld.long 0x1C 1. "PCIE_CAP_SYS_ERR_ON_NON_FATAL_ERR_EN,System Error on Non-Fatal Error Enable. If set this bit indicates that a System Error should be generated if a Non-fatal error (ERR_NONFATAL) is reported by any of the devices in the Hierarchy Domain associated with.." "0,1" bitfld.long 0x1C 0. "PCIE_CAP_SYS_ERR_ON_CORR_ERR_EN,System Error on Correctable Error Enable. If set this bit indicates that a System Error should be generated if a correctable error (ERR_COR) is reported by any of the devices in the Hierarchy Domain associated with this.." "0,1" line.long 0x20 "ROOT_STATUS_REG,Root Status Register. The Root Status register provides information about PCI Express device specific parameters." hexmask.long.word 0x20 18.--31. 1. "RSVDP_18,Reserved for future use." rbitfld.long 0x20 17. "PCIE_CAP_PME_PENDING,PME Pending. This bit indicates that another PME is pending when the PME Status bit is s et. When the PME Status bit is cleared by software; the PME is delivered by hardware by setting the PME Status bit again and updating the PME.." "0,1" newline bitfld.long 0x20 16. "PCIE_CAP_PME_STATUS,PME Status. This bit indicates that PME was asserted by the PME Requester indicated in the PME Requester ID field. Subsequent PMEs are kept pending until the status register is cleared by software by writing a 1b." "0,1" hexmask.long.word 0x20 0.--15. 1. "PCIE_CAP_PME_REQ_ID,PME Requester ID. This field indicates the PCI Requester ID of the last PME Requester. This field is only valid when the PME Status bit is set." line.long 0x24 "DEVICE_CAPABILITIES2_REG,Device Capabilities 2 Register." bitfld.long 0x24 31. "PCIE_CAP_FRS_SUPPORTED,FRS Supported. When set indicates support for the optional Function Readiness Status (FRS) capability. Must be set for all Functions that support generation or reception capabilities of FRS Messages. Must not be set by Switch.." "0,1" hexmask.long.byte 0x24 24.--30. 1. "RSVDP_24,Reserved for future use." newline bitfld.long 0x24 22.--23. "PCIE_CAP2_CFG_MAX_END2END_TLP_PRFXS,Max End-End TLP Prefixes. Indicates the maximum number of End-End TLP Prefixes supported by this Function. For more details see Section 2.2.10.2 of PCI Express Base Specification. Values are: - 01b: 1 End-End TLP.." "0,1,2,3" bitfld.long 0x24 21. "PCIE_CAP2_CFG_END2END_TLP_PRFX_SUPPORT,End-End TLP Prefix Supported. Indicates whether End-End TLP Prefix support is offered by a Function. Values are: - 0b: No Support - 1b: Support is provided to receive TLPs containing End-End TLP Prefixes. All Ports.." "0,1" newline bitfld.long 0x24 20. "PCIE_CAP2_CFG_EXTND_FMT_SUPPORT,Extended Fmt Field Supported. If set the Function supports the 3-bit definition of the Fmt field. If clear the Function supports a 2-bit definition of the Fmt field. For more details see section 2.2 of PCI Express Base.." "0,1" rbitfld.long 0x24 17. "PCIE_CAP2_10_BIT_TAG_REQ_SUPPORT,10-Bit Tag Requester Supported. If this bit is set the Function supports 10-Bit Tag Requester capability; otherwise the Function does not. This bit must not be set if the 10-Bit Tag Completer Supported bit is clear." "0,1" newline rbitfld.long 0x24 16. "PCIE_CAP2_10_BIT_TAG_COMP_SUPPORT,10-Bit Tag Completer Supported. If this bit is set the Function supports 10-Bit Tag Completer capability; otherwise the Function does not. For more details see section 2.2.6.2. of PCI Express Base Specification." "0,1" rbitfld.long 0x24 13. "PCIE_CAP_TPH_CMPLT_SUPPORT_1,TPH Completer Supported Bit 1." "0,1" newline rbitfld.long 0x24 12. "PCIE_CAP_TPH_CMPLT_SUPPORT_0,TPH Completer Supported Bit 0. Value of this bit along with TPH Completer Supported Bit 1 indicates Completer support for TPH or Extended TPH. Applicable only to Root Ports and Endpoints. For all other Functions this field.." "0,1" bitfld.long 0x24 11. "PCIE_CAP_LTR_SUPP,LTR Mechanism Supported. A value of 1b indicates support for the optional Latency Tolerance Reporting (LTR) mechanism. Root Ports Switches and Endpoints are permitted to implement this capability. For a Multi-Function Device associated.." "0,1" newline rbitfld.long 0x24 10. "PCIE_CAP_NO_RO_EN_PR2PR_PAR,No RO-enabled PR-PR Passing. If this bit is set the routing element never carries out the passing permitted by Table 2-39 of PCI Express Base Specification entry A2b that is associated with the Relaxed Ordering Attribute.." "0,1" rbitfld.long 0x24 9. "PCIE_CAP_128_CAS_CPL_SUPP,128-bit CAS Completer Supported. Applicable to Functions with Memory Space BARs as well as all Root Ports; must be 0b otherwise. This bit must be set to 1b if the Function supports this optional capability. For more details see.." "0,1" newline rbitfld.long 0x24 8. "PCIE_CAP_64_ATOMIC_CPL_SUPP,64-bit AtomicOp Completer Supported. Applicable to Functions with Memory Space BARs as well as all Root Ports; must be 0b otherwise. Includes FetchAdd Swap and CAS AtomicOps. This bit must be set to 1b if the Function.." "0,1" rbitfld.long 0x24 7. "PCIE_CAP_32_ATOMIC_CPL_SUPP,32-bit AtomicOp Completer Supported. Applicable to Functions with Memory Space BARs as well as all Root Ports; must be 0b otherwise. Includes FetchAdd Swap and CAS AtomicOps. This bit must be set to 1b if the Function.." "0,1" newline rbitfld.long 0x24 6. "PCIE_CAP_ATOMIC_ROUTING_SUPP,AtomicOp Routing Supported. Applicable only to Switch Upstream Ports Switch Downstream Ports and Root Ports; must be 0b for other Function types. This bit must be set to 1b if the Port supports this optional capability. For.." "0,1" rbitfld.long 0x24 5. "PCIE_CAP_ARI_FORWARD_SUPPORT,ARI Forwarding Supported. Applicable only to Switch Downstream Ports and Root Ports; must be 0b for other Function types. This bit must be set to 1b if a Switch Downstream Port or Root Port supports this optional capability." "0,1" newline rbitfld.long 0x24 4. "PCIE_CAP_CPL_TIMEOUT_DISABLE_SUPPORT,Completion Timeout Disable Supported. A value of 1b indicates support for the Completion Timeout Disable mechanism. The Completion Timeout Disable mechanism is required for Endpoints that issue Requests on their own.." "0,1" hexmask.long.byte 0x24 0.--3. 1. "PCIE_CAP_CPL_TIMEOUT_RANGE,Completion Timeout Ranges Supported. This field indicates device Function support for the optional Completion Timeout programmability mechanism. This mechanism allows system software to modify the Completion Timeout value. This.." line.long 0x28 "DEVICE_CONTROL2_DEVICE_STATUS2_REG,Device Control 2 and Status 2 Register." hexmask.long.word 0x28 16.--31. 1. "RSVDP_16,Reserved for future use." bitfld.long 0x28 15. "PCIE_CTRL2_CFG_END2END_TLP_PFX_BLCK,End-End TLP Prefix Blocking. Controls whether the routing function is permitted to forward TLPs containing an End-End TLP Prefix. Values are: - 0b: Forwarding Enabled - Function is permitted to send TLPs with End-End.." "0,1" newline rbitfld.long 0x28 11. "RSVDP_11,Reserved for future use." "0,1" bitfld.long 0x28 10. "PCIE_CAP_LTR_EN,LTR Mechanism Enable. When set to 1b this bit enables Upstream Ports to send LTR messages and Downstream Ports to process LTR Messages. For a Multi-Function Device associated with an Upstream Port of a device that implements LTR the bit.." "0,1" newline rbitfld.long 0x28 5. "PCIE_CAP_ARI_FORWARD_SUPPORT_CS,ARI Forwarding Enable. When set the Downstream Port disables its traditional Device Number field being 0 enforcement when turning a Type 1 Configuration Request into a Type 0 Configuration Request permitting access to.." "0,1" bitfld.long 0x28 4. "PCIE_CAP_CPL_TIMEOUT_DISABLE,Completion Timeout Disable. When set this bit disables the Completion Timeout mechanism. This bit is required for all Functions that support the Completion Timeout Disable Capability. Functions that do not support this.." "0,1" newline hexmask.long.byte 0x28 0.--3. 1. "PCIE_CAP_CPL_TIMEOUT_VALUE,Completion Timeout Value. In device Functions that support Completion Timeout programmability this field allows system software to modify the Completion Timeout value. This field is applicable to Root Ports Endpoints that.." line.long 0x2C "LINK_CAPABILITIES2_REG,Link Capabilities 2 Register." bitfld.long 0x2C 31. "DRS_SUPPORTED,DRS Supported. When set indicates support for the optional Device Readiness Status (DRS) capability. Must be Set in Downstream Ports that support DRS. Must be Set in Downstream Ports that support FRS. For Upstream Ports that support DRS.." "0,1" hexmask.long.byte 0x2C 25.--30. 1. "RSVDP_25,Reserved for future use." newline hexmask.long.word 0x2C 9.--22. 1. "RSVDP_9,Reserved for future use." rbitfld.long 0x2C 8. "PCIE_CAP_CROSS_LINK_SUPPORT,Crosslink Supported. When set to 1b this bit indicates that the associated Port supports crosslinks (for more details see section 4.2.6.3.1 of PCI Express Base Specification). When set to 0b on a Port that supports Link.." "0,1" newline hexmask.long.byte 0x2C 1.--7. 1. "PCIE_CAP_SUPPORT_LINK_SPEED_VECTOR,Supported Link Speeds Vector. This field indicates the supported Link speed(s) of the associated Port. For each bit a value of 1b indicates that the corresponding Link speed is supported; otherwise the Link speed is.." rbitfld.long 0x2C 0. "RSVDP_0,Reserved for future use." "0,1" line.long 0x30 "LINK_CONTROL2_LINK_STATUS2_REG,Link Control 2 and Status 2 Register." bitfld.long 0x30 31. "DRS_MESSAGE_RECEIVED,DRS Message Received. This bit must be set whenever the Port receives a DRS Message. This bit must be cleared in DL_Down. This bit must be implemented in any Downstream Port where the DRS Supported bit is Set in the Link Capabilities.." "0,1" rbitfld.long 0x30 28.--30. "DOWNSTREAM_COMPO_PRESENCE,Downstream Component Presence. This field indicates the presence and DRS status for the Downstream Component if any connected to the Link; defined values are: - 000b: Link Down - Presence Not Determined - 001b: Link Down -.." "0,1,2,3,4,5,6,7" newline rbitfld.long 0x30 26.--27. "RSVDP_26,Reserved for future use." "0,1,2,3" bitfld.long 0x30 21. "PCIE_CAP_LINK_EQ_REQ,Link Equalization Request 8.0 GT/s. This bit is set by hardware to request the 8.0 GT/s Link equalization process to be performed on the Link. For more details see sections 4.2.3 and 4.2.6.4.2 of PCI Express Base Specification. For.." "0,1" newline rbitfld.long 0x30 20. "PCIE_CAP_EQ_CPL_P3,EEqualization 8.0 GT/s Phase 3 Successful. When set to 1b this bit indicates that Phase 3 of the 8.0 GT/s Transmitter Equalization procedure has successfully completed. Details of the Transmitter Equalization process and when this bit.." "0,1" rbitfld.long 0x30 19. "PCIE_CAP_EQ_CPL_P2,Equalization 8.0 GT/s Phase 2 Successful. When set to 1b this bit indicates that Phase 2 of the 8.0 GT/s Transmitter Equalization procedure has successfully completed. Details of the Transmitter Equalization process and when this bit.." "0,1" newline rbitfld.long 0x30 18. "PCIE_CAP_EQ_CPL_P1,Equalization 8.0 GT/s Phase 1 Successful. When set to 1b this bit indicates that Phase 1 of the 8.0 GT/s Transmitter Equalization procedure has successfully completed. Details of the Transmitter Equalization process and when this bit.." "0,1" rbitfld.long 0x30 17. "PCIE_CAP_EQ_CPL,Equalization 8.0 GT/s Complete. When set to 1b this bit indicates that the Transmitter Equalization procedure at the 8.0 GT/s data rate has completed. Details of the Transmitter Equalization process and when this bit needs to be set to.." "0,1" newline rbitfld.long 0x30 16. "PCIE_CAP_CURR_DEEMPHASIS,Current De-emphasis Level. When the Link is operating at 5.0 GT/s speed this bit reflects the level of de-emphasis. Encodings: - 1b: -3.5 dB - 0b: -6 dB The value in this bit is undefined when the Link is not operating at 5.0.." "0,1" hexmask.long.byte 0x30 12.--15. 1. "PCIE_CAP_COMPLIANCE_PRESET,Compliance Preset/De-emphasis. For 8.0 GT/s and higher Data Rate: This field sets the Transmitter Preset in Polling.Compliance state if the entry occurred due to the Enter Compliance bit being 1b. The encodings are defined in.." newline bitfld.long 0x30 11. "PCIE_CAP_COMPLIANCE_SOS,Compliance SOS. When set to 1b the LTSSM is required to send SKP Ordered Sets between sequences when sending the Compliance Pattern or Modified Compliance Pattern. For a Multi-Function Device associated with an Upstream Port the.." "0,1" bitfld.long 0x30 10. "PCIE_CAP_ENTER_MODIFIED_COMPLIANCE,Enter Modified Compliance. When this bit is set to 1b the device transmits Modified Compliance Pattern if the LTSSM enters Polling.Compliance substate. Components that support only the 2.5 GT/s speed are permitted to.." "0,1" newline bitfld.long 0x30 7.--9. "PCIE_CAP_TX_MARGIN,Transmit Margin - This field controls the value of the non-deemphasized voltage level at the Transmitter pins. This field is reset to 000b on entry to the LTSSM Polling.Configuration substate (see Chapter 4 of PCI Express Base.." "0,1,2,3,4,5,6,7" bitfld.long 0x30 6. "PCIE_CAP_SEL_DEEMPHASIS,Selectable De-emphasis. When the Link is operating at 5.0 GT/s speed this bit is used to control the transmit de-emphasis of the link in specific situations. For more details see section 4.2.6 of PCI Express Base Specification." "0,1" newline bitfld.long 0x30 5. "PCIE_CAP_HW_AUTO_SPEED_DISABLE,Hardware Autonomous Speed Disable. When set this bit disables hardware from changing the Link speed for device-specific reasons other than attempting to correct unreliable Link operation by reducing Link speed. Initial.." "0,1" bitfld.long 0x30 4. "PCIE_CAP_ENTER_COMPLIANCE,Enter Compliance. Software is permitted to force a Link to enter Compliance mode (at the speed indicated in the Target Link Speed field and the de-emphasis/preset level indicated by the Compliance Preset/De-emphasis field) by.." "0,1" newline hexmask.long.byte 0x30 0.--3. 1. "PCIE_CAP_TARGET_LINK_SPEED,Target Link Speed. For Downstream Ports this field sets an upper limit on Link operational speed by restricting the values advertised by the Upstream component in its training sequences. The encoded value specifies a bit.." tree.end tree "PF0_AER_CAP (PF Advanced Error Reporting Capability Structure)" group.long (0x0+0x100)++0x1B line.long 0x0 "AER_EXT_CAP_HDR_OFF,Advanced Error Reporting Extended Capability Header. For a description of this standard PCIe register. see the PCI Express Specification." hexmask.long.word 0x0 20.--31. 1. "NEXT_OFFSET,Next Capability Offset. For a description of this standard PCIe register field see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky).." hexmask.long.byte 0x0 16.--19. 1. "CAP_VERSION,Capability Version. For a description of this standard PCIe register field see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else.." hexmask.long.word 0x0 0.--15. 1. "CAP_ID,AER Extended Capability ID. For a description of this standard PCIe register field see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else.." line.long 0x4 "UNCORR_ERR_STATUS_OFF,Uncorrectable Error Status Register. For a description of this standard PCIe register. see the PCI Express Specification." hexmask.long.byte 0x4 27.--31. 1. "RSVDP_27,Reserved for future use." bitfld.long 0x4 25. "TLP_PRFX_BLOCKED_ERR_STATUS,TLP Prefix Blocked Error Status. For a description of this standard PCIe register field see the PCI Express Specification. Note: Not supported." "0,1" rbitfld.long 0x4 23. "RSVDP_23,Reserved for future use." "0,1" newline bitfld.long 0x4 22. "INTERNAL_ERR_STATUS,Uncorrectable Internal Error Status. For a description of this standard PCIe register field see the PCI Express Specification. The controller sets this bit when your application asserts app_err_bus[9]. It does not set this bit when.." "0,1" bitfld.long 0x4 20. "UNSUPPORTED_REQ_ERR_STATUS,Unsupported Request Error Status. For a description of this standard PCIe register field see the PCI Express Specification." "0,1" bitfld.long 0x4 19. "ECRC_ERR_STATUS,ECRC Error Status. For a description of this standard PCIe register field see the PCI Express Specification. Note:If CX_ECRC_ENABLE=0 the register field always reads 0." "0,1" newline bitfld.long 0x4 18. "MALF_TLP_ERR_STATUS,Malformed TLP Status. For a description of this standard PCIe register field see the PCI Express Specification." "0,1" bitfld.long 0x4 17. "REC_OVERFLOW_ERR_STATUS,Receiver Overflow Status. For a description of this standard PCIe register field see the PCI Express Specification." "0,1" bitfld.long 0x4 16. "UNEXP_CMPLT_ERR_STATUS,Unexpected Completion Status. For a description of this standard PCIe register field see the PCI Express Specification." "0,1" newline bitfld.long 0x4 15. "CMPLT_ABORT_ERR_STATUS,Completer Abort Status. For a description of this standard PCIe register field see the PCI Express Specification." "0,1" bitfld.long 0x4 14. "CMPLT_TIMEOUT_ERR_STATUS,Completion Timeout Status. For a description of this standard PCIe register field see the PCI Express Specification." "0,1" bitfld.long 0x4 13. "FC_PROTOCOL_ERR_STATUS,Flow Control Protocol Error Status. For a description of this standard PCIe register field see the PCI Express Specification." "0,1" newline bitfld.long 0x4 12. "POIS_TLP_ERR_STATUS,Poisoned TLP Status. For a description of this standard PCIe register field see the PCI Express Specification." "0,1" hexmask.long.byte 0x4 6.--11. 1. "RSVDP_6,Reserved for future use." bitfld.long 0x4 5. "SURPRISE_DOWN_ERR_STATUS,Surprise Down Error Status (Optional). For a description of this standard PCIe register field see the PCI Express Specification." "0,1" newline bitfld.long 0x4 4. "DL_PROTOCOL_ERR_STATUS,Data Link Protocol Error Status. For a description of this standard PCIe register field see the PCI Express Specification." "0,1" hexmask.long.byte 0x4 0.--3. 1. "RSVDP_0,Reserved for future use." line.long 0x8 "UNCORR_ERR_MASK_OFF,Uncorrectable Error Mask Register. For a description of this standard PCIe register. see the PCI Express Specification." hexmask.long.byte 0x8 27.--31. 1. "RSVDP_27,Reserved for future use." bitfld.long 0x8 25. "TLP_PRFX_BLOCKED_ERR_MASK,TLP Prefix Blocked Error Mask. For a description of this standard PCIe register field see the PCI Express Specification. Note: Not supported. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi:.." "0,1" rbitfld.long 0x8 23. "RSVDP_23,Reserved for future use." "0,1" newline bitfld.long 0x8 22. "INTERNAL_ERR_MASK,Uncorrectable Internal Error Mask (Optional). For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." "0,1" rbitfld.long 0x8 21. "ACS_VIOLATION_MASK,ACS Violation Mask. Setting the ACS Violation Mask bit disables error logging and signaling for ACS Violation errors. The bit is Read-Only Zero for upstream ports when ACS P2P Egress Control Enable is not set. For a description of.." "0,1" bitfld.long 0x8 20. "UNSUPPORTED_REQ_ERR_MASK,Unsupported Request Error Mask. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." "0,1" newline bitfld.long 0x8 19. "ECRC_ERR_MASK,ECRC Error Mask (Optional). For a description of this standard PCIe register field see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W (sticky) Note: This register.." "0,1" bitfld.long 0x8 18. "MALF_TLP_ERR_MASK,Malformed TLP Mask. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." "0,1" bitfld.long 0x8 17. "REC_OVERFLOW_ERR_MASK,Receiver Overflow Mask (Optional). For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." "0,1" newline bitfld.long 0x8 16. "UNEXP_CMPLT_ERR_MASK,Unexpected Completion Mask. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." "0,1" bitfld.long 0x8 15. "CMPLT_ABORT_ERR_MASK,Completer Abort Error Mask (Optional). For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." "0,1" bitfld.long 0x8 14. "CMPLT_TIMEOUT_ERR_MASK,Completion Timeout Error Mask. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." "0,1" newline bitfld.long 0x8 13. "FC_PROTOCOL_ERR_MASK,Flow Control Protocol Error Mask. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." "0,1" bitfld.long 0x8 12. "POIS_TLP_ERR_MASK,Poisoned TLP Error Mask. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." "0,1" hexmask.long.byte 0x8 6.--11. 1. "RSVDP_6,Reserved for future use." newline rbitfld.long 0x8 5. "SURPRISE_DOWN_ERR_MASK,Surprise Down Error Mask. For a description of this standard PCIe register field see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi:.." "0,1" bitfld.long 0x8 4. "DL_PROTOCOL_ERR_MASK,Data Link Protocol Error Mask. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." "0,1" hexmask.long.byte 0x8 0.--3. 1. "RSVDP_0,Reserved for future use." line.long 0xC "UNCORR_ERR_SEV_OFF,Uncorrectable Error Severity Register. For a description of this standard PCIe register. see the PCI Express Specification." hexmask.long.byte 0xC 27.--31. 1. "RSVDP_27,Reserved for future use." bitfld.long 0xC 25. "TLP_PRFX_BLOCKED_ERR_SEVERITY,TLP Prefix Blocked Error Severity (Optional). For a description of this standard PCIe register field see the PCI Express Specification. Note: Not supported. Note: The access attributes of this field are as follows: - Wire:.." "0,1" rbitfld.long 0xC 24. "ATOMIC_EGRESS_BLOCKED_ERR_SEVERITY,AtomicOp Egress Blocked Severity (Optional). For a description of this standard PCIe register field see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi:.." "0,1" newline rbitfld.long 0xC 23. "RSVDP_23,Reserved for future use." "0,1" bitfld.long 0xC 22. "INTERNAL_ERR_SEVERITY,Uncorrectable Internal Error Severity (Optional). For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." "0,1" bitfld.long 0xC 20. "UNSUPPORTED_REQ_ERR_SEVERITY,Unsupported Request Error Severity. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." "0,1" newline bitfld.long 0xC 19. "ECRC_ERR_SEVERITY,ECRC Error Severity (Optional). For a description of this standard PCIe register field see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W (sticky) Note: This.." "0,1" bitfld.long 0xC 18. "MALF_TLP_ERR_SEVERITY,Malformed TLP Severity. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." "0,1" bitfld.long 0xC 17. "REC_OVERFLOW_ERR_SEVERITY,Receiver Overflow Error Severity (Optional). For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." "0,1" newline bitfld.long 0xC 16. "UNEXP_CMPLT_ERR_SEVERITY,Unexpected Completion Error Severity. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." "0,1" bitfld.long 0xC 15. "CMPLT_ABORT_ERR_SEVERITY,Completer Abort Error Severity (Optional). For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." "0,1" bitfld.long 0xC 14. "CMPLT_TIMEOUT_ERR_SEVERITY,Completion Timeout Error Severity. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." "0,1" newline bitfld.long 0xC 13. "FC_PROTOCOL_ERR_SEVERITY,Flow Control Protocol Error Severity (Optional). For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." "0,1" bitfld.long 0xC 12. "POIS_TLP_ERR_SEVERITY,Poisoned TLP Severity. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." "0,1" hexmask.long.byte 0xC 6.--11. 1. "RSVDP_6,Reserved for future use." newline rbitfld.long 0xC 5. "SURPRISE_DOWN_ERR_SVRITY,Surprise Down Error Severity (Optional). For a description of this standard PCIe register field see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi:.." "0,1" bitfld.long 0xC 4. "DL_PROTOCOL_ERR_SEVERITY,Data Link Protocol Error Severity. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." "0,1" hexmask.long.byte 0xC 0.--3. 1. "RSVDP_0,Reserved for future use." line.long 0x10 "CORR_ERR_STATUS_OFF,Correctable Error Status Register. For a description of this standard PCIe register. see the PCI Express Specification." hexmask.long.word 0x10 16.--31. 1. "RSVDP_16,Reserved for future use." bitfld.long 0x10 15. "HEADER_LOG_OVERFLOW_STATUS,Header Log Overflow Error Status (Optional). For a description of this standard PCIe register field see the PCI Express Specification." "0,1" bitfld.long 0x10 14. "CORRECTED_INT_ERR_STATUS,Corrected Internal Error Status (Optional). For a description of this standard PCIe register field see the PCI Express Specification." "0,1" newline bitfld.long 0x10 13. "ADVISORY_NON_FATAL_ERR_STATUS,Advisory Non-Fatal Error Status. For a description of this standard PCIe register field see the PCI Express Specification." "0,1" bitfld.long 0x10 12. "RPL_TIMER_TIMEOUT_STATUS,Replay Timer Timeout Status. For a description of this standard PCIe register field see the PCI Express Specification." "0,1" rbitfld.long 0x10 9.--11. "RSVDP_9,Reserved for future use." "0,1,2,3,4,5,6,7" newline bitfld.long 0x10 8. "REPLAY_NO_ROLEOVER_STATUS,REPLAY_NUM Rollover Status. For a description of this standard PCIe register field see the PCI Express Specification." "0,1" bitfld.long 0x10 7. "BAD_DLLP_STATUS,Bad DLLP Status. For a description of this standard PCIe register field see the PCI Express Specification." "0,1" bitfld.long 0x10 6. "BAD_TLP_STATUS,Bad TLP Status. For a description of this standard PCIe register field see the PCI Express Specification." "0,1" newline hexmask.long.byte 0x10 1.--5. 1. "RSVDP_1,Reserved for future use." bitfld.long 0x10 0. "RX_ERR_STATUS,Receiver Error Status (Optional). For a description of this standard PCIe register field see the PCI Express Specification." "0,1" line.long 0x14 "CORR_ERR_MASK_OFF,Correctable Error Mask Register. For a description of this standard PCIe register. see the PCI Express Specification." hexmask.long.word 0x14 16.--31. 1. "RSVDP_16,Reserved for future use." bitfld.long 0x14 15. "HEADER_LOG_OVERFLOW_MASK,Header Log Overflow Error Mask (Optional). For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." "0,1" bitfld.long 0x14 14. "CORRECTED_INT_ERR_MASK,Corrected Internal Error Mask (Optional). For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." "0,1" newline bitfld.long 0x14 13. "ADVISORY_NON_FATAL_ERR_MASK,Advisory Non-Fatal Error Mask. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." "0,1" bitfld.long 0x14 12. "RPL_TIMER_TIMEOUT_MASK,Replay Timer Timeout Mask. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." "0,1" rbitfld.long 0x14 9.--11. "RSVDP_9,Reserved for future use." "0,1,2,3,4,5,6,7" newline bitfld.long 0x14 8. "REPLAY_NO_ROLEOVER_MASK,REPLAY_NUM Rollover Mask. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." "0,1" bitfld.long 0x14 7. "BAD_DLLP_MASK,Bad DLLP Mask. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." "0,1" bitfld.long 0x14 6. "BAD_TLP_MASK,Bad TLP Mask. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." "0,1" newline hexmask.long.byte 0x14 1.--5. 1. "RSVDP_1,Reserved for future use." bitfld.long 0x14 0. "RX_ERR_MASK,Receiver Error Mask (Optional). For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." "0,1" line.long 0x18 "ADV_ERR_CAP_CTRL_OFF,Advanced Error Capabilities and Control Register. For a description of this standard PCIe register. see the PCI Express Specification." hexmask.long.tbyte 0x18 13.--31. 1. "RSVDP_13,Reserved for future use." rbitfld.long 0x18 12. "CTO_PRFX_HDR_LOG_CAP,TLP Prefix Log Present. For a description of this standard PCIe register field see the PCI Express Specification." "0,1" rbitfld.long 0x18 11. "TLP_PRFX_LOG_PRESENT,Completion Timeout Prefix/Header Log Capable. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." "0,1" newline rbitfld.long 0x18 10. "MULTIPLE_HEADER_EN,Multiple Header Recording Enable. For a description of this standard PCIe register field see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R (sticky) Note: This.." "0,1" rbitfld.long 0x18 9. "MULTIPLE_HEADER_CAP,Multiple Header Recording Capable. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." "0,1" bitfld.long 0x18 8. "ECRC_CHECK_EN,ECRC Check Enable. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." "0,1" newline rbitfld.long 0x18 7. "ECRC_CHECK_CAP,ECRC Check Capable. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." "0,1" bitfld.long 0x18 6. "ECRC_GEN_EN,ECRC Generation Enable. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." "0,1" rbitfld.long 0x18 5. "ECRC_GEN_CAP,ECRC Generation Capable. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." "0,1" newline hexmask.long.byte 0x18 0.--4. 1. "FIRST_ERR_POINTER,First Error Pointer. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." rgroup.long (0x1C+0x100)++0xF line.long 0x0 "HDR_LOG_0_OFF,Header Log Register 0. For a description of this standard PCIe register. see the PCI Express Specification." hexmask.long.byte 0x0 24.--31. 1. "FIRST_DWORD_FOURTH_BYTE,Byte 3 of Header log register of First 32 bit Data Word. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." hexmask.long.byte 0x0 16.--23. 1. "FIRST_DWORD_THIRD_BYTE,Byte 2 of Header log register of First 32 bit Data Word. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." hexmask.long.byte 0x0 8.--15. 1. "FIRST_DWORD_SECOND_BYTE,Byte 1 of Header log register of First 32 bit Data Word. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." newline hexmask.long.byte 0x0 0.--7. 1. "FIRST_DWORD_FIRST_BYTE,Byte 0 of Header log register of First 32 bit Data Word. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." line.long 0x4 "HDR_LOG_1_OFF,Header Log Register 1. For a description of this standard PCIe register. see the PCI Express Specification." hexmask.long.byte 0x4 24.--31. 1. "SECOND_DWORD_FOURTH_BYTE,Byte 3 of Header log register of Second 32 bit Data Word. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." hexmask.long.byte 0x4 16.--23. 1. "SECOND_DWORD_THIRD_BYTE,Byte 2 of Header log register of Second 32 bit Data Word. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." hexmask.long.byte 0x4 8.--15. 1. "SECOND_DWORD_SECOND_BYTE,Byte 1 of Header log register of Second 32 bit Data Word. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." newline hexmask.long.byte 0x4 0.--7. 1. "SECOND_DWORD_FIRST_BYTE,Byte 0 of Header log register of Second 32 bit Data Word. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." line.long 0x8 "HDR_LOG_2_OFF,Header Log Register 2. For a description of this standard PCIe register. see the PCI Express Specification." hexmask.long.byte 0x8 24.--31. 1. "THIRD_DWORD_FOURTH_BYTE,Byte 3 of Header log register of Third 32 bit Data Word. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." hexmask.long.byte 0x8 16.--23. 1. "THIRD_DWORD_THIRD_BYTE,Byte 2 of Header log register of Third 32 bit Data Word. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." hexmask.long.byte 0x8 8.--15. 1. "THIRD_DWORD_SECOND_BYTE,Byte 1 of Header log register of Third 32 bit Data Word. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." newline hexmask.long.byte 0x8 0.--7. 1. "THIRD_DWORD_FIRST_BYTE,Byte 0 of Header log register of Third 32 bit Data Word. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." line.long 0xC "HDR_LOG_3_OFF,Header Log Register 3. For a description of this standard PCIe register. see the PCI Express Specification." hexmask.long.byte 0xC 24.--31. 1. "FOURTH_DWORD_FOURTH_BYTE,Byte 3 of Header log register of Fourth 32 bit Data Word. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." hexmask.long.byte 0xC 16.--23. 1. "FOURTH_DWORD_THIRD_BYTE,Byte 2 of Header log register of Fourth 32 bit Data Word. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." hexmask.long.byte 0xC 8.--15. 1. "FOURTH_DWORD_SECOND_BYTE,Byte 1 of Header log register of Fourth 32 bit Data Word. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." newline hexmask.long.byte 0xC 0.--7. 1. "FOURTH_DWORD_FIRST_BYTE,Byte 0 of Header log register of Fourth 32 bit Data Word. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." group.long (0x2C+0x100)++0x7 line.long 0x0 "ROOT_ERR_CMD_OFF,Root Error Command Register. For a description of this standard PCIe register. see the PCI Express Specification." hexmask.long 0x0 3.--31. 1. "RSVDP_3,Reserved for future use." bitfld.long 0x0 2. "FATAL_ERR_REPORTING_EN,Fatal Error Reporting Enable. For a description of this standard PCIe register field see the PCI Express Specification." "0,1" bitfld.long 0x0 1. "NON_FATAL_ERR_REPORTING_EN,Non-Fatal Error Reporting Enable. For a description of this standard PCIe register field see the PCI Express Specification." "0,1" newline bitfld.long 0x0 0. "CORR_ERR_REPORTING_EN,Correctable Error Reporting Enable. For a description of this standard PCIe register field see the PCI Express Specification." "0,1" line.long 0x4 "ROOT_ERR_STATUS_OFF,Root Error Status Register. For a description of this standard PCIe register. see the PCI Express Specification." hexmask.long.byte 0x4 27.--31. 1. "ADV_ERR_INT_MSG_NUM,Advanced Error Interrupt Message Number. For a description of this standard PCIe register field see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN.." hexmask.long.tbyte 0x4 7.--26. 1. "RSVDP_7,Reserved for future use." bitfld.long 0x4 6. "FATAL_ERR_MSG_RX,One or more Fatal Error Messages Received. For a description of this standard PCIe register field see the PCI Express Specification." "0,1" newline bitfld.long 0x4 5. "NON_FATAL_ERR_MSG_RX,One or more Non-Fatal Error Messages Received. For a description of this standard PCIe register field see the PCI Express Specification." "0,1" bitfld.long 0x4 4. "FIRST_UNCORR_FATAL,First Uncorrectable Error is Fatal. For a description of this standard PCIe register field see the PCI Express Specification." "0,1" bitfld.long 0x4 3. "MUL_ERR_FATAL_NON_FATAL_RX,Multiple Fatal or Non-Fatal Errors Received. For a description of this standard PCIe register field see the PCI Express Specification." "0,1" newline bitfld.long 0x4 2. "ERR_FATAL_NON_FATAL_RX,Fatal or Non-Fatal Error Received. For a description of this standard PCIe register field see the PCI Express Specification." "0,1" bitfld.long 0x4 1. "MUL_ERR_COR_RX,Multiple Correctable Errors Received. For a description of this standard PCIe register field see the PCI Express Specification." "0,1" bitfld.long 0x4 0. "ERR_COR_RX,Correctable Error Received. For a description of this standard PCIe register field see the PCI Express Specification." "0,1" rgroup.long (0x34+0x100)++0x13 line.long 0x0 "ERR_SRC_ID_OFF,Error Source Identification Register. For a description of this standard PCIe register. see the PCI Express Specification." hexmask.long.word 0x0 16.--31. 1. "ERR_FATAL_NON_FATAL_SOURCE_ID,Source of Fatal/Non-Fatal Error. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." hexmask.long.word 0x0 0.--15. 1. "ERR_COR_SOURCE_ID,Source of Correctable Error. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." line.long 0x4 "TLP_PREFIX_LOG_1_OFF,TLP Prefix Log Register 1. For a description of this standard PCIe register. see the PCI Express Specification." hexmask.long.byte 0x4 24.--31. 1. "CFG_TLP_PFX_LOG_1_FOURTH_BYTE,Byte 3 of Error TLP Prefix Log 1. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." hexmask.long.byte 0x4 16.--23. 1. "CFG_TLP_PFX_LOG_1_THIRD_BYTE,Byte 2 of Error TLP Prefix Log 1. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." hexmask.long.byte 0x4 8.--15. 1. "CFG_TLP_PFX_LOG_1_SECOND_BYTE,Byte 1 of Error TLP Prefix Log 1. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." newline hexmask.long.byte 0x4 0.--7. 1. "CFG_TLP_PFX_LOG_1_FIRST_BYTE,Byte 0 of Error TLP Prefix Log 1. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." line.long 0x8 "TLP_PREFIX_LOG_2_OFF,TLP Prefix Log Register 2. For a description of this standard PCIe register. see the PCI Express Specification." hexmask.long.byte 0x8 24.--31. 1. "CFG_TLP_PFX_LOG_2_FOURTH_BYTE,Byte 3 Error TLP Prefix Log 2. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." hexmask.long.byte 0x8 16.--23. 1. "CFG_TLP_PFX_LOG_2_THIRD_BYTE,Byte 2 Error TLP Prefix Log 2. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." hexmask.long.byte 0x8 8.--15. 1. "CFG_TLP_PFX_LOG_2_SECOND_BYTE,Byte 1 Error TLP Prefix Log 2. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." newline hexmask.long.byte 0x8 0.--7. 1. "CFG_TLP_PFX_LOG_2_FIRST_BYTE,Byte 0 Error TLP Prefix Log 2. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." line.long 0xC "TLP_PREFIX_LOG_3_OFF,TLP Prefix Log Register 3. For a description of this standard PCIe register. see the PCI Express Specification." hexmask.long.byte 0xC 24.--31. 1. "CFG_TLP_PFX_LOG_3_FOURTH_BYTE,Byte 3 Error TLP Prefix Log 3. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." hexmask.long.byte 0xC 16.--23. 1. "CFG_TLP_PFX_LOG_3_THIRD_BYTE,Byte 2 Error TLP Prefix Log 3. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." hexmask.long.byte 0xC 8.--15. 1. "CFG_TLP_PFX_LOG_3_SECOND_BYTE,Byte 1 Error TLP Prefix Log 3. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." newline hexmask.long.byte 0xC 0.--7. 1. "CFG_TLP_PFX_LOG_3_FIRST_BYTE,Byte 0 Error TLP Prefix Log 3. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." line.long 0x10 "TLP_PREFIX_LOG_4_OFF,TLP Prefix Log Register 4. For a description of this standard PCIe register. see the PCI Express Specification." hexmask.long.byte 0x10 24.--31. 1. "CFG_TLP_PFX_LOG_4_FOURTH_BYTE,Byte 3 Error TLP Prefix Log 4. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." hexmask.long.byte 0x10 16.--23. 1. "CFG_TLP_PFX_LOG_4_THIRD_BYTE,Byte 2 Error TLP Prefix Log 4. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." hexmask.long.byte 0x10 8.--15. 1. "CFG_TLP_PFX_LOG_4_SECOND_BYTE,Byte 1 Error TLP Prefix Log 4. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." newline hexmask.long.byte 0x10 0.--7. 1. "CFG_TLP_PFX_LOG_4_FIRST_BYTE,Byte 0 Error TLP Prefix Log 4. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." tree.end tree "PF0_MSI_CAP (PF MSI Capability Structure)" group.long (0x0+0x50)++0x13 line.long 0x0 "PCI_MSI_CAP_ID_NEXT_CTRL_REG,MSI Capability Header and Message Control Register." hexmask.long.byte 0x0 27.--31. 1. "RSVDP_27,Reserved for future use." bitfld.long 0x0 26. "PCI_MSI_EXT_DATA_EN,Extended Message Data Enable. - If set the function is enabled to provide Extended Message Data. - If clear the function is not enabled to provide Extended Message Data. Note: The access attributes of this field are as follows: -.." "0,1" bitfld.long 0x0 25. "PCI_MSI_EXT_DATA_CAP,Extended Message Data Capable. - If set the function is capable of providing Extended Message Data. - If clear the function does not support providing Extended Message Data. Note: The access attributes of this field are as follows:.." "0,1" newline rbitfld.long 0x0 24. "PCI_PVM_SUPPORT,Per-Vector Masking Capable. - If set the function supports MSI Per-Vector Masking. - If clear the function does not support MSI Per-Vector Masking. This bit must be set if the function is a PF or VF within an SR-IOV Device." "0,1" bitfld.long 0x0 23. "PCI_MSI_64_BIT_ADDR_CAP,64 bit address capable. - If set the function is capable of sending a 64-bit message address. - If clear the function is not capable of sending a 64-bit message address. This bit must be set if the function is a PCI Express.." "0,1" bitfld.long 0x0 20.--22. "PCI_MSI_MULTIPLE_MSG_EN,Multiple Message Enable. Software writes to this field to indicate the number of allocated vectors (equal to or less than the number of requested vectors). The number of allocated vectors is aligned to a power of two. If a.." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 17.--19. "PCI_MSI_MULTIPLE_MSG_CAP,Multiple Message Capable. System software reads this field to determine the number of requested vectors. The number of requested vectors must be aligned to a power of two (if a function requires three vectors it requests four by.." "0,1,2,3,4,5,6,7" bitfld.long 0x0 16. "PCI_MSI_ENABLE,MSI Enable. - If set and the MSI-X Enable bit in the MSI-X Message Control register is clear the function is permitted to use MSI to request service and is prohibited from using INTx interrupts. System configuration software sets this bit.." "0,1" hexmask.long.byte 0x0 8.--15. 1. "PCI_MSI_CAP_NEXT_OFFSET,Next Capability Pointer. This field contains the offset to the next PCI Capability structure or 00h if no other items exist in the linked list of Capabilities. Note: The access attributes of this field are as follows: - Wire: No.." newline hexmask.long.byte 0x0 0.--7. 1. "PCI_MSI_CAP_ID,Capability ID. Indicates the MSI Capability structure. This field returns a Capability ID of 05h indicating that this is an MSI Capability structure." line.long 0x4 "MSI_CAP_OFF_04H_REG,Message Address Register for MSI (Offset 04h)." hexmask.long 0x4 2.--31. 1. "PCI_MSI_CAP_OFF_04H,Message Address - System-specified message address. If the Message Enable bit (bit 16 of the PCI_MSI_CAP_ID_NEXT_CTRL_REG register) is set the contents of this field specify the DWORD-aligned address (Address[31:02]) for the MSI.." rbitfld.long 0x4 0.--1. "RSVDP_0,Reserved for future use." "0,1,2,3" line.long 0x8 "MSI_CAP_OFF_08H_REG,For a function that supports a 32-bit message address. - bits[31:16] of this register represent the Extended Message Data. and - bits[15:0] of this register represent the Message Data For a function that supports a 64-bit message.." hexmask.long.word 0x8 16.--31. 1. "PCI_MSI_CAP_OFF_0AH,For a function that supports a 32-bit message address this field contains Extended Message Data (System-specified message data). For the MSI Capability structures without per-vector masking it must be implemented if the Extended.." hexmask.long.word 0x8 0.--15. 1. "PCI_MSI_CAP_OFF_08H,For a function that supports a 32-bit message address this field contains Message Data (System-specified message data). If the Message Enable bit (bit 16 of the PCI_MSI_CAP_ID_NEXT_CTRL_REG) is set the function sends a DWORD Memory.." line.long 0xC "MSI_CAP_OFF_0CH_REG,For a function that supports a 32-bit message address. this register contains the Mask Bits when the Per-Vector Masking Capable bit (bit 24 of PCI_MSI_CAP_ID_NEXT_CTRL_REG) is set. For a function that supports a 64-bit message.." hexmask.long.word 0xC 16.--31. 1. "PCI_MSI_CAP_OFF_0EH,For a function that supports a 32-bit message address this field contains the upper Mask Bits when the Per Vector Masking Capable bit (PCI_MSI_CAP_ID_NEXT_CTRL_REG.PCI_PVM_SUPPORT) is set. For a function that supports a 64-bit.." hexmask.long.word 0xC 0.--15. 1. "PCI_MSI_CAP_OFF_0CH,For a function that supports a 32-bit message address this field contains the lower Mask Bits when the Per Vector Masking Capable bit (PCI_MSI_CAP_ID_NEXT_CTRL_REG.PCI_PVM_SUPPORT) is set. For a function that supports a 64-bit.." line.long 0x10 "MSI_CAP_OFF_10H_REG,For a function that supports a 32-bit message address. this register contains the Pending Bits when the Per-Vector Masking Capable bit (bit 24 of PCI_MSI_CAP_ID_NEXT_CTRL_REG) is set. For a function that supports a 64-bit message.." hexmask.long 0x10 0.--31. 1. "PCI_MSI_CAP_OFF_10H,Used for MSI when the Per Vector Masking Capable bit (PCI_MSI_CAP_ID_NEXT_CTRL_REG.PCI_PVM_SUPPORT) is set. For 32-bit contains Pending Bits. For 64-bit contains Mask Bits. For a description of this standard PCIe register field see.." rgroup.long (0x14+0x50)++0x3 line.long 0x0 "MSI_CAP_OFF_14H_REG,Pending Bits Register for MSI. This register is used for a function that supports a 64-bit message address when the Per-Vector Masking Capable bit (bit 24 of PCI_MSI_CAP_ID_NEXT_CTRL_REG) is set." hexmask.long 0x0 0.--31. 1. "PCI_MSI_CAP_OFF_14H,Pending Bits. For each pending bit that is set the function has a pending associated message." tree.end tree "PF0_MSIX_CAP (PF MSI-X Capability Structure)" group.long (0x0+0xB0)++0xB line.long 0x0 "PCI_MSIX_CAP_ID_NEXT_CTRL_REG,MSI-X Capability ID. Next Pointer. Control Registers. For a description of this standard PCIe register. see the PCI Express Base Specification." bitfld.long 0x0 31. "PCI_MSIX_ENABLE,MSI-X Enable. For a description of this standard PCIe register field see the PCI Express Base Specification." "0,1" bitfld.long 0x0 30. "PCI_MSIX_FUNCTION_MASK,Function Mask. For a description of this standard PCIe register field see the PCI Express Base Specification. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" "0,1" rbitfld.long 0x0 27.--29. "RSVDP_27,Reserved for future use." "0,1,2,3,4,5,6,7" newline hexmask.long.word 0x0 16.--26. 1. "PCI_MSIX_TABLE_SIZE,MSI-X Table Size. For a description of this standard PCIe register field see the PCI Express Base Specification. SRIOV Note: All VFs in a single PF have the same value for 'MSI-X Table Size' (PCI_MSIX_TABLE_SIZE field in.." hexmask.long.byte 0x0 8.--15. 1. "PCI_MSIX_CAP_NEXT_OFFSET,MSI-X Next Capability Pointer. For a description of this standard PCIe register field see the PCI Express Base Specification. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN.." hexmask.long.byte 0x0 0.--7. 1. "PCI_MSIX_CAP_ID,MSI-X Capability ID. For a description of this standard PCIe register field see the PCI Express Base Specification." line.long 0x4 "MSIX_TABLE_OFFSET_REG,MSI-X Table Offset and BIR Register. For a description of this standard PCIe register. see the PCI Express Base Specification." hexmask.long 0x4 3.--31. 1. "PCI_MSIX_TABLE_OFFSET,MSI-X Table Offset. For a description of this standard PCIe register field see the PCI Express Base Specification. SRIOV Note: All VFs in a single PF have the same value for 'MSI-X Table Offset' (PCI_MSIX_TABLE_OFFSET field in.." bitfld.long 0x4 0.--2. "PCI_MSIX_BIR,MSI-X Table BAR Indicator Register Field. For a description of this standard PCIe register field see the PCI Express Base Specification. SRIOV Note: All VFs in a single PF have the same value for 'MSI-X Table BAR Indicator Register'.." "0,1,2,3,4,5,6,7" line.long 0x8 "MSIX_PBA_OFFSET_REG,MSI-X PBA Offset and BIR Register. For a description of this standard PCIe register. see the PCI Express Base Specification." hexmask.long 0x8 3.--31. 1. "PCI_MSIX_PBA_OFFSET,MSI-X PBA Offset. For a description of this standard PCIe register field see the PCI Express Base Specification. SRIOV Note: All VFs in a single PF have the same value for 'MSI-X PBA Offset' (PCI_MSIX_PBA_OFFSET field in.." bitfld.long 0x8 0.--2. "PCI_MSIX_PBA_BIR,MSI-X PBA BIR. For a description of this standard PCIe register field see the PCI Express Base Specification. SRIOV Note: All VFs in a single PF have the same value for 'MSI-X PBA BIR' (PCI_MSIX_PBA_BIR field in.." "0,1,2,3,4,5,6,7" tree.end tree "PF0_MSIX_CAP_DBI2 (DBI2 Shadow Block: PF MSI-X Capability Structure)" rgroup.long (0x0+0x10B0)++0x3 line.long 0x0 "SHADOW_PCI_MSIX_CAP_ID_NEXT_CTRL_REG,MSI-X Capability ID. Next Pointer. Control Registers. For a description of this standard PCIe register. see the PCI Express Base Specification." hexmask.long.byte 0x0 27.--31. 1. "RSVDP_27,Reserved for future use." hexmask.long.word 0x0 16.--26. 1. "PCI_MSIX_TABLE_SIZE,MSI-X Table Size in the shadow register. Note: The access attributes of this field are as follows: - Wire: No access - Dbi: No access - Dbi2: if (DBI_RO_WR_EN == 1) then R/W else R Note: This register field is sticky." hexmask.long.word 0x0 0.--15. 1. "RSVDP_0,Reserved for future use." group.long 0x4++0x7 line.long 0x0 "SHADOW_MSIX_TABLE_OFFSET_REG,MSI-X Table Offset and BIR Register. For a description of this standard PCIe register. see the PCI Express Base Specification." hexmask.long 0x0 3.--31. 1. "PCI_MSIX_TABLE_OFFSET,MSI-X Table Offset. For a description of this standard PCIe register field see the PCI Express Base Specification. Note: The access attributes of this field are as follows: - Wire: No access - Dbi: No access - Dbi2: if.." bitfld.long 0x0 0.--2. "PCI_MSIX_BIR,MSI-X Table BAR Indicator Register Field. For a description of this standard PCIe register field see the PCI Express Base Specification. Note: The access attributes of this field are as follows: - Wire: No access - Dbi: No access - Dbi2: if.." "?,?,if,?,?,?,?,?" line.long 0x4 "SHADOW_MSIX_PBA_OFFSET_REG,MSI-X PBA Offset and BIR Register. For a description of this standard PCIe register. see the PCI Express Base Specification." hexmask.long 0x4 3.--31. 1. "PCI_MSIX_PBA_OFFSET,MSI-X PBA Offset. For a description of this standard PCIe register field see the PCI Express Base Specification. Note: The access attributes of this field are as follows: - Wire: No access - Dbi: No access - Dbi2: if (DBI_RO_WR_EN ==.." bitfld.long 0x4 0.--2. "PCI_MSIX_PBA_BIR,MSI-X PBA BIR. For a description of this standard PCIe register field see the PCI Express Base Specification. Note: The access attributes of this field are as follows: - Wire: No access - Dbi: No access - Dbi2: if (DBI_RO_WR_EN == 1 &&.." "?,?,if,?,?,?,?,?" tree.end tree "PF0_DMA_CAP (DMA Port Logic Structure)" group.long (0x0+0xC8000)++0x3 line.long 0x0 "DMA_CTRL_DATA_ARB_PRIOR_OFF,DMA Arbitration Scheme for TRGT1 Interface. This register is used to control traffic priorities among various sources that are delivered to your application through TRGT1 where 0x0 represents the highest priority. - Non-DMA Rx.." hexmask.long.tbyte 0x0 12.--31. 1. "RSVDP_12,Reserved for future use." bitfld.long 0x0 9.--11. "RDBUFF_TRGT_WEIGHT,DMA Read Channel MWr Requests. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 6.--8. "RD_CTRL_TRGT_WEIGHT,DMA Read Channel MRd Requests. For LL element/descriptor access. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" "0,1,2,3,4,5,6,7" bitfld.long 0x0 3.--5. "WR_CTRL_TRGT_WEIGHT,DMA Write Channel MRd Requests. For DMA data requests and LL element/descriptor access. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 0.--2. "RTRGT1_WEIGHT,Non-DMA Rx Requests. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" "0,1,2,3,4,5,6,7" group.long (0x8+0xC8000)++0xB line.long 0x0 "DMA_CTRL_OFF,DMA Number of Channels Register." hexmask.long.byte 0x0 26.--31. 1. "RSVDP_26,Reserved for future use." bitfld.long 0x0 25. "DIS_C2W_CACHE_RD,Disable DMA Read Channels 'completion to memory write' context cache pre-fetch function. Note: For internal debugging only. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" "0,1" newline bitfld.long 0x0 24. "DIS_C2W_CACHE_WR,Disable DMA Write Channels 'completion to memory write' context cache pre-fetch function. Note: For internal debugging only. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" "0,1" hexmask.long.byte 0x0 20.--23. 1. "RSVDP_20,Reserved for future use." newline hexmask.long.byte 0x0 16.--19. 1. "NUM_DMA_RD_CHAN,Number of Read Channels. You can read this register to determine the number of read channels the DMA controller has been configured to support." hexmask.long.word 0x0 4.--15. 1. "RSVDP_4,Reserved for future use." newline hexmask.long.byte 0x0 0.--3. 1. "NUM_DMA_WR_CHAN,Number of Write Channels. You can read this register to determine the number of write channels the DMA controller has been configured to support." line.long 0x4 "DMA_WRITE_ENGINE_EN_OFF,DMA Write Engine Enable Register." hexmask.long.byte 0x4 24.--31. 1. "RSVDP_24,Reserved for future use." bitfld.long 0x4 23. "DMA_WRITE_ENGINE_EN_HSHAKE_CH7,Enable Handshake for DMA Write Engine Channel 7. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" "0,1" newline bitfld.long 0x4 22. "DMA_WRITE_ENGINE_EN_HSHAKE_CH6,Enable Handshake for DMA Write Engine Channel 6. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" "0,1" bitfld.long 0x4 21. "DMA_WRITE_ENGINE_EN_HSHAKE_CH5,Enable Handshake for DMA Write Engine Channel 5. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" "0,1" newline bitfld.long 0x4 20. "DMA_WRITE_ENGINE_EN_HSHAKE_CH4,Enable Handshake for DMA Write Engine Channel 4. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" "0,1" bitfld.long 0x4 19. "DMA_WRITE_ENGINE_EN_HSHAKE_CH3,Enable Handshake for DMA Write Engine Channel 3. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" "0,1" newline bitfld.long 0x4 18. "DMA_WRITE_ENGINE_EN_HSHAKE_CH2,Enable Handshake for DMA Write Engine Channel 2. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" "0,1" bitfld.long 0x4 17. "DMA_WRITE_ENGINE_EN_HSHAKE_CH1,Enable Handshake for DMA Write Engine Channel 1. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" "0,1" newline bitfld.long 0x4 16. "DMA_WRITE_ENGINE_EN_HSHAKE_CH0,Enable Handshake for DMA Write Engine Channel 0. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" "0,1" hexmask.long.word 0x4 1.--15. 1. "RSVDP_1,Reserved for future use." newline bitfld.long 0x4 0. "DMA_WRITE_ENGINE,DMA Write Engine Enable. - 1: Enable - 0: Disable (Soft Reset) For normal operation you must initially set this bit to '1' before any other software setup actions. You do not need to toggle or rewrite to this bit during normal.." "Disable,Enable" line.long 0x8 "DMA_WRITE_DOORBELL_OFF,DMA Write Doorbell Register." bitfld.long 0x8 31. "WR_STOP,Stop. Set in conjunction with the Doorbell Number field. The DMA write channel stops issuing requests sets the channel status to 'Stopped' and asserts the 'Abort' interrupt if it is enabled. Before setting the Stop bit you must read the.." "0,1" hexmask.long 0x8 3.--30. 1. "RSVDP_3,Reserved for future use." newline bitfld.long 0x8 0.--2. "WR_DOORBELL_NUM,Doorbell Number. You must write the channel number to this register to start the DMA write transfer for that channel. The DMA detects a write to this register field even if the value of this field does not change. You do not need to.." "0,1,2,3,4,5,6,7" group.long (0x18+0xC8000)++0x7 line.long 0x0 "DMA_WRITE_CHANNEL_ARB_WEIGHT_LOW_OFF,DMA Write Engine Channel Arbitration Weight Low Register. The 5-bit channel weight (for write channels 0-3) specifies the maximum number of TLP requests that the DMA can issue for that channel before it must return to.." hexmask.long.word 0x0 20.--31. 1. "RSVDP_20,Reserved for future use." hexmask.long.byte 0x0 15.--19. 1. "WRITE_CHANNEL3_WEIGHT,Channel 3 Weight. The weight is initialized by software before ringing the doorbell. The value is used by the channel weighted round robin arbiter to select the next channel read request. A value of '0' means that one TLP is issued.." newline hexmask.long.byte 0x0 10.--14. 1. "WRITE_CHANNEL2_WEIGHT,Channel 2 Weight. The weight is initialized by software before ringing the doorbell. The value is used by the channel weighted round robin arbiter to select the next channel read request. A value of '0' means that one TLP is issued.." hexmask.long.byte 0x0 5.--9. 1. "WRITE_CHANNEL1_WEIGHT,Channel 1 Weight. The weight is initialized by software before ringing the doorbell. The value is used by the channel weighted round robin arbiter to select the next channel read request. A value of '0' means that one TLP is issued.." newline hexmask.long.byte 0x0 0.--4. 1. "WRITE_CHANNEL0_WEIGHT,Channel 0 Weight. The weight is initialized by software before ringing the doorbell. The value is used by the channel weighted round robin arbiter to select the next channel read request. A value of '0' means that one TLP is issued.." line.long 0x4 "DMA_WRITE_CHANNEL_ARB_WEIGHT_HIGH_OFF,DMA Write Engine Channel Arbitration Weight High Register. The 5-bit channel weight (for write channels 4-7) specifies the maximum number of TLP requests that the DMA can issue for that channel before it must return.." hexmask.long.word 0x4 20.--31. 1. "RSVDP_20,Reserved for future use." hexmask.long.byte 0x4 15.--19. 1. "WRITE_CHANNEL7_WEIGHT,Channel 7 Weight. The weight is initialized by software before ringing the doorbell. The value is used by the channel weighted round robin arbiter to select the next channel read request. A value of '0' means that one TLP is issued.." newline hexmask.long.byte 0x4 10.--14. 1. "WRITE_CHANNEL6_WEIGHT,Channel 6 Weight. The weight is initialized by software before ringing the doorbell. The value is used by the channel weighted round robin arbiter to select the next channel read request. A value of '0' means that one TLP is issued.." hexmask.long.byte 0x4 5.--9. 1. "WRITE_CHANNEL5_WEIGHT,Channel 5 Weight. The weight is initialized by software before ringing the doorbell. The value is used by the channel weighted round robin arbiter to select the next channel read request. A value of '0' means that one TLP is issued.." newline hexmask.long.byte 0x4 0.--4. 1. "WRITE_CHANNEL4_WEIGHT,Channel 4 Weight. The weight is initialized by software before ringing the doorbell. The value is used by the channel weighted round robin arbiter to select the next channel read request. A value of '0' means that one TLP is issued.." group.long (0x2C+0xC8000)++0x7 line.long 0x0 "DMA_READ_ENGINE_EN_OFF,DMA Read Engine Enable Register." hexmask.long.byte 0x0 24.--31. 1. "RSVDP_24,Reserved for future use." bitfld.long 0x0 23. "DMA_READ_ENGINE_EN_HSHAKE_CH7,Enable Handshake for DMA Read Engine Channel 7. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" "0,1" newline bitfld.long 0x0 22. "DMA_READ_ENGINE_EN_HSHAKE_CH6,Enable Handshake for DMA Read Engine Channel 6. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" "0,1" bitfld.long 0x0 21. "DMA_READ_ENGINE_EN_HSHAKE_CH5,Enable Handshake for DMA Read Engine Channel 5. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" "0,1" newline bitfld.long 0x0 20. "DMA_READ_ENGINE_EN_HSHAKE_CH4,Enable Handshake for DMA Read Engine Channel 4. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" "0,1" bitfld.long 0x0 19. "DMA_READ_ENGINE_EN_HSHAKE_CH3,Enable Handshake for DMA Read Engine Channel 3. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" "0,1" newline bitfld.long 0x0 18. "DMA_READ_ENGINE_EN_HSHAKE_CH2,Enable Handshake for DMA Read Engine Channel 2. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" "0,1" bitfld.long 0x0 17. "DMA_READ_ENGINE_EN_HSHAKE_CH1,Enable Handshake for DMA Read Engine Channel 1. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" "0,1" newline bitfld.long 0x0 16. "DMA_READ_ENGINE_EN_HSHAKE_CH0,Enable Handshake for DMA Read Engine Channel 0. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" "0,1" hexmask.long.word 0x0 1.--15. 1. "RSVDP_1,Reserved for future use." newline bitfld.long 0x0 0. "DMA_READ_ENGINE,DMA Read Engine Enable. - 1: Enable - 0: Disable (Soft Reset) For normal operation you must initially set this bit to '1' before any other software setup actions. You do not need to toggle or rewrite to this bit during normal operation." "Disable,Enable" line.long 0x4 "DMA_READ_DOORBELL_OFF,DMA Read Doorbell Register." bitfld.long 0x4 31. "RD_STOP,Stop. Set in conjunction with the Doorbell Number field. The DMA read channel stops issuing requests sets the channel status to 'Stopped' and asserts the 'Abort' interrupt if it is enabled. Before setting the Stop bit you must read the channel.." "0,1" hexmask.long 0x4 3.--30. 1. "RSVDP_3,Reserved for future use." newline bitfld.long 0x4 0.--2. "RD_DOORBELL_NUM,Doorbell Number. You must write 0x0 to this register to start the DMA read transfer for that channel. The DMA detects a write to this register field even if the value of this field does not change. The range of this field is 0x0 to 0x7.." "0,1,2,3,4,5,6,7" group.long (0x38+0xC8000)++0x7 line.long 0x0 "DMA_READ_CHANNEL_ARB_WEIGHT_LOW_OFF,DMA Read Engine Channel Arbitration Weight Low Register. The 5-bit channel weight (for read channels 0-3) specifies the maximum number of TLP requests that the DMA can issue for that channel before it must return to.." hexmask.long.word 0x0 20.--31. 1. "RSVDP_20,Reserved for future use." hexmask.long.byte 0x0 15.--19. 1. "READ_CHANNEL3_WEIGHT,Channel 3 Weight. The weight is initialized by software before ringing the doorbell. The value is used by the channel weighted round robin arbiter to select the next channel read request. Note: The access attributes of this field are.." newline hexmask.long.byte 0x0 10.--14. 1. "READ_CHANNEL2_WEIGHT,Channel 2 Weight. The weight is initialized by software before ringing the doorbell. The value is used by the channel weighted round robin arbiter to select the next channel read request. Note: The access attributes of this field are.." hexmask.long.byte 0x0 5.--9. 1. "READ_CHANNEL1_WEIGHT,Channel 1 Weight. The weight is initialized by software before ringing the doorbell. The value is used by the channel weighted round robin arbiter to select the next channel read request. Note: The access attributes of this field are.." newline hexmask.long.byte 0x0 0.--4. 1. "READ_CHANNEL0_WEIGHT,Channel 0 Weight. The weight is initialized by software before ringing the doorbell. The value is used by the channel weighted round robin arbiter to select the next channel read request. Note: The access attributes of this field are.." line.long 0x4 "DMA_READ_CHANNEL_ARB_WEIGHT_HIGH_OFF,DMA Read Engine Channel Arbitration Weight High Register. The 5-bit channel weight (for read channels 4-7) specifies the maximum number of TLP requests that the DMA can issue for that channel before it must return to.." hexmask.long.word 0x4 20.--31. 1. "RSVDP_20,Reserved for future use." hexmask.long.byte 0x4 15.--19. 1. "READ_CHANNEL7_WEIGHT,Channel 7 Weight. The weight is initialized by software before ringing the doorbell. The value is used by the channel weighted round robin arbiter to select the next channel read request. Note: The access attributes of this field are.." newline hexmask.long.byte 0x4 10.--14. 1. "READ_CHANNEL6_WEIGHT,Channel 6 Weight. The weight is initialized by software before ringing the doorbell. The value is used by the channel weighted round robin arbiter to select the next channel read request. Note: The access attributes of this field are.." hexmask.long.byte 0x4 5.--9. 1. "READ_CHANNEL5_WEIGHT,Channel 5 Weight. The weight is initialized by software before ringing the doorbell. The value is used by the channel weighted round robin arbiter to select the next channel read request. Note: The access attributes of this field are.." newline hexmask.long.byte 0x4 0.--4. 1. "READ_CHANNEL4_WEIGHT,Channel 4 Weight. The weight is initialized by software before ringing the doorbell. The value is used by the channel weighted round robin arbiter to select the next channel read request. Note: The access attributes of this field are.." group.long (0x4C+0xC8000)++0x3 line.long 0x0 "DMA_WRITE_INT_STATUS_OFF,DMA Write Interrupt Status Register." hexmask.long.byte 0x0 24.--31. 1. "RSVDP_24,Reserved for future use." hexmask.long.byte 0x0 16.--23. 1. "WR_ABORT_INT_STATUS,Abort Interrupt Status. The DMA write channel has detected an error or you manually stopped the transfer as described in 'Error Handling Assistance by Remote Software'. Each bit corresponds to a DMA channel. Bit [0] corresponds to.." newline hexmask.long.byte 0x0 8.--15. 1. "RSVDP_8,Reserved for future use." hexmask.long.byte 0x0 0.--7. 1. "WR_DONE_INT_STATUS,Done Interrupt Status. The DMA write channel has successfully completed the DMA transfer. For more details see 'Interrupts and Error Handling'. Each bit corresponds to a DMA channel. Bit [0] corresponds to channel 0. - Enabling: For.." group.long (0x54+0xC8000)++0x7 line.long 0x0 "DMA_WRITE_INT_MASK_OFF,DMA Write Interrupt Mask Register." hexmask.long.byte 0x0 24.--31. 1. "RSVDP_24,Reserved for future use." hexmask.long.byte 0x0 16.--23. 1. "WR_ABORT_INT_MASK,Abort Interrupt Mask. Prevents the Abort interrupt status field in the DMA write interrupt status register from asserting the edma_int output. Each bit corresponds to a DMA channel. Bit [0] corresponds to channel 0. Note: The access.." newline hexmask.long.byte 0x0 8.--15. 1. "RSVDP_8,Reserved for future use." hexmask.long.byte 0x0 0.--7. 1. "WR_DONE_INT_MASK,Done Interrupt Mask. Prevents the Done interrupt status field in the DMA write interrupt status register from asserting the edma_int output. Each bit corresponds to a DMA channel. Bit [0] corresponds to channel 0. Note: The access.." line.long 0x4 "DMA_WRITE_INT_CLEAR_OFF,DMA Write Interrupt Clear Register." hexmask.long.byte 0x4 24.--31. 1. "RSVDP_24,Reserved for future use." hexmask.long.byte 0x4 16.--23. 1. "WR_ABORT_INT_CLEAR,Abort Interrupt Clear. You must write a 1'b1 to clear the corresponding bit in the Abort interrupt status field of the DMA write interrupt status register. Each bit corresponds to a DMA channel. Bit [0] corresponds to channel 0. Note:.." newline hexmask.long.byte 0x4 8.--15. 1. "RSVDP_8,Reserved for future use." hexmask.long.byte 0x4 0.--7. 1. "WR_DONE_INT_CLEAR,Done Interrupt Clear. You must write a 1'b1 to clear the corresponding bit in the Done interrupt status field of the DMA write interrupt status register. Each bit corresponds to a DMA channel. Bit [0] corresponds to channel 0. Note:.." rgroup.long (0x5C+0xC8000)++0x3 line.long 0x0 "DMA_WRITE_ERR_STATUS_OFF,DMA Write Error Status Register" hexmask.long.byte 0x0 24.--31. 1. "RSVDP_24,Reserved for future use." hexmask.long.byte 0x0 16.--23. 1. "LINKLIST_ELEMENT_FETCH_ERR_DETECT,Linked List Element Fetch Error Detected. The DMA write channel has received an error response from the AXI bus (or TRGT1 interface when the AXI Bridge is not used) while reading a linked list element from local memory." newline hexmask.long.byte 0x0 8.--15. 1. "RSVDP_8,Reserved for future use." hexmask.long.byte 0x0 0.--7. 1. "APP_READ_ERR_DETECT,Application Read Error Detected. The DMA write channel has received an error response from the AXI bus (or TRGT1 interface when the AXI Bridge is not used) while reading data from it. Each bit corresponds to a DMA channel. Bit [0].." group.long (0x60+0xC8000)++0x1F line.long 0x0 "DMA_WRITE_DONE_IMWR_LOW_OFF,DMA Write Done IMWr Address Low Register." hexmask.long 0x0 0.--31. 1. "DMA_WRITE_DONE_LOW_REG,The DMA uses this field to generate bits [31:0] of the address field for the Done IMWr TLP. Bits [1:0] must be '00' as this address must be dword aligned. Note: The access attributes of this field are as follows: - Wire: No access." line.long 0x4 "DMA_WRITE_DONE_IMWR_HIGH_OFF,DMA Write Done IMWr Interrupt Address High Register." hexmask.long 0x4 0.--31. 1. "DMA_WRITE_DONE_HIGH_REG,The DMA uses this field to generate bits [63:32] of the address field for the Done IMWr TLP. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" line.long 0x8 "DMA_WRITE_ABORT_IMWR_LOW_OFF,DMA Write Abort IMWr Address Low Register." hexmask.long 0x8 0.--31. 1. "DMA_WRITE_ABORT_LOW_REG,The DMA uses this field to generate bits [31:0] of the address field for the Abort IMWr TLP it generates. Bits [1:0] must be '00' as this address must be dword aligned. Note: The access attributes of this field are as follows: -.." line.long 0xC "DMA_WRITE_ABORT_IMWR_HIGH_OFF,DMA Write Abort IMWr Address High Register." hexmask.long 0xC 0.--31. 1. "DMA_WRITE_ABORT_HIGH_REG,The DMA uses this field to generate bits [63:32] of the address field for the Abort IMWr TLP. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" line.long 0x10 "DMA_WRITE_CH01_IMWR_DATA_OFF,DMA Write Channel 1 and 0 IMWr Data Register." hexmask.long.word 0x10 16.--31. 1. "WR_CHANNEL_1_DATA,The DMA uses this field to generate the data field for the Done or Abort IMWr TLPs it generates for write channel 1. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" hexmask.long.word 0x10 0.--15. 1. "WR_CHANNEL_0_DATA,The DMA uses this field to generate the data field for the Done or Abort IMWr TLPs it generates for write channel 0. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" line.long 0x14 "DMA_WRITE_CH23_IMWR_DATA_OFF,DMA Write Channel 3 and 2 IMWr Data Register." hexmask.long.word 0x14 16.--31. 1. "WR_CHANNEL_3_DATA,The DMA uses this field to generate the data field for the Done or Abort IMWr TLPs it generates for write channel 3. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" hexmask.long.word 0x14 0.--15. 1. "WR_CHANNEL_2_DATA,The DMA uses this field to generate the data field for the Done or Abort IMWr TLPs it generates for write channel 2. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" line.long 0x18 "DMA_WRITE_CH45_IMWR_DATA_OFF,DMA Write Channel 5 and 4 IMWr Data Register." hexmask.long.word 0x18 16.--31. 1. "WR_CHANNEL_5_DATA,The DMA uses this field to generate the data field for the Done or Abort IMWr TLPs it generates for write channel 5. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" hexmask.long.word 0x18 0.--15. 1. "WR_CHANNEL_4_DATA,The DMA uses this field to generate the data field for the Done or Abort IMWr TLPs it generates for write channel 4. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" line.long 0x1C "DMA_WRITE_CH67_IMWR_DATA_OFF,DMA Write Channel 7 and 6 IMWr Data Register." hexmask.long.word 0x1C 16.--31. 1. "WR_CHANNEL_7_DATA,The DMA uses this field to generate the data field for the Done or Abort IMWr TLPs it generates for write channel 7. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" hexmask.long.word 0x1C 0.--15. 1. "WR_CHANNEL_6_DATA,The DMA uses this field to generate the data field for the Done or Abort IMWr TLPs it generates for write channel 6. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" group.long (0x90+0xC8000)++0x3 line.long 0x0 "DMA_WRITE_LINKED_LIST_ERR_EN_OFF,DMA Write Linked List Error Enable Register. The LIE and RIE bits in the LL element enable the channel 'done' interrupts (local and remote). The LLLAIE and LLRAIE bits enable the channel 'abort' interrupts (local and.." hexmask.long.byte 0x0 24.--31. 1. "RSVDP_24,Reserved for future use." hexmask.long.byte 0x0 16.--23. 1. "WR_CHANNEL_LLLAIE,Write Channel LL Local Abort Interrupt Enable (LLLAIE). You enable the write channel local abort interrupt through this bit. The LIE and RIE bits in the LL element enable the write channel done interrupts. Each bit corresponds to a DMA.." newline hexmask.long.byte 0x0 8.--15. 1. "RSVDP_8,Reserved for future use." hexmask.long.byte 0x0 0.--7. 1. "WR_CHANNEL_LLRAIE,Write Channel LL Remote Abort Interrupt Enable (LLRAIE). You enable the write channel remote abort interrupt through this bit. The LIE and RIE bits in the LL element enable the write channel done interrupts. Each bit corresponds to a.." group.long (0xA0+0xC8000)++0x3 line.long 0x0 "DMA_READ_INT_STATUS_OFF,DMA Read Interrupt Status Register." hexmask.long.byte 0x0 24.--31. 1. "RSVDP_24,Reserved for future use." hexmask.long.byte 0x0 16.--23. 1. "RD_ABORT_INT_STATUS,Abort Interrupt Status. The DMA read channel has detected an error or you manually stopped the transfer as described in 'Stopping the DMA Transfer (Software Stop)'. Each bit corresponds to a DMA channel. Bit [0] corresponds to.." newline hexmask.long.byte 0x0 8.--15. 1. "RSVDP_8,Reserved for future use." hexmask.long.byte 0x0 0.--7. 1. "RD_DONE_INT_STATUS,Done Interrupt Status. The DMA read channel has successfully completed the DMA read transfer. Each bit corresponds to a DMA channel. Bit [0] corresponds to channel 0. - Enabling: For details see 'Interrupts and Error Handling'. -.." group.long (0xA8+0xC8000)++0x7 line.long 0x0 "DMA_READ_INT_MASK_OFF,DMA Read Interrupt Mask Register." hexmask.long.byte 0x0 24.--31. 1. "RSVDP_24,Reserved for future use." hexmask.long.byte 0x0 16.--23. 1. "RD_ABORT_INT_MASK,Abort Interrupt Mask. Prevents the Abort interrupt status field in the DMA read interrupt status register from asserting the edma_int output. Each bit corresponds to a DMA channel. Bit [0] corresponds to channel 0. Note: The access.." newline hexmask.long.byte 0x0 8.--15. 1. "RSVDP_8,Reserved for future use." hexmask.long.byte 0x0 0.--7. 1. "RD_DONE_INT_MASK,Done Interrupt Mask. Prevents the Done interrupt status field in the DMA read interrupt status register from asserting the edma_int output. Each bit corresponds to a DMA channel. Bit [0] corresponds to channel 0. Note: The access.." line.long 0x4 "DMA_READ_INT_CLEAR_OFF,DMA Read Interrupt Clear Register." hexmask.long.byte 0x4 24.--31. 1. "RSVDP_24,Reserved for future use." hexmask.long.byte 0x4 16.--23. 1. "RD_ABORT_INT_CLEAR,Abort Interrupt Clear. You must write a 1'b1 to clear the corresponding bit in the Abort interrupt status field of the DMA read interrupt status register. Each bit corresponds to a DMA channel. Bit [0] corresponds to channel 0. Note:.." newline hexmask.long.byte 0x4 8.--15. 1. "RSVDP_8,Reserved for future use." hexmask.long.byte 0x4 0.--7. 1. "RD_DONE_INT_CLEAR,Done Interrupt Clear. You must write a 1'b1 to clear the corresponding bit in the Done interrupt status field of the DMA read interrupt status register. Each bit corresponds to a DMA channel. Bit [0] corresponds to channel 0. Note:.." rgroup.long (0xB4+0xC8000)++0x7 line.long 0x0 "DMA_READ_ERR_STATUS_LOW_OFF,DMA Read Error Status Low Register." hexmask.long.byte 0x0 24.--31. 1. "RSVDP_24,Reserved for future use." hexmask.long.byte 0x0 16.--23. 1. "LINK_LIST_ELEMENT_FETCH_ERR_DETECT,Linked List Element Fetch Error Detected. - The DMA read channel has received an error response from the AXI bus while reading a linked list element from local memory. Each bit corresponds to a DMA channel. Bit [0].." newline hexmask.long.byte 0x0 8.--15. 1. "RSVDP_8,Reserved for future use." hexmask.long.byte 0x0 0.--7. 1. "APP_WR_ERR_DETECT,Application Write Error Detected. The DMA read channel has received an error response from the AXI bus (or TRGT1 interface when the AXI Bridge is not used) while writing data to it. This error is fatal. You must restart the transfer.." line.long 0x4 "DMA_READ_ERR_STATUS_HIGH_OFF,DMA Read Error Status High Register." hexmask.long.byte 0x4 24.--31. 1. "DATA_POISIONING,Data Poisoning. The DMA read channel has detected data poisoning in the completion from the remote device (in response to the MRd request). The DMA read channel will drop the completion and then be halted. The CX_FLT_MASK_UR_POIS filter.." hexmask.long.byte 0x4 16.--23. 1. "CPL_TIMEOUT,Completion Time Out. The DMA read channel has timed-out while waiting for the remote device to respond to the MRd request or a malformed CplD has been received. For more details see 'Linked List Mode'. Each bit corresponds to a DMA channel." newline hexmask.long.byte 0x4 8.--15. 1. "CPL_ABORT,Completer Abort. The DMA read channel has received a PCIe completer abort completion status from the remote device in response to the MRd request. For more details see 'Linked List Mode'. Each bit corresponds to a DMA channel. Bit [0].." hexmask.long.byte 0x4 0.--7. 1. "UNSUPPORTED_REQ,Unsupported Request. The DMA read channel has received a PCIe unsupported request completion status from the remote device in response to the MRd request. For more details see 'Linked List Mode'. Each bit corresponds to a DMA channel." group.long (0xC4+0xC8000)++0x3 line.long 0x0 "DMA_READ_LINKED_LIST_ERR_EN_OFF,DMA Read Linked List Error Enable Register. The LIE and RIE bits in the LL element enable the channel 'done' interrupts (local and remote). The LLLAIE and LLRAIE bits enable the channel 'abort' interrupts (local and remote)." hexmask.long.byte 0x0 24.--31. 1. "RSVDP_24,Reserved for future use." hexmask.long.byte 0x0 16.--23. 1. "RD_CHANNEL_LLLAIE,Read Channel LL Local Abort Interrupt Enable (LLLAIE). You enable the read channel Local Abort interrupt through this bit. The LIE and RIE bits in the LL element enable the read channel done interrupts. Each bit corresponds to a DMA.." newline hexmask.long.byte 0x0 8.--15. 1. "RSVDP_8,Reserved for future use." hexmask.long.byte 0x0 0.--7. 1. "RD_CHANNEL_LLRAIE,Read Channel LL Remote Abort Interrupt Enable (LLRAIE). You enable the read channel Remote Abort interrupt through this bit. The LIE and RIE bits in the LL element enable the read channel done interrupts. Each bit corresponds to a DMA.." group.long (0xCC+0xC8000)++0x1F line.long 0x0 "DMA_READ_DONE_IMWR_LOW_OFF,DMA Read Done IMWr Address Low Register." hexmask.long 0x0 0.--31. 1. "DMA_READ_DONE_LOW_REG,The DMA uses this field to generate bits [31:0] of the address field for the Done IMWr TLP. Bits [1:0] must be '00' as this address must be dword aligned. Note: The access attributes of this field are as follows: - Wire: No access." line.long 0x4 "DMA_READ_DONE_IMWR_HIGH_OFF,DMA Read Done IMWr Address High Register." hexmask.long 0x4 0.--31. 1. "DMA_READ_DONE_HIGH_REG,The DMA uses this field to generate bits [63:32] of the address field for the Done IMWr TLP. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" line.long 0x8 "DMA_READ_ABORT_IMWR_LOW_OFF,DMA Read Abort IMWr Address Low Register." hexmask.long 0x8 0.--31. 1. "DMA_READ_ABORT_LOW_REG,The DMA uses this field to generate bits [31:0] of the address field for the Abort IMWr TLP. Bits [1:0] must be '00' as this address must be dword aligned. Note: The access attributes of this field are as follows: - Wire: No.." line.long 0xC "DMA_READ_ABORT_IMWR_HIGH_OFF,DMA Read Abort IMWr Address High Register." hexmask.long 0xC 0.--31. 1. "DMA_READ_ABORT_HIGH_REG,The DMA uses this field to generate bits [63:32] of the address field for the Abort IMWr TLP. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" line.long 0x10 "DMA_READ_CH01_IMWR_DATA_OFF,DMA Read Channel 1 and 0 IMWr Data Register." hexmask.long.word 0x10 16.--31. 1. "RD_CHANNEL_1_DATA,The DMA uses this field to generate the data field for the Done or Abort IMWr TLPs it generates for read channel 1. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" hexmask.long.word 0x10 0.--15. 1. "RD_CHANNEL_0_DATA,The DMA uses this field to generate the data field for the Done or Abort IMWr TLPs it generates for read channel 0. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" line.long 0x14 "DMA_READ_CH23_IMWR_DATA_OFF,DMA Read Channel 3 and 2 IMWr Data Register." hexmask.long.word 0x14 16.--31. 1. "RD_CHANNEL_3_DATA,The DMA uses this field to generate the data field for the Done or Abort IMWr TLPs it generates for read channel 3. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" hexmask.long.word 0x14 0.--15. 1. "RD_CHANNEL_2_DATA,The DMA uses this field to generate the data field for the Done or Abort IMWr TLPs it generates for read channel 2. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" line.long 0x18 "DMA_READ_CH45_IMWR_DATA_OFF,DMA Read Channel 5 and 4 IMWr Data Register." hexmask.long.word 0x18 16.--31. 1. "RD_CHANNEL_5_DATA,The DMA uses this field to generate the data field for the Done or Abort IMWr TLPs it generates for read channel 5. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" hexmask.long.word 0x18 0.--15. 1. "RD_CHANNEL_4_DATA,The DMA uses this field to generate the data field for the Done or Abort IMWr TLPs it generates for read channel 4. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" line.long 0x1C "DMA_READ_CH67_IMWR_DATA_OFF,DMA Read Channel 7 and 6 IMWr Data Register." hexmask.long.word 0x1C 16.--31. 1. "RD_CHANNEL_7_DATA,The DMA uses this field to generate the data field for the Done or Abort IMWr TLPs it generates for read channel 7. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" hexmask.long.word 0x1C 0.--15. 1. "RD_CHANNEL_6_DATA,The DMA uses this field to generate the data field for the Done or Abort IMWr TLPs it generates for read channel 6. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" rgroup.long (0x108+0xC8000)++0x7 line.long 0x0 "DMA_WRITE_ENGINE_HSHAKE_CNT_LOW_OFF,DMA Write Engine Handshake Counter Channel 0/1/2/3 Register." bitfld.long 0x0 29.--31. "RSVDP_29,Reserved for future use." "0,1,2,3,4,5,6,7" hexmask.long.byte 0x0 24.--28. 1. "DMA_WRITE_ENGINE_HSHAKE_CNT_CH3,DMA handshake counter for DMA Write Engine Channel 3. If CC_DMA_HSHAKE =1 the data transfer in Linked List mode starts only when the counter is non-zero." newline bitfld.long 0x0 21.--23. "RSVDP_21,Reserved for future use." "0,1,2,3,4,5,6,7" hexmask.long.byte 0x0 16.--20. 1. "DMA_WRITE_ENGINE_HSHAKE_CNT_CH2,DMA handshake counter for DMA Write Engine Channel 2. If CC_DMA_HSHAKE =1 the data transfer in Linked List mode starts only when the counter is non-zero." newline bitfld.long 0x0 13.--15. "RSVDP_13,Reserved for future use." "0,1,2,3,4,5,6,7" hexmask.long.byte 0x0 8.--12. 1. "DMA_WRITE_ENGINE_HSHAKE_CNT_CH1,DMA handshake counter for DMA Write Engine Channel 1. If CC_DMA_HSHAKE =1 the data transfer in Linked List mode starts only when the counter is non-zero." newline bitfld.long 0x0 5.--7. "RSVDP_5,Reserved for future use." "0,1,2,3,4,5,6,7" hexmask.long.byte 0x0 0.--4. 1. "DMA_WRITE_ENGINE_HSHAKE_CNT_CH0,DMA handshake counter for DMA Write Engine Channel 0. If CC_DMA_HSHAKE =1 the data transfer in Linked List mode starts only when the counter is non-zero." line.long 0x4 "DMA_WRITE_ENGINE_HSHAKE_CNT_HIGH_OFF,DMA Write Engine Handshake Counter Channel 4/5/6/7 Register." bitfld.long 0x4 29.--31. "RSVDP_29,Reserved for future use." "0,1,2,3,4,5,6,7" hexmask.long.byte 0x4 24.--28. 1. "DMA_WRITE_ENGINE_HSHAKE_CNT_CH7,DMA handshake counter for DMA Write Engine Channel 7. If CC_DMA_HSHAKE =1 the data transfer in Linked List mode starts only when the counter is non-zero." newline bitfld.long 0x4 21.--23. "RSVDP_21,Reserved for future use." "0,1,2,3,4,5,6,7" hexmask.long.byte 0x4 16.--20. 1. "DMA_WRITE_ENGINE_HSHAKE_CNT_CH6,DMA handshake counter for DMA Write Engine Channel 6. If CC_DMA_HSHAKE =1 the data transfer in Linked List mode starts only when the counter is non-zero." newline bitfld.long 0x4 13.--15. "RSVDP_13,Reserved for future use." "0,1,2,3,4,5,6,7" hexmask.long.byte 0x4 8.--12. 1. "DMA_WRITE_ENGINE_HSHAKE_CNT_CH5,DMA handshake counter for DMA Write Engine Channel 5. If CC_DMA_HSHAKE =1 the data transfer in Linked List mode starts only when the counter is non-zero." newline bitfld.long 0x4 5.--7. "RSVDP_5,Reserved for future use." "0,1,2,3,4,5,6,7" hexmask.long.byte 0x4 0.--4. 1. "DMA_WRITE_ENGINE_HSHAKE_CNT_CH4,DMA handshake counter for DMA Write Engine Channel 4. If CC_DMA_HSHAKE =1 the data transfer in Linked List mode starts only when the counter is non-zero." rgroup.long (0x118+0xC8000)++0x7 line.long 0x0 "DMA_READ_ENGINE_HSHAKE_CNT_LOW_OFF,DMA Read Engine Handshake Counter Channel 0/1/2/3 Register." bitfld.long 0x0 29.--31. "RSVDP_29,Reserved for future use." "0,1,2,3,4,5,6,7" hexmask.long.byte 0x0 24.--28. 1. "DMA_READ_ENGINE_HSHAKE_CNT_CH3,DMA handshake counter for DMA Read Engine Channel 3. If CC_DMA_HSHAKE =1 the data transfer in Linked List mode starts only when the counter is non-zero." newline bitfld.long 0x0 21.--23. "RSVDP_21,Reserved for future use." "0,1,2,3,4,5,6,7" hexmask.long.byte 0x0 16.--20. 1. "DMA_READ_ENGINE_HSHAKE_CNT_CH2,DMA handshake counter for DMA Read Engine Channel 2. If CC_DMA_HSHAKE =1 the data transfer in Linked List mode starts only when the counter is non-zero." newline bitfld.long 0x0 13.--15. "RSVDP_13,Reserved for future use." "0,1,2,3,4,5,6,7" hexmask.long.byte 0x0 8.--12. 1. "DMA_READ_ENGINE_HSHAKE_CNT_CH1,DMA handshake counter for DMA Read Engine Channel 1. If CC_DMA_HSHAKE =1 the data transfer in Linked List mode starts only when the counter is non-zero." newline bitfld.long 0x0 5.--7. "RSVDP_5,Reserved for future use." "0,1,2,3,4,5,6,7" hexmask.long.byte 0x0 0.--4. 1. "DMA_READ_ENGINE_HSHAKE_CNT_CH0,DMA handshake counter for DMA Read Engine Channel 0. If CC_DMA_HSHAKE =1 the data transfer in Linked List mode starts only when the counter is non-zero." line.long 0x4 "DMA_READ_ENGINE_HSHAKE_CNT_HIGH_OFF,DMA Read Engine Handshake Counter Channel 4/5/6/7 Register." bitfld.long 0x4 29.--31. "RSVDP_29,Reserved for future use." "0,1,2,3,4,5,6,7" hexmask.long.byte 0x4 24.--28. 1. "DMA_READ_ENGINE_HSHAKE_CNT_CH7,DMA handshake counter for DMA Read Engine Channel 7. If CC_DMA_HSHAKE =1 the data transfer in Linked List mode starts only when the counter is non-zero." newline bitfld.long 0x4 21.--23. "RSVDP_21,Reserved for future use." "0,1,2,3,4,5,6,7" hexmask.long.byte 0x4 16.--20. 1. "DMA_READ_ENGINE_HSHAKE_CNT_CH6,DMA handshake counter for DMA Read Engine Channel 6. If CC_DMA_HSHAKE =1 the data transfer in Linked List mode starts only when the counter is non-zero." newline bitfld.long 0x4 13.--15. "RSVDP_13,Reserved for future use." "0,1,2,3,4,5,6,7" hexmask.long.byte 0x4 8.--12. 1. "DMA_READ_ENGINE_HSHAKE_CNT_CH5,DMA handshake counter for DMA Read Engine Channel 5. If CC_DMA_HSHAKE =1 the data transfer in Linked List mode starts only when the counter is non-zero." newline bitfld.long 0x4 5.--7. "RSVDP_5,Reserved for future use." "0,1,2,3,4,5,6,7" hexmask.long.byte 0x4 0.--4. 1. "DMA_READ_ENGINE_HSHAKE_CNT_CH4,DMA handshake counter for DMA Read Engine Channel 4. If CC_DMA_HSHAKE =1 the data transfer in Linked List mode starts only when the counter is non-zero." repeat 8. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 )(list 0x0 0x200 0x400 0x600 0x800 0xA00 0xC00 0xE00 ) group.long ($2+0x200+0xC8000)++0x3 line.long 0x0 "DMA_CH_CONTROL1_OFF_WRCH_$1,DMA Write Channel Control 1 Register." bitfld.long 0x0 30.--31. "DMA_AT,Address Translation TLP Header Bit (AT) The DMA uses this TLP header field when generating MRd/MWr (not IMWr) TLPs. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" "0,1,2,3" bitfld.long 0x0 27.--29. "DMA_TC,Traffic Class TLP Header Bit (TC) The DMA uses this TLP header field when generating MRd/MWr (not IMWr) TLPs. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 26. "DMA_RESERVED5,Reserved. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" "0,1" bitfld.long 0x0 25. "DMA_RO,Relaxed Ordering TLP Header Bit (RO) The DMA uses this TLP header field when generating MRd/MWr (not IMWr) TLPs. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" "0,1" newline bitfld.long 0x0 24. "DMA_NS_SRC,Source No Snoop TLP Header Bit (DMA_NS_SRC). The DMA uses this TLP header field when generating MRd (SAR addressing space) (not IMWr) TLPs. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" "0,1" bitfld.long 0x0 23. "DMA_NS_DST,Destination No Snoop TLP Header Bit (DMA_NS_DST). The DMA uses this TLP header field when generating MWr (DAR addressing space) (not IMWr) TLPs. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" "0,1" newline bitfld.long 0x0 22. "DMA_MEM_TYPE,Master AXI ACE-Lite Cache Coherency Control. This field sets the DMA channel memory type of the address space of the data transfer as follows: - 0x0:peripheral type - 0x1:memory type For more details see 'ACE-Lite Features and Limitations'.." "peripheral type,memory type" hexmask.long.byte 0x0 17.--21. 1. "DMA_RESERVED2,Reserved. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" newline hexmask.long.byte 0x0 12.--16. 1. "DMA_FUNC_NUM,Function Number (FN). The controller uses this field when generating the requester ID for the MRd/MWr DMA TLP. When you have enabled SR-IOV then this field is ignored if you have set the VFE field in the 'DMA Write Channel Control 2.." bitfld.long 0x0 10.--11. "DMA_RESERVED1,Reserved. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" "0,1,2,3" newline bitfld.long 0x0 9. "LLE,Linked List Enable (LLE). - 0: Disable linked list operation - 1: Enable linked list operation Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" "Disable linked list operation,Enable linked list operation" bitfld.long 0x0 8. "CCS,Consumer Cycle State (CCS). Used in linked list mode only. It is used to synchronize the producer (software) and the consumer (DMA). For more details see 'PCS-CCS-CB-TCB Producer-Consumer Synchronization'. You must initialize this bit. The DMA.." "0,1" newline bitfld.long 0x0 7. "DMA_RESERVED0,Reserved. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" "0,1" bitfld.long 0x0 5.--6. "CS,Channel Status (CS). The channel status bits identify the current operational state of the DMA channel. The operation state encoding for each DMA channel is a s follows: - 00: Reserved - 01: Running. This channel is active and transferring data. - 10:.." "Reserved,Running,?,?" newline bitfld.long 0x0 4. "RIE,Remote Interrupt Enable (RIE). You must set this bit to enable the generation of the Done or Abort Remote interrupts. For more details see 'Interrupts and Error Handling'. In LL mode the DMA overwrites this with the RIE of the LL element. The RIE.." "0,1" bitfld.long 0x0 3. "LIE,Local Interrupt Enable (LIE). You must set this bit to enable the generation of the Done or Abort Local interrupts. For more details see 'Interrupts and Error Handling'. In LL mode the DMA overwrites this with the LIE of the LL element. The LIE bit.." "0,1" newline bitfld.long 0x0 2. "LLP,Load Link Pointer (LLP). Used in linked list mode only. Indicates that this linked list element is a link element and its LL element pointer dwords are pointing to the next (non-contiguous) element. The DMA loads this field with the LLP of the.." "0,1" bitfld.long 0x0 1. "TCB,Toggle Cycle Bit (TCB). Indicates to the DMA to toggle its interpretation of the CB. Used in linked list mode only. It is used to synchronize the producer (software) and the consumer (DMA). For more details see 'PCS-CCS-CB-TCB Producer-Consumer.." "0,1" newline bitfld.long 0x0 0. "CB,Cycle Bit (CB). Used in linked list mode only. It is used to synchronize the producer (software) and the consumer (DMA). For more details see 'PCS-CCS-CB-TCB Producer-Consumer Synchronization'. The DMA loads this field with the CB of the linked list.." "0,1" repeat.end repeat 8. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 )(list 0x0 0x200 0x400 0x600 0x800 0xA00 0xC00 0xE00 ) group.long ($2+0x208+0xC8000)++0x3 line.long 0x0 "DMA_TRANSFER_SIZE_OFF_WRCH_$1,DMA Write Transfer Size Register." hexmask.long 0x0 0.--31. 1. "DMA_TRANSFER_SIZE,DMA Transfer Size. You program this register with the size of the DMA transfer. The maximum DMA transfer size is 4Gbytes. The minimum transfer size is one byte (0x1). This field is automatically decremented by the DMA as the DMA write.." repeat.end repeat 8. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 )(list 0x0 0x200 0x400 0x600 0x800 0xA00 0xC00 0xE00 ) group.long ($2+0x20C+0xC8000)++0x3 line.long 0x0 "DMA_SAR_LOW_OFF_WRCH_$1,DMA Write SAR Low Register." hexmask.long 0x0 0.--31. 1. "SRC_ADDR_REG_LOW,Source Address Register (Lower 32 bits). Indicates the next address to be read from. The DMA increments the SAR as the DMA transfer progresses. In LL mode the DMA overwrites this with the corresponding dword of the LL element. - DMA.." repeat.end repeat 8. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 )(list 0x0 0x200 0x400 0x600 0x800 0xA00 0xC00 0xE00 ) group.long ($2+0x210+0xC8000)++0x3 line.long 0x0 "DMA_SAR_HIGH_OFF_WRCH_$1,DMA Write SAR High Register." hexmask.long 0x0 0.--31. 1. "SRC_ADDR_REG_HIGH,Source Address Register (Higher 32 bits). In LL mode the DMA overwrites this with the corresponding dword of the LL element. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" repeat.end repeat 8. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 )(list 0x0 0x200 0x400 0x600 0x800 0xA00 0xC00 0xE00 ) group.long ($2+0x214+0xC8000)++0x3 line.long 0x0 "DMA_DAR_LOW_OFF_WRCH_$1,DMA Write DAR Low Register." hexmask.long 0x0 0.--31. 1. "DST_ADDR_REG_LOW,Destination Address Register (Lower 32 bits). Indicates the next address to be written to. The DMA increments the DAR as the DMA transfer progresses. In LL mode the DMA overwrites this with the corresponding dword of the LL element. -.." repeat.end repeat 8. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 )(list 0x0 0x200 0x400 0x600 0x800 0xA00 0xC00 0xE00 ) group.long ($2+0x218+0xC8000)++0x3 line.long 0x0 "DMA_DAR_HIGH_OFF_WRCH_$1,DMA Write DAR High Register." hexmask.long 0x0 0.--31. 1. "DST_ADDR_REG_HIGH,Destination Address Register (Higher 32 bits). In LL mode the DMA overwrites this with the corresponding dword of the LL element. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" repeat.end repeat 8. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 )(list 0x0 0x200 0x400 0x600 0x800 0xA00 0xC00 0xE00 ) group.long ($2+0x21C+0xC8000)++0x3 line.long 0x0 "DMA_LLP_LOW_OFF_WRCH_$1,DMA Write Linked List Pointer Low Register." hexmask.long 0x0 0.--31. 1. "LLP_LOW,Lower bits of the address of the linked list transfer list in local memory. Used in linked list mode only. Updated by the DMA to point to the next element in the transfer list after the previous element is consumed. - When the current element is.." repeat.end repeat 8. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 )(list 0x0 0x200 0x400 0x600 0x800 0xA00 0xC00 0xE00 ) group.long ($2+0x220+0xC8000)++0x3 line.long 0x0 "DMA_LLP_HIGH_OFF_WRCH_$1,DMA Write Linked List Pointer High Register." hexmask.long 0x0 0.--31. 1. "LLP_HIGH,Upper 32 bits of the address of the linked list transfer list in local memory. Used in linked list mode only. Updated by the DMA to point to the next element in the transfer list as elements are consumed. Note: The access attributes of this.." repeat.end repeat 8. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 )(list 0x0 0x200 0x400 0x600 0x800 0xA00 0xC00 0xE00 ) group.long ($2+0x300+0xC8000)++0x3 line.long 0x0 "DMA_CH_CONTROL1_OFF_RDCH_$1,DMA Read Channel Control 1 Register." bitfld.long 0x0 30.--31. "DMA_AT,Address Translation TLP Header Bit (AT) The DMA uses this TLP header field when generating MRd/MWr (not IMWr) TLPs. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" "0,1,2,3" bitfld.long 0x0 27.--29. "DMA_TC,Traffic Class TLP Header Bit (TC) The DMA uses this TLP header field when generating MRd/MWr (not IMWr) TLPs. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 26. "DMA_RESERVED5,Reserved. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" "0,1" bitfld.long 0x0 25. "DMA_RO,Relaxed Ordering TLP Header Bit (RO) The DMA uses this TLP header field when generating MRd/MWr (not IMWr) TLPs. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" "0,1" newline bitfld.long 0x0 24. "DMA_NS_SRC,Source No Snoop TLP Header Bit (DMA_NS_SRC). The DMA uses this TLP header field when generating MRd (SAR addressing space) (not IMWr) TLPs. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" "0,1" bitfld.long 0x0 23. "DMA_NS_DST,Destination No Snoop TLP Header Bit (DMA_NS_DST). The DMA uses this TLP header field when generating MWr (DAR addressing space) (not IMWr) TLPs. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" "0,1" newline bitfld.long 0x0 22. "DMA_MEM_TYPE,Master AXI ACE-Lite Cache Coherency Control. This field sets the DMA channel memory type of the address space of the data transfer as follows: - 0x0:peripheral type - 0x1:memory type For more details see 'ACE-Lite Features and Limitations'.." "peripheral type,memory type" hexmask.long.byte 0x0 17.--21. 1. "DMA_RESERVED2,Reserved. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" newline hexmask.long.byte 0x0 12.--16. 1. "DMA_FUNC_NUM,Function Number (FN). The controller uses this field when generating the requester ID for the MRd/MWr DMA TLP. When you have enabled SR-IOV then this field is ignored if you have set the VFE field in the 'DMA Read Channel Control 2.." bitfld.long 0x0 10.--11. "DMA_RESERVED1,Reserved. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" "0,1,2,3" newline bitfld.long 0x0 9. "LLE,Linked List Enable (LLE). - 0: Disable linked list operation - 1: Enable linked list operation Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" "Disable linked list operation,Enable linked list operation" bitfld.long 0x0 8. "CCS,Consumer Cycle State (CCS). Used in linked list mode only. It is used to synchronize the producer (software) and the consumer (DMA). For more details see 'PCS-CCS-CB-TCB Producer-Consumer Synchronization'. You must initialize this bit. The DMA.." "0,1" newline bitfld.long 0x0 7. "DMA_RESERVED0,Reserved. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" "0,1" bitfld.long 0x0 5.--6. "CS,Channel Status (CS). The channel status bits identify the current operational state of the DMA channel. The operation state encoding for each DMA channel is a s follows: - 00: Reserved - 01: Running. This channel is active and transferring data. - 10:.." "Reserved,Running,?,?" newline bitfld.long 0x0 4. "RIE,Remote Interrupt Enable (RIE). You must set this bit to enable the generation of the Done or Abort Remote interrupts. For more details see 'Interrupts and Error Handling'. In LL mode the DMA overwrites this with the RIE of the LL element. The RIE.." "0,1" bitfld.long 0x0 3. "LIE,Local Interrupt Enable (LIE). You must set this bit to enable the generation of the Done or Abort Local interrupts. For more details see 'Interrupts and Error Handling'. In LL mode the DMA overwrites this with the LIE of the LL element. The LIE bit.." "0,1" newline bitfld.long 0x0 2. "LLP,Load Link Pointer (LLP). Used in linked list mode only. Indicates that this linked list element is a link element and its LL element pointer dwords are pointing to the next (non-contiguous) element. The DMA loads this field with the LLP of the.." "0,1" bitfld.long 0x0 1. "TCB,Toggle Cycle Bit (TCB). Indicates to the DMA to toggle its interpretation of the CB. Used in linked list mode only. It is used to synchronize the producer (software) and the consumer (DMA). For more details see 'PCS-CCS-CB-TCB Producer-Consumer.." "0,1" newline bitfld.long 0x0 0. "CB,Cycle Bit (CB). Used in linked list mode only. It is used to synchronize the producer (software) and the consumer (DMA). For more details see 'PCS-CCS-CB-TCB Producer-Consumer Synchronization'. The DMA loads this field with the CB of the linked list.." "0,1" repeat.end repeat 8. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 )(list 0x0 0x200 0x400 0x600 0x800 0xA00 0xC00 0xE00 ) group.long ($2+0x308+0xC8000)++0x3 line.long 0x0 "DMA_TRANSFER_SIZE_OFF_RDCH_$1,DMA Read Transfer Size Register." hexmask.long 0x0 0.--31. 1. "DMA_TRANSFER_SIZE,DMA Transfer Size. You program this register with the size of the DMA transfer. The maximum DMA transfer size is 4Gbytes. The minimum transfer size is one byte (0x1). This field is automatically decremented by the DMA as the DMA read.." repeat.end repeat 8. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 )(list 0x0 0x200 0x400 0x600 0x800 0xA00 0xC00 0xE00 ) group.long ($2+0x30C+0xC8000)++0x3 line.long 0x0 "DMA_SAR_LOW_OFF_RDCH_$1,DMA Read SAR Low Register." hexmask.long 0x0 0.--31. 1. "SRC_ADDR_REG_LOW,Source Address Register (Lower 32 bits). Indicates the next address to be read from. The DMA increments the SAR as the DMA transfer progresses. In LL mode the DMA overwrites this with the corresponding dword of the LL element. - DMA.." repeat.end repeat 8. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 )(list 0x0 0x200 0x400 0x600 0x800 0xA00 0xC00 0xE00 ) group.long ($2+0x310+0xC8000)++0x3 line.long 0x0 "DMA_SAR_HIGH_OFF_RDCH_$1,DMA Read SAR High Register." hexmask.long 0x0 0.--31. 1. "SRC_ADDR_REG_HIGH,Source Address Register (Higher 32 bits). In LL mode the DMA overwrites this with the corresponding dword of the LL element. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" repeat.end repeat 8. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 )(list 0x0 0x200 0x400 0x600 0x800 0xA00 0xC00 0xE00 ) group.long ($2+0x314+0xC8000)++0x3 line.long 0x0 "DMA_DAR_LOW_OFF_RDCH_$1,DMA Read DAR Low Register." hexmask.long 0x0 0.--31. 1. "DST_ADDR_REG_LOW,Destination Address Register (Lower 32 bits). Indicates the next address to be written to. The DMA increments the DAR as the DMA transfer progresses. In LL mode the DMA overwrites this with the corresponding dword of the LL element. -.." repeat.end repeat 8. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 )(list 0x0 0x200 0x400 0x600 0x800 0xA00 0xC00 0xE00 ) group.long ($2+0x318+0xC8000)++0x3 line.long 0x0 "DMA_DAR_HIGH_OFF_RDCH_$1,DMA Read DAR High Register." hexmask.long 0x0 0.--31. 1. "DST_ADDR_REG_HIGH,Destination Address Register (Higher 32 bits). In LL mode the DMA overwrites this with the corresponding dword of the LL element. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" repeat.end repeat 8. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 )(list 0x0 0x200 0x400 0x600 0x800 0xA00 0xC00 0xE00 ) group.long ($2+0x31C+0xC8000)++0x3 line.long 0x0 "DMA_LLP_LOW_OFF_RDCH_$1,DMA Read Linked List Pointer Low Register." hexmask.long 0x0 0.--31. 1. "LLP_LOW,Lower bits of the address of the linked list transfer list in local memory. Used in linked list mode only. Updated by the DMA to point to the next element in the transfer list after the previous element is consumed. - When the current element is.." repeat.end repeat 8. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 )(list 0x0 0x200 0x400 0x600 0x800 0xA00 0xC00 0xE00 ) group.long ($2+0x320+0xC8000)++0x3 line.long 0x0 "DMA_LLP_HIGH_OFF_RDCH_$1,DMA Read Linked List Pointer High Register." hexmask.long 0x0 0.--31. 1. "LLP_HIGH,Upper 32 bits of the address of the linked list transfer list in local memory. Used in linked list mode only. Updated by the DMA to point to the next element in the transfer list as elements are consumed. Note: The access attributes of this.." repeat.end tree.end tree "PF0_ATU_CAP (ATU Por Logic Structure)" repeat 8. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 )(list 0x0 0x200 0x400 0x600 0x800 0xA00 0xC00 0xE00 ) group.long ($2+0xC0000)++0x3 line.long 0x0 "IATU_REGION_CTRL_1_OFF_OUTBOUND_$1,iATU Region Control 1 Register." bitfld.long 0x0 20. "CTRL_1_FUNC_NUM,Function Number. - When the address of an outbound TLP is matched to this region and the FUNC_BYPASS field in the 'iATU Control 2 Register' is '0' then the function number used in generating the function part of the requester ID (RID).." "0,1" newline bitfld.long 0x0 13. "INCREASE_REGION_SIZE,Increase the maximum ATU Region size. When set the maximum ATU Region size is determined by CX_ATU_MAX_REGION_SIZE. When clear the maximum ATU Region size is 4 GB (default). Note: This register field is sticky." "0,1" newline bitfld.long 0x0 9.--10. "ATTR,When the address of an outbound TLP is matched to this region then the ATTR field of the TLP is changed to the value in this register. Note: This register field is sticky." "0,1,2,3" newline bitfld.long 0x0 8. "TD,This is a reserved field. Do not use. Note: This register field is sticky." "0,1" newline bitfld.long 0x0 5.--7. "TC,When the address of an outbound TLP is matched to this region then the TC field of the TLP is changed to the value in this register. Note: This register field is sticky." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x0 0.--4. 1. "TYPE,When the address of an outbound TLP is matched to this region then the TYPE field of the TLP is changed to the value in this register. Note: This register field is sticky." repeat.end repeat 8. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 )(list 0x0 0x200 0x400 0x600 0x800 0xA00 0xC00 0xE00 ) group.long ($2+0x4+0xC0000)++0x3 line.long 0x0 "IATU_REGION_CTRL_2_OFF_OUTBOUND_$1,iATU Region Control 2 Register." bitfld.long 0x0 31. "REGION_EN,Region Enable. This bit must be set to '1' for address translation to take place. Note: This register field is sticky." "0,1" newline bitfld.long 0x0 29. "INVERT_MODE,Invert Mode. When set the address matching region is inverted. Therefore an address match occurs when the untranslated address is in the region outside the defined range (Base Address to Limit Address). Note: This register field is sticky." "0,1" newline bitfld.long 0x0 28. "CFG_SHIFT_MODE,CFG Shift Mode. The iATU uses bits [27:12] of the untranslated address (on the XALI0/1/2 interface or AXI slave interface address) to form the BDF number of the outgoing CFG TLP. This supports the Enhanced Configuration Address Mapping.." "0,1" newline bitfld.long 0x0 27. "DMA_BYPASS,DMA Bypass Mode. Allows request TLPs which are initiated by the DMA controller to pass through the iATU untranslated. Note: This field is reserved for the SW product. You must set it to '0'. Note: This register field is sticky." "0,1" newline bitfld.long 0x0 23. "HEADER_SUBSTITUTE_EN,Header Substitute Enable. When enabled and region address is matched the iATU fully substitutes bytes 8-11 (for 3 DWORD header) or bytes 12-15 (for 4 DWORD header) of the outbound TLP header with the contents of the LWR_TARGET_RW.." "LWR_TARGET_RW in the..,LWR_TARGET_RW in the.." newline bitfld.long 0x0 22. "INHIBIT_PAYLOAD,Inhibit TLP Payload Data for TLP's in Matched Region; assign iATU region to be TLP without data. When enabled and region address is matched the iATU marks all TLPs as having no payload data by forcing the TLP header Fmt[1] bit =0.." "Fmt[1] =0/1 so that TLPs with or without data..,Fmt[1] =0 so that only TLP type without data is.." newline bitfld.long 0x0 21. "TLP_HEADER_FIELDS_BYPASS,TLP Header Fields Translation Bypass. In this mode header fields of the translated TLP is taken from your application transmit interface or if AMBA is configured from the AMBA sideband bus (slv_awmisc_info) and not from the.." "0,1" newline bitfld.long 0x0 20. "SNP,Serialize Non-Posted Requests. In this mode when the AXI Bridge is populated same AXI ID Non-Posted Read/Write Requests are transmitted on the wire if there are no other same ID Non-Posted Requests outstanding. Note: This register field is sticky." "0,1" newline bitfld.long 0x0 19. "FUNC_BYPASS,Function Number Translation Bypass. In this mode the function number of the translated TLP is taken from your application transmit interface and not from the CTRL_1_FUNC_NUM field of the 'iATU Control 1 Register' or the VF_NUMBER field of.." "0,1" newline bitfld.long 0x0 16. "TAG_SUBSTITUTE_EN,TAG Substitute Enable. When enabled and region address is matched the iATU substitutes the TAG field of the outbound TLP header with the contents of the TAG field in this register. The expected usage scenario is translation from AXI.." "0,1" newline hexmask.long.byte 0x0 8.--15. 1. "TAG,TAG. The substituted TAG field (byte 6) in the outgoing TLP header when TAG_SUBSTITUTE_EN is set. Note: This register field is sticky." newline hexmask.long.byte 0x0 0.--7. 1. "MSG_CODE,MSG TLPs (Message Code). When the address of an outbound TLP is matched to this region and the translated TLP TYPE field is Msg or MsgD; then the message field of the TLP is changed to the value in this register. Memory TLPs: (ST;Steering Tag)." repeat.end repeat 8. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 )(list 0x0 0x200 0x400 0x600 0x800 0xA00 0xC00 0xE00 ) group.long ($2+0x8+0xC0000)++0x3 line.long 0x0 "IATU_LWR_BASE_ADDR_OFF_OUTBOUND_$1,iATU Lower Base Address Register. The CX_ATU_MIN_REGION_SIZE configuration parameter (Value Range: 4 kB. 8 kB. 16 kB. 32 kB. 64 kB defaults to 64 kB) specifies the minimum size of an address translation region. For.." hexmask.long.tbyte 0x0 12.--31. 1. "LWR_BASE_RW,Forms bits [31:n] of the start address of the address region to be translated. n is log2(CX_ATU_MIN_REGION_SIZE) Note: This register field is sticky." newline hexmask.long.word 0x0 0.--11. 1. "LWR_BASE_HW,Forms bits [n-1:0] of the start address of the address region to be translated. The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary so these bits are always 0. A write to this location is ignored by the PCIe controller." repeat.end repeat 8. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 )(list 0x0 0x200 0x400 0x600 0x800 0xA00 0xC00 0xE00 ) group.long ($2+0xC+0xC0000)++0x3 line.long 0x0 "IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_$1,iATU Upper Base Address Register." hexmask.long 0x0 0.--31. 1. "UPPER_BASE_RW,Forms bits [63:32] of the start (and end) address of the address region to be translated. In systems with a 32-bit address space this register is not used and therefore writing to this register has no effect. Note: This register field is.." repeat.end repeat 8. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 )(list 0x0 0x200 0x400 0x600 0x800 0xA00 0xC00 0xE00 ) group.long ($2+0x10+0xC0000)++0x3 line.long 0x0 "IATU_LIMIT_ADDR_OFF_OUTBOUND_$1,iATU Limit Address Register." hexmask.long.tbyte 0x0 12.--31. 1. "LIMIT_ADDR_RW,Forms upper bits of the end address of the address region to be translated. Note: This register field is sticky." newline hexmask.long.word 0x0 0.--11. 1. "LIMIT_ADDR_HW,Forms lower bits of the end address of the address region to be translated. The end address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary so these bits are always all ones. A write to this location is ignored by the PCIe.." repeat.end repeat 8. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 )(list 0x0 0x200 0x400 0x600 0x800 0xA00 0xC00 0xE00 ) group.long ($2+0x14+0xC0000)++0x3 line.long 0x0 "IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_$1,iATU Lower Target Address Register." hexmask.long 0x0 0.--31. 1. "LWR_TARGET_RW_OUTBOUND,When HEADER_SUBSTITUTE_EN in IATU_REGION_CTRL_2_OFF_OUTBOUND_ is '0' (normal operation): - LWR_TARGET_RW[31:n] forms MSB's of the Lower Target part of the new address of the translated region; - LWR_TARGET_RW[n-1:0] are not used." repeat.end repeat 8. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 )(list 0x0 0x200 0x400 0x600 0x800 0xA00 0xC00 0xE00 ) group.long ($2+0x18+0xC0000)++0x3 line.long 0x0 "IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_$1,iATU Upper Target Address Register." hexmask.long 0x0 0.--31. 1. "UPPER_TARGET_RW,Forms bits [63:32] of the start address (Upper Target part) of the new address of the translated region. Note: This register field is sticky." repeat.end repeat 8. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 )(list 0x0 0x200 0x400 0x600 0x800 0xA00 0xC00 0xE00 ) group.long ($2+0x1C+0xC0000)++0x3 line.long 0x0 "IATU_REGION_CTRL_3_OFF_OUTBOUND_$1,iATU Region Control 3 Register." bitfld.long 0x0 31. "VF_ACTIVE,Virtual Function Active. Indicates that all of the outbound accesses are from virtual functions. For more details see VF_ACTIVE field. Note: This register field is sticky." "0,1" newline hexmask.long 0x0 3.--30. 1. "RSVDP_VF_NUMBER,Reserved for future use." newline bitfld.long 0x0 0.--2. "VF_NUMBER,Virtual Function Number. When the address of an outbound TLP is matched to this region and the FUNC_BYPASS field in the 'iATU Control 2 Register' is '0' then this field used in generating the Function part of the requester ID (RID) field of.." "0,1,2,3,4,5,6,7" repeat.end repeat 8. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 )(list 0x0 0x200 0x400 0x600 0x800 0xA00 0xC00 0xE00 ) group.long ($2+0x100+0xC0000)++0x3 line.long 0x0 "IATU_REGION_CTRL_1_OFF_INBOUND_$1,iATU Region Control 1 Register." bitfld.long 0x0 20. "CTRL_1_FUNC_NUM,Function Number. - MEM-I/O: When the Address and BAR matching logic in the controller indicate that a MEM-I/O transaction matches a BAR in the function corresponding to this value then address translation proceeds. This check is only.." "?,When the destination function number as.." newline bitfld.long 0x0 13. "INCREASE_REGION_SIZE,Increase the maximum ATU Region size. When set the maximum ATU Region size is determined by CX_ATU_MAX_REGION_SIZE. When clear the maximum ATU Region size is 4 GB (default). Note: This register field is sticky." "0,1" newline bitfld.long 0x0 9.--10. "ATTR,When the ATTR field of an inbound TLP is matched to this value then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the 'ATTR Match Enable' bit of the 'iATU Control 2 Register' is.." "0,1,2,3" newline bitfld.long 0x0 8. "TD,When the TD field of an inbound TLP is matched to this value then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the 'TD Match Enable' bit of the 'iATU Control 2 Register' is set." "0,1" newline bitfld.long 0x0 5.--7. "TC,When the TC field of an inbound TLP is matched to this value then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the 'TC Match Enable' bit of the 'iATU Control 2 Register' is set." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x0 0.--4. 1. "TYPE,When the TYPE field of an inbound TLP is matched to this value then address translation proceeds (when all other enabled field-matches are successful). Note: This register field is sticky." repeat.end repeat 8. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 )(list 0x0 0x200 0x400 0x600 0x800 0xA00 0xC00 0xE00 ) group.long ($2+0x104+0xC0000)++0x3 line.long 0x0 "IATU_REGION_CTRL_2_OFF_INBOUND_$1,iATU Region Control 2 Register." bitfld.long 0x0 31. "REGION_EN,Region Enable. This bit must be set to '1' for address translation to take place. Note: This register field is sticky." "0,1" newline bitfld.long 0x0 30. "MATCH_MODE,Match Mode. Determines Inbound matching mode for TLPs. The mode depends on the type of TLP that is received as follows: For MEM-I/O TLPs this field is interpreted as follows: - 0: Address Match Mode. The iATU operates using addresses as in.." "Address Match Mode,Vendor ID Match Mode" newline bitfld.long 0x0 29. "INVERT_MODE,Invert Mode. When set the address matching region is inverted. Therefore an address match occurs when the untranslated address is in the region outside the defined range (Base Address to Limit Address). Note: This register field is sticky." "0,1" newline bitfld.long 0x0 28. "CFG_SHIFT_MODE,CFG Shift Mode. This is useful for CFG transactions where the PCIe configuration mechanism maps bits [27:12] of the address to the bus/device and function number. This allows a CFG configuration space to be located in any 256MB window of.." "0,1" newline bitfld.long 0x0 27. "FUZZY_TYPE_MATCH_CODE,Fuzzy Type Match Mode. When enabled the iATU relaxes the matching of the TLP TYPE field against the expected TYPE field so that - CfgRd0 and CfgRd1 TLPs are seen as identical. Similarly with CfgWr0 and CfgWr1. - MWr MRd and MRdLk.." "0,1" newline bitfld.long 0x0 26. "VFBAR_MATCH_MODE_EN,VF BAR Match Mode enable. When set Virtual Function BAR matching is used which allows all VFs in a PF which match a BAR to be matched with a single ATU region. Note: This register field is sticky." "0,1" newline bitfld.long 0x0 24.--25. "RESPONSE_CODE,Response Code. Defines the type of response to give for accesses matching this region. This overrides the normal RADM filter response. Note that this feature is not available for any region where Single Address Location Translate is.." "Normal RADM filter response is used,Unsupported request,?,?" newline bitfld.long 0x0 23. "SINGLE_ADDR_LOC_TRANS_EN,Single Address Location Translate Enable. When enabled Rx TLPs can be translated to a single address location as determined by the target address register of the iATU region. The main usage scenario is translation of Messages.." "0,1" newline bitfld.long 0x0 21. "MSG_CODE_MATCH_EN,Message Code Match Enable (Msg TLPS). Ensures that a successful message Code TLP field comparison match (see Message Code field of the 'iATU Control 2 Register') occurs (in MSG transactions) for address translation to proceed. ST Match.." "0,1" newline bitfld.long 0x0 20. "VF_MATCH_EN,Virtual Function Number Match Enable. Ensures that a successful Virtual Function Number TLP field comparison match (see Virtual Function Number field of the 'iATU Control 3 Register') occurs (in MEM-I/O transactions) for address translation.." "0,1" newline bitfld.long 0x0 19. "FUNC_NUM_MATCH_EN,Function Number Match Enable. Ensures that a successful Function Number TLP field comparison match (see Function Number field of the 'iATU Control 1 Register') occurs (in MEM-I/O and CFG0/CFG1 transactions) for address translation to.." "0,1" newline bitfld.long 0x0 16. "ATTR_MATCH_EN,ATTR Match Enable. Ensures that a successful ATTR TLP field comparison match (see ATTR field of the 'iATU Control 1 Register') occurs for address translation to proceed. Note: This register field is sticky." "0,1" newline bitfld.long 0x0 15. "TD_MATCH_EN,TD Match Enable. Ensures that a successful TD TLP field comparison match (see TD field of the 'iATU Control 1 Register') occurs for address translation to proceed. Note: This register field is sticky." "0,1" newline bitfld.long 0x0 14. "TC_MATCH_EN,TC Match Enable. Ensures that a successful TC TLP field comparison match (see TC field of the 'iATU Control 1 Register') occurs for address translation to proceed. Note: This register field is sticky." "0,1" newline bitfld.long 0x0 13. "MSG_TYPE_MATCH_MODE,Message Type Match Mode. When enabled and if single address location translate enable is set then inbound TLPs of type MSG/MSGd which match the type field of the iatu_region_ctrl_1_OFF_inbound register (=>TYPE[4:3]=2'b10) will be.." "0,1" newline bitfld.long 0x0 8.--10. "BAR_NUM,BAR Number. When the BAR number of an inbound MEM or IO TLP ' that is matched by the normal internal BAR address matching mechanism ' is the same as this field address translation proceeds (when all other enabled field-matches are successful)." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x0 0.--7. 1. "MSG_CODE,MSG TLPs: (Message Code). When the TYPE field of an inbound Msg/MsgD TLP is matched to this value then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the 'Message Code Match.." repeat.end repeat 8. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 )(list 0x0 0x200 0x400 0x600 0x800 0xA00 0xC00 0xE00 ) group.long ($2+0x108+0xC0000)++0x3 line.long 0x0 "IATU_LWR_BASE_ADDR_OFF_INBOUND_$1,iATU Lower Base Address Register. The CX_ATU_MIN_REGION_SIZE configuration parameter (Value Range: 4 kB. 8 kB. 16 kB. 32 kB. 64 kB defaults to 64 kB) specifies the minimum size of an address translation region. For.." hexmask.long.tbyte 0x0 12.--31. 1. "LWR_BASE_RW,Forms bits [31:n] of the start address of the address region to be translated. n is log2(CX_ATU_MIN_REGION_SIZE) Note: This register field is sticky." newline hexmask.long.word 0x0 0.--11. 1. "LWR_BASE_HW,Forms bits [n-1:0] of the start address of the address region to be translated. The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary so these bits are always 0. A write to this location is ignored by the PCIe controller." repeat.end repeat 8. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 )(list 0x0 0x200 0x400 0x600 0x800 0xA00 0xC00 0xE00 ) group.long ($2+0x10C+0xC0000)++0x3 line.long 0x0 "IATU_UPPER_BASE_ADDR_OFF_INBOUND_$1,iATU Upper Base Address Register." hexmask.long 0x0 0.--31. 1. "UPPER_BASE_RW,Forms bits [63:32] of the start (and end) address of the address region to be translated. Note: This register field is sticky." repeat.end repeat 8. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 )(list 0x0 0x200 0x400 0x600 0x800 0xA00 0xC00 0xE00 ) group.long ($2+0x110+0xC0000)++0x3 line.long 0x0 "IATU_LIMIT_ADDR_OFF_INBOUND_$1,iATU Limit Address Register." hexmask.long.tbyte 0x0 12.--31. 1. "LIMIT_ADDR_RW,Forms upper bits of the end address of the address region to be translated. Note: This register field is sticky." newline hexmask.long.word 0x0 0.--11. 1. "LIMIT_ADDR_HW,Forms lower bits of the end address of the address region to be translated. The end address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary so these bits are always all ones. A write to this location is ignored by the PCIe.." repeat.end repeat 8. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 )(list 0x0 0x200 0x400 0x600 0x800 0xA00 0xC00 0xE00 ) group.long ($2+0x114+0xC0000)++0x3 line.long 0x0 "IATU_LWR_TARGET_ADDR_OFF_INBOUND_$1,iATU Lower Target Address Register." hexmask.long.tbyte 0x0 12.--31. 1. "LWR_TARGET_RW,Forms MSB's of the Lower Target part of the new address of the translated region. These bits are always '0'. - Field size depends on log2(CX_ATU_MIN_REGION_SIZE) in address match mode. - Field size depends on log2(BAR_MASK+1) in BAR match.." newline hexmask.long.word 0x0 0.--11. 1. "LWR_TARGET_HW,Forms the LSB's of the Lower Target part of the new address of the translated region. The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary (in address match mode); and to the Bar size boundary (in BAR match mode) so.." repeat.end repeat 8. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 )(list 0x0 0x200 0x400 0x600 0x800 0xA00 0xC00 0xE00 ) group.long ($2+0x118+0xC0000)++0x3 line.long 0x0 "IATU_UPPER_TARGET_ADDR_OFF_INBOUND_$1,iATU Upper Target Address Register." hexmask.long 0x0 0.--31. 1. "UPPER_TARGET_RW,Forms bits [63:32] of the start address (Upper Target part) of the new address of the translated region. In systems with a 32-bit address space this register is not used and therefore writing to this register has no effect. Note: This.." repeat.end repeat 8. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 )(list 0x0 0x200 0x400 0x600 0x800 0xA00 0xC00 0xE00 ) group.long ($2+0x11C+0xC0000)++0x3 line.long 0x0 "IATU_REGION_CTRL_3_OFF_INBOUND_$1,iATU Region Control 3 Register." rbitfld.long 0x0 31. "VF_ACTIVE,Reserved. Not used." "0,1" newline hexmask.long 0x0 3.--30. 1. "RSVDP_VF_NUMBER,Reserved for future use." newline bitfld.long 0x0 0.--2. "VF_NUMBER,Virtual Function Number. When the Address and BAR matching logic in the controller indicates that a MEM-I/O transaction matches a BAR in the virtual function corresponding to this value then address translation proceeds. This check is only.." "0,1,2,3,4,5,6,7" repeat.end tree.end tree "PF0_PORT_LOGIC (Port Logic)" group.long (0x0+0x700)++0x27 line.long 0x0 "ACK_LATENCY_TIMER_OFF,Ack Latency Timer and Replay Timer Register." hexmask.long.word 0x0 16.--31. 1. "REPLAY_TIME_LIMIT,Replay Timer Limit. The replay timer expires when it reaches this limit. The controller initiates a replay upon reception of a NAK or when the replay timer expires. For more details see 'Transmit Replay'. You can modify the effective.." newline hexmask.long.word 0x0 0.--15. 1. "ROUND_TRIP_LATENCY_TIME_LIMIT,Ack Latency Timer Limit. The Ack latency timer expires when it reaches this limit. For more details see 'Ack Scheduling'. You can modify the effective timer limit with the TIMER_MOD_ACK_NAK field of the.." line.long 0x4 "VENDOR_SPEC_DLLP_OFF,Vendor Specific DLLP Register." hexmask.long 0x4 0.--31. 1. "VENDOR_SPEC_DLLP,Vendor Specific DLLP Register. Used to send a specific PCI Express DLLP. Your application writes the 8-bit DLLP Type and 24-bits of Payload data into this register then sets the field VENDOR_SPECIFIC_DLLP_REQ of PORT_LINK_CTRL_OFF to.." line.long 0x8 "PORT_FORCE_OFF,Port Force Link Register." hexmask.long.byte 0x8 24.--31. 1. "RSVDP_24,Reserved for future use." newline bitfld.long 0x8 23. "DO_DESKEW_FOR_SRIS,Use the transitions from TS2 to Logical Idle Symbol SKP OS to Logical Idle Symbol EIEOS to Logical Idle Symbol and FTS Sequence to SKP OS to do deskew instead of using received SKP OS or TS1 to TS2 transition if DO_DESKEW_FOR_SRIS.." "0,1" newline rbitfld.long 0x8 22. "RSVDP_22,Reserved for future use." "0,1" newline hexmask.long.byte 0x8 16.--21. 1. "LINK_STATE,Forced LTSSM State. The LTSSM state that the controller is forced to when you set the FORCE_EN bit (Force Link). LTSSM state encoding is defined by the lts_state variable in workspace/src/Layer1/smlh_ltssm.v. Note: This register field is sticky." newline bitfld.long 0x8 15. "FORCE_EN,Force Link. The controller supports a testing and debug capability to allow your software to force the LTSSM state machine into a specific state and to force the controller to transmit a specific Link Command. Asserting this bit triggers the.." "0,1" newline rbitfld.long 0x8 12.--14. "RSVDP_12,Reserved for future use." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x8 8.--11. 1. "FORCED_LTSSM,Forced Link Command. The link command that the controller is forced to transmit when you set FORCE_EN bit (Force Link). Link command encoding is defined by the ltssm_cmd variable in workspace/src/Layer1/smlh_ltssm.v. Note: This register.." newline hexmask.long.byte 0x8 0.--7. 1. "LINK_NUM,Link Number. Not used for endpoint. Not used for M-PCIe. Note: This register field is sticky." line.long 0xC "ACK_F_ASPM_CTRL_OFF,Ack Frequency and L0-L1 ASPM Control Register." rbitfld.long 0xC 31. "RSVDP_31,Reserved for future use." "0,1" newline bitfld.long 0xC 30. "ENTER_ASPM,ASPM L1 Entry Control. - 1: Controller enters ASPM L1 after a period in which it has been idle. - 0: Controller enters ASPM L1 only after idle period during which both receive and transmit are in L0s. Note: This register field is sticky." "Controller enters ASPM L1 only after idle period..,Controller enters ASPM L1 after a period in.." newline bitfld.long 0xC 27.--29. "L1_ENTRANCE_LATENCY,L1 Entrance Latency. Value range is: - 000: 1 us - 001: 2 us - 010: 4 us - 011: 8 us - 100: 16 us - 101: 32 us - 110 or 111: 64 us Note: Programming this timer with a value greater that 32us has no effect unless extended sync is used.." "0,1,2,3,4,5,6,7" newline bitfld.long 0xC 24.--26. "L0S_ENTRANCE_LATENCY,L0s Entrance Latency. Values correspond to: - 000: 1 us - 001: 2 us - 010: 3 us - 011: 4 us - 100: 5 us - 101: 6 us - 110 or 111: 7 us This field is applicable to STALL while in L0 for M-PCIe. Note: This register field is sticky." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0xC 16.--23. 1. "COMMON_CLK_N_FTS,Common Clock N_FTS. This is the N_FTS when common clock is used. The number of Fast Training Sequence ordered sets to be transmitted when transitioning from L0s to L0. The maximum number of FTS ordered-sets that a component can request.." newline hexmask.long.byte 0xC 8.--15. 1. "ACK_N_FTS,N_FTS. The number of Fast Training Sequence ordered sets to be transmitted when transitioning from L0s to L0. The maximum number of FTS ordered-sets that a component can request is 255. The controller does not support a value of zero; a value.." newline hexmask.long.byte 0xC 0.--7. 1. "ACK_FREQ,Ack Frequency. The controller accumulates the number of pending ACKs specified here (up to 255) before scheduling an ACK DLLP. - 0: Indicates that this Ack Frequency Counter feature is turned off. The controller generates a low-priority ACK.." line.long 0x10 "PORT_LINK_CTRL_OFF,Port Link Control Register." hexmask.long.byte 0x10 28.--31. 1. "RSVDP_28,Reserved for future use." newline bitfld.long 0x10 27. "TRANSMIT_LANE_REVERSALE_ENABLE,TRANSMIT_LANE_REVERSALE_ENABLE is an internally reserved field. Do not use. Note: This register field is sticky." "0,1" newline bitfld.long 0x10 26. "EXTENDED_SYNCH,EXTENDED_SYNCH is an internally reserved field. Do not use. Note: This register field is sticky." "0,1" newline bitfld.long 0x10 25. "CORRUPT_LCRC_ENABLE,CORRUPT_LCRC_ENABLE is an internally reserved field. Do not use. Note: This register field is sticky." "0,1" newline bitfld.long 0x10 24. "BEACON_ENABLE,BEACON_ENABLE is an internally reserved field. Do not use. Note: This register field is sticky." "0,1" newline hexmask.long.byte 0x10 16.--21. 1. "LINK_CAPABLE,Link Mode Enable. Sets the number of lanes in the link that you want to connect to the link partner. When you have unused lanes in your system then you must change the value in this register to reflect the number of lanes. You must also.." newline hexmask.long.byte 0x10 12.--15. 1. "RSVDP_12,Reserved for future use." newline hexmask.long.byte 0x10 8.--11. 1. "LINK_RATE,LINK_RATE is an internally reserved field. Do not use. Note: This register field is sticky." newline bitfld.long 0x10 7. "FAST_LINK_MODE,Fast Link Mode. Sets all internal LTSSM millisecond timers to Fast Mode for speeding up simulation. Forces the LTSSM training (link initialization) to use shorter time-outs and to link up faster. The default scaling factor can be changed.." "0,1" newline bitfld.long 0x10 6. "LINK_DISABLE,LINK_DISABLE is an internally reserved field. Do not use. Note: This register field is sticky." "0,1" newline bitfld.long 0x10 5. "DLL_LINK_EN,DLL Link Enable. Enables link initialization. When DLL Link Enable =0 the controller does not transmit InitFC DLLPs and does not establish a link. Note: This register field is sticky." "0,1" newline rbitfld.long 0x10 4. "RSVDP_4,Reserved for future use." "0,1" newline bitfld.long 0x10 3. "RESET_ASSERT,Reset Assert. Triggers a recovery and forces the LTSSM to the hot reset state (downstream port only). Note: This register field is sticky." "0,1" newline bitfld.long 0x10 2. "LOOPBACK_ENABLE,Loopback Enable. Turns on loopback. For more details see 'Loopback'. For M-PCIe to force the master to enter Digital Loopback mode you must set this field to '1' during Configuration.start state(initial discovery/configuration). M-PCIe.." "0,1" newline bitfld.long 0x10 1. "SCRAMBLE_DISABLE,Scramble Disable. Turns off data scrambling. Note: This register field is sticky." "0,1" newline bitfld.long 0x10 0. "VENDOR_SPECIFIC_DLLP_REQ,Vendor Specific DLLP Request. When software writes a '1' to this bit the controller transmits the DLLP contained in the VENDOR_SPEC_DLLP field of VENDOR_SPEC_DLLP_OFF. Reading from this self-clearing register field always.." "0,1" line.long 0x14 "LANE_SKEW_OFF,Lane Skew Register." bitfld.long 0x14 31. "DISABLE_LANE_TO_LANE_DESKEW,Disable Lane-to-Lane Deskew. Causes the controller to disable the internal Lane-to-Lane deskew logic. Note: This register field is sticky." "0,1" newline hexmask.long.byte 0x14 27.--30. 1. "IMPLEMENT_NUM_LANES,Implementation-specific Number of Lanes. Set the implementation-specific number of lanes. Allowed values are: - 4'b0000: 1 lane - 4'b0001: 2 lanes - 4'b0011: 4 lanes - 4'b0111: 8 lanes - 4'b1111: 16 lanes The number of lanes to be.." newline bitfld.long 0x14 26. "ELASTIC_BUFFER_MODE,Selects Elasticity Buffer operating mode: 0: Nominal Half Full Buffer mode 1: Nominal Empty Buffer Mode Note: This register field is sticky." "Nominal Half Full Buffer mode,Nominal Empty Buffer Mode" newline bitfld.long 0x14 25. "ACK_NAK_DISABLE,Ack/Nak Disable. Prevents the controller from sending ACK and NAK DLLPs. Note: This register field is sticky." "0,1" newline bitfld.long 0x14 24. "FLOW_CTRL_DISABLE,Flow Control Disable. Prevents the controller from sending FC DLLPs. Note: This register field is sticky." "0,1" newline hexmask.long.tbyte 0x14 0.--23. 1. "INSERT_LANE_SKEW,INSERT_LANE_SKEW is an internally reserved field. Do not use. Note: This register field is sticky." line.long 0x18 "TIMER_CTRL_MAX_FUNC_NUM_OFF,Timer Control and Max Function Number Register." rbitfld.long 0x18 31. "RSVDP_31,Reserved for future use." "0,1" newline bitfld.long 0x18 29.--30. "FAST_LINK_SCALING_FACTOR,Fast Link Timer Scaling Factor. Sets the scaling factor of LTSSM timer when FAST_LINK_MODE field in PORT_LINK_CTRL_OFF is set to '1'. - 0: Scaling Factor is 1024 (1ms is 1us *a) - 1: Scaling Factor is 256 (1ms is 4us) - 2:.." "Scaling Factor is 1024,Scaling Factor is 256,Scaling Factor is 64,Scaling Factor is 16" newline hexmask.long.byte 0x18 24.--28. 1. "UPDATE_FREQ_TIMER,UPDATE_FREQ_TIMER is an internally reserved field. Do not use. Note: This register field is sticky." newline hexmask.long.byte 0x18 19.--23. 1. "TIMER_MOD_ACK_NAK,Ack Latency Timer Modifier. Increases the timer value for the Ack latency timer in increments of 64 clock cycles. A value of '0' represents no modification to the timer value. For more details see the ROUND_TRIP_LATENCY_TIME_LIMIT.." newline hexmask.long.byte 0x18 14.--18. 1. "TIMER_MOD_REPLAY_TIMER,Replay Timer Limit Modifier. Increases the time-out value for the replay timer in increments of 64 clock cycles at Gen1 or Gen2 speed and in increments of 256 clock cycles at Gen3 speed. A value of '0' represents no modification.." newline hexmask.long.byte 0x18 8.--13. 1. "RSVDP_8,Reserved for future use." newline hexmask.long.byte 0x18 0.--7. 1. "MAX_FUNC_NUM,Maximum function number that can be used in a request. Configuration requests targeted at function numbers above this value are returned with UR (unsupported request). Note: This register field is sticky." line.long 0x1C "SYMBOL_TIMER_FILTER_1_OFF,Symbol Timer Register and Filter Mask 1 Register. The Filter Mask 1 Register modifies the RADM filtering and error handling rules. For more details. see the 'Receive Filtering' section. In each case. '0' applies the associated.." hexmask.long.word 0x1C 16.--31. 1. "MASK_RADM_1,Filter Mask 1. The Filter Mask 1 Register modifies the RADM filtering and error handling rules. For more details see the 'Receive Filtering' section. In each case '0' applies the associated filtering rule and '1' masks the associated.." newline bitfld.long 0x1C 15. "DISABLE_FC_WD_TIMER,Disable FC Watchdog Timer. Note: This register field is sticky." "0,1" newline hexmask.long.byte 0x1C 11.--14. 1. "EIDLE_TIMER,EIDLE_TIMER is an internally reserved field. Do not use. Note: This register field is sticky." newline hexmask.long.word 0x1C 0.--10. 1. "SKP_INT_VAL,SKP Interval Value. The number of symbol times to wait between transmitting SKP ordered sets. Note that the controller actually waits the number of symbol times in this register plus 1 between transmitting SKP ordered sets. Your application.." line.long 0x20 "FILTER_MASK_2_OFF,Filter Mask 2 Register. This register modifies the RADM filtering and error handling rules. For more details. see the 'Receive Filtering' section. In each case. '0' applies the associated filtering rule and '1' masks the associated.." hexmask.long 0x20 0.--31. 1. "MASK_RADM_2,Filter Mask 2. This field modifies the RADM filtering and error handling rules. For more details see the 'Receive Filtering' section. In each case '0' applies the associated filtering rule and '1' masks the associated filtering rule." line.long 0x24 "AMBA_MUL_OB_DECOMP_NP_SUB_REQ_CTRL_OFF,AMBA Multiple Outbound Decomposed NP SubRequests Control Register." hexmask.long 0x24 1.--31. 1. "RSVDP_1,Reserved for future use." newline bitfld.long 0x24 0. "OB_RD_SPLIT_BURST_EN,Enable AMBA Multiple Outbound Decomposed NP SubRequests. This bit when set to '0' disables the possibility of having multiple outstanding non-posted requests that were derived from decomposition of an outbound AMBA request. For more.." "0,1" rgroup.long (0x28+0x700)++0x13 line.long 0x0 "PL_DEBUG0_OFF,Debug Register 0" hexmask.long 0x0 0.--31. 1. "DEB_REG_0,The value on cxpl_debug_info[31:0]." line.long 0x4 "PL_DEBUG1_OFF,Debug Register 1" hexmask.long 0x4 0.--31. 1. "DEB_REG_1,The value on cxpl_debug_info[63:32]." line.long 0x8 "TX_P_FC_CREDIT_STATUS_OFF,Transmit Posted FC Credit Status" hexmask.long.word 0x8 20.--31. 1. "RSVDP_TX_P_FC_CREDIT_STATUS,Reserved for future use." newline hexmask.long.byte 0x8 12.--19. 1. "TX_P_HEADER_FC_CREDIT,Transmit Posted Header FC Credits. The posted Header credits advertised by the receiver at the other end of the link updated with each UpdateFC DLLP. Default value depends on the number of advertised credits for header and data.." newline hexmask.long.word 0x8 0.--11. 1. "TX_P_DATA_FC_CREDIT,Transmit Posted Data FC Credits. The posted Data credits advertised by the receiver at the other end of the link updated with each UpdateFC DLLP. Default value depends on the number of advertised credits for header and data Scaled.." line.long 0xC "TX_NP_FC_CREDIT_STATUS_OFF,Transmit Non-Posted FC Credit Status" hexmask.long.word 0xC 20.--31. 1. "RSVDP_TX_NP_FC_CREDIT_STATUS,Reserved for future use." newline hexmask.long.byte 0xC 12.--19. 1. "TX_NP_HEADER_FC_CREDIT,Transmit Non-Posted Header FC Credits. The non-posted Header credits advertised by the receiver at the other end of the link updated with each UpdateFC DLLP. Default value depends on the number of advertised credits for header and.." newline hexmask.long.word 0xC 0.--11. 1. "TX_NP_DATA_FC_CREDIT,Transmit Non-Posted Data FC Credits. The non-posted Data credits advertised by the receiver at the other end of the link updated with each UpdateFC DLLP. Default value depends on the number of advertised credits for header and data.." line.long 0x10 "TX_CPL_FC_CREDIT_STATUS_OFF,Transmit Completion FC Credit Status" hexmask.long.word 0x10 20.--31. 1. "RSVDP_TX_CPL_FC_CREDIT_STATUS,Reserved for future use." newline hexmask.long.byte 0x10 12.--19. 1. "TX_CPL_HEADER_FC_CREDIT,Transmit Completion Header FC Credits. The Completion Header credits advertised by the receiver at the other end of the link updated with each UpdateFC DLLP. Default value depends on the number of advertised credits for header.." newline hexmask.long.word 0x10 0.--11. 1. "TX_CPL_DATA_FC_CREDIT,Transmit Completion Data FC Credits. The Completion Data credits advertised by the receiver at the other end of the link updated with each UpdateFC DLLP. Default value depends on the number of advertised credits for header and data.." group.long (0x3C+0x700)++0x3 line.long 0x0 "QUEUE_STATUS_OFF,Queue Status" bitfld.long 0x0 31. "TIMER_MOD_FLOW_CONTROL_EN,FC Latency Timer Override Enable. When this bit is set the value from the 'FC Latency Timer Override Value' field in this register will override the FC latency timer value that the controller calculates according to the PCIe.." "0,1" newline rbitfld.long 0x0 29.--30. "RSVDP_29,Reserved for future use." "0,1,2,3" newline hexmask.long.word 0x0 16.--28. 1. "TIMER_MOD_FLOW_CONTROL,FC Latency Timer Override Value. When you set the 'FC Latency Timer Override Enable' in this register the value in this field will override the FC latency timer value that the controller calculates according to the PCIe.." newline rbitfld.long 0x0 13. "RX_SERIALIZATION_Q_NON_EMPTY,Receive Serialization Queue Not Empty. Indicates there is data in the serialization queue." "0,1" newline hexmask.long.word 0x0 4.--12. 1. "RSVDP_4,Reserved for future use." newline bitfld.long 0x0 3. "RX_QUEUE_OVERFLOW,Receive Credit Queue Overflow. Indicates insufficient buffer space available to write to the P/NP/CPL credit queue." "0,1" newline rbitfld.long 0x0 2. "RX_QUEUE_NON_EMPTY,Receive Credit Queue Not Empty. Indicates there is data in one or more of the receive buffers." "0,1" newline rbitfld.long 0x0 1. "TX_RETRY_BUFFER_NE,Transmit Retry Buffer Not Empty. Indicates that there is data in the transmit retry buffer." "0,1" newline rbitfld.long 0x0 0. "RX_TLP_FC_CREDIT_NON_RETURN,Received TLP FC Credits Not Returned. Indicates that the controller has received a TLP but has not yet sent an UpdateFC DLLP indicating that the credits for that TLP have been restored by the receiver at the other end of the.." "0,1" rgroup.long (0x40+0x700)++0x7 line.long 0x0 "VC_TX_ARBI_1_OFF,VC Transmit Arbitration Register 1" hexmask.long.byte 0x0 24.--31. 1. "WRR_WEIGHT_VC_3,WRR Weight for VC3. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R" newline hexmask.long.byte 0x0 16.--23. 1. "WRR_WEIGHT_VC_2,WRR Weight for VC2. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R" newline hexmask.long.byte 0x0 8.--15. 1. "WRR_WEIGHT_VC_1,WRR Weight for VC1. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R" newline hexmask.long.byte 0x0 0.--7. 1. "WRR_WEIGHT_VC_0,WRR Weight for VC0. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R" line.long 0x4 "VC_TX_ARBI_2_OFF,VC Transmit Arbitration Register 2" hexmask.long.byte 0x4 24.--31. 1. "WRR_WEIGHT_VC_7,WRR Weight for VC7. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R" newline hexmask.long.byte 0x4 16.--23. 1. "WRR_WEIGHT_VC_6,WRR Weight for VC6. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R" newline hexmask.long.byte 0x4 8.--15. 1. "WRR_WEIGHT_VC_5,WRR Weight for VC5. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R" newline hexmask.long.byte 0x4 0.--7. 1. "WRR_WEIGHT_VC_4,WRR Weight for VC4. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R" group.long (0x48+0x700)++0xB line.long 0x0 "VC0_P_RX_Q_CTRL_OFF,Segmented-Buffer VC0 Posted Receive Queue Control." bitfld.long 0x0 31. "VC_ORDERING_RX_Q,VC Ordering for Receive Queues. Determines the VC ordering rule for the receive queues used only in the segmented-buffer configuration: - 1: Strict ordering higher numbered VCs have higher priority - 0: Round robin Note: This register.." "Round robin,Strict ordering" newline bitfld.long 0x0 30. "TLP_TYPE_ORDERING_VC0,TLP Type Ordering for VC0. Determines the TLP type ordering rule for VC0 receive queues used only in the segmented-buffer configuration: - 1: PCIe ordering rules (recommended) - 0: Strict ordering: posted completion then.." "Strict ordering: posted,PCIe ordering rules" newline bitfld.long 0x0 28.--29. "RESERVED5,Reserved. Note: This register field is sticky." "0,1,2,3" newline bitfld.long 0x0 26.--27. "VC0_P_DATA_SCALE,VC0 Scale Posted Data Credites. Note: This register field is sticky." "0,1,2,3" newline bitfld.long 0x0 24.--25. "VC0_P_HDR_SCALE,VC0 Scale Posted Header Credites. Note: This register field is sticky." "0,1,2,3" newline bitfld.long 0x0 21.--23. "VC0_P_TLP_Q_MODE,Reserved. Note: This register field is sticky." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 20. "RESERVED4,Reserved. Note: This register field is sticky." "0,1" newline hexmask.long.byte 0x0 12.--19. 1. "VC0_P_HEADER_CREDIT,VC0 Posted Header Credits. The number of initial posted header credits for VC0 used only in the segmented-buffer configuration. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R (sticky) Note: This.." newline hexmask.long.word 0x0 0.--11. 1. "VC0_P_DATA_CREDIT,VC0 Posted Data Credits. The number of initial posted data credits for VC0 used only in the segmented-buffer configuration. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R (sticky) Note: This.." line.long 0x4 "VC0_NP_RX_Q_CTRL_OFF,Segmented-Buffer VC0 Non-Posted Receive Queue Control." hexmask.long.byte 0x4 28.--31. 1. "RESERVED7,Reserved. Note: This register field is sticky." newline bitfld.long 0x4 26.--27. "VC0_NP_DATA_SCALE,VC0 Scale Non-Posted Data Credites. Note: This register field is sticky." "0,1,2,3" newline bitfld.long 0x4 24.--25. "VC0_NP_HDR_SCALE,VC0 Scale Non-Posted Header Credites. Note: This register field is sticky." "0,1,2,3" newline bitfld.long 0x4 21.--23. "VC0_NP_TLP_Q_MODE,Reserved. Note: This register field is sticky." "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 20. "RESERVED6,Reserved. Note: This register field is sticky." "0,1" newline hexmask.long.byte 0x4 12.--19. 1. "VC0_NP_HEADER_CREDIT,VC0 Non-Posted Header Credits. The number of initial non-posted header credits for VC0 used only in the segmented-buffer configuration. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R (sticky).." newline hexmask.long.word 0x4 0.--11. 1. "VC0_NP_DATA_CREDIT,VC0 Non-Posted Data Credits. The number of initial non-posted data credits for VC0 used only in the segmented-buffer configuration. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R (sticky) Note:.." line.long 0x8 "VC0_CPL_RX_Q_CTRL_OFF,Segmented-Buffer VC0 Completion Receive Queue Control." hexmask.long.byte 0x8 28.--31. 1. "RESERVED9,Reserved. Note: This register field is sticky." newline bitfld.long 0x8 26.--27. "VC0_CPL_DATA_SCALE,VC0 Scale CPL Data Credites. Note: This register field is sticky." "0,1,2,3" newline bitfld.long 0x8 24.--25. "VC0_CPL_HDR_SCALE,VC0 Scale CPL Header Credites. Note: This register field is sticky." "0,1,2,3" newline bitfld.long 0x8 21.--23. "VC0_CPL_TLP_Q_MODE,Reserved. Note: This register field is sticky." "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 20. "RESERVED8,Reserved. Note: This register field is sticky." "0,1" newline hexmask.long.byte 0x8 12.--19. 1. "VC0_CPL_HEADER_CREDIT,VC0 Completion Header Credits. The number of initial Completion header credits for VC0 used only in the segmented-buffer configuration. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R (sticky).." newline hexmask.long.word 0x8 0.--11. 1. "VC0_CPL_DATA_CREDIT,VC0 Completion Data Credits. The number of initial Completion data credits for VC0 used only in the segmented-buffer configuration. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R (sticky) Note:.." group.long (0x10C+0x700)++0x3 line.long 0x0 "GEN2_CTRL_OFF,This register is used to control various functions of the controller related to link training. lane reversal. and equalization." rbitfld.long 0x0 31. "RSVDP_31,Reserved for future use." "0,1" newline bitfld.long 0x0 30. "FORCE_LANE_FLIP,Enable to force the LANE_UNDER_TEST physical lane flips to logical lane 0. All the other physical lanes are turned off. The LINK_CAPABLE register must be set to 1 and only x1 link can be formed if the FORCE_LANE_FLIP register is set to 1." "0,1" newline hexmask.long.byte 0x0 24.--27. 1. "LANE_UNDER_TEST,The Lane Under Test is the lane for Forced Lane Flip or for Loopback Eq. The value is from 0 to CX_NL. Only one lane is configured each time. The default of this field is the CX_DEFAULT_LANE_UNDER_TEST configuration parameter. This field.." newline rbitfld.long 0x0 22.--23. "RSVDP_22,Reserved for future use." "0,1,2,3" newline bitfld.long 0x0 21. "GEN1_EI_INFERENCE,Electrical Idle Inference Mode at Gen1 Rate. Programmable mode to determine inferred electrical idle (EI) in Recovery.Speed or Loopback.Active (as slave) state at Gen1 speed by looking for a '1' value on RxElecIdle instead of looking.." "Use RxElecIdle signal to infer Electrical Idle,Use RxValid signal to infer Electrical Idle" newline bitfld.long 0x0 20. "SEL_DEEMPHASIS,Used to set the de-emphasis level for upstream ports. This bit selects the level of de-emphasis the link operates at. - 0: -6 dB - 1: -3.5 dB This field is reserved (fixed to '0') for M-PCIe. Note: The access attributes of this field are.." "0,1" newline bitfld.long 0x0 19. "CONFIG_TX_COMP_RX,Config Tx Compliance Receive Bit. When set to 1 signals LTSSM to transmit TS ordered sets with the compliance receive bit assert (equal to '1'). This field is reserved (fixed to '0') for M-PCIe. Note: The access attributes of this.." "0,1" newline bitfld.long 0x0 18. "CONFIG_PHY_TX_CHANGE,Config PHY Tx Swing. Controls the PHY transmitter voltage swing level. The controller drives the mac_phy_txswing output from this register bit field. - 0: Full Swing - 1: Low Swing This field is reserved (fixed to '0') for M-PCIe." "Full Swing,Low Swing" newline bitfld.long 0x0 17. "DIRECT_SPEED_CHANGE,Directed Speed Change. Writing '1' to this field instructs the LTSSM to initiate a speed change to Gen2 or Gen3 after the link is initialized at Gen1 speed. When the speed change occurs the controller will clear the contents of this.." "0,1" newline bitfld.long 0x0 16. "AUTO_LANE_FLIP_CTRL_EN,Enable Auto flipping of the lanes. You must set the CX_AUTO_LANE_FLIP_CTRL_EN configuration parameter to include the hardware for this feature in the controller. For more details see the 'Lane Reversal' appendix in the Databook." "0,1" newline bitfld.long 0x0 13.--15. "PRE_DET_LANE,Predetermined Lane for Auto Flip. This field defines which physical lane is connected to logical Lane0 by the flip operation performed in Detect. This field is used to restrict the receiver detect procedure to a particular lane when the.." "LANE0,LANE1,LANE3,LANE7,LANE15,?,?,?" newline hexmask.long.byte 0x0 8.--12. 1. "NUM_OF_LANES,Predetermined Number of Lanes. Defines the number of lanes which are connected and not bad. Used to limit the effective link width to ignore 'broken' or 'unused' lanes that detect a receiver. Indicates the number of lanes to check for exit.." newline hexmask.long.byte 0x0 0.--7. 1. "FAST_TRAINING_SEQ,Sets the Number of Fast Training Sequences (N_FTS) that the controller advertises as its N_FTS during Gen2 or Gen3 link training. This value is used to inform the link partner about the PHY's ability to recover synchronization after a.." rgroup.long (0x110+0x700)++0x3 line.long 0x0 "PHY_STATUS_OFF,PHY Status Register. Memory mapped register from phy_cfg_status GPIO input pins." hexmask.long 0x0 0.--31. 1. "PHY_STATUS,PHY Status. Data received directly from the phy_cfg_status bus. These is a GPIO register reflecting the values on the static phy_cfg_status input signals. The usage is left completely to the user and does not in any way influence controller.." group.long (0x114+0x700)++0x3 line.long 0x0 "PHY_CONTROL_OFF,PHY Control Register. Memory mapped register to cfg_phy_control GPIO output pins." hexmask.long 0x0 0.--31. 1. "PHY_CONTROL,PHY Control. Data sent directly to the cfg_phy_control bus. These is a GPIO register driving the values on the static cfg_phy_control output signals. The usage is left completely to the user and does not in any way influence controller.." group.long (0x11C+0x700)++0x77 line.long 0x0 "TRGT_MAP_CTRL_OFF,Programmable Target Map Control Register." hexmask.long.word 0x0 21.--31. 1. "TARGET_MAP_RESERVED_21_31,Reserved. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R (sticky)" newline hexmask.long.byte 0x0 16.--20. 1. "TARGET_MAP_INDEX,The number of the PF Function on which the Target Values are set. This register does not respect the Byte Enable setting. any write will affect all register bits." newline rbitfld.long 0x0 13.--15. "TARGET_MAP_RESERVED_13_15,Reserved. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R (sticky)" "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x0 7.--12. 1. "TARGET_MAP_VF,Target Values for each BAR on the VF Function selected by the index number. This register does not respect the Byte Enable setting. any write will affect all register bits." newline bitfld.long 0x0 6. "TARGET_MAP_ROM,Target Value for the ROM page of the PF Function selected by the index number. This register does not respect the Byte Enable setting. any write will affect all register bits." "0,1" newline hexmask.long.byte 0x0 0.--5. 1. "TARGET_MAP_PF,Target Values for each BAR on the PF Function selected by the index number. This register does not respect the Byte Enable setting. any write will affect all register bits." line.long 0x4 "MSI_CTRL_ADDR_OFF,Integrated MSI Reception Module (iMRM) Address Register." hexmask.long 0x4 0.--31. 1. "MSI_CTRL_ADDR,Integrated MSI Reception Module Address. System specified address for MSI memory write transaction termination. Within the AXI Bridge every received Memory Write request is examined to see if it targets the MSI Address that has been.." line.long 0x8 "MSI_CTRL_UPPER_ADDR_OFF,Integrated MSI Reception Module Upper Address Register." hexmask.long 0x8 0.--31. 1. "MSI_CTRL_UPPER_ADDR,Integrated MSI Reception Module Upper Address. System specified upper address for MSI memory write transaction termination. Allows functions to support a 64-bit MSI address. Note: This register field is sticky." line.long 0xC "MSI_CTRL_INT_0_EN_OFF,Integrated MSI Reception Module Interrupt#i Enable Register." hexmask.long 0xC 0.--31. 1. "MSI_CTRL_INT_0_EN,MSI Interrupt#i Enable. Specifies which interrupts are enabled. When an MSI is received from a disabled interrupt no status bit gets set in MSI controller interrupt status register. Each bit corresponds to a single MSI Interrupt.." line.long 0x10 "MSI_CTRL_INT_0_MASK_OFF,Integrated MSI Reception Module Interrupt#i Mask Register." hexmask.long 0x10 0.--31. 1. "MSI_CTRL_INT_0_MASK,MSI Interrupt#i Mask. Allows enabled interrupts to be masked. When an MSI is received for a masked interrupt the corresponding status bit gets set in the interrupt status register but the msi_ctrl_int output is not set HIGH. Each bit.." line.long 0x14 "MSI_CTRL_INT_0_STATUS_OFF,Integrated MSI Reception Module Interrupt#i Status Register." hexmask.long 0x14 0.--31. 1. "MSI_CTRL_INT_0_STATUS,MSI Interrupt#i Status. When an MSI is detected for EP#i one bit in this register is set. The decoding of the data payload of the MSI Memory Write request determines which bit gets set. A status is bit is cleared by writing a 1 to.." line.long 0x18 "MSI_CTRL_INT_1_EN_OFF,Integrated MSI Reception Module Interrupt#i Enable Register." hexmask.long 0x18 0.--31. 1. "MSI_CTRL_INT_1_EN,MSI Interrupt#i Enable. Specifies which interrupts are enabled. When an MSI is received from a disabled interrupt no status bit gets set in MSI controller interrupt status register. Each bit corresponds to a single MSI Interrupt.." line.long 0x1C "MSI_CTRL_INT_1_MASK_OFF,Integrated MSI Reception Module Interrupt#i Mask Register." hexmask.long 0x1C 0.--31. 1. "MSI_CTRL_INT_1_MASK,MSI Interrupt#i Mask. Allows enabled interrupts to be masked. When an MSI is received for a masked interrupt the corresponding status bit gets set in the interrupt status register but the msi_ctrl_int output is not set HIGH. Each bit.." line.long 0x20 "MSI_CTRL_INT_1_STATUS_OFF,Integrated MSI Reception Module Interrupt#i Status Register." hexmask.long 0x20 0.--31. 1. "MSI_CTRL_INT_1_STATUS,MSI Interrupt#i Status. When an MSI is detected for EP#i one bit in this register is set. The decoding of the data payload of the MSI Memory Write request determines which bit gets set. A status is bit is cleared by writing a 1 to.." line.long 0x24 "MSI_CTRL_INT_2_EN_OFF,Integrated MSI Reception Module Interrupt#i Enable Register." hexmask.long 0x24 0.--31. 1. "MSI_CTRL_INT_2_EN,MSI Interrupt#i Enable. Specifies which interrupts are enabled. When an MSI is received from a disabled interrupt no status bit gets set in MSI controller interrupt status register. Each bit corresponds to a single MSI Interrupt.." line.long 0x28 "MSI_CTRL_INT_2_MASK_OFF,Integrated MSI Reception Module Interrupt#i Mask Register." hexmask.long 0x28 0.--31. 1. "MSI_CTRL_INT_2_MASK,MSI Interrupt#i Mask. Allows enabled interrupts to be masked. When an MSI is received for a masked interrupt the corresponding status bit gets set in the interrupt status register but the msi_ctrl_int output is not set HIGH. Each bit.." line.long 0x2C "MSI_CTRL_INT_2_STATUS_OFF,Integrated MSI Reception Module Interrupt#i Status Register." hexmask.long 0x2C 0.--31. 1. "MSI_CTRL_INT_2_STATUS,MSI Interrupt#i Status. When an MSI is detected for EP#i one bit in this register is set. The decoding of the data payload of the MSI Memory Write request determines which bit gets set. A status is bit is cleared by writing a 1 to.." line.long 0x30 "MSI_CTRL_INT_3_EN_OFF,Integrated MSI Reception Module Interrupt#i Enable Register." hexmask.long 0x30 0.--31. 1. "MSI_CTRL_INT_3_EN,MSI Interrupt#i Enable. Specifies which interrupts are enabled. When an MSI is received from a disabled interrupt no status bit gets set in MSI controller interrupt status register. Each bit corresponds to a single MSI Interrupt.." line.long 0x34 "MSI_CTRL_INT_3_MASK_OFF,Integrated MSI Reception Module Interrupt#i Mask Register." hexmask.long 0x34 0.--31. 1. "MSI_CTRL_INT_3_MASK,MSI Interrupt#i Mask. Allows enabled interrupts to be masked. When an MSI is received for a masked interrupt the corresponding status bit gets set in the interrupt status register but the msi_ctrl_int output is not set HIGH. Each bit.." line.long 0x38 "MSI_CTRL_INT_3_STATUS_OFF,Integrated MSI Reception Module Interrupt#i Status Register." hexmask.long 0x38 0.--31. 1. "MSI_CTRL_INT_3_STATUS,MSI Interrupt#i Status. When an MSI is detected for EP#i one bit in this register is set. The decoding of the data payload of the MSI Memory Write request determines which bit gets set. A status is bit is cleared by writing a 1 to.." line.long 0x3C "MSI_CTRL_INT_4_EN_OFF,Integrated MSI Reception Module Interrupt#i Enable Register." hexmask.long 0x3C 0.--31. 1. "MSI_CTRL_INT_4_EN,MSI Interrupt#i Enable. Specifies which interrupts are enabled. When an MSI is received from a disabled interrupt no status bit gets set in MSI controller interrupt status register. Each bit corresponds to a single MSI Interrupt.." line.long 0x40 "MSI_CTRL_INT_4_MASK_OFF,Integrated MSI Reception Module Interrupt#i Mask Register." hexmask.long 0x40 0.--31. 1. "MSI_CTRL_INT_4_MASK,MSI Interrupt#i Mask. Allows enabled interrupts to be masked. When an MSI is received for a masked interrupt the corresponding status bit gets set in the interrupt status register but the msi_ctrl_int output is not set HIGH. Each bit.." line.long 0x44 "MSI_CTRL_INT_4_STATUS_OFF,Integrated MSI Reception Module Interrupt#i Status Register." hexmask.long 0x44 0.--31. 1. "MSI_CTRL_INT_4_STATUS,MSI Interrupt#i Status. When an MSI is detected for EP#i one bit in this register is set. The decoding of the data payload of the MSI Memory Write request determines which bit gets set. A status is bit is cleared by writing a 1 to.." line.long 0x48 "MSI_CTRL_INT_5_EN_OFF,Integrated MSI Reception Module Interrupt#i Enable Register." hexmask.long 0x48 0.--31. 1. "MSI_CTRL_INT_5_EN,MSI Interrupt#i Enable. Specifies which interrupts are enabled. When an MSI is received from a disabled interrupt no status bit gets set in MSI controller interrupt status register. Each bit corresponds to a single MSI Interrupt.." line.long 0x4C "MSI_CTRL_INT_5_MASK_OFF,Integrated MSI Reception Module Interrupt#i Mask Register." hexmask.long 0x4C 0.--31. 1. "MSI_CTRL_INT_5_MASK,MSI Interrupt#i Mask. Allows enabled interrupts to be masked. When an MSI is received for a masked interrupt the corresponding status bit gets set in the interrupt status register but the msi_ctrl_int output is not set HIGH. Each bit.." line.long 0x50 "MSI_CTRL_INT_5_STATUS_OFF,Integrated MSI Reception Module Interrupt#i Status Register." hexmask.long 0x50 0.--31. 1. "MSI_CTRL_INT_5_STATUS,MSI Interrupt#i Status. When an MSI is detected for EP#i one bit in this register is set. The decoding of the data payload of the MSI Memory Write request determines which bit gets set. A status is bit is cleared by writing a 1 to.." line.long 0x54 "MSI_CTRL_INT_6_EN_OFF,Integrated MSI Reception Module Interrupt#i Enable Register." hexmask.long 0x54 0.--31. 1. "MSI_CTRL_INT_6_EN,MSI Interrupt#i Enable. Specifies which interrupts are enabled. When an MSI is received from a disabled interrupt no status bit gets set in MSI controller interrupt status register. Each bit corresponds to a single MSI Interrupt.." line.long 0x58 "MSI_CTRL_INT_6_MASK_OFF,Integrated MSI Reception Module Interrupt#i Mask Register." hexmask.long 0x58 0.--31. 1. "MSI_CTRL_INT_6_MASK,MSI Interrupt#i Mask. Allows enabled interrupts to be masked. When an MSI is received for a masked interrupt the corresponding status bit gets set in the interrupt status register but the msi_ctrl_int output is not set HIGH. Each bit.." line.long 0x5C "MSI_CTRL_INT_6_STATUS_OFF,Integrated MSI Reception Module Interrupt#i Status Register." hexmask.long 0x5C 0.--31. 1. "MSI_CTRL_INT_6_STATUS,MSI Interrupt#i Status. When an MSI is detected for EP#i one bit in this register is set. The decoding of the data payload of the MSI Memory Write request determines which bit gets set. A status is bit is cleared by writing a 1 to.." line.long 0x60 "MSI_CTRL_INT_7_EN_OFF,Integrated MSI Reception Module Interrupt#i Enable Register." hexmask.long 0x60 0.--31. 1. "MSI_CTRL_INT_7_EN,MSI Interrupt#i Enable. Specifies which interrupts are enabled. When an MSI is received from a disabled interrupt no status bit gets set in MSI controller interrupt status register. Each bit corresponds to a single MSI Interrupt.." line.long 0x64 "MSI_CTRL_INT_7_MASK_OFF,Integrated MSI Reception Module Interrupt#i Mask Register." hexmask.long 0x64 0.--31. 1. "MSI_CTRL_INT_7_MASK,MSI Interrupt#i Mask. Allows enabled interrupts to be masked. When an MSI is received for a masked interrupt the corresponding status bit gets set in the interrupt status register but the msi_ctrl_int output is not set HIGH. Each bit.." line.long 0x68 "MSI_CTRL_INT_7_STATUS_OFF,Integrated MSI Reception Module Interrupt#i Status Register." hexmask.long 0x68 0.--31. 1. "MSI_CTRL_INT_7_STATUS,MSI Interrupt#i Status. When an MSI is detected for EP#i one bit in this register is set. The decoding of the data payload of the MSI Memory Write request determines which bit gets set. A status is bit is cleared by writing a 1 to.." line.long 0x6C "MSI_GPIO_IO_OFF,Integrated MSI Reception Module General Purpose IO Register." hexmask.long 0x6C 0.--31. 1. "MSI_GPIO_REG,MSI GPIO Register. The contents of this register drives the top-level GPIO msi_ctrl_io[31:0] Note: This register field is sticky." line.long 0x70 "CLOCK_GATING_CTRL_OFF,This register enables you to disable dynamic clock gating. By default dynamic clock gating is on. allowing the controller to autonomously enable and disable its clocks. The clock gating is performed in the clock and reset module." hexmask.long 0x70 2.--31. 1. "RSVDP_2,Reserved for future use." newline bitfld.long 0x70 1. "AXI_CLK_GATING_EN,AXI Clock Gating Enable. This register enables the AXI Bridge to autonomously enable and disable the AXI Master clock the AXI Slave clock and the AXI DBI slave clock. The DWC_pcie_clk_rst.v module provides the gated clock.." "Disable,Enable" newline bitfld.long 0x70 0. "RADM_CLK_GATING_EN,RADM Clock Gating Enable. This register if set enables the RADM to autonomously enable and disable its clock. The DWC_pcie_clk_rst.v module provides the gated clock radm_clk_g to the RADM and is enabled when the controllers clock.." "Disable,Enable" line.long 0x74 "GEN3_RELATED_OFF,Gen3 Control Register. There is no Gen3-specific N_FTS field. The N_FTS field in the 'Link Width and Speed Change Control Register' is used for both Gen2 and Gen3 speed modes. There is no Gen3-specific 'Directed Speed Change' field. The.." hexmask.long.byte 0x74 26.--31. 1. "RSVDP_26,Reserved for future use." newline bitfld.long 0x74 23. "GEN3_EQ_INVREQ_EVAL_DIFF_DISABLE,Eq InvalidRequest and RxEqEval Different Time Assertion Disable. Disable the assertion of Eq InvalidRequest and RxEqEval at different time. Note: When CX_GEN4_SPEED/CX_GEN5_SPEED this register is shared for Gen3 and.." "0,1" newline rbitfld.long 0x74 19.--20. "RSVDP_19,Reserved for future use." "0,1,2,3" newline bitfld.long 0x74 18. "GEN3_DC_BALANCE_DISABLE,DC Balance Disable. Disable DC Balance feature. Note: When CX_GEN4_SPEED/CX_GEN5_SPEED this register is shared for Gen3 and Gen4/Gen5 data rate. Note: This register field is sticky." "0,1" newline bitfld.long 0x74 17. "GEN3_DLLP_XMT_DELAY_DISABLE,DLLP Transmission Delay Disable. Disable delay transmission of DLLPs before equalization. Note: When CX_GEN4_SPEED/CX_GEN5_SPEED this register is shared for Gen3 and Gen4/Gen5 data rate. Note: This register field is sticky." "0,1" newline bitfld.long 0x74 16. "GEN3_EQUALIZATION_DISABLE,Equalization Disable. Disable equalization feature. This bit cannot be changed once the LTSSM starts link training. Note: When CX_GEN4_SPEED/CX_GEN5_SPEED this register is shared for Gen3 and Gen4/Gen5 data rate. Note: This.." "0,1" newline rbitfld.long 0x74 14.--15. "RSVDP_14,Reserved for future use." "0,1,2,3" newline bitfld.long 0x74 13. "RXEQ_RGRDLESS_RXTS,When set to '1' the controller as Gen3 EQ master asserts RxEqEval to instruct the PHY to do Rx adaptation and evaluation after a 500ns timeout from a new preset request. - 0: mac_phy_rxeqeval asserts after 1us and 2 TS1 received from.." "mac_phy_rxeqeval asserts after 1us and 2 TS1..,mac_phy_rxeqeval asserts after 500ns regardless.." newline bitfld.long 0x74 12. "RXEQ_PH01_EN,Rx Equalization Phase 0/Phase 1 Hold Enable. When this bit is set the upstream port holds phase 0 (the downstream port holds phase 1) for 10ms. Holding phase 0 or phase 1 can be used to allow sufficient time for Rx Equalization to be.." "Tx equalization only in phase 2/3,No Tx equalization" newline bitfld.long 0x74 11. "EQ_REDO,Equalization Redo Disable. Disable autonomous mechanism for requesting to redo the equalization process. The received presets or coefficients mismatch in Recovery.RcvrLock after Recovery EQ phases causes the EQ redo requests. If the EQ redo is.." "0,1" newline bitfld.long 0x74 10. "EQ_EIEOS_CNT,Equalization EIEOS Count Reset Disable. Disable requesting reset of EIEOS count during equalization. Note: When CX_GEN4_SPEED/CX_GEN5_SPEED this register is shared for Gen3 and Gen4/Gen5 data rate. Note: This register field is sticky." "0,1" newline bitfld.long 0x74 9. "EQ_PHASE_2_3,Equalization Phase 2 and Phase 3 Disable. This applies to downstream ports only. Note: When CX_GEN4_SPEED/CX_GEN5_SPEED this register is shadow register for Gen3 and Gen4/Gen5 data rate. If RATE_SHADOW_SEL==00b this register is for Gen3.." "0,1" newline bitfld.long 0x74 8. "DISABLE_SCRAMBLER_GEN_3,Disable Scrambler for Gen3 and Gen4 Data Rate. The Gen3 and Gen4 scrambler/descrambler within the controller needs to be disabled when the scrambling function is implemented outside of the controller (for example within the PHY)." "0,1" newline hexmask.long.byte 0x74 1.--7. 1. "RSVDP_1,Reserved for future use." newline bitfld.long 0x74 0. "GEN3_ZRXDC_NONCOMPL,Gen3 Receiver Impedance ZRX-DC Not Compliant. Receivers that operate at 8.0 GT/s with an impedance other than the range defined by the ZRX-DC parameter for 2.5 GT/s (40-60 Ohms) must meet additional behavior requirements in the.." "The receiver complies with the ZRX-DC parameter..,The receiver does not comply with the ZRX-DC.." group.long (0x1A8+0x700)++0x7 line.long 0x0 "GEN3_EQ_CONTROL_OFF,Gen3 EQ Control Register. This register controls equalization for Phase2 in an upstream port (USP). or Phase3 in a downstream port (DSP). M-PCIe doesn't have Conventional PCIe Gen3 feature. The registers of this section do not exist." hexmask.long.byte 0x0 27.--31. 1. "RSVDP_27,Reserved for future use." newline bitfld.long 0x0 26. "GEN3_REQ_SEND_CONSEC_EIEOS_FOR_PSET_MAP,Request controller to send back-to-back EIEOS in Recovery.RcvrLock state until presets to coefficients mapping is complete. - 0: Do not request - 1: request Note: Gen3 and Gen4 share the same register bit and have.." "Do not request,request" newline bitfld.long 0x0 25. "GEN3_EQ_PSET_REQ_AS_COEF,GEN3_EQ_PSET_REQ_AS_COEF is an internally reserved field. Do not use. Note: This register field is sticky." "0,1" newline bitfld.long 0x0 24. "GEN3_EQ_FOM_INC_INITIAL_EVAL,Include Initial FOM. Include or not the FOM feedback from the initial preset evaluation performed in the EQ Master when finding the highest FOM among all preset evaluations. - 0: Do not include - 1: Include Note: When.." "Do not include,Include" newline hexmask.long.word 0x0 8.--23. 1. "GEN3_EQ_PSET_REQ_VEC,Preset Request Vector. Requesting of Presets during the initial part of the EQ Master Phase. Encoding scheme is as follows: Bit [15:0] =0x0: No preset is requested and evaluated in EQ Master Phase. Bit [i] =1: 'Preset=i' is requested.." newline rbitfld.long 0x0 7. "RSVDP_7,Reserved for future use." "0,1" newline bitfld.long 0x0 6. "GEN3_LOWER_RATE_EQ_REDO_ENABLE,Support EQ redo and lower rate change: - 0: not support - 1: support Note: Gen3 and Gen4 share the same register bit and have the same feature. Note: This register field is sticky." "not support,support" newline bitfld.long 0x0 5. "GEN3_EQ_EVAL_2MS_DISABLE,Phase2_3 2 ms Timeout Disable. Determine behavior in Phase2 for USP (Phase3 if DSP) when the PHY does not respond within 2ms to the assertion of RxEqEval: - 0: abort the current evaluation stop any attempt to modify the remote.." "abort the current evaluation,ignore the 2ms timeout and continue as normal" newline bitfld.long 0x0 4. "GEN3_EQ_PHASE23_EXIT_MODE,Behavior After 24 ms Timeout (when optimal settings are not found). For a USP: Determine next LTSSM state from Phase2 after 24ms Timeout - 0: Recovery.Speed - 1: Recovery.Equalization.Phase3 When optimal settings are not found.." "Equalization Phase 3 Successful status bit is..,Recovery" newline hexmask.long.byte 0x0 0.--3. 1. "GEN3_EQ_FB_MODE,Feedback Mode. - 0000b: Direction Change - 0001b: Figure Of Merit - 0010b: Reserved - .....: Reserved - 1111b: Reserved Note: When CX_GEN4_SPEED/CX_GEN5_SPEED this register is a shadow register for Gen3 and Gen4/Gen5 data rate. If.." line.long 0x4 "GEN3_EQ_FB_MODE_DIR_CHANGE_OFF,Gen3 EQ Direction Change Feedback Mode Control Register. Equalization controls to be used in Phase2 (USP) or Phase 3 (DSP). when you set the Feedback Mode in 'Gen3 EQ Control Register' to 'Direction Change.' These fields.." hexmask.long.word 0x4 18.--31. 1. "RSVDP_18,Reserved for future use." newline hexmask.long.byte 0x4 14.--17. 1. "GEN3_EQ_FMDC_MAX_POST_CUSROR_DELTA,Convergence Window Aperture for C+1. Post-cursor coefficients maximum delta within the convergence window depth. Allowed range: 0 1 2 ..15. Note: When CX_GEN4_SPEED/CX_GEN5_SPEED this register is shadow register for.." newline hexmask.long.byte 0x4 10.--13. 1. "GEN3_EQ_FMDC_MAX_PRE_CUSROR_DELTA,Convergence Window Aperture for C-1. Pre-cursor coefficients maximum delta within the convergence window depth. Allowed range: 0 1 2 ..15. Note: When CX_GEN4_SPEED/CX_GEN5_SPEED this register is shadow register for Gen3.." newline hexmask.long.byte 0x4 5.--9. 1. "GEN3_EQ_FMDC_N_EVALS,Convergence Window Depth. Number of consecutive evaluations considered in Phase 2/3 when determining if optimal coefficients have been found. Allowed range: 0 1 2 ..16 up to a maximum of CX_GEN3_EQ_COEFQ_DEPTH. When set to 0 EQ.." newline hexmask.long.byte 0x4 0.--4. 1. "GEN3_EQ_FMDC_T_MIN_PHASE23,Minimum Time (in ms) To Remain in EQ Master Phase. The LTSSM stays in EQ Master phase for at least this amount of time before starting to check for convergence of the coefficients. Allowed values 0 1 ... 24. Note: When.." group.long (0x1B4+0x700)++0x27 line.long 0x0 "ORDER_RULE_CTRL_OFF,Order Rule Control Register." hexmask.long.word 0x0 16.--31. 1. "RSVDP_16,Reserved for future use." newline hexmask.long.byte 0x0 8.--15. 1. "CPL_PASS_P,Completion Passing Posted Ordering Rule Control. Determines if CPL can pass halted P queue. - 0: CPL can not pass P (recommended) - 1: CPL can pass P" newline hexmask.long.byte 0x0 0.--7. 1. "NP_PASS_P,Non-Posted Passing Posted Ordering Rule Control. Determines if NP can pass halted P queue. - 0 : NP can not pass P (recommended). - 1 : NP can pass P" line.long 0x4 "PIPE_LOOPBACK_CONTROL_OFF,PIPE Loopback Control Register." bitfld.long 0x4 31. "PIPE_LOOPBACK,PIPE Loopback Enable. Indicates RMMI Loopback if M-PCIe. Note: This register field is sticky." "0,1" newline hexmask.long.byte 0x4 27.--30. 1. "RSVDP_27,Reserved for future use." newline bitfld.long 0x4 24.--26. "RXSTATUS_VALUE,RXSTATUS_VALUE is an internally reserved field. Do not use." "0,1,2,3,4,5,6,7" newline rbitfld.long 0x4 22.--23. "RSVDP_22,Reserved for future use." "0,1,2,3" newline hexmask.long.byte 0x4 16.--21. 1. "RXSTATUS_LANE,RXSTATUS_LANE is an internally reserved field. Do not use. Note: This register field is sticky." newline hexmask.long.word 0x4 0.--15. 1. "LPBK_RXVALID,LPBK_RXVALID is an internally reserved field. Do not use. Note: This register field is sticky." line.long 0x8 "MISC_CONTROL_1_OFF,DBI Read-Only Write Enable Register." hexmask.long.word 0x8 22.--31. 1. "RSVDP_22,Reserved for future use." newline bitfld.long 0x8 21. "P2P_ERR_RPT_CTRL,Determines whether to track completion of transmitted Non-Posted TLPs in P2P mode. - 0: Do not track completion - 1: Track completion Note: This register field is sticky." "Do not track completion,Track completion" newline bitfld.long 0x8 20. "P2P_TRACK_CPL_TO_REG,Determines whether to enable Peer to Peer (P2P) error reporting. - 0: Disable P2P error reporting - 1: Enable P2P error reporting Note: This register field is sticky." "Disable P2P error reporting,Enable P2P error reporting" newline bitfld.long 0x8 18.--19. "TARGET_ABOVE_CONFIG_LIMIT_REG,Configuration requests with an address greater than CONFIG_LIMIT_REG are directed to either ELBI or TRGT1 interface based on the setting of this field. This field can have the following values: - 1: ELBI - 2: TRGT1 Note:.." "?,ELBI,TRGT1,?" newline hexmask.long.word 0x8 8.--17. 1. "CONFIG_LIMIT_REG,Configuration requests are directed either to CDM or ELBI/RTRGT1 based on the value of this field. - Configuration requests with an address less CONFIG_LIMIT_REG are directed to the CDM - Configuration requests with an address greater.." newline bitfld.long 0x8 7. "CFG_TLP_BYPASS_EN_REG,Setting of this field defines which field TARGET_ABOVE_CONFIG_LIMIT_REG or CONFIG_LIMIT_REG decides the destination of Configuration requests. This field can have the following values: - 0: Configuration TLPs are routed according to.." "Configuration TLPs are routed according to the..,Configuration TLPs are routed according to the.." newline bitfld.long 0x8 6. "CPLQ_MNG_EN,This field enables the Completion Queue Management feature. Note: This register field is sticky." "0,1" newline bitfld.long 0x8 5. "ARI_DEVICE_NUMBER,When ARI is enabled this field enables use of the device ID. Note: This register field is sticky." "0,1" newline bitfld.long 0x8 4. "DISABLE_AUTO_LTR_CLR_MSG,Disable the autonomous generation of LTR clear message in upstream port. This field can have the following values: - 0: Allow the autonomous generation of LTR clear message. - 1: Disable the autonomous generation of LTR clear.." "Allow the autonomous generation of LTR clear..,Disable the autonomous generation of LTR clear.." newline bitfld.long 0x8 3. "SIMPLIFIED_REPLAY_TIMER,Enables Simplified Replay Timer (Gen4). For more details see 'Transmit Replay' in 'Transmit TLP Processing' section in the 'Controller Operations' chapter of the Databook. Simplified Replay Timer can have the following Values: -.." "0,1" newline bitfld.long 0x8 2. "UR_CA_MASK_4_TRGT1,When this field is set to '1' the controller suppresses error logging error message generation and CPL generation for non-posted requests TLPs (with UR filtering status) forwarded to your application (that is when DEFAULT_TARGET.." "0,1" newline bitfld.long 0x8 1. "DEFAULT_TARGET,Default target for an IO or MEM request with UR/CA/CRS received. Based on the value of this field the controller either drops or forwards these requests to your application. - 0: The controller drops all incoming I/O or MEM requests (after.." "The controller drops all incoming I/O or MEM..,The controller forwards all incoming I/O or MEM.." newline bitfld.long 0x8 0. "DBI_RO_WR_EN,Write to RO Registers Using DBI. Your application can write to some RO and HwInit register fields through the DBI when you set this field to '1'. For more details see 'Writing to Read-Only Registers' in 'Register Module LBC and DBI'.." "0,1" line.long 0xC "MULTI_LANE_CONTROL_OFF,UpConfigure Multi-lane Control Register. Used when upsizing or downsizing the link width through Configuration state without bringing the link down. For more details. see the 'Link Establishment' section in the 'Controller.." hexmask.long.tbyte 0xC 8.--31. 1. "RSVDP_8,Reserved for future use." newline bitfld.long 0xC 7. "UPCONFIGURE_SUPPORT,Upconfigure Support. The controller sends this value as the Link Upconfigure Capability in TS2 Ordered Sets in Configuration.Complete state. This field is reserved (fixed to '0') for M-PCIe. Note: This register field is sticky." "0,1" newline bitfld.long 0xC 6. "DIRECT_LINK_WIDTH_CHANGE,Directed Link Width Change. The controller always moves to Configuration state through Recovery state when this bit is set to '1'. - If the upconfigure_capable variable is '1' and the PCIE_CAP_HW_AUTO_WIDTH_DISABLE bit in.." "0,1" newline hexmask.long.byte 0xC 0.--5. 1. "TARGET_LINK_WIDTH,Target Link Width. Values correspond to: - 6'b000000: Controller does not start upconfigure or autonomous width downsizing in the Configuration state. - 6'b000001: x1 - 6'b000010: x2 - 6'b000100: x4 - 6'b001000: x8 - 6'b010000: x16 -.." line.long 0x10 "PHY_INTEROP_CTRL_OFF,PHY Interoperability Control Register." hexmask.long.tbyte 0x10 12.--31. 1. "RSVDP_12,Reserved for future use." newline bitfld.long 0x10 10. "L1_CLK_SEL,L1 Clock control bit. This field is reserved for internal use. You should not write to this field and change the default unless specifically instructed by Synopsys support. - 1: Controller does not request aux_clk switch and core_clk gating in.." "Controller requests aux_clk switch and core_clk..,Controller does not request aux_clk switch and.." newline rbitfld.long 0x10 9. "L1_NOWAIT_P1,L1 entry control bit. This field is reserved for internal use. You should not write to this field and change the default unless specifically instructed by Synopsys support. - 1: Controller does not wait for PHY to acknowledge transition to.." "Controller waits for the PHY to acknowledge..,Controller does not wait for PHY to acknowledge.." newline bitfld.long 0x10 8. "L1SUB_EXIT_MODE,L1 Exit Control Using phy_mac_pclkack_n. This field is reserved for internal use. You should not write to this field and change the default unless specifically instructed by Synopsys support. - 1: Controller exits L1 without waiting for.." "Controller waits for the PHY to assert..,Controller exits L1 without waiting for the PHY.." newline rbitfld.long 0x10 7. "RSVDP_7,Reserved for future use." "0,1" newline hexmask.long.byte 0x10 0.--6. 1. "RXSTANDBY_CONTROL,Rxstandby Control. Bits 0..5 determine if the controller asserts the RxStandby signal (mac_phy_rxstandby) in the indicated condition. Bit 6 enables the controller to perform the RxStandby/RxStandbyStatus handshake. This field is.." line.long 0x14 "TRGT_CPL_LUT_DELETE_ENTRY_OFF,TRGT_CPL_LUT Delete Entry Control register. Using this register you can delete one entry in the target completion LUT. You should only use this register when you know that your application will never send the completion.." bitfld.long 0x14 31. "DELETE_EN,This is a one-shot bit. A '1' write to this bit triggers the deletion of the target completion LUT entry that is specified in the LOOK_UP_ID field. This is a self-clearing register field. Reading from this register field always returns a '0'." "0,1" newline hexmask.long 0x14 0.--30. 1. "LOOK_UP_ID,This number selects one entry to delete of the TRGT_CPL_LUT." line.long 0x18 "LINK_FLUSH_CONTROL_OFF,Link Reset Request Flush Control Register." hexmask.long.byte 0x18 24.--31. 1. "RSVD_I_8,This is an internally reserved field. Do not use. Note: This register field is sticky." newline hexmask.long.tbyte 0x18 1.--23. 1. "RSVDP_1,Reserved for future use." newline bitfld.long 0x18 0. "AUTO_FLUSH_EN,Enables automatic flushing of pending requests before sending the reset request to the application logic to reset the PCIe controller and the AXI Bridge. The flushing process is initiated if any of the following events occur: - Hot reset.." "0,1" line.long 0x1C "AMBA_ERROR_RESPONSE_DEFAULT_OFF,AXI Bridge Slave Error Response Register." hexmask.long.word 0x1C 16.--31. 1. "RSVDP_16,Reserved for future use." newline hexmask.long.byte 0x1C 10.--15. 1. "AMBA_ERROR_RESPONSE_MAP,AXI Slave Response Error Map. Allows you to selectively map the errors received from the PCIe completion (for non-posted requests) to the AXI slave responses slv_rresp or slv_bresp. The recommended setting is SLVERR. CRS is.." newline hexmask.long.byte 0x1C 5.--9. 1. "RSVDP_5,Reserved for future use." newline bitfld.long 0x1C 3.--4. "AMBA_ERROR_RESPONSE_CRS,CRS Slave Error Response Mapping. Determines the AXI slave response for CRS completions. For more details see 'Error Handling' in the AXI chapter of the Databook. AHB: - always returns OKAY AXI: - 00: OKAY - 01: OKAY with all.." "OKAY,OKAY with all FFFF_FFFF data for all CRS..,?,?" newline bitfld.long 0x1C 2. "AMBA_ERROR_RESPONSE_VENDORID,Vendor ID Non-existent Slave Error Response Mapping. Determines the AXI slave response for errors on reads to non-existent Vendor ID register. For more details see 'Error Handling' in the AXI chapter of the Databook. AHB: -.." "OKAY,SLVERR/DECERR" newline rbitfld.long 0x1C 1. "RSVDP_1,Reserved for future use." "0,1" newline bitfld.long 0x1C 0. "AMBA_ERROR_RESPONSE_GLOBAL,Global Slave Error Response Mapping. Determines the AXI slave response for all error scenarios on non-posted requests. For more details see 'Error Handling' in the AXI chapter of the Databook. AHB: - 0: OKAY (with FFFF data for.." "OKAY,SLVERR/DECERR" line.long 0x20 "AMBA_LINK_TIMEOUT_OFF,Link Down AXI Bridge Slave Timeout Register. If your application AXI master issues outbound requests to the AXI bridge slave interface before the PCIe link is operational. the controller starts a 'flush' timer. The timeout value of.." hexmask.long.tbyte 0x20 9.--31. 1. "RSVDP_9,Reserved for future use." newline bitfld.long 0x20 8. "LINK_TIMEOUT_ENABLE_DEFAULT,Disable Flush. You can disable the flush feature by setting this field to '1'. Note: This register field is sticky." "0,1" newline hexmask.long.byte 0x20 0.--7. 1. "LINK_TIMEOUT_PERIOD_DEFAULT,Timeout Value (ms). The timer will timeout and then flush the bridge TX request queues after this amount of time. The timer counts when there are pending outbound AXI slave interface requests and the PCIe TX link is not.." line.long 0x24 "AMBA_ORDERING_CTRL_OFF,AMBA Ordering Control." hexmask.long.tbyte 0x24 8.--31. 1. "RSVDP_8,Reserved for future use." newline bitfld.long 0x24 7. "AX_MSTR_ZEROLREAD_FW,AXI Master Zero Length Read Forward to the application. The DW PCIe controller AXI bridge is able to terminate in order with the Posted transactions the zero length read implementing the PCIe express flush semantics of the Posted.." "The zero length Read is terminated at the DW..,The zero length Read is forward to the application" newline rbitfld.long 0x24 5.--6. "RSVDP_5,Reserved for future use." "0,1,2,3" newline bitfld.long 0x24 3.--4. "AX_MSTR_ORDR_P_EVENT_SEL,AXI Master Posted Ordering Event Selector. This field selects how the master interface determines when a P write is completed when enforcing the PCIe ordering rule 'NP must not pass P' at the AXI Master Interface. The AXI.." "B'last event: wait for the all of the write..,AW'last event: wait until the complete Posted..,This setting will not affect:,?" newline rbitfld.long 0x24 2. "RSVDP_2,Reserved for future use." "0,1" newline bitfld.long 0x24 1. "AX_SNP_EN,AXI Serialize Non-Posted Requests Enable. This field enables the AXI Bridge to serialize same ID Non-Posted Read/Write Requests on the wire. Serialization implies one outstanding same ID NP Read or Write on the wire and used to avoid AXI RAR.." "0,1" newline rbitfld.long 0x24 0. "RSVDP_0,Reserved for future use." "0,1" group.long (0x1E0+0x700)++0xB line.long 0x0 "COHERENCY_CONTROL_1_OFF,ACE Cache Coherency Control Register 1" hexmask.long 0x0 2.--31. 1. "CFG_MEMTYPE_BOUNDARY_LOW_ADDR,Boundary Lower Address For Memory Type. Bits [31:0] of dword-aligned address of the boundary for Memory type. The two lower address LSBs are '00'. Addresses up to but not including this value are in the lower address space.." newline rbitfld.long 0x0 1. "RSVDP_1,Reserved for future use." "0,1" newline bitfld.long 0x0 0. "CFG_MEMTYPE_VALUE,Sets the memory type for the lower and upper parts of the address space: - 0: lower = Peripheral; upper = Memory - 1: lower = Memory type; upper = Peripheral Note: This register field is sticky." "lower = Peripheral; upper = Memory,lower = Memory type; upper = Peripheral" line.long 0x4 "COHERENCY_CONTROL_2_OFF,ACE Cache Coherency Control Register 2" hexmask.long 0x4 0.--31. 1. "CFG_MEMTYPE_BOUNDARY_HIGH_ADDR,Boundary Upper Address For Memory Type. Bits [63:32] of the 64-bit dword-aligned address of the boundary for Memory type. Note: This register field is sticky." line.long 0x8 "COHERENCY_CONTROL_3_OFF,ACE Cache Coherency Control Register 3" hexmask.long.byte 0x8 27.--30. 1. "CFG_MSTR_AWCACHE_VALUE,Master Write CACHE Signal Value. Value of the individual bits in mstr_awcache when CFG_MSTR_AWCACHE_MODE is '1'. Note: not applicable to message requests; for message requests the value of mstr_awcache is always '0000' Note: This.." newline hexmask.long.byte 0x8 19.--22. 1. "CFG_MSTR_ARCACHE_VALUE,Master Read CACHE Signal Value. Value of the individual bits in mstr_arcache when CFG_MSTR_ARCACHE_MODE is '1'. Note: This register field is sticky." newline hexmask.long.byte 0x8 11.--14. 1. "CFG_MSTR_AWCACHE_MODE,Master Write CACHE Signal Behavior. Defines how the individual bits in mstr_awcache are controlled: - 0: set automatically by the AXI master - 1: set by the value of the corresponding bit of the CFG_MSTR_AWCACHE_VALUE field Note:.." newline hexmask.long.byte 0x8 3.--6. 1. "CFG_MSTR_ARCACHE_MODE,Master Read CACHE Signal Behavior. Defines how the individual bits in mstr_arcache are controlled: - 0: set automatically by the AXI master - 1: set by the value of the corresponding bit of the CFG_MSTR_ARCACHE_VALUE field Note:.." group.long (0x1F0+0x700)++0x7 line.long 0x0 "AXI_MSTR_MSG_ADDR_LOW_OFF,Lower 20 bits of the programmable AXI address where Messages coming from wire are mapped to. Bits [11:0] of the register are tied to zero for the address to be 4k-aligned. In previous releases. the third and fourth DWORDs of a.." hexmask.long.tbyte 0x0 12.--31. 1. "CFG_AXIMSTR_MSG_ADDR_LOW,Lower 20 bits of the programmable AXI address for Messages. Note: This register field is sticky." newline hexmask.long.word 0x0 0.--11. 1. "CFG_AXIMSTR_MSG_ADDR_LOW_RESERVED,Reserved for future use. Note: This register field is sticky." line.long 0x4 "AXI_MSTR_MSG_ADDR_HIGH_OFF,Upper 32 bits of the programmable AXI address where Messages coming from wire are mapped to." hexmask.long 0x4 0.--31. 1. "CFG_AXIMSTR_MSG_ADDR_HIGH,Upper 32 bits of the programmable AXI address for Messages. Note: This register field is sticky." rgroup.long (0x1F8+0x700)++0x7 line.long 0x0 "PCIE_VERSION_NUMBER_OFF,PCIe Controller IIP Release Version Number. The version number is given in hex format. You should convert each pair of hex characters to ASCII to interpret. Using 4.70a (GA) as an example: - VERSION_NUMBER = 0x3437302a which.." hexmask.long 0x0 0.--31. 1. "VERSION_NUMBER,Version Number." line.long 0x4 "PCIE_VERSION_TYPE_OFF,PCIe Controller IIP Release Version Type. The type is given in hex format. You should convert each pair of hex characters to ASCII to interpret. Using 4.70a (GA) as an example: - VERSION_NUMBER = 0x3437302a which translates to 470*.." hexmask.long 0x4 0.--31. 1. "VERSION_TYPE,Version Type." group.long (0x240+0x700)++0x7 line.long 0x0 "MSIX_ADDRESS_MATCH_LOW_OFF,MSI-X Address Match Low Register. When you enable the MSI-X Table RAM feature (MSIX_TABLE_EN=1). the controller implements the logic and RAM required to generate MSI-X requests. For more details. see the Interrupts section in.." hexmask.long 0x0 2.--31. 1. "MSIX_ADDRESS_MATCH_LOW,MSI-X Address Match Low Address. Note: This register field is sticky." newline rbitfld.long 0x0 1. "MSIX_ADDRESS_MATCH_RESERVED_1,Reserved. Note: This register field is sticky." "0,1" newline bitfld.long 0x0 0. "MSIX_ADDRESS_MATCH_EN,MSI-X Match Enable. Enable the MSI-X Address Match feature when the AXI bridge is present. Note: This register field is sticky." "0,1" line.long 0x4 "MSIX_ADDRESS_MATCH_HIGH_OFF,MSI-X Address Match High Register. When you enable the MSI-X Table RAM feature (MSIX_TABLE_EN=1). the controller implements the logic and RAM required to generate MSI-X requests. For more details. see the Interrupts section in.." hexmask.long 0x4 0.--31. 1. "MSIX_ADDRESS_MATCH_HIGH,MSI-X Address Match High Address. Note: This register field is sticky." wgroup.long (0x248+0x700)++0x3 line.long 0x0 "MSIX_DOORBELL_OFF,MSI-X Doorbell Register. When you enable the MSI-X Table RAM feature (MSIX_TABLE_EN=1). the controller implements the logic and RAM required to generate MSI-X requests. For more details. see the Interrupts section in the 'Controller.." bitfld.long 0x0 29.--31. "MSIX_DOORBELL_RESERVED_29_31,Reserved." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x0 24.--28. 1. "MSIX_DOORBELL_PF,MSIX Doorbell Physical Function. This register determines the Physical Function for the MSI-X transaction." newline hexmask.long.byte 0x0 16.--23. 1. "MSIX_DOORBELL_VF,MSIX Doorbell Virtual Function. This register determines the Virtual Function for the MSI-X transaction." newline bitfld.long 0x0 15. "MSIX_DOORBELL_VF_ACTIVE,MSIX Doorbell Virtual Function Active. This register determines whether a Virtual Function is used to generate the MSI-X transaction." "0,1" newline bitfld.long 0x0 12.--14. "MSIX_DOORBELL_TC,MSIX Doorbell Traffic Class. This register determines which traffic class to generate the MSI-X transaction with." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 11. "MSIX_DOORBELL_RESERVED_11,Reserved." "0,1" newline hexmask.long.word 0x0 0.--10. 1. "MSIX_DOORBELL_VECTOR,MSI-X Doorbell Vector. This register determines which vector to generate the MSI-X transaction for." group.long (0x24C+0x700)++0x3 line.long 0x0 "MSIX_RAM_CTRL_OFF,MSI-X RAM power mode and debug control register. When you enable the MSI-X Table RAM feature (MSIX_TABLE_EN=1). the controller implements the logic and RAM required to generate MSI-X requests. For more details. see the Interrupts.." hexmask.long.byte 0x0 26.--31. 1. "MSIX_RAM_CTRL_RESERVED_26_31,Reserved. Note: This register field is sticky." newline bitfld.long 0x0 25. "MSIX_RAM_CTRL_DBG_PBA,MSIX PBA RAM Debug Mode. Use this bit to activate the debug mode and allow direct read/write access to the PBA. Use can also use the dbg_pba input to activate debug mode. Debug mode turns off the PF/VF/Offset-based addressing into.." "0,1" newline bitfld.long 0x0 24. "MSIX_RAM_CTRL_DBG_TABLE,MSIX Table RAM Debug Mode. Use this bit to activate the debug mode and allow direct read/write access to the Table. Use can also use the dbg_table input to activate debug mode. Debug mode turns off the PF/VF/Offset-based.." "0,1" newline hexmask.long.byte 0x0 17.--23. 1. "MSIX_RAM_CTRL_RESERVED_17_23,Reserved. Note: This register field is sticky." newline bitfld.long 0x0 16. "MSIX_RAM_CTRL_BYPASS,MSIX RAM Control Bypass. The bypass field when set disables the internal generation of low power signals for both RAMs. It is up to the application to ensure the RAMs are in the proper power state before trying to access them." "0,1" newline hexmask.long.byte 0x0 10.--15. 1. "MSIX_RAM_CTRL_RESERVED_10_15,Reserved. Note: This register field is sticky." newline bitfld.long 0x0 9. "MSIX_RAM_CTRL_PBA_SD,MSIX PBA RAM Shut Down. Set this bit to drive the cfg_msix_pba_sd output to signal your external logic to place the MSIX PBA RAM in Shut Down low-power mode. Note: This register field is sticky." "0,1" newline bitfld.long 0x0 8. "MSIX_RAM_CTRL_PBA_DS,MSIX PBA RAM Deep Sleep. Set this bit to drive the cfg_msix_pba_ds output to signal your external logic to place the MSIX PBA RAM in Deep Sleep low-power mode. Note: This register field is sticky." "0,1" newline hexmask.long.byte 0x0 2.--7. 1. "MSIX_RAM_CTRL_RESERVED_2_7,Reserved. Note: This register field is sticky." newline bitfld.long 0x0 1. "MSIX_RAM_CTRL_TABLE_SD,MSIX Table RAM Shut Down. Set this bit to drive the cfg_msix_table_sd output to signal your external logic to place the MSIX Table RAM in Shut Down low-power mode. Note: This register field is sticky." "0,1" newline bitfld.long 0x0 0. "MSIX_RAM_CTRL_TABLE_DS,MSIX Table RAM Deep Sleep. Set this bit to drive the cfg_msix_table_ds output to signal your external logic to place the MSIX Table RAM in Deep Sleep low-power mode. Note: This register field is sticky." "0,1" group.long (0x430+0x700)++0x3 line.long 0x0 "PL_LTR_LATENCY_OFF,LTR Latency Register. The function of this register field (and all other fields in this register) differs between an upstream port and a downstream port. For an upstream port. the register fields capture the corresponding fields in the.." bitfld.long 0x0 31. "NO_SNOOP_LATENCY_REQUIRE,No Snoop Latency Requirement. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" "0,1" newline rbitfld.long 0x0 29.--30. "RSVDP_29,Reserved for future use." "0,1,2,3" newline bitfld.long 0x0 26.--28. "NO_SNOOP_LATENCY_SCALE,No Snoop Latency Scale. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" "0,1,2,3,4,5,6,7" newline hexmask.long.word 0x0 16.--25. 1. "NO_SNOOP_LATENCY_VALUE,No Snoop Latency Value. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" newline bitfld.long 0x0 15. "SNOOP_LATENCY_REQUIRE,Snoop Latency Requirement. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" "0,1" newline rbitfld.long 0x0 13.--14. "RSVDP_13,Reserved for future use." "0,1,2,3" newline bitfld.long 0x0 10.--12. "SNOOP_LATENCY_SCALE,Snoop Latency Scale. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" "0,1,2,3,4,5,6,7" newline hexmask.long.word 0x0 0.--9. 1. "SNOOP_LATENCY_VALUE,Snoop Latency Value. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" group.long (0x440+0x700)++0xB line.long 0x0 "AUX_CLK_FREQ_OFF,Auxiliary Clock Frequency Control Register." hexmask.long.tbyte 0x0 10.--31. 1. "RSVDP_10,Reserved for future use." newline hexmask.long.word 0x0 0.--9. 1. "AUX_CLK_FREQ,The aux_clk frequency in MHz. This value is used to provide a 1 us reference for counting time during low-power states with aux_clk when the PHY has removed the pipe_clk. Frequencies lower than 1 MHz are possible but with a loss of accuracy.." line.long 0x4 "L1_SUBSTATES_OFF,L1 Substates Timing Register." hexmask.long.tbyte 0x4 9.--31. 1. "RSVDP_9,Reserved for future use." newline bitfld.long 0x4 8. "L1SUB_LOW_POWER_CLOCK_SWITCH_MODE,If this bit is set to 1'b1 the reference clock will be running regardless of the CLKREQ# setting. If this bit is set to 1'b0 the reference clock may be gated off when CLKREQ# is de-asserted. If the bit is set to 1'b1 the.." "0,1" newline bitfld.long 0x4 6.--7. "L1SUB_T_PCLKACK,Max delay (in 1us units) between a MAC request to remove the clock on mac_phy_pclkreq_n and a PHY response on phy_mac_pclkack_n. If the PHY does not respond within this time the request is aborted.The actual timeout value will be.." "0,1,2,3" newline hexmask.long.byte 0x4 2.--5. 1. "L1SUB_T_L1_2,Duration (in 1us units) of L1.2. The actual timeout value will be L1SUB_T_L1_2 + 1. Range is 0.15. Note: This register field is sticky." newline bitfld.long 0x4 0.--1. "L1SUB_T_POWER_OFF,Duration (in 1us units) of L1.2.Entry. The actual timeout value will be L1SUB_T_POWER_OFF + 1. Range is 0.3. Note: This register field is sticky." "0,1,2,3" line.long 0x8 "POWERDOWN_CTRL_STATUS_OFF,Powerdown Control and Status Register." hexmask.long.tbyte 0x8 12.--31. 1. "RSVDP_12,Reserved for future use." newline hexmask.long.byte 0x8 8.--11. 1. "POWERDOWN_PHY_POWERDOWN,This field represents the Powerdown value that has been acknowledged by the PHY. It is updated with the value of Powerdown driven by the controller when the PHY has returned the Phystatus acknowledgment for the Powerdown.." newline hexmask.long.byte 0x8 4.--7. 1. "POWERDOWN_MAC_POWERDOWN,This field represents the Powerdown value driven by the controller to the PHY." newline rbitfld.long 0x8 1.--3. "RSVDP_1,Reserved for future use." "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 0. "POWERDOWN_FORCE,This field is a one shot field. Writing a value of 1 to this field causes the controller to complete the P2 Powerdown handshake regardless of whether the PHY has returned Phystatus. This field could be used for debug purposes in event.." "0,1" group.long (0x470+0x700)++0x7 line.long 0x0 "PHY_VIEWPORT_CTLSTS_OFF,PHY Register Viewport Control and Status Register." rbitfld.long 0x0 31. "PHY_VIEWPORT_PENDING,PHY viewport pending. Indicates the access is pending. - 1 : Pending - 0 : Idle This bit is set to 1 when the read/write access has been initiated. This bit is cleared when the access is completed. If phy_reg_clk_g is never activated.." "Idle,Pending" newline rbitfld.long 0x0 30. "PHY_VIEWPORT_STATUS,PHY viewport status. Indicates the status of the latest access. - 1 : Timeout - 0 : No errors If the timeout is detected this bit is set to 1 and PHY_VIEWPORT_PENDING is cleared. This bit is cleared when the read/write access is.." "No errors,Timeout" newline hexmask.long.byte 0x0 23.--29. 1. "RSVDP_23,Reserved for future use." newline bitfld.long 0x0 22. "PHY_VIEWPORT_TIMEOUT_DISABLE,PHY viewport timeout disable. Disables the PHY register access timeout structure. When the timeout is disabled you must ensure that the PHY register accesses are always acknowledged by cr_para_ack. Otherwise.." "0,1" newline bitfld.long 0x0 21. "PHY_VIEWPORT_BCWR,Broadcast write access to all xN sub-blocks. If you need to broadcast the write accesses into all lanes both PHY_VIEWPORT_ADDR[15] and this bit should be 1. Note: This register field is sticky." "0,1" newline bitfld.long 0x0 20. "PHY_VIEWPORT_READ,PHY viewport read. If set a read access is initiated. The value is always 0 when this bit is read. Note: This register field is sticky." "0,1" newline hexmask.long.byte 0x0 16.--19. 1. "PHY_VIEWPORT_NUM,PHY viewport xN sub-block number. Selects one of xN sub-blocks. This register is not used when the write access is initiated with PHY_VIEWPORT_BCWR==1. Note: This register field is sticky." newline hexmask.long.word 0x0 0.--15. 1. "PHY_VIEWPORT_ADDR,PHY viewport address. Indicates the PHY's register address. Please refer to the PHY databook for the address map definition. Note: This register field is sticky." line.long 0x4 "PHY_VIEWPORT_DATA_OFF,PHY Register Viewport Data Register." hexmask.long.word 0x4 16.--31. 1. "RSVDP_16,Reserved for future use." newline hexmask.long.word 0x4 0.--15. 1. "PHY_VIEWPORT_DATA,PHY viewport data. A write access to this register initiates the PHY register write access. By a read access to this register this field returns the latest read data from the PHY register. Note: This register field is sticky." group.long (0x490+0x700)++0x3 line.long 0x0 "PIPE_RELATED_OFF,PIPE Related Register. This register controls the pipe's capabitity. control. and status parameters." hexmask.long.tbyte 0x0 9.--31. 1. "RSVDP_9,Reserved for future use." newline bitfld.long 0x0 8. "PIPE_GARBAGE_DATA_MODE,PIPE Garbage Data Mode. - 0: PIPE Spec compliant mode: The MAC discards any symbols received after the electrical idle ordered-set until RxValid is deasserted. - 1: Special PHY Support mode: The MAC discards any symbols received.." "PIPE Spec compliant mode: The MAC discards any..,Special PHY Support mode: The MAC discards any.." tree.end tree.end tree "PCIE1_VF23" base ad:0x31040000 tree "PF0_TYPE1_HDR (PCI-Compatible Configuration Space Header Type1)" group.long 0x0++0x2F line.long 0x0 "TYPE1_DEV_ID_VEND_ID_REG,Device ID and Vendor ID Register." hexmask.long.word 0x0 16.--31. 1. "DEVICE_ID,Device ID. The Device ID register identifies the particular Function. This identifier is allocated by the vendor. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else.." newline hexmask.long.word 0x0 0.--15. 1. "VENDOR_ID,Vendor ID. The Vendor ID register identifies the manufacturer of the Function. Valid vendor identifiers are allocated by the PCI-SIG to ensure uniqueness. It is not permitted to populate this register with a value of FFFFh which is an invalid.." line.long 0x4 "TYPE1_STATUS_COMMAND_REG,Status and Command Register." bitfld.long 0x4 31. "DETECTED_PARITY_ERROR,Detected Parity Error. This bit is set by a Function whenever it receives a Poisoned TLP regardless of the state the Parity Error Response bit in the Command register. The bit is set when the Poisoned TLP is received by a.." "0,1" newline bitfld.long 0x4 30. "SIGNALED_SYS_ERROR,Signaled System Error. This bit is set when a Function sends an ERR_FATAL or ERR_NONFATAL Message and the SERR# Enable bit in the Command register is 1b." "0,1" newline bitfld.long 0x4 29. "RCVD_MASTER_ABORT,Received Master Abort. This bit is set when a Requester receives a Completion with Unsupported Request Completion status. The bit is set when the Unsupported Request is received by a Function's primary side." "0,1" newline bitfld.long 0x4 28. "RCVD_TARGET_ABORT,Received Target Abort. This bit is set when a Requester receives a Completion with Completer Abort Completion status. The bit is set when the Completer Abort is received by a Function's primary side." "0,1" newline bitfld.long 0x4 27. "SIGNALED_TARGET_ABORT,Signaled Target Abort. This bit is set when a Function completes a Posted or Non-Posted Request as a Completer Abort error. This applies to a Function when the Completer Abort was generated by its primary side." "0,1" newline rbitfld.long 0x4 25.--26. "DEV_SEL_TIMING,DEVSEL Timing. This field was originally described in the PCI Local Bus Specification. Its functionality does not apply to PCI Express. The controller hardwires it to 00b." "0,1,2,3" newline bitfld.long 0x4 24. "MASTER_DPE,Master Data Parity Error. This bit is set by a Function if the Parity Error Response bit in the Command register is 1b and either of the following two conditions occurs: - Port receives a Poisoned Completion going downstream - Port transmits a.." "0,1" newline rbitfld.long 0x4 23. "FAST_B2B_CAP,Fast Back-to-Back Transactions Capable. This bit was originally described in the PCI Local Bus Specification. Its functionality does not apply to PCI Express. The controller hardwires this bit to 0b." "0,1" newline rbitfld.long 0x4 22. "RSVDP_22,Reserved for future use." "0,1" newline rbitfld.long 0x4 21. "FAST_66MHZ_CAP,66 MHz Capable. This bit was originally described in the PCI Local Bus Specification. Its functionality does not apply to PCI Express. The controller hardwires this bit to 0b." "0,1" newline rbitfld.long 0x4 20. "CAP_LIST,Capabilities List. Indicates the presence of an Extended Capability list item. Since all PCI Express device Functions are required to implement the PCI Express Capability structure the controller hardwires this bit to 1b." "0,1" newline rbitfld.long 0x4 19. "INT_STATUS,Interrupt Status. When set indicates that an INTx emulation interrupt is pending internally in the Function. INTx emulation interrupts forwarded by Functions from the secondary side are not reflected in this bit. Setting the Interrupt Disable.." "0,1" newline rbitfld.long 0x4 17.--18. "RSVDP_17,Reserved for future use." "0,1,2,3" newline bitfld.long 0x4 16. "IMM_READINESS,Immediate Readiness. This optional bit when set indicates the Function is guaranteed to be ready to successfully complete valid configuration accesses at any time following any reset that the host is capable of issuing Configuration.." "0,1" newline hexmask.long.byte 0x4 11.--15. 1. "RESERV,Reserved." newline bitfld.long 0x4 10. "INT_EN,Interrupt Disable. Controls the ability of a Function to generate INTx emulation interrupts. When set Functions are prevented from asserting INTx interrupts. Note: - Any INTx emulation interrupts already asserted by the Function must be.." "0,1" newline rbitfld.long 0x4 9. "RSVDP_9,Reserved for future use." "0,1" newline bitfld.long 0x4 8. "SERREN,SERR# Enable. When set this bit enables reporting upstream of Non-fatal and Fatal errors detected by the Function. Note: The errors are reported if enabled either through this bit or through the PCI Express specific bits in the Device Control.." "0,1" newline rbitfld.long 0x4 7. "IDSEL,IDSEL Stepping/Wait Cycle Control. This bit was originally described in the PCI Local Bus Specification. Its functionality does not apply to PCI Express. The controller hardwires this bit to 0b." "0,1" newline bitfld.long 0x4 6. "PERREN,Parity Error Response. This bit controls the logging of poisoned TLPs in the Master Data Parity Error bit in the Status register. For more details see the 'Error Registers' section of the PCI Express Base Specification." "0,1" newline rbitfld.long 0x4 5. "VGAPS,VGA Palette Snoop. This bit was originally described in the PCI Local Bus Specification and the PCI-to-PCI Bridge Architecture Specification. Its functionality does not apply to PCI Express. The controller hardwires this bit to 0b." "0,1" newline rbitfld.long 0x4 4. "MWI_EN,Memory Write and Invalidate. This bit was originally described in the PCI Local Bus Specification and the PCI-to-PCI Bridge Architecture Specification. Its functionality does not apply to PCI Express. The controller hardwires this bit to 0b. For.." "0,1" newline rbitfld.long 0x4 3. "SCO,Special Cycle Enable. This bit was originally described in the PCI Local Bus Specification. Its functionality does not apply to PCI Express. The controller hardwires this bit to 0b." "0,1" newline bitfld.long 0x4 2. "BME,Bus Master Enable. This bit controls forwarding of Memory or I/O requests by a port in the Upstream direction. When this bit is 0b Memory and I/O Requests received at a Root Port must be handled as Unsupported Requests (UR) For Non-Posted Requests a.." "0,1" newline bitfld.long 0x4 1. "MSE,Memory Space Enable. This bit controls a Function's response to Memory Space accesses received on its primary side. - When set the Function is enabled to decode the address and further process Memory Space accesses. - When clear all received Memory.." "0,1" newline bitfld.long 0x4 0. "IO_EN,IO Space Enable. This bit controls a Function's response to I/O Space accesses received on its primary side. - When set the Function is enabled to decode the address and further process I/O Space accesses. - When clear all received I/O accesses.." "0,1" line.long 0x8 "TYPE1_CLASS_CODE_REV_ID_REG,Class Code and Revision ID Register." hexmask.long.byte 0x8 24.--31. 1. "BASE_CLASS_CODE,Base Class Code. A code that broadly classifies the type of operation the Function performs. Encodings for base class are provided in the PCI Code and ID Assignment Specification. All unspecified encodings are reserved. Note: The access.." newline hexmask.long.byte 0x8 16.--23. 1. "SUBCLASS_CODE,Sub-Class Code. Specifies a base class sub-class which identifies more specifically the operation of the Function. Encodings for sub-class are provided in the PCI Code and ID Assignment Specification. All unspecified encodings are.." newline hexmask.long.byte 0x8 8.--15. 1. "PROGRAM_INTERFACE,Programming Interface. This field identifies a specific register level programming interface (if any) so that device independent software can interact with the Function. Encodings for interface are provided in the PCI Code and ID.." newline hexmask.long.byte 0x8 0.--7. 1. "REVISION_ID,Revision ID. The value of this field specifies a Function specific revision identifier. The value is chosen by the vendor. Zero is an acceptable value. The Revision ID should be viewed as a vendor defined extension to the Device ID. Note: The.." line.long 0xC "TYPE1_BIST_HDR_TYPE_LAT_CACHE_LINE_SIZE_REG,BIST. Header Type. Latency Timer. and Cache Line Size Register." hexmask.long.byte 0xC 24.--31. 1. "BIST,BIST. This register is used for control and status of BIST. Functions that do not support BIST must hardwire the register to 00h. A Function whose BIST is invoked must not prevent normal operation of the PCI Express Link. Bit descriptions: - [31]:.." newline rbitfld.long 0xC 23. "MULTI_FUNC,Multi-Function Device. - When set indicates that the device may contain multiple Functions but not necessarily. Software is permitted to probe for Functions other than Function 0. - When clear software must not probe for Functions other.." "0,1" newline hexmask.long.byte 0xC 16.--22. 1. "HEADER_TYPE,Header Layout. This field identifies the layout of the second part of the predefined header. The controller uses 000 0001b encoding. The encoding 000 0010b is reserved. This encoding was originally described in the PC Card Standard Electrical.." newline hexmask.long.byte 0xC 8.--15. 1. "LATENCY_MASTER_TIMER,Latency Timer. This register is also referred to as Primary Latency Timer. The Latency Timer was originally described in the PCI Local Bus Specification and the PCI-to-PCI Bridge Architecture Specification. Its functionality does not.." newline hexmask.long.byte 0xC 0.--7. 1. "CACHE_LINE_SIZE,Cache Line Size. The Cache Line Size register is programmed by the system firmware or the operating system to system cache line size. However legacy conventional PCI software may not always be able to program this register correctly.." line.long 0x10 "BAR0_REG,BAR0 Register. System software must build a consistent address map before booting the machine to an operating system. This means it has to determine how much memory is in the system. and how much address space the Functions in the system.." hexmask.long 0x10 4.--31. 1. "BAR0_START,BAR0 Base Address. - Memory Space: Base Address. - IO Space: bits[31:2] are used to map the function into IO space/Base. Address. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R(Sticky)/W(Sticky) if.." newline bitfld.long 0x10 3. "BAR0_PREFETCH,BAR0 Prefetchable. - Memory Space: Set to one if data is pre-fetchable. A Function is permitted to mark a range as prefetchable. If there are no side effects on reads the function returns all bytes on reads regardless of the byte enables.." "0,1" newline bitfld.long 0x10 1.--2. "BAR0_TYPE,BAR0 Type. - Memory Space: Base Address registers that map into Memory Space can be 32 bits or 64 bits wide (to support mapping into a 64-bit address space). The bit encoding is as follows: -- 00: Base register is 32 bits wide and can be mapped.." "Base register is 32 bits wide and can be mapped..,Reserved,?,?" newline bitfld.long 0x10 0. "BAR0_MEM_IO,BAR0 Memory Space Indicator. This bit is used to determine whether the register maps into Memory or I/O Space. Base Address registers that map to Memory Space must return a 0b. Base Address registers that map to I/O Space must return a 1b." "0,1" line.long 0x14 "BAR1_REG,BAR1 Register. System software must build a consistent address map before booting the machine to an operating system. This means it has to determine how much memory is in the system. and how much address space the Functions in the system.." hexmask.long 0x14 4.--31. 1. "BAR1_START,BAR1 Base Address. - Memory Space: Base Address. - IO Space: bits[31:2] are used to map the function into IO space/Base. Address. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R(Sticky)/W(Sticky) if.." newline bitfld.long 0x14 3. "BAR1_PREFETCH,BAR1 Prefetchable. - Memory Space: Set to one if data is pre-fetchable. A Function is permitted to mark a range as prefetchable. If there are no side effects on reads the function returns all bytes on reads regardless of the byte enables.." "0,1" newline bitfld.long 0x14 1.--2. "BAR1_TYPE,BAR1 Type. - Memory Space: Base Address registers that map into Memory Space can be 32 bits or 64 bits wide (to support mapping into a 64-bit address space). The bit encoding is as follows: -- 00: Base register is 32 bits wide and can be mapped.." "Base register is 32 bits wide and can be mapped..,Reserved,?,?" newline bitfld.long 0x14 0. "BAR1_MEM_IO,BAR1 Memory Space Indicator. This bit is used to determine whether the register maps into Memory or I/O Space. Base Address registers that map to Memory Space must return a 0b. Base Address registers that map to I/O Space must return a 1b." "0,1" line.long 0x18 "SEC_LAT_TIMER_SUB_BUS_SEC_BUS_PRI_BUS_REG,Secondary Latency Timer. Subordinate Bus Number. Secondary Bus Number. and Primary Bus Number Register." hexmask.long.byte 0x18 24.--31. 1. "SEC_LAT_TIMER,Secondary Latency Timer. This register does not apply to PCI Express. The controller hardwires it to 00h." newline hexmask.long.byte 0x18 16.--23. 1. "SUB_BUS,Subordinate Bus Number. The Subordinate Bus Number register is used to record the bus number of the highest numbered PCI bus segment which is behind (or subordinate to) the bridge. Configuration software programs the value in this register. The.." newline hexmask.long.byte 0x18 8.--15. 1. "SEC_BUS,Secondary Bus Number. The Secondary Bus Number register is used to record the bus number of the PCI bus segment to which the secondary interface of the bridge is connected. Configuration software programs the value in this register. The bridge.." newline hexmask.long.byte 0x18 0.--7. 1. "PRIM_BUS,Primary Bus Number. This register is not used by PCI Express Functions. It is implemented for compatibility with legacy software." line.long 0x1C "SEC_STAT_IO_LIMIT_IO_BASE_REG,Secondary Status. and I/O Limit and Base Register. The I/O Limit and I/O Base registers are optional and define an address range that is used by the bridge to determine when to forward I/O transactions from one interface to.." bitfld.long 0x1C 31. "SEC_STAT_DPE,Detected Parity Error. This bit is set by a Function when a Poisoned TLP is received by its secondary side regardless of the state the Parity Error Response Enable bit in the Bridge Control register." "0,1" newline bitfld.long 0x1C 30. "SEC_STAT_RCVD_SYS_ERR,Received System Error. This bit is set when the secondary side of a Function receives an ERR_FATAL or ERR_NONFATAL message." "0,1" newline bitfld.long 0x1C 29. "SEC_STAT_RCVD_MSTR_ABRT,Received Master Abort. This bit is set when the secondary side of a Function (for requests initiated by the Type 1 header Function itself) receives a Completion with Unsupported Request Completion status." "0,1" newline bitfld.long 0x1C 28. "SEC_STAT_RCVD_TRGT_ABRT,Received Target Abort. This bit is set when the secondary side of a Function (for requests initiated by the Type 1 header Function itself) receives a Completion with Completer Abort Completion status." "0,1" newline bitfld.long 0x1C 27. "SEC_STAT_SIG_TRGT_ABRT,Signaled Target Abort. This bit is set when the secondary side of the Function (for Requests completed by the Type 1 header Function itself) completes a Posted or Non-Posted request as a Completer Abort error." "0,1" newline rbitfld.long 0x1C 25.--26. "RSVDP_25,Reserved for future use." "0,1,2,3" newline bitfld.long 0x1C 24. "SEC_STAT_MDPE,Master Data Parity Error. This bit is set by a Function if the Parity Error Response Enable bit in the Bridge Control register is set and either of the following two conditions occurs: - Port receives a Poisoned Completion coming Upstream.." "0,1" newline rbitfld.long 0x1C 23. "RSVDP_23,Reserved for future use." "0,1" newline hexmask.long.byte 0x1C 16.--22. 1. "SEC_STAT_RESERV,Reserved." newline hexmask.long.byte 0x1C 12.--15. 1. "IO_LIMIT,I/O Limit Address. These bits correspond to the address[15:12] of IO address range. For the purpose of address decoding the bridge assumes that the lower 12 address bits address[11:0] of the I/O limit address (not implemented in the I/O Limit.." newline rbitfld.long 0x1C 9.--11. "IO_RESERV1,Reserved." "0,1,2,3,4,5,6,7" newline bitfld.long 0x1C 8. "IO_DECODE_BIT8,I/O Addressing Encode (IO Limit Address). This bit encodes the IO addressing capability of the bridge. IO_DECODE_BIT8 indicates the following: - 0h: The bridge supports only 16-bit I/O addressing (for ISA compatibility). For the purpose of.." "0,1" newline hexmask.long.byte 0x1C 4.--7. 1. "IO_BASE,I/O Base Address. These bits correspond to the address[15:12] of IO address range. For the purpose of address decoding the bridge assumes that the lower 12 address bits address[11:0] of the I/O base address (not implemented in the I/O Base.." newline rbitfld.long 0x1C 1.--3. "IO_RESERV,Reserved." "0,1,2,3,4,5,6,7" newline bitfld.long 0x1C 0. "IO_DECODE,I/O Addressing Encode (IO Base Address) This bit encodes the IO addressing capability of the bridge. IO_DECODE indicates the following: - 0h: The bridge supports only 16-bit I/O addressing (for ISA compatibility). For the purpose of address.." "0,1" line.long 0x20 "MEM_LIMIT_MEM_BASE_REG,Memory Limit and Base Register. The Memory Limit and Memory Base registers define a memory mapped address range which is used by the bridge to determine when to forward memory transactions from one interface to the other. If there.." hexmask.long.word 0x20 20.--31. 1. "MEM_LIMIT,Memory Limit Address. These bits correspond to the upper 12 address bits Address[31:20] of 32-bit addresses. For the purpose of address decoding the bridge assumes that the lower 20 address bits Address[19:0] of the memory limit address.." newline hexmask.long.byte 0x20 16.--19. 1. "MEM_LIMIT_RESERV,Reserved." newline hexmask.long.word 0x20 4.--15. 1. "MEM_BASE,Memory Base Address. These bits correspond to the upper 12 address bits Address[31:20] of 32-bit addresses. For the purpose of address decoding the bridge assumes that the lower 20 address bits Address[19:0] of the memory base address (not.." newline hexmask.long.byte 0x20 0.--3. 1. "MEM_BASE_RESERV,Reserved." line.long 0x24 "PREF_MEM_LIMIT_PREF_MEM_BASE_REG,Prefetchable Memory Limit and Base Register. The Prefetchable Memory Limit and Prefetchable Memory Base registers must indicate that 64-bit addresses are supported. as defined in PCI-to-PCI Bridge Architecture.." hexmask.long.word 0x24 20.--31. 1. "PREF_MEM_LIMIT,Prefetchable Memory Limit Address. If the Prefetchable Memory Limit register indicates support for 32-bit addressing then the Prefetchable Limit Upper 32 Bits register is implemented as a read-only register that returns zero when read. If.." newline rbitfld.long 0x24 17.--19. "PREF_RESERV1,Reserved." "0,1,2,3,4,5,6,7" newline rbitfld.long 0x24 16. "PREF_MEM_LIMIT_DECODE,Prefetchable Memory Limit Decode. This bit encodes whether or not the bridge supports 64-bit addresses. Note: This bit is a copy of the PREF_MEM_DECODE bit and always reflects the current value of that bit. The value of.." "0,1" newline hexmask.long.word 0x24 4.--15. 1. "PREF_MEM_BASE,Prefetchable Memory Base Address. If the Prefetchable Memory Base register indicates support for 32-bit addressing then the Prefetchable Base Upper 32 Bits register is implemented as a read-only register that returns zero when read. If the.." newline rbitfld.long 0x24 1.--3. "PREF_RESERV,Reserved." "0,1,2,3,4,5,6,7" newline bitfld.long 0x24 0. "PREF_MEM_DECODE,Prefetchable Memory Base Decode. This bit encodes whether or not the bridge supports 64-bit addresses. Note: By default the bit is set to 1'b1 indicating that 64-bit addresses are supported. If the bridge only supports 32-bit prefetchable.." "0,1" line.long 0x28 "PREF_BASE_UPPER_REG,Prefetchable Base Upper 32 Bits Register. The Prefetchable Base Upper 32 Bits register is an optional extension to the Prefetchable Memory Base register." hexmask.long 0x28 0.--31. 1. "PREF_MEM_BASE_UPPER,Prefetchable Base Upper 32 Bit. If the Prefetchable Memory Base register indicates support for 32-bit addressing then this register is implemented as read-only register that returns zero when read. If the Prefetchable Memory Base.." line.long 0x2C "PREF_LIMIT_UPPER_REG,Prefetchable Limit Upper 32 Bits Register. The Prefetchable Limit Upper 32 Bits register is an optional extension to the Prefetchable Memory Limit register." hexmask.long 0x2C 0.--31. 1. "PREF_MEM_LIMIT_UPPER,Prefetchable Limit Upper 32 Bit. If the Prefetchable Memory Limit register indicate support for 64-bit addressing then this register is implemented as read/write register which must be initialized by configuration software. This.." rgroup.long 0x30++0x3 line.long 0x0 "IO_LIMIT_UPPER_IO_BASE_UPPER_REG,I/O Limit and Base Upper 16 Bits Register. The I/O Limit Upper 16 Bits and I/O Base Upper 16 Bits registers are optional extensions to the I/O Limit and I/O Base registers." hexmask.long.word 0x0 16.--31. 1. "IO_LIMIT_UPPER,I/O Limit Upper 16 Bits. If the I/O Limit register indicates support for 16-bit I/O address decoding then this register is implemented as a read-only register which return zero when read. If the I/O Limit register indicates support for.." newline hexmask.long.word 0x0 0.--15. 1. "IO_BASE_UPPER,I/O Base Upper 16 Bits. If the I/O Base register indicates support for 16-bit I/O address decoding then this register is implemented as a read-only register which return zero when read. If the I/O base register indicates support for 32-bit.." group.long 0x34++0xB line.long 0x0 "TYPE1_CAP_PTR_REG,Capabilities Pointer Register." hexmask.long.tbyte 0x0 8.--31. 1. "RSVDP_8,Reserved for future use." newline hexmask.long.byte 0x0 0.--7. 1. "CAP_POINTER,Capabilities Pointer. This register is used to point to a linked list of capabilities implemented by this Function. Since all PCI Express Functions are required to implement the PCI Express Capability structure this register must point to a.." line.long 0x4 "TYPE1_EXP_ROM_BASE_REG,Expansion ROM Base Address Register. This register is defined to handle the base address and size information for this expansion ROM. The mask for this ROM BAR exists (if implemented) as a shadow register at this address. The.." hexmask.long.tbyte 0x4 11.--31. 1. "EXP_ROM_BASE_ADDRESS,Expansion ROM Base Address. Upper 21 bits of the Expansion ROM base address. The number of bits (out of these 21) that a Function actually implements depends on how much address space the Function requires. The mask for this ROM BAR.." newline hexmask.long.word 0x4 1.--10. 1. "RSVDP_1,Reserved for future use." newline bitfld.long 0x4 0. "ROM_BAR_ENABLE,Expansion ROM Enable. This bit controls whether or not the Function accepts accesses to its expansion ROM. When this bit is 0b the Function's expansion ROM address space is disabled. When the bit is 1b address decoding is enabled using.." "0,1" line.long 0x8 "BRIDGE_CTRL_INT_PIN_INT_LINE_REG,Bridge Control. Interrupt Pin. and Interrupt Line Register." hexmask.long.word 0x8 23.--31. 1. "BRIDGE_CTRL_RESERV,Reserved." newline bitfld.long 0x8 22. "SBR,Secondary Bus Reset. Setting this bit triggers a hot reset on the corresponding PCI Express Port. Software must ensure a minimum reset duration (Trst) as defined in the PCI Local Bus Specification. Software and systems must honor.." "0,1" newline rbitfld.long 0x8 21. "MSTR_ABORT_MODE,Master Abort Mode. This bit was originally described in the PCI-to-PCI Bridge Architecture Specification. Its functionality does not apply to PCI Express. The controller hardwires this bit to 0b. Note: The access attributes of this field.." "0,1" newline rbitfld.long 0x8 20. "VGA_16B_DEC,VGA 16 bit decode. This bit only has meaning if VGA Enable bit is set. This bit enables system configuration software to select between 10-bit and 16-bit I/O address decoding for all VGA I/O register accesses that are forwarded from primary.." "0,1" newline rbitfld.long 0x8 19. "VGA_EN,VGA Enable. Modifies the response by the bridge to VGA compatible addresses. If the VGA Enable bit is set the bridge will positively decode and forward the following accesses on the primary interface to the secondary interface (and conversely.." "0,1" newline bitfld.long 0x8 18. "ISA_EN,ISA Enable. Modifies the response by the bridge to ISA I/O addresses. This applies only to I/O addresses that are enabled by the I/O Base and I/O Limit registers and are in the first 64 KB of I/O address space (0000 0000h to 0000 FFFFh). If this.." "?,KB block" newline bitfld.long 0x8 17. "SERR_EN,SERR# Enable. This bit controls forwarding of ERR_COR ERR_NONFATAL and ERR_FATAL from secondary to primary." "0,1" newline bitfld.long 0x8 16. "PERE,Parity Error Response Enable. This bit controls the logging of poisoned TLPs in the Master Data Parity Error bit in the Secondary Status register." "0,1" newline hexmask.long.byte 0x8 8.--15. 1. "INT_PIN,Interrupt PIN. The Interrupt Pin register register that identifies the legacy interrupt Message(s) the Function uses. Valid values are: - 01h 02h 03h and 04h: map to legacy interrupt Messages for INTA INTB INTC and INTD respectively. - 00h:.." newline hexmask.long.byte 0x8 0.--7. 1. "INT_LINE,Interrupt Line. The Interrupt Line register communicates interrupt line routing information. The register must be implemented by any Function that uses an interrupt pin. Values in this register are programmed by system software and are system.." tree.end tree "PF0_SPCIE_CAP (Secondary PCI Express Capability Structure)" group.long (0x0+0x1A0)++0xF line.long 0x0 "SPCIE_CAP_HEADER_REG,SPCIE Capability Header. For a description of this standard PCIe register. see the PCI Express Specification." hexmask.long.word 0x0 20.--31. 1. "NEXT_OFFSET,Next Capability Offset. For a description of this standard PCIe register field see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky).." hexmask.long.byte 0x0 16.--19. 1. "CAP_VERSION,Capability Version. For a description of this standard PCIe register field see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else.." hexmask.long.word 0x0 0.--15. 1. "EXTENDED_CAP_ID,Secondary PCI Express Extended Capability ID. For a description of this standard PCIe register field see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN.." line.long 0x4 "LINK_CONTROL3_REG,Link Control 3 Register. For a description of this standard PCIe register. see the PCI Express Specification." hexmask.long 0x4 2.--31. 1. "RSVDP_2,Reserved for future use." bitfld.long 0x4 1. "EQ_REQ_INT_EN,Link Equalization Request Interrupt Enable. For a description of this standard PCIe register field see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" "0,1" bitfld.long 0x4 0. "PERFORM_EQ,Perform Equalization. For a description of this standard PCIe register field see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" "0,1" line.long 0x8 "LANE_ERR_STATUS_REG,Lane Error Status Register. For a description of this standard PCIe register. see the PCI Express Specification." hexmask.long 0x8 2.--31. 1. "RSVDP_LANE_ERR_STATUS,Reserved for future use." bitfld.long 0x8 0.--1. "LANE_ERR_STATUS,Lane Error Status Bits per Lane. For a description of this standard PCIe register field see the PCI Express Specification." "0,1,2,3" line.long 0xC "SPCIE_CAP_OFF_0CH_REG,Lane Equalization Control Register for lanes 1 and 0. For a description of this standard PCIe register. see the PCI Express Specification." rbitfld.long 0xC 31. "RSVDP_31,Reserved for future use." "0,1" bitfld.long 0xC 28.--30. "USP_RX_PRESET_HINT1,Upstream Port 8.0 GT/s Receiver Preset Hint 1. The write value is gated with the PCIE_CAP_CROSS_LINK_SUPPORT field of LINK_CAPABILITIES2_REG. For a description of this standard PCIe register field see the PCI Express Specification." "0,1,2,3,4,5,6,7" hexmask.long.byte 0xC 24.--27. 1. "USP_TX_PRESET1,Upstream Port 8.0 GT/s Transmitter Preset 1. The write value is gated with the PCIE_CAP_CROSS_LINK_SUPPORT field of LINK_CAPABILITIES2_REG. For a description of this standard PCIe register field see the PCI Express Specification. Note:.." rbitfld.long 0xC 23. "RSVDP_23,Reserved for future use." "0,1" newline bitfld.long 0xC 20.--22. "DSP_RX_PRESET_HINT1,Downstream Port 8.0 GT/s Receiver Preset Hint 1. For a description of this standard PCIe register field see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if.." "0,1,2,3,4,5,6,7" hexmask.long.byte 0xC 16.--19. 1. "DSP_TX_PRESET1,Downstream Port 8.0 GT/s Transmitter Preset 1. For a description of this standard PCIe register field see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN.." rbitfld.long 0xC 15. "RSVDP_15,Reserved for future use." "0,1" bitfld.long 0xC 12.--14. "USP_RX_PRESET_HINT0,Upstream Port 8.0 GT/s Receiver Preset Hint 0. The write value is gated with the PCIE_CAP_CROSS_LINK_SUPPORT field of LINK_CAPABILITIES2_REG. For a description of this standard PCIe register field see the PCI Express Specification." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0xC 8.--11. 1. "USP_TX_PRESET0,Upstream Port 8.0 GT/s Transmitter Preset 0. The write value is gated with the PCIE_CAP_CROSS_LINK_SUPPORT field of LINK_CAPABILITIES2_REG. For a description of this standard PCIe register field see the PCI Express Specification. Note:.." rbitfld.long 0xC 7. "RSVDP_7,Reserved for future use." "0,1" bitfld.long 0xC 4.--6. "DSP_RX_PRESET_HINT0,Downstream Port 8.0 GT/s Receiver Preset Hint 0. For a description of this standard PCIe register field see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if.." "0,1,2,3,4,5,6,7" hexmask.long.byte 0xC 0.--3. 1. "DSP_TX_PRESET0,Downstream Port 8.0 GT/s Transmitter Preset 0. For a description of this standard PCIe register field see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN.." tree.end tree "PF0_L1SUB_CAP (L1 Substates Capability Structure)" group.long (0x0+0x2E8)++0xF line.long 0x0 "L1SUB_CAP_HEADER_REG,L1 Substates Extended Capability Header. This register provides capbility ID. capability version and next offset value for L1 Substates." hexmask.long.word 0x0 20.--31. 1. "NEXT_OFFSET,Next Capability Offset. This field contains the offset to the next PCI Express Capability structure or 000h if no other items exist in the linked list of Capabilities. For Extended Capabilities implemented in Configuration Space this offset.." hexmask.long.byte 0x0 16.--19. 1. "CAP_VERSION,Capability Version. This field is a PCI-SIG defined version number that indicates the version of the Capability structure present. This field is depends on version of the specification. Note: The access attributes of this field are as.." hexmask.long.word 0x0 0.--15. 1. "EXTENDED_CAP_ID,L1SUB Extended Capability ID. This field is a PCI-SIG defined ID number that indicates the nature and format of the Extended Capability. Extended Capability ID for L1 PM Substates is 001Eh. Note: The access attributes of this field are as.." line.long 0x4 "L1SUB_CAPABILITY_REG,L1 Substates Capability Register. This register provides extended capability of L1 Substates." hexmask.long.byte 0x4 24.--31. 1. "RSVDP_24,Reserved for future use." hexmask.long.byte 0x4 19.--23. 1. "PWR_ON_VALUE_SUPPORT,Port T Power On Value. Along with the Port T_POWER_ON Scale field in the L1 PM Substates Capabilities register sets the time (in us) that this Port requires the port on the opposite side of Link to wait in L1.2.Exit after sampling.." rbitfld.long 0x4 18. "RSVDP_18,Reserved for future use." "0,1" bitfld.long 0x4 16.--17. "PWR_ON_SCALE_SUPPORT,Port T Power On Scale. Specifies the scale used for the Port T_POWER_ON Value field in the L1 PM Substates Capabilities register. Range of values are given below. Required for all Ports for which either the PCI-PM L1.2 Supported bit.." "?,?,?,Reserved" newline hexmask.long.byte 0x4 8.--15. 1. "COMM_MODE_SUPPORT,Port Common Mode Restore Time. Time (in us) required for this Port to re-establish common mode. Required for all Ports for which either the PCI-PM L1.2 Supported bit is Set ASPM L1.2 Supported bit is Set or both are Set otherwise.." rbitfld.long 0x4 5.--7. "RSVDP_5,Reserved for future use." "0,1,2,3,4,5,6,7" bitfld.long 0x4 4. "L1_PMSUB_SUPPORT,L1 PM Substates ECN Supported. When Set this bit indicates that this Port supports L1 PM Substates. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W (sticky)" "0,1" bitfld.long 0x4 3. "L1_1_ASPM_SUPPORT,ASPM L11 Supported. When Set this bit indicates that ASPM L1.1 is supported. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W (sticky)" "0,1" newline bitfld.long 0x4 2. "L1_2_ASPM_SUPPORT,ASPM L12 Supported. When Set this bit indicates that ASPM L1.2 is supported. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W (sticky)" "0,1" bitfld.long 0x4 1. "L1_1_PCIPM_SUPPORT,PCI-PM L11 Supported. When Set this bit indicates that PCI-PM L1.1 is supported and must be Set by all Ports implementing L1 PM Substates. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W (sticky)" "0,1" bitfld.long 0x4 0. "L1_2_PCIPM_SUPPORT,PCI-PM L12 Supported. When Set this bit indicates that PCI-PM L1.2 is supported. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W (sticky)" "0,1" line.long 0x8 "L1SUB_CONTROL1_REG,L1 Substates Control 1 Register. This register provides Controls to extended capability." bitfld.long 0x8 29.--31. "L1_2_TH_SCA,LTR L12 Threshold Scale. This field provides a scale for the value contained within the LTR_L1.2_THRESHOLD_Value.The default value for this field is 000b.Hardware operation is undefined if software writes a Not-Permitted value to this field." "0,1,2,3,4,5,6,7" rbitfld.long 0x8 26.--28. "RSVDP_26,Reserved for future use." "0,1,2,3,4,5,6,7" hexmask.long.word 0x8 16.--25. 1. "L1_2_TH_VAL,LTR L12 Threshold Value. Along with the LTR_L1.2_THRESHOLD_Scale this field indicates the LTR threshold used to determine if entry into L1 results in L1.1 (if enabled) or L1.2 (if enabled). The default value for this field is 00 0000 0000b." hexmask.long.byte 0x8 8.--15. 1. "T_COMMON_MODE,Common Mode Restore Time. Sets value of TCOMMONMODE (in us) which must be used by the Downstream Ports for timing the re-establishment of common mode.This field is of type RsvdP for Upstream Ports. Default value is implementation.." newline hexmask.long.byte 0x8 4.--7. 1. "RSVDP_4,Reserved for future use." bitfld.long 0x8 3. "L1_1_ASPM_EN,ASPM L11 Enable. When Set this bit enables ASPM L1.1.For Ports for which the ASPM L1.1 Supported bit is Clear this bit is permitted to be hardwired to 0.Default value is 0b." "0,1" bitfld.long 0x8 2. "L1_2_ASPM_EN,ASPM L12 Enable. When Set this bit enables ASPM L1.2.For Ports for which the ASPM L1.2 Supported bit is Clear this bit is permitted to be hardwired to 0.Default value is 0b." "0,1" bitfld.long 0x8 1. "L1_1_PCIPM_EN,PCI-PM L11 Enable. When Set this bit enables PCI-PM L1.1. Default value is 0b." "0,1" newline bitfld.long 0x8 0. "L1_2_PCIPM_EN,PCI-PM L12 Enable. When Set this bit enables PCI-PM L1.2.For Ports for which the PCI-PM L1.2 Supported bit is Clear this bit is permitted to be hardwired to 0.Default value is 0b." "0,1" line.long 0xC "L1SUB_CONTROL2_REG,L1 Substates Control 2 Register. This register provides Controls to extended capability." hexmask.long.tbyte 0xC 8.--31. 1. "RSVDP_8,Reserved for future use." hexmask.long.byte 0xC 3.--7. 1. "T_POWER_ON_VALUE,T Power On Value. Along with the T_POWER_ON Scale sets the minimum amount of time (in us) that the Port must wait in L1.2.Exit after sampling CLKREQ# asserted before actively driving the interface.Default value is 00101b. T_POWER_ON is.." rbitfld.long 0xC 2. "RSVDP_2,Reserved for future use." "0,1" bitfld.long 0xC 0.--1. "T_POWER_ON_SCALE,T Power On Scale. Specifies the scale used for T_POWER_ON Value. Range of values are given below. Required for all Ports that support L1.2 otherwise this field is of type RsvdP. This field must only be modified when the ASPM L1.2 Enable.." "?,?,?,Reserved" tree.end tree "PF0_RAS_DES_CAP (RAS D.E.S. Capability Structure (VSEC))" group.long (0x0+0x30C)++0x3 line.long 0x0 "RAS_DES_CAP_HEADER_REG,Vendor-Specific Extended Capability Header. For a description of this standard PCIe register. see the PCI Express Specification." hexmask.long.word 0x0 20.--31. 1. "NEXT_OFFSET,Next Capability Offset. For a description of this standard PCIe register field see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky).." newline hexmask.long.byte 0x0 16.--19. 1. "CAP_VERSION,Capability Version. For a description of this standard PCIe register field see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else.." newline hexmask.long.word 0x0 0.--15. 1. "EXTENDED_CAP_ID,PCI Express Extended Capability ID. For a description of this standard PCIe register field see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then.." rgroup.long (0x4+0x30C)++0x3 line.long 0x0 "VENDOR_SPECIFIC_HEADER_REG,Vendor-Specific Header. For a description of this standard PCIe register. see the PCI Express Specification." hexmask.long.word 0x0 20.--31. 1. "VSEC_LENGTH,VSEC Length. For a description of this standard PCIe register field see the PCI Express Specification." newline hexmask.long.byte 0x0 16.--19. 1. "VSEC_REV,VSEC Rev. For a description of this standard PCIe register field see the PCI Express Specification." newline hexmask.long.word 0x0 0.--15. 1. "VSEC_ID,VSEC ID. For a description of this standard PCIe register field see the PCI Express Specification." group.long (0x8+0x30C)++0x3 line.long 0x0 "EVENT_COUNTER_CONTROL_REG,Event Counter Control. This is a viewport control register. - Setting the EVENT_COUNTER_EVENT_SELECT and EVENT_COUNTER_LANE_SELECT fields in this register determine the Event Counter data returned by the EVENT_COUNTER_DATA_REG.." hexmask.long.byte 0x0 28.--31. 1. "RSVDP_28,Reserved for future use." newline hexmask.long.word 0x0 16.--27. 1. "EVENT_COUNTER_EVENT_SELECT,Event Counter Data Select. This field in conjunction with the EVENT_COUNTER_LANE_SELECT field indexes the Event Counter data returned by the EVENT_COUNTER_DATA_REG register. - 27-24: Group number(4-bit: 0..0x7) - 23-16: Event.." newline hexmask.long.byte 0x0 12.--15. 1. "RSVDP_12,Reserved for future use." newline hexmask.long.byte 0x0 8.--11. 1. "EVENT_COUNTER_LANE_SELECT,Event Counter Lane Select. This field in conjunction with EVENT_COUNTER_EVENT_SELECT indexes the Event Counter data returned by the EVENT_COUNTER_DATA_REG register. - 0x0: Lane0 - 0x1: Lane1 - 0x2: Lane2 - .. - 0xF: Lane15 Note:.." newline rbitfld.long 0x0 7. "EVENT_COUNTER_STATUS,Event Counter Status. This register returns the current value of the Event Counter selected by the following fields: - EVENT_COUNTER_EVENT_SELECT - EVENT_COUNTER_LANE_SELECT Note: This register field is sticky." "0,1" newline rbitfld.long 0x0 5.--6. "RSVDP_5,Reserved for future use." "0,1,2,3" newline bitfld.long 0x0 2.--4. "EVENT_COUNTER_ENABLE,Event Counter Enable. Enables/disables the Event Counter selected by the EVENT_COUNTER_EVENT_SELECT and EVENT_COUNTER_LANE_SELECT fields in this register. By default all event counters are disabled. You can enable/disable a specific.." "no change,per event off,?,?,?,?,?,?" newline bitfld.long 0x0 0.--1. "EVENT_COUNTER_CLEAR,Event Counter Clear. Clears the Event Counter selected by the EVENT_COUNTER_EVENT_SELECT and EVENT_COUNTER_LANE_SELECT fields in this register. You can clear the value of a specific Event Counter by writing the 'per clear' code and.." "no change,per clear,?,?" rgroup.long (0xC+0x30C)++0x3 line.long 0x0 "EVENT_COUNTER_DATA_REG,Event Counter Data. This viewport register returns the data selected by the following fields: - EVENT_COUNTER_EVENT_SELECT in EVENT_COUNTER_CONTROL_REG - EVENT_COUNTER_LANE_SELECT in EVENT_COUNTER_CONTROL_REG For more details. see.." hexmask.long 0x0 0.--31. 1. "EVENT_COUNTER_DATA,Event Counter Data. This register returns the data selected by the following fields: - EVENT_COUNTER_EVENT_SELECT in EVENT_COUNTER_CONTROL_REG - EVENT_COUNTER_LANE_SELECT in EVENT_COUNTER_CONTROL_REG Note: This register field is sticky." group.long (0x10+0x30C)++0x3 line.long 0x0 "TIME_BASED_ANALYSIS_CONTROL_REG,Time-based Analysis Control. Used for controlling the measurement of RX/TX data throughput and time spent in each low-power LTSSM state. For more details. see the RAS DES section in the Core Operations chapter of the.." hexmask.long.byte 0x0 24.--31. 1. "TIME_BASED_REPORT_SELECT,Time-based Report Select. Selects what type of data is measured for the selected duration (TIME_BASED_DURATION_SELECT) and returned in TIME_BASED_ANALYSIS_DATA. Each type of data is measured using one of three types of units: -.." newline hexmask.long.byte 0x0 16.--23. 1. "RSVDP_16,Reserved for future use." newline hexmask.long.byte 0x0 8.--15. 1. "TIME_BASED_DURATION_SELECT,Time-based Duration Select. Selects the duration of time-based analysis. When 'manual control' is selected and TIMER_START is set to '1' this analysis never stops until TIMER_STOP is set to '0'. - 0x0: Manual control - 0x1:.." newline hexmask.long.byte 0x0 1.--7. 1. "RSVDP_1,Reserved for future use." newline bitfld.long 0x0 0. "TIMER_START,Timer Start. - 1: Start/Restart - 0: Stop This bit will be cleared automatically when the measurement is finished. Note: The app_ras_des_tba_ctrl input also sets the contents of this field and controls the measurement start/stop. Note: This.." "Stop,Start/Restart" rgroup.long (0x14+0x30C)++0x7 line.long 0x0 "TIME_BASED_ANALYSIS_DATA_REG,Time-based Analysis Data. Contains the measurement results of RX/TX data throughput and time spent in each low-power LTSSM state. This viewport register returns the data selected by the TIME_BASED_REPORT_SELECT field in.." hexmask.long 0x0 0.--31. 1. "TIME_BASED_ANALYSIS_DATA,Time Based Analysis Data. This register returns the data selected by the TIME_BASED_REPORT_SELECT field in TIME_BASED_ANALYSIS_CONTROL_REG. The results are cleared when next measurement starts. Note: This register field is sticky." line.long 0x4 "TIME_BASED_ANALYSIS_DATA_63_32_REG,Upper 32 bits of Time-based Analysis Data. This viewport register returns the data selected by the TIME_BASED_REPORT_SELECT field in TIME_BASED_ANALYSIS_CONTROL_REG. For more details. see the RAS DES section in the Core.." hexmask.long 0x4 0.--31. 1. "TIME_BASED_ANALYSIS_DATA_63_32,Upper 32 bits of Time Based Analysis Data. Note: This register field is sticky." group.long (0x30+0x30C)++0x5F line.long 0x0 "EINJ_ENABLE_REG,Error Injection Enable. Each type of error insertion is enabled by the corresponding bit in this register. The specific injection controls for each type of error are defined in the following registers: - 0: CRC Error: EINJ0_CRC_REG - 1:.." hexmask.long 0x0 7.--31. 1. "RSVDP_7,Reserved for future use." newline bitfld.long 0x0 6. "ERROR_INJECTION6_ENABLE,Error Injection6 Enable (Specific TLP Error). Enables insertion of errors into the packets that you select. You can set this bit to '1' when you have disabled RAS datapath protection (DP) by setting CX_RASDP = CX_RASDP_RAM_PROT.." "0,1" newline bitfld.long 0x0 5. "ERROR_INJECTION5_ENABLE,Error Injection5 Enable (TLP Duplicate/Nullify Error). Enables insertion of duplicate/nullified TLPs. For more details see the EINJ5_SP_TLP_REG register. Note: This register field is sticky." "0,1" newline bitfld.long 0x0 4. "ERROR_INJECTION4_ENABLE,Error Injection4 Enable (FC Credit Update Error). Enables insertion of errors into UpdateFCs. For more details see the EINJ4_FC_REG register. Note: This register field is sticky." "0,1" newline bitfld.long 0x0 3. "ERROR_INJECTION3_ENABLE,Error Injection3 Enable (Symbol DataK Mask Error or Sync Header Error). Enables DataK masking of special symbols or the breaking of the sync header. For more details see the EINJ3_SYMBOL_REG register. Note: This register field is.." "0,1" newline bitfld.long 0x0 2. "ERROR_INJECTION2_ENABLE,Error Injection2 Enable (DLLP Error). Enables insertion of DLLP errors. For more details see the EINJ2_DLLP_REG register. Note: This register field is sticky." "0,1" newline bitfld.long 0x0 1. "ERROR_INJECTION1_ENABLE,Error Injection1 Enable (Sequence Number Error). Enables insertion of errors into sequence numbers. For more details see the EINJ1_SEQNUM_REG register. Note: This register field is sticky." "0,1" newline bitfld.long 0x0 0. "ERROR_INJECTION0_ENABLE,Error Injection0 Enable (CRC Error). Enables insertion of errors into various CRC. For more details see the EINJ0_CRC_REG register. Note: This register field is sticky." "0,1" line.long 0x4 "EINJ0_CRC_REG,Error Injection Control 0 (CRC Error). Controls the insertion of errors into the CRC. and parity of ordered sets for the selected type of the packets as follows: - LCRC. Bad TLP will be detected at the receiver side; receiver responds with.." hexmask.long.tbyte 0x4 12.--31. 1. "RSVDP_12,Reserved for future use." newline hexmask.long.byte 0x4 8.--11. 1. "EINJ0_CRC_TYPE,Error injection type. Selects the type of CRC error to be inserted. Tx Path - 0000b: New TLP's LCRC error injection - 0001b: 16bCRC error injection of ACK/NAK DLLP - 0010b: 16bCRC error injection of Update-FC DLLP - 0011b: New TLP's ECRC.." newline hexmask.long.byte 0x4 0.--7. 1. "EINJ0_COUNT,Error injection count. Indicates the number of errors. This register is decremented when the errors have been inserted. - If the counter value is 0x01 and error is inserted ERROR_INJECTION0_ENABLE in EINJ_ENABLE_REG returns 0b. - If the.." line.long 0x8 "EINJ1_SEQNUM_REG,Error Injection Control 1 (Sequence Number Error). Controls the sequence number of the specific TLPs and ACK/NAK DLLPs. Data Link Protocol Error will be detected at the Rx side of ACK/NAL DLLPs when one of these conditions is true: -.." rbitfld.long 0x8 29.--31. "RSVDP_29,Reserved for future use." "0,1,2,3,4,5,6,7" newline hexmask.long.word 0x8 16.--28. 1. "EINJ1_BAD_SEQNUM,Bad sequence number. Indicates the value to add/subtract from the naturally-assigned sequence numbers. This value is represented by two's complement. - 0x0FFF: +4095 - .. - 0x0002: +2 - 0x0001: +1 - 0x0000: 0 - 0x1FFF: -1 - 0x1FFE: -2 -.." newline hexmask.long.byte 0x8 9.--15. 1. "RSVDP_9,Reserved for future use." newline bitfld.long 0x8 8. "EINJ1_SEQNUM_TYPE,Sequence number type. Selects the type of sequence number. - 0b: Insertion of New TLP's SEQ# error - 1b: Insertion of ACK/NAK DLLP's SEQ# Error Note: This register field is sticky." "0,1" newline hexmask.long.byte 0x8 0.--7. 1. "EINJ1_COUNT,Error injection count. Indicates the number of errors. This register is decremented as the errors are being inserted. - If the counter value is 0x01 and error is inserted ERROR_INJECTION1_ENABLE in EINJ_ENABLE_REG returns '0'. - If the.." line.long 0xC "EINJ2_DLLP_REG,Error Injection Control 2 (DLLP Error). Controls the transmission of DLLPs and inserts the following errors: - If 'ACK/NAK DLLP's transmission block' is selected. replay timeout error will occur at the transmitter of the TLPs and then Data.." hexmask.long.tbyte 0xC 10.--31. 1. "RSVDP_10,Reserved for future use." newline bitfld.long 0xC 8.--9. "EINJ2_DLLP_TYPE,DLLP Type. Selects the type of DLLP errors to be inserted. - 00b: ACK/NAK DLLP's transmission block - 01b: Update FC DLLP's transmission block - 10b: Always Transmission for NAK DLLP - 11b: Reserved Note: This register field is sticky." "0,1,2,3" newline hexmask.long.byte 0xC 0.--7. 1. "EINJ2_COUNT,Error injection count. Indicates the number of errors. This register is decremented as the errors are being inserted. - If the counter value is 0x01 and the error is inserted ERROR_INJECTION2_ENABLE in EINJ_ENABLE_REG returns '0'. - If the.." line.long 0x10 "EINJ3_SYMBOL_REG,Error Injection Control 3 (Symbol Error). When 8b/10b encoding is used. this register controls error insertion into the special (K code) symbols. - If TS1/TS2/FTS/E-Idle/SKP is selected. it affects whole of the ordered set. It might.." hexmask.long.tbyte 0x10 11.--31. 1. "RSVDP_11,Reserved for future use." newline bitfld.long 0x10 8.--10. "EINJ3_SYMBOL_TYPE,Error Type. 8b/10b encoding - Mask K symbol. It is not supported to insert errors into the first ordered-set after exiting from TxElecIdle when CX_FREQ_STEP_EN has been enabled. - 000b: Reserved - 001b: COM/PAD(TS1 Order set) - 010b:.." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x10 0.--7. 1. "EINJ3_COUNT,Error injection count. Indicates the number of errors. This register is decremented as the errors are being inserted. - If the counter value is 0x01 and error is inserted ERROR_INJECTION3_ENABLE in EINJ_ENABLE_REG returns '0'. - If the.." line.long 0x14 "EINJ4_FC_REG,Error Injection Control 4 (FC Credit Error). Controls error insertion into the credit value in the UpdateFCs. It is possible to insert errors for any of the following types: - Posted TLP Header credit - Non-Posted TLP Header credit -.." rbitfld.long 0x14 29.--31. "RSVDP_29,Reserved for future use." "0,1,2,3,4,5,6,7" newline hexmask.long.word 0x14 16.--28. 1. "EINJ4_BAD_UPDFC_VALUE,Bad update-FC credit value. Indicates the value to add/subtract from the UpdateFC credit. This value is represented by two's complement. - 0x0FFF: +4095 - .. - 0x0002: +2 - 0x0001: +1 - 0x0000: 0 - 0x1FFF: -1 - 0x1FFE: -2 - .. -.." newline rbitfld.long 0x14 15. "RSVDP_15,Reserved for future use." "0,1" newline bitfld.long 0x14 12.--14. "EINJ4_VC_NUMBER,VC Number. Indicates target VC Number. Note: This register field is sticky." "0,1,2,3,4,5,6,7" newline rbitfld.long 0x14 11. "RSVDP_11,Reserved for future use." "0,1" newline bitfld.long 0x14 8.--10. "EINJ4_UPDFC_TYPE,Update-FC type. Selects the credit type. - 000b: Posted TLP Header Credit value control - 001b: Non-Posted TLP Header Credit value control - 010b: Completion TLP Header Credit value control - 011b: Reserved - 100b: Posted TLP Data Credit.." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x14 0.--7. 1. "EINJ4_COUNT,Error injection count. Indicates the number of errors. This register is decremented as the errors are being inserted. - If the counter value is 0x01 and error is inserted ERROR_INJECTION4_ENABLE in EINJ_ENABLE_REG returns '0'. - If the.." line.long 0x18 "EINJ5_SP_TLP_REG,Error Injection Control 5 (Specific TLP Error). Controls the generation of specified TLPs. Correctable errors will occur which will be fixed by the PCIe protocol. - For Duplicate TLP. the controller initiates Data Link Retry by handling.." hexmask.long.tbyte 0x18 9.--31. 1. "RSVDP_9,Reserved for future use." newline bitfld.long 0x18 8. "EINJ5_SPECIFIED_TLP,Specified TLP. Selects the specified TLP to be inserted. - 0: Generates duplicate TLPs by handling ACK DLLP as NAK DLLP. - 1: Generates Nullified TLP (Original TLP will be stored in retry buffer). Note: This register field is sticky." "Generates duplicate TLPs by handling ACK DLLP as..,Generates Nullified TLP" newline hexmask.long.byte 0x18 0.--7. 1. "EINJ5_COUNT,Error injection count. Indicates the number of errors. This register is decremented as the errors are being inserted. - If the counter value is 0x01 and error is inserted ERROR_INJECTION5_ENABLE in EINJ_ENABLE_REG returns '0'. - If the.." line.long 0x1C "EINJ6_COMPARE_POINT_H0_REG,Error Injection Control 6 (Compare Point Header DWORD #0). Program this register for the 1st DWORD of TLP header/prefix. It is necessary to carefully consider the endianness when you program this register. Bits [31:0] =.." hexmask.long 0x1C 0.--31. 1. "EINJ6_COMPARE_POINT_H0,Packet Compare Point: 1st DWORD. Specifies which Tx TLP header DWORD#0 bits to compare with the corresponding bits in the Packet Compare Value registers (EINJ6_COMPARE_VALUE*). When all specified bits (in the Tx TLP header and.." line.long 0x20 "EINJ6_COMPARE_POINT_H1_REG,Error Injection Control 6 (Compare Point Header DWORD #1). Program this register for the 2nd DWORD of TLP header/prefix. It is necessary to carefully consider the endianness when you program this register. Bits [31:0] =.." hexmask.long 0x20 0.--31. 1. "EINJ6_COMPARE_POINT_H1,Packet Compare Point: 2nd DWORD. Specifies which Tx TLP header DWORD#1 bits to compare with the corresponding bits in the Packet Compare Value registers (EINJ6_COMPARE_VALUE*). When all specified bits (in the Tx TLP header and.." line.long 0x24 "EINJ6_COMPARE_POINT_H2_REG,Error Injection Control 6 (Compare Point Header DWORD #2). Program this register for the 3rd DWORD of TLP header/prefix. It is necessary to carefully consider the endianness when you program this register. Bits [31:0] =.." hexmask.long 0x24 0.--31. 1. "EINJ6_COMPARE_POINT_H2,Packet Compare Point: 3rd DWORD. Specifies which Tx TLP header DWORD#2 bits to compare with the corresponding bits in the Packet Compare Value registers (EINJ6_COMPARE_VALUE*). When all specified bits (in the Tx TLP header and.." line.long 0x28 "EINJ6_COMPARE_POINT_H3_REG,Error Injection Control 6 (Compare Point Header DWORD #3). Program this register for the 4th DWORD of TLP header/prefix. It is necessary to carefully consider the endianness when you program this register. Bits [31:0] =.." hexmask.long 0x28 0.--31. 1. "EINJ6_COMPARE_POINT_H3,Packet Compare Point: 4th DWORD. Specifies which Tx TLP header DWORD#3 bits to compare with the corresponding bits in the Packet Compare Value registers (EINJ6_COMPARE_VALUE*). When all specified bits (in the Tx TLP header and.." line.long 0x2C "EINJ6_COMPARE_VALUE_H0_REG,Error Injection Control 6 (Compare Value Header DWORD #0). Program this register for the 1st DWORD of TLP header/prefix. It is necessary to carefully consider the endianness when you program this register. Bits [31:0] =.." hexmask.long 0x2C 0.--31. 1. "EINJ6_COMPARE_VALUE_H0,Packet Compare Value: 1st DWORD. Specifies the value to compare against Tx the TLP header DWORD#0 bits specified in the Packet Compare Point registers (EINJ6_COMPARE_POINT*). Note: This register field is sticky." line.long 0x30 "EINJ6_COMPARE_VALUE_H1_REG,Error Injection Control 6 (Compare Value Header DWORD #1). Program this register for the 2nd DWORD of TLP header/prefix. It is necessary to carefully consider the endianness when you program this register. Bits [31:0] =.." hexmask.long 0x30 0.--31. 1. "EINJ6_COMPARE_VALUE_H1,Packet Compare Value: 2nd DWORD. Specifies the value to compare against Tx the TLP header DWORD#1 bits specified in the Packet Compare Point registers (EINJ6_COMPARE_POINT*). Note: This register field is sticky." line.long 0x34 "EINJ6_COMPARE_VALUE_H2_REG,Error Injection Control 6 (Compare Value Header DWORD #2). Program this register for the 3rd DWORD of TLP header/prefix. It is necessary to carefully consider the endianness when you program this register. Bits [31:0] =.." hexmask.long 0x34 0.--31. 1. "EINJ6_COMPARE_VALUE_H2,Packet Compare Value: 3rd DWORD. Specifies the value to compare against Tx the TLP header DWORD#2 bits specified in the Packet Compare Point registers (EINJ6_COMPARE_POINT*). Note: This register field is sticky." line.long 0x38 "EINJ6_COMPARE_VALUE_H3_REG,Error Injection Control 6 (Compare Value Header DWORD #3). Program this register for the 4th DWORD of TLP header/prefix. It is necessary to carefully consider the endianness when you program this register. Bits [31:0] =.." hexmask.long 0x38 0.--31. 1. "EINJ6_COMPARE_VALUE_H3,Packet Compare Value: 4th DWORD. Specifies the value to compare against Tx the TLP header DWORD#3 bits specified in the Packet Compare Point registers (EINJ6_COMPARE_POINT*). Note: This register field is sticky." line.long 0x3C "EINJ6_CHANGE_POINT_H0_REG,Error Injection Control 6 (Change Point Header DWORD #0). Program this register for the 1st DWORD of TLP header/prefix. It is necessary to carefully consider the endianness when you program this register. Bits [31:0] =.." hexmask.long 0x3C 0.--31. 1. "EINJ6_CHANGE_POINT_H0,Packet Change Point: 1st DWORD. Specifies which Tx TLP header DWORD#0 bits to replace with the corresponding bits in the Packet Change Value registers (EINJ6_CHANGE_VALUE*). Note: This register field is sticky." line.long 0x40 "EINJ6_CHANGE_POINT_H1_REG,Error Injection Control 6 (Change Point Header DWORD #1). Program this register for the 2nd DWORD of TLP header/prefix. It is necessary to carefully consider the endianness when you program this register. Bits [31:0] =.." hexmask.long 0x40 0.--31. 1. "EINJ6_CHANGE_POINT_H1,Packet Change Point: 2nd DWORD. Specifies which Tx TLP header DWORD#1 bits to replace with the corresponding bits in the Packet Change Value registers (EINJ6_CHANGE_VALUE*). Note: This register field is sticky." line.long 0x44 "EINJ6_CHANGE_POINT_H2_REG,Error Injection Control 6 (Change Point Header DWORD #2). Program this register for the 3rd DWORD of TLP header/prefix. It is necessary to carefully consider the endianness when you program this register. Bits [31:0] =.." hexmask.long 0x44 0.--31. 1. "EINJ6_CHANGE_POINT_H2,Packet Change Point: 3rd DWORD. Specifies which Tx TLP header DWORD#2 bits to replace with the corresponding bits in the Packet Change Value registers (EINJ6_CHANGE_VALUE*). Note: This register field is sticky." line.long 0x48 "EINJ6_CHANGE_POINT_H3_REG,Error Injection Control 6 (Change Point Header DWORD #3). Program this register for the 4th DWORD of TLP header/prefix. It is necessary to carefully consider the endianness when you program this register. Bits [31:0] =.." hexmask.long 0x48 0.--31. 1. "EINJ6_CHANGE_POINT_H3,Packet Change Point: 4th DWORD. Specifies which Tx TLP header DWORD#3 bits to replace with the corresponding bits in the Packet Change Value registers (EINJ6_CHANGE_VALUE*). Note: This register field is sticky." line.long 0x4C "EINJ6_CHANGE_VALUE_H0_REG,Error Injection Control 6 (Change Value Header DWORD #0). Program this register for the 1st DWORD of TLP header/prefix. It is necessary to carefully consider the endianness when you program this register. Bits [31:0] =.." hexmask.long 0x4C 0.--31. 1. "EINJ6_CHANGE_VALUE_H0,Packet Change Value: 1st DWORD. Specifies replacement values for the Tx TLP header DWORD#0 bits defined in the Packet Change Point registers (EINJ6_CHANGE_POINT*). Only applies when the EINJ6_INVERTED_CONTROL field in EINJ6_TLP_REG.." line.long 0x50 "EINJ6_CHANGE_VALUE_H1_REG,Error Injection Control 6 (Change Value Header DWORD #1). Program this register for the 2nd DWORD of TLP header/prefix. It is necessary to carefully consider the endianness when you program this register. Bits [31:0] =.." hexmask.long 0x50 0.--31. 1. "EINJ6_CHANGE_VALUE_H1,Packet Change Value: 2nd DWORD. Specifies replacement values for the Tx TLP header DWORD#1 bits defined in the Packet Change Point registers (EINJ6_CHANGE_POINT*). Only applies when the EINJ6_INVERTED_CONTROL field in EINJ6_TLP_REG.." line.long 0x54 "EINJ6_CHANGE_VALUE_H2_REG,Error Injection Control 6 (Change Value Header DWORD #2). Program this register for the 3rd DWORD of TLP header/prefix. It is necessary to carefully consider the endianness when you program this register. Bits [31:0] =.." hexmask.long 0x54 0.--31. 1. "EINJ6_CHANGE_VALUE_H2,Packet Change Value: 3rd DWORD. Specifies replacement values for the Tx TLP header DWORD#2 bits defined in the Packet Change Point registers (EINJ6_CHANGE_POINT*). Only applies when the EINJ6_INVERTED_CONTROL field in EINJ6_TLP_REG.." line.long 0x58 "EINJ6_CHANGE_VALUE_H3_REG,Error Injection Control 6 (Change Value Header DWORD #3). Program this register for the 4th DWORD of TLP header/prefix. It is necessary to carefully consider the endianness when you program this register. Bits [31:0] =.." hexmask.long 0x58 0.--31. 1. "EINJ6_CHANGE_VALUE_H3,Packet Change Value: 4th DWORD. Specifies replacement values for the Tx TLP header DWORD#3 bits defined in the Packet Change Point registers (EINJ6_CHANGE_POINT*). Only applies when the EINJ6_INVERTED_CONTROL field in EINJ6_TLP_REG.." line.long 0x5C "EINJ6_TLP_REG,Error Injection Control 6 (Packet Error). The Packet Compare Point registers (EINJ6_COMPARE_POINT*) specify which Tx TLP header bits to compare with the corresponding bits in the Packet Compare Value registers (EINJ6_COMPARE_VALUE*). When.." hexmask.long.tbyte 0x5C 12.--31. 1. "RSVDP_12,Reserved for future use." newline bitfld.long 0x5C 9.--11. "EINJ6_PACKET_TYPE,Packet type. Selects the TLP packets to inject errors into. - 0: TLP Header - 1: TLP Prefix 1st 4-DWORDs - 2: TLP Prefix 2nd -DWORDs - Else: Reserved Note: This register field is sticky." "TLP Header,TLP Prefix 1st 4-DWORDs,TLP Prefix 2nd -DWORDs,?,?,?,?,?" newline bitfld.long 0x5C 8. "EINJ6_INVERTED_CONTROL,Inverted Error Injection Control. - 0: EINJ6_CHANGE_VALUE_H[0/1/2/3] is used to replace bits specified by EINJ6_CHANGE_POINT_H[0/1/2/3]. - 1: EINJ6_CHANGE_VALUE_H[0/1/2/3] is ignored and inverts bits specified by.." "EINJ6_CHANGE_VALUE_H[0/1/2/3] is used to replace..,EINJ6_CHANGE_VALUE_H[0/1/2/3] is ignored and.." newline hexmask.long.byte 0x5C 0.--7. 1. "EINJ6_COUNT,Error Injection Count. Indicates the number of errors to insert. This counter is decremented while errors are been inserted. - If the counter value is 0x01 and error is inserted ERROR_INJECTION6_ENABLE in EINJ_ENABLE_REG returns '0'. - If.." group.long (0xA0+0x30C)++0x7 line.long 0x0 "SD_CONTROL1_REG,Silicon Debug Control 1. For more details. see the RAS DES section in the Core Operations chapter of the Databook." hexmask.long.byte 0x0 24.--31. 1. "RSVDP_24,Reserved for future use." newline bitfld.long 0x0 22.--23. "LOW_POWER_INTERVAL,Low Power Entry Interval Time. Interval Time that the controller starts monitoring RXELECIDLE signal after L0s/L1/L2 entry. You should set the value according to the latency from receiving EIOS to RXELECIDLE assertion at the PHY. -.." "0,1,2,3" newline bitfld.long 0x0 20.--21. "TX_EIOS_NUM,Number of Tx EIOS. This register sets the number of transmit EIOS for L0s/L1 entry and Disable/Loopback/Hot-reset exit. The controller selects the greater value between this register and the value defined by the PCI-SIG specification. 2.5GT/s.." "0,1,2,3" newline rbitfld.long 0x0 17.--19. "RSVDP_17,Reserved for future use." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 16. "FORCE_DETECT_LANE_EN,Force Detect Lane Enable. When this bit is set the controller ignores receiver detection from PHY during LTSSM Detect state and uses FORCE_DETECT_LANE. Note: This register field is sticky." "0,1" newline hexmask.long.word 0x0 0.--15. 1. "FORCE_DETECT_LANE,Force Detect Lane. When the FORCE_DETECT_LANE_EN field is set the controller ignores receiver detection from PHY during LTSSM Detect state and uses this value instead. - 0: Lane0 - 1: Lane1 - 2: Lane2 - .. - 15: Lane15 Note: This.." line.long 0x4 "SD_CONTROL2_REG,Silicon Debug Control 2. For more details. see the RAS DES section in the Core Operations chapter of the Databook." hexmask.long.word 0x4 17.--31. 1. "RSVDP_17,Reserved for future use." newline bitfld.long 0x4 16. "FRAMING_ERR_RECOVERY_DISABLE,Framing Error Recovery Disable. This bit disables a transition to Recovery state when a Framing Error is occurred. Note: This register field is sticky." "0,1" newline hexmask.long.byte 0x4 11.--15. 1. "RSVDP_11,Reserved for future use." newline bitfld.long 0x4 10. "DIRECT_LPBKSLV_TO_EXIT,Direct Loopback Slave To Exit. When this bit is set and the LTSSM is in Loopback Slave Active State the LTSSM transitions to Loopback Slave Exit state. Note: This register field is sticky." "0,1" newline bitfld.long 0x4 9. "DIRECT_POLCOMP_TO_DETECT,Direct Polling.Compliance to Detect. When this bit is set and the LTSSM is in Polling Compliance State the LTSSM transitions to Detect state. Note: This register field is sticky." "0,1" newline bitfld.long 0x4 8. "DIRECT_RECIDLE_TO_CONFIG,Direct Recovery.Idle to Configuration. When this bit is set and the LTSSM is in Recovery Idle State the LTSSM transitions to Configuration state. Note: This register field is sticky." "0,1" newline hexmask.long.byte 0x4 3.--7. 1. "RSVDP_3,Reserved for future use." newline bitfld.long 0x4 2. "NOACK_FORCE_LINKDOWN,Force LinkDown. When this bit is set and the controller detects REPLY_NUM rolling over 4 times the LTSSM transitions to Detect State. Note: This register field is sticky." "0,1" newline bitfld.long 0x4 1. "RECOVERY_REQUEST,Recovery Request. When this bit is set to '1' in L0 or L0s the LTSSM starts transitioning to Recovery State. This request does not cause a speed change or re-equalization." "0,1" newline bitfld.long 0x4 0. "HOLD_LTSSM,Hold and Release LTSSM. For as long as this register is '1' the controller stays in the current LTSSM. Note: This register field is sticky." "0,1" group.long (0xB0+0x30C)++0xB line.long 0x0 "SD_STATUS_L1LANE_REG,Silicon Debug Status(Layer1 Per-lane). This viewport register returns the data selected by the following field: - LANE_SELECT in SD_STATUS_L1LANE_REG For more details. see the RAS DES section in the Core Operations chapter of the.." hexmask.long.byte 0x0 24.--31. 1. "DESKEW_POINTER,Deskew Pointer. Indicates Deskew pointer of internal Deskew buffer of selected lane number(LANE_SELECT). Note: This register field is sticky." newline rbitfld.long 0x0 21.--23. "RSVDP_21,Reserved for future use." "0,1,2,3,4,5,6,7" newline rbitfld.long 0x0 20. "PIPE_TXELECIDLE,PIPE:TxElecIdle. Indicates PIPE TXELECIDLE signal of selected lane number(LANE_SELECT). Note: This register field is sticky." "0,1" newline rbitfld.long 0x0 19. "PIPE_RXELECIDLE,PIPE:RxElecIdle. Indicates PIPE RXELECIDLE signal of selected lane number(LANE_SELECT). Note: This register field is sticky." "0,1" newline rbitfld.long 0x0 18. "PIPE_RXVALID,PIPE:RxValid. Indicates PIPE RXVALID signal of selected lane number(LANE_SELECT). Note: This register field is sticky." "0,1" newline rbitfld.long 0x0 17. "PIPE_DETECT_LANE,PIPE:Detect Lane. Indicates whether PHY indicates receiver detection or not on selected lane number(LANE_SELECT). Note: This register field is sticky." "0,1" newline rbitfld.long 0x0 16. "PIPE_RXPOLARITY,PIPE:RxPolarity. Indicates PIPE RXPOLARITY signal of selected lane number(LANE_SELECT). Note: This register field is sticky." "0,1" newline hexmask.long.word 0x0 4.--15. 1. "RSVDP_4,Reserved for future use." newline hexmask.long.byte 0x0 0.--3. 1. "LANE_SELECT,Lane Select. Lane Select register for Silicon Debug Status Register of Layer1-PerLane. - 0x0: Lane0 - 0x1: Lane1 - 0x2: Lane2 - .. - 0xF: Lane15 Note: This register field is sticky." line.long 0x4 "SD_STATUS_L1LTSSM_REG,Silicon Debug Status(Layer1 LTSSM). For more details. see the RAS DES section in the Core Operations chapter of the Databook." hexmask.long.word 0x4 16.--31. 1. "LTSSM_VARIABLE,LTSSM Variable. Indicates internal LTSSM variables defined in the PCI Express Base Specification. C-PCIe Mode: - 0: directed_speed_change - 1: changed_speed_recovery - 2: successful_speed_negotiation - 3: upconfigure_capable; Set to '1' if.." newline rbitfld.long 0x4 15. "LANE_REVERSAL,Lane Reversal Operation. Receiver detected lane reversal. This field is only valid in the L0 LTSSM state. Note: This register field is sticky." "0,1" newline hexmask.long.byte 0x4 11.--14. 1. "RSVDP_11,Reserved for future use." newline rbitfld.long 0x4 8.--10. "PIPE_POWER_DOWN,PIPE:PowerDown. Indicates PIPE PowerDown signal. Note: This register field is sticky." "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 7. "FRAMING_ERR,Framing Error. Indicates Framing Error detection status." "0,1" newline hexmask.long.byte 0x4 0.--6. 1. "FRAMING_ERR_PTR,First Framing Error Pointer. Identifies the first Framing Error using the following encoding. The field contents are only valid value when FRAMING_ERR =1. Received Unexpected Framing Token - 01h: When non- STP/SDP/IDL Token was received.." line.long 0x8 "SD_STATUS_PM_REG,Silicon Debug Status(PM). For more details. see the RAS DES section in the Core Operations chapter of the Databook." hexmask.long.byte 0x8 24.--31. 1. "RSVDP_24,Reserved for future use." newline hexmask.long.byte 0x8 16.--23. 1. "LATCHED_NFTS,Latched N_FTS. Indicates the value of N_FTS in the received TS Ordered Sets from the Link Partner Note: This register field is sticky." newline rbitfld.long 0x8 13.--15. "L1SUB_STATE,L1Sub State. Indicates internal state machine of L1Sub state. - 0h: S_L1_U : idle state - 1h: S_L1_0 : wait for aux_clk_active - 2h: S_L1_0_WAIT4_ACK : wait for pclkack - 3h: S_L1_0_WAIT4_CLKREQ : wait for clkreq - 4h: S_L1_N_ENTRY : check.." "wait for aux_clk_active,?,?,?,?,?,?,?" newline bitfld.long 0x8 12. "PME_RESEND_FLAG,PME Re-send flag. When the DUT sends a PM_PME message TLP the DUT sets PME_Status bit. If host software does not clear PME_Status bit for 100ms(+50%/-5%) the DUT resends the PM_PME Message. This bit indicates that a PM_PME was resent." "0,1" newline hexmask.long.byte 0x8 8.--11. 1. "INTERNAL_PM_SSTATE,Internal PM State(Slave). Indicates internal state machine of Power Management Slave controller. - 0h: S_IDLE - 1h: S_RESPOND_NAK - 2h: S_BLOCK_TLP - 3h: S_WAIT_LAST_TLP_ACK - 4h: S_WAIT_EIDLE - 5h: S_LINK_ENTR_L1 - 6h: S_L1 - 7h:.." newline rbitfld.long 0x8 5.--7. "RSVDP_5,Reserved for future use." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x8 0.--4. 1. "INTERNAL_PM_MSTATE,Internal PM State(Master). Indicates internal state machine of Power Management Master controller. - 00h: IDLE - 01h: L0 - 02h: L0S - 03h: ENTER_L0S - 04h: L0S_EXIT - 05h: WAIT_PMCSR_CPL_SENT - 08h: L1 - 09h: L1_BLOCK_TLP - 0Ah:.." rgroup.long (0xBC+0x30C)++0x3 line.long 0x0 "SD_STATUS_L2_REG,Silicon Debug Status(Layer2). For more details. see the RAS DES section in the Core Operations chapter of the Databook." hexmask.long.byte 0x0 28.--31. 1. "RSVDP_28,Reserved for future use." newline bitfld.long 0x0 27. "FC_INIT2,FC_INIT2. Indicates the controller is in FC_INIT2(VC0) state. Note: This register field is sticky." "0,1" newline bitfld.long 0x0 26. "FC_INIT1,FC_INIT1. Indicates the controller is in FC_INIT1(VC0) state. Note: This register field is sticky." "0,1" newline bitfld.long 0x0 24.--25. "DLCMSM,DLCMSM. Indicates the current DLCMSM. - 00b: DL_INACTIVE - 01b: DL_FC_INIT - 11b: DL_ACTIVE Note: This register field is sticky." "0,1,2,3" newline hexmask.long.word 0x0 12.--23. 1. "RX_ACK_SEQ_NO,Tx Ack Sequence Number. Indicates ACKD_SEQ which is updated by receiving ACK/NAK DLLP. Note: This register field is sticky." newline hexmask.long.word 0x0 0.--11. 1. "TX_TLP_SEQ_NO,Tx Tlp Sequence Number. Indicates next transmit sequence number for transmit TLP. Note: This register field is sticky." group.long (0xC0+0x30C)++0x7 line.long 0x0 "SD_STATUS_L3FC_REG,Silicon Debug Status(Layer3 FC). The CREDIT_DATA[0/1] fields in this viewport register return the data for the VC and TLP Type selected by the following fields: - CREDIT_SEL_VC - CREDIT_SEL_CREDIT_TYPE - CREDIT_SEL_TLP_TYPE -.." hexmask.long.word 0x0 20.--31. 1. "CREDIT_DATA1,Credit Data1. Current FC credit data selected by the CREDIT_SEL_VC CREDIT_SEL_CREDIT_TYPE CREDIT_SEL_TLP_TYPE and CREDIT_SEL_HD viewport-select fields. - Rx: Credit Allocated Value - Tx: Credit Limit Value. This value is valid when.." newline hexmask.long.word 0x0 8.--19. 1. "CREDIT_DATA0,Credit Data0. Current FC credit data selected by the CREDIT_SEL_VC CREDIT_SEL_CREDIT_TYPE CREDIT_SEL_TLP_TYPE and CREDIT_SEL_HD viewport-select fields. - Rx: Credit Received Value - Tx: Credit Consumed Value Note: This register field is.." newline rbitfld.long 0x0 7. "RSVDP_7,Reserved for future use." "0,1" newline bitfld.long 0x0 6. "CREDIT_SEL_HD,Credit Select(HeaderData). This field in conjunction with the CREDIT_SEL_VC CREDIT_SEL_CREDIT_TYPE and CREDIT_SEL_TLP_TYPE viewport-select fields determines that data that is returned by the CREDIT_DATA0 and CREDIT_DATA1 data fields. -.." "Header Credit,Data Credit" newline bitfld.long 0x0 4.--5. "CREDIT_SEL_TLP_TYPE,Credit Select(TLP Type). This field in conjunction with the CREDIT_SEL_VC CREDIT_SEL_CREDIT_TYPE and CREDIT_SEL_HD viewport-select fields determines that data that is returned by the CREDIT_DATA0 and CREDIT_DATA1 data fields. - 0x0:.." "Posted,Non-Posted,Completion,?" newline bitfld.long 0x0 3. "CREDIT_SEL_CREDIT_TYPE,Credit Select(Credit Type). This field in conjunction with the CREDIT_SEL_VC CREDIT_SEL_TLP_TYPE and CREDIT_SEL_HD viewport-select fields determines that data that is returned by the CREDIT_DATA0 and CREDIT_DATA1 data fields. -.." "Rx,Tx" newline bitfld.long 0x0 0.--2. "CREDIT_SEL_VC,Credit Select(VC). This field in conjunction with the CREDIT_SEL_CREDIT_TYPE CREDIT_SEL_TLP_TYPE and CREDIT_SEL_HD viewport-select fields determines that data that is returned by the CREDIT_DATA0 and CREDIT_DATA1 data fields. - 0x0: VC0 -.." "VC0,VC1,VC2,?,?,?,?,VC7" line.long 0x4 "SD_STATUS_L3_REG,Silicon Debug Status(Layer3). For more details. see the RAS DES section in the Core Operations chapter of the Databook." hexmask.long.tbyte 0x4 8.--31. 1. "RSVDP_8,Reserved for future use." newline bitfld.long 0x4 7. "MFTLP_STATUS,Malformed TLP Status. Indicates malformed TLP has occurred." "0,1" newline hexmask.long.byte 0x4 0.--6. 1. "MFTLP_POINTER,First Malformed TLP Error Pointer. Indicates the element of the received first malformed TLP. This pointer is validated by MFTLP_STATUS. - 01h: AtomicOp address alignment - 02h: AtomicOp operand - 03h: AtomicOp byte enable - 04h: TLP length.." group.long (0xD0+0x30C)++0xB line.long 0x0 "SD_EQ_CONTROL1_REG,Silicon Debug EQ Control 1. This is a viewport control register. Setting the EQ_RATE_SEL and EQ_LANE_SEL fields in this register determine the per-lane Silicon Debug EQ Status data returned by the SD_EQ_STATUS[1/2/3] viewport.." hexmask.long.byte 0x0 24.--31. 1. "FOM_TARGET,FOM Target. Indicates figure of merit target criteria value of EQ Master(DSP in EQ Phase3/USP in EQ Phase2). This field is only valid when GEN3_EQ_FB_MODE is 0001b(Figure Of Merit). Note: This register field is sticky." newline bitfld.long 0x0 23. "FOM_TARGET_ENABLE,FOM Target Enable. Enables the FOM_TARGET fields. Note: This register field is sticky." "0,1" newline hexmask.long.byte 0x0 18.--22. 1. "RSVDP_18,Reserved for future use." newline bitfld.long 0x0 16.--17. "EVAL_INTERVAL_TIME,Eval Interval Time. Indicates interval time of RxEqEval assertion. - 00: 500ns - 01: 1us - 10: 2us - 11: 4us This field is used for EQ Master(DSP in EQ Phase3/USP in EQ Phase2). Note: This register field is sticky." "0,1,2,3" newline hexmask.long.byte 0x0 10.--15. 1. "RSVDP_10,Reserved for future use." newline bitfld.long 0x0 8.--9. "EXT_EQ_TIMEOUT,Extends EQ Phase2/3 Timeout. This field is used when the Ltssm is in Recovery.EQ2/3. When this field is set the value of EQ2/3 timeout is extended. EQ Master(DSP in EQ Phase3/USP in EQ Phase2). - 00: 24ms (default) - 01: 48ms (x2) - 10:.." "0,1,2,3" newline rbitfld.long 0x0 6.--7. "RSVDP_6,Reserved for future use." "0,1,2,3" newline bitfld.long 0x0 4.--5. "EQ_RATE_SEL,EQ Status Rate Select. Setting this field in conjunction with the EQ_LANE_SEL field determines the per-lane Silicon Debug EQ Status data returned by the SD_EQ_CONTROL[2/3] and SD_EQ_STATUS[1/2/3] viewport registers. - 0x0: 8.0GT/s Speed.." "0,1,2,3" newline hexmask.long.byte 0x0 0.--3. 1. "EQ_LANE_SEL,EQ Status Lane Select. Setting this field in conjunction with the EQ_RATE_SEL field determines the per-lane Silicon Debug EQ Status data returned by the SD_EQ_CONTROL[2/3] and SD_EQ_STATUS[1/2/3] viewport registers. - 0x0: Lane0 - 0x1: Lane1.." line.long 0x4 "SD_EQ_CONTROL2_REG,Silicon Debug EQ Control 2. This viewport register returns the value for the rate and lane selected by the EQ_RATE_SEL and EQ_LANE_SEL fields in the SD_EQ_CONTROL1_REG register. For more details. see the RAS DES section in the Core.." rbitfld.long 0x4 31. "RSVDP_31,Reserved for future use." "0,1" newline bitfld.long 0x4 30. "FORCE_LOCAL_TX_PRESET_ENABLE,Force Local Transmitter Preset Enable. Enables the FORCE_LOCAL_TX_PRESET field. If select rate in the EQ_RATE_SEL field is 32.0GT/s Speed this feature is not available. Note: This register field is sticky." "0,1" newline bitfld.long 0x4 29. "FORCE_LOCAL_RX_HINT_ENABLE,Force Local Receiver Preset Hint Enable. Enables the FORCE_LOCAL_RX_HINT field. If select rate in the EQ_RATE_SEL field is other than 8.0GT/s Speed this feature is not available. Note: This register field is sticky." "0,1" newline bitfld.long 0x4 28. "FORCE_LOCAL_TX_COEF_ENABLE,Force Local Transmitter Coefficient Enable. Enables the following fields: - FORCE_LOCAL_TX_PRE_CURSOR - FORCE_LOCAL_TX_CURSOR - FORCE_LOCAL_TX_POST_CURSOR Note: This register field is sticky." "0,1" newline hexmask.long.byte 0x4 24.--27. 1. "FORCE_LOCAL_TX_PRESET,Force Local Transmitter Preset. Indicates initial preset value of USP in EQ Slave(EQ Phase2) instead of receiving EQ TS2. If select rate in the EQ_RATE_SEL field is 32.0GT/s Speed this feature is not available. Note: This register.." newline rbitfld.long 0x4 21.--23. "RSVDP_21,Reserved for future use." "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 18.--20. "FORCE_LOCAL_RX_HINT,Force Local Receiver Preset Hint. Indicates the RxPresetHint value of EQ Slave(DSP in EQ Phase2/USP in EQ Phase3) instead of received or set value. If select rate in the EQ_RATE_SEL field is other than 8.0GT/s Speed this feature is.." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x4 12.--17. 1. "FORCE_LOCAL_TX_POST_CURSOR,Force Local Transmitter Post-Cursor. Indicates the coefficient value of EQ Slave(DSP in EQ Phase2/USP in EQ Phase3) instead of the value instructed from link partner. Note: This register field is sticky." newline hexmask.long.byte 0x4 6.--11. 1. "FORCE_LOCAL_TX_CURSOR,Force Local Transmitter Cursor. Indicates the coefficient value of EQ Slave(DSP in EQ Phase2/USP in EQ Phase3) instead of the value instructed from link partner. Note: This register field is sticky." newline hexmask.long.byte 0x4 0.--5. 1. "FORCE_LOCAL_TX_PRE_CURSOR,Force Local Transmitter Pre-cursor. Indicates the coefficient value of EQ Slave(DSP in EQ Phase2/USP in EQ Phase3) instead of the value instructed from link partner. Note: This register field is sticky." line.long 0x8 "SD_EQ_CONTROL3_REG,Silicon Debug EQ Control 3. This viewport register returns the value for the rate and lane selected by the EQ_RATE_SEL and EQ_LANE_SEL fields in the SD_EQ_CONTROL1_REG register. For more details. see the RAS DES section in the Core.." rbitfld.long 0x8 29.--31. "RSVDP_29,Reserved for future use." "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 28. "FORCE_REMOTE_TX_COEF_ENABLE,Force Remote Transmitter Coefficient Enable. Enables the following fields: - FORCE_REMOTE_TX_PRE_CURSOR - FORCE_REMOTE_TX_CURSOR - FORCE_REMOTE_TX_POST_CURSOR This function can only be used when GEN3_EQ_FB_MODE =.." "0,1" newline hexmask.long.word 0x8 18.--27. 1. "RSVDP_18,Reserved for future use." newline hexmask.long.byte 0x8 12.--17. 1. "FORCE_REMOTE_TX_POST_CURSOR,Force Remote Transmitter Post-Cursor. Indicates the coefficient value of EQ Master(DSP in EQ Phase3/USP in EQ Phase2) instead of the value instructed from local phy in dirchange mode. Note: This register field is sticky." newline hexmask.long.byte 0x8 6.--11. 1. "FORCE_REMOTE_TX_CURSOR,Force Remote Transmitter Cursor. Indicates the coefficient value of EQ Master(DSP in EQ Phase3/USP in EQ Phase2) instead of the value instructed from local phy in dirchange mode. Note: This register field is sticky." newline hexmask.long.byte 0x8 0.--5. 1. "FORCE_REMOTE_TX_PRE_CURSOR,Force Remote Transmitter Pre-Cursor. Indicates the coefficient value of EQ Master(DSP in EQ Phase3/USP in EQ Phase2) instead of the value instructed from local phy in dirchange mode. Note: This register field is sticky." rgroup.long (0xE0+0x30C)++0xB line.long 0x0 "SD_EQ_STATUS1_REG,Silicon Debug EQ Status 1. This viewport register returns the first of three words of Silicon Debug EQ Status data for the rate and lane selected by the EQ_RATE_SEL and EQ_LANE_SEL fields in the SD_EQ_CONTROL1_REG register. The.." hexmask.long.tbyte 0x0 8.--31. 1. "RSVDP_8,Reserved for future use." newline bitfld.long 0x0 7. "EQ_REJECT_EVENT,EQ Reject Event. Indicates that the controller receives two consecutive TS1 OS w/Reject=1b during EQ Master phase(DSP in EQ Phase3/USP in EQ Phase2). This bit is automatically cleared when the controller starts EQ Master phase again." "0,1" newline bitfld.long 0x0 6. "EQ_RULEC_VIOLATION,EQ Rule C Violation. Indicates that coefficients rule C violation is detected in the values provided by PHY using direction change method during EQ Master phase(DSP in EQ Phase3/USP in EQ Phase2). The coefficients rule C correspond to.." "0,1" newline bitfld.long 0x0 5. "EQ_RULEB_VIOLATION,EQ Rule B Violation. Indicates that coefficients rule B violation is detected in the values provided by PHY using direction change method during EQ Master phase(DSP in EQ Phase3/USP in EQ Phase2). The coefficients rules B correspond to.." "0,1" newline bitfld.long 0x0 4. "EQ_RULEA_VIOLATION,EQ Rule A Violation. Indicates that coefficients rule A violation is detected in the values provided by PHY using direction change method during EQ Master phase(DSP in EQ Phase3/USP in EQ Phase2). The coefficients rules A correspond to.." "0,1" newline bitfld.long 0x0 3. "RSVDP_3,Reserved for future use." "0,1" newline bitfld.long 0x0 1.--2. "EQ_CONVERGENCE_INFO,EQ Convergence Info. Indicates equalization convergence information. - 0x0: Equalization is not attempted - 0x1: Equalization finished successfully - 0x2: Equalization finished unsuccessfully - 0x3: Reserved This bit is automatically.." "Equalization is not attempted,Equalization finished successfully,Equalization finished unsuccessfully,Reserved" newline bitfld.long 0x0 0. "EQ_SEQUENCE,EQ Sequence. Indicates that the controller is starting the equalization sequence. Note: This register field is sticky." "0,1" line.long 0x4 "SD_EQ_STATUS2_REG,Silicon Debug EQ Status 2. This viewport register returns the second of three words of Silicon Debug EQ Status data for the rate and lane selected by the EQ_RATE_SEL and EQ_LANE_SEL fields in the SD_EQ_CONTROL1_REG register. Each field.." hexmask.long.byte 0x4 24.--31. 1. "EQ_LOCAL_FOM_VALUE,EQ Local Figure of Merit. Indicates Local maximum Figure of Merit value. Note: This register field is sticky." newline bitfld.long 0x4 21.--23. "RSVDP_21,Reserved for future use." "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 18.--20. "EQ_LOCAL_RX_HINT,EQ Local Receiver Preset Hint. Indicates Local Receiver Preset Hint value. If select rate in the EQ_RATE_SEL field is other than 8.0GT/s Speed this feature is not available. Note: This register field is sticky." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x4 12.--17. 1. "EQ_LOCAL_POST_CURSOR,EQ Local Post-Cursor. Indicates Local post cursor coefficient value. Note: This register field is sticky." newline hexmask.long.byte 0x4 6.--11. 1. "EQ_LOCAL_CURSOR,EQ Local Cursor. Indicates Local cursor coefficient value. Note: This register field is sticky." newline hexmask.long.byte 0x4 0.--5. 1. "EQ_LOCAL_PRE_CURSOR,EQ Local Pre-Cursor. Indicates Local pre cursor coefficient value. Note: This register field is sticky." line.long 0x8 "SD_EQ_STATUS3_REG,Silicon Debug EQ Status 3. This viewport register returns the third of three words of Silicon Debug EQ Status data for the rate and lane selected by the EQ_RATE_SEL and EQ_LANE_SEL fields in the SD_EQ_CONTROL1_REG register. Each field.." bitfld.long 0x8 30.--31. "RSVDP_30,Reserved for future use." "0,1,2,3" newline hexmask.long.byte 0x8 24.--29. 1. "EQ_REMOTE_FS,EQ Remote FS. Indicates Remote FS value. Note: This register field is sticky." newline hexmask.long.byte 0x8 18.--23. 1. "EQ_REMOTE_LF,EQ Remote LF. Indicates Remote LF value. Note: This register field is sticky." newline hexmask.long.byte 0x8 12.--17. 1. "EQ_REMOTE_POST_CURSOR,EQ Remote Post-Cursor. Indicates Remote post cursor coefficient value. Note: This register field is sticky." newline hexmask.long.byte 0x8 6.--11. 1. "EQ_REMOTE_CURSOR,EQ Remote Cursor. Indicates Remote cursor coefficient value. Note: This register field is sticky." newline hexmask.long.byte 0x8 0.--5. 1. "EQ_REMOTE_PRE_CURSOR,EQ Remote Pre-Cursor. Indicates Remote pre cursor coefficient value. Note: This register field is sticky." tree.end tree "PF0_SN_CAP (Device Serial Number Capability Structure)" group.long (0x0+0x170)++0xB line.long 0x0 "SN_BASE,Device Serial Number Extended Capability Header. For a description of this standard PCIe register. see the PCI Express Base Specification." hexmask.long.word 0x0 20.--31. 1. "SN_NEXT_OFFSET,Next Capability Offset. For a description of this standard PCIe register field see the PCI Express Base Specification. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then.." hexmask.long.byte 0x0 16.--19. 1. "SN_CAP_VERSION,Capability Version. For a description of this standard PCIe register field see the PCI Express Base Specification. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky).." hexmask.long.word 0x0 0.--15. 1. "SN_PCIE_EXTENDED_CAP_ID,Serial Number Extended Capability ID. For a description of this standard PCIe register field see the PCI Express Base Specification. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if.." line.long 0x4 "SER_NUM_REG_DW_1,Serial Number 1 Register. For a description of this standard PCIe register. see the PCI Express Base Specification." hexmask.long 0x4 0.--31. 1. "SN_SER_NUM_REG_1_DW,IEEE 64 bit Device Serial Number (DW 1). For a description of this standard PCIe register field see the PCI Express Base Specification. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if.." line.long 0x8 "SER_NUM_REG_DW_2,Serial Number 2 Register. For a description of this standard PCIe register. see the PCI Express Base Specification." hexmask.long 0x8 0.--31. 1. "SN_SER_NUM_REG_2_DW,IEEE 64 bit Device Serial Number (DW 2). For a description of this standard PCIe register field see the PCI Express Base Specification. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if.." tree.end tree "PF0_VSECRAS_CAP (PF RAS Datapath Protection Capability Structure (VSEC))" group.long (0x0+0x480)++0x3 line.long 0x0 "RASDP_EXT_CAP_HDR_OFF,PCIe Extended capability ID. Capability version and Next capability offset. For a description of this standard PCIe register. see the PCI Express Specification." hexmask.long.word 0x0 20.--31. 1. "NEXT_OFFSET,Next Capability Offset. For a description of this standard PCIe register see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else.." newline hexmask.long.byte 0x0 16.--19. 1. "CAP,Capability Version. For a description of this standard PCIe register see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note:.." newline hexmask.long.word 0x0 0.--15. 1. "ID,PCI Express Extended Capability ID. For a description of this standard PCIe register see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else.." rgroup.long (0x4+0x480)++0x3 line.long 0x0 "RASDP_VENDOR_SPECIFIC_HDR_OFF,Vendor Specific Header. For a description of this standard PCIe register. see the PCI Express Specification." hexmask.long.word 0x0 20.--31. 1. "VSEC_LENGTH,VSEC Length. For a description of this standard PCIe register see the PCI Express Specification. Note: This register field is sticky." newline hexmask.long.byte 0x0 16.--19. 1. "VSEC_REV,VSEC Rev. For a description of this standard PCIe register see the PCI Express Specification. Note: This register field is sticky." newline hexmask.long.word 0x0 0.--15. 1. "VSEC_ID,VSEC ID. For a description of this standard PCIe register see the PCI Express Specification. Note: This register field is sticky." group.long (0x8+0x480)++0x7 line.long 0x0 "RASDP_ERROR_PROT_CTRL_OFF,ECC error correction control. Allows you to disable ECC error correction for RAMs and datapath. When the AXI Bridge Module is implemented and the master / slave clocks are asynchronous to the PCIe native controller clock.." hexmask.long.byte 0x0 24.--31. 1. "RSVDP_24,Reserved for future use." newline bitfld.long 0x0 23. "ERROR_PROT_DISABLE_CXS_RX,Error correction disable for CXS Tx path (PCIe Rx path). Note: This register field is sticky." "0,1" newline bitfld.long 0x0 22. "ERROR_PROT_DISABLE_ADM_RX,Error correction disable for ADM Rx path. Note: This register field is sticky." "0,1" newline bitfld.long 0x0 21. "ERROR_PROT_DISABLE_LAYER3_RX,Error correction disable for layer 3 Rx path. Note: This register field is sticky." "0,1" newline bitfld.long 0x0 20. "ERROR_PROT_DISABLE_LAYER2_RX,Error correction disable for layer 2 Rx path. Note: This register field is sticky." "0,1" newline bitfld.long 0x0 19. "ERROR_PROT_DISABLE_DMA_READ,Error correction disable for DMA read engine. Note: This register field is sticky." "0,1" newline bitfld.long 0x0 18. "ERROR_PROT_DISABLE_AXI_BRIDGE_INBOUND_REQUEST,Error correction disable for AXI bridge inbound request path. Note: This register field is sticky." "0,1" newline bitfld.long 0x0 17. "ERROR_PROT_DISABLE_AXI_BRIDGE_INBOUND_COMPLETION,Error correction disable for AXI bridge inbound completion composer. Does not disable the error detection reporting for 1-bit and 2-bit ECC errors. Note: This register field is sticky." "?,bit and 2-bit ECC errors" newline bitfld.long 0x0 16. "ERROR_PROT_DISABLE_RX,Global error correction disable for all Rx layers. Note: This register field is sticky." "0,1" newline hexmask.long.byte 0x0 9.--15. 1. "RSVDP_9,Reserved for future use." newline bitfld.long 0x0 8. "ERROR_PROT_DISABLE_DTIM_TX,Error correction disable for DTIM Tx path. Note: This register field is sticky." "0,1" newline bitfld.long 0x0 7. "ERROR_PROT_DISABLE_CXS_TX,Error correction disable for CXS Rx path (PCIe Tx path). Note: This register field is sticky." "0,1" newline bitfld.long 0x0 6. "ERROR_PROT_DISABLE_ADM_TX,Error correction disable for Adm Tx path. Note: This register field is sticky." "0,1" newline bitfld.long 0x0 5. "ERROR_PROT_DISABLE_LAYER3_TX,Error correction disable for layer 3 Tx path. Note: This register field is sticky." "0,1" newline bitfld.long 0x0 4. "ERROR_PROT_DISABLE_LAYER2_TX,Error correction disable for layer 2 Tx path. Note: This register field is sticky." "0,1" newline bitfld.long 0x0 3. "ERROR_PROT_DISABLE_DMA_WRITE,Error correction disable for DMA write engine. Note: This register field is sticky." "0,1" newline bitfld.long 0x0 2. "ERROR_PROT_DISABLE_AXI_BRIDGE_OUTBOUND,Error correction disable for AXI bridge outbound request path. Note: This register field is sticky." "0,1" newline bitfld.long 0x0 1. "ERROR_PROT_DISABLE_AXI_BRIDGE_MASTER,Error correction disable for AXI bridge master completion buffer. Note: This register field is sticky." "0,1" newline bitfld.long 0x0 0. "ERROR_PROT_DISABLE_TX,Global error correction disable for all Tx layers. Does not disable the error detection reporting for 1-bit and 2-bit ECC errors. Note: This register field is sticky." "?,bit and 2-bit ECC errors" line.long 0x4 "RASDP_CORR_COUNTER_CTRL_OFF,Corrected error (1-bit ECC) counter selection and control. This is a viewport control register. Setting the CORR_COUNTER_SELECTION_REGION and CORR_COUNTER_SELECTION fields in this register determine the counter data returned.." hexmask.long.byte 0x4 24.--31. 1. "CORR_COUNTER_SELECTION,Counter selection. This field selects the counter ID (within the region defined by CORR_COUNTER_SELECTION_REGION) whose contents can be read from the RASDP_CORR_COUNT_REPORT_OFF register. You can cycle this field value from 0 to.." newline hexmask.long.byte 0x4 20.--23. 1. "CORR_COUNTER_SELECTION_REGION,Select correctable counter region: - 0x0: Region select for Adm Rx path - 0x1: Region select for layer 3 Rx path - 0x2: Region select for layer 2 Rx path - 0x3: Region select for DMA inbound path - 0x4: Region select for AXI.." newline hexmask.long.word 0x4 5.--19. 1. "RSVDP_5,Reserved for future use." newline bitfld.long 0x4 4. "CORR_EN_COUNTERS,Enable correctable errors counters. - 1: counters increment when the controller detects a correctable error - 0: counters are frozen The counters are enabled by default." "counters are frozen,counters increment when the controller detects a.." newline rbitfld.long 0x4 1.--3. "RSVDP_1,Reserved for future use." "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 0. "CORR_CLEAR_COUNTERS,Clear all correctable error counters." "0,1" rgroup.long (0x10+0x480)++0x3 line.long 0x0 "RASDP_CORR_COUNT_REPORT_OFF,Corrected error (1-bit ECC) counter data. This viewport register returns the counter data selected by the CORR_COUNTER_SELECTION_REGION and CORR_COUNTER_SELECTION fields in the RASDP_CORR_COUNTER_CTRL_OFF register." hexmask.long.byte 0x0 24.--31. 1. "CORR_COUNTER_SELECTED,Counter selection. Returns the value set in the CORR_COUNTER_SELECTION field of the RASDP_CORR_COUNTER_CTRL_OFF register." newline hexmask.long.byte 0x0 20.--23. 1. "CORR_COUNTER_SELECTED_REGION,Selected correctable counter region: - 0x0: Region select for Adm Rx path - 0x1: Region select for layer 3 Rx path - 0x2: Region select for layer 2 Rx path - 0x3: Region select for DMA inbound path - 0x4: Region select for.." newline hexmask.long.word 0x0 8.--19. 1. "RSVDP_8,Reserved for future use." newline hexmask.long.byte 0x0 0.--7. 1. "CORR_COUNTER,Current corrected error count for the selected counter." group.long (0x14+0x480)++0x3 line.long 0x0 "RASDP_UNCORR_COUNTER_CTRL_OFF,Uncorrected error (2-bit ECC and parity) counter selection and control. This is a viewport control register. Setting the UNCORR_COUNTER_SELECTION_REGION and UNCORR_COUNTER_SELECTION fields in this register determine the.." hexmask.long.byte 0x0 24.--31. 1. "UNCORR_COUNTER_SELECTION,Counter selection. This field selects the counter ID (within the region defined by UNCORR_COUNTER_SELECTION_REGION) whose contents can be read from the RASDP_UNCORR_COUNT_REPORT_OFF register. You can cycle this field value from 0.." newline hexmask.long.byte 0x0 20.--23. 1. "UNCORR_COUNTER_SELECTION_REGION,Select uncorrectable counter region: - 0x0: Region select for Adm Rx path - 0x1: Region select for layer 3 Rx path - 0x2: Region select for layer 2 Rx path - 0x3: Region select for DMA inbound path - 0x4: Region select for.." newline hexmask.long.word 0x0 5.--19. 1. "RSVDP_5,Reserved for future use." newline bitfld.long 0x0 4. "UNCORR_EN_COUNTERS,Enable uncorrectable errors counters. - 1: enables the counters to increment on detected correctable errors - 0: counters are frozen The counters are enabled by default." "counters are frozen,enables the counters to increment on detected.." newline rbitfld.long 0x0 1.--3. "RSVDP_1,Reserved for future use." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 0. "UNCORR_CLEAR_COUNTERS,Clear uncorrectable errors counters. When asserted causes all counters tracking the uncorrectable errors to be cleared." "0,1" rgroup.long (0x18+0x480)++0x3 line.long 0x0 "RASDP_UNCORR_COUNT_REPORT_OFF,Uncorrected error (2-bit ECC and parity) counter data. This viewport register returns the counter data selected by the UNCORR_COUNTER_SELECTION_REGION and UNCORR_COUNTER_SELECTION fields in the RASDP_UNCORR_COUNTER_CTRL_OFF.." hexmask.long.byte 0x0 24.--31. 1. "UNCORR_COUNTER_SELECTED,Counter selection. Returns the value set in the UNCORR_COUNTER_SELECTION field of the RASDP_UNCORR_COUNTER_CTRL_OFF register." newline hexmask.long.byte 0x0 20.--23. 1. "UNCORR_COUNTER_SELECTED_REGION,Selected uncorrectable counter region: - 0x0: Region select for Adm Rx path - 0x1: Region select for layer 3 Rx path - 0x2: Region select for layer 2 Rx path - 0x3: Region select for DMA inbound path - 0x4: Region select.." newline hexmask.long.word 0x0 8.--19. 1. "RSVDP_8,Reserved for future use." newline hexmask.long.byte 0x0 0.--7. 1. "UNCORR_COUNTER,Current uncorrected error count for the selected counter" group.long (0x1C+0x480)++0x3 line.long 0x0 "RASDP_ERROR_INJ_CTRL_OFF,Error injection control for the following features: - 1-bit or 2-bit injection - Continuous or fixed-number (n) injection modes - Global enable/disable - Selectable location where injection occurs" hexmask.long.byte 0x0 24.--31. 1. "RSVDP_24,Reserved for future use." newline hexmask.long.byte 0x0 16.--23. 1. "ERROR_INJ_LOC,Error injection location. Selects where error injection takes place. You can cycle this field value from 0 to 255 to access all locations according to the detailed report of check points at.." newline hexmask.long.byte 0x0 8.--15. 1. "ERROR_INJ_COUNT,Error injection count. - 0: errors are inserted in every TLP until you clear ERROR_INJ_EN. - 1: one errors injected - 2: two errors injected - n: amount of errors injected" newline rbitfld.long 0x0 6.--7. "RSVDP_6,Reserved for future use." "0,1,2,3" newline bitfld.long 0x0 4.--5. "ERROR_INJ_TYPE,Error injection type: - 0: none - 1: 1-bit - 2: 2-bit" "none,bit,bit,?" newline rbitfld.long 0x0 1.--3. "RSVDP_1,Reserved for future use." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 0. "ERROR_INJ_EN,Error injection global enable. When set enables the error insertion logic." "0,1" rgroup.long (0x20+0x480)++0x7 line.long 0x0 "RASDP_CORR_ERROR_LOCATION_OFF,Corrected errors locations. For more details. see the RAS Data Protection (DP) section in the Core Operations chapter of the Databook." hexmask.long.byte 0x0 24.--31. 1. "LOC_LAST_CORR_ERROR,Location/ID of the last corrected error within the region defined by REG_LAST_CORR_ERROR. You can cycle this field value from 0 to 255 to access all counters according to the detailed report of check points at.." newline hexmask.long.byte 0x0 20.--23. 1. "REG_LAST_CORR_ERROR,Region of the last corrected error: - 0x0: Region select for Adm Rx path - 0x1: Region select for layer 3 Rx path - 0x2: Region select for layer 2 Rx path - 0x3: Region select for DMA inbound path - 0x4: Region select for AXI bridge.." newline hexmask.long.byte 0x0 16.--19. 1. "RSVDP_16,Reserved for future use." newline hexmask.long.byte 0x0 8.--15. 1. "LOC_FIRST_CORR_ERROR,Location/ID of the first corrected error within the region defined by REG_FIRST_CORR_ERROR. You can cycle this field value from 0 to 255 to access all counters according to the detailed report of check points at.." newline hexmask.long.byte 0x0 4.--7. 1. "REG_FIRST_CORR_ERROR,Region of the first corrected error: - 0x0: Region select for Adm Rx path - 0x1: Region select for layer 3 Rx path - 0x2: Region select for layer 2 Rx path - 0x3: Region select for DMA inbound path - 0x4: Region select for AXI bridge.." newline hexmask.long.byte 0x0 0.--3. 1. "RSVDP_0,Reserved for future use." line.long 0x4 "RASDP_UNCORR_ERROR_LOCATION_OFF,Uncorrected errors locations. For more details. see the RAS Data Protection (DP) section in the Core Operations chapter of the Databook." hexmask.long.byte 0x4 24.--31. 1. "LOC_LAST_UNCORR_ERROR,Location/ID of the last uncorrected error within the region defined by REG_LAST_UNCORR_ERROR. You can cycle this field value from 0 to 255 to access all counters according to the detailed report of check points at.." newline hexmask.long.byte 0x4 20.--23. 1. "REG_LAST_UNCORR_ERROR,Region of the last uncorrected error: - 0x0: Region select for Adm Rx path - 0x1: Region select for layer 3 Rx path - 0x2: Region select for layer 2 Rx path - 0x3: Region select for DMA inbound path - 0x4: Region select for AXI.." newline hexmask.long.byte 0x4 16.--19. 1. "RSVDP_16,Reserved for future use." newline hexmask.long.byte 0x4 8.--15. 1. "LOC_FIRST_UNCORR_ERROR,Location/ID of the first uncorrected error within the region defined by REG_FIRST_UNCORR_ERROR. You can cycle this field value from 0 to 255 to access all counters according to the detailed report of check points at.." newline hexmask.long.byte 0x4 4.--7. 1. "REG_FIRST_UNCORR_ERROR,Region of the first uncorrected error: - 0x0: Region select for Adm Rx path - 0x1: Region select for layer 3 Rx path - 0x2: Region select for layer 2 Rx path - 0x3: Region select for DMA inbound path - 0x4: Region select for AXI.." newline hexmask.long.byte 0x4 0.--3. 1. "RSVDP_0,Reserved for future use." group.long (0x28+0x480)++0x7 line.long 0x0 "RASDP_ERROR_MODE_EN_OFF,RASDP error mode enable. The controller enters RASDP error mode (if ERROR_MODE_EN =1) upon detection of the first uncorrectable error. During this mode: - Rx TLPs that are forwarded to your application are not guaranteed to be.." hexmask.long 0x0 2.--31. 1. "RSVDP_2,Reserved for future use." newline bitfld.long 0x0 1. "AUTO_LINK_DOWN_EN,Write '1' to enable the controller to bring the link down when the controller enters RASDP error mode. Note: This register field is sticky." "0,1" newline bitfld.long 0x0 0. "ERROR_MODE_EN,Write '1' to enable the controller enter RASDP error mode when it detects an uncorrectable error. Note: This register field is sticky." "0,1" line.long 0x4 "RASDP_ERROR_MODE_CLEAR_OFF,Exit RASDP error mode. For more details. see the RAS Data Protection (DP) section in the Core Operations chapter of the Databook." hexmask.long 0x4 1.--31. 1. "RSVDP_1,Reserved for future use." newline bitfld.long 0x4 0. "ERROR_MODE_CLEAR,Write '1' to take the controller out of RASDP error mode. The controller will then report uncorrectable errors (through AER internal error reporting) and also stop nullifying/discarding TLPs." "0,1" rgroup.long (0x30+0x480)++0x7 line.long 0x0 "RASDP_RAM_ADDR_CORR_ERROR_OFF,RAM Address where a corrected error (1-bit ECC) has been detected. For more details. see the RAS Data Protection (DP) section in the Core Operations chapter of the Databook." hexmask.long.byte 0x0 28.--31. 1. "RAM_INDEX_CORR_ERROR,RAM index where a corrected error (1-bit ECC) has been detected." newline bitfld.long 0x0 27. "RSVDP_27,Reserved for future use." "0,1" newline hexmask.long 0x0 0.--26. 1. "RAM_ADDR_CORR_ERROR,RAM Address where a corrected error (1-bit ECC) has been detected." line.long 0x4 "RASDP_RAM_ADDR_UNCORR_ERROR_OFF,RAM Address where an uncorrected error (2-bit ECC) has been detected. For more details. see the RAS Data Protection (DP) section in the Core Operations chapter of the Databook." hexmask.long.byte 0x4 28.--31. 1. "RAM_INDEX_UNCORR_ERROR,RAM index where an uncorrected error (2-bit ECC) has been detected." newline bitfld.long 0x4 27. "RSVDP_27,Reserved for future use." "0,1" newline hexmask.long 0x4 0.--26. 1. "RAM_ADDR_UNCORR_ERROR,RAM Address where an uncorrected error (2-bit ECC) has been detected." tree.end tree "PF0_RTR_CAP (PF RTR Capability Structure)" group.long (0x0+0x2F8)++0xB line.long 0x0 "RTR_EXT_CAP_HDR_OFF,Readiness Time Reporting PCI Express Extended Capability Header. For a description of this standard PCIe register. see the PCI Express Specification." hexmask.long.word 0x0 20.--31. 1. "RTR_NEXT_OFFSET,Next Capability Offset. For a description of this standard PCIe register field see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky).." hexmask.long.byte 0x0 16.--19. 1. "RTR_CAP_VERSION,Capability Version. For a description of this standard PCIe register field see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky).." hexmask.long.word 0x0 0.--15. 1. "RTR_EXT_CAP_ID,PCI Express Extended Capability ID. For a description of this standard PCIe register field see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then.." line.long 0x4 "READI_TIME_REPORTING1_OFF,Readiness Time Reporting 1. For a description of this standard PCIe register. see the PCI Express Specification." bitfld.long 0x4 31. "RTR_TIME_VALID,Valid. For a description of this standard PCIe register field see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky)" "0,1" hexmask.long.byte 0x4 24.--30. 1. "RSVDP_24,Reserved for future use." hexmask.long.word 0x4 12.--23. 1. "DL_UP_TIME,DL_UP Time. For a description of this standard PCIe register field see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky)" hexmask.long.word 0x4 0.--11. 1. "RESET_TIME,Reset Time. For a description of this standard PCIe register field see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky)" line.long 0x8 "READI_TIME_REPORTING2_OFF,Readiness Time Reporting 2. For a description of this standard PCIe register. see the PCI Express Specification." hexmask.long.byte 0x8 24.--31. 1. "RSVDP_24,Reserved for future use." hexmask.long.word 0x8 12.--23. 1. "D3HOT_D0_TIME,D3hot to D0 Time. For a description of this standard PCIe register field see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else.." hexmask.long.word 0x8 0.--11. 1. "FLR_TIME,FLR Time. For a description of this standard PCIe register field see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky)" tree.end tree "PF0_RTR_CAP_DBI2 (DBI2 Shadow Block: PF RTR Capability Structure)" rgroup.long (0x4+0x12F8)++0x7 line.long 0x0 "SHADOW_READI_TIME_REPORTING1_OFF,Shadow Register Readiness Time Reporting 1. For a description of this standard PCIe register. see the PCI Express Specification." bitfld.long 0x0 31. "RTR_TIME_VALID,Shadow Valid in the shadow register. For a description of this standard PCIe register field see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access - Dbi: No access - Dbi2: if.." "0,1" hexmask.long.tbyte 0x0 12.--30. 1. "RSVDP_12,Reserved for future use." hexmask.long.word 0x0 0.--11. 1. "RESET_TIME,Shadow Reset Time in the shadow register. For a description of this standard PCIe register field see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access - Dbi: No access - Dbi2: if.." line.long 0x4 "SHADOW_READI_TIME_REPORTING2_OFF,Shadow Register Readiness Time Reporting 2. For a description of this standard PCIe register. see the PCI Express Specification." hexmask.long.byte 0x4 24.--31. 1. "RSVDP_24,Reserved for future use." hexmask.long.word 0x4 12.--23. 1. "D3HOT_D0_TIME,Shadow D3hot to D0 Time in the shadow register. For a description of this standard PCIe register field see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access - Dbi: No access - Dbi2:.." hexmask.long.word 0x4 0.--11. 1. "FLR_TIME,Shadow FLR Time in the shadow register. For a description of this standard PCIe register field see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access - Dbi: No access - Dbi2: if.." tree.end tree "PF0_FRSQ_CAP (PF FRSQ Capability Structure)" group.long (0x0+0x2E8)++0xB line.long 0x0 "FRSQ_EXT_CAP_HDR_OFF,FRS Queuing Extended Capability Header. For a description of this standard PCIe register. see the PCI Express Specification." hexmask.long.word 0x0 20.--31. 1. "FRSQ_NEXT_OFFSET,Next Capability Offset. For a description of this standard PCIe register field see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then.." hexmask.long.byte 0x0 16.--19. 1. "FRSQ_CAP_VERSION,Capability Version. For a description of this standard PCIe register field see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky).." hexmask.long.word 0x0 0.--15. 1. "FRSQ_EXT_CAP_ID,PCI Express Extended Capability ID. For a description of this standard PCIe register field see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then.." line.long 0x4 "FRSQ_CAP_OFF,FRS Queuing Capability Register. For a description of this standard PCIe register. see the PCI Express Specification." hexmask.long.word 0x4 21.--31. 1. "RSVDP_21,Reserved for future use." hexmask.long.byte 0x4 16.--20. 1. "FRS_INT_MESSAGE_NUMBER,FRS Interrupt Message Number. For a description of this standard PCIe register field see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1).." hexmask.long.byte 0x4 12.--15. 1. "RSVDP_12,Reserved for future use." hexmask.long.word 0x4 0.--11. 1. "FRSQ_MAX_DEPTH,FRS Queue Max Depth. For a description of this standard PCIe register field see the PCI Express Specification." line.long 0x8 "FRSQ_CONTROL_FRSQ_STATUS_OFF,FRS Queuing Status and Control Register. For a description of this standard PCIe register. see the PCI Express Specification." hexmask.long.word 0x8 17.--31. 1. "RSVDP_17,Reserved for future use." bitfld.long 0x8 16. "FRS_INTERRUPT_ENABLE,FRS Interrupt Enable. For a description of this standard PCIe register field see the PCI Express Specification." "0,1" hexmask.long.word 0x8 2.--15. 1. "RSVDP_2,Reserved for future use." bitfld.long 0x8 1. "FRS_MESSAGE_OVERFLOW,FRS Message Overflow. For a description of this standard PCIe register field see the PCI Express Specification." "0,1" newline bitfld.long 0x8 0. "FRS_MESSAGE_RECEIVED,FRS Message Received. For a description of this standard PCIe register field see the PCI Express Specification." "0,1" rgroup.long (0xC+0x2E8)++0x3 line.long 0x0 "FRS_MESSAGE_QUEUE_OFF,FRS Message Queue Register. For a description of this standard PCIe register. see the PCI Express Specification." hexmask.long.word 0x0 20.--31. 1. "FRS_MESSAGE_QUE_DEPTH,FRS Message Queue Depth. For a description of this standard PCIe register field see the PCI Express Specification." hexmask.long.byte 0x0 16.--19. 1. "FRS_MESSAGE_QUE_REASON,FRS Message Queue Reason. For a description of this standard PCIe register field see the PCI Express Specification." hexmask.long.word 0x0 0.--15. 1. "FRS_MESSAGE_QUE_FUNC_ID,FRS Message Queue Function ID. For a description of this standard PCIe register field see the PCI Express Specification." tree.end tree "PF0_PTM_CAP (PF PTM Capability Structure)" group.long (0x0+0x40C)++0xB line.long 0x0 "PTM_EXT_CAP_HDR_OFF,Precision Time Measurement Capability Header. For a description of this standard PCIe register. see the PCI Express Specification." hexmask.long.word 0x0 20.--31. 1. "PTM_NEXT_OFFSET,Precision Time Measurement PCI Express Extended Capability Next Offset. For a description of this standard PCIe register see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access. -.." hexmask.long.byte 0x0 16.--19. 1. "PTM_CAP_VERSION,Precision Time Measurement PCI Express Extended Capability Version. For a description of this standard PCIe register see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi:.." hexmask.long.word 0x0 0.--15. 1. "PTM_CAP_ID,Precision Time Measurement PCI Express Extended Capability ID. For a description of this standard PCIe register see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if.." line.long 0x4 "PTM_CAP_OFF,PTM Capability Register. For a description of this standard PCIe register. see the PCI Express Specification." hexmask.long.word 0x4 16.--31. 1. "RSVDP_16,Reserved for future use." hexmask.long.byte 0x4 8.--15. 1. "PTM_CLK_GRAN,PTM Local Clock Granularity. For a description of this standard PCIe register see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky).." hexmask.long.byte 0x4 3.--7. 1. "RSVDP_3,Reserved for future use." bitfld.long 0x4 2. "PTM_ROOT_CAPABLE,PTM Root Capable. For a description of this standard PCIe register see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else.." "0,1" bitfld.long 0x4 1. "PTM_RES_CAPABLE,PTM Responder Capable. For a description of this standard PCIe register see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else.." "0,1" newline bitfld.long 0x4 0. "PTM_REQ_CAPABLE,PTM Requester Capable. For a description of this standard PCIe register see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else.." "0,1" line.long 0x8 "PTM_CONTROL_OFF,PTM Control Register. For a description of this standard PCIe register. see the PCI Express Specification." hexmask.long.word 0x8 16.--31. 1. "RSVDP_16,Reserved for future use." hexmask.long.byte 0x8 8.--15. 1. "EFF_GRAN,PTM Effective Granularity. For a description of this standard PCIe register see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: HWINIT" hexmask.long.byte 0x8 2.--7. 1. "RSVDP_2,Reserved for future use." rbitfld.long 0x8 1. "ROOT_SELECT,PTM Root Select. When set this Time Source is the PTM Root. For a description of this standard PCIe register see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: HWINIT" "0,1" bitfld.long 0x8 0. "PTM_ENABLE,PTM Enable. When set this function is permitted to participate in the PTM mechanism. For a description of this standard PCIe register see the PCI Express Specification." "0,1" tree.end tree "PF0_PTM_RES_CAP (PF PTM Responder Capability Structure (VSEC))" group.long (0x0+0x418)++0xB line.long 0x0 "PTM_RES_CAP_HDR_OFF,Precision Time Measurement Responder Capability Header (VSEC). For more details. see the PTM section in the Databook." hexmask.long.word 0x0 20.--31. 1. "PTM_RES_EXT_CAP_NEXT_OFFS,Precision Time Measurement Responder VSEC Next Pointer. For more details see the PTM section in the Databook. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then.." hexmask.long.byte 0x0 16.--19. 1. "PTM_RES_EXT_CAP_VER,Precision Time Measurement Responder VSEC Version. For more details see the PTM section in the Databook. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else.." hexmask.long.word 0x0 0.--15. 1. "PTM_RES_EXT_CAP_ID,Precision Time Measurement Responder VSEC ID. For more details see the PTM section in the Databook. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else.." line.long 0x4 "PTM_RES_HDR_OFF,Precision Time Measurement Responder Vendor Specific Header. For more details. see the PTM section in the Databook." hexmask.long.word 0x4 20.--31. 1. "PTM_RES_VSEC_LENGTH,PTM Responder VSEC Length. For more details see the PTM section in the Databook. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This.." hexmask.long.byte 0x4 16.--19. 1. "PTM_RES_VSEC_REV,PTM Responder VSEC Revision. For more details see the PTM section in the Databook. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This.." hexmask.long.word 0x4 0.--15. 1. "PTM_RES_VSEC_ID,PTM Responder VSEC ID. For more details see the PTM section in the Databook. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register.." line.long 0x8 "PTM_RES_CONTROL_OFF,PTM Responder Control Register. For more details. see the PTM section in the Databook." hexmask.long 0x8 2.--31. 1. "RSVDP_2,Reserved for future use." bitfld.long 0x8 1. "PTM_RES_PDEL_BYTE_REV,PTM Requester Propagation Delay Byte Reversal - Reverse the order of bytes in the PTM Propagation Delay data word of the PTM ResponseD Message for compatibility with previous revisions. For more details see the PTM section in the.." "0,1" bitfld.long 0x8 0. "PTM_RES_CCONTEXT_VALID,PTM Responder Control Context Valid - PTM Local Timing is valid. This bit is set over the DBI. A speed change or aux_clk_active will set this bit low. For more details see the PTM section in the Databook. Note: The access.." "0,1" rgroup.long (0xC+0x418)++0x3 line.long 0x0 "PTM_RES_STATUS_OFF,PTM Responder Status Register. For more details. see the PTM section in the Databook." hexmask.long 0x0 2.--31. 1. "RSVDP_2,Reserved for future use." bitfld.long 0x0 1. "PTM_RES_REQUEST_RECEIVED,PTM 1st Request Received - PTM Responder has received the first PTM Request Message. Upon receipt of a second PTM Request Message a ResponseD message with timing information will be sent from the Responder if the context is.." "0,1" bitfld.long 0x0 0. "PTM_RES_CONTEXT_VALID,PTM Responder Status Context Valid - PTM Local Timing Context is Valid. Value set from upstream port Requester in a Switch. Shadows the same in the control register in all other products. For more details see the PTM section in the.." "0,1" group.long (0x10+0x418)++0x7 line.long 0x0 "PTM_RES_LOCAL_LSB_OFF,PTM Responder Local Clock LSB. For more details. see the PTM section in the Databook." hexmask.long 0x0 0.--31. 1. "PTM_RES_LOCAL_LSB,PTM Responder Local Clock LSB - Lower 32 bits of local timer value. For more details see the PTM section in the Databook. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then.." line.long 0x4 "PTM_RES_LOCAL_MSB_OFF,PTM Responder Local Clock MSB. For more details. see the PTM section in the Databook." hexmask.long 0x4 0.--31. 1. "PTM_RES_LOCAL_MSB,PTM Responder Local Clock MSB - Upper 32 bits of local timer value. For more details see the PTM section in the Databook. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then.." rgroup.long (0x18+0x418)++0x1F line.long 0x0 "PTM_RES_T2_LSB_OFF,PTM Responder T2 Timestamp LSB. For more details. see the PTM section in the Databook." hexmask.long 0x0 0.--31. 1. "PTM_RES_T2_LSB,PTM Responder T2 Timestamp LSB - Lower 32 bits of the T2 Timestamp value. For more details see the PTM section in the Databook. Note: This register field is sticky." line.long 0x4 "PTM_RES_T2_MSB_OFF,PTM Responder T2 Timestamp MSB. For more details. see the PTM section in the Databook." hexmask.long 0x4 0.--31. 1. "PTM_RES_T2_MSB,PTM Responder T2 Timestamp MSB - Upper 32 bits of the T2 Timestamp value. For more details see the PTM section in the Databook. Note: This register field is sticky." line.long 0x8 "PTM_RES_T2P_LSB_OFF,PTM Responder T2 Previous Timestamp LSB. For more details. see the PTM section in the Databook." hexmask.long 0x8 0.--31. 1. "PTM_RES_T2P_LSB,PTM Responder T2 Previous Timestamp LSB - Lower 32 bits of the previously stored T2 Timestamp value. For more details see the PTM section in the Databook. Note: This register field is sticky." line.long 0xC "PTM_RES_T2P_MSB_OFF,PTM Responder T2 Previous Timestamp MSB. For more details. see the PTM section in the Databook." hexmask.long 0xC 0.--31. 1. "PTM_RES_T2P_MSB,PTM Responder T2 Previous Timestamp MSB - Upper 32 bits of the previously stored T2 Timestamp value. For more details see the PTM section in the Databook. Note: This register field is sticky." line.long 0x10 "PTM_RES_T3_LSB_OFF,PTM Responder T3 Timestamp LSB. For more details. see the PTM section in the Databook." hexmask.long 0x10 0.--31. 1. "PTM_RES_T3_LSB,PTM Responder T3 Timestamp LSB - Lower 32 bits of the T3 Timestamp value. For more details see the PTM section in the Databook. Note: This register field is sticky." line.long 0x14 "PTM_RES_T3_MSB_OFF,PTM Responder T3 Timestamp MSB. For more details. see the PTM section in the Databook." hexmask.long 0x14 0.--31. 1. "PTM_RES_T3_MSB,PTM Responder T3 Timestamp MSB - Upper 32 bits of the T2 Timestamp value. For more details see the PTM section in the Databook. Note: This register field is sticky." line.long 0x18 "PTM_RES_T3P_LSB_OFF,PTM Responder T3 Previous Timestamp LSB. For more details. see the PTM section in the Databook." hexmask.long 0x18 0.--31. 1. "PTM_RES_T3P_LSB,PTM Responder T3 Previous Timestamp LSB - Lower 32 bits of the previously stored T3 Timestamp value. For more details see the PTM section in the Databook. Note: This register field is sticky." line.long 0x1C "PTM_RES_T3P_MSB_OFF,PTM Responder T3 Previous Timestamp MSB. For more details. see the PTM section in the Databook." hexmask.long 0x1C 0.--31. 1. "PTM_RES_T3P_MSB,PTM Responder T3 Previous Timestamp MSB - Upper 32 bits of the previously stored T3 Timestamp value. For more details see the PTM section in the Databook. Note: This register field is sticky." group.long (0x38+0x418)++0x7 line.long 0x0 "PTM_RES_TX_LATENCY_OFF,PTM Responder TX Latency. For more details. see the PTM section in the Databook." hexmask.long.tbyte 0x0 12.--31. 1. "RSVDP_12,Reserved for future use." hexmask.long.word 0x0 0.--11. 1. "PTM_RES_TX_LATENCY,PTM Responder TX Latency - Responder Transmit path latency (12 bit wide). For more details see the PTM section in the Databook. Note: This register field is sticky." line.long 0x4 "PTM_RES_RX_LATENCY_OFF,PTM Responder RX Latency. For more details. see the PTM section in the Databook." hexmask.long.tbyte 0x4 12.--31. 1. "RSVDP_12,Reserved for future use." hexmask.long.word 0x4 0.--11. 1. "PTM_RES_RX_LATENCY,PTM Responder RX Latency - Responder Receive path latency (12 bit wide). For more details see the PTM section in the Databook. Note: This register field is sticky." rgroup.long (0x40+0x418)++0x3 line.long 0x0 "PTM_RES_NOM_CLOCK_T_OFF,PTM Responder Nominal Clock Period. For more details. see the PTM section in the Databook." hexmask.long.byte 0x0 24.--31. 1. "RSVDP_24,Reserved for future use." hexmask.long.byte 0x0 16.--23. 1. "PTM_RES_NOM_CLOCK_T_INT,PTM Responder Nominal Clock Period Integral - Integral part of the nominal PTM local clock period in nanoseconds. For more details see the PTM section in the Databook. Note: This register field is sticky." hexmask.long.word 0x0 0.--15. 1. "PTM_RES_NOM_CLOCK_T_FRAC,PTM Responder Nominal Clock Period Fractional - Fractional part of the nominal PTM local clock period. LSB is 1/(2^16) nanoseconds. For more details see the PTM section in the Databook. Note: This register field is sticky." group.long (0x44+0x418)++0x3 line.long 0x0 "PTM_RES_SCALED_CLOCK_T_OFF,PTM Responder Scaled Clock Period. For more details. see the PTM section in the Databook." bitfld.long 0x0 31. "PTM_RES_SCALED_CLOCK_T_EN,PTM Responder Scaled Clock Period Enable - Use the programmed scaled PTM clock period rather than the nominal values. This bit is cleared when the core_clk rate starts to change and can only be set when the clock period change.." "0,1" hexmask.long.byte 0x0 24.--30. 1. "RSVDP_24,Reserved for future use." hexmask.long.byte 0x0 16.--23. 1. "PTM_RES_SCALED_CLOCK_T_INT,PTM Responder Scaled Clock Period Integral - Integral part of the nominal PTM local clock period in nanoseconds. For more details see the PTM section in the Databook. Note: This register field is sticky." newline hexmask.long.word 0x0 0.--15. 1. "PTM_RES_SCALED_CLOCK_T_FRAC,PTM Responder Scaled Clock Period Fractional - Fractional part of the nominal PTM local clock period. LSB is 1/(2^16) nanoseconds. For more details see the PTM section in the Databook. Note: This register field is sticky." tree.end tree "PF0_PM_CAP (PF PCI Power Management Capability Structure)" group.long (0x0+0x40)++0x7 line.long 0x0 "CAP_ID_NXT_PTR_REG,Power Management Capabilities Register." hexmask.long.byte 0x0 27.--31. 1. "PME_SUPPORT,PME_Support. This 5-bit field indicates the power states in which the function may generate a PME and/or forward PME messages. A value of 0b for any bit indicates that the function is not capable of asserting PME while in that power state. -.." bitfld.long 0x0 26. "D2_SUPPORT,D2_Support. If this bit is set this function supports the D2 Power Management state. Functions that do not support D2 must always return a value of 0b for this bit. Note: The access attributes of this field are as follows: - Wire: No access." "0,1" bitfld.long 0x0 25. "D1_SUPPORT,D1_Support. If this bit is set this function supports the D1 Power Management state. Functions that do not support D1 must always return a value of 0b for this bit. Note: The access attributes of this field are as follows: - Wire: No access." "0,1" bitfld.long 0x0 22.--24. "AUX_CURR,Aux_Current. This 3 bit field reports the Vaux auxiliary current requirements for the function. If this function implements the Data Register the controller hardwires this field to 000b. If PME_Support is 0 xxxxb (PME assertion from D3cold is.." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 21. "DSI,Device Specific Initialization. The DSI bit indicates whether special initialization of this function is required. When set indicates that the function requires a device specific initialization sequence following a transition to the D0uninitialized.." "0,1" bitfld.long 0x0 20. "PME_IMM_READI_RETURN_DO,Immediate_Readiness_on_Return_to_D0. - If this bit is a '1' this function is guaranteed to be ready to successfully complete valid accesses immediately after being set to D0. These accesses include configuration cycles and if.." "0,1" rbitfld.long 0x0 19. "PME_CLK,PME Clock. Does not apply to PCI Express the controller hardwires it to 0b. Note: This register field is sticky." "0,1" bitfld.long 0x0 16.--18. "PM_SPEC_VER,Version. This field provides the Power Management specification version. The controller hardwires this field to 011b for functions compliant to PCI Express Base Specification Revision 4.0 Version 1.0>. Note: The access attributes of this.." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x0 8.--15. 1. "PM_NEXT_POINTER,Next Capability Pointer. This field provides an offset into the function's configuration space pointing to the location of next item in the capabilities list. If there are no additional items in the capabilities list this field is set to.." hexmask.long.byte 0x0 0.--7. 1. "PM_CAP_ID,Capability ID. This field returns 01h to indicate that this is the PCI Power Management Capability. Each function may have only one item in its capability list with Capability ID set to 01h." line.long 0x4 "CON_STATUS_REG,Power Management Control and Status Register. This register is used to manage the PCI function's power management state as well as to enable/monitor PMEs." hexmask.long.byte 0x4 24.--31. 1. "DATA_REG_ADD_INFO,Data. This field is used to report the state dependent data requested by the Data_Select field. The value of this field is scaled by the value reported by the Data_Scale field." rbitfld.long 0x4 23. "BUS_PWR_CLK_CON_EN,Bus Power/Clock Control Enable. For a description of this standard PCIe register field see the PCI Express Base Specification." "0,1" rbitfld.long 0x4 22. "B2_B3_SUPPORT,B2B3 Support for D3hot. For a description of this standard PCIe register field see the PCI Express Base Specification." "0,1" hexmask.long.byte 0x4 16.--21. 1. "RSVDP_16,Reserved for future use." newline bitfld.long 0x4 15. "PME_STATUS,PME_Status. This bit is set when the function normally generates a PME signal. The value of this bit is not affected by the value of the PME_En bit. If PME_Support bit 31 of the Power Management Capabilities register is clear this bit is.." "0,1" rbitfld.long 0x4 13.--14. "DATA_SCALE,Data_Scale. This field indicates the scaling factor to be used when interpreting the value of the Data field. The value and meaning of this field varies depending on which data value has been selected by the Data_Select field. For more details.." "0,1,2,3" hexmask.long.byte 0x4 9.--12. 1. "DATA_SELECT,Data_Select. This 4-bit field is used to select which data is to be reported through the Data and Data_Scale field. If the Data field is not implemented this field must be hardwired to 0000b." bitfld.long 0x4 8. "PME_ENABLE,PME_En. - When set the function is permitted to generate a PME. - When clear the function is not permitted to generate a PME. If PME_Support is 1 xxxxb (PME generation from D3cold) or the function consumes Aux power and Aux power is.." "0,1" newline hexmask.long.byte 0x4 4.--7. 1. "RSVDP_4,Reserved for future use." bitfld.long 0x4 3. "NO_SOFT_RST,No_Soft_Reset. This bit indicates the state of the function after writing the PowerState field to transition the function from D3hot to D0. - When set this transition preserves internal function state. The function is in D0Active and no.." "0,1" rbitfld.long 0x4 2. "RSVDP_2,Reserved for future use." "0,1" bitfld.long 0x4 0.--1. "POWER_STATE,PowerState. This 2-bit field is used both to determine the current power state of a function and to set the function into a new power state. The definition of the field values is given below. You can write to this register; however the.." "D0,D1,D2,D3hot" tree.end tree "PF0_PCIE_CAP (PF PCI Express Capability Structure)" group.long (0x0+0x70)++0x33 line.long 0x0 "PCIE_CAP_ID_PCIE_NEXT_CAP_PTR_PCIE_CAP_REG,PCI Express Capabilities. ID. Next Pointer Register." rbitfld.long 0x0 31. "RSVDP_31,Reserved for future use." "0,1" rbitfld.long 0x0 30. "RSVD,Reserved." "0,1" newline hexmask.long.byte 0x0 25.--29. 1. "PCIE_INT_MSG_NUM,PCIE Interrupt Message Number. For a description of this standard PCIe register field see the PCI Express Base Specification. Interrupt Message Number. This field indicates which MSI/MSI-X vector is used for the interrupt message.." bitfld.long 0x0 24. "PCIE_SLOT_IMP,Slot Implemented. When set this bit indicates that the Link associated with this Port is connected to a slot (as compared to being connected to a system-integrated device or being disabled). This bit is valid for Downstream Ports. This bit.." "0,1" newline hexmask.long.byte 0x0 20.--23. 1. "PCIE_DEV_PORT_TYPE,Device/Port Type. Indicates the specific type of this PCI Express function. Note: Different functions in a Multi-Function Device can generally be of different types. Defined encodings for functions that implement a Type 00h PCI.." hexmask.long.byte 0x0 16.--19. 1. "PCIE_CAP_REG,Capability Version. Indicates PCI-SIG defined PCI Express Capability structure version number. A version of the specification that changes the PCI Express Capability structure in a way that is not otherwise identifiable (for example through.." newline hexmask.long.byte 0x0 8.--15. 1. "PCIE_CAP_NEXT_PTR,Next Capability Pointer. This field contains the offset to the next PCI Capability structure or 00h if no other items exist in the linked list of Capabilities. Note: The access attributes of this field are as follows: - Wire: No access." hexmask.long.byte 0x0 0.--7. 1. "PCIE_CAP_ID,Capability ID. Indicates the PCI Express Capability structure. This field must return a Capability ID of 10h indicating that this is a PCI Express Capability structure." line.long 0x4 "DEVICE_CAPABILITIES_REG,Device Capabilities Register. The Device Capabilities register identifies PCI Express device function specific capabilities." hexmask.long.word 0x4 16.--31. 1. "RSVDP_16,Reserved for future use." bitfld.long 0x4 15. "PCIE_CAP_ROLE_BASED_ERR_REPORT,Role-Based Error Reporting. When set this bit indicates that the function implements the functionality originally defined in the Error Reporting ECN for PCI Express Base Specification Revision 1.0a and later incorporated.." "0,1" newline hexmask.long.word 0x4 6.--14. 1. "RSVDP_6,Reserved for future use." bitfld.long 0x4 5. "PCIE_CAP_EXT_TAG_SUPP,Extended Tag Field Supported. This bit in combination with the 10-Bit Tag Requester Supported bit in the Device Capabilities 2 register indicates the maximum supported size of the Tag field as a Requester. This bit must be set if.." "0,1" newline bitfld.long 0x4 3.--4. "PCIE_CAP_PHANTOM_FUNC_SUPPORT,Phantom Functions Supported. This field indicates the support for use of unclaimed function numbers to extend the number of outstanding transactions allowed by logically combining unclaimed function numbers (called Phantom.." "0,1,2,3" bitfld.long 0x4 0.--2. "PCIE_CAP_MAX_PAYLOAD_SIZE,Max_Payload_Size Supported. This field indicates the maximum payload size that the function can support for TLPs. Defined encodings are: - 000b: 128 bytes max payload size - 001b: 256 bytes max payload size - 010b: 512 bytes max.." "0,1,2,3,4,5,6,7" line.long 0x8 "DEVICE_CONTROL_DEVICE_STATUS,Device Control and Device Status Register. This register controls PCI Express device specific parameters and provides information about PCI Express device (function) specific parameters." hexmask.long.word 0x8 22.--31. 1. "RSVDP_22,Reserved for future use." rbitfld.long 0x8 21. "PCIE_CAP_TRANS_PENDING,Transactions Pending. Endpoints: When set this bit indicates that the function has issued Non-Posted Requests that have not been completed. A Function reports this bit cleared only when all outstanding Non-Posted Requests have.." "0,1" newline rbitfld.long 0x8 20. "PCIE_CAP_AUX_POWER_DETECTED,AUX Power Detected. Functions that require Aux power report this bit as set if Aux power is detected by the function. This bit is derived by sampling the sys_aux_pwr_det input." "0,1" bitfld.long 0x8 19. "PCIE_CAP_UNSUPPORTED_REQ_DETECTED,Unsupported Request Detected. This bit indicates that the function received an Unsupported Request. Errors are logged in this register regardless of whether error reporting is enabled or not in the Device Control.." "0,1" newline bitfld.long 0x8 18. "PCIE_CAP_FATAL_ERR_DETECTED,Fatal Error Detected. This bit indicates status of Fatal errors detected. Errors are logged in this register regardless of whether error reporting is enabled or not in the Device Control register. For a Multi-Function device.." "0,1" bitfld.long 0x8 17. "PCIE_CAP_NON_FATAL_ERR_DETECTED,Non-Fatal Error Detected. This bit indicates status of Non-fatal errors detected. Errors are logged in this register regardless of whether error reporting is enabled or not in the Device Control register. For a.." "0,1" newline bitfld.long 0x8 16. "PCIE_CAP_CORR_ERR_DETECTED,Correctable Error Detected. This bit indicates status of correctable errors detected. Errors are logged in this register regardless of whether error reporting is enabled or not in the Device Control register. For a.." "0,1" bitfld.long 0x8 15. "PCIE_CAP_INITIATE_FLR,Initiate Function Level Reset (applicable to Endpoints with Function Level Reset Capability set to 1b). A write of 1b initiates Function Level Reset to the Function. The value read by software from this bit is always 0b." "0,1" newline bitfld.long 0x8 12.--14. "PCIE_CAP_MAX_READ_REQ_SIZE,Max_Read_Request_Size. This field sets the maximum Read Request size for the function as a Requester. The function must not generate Read Requests with a size exceeding the set value. Defined encodings for this field are: -.." "0,1,2,3,4,5,6,7" rbitfld.long 0x8 11. "PCIE_CAP_EN_NO_SNOOP,Enable No Snoop. If this bit is set the function is permitted to Set the No Snoop bit in the Requester Attributes of transactions it initiates that do not require hardware enforced cache coherency (see section 2.2.6.5 in PCI Express.." "0,1" newline bitfld.long 0x8 10. "PCIE_CAP_AUX_POWER_PM_EN,Aux Power PM Enable. This bit is derived by sampling the sys_aux_pwr_det input. When set this bit enables a function to draw Aux power independent of PME Aux power. Functions that require Aux power on legacy operating systems.." "0,1" rbitfld.long 0x8 9. "PCIE_CAP_PHANTOM_FUNC_EN,Phantom Functions Enable. This bit in combination with the 10-Bit Tag Requester Enable bit in the Device Control 2 register determines how many Tag field bits a Requester is permitted to use. When the 10-Bit Tag Requester.." "0,1" newline rbitfld.long 0x8 8. "PCIE_CAP_EXT_TAG_EN,Extended Tag Field Enable. This bit in combination with the 10-Bit Tag Requester Enable bit in the Device Control 2 register determines how many Tag field bits a Requester is permitted to use. When the 10-Bit Tag Requester Enable.." "0,1" bitfld.long 0x8 5.--7. "PCIE_CAP_MAX_PAYLOAD_SIZE_CS,Max_Payload_Size. This field sets maximum TLP payload size for the Function. As a Receiver the Function must handle TLPs as large as the set value. As a Transmitter the Function must not generate TLPs exceeding the set.." "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 4. "PCIE_CAP_EN_REL_ORDER,Enable Relaxed Ordering. If this bit is set the function is permitted to set the Relaxed Ordering bit in the Attributes field of transactions it initiates that do not require strong write ordering (for more details see section.." "0,1" bitfld.long 0x8 3. "PCIE_CAP_UNSUPPORT_REQ_REP_EN,Unsupported Request Reporting Enable. This bit in conjunction with other bits controls the signaling of Unsupported Request Errors by sending error Messages (for more details see section 6.2.5 and section 6.2.6 of PCI.." "0,1" newline bitfld.long 0x8 2. "PCIE_CAP_FATAL_ERR_REPORT_EN,Fatal Error Reporting Enable. This bit in conjunction with other bits controls sending ERR_FATAL Messages (for more details see section 6.2.5 and section 6.2.6 of of PCI Express Base Specification). For a Multi-Function.." "0,1" bitfld.long 0x8 1. "PCIE_CAP_NON_FATAL_ERR_REPORT_EN,Non-Fatal Error Reporting Enable. This bit in conjunction with other bits controls sending ERR_NONFATAL Messages (for more details see section 6.2.5 and Section 6.2.6 of PCI Express Base Specification). For a.." "0,1" newline bitfld.long 0x8 0. "PCIE_CAP_CORR_ERR_REPORT_EN,Correctable Error Reporting Enable. This bit in conjunction with other bits controls sending ERR_COR Messages (for more details see section 6.2.5 section 6.2.6 and section 6.2.10.2 of PCI Express Base Specification). For.." "0,1" line.long 0xC "LINK_CAPABILITIES_REG,Link Capabilities Register. The Link Capabilities register identifies PCI Express Link specific capabilities." hexmask.long.byte 0xC 24.--31. 1. "PCIE_CAP_PORT_NUM,Port Number. This field indicates the PCI Express Port number for the given PCI Express Link. Multi-Function Devices associated with an Upstream Port must report the same value in this field for all functions. Note: The access.." rbitfld.long 0xC 23. "RSVDP_23,Reserved for future use." "0,1" newline bitfld.long 0xC 22. "PCIE_CAP_ASPM_OPT_COMPLIANCE,ASPM Optionality Compliance. This bit must be set to 1b in all functions. Components implemented against certain earlier versions of this specification will have this bit set to 0b. Software is permitted to use the value of.." "0,1" bitfld.long 0xC 21. "PCIE_CAP_LINK_BW_NOT_CAP,Link Bandwidth Notification Capability. A value of 1b indicates support for the Link Bandwidth Notification status and interrupt mechanisms. This capability is required for all Root Ports and Switch Downstream Ports supporting.." "0,1" newline rbitfld.long 0xC 20. "PCIE_CAP_DLL_ACTIVE_REP_CAP,Data Link Layer Link Active Reporting Capable. For a Downstream Port the controller hardwires this bit to 1b if the component supports the optional capability of reporting the DL_Active state of the Data Link Control and.." "0,1" bitfld.long 0xC 19. "PCIE_CAP_SURPRISE_DOWN_ERR_REP_CAP,Surprise Down Error Reporting Capable. For a Downstream Port this bit must be set if the component supports the optional capability of detecting and reporting a Surprise Down error condition. For Upstream Ports and.." "0,1" newline rbitfld.long 0xC 18. "PCIE_CAP_CLOCK_POWER_MAN,Clock Power Management. For Upstream Ports a value of 1b in this bit indicates that the component tolerates the removal of any reference clock(s) via the 'clock request' (CLKREQ#) mechanism when the Link is in the L1 and L2/L3.." "0,1" bitfld.long 0xC 15.--17. "PCIE_CAP_L1_EXIT_LATENCY,L1 Exit Latency. This field indicates the L1 exit latency for the given PCI Express Link. The value reported indicates the length of time this Port requires to complete transition from ASPM L1 to L0. If ASPM L1 is not supported.." "0,1,2,3,4,5,6,7" newline bitfld.long 0xC 12.--14. "PCIE_CAP_L0S_EXIT_LATENCY,L0s Exit Latency. This field indicates the L0s exit latency for the given PCI Express Link. The value reported indicates the length of time this Port requires to complete transition from L0s to L0. If L0s is not supported the.." "0,1,2,3,4,5,6,7" bitfld.long 0xC 10.--11. "PCIE_CAP_ACTIVE_STATE_LINK_PM_SUPPORT,Active State Power Management (ASPM) Support. This field indicates the level of ASPM supported on the given PCI Express Link. For more details on ASPM support requirements see section 5.4.1 of PCI Express Base.." "0,1,2,3" newline hexmask.long.byte 0xC 4.--9. 1. "PCIE_CAP_MAX_LINK_WIDTH,Maximum Link Width. This field indicates the maximum Link width (xN - corresponding to N Lanes) implemented by the component. This value is permitted to exceed the number of Lanes routed to the slot (Downstream Port) adapter.." hexmask.long.byte 0xC 0.--3. 1. "PCIE_CAP_MAX_LINK_SPEED,Max Link Speed. This field indicates the maximum Link speed of the associated Port. The encoded value specifies a bit location in the Supported Link Speeds Vector (in the Link Capabilities 2 register) that corresponds to the.." line.long 0x10 "LINK_CONTROL_LINK_STATUS_REG,Link Control and Link Status Register. This register controls and provides information about PCI Express Link specific parameters." bitfld.long 0x10 31. "PCIE_CAP_LINK_AUTO_BW_STATUS,Link Autonomous Bandwidth Status. This bit is set by hardware to indicate that hardware has autonomously changed Link speed or width without the Port transitioning through DL_Down status for reasons other than to attempt to.." "0,1" bitfld.long 0x10 30. "PCIE_CAP_LINK_BW_MAN_STATUS,Link Bandwidth Management Status. This bit is set by hardware to indicate that either of the following has occurred without the Port transitioning through DL_Down status: - A Link retraining has completed following a write of.." "0,1" newline rbitfld.long 0x10 29. "PCIE_CAP_DLL_ACTIVE,Data Link Layer Link Active. This bit indicates the status of the Data Link Control and Management State Machine. It returns a 1b to indicate the DL_Active state 0b otherwise. This bit must be implemented if the Data Link Layer Link.." "0,1" bitfld.long 0x10 28. "PCIE_CAP_SLOT_CLK_CONFIG,Slot Clock Configuration. This bit indicates that the component uses the same physical reference clock that the platform provides on the connector. If the device uses an independent clock irrespective of the presence of a.." "0,1" newline rbitfld.long 0x10 27. "PCIE_CAP_LINK_TRAINING,Link Training. This read-only bit indicates that the Physical Layer LTSSM is in the Configuration or Recovery state or that 1b was written to the Retrain Link bit but Link training has not yet begun. Hardware clears this bit when.." "0,1" rbitfld.long 0x10 26. "RSVDP_26,Reserved for future use." "0,1" newline hexmask.long.byte 0x10 20.--25. 1. "PCIE_CAP_NEGO_LINK_WIDTH,Negotiated Link Width. This field indicates the negotiated width of the given PCI Express Link. Defined encodings are: -00 0001b: x1 -00 0010b: x2 -00 0100b: x4 -00 1000b: x8 -00 1100b: x12 -01 0000b: x16 -10 0000b: x32 All other.." hexmask.long.byte 0x10 16.--19. 1. "PCIE_CAP_LINK_SPEED,Current Link Speed. This field indicates the negotiated Link speed of the given PCI Express Link. The encoded value specifies a bit location in the Supported Link Speeds Vector (in the Link Capabilities 2 register) that corresponds to.." newline bitfld.long 0x10 14.--15. "PCIE_CAP_DRS_SIGNALING_CONTROL,DRS Signaling Control. Indicates the mechanism used to report reception of a DRS message. Must be implemented for Downstream Ports with the DRS Supported bit Set in the Link Capabilities 2 Register. Encodings are: - 00b:.." "0,1,2,3" rbitfld.long 0x10 12.--13. "RSVDP_12,Reserved for future use." "0,1,2,3" newline bitfld.long 0x10 11. "PCIE_CAP_LINK_AUTO_BW_INT_EN,Link Autonomous Bandwidth Management Interrupt Enable. When set this bit enables the generation of an interrupt to indicate that the Link Autonomous Bandwidth Status bit has been set. The write value is gated with the.." "0,1" bitfld.long 0x10 10. "PCIE_CAP_LINK_BW_MAN_INT_EN,Link Bandwidth Management Interrupt Enable. When set this bit enables the generation of an interrupt to indicate that the Link Bandwidth Management Status bit has been set. The write value is gated with the.." "0,1" newline bitfld.long 0x10 9. "PCIE_CAP_HW_AUTO_WIDTH_DISABLE,Hardware Autonomous Width Disable. When set this bit disables hardware from changing the Link width for reasons other than attempting to correct unreliable Link operation by reducing Link width. For a Multi-Function Device.." "0,1" bitfld.long 0x10 8. "PCIE_CAP_EN_CLK_POWER_MAN,Enable Clock Power Management. Applicable only for Upstream Ports and with form factors that support a 'Clock Request' (CLKREQ#) mechanism this bit operates as follows: - 0b: Clock power management is disabled and device must.." "0,1" newline bitfld.long 0x10 7. "PCIE_CAP_EXTENDED_SYNCH,Extended Synch. When set this bit forces the transmission of additional Ordered Sets when exiting the L0s state (see section 4.2.4.5 of PCI Express Base Specification) and when in the Recovery state (see section 4.2.6.4.1 of PCI.." "0,1" bitfld.long 0x10 6. "PCIE_CAP_COMMON_CLK_CONFIG,Common Clock Configuration. When set this bit indicates that this component and the component at the opposite end of this Link are operating with a distributed common reference clock. A value of 0b indicates that this.." "0,1" newline bitfld.long 0x10 5. "PCIE_CAP_RETRAIN_LINK,Retrain Link. A write of 1b to this bit initiates Link retraining by directing the Physical Layer LTSSM to the Recovery state. If the LTSSM is already in Recovery or Configuration re-entering Recovery is permitted but not required." "0,1" bitfld.long 0x10 4. "PCIE_CAP_LINK_DISABLE,Link Disable. This bit disables the Link by directing the LTSSM to the Disabled state when set; this bit is Reserved on Endpoints PCI Express to PCI/PCI-X bridges and Upstream Ports of Switches. Writes to this bit are immediately.." "0,1" newline bitfld.long 0x10 3. "PCIE_CAP_RCB,Read Completion Boundary (RCB). Root Ports: Indicates the RCB value for the Root Port. Refer to section 2.3.1.1 of PCI Express Base Specification for the definition of the parameter RCB. Defined encodings are: - 0b: 64 byte - 1b: 128 byte.." "0,1" rbitfld.long 0x10 2. "RSVDP_2,Reserved for future use." "0,1" newline bitfld.long 0x10 0.--1. "PCIE_CAP_ACTIVE_STATE_LINK_PM_CONTROL,Active State Power Management (ASPM) Control. This field controls the level of ASPM enabled on the given PCI Express Link. See section 5.4.1.3 of PCI Express Base Specification for requirements on when and how to.." "0,1,2,3" line.long 0x14 "SLOT_CAPABILITIES_REG,Slot Capabilities Register. The Slot Capabilities register identifies PCI Express slot specific capabilities." hexmask.long.word 0x14 19.--31. 1. "PCIE_CAP_PHY_SLOT_NUM,Physical Slot Number. This field indicates the physical slot number attached to this Port. This field must be hardware initialized to a value that assigns a slot number that is unique within the chassis regardless of the form.." bitfld.long 0x14 18. "PCIE_CAP_NO_CMD_CPL_SUPPORT,No Command Completed Support. When set this bit indicates that this slot does not generate software notification when an issued command is completed by the Hot-Plug Controller. This bit is only permitted to be set if the.." "0,1" newline bitfld.long 0x14 17. "PCIE_CAP_ELECTROMECH_INTERLOCK,Electromechanical Interlock Present. When set this bit indicates that an Electromechanical Interlock is implemented on the chassis for this slot. Note: The access attributes of this field are as follows: - Wire: No access." "0,1" bitfld.long 0x14 15.--16. "PCIE_CAP_SLOT_POWER_LIMIT_SCALE,Slot Power Limit Scale. Specifies the scale used for the Slot Power Limit Value (for more details see Section 6.9 of PCI Express Base Specification). Range of Values: - 00b: 1.0x - 01b: 0.1x - 10b: 0.01x - 11b: 0.001x.." "0,1,2,3" newline hexmask.long.byte 0x14 7.--14. 1. "PCIE_CAP_SLOT_POWER_LIMIT_VALUE,Slot Power Limit Value. In combination with the Slot Power Limit Scale value specifies the upper limit on power supplied by the slot (for more detais see Section 6.9 of PCI Express Base Specification) or by other means.." bitfld.long 0x14 6. "PCIE_CAP_HOT_PLUG_CAPABLE,Hot-Plug Capable. When set this bit indicates that this slot is capable of supporting hot-plug operations. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then R/W else R" "0,1" newline bitfld.long 0x14 5. "PCIE_CAP_HOT_PLUG_SURPRISE,Hot-Plug Surprise. When set this bit indicates that an adapter present in this slot might be removed from the system without any prior notification. This is a form factor specific capability. This bit is an indication to the.." "0,1" bitfld.long 0x14 4. "PCIE_CAP_POWER_INDICATOR,Power Indicator Present. When set this bit indicates that a Power Indicator is electrically controlled by the chassis for this slot. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if.." "0,1" newline bitfld.long 0x14 3. "PCIE_CAP_ATTENTION_INDICATOR,Attention Indicator Present. When set this bit indicates that an Attention Indicator is electrically controlled by the chassis. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if.." "0,1" bitfld.long 0x14 2. "PCIE_CAP_MRL_SENSOR,MRL Sensor Present. When set this bit indicates that an MRL Sensor is implemented on the chassis for this slot. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then R/W else R" "0,1" newline bitfld.long 0x14 1. "PCIE_CAP_POWER_CONTROLLER,Power Controller Present. When set this bit indicates that a software programmable Power Controller is implemented for this slot/adapter (depending on form factor). Note: The access attributes of this field are as follows: -.." "0,1" bitfld.long 0x14 0. "PCIE_CAP_ATTENTION_INDICATOR_BUTTON,Attention Button Present. When set this bit indicates that an Attention Button for this slot is electrically controlled by the chassis. Note: The access attributes of this field are as follows: - Wire: No access. -.." "0,1" line.long 0x18 "SLOT_CONTROL_SLOT_STATUS,Slot Control and Status Register. This register controls and provides information about PCI Express Slot specific parameters." hexmask.long.byte 0x18 25.--31. 1. "RSVDP_25,Reserved for future use." bitfld.long 0x18 24. "PCIE_CAP_DLL_STATE_CHANGED,Data Link Layer State Changed. This bit is set when the value reported in the Data Link Layer Link Active bit of the Link Status register is changed. In response to a Data Link Layer State Changed event software must read the.." "0,1" newline rbitfld.long 0x18 23. "PCIE_CAP_ELECTROMECH_INTERLOCK_STATUS,Electromechanical Interlock Status. If an Electromechanical Interlock is implemented this bit indicates the status of the Electromechanical Interlock. Defined encodings are: - 0b: Electromechanical Interlock.." "0,1" rbitfld.long 0x18 22. "PCIE_CAP_PRESENCE_DETECT_STATE,Presence Detect State. This bit indicates the presence of an adapter in the slot reflected by the logical 'OR' of the Physical Layer in-band presence detect mechanism and if present any out-of-band presence detect.." "0,1" newline rbitfld.long 0x18 21. "PCIE_CAP_MRL_SENSOR_STATE,MRL Sensor State. This bit reports the status of the MRL sensor if implemented. Defined encodings are: - 0b: MRL Closed - 1b: MRL Open" "0,1" bitfld.long 0x18 20. "PCIE_CAP_CMD_CPLD,Command Completed. If Command Completed notification is supported (if the No Command Completed Support bit in the Slot Capabilities register is 0b) this bit is set when a hot-plug command has completed and the Hot-Plug Controller is.." "0,1" newline bitfld.long 0x18 19. "PCIE_CAP_PRESENCE_DETECTED_CHANGED,Presence Detect Changed. This bit is set when the value reported in the Presence Detect State bit is changed." "0,1" bitfld.long 0x18 18. "PCIE_CAP_MRL_SENSOR_CHANGED,MRL Sensor Changed. If an MRL sensor is implemented this bit is set when a MRL Sensor state change is detected. If an MRL sensor is not implemented this bit must not be set." "0,1" newline bitfld.long 0x18 17. "PCIE_CAP_POWER_FAULT_DETECTED,Power Fault Detected. If a Power Controller that supports power fault detection is implemented this bit issSet when the Power Controller detects a power fault at this slot. Note: Depending on hardware capability it is.." "0,1" bitfld.long 0x18 16. "PCIE_CAP_ATTENTION_BUTTON_PRESSED,Attention Button Pressed. If an Attention Button is implemented this bit is set when the attention button is pressed. If an Attention Button is not supported this bit must not be set." "0,1" newline rbitfld.long 0x18 14.--15. "RSVDP_14,Reserved for future use." "0,1,2,3" bitfld.long 0x18 12. "PCIE_CAP_DLL_STATE_CHANGED_EN,Data Link Layer State Changed Enable. If the Data Link Layer Link Active Reporting capability is 1b this bit enables software notification when Data Link Layer Link Active bit is changed. If the Data Link Layer Link Active.." "0,1" newline bitfld.long 0x18 11. "PCIE_CAP_ELECTROMECH_INTERLOCK_CTRL,Electromechanical Interlock Control. If an Electromechanical Interlock is implemented a write of 1b to this bit causes the state of the interlock to toggle. A write of 0b to this bit has no effect. A read of this bit.." "0,1" bitfld.long 0x18 10. "PCIE_CAP_POWER_CONTROLLER_CTRL,Power Controller Control. If a Power Controller is implemented this bit when written sets the power state of the slot per the defined encodings. Reads of this bit must reflect the value from the latest write even if the.." "0,1" newline bitfld.long 0x18 8.--9. "PCIE_CAP_POWER_INDICATOR_CTRL,Power Indicator Control. If a Power Indicator is implemented writes to this field set the Power Indicator to the written state. Reads of this field must reflect the value from the latest write even if the corresponding.." "0,1,2,3" bitfld.long 0x18 6.--7. "PCIE_CAP_ATTENTION_INDICATOR_CTRL,Attention Indicator Control. If an Attention Indicator is implemented writes to this field set the Attention Indicator to the written state. Reads of this field must reflect the value from the latest write even if the.." "0,1,2,3" newline bitfld.long 0x18 5. "PCIE_CAP_HOT_PLUG_INT_EN,Hot-Plug Interrupt Enable. When set this bit enables generation of an interrupt on enabled hot-plug events. If the Hot Plug Capable bit in the Slot Capabilities register is clear this bit is permitted to be read-only with a.." "0,1" bitfld.long 0x18 4. "PCIE_CAP_CMD_CPL_INT_EN,Command Completed Interrupt Enable. If Command Completed notification is supported (if the No Command Completed Support bit in the Slot Capabilities register is 0b) when set this bit enables software notification when a hot-plug.." "0,1" newline bitfld.long 0x18 3. "PCIE_CAP_PRESENCE_DETECT_CHANGE_EN,Presence Detect Changed Enable. When set this bit enables software notification on a presence detect changed event (for more details see Section 6.7.3 of PCI Express Base Specification). If the Hot-Plug Capable bit in.." "0,1" bitfld.long 0x18 2. "PCIE_CAP_MRL_SENSOR_CHANGED_EN,MRL Sensor Changed Enable. When set this bit enables software notification on a MRL sensor changed event (for more details see Section 6.7.3 of PCI Express Base Specification). If the MRL Sensor Present bit in the Slot.." "0,1" newline bitfld.long 0x18 1. "PCIE_CAP_POWER_FAULT_DETECTED_EN,Power Fault Detected Enable. When set this bit enables software notification on a power fault event (for more details see Section 6.7.3 of PCI Express Base Specification). If a Power Controller that supports power fault.." "0,1" bitfld.long 0x18 0. "PCIE_CAP_ATTENTION_BUTTON_PRESSED_EN,Attention Button Pressed Enable. When set to 1b this bit enables software notification on an attention button pressed event (for more details see Section 6.7.3 of PCI Express Base Specification). If the Attention.." "0,1" line.long 0x1C "ROOT_CONTROL_ROOT_CAPABILITIES_REG,Root Control and Capabilities Register. This register controls PCI Express Root Complex specific parameters and identifies PCI Express Root Port specific capabilities." hexmask.long.word 0x1C 17.--31. 1. "RSVDP_17,Reserved for future use." bitfld.long 0x1C 16. "PCIE_CAP_CRS_SW_VISIBILITY,CRS Software Visibility Capable. For a description of this standard PCIe register field see the PCI Express Base Specification. CRS Software Visibility. When set this bit indicates that the Root Port is capable of returning.." "0,1" newline hexmask.long.word 0x1C 5.--15. 1. "RSVDP_5,Reserved for future use." bitfld.long 0x1C 4. "PCIE_CAP_CRS_SW_VISIBILITY_EN,CRS Software Visibility Enable. When set this bit enables the Root Port to return Configuration Request Retry Status (CRS) Completion Status to software (for more details see section 2.3.1 of PCI Express Base.." "0,1" newline bitfld.long 0x1C 3. "PCIE_CAP_PME_INT_EN,PME Interrupt Enable. When set this bit enables PME interrupt generation upon receipt of a PME Message as reflected in the PME Status bit (for more details see Table 7-29 of PCI Express Base Specification). A PME interrupt is also.." "0,1" bitfld.long 0x1C 2. "PCIE_CAP_SYS_ERR_ON_FATAL_ERR_EN,System Error on Fatal Error Enable. If set this bit indicates that a System Error should be generated if a Fatal error (ERR_FATAL) is reported by any of the devices in the Hierarchy Domain associated with this Root Port.." "0,1" newline bitfld.long 0x1C 1. "PCIE_CAP_SYS_ERR_ON_NON_FATAL_ERR_EN,System Error on Non-Fatal Error Enable. If set this bit indicates that a System Error should be generated if a Non-fatal error (ERR_NONFATAL) is reported by any of the devices in the Hierarchy Domain associated with.." "0,1" bitfld.long 0x1C 0. "PCIE_CAP_SYS_ERR_ON_CORR_ERR_EN,System Error on Correctable Error Enable. If set this bit indicates that a System Error should be generated if a correctable error (ERR_COR) is reported by any of the devices in the Hierarchy Domain associated with this.." "0,1" line.long 0x20 "ROOT_STATUS_REG,Root Status Register. The Root Status register provides information about PCI Express device specific parameters." hexmask.long.word 0x20 18.--31. 1. "RSVDP_18,Reserved for future use." rbitfld.long 0x20 17. "PCIE_CAP_PME_PENDING,PME Pending. This bit indicates that another PME is pending when the PME Status bit is s et. When the PME Status bit is cleared by software; the PME is delivered by hardware by setting the PME Status bit again and updating the PME.." "0,1" newline bitfld.long 0x20 16. "PCIE_CAP_PME_STATUS,PME Status. This bit indicates that PME was asserted by the PME Requester indicated in the PME Requester ID field. Subsequent PMEs are kept pending until the status register is cleared by software by writing a 1b." "0,1" hexmask.long.word 0x20 0.--15. 1. "PCIE_CAP_PME_REQ_ID,PME Requester ID. This field indicates the PCI Requester ID of the last PME Requester. This field is only valid when the PME Status bit is set." line.long 0x24 "DEVICE_CAPABILITIES2_REG,Device Capabilities 2 Register." bitfld.long 0x24 31. "PCIE_CAP_FRS_SUPPORTED,FRS Supported. When set indicates support for the optional Function Readiness Status (FRS) capability. Must be set for all Functions that support generation or reception capabilities of FRS Messages. Must not be set by Switch.." "0,1" hexmask.long.byte 0x24 24.--30. 1. "RSVDP_24,Reserved for future use." newline bitfld.long 0x24 22.--23. "PCIE_CAP2_CFG_MAX_END2END_TLP_PRFXS,Max End-End TLP Prefixes. Indicates the maximum number of End-End TLP Prefixes supported by this Function. For more details see Section 2.2.10.2 of PCI Express Base Specification. Values are: - 01b: 1 End-End TLP.." "0,1,2,3" bitfld.long 0x24 21. "PCIE_CAP2_CFG_END2END_TLP_PRFX_SUPPORT,End-End TLP Prefix Supported. Indicates whether End-End TLP Prefix support is offered by a Function. Values are: - 0b: No Support - 1b: Support is provided to receive TLPs containing End-End TLP Prefixes. All Ports.." "0,1" newline bitfld.long 0x24 20. "PCIE_CAP2_CFG_EXTND_FMT_SUPPORT,Extended Fmt Field Supported. If set the Function supports the 3-bit definition of the Fmt field. If clear the Function supports a 2-bit definition of the Fmt field. For more details see section 2.2 of PCI Express Base.." "0,1" rbitfld.long 0x24 17. "PCIE_CAP2_10_BIT_TAG_REQ_SUPPORT,10-Bit Tag Requester Supported. If this bit is set the Function supports 10-Bit Tag Requester capability; otherwise the Function does not. This bit must not be set if the 10-Bit Tag Completer Supported bit is clear." "0,1" newline rbitfld.long 0x24 16. "PCIE_CAP2_10_BIT_TAG_COMP_SUPPORT,10-Bit Tag Completer Supported. If this bit is set the Function supports 10-Bit Tag Completer capability; otherwise the Function does not. For more details see section 2.2.6.2. of PCI Express Base Specification." "0,1" rbitfld.long 0x24 13. "PCIE_CAP_TPH_CMPLT_SUPPORT_1,TPH Completer Supported Bit 1." "0,1" newline rbitfld.long 0x24 12. "PCIE_CAP_TPH_CMPLT_SUPPORT_0,TPH Completer Supported Bit 0. Value of this bit along with TPH Completer Supported Bit 1 indicates Completer support for TPH or Extended TPH. Applicable only to Root Ports and Endpoints. For all other Functions this field.." "0,1" bitfld.long 0x24 11. "PCIE_CAP_LTR_SUPP,LTR Mechanism Supported. A value of 1b indicates support for the optional Latency Tolerance Reporting (LTR) mechanism. Root Ports Switches and Endpoints are permitted to implement this capability. For a Multi-Function Device associated.." "0,1" newline rbitfld.long 0x24 10. "PCIE_CAP_NO_RO_EN_PR2PR_PAR,No RO-enabled PR-PR Passing. If this bit is set the routing element never carries out the passing permitted by Table 2-39 of PCI Express Base Specification entry A2b that is associated with the Relaxed Ordering Attribute.." "0,1" rbitfld.long 0x24 9. "PCIE_CAP_128_CAS_CPL_SUPP,128-bit CAS Completer Supported. Applicable to Functions with Memory Space BARs as well as all Root Ports; must be 0b otherwise. This bit must be set to 1b if the Function supports this optional capability. For more details see.." "0,1" newline rbitfld.long 0x24 8. "PCIE_CAP_64_ATOMIC_CPL_SUPP,64-bit AtomicOp Completer Supported. Applicable to Functions with Memory Space BARs as well as all Root Ports; must be 0b otherwise. Includes FetchAdd Swap and CAS AtomicOps. This bit must be set to 1b if the Function.." "0,1" rbitfld.long 0x24 7. "PCIE_CAP_32_ATOMIC_CPL_SUPP,32-bit AtomicOp Completer Supported. Applicable to Functions with Memory Space BARs as well as all Root Ports; must be 0b otherwise. Includes FetchAdd Swap and CAS AtomicOps. This bit must be set to 1b if the Function.." "0,1" newline rbitfld.long 0x24 6. "PCIE_CAP_ATOMIC_ROUTING_SUPP,AtomicOp Routing Supported. Applicable only to Switch Upstream Ports Switch Downstream Ports and Root Ports; must be 0b for other Function types. This bit must be set to 1b if the Port supports this optional capability. For.." "0,1" rbitfld.long 0x24 5. "PCIE_CAP_ARI_FORWARD_SUPPORT,ARI Forwarding Supported. Applicable only to Switch Downstream Ports and Root Ports; must be 0b for other Function types. This bit must be set to 1b if a Switch Downstream Port or Root Port supports this optional capability." "0,1" newline rbitfld.long 0x24 4. "PCIE_CAP_CPL_TIMEOUT_DISABLE_SUPPORT,Completion Timeout Disable Supported. A value of 1b indicates support for the Completion Timeout Disable mechanism. The Completion Timeout Disable mechanism is required for Endpoints that issue Requests on their own.." "0,1" hexmask.long.byte 0x24 0.--3. 1. "PCIE_CAP_CPL_TIMEOUT_RANGE,Completion Timeout Ranges Supported. This field indicates device Function support for the optional Completion Timeout programmability mechanism. This mechanism allows system software to modify the Completion Timeout value. This.." line.long 0x28 "DEVICE_CONTROL2_DEVICE_STATUS2_REG,Device Control 2 and Status 2 Register." hexmask.long.word 0x28 16.--31. 1. "RSVDP_16,Reserved for future use." bitfld.long 0x28 15. "PCIE_CTRL2_CFG_END2END_TLP_PFX_BLCK,End-End TLP Prefix Blocking. Controls whether the routing function is permitted to forward TLPs containing an End-End TLP Prefix. Values are: - 0b: Forwarding Enabled - Function is permitted to send TLPs with End-End.." "0,1" newline rbitfld.long 0x28 11. "RSVDP_11,Reserved for future use." "0,1" bitfld.long 0x28 10. "PCIE_CAP_LTR_EN,LTR Mechanism Enable. When set to 1b this bit enables Upstream Ports to send LTR messages and Downstream Ports to process LTR Messages. For a Multi-Function Device associated with an Upstream Port of a device that implements LTR the bit.." "0,1" newline rbitfld.long 0x28 5. "PCIE_CAP_ARI_FORWARD_SUPPORT_CS,ARI Forwarding Enable. When set the Downstream Port disables its traditional Device Number field being 0 enforcement when turning a Type 1 Configuration Request into a Type 0 Configuration Request permitting access to.." "0,1" bitfld.long 0x28 4. "PCIE_CAP_CPL_TIMEOUT_DISABLE,Completion Timeout Disable. When set this bit disables the Completion Timeout mechanism. This bit is required for all Functions that support the Completion Timeout Disable Capability. Functions that do not support this.." "0,1" newline hexmask.long.byte 0x28 0.--3. 1. "PCIE_CAP_CPL_TIMEOUT_VALUE,Completion Timeout Value. In device Functions that support Completion Timeout programmability this field allows system software to modify the Completion Timeout value. This field is applicable to Root Ports Endpoints that.." line.long 0x2C "LINK_CAPABILITIES2_REG,Link Capabilities 2 Register." bitfld.long 0x2C 31. "DRS_SUPPORTED,DRS Supported. When set indicates support for the optional Device Readiness Status (DRS) capability. Must be Set in Downstream Ports that support DRS. Must be Set in Downstream Ports that support FRS. For Upstream Ports that support DRS.." "0,1" hexmask.long.byte 0x2C 25.--30. 1. "RSVDP_25,Reserved for future use." newline hexmask.long.word 0x2C 9.--22. 1. "RSVDP_9,Reserved for future use." rbitfld.long 0x2C 8. "PCIE_CAP_CROSS_LINK_SUPPORT,Crosslink Supported. When set to 1b this bit indicates that the associated Port supports crosslinks (for more details see section 4.2.6.3.1 of PCI Express Base Specification). When set to 0b on a Port that supports Link.." "0,1" newline hexmask.long.byte 0x2C 1.--7. 1. "PCIE_CAP_SUPPORT_LINK_SPEED_VECTOR,Supported Link Speeds Vector. This field indicates the supported Link speed(s) of the associated Port. For each bit a value of 1b indicates that the corresponding Link speed is supported; otherwise the Link speed is.." rbitfld.long 0x2C 0. "RSVDP_0,Reserved for future use." "0,1" line.long 0x30 "LINK_CONTROL2_LINK_STATUS2_REG,Link Control 2 and Status 2 Register." bitfld.long 0x30 31. "DRS_MESSAGE_RECEIVED,DRS Message Received. This bit must be set whenever the Port receives a DRS Message. This bit must be cleared in DL_Down. This bit must be implemented in any Downstream Port where the DRS Supported bit is Set in the Link Capabilities.." "0,1" rbitfld.long 0x30 28.--30. "DOWNSTREAM_COMPO_PRESENCE,Downstream Component Presence. This field indicates the presence and DRS status for the Downstream Component if any connected to the Link; defined values are: - 000b: Link Down - Presence Not Determined - 001b: Link Down -.." "0,1,2,3,4,5,6,7" newline rbitfld.long 0x30 26.--27. "RSVDP_26,Reserved for future use." "0,1,2,3" bitfld.long 0x30 21. "PCIE_CAP_LINK_EQ_REQ,Link Equalization Request 8.0 GT/s. This bit is set by hardware to request the 8.0 GT/s Link equalization process to be performed on the Link. For more details see sections 4.2.3 and 4.2.6.4.2 of PCI Express Base Specification. For.." "0,1" newline rbitfld.long 0x30 20. "PCIE_CAP_EQ_CPL_P3,EEqualization 8.0 GT/s Phase 3 Successful. When set to 1b this bit indicates that Phase 3 of the 8.0 GT/s Transmitter Equalization procedure has successfully completed. Details of the Transmitter Equalization process and when this bit.." "0,1" rbitfld.long 0x30 19. "PCIE_CAP_EQ_CPL_P2,Equalization 8.0 GT/s Phase 2 Successful. When set to 1b this bit indicates that Phase 2 of the 8.0 GT/s Transmitter Equalization procedure has successfully completed. Details of the Transmitter Equalization process and when this bit.." "0,1" newline rbitfld.long 0x30 18. "PCIE_CAP_EQ_CPL_P1,Equalization 8.0 GT/s Phase 1 Successful. When set to 1b this bit indicates that Phase 1 of the 8.0 GT/s Transmitter Equalization procedure has successfully completed. Details of the Transmitter Equalization process and when this bit.." "0,1" rbitfld.long 0x30 17. "PCIE_CAP_EQ_CPL,Equalization 8.0 GT/s Complete. When set to 1b this bit indicates that the Transmitter Equalization procedure at the 8.0 GT/s data rate has completed. Details of the Transmitter Equalization process and when this bit needs to be set to.." "0,1" newline rbitfld.long 0x30 16. "PCIE_CAP_CURR_DEEMPHASIS,Current De-emphasis Level. When the Link is operating at 5.0 GT/s speed this bit reflects the level of de-emphasis. Encodings: - 1b: -3.5 dB - 0b: -6 dB The value in this bit is undefined when the Link is not operating at 5.0.." "0,1" hexmask.long.byte 0x30 12.--15. 1. "PCIE_CAP_COMPLIANCE_PRESET,Compliance Preset/De-emphasis. For 8.0 GT/s and higher Data Rate: This field sets the Transmitter Preset in Polling.Compliance state if the entry occurred due to the Enter Compliance bit being 1b. The encodings are defined in.." newline bitfld.long 0x30 11. "PCIE_CAP_COMPLIANCE_SOS,Compliance SOS. When set to 1b the LTSSM is required to send SKP Ordered Sets between sequences when sending the Compliance Pattern or Modified Compliance Pattern. For a Multi-Function Device associated with an Upstream Port the.." "0,1" bitfld.long 0x30 10. "PCIE_CAP_ENTER_MODIFIED_COMPLIANCE,Enter Modified Compliance. When this bit is set to 1b the device transmits Modified Compliance Pattern if the LTSSM enters Polling.Compliance substate. Components that support only the 2.5 GT/s speed are permitted to.." "0,1" newline bitfld.long 0x30 7.--9. "PCIE_CAP_TX_MARGIN,Transmit Margin - This field controls the value of the non-deemphasized voltage level at the Transmitter pins. This field is reset to 000b on entry to the LTSSM Polling.Configuration substate (see Chapter 4 of PCI Express Base.." "0,1,2,3,4,5,6,7" bitfld.long 0x30 6. "PCIE_CAP_SEL_DEEMPHASIS,Selectable De-emphasis. When the Link is operating at 5.0 GT/s speed this bit is used to control the transmit de-emphasis of the link in specific situations. For more details see section 4.2.6 of PCI Express Base Specification." "0,1" newline bitfld.long 0x30 5. "PCIE_CAP_HW_AUTO_SPEED_DISABLE,Hardware Autonomous Speed Disable. When set this bit disables hardware from changing the Link speed for device-specific reasons other than attempting to correct unreliable Link operation by reducing Link speed. Initial.." "0,1" bitfld.long 0x30 4. "PCIE_CAP_ENTER_COMPLIANCE,Enter Compliance. Software is permitted to force a Link to enter Compliance mode (at the speed indicated in the Target Link Speed field and the de-emphasis/preset level indicated by the Compliance Preset/De-emphasis field) by.." "0,1" newline hexmask.long.byte 0x30 0.--3. 1. "PCIE_CAP_TARGET_LINK_SPEED,Target Link Speed. For Downstream Ports this field sets an upper limit on Link operational speed by restricting the values advertised by the Upstream component in its training sequences. The encoded value specifies a bit.." tree.end tree "PF0_AER_CAP (PF Advanced Error Reporting Capability Structure)" group.long (0x0+0x100)++0x1B line.long 0x0 "AER_EXT_CAP_HDR_OFF,Advanced Error Reporting Extended Capability Header. For a description of this standard PCIe register. see the PCI Express Specification." hexmask.long.word 0x0 20.--31. 1. "NEXT_OFFSET,Next Capability Offset. For a description of this standard PCIe register field see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky).." hexmask.long.byte 0x0 16.--19. 1. "CAP_VERSION,Capability Version. For a description of this standard PCIe register field see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else.." hexmask.long.word 0x0 0.--15. 1. "CAP_ID,AER Extended Capability ID. For a description of this standard PCIe register field see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else.." line.long 0x4 "UNCORR_ERR_STATUS_OFF,Uncorrectable Error Status Register. For a description of this standard PCIe register. see the PCI Express Specification." hexmask.long.byte 0x4 27.--31. 1. "RSVDP_27,Reserved for future use." bitfld.long 0x4 25. "TLP_PRFX_BLOCKED_ERR_STATUS,TLP Prefix Blocked Error Status. For a description of this standard PCIe register field see the PCI Express Specification. Note: Not supported." "0,1" rbitfld.long 0x4 23. "RSVDP_23,Reserved for future use." "0,1" newline bitfld.long 0x4 22. "INTERNAL_ERR_STATUS,Uncorrectable Internal Error Status. For a description of this standard PCIe register field see the PCI Express Specification. The controller sets this bit when your application asserts app_err_bus[9]. It does not set this bit when.." "0,1" bitfld.long 0x4 20. "UNSUPPORTED_REQ_ERR_STATUS,Unsupported Request Error Status. For a description of this standard PCIe register field see the PCI Express Specification." "0,1" bitfld.long 0x4 19. "ECRC_ERR_STATUS,ECRC Error Status. For a description of this standard PCIe register field see the PCI Express Specification. Note:If CX_ECRC_ENABLE=0 the register field always reads 0." "0,1" newline bitfld.long 0x4 18. "MALF_TLP_ERR_STATUS,Malformed TLP Status. For a description of this standard PCIe register field see the PCI Express Specification." "0,1" bitfld.long 0x4 17. "REC_OVERFLOW_ERR_STATUS,Receiver Overflow Status. For a description of this standard PCIe register field see the PCI Express Specification." "0,1" bitfld.long 0x4 16. "UNEXP_CMPLT_ERR_STATUS,Unexpected Completion Status. For a description of this standard PCIe register field see the PCI Express Specification." "0,1" newline bitfld.long 0x4 15. "CMPLT_ABORT_ERR_STATUS,Completer Abort Status. For a description of this standard PCIe register field see the PCI Express Specification." "0,1" bitfld.long 0x4 14. "CMPLT_TIMEOUT_ERR_STATUS,Completion Timeout Status. For a description of this standard PCIe register field see the PCI Express Specification." "0,1" bitfld.long 0x4 13. "FC_PROTOCOL_ERR_STATUS,Flow Control Protocol Error Status. For a description of this standard PCIe register field see the PCI Express Specification." "0,1" newline bitfld.long 0x4 12. "POIS_TLP_ERR_STATUS,Poisoned TLP Status. For a description of this standard PCIe register field see the PCI Express Specification." "0,1" hexmask.long.byte 0x4 6.--11. 1. "RSVDP_6,Reserved for future use." bitfld.long 0x4 5. "SURPRISE_DOWN_ERR_STATUS,Surprise Down Error Status (Optional). For a description of this standard PCIe register field see the PCI Express Specification." "0,1" newline bitfld.long 0x4 4. "DL_PROTOCOL_ERR_STATUS,Data Link Protocol Error Status. For a description of this standard PCIe register field see the PCI Express Specification." "0,1" hexmask.long.byte 0x4 0.--3. 1. "RSVDP_0,Reserved for future use." line.long 0x8 "UNCORR_ERR_MASK_OFF,Uncorrectable Error Mask Register. For a description of this standard PCIe register. see the PCI Express Specification." hexmask.long.byte 0x8 27.--31. 1. "RSVDP_27,Reserved for future use." bitfld.long 0x8 25. "TLP_PRFX_BLOCKED_ERR_MASK,TLP Prefix Blocked Error Mask. For a description of this standard PCIe register field see the PCI Express Specification. Note: Not supported. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi:.." "0,1" rbitfld.long 0x8 23. "RSVDP_23,Reserved for future use." "0,1" newline bitfld.long 0x8 22. "INTERNAL_ERR_MASK,Uncorrectable Internal Error Mask (Optional). For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." "0,1" rbitfld.long 0x8 21. "ACS_VIOLATION_MASK,ACS Violation Mask. Setting the ACS Violation Mask bit disables error logging and signaling for ACS Violation errors. The bit is Read-Only Zero for upstream ports when ACS P2P Egress Control Enable is not set. For a description of.." "0,1" bitfld.long 0x8 20. "UNSUPPORTED_REQ_ERR_MASK,Unsupported Request Error Mask. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." "0,1" newline bitfld.long 0x8 19. "ECRC_ERR_MASK,ECRC Error Mask (Optional). For a description of this standard PCIe register field see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W (sticky) Note: This register.." "0,1" bitfld.long 0x8 18. "MALF_TLP_ERR_MASK,Malformed TLP Mask. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." "0,1" bitfld.long 0x8 17. "REC_OVERFLOW_ERR_MASK,Receiver Overflow Mask (Optional). For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." "0,1" newline bitfld.long 0x8 16. "UNEXP_CMPLT_ERR_MASK,Unexpected Completion Mask. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." "0,1" bitfld.long 0x8 15. "CMPLT_ABORT_ERR_MASK,Completer Abort Error Mask (Optional). For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." "0,1" bitfld.long 0x8 14. "CMPLT_TIMEOUT_ERR_MASK,Completion Timeout Error Mask. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." "0,1" newline bitfld.long 0x8 13. "FC_PROTOCOL_ERR_MASK,Flow Control Protocol Error Mask. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." "0,1" bitfld.long 0x8 12. "POIS_TLP_ERR_MASK,Poisoned TLP Error Mask. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." "0,1" hexmask.long.byte 0x8 6.--11. 1. "RSVDP_6,Reserved for future use." newline rbitfld.long 0x8 5. "SURPRISE_DOWN_ERR_MASK,Surprise Down Error Mask. For a description of this standard PCIe register field see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi:.." "0,1" bitfld.long 0x8 4. "DL_PROTOCOL_ERR_MASK,Data Link Protocol Error Mask. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." "0,1" hexmask.long.byte 0x8 0.--3. 1. "RSVDP_0,Reserved for future use." line.long 0xC "UNCORR_ERR_SEV_OFF,Uncorrectable Error Severity Register. For a description of this standard PCIe register. see the PCI Express Specification." hexmask.long.byte 0xC 27.--31. 1. "RSVDP_27,Reserved for future use." bitfld.long 0xC 25. "TLP_PRFX_BLOCKED_ERR_SEVERITY,TLP Prefix Blocked Error Severity (Optional). For a description of this standard PCIe register field see the PCI Express Specification. Note: Not supported. Note: The access attributes of this field are as follows: - Wire:.." "0,1" rbitfld.long 0xC 24. "ATOMIC_EGRESS_BLOCKED_ERR_SEVERITY,AtomicOp Egress Blocked Severity (Optional). For a description of this standard PCIe register field see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi:.." "0,1" newline rbitfld.long 0xC 23. "RSVDP_23,Reserved for future use." "0,1" bitfld.long 0xC 22. "INTERNAL_ERR_SEVERITY,Uncorrectable Internal Error Severity (Optional). For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." "0,1" bitfld.long 0xC 20. "UNSUPPORTED_REQ_ERR_SEVERITY,Unsupported Request Error Severity. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." "0,1" newline bitfld.long 0xC 19. "ECRC_ERR_SEVERITY,ECRC Error Severity (Optional). For a description of this standard PCIe register field see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W (sticky) Note: This.." "0,1" bitfld.long 0xC 18. "MALF_TLP_ERR_SEVERITY,Malformed TLP Severity. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." "0,1" bitfld.long 0xC 17. "REC_OVERFLOW_ERR_SEVERITY,Receiver Overflow Error Severity (Optional). For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." "0,1" newline bitfld.long 0xC 16. "UNEXP_CMPLT_ERR_SEVERITY,Unexpected Completion Error Severity. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." "0,1" bitfld.long 0xC 15. "CMPLT_ABORT_ERR_SEVERITY,Completer Abort Error Severity (Optional). For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." "0,1" bitfld.long 0xC 14. "CMPLT_TIMEOUT_ERR_SEVERITY,Completion Timeout Error Severity. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." "0,1" newline bitfld.long 0xC 13. "FC_PROTOCOL_ERR_SEVERITY,Flow Control Protocol Error Severity (Optional). For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." "0,1" bitfld.long 0xC 12. "POIS_TLP_ERR_SEVERITY,Poisoned TLP Severity. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." "0,1" hexmask.long.byte 0xC 6.--11. 1. "RSVDP_6,Reserved for future use." newline rbitfld.long 0xC 5. "SURPRISE_DOWN_ERR_SVRITY,Surprise Down Error Severity (Optional). For a description of this standard PCIe register field see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi:.." "0,1" bitfld.long 0xC 4. "DL_PROTOCOL_ERR_SEVERITY,Data Link Protocol Error Severity. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." "0,1" hexmask.long.byte 0xC 0.--3. 1. "RSVDP_0,Reserved for future use." line.long 0x10 "CORR_ERR_STATUS_OFF,Correctable Error Status Register. For a description of this standard PCIe register. see the PCI Express Specification." hexmask.long.word 0x10 16.--31. 1. "RSVDP_16,Reserved for future use." bitfld.long 0x10 15. "HEADER_LOG_OVERFLOW_STATUS,Header Log Overflow Error Status (Optional). For a description of this standard PCIe register field see the PCI Express Specification." "0,1" bitfld.long 0x10 14. "CORRECTED_INT_ERR_STATUS,Corrected Internal Error Status (Optional). For a description of this standard PCIe register field see the PCI Express Specification." "0,1" newline bitfld.long 0x10 13. "ADVISORY_NON_FATAL_ERR_STATUS,Advisory Non-Fatal Error Status. For a description of this standard PCIe register field see the PCI Express Specification." "0,1" bitfld.long 0x10 12. "RPL_TIMER_TIMEOUT_STATUS,Replay Timer Timeout Status. For a description of this standard PCIe register field see the PCI Express Specification." "0,1" rbitfld.long 0x10 9.--11. "RSVDP_9,Reserved for future use." "0,1,2,3,4,5,6,7" newline bitfld.long 0x10 8. "REPLAY_NO_ROLEOVER_STATUS,REPLAY_NUM Rollover Status. For a description of this standard PCIe register field see the PCI Express Specification." "0,1" bitfld.long 0x10 7. "BAD_DLLP_STATUS,Bad DLLP Status. For a description of this standard PCIe register field see the PCI Express Specification." "0,1" bitfld.long 0x10 6. "BAD_TLP_STATUS,Bad TLP Status. For a description of this standard PCIe register field see the PCI Express Specification." "0,1" newline hexmask.long.byte 0x10 1.--5. 1. "RSVDP_1,Reserved for future use." bitfld.long 0x10 0. "RX_ERR_STATUS,Receiver Error Status (Optional). For a description of this standard PCIe register field see the PCI Express Specification." "0,1" line.long 0x14 "CORR_ERR_MASK_OFF,Correctable Error Mask Register. For a description of this standard PCIe register. see the PCI Express Specification." hexmask.long.word 0x14 16.--31. 1. "RSVDP_16,Reserved for future use." bitfld.long 0x14 15. "HEADER_LOG_OVERFLOW_MASK,Header Log Overflow Error Mask (Optional). For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." "0,1" bitfld.long 0x14 14. "CORRECTED_INT_ERR_MASK,Corrected Internal Error Mask (Optional). For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." "0,1" newline bitfld.long 0x14 13. "ADVISORY_NON_FATAL_ERR_MASK,Advisory Non-Fatal Error Mask. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." "0,1" bitfld.long 0x14 12. "RPL_TIMER_TIMEOUT_MASK,Replay Timer Timeout Mask. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." "0,1" rbitfld.long 0x14 9.--11. "RSVDP_9,Reserved for future use." "0,1,2,3,4,5,6,7" newline bitfld.long 0x14 8. "REPLAY_NO_ROLEOVER_MASK,REPLAY_NUM Rollover Mask. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." "0,1" bitfld.long 0x14 7. "BAD_DLLP_MASK,Bad DLLP Mask. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." "0,1" bitfld.long 0x14 6. "BAD_TLP_MASK,Bad TLP Mask. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." "0,1" newline hexmask.long.byte 0x14 1.--5. 1. "RSVDP_1,Reserved for future use." bitfld.long 0x14 0. "RX_ERR_MASK,Receiver Error Mask (Optional). For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." "0,1" line.long 0x18 "ADV_ERR_CAP_CTRL_OFF,Advanced Error Capabilities and Control Register. For a description of this standard PCIe register. see the PCI Express Specification." hexmask.long.tbyte 0x18 13.--31. 1. "RSVDP_13,Reserved for future use." rbitfld.long 0x18 12. "CTO_PRFX_HDR_LOG_CAP,TLP Prefix Log Present. For a description of this standard PCIe register field see the PCI Express Specification." "0,1" rbitfld.long 0x18 11. "TLP_PRFX_LOG_PRESENT,Completion Timeout Prefix/Header Log Capable. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." "0,1" newline rbitfld.long 0x18 10. "MULTIPLE_HEADER_EN,Multiple Header Recording Enable. For a description of this standard PCIe register field see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R (sticky) Note: This.." "0,1" rbitfld.long 0x18 9. "MULTIPLE_HEADER_CAP,Multiple Header Recording Capable. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." "0,1" bitfld.long 0x18 8. "ECRC_CHECK_EN,ECRC Check Enable. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." "0,1" newline rbitfld.long 0x18 7. "ECRC_CHECK_CAP,ECRC Check Capable. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." "0,1" bitfld.long 0x18 6. "ECRC_GEN_EN,ECRC Generation Enable. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." "0,1" rbitfld.long 0x18 5. "ECRC_GEN_CAP,ECRC Generation Capable. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." "0,1" newline hexmask.long.byte 0x18 0.--4. 1. "FIRST_ERR_POINTER,First Error Pointer. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." rgroup.long (0x1C+0x100)++0xF line.long 0x0 "HDR_LOG_0_OFF,Header Log Register 0. For a description of this standard PCIe register. see the PCI Express Specification." hexmask.long.byte 0x0 24.--31. 1. "FIRST_DWORD_FOURTH_BYTE,Byte 3 of Header log register of First 32 bit Data Word. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." hexmask.long.byte 0x0 16.--23. 1. "FIRST_DWORD_THIRD_BYTE,Byte 2 of Header log register of First 32 bit Data Word. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." hexmask.long.byte 0x0 8.--15. 1. "FIRST_DWORD_SECOND_BYTE,Byte 1 of Header log register of First 32 bit Data Word. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." newline hexmask.long.byte 0x0 0.--7. 1. "FIRST_DWORD_FIRST_BYTE,Byte 0 of Header log register of First 32 bit Data Word. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." line.long 0x4 "HDR_LOG_1_OFF,Header Log Register 1. For a description of this standard PCIe register. see the PCI Express Specification." hexmask.long.byte 0x4 24.--31. 1. "SECOND_DWORD_FOURTH_BYTE,Byte 3 of Header log register of Second 32 bit Data Word. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." hexmask.long.byte 0x4 16.--23. 1. "SECOND_DWORD_THIRD_BYTE,Byte 2 of Header log register of Second 32 bit Data Word. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." hexmask.long.byte 0x4 8.--15. 1. "SECOND_DWORD_SECOND_BYTE,Byte 1 of Header log register of Second 32 bit Data Word. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." newline hexmask.long.byte 0x4 0.--7. 1. "SECOND_DWORD_FIRST_BYTE,Byte 0 of Header log register of Second 32 bit Data Word. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." line.long 0x8 "HDR_LOG_2_OFF,Header Log Register 2. For a description of this standard PCIe register. see the PCI Express Specification." hexmask.long.byte 0x8 24.--31. 1. "THIRD_DWORD_FOURTH_BYTE,Byte 3 of Header log register of Third 32 bit Data Word. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." hexmask.long.byte 0x8 16.--23. 1. "THIRD_DWORD_THIRD_BYTE,Byte 2 of Header log register of Third 32 bit Data Word. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." hexmask.long.byte 0x8 8.--15. 1. "THIRD_DWORD_SECOND_BYTE,Byte 1 of Header log register of Third 32 bit Data Word. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." newline hexmask.long.byte 0x8 0.--7. 1. "THIRD_DWORD_FIRST_BYTE,Byte 0 of Header log register of Third 32 bit Data Word. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." line.long 0xC "HDR_LOG_3_OFF,Header Log Register 3. For a description of this standard PCIe register. see the PCI Express Specification." hexmask.long.byte 0xC 24.--31. 1. "FOURTH_DWORD_FOURTH_BYTE,Byte 3 of Header log register of Fourth 32 bit Data Word. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." hexmask.long.byte 0xC 16.--23. 1. "FOURTH_DWORD_THIRD_BYTE,Byte 2 of Header log register of Fourth 32 bit Data Word. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." hexmask.long.byte 0xC 8.--15. 1. "FOURTH_DWORD_SECOND_BYTE,Byte 1 of Header log register of Fourth 32 bit Data Word. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." newline hexmask.long.byte 0xC 0.--7. 1. "FOURTH_DWORD_FIRST_BYTE,Byte 0 of Header log register of Fourth 32 bit Data Word. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." group.long (0x2C+0x100)++0x7 line.long 0x0 "ROOT_ERR_CMD_OFF,Root Error Command Register. For a description of this standard PCIe register. see the PCI Express Specification." hexmask.long 0x0 3.--31. 1. "RSVDP_3,Reserved for future use." bitfld.long 0x0 2. "FATAL_ERR_REPORTING_EN,Fatal Error Reporting Enable. For a description of this standard PCIe register field see the PCI Express Specification." "0,1" bitfld.long 0x0 1. "NON_FATAL_ERR_REPORTING_EN,Non-Fatal Error Reporting Enable. For a description of this standard PCIe register field see the PCI Express Specification." "0,1" newline bitfld.long 0x0 0. "CORR_ERR_REPORTING_EN,Correctable Error Reporting Enable. For a description of this standard PCIe register field see the PCI Express Specification." "0,1" line.long 0x4 "ROOT_ERR_STATUS_OFF,Root Error Status Register. For a description of this standard PCIe register. see the PCI Express Specification." hexmask.long.byte 0x4 27.--31. 1. "ADV_ERR_INT_MSG_NUM,Advanced Error Interrupt Message Number. For a description of this standard PCIe register field see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN.." hexmask.long.tbyte 0x4 7.--26. 1. "RSVDP_7,Reserved for future use." bitfld.long 0x4 6. "FATAL_ERR_MSG_RX,One or more Fatal Error Messages Received. For a description of this standard PCIe register field see the PCI Express Specification." "0,1" newline bitfld.long 0x4 5. "NON_FATAL_ERR_MSG_RX,One or more Non-Fatal Error Messages Received. For a description of this standard PCIe register field see the PCI Express Specification." "0,1" bitfld.long 0x4 4. "FIRST_UNCORR_FATAL,First Uncorrectable Error is Fatal. For a description of this standard PCIe register field see the PCI Express Specification." "0,1" bitfld.long 0x4 3. "MUL_ERR_FATAL_NON_FATAL_RX,Multiple Fatal or Non-Fatal Errors Received. For a description of this standard PCIe register field see the PCI Express Specification." "0,1" newline bitfld.long 0x4 2. "ERR_FATAL_NON_FATAL_RX,Fatal or Non-Fatal Error Received. For a description of this standard PCIe register field see the PCI Express Specification." "0,1" bitfld.long 0x4 1. "MUL_ERR_COR_RX,Multiple Correctable Errors Received. For a description of this standard PCIe register field see the PCI Express Specification." "0,1" bitfld.long 0x4 0. "ERR_COR_RX,Correctable Error Received. For a description of this standard PCIe register field see the PCI Express Specification." "0,1" rgroup.long (0x34+0x100)++0x13 line.long 0x0 "ERR_SRC_ID_OFF,Error Source Identification Register. For a description of this standard PCIe register. see the PCI Express Specification." hexmask.long.word 0x0 16.--31. 1. "ERR_FATAL_NON_FATAL_SOURCE_ID,Source of Fatal/Non-Fatal Error. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." hexmask.long.word 0x0 0.--15. 1. "ERR_COR_SOURCE_ID,Source of Correctable Error. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." line.long 0x4 "TLP_PREFIX_LOG_1_OFF,TLP Prefix Log Register 1. For a description of this standard PCIe register. see the PCI Express Specification." hexmask.long.byte 0x4 24.--31. 1. "CFG_TLP_PFX_LOG_1_FOURTH_BYTE,Byte 3 of Error TLP Prefix Log 1. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." hexmask.long.byte 0x4 16.--23. 1. "CFG_TLP_PFX_LOG_1_THIRD_BYTE,Byte 2 of Error TLP Prefix Log 1. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." hexmask.long.byte 0x4 8.--15. 1. "CFG_TLP_PFX_LOG_1_SECOND_BYTE,Byte 1 of Error TLP Prefix Log 1. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." newline hexmask.long.byte 0x4 0.--7. 1. "CFG_TLP_PFX_LOG_1_FIRST_BYTE,Byte 0 of Error TLP Prefix Log 1. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." line.long 0x8 "TLP_PREFIX_LOG_2_OFF,TLP Prefix Log Register 2. For a description of this standard PCIe register. see the PCI Express Specification." hexmask.long.byte 0x8 24.--31. 1. "CFG_TLP_PFX_LOG_2_FOURTH_BYTE,Byte 3 Error TLP Prefix Log 2. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." hexmask.long.byte 0x8 16.--23. 1. "CFG_TLP_PFX_LOG_2_THIRD_BYTE,Byte 2 Error TLP Prefix Log 2. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." hexmask.long.byte 0x8 8.--15. 1. "CFG_TLP_PFX_LOG_2_SECOND_BYTE,Byte 1 Error TLP Prefix Log 2. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." newline hexmask.long.byte 0x8 0.--7. 1. "CFG_TLP_PFX_LOG_2_FIRST_BYTE,Byte 0 Error TLP Prefix Log 2. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." line.long 0xC "TLP_PREFIX_LOG_3_OFF,TLP Prefix Log Register 3. For a description of this standard PCIe register. see the PCI Express Specification." hexmask.long.byte 0xC 24.--31. 1. "CFG_TLP_PFX_LOG_3_FOURTH_BYTE,Byte 3 Error TLP Prefix Log 3. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." hexmask.long.byte 0xC 16.--23. 1. "CFG_TLP_PFX_LOG_3_THIRD_BYTE,Byte 2 Error TLP Prefix Log 3. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." hexmask.long.byte 0xC 8.--15. 1. "CFG_TLP_PFX_LOG_3_SECOND_BYTE,Byte 1 Error TLP Prefix Log 3. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." newline hexmask.long.byte 0xC 0.--7. 1. "CFG_TLP_PFX_LOG_3_FIRST_BYTE,Byte 0 Error TLP Prefix Log 3. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." line.long 0x10 "TLP_PREFIX_LOG_4_OFF,TLP Prefix Log Register 4. For a description of this standard PCIe register. see the PCI Express Specification." hexmask.long.byte 0x10 24.--31. 1. "CFG_TLP_PFX_LOG_4_FOURTH_BYTE,Byte 3 Error TLP Prefix Log 4. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." hexmask.long.byte 0x10 16.--23. 1. "CFG_TLP_PFX_LOG_4_THIRD_BYTE,Byte 2 Error TLP Prefix Log 4. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." hexmask.long.byte 0x10 8.--15. 1. "CFG_TLP_PFX_LOG_4_SECOND_BYTE,Byte 1 Error TLP Prefix Log 4. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." newline hexmask.long.byte 0x10 0.--7. 1. "CFG_TLP_PFX_LOG_4_FIRST_BYTE,Byte 0 Error TLP Prefix Log 4. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." tree.end tree "PF0_MSI_CAP (PF MSI Capability Structure)" group.long (0x0+0x50)++0x13 line.long 0x0 "PCI_MSI_CAP_ID_NEXT_CTRL_REG,MSI Capability Header and Message Control Register." hexmask.long.byte 0x0 27.--31. 1. "RSVDP_27,Reserved for future use." bitfld.long 0x0 26. "PCI_MSI_EXT_DATA_EN,Extended Message Data Enable. - If set the function is enabled to provide Extended Message Data. - If clear the function is not enabled to provide Extended Message Data. Note: The access attributes of this field are as follows: -.." "0,1" bitfld.long 0x0 25. "PCI_MSI_EXT_DATA_CAP,Extended Message Data Capable. - If set the function is capable of providing Extended Message Data. - If clear the function does not support providing Extended Message Data. Note: The access attributes of this field are as follows:.." "0,1" newline rbitfld.long 0x0 24. "PCI_PVM_SUPPORT,Per-Vector Masking Capable. - If set the function supports MSI Per-Vector Masking. - If clear the function does not support MSI Per-Vector Masking. This bit must be set if the function is a PF or VF within an SR-IOV Device." "0,1" bitfld.long 0x0 23. "PCI_MSI_64_BIT_ADDR_CAP,64 bit address capable. - If set the function is capable of sending a 64-bit message address. - If clear the function is not capable of sending a 64-bit message address. This bit must be set if the function is a PCI Express.." "0,1" bitfld.long 0x0 20.--22. "PCI_MSI_MULTIPLE_MSG_EN,Multiple Message Enable. Software writes to this field to indicate the number of allocated vectors (equal to or less than the number of requested vectors). The number of allocated vectors is aligned to a power of two. If a.." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 17.--19. "PCI_MSI_MULTIPLE_MSG_CAP,Multiple Message Capable. System software reads this field to determine the number of requested vectors. The number of requested vectors must be aligned to a power of two (if a function requires three vectors it requests four by.." "0,1,2,3,4,5,6,7" bitfld.long 0x0 16. "PCI_MSI_ENABLE,MSI Enable. - If set and the MSI-X Enable bit in the MSI-X Message Control register is clear the function is permitted to use MSI to request service and is prohibited from using INTx interrupts. System configuration software sets this bit.." "0,1" hexmask.long.byte 0x0 8.--15. 1. "PCI_MSI_CAP_NEXT_OFFSET,Next Capability Pointer. This field contains the offset to the next PCI Capability structure or 00h if no other items exist in the linked list of Capabilities. Note: The access attributes of this field are as follows: - Wire: No.." newline hexmask.long.byte 0x0 0.--7. 1. "PCI_MSI_CAP_ID,Capability ID. Indicates the MSI Capability structure. This field returns a Capability ID of 05h indicating that this is an MSI Capability structure." line.long 0x4 "MSI_CAP_OFF_04H_REG,Message Address Register for MSI (Offset 04h)." hexmask.long 0x4 2.--31. 1. "PCI_MSI_CAP_OFF_04H,Message Address - System-specified message address. If the Message Enable bit (bit 16 of the PCI_MSI_CAP_ID_NEXT_CTRL_REG register) is set the contents of this field specify the DWORD-aligned address (Address[31:02]) for the MSI.." rbitfld.long 0x4 0.--1. "RSVDP_0,Reserved for future use." "0,1,2,3" line.long 0x8 "MSI_CAP_OFF_08H_REG,For a function that supports a 32-bit message address. - bits[31:16] of this register represent the Extended Message Data. and - bits[15:0] of this register represent the Message Data For a function that supports a 64-bit message.." hexmask.long.word 0x8 16.--31. 1. "PCI_MSI_CAP_OFF_0AH,For a function that supports a 32-bit message address this field contains Extended Message Data (System-specified message data). For the MSI Capability structures without per-vector masking it must be implemented if the Extended.." hexmask.long.word 0x8 0.--15. 1. "PCI_MSI_CAP_OFF_08H,For a function that supports a 32-bit message address this field contains Message Data (System-specified message data). If the Message Enable bit (bit 16 of the PCI_MSI_CAP_ID_NEXT_CTRL_REG) is set the function sends a DWORD Memory.." line.long 0xC "MSI_CAP_OFF_0CH_REG,For a function that supports a 32-bit message address. this register contains the Mask Bits when the Per-Vector Masking Capable bit (bit 24 of PCI_MSI_CAP_ID_NEXT_CTRL_REG) is set. For a function that supports a 64-bit message.." hexmask.long.word 0xC 16.--31. 1. "PCI_MSI_CAP_OFF_0EH,For a function that supports a 32-bit message address this field contains the upper Mask Bits when the Per Vector Masking Capable bit (PCI_MSI_CAP_ID_NEXT_CTRL_REG.PCI_PVM_SUPPORT) is set. For a function that supports a 64-bit.." hexmask.long.word 0xC 0.--15. 1. "PCI_MSI_CAP_OFF_0CH,For a function that supports a 32-bit message address this field contains the lower Mask Bits when the Per Vector Masking Capable bit (PCI_MSI_CAP_ID_NEXT_CTRL_REG.PCI_PVM_SUPPORT) is set. For a function that supports a 64-bit.." line.long 0x10 "MSI_CAP_OFF_10H_REG,For a function that supports a 32-bit message address. this register contains the Pending Bits when the Per-Vector Masking Capable bit (bit 24 of PCI_MSI_CAP_ID_NEXT_CTRL_REG) is set. For a function that supports a 64-bit message.." hexmask.long 0x10 0.--31. 1. "PCI_MSI_CAP_OFF_10H,Used for MSI when the Per Vector Masking Capable bit (PCI_MSI_CAP_ID_NEXT_CTRL_REG.PCI_PVM_SUPPORT) is set. For 32-bit contains Pending Bits. For 64-bit contains Mask Bits. For a description of this standard PCIe register field see.." rgroup.long (0x14+0x50)++0x3 line.long 0x0 "MSI_CAP_OFF_14H_REG,Pending Bits Register for MSI. This register is used for a function that supports a 64-bit message address when the Per-Vector Masking Capable bit (bit 24 of PCI_MSI_CAP_ID_NEXT_CTRL_REG) is set." hexmask.long 0x0 0.--31. 1. "PCI_MSI_CAP_OFF_14H,Pending Bits. For each pending bit that is set the function has a pending associated message." tree.end tree "PF0_MSIX_CAP (PF MSI-X Capability Structure)" group.long (0x0+0xB0)++0xB line.long 0x0 "PCI_MSIX_CAP_ID_NEXT_CTRL_REG,MSI-X Capability ID. Next Pointer. Control Registers. For a description of this standard PCIe register. see the PCI Express Base Specification." bitfld.long 0x0 31. "PCI_MSIX_ENABLE,MSI-X Enable. For a description of this standard PCIe register field see the PCI Express Base Specification." "0,1" bitfld.long 0x0 30. "PCI_MSIX_FUNCTION_MASK,Function Mask. For a description of this standard PCIe register field see the PCI Express Base Specification. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" "0,1" rbitfld.long 0x0 27.--29. "RSVDP_27,Reserved for future use." "0,1,2,3,4,5,6,7" newline hexmask.long.word 0x0 16.--26. 1. "PCI_MSIX_TABLE_SIZE,MSI-X Table Size. For a description of this standard PCIe register field see the PCI Express Base Specification. SRIOV Note: All VFs in a single PF have the same value for 'MSI-X Table Size' (PCI_MSIX_TABLE_SIZE field in.." hexmask.long.byte 0x0 8.--15. 1. "PCI_MSIX_CAP_NEXT_OFFSET,MSI-X Next Capability Pointer. For a description of this standard PCIe register field see the PCI Express Base Specification. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN.." hexmask.long.byte 0x0 0.--7. 1. "PCI_MSIX_CAP_ID,MSI-X Capability ID. For a description of this standard PCIe register field see the PCI Express Base Specification." line.long 0x4 "MSIX_TABLE_OFFSET_REG,MSI-X Table Offset and BIR Register. For a description of this standard PCIe register. see the PCI Express Base Specification." hexmask.long 0x4 3.--31. 1. "PCI_MSIX_TABLE_OFFSET,MSI-X Table Offset. For a description of this standard PCIe register field see the PCI Express Base Specification. SRIOV Note: All VFs in a single PF have the same value for 'MSI-X Table Offset' (PCI_MSIX_TABLE_OFFSET field in.." bitfld.long 0x4 0.--2. "PCI_MSIX_BIR,MSI-X Table BAR Indicator Register Field. For a description of this standard PCIe register field see the PCI Express Base Specification. SRIOV Note: All VFs in a single PF have the same value for 'MSI-X Table BAR Indicator Register'.." "0,1,2,3,4,5,6,7" line.long 0x8 "MSIX_PBA_OFFSET_REG,MSI-X PBA Offset and BIR Register. For a description of this standard PCIe register. see the PCI Express Base Specification." hexmask.long 0x8 3.--31. 1. "PCI_MSIX_PBA_OFFSET,MSI-X PBA Offset. For a description of this standard PCIe register field see the PCI Express Base Specification. SRIOV Note: All VFs in a single PF have the same value for 'MSI-X PBA Offset' (PCI_MSIX_PBA_OFFSET field in.." bitfld.long 0x8 0.--2. "PCI_MSIX_PBA_BIR,MSI-X PBA BIR. For a description of this standard PCIe register field see the PCI Express Base Specification. SRIOV Note: All VFs in a single PF have the same value for 'MSI-X PBA BIR' (PCI_MSIX_PBA_BIR field in.." "0,1,2,3,4,5,6,7" tree.end tree "PF0_MSIX_CAP_DBI2 (DBI2 Shadow Block: PF MSI-X Capability Structure)" rgroup.long (0x0+0x10B0)++0x3 line.long 0x0 "SHADOW_PCI_MSIX_CAP_ID_NEXT_CTRL_REG,MSI-X Capability ID. Next Pointer. Control Registers. For a description of this standard PCIe register. see the PCI Express Base Specification." hexmask.long.byte 0x0 27.--31. 1. "RSVDP_27,Reserved for future use." hexmask.long.word 0x0 16.--26. 1. "PCI_MSIX_TABLE_SIZE,MSI-X Table Size in the shadow register. Note: The access attributes of this field are as follows: - Wire: No access - Dbi: No access - Dbi2: if (DBI_RO_WR_EN == 1) then R/W else R Note: This register field is sticky." hexmask.long.word 0x0 0.--15. 1. "RSVDP_0,Reserved for future use." group.long 0x4++0x7 line.long 0x0 "SHADOW_MSIX_TABLE_OFFSET_REG,MSI-X Table Offset and BIR Register. For a description of this standard PCIe register. see the PCI Express Base Specification." hexmask.long 0x0 3.--31. 1. "PCI_MSIX_TABLE_OFFSET,MSI-X Table Offset. For a description of this standard PCIe register field see the PCI Express Base Specification. Note: The access attributes of this field are as follows: - Wire: No access - Dbi: No access - Dbi2: if.." bitfld.long 0x0 0.--2. "PCI_MSIX_BIR,MSI-X Table BAR Indicator Register Field. For a description of this standard PCIe register field see the PCI Express Base Specification. Note: The access attributes of this field are as follows: - Wire: No access - Dbi: No access - Dbi2: if.." "?,?,if,?,?,?,?,?" line.long 0x4 "SHADOW_MSIX_PBA_OFFSET_REG,MSI-X PBA Offset and BIR Register. For a description of this standard PCIe register. see the PCI Express Base Specification." hexmask.long 0x4 3.--31. 1. "PCI_MSIX_PBA_OFFSET,MSI-X PBA Offset. For a description of this standard PCIe register field see the PCI Express Base Specification. Note: The access attributes of this field are as follows: - Wire: No access - Dbi: No access - Dbi2: if (DBI_RO_WR_EN ==.." bitfld.long 0x4 0.--2. "PCI_MSIX_PBA_BIR,MSI-X PBA BIR. For a description of this standard PCIe register field see the PCI Express Base Specification. Note: The access attributes of this field are as follows: - Wire: No access - Dbi: No access - Dbi2: if (DBI_RO_WR_EN == 1 &&.." "?,?,if,?,?,?,?,?" tree.end tree "PF0_DMA_CAP (DMA Port Logic Structure)" group.long (0x0+0xC8000)++0x3 line.long 0x0 "DMA_CTRL_DATA_ARB_PRIOR_OFF,DMA Arbitration Scheme for TRGT1 Interface. This register is used to control traffic priorities among various sources that are delivered to your application through TRGT1 where 0x0 represents the highest priority. - Non-DMA Rx.." hexmask.long.tbyte 0x0 12.--31. 1. "RSVDP_12,Reserved for future use." bitfld.long 0x0 9.--11. "RDBUFF_TRGT_WEIGHT,DMA Read Channel MWr Requests. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 6.--8. "RD_CTRL_TRGT_WEIGHT,DMA Read Channel MRd Requests. For LL element/descriptor access. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" "0,1,2,3,4,5,6,7" bitfld.long 0x0 3.--5. "WR_CTRL_TRGT_WEIGHT,DMA Write Channel MRd Requests. For DMA data requests and LL element/descriptor access. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 0.--2. "RTRGT1_WEIGHT,Non-DMA Rx Requests. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" "0,1,2,3,4,5,6,7" group.long (0x8+0xC8000)++0xB line.long 0x0 "DMA_CTRL_OFF,DMA Number of Channels Register." hexmask.long.byte 0x0 26.--31. 1. "RSVDP_26,Reserved for future use." bitfld.long 0x0 25. "DIS_C2W_CACHE_RD,Disable DMA Read Channels 'completion to memory write' context cache pre-fetch function. Note: For internal debugging only. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" "0,1" newline bitfld.long 0x0 24. "DIS_C2W_CACHE_WR,Disable DMA Write Channels 'completion to memory write' context cache pre-fetch function. Note: For internal debugging only. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" "0,1" hexmask.long.byte 0x0 20.--23. 1. "RSVDP_20,Reserved for future use." newline hexmask.long.byte 0x0 16.--19. 1. "NUM_DMA_RD_CHAN,Number of Read Channels. You can read this register to determine the number of read channels the DMA controller has been configured to support." hexmask.long.word 0x0 4.--15. 1. "RSVDP_4,Reserved for future use." newline hexmask.long.byte 0x0 0.--3. 1. "NUM_DMA_WR_CHAN,Number of Write Channels. You can read this register to determine the number of write channels the DMA controller has been configured to support." line.long 0x4 "DMA_WRITE_ENGINE_EN_OFF,DMA Write Engine Enable Register." hexmask.long.byte 0x4 24.--31. 1. "RSVDP_24,Reserved for future use." bitfld.long 0x4 23. "DMA_WRITE_ENGINE_EN_HSHAKE_CH7,Enable Handshake for DMA Write Engine Channel 7. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" "0,1" newline bitfld.long 0x4 22. "DMA_WRITE_ENGINE_EN_HSHAKE_CH6,Enable Handshake for DMA Write Engine Channel 6. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" "0,1" bitfld.long 0x4 21. "DMA_WRITE_ENGINE_EN_HSHAKE_CH5,Enable Handshake for DMA Write Engine Channel 5. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" "0,1" newline bitfld.long 0x4 20. "DMA_WRITE_ENGINE_EN_HSHAKE_CH4,Enable Handshake for DMA Write Engine Channel 4. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" "0,1" bitfld.long 0x4 19. "DMA_WRITE_ENGINE_EN_HSHAKE_CH3,Enable Handshake for DMA Write Engine Channel 3. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" "0,1" newline bitfld.long 0x4 18. "DMA_WRITE_ENGINE_EN_HSHAKE_CH2,Enable Handshake for DMA Write Engine Channel 2. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" "0,1" bitfld.long 0x4 17. "DMA_WRITE_ENGINE_EN_HSHAKE_CH1,Enable Handshake for DMA Write Engine Channel 1. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" "0,1" newline bitfld.long 0x4 16. "DMA_WRITE_ENGINE_EN_HSHAKE_CH0,Enable Handshake for DMA Write Engine Channel 0. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" "0,1" hexmask.long.word 0x4 1.--15. 1. "RSVDP_1,Reserved for future use." newline bitfld.long 0x4 0. "DMA_WRITE_ENGINE,DMA Write Engine Enable. - 1: Enable - 0: Disable (Soft Reset) For normal operation you must initially set this bit to '1' before any other software setup actions. You do not need to toggle or rewrite to this bit during normal.." "Disable,Enable" line.long 0x8 "DMA_WRITE_DOORBELL_OFF,DMA Write Doorbell Register." bitfld.long 0x8 31. "WR_STOP,Stop. Set in conjunction with the Doorbell Number field. The DMA write channel stops issuing requests sets the channel status to 'Stopped' and asserts the 'Abort' interrupt if it is enabled. Before setting the Stop bit you must read the.." "0,1" hexmask.long 0x8 3.--30. 1. "RSVDP_3,Reserved for future use." newline bitfld.long 0x8 0.--2. "WR_DOORBELL_NUM,Doorbell Number. You must write the channel number to this register to start the DMA write transfer for that channel. The DMA detects a write to this register field even if the value of this field does not change. You do not need to.." "0,1,2,3,4,5,6,7" group.long (0x18+0xC8000)++0x7 line.long 0x0 "DMA_WRITE_CHANNEL_ARB_WEIGHT_LOW_OFF,DMA Write Engine Channel Arbitration Weight Low Register. The 5-bit channel weight (for write channels 0-3) specifies the maximum number of TLP requests that the DMA can issue for that channel before it must return to.." hexmask.long.word 0x0 20.--31. 1. "RSVDP_20,Reserved for future use." hexmask.long.byte 0x0 15.--19. 1. "WRITE_CHANNEL3_WEIGHT,Channel 3 Weight. The weight is initialized by software before ringing the doorbell. The value is used by the channel weighted round robin arbiter to select the next channel read request. A value of '0' means that one TLP is issued.." newline hexmask.long.byte 0x0 10.--14. 1. "WRITE_CHANNEL2_WEIGHT,Channel 2 Weight. The weight is initialized by software before ringing the doorbell. The value is used by the channel weighted round robin arbiter to select the next channel read request. A value of '0' means that one TLP is issued.." hexmask.long.byte 0x0 5.--9. 1. "WRITE_CHANNEL1_WEIGHT,Channel 1 Weight. The weight is initialized by software before ringing the doorbell. The value is used by the channel weighted round robin arbiter to select the next channel read request. A value of '0' means that one TLP is issued.." newline hexmask.long.byte 0x0 0.--4. 1. "WRITE_CHANNEL0_WEIGHT,Channel 0 Weight. The weight is initialized by software before ringing the doorbell. The value is used by the channel weighted round robin arbiter to select the next channel read request. A value of '0' means that one TLP is issued.." line.long 0x4 "DMA_WRITE_CHANNEL_ARB_WEIGHT_HIGH_OFF,DMA Write Engine Channel Arbitration Weight High Register. The 5-bit channel weight (for write channels 4-7) specifies the maximum number of TLP requests that the DMA can issue for that channel before it must return.." hexmask.long.word 0x4 20.--31. 1. "RSVDP_20,Reserved for future use." hexmask.long.byte 0x4 15.--19. 1. "WRITE_CHANNEL7_WEIGHT,Channel 7 Weight. The weight is initialized by software before ringing the doorbell. The value is used by the channel weighted round robin arbiter to select the next channel read request. A value of '0' means that one TLP is issued.." newline hexmask.long.byte 0x4 10.--14. 1. "WRITE_CHANNEL6_WEIGHT,Channel 6 Weight. The weight is initialized by software before ringing the doorbell. The value is used by the channel weighted round robin arbiter to select the next channel read request. A value of '0' means that one TLP is issued.." hexmask.long.byte 0x4 5.--9. 1. "WRITE_CHANNEL5_WEIGHT,Channel 5 Weight. The weight is initialized by software before ringing the doorbell. The value is used by the channel weighted round robin arbiter to select the next channel read request. A value of '0' means that one TLP is issued.." newline hexmask.long.byte 0x4 0.--4. 1. "WRITE_CHANNEL4_WEIGHT,Channel 4 Weight. The weight is initialized by software before ringing the doorbell. The value is used by the channel weighted round robin arbiter to select the next channel read request. A value of '0' means that one TLP is issued.." group.long (0x2C+0xC8000)++0x7 line.long 0x0 "DMA_READ_ENGINE_EN_OFF,DMA Read Engine Enable Register." hexmask.long.byte 0x0 24.--31. 1. "RSVDP_24,Reserved for future use." bitfld.long 0x0 23. "DMA_READ_ENGINE_EN_HSHAKE_CH7,Enable Handshake for DMA Read Engine Channel 7. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" "0,1" newline bitfld.long 0x0 22. "DMA_READ_ENGINE_EN_HSHAKE_CH6,Enable Handshake for DMA Read Engine Channel 6. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" "0,1" bitfld.long 0x0 21. "DMA_READ_ENGINE_EN_HSHAKE_CH5,Enable Handshake for DMA Read Engine Channel 5. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" "0,1" newline bitfld.long 0x0 20. "DMA_READ_ENGINE_EN_HSHAKE_CH4,Enable Handshake for DMA Read Engine Channel 4. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" "0,1" bitfld.long 0x0 19. "DMA_READ_ENGINE_EN_HSHAKE_CH3,Enable Handshake for DMA Read Engine Channel 3. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" "0,1" newline bitfld.long 0x0 18. "DMA_READ_ENGINE_EN_HSHAKE_CH2,Enable Handshake for DMA Read Engine Channel 2. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" "0,1" bitfld.long 0x0 17. "DMA_READ_ENGINE_EN_HSHAKE_CH1,Enable Handshake for DMA Read Engine Channel 1. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" "0,1" newline bitfld.long 0x0 16. "DMA_READ_ENGINE_EN_HSHAKE_CH0,Enable Handshake for DMA Read Engine Channel 0. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" "0,1" hexmask.long.word 0x0 1.--15. 1. "RSVDP_1,Reserved for future use." newline bitfld.long 0x0 0. "DMA_READ_ENGINE,DMA Read Engine Enable. - 1: Enable - 0: Disable (Soft Reset) For normal operation you must initially set this bit to '1' before any other software setup actions. You do not need to toggle or rewrite to this bit during normal operation." "Disable,Enable" line.long 0x4 "DMA_READ_DOORBELL_OFF,DMA Read Doorbell Register." bitfld.long 0x4 31. "RD_STOP,Stop. Set in conjunction with the Doorbell Number field. The DMA read channel stops issuing requests sets the channel status to 'Stopped' and asserts the 'Abort' interrupt if it is enabled. Before setting the Stop bit you must read the channel.." "0,1" hexmask.long 0x4 3.--30. 1. "RSVDP_3,Reserved for future use." newline bitfld.long 0x4 0.--2. "RD_DOORBELL_NUM,Doorbell Number. You must write 0x0 to this register to start the DMA read transfer for that channel. The DMA detects a write to this register field even if the value of this field does not change. The range of this field is 0x0 to 0x7.." "0,1,2,3,4,5,6,7" group.long (0x38+0xC8000)++0x7 line.long 0x0 "DMA_READ_CHANNEL_ARB_WEIGHT_LOW_OFF,DMA Read Engine Channel Arbitration Weight Low Register. The 5-bit channel weight (for read channels 0-3) specifies the maximum number of TLP requests that the DMA can issue for that channel before it must return to.." hexmask.long.word 0x0 20.--31. 1. "RSVDP_20,Reserved for future use." hexmask.long.byte 0x0 15.--19. 1. "READ_CHANNEL3_WEIGHT,Channel 3 Weight. The weight is initialized by software before ringing the doorbell. The value is used by the channel weighted round robin arbiter to select the next channel read request. Note: The access attributes of this field are.." newline hexmask.long.byte 0x0 10.--14. 1. "READ_CHANNEL2_WEIGHT,Channel 2 Weight. The weight is initialized by software before ringing the doorbell. The value is used by the channel weighted round robin arbiter to select the next channel read request. Note: The access attributes of this field are.." hexmask.long.byte 0x0 5.--9. 1. "READ_CHANNEL1_WEIGHT,Channel 1 Weight. The weight is initialized by software before ringing the doorbell. The value is used by the channel weighted round robin arbiter to select the next channel read request. Note: The access attributes of this field are.." newline hexmask.long.byte 0x0 0.--4. 1. "READ_CHANNEL0_WEIGHT,Channel 0 Weight. The weight is initialized by software before ringing the doorbell. The value is used by the channel weighted round robin arbiter to select the next channel read request. Note: The access attributes of this field are.." line.long 0x4 "DMA_READ_CHANNEL_ARB_WEIGHT_HIGH_OFF,DMA Read Engine Channel Arbitration Weight High Register. The 5-bit channel weight (for read channels 4-7) specifies the maximum number of TLP requests that the DMA can issue for that channel before it must return to.." hexmask.long.word 0x4 20.--31. 1. "RSVDP_20,Reserved for future use." hexmask.long.byte 0x4 15.--19. 1. "READ_CHANNEL7_WEIGHT,Channel 7 Weight. The weight is initialized by software before ringing the doorbell. The value is used by the channel weighted round robin arbiter to select the next channel read request. Note: The access attributes of this field are.." newline hexmask.long.byte 0x4 10.--14. 1. "READ_CHANNEL6_WEIGHT,Channel 6 Weight. The weight is initialized by software before ringing the doorbell. The value is used by the channel weighted round robin arbiter to select the next channel read request. Note: The access attributes of this field are.." hexmask.long.byte 0x4 5.--9. 1. "READ_CHANNEL5_WEIGHT,Channel 5 Weight. The weight is initialized by software before ringing the doorbell. The value is used by the channel weighted round robin arbiter to select the next channel read request. Note: The access attributes of this field are.." newline hexmask.long.byte 0x4 0.--4. 1. "READ_CHANNEL4_WEIGHT,Channel 4 Weight. The weight is initialized by software before ringing the doorbell. The value is used by the channel weighted round robin arbiter to select the next channel read request. Note: The access attributes of this field are.." group.long (0x4C+0xC8000)++0x3 line.long 0x0 "DMA_WRITE_INT_STATUS_OFF,DMA Write Interrupt Status Register." hexmask.long.byte 0x0 24.--31. 1. "RSVDP_24,Reserved for future use." hexmask.long.byte 0x0 16.--23. 1. "WR_ABORT_INT_STATUS,Abort Interrupt Status. The DMA write channel has detected an error or you manually stopped the transfer as described in 'Error Handling Assistance by Remote Software'. Each bit corresponds to a DMA channel. Bit [0] corresponds to.." newline hexmask.long.byte 0x0 8.--15. 1. "RSVDP_8,Reserved for future use." hexmask.long.byte 0x0 0.--7. 1. "WR_DONE_INT_STATUS,Done Interrupt Status. The DMA write channel has successfully completed the DMA transfer. For more details see 'Interrupts and Error Handling'. Each bit corresponds to a DMA channel. Bit [0] corresponds to channel 0. - Enabling: For.." group.long (0x54+0xC8000)++0x7 line.long 0x0 "DMA_WRITE_INT_MASK_OFF,DMA Write Interrupt Mask Register." hexmask.long.byte 0x0 24.--31. 1. "RSVDP_24,Reserved for future use." hexmask.long.byte 0x0 16.--23. 1. "WR_ABORT_INT_MASK,Abort Interrupt Mask. Prevents the Abort interrupt status field in the DMA write interrupt status register from asserting the edma_int output. Each bit corresponds to a DMA channel. Bit [0] corresponds to channel 0. Note: The access.." newline hexmask.long.byte 0x0 8.--15. 1. "RSVDP_8,Reserved for future use." hexmask.long.byte 0x0 0.--7. 1. "WR_DONE_INT_MASK,Done Interrupt Mask. Prevents the Done interrupt status field in the DMA write interrupt status register from asserting the edma_int output. Each bit corresponds to a DMA channel. Bit [0] corresponds to channel 0. Note: The access.." line.long 0x4 "DMA_WRITE_INT_CLEAR_OFF,DMA Write Interrupt Clear Register." hexmask.long.byte 0x4 24.--31. 1. "RSVDP_24,Reserved for future use." hexmask.long.byte 0x4 16.--23. 1. "WR_ABORT_INT_CLEAR,Abort Interrupt Clear. You must write a 1'b1 to clear the corresponding bit in the Abort interrupt status field of the DMA write interrupt status register. Each bit corresponds to a DMA channel. Bit [0] corresponds to channel 0. Note:.." newline hexmask.long.byte 0x4 8.--15. 1. "RSVDP_8,Reserved for future use." hexmask.long.byte 0x4 0.--7. 1. "WR_DONE_INT_CLEAR,Done Interrupt Clear. You must write a 1'b1 to clear the corresponding bit in the Done interrupt status field of the DMA write interrupt status register. Each bit corresponds to a DMA channel. Bit [0] corresponds to channel 0. Note:.." rgroup.long (0x5C+0xC8000)++0x3 line.long 0x0 "DMA_WRITE_ERR_STATUS_OFF,DMA Write Error Status Register" hexmask.long.byte 0x0 24.--31. 1. "RSVDP_24,Reserved for future use." hexmask.long.byte 0x0 16.--23. 1. "LINKLIST_ELEMENT_FETCH_ERR_DETECT,Linked List Element Fetch Error Detected. The DMA write channel has received an error response from the AXI bus (or TRGT1 interface when the AXI Bridge is not used) while reading a linked list element from local memory." newline hexmask.long.byte 0x0 8.--15. 1. "RSVDP_8,Reserved for future use." hexmask.long.byte 0x0 0.--7. 1. "APP_READ_ERR_DETECT,Application Read Error Detected. The DMA write channel has received an error response from the AXI bus (or TRGT1 interface when the AXI Bridge is not used) while reading data from it. Each bit corresponds to a DMA channel. Bit [0].." group.long (0x60+0xC8000)++0x1F line.long 0x0 "DMA_WRITE_DONE_IMWR_LOW_OFF,DMA Write Done IMWr Address Low Register." hexmask.long 0x0 0.--31. 1. "DMA_WRITE_DONE_LOW_REG,The DMA uses this field to generate bits [31:0] of the address field for the Done IMWr TLP. Bits [1:0] must be '00' as this address must be dword aligned. Note: The access attributes of this field are as follows: - Wire: No access." line.long 0x4 "DMA_WRITE_DONE_IMWR_HIGH_OFF,DMA Write Done IMWr Interrupt Address High Register." hexmask.long 0x4 0.--31. 1. "DMA_WRITE_DONE_HIGH_REG,The DMA uses this field to generate bits [63:32] of the address field for the Done IMWr TLP. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" line.long 0x8 "DMA_WRITE_ABORT_IMWR_LOW_OFF,DMA Write Abort IMWr Address Low Register." hexmask.long 0x8 0.--31. 1. "DMA_WRITE_ABORT_LOW_REG,The DMA uses this field to generate bits [31:0] of the address field for the Abort IMWr TLP it generates. Bits [1:0] must be '00' as this address must be dword aligned. Note: The access attributes of this field are as follows: -.." line.long 0xC "DMA_WRITE_ABORT_IMWR_HIGH_OFF,DMA Write Abort IMWr Address High Register." hexmask.long 0xC 0.--31. 1. "DMA_WRITE_ABORT_HIGH_REG,The DMA uses this field to generate bits [63:32] of the address field for the Abort IMWr TLP. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" line.long 0x10 "DMA_WRITE_CH01_IMWR_DATA_OFF,DMA Write Channel 1 and 0 IMWr Data Register." hexmask.long.word 0x10 16.--31. 1. "WR_CHANNEL_1_DATA,The DMA uses this field to generate the data field for the Done or Abort IMWr TLPs it generates for write channel 1. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" hexmask.long.word 0x10 0.--15. 1. "WR_CHANNEL_0_DATA,The DMA uses this field to generate the data field for the Done or Abort IMWr TLPs it generates for write channel 0. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" line.long 0x14 "DMA_WRITE_CH23_IMWR_DATA_OFF,DMA Write Channel 3 and 2 IMWr Data Register." hexmask.long.word 0x14 16.--31. 1. "WR_CHANNEL_3_DATA,The DMA uses this field to generate the data field for the Done or Abort IMWr TLPs it generates for write channel 3. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" hexmask.long.word 0x14 0.--15. 1. "WR_CHANNEL_2_DATA,The DMA uses this field to generate the data field for the Done or Abort IMWr TLPs it generates for write channel 2. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" line.long 0x18 "DMA_WRITE_CH45_IMWR_DATA_OFF,DMA Write Channel 5 and 4 IMWr Data Register." hexmask.long.word 0x18 16.--31. 1. "WR_CHANNEL_5_DATA,The DMA uses this field to generate the data field for the Done or Abort IMWr TLPs it generates for write channel 5. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" hexmask.long.word 0x18 0.--15. 1. "WR_CHANNEL_4_DATA,The DMA uses this field to generate the data field for the Done or Abort IMWr TLPs it generates for write channel 4. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" line.long 0x1C "DMA_WRITE_CH67_IMWR_DATA_OFF,DMA Write Channel 7 and 6 IMWr Data Register." hexmask.long.word 0x1C 16.--31. 1. "WR_CHANNEL_7_DATA,The DMA uses this field to generate the data field for the Done or Abort IMWr TLPs it generates for write channel 7. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" hexmask.long.word 0x1C 0.--15. 1. "WR_CHANNEL_6_DATA,The DMA uses this field to generate the data field for the Done or Abort IMWr TLPs it generates for write channel 6. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" group.long (0x90+0xC8000)++0x3 line.long 0x0 "DMA_WRITE_LINKED_LIST_ERR_EN_OFF,DMA Write Linked List Error Enable Register. The LIE and RIE bits in the LL element enable the channel 'done' interrupts (local and remote). The LLLAIE and LLRAIE bits enable the channel 'abort' interrupts (local and.." hexmask.long.byte 0x0 24.--31. 1. "RSVDP_24,Reserved for future use." hexmask.long.byte 0x0 16.--23. 1. "WR_CHANNEL_LLLAIE,Write Channel LL Local Abort Interrupt Enable (LLLAIE). You enable the write channel local abort interrupt through this bit. The LIE and RIE bits in the LL element enable the write channel done interrupts. Each bit corresponds to a DMA.." newline hexmask.long.byte 0x0 8.--15. 1. "RSVDP_8,Reserved for future use." hexmask.long.byte 0x0 0.--7. 1. "WR_CHANNEL_LLRAIE,Write Channel LL Remote Abort Interrupt Enable (LLRAIE). You enable the write channel remote abort interrupt through this bit. The LIE and RIE bits in the LL element enable the write channel done interrupts. Each bit corresponds to a.." group.long (0xA0+0xC8000)++0x3 line.long 0x0 "DMA_READ_INT_STATUS_OFF,DMA Read Interrupt Status Register." hexmask.long.byte 0x0 24.--31. 1. "RSVDP_24,Reserved for future use." hexmask.long.byte 0x0 16.--23. 1. "RD_ABORT_INT_STATUS,Abort Interrupt Status. The DMA read channel has detected an error or you manually stopped the transfer as described in 'Stopping the DMA Transfer (Software Stop)'. Each bit corresponds to a DMA channel. Bit [0] corresponds to.." newline hexmask.long.byte 0x0 8.--15. 1. "RSVDP_8,Reserved for future use." hexmask.long.byte 0x0 0.--7. 1. "RD_DONE_INT_STATUS,Done Interrupt Status. The DMA read channel has successfully completed the DMA read transfer. Each bit corresponds to a DMA channel. Bit [0] corresponds to channel 0. - Enabling: For details see 'Interrupts and Error Handling'. -.." group.long (0xA8+0xC8000)++0x7 line.long 0x0 "DMA_READ_INT_MASK_OFF,DMA Read Interrupt Mask Register." hexmask.long.byte 0x0 24.--31. 1. "RSVDP_24,Reserved for future use." hexmask.long.byte 0x0 16.--23. 1. "RD_ABORT_INT_MASK,Abort Interrupt Mask. Prevents the Abort interrupt status field in the DMA read interrupt status register from asserting the edma_int output. Each bit corresponds to a DMA channel. Bit [0] corresponds to channel 0. Note: The access.." newline hexmask.long.byte 0x0 8.--15. 1. "RSVDP_8,Reserved for future use." hexmask.long.byte 0x0 0.--7. 1. "RD_DONE_INT_MASK,Done Interrupt Mask. Prevents the Done interrupt status field in the DMA read interrupt status register from asserting the edma_int output. Each bit corresponds to a DMA channel. Bit [0] corresponds to channel 0. Note: The access.." line.long 0x4 "DMA_READ_INT_CLEAR_OFF,DMA Read Interrupt Clear Register." hexmask.long.byte 0x4 24.--31. 1. "RSVDP_24,Reserved for future use." hexmask.long.byte 0x4 16.--23. 1. "RD_ABORT_INT_CLEAR,Abort Interrupt Clear. You must write a 1'b1 to clear the corresponding bit in the Abort interrupt status field of the DMA read interrupt status register. Each bit corresponds to a DMA channel. Bit [0] corresponds to channel 0. Note:.." newline hexmask.long.byte 0x4 8.--15. 1. "RSVDP_8,Reserved for future use." hexmask.long.byte 0x4 0.--7. 1. "RD_DONE_INT_CLEAR,Done Interrupt Clear. You must write a 1'b1 to clear the corresponding bit in the Done interrupt status field of the DMA read interrupt status register. Each bit corresponds to a DMA channel. Bit [0] corresponds to channel 0. Note:.." rgroup.long (0xB4+0xC8000)++0x7 line.long 0x0 "DMA_READ_ERR_STATUS_LOW_OFF,DMA Read Error Status Low Register." hexmask.long.byte 0x0 24.--31. 1. "RSVDP_24,Reserved for future use." hexmask.long.byte 0x0 16.--23. 1. "LINK_LIST_ELEMENT_FETCH_ERR_DETECT,Linked List Element Fetch Error Detected. - The DMA read channel has received an error response from the AXI bus while reading a linked list element from local memory. Each bit corresponds to a DMA channel. Bit [0].." newline hexmask.long.byte 0x0 8.--15. 1. "RSVDP_8,Reserved for future use." hexmask.long.byte 0x0 0.--7. 1. "APP_WR_ERR_DETECT,Application Write Error Detected. The DMA read channel has received an error response from the AXI bus (or TRGT1 interface when the AXI Bridge is not used) while writing data to it. This error is fatal. You must restart the transfer.." line.long 0x4 "DMA_READ_ERR_STATUS_HIGH_OFF,DMA Read Error Status High Register." hexmask.long.byte 0x4 24.--31. 1. "DATA_POISIONING,Data Poisoning. The DMA read channel has detected data poisoning in the completion from the remote device (in response to the MRd request). The DMA read channel will drop the completion and then be halted. The CX_FLT_MASK_UR_POIS filter.." hexmask.long.byte 0x4 16.--23. 1. "CPL_TIMEOUT,Completion Time Out. The DMA read channel has timed-out while waiting for the remote device to respond to the MRd request or a malformed CplD has been received. For more details see 'Linked List Mode'. Each bit corresponds to a DMA channel." newline hexmask.long.byte 0x4 8.--15. 1. "CPL_ABORT,Completer Abort. The DMA read channel has received a PCIe completer abort completion status from the remote device in response to the MRd request. For more details see 'Linked List Mode'. Each bit corresponds to a DMA channel. Bit [0].." hexmask.long.byte 0x4 0.--7. 1. "UNSUPPORTED_REQ,Unsupported Request. The DMA read channel has received a PCIe unsupported request completion status from the remote device in response to the MRd request. For more details see 'Linked List Mode'. Each bit corresponds to a DMA channel." group.long (0xC4+0xC8000)++0x3 line.long 0x0 "DMA_READ_LINKED_LIST_ERR_EN_OFF,DMA Read Linked List Error Enable Register. The LIE and RIE bits in the LL element enable the channel 'done' interrupts (local and remote). The LLLAIE and LLRAIE bits enable the channel 'abort' interrupts (local and remote)." hexmask.long.byte 0x0 24.--31. 1. "RSVDP_24,Reserved for future use." hexmask.long.byte 0x0 16.--23. 1. "RD_CHANNEL_LLLAIE,Read Channel LL Local Abort Interrupt Enable (LLLAIE). You enable the read channel Local Abort interrupt through this bit. The LIE and RIE bits in the LL element enable the read channel done interrupts. Each bit corresponds to a DMA.." newline hexmask.long.byte 0x0 8.--15. 1. "RSVDP_8,Reserved for future use." hexmask.long.byte 0x0 0.--7. 1. "RD_CHANNEL_LLRAIE,Read Channel LL Remote Abort Interrupt Enable (LLRAIE). You enable the read channel Remote Abort interrupt through this bit. The LIE and RIE bits in the LL element enable the read channel done interrupts. Each bit corresponds to a DMA.." group.long (0xCC+0xC8000)++0x1F line.long 0x0 "DMA_READ_DONE_IMWR_LOW_OFF,DMA Read Done IMWr Address Low Register." hexmask.long 0x0 0.--31. 1. "DMA_READ_DONE_LOW_REG,The DMA uses this field to generate bits [31:0] of the address field for the Done IMWr TLP. Bits [1:0] must be '00' as this address must be dword aligned. Note: The access attributes of this field are as follows: - Wire: No access." line.long 0x4 "DMA_READ_DONE_IMWR_HIGH_OFF,DMA Read Done IMWr Address High Register." hexmask.long 0x4 0.--31. 1. "DMA_READ_DONE_HIGH_REG,The DMA uses this field to generate bits [63:32] of the address field for the Done IMWr TLP. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" line.long 0x8 "DMA_READ_ABORT_IMWR_LOW_OFF,DMA Read Abort IMWr Address Low Register." hexmask.long 0x8 0.--31. 1. "DMA_READ_ABORT_LOW_REG,The DMA uses this field to generate bits [31:0] of the address field for the Abort IMWr TLP. Bits [1:0] must be '00' as this address must be dword aligned. Note: The access attributes of this field are as follows: - Wire: No.." line.long 0xC "DMA_READ_ABORT_IMWR_HIGH_OFF,DMA Read Abort IMWr Address High Register." hexmask.long 0xC 0.--31. 1. "DMA_READ_ABORT_HIGH_REG,The DMA uses this field to generate bits [63:32] of the address field for the Abort IMWr TLP. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" line.long 0x10 "DMA_READ_CH01_IMWR_DATA_OFF,DMA Read Channel 1 and 0 IMWr Data Register." hexmask.long.word 0x10 16.--31. 1. "RD_CHANNEL_1_DATA,The DMA uses this field to generate the data field for the Done or Abort IMWr TLPs it generates for read channel 1. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" hexmask.long.word 0x10 0.--15. 1. "RD_CHANNEL_0_DATA,The DMA uses this field to generate the data field for the Done or Abort IMWr TLPs it generates for read channel 0. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" line.long 0x14 "DMA_READ_CH23_IMWR_DATA_OFF,DMA Read Channel 3 and 2 IMWr Data Register." hexmask.long.word 0x14 16.--31. 1. "RD_CHANNEL_3_DATA,The DMA uses this field to generate the data field for the Done or Abort IMWr TLPs it generates for read channel 3. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" hexmask.long.word 0x14 0.--15. 1. "RD_CHANNEL_2_DATA,The DMA uses this field to generate the data field for the Done or Abort IMWr TLPs it generates for read channel 2. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" line.long 0x18 "DMA_READ_CH45_IMWR_DATA_OFF,DMA Read Channel 5 and 4 IMWr Data Register." hexmask.long.word 0x18 16.--31. 1. "RD_CHANNEL_5_DATA,The DMA uses this field to generate the data field for the Done or Abort IMWr TLPs it generates for read channel 5. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" hexmask.long.word 0x18 0.--15. 1. "RD_CHANNEL_4_DATA,The DMA uses this field to generate the data field for the Done or Abort IMWr TLPs it generates for read channel 4. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" line.long 0x1C "DMA_READ_CH67_IMWR_DATA_OFF,DMA Read Channel 7 and 6 IMWr Data Register." hexmask.long.word 0x1C 16.--31. 1. "RD_CHANNEL_7_DATA,The DMA uses this field to generate the data field for the Done or Abort IMWr TLPs it generates for read channel 7. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" hexmask.long.word 0x1C 0.--15. 1. "RD_CHANNEL_6_DATA,The DMA uses this field to generate the data field for the Done or Abort IMWr TLPs it generates for read channel 6. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" rgroup.long (0x108+0xC8000)++0x7 line.long 0x0 "DMA_WRITE_ENGINE_HSHAKE_CNT_LOW_OFF,DMA Write Engine Handshake Counter Channel 0/1/2/3 Register." bitfld.long 0x0 29.--31. "RSVDP_29,Reserved for future use." "0,1,2,3,4,5,6,7" hexmask.long.byte 0x0 24.--28. 1. "DMA_WRITE_ENGINE_HSHAKE_CNT_CH3,DMA handshake counter for DMA Write Engine Channel 3. If CC_DMA_HSHAKE =1 the data transfer in Linked List mode starts only when the counter is non-zero." newline bitfld.long 0x0 21.--23. "RSVDP_21,Reserved for future use." "0,1,2,3,4,5,6,7" hexmask.long.byte 0x0 16.--20. 1. "DMA_WRITE_ENGINE_HSHAKE_CNT_CH2,DMA handshake counter for DMA Write Engine Channel 2. If CC_DMA_HSHAKE =1 the data transfer in Linked List mode starts only when the counter is non-zero." newline bitfld.long 0x0 13.--15. "RSVDP_13,Reserved for future use." "0,1,2,3,4,5,6,7" hexmask.long.byte 0x0 8.--12. 1. "DMA_WRITE_ENGINE_HSHAKE_CNT_CH1,DMA handshake counter for DMA Write Engine Channel 1. If CC_DMA_HSHAKE =1 the data transfer in Linked List mode starts only when the counter is non-zero." newline bitfld.long 0x0 5.--7. "RSVDP_5,Reserved for future use." "0,1,2,3,4,5,6,7" hexmask.long.byte 0x0 0.--4. 1. "DMA_WRITE_ENGINE_HSHAKE_CNT_CH0,DMA handshake counter for DMA Write Engine Channel 0. If CC_DMA_HSHAKE =1 the data transfer in Linked List mode starts only when the counter is non-zero." line.long 0x4 "DMA_WRITE_ENGINE_HSHAKE_CNT_HIGH_OFF,DMA Write Engine Handshake Counter Channel 4/5/6/7 Register." bitfld.long 0x4 29.--31. "RSVDP_29,Reserved for future use." "0,1,2,3,4,5,6,7" hexmask.long.byte 0x4 24.--28. 1. "DMA_WRITE_ENGINE_HSHAKE_CNT_CH7,DMA handshake counter for DMA Write Engine Channel 7. If CC_DMA_HSHAKE =1 the data transfer in Linked List mode starts only when the counter is non-zero." newline bitfld.long 0x4 21.--23. "RSVDP_21,Reserved for future use." "0,1,2,3,4,5,6,7" hexmask.long.byte 0x4 16.--20. 1. "DMA_WRITE_ENGINE_HSHAKE_CNT_CH6,DMA handshake counter for DMA Write Engine Channel 6. If CC_DMA_HSHAKE =1 the data transfer in Linked List mode starts only when the counter is non-zero." newline bitfld.long 0x4 13.--15. "RSVDP_13,Reserved for future use." "0,1,2,3,4,5,6,7" hexmask.long.byte 0x4 8.--12. 1. "DMA_WRITE_ENGINE_HSHAKE_CNT_CH5,DMA handshake counter for DMA Write Engine Channel 5. If CC_DMA_HSHAKE =1 the data transfer in Linked List mode starts only when the counter is non-zero." newline bitfld.long 0x4 5.--7. "RSVDP_5,Reserved for future use." "0,1,2,3,4,5,6,7" hexmask.long.byte 0x4 0.--4. 1. "DMA_WRITE_ENGINE_HSHAKE_CNT_CH4,DMA handshake counter for DMA Write Engine Channel 4. If CC_DMA_HSHAKE =1 the data transfer in Linked List mode starts only when the counter is non-zero." rgroup.long (0x118+0xC8000)++0x7 line.long 0x0 "DMA_READ_ENGINE_HSHAKE_CNT_LOW_OFF,DMA Read Engine Handshake Counter Channel 0/1/2/3 Register." bitfld.long 0x0 29.--31. "RSVDP_29,Reserved for future use." "0,1,2,3,4,5,6,7" hexmask.long.byte 0x0 24.--28. 1. "DMA_READ_ENGINE_HSHAKE_CNT_CH3,DMA handshake counter for DMA Read Engine Channel 3. If CC_DMA_HSHAKE =1 the data transfer in Linked List mode starts only when the counter is non-zero." newline bitfld.long 0x0 21.--23. "RSVDP_21,Reserved for future use." "0,1,2,3,4,5,6,7" hexmask.long.byte 0x0 16.--20. 1. "DMA_READ_ENGINE_HSHAKE_CNT_CH2,DMA handshake counter for DMA Read Engine Channel 2. If CC_DMA_HSHAKE =1 the data transfer in Linked List mode starts only when the counter is non-zero." newline bitfld.long 0x0 13.--15. "RSVDP_13,Reserved for future use." "0,1,2,3,4,5,6,7" hexmask.long.byte 0x0 8.--12. 1. "DMA_READ_ENGINE_HSHAKE_CNT_CH1,DMA handshake counter for DMA Read Engine Channel 1. If CC_DMA_HSHAKE =1 the data transfer in Linked List mode starts only when the counter is non-zero." newline bitfld.long 0x0 5.--7. "RSVDP_5,Reserved for future use." "0,1,2,3,4,5,6,7" hexmask.long.byte 0x0 0.--4. 1. "DMA_READ_ENGINE_HSHAKE_CNT_CH0,DMA handshake counter for DMA Read Engine Channel 0. If CC_DMA_HSHAKE =1 the data transfer in Linked List mode starts only when the counter is non-zero." line.long 0x4 "DMA_READ_ENGINE_HSHAKE_CNT_HIGH_OFF,DMA Read Engine Handshake Counter Channel 4/5/6/7 Register." bitfld.long 0x4 29.--31. "RSVDP_29,Reserved for future use." "0,1,2,3,4,5,6,7" hexmask.long.byte 0x4 24.--28. 1. "DMA_READ_ENGINE_HSHAKE_CNT_CH7,DMA handshake counter for DMA Read Engine Channel 7. If CC_DMA_HSHAKE =1 the data transfer in Linked List mode starts only when the counter is non-zero." newline bitfld.long 0x4 21.--23. "RSVDP_21,Reserved for future use." "0,1,2,3,4,5,6,7" hexmask.long.byte 0x4 16.--20. 1. "DMA_READ_ENGINE_HSHAKE_CNT_CH6,DMA handshake counter for DMA Read Engine Channel 6. If CC_DMA_HSHAKE =1 the data transfer in Linked List mode starts only when the counter is non-zero." newline bitfld.long 0x4 13.--15. "RSVDP_13,Reserved for future use." "0,1,2,3,4,5,6,7" hexmask.long.byte 0x4 8.--12. 1. "DMA_READ_ENGINE_HSHAKE_CNT_CH5,DMA handshake counter for DMA Read Engine Channel 5. If CC_DMA_HSHAKE =1 the data transfer in Linked List mode starts only when the counter is non-zero." newline bitfld.long 0x4 5.--7. "RSVDP_5,Reserved for future use." "0,1,2,3,4,5,6,7" hexmask.long.byte 0x4 0.--4. 1. "DMA_READ_ENGINE_HSHAKE_CNT_CH4,DMA handshake counter for DMA Read Engine Channel 4. If CC_DMA_HSHAKE =1 the data transfer in Linked List mode starts only when the counter is non-zero." repeat 8. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 )(list 0x0 0x200 0x400 0x600 0x800 0xA00 0xC00 0xE00 ) group.long ($2+0x200+0xC8000)++0x3 line.long 0x0 "DMA_CH_CONTROL1_OFF_WRCH_$1,DMA Write Channel Control 1 Register." bitfld.long 0x0 30.--31. "DMA_AT,Address Translation TLP Header Bit (AT) The DMA uses this TLP header field when generating MRd/MWr (not IMWr) TLPs. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" "0,1,2,3" bitfld.long 0x0 27.--29. "DMA_TC,Traffic Class TLP Header Bit (TC) The DMA uses this TLP header field when generating MRd/MWr (not IMWr) TLPs. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 26. "DMA_RESERVED5,Reserved. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" "0,1" bitfld.long 0x0 25. "DMA_RO,Relaxed Ordering TLP Header Bit (RO) The DMA uses this TLP header field when generating MRd/MWr (not IMWr) TLPs. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" "0,1" newline bitfld.long 0x0 24. "DMA_NS_SRC,Source No Snoop TLP Header Bit (DMA_NS_SRC). The DMA uses this TLP header field when generating MRd (SAR addressing space) (not IMWr) TLPs. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" "0,1" bitfld.long 0x0 23. "DMA_NS_DST,Destination No Snoop TLP Header Bit (DMA_NS_DST). The DMA uses this TLP header field when generating MWr (DAR addressing space) (not IMWr) TLPs. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" "0,1" newline bitfld.long 0x0 22. "DMA_MEM_TYPE,Master AXI ACE-Lite Cache Coherency Control. This field sets the DMA channel memory type of the address space of the data transfer as follows: - 0x0:peripheral type - 0x1:memory type For more details see 'ACE-Lite Features and Limitations'.." "peripheral type,memory type" hexmask.long.byte 0x0 17.--21. 1. "DMA_RESERVED2,Reserved. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" newline hexmask.long.byte 0x0 12.--16. 1. "DMA_FUNC_NUM,Function Number (FN). The controller uses this field when generating the requester ID for the MRd/MWr DMA TLP. When you have enabled SR-IOV then this field is ignored if you have set the VFE field in the 'DMA Write Channel Control 2.." bitfld.long 0x0 10.--11. "DMA_RESERVED1,Reserved. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" "0,1,2,3" newline bitfld.long 0x0 9. "LLE,Linked List Enable (LLE). - 0: Disable linked list operation - 1: Enable linked list operation Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" "Disable linked list operation,Enable linked list operation" bitfld.long 0x0 8. "CCS,Consumer Cycle State (CCS). Used in linked list mode only. It is used to synchronize the producer (software) and the consumer (DMA). For more details see 'PCS-CCS-CB-TCB Producer-Consumer Synchronization'. You must initialize this bit. The DMA.." "0,1" newline bitfld.long 0x0 7. "DMA_RESERVED0,Reserved. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" "0,1" bitfld.long 0x0 5.--6. "CS,Channel Status (CS). The channel status bits identify the current operational state of the DMA channel. The operation state encoding for each DMA channel is a s follows: - 00: Reserved - 01: Running. This channel is active and transferring data. - 10:.." "Reserved,Running,?,?" newline bitfld.long 0x0 4. "RIE,Remote Interrupt Enable (RIE). You must set this bit to enable the generation of the Done or Abort Remote interrupts. For more details see 'Interrupts and Error Handling'. In LL mode the DMA overwrites this with the RIE of the LL element. The RIE.." "0,1" bitfld.long 0x0 3. "LIE,Local Interrupt Enable (LIE). You must set this bit to enable the generation of the Done or Abort Local interrupts. For more details see 'Interrupts and Error Handling'. In LL mode the DMA overwrites this with the LIE of the LL element. The LIE bit.." "0,1" newline bitfld.long 0x0 2. "LLP,Load Link Pointer (LLP). Used in linked list mode only. Indicates that this linked list element is a link element and its LL element pointer dwords are pointing to the next (non-contiguous) element. The DMA loads this field with the LLP of the.." "0,1" bitfld.long 0x0 1. "TCB,Toggle Cycle Bit (TCB). Indicates to the DMA to toggle its interpretation of the CB. Used in linked list mode only. It is used to synchronize the producer (software) and the consumer (DMA). For more details see 'PCS-CCS-CB-TCB Producer-Consumer.." "0,1" newline bitfld.long 0x0 0. "CB,Cycle Bit (CB). Used in linked list mode only. It is used to synchronize the producer (software) and the consumer (DMA). For more details see 'PCS-CCS-CB-TCB Producer-Consumer Synchronization'. The DMA loads this field with the CB of the linked list.." "0,1" repeat.end repeat 8. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 )(list 0x0 0x200 0x400 0x600 0x800 0xA00 0xC00 0xE00 ) group.long ($2+0x208+0xC8000)++0x3 line.long 0x0 "DMA_TRANSFER_SIZE_OFF_WRCH_$1,DMA Write Transfer Size Register." hexmask.long 0x0 0.--31. 1. "DMA_TRANSFER_SIZE,DMA Transfer Size. You program this register with the size of the DMA transfer. The maximum DMA transfer size is 4Gbytes. The minimum transfer size is one byte (0x1). This field is automatically decremented by the DMA as the DMA write.." repeat.end repeat 8. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 )(list 0x0 0x200 0x400 0x600 0x800 0xA00 0xC00 0xE00 ) group.long ($2+0x20C+0xC8000)++0x3 line.long 0x0 "DMA_SAR_LOW_OFF_WRCH_$1,DMA Write SAR Low Register." hexmask.long 0x0 0.--31. 1. "SRC_ADDR_REG_LOW,Source Address Register (Lower 32 bits). Indicates the next address to be read from. The DMA increments the SAR as the DMA transfer progresses. In LL mode the DMA overwrites this with the corresponding dword of the LL element. - DMA.." repeat.end repeat 8. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 )(list 0x0 0x200 0x400 0x600 0x800 0xA00 0xC00 0xE00 ) group.long ($2+0x210+0xC8000)++0x3 line.long 0x0 "DMA_SAR_HIGH_OFF_WRCH_$1,DMA Write SAR High Register." hexmask.long 0x0 0.--31. 1. "SRC_ADDR_REG_HIGH,Source Address Register (Higher 32 bits). In LL mode the DMA overwrites this with the corresponding dword of the LL element. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" repeat.end repeat 8. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 )(list 0x0 0x200 0x400 0x600 0x800 0xA00 0xC00 0xE00 ) group.long ($2+0x214+0xC8000)++0x3 line.long 0x0 "DMA_DAR_LOW_OFF_WRCH_$1,DMA Write DAR Low Register." hexmask.long 0x0 0.--31. 1. "DST_ADDR_REG_LOW,Destination Address Register (Lower 32 bits). Indicates the next address to be written to. The DMA increments the DAR as the DMA transfer progresses. In LL mode the DMA overwrites this with the corresponding dword of the LL element. -.." repeat.end repeat 8. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 )(list 0x0 0x200 0x400 0x600 0x800 0xA00 0xC00 0xE00 ) group.long ($2+0x218+0xC8000)++0x3 line.long 0x0 "DMA_DAR_HIGH_OFF_WRCH_$1,DMA Write DAR High Register." hexmask.long 0x0 0.--31. 1. "DST_ADDR_REG_HIGH,Destination Address Register (Higher 32 bits). In LL mode the DMA overwrites this with the corresponding dword of the LL element. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" repeat.end repeat 8. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 )(list 0x0 0x200 0x400 0x600 0x800 0xA00 0xC00 0xE00 ) group.long ($2+0x21C+0xC8000)++0x3 line.long 0x0 "DMA_LLP_LOW_OFF_WRCH_$1,DMA Write Linked List Pointer Low Register." hexmask.long 0x0 0.--31. 1. "LLP_LOW,Lower bits of the address of the linked list transfer list in local memory. Used in linked list mode only. Updated by the DMA to point to the next element in the transfer list after the previous element is consumed. - When the current element is.." repeat.end repeat 8. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 )(list 0x0 0x200 0x400 0x600 0x800 0xA00 0xC00 0xE00 ) group.long ($2+0x220+0xC8000)++0x3 line.long 0x0 "DMA_LLP_HIGH_OFF_WRCH_$1,DMA Write Linked List Pointer High Register." hexmask.long 0x0 0.--31. 1. "LLP_HIGH,Upper 32 bits of the address of the linked list transfer list in local memory. Used in linked list mode only. Updated by the DMA to point to the next element in the transfer list as elements are consumed. Note: The access attributes of this.." repeat.end repeat 8. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 )(list 0x0 0x200 0x400 0x600 0x800 0xA00 0xC00 0xE00 ) group.long ($2+0x300+0xC8000)++0x3 line.long 0x0 "DMA_CH_CONTROL1_OFF_RDCH_$1,DMA Read Channel Control 1 Register." bitfld.long 0x0 30.--31. "DMA_AT,Address Translation TLP Header Bit (AT) The DMA uses this TLP header field when generating MRd/MWr (not IMWr) TLPs. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" "0,1,2,3" bitfld.long 0x0 27.--29. "DMA_TC,Traffic Class TLP Header Bit (TC) The DMA uses this TLP header field when generating MRd/MWr (not IMWr) TLPs. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 26. "DMA_RESERVED5,Reserved. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" "0,1" bitfld.long 0x0 25. "DMA_RO,Relaxed Ordering TLP Header Bit (RO) The DMA uses this TLP header field when generating MRd/MWr (not IMWr) TLPs. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" "0,1" newline bitfld.long 0x0 24. "DMA_NS_SRC,Source No Snoop TLP Header Bit (DMA_NS_SRC). The DMA uses this TLP header field when generating MRd (SAR addressing space) (not IMWr) TLPs. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" "0,1" bitfld.long 0x0 23. "DMA_NS_DST,Destination No Snoop TLP Header Bit (DMA_NS_DST). The DMA uses this TLP header field when generating MWr (DAR addressing space) (not IMWr) TLPs. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" "0,1" newline bitfld.long 0x0 22. "DMA_MEM_TYPE,Master AXI ACE-Lite Cache Coherency Control. This field sets the DMA channel memory type of the address space of the data transfer as follows: - 0x0:peripheral type - 0x1:memory type For more details see 'ACE-Lite Features and Limitations'.." "peripheral type,memory type" hexmask.long.byte 0x0 17.--21. 1. "DMA_RESERVED2,Reserved. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" newline hexmask.long.byte 0x0 12.--16. 1. "DMA_FUNC_NUM,Function Number (FN). The controller uses this field when generating the requester ID for the MRd/MWr DMA TLP. When you have enabled SR-IOV then this field is ignored if you have set the VFE field in the 'DMA Read Channel Control 2.." bitfld.long 0x0 10.--11. "DMA_RESERVED1,Reserved. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" "0,1,2,3" newline bitfld.long 0x0 9. "LLE,Linked List Enable (LLE). - 0: Disable linked list operation - 1: Enable linked list operation Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" "Disable linked list operation,Enable linked list operation" bitfld.long 0x0 8. "CCS,Consumer Cycle State (CCS). Used in linked list mode only. It is used to synchronize the producer (software) and the consumer (DMA). For more details see 'PCS-CCS-CB-TCB Producer-Consumer Synchronization'. You must initialize this bit. The DMA.." "0,1" newline bitfld.long 0x0 7. "DMA_RESERVED0,Reserved. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" "0,1" bitfld.long 0x0 5.--6. "CS,Channel Status (CS). The channel status bits identify the current operational state of the DMA channel. The operation state encoding for each DMA channel is a s follows: - 00: Reserved - 01: Running. This channel is active and transferring data. - 10:.." "Reserved,Running,?,?" newline bitfld.long 0x0 4. "RIE,Remote Interrupt Enable (RIE). You must set this bit to enable the generation of the Done or Abort Remote interrupts. For more details see 'Interrupts and Error Handling'. In LL mode the DMA overwrites this with the RIE of the LL element. The RIE.." "0,1" bitfld.long 0x0 3. "LIE,Local Interrupt Enable (LIE). You must set this bit to enable the generation of the Done or Abort Local interrupts. For more details see 'Interrupts and Error Handling'. In LL mode the DMA overwrites this with the LIE of the LL element. The LIE bit.." "0,1" newline bitfld.long 0x0 2. "LLP,Load Link Pointer (LLP). Used in linked list mode only. Indicates that this linked list element is a link element and its LL element pointer dwords are pointing to the next (non-contiguous) element. The DMA loads this field with the LLP of the.." "0,1" bitfld.long 0x0 1. "TCB,Toggle Cycle Bit (TCB). Indicates to the DMA to toggle its interpretation of the CB. Used in linked list mode only. It is used to synchronize the producer (software) and the consumer (DMA). For more details see 'PCS-CCS-CB-TCB Producer-Consumer.." "0,1" newline bitfld.long 0x0 0. "CB,Cycle Bit (CB). Used in linked list mode only. It is used to synchronize the producer (software) and the consumer (DMA). For more details see 'PCS-CCS-CB-TCB Producer-Consumer Synchronization'. The DMA loads this field with the CB of the linked list.." "0,1" repeat.end repeat 8. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 )(list 0x0 0x200 0x400 0x600 0x800 0xA00 0xC00 0xE00 ) group.long ($2+0x308+0xC8000)++0x3 line.long 0x0 "DMA_TRANSFER_SIZE_OFF_RDCH_$1,DMA Read Transfer Size Register." hexmask.long 0x0 0.--31. 1. "DMA_TRANSFER_SIZE,DMA Transfer Size. You program this register with the size of the DMA transfer. The maximum DMA transfer size is 4Gbytes. The minimum transfer size is one byte (0x1). This field is automatically decremented by the DMA as the DMA read.." repeat.end repeat 8. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 )(list 0x0 0x200 0x400 0x600 0x800 0xA00 0xC00 0xE00 ) group.long ($2+0x30C+0xC8000)++0x3 line.long 0x0 "DMA_SAR_LOW_OFF_RDCH_$1,DMA Read SAR Low Register." hexmask.long 0x0 0.--31. 1. "SRC_ADDR_REG_LOW,Source Address Register (Lower 32 bits). Indicates the next address to be read from. The DMA increments the SAR as the DMA transfer progresses. In LL mode the DMA overwrites this with the corresponding dword of the LL element. - DMA.." repeat.end repeat 8. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 )(list 0x0 0x200 0x400 0x600 0x800 0xA00 0xC00 0xE00 ) group.long ($2+0x310+0xC8000)++0x3 line.long 0x0 "DMA_SAR_HIGH_OFF_RDCH_$1,DMA Read SAR High Register." hexmask.long 0x0 0.--31. 1. "SRC_ADDR_REG_HIGH,Source Address Register (Higher 32 bits). In LL mode the DMA overwrites this with the corresponding dword of the LL element. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" repeat.end repeat 8. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 )(list 0x0 0x200 0x400 0x600 0x800 0xA00 0xC00 0xE00 ) group.long ($2+0x314+0xC8000)++0x3 line.long 0x0 "DMA_DAR_LOW_OFF_RDCH_$1,DMA Read DAR Low Register." hexmask.long 0x0 0.--31. 1. "DST_ADDR_REG_LOW,Destination Address Register (Lower 32 bits). Indicates the next address to be written to. The DMA increments the DAR as the DMA transfer progresses. In LL mode the DMA overwrites this with the corresponding dword of the LL element. -.." repeat.end repeat 8. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 )(list 0x0 0x200 0x400 0x600 0x800 0xA00 0xC00 0xE00 ) group.long ($2+0x318+0xC8000)++0x3 line.long 0x0 "DMA_DAR_HIGH_OFF_RDCH_$1,DMA Read DAR High Register." hexmask.long 0x0 0.--31. 1. "DST_ADDR_REG_HIGH,Destination Address Register (Higher 32 bits). In LL mode the DMA overwrites this with the corresponding dword of the LL element. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" repeat.end repeat 8. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 )(list 0x0 0x200 0x400 0x600 0x800 0xA00 0xC00 0xE00 ) group.long ($2+0x31C+0xC8000)++0x3 line.long 0x0 "DMA_LLP_LOW_OFF_RDCH_$1,DMA Read Linked List Pointer Low Register." hexmask.long 0x0 0.--31. 1. "LLP_LOW,Lower bits of the address of the linked list transfer list in local memory. Used in linked list mode only. Updated by the DMA to point to the next element in the transfer list after the previous element is consumed. - When the current element is.." repeat.end repeat 8. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 )(list 0x0 0x200 0x400 0x600 0x800 0xA00 0xC00 0xE00 ) group.long ($2+0x320+0xC8000)++0x3 line.long 0x0 "DMA_LLP_HIGH_OFF_RDCH_$1,DMA Read Linked List Pointer High Register." hexmask.long 0x0 0.--31. 1. "LLP_HIGH,Upper 32 bits of the address of the linked list transfer list in local memory. Used in linked list mode only. Updated by the DMA to point to the next element in the transfer list as elements are consumed. Note: The access attributes of this.." repeat.end tree.end tree "PF0_ATU_CAP (ATU Por Logic Structure)" repeat 8. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 )(list 0x0 0x200 0x400 0x600 0x800 0xA00 0xC00 0xE00 ) group.long ($2+0xC0000)++0x3 line.long 0x0 "IATU_REGION_CTRL_1_OFF_OUTBOUND_$1,iATU Region Control 1 Register." bitfld.long 0x0 20. "CTRL_1_FUNC_NUM,Function Number. - When the address of an outbound TLP is matched to this region and the FUNC_BYPASS field in the 'iATU Control 2 Register' is '0' then the function number used in generating the function part of the requester ID (RID).." "0,1" newline bitfld.long 0x0 13. "INCREASE_REGION_SIZE,Increase the maximum ATU Region size. When set the maximum ATU Region size is determined by CX_ATU_MAX_REGION_SIZE. When clear the maximum ATU Region size is 4 GB (default). Note: This register field is sticky." "0,1" newline bitfld.long 0x0 9.--10. "ATTR,When the address of an outbound TLP is matched to this region then the ATTR field of the TLP is changed to the value in this register. Note: This register field is sticky." "0,1,2,3" newline bitfld.long 0x0 8. "TD,This is a reserved field. Do not use. Note: This register field is sticky." "0,1" newline bitfld.long 0x0 5.--7. "TC,When the address of an outbound TLP is matched to this region then the TC field of the TLP is changed to the value in this register. Note: This register field is sticky." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x0 0.--4. 1. "TYPE,When the address of an outbound TLP is matched to this region then the TYPE field of the TLP is changed to the value in this register. Note: This register field is sticky." repeat.end repeat 8. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 )(list 0x0 0x200 0x400 0x600 0x800 0xA00 0xC00 0xE00 ) group.long ($2+0x4+0xC0000)++0x3 line.long 0x0 "IATU_REGION_CTRL_2_OFF_OUTBOUND_$1,iATU Region Control 2 Register." bitfld.long 0x0 31. "REGION_EN,Region Enable. This bit must be set to '1' for address translation to take place. Note: This register field is sticky." "0,1" newline bitfld.long 0x0 29. "INVERT_MODE,Invert Mode. When set the address matching region is inverted. Therefore an address match occurs when the untranslated address is in the region outside the defined range (Base Address to Limit Address). Note: This register field is sticky." "0,1" newline bitfld.long 0x0 28. "CFG_SHIFT_MODE,CFG Shift Mode. The iATU uses bits [27:12] of the untranslated address (on the XALI0/1/2 interface or AXI slave interface address) to form the BDF number of the outgoing CFG TLP. This supports the Enhanced Configuration Address Mapping.." "0,1" newline bitfld.long 0x0 27. "DMA_BYPASS,DMA Bypass Mode. Allows request TLPs which are initiated by the DMA controller to pass through the iATU untranslated. Note: This field is reserved for the SW product. You must set it to '0'. Note: This register field is sticky." "0,1" newline bitfld.long 0x0 23. "HEADER_SUBSTITUTE_EN,Header Substitute Enable. When enabled and region address is matched the iATU fully substitutes bytes 8-11 (for 3 DWORD header) or bytes 12-15 (for 4 DWORD header) of the outbound TLP header with the contents of the LWR_TARGET_RW.." "LWR_TARGET_RW in the..,LWR_TARGET_RW in the.." newline bitfld.long 0x0 22. "INHIBIT_PAYLOAD,Inhibit TLP Payload Data for TLP's in Matched Region; assign iATU region to be TLP without data. When enabled and region address is matched the iATU marks all TLPs as having no payload data by forcing the TLP header Fmt[1] bit =0.." "Fmt[1] =0/1 so that TLPs with or without data..,Fmt[1] =0 so that only TLP type without data is.." newline bitfld.long 0x0 21. "TLP_HEADER_FIELDS_BYPASS,TLP Header Fields Translation Bypass. In this mode header fields of the translated TLP is taken from your application transmit interface or if AMBA is configured from the AMBA sideband bus (slv_awmisc_info) and not from the.." "0,1" newline bitfld.long 0x0 20. "SNP,Serialize Non-Posted Requests. In this mode when the AXI Bridge is populated same AXI ID Non-Posted Read/Write Requests are transmitted on the wire if there are no other same ID Non-Posted Requests outstanding. Note: This register field is sticky." "0,1" newline bitfld.long 0x0 19. "FUNC_BYPASS,Function Number Translation Bypass. In this mode the function number of the translated TLP is taken from your application transmit interface and not from the CTRL_1_FUNC_NUM field of the 'iATU Control 1 Register' or the VF_NUMBER field of.." "0,1" newline bitfld.long 0x0 16. "TAG_SUBSTITUTE_EN,TAG Substitute Enable. When enabled and region address is matched the iATU substitutes the TAG field of the outbound TLP header with the contents of the TAG field in this register. The expected usage scenario is translation from AXI.." "0,1" newline hexmask.long.byte 0x0 8.--15. 1. "TAG,TAG. The substituted TAG field (byte 6) in the outgoing TLP header when TAG_SUBSTITUTE_EN is set. Note: This register field is sticky." newline hexmask.long.byte 0x0 0.--7. 1. "MSG_CODE,MSG TLPs (Message Code). When the address of an outbound TLP is matched to this region and the translated TLP TYPE field is Msg or MsgD; then the message field of the TLP is changed to the value in this register. Memory TLPs: (ST;Steering Tag)." repeat.end repeat 8. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 )(list 0x0 0x200 0x400 0x600 0x800 0xA00 0xC00 0xE00 ) group.long ($2+0x8+0xC0000)++0x3 line.long 0x0 "IATU_LWR_BASE_ADDR_OFF_OUTBOUND_$1,iATU Lower Base Address Register. The CX_ATU_MIN_REGION_SIZE configuration parameter (Value Range: 4 kB. 8 kB. 16 kB. 32 kB. 64 kB defaults to 64 kB) specifies the minimum size of an address translation region. For.." hexmask.long.tbyte 0x0 12.--31. 1. "LWR_BASE_RW,Forms bits [31:n] of the start address of the address region to be translated. n is log2(CX_ATU_MIN_REGION_SIZE) Note: This register field is sticky." newline hexmask.long.word 0x0 0.--11. 1. "LWR_BASE_HW,Forms bits [n-1:0] of the start address of the address region to be translated. The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary so these bits are always 0. A write to this location is ignored by the PCIe controller." repeat.end repeat 8. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 )(list 0x0 0x200 0x400 0x600 0x800 0xA00 0xC00 0xE00 ) group.long ($2+0xC+0xC0000)++0x3 line.long 0x0 "IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_$1,iATU Upper Base Address Register." hexmask.long 0x0 0.--31. 1. "UPPER_BASE_RW,Forms bits [63:32] of the start (and end) address of the address region to be translated. In systems with a 32-bit address space this register is not used and therefore writing to this register has no effect. Note: This register field is.." repeat.end repeat 8. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 )(list 0x0 0x200 0x400 0x600 0x800 0xA00 0xC00 0xE00 ) group.long ($2+0x10+0xC0000)++0x3 line.long 0x0 "IATU_LIMIT_ADDR_OFF_OUTBOUND_$1,iATU Limit Address Register." hexmask.long.tbyte 0x0 12.--31. 1. "LIMIT_ADDR_RW,Forms upper bits of the end address of the address region to be translated. Note: This register field is sticky." newline hexmask.long.word 0x0 0.--11. 1. "LIMIT_ADDR_HW,Forms lower bits of the end address of the address region to be translated. The end address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary so these bits are always all ones. A write to this location is ignored by the PCIe.." repeat.end repeat 8. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 )(list 0x0 0x200 0x400 0x600 0x800 0xA00 0xC00 0xE00 ) group.long ($2+0x14+0xC0000)++0x3 line.long 0x0 "IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_$1,iATU Lower Target Address Register." hexmask.long 0x0 0.--31. 1. "LWR_TARGET_RW_OUTBOUND,When HEADER_SUBSTITUTE_EN in IATU_REGION_CTRL_2_OFF_OUTBOUND_ is '0' (normal operation): - LWR_TARGET_RW[31:n] forms MSB's of the Lower Target part of the new address of the translated region; - LWR_TARGET_RW[n-1:0] are not used." repeat.end repeat 8. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 )(list 0x0 0x200 0x400 0x600 0x800 0xA00 0xC00 0xE00 ) group.long ($2+0x18+0xC0000)++0x3 line.long 0x0 "IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_$1,iATU Upper Target Address Register." hexmask.long 0x0 0.--31. 1. "UPPER_TARGET_RW,Forms bits [63:32] of the start address (Upper Target part) of the new address of the translated region. Note: This register field is sticky." repeat.end repeat 8. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 )(list 0x0 0x200 0x400 0x600 0x800 0xA00 0xC00 0xE00 ) group.long ($2+0x1C+0xC0000)++0x3 line.long 0x0 "IATU_REGION_CTRL_3_OFF_OUTBOUND_$1,iATU Region Control 3 Register." bitfld.long 0x0 31. "VF_ACTIVE,Virtual Function Active. Indicates that all of the outbound accesses are from virtual functions. For more details see VF_ACTIVE field. Note: This register field is sticky." "0,1" newline hexmask.long 0x0 3.--30. 1. "RSVDP_VF_NUMBER,Reserved for future use." newline bitfld.long 0x0 0.--2. "VF_NUMBER,Virtual Function Number. When the address of an outbound TLP is matched to this region and the FUNC_BYPASS field in the 'iATU Control 2 Register' is '0' then this field used in generating the Function part of the requester ID (RID) field of.." "0,1,2,3,4,5,6,7" repeat.end repeat 8. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 )(list 0x0 0x200 0x400 0x600 0x800 0xA00 0xC00 0xE00 ) group.long ($2+0x100+0xC0000)++0x3 line.long 0x0 "IATU_REGION_CTRL_1_OFF_INBOUND_$1,iATU Region Control 1 Register." bitfld.long 0x0 20. "CTRL_1_FUNC_NUM,Function Number. - MEM-I/O: When the Address and BAR matching logic in the controller indicate that a MEM-I/O transaction matches a BAR in the function corresponding to this value then address translation proceeds. This check is only.." "?,When the destination function number as.." newline bitfld.long 0x0 13. "INCREASE_REGION_SIZE,Increase the maximum ATU Region size. When set the maximum ATU Region size is determined by CX_ATU_MAX_REGION_SIZE. When clear the maximum ATU Region size is 4 GB (default). Note: This register field is sticky." "0,1" newline bitfld.long 0x0 9.--10. "ATTR,When the ATTR field of an inbound TLP is matched to this value then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the 'ATTR Match Enable' bit of the 'iATU Control 2 Register' is.." "0,1,2,3" newline bitfld.long 0x0 8. "TD,When the TD field of an inbound TLP is matched to this value then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the 'TD Match Enable' bit of the 'iATU Control 2 Register' is set." "0,1" newline bitfld.long 0x0 5.--7. "TC,When the TC field of an inbound TLP is matched to this value then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the 'TC Match Enable' bit of the 'iATU Control 2 Register' is set." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x0 0.--4. 1. "TYPE,When the TYPE field of an inbound TLP is matched to this value then address translation proceeds (when all other enabled field-matches are successful). Note: This register field is sticky." repeat.end repeat 8. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 )(list 0x0 0x200 0x400 0x600 0x800 0xA00 0xC00 0xE00 ) group.long ($2+0x104+0xC0000)++0x3 line.long 0x0 "IATU_REGION_CTRL_2_OFF_INBOUND_$1,iATU Region Control 2 Register." bitfld.long 0x0 31. "REGION_EN,Region Enable. This bit must be set to '1' for address translation to take place. Note: This register field is sticky." "0,1" newline bitfld.long 0x0 30. "MATCH_MODE,Match Mode. Determines Inbound matching mode for TLPs. The mode depends on the type of TLP that is received as follows: For MEM-I/O TLPs this field is interpreted as follows: - 0: Address Match Mode. The iATU operates using addresses as in.." "Address Match Mode,Vendor ID Match Mode" newline bitfld.long 0x0 29. "INVERT_MODE,Invert Mode. When set the address matching region is inverted. Therefore an address match occurs when the untranslated address is in the region outside the defined range (Base Address to Limit Address). Note: This register field is sticky." "0,1" newline bitfld.long 0x0 28. "CFG_SHIFT_MODE,CFG Shift Mode. This is useful for CFG transactions where the PCIe configuration mechanism maps bits [27:12] of the address to the bus/device and function number. This allows a CFG configuration space to be located in any 256MB window of.." "0,1" newline bitfld.long 0x0 27. "FUZZY_TYPE_MATCH_CODE,Fuzzy Type Match Mode. When enabled the iATU relaxes the matching of the TLP TYPE field against the expected TYPE field so that - CfgRd0 and CfgRd1 TLPs are seen as identical. Similarly with CfgWr0 and CfgWr1. - MWr MRd and MRdLk.." "0,1" newline bitfld.long 0x0 26. "VFBAR_MATCH_MODE_EN,VF BAR Match Mode enable. When set Virtual Function BAR matching is used which allows all VFs in a PF which match a BAR to be matched with a single ATU region. Note: This register field is sticky." "0,1" newline bitfld.long 0x0 24.--25. "RESPONSE_CODE,Response Code. Defines the type of response to give for accesses matching this region. This overrides the normal RADM filter response. Note that this feature is not available for any region where Single Address Location Translate is.." "Normal RADM filter response is used,Unsupported request,?,?" newline bitfld.long 0x0 23. "SINGLE_ADDR_LOC_TRANS_EN,Single Address Location Translate Enable. When enabled Rx TLPs can be translated to a single address location as determined by the target address register of the iATU region. The main usage scenario is translation of Messages.." "0,1" newline bitfld.long 0x0 21. "MSG_CODE_MATCH_EN,Message Code Match Enable (Msg TLPS). Ensures that a successful message Code TLP field comparison match (see Message Code field of the 'iATU Control 2 Register') occurs (in MSG transactions) for address translation to proceed. ST Match.." "0,1" newline bitfld.long 0x0 20. "VF_MATCH_EN,Virtual Function Number Match Enable. Ensures that a successful Virtual Function Number TLP field comparison match (see Virtual Function Number field of the 'iATU Control 3 Register') occurs (in MEM-I/O transactions) for address translation.." "0,1" newline bitfld.long 0x0 19. "FUNC_NUM_MATCH_EN,Function Number Match Enable. Ensures that a successful Function Number TLP field comparison match (see Function Number field of the 'iATU Control 1 Register') occurs (in MEM-I/O and CFG0/CFG1 transactions) for address translation to.." "0,1" newline bitfld.long 0x0 16. "ATTR_MATCH_EN,ATTR Match Enable. Ensures that a successful ATTR TLP field comparison match (see ATTR field of the 'iATU Control 1 Register') occurs for address translation to proceed. Note: This register field is sticky." "0,1" newline bitfld.long 0x0 15. "TD_MATCH_EN,TD Match Enable. Ensures that a successful TD TLP field comparison match (see TD field of the 'iATU Control 1 Register') occurs for address translation to proceed. Note: This register field is sticky." "0,1" newline bitfld.long 0x0 14. "TC_MATCH_EN,TC Match Enable. Ensures that a successful TC TLP field comparison match (see TC field of the 'iATU Control 1 Register') occurs for address translation to proceed. Note: This register field is sticky." "0,1" newline bitfld.long 0x0 13. "MSG_TYPE_MATCH_MODE,Message Type Match Mode. When enabled and if single address location translate enable is set then inbound TLPs of type MSG/MSGd which match the type field of the iatu_region_ctrl_1_OFF_inbound register (=>TYPE[4:3]=2'b10) will be.." "0,1" newline bitfld.long 0x0 8.--10. "BAR_NUM,BAR Number. When the BAR number of an inbound MEM or IO TLP ' that is matched by the normal internal BAR address matching mechanism ' is the same as this field address translation proceeds (when all other enabled field-matches are successful)." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x0 0.--7. 1. "MSG_CODE,MSG TLPs: (Message Code). When the TYPE field of an inbound Msg/MsgD TLP is matched to this value then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the 'Message Code Match.." repeat.end repeat 8. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 )(list 0x0 0x200 0x400 0x600 0x800 0xA00 0xC00 0xE00 ) group.long ($2+0x108+0xC0000)++0x3 line.long 0x0 "IATU_LWR_BASE_ADDR_OFF_INBOUND_$1,iATU Lower Base Address Register. The CX_ATU_MIN_REGION_SIZE configuration parameter (Value Range: 4 kB. 8 kB. 16 kB. 32 kB. 64 kB defaults to 64 kB) specifies the minimum size of an address translation region. For.." hexmask.long.tbyte 0x0 12.--31. 1. "LWR_BASE_RW,Forms bits [31:n] of the start address of the address region to be translated. n is log2(CX_ATU_MIN_REGION_SIZE) Note: This register field is sticky." newline hexmask.long.word 0x0 0.--11. 1. "LWR_BASE_HW,Forms bits [n-1:0] of the start address of the address region to be translated. The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary so these bits are always 0. A write to this location is ignored by the PCIe controller." repeat.end repeat 8. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 )(list 0x0 0x200 0x400 0x600 0x800 0xA00 0xC00 0xE00 ) group.long ($2+0x10C+0xC0000)++0x3 line.long 0x0 "IATU_UPPER_BASE_ADDR_OFF_INBOUND_$1,iATU Upper Base Address Register." hexmask.long 0x0 0.--31. 1. "UPPER_BASE_RW,Forms bits [63:32] of the start (and end) address of the address region to be translated. Note: This register field is sticky." repeat.end repeat 8. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 )(list 0x0 0x200 0x400 0x600 0x800 0xA00 0xC00 0xE00 ) group.long ($2+0x110+0xC0000)++0x3 line.long 0x0 "IATU_LIMIT_ADDR_OFF_INBOUND_$1,iATU Limit Address Register." hexmask.long.tbyte 0x0 12.--31. 1. "LIMIT_ADDR_RW,Forms upper bits of the end address of the address region to be translated. Note: This register field is sticky." newline hexmask.long.word 0x0 0.--11. 1. "LIMIT_ADDR_HW,Forms lower bits of the end address of the address region to be translated. The end address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary so these bits are always all ones. A write to this location is ignored by the PCIe.." repeat.end repeat 8. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 )(list 0x0 0x200 0x400 0x600 0x800 0xA00 0xC00 0xE00 ) group.long ($2+0x114+0xC0000)++0x3 line.long 0x0 "IATU_LWR_TARGET_ADDR_OFF_INBOUND_$1,iATU Lower Target Address Register." hexmask.long.tbyte 0x0 12.--31. 1. "LWR_TARGET_RW,Forms MSB's of the Lower Target part of the new address of the translated region. These bits are always '0'. - Field size depends on log2(CX_ATU_MIN_REGION_SIZE) in address match mode. - Field size depends on log2(BAR_MASK+1) in BAR match.." newline hexmask.long.word 0x0 0.--11. 1. "LWR_TARGET_HW,Forms the LSB's of the Lower Target part of the new address of the translated region. The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary (in address match mode); and to the Bar size boundary (in BAR match mode) so.." repeat.end repeat 8. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 )(list 0x0 0x200 0x400 0x600 0x800 0xA00 0xC00 0xE00 ) group.long ($2+0x118+0xC0000)++0x3 line.long 0x0 "IATU_UPPER_TARGET_ADDR_OFF_INBOUND_$1,iATU Upper Target Address Register." hexmask.long 0x0 0.--31. 1. "UPPER_TARGET_RW,Forms bits [63:32] of the start address (Upper Target part) of the new address of the translated region. In systems with a 32-bit address space this register is not used and therefore writing to this register has no effect. Note: This.." repeat.end repeat 8. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 )(list 0x0 0x200 0x400 0x600 0x800 0xA00 0xC00 0xE00 ) group.long ($2+0x11C+0xC0000)++0x3 line.long 0x0 "IATU_REGION_CTRL_3_OFF_INBOUND_$1,iATU Region Control 3 Register." rbitfld.long 0x0 31. "VF_ACTIVE,Reserved. Not used." "0,1" newline hexmask.long 0x0 3.--30. 1. "RSVDP_VF_NUMBER,Reserved for future use." newline bitfld.long 0x0 0.--2. "VF_NUMBER,Virtual Function Number. When the Address and BAR matching logic in the controller indicates that a MEM-I/O transaction matches a BAR in the virtual function corresponding to this value then address translation proceeds. This check is only.." "0,1,2,3,4,5,6,7" repeat.end tree.end tree "PF0_PORT_LOGIC (Port Logic)" group.long (0x0+0x700)++0x27 line.long 0x0 "ACK_LATENCY_TIMER_OFF,Ack Latency Timer and Replay Timer Register." hexmask.long.word 0x0 16.--31. 1. "REPLAY_TIME_LIMIT,Replay Timer Limit. The replay timer expires when it reaches this limit. The controller initiates a replay upon reception of a NAK or when the replay timer expires. For more details see 'Transmit Replay'. You can modify the effective.." newline hexmask.long.word 0x0 0.--15. 1. "ROUND_TRIP_LATENCY_TIME_LIMIT,Ack Latency Timer Limit. The Ack latency timer expires when it reaches this limit. For more details see 'Ack Scheduling'. You can modify the effective timer limit with the TIMER_MOD_ACK_NAK field of the.." line.long 0x4 "VENDOR_SPEC_DLLP_OFF,Vendor Specific DLLP Register." hexmask.long 0x4 0.--31. 1. "VENDOR_SPEC_DLLP,Vendor Specific DLLP Register. Used to send a specific PCI Express DLLP. Your application writes the 8-bit DLLP Type and 24-bits of Payload data into this register then sets the field VENDOR_SPECIFIC_DLLP_REQ of PORT_LINK_CTRL_OFF to.." line.long 0x8 "PORT_FORCE_OFF,Port Force Link Register." hexmask.long.byte 0x8 24.--31. 1. "RSVDP_24,Reserved for future use." newline bitfld.long 0x8 23. "DO_DESKEW_FOR_SRIS,Use the transitions from TS2 to Logical Idle Symbol SKP OS to Logical Idle Symbol EIEOS to Logical Idle Symbol and FTS Sequence to SKP OS to do deskew instead of using received SKP OS or TS1 to TS2 transition if DO_DESKEW_FOR_SRIS.." "0,1" newline rbitfld.long 0x8 22. "RSVDP_22,Reserved for future use." "0,1" newline hexmask.long.byte 0x8 16.--21. 1. "LINK_STATE,Forced LTSSM State. The LTSSM state that the controller is forced to when you set the FORCE_EN bit (Force Link). LTSSM state encoding is defined by the lts_state variable in workspace/src/Layer1/smlh_ltssm.v. Note: This register field is sticky." newline bitfld.long 0x8 15. "FORCE_EN,Force Link. The controller supports a testing and debug capability to allow your software to force the LTSSM state machine into a specific state and to force the controller to transmit a specific Link Command. Asserting this bit triggers the.." "0,1" newline rbitfld.long 0x8 12.--14. "RSVDP_12,Reserved for future use." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x8 8.--11. 1. "FORCED_LTSSM,Forced Link Command. The link command that the controller is forced to transmit when you set FORCE_EN bit (Force Link). Link command encoding is defined by the ltssm_cmd variable in workspace/src/Layer1/smlh_ltssm.v. Note: This register.." newline hexmask.long.byte 0x8 0.--7. 1. "LINK_NUM,Link Number. Not used for endpoint. Not used for M-PCIe. Note: This register field is sticky." line.long 0xC "ACK_F_ASPM_CTRL_OFF,Ack Frequency and L0-L1 ASPM Control Register." rbitfld.long 0xC 31. "RSVDP_31,Reserved for future use." "0,1" newline bitfld.long 0xC 30. "ENTER_ASPM,ASPM L1 Entry Control. - 1: Controller enters ASPM L1 after a period in which it has been idle. - 0: Controller enters ASPM L1 only after idle period during which both receive and transmit are in L0s. Note: This register field is sticky." "Controller enters ASPM L1 only after idle period..,Controller enters ASPM L1 after a period in.." newline bitfld.long 0xC 27.--29. "L1_ENTRANCE_LATENCY,L1 Entrance Latency. Value range is: - 000: 1 us - 001: 2 us - 010: 4 us - 011: 8 us - 100: 16 us - 101: 32 us - 110 or 111: 64 us Note: Programming this timer with a value greater that 32us has no effect unless extended sync is used.." "0,1,2,3,4,5,6,7" newline bitfld.long 0xC 24.--26. "L0S_ENTRANCE_LATENCY,L0s Entrance Latency. Values correspond to: - 000: 1 us - 001: 2 us - 010: 3 us - 011: 4 us - 100: 5 us - 101: 6 us - 110 or 111: 7 us This field is applicable to STALL while in L0 for M-PCIe. Note: This register field is sticky." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0xC 16.--23. 1. "COMMON_CLK_N_FTS,Common Clock N_FTS. This is the N_FTS when common clock is used. The number of Fast Training Sequence ordered sets to be transmitted when transitioning from L0s to L0. The maximum number of FTS ordered-sets that a component can request.." newline hexmask.long.byte 0xC 8.--15. 1. "ACK_N_FTS,N_FTS. The number of Fast Training Sequence ordered sets to be transmitted when transitioning from L0s to L0. The maximum number of FTS ordered-sets that a component can request is 255. The controller does not support a value of zero; a value.." newline hexmask.long.byte 0xC 0.--7. 1. "ACK_FREQ,Ack Frequency. The controller accumulates the number of pending ACKs specified here (up to 255) before scheduling an ACK DLLP. - 0: Indicates that this Ack Frequency Counter feature is turned off. The controller generates a low-priority ACK.." line.long 0x10 "PORT_LINK_CTRL_OFF,Port Link Control Register." hexmask.long.byte 0x10 28.--31. 1. "RSVDP_28,Reserved for future use." newline bitfld.long 0x10 27. "TRANSMIT_LANE_REVERSALE_ENABLE,TRANSMIT_LANE_REVERSALE_ENABLE is an internally reserved field. Do not use. Note: This register field is sticky." "0,1" newline bitfld.long 0x10 26. "EXTENDED_SYNCH,EXTENDED_SYNCH is an internally reserved field. Do not use. Note: This register field is sticky." "0,1" newline bitfld.long 0x10 25. "CORRUPT_LCRC_ENABLE,CORRUPT_LCRC_ENABLE is an internally reserved field. Do not use. Note: This register field is sticky." "0,1" newline bitfld.long 0x10 24. "BEACON_ENABLE,BEACON_ENABLE is an internally reserved field. Do not use. Note: This register field is sticky." "0,1" newline hexmask.long.byte 0x10 16.--21. 1. "LINK_CAPABLE,Link Mode Enable. Sets the number of lanes in the link that you want to connect to the link partner. When you have unused lanes in your system then you must change the value in this register to reflect the number of lanes. You must also.." newline hexmask.long.byte 0x10 12.--15. 1. "RSVDP_12,Reserved for future use." newline hexmask.long.byte 0x10 8.--11. 1. "LINK_RATE,LINK_RATE is an internally reserved field. Do not use. Note: This register field is sticky." newline bitfld.long 0x10 7. "FAST_LINK_MODE,Fast Link Mode. Sets all internal LTSSM millisecond timers to Fast Mode for speeding up simulation. Forces the LTSSM training (link initialization) to use shorter time-outs and to link up faster. The default scaling factor can be changed.." "0,1" newline bitfld.long 0x10 6. "LINK_DISABLE,LINK_DISABLE is an internally reserved field. Do not use. Note: This register field is sticky." "0,1" newline bitfld.long 0x10 5. "DLL_LINK_EN,DLL Link Enable. Enables link initialization. When DLL Link Enable =0 the controller does not transmit InitFC DLLPs and does not establish a link. Note: This register field is sticky." "0,1" newline rbitfld.long 0x10 4. "RSVDP_4,Reserved for future use." "0,1" newline bitfld.long 0x10 3. "RESET_ASSERT,Reset Assert. Triggers a recovery and forces the LTSSM to the hot reset state (downstream port only). Note: This register field is sticky." "0,1" newline bitfld.long 0x10 2. "LOOPBACK_ENABLE,Loopback Enable. Turns on loopback. For more details see 'Loopback'. For M-PCIe to force the master to enter Digital Loopback mode you must set this field to '1' during Configuration.start state(initial discovery/configuration). M-PCIe.." "0,1" newline bitfld.long 0x10 1. "SCRAMBLE_DISABLE,Scramble Disable. Turns off data scrambling. Note: This register field is sticky." "0,1" newline bitfld.long 0x10 0. "VENDOR_SPECIFIC_DLLP_REQ,Vendor Specific DLLP Request. When software writes a '1' to this bit the controller transmits the DLLP contained in the VENDOR_SPEC_DLLP field of VENDOR_SPEC_DLLP_OFF. Reading from this self-clearing register field always.." "0,1" line.long 0x14 "LANE_SKEW_OFF,Lane Skew Register." bitfld.long 0x14 31. "DISABLE_LANE_TO_LANE_DESKEW,Disable Lane-to-Lane Deskew. Causes the controller to disable the internal Lane-to-Lane deskew logic. Note: This register field is sticky." "0,1" newline hexmask.long.byte 0x14 27.--30. 1. "IMPLEMENT_NUM_LANES,Implementation-specific Number of Lanes. Set the implementation-specific number of lanes. Allowed values are: - 4'b0000: 1 lane - 4'b0001: 2 lanes - 4'b0011: 4 lanes - 4'b0111: 8 lanes - 4'b1111: 16 lanes The number of lanes to be.." newline bitfld.long 0x14 26. "ELASTIC_BUFFER_MODE,Selects Elasticity Buffer operating mode: 0: Nominal Half Full Buffer mode 1: Nominal Empty Buffer Mode Note: This register field is sticky." "Nominal Half Full Buffer mode,Nominal Empty Buffer Mode" newline bitfld.long 0x14 25. "ACK_NAK_DISABLE,Ack/Nak Disable. Prevents the controller from sending ACK and NAK DLLPs. Note: This register field is sticky." "0,1" newline bitfld.long 0x14 24. "FLOW_CTRL_DISABLE,Flow Control Disable. Prevents the controller from sending FC DLLPs. Note: This register field is sticky." "0,1" newline hexmask.long.tbyte 0x14 0.--23. 1. "INSERT_LANE_SKEW,INSERT_LANE_SKEW is an internally reserved field. Do not use. Note: This register field is sticky." line.long 0x18 "TIMER_CTRL_MAX_FUNC_NUM_OFF,Timer Control and Max Function Number Register." rbitfld.long 0x18 31. "RSVDP_31,Reserved for future use." "0,1" newline bitfld.long 0x18 29.--30. "FAST_LINK_SCALING_FACTOR,Fast Link Timer Scaling Factor. Sets the scaling factor of LTSSM timer when FAST_LINK_MODE field in PORT_LINK_CTRL_OFF is set to '1'. - 0: Scaling Factor is 1024 (1ms is 1us *a) - 1: Scaling Factor is 256 (1ms is 4us) - 2:.." "Scaling Factor is 1024,Scaling Factor is 256,Scaling Factor is 64,Scaling Factor is 16" newline hexmask.long.byte 0x18 24.--28. 1. "UPDATE_FREQ_TIMER,UPDATE_FREQ_TIMER is an internally reserved field. Do not use. Note: This register field is sticky." newline hexmask.long.byte 0x18 19.--23. 1. "TIMER_MOD_ACK_NAK,Ack Latency Timer Modifier. Increases the timer value for the Ack latency timer in increments of 64 clock cycles. A value of '0' represents no modification to the timer value. For more details see the ROUND_TRIP_LATENCY_TIME_LIMIT.." newline hexmask.long.byte 0x18 14.--18. 1. "TIMER_MOD_REPLAY_TIMER,Replay Timer Limit Modifier. Increases the time-out value for the replay timer in increments of 64 clock cycles at Gen1 or Gen2 speed and in increments of 256 clock cycles at Gen3 speed. A value of '0' represents no modification.." newline hexmask.long.byte 0x18 8.--13. 1. "RSVDP_8,Reserved for future use." newline hexmask.long.byte 0x18 0.--7. 1. "MAX_FUNC_NUM,Maximum function number that can be used in a request. Configuration requests targeted at function numbers above this value are returned with UR (unsupported request). Note: This register field is sticky." line.long 0x1C "SYMBOL_TIMER_FILTER_1_OFF,Symbol Timer Register and Filter Mask 1 Register. The Filter Mask 1 Register modifies the RADM filtering and error handling rules. For more details. see the 'Receive Filtering' section. In each case. '0' applies the associated.." hexmask.long.word 0x1C 16.--31. 1. "MASK_RADM_1,Filter Mask 1. The Filter Mask 1 Register modifies the RADM filtering and error handling rules. For more details see the 'Receive Filtering' section. In each case '0' applies the associated filtering rule and '1' masks the associated.." newline bitfld.long 0x1C 15. "DISABLE_FC_WD_TIMER,Disable FC Watchdog Timer. Note: This register field is sticky." "0,1" newline hexmask.long.byte 0x1C 11.--14. 1. "EIDLE_TIMER,EIDLE_TIMER is an internally reserved field. Do not use. Note: This register field is sticky." newline hexmask.long.word 0x1C 0.--10. 1. "SKP_INT_VAL,SKP Interval Value. The number of symbol times to wait between transmitting SKP ordered sets. Note that the controller actually waits the number of symbol times in this register plus 1 between transmitting SKP ordered sets. Your application.." line.long 0x20 "FILTER_MASK_2_OFF,Filter Mask 2 Register. This register modifies the RADM filtering and error handling rules. For more details. see the 'Receive Filtering' section. In each case. '0' applies the associated filtering rule and '1' masks the associated.." hexmask.long 0x20 0.--31. 1. "MASK_RADM_2,Filter Mask 2. This field modifies the RADM filtering and error handling rules. For more details see the 'Receive Filtering' section. In each case '0' applies the associated filtering rule and '1' masks the associated filtering rule." line.long 0x24 "AMBA_MUL_OB_DECOMP_NP_SUB_REQ_CTRL_OFF,AMBA Multiple Outbound Decomposed NP SubRequests Control Register." hexmask.long 0x24 1.--31. 1. "RSVDP_1,Reserved for future use." newline bitfld.long 0x24 0. "OB_RD_SPLIT_BURST_EN,Enable AMBA Multiple Outbound Decomposed NP SubRequests. This bit when set to '0' disables the possibility of having multiple outstanding non-posted requests that were derived from decomposition of an outbound AMBA request. For more.." "0,1" rgroup.long (0x28+0x700)++0x13 line.long 0x0 "PL_DEBUG0_OFF,Debug Register 0" hexmask.long 0x0 0.--31. 1. "DEB_REG_0,The value on cxpl_debug_info[31:0]." line.long 0x4 "PL_DEBUG1_OFF,Debug Register 1" hexmask.long 0x4 0.--31. 1. "DEB_REG_1,The value on cxpl_debug_info[63:32]." line.long 0x8 "TX_P_FC_CREDIT_STATUS_OFF,Transmit Posted FC Credit Status" hexmask.long.word 0x8 20.--31. 1. "RSVDP_TX_P_FC_CREDIT_STATUS,Reserved for future use." newline hexmask.long.byte 0x8 12.--19. 1. "TX_P_HEADER_FC_CREDIT,Transmit Posted Header FC Credits. The posted Header credits advertised by the receiver at the other end of the link updated with each UpdateFC DLLP. Default value depends on the number of advertised credits for header and data.." newline hexmask.long.word 0x8 0.--11. 1. "TX_P_DATA_FC_CREDIT,Transmit Posted Data FC Credits. The posted Data credits advertised by the receiver at the other end of the link updated with each UpdateFC DLLP. Default value depends on the number of advertised credits for header and data Scaled.." line.long 0xC "TX_NP_FC_CREDIT_STATUS_OFF,Transmit Non-Posted FC Credit Status" hexmask.long.word 0xC 20.--31. 1. "RSVDP_TX_NP_FC_CREDIT_STATUS,Reserved for future use." newline hexmask.long.byte 0xC 12.--19. 1. "TX_NP_HEADER_FC_CREDIT,Transmit Non-Posted Header FC Credits. The non-posted Header credits advertised by the receiver at the other end of the link updated with each UpdateFC DLLP. Default value depends on the number of advertised credits for header and.." newline hexmask.long.word 0xC 0.--11. 1. "TX_NP_DATA_FC_CREDIT,Transmit Non-Posted Data FC Credits. The non-posted Data credits advertised by the receiver at the other end of the link updated with each UpdateFC DLLP. Default value depends on the number of advertised credits for header and data.." line.long 0x10 "TX_CPL_FC_CREDIT_STATUS_OFF,Transmit Completion FC Credit Status" hexmask.long.word 0x10 20.--31. 1. "RSVDP_TX_CPL_FC_CREDIT_STATUS,Reserved for future use." newline hexmask.long.byte 0x10 12.--19. 1. "TX_CPL_HEADER_FC_CREDIT,Transmit Completion Header FC Credits. The Completion Header credits advertised by the receiver at the other end of the link updated with each UpdateFC DLLP. Default value depends on the number of advertised credits for header.." newline hexmask.long.word 0x10 0.--11. 1. "TX_CPL_DATA_FC_CREDIT,Transmit Completion Data FC Credits. The Completion Data credits advertised by the receiver at the other end of the link updated with each UpdateFC DLLP. Default value depends on the number of advertised credits for header and data.." group.long (0x3C+0x700)++0x3 line.long 0x0 "QUEUE_STATUS_OFF,Queue Status" bitfld.long 0x0 31. "TIMER_MOD_FLOW_CONTROL_EN,FC Latency Timer Override Enable. When this bit is set the value from the 'FC Latency Timer Override Value' field in this register will override the FC latency timer value that the controller calculates according to the PCIe.." "0,1" newline rbitfld.long 0x0 29.--30. "RSVDP_29,Reserved for future use." "0,1,2,3" newline hexmask.long.word 0x0 16.--28. 1. "TIMER_MOD_FLOW_CONTROL,FC Latency Timer Override Value. When you set the 'FC Latency Timer Override Enable' in this register the value in this field will override the FC latency timer value that the controller calculates according to the PCIe.." newline rbitfld.long 0x0 13. "RX_SERIALIZATION_Q_NON_EMPTY,Receive Serialization Queue Not Empty. Indicates there is data in the serialization queue." "0,1" newline hexmask.long.word 0x0 4.--12. 1. "RSVDP_4,Reserved for future use." newline bitfld.long 0x0 3. "RX_QUEUE_OVERFLOW,Receive Credit Queue Overflow. Indicates insufficient buffer space available to write to the P/NP/CPL credit queue." "0,1" newline rbitfld.long 0x0 2. "RX_QUEUE_NON_EMPTY,Receive Credit Queue Not Empty. Indicates there is data in one or more of the receive buffers." "0,1" newline rbitfld.long 0x0 1. "TX_RETRY_BUFFER_NE,Transmit Retry Buffer Not Empty. Indicates that there is data in the transmit retry buffer." "0,1" newline rbitfld.long 0x0 0. "RX_TLP_FC_CREDIT_NON_RETURN,Received TLP FC Credits Not Returned. Indicates that the controller has received a TLP but has not yet sent an UpdateFC DLLP indicating that the credits for that TLP have been restored by the receiver at the other end of the.." "0,1" rgroup.long (0x40+0x700)++0x7 line.long 0x0 "VC_TX_ARBI_1_OFF,VC Transmit Arbitration Register 1" hexmask.long.byte 0x0 24.--31. 1. "WRR_WEIGHT_VC_3,WRR Weight for VC3. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R" newline hexmask.long.byte 0x0 16.--23. 1. "WRR_WEIGHT_VC_2,WRR Weight for VC2. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R" newline hexmask.long.byte 0x0 8.--15. 1. "WRR_WEIGHT_VC_1,WRR Weight for VC1. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R" newline hexmask.long.byte 0x0 0.--7. 1. "WRR_WEIGHT_VC_0,WRR Weight for VC0. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R" line.long 0x4 "VC_TX_ARBI_2_OFF,VC Transmit Arbitration Register 2" hexmask.long.byte 0x4 24.--31. 1. "WRR_WEIGHT_VC_7,WRR Weight for VC7. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R" newline hexmask.long.byte 0x4 16.--23. 1. "WRR_WEIGHT_VC_6,WRR Weight for VC6. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R" newline hexmask.long.byte 0x4 8.--15. 1. "WRR_WEIGHT_VC_5,WRR Weight for VC5. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R" newline hexmask.long.byte 0x4 0.--7. 1. "WRR_WEIGHT_VC_4,WRR Weight for VC4. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R" group.long (0x48+0x700)++0xB line.long 0x0 "VC0_P_RX_Q_CTRL_OFF,Segmented-Buffer VC0 Posted Receive Queue Control." bitfld.long 0x0 31. "VC_ORDERING_RX_Q,VC Ordering for Receive Queues. Determines the VC ordering rule for the receive queues used only in the segmented-buffer configuration: - 1: Strict ordering higher numbered VCs have higher priority - 0: Round robin Note: This register.." "Round robin,Strict ordering" newline bitfld.long 0x0 30. "TLP_TYPE_ORDERING_VC0,TLP Type Ordering for VC0. Determines the TLP type ordering rule for VC0 receive queues used only in the segmented-buffer configuration: - 1: PCIe ordering rules (recommended) - 0: Strict ordering: posted completion then.." "Strict ordering: posted,PCIe ordering rules" newline bitfld.long 0x0 28.--29. "RESERVED5,Reserved. Note: This register field is sticky." "0,1,2,3" newline bitfld.long 0x0 26.--27. "VC0_P_DATA_SCALE,VC0 Scale Posted Data Credites. Note: This register field is sticky." "0,1,2,3" newline bitfld.long 0x0 24.--25. "VC0_P_HDR_SCALE,VC0 Scale Posted Header Credites. Note: This register field is sticky." "0,1,2,3" newline bitfld.long 0x0 21.--23. "VC0_P_TLP_Q_MODE,Reserved. Note: This register field is sticky." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 20. "RESERVED4,Reserved. Note: This register field is sticky." "0,1" newline hexmask.long.byte 0x0 12.--19. 1. "VC0_P_HEADER_CREDIT,VC0 Posted Header Credits. The number of initial posted header credits for VC0 used only in the segmented-buffer configuration. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R (sticky) Note: This.." newline hexmask.long.word 0x0 0.--11. 1. "VC0_P_DATA_CREDIT,VC0 Posted Data Credits. The number of initial posted data credits for VC0 used only in the segmented-buffer configuration. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R (sticky) Note: This.." line.long 0x4 "VC0_NP_RX_Q_CTRL_OFF,Segmented-Buffer VC0 Non-Posted Receive Queue Control." hexmask.long.byte 0x4 28.--31. 1. "RESERVED7,Reserved. Note: This register field is sticky." newline bitfld.long 0x4 26.--27. "VC0_NP_DATA_SCALE,VC0 Scale Non-Posted Data Credites. Note: This register field is sticky." "0,1,2,3" newline bitfld.long 0x4 24.--25. "VC0_NP_HDR_SCALE,VC0 Scale Non-Posted Header Credites. Note: This register field is sticky." "0,1,2,3" newline bitfld.long 0x4 21.--23. "VC0_NP_TLP_Q_MODE,Reserved. Note: This register field is sticky." "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 20. "RESERVED6,Reserved. Note: This register field is sticky." "0,1" newline hexmask.long.byte 0x4 12.--19. 1. "VC0_NP_HEADER_CREDIT,VC0 Non-Posted Header Credits. The number of initial non-posted header credits for VC0 used only in the segmented-buffer configuration. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R (sticky).." newline hexmask.long.word 0x4 0.--11. 1. "VC0_NP_DATA_CREDIT,VC0 Non-Posted Data Credits. The number of initial non-posted data credits for VC0 used only in the segmented-buffer configuration. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R (sticky) Note:.." line.long 0x8 "VC0_CPL_RX_Q_CTRL_OFF,Segmented-Buffer VC0 Completion Receive Queue Control." hexmask.long.byte 0x8 28.--31. 1. "RESERVED9,Reserved. Note: This register field is sticky." newline bitfld.long 0x8 26.--27. "VC0_CPL_DATA_SCALE,VC0 Scale CPL Data Credites. Note: This register field is sticky." "0,1,2,3" newline bitfld.long 0x8 24.--25. "VC0_CPL_HDR_SCALE,VC0 Scale CPL Header Credites. Note: This register field is sticky." "0,1,2,3" newline bitfld.long 0x8 21.--23. "VC0_CPL_TLP_Q_MODE,Reserved. Note: This register field is sticky." "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 20. "RESERVED8,Reserved. Note: This register field is sticky." "0,1" newline hexmask.long.byte 0x8 12.--19. 1. "VC0_CPL_HEADER_CREDIT,VC0 Completion Header Credits. The number of initial Completion header credits for VC0 used only in the segmented-buffer configuration. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R (sticky).." newline hexmask.long.word 0x8 0.--11. 1. "VC0_CPL_DATA_CREDIT,VC0 Completion Data Credits. The number of initial Completion data credits for VC0 used only in the segmented-buffer configuration. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R (sticky) Note:.." group.long (0x10C+0x700)++0x3 line.long 0x0 "GEN2_CTRL_OFF,This register is used to control various functions of the controller related to link training. lane reversal. and equalization." rbitfld.long 0x0 31. "RSVDP_31,Reserved for future use." "0,1" newline bitfld.long 0x0 30. "FORCE_LANE_FLIP,Enable to force the LANE_UNDER_TEST physical lane flips to logical lane 0. All the other physical lanes are turned off. The LINK_CAPABLE register must be set to 1 and only x1 link can be formed if the FORCE_LANE_FLIP register is set to 1." "0,1" newline hexmask.long.byte 0x0 24.--27. 1. "LANE_UNDER_TEST,The Lane Under Test is the lane for Forced Lane Flip or for Loopback Eq. The value is from 0 to CX_NL. Only one lane is configured each time. The default of this field is the CX_DEFAULT_LANE_UNDER_TEST configuration parameter. This field.." newline rbitfld.long 0x0 22.--23. "RSVDP_22,Reserved for future use." "0,1,2,3" newline bitfld.long 0x0 21. "GEN1_EI_INFERENCE,Electrical Idle Inference Mode at Gen1 Rate. Programmable mode to determine inferred electrical idle (EI) in Recovery.Speed or Loopback.Active (as slave) state at Gen1 speed by looking for a '1' value on RxElecIdle instead of looking.." "Use RxElecIdle signal to infer Electrical Idle,Use RxValid signal to infer Electrical Idle" newline bitfld.long 0x0 20. "SEL_DEEMPHASIS,Used to set the de-emphasis level for upstream ports. This bit selects the level of de-emphasis the link operates at. - 0: -6 dB - 1: -3.5 dB This field is reserved (fixed to '0') for M-PCIe. Note: The access attributes of this field are.." "0,1" newline bitfld.long 0x0 19. "CONFIG_TX_COMP_RX,Config Tx Compliance Receive Bit. When set to 1 signals LTSSM to transmit TS ordered sets with the compliance receive bit assert (equal to '1'). This field is reserved (fixed to '0') for M-PCIe. Note: The access attributes of this.." "0,1" newline bitfld.long 0x0 18. "CONFIG_PHY_TX_CHANGE,Config PHY Tx Swing. Controls the PHY transmitter voltage swing level. The controller drives the mac_phy_txswing output from this register bit field. - 0: Full Swing - 1: Low Swing This field is reserved (fixed to '0') for M-PCIe." "Full Swing,Low Swing" newline bitfld.long 0x0 17. "DIRECT_SPEED_CHANGE,Directed Speed Change. Writing '1' to this field instructs the LTSSM to initiate a speed change to Gen2 or Gen3 after the link is initialized at Gen1 speed. When the speed change occurs the controller will clear the contents of this.." "0,1" newline bitfld.long 0x0 16. "AUTO_LANE_FLIP_CTRL_EN,Enable Auto flipping of the lanes. You must set the CX_AUTO_LANE_FLIP_CTRL_EN configuration parameter to include the hardware for this feature in the controller. For more details see the 'Lane Reversal' appendix in the Databook." "0,1" newline bitfld.long 0x0 13.--15. "PRE_DET_LANE,Predetermined Lane for Auto Flip. This field defines which physical lane is connected to logical Lane0 by the flip operation performed in Detect. This field is used to restrict the receiver detect procedure to a particular lane when the.." "LANE0,LANE1,LANE3,LANE7,LANE15,?,?,?" newline hexmask.long.byte 0x0 8.--12. 1. "NUM_OF_LANES,Predetermined Number of Lanes. Defines the number of lanes which are connected and not bad. Used to limit the effective link width to ignore 'broken' or 'unused' lanes that detect a receiver. Indicates the number of lanes to check for exit.." newline hexmask.long.byte 0x0 0.--7. 1. "FAST_TRAINING_SEQ,Sets the Number of Fast Training Sequences (N_FTS) that the controller advertises as its N_FTS during Gen2 or Gen3 link training. This value is used to inform the link partner about the PHY's ability to recover synchronization after a.." rgroup.long (0x110+0x700)++0x3 line.long 0x0 "PHY_STATUS_OFF,PHY Status Register. Memory mapped register from phy_cfg_status GPIO input pins." hexmask.long 0x0 0.--31. 1. "PHY_STATUS,PHY Status. Data received directly from the phy_cfg_status bus. These is a GPIO register reflecting the values on the static phy_cfg_status input signals. The usage is left completely to the user and does not in any way influence controller.." group.long (0x114+0x700)++0x3 line.long 0x0 "PHY_CONTROL_OFF,PHY Control Register. Memory mapped register to cfg_phy_control GPIO output pins." hexmask.long 0x0 0.--31. 1. "PHY_CONTROL,PHY Control. Data sent directly to the cfg_phy_control bus. These is a GPIO register driving the values on the static cfg_phy_control output signals. The usage is left completely to the user and does not in any way influence controller.." group.long (0x11C+0x700)++0x77 line.long 0x0 "TRGT_MAP_CTRL_OFF,Programmable Target Map Control Register." hexmask.long.word 0x0 21.--31. 1. "TARGET_MAP_RESERVED_21_31,Reserved. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R (sticky)" newline hexmask.long.byte 0x0 16.--20. 1. "TARGET_MAP_INDEX,The number of the PF Function on which the Target Values are set. This register does not respect the Byte Enable setting. any write will affect all register bits." newline rbitfld.long 0x0 13.--15. "TARGET_MAP_RESERVED_13_15,Reserved. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R (sticky)" "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x0 7.--12. 1. "TARGET_MAP_VF,Target Values for each BAR on the VF Function selected by the index number. This register does not respect the Byte Enable setting. any write will affect all register bits." newline bitfld.long 0x0 6. "TARGET_MAP_ROM,Target Value for the ROM page of the PF Function selected by the index number. This register does not respect the Byte Enable setting. any write will affect all register bits." "0,1" newline hexmask.long.byte 0x0 0.--5. 1. "TARGET_MAP_PF,Target Values for each BAR on the PF Function selected by the index number. This register does not respect the Byte Enable setting. any write will affect all register bits." line.long 0x4 "MSI_CTRL_ADDR_OFF,Integrated MSI Reception Module (iMRM) Address Register." hexmask.long 0x4 0.--31. 1. "MSI_CTRL_ADDR,Integrated MSI Reception Module Address. System specified address for MSI memory write transaction termination. Within the AXI Bridge every received Memory Write request is examined to see if it targets the MSI Address that has been.." line.long 0x8 "MSI_CTRL_UPPER_ADDR_OFF,Integrated MSI Reception Module Upper Address Register." hexmask.long 0x8 0.--31. 1. "MSI_CTRL_UPPER_ADDR,Integrated MSI Reception Module Upper Address. System specified upper address for MSI memory write transaction termination. Allows functions to support a 64-bit MSI address. Note: This register field is sticky." line.long 0xC "MSI_CTRL_INT_0_EN_OFF,Integrated MSI Reception Module Interrupt#i Enable Register." hexmask.long 0xC 0.--31. 1. "MSI_CTRL_INT_0_EN,MSI Interrupt#i Enable. Specifies which interrupts are enabled. When an MSI is received from a disabled interrupt no status bit gets set in MSI controller interrupt status register. Each bit corresponds to a single MSI Interrupt.." line.long 0x10 "MSI_CTRL_INT_0_MASK_OFF,Integrated MSI Reception Module Interrupt#i Mask Register." hexmask.long 0x10 0.--31. 1. "MSI_CTRL_INT_0_MASK,MSI Interrupt#i Mask. Allows enabled interrupts to be masked. When an MSI is received for a masked interrupt the corresponding status bit gets set in the interrupt status register but the msi_ctrl_int output is not set HIGH. Each bit.." line.long 0x14 "MSI_CTRL_INT_0_STATUS_OFF,Integrated MSI Reception Module Interrupt#i Status Register." hexmask.long 0x14 0.--31. 1. "MSI_CTRL_INT_0_STATUS,MSI Interrupt#i Status. When an MSI is detected for EP#i one bit in this register is set. The decoding of the data payload of the MSI Memory Write request determines which bit gets set. A status is bit is cleared by writing a 1 to.." line.long 0x18 "MSI_CTRL_INT_1_EN_OFF,Integrated MSI Reception Module Interrupt#i Enable Register." hexmask.long 0x18 0.--31. 1. "MSI_CTRL_INT_1_EN,MSI Interrupt#i Enable. Specifies which interrupts are enabled. When an MSI is received from a disabled interrupt no status bit gets set in MSI controller interrupt status register. Each bit corresponds to a single MSI Interrupt.." line.long 0x1C "MSI_CTRL_INT_1_MASK_OFF,Integrated MSI Reception Module Interrupt#i Mask Register." hexmask.long 0x1C 0.--31. 1. "MSI_CTRL_INT_1_MASK,MSI Interrupt#i Mask. Allows enabled interrupts to be masked. When an MSI is received for a masked interrupt the corresponding status bit gets set in the interrupt status register but the msi_ctrl_int output is not set HIGH. Each bit.." line.long 0x20 "MSI_CTRL_INT_1_STATUS_OFF,Integrated MSI Reception Module Interrupt#i Status Register." hexmask.long 0x20 0.--31. 1. "MSI_CTRL_INT_1_STATUS,MSI Interrupt#i Status. When an MSI is detected for EP#i one bit in this register is set. The decoding of the data payload of the MSI Memory Write request determines which bit gets set. A status is bit is cleared by writing a 1 to.." line.long 0x24 "MSI_CTRL_INT_2_EN_OFF,Integrated MSI Reception Module Interrupt#i Enable Register." hexmask.long 0x24 0.--31. 1. "MSI_CTRL_INT_2_EN,MSI Interrupt#i Enable. Specifies which interrupts are enabled. When an MSI is received from a disabled interrupt no status bit gets set in MSI controller interrupt status register. Each bit corresponds to a single MSI Interrupt.." line.long 0x28 "MSI_CTRL_INT_2_MASK_OFF,Integrated MSI Reception Module Interrupt#i Mask Register." hexmask.long 0x28 0.--31. 1. "MSI_CTRL_INT_2_MASK,MSI Interrupt#i Mask. Allows enabled interrupts to be masked. When an MSI is received for a masked interrupt the corresponding status bit gets set in the interrupt status register but the msi_ctrl_int output is not set HIGH. Each bit.." line.long 0x2C "MSI_CTRL_INT_2_STATUS_OFF,Integrated MSI Reception Module Interrupt#i Status Register." hexmask.long 0x2C 0.--31. 1. "MSI_CTRL_INT_2_STATUS,MSI Interrupt#i Status. When an MSI is detected for EP#i one bit in this register is set. The decoding of the data payload of the MSI Memory Write request determines which bit gets set. A status is bit is cleared by writing a 1 to.." line.long 0x30 "MSI_CTRL_INT_3_EN_OFF,Integrated MSI Reception Module Interrupt#i Enable Register." hexmask.long 0x30 0.--31. 1. "MSI_CTRL_INT_3_EN,MSI Interrupt#i Enable. Specifies which interrupts are enabled. When an MSI is received from a disabled interrupt no status bit gets set in MSI controller interrupt status register. Each bit corresponds to a single MSI Interrupt.." line.long 0x34 "MSI_CTRL_INT_3_MASK_OFF,Integrated MSI Reception Module Interrupt#i Mask Register." hexmask.long 0x34 0.--31. 1. "MSI_CTRL_INT_3_MASK,MSI Interrupt#i Mask. Allows enabled interrupts to be masked. When an MSI is received for a masked interrupt the corresponding status bit gets set in the interrupt status register but the msi_ctrl_int output is not set HIGH. Each bit.." line.long 0x38 "MSI_CTRL_INT_3_STATUS_OFF,Integrated MSI Reception Module Interrupt#i Status Register." hexmask.long 0x38 0.--31. 1. "MSI_CTRL_INT_3_STATUS,MSI Interrupt#i Status. When an MSI is detected for EP#i one bit in this register is set. The decoding of the data payload of the MSI Memory Write request determines which bit gets set. A status is bit is cleared by writing a 1 to.." line.long 0x3C "MSI_CTRL_INT_4_EN_OFF,Integrated MSI Reception Module Interrupt#i Enable Register." hexmask.long 0x3C 0.--31. 1. "MSI_CTRL_INT_4_EN,MSI Interrupt#i Enable. Specifies which interrupts are enabled. When an MSI is received from a disabled interrupt no status bit gets set in MSI controller interrupt status register. Each bit corresponds to a single MSI Interrupt.." line.long 0x40 "MSI_CTRL_INT_4_MASK_OFF,Integrated MSI Reception Module Interrupt#i Mask Register." hexmask.long 0x40 0.--31. 1. "MSI_CTRL_INT_4_MASK,MSI Interrupt#i Mask. Allows enabled interrupts to be masked. When an MSI is received for a masked interrupt the corresponding status bit gets set in the interrupt status register but the msi_ctrl_int output is not set HIGH. Each bit.." line.long 0x44 "MSI_CTRL_INT_4_STATUS_OFF,Integrated MSI Reception Module Interrupt#i Status Register." hexmask.long 0x44 0.--31. 1. "MSI_CTRL_INT_4_STATUS,MSI Interrupt#i Status. When an MSI is detected for EP#i one bit in this register is set. The decoding of the data payload of the MSI Memory Write request determines which bit gets set. A status is bit is cleared by writing a 1 to.." line.long 0x48 "MSI_CTRL_INT_5_EN_OFF,Integrated MSI Reception Module Interrupt#i Enable Register." hexmask.long 0x48 0.--31. 1. "MSI_CTRL_INT_5_EN,MSI Interrupt#i Enable. Specifies which interrupts are enabled. When an MSI is received from a disabled interrupt no status bit gets set in MSI controller interrupt status register. Each bit corresponds to a single MSI Interrupt.." line.long 0x4C "MSI_CTRL_INT_5_MASK_OFF,Integrated MSI Reception Module Interrupt#i Mask Register." hexmask.long 0x4C 0.--31. 1. "MSI_CTRL_INT_5_MASK,MSI Interrupt#i Mask. Allows enabled interrupts to be masked. When an MSI is received for a masked interrupt the corresponding status bit gets set in the interrupt status register but the msi_ctrl_int output is not set HIGH. Each bit.." line.long 0x50 "MSI_CTRL_INT_5_STATUS_OFF,Integrated MSI Reception Module Interrupt#i Status Register." hexmask.long 0x50 0.--31. 1. "MSI_CTRL_INT_5_STATUS,MSI Interrupt#i Status. When an MSI is detected for EP#i one bit in this register is set. The decoding of the data payload of the MSI Memory Write request determines which bit gets set. A status is bit is cleared by writing a 1 to.." line.long 0x54 "MSI_CTRL_INT_6_EN_OFF,Integrated MSI Reception Module Interrupt#i Enable Register." hexmask.long 0x54 0.--31. 1. "MSI_CTRL_INT_6_EN,MSI Interrupt#i Enable. Specifies which interrupts are enabled. When an MSI is received from a disabled interrupt no status bit gets set in MSI controller interrupt status register. Each bit corresponds to a single MSI Interrupt.." line.long 0x58 "MSI_CTRL_INT_6_MASK_OFF,Integrated MSI Reception Module Interrupt#i Mask Register." hexmask.long 0x58 0.--31. 1. "MSI_CTRL_INT_6_MASK,MSI Interrupt#i Mask. Allows enabled interrupts to be masked. When an MSI is received for a masked interrupt the corresponding status bit gets set in the interrupt status register but the msi_ctrl_int output is not set HIGH. Each bit.." line.long 0x5C "MSI_CTRL_INT_6_STATUS_OFF,Integrated MSI Reception Module Interrupt#i Status Register." hexmask.long 0x5C 0.--31. 1. "MSI_CTRL_INT_6_STATUS,MSI Interrupt#i Status. When an MSI is detected for EP#i one bit in this register is set. The decoding of the data payload of the MSI Memory Write request determines which bit gets set. A status is bit is cleared by writing a 1 to.." line.long 0x60 "MSI_CTRL_INT_7_EN_OFF,Integrated MSI Reception Module Interrupt#i Enable Register." hexmask.long 0x60 0.--31. 1. "MSI_CTRL_INT_7_EN,MSI Interrupt#i Enable. Specifies which interrupts are enabled. When an MSI is received from a disabled interrupt no status bit gets set in MSI controller interrupt status register. Each bit corresponds to a single MSI Interrupt.." line.long 0x64 "MSI_CTRL_INT_7_MASK_OFF,Integrated MSI Reception Module Interrupt#i Mask Register." hexmask.long 0x64 0.--31. 1. "MSI_CTRL_INT_7_MASK,MSI Interrupt#i Mask. Allows enabled interrupts to be masked. When an MSI is received for a masked interrupt the corresponding status bit gets set in the interrupt status register but the msi_ctrl_int output is not set HIGH. Each bit.." line.long 0x68 "MSI_CTRL_INT_7_STATUS_OFF,Integrated MSI Reception Module Interrupt#i Status Register." hexmask.long 0x68 0.--31. 1. "MSI_CTRL_INT_7_STATUS,MSI Interrupt#i Status. When an MSI is detected for EP#i one bit in this register is set. The decoding of the data payload of the MSI Memory Write request determines which bit gets set. A status is bit is cleared by writing a 1 to.." line.long 0x6C "MSI_GPIO_IO_OFF,Integrated MSI Reception Module General Purpose IO Register." hexmask.long 0x6C 0.--31. 1. "MSI_GPIO_REG,MSI GPIO Register. The contents of this register drives the top-level GPIO msi_ctrl_io[31:0] Note: This register field is sticky." line.long 0x70 "CLOCK_GATING_CTRL_OFF,This register enables you to disable dynamic clock gating. By default dynamic clock gating is on. allowing the controller to autonomously enable and disable its clocks. The clock gating is performed in the clock and reset module." hexmask.long 0x70 2.--31. 1. "RSVDP_2,Reserved for future use." newline bitfld.long 0x70 1. "AXI_CLK_GATING_EN,AXI Clock Gating Enable. This register enables the AXI Bridge to autonomously enable and disable the AXI Master clock the AXI Slave clock and the AXI DBI slave clock. The DWC_pcie_clk_rst.v module provides the gated clock.." "Disable,Enable" newline bitfld.long 0x70 0. "RADM_CLK_GATING_EN,RADM Clock Gating Enable. This register if set enables the RADM to autonomously enable and disable its clock. The DWC_pcie_clk_rst.v module provides the gated clock radm_clk_g to the RADM and is enabled when the controllers clock.." "Disable,Enable" line.long 0x74 "GEN3_RELATED_OFF,Gen3 Control Register. There is no Gen3-specific N_FTS field. The N_FTS field in the 'Link Width and Speed Change Control Register' is used for both Gen2 and Gen3 speed modes. There is no Gen3-specific 'Directed Speed Change' field. The.." hexmask.long.byte 0x74 26.--31. 1. "RSVDP_26,Reserved for future use." newline bitfld.long 0x74 23. "GEN3_EQ_INVREQ_EVAL_DIFF_DISABLE,Eq InvalidRequest and RxEqEval Different Time Assertion Disable. Disable the assertion of Eq InvalidRequest and RxEqEval at different time. Note: When CX_GEN4_SPEED/CX_GEN5_SPEED this register is shared for Gen3 and.." "0,1" newline rbitfld.long 0x74 19.--20. "RSVDP_19,Reserved for future use." "0,1,2,3" newline bitfld.long 0x74 18. "GEN3_DC_BALANCE_DISABLE,DC Balance Disable. Disable DC Balance feature. Note: When CX_GEN4_SPEED/CX_GEN5_SPEED this register is shared for Gen3 and Gen4/Gen5 data rate. Note: This register field is sticky." "0,1" newline bitfld.long 0x74 17. "GEN3_DLLP_XMT_DELAY_DISABLE,DLLP Transmission Delay Disable. Disable delay transmission of DLLPs before equalization. Note: When CX_GEN4_SPEED/CX_GEN5_SPEED this register is shared for Gen3 and Gen4/Gen5 data rate. Note: This register field is sticky." "0,1" newline bitfld.long 0x74 16. "GEN3_EQUALIZATION_DISABLE,Equalization Disable. Disable equalization feature. This bit cannot be changed once the LTSSM starts link training. Note: When CX_GEN4_SPEED/CX_GEN5_SPEED this register is shared for Gen3 and Gen4/Gen5 data rate. Note: This.." "0,1" newline rbitfld.long 0x74 14.--15. "RSVDP_14,Reserved for future use." "0,1,2,3" newline bitfld.long 0x74 13. "RXEQ_RGRDLESS_RXTS,When set to '1' the controller as Gen3 EQ master asserts RxEqEval to instruct the PHY to do Rx adaptation and evaluation after a 500ns timeout from a new preset request. - 0: mac_phy_rxeqeval asserts after 1us and 2 TS1 received from.." "mac_phy_rxeqeval asserts after 1us and 2 TS1..,mac_phy_rxeqeval asserts after 500ns regardless.." newline bitfld.long 0x74 12. "RXEQ_PH01_EN,Rx Equalization Phase 0/Phase 1 Hold Enable. When this bit is set the upstream port holds phase 0 (the downstream port holds phase 1) for 10ms. Holding phase 0 or phase 1 can be used to allow sufficient time for Rx Equalization to be.." "Tx equalization only in phase 2/3,No Tx equalization" newline bitfld.long 0x74 11. "EQ_REDO,Equalization Redo Disable. Disable autonomous mechanism for requesting to redo the equalization process. The received presets or coefficients mismatch in Recovery.RcvrLock after Recovery EQ phases causes the EQ redo requests. If the EQ redo is.." "0,1" newline bitfld.long 0x74 10. "EQ_EIEOS_CNT,Equalization EIEOS Count Reset Disable. Disable requesting reset of EIEOS count during equalization. Note: When CX_GEN4_SPEED/CX_GEN5_SPEED this register is shared for Gen3 and Gen4/Gen5 data rate. Note: This register field is sticky." "0,1" newline bitfld.long 0x74 9. "EQ_PHASE_2_3,Equalization Phase 2 and Phase 3 Disable. This applies to downstream ports only. Note: When CX_GEN4_SPEED/CX_GEN5_SPEED this register is shadow register for Gen3 and Gen4/Gen5 data rate. If RATE_SHADOW_SEL==00b this register is for Gen3.." "0,1" newline bitfld.long 0x74 8. "DISABLE_SCRAMBLER_GEN_3,Disable Scrambler for Gen3 and Gen4 Data Rate. The Gen3 and Gen4 scrambler/descrambler within the controller needs to be disabled when the scrambling function is implemented outside of the controller (for example within the PHY)." "0,1" newline hexmask.long.byte 0x74 1.--7. 1. "RSVDP_1,Reserved for future use." newline bitfld.long 0x74 0. "GEN3_ZRXDC_NONCOMPL,Gen3 Receiver Impedance ZRX-DC Not Compliant. Receivers that operate at 8.0 GT/s with an impedance other than the range defined by the ZRX-DC parameter for 2.5 GT/s (40-60 Ohms) must meet additional behavior requirements in the.." "The receiver complies with the ZRX-DC parameter..,The receiver does not comply with the ZRX-DC.." group.long (0x1A8+0x700)++0x7 line.long 0x0 "GEN3_EQ_CONTROL_OFF,Gen3 EQ Control Register. This register controls equalization for Phase2 in an upstream port (USP). or Phase3 in a downstream port (DSP). M-PCIe doesn't have Conventional PCIe Gen3 feature. The registers of this section do not exist." hexmask.long.byte 0x0 27.--31. 1. "RSVDP_27,Reserved for future use." newline bitfld.long 0x0 26. "GEN3_REQ_SEND_CONSEC_EIEOS_FOR_PSET_MAP,Request controller to send back-to-back EIEOS in Recovery.RcvrLock state until presets to coefficients mapping is complete. - 0: Do not request - 1: request Note: Gen3 and Gen4 share the same register bit and have.." "Do not request,request" newline bitfld.long 0x0 25. "GEN3_EQ_PSET_REQ_AS_COEF,GEN3_EQ_PSET_REQ_AS_COEF is an internally reserved field. Do not use. Note: This register field is sticky." "0,1" newline bitfld.long 0x0 24. "GEN3_EQ_FOM_INC_INITIAL_EVAL,Include Initial FOM. Include or not the FOM feedback from the initial preset evaluation performed in the EQ Master when finding the highest FOM among all preset evaluations. - 0: Do not include - 1: Include Note: When.." "Do not include,Include" newline hexmask.long.word 0x0 8.--23. 1. "GEN3_EQ_PSET_REQ_VEC,Preset Request Vector. Requesting of Presets during the initial part of the EQ Master Phase. Encoding scheme is as follows: Bit [15:0] =0x0: No preset is requested and evaluated in EQ Master Phase. Bit [i] =1: 'Preset=i' is requested.." newline rbitfld.long 0x0 7. "RSVDP_7,Reserved for future use." "0,1" newline bitfld.long 0x0 6. "GEN3_LOWER_RATE_EQ_REDO_ENABLE,Support EQ redo and lower rate change: - 0: not support - 1: support Note: Gen3 and Gen4 share the same register bit and have the same feature. Note: This register field is sticky." "not support,support" newline bitfld.long 0x0 5. "GEN3_EQ_EVAL_2MS_DISABLE,Phase2_3 2 ms Timeout Disable. Determine behavior in Phase2 for USP (Phase3 if DSP) when the PHY does not respond within 2ms to the assertion of RxEqEval: - 0: abort the current evaluation stop any attempt to modify the remote.." "abort the current evaluation,ignore the 2ms timeout and continue as normal" newline bitfld.long 0x0 4. "GEN3_EQ_PHASE23_EXIT_MODE,Behavior After 24 ms Timeout (when optimal settings are not found). For a USP: Determine next LTSSM state from Phase2 after 24ms Timeout - 0: Recovery.Speed - 1: Recovery.Equalization.Phase3 When optimal settings are not found.." "Equalization Phase 3 Successful status bit is..,Recovery" newline hexmask.long.byte 0x0 0.--3. 1. "GEN3_EQ_FB_MODE,Feedback Mode. - 0000b: Direction Change - 0001b: Figure Of Merit - 0010b: Reserved - .....: Reserved - 1111b: Reserved Note: When CX_GEN4_SPEED/CX_GEN5_SPEED this register is a shadow register for Gen3 and Gen4/Gen5 data rate. If.." line.long 0x4 "GEN3_EQ_FB_MODE_DIR_CHANGE_OFF,Gen3 EQ Direction Change Feedback Mode Control Register. Equalization controls to be used in Phase2 (USP) or Phase 3 (DSP). when you set the Feedback Mode in 'Gen3 EQ Control Register' to 'Direction Change.' These fields.." hexmask.long.word 0x4 18.--31. 1. "RSVDP_18,Reserved for future use." newline hexmask.long.byte 0x4 14.--17. 1. "GEN3_EQ_FMDC_MAX_POST_CUSROR_DELTA,Convergence Window Aperture for C+1. Post-cursor coefficients maximum delta within the convergence window depth. Allowed range: 0 1 2 ..15. Note: When CX_GEN4_SPEED/CX_GEN5_SPEED this register is shadow register for.." newline hexmask.long.byte 0x4 10.--13. 1. "GEN3_EQ_FMDC_MAX_PRE_CUSROR_DELTA,Convergence Window Aperture for C-1. Pre-cursor coefficients maximum delta within the convergence window depth. Allowed range: 0 1 2 ..15. Note: When CX_GEN4_SPEED/CX_GEN5_SPEED this register is shadow register for Gen3.." newline hexmask.long.byte 0x4 5.--9. 1. "GEN3_EQ_FMDC_N_EVALS,Convergence Window Depth. Number of consecutive evaluations considered in Phase 2/3 when determining if optimal coefficients have been found. Allowed range: 0 1 2 ..16 up to a maximum of CX_GEN3_EQ_COEFQ_DEPTH. When set to 0 EQ.." newline hexmask.long.byte 0x4 0.--4. 1. "GEN3_EQ_FMDC_T_MIN_PHASE23,Minimum Time (in ms) To Remain in EQ Master Phase. The LTSSM stays in EQ Master phase for at least this amount of time before starting to check for convergence of the coefficients. Allowed values 0 1 ... 24. Note: When.." group.long (0x1B4+0x700)++0x27 line.long 0x0 "ORDER_RULE_CTRL_OFF,Order Rule Control Register." hexmask.long.word 0x0 16.--31. 1. "RSVDP_16,Reserved for future use." newline hexmask.long.byte 0x0 8.--15. 1. "CPL_PASS_P,Completion Passing Posted Ordering Rule Control. Determines if CPL can pass halted P queue. - 0: CPL can not pass P (recommended) - 1: CPL can pass P" newline hexmask.long.byte 0x0 0.--7. 1. "NP_PASS_P,Non-Posted Passing Posted Ordering Rule Control. Determines if NP can pass halted P queue. - 0 : NP can not pass P (recommended). - 1 : NP can pass P" line.long 0x4 "PIPE_LOOPBACK_CONTROL_OFF,PIPE Loopback Control Register." bitfld.long 0x4 31. "PIPE_LOOPBACK,PIPE Loopback Enable. Indicates RMMI Loopback if M-PCIe. Note: This register field is sticky." "0,1" newline hexmask.long.byte 0x4 27.--30. 1. "RSVDP_27,Reserved for future use." newline bitfld.long 0x4 24.--26. "RXSTATUS_VALUE,RXSTATUS_VALUE is an internally reserved field. Do not use." "0,1,2,3,4,5,6,7" newline rbitfld.long 0x4 22.--23. "RSVDP_22,Reserved for future use." "0,1,2,3" newline hexmask.long.byte 0x4 16.--21. 1. "RXSTATUS_LANE,RXSTATUS_LANE is an internally reserved field. Do not use. Note: This register field is sticky." newline hexmask.long.word 0x4 0.--15. 1. "LPBK_RXVALID,LPBK_RXVALID is an internally reserved field. Do not use. Note: This register field is sticky." line.long 0x8 "MISC_CONTROL_1_OFF,DBI Read-Only Write Enable Register." hexmask.long.word 0x8 22.--31. 1. "RSVDP_22,Reserved for future use." newline bitfld.long 0x8 21. "P2P_ERR_RPT_CTRL,Determines whether to track completion of transmitted Non-Posted TLPs in P2P mode. - 0: Do not track completion - 1: Track completion Note: This register field is sticky." "Do not track completion,Track completion" newline bitfld.long 0x8 20. "P2P_TRACK_CPL_TO_REG,Determines whether to enable Peer to Peer (P2P) error reporting. - 0: Disable P2P error reporting - 1: Enable P2P error reporting Note: This register field is sticky." "Disable P2P error reporting,Enable P2P error reporting" newline bitfld.long 0x8 18.--19. "TARGET_ABOVE_CONFIG_LIMIT_REG,Configuration requests with an address greater than CONFIG_LIMIT_REG are directed to either ELBI or TRGT1 interface based on the setting of this field. This field can have the following values: - 1: ELBI - 2: TRGT1 Note:.." "?,ELBI,TRGT1,?" newline hexmask.long.word 0x8 8.--17. 1. "CONFIG_LIMIT_REG,Configuration requests are directed either to CDM or ELBI/RTRGT1 based on the value of this field. - Configuration requests with an address less CONFIG_LIMIT_REG are directed to the CDM - Configuration requests with an address greater.." newline bitfld.long 0x8 7. "CFG_TLP_BYPASS_EN_REG,Setting of this field defines which field TARGET_ABOVE_CONFIG_LIMIT_REG or CONFIG_LIMIT_REG decides the destination of Configuration requests. This field can have the following values: - 0: Configuration TLPs are routed according to.." "Configuration TLPs are routed according to the..,Configuration TLPs are routed according to the.." newline bitfld.long 0x8 6. "CPLQ_MNG_EN,This field enables the Completion Queue Management feature. Note: This register field is sticky." "0,1" newline bitfld.long 0x8 5. "ARI_DEVICE_NUMBER,When ARI is enabled this field enables use of the device ID. Note: This register field is sticky." "0,1" newline bitfld.long 0x8 4. "DISABLE_AUTO_LTR_CLR_MSG,Disable the autonomous generation of LTR clear message in upstream port. This field can have the following values: - 0: Allow the autonomous generation of LTR clear message. - 1: Disable the autonomous generation of LTR clear.." "Allow the autonomous generation of LTR clear..,Disable the autonomous generation of LTR clear.." newline bitfld.long 0x8 3. "SIMPLIFIED_REPLAY_TIMER,Enables Simplified Replay Timer (Gen4). For more details see 'Transmit Replay' in 'Transmit TLP Processing' section in the 'Controller Operations' chapter of the Databook. Simplified Replay Timer can have the following Values: -.." "0,1" newline bitfld.long 0x8 2. "UR_CA_MASK_4_TRGT1,When this field is set to '1' the controller suppresses error logging error message generation and CPL generation for non-posted requests TLPs (with UR filtering status) forwarded to your application (that is when DEFAULT_TARGET.." "0,1" newline bitfld.long 0x8 1. "DEFAULT_TARGET,Default target for an IO or MEM request with UR/CA/CRS received. Based on the value of this field the controller either drops or forwards these requests to your application. - 0: The controller drops all incoming I/O or MEM requests (after.." "The controller drops all incoming I/O or MEM..,The controller forwards all incoming I/O or MEM.." newline bitfld.long 0x8 0. "DBI_RO_WR_EN,Write to RO Registers Using DBI. Your application can write to some RO and HwInit register fields through the DBI when you set this field to '1'. For more details see 'Writing to Read-Only Registers' in 'Register Module LBC and DBI'.." "0,1" line.long 0xC "MULTI_LANE_CONTROL_OFF,UpConfigure Multi-lane Control Register. Used when upsizing or downsizing the link width through Configuration state without bringing the link down. For more details. see the 'Link Establishment' section in the 'Controller.." hexmask.long.tbyte 0xC 8.--31. 1. "RSVDP_8,Reserved for future use." newline bitfld.long 0xC 7. "UPCONFIGURE_SUPPORT,Upconfigure Support. The controller sends this value as the Link Upconfigure Capability in TS2 Ordered Sets in Configuration.Complete state. This field is reserved (fixed to '0') for M-PCIe. Note: This register field is sticky." "0,1" newline bitfld.long 0xC 6. "DIRECT_LINK_WIDTH_CHANGE,Directed Link Width Change. The controller always moves to Configuration state through Recovery state when this bit is set to '1'. - If the upconfigure_capable variable is '1' and the PCIE_CAP_HW_AUTO_WIDTH_DISABLE bit in.." "0,1" newline hexmask.long.byte 0xC 0.--5. 1. "TARGET_LINK_WIDTH,Target Link Width. Values correspond to: - 6'b000000: Controller does not start upconfigure or autonomous width downsizing in the Configuration state. - 6'b000001: x1 - 6'b000010: x2 - 6'b000100: x4 - 6'b001000: x8 - 6'b010000: x16 -.." line.long 0x10 "PHY_INTEROP_CTRL_OFF,PHY Interoperability Control Register." hexmask.long.tbyte 0x10 12.--31. 1. "RSVDP_12,Reserved for future use." newline bitfld.long 0x10 10. "L1_CLK_SEL,L1 Clock control bit. This field is reserved for internal use. You should not write to this field and change the default unless specifically instructed by Synopsys support. - 1: Controller does not request aux_clk switch and core_clk gating in.." "Controller requests aux_clk switch and core_clk..,Controller does not request aux_clk switch and.." newline rbitfld.long 0x10 9. "L1_NOWAIT_P1,L1 entry control bit. This field is reserved for internal use. You should not write to this field and change the default unless specifically instructed by Synopsys support. - 1: Controller does not wait for PHY to acknowledge transition to.." "Controller waits for the PHY to acknowledge..,Controller does not wait for PHY to acknowledge.." newline bitfld.long 0x10 8. "L1SUB_EXIT_MODE,L1 Exit Control Using phy_mac_pclkack_n. This field is reserved for internal use. You should not write to this field and change the default unless specifically instructed by Synopsys support. - 1: Controller exits L1 without waiting for.." "Controller waits for the PHY to assert..,Controller exits L1 without waiting for the PHY.." newline rbitfld.long 0x10 7. "RSVDP_7,Reserved for future use." "0,1" newline hexmask.long.byte 0x10 0.--6. 1. "RXSTANDBY_CONTROL,Rxstandby Control. Bits 0..5 determine if the controller asserts the RxStandby signal (mac_phy_rxstandby) in the indicated condition. Bit 6 enables the controller to perform the RxStandby/RxStandbyStatus handshake. This field is.." line.long 0x14 "TRGT_CPL_LUT_DELETE_ENTRY_OFF,TRGT_CPL_LUT Delete Entry Control register. Using this register you can delete one entry in the target completion LUT. You should only use this register when you know that your application will never send the completion.." bitfld.long 0x14 31. "DELETE_EN,This is a one-shot bit. A '1' write to this bit triggers the deletion of the target completion LUT entry that is specified in the LOOK_UP_ID field. This is a self-clearing register field. Reading from this register field always returns a '0'." "0,1" newline hexmask.long 0x14 0.--30. 1. "LOOK_UP_ID,This number selects one entry to delete of the TRGT_CPL_LUT." line.long 0x18 "LINK_FLUSH_CONTROL_OFF,Link Reset Request Flush Control Register." hexmask.long.byte 0x18 24.--31. 1. "RSVD_I_8,This is an internally reserved field. Do not use. Note: This register field is sticky." newline hexmask.long.tbyte 0x18 1.--23. 1. "RSVDP_1,Reserved for future use." newline bitfld.long 0x18 0. "AUTO_FLUSH_EN,Enables automatic flushing of pending requests before sending the reset request to the application logic to reset the PCIe controller and the AXI Bridge. The flushing process is initiated if any of the following events occur: - Hot reset.." "0,1" line.long 0x1C "AMBA_ERROR_RESPONSE_DEFAULT_OFF,AXI Bridge Slave Error Response Register." hexmask.long.word 0x1C 16.--31. 1. "RSVDP_16,Reserved for future use." newline hexmask.long.byte 0x1C 10.--15. 1. "AMBA_ERROR_RESPONSE_MAP,AXI Slave Response Error Map. Allows you to selectively map the errors received from the PCIe completion (for non-posted requests) to the AXI slave responses slv_rresp or slv_bresp. The recommended setting is SLVERR. CRS is.." newline hexmask.long.byte 0x1C 5.--9. 1. "RSVDP_5,Reserved for future use." newline bitfld.long 0x1C 3.--4. "AMBA_ERROR_RESPONSE_CRS,CRS Slave Error Response Mapping. Determines the AXI slave response for CRS completions. For more details see 'Error Handling' in the AXI chapter of the Databook. AHB: - always returns OKAY AXI: - 00: OKAY - 01: OKAY with all.." "OKAY,OKAY with all FFFF_FFFF data for all CRS..,?,?" newline bitfld.long 0x1C 2. "AMBA_ERROR_RESPONSE_VENDORID,Vendor ID Non-existent Slave Error Response Mapping. Determines the AXI slave response for errors on reads to non-existent Vendor ID register. For more details see 'Error Handling' in the AXI chapter of the Databook. AHB: -.." "OKAY,SLVERR/DECERR" newline rbitfld.long 0x1C 1. "RSVDP_1,Reserved for future use." "0,1" newline bitfld.long 0x1C 0. "AMBA_ERROR_RESPONSE_GLOBAL,Global Slave Error Response Mapping. Determines the AXI slave response for all error scenarios on non-posted requests. For more details see 'Error Handling' in the AXI chapter of the Databook. AHB: - 0: OKAY (with FFFF data for.." "OKAY,SLVERR/DECERR" line.long 0x20 "AMBA_LINK_TIMEOUT_OFF,Link Down AXI Bridge Slave Timeout Register. If your application AXI master issues outbound requests to the AXI bridge slave interface before the PCIe link is operational. the controller starts a 'flush' timer. The timeout value of.." hexmask.long.tbyte 0x20 9.--31. 1. "RSVDP_9,Reserved for future use." newline bitfld.long 0x20 8. "LINK_TIMEOUT_ENABLE_DEFAULT,Disable Flush. You can disable the flush feature by setting this field to '1'. Note: This register field is sticky." "0,1" newline hexmask.long.byte 0x20 0.--7. 1. "LINK_TIMEOUT_PERIOD_DEFAULT,Timeout Value (ms). The timer will timeout and then flush the bridge TX request queues after this amount of time. The timer counts when there are pending outbound AXI slave interface requests and the PCIe TX link is not.." line.long 0x24 "AMBA_ORDERING_CTRL_OFF,AMBA Ordering Control." hexmask.long.tbyte 0x24 8.--31. 1. "RSVDP_8,Reserved for future use." newline bitfld.long 0x24 7. "AX_MSTR_ZEROLREAD_FW,AXI Master Zero Length Read Forward to the application. The DW PCIe controller AXI bridge is able to terminate in order with the Posted transactions the zero length read implementing the PCIe express flush semantics of the Posted.." "The zero length Read is terminated at the DW..,The zero length Read is forward to the application" newline rbitfld.long 0x24 5.--6. "RSVDP_5,Reserved for future use." "0,1,2,3" newline bitfld.long 0x24 3.--4. "AX_MSTR_ORDR_P_EVENT_SEL,AXI Master Posted Ordering Event Selector. This field selects how the master interface determines when a P write is completed when enforcing the PCIe ordering rule 'NP must not pass P' at the AXI Master Interface. The AXI.." "B'last event: wait for the all of the write..,AW'last event: wait until the complete Posted..,This setting will not affect:,?" newline rbitfld.long 0x24 2. "RSVDP_2,Reserved for future use." "0,1" newline bitfld.long 0x24 1. "AX_SNP_EN,AXI Serialize Non-Posted Requests Enable. This field enables the AXI Bridge to serialize same ID Non-Posted Read/Write Requests on the wire. Serialization implies one outstanding same ID NP Read or Write on the wire and used to avoid AXI RAR.." "0,1" newline rbitfld.long 0x24 0. "RSVDP_0,Reserved for future use." "0,1" group.long (0x1E0+0x700)++0xB line.long 0x0 "COHERENCY_CONTROL_1_OFF,ACE Cache Coherency Control Register 1" hexmask.long 0x0 2.--31. 1. "CFG_MEMTYPE_BOUNDARY_LOW_ADDR,Boundary Lower Address For Memory Type. Bits [31:0] of dword-aligned address of the boundary for Memory type. The two lower address LSBs are '00'. Addresses up to but not including this value are in the lower address space.." newline rbitfld.long 0x0 1. "RSVDP_1,Reserved for future use." "0,1" newline bitfld.long 0x0 0. "CFG_MEMTYPE_VALUE,Sets the memory type for the lower and upper parts of the address space: - 0: lower = Peripheral; upper = Memory - 1: lower = Memory type; upper = Peripheral Note: This register field is sticky." "lower = Peripheral; upper = Memory,lower = Memory type; upper = Peripheral" line.long 0x4 "COHERENCY_CONTROL_2_OFF,ACE Cache Coherency Control Register 2" hexmask.long 0x4 0.--31. 1. "CFG_MEMTYPE_BOUNDARY_HIGH_ADDR,Boundary Upper Address For Memory Type. Bits [63:32] of the 64-bit dword-aligned address of the boundary for Memory type. Note: This register field is sticky." line.long 0x8 "COHERENCY_CONTROL_3_OFF,ACE Cache Coherency Control Register 3" hexmask.long.byte 0x8 27.--30. 1. "CFG_MSTR_AWCACHE_VALUE,Master Write CACHE Signal Value. Value of the individual bits in mstr_awcache when CFG_MSTR_AWCACHE_MODE is '1'. Note: not applicable to message requests; for message requests the value of mstr_awcache is always '0000' Note: This.." newline hexmask.long.byte 0x8 19.--22. 1. "CFG_MSTR_ARCACHE_VALUE,Master Read CACHE Signal Value. Value of the individual bits in mstr_arcache when CFG_MSTR_ARCACHE_MODE is '1'. Note: This register field is sticky." newline hexmask.long.byte 0x8 11.--14. 1. "CFG_MSTR_AWCACHE_MODE,Master Write CACHE Signal Behavior. Defines how the individual bits in mstr_awcache are controlled: - 0: set automatically by the AXI master - 1: set by the value of the corresponding bit of the CFG_MSTR_AWCACHE_VALUE field Note:.." newline hexmask.long.byte 0x8 3.--6. 1. "CFG_MSTR_ARCACHE_MODE,Master Read CACHE Signal Behavior. Defines how the individual bits in mstr_arcache are controlled: - 0: set automatically by the AXI master - 1: set by the value of the corresponding bit of the CFG_MSTR_ARCACHE_VALUE field Note:.." group.long (0x1F0+0x700)++0x7 line.long 0x0 "AXI_MSTR_MSG_ADDR_LOW_OFF,Lower 20 bits of the programmable AXI address where Messages coming from wire are mapped to. Bits [11:0] of the register are tied to zero for the address to be 4k-aligned. In previous releases. the third and fourth DWORDs of a.." hexmask.long.tbyte 0x0 12.--31. 1. "CFG_AXIMSTR_MSG_ADDR_LOW,Lower 20 bits of the programmable AXI address for Messages. Note: This register field is sticky." newline hexmask.long.word 0x0 0.--11. 1. "CFG_AXIMSTR_MSG_ADDR_LOW_RESERVED,Reserved for future use. Note: This register field is sticky." line.long 0x4 "AXI_MSTR_MSG_ADDR_HIGH_OFF,Upper 32 bits of the programmable AXI address where Messages coming from wire are mapped to." hexmask.long 0x4 0.--31. 1. "CFG_AXIMSTR_MSG_ADDR_HIGH,Upper 32 bits of the programmable AXI address for Messages. Note: This register field is sticky." rgroup.long (0x1F8+0x700)++0x7 line.long 0x0 "PCIE_VERSION_NUMBER_OFF,PCIe Controller IIP Release Version Number. The version number is given in hex format. You should convert each pair of hex characters to ASCII to interpret. Using 4.70a (GA) as an example: - VERSION_NUMBER = 0x3437302a which.." hexmask.long 0x0 0.--31. 1. "VERSION_NUMBER,Version Number." line.long 0x4 "PCIE_VERSION_TYPE_OFF,PCIe Controller IIP Release Version Type. The type is given in hex format. You should convert each pair of hex characters to ASCII to interpret. Using 4.70a (GA) as an example: - VERSION_NUMBER = 0x3437302a which translates to 470*.." hexmask.long 0x4 0.--31. 1. "VERSION_TYPE,Version Type." group.long (0x240+0x700)++0x7 line.long 0x0 "MSIX_ADDRESS_MATCH_LOW_OFF,MSI-X Address Match Low Register. When you enable the MSI-X Table RAM feature (MSIX_TABLE_EN=1). the controller implements the logic and RAM required to generate MSI-X requests. For more details. see the Interrupts section in.." hexmask.long 0x0 2.--31. 1. "MSIX_ADDRESS_MATCH_LOW,MSI-X Address Match Low Address. Note: This register field is sticky." newline rbitfld.long 0x0 1. "MSIX_ADDRESS_MATCH_RESERVED_1,Reserved. Note: This register field is sticky." "0,1" newline bitfld.long 0x0 0. "MSIX_ADDRESS_MATCH_EN,MSI-X Match Enable. Enable the MSI-X Address Match feature when the AXI bridge is present. Note: This register field is sticky." "0,1" line.long 0x4 "MSIX_ADDRESS_MATCH_HIGH_OFF,MSI-X Address Match High Register. When you enable the MSI-X Table RAM feature (MSIX_TABLE_EN=1). the controller implements the logic and RAM required to generate MSI-X requests. For more details. see the Interrupts section in.." hexmask.long 0x4 0.--31. 1. "MSIX_ADDRESS_MATCH_HIGH,MSI-X Address Match High Address. Note: This register field is sticky." wgroup.long (0x248+0x700)++0x3 line.long 0x0 "MSIX_DOORBELL_OFF,MSI-X Doorbell Register. When you enable the MSI-X Table RAM feature (MSIX_TABLE_EN=1). the controller implements the logic and RAM required to generate MSI-X requests. For more details. see the Interrupts section in the 'Controller.." bitfld.long 0x0 29.--31. "MSIX_DOORBELL_RESERVED_29_31,Reserved." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x0 24.--28. 1. "MSIX_DOORBELL_PF,MSIX Doorbell Physical Function. This register determines the Physical Function for the MSI-X transaction." newline hexmask.long.byte 0x0 16.--23. 1. "MSIX_DOORBELL_VF,MSIX Doorbell Virtual Function. This register determines the Virtual Function for the MSI-X transaction." newline bitfld.long 0x0 15. "MSIX_DOORBELL_VF_ACTIVE,MSIX Doorbell Virtual Function Active. This register determines whether a Virtual Function is used to generate the MSI-X transaction." "0,1" newline bitfld.long 0x0 12.--14. "MSIX_DOORBELL_TC,MSIX Doorbell Traffic Class. This register determines which traffic class to generate the MSI-X transaction with." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 11. "MSIX_DOORBELL_RESERVED_11,Reserved." "0,1" newline hexmask.long.word 0x0 0.--10. 1. "MSIX_DOORBELL_VECTOR,MSI-X Doorbell Vector. This register determines which vector to generate the MSI-X transaction for." group.long (0x24C+0x700)++0x3 line.long 0x0 "MSIX_RAM_CTRL_OFF,MSI-X RAM power mode and debug control register. When you enable the MSI-X Table RAM feature (MSIX_TABLE_EN=1). the controller implements the logic and RAM required to generate MSI-X requests. For more details. see the Interrupts.." hexmask.long.byte 0x0 26.--31. 1. "MSIX_RAM_CTRL_RESERVED_26_31,Reserved. Note: This register field is sticky." newline bitfld.long 0x0 25. "MSIX_RAM_CTRL_DBG_PBA,MSIX PBA RAM Debug Mode. Use this bit to activate the debug mode and allow direct read/write access to the PBA. Use can also use the dbg_pba input to activate debug mode. Debug mode turns off the PF/VF/Offset-based addressing into.." "0,1" newline bitfld.long 0x0 24. "MSIX_RAM_CTRL_DBG_TABLE,MSIX Table RAM Debug Mode. Use this bit to activate the debug mode and allow direct read/write access to the Table. Use can also use the dbg_table input to activate debug mode. Debug mode turns off the PF/VF/Offset-based.." "0,1" newline hexmask.long.byte 0x0 17.--23. 1. "MSIX_RAM_CTRL_RESERVED_17_23,Reserved. Note: This register field is sticky." newline bitfld.long 0x0 16. "MSIX_RAM_CTRL_BYPASS,MSIX RAM Control Bypass. The bypass field when set disables the internal generation of low power signals for both RAMs. It is up to the application to ensure the RAMs are in the proper power state before trying to access them." "0,1" newline hexmask.long.byte 0x0 10.--15. 1. "MSIX_RAM_CTRL_RESERVED_10_15,Reserved. Note: This register field is sticky." newline bitfld.long 0x0 9. "MSIX_RAM_CTRL_PBA_SD,MSIX PBA RAM Shut Down. Set this bit to drive the cfg_msix_pba_sd output to signal your external logic to place the MSIX PBA RAM in Shut Down low-power mode. Note: This register field is sticky." "0,1" newline bitfld.long 0x0 8. "MSIX_RAM_CTRL_PBA_DS,MSIX PBA RAM Deep Sleep. Set this bit to drive the cfg_msix_pba_ds output to signal your external logic to place the MSIX PBA RAM in Deep Sleep low-power mode. Note: This register field is sticky." "0,1" newline hexmask.long.byte 0x0 2.--7. 1. "MSIX_RAM_CTRL_RESERVED_2_7,Reserved. Note: This register field is sticky." newline bitfld.long 0x0 1. "MSIX_RAM_CTRL_TABLE_SD,MSIX Table RAM Shut Down. Set this bit to drive the cfg_msix_table_sd output to signal your external logic to place the MSIX Table RAM in Shut Down low-power mode. Note: This register field is sticky." "0,1" newline bitfld.long 0x0 0. "MSIX_RAM_CTRL_TABLE_DS,MSIX Table RAM Deep Sleep. Set this bit to drive the cfg_msix_table_ds output to signal your external logic to place the MSIX Table RAM in Deep Sleep low-power mode. Note: This register field is sticky." "0,1" group.long (0x430+0x700)++0x3 line.long 0x0 "PL_LTR_LATENCY_OFF,LTR Latency Register. The function of this register field (and all other fields in this register) differs between an upstream port and a downstream port. For an upstream port. the register fields capture the corresponding fields in the.." bitfld.long 0x0 31. "NO_SNOOP_LATENCY_REQUIRE,No Snoop Latency Requirement. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" "0,1" newline rbitfld.long 0x0 29.--30. "RSVDP_29,Reserved for future use." "0,1,2,3" newline bitfld.long 0x0 26.--28. "NO_SNOOP_LATENCY_SCALE,No Snoop Latency Scale. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" "0,1,2,3,4,5,6,7" newline hexmask.long.word 0x0 16.--25. 1. "NO_SNOOP_LATENCY_VALUE,No Snoop Latency Value. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" newline bitfld.long 0x0 15. "SNOOP_LATENCY_REQUIRE,Snoop Latency Requirement. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" "0,1" newline rbitfld.long 0x0 13.--14. "RSVDP_13,Reserved for future use." "0,1,2,3" newline bitfld.long 0x0 10.--12. "SNOOP_LATENCY_SCALE,Snoop Latency Scale. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" "0,1,2,3,4,5,6,7" newline hexmask.long.word 0x0 0.--9. 1. "SNOOP_LATENCY_VALUE,Snoop Latency Value. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" group.long (0x440+0x700)++0xB line.long 0x0 "AUX_CLK_FREQ_OFF,Auxiliary Clock Frequency Control Register." hexmask.long.tbyte 0x0 10.--31. 1. "RSVDP_10,Reserved for future use." newline hexmask.long.word 0x0 0.--9. 1. "AUX_CLK_FREQ,The aux_clk frequency in MHz. This value is used to provide a 1 us reference for counting time during low-power states with aux_clk when the PHY has removed the pipe_clk. Frequencies lower than 1 MHz are possible but with a loss of accuracy.." line.long 0x4 "L1_SUBSTATES_OFF,L1 Substates Timing Register." hexmask.long.tbyte 0x4 9.--31. 1. "RSVDP_9,Reserved for future use." newline bitfld.long 0x4 8. "L1SUB_LOW_POWER_CLOCK_SWITCH_MODE,If this bit is set to 1'b1 the reference clock will be running regardless of the CLKREQ# setting. If this bit is set to 1'b0 the reference clock may be gated off when CLKREQ# is de-asserted. If the bit is set to 1'b1 the.." "0,1" newline bitfld.long 0x4 6.--7. "L1SUB_T_PCLKACK,Max delay (in 1us units) between a MAC request to remove the clock on mac_phy_pclkreq_n and a PHY response on phy_mac_pclkack_n. If the PHY does not respond within this time the request is aborted.The actual timeout value will be.." "0,1,2,3" newline hexmask.long.byte 0x4 2.--5. 1. "L1SUB_T_L1_2,Duration (in 1us units) of L1.2. The actual timeout value will be L1SUB_T_L1_2 + 1. Range is 0.15. Note: This register field is sticky." newline bitfld.long 0x4 0.--1. "L1SUB_T_POWER_OFF,Duration (in 1us units) of L1.2.Entry. The actual timeout value will be L1SUB_T_POWER_OFF + 1. Range is 0.3. Note: This register field is sticky." "0,1,2,3" line.long 0x8 "POWERDOWN_CTRL_STATUS_OFF,Powerdown Control and Status Register." hexmask.long.tbyte 0x8 12.--31. 1. "RSVDP_12,Reserved for future use." newline hexmask.long.byte 0x8 8.--11. 1. "POWERDOWN_PHY_POWERDOWN,This field represents the Powerdown value that has been acknowledged by the PHY. It is updated with the value of Powerdown driven by the controller when the PHY has returned the Phystatus acknowledgment for the Powerdown.." newline hexmask.long.byte 0x8 4.--7. 1. "POWERDOWN_MAC_POWERDOWN,This field represents the Powerdown value driven by the controller to the PHY." newline rbitfld.long 0x8 1.--3. "RSVDP_1,Reserved for future use." "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 0. "POWERDOWN_FORCE,This field is a one shot field. Writing a value of 1 to this field causes the controller to complete the P2 Powerdown handshake regardless of whether the PHY has returned Phystatus. This field could be used for debug purposes in event.." "0,1" group.long (0x470+0x700)++0x7 line.long 0x0 "PHY_VIEWPORT_CTLSTS_OFF,PHY Register Viewport Control and Status Register." rbitfld.long 0x0 31. "PHY_VIEWPORT_PENDING,PHY viewport pending. Indicates the access is pending. - 1 : Pending - 0 : Idle This bit is set to 1 when the read/write access has been initiated. This bit is cleared when the access is completed. If phy_reg_clk_g is never activated.." "Idle,Pending" newline rbitfld.long 0x0 30. "PHY_VIEWPORT_STATUS,PHY viewport status. Indicates the status of the latest access. - 1 : Timeout - 0 : No errors If the timeout is detected this bit is set to 1 and PHY_VIEWPORT_PENDING is cleared. This bit is cleared when the read/write access is.." "No errors,Timeout" newline hexmask.long.byte 0x0 23.--29. 1. "RSVDP_23,Reserved for future use." newline bitfld.long 0x0 22. "PHY_VIEWPORT_TIMEOUT_DISABLE,PHY viewport timeout disable. Disables the PHY register access timeout structure. When the timeout is disabled you must ensure that the PHY register accesses are always acknowledged by cr_para_ack. Otherwise.." "0,1" newline bitfld.long 0x0 21. "PHY_VIEWPORT_BCWR,Broadcast write access to all xN sub-blocks. If you need to broadcast the write accesses into all lanes both PHY_VIEWPORT_ADDR[15] and this bit should be 1. Note: This register field is sticky." "0,1" newline bitfld.long 0x0 20. "PHY_VIEWPORT_READ,PHY viewport read. If set a read access is initiated. The value is always 0 when this bit is read. Note: This register field is sticky." "0,1" newline hexmask.long.byte 0x0 16.--19. 1. "PHY_VIEWPORT_NUM,PHY viewport xN sub-block number. Selects one of xN sub-blocks. This register is not used when the write access is initiated with PHY_VIEWPORT_BCWR==1. Note: This register field is sticky." newline hexmask.long.word 0x0 0.--15. 1. "PHY_VIEWPORT_ADDR,PHY viewport address. Indicates the PHY's register address. Please refer to the PHY databook for the address map definition. Note: This register field is sticky." line.long 0x4 "PHY_VIEWPORT_DATA_OFF,PHY Register Viewport Data Register." hexmask.long.word 0x4 16.--31. 1. "RSVDP_16,Reserved for future use." newline hexmask.long.word 0x4 0.--15. 1. "PHY_VIEWPORT_DATA,PHY viewport data. A write access to this register initiates the PHY register write access. By a read access to this register this field returns the latest read data from the PHY register. Note: This register field is sticky." group.long (0x490+0x700)++0x3 line.long 0x0 "PIPE_RELATED_OFF,PIPE Related Register. This register controls the pipe's capabitity. control. and status parameters." hexmask.long.tbyte 0x0 9.--31. 1. "RSVDP_9,Reserved for future use." newline bitfld.long 0x0 8. "PIPE_GARBAGE_DATA_MODE,PIPE Garbage Data Mode. - 0: PIPE Spec compliant mode: The MAC discards any symbols received after the electrical idle ordered-set until RxValid is deasserted. - 1: Special PHY Support mode: The MAC discards any symbols received.." "PIPE Spec compliant mode: The MAC discards any..,Special PHY Support mode: The MAC discards any.." tree.end tree.end tree "PCIE1_PF1" base ad:0x31060000 tree "PF0_TYPE1_HDR (PCI-Compatible Configuration Space Header Type1)" group.long 0x0++0x2F line.long 0x0 "TYPE1_DEV_ID_VEND_ID_REG,Device ID and Vendor ID Register." hexmask.long.word 0x0 16.--31. 1. "DEVICE_ID,Device ID. The Device ID register identifies the particular Function. This identifier is allocated by the vendor. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else.." newline hexmask.long.word 0x0 0.--15. 1. "VENDOR_ID,Vendor ID. The Vendor ID register identifies the manufacturer of the Function. Valid vendor identifiers are allocated by the PCI-SIG to ensure uniqueness. It is not permitted to populate this register with a value of FFFFh which is an invalid.." line.long 0x4 "TYPE1_STATUS_COMMAND_REG,Status and Command Register." bitfld.long 0x4 31. "DETECTED_PARITY_ERROR,Detected Parity Error. This bit is set by a Function whenever it receives a Poisoned TLP regardless of the state the Parity Error Response bit in the Command register. The bit is set when the Poisoned TLP is received by a.." "0,1" newline bitfld.long 0x4 30. "SIGNALED_SYS_ERROR,Signaled System Error. This bit is set when a Function sends an ERR_FATAL or ERR_NONFATAL Message and the SERR# Enable bit in the Command register is 1b." "0,1" newline bitfld.long 0x4 29. "RCVD_MASTER_ABORT,Received Master Abort. This bit is set when a Requester receives a Completion with Unsupported Request Completion status. The bit is set when the Unsupported Request is received by a Function's primary side." "0,1" newline bitfld.long 0x4 28. "RCVD_TARGET_ABORT,Received Target Abort. This bit is set when a Requester receives a Completion with Completer Abort Completion status. The bit is set when the Completer Abort is received by a Function's primary side." "0,1" newline bitfld.long 0x4 27. "SIGNALED_TARGET_ABORT,Signaled Target Abort. This bit is set when a Function completes a Posted or Non-Posted Request as a Completer Abort error. This applies to a Function when the Completer Abort was generated by its primary side." "0,1" newline rbitfld.long 0x4 25.--26. "DEV_SEL_TIMING,DEVSEL Timing. This field was originally described in the PCI Local Bus Specification. Its functionality does not apply to PCI Express. The controller hardwires it to 00b." "0,1,2,3" newline bitfld.long 0x4 24. "MASTER_DPE,Master Data Parity Error. This bit is set by a Function if the Parity Error Response bit in the Command register is 1b and either of the following two conditions occurs: - Port receives a Poisoned Completion going downstream - Port transmits a.." "0,1" newline rbitfld.long 0x4 23. "FAST_B2B_CAP,Fast Back-to-Back Transactions Capable. This bit was originally described in the PCI Local Bus Specification. Its functionality does not apply to PCI Express. The controller hardwires this bit to 0b." "0,1" newline rbitfld.long 0x4 22. "RSVDP_22,Reserved for future use." "0,1" newline rbitfld.long 0x4 21. "FAST_66MHZ_CAP,66 MHz Capable. This bit was originally described in the PCI Local Bus Specification. Its functionality does not apply to PCI Express. The controller hardwires this bit to 0b." "0,1" newline rbitfld.long 0x4 20. "CAP_LIST,Capabilities List. Indicates the presence of an Extended Capability list item. Since all PCI Express device Functions are required to implement the PCI Express Capability structure the controller hardwires this bit to 1b." "0,1" newline rbitfld.long 0x4 19. "INT_STATUS,Interrupt Status. When set indicates that an INTx emulation interrupt is pending internally in the Function. INTx emulation interrupts forwarded by Functions from the secondary side are not reflected in this bit. Setting the Interrupt Disable.." "0,1" newline rbitfld.long 0x4 17.--18. "RSVDP_17,Reserved for future use." "0,1,2,3" newline bitfld.long 0x4 16. "IMM_READINESS,Immediate Readiness. This optional bit when set indicates the Function is guaranteed to be ready to successfully complete valid configuration accesses at any time following any reset that the host is capable of issuing Configuration.." "0,1" newline hexmask.long.byte 0x4 11.--15. 1. "RESERV,Reserved." newline bitfld.long 0x4 10. "INT_EN,Interrupt Disable. Controls the ability of a Function to generate INTx emulation interrupts. When set Functions are prevented from asserting INTx interrupts. Note: - Any INTx emulation interrupts already asserted by the Function must be.." "0,1" newline rbitfld.long 0x4 9. "RSVDP_9,Reserved for future use." "0,1" newline bitfld.long 0x4 8. "SERREN,SERR# Enable. When set this bit enables reporting upstream of Non-fatal and Fatal errors detected by the Function. Note: The errors are reported if enabled either through this bit or through the PCI Express specific bits in the Device Control.." "0,1" newline rbitfld.long 0x4 7. "IDSEL,IDSEL Stepping/Wait Cycle Control. This bit was originally described in the PCI Local Bus Specification. Its functionality does not apply to PCI Express. The controller hardwires this bit to 0b." "0,1" newline bitfld.long 0x4 6. "PERREN,Parity Error Response. This bit controls the logging of poisoned TLPs in the Master Data Parity Error bit in the Status register. For more details see the 'Error Registers' section of the PCI Express Base Specification." "0,1" newline rbitfld.long 0x4 5. "VGAPS,VGA Palette Snoop. This bit was originally described in the PCI Local Bus Specification and the PCI-to-PCI Bridge Architecture Specification. Its functionality does not apply to PCI Express. The controller hardwires this bit to 0b." "0,1" newline rbitfld.long 0x4 4. "MWI_EN,Memory Write and Invalidate. This bit was originally described in the PCI Local Bus Specification and the PCI-to-PCI Bridge Architecture Specification. Its functionality does not apply to PCI Express. The controller hardwires this bit to 0b. For.." "0,1" newline rbitfld.long 0x4 3. "SCO,Special Cycle Enable. This bit was originally described in the PCI Local Bus Specification. Its functionality does not apply to PCI Express. The controller hardwires this bit to 0b." "0,1" newline bitfld.long 0x4 2. "BME,Bus Master Enable. This bit controls forwarding of Memory or I/O requests by a port in the Upstream direction. When this bit is 0b Memory and I/O Requests received at a Root Port must be handled as Unsupported Requests (UR) For Non-Posted Requests a.." "0,1" newline bitfld.long 0x4 1. "MSE,Memory Space Enable. This bit controls a Function's response to Memory Space accesses received on its primary side. - When set the Function is enabled to decode the address and further process Memory Space accesses. - When clear all received Memory.." "0,1" newline bitfld.long 0x4 0. "IO_EN,IO Space Enable. This bit controls a Function's response to I/O Space accesses received on its primary side. - When set the Function is enabled to decode the address and further process I/O Space accesses. - When clear all received I/O accesses.." "0,1" line.long 0x8 "TYPE1_CLASS_CODE_REV_ID_REG,Class Code and Revision ID Register." hexmask.long.byte 0x8 24.--31. 1. "BASE_CLASS_CODE,Base Class Code. A code that broadly classifies the type of operation the Function performs. Encodings for base class are provided in the PCI Code and ID Assignment Specification. All unspecified encodings are reserved. Note: The access.." newline hexmask.long.byte 0x8 16.--23. 1. "SUBCLASS_CODE,Sub-Class Code. Specifies a base class sub-class which identifies more specifically the operation of the Function. Encodings for sub-class are provided in the PCI Code and ID Assignment Specification. All unspecified encodings are.." newline hexmask.long.byte 0x8 8.--15. 1. "PROGRAM_INTERFACE,Programming Interface. This field identifies a specific register level programming interface (if any) so that device independent software can interact with the Function. Encodings for interface are provided in the PCI Code and ID.." newline hexmask.long.byte 0x8 0.--7. 1. "REVISION_ID,Revision ID. The value of this field specifies a Function specific revision identifier. The value is chosen by the vendor. Zero is an acceptable value. The Revision ID should be viewed as a vendor defined extension to the Device ID. Note: The.." line.long 0xC "TYPE1_BIST_HDR_TYPE_LAT_CACHE_LINE_SIZE_REG,BIST. Header Type. Latency Timer. and Cache Line Size Register." hexmask.long.byte 0xC 24.--31. 1. "BIST,BIST. This register is used for control and status of BIST. Functions that do not support BIST must hardwire the register to 00h. A Function whose BIST is invoked must not prevent normal operation of the PCI Express Link. Bit descriptions: - [31]:.." newline rbitfld.long 0xC 23. "MULTI_FUNC,Multi-Function Device. - When set indicates that the device may contain multiple Functions but not necessarily. Software is permitted to probe for Functions other than Function 0. - When clear software must not probe for Functions other.." "0,1" newline hexmask.long.byte 0xC 16.--22. 1. "HEADER_TYPE,Header Layout. This field identifies the layout of the second part of the predefined header. The controller uses 000 0001b encoding. The encoding 000 0010b is reserved. This encoding was originally described in the PC Card Standard Electrical.." newline hexmask.long.byte 0xC 8.--15. 1. "LATENCY_MASTER_TIMER,Latency Timer. This register is also referred to as Primary Latency Timer. The Latency Timer was originally described in the PCI Local Bus Specification and the PCI-to-PCI Bridge Architecture Specification. Its functionality does not.." newline hexmask.long.byte 0xC 0.--7. 1. "CACHE_LINE_SIZE,Cache Line Size. The Cache Line Size register is programmed by the system firmware or the operating system to system cache line size. However legacy conventional PCI software may not always be able to program this register correctly.." line.long 0x10 "BAR0_REG,BAR0 Register. System software must build a consistent address map before booting the machine to an operating system. This means it has to determine how much memory is in the system. and how much address space the Functions in the system.." hexmask.long 0x10 4.--31. 1. "BAR0_START,BAR0 Base Address. - Memory Space: Base Address. - IO Space: bits[31:2] are used to map the function into IO space/Base. Address. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R(Sticky)/W(Sticky) if.." newline bitfld.long 0x10 3. "BAR0_PREFETCH,BAR0 Prefetchable. - Memory Space: Set to one if data is pre-fetchable. A Function is permitted to mark a range as prefetchable. If there are no side effects on reads the function returns all bytes on reads regardless of the byte enables.." "0,1" newline bitfld.long 0x10 1.--2. "BAR0_TYPE,BAR0 Type. - Memory Space: Base Address registers that map into Memory Space can be 32 bits or 64 bits wide (to support mapping into a 64-bit address space). The bit encoding is as follows: -- 00: Base register is 32 bits wide and can be mapped.." "Base register is 32 bits wide and can be mapped..,Reserved,?,?" newline bitfld.long 0x10 0. "BAR0_MEM_IO,BAR0 Memory Space Indicator. This bit is used to determine whether the register maps into Memory or I/O Space. Base Address registers that map to Memory Space must return a 0b. Base Address registers that map to I/O Space must return a 1b." "0,1" line.long 0x14 "BAR1_REG,BAR1 Register. System software must build a consistent address map before booting the machine to an operating system. This means it has to determine how much memory is in the system. and how much address space the Functions in the system.." hexmask.long 0x14 4.--31. 1. "BAR1_START,BAR1 Base Address. - Memory Space: Base Address. - IO Space: bits[31:2] are used to map the function into IO space/Base. Address. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R(Sticky)/W(Sticky) if.." newline bitfld.long 0x14 3. "BAR1_PREFETCH,BAR1 Prefetchable. - Memory Space: Set to one if data is pre-fetchable. A Function is permitted to mark a range as prefetchable. If there are no side effects on reads the function returns all bytes on reads regardless of the byte enables.." "0,1" newline bitfld.long 0x14 1.--2. "BAR1_TYPE,BAR1 Type. - Memory Space: Base Address registers that map into Memory Space can be 32 bits or 64 bits wide (to support mapping into a 64-bit address space). The bit encoding is as follows: -- 00: Base register is 32 bits wide and can be mapped.." "Base register is 32 bits wide and can be mapped..,Reserved,?,?" newline bitfld.long 0x14 0. "BAR1_MEM_IO,BAR1 Memory Space Indicator. This bit is used to determine whether the register maps into Memory or I/O Space. Base Address registers that map to Memory Space must return a 0b. Base Address registers that map to I/O Space must return a 1b." "0,1" line.long 0x18 "SEC_LAT_TIMER_SUB_BUS_SEC_BUS_PRI_BUS_REG,Secondary Latency Timer. Subordinate Bus Number. Secondary Bus Number. and Primary Bus Number Register." hexmask.long.byte 0x18 24.--31. 1. "SEC_LAT_TIMER,Secondary Latency Timer. This register does not apply to PCI Express. The controller hardwires it to 00h." newline hexmask.long.byte 0x18 16.--23. 1. "SUB_BUS,Subordinate Bus Number. The Subordinate Bus Number register is used to record the bus number of the highest numbered PCI bus segment which is behind (or subordinate to) the bridge. Configuration software programs the value in this register. The.." newline hexmask.long.byte 0x18 8.--15. 1. "SEC_BUS,Secondary Bus Number. The Secondary Bus Number register is used to record the bus number of the PCI bus segment to which the secondary interface of the bridge is connected. Configuration software programs the value in this register. The bridge.." newline hexmask.long.byte 0x18 0.--7. 1. "PRIM_BUS,Primary Bus Number. This register is not used by PCI Express Functions. It is implemented for compatibility with legacy software." line.long 0x1C "SEC_STAT_IO_LIMIT_IO_BASE_REG,Secondary Status. and I/O Limit and Base Register. The I/O Limit and I/O Base registers are optional and define an address range that is used by the bridge to determine when to forward I/O transactions from one interface to.." bitfld.long 0x1C 31. "SEC_STAT_DPE,Detected Parity Error. This bit is set by a Function when a Poisoned TLP is received by its secondary side regardless of the state the Parity Error Response Enable bit in the Bridge Control register." "0,1" newline bitfld.long 0x1C 30. "SEC_STAT_RCVD_SYS_ERR,Received System Error. This bit is set when the secondary side of a Function receives an ERR_FATAL or ERR_NONFATAL message." "0,1" newline bitfld.long 0x1C 29. "SEC_STAT_RCVD_MSTR_ABRT,Received Master Abort. This bit is set when the secondary side of a Function (for requests initiated by the Type 1 header Function itself) receives a Completion with Unsupported Request Completion status." "0,1" newline bitfld.long 0x1C 28. "SEC_STAT_RCVD_TRGT_ABRT,Received Target Abort. This bit is set when the secondary side of a Function (for requests initiated by the Type 1 header Function itself) receives a Completion with Completer Abort Completion status." "0,1" newline bitfld.long 0x1C 27. "SEC_STAT_SIG_TRGT_ABRT,Signaled Target Abort. This bit is set when the secondary side of the Function (for Requests completed by the Type 1 header Function itself) completes a Posted or Non-Posted request as a Completer Abort error." "0,1" newline rbitfld.long 0x1C 25.--26. "RSVDP_25,Reserved for future use." "0,1,2,3" newline bitfld.long 0x1C 24. "SEC_STAT_MDPE,Master Data Parity Error. This bit is set by a Function if the Parity Error Response Enable bit in the Bridge Control register is set and either of the following two conditions occurs: - Port receives a Poisoned Completion coming Upstream.." "0,1" newline rbitfld.long 0x1C 23. "RSVDP_23,Reserved for future use." "0,1" newline hexmask.long.byte 0x1C 16.--22. 1. "SEC_STAT_RESERV,Reserved." newline hexmask.long.byte 0x1C 12.--15. 1. "IO_LIMIT,I/O Limit Address. These bits correspond to the address[15:12] of IO address range. For the purpose of address decoding the bridge assumes that the lower 12 address bits address[11:0] of the I/O limit address (not implemented in the I/O Limit.." newline rbitfld.long 0x1C 9.--11. "IO_RESERV1,Reserved." "0,1,2,3,4,5,6,7" newline bitfld.long 0x1C 8. "IO_DECODE_BIT8,I/O Addressing Encode (IO Limit Address). This bit encodes the IO addressing capability of the bridge. IO_DECODE_BIT8 indicates the following: - 0h: The bridge supports only 16-bit I/O addressing (for ISA compatibility). For the purpose of.." "0,1" newline hexmask.long.byte 0x1C 4.--7. 1. "IO_BASE,I/O Base Address. These bits correspond to the address[15:12] of IO address range. For the purpose of address decoding the bridge assumes that the lower 12 address bits address[11:0] of the I/O base address (not implemented in the I/O Base.." newline rbitfld.long 0x1C 1.--3. "IO_RESERV,Reserved." "0,1,2,3,4,5,6,7" newline bitfld.long 0x1C 0. "IO_DECODE,I/O Addressing Encode (IO Base Address) This bit encodes the IO addressing capability of the bridge. IO_DECODE indicates the following: - 0h: The bridge supports only 16-bit I/O addressing (for ISA compatibility). For the purpose of address.." "0,1" line.long 0x20 "MEM_LIMIT_MEM_BASE_REG,Memory Limit and Base Register. The Memory Limit and Memory Base registers define a memory mapped address range which is used by the bridge to determine when to forward memory transactions from one interface to the other. If there.." hexmask.long.word 0x20 20.--31. 1. "MEM_LIMIT,Memory Limit Address. These bits correspond to the upper 12 address bits Address[31:20] of 32-bit addresses. For the purpose of address decoding the bridge assumes that the lower 20 address bits Address[19:0] of the memory limit address.." newline hexmask.long.byte 0x20 16.--19. 1. "MEM_LIMIT_RESERV,Reserved." newline hexmask.long.word 0x20 4.--15. 1. "MEM_BASE,Memory Base Address. These bits correspond to the upper 12 address bits Address[31:20] of 32-bit addresses. For the purpose of address decoding the bridge assumes that the lower 20 address bits Address[19:0] of the memory base address (not.." newline hexmask.long.byte 0x20 0.--3. 1. "MEM_BASE_RESERV,Reserved." line.long 0x24 "PREF_MEM_LIMIT_PREF_MEM_BASE_REG,Prefetchable Memory Limit and Base Register. The Prefetchable Memory Limit and Prefetchable Memory Base registers must indicate that 64-bit addresses are supported. as defined in PCI-to-PCI Bridge Architecture.." hexmask.long.word 0x24 20.--31. 1. "PREF_MEM_LIMIT,Prefetchable Memory Limit Address. If the Prefetchable Memory Limit register indicates support for 32-bit addressing then the Prefetchable Limit Upper 32 Bits register is implemented as a read-only register that returns zero when read. If.." newline rbitfld.long 0x24 17.--19. "PREF_RESERV1,Reserved." "0,1,2,3,4,5,6,7" newline rbitfld.long 0x24 16. "PREF_MEM_LIMIT_DECODE,Prefetchable Memory Limit Decode. This bit encodes whether or not the bridge supports 64-bit addresses. Note: This bit is a copy of the PREF_MEM_DECODE bit and always reflects the current value of that bit. The value of.." "0,1" newline hexmask.long.word 0x24 4.--15. 1. "PREF_MEM_BASE,Prefetchable Memory Base Address. If the Prefetchable Memory Base register indicates support for 32-bit addressing then the Prefetchable Base Upper 32 Bits register is implemented as a read-only register that returns zero when read. If the.." newline rbitfld.long 0x24 1.--3. "PREF_RESERV,Reserved." "0,1,2,3,4,5,6,7" newline bitfld.long 0x24 0. "PREF_MEM_DECODE,Prefetchable Memory Base Decode. This bit encodes whether or not the bridge supports 64-bit addresses. Note: By default the bit is set to 1'b1 indicating that 64-bit addresses are supported. If the bridge only supports 32-bit prefetchable.." "0,1" line.long 0x28 "PREF_BASE_UPPER_REG,Prefetchable Base Upper 32 Bits Register. The Prefetchable Base Upper 32 Bits register is an optional extension to the Prefetchable Memory Base register." hexmask.long 0x28 0.--31. 1. "PREF_MEM_BASE_UPPER,Prefetchable Base Upper 32 Bit. If the Prefetchable Memory Base register indicates support for 32-bit addressing then this register is implemented as read-only register that returns zero when read. If the Prefetchable Memory Base.." line.long 0x2C "PREF_LIMIT_UPPER_REG,Prefetchable Limit Upper 32 Bits Register. The Prefetchable Limit Upper 32 Bits register is an optional extension to the Prefetchable Memory Limit register." hexmask.long 0x2C 0.--31. 1. "PREF_MEM_LIMIT_UPPER,Prefetchable Limit Upper 32 Bit. If the Prefetchable Memory Limit register indicate support for 64-bit addressing then this register is implemented as read/write register which must be initialized by configuration software. This.." rgroup.long 0x30++0x3 line.long 0x0 "IO_LIMIT_UPPER_IO_BASE_UPPER_REG,I/O Limit and Base Upper 16 Bits Register. The I/O Limit Upper 16 Bits and I/O Base Upper 16 Bits registers are optional extensions to the I/O Limit and I/O Base registers." hexmask.long.word 0x0 16.--31. 1. "IO_LIMIT_UPPER,I/O Limit Upper 16 Bits. If the I/O Limit register indicates support for 16-bit I/O address decoding then this register is implemented as a read-only register which return zero when read. If the I/O Limit register indicates support for.." newline hexmask.long.word 0x0 0.--15. 1. "IO_BASE_UPPER,I/O Base Upper 16 Bits. If the I/O Base register indicates support for 16-bit I/O address decoding then this register is implemented as a read-only register which return zero when read. If the I/O base register indicates support for 32-bit.." group.long 0x34++0xB line.long 0x0 "TYPE1_CAP_PTR_REG,Capabilities Pointer Register." hexmask.long.tbyte 0x0 8.--31. 1. "RSVDP_8,Reserved for future use." newline hexmask.long.byte 0x0 0.--7. 1. "CAP_POINTER,Capabilities Pointer. This register is used to point to a linked list of capabilities implemented by this Function. Since all PCI Express Functions are required to implement the PCI Express Capability structure this register must point to a.." line.long 0x4 "TYPE1_EXP_ROM_BASE_REG,Expansion ROM Base Address Register. This register is defined to handle the base address and size information for this expansion ROM. The mask for this ROM BAR exists (if implemented) as a shadow register at this address. The.." hexmask.long.tbyte 0x4 11.--31. 1. "EXP_ROM_BASE_ADDRESS,Expansion ROM Base Address. Upper 21 bits of the Expansion ROM base address. The number of bits (out of these 21) that a Function actually implements depends on how much address space the Function requires. The mask for this ROM BAR.." newline hexmask.long.word 0x4 1.--10. 1. "RSVDP_1,Reserved for future use." newline bitfld.long 0x4 0. "ROM_BAR_ENABLE,Expansion ROM Enable. This bit controls whether or not the Function accepts accesses to its expansion ROM. When this bit is 0b the Function's expansion ROM address space is disabled. When the bit is 1b address decoding is enabled using.." "0,1" line.long 0x8 "BRIDGE_CTRL_INT_PIN_INT_LINE_REG,Bridge Control. Interrupt Pin. and Interrupt Line Register." hexmask.long.word 0x8 23.--31. 1. "BRIDGE_CTRL_RESERV,Reserved." newline bitfld.long 0x8 22. "SBR,Secondary Bus Reset. Setting this bit triggers a hot reset on the corresponding PCI Express Port. Software must ensure a minimum reset duration (Trst) as defined in the PCI Local Bus Specification. Software and systems must honor.." "0,1" newline rbitfld.long 0x8 21. "MSTR_ABORT_MODE,Master Abort Mode. This bit was originally described in the PCI-to-PCI Bridge Architecture Specification. Its functionality does not apply to PCI Express. The controller hardwires this bit to 0b. Note: The access attributes of this field.." "0,1" newline rbitfld.long 0x8 20. "VGA_16B_DEC,VGA 16 bit decode. This bit only has meaning if VGA Enable bit is set. This bit enables system configuration software to select between 10-bit and 16-bit I/O address decoding for all VGA I/O register accesses that are forwarded from primary.." "0,1" newline rbitfld.long 0x8 19. "VGA_EN,VGA Enable. Modifies the response by the bridge to VGA compatible addresses. If the VGA Enable bit is set the bridge will positively decode and forward the following accesses on the primary interface to the secondary interface (and conversely.." "0,1" newline bitfld.long 0x8 18. "ISA_EN,ISA Enable. Modifies the response by the bridge to ISA I/O addresses. This applies only to I/O addresses that are enabled by the I/O Base and I/O Limit registers and are in the first 64 KB of I/O address space (0000 0000h to 0000 FFFFh). If this.." "?,KB block" newline bitfld.long 0x8 17. "SERR_EN,SERR# Enable. This bit controls forwarding of ERR_COR ERR_NONFATAL and ERR_FATAL from secondary to primary." "0,1" newline bitfld.long 0x8 16. "PERE,Parity Error Response Enable. This bit controls the logging of poisoned TLPs in the Master Data Parity Error bit in the Secondary Status register." "0,1" newline hexmask.long.byte 0x8 8.--15. 1. "INT_PIN,Interrupt PIN. The Interrupt Pin register register that identifies the legacy interrupt Message(s) the Function uses. Valid values are: - 01h 02h 03h and 04h: map to legacy interrupt Messages for INTA INTB INTC and INTD respectively. - 00h:.." newline hexmask.long.byte 0x8 0.--7. 1. "INT_LINE,Interrupt Line. The Interrupt Line register communicates interrupt line routing information. The register must be implemented by any Function that uses an interrupt pin. Values in this register are programmed by system software and are system.." tree.end tree "PF0_SPCIE_CAP (Secondary PCI Express Capability Structure)" group.long (0x0+0x1A0)++0xF line.long 0x0 "SPCIE_CAP_HEADER_REG,SPCIE Capability Header. For a description of this standard PCIe register. see the PCI Express Specification." hexmask.long.word 0x0 20.--31. 1. "NEXT_OFFSET,Next Capability Offset. For a description of this standard PCIe register field see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky).." hexmask.long.byte 0x0 16.--19. 1. "CAP_VERSION,Capability Version. For a description of this standard PCIe register field see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else.." hexmask.long.word 0x0 0.--15. 1. "EXTENDED_CAP_ID,Secondary PCI Express Extended Capability ID. For a description of this standard PCIe register field see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN.." line.long 0x4 "LINK_CONTROL3_REG,Link Control 3 Register. For a description of this standard PCIe register. see the PCI Express Specification." hexmask.long 0x4 2.--31. 1. "RSVDP_2,Reserved for future use." bitfld.long 0x4 1. "EQ_REQ_INT_EN,Link Equalization Request Interrupt Enable. For a description of this standard PCIe register field see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" "0,1" bitfld.long 0x4 0. "PERFORM_EQ,Perform Equalization. For a description of this standard PCIe register field see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" "0,1" line.long 0x8 "LANE_ERR_STATUS_REG,Lane Error Status Register. For a description of this standard PCIe register. see the PCI Express Specification." hexmask.long 0x8 2.--31. 1. "RSVDP_LANE_ERR_STATUS,Reserved for future use." bitfld.long 0x8 0.--1. "LANE_ERR_STATUS,Lane Error Status Bits per Lane. For a description of this standard PCIe register field see the PCI Express Specification." "0,1,2,3" line.long 0xC "SPCIE_CAP_OFF_0CH_REG,Lane Equalization Control Register for lanes 1 and 0. For a description of this standard PCIe register. see the PCI Express Specification." rbitfld.long 0xC 31. "RSVDP_31,Reserved for future use." "0,1" bitfld.long 0xC 28.--30. "USP_RX_PRESET_HINT1,Upstream Port 8.0 GT/s Receiver Preset Hint 1. The write value is gated with the PCIE_CAP_CROSS_LINK_SUPPORT field of LINK_CAPABILITIES2_REG. For a description of this standard PCIe register field see the PCI Express Specification." "0,1,2,3,4,5,6,7" hexmask.long.byte 0xC 24.--27. 1. "USP_TX_PRESET1,Upstream Port 8.0 GT/s Transmitter Preset 1. The write value is gated with the PCIE_CAP_CROSS_LINK_SUPPORT field of LINK_CAPABILITIES2_REG. For a description of this standard PCIe register field see the PCI Express Specification. Note:.." rbitfld.long 0xC 23. "RSVDP_23,Reserved for future use." "0,1" newline bitfld.long 0xC 20.--22. "DSP_RX_PRESET_HINT1,Downstream Port 8.0 GT/s Receiver Preset Hint 1. For a description of this standard PCIe register field see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if.." "0,1,2,3,4,5,6,7" hexmask.long.byte 0xC 16.--19. 1. "DSP_TX_PRESET1,Downstream Port 8.0 GT/s Transmitter Preset 1. For a description of this standard PCIe register field see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN.." rbitfld.long 0xC 15. "RSVDP_15,Reserved for future use." "0,1" bitfld.long 0xC 12.--14. "USP_RX_PRESET_HINT0,Upstream Port 8.0 GT/s Receiver Preset Hint 0. The write value is gated with the PCIE_CAP_CROSS_LINK_SUPPORT field of LINK_CAPABILITIES2_REG. For a description of this standard PCIe register field see the PCI Express Specification." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0xC 8.--11. 1. "USP_TX_PRESET0,Upstream Port 8.0 GT/s Transmitter Preset 0. The write value is gated with the PCIE_CAP_CROSS_LINK_SUPPORT field of LINK_CAPABILITIES2_REG. For a description of this standard PCIe register field see the PCI Express Specification. Note:.." rbitfld.long 0xC 7. "RSVDP_7,Reserved for future use." "0,1" bitfld.long 0xC 4.--6. "DSP_RX_PRESET_HINT0,Downstream Port 8.0 GT/s Receiver Preset Hint 0. For a description of this standard PCIe register field see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if.." "0,1,2,3,4,5,6,7" hexmask.long.byte 0xC 0.--3. 1. "DSP_TX_PRESET0,Downstream Port 8.0 GT/s Transmitter Preset 0. For a description of this standard PCIe register field see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN.." tree.end tree "PF0_L1SUB_CAP (L1 Substates Capability Structure)" group.long (0x0+0x2E8)++0xF line.long 0x0 "L1SUB_CAP_HEADER_REG,L1 Substates Extended Capability Header. This register provides capbility ID. capability version and next offset value for L1 Substates." hexmask.long.word 0x0 20.--31. 1. "NEXT_OFFSET,Next Capability Offset. This field contains the offset to the next PCI Express Capability structure or 000h if no other items exist in the linked list of Capabilities. For Extended Capabilities implemented in Configuration Space this offset.." hexmask.long.byte 0x0 16.--19. 1. "CAP_VERSION,Capability Version. This field is a PCI-SIG defined version number that indicates the version of the Capability structure present. This field is depends on version of the specification. Note: The access attributes of this field are as.." hexmask.long.word 0x0 0.--15. 1. "EXTENDED_CAP_ID,L1SUB Extended Capability ID. This field is a PCI-SIG defined ID number that indicates the nature and format of the Extended Capability. Extended Capability ID for L1 PM Substates is 001Eh. Note: The access attributes of this field are as.." line.long 0x4 "L1SUB_CAPABILITY_REG,L1 Substates Capability Register. This register provides extended capability of L1 Substates." hexmask.long.byte 0x4 24.--31. 1. "RSVDP_24,Reserved for future use." hexmask.long.byte 0x4 19.--23. 1. "PWR_ON_VALUE_SUPPORT,Port T Power On Value. Along with the Port T_POWER_ON Scale field in the L1 PM Substates Capabilities register sets the time (in us) that this Port requires the port on the opposite side of Link to wait in L1.2.Exit after sampling.." rbitfld.long 0x4 18. "RSVDP_18,Reserved for future use." "0,1" bitfld.long 0x4 16.--17. "PWR_ON_SCALE_SUPPORT,Port T Power On Scale. Specifies the scale used for the Port T_POWER_ON Value field in the L1 PM Substates Capabilities register. Range of values are given below. Required for all Ports for which either the PCI-PM L1.2 Supported bit.." "?,?,?,Reserved" newline hexmask.long.byte 0x4 8.--15. 1. "COMM_MODE_SUPPORT,Port Common Mode Restore Time. Time (in us) required for this Port to re-establish common mode. Required for all Ports for which either the PCI-PM L1.2 Supported bit is Set ASPM L1.2 Supported bit is Set or both are Set otherwise.." rbitfld.long 0x4 5.--7. "RSVDP_5,Reserved for future use." "0,1,2,3,4,5,6,7" bitfld.long 0x4 4. "L1_PMSUB_SUPPORT,L1 PM Substates ECN Supported. When Set this bit indicates that this Port supports L1 PM Substates. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W (sticky)" "0,1" bitfld.long 0x4 3. "L1_1_ASPM_SUPPORT,ASPM L11 Supported. When Set this bit indicates that ASPM L1.1 is supported. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W (sticky)" "0,1" newline bitfld.long 0x4 2. "L1_2_ASPM_SUPPORT,ASPM L12 Supported. When Set this bit indicates that ASPM L1.2 is supported. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W (sticky)" "0,1" bitfld.long 0x4 1. "L1_1_PCIPM_SUPPORT,PCI-PM L11 Supported. When Set this bit indicates that PCI-PM L1.1 is supported and must be Set by all Ports implementing L1 PM Substates. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W (sticky)" "0,1" bitfld.long 0x4 0. "L1_2_PCIPM_SUPPORT,PCI-PM L12 Supported. When Set this bit indicates that PCI-PM L1.2 is supported. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W (sticky)" "0,1" line.long 0x8 "L1SUB_CONTROL1_REG,L1 Substates Control 1 Register. This register provides Controls to extended capability." bitfld.long 0x8 29.--31. "L1_2_TH_SCA,LTR L12 Threshold Scale. This field provides a scale for the value contained within the LTR_L1.2_THRESHOLD_Value.The default value for this field is 000b.Hardware operation is undefined if software writes a Not-Permitted value to this field." "0,1,2,3,4,5,6,7" rbitfld.long 0x8 26.--28. "RSVDP_26,Reserved for future use." "0,1,2,3,4,5,6,7" hexmask.long.word 0x8 16.--25. 1. "L1_2_TH_VAL,LTR L12 Threshold Value. Along with the LTR_L1.2_THRESHOLD_Scale this field indicates the LTR threshold used to determine if entry into L1 results in L1.1 (if enabled) or L1.2 (if enabled). The default value for this field is 00 0000 0000b." hexmask.long.byte 0x8 8.--15. 1. "T_COMMON_MODE,Common Mode Restore Time. Sets value of TCOMMONMODE (in us) which must be used by the Downstream Ports for timing the re-establishment of common mode.This field is of type RsvdP for Upstream Ports. Default value is implementation.." newline hexmask.long.byte 0x8 4.--7. 1. "RSVDP_4,Reserved for future use." bitfld.long 0x8 3. "L1_1_ASPM_EN,ASPM L11 Enable. When Set this bit enables ASPM L1.1.For Ports for which the ASPM L1.1 Supported bit is Clear this bit is permitted to be hardwired to 0.Default value is 0b." "0,1" bitfld.long 0x8 2. "L1_2_ASPM_EN,ASPM L12 Enable. When Set this bit enables ASPM L1.2.For Ports for which the ASPM L1.2 Supported bit is Clear this bit is permitted to be hardwired to 0.Default value is 0b." "0,1" bitfld.long 0x8 1. "L1_1_PCIPM_EN,PCI-PM L11 Enable. When Set this bit enables PCI-PM L1.1. Default value is 0b." "0,1" newline bitfld.long 0x8 0. "L1_2_PCIPM_EN,PCI-PM L12 Enable. When Set this bit enables PCI-PM L1.2.For Ports for which the PCI-PM L1.2 Supported bit is Clear this bit is permitted to be hardwired to 0.Default value is 0b." "0,1" line.long 0xC "L1SUB_CONTROL2_REG,L1 Substates Control 2 Register. This register provides Controls to extended capability." hexmask.long.tbyte 0xC 8.--31. 1. "RSVDP_8,Reserved for future use." hexmask.long.byte 0xC 3.--7. 1. "T_POWER_ON_VALUE,T Power On Value. Along with the T_POWER_ON Scale sets the minimum amount of time (in us) that the Port must wait in L1.2.Exit after sampling CLKREQ# asserted before actively driving the interface.Default value is 00101b. T_POWER_ON is.." rbitfld.long 0xC 2. "RSVDP_2,Reserved for future use." "0,1" bitfld.long 0xC 0.--1. "T_POWER_ON_SCALE,T Power On Scale. Specifies the scale used for T_POWER_ON Value. Range of values are given below. Required for all Ports that support L1.2 otherwise this field is of type RsvdP. This field must only be modified when the ASPM L1.2 Enable.." "?,?,?,Reserved" tree.end tree "PF0_RAS_DES_CAP (RAS D.E.S. Capability Structure (VSEC))" group.long (0x0+0x30C)++0x3 line.long 0x0 "RAS_DES_CAP_HEADER_REG,Vendor-Specific Extended Capability Header. For a description of this standard PCIe register. see the PCI Express Specification." hexmask.long.word 0x0 20.--31. 1. "NEXT_OFFSET,Next Capability Offset. For a description of this standard PCIe register field see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky).." newline hexmask.long.byte 0x0 16.--19. 1. "CAP_VERSION,Capability Version. For a description of this standard PCIe register field see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else.." newline hexmask.long.word 0x0 0.--15. 1. "EXTENDED_CAP_ID,PCI Express Extended Capability ID. For a description of this standard PCIe register field see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then.." rgroup.long (0x4+0x30C)++0x3 line.long 0x0 "VENDOR_SPECIFIC_HEADER_REG,Vendor-Specific Header. For a description of this standard PCIe register. see the PCI Express Specification." hexmask.long.word 0x0 20.--31. 1. "VSEC_LENGTH,VSEC Length. For a description of this standard PCIe register field see the PCI Express Specification." newline hexmask.long.byte 0x0 16.--19. 1. "VSEC_REV,VSEC Rev. For a description of this standard PCIe register field see the PCI Express Specification." newline hexmask.long.word 0x0 0.--15. 1. "VSEC_ID,VSEC ID. For a description of this standard PCIe register field see the PCI Express Specification." group.long (0x8+0x30C)++0x3 line.long 0x0 "EVENT_COUNTER_CONTROL_REG,Event Counter Control. This is a viewport control register. - Setting the EVENT_COUNTER_EVENT_SELECT and EVENT_COUNTER_LANE_SELECT fields in this register determine the Event Counter data returned by the EVENT_COUNTER_DATA_REG.." hexmask.long.byte 0x0 28.--31. 1. "RSVDP_28,Reserved for future use." newline hexmask.long.word 0x0 16.--27. 1. "EVENT_COUNTER_EVENT_SELECT,Event Counter Data Select. This field in conjunction with the EVENT_COUNTER_LANE_SELECT field indexes the Event Counter data returned by the EVENT_COUNTER_DATA_REG register. - 27-24: Group number(4-bit: 0..0x7) - 23-16: Event.." newline hexmask.long.byte 0x0 12.--15. 1. "RSVDP_12,Reserved for future use." newline hexmask.long.byte 0x0 8.--11. 1. "EVENT_COUNTER_LANE_SELECT,Event Counter Lane Select. This field in conjunction with EVENT_COUNTER_EVENT_SELECT indexes the Event Counter data returned by the EVENT_COUNTER_DATA_REG register. - 0x0: Lane0 - 0x1: Lane1 - 0x2: Lane2 - .. - 0xF: Lane15 Note:.." newline rbitfld.long 0x0 7. "EVENT_COUNTER_STATUS,Event Counter Status. This register returns the current value of the Event Counter selected by the following fields: - EVENT_COUNTER_EVENT_SELECT - EVENT_COUNTER_LANE_SELECT Note: This register field is sticky." "0,1" newline rbitfld.long 0x0 5.--6. "RSVDP_5,Reserved for future use." "0,1,2,3" newline bitfld.long 0x0 2.--4. "EVENT_COUNTER_ENABLE,Event Counter Enable. Enables/disables the Event Counter selected by the EVENT_COUNTER_EVENT_SELECT and EVENT_COUNTER_LANE_SELECT fields in this register. By default all event counters are disabled. You can enable/disable a specific.." "no change,per event off,?,?,?,?,?,?" newline bitfld.long 0x0 0.--1. "EVENT_COUNTER_CLEAR,Event Counter Clear. Clears the Event Counter selected by the EVENT_COUNTER_EVENT_SELECT and EVENT_COUNTER_LANE_SELECT fields in this register. You can clear the value of a specific Event Counter by writing the 'per clear' code and.." "no change,per clear,?,?" rgroup.long (0xC+0x30C)++0x3 line.long 0x0 "EVENT_COUNTER_DATA_REG,Event Counter Data. This viewport register returns the data selected by the following fields: - EVENT_COUNTER_EVENT_SELECT in EVENT_COUNTER_CONTROL_REG - EVENT_COUNTER_LANE_SELECT in EVENT_COUNTER_CONTROL_REG For more details. see.." hexmask.long 0x0 0.--31. 1. "EVENT_COUNTER_DATA,Event Counter Data. This register returns the data selected by the following fields: - EVENT_COUNTER_EVENT_SELECT in EVENT_COUNTER_CONTROL_REG - EVENT_COUNTER_LANE_SELECT in EVENT_COUNTER_CONTROL_REG Note: This register field is sticky." group.long (0x10+0x30C)++0x3 line.long 0x0 "TIME_BASED_ANALYSIS_CONTROL_REG,Time-based Analysis Control. Used for controlling the measurement of RX/TX data throughput and time spent in each low-power LTSSM state. For more details. see the RAS DES section in the Core Operations chapter of the.." hexmask.long.byte 0x0 24.--31. 1. "TIME_BASED_REPORT_SELECT,Time-based Report Select. Selects what type of data is measured for the selected duration (TIME_BASED_DURATION_SELECT) and returned in TIME_BASED_ANALYSIS_DATA. Each type of data is measured using one of three types of units: -.." newline hexmask.long.byte 0x0 16.--23. 1. "RSVDP_16,Reserved for future use." newline hexmask.long.byte 0x0 8.--15. 1. "TIME_BASED_DURATION_SELECT,Time-based Duration Select. Selects the duration of time-based analysis. When 'manual control' is selected and TIMER_START is set to '1' this analysis never stops until TIMER_STOP is set to '0'. - 0x0: Manual control - 0x1:.." newline hexmask.long.byte 0x0 1.--7. 1. "RSVDP_1,Reserved for future use." newline bitfld.long 0x0 0. "TIMER_START,Timer Start. - 1: Start/Restart - 0: Stop This bit will be cleared automatically when the measurement is finished. Note: The app_ras_des_tba_ctrl input also sets the contents of this field and controls the measurement start/stop. Note: This.." "Stop,Start/Restart" rgroup.long (0x14+0x30C)++0x7 line.long 0x0 "TIME_BASED_ANALYSIS_DATA_REG,Time-based Analysis Data. Contains the measurement results of RX/TX data throughput and time spent in each low-power LTSSM state. This viewport register returns the data selected by the TIME_BASED_REPORT_SELECT field in.." hexmask.long 0x0 0.--31. 1. "TIME_BASED_ANALYSIS_DATA,Time Based Analysis Data. This register returns the data selected by the TIME_BASED_REPORT_SELECT field in TIME_BASED_ANALYSIS_CONTROL_REG. The results are cleared when next measurement starts. Note: This register field is sticky." line.long 0x4 "TIME_BASED_ANALYSIS_DATA_63_32_REG,Upper 32 bits of Time-based Analysis Data. This viewport register returns the data selected by the TIME_BASED_REPORT_SELECT field in TIME_BASED_ANALYSIS_CONTROL_REG. For more details. see the RAS DES section in the Core.." hexmask.long 0x4 0.--31. 1. "TIME_BASED_ANALYSIS_DATA_63_32,Upper 32 bits of Time Based Analysis Data. Note: This register field is sticky." group.long (0x30+0x30C)++0x5F line.long 0x0 "EINJ_ENABLE_REG,Error Injection Enable. Each type of error insertion is enabled by the corresponding bit in this register. The specific injection controls for each type of error are defined in the following registers: - 0: CRC Error: EINJ0_CRC_REG - 1:.." hexmask.long 0x0 7.--31. 1. "RSVDP_7,Reserved for future use." newline bitfld.long 0x0 6. "ERROR_INJECTION6_ENABLE,Error Injection6 Enable (Specific TLP Error). Enables insertion of errors into the packets that you select. You can set this bit to '1' when you have disabled RAS datapath protection (DP) by setting CX_RASDP = CX_RASDP_RAM_PROT.." "0,1" newline bitfld.long 0x0 5. "ERROR_INJECTION5_ENABLE,Error Injection5 Enable (TLP Duplicate/Nullify Error). Enables insertion of duplicate/nullified TLPs. For more details see the EINJ5_SP_TLP_REG register. Note: This register field is sticky." "0,1" newline bitfld.long 0x0 4. "ERROR_INJECTION4_ENABLE,Error Injection4 Enable (FC Credit Update Error). Enables insertion of errors into UpdateFCs. For more details see the EINJ4_FC_REG register. Note: This register field is sticky." "0,1" newline bitfld.long 0x0 3. "ERROR_INJECTION3_ENABLE,Error Injection3 Enable (Symbol DataK Mask Error or Sync Header Error). Enables DataK masking of special symbols or the breaking of the sync header. For more details see the EINJ3_SYMBOL_REG register. Note: This register field is.." "0,1" newline bitfld.long 0x0 2. "ERROR_INJECTION2_ENABLE,Error Injection2 Enable (DLLP Error). Enables insertion of DLLP errors. For more details see the EINJ2_DLLP_REG register. Note: This register field is sticky." "0,1" newline bitfld.long 0x0 1. "ERROR_INJECTION1_ENABLE,Error Injection1 Enable (Sequence Number Error). Enables insertion of errors into sequence numbers. For more details see the EINJ1_SEQNUM_REG register. Note: This register field is sticky." "0,1" newline bitfld.long 0x0 0. "ERROR_INJECTION0_ENABLE,Error Injection0 Enable (CRC Error). Enables insertion of errors into various CRC. For more details see the EINJ0_CRC_REG register. Note: This register field is sticky." "0,1" line.long 0x4 "EINJ0_CRC_REG,Error Injection Control 0 (CRC Error). Controls the insertion of errors into the CRC. and parity of ordered sets for the selected type of the packets as follows: - LCRC. Bad TLP will be detected at the receiver side; receiver responds with.." hexmask.long.tbyte 0x4 12.--31. 1. "RSVDP_12,Reserved for future use." newline hexmask.long.byte 0x4 8.--11. 1. "EINJ0_CRC_TYPE,Error injection type. Selects the type of CRC error to be inserted. Tx Path - 0000b: New TLP's LCRC error injection - 0001b: 16bCRC error injection of ACK/NAK DLLP - 0010b: 16bCRC error injection of Update-FC DLLP - 0011b: New TLP's ECRC.." newline hexmask.long.byte 0x4 0.--7. 1. "EINJ0_COUNT,Error injection count. Indicates the number of errors. This register is decremented when the errors have been inserted. - If the counter value is 0x01 and error is inserted ERROR_INJECTION0_ENABLE in EINJ_ENABLE_REG returns 0b. - If the.." line.long 0x8 "EINJ1_SEQNUM_REG,Error Injection Control 1 (Sequence Number Error). Controls the sequence number of the specific TLPs and ACK/NAK DLLPs. Data Link Protocol Error will be detected at the Rx side of ACK/NAL DLLPs when one of these conditions is true: -.." rbitfld.long 0x8 29.--31. "RSVDP_29,Reserved for future use." "0,1,2,3,4,5,6,7" newline hexmask.long.word 0x8 16.--28. 1. "EINJ1_BAD_SEQNUM,Bad sequence number. Indicates the value to add/subtract from the naturally-assigned sequence numbers. This value is represented by two's complement. - 0x0FFF: +4095 - .. - 0x0002: +2 - 0x0001: +1 - 0x0000: 0 - 0x1FFF: -1 - 0x1FFE: -2 -.." newline hexmask.long.byte 0x8 9.--15. 1. "RSVDP_9,Reserved for future use." newline bitfld.long 0x8 8. "EINJ1_SEQNUM_TYPE,Sequence number type. Selects the type of sequence number. - 0b: Insertion of New TLP's SEQ# error - 1b: Insertion of ACK/NAK DLLP's SEQ# Error Note: This register field is sticky." "0,1" newline hexmask.long.byte 0x8 0.--7. 1. "EINJ1_COUNT,Error injection count. Indicates the number of errors. This register is decremented as the errors are being inserted. - If the counter value is 0x01 and error is inserted ERROR_INJECTION1_ENABLE in EINJ_ENABLE_REG returns '0'. - If the.." line.long 0xC "EINJ2_DLLP_REG,Error Injection Control 2 (DLLP Error). Controls the transmission of DLLPs and inserts the following errors: - If 'ACK/NAK DLLP's transmission block' is selected. replay timeout error will occur at the transmitter of the TLPs and then Data.." hexmask.long.tbyte 0xC 10.--31. 1. "RSVDP_10,Reserved for future use." newline bitfld.long 0xC 8.--9. "EINJ2_DLLP_TYPE,DLLP Type. Selects the type of DLLP errors to be inserted. - 00b: ACK/NAK DLLP's transmission block - 01b: Update FC DLLP's transmission block - 10b: Always Transmission for NAK DLLP - 11b: Reserved Note: This register field is sticky." "0,1,2,3" newline hexmask.long.byte 0xC 0.--7. 1. "EINJ2_COUNT,Error injection count. Indicates the number of errors. This register is decremented as the errors are being inserted. - If the counter value is 0x01 and the error is inserted ERROR_INJECTION2_ENABLE in EINJ_ENABLE_REG returns '0'. - If the.." line.long 0x10 "EINJ3_SYMBOL_REG,Error Injection Control 3 (Symbol Error). When 8b/10b encoding is used. this register controls error insertion into the special (K code) symbols. - If TS1/TS2/FTS/E-Idle/SKP is selected. it affects whole of the ordered set. It might.." hexmask.long.tbyte 0x10 11.--31. 1. "RSVDP_11,Reserved for future use." newline bitfld.long 0x10 8.--10. "EINJ3_SYMBOL_TYPE,Error Type. 8b/10b encoding - Mask K symbol. It is not supported to insert errors into the first ordered-set after exiting from TxElecIdle when CX_FREQ_STEP_EN has been enabled. - 000b: Reserved - 001b: COM/PAD(TS1 Order set) - 010b:.." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x10 0.--7. 1. "EINJ3_COUNT,Error injection count. Indicates the number of errors. This register is decremented as the errors are being inserted. - If the counter value is 0x01 and error is inserted ERROR_INJECTION3_ENABLE in EINJ_ENABLE_REG returns '0'. - If the.." line.long 0x14 "EINJ4_FC_REG,Error Injection Control 4 (FC Credit Error). Controls error insertion into the credit value in the UpdateFCs. It is possible to insert errors for any of the following types: - Posted TLP Header credit - Non-Posted TLP Header credit -.." rbitfld.long 0x14 29.--31. "RSVDP_29,Reserved for future use." "0,1,2,3,4,5,6,7" newline hexmask.long.word 0x14 16.--28. 1. "EINJ4_BAD_UPDFC_VALUE,Bad update-FC credit value. Indicates the value to add/subtract from the UpdateFC credit. This value is represented by two's complement. - 0x0FFF: +4095 - .. - 0x0002: +2 - 0x0001: +1 - 0x0000: 0 - 0x1FFF: -1 - 0x1FFE: -2 - .. -.." newline rbitfld.long 0x14 15. "RSVDP_15,Reserved for future use." "0,1" newline bitfld.long 0x14 12.--14. "EINJ4_VC_NUMBER,VC Number. Indicates target VC Number. Note: This register field is sticky." "0,1,2,3,4,5,6,7" newline rbitfld.long 0x14 11. "RSVDP_11,Reserved for future use." "0,1" newline bitfld.long 0x14 8.--10. "EINJ4_UPDFC_TYPE,Update-FC type. Selects the credit type. - 000b: Posted TLP Header Credit value control - 001b: Non-Posted TLP Header Credit value control - 010b: Completion TLP Header Credit value control - 011b: Reserved - 100b: Posted TLP Data Credit.." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x14 0.--7. 1. "EINJ4_COUNT,Error injection count. Indicates the number of errors. This register is decremented as the errors are being inserted. - If the counter value is 0x01 and error is inserted ERROR_INJECTION4_ENABLE in EINJ_ENABLE_REG returns '0'. - If the.." line.long 0x18 "EINJ5_SP_TLP_REG,Error Injection Control 5 (Specific TLP Error). Controls the generation of specified TLPs. Correctable errors will occur which will be fixed by the PCIe protocol. - For Duplicate TLP. the controller initiates Data Link Retry by handling.." hexmask.long.tbyte 0x18 9.--31. 1. "RSVDP_9,Reserved for future use." newline bitfld.long 0x18 8. "EINJ5_SPECIFIED_TLP,Specified TLP. Selects the specified TLP to be inserted. - 0: Generates duplicate TLPs by handling ACK DLLP as NAK DLLP. - 1: Generates Nullified TLP (Original TLP will be stored in retry buffer). Note: This register field is sticky." "Generates duplicate TLPs by handling ACK DLLP as..,Generates Nullified TLP" newline hexmask.long.byte 0x18 0.--7. 1. "EINJ5_COUNT,Error injection count. Indicates the number of errors. This register is decremented as the errors are being inserted. - If the counter value is 0x01 and error is inserted ERROR_INJECTION5_ENABLE in EINJ_ENABLE_REG returns '0'. - If the.." line.long 0x1C "EINJ6_COMPARE_POINT_H0_REG,Error Injection Control 6 (Compare Point Header DWORD #0). Program this register for the 1st DWORD of TLP header/prefix. It is necessary to carefully consider the endianness when you program this register. Bits [31:0] =.." hexmask.long 0x1C 0.--31. 1. "EINJ6_COMPARE_POINT_H0,Packet Compare Point: 1st DWORD. Specifies which Tx TLP header DWORD#0 bits to compare with the corresponding bits in the Packet Compare Value registers (EINJ6_COMPARE_VALUE*). When all specified bits (in the Tx TLP header and.." line.long 0x20 "EINJ6_COMPARE_POINT_H1_REG,Error Injection Control 6 (Compare Point Header DWORD #1). Program this register for the 2nd DWORD of TLP header/prefix. It is necessary to carefully consider the endianness when you program this register. Bits [31:0] =.." hexmask.long 0x20 0.--31. 1. "EINJ6_COMPARE_POINT_H1,Packet Compare Point: 2nd DWORD. Specifies which Tx TLP header DWORD#1 bits to compare with the corresponding bits in the Packet Compare Value registers (EINJ6_COMPARE_VALUE*). When all specified bits (in the Tx TLP header and.." line.long 0x24 "EINJ6_COMPARE_POINT_H2_REG,Error Injection Control 6 (Compare Point Header DWORD #2). Program this register for the 3rd DWORD of TLP header/prefix. It is necessary to carefully consider the endianness when you program this register. Bits [31:0] =.." hexmask.long 0x24 0.--31. 1. "EINJ6_COMPARE_POINT_H2,Packet Compare Point: 3rd DWORD. Specifies which Tx TLP header DWORD#2 bits to compare with the corresponding bits in the Packet Compare Value registers (EINJ6_COMPARE_VALUE*). When all specified bits (in the Tx TLP header and.." line.long 0x28 "EINJ6_COMPARE_POINT_H3_REG,Error Injection Control 6 (Compare Point Header DWORD #3). Program this register for the 4th DWORD of TLP header/prefix. It is necessary to carefully consider the endianness when you program this register. Bits [31:0] =.." hexmask.long 0x28 0.--31. 1. "EINJ6_COMPARE_POINT_H3,Packet Compare Point: 4th DWORD. Specifies which Tx TLP header DWORD#3 bits to compare with the corresponding bits in the Packet Compare Value registers (EINJ6_COMPARE_VALUE*). When all specified bits (in the Tx TLP header and.." line.long 0x2C "EINJ6_COMPARE_VALUE_H0_REG,Error Injection Control 6 (Compare Value Header DWORD #0). Program this register for the 1st DWORD of TLP header/prefix. It is necessary to carefully consider the endianness when you program this register. Bits [31:0] =.." hexmask.long 0x2C 0.--31. 1. "EINJ6_COMPARE_VALUE_H0,Packet Compare Value: 1st DWORD. Specifies the value to compare against Tx the TLP header DWORD#0 bits specified in the Packet Compare Point registers (EINJ6_COMPARE_POINT*). Note: This register field is sticky." line.long 0x30 "EINJ6_COMPARE_VALUE_H1_REG,Error Injection Control 6 (Compare Value Header DWORD #1). Program this register for the 2nd DWORD of TLP header/prefix. It is necessary to carefully consider the endianness when you program this register. Bits [31:0] =.." hexmask.long 0x30 0.--31. 1. "EINJ6_COMPARE_VALUE_H1,Packet Compare Value: 2nd DWORD. Specifies the value to compare against Tx the TLP header DWORD#1 bits specified in the Packet Compare Point registers (EINJ6_COMPARE_POINT*). Note: This register field is sticky." line.long 0x34 "EINJ6_COMPARE_VALUE_H2_REG,Error Injection Control 6 (Compare Value Header DWORD #2). Program this register for the 3rd DWORD of TLP header/prefix. It is necessary to carefully consider the endianness when you program this register. Bits [31:0] =.." hexmask.long 0x34 0.--31. 1. "EINJ6_COMPARE_VALUE_H2,Packet Compare Value: 3rd DWORD. Specifies the value to compare against Tx the TLP header DWORD#2 bits specified in the Packet Compare Point registers (EINJ6_COMPARE_POINT*). Note: This register field is sticky." line.long 0x38 "EINJ6_COMPARE_VALUE_H3_REG,Error Injection Control 6 (Compare Value Header DWORD #3). Program this register for the 4th DWORD of TLP header/prefix. It is necessary to carefully consider the endianness when you program this register. Bits [31:0] =.." hexmask.long 0x38 0.--31. 1. "EINJ6_COMPARE_VALUE_H3,Packet Compare Value: 4th DWORD. Specifies the value to compare against Tx the TLP header DWORD#3 bits specified in the Packet Compare Point registers (EINJ6_COMPARE_POINT*). Note: This register field is sticky." line.long 0x3C "EINJ6_CHANGE_POINT_H0_REG,Error Injection Control 6 (Change Point Header DWORD #0). Program this register for the 1st DWORD of TLP header/prefix. It is necessary to carefully consider the endianness when you program this register. Bits [31:0] =.." hexmask.long 0x3C 0.--31. 1. "EINJ6_CHANGE_POINT_H0,Packet Change Point: 1st DWORD. Specifies which Tx TLP header DWORD#0 bits to replace with the corresponding bits in the Packet Change Value registers (EINJ6_CHANGE_VALUE*). Note: This register field is sticky." line.long 0x40 "EINJ6_CHANGE_POINT_H1_REG,Error Injection Control 6 (Change Point Header DWORD #1). Program this register for the 2nd DWORD of TLP header/prefix. It is necessary to carefully consider the endianness when you program this register. Bits [31:0] =.." hexmask.long 0x40 0.--31. 1. "EINJ6_CHANGE_POINT_H1,Packet Change Point: 2nd DWORD. Specifies which Tx TLP header DWORD#1 bits to replace with the corresponding bits in the Packet Change Value registers (EINJ6_CHANGE_VALUE*). Note: This register field is sticky." line.long 0x44 "EINJ6_CHANGE_POINT_H2_REG,Error Injection Control 6 (Change Point Header DWORD #2). Program this register for the 3rd DWORD of TLP header/prefix. It is necessary to carefully consider the endianness when you program this register. Bits [31:0] =.." hexmask.long 0x44 0.--31. 1. "EINJ6_CHANGE_POINT_H2,Packet Change Point: 3rd DWORD. Specifies which Tx TLP header DWORD#2 bits to replace with the corresponding bits in the Packet Change Value registers (EINJ6_CHANGE_VALUE*). Note: This register field is sticky." line.long 0x48 "EINJ6_CHANGE_POINT_H3_REG,Error Injection Control 6 (Change Point Header DWORD #3). Program this register for the 4th DWORD of TLP header/prefix. It is necessary to carefully consider the endianness when you program this register. Bits [31:0] =.." hexmask.long 0x48 0.--31. 1. "EINJ6_CHANGE_POINT_H3,Packet Change Point: 4th DWORD. Specifies which Tx TLP header DWORD#3 bits to replace with the corresponding bits in the Packet Change Value registers (EINJ6_CHANGE_VALUE*). Note: This register field is sticky." line.long 0x4C "EINJ6_CHANGE_VALUE_H0_REG,Error Injection Control 6 (Change Value Header DWORD #0). Program this register for the 1st DWORD of TLP header/prefix. It is necessary to carefully consider the endianness when you program this register. Bits [31:0] =.." hexmask.long 0x4C 0.--31. 1. "EINJ6_CHANGE_VALUE_H0,Packet Change Value: 1st DWORD. Specifies replacement values for the Tx TLP header DWORD#0 bits defined in the Packet Change Point registers (EINJ6_CHANGE_POINT*). Only applies when the EINJ6_INVERTED_CONTROL field in EINJ6_TLP_REG.." line.long 0x50 "EINJ6_CHANGE_VALUE_H1_REG,Error Injection Control 6 (Change Value Header DWORD #1). Program this register for the 2nd DWORD of TLP header/prefix. It is necessary to carefully consider the endianness when you program this register. Bits [31:0] =.." hexmask.long 0x50 0.--31. 1. "EINJ6_CHANGE_VALUE_H1,Packet Change Value: 2nd DWORD. Specifies replacement values for the Tx TLP header DWORD#1 bits defined in the Packet Change Point registers (EINJ6_CHANGE_POINT*). Only applies when the EINJ6_INVERTED_CONTROL field in EINJ6_TLP_REG.." line.long 0x54 "EINJ6_CHANGE_VALUE_H2_REG,Error Injection Control 6 (Change Value Header DWORD #2). Program this register for the 3rd DWORD of TLP header/prefix. It is necessary to carefully consider the endianness when you program this register. Bits [31:0] =.." hexmask.long 0x54 0.--31. 1. "EINJ6_CHANGE_VALUE_H2,Packet Change Value: 3rd DWORD. Specifies replacement values for the Tx TLP header DWORD#2 bits defined in the Packet Change Point registers (EINJ6_CHANGE_POINT*). Only applies when the EINJ6_INVERTED_CONTROL field in EINJ6_TLP_REG.." line.long 0x58 "EINJ6_CHANGE_VALUE_H3_REG,Error Injection Control 6 (Change Value Header DWORD #3). Program this register for the 4th DWORD of TLP header/prefix. It is necessary to carefully consider the endianness when you program this register. Bits [31:0] =.." hexmask.long 0x58 0.--31. 1. "EINJ6_CHANGE_VALUE_H3,Packet Change Value: 4th DWORD. Specifies replacement values for the Tx TLP header DWORD#3 bits defined in the Packet Change Point registers (EINJ6_CHANGE_POINT*). Only applies when the EINJ6_INVERTED_CONTROL field in EINJ6_TLP_REG.." line.long 0x5C "EINJ6_TLP_REG,Error Injection Control 6 (Packet Error). The Packet Compare Point registers (EINJ6_COMPARE_POINT*) specify which Tx TLP header bits to compare with the corresponding bits in the Packet Compare Value registers (EINJ6_COMPARE_VALUE*). When.." hexmask.long.tbyte 0x5C 12.--31. 1. "RSVDP_12,Reserved for future use." newline bitfld.long 0x5C 9.--11. "EINJ6_PACKET_TYPE,Packet type. Selects the TLP packets to inject errors into. - 0: TLP Header - 1: TLP Prefix 1st 4-DWORDs - 2: TLP Prefix 2nd -DWORDs - Else: Reserved Note: This register field is sticky." "TLP Header,TLP Prefix 1st 4-DWORDs,TLP Prefix 2nd -DWORDs,?,?,?,?,?" newline bitfld.long 0x5C 8. "EINJ6_INVERTED_CONTROL,Inverted Error Injection Control. - 0: EINJ6_CHANGE_VALUE_H[0/1/2/3] is used to replace bits specified by EINJ6_CHANGE_POINT_H[0/1/2/3]. - 1: EINJ6_CHANGE_VALUE_H[0/1/2/3] is ignored and inverts bits specified by.." "EINJ6_CHANGE_VALUE_H[0/1/2/3] is used to replace..,EINJ6_CHANGE_VALUE_H[0/1/2/3] is ignored and.." newline hexmask.long.byte 0x5C 0.--7. 1. "EINJ6_COUNT,Error Injection Count. Indicates the number of errors to insert. This counter is decremented while errors are been inserted. - If the counter value is 0x01 and error is inserted ERROR_INJECTION6_ENABLE in EINJ_ENABLE_REG returns '0'. - If.." group.long (0xA0+0x30C)++0x7 line.long 0x0 "SD_CONTROL1_REG,Silicon Debug Control 1. For more details. see the RAS DES section in the Core Operations chapter of the Databook." hexmask.long.byte 0x0 24.--31. 1. "RSVDP_24,Reserved for future use." newline bitfld.long 0x0 22.--23. "LOW_POWER_INTERVAL,Low Power Entry Interval Time. Interval Time that the controller starts monitoring RXELECIDLE signal after L0s/L1/L2 entry. You should set the value according to the latency from receiving EIOS to RXELECIDLE assertion at the PHY. -.." "0,1,2,3" newline bitfld.long 0x0 20.--21. "TX_EIOS_NUM,Number of Tx EIOS. This register sets the number of transmit EIOS for L0s/L1 entry and Disable/Loopback/Hot-reset exit. The controller selects the greater value between this register and the value defined by the PCI-SIG specification. 2.5GT/s.." "0,1,2,3" newline rbitfld.long 0x0 17.--19. "RSVDP_17,Reserved for future use." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 16. "FORCE_DETECT_LANE_EN,Force Detect Lane Enable. When this bit is set the controller ignores receiver detection from PHY during LTSSM Detect state and uses FORCE_DETECT_LANE. Note: This register field is sticky." "0,1" newline hexmask.long.word 0x0 0.--15. 1. "FORCE_DETECT_LANE,Force Detect Lane. When the FORCE_DETECT_LANE_EN field is set the controller ignores receiver detection from PHY during LTSSM Detect state and uses this value instead. - 0: Lane0 - 1: Lane1 - 2: Lane2 - .. - 15: Lane15 Note: This.." line.long 0x4 "SD_CONTROL2_REG,Silicon Debug Control 2. For more details. see the RAS DES section in the Core Operations chapter of the Databook." hexmask.long.word 0x4 17.--31. 1. "RSVDP_17,Reserved for future use." newline bitfld.long 0x4 16. "FRAMING_ERR_RECOVERY_DISABLE,Framing Error Recovery Disable. This bit disables a transition to Recovery state when a Framing Error is occurred. Note: This register field is sticky." "0,1" newline hexmask.long.byte 0x4 11.--15. 1. "RSVDP_11,Reserved for future use." newline bitfld.long 0x4 10. "DIRECT_LPBKSLV_TO_EXIT,Direct Loopback Slave To Exit. When this bit is set and the LTSSM is in Loopback Slave Active State the LTSSM transitions to Loopback Slave Exit state. Note: This register field is sticky." "0,1" newline bitfld.long 0x4 9. "DIRECT_POLCOMP_TO_DETECT,Direct Polling.Compliance to Detect. When this bit is set and the LTSSM is in Polling Compliance State the LTSSM transitions to Detect state. Note: This register field is sticky." "0,1" newline bitfld.long 0x4 8. "DIRECT_RECIDLE_TO_CONFIG,Direct Recovery.Idle to Configuration. When this bit is set and the LTSSM is in Recovery Idle State the LTSSM transitions to Configuration state. Note: This register field is sticky." "0,1" newline hexmask.long.byte 0x4 3.--7. 1. "RSVDP_3,Reserved for future use." newline bitfld.long 0x4 2. "NOACK_FORCE_LINKDOWN,Force LinkDown. When this bit is set and the controller detects REPLY_NUM rolling over 4 times the LTSSM transitions to Detect State. Note: This register field is sticky." "0,1" newline bitfld.long 0x4 1. "RECOVERY_REQUEST,Recovery Request. When this bit is set to '1' in L0 or L0s the LTSSM starts transitioning to Recovery State. This request does not cause a speed change or re-equalization." "0,1" newline bitfld.long 0x4 0. "HOLD_LTSSM,Hold and Release LTSSM. For as long as this register is '1' the controller stays in the current LTSSM. Note: This register field is sticky." "0,1" group.long (0xB0+0x30C)++0xB line.long 0x0 "SD_STATUS_L1LANE_REG,Silicon Debug Status(Layer1 Per-lane). This viewport register returns the data selected by the following field: - LANE_SELECT in SD_STATUS_L1LANE_REG For more details. see the RAS DES section in the Core Operations chapter of the.." hexmask.long.byte 0x0 24.--31. 1. "DESKEW_POINTER,Deskew Pointer. Indicates Deskew pointer of internal Deskew buffer of selected lane number(LANE_SELECT). Note: This register field is sticky." newline rbitfld.long 0x0 21.--23. "RSVDP_21,Reserved for future use." "0,1,2,3,4,5,6,7" newline rbitfld.long 0x0 20. "PIPE_TXELECIDLE,PIPE:TxElecIdle. Indicates PIPE TXELECIDLE signal of selected lane number(LANE_SELECT). Note: This register field is sticky." "0,1" newline rbitfld.long 0x0 19. "PIPE_RXELECIDLE,PIPE:RxElecIdle. Indicates PIPE RXELECIDLE signal of selected lane number(LANE_SELECT). Note: This register field is sticky." "0,1" newline rbitfld.long 0x0 18. "PIPE_RXVALID,PIPE:RxValid. Indicates PIPE RXVALID signal of selected lane number(LANE_SELECT). Note: This register field is sticky." "0,1" newline rbitfld.long 0x0 17. "PIPE_DETECT_LANE,PIPE:Detect Lane. Indicates whether PHY indicates receiver detection or not on selected lane number(LANE_SELECT). Note: This register field is sticky." "0,1" newline rbitfld.long 0x0 16. "PIPE_RXPOLARITY,PIPE:RxPolarity. Indicates PIPE RXPOLARITY signal of selected lane number(LANE_SELECT). Note: This register field is sticky." "0,1" newline hexmask.long.word 0x0 4.--15. 1. "RSVDP_4,Reserved for future use." newline hexmask.long.byte 0x0 0.--3. 1. "LANE_SELECT,Lane Select. Lane Select register for Silicon Debug Status Register of Layer1-PerLane. - 0x0: Lane0 - 0x1: Lane1 - 0x2: Lane2 - .. - 0xF: Lane15 Note: This register field is sticky." line.long 0x4 "SD_STATUS_L1LTSSM_REG,Silicon Debug Status(Layer1 LTSSM). For more details. see the RAS DES section in the Core Operations chapter of the Databook." hexmask.long.word 0x4 16.--31. 1. "LTSSM_VARIABLE,LTSSM Variable. Indicates internal LTSSM variables defined in the PCI Express Base Specification. C-PCIe Mode: - 0: directed_speed_change - 1: changed_speed_recovery - 2: successful_speed_negotiation - 3: upconfigure_capable; Set to '1' if.." newline rbitfld.long 0x4 15. "LANE_REVERSAL,Lane Reversal Operation. Receiver detected lane reversal. This field is only valid in the L0 LTSSM state. Note: This register field is sticky." "0,1" newline hexmask.long.byte 0x4 11.--14. 1. "RSVDP_11,Reserved for future use." newline rbitfld.long 0x4 8.--10. "PIPE_POWER_DOWN,PIPE:PowerDown. Indicates PIPE PowerDown signal. Note: This register field is sticky." "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 7. "FRAMING_ERR,Framing Error. Indicates Framing Error detection status." "0,1" newline hexmask.long.byte 0x4 0.--6. 1. "FRAMING_ERR_PTR,First Framing Error Pointer. Identifies the first Framing Error using the following encoding. The field contents are only valid value when FRAMING_ERR =1. Received Unexpected Framing Token - 01h: When non- STP/SDP/IDL Token was received.." line.long 0x8 "SD_STATUS_PM_REG,Silicon Debug Status(PM). For more details. see the RAS DES section in the Core Operations chapter of the Databook." hexmask.long.byte 0x8 24.--31. 1. "RSVDP_24,Reserved for future use." newline hexmask.long.byte 0x8 16.--23. 1. "LATCHED_NFTS,Latched N_FTS. Indicates the value of N_FTS in the received TS Ordered Sets from the Link Partner Note: This register field is sticky." newline rbitfld.long 0x8 13.--15. "L1SUB_STATE,L1Sub State. Indicates internal state machine of L1Sub state. - 0h: S_L1_U : idle state - 1h: S_L1_0 : wait for aux_clk_active - 2h: S_L1_0_WAIT4_ACK : wait for pclkack - 3h: S_L1_0_WAIT4_CLKREQ : wait for clkreq - 4h: S_L1_N_ENTRY : check.." "wait for aux_clk_active,?,?,?,?,?,?,?" newline bitfld.long 0x8 12. "PME_RESEND_FLAG,PME Re-send flag. When the DUT sends a PM_PME message TLP the DUT sets PME_Status bit. If host software does not clear PME_Status bit for 100ms(+50%/-5%) the DUT resends the PM_PME Message. This bit indicates that a PM_PME was resent." "0,1" newline hexmask.long.byte 0x8 8.--11. 1. "INTERNAL_PM_SSTATE,Internal PM State(Slave). Indicates internal state machine of Power Management Slave controller. - 0h: S_IDLE - 1h: S_RESPOND_NAK - 2h: S_BLOCK_TLP - 3h: S_WAIT_LAST_TLP_ACK - 4h: S_WAIT_EIDLE - 5h: S_LINK_ENTR_L1 - 6h: S_L1 - 7h:.." newline rbitfld.long 0x8 5.--7. "RSVDP_5,Reserved for future use." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x8 0.--4. 1. "INTERNAL_PM_MSTATE,Internal PM State(Master). Indicates internal state machine of Power Management Master controller. - 00h: IDLE - 01h: L0 - 02h: L0S - 03h: ENTER_L0S - 04h: L0S_EXIT - 05h: WAIT_PMCSR_CPL_SENT - 08h: L1 - 09h: L1_BLOCK_TLP - 0Ah:.." rgroup.long (0xBC+0x30C)++0x3 line.long 0x0 "SD_STATUS_L2_REG,Silicon Debug Status(Layer2). For more details. see the RAS DES section in the Core Operations chapter of the Databook." hexmask.long.byte 0x0 28.--31. 1. "RSVDP_28,Reserved for future use." newline bitfld.long 0x0 27. "FC_INIT2,FC_INIT2. Indicates the controller is in FC_INIT2(VC0) state. Note: This register field is sticky." "0,1" newline bitfld.long 0x0 26. "FC_INIT1,FC_INIT1. Indicates the controller is in FC_INIT1(VC0) state. Note: This register field is sticky." "0,1" newline bitfld.long 0x0 24.--25. "DLCMSM,DLCMSM. Indicates the current DLCMSM. - 00b: DL_INACTIVE - 01b: DL_FC_INIT - 11b: DL_ACTIVE Note: This register field is sticky." "0,1,2,3" newline hexmask.long.word 0x0 12.--23. 1. "RX_ACK_SEQ_NO,Tx Ack Sequence Number. Indicates ACKD_SEQ which is updated by receiving ACK/NAK DLLP. Note: This register field is sticky." newline hexmask.long.word 0x0 0.--11. 1. "TX_TLP_SEQ_NO,Tx Tlp Sequence Number. Indicates next transmit sequence number for transmit TLP. Note: This register field is sticky." group.long (0xC0+0x30C)++0x7 line.long 0x0 "SD_STATUS_L3FC_REG,Silicon Debug Status(Layer3 FC). The CREDIT_DATA[0/1] fields in this viewport register return the data for the VC and TLP Type selected by the following fields: - CREDIT_SEL_VC - CREDIT_SEL_CREDIT_TYPE - CREDIT_SEL_TLP_TYPE -.." hexmask.long.word 0x0 20.--31. 1. "CREDIT_DATA1,Credit Data1. Current FC credit data selected by the CREDIT_SEL_VC CREDIT_SEL_CREDIT_TYPE CREDIT_SEL_TLP_TYPE and CREDIT_SEL_HD viewport-select fields. - Rx: Credit Allocated Value - Tx: Credit Limit Value. This value is valid when.." newline hexmask.long.word 0x0 8.--19. 1. "CREDIT_DATA0,Credit Data0. Current FC credit data selected by the CREDIT_SEL_VC CREDIT_SEL_CREDIT_TYPE CREDIT_SEL_TLP_TYPE and CREDIT_SEL_HD viewport-select fields. - Rx: Credit Received Value - Tx: Credit Consumed Value Note: This register field is.." newline rbitfld.long 0x0 7. "RSVDP_7,Reserved for future use." "0,1" newline bitfld.long 0x0 6. "CREDIT_SEL_HD,Credit Select(HeaderData). This field in conjunction with the CREDIT_SEL_VC CREDIT_SEL_CREDIT_TYPE and CREDIT_SEL_TLP_TYPE viewport-select fields determines that data that is returned by the CREDIT_DATA0 and CREDIT_DATA1 data fields. -.." "Header Credit,Data Credit" newline bitfld.long 0x0 4.--5. "CREDIT_SEL_TLP_TYPE,Credit Select(TLP Type). This field in conjunction with the CREDIT_SEL_VC CREDIT_SEL_CREDIT_TYPE and CREDIT_SEL_HD viewport-select fields determines that data that is returned by the CREDIT_DATA0 and CREDIT_DATA1 data fields. - 0x0:.." "Posted,Non-Posted,Completion,?" newline bitfld.long 0x0 3. "CREDIT_SEL_CREDIT_TYPE,Credit Select(Credit Type). This field in conjunction with the CREDIT_SEL_VC CREDIT_SEL_TLP_TYPE and CREDIT_SEL_HD viewport-select fields determines that data that is returned by the CREDIT_DATA0 and CREDIT_DATA1 data fields. -.." "Rx,Tx" newline bitfld.long 0x0 0.--2. "CREDIT_SEL_VC,Credit Select(VC). This field in conjunction with the CREDIT_SEL_CREDIT_TYPE CREDIT_SEL_TLP_TYPE and CREDIT_SEL_HD viewport-select fields determines that data that is returned by the CREDIT_DATA0 and CREDIT_DATA1 data fields. - 0x0: VC0 -.." "VC0,VC1,VC2,?,?,?,?,VC7" line.long 0x4 "SD_STATUS_L3_REG,Silicon Debug Status(Layer3). For more details. see the RAS DES section in the Core Operations chapter of the Databook." hexmask.long.tbyte 0x4 8.--31. 1. "RSVDP_8,Reserved for future use." newline bitfld.long 0x4 7. "MFTLP_STATUS,Malformed TLP Status. Indicates malformed TLP has occurred." "0,1" newline hexmask.long.byte 0x4 0.--6. 1. "MFTLP_POINTER,First Malformed TLP Error Pointer. Indicates the element of the received first malformed TLP. This pointer is validated by MFTLP_STATUS. - 01h: AtomicOp address alignment - 02h: AtomicOp operand - 03h: AtomicOp byte enable - 04h: TLP length.." group.long (0xD0+0x30C)++0xB line.long 0x0 "SD_EQ_CONTROL1_REG,Silicon Debug EQ Control 1. This is a viewport control register. Setting the EQ_RATE_SEL and EQ_LANE_SEL fields in this register determine the per-lane Silicon Debug EQ Status data returned by the SD_EQ_STATUS[1/2/3] viewport.." hexmask.long.byte 0x0 24.--31. 1. "FOM_TARGET,FOM Target. Indicates figure of merit target criteria value of EQ Master(DSP in EQ Phase3/USP in EQ Phase2). This field is only valid when GEN3_EQ_FB_MODE is 0001b(Figure Of Merit). Note: This register field is sticky." newline bitfld.long 0x0 23. "FOM_TARGET_ENABLE,FOM Target Enable. Enables the FOM_TARGET fields. Note: This register field is sticky." "0,1" newline hexmask.long.byte 0x0 18.--22. 1. "RSVDP_18,Reserved for future use." newline bitfld.long 0x0 16.--17. "EVAL_INTERVAL_TIME,Eval Interval Time. Indicates interval time of RxEqEval assertion. - 00: 500ns - 01: 1us - 10: 2us - 11: 4us This field is used for EQ Master(DSP in EQ Phase3/USP in EQ Phase2). Note: This register field is sticky." "0,1,2,3" newline hexmask.long.byte 0x0 10.--15. 1. "RSVDP_10,Reserved for future use." newline bitfld.long 0x0 8.--9. "EXT_EQ_TIMEOUT,Extends EQ Phase2/3 Timeout. This field is used when the Ltssm is in Recovery.EQ2/3. When this field is set the value of EQ2/3 timeout is extended. EQ Master(DSP in EQ Phase3/USP in EQ Phase2). - 00: 24ms (default) - 01: 48ms (x2) - 10:.." "0,1,2,3" newline rbitfld.long 0x0 6.--7. "RSVDP_6,Reserved for future use." "0,1,2,3" newline bitfld.long 0x0 4.--5. "EQ_RATE_SEL,EQ Status Rate Select. Setting this field in conjunction with the EQ_LANE_SEL field determines the per-lane Silicon Debug EQ Status data returned by the SD_EQ_CONTROL[2/3] and SD_EQ_STATUS[1/2/3] viewport registers. - 0x0: 8.0GT/s Speed.." "0,1,2,3" newline hexmask.long.byte 0x0 0.--3. 1. "EQ_LANE_SEL,EQ Status Lane Select. Setting this field in conjunction with the EQ_RATE_SEL field determines the per-lane Silicon Debug EQ Status data returned by the SD_EQ_CONTROL[2/3] and SD_EQ_STATUS[1/2/3] viewport registers. - 0x0: Lane0 - 0x1: Lane1.." line.long 0x4 "SD_EQ_CONTROL2_REG,Silicon Debug EQ Control 2. This viewport register returns the value for the rate and lane selected by the EQ_RATE_SEL and EQ_LANE_SEL fields in the SD_EQ_CONTROL1_REG register. For more details. see the RAS DES section in the Core.." rbitfld.long 0x4 31. "RSVDP_31,Reserved for future use." "0,1" newline bitfld.long 0x4 30. "FORCE_LOCAL_TX_PRESET_ENABLE,Force Local Transmitter Preset Enable. Enables the FORCE_LOCAL_TX_PRESET field. If select rate in the EQ_RATE_SEL field is 32.0GT/s Speed this feature is not available. Note: This register field is sticky." "0,1" newline bitfld.long 0x4 29. "FORCE_LOCAL_RX_HINT_ENABLE,Force Local Receiver Preset Hint Enable. Enables the FORCE_LOCAL_RX_HINT field. If select rate in the EQ_RATE_SEL field is other than 8.0GT/s Speed this feature is not available. Note: This register field is sticky." "0,1" newline bitfld.long 0x4 28. "FORCE_LOCAL_TX_COEF_ENABLE,Force Local Transmitter Coefficient Enable. Enables the following fields: - FORCE_LOCAL_TX_PRE_CURSOR - FORCE_LOCAL_TX_CURSOR - FORCE_LOCAL_TX_POST_CURSOR Note: This register field is sticky." "0,1" newline hexmask.long.byte 0x4 24.--27. 1. "FORCE_LOCAL_TX_PRESET,Force Local Transmitter Preset. Indicates initial preset value of USP in EQ Slave(EQ Phase2) instead of receiving EQ TS2. If select rate in the EQ_RATE_SEL field is 32.0GT/s Speed this feature is not available. Note: This register.." newline rbitfld.long 0x4 21.--23. "RSVDP_21,Reserved for future use." "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 18.--20. "FORCE_LOCAL_RX_HINT,Force Local Receiver Preset Hint. Indicates the RxPresetHint value of EQ Slave(DSP in EQ Phase2/USP in EQ Phase3) instead of received or set value. If select rate in the EQ_RATE_SEL field is other than 8.0GT/s Speed this feature is.." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x4 12.--17. 1. "FORCE_LOCAL_TX_POST_CURSOR,Force Local Transmitter Post-Cursor. Indicates the coefficient value of EQ Slave(DSP in EQ Phase2/USP in EQ Phase3) instead of the value instructed from link partner. Note: This register field is sticky." newline hexmask.long.byte 0x4 6.--11. 1. "FORCE_LOCAL_TX_CURSOR,Force Local Transmitter Cursor. Indicates the coefficient value of EQ Slave(DSP in EQ Phase2/USP in EQ Phase3) instead of the value instructed from link partner. Note: This register field is sticky." newline hexmask.long.byte 0x4 0.--5. 1. "FORCE_LOCAL_TX_PRE_CURSOR,Force Local Transmitter Pre-cursor. Indicates the coefficient value of EQ Slave(DSP in EQ Phase2/USP in EQ Phase3) instead of the value instructed from link partner. Note: This register field is sticky." line.long 0x8 "SD_EQ_CONTROL3_REG,Silicon Debug EQ Control 3. This viewport register returns the value for the rate and lane selected by the EQ_RATE_SEL and EQ_LANE_SEL fields in the SD_EQ_CONTROL1_REG register. For more details. see the RAS DES section in the Core.." rbitfld.long 0x8 29.--31. "RSVDP_29,Reserved for future use." "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 28. "FORCE_REMOTE_TX_COEF_ENABLE,Force Remote Transmitter Coefficient Enable. Enables the following fields: - FORCE_REMOTE_TX_PRE_CURSOR - FORCE_REMOTE_TX_CURSOR - FORCE_REMOTE_TX_POST_CURSOR This function can only be used when GEN3_EQ_FB_MODE =.." "0,1" newline hexmask.long.word 0x8 18.--27. 1. "RSVDP_18,Reserved for future use." newline hexmask.long.byte 0x8 12.--17. 1. "FORCE_REMOTE_TX_POST_CURSOR,Force Remote Transmitter Post-Cursor. Indicates the coefficient value of EQ Master(DSP in EQ Phase3/USP in EQ Phase2) instead of the value instructed from local phy in dirchange mode. Note: This register field is sticky." newline hexmask.long.byte 0x8 6.--11. 1. "FORCE_REMOTE_TX_CURSOR,Force Remote Transmitter Cursor. Indicates the coefficient value of EQ Master(DSP in EQ Phase3/USP in EQ Phase2) instead of the value instructed from local phy in dirchange mode. Note: This register field is sticky." newline hexmask.long.byte 0x8 0.--5. 1. "FORCE_REMOTE_TX_PRE_CURSOR,Force Remote Transmitter Pre-Cursor. Indicates the coefficient value of EQ Master(DSP in EQ Phase3/USP in EQ Phase2) instead of the value instructed from local phy in dirchange mode. Note: This register field is sticky." rgroup.long (0xE0+0x30C)++0xB line.long 0x0 "SD_EQ_STATUS1_REG,Silicon Debug EQ Status 1. This viewport register returns the first of three words of Silicon Debug EQ Status data for the rate and lane selected by the EQ_RATE_SEL and EQ_LANE_SEL fields in the SD_EQ_CONTROL1_REG register. The.." hexmask.long.tbyte 0x0 8.--31. 1. "RSVDP_8,Reserved for future use." newline bitfld.long 0x0 7. "EQ_REJECT_EVENT,EQ Reject Event. Indicates that the controller receives two consecutive TS1 OS w/Reject=1b during EQ Master phase(DSP in EQ Phase3/USP in EQ Phase2). This bit is automatically cleared when the controller starts EQ Master phase again." "0,1" newline bitfld.long 0x0 6. "EQ_RULEC_VIOLATION,EQ Rule C Violation. Indicates that coefficients rule C violation is detected in the values provided by PHY using direction change method during EQ Master phase(DSP in EQ Phase3/USP in EQ Phase2). The coefficients rule C correspond to.." "0,1" newline bitfld.long 0x0 5. "EQ_RULEB_VIOLATION,EQ Rule B Violation. Indicates that coefficients rule B violation is detected in the values provided by PHY using direction change method during EQ Master phase(DSP in EQ Phase3/USP in EQ Phase2). The coefficients rules B correspond to.." "0,1" newline bitfld.long 0x0 4. "EQ_RULEA_VIOLATION,EQ Rule A Violation. Indicates that coefficients rule A violation is detected in the values provided by PHY using direction change method during EQ Master phase(DSP in EQ Phase3/USP in EQ Phase2). The coefficients rules A correspond to.." "0,1" newline bitfld.long 0x0 3. "RSVDP_3,Reserved for future use." "0,1" newline bitfld.long 0x0 1.--2. "EQ_CONVERGENCE_INFO,EQ Convergence Info. Indicates equalization convergence information. - 0x0: Equalization is not attempted - 0x1: Equalization finished successfully - 0x2: Equalization finished unsuccessfully - 0x3: Reserved This bit is automatically.." "Equalization is not attempted,Equalization finished successfully,Equalization finished unsuccessfully,Reserved" newline bitfld.long 0x0 0. "EQ_SEQUENCE,EQ Sequence. Indicates that the controller is starting the equalization sequence. Note: This register field is sticky." "0,1" line.long 0x4 "SD_EQ_STATUS2_REG,Silicon Debug EQ Status 2. This viewport register returns the second of three words of Silicon Debug EQ Status data for the rate and lane selected by the EQ_RATE_SEL and EQ_LANE_SEL fields in the SD_EQ_CONTROL1_REG register. Each field.." hexmask.long.byte 0x4 24.--31. 1. "EQ_LOCAL_FOM_VALUE,EQ Local Figure of Merit. Indicates Local maximum Figure of Merit value. Note: This register field is sticky." newline bitfld.long 0x4 21.--23. "RSVDP_21,Reserved for future use." "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 18.--20. "EQ_LOCAL_RX_HINT,EQ Local Receiver Preset Hint. Indicates Local Receiver Preset Hint value. If select rate in the EQ_RATE_SEL field is other than 8.0GT/s Speed this feature is not available. Note: This register field is sticky." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x4 12.--17. 1. "EQ_LOCAL_POST_CURSOR,EQ Local Post-Cursor. Indicates Local post cursor coefficient value. Note: This register field is sticky." newline hexmask.long.byte 0x4 6.--11. 1. "EQ_LOCAL_CURSOR,EQ Local Cursor. Indicates Local cursor coefficient value. Note: This register field is sticky." newline hexmask.long.byte 0x4 0.--5. 1. "EQ_LOCAL_PRE_CURSOR,EQ Local Pre-Cursor. Indicates Local pre cursor coefficient value. Note: This register field is sticky." line.long 0x8 "SD_EQ_STATUS3_REG,Silicon Debug EQ Status 3. This viewport register returns the third of three words of Silicon Debug EQ Status data for the rate and lane selected by the EQ_RATE_SEL and EQ_LANE_SEL fields in the SD_EQ_CONTROL1_REG register. Each field.." bitfld.long 0x8 30.--31. "RSVDP_30,Reserved for future use." "0,1,2,3" newline hexmask.long.byte 0x8 24.--29. 1. "EQ_REMOTE_FS,EQ Remote FS. Indicates Remote FS value. Note: This register field is sticky." newline hexmask.long.byte 0x8 18.--23. 1. "EQ_REMOTE_LF,EQ Remote LF. Indicates Remote LF value. Note: This register field is sticky." newline hexmask.long.byte 0x8 12.--17. 1. "EQ_REMOTE_POST_CURSOR,EQ Remote Post-Cursor. Indicates Remote post cursor coefficient value. Note: This register field is sticky." newline hexmask.long.byte 0x8 6.--11. 1. "EQ_REMOTE_CURSOR,EQ Remote Cursor. Indicates Remote cursor coefficient value. Note: This register field is sticky." newline hexmask.long.byte 0x8 0.--5. 1. "EQ_REMOTE_PRE_CURSOR,EQ Remote Pre-Cursor. Indicates Remote pre cursor coefficient value. Note: This register field is sticky." tree.end tree "PF0_SN_CAP (Device Serial Number Capability Structure)" group.long (0x0+0x170)++0xB line.long 0x0 "SN_BASE,Device Serial Number Extended Capability Header. For a description of this standard PCIe register. see the PCI Express Base Specification." hexmask.long.word 0x0 20.--31. 1. "SN_NEXT_OFFSET,Next Capability Offset. For a description of this standard PCIe register field see the PCI Express Base Specification. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then.." hexmask.long.byte 0x0 16.--19. 1. "SN_CAP_VERSION,Capability Version. For a description of this standard PCIe register field see the PCI Express Base Specification. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky).." hexmask.long.word 0x0 0.--15. 1. "SN_PCIE_EXTENDED_CAP_ID,Serial Number Extended Capability ID. For a description of this standard PCIe register field see the PCI Express Base Specification. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if.." line.long 0x4 "SER_NUM_REG_DW_1,Serial Number 1 Register. For a description of this standard PCIe register. see the PCI Express Base Specification." hexmask.long 0x4 0.--31. 1. "SN_SER_NUM_REG_1_DW,IEEE 64 bit Device Serial Number (DW 1). For a description of this standard PCIe register field see the PCI Express Base Specification. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if.." line.long 0x8 "SER_NUM_REG_DW_2,Serial Number 2 Register. For a description of this standard PCIe register. see the PCI Express Base Specification." hexmask.long 0x8 0.--31. 1. "SN_SER_NUM_REG_2_DW,IEEE 64 bit Device Serial Number (DW 2). For a description of this standard PCIe register field see the PCI Express Base Specification. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if.." tree.end tree "PF0_VSECRAS_CAP (PF RAS Datapath Protection Capability Structure (VSEC))" group.long (0x0+0x480)++0x3 line.long 0x0 "RASDP_EXT_CAP_HDR_OFF,PCIe Extended capability ID. Capability version and Next capability offset. For a description of this standard PCIe register. see the PCI Express Specification." hexmask.long.word 0x0 20.--31. 1. "NEXT_OFFSET,Next Capability Offset. For a description of this standard PCIe register see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else.." newline hexmask.long.byte 0x0 16.--19. 1. "CAP,Capability Version. For a description of this standard PCIe register see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note:.." newline hexmask.long.word 0x0 0.--15. 1. "ID,PCI Express Extended Capability ID. For a description of this standard PCIe register see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else.." rgroup.long (0x4+0x480)++0x3 line.long 0x0 "RASDP_VENDOR_SPECIFIC_HDR_OFF,Vendor Specific Header. For a description of this standard PCIe register. see the PCI Express Specification." hexmask.long.word 0x0 20.--31. 1. "VSEC_LENGTH,VSEC Length. For a description of this standard PCIe register see the PCI Express Specification. Note: This register field is sticky." newline hexmask.long.byte 0x0 16.--19. 1. "VSEC_REV,VSEC Rev. For a description of this standard PCIe register see the PCI Express Specification. Note: This register field is sticky." newline hexmask.long.word 0x0 0.--15. 1. "VSEC_ID,VSEC ID. For a description of this standard PCIe register see the PCI Express Specification. Note: This register field is sticky." group.long (0x8+0x480)++0x7 line.long 0x0 "RASDP_ERROR_PROT_CTRL_OFF,ECC error correction control. Allows you to disable ECC error correction for RAMs and datapath. When the AXI Bridge Module is implemented and the master / slave clocks are asynchronous to the PCIe native controller clock.." hexmask.long.byte 0x0 24.--31. 1. "RSVDP_24,Reserved for future use." newline bitfld.long 0x0 23. "ERROR_PROT_DISABLE_CXS_RX,Error correction disable for CXS Tx path (PCIe Rx path). Note: This register field is sticky." "0,1" newline bitfld.long 0x0 22. "ERROR_PROT_DISABLE_ADM_RX,Error correction disable for ADM Rx path. Note: This register field is sticky." "0,1" newline bitfld.long 0x0 21. "ERROR_PROT_DISABLE_LAYER3_RX,Error correction disable for layer 3 Rx path. Note: This register field is sticky." "0,1" newline bitfld.long 0x0 20. "ERROR_PROT_DISABLE_LAYER2_RX,Error correction disable for layer 2 Rx path. Note: This register field is sticky." "0,1" newline bitfld.long 0x0 19. "ERROR_PROT_DISABLE_DMA_READ,Error correction disable for DMA read engine. Note: This register field is sticky." "0,1" newline bitfld.long 0x0 18. "ERROR_PROT_DISABLE_AXI_BRIDGE_INBOUND_REQUEST,Error correction disable for AXI bridge inbound request path. Note: This register field is sticky." "0,1" newline bitfld.long 0x0 17. "ERROR_PROT_DISABLE_AXI_BRIDGE_INBOUND_COMPLETION,Error correction disable for AXI bridge inbound completion composer. Does not disable the error detection reporting for 1-bit and 2-bit ECC errors. Note: This register field is sticky." "?,bit and 2-bit ECC errors" newline bitfld.long 0x0 16. "ERROR_PROT_DISABLE_RX,Global error correction disable for all Rx layers. Note: This register field is sticky." "0,1" newline hexmask.long.byte 0x0 9.--15. 1. "RSVDP_9,Reserved for future use." newline bitfld.long 0x0 8. "ERROR_PROT_DISABLE_DTIM_TX,Error correction disable for DTIM Tx path. Note: This register field is sticky." "0,1" newline bitfld.long 0x0 7. "ERROR_PROT_DISABLE_CXS_TX,Error correction disable for CXS Rx path (PCIe Tx path). Note: This register field is sticky." "0,1" newline bitfld.long 0x0 6. "ERROR_PROT_DISABLE_ADM_TX,Error correction disable for Adm Tx path. Note: This register field is sticky." "0,1" newline bitfld.long 0x0 5. "ERROR_PROT_DISABLE_LAYER3_TX,Error correction disable for layer 3 Tx path. Note: This register field is sticky." "0,1" newline bitfld.long 0x0 4. "ERROR_PROT_DISABLE_LAYER2_TX,Error correction disable for layer 2 Tx path. Note: This register field is sticky." "0,1" newline bitfld.long 0x0 3. "ERROR_PROT_DISABLE_DMA_WRITE,Error correction disable for DMA write engine. Note: This register field is sticky." "0,1" newline bitfld.long 0x0 2. "ERROR_PROT_DISABLE_AXI_BRIDGE_OUTBOUND,Error correction disable for AXI bridge outbound request path. Note: This register field is sticky." "0,1" newline bitfld.long 0x0 1. "ERROR_PROT_DISABLE_AXI_BRIDGE_MASTER,Error correction disable for AXI bridge master completion buffer. Note: This register field is sticky." "0,1" newline bitfld.long 0x0 0. "ERROR_PROT_DISABLE_TX,Global error correction disable for all Tx layers. Does not disable the error detection reporting for 1-bit and 2-bit ECC errors. Note: This register field is sticky." "?,bit and 2-bit ECC errors" line.long 0x4 "RASDP_CORR_COUNTER_CTRL_OFF,Corrected error (1-bit ECC) counter selection and control. This is a viewport control register. Setting the CORR_COUNTER_SELECTION_REGION and CORR_COUNTER_SELECTION fields in this register determine the counter data returned.." hexmask.long.byte 0x4 24.--31. 1. "CORR_COUNTER_SELECTION,Counter selection. This field selects the counter ID (within the region defined by CORR_COUNTER_SELECTION_REGION) whose contents can be read from the RASDP_CORR_COUNT_REPORT_OFF register. You can cycle this field value from 0 to.." newline hexmask.long.byte 0x4 20.--23. 1. "CORR_COUNTER_SELECTION_REGION,Select correctable counter region: - 0x0: Region select for Adm Rx path - 0x1: Region select for layer 3 Rx path - 0x2: Region select for layer 2 Rx path - 0x3: Region select for DMA inbound path - 0x4: Region select for AXI.." newline hexmask.long.word 0x4 5.--19. 1. "RSVDP_5,Reserved for future use." newline bitfld.long 0x4 4. "CORR_EN_COUNTERS,Enable correctable errors counters. - 1: counters increment when the controller detects a correctable error - 0: counters are frozen The counters are enabled by default." "counters are frozen,counters increment when the controller detects a.." newline rbitfld.long 0x4 1.--3. "RSVDP_1,Reserved for future use." "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 0. "CORR_CLEAR_COUNTERS,Clear all correctable error counters." "0,1" rgroup.long (0x10+0x480)++0x3 line.long 0x0 "RASDP_CORR_COUNT_REPORT_OFF,Corrected error (1-bit ECC) counter data. This viewport register returns the counter data selected by the CORR_COUNTER_SELECTION_REGION and CORR_COUNTER_SELECTION fields in the RASDP_CORR_COUNTER_CTRL_OFF register." hexmask.long.byte 0x0 24.--31. 1. "CORR_COUNTER_SELECTED,Counter selection. Returns the value set in the CORR_COUNTER_SELECTION field of the RASDP_CORR_COUNTER_CTRL_OFF register." newline hexmask.long.byte 0x0 20.--23. 1. "CORR_COUNTER_SELECTED_REGION,Selected correctable counter region: - 0x0: Region select for Adm Rx path - 0x1: Region select for layer 3 Rx path - 0x2: Region select for layer 2 Rx path - 0x3: Region select for DMA inbound path - 0x4: Region select for.." newline hexmask.long.word 0x0 8.--19. 1. "RSVDP_8,Reserved for future use." newline hexmask.long.byte 0x0 0.--7. 1. "CORR_COUNTER,Current corrected error count for the selected counter." group.long (0x14+0x480)++0x3 line.long 0x0 "RASDP_UNCORR_COUNTER_CTRL_OFF,Uncorrected error (2-bit ECC and parity) counter selection and control. This is a viewport control register. Setting the UNCORR_COUNTER_SELECTION_REGION and UNCORR_COUNTER_SELECTION fields in this register determine the.." hexmask.long.byte 0x0 24.--31. 1. "UNCORR_COUNTER_SELECTION,Counter selection. This field selects the counter ID (within the region defined by UNCORR_COUNTER_SELECTION_REGION) whose contents can be read from the RASDP_UNCORR_COUNT_REPORT_OFF register. You can cycle this field value from 0.." newline hexmask.long.byte 0x0 20.--23. 1. "UNCORR_COUNTER_SELECTION_REGION,Select uncorrectable counter region: - 0x0: Region select for Adm Rx path - 0x1: Region select for layer 3 Rx path - 0x2: Region select for layer 2 Rx path - 0x3: Region select for DMA inbound path - 0x4: Region select for.." newline hexmask.long.word 0x0 5.--19. 1. "RSVDP_5,Reserved for future use." newline bitfld.long 0x0 4. "UNCORR_EN_COUNTERS,Enable uncorrectable errors counters. - 1: enables the counters to increment on detected correctable errors - 0: counters are frozen The counters are enabled by default." "counters are frozen,enables the counters to increment on detected.." newline rbitfld.long 0x0 1.--3. "RSVDP_1,Reserved for future use." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 0. "UNCORR_CLEAR_COUNTERS,Clear uncorrectable errors counters. When asserted causes all counters tracking the uncorrectable errors to be cleared." "0,1" rgroup.long (0x18+0x480)++0x3 line.long 0x0 "RASDP_UNCORR_COUNT_REPORT_OFF,Uncorrected error (2-bit ECC and parity) counter data. This viewport register returns the counter data selected by the UNCORR_COUNTER_SELECTION_REGION and UNCORR_COUNTER_SELECTION fields in the RASDP_UNCORR_COUNTER_CTRL_OFF.." hexmask.long.byte 0x0 24.--31. 1. "UNCORR_COUNTER_SELECTED,Counter selection. Returns the value set in the UNCORR_COUNTER_SELECTION field of the RASDP_UNCORR_COUNTER_CTRL_OFF register." newline hexmask.long.byte 0x0 20.--23. 1. "UNCORR_COUNTER_SELECTED_REGION,Selected uncorrectable counter region: - 0x0: Region select for Adm Rx path - 0x1: Region select for layer 3 Rx path - 0x2: Region select for layer 2 Rx path - 0x3: Region select for DMA inbound path - 0x4: Region select.." newline hexmask.long.word 0x0 8.--19. 1. "RSVDP_8,Reserved for future use." newline hexmask.long.byte 0x0 0.--7. 1. "UNCORR_COUNTER,Current uncorrected error count for the selected counter" group.long (0x1C+0x480)++0x3 line.long 0x0 "RASDP_ERROR_INJ_CTRL_OFF,Error injection control for the following features: - 1-bit or 2-bit injection - Continuous or fixed-number (n) injection modes - Global enable/disable - Selectable location where injection occurs" hexmask.long.byte 0x0 24.--31. 1. "RSVDP_24,Reserved for future use." newline hexmask.long.byte 0x0 16.--23. 1. "ERROR_INJ_LOC,Error injection location. Selects where error injection takes place. You can cycle this field value from 0 to 255 to access all locations according to the detailed report of check points at.." newline hexmask.long.byte 0x0 8.--15. 1. "ERROR_INJ_COUNT,Error injection count. - 0: errors are inserted in every TLP until you clear ERROR_INJ_EN. - 1: one errors injected - 2: two errors injected - n: amount of errors injected" newline rbitfld.long 0x0 6.--7. "RSVDP_6,Reserved for future use." "0,1,2,3" newline bitfld.long 0x0 4.--5. "ERROR_INJ_TYPE,Error injection type: - 0: none - 1: 1-bit - 2: 2-bit" "none,bit,bit,?" newline rbitfld.long 0x0 1.--3. "RSVDP_1,Reserved for future use." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 0. "ERROR_INJ_EN,Error injection global enable. When set enables the error insertion logic." "0,1" rgroup.long (0x20+0x480)++0x7 line.long 0x0 "RASDP_CORR_ERROR_LOCATION_OFF,Corrected errors locations. For more details. see the RAS Data Protection (DP) section in the Core Operations chapter of the Databook." hexmask.long.byte 0x0 24.--31. 1. "LOC_LAST_CORR_ERROR,Location/ID of the last corrected error within the region defined by REG_LAST_CORR_ERROR. You can cycle this field value from 0 to 255 to access all counters according to the detailed report of check points at.." newline hexmask.long.byte 0x0 20.--23. 1. "REG_LAST_CORR_ERROR,Region of the last corrected error: - 0x0: Region select for Adm Rx path - 0x1: Region select for layer 3 Rx path - 0x2: Region select for layer 2 Rx path - 0x3: Region select for DMA inbound path - 0x4: Region select for AXI bridge.." newline hexmask.long.byte 0x0 16.--19. 1. "RSVDP_16,Reserved for future use." newline hexmask.long.byte 0x0 8.--15. 1. "LOC_FIRST_CORR_ERROR,Location/ID of the first corrected error within the region defined by REG_FIRST_CORR_ERROR. You can cycle this field value from 0 to 255 to access all counters according to the detailed report of check points at.." newline hexmask.long.byte 0x0 4.--7. 1. "REG_FIRST_CORR_ERROR,Region of the first corrected error: - 0x0: Region select for Adm Rx path - 0x1: Region select for layer 3 Rx path - 0x2: Region select for layer 2 Rx path - 0x3: Region select for DMA inbound path - 0x4: Region select for AXI bridge.." newline hexmask.long.byte 0x0 0.--3. 1. "RSVDP_0,Reserved for future use." line.long 0x4 "RASDP_UNCORR_ERROR_LOCATION_OFF,Uncorrected errors locations. For more details. see the RAS Data Protection (DP) section in the Core Operations chapter of the Databook." hexmask.long.byte 0x4 24.--31. 1. "LOC_LAST_UNCORR_ERROR,Location/ID of the last uncorrected error within the region defined by REG_LAST_UNCORR_ERROR. You can cycle this field value from 0 to 255 to access all counters according to the detailed report of check points at.." newline hexmask.long.byte 0x4 20.--23. 1. "REG_LAST_UNCORR_ERROR,Region of the last uncorrected error: - 0x0: Region select for Adm Rx path - 0x1: Region select for layer 3 Rx path - 0x2: Region select for layer 2 Rx path - 0x3: Region select for DMA inbound path - 0x4: Region select for AXI.." newline hexmask.long.byte 0x4 16.--19. 1. "RSVDP_16,Reserved for future use." newline hexmask.long.byte 0x4 8.--15. 1. "LOC_FIRST_UNCORR_ERROR,Location/ID of the first uncorrected error within the region defined by REG_FIRST_UNCORR_ERROR. You can cycle this field value from 0 to 255 to access all counters according to the detailed report of check points at.." newline hexmask.long.byte 0x4 4.--7. 1. "REG_FIRST_UNCORR_ERROR,Region of the first uncorrected error: - 0x0: Region select for Adm Rx path - 0x1: Region select for layer 3 Rx path - 0x2: Region select for layer 2 Rx path - 0x3: Region select for DMA inbound path - 0x4: Region select for AXI.." newline hexmask.long.byte 0x4 0.--3. 1. "RSVDP_0,Reserved for future use." group.long (0x28+0x480)++0x7 line.long 0x0 "RASDP_ERROR_MODE_EN_OFF,RASDP error mode enable. The controller enters RASDP error mode (if ERROR_MODE_EN =1) upon detection of the first uncorrectable error. During this mode: - Rx TLPs that are forwarded to your application are not guaranteed to be.." hexmask.long 0x0 2.--31. 1. "RSVDP_2,Reserved for future use." newline bitfld.long 0x0 1. "AUTO_LINK_DOWN_EN,Write '1' to enable the controller to bring the link down when the controller enters RASDP error mode. Note: This register field is sticky." "0,1" newline bitfld.long 0x0 0. "ERROR_MODE_EN,Write '1' to enable the controller enter RASDP error mode when it detects an uncorrectable error. Note: This register field is sticky." "0,1" line.long 0x4 "RASDP_ERROR_MODE_CLEAR_OFF,Exit RASDP error mode. For more details. see the RAS Data Protection (DP) section in the Core Operations chapter of the Databook." hexmask.long 0x4 1.--31. 1. "RSVDP_1,Reserved for future use." newline bitfld.long 0x4 0. "ERROR_MODE_CLEAR,Write '1' to take the controller out of RASDP error mode. The controller will then report uncorrectable errors (through AER internal error reporting) and also stop nullifying/discarding TLPs." "0,1" rgroup.long (0x30+0x480)++0x7 line.long 0x0 "RASDP_RAM_ADDR_CORR_ERROR_OFF,RAM Address where a corrected error (1-bit ECC) has been detected. For more details. see the RAS Data Protection (DP) section in the Core Operations chapter of the Databook." hexmask.long.byte 0x0 28.--31. 1. "RAM_INDEX_CORR_ERROR,RAM index where a corrected error (1-bit ECC) has been detected." newline bitfld.long 0x0 27. "RSVDP_27,Reserved for future use." "0,1" newline hexmask.long 0x0 0.--26. 1. "RAM_ADDR_CORR_ERROR,RAM Address where a corrected error (1-bit ECC) has been detected." line.long 0x4 "RASDP_RAM_ADDR_UNCORR_ERROR_OFF,RAM Address where an uncorrected error (2-bit ECC) has been detected. For more details. see the RAS Data Protection (DP) section in the Core Operations chapter of the Databook." hexmask.long.byte 0x4 28.--31. 1. "RAM_INDEX_UNCORR_ERROR,RAM index where an uncorrected error (2-bit ECC) has been detected." newline bitfld.long 0x4 27. "RSVDP_27,Reserved for future use." "0,1" newline hexmask.long 0x4 0.--26. 1. "RAM_ADDR_UNCORR_ERROR,RAM Address where an uncorrected error (2-bit ECC) has been detected." tree.end tree "PF0_RTR_CAP (PF RTR Capability Structure)" group.long (0x0+0x2F8)++0xB line.long 0x0 "RTR_EXT_CAP_HDR_OFF,Readiness Time Reporting PCI Express Extended Capability Header. For a description of this standard PCIe register. see the PCI Express Specification." hexmask.long.word 0x0 20.--31. 1. "RTR_NEXT_OFFSET,Next Capability Offset. For a description of this standard PCIe register field see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky).." hexmask.long.byte 0x0 16.--19. 1. "RTR_CAP_VERSION,Capability Version. For a description of this standard PCIe register field see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky).." hexmask.long.word 0x0 0.--15. 1. "RTR_EXT_CAP_ID,PCI Express Extended Capability ID. For a description of this standard PCIe register field see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then.." line.long 0x4 "READI_TIME_REPORTING1_OFF,Readiness Time Reporting 1. For a description of this standard PCIe register. see the PCI Express Specification." bitfld.long 0x4 31. "RTR_TIME_VALID,Valid. For a description of this standard PCIe register field see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky)" "0,1" hexmask.long.byte 0x4 24.--30. 1. "RSVDP_24,Reserved for future use." hexmask.long.word 0x4 12.--23. 1. "DL_UP_TIME,DL_UP Time. For a description of this standard PCIe register field see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky)" hexmask.long.word 0x4 0.--11. 1. "RESET_TIME,Reset Time. For a description of this standard PCIe register field see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky)" line.long 0x8 "READI_TIME_REPORTING2_OFF,Readiness Time Reporting 2. For a description of this standard PCIe register. see the PCI Express Specification." hexmask.long.byte 0x8 24.--31. 1. "RSVDP_24,Reserved for future use." hexmask.long.word 0x8 12.--23. 1. "D3HOT_D0_TIME,D3hot to D0 Time. For a description of this standard PCIe register field see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else.." hexmask.long.word 0x8 0.--11. 1. "FLR_TIME,FLR Time. For a description of this standard PCIe register field see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky)" tree.end tree "PF0_RTR_CAP_DBI2 (DBI2 Shadow Block: PF RTR Capability Structure)" rgroup.long (0x4+0x12F8)++0x7 line.long 0x0 "SHADOW_READI_TIME_REPORTING1_OFF,Shadow Register Readiness Time Reporting 1. For a description of this standard PCIe register. see the PCI Express Specification." bitfld.long 0x0 31. "RTR_TIME_VALID,Shadow Valid in the shadow register. For a description of this standard PCIe register field see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access - Dbi: No access - Dbi2: if.." "0,1" hexmask.long.tbyte 0x0 12.--30. 1. "RSVDP_12,Reserved for future use." hexmask.long.word 0x0 0.--11. 1. "RESET_TIME,Shadow Reset Time in the shadow register. For a description of this standard PCIe register field see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access - Dbi: No access - Dbi2: if.." line.long 0x4 "SHADOW_READI_TIME_REPORTING2_OFF,Shadow Register Readiness Time Reporting 2. For a description of this standard PCIe register. see the PCI Express Specification." hexmask.long.byte 0x4 24.--31. 1. "RSVDP_24,Reserved for future use." hexmask.long.word 0x4 12.--23. 1. "D3HOT_D0_TIME,Shadow D3hot to D0 Time in the shadow register. For a description of this standard PCIe register field see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access - Dbi: No access - Dbi2:.." hexmask.long.word 0x4 0.--11. 1. "FLR_TIME,Shadow FLR Time in the shadow register. For a description of this standard PCIe register field see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access - Dbi: No access - Dbi2: if.." tree.end tree "PF0_FRSQ_CAP (PF FRSQ Capability Structure)" group.long (0x0+0x2E8)++0xB line.long 0x0 "FRSQ_EXT_CAP_HDR_OFF,FRS Queuing Extended Capability Header. For a description of this standard PCIe register. see the PCI Express Specification." hexmask.long.word 0x0 20.--31. 1. "FRSQ_NEXT_OFFSET,Next Capability Offset. For a description of this standard PCIe register field see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then.." hexmask.long.byte 0x0 16.--19. 1. "FRSQ_CAP_VERSION,Capability Version. For a description of this standard PCIe register field see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky).." hexmask.long.word 0x0 0.--15. 1. "FRSQ_EXT_CAP_ID,PCI Express Extended Capability ID. For a description of this standard PCIe register field see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then.." line.long 0x4 "FRSQ_CAP_OFF,FRS Queuing Capability Register. For a description of this standard PCIe register. see the PCI Express Specification." hexmask.long.word 0x4 21.--31. 1. "RSVDP_21,Reserved for future use." hexmask.long.byte 0x4 16.--20. 1. "FRS_INT_MESSAGE_NUMBER,FRS Interrupt Message Number. For a description of this standard PCIe register field see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1).." hexmask.long.byte 0x4 12.--15. 1. "RSVDP_12,Reserved for future use." hexmask.long.word 0x4 0.--11. 1. "FRSQ_MAX_DEPTH,FRS Queue Max Depth. For a description of this standard PCIe register field see the PCI Express Specification." line.long 0x8 "FRSQ_CONTROL_FRSQ_STATUS_OFF,FRS Queuing Status and Control Register. For a description of this standard PCIe register. see the PCI Express Specification." hexmask.long.word 0x8 17.--31. 1. "RSVDP_17,Reserved for future use." bitfld.long 0x8 16. "FRS_INTERRUPT_ENABLE,FRS Interrupt Enable. For a description of this standard PCIe register field see the PCI Express Specification." "0,1" hexmask.long.word 0x8 2.--15. 1. "RSVDP_2,Reserved for future use." bitfld.long 0x8 1. "FRS_MESSAGE_OVERFLOW,FRS Message Overflow. For a description of this standard PCIe register field see the PCI Express Specification." "0,1" newline bitfld.long 0x8 0. "FRS_MESSAGE_RECEIVED,FRS Message Received. For a description of this standard PCIe register field see the PCI Express Specification." "0,1" rgroup.long (0xC+0x2E8)++0x3 line.long 0x0 "FRS_MESSAGE_QUEUE_OFF,FRS Message Queue Register. For a description of this standard PCIe register. see the PCI Express Specification." hexmask.long.word 0x0 20.--31. 1. "FRS_MESSAGE_QUE_DEPTH,FRS Message Queue Depth. For a description of this standard PCIe register field see the PCI Express Specification." hexmask.long.byte 0x0 16.--19. 1. "FRS_MESSAGE_QUE_REASON,FRS Message Queue Reason. For a description of this standard PCIe register field see the PCI Express Specification." hexmask.long.word 0x0 0.--15. 1. "FRS_MESSAGE_QUE_FUNC_ID,FRS Message Queue Function ID. For a description of this standard PCIe register field see the PCI Express Specification." tree.end tree "PF0_PTM_CAP (PF PTM Capability Structure)" group.long (0x0+0x40C)++0xB line.long 0x0 "PTM_EXT_CAP_HDR_OFF,Precision Time Measurement Capability Header. For a description of this standard PCIe register. see the PCI Express Specification." hexmask.long.word 0x0 20.--31. 1. "PTM_NEXT_OFFSET,Precision Time Measurement PCI Express Extended Capability Next Offset. For a description of this standard PCIe register see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access. -.." hexmask.long.byte 0x0 16.--19. 1. "PTM_CAP_VERSION,Precision Time Measurement PCI Express Extended Capability Version. For a description of this standard PCIe register see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi:.." hexmask.long.word 0x0 0.--15. 1. "PTM_CAP_ID,Precision Time Measurement PCI Express Extended Capability ID. For a description of this standard PCIe register see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if.." line.long 0x4 "PTM_CAP_OFF,PTM Capability Register. For a description of this standard PCIe register. see the PCI Express Specification." hexmask.long.word 0x4 16.--31. 1. "RSVDP_16,Reserved for future use." hexmask.long.byte 0x4 8.--15. 1. "PTM_CLK_GRAN,PTM Local Clock Granularity. For a description of this standard PCIe register see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky).." hexmask.long.byte 0x4 3.--7. 1. "RSVDP_3,Reserved for future use." bitfld.long 0x4 2. "PTM_ROOT_CAPABLE,PTM Root Capable. For a description of this standard PCIe register see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else.." "0,1" bitfld.long 0x4 1. "PTM_RES_CAPABLE,PTM Responder Capable. For a description of this standard PCIe register see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else.." "0,1" newline bitfld.long 0x4 0. "PTM_REQ_CAPABLE,PTM Requester Capable. For a description of this standard PCIe register see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else.." "0,1" line.long 0x8 "PTM_CONTROL_OFF,PTM Control Register. For a description of this standard PCIe register. see the PCI Express Specification." hexmask.long.word 0x8 16.--31. 1. "RSVDP_16,Reserved for future use." hexmask.long.byte 0x8 8.--15. 1. "EFF_GRAN,PTM Effective Granularity. For a description of this standard PCIe register see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: HWINIT" hexmask.long.byte 0x8 2.--7. 1. "RSVDP_2,Reserved for future use." rbitfld.long 0x8 1. "ROOT_SELECT,PTM Root Select. When set this Time Source is the PTM Root. For a description of this standard PCIe register see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: HWINIT" "0,1" bitfld.long 0x8 0. "PTM_ENABLE,PTM Enable. When set this function is permitted to participate in the PTM mechanism. For a description of this standard PCIe register see the PCI Express Specification." "0,1" tree.end tree "PF0_PTM_RES_CAP (PF PTM Responder Capability Structure (VSEC))" group.long (0x0+0x418)++0xB line.long 0x0 "PTM_RES_CAP_HDR_OFF,Precision Time Measurement Responder Capability Header (VSEC). For more details. see the PTM section in the Databook." hexmask.long.word 0x0 20.--31. 1. "PTM_RES_EXT_CAP_NEXT_OFFS,Precision Time Measurement Responder VSEC Next Pointer. For more details see the PTM section in the Databook. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then.." hexmask.long.byte 0x0 16.--19. 1. "PTM_RES_EXT_CAP_VER,Precision Time Measurement Responder VSEC Version. For more details see the PTM section in the Databook. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else.." hexmask.long.word 0x0 0.--15. 1. "PTM_RES_EXT_CAP_ID,Precision Time Measurement Responder VSEC ID. For more details see the PTM section in the Databook. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else.." line.long 0x4 "PTM_RES_HDR_OFF,Precision Time Measurement Responder Vendor Specific Header. For more details. see the PTM section in the Databook." hexmask.long.word 0x4 20.--31. 1. "PTM_RES_VSEC_LENGTH,PTM Responder VSEC Length. For more details see the PTM section in the Databook. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This.." hexmask.long.byte 0x4 16.--19. 1. "PTM_RES_VSEC_REV,PTM Responder VSEC Revision. For more details see the PTM section in the Databook. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This.." hexmask.long.word 0x4 0.--15. 1. "PTM_RES_VSEC_ID,PTM Responder VSEC ID. For more details see the PTM section in the Databook. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register.." line.long 0x8 "PTM_RES_CONTROL_OFF,PTM Responder Control Register. For more details. see the PTM section in the Databook." hexmask.long 0x8 2.--31. 1. "RSVDP_2,Reserved for future use." bitfld.long 0x8 1. "PTM_RES_PDEL_BYTE_REV,PTM Requester Propagation Delay Byte Reversal - Reverse the order of bytes in the PTM Propagation Delay data word of the PTM ResponseD Message for compatibility with previous revisions. For more details see the PTM section in the.." "0,1" bitfld.long 0x8 0. "PTM_RES_CCONTEXT_VALID,PTM Responder Control Context Valid - PTM Local Timing is valid. This bit is set over the DBI. A speed change or aux_clk_active will set this bit low. For more details see the PTM section in the Databook. Note: The access.." "0,1" rgroup.long (0xC+0x418)++0x3 line.long 0x0 "PTM_RES_STATUS_OFF,PTM Responder Status Register. For more details. see the PTM section in the Databook." hexmask.long 0x0 2.--31. 1. "RSVDP_2,Reserved for future use." bitfld.long 0x0 1. "PTM_RES_REQUEST_RECEIVED,PTM 1st Request Received - PTM Responder has received the first PTM Request Message. Upon receipt of a second PTM Request Message a ResponseD message with timing information will be sent from the Responder if the context is.." "0,1" bitfld.long 0x0 0. "PTM_RES_CONTEXT_VALID,PTM Responder Status Context Valid - PTM Local Timing Context is Valid. Value set from upstream port Requester in a Switch. Shadows the same in the control register in all other products. For more details see the PTM section in the.." "0,1" group.long (0x10+0x418)++0x7 line.long 0x0 "PTM_RES_LOCAL_LSB_OFF,PTM Responder Local Clock LSB. For more details. see the PTM section in the Databook." hexmask.long 0x0 0.--31. 1. "PTM_RES_LOCAL_LSB,PTM Responder Local Clock LSB - Lower 32 bits of local timer value. For more details see the PTM section in the Databook. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then.." line.long 0x4 "PTM_RES_LOCAL_MSB_OFF,PTM Responder Local Clock MSB. For more details. see the PTM section in the Databook." hexmask.long 0x4 0.--31. 1. "PTM_RES_LOCAL_MSB,PTM Responder Local Clock MSB - Upper 32 bits of local timer value. For more details see the PTM section in the Databook. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then.." rgroup.long (0x18+0x418)++0x1F line.long 0x0 "PTM_RES_T2_LSB_OFF,PTM Responder T2 Timestamp LSB. For more details. see the PTM section in the Databook." hexmask.long 0x0 0.--31. 1. "PTM_RES_T2_LSB,PTM Responder T2 Timestamp LSB - Lower 32 bits of the T2 Timestamp value. For more details see the PTM section in the Databook. Note: This register field is sticky." line.long 0x4 "PTM_RES_T2_MSB_OFF,PTM Responder T2 Timestamp MSB. For more details. see the PTM section in the Databook." hexmask.long 0x4 0.--31. 1. "PTM_RES_T2_MSB,PTM Responder T2 Timestamp MSB - Upper 32 bits of the T2 Timestamp value. For more details see the PTM section in the Databook. Note: This register field is sticky." line.long 0x8 "PTM_RES_T2P_LSB_OFF,PTM Responder T2 Previous Timestamp LSB. For more details. see the PTM section in the Databook." hexmask.long 0x8 0.--31. 1. "PTM_RES_T2P_LSB,PTM Responder T2 Previous Timestamp LSB - Lower 32 bits of the previously stored T2 Timestamp value. For more details see the PTM section in the Databook. Note: This register field is sticky." line.long 0xC "PTM_RES_T2P_MSB_OFF,PTM Responder T2 Previous Timestamp MSB. For more details. see the PTM section in the Databook." hexmask.long 0xC 0.--31. 1. "PTM_RES_T2P_MSB,PTM Responder T2 Previous Timestamp MSB - Upper 32 bits of the previously stored T2 Timestamp value. For more details see the PTM section in the Databook. Note: This register field is sticky." line.long 0x10 "PTM_RES_T3_LSB_OFF,PTM Responder T3 Timestamp LSB. For more details. see the PTM section in the Databook." hexmask.long 0x10 0.--31. 1. "PTM_RES_T3_LSB,PTM Responder T3 Timestamp LSB - Lower 32 bits of the T3 Timestamp value. For more details see the PTM section in the Databook. Note: This register field is sticky." line.long 0x14 "PTM_RES_T3_MSB_OFF,PTM Responder T3 Timestamp MSB. For more details. see the PTM section in the Databook." hexmask.long 0x14 0.--31. 1. "PTM_RES_T3_MSB,PTM Responder T3 Timestamp MSB - Upper 32 bits of the T2 Timestamp value. For more details see the PTM section in the Databook. Note: This register field is sticky." line.long 0x18 "PTM_RES_T3P_LSB_OFF,PTM Responder T3 Previous Timestamp LSB. For more details. see the PTM section in the Databook." hexmask.long 0x18 0.--31. 1. "PTM_RES_T3P_LSB,PTM Responder T3 Previous Timestamp LSB - Lower 32 bits of the previously stored T3 Timestamp value. For more details see the PTM section in the Databook. Note: This register field is sticky." line.long 0x1C "PTM_RES_T3P_MSB_OFF,PTM Responder T3 Previous Timestamp MSB. For more details. see the PTM section in the Databook." hexmask.long 0x1C 0.--31. 1. "PTM_RES_T3P_MSB,PTM Responder T3 Previous Timestamp MSB - Upper 32 bits of the previously stored T3 Timestamp value. For more details see the PTM section in the Databook. Note: This register field is sticky." group.long (0x38+0x418)++0x7 line.long 0x0 "PTM_RES_TX_LATENCY_OFF,PTM Responder TX Latency. For more details. see the PTM section in the Databook." hexmask.long.tbyte 0x0 12.--31. 1. "RSVDP_12,Reserved for future use." hexmask.long.word 0x0 0.--11. 1. "PTM_RES_TX_LATENCY,PTM Responder TX Latency - Responder Transmit path latency (12 bit wide). For more details see the PTM section in the Databook. Note: This register field is sticky." line.long 0x4 "PTM_RES_RX_LATENCY_OFF,PTM Responder RX Latency. For more details. see the PTM section in the Databook." hexmask.long.tbyte 0x4 12.--31. 1. "RSVDP_12,Reserved for future use." hexmask.long.word 0x4 0.--11. 1. "PTM_RES_RX_LATENCY,PTM Responder RX Latency - Responder Receive path latency (12 bit wide). For more details see the PTM section in the Databook. Note: This register field is sticky." rgroup.long (0x40+0x418)++0x3 line.long 0x0 "PTM_RES_NOM_CLOCK_T_OFF,PTM Responder Nominal Clock Period. For more details. see the PTM section in the Databook." hexmask.long.byte 0x0 24.--31. 1. "RSVDP_24,Reserved for future use." hexmask.long.byte 0x0 16.--23. 1. "PTM_RES_NOM_CLOCK_T_INT,PTM Responder Nominal Clock Period Integral - Integral part of the nominal PTM local clock period in nanoseconds. For more details see the PTM section in the Databook. Note: This register field is sticky." hexmask.long.word 0x0 0.--15. 1. "PTM_RES_NOM_CLOCK_T_FRAC,PTM Responder Nominal Clock Period Fractional - Fractional part of the nominal PTM local clock period. LSB is 1/(2^16) nanoseconds. For more details see the PTM section in the Databook. Note: This register field is sticky." group.long (0x44+0x418)++0x3 line.long 0x0 "PTM_RES_SCALED_CLOCK_T_OFF,PTM Responder Scaled Clock Period. For more details. see the PTM section in the Databook." bitfld.long 0x0 31. "PTM_RES_SCALED_CLOCK_T_EN,PTM Responder Scaled Clock Period Enable - Use the programmed scaled PTM clock period rather than the nominal values. This bit is cleared when the core_clk rate starts to change and can only be set when the clock period change.." "0,1" hexmask.long.byte 0x0 24.--30. 1. "RSVDP_24,Reserved for future use." hexmask.long.byte 0x0 16.--23. 1. "PTM_RES_SCALED_CLOCK_T_INT,PTM Responder Scaled Clock Period Integral - Integral part of the nominal PTM local clock period in nanoseconds. For more details see the PTM section in the Databook. Note: This register field is sticky." newline hexmask.long.word 0x0 0.--15. 1. "PTM_RES_SCALED_CLOCK_T_FRAC,PTM Responder Scaled Clock Period Fractional - Fractional part of the nominal PTM local clock period. LSB is 1/(2^16) nanoseconds. For more details see the PTM section in the Databook. Note: This register field is sticky." tree.end tree "PF0_PM_CAP (PF PCI Power Management Capability Structure)" group.long (0x0+0x40)++0x7 line.long 0x0 "CAP_ID_NXT_PTR_REG,Power Management Capabilities Register." hexmask.long.byte 0x0 27.--31. 1. "PME_SUPPORT,PME_Support. This 5-bit field indicates the power states in which the function may generate a PME and/or forward PME messages. A value of 0b for any bit indicates that the function is not capable of asserting PME while in that power state. -.." bitfld.long 0x0 26. "D2_SUPPORT,D2_Support. If this bit is set this function supports the D2 Power Management state. Functions that do not support D2 must always return a value of 0b for this bit. Note: The access attributes of this field are as follows: - Wire: No access." "0,1" bitfld.long 0x0 25. "D1_SUPPORT,D1_Support. If this bit is set this function supports the D1 Power Management state. Functions that do not support D1 must always return a value of 0b for this bit. Note: The access attributes of this field are as follows: - Wire: No access." "0,1" bitfld.long 0x0 22.--24. "AUX_CURR,Aux_Current. This 3 bit field reports the Vaux auxiliary current requirements for the function. If this function implements the Data Register the controller hardwires this field to 000b. If PME_Support is 0 xxxxb (PME assertion from D3cold is.." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 21. "DSI,Device Specific Initialization. The DSI bit indicates whether special initialization of this function is required. When set indicates that the function requires a device specific initialization sequence following a transition to the D0uninitialized.." "0,1" bitfld.long 0x0 20. "PME_IMM_READI_RETURN_DO,Immediate_Readiness_on_Return_to_D0. - If this bit is a '1' this function is guaranteed to be ready to successfully complete valid accesses immediately after being set to D0. These accesses include configuration cycles and if.." "0,1" rbitfld.long 0x0 19. "PME_CLK,PME Clock. Does not apply to PCI Express the controller hardwires it to 0b. Note: This register field is sticky." "0,1" bitfld.long 0x0 16.--18. "PM_SPEC_VER,Version. This field provides the Power Management specification version. The controller hardwires this field to 011b for functions compliant to PCI Express Base Specification Revision 4.0 Version 1.0>. Note: The access attributes of this.." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x0 8.--15. 1. "PM_NEXT_POINTER,Next Capability Pointer. This field provides an offset into the function's configuration space pointing to the location of next item in the capabilities list. If there are no additional items in the capabilities list this field is set to.." hexmask.long.byte 0x0 0.--7. 1. "PM_CAP_ID,Capability ID. This field returns 01h to indicate that this is the PCI Power Management Capability. Each function may have only one item in its capability list with Capability ID set to 01h." line.long 0x4 "CON_STATUS_REG,Power Management Control and Status Register. This register is used to manage the PCI function's power management state as well as to enable/monitor PMEs." hexmask.long.byte 0x4 24.--31. 1. "DATA_REG_ADD_INFO,Data. This field is used to report the state dependent data requested by the Data_Select field. The value of this field is scaled by the value reported by the Data_Scale field." rbitfld.long 0x4 23. "BUS_PWR_CLK_CON_EN,Bus Power/Clock Control Enable. For a description of this standard PCIe register field see the PCI Express Base Specification." "0,1" rbitfld.long 0x4 22. "B2_B3_SUPPORT,B2B3 Support for D3hot. For a description of this standard PCIe register field see the PCI Express Base Specification." "0,1" hexmask.long.byte 0x4 16.--21. 1. "RSVDP_16,Reserved for future use." newline bitfld.long 0x4 15. "PME_STATUS,PME_Status. This bit is set when the function normally generates a PME signal. The value of this bit is not affected by the value of the PME_En bit. If PME_Support bit 31 of the Power Management Capabilities register is clear this bit is.." "0,1" rbitfld.long 0x4 13.--14. "DATA_SCALE,Data_Scale. This field indicates the scaling factor to be used when interpreting the value of the Data field. The value and meaning of this field varies depending on which data value has been selected by the Data_Select field. For more details.." "0,1,2,3" hexmask.long.byte 0x4 9.--12. 1. "DATA_SELECT,Data_Select. This 4-bit field is used to select which data is to be reported through the Data and Data_Scale field. If the Data field is not implemented this field must be hardwired to 0000b." bitfld.long 0x4 8. "PME_ENABLE,PME_En. - When set the function is permitted to generate a PME. - When clear the function is not permitted to generate a PME. If PME_Support is 1 xxxxb (PME generation from D3cold) or the function consumes Aux power and Aux power is.." "0,1" newline hexmask.long.byte 0x4 4.--7. 1. "RSVDP_4,Reserved for future use." bitfld.long 0x4 3. "NO_SOFT_RST,No_Soft_Reset. This bit indicates the state of the function after writing the PowerState field to transition the function from D3hot to D0. - When set this transition preserves internal function state. The function is in D0Active and no.." "0,1" rbitfld.long 0x4 2. "RSVDP_2,Reserved for future use." "0,1" bitfld.long 0x4 0.--1. "POWER_STATE,PowerState. This 2-bit field is used both to determine the current power state of a function and to set the function into a new power state. The definition of the field values is given below. You can write to this register; however the.." "D0,D1,D2,D3hot" tree.end tree "PF0_PCIE_CAP (PF PCI Express Capability Structure)" group.long (0x0+0x70)++0x33 line.long 0x0 "PCIE_CAP_ID_PCIE_NEXT_CAP_PTR_PCIE_CAP_REG,PCI Express Capabilities. ID. Next Pointer Register." rbitfld.long 0x0 31. "RSVDP_31,Reserved for future use." "0,1" rbitfld.long 0x0 30. "RSVD,Reserved." "0,1" newline hexmask.long.byte 0x0 25.--29. 1. "PCIE_INT_MSG_NUM,PCIE Interrupt Message Number. For a description of this standard PCIe register field see the PCI Express Base Specification. Interrupt Message Number. This field indicates which MSI/MSI-X vector is used for the interrupt message.." bitfld.long 0x0 24. "PCIE_SLOT_IMP,Slot Implemented. When set this bit indicates that the Link associated with this Port is connected to a slot (as compared to being connected to a system-integrated device or being disabled). This bit is valid for Downstream Ports. This bit.." "0,1" newline hexmask.long.byte 0x0 20.--23. 1. "PCIE_DEV_PORT_TYPE,Device/Port Type. Indicates the specific type of this PCI Express function. Note: Different functions in a Multi-Function Device can generally be of different types. Defined encodings for functions that implement a Type 00h PCI.." hexmask.long.byte 0x0 16.--19. 1. "PCIE_CAP_REG,Capability Version. Indicates PCI-SIG defined PCI Express Capability structure version number. A version of the specification that changes the PCI Express Capability structure in a way that is not otherwise identifiable (for example through.." newline hexmask.long.byte 0x0 8.--15. 1. "PCIE_CAP_NEXT_PTR,Next Capability Pointer. This field contains the offset to the next PCI Capability structure or 00h if no other items exist in the linked list of Capabilities. Note: The access attributes of this field are as follows: - Wire: No access." hexmask.long.byte 0x0 0.--7. 1. "PCIE_CAP_ID,Capability ID. Indicates the PCI Express Capability structure. This field must return a Capability ID of 10h indicating that this is a PCI Express Capability structure." line.long 0x4 "DEVICE_CAPABILITIES_REG,Device Capabilities Register. The Device Capabilities register identifies PCI Express device function specific capabilities." hexmask.long.word 0x4 16.--31. 1. "RSVDP_16,Reserved for future use." bitfld.long 0x4 15. "PCIE_CAP_ROLE_BASED_ERR_REPORT,Role-Based Error Reporting. When set this bit indicates that the function implements the functionality originally defined in the Error Reporting ECN for PCI Express Base Specification Revision 1.0a and later incorporated.." "0,1" newline hexmask.long.word 0x4 6.--14. 1. "RSVDP_6,Reserved for future use." bitfld.long 0x4 5. "PCIE_CAP_EXT_TAG_SUPP,Extended Tag Field Supported. This bit in combination with the 10-Bit Tag Requester Supported bit in the Device Capabilities 2 register indicates the maximum supported size of the Tag field as a Requester. This bit must be set if.." "0,1" newline bitfld.long 0x4 3.--4. "PCIE_CAP_PHANTOM_FUNC_SUPPORT,Phantom Functions Supported. This field indicates the support for use of unclaimed function numbers to extend the number of outstanding transactions allowed by logically combining unclaimed function numbers (called Phantom.." "0,1,2,3" bitfld.long 0x4 0.--2. "PCIE_CAP_MAX_PAYLOAD_SIZE,Max_Payload_Size Supported. This field indicates the maximum payload size that the function can support for TLPs. Defined encodings are: - 000b: 128 bytes max payload size - 001b: 256 bytes max payload size - 010b: 512 bytes max.." "0,1,2,3,4,5,6,7" line.long 0x8 "DEVICE_CONTROL_DEVICE_STATUS,Device Control and Device Status Register. This register controls PCI Express device specific parameters and provides information about PCI Express device (function) specific parameters." hexmask.long.word 0x8 22.--31. 1. "RSVDP_22,Reserved for future use." rbitfld.long 0x8 21. "PCIE_CAP_TRANS_PENDING,Transactions Pending. Endpoints: When set this bit indicates that the function has issued Non-Posted Requests that have not been completed. A Function reports this bit cleared only when all outstanding Non-Posted Requests have.." "0,1" newline rbitfld.long 0x8 20. "PCIE_CAP_AUX_POWER_DETECTED,AUX Power Detected. Functions that require Aux power report this bit as set if Aux power is detected by the function. This bit is derived by sampling the sys_aux_pwr_det input." "0,1" bitfld.long 0x8 19. "PCIE_CAP_UNSUPPORTED_REQ_DETECTED,Unsupported Request Detected. This bit indicates that the function received an Unsupported Request. Errors are logged in this register regardless of whether error reporting is enabled or not in the Device Control.." "0,1" newline bitfld.long 0x8 18. "PCIE_CAP_FATAL_ERR_DETECTED,Fatal Error Detected. This bit indicates status of Fatal errors detected. Errors are logged in this register regardless of whether error reporting is enabled or not in the Device Control register. For a Multi-Function device.." "0,1" bitfld.long 0x8 17. "PCIE_CAP_NON_FATAL_ERR_DETECTED,Non-Fatal Error Detected. This bit indicates status of Non-fatal errors detected. Errors are logged in this register regardless of whether error reporting is enabled or not in the Device Control register. For a.." "0,1" newline bitfld.long 0x8 16. "PCIE_CAP_CORR_ERR_DETECTED,Correctable Error Detected. This bit indicates status of correctable errors detected. Errors are logged in this register regardless of whether error reporting is enabled or not in the Device Control register. For a.." "0,1" bitfld.long 0x8 15. "PCIE_CAP_INITIATE_FLR,Initiate Function Level Reset (applicable to Endpoints with Function Level Reset Capability set to 1b). A write of 1b initiates Function Level Reset to the Function. The value read by software from this bit is always 0b." "0,1" newline bitfld.long 0x8 12.--14. "PCIE_CAP_MAX_READ_REQ_SIZE,Max_Read_Request_Size. This field sets the maximum Read Request size for the function as a Requester. The function must not generate Read Requests with a size exceeding the set value. Defined encodings for this field are: -.." "0,1,2,3,4,5,6,7" rbitfld.long 0x8 11. "PCIE_CAP_EN_NO_SNOOP,Enable No Snoop. If this bit is set the function is permitted to Set the No Snoop bit in the Requester Attributes of transactions it initiates that do not require hardware enforced cache coherency (see section 2.2.6.5 in PCI Express.." "0,1" newline bitfld.long 0x8 10. "PCIE_CAP_AUX_POWER_PM_EN,Aux Power PM Enable. This bit is derived by sampling the sys_aux_pwr_det input. When set this bit enables a function to draw Aux power independent of PME Aux power. Functions that require Aux power on legacy operating systems.." "0,1" rbitfld.long 0x8 9. "PCIE_CAP_PHANTOM_FUNC_EN,Phantom Functions Enable. This bit in combination with the 10-Bit Tag Requester Enable bit in the Device Control 2 register determines how many Tag field bits a Requester is permitted to use. When the 10-Bit Tag Requester.." "0,1" newline rbitfld.long 0x8 8. "PCIE_CAP_EXT_TAG_EN,Extended Tag Field Enable. This bit in combination with the 10-Bit Tag Requester Enable bit in the Device Control 2 register determines how many Tag field bits a Requester is permitted to use. When the 10-Bit Tag Requester Enable.." "0,1" bitfld.long 0x8 5.--7. "PCIE_CAP_MAX_PAYLOAD_SIZE_CS,Max_Payload_Size. This field sets maximum TLP payload size for the Function. As a Receiver the Function must handle TLPs as large as the set value. As a Transmitter the Function must not generate TLPs exceeding the set.." "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 4. "PCIE_CAP_EN_REL_ORDER,Enable Relaxed Ordering. If this bit is set the function is permitted to set the Relaxed Ordering bit in the Attributes field of transactions it initiates that do not require strong write ordering (for more details see section.." "0,1" bitfld.long 0x8 3. "PCIE_CAP_UNSUPPORT_REQ_REP_EN,Unsupported Request Reporting Enable. This bit in conjunction with other bits controls the signaling of Unsupported Request Errors by sending error Messages (for more details see section 6.2.5 and section 6.2.6 of PCI.." "0,1" newline bitfld.long 0x8 2. "PCIE_CAP_FATAL_ERR_REPORT_EN,Fatal Error Reporting Enable. This bit in conjunction with other bits controls sending ERR_FATAL Messages (for more details see section 6.2.5 and section 6.2.6 of of PCI Express Base Specification). For a Multi-Function.." "0,1" bitfld.long 0x8 1. "PCIE_CAP_NON_FATAL_ERR_REPORT_EN,Non-Fatal Error Reporting Enable. This bit in conjunction with other bits controls sending ERR_NONFATAL Messages (for more details see section 6.2.5 and Section 6.2.6 of PCI Express Base Specification). For a.." "0,1" newline bitfld.long 0x8 0. "PCIE_CAP_CORR_ERR_REPORT_EN,Correctable Error Reporting Enable. This bit in conjunction with other bits controls sending ERR_COR Messages (for more details see section 6.2.5 section 6.2.6 and section 6.2.10.2 of PCI Express Base Specification). For.." "0,1" line.long 0xC "LINK_CAPABILITIES_REG,Link Capabilities Register. The Link Capabilities register identifies PCI Express Link specific capabilities." hexmask.long.byte 0xC 24.--31. 1. "PCIE_CAP_PORT_NUM,Port Number. This field indicates the PCI Express Port number for the given PCI Express Link. Multi-Function Devices associated with an Upstream Port must report the same value in this field for all functions. Note: The access.." rbitfld.long 0xC 23. "RSVDP_23,Reserved for future use." "0,1" newline bitfld.long 0xC 22. "PCIE_CAP_ASPM_OPT_COMPLIANCE,ASPM Optionality Compliance. This bit must be set to 1b in all functions. Components implemented against certain earlier versions of this specification will have this bit set to 0b. Software is permitted to use the value of.." "0,1" bitfld.long 0xC 21. "PCIE_CAP_LINK_BW_NOT_CAP,Link Bandwidth Notification Capability. A value of 1b indicates support for the Link Bandwidth Notification status and interrupt mechanisms. This capability is required for all Root Ports and Switch Downstream Ports supporting.." "0,1" newline rbitfld.long 0xC 20. "PCIE_CAP_DLL_ACTIVE_REP_CAP,Data Link Layer Link Active Reporting Capable. For a Downstream Port the controller hardwires this bit to 1b if the component supports the optional capability of reporting the DL_Active state of the Data Link Control and.." "0,1" bitfld.long 0xC 19. "PCIE_CAP_SURPRISE_DOWN_ERR_REP_CAP,Surprise Down Error Reporting Capable. For a Downstream Port this bit must be set if the component supports the optional capability of detecting and reporting a Surprise Down error condition. For Upstream Ports and.." "0,1" newline rbitfld.long 0xC 18. "PCIE_CAP_CLOCK_POWER_MAN,Clock Power Management. For Upstream Ports a value of 1b in this bit indicates that the component tolerates the removal of any reference clock(s) via the 'clock request' (CLKREQ#) mechanism when the Link is in the L1 and L2/L3.." "0,1" bitfld.long 0xC 15.--17. "PCIE_CAP_L1_EXIT_LATENCY,L1 Exit Latency. This field indicates the L1 exit latency for the given PCI Express Link. The value reported indicates the length of time this Port requires to complete transition from ASPM L1 to L0. If ASPM L1 is not supported.." "0,1,2,3,4,5,6,7" newline bitfld.long 0xC 12.--14. "PCIE_CAP_L0S_EXIT_LATENCY,L0s Exit Latency. This field indicates the L0s exit latency for the given PCI Express Link. The value reported indicates the length of time this Port requires to complete transition from L0s to L0. If L0s is not supported the.." "0,1,2,3,4,5,6,7" bitfld.long 0xC 10.--11. "PCIE_CAP_ACTIVE_STATE_LINK_PM_SUPPORT,Active State Power Management (ASPM) Support. This field indicates the level of ASPM supported on the given PCI Express Link. For more details on ASPM support requirements see section 5.4.1 of PCI Express Base.." "0,1,2,3" newline hexmask.long.byte 0xC 4.--9. 1. "PCIE_CAP_MAX_LINK_WIDTH,Maximum Link Width. This field indicates the maximum Link width (xN - corresponding to N Lanes) implemented by the component. This value is permitted to exceed the number of Lanes routed to the slot (Downstream Port) adapter.." hexmask.long.byte 0xC 0.--3. 1. "PCIE_CAP_MAX_LINK_SPEED,Max Link Speed. This field indicates the maximum Link speed of the associated Port. The encoded value specifies a bit location in the Supported Link Speeds Vector (in the Link Capabilities 2 register) that corresponds to the.." line.long 0x10 "LINK_CONTROL_LINK_STATUS_REG,Link Control and Link Status Register. This register controls and provides information about PCI Express Link specific parameters." bitfld.long 0x10 31. "PCIE_CAP_LINK_AUTO_BW_STATUS,Link Autonomous Bandwidth Status. This bit is set by hardware to indicate that hardware has autonomously changed Link speed or width without the Port transitioning through DL_Down status for reasons other than to attempt to.." "0,1" bitfld.long 0x10 30. "PCIE_CAP_LINK_BW_MAN_STATUS,Link Bandwidth Management Status. This bit is set by hardware to indicate that either of the following has occurred without the Port transitioning through DL_Down status: - A Link retraining has completed following a write of.." "0,1" newline rbitfld.long 0x10 29. "PCIE_CAP_DLL_ACTIVE,Data Link Layer Link Active. This bit indicates the status of the Data Link Control and Management State Machine. It returns a 1b to indicate the DL_Active state 0b otherwise. This bit must be implemented if the Data Link Layer Link.." "0,1" bitfld.long 0x10 28. "PCIE_CAP_SLOT_CLK_CONFIG,Slot Clock Configuration. This bit indicates that the component uses the same physical reference clock that the platform provides on the connector. If the device uses an independent clock irrespective of the presence of a.." "0,1" newline rbitfld.long 0x10 27. "PCIE_CAP_LINK_TRAINING,Link Training. This read-only bit indicates that the Physical Layer LTSSM is in the Configuration or Recovery state or that 1b was written to the Retrain Link bit but Link training has not yet begun. Hardware clears this bit when.." "0,1" rbitfld.long 0x10 26. "RSVDP_26,Reserved for future use." "0,1" newline hexmask.long.byte 0x10 20.--25. 1. "PCIE_CAP_NEGO_LINK_WIDTH,Negotiated Link Width. This field indicates the negotiated width of the given PCI Express Link. Defined encodings are: -00 0001b: x1 -00 0010b: x2 -00 0100b: x4 -00 1000b: x8 -00 1100b: x12 -01 0000b: x16 -10 0000b: x32 All other.." hexmask.long.byte 0x10 16.--19. 1. "PCIE_CAP_LINK_SPEED,Current Link Speed. This field indicates the negotiated Link speed of the given PCI Express Link. The encoded value specifies a bit location in the Supported Link Speeds Vector (in the Link Capabilities 2 register) that corresponds to.." newline bitfld.long 0x10 14.--15. "PCIE_CAP_DRS_SIGNALING_CONTROL,DRS Signaling Control. Indicates the mechanism used to report reception of a DRS message. Must be implemented for Downstream Ports with the DRS Supported bit Set in the Link Capabilities 2 Register. Encodings are: - 00b:.." "0,1,2,3" rbitfld.long 0x10 12.--13. "RSVDP_12,Reserved for future use." "0,1,2,3" newline bitfld.long 0x10 11. "PCIE_CAP_LINK_AUTO_BW_INT_EN,Link Autonomous Bandwidth Management Interrupt Enable. When set this bit enables the generation of an interrupt to indicate that the Link Autonomous Bandwidth Status bit has been set. The write value is gated with the.." "0,1" bitfld.long 0x10 10. "PCIE_CAP_LINK_BW_MAN_INT_EN,Link Bandwidth Management Interrupt Enable. When set this bit enables the generation of an interrupt to indicate that the Link Bandwidth Management Status bit has been set. The write value is gated with the.." "0,1" newline bitfld.long 0x10 9. "PCIE_CAP_HW_AUTO_WIDTH_DISABLE,Hardware Autonomous Width Disable. When set this bit disables hardware from changing the Link width for reasons other than attempting to correct unreliable Link operation by reducing Link width. For a Multi-Function Device.." "0,1" bitfld.long 0x10 8. "PCIE_CAP_EN_CLK_POWER_MAN,Enable Clock Power Management. Applicable only for Upstream Ports and with form factors that support a 'Clock Request' (CLKREQ#) mechanism this bit operates as follows: - 0b: Clock power management is disabled and device must.." "0,1" newline bitfld.long 0x10 7. "PCIE_CAP_EXTENDED_SYNCH,Extended Synch. When set this bit forces the transmission of additional Ordered Sets when exiting the L0s state (see section 4.2.4.5 of PCI Express Base Specification) and when in the Recovery state (see section 4.2.6.4.1 of PCI.." "0,1" bitfld.long 0x10 6. "PCIE_CAP_COMMON_CLK_CONFIG,Common Clock Configuration. When set this bit indicates that this component and the component at the opposite end of this Link are operating with a distributed common reference clock. A value of 0b indicates that this.." "0,1" newline bitfld.long 0x10 5. "PCIE_CAP_RETRAIN_LINK,Retrain Link. A write of 1b to this bit initiates Link retraining by directing the Physical Layer LTSSM to the Recovery state. If the LTSSM is already in Recovery or Configuration re-entering Recovery is permitted but not required." "0,1" bitfld.long 0x10 4. "PCIE_CAP_LINK_DISABLE,Link Disable. This bit disables the Link by directing the LTSSM to the Disabled state when set; this bit is Reserved on Endpoints PCI Express to PCI/PCI-X bridges and Upstream Ports of Switches. Writes to this bit are immediately.." "0,1" newline bitfld.long 0x10 3. "PCIE_CAP_RCB,Read Completion Boundary (RCB). Root Ports: Indicates the RCB value for the Root Port. Refer to section 2.3.1.1 of PCI Express Base Specification for the definition of the parameter RCB. Defined encodings are: - 0b: 64 byte - 1b: 128 byte.." "0,1" rbitfld.long 0x10 2. "RSVDP_2,Reserved for future use." "0,1" newline bitfld.long 0x10 0.--1. "PCIE_CAP_ACTIVE_STATE_LINK_PM_CONTROL,Active State Power Management (ASPM) Control. This field controls the level of ASPM enabled on the given PCI Express Link. See section 5.4.1.3 of PCI Express Base Specification for requirements on when and how to.." "0,1,2,3" line.long 0x14 "SLOT_CAPABILITIES_REG,Slot Capabilities Register. The Slot Capabilities register identifies PCI Express slot specific capabilities." hexmask.long.word 0x14 19.--31. 1. "PCIE_CAP_PHY_SLOT_NUM,Physical Slot Number. This field indicates the physical slot number attached to this Port. This field must be hardware initialized to a value that assigns a slot number that is unique within the chassis regardless of the form.." bitfld.long 0x14 18. "PCIE_CAP_NO_CMD_CPL_SUPPORT,No Command Completed Support. When set this bit indicates that this slot does not generate software notification when an issued command is completed by the Hot-Plug Controller. This bit is only permitted to be set if the.." "0,1" newline bitfld.long 0x14 17. "PCIE_CAP_ELECTROMECH_INTERLOCK,Electromechanical Interlock Present. When set this bit indicates that an Electromechanical Interlock is implemented on the chassis for this slot. Note: The access attributes of this field are as follows: - Wire: No access." "0,1" bitfld.long 0x14 15.--16. "PCIE_CAP_SLOT_POWER_LIMIT_SCALE,Slot Power Limit Scale. Specifies the scale used for the Slot Power Limit Value (for more details see Section 6.9 of PCI Express Base Specification). Range of Values: - 00b: 1.0x - 01b: 0.1x - 10b: 0.01x - 11b: 0.001x.." "0,1,2,3" newline hexmask.long.byte 0x14 7.--14. 1. "PCIE_CAP_SLOT_POWER_LIMIT_VALUE,Slot Power Limit Value. In combination with the Slot Power Limit Scale value specifies the upper limit on power supplied by the slot (for more detais see Section 6.9 of PCI Express Base Specification) or by other means.." bitfld.long 0x14 6. "PCIE_CAP_HOT_PLUG_CAPABLE,Hot-Plug Capable. When set this bit indicates that this slot is capable of supporting hot-plug operations. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then R/W else R" "0,1" newline bitfld.long 0x14 5. "PCIE_CAP_HOT_PLUG_SURPRISE,Hot-Plug Surprise. When set this bit indicates that an adapter present in this slot might be removed from the system without any prior notification. This is a form factor specific capability. This bit is an indication to the.." "0,1" bitfld.long 0x14 4. "PCIE_CAP_POWER_INDICATOR,Power Indicator Present. When set this bit indicates that a Power Indicator is electrically controlled by the chassis for this slot. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if.." "0,1" newline bitfld.long 0x14 3. "PCIE_CAP_ATTENTION_INDICATOR,Attention Indicator Present. When set this bit indicates that an Attention Indicator is electrically controlled by the chassis. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if.." "0,1" bitfld.long 0x14 2. "PCIE_CAP_MRL_SENSOR,MRL Sensor Present. When set this bit indicates that an MRL Sensor is implemented on the chassis for this slot. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then R/W else R" "0,1" newline bitfld.long 0x14 1. "PCIE_CAP_POWER_CONTROLLER,Power Controller Present. When set this bit indicates that a software programmable Power Controller is implemented for this slot/adapter (depending on form factor). Note: The access attributes of this field are as follows: -.." "0,1" bitfld.long 0x14 0. "PCIE_CAP_ATTENTION_INDICATOR_BUTTON,Attention Button Present. When set this bit indicates that an Attention Button for this slot is electrically controlled by the chassis. Note: The access attributes of this field are as follows: - Wire: No access. -.." "0,1" line.long 0x18 "SLOT_CONTROL_SLOT_STATUS,Slot Control and Status Register. This register controls and provides information about PCI Express Slot specific parameters." hexmask.long.byte 0x18 25.--31. 1. "RSVDP_25,Reserved for future use." bitfld.long 0x18 24. "PCIE_CAP_DLL_STATE_CHANGED,Data Link Layer State Changed. This bit is set when the value reported in the Data Link Layer Link Active bit of the Link Status register is changed. In response to a Data Link Layer State Changed event software must read the.." "0,1" newline rbitfld.long 0x18 23. "PCIE_CAP_ELECTROMECH_INTERLOCK_STATUS,Electromechanical Interlock Status. If an Electromechanical Interlock is implemented this bit indicates the status of the Electromechanical Interlock. Defined encodings are: - 0b: Electromechanical Interlock.." "0,1" rbitfld.long 0x18 22. "PCIE_CAP_PRESENCE_DETECT_STATE,Presence Detect State. This bit indicates the presence of an adapter in the slot reflected by the logical 'OR' of the Physical Layer in-band presence detect mechanism and if present any out-of-band presence detect.." "0,1" newline rbitfld.long 0x18 21. "PCIE_CAP_MRL_SENSOR_STATE,MRL Sensor State. This bit reports the status of the MRL sensor if implemented. Defined encodings are: - 0b: MRL Closed - 1b: MRL Open" "0,1" bitfld.long 0x18 20. "PCIE_CAP_CMD_CPLD,Command Completed. If Command Completed notification is supported (if the No Command Completed Support bit in the Slot Capabilities register is 0b) this bit is set when a hot-plug command has completed and the Hot-Plug Controller is.." "0,1" newline bitfld.long 0x18 19. "PCIE_CAP_PRESENCE_DETECTED_CHANGED,Presence Detect Changed. This bit is set when the value reported in the Presence Detect State bit is changed." "0,1" bitfld.long 0x18 18. "PCIE_CAP_MRL_SENSOR_CHANGED,MRL Sensor Changed. If an MRL sensor is implemented this bit is set when a MRL Sensor state change is detected. If an MRL sensor is not implemented this bit must not be set." "0,1" newline bitfld.long 0x18 17. "PCIE_CAP_POWER_FAULT_DETECTED,Power Fault Detected. If a Power Controller that supports power fault detection is implemented this bit issSet when the Power Controller detects a power fault at this slot. Note: Depending on hardware capability it is.." "0,1" bitfld.long 0x18 16. "PCIE_CAP_ATTENTION_BUTTON_PRESSED,Attention Button Pressed. If an Attention Button is implemented this bit is set when the attention button is pressed. If an Attention Button is not supported this bit must not be set." "0,1" newline rbitfld.long 0x18 14.--15. "RSVDP_14,Reserved for future use." "0,1,2,3" bitfld.long 0x18 12. "PCIE_CAP_DLL_STATE_CHANGED_EN,Data Link Layer State Changed Enable. If the Data Link Layer Link Active Reporting capability is 1b this bit enables software notification when Data Link Layer Link Active bit is changed. If the Data Link Layer Link Active.." "0,1" newline bitfld.long 0x18 11. "PCIE_CAP_ELECTROMECH_INTERLOCK_CTRL,Electromechanical Interlock Control. If an Electromechanical Interlock is implemented a write of 1b to this bit causes the state of the interlock to toggle. A write of 0b to this bit has no effect. A read of this bit.." "0,1" bitfld.long 0x18 10. "PCIE_CAP_POWER_CONTROLLER_CTRL,Power Controller Control. If a Power Controller is implemented this bit when written sets the power state of the slot per the defined encodings. Reads of this bit must reflect the value from the latest write even if the.." "0,1" newline bitfld.long 0x18 8.--9. "PCIE_CAP_POWER_INDICATOR_CTRL,Power Indicator Control. If a Power Indicator is implemented writes to this field set the Power Indicator to the written state. Reads of this field must reflect the value from the latest write even if the corresponding.." "0,1,2,3" bitfld.long 0x18 6.--7. "PCIE_CAP_ATTENTION_INDICATOR_CTRL,Attention Indicator Control. If an Attention Indicator is implemented writes to this field set the Attention Indicator to the written state. Reads of this field must reflect the value from the latest write even if the.." "0,1,2,3" newline bitfld.long 0x18 5. "PCIE_CAP_HOT_PLUG_INT_EN,Hot-Plug Interrupt Enable. When set this bit enables generation of an interrupt on enabled hot-plug events. If the Hot Plug Capable bit in the Slot Capabilities register is clear this bit is permitted to be read-only with a.." "0,1" bitfld.long 0x18 4. "PCIE_CAP_CMD_CPL_INT_EN,Command Completed Interrupt Enable. If Command Completed notification is supported (if the No Command Completed Support bit in the Slot Capabilities register is 0b) when set this bit enables software notification when a hot-plug.." "0,1" newline bitfld.long 0x18 3. "PCIE_CAP_PRESENCE_DETECT_CHANGE_EN,Presence Detect Changed Enable. When set this bit enables software notification on a presence detect changed event (for more details see Section 6.7.3 of PCI Express Base Specification). If the Hot-Plug Capable bit in.." "0,1" bitfld.long 0x18 2. "PCIE_CAP_MRL_SENSOR_CHANGED_EN,MRL Sensor Changed Enable. When set this bit enables software notification on a MRL sensor changed event (for more details see Section 6.7.3 of PCI Express Base Specification). If the MRL Sensor Present bit in the Slot.." "0,1" newline bitfld.long 0x18 1. "PCIE_CAP_POWER_FAULT_DETECTED_EN,Power Fault Detected Enable. When set this bit enables software notification on a power fault event (for more details see Section 6.7.3 of PCI Express Base Specification). If a Power Controller that supports power fault.." "0,1" bitfld.long 0x18 0. "PCIE_CAP_ATTENTION_BUTTON_PRESSED_EN,Attention Button Pressed Enable. When set to 1b this bit enables software notification on an attention button pressed event (for more details see Section 6.7.3 of PCI Express Base Specification). If the Attention.." "0,1" line.long 0x1C "ROOT_CONTROL_ROOT_CAPABILITIES_REG,Root Control and Capabilities Register. This register controls PCI Express Root Complex specific parameters and identifies PCI Express Root Port specific capabilities." hexmask.long.word 0x1C 17.--31. 1. "RSVDP_17,Reserved for future use." bitfld.long 0x1C 16. "PCIE_CAP_CRS_SW_VISIBILITY,CRS Software Visibility Capable. For a description of this standard PCIe register field see the PCI Express Base Specification. CRS Software Visibility. When set this bit indicates that the Root Port is capable of returning.." "0,1" newline hexmask.long.word 0x1C 5.--15. 1. "RSVDP_5,Reserved for future use." bitfld.long 0x1C 4. "PCIE_CAP_CRS_SW_VISIBILITY_EN,CRS Software Visibility Enable. When set this bit enables the Root Port to return Configuration Request Retry Status (CRS) Completion Status to software (for more details see section 2.3.1 of PCI Express Base.." "0,1" newline bitfld.long 0x1C 3. "PCIE_CAP_PME_INT_EN,PME Interrupt Enable. When set this bit enables PME interrupt generation upon receipt of a PME Message as reflected in the PME Status bit (for more details see Table 7-29 of PCI Express Base Specification). A PME interrupt is also.." "0,1" bitfld.long 0x1C 2. "PCIE_CAP_SYS_ERR_ON_FATAL_ERR_EN,System Error on Fatal Error Enable. If set this bit indicates that a System Error should be generated if a Fatal error (ERR_FATAL) is reported by any of the devices in the Hierarchy Domain associated with this Root Port.." "0,1" newline bitfld.long 0x1C 1. "PCIE_CAP_SYS_ERR_ON_NON_FATAL_ERR_EN,System Error on Non-Fatal Error Enable. If set this bit indicates that a System Error should be generated if a Non-fatal error (ERR_NONFATAL) is reported by any of the devices in the Hierarchy Domain associated with.." "0,1" bitfld.long 0x1C 0. "PCIE_CAP_SYS_ERR_ON_CORR_ERR_EN,System Error on Correctable Error Enable. If set this bit indicates that a System Error should be generated if a correctable error (ERR_COR) is reported by any of the devices in the Hierarchy Domain associated with this.." "0,1" line.long 0x20 "ROOT_STATUS_REG,Root Status Register. The Root Status register provides information about PCI Express device specific parameters." hexmask.long.word 0x20 18.--31. 1. "RSVDP_18,Reserved for future use." rbitfld.long 0x20 17. "PCIE_CAP_PME_PENDING,PME Pending. This bit indicates that another PME is pending when the PME Status bit is s et. When the PME Status bit is cleared by software; the PME is delivered by hardware by setting the PME Status bit again and updating the PME.." "0,1" newline bitfld.long 0x20 16. "PCIE_CAP_PME_STATUS,PME Status. This bit indicates that PME was asserted by the PME Requester indicated in the PME Requester ID field. Subsequent PMEs are kept pending until the status register is cleared by software by writing a 1b." "0,1" hexmask.long.word 0x20 0.--15. 1. "PCIE_CAP_PME_REQ_ID,PME Requester ID. This field indicates the PCI Requester ID of the last PME Requester. This field is only valid when the PME Status bit is set." line.long 0x24 "DEVICE_CAPABILITIES2_REG,Device Capabilities 2 Register." bitfld.long 0x24 31. "PCIE_CAP_FRS_SUPPORTED,FRS Supported. When set indicates support for the optional Function Readiness Status (FRS) capability. Must be set for all Functions that support generation or reception capabilities of FRS Messages. Must not be set by Switch.." "0,1" hexmask.long.byte 0x24 24.--30. 1. "RSVDP_24,Reserved for future use." newline bitfld.long 0x24 22.--23. "PCIE_CAP2_CFG_MAX_END2END_TLP_PRFXS,Max End-End TLP Prefixes. Indicates the maximum number of End-End TLP Prefixes supported by this Function. For more details see Section 2.2.10.2 of PCI Express Base Specification. Values are: - 01b: 1 End-End TLP.." "0,1,2,3" bitfld.long 0x24 21. "PCIE_CAP2_CFG_END2END_TLP_PRFX_SUPPORT,End-End TLP Prefix Supported. Indicates whether End-End TLP Prefix support is offered by a Function. Values are: - 0b: No Support - 1b: Support is provided to receive TLPs containing End-End TLP Prefixes. All Ports.." "0,1" newline bitfld.long 0x24 20. "PCIE_CAP2_CFG_EXTND_FMT_SUPPORT,Extended Fmt Field Supported. If set the Function supports the 3-bit definition of the Fmt field. If clear the Function supports a 2-bit definition of the Fmt field. For more details see section 2.2 of PCI Express Base.." "0,1" rbitfld.long 0x24 17. "PCIE_CAP2_10_BIT_TAG_REQ_SUPPORT,10-Bit Tag Requester Supported. If this bit is set the Function supports 10-Bit Tag Requester capability; otherwise the Function does not. This bit must not be set if the 10-Bit Tag Completer Supported bit is clear." "0,1" newline rbitfld.long 0x24 16. "PCIE_CAP2_10_BIT_TAG_COMP_SUPPORT,10-Bit Tag Completer Supported. If this bit is set the Function supports 10-Bit Tag Completer capability; otherwise the Function does not. For more details see section 2.2.6.2. of PCI Express Base Specification." "0,1" rbitfld.long 0x24 13. "PCIE_CAP_TPH_CMPLT_SUPPORT_1,TPH Completer Supported Bit 1." "0,1" newline rbitfld.long 0x24 12. "PCIE_CAP_TPH_CMPLT_SUPPORT_0,TPH Completer Supported Bit 0. Value of this bit along with TPH Completer Supported Bit 1 indicates Completer support for TPH or Extended TPH. Applicable only to Root Ports and Endpoints. For all other Functions this field.." "0,1" bitfld.long 0x24 11. "PCIE_CAP_LTR_SUPP,LTR Mechanism Supported. A value of 1b indicates support for the optional Latency Tolerance Reporting (LTR) mechanism. Root Ports Switches and Endpoints are permitted to implement this capability. For a Multi-Function Device associated.." "0,1" newline rbitfld.long 0x24 10. "PCIE_CAP_NO_RO_EN_PR2PR_PAR,No RO-enabled PR-PR Passing. If this bit is set the routing element never carries out the passing permitted by Table 2-39 of PCI Express Base Specification entry A2b that is associated with the Relaxed Ordering Attribute.." "0,1" rbitfld.long 0x24 9. "PCIE_CAP_128_CAS_CPL_SUPP,128-bit CAS Completer Supported. Applicable to Functions with Memory Space BARs as well as all Root Ports; must be 0b otherwise. This bit must be set to 1b if the Function supports this optional capability. For more details see.." "0,1" newline rbitfld.long 0x24 8. "PCIE_CAP_64_ATOMIC_CPL_SUPP,64-bit AtomicOp Completer Supported. Applicable to Functions with Memory Space BARs as well as all Root Ports; must be 0b otherwise. Includes FetchAdd Swap and CAS AtomicOps. This bit must be set to 1b if the Function.." "0,1" rbitfld.long 0x24 7. "PCIE_CAP_32_ATOMIC_CPL_SUPP,32-bit AtomicOp Completer Supported. Applicable to Functions with Memory Space BARs as well as all Root Ports; must be 0b otherwise. Includes FetchAdd Swap and CAS AtomicOps. This bit must be set to 1b if the Function.." "0,1" newline rbitfld.long 0x24 6. "PCIE_CAP_ATOMIC_ROUTING_SUPP,AtomicOp Routing Supported. Applicable only to Switch Upstream Ports Switch Downstream Ports and Root Ports; must be 0b for other Function types. This bit must be set to 1b if the Port supports this optional capability. For.." "0,1" rbitfld.long 0x24 5. "PCIE_CAP_ARI_FORWARD_SUPPORT,ARI Forwarding Supported. Applicable only to Switch Downstream Ports and Root Ports; must be 0b for other Function types. This bit must be set to 1b if a Switch Downstream Port or Root Port supports this optional capability." "0,1" newline rbitfld.long 0x24 4. "PCIE_CAP_CPL_TIMEOUT_DISABLE_SUPPORT,Completion Timeout Disable Supported. A value of 1b indicates support for the Completion Timeout Disable mechanism. The Completion Timeout Disable mechanism is required for Endpoints that issue Requests on their own.." "0,1" hexmask.long.byte 0x24 0.--3. 1. "PCIE_CAP_CPL_TIMEOUT_RANGE,Completion Timeout Ranges Supported. This field indicates device Function support for the optional Completion Timeout programmability mechanism. This mechanism allows system software to modify the Completion Timeout value. This.." line.long 0x28 "DEVICE_CONTROL2_DEVICE_STATUS2_REG,Device Control 2 and Status 2 Register." hexmask.long.word 0x28 16.--31. 1. "RSVDP_16,Reserved for future use." bitfld.long 0x28 15. "PCIE_CTRL2_CFG_END2END_TLP_PFX_BLCK,End-End TLP Prefix Blocking. Controls whether the routing function is permitted to forward TLPs containing an End-End TLP Prefix. Values are: - 0b: Forwarding Enabled - Function is permitted to send TLPs with End-End.." "0,1" newline rbitfld.long 0x28 11. "RSVDP_11,Reserved for future use." "0,1" bitfld.long 0x28 10. "PCIE_CAP_LTR_EN,LTR Mechanism Enable. When set to 1b this bit enables Upstream Ports to send LTR messages and Downstream Ports to process LTR Messages. For a Multi-Function Device associated with an Upstream Port of a device that implements LTR the bit.." "0,1" newline rbitfld.long 0x28 5. "PCIE_CAP_ARI_FORWARD_SUPPORT_CS,ARI Forwarding Enable. When set the Downstream Port disables its traditional Device Number field being 0 enforcement when turning a Type 1 Configuration Request into a Type 0 Configuration Request permitting access to.." "0,1" bitfld.long 0x28 4. "PCIE_CAP_CPL_TIMEOUT_DISABLE,Completion Timeout Disable. When set this bit disables the Completion Timeout mechanism. This bit is required for all Functions that support the Completion Timeout Disable Capability. Functions that do not support this.." "0,1" newline hexmask.long.byte 0x28 0.--3. 1. "PCIE_CAP_CPL_TIMEOUT_VALUE,Completion Timeout Value. In device Functions that support Completion Timeout programmability this field allows system software to modify the Completion Timeout value. This field is applicable to Root Ports Endpoints that.." line.long 0x2C "LINK_CAPABILITIES2_REG,Link Capabilities 2 Register." bitfld.long 0x2C 31. "DRS_SUPPORTED,DRS Supported. When set indicates support for the optional Device Readiness Status (DRS) capability. Must be Set in Downstream Ports that support DRS. Must be Set in Downstream Ports that support FRS. For Upstream Ports that support DRS.." "0,1" hexmask.long.byte 0x2C 25.--30. 1. "RSVDP_25,Reserved for future use." newline hexmask.long.word 0x2C 9.--22. 1. "RSVDP_9,Reserved for future use." rbitfld.long 0x2C 8. "PCIE_CAP_CROSS_LINK_SUPPORT,Crosslink Supported. When set to 1b this bit indicates that the associated Port supports crosslinks (for more details see section 4.2.6.3.1 of PCI Express Base Specification). When set to 0b on a Port that supports Link.." "0,1" newline hexmask.long.byte 0x2C 1.--7. 1. "PCIE_CAP_SUPPORT_LINK_SPEED_VECTOR,Supported Link Speeds Vector. This field indicates the supported Link speed(s) of the associated Port. For each bit a value of 1b indicates that the corresponding Link speed is supported; otherwise the Link speed is.." rbitfld.long 0x2C 0. "RSVDP_0,Reserved for future use." "0,1" line.long 0x30 "LINK_CONTROL2_LINK_STATUS2_REG,Link Control 2 and Status 2 Register." bitfld.long 0x30 31. "DRS_MESSAGE_RECEIVED,DRS Message Received. This bit must be set whenever the Port receives a DRS Message. This bit must be cleared in DL_Down. This bit must be implemented in any Downstream Port where the DRS Supported bit is Set in the Link Capabilities.." "0,1" rbitfld.long 0x30 28.--30. "DOWNSTREAM_COMPO_PRESENCE,Downstream Component Presence. This field indicates the presence and DRS status for the Downstream Component if any connected to the Link; defined values are: - 000b: Link Down - Presence Not Determined - 001b: Link Down -.." "0,1,2,3,4,5,6,7" newline rbitfld.long 0x30 26.--27. "RSVDP_26,Reserved for future use." "0,1,2,3" bitfld.long 0x30 21. "PCIE_CAP_LINK_EQ_REQ,Link Equalization Request 8.0 GT/s. This bit is set by hardware to request the 8.0 GT/s Link equalization process to be performed on the Link. For more details see sections 4.2.3 and 4.2.6.4.2 of PCI Express Base Specification. For.." "0,1" newline rbitfld.long 0x30 20. "PCIE_CAP_EQ_CPL_P3,EEqualization 8.0 GT/s Phase 3 Successful. When set to 1b this bit indicates that Phase 3 of the 8.0 GT/s Transmitter Equalization procedure has successfully completed. Details of the Transmitter Equalization process and when this bit.." "0,1" rbitfld.long 0x30 19. "PCIE_CAP_EQ_CPL_P2,Equalization 8.0 GT/s Phase 2 Successful. When set to 1b this bit indicates that Phase 2 of the 8.0 GT/s Transmitter Equalization procedure has successfully completed. Details of the Transmitter Equalization process and when this bit.." "0,1" newline rbitfld.long 0x30 18. "PCIE_CAP_EQ_CPL_P1,Equalization 8.0 GT/s Phase 1 Successful. When set to 1b this bit indicates that Phase 1 of the 8.0 GT/s Transmitter Equalization procedure has successfully completed. Details of the Transmitter Equalization process and when this bit.." "0,1" rbitfld.long 0x30 17. "PCIE_CAP_EQ_CPL,Equalization 8.0 GT/s Complete. When set to 1b this bit indicates that the Transmitter Equalization procedure at the 8.0 GT/s data rate has completed. Details of the Transmitter Equalization process and when this bit needs to be set to.." "0,1" newline rbitfld.long 0x30 16. "PCIE_CAP_CURR_DEEMPHASIS,Current De-emphasis Level. When the Link is operating at 5.0 GT/s speed this bit reflects the level of de-emphasis. Encodings: - 1b: -3.5 dB - 0b: -6 dB The value in this bit is undefined when the Link is not operating at 5.0.." "0,1" hexmask.long.byte 0x30 12.--15. 1. "PCIE_CAP_COMPLIANCE_PRESET,Compliance Preset/De-emphasis. For 8.0 GT/s and higher Data Rate: This field sets the Transmitter Preset in Polling.Compliance state if the entry occurred due to the Enter Compliance bit being 1b. The encodings are defined in.." newline bitfld.long 0x30 11. "PCIE_CAP_COMPLIANCE_SOS,Compliance SOS. When set to 1b the LTSSM is required to send SKP Ordered Sets between sequences when sending the Compliance Pattern or Modified Compliance Pattern. For a Multi-Function Device associated with an Upstream Port the.." "0,1" bitfld.long 0x30 10. "PCIE_CAP_ENTER_MODIFIED_COMPLIANCE,Enter Modified Compliance. When this bit is set to 1b the device transmits Modified Compliance Pattern if the LTSSM enters Polling.Compliance substate. Components that support only the 2.5 GT/s speed are permitted to.." "0,1" newline bitfld.long 0x30 7.--9. "PCIE_CAP_TX_MARGIN,Transmit Margin - This field controls the value of the non-deemphasized voltage level at the Transmitter pins. This field is reset to 000b on entry to the LTSSM Polling.Configuration substate (see Chapter 4 of PCI Express Base.." "0,1,2,3,4,5,6,7" bitfld.long 0x30 6. "PCIE_CAP_SEL_DEEMPHASIS,Selectable De-emphasis. When the Link is operating at 5.0 GT/s speed this bit is used to control the transmit de-emphasis of the link in specific situations. For more details see section 4.2.6 of PCI Express Base Specification." "0,1" newline bitfld.long 0x30 5. "PCIE_CAP_HW_AUTO_SPEED_DISABLE,Hardware Autonomous Speed Disable. When set this bit disables hardware from changing the Link speed for device-specific reasons other than attempting to correct unreliable Link operation by reducing Link speed. Initial.." "0,1" bitfld.long 0x30 4. "PCIE_CAP_ENTER_COMPLIANCE,Enter Compliance. Software is permitted to force a Link to enter Compliance mode (at the speed indicated in the Target Link Speed field and the de-emphasis/preset level indicated by the Compliance Preset/De-emphasis field) by.." "0,1" newline hexmask.long.byte 0x30 0.--3. 1. "PCIE_CAP_TARGET_LINK_SPEED,Target Link Speed. For Downstream Ports this field sets an upper limit on Link operational speed by restricting the values advertised by the Upstream component in its training sequences. The encoded value specifies a bit.." tree.end tree "PF0_AER_CAP (PF Advanced Error Reporting Capability Structure)" group.long (0x0+0x100)++0x1B line.long 0x0 "AER_EXT_CAP_HDR_OFF,Advanced Error Reporting Extended Capability Header. For a description of this standard PCIe register. see the PCI Express Specification." hexmask.long.word 0x0 20.--31. 1. "NEXT_OFFSET,Next Capability Offset. For a description of this standard PCIe register field see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky).." hexmask.long.byte 0x0 16.--19. 1. "CAP_VERSION,Capability Version. For a description of this standard PCIe register field see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else.." hexmask.long.word 0x0 0.--15. 1. "CAP_ID,AER Extended Capability ID. For a description of this standard PCIe register field see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else.." line.long 0x4 "UNCORR_ERR_STATUS_OFF,Uncorrectable Error Status Register. For a description of this standard PCIe register. see the PCI Express Specification." hexmask.long.byte 0x4 27.--31. 1. "RSVDP_27,Reserved for future use." bitfld.long 0x4 25. "TLP_PRFX_BLOCKED_ERR_STATUS,TLP Prefix Blocked Error Status. For a description of this standard PCIe register field see the PCI Express Specification. Note: Not supported." "0,1" rbitfld.long 0x4 23. "RSVDP_23,Reserved for future use." "0,1" newline bitfld.long 0x4 22. "INTERNAL_ERR_STATUS,Uncorrectable Internal Error Status. For a description of this standard PCIe register field see the PCI Express Specification. The controller sets this bit when your application asserts app_err_bus[9]. It does not set this bit when.." "0,1" bitfld.long 0x4 20. "UNSUPPORTED_REQ_ERR_STATUS,Unsupported Request Error Status. For a description of this standard PCIe register field see the PCI Express Specification." "0,1" bitfld.long 0x4 19. "ECRC_ERR_STATUS,ECRC Error Status. For a description of this standard PCIe register field see the PCI Express Specification. Note:If CX_ECRC_ENABLE=0 the register field always reads 0." "0,1" newline bitfld.long 0x4 18. "MALF_TLP_ERR_STATUS,Malformed TLP Status. For a description of this standard PCIe register field see the PCI Express Specification." "0,1" bitfld.long 0x4 17. "REC_OVERFLOW_ERR_STATUS,Receiver Overflow Status. For a description of this standard PCIe register field see the PCI Express Specification." "0,1" bitfld.long 0x4 16. "UNEXP_CMPLT_ERR_STATUS,Unexpected Completion Status. For a description of this standard PCIe register field see the PCI Express Specification." "0,1" newline bitfld.long 0x4 15. "CMPLT_ABORT_ERR_STATUS,Completer Abort Status. For a description of this standard PCIe register field see the PCI Express Specification." "0,1" bitfld.long 0x4 14. "CMPLT_TIMEOUT_ERR_STATUS,Completion Timeout Status. For a description of this standard PCIe register field see the PCI Express Specification." "0,1" bitfld.long 0x4 13. "FC_PROTOCOL_ERR_STATUS,Flow Control Protocol Error Status. For a description of this standard PCIe register field see the PCI Express Specification." "0,1" newline bitfld.long 0x4 12. "POIS_TLP_ERR_STATUS,Poisoned TLP Status. For a description of this standard PCIe register field see the PCI Express Specification." "0,1" hexmask.long.byte 0x4 6.--11. 1. "RSVDP_6,Reserved for future use." bitfld.long 0x4 5. "SURPRISE_DOWN_ERR_STATUS,Surprise Down Error Status (Optional). For a description of this standard PCIe register field see the PCI Express Specification." "0,1" newline bitfld.long 0x4 4. "DL_PROTOCOL_ERR_STATUS,Data Link Protocol Error Status. For a description of this standard PCIe register field see the PCI Express Specification." "0,1" hexmask.long.byte 0x4 0.--3. 1. "RSVDP_0,Reserved for future use." line.long 0x8 "UNCORR_ERR_MASK_OFF,Uncorrectable Error Mask Register. For a description of this standard PCIe register. see the PCI Express Specification." hexmask.long.byte 0x8 27.--31. 1. "RSVDP_27,Reserved for future use." bitfld.long 0x8 25. "TLP_PRFX_BLOCKED_ERR_MASK,TLP Prefix Blocked Error Mask. For a description of this standard PCIe register field see the PCI Express Specification. Note: Not supported. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi:.." "0,1" rbitfld.long 0x8 23. "RSVDP_23,Reserved for future use." "0,1" newline bitfld.long 0x8 22. "INTERNAL_ERR_MASK,Uncorrectable Internal Error Mask (Optional). For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." "0,1" rbitfld.long 0x8 21. "ACS_VIOLATION_MASK,ACS Violation Mask. Setting the ACS Violation Mask bit disables error logging and signaling for ACS Violation errors. The bit is Read-Only Zero for upstream ports when ACS P2P Egress Control Enable is not set. For a description of.." "0,1" bitfld.long 0x8 20. "UNSUPPORTED_REQ_ERR_MASK,Unsupported Request Error Mask. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." "0,1" newline bitfld.long 0x8 19. "ECRC_ERR_MASK,ECRC Error Mask (Optional). For a description of this standard PCIe register field see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W (sticky) Note: This register.." "0,1" bitfld.long 0x8 18. "MALF_TLP_ERR_MASK,Malformed TLP Mask. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." "0,1" bitfld.long 0x8 17. "REC_OVERFLOW_ERR_MASK,Receiver Overflow Mask (Optional). For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." "0,1" newline bitfld.long 0x8 16. "UNEXP_CMPLT_ERR_MASK,Unexpected Completion Mask. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." "0,1" bitfld.long 0x8 15. "CMPLT_ABORT_ERR_MASK,Completer Abort Error Mask (Optional). For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." "0,1" bitfld.long 0x8 14. "CMPLT_TIMEOUT_ERR_MASK,Completion Timeout Error Mask. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." "0,1" newline bitfld.long 0x8 13. "FC_PROTOCOL_ERR_MASK,Flow Control Protocol Error Mask. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." "0,1" bitfld.long 0x8 12. "POIS_TLP_ERR_MASK,Poisoned TLP Error Mask. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." "0,1" hexmask.long.byte 0x8 6.--11. 1. "RSVDP_6,Reserved for future use." newline rbitfld.long 0x8 5. "SURPRISE_DOWN_ERR_MASK,Surprise Down Error Mask. For a description of this standard PCIe register field see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi:.." "0,1" bitfld.long 0x8 4. "DL_PROTOCOL_ERR_MASK,Data Link Protocol Error Mask. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." "0,1" hexmask.long.byte 0x8 0.--3. 1. "RSVDP_0,Reserved for future use." line.long 0xC "UNCORR_ERR_SEV_OFF,Uncorrectable Error Severity Register. For a description of this standard PCIe register. see the PCI Express Specification." hexmask.long.byte 0xC 27.--31. 1. "RSVDP_27,Reserved for future use." bitfld.long 0xC 25. "TLP_PRFX_BLOCKED_ERR_SEVERITY,TLP Prefix Blocked Error Severity (Optional). For a description of this standard PCIe register field see the PCI Express Specification. Note: Not supported. Note: The access attributes of this field are as follows: - Wire:.." "0,1" rbitfld.long 0xC 24. "ATOMIC_EGRESS_BLOCKED_ERR_SEVERITY,AtomicOp Egress Blocked Severity (Optional). For a description of this standard PCIe register field see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi:.." "0,1" newline rbitfld.long 0xC 23. "RSVDP_23,Reserved for future use." "0,1" bitfld.long 0xC 22. "INTERNAL_ERR_SEVERITY,Uncorrectable Internal Error Severity (Optional). For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." "0,1" bitfld.long 0xC 20. "UNSUPPORTED_REQ_ERR_SEVERITY,Unsupported Request Error Severity. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." "0,1" newline bitfld.long 0xC 19. "ECRC_ERR_SEVERITY,ECRC Error Severity (Optional). For a description of this standard PCIe register field see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W (sticky) Note: This.." "0,1" bitfld.long 0xC 18. "MALF_TLP_ERR_SEVERITY,Malformed TLP Severity. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." "0,1" bitfld.long 0xC 17. "REC_OVERFLOW_ERR_SEVERITY,Receiver Overflow Error Severity (Optional). For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." "0,1" newline bitfld.long 0xC 16. "UNEXP_CMPLT_ERR_SEVERITY,Unexpected Completion Error Severity. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." "0,1" bitfld.long 0xC 15. "CMPLT_ABORT_ERR_SEVERITY,Completer Abort Error Severity (Optional). For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." "0,1" bitfld.long 0xC 14. "CMPLT_TIMEOUT_ERR_SEVERITY,Completion Timeout Error Severity. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." "0,1" newline bitfld.long 0xC 13. "FC_PROTOCOL_ERR_SEVERITY,Flow Control Protocol Error Severity (Optional). For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." "0,1" bitfld.long 0xC 12. "POIS_TLP_ERR_SEVERITY,Poisoned TLP Severity. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." "0,1" hexmask.long.byte 0xC 6.--11. 1. "RSVDP_6,Reserved for future use." newline rbitfld.long 0xC 5. "SURPRISE_DOWN_ERR_SVRITY,Surprise Down Error Severity (Optional). For a description of this standard PCIe register field see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi:.." "0,1" bitfld.long 0xC 4. "DL_PROTOCOL_ERR_SEVERITY,Data Link Protocol Error Severity. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." "0,1" hexmask.long.byte 0xC 0.--3. 1. "RSVDP_0,Reserved for future use." line.long 0x10 "CORR_ERR_STATUS_OFF,Correctable Error Status Register. For a description of this standard PCIe register. see the PCI Express Specification." hexmask.long.word 0x10 16.--31. 1. "RSVDP_16,Reserved for future use." bitfld.long 0x10 15. "HEADER_LOG_OVERFLOW_STATUS,Header Log Overflow Error Status (Optional). For a description of this standard PCIe register field see the PCI Express Specification." "0,1" bitfld.long 0x10 14. "CORRECTED_INT_ERR_STATUS,Corrected Internal Error Status (Optional). For a description of this standard PCIe register field see the PCI Express Specification." "0,1" newline bitfld.long 0x10 13. "ADVISORY_NON_FATAL_ERR_STATUS,Advisory Non-Fatal Error Status. For a description of this standard PCIe register field see the PCI Express Specification." "0,1" bitfld.long 0x10 12. "RPL_TIMER_TIMEOUT_STATUS,Replay Timer Timeout Status. For a description of this standard PCIe register field see the PCI Express Specification." "0,1" rbitfld.long 0x10 9.--11. "RSVDP_9,Reserved for future use." "0,1,2,3,4,5,6,7" newline bitfld.long 0x10 8. "REPLAY_NO_ROLEOVER_STATUS,REPLAY_NUM Rollover Status. For a description of this standard PCIe register field see the PCI Express Specification." "0,1" bitfld.long 0x10 7. "BAD_DLLP_STATUS,Bad DLLP Status. For a description of this standard PCIe register field see the PCI Express Specification." "0,1" bitfld.long 0x10 6. "BAD_TLP_STATUS,Bad TLP Status. For a description of this standard PCIe register field see the PCI Express Specification." "0,1" newline hexmask.long.byte 0x10 1.--5. 1. "RSVDP_1,Reserved for future use." bitfld.long 0x10 0. "RX_ERR_STATUS,Receiver Error Status (Optional). For a description of this standard PCIe register field see the PCI Express Specification." "0,1" line.long 0x14 "CORR_ERR_MASK_OFF,Correctable Error Mask Register. For a description of this standard PCIe register. see the PCI Express Specification." hexmask.long.word 0x14 16.--31. 1. "RSVDP_16,Reserved for future use." bitfld.long 0x14 15. "HEADER_LOG_OVERFLOW_MASK,Header Log Overflow Error Mask (Optional). For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." "0,1" bitfld.long 0x14 14. "CORRECTED_INT_ERR_MASK,Corrected Internal Error Mask (Optional). For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." "0,1" newline bitfld.long 0x14 13. "ADVISORY_NON_FATAL_ERR_MASK,Advisory Non-Fatal Error Mask. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." "0,1" bitfld.long 0x14 12. "RPL_TIMER_TIMEOUT_MASK,Replay Timer Timeout Mask. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." "0,1" rbitfld.long 0x14 9.--11. "RSVDP_9,Reserved for future use." "0,1,2,3,4,5,6,7" newline bitfld.long 0x14 8. "REPLAY_NO_ROLEOVER_MASK,REPLAY_NUM Rollover Mask. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." "0,1" bitfld.long 0x14 7. "BAD_DLLP_MASK,Bad DLLP Mask. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." "0,1" bitfld.long 0x14 6. "BAD_TLP_MASK,Bad TLP Mask. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." "0,1" newline hexmask.long.byte 0x14 1.--5. 1. "RSVDP_1,Reserved for future use." bitfld.long 0x14 0. "RX_ERR_MASK,Receiver Error Mask (Optional). For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." "0,1" line.long 0x18 "ADV_ERR_CAP_CTRL_OFF,Advanced Error Capabilities and Control Register. For a description of this standard PCIe register. see the PCI Express Specification." hexmask.long.tbyte 0x18 13.--31. 1. "RSVDP_13,Reserved for future use." rbitfld.long 0x18 12. "CTO_PRFX_HDR_LOG_CAP,TLP Prefix Log Present. For a description of this standard PCIe register field see the PCI Express Specification." "0,1" rbitfld.long 0x18 11. "TLP_PRFX_LOG_PRESENT,Completion Timeout Prefix/Header Log Capable. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." "0,1" newline rbitfld.long 0x18 10. "MULTIPLE_HEADER_EN,Multiple Header Recording Enable. For a description of this standard PCIe register field see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R (sticky) Note: This.." "0,1" rbitfld.long 0x18 9. "MULTIPLE_HEADER_CAP,Multiple Header Recording Capable. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." "0,1" bitfld.long 0x18 8. "ECRC_CHECK_EN,ECRC Check Enable. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." "0,1" newline rbitfld.long 0x18 7. "ECRC_CHECK_CAP,ECRC Check Capable. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." "0,1" bitfld.long 0x18 6. "ECRC_GEN_EN,ECRC Generation Enable. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." "0,1" rbitfld.long 0x18 5. "ECRC_GEN_CAP,ECRC Generation Capable. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." "0,1" newline hexmask.long.byte 0x18 0.--4. 1. "FIRST_ERR_POINTER,First Error Pointer. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." rgroup.long (0x1C+0x100)++0xF line.long 0x0 "HDR_LOG_0_OFF,Header Log Register 0. For a description of this standard PCIe register. see the PCI Express Specification." hexmask.long.byte 0x0 24.--31. 1. "FIRST_DWORD_FOURTH_BYTE,Byte 3 of Header log register of First 32 bit Data Word. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." hexmask.long.byte 0x0 16.--23. 1. "FIRST_DWORD_THIRD_BYTE,Byte 2 of Header log register of First 32 bit Data Word. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." hexmask.long.byte 0x0 8.--15. 1. "FIRST_DWORD_SECOND_BYTE,Byte 1 of Header log register of First 32 bit Data Word. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." newline hexmask.long.byte 0x0 0.--7. 1. "FIRST_DWORD_FIRST_BYTE,Byte 0 of Header log register of First 32 bit Data Word. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." line.long 0x4 "HDR_LOG_1_OFF,Header Log Register 1. For a description of this standard PCIe register. see the PCI Express Specification." hexmask.long.byte 0x4 24.--31. 1. "SECOND_DWORD_FOURTH_BYTE,Byte 3 of Header log register of Second 32 bit Data Word. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." hexmask.long.byte 0x4 16.--23. 1. "SECOND_DWORD_THIRD_BYTE,Byte 2 of Header log register of Second 32 bit Data Word. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." hexmask.long.byte 0x4 8.--15. 1. "SECOND_DWORD_SECOND_BYTE,Byte 1 of Header log register of Second 32 bit Data Word. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." newline hexmask.long.byte 0x4 0.--7. 1. "SECOND_DWORD_FIRST_BYTE,Byte 0 of Header log register of Second 32 bit Data Word. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." line.long 0x8 "HDR_LOG_2_OFF,Header Log Register 2. For a description of this standard PCIe register. see the PCI Express Specification." hexmask.long.byte 0x8 24.--31. 1. "THIRD_DWORD_FOURTH_BYTE,Byte 3 of Header log register of Third 32 bit Data Word. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." hexmask.long.byte 0x8 16.--23. 1. "THIRD_DWORD_THIRD_BYTE,Byte 2 of Header log register of Third 32 bit Data Word. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." hexmask.long.byte 0x8 8.--15. 1. "THIRD_DWORD_SECOND_BYTE,Byte 1 of Header log register of Third 32 bit Data Word. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." newline hexmask.long.byte 0x8 0.--7. 1. "THIRD_DWORD_FIRST_BYTE,Byte 0 of Header log register of Third 32 bit Data Word. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." line.long 0xC "HDR_LOG_3_OFF,Header Log Register 3. For a description of this standard PCIe register. see the PCI Express Specification." hexmask.long.byte 0xC 24.--31. 1. "FOURTH_DWORD_FOURTH_BYTE,Byte 3 of Header log register of Fourth 32 bit Data Word. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." hexmask.long.byte 0xC 16.--23. 1. "FOURTH_DWORD_THIRD_BYTE,Byte 2 of Header log register of Fourth 32 bit Data Word. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." hexmask.long.byte 0xC 8.--15. 1. "FOURTH_DWORD_SECOND_BYTE,Byte 1 of Header log register of Fourth 32 bit Data Word. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." newline hexmask.long.byte 0xC 0.--7. 1. "FOURTH_DWORD_FIRST_BYTE,Byte 0 of Header log register of Fourth 32 bit Data Word. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." group.long (0x2C+0x100)++0x7 line.long 0x0 "ROOT_ERR_CMD_OFF,Root Error Command Register. For a description of this standard PCIe register. see the PCI Express Specification." hexmask.long 0x0 3.--31. 1. "RSVDP_3,Reserved for future use." bitfld.long 0x0 2. "FATAL_ERR_REPORTING_EN,Fatal Error Reporting Enable. For a description of this standard PCIe register field see the PCI Express Specification." "0,1" bitfld.long 0x0 1. "NON_FATAL_ERR_REPORTING_EN,Non-Fatal Error Reporting Enable. For a description of this standard PCIe register field see the PCI Express Specification." "0,1" newline bitfld.long 0x0 0. "CORR_ERR_REPORTING_EN,Correctable Error Reporting Enable. For a description of this standard PCIe register field see the PCI Express Specification." "0,1" line.long 0x4 "ROOT_ERR_STATUS_OFF,Root Error Status Register. For a description of this standard PCIe register. see the PCI Express Specification." hexmask.long.byte 0x4 27.--31. 1. "ADV_ERR_INT_MSG_NUM,Advanced Error Interrupt Message Number. For a description of this standard PCIe register field see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN.." hexmask.long.tbyte 0x4 7.--26. 1. "RSVDP_7,Reserved for future use." bitfld.long 0x4 6. "FATAL_ERR_MSG_RX,One or more Fatal Error Messages Received. For a description of this standard PCIe register field see the PCI Express Specification." "0,1" newline bitfld.long 0x4 5. "NON_FATAL_ERR_MSG_RX,One or more Non-Fatal Error Messages Received. For a description of this standard PCIe register field see the PCI Express Specification." "0,1" bitfld.long 0x4 4. "FIRST_UNCORR_FATAL,First Uncorrectable Error is Fatal. For a description of this standard PCIe register field see the PCI Express Specification." "0,1" bitfld.long 0x4 3. "MUL_ERR_FATAL_NON_FATAL_RX,Multiple Fatal or Non-Fatal Errors Received. For a description of this standard PCIe register field see the PCI Express Specification." "0,1" newline bitfld.long 0x4 2. "ERR_FATAL_NON_FATAL_RX,Fatal or Non-Fatal Error Received. For a description of this standard PCIe register field see the PCI Express Specification." "0,1" bitfld.long 0x4 1. "MUL_ERR_COR_RX,Multiple Correctable Errors Received. For a description of this standard PCIe register field see the PCI Express Specification." "0,1" bitfld.long 0x4 0. "ERR_COR_RX,Correctable Error Received. For a description of this standard PCIe register field see the PCI Express Specification." "0,1" rgroup.long (0x34+0x100)++0x13 line.long 0x0 "ERR_SRC_ID_OFF,Error Source Identification Register. For a description of this standard PCIe register. see the PCI Express Specification." hexmask.long.word 0x0 16.--31. 1. "ERR_FATAL_NON_FATAL_SOURCE_ID,Source of Fatal/Non-Fatal Error. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." hexmask.long.word 0x0 0.--15. 1. "ERR_COR_SOURCE_ID,Source of Correctable Error. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." line.long 0x4 "TLP_PREFIX_LOG_1_OFF,TLP Prefix Log Register 1. For a description of this standard PCIe register. see the PCI Express Specification." hexmask.long.byte 0x4 24.--31. 1. "CFG_TLP_PFX_LOG_1_FOURTH_BYTE,Byte 3 of Error TLP Prefix Log 1. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." hexmask.long.byte 0x4 16.--23. 1. "CFG_TLP_PFX_LOG_1_THIRD_BYTE,Byte 2 of Error TLP Prefix Log 1. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." hexmask.long.byte 0x4 8.--15. 1. "CFG_TLP_PFX_LOG_1_SECOND_BYTE,Byte 1 of Error TLP Prefix Log 1. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." newline hexmask.long.byte 0x4 0.--7. 1. "CFG_TLP_PFX_LOG_1_FIRST_BYTE,Byte 0 of Error TLP Prefix Log 1. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." line.long 0x8 "TLP_PREFIX_LOG_2_OFF,TLP Prefix Log Register 2. For a description of this standard PCIe register. see the PCI Express Specification." hexmask.long.byte 0x8 24.--31. 1. "CFG_TLP_PFX_LOG_2_FOURTH_BYTE,Byte 3 Error TLP Prefix Log 2. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." hexmask.long.byte 0x8 16.--23. 1. "CFG_TLP_PFX_LOG_2_THIRD_BYTE,Byte 2 Error TLP Prefix Log 2. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." hexmask.long.byte 0x8 8.--15. 1. "CFG_TLP_PFX_LOG_2_SECOND_BYTE,Byte 1 Error TLP Prefix Log 2. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." newline hexmask.long.byte 0x8 0.--7. 1. "CFG_TLP_PFX_LOG_2_FIRST_BYTE,Byte 0 Error TLP Prefix Log 2. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." line.long 0xC "TLP_PREFIX_LOG_3_OFF,TLP Prefix Log Register 3. For a description of this standard PCIe register. see the PCI Express Specification." hexmask.long.byte 0xC 24.--31. 1. "CFG_TLP_PFX_LOG_3_FOURTH_BYTE,Byte 3 Error TLP Prefix Log 3. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." hexmask.long.byte 0xC 16.--23. 1. "CFG_TLP_PFX_LOG_3_THIRD_BYTE,Byte 2 Error TLP Prefix Log 3. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." hexmask.long.byte 0xC 8.--15. 1. "CFG_TLP_PFX_LOG_3_SECOND_BYTE,Byte 1 Error TLP Prefix Log 3. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." newline hexmask.long.byte 0xC 0.--7. 1. "CFG_TLP_PFX_LOG_3_FIRST_BYTE,Byte 0 Error TLP Prefix Log 3. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." line.long 0x10 "TLP_PREFIX_LOG_4_OFF,TLP Prefix Log Register 4. For a description of this standard PCIe register. see the PCI Express Specification." hexmask.long.byte 0x10 24.--31. 1. "CFG_TLP_PFX_LOG_4_FOURTH_BYTE,Byte 3 Error TLP Prefix Log 4. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." hexmask.long.byte 0x10 16.--23. 1. "CFG_TLP_PFX_LOG_4_THIRD_BYTE,Byte 2 Error TLP Prefix Log 4. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." hexmask.long.byte 0x10 8.--15. 1. "CFG_TLP_PFX_LOG_4_SECOND_BYTE,Byte 1 Error TLP Prefix Log 4. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." newline hexmask.long.byte 0x10 0.--7. 1. "CFG_TLP_PFX_LOG_4_FIRST_BYTE,Byte 0 Error TLP Prefix Log 4. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." tree.end tree "PF0_MSI_CAP (PF MSI Capability Structure)" group.long (0x0+0x50)++0x13 line.long 0x0 "PCI_MSI_CAP_ID_NEXT_CTRL_REG,MSI Capability Header and Message Control Register." hexmask.long.byte 0x0 27.--31. 1. "RSVDP_27,Reserved for future use." bitfld.long 0x0 26. "PCI_MSI_EXT_DATA_EN,Extended Message Data Enable. - If set the function is enabled to provide Extended Message Data. - If clear the function is not enabled to provide Extended Message Data. Note: The access attributes of this field are as follows: -.." "0,1" bitfld.long 0x0 25. "PCI_MSI_EXT_DATA_CAP,Extended Message Data Capable. - If set the function is capable of providing Extended Message Data. - If clear the function does not support providing Extended Message Data. Note: The access attributes of this field are as follows:.." "0,1" newline rbitfld.long 0x0 24. "PCI_PVM_SUPPORT,Per-Vector Masking Capable. - If set the function supports MSI Per-Vector Masking. - If clear the function does not support MSI Per-Vector Masking. This bit must be set if the function is a PF or VF within an SR-IOV Device." "0,1" bitfld.long 0x0 23. "PCI_MSI_64_BIT_ADDR_CAP,64 bit address capable. - If set the function is capable of sending a 64-bit message address. - If clear the function is not capable of sending a 64-bit message address. This bit must be set if the function is a PCI Express.." "0,1" bitfld.long 0x0 20.--22. "PCI_MSI_MULTIPLE_MSG_EN,Multiple Message Enable. Software writes to this field to indicate the number of allocated vectors (equal to or less than the number of requested vectors). The number of allocated vectors is aligned to a power of two. If a.." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 17.--19. "PCI_MSI_MULTIPLE_MSG_CAP,Multiple Message Capable. System software reads this field to determine the number of requested vectors. The number of requested vectors must be aligned to a power of two (if a function requires three vectors it requests four by.." "0,1,2,3,4,5,6,7" bitfld.long 0x0 16. "PCI_MSI_ENABLE,MSI Enable. - If set and the MSI-X Enable bit in the MSI-X Message Control register is clear the function is permitted to use MSI to request service and is prohibited from using INTx interrupts. System configuration software sets this bit.." "0,1" hexmask.long.byte 0x0 8.--15. 1. "PCI_MSI_CAP_NEXT_OFFSET,Next Capability Pointer. This field contains the offset to the next PCI Capability structure or 00h if no other items exist in the linked list of Capabilities. Note: The access attributes of this field are as follows: - Wire: No.." newline hexmask.long.byte 0x0 0.--7. 1. "PCI_MSI_CAP_ID,Capability ID. Indicates the MSI Capability structure. This field returns a Capability ID of 05h indicating that this is an MSI Capability structure." line.long 0x4 "MSI_CAP_OFF_04H_REG,Message Address Register for MSI (Offset 04h)." hexmask.long 0x4 2.--31. 1. "PCI_MSI_CAP_OFF_04H,Message Address - System-specified message address. If the Message Enable bit (bit 16 of the PCI_MSI_CAP_ID_NEXT_CTRL_REG register) is set the contents of this field specify the DWORD-aligned address (Address[31:02]) for the MSI.." rbitfld.long 0x4 0.--1. "RSVDP_0,Reserved for future use." "0,1,2,3" line.long 0x8 "MSI_CAP_OFF_08H_REG,For a function that supports a 32-bit message address. - bits[31:16] of this register represent the Extended Message Data. and - bits[15:0] of this register represent the Message Data For a function that supports a 64-bit message.." hexmask.long.word 0x8 16.--31. 1. "PCI_MSI_CAP_OFF_0AH,For a function that supports a 32-bit message address this field contains Extended Message Data (System-specified message data). For the MSI Capability structures without per-vector masking it must be implemented if the Extended.." hexmask.long.word 0x8 0.--15. 1. "PCI_MSI_CAP_OFF_08H,For a function that supports a 32-bit message address this field contains Message Data (System-specified message data). If the Message Enable bit (bit 16 of the PCI_MSI_CAP_ID_NEXT_CTRL_REG) is set the function sends a DWORD Memory.." line.long 0xC "MSI_CAP_OFF_0CH_REG,For a function that supports a 32-bit message address. this register contains the Mask Bits when the Per-Vector Masking Capable bit (bit 24 of PCI_MSI_CAP_ID_NEXT_CTRL_REG) is set. For a function that supports a 64-bit message.." hexmask.long.word 0xC 16.--31. 1. "PCI_MSI_CAP_OFF_0EH,For a function that supports a 32-bit message address this field contains the upper Mask Bits when the Per Vector Masking Capable bit (PCI_MSI_CAP_ID_NEXT_CTRL_REG.PCI_PVM_SUPPORT) is set. For a function that supports a 64-bit.." hexmask.long.word 0xC 0.--15. 1. "PCI_MSI_CAP_OFF_0CH,For a function that supports a 32-bit message address this field contains the lower Mask Bits when the Per Vector Masking Capable bit (PCI_MSI_CAP_ID_NEXT_CTRL_REG.PCI_PVM_SUPPORT) is set. For a function that supports a 64-bit.." line.long 0x10 "MSI_CAP_OFF_10H_REG,For a function that supports a 32-bit message address. this register contains the Pending Bits when the Per-Vector Masking Capable bit (bit 24 of PCI_MSI_CAP_ID_NEXT_CTRL_REG) is set. For a function that supports a 64-bit message.." hexmask.long 0x10 0.--31. 1. "PCI_MSI_CAP_OFF_10H,Used for MSI when the Per Vector Masking Capable bit (PCI_MSI_CAP_ID_NEXT_CTRL_REG.PCI_PVM_SUPPORT) is set. For 32-bit contains Pending Bits. For 64-bit contains Mask Bits. For a description of this standard PCIe register field see.." rgroup.long (0x14+0x50)++0x3 line.long 0x0 "MSI_CAP_OFF_14H_REG,Pending Bits Register for MSI. This register is used for a function that supports a 64-bit message address when the Per-Vector Masking Capable bit (bit 24 of PCI_MSI_CAP_ID_NEXT_CTRL_REG) is set." hexmask.long 0x0 0.--31. 1. "PCI_MSI_CAP_OFF_14H,Pending Bits. For each pending bit that is set the function has a pending associated message." tree.end tree "PF0_MSIX_CAP (PF MSI-X Capability Structure)" group.long (0x0+0xB0)++0xB line.long 0x0 "PCI_MSIX_CAP_ID_NEXT_CTRL_REG,MSI-X Capability ID. Next Pointer. Control Registers. For a description of this standard PCIe register. see the PCI Express Base Specification." bitfld.long 0x0 31. "PCI_MSIX_ENABLE,MSI-X Enable. For a description of this standard PCIe register field see the PCI Express Base Specification." "0,1" bitfld.long 0x0 30. "PCI_MSIX_FUNCTION_MASK,Function Mask. For a description of this standard PCIe register field see the PCI Express Base Specification. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" "0,1" rbitfld.long 0x0 27.--29. "RSVDP_27,Reserved for future use." "0,1,2,3,4,5,6,7" newline hexmask.long.word 0x0 16.--26. 1. "PCI_MSIX_TABLE_SIZE,MSI-X Table Size. For a description of this standard PCIe register field see the PCI Express Base Specification. SRIOV Note: All VFs in a single PF have the same value for 'MSI-X Table Size' (PCI_MSIX_TABLE_SIZE field in.." hexmask.long.byte 0x0 8.--15. 1. "PCI_MSIX_CAP_NEXT_OFFSET,MSI-X Next Capability Pointer. For a description of this standard PCIe register field see the PCI Express Base Specification. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN.." hexmask.long.byte 0x0 0.--7. 1. "PCI_MSIX_CAP_ID,MSI-X Capability ID. For a description of this standard PCIe register field see the PCI Express Base Specification." line.long 0x4 "MSIX_TABLE_OFFSET_REG,MSI-X Table Offset and BIR Register. For a description of this standard PCIe register. see the PCI Express Base Specification." hexmask.long 0x4 3.--31. 1. "PCI_MSIX_TABLE_OFFSET,MSI-X Table Offset. For a description of this standard PCIe register field see the PCI Express Base Specification. SRIOV Note: All VFs in a single PF have the same value for 'MSI-X Table Offset' (PCI_MSIX_TABLE_OFFSET field in.." bitfld.long 0x4 0.--2. "PCI_MSIX_BIR,MSI-X Table BAR Indicator Register Field. For a description of this standard PCIe register field see the PCI Express Base Specification. SRIOV Note: All VFs in a single PF have the same value for 'MSI-X Table BAR Indicator Register'.." "0,1,2,3,4,5,6,7" line.long 0x8 "MSIX_PBA_OFFSET_REG,MSI-X PBA Offset and BIR Register. For a description of this standard PCIe register. see the PCI Express Base Specification." hexmask.long 0x8 3.--31. 1. "PCI_MSIX_PBA_OFFSET,MSI-X PBA Offset. For a description of this standard PCIe register field see the PCI Express Base Specification. SRIOV Note: All VFs in a single PF have the same value for 'MSI-X PBA Offset' (PCI_MSIX_PBA_OFFSET field in.." bitfld.long 0x8 0.--2. "PCI_MSIX_PBA_BIR,MSI-X PBA BIR. For a description of this standard PCIe register field see the PCI Express Base Specification. SRIOV Note: All VFs in a single PF have the same value for 'MSI-X PBA BIR' (PCI_MSIX_PBA_BIR field in.." "0,1,2,3,4,5,6,7" tree.end tree "PF0_MSIX_CAP_DBI2 (DBI2 Shadow Block: PF MSI-X Capability Structure)" rgroup.long (0x0+0x10B0)++0x3 line.long 0x0 "SHADOW_PCI_MSIX_CAP_ID_NEXT_CTRL_REG,MSI-X Capability ID. Next Pointer. Control Registers. For a description of this standard PCIe register. see the PCI Express Base Specification." hexmask.long.byte 0x0 27.--31. 1. "RSVDP_27,Reserved for future use." hexmask.long.word 0x0 16.--26. 1. "PCI_MSIX_TABLE_SIZE,MSI-X Table Size in the shadow register. Note: The access attributes of this field are as follows: - Wire: No access - Dbi: No access - Dbi2: if (DBI_RO_WR_EN == 1) then R/W else R Note: This register field is sticky." hexmask.long.word 0x0 0.--15. 1. "RSVDP_0,Reserved for future use." group.long 0x4++0x7 line.long 0x0 "SHADOW_MSIX_TABLE_OFFSET_REG,MSI-X Table Offset and BIR Register. For a description of this standard PCIe register. see the PCI Express Base Specification." hexmask.long 0x0 3.--31. 1. "PCI_MSIX_TABLE_OFFSET,MSI-X Table Offset. For a description of this standard PCIe register field see the PCI Express Base Specification. Note: The access attributes of this field are as follows: - Wire: No access - Dbi: No access - Dbi2: if.." bitfld.long 0x0 0.--2. "PCI_MSIX_BIR,MSI-X Table BAR Indicator Register Field. For a description of this standard PCIe register field see the PCI Express Base Specification. Note: The access attributes of this field are as follows: - Wire: No access - Dbi: No access - Dbi2: if.." "?,?,if,?,?,?,?,?" line.long 0x4 "SHADOW_MSIX_PBA_OFFSET_REG,MSI-X PBA Offset and BIR Register. For a description of this standard PCIe register. see the PCI Express Base Specification." hexmask.long 0x4 3.--31. 1. "PCI_MSIX_PBA_OFFSET,MSI-X PBA Offset. For a description of this standard PCIe register field see the PCI Express Base Specification. Note: The access attributes of this field are as follows: - Wire: No access - Dbi: No access - Dbi2: if (DBI_RO_WR_EN ==.." bitfld.long 0x4 0.--2. "PCI_MSIX_PBA_BIR,MSI-X PBA BIR. For a description of this standard PCIe register field see the PCI Express Base Specification. Note: The access attributes of this field are as follows: - Wire: No access - Dbi: No access - Dbi2: if (DBI_RO_WR_EN == 1 &&.." "?,?,if,?,?,?,?,?" tree.end tree "PF0_DMA_CAP (DMA Port Logic Structure)" group.long (0x0+0xC8000)++0x3 line.long 0x0 "DMA_CTRL_DATA_ARB_PRIOR_OFF,DMA Arbitration Scheme for TRGT1 Interface. This register is used to control traffic priorities among various sources that are delivered to your application through TRGT1 where 0x0 represents the highest priority. - Non-DMA Rx.." hexmask.long.tbyte 0x0 12.--31. 1. "RSVDP_12,Reserved for future use." bitfld.long 0x0 9.--11. "RDBUFF_TRGT_WEIGHT,DMA Read Channel MWr Requests. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 6.--8. "RD_CTRL_TRGT_WEIGHT,DMA Read Channel MRd Requests. For LL element/descriptor access. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" "0,1,2,3,4,5,6,7" bitfld.long 0x0 3.--5. "WR_CTRL_TRGT_WEIGHT,DMA Write Channel MRd Requests. For DMA data requests and LL element/descriptor access. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 0.--2. "RTRGT1_WEIGHT,Non-DMA Rx Requests. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" "0,1,2,3,4,5,6,7" group.long (0x8+0xC8000)++0xB line.long 0x0 "DMA_CTRL_OFF,DMA Number of Channels Register." hexmask.long.byte 0x0 26.--31. 1. "RSVDP_26,Reserved for future use." bitfld.long 0x0 25. "DIS_C2W_CACHE_RD,Disable DMA Read Channels 'completion to memory write' context cache pre-fetch function. Note: For internal debugging only. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" "0,1" newline bitfld.long 0x0 24. "DIS_C2W_CACHE_WR,Disable DMA Write Channels 'completion to memory write' context cache pre-fetch function. Note: For internal debugging only. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" "0,1" hexmask.long.byte 0x0 20.--23. 1. "RSVDP_20,Reserved for future use." newline hexmask.long.byte 0x0 16.--19. 1. "NUM_DMA_RD_CHAN,Number of Read Channels. You can read this register to determine the number of read channels the DMA controller has been configured to support." hexmask.long.word 0x0 4.--15. 1. "RSVDP_4,Reserved for future use." newline hexmask.long.byte 0x0 0.--3. 1. "NUM_DMA_WR_CHAN,Number of Write Channels. You can read this register to determine the number of write channels the DMA controller has been configured to support." line.long 0x4 "DMA_WRITE_ENGINE_EN_OFF,DMA Write Engine Enable Register." hexmask.long.byte 0x4 24.--31. 1. "RSVDP_24,Reserved for future use." bitfld.long 0x4 23. "DMA_WRITE_ENGINE_EN_HSHAKE_CH7,Enable Handshake for DMA Write Engine Channel 7. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" "0,1" newline bitfld.long 0x4 22. "DMA_WRITE_ENGINE_EN_HSHAKE_CH6,Enable Handshake for DMA Write Engine Channel 6. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" "0,1" bitfld.long 0x4 21. "DMA_WRITE_ENGINE_EN_HSHAKE_CH5,Enable Handshake for DMA Write Engine Channel 5. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" "0,1" newline bitfld.long 0x4 20. "DMA_WRITE_ENGINE_EN_HSHAKE_CH4,Enable Handshake for DMA Write Engine Channel 4. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" "0,1" bitfld.long 0x4 19. "DMA_WRITE_ENGINE_EN_HSHAKE_CH3,Enable Handshake for DMA Write Engine Channel 3. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" "0,1" newline bitfld.long 0x4 18. "DMA_WRITE_ENGINE_EN_HSHAKE_CH2,Enable Handshake for DMA Write Engine Channel 2. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" "0,1" bitfld.long 0x4 17. "DMA_WRITE_ENGINE_EN_HSHAKE_CH1,Enable Handshake for DMA Write Engine Channel 1. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" "0,1" newline bitfld.long 0x4 16. "DMA_WRITE_ENGINE_EN_HSHAKE_CH0,Enable Handshake for DMA Write Engine Channel 0. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" "0,1" hexmask.long.word 0x4 1.--15. 1. "RSVDP_1,Reserved for future use." newline bitfld.long 0x4 0. "DMA_WRITE_ENGINE,DMA Write Engine Enable. - 1: Enable - 0: Disable (Soft Reset) For normal operation you must initially set this bit to '1' before any other software setup actions. You do not need to toggle or rewrite to this bit during normal.." "Disable,Enable" line.long 0x8 "DMA_WRITE_DOORBELL_OFF,DMA Write Doorbell Register." bitfld.long 0x8 31. "WR_STOP,Stop. Set in conjunction with the Doorbell Number field. The DMA write channel stops issuing requests sets the channel status to 'Stopped' and asserts the 'Abort' interrupt if it is enabled. Before setting the Stop bit you must read the.." "0,1" hexmask.long 0x8 3.--30. 1. "RSVDP_3,Reserved for future use." newline bitfld.long 0x8 0.--2. "WR_DOORBELL_NUM,Doorbell Number. You must write the channel number to this register to start the DMA write transfer for that channel. The DMA detects a write to this register field even if the value of this field does not change. You do not need to.." "0,1,2,3,4,5,6,7" group.long (0x18+0xC8000)++0x7 line.long 0x0 "DMA_WRITE_CHANNEL_ARB_WEIGHT_LOW_OFF,DMA Write Engine Channel Arbitration Weight Low Register. The 5-bit channel weight (for write channels 0-3) specifies the maximum number of TLP requests that the DMA can issue for that channel before it must return to.." hexmask.long.word 0x0 20.--31. 1. "RSVDP_20,Reserved for future use." hexmask.long.byte 0x0 15.--19. 1. "WRITE_CHANNEL3_WEIGHT,Channel 3 Weight. The weight is initialized by software before ringing the doorbell. The value is used by the channel weighted round robin arbiter to select the next channel read request. A value of '0' means that one TLP is issued.." newline hexmask.long.byte 0x0 10.--14. 1. "WRITE_CHANNEL2_WEIGHT,Channel 2 Weight. The weight is initialized by software before ringing the doorbell. The value is used by the channel weighted round robin arbiter to select the next channel read request. A value of '0' means that one TLP is issued.." hexmask.long.byte 0x0 5.--9. 1. "WRITE_CHANNEL1_WEIGHT,Channel 1 Weight. The weight is initialized by software before ringing the doorbell. The value is used by the channel weighted round robin arbiter to select the next channel read request. A value of '0' means that one TLP is issued.." newline hexmask.long.byte 0x0 0.--4. 1. "WRITE_CHANNEL0_WEIGHT,Channel 0 Weight. The weight is initialized by software before ringing the doorbell. The value is used by the channel weighted round robin arbiter to select the next channel read request. A value of '0' means that one TLP is issued.." line.long 0x4 "DMA_WRITE_CHANNEL_ARB_WEIGHT_HIGH_OFF,DMA Write Engine Channel Arbitration Weight High Register. The 5-bit channel weight (for write channels 4-7) specifies the maximum number of TLP requests that the DMA can issue for that channel before it must return.." hexmask.long.word 0x4 20.--31. 1. "RSVDP_20,Reserved for future use." hexmask.long.byte 0x4 15.--19. 1. "WRITE_CHANNEL7_WEIGHT,Channel 7 Weight. The weight is initialized by software before ringing the doorbell. The value is used by the channel weighted round robin arbiter to select the next channel read request. A value of '0' means that one TLP is issued.." newline hexmask.long.byte 0x4 10.--14. 1. "WRITE_CHANNEL6_WEIGHT,Channel 6 Weight. The weight is initialized by software before ringing the doorbell. The value is used by the channel weighted round robin arbiter to select the next channel read request. A value of '0' means that one TLP is issued.." hexmask.long.byte 0x4 5.--9. 1. "WRITE_CHANNEL5_WEIGHT,Channel 5 Weight. The weight is initialized by software before ringing the doorbell. The value is used by the channel weighted round robin arbiter to select the next channel read request. A value of '0' means that one TLP is issued.." newline hexmask.long.byte 0x4 0.--4. 1. "WRITE_CHANNEL4_WEIGHT,Channel 4 Weight. The weight is initialized by software before ringing the doorbell. The value is used by the channel weighted round robin arbiter to select the next channel read request. A value of '0' means that one TLP is issued.." group.long (0x2C+0xC8000)++0x7 line.long 0x0 "DMA_READ_ENGINE_EN_OFF,DMA Read Engine Enable Register." hexmask.long.byte 0x0 24.--31. 1. "RSVDP_24,Reserved for future use." bitfld.long 0x0 23. "DMA_READ_ENGINE_EN_HSHAKE_CH7,Enable Handshake for DMA Read Engine Channel 7. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" "0,1" newline bitfld.long 0x0 22. "DMA_READ_ENGINE_EN_HSHAKE_CH6,Enable Handshake for DMA Read Engine Channel 6. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" "0,1" bitfld.long 0x0 21. "DMA_READ_ENGINE_EN_HSHAKE_CH5,Enable Handshake for DMA Read Engine Channel 5. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" "0,1" newline bitfld.long 0x0 20. "DMA_READ_ENGINE_EN_HSHAKE_CH4,Enable Handshake for DMA Read Engine Channel 4. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" "0,1" bitfld.long 0x0 19. "DMA_READ_ENGINE_EN_HSHAKE_CH3,Enable Handshake for DMA Read Engine Channel 3. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" "0,1" newline bitfld.long 0x0 18. "DMA_READ_ENGINE_EN_HSHAKE_CH2,Enable Handshake for DMA Read Engine Channel 2. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" "0,1" bitfld.long 0x0 17. "DMA_READ_ENGINE_EN_HSHAKE_CH1,Enable Handshake for DMA Read Engine Channel 1. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" "0,1" newline bitfld.long 0x0 16. "DMA_READ_ENGINE_EN_HSHAKE_CH0,Enable Handshake for DMA Read Engine Channel 0. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" "0,1" hexmask.long.word 0x0 1.--15. 1. "RSVDP_1,Reserved for future use." newline bitfld.long 0x0 0. "DMA_READ_ENGINE,DMA Read Engine Enable. - 1: Enable - 0: Disable (Soft Reset) For normal operation you must initially set this bit to '1' before any other software setup actions. You do not need to toggle or rewrite to this bit during normal operation." "Disable,Enable" line.long 0x4 "DMA_READ_DOORBELL_OFF,DMA Read Doorbell Register." bitfld.long 0x4 31. "RD_STOP,Stop. Set in conjunction with the Doorbell Number field. The DMA read channel stops issuing requests sets the channel status to 'Stopped' and asserts the 'Abort' interrupt if it is enabled. Before setting the Stop bit you must read the channel.." "0,1" hexmask.long 0x4 3.--30. 1. "RSVDP_3,Reserved for future use." newline bitfld.long 0x4 0.--2. "RD_DOORBELL_NUM,Doorbell Number. You must write 0x0 to this register to start the DMA read transfer for that channel. The DMA detects a write to this register field even if the value of this field does not change. The range of this field is 0x0 to 0x7.." "0,1,2,3,4,5,6,7" group.long (0x38+0xC8000)++0x7 line.long 0x0 "DMA_READ_CHANNEL_ARB_WEIGHT_LOW_OFF,DMA Read Engine Channel Arbitration Weight Low Register. The 5-bit channel weight (for read channels 0-3) specifies the maximum number of TLP requests that the DMA can issue for that channel before it must return to.." hexmask.long.word 0x0 20.--31. 1. "RSVDP_20,Reserved for future use." hexmask.long.byte 0x0 15.--19. 1. "READ_CHANNEL3_WEIGHT,Channel 3 Weight. The weight is initialized by software before ringing the doorbell. The value is used by the channel weighted round robin arbiter to select the next channel read request. Note: The access attributes of this field are.." newline hexmask.long.byte 0x0 10.--14. 1. "READ_CHANNEL2_WEIGHT,Channel 2 Weight. The weight is initialized by software before ringing the doorbell. The value is used by the channel weighted round robin arbiter to select the next channel read request. Note: The access attributes of this field are.." hexmask.long.byte 0x0 5.--9. 1. "READ_CHANNEL1_WEIGHT,Channel 1 Weight. The weight is initialized by software before ringing the doorbell. The value is used by the channel weighted round robin arbiter to select the next channel read request. Note: The access attributes of this field are.." newline hexmask.long.byte 0x0 0.--4. 1. "READ_CHANNEL0_WEIGHT,Channel 0 Weight. The weight is initialized by software before ringing the doorbell. The value is used by the channel weighted round robin arbiter to select the next channel read request. Note: The access attributes of this field are.." line.long 0x4 "DMA_READ_CHANNEL_ARB_WEIGHT_HIGH_OFF,DMA Read Engine Channel Arbitration Weight High Register. The 5-bit channel weight (for read channels 4-7) specifies the maximum number of TLP requests that the DMA can issue for that channel before it must return to.." hexmask.long.word 0x4 20.--31. 1. "RSVDP_20,Reserved for future use." hexmask.long.byte 0x4 15.--19. 1. "READ_CHANNEL7_WEIGHT,Channel 7 Weight. The weight is initialized by software before ringing the doorbell. The value is used by the channel weighted round robin arbiter to select the next channel read request. Note: The access attributes of this field are.." newline hexmask.long.byte 0x4 10.--14. 1. "READ_CHANNEL6_WEIGHT,Channel 6 Weight. The weight is initialized by software before ringing the doorbell. The value is used by the channel weighted round robin arbiter to select the next channel read request. Note: The access attributes of this field are.." hexmask.long.byte 0x4 5.--9. 1. "READ_CHANNEL5_WEIGHT,Channel 5 Weight. The weight is initialized by software before ringing the doorbell. The value is used by the channel weighted round robin arbiter to select the next channel read request. Note: The access attributes of this field are.." newline hexmask.long.byte 0x4 0.--4. 1. "READ_CHANNEL4_WEIGHT,Channel 4 Weight. The weight is initialized by software before ringing the doorbell. The value is used by the channel weighted round robin arbiter to select the next channel read request. Note: The access attributes of this field are.." group.long (0x4C+0xC8000)++0x3 line.long 0x0 "DMA_WRITE_INT_STATUS_OFF,DMA Write Interrupt Status Register." hexmask.long.byte 0x0 24.--31. 1. "RSVDP_24,Reserved for future use." hexmask.long.byte 0x0 16.--23. 1. "WR_ABORT_INT_STATUS,Abort Interrupt Status. The DMA write channel has detected an error or you manually stopped the transfer as described in 'Error Handling Assistance by Remote Software'. Each bit corresponds to a DMA channel. Bit [0] corresponds to.." newline hexmask.long.byte 0x0 8.--15. 1. "RSVDP_8,Reserved for future use." hexmask.long.byte 0x0 0.--7. 1. "WR_DONE_INT_STATUS,Done Interrupt Status. The DMA write channel has successfully completed the DMA transfer. For more details see 'Interrupts and Error Handling'. Each bit corresponds to a DMA channel. Bit [0] corresponds to channel 0. - Enabling: For.." group.long (0x54+0xC8000)++0x7 line.long 0x0 "DMA_WRITE_INT_MASK_OFF,DMA Write Interrupt Mask Register." hexmask.long.byte 0x0 24.--31. 1. "RSVDP_24,Reserved for future use." hexmask.long.byte 0x0 16.--23. 1. "WR_ABORT_INT_MASK,Abort Interrupt Mask. Prevents the Abort interrupt status field in the DMA write interrupt status register from asserting the edma_int output. Each bit corresponds to a DMA channel. Bit [0] corresponds to channel 0. Note: The access.." newline hexmask.long.byte 0x0 8.--15. 1. "RSVDP_8,Reserved for future use." hexmask.long.byte 0x0 0.--7. 1. "WR_DONE_INT_MASK,Done Interrupt Mask. Prevents the Done interrupt status field in the DMA write interrupt status register from asserting the edma_int output. Each bit corresponds to a DMA channel. Bit [0] corresponds to channel 0. Note: The access.." line.long 0x4 "DMA_WRITE_INT_CLEAR_OFF,DMA Write Interrupt Clear Register." hexmask.long.byte 0x4 24.--31. 1. "RSVDP_24,Reserved for future use." hexmask.long.byte 0x4 16.--23. 1. "WR_ABORT_INT_CLEAR,Abort Interrupt Clear. You must write a 1'b1 to clear the corresponding bit in the Abort interrupt status field of the DMA write interrupt status register. Each bit corresponds to a DMA channel. Bit [0] corresponds to channel 0. Note:.." newline hexmask.long.byte 0x4 8.--15. 1. "RSVDP_8,Reserved for future use." hexmask.long.byte 0x4 0.--7. 1. "WR_DONE_INT_CLEAR,Done Interrupt Clear. You must write a 1'b1 to clear the corresponding bit in the Done interrupt status field of the DMA write interrupt status register. Each bit corresponds to a DMA channel. Bit [0] corresponds to channel 0. Note:.." rgroup.long (0x5C+0xC8000)++0x3 line.long 0x0 "DMA_WRITE_ERR_STATUS_OFF,DMA Write Error Status Register" hexmask.long.byte 0x0 24.--31. 1. "RSVDP_24,Reserved for future use." hexmask.long.byte 0x0 16.--23. 1. "LINKLIST_ELEMENT_FETCH_ERR_DETECT,Linked List Element Fetch Error Detected. The DMA write channel has received an error response from the AXI bus (or TRGT1 interface when the AXI Bridge is not used) while reading a linked list element from local memory." newline hexmask.long.byte 0x0 8.--15. 1. "RSVDP_8,Reserved for future use." hexmask.long.byte 0x0 0.--7. 1. "APP_READ_ERR_DETECT,Application Read Error Detected. The DMA write channel has received an error response from the AXI bus (or TRGT1 interface when the AXI Bridge is not used) while reading data from it. Each bit corresponds to a DMA channel. Bit [0].." group.long (0x60+0xC8000)++0x1F line.long 0x0 "DMA_WRITE_DONE_IMWR_LOW_OFF,DMA Write Done IMWr Address Low Register." hexmask.long 0x0 0.--31. 1. "DMA_WRITE_DONE_LOW_REG,The DMA uses this field to generate bits [31:0] of the address field for the Done IMWr TLP. Bits [1:0] must be '00' as this address must be dword aligned. Note: The access attributes of this field are as follows: - Wire: No access." line.long 0x4 "DMA_WRITE_DONE_IMWR_HIGH_OFF,DMA Write Done IMWr Interrupt Address High Register." hexmask.long 0x4 0.--31. 1. "DMA_WRITE_DONE_HIGH_REG,The DMA uses this field to generate bits [63:32] of the address field for the Done IMWr TLP. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" line.long 0x8 "DMA_WRITE_ABORT_IMWR_LOW_OFF,DMA Write Abort IMWr Address Low Register." hexmask.long 0x8 0.--31. 1. "DMA_WRITE_ABORT_LOW_REG,The DMA uses this field to generate bits [31:0] of the address field for the Abort IMWr TLP it generates. Bits [1:0] must be '00' as this address must be dword aligned. Note: The access attributes of this field are as follows: -.." line.long 0xC "DMA_WRITE_ABORT_IMWR_HIGH_OFF,DMA Write Abort IMWr Address High Register." hexmask.long 0xC 0.--31. 1. "DMA_WRITE_ABORT_HIGH_REG,The DMA uses this field to generate bits [63:32] of the address field for the Abort IMWr TLP. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" line.long 0x10 "DMA_WRITE_CH01_IMWR_DATA_OFF,DMA Write Channel 1 and 0 IMWr Data Register." hexmask.long.word 0x10 16.--31. 1. "WR_CHANNEL_1_DATA,The DMA uses this field to generate the data field for the Done or Abort IMWr TLPs it generates for write channel 1. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" hexmask.long.word 0x10 0.--15. 1. "WR_CHANNEL_0_DATA,The DMA uses this field to generate the data field for the Done or Abort IMWr TLPs it generates for write channel 0. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" line.long 0x14 "DMA_WRITE_CH23_IMWR_DATA_OFF,DMA Write Channel 3 and 2 IMWr Data Register." hexmask.long.word 0x14 16.--31. 1. "WR_CHANNEL_3_DATA,The DMA uses this field to generate the data field for the Done or Abort IMWr TLPs it generates for write channel 3. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" hexmask.long.word 0x14 0.--15. 1. "WR_CHANNEL_2_DATA,The DMA uses this field to generate the data field for the Done or Abort IMWr TLPs it generates for write channel 2. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" line.long 0x18 "DMA_WRITE_CH45_IMWR_DATA_OFF,DMA Write Channel 5 and 4 IMWr Data Register." hexmask.long.word 0x18 16.--31. 1. "WR_CHANNEL_5_DATA,The DMA uses this field to generate the data field for the Done or Abort IMWr TLPs it generates for write channel 5. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" hexmask.long.word 0x18 0.--15. 1. "WR_CHANNEL_4_DATA,The DMA uses this field to generate the data field for the Done or Abort IMWr TLPs it generates for write channel 4. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" line.long 0x1C "DMA_WRITE_CH67_IMWR_DATA_OFF,DMA Write Channel 7 and 6 IMWr Data Register." hexmask.long.word 0x1C 16.--31. 1. "WR_CHANNEL_7_DATA,The DMA uses this field to generate the data field for the Done or Abort IMWr TLPs it generates for write channel 7. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" hexmask.long.word 0x1C 0.--15. 1. "WR_CHANNEL_6_DATA,The DMA uses this field to generate the data field for the Done or Abort IMWr TLPs it generates for write channel 6. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" group.long (0x90+0xC8000)++0x3 line.long 0x0 "DMA_WRITE_LINKED_LIST_ERR_EN_OFF,DMA Write Linked List Error Enable Register. The LIE and RIE bits in the LL element enable the channel 'done' interrupts (local and remote). The LLLAIE and LLRAIE bits enable the channel 'abort' interrupts (local and.." hexmask.long.byte 0x0 24.--31. 1. "RSVDP_24,Reserved for future use." hexmask.long.byte 0x0 16.--23. 1. "WR_CHANNEL_LLLAIE,Write Channel LL Local Abort Interrupt Enable (LLLAIE). You enable the write channel local abort interrupt through this bit. The LIE and RIE bits in the LL element enable the write channel done interrupts. Each bit corresponds to a DMA.." newline hexmask.long.byte 0x0 8.--15. 1. "RSVDP_8,Reserved for future use." hexmask.long.byte 0x0 0.--7. 1. "WR_CHANNEL_LLRAIE,Write Channel LL Remote Abort Interrupt Enable (LLRAIE). You enable the write channel remote abort interrupt through this bit. The LIE and RIE bits in the LL element enable the write channel done interrupts. Each bit corresponds to a.." group.long (0xA0+0xC8000)++0x3 line.long 0x0 "DMA_READ_INT_STATUS_OFF,DMA Read Interrupt Status Register." hexmask.long.byte 0x0 24.--31. 1. "RSVDP_24,Reserved for future use." hexmask.long.byte 0x0 16.--23. 1. "RD_ABORT_INT_STATUS,Abort Interrupt Status. The DMA read channel has detected an error or you manually stopped the transfer as described in 'Stopping the DMA Transfer (Software Stop)'. Each bit corresponds to a DMA channel. Bit [0] corresponds to.." newline hexmask.long.byte 0x0 8.--15. 1. "RSVDP_8,Reserved for future use." hexmask.long.byte 0x0 0.--7. 1. "RD_DONE_INT_STATUS,Done Interrupt Status. The DMA read channel has successfully completed the DMA read transfer. Each bit corresponds to a DMA channel. Bit [0] corresponds to channel 0. - Enabling: For details see 'Interrupts and Error Handling'. -.." group.long (0xA8+0xC8000)++0x7 line.long 0x0 "DMA_READ_INT_MASK_OFF,DMA Read Interrupt Mask Register." hexmask.long.byte 0x0 24.--31. 1. "RSVDP_24,Reserved for future use." hexmask.long.byte 0x0 16.--23. 1. "RD_ABORT_INT_MASK,Abort Interrupt Mask. Prevents the Abort interrupt status field in the DMA read interrupt status register from asserting the edma_int output. Each bit corresponds to a DMA channel. Bit [0] corresponds to channel 0. Note: The access.." newline hexmask.long.byte 0x0 8.--15. 1. "RSVDP_8,Reserved for future use." hexmask.long.byte 0x0 0.--7. 1. "RD_DONE_INT_MASK,Done Interrupt Mask. Prevents the Done interrupt status field in the DMA read interrupt status register from asserting the edma_int output. Each bit corresponds to a DMA channel. Bit [0] corresponds to channel 0. Note: The access.." line.long 0x4 "DMA_READ_INT_CLEAR_OFF,DMA Read Interrupt Clear Register." hexmask.long.byte 0x4 24.--31. 1. "RSVDP_24,Reserved for future use." hexmask.long.byte 0x4 16.--23. 1. "RD_ABORT_INT_CLEAR,Abort Interrupt Clear. You must write a 1'b1 to clear the corresponding bit in the Abort interrupt status field of the DMA read interrupt status register. Each bit corresponds to a DMA channel. Bit [0] corresponds to channel 0. Note:.." newline hexmask.long.byte 0x4 8.--15. 1. "RSVDP_8,Reserved for future use." hexmask.long.byte 0x4 0.--7. 1. "RD_DONE_INT_CLEAR,Done Interrupt Clear. You must write a 1'b1 to clear the corresponding bit in the Done interrupt status field of the DMA read interrupt status register. Each bit corresponds to a DMA channel. Bit [0] corresponds to channel 0. Note:.." rgroup.long (0xB4+0xC8000)++0x7 line.long 0x0 "DMA_READ_ERR_STATUS_LOW_OFF,DMA Read Error Status Low Register." hexmask.long.byte 0x0 24.--31. 1. "RSVDP_24,Reserved for future use." hexmask.long.byte 0x0 16.--23. 1. "LINK_LIST_ELEMENT_FETCH_ERR_DETECT,Linked List Element Fetch Error Detected. - The DMA read channel has received an error response from the AXI bus while reading a linked list element from local memory. Each bit corresponds to a DMA channel. Bit [0].." newline hexmask.long.byte 0x0 8.--15. 1. "RSVDP_8,Reserved for future use." hexmask.long.byte 0x0 0.--7. 1. "APP_WR_ERR_DETECT,Application Write Error Detected. The DMA read channel has received an error response from the AXI bus (or TRGT1 interface when the AXI Bridge is not used) while writing data to it. This error is fatal. You must restart the transfer.." line.long 0x4 "DMA_READ_ERR_STATUS_HIGH_OFF,DMA Read Error Status High Register." hexmask.long.byte 0x4 24.--31. 1. "DATA_POISIONING,Data Poisoning. The DMA read channel has detected data poisoning in the completion from the remote device (in response to the MRd request). The DMA read channel will drop the completion and then be halted. The CX_FLT_MASK_UR_POIS filter.." hexmask.long.byte 0x4 16.--23. 1. "CPL_TIMEOUT,Completion Time Out. The DMA read channel has timed-out while waiting for the remote device to respond to the MRd request or a malformed CplD has been received. For more details see 'Linked List Mode'. Each bit corresponds to a DMA channel." newline hexmask.long.byte 0x4 8.--15. 1. "CPL_ABORT,Completer Abort. The DMA read channel has received a PCIe completer abort completion status from the remote device in response to the MRd request. For more details see 'Linked List Mode'. Each bit corresponds to a DMA channel. Bit [0].." hexmask.long.byte 0x4 0.--7. 1. "UNSUPPORTED_REQ,Unsupported Request. The DMA read channel has received a PCIe unsupported request completion status from the remote device in response to the MRd request. For more details see 'Linked List Mode'. Each bit corresponds to a DMA channel." group.long (0xC4+0xC8000)++0x3 line.long 0x0 "DMA_READ_LINKED_LIST_ERR_EN_OFF,DMA Read Linked List Error Enable Register. The LIE and RIE bits in the LL element enable the channel 'done' interrupts (local and remote). The LLLAIE and LLRAIE bits enable the channel 'abort' interrupts (local and remote)." hexmask.long.byte 0x0 24.--31. 1. "RSVDP_24,Reserved for future use." hexmask.long.byte 0x0 16.--23. 1. "RD_CHANNEL_LLLAIE,Read Channel LL Local Abort Interrupt Enable (LLLAIE). You enable the read channel Local Abort interrupt through this bit. The LIE and RIE bits in the LL element enable the read channel done interrupts. Each bit corresponds to a DMA.." newline hexmask.long.byte 0x0 8.--15. 1. "RSVDP_8,Reserved for future use." hexmask.long.byte 0x0 0.--7. 1. "RD_CHANNEL_LLRAIE,Read Channel LL Remote Abort Interrupt Enable (LLRAIE). You enable the read channel Remote Abort interrupt through this bit. The LIE and RIE bits in the LL element enable the read channel done interrupts. Each bit corresponds to a DMA.." group.long (0xCC+0xC8000)++0x1F line.long 0x0 "DMA_READ_DONE_IMWR_LOW_OFF,DMA Read Done IMWr Address Low Register." hexmask.long 0x0 0.--31. 1. "DMA_READ_DONE_LOW_REG,The DMA uses this field to generate bits [31:0] of the address field for the Done IMWr TLP. Bits [1:0] must be '00' as this address must be dword aligned. Note: The access attributes of this field are as follows: - Wire: No access." line.long 0x4 "DMA_READ_DONE_IMWR_HIGH_OFF,DMA Read Done IMWr Address High Register." hexmask.long 0x4 0.--31. 1. "DMA_READ_DONE_HIGH_REG,The DMA uses this field to generate bits [63:32] of the address field for the Done IMWr TLP. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" line.long 0x8 "DMA_READ_ABORT_IMWR_LOW_OFF,DMA Read Abort IMWr Address Low Register." hexmask.long 0x8 0.--31. 1. "DMA_READ_ABORT_LOW_REG,The DMA uses this field to generate bits [31:0] of the address field for the Abort IMWr TLP. Bits [1:0] must be '00' as this address must be dword aligned. Note: The access attributes of this field are as follows: - Wire: No.." line.long 0xC "DMA_READ_ABORT_IMWR_HIGH_OFF,DMA Read Abort IMWr Address High Register." hexmask.long 0xC 0.--31. 1. "DMA_READ_ABORT_HIGH_REG,The DMA uses this field to generate bits [63:32] of the address field for the Abort IMWr TLP. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" line.long 0x10 "DMA_READ_CH01_IMWR_DATA_OFF,DMA Read Channel 1 and 0 IMWr Data Register." hexmask.long.word 0x10 16.--31. 1. "RD_CHANNEL_1_DATA,The DMA uses this field to generate the data field for the Done or Abort IMWr TLPs it generates for read channel 1. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" hexmask.long.word 0x10 0.--15. 1. "RD_CHANNEL_0_DATA,The DMA uses this field to generate the data field for the Done or Abort IMWr TLPs it generates for read channel 0. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" line.long 0x14 "DMA_READ_CH23_IMWR_DATA_OFF,DMA Read Channel 3 and 2 IMWr Data Register." hexmask.long.word 0x14 16.--31. 1. "RD_CHANNEL_3_DATA,The DMA uses this field to generate the data field for the Done or Abort IMWr TLPs it generates for read channel 3. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" hexmask.long.word 0x14 0.--15. 1. "RD_CHANNEL_2_DATA,The DMA uses this field to generate the data field for the Done or Abort IMWr TLPs it generates for read channel 2. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" line.long 0x18 "DMA_READ_CH45_IMWR_DATA_OFF,DMA Read Channel 5 and 4 IMWr Data Register." hexmask.long.word 0x18 16.--31. 1. "RD_CHANNEL_5_DATA,The DMA uses this field to generate the data field for the Done or Abort IMWr TLPs it generates for read channel 5. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" hexmask.long.word 0x18 0.--15. 1. "RD_CHANNEL_4_DATA,The DMA uses this field to generate the data field for the Done or Abort IMWr TLPs it generates for read channel 4. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" line.long 0x1C "DMA_READ_CH67_IMWR_DATA_OFF,DMA Read Channel 7 and 6 IMWr Data Register." hexmask.long.word 0x1C 16.--31. 1. "RD_CHANNEL_7_DATA,The DMA uses this field to generate the data field for the Done or Abort IMWr TLPs it generates for read channel 7. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" hexmask.long.word 0x1C 0.--15. 1. "RD_CHANNEL_6_DATA,The DMA uses this field to generate the data field for the Done or Abort IMWr TLPs it generates for read channel 6. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" rgroup.long (0x108+0xC8000)++0x7 line.long 0x0 "DMA_WRITE_ENGINE_HSHAKE_CNT_LOW_OFF,DMA Write Engine Handshake Counter Channel 0/1/2/3 Register." bitfld.long 0x0 29.--31. "RSVDP_29,Reserved for future use." "0,1,2,3,4,5,6,7" hexmask.long.byte 0x0 24.--28. 1. "DMA_WRITE_ENGINE_HSHAKE_CNT_CH3,DMA handshake counter for DMA Write Engine Channel 3. If CC_DMA_HSHAKE =1 the data transfer in Linked List mode starts only when the counter is non-zero." newline bitfld.long 0x0 21.--23. "RSVDP_21,Reserved for future use." "0,1,2,3,4,5,6,7" hexmask.long.byte 0x0 16.--20. 1. "DMA_WRITE_ENGINE_HSHAKE_CNT_CH2,DMA handshake counter for DMA Write Engine Channel 2. If CC_DMA_HSHAKE =1 the data transfer in Linked List mode starts only when the counter is non-zero." newline bitfld.long 0x0 13.--15. "RSVDP_13,Reserved for future use." "0,1,2,3,4,5,6,7" hexmask.long.byte 0x0 8.--12. 1. "DMA_WRITE_ENGINE_HSHAKE_CNT_CH1,DMA handshake counter for DMA Write Engine Channel 1. If CC_DMA_HSHAKE =1 the data transfer in Linked List mode starts only when the counter is non-zero." newline bitfld.long 0x0 5.--7. "RSVDP_5,Reserved for future use." "0,1,2,3,4,5,6,7" hexmask.long.byte 0x0 0.--4. 1. "DMA_WRITE_ENGINE_HSHAKE_CNT_CH0,DMA handshake counter for DMA Write Engine Channel 0. If CC_DMA_HSHAKE =1 the data transfer in Linked List mode starts only when the counter is non-zero." line.long 0x4 "DMA_WRITE_ENGINE_HSHAKE_CNT_HIGH_OFF,DMA Write Engine Handshake Counter Channel 4/5/6/7 Register." bitfld.long 0x4 29.--31. "RSVDP_29,Reserved for future use." "0,1,2,3,4,5,6,7" hexmask.long.byte 0x4 24.--28. 1. "DMA_WRITE_ENGINE_HSHAKE_CNT_CH7,DMA handshake counter for DMA Write Engine Channel 7. If CC_DMA_HSHAKE =1 the data transfer in Linked List mode starts only when the counter is non-zero." newline bitfld.long 0x4 21.--23. "RSVDP_21,Reserved for future use." "0,1,2,3,4,5,6,7" hexmask.long.byte 0x4 16.--20. 1. "DMA_WRITE_ENGINE_HSHAKE_CNT_CH6,DMA handshake counter for DMA Write Engine Channel 6. If CC_DMA_HSHAKE =1 the data transfer in Linked List mode starts only when the counter is non-zero." newline bitfld.long 0x4 13.--15. "RSVDP_13,Reserved for future use." "0,1,2,3,4,5,6,7" hexmask.long.byte 0x4 8.--12. 1. "DMA_WRITE_ENGINE_HSHAKE_CNT_CH5,DMA handshake counter for DMA Write Engine Channel 5. If CC_DMA_HSHAKE =1 the data transfer in Linked List mode starts only when the counter is non-zero." newline bitfld.long 0x4 5.--7. "RSVDP_5,Reserved for future use." "0,1,2,3,4,5,6,7" hexmask.long.byte 0x4 0.--4. 1. "DMA_WRITE_ENGINE_HSHAKE_CNT_CH4,DMA handshake counter for DMA Write Engine Channel 4. If CC_DMA_HSHAKE =1 the data transfer in Linked List mode starts only when the counter is non-zero." rgroup.long (0x118+0xC8000)++0x7 line.long 0x0 "DMA_READ_ENGINE_HSHAKE_CNT_LOW_OFF,DMA Read Engine Handshake Counter Channel 0/1/2/3 Register." bitfld.long 0x0 29.--31. "RSVDP_29,Reserved for future use." "0,1,2,3,4,5,6,7" hexmask.long.byte 0x0 24.--28. 1. "DMA_READ_ENGINE_HSHAKE_CNT_CH3,DMA handshake counter for DMA Read Engine Channel 3. If CC_DMA_HSHAKE =1 the data transfer in Linked List mode starts only when the counter is non-zero." newline bitfld.long 0x0 21.--23. "RSVDP_21,Reserved for future use." "0,1,2,3,4,5,6,7" hexmask.long.byte 0x0 16.--20. 1. "DMA_READ_ENGINE_HSHAKE_CNT_CH2,DMA handshake counter for DMA Read Engine Channel 2. If CC_DMA_HSHAKE =1 the data transfer in Linked List mode starts only when the counter is non-zero." newline bitfld.long 0x0 13.--15. "RSVDP_13,Reserved for future use." "0,1,2,3,4,5,6,7" hexmask.long.byte 0x0 8.--12. 1. "DMA_READ_ENGINE_HSHAKE_CNT_CH1,DMA handshake counter for DMA Read Engine Channel 1. If CC_DMA_HSHAKE =1 the data transfer in Linked List mode starts only when the counter is non-zero." newline bitfld.long 0x0 5.--7. "RSVDP_5,Reserved for future use." "0,1,2,3,4,5,6,7" hexmask.long.byte 0x0 0.--4. 1. "DMA_READ_ENGINE_HSHAKE_CNT_CH0,DMA handshake counter for DMA Read Engine Channel 0. If CC_DMA_HSHAKE =1 the data transfer in Linked List mode starts only when the counter is non-zero." line.long 0x4 "DMA_READ_ENGINE_HSHAKE_CNT_HIGH_OFF,DMA Read Engine Handshake Counter Channel 4/5/6/7 Register." bitfld.long 0x4 29.--31. "RSVDP_29,Reserved for future use." "0,1,2,3,4,5,6,7" hexmask.long.byte 0x4 24.--28. 1. "DMA_READ_ENGINE_HSHAKE_CNT_CH7,DMA handshake counter for DMA Read Engine Channel 7. If CC_DMA_HSHAKE =1 the data transfer in Linked List mode starts only when the counter is non-zero." newline bitfld.long 0x4 21.--23. "RSVDP_21,Reserved for future use." "0,1,2,3,4,5,6,7" hexmask.long.byte 0x4 16.--20. 1. "DMA_READ_ENGINE_HSHAKE_CNT_CH6,DMA handshake counter for DMA Read Engine Channel 6. If CC_DMA_HSHAKE =1 the data transfer in Linked List mode starts only when the counter is non-zero." newline bitfld.long 0x4 13.--15. "RSVDP_13,Reserved for future use." "0,1,2,3,4,5,6,7" hexmask.long.byte 0x4 8.--12. 1. "DMA_READ_ENGINE_HSHAKE_CNT_CH5,DMA handshake counter for DMA Read Engine Channel 5. If CC_DMA_HSHAKE =1 the data transfer in Linked List mode starts only when the counter is non-zero." newline bitfld.long 0x4 5.--7. "RSVDP_5,Reserved for future use." "0,1,2,3,4,5,6,7" hexmask.long.byte 0x4 0.--4. 1. "DMA_READ_ENGINE_HSHAKE_CNT_CH4,DMA handshake counter for DMA Read Engine Channel 4. If CC_DMA_HSHAKE =1 the data transfer in Linked List mode starts only when the counter is non-zero." repeat 8. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 )(list 0x0 0x200 0x400 0x600 0x800 0xA00 0xC00 0xE00 ) group.long ($2+0x200+0xC8000)++0x3 line.long 0x0 "DMA_CH_CONTROL1_OFF_WRCH_$1,DMA Write Channel Control 1 Register." bitfld.long 0x0 30.--31. "DMA_AT,Address Translation TLP Header Bit (AT) The DMA uses this TLP header field when generating MRd/MWr (not IMWr) TLPs. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" "0,1,2,3" bitfld.long 0x0 27.--29. "DMA_TC,Traffic Class TLP Header Bit (TC) The DMA uses this TLP header field when generating MRd/MWr (not IMWr) TLPs. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 26. "DMA_RESERVED5,Reserved. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" "0,1" bitfld.long 0x0 25. "DMA_RO,Relaxed Ordering TLP Header Bit (RO) The DMA uses this TLP header field when generating MRd/MWr (not IMWr) TLPs. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" "0,1" newline bitfld.long 0x0 24. "DMA_NS_SRC,Source No Snoop TLP Header Bit (DMA_NS_SRC). The DMA uses this TLP header field when generating MRd (SAR addressing space) (not IMWr) TLPs. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" "0,1" bitfld.long 0x0 23. "DMA_NS_DST,Destination No Snoop TLP Header Bit (DMA_NS_DST). The DMA uses this TLP header field when generating MWr (DAR addressing space) (not IMWr) TLPs. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" "0,1" newline bitfld.long 0x0 22. "DMA_MEM_TYPE,Master AXI ACE-Lite Cache Coherency Control. This field sets the DMA channel memory type of the address space of the data transfer as follows: - 0x0:peripheral type - 0x1:memory type For more details see 'ACE-Lite Features and Limitations'.." "peripheral type,memory type" hexmask.long.byte 0x0 17.--21. 1. "DMA_RESERVED2,Reserved. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" newline hexmask.long.byte 0x0 12.--16. 1. "DMA_FUNC_NUM,Function Number (FN). The controller uses this field when generating the requester ID for the MRd/MWr DMA TLP. When you have enabled SR-IOV then this field is ignored if you have set the VFE field in the 'DMA Write Channel Control 2.." bitfld.long 0x0 10.--11. "DMA_RESERVED1,Reserved. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" "0,1,2,3" newline bitfld.long 0x0 9. "LLE,Linked List Enable (LLE). - 0: Disable linked list operation - 1: Enable linked list operation Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" "Disable linked list operation,Enable linked list operation" bitfld.long 0x0 8. "CCS,Consumer Cycle State (CCS). Used in linked list mode only. It is used to synchronize the producer (software) and the consumer (DMA). For more details see 'PCS-CCS-CB-TCB Producer-Consumer Synchronization'. You must initialize this bit. The DMA.." "0,1" newline bitfld.long 0x0 7. "DMA_RESERVED0,Reserved. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" "0,1" bitfld.long 0x0 5.--6. "CS,Channel Status (CS). The channel status bits identify the current operational state of the DMA channel. The operation state encoding for each DMA channel is a s follows: - 00: Reserved - 01: Running. This channel is active and transferring data. - 10:.." "Reserved,Running,?,?" newline bitfld.long 0x0 4. "RIE,Remote Interrupt Enable (RIE). You must set this bit to enable the generation of the Done or Abort Remote interrupts. For more details see 'Interrupts and Error Handling'. In LL mode the DMA overwrites this with the RIE of the LL element. The RIE.." "0,1" bitfld.long 0x0 3. "LIE,Local Interrupt Enable (LIE). You must set this bit to enable the generation of the Done or Abort Local interrupts. For more details see 'Interrupts and Error Handling'. In LL mode the DMA overwrites this with the LIE of the LL element. The LIE bit.." "0,1" newline bitfld.long 0x0 2. "LLP,Load Link Pointer (LLP). Used in linked list mode only. Indicates that this linked list element is a link element and its LL element pointer dwords are pointing to the next (non-contiguous) element. The DMA loads this field with the LLP of the.." "0,1" bitfld.long 0x0 1. "TCB,Toggle Cycle Bit (TCB). Indicates to the DMA to toggle its interpretation of the CB. Used in linked list mode only. It is used to synchronize the producer (software) and the consumer (DMA). For more details see 'PCS-CCS-CB-TCB Producer-Consumer.." "0,1" newline bitfld.long 0x0 0. "CB,Cycle Bit (CB). Used in linked list mode only. It is used to synchronize the producer (software) and the consumer (DMA). For more details see 'PCS-CCS-CB-TCB Producer-Consumer Synchronization'. The DMA loads this field with the CB of the linked list.." "0,1" repeat.end repeat 8. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 )(list 0x0 0x200 0x400 0x600 0x800 0xA00 0xC00 0xE00 ) group.long ($2+0x208+0xC8000)++0x3 line.long 0x0 "DMA_TRANSFER_SIZE_OFF_WRCH_$1,DMA Write Transfer Size Register." hexmask.long 0x0 0.--31. 1. "DMA_TRANSFER_SIZE,DMA Transfer Size. You program this register with the size of the DMA transfer. The maximum DMA transfer size is 4Gbytes. The minimum transfer size is one byte (0x1). This field is automatically decremented by the DMA as the DMA write.." repeat.end repeat 8. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 )(list 0x0 0x200 0x400 0x600 0x800 0xA00 0xC00 0xE00 ) group.long ($2+0x20C+0xC8000)++0x3 line.long 0x0 "DMA_SAR_LOW_OFF_WRCH_$1,DMA Write SAR Low Register." hexmask.long 0x0 0.--31. 1. "SRC_ADDR_REG_LOW,Source Address Register (Lower 32 bits). Indicates the next address to be read from. The DMA increments the SAR as the DMA transfer progresses. In LL mode the DMA overwrites this with the corresponding dword of the LL element. - DMA.." repeat.end repeat 8. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 )(list 0x0 0x200 0x400 0x600 0x800 0xA00 0xC00 0xE00 ) group.long ($2+0x210+0xC8000)++0x3 line.long 0x0 "DMA_SAR_HIGH_OFF_WRCH_$1,DMA Write SAR High Register." hexmask.long 0x0 0.--31. 1. "SRC_ADDR_REG_HIGH,Source Address Register (Higher 32 bits). In LL mode the DMA overwrites this with the corresponding dword of the LL element. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" repeat.end repeat 8. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 )(list 0x0 0x200 0x400 0x600 0x800 0xA00 0xC00 0xE00 ) group.long ($2+0x214+0xC8000)++0x3 line.long 0x0 "DMA_DAR_LOW_OFF_WRCH_$1,DMA Write DAR Low Register." hexmask.long 0x0 0.--31. 1. "DST_ADDR_REG_LOW,Destination Address Register (Lower 32 bits). Indicates the next address to be written to. The DMA increments the DAR as the DMA transfer progresses. In LL mode the DMA overwrites this with the corresponding dword of the LL element. -.." repeat.end repeat 8. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 )(list 0x0 0x200 0x400 0x600 0x800 0xA00 0xC00 0xE00 ) group.long ($2+0x218+0xC8000)++0x3 line.long 0x0 "DMA_DAR_HIGH_OFF_WRCH_$1,DMA Write DAR High Register." hexmask.long 0x0 0.--31. 1. "DST_ADDR_REG_HIGH,Destination Address Register (Higher 32 bits). In LL mode the DMA overwrites this with the corresponding dword of the LL element. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" repeat.end repeat 8. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 )(list 0x0 0x200 0x400 0x600 0x800 0xA00 0xC00 0xE00 ) group.long ($2+0x21C+0xC8000)++0x3 line.long 0x0 "DMA_LLP_LOW_OFF_WRCH_$1,DMA Write Linked List Pointer Low Register." hexmask.long 0x0 0.--31. 1. "LLP_LOW,Lower bits of the address of the linked list transfer list in local memory. Used in linked list mode only. Updated by the DMA to point to the next element in the transfer list after the previous element is consumed. - When the current element is.." repeat.end repeat 8. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 )(list 0x0 0x200 0x400 0x600 0x800 0xA00 0xC00 0xE00 ) group.long ($2+0x220+0xC8000)++0x3 line.long 0x0 "DMA_LLP_HIGH_OFF_WRCH_$1,DMA Write Linked List Pointer High Register." hexmask.long 0x0 0.--31. 1. "LLP_HIGH,Upper 32 bits of the address of the linked list transfer list in local memory. Used in linked list mode only. Updated by the DMA to point to the next element in the transfer list as elements are consumed. Note: The access attributes of this.." repeat.end repeat 8. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 )(list 0x0 0x200 0x400 0x600 0x800 0xA00 0xC00 0xE00 ) group.long ($2+0x300+0xC8000)++0x3 line.long 0x0 "DMA_CH_CONTROL1_OFF_RDCH_$1,DMA Read Channel Control 1 Register." bitfld.long 0x0 30.--31. "DMA_AT,Address Translation TLP Header Bit (AT) The DMA uses this TLP header field when generating MRd/MWr (not IMWr) TLPs. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" "0,1,2,3" bitfld.long 0x0 27.--29. "DMA_TC,Traffic Class TLP Header Bit (TC) The DMA uses this TLP header field when generating MRd/MWr (not IMWr) TLPs. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 26. "DMA_RESERVED5,Reserved. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" "0,1" bitfld.long 0x0 25. "DMA_RO,Relaxed Ordering TLP Header Bit (RO) The DMA uses this TLP header field when generating MRd/MWr (not IMWr) TLPs. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" "0,1" newline bitfld.long 0x0 24. "DMA_NS_SRC,Source No Snoop TLP Header Bit (DMA_NS_SRC). The DMA uses this TLP header field when generating MRd (SAR addressing space) (not IMWr) TLPs. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" "0,1" bitfld.long 0x0 23. "DMA_NS_DST,Destination No Snoop TLP Header Bit (DMA_NS_DST). The DMA uses this TLP header field when generating MWr (DAR addressing space) (not IMWr) TLPs. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" "0,1" newline bitfld.long 0x0 22. "DMA_MEM_TYPE,Master AXI ACE-Lite Cache Coherency Control. This field sets the DMA channel memory type of the address space of the data transfer as follows: - 0x0:peripheral type - 0x1:memory type For more details see 'ACE-Lite Features and Limitations'.." "peripheral type,memory type" hexmask.long.byte 0x0 17.--21. 1. "DMA_RESERVED2,Reserved. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" newline hexmask.long.byte 0x0 12.--16. 1. "DMA_FUNC_NUM,Function Number (FN). The controller uses this field when generating the requester ID for the MRd/MWr DMA TLP. When you have enabled SR-IOV then this field is ignored if you have set the VFE field in the 'DMA Read Channel Control 2.." bitfld.long 0x0 10.--11. "DMA_RESERVED1,Reserved. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" "0,1,2,3" newline bitfld.long 0x0 9. "LLE,Linked List Enable (LLE). - 0: Disable linked list operation - 1: Enable linked list operation Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" "Disable linked list operation,Enable linked list operation" bitfld.long 0x0 8. "CCS,Consumer Cycle State (CCS). Used in linked list mode only. It is used to synchronize the producer (software) and the consumer (DMA). For more details see 'PCS-CCS-CB-TCB Producer-Consumer Synchronization'. You must initialize this bit. The DMA.." "0,1" newline bitfld.long 0x0 7. "DMA_RESERVED0,Reserved. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" "0,1" bitfld.long 0x0 5.--6. "CS,Channel Status (CS). The channel status bits identify the current operational state of the DMA channel. The operation state encoding for each DMA channel is a s follows: - 00: Reserved - 01: Running. This channel is active and transferring data. - 10:.." "Reserved,Running,?,?" newline bitfld.long 0x0 4. "RIE,Remote Interrupt Enable (RIE). You must set this bit to enable the generation of the Done or Abort Remote interrupts. For more details see 'Interrupts and Error Handling'. In LL mode the DMA overwrites this with the RIE of the LL element. The RIE.." "0,1" bitfld.long 0x0 3. "LIE,Local Interrupt Enable (LIE). You must set this bit to enable the generation of the Done or Abort Local interrupts. For more details see 'Interrupts and Error Handling'. In LL mode the DMA overwrites this with the LIE of the LL element. The LIE bit.." "0,1" newline bitfld.long 0x0 2. "LLP,Load Link Pointer (LLP). Used in linked list mode only. Indicates that this linked list element is a link element and its LL element pointer dwords are pointing to the next (non-contiguous) element. The DMA loads this field with the LLP of the.." "0,1" bitfld.long 0x0 1. "TCB,Toggle Cycle Bit (TCB). Indicates to the DMA to toggle its interpretation of the CB. Used in linked list mode only. It is used to synchronize the producer (software) and the consumer (DMA). For more details see 'PCS-CCS-CB-TCB Producer-Consumer.." "0,1" newline bitfld.long 0x0 0. "CB,Cycle Bit (CB). Used in linked list mode only. It is used to synchronize the producer (software) and the consumer (DMA). For more details see 'PCS-CCS-CB-TCB Producer-Consumer Synchronization'. The DMA loads this field with the CB of the linked list.." "0,1" repeat.end repeat 8. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 )(list 0x0 0x200 0x400 0x600 0x800 0xA00 0xC00 0xE00 ) group.long ($2+0x308+0xC8000)++0x3 line.long 0x0 "DMA_TRANSFER_SIZE_OFF_RDCH_$1,DMA Read Transfer Size Register." hexmask.long 0x0 0.--31. 1. "DMA_TRANSFER_SIZE,DMA Transfer Size. You program this register with the size of the DMA transfer. The maximum DMA transfer size is 4Gbytes. The minimum transfer size is one byte (0x1). This field is automatically decremented by the DMA as the DMA read.." repeat.end repeat 8. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 )(list 0x0 0x200 0x400 0x600 0x800 0xA00 0xC00 0xE00 ) group.long ($2+0x30C+0xC8000)++0x3 line.long 0x0 "DMA_SAR_LOW_OFF_RDCH_$1,DMA Read SAR Low Register." hexmask.long 0x0 0.--31. 1. "SRC_ADDR_REG_LOW,Source Address Register (Lower 32 bits). Indicates the next address to be read from. The DMA increments the SAR as the DMA transfer progresses. In LL mode the DMA overwrites this with the corresponding dword of the LL element. - DMA.." repeat.end repeat 8. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 )(list 0x0 0x200 0x400 0x600 0x800 0xA00 0xC00 0xE00 ) group.long ($2+0x310+0xC8000)++0x3 line.long 0x0 "DMA_SAR_HIGH_OFF_RDCH_$1,DMA Read SAR High Register." hexmask.long 0x0 0.--31. 1. "SRC_ADDR_REG_HIGH,Source Address Register (Higher 32 bits). In LL mode the DMA overwrites this with the corresponding dword of the LL element. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" repeat.end repeat 8. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 )(list 0x0 0x200 0x400 0x600 0x800 0xA00 0xC00 0xE00 ) group.long ($2+0x314+0xC8000)++0x3 line.long 0x0 "DMA_DAR_LOW_OFF_RDCH_$1,DMA Read DAR Low Register." hexmask.long 0x0 0.--31. 1. "DST_ADDR_REG_LOW,Destination Address Register (Lower 32 bits). Indicates the next address to be written to. The DMA increments the DAR as the DMA transfer progresses. In LL mode the DMA overwrites this with the corresponding dword of the LL element. -.." repeat.end repeat 8. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 )(list 0x0 0x200 0x400 0x600 0x800 0xA00 0xC00 0xE00 ) group.long ($2+0x318+0xC8000)++0x3 line.long 0x0 "DMA_DAR_HIGH_OFF_RDCH_$1,DMA Read DAR High Register." hexmask.long 0x0 0.--31. 1. "DST_ADDR_REG_HIGH,Destination Address Register (Higher 32 bits). In LL mode the DMA overwrites this with the corresponding dword of the LL element. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" repeat.end repeat 8. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 )(list 0x0 0x200 0x400 0x600 0x800 0xA00 0xC00 0xE00 ) group.long ($2+0x31C+0xC8000)++0x3 line.long 0x0 "DMA_LLP_LOW_OFF_RDCH_$1,DMA Read Linked List Pointer Low Register." hexmask.long 0x0 0.--31. 1. "LLP_LOW,Lower bits of the address of the linked list transfer list in local memory. Used in linked list mode only. Updated by the DMA to point to the next element in the transfer list after the previous element is consumed. - When the current element is.." repeat.end repeat 8. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 )(list 0x0 0x200 0x400 0x600 0x800 0xA00 0xC00 0xE00 ) group.long ($2+0x320+0xC8000)++0x3 line.long 0x0 "DMA_LLP_HIGH_OFF_RDCH_$1,DMA Read Linked List Pointer High Register." hexmask.long 0x0 0.--31. 1. "LLP_HIGH,Upper 32 bits of the address of the linked list transfer list in local memory. Used in linked list mode only. Updated by the DMA to point to the next element in the transfer list as elements are consumed. Note: The access attributes of this.." repeat.end tree.end tree "PF0_ATU_CAP (ATU Por Logic Structure)" repeat 8. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 )(list 0x0 0x200 0x400 0x600 0x800 0xA00 0xC00 0xE00 ) group.long ($2+0xC0000)++0x3 line.long 0x0 "IATU_REGION_CTRL_1_OFF_OUTBOUND_$1,iATU Region Control 1 Register." bitfld.long 0x0 20. "CTRL_1_FUNC_NUM,Function Number. - When the address of an outbound TLP is matched to this region and the FUNC_BYPASS field in the 'iATU Control 2 Register' is '0' then the function number used in generating the function part of the requester ID (RID).." "0,1" newline bitfld.long 0x0 13. "INCREASE_REGION_SIZE,Increase the maximum ATU Region size. When set the maximum ATU Region size is determined by CX_ATU_MAX_REGION_SIZE. When clear the maximum ATU Region size is 4 GB (default). Note: This register field is sticky." "0,1" newline bitfld.long 0x0 9.--10. "ATTR,When the address of an outbound TLP is matched to this region then the ATTR field of the TLP is changed to the value in this register. Note: This register field is sticky." "0,1,2,3" newline bitfld.long 0x0 8. "TD,This is a reserved field. Do not use. Note: This register field is sticky." "0,1" newline bitfld.long 0x0 5.--7. "TC,When the address of an outbound TLP is matched to this region then the TC field of the TLP is changed to the value in this register. Note: This register field is sticky." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x0 0.--4. 1. "TYPE,When the address of an outbound TLP is matched to this region then the TYPE field of the TLP is changed to the value in this register. Note: This register field is sticky." repeat.end repeat 8. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 )(list 0x0 0x200 0x400 0x600 0x800 0xA00 0xC00 0xE00 ) group.long ($2+0x4+0xC0000)++0x3 line.long 0x0 "IATU_REGION_CTRL_2_OFF_OUTBOUND_$1,iATU Region Control 2 Register." bitfld.long 0x0 31. "REGION_EN,Region Enable. This bit must be set to '1' for address translation to take place. Note: This register field is sticky." "0,1" newline bitfld.long 0x0 29. "INVERT_MODE,Invert Mode. When set the address matching region is inverted. Therefore an address match occurs when the untranslated address is in the region outside the defined range (Base Address to Limit Address). Note: This register field is sticky." "0,1" newline bitfld.long 0x0 28. "CFG_SHIFT_MODE,CFG Shift Mode. The iATU uses bits [27:12] of the untranslated address (on the XALI0/1/2 interface or AXI slave interface address) to form the BDF number of the outgoing CFG TLP. This supports the Enhanced Configuration Address Mapping.." "0,1" newline bitfld.long 0x0 27. "DMA_BYPASS,DMA Bypass Mode. Allows request TLPs which are initiated by the DMA controller to pass through the iATU untranslated. Note: This field is reserved for the SW product. You must set it to '0'. Note: This register field is sticky." "0,1" newline bitfld.long 0x0 23. "HEADER_SUBSTITUTE_EN,Header Substitute Enable. When enabled and region address is matched the iATU fully substitutes bytes 8-11 (for 3 DWORD header) or bytes 12-15 (for 4 DWORD header) of the outbound TLP header with the contents of the LWR_TARGET_RW.." "LWR_TARGET_RW in the..,LWR_TARGET_RW in the.." newline bitfld.long 0x0 22. "INHIBIT_PAYLOAD,Inhibit TLP Payload Data for TLP's in Matched Region; assign iATU region to be TLP without data. When enabled and region address is matched the iATU marks all TLPs as having no payload data by forcing the TLP header Fmt[1] bit =0.." "Fmt[1] =0/1 so that TLPs with or without data..,Fmt[1] =0 so that only TLP type without data is.." newline bitfld.long 0x0 21. "TLP_HEADER_FIELDS_BYPASS,TLP Header Fields Translation Bypass. In this mode header fields of the translated TLP is taken from your application transmit interface or if AMBA is configured from the AMBA sideband bus (slv_awmisc_info) and not from the.." "0,1" newline bitfld.long 0x0 20. "SNP,Serialize Non-Posted Requests. In this mode when the AXI Bridge is populated same AXI ID Non-Posted Read/Write Requests are transmitted on the wire if there are no other same ID Non-Posted Requests outstanding. Note: This register field is sticky." "0,1" newline bitfld.long 0x0 19. "FUNC_BYPASS,Function Number Translation Bypass. In this mode the function number of the translated TLP is taken from your application transmit interface and not from the CTRL_1_FUNC_NUM field of the 'iATU Control 1 Register' or the VF_NUMBER field of.." "0,1" newline bitfld.long 0x0 16. "TAG_SUBSTITUTE_EN,TAG Substitute Enable. When enabled and region address is matched the iATU substitutes the TAG field of the outbound TLP header with the contents of the TAG field in this register. The expected usage scenario is translation from AXI.." "0,1" newline hexmask.long.byte 0x0 8.--15. 1. "TAG,TAG. The substituted TAG field (byte 6) in the outgoing TLP header when TAG_SUBSTITUTE_EN is set. Note: This register field is sticky." newline hexmask.long.byte 0x0 0.--7. 1. "MSG_CODE,MSG TLPs (Message Code). When the address of an outbound TLP is matched to this region and the translated TLP TYPE field is Msg or MsgD; then the message field of the TLP is changed to the value in this register. Memory TLPs: (ST;Steering Tag)." repeat.end repeat 8. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 )(list 0x0 0x200 0x400 0x600 0x800 0xA00 0xC00 0xE00 ) group.long ($2+0x8+0xC0000)++0x3 line.long 0x0 "IATU_LWR_BASE_ADDR_OFF_OUTBOUND_$1,iATU Lower Base Address Register. The CX_ATU_MIN_REGION_SIZE configuration parameter (Value Range: 4 kB. 8 kB. 16 kB. 32 kB. 64 kB defaults to 64 kB) specifies the minimum size of an address translation region. For.." hexmask.long.tbyte 0x0 12.--31. 1. "LWR_BASE_RW,Forms bits [31:n] of the start address of the address region to be translated. n is log2(CX_ATU_MIN_REGION_SIZE) Note: This register field is sticky." newline hexmask.long.word 0x0 0.--11. 1. "LWR_BASE_HW,Forms bits [n-1:0] of the start address of the address region to be translated. The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary so these bits are always 0. A write to this location is ignored by the PCIe controller." repeat.end repeat 8. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 )(list 0x0 0x200 0x400 0x600 0x800 0xA00 0xC00 0xE00 ) group.long ($2+0xC+0xC0000)++0x3 line.long 0x0 "IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_$1,iATU Upper Base Address Register." hexmask.long 0x0 0.--31. 1. "UPPER_BASE_RW,Forms bits [63:32] of the start (and end) address of the address region to be translated. In systems with a 32-bit address space this register is not used and therefore writing to this register has no effect. Note: This register field is.." repeat.end repeat 8. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 )(list 0x0 0x200 0x400 0x600 0x800 0xA00 0xC00 0xE00 ) group.long ($2+0x10+0xC0000)++0x3 line.long 0x0 "IATU_LIMIT_ADDR_OFF_OUTBOUND_$1,iATU Limit Address Register." hexmask.long.tbyte 0x0 12.--31. 1. "LIMIT_ADDR_RW,Forms upper bits of the end address of the address region to be translated. Note: This register field is sticky." newline hexmask.long.word 0x0 0.--11. 1. "LIMIT_ADDR_HW,Forms lower bits of the end address of the address region to be translated. The end address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary so these bits are always all ones. A write to this location is ignored by the PCIe.." repeat.end repeat 8. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 )(list 0x0 0x200 0x400 0x600 0x800 0xA00 0xC00 0xE00 ) group.long ($2+0x14+0xC0000)++0x3 line.long 0x0 "IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_$1,iATU Lower Target Address Register." hexmask.long 0x0 0.--31. 1. "LWR_TARGET_RW_OUTBOUND,When HEADER_SUBSTITUTE_EN in IATU_REGION_CTRL_2_OFF_OUTBOUND_ is '0' (normal operation): - LWR_TARGET_RW[31:n] forms MSB's of the Lower Target part of the new address of the translated region; - LWR_TARGET_RW[n-1:0] are not used." repeat.end repeat 8. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 )(list 0x0 0x200 0x400 0x600 0x800 0xA00 0xC00 0xE00 ) group.long ($2+0x18+0xC0000)++0x3 line.long 0x0 "IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_$1,iATU Upper Target Address Register." hexmask.long 0x0 0.--31. 1. "UPPER_TARGET_RW,Forms bits [63:32] of the start address (Upper Target part) of the new address of the translated region. Note: This register field is sticky." repeat.end repeat 8. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 )(list 0x0 0x200 0x400 0x600 0x800 0xA00 0xC00 0xE00 ) group.long ($2+0x1C+0xC0000)++0x3 line.long 0x0 "IATU_REGION_CTRL_3_OFF_OUTBOUND_$1,iATU Region Control 3 Register." bitfld.long 0x0 31. "VF_ACTIVE,Virtual Function Active. Indicates that all of the outbound accesses are from virtual functions. For more details see VF_ACTIVE field. Note: This register field is sticky." "0,1" newline hexmask.long 0x0 3.--30. 1. "RSVDP_VF_NUMBER,Reserved for future use." newline bitfld.long 0x0 0.--2. "VF_NUMBER,Virtual Function Number. When the address of an outbound TLP is matched to this region and the FUNC_BYPASS field in the 'iATU Control 2 Register' is '0' then this field used in generating the Function part of the requester ID (RID) field of.." "0,1,2,3,4,5,6,7" repeat.end repeat 8. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 )(list 0x0 0x200 0x400 0x600 0x800 0xA00 0xC00 0xE00 ) group.long ($2+0x100+0xC0000)++0x3 line.long 0x0 "IATU_REGION_CTRL_1_OFF_INBOUND_$1,iATU Region Control 1 Register." bitfld.long 0x0 20. "CTRL_1_FUNC_NUM,Function Number. - MEM-I/O: When the Address and BAR matching logic in the controller indicate that a MEM-I/O transaction matches a BAR in the function corresponding to this value then address translation proceeds. This check is only.." "?,When the destination function number as.." newline bitfld.long 0x0 13. "INCREASE_REGION_SIZE,Increase the maximum ATU Region size. When set the maximum ATU Region size is determined by CX_ATU_MAX_REGION_SIZE. When clear the maximum ATU Region size is 4 GB (default). Note: This register field is sticky." "0,1" newline bitfld.long 0x0 9.--10. "ATTR,When the ATTR field of an inbound TLP is matched to this value then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the 'ATTR Match Enable' bit of the 'iATU Control 2 Register' is.." "0,1,2,3" newline bitfld.long 0x0 8. "TD,When the TD field of an inbound TLP is matched to this value then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the 'TD Match Enable' bit of the 'iATU Control 2 Register' is set." "0,1" newline bitfld.long 0x0 5.--7. "TC,When the TC field of an inbound TLP is matched to this value then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the 'TC Match Enable' bit of the 'iATU Control 2 Register' is set." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x0 0.--4. 1. "TYPE,When the TYPE field of an inbound TLP is matched to this value then address translation proceeds (when all other enabled field-matches are successful). Note: This register field is sticky." repeat.end repeat 8. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 )(list 0x0 0x200 0x400 0x600 0x800 0xA00 0xC00 0xE00 ) group.long ($2+0x104+0xC0000)++0x3 line.long 0x0 "IATU_REGION_CTRL_2_OFF_INBOUND_$1,iATU Region Control 2 Register." bitfld.long 0x0 31. "REGION_EN,Region Enable. This bit must be set to '1' for address translation to take place. Note: This register field is sticky." "0,1" newline bitfld.long 0x0 30. "MATCH_MODE,Match Mode. Determines Inbound matching mode for TLPs. The mode depends on the type of TLP that is received as follows: For MEM-I/O TLPs this field is interpreted as follows: - 0: Address Match Mode. The iATU operates using addresses as in.." "Address Match Mode,Vendor ID Match Mode" newline bitfld.long 0x0 29. "INVERT_MODE,Invert Mode. When set the address matching region is inverted. Therefore an address match occurs when the untranslated address is in the region outside the defined range (Base Address to Limit Address). Note: This register field is sticky." "0,1" newline bitfld.long 0x0 28. "CFG_SHIFT_MODE,CFG Shift Mode. This is useful for CFG transactions where the PCIe configuration mechanism maps bits [27:12] of the address to the bus/device and function number. This allows a CFG configuration space to be located in any 256MB window of.." "0,1" newline bitfld.long 0x0 27. "FUZZY_TYPE_MATCH_CODE,Fuzzy Type Match Mode. When enabled the iATU relaxes the matching of the TLP TYPE field against the expected TYPE field so that - CfgRd0 and CfgRd1 TLPs are seen as identical. Similarly with CfgWr0 and CfgWr1. - MWr MRd and MRdLk.." "0,1" newline bitfld.long 0x0 26. "VFBAR_MATCH_MODE_EN,VF BAR Match Mode enable. When set Virtual Function BAR matching is used which allows all VFs in a PF which match a BAR to be matched with a single ATU region. Note: This register field is sticky." "0,1" newline bitfld.long 0x0 24.--25. "RESPONSE_CODE,Response Code. Defines the type of response to give for accesses matching this region. This overrides the normal RADM filter response. Note that this feature is not available for any region where Single Address Location Translate is.." "Normal RADM filter response is used,Unsupported request,?,?" newline bitfld.long 0x0 23. "SINGLE_ADDR_LOC_TRANS_EN,Single Address Location Translate Enable. When enabled Rx TLPs can be translated to a single address location as determined by the target address register of the iATU region. The main usage scenario is translation of Messages.." "0,1" newline bitfld.long 0x0 21. "MSG_CODE_MATCH_EN,Message Code Match Enable (Msg TLPS). Ensures that a successful message Code TLP field comparison match (see Message Code field of the 'iATU Control 2 Register') occurs (in MSG transactions) for address translation to proceed. ST Match.." "0,1" newline bitfld.long 0x0 20. "VF_MATCH_EN,Virtual Function Number Match Enable. Ensures that a successful Virtual Function Number TLP field comparison match (see Virtual Function Number field of the 'iATU Control 3 Register') occurs (in MEM-I/O transactions) for address translation.." "0,1" newline bitfld.long 0x0 19. "FUNC_NUM_MATCH_EN,Function Number Match Enable. Ensures that a successful Function Number TLP field comparison match (see Function Number field of the 'iATU Control 1 Register') occurs (in MEM-I/O and CFG0/CFG1 transactions) for address translation to.." "0,1" newline bitfld.long 0x0 16. "ATTR_MATCH_EN,ATTR Match Enable. Ensures that a successful ATTR TLP field comparison match (see ATTR field of the 'iATU Control 1 Register') occurs for address translation to proceed. Note: This register field is sticky." "0,1" newline bitfld.long 0x0 15. "TD_MATCH_EN,TD Match Enable. Ensures that a successful TD TLP field comparison match (see TD field of the 'iATU Control 1 Register') occurs for address translation to proceed. Note: This register field is sticky." "0,1" newline bitfld.long 0x0 14. "TC_MATCH_EN,TC Match Enable. Ensures that a successful TC TLP field comparison match (see TC field of the 'iATU Control 1 Register') occurs for address translation to proceed. Note: This register field is sticky." "0,1" newline bitfld.long 0x0 13. "MSG_TYPE_MATCH_MODE,Message Type Match Mode. When enabled and if single address location translate enable is set then inbound TLPs of type MSG/MSGd which match the type field of the iatu_region_ctrl_1_OFF_inbound register (=>TYPE[4:3]=2'b10) will be.." "0,1" newline bitfld.long 0x0 8.--10. "BAR_NUM,BAR Number. When the BAR number of an inbound MEM or IO TLP ' that is matched by the normal internal BAR address matching mechanism ' is the same as this field address translation proceeds (when all other enabled field-matches are successful)." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x0 0.--7. 1. "MSG_CODE,MSG TLPs: (Message Code). When the TYPE field of an inbound Msg/MsgD TLP is matched to this value then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the 'Message Code Match.." repeat.end repeat 8. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 )(list 0x0 0x200 0x400 0x600 0x800 0xA00 0xC00 0xE00 ) group.long ($2+0x108+0xC0000)++0x3 line.long 0x0 "IATU_LWR_BASE_ADDR_OFF_INBOUND_$1,iATU Lower Base Address Register. The CX_ATU_MIN_REGION_SIZE configuration parameter (Value Range: 4 kB. 8 kB. 16 kB. 32 kB. 64 kB defaults to 64 kB) specifies the minimum size of an address translation region. For.." hexmask.long.tbyte 0x0 12.--31. 1. "LWR_BASE_RW,Forms bits [31:n] of the start address of the address region to be translated. n is log2(CX_ATU_MIN_REGION_SIZE) Note: This register field is sticky." newline hexmask.long.word 0x0 0.--11. 1. "LWR_BASE_HW,Forms bits [n-1:0] of the start address of the address region to be translated. The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary so these bits are always 0. A write to this location is ignored by the PCIe controller." repeat.end repeat 8. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 )(list 0x0 0x200 0x400 0x600 0x800 0xA00 0xC00 0xE00 ) group.long ($2+0x10C+0xC0000)++0x3 line.long 0x0 "IATU_UPPER_BASE_ADDR_OFF_INBOUND_$1,iATU Upper Base Address Register." hexmask.long 0x0 0.--31. 1. "UPPER_BASE_RW,Forms bits [63:32] of the start (and end) address of the address region to be translated. Note: This register field is sticky." repeat.end repeat 8. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 )(list 0x0 0x200 0x400 0x600 0x800 0xA00 0xC00 0xE00 ) group.long ($2+0x110+0xC0000)++0x3 line.long 0x0 "IATU_LIMIT_ADDR_OFF_INBOUND_$1,iATU Limit Address Register." hexmask.long.tbyte 0x0 12.--31. 1. "LIMIT_ADDR_RW,Forms upper bits of the end address of the address region to be translated. Note: This register field is sticky." newline hexmask.long.word 0x0 0.--11. 1. "LIMIT_ADDR_HW,Forms lower bits of the end address of the address region to be translated. The end address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary so these bits are always all ones. A write to this location is ignored by the PCIe.." repeat.end repeat 8. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 )(list 0x0 0x200 0x400 0x600 0x800 0xA00 0xC00 0xE00 ) group.long ($2+0x114+0xC0000)++0x3 line.long 0x0 "IATU_LWR_TARGET_ADDR_OFF_INBOUND_$1,iATU Lower Target Address Register." hexmask.long.tbyte 0x0 12.--31. 1. "LWR_TARGET_RW,Forms MSB's of the Lower Target part of the new address of the translated region. These bits are always '0'. - Field size depends on log2(CX_ATU_MIN_REGION_SIZE) in address match mode. - Field size depends on log2(BAR_MASK+1) in BAR match.." newline hexmask.long.word 0x0 0.--11. 1. "LWR_TARGET_HW,Forms the LSB's of the Lower Target part of the new address of the translated region. The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary (in address match mode); and to the Bar size boundary (in BAR match mode) so.." repeat.end repeat 8. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 )(list 0x0 0x200 0x400 0x600 0x800 0xA00 0xC00 0xE00 ) group.long ($2+0x118+0xC0000)++0x3 line.long 0x0 "IATU_UPPER_TARGET_ADDR_OFF_INBOUND_$1,iATU Upper Target Address Register." hexmask.long 0x0 0.--31. 1. "UPPER_TARGET_RW,Forms bits [63:32] of the start address (Upper Target part) of the new address of the translated region. In systems with a 32-bit address space this register is not used and therefore writing to this register has no effect. Note: This.." repeat.end repeat 8. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 )(list 0x0 0x200 0x400 0x600 0x800 0xA00 0xC00 0xE00 ) group.long ($2+0x11C+0xC0000)++0x3 line.long 0x0 "IATU_REGION_CTRL_3_OFF_INBOUND_$1,iATU Region Control 3 Register." rbitfld.long 0x0 31. "VF_ACTIVE,Reserved. Not used." "0,1" newline hexmask.long 0x0 3.--30. 1. "RSVDP_VF_NUMBER,Reserved for future use." newline bitfld.long 0x0 0.--2. "VF_NUMBER,Virtual Function Number. When the Address and BAR matching logic in the controller indicates that a MEM-I/O transaction matches a BAR in the virtual function corresponding to this value then address translation proceeds. This check is only.." "0,1,2,3,4,5,6,7" repeat.end tree.end tree "PF0_PORT_LOGIC (Port Logic)" group.long (0x0+0x700)++0x27 line.long 0x0 "ACK_LATENCY_TIMER_OFF,Ack Latency Timer and Replay Timer Register." hexmask.long.word 0x0 16.--31. 1. "REPLAY_TIME_LIMIT,Replay Timer Limit. The replay timer expires when it reaches this limit. The controller initiates a replay upon reception of a NAK or when the replay timer expires. For more details see 'Transmit Replay'. You can modify the effective.." newline hexmask.long.word 0x0 0.--15. 1. "ROUND_TRIP_LATENCY_TIME_LIMIT,Ack Latency Timer Limit. The Ack latency timer expires when it reaches this limit. For more details see 'Ack Scheduling'. You can modify the effective timer limit with the TIMER_MOD_ACK_NAK field of the.." line.long 0x4 "VENDOR_SPEC_DLLP_OFF,Vendor Specific DLLP Register." hexmask.long 0x4 0.--31. 1. "VENDOR_SPEC_DLLP,Vendor Specific DLLP Register. Used to send a specific PCI Express DLLP. Your application writes the 8-bit DLLP Type and 24-bits of Payload data into this register then sets the field VENDOR_SPECIFIC_DLLP_REQ of PORT_LINK_CTRL_OFF to.." line.long 0x8 "PORT_FORCE_OFF,Port Force Link Register." hexmask.long.byte 0x8 24.--31. 1. "RSVDP_24,Reserved for future use." newline bitfld.long 0x8 23. "DO_DESKEW_FOR_SRIS,Use the transitions from TS2 to Logical Idle Symbol SKP OS to Logical Idle Symbol EIEOS to Logical Idle Symbol and FTS Sequence to SKP OS to do deskew instead of using received SKP OS or TS1 to TS2 transition if DO_DESKEW_FOR_SRIS.." "0,1" newline rbitfld.long 0x8 22. "RSVDP_22,Reserved for future use." "0,1" newline hexmask.long.byte 0x8 16.--21. 1. "LINK_STATE,Forced LTSSM State. The LTSSM state that the controller is forced to when you set the FORCE_EN bit (Force Link). LTSSM state encoding is defined by the lts_state variable in workspace/src/Layer1/smlh_ltssm.v. Note: This register field is sticky." newline bitfld.long 0x8 15. "FORCE_EN,Force Link. The controller supports a testing and debug capability to allow your software to force the LTSSM state machine into a specific state and to force the controller to transmit a specific Link Command. Asserting this bit triggers the.." "0,1" newline rbitfld.long 0x8 12.--14. "RSVDP_12,Reserved for future use." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x8 8.--11. 1. "FORCED_LTSSM,Forced Link Command. The link command that the controller is forced to transmit when you set FORCE_EN bit (Force Link). Link command encoding is defined by the ltssm_cmd variable in workspace/src/Layer1/smlh_ltssm.v. Note: This register.." newline hexmask.long.byte 0x8 0.--7. 1. "LINK_NUM,Link Number. Not used for endpoint. Not used for M-PCIe. Note: This register field is sticky." line.long 0xC "ACK_F_ASPM_CTRL_OFF,Ack Frequency and L0-L1 ASPM Control Register." rbitfld.long 0xC 31. "RSVDP_31,Reserved for future use." "0,1" newline bitfld.long 0xC 30. "ENTER_ASPM,ASPM L1 Entry Control. - 1: Controller enters ASPM L1 after a period in which it has been idle. - 0: Controller enters ASPM L1 only after idle period during which both receive and transmit are in L0s. Note: This register field is sticky." "Controller enters ASPM L1 only after idle period..,Controller enters ASPM L1 after a period in.." newline bitfld.long 0xC 27.--29. "L1_ENTRANCE_LATENCY,L1 Entrance Latency. Value range is: - 000: 1 us - 001: 2 us - 010: 4 us - 011: 8 us - 100: 16 us - 101: 32 us - 110 or 111: 64 us Note: Programming this timer with a value greater that 32us has no effect unless extended sync is used.." "0,1,2,3,4,5,6,7" newline bitfld.long 0xC 24.--26. "L0S_ENTRANCE_LATENCY,L0s Entrance Latency. Values correspond to: - 000: 1 us - 001: 2 us - 010: 3 us - 011: 4 us - 100: 5 us - 101: 6 us - 110 or 111: 7 us This field is applicable to STALL while in L0 for M-PCIe. Note: This register field is sticky." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0xC 16.--23. 1. "COMMON_CLK_N_FTS,Common Clock N_FTS. This is the N_FTS when common clock is used. The number of Fast Training Sequence ordered sets to be transmitted when transitioning from L0s to L0. The maximum number of FTS ordered-sets that a component can request.." newline hexmask.long.byte 0xC 8.--15. 1. "ACK_N_FTS,N_FTS. The number of Fast Training Sequence ordered sets to be transmitted when transitioning from L0s to L0. The maximum number of FTS ordered-sets that a component can request is 255. The controller does not support a value of zero; a value.." newline hexmask.long.byte 0xC 0.--7. 1. "ACK_FREQ,Ack Frequency. The controller accumulates the number of pending ACKs specified here (up to 255) before scheduling an ACK DLLP. - 0: Indicates that this Ack Frequency Counter feature is turned off. The controller generates a low-priority ACK.." line.long 0x10 "PORT_LINK_CTRL_OFF,Port Link Control Register." hexmask.long.byte 0x10 28.--31. 1. "RSVDP_28,Reserved for future use." newline bitfld.long 0x10 27. "TRANSMIT_LANE_REVERSALE_ENABLE,TRANSMIT_LANE_REVERSALE_ENABLE is an internally reserved field. Do not use. Note: This register field is sticky." "0,1" newline bitfld.long 0x10 26. "EXTENDED_SYNCH,EXTENDED_SYNCH is an internally reserved field. Do not use. Note: This register field is sticky." "0,1" newline bitfld.long 0x10 25. "CORRUPT_LCRC_ENABLE,CORRUPT_LCRC_ENABLE is an internally reserved field. Do not use. Note: This register field is sticky." "0,1" newline bitfld.long 0x10 24. "BEACON_ENABLE,BEACON_ENABLE is an internally reserved field. Do not use. Note: This register field is sticky." "0,1" newline hexmask.long.byte 0x10 16.--21. 1. "LINK_CAPABLE,Link Mode Enable. Sets the number of lanes in the link that you want to connect to the link partner. When you have unused lanes in your system then you must change the value in this register to reflect the number of lanes. You must also.." newline hexmask.long.byte 0x10 12.--15. 1. "RSVDP_12,Reserved for future use." newline hexmask.long.byte 0x10 8.--11. 1. "LINK_RATE,LINK_RATE is an internally reserved field. Do not use. Note: This register field is sticky." newline bitfld.long 0x10 7. "FAST_LINK_MODE,Fast Link Mode. Sets all internal LTSSM millisecond timers to Fast Mode for speeding up simulation. Forces the LTSSM training (link initialization) to use shorter time-outs and to link up faster. The default scaling factor can be changed.." "0,1" newline bitfld.long 0x10 6. "LINK_DISABLE,LINK_DISABLE is an internally reserved field. Do not use. Note: This register field is sticky." "0,1" newline bitfld.long 0x10 5. "DLL_LINK_EN,DLL Link Enable. Enables link initialization. When DLL Link Enable =0 the controller does not transmit InitFC DLLPs and does not establish a link. Note: This register field is sticky." "0,1" newline rbitfld.long 0x10 4. "RSVDP_4,Reserved for future use." "0,1" newline bitfld.long 0x10 3. "RESET_ASSERT,Reset Assert. Triggers a recovery and forces the LTSSM to the hot reset state (downstream port only). Note: This register field is sticky." "0,1" newline bitfld.long 0x10 2. "LOOPBACK_ENABLE,Loopback Enable. Turns on loopback. For more details see 'Loopback'. For M-PCIe to force the master to enter Digital Loopback mode you must set this field to '1' during Configuration.start state(initial discovery/configuration). M-PCIe.." "0,1" newline bitfld.long 0x10 1. "SCRAMBLE_DISABLE,Scramble Disable. Turns off data scrambling. Note: This register field is sticky." "0,1" newline bitfld.long 0x10 0. "VENDOR_SPECIFIC_DLLP_REQ,Vendor Specific DLLP Request. When software writes a '1' to this bit the controller transmits the DLLP contained in the VENDOR_SPEC_DLLP field of VENDOR_SPEC_DLLP_OFF. Reading from this self-clearing register field always.." "0,1" line.long 0x14 "LANE_SKEW_OFF,Lane Skew Register." bitfld.long 0x14 31. "DISABLE_LANE_TO_LANE_DESKEW,Disable Lane-to-Lane Deskew. Causes the controller to disable the internal Lane-to-Lane deskew logic. Note: This register field is sticky." "0,1" newline hexmask.long.byte 0x14 27.--30. 1. "IMPLEMENT_NUM_LANES,Implementation-specific Number of Lanes. Set the implementation-specific number of lanes. Allowed values are: - 4'b0000: 1 lane - 4'b0001: 2 lanes - 4'b0011: 4 lanes - 4'b0111: 8 lanes - 4'b1111: 16 lanes The number of lanes to be.." newline bitfld.long 0x14 26. "ELASTIC_BUFFER_MODE,Selects Elasticity Buffer operating mode: 0: Nominal Half Full Buffer mode 1: Nominal Empty Buffer Mode Note: This register field is sticky." "Nominal Half Full Buffer mode,Nominal Empty Buffer Mode" newline bitfld.long 0x14 25. "ACK_NAK_DISABLE,Ack/Nak Disable. Prevents the controller from sending ACK and NAK DLLPs. Note: This register field is sticky." "0,1" newline bitfld.long 0x14 24. "FLOW_CTRL_DISABLE,Flow Control Disable. Prevents the controller from sending FC DLLPs. Note: This register field is sticky." "0,1" newline hexmask.long.tbyte 0x14 0.--23. 1. "INSERT_LANE_SKEW,INSERT_LANE_SKEW is an internally reserved field. Do not use. Note: This register field is sticky." line.long 0x18 "TIMER_CTRL_MAX_FUNC_NUM_OFF,Timer Control and Max Function Number Register." rbitfld.long 0x18 31. "RSVDP_31,Reserved for future use." "0,1" newline bitfld.long 0x18 29.--30. "FAST_LINK_SCALING_FACTOR,Fast Link Timer Scaling Factor. Sets the scaling factor of LTSSM timer when FAST_LINK_MODE field in PORT_LINK_CTRL_OFF is set to '1'. - 0: Scaling Factor is 1024 (1ms is 1us *a) - 1: Scaling Factor is 256 (1ms is 4us) - 2:.." "Scaling Factor is 1024,Scaling Factor is 256,Scaling Factor is 64,Scaling Factor is 16" newline hexmask.long.byte 0x18 24.--28. 1. "UPDATE_FREQ_TIMER,UPDATE_FREQ_TIMER is an internally reserved field. Do not use. Note: This register field is sticky." newline hexmask.long.byte 0x18 19.--23. 1. "TIMER_MOD_ACK_NAK,Ack Latency Timer Modifier. Increases the timer value for the Ack latency timer in increments of 64 clock cycles. A value of '0' represents no modification to the timer value. For more details see the ROUND_TRIP_LATENCY_TIME_LIMIT.." newline hexmask.long.byte 0x18 14.--18. 1. "TIMER_MOD_REPLAY_TIMER,Replay Timer Limit Modifier. Increases the time-out value for the replay timer in increments of 64 clock cycles at Gen1 or Gen2 speed and in increments of 256 clock cycles at Gen3 speed. A value of '0' represents no modification.." newline hexmask.long.byte 0x18 8.--13. 1. "RSVDP_8,Reserved for future use." newline hexmask.long.byte 0x18 0.--7. 1. "MAX_FUNC_NUM,Maximum function number that can be used in a request. Configuration requests targeted at function numbers above this value are returned with UR (unsupported request). Note: This register field is sticky." line.long 0x1C "SYMBOL_TIMER_FILTER_1_OFF,Symbol Timer Register and Filter Mask 1 Register. The Filter Mask 1 Register modifies the RADM filtering and error handling rules. For more details. see the 'Receive Filtering' section. In each case. '0' applies the associated.." hexmask.long.word 0x1C 16.--31. 1. "MASK_RADM_1,Filter Mask 1. The Filter Mask 1 Register modifies the RADM filtering and error handling rules. For more details see the 'Receive Filtering' section. In each case '0' applies the associated filtering rule and '1' masks the associated.." newline bitfld.long 0x1C 15. "DISABLE_FC_WD_TIMER,Disable FC Watchdog Timer. Note: This register field is sticky." "0,1" newline hexmask.long.byte 0x1C 11.--14. 1. "EIDLE_TIMER,EIDLE_TIMER is an internally reserved field. Do not use. Note: This register field is sticky." newline hexmask.long.word 0x1C 0.--10. 1. "SKP_INT_VAL,SKP Interval Value. The number of symbol times to wait between transmitting SKP ordered sets. Note that the controller actually waits the number of symbol times in this register plus 1 between transmitting SKP ordered sets. Your application.." line.long 0x20 "FILTER_MASK_2_OFF,Filter Mask 2 Register. This register modifies the RADM filtering and error handling rules. For more details. see the 'Receive Filtering' section. In each case. '0' applies the associated filtering rule and '1' masks the associated.." hexmask.long 0x20 0.--31. 1. "MASK_RADM_2,Filter Mask 2. This field modifies the RADM filtering and error handling rules. For more details see the 'Receive Filtering' section. In each case '0' applies the associated filtering rule and '1' masks the associated filtering rule." line.long 0x24 "AMBA_MUL_OB_DECOMP_NP_SUB_REQ_CTRL_OFF,AMBA Multiple Outbound Decomposed NP SubRequests Control Register." hexmask.long 0x24 1.--31. 1. "RSVDP_1,Reserved for future use." newline bitfld.long 0x24 0. "OB_RD_SPLIT_BURST_EN,Enable AMBA Multiple Outbound Decomposed NP SubRequests. This bit when set to '0' disables the possibility of having multiple outstanding non-posted requests that were derived from decomposition of an outbound AMBA request. For more.." "0,1" rgroup.long (0x28+0x700)++0x13 line.long 0x0 "PL_DEBUG0_OFF,Debug Register 0" hexmask.long 0x0 0.--31. 1. "DEB_REG_0,The value on cxpl_debug_info[31:0]." line.long 0x4 "PL_DEBUG1_OFF,Debug Register 1" hexmask.long 0x4 0.--31. 1. "DEB_REG_1,The value on cxpl_debug_info[63:32]." line.long 0x8 "TX_P_FC_CREDIT_STATUS_OFF,Transmit Posted FC Credit Status" hexmask.long.word 0x8 20.--31. 1. "RSVDP_TX_P_FC_CREDIT_STATUS,Reserved for future use." newline hexmask.long.byte 0x8 12.--19. 1. "TX_P_HEADER_FC_CREDIT,Transmit Posted Header FC Credits. The posted Header credits advertised by the receiver at the other end of the link updated with each UpdateFC DLLP. Default value depends on the number of advertised credits for header and data.." newline hexmask.long.word 0x8 0.--11. 1. "TX_P_DATA_FC_CREDIT,Transmit Posted Data FC Credits. The posted Data credits advertised by the receiver at the other end of the link updated with each UpdateFC DLLP. Default value depends on the number of advertised credits for header and data Scaled.." line.long 0xC "TX_NP_FC_CREDIT_STATUS_OFF,Transmit Non-Posted FC Credit Status" hexmask.long.word 0xC 20.--31. 1. "RSVDP_TX_NP_FC_CREDIT_STATUS,Reserved for future use." newline hexmask.long.byte 0xC 12.--19. 1. "TX_NP_HEADER_FC_CREDIT,Transmit Non-Posted Header FC Credits. The non-posted Header credits advertised by the receiver at the other end of the link updated with each UpdateFC DLLP. Default value depends on the number of advertised credits for header and.." newline hexmask.long.word 0xC 0.--11. 1. "TX_NP_DATA_FC_CREDIT,Transmit Non-Posted Data FC Credits. The non-posted Data credits advertised by the receiver at the other end of the link updated with each UpdateFC DLLP. Default value depends on the number of advertised credits for header and data.." line.long 0x10 "TX_CPL_FC_CREDIT_STATUS_OFF,Transmit Completion FC Credit Status" hexmask.long.word 0x10 20.--31. 1. "RSVDP_TX_CPL_FC_CREDIT_STATUS,Reserved for future use." newline hexmask.long.byte 0x10 12.--19. 1. "TX_CPL_HEADER_FC_CREDIT,Transmit Completion Header FC Credits. The Completion Header credits advertised by the receiver at the other end of the link updated with each UpdateFC DLLP. Default value depends on the number of advertised credits for header.." newline hexmask.long.word 0x10 0.--11. 1. "TX_CPL_DATA_FC_CREDIT,Transmit Completion Data FC Credits. The Completion Data credits advertised by the receiver at the other end of the link updated with each UpdateFC DLLP. Default value depends on the number of advertised credits for header and data.." group.long (0x3C+0x700)++0x3 line.long 0x0 "QUEUE_STATUS_OFF,Queue Status" bitfld.long 0x0 31. "TIMER_MOD_FLOW_CONTROL_EN,FC Latency Timer Override Enable. When this bit is set the value from the 'FC Latency Timer Override Value' field in this register will override the FC latency timer value that the controller calculates according to the PCIe.." "0,1" newline rbitfld.long 0x0 29.--30. "RSVDP_29,Reserved for future use." "0,1,2,3" newline hexmask.long.word 0x0 16.--28. 1. "TIMER_MOD_FLOW_CONTROL,FC Latency Timer Override Value. When you set the 'FC Latency Timer Override Enable' in this register the value in this field will override the FC latency timer value that the controller calculates according to the PCIe.." newline rbitfld.long 0x0 13. "RX_SERIALIZATION_Q_NON_EMPTY,Receive Serialization Queue Not Empty. Indicates there is data in the serialization queue." "0,1" newline hexmask.long.word 0x0 4.--12. 1. "RSVDP_4,Reserved for future use." newline bitfld.long 0x0 3. "RX_QUEUE_OVERFLOW,Receive Credit Queue Overflow. Indicates insufficient buffer space available to write to the P/NP/CPL credit queue." "0,1" newline rbitfld.long 0x0 2. "RX_QUEUE_NON_EMPTY,Receive Credit Queue Not Empty. Indicates there is data in one or more of the receive buffers." "0,1" newline rbitfld.long 0x0 1. "TX_RETRY_BUFFER_NE,Transmit Retry Buffer Not Empty. Indicates that there is data in the transmit retry buffer." "0,1" newline rbitfld.long 0x0 0. "RX_TLP_FC_CREDIT_NON_RETURN,Received TLP FC Credits Not Returned. Indicates that the controller has received a TLP but has not yet sent an UpdateFC DLLP indicating that the credits for that TLP have been restored by the receiver at the other end of the.." "0,1" rgroup.long (0x40+0x700)++0x7 line.long 0x0 "VC_TX_ARBI_1_OFF,VC Transmit Arbitration Register 1" hexmask.long.byte 0x0 24.--31. 1. "WRR_WEIGHT_VC_3,WRR Weight for VC3. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R" newline hexmask.long.byte 0x0 16.--23. 1. "WRR_WEIGHT_VC_2,WRR Weight for VC2. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R" newline hexmask.long.byte 0x0 8.--15. 1. "WRR_WEIGHT_VC_1,WRR Weight for VC1. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R" newline hexmask.long.byte 0x0 0.--7. 1. "WRR_WEIGHT_VC_0,WRR Weight for VC0. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R" line.long 0x4 "VC_TX_ARBI_2_OFF,VC Transmit Arbitration Register 2" hexmask.long.byte 0x4 24.--31. 1. "WRR_WEIGHT_VC_7,WRR Weight for VC7. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R" newline hexmask.long.byte 0x4 16.--23. 1. "WRR_WEIGHT_VC_6,WRR Weight for VC6. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R" newline hexmask.long.byte 0x4 8.--15. 1. "WRR_WEIGHT_VC_5,WRR Weight for VC5. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R" newline hexmask.long.byte 0x4 0.--7. 1. "WRR_WEIGHT_VC_4,WRR Weight for VC4. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R" group.long (0x48+0x700)++0xB line.long 0x0 "VC0_P_RX_Q_CTRL_OFF,Segmented-Buffer VC0 Posted Receive Queue Control." bitfld.long 0x0 31. "VC_ORDERING_RX_Q,VC Ordering for Receive Queues. Determines the VC ordering rule for the receive queues used only in the segmented-buffer configuration: - 1: Strict ordering higher numbered VCs have higher priority - 0: Round robin Note: This register.." "Round robin,Strict ordering" newline bitfld.long 0x0 30. "TLP_TYPE_ORDERING_VC0,TLP Type Ordering for VC0. Determines the TLP type ordering rule for VC0 receive queues used only in the segmented-buffer configuration: - 1: PCIe ordering rules (recommended) - 0: Strict ordering: posted completion then.." "Strict ordering: posted,PCIe ordering rules" newline bitfld.long 0x0 28.--29. "RESERVED5,Reserved. Note: This register field is sticky." "0,1,2,3" newline bitfld.long 0x0 26.--27. "VC0_P_DATA_SCALE,VC0 Scale Posted Data Credites. Note: This register field is sticky." "0,1,2,3" newline bitfld.long 0x0 24.--25. "VC0_P_HDR_SCALE,VC0 Scale Posted Header Credites. Note: This register field is sticky." "0,1,2,3" newline bitfld.long 0x0 21.--23. "VC0_P_TLP_Q_MODE,Reserved. Note: This register field is sticky." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 20. "RESERVED4,Reserved. Note: This register field is sticky." "0,1" newline hexmask.long.byte 0x0 12.--19. 1. "VC0_P_HEADER_CREDIT,VC0 Posted Header Credits. The number of initial posted header credits for VC0 used only in the segmented-buffer configuration. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R (sticky) Note: This.." newline hexmask.long.word 0x0 0.--11. 1. "VC0_P_DATA_CREDIT,VC0 Posted Data Credits. The number of initial posted data credits for VC0 used only in the segmented-buffer configuration. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R (sticky) Note: This.." line.long 0x4 "VC0_NP_RX_Q_CTRL_OFF,Segmented-Buffer VC0 Non-Posted Receive Queue Control." hexmask.long.byte 0x4 28.--31. 1. "RESERVED7,Reserved. Note: This register field is sticky." newline bitfld.long 0x4 26.--27. "VC0_NP_DATA_SCALE,VC0 Scale Non-Posted Data Credites. Note: This register field is sticky." "0,1,2,3" newline bitfld.long 0x4 24.--25. "VC0_NP_HDR_SCALE,VC0 Scale Non-Posted Header Credites. Note: This register field is sticky." "0,1,2,3" newline bitfld.long 0x4 21.--23. "VC0_NP_TLP_Q_MODE,Reserved. Note: This register field is sticky." "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 20. "RESERVED6,Reserved. Note: This register field is sticky." "0,1" newline hexmask.long.byte 0x4 12.--19. 1. "VC0_NP_HEADER_CREDIT,VC0 Non-Posted Header Credits. The number of initial non-posted header credits for VC0 used only in the segmented-buffer configuration. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R (sticky).." newline hexmask.long.word 0x4 0.--11. 1. "VC0_NP_DATA_CREDIT,VC0 Non-Posted Data Credits. The number of initial non-posted data credits for VC0 used only in the segmented-buffer configuration. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R (sticky) Note:.." line.long 0x8 "VC0_CPL_RX_Q_CTRL_OFF,Segmented-Buffer VC0 Completion Receive Queue Control." hexmask.long.byte 0x8 28.--31. 1. "RESERVED9,Reserved. Note: This register field is sticky." newline bitfld.long 0x8 26.--27. "VC0_CPL_DATA_SCALE,VC0 Scale CPL Data Credites. Note: This register field is sticky." "0,1,2,3" newline bitfld.long 0x8 24.--25. "VC0_CPL_HDR_SCALE,VC0 Scale CPL Header Credites. Note: This register field is sticky." "0,1,2,3" newline bitfld.long 0x8 21.--23. "VC0_CPL_TLP_Q_MODE,Reserved. Note: This register field is sticky." "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 20. "RESERVED8,Reserved. Note: This register field is sticky." "0,1" newline hexmask.long.byte 0x8 12.--19. 1. "VC0_CPL_HEADER_CREDIT,VC0 Completion Header Credits. The number of initial Completion header credits for VC0 used only in the segmented-buffer configuration. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R (sticky).." newline hexmask.long.word 0x8 0.--11. 1. "VC0_CPL_DATA_CREDIT,VC0 Completion Data Credits. The number of initial Completion data credits for VC0 used only in the segmented-buffer configuration. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R (sticky) Note:.." group.long (0x10C+0x700)++0x3 line.long 0x0 "GEN2_CTRL_OFF,This register is used to control various functions of the controller related to link training. lane reversal. and equalization." rbitfld.long 0x0 31. "RSVDP_31,Reserved for future use." "0,1" newline bitfld.long 0x0 30. "FORCE_LANE_FLIP,Enable to force the LANE_UNDER_TEST physical lane flips to logical lane 0. All the other physical lanes are turned off. The LINK_CAPABLE register must be set to 1 and only x1 link can be formed if the FORCE_LANE_FLIP register is set to 1." "0,1" newline hexmask.long.byte 0x0 24.--27. 1. "LANE_UNDER_TEST,The Lane Under Test is the lane for Forced Lane Flip or for Loopback Eq. The value is from 0 to CX_NL. Only one lane is configured each time. The default of this field is the CX_DEFAULT_LANE_UNDER_TEST configuration parameter. This field.." newline rbitfld.long 0x0 22.--23. "RSVDP_22,Reserved for future use." "0,1,2,3" newline bitfld.long 0x0 21. "GEN1_EI_INFERENCE,Electrical Idle Inference Mode at Gen1 Rate. Programmable mode to determine inferred electrical idle (EI) in Recovery.Speed or Loopback.Active (as slave) state at Gen1 speed by looking for a '1' value on RxElecIdle instead of looking.." "Use RxElecIdle signal to infer Electrical Idle,Use RxValid signal to infer Electrical Idle" newline bitfld.long 0x0 20. "SEL_DEEMPHASIS,Used to set the de-emphasis level for upstream ports. This bit selects the level of de-emphasis the link operates at. - 0: -6 dB - 1: -3.5 dB This field is reserved (fixed to '0') for M-PCIe. Note: The access attributes of this field are.." "0,1" newline bitfld.long 0x0 19. "CONFIG_TX_COMP_RX,Config Tx Compliance Receive Bit. When set to 1 signals LTSSM to transmit TS ordered sets with the compliance receive bit assert (equal to '1'). This field is reserved (fixed to '0') for M-PCIe. Note: The access attributes of this.." "0,1" newline bitfld.long 0x0 18. "CONFIG_PHY_TX_CHANGE,Config PHY Tx Swing. Controls the PHY transmitter voltage swing level. The controller drives the mac_phy_txswing output from this register bit field. - 0: Full Swing - 1: Low Swing This field is reserved (fixed to '0') for M-PCIe." "Full Swing,Low Swing" newline bitfld.long 0x0 17. "DIRECT_SPEED_CHANGE,Directed Speed Change. Writing '1' to this field instructs the LTSSM to initiate a speed change to Gen2 or Gen3 after the link is initialized at Gen1 speed. When the speed change occurs the controller will clear the contents of this.." "0,1" newline bitfld.long 0x0 16. "AUTO_LANE_FLIP_CTRL_EN,Enable Auto flipping of the lanes. You must set the CX_AUTO_LANE_FLIP_CTRL_EN configuration parameter to include the hardware for this feature in the controller. For more details see the 'Lane Reversal' appendix in the Databook." "0,1" newline bitfld.long 0x0 13.--15. "PRE_DET_LANE,Predetermined Lane for Auto Flip. This field defines which physical lane is connected to logical Lane0 by the flip operation performed in Detect. This field is used to restrict the receiver detect procedure to a particular lane when the.." "LANE0,LANE1,LANE3,LANE7,LANE15,?,?,?" newline hexmask.long.byte 0x0 8.--12. 1. "NUM_OF_LANES,Predetermined Number of Lanes. Defines the number of lanes which are connected and not bad. Used to limit the effective link width to ignore 'broken' or 'unused' lanes that detect a receiver. Indicates the number of lanes to check for exit.." newline hexmask.long.byte 0x0 0.--7. 1. "FAST_TRAINING_SEQ,Sets the Number of Fast Training Sequences (N_FTS) that the controller advertises as its N_FTS during Gen2 or Gen3 link training. This value is used to inform the link partner about the PHY's ability to recover synchronization after a.." rgroup.long (0x110+0x700)++0x3 line.long 0x0 "PHY_STATUS_OFF,PHY Status Register. Memory mapped register from phy_cfg_status GPIO input pins." hexmask.long 0x0 0.--31. 1. "PHY_STATUS,PHY Status. Data received directly from the phy_cfg_status bus. These is a GPIO register reflecting the values on the static phy_cfg_status input signals. The usage is left completely to the user and does not in any way influence controller.." group.long (0x114+0x700)++0x3 line.long 0x0 "PHY_CONTROL_OFF,PHY Control Register. Memory mapped register to cfg_phy_control GPIO output pins." hexmask.long 0x0 0.--31. 1. "PHY_CONTROL,PHY Control. Data sent directly to the cfg_phy_control bus. These is a GPIO register driving the values on the static cfg_phy_control output signals. The usage is left completely to the user and does not in any way influence controller.." group.long (0x11C+0x700)++0x77 line.long 0x0 "TRGT_MAP_CTRL_OFF,Programmable Target Map Control Register." hexmask.long.word 0x0 21.--31. 1. "TARGET_MAP_RESERVED_21_31,Reserved. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R (sticky)" newline hexmask.long.byte 0x0 16.--20. 1. "TARGET_MAP_INDEX,The number of the PF Function on which the Target Values are set. This register does not respect the Byte Enable setting. any write will affect all register bits." newline rbitfld.long 0x0 13.--15. "TARGET_MAP_RESERVED_13_15,Reserved. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R (sticky)" "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x0 7.--12. 1. "TARGET_MAP_VF,Target Values for each BAR on the VF Function selected by the index number. This register does not respect the Byte Enable setting. any write will affect all register bits." newline bitfld.long 0x0 6. "TARGET_MAP_ROM,Target Value for the ROM page of the PF Function selected by the index number. This register does not respect the Byte Enable setting. any write will affect all register bits." "0,1" newline hexmask.long.byte 0x0 0.--5. 1. "TARGET_MAP_PF,Target Values for each BAR on the PF Function selected by the index number. This register does not respect the Byte Enable setting. any write will affect all register bits." line.long 0x4 "MSI_CTRL_ADDR_OFF,Integrated MSI Reception Module (iMRM) Address Register." hexmask.long 0x4 0.--31. 1. "MSI_CTRL_ADDR,Integrated MSI Reception Module Address. System specified address for MSI memory write transaction termination. Within the AXI Bridge every received Memory Write request is examined to see if it targets the MSI Address that has been.." line.long 0x8 "MSI_CTRL_UPPER_ADDR_OFF,Integrated MSI Reception Module Upper Address Register." hexmask.long 0x8 0.--31. 1. "MSI_CTRL_UPPER_ADDR,Integrated MSI Reception Module Upper Address. System specified upper address for MSI memory write transaction termination. Allows functions to support a 64-bit MSI address. Note: This register field is sticky." line.long 0xC "MSI_CTRL_INT_0_EN_OFF,Integrated MSI Reception Module Interrupt#i Enable Register." hexmask.long 0xC 0.--31. 1. "MSI_CTRL_INT_0_EN,MSI Interrupt#i Enable. Specifies which interrupts are enabled. When an MSI is received from a disabled interrupt no status bit gets set in MSI controller interrupt status register. Each bit corresponds to a single MSI Interrupt.." line.long 0x10 "MSI_CTRL_INT_0_MASK_OFF,Integrated MSI Reception Module Interrupt#i Mask Register." hexmask.long 0x10 0.--31. 1. "MSI_CTRL_INT_0_MASK,MSI Interrupt#i Mask. Allows enabled interrupts to be masked. When an MSI is received for a masked interrupt the corresponding status bit gets set in the interrupt status register but the msi_ctrl_int output is not set HIGH. Each bit.." line.long 0x14 "MSI_CTRL_INT_0_STATUS_OFF,Integrated MSI Reception Module Interrupt#i Status Register." hexmask.long 0x14 0.--31. 1. "MSI_CTRL_INT_0_STATUS,MSI Interrupt#i Status. When an MSI is detected for EP#i one bit in this register is set. The decoding of the data payload of the MSI Memory Write request determines which bit gets set. A status is bit is cleared by writing a 1 to.." line.long 0x18 "MSI_CTRL_INT_1_EN_OFF,Integrated MSI Reception Module Interrupt#i Enable Register." hexmask.long 0x18 0.--31. 1. "MSI_CTRL_INT_1_EN,MSI Interrupt#i Enable. Specifies which interrupts are enabled. When an MSI is received from a disabled interrupt no status bit gets set in MSI controller interrupt status register. Each bit corresponds to a single MSI Interrupt.." line.long 0x1C "MSI_CTRL_INT_1_MASK_OFF,Integrated MSI Reception Module Interrupt#i Mask Register." hexmask.long 0x1C 0.--31. 1. "MSI_CTRL_INT_1_MASK,MSI Interrupt#i Mask. Allows enabled interrupts to be masked. When an MSI is received for a masked interrupt the corresponding status bit gets set in the interrupt status register but the msi_ctrl_int output is not set HIGH. Each bit.." line.long 0x20 "MSI_CTRL_INT_1_STATUS_OFF,Integrated MSI Reception Module Interrupt#i Status Register." hexmask.long 0x20 0.--31. 1. "MSI_CTRL_INT_1_STATUS,MSI Interrupt#i Status. When an MSI is detected for EP#i one bit in this register is set. The decoding of the data payload of the MSI Memory Write request determines which bit gets set. A status is bit is cleared by writing a 1 to.." line.long 0x24 "MSI_CTRL_INT_2_EN_OFF,Integrated MSI Reception Module Interrupt#i Enable Register." hexmask.long 0x24 0.--31. 1. "MSI_CTRL_INT_2_EN,MSI Interrupt#i Enable. Specifies which interrupts are enabled. When an MSI is received from a disabled interrupt no status bit gets set in MSI controller interrupt status register. Each bit corresponds to a single MSI Interrupt.." line.long 0x28 "MSI_CTRL_INT_2_MASK_OFF,Integrated MSI Reception Module Interrupt#i Mask Register." hexmask.long 0x28 0.--31. 1. "MSI_CTRL_INT_2_MASK,MSI Interrupt#i Mask. Allows enabled interrupts to be masked. When an MSI is received for a masked interrupt the corresponding status bit gets set in the interrupt status register but the msi_ctrl_int output is not set HIGH. Each bit.." line.long 0x2C "MSI_CTRL_INT_2_STATUS_OFF,Integrated MSI Reception Module Interrupt#i Status Register." hexmask.long 0x2C 0.--31. 1. "MSI_CTRL_INT_2_STATUS,MSI Interrupt#i Status. When an MSI is detected for EP#i one bit in this register is set. The decoding of the data payload of the MSI Memory Write request determines which bit gets set. A status is bit is cleared by writing a 1 to.." line.long 0x30 "MSI_CTRL_INT_3_EN_OFF,Integrated MSI Reception Module Interrupt#i Enable Register." hexmask.long 0x30 0.--31. 1. "MSI_CTRL_INT_3_EN,MSI Interrupt#i Enable. Specifies which interrupts are enabled. When an MSI is received from a disabled interrupt no status bit gets set in MSI controller interrupt status register. Each bit corresponds to a single MSI Interrupt.." line.long 0x34 "MSI_CTRL_INT_3_MASK_OFF,Integrated MSI Reception Module Interrupt#i Mask Register." hexmask.long 0x34 0.--31. 1. "MSI_CTRL_INT_3_MASK,MSI Interrupt#i Mask. Allows enabled interrupts to be masked. When an MSI is received for a masked interrupt the corresponding status bit gets set in the interrupt status register but the msi_ctrl_int output is not set HIGH. Each bit.." line.long 0x38 "MSI_CTRL_INT_3_STATUS_OFF,Integrated MSI Reception Module Interrupt#i Status Register." hexmask.long 0x38 0.--31. 1. "MSI_CTRL_INT_3_STATUS,MSI Interrupt#i Status. When an MSI is detected for EP#i one bit in this register is set. The decoding of the data payload of the MSI Memory Write request determines which bit gets set. A status is bit is cleared by writing a 1 to.." line.long 0x3C "MSI_CTRL_INT_4_EN_OFF,Integrated MSI Reception Module Interrupt#i Enable Register." hexmask.long 0x3C 0.--31. 1. "MSI_CTRL_INT_4_EN,MSI Interrupt#i Enable. Specifies which interrupts are enabled. When an MSI is received from a disabled interrupt no status bit gets set in MSI controller interrupt status register. Each bit corresponds to a single MSI Interrupt.." line.long 0x40 "MSI_CTRL_INT_4_MASK_OFF,Integrated MSI Reception Module Interrupt#i Mask Register." hexmask.long 0x40 0.--31. 1. "MSI_CTRL_INT_4_MASK,MSI Interrupt#i Mask. Allows enabled interrupts to be masked. When an MSI is received for a masked interrupt the corresponding status bit gets set in the interrupt status register but the msi_ctrl_int output is not set HIGH. Each bit.." line.long 0x44 "MSI_CTRL_INT_4_STATUS_OFF,Integrated MSI Reception Module Interrupt#i Status Register." hexmask.long 0x44 0.--31. 1. "MSI_CTRL_INT_4_STATUS,MSI Interrupt#i Status. When an MSI is detected for EP#i one bit in this register is set. The decoding of the data payload of the MSI Memory Write request determines which bit gets set. A status is bit is cleared by writing a 1 to.." line.long 0x48 "MSI_CTRL_INT_5_EN_OFF,Integrated MSI Reception Module Interrupt#i Enable Register." hexmask.long 0x48 0.--31. 1. "MSI_CTRL_INT_5_EN,MSI Interrupt#i Enable. Specifies which interrupts are enabled. When an MSI is received from a disabled interrupt no status bit gets set in MSI controller interrupt status register. Each bit corresponds to a single MSI Interrupt.." line.long 0x4C "MSI_CTRL_INT_5_MASK_OFF,Integrated MSI Reception Module Interrupt#i Mask Register." hexmask.long 0x4C 0.--31. 1. "MSI_CTRL_INT_5_MASK,MSI Interrupt#i Mask. Allows enabled interrupts to be masked. When an MSI is received for a masked interrupt the corresponding status bit gets set in the interrupt status register but the msi_ctrl_int output is not set HIGH. Each bit.." line.long 0x50 "MSI_CTRL_INT_5_STATUS_OFF,Integrated MSI Reception Module Interrupt#i Status Register." hexmask.long 0x50 0.--31. 1. "MSI_CTRL_INT_5_STATUS,MSI Interrupt#i Status. When an MSI is detected for EP#i one bit in this register is set. The decoding of the data payload of the MSI Memory Write request determines which bit gets set. A status is bit is cleared by writing a 1 to.." line.long 0x54 "MSI_CTRL_INT_6_EN_OFF,Integrated MSI Reception Module Interrupt#i Enable Register." hexmask.long 0x54 0.--31. 1. "MSI_CTRL_INT_6_EN,MSI Interrupt#i Enable. Specifies which interrupts are enabled. When an MSI is received from a disabled interrupt no status bit gets set in MSI controller interrupt status register. Each bit corresponds to a single MSI Interrupt.." line.long 0x58 "MSI_CTRL_INT_6_MASK_OFF,Integrated MSI Reception Module Interrupt#i Mask Register." hexmask.long 0x58 0.--31. 1. "MSI_CTRL_INT_6_MASK,MSI Interrupt#i Mask. Allows enabled interrupts to be masked. When an MSI is received for a masked interrupt the corresponding status bit gets set in the interrupt status register but the msi_ctrl_int output is not set HIGH. Each bit.." line.long 0x5C "MSI_CTRL_INT_6_STATUS_OFF,Integrated MSI Reception Module Interrupt#i Status Register." hexmask.long 0x5C 0.--31. 1. "MSI_CTRL_INT_6_STATUS,MSI Interrupt#i Status. When an MSI is detected for EP#i one bit in this register is set. The decoding of the data payload of the MSI Memory Write request determines which bit gets set. A status is bit is cleared by writing a 1 to.." line.long 0x60 "MSI_CTRL_INT_7_EN_OFF,Integrated MSI Reception Module Interrupt#i Enable Register." hexmask.long 0x60 0.--31. 1. "MSI_CTRL_INT_7_EN,MSI Interrupt#i Enable. Specifies which interrupts are enabled. When an MSI is received from a disabled interrupt no status bit gets set in MSI controller interrupt status register. Each bit corresponds to a single MSI Interrupt.." line.long 0x64 "MSI_CTRL_INT_7_MASK_OFF,Integrated MSI Reception Module Interrupt#i Mask Register." hexmask.long 0x64 0.--31. 1. "MSI_CTRL_INT_7_MASK,MSI Interrupt#i Mask. Allows enabled interrupts to be masked. When an MSI is received for a masked interrupt the corresponding status bit gets set in the interrupt status register but the msi_ctrl_int output is not set HIGH. Each bit.." line.long 0x68 "MSI_CTRL_INT_7_STATUS_OFF,Integrated MSI Reception Module Interrupt#i Status Register." hexmask.long 0x68 0.--31. 1. "MSI_CTRL_INT_7_STATUS,MSI Interrupt#i Status. When an MSI is detected for EP#i one bit in this register is set. The decoding of the data payload of the MSI Memory Write request determines which bit gets set. A status is bit is cleared by writing a 1 to.." line.long 0x6C "MSI_GPIO_IO_OFF,Integrated MSI Reception Module General Purpose IO Register." hexmask.long 0x6C 0.--31. 1. "MSI_GPIO_REG,MSI GPIO Register. The contents of this register drives the top-level GPIO msi_ctrl_io[31:0] Note: This register field is sticky." line.long 0x70 "CLOCK_GATING_CTRL_OFF,This register enables you to disable dynamic clock gating. By default dynamic clock gating is on. allowing the controller to autonomously enable and disable its clocks. The clock gating is performed in the clock and reset module." hexmask.long 0x70 2.--31. 1. "RSVDP_2,Reserved for future use." newline bitfld.long 0x70 1. "AXI_CLK_GATING_EN,AXI Clock Gating Enable. This register enables the AXI Bridge to autonomously enable and disable the AXI Master clock the AXI Slave clock and the AXI DBI slave clock. The DWC_pcie_clk_rst.v module provides the gated clock.." "Disable,Enable" newline bitfld.long 0x70 0. "RADM_CLK_GATING_EN,RADM Clock Gating Enable. This register if set enables the RADM to autonomously enable and disable its clock. The DWC_pcie_clk_rst.v module provides the gated clock radm_clk_g to the RADM and is enabled when the controllers clock.." "Disable,Enable" line.long 0x74 "GEN3_RELATED_OFF,Gen3 Control Register. There is no Gen3-specific N_FTS field. The N_FTS field in the 'Link Width and Speed Change Control Register' is used for both Gen2 and Gen3 speed modes. There is no Gen3-specific 'Directed Speed Change' field. The.." hexmask.long.byte 0x74 26.--31. 1. "RSVDP_26,Reserved for future use." newline bitfld.long 0x74 23. "GEN3_EQ_INVREQ_EVAL_DIFF_DISABLE,Eq InvalidRequest and RxEqEval Different Time Assertion Disable. Disable the assertion of Eq InvalidRequest and RxEqEval at different time. Note: When CX_GEN4_SPEED/CX_GEN5_SPEED this register is shared for Gen3 and.." "0,1" newline rbitfld.long 0x74 19.--20. "RSVDP_19,Reserved for future use." "0,1,2,3" newline bitfld.long 0x74 18. "GEN3_DC_BALANCE_DISABLE,DC Balance Disable. Disable DC Balance feature. Note: When CX_GEN4_SPEED/CX_GEN5_SPEED this register is shared for Gen3 and Gen4/Gen5 data rate. Note: This register field is sticky." "0,1" newline bitfld.long 0x74 17. "GEN3_DLLP_XMT_DELAY_DISABLE,DLLP Transmission Delay Disable. Disable delay transmission of DLLPs before equalization. Note: When CX_GEN4_SPEED/CX_GEN5_SPEED this register is shared for Gen3 and Gen4/Gen5 data rate. Note: This register field is sticky." "0,1" newline bitfld.long 0x74 16. "GEN3_EQUALIZATION_DISABLE,Equalization Disable. Disable equalization feature. This bit cannot be changed once the LTSSM starts link training. Note: When CX_GEN4_SPEED/CX_GEN5_SPEED this register is shared for Gen3 and Gen4/Gen5 data rate. Note: This.." "0,1" newline rbitfld.long 0x74 14.--15. "RSVDP_14,Reserved for future use." "0,1,2,3" newline bitfld.long 0x74 13. "RXEQ_RGRDLESS_RXTS,When set to '1' the controller as Gen3 EQ master asserts RxEqEval to instruct the PHY to do Rx adaptation and evaluation after a 500ns timeout from a new preset request. - 0: mac_phy_rxeqeval asserts after 1us and 2 TS1 received from.." "mac_phy_rxeqeval asserts after 1us and 2 TS1..,mac_phy_rxeqeval asserts after 500ns regardless.." newline bitfld.long 0x74 12. "RXEQ_PH01_EN,Rx Equalization Phase 0/Phase 1 Hold Enable. When this bit is set the upstream port holds phase 0 (the downstream port holds phase 1) for 10ms. Holding phase 0 or phase 1 can be used to allow sufficient time for Rx Equalization to be.." "Tx equalization only in phase 2/3,No Tx equalization" newline bitfld.long 0x74 11. "EQ_REDO,Equalization Redo Disable. Disable autonomous mechanism for requesting to redo the equalization process. The received presets or coefficients mismatch in Recovery.RcvrLock after Recovery EQ phases causes the EQ redo requests. If the EQ redo is.." "0,1" newline bitfld.long 0x74 10. "EQ_EIEOS_CNT,Equalization EIEOS Count Reset Disable. Disable requesting reset of EIEOS count during equalization. Note: When CX_GEN4_SPEED/CX_GEN5_SPEED this register is shared for Gen3 and Gen4/Gen5 data rate. Note: This register field is sticky." "0,1" newline bitfld.long 0x74 9. "EQ_PHASE_2_3,Equalization Phase 2 and Phase 3 Disable. This applies to downstream ports only. Note: When CX_GEN4_SPEED/CX_GEN5_SPEED this register is shadow register for Gen3 and Gen4/Gen5 data rate. If RATE_SHADOW_SEL==00b this register is for Gen3.." "0,1" newline bitfld.long 0x74 8. "DISABLE_SCRAMBLER_GEN_3,Disable Scrambler for Gen3 and Gen4 Data Rate. The Gen3 and Gen4 scrambler/descrambler within the controller needs to be disabled when the scrambling function is implemented outside of the controller (for example within the PHY)." "0,1" newline hexmask.long.byte 0x74 1.--7. 1. "RSVDP_1,Reserved for future use." newline bitfld.long 0x74 0. "GEN3_ZRXDC_NONCOMPL,Gen3 Receiver Impedance ZRX-DC Not Compliant. Receivers that operate at 8.0 GT/s with an impedance other than the range defined by the ZRX-DC parameter for 2.5 GT/s (40-60 Ohms) must meet additional behavior requirements in the.." "The receiver complies with the ZRX-DC parameter..,The receiver does not comply with the ZRX-DC.." group.long (0x1A8+0x700)++0x7 line.long 0x0 "GEN3_EQ_CONTROL_OFF,Gen3 EQ Control Register. This register controls equalization for Phase2 in an upstream port (USP). or Phase3 in a downstream port (DSP). M-PCIe doesn't have Conventional PCIe Gen3 feature. The registers of this section do not exist." hexmask.long.byte 0x0 27.--31. 1. "RSVDP_27,Reserved for future use." newline bitfld.long 0x0 26. "GEN3_REQ_SEND_CONSEC_EIEOS_FOR_PSET_MAP,Request controller to send back-to-back EIEOS in Recovery.RcvrLock state until presets to coefficients mapping is complete. - 0: Do not request - 1: request Note: Gen3 and Gen4 share the same register bit and have.." "Do not request,request" newline bitfld.long 0x0 25. "GEN3_EQ_PSET_REQ_AS_COEF,GEN3_EQ_PSET_REQ_AS_COEF is an internally reserved field. Do not use. Note: This register field is sticky." "0,1" newline bitfld.long 0x0 24. "GEN3_EQ_FOM_INC_INITIAL_EVAL,Include Initial FOM. Include or not the FOM feedback from the initial preset evaluation performed in the EQ Master when finding the highest FOM among all preset evaluations. - 0: Do not include - 1: Include Note: When.." "Do not include,Include" newline hexmask.long.word 0x0 8.--23. 1. "GEN3_EQ_PSET_REQ_VEC,Preset Request Vector. Requesting of Presets during the initial part of the EQ Master Phase. Encoding scheme is as follows: Bit [15:0] =0x0: No preset is requested and evaluated in EQ Master Phase. Bit [i] =1: 'Preset=i' is requested.." newline rbitfld.long 0x0 7. "RSVDP_7,Reserved for future use." "0,1" newline bitfld.long 0x0 6. "GEN3_LOWER_RATE_EQ_REDO_ENABLE,Support EQ redo and lower rate change: - 0: not support - 1: support Note: Gen3 and Gen4 share the same register bit and have the same feature. Note: This register field is sticky." "not support,support" newline bitfld.long 0x0 5. "GEN3_EQ_EVAL_2MS_DISABLE,Phase2_3 2 ms Timeout Disable. Determine behavior in Phase2 for USP (Phase3 if DSP) when the PHY does not respond within 2ms to the assertion of RxEqEval: - 0: abort the current evaluation stop any attempt to modify the remote.." "abort the current evaluation,ignore the 2ms timeout and continue as normal" newline bitfld.long 0x0 4. "GEN3_EQ_PHASE23_EXIT_MODE,Behavior After 24 ms Timeout (when optimal settings are not found). For a USP: Determine next LTSSM state from Phase2 after 24ms Timeout - 0: Recovery.Speed - 1: Recovery.Equalization.Phase3 When optimal settings are not found.." "Equalization Phase 3 Successful status bit is..,Recovery" newline hexmask.long.byte 0x0 0.--3. 1. "GEN3_EQ_FB_MODE,Feedback Mode. - 0000b: Direction Change - 0001b: Figure Of Merit - 0010b: Reserved - .....: Reserved - 1111b: Reserved Note: When CX_GEN4_SPEED/CX_GEN5_SPEED this register is a shadow register for Gen3 and Gen4/Gen5 data rate. If.." line.long 0x4 "GEN3_EQ_FB_MODE_DIR_CHANGE_OFF,Gen3 EQ Direction Change Feedback Mode Control Register. Equalization controls to be used in Phase2 (USP) or Phase 3 (DSP). when you set the Feedback Mode in 'Gen3 EQ Control Register' to 'Direction Change.' These fields.." hexmask.long.word 0x4 18.--31. 1. "RSVDP_18,Reserved for future use." newline hexmask.long.byte 0x4 14.--17. 1. "GEN3_EQ_FMDC_MAX_POST_CUSROR_DELTA,Convergence Window Aperture for C+1. Post-cursor coefficients maximum delta within the convergence window depth. Allowed range: 0 1 2 ..15. Note: When CX_GEN4_SPEED/CX_GEN5_SPEED this register is shadow register for.." newline hexmask.long.byte 0x4 10.--13. 1. "GEN3_EQ_FMDC_MAX_PRE_CUSROR_DELTA,Convergence Window Aperture for C-1. Pre-cursor coefficients maximum delta within the convergence window depth. Allowed range: 0 1 2 ..15. Note: When CX_GEN4_SPEED/CX_GEN5_SPEED this register is shadow register for Gen3.." newline hexmask.long.byte 0x4 5.--9. 1. "GEN3_EQ_FMDC_N_EVALS,Convergence Window Depth. Number of consecutive evaluations considered in Phase 2/3 when determining if optimal coefficients have been found. Allowed range: 0 1 2 ..16 up to a maximum of CX_GEN3_EQ_COEFQ_DEPTH. When set to 0 EQ.." newline hexmask.long.byte 0x4 0.--4. 1. "GEN3_EQ_FMDC_T_MIN_PHASE23,Minimum Time (in ms) To Remain in EQ Master Phase. The LTSSM stays in EQ Master phase for at least this amount of time before starting to check for convergence of the coefficients. Allowed values 0 1 ... 24. Note: When.." group.long (0x1B4+0x700)++0x27 line.long 0x0 "ORDER_RULE_CTRL_OFF,Order Rule Control Register." hexmask.long.word 0x0 16.--31. 1. "RSVDP_16,Reserved for future use." newline hexmask.long.byte 0x0 8.--15. 1. "CPL_PASS_P,Completion Passing Posted Ordering Rule Control. Determines if CPL can pass halted P queue. - 0: CPL can not pass P (recommended) - 1: CPL can pass P" newline hexmask.long.byte 0x0 0.--7. 1. "NP_PASS_P,Non-Posted Passing Posted Ordering Rule Control. Determines if NP can pass halted P queue. - 0 : NP can not pass P (recommended). - 1 : NP can pass P" line.long 0x4 "PIPE_LOOPBACK_CONTROL_OFF,PIPE Loopback Control Register." bitfld.long 0x4 31. "PIPE_LOOPBACK,PIPE Loopback Enable. Indicates RMMI Loopback if M-PCIe. Note: This register field is sticky." "0,1" newline hexmask.long.byte 0x4 27.--30. 1. "RSVDP_27,Reserved for future use." newline bitfld.long 0x4 24.--26. "RXSTATUS_VALUE,RXSTATUS_VALUE is an internally reserved field. Do not use." "0,1,2,3,4,5,6,7" newline rbitfld.long 0x4 22.--23. "RSVDP_22,Reserved for future use." "0,1,2,3" newline hexmask.long.byte 0x4 16.--21. 1. "RXSTATUS_LANE,RXSTATUS_LANE is an internally reserved field. Do not use. Note: This register field is sticky." newline hexmask.long.word 0x4 0.--15. 1. "LPBK_RXVALID,LPBK_RXVALID is an internally reserved field. Do not use. Note: This register field is sticky." line.long 0x8 "MISC_CONTROL_1_OFF,DBI Read-Only Write Enable Register." hexmask.long.word 0x8 22.--31. 1. "RSVDP_22,Reserved for future use." newline bitfld.long 0x8 21. "P2P_ERR_RPT_CTRL,Determines whether to track completion of transmitted Non-Posted TLPs in P2P mode. - 0: Do not track completion - 1: Track completion Note: This register field is sticky." "Do not track completion,Track completion" newline bitfld.long 0x8 20. "P2P_TRACK_CPL_TO_REG,Determines whether to enable Peer to Peer (P2P) error reporting. - 0: Disable P2P error reporting - 1: Enable P2P error reporting Note: This register field is sticky." "Disable P2P error reporting,Enable P2P error reporting" newline bitfld.long 0x8 18.--19. "TARGET_ABOVE_CONFIG_LIMIT_REG,Configuration requests with an address greater than CONFIG_LIMIT_REG are directed to either ELBI or TRGT1 interface based on the setting of this field. This field can have the following values: - 1: ELBI - 2: TRGT1 Note:.." "?,ELBI,TRGT1,?" newline hexmask.long.word 0x8 8.--17. 1. "CONFIG_LIMIT_REG,Configuration requests are directed either to CDM or ELBI/RTRGT1 based on the value of this field. - Configuration requests with an address less CONFIG_LIMIT_REG are directed to the CDM - Configuration requests with an address greater.." newline bitfld.long 0x8 7. "CFG_TLP_BYPASS_EN_REG,Setting of this field defines which field TARGET_ABOVE_CONFIG_LIMIT_REG or CONFIG_LIMIT_REG decides the destination of Configuration requests. This field can have the following values: - 0: Configuration TLPs are routed according to.." "Configuration TLPs are routed according to the..,Configuration TLPs are routed according to the.." newline bitfld.long 0x8 6. "CPLQ_MNG_EN,This field enables the Completion Queue Management feature. Note: This register field is sticky." "0,1" newline bitfld.long 0x8 5. "ARI_DEVICE_NUMBER,When ARI is enabled this field enables use of the device ID. Note: This register field is sticky." "0,1" newline bitfld.long 0x8 4. "DISABLE_AUTO_LTR_CLR_MSG,Disable the autonomous generation of LTR clear message in upstream port. This field can have the following values: - 0: Allow the autonomous generation of LTR clear message. - 1: Disable the autonomous generation of LTR clear.." "Allow the autonomous generation of LTR clear..,Disable the autonomous generation of LTR clear.." newline bitfld.long 0x8 3. "SIMPLIFIED_REPLAY_TIMER,Enables Simplified Replay Timer (Gen4). For more details see 'Transmit Replay' in 'Transmit TLP Processing' section in the 'Controller Operations' chapter of the Databook. Simplified Replay Timer can have the following Values: -.." "0,1" newline bitfld.long 0x8 2. "UR_CA_MASK_4_TRGT1,When this field is set to '1' the controller suppresses error logging error message generation and CPL generation for non-posted requests TLPs (with UR filtering status) forwarded to your application (that is when DEFAULT_TARGET.." "0,1" newline bitfld.long 0x8 1. "DEFAULT_TARGET,Default target for an IO or MEM request with UR/CA/CRS received. Based on the value of this field the controller either drops or forwards these requests to your application. - 0: The controller drops all incoming I/O or MEM requests (after.." "The controller drops all incoming I/O or MEM..,The controller forwards all incoming I/O or MEM.." newline bitfld.long 0x8 0. "DBI_RO_WR_EN,Write to RO Registers Using DBI. Your application can write to some RO and HwInit register fields through the DBI when you set this field to '1'. For more details see 'Writing to Read-Only Registers' in 'Register Module LBC and DBI'.." "0,1" line.long 0xC "MULTI_LANE_CONTROL_OFF,UpConfigure Multi-lane Control Register. Used when upsizing or downsizing the link width through Configuration state without bringing the link down. For more details. see the 'Link Establishment' section in the 'Controller.." hexmask.long.tbyte 0xC 8.--31. 1. "RSVDP_8,Reserved for future use." newline bitfld.long 0xC 7. "UPCONFIGURE_SUPPORT,Upconfigure Support. The controller sends this value as the Link Upconfigure Capability in TS2 Ordered Sets in Configuration.Complete state. This field is reserved (fixed to '0') for M-PCIe. Note: This register field is sticky." "0,1" newline bitfld.long 0xC 6. "DIRECT_LINK_WIDTH_CHANGE,Directed Link Width Change. The controller always moves to Configuration state through Recovery state when this bit is set to '1'. - If the upconfigure_capable variable is '1' and the PCIE_CAP_HW_AUTO_WIDTH_DISABLE bit in.." "0,1" newline hexmask.long.byte 0xC 0.--5. 1. "TARGET_LINK_WIDTH,Target Link Width. Values correspond to: - 6'b000000: Controller does not start upconfigure or autonomous width downsizing in the Configuration state. - 6'b000001: x1 - 6'b000010: x2 - 6'b000100: x4 - 6'b001000: x8 - 6'b010000: x16 -.." line.long 0x10 "PHY_INTEROP_CTRL_OFF,PHY Interoperability Control Register." hexmask.long.tbyte 0x10 12.--31. 1. "RSVDP_12,Reserved for future use." newline bitfld.long 0x10 10. "L1_CLK_SEL,L1 Clock control bit. This field is reserved for internal use. You should not write to this field and change the default unless specifically instructed by Synopsys support. - 1: Controller does not request aux_clk switch and core_clk gating in.." "Controller requests aux_clk switch and core_clk..,Controller does not request aux_clk switch and.." newline rbitfld.long 0x10 9. "L1_NOWAIT_P1,L1 entry control bit. This field is reserved for internal use. You should not write to this field and change the default unless specifically instructed by Synopsys support. - 1: Controller does not wait for PHY to acknowledge transition to.." "Controller waits for the PHY to acknowledge..,Controller does not wait for PHY to acknowledge.." newline bitfld.long 0x10 8. "L1SUB_EXIT_MODE,L1 Exit Control Using phy_mac_pclkack_n. This field is reserved for internal use. You should not write to this field and change the default unless specifically instructed by Synopsys support. - 1: Controller exits L1 without waiting for.." "Controller waits for the PHY to assert..,Controller exits L1 without waiting for the PHY.." newline rbitfld.long 0x10 7. "RSVDP_7,Reserved for future use." "0,1" newline hexmask.long.byte 0x10 0.--6. 1. "RXSTANDBY_CONTROL,Rxstandby Control. Bits 0..5 determine if the controller asserts the RxStandby signal (mac_phy_rxstandby) in the indicated condition. Bit 6 enables the controller to perform the RxStandby/RxStandbyStatus handshake. This field is.." line.long 0x14 "TRGT_CPL_LUT_DELETE_ENTRY_OFF,TRGT_CPL_LUT Delete Entry Control register. Using this register you can delete one entry in the target completion LUT. You should only use this register when you know that your application will never send the completion.." bitfld.long 0x14 31. "DELETE_EN,This is a one-shot bit. A '1' write to this bit triggers the deletion of the target completion LUT entry that is specified in the LOOK_UP_ID field. This is a self-clearing register field. Reading from this register field always returns a '0'." "0,1" newline hexmask.long 0x14 0.--30. 1. "LOOK_UP_ID,This number selects one entry to delete of the TRGT_CPL_LUT." line.long 0x18 "LINK_FLUSH_CONTROL_OFF,Link Reset Request Flush Control Register." hexmask.long.byte 0x18 24.--31. 1. "RSVD_I_8,This is an internally reserved field. Do not use. Note: This register field is sticky." newline hexmask.long.tbyte 0x18 1.--23. 1. "RSVDP_1,Reserved for future use." newline bitfld.long 0x18 0. "AUTO_FLUSH_EN,Enables automatic flushing of pending requests before sending the reset request to the application logic to reset the PCIe controller and the AXI Bridge. The flushing process is initiated if any of the following events occur: - Hot reset.." "0,1" line.long 0x1C "AMBA_ERROR_RESPONSE_DEFAULT_OFF,AXI Bridge Slave Error Response Register." hexmask.long.word 0x1C 16.--31. 1. "RSVDP_16,Reserved for future use." newline hexmask.long.byte 0x1C 10.--15. 1. "AMBA_ERROR_RESPONSE_MAP,AXI Slave Response Error Map. Allows you to selectively map the errors received from the PCIe completion (for non-posted requests) to the AXI slave responses slv_rresp or slv_bresp. The recommended setting is SLVERR. CRS is.." newline hexmask.long.byte 0x1C 5.--9. 1. "RSVDP_5,Reserved for future use." newline bitfld.long 0x1C 3.--4. "AMBA_ERROR_RESPONSE_CRS,CRS Slave Error Response Mapping. Determines the AXI slave response for CRS completions. For more details see 'Error Handling' in the AXI chapter of the Databook. AHB: - always returns OKAY AXI: - 00: OKAY - 01: OKAY with all.." "OKAY,OKAY with all FFFF_FFFF data for all CRS..,?,?" newline bitfld.long 0x1C 2. "AMBA_ERROR_RESPONSE_VENDORID,Vendor ID Non-existent Slave Error Response Mapping. Determines the AXI slave response for errors on reads to non-existent Vendor ID register. For more details see 'Error Handling' in the AXI chapter of the Databook. AHB: -.." "OKAY,SLVERR/DECERR" newline rbitfld.long 0x1C 1. "RSVDP_1,Reserved for future use." "0,1" newline bitfld.long 0x1C 0. "AMBA_ERROR_RESPONSE_GLOBAL,Global Slave Error Response Mapping. Determines the AXI slave response for all error scenarios on non-posted requests. For more details see 'Error Handling' in the AXI chapter of the Databook. AHB: - 0: OKAY (with FFFF data for.." "OKAY,SLVERR/DECERR" line.long 0x20 "AMBA_LINK_TIMEOUT_OFF,Link Down AXI Bridge Slave Timeout Register. If your application AXI master issues outbound requests to the AXI bridge slave interface before the PCIe link is operational. the controller starts a 'flush' timer. The timeout value of.." hexmask.long.tbyte 0x20 9.--31. 1. "RSVDP_9,Reserved for future use." newline bitfld.long 0x20 8. "LINK_TIMEOUT_ENABLE_DEFAULT,Disable Flush. You can disable the flush feature by setting this field to '1'. Note: This register field is sticky." "0,1" newline hexmask.long.byte 0x20 0.--7. 1. "LINK_TIMEOUT_PERIOD_DEFAULT,Timeout Value (ms). The timer will timeout and then flush the bridge TX request queues after this amount of time. The timer counts when there are pending outbound AXI slave interface requests and the PCIe TX link is not.." line.long 0x24 "AMBA_ORDERING_CTRL_OFF,AMBA Ordering Control." hexmask.long.tbyte 0x24 8.--31. 1. "RSVDP_8,Reserved for future use." newline bitfld.long 0x24 7. "AX_MSTR_ZEROLREAD_FW,AXI Master Zero Length Read Forward to the application. The DW PCIe controller AXI bridge is able to terminate in order with the Posted transactions the zero length read implementing the PCIe express flush semantics of the Posted.." "The zero length Read is terminated at the DW..,The zero length Read is forward to the application" newline rbitfld.long 0x24 5.--6. "RSVDP_5,Reserved for future use." "0,1,2,3" newline bitfld.long 0x24 3.--4. "AX_MSTR_ORDR_P_EVENT_SEL,AXI Master Posted Ordering Event Selector. This field selects how the master interface determines when a P write is completed when enforcing the PCIe ordering rule 'NP must not pass P' at the AXI Master Interface. The AXI.." "B'last event: wait for the all of the write..,AW'last event: wait until the complete Posted..,This setting will not affect:,?" newline rbitfld.long 0x24 2. "RSVDP_2,Reserved for future use." "0,1" newline bitfld.long 0x24 1. "AX_SNP_EN,AXI Serialize Non-Posted Requests Enable. This field enables the AXI Bridge to serialize same ID Non-Posted Read/Write Requests on the wire. Serialization implies one outstanding same ID NP Read or Write on the wire and used to avoid AXI RAR.." "0,1" newline rbitfld.long 0x24 0. "RSVDP_0,Reserved for future use." "0,1" group.long (0x1E0+0x700)++0xB line.long 0x0 "COHERENCY_CONTROL_1_OFF,ACE Cache Coherency Control Register 1" hexmask.long 0x0 2.--31. 1. "CFG_MEMTYPE_BOUNDARY_LOW_ADDR,Boundary Lower Address For Memory Type. Bits [31:0] of dword-aligned address of the boundary for Memory type. The two lower address LSBs are '00'. Addresses up to but not including this value are in the lower address space.." newline rbitfld.long 0x0 1. "RSVDP_1,Reserved for future use." "0,1" newline bitfld.long 0x0 0. "CFG_MEMTYPE_VALUE,Sets the memory type for the lower and upper parts of the address space: - 0: lower = Peripheral; upper = Memory - 1: lower = Memory type; upper = Peripheral Note: This register field is sticky." "lower = Peripheral; upper = Memory,lower = Memory type; upper = Peripheral" line.long 0x4 "COHERENCY_CONTROL_2_OFF,ACE Cache Coherency Control Register 2" hexmask.long 0x4 0.--31. 1. "CFG_MEMTYPE_BOUNDARY_HIGH_ADDR,Boundary Upper Address For Memory Type. Bits [63:32] of the 64-bit dword-aligned address of the boundary for Memory type. Note: This register field is sticky." line.long 0x8 "COHERENCY_CONTROL_3_OFF,ACE Cache Coherency Control Register 3" hexmask.long.byte 0x8 27.--30. 1. "CFG_MSTR_AWCACHE_VALUE,Master Write CACHE Signal Value. Value of the individual bits in mstr_awcache when CFG_MSTR_AWCACHE_MODE is '1'. Note: not applicable to message requests; for message requests the value of mstr_awcache is always '0000' Note: This.." newline hexmask.long.byte 0x8 19.--22. 1. "CFG_MSTR_ARCACHE_VALUE,Master Read CACHE Signal Value. Value of the individual bits in mstr_arcache when CFG_MSTR_ARCACHE_MODE is '1'. Note: This register field is sticky." newline hexmask.long.byte 0x8 11.--14. 1. "CFG_MSTR_AWCACHE_MODE,Master Write CACHE Signal Behavior. Defines how the individual bits in mstr_awcache are controlled: - 0: set automatically by the AXI master - 1: set by the value of the corresponding bit of the CFG_MSTR_AWCACHE_VALUE field Note:.." newline hexmask.long.byte 0x8 3.--6. 1. "CFG_MSTR_ARCACHE_MODE,Master Read CACHE Signal Behavior. Defines how the individual bits in mstr_arcache are controlled: - 0: set automatically by the AXI master - 1: set by the value of the corresponding bit of the CFG_MSTR_ARCACHE_VALUE field Note:.." group.long (0x1F0+0x700)++0x7 line.long 0x0 "AXI_MSTR_MSG_ADDR_LOW_OFF,Lower 20 bits of the programmable AXI address where Messages coming from wire are mapped to. Bits [11:0] of the register are tied to zero for the address to be 4k-aligned. In previous releases. the third and fourth DWORDs of a.." hexmask.long.tbyte 0x0 12.--31. 1. "CFG_AXIMSTR_MSG_ADDR_LOW,Lower 20 bits of the programmable AXI address for Messages. Note: This register field is sticky." newline hexmask.long.word 0x0 0.--11. 1. "CFG_AXIMSTR_MSG_ADDR_LOW_RESERVED,Reserved for future use. Note: This register field is sticky." line.long 0x4 "AXI_MSTR_MSG_ADDR_HIGH_OFF,Upper 32 bits of the programmable AXI address where Messages coming from wire are mapped to." hexmask.long 0x4 0.--31. 1. "CFG_AXIMSTR_MSG_ADDR_HIGH,Upper 32 bits of the programmable AXI address for Messages. Note: This register field is sticky." rgroup.long (0x1F8+0x700)++0x7 line.long 0x0 "PCIE_VERSION_NUMBER_OFF,PCIe Controller IIP Release Version Number. The version number is given in hex format. You should convert each pair of hex characters to ASCII to interpret. Using 4.70a (GA) as an example: - VERSION_NUMBER = 0x3437302a which.." hexmask.long 0x0 0.--31. 1. "VERSION_NUMBER,Version Number." line.long 0x4 "PCIE_VERSION_TYPE_OFF,PCIe Controller IIP Release Version Type. The type is given in hex format. You should convert each pair of hex characters to ASCII to interpret. Using 4.70a (GA) as an example: - VERSION_NUMBER = 0x3437302a which translates to 470*.." hexmask.long 0x4 0.--31. 1. "VERSION_TYPE,Version Type." group.long (0x240+0x700)++0x7 line.long 0x0 "MSIX_ADDRESS_MATCH_LOW_OFF,MSI-X Address Match Low Register. When you enable the MSI-X Table RAM feature (MSIX_TABLE_EN=1). the controller implements the logic and RAM required to generate MSI-X requests. For more details. see the Interrupts section in.." hexmask.long 0x0 2.--31. 1. "MSIX_ADDRESS_MATCH_LOW,MSI-X Address Match Low Address. Note: This register field is sticky." newline rbitfld.long 0x0 1. "MSIX_ADDRESS_MATCH_RESERVED_1,Reserved. Note: This register field is sticky." "0,1" newline bitfld.long 0x0 0. "MSIX_ADDRESS_MATCH_EN,MSI-X Match Enable. Enable the MSI-X Address Match feature when the AXI bridge is present. Note: This register field is sticky." "0,1" line.long 0x4 "MSIX_ADDRESS_MATCH_HIGH_OFF,MSI-X Address Match High Register. When you enable the MSI-X Table RAM feature (MSIX_TABLE_EN=1). the controller implements the logic and RAM required to generate MSI-X requests. For more details. see the Interrupts section in.." hexmask.long 0x4 0.--31. 1. "MSIX_ADDRESS_MATCH_HIGH,MSI-X Address Match High Address. Note: This register field is sticky." wgroup.long (0x248+0x700)++0x3 line.long 0x0 "MSIX_DOORBELL_OFF,MSI-X Doorbell Register. When you enable the MSI-X Table RAM feature (MSIX_TABLE_EN=1). the controller implements the logic and RAM required to generate MSI-X requests. For more details. see the Interrupts section in the 'Controller.." bitfld.long 0x0 29.--31. "MSIX_DOORBELL_RESERVED_29_31,Reserved." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x0 24.--28. 1. "MSIX_DOORBELL_PF,MSIX Doorbell Physical Function. This register determines the Physical Function for the MSI-X transaction." newline hexmask.long.byte 0x0 16.--23. 1. "MSIX_DOORBELL_VF,MSIX Doorbell Virtual Function. This register determines the Virtual Function for the MSI-X transaction." newline bitfld.long 0x0 15. "MSIX_DOORBELL_VF_ACTIVE,MSIX Doorbell Virtual Function Active. This register determines whether a Virtual Function is used to generate the MSI-X transaction." "0,1" newline bitfld.long 0x0 12.--14. "MSIX_DOORBELL_TC,MSIX Doorbell Traffic Class. This register determines which traffic class to generate the MSI-X transaction with." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 11. "MSIX_DOORBELL_RESERVED_11,Reserved." "0,1" newline hexmask.long.word 0x0 0.--10. 1. "MSIX_DOORBELL_VECTOR,MSI-X Doorbell Vector. This register determines which vector to generate the MSI-X transaction for." group.long (0x24C+0x700)++0x3 line.long 0x0 "MSIX_RAM_CTRL_OFF,MSI-X RAM power mode and debug control register. When you enable the MSI-X Table RAM feature (MSIX_TABLE_EN=1). the controller implements the logic and RAM required to generate MSI-X requests. For more details. see the Interrupts.." hexmask.long.byte 0x0 26.--31. 1. "MSIX_RAM_CTRL_RESERVED_26_31,Reserved. Note: This register field is sticky." newline bitfld.long 0x0 25. "MSIX_RAM_CTRL_DBG_PBA,MSIX PBA RAM Debug Mode. Use this bit to activate the debug mode and allow direct read/write access to the PBA. Use can also use the dbg_pba input to activate debug mode. Debug mode turns off the PF/VF/Offset-based addressing into.." "0,1" newline bitfld.long 0x0 24. "MSIX_RAM_CTRL_DBG_TABLE,MSIX Table RAM Debug Mode. Use this bit to activate the debug mode and allow direct read/write access to the Table. Use can also use the dbg_table input to activate debug mode. Debug mode turns off the PF/VF/Offset-based.." "0,1" newline hexmask.long.byte 0x0 17.--23. 1. "MSIX_RAM_CTRL_RESERVED_17_23,Reserved. Note: This register field is sticky." newline bitfld.long 0x0 16. "MSIX_RAM_CTRL_BYPASS,MSIX RAM Control Bypass. The bypass field when set disables the internal generation of low power signals for both RAMs. It is up to the application to ensure the RAMs are in the proper power state before trying to access them." "0,1" newline hexmask.long.byte 0x0 10.--15. 1. "MSIX_RAM_CTRL_RESERVED_10_15,Reserved. Note: This register field is sticky." newline bitfld.long 0x0 9. "MSIX_RAM_CTRL_PBA_SD,MSIX PBA RAM Shut Down. Set this bit to drive the cfg_msix_pba_sd output to signal your external logic to place the MSIX PBA RAM in Shut Down low-power mode. Note: This register field is sticky." "0,1" newline bitfld.long 0x0 8. "MSIX_RAM_CTRL_PBA_DS,MSIX PBA RAM Deep Sleep. Set this bit to drive the cfg_msix_pba_ds output to signal your external logic to place the MSIX PBA RAM in Deep Sleep low-power mode. Note: This register field is sticky." "0,1" newline hexmask.long.byte 0x0 2.--7. 1. "MSIX_RAM_CTRL_RESERVED_2_7,Reserved. Note: This register field is sticky." newline bitfld.long 0x0 1. "MSIX_RAM_CTRL_TABLE_SD,MSIX Table RAM Shut Down. Set this bit to drive the cfg_msix_table_sd output to signal your external logic to place the MSIX Table RAM in Shut Down low-power mode. Note: This register field is sticky." "0,1" newline bitfld.long 0x0 0. "MSIX_RAM_CTRL_TABLE_DS,MSIX Table RAM Deep Sleep. Set this bit to drive the cfg_msix_table_ds output to signal your external logic to place the MSIX Table RAM in Deep Sleep low-power mode. Note: This register field is sticky." "0,1" group.long (0x430+0x700)++0x3 line.long 0x0 "PL_LTR_LATENCY_OFF,LTR Latency Register. The function of this register field (and all other fields in this register) differs between an upstream port and a downstream port. For an upstream port. the register fields capture the corresponding fields in the.." bitfld.long 0x0 31. "NO_SNOOP_LATENCY_REQUIRE,No Snoop Latency Requirement. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" "0,1" newline rbitfld.long 0x0 29.--30. "RSVDP_29,Reserved for future use." "0,1,2,3" newline bitfld.long 0x0 26.--28. "NO_SNOOP_LATENCY_SCALE,No Snoop Latency Scale. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" "0,1,2,3,4,5,6,7" newline hexmask.long.word 0x0 16.--25. 1. "NO_SNOOP_LATENCY_VALUE,No Snoop Latency Value. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" newline bitfld.long 0x0 15. "SNOOP_LATENCY_REQUIRE,Snoop Latency Requirement. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" "0,1" newline rbitfld.long 0x0 13.--14. "RSVDP_13,Reserved for future use." "0,1,2,3" newline bitfld.long 0x0 10.--12. "SNOOP_LATENCY_SCALE,Snoop Latency Scale. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" "0,1,2,3,4,5,6,7" newline hexmask.long.word 0x0 0.--9. 1. "SNOOP_LATENCY_VALUE,Snoop Latency Value. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" group.long (0x440+0x700)++0xB line.long 0x0 "AUX_CLK_FREQ_OFF,Auxiliary Clock Frequency Control Register." hexmask.long.tbyte 0x0 10.--31. 1. "RSVDP_10,Reserved for future use." newline hexmask.long.word 0x0 0.--9. 1. "AUX_CLK_FREQ,The aux_clk frequency in MHz. This value is used to provide a 1 us reference for counting time during low-power states with aux_clk when the PHY has removed the pipe_clk. Frequencies lower than 1 MHz are possible but with a loss of accuracy.." line.long 0x4 "L1_SUBSTATES_OFF,L1 Substates Timing Register." hexmask.long.tbyte 0x4 9.--31. 1. "RSVDP_9,Reserved for future use." newline bitfld.long 0x4 8. "L1SUB_LOW_POWER_CLOCK_SWITCH_MODE,If this bit is set to 1'b1 the reference clock will be running regardless of the CLKREQ# setting. If this bit is set to 1'b0 the reference clock may be gated off when CLKREQ# is de-asserted. If the bit is set to 1'b1 the.." "0,1" newline bitfld.long 0x4 6.--7. "L1SUB_T_PCLKACK,Max delay (in 1us units) between a MAC request to remove the clock on mac_phy_pclkreq_n and a PHY response on phy_mac_pclkack_n. If the PHY does not respond within this time the request is aborted.The actual timeout value will be.." "0,1,2,3" newline hexmask.long.byte 0x4 2.--5. 1. "L1SUB_T_L1_2,Duration (in 1us units) of L1.2. The actual timeout value will be L1SUB_T_L1_2 + 1. Range is 0.15. Note: This register field is sticky." newline bitfld.long 0x4 0.--1. "L1SUB_T_POWER_OFF,Duration (in 1us units) of L1.2.Entry. The actual timeout value will be L1SUB_T_POWER_OFF + 1. Range is 0.3. Note: This register field is sticky." "0,1,2,3" line.long 0x8 "POWERDOWN_CTRL_STATUS_OFF,Powerdown Control and Status Register." hexmask.long.tbyte 0x8 12.--31. 1. "RSVDP_12,Reserved for future use." newline hexmask.long.byte 0x8 8.--11. 1. "POWERDOWN_PHY_POWERDOWN,This field represents the Powerdown value that has been acknowledged by the PHY. It is updated with the value of Powerdown driven by the controller when the PHY has returned the Phystatus acknowledgment for the Powerdown.." newline hexmask.long.byte 0x8 4.--7. 1. "POWERDOWN_MAC_POWERDOWN,This field represents the Powerdown value driven by the controller to the PHY." newline rbitfld.long 0x8 1.--3. "RSVDP_1,Reserved for future use." "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 0. "POWERDOWN_FORCE,This field is a one shot field. Writing a value of 1 to this field causes the controller to complete the P2 Powerdown handshake regardless of whether the PHY has returned Phystatus. This field could be used for debug purposes in event.." "0,1" group.long (0x470+0x700)++0x7 line.long 0x0 "PHY_VIEWPORT_CTLSTS_OFF,PHY Register Viewport Control and Status Register." rbitfld.long 0x0 31. "PHY_VIEWPORT_PENDING,PHY viewport pending. Indicates the access is pending. - 1 : Pending - 0 : Idle This bit is set to 1 when the read/write access has been initiated. This bit is cleared when the access is completed. If phy_reg_clk_g is never activated.." "Idle,Pending" newline rbitfld.long 0x0 30. "PHY_VIEWPORT_STATUS,PHY viewport status. Indicates the status of the latest access. - 1 : Timeout - 0 : No errors If the timeout is detected this bit is set to 1 and PHY_VIEWPORT_PENDING is cleared. This bit is cleared when the read/write access is.." "No errors,Timeout" newline hexmask.long.byte 0x0 23.--29. 1. "RSVDP_23,Reserved for future use." newline bitfld.long 0x0 22. "PHY_VIEWPORT_TIMEOUT_DISABLE,PHY viewport timeout disable. Disables the PHY register access timeout structure. When the timeout is disabled you must ensure that the PHY register accesses are always acknowledged by cr_para_ack. Otherwise.." "0,1" newline bitfld.long 0x0 21. "PHY_VIEWPORT_BCWR,Broadcast write access to all xN sub-blocks. If you need to broadcast the write accesses into all lanes both PHY_VIEWPORT_ADDR[15] and this bit should be 1. Note: This register field is sticky." "0,1" newline bitfld.long 0x0 20. "PHY_VIEWPORT_READ,PHY viewport read. If set a read access is initiated. The value is always 0 when this bit is read. Note: This register field is sticky." "0,1" newline hexmask.long.byte 0x0 16.--19. 1. "PHY_VIEWPORT_NUM,PHY viewport xN sub-block number. Selects one of xN sub-blocks. This register is not used when the write access is initiated with PHY_VIEWPORT_BCWR==1. Note: This register field is sticky." newline hexmask.long.word 0x0 0.--15. 1. "PHY_VIEWPORT_ADDR,PHY viewport address. Indicates the PHY's register address. Please refer to the PHY databook for the address map definition. Note: This register field is sticky." line.long 0x4 "PHY_VIEWPORT_DATA_OFF,PHY Register Viewport Data Register." hexmask.long.word 0x4 16.--31. 1. "RSVDP_16,Reserved for future use." newline hexmask.long.word 0x4 0.--15. 1. "PHY_VIEWPORT_DATA,PHY viewport data. A write access to this register initiates the PHY register write access. By a read access to this register this field returns the latest read data from the PHY register. Note: This register field is sticky." group.long (0x490+0x700)++0x3 line.long 0x0 "PIPE_RELATED_OFF,PIPE Related Register. This register controls the pipe's capabitity. control. and status parameters." hexmask.long.tbyte 0x0 9.--31. 1. "RSVDP_9,Reserved for future use." newline bitfld.long 0x0 8. "PIPE_GARBAGE_DATA_MODE,PIPE Garbage Data Mode. - 0: PIPE Spec compliant mode: The MAC discards any symbols received after the electrical idle ordered-set until RxValid is deasserted. - 1: Special PHY Support mode: The MAC discards any symbols received.." "PIPE Spec compliant mode: The MAC discards any..,Special PHY Support mode: The MAC discards any.." tree.end tree.end tree "PCIE1_VF45" base ad:0x31080000 tree "PF0_TYPE1_HDR (PCI-Compatible Configuration Space Header Type1)" group.long 0x0++0x2F line.long 0x0 "TYPE1_DEV_ID_VEND_ID_REG,Device ID and Vendor ID Register." hexmask.long.word 0x0 16.--31. 1. "DEVICE_ID,Device ID. The Device ID register identifies the particular Function. This identifier is allocated by the vendor. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else.." newline hexmask.long.word 0x0 0.--15. 1. "VENDOR_ID,Vendor ID. The Vendor ID register identifies the manufacturer of the Function. Valid vendor identifiers are allocated by the PCI-SIG to ensure uniqueness. It is not permitted to populate this register with a value of FFFFh which is an invalid.." line.long 0x4 "TYPE1_STATUS_COMMAND_REG,Status and Command Register." bitfld.long 0x4 31. "DETECTED_PARITY_ERROR,Detected Parity Error. This bit is set by a Function whenever it receives a Poisoned TLP regardless of the state the Parity Error Response bit in the Command register. The bit is set when the Poisoned TLP is received by a.." "0,1" newline bitfld.long 0x4 30. "SIGNALED_SYS_ERROR,Signaled System Error. This bit is set when a Function sends an ERR_FATAL or ERR_NONFATAL Message and the SERR# Enable bit in the Command register is 1b." "0,1" newline bitfld.long 0x4 29. "RCVD_MASTER_ABORT,Received Master Abort. This bit is set when a Requester receives a Completion with Unsupported Request Completion status. The bit is set when the Unsupported Request is received by a Function's primary side." "0,1" newline bitfld.long 0x4 28. "RCVD_TARGET_ABORT,Received Target Abort. This bit is set when a Requester receives a Completion with Completer Abort Completion status. The bit is set when the Completer Abort is received by a Function's primary side." "0,1" newline bitfld.long 0x4 27. "SIGNALED_TARGET_ABORT,Signaled Target Abort. This bit is set when a Function completes a Posted or Non-Posted Request as a Completer Abort error. This applies to a Function when the Completer Abort was generated by its primary side." "0,1" newline rbitfld.long 0x4 25.--26. "DEV_SEL_TIMING,DEVSEL Timing. This field was originally described in the PCI Local Bus Specification. Its functionality does not apply to PCI Express. The controller hardwires it to 00b." "0,1,2,3" newline bitfld.long 0x4 24. "MASTER_DPE,Master Data Parity Error. This bit is set by a Function if the Parity Error Response bit in the Command register is 1b and either of the following two conditions occurs: - Port receives a Poisoned Completion going downstream - Port transmits a.." "0,1" newline rbitfld.long 0x4 23. "FAST_B2B_CAP,Fast Back-to-Back Transactions Capable. This bit was originally described in the PCI Local Bus Specification. Its functionality does not apply to PCI Express. The controller hardwires this bit to 0b." "0,1" newline rbitfld.long 0x4 22. "RSVDP_22,Reserved for future use." "0,1" newline rbitfld.long 0x4 21. "FAST_66MHZ_CAP,66 MHz Capable. This bit was originally described in the PCI Local Bus Specification. Its functionality does not apply to PCI Express. The controller hardwires this bit to 0b." "0,1" newline rbitfld.long 0x4 20. "CAP_LIST,Capabilities List. Indicates the presence of an Extended Capability list item. Since all PCI Express device Functions are required to implement the PCI Express Capability structure the controller hardwires this bit to 1b." "0,1" newline rbitfld.long 0x4 19. "INT_STATUS,Interrupt Status. When set indicates that an INTx emulation interrupt is pending internally in the Function. INTx emulation interrupts forwarded by Functions from the secondary side are not reflected in this bit. Setting the Interrupt Disable.." "0,1" newline rbitfld.long 0x4 17.--18. "RSVDP_17,Reserved for future use." "0,1,2,3" newline bitfld.long 0x4 16. "IMM_READINESS,Immediate Readiness. This optional bit when set indicates the Function is guaranteed to be ready to successfully complete valid configuration accesses at any time following any reset that the host is capable of issuing Configuration.." "0,1" newline hexmask.long.byte 0x4 11.--15. 1. "RESERV,Reserved." newline bitfld.long 0x4 10. "INT_EN,Interrupt Disable. Controls the ability of a Function to generate INTx emulation interrupts. When set Functions are prevented from asserting INTx interrupts. Note: - Any INTx emulation interrupts already asserted by the Function must be.." "0,1" newline rbitfld.long 0x4 9. "RSVDP_9,Reserved for future use." "0,1" newline bitfld.long 0x4 8. "SERREN,SERR# Enable. When set this bit enables reporting upstream of Non-fatal and Fatal errors detected by the Function. Note: The errors are reported if enabled either through this bit or through the PCI Express specific bits in the Device Control.." "0,1" newline rbitfld.long 0x4 7. "IDSEL,IDSEL Stepping/Wait Cycle Control. This bit was originally described in the PCI Local Bus Specification. Its functionality does not apply to PCI Express. The controller hardwires this bit to 0b." "0,1" newline bitfld.long 0x4 6. "PERREN,Parity Error Response. This bit controls the logging of poisoned TLPs in the Master Data Parity Error bit in the Status register. For more details see the 'Error Registers' section of the PCI Express Base Specification." "0,1" newline rbitfld.long 0x4 5. "VGAPS,VGA Palette Snoop. This bit was originally described in the PCI Local Bus Specification and the PCI-to-PCI Bridge Architecture Specification. Its functionality does not apply to PCI Express. The controller hardwires this bit to 0b." "0,1" newline rbitfld.long 0x4 4. "MWI_EN,Memory Write and Invalidate. This bit was originally described in the PCI Local Bus Specification and the PCI-to-PCI Bridge Architecture Specification. Its functionality does not apply to PCI Express. The controller hardwires this bit to 0b. For.." "0,1" newline rbitfld.long 0x4 3. "SCO,Special Cycle Enable. This bit was originally described in the PCI Local Bus Specification. Its functionality does not apply to PCI Express. The controller hardwires this bit to 0b." "0,1" newline bitfld.long 0x4 2. "BME,Bus Master Enable. This bit controls forwarding of Memory or I/O requests by a port in the Upstream direction. When this bit is 0b Memory and I/O Requests received at a Root Port must be handled as Unsupported Requests (UR) For Non-Posted Requests a.." "0,1" newline bitfld.long 0x4 1. "MSE,Memory Space Enable. This bit controls a Function's response to Memory Space accesses received on its primary side. - When set the Function is enabled to decode the address and further process Memory Space accesses. - When clear all received Memory.." "0,1" newline bitfld.long 0x4 0. "IO_EN,IO Space Enable. This bit controls a Function's response to I/O Space accesses received on its primary side. - When set the Function is enabled to decode the address and further process I/O Space accesses. - When clear all received I/O accesses.." "0,1" line.long 0x8 "TYPE1_CLASS_CODE_REV_ID_REG,Class Code and Revision ID Register." hexmask.long.byte 0x8 24.--31. 1. "BASE_CLASS_CODE,Base Class Code. A code that broadly classifies the type of operation the Function performs. Encodings for base class are provided in the PCI Code and ID Assignment Specification. All unspecified encodings are reserved. Note: The access.." newline hexmask.long.byte 0x8 16.--23. 1. "SUBCLASS_CODE,Sub-Class Code. Specifies a base class sub-class which identifies more specifically the operation of the Function. Encodings for sub-class are provided in the PCI Code and ID Assignment Specification. All unspecified encodings are.." newline hexmask.long.byte 0x8 8.--15. 1. "PROGRAM_INTERFACE,Programming Interface. This field identifies a specific register level programming interface (if any) so that device independent software can interact with the Function. Encodings for interface are provided in the PCI Code and ID.." newline hexmask.long.byte 0x8 0.--7. 1. "REVISION_ID,Revision ID. The value of this field specifies a Function specific revision identifier. The value is chosen by the vendor. Zero is an acceptable value. The Revision ID should be viewed as a vendor defined extension to the Device ID. Note: The.." line.long 0xC "TYPE1_BIST_HDR_TYPE_LAT_CACHE_LINE_SIZE_REG,BIST. Header Type. Latency Timer. and Cache Line Size Register." hexmask.long.byte 0xC 24.--31. 1. "BIST,BIST. This register is used for control and status of BIST. Functions that do not support BIST must hardwire the register to 00h. A Function whose BIST is invoked must not prevent normal operation of the PCI Express Link. Bit descriptions: - [31]:.." newline rbitfld.long 0xC 23. "MULTI_FUNC,Multi-Function Device. - When set indicates that the device may contain multiple Functions but not necessarily. Software is permitted to probe for Functions other than Function 0. - When clear software must not probe for Functions other.." "0,1" newline hexmask.long.byte 0xC 16.--22. 1. "HEADER_TYPE,Header Layout. This field identifies the layout of the second part of the predefined header. The controller uses 000 0001b encoding. The encoding 000 0010b is reserved. This encoding was originally described in the PC Card Standard Electrical.." newline hexmask.long.byte 0xC 8.--15. 1. "LATENCY_MASTER_TIMER,Latency Timer. This register is also referred to as Primary Latency Timer. The Latency Timer was originally described in the PCI Local Bus Specification and the PCI-to-PCI Bridge Architecture Specification. Its functionality does not.." newline hexmask.long.byte 0xC 0.--7. 1. "CACHE_LINE_SIZE,Cache Line Size. The Cache Line Size register is programmed by the system firmware or the operating system to system cache line size. However legacy conventional PCI software may not always be able to program this register correctly.." line.long 0x10 "BAR0_REG,BAR0 Register. System software must build a consistent address map before booting the machine to an operating system. This means it has to determine how much memory is in the system. and how much address space the Functions in the system.." hexmask.long 0x10 4.--31. 1. "BAR0_START,BAR0 Base Address. - Memory Space: Base Address. - IO Space: bits[31:2] are used to map the function into IO space/Base. Address. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R(Sticky)/W(Sticky) if.." newline bitfld.long 0x10 3. "BAR0_PREFETCH,BAR0 Prefetchable. - Memory Space: Set to one if data is pre-fetchable. A Function is permitted to mark a range as prefetchable. If there are no side effects on reads the function returns all bytes on reads regardless of the byte enables.." "0,1" newline bitfld.long 0x10 1.--2. "BAR0_TYPE,BAR0 Type. - Memory Space: Base Address registers that map into Memory Space can be 32 bits or 64 bits wide (to support mapping into a 64-bit address space). The bit encoding is as follows: -- 00: Base register is 32 bits wide and can be mapped.." "Base register is 32 bits wide and can be mapped..,Reserved,?,?" newline bitfld.long 0x10 0. "BAR0_MEM_IO,BAR0 Memory Space Indicator. This bit is used to determine whether the register maps into Memory or I/O Space. Base Address registers that map to Memory Space must return a 0b. Base Address registers that map to I/O Space must return a 1b." "0,1" line.long 0x14 "BAR1_REG,BAR1 Register. System software must build a consistent address map before booting the machine to an operating system. This means it has to determine how much memory is in the system. and how much address space the Functions in the system.." hexmask.long 0x14 4.--31. 1. "BAR1_START,BAR1 Base Address. - Memory Space: Base Address. - IO Space: bits[31:2] are used to map the function into IO space/Base. Address. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R(Sticky)/W(Sticky) if.." newline bitfld.long 0x14 3. "BAR1_PREFETCH,BAR1 Prefetchable. - Memory Space: Set to one if data is pre-fetchable. A Function is permitted to mark a range as prefetchable. If there are no side effects on reads the function returns all bytes on reads regardless of the byte enables.." "0,1" newline bitfld.long 0x14 1.--2. "BAR1_TYPE,BAR1 Type. - Memory Space: Base Address registers that map into Memory Space can be 32 bits or 64 bits wide (to support mapping into a 64-bit address space). The bit encoding is as follows: -- 00: Base register is 32 bits wide and can be mapped.." "Base register is 32 bits wide and can be mapped..,Reserved,?,?" newline bitfld.long 0x14 0. "BAR1_MEM_IO,BAR1 Memory Space Indicator. This bit is used to determine whether the register maps into Memory or I/O Space. Base Address registers that map to Memory Space must return a 0b. Base Address registers that map to I/O Space must return a 1b." "0,1" line.long 0x18 "SEC_LAT_TIMER_SUB_BUS_SEC_BUS_PRI_BUS_REG,Secondary Latency Timer. Subordinate Bus Number. Secondary Bus Number. and Primary Bus Number Register." hexmask.long.byte 0x18 24.--31. 1. "SEC_LAT_TIMER,Secondary Latency Timer. This register does not apply to PCI Express. The controller hardwires it to 00h." newline hexmask.long.byte 0x18 16.--23. 1. "SUB_BUS,Subordinate Bus Number. The Subordinate Bus Number register is used to record the bus number of the highest numbered PCI bus segment which is behind (or subordinate to) the bridge. Configuration software programs the value in this register. The.." newline hexmask.long.byte 0x18 8.--15. 1. "SEC_BUS,Secondary Bus Number. The Secondary Bus Number register is used to record the bus number of the PCI bus segment to which the secondary interface of the bridge is connected. Configuration software programs the value in this register. The bridge.." newline hexmask.long.byte 0x18 0.--7. 1. "PRIM_BUS,Primary Bus Number. This register is not used by PCI Express Functions. It is implemented for compatibility with legacy software." line.long 0x1C "SEC_STAT_IO_LIMIT_IO_BASE_REG,Secondary Status. and I/O Limit and Base Register. The I/O Limit and I/O Base registers are optional and define an address range that is used by the bridge to determine when to forward I/O transactions from one interface to.." bitfld.long 0x1C 31. "SEC_STAT_DPE,Detected Parity Error. This bit is set by a Function when a Poisoned TLP is received by its secondary side regardless of the state the Parity Error Response Enable bit in the Bridge Control register." "0,1" newline bitfld.long 0x1C 30. "SEC_STAT_RCVD_SYS_ERR,Received System Error. This bit is set when the secondary side of a Function receives an ERR_FATAL or ERR_NONFATAL message." "0,1" newline bitfld.long 0x1C 29. "SEC_STAT_RCVD_MSTR_ABRT,Received Master Abort. This bit is set when the secondary side of a Function (for requests initiated by the Type 1 header Function itself) receives a Completion with Unsupported Request Completion status." "0,1" newline bitfld.long 0x1C 28. "SEC_STAT_RCVD_TRGT_ABRT,Received Target Abort. This bit is set when the secondary side of a Function (for requests initiated by the Type 1 header Function itself) receives a Completion with Completer Abort Completion status." "0,1" newline bitfld.long 0x1C 27. "SEC_STAT_SIG_TRGT_ABRT,Signaled Target Abort. This bit is set when the secondary side of the Function (for Requests completed by the Type 1 header Function itself) completes a Posted or Non-Posted request as a Completer Abort error." "0,1" newline rbitfld.long 0x1C 25.--26. "RSVDP_25,Reserved for future use." "0,1,2,3" newline bitfld.long 0x1C 24. "SEC_STAT_MDPE,Master Data Parity Error. This bit is set by a Function if the Parity Error Response Enable bit in the Bridge Control register is set and either of the following two conditions occurs: - Port receives a Poisoned Completion coming Upstream.." "0,1" newline rbitfld.long 0x1C 23. "RSVDP_23,Reserved for future use." "0,1" newline hexmask.long.byte 0x1C 16.--22. 1. "SEC_STAT_RESERV,Reserved." newline hexmask.long.byte 0x1C 12.--15. 1. "IO_LIMIT,I/O Limit Address. These bits correspond to the address[15:12] of IO address range. For the purpose of address decoding the bridge assumes that the lower 12 address bits address[11:0] of the I/O limit address (not implemented in the I/O Limit.." newline rbitfld.long 0x1C 9.--11. "IO_RESERV1,Reserved." "0,1,2,3,4,5,6,7" newline bitfld.long 0x1C 8. "IO_DECODE_BIT8,I/O Addressing Encode (IO Limit Address). This bit encodes the IO addressing capability of the bridge. IO_DECODE_BIT8 indicates the following: - 0h: The bridge supports only 16-bit I/O addressing (for ISA compatibility). For the purpose of.." "0,1" newline hexmask.long.byte 0x1C 4.--7. 1. "IO_BASE,I/O Base Address. These bits correspond to the address[15:12] of IO address range. For the purpose of address decoding the bridge assumes that the lower 12 address bits address[11:0] of the I/O base address (not implemented in the I/O Base.." newline rbitfld.long 0x1C 1.--3. "IO_RESERV,Reserved." "0,1,2,3,4,5,6,7" newline bitfld.long 0x1C 0. "IO_DECODE,I/O Addressing Encode (IO Base Address) This bit encodes the IO addressing capability of the bridge. IO_DECODE indicates the following: - 0h: The bridge supports only 16-bit I/O addressing (for ISA compatibility). For the purpose of address.." "0,1" line.long 0x20 "MEM_LIMIT_MEM_BASE_REG,Memory Limit and Base Register. The Memory Limit and Memory Base registers define a memory mapped address range which is used by the bridge to determine when to forward memory transactions from one interface to the other. If there.." hexmask.long.word 0x20 20.--31. 1. "MEM_LIMIT,Memory Limit Address. These bits correspond to the upper 12 address bits Address[31:20] of 32-bit addresses. For the purpose of address decoding the bridge assumes that the lower 20 address bits Address[19:0] of the memory limit address.." newline hexmask.long.byte 0x20 16.--19. 1. "MEM_LIMIT_RESERV,Reserved." newline hexmask.long.word 0x20 4.--15. 1. "MEM_BASE,Memory Base Address. These bits correspond to the upper 12 address bits Address[31:20] of 32-bit addresses. For the purpose of address decoding the bridge assumes that the lower 20 address bits Address[19:0] of the memory base address (not.." newline hexmask.long.byte 0x20 0.--3. 1. "MEM_BASE_RESERV,Reserved." line.long 0x24 "PREF_MEM_LIMIT_PREF_MEM_BASE_REG,Prefetchable Memory Limit and Base Register. The Prefetchable Memory Limit and Prefetchable Memory Base registers must indicate that 64-bit addresses are supported. as defined in PCI-to-PCI Bridge Architecture.." hexmask.long.word 0x24 20.--31. 1. "PREF_MEM_LIMIT,Prefetchable Memory Limit Address. If the Prefetchable Memory Limit register indicates support for 32-bit addressing then the Prefetchable Limit Upper 32 Bits register is implemented as a read-only register that returns zero when read. If.." newline rbitfld.long 0x24 17.--19. "PREF_RESERV1,Reserved." "0,1,2,3,4,5,6,7" newline rbitfld.long 0x24 16. "PREF_MEM_LIMIT_DECODE,Prefetchable Memory Limit Decode. This bit encodes whether or not the bridge supports 64-bit addresses. Note: This bit is a copy of the PREF_MEM_DECODE bit and always reflects the current value of that bit. The value of.." "0,1" newline hexmask.long.word 0x24 4.--15. 1. "PREF_MEM_BASE,Prefetchable Memory Base Address. If the Prefetchable Memory Base register indicates support for 32-bit addressing then the Prefetchable Base Upper 32 Bits register is implemented as a read-only register that returns zero when read. If the.." newline rbitfld.long 0x24 1.--3. "PREF_RESERV,Reserved." "0,1,2,3,4,5,6,7" newline bitfld.long 0x24 0. "PREF_MEM_DECODE,Prefetchable Memory Base Decode. This bit encodes whether or not the bridge supports 64-bit addresses. Note: By default the bit is set to 1'b1 indicating that 64-bit addresses are supported. If the bridge only supports 32-bit prefetchable.." "0,1" line.long 0x28 "PREF_BASE_UPPER_REG,Prefetchable Base Upper 32 Bits Register. The Prefetchable Base Upper 32 Bits register is an optional extension to the Prefetchable Memory Base register." hexmask.long 0x28 0.--31. 1. "PREF_MEM_BASE_UPPER,Prefetchable Base Upper 32 Bit. If the Prefetchable Memory Base register indicates support for 32-bit addressing then this register is implemented as read-only register that returns zero when read. If the Prefetchable Memory Base.." line.long 0x2C "PREF_LIMIT_UPPER_REG,Prefetchable Limit Upper 32 Bits Register. The Prefetchable Limit Upper 32 Bits register is an optional extension to the Prefetchable Memory Limit register." hexmask.long 0x2C 0.--31. 1. "PREF_MEM_LIMIT_UPPER,Prefetchable Limit Upper 32 Bit. If the Prefetchable Memory Limit register indicate support for 64-bit addressing then this register is implemented as read/write register which must be initialized by configuration software. This.." rgroup.long 0x30++0x3 line.long 0x0 "IO_LIMIT_UPPER_IO_BASE_UPPER_REG,I/O Limit and Base Upper 16 Bits Register. The I/O Limit Upper 16 Bits and I/O Base Upper 16 Bits registers are optional extensions to the I/O Limit and I/O Base registers." hexmask.long.word 0x0 16.--31. 1. "IO_LIMIT_UPPER,I/O Limit Upper 16 Bits. If the I/O Limit register indicates support for 16-bit I/O address decoding then this register is implemented as a read-only register which return zero when read. If the I/O Limit register indicates support for.." newline hexmask.long.word 0x0 0.--15. 1. "IO_BASE_UPPER,I/O Base Upper 16 Bits. If the I/O Base register indicates support for 16-bit I/O address decoding then this register is implemented as a read-only register which return zero when read. If the I/O base register indicates support for 32-bit.." group.long 0x34++0xB line.long 0x0 "TYPE1_CAP_PTR_REG,Capabilities Pointer Register." hexmask.long.tbyte 0x0 8.--31. 1. "RSVDP_8,Reserved for future use." newline hexmask.long.byte 0x0 0.--7. 1. "CAP_POINTER,Capabilities Pointer. This register is used to point to a linked list of capabilities implemented by this Function. Since all PCI Express Functions are required to implement the PCI Express Capability structure this register must point to a.." line.long 0x4 "TYPE1_EXP_ROM_BASE_REG,Expansion ROM Base Address Register. This register is defined to handle the base address and size information for this expansion ROM. The mask for this ROM BAR exists (if implemented) as a shadow register at this address. The.." hexmask.long.tbyte 0x4 11.--31. 1. "EXP_ROM_BASE_ADDRESS,Expansion ROM Base Address. Upper 21 bits of the Expansion ROM base address. The number of bits (out of these 21) that a Function actually implements depends on how much address space the Function requires. The mask for this ROM BAR.." newline hexmask.long.word 0x4 1.--10. 1. "RSVDP_1,Reserved for future use." newline bitfld.long 0x4 0. "ROM_BAR_ENABLE,Expansion ROM Enable. This bit controls whether or not the Function accepts accesses to its expansion ROM. When this bit is 0b the Function's expansion ROM address space is disabled. When the bit is 1b address decoding is enabled using.." "0,1" line.long 0x8 "BRIDGE_CTRL_INT_PIN_INT_LINE_REG,Bridge Control. Interrupt Pin. and Interrupt Line Register." hexmask.long.word 0x8 23.--31. 1. "BRIDGE_CTRL_RESERV,Reserved." newline bitfld.long 0x8 22. "SBR,Secondary Bus Reset. Setting this bit triggers a hot reset on the corresponding PCI Express Port. Software must ensure a minimum reset duration (Trst) as defined in the PCI Local Bus Specification. Software and systems must honor.." "0,1" newline rbitfld.long 0x8 21. "MSTR_ABORT_MODE,Master Abort Mode. This bit was originally described in the PCI-to-PCI Bridge Architecture Specification. Its functionality does not apply to PCI Express. The controller hardwires this bit to 0b. Note: The access attributes of this field.." "0,1" newline rbitfld.long 0x8 20. "VGA_16B_DEC,VGA 16 bit decode. This bit only has meaning if VGA Enable bit is set. This bit enables system configuration software to select between 10-bit and 16-bit I/O address decoding for all VGA I/O register accesses that are forwarded from primary.." "0,1" newline rbitfld.long 0x8 19. "VGA_EN,VGA Enable. Modifies the response by the bridge to VGA compatible addresses. If the VGA Enable bit is set the bridge will positively decode and forward the following accesses on the primary interface to the secondary interface (and conversely.." "0,1" newline bitfld.long 0x8 18. "ISA_EN,ISA Enable. Modifies the response by the bridge to ISA I/O addresses. This applies only to I/O addresses that are enabled by the I/O Base and I/O Limit registers and are in the first 64 KB of I/O address space (0000 0000h to 0000 FFFFh). If this.." "?,KB block" newline bitfld.long 0x8 17. "SERR_EN,SERR# Enable. This bit controls forwarding of ERR_COR ERR_NONFATAL and ERR_FATAL from secondary to primary." "0,1" newline bitfld.long 0x8 16. "PERE,Parity Error Response Enable. This bit controls the logging of poisoned TLPs in the Master Data Parity Error bit in the Secondary Status register." "0,1" newline hexmask.long.byte 0x8 8.--15. 1. "INT_PIN,Interrupt PIN. The Interrupt Pin register register that identifies the legacy interrupt Message(s) the Function uses. Valid values are: - 01h 02h 03h and 04h: map to legacy interrupt Messages for INTA INTB INTC and INTD respectively. - 00h:.." newline hexmask.long.byte 0x8 0.--7. 1. "INT_LINE,Interrupt Line. The Interrupt Line register communicates interrupt line routing information. The register must be implemented by any Function that uses an interrupt pin. Values in this register are programmed by system software and are system.." tree.end tree "PF0_SPCIE_CAP (Secondary PCI Express Capability Structure)" group.long (0x0+0x1A0)++0xF line.long 0x0 "SPCIE_CAP_HEADER_REG,SPCIE Capability Header. For a description of this standard PCIe register. see the PCI Express Specification." hexmask.long.word 0x0 20.--31. 1. "NEXT_OFFSET,Next Capability Offset. For a description of this standard PCIe register field see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky).." hexmask.long.byte 0x0 16.--19. 1. "CAP_VERSION,Capability Version. For a description of this standard PCIe register field see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else.." hexmask.long.word 0x0 0.--15. 1. "EXTENDED_CAP_ID,Secondary PCI Express Extended Capability ID. For a description of this standard PCIe register field see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN.." line.long 0x4 "LINK_CONTROL3_REG,Link Control 3 Register. For a description of this standard PCIe register. see the PCI Express Specification." hexmask.long 0x4 2.--31. 1. "RSVDP_2,Reserved for future use." bitfld.long 0x4 1. "EQ_REQ_INT_EN,Link Equalization Request Interrupt Enable. For a description of this standard PCIe register field see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" "0,1" bitfld.long 0x4 0. "PERFORM_EQ,Perform Equalization. For a description of this standard PCIe register field see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" "0,1" line.long 0x8 "LANE_ERR_STATUS_REG,Lane Error Status Register. For a description of this standard PCIe register. see the PCI Express Specification." hexmask.long 0x8 2.--31. 1. "RSVDP_LANE_ERR_STATUS,Reserved for future use." bitfld.long 0x8 0.--1. "LANE_ERR_STATUS,Lane Error Status Bits per Lane. For a description of this standard PCIe register field see the PCI Express Specification." "0,1,2,3" line.long 0xC "SPCIE_CAP_OFF_0CH_REG,Lane Equalization Control Register for lanes 1 and 0. For a description of this standard PCIe register. see the PCI Express Specification." rbitfld.long 0xC 31. "RSVDP_31,Reserved for future use." "0,1" bitfld.long 0xC 28.--30. "USP_RX_PRESET_HINT1,Upstream Port 8.0 GT/s Receiver Preset Hint 1. The write value is gated with the PCIE_CAP_CROSS_LINK_SUPPORT field of LINK_CAPABILITIES2_REG. For a description of this standard PCIe register field see the PCI Express Specification." "0,1,2,3,4,5,6,7" hexmask.long.byte 0xC 24.--27. 1. "USP_TX_PRESET1,Upstream Port 8.0 GT/s Transmitter Preset 1. The write value is gated with the PCIE_CAP_CROSS_LINK_SUPPORT field of LINK_CAPABILITIES2_REG. For a description of this standard PCIe register field see the PCI Express Specification. Note:.." rbitfld.long 0xC 23. "RSVDP_23,Reserved for future use." "0,1" newline bitfld.long 0xC 20.--22. "DSP_RX_PRESET_HINT1,Downstream Port 8.0 GT/s Receiver Preset Hint 1. For a description of this standard PCIe register field see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if.." "0,1,2,3,4,5,6,7" hexmask.long.byte 0xC 16.--19. 1. "DSP_TX_PRESET1,Downstream Port 8.0 GT/s Transmitter Preset 1. For a description of this standard PCIe register field see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN.." rbitfld.long 0xC 15. "RSVDP_15,Reserved for future use." "0,1" bitfld.long 0xC 12.--14. "USP_RX_PRESET_HINT0,Upstream Port 8.0 GT/s Receiver Preset Hint 0. The write value is gated with the PCIE_CAP_CROSS_LINK_SUPPORT field of LINK_CAPABILITIES2_REG. For a description of this standard PCIe register field see the PCI Express Specification." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0xC 8.--11. 1. "USP_TX_PRESET0,Upstream Port 8.0 GT/s Transmitter Preset 0. The write value is gated with the PCIE_CAP_CROSS_LINK_SUPPORT field of LINK_CAPABILITIES2_REG. For a description of this standard PCIe register field see the PCI Express Specification. Note:.." rbitfld.long 0xC 7. "RSVDP_7,Reserved for future use." "0,1" bitfld.long 0xC 4.--6. "DSP_RX_PRESET_HINT0,Downstream Port 8.0 GT/s Receiver Preset Hint 0. For a description of this standard PCIe register field see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if.." "0,1,2,3,4,5,6,7" hexmask.long.byte 0xC 0.--3. 1. "DSP_TX_PRESET0,Downstream Port 8.0 GT/s Transmitter Preset 0. For a description of this standard PCIe register field see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN.." tree.end tree "PF0_L1SUB_CAP (L1 Substates Capability Structure)" group.long (0x0+0x2E8)++0xF line.long 0x0 "L1SUB_CAP_HEADER_REG,L1 Substates Extended Capability Header. This register provides capbility ID. capability version and next offset value for L1 Substates." hexmask.long.word 0x0 20.--31. 1. "NEXT_OFFSET,Next Capability Offset. This field contains the offset to the next PCI Express Capability structure or 000h if no other items exist in the linked list of Capabilities. For Extended Capabilities implemented in Configuration Space this offset.." hexmask.long.byte 0x0 16.--19. 1. "CAP_VERSION,Capability Version. This field is a PCI-SIG defined version number that indicates the version of the Capability structure present. This field is depends on version of the specification. Note: The access attributes of this field are as.." hexmask.long.word 0x0 0.--15. 1. "EXTENDED_CAP_ID,L1SUB Extended Capability ID. This field is a PCI-SIG defined ID number that indicates the nature and format of the Extended Capability. Extended Capability ID for L1 PM Substates is 001Eh. Note: The access attributes of this field are as.." line.long 0x4 "L1SUB_CAPABILITY_REG,L1 Substates Capability Register. This register provides extended capability of L1 Substates." hexmask.long.byte 0x4 24.--31. 1. "RSVDP_24,Reserved for future use." hexmask.long.byte 0x4 19.--23. 1. "PWR_ON_VALUE_SUPPORT,Port T Power On Value. Along with the Port T_POWER_ON Scale field in the L1 PM Substates Capabilities register sets the time (in us) that this Port requires the port on the opposite side of Link to wait in L1.2.Exit after sampling.." rbitfld.long 0x4 18. "RSVDP_18,Reserved for future use." "0,1" bitfld.long 0x4 16.--17. "PWR_ON_SCALE_SUPPORT,Port T Power On Scale. Specifies the scale used for the Port T_POWER_ON Value field in the L1 PM Substates Capabilities register. Range of values are given below. Required for all Ports for which either the PCI-PM L1.2 Supported bit.." "?,?,?,Reserved" newline hexmask.long.byte 0x4 8.--15. 1. "COMM_MODE_SUPPORT,Port Common Mode Restore Time. Time (in us) required for this Port to re-establish common mode. Required for all Ports for which either the PCI-PM L1.2 Supported bit is Set ASPM L1.2 Supported bit is Set or both are Set otherwise.." rbitfld.long 0x4 5.--7. "RSVDP_5,Reserved for future use." "0,1,2,3,4,5,6,7" bitfld.long 0x4 4. "L1_PMSUB_SUPPORT,L1 PM Substates ECN Supported. When Set this bit indicates that this Port supports L1 PM Substates. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W (sticky)" "0,1" bitfld.long 0x4 3. "L1_1_ASPM_SUPPORT,ASPM L11 Supported. When Set this bit indicates that ASPM L1.1 is supported. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W (sticky)" "0,1" newline bitfld.long 0x4 2. "L1_2_ASPM_SUPPORT,ASPM L12 Supported. When Set this bit indicates that ASPM L1.2 is supported. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W (sticky)" "0,1" bitfld.long 0x4 1. "L1_1_PCIPM_SUPPORT,PCI-PM L11 Supported. When Set this bit indicates that PCI-PM L1.1 is supported and must be Set by all Ports implementing L1 PM Substates. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W (sticky)" "0,1" bitfld.long 0x4 0. "L1_2_PCIPM_SUPPORT,PCI-PM L12 Supported. When Set this bit indicates that PCI-PM L1.2 is supported. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W (sticky)" "0,1" line.long 0x8 "L1SUB_CONTROL1_REG,L1 Substates Control 1 Register. This register provides Controls to extended capability." bitfld.long 0x8 29.--31. "L1_2_TH_SCA,LTR L12 Threshold Scale. This field provides a scale for the value contained within the LTR_L1.2_THRESHOLD_Value.The default value for this field is 000b.Hardware operation is undefined if software writes a Not-Permitted value to this field." "0,1,2,3,4,5,6,7" rbitfld.long 0x8 26.--28. "RSVDP_26,Reserved for future use." "0,1,2,3,4,5,6,7" hexmask.long.word 0x8 16.--25. 1. "L1_2_TH_VAL,LTR L12 Threshold Value. Along with the LTR_L1.2_THRESHOLD_Scale this field indicates the LTR threshold used to determine if entry into L1 results in L1.1 (if enabled) or L1.2 (if enabled). The default value for this field is 00 0000 0000b." hexmask.long.byte 0x8 8.--15. 1. "T_COMMON_MODE,Common Mode Restore Time. Sets value of TCOMMONMODE (in us) which must be used by the Downstream Ports for timing the re-establishment of common mode.This field is of type RsvdP for Upstream Ports. Default value is implementation.." newline hexmask.long.byte 0x8 4.--7. 1. "RSVDP_4,Reserved for future use." bitfld.long 0x8 3. "L1_1_ASPM_EN,ASPM L11 Enable. When Set this bit enables ASPM L1.1.For Ports for which the ASPM L1.1 Supported bit is Clear this bit is permitted to be hardwired to 0.Default value is 0b." "0,1" bitfld.long 0x8 2. "L1_2_ASPM_EN,ASPM L12 Enable. When Set this bit enables ASPM L1.2.For Ports for which the ASPM L1.2 Supported bit is Clear this bit is permitted to be hardwired to 0.Default value is 0b." "0,1" bitfld.long 0x8 1. "L1_1_PCIPM_EN,PCI-PM L11 Enable. When Set this bit enables PCI-PM L1.1. Default value is 0b." "0,1" newline bitfld.long 0x8 0. "L1_2_PCIPM_EN,PCI-PM L12 Enable. When Set this bit enables PCI-PM L1.2.For Ports for which the PCI-PM L1.2 Supported bit is Clear this bit is permitted to be hardwired to 0.Default value is 0b." "0,1" line.long 0xC "L1SUB_CONTROL2_REG,L1 Substates Control 2 Register. This register provides Controls to extended capability." hexmask.long.tbyte 0xC 8.--31. 1. "RSVDP_8,Reserved for future use." hexmask.long.byte 0xC 3.--7. 1. "T_POWER_ON_VALUE,T Power On Value. Along with the T_POWER_ON Scale sets the minimum amount of time (in us) that the Port must wait in L1.2.Exit after sampling CLKREQ# asserted before actively driving the interface.Default value is 00101b. T_POWER_ON is.." rbitfld.long 0xC 2. "RSVDP_2,Reserved for future use." "0,1" bitfld.long 0xC 0.--1. "T_POWER_ON_SCALE,T Power On Scale. Specifies the scale used for T_POWER_ON Value. Range of values are given below. Required for all Ports that support L1.2 otherwise this field is of type RsvdP. This field must only be modified when the ASPM L1.2 Enable.." "?,?,?,Reserved" tree.end tree "PF0_RAS_DES_CAP (RAS D.E.S. Capability Structure (VSEC))" group.long (0x0+0x30C)++0x3 line.long 0x0 "RAS_DES_CAP_HEADER_REG,Vendor-Specific Extended Capability Header. For a description of this standard PCIe register. see the PCI Express Specification." hexmask.long.word 0x0 20.--31. 1. "NEXT_OFFSET,Next Capability Offset. For a description of this standard PCIe register field see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky).." newline hexmask.long.byte 0x0 16.--19. 1. "CAP_VERSION,Capability Version. For a description of this standard PCIe register field see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else.." newline hexmask.long.word 0x0 0.--15. 1. "EXTENDED_CAP_ID,PCI Express Extended Capability ID. For a description of this standard PCIe register field see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then.." rgroup.long (0x4+0x30C)++0x3 line.long 0x0 "VENDOR_SPECIFIC_HEADER_REG,Vendor-Specific Header. For a description of this standard PCIe register. see the PCI Express Specification." hexmask.long.word 0x0 20.--31. 1. "VSEC_LENGTH,VSEC Length. For a description of this standard PCIe register field see the PCI Express Specification." newline hexmask.long.byte 0x0 16.--19. 1. "VSEC_REV,VSEC Rev. For a description of this standard PCIe register field see the PCI Express Specification." newline hexmask.long.word 0x0 0.--15. 1. "VSEC_ID,VSEC ID. For a description of this standard PCIe register field see the PCI Express Specification." group.long (0x8+0x30C)++0x3 line.long 0x0 "EVENT_COUNTER_CONTROL_REG,Event Counter Control. This is a viewport control register. - Setting the EVENT_COUNTER_EVENT_SELECT and EVENT_COUNTER_LANE_SELECT fields in this register determine the Event Counter data returned by the EVENT_COUNTER_DATA_REG.." hexmask.long.byte 0x0 28.--31. 1. "RSVDP_28,Reserved for future use." newline hexmask.long.word 0x0 16.--27. 1. "EVENT_COUNTER_EVENT_SELECT,Event Counter Data Select. This field in conjunction with the EVENT_COUNTER_LANE_SELECT field indexes the Event Counter data returned by the EVENT_COUNTER_DATA_REG register. - 27-24: Group number(4-bit: 0..0x7) - 23-16: Event.." newline hexmask.long.byte 0x0 12.--15. 1. "RSVDP_12,Reserved for future use." newline hexmask.long.byte 0x0 8.--11. 1. "EVENT_COUNTER_LANE_SELECT,Event Counter Lane Select. This field in conjunction with EVENT_COUNTER_EVENT_SELECT indexes the Event Counter data returned by the EVENT_COUNTER_DATA_REG register. - 0x0: Lane0 - 0x1: Lane1 - 0x2: Lane2 - .. - 0xF: Lane15 Note:.." newline rbitfld.long 0x0 7. "EVENT_COUNTER_STATUS,Event Counter Status. This register returns the current value of the Event Counter selected by the following fields: - EVENT_COUNTER_EVENT_SELECT - EVENT_COUNTER_LANE_SELECT Note: This register field is sticky." "0,1" newline rbitfld.long 0x0 5.--6. "RSVDP_5,Reserved for future use." "0,1,2,3" newline bitfld.long 0x0 2.--4. "EVENT_COUNTER_ENABLE,Event Counter Enable. Enables/disables the Event Counter selected by the EVENT_COUNTER_EVENT_SELECT and EVENT_COUNTER_LANE_SELECT fields in this register. By default all event counters are disabled. You can enable/disable a specific.." "no change,per event off,?,?,?,?,?,?" newline bitfld.long 0x0 0.--1. "EVENT_COUNTER_CLEAR,Event Counter Clear. Clears the Event Counter selected by the EVENT_COUNTER_EVENT_SELECT and EVENT_COUNTER_LANE_SELECT fields in this register. You can clear the value of a specific Event Counter by writing the 'per clear' code and.." "no change,per clear,?,?" rgroup.long (0xC+0x30C)++0x3 line.long 0x0 "EVENT_COUNTER_DATA_REG,Event Counter Data. This viewport register returns the data selected by the following fields: - EVENT_COUNTER_EVENT_SELECT in EVENT_COUNTER_CONTROL_REG - EVENT_COUNTER_LANE_SELECT in EVENT_COUNTER_CONTROL_REG For more details. see.." hexmask.long 0x0 0.--31. 1. "EVENT_COUNTER_DATA,Event Counter Data. This register returns the data selected by the following fields: - EVENT_COUNTER_EVENT_SELECT in EVENT_COUNTER_CONTROL_REG - EVENT_COUNTER_LANE_SELECT in EVENT_COUNTER_CONTROL_REG Note: This register field is sticky." group.long (0x10+0x30C)++0x3 line.long 0x0 "TIME_BASED_ANALYSIS_CONTROL_REG,Time-based Analysis Control. Used for controlling the measurement of RX/TX data throughput and time spent in each low-power LTSSM state. For more details. see the RAS DES section in the Core Operations chapter of the.." hexmask.long.byte 0x0 24.--31. 1. "TIME_BASED_REPORT_SELECT,Time-based Report Select. Selects what type of data is measured for the selected duration (TIME_BASED_DURATION_SELECT) and returned in TIME_BASED_ANALYSIS_DATA. Each type of data is measured using one of three types of units: -.." newline hexmask.long.byte 0x0 16.--23. 1. "RSVDP_16,Reserved for future use." newline hexmask.long.byte 0x0 8.--15. 1. "TIME_BASED_DURATION_SELECT,Time-based Duration Select. Selects the duration of time-based analysis. When 'manual control' is selected and TIMER_START is set to '1' this analysis never stops until TIMER_STOP is set to '0'. - 0x0: Manual control - 0x1:.." newline hexmask.long.byte 0x0 1.--7. 1. "RSVDP_1,Reserved for future use." newline bitfld.long 0x0 0. "TIMER_START,Timer Start. - 1: Start/Restart - 0: Stop This bit will be cleared automatically when the measurement is finished. Note: The app_ras_des_tba_ctrl input also sets the contents of this field and controls the measurement start/stop. Note: This.." "Stop,Start/Restart" rgroup.long (0x14+0x30C)++0x7 line.long 0x0 "TIME_BASED_ANALYSIS_DATA_REG,Time-based Analysis Data. Contains the measurement results of RX/TX data throughput and time spent in each low-power LTSSM state. This viewport register returns the data selected by the TIME_BASED_REPORT_SELECT field in.." hexmask.long 0x0 0.--31. 1. "TIME_BASED_ANALYSIS_DATA,Time Based Analysis Data. This register returns the data selected by the TIME_BASED_REPORT_SELECT field in TIME_BASED_ANALYSIS_CONTROL_REG. The results are cleared when next measurement starts. Note: This register field is sticky." line.long 0x4 "TIME_BASED_ANALYSIS_DATA_63_32_REG,Upper 32 bits of Time-based Analysis Data. This viewport register returns the data selected by the TIME_BASED_REPORT_SELECT field in TIME_BASED_ANALYSIS_CONTROL_REG. For more details. see the RAS DES section in the Core.." hexmask.long 0x4 0.--31. 1. "TIME_BASED_ANALYSIS_DATA_63_32,Upper 32 bits of Time Based Analysis Data. Note: This register field is sticky." group.long (0x30+0x30C)++0x5F line.long 0x0 "EINJ_ENABLE_REG,Error Injection Enable. Each type of error insertion is enabled by the corresponding bit in this register. The specific injection controls for each type of error are defined in the following registers: - 0: CRC Error: EINJ0_CRC_REG - 1:.." hexmask.long 0x0 7.--31. 1. "RSVDP_7,Reserved for future use." newline bitfld.long 0x0 6. "ERROR_INJECTION6_ENABLE,Error Injection6 Enable (Specific TLP Error). Enables insertion of errors into the packets that you select. You can set this bit to '1' when you have disabled RAS datapath protection (DP) by setting CX_RASDP = CX_RASDP_RAM_PROT.." "0,1" newline bitfld.long 0x0 5. "ERROR_INJECTION5_ENABLE,Error Injection5 Enable (TLP Duplicate/Nullify Error). Enables insertion of duplicate/nullified TLPs. For more details see the EINJ5_SP_TLP_REG register. Note: This register field is sticky." "0,1" newline bitfld.long 0x0 4. "ERROR_INJECTION4_ENABLE,Error Injection4 Enable (FC Credit Update Error). Enables insertion of errors into UpdateFCs. For more details see the EINJ4_FC_REG register. Note: This register field is sticky." "0,1" newline bitfld.long 0x0 3. "ERROR_INJECTION3_ENABLE,Error Injection3 Enable (Symbol DataK Mask Error or Sync Header Error). Enables DataK masking of special symbols or the breaking of the sync header. For more details see the EINJ3_SYMBOL_REG register. Note: This register field is.." "0,1" newline bitfld.long 0x0 2. "ERROR_INJECTION2_ENABLE,Error Injection2 Enable (DLLP Error). Enables insertion of DLLP errors. For more details see the EINJ2_DLLP_REG register. Note: This register field is sticky." "0,1" newline bitfld.long 0x0 1. "ERROR_INJECTION1_ENABLE,Error Injection1 Enable (Sequence Number Error). Enables insertion of errors into sequence numbers. For more details see the EINJ1_SEQNUM_REG register. Note: This register field is sticky." "0,1" newline bitfld.long 0x0 0. "ERROR_INJECTION0_ENABLE,Error Injection0 Enable (CRC Error). Enables insertion of errors into various CRC. For more details see the EINJ0_CRC_REG register. Note: This register field is sticky." "0,1" line.long 0x4 "EINJ0_CRC_REG,Error Injection Control 0 (CRC Error). Controls the insertion of errors into the CRC. and parity of ordered sets for the selected type of the packets as follows: - LCRC. Bad TLP will be detected at the receiver side; receiver responds with.." hexmask.long.tbyte 0x4 12.--31. 1. "RSVDP_12,Reserved for future use." newline hexmask.long.byte 0x4 8.--11. 1. "EINJ0_CRC_TYPE,Error injection type. Selects the type of CRC error to be inserted. Tx Path - 0000b: New TLP's LCRC error injection - 0001b: 16bCRC error injection of ACK/NAK DLLP - 0010b: 16bCRC error injection of Update-FC DLLP - 0011b: New TLP's ECRC.." newline hexmask.long.byte 0x4 0.--7. 1. "EINJ0_COUNT,Error injection count. Indicates the number of errors. This register is decremented when the errors have been inserted. - If the counter value is 0x01 and error is inserted ERROR_INJECTION0_ENABLE in EINJ_ENABLE_REG returns 0b. - If the.." line.long 0x8 "EINJ1_SEQNUM_REG,Error Injection Control 1 (Sequence Number Error). Controls the sequence number of the specific TLPs and ACK/NAK DLLPs. Data Link Protocol Error will be detected at the Rx side of ACK/NAL DLLPs when one of these conditions is true: -.." rbitfld.long 0x8 29.--31. "RSVDP_29,Reserved for future use." "0,1,2,3,4,5,6,7" newline hexmask.long.word 0x8 16.--28. 1. "EINJ1_BAD_SEQNUM,Bad sequence number. Indicates the value to add/subtract from the naturally-assigned sequence numbers. This value is represented by two's complement. - 0x0FFF: +4095 - .. - 0x0002: +2 - 0x0001: +1 - 0x0000: 0 - 0x1FFF: -1 - 0x1FFE: -2 -.." newline hexmask.long.byte 0x8 9.--15. 1. "RSVDP_9,Reserved for future use." newline bitfld.long 0x8 8. "EINJ1_SEQNUM_TYPE,Sequence number type. Selects the type of sequence number. - 0b: Insertion of New TLP's SEQ# error - 1b: Insertion of ACK/NAK DLLP's SEQ# Error Note: This register field is sticky." "0,1" newline hexmask.long.byte 0x8 0.--7. 1. "EINJ1_COUNT,Error injection count. Indicates the number of errors. This register is decremented as the errors are being inserted. - If the counter value is 0x01 and error is inserted ERROR_INJECTION1_ENABLE in EINJ_ENABLE_REG returns '0'. - If the.." line.long 0xC "EINJ2_DLLP_REG,Error Injection Control 2 (DLLP Error). Controls the transmission of DLLPs and inserts the following errors: - If 'ACK/NAK DLLP's transmission block' is selected. replay timeout error will occur at the transmitter of the TLPs and then Data.." hexmask.long.tbyte 0xC 10.--31. 1. "RSVDP_10,Reserved for future use." newline bitfld.long 0xC 8.--9. "EINJ2_DLLP_TYPE,DLLP Type. Selects the type of DLLP errors to be inserted. - 00b: ACK/NAK DLLP's transmission block - 01b: Update FC DLLP's transmission block - 10b: Always Transmission for NAK DLLP - 11b: Reserved Note: This register field is sticky." "0,1,2,3" newline hexmask.long.byte 0xC 0.--7. 1. "EINJ2_COUNT,Error injection count. Indicates the number of errors. This register is decremented as the errors are being inserted. - If the counter value is 0x01 and the error is inserted ERROR_INJECTION2_ENABLE in EINJ_ENABLE_REG returns '0'. - If the.." line.long 0x10 "EINJ3_SYMBOL_REG,Error Injection Control 3 (Symbol Error). When 8b/10b encoding is used. this register controls error insertion into the special (K code) symbols. - If TS1/TS2/FTS/E-Idle/SKP is selected. it affects whole of the ordered set. It might.." hexmask.long.tbyte 0x10 11.--31. 1. "RSVDP_11,Reserved for future use." newline bitfld.long 0x10 8.--10. "EINJ3_SYMBOL_TYPE,Error Type. 8b/10b encoding - Mask K symbol. It is not supported to insert errors into the first ordered-set after exiting from TxElecIdle when CX_FREQ_STEP_EN has been enabled. - 000b: Reserved - 001b: COM/PAD(TS1 Order set) - 010b:.." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x10 0.--7. 1. "EINJ3_COUNT,Error injection count. Indicates the number of errors. This register is decremented as the errors are being inserted. - If the counter value is 0x01 and error is inserted ERROR_INJECTION3_ENABLE in EINJ_ENABLE_REG returns '0'. - If the.." line.long 0x14 "EINJ4_FC_REG,Error Injection Control 4 (FC Credit Error). Controls error insertion into the credit value in the UpdateFCs. It is possible to insert errors for any of the following types: - Posted TLP Header credit - Non-Posted TLP Header credit -.." rbitfld.long 0x14 29.--31. "RSVDP_29,Reserved for future use." "0,1,2,3,4,5,6,7" newline hexmask.long.word 0x14 16.--28. 1. "EINJ4_BAD_UPDFC_VALUE,Bad update-FC credit value. Indicates the value to add/subtract from the UpdateFC credit. This value is represented by two's complement. - 0x0FFF: +4095 - .. - 0x0002: +2 - 0x0001: +1 - 0x0000: 0 - 0x1FFF: -1 - 0x1FFE: -2 - .. -.." newline rbitfld.long 0x14 15. "RSVDP_15,Reserved for future use." "0,1" newline bitfld.long 0x14 12.--14. "EINJ4_VC_NUMBER,VC Number. Indicates target VC Number. Note: This register field is sticky." "0,1,2,3,4,5,6,7" newline rbitfld.long 0x14 11. "RSVDP_11,Reserved for future use." "0,1" newline bitfld.long 0x14 8.--10. "EINJ4_UPDFC_TYPE,Update-FC type. Selects the credit type. - 000b: Posted TLP Header Credit value control - 001b: Non-Posted TLP Header Credit value control - 010b: Completion TLP Header Credit value control - 011b: Reserved - 100b: Posted TLP Data Credit.." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x14 0.--7. 1. "EINJ4_COUNT,Error injection count. Indicates the number of errors. This register is decremented as the errors are being inserted. - If the counter value is 0x01 and error is inserted ERROR_INJECTION4_ENABLE in EINJ_ENABLE_REG returns '0'. - If the.." line.long 0x18 "EINJ5_SP_TLP_REG,Error Injection Control 5 (Specific TLP Error). Controls the generation of specified TLPs. Correctable errors will occur which will be fixed by the PCIe protocol. - For Duplicate TLP. the controller initiates Data Link Retry by handling.." hexmask.long.tbyte 0x18 9.--31. 1. "RSVDP_9,Reserved for future use." newline bitfld.long 0x18 8. "EINJ5_SPECIFIED_TLP,Specified TLP. Selects the specified TLP to be inserted. - 0: Generates duplicate TLPs by handling ACK DLLP as NAK DLLP. - 1: Generates Nullified TLP (Original TLP will be stored in retry buffer). Note: This register field is sticky." "Generates duplicate TLPs by handling ACK DLLP as..,Generates Nullified TLP" newline hexmask.long.byte 0x18 0.--7. 1. "EINJ5_COUNT,Error injection count. Indicates the number of errors. This register is decremented as the errors are being inserted. - If the counter value is 0x01 and error is inserted ERROR_INJECTION5_ENABLE in EINJ_ENABLE_REG returns '0'. - If the.." line.long 0x1C "EINJ6_COMPARE_POINT_H0_REG,Error Injection Control 6 (Compare Point Header DWORD #0). Program this register for the 1st DWORD of TLP header/prefix. It is necessary to carefully consider the endianness when you program this register. Bits [31:0] =.." hexmask.long 0x1C 0.--31. 1. "EINJ6_COMPARE_POINT_H0,Packet Compare Point: 1st DWORD. Specifies which Tx TLP header DWORD#0 bits to compare with the corresponding bits in the Packet Compare Value registers (EINJ6_COMPARE_VALUE*). When all specified bits (in the Tx TLP header and.." line.long 0x20 "EINJ6_COMPARE_POINT_H1_REG,Error Injection Control 6 (Compare Point Header DWORD #1). Program this register for the 2nd DWORD of TLP header/prefix. It is necessary to carefully consider the endianness when you program this register. Bits [31:0] =.." hexmask.long 0x20 0.--31. 1. "EINJ6_COMPARE_POINT_H1,Packet Compare Point: 2nd DWORD. Specifies which Tx TLP header DWORD#1 bits to compare with the corresponding bits in the Packet Compare Value registers (EINJ6_COMPARE_VALUE*). When all specified bits (in the Tx TLP header and.." line.long 0x24 "EINJ6_COMPARE_POINT_H2_REG,Error Injection Control 6 (Compare Point Header DWORD #2). Program this register for the 3rd DWORD of TLP header/prefix. It is necessary to carefully consider the endianness when you program this register. Bits [31:0] =.." hexmask.long 0x24 0.--31. 1. "EINJ6_COMPARE_POINT_H2,Packet Compare Point: 3rd DWORD. Specifies which Tx TLP header DWORD#2 bits to compare with the corresponding bits in the Packet Compare Value registers (EINJ6_COMPARE_VALUE*). When all specified bits (in the Tx TLP header and.." line.long 0x28 "EINJ6_COMPARE_POINT_H3_REG,Error Injection Control 6 (Compare Point Header DWORD #3). Program this register for the 4th DWORD of TLP header/prefix. It is necessary to carefully consider the endianness when you program this register. Bits [31:0] =.." hexmask.long 0x28 0.--31. 1. "EINJ6_COMPARE_POINT_H3,Packet Compare Point: 4th DWORD. Specifies which Tx TLP header DWORD#3 bits to compare with the corresponding bits in the Packet Compare Value registers (EINJ6_COMPARE_VALUE*). When all specified bits (in the Tx TLP header and.." line.long 0x2C "EINJ6_COMPARE_VALUE_H0_REG,Error Injection Control 6 (Compare Value Header DWORD #0). Program this register for the 1st DWORD of TLP header/prefix. It is necessary to carefully consider the endianness when you program this register. Bits [31:0] =.." hexmask.long 0x2C 0.--31. 1. "EINJ6_COMPARE_VALUE_H0,Packet Compare Value: 1st DWORD. Specifies the value to compare against Tx the TLP header DWORD#0 bits specified in the Packet Compare Point registers (EINJ6_COMPARE_POINT*). Note: This register field is sticky." line.long 0x30 "EINJ6_COMPARE_VALUE_H1_REG,Error Injection Control 6 (Compare Value Header DWORD #1). Program this register for the 2nd DWORD of TLP header/prefix. It is necessary to carefully consider the endianness when you program this register. Bits [31:0] =.." hexmask.long 0x30 0.--31. 1. "EINJ6_COMPARE_VALUE_H1,Packet Compare Value: 2nd DWORD. Specifies the value to compare against Tx the TLP header DWORD#1 bits specified in the Packet Compare Point registers (EINJ6_COMPARE_POINT*). Note: This register field is sticky." line.long 0x34 "EINJ6_COMPARE_VALUE_H2_REG,Error Injection Control 6 (Compare Value Header DWORD #2). Program this register for the 3rd DWORD of TLP header/prefix. It is necessary to carefully consider the endianness when you program this register. Bits [31:0] =.." hexmask.long 0x34 0.--31. 1. "EINJ6_COMPARE_VALUE_H2,Packet Compare Value: 3rd DWORD. Specifies the value to compare against Tx the TLP header DWORD#2 bits specified in the Packet Compare Point registers (EINJ6_COMPARE_POINT*). Note: This register field is sticky." line.long 0x38 "EINJ6_COMPARE_VALUE_H3_REG,Error Injection Control 6 (Compare Value Header DWORD #3). Program this register for the 4th DWORD of TLP header/prefix. It is necessary to carefully consider the endianness when you program this register. Bits [31:0] =.." hexmask.long 0x38 0.--31. 1. "EINJ6_COMPARE_VALUE_H3,Packet Compare Value: 4th DWORD. Specifies the value to compare against Tx the TLP header DWORD#3 bits specified in the Packet Compare Point registers (EINJ6_COMPARE_POINT*). Note: This register field is sticky." line.long 0x3C "EINJ6_CHANGE_POINT_H0_REG,Error Injection Control 6 (Change Point Header DWORD #0). Program this register for the 1st DWORD of TLP header/prefix. It is necessary to carefully consider the endianness when you program this register. Bits [31:0] =.." hexmask.long 0x3C 0.--31. 1. "EINJ6_CHANGE_POINT_H0,Packet Change Point: 1st DWORD. Specifies which Tx TLP header DWORD#0 bits to replace with the corresponding bits in the Packet Change Value registers (EINJ6_CHANGE_VALUE*). Note: This register field is sticky." line.long 0x40 "EINJ6_CHANGE_POINT_H1_REG,Error Injection Control 6 (Change Point Header DWORD #1). Program this register for the 2nd DWORD of TLP header/prefix. It is necessary to carefully consider the endianness when you program this register. Bits [31:0] =.." hexmask.long 0x40 0.--31. 1. "EINJ6_CHANGE_POINT_H1,Packet Change Point: 2nd DWORD. Specifies which Tx TLP header DWORD#1 bits to replace with the corresponding bits in the Packet Change Value registers (EINJ6_CHANGE_VALUE*). Note: This register field is sticky." line.long 0x44 "EINJ6_CHANGE_POINT_H2_REG,Error Injection Control 6 (Change Point Header DWORD #2). Program this register for the 3rd DWORD of TLP header/prefix. It is necessary to carefully consider the endianness when you program this register. Bits [31:0] =.." hexmask.long 0x44 0.--31. 1. "EINJ6_CHANGE_POINT_H2,Packet Change Point: 3rd DWORD. Specifies which Tx TLP header DWORD#2 bits to replace with the corresponding bits in the Packet Change Value registers (EINJ6_CHANGE_VALUE*). Note: This register field is sticky." line.long 0x48 "EINJ6_CHANGE_POINT_H3_REG,Error Injection Control 6 (Change Point Header DWORD #3). Program this register for the 4th DWORD of TLP header/prefix. It is necessary to carefully consider the endianness when you program this register. Bits [31:0] =.." hexmask.long 0x48 0.--31. 1. "EINJ6_CHANGE_POINT_H3,Packet Change Point: 4th DWORD. Specifies which Tx TLP header DWORD#3 bits to replace with the corresponding bits in the Packet Change Value registers (EINJ6_CHANGE_VALUE*). Note: This register field is sticky." line.long 0x4C "EINJ6_CHANGE_VALUE_H0_REG,Error Injection Control 6 (Change Value Header DWORD #0). Program this register for the 1st DWORD of TLP header/prefix. It is necessary to carefully consider the endianness when you program this register. Bits [31:0] =.." hexmask.long 0x4C 0.--31. 1. "EINJ6_CHANGE_VALUE_H0,Packet Change Value: 1st DWORD. Specifies replacement values for the Tx TLP header DWORD#0 bits defined in the Packet Change Point registers (EINJ6_CHANGE_POINT*). Only applies when the EINJ6_INVERTED_CONTROL field in EINJ6_TLP_REG.." line.long 0x50 "EINJ6_CHANGE_VALUE_H1_REG,Error Injection Control 6 (Change Value Header DWORD #1). Program this register for the 2nd DWORD of TLP header/prefix. It is necessary to carefully consider the endianness when you program this register. Bits [31:0] =.." hexmask.long 0x50 0.--31. 1. "EINJ6_CHANGE_VALUE_H1,Packet Change Value: 2nd DWORD. Specifies replacement values for the Tx TLP header DWORD#1 bits defined in the Packet Change Point registers (EINJ6_CHANGE_POINT*). Only applies when the EINJ6_INVERTED_CONTROL field in EINJ6_TLP_REG.." line.long 0x54 "EINJ6_CHANGE_VALUE_H2_REG,Error Injection Control 6 (Change Value Header DWORD #2). Program this register for the 3rd DWORD of TLP header/prefix. It is necessary to carefully consider the endianness when you program this register. Bits [31:0] =.." hexmask.long 0x54 0.--31. 1. "EINJ6_CHANGE_VALUE_H2,Packet Change Value: 3rd DWORD. Specifies replacement values for the Tx TLP header DWORD#2 bits defined in the Packet Change Point registers (EINJ6_CHANGE_POINT*). Only applies when the EINJ6_INVERTED_CONTROL field in EINJ6_TLP_REG.." line.long 0x58 "EINJ6_CHANGE_VALUE_H3_REG,Error Injection Control 6 (Change Value Header DWORD #3). Program this register for the 4th DWORD of TLP header/prefix. It is necessary to carefully consider the endianness when you program this register. Bits [31:0] =.." hexmask.long 0x58 0.--31. 1. "EINJ6_CHANGE_VALUE_H3,Packet Change Value: 4th DWORD. Specifies replacement values for the Tx TLP header DWORD#3 bits defined in the Packet Change Point registers (EINJ6_CHANGE_POINT*). Only applies when the EINJ6_INVERTED_CONTROL field in EINJ6_TLP_REG.." line.long 0x5C "EINJ6_TLP_REG,Error Injection Control 6 (Packet Error). The Packet Compare Point registers (EINJ6_COMPARE_POINT*) specify which Tx TLP header bits to compare with the corresponding bits in the Packet Compare Value registers (EINJ6_COMPARE_VALUE*). When.." hexmask.long.tbyte 0x5C 12.--31. 1. "RSVDP_12,Reserved for future use." newline bitfld.long 0x5C 9.--11. "EINJ6_PACKET_TYPE,Packet type. Selects the TLP packets to inject errors into. - 0: TLP Header - 1: TLP Prefix 1st 4-DWORDs - 2: TLP Prefix 2nd -DWORDs - Else: Reserved Note: This register field is sticky." "TLP Header,TLP Prefix 1st 4-DWORDs,TLP Prefix 2nd -DWORDs,?,?,?,?,?" newline bitfld.long 0x5C 8. "EINJ6_INVERTED_CONTROL,Inverted Error Injection Control. - 0: EINJ6_CHANGE_VALUE_H[0/1/2/3] is used to replace bits specified by EINJ6_CHANGE_POINT_H[0/1/2/3]. - 1: EINJ6_CHANGE_VALUE_H[0/1/2/3] is ignored and inverts bits specified by.." "EINJ6_CHANGE_VALUE_H[0/1/2/3] is used to replace..,EINJ6_CHANGE_VALUE_H[0/1/2/3] is ignored and.." newline hexmask.long.byte 0x5C 0.--7. 1. "EINJ6_COUNT,Error Injection Count. Indicates the number of errors to insert. This counter is decremented while errors are been inserted. - If the counter value is 0x01 and error is inserted ERROR_INJECTION6_ENABLE in EINJ_ENABLE_REG returns '0'. - If.." group.long (0xA0+0x30C)++0x7 line.long 0x0 "SD_CONTROL1_REG,Silicon Debug Control 1. For more details. see the RAS DES section in the Core Operations chapter of the Databook." hexmask.long.byte 0x0 24.--31. 1. "RSVDP_24,Reserved for future use." newline bitfld.long 0x0 22.--23. "LOW_POWER_INTERVAL,Low Power Entry Interval Time. Interval Time that the controller starts monitoring RXELECIDLE signal after L0s/L1/L2 entry. You should set the value according to the latency from receiving EIOS to RXELECIDLE assertion at the PHY. -.." "0,1,2,3" newline bitfld.long 0x0 20.--21. "TX_EIOS_NUM,Number of Tx EIOS. This register sets the number of transmit EIOS for L0s/L1 entry and Disable/Loopback/Hot-reset exit. The controller selects the greater value between this register and the value defined by the PCI-SIG specification. 2.5GT/s.." "0,1,2,3" newline rbitfld.long 0x0 17.--19. "RSVDP_17,Reserved for future use." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 16. "FORCE_DETECT_LANE_EN,Force Detect Lane Enable. When this bit is set the controller ignores receiver detection from PHY during LTSSM Detect state and uses FORCE_DETECT_LANE. Note: This register field is sticky." "0,1" newline hexmask.long.word 0x0 0.--15. 1. "FORCE_DETECT_LANE,Force Detect Lane. When the FORCE_DETECT_LANE_EN field is set the controller ignores receiver detection from PHY during LTSSM Detect state and uses this value instead. - 0: Lane0 - 1: Lane1 - 2: Lane2 - .. - 15: Lane15 Note: This.." line.long 0x4 "SD_CONTROL2_REG,Silicon Debug Control 2. For more details. see the RAS DES section in the Core Operations chapter of the Databook." hexmask.long.word 0x4 17.--31. 1. "RSVDP_17,Reserved for future use." newline bitfld.long 0x4 16. "FRAMING_ERR_RECOVERY_DISABLE,Framing Error Recovery Disable. This bit disables a transition to Recovery state when a Framing Error is occurred. Note: This register field is sticky." "0,1" newline hexmask.long.byte 0x4 11.--15. 1. "RSVDP_11,Reserved for future use." newline bitfld.long 0x4 10. "DIRECT_LPBKSLV_TO_EXIT,Direct Loopback Slave To Exit. When this bit is set and the LTSSM is in Loopback Slave Active State the LTSSM transitions to Loopback Slave Exit state. Note: This register field is sticky." "0,1" newline bitfld.long 0x4 9. "DIRECT_POLCOMP_TO_DETECT,Direct Polling.Compliance to Detect. When this bit is set and the LTSSM is in Polling Compliance State the LTSSM transitions to Detect state. Note: This register field is sticky." "0,1" newline bitfld.long 0x4 8. "DIRECT_RECIDLE_TO_CONFIG,Direct Recovery.Idle to Configuration. When this bit is set and the LTSSM is in Recovery Idle State the LTSSM transitions to Configuration state. Note: This register field is sticky." "0,1" newline hexmask.long.byte 0x4 3.--7. 1. "RSVDP_3,Reserved for future use." newline bitfld.long 0x4 2. "NOACK_FORCE_LINKDOWN,Force LinkDown. When this bit is set and the controller detects REPLY_NUM rolling over 4 times the LTSSM transitions to Detect State. Note: This register field is sticky." "0,1" newline bitfld.long 0x4 1. "RECOVERY_REQUEST,Recovery Request. When this bit is set to '1' in L0 or L0s the LTSSM starts transitioning to Recovery State. This request does not cause a speed change or re-equalization." "0,1" newline bitfld.long 0x4 0. "HOLD_LTSSM,Hold and Release LTSSM. For as long as this register is '1' the controller stays in the current LTSSM. Note: This register field is sticky." "0,1" group.long (0xB0+0x30C)++0xB line.long 0x0 "SD_STATUS_L1LANE_REG,Silicon Debug Status(Layer1 Per-lane). This viewport register returns the data selected by the following field: - LANE_SELECT in SD_STATUS_L1LANE_REG For more details. see the RAS DES section in the Core Operations chapter of the.." hexmask.long.byte 0x0 24.--31. 1. "DESKEW_POINTER,Deskew Pointer. Indicates Deskew pointer of internal Deskew buffer of selected lane number(LANE_SELECT). Note: This register field is sticky." newline rbitfld.long 0x0 21.--23. "RSVDP_21,Reserved for future use." "0,1,2,3,4,5,6,7" newline rbitfld.long 0x0 20. "PIPE_TXELECIDLE,PIPE:TxElecIdle. Indicates PIPE TXELECIDLE signal of selected lane number(LANE_SELECT). Note: This register field is sticky." "0,1" newline rbitfld.long 0x0 19. "PIPE_RXELECIDLE,PIPE:RxElecIdle. Indicates PIPE RXELECIDLE signal of selected lane number(LANE_SELECT). Note: This register field is sticky." "0,1" newline rbitfld.long 0x0 18. "PIPE_RXVALID,PIPE:RxValid. Indicates PIPE RXVALID signal of selected lane number(LANE_SELECT). Note: This register field is sticky." "0,1" newline rbitfld.long 0x0 17. "PIPE_DETECT_LANE,PIPE:Detect Lane. Indicates whether PHY indicates receiver detection or not on selected lane number(LANE_SELECT). Note: This register field is sticky." "0,1" newline rbitfld.long 0x0 16. "PIPE_RXPOLARITY,PIPE:RxPolarity. Indicates PIPE RXPOLARITY signal of selected lane number(LANE_SELECT). Note: This register field is sticky." "0,1" newline hexmask.long.word 0x0 4.--15. 1. "RSVDP_4,Reserved for future use." newline hexmask.long.byte 0x0 0.--3. 1. "LANE_SELECT,Lane Select. Lane Select register for Silicon Debug Status Register of Layer1-PerLane. - 0x0: Lane0 - 0x1: Lane1 - 0x2: Lane2 - .. - 0xF: Lane15 Note: This register field is sticky." line.long 0x4 "SD_STATUS_L1LTSSM_REG,Silicon Debug Status(Layer1 LTSSM). For more details. see the RAS DES section in the Core Operations chapter of the Databook." hexmask.long.word 0x4 16.--31. 1. "LTSSM_VARIABLE,LTSSM Variable. Indicates internal LTSSM variables defined in the PCI Express Base Specification. C-PCIe Mode: - 0: directed_speed_change - 1: changed_speed_recovery - 2: successful_speed_negotiation - 3: upconfigure_capable; Set to '1' if.." newline rbitfld.long 0x4 15. "LANE_REVERSAL,Lane Reversal Operation. Receiver detected lane reversal. This field is only valid in the L0 LTSSM state. Note: This register field is sticky." "0,1" newline hexmask.long.byte 0x4 11.--14. 1. "RSVDP_11,Reserved for future use." newline rbitfld.long 0x4 8.--10. "PIPE_POWER_DOWN,PIPE:PowerDown. Indicates PIPE PowerDown signal. Note: This register field is sticky." "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 7. "FRAMING_ERR,Framing Error. Indicates Framing Error detection status." "0,1" newline hexmask.long.byte 0x4 0.--6. 1. "FRAMING_ERR_PTR,First Framing Error Pointer. Identifies the first Framing Error using the following encoding. The field contents are only valid value when FRAMING_ERR =1. Received Unexpected Framing Token - 01h: When non- STP/SDP/IDL Token was received.." line.long 0x8 "SD_STATUS_PM_REG,Silicon Debug Status(PM). For more details. see the RAS DES section in the Core Operations chapter of the Databook." hexmask.long.byte 0x8 24.--31. 1. "RSVDP_24,Reserved for future use." newline hexmask.long.byte 0x8 16.--23. 1. "LATCHED_NFTS,Latched N_FTS. Indicates the value of N_FTS in the received TS Ordered Sets from the Link Partner Note: This register field is sticky." newline rbitfld.long 0x8 13.--15. "L1SUB_STATE,L1Sub State. Indicates internal state machine of L1Sub state. - 0h: S_L1_U : idle state - 1h: S_L1_0 : wait for aux_clk_active - 2h: S_L1_0_WAIT4_ACK : wait for pclkack - 3h: S_L1_0_WAIT4_CLKREQ : wait for clkreq - 4h: S_L1_N_ENTRY : check.." "wait for aux_clk_active,?,?,?,?,?,?,?" newline bitfld.long 0x8 12. "PME_RESEND_FLAG,PME Re-send flag. When the DUT sends a PM_PME message TLP the DUT sets PME_Status bit. If host software does not clear PME_Status bit for 100ms(+50%/-5%) the DUT resends the PM_PME Message. This bit indicates that a PM_PME was resent." "0,1" newline hexmask.long.byte 0x8 8.--11. 1. "INTERNAL_PM_SSTATE,Internal PM State(Slave). Indicates internal state machine of Power Management Slave controller. - 0h: S_IDLE - 1h: S_RESPOND_NAK - 2h: S_BLOCK_TLP - 3h: S_WAIT_LAST_TLP_ACK - 4h: S_WAIT_EIDLE - 5h: S_LINK_ENTR_L1 - 6h: S_L1 - 7h:.." newline rbitfld.long 0x8 5.--7. "RSVDP_5,Reserved for future use." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x8 0.--4. 1. "INTERNAL_PM_MSTATE,Internal PM State(Master). Indicates internal state machine of Power Management Master controller. - 00h: IDLE - 01h: L0 - 02h: L0S - 03h: ENTER_L0S - 04h: L0S_EXIT - 05h: WAIT_PMCSR_CPL_SENT - 08h: L1 - 09h: L1_BLOCK_TLP - 0Ah:.." rgroup.long (0xBC+0x30C)++0x3 line.long 0x0 "SD_STATUS_L2_REG,Silicon Debug Status(Layer2). For more details. see the RAS DES section in the Core Operations chapter of the Databook." hexmask.long.byte 0x0 28.--31. 1. "RSVDP_28,Reserved for future use." newline bitfld.long 0x0 27. "FC_INIT2,FC_INIT2. Indicates the controller is in FC_INIT2(VC0) state. Note: This register field is sticky." "0,1" newline bitfld.long 0x0 26. "FC_INIT1,FC_INIT1. Indicates the controller is in FC_INIT1(VC0) state. Note: This register field is sticky." "0,1" newline bitfld.long 0x0 24.--25. "DLCMSM,DLCMSM. Indicates the current DLCMSM. - 00b: DL_INACTIVE - 01b: DL_FC_INIT - 11b: DL_ACTIVE Note: This register field is sticky." "0,1,2,3" newline hexmask.long.word 0x0 12.--23. 1. "RX_ACK_SEQ_NO,Tx Ack Sequence Number. Indicates ACKD_SEQ which is updated by receiving ACK/NAK DLLP. Note: This register field is sticky." newline hexmask.long.word 0x0 0.--11. 1. "TX_TLP_SEQ_NO,Tx Tlp Sequence Number. Indicates next transmit sequence number for transmit TLP. Note: This register field is sticky." group.long (0xC0+0x30C)++0x7 line.long 0x0 "SD_STATUS_L3FC_REG,Silicon Debug Status(Layer3 FC). The CREDIT_DATA[0/1] fields in this viewport register return the data for the VC and TLP Type selected by the following fields: - CREDIT_SEL_VC - CREDIT_SEL_CREDIT_TYPE - CREDIT_SEL_TLP_TYPE -.." hexmask.long.word 0x0 20.--31. 1. "CREDIT_DATA1,Credit Data1. Current FC credit data selected by the CREDIT_SEL_VC CREDIT_SEL_CREDIT_TYPE CREDIT_SEL_TLP_TYPE and CREDIT_SEL_HD viewport-select fields. - Rx: Credit Allocated Value - Tx: Credit Limit Value. This value is valid when.." newline hexmask.long.word 0x0 8.--19. 1. "CREDIT_DATA0,Credit Data0. Current FC credit data selected by the CREDIT_SEL_VC CREDIT_SEL_CREDIT_TYPE CREDIT_SEL_TLP_TYPE and CREDIT_SEL_HD viewport-select fields. - Rx: Credit Received Value - Tx: Credit Consumed Value Note: This register field is.." newline rbitfld.long 0x0 7. "RSVDP_7,Reserved for future use." "0,1" newline bitfld.long 0x0 6. "CREDIT_SEL_HD,Credit Select(HeaderData). This field in conjunction with the CREDIT_SEL_VC CREDIT_SEL_CREDIT_TYPE and CREDIT_SEL_TLP_TYPE viewport-select fields determines that data that is returned by the CREDIT_DATA0 and CREDIT_DATA1 data fields. -.." "Header Credit,Data Credit" newline bitfld.long 0x0 4.--5. "CREDIT_SEL_TLP_TYPE,Credit Select(TLP Type). This field in conjunction with the CREDIT_SEL_VC CREDIT_SEL_CREDIT_TYPE and CREDIT_SEL_HD viewport-select fields determines that data that is returned by the CREDIT_DATA0 and CREDIT_DATA1 data fields. - 0x0:.." "Posted,Non-Posted,Completion,?" newline bitfld.long 0x0 3. "CREDIT_SEL_CREDIT_TYPE,Credit Select(Credit Type). This field in conjunction with the CREDIT_SEL_VC CREDIT_SEL_TLP_TYPE and CREDIT_SEL_HD viewport-select fields determines that data that is returned by the CREDIT_DATA0 and CREDIT_DATA1 data fields. -.." "Rx,Tx" newline bitfld.long 0x0 0.--2. "CREDIT_SEL_VC,Credit Select(VC). This field in conjunction with the CREDIT_SEL_CREDIT_TYPE CREDIT_SEL_TLP_TYPE and CREDIT_SEL_HD viewport-select fields determines that data that is returned by the CREDIT_DATA0 and CREDIT_DATA1 data fields. - 0x0: VC0 -.." "VC0,VC1,VC2,?,?,?,?,VC7" line.long 0x4 "SD_STATUS_L3_REG,Silicon Debug Status(Layer3). For more details. see the RAS DES section in the Core Operations chapter of the Databook." hexmask.long.tbyte 0x4 8.--31. 1. "RSVDP_8,Reserved for future use." newline bitfld.long 0x4 7. "MFTLP_STATUS,Malformed TLP Status. Indicates malformed TLP has occurred." "0,1" newline hexmask.long.byte 0x4 0.--6. 1. "MFTLP_POINTER,First Malformed TLP Error Pointer. Indicates the element of the received first malformed TLP. This pointer is validated by MFTLP_STATUS. - 01h: AtomicOp address alignment - 02h: AtomicOp operand - 03h: AtomicOp byte enable - 04h: TLP length.." group.long (0xD0+0x30C)++0xB line.long 0x0 "SD_EQ_CONTROL1_REG,Silicon Debug EQ Control 1. This is a viewport control register. Setting the EQ_RATE_SEL and EQ_LANE_SEL fields in this register determine the per-lane Silicon Debug EQ Status data returned by the SD_EQ_STATUS[1/2/3] viewport.." hexmask.long.byte 0x0 24.--31. 1. "FOM_TARGET,FOM Target. Indicates figure of merit target criteria value of EQ Master(DSP in EQ Phase3/USP in EQ Phase2). This field is only valid when GEN3_EQ_FB_MODE is 0001b(Figure Of Merit). Note: This register field is sticky." newline bitfld.long 0x0 23. "FOM_TARGET_ENABLE,FOM Target Enable. Enables the FOM_TARGET fields. Note: This register field is sticky." "0,1" newline hexmask.long.byte 0x0 18.--22. 1. "RSVDP_18,Reserved for future use." newline bitfld.long 0x0 16.--17. "EVAL_INTERVAL_TIME,Eval Interval Time. Indicates interval time of RxEqEval assertion. - 00: 500ns - 01: 1us - 10: 2us - 11: 4us This field is used for EQ Master(DSP in EQ Phase3/USP in EQ Phase2). Note: This register field is sticky." "0,1,2,3" newline hexmask.long.byte 0x0 10.--15. 1. "RSVDP_10,Reserved for future use." newline bitfld.long 0x0 8.--9. "EXT_EQ_TIMEOUT,Extends EQ Phase2/3 Timeout. This field is used when the Ltssm is in Recovery.EQ2/3. When this field is set the value of EQ2/3 timeout is extended. EQ Master(DSP in EQ Phase3/USP in EQ Phase2). - 00: 24ms (default) - 01: 48ms (x2) - 10:.." "0,1,2,3" newline rbitfld.long 0x0 6.--7. "RSVDP_6,Reserved for future use." "0,1,2,3" newline bitfld.long 0x0 4.--5. "EQ_RATE_SEL,EQ Status Rate Select. Setting this field in conjunction with the EQ_LANE_SEL field determines the per-lane Silicon Debug EQ Status data returned by the SD_EQ_CONTROL[2/3] and SD_EQ_STATUS[1/2/3] viewport registers. - 0x0: 8.0GT/s Speed.." "0,1,2,3" newline hexmask.long.byte 0x0 0.--3. 1. "EQ_LANE_SEL,EQ Status Lane Select. Setting this field in conjunction with the EQ_RATE_SEL field determines the per-lane Silicon Debug EQ Status data returned by the SD_EQ_CONTROL[2/3] and SD_EQ_STATUS[1/2/3] viewport registers. - 0x0: Lane0 - 0x1: Lane1.." line.long 0x4 "SD_EQ_CONTROL2_REG,Silicon Debug EQ Control 2. This viewport register returns the value for the rate and lane selected by the EQ_RATE_SEL and EQ_LANE_SEL fields in the SD_EQ_CONTROL1_REG register. For more details. see the RAS DES section in the Core.." rbitfld.long 0x4 31. "RSVDP_31,Reserved for future use." "0,1" newline bitfld.long 0x4 30. "FORCE_LOCAL_TX_PRESET_ENABLE,Force Local Transmitter Preset Enable. Enables the FORCE_LOCAL_TX_PRESET field. If select rate in the EQ_RATE_SEL field is 32.0GT/s Speed this feature is not available. Note: This register field is sticky." "0,1" newline bitfld.long 0x4 29. "FORCE_LOCAL_RX_HINT_ENABLE,Force Local Receiver Preset Hint Enable. Enables the FORCE_LOCAL_RX_HINT field. If select rate in the EQ_RATE_SEL field is other than 8.0GT/s Speed this feature is not available. Note: This register field is sticky." "0,1" newline bitfld.long 0x4 28. "FORCE_LOCAL_TX_COEF_ENABLE,Force Local Transmitter Coefficient Enable. Enables the following fields: - FORCE_LOCAL_TX_PRE_CURSOR - FORCE_LOCAL_TX_CURSOR - FORCE_LOCAL_TX_POST_CURSOR Note: This register field is sticky." "0,1" newline hexmask.long.byte 0x4 24.--27. 1. "FORCE_LOCAL_TX_PRESET,Force Local Transmitter Preset. Indicates initial preset value of USP in EQ Slave(EQ Phase2) instead of receiving EQ TS2. If select rate in the EQ_RATE_SEL field is 32.0GT/s Speed this feature is not available. Note: This register.." newline rbitfld.long 0x4 21.--23. "RSVDP_21,Reserved for future use." "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 18.--20. "FORCE_LOCAL_RX_HINT,Force Local Receiver Preset Hint. Indicates the RxPresetHint value of EQ Slave(DSP in EQ Phase2/USP in EQ Phase3) instead of received or set value. If select rate in the EQ_RATE_SEL field is other than 8.0GT/s Speed this feature is.." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x4 12.--17. 1. "FORCE_LOCAL_TX_POST_CURSOR,Force Local Transmitter Post-Cursor. Indicates the coefficient value of EQ Slave(DSP in EQ Phase2/USP in EQ Phase3) instead of the value instructed from link partner. Note: This register field is sticky." newline hexmask.long.byte 0x4 6.--11. 1. "FORCE_LOCAL_TX_CURSOR,Force Local Transmitter Cursor. Indicates the coefficient value of EQ Slave(DSP in EQ Phase2/USP in EQ Phase3) instead of the value instructed from link partner. Note: This register field is sticky." newline hexmask.long.byte 0x4 0.--5. 1. "FORCE_LOCAL_TX_PRE_CURSOR,Force Local Transmitter Pre-cursor. Indicates the coefficient value of EQ Slave(DSP in EQ Phase2/USP in EQ Phase3) instead of the value instructed from link partner. Note: This register field is sticky." line.long 0x8 "SD_EQ_CONTROL3_REG,Silicon Debug EQ Control 3. This viewport register returns the value for the rate and lane selected by the EQ_RATE_SEL and EQ_LANE_SEL fields in the SD_EQ_CONTROL1_REG register. For more details. see the RAS DES section in the Core.." rbitfld.long 0x8 29.--31. "RSVDP_29,Reserved for future use." "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 28. "FORCE_REMOTE_TX_COEF_ENABLE,Force Remote Transmitter Coefficient Enable. Enables the following fields: - FORCE_REMOTE_TX_PRE_CURSOR - FORCE_REMOTE_TX_CURSOR - FORCE_REMOTE_TX_POST_CURSOR This function can only be used when GEN3_EQ_FB_MODE =.." "0,1" newline hexmask.long.word 0x8 18.--27. 1. "RSVDP_18,Reserved for future use." newline hexmask.long.byte 0x8 12.--17. 1. "FORCE_REMOTE_TX_POST_CURSOR,Force Remote Transmitter Post-Cursor. Indicates the coefficient value of EQ Master(DSP in EQ Phase3/USP in EQ Phase2) instead of the value instructed from local phy in dirchange mode. Note: This register field is sticky." newline hexmask.long.byte 0x8 6.--11. 1. "FORCE_REMOTE_TX_CURSOR,Force Remote Transmitter Cursor. Indicates the coefficient value of EQ Master(DSP in EQ Phase3/USP in EQ Phase2) instead of the value instructed from local phy in dirchange mode. Note: This register field is sticky." newline hexmask.long.byte 0x8 0.--5. 1. "FORCE_REMOTE_TX_PRE_CURSOR,Force Remote Transmitter Pre-Cursor. Indicates the coefficient value of EQ Master(DSP in EQ Phase3/USP in EQ Phase2) instead of the value instructed from local phy in dirchange mode. Note: This register field is sticky." rgroup.long (0xE0+0x30C)++0xB line.long 0x0 "SD_EQ_STATUS1_REG,Silicon Debug EQ Status 1. This viewport register returns the first of three words of Silicon Debug EQ Status data for the rate and lane selected by the EQ_RATE_SEL and EQ_LANE_SEL fields in the SD_EQ_CONTROL1_REG register. The.." hexmask.long.tbyte 0x0 8.--31. 1. "RSVDP_8,Reserved for future use." newline bitfld.long 0x0 7. "EQ_REJECT_EVENT,EQ Reject Event. Indicates that the controller receives two consecutive TS1 OS w/Reject=1b during EQ Master phase(DSP in EQ Phase3/USP in EQ Phase2). This bit is automatically cleared when the controller starts EQ Master phase again." "0,1" newline bitfld.long 0x0 6. "EQ_RULEC_VIOLATION,EQ Rule C Violation. Indicates that coefficients rule C violation is detected in the values provided by PHY using direction change method during EQ Master phase(DSP in EQ Phase3/USP in EQ Phase2). The coefficients rule C correspond to.." "0,1" newline bitfld.long 0x0 5. "EQ_RULEB_VIOLATION,EQ Rule B Violation. Indicates that coefficients rule B violation is detected in the values provided by PHY using direction change method during EQ Master phase(DSP in EQ Phase3/USP in EQ Phase2). The coefficients rules B correspond to.." "0,1" newline bitfld.long 0x0 4. "EQ_RULEA_VIOLATION,EQ Rule A Violation. Indicates that coefficients rule A violation is detected in the values provided by PHY using direction change method during EQ Master phase(DSP in EQ Phase3/USP in EQ Phase2). The coefficients rules A correspond to.." "0,1" newline bitfld.long 0x0 3. "RSVDP_3,Reserved for future use." "0,1" newline bitfld.long 0x0 1.--2. "EQ_CONVERGENCE_INFO,EQ Convergence Info. Indicates equalization convergence information. - 0x0: Equalization is not attempted - 0x1: Equalization finished successfully - 0x2: Equalization finished unsuccessfully - 0x3: Reserved This bit is automatically.." "Equalization is not attempted,Equalization finished successfully,Equalization finished unsuccessfully,Reserved" newline bitfld.long 0x0 0. "EQ_SEQUENCE,EQ Sequence. Indicates that the controller is starting the equalization sequence. Note: This register field is sticky." "0,1" line.long 0x4 "SD_EQ_STATUS2_REG,Silicon Debug EQ Status 2. This viewport register returns the second of three words of Silicon Debug EQ Status data for the rate and lane selected by the EQ_RATE_SEL and EQ_LANE_SEL fields in the SD_EQ_CONTROL1_REG register. Each field.." hexmask.long.byte 0x4 24.--31. 1. "EQ_LOCAL_FOM_VALUE,EQ Local Figure of Merit. Indicates Local maximum Figure of Merit value. Note: This register field is sticky." newline bitfld.long 0x4 21.--23. "RSVDP_21,Reserved for future use." "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 18.--20. "EQ_LOCAL_RX_HINT,EQ Local Receiver Preset Hint. Indicates Local Receiver Preset Hint value. If select rate in the EQ_RATE_SEL field is other than 8.0GT/s Speed this feature is not available. Note: This register field is sticky." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x4 12.--17. 1. "EQ_LOCAL_POST_CURSOR,EQ Local Post-Cursor. Indicates Local post cursor coefficient value. Note: This register field is sticky." newline hexmask.long.byte 0x4 6.--11. 1. "EQ_LOCAL_CURSOR,EQ Local Cursor. Indicates Local cursor coefficient value. Note: This register field is sticky." newline hexmask.long.byte 0x4 0.--5. 1. "EQ_LOCAL_PRE_CURSOR,EQ Local Pre-Cursor. Indicates Local pre cursor coefficient value. Note: This register field is sticky." line.long 0x8 "SD_EQ_STATUS3_REG,Silicon Debug EQ Status 3. This viewport register returns the third of three words of Silicon Debug EQ Status data for the rate and lane selected by the EQ_RATE_SEL and EQ_LANE_SEL fields in the SD_EQ_CONTROL1_REG register. Each field.." bitfld.long 0x8 30.--31. "RSVDP_30,Reserved for future use." "0,1,2,3" newline hexmask.long.byte 0x8 24.--29. 1. "EQ_REMOTE_FS,EQ Remote FS. Indicates Remote FS value. Note: This register field is sticky." newline hexmask.long.byte 0x8 18.--23. 1. "EQ_REMOTE_LF,EQ Remote LF. Indicates Remote LF value. Note: This register field is sticky." newline hexmask.long.byte 0x8 12.--17. 1. "EQ_REMOTE_POST_CURSOR,EQ Remote Post-Cursor. Indicates Remote post cursor coefficient value. Note: This register field is sticky." newline hexmask.long.byte 0x8 6.--11. 1. "EQ_REMOTE_CURSOR,EQ Remote Cursor. Indicates Remote cursor coefficient value. Note: This register field is sticky." newline hexmask.long.byte 0x8 0.--5. 1. "EQ_REMOTE_PRE_CURSOR,EQ Remote Pre-Cursor. Indicates Remote pre cursor coefficient value. Note: This register field is sticky." tree.end tree "PF0_SN_CAP (Device Serial Number Capability Structure)" group.long (0x0+0x170)++0xB line.long 0x0 "SN_BASE,Device Serial Number Extended Capability Header. For a description of this standard PCIe register. see the PCI Express Base Specification." hexmask.long.word 0x0 20.--31. 1. "SN_NEXT_OFFSET,Next Capability Offset. For a description of this standard PCIe register field see the PCI Express Base Specification. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then.." hexmask.long.byte 0x0 16.--19. 1. "SN_CAP_VERSION,Capability Version. For a description of this standard PCIe register field see the PCI Express Base Specification. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky).." hexmask.long.word 0x0 0.--15. 1. "SN_PCIE_EXTENDED_CAP_ID,Serial Number Extended Capability ID. For a description of this standard PCIe register field see the PCI Express Base Specification. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if.." line.long 0x4 "SER_NUM_REG_DW_1,Serial Number 1 Register. For a description of this standard PCIe register. see the PCI Express Base Specification." hexmask.long 0x4 0.--31. 1. "SN_SER_NUM_REG_1_DW,IEEE 64 bit Device Serial Number (DW 1). For a description of this standard PCIe register field see the PCI Express Base Specification. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if.." line.long 0x8 "SER_NUM_REG_DW_2,Serial Number 2 Register. For a description of this standard PCIe register. see the PCI Express Base Specification." hexmask.long 0x8 0.--31. 1. "SN_SER_NUM_REG_2_DW,IEEE 64 bit Device Serial Number (DW 2). For a description of this standard PCIe register field see the PCI Express Base Specification. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if.." tree.end tree "PF0_VSECRAS_CAP (PF RAS Datapath Protection Capability Structure (VSEC))" group.long (0x0+0x480)++0x3 line.long 0x0 "RASDP_EXT_CAP_HDR_OFF,PCIe Extended capability ID. Capability version and Next capability offset. For a description of this standard PCIe register. see the PCI Express Specification." hexmask.long.word 0x0 20.--31. 1. "NEXT_OFFSET,Next Capability Offset. For a description of this standard PCIe register see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else.." newline hexmask.long.byte 0x0 16.--19. 1. "CAP,Capability Version. For a description of this standard PCIe register see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note:.." newline hexmask.long.word 0x0 0.--15. 1. "ID,PCI Express Extended Capability ID. For a description of this standard PCIe register see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else.." rgroup.long (0x4+0x480)++0x3 line.long 0x0 "RASDP_VENDOR_SPECIFIC_HDR_OFF,Vendor Specific Header. For a description of this standard PCIe register. see the PCI Express Specification." hexmask.long.word 0x0 20.--31. 1. "VSEC_LENGTH,VSEC Length. For a description of this standard PCIe register see the PCI Express Specification. Note: This register field is sticky." newline hexmask.long.byte 0x0 16.--19. 1. "VSEC_REV,VSEC Rev. For a description of this standard PCIe register see the PCI Express Specification. Note: This register field is sticky." newline hexmask.long.word 0x0 0.--15. 1. "VSEC_ID,VSEC ID. For a description of this standard PCIe register see the PCI Express Specification. Note: This register field is sticky." group.long (0x8+0x480)++0x7 line.long 0x0 "RASDP_ERROR_PROT_CTRL_OFF,ECC error correction control. Allows you to disable ECC error correction for RAMs and datapath. When the AXI Bridge Module is implemented and the master / slave clocks are asynchronous to the PCIe native controller clock.." hexmask.long.byte 0x0 24.--31. 1. "RSVDP_24,Reserved for future use." newline bitfld.long 0x0 23. "ERROR_PROT_DISABLE_CXS_RX,Error correction disable for CXS Tx path (PCIe Rx path). Note: This register field is sticky." "0,1" newline bitfld.long 0x0 22. "ERROR_PROT_DISABLE_ADM_RX,Error correction disable for ADM Rx path. Note: This register field is sticky." "0,1" newline bitfld.long 0x0 21. "ERROR_PROT_DISABLE_LAYER3_RX,Error correction disable for layer 3 Rx path. Note: This register field is sticky." "0,1" newline bitfld.long 0x0 20. "ERROR_PROT_DISABLE_LAYER2_RX,Error correction disable for layer 2 Rx path. Note: This register field is sticky." "0,1" newline bitfld.long 0x0 19. "ERROR_PROT_DISABLE_DMA_READ,Error correction disable for DMA read engine. Note: This register field is sticky." "0,1" newline bitfld.long 0x0 18. "ERROR_PROT_DISABLE_AXI_BRIDGE_INBOUND_REQUEST,Error correction disable for AXI bridge inbound request path. Note: This register field is sticky." "0,1" newline bitfld.long 0x0 17. "ERROR_PROT_DISABLE_AXI_BRIDGE_INBOUND_COMPLETION,Error correction disable for AXI bridge inbound completion composer. Does not disable the error detection reporting for 1-bit and 2-bit ECC errors. Note: This register field is sticky." "?,bit and 2-bit ECC errors" newline bitfld.long 0x0 16. "ERROR_PROT_DISABLE_RX,Global error correction disable for all Rx layers. Note: This register field is sticky." "0,1" newline hexmask.long.byte 0x0 9.--15. 1. "RSVDP_9,Reserved for future use." newline bitfld.long 0x0 8. "ERROR_PROT_DISABLE_DTIM_TX,Error correction disable for DTIM Tx path. Note: This register field is sticky." "0,1" newline bitfld.long 0x0 7. "ERROR_PROT_DISABLE_CXS_TX,Error correction disable for CXS Rx path (PCIe Tx path). Note: This register field is sticky." "0,1" newline bitfld.long 0x0 6. "ERROR_PROT_DISABLE_ADM_TX,Error correction disable for Adm Tx path. Note: This register field is sticky." "0,1" newline bitfld.long 0x0 5. "ERROR_PROT_DISABLE_LAYER3_TX,Error correction disable for layer 3 Tx path. Note: This register field is sticky." "0,1" newline bitfld.long 0x0 4. "ERROR_PROT_DISABLE_LAYER2_TX,Error correction disable for layer 2 Tx path. Note: This register field is sticky." "0,1" newline bitfld.long 0x0 3. "ERROR_PROT_DISABLE_DMA_WRITE,Error correction disable for DMA write engine. Note: This register field is sticky." "0,1" newline bitfld.long 0x0 2. "ERROR_PROT_DISABLE_AXI_BRIDGE_OUTBOUND,Error correction disable for AXI bridge outbound request path. Note: This register field is sticky." "0,1" newline bitfld.long 0x0 1. "ERROR_PROT_DISABLE_AXI_BRIDGE_MASTER,Error correction disable for AXI bridge master completion buffer. Note: This register field is sticky." "0,1" newline bitfld.long 0x0 0. "ERROR_PROT_DISABLE_TX,Global error correction disable for all Tx layers. Does not disable the error detection reporting for 1-bit and 2-bit ECC errors. Note: This register field is sticky." "?,bit and 2-bit ECC errors" line.long 0x4 "RASDP_CORR_COUNTER_CTRL_OFF,Corrected error (1-bit ECC) counter selection and control. This is a viewport control register. Setting the CORR_COUNTER_SELECTION_REGION and CORR_COUNTER_SELECTION fields in this register determine the counter data returned.." hexmask.long.byte 0x4 24.--31. 1. "CORR_COUNTER_SELECTION,Counter selection. This field selects the counter ID (within the region defined by CORR_COUNTER_SELECTION_REGION) whose contents can be read from the RASDP_CORR_COUNT_REPORT_OFF register. You can cycle this field value from 0 to.." newline hexmask.long.byte 0x4 20.--23. 1. "CORR_COUNTER_SELECTION_REGION,Select correctable counter region: - 0x0: Region select for Adm Rx path - 0x1: Region select for layer 3 Rx path - 0x2: Region select for layer 2 Rx path - 0x3: Region select for DMA inbound path - 0x4: Region select for AXI.." newline hexmask.long.word 0x4 5.--19. 1. "RSVDP_5,Reserved for future use." newline bitfld.long 0x4 4. "CORR_EN_COUNTERS,Enable correctable errors counters. - 1: counters increment when the controller detects a correctable error - 0: counters are frozen The counters are enabled by default." "counters are frozen,counters increment when the controller detects a.." newline rbitfld.long 0x4 1.--3. "RSVDP_1,Reserved for future use." "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 0. "CORR_CLEAR_COUNTERS,Clear all correctable error counters." "0,1" rgroup.long (0x10+0x480)++0x3 line.long 0x0 "RASDP_CORR_COUNT_REPORT_OFF,Corrected error (1-bit ECC) counter data. This viewport register returns the counter data selected by the CORR_COUNTER_SELECTION_REGION and CORR_COUNTER_SELECTION fields in the RASDP_CORR_COUNTER_CTRL_OFF register." hexmask.long.byte 0x0 24.--31. 1. "CORR_COUNTER_SELECTED,Counter selection. Returns the value set in the CORR_COUNTER_SELECTION field of the RASDP_CORR_COUNTER_CTRL_OFF register." newline hexmask.long.byte 0x0 20.--23. 1. "CORR_COUNTER_SELECTED_REGION,Selected correctable counter region: - 0x0: Region select for Adm Rx path - 0x1: Region select for layer 3 Rx path - 0x2: Region select for layer 2 Rx path - 0x3: Region select for DMA inbound path - 0x4: Region select for.." newline hexmask.long.word 0x0 8.--19. 1. "RSVDP_8,Reserved for future use." newline hexmask.long.byte 0x0 0.--7. 1. "CORR_COUNTER,Current corrected error count for the selected counter." group.long (0x14+0x480)++0x3 line.long 0x0 "RASDP_UNCORR_COUNTER_CTRL_OFF,Uncorrected error (2-bit ECC and parity) counter selection and control. This is a viewport control register. Setting the UNCORR_COUNTER_SELECTION_REGION and UNCORR_COUNTER_SELECTION fields in this register determine the.." hexmask.long.byte 0x0 24.--31. 1. "UNCORR_COUNTER_SELECTION,Counter selection. This field selects the counter ID (within the region defined by UNCORR_COUNTER_SELECTION_REGION) whose contents can be read from the RASDP_UNCORR_COUNT_REPORT_OFF register. You can cycle this field value from 0.." newline hexmask.long.byte 0x0 20.--23. 1. "UNCORR_COUNTER_SELECTION_REGION,Select uncorrectable counter region: - 0x0: Region select for Adm Rx path - 0x1: Region select for layer 3 Rx path - 0x2: Region select for layer 2 Rx path - 0x3: Region select for DMA inbound path - 0x4: Region select for.." newline hexmask.long.word 0x0 5.--19. 1. "RSVDP_5,Reserved for future use." newline bitfld.long 0x0 4. "UNCORR_EN_COUNTERS,Enable uncorrectable errors counters. - 1: enables the counters to increment on detected correctable errors - 0: counters are frozen The counters are enabled by default." "counters are frozen,enables the counters to increment on detected.." newline rbitfld.long 0x0 1.--3. "RSVDP_1,Reserved for future use." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 0. "UNCORR_CLEAR_COUNTERS,Clear uncorrectable errors counters. When asserted causes all counters tracking the uncorrectable errors to be cleared." "0,1" rgroup.long (0x18+0x480)++0x3 line.long 0x0 "RASDP_UNCORR_COUNT_REPORT_OFF,Uncorrected error (2-bit ECC and parity) counter data. This viewport register returns the counter data selected by the UNCORR_COUNTER_SELECTION_REGION and UNCORR_COUNTER_SELECTION fields in the RASDP_UNCORR_COUNTER_CTRL_OFF.." hexmask.long.byte 0x0 24.--31. 1. "UNCORR_COUNTER_SELECTED,Counter selection. Returns the value set in the UNCORR_COUNTER_SELECTION field of the RASDP_UNCORR_COUNTER_CTRL_OFF register." newline hexmask.long.byte 0x0 20.--23. 1. "UNCORR_COUNTER_SELECTED_REGION,Selected uncorrectable counter region: - 0x0: Region select for Adm Rx path - 0x1: Region select for layer 3 Rx path - 0x2: Region select for layer 2 Rx path - 0x3: Region select for DMA inbound path - 0x4: Region select.." newline hexmask.long.word 0x0 8.--19. 1. "RSVDP_8,Reserved for future use." newline hexmask.long.byte 0x0 0.--7. 1. "UNCORR_COUNTER,Current uncorrected error count for the selected counter" group.long (0x1C+0x480)++0x3 line.long 0x0 "RASDP_ERROR_INJ_CTRL_OFF,Error injection control for the following features: - 1-bit or 2-bit injection - Continuous or fixed-number (n) injection modes - Global enable/disable - Selectable location where injection occurs" hexmask.long.byte 0x0 24.--31. 1. "RSVDP_24,Reserved for future use." newline hexmask.long.byte 0x0 16.--23. 1. "ERROR_INJ_LOC,Error injection location. Selects where error injection takes place. You can cycle this field value from 0 to 255 to access all locations according to the detailed report of check points at.." newline hexmask.long.byte 0x0 8.--15. 1. "ERROR_INJ_COUNT,Error injection count. - 0: errors are inserted in every TLP until you clear ERROR_INJ_EN. - 1: one errors injected - 2: two errors injected - n: amount of errors injected" newline rbitfld.long 0x0 6.--7. "RSVDP_6,Reserved for future use." "0,1,2,3" newline bitfld.long 0x0 4.--5. "ERROR_INJ_TYPE,Error injection type: - 0: none - 1: 1-bit - 2: 2-bit" "none,bit,bit,?" newline rbitfld.long 0x0 1.--3. "RSVDP_1,Reserved for future use." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 0. "ERROR_INJ_EN,Error injection global enable. When set enables the error insertion logic." "0,1" rgroup.long (0x20+0x480)++0x7 line.long 0x0 "RASDP_CORR_ERROR_LOCATION_OFF,Corrected errors locations. For more details. see the RAS Data Protection (DP) section in the Core Operations chapter of the Databook." hexmask.long.byte 0x0 24.--31. 1. "LOC_LAST_CORR_ERROR,Location/ID of the last corrected error within the region defined by REG_LAST_CORR_ERROR. You can cycle this field value from 0 to 255 to access all counters according to the detailed report of check points at.." newline hexmask.long.byte 0x0 20.--23. 1. "REG_LAST_CORR_ERROR,Region of the last corrected error: - 0x0: Region select for Adm Rx path - 0x1: Region select for layer 3 Rx path - 0x2: Region select for layer 2 Rx path - 0x3: Region select for DMA inbound path - 0x4: Region select for AXI bridge.." newline hexmask.long.byte 0x0 16.--19. 1. "RSVDP_16,Reserved for future use." newline hexmask.long.byte 0x0 8.--15. 1. "LOC_FIRST_CORR_ERROR,Location/ID of the first corrected error within the region defined by REG_FIRST_CORR_ERROR. You can cycle this field value from 0 to 255 to access all counters according to the detailed report of check points at.." newline hexmask.long.byte 0x0 4.--7. 1. "REG_FIRST_CORR_ERROR,Region of the first corrected error: - 0x0: Region select for Adm Rx path - 0x1: Region select for layer 3 Rx path - 0x2: Region select for layer 2 Rx path - 0x3: Region select for DMA inbound path - 0x4: Region select for AXI bridge.." newline hexmask.long.byte 0x0 0.--3. 1. "RSVDP_0,Reserved for future use." line.long 0x4 "RASDP_UNCORR_ERROR_LOCATION_OFF,Uncorrected errors locations. For more details. see the RAS Data Protection (DP) section in the Core Operations chapter of the Databook." hexmask.long.byte 0x4 24.--31. 1. "LOC_LAST_UNCORR_ERROR,Location/ID of the last uncorrected error within the region defined by REG_LAST_UNCORR_ERROR. You can cycle this field value from 0 to 255 to access all counters according to the detailed report of check points at.." newline hexmask.long.byte 0x4 20.--23. 1. "REG_LAST_UNCORR_ERROR,Region of the last uncorrected error: - 0x0: Region select for Adm Rx path - 0x1: Region select for layer 3 Rx path - 0x2: Region select for layer 2 Rx path - 0x3: Region select for DMA inbound path - 0x4: Region select for AXI.." newline hexmask.long.byte 0x4 16.--19. 1. "RSVDP_16,Reserved for future use." newline hexmask.long.byte 0x4 8.--15. 1. "LOC_FIRST_UNCORR_ERROR,Location/ID of the first uncorrected error within the region defined by REG_FIRST_UNCORR_ERROR. You can cycle this field value from 0 to 255 to access all counters according to the detailed report of check points at.." newline hexmask.long.byte 0x4 4.--7. 1. "REG_FIRST_UNCORR_ERROR,Region of the first uncorrected error: - 0x0: Region select for Adm Rx path - 0x1: Region select for layer 3 Rx path - 0x2: Region select for layer 2 Rx path - 0x3: Region select for DMA inbound path - 0x4: Region select for AXI.." newline hexmask.long.byte 0x4 0.--3. 1. "RSVDP_0,Reserved for future use." group.long (0x28+0x480)++0x7 line.long 0x0 "RASDP_ERROR_MODE_EN_OFF,RASDP error mode enable. The controller enters RASDP error mode (if ERROR_MODE_EN =1) upon detection of the first uncorrectable error. During this mode: - Rx TLPs that are forwarded to your application are not guaranteed to be.." hexmask.long 0x0 2.--31. 1. "RSVDP_2,Reserved for future use." newline bitfld.long 0x0 1. "AUTO_LINK_DOWN_EN,Write '1' to enable the controller to bring the link down when the controller enters RASDP error mode. Note: This register field is sticky." "0,1" newline bitfld.long 0x0 0. "ERROR_MODE_EN,Write '1' to enable the controller enter RASDP error mode when it detects an uncorrectable error. Note: This register field is sticky." "0,1" line.long 0x4 "RASDP_ERROR_MODE_CLEAR_OFF,Exit RASDP error mode. For more details. see the RAS Data Protection (DP) section in the Core Operations chapter of the Databook." hexmask.long 0x4 1.--31. 1. "RSVDP_1,Reserved for future use." newline bitfld.long 0x4 0. "ERROR_MODE_CLEAR,Write '1' to take the controller out of RASDP error mode. The controller will then report uncorrectable errors (through AER internal error reporting) and also stop nullifying/discarding TLPs." "0,1" rgroup.long (0x30+0x480)++0x7 line.long 0x0 "RASDP_RAM_ADDR_CORR_ERROR_OFF,RAM Address where a corrected error (1-bit ECC) has been detected. For more details. see the RAS Data Protection (DP) section in the Core Operations chapter of the Databook." hexmask.long.byte 0x0 28.--31. 1. "RAM_INDEX_CORR_ERROR,RAM index where a corrected error (1-bit ECC) has been detected." newline bitfld.long 0x0 27. "RSVDP_27,Reserved for future use." "0,1" newline hexmask.long 0x0 0.--26. 1. "RAM_ADDR_CORR_ERROR,RAM Address where a corrected error (1-bit ECC) has been detected." line.long 0x4 "RASDP_RAM_ADDR_UNCORR_ERROR_OFF,RAM Address where an uncorrected error (2-bit ECC) has been detected. For more details. see the RAS Data Protection (DP) section in the Core Operations chapter of the Databook." hexmask.long.byte 0x4 28.--31. 1. "RAM_INDEX_UNCORR_ERROR,RAM index where an uncorrected error (2-bit ECC) has been detected." newline bitfld.long 0x4 27. "RSVDP_27,Reserved for future use." "0,1" newline hexmask.long 0x4 0.--26. 1. "RAM_ADDR_UNCORR_ERROR,RAM Address where an uncorrected error (2-bit ECC) has been detected." tree.end tree "PF0_RTR_CAP (PF RTR Capability Structure)" group.long (0x0+0x2F8)++0xB line.long 0x0 "RTR_EXT_CAP_HDR_OFF,Readiness Time Reporting PCI Express Extended Capability Header. For a description of this standard PCIe register. see the PCI Express Specification." hexmask.long.word 0x0 20.--31. 1. "RTR_NEXT_OFFSET,Next Capability Offset. For a description of this standard PCIe register field see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky).." hexmask.long.byte 0x0 16.--19. 1. "RTR_CAP_VERSION,Capability Version. For a description of this standard PCIe register field see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky).." hexmask.long.word 0x0 0.--15. 1. "RTR_EXT_CAP_ID,PCI Express Extended Capability ID. For a description of this standard PCIe register field see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then.." line.long 0x4 "READI_TIME_REPORTING1_OFF,Readiness Time Reporting 1. For a description of this standard PCIe register. see the PCI Express Specification." bitfld.long 0x4 31. "RTR_TIME_VALID,Valid. For a description of this standard PCIe register field see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky)" "0,1" hexmask.long.byte 0x4 24.--30. 1. "RSVDP_24,Reserved for future use." hexmask.long.word 0x4 12.--23. 1. "DL_UP_TIME,DL_UP Time. For a description of this standard PCIe register field see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky)" hexmask.long.word 0x4 0.--11. 1. "RESET_TIME,Reset Time. For a description of this standard PCIe register field see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky)" line.long 0x8 "READI_TIME_REPORTING2_OFF,Readiness Time Reporting 2. For a description of this standard PCIe register. see the PCI Express Specification." hexmask.long.byte 0x8 24.--31. 1. "RSVDP_24,Reserved for future use." hexmask.long.word 0x8 12.--23. 1. "D3HOT_D0_TIME,D3hot to D0 Time. For a description of this standard PCIe register field see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else.." hexmask.long.word 0x8 0.--11. 1. "FLR_TIME,FLR Time. For a description of this standard PCIe register field see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky)" tree.end tree "PF0_RTR_CAP_DBI2 (DBI2 Shadow Block: PF RTR Capability Structure)" rgroup.long (0x4+0x12F8)++0x7 line.long 0x0 "SHADOW_READI_TIME_REPORTING1_OFF,Shadow Register Readiness Time Reporting 1. For a description of this standard PCIe register. see the PCI Express Specification." bitfld.long 0x0 31. "RTR_TIME_VALID,Shadow Valid in the shadow register. For a description of this standard PCIe register field see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access - Dbi: No access - Dbi2: if.." "0,1" hexmask.long.tbyte 0x0 12.--30. 1. "RSVDP_12,Reserved for future use." hexmask.long.word 0x0 0.--11. 1. "RESET_TIME,Shadow Reset Time in the shadow register. For a description of this standard PCIe register field see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access - Dbi: No access - Dbi2: if.." line.long 0x4 "SHADOW_READI_TIME_REPORTING2_OFF,Shadow Register Readiness Time Reporting 2. For a description of this standard PCIe register. see the PCI Express Specification." hexmask.long.byte 0x4 24.--31. 1. "RSVDP_24,Reserved for future use." hexmask.long.word 0x4 12.--23. 1. "D3HOT_D0_TIME,Shadow D3hot to D0 Time in the shadow register. For a description of this standard PCIe register field see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access - Dbi: No access - Dbi2:.." hexmask.long.word 0x4 0.--11. 1. "FLR_TIME,Shadow FLR Time in the shadow register. For a description of this standard PCIe register field see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access - Dbi: No access - Dbi2: if.." tree.end tree "PF0_FRSQ_CAP (PF FRSQ Capability Structure)" group.long (0x0+0x2E8)++0xB line.long 0x0 "FRSQ_EXT_CAP_HDR_OFF,FRS Queuing Extended Capability Header. For a description of this standard PCIe register. see the PCI Express Specification." hexmask.long.word 0x0 20.--31. 1. "FRSQ_NEXT_OFFSET,Next Capability Offset. For a description of this standard PCIe register field see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then.." hexmask.long.byte 0x0 16.--19. 1. "FRSQ_CAP_VERSION,Capability Version. For a description of this standard PCIe register field see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky).." hexmask.long.word 0x0 0.--15. 1. "FRSQ_EXT_CAP_ID,PCI Express Extended Capability ID. For a description of this standard PCIe register field see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then.." line.long 0x4 "FRSQ_CAP_OFF,FRS Queuing Capability Register. For a description of this standard PCIe register. see the PCI Express Specification." hexmask.long.word 0x4 21.--31. 1. "RSVDP_21,Reserved for future use." hexmask.long.byte 0x4 16.--20. 1. "FRS_INT_MESSAGE_NUMBER,FRS Interrupt Message Number. For a description of this standard PCIe register field see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1).." hexmask.long.byte 0x4 12.--15. 1. "RSVDP_12,Reserved for future use." hexmask.long.word 0x4 0.--11. 1. "FRSQ_MAX_DEPTH,FRS Queue Max Depth. For a description of this standard PCIe register field see the PCI Express Specification." line.long 0x8 "FRSQ_CONTROL_FRSQ_STATUS_OFF,FRS Queuing Status and Control Register. For a description of this standard PCIe register. see the PCI Express Specification." hexmask.long.word 0x8 17.--31. 1. "RSVDP_17,Reserved for future use." bitfld.long 0x8 16. "FRS_INTERRUPT_ENABLE,FRS Interrupt Enable. For a description of this standard PCIe register field see the PCI Express Specification." "0,1" hexmask.long.word 0x8 2.--15. 1. "RSVDP_2,Reserved for future use." bitfld.long 0x8 1. "FRS_MESSAGE_OVERFLOW,FRS Message Overflow. For a description of this standard PCIe register field see the PCI Express Specification." "0,1" newline bitfld.long 0x8 0. "FRS_MESSAGE_RECEIVED,FRS Message Received. For a description of this standard PCIe register field see the PCI Express Specification." "0,1" rgroup.long (0xC+0x2E8)++0x3 line.long 0x0 "FRS_MESSAGE_QUEUE_OFF,FRS Message Queue Register. For a description of this standard PCIe register. see the PCI Express Specification." hexmask.long.word 0x0 20.--31. 1. "FRS_MESSAGE_QUE_DEPTH,FRS Message Queue Depth. For a description of this standard PCIe register field see the PCI Express Specification." hexmask.long.byte 0x0 16.--19. 1. "FRS_MESSAGE_QUE_REASON,FRS Message Queue Reason. For a description of this standard PCIe register field see the PCI Express Specification." hexmask.long.word 0x0 0.--15. 1. "FRS_MESSAGE_QUE_FUNC_ID,FRS Message Queue Function ID. For a description of this standard PCIe register field see the PCI Express Specification." tree.end tree "PF0_PTM_CAP (PF PTM Capability Structure)" group.long (0x0+0x40C)++0xB line.long 0x0 "PTM_EXT_CAP_HDR_OFF,Precision Time Measurement Capability Header. For a description of this standard PCIe register. see the PCI Express Specification." hexmask.long.word 0x0 20.--31. 1. "PTM_NEXT_OFFSET,Precision Time Measurement PCI Express Extended Capability Next Offset. For a description of this standard PCIe register see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access. -.." hexmask.long.byte 0x0 16.--19. 1. "PTM_CAP_VERSION,Precision Time Measurement PCI Express Extended Capability Version. For a description of this standard PCIe register see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi:.." hexmask.long.word 0x0 0.--15. 1. "PTM_CAP_ID,Precision Time Measurement PCI Express Extended Capability ID. For a description of this standard PCIe register see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if.." line.long 0x4 "PTM_CAP_OFF,PTM Capability Register. For a description of this standard PCIe register. see the PCI Express Specification." hexmask.long.word 0x4 16.--31. 1. "RSVDP_16,Reserved for future use." hexmask.long.byte 0x4 8.--15. 1. "PTM_CLK_GRAN,PTM Local Clock Granularity. For a description of this standard PCIe register see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky).." hexmask.long.byte 0x4 3.--7. 1. "RSVDP_3,Reserved for future use." bitfld.long 0x4 2. "PTM_ROOT_CAPABLE,PTM Root Capable. For a description of this standard PCIe register see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else.." "0,1" bitfld.long 0x4 1. "PTM_RES_CAPABLE,PTM Responder Capable. For a description of this standard PCIe register see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else.." "0,1" newline bitfld.long 0x4 0. "PTM_REQ_CAPABLE,PTM Requester Capable. For a description of this standard PCIe register see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else.." "0,1" line.long 0x8 "PTM_CONTROL_OFF,PTM Control Register. For a description of this standard PCIe register. see the PCI Express Specification." hexmask.long.word 0x8 16.--31. 1. "RSVDP_16,Reserved for future use." hexmask.long.byte 0x8 8.--15. 1. "EFF_GRAN,PTM Effective Granularity. For a description of this standard PCIe register see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: HWINIT" hexmask.long.byte 0x8 2.--7. 1. "RSVDP_2,Reserved for future use." rbitfld.long 0x8 1. "ROOT_SELECT,PTM Root Select. When set this Time Source is the PTM Root. For a description of this standard PCIe register see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: HWINIT" "0,1" bitfld.long 0x8 0. "PTM_ENABLE,PTM Enable. When set this function is permitted to participate in the PTM mechanism. For a description of this standard PCIe register see the PCI Express Specification." "0,1" tree.end tree "PF0_PTM_RES_CAP (PF PTM Responder Capability Structure (VSEC))" group.long (0x0+0x418)++0xB line.long 0x0 "PTM_RES_CAP_HDR_OFF,Precision Time Measurement Responder Capability Header (VSEC). For more details. see the PTM section in the Databook." hexmask.long.word 0x0 20.--31. 1. "PTM_RES_EXT_CAP_NEXT_OFFS,Precision Time Measurement Responder VSEC Next Pointer. For more details see the PTM section in the Databook. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then.." hexmask.long.byte 0x0 16.--19. 1. "PTM_RES_EXT_CAP_VER,Precision Time Measurement Responder VSEC Version. For more details see the PTM section in the Databook. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else.." hexmask.long.word 0x0 0.--15. 1. "PTM_RES_EXT_CAP_ID,Precision Time Measurement Responder VSEC ID. For more details see the PTM section in the Databook. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else.." line.long 0x4 "PTM_RES_HDR_OFF,Precision Time Measurement Responder Vendor Specific Header. For more details. see the PTM section in the Databook." hexmask.long.word 0x4 20.--31. 1. "PTM_RES_VSEC_LENGTH,PTM Responder VSEC Length. For more details see the PTM section in the Databook. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This.." hexmask.long.byte 0x4 16.--19. 1. "PTM_RES_VSEC_REV,PTM Responder VSEC Revision. For more details see the PTM section in the Databook. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This.." hexmask.long.word 0x4 0.--15. 1. "PTM_RES_VSEC_ID,PTM Responder VSEC ID. For more details see the PTM section in the Databook. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register.." line.long 0x8 "PTM_RES_CONTROL_OFF,PTM Responder Control Register. For more details. see the PTM section in the Databook." hexmask.long 0x8 2.--31. 1. "RSVDP_2,Reserved for future use." bitfld.long 0x8 1. "PTM_RES_PDEL_BYTE_REV,PTM Requester Propagation Delay Byte Reversal - Reverse the order of bytes in the PTM Propagation Delay data word of the PTM ResponseD Message for compatibility with previous revisions. For more details see the PTM section in the.." "0,1" bitfld.long 0x8 0. "PTM_RES_CCONTEXT_VALID,PTM Responder Control Context Valid - PTM Local Timing is valid. This bit is set over the DBI. A speed change or aux_clk_active will set this bit low. For more details see the PTM section in the Databook. Note: The access.." "0,1" rgroup.long (0xC+0x418)++0x3 line.long 0x0 "PTM_RES_STATUS_OFF,PTM Responder Status Register. For more details. see the PTM section in the Databook." hexmask.long 0x0 2.--31. 1. "RSVDP_2,Reserved for future use." bitfld.long 0x0 1. "PTM_RES_REQUEST_RECEIVED,PTM 1st Request Received - PTM Responder has received the first PTM Request Message. Upon receipt of a second PTM Request Message a ResponseD message with timing information will be sent from the Responder if the context is.." "0,1" bitfld.long 0x0 0. "PTM_RES_CONTEXT_VALID,PTM Responder Status Context Valid - PTM Local Timing Context is Valid. Value set from upstream port Requester in a Switch. Shadows the same in the control register in all other products. For more details see the PTM section in the.." "0,1" group.long (0x10+0x418)++0x7 line.long 0x0 "PTM_RES_LOCAL_LSB_OFF,PTM Responder Local Clock LSB. For more details. see the PTM section in the Databook." hexmask.long 0x0 0.--31. 1. "PTM_RES_LOCAL_LSB,PTM Responder Local Clock LSB - Lower 32 bits of local timer value. For more details see the PTM section in the Databook. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then.." line.long 0x4 "PTM_RES_LOCAL_MSB_OFF,PTM Responder Local Clock MSB. For more details. see the PTM section in the Databook." hexmask.long 0x4 0.--31. 1. "PTM_RES_LOCAL_MSB,PTM Responder Local Clock MSB - Upper 32 bits of local timer value. For more details see the PTM section in the Databook. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then.." rgroup.long (0x18+0x418)++0x1F line.long 0x0 "PTM_RES_T2_LSB_OFF,PTM Responder T2 Timestamp LSB. For more details. see the PTM section in the Databook." hexmask.long 0x0 0.--31. 1. "PTM_RES_T2_LSB,PTM Responder T2 Timestamp LSB - Lower 32 bits of the T2 Timestamp value. For more details see the PTM section in the Databook. Note: This register field is sticky." line.long 0x4 "PTM_RES_T2_MSB_OFF,PTM Responder T2 Timestamp MSB. For more details. see the PTM section in the Databook." hexmask.long 0x4 0.--31. 1. "PTM_RES_T2_MSB,PTM Responder T2 Timestamp MSB - Upper 32 bits of the T2 Timestamp value. For more details see the PTM section in the Databook. Note: This register field is sticky." line.long 0x8 "PTM_RES_T2P_LSB_OFF,PTM Responder T2 Previous Timestamp LSB. For more details. see the PTM section in the Databook." hexmask.long 0x8 0.--31. 1. "PTM_RES_T2P_LSB,PTM Responder T2 Previous Timestamp LSB - Lower 32 bits of the previously stored T2 Timestamp value. For more details see the PTM section in the Databook. Note: This register field is sticky." line.long 0xC "PTM_RES_T2P_MSB_OFF,PTM Responder T2 Previous Timestamp MSB. For more details. see the PTM section in the Databook." hexmask.long 0xC 0.--31. 1. "PTM_RES_T2P_MSB,PTM Responder T2 Previous Timestamp MSB - Upper 32 bits of the previously stored T2 Timestamp value. For more details see the PTM section in the Databook. Note: This register field is sticky." line.long 0x10 "PTM_RES_T3_LSB_OFF,PTM Responder T3 Timestamp LSB. For more details. see the PTM section in the Databook." hexmask.long 0x10 0.--31. 1. "PTM_RES_T3_LSB,PTM Responder T3 Timestamp LSB - Lower 32 bits of the T3 Timestamp value. For more details see the PTM section in the Databook. Note: This register field is sticky." line.long 0x14 "PTM_RES_T3_MSB_OFF,PTM Responder T3 Timestamp MSB. For more details. see the PTM section in the Databook." hexmask.long 0x14 0.--31. 1. "PTM_RES_T3_MSB,PTM Responder T3 Timestamp MSB - Upper 32 bits of the T2 Timestamp value. For more details see the PTM section in the Databook. Note: This register field is sticky." line.long 0x18 "PTM_RES_T3P_LSB_OFF,PTM Responder T3 Previous Timestamp LSB. For more details. see the PTM section in the Databook." hexmask.long 0x18 0.--31. 1. "PTM_RES_T3P_LSB,PTM Responder T3 Previous Timestamp LSB - Lower 32 bits of the previously stored T3 Timestamp value. For more details see the PTM section in the Databook. Note: This register field is sticky." line.long 0x1C "PTM_RES_T3P_MSB_OFF,PTM Responder T3 Previous Timestamp MSB. For more details. see the PTM section in the Databook." hexmask.long 0x1C 0.--31. 1. "PTM_RES_T3P_MSB,PTM Responder T3 Previous Timestamp MSB - Upper 32 bits of the previously stored T3 Timestamp value. For more details see the PTM section in the Databook. Note: This register field is sticky." group.long (0x38+0x418)++0x7 line.long 0x0 "PTM_RES_TX_LATENCY_OFF,PTM Responder TX Latency. For more details. see the PTM section in the Databook." hexmask.long.tbyte 0x0 12.--31. 1. "RSVDP_12,Reserved for future use." hexmask.long.word 0x0 0.--11. 1. "PTM_RES_TX_LATENCY,PTM Responder TX Latency - Responder Transmit path latency (12 bit wide). For more details see the PTM section in the Databook. Note: This register field is sticky." line.long 0x4 "PTM_RES_RX_LATENCY_OFF,PTM Responder RX Latency. For more details. see the PTM section in the Databook." hexmask.long.tbyte 0x4 12.--31. 1. "RSVDP_12,Reserved for future use." hexmask.long.word 0x4 0.--11. 1. "PTM_RES_RX_LATENCY,PTM Responder RX Latency - Responder Receive path latency (12 bit wide). For more details see the PTM section in the Databook. Note: This register field is sticky." rgroup.long (0x40+0x418)++0x3 line.long 0x0 "PTM_RES_NOM_CLOCK_T_OFF,PTM Responder Nominal Clock Period. For more details. see the PTM section in the Databook." hexmask.long.byte 0x0 24.--31. 1. "RSVDP_24,Reserved for future use." hexmask.long.byte 0x0 16.--23. 1. "PTM_RES_NOM_CLOCK_T_INT,PTM Responder Nominal Clock Period Integral - Integral part of the nominal PTM local clock period in nanoseconds. For more details see the PTM section in the Databook. Note: This register field is sticky." hexmask.long.word 0x0 0.--15. 1. "PTM_RES_NOM_CLOCK_T_FRAC,PTM Responder Nominal Clock Period Fractional - Fractional part of the nominal PTM local clock period. LSB is 1/(2^16) nanoseconds. For more details see the PTM section in the Databook. Note: This register field is sticky." group.long (0x44+0x418)++0x3 line.long 0x0 "PTM_RES_SCALED_CLOCK_T_OFF,PTM Responder Scaled Clock Period. For more details. see the PTM section in the Databook." bitfld.long 0x0 31. "PTM_RES_SCALED_CLOCK_T_EN,PTM Responder Scaled Clock Period Enable - Use the programmed scaled PTM clock period rather than the nominal values. This bit is cleared when the core_clk rate starts to change and can only be set when the clock period change.." "0,1" hexmask.long.byte 0x0 24.--30. 1. "RSVDP_24,Reserved for future use." hexmask.long.byte 0x0 16.--23. 1. "PTM_RES_SCALED_CLOCK_T_INT,PTM Responder Scaled Clock Period Integral - Integral part of the nominal PTM local clock period in nanoseconds. For more details see the PTM section in the Databook. Note: This register field is sticky." newline hexmask.long.word 0x0 0.--15. 1. "PTM_RES_SCALED_CLOCK_T_FRAC,PTM Responder Scaled Clock Period Fractional - Fractional part of the nominal PTM local clock period. LSB is 1/(2^16) nanoseconds. For more details see the PTM section in the Databook. Note: This register field is sticky." tree.end tree "PF0_PM_CAP (PF PCI Power Management Capability Structure)" group.long (0x0+0x40)++0x7 line.long 0x0 "CAP_ID_NXT_PTR_REG,Power Management Capabilities Register." hexmask.long.byte 0x0 27.--31. 1. "PME_SUPPORT,PME_Support. This 5-bit field indicates the power states in which the function may generate a PME and/or forward PME messages. A value of 0b for any bit indicates that the function is not capable of asserting PME while in that power state. -.." bitfld.long 0x0 26. "D2_SUPPORT,D2_Support. If this bit is set this function supports the D2 Power Management state. Functions that do not support D2 must always return a value of 0b for this bit. Note: The access attributes of this field are as follows: - Wire: No access." "0,1" bitfld.long 0x0 25. "D1_SUPPORT,D1_Support. If this bit is set this function supports the D1 Power Management state. Functions that do not support D1 must always return a value of 0b for this bit. Note: The access attributes of this field are as follows: - Wire: No access." "0,1" bitfld.long 0x0 22.--24. "AUX_CURR,Aux_Current. This 3 bit field reports the Vaux auxiliary current requirements for the function. If this function implements the Data Register the controller hardwires this field to 000b. If PME_Support is 0 xxxxb (PME assertion from D3cold is.." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 21. "DSI,Device Specific Initialization. The DSI bit indicates whether special initialization of this function is required. When set indicates that the function requires a device specific initialization sequence following a transition to the D0uninitialized.." "0,1" bitfld.long 0x0 20. "PME_IMM_READI_RETURN_DO,Immediate_Readiness_on_Return_to_D0. - If this bit is a '1' this function is guaranteed to be ready to successfully complete valid accesses immediately after being set to D0. These accesses include configuration cycles and if.." "0,1" rbitfld.long 0x0 19. "PME_CLK,PME Clock. Does not apply to PCI Express the controller hardwires it to 0b. Note: This register field is sticky." "0,1" bitfld.long 0x0 16.--18. "PM_SPEC_VER,Version. This field provides the Power Management specification version. The controller hardwires this field to 011b for functions compliant to PCI Express Base Specification Revision 4.0 Version 1.0>. Note: The access attributes of this.." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x0 8.--15. 1. "PM_NEXT_POINTER,Next Capability Pointer. This field provides an offset into the function's configuration space pointing to the location of next item in the capabilities list. If there are no additional items in the capabilities list this field is set to.." hexmask.long.byte 0x0 0.--7. 1. "PM_CAP_ID,Capability ID. This field returns 01h to indicate that this is the PCI Power Management Capability. Each function may have only one item in its capability list with Capability ID set to 01h." line.long 0x4 "CON_STATUS_REG,Power Management Control and Status Register. This register is used to manage the PCI function's power management state as well as to enable/monitor PMEs." hexmask.long.byte 0x4 24.--31. 1. "DATA_REG_ADD_INFO,Data. This field is used to report the state dependent data requested by the Data_Select field. The value of this field is scaled by the value reported by the Data_Scale field." rbitfld.long 0x4 23. "BUS_PWR_CLK_CON_EN,Bus Power/Clock Control Enable. For a description of this standard PCIe register field see the PCI Express Base Specification." "0,1" rbitfld.long 0x4 22. "B2_B3_SUPPORT,B2B3 Support for D3hot. For a description of this standard PCIe register field see the PCI Express Base Specification." "0,1" hexmask.long.byte 0x4 16.--21. 1. "RSVDP_16,Reserved for future use." newline bitfld.long 0x4 15. "PME_STATUS,PME_Status. This bit is set when the function normally generates a PME signal. The value of this bit is not affected by the value of the PME_En bit. If PME_Support bit 31 of the Power Management Capabilities register is clear this bit is.." "0,1" rbitfld.long 0x4 13.--14. "DATA_SCALE,Data_Scale. This field indicates the scaling factor to be used when interpreting the value of the Data field. The value and meaning of this field varies depending on which data value has been selected by the Data_Select field. For more details.." "0,1,2,3" hexmask.long.byte 0x4 9.--12. 1. "DATA_SELECT,Data_Select. This 4-bit field is used to select which data is to be reported through the Data and Data_Scale field. If the Data field is not implemented this field must be hardwired to 0000b." bitfld.long 0x4 8. "PME_ENABLE,PME_En. - When set the function is permitted to generate a PME. - When clear the function is not permitted to generate a PME. If PME_Support is 1 xxxxb (PME generation from D3cold) or the function consumes Aux power and Aux power is.." "0,1" newline hexmask.long.byte 0x4 4.--7. 1. "RSVDP_4,Reserved for future use." bitfld.long 0x4 3. "NO_SOFT_RST,No_Soft_Reset. This bit indicates the state of the function after writing the PowerState field to transition the function from D3hot to D0. - When set this transition preserves internal function state. The function is in D0Active and no.." "0,1" rbitfld.long 0x4 2. "RSVDP_2,Reserved for future use." "0,1" bitfld.long 0x4 0.--1. "POWER_STATE,PowerState. This 2-bit field is used both to determine the current power state of a function and to set the function into a new power state. The definition of the field values is given below. You can write to this register; however the.." "D0,D1,D2,D3hot" tree.end tree "PF0_PCIE_CAP (PF PCI Express Capability Structure)" group.long (0x0+0x70)++0x33 line.long 0x0 "PCIE_CAP_ID_PCIE_NEXT_CAP_PTR_PCIE_CAP_REG,PCI Express Capabilities. ID. Next Pointer Register." rbitfld.long 0x0 31. "RSVDP_31,Reserved for future use." "0,1" rbitfld.long 0x0 30. "RSVD,Reserved." "0,1" newline hexmask.long.byte 0x0 25.--29. 1. "PCIE_INT_MSG_NUM,PCIE Interrupt Message Number. For a description of this standard PCIe register field see the PCI Express Base Specification. Interrupt Message Number. This field indicates which MSI/MSI-X vector is used for the interrupt message.." bitfld.long 0x0 24. "PCIE_SLOT_IMP,Slot Implemented. When set this bit indicates that the Link associated with this Port is connected to a slot (as compared to being connected to a system-integrated device or being disabled). This bit is valid for Downstream Ports. This bit.." "0,1" newline hexmask.long.byte 0x0 20.--23. 1. "PCIE_DEV_PORT_TYPE,Device/Port Type. Indicates the specific type of this PCI Express function. Note: Different functions in a Multi-Function Device can generally be of different types. Defined encodings for functions that implement a Type 00h PCI.." hexmask.long.byte 0x0 16.--19. 1. "PCIE_CAP_REG,Capability Version. Indicates PCI-SIG defined PCI Express Capability structure version number. A version of the specification that changes the PCI Express Capability structure in a way that is not otherwise identifiable (for example through.." newline hexmask.long.byte 0x0 8.--15. 1. "PCIE_CAP_NEXT_PTR,Next Capability Pointer. This field contains the offset to the next PCI Capability structure or 00h if no other items exist in the linked list of Capabilities. Note: The access attributes of this field are as follows: - Wire: No access." hexmask.long.byte 0x0 0.--7. 1. "PCIE_CAP_ID,Capability ID. Indicates the PCI Express Capability structure. This field must return a Capability ID of 10h indicating that this is a PCI Express Capability structure." line.long 0x4 "DEVICE_CAPABILITIES_REG,Device Capabilities Register. The Device Capabilities register identifies PCI Express device function specific capabilities." hexmask.long.word 0x4 16.--31. 1. "RSVDP_16,Reserved for future use." bitfld.long 0x4 15. "PCIE_CAP_ROLE_BASED_ERR_REPORT,Role-Based Error Reporting. When set this bit indicates that the function implements the functionality originally defined in the Error Reporting ECN for PCI Express Base Specification Revision 1.0a and later incorporated.." "0,1" newline hexmask.long.word 0x4 6.--14. 1. "RSVDP_6,Reserved for future use." bitfld.long 0x4 5. "PCIE_CAP_EXT_TAG_SUPP,Extended Tag Field Supported. This bit in combination with the 10-Bit Tag Requester Supported bit in the Device Capabilities 2 register indicates the maximum supported size of the Tag field as a Requester. This bit must be set if.." "0,1" newline bitfld.long 0x4 3.--4. "PCIE_CAP_PHANTOM_FUNC_SUPPORT,Phantom Functions Supported. This field indicates the support for use of unclaimed function numbers to extend the number of outstanding transactions allowed by logically combining unclaimed function numbers (called Phantom.." "0,1,2,3" bitfld.long 0x4 0.--2. "PCIE_CAP_MAX_PAYLOAD_SIZE,Max_Payload_Size Supported. This field indicates the maximum payload size that the function can support for TLPs. Defined encodings are: - 000b: 128 bytes max payload size - 001b: 256 bytes max payload size - 010b: 512 bytes max.." "0,1,2,3,4,5,6,7" line.long 0x8 "DEVICE_CONTROL_DEVICE_STATUS,Device Control and Device Status Register. This register controls PCI Express device specific parameters and provides information about PCI Express device (function) specific parameters." hexmask.long.word 0x8 22.--31. 1. "RSVDP_22,Reserved for future use." rbitfld.long 0x8 21. "PCIE_CAP_TRANS_PENDING,Transactions Pending. Endpoints: When set this bit indicates that the function has issued Non-Posted Requests that have not been completed. A Function reports this bit cleared only when all outstanding Non-Posted Requests have.." "0,1" newline rbitfld.long 0x8 20. "PCIE_CAP_AUX_POWER_DETECTED,AUX Power Detected. Functions that require Aux power report this bit as set if Aux power is detected by the function. This bit is derived by sampling the sys_aux_pwr_det input." "0,1" bitfld.long 0x8 19. "PCIE_CAP_UNSUPPORTED_REQ_DETECTED,Unsupported Request Detected. This bit indicates that the function received an Unsupported Request. Errors are logged in this register regardless of whether error reporting is enabled or not in the Device Control.." "0,1" newline bitfld.long 0x8 18. "PCIE_CAP_FATAL_ERR_DETECTED,Fatal Error Detected. This bit indicates status of Fatal errors detected. Errors are logged in this register regardless of whether error reporting is enabled or not in the Device Control register. For a Multi-Function device.." "0,1" bitfld.long 0x8 17. "PCIE_CAP_NON_FATAL_ERR_DETECTED,Non-Fatal Error Detected. This bit indicates status of Non-fatal errors detected. Errors are logged in this register regardless of whether error reporting is enabled or not in the Device Control register. For a.." "0,1" newline bitfld.long 0x8 16. "PCIE_CAP_CORR_ERR_DETECTED,Correctable Error Detected. This bit indicates status of correctable errors detected. Errors are logged in this register regardless of whether error reporting is enabled or not in the Device Control register. For a.." "0,1" bitfld.long 0x8 15. "PCIE_CAP_INITIATE_FLR,Initiate Function Level Reset (applicable to Endpoints with Function Level Reset Capability set to 1b). A write of 1b initiates Function Level Reset to the Function. The value read by software from this bit is always 0b." "0,1" newline bitfld.long 0x8 12.--14. "PCIE_CAP_MAX_READ_REQ_SIZE,Max_Read_Request_Size. This field sets the maximum Read Request size for the function as a Requester. The function must not generate Read Requests with a size exceeding the set value. Defined encodings for this field are: -.." "0,1,2,3,4,5,6,7" rbitfld.long 0x8 11. "PCIE_CAP_EN_NO_SNOOP,Enable No Snoop. If this bit is set the function is permitted to Set the No Snoop bit in the Requester Attributes of transactions it initiates that do not require hardware enforced cache coherency (see section 2.2.6.5 in PCI Express.." "0,1" newline bitfld.long 0x8 10. "PCIE_CAP_AUX_POWER_PM_EN,Aux Power PM Enable. This bit is derived by sampling the sys_aux_pwr_det input. When set this bit enables a function to draw Aux power independent of PME Aux power. Functions that require Aux power on legacy operating systems.." "0,1" rbitfld.long 0x8 9. "PCIE_CAP_PHANTOM_FUNC_EN,Phantom Functions Enable. This bit in combination with the 10-Bit Tag Requester Enable bit in the Device Control 2 register determines how many Tag field bits a Requester is permitted to use. When the 10-Bit Tag Requester.." "0,1" newline rbitfld.long 0x8 8. "PCIE_CAP_EXT_TAG_EN,Extended Tag Field Enable. This bit in combination with the 10-Bit Tag Requester Enable bit in the Device Control 2 register determines how many Tag field bits a Requester is permitted to use. When the 10-Bit Tag Requester Enable.." "0,1" bitfld.long 0x8 5.--7. "PCIE_CAP_MAX_PAYLOAD_SIZE_CS,Max_Payload_Size. This field sets maximum TLP payload size for the Function. As a Receiver the Function must handle TLPs as large as the set value. As a Transmitter the Function must not generate TLPs exceeding the set.." "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 4. "PCIE_CAP_EN_REL_ORDER,Enable Relaxed Ordering. If this bit is set the function is permitted to set the Relaxed Ordering bit in the Attributes field of transactions it initiates that do not require strong write ordering (for more details see section.." "0,1" bitfld.long 0x8 3. "PCIE_CAP_UNSUPPORT_REQ_REP_EN,Unsupported Request Reporting Enable. This bit in conjunction with other bits controls the signaling of Unsupported Request Errors by sending error Messages (for more details see section 6.2.5 and section 6.2.6 of PCI.." "0,1" newline bitfld.long 0x8 2. "PCIE_CAP_FATAL_ERR_REPORT_EN,Fatal Error Reporting Enable. This bit in conjunction with other bits controls sending ERR_FATAL Messages (for more details see section 6.2.5 and section 6.2.6 of of PCI Express Base Specification). For a Multi-Function.." "0,1" bitfld.long 0x8 1. "PCIE_CAP_NON_FATAL_ERR_REPORT_EN,Non-Fatal Error Reporting Enable. This bit in conjunction with other bits controls sending ERR_NONFATAL Messages (for more details see section 6.2.5 and Section 6.2.6 of PCI Express Base Specification). For a.." "0,1" newline bitfld.long 0x8 0. "PCIE_CAP_CORR_ERR_REPORT_EN,Correctable Error Reporting Enable. This bit in conjunction with other bits controls sending ERR_COR Messages (for more details see section 6.2.5 section 6.2.6 and section 6.2.10.2 of PCI Express Base Specification). For.." "0,1" line.long 0xC "LINK_CAPABILITIES_REG,Link Capabilities Register. The Link Capabilities register identifies PCI Express Link specific capabilities." hexmask.long.byte 0xC 24.--31. 1. "PCIE_CAP_PORT_NUM,Port Number. This field indicates the PCI Express Port number for the given PCI Express Link. Multi-Function Devices associated with an Upstream Port must report the same value in this field for all functions. Note: The access.." rbitfld.long 0xC 23. "RSVDP_23,Reserved for future use." "0,1" newline bitfld.long 0xC 22. "PCIE_CAP_ASPM_OPT_COMPLIANCE,ASPM Optionality Compliance. This bit must be set to 1b in all functions. Components implemented against certain earlier versions of this specification will have this bit set to 0b. Software is permitted to use the value of.." "0,1" bitfld.long 0xC 21. "PCIE_CAP_LINK_BW_NOT_CAP,Link Bandwidth Notification Capability. A value of 1b indicates support for the Link Bandwidth Notification status and interrupt mechanisms. This capability is required for all Root Ports and Switch Downstream Ports supporting.." "0,1" newline rbitfld.long 0xC 20. "PCIE_CAP_DLL_ACTIVE_REP_CAP,Data Link Layer Link Active Reporting Capable. For a Downstream Port the controller hardwires this bit to 1b if the component supports the optional capability of reporting the DL_Active state of the Data Link Control and.." "0,1" bitfld.long 0xC 19. "PCIE_CAP_SURPRISE_DOWN_ERR_REP_CAP,Surprise Down Error Reporting Capable. For a Downstream Port this bit must be set if the component supports the optional capability of detecting and reporting a Surprise Down error condition. For Upstream Ports and.." "0,1" newline rbitfld.long 0xC 18. "PCIE_CAP_CLOCK_POWER_MAN,Clock Power Management. For Upstream Ports a value of 1b in this bit indicates that the component tolerates the removal of any reference clock(s) via the 'clock request' (CLKREQ#) mechanism when the Link is in the L1 and L2/L3.." "0,1" bitfld.long 0xC 15.--17. "PCIE_CAP_L1_EXIT_LATENCY,L1 Exit Latency. This field indicates the L1 exit latency for the given PCI Express Link. The value reported indicates the length of time this Port requires to complete transition from ASPM L1 to L0. If ASPM L1 is not supported.." "0,1,2,3,4,5,6,7" newline bitfld.long 0xC 12.--14. "PCIE_CAP_L0S_EXIT_LATENCY,L0s Exit Latency. This field indicates the L0s exit latency for the given PCI Express Link. The value reported indicates the length of time this Port requires to complete transition from L0s to L0. If L0s is not supported the.." "0,1,2,3,4,5,6,7" bitfld.long 0xC 10.--11. "PCIE_CAP_ACTIVE_STATE_LINK_PM_SUPPORT,Active State Power Management (ASPM) Support. This field indicates the level of ASPM supported on the given PCI Express Link. For more details on ASPM support requirements see section 5.4.1 of PCI Express Base.." "0,1,2,3" newline hexmask.long.byte 0xC 4.--9. 1. "PCIE_CAP_MAX_LINK_WIDTH,Maximum Link Width. This field indicates the maximum Link width (xN - corresponding to N Lanes) implemented by the component. This value is permitted to exceed the number of Lanes routed to the slot (Downstream Port) adapter.." hexmask.long.byte 0xC 0.--3. 1. "PCIE_CAP_MAX_LINK_SPEED,Max Link Speed. This field indicates the maximum Link speed of the associated Port. The encoded value specifies a bit location in the Supported Link Speeds Vector (in the Link Capabilities 2 register) that corresponds to the.." line.long 0x10 "LINK_CONTROL_LINK_STATUS_REG,Link Control and Link Status Register. This register controls and provides information about PCI Express Link specific parameters." bitfld.long 0x10 31. "PCIE_CAP_LINK_AUTO_BW_STATUS,Link Autonomous Bandwidth Status. This bit is set by hardware to indicate that hardware has autonomously changed Link speed or width without the Port transitioning through DL_Down status for reasons other than to attempt to.." "0,1" bitfld.long 0x10 30. "PCIE_CAP_LINK_BW_MAN_STATUS,Link Bandwidth Management Status. This bit is set by hardware to indicate that either of the following has occurred without the Port transitioning through DL_Down status: - A Link retraining has completed following a write of.." "0,1" newline rbitfld.long 0x10 29. "PCIE_CAP_DLL_ACTIVE,Data Link Layer Link Active. This bit indicates the status of the Data Link Control and Management State Machine. It returns a 1b to indicate the DL_Active state 0b otherwise. This bit must be implemented if the Data Link Layer Link.." "0,1" bitfld.long 0x10 28. "PCIE_CAP_SLOT_CLK_CONFIG,Slot Clock Configuration. This bit indicates that the component uses the same physical reference clock that the platform provides on the connector. If the device uses an independent clock irrespective of the presence of a.." "0,1" newline rbitfld.long 0x10 27. "PCIE_CAP_LINK_TRAINING,Link Training. This read-only bit indicates that the Physical Layer LTSSM is in the Configuration or Recovery state or that 1b was written to the Retrain Link bit but Link training has not yet begun. Hardware clears this bit when.." "0,1" rbitfld.long 0x10 26. "RSVDP_26,Reserved for future use." "0,1" newline hexmask.long.byte 0x10 20.--25. 1. "PCIE_CAP_NEGO_LINK_WIDTH,Negotiated Link Width. This field indicates the negotiated width of the given PCI Express Link. Defined encodings are: -00 0001b: x1 -00 0010b: x2 -00 0100b: x4 -00 1000b: x8 -00 1100b: x12 -01 0000b: x16 -10 0000b: x32 All other.." hexmask.long.byte 0x10 16.--19. 1. "PCIE_CAP_LINK_SPEED,Current Link Speed. This field indicates the negotiated Link speed of the given PCI Express Link. The encoded value specifies a bit location in the Supported Link Speeds Vector (in the Link Capabilities 2 register) that corresponds to.." newline bitfld.long 0x10 14.--15. "PCIE_CAP_DRS_SIGNALING_CONTROL,DRS Signaling Control. Indicates the mechanism used to report reception of a DRS message. Must be implemented for Downstream Ports with the DRS Supported bit Set in the Link Capabilities 2 Register. Encodings are: - 00b:.." "0,1,2,3" rbitfld.long 0x10 12.--13. "RSVDP_12,Reserved for future use." "0,1,2,3" newline bitfld.long 0x10 11. "PCIE_CAP_LINK_AUTO_BW_INT_EN,Link Autonomous Bandwidth Management Interrupt Enable. When set this bit enables the generation of an interrupt to indicate that the Link Autonomous Bandwidth Status bit has been set. The write value is gated with the.." "0,1" bitfld.long 0x10 10. "PCIE_CAP_LINK_BW_MAN_INT_EN,Link Bandwidth Management Interrupt Enable. When set this bit enables the generation of an interrupt to indicate that the Link Bandwidth Management Status bit has been set. The write value is gated with the.." "0,1" newline bitfld.long 0x10 9. "PCIE_CAP_HW_AUTO_WIDTH_DISABLE,Hardware Autonomous Width Disable. When set this bit disables hardware from changing the Link width for reasons other than attempting to correct unreliable Link operation by reducing Link width. For a Multi-Function Device.." "0,1" bitfld.long 0x10 8. "PCIE_CAP_EN_CLK_POWER_MAN,Enable Clock Power Management. Applicable only for Upstream Ports and with form factors that support a 'Clock Request' (CLKREQ#) mechanism this bit operates as follows: - 0b: Clock power management is disabled and device must.." "0,1" newline bitfld.long 0x10 7. "PCIE_CAP_EXTENDED_SYNCH,Extended Synch. When set this bit forces the transmission of additional Ordered Sets when exiting the L0s state (see section 4.2.4.5 of PCI Express Base Specification) and when in the Recovery state (see section 4.2.6.4.1 of PCI.." "0,1" bitfld.long 0x10 6. "PCIE_CAP_COMMON_CLK_CONFIG,Common Clock Configuration. When set this bit indicates that this component and the component at the opposite end of this Link are operating with a distributed common reference clock. A value of 0b indicates that this.." "0,1" newline bitfld.long 0x10 5. "PCIE_CAP_RETRAIN_LINK,Retrain Link. A write of 1b to this bit initiates Link retraining by directing the Physical Layer LTSSM to the Recovery state. If the LTSSM is already in Recovery or Configuration re-entering Recovery is permitted but not required." "0,1" bitfld.long 0x10 4. "PCIE_CAP_LINK_DISABLE,Link Disable. This bit disables the Link by directing the LTSSM to the Disabled state when set; this bit is Reserved on Endpoints PCI Express to PCI/PCI-X bridges and Upstream Ports of Switches. Writes to this bit are immediately.." "0,1" newline bitfld.long 0x10 3. "PCIE_CAP_RCB,Read Completion Boundary (RCB). Root Ports: Indicates the RCB value for the Root Port. Refer to section 2.3.1.1 of PCI Express Base Specification for the definition of the parameter RCB. Defined encodings are: - 0b: 64 byte - 1b: 128 byte.." "0,1" rbitfld.long 0x10 2. "RSVDP_2,Reserved for future use." "0,1" newline bitfld.long 0x10 0.--1. "PCIE_CAP_ACTIVE_STATE_LINK_PM_CONTROL,Active State Power Management (ASPM) Control. This field controls the level of ASPM enabled on the given PCI Express Link. See section 5.4.1.3 of PCI Express Base Specification for requirements on when and how to.." "0,1,2,3" line.long 0x14 "SLOT_CAPABILITIES_REG,Slot Capabilities Register. The Slot Capabilities register identifies PCI Express slot specific capabilities." hexmask.long.word 0x14 19.--31. 1. "PCIE_CAP_PHY_SLOT_NUM,Physical Slot Number. This field indicates the physical slot number attached to this Port. This field must be hardware initialized to a value that assigns a slot number that is unique within the chassis regardless of the form.." bitfld.long 0x14 18. "PCIE_CAP_NO_CMD_CPL_SUPPORT,No Command Completed Support. When set this bit indicates that this slot does not generate software notification when an issued command is completed by the Hot-Plug Controller. This bit is only permitted to be set if the.." "0,1" newline bitfld.long 0x14 17. "PCIE_CAP_ELECTROMECH_INTERLOCK,Electromechanical Interlock Present. When set this bit indicates that an Electromechanical Interlock is implemented on the chassis for this slot. Note: The access attributes of this field are as follows: - Wire: No access." "0,1" bitfld.long 0x14 15.--16. "PCIE_CAP_SLOT_POWER_LIMIT_SCALE,Slot Power Limit Scale. Specifies the scale used for the Slot Power Limit Value (for more details see Section 6.9 of PCI Express Base Specification). Range of Values: - 00b: 1.0x - 01b: 0.1x - 10b: 0.01x - 11b: 0.001x.." "0,1,2,3" newline hexmask.long.byte 0x14 7.--14. 1. "PCIE_CAP_SLOT_POWER_LIMIT_VALUE,Slot Power Limit Value. In combination with the Slot Power Limit Scale value specifies the upper limit on power supplied by the slot (for more detais see Section 6.9 of PCI Express Base Specification) or by other means.." bitfld.long 0x14 6. "PCIE_CAP_HOT_PLUG_CAPABLE,Hot-Plug Capable. When set this bit indicates that this slot is capable of supporting hot-plug operations. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then R/W else R" "0,1" newline bitfld.long 0x14 5. "PCIE_CAP_HOT_PLUG_SURPRISE,Hot-Plug Surprise. When set this bit indicates that an adapter present in this slot might be removed from the system without any prior notification. This is a form factor specific capability. This bit is an indication to the.." "0,1" bitfld.long 0x14 4. "PCIE_CAP_POWER_INDICATOR,Power Indicator Present. When set this bit indicates that a Power Indicator is electrically controlled by the chassis for this slot. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if.." "0,1" newline bitfld.long 0x14 3. "PCIE_CAP_ATTENTION_INDICATOR,Attention Indicator Present. When set this bit indicates that an Attention Indicator is electrically controlled by the chassis. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if.." "0,1" bitfld.long 0x14 2. "PCIE_CAP_MRL_SENSOR,MRL Sensor Present. When set this bit indicates that an MRL Sensor is implemented on the chassis for this slot. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then R/W else R" "0,1" newline bitfld.long 0x14 1. "PCIE_CAP_POWER_CONTROLLER,Power Controller Present. When set this bit indicates that a software programmable Power Controller is implemented for this slot/adapter (depending on form factor). Note: The access attributes of this field are as follows: -.." "0,1" bitfld.long 0x14 0. "PCIE_CAP_ATTENTION_INDICATOR_BUTTON,Attention Button Present. When set this bit indicates that an Attention Button for this slot is electrically controlled by the chassis. Note: The access attributes of this field are as follows: - Wire: No access. -.." "0,1" line.long 0x18 "SLOT_CONTROL_SLOT_STATUS,Slot Control and Status Register. This register controls and provides information about PCI Express Slot specific parameters." hexmask.long.byte 0x18 25.--31. 1. "RSVDP_25,Reserved for future use." bitfld.long 0x18 24. "PCIE_CAP_DLL_STATE_CHANGED,Data Link Layer State Changed. This bit is set when the value reported in the Data Link Layer Link Active bit of the Link Status register is changed. In response to a Data Link Layer State Changed event software must read the.." "0,1" newline rbitfld.long 0x18 23. "PCIE_CAP_ELECTROMECH_INTERLOCK_STATUS,Electromechanical Interlock Status. If an Electromechanical Interlock is implemented this bit indicates the status of the Electromechanical Interlock. Defined encodings are: - 0b: Electromechanical Interlock.." "0,1" rbitfld.long 0x18 22. "PCIE_CAP_PRESENCE_DETECT_STATE,Presence Detect State. This bit indicates the presence of an adapter in the slot reflected by the logical 'OR' of the Physical Layer in-band presence detect mechanism and if present any out-of-band presence detect.." "0,1" newline rbitfld.long 0x18 21. "PCIE_CAP_MRL_SENSOR_STATE,MRL Sensor State. This bit reports the status of the MRL sensor if implemented. Defined encodings are: - 0b: MRL Closed - 1b: MRL Open" "0,1" bitfld.long 0x18 20. "PCIE_CAP_CMD_CPLD,Command Completed. If Command Completed notification is supported (if the No Command Completed Support bit in the Slot Capabilities register is 0b) this bit is set when a hot-plug command has completed and the Hot-Plug Controller is.." "0,1" newline bitfld.long 0x18 19. "PCIE_CAP_PRESENCE_DETECTED_CHANGED,Presence Detect Changed. This bit is set when the value reported in the Presence Detect State bit is changed." "0,1" bitfld.long 0x18 18. "PCIE_CAP_MRL_SENSOR_CHANGED,MRL Sensor Changed. If an MRL sensor is implemented this bit is set when a MRL Sensor state change is detected. If an MRL sensor is not implemented this bit must not be set." "0,1" newline bitfld.long 0x18 17. "PCIE_CAP_POWER_FAULT_DETECTED,Power Fault Detected. If a Power Controller that supports power fault detection is implemented this bit issSet when the Power Controller detects a power fault at this slot. Note: Depending on hardware capability it is.." "0,1" bitfld.long 0x18 16. "PCIE_CAP_ATTENTION_BUTTON_PRESSED,Attention Button Pressed. If an Attention Button is implemented this bit is set when the attention button is pressed. If an Attention Button is not supported this bit must not be set." "0,1" newline rbitfld.long 0x18 14.--15. "RSVDP_14,Reserved for future use." "0,1,2,3" bitfld.long 0x18 12. "PCIE_CAP_DLL_STATE_CHANGED_EN,Data Link Layer State Changed Enable. If the Data Link Layer Link Active Reporting capability is 1b this bit enables software notification when Data Link Layer Link Active bit is changed. If the Data Link Layer Link Active.." "0,1" newline bitfld.long 0x18 11. "PCIE_CAP_ELECTROMECH_INTERLOCK_CTRL,Electromechanical Interlock Control. If an Electromechanical Interlock is implemented a write of 1b to this bit causes the state of the interlock to toggle. A write of 0b to this bit has no effect. A read of this bit.." "0,1" bitfld.long 0x18 10. "PCIE_CAP_POWER_CONTROLLER_CTRL,Power Controller Control. If a Power Controller is implemented this bit when written sets the power state of the slot per the defined encodings. Reads of this bit must reflect the value from the latest write even if the.." "0,1" newline bitfld.long 0x18 8.--9. "PCIE_CAP_POWER_INDICATOR_CTRL,Power Indicator Control. If a Power Indicator is implemented writes to this field set the Power Indicator to the written state. Reads of this field must reflect the value from the latest write even if the corresponding.." "0,1,2,3" bitfld.long 0x18 6.--7. "PCIE_CAP_ATTENTION_INDICATOR_CTRL,Attention Indicator Control. If an Attention Indicator is implemented writes to this field set the Attention Indicator to the written state. Reads of this field must reflect the value from the latest write even if the.." "0,1,2,3" newline bitfld.long 0x18 5. "PCIE_CAP_HOT_PLUG_INT_EN,Hot-Plug Interrupt Enable. When set this bit enables generation of an interrupt on enabled hot-plug events. If the Hot Plug Capable bit in the Slot Capabilities register is clear this bit is permitted to be read-only with a.." "0,1" bitfld.long 0x18 4. "PCIE_CAP_CMD_CPL_INT_EN,Command Completed Interrupt Enable. If Command Completed notification is supported (if the No Command Completed Support bit in the Slot Capabilities register is 0b) when set this bit enables software notification when a hot-plug.." "0,1" newline bitfld.long 0x18 3. "PCIE_CAP_PRESENCE_DETECT_CHANGE_EN,Presence Detect Changed Enable. When set this bit enables software notification on a presence detect changed event (for more details see Section 6.7.3 of PCI Express Base Specification). If the Hot-Plug Capable bit in.." "0,1" bitfld.long 0x18 2. "PCIE_CAP_MRL_SENSOR_CHANGED_EN,MRL Sensor Changed Enable. When set this bit enables software notification on a MRL sensor changed event (for more details see Section 6.7.3 of PCI Express Base Specification). If the MRL Sensor Present bit in the Slot.." "0,1" newline bitfld.long 0x18 1. "PCIE_CAP_POWER_FAULT_DETECTED_EN,Power Fault Detected Enable. When set this bit enables software notification on a power fault event (for more details see Section 6.7.3 of PCI Express Base Specification). If a Power Controller that supports power fault.." "0,1" bitfld.long 0x18 0. "PCIE_CAP_ATTENTION_BUTTON_PRESSED_EN,Attention Button Pressed Enable. When set to 1b this bit enables software notification on an attention button pressed event (for more details see Section 6.7.3 of PCI Express Base Specification). If the Attention.." "0,1" line.long 0x1C "ROOT_CONTROL_ROOT_CAPABILITIES_REG,Root Control and Capabilities Register. This register controls PCI Express Root Complex specific parameters and identifies PCI Express Root Port specific capabilities." hexmask.long.word 0x1C 17.--31. 1. "RSVDP_17,Reserved for future use." bitfld.long 0x1C 16. "PCIE_CAP_CRS_SW_VISIBILITY,CRS Software Visibility Capable. For a description of this standard PCIe register field see the PCI Express Base Specification. CRS Software Visibility. When set this bit indicates that the Root Port is capable of returning.." "0,1" newline hexmask.long.word 0x1C 5.--15. 1. "RSVDP_5,Reserved for future use." bitfld.long 0x1C 4. "PCIE_CAP_CRS_SW_VISIBILITY_EN,CRS Software Visibility Enable. When set this bit enables the Root Port to return Configuration Request Retry Status (CRS) Completion Status to software (for more details see section 2.3.1 of PCI Express Base.." "0,1" newline bitfld.long 0x1C 3. "PCIE_CAP_PME_INT_EN,PME Interrupt Enable. When set this bit enables PME interrupt generation upon receipt of a PME Message as reflected in the PME Status bit (for more details see Table 7-29 of PCI Express Base Specification). A PME interrupt is also.." "0,1" bitfld.long 0x1C 2. "PCIE_CAP_SYS_ERR_ON_FATAL_ERR_EN,System Error on Fatal Error Enable. If set this bit indicates that a System Error should be generated if a Fatal error (ERR_FATAL) is reported by any of the devices in the Hierarchy Domain associated with this Root Port.." "0,1" newline bitfld.long 0x1C 1. "PCIE_CAP_SYS_ERR_ON_NON_FATAL_ERR_EN,System Error on Non-Fatal Error Enable. If set this bit indicates that a System Error should be generated if a Non-fatal error (ERR_NONFATAL) is reported by any of the devices in the Hierarchy Domain associated with.." "0,1" bitfld.long 0x1C 0. "PCIE_CAP_SYS_ERR_ON_CORR_ERR_EN,System Error on Correctable Error Enable. If set this bit indicates that a System Error should be generated if a correctable error (ERR_COR) is reported by any of the devices in the Hierarchy Domain associated with this.." "0,1" line.long 0x20 "ROOT_STATUS_REG,Root Status Register. The Root Status register provides information about PCI Express device specific parameters." hexmask.long.word 0x20 18.--31. 1. "RSVDP_18,Reserved for future use." rbitfld.long 0x20 17. "PCIE_CAP_PME_PENDING,PME Pending. This bit indicates that another PME is pending when the PME Status bit is s et. When the PME Status bit is cleared by software; the PME is delivered by hardware by setting the PME Status bit again and updating the PME.." "0,1" newline bitfld.long 0x20 16. "PCIE_CAP_PME_STATUS,PME Status. This bit indicates that PME was asserted by the PME Requester indicated in the PME Requester ID field. Subsequent PMEs are kept pending until the status register is cleared by software by writing a 1b." "0,1" hexmask.long.word 0x20 0.--15. 1. "PCIE_CAP_PME_REQ_ID,PME Requester ID. This field indicates the PCI Requester ID of the last PME Requester. This field is only valid when the PME Status bit is set." line.long 0x24 "DEVICE_CAPABILITIES2_REG,Device Capabilities 2 Register." bitfld.long 0x24 31. "PCIE_CAP_FRS_SUPPORTED,FRS Supported. When set indicates support for the optional Function Readiness Status (FRS) capability. Must be set for all Functions that support generation or reception capabilities of FRS Messages. Must not be set by Switch.." "0,1" hexmask.long.byte 0x24 24.--30. 1. "RSVDP_24,Reserved for future use." newline bitfld.long 0x24 22.--23. "PCIE_CAP2_CFG_MAX_END2END_TLP_PRFXS,Max End-End TLP Prefixes. Indicates the maximum number of End-End TLP Prefixes supported by this Function. For more details see Section 2.2.10.2 of PCI Express Base Specification. Values are: - 01b: 1 End-End TLP.." "0,1,2,3" bitfld.long 0x24 21. "PCIE_CAP2_CFG_END2END_TLP_PRFX_SUPPORT,End-End TLP Prefix Supported. Indicates whether End-End TLP Prefix support is offered by a Function. Values are: - 0b: No Support - 1b: Support is provided to receive TLPs containing End-End TLP Prefixes. All Ports.." "0,1" newline bitfld.long 0x24 20. "PCIE_CAP2_CFG_EXTND_FMT_SUPPORT,Extended Fmt Field Supported. If set the Function supports the 3-bit definition of the Fmt field. If clear the Function supports a 2-bit definition of the Fmt field. For more details see section 2.2 of PCI Express Base.." "0,1" rbitfld.long 0x24 17. "PCIE_CAP2_10_BIT_TAG_REQ_SUPPORT,10-Bit Tag Requester Supported. If this bit is set the Function supports 10-Bit Tag Requester capability; otherwise the Function does not. This bit must not be set if the 10-Bit Tag Completer Supported bit is clear." "0,1" newline rbitfld.long 0x24 16. "PCIE_CAP2_10_BIT_TAG_COMP_SUPPORT,10-Bit Tag Completer Supported. If this bit is set the Function supports 10-Bit Tag Completer capability; otherwise the Function does not. For more details see section 2.2.6.2. of PCI Express Base Specification." "0,1" rbitfld.long 0x24 13. "PCIE_CAP_TPH_CMPLT_SUPPORT_1,TPH Completer Supported Bit 1." "0,1" newline rbitfld.long 0x24 12. "PCIE_CAP_TPH_CMPLT_SUPPORT_0,TPH Completer Supported Bit 0. Value of this bit along with TPH Completer Supported Bit 1 indicates Completer support for TPH or Extended TPH. Applicable only to Root Ports and Endpoints. For all other Functions this field.." "0,1" bitfld.long 0x24 11. "PCIE_CAP_LTR_SUPP,LTR Mechanism Supported. A value of 1b indicates support for the optional Latency Tolerance Reporting (LTR) mechanism. Root Ports Switches and Endpoints are permitted to implement this capability. For a Multi-Function Device associated.." "0,1" newline rbitfld.long 0x24 10. "PCIE_CAP_NO_RO_EN_PR2PR_PAR,No RO-enabled PR-PR Passing. If this bit is set the routing element never carries out the passing permitted by Table 2-39 of PCI Express Base Specification entry A2b that is associated with the Relaxed Ordering Attribute.." "0,1" rbitfld.long 0x24 9. "PCIE_CAP_128_CAS_CPL_SUPP,128-bit CAS Completer Supported. Applicable to Functions with Memory Space BARs as well as all Root Ports; must be 0b otherwise. This bit must be set to 1b if the Function supports this optional capability. For more details see.." "0,1" newline rbitfld.long 0x24 8. "PCIE_CAP_64_ATOMIC_CPL_SUPP,64-bit AtomicOp Completer Supported. Applicable to Functions with Memory Space BARs as well as all Root Ports; must be 0b otherwise. Includes FetchAdd Swap and CAS AtomicOps. This bit must be set to 1b if the Function.." "0,1" rbitfld.long 0x24 7. "PCIE_CAP_32_ATOMIC_CPL_SUPP,32-bit AtomicOp Completer Supported. Applicable to Functions with Memory Space BARs as well as all Root Ports; must be 0b otherwise. Includes FetchAdd Swap and CAS AtomicOps. This bit must be set to 1b if the Function.." "0,1" newline rbitfld.long 0x24 6. "PCIE_CAP_ATOMIC_ROUTING_SUPP,AtomicOp Routing Supported. Applicable only to Switch Upstream Ports Switch Downstream Ports and Root Ports; must be 0b for other Function types. This bit must be set to 1b if the Port supports this optional capability. For.." "0,1" rbitfld.long 0x24 5. "PCIE_CAP_ARI_FORWARD_SUPPORT,ARI Forwarding Supported. Applicable only to Switch Downstream Ports and Root Ports; must be 0b for other Function types. This bit must be set to 1b if a Switch Downstream Port or Root Port supports this optional capability." "0,1" newline rbitfld.long 0x24 4. "PCIE_CAP_CPL_TIMEOUT_DISABLE_SUPPORT,Completion Timeout Disable Supported. A value of 1b indicates support for the Completion Timeout Disable mechanism. The Completion Timeout Disable mechanism is required for Endpoints that issue Requests on their own.." "0,1" hexmask.long.byte 0x24 0.--3. 1. "PCIE_CAP_CPL_TIMEOUT_RANGE,Completion Timeout Ranges Supported. This field indicates device Function support for the optional Completion Timeout programmability mechanism. This mechanism allows system software to modify the Completion Timeout value. This.." line.long 0x28 "DEVICE_CONTROL2_DEVICE_STATUS2_REG,Device Control 2 and Status 2 Register." hexmask.long.word 0x28 16.--31. 1. "RSVDP_16,Reserved for future use." bitfld.long 0x28 15. "PCIE_CTRL2_CFG_END2END_TLP_PFX_BLCK,End-End TLP Prefix Blocking. Controls whether the routing function is permitted to forward TLPs containing an End-End TLP Prefix. Values are: - 0b: Forwarding Enabled - Function is permitted to send TLPs with End-End.." "0,1" newline rbitfld.long 0x28 11. "RSVDP_11,Reserved for future use." "0,1" bitfld.long 0x28 10. "PCIE_CAP_LTR_EN,LTR Mechanism Enable. When set to 1b this bit enables Upstream Ports to send LTR messages and Downstream Ports to process LTR Messages. For a Multi-Function Device associated with an Upstream Port of a device that implements LTR the bit.." "0,1" newline rbitfld.long 0x28 5. "PCIE_CAP_ARI_FORWARD_SUPPORT_CS,ARI Forwarding Enable. When set the Downstream Port disables its traditional Device Number field being 0 enforcement when turning a Type 1 Configuration Request into a Type 0 Configuration Request permitting access to.." "0,1" bitfld.long 0x28 4. "PCIE_CAP_CPL_TIMEOUT_DISABLE,Completion Timeout Disable. When set this bit disables the Completion Timeout mechanism. This bit is required for all Functions that support the Completion Timeout Disable Capability. Functions that do not support this.." "0,1" newline hexmask.long.byte 0x28 0.--3. 1. "PCIE_CAP_CPL_TIMEOUT_VALUE,Completion Timeout Value. In device Functions that support Completion Timeout programmability this field allows system software to modify the Completion Timeout value. This field is applicable to Root Ports Endpoints that.." line.long 0x2C "LINK_CAPABILITIES2_REG,Link Capabilities 2 Register." bitfld.long 0x2C 31. "DRS_SUPPORTED,DRS Supported. When set indicates support for the optional Device Readiness Status (DRS) capability. Must be Set in Downstream Ports that support DRS. Must be Set in Downstream Ports that support FRS. For Upstream Ports that support DRS.." "0,1" hexmask.long.byte 0x2C 25.--30. 1. "RSVDP_25,Reserved for future use." newline hexmask.long.word 0x2C 9.--22. 1. "RSVDP_9,Reserved for future use." rbitfld.long 0x2C 8. "PCIE_CAP_CROSS_LINK_SUPPORT,Crosslink Supported. When set to 1b this bit indicates that the associated Port supports crosslinks (for more details see section 4.2.6.3.1 of PCI Express Base Specification). When set to 0b on a Port that supports Link.." "0,1" newline hexmask.long.byte 0x2C 1.--7. 1. "PCIE_CAP_SUPPORT_LINK_SPEED_VECTOR,Supported Link Speeds Vector. This field indicates the supported Link speed(s) of the associated Port. For each bit a value of 1b indicates that the corresponding Link speed is supported; otherwise the Link speed is.." rbitfld.long 0x2C 0. "RSVDP_0,Reserved for future use." "0,1" line.long 0x30 "LINK_CONTROL2_LINK_STATUS2_REG,Link Control 2 and Status 2 Register." bitfld.long 0x30 31. "DRS_MESSAGE_RECEIVED,DRS Message Received. This bit must be set whenever the Port receives a DRS Message. This bit must be cleared in DL_Down. This bit must be implemented in any Downstream Port where the DRS Supported bit is Set in the Link Capabilities.." "0,1" rbitfld.long 0x30 28.--30. "DOWNSTREAM_COMPO_PRESENCE,Downstream Component Presence. This field indicates the presence and DRS status for the Downstream Component if any connected to the Link; defined values are: - 000b: Link Down - Presence Not Determined - 001b: Link Down -.." "0,1,2,3,4,5,6,7" newline rbitfld.long 0x30 26.--27. "RSVDP_26,Reserved for future use." "0,1,2,3" bitfld.long 0x30 21. "PCIE_CAP_LINK_EQ_REQ,Link Equalization Request 8.0 GT/s. This bit is set by hardware to request the 8.0 GT/s Link equalization process to be performed on the Link. For more details see sections 4.2.3 and 4.2.6.4.2 of PCI Express Base Specification. For.." "0,1" newline rbitfld.long 0x30 20. "PCIE_CAP_EQ_CPL_P3,EEqualization 8.0 GT/s Phase 3 Successful. When set to 1b this bit indicates that Phase 3 of the 8.0 GT/s Transmitter Equalization procedure has successfully completed. Details of the Transmitter Equalization process and when this bit.." "0,1" rbitfld.long 0x30 19. "PCIE_CAP_EQ_CPL_P2,Equalization 8.0 GT/s Phase 2 Successful. When set to 1b this bit indicates that Phase 2 of the 8.0 GT/s Transmitter Equalization procedure has successfully completed. Details of the Transmitter Equalization process and when this bit.." "0,1" newline rbitfld.long 0x30 18. "PCIE_CAP_EQ_CPL_P1,Equalization 8.0 GT/s Phase 1 Successful. When set to 1b this bit indicates that Phase 1 of the 8.0 GT/s Transmitter Equalization procedure has successfully completed. Details of the Transmitter Equalization process and when this bit.." "0,1" rbitfld.long 0x30 17. "PCIE_CAP_EQ_CPL,Equalization 8.0 GT/s Complete. When set to 1b this bit indicates that the Transmitter Equalization procedure at the 8.0 GT/s data rate has completed. Details of the Transmitter Equalization process and when this bit needs to be set to.." "0,1" newline rbitfld.long 0x30 16. "PCIE_CAP_CURR_DEEMPHASIS,Current De-emphasis Level. When the Link is operating at 5.0 GT/s speed this bit reflects the level of de-emphasis. Encodings: - 1b: -3.5 dB - 0b: -6 dB The value in this bit is undefined when the Link is not operating at 5.0.." "0,1" hexmask.long.byte 0x30 12.--15. 1. "PCIE_CAP_COMPLIANCE_PRESET,Compliance Preset/De-emphasis. For 8.0 GT/s and higher Data Rate: This field sets the Transmitter Preset in Polling.Compliance state if the entry occurred due to the Enter Compliance bit being 1b. The encodings are defined in.." newline bitfld.long 0x30 11. "PCIE_CAP_COMPLIANCE_SOS,Compliance SOS. When set to 1b the LTSSM is required to send SKP Ordered Sets between sequences when sending the Compliance Pattern or Modified Compliance Pattern. For a Multi-Function Device associated with an Upstream Port the.." "0,1" bitfld.long 0x30 10. "PCIE_CAP_ENTER_MODIFIED_COMPLIANCE,Enter Modified Compliance. When this bit is set to 1b the device transmits Modified Compliance Pattern if the LTSSM enters Polling.Compliance substate. Components that support only the 2.5 GT/s speed are permitted to.." "0,1" newline bitfld.long 0x30 7.--9. "PCIE_CAP_TX_MARGIN,Transmit Margin - This field controls the value of the non-deemphasized voltage level at the Transmitter pins. This field is reset to 000b on entry to the LTSSM Polling.Configuration substate (see Chapter 4 of PCI Express Base.." "0,1,2,3,4,5,6,7" bitfld.long 0x30 6. "PCIE_CAP_SEL_DEEMPHASIS,Selectable De-emphasis. When the Link is operating at 5.0 GT/s speed this bit is used to control the transmit de-emphasis of the link in specific situations. For more details see section 4.2.6 of PCI Express Base Specification." "0,1" newline bitfld.long 0x30 5. "PCIE_CAP_HW_AUTO_SPEED_DISABLE,Hardware Autonomous Speed Disable. When set this bit disables hardware from changing the Link speed for device-specific reasons other than attempting to correct unreliable Link operation by reducing Link speed. Initial.." "0,1" bitfld.long 0x30 4. "PCIE_CAP_ENTER_COMPLIANCE,Enter Compliance. Software is permitted to force a Link to enter Compliance mode (at the speed indicated in the Target Link Speed field and the de-emphasis/preset level indicated by the Compliance Preset/De-emphasis field) by.." "0,1" newline hexmask.long.byte 0x30 0.--3. 1. "PCIE_CAP_TARGET_LINK_SPEED,Target Link Speed. For Downstream Ports this field sets an upper limit on Link operational speed by restricting the values advertised by the Upstream component in its training sequences. The encoded value specifies a bit.." tree.end tree "PF0_AER_CAP (PF Advanced Error Reporting Capability Structure)" group.long (0x0+0x100)++0x1B line.long 0x0 "AER_EXT_CAP_HDR_OFF,Advanced Error Reporting Extended Capability Header. For a description of this standard PCIe register. see the PCI Express Specification." hexmask.long.word 0x0 20.--31. 1. "NEXT_OFFSET,Next Capability Offset. For a description of this standard PCIe register field see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky).." hexmask.long.byte 0x0 16.--19. 1. "CAP_VERSION,Capability Version. For a description of this standard PCIe register field see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else.." hexmask.long.word 0x0 0.--15. 1. "CAP_ID,AER Extended Capability ID. For a description of this standard PCIe register field see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else.." line.long 0x4 "UNCORR_ERR_STATUS_OFF,Uncorrectable Error Status Register. For a description of this standard PCIe register. see the PCI Express Specification." hexmask.long.byte 0x4 27.--31. 1. "RSVDP_27,Reserved for future use." bitfld.long 0x4 25. "TLP_PRFX_BLOCKED_ERR_STATUS,TLP Prefix Blocked Error Status. For a description of this standard PCIe register field see the PCI Express Specification. Note: Not supported." "0,1" rbitfld.long 0x4 23. "RSVDP_23,Reserved for future use." "0,1" newline bitfld.long 0x4 22. "INTERNAL_ERR_STATUS,Uncorrectable Internal Error Status. For a description of this standard PCIe register field see the PCI Express Specification. The controller sets this bit when your application asserts app_err_bus[9]. It does not set this bit when.." "0,1" bitfld.long 0x4 20. "UNSUPPORTED_REQ_ERR_STATUS,Unsupported Request Error Status. For a description of this standard PCIe register field see the PCI Express Specification." "0,1" bitfld.long 0x4 19. "ECRC_ERR_STATUS,ECRC Error Status. For a description of this standard PCIe register field see the PCI Express Specification. Note:If CX_ECRC_ENABLE=0 the register field always reads 0." "0,1" newline bitfld.long 0x4 18. "MALF_TLP_ERR_STATUS,Malformed TLP Status. For a description of this standard PCIe register field see the PCI Express Specification." "0,1" bitfld.long 0x4 17. "REC_OVERFLOW_ERR_STATUS,Receiver Overflow Status. For a description of this standard PCIe register field see the PCI Express Specification." "0,1" bitfld.long 0x4 16. "UNEXP_CMPLT_ERR_STATUS,Unexpected Completion Status. For a description of this standard PCIe register field see the PCI Express Specification." "0,1" newline bitfld.long 0x4 15. "CMPLT_ABORT_ERR_STATUS,Completer Abort Status. For a description of this standard PCIe register field see the PCI Express Specification." "0,1" bitfld.long 0x4 14. "CMPLT_TIMEOUT_ERR_STATUS,Completion Timeout Status. For a description of this standard PCIe register field see the PCI Express Specification." "0,1" bitfld.long 0x4 13. "FC_PROTOCOL_ERR_STATUS,Flow Control Protocol Error Status. For a description of this standard PCIe register field see the PCI Express Specification." "0,1" newline bitfld.long 0x4 12. "POIS_TLP_ERR_STATUS,Poisoned TLP Status. For a description of this standard PCIe register field see the PCI Express Specification." "0,1" hexmask.long.byte 0x4 6.--11. 1. "RSVDP_6,Reserved for future use." bitfld.long 0x4 5. "SURPRISE_DOWN_ERR_STATUS,Surprise Down Error Status (Optional). For a description of this standard PCIe register field see the PCI Express Specification." "0,1" newline bitfld.long 0x4 4. "DL_PROTOCOL_ERR_STATUS,Data Link Protocol Error Status. For a description of this standard PCIe register field see the PCI Express Specification." "0,1" hexmask.long.byte 0x4 0.--3. 1. "RSVDP_0,Reserved for future use." line.long 0x8 "UNCORR_ERR_MASK_OFF,Uncorrectable Error Mask Register. For a description of this standard PCIe register. see the PCI Express Specification." hexmask.long.byte 0x8 27.--31. 1. "RSVDP_27,Reserved for future use." bitfld.long 0x8 25. "TLP_PRFX_BLOCKED_ERR_MASK,TLP Prefix Blocked Error Mask. For a description of this standard PCIe register field see the PCI Express Specification. Note: Not supported. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi:.." "0,1" rbitfld.long 0x8 23. "RSVDP_23,Reserved for future use." "0,1" newline bitfld.long 0x8 22. "INTERNAL_ERR_MASK,Uncorrectable Internal Error Mask (Optional). For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." "0,1" rbitfld.long 0x8 21. "ACS_VIOLATION_MASK,ACS Violation Mask. Setting the ACS Violation Mask bit disables error logging and signaling for ACS Violation errors. The bit is Read-Only Zero for upstream ports when ACS P2P Egress Control Enable is not set. For a description of.." "0,1" bitfld.long 0x8 20. "UNSUPPORTED_REQ_ERR_MASK,Unsupported Request Error Mask. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." "0,1" newline bitfld.long 0x8 19. "ECRC_ERR_MASK,ECRC Error Mask (Optional). For a description of this standard PCIe register field see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W (sticky) Note: This register.." "0,1" bitfld.long 0x8 18. "MALF_TLP_ERR_MASK,Malformed TLP Mask. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." "0,1" bitfld.long 0x8 17. "REC_OVERFLOW_ERR_MASK,Receiver Overflow Mask (Optional). For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." "0,1" newline bitfld.long 0x8 16. "UNEXP_CMPLT_ERR_MASK,Unexpected Completion Mask. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." "0,1" bitfld.long 0x8 15. "CMPLT_ABORT_ERR_MASK,Completer Abort Error Mask (Optional). For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." "0,1" bitfld.long 0x8 14. "CMPLT_TIMEOUT_ERR_MASK,Completion Timeout Error Mask. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." "0,1" newline bitfld.long 0x8 13. "FC_PROTOCOL_ERR_MASK,Flow Control Protocol Error Mask. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." "0,1" bitfld.long 0x8 12. "POIS_TLP_ERR_MASK,Poisoned TLP Error Mask. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." "0,1" hexmask.long.byte 0x8 6.--11. 1. "RSVDP_6,Reserved for future use." newline rbitfld.long 0x8 5. "SURPRISE_DOWN_ERR_MASK,Surprise Down Error Mask. For a description of this standard PCIe register field see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi:.." "0,1" bitfld.long 0x8 4. "DL_PROTOCOL_ERR_MASK,Data Link Protocol Error Mask. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." "0,1" hexmask.long.byte 0x8 0.--3. 1. "RSVDP_0,Reserved for future use." line.long 0xC "UNCORR_ERR_SEV_OFF,Uncorrectable Error Severity Register. For a description of this standard PCIe register. see the PCI Express Specification." hexmask.long.byte 0xC 27.--31. 1. "RSVDP_27,Reserved for future use." bitfld.long 0xC 25. "TLP_PRFX_BLOCKED_ERR_SEVERITY,TLP Prefix Blocked Error Severity (Optional). For a description of this standard PCIe register field see the PCI Express Specification. Note: Not supported. Note: The access attributes of this field are as follows: - Wire:.." "0,1" rbitfld.long 0xC 24. "ATOMIC_EGRESS_BLOCKED_ERR_SEVERITY,AtomicOp Egress Blocked Severity (Optional). For a description of this standard PCIe register field see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi:.." "0,1" newline rbitfld.long 0xC 23. "RSVDP_23,Reserved for future use." "0,1" bitfld.long 0xC 22. "INTERNAL_ERR_SEVERITY,Uncorrectable Internal Error Severity (Optional). For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." "0,1" bitfld.long 0xC 20. "UNSUPPORTED_REQ_ERR_SEVERITY,Unsupported Request Error Severity. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." "0,1" newline bitfld.long 0xC 19. "ECRC_ERR_SEVERITY,ECRC Error Severity (Optional). For a description of this standard PCIe register field see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W (sticky) Note: This.." "0,1" bitfld.long 0xC 18. "MALF_TLP_ERR_SEVERITY,Malformed TLP Severity. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." "0,1" bitfld.long 0xC 17. "REC_OVERFLOW_ERR_SEVERITY,Receiver Overflow Error Severity (Optional). For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." "0,1" newline bitfld.long 0xC 16. "UNEXP_CMPLT_ERR_SEVERITY,Unexpected Completion Error Severity. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." "0,1" bitfld.long 0xC 15. "CMPLT_ABORT_ERR_SEVERITY,Completer Abort Error Severity (Optional). For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." "0,1" bitfld.long 0xC 14. "CMPLT_TIMEOUT_ERR_SEVERITY,Completion Timeout Error Severity. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." "0,1" newline bitfld.long 0xC 13. "FC_PROTOCOL_ERR_SEVERITY,Flow Control Protocol Error Severity (Optional). For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." "0,1" bitfld.long 0xC 12. "POIS_TLP_ERR_SEVERITY,Poisoned TLP Severity. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." "0,1" hexmask.long.byte 0xC 6.--11. 1. "RSVDP_6,Reserved for future use." newline rbitfld.long 0xC 5. "SURPRISE_DOWN_ERR_SVRITY,Surprise Down Error Severity (Optional). For a description of this standard PCIe register field see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi:.." "0,1" bitfld.long 0xC 4. "DL_PROTOCOL_ERR_SEVERITY,Data Link Protocol Error Severity. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." "0,1" hexmask.long.byte 0xC 0.--3. 1. "RSVDP_0,Reserved for future use." line.long 0x10 "CORR_ERR_STATUS_OFF,Correctable Error Status Register. For a description of this standard PCIe register. see the PCI Express Specification." hexmask.long.word 0x10 16.--31. 1. "RSVDP_16,Reserved for future use." bitfld.long 0x10 15. "HEADER_LOG_OVERFLOW_STATUS,Header Log Overflow Error Status (Optional). For a description of this standard PCIe register field see the PCI Express Specification." "0,1" bitfld.long 0x10 14. "CORRECTED_INT_ERR_STATUS,Corrected Internal Error Status (Optional). For a description of this standard PCIe register field see the PCI Express Specification." "0,1" newline bitfld.long 0x10 13. "ADVISORY_NON_FATAL_ERR_STATUS,Advisory Non-Fatal Error Status. For a description of this standard PCIe register field see the PCI Express Specification." "0,1" bitfld.long 0x10 12. "RPL_TIMER_TIMEOUT_STATUS,Replay Timer Timeout Status. For a description of this standard PCIe register field see the PCI Express Specification." "0,1" rbitfld.long 0x10 9.--11. "RSVDP_9,Reserved for future use." "0,1,2,3,4,5,6,7" newline bitfld.long 0x10 8. "REPLAY_NO_ROLEOVER_STATUS,REPLAY_NUM Rollover Status. For a description of this standard PCIe register field see the PCI Express Specification." "0,1" bitfld.long 0x10 7. "BAD_DLLP_STATUS,Bad DLLP Status. For a description of this standard PCIe register field see the PCI Express Specification." "0,1" bitfld.long 0x10 6. "BAD_TLP_STATUS,Bad TLP Status. For a description of this standard PCIe register field see the PCI Express Specification." "0,1" newline hexmask.long.byte 0x10 1.--5. 1. "RSVDP_1,Reserved for future use." bitfld.long 0x10 0. "RX_ERR_STATUS,Receiver Error Status (Optional). For a description of this standard PCIe register field see the PCI Express Specification." "0,1" line.long 0x14 "CORR_ERR_MASK_OFF,Correctable Error Mask Register. For a description of this standard PCIe register. see the PCI Express Specification." hexmask.long.word 0x14 16.--31. 1. "RSVDP_16,Reserved for future use." bitfld.long 0x14 15. "HEADER_LOG_OVERFLOW_MASK,Header Log Overflow Error Mask (Optional). For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." "0,1" bitfld.long 0x14 14. "CORRECTED_INT_ERR_MASK,Corrected Internal Error Mask (Optional). For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." "0,1" newline bitfld.long 0x14 13. "ADVISORY_NON_FATAL_ERR_MASK,Advisory Non-Fatal Error Mask. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." "0,1" bitfld.long 0x14 12. "RPL_TIMER_TIMEOUT_MASK,Replay Timer Timeout Mask. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." "0,1" rbitfld.long 0x14 9.--11. "RSVDP_9,Reserved for future use." "0,1,2,3,4,5,6,7" newline bitfld.long 0x14 8. "REPLAY_NO_ROLEOVER_MASK,REPLAY_NUM Rollover Mask. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." "0,1" bitfld.long 0x14 7. "BAD_DLLP_MASK,Bad DLLP Mask. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." "0,1" bitfld.long 0x14 6. "BAD_TLP_MASK,Bad TLP Mask. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." "0,1" newline hexmask.long.byte 0x14 1.--5. 1. "RSVDP_1,Reserved for future use." bitfld.long 0x14 0. "RX_ERR_MASK,Receiver Error Mask (Optional). For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." "0,1" line.long 0x18 "ADV_ERR_CAP_CTRL_OFF,Advanced Error Capabilities and Control Register. For a description of this standard PCIe register. see the PCI Express Specification." hexmask.long.tbyte 0x18 13.--31. 1. "RSVDP_13,Reserved for future use." rbitfld.long 0x18 12. "CTO_PRFX_HDR_LOG_CAP,TLP Prefix Log Present. For a description of this standard PCIe register field see the PCI Express Specification." "0,1" rbitfld.long 0x18 11. "TLP_PRFX_LOG_PRESENT,Completion Timeout Prefix/Header Log Capable. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." "0,1" newline rbitfld.long 0x18 10. "MULTIPLE_HEADER_EN,Multiple Header Recording Enable. For a description of this standard PCIe register field see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R (sticky) Note: This.." "0,1" rbitfld.long 0x18 9. "MULTIPLE_HEADER_CAP,Multiple Header Recording Capable. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." "0,1" bitfld.long 0x18 8. "ECRC_CHECK_EN,ECRC Check Enable. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." "0,1" newline rbitfld.long 0x18 7. "ECRC_CHECK_CAP,ECRC Check Capable. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." "0,1" bitfld.long 0x18 6. "ECRC_GEN_EN,ECRC Generation Enable. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." "0,1" rbitfld.long 0x18 5. "ECRC_GEN_CAP,ECRC Generation Capable. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." "0,1" newline hexmask.long.byte 0x18 0.--4. 1. "FIRST_ERR_POINTER,First Error Pointer. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." rgroup.long (0x1C+0x100)++0xF line.long 0x0 "HDR_LOG_0_OFF,Header Log Register 0. For a description of this standard PCIe register. see the PCI Express Specification." hexmask.long.byte 0x0 24.--31. 1. "FIRST_DWORD_FOURTH_BYTE,Byte 3 of Header log register of First 32 bit Data Word. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." hexmask.long.byte 0x0 16.--23. 1. "FIRST_DWORD_THIRD_BYTE,Byte 2 of Header log register of First 32 bit Data Word. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." hexmask.long.byte 0x0 8.--15. 1. "FIRST_DWORD_SECOND_BYTE,Byte 1 of Header log register of First 32 bit Data Word. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." newline hexmask.long.byte 0x0 0.--7. 1. "FIRST_DWORD_FIRST_BYTE,Byte 0 of Header log register of First 32 bit Data Word. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." line.long 0x4 "HDR_LOG_1_OFF,Header Log Register 1. For a description of this standard PCIe register. see the PCI Express Specification." hexmask.long.byte 0x4 24.--31. 1. "SECOND_DWORD_FOURTH_BYTE,Byte 3 of Header log register of Second 32 bit Data Word. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." hexmask.long.byte 0x4 16.--23. 1. "SECOND_DWORD_THIRD_BYTE,Byte 2 of Header log register of Second 32 bit Data Word. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." hexmask.long.byte 0x4 8.--15. 1. "SECOND_DWORD_SECOND_BYTE,Byte 1 of Header log register of Second 32 bit Data Word. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." newline hexmask.long.byte 0x4 0.--7. 1. "SECOND_DWORD_FIRST_BYTE,Byte 0 of Header log register of Second 32 bit Data Word. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." line.long 0x8 "HDR_LOG_2_OFF,Header Log Register 2. For a description of this standard PCIe register. see the PCI Express Specification." hexmask.long.byte 0x8 24.--31. 1. "THIRD_DWORD_FOURTH_BYTE,Byte 3 of Header log register of Third 32 bit Data Word. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." hexmask.long.byte 0x8 16.--23. 1. "THIRD_DWORD_THIRD_BYTE,Byte 2 of Header log register of Third 32 bit Data Word. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." hexmask.long.byte 0x8 8.--15. 1. "THIRD_DWORD_SECOND_BYTE,Byte 1 of Header log register of Third 32 bit Data Word. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." newline hexmask.long.byte 0x8 0.--7. 1. "THIRD_DWORD_FIRST_BYTE,Byte 0 of Header log register of Third 32 bit Data Word. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." line.long 0xC "HDR_LOG_3_OFF,Header Log Register 3. For a description of this standard PCIe register. see the PCI Express Specification." hexmask.long.byte 0xC 24.--31. 1. "FOURTH_DWORD_FOURTH_BYTE,Byte 3 of Header log register of Fourth 32 bit Data Word. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." hexmask.long.byte 0xC 16.--23. 1. "FOURTH_DWORD_THIRD_BYTE,Byte 2 of Header log register of Fourth 32 bit Data Word. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." hexmask.long.byte 0xC 8.--15. 1. "FOURTH_DWORD_SECOND_BYTE,Byte 1 of Header log register of Fourth 32 bit Data Word. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." newline hexmask.long.byte 0xC 0.--7. 1. "FOURTH_DWORD_FIRST_BYTE,Byte 0 of Header log register of Fourth 32 bit Data Word. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." group.long (0x2C+0x100)++0x7 line.long 0x0 "ROOT_ERR_CMD_OFF,Root Error Command Register. For a description of this standard PCIe register. see the PCI Express Specification." hexmask.long 0x0 3.--31. 1. "RSVDP_3,Reserved for future use." bitfld.long 0x0 2. "FATAL_ERR_REPORTING_EN,Fatal Error Reporting Enable. For a description of this standard PCIe register field see the PCI Express Specification." "0,1" bitfld.long 0x0 1. "NON_FATAL_ERR_REPORTING_EN,Non-Fatal Error Reporting Enable. For a description of this standard PCIe register field see the PCI Express Specification." "0,1" newline bitfld.long 0x0 0. "CORR_ERR_REPORTING_EN,Correctable Error Reporting Enable. For a description of this standard PCIe register field see the PCI Express Specification." "0,1" line.long 0x4 "ROOT_ERR_STATUS_OFF,Root Error Status Register. For a description of this standard PCIe register. see the PCI Express Specification." hexmask.long.byte 0x4 27.--31. 1. "ADV_ERR_INT_MSG_NUM,Advanced Error Interrupt Message Number. For a description of this standard PCIe register field see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN.." hexmask.long.tbyte 0x4 7.--26. 1. "RSVDP_7,Reserved for future use." bitfld.long 0x4 6. "FATAL_ERR_MSG_RX,One or more Fatal Error Messages Received. For a description of this standard PCIe register field see the PCI Express Specification." "0,1" newline bitfld.long 0x4 5. "NON_FATAL_ERR_MSG_RX,One or more Non-Fatal Error Messages Received. For a description of this standard PCIe register field see the PCI Express Specification." "0,1" bitfld.long 0x4 4. "FIRST_UNCORR_FATAL,First Uncorrectable Error is Fatal. For a description of this standard PCIe register field see the PCI Express Specification." "0,1" bitfld.long 0x4 3. "MUL_ERR_FATAL_NON_FATAL_RX,Multiple Fatal or Non-Fatal Errors Received. For a description of this standard PCIe register field see the PCI Express Specification." "0,1" newline bitfld.long 0x4 2. "ERR_FATAL_NON_FATAL_RX,Fatal or Non-Fatal Error Received. For a description of this standard PCIe register field see the PCI Express Specification." "0,1" bitfld.long 0x4 1. "MUL_ERR_COR_RX,Multiple Correctable Errors Received. For a description of this standard PCIe register field see the PCI Express Specification." "0,1" bitfld.long 0x4 0. "ERR_COR_RX,Correctable Error Received. For a description of this standard PCIe register field see the PCI Express Specification." "0,1" rgroup.long (0x34+0x100)++0x13 line.long 0x0 "ERR_SRC_ID_OFF,Error Source Identification Register. For a description of this standard PCIe register. see the PCI Express Specification." hexmask.long.word 0x0 16.--31. 1. "ERR_FATAL_NON_FATAL_SOURCE_ID,Source of Fatal/Non-Fatal Error. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." hexmask.long.word 0x0 0.--15. 1. "ERR_COR_SOURCE_ID,Source of Correctable Error. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." line.long 0x4 "TLP_PREFIX_LOG_1_OFF,TLP Prefix Log Register 1. For a description of this standard PCIe register. see the PCI Express Specification." hexmask.long.byte 0x4 24.--31. 1. "CFG_TLP_PFX_LOG_1_FOURTH_BYTE,Byte 3 of Error TLP Prefix Log 1. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." hexmask.long.byte 0x4 16.--23. 1. "CFG_TLP_PFX_LOG_1_THIRD_BYTE,Byte 2 of Error TLP Prefix Log 1. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." hexmask.long.byte 0x4 8.--15. 1. "CFG_TLP_PFX_LOG_1_SECOND_BYTE,Byte 1 of Error TLP Prefix Log 1. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." newline hexmask.long.byte 0x4 0.--7. 1. "CFG_TLP_PFX_LOG_1_FIRST_BYTE,Byte 0 of Error TLP Prefix Log 1. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." line.long 0x8 "TLP_PREFIX_LOG_2_OFF,TLP Prefix Log Register 2. For a description of this standard PCIe register. see the PCI Express Specification." hexmask.long.byte 0x8 24.--31. 1. "CFG_TLP_PFX_LOG_2_FOURTH_BYTE,Byte 3 Error TLP Prefix Log 2. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." hexmask.long.byte 0x8 16.--23. 1. "CFG_TLP_PFX_LOG_2_THIRD_BYTE,Byte 2 Error TLP Prefix Log 2. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." hexmask.long.byte 0x8 8.--15. 1. "CFG_TLP_PFX_LOG_2_SECOND_BYTE,Byte 1 Error TLP Prefix Log 2. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." newline hexmask.long.byte 0x8 0.--7. 1. "CFG_TLP_PFX_LOG_2_FIRST_BYTE,Byte 0 Error TLP Prefix Log 2. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." line.long 0xC "TLP_PREFIX_LOG_3_OFF,TLP Prefix Log Register 3. For a description of this standard PCIe register. see the PCI Express Specification." hexmask.long.byte 0xC 24.--31. 1. "CFG_TLP_PFX_LOG_3_FOURTH_BYTE,Byte 3 Error TLP Prefix Log 3. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." hexmask.long.byte 0xC 16.--23. 1. "CFG_TLP_PFX_LOG_3_THIRD_BYTE,Byte 2 Error TLP Prefix Log 3. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." hexmask.long.byte 0xC 8.--15. 1. "CFG_TLP_PFX_LOG_3_SECOND_BYTE,Byte 1 Error TLP Prefix Log 3. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." newline hexmask.long.byte 0xC 0.--7. 1. "CFG_TLP_PFX_LOG_3_FIRST_BYTE,Byte 0 Error TLP Prefix Log 3. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." line.long 0x10 "TLP_PREFIX_LOG_4_OFF,TLP Prefix Log Register 4. For a description of this standard PCIe register. see the PCI Express Specification." hexmask.long.byte 0x10 24.--31. 1. "CFG_TLP_PFX_LOG_4_FOURTH_BYTE,Byte 3 Error TLP Prefix Log 4. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." hexmask.long.byte 0x10 16.--23. 1. "CFG_TLP_PFX_LOG_4_THIRD_BYTE,Byte 2 Error TLP Prefix Log 4. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." hexmask.long.byte 0x10 8.--15. 1. "CFG_TLP_PFX_LOG_4_SECOND_BYTE,Byte 1 Error TLP Prefix Log 4. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." newline hexmask.long.byte 0x10 0.--7. 1. "CFG_TLP_PFX_LOG_4_FIRST_BYTE,Byte 0 Error TLP Prefix Log 4. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." tree.end tree "PF0_MSI_CAP (PF MSI Capability Structure)" group.long (0x0+0x50)++0x13 line.long 0x0 "PCI_MSI_CAP_ID_NEXT_CTRL_REG,MSI Capability Header and Message Control Register." hexmask.long.byte 0x0 27.--31. 1. "RSVDP_27,Reserved for future use." bitfld.long 0x0 26. "PCI_MSI_EXT_DATA_EN,Extended Message Data Enable. - If set the function is enabled to provide Extended Message Data. - If clear the function is not enabled to provide Extended Message Data. Note: The access attributes of this field are as follows: -.." "0,1" bitfld.long 0x0 25. "PCI_MSI_EXT_DATA_CAP,Extended Message Data Capable. - If set the function is capable of providing Extended Message Data. - If clear the function does not support providing Extended Message Data. Note: The access attributes of this field are as follows:.." "0,1" newline rbitfld.long 0x0 24. "PCI_PVM_SUPPORT,Per-Vector Masking Capable. - If set the function supports MSI Per-Vector Masking. - If clear the function does not support MSI Per-Vector Masking. This bit must be set if the function is a PF or VF within an SR-IOV Device." "0,1" bitfld.long 0x0 23. "PCI_MSI_64_BIT_ADDR_CAP,64 bit address capable. - If set the function is capable of sending a 64-bit message address. - If clear the function is not capable of sending a 64-bit message address. This bit must be set if the function is a PCI Express.." "0,1" bitfld.long 0x0 20.--22. "PCI_MSI_MULTIPLE_MSG_EN,Multiple Message Enable. Software writes to this field to indicate the number of allocated vectors (equal to or less than the number of requested vectors). The number of allocated vectors is aligned to a power of two. If a.." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 17.--19. "PCI_MSI_MULTIPLE_MSG_CAP,Multiple Message Capable. System software reads this field to determine the number of requested vectors. The number of requested vectors must be aligned to a power of two (if a function requires three vectors it requests four by.." "0,1,2,3,4,5,6,7" bitfld.long 0x0 16. "PCI_MSI_ENABLE,MSI Enable. - If set and the MSI-X Enable bit in the MSI-X Message Control register is clear the function is permitted to use MSI to request service and is prohibited from using INTx interrupts. System configuration software sets this bit.." "0,1" hexmask.long.byte 0x0 8.--15. 1. "PCI_MSI_CAP_NEXT_OFFSET,Next Capability Pointer. This field contains the offset to the next PCI Capability structure or 00h if no other items exist in the linked list of Capabilities. Note: The access attributes of this field are as follows: - Wire: No.." newline hexmask.long.byte 0x0 0.--7. 1. "PCI_MSI_CAP_ID,Capability ID. Indicates the MSI Capability structure. This field returns a Capability ID of 05h indicating that this is an MSI Capability structure." line.long 0x4 "MSI_CAP_OFF_04H_REG,Message Address Register for MSI (Offset 04h)." hexmask.long 0x4 2.--31. 1. "PCI_MSI_CAP_OFF_04H,Message Address - System-specified message address. If the Message Enable bit (bit 16 of the PCI_MSI_CAP_ID_NEXT_CTRL_REG register) is set the contents of this field specify the DWORD-aligned address (Address[31:02]) for the MSI.." rbitfld.long 0x4 0.--1. "RSVDP_0,Reserved for future use." "0,1,2,3" line.long 0x8 "MSI_CAP_OFF_08H_REG,For a function that supports a 32-bit message address. - bits[31:16] of this register represent the Extended Message Data. and - bits[15:0] of this register represent the Message Data For a function that supports a 64-bit message.." hexmask.long.word 0x8 16.--31. 1. "PCI_MSI_CAP_OFF_0AH,For a function that supports a 32-bit message address this field contains Extended Message Data (System-specified message data). For the MSI Capability structures without per-vector masking it must be implemented if the Extended.." hexmask.long.word 0x8 0.--15. 1. "PCI_MSI_CAP_OFF_08H,For a function that supports a 32-bit message address this field contains Message Data (System-specified message data). If the Message Enable bit (bit 16 of the PCI_MSI_CAP_ID_NEXT_CTRL_REG) is set the function sends a DWORD Memory.." line.long 0xC "MSI_CAP_OFF_0CH_REG,For a function that supports a 32-bit message address. this register contains the Mask Bits when the Per-Vector Masking Capable bit (bit 24 of PCI_MSI_CAP_ID_NEXT_CTRL_REG) is set. For a function that supports a 64-bit message.." hexmask.long.word 0xC 16.--31. 1. "PCI_MSI_CAP_OFF_0EH,For a function that supports a 32-bit message address this field contains the upper Mask Bits when the Per Vector Masking Capable bit (PCI_MSI_CAP_ID_NEXT_CTRL_REG.PCI_PVM_SUPPORT) is set. For a function that supports a 64-bit.." hexmask.long.word 0xC 0.--15. 1. "PCI_MSI_CAP_OFF_0CH,For a function that supports a 32-bit message address this field contains the lower Mask Bits when the Per Vector Masking Capable bit (PCI_MSI_CAP_ID_NEXT_CTRL_REG.PCI_PVM_SUPPORT) is set. For a function that supports a 64-bit.." line.long 0x10 "MSI_CAP_OFF_10H_REG,For a function that supports a 32-bit message address. this register contains the Pending Bits when the Per-Vector Masking Capable bit (bit 24 of PCI_MSI_CAP_ID_NEXT_CTRL_REG) is set. For a function that supports a 64-bit message.." hexmask.long 0x10 0.--31. 1. "PCI_MSI_CAP_OFF_10H,Used for MSI when the Per Vector Masking Capable bit (PCI_MSI_CAP_ID_NEXT_CTRL_REG.PCI_PVM_SUPPORT) is set. For 32-bit contains Pending Bits. For 64-bit contains Mask Bits. For a description of this standard PCIe register field see.." rgroup.long (0x14+0x50)++0x3 line.long 0x0 "MSI_CAP_OFF_14H_REG,Pending Bits Register for MSI. This register is used for a function that supports a 64-bit message address when the Per-Vector Masking Capable bit (bit 24 of PCI_MSI_CAP_ID_NEXT_CTRL_REG) is set." hexmask.long 0x0 0.--31. 1. "PCI_MSI_CAP_OFF_14H,Pending Bits. For each pending bit that is set the function has a pending associated message." tree.end tree "PF0_MSIX_CAP (PF MSI-X Capability Structure)" group.long (0x0+0xB0)++0xB line.long 0x0 "PCI_MSIX_CAP_ID_NEXT_CTRL_REG,MSI-X Capability ID. Next Pointer. Control Registers. For a description of this standard PCIe register. see the PCI Express Base Specification." bitfld.long 0x0 31. "PCI_MSIX_ENABLE,MSI-X Enable. For a description of this standard PCIe register field see the PCI Express Base Specification." "0,1" bitfld.long 0x0 30. "PCI_MSIX_FUNCTION_MASK,Function Mask. For a description of this standard PCIe register field see the PCI Express Base Specification. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" "0,1" rbitfld.long 0x0 27.--29. "RSVDP_27,Reserved for future use." "0,1,2,3,4,5,6,7" newline hexmask.long.word 0x0 16.--26. 1. "PCI_MSIX_TABLE_SIZE,MSI-X Table Size. For a description of this standard PCIe register field see the PCI Express Base Specification. SRIOV Note: All VFs in a single PF have the same value for 'MSI-X Table Size' (PCI_MSIX_TABLE_SIZE field in.." hexmask.long.byte 0x0 8.--15. 1. "PCI_MSIX_CAP_NEXT_OFFSET,MSI-X Next Capability Pointer. For a description of this standard PCIe register field see the PCI Express Base Specification. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN.." hexmask.long.byte 0x0 0.--7. 1. "PCI_MSIX_CAP_ID,MSI-X Capability ID. For a description of this standard PCIe register field see the PCI Express Base Specification." line.long 0x4 "MSIX_TABLE_OFFSET_REG,MSI-X Table Offset and BIR Register. For a description of this standard PCIe register. see the PCI Express Base Specification." hexmask.long 0x4 3.--31. 1. "PCI_MSIX_TABLE_OFFSET,MSI-X Table Offset. For a description of this standard PCIe register field see the PCI Express Base Specification. SRIOV Note: All VFs in a single PF have the same value for 'MSI-X Table Offset' (PCI_MSIX_TABLE_OFFSET field in.." bitfld.long 0x4 0.--2. "PCI_MSIX_BIR,MSI-X Table BAR Indicator Register Field. For a description of this standard PCIe register field see the PCI Express Base Specification. SRIOV Note: All VFs in a single PF have the same value for 'MSI-X Table BAR Indicator Register'.." "0,1,2,3,4,5,6,7" line.long 0x8 "MSIX_PBA_OFFSET_REG,MSI-X PBA Offset and BIR Register. For a description of this standard PCIe register. see the PCI Express Base Specification." hexmask.long 0x8 3.--31. 1. "PCI_MSIX_PBA_OFFSET,MSI-X PBA Offset. For a description of this standard PCIe register field see the PCI Express Base Specification. SRIOV Note: All VFs in a single PF have the same value for 'MSI-X PBA Offset' (PCI_MSIX_PBA_OFFSET field in.." bitfld.long 0x8 0.--2. "PCI_MSIX_PBA_BIR,MSI-X PBA BIR. For a description of this standard PCIe register field see the PCI Express Base Specification. SRIOV Note: All VFs in a single PF have the same value for 'MSI-X PBA BIR' (PCI_MSIX_PBA_BIR field in.." "0,1,2,3,4,5,6,7" tree.end tree "PF0_MSIX_CAP_DBI2 (DBI2 Shadow Block: PF MSI-X Capability Structure)" rgroup.long (0x0+0x10B0)++0x3 line.long 0x0 "SHADOW_PCI_MSIX_CAP_ID_NEXT_CTRL_REG,MSI-X Capability ID. Next Pointer. Control Registers. For a description of this standard PCIe register. see the PCI Express Base Specification." hexmask.long.byte 0x0 27.--31. 1. "RSVDP_27,Reserved for future use." hexmask.long.word 0x0 16.--26. 1. "PCI_MSIX_TABLE_SIZE,MSI-X Table Size in the shadow register. Note: The access attributes of this field are as follows: - Wire: No access - Dbi: No access - Dbi2: if (DBI_RO_WR_EN == 1) then R/W else R Note: This register field is sticky." hexmask.long.word 0x0 0.--15. 1. "RSVDP_0,Reserved for future use." group.long 0x4++0x7 line.long 0x0 "SHADOW_MSIX_TABLE_OFFSET_REG,MSI-X Table Offset and BIR Register. For a description of this standard PCIe register. see the PCI Express Base Specification." hexmask.long 0x0 3.--31. 1. "PCI_MSIX_TABLE_OFFSET,MSI-X Table Offset. For a description of this standard PCIe register field see the PCI Express Base Specification. Note: The access attributes of this field are as follows: - Wire: No access - Dbi: No access - Dbi2: if.." bitfld.long 0x0 0.--2. "PCI_MSIX_BIR,MSI-X Table BAR Indicator Register Field. For a description of this standard PCIe register field see the PCI Express Base Specification. Note: The access attributes of this field are as follows: - Wire: No access - Dbi: No access - Dbi2: if.." "?,?,if,?,?,?,?,?" line.long 0x4 "SHADOW_MSIX_PBA_OFFSET_REG,MSI-X PBA Offset and BIR Register. For a description of this standard PCIe register. see the PCI Express Base Specification." hexmask.long 0x4 3.--31. 1. "PCI_MSIX_PBA_OFFSET,MSI-X PBA Offset. For a description of this standard PCIe register field see the PCI Express Base Specification. Note: The access attributes of this field are as follows: - Wire: No access - Dbi: No access - Dbi2: if (DBI_RO_WR_EN ==.." bitfld.long 0x4 0.--2. "PCI_MSIX_PBA_BIR,MSI-X PBA BIR. For a description of this standard PCIe register field see the PCI Express Base Specification. Note: The access attributes of this field are as follows: - Wire: No access - Dbi: No access - Dbi2: if (DBI_RO_WR_EN == 1 &&.." "?,?,if,?,?,?,?,?" tree.end tree "PF0_DMA_CAP (DMA Port Logic Structure)" group.long (0x0+0xC8000)++0x3 line.long 0x0 "DMA_CTRL_DATA_ARB_PRIOR_OFF,DMA Arbitration Scheme for TRGT1 Interface. This register is used to control traffic priorities among various sources that are delivered to your application through TRGT1 where 0x0 represents the highest priority. - Non-DMA Rx.." hexmask.long.tbyte 0x0 12.--31. 1. "RSVDP_12,Reserved for future use." bitfld.long 0x0 9.--11. "RDBUFF_TRGT_WEIGHT,DMA Read Channel MWr Requests. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 6.--8. "RD_CTRL_TRGT_WEIGHT,DMA Read Channel MRd Requests. For LL element/descriptor access. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" "0,1,2,3,4,5,6,7" bitfld.long 0x0 3.--5. "WR_CTRL_TRGT_WEIGHT,DMA Write Channel MRd Requests. For DMA data requests and LL element/descriptor access. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 0.--2. "RTRGT1_WEIGHT,Non-DMA Rx Requests. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" "0,1,2,3,4,5,6,7" group.long (0x8+0xC8000)++0xB line.long 0x0 "DMA_CTRL_OFF,DMA Number of Channels Register." hexmask.long.byte 0x0 26.--31. 1. "RSVDP_26,Reserved for future use." bitfld.long 0x0 25. "DIS_C2W_CACHE_RD,Disable DMA Read Channels 'completion to memory write' context cache pre-fetch function. Note: For internal debugging only. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" "0,1" newline bitfld.long 0x0 24. "DIS_C2W_CACHE_WR,Disable DMA Write Channels 'completion to memory write' context cache pre-fetch function. Note: For internal debugging only. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" "0,1" hexmask.long.byte 0x0 20.--23. 1. "RSVDP_20,Reserved for future use." newline hexmask.long.byte 0x0 16.--19. 1. "NUM_DMA_RD_CHAN,Number of Read Channels. You can read this register to determine the number of read channels the DMA controller has been configured to support." hexmask.long.word 0x0 4.--15. 1. "RSVDP_4,Reserved for future use." newline hexmask.long.byte 0x0 0.--3. 1. "NUM_DMA_WR_CHAN,Number of Write Channels. You can read this register to determine the number of write channels the DMA controller has been configured to support." line.long 0x4 "DMA_WRITE_ENGINE_EN_OFF,DMA Write Engine Enable Register." hexmask.long.byte 0x4 24.--31. 1. "RSVDP_24,Reserved for future use." bitfld.long 0x4 23. "DMA_WRITE_ENGINE_EN_HSHAKE_CH7,Enable Handshake for DMA Write Engine Channel 7. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" "0,1" newline bitfld.long 0x4 22. "DMA_WRITE_ENGINE_EN_HSHAKE_CH6,Enable Handshake for DMA Write Engine Channel 6. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" "0,1" bitfld.long 0x4 21. "DMA_WRITE_ENGINE_EN_HSHAKE_CH5,Enable Handshake for DMA Write Engine Channel 5. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" "0,1" newline bitfld.long 0x4 20. "DMA_WRITE_ENGINE_EN_HSHAKE_CH4,Enable Handshake for DMA Write Engine Channel 4. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" "0,1" bitfld.long 0x4 19. "DMA_WRITE_ENGINE_EN_HSHAKE_CH3,Enable Handshake for DMA Write Engine Channel 3. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" "0,1" newline bitfld.long 0x4 18. "DMA_WRITE_ENGINE_EN_HSHAKE_CH2,Enable Handshake for DMA Write Engine Channel 2. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" "0,1" bitfld.long 0x4 17. "DMA_WRITE_ENGINE_EN_HSHAKE_CH1,Enable Handshake for DMA Write Engine Channel 1. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" "0,1" newline bitfld.long 0x4 16. "DMA_WRITE_ENGINE_EN_HSHAKE_CH0,Enable Handshake for DMA Write Engine Channel 0. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" "0,1" hexmask.long.word 0x4 1.--15. 1. "RSVDP_1,Reserved for future use." newline bitfld.long 0x4 0. "DMA_WRITE_ENGINE,DMA Write Engine Enable. - 1: Enable - 0: Disable (Soft Reset) For normal operation you must initially set this bit to '1' before any other software setup actions. You do not need to toggle or rewrite to this bit during normal.." "Disable,Enable" line.long 0x8 "DMA_WRITE_DOORBELL_OFF,DMA Write Doorbell Register." bitfld.long 0x8 31. "WR_STOP,Stop. Set in conjunction with the Doorbell Number field. The DMA write channel stops issuing requests sets the channel status to 'Stopped' and asserts the 'Abort' interrupt if it is enabled. Before setting the Stop bit you must read the.." "0,1" hexmask.long 0x8 3.--30. 1. "RSVDP_3,Reserved for future use." newline bitfld.long 0x8 0.--2. "WR_DOORBELL_NUM,Doorbell Number. You must write the channel number to this register to start the DMA write transfer for that channel. The DMA detects a write to this register field even if the value of this field does not change. You do not need to.." "0,1,2,3,4,5,6,7" group.long (0x18+0xC8000)++0x7 line.long 0x0 "DMA_WRITE_CHANNEL_ARB_WEIGHT_LOW_OFF,DMA Write Engine Channel Arbitration Weight Low Register. The 5-bit channel weight (for write channels 0-3) specifies the maximum number of TLP requests that the DMA can issue for that channel before it must return to.." hexmask.long.word 0x0 20.--31. 1. "RSVDP_20,Reserved for future use." hexmask.long.byte 0x0 15.--19. 1. "WRITE_CHANNEL3_WEIGHT,Channel 3 Weight. The weight is initialized by software before ringing the doorbell. The value is used by the channel weighted round robin arbiter to select the next channel read request. A value of '0' means that one TLP is issued.." newline hexmask.long.byte 0x0 10.--14. 1. "WRITE_CHANNEL2_WEIGHT,Channel 2 Weight. The weight is initialized by software before ringing the doorbell. The value is used by the channel weighted round robin arbiter to select the next channel read request. A value of '0' means that one TLP is issued.." hexmask.long.byte 0x0 5.--9. 1. "WRITE_CHANNEL1_WEIGHT,Channel 1 Weight. The weight is initialized by software before ringing the doorbell. The value is used by the channel weighted round robin arbiter to select the next channel read request. A value of '0' means that one TLP is issued.." newline hexmask.long.byte 0x0 0.--4. 1. "WRITE_CHANNEL0_WEIGHT,Channel 0 Weight. The weight is initialized by software before ringing the doorbell. The value is used by the channel weighted round robin arbiter to select the next channel read request. A value of '0' means that one TLP is issued.." line.long 0x4 "DMA_WRITE_CHANNEL_ARB_WEIGHT_HIGH_OFF,DMA Write Engine Channel Arbitration Weight High Register. The 5-bit channel weight (for write channels 4-7) specifies the maximum number of TLP requests that the DMA can issue for that channel before it must return.." hexmask.long.word 0x4 20.--31. 1. "RSVDP_20,Reserved for future use." hexmask.long.byte 0x4 15.--19. 1. "WRITE_CHANNEL7_WEIGHT,Channel 7 Weight. The weight is initialized by software before ringing the doorbell. The value is used by the channel weighted round robin arbiter to select the next channel read request. A value of '0' means that one TLP is issued.." newline hexmask.long.byte 0x4 10.--14. 1. "WRITE_CHANNEL6_WEIGHT,Channel 6 Weight. The weight is initialized by software before ringing the doorbell. The value is used by the channel weighted round robin arbiter to select the next channel read request. A value of '0' means that one TLP is issued.." hexmask.long.byte 0x4 5.--9. 1. "WRITE_CHANNEL5_WEIGHT,Channel 5 Weight. The weight is initialized by software before ringing the doorbell. The value is used by the channel weighted round robin arbiter to select the next channel read request. A value of '0' means that one TLP is issued.." newline hexmask.long.byte 0x4 0.--4. 1. "WRITE_CHANNEL4_WEIGHT,Channel 4 Weight. The weight is initialized by software before ringing the doorbell. The value is used by the channel weighted round robin arbiter to select the next channel read request. A value of '0' means that one TLP is issued.." group.long (0x2C+0xC8000)++0x7 line.long 0x0 "DMA_READ_ENGINE_EN_OFF,DMA Read Engine Enable Register." hexmask.long.byte 0x0 24.--31. 1. "RSVDP_24,Reserved for future use." bitfld.long 0x0 23. "DMA_READ_ENGINE_EN_HSHAKE_CH7,Enable Handshake for DMA Read Engine Channel 7. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" "0,1" newline bitfld.long 0x0 22. "DMA_READ_ENGINE_EN_HSHAKE_CH6,Enable Handshake for DMA Read Engine Channel 6. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" "0,1" bitfld.long 0x0 21. "DMA_READ_ENGINE_EN_HSHAKE_CH5,Enable Handshake for DMA Read Engine Channel 5. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" "0,1" newline bitfld.long 0x0 20. "DMA_READ_ENGINE_EN_HSHAKE_CH4,Enable Handshake for DMA Read Engine Channel 4. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" "0,1" bitfld.long 0x0 19. "DMA_READ_ENGINE_EN_HSHAKE_CH3,Enable Handshake for DMA Read Engine Channel 3. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" "0,1" newline bitfld.long 0x0 18. "DMA_READ_ENGINE_EN_HSHAKE_CH2,Enable Handshake for DMA Read Engine Channel 2. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" "0,1" bitfld.long 0x0 17. "DMA_READ_ENGINE_EN_HSHAKE_CH1,Enable Handshake for DMA Read Engine Channel 1. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" "0,1" newline bitfld.long 0x0 16. "DMA_READ_ENGINE_EN_HSHAKE_CH0,Enable Handshake for DMA Read Engine Channel 0. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" "0,1" hexmask.long.word 0x0 1.--15. 1. "RSVDP_1,Reserved for future use." newline bitfld.long 0x0 0. "DMA_READ_ENGINE,DMA Read Engine Enable. - 1: Enable - 0: Disable (Soft Reset) For normal operation you must initially set this bit to '1' before any other software setup actions. You do not need to toggle or rewrite to this bit during normal operation." "Disable,Enable" line.long 0x4 "DMA_READ_DOORBELL_OFF,DMA Read Doorbell Register." bitfld.long 0x4 31. "RD_STOP,Stop. Set in conjunction with the Doorbell Number field. The DMA read channel stops issuing requests sets the channel status to 'Stopped' and asserts the 'Abort' interrupt if it is enabled. Before setting the Stop bit you must read the channel.." "0,1" hexmask.long 0x4 3.--30. 1. "RSVDP_3,Reserved for future use." newline bitfld.long 0x4 0.--2. "RD_DOORBELL_NUM,Doorbell Number. You must write 0x0 to this register to start the DMA read transfer for that channel. The DMA detects a write to this register field even if the value of this field does not change. The range of this field is 0x0 to 0x7.." "0,1,2,3,4,5,6,7" group.long (0x38+0xC8000)++0x7 line.long 0x0 "DMA_READ_CHANNEL_ARB_WEIGHT_LOW_OFF,DMA Read Engine Channel Arbitration Weight Low Register. The 5-bit channel weight (for read channels 0-3) specifies the maximum number of TLP requests that the DMA can issue for that channel before it must return to.." hexmask.long.word 0x0 20.--31. 1. "RSVDP_20,Reserved for future use." hexmask.long.byte 0x0 15.--19. 1. "READ_CHANNEL3_WEIGHT,Channel 3 Weight. The weight is initialized by software before ringing the doorbell. The value is used by the channel weighted round robin arbiter to select the next channel read request. Note: The access attributes of this field are.." newline hexmask.long.byte 0x0 10.--14. 1. "READ_CHANNEL2_WEIGHT,Channel 2 Weight. The weight is initialized by software before ringing the doorbell. The value is used by the channel weighted round robin arbiter to select the next channel read request. Note: The access attributes of this field are.." hexmask.long.byte 0x0 5.--9. 1. "READ_CHANNEL1_WEIGHT,Channel 1 Weight. The weight is initialized by software before ringing the doorbell. The value is used by the channel weighted round robin arbiter to select the next channel read request. Note: The access attributes of this field are.." newline hexmask.long.byte 0x0 0.--4. 1. "READ_CHANNEL0_WEIGHT,Channel 0 Weight. The weight is initialized by software before ringing the doorbell. The value is used by the channel weighted round robin arbiter to select the next channel read request. Note: The access attributes of this field are.." line.long 0x4 "DMA_READ_CHANNEL_ARB_WEIGHT_HIGH_OFF,DMA Read Engine Channel Arbitration Weight High Register. The 5-bit channel weight (for read channels 4-7) specifies the maximum number of TLP requests that the DMA can issue for that channel before it must return to.." hexmask.long.word 0x4 20.--31. 1. "RSVDP_20,Reserved for future use." hexmask.long.byte 0x4 15.--19. 1. "READ_CHANNEL7_WEIGHT,Channel 7 Weight. The weight is initialized by software before ringing the doorbell. The value is used by the channel weighted round robin arbiter to select the next channel read request. Note: The access attributes of this field are.." newline hexmask.long.byte 0x4 10.--14. 1. "READ_CHANNEL6_WEIGHT,Channel 6 Weight. The weight is initialized by software before ringing the doorbell. The value is used by the channel weighted round robin arbiter to select the next channel read request. Note: The access attributes of this field are.." hexmask.long.byte 0x4 5.--9. 1. "READ_CHANNEL5_WEIGHT,Channel 5 Weight. The weight is initialized by software before ringing the doorbell. The value is used by the channel weighted round robin arbiter to select the next channel read request. Note: The access attributes of this field are.." newline hexmask.long.byte 0x4 0.--4. 1. "READ_CHANNEL4_WEIGHT,Channel 4 Weight. The weight is initialized by software before ringing the doorbell. The value is used by the channel weighted round robin arbiter to select the next channel read request. Note: The access attributes of this field are.." group.long (0x4C+0xC8000)++0x3 line.long 0x0 "DMA_WRITE_INT_STATUS_OFF,DMA Write Interrupt Status Register." hexmask.long.byte 0x0 24.--31. 1. "RSVDP_24,Reserved for future use." hexmask.long.byte 0x0 16.--23. 1. "WR_ABORT_INT_STATUS,Abort Interrupt Status. The DMA write channel has detected an error or you manually stopped the transfer as described in 'Error Handling Assistance by Remote Software'. Each bit corresponds to a DMA channel. Bit [0] corresponds to.." newline hexmask.long.byte 0x0 8.--15. 1. "RSVDP_8,Reserved for future use." hexmask.long.byte 0x0 0.--7. 1. "WR_DONE_INT_STATUS,Done Interrupt Status. The DMA write channel has successfully completed the DMA transfer. For more details see 'Interrupts and Error Handling'. Each bit corresponds to a DMA channel. Bit [0] corresponds to channel 0. - Enabling: For.." group.long (0x54+0xC8000)++0x7 line.long 0x0 "DMA_WRITE_INT_MASK_OFF,DMA Write Interrupt Mask Register." hexmask.long.byte 0x0 24.--31. 1. "RSVDP_24,Reserved for future use." hexmask.long.byte 0x0 16.--23. 1. "WR_ABORT_INT_MASK,Abort Interrupt Mask. Prevents the Abort interrupt status field in the DMA write interrupt status register from asserting the edma_int output. Each bit corresponds to a DMA channel. Bit [0] corresponds to channel 0. Note: The access.." newline hexmask.long.byte 0x0 8.--15. 1. "RSVDP_8,Reserved for future use." hexmask.long.byte 0x0 0.--7. 1. "WR_DONE_INT_MASK,Done Interrupt Mask. Prevents the Done interrupt status field in the DMA write interrupt status register from asserting the edma_int output. Each bit corresponds to a DMA channel. Bit [0] corresponds to channel 0. Note: The access.." line.long 0x4 "DMA_WRITE_INT_CLEAR_OFF,DMA Write Interrupt Clear Register." hexmask.long.byte 0x4 24.--31. 1. "RSVDP_24,Reserved for future use." hexmask.long.byte 0x4 16.--23. 1. "WR_ABORT_INT_CLEAR,Abort Interrupt Clear. You must write a 1'b1 to clear the corresponding bit in the Abort interrupt status field of the DMA write interrupt status register. Each bit corresponds to a DMA channel. Bit [0] corresponds to channel 0. Note:.." newline hexmask.long.byte 0x4 8.--15. 1. "RSVDP_8,Reserved for future use." hexmask.long.byte 0x4 0.--7. 1. "WR_DONE_INT_CLEAR,Done Interrupt Clear. You must write a 1'b1 to clear the corresponding bit in the Done interrupt status field of the DMA write interrupt status register. Each bit corresponds to a DMA channel. Bit [0] corresponds to channel 0. Note:.." rgroup.long (0x5C+0xC8000)++0x3 line.long 0x0 "DMA_WRITE_ERR_STATUS_OFF,DMA Write Error Status Register" hexmask.long.byte 0x0 24.--31. 1. "RSVDP_24,Reserved for future use." hexmask.long.byte 0x0 16.--23. 1. "LINKLIST_ELEMENT_FETCH_ERR_DETECT,Linked List Element Fetch Error Detected. The DMA write channel has received an error response from the AXI bus (or TRGT1 interface when the AXI Bridge is not used) while reading a linked list element from local memory." newline hexmask.long.byte 0x0 8.--15. 1. "RSVDP_8,Reserved for future use." hexmask.long.byte 0x0 0.--7. 1. "APP_READ_ERR_DETECT,Application Read Error Detected. The DMA write channel has received an error response from the AXI bus (or TRGT1 interface when the AXI Bridge is not used) while reading data from it. Each bit corresponds to a DMA channel. Bit [0].." group.long (0x60+0xC8000)++0x1F line.long 0x0 "DMA_WRITE_DONE_IMWR_LOW_OFF,DMA Write Done IMWr Address Low Register." hexmask.long 0x0 0.--31. 1. "DMA_WRITE_DONE_LOW_REG,The DMA uses this field to generate bits [31:0] of the address field for the Done IMWr TLP. Bits [1:0] must be '00' as this address must be dword aligned. Note: The access attributes of this field are as follows: - Wire: No access." line.long 0x4 "DMA_WRITE_DONE_IMWR_HIGH_OFF,DMA Write Done IMWr Interrupt Address High Register." hexmask.long 0x4 0.--31. 1. "DMA_WRITE_DONE_HIGH_REG,The DMA uses this field to generate bits [63:32] of the address field for the Done IMWr TLP. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" line.long 0x8 "DMA_WRITE_ABORT_IMWR_LOW_OFF,DMA Write Abort IMWr Address Low Register." hexmask.long 0x8 0.--31. 1. "DMA_WRITE_ABORT_LOW_REG,The DMA uses this field to generate bits [31:0] of the address field for the Abort IMWr TLP it generates. Bits [1:0] must be '00' as this address must be dword aligned. Note: The access attributes of this field are as follows: -.." line.long 0xC "DMA_WRITE_ABORT_IMWR_HIGH_OFF,DMA Write Abort IMWr Address High Register." hexmask.long 0xC 0.--31. 1. "DMA_WRITE_ABORT_HIGH_REG,The DMA uses this field to generate bits [63:32] of the address field for the Abort IMWr TLP. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" line.long 0x10 "DMA_WRITE_CH01_IMWR_DATA_OFF,DMA Write Channel 1 and 0 IMWr Data Register." hexmask.long.word 0x10 16.--31. 1. "WR_CHANNEL_1_DATA,The DMA uses this field to generate the data field for the Done or Abort IMWr TLPs it generates for write channel 1. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" hexmask.long.word 0x10 0.--15. 1. "WR_CHANNEL_0_DATA,The DMA uses this field to generate the data field for the Done or Abort IMWr TLPs it generates for write channel 0. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" line.long 0x14 "DMA_WRITE_CH23_IMWR_DATA_OFF,DMA Write Channel 3 and 2 IMWr Data Register." hexmask.long.word 0x14 16.--31. 1. "WR_CHANNEL_3_DATA,The DMA uses this field to generate the data field for the Done or Abort IMWr TLPs it generates for write channel 3. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" hexmask.long.word 0x14 0.--15. 1. "WR_CHANNEL_2_DATA,The DMA uses this field to generate the data field for the Done or Abort IMWr TLPs it generates for write channel 2. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" line.long 0x18 "DMA_WRITE_CH45_IMWR_DATA_OFF,DMA Write Channel 5 and 4 IMWr Data Register." hexmask.long.word 0x18 16.--31. 1. "WR_CHANNEL_5_DATA,The DMA uses this field to generate the data field for the Done or Abort IMWr TLPs it generates for write channel 5. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" hexmask.long.word 0x18 0.--15. 1. "WR_CHANNEL_4_DATA,The DMA uses this field to generate the data field for the Done or Abort IMWr TLPs it generates for write channel 4. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" line.long 0x1C "DMA_WRITE_CH67_IMWR_DATA_OFF,DMA Write Channel 7 and 6 IMWr Data Register." hexmask.long.word 0x1C 16.--31. 1. "WR_CHANNEL_7_DATA,The DMA uses this field to generate the data field for the Done or Abort IMWr TLPs it generates for write channel 7. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" hexmask.long.word 0x1C 0.--15. 1. "WR_CHANNEL_6_DATA,The DMA uses this field to generate the data field for the Done or Abort IMWr TLPs it generates for write channel 6. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" group.long (0x90+0xC8000)++0x3 line.long 0x0 "DMA_WRITE_LINKED_LIST_ERR_EN_OFF,DMA Write Linked List Error Enable Register. The LIE and RIE bits in the LL element enable the channel 'done' interrupts (local and remote). The LLLAIE and LLRAIE bits enable the channel 'abort' interrupts (local and.." hexmask.long.byte 0x0 24.--31. 1. "RSVDP_24,Reserved for future use." hexmask.long.byte 0x0 16.--23. 1. "WR_CHANNEL_LLLAIE,Write Channel LL Local Abort Interrupt Enable (LLLAIE). You enable the write channel local abort interrupt through this bit. The LIE and RIE bits in the LL element enable the write channel done interrupts. Each bit corresponds to a DMA.." newline hexmask.long.byte 0x0 8.--15. 1. "RSVDP_8,Reserved for future use." hexmask.long.byte 0x0 0.--7. 1. "WR_CHANNEL_LLRAIE,Write Channel LL Remote Abort Interrupt Enable (LLRAIE). You enable the write channel remote abort interrupt through this bit. The LIE and RIE bits in the LL element enable the write channel done interrupts. Each bit corresponds to a.." group.long (0xA0+0xC8000)++0x3 line.long 0x0 "DMA_READ_INT_STATUS_OFF,DMA Read Interrupt Status Register." hexmask.long.byte 0x0 24.--31. 1. "RSVDP_24,Reserved for future use." hexmask.long.byte 0x0 16.--23. 1. "RD_ABORT_INT_STATUS,Abort Interrupt Status. The DMA read channel has detected an error or you manually stopped the transfer as described in 'Stopping the DMA Transfer (Software Stop)'. Each bit corresponds to a DMA channel. Bit [0] corresponds to.." newline hexmask.long.byte 0x0 8.--15. 1. "RSVDP_8,Reserved for future use." hexmask.long.byte 0x0 0.--7. 1. "RD_DONE_INT_STATUS,Done Interrupt Status. The DMA read channel has successfully completed the DMA read transfer. Each bit corresponds to a DMA channel. Bit [0] corresponds to channel 0. - Enabling: For details see 'Interrupts and Error Handling'. -.." group.long (0xA8+0xC8000)++0x7 line.long 0x0 "DMA_READ_INT_MASK_OFF,DMA Read Interrupt Mask Register." hexmask.long.byte 0x0 24.--31. 1. "RSVDP_24,Reserved for future use." hexmask.long.byte 0x0 16.--23. 1. "RD_ABORT_INT_MASK,Abort Interrupt Mask. Prevents the Abort interrupt status field in the DMA read interrupt status register from asserting the edma_int output. Each bit corresponds to a DMA channel. Bit [0] corresponds to channel 0. Note: The access.." newline hexmask.long.byte 0x0 8.--15. 1. "RSVDP_8,Reserved for future use." hexmask.long.byte 0x0 0.--7. 1. "RD_DONE_INT_MASK,Done Interrupt Mask. Prevents the Done interrupt status field in the DMA read interrupt status register from asserting the edma_int output. Each bit corresponds to a DMA channel. Bit [0] corresponds to channel 0. Note: The access.." line.long 0x4 "DMA_READ_INT_CLEAR_OFF,DMA Read Interrupt Clear Register." hexmask.long.byte 0x4 24.--31. 1. "RSVDP_24,Reserved for future use." hexmask.long.byte 0x4 16.--23. 1. "RD_ABORT_INT_CLEAR,Abort Interrupt Clear. You must write a 1'b1 to clear the corresponding bit in the Abort interrupt status field of the DMA read interrupt status register. Each bit corresponds to a DMA channel. Bit [0] corresponds to channel 0. Note:.." newline hexmask.long.byte 0x4 8.--15. 1. "RSVDP_8,Reserved for future use." hexmask.long.byte 0x4 0.--7. 1. "RD_DONE_INT_CLEAR,Done Interrupt Clear. You must write a 1'b1 to clear the corresponding bit in the Done interrupt status field of the DMA read interrupt status register. Each bit corresponds to a DMA channel. Bit [0] corresponds to channel 0. Note:.." rgroup.long (0xB4+0xC8000)++0x7 line.long 0x0 "DMA_READ_ERR_STATUS_LOW_OFF,DMA Read Error Status Low Register." hexmask.long.byte 0x0 24.--31. 1. "RSVDP_24,Reserved for future use." hexmask.long.byte 0x0 16.--23. 1. "LINK_LIST_ELEMENT_FETCH_ERR_DETECT,Linked List Element Fetch Error Detected. - The DMA read channel has received an error response from the AXI bus while reading a linked list element from local memory. Each bit corresponds to a DMA channel. Bit [0].." newline hexmask.long.byte 0x0 8.--15. 1. "RSVDP_8,Reserved for future use." hexmask.long.byte 0x0 0.--7. 1. "APP_WR_ERR_DETECT,Application Write Error Detected. The DMA read channel has received an error response from the AXI bus (or TRGT1 interface when the AXI Bridge is not used) while writing data to it. This error is fatal. You must restart the transfer.." line.long 0x4 "DMA_READ_ERR_STATUS_HIGH_OFF,DMA Read Error Status High Register." hexmask.long.byte 0x4 24.--31. 1. "DATA_POISIONING,Data Poisoning. The DMA read channel has detected data poisoning in the completion from the remote device (in response to the MRd request). The DMA read channel will drop the completion and then be halted. The CX_FLT_MASK_UR_POIS filter.." hexmask.long.byte 0x4 16.--23. 1. "CPL_TIMEOUT,Completion Time Out. The DMA read channel has timed-out while waiting for the remote device to respond to the MRd request or a malformed CplD has been received. For more details see 'Linked List Mode'. Each bit corresponds to a DMA channel." newline hexmask.long.byte 0x4 8.--15. 1. "CPL_ABORT,Completer Abort. The DMA read channel has received a PCIe completer abort completion status from the remote device in response to the MRd request. For more details see 'Linked List Mode'. Each bit corresponds to a DMA channel. Bit [0].." hexmask.long.byte 0x4 0.--7. 1. "UNSUPPORTED_REQ,Unsupported Request. The DMA read channel has received a PCIe unsupported request completion status from the remote device in response to the MRd request. For more details see 'Linked List Mode'. Each bit corresponds to a DMA channel." group.long (0xC4+0xC8000)++0x3 line.long 0x0 "DMA_READ_LINKED_LIST_ERR_EN_OFF,DMA Read Linked List Error Enable Register. The LIE and RIE bits in the LL element enable the channel 'done' interrupts (local and remote). The LLLAIE and LLRAIE bits enable the channel 'abort' interrupts (local and remote)." hexmask.long.byte 0x0 24.--31. 1. "RSVDP_24,Reserved for future use." hexmask.long.byte 0x0 16.--23. 1. "RD_CHANNEL_LLLAIE,Read Channel LL Local Abort Interrupt Enable (LLLAIE). You enable the read channel Local Abort interrupt through this bit. The LIE and RIE bits in the LL element enable the read channel done interrupts. Each bit corresponds to a DMA.." newline hexmask.long.byte 0x0 8.--15. 1. "RSVDP_8,Reserved for future use." hexmask.long.byte 0x0 0.--7. 1. "RD_CHANNEL_LLRAIE,Read Channel LL Remote Abort Interrupt Enable (LLRAIE). You enable the read channel Remote Abort interrupt through this bit. The LIE and RIE bits in the LL element enable the read channel done interrupts. Each bit corresponds to a DMA.." group.long (0xCC+0xC8000)++0x1F line.long 0x0 "DMA_READ_DONE_IMWR_LOW_OFF,DMA Read Done IMWr Address Low Register." hexmask.long 0x0 0.--31. 1. "DMA_READ_DONE_LOW_REG,The DMA uses this field to generate bits [31:0] of the address field for the Done IMWr TLP. Bits [1:0] must be '00' as this address must be dword aligned. Note: The access attributes of this field are as follows: - Wire: No access." line.long 0x4 "DMA_READ_DONE_IMWR_HIGH_OFF,DMA Read Done IMWr Address High Register." hexmask.long 0x4 0.--31. 1. "DMA_READ_DONE_HIGH_REG,The DMA uses this field to generate bits [63:32] of the address field for the Done IMWr TLP. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" line.long 0x8 "DMA_READ_ABORT_IMWR_LOW_OFF,DMA Read Abort IMWr Address Low Register." hexmask.long 0x8 0.--31. 1. "DMA_READ_ABORT_LOW_REG,The DMA uses this field to generate bits [31:0] of the address field for the Abort IMWr TLP. Bits [1:0] must be '00' as this address must be dword aligned. Note: The access attributes of this field are as follows: - Wire: No.." line.long 0xC "DMA_READ_ABORT_IMWR_HIGH_OFF,DMA Read Abort IMWr Address High Register." hexmask.long 0xC 0.--31. 1. "DMA_READ_ABORT_HIGH_REG,The DMA uses this field to generate bits [63:32] of the address field for the Abort IMWr TLP. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" line.long 0x10 "DMA_READ_CH01_IMWR_DATA_OFF,DMA Read Channel 1 and 0 IMWr Data Register." hexmask.long.word 0x10 16.--31. 1. "RD_CHANNEL_1_DATA,The DMA uses this field to generate the data field for the Done or Abort IMWr TLPs it generates for read channel 1. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" hexmask.long.word 0x10 0.--15. 1. "RD_CHANNEL_0_DATA,The DMA uses this field to generate the data field for the Done or Abort IMWr TLPs it generates for read channel 0. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" line.long 0x14 "DMA_READ_CH23_IMWR_DATA_OFF,DMA Read Channel 3 and 2 IMWr Data Register." hexmask.long.word 0x14 16.--31. 1. "RD_CHANNEL_3_DATA,The DMA uses this field to generate the data field for the Done or Abort IMWr TLPs it generates for read channel 3. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" hexmask.long.word 0x14 0.--15. 1. "RD_CHANNEL_2_DATA,The DMA uses this field to generate the data field for the Done or Abort IMWr TLPs it generates for read channel 2. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" line.long 0x18 "DMA_READ_CH45_IMWR_DATA_OFF,DMA Read Channel 5 and 4 IMWr Data Register." hexmask.long.word 0x18 16.--31. 1. "RD_CHANNEL_5_DATA,The DMA uses this field to generate the data field for the Done or Abort IMWr TLPs it generates for read channel 5. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" hexmask.long.word 0x18 0.--15. 1. "RD_CHANNEL_4_DATA,The DMA uses this field to generate the data field for the Done or Abort IMWr TLPs it generates for read channel 4. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" line.long 0x1C "DMA_READ_CH67_IMWR_DATA_OFF,DMA Read Channel 7 and 6 IMWr Data Register." hexmask.long.word 0x1C 16.--31. 1. "RD_CHANNEL_7_DATA,The DMA uses this field to generate the data field for the Done or Abort IMWr TLPs it generates for read channel 7. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" hexmask.long.word 0x1C 0.--15. 1. "RD_CHANNEL_6_DATA,The DMA uses this field to generate the data field for the Done or Abort IMWr TLPs it generates for read channel 6. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" rgroup.long (0x108+0xC8000)++0x7 line.long 0x0 "DMA_WRITE_ENGINE_HSHAKE_CNT_LOW_OFF,DMA Write Engine Handshake Counter Channel 0/1/2/3 Register." bitfld.long 0x0 29.--31. "RSVDP_29,Reserved for future use." "0,1,2,3,4,5,6,7" hexmask.long.byte 0x0 24.--28. 1. "DMA_WRITE_ENGINE_HSHAKE_CNT_CH3,DMA handshake counter for DMA Write Engine Channel 3. If CC_DMA_HSHAKE =1 the data transfer in Linked List mode starts only when the counter is non-zero." newline bitfld.long 0x0 21.--23. "RSVDP_21,Reserved for future use." "0,1,2,3,4,5,6,7" hexmask.long.byte 0x0 16.--20. 1. "DMA_WRITE_ENGINE_HSHAKE_CNT_CH2,DMA handshake counter for DMA Write Engine Channel 2. If CC_DMA_HSHAKE =1 the data transfer in Linked List mode starts only when the counter is non-zero." newline bitfld.long 0x0 13.--15. "RSVDP_13,Reserved for future use." "0,1,2,3,4,5,6,7" hexmask.long.byte 0x0 8.--12. 1. "DMA_WRITE_ENGINE_HSHAKE_CNT_CH1,DMA handshake counter for DMA Write Engine Channel 1. If CC_DMA_HSHAKE =1 the data transfer in Linked List mode starts only when the counter is non-zero." newline bitfld.long 0x0 5.--7. "RSVDP_5,Reserved for future use." "0,1,2,3,4,5,6,7" hexmask.long.byte 0x0 0.--4. 1. "DMA_WRITE_ENGINE_HSHAKE_CNT_CH0,DMA handshake counter for DMA Write Engine Channel 0. If CC_DMA_HSHAKE =1 the data transfer in Linked List mode starts only when the counter is non-zero." line.long 0x4 "DMA_WRITE_ENGINE_HSHAKE_CNT_HIGH_OFF,DMA Write Engine Handshake Counter Channel 4/5/6/7 Register." bitfld.long 0x4 29.--31. "RSVDP_29,Reserved for future use." "0,1,2,3,4,5,6,7" hexmask.long.byte 0x4 24.--28. 1. "DMA_WRITE_ENGINE_HSHAKE_CNT_CH7,DMA handshake counter for DMA Write Engine Channel 7. If CC_DMA_HSHAKE =1 the data transfer in Linked List mode starts only when the counter is non-zero." newline bitfld.long 0x4 21.--23. "RSVDP_21,Reserved for future use." "0,1,2,3,4,5,6,7" hexmask.long.byte 0x4 16.--20. 1. "DMA_WRITE_ENGINE_HSHAKE_CNT_CH6,DMA handshake counter for DMA Write Engine Channel 6. If CC_DMA_HSHAKE =1 the data transfer in Linked List mode starts only when the counter is non-zero." newline bitfld.long 0x4 13.--15. "RSVDP_13,Reserved for future use." "0,1,2,3,4,5,6,7" hexmask.long.byte 0x4 8.--12. 1. "DMA_WRITE_ENGINE_HSHAKE_CNT_CH5,DMA handshake counter for DMA Write Engine Channel 5. If CC_DMA_HSHAKE =1 the data transfer in Linked List mode starts only when the counter is non-zero." newline bitfld.long 0x4 5.--7. "RSVDP_5,Reserved for future use." "0,1,2,3,4,5,6,7" hexmask.long.byte 0x4 0.--4. 1. "DMA_WRITE_ENGINE_HSHAKE_CNT_CH4,DMA handshake counter for DMA Write Engine Channel 4. If CC_DMA_HSHAKE =1 the data transfer in Linked List mode starts only when the counter is non-zero." rgroup.long (0x118+0xC8000)++0x7 line.long 0x0 "DMA_READ_ENGINE_HSHAKE_CNT_LOW_OFF,DMA Read Engine Handshake Counter Channel 0/1/2/3 Register." bitfld.long 0x0 29.--31. "RSVDP_29,Reserved for future use." "0,1,2,3,4,5,6,7" hexmask.long.byte 0x0 24.--28. 1. "DMA_READ_ENGINE_HSHAKE_CNT_CH3,DMA handshake counter for DMA Read Engine Channel 3. If CC_DMA_HSHAKE =1 the data transfer in Linked List mode starts only when the counter is non-zero." newline bitfld.long 0x0 21.--23. "RSVDP_21,Reserved for future use." "0,1,2,3,4,5,6,7" hexmask.long.byte 0x0 16.--20. 1. "DMA_READ_ENGINE_HSHAKE_CNT_CH2,DMA handshake counter for DMA Read Engine Channel 2. If CC_DMA_HSHAKE =1 the data transfer in Linked List mode starts only when the counter is non-zero." newline bitfld.long 0x0 13.--15. "RSVDP_13,Reserved for future use." "0,1,2,3,4,5,6,7" hexmask.long.byte 0x0 8.--12. 1. "DMA_READ_ENGINE_HSHAKE_CNT_CH1,DMA handshake counter for DMA Read Engine Channel 1. If CC_DMA_HSHAKE =1 the data transfer in Linked List mode starts only when the counter is non-zero." newline bitfld.long 0x0 5.--7. "RSVDP_5,Reserved for future use." "0,1,2,3,4,5,6,7" hexmask.long.byte 0x0 0.--4. 1. "DMA_READ_ENGINE_HSHAKE_CNT_CH0,DMA handshake counter for DMA Read Engine Channel 0. If CC_DMA_HSHAKE =1 the data transfer in Linked List mode starts only when the counter is non-zero." line.long 0x4 "DMA_READ_ENGINE_HSHAKE_CNT_HIGH_OFF,DMA Read Engine Handshake Counter Channel 4/5/6/7 Register." bitfld.long 0x4 29.--31. "RSVDP_29,Reserved for future use." "0,1,2,3,4,5,6,7" hexmask.long.byte 0x4 24.--28. 1. "DMA_READ_ENGINE_HSHAKE_CNT_CH7,DMA handshake counter for DMA Read Engine Channel 7. If CC_DMA_HSHAKE =1 the data transfer in Linked List mode starts only when the counter is non-zero." newline bitfld.long 0x4 21.--23. "RSVDP_21,Reserved for future use." "0,1,2,3,4,5,6,7" hexmask.long.byte 0x4 16.--20. 1. "DMA_READ_ENGINE_HSHAKE_CNT_CH6,DMA handshake counter for DMA Read Engine Channel 6. If CC_DMA_HSHAKE =1 the data transfer in Linked List mode starts only when the counter is non-zero." newline bitfld.long 0x4 13.--15. "RSVDP_13,Reserved for future use." "0,1,2,3,4,5,6,7" hexmask.long.byte 0x4 8.--12. 1. "DMA_READ_ENGINE_HSHAKE_CNT_CH5,DMA handshake counter for DMA Read Engine Channel 5. If CC_DMA_HSHAKE =1 the data transfer in Linked List mode starts only when the counter is non-zero." newline bitfld.long 0x4 5.--7. "RSVDP_5,Reserved for future use." "0,1,2,3,4,5,6,7" hexmask.long.byte 0x4 0.--4. 1. "DMA_READ_ENGINE_HSHAKE_CNT_CH4,DMA handshake counter for DMA Read Engine Channel 4. If CC_DMA_HSHAKE =1 the data transfer in Linked List mode starts only when the counter is non-zero." repeat 8. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 )(list 0x0 0x200 0x400 0x600 0x800 0xA00 0xC00 0xE00 ) group.long ($2+0x200+0xC8000)++0x3 line.long 0x0 "DMA_CH_CONTROL1_OFF_WRCH_$1,DMA Write Channel Control 1 Register." bitfld.long 0x0 30.--31. "DMA_AT,Address Translation TLP Header Bit (AT) The DMA uses this TLP header field when generating MRd/MWr (not IMWr) TLPs. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" "0,1,2,3" bitfld.long 0x0 27.--29. "DMA_TC,Traffic Class TLP Header Bit (TC) The DMA uses this TLP header field when generating MRd/MWr (not IMWr) TLPs. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 26. "DMA_RESERVED5,Reserved. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" "0,1" bitfld.long 0x0 25. "DMA_RO,Relaxed Ordering TLP Header Bit (RO) The DMA uses this TLP header field when generating MRd/MWr (not IMWr) TLPs. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" "0,1" newline bitfld.long 0x0 24. "DMA_NS_SRC,Source No Snoop TLP Header Bit (DMA_NS_SRC). The DMA uses this TLP header field when generating MRd (SAR addressing space) (not IMWr) TLPs. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" "0,1" bitfld.long 0x0 23. "DMA_NS_DST,Destination No Snoop TLP Header Bit (DMA_NS_DST). The DMA uses this TLP header field when generating MWr (DAR addressing space) (not IMWr) TLPs. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" "0,1" newline bitfld.long 0x0 22. "DMA_MEM_TYPE,Master AXI ACE-Lite Cache Coherency Control. This field sets the DMA channel memory type of the address space of the data transfer as follows: - 0x0:peripheral type - 0x1:memory type For more details see 'ACE-Lite Features and Limitations'.." "peripheral type,memory type" hexmask.long.byte 0x0 17.--21. 1. "DMA_RESERVED2,Reserved. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" newline hexmask.long.byte 0x0 12.--16. 1. "DMA_FUNC_NUM,Function Number (FN). The controller uses this field when generating the requester ID for the MRd/MWr DMA TLP. When you have enabled SR-IOV then this field is ignored if you have set the VFE field in the 'DMA Write Channel Control 2.." bitfld.long 0x0 10.--11. "DMA_RESERVED1,Reserved. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" "0,1,2,3" newline bitfld.long 0x0 9. "LLE,Linked List Enable (LLE). - 0: Disable linked list operation - 1: Enable linked list operation Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" "Disable linked list operation,Enable linked list operation" bitfld.long 0x0 8. "CCS,Consumer Cycle State (CCS). Used in linked list mode only. It is used to synchronize the producer (software) and the consumer (DMA). For more details see 'PCS-CCS-CB-TCB Producer-Consumer Synchronization'. You must initialize this bit. The DMA.." "0,1" newline bitfld.long 0x0 7. "DMA_RESERVED0,Reserved. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" "0,1" bitfld.long 0x0 5.--6. "CS,Channel Status (CS). The channel status bits identify the current operational state of the DMA channel. The operation state encoding for each DMA channel is a s follows: - 00: Reserved - 01: Running. This channel is active and transferring data. - 10:.." "Reserved,Running,?,?" newline bitfld.long 0x0 4. "RIE,Remote Interrupt Enable (RIE). You must set this bit to enable the generation of the Done or Abort Remote interrupts. For more details see 'Interrupts and Error Handling'. In LL mode the DMA overwrites this with the RIE of the LL element. The RIE.." "0,1" bitfld.long 0x0 3. "LIE,Local Interrupt Enable (LIE). You must set this bit to enable the generation of the Done or Abort Local interrupts. For more details see 'Interrupts and Error Handling'. In LL mode the DMA overwrites this with the LIE of the LL element. The LIE bit.." "0,1" newline bitfld.long 0x0 2. "LLP,Load Link Pointer (LLP). Used in linked list mode only. Indicates that this linked list element is a link element and its LL element pointer dwords are pointing to the next (non-contiguous) element. The DMA loads this field with the LLP of the.." "0,1" bitfld.long 0x0 1. "TCB,Toggle Cycle Bit (TCB). Indicates to the DMA to toggle its interpretation of the CB. Used in linked list mode only. It is used to synchronize the producer (software) and the consumer (DMA). For more details see 'PCS-CCS-CB-TCB Producer-Consumer.." "0,1" newline bitfld.long 0x0 0. "CB,Cycle Bit (CB). Used in linked list mode only. It is used to synchronize the producer (software) and the consumer (DMA). For more details see 'PCS-CCS-CB-TCB Producer-Consumer Synchronization'. The DMA loads this field with the CB of the linked list.." "0,1" repeat.end repeat 8. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 )(list 0x0 0x200 0x400 0x600 0x800 0xA00 0xC00 0xE00 ) group.long ($2+0x208+0xC8000)++0x3 line.long 0x0 "DMA_TRANSFER_SIZE_OFF_WRCH_$1,DMA Write Transfer Size Register." hexmask.long 0x0 0.--31. 1. "DMA_TRANSFER_SIZE,DMA Transfer Size. You program this register with the size of the DMA transfer. The maximum DMA transfer size is 4Gbytes. The minimum transfer size is one byte (0x1). This field is automatically decremented by the DMA as the DMA write.." repeat.end repeat 8. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 )(list 0x0 0x200 0x400 0x600 0x800 0xA00 0xC00 0xE00 ) group.long ($2+0x20C+0xC8000)++0x3 line.long 0x0 "DMA_SAR_LOW_OFF_WRCH_$1,DMA Write SAR Low Register." hexmask.long 0x0 0.--31. 1. "SRC_ADDR_REG_LOW,Source Address Register (Lower 32 bits). Indicates the next address to be read from. The DMA increments the SAR as the DMA transfer progresses. In LL mode the DMA overwrites this with the corresponding dword of the LL element. - DMA.." repeat.end repeat 8. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 )(list 0x0 0x200 0x400 0x600 0x800 0xA00 0xC00 0xE00 ) group.long ($2+0x210+0xC8000)++0x3 line.long 0x0 "DMA_SAR_HIGH_OFF_WRCH_$1,DMA Write SAR High Register." hexmask.long 0x0 0.--31. 1. "SRC_ADDR_REG_HIGH,Source Address Register (Higher 32 bits). In LL mode the DMA overwrites this with the corresponding dword of the LL element. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" repeat.end repeat 8. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 )(list 0x0 0x200 0x400 0x600 0x800 0xA00 0xC00 0xE00 ) group.long ($2+0x214+0xC8000)++0x3 line.long 0x0 "DMA_DAR_LOW_OFF_WRCH_$1,DMA Write DAR Low Register." hexmask.long 0x0 0.--31. 1. "DST_ADDR_REG_LOW,Destination Address Register (Lower 32 bits). Indicates the next address to be written to. The DMA increments the DAR as the DMA transfer progresses. In LL mode the DMA overwrites this with the corresponding dword of the LL element. -.." repeat.end repeat 8. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 )(list 0x0 0x200 0x400 0x600 0x800 0xA00 0xC00 0xE00 ) group.long ($2+0x218+0xC8000)++0x3 line.long 0x0 "DMA_DAR_HIGH_OFF_WRCH_$1,DMA Write DAR High Register." hexmask.long 0x0 0.--31. 1. "DST_ADDR_REG_HIGH,Destination Address Register (Higher 32 bits). In LL mode the DMA overwrites this with the corresponding dword of the LL element. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" repeat.end repeat 8. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 )(list 0x0 0x200 0x400 0x600 0x800 0xA00 0xC00 0xE00 ) group.long ($2+0x21C+0xC8000)++0x3 line.long 0x0 "DMA_LLP_LOW_OFF_WRCH_$1,DMA Write Linked List Pointer Low Register." hexmask.long 0x0 0.--31. 1. "LLP_LOW,Lower bits of the address of the linked list transfer list in local memory. Used in linked list mode only. Updated by the DMA to point to the next element in the transfer list after the previous element is consumed. - When the current element is.." repeat.end repeat 8. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 )(list 0x0 0x200 0x400 0x600 0x800 0xA00 0xC00 0xE00 ) group.long ($2+0x220+0xC8000)++0x3 line.long 0x0 "DMA_LLP_HIGH_OFF_WRCH_$1,DMA Write Linked List Pointer High Register." hexmask.long 0x0 0.--31. 1. "LLP_HIGH,Upper 32 bits of the address of the linked list transfer list in local memory. Used in linked list mode only. Updated by the DMA to point to the next element in the transfer list as elements are consumed. Note: The access attributes of this.." repeat.end repeat 8. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 )(list 0x0 0x200 0x400 0x600 0x800 0xA00 0xC00 0xE00 ) group.long ($2+0x300+0xC8000)++0x3 line.long 0x0 "DMA_CH_CONTROL1_OFF_RDCH_$1,DMA Read Channel Control 1 Register." bitfld.long 0x0 30.--31. "DMA_AT,Address Translation TLP Header Bit (AT) The DMA uses this TLP header field when generating MRd/MWr (not IMWr) TLPs. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" "0,1,2,3" bitfld.long 0x0 27.--29. "DMA_TC,Traffic Class TLP Header Bit (TC) The DMA uses this TLP header field when generating MRd/MWr (not IMWr) TLPs. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 26. "DMA_RESERVED5,Reserved. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" "0,1" bitfld.long 0x0 25. "DMA_RO,Relaxed Ordering TLP Header Bit (RO) The DMA uses this TLP header field when generating MRd/MWr (not IMWr) TLPs. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" "0,1" newline bitfld.long 0x0 24. "DMA_NS_SRC,Source No Snoop TLP Header Bit (DMA_NS_SRC). The DMA uses this TLP header field when generating MRd (SAR addressing space) (not IMWr) TLPs. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" "0,1" bitfld.long 0x0 23. "DMA_NS_DST,Destination No Snoop TLP Header Bit (DMA_NS_DST). The DMA uses this TLP header field when generating MWr (DAR addressing space) (not IMWr) TLPs. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" "0,1" newline bitfld.long 0x0 22. "DMA_MEM_TYPE,Master AXI ACE-Lite Cache Coherency Control. This field sets the DMA channel memory type of the address space of the data transfer as follows: - 0x0:peripheral type - 0x1:memory type For more details see 'ACE-Lite Features and Limitations'.." "peripheral type,memory type" hexmask.long.byte 0x0 17.--21. 1. "DMA_RESERVED2,Reserved. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" newline hexmask.long.byte 0x0 12.--16. 1. "DMA_FUNC_NUM,Function Number (FN). The controller uses this field when generating the requester ID for the MRd/MWr DMA TLP. When you have enabled SR-IOV then this field is ignored if you have set the VFE field in the 'DMA Read Channel Control 2.." bitfld.long 0x0 10.--11. "DMA_RESERVED1,Reserved. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" "0,1,2,3" newline bitfld.long 0x0 9. "LLE,Linked List Enable (LLE). - 0: Disable linked list operation - 1: Enable linked list operation Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" "Disable linked list operation,Enable linked list operation" bitfld.long 0x0 8. "CCS,Consumer Cycle State (CCS). Used in linked list mode only. It is used to synchronize the producer (software) and the consumer (DMA). For more details see 'PCS-CCS-CB-TCB Producer-Consumer Synchronization'. You must initialize this bit. The DMA.." "0,1" newline bitfld.long 0x0 7. "DMA_RESERVED0,Reserved. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" "0,1" bitfld.long 0x0 5.--6. "CS,Channel Status (CS). The channel status bits identify the current operational state of the DMA channel. The operation state encoding for each DMA channel is a s follows: - 00: Reserved - 01: Running. This channel is active and transferring data. - 10:.." "Reserved,Running,?,?" newline bitfld.long 0x0 4. "RIE,Remote Interrupt Enable (RIE). You must set this bit to enable the generation of the Done or Abort Remote interrupts. For more details see 'Interrupts and Error Handling'. In LL mode the DMA overwrites this with the RIE of the LL element. The RIE.." "0,1" bitfld.long 0x0 3. "LIE,Local Interrupt Enable (LIE). You must set this bit to enable the generation of the Done or Abort Local interrupts. For more details see 'Interrupts and Error Handling'. In LL mode the DMA overwrites this with the LIE of the LL element. The LIE bit.." "0,1" newline bitfld.long 0x0 2. "LLP,Load Link Pointer (LLP). Used in linked list mode only. Indicates that this linked list element is a link element and its LL element pointer dwords are pointing to the next (non-contiguous) element. The DMA loads this field with the LLP of the.." "0,1" bitfld.long 0x0 1. "TCB,Toggle Cycle Bit (TCB). Indicates to the DMA to toggle its interpretation of the CB. Used in linked list mode only. It is used to synchronize the producer (software) and the consumer (DMA). For more details see 'PCS-CCS-CB-TCB Producer-Consumer.." "0,1" newline bitfld.long 0x0 0. "CB,Cycle Bit (CB). Used in linked list mode only. It is used to synchronize the producer (software) and the consumer (DMA). For more details see 'PCS-CCS-CB-TCB Producer-Consumer Synchronization'. The DMA loads this field with the CB of the linked list.." "0,1" repeat.end repeat 8. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 )(list 0x0 0x200 0x400 0x600 0x800 0xA00 0xC00 0xE00 ) group.long ($2+0x308+0xC8000)++0x3 line.long 0x0 "DMA_TRANSFER_SIZE_OFF_RDCH_$1,DMA Read Transfer Size Register." hexmask.long 0x0 0.--31. 1. "DMA_TRANSFER_SIZE,DMA Transfer Size. You program this register with the size of the DMA transfer. The maximum DMA transfer size is 4Gbytes. The minimum transfer size is one byte (0x1). This field is automatically decremented by the DMA as the DMA read.." repeat.end repeat 8. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 )(list 0x0 0x200 0x400 0x600 0x800 0xA00 0xC00 0xE00 ) group.long ($2+0x30C+0xC8000)++0x3 line.long 0x0 "DMA_SAR_LOW_OFF_RDCH_$1,DMA Read SAR Low Register." hexmask.long 0x0 0.--31. 1. "SRC_ADDR_REG_LOW,Source Address Register (Lower 32 bits). Indicates the next address to be read from. The DMA increments the SAR as the DMA transfer progresses. In LL mode the DMA overwrites this with the corresponding dword of the LL element. - DMA.." repeat.end repeat 8. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 )(list 0x0 0x200 0x400 0x600 0x800 0xA00 0xC00 0xE00 ) group.long ($2+0x310+0xC8000)++0x3 line.long 0x0 "DMA_SAR_HIGH_OFF_RDCH_$1,DMA Read SAR High Register." hexmask.long 0x0 0.--31. 1. "SRC_ADDR_REG_HIGH,Source Address Register (Higher 32 bits). In LL mode the DMA overwrites this with the corresponding dword of the LL element. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" repeat.end repeat 8. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 )(list 0x0 0x200 0x400 0x600 0x800 0xA00 0xC00 0xE00 ) group.long ($2+0x314+0xC8000)++0x3 line.long 0x0 "DMA_DAR_LOW_OFF_RDCH_$1,DMA Read DAR Low Register." hexmask.long 0x0 0.--31. 1. "DST_ADDR_REG_LOW,Destination Address Register (Lower 32 bits). Indicates the next address to be written to. The DMA increments the DAR as the DMA transfer progresses. In LL mode the DMA overwrites this with the corresponding dword of the LL element. -.." repeat.end repeat 8. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 )(list 0x0 0x200 0x400 0x600 0x800 0xA00 0xC00 0xE00 ) group.long ($2+0x318+0xC8000)++0x3 line.long 0x0 "DMA_DAR_HIGH_OFF_RDCH_$1,DMA Read DAR High Register." hexmask.long 0x0 0.--31. 1. "DST_ADDR_REG_HIGH,Destination Address Register (Higher 32 bits). In LL mode the DMA overwrites this with the corresponding dword of the LL element. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" repeat.end repeat 8. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 )(list 0x0 0x200 0x400 0x600 0x800 0xA00 0xC00 0xE00 ) group.long ($2+0x31C+0xC8000)++0x3 line.long 0x0 "DMA_LLP_LOW_OFF_RDCH_$1,DMA Read Linked List Pointer Low Register." hexmask.long 0x0 0.--31. 1. "LLP_LOW,Lower bits of the address of the linked list transfer list in local memory. Used in linked list mode only. Updated by the DMA to point to the next element in the transfer list after the previous element is consumed. - When the current element is.." repeat.end repeat 8. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 )(list 0x0 0x200 0x400 0x600 0x800 0xA00 0xC00 0xE00 ) group.long ($2+0x320+0xC8000)++0x3 line.long 0x0 "DMA_LLP_HIGH_OFF_RDCH_$1,DMA Read Linked List Pointer High Register." hexmask.long 0x0 0.--31. 1. "LLP_HIGH,Upper 32 bits of the address of the linked list transfer list in local memory. Used in linked list mode only. Updated by the DMA to point to the next element in the transfer list as elements are consumed. Note: The access attributes of this.." repeat.end tree.end tree "PF0_ATU_CAP (ATU Por Logic Structure)" repeat 8. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 )(list 0x0 0x200 0x400 0x600 0x800 0xA00 0xC00 0xE00 ) group.long ($2+0xC0000)++0x3 line.long 0x0 "IATU_REGION_CTRL_1_OFF_OUTBOUND_$1,iATU Region Control 1 Register." bitfld.long 0x0 20. "CTRL_1_FUNC_NUM,Function Number. - When the address of an outbound TLP is matched to this region and the FUNC_BYPASS field in the 'iATU Control 2 Register' is '0' then the function number used in generating the function part of the requester ID (RID).." "0,1" newline bitfld.long 0x0 13. "INCREASE_REGION_SIZE,Increase the maximum ATU Region size. When set the maximum ATU Region size is determined by CX_ATU_MAX_REGION_SIZE. When clear the maximum ATU Region size is 4 GB (default). Note: This register field is sticky." "0,1" newline bitfld.long 0x0 9.--10. "ATTR,When the address of an outbound TLP is matched to this region then the ATTR field of the TLP is changed to the value in this register. Note: This register field is sticky." "0,1,2,3" newline bitfld.long 0x0 8. "TD,This is a reserved field. Do not use. Note: This register field is sticky." "0,1" newline bitfld.long 0x0 5.--7. "TC,When the address of an outbound TLP is matched to this region then the TC field of the TLP is changed to the value in this register. Note: This register field is sticky." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x0 0.--4. 1. "TYPE,When the address of an outbound TLP is matched to this region then the TYPE field of the TLP is changed to the value in this register. Note: This register field is sticky." repeat.end repeat 8. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 )(list 0x0 0x200 0x400 0x600 0x800 0xA00 0xC00 0xE00 ) group.long ($2+0x4+0xC0000)++0x3 line.long 0x0 "IATU_REGION_CTRL_2_OFF_OUTBOUND_$1,iATU Region Control 2 Register." bitfld.long 0x0 31. "REGION_EN,Region Enable. This bit must be set to '1' for address translation to take place. Note: This register field is sticky." "0,1" newline bitfld.long 0x0 29. "INVERT_MODE,Invert Mode. When set the address matching region is inverted. Therefore an address match occurs when the untranslated address is in the region outside the defined range (Base Address to Limit Address). Note: This register field is sticky." "0,1" newline bitfld.long 0x0 28. "CFG_SHIFT_MODE,CFG Shift Mode. The iATU uses bits [27:12] of the untranslated address (on the XALI0/1/2 interface or AXI slave interface address) to form the BDF number of the outgoing CFG TLP. This supports the Enhanced Configuration Address Mapping.." "0,1" newline bitfld.long 0x0 27. "DMA_BYPASS,DMA Bypass Mode. Allows request TLPs which are initiated by the DMA controller to pass through the iATU untranslated. Note: This field is reserved for the SW product. You must set it to '0'. Note: This register field is sticky." "0,1" newline bitfld.long 0x0 23. "HEADER_SUBSTITUTE_EN,Header Substitute Enable. When enabled and region address is matched the iATU fully substitutes bytes 8-11 (for 3 DWORD header) or bytes 12-15 (for 4 DWORD header) of the outbound TLP header with the contents of the LWR_TARGET_RW.." "LWR_TARGET_RW in the..,LWR_TARGET_RW in the.." newline bitfld.long 0x0 22. "INHIBIT_PAYLOAD,Inhibit TLP Payload Data for TLP's in Matched Region; assign iATU region to be TLP without data. When enabled and region address is matched the iATU marks all TLPs as having no payload data by forcing the TLP header Fmt[1] bit =0.." "Fmt[1] =0/1 so that TLPs with or without data..,Fmt[1] =0 so that only TLP type without data is.." newline bitfld.long 0x0 21. "TLP_HEADER_FIELDS_BYPASS,TLP Header Fields Translation Bypass. In this mode header fields of the translated TLP is taken from your application transmit interface or if AMBA is configured from the AMBA sideband bus (slv_awmisc_info) and not from the.." "0,1" newline bitfld.long 0x0 20. "SNP,Serialize Non-Posted Requests. In this mode when the AXI Bridge is populated same AXI ID Non-Posted Read/Write Requests are transmitted on the wire if there are no other same ID Non-Posted Requests outstanding. Note: This register field is sticky." "0,1" newline bitfld.long 0x0 19. "FUNC_BYPASS,Function Number Translation Bypass. In this mode the function number of the translated TLP is taken from your application transmit interface and not from the CTRL_1_FUNC_NUM field of the 'iATU Control 1 Register' or the VF_NUMBER field of.." "0,1" newline bitfld.long 0x0 16. "TAG_SUBSTITUTE_EN,TAG Substitute Enable. When enabled and region address is matched the iATU substitutes the TAG field of the outbound TLP header with the contents of the TAG field in this register. The expected usage scenario is translation from AXI.." "0,1" newline hexmask.long.byte 0x0 8.--15. 1. "TAG,TAG. The substituted TAG field (byte 6) in the outgoing TLP header when TAG_SUBSTITUTE_EN is set. Note: This register field is sticky." newline hexmask.long.byte 0x0 0.--7. 1. "MSG_CODE,MSG TLPs (Message Code). When the address of an outbound TLP is matched to this region and the translated TLP TYPE field is Msg or MsgD; then the message field of the TLP is changed to the value in this register. Memory TLPs: (ST;Steering Tag)." repeat.end repeat 8. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 )(list 0x0 0x200 0x400 0x600 0x800 0xA00 0xC00 0xE00 ) group.long ($2+0x8+0xC0000)++0x3 line.long 0x0 "IATU_LWR_BASE_ADDR_OFF_OUTBOUND_$1,iATU Lower Base Address Register. The CX_ATU_MIN_REGION_SIZE configuration parameter (Value Range: 4 kB. 8 kB. 16 kB. 32 kB. 64 kB defaults to 64 kB) specifies the minimum size of an address translation region. For.." hexmask.long.tbyte 0x0 12.--31. 1. "LWR_BASE_RW,Forms bits [31:n] of the start address of the address region to be translated. n is log2(CX_ATU_MIN_REGION_SIZE) Note: This register field is sticky." newline hexmask.long.word 0x0 0.--11. 1. "LWR_BASE_HW,Forms bits [n-1:0] of the start address of the address region to be translated. The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary so these bits are always 0. A write to this location is ignored by the PCIe controller." repeat.end repeat 8. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 )(list 0x0 0x200 0x400 0x600 0x800 0xA00 0xC00 0xE00 ) group.long ($2+0xC+0xC0000)++0x3 line.long 0x0 "IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_$1,iATU Upper Base Address Register." hexmask.long 0x0 0.--31. 1. "UPPER_BASE_RW,Forms bits [63:32] of the start (and end) address of the address region to be translated. In systems with a 32-bit address space this register is not used and therefore writing to this register has no effect. Note: This register field is.." repeat.end repeat 8. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 )(list 0x0 0x200 0x400 0x600 0x800 0xA00 0xC00 0xE00 ) group.long ($2+0x10+0xC0000)++0x3 line.long 0x0 "IATU_LIMIT_ADDR_OFF_OUTBOUND_$1,iATU Limit Address Register." hexmask.long.tbyte 0x0 12.--31. 1. "LIMIT_ADDR_RW,Forms upper bits of the end address of the address region to be translated. Note: This register field is sticky." newline hexmask.long.word 0x0 0.--11. 1. "LIMIT_ADDR_HW,Forms lower bits of the end address of the address region to be translated. The end address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary so these bits are always all ones. A write to this location is ignored by the PCIe.." repeat.end repeat 8. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 )(list 0x0 0x200 0x400 0x600 0x800 0xA00 0xC00 0xE00 ) group.long ($2+0x14+0xC0000)++0x3 line.long 0x0 "IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_$1,iATU Lower Target Address Register." hexmask.long 0x0 0.--31. 1. "LWR_TARGET_RW_OUTBOUND,When HEADER_SUBSTITUTE_EN in IATU_REGION_CTRL_2_OFF_OUTBOUND_ is '0' (normal operation): - LWR_TARGET_RW[31:n] forms MSB's of the Lower Target part of the new address of the translated region; - LWR_TARGET_RW[n-1:0] are not used." repeat.end repeat 8. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 )(list 0x0 0x200 0x400 0x600 0x800 0xA00 0xC00 0xE00 ) group.long ($2+0x18+0xC0000)++0x3 line.long 0x0 "IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_$1,iATU Upper Target Address Register." hexmask.long 0x0 0.--31. 1. "UPPER_TARGET_RW,Forms bits [63:32] of the start address (Upper Target part) of the new address of the translated region. Note: This register field is sticky." repeat.end repeat 8. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 )(list 0x0 0x200 0x400 0x600 0x800 0xA00 0xC00 0xE00 ) group.long ($2+0x1C+0xC0000)++0x3 line.long 0x0 "IATU_REGION_CTRL_3_OFF_OUTBOUND_$1,iATU Region Control 3 Register." bitfld.long 0x0 31. "VF_ACTIVE,Virtual Function Active. Indicates that all of the outbound accesses are from virtual functions. For more details see VF_ACTIVE field. Note: This register field is sticky." "0,1" newline hexmask.long 0x0 3.--30. 1. "RSVDP_VF_NUMBER,Reserved for future use." newline bitfld.long 0x0 0.--2. "VF_NUMBER,Virtual Function Number. When the address of an outbound TLP is matched to this region and the FUNC_BYPASS field in the 'iATU Control 2 Register' is '0' then this field used in generating the Function part of the requester ID (RID) field of.." "0,1,2,3,4,5,6,7" repeat.end repeat 8. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 )(list 0x0 0x200 0x400 0x600 0x800 0xA00 0xC00 0xE00 ) group.long ($2+0x100+0xC0000)++0x3 line.long 0x0 "IATU_REGION_CTRL_1_OFF_INBOUND_$1,iATU Region Control 1 Register." bitfld.long 0x0 20. "CTRL_1_FUNC_NUM,Function Number. - MEM-I/O: When the Address and BAR matching logic in the controller indicate that a MEM-I/O transaction matches a BAR in the function corresponding to this value then address translation proceeds. This check is only.." "?,When the destination function number as.." newline bitfld.long 0x0 13. "INCREASE_REGION_SIZE,Increase the maximum ATU Region size. When set the maximum ATU Region size is determined by CX_ATU_MAX_REGION_SIZE. When clear the maximum ATU Region size is 4 GB (default). Note: This register field is sticky." "0,1" newline bitfld.long 0x0 9.--10. "ATTR,When the ATTR field of an inbound TLP is matched to this value then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the 'ATTR Match Enable' bit of the 'iATU Control 2 Register' is.." "0,1,2,3" newline bitfld.long 0x0 8. "TD,When the TD field of an inbound TLP is matched to this value then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the 'TD Match Enable' bit of the 'iATU Control 2 Register' is set." "0,1" newline bitfld.long 0x0 5.--7. "TC,When the TC field of an inbound TLP is matched to this value then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the 'TC Match Enable' bit of the 'iATU Control 2 Register' is set." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x0 0.--4. 1. "TYPE,When the TYPE field of an inbound TLP is matched to this value then address translation proceeds (when all other enabled field-matches are successful). Note: This register field is sticky." repeat.end repeat 8. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 )(list 0x0 0x200 0x400 0x600 0x800 0xA00 0xC00 0xE00 ) group.long ($2+0x104+0xC0000)++0x3 line.long 0x0 "IATU_REGION_CTRL_2_OFF_INBOUND_$1,iATU Region Control 2 Register." bitfld.long 0x0 31. "REGION_EN,Region Enable. This bit must be set to '1' for address translation to take place. Note: This register field is sticky." "0,1" newline bitfld.long 0x0 30. "MATCH_MODE,Match Mode. Determines Inbound matching mode for TLPs. The mode depends on the type of TLP that is received as follows: For MEM-I/O TLPs this field is interpreted as follows: - 0: Address Match Mode. The iATU operates using addresses as in.." "Address Match Mode,Vendor ID Match Mode" newline bitfld.long 0x0 29. "INVERT_MODE,Invert Mode. When set the address matching region is inverted. Therefore an address match occurs when the untranslated address is in the region outside the defined range (Base Address to Limit Address). Note: This register field is sticky." "0,1" newline bitfld.long 0x0 28. "CFG_SHIFT_MODE,CFG Shift Mode. This is useful for CFG transactions where the PCIe configuration mechanism maps bits [27:12] of the address to the bus/device and function number. This allows a CFG configuration space to be located in any 256MB window of.." "0,1" newline bitfld.long 0x0 27. "FUZZY_TYPE_MATCH_CODE,Fuzzy Type Match Mode. When enabled the iATU relaxes the matching of the TLP TYPE field against the expected TYPE field so that - CfgRd0 and CfgRd1 TLPs are seen as identical. Similarly with CfgWr0 and CfgWr1. - MWr MRd and MRdLk.." "0,1" newline bitfld.long 0x0 26. "VFBAR_MATCH_MODE_EN,VF BAR Match Mode enable. When set Virtual Function BAR matching is used which allows all VFs in a PF which match a BAR to be matched with a single ATU region. Note: This register field is sticky." "0,1" newline bitfld.long 0x0 24.--25. "RESPONSE_CODE,Response Code. Defines the type of response to give for accesses matching this region. This overrides the normal RADM filter response. Note that this feature is not available for any region where Single Address Location Translate is.." "Normal RADM filter response is used,Unsupported request,?,?" newline bitfld.long 0x0 23. "SINGLE_ADDR_LOC_TRANS_EN,Single Address Location Translate Enable. When enabled Rx TLPs can be translated to a single address location as determined by the target address register of the iATU region. The main usage scenario is translation of Messages.." "0,1" newline bitfld.long 0x0 21. "MSG_CODE_MATCH_EN,Message Code Match Enable (Msg TLPS). Ensures that a successful message Code TLP field comparison match (see Message Code field of the 'iATU Control 2 Register') occurs (in MSG transactions) for address translation to proceed. ST Match.." "0,1" newline bitfld.long 0x0 20. "VF_MATCH_EN,Virtual Function Number Match Enable. Ensures that a successful Virtual Function Number TLP field comparison match (see Virtual Function Number field of the 'iATU Control 3 Register') occurs (in MEM-I/O transactions) for address translation.." "0,1" newline bitfld.long 0x0 19. "FUNC_NUM_MATCH_EN,Function Number Match Enable. Ensures that a successful Function Number TLP field comparison match (see Function Number field of the 'iATU Control 1 Register') occurs (in MEM-I/O and CFG0/CFG1 transactions) for address translation to.." "0,1" newline bitfld.long 0x0 16. "ATTR_MATCH_EN,ATTR Match Enable. Ensures that a successful ATTR TLP field comparison match (see ATTR field of the 'iATU Control 1 Register') occurs for address translation to proceed. Note: This register field is sticky." "0,1" newline bitfld.long 0x0 15. "TD_MATCH_EN,TD Match Enable. Ensures that a successful TD TLP field comparison match (see TD field of the 'iATU Control 1 Register') occurs for address translation to proceed. Note: This register field is sticky." "0,1" newline bitfld.long 0x0 14. "TC_MATCH_EN,TC Match Enable. Ensures that a successful TC TLP field comparison match (see TC field of the 'iATU Control 1 Register') occurs for address translation to proceed. Note: This register field is sticky." "0,1" newline bitfld.long 0x0 13. "MSG_TYPE_MATCH_MODE,Message Type Match Mode. When enabled and if single address location translate enable is set then inbound TLPs of type MSG/MSGd which match the type field of the iatu_region_ctrl_1_OFF_inbound register (=>TYPE[4:3]=2'b10) will be.." "0,1" newline bitfld.long 0x0 8.--10. "BAR_NUM,BAR Number. When the BAR number of an inbound MEM or IO TLP ' that is matched by the normal internal BAR address matching mechanism ' is the same as this field address translation proceeds (when all other enabled field-matches are successful)." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x0 0.--7. 1. "MSG_CODE,MSG TLPs: (Message Code). When the TYPE field of an inbound Msg/MsgD TLP is matched to this value then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the 'Message Code Match.." repeat.end repeat 8. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 )(list 0x0 0x200 0x400 0x600 0x800 0xA00 0xC00 0xE00 ) group.long ($2+0x108+0xC0000)++0x3 line.long 0x0 "IATU_LWR_BASE_ADDR_OFF_INBOUND_$1,iATU Lower Base Address Register. The CX_ATU_MIN_REGION_SIZE configuration parameter (Value Range: 4 kB. 8 kB. 16 kB. 32 kB. 64 kB defaults to 64 kB) specifies the minimum size of an address translation region. For.." hexmask.long.tbyte 0x0 12.--31. 1. "LWR_BASE_RW,Forms bits [31:n] of the start address of the address region to be translated. n is log2(CX_ATU_MIN_REGION_SIZE) Note: This register field is sticky." newline hexmask.long.word 0x0 0.--11. 1. "LWR_BASE_HW,Forms bits [n-1:0] of the start address of the address region to be translated. The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary so these bits are always 0. A write to this location is ignored by the PCIe controller." repeat.end repeat 8. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 )(list 0x0 0x200 0x400 0x600 0x800 0xA00 0xC00 0xE00 ) group.long ($2+0x10C+0xC0000)++0x3 line.long 0x0 "IATU_UPPER_BASE_ADDR_OFF_INBOUND_$1,iATU Upper Base Address Register." hexmask.long 0x0 0.--31. 1. "UPPER_BASE_RW,Forms bits [63:32] of the start (and end) address of the address region to be translated. Note: This register field is sticky." repeat.end repeat 8. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 )(list 0x0 0x200 0x400 0x600 0x800 0xA00 0xC00 0xE00 ) group.long ($2+0x110+0xC0000)++0x3 line.long 0x0 "IATU_LIMIT_ADDR_OFF_INBOUND_$1,iATU Limit Address Register." hexmask.long.tbyte 0x0 12.--31. 1. "LIMIT_ADDR_RW,Forms upper bits of the end address of the address region to be translated. Note: This register field is sticky." newline hexmask.long.word 0x0 0.--11. 1. "LIMIT_ADDR_HW,Forms lower bits of the end address of the address region to be translated. The end address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary so these bits are always all ones. A write to this location is ignored by the PCIe.." repeat.end repeat 8. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 )(list 0x0 0x200 0x400 0x600 0x800 0xA00 0xC00 0xE00 ) group.long ($2+0x114+0xC0000)++0x3 line.long 0x0 "IATU_LWR_TARGET_ADDR_OFF_INBOUND_$1,iATU Lower Target Address Register." hexmask.long.tbyte 0x0 12.--31. 1. "LWR_TARGET_RW,Forms MSB's of the Lower Target part of the new address of the translated region. These bits are always '0'. - Field size depends on log2(CX_ATU_MIN_REGION_SIZE) in address match mode. - Field size depends on log2(BAR_MASK+1) in BAR match.." newline hexmask.long.word 0x0 0.--11. 1. "LWR_TARGET_HW,Forms the LSB's of the Lower Target part of the new address of the translated region. The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary (in address match mode); and to the Bar size boundary (in BAR match mode) so.." repeat.end repeat 8. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 )(list 0x0 0x200 0x400 0x600 0x800 0xA00 0xC00 0xE00 ) group.long ($2+0x118+0xC0000)++0x3 line.long 0x0 "IATU_UPPER_TARGET_ADDR_OFF_INBOUND_$1,iATU Upper Target Address Register." hexmask.long 0x0 0.--31. 1. "UPPER_TARGET_RW,Forms bits [63:32] of the start address (Upper Target part) of the new address of the translated region. In systems with a 32-bit address space this register is not used and therefore writing to this register has no effect. Note: This.." repeat.end repeat 8. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 )(list 0x0 0x200 0x400 0x600 0x800 0xA00 0xC00 0xE00 ) group.long ($2+0x11C+0xC0000)++0x3 line.long 0x0 "IATU_REGION_CTRL_3_OFF_INBOUND_$1,iATU Region Control 3 Register." rbitfld.long 0x0 31. "VF_ACTIVE,Reserved. Not used." "0,1" newline hexmask.long 0x0 3.--30. 1. "RSVDP_VF_NUMBER,Reserved for future use." newline bitfld.long 0x0 0.--2. "VF_NUMBER,Virtual Function Number. When the Address and BAR matching logic in the controller indicates that a MEM-I/O transaction matches a BAR in the virtual function corresponding to this value then address translation proceeds. This check is only.." "0,1,2,3,4,5,6,7" repeat.end tree.end tree "PF0_PORT_LOGIC (Port Logic)" group.long (0x0+0x700)++0x27 line.long 0x0 "ACK_LATENCY_TIMER_OFF,Ack Latency Timer and Replay Timer Register." hexmask.long.word 0x0 16.--31. 1. "REPLAY_TIME_LIMIT,Replay Timer Limit. The replay timer expires when it reaches this limit. The controller initiates a replay upon reception of a NAK or when the replay timer expires. For more details see 'Transmit Replay'. You can modify the effective.." newline hexmask.long.word 0x0 0.--15. 1. "ROUND_TRIP_LATENCY_TIME_LIMIT,Ack Latency Timer Limit. The Ack latency timer expires when it reaches this limit. For more details see 'Ack Scheduling'. You can modify the effective timer limit with the TIMER_MOD_ACK_NAK field of the.." line.long 0x4 "VENDOR_SPEC_DLLP_OFF,Vendor Specific DLLP Register." hexmask.long 0x4 0.--31. 1. "VENDOR_SPEC_DLLP,Vendor Specific DLLP Register. Used to send a specific PCI Express DLLP. Your application writes the 8-bit DLLP Type and 24-bits of Payload data into this register then sets the field VENDOR_SPECIFIC_DLLP_REQ of PORT_LINK_CTRL_OFF to.." line.long 0x8 "PORT_FORCE_OFF,Port Force Link Register." hexmask.long.byte 0x8 24.--31. 1. "RSVDP_24,Reserved for future use." newline bitfld.long 0x8 23. "DO_DESKEW_FOR_SRIS,Use the transitions from TS2 to Logical Idle Symbol SKP OS to Logical Idle Symbol EIEOS to Logical Idle Symbol and FTS Sequence to SKP OS to do deskew instead of using received SKP OS or TS1 to TS2 transition if DO_DESKEW_FOR_SRIS.." "0,1" newline rbitfld.long 0x8 22. "RSVDP_22,Reserved for future use." "0,1" newline hexmask.long.byte 0x8 16.--21. 1. "LINK_STATE,Forced LTSSM State. The LTSSM state that the controller is forced to when you set the FORCE_EN bit (Force Link). LTSSM state encoding is defined by the lts_state variable in workspace/src/Layer1/smlh_ltssm.v. Note: This register field is sticky." newline bitfld.long 0x8 15. "FORCE_EN,Force Link. The controller supports a testing and debug capability to allow your software to force the LTSSM state machine into a specific state and to force the controller to transmit a specific Link Command. Asserting this bit triggers the.." "0,1" newline rbitfld.long 0x8 12.--14. "RSVDP_12,Reserved for future use." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x8 8.--11. 1. "FORCED_LTSSM,Forced Link Command. The link command that the controller is forced to transmit when you set FORCE_EN bit (Force Link). Link command encoding is defined by the ltssm_cmd variable in workspace/src/Layer1/smlh_ltssm.v. Note: This register.." newline hexmask.long.byte 0x8 0.--7. 1. "LINK_NUM,Link Number. Not used for endpoint. Not used for M-PCIe. Note: This register field is sticky." line.long 0xC "ACK_F_ASPM_CTRL_OFF,Ack Frequency and L0-L1 ASPM Control Register." rbitfld.long 0xC 31. "RSVDP_31,Reserved for future use." "0,1" newline bitfld.long 0xC 30. "ENTER_ASPM,ASPM L1 Entry Control. - 1: Controller enters ASPM L1 after a period in which it has been idle. - 0: Controller enters ASPM L1 only after idle period during which both receive and transmit are in L0s. Note: This register field is sticky." "Controller enters ASPM L1 only after idle period..,Controller enters ASPM L1 after a period in.." newline bitfld.long 0xC 27.--29. "L1_ENTRANCE_LATENCY,L1 Entrance Latency. Value range is: - 000: 1 us - 001: 2 us - 010: 4 us - 011: 8 us - 100: 16 us - 101: 32 us - 110 or 111: 64 us Note: Programming this timer with a value greater that 32us has no effect unless extended sync is used.." "0,1,2,3,4,5,6,7" newline bitfld.long 0xC 24.--26. "L0S_ENTRANCE_LATENCY,L0s Entrance Latency. Values correspond to: - 000: 1 us - 001: 2 us - 010: 3 us - 011: 4 us - 100: 5 us - 101: 6 us - 110 or 111: 7 us This field is applicable to STALL while in L0 for M-PCIe. Note: This register field is sticky." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0xC 16.--23. 1. "COMMON_CLK_N_FTS,Common Clock N_FTS. This is the N_FTS when common clock is used. The number of Fast Training Sequence ordered sets to be transmitted when transitioning from L0s to L0. The maximum number of FTS ordered-sets that a component can request.." newline hexmask.long.byte 0xC 8.--15. 1. "ACK_N_FTS,N_FTS. The number of Fast Training Sequence ordered sets to be transmitted when transitioning from L0s to L0. The maximum number of FTS ordered-sets that a component can request is 255. The controller does not support a value of zero; a value.." newline hexmask.long.byte 0xC 0.--7. 1. "ACK_FREQ,Ack Frequency. The controller accumulates the number of pending ACKs specified here (up to 255) before scheduling an ACK DLLP. - 0: Indicates that this Ack Frequency Counter feature is turned off. The controller generates a low-priority ACK.." line.long 0x10 "PORT_LINK_CTRL_OFF,Port Link Control Register." hexmask.long.byte 0x10 28.--31. 1. "RSVDP_28,Reserved for future use." newline bitfld.long 0x10 27. "TRANSMIT_LANE_REVERSALE_ENABLE,TRANSMIT_LANE_REVERSALE_ENABLE is an internally reserved field. Do not use. Note: This register field is sticky." "0,1" newline bitfld.long 0x10 26. "EXTENDED_SYNCH,EXTENDED_SYNCH is an internally reserved field. Do not use. Note: This register field is sticky." "0,1" newline bitfld.long 0x10 25. "CORRUPT_LCRC_ENABLE,CORRUPT_LCRC_ENABLE is an internally reserved field. Do not use. Note: This register field is sticky." "0,1" newline bitfld.long 0x10 24. "BEACON_ENABLE,BEACON_ENABLE is an internally reserved field. Do not use. Note: This register field is sticky." "0,1" newline hexmask.long.byte 0x10 16.--21. 1. "LINK_CAPABLE,Link Mode Enable. Sets the number of lanes in the link that you want to connect to the link partner. When you have unused lanes in your system then you must change the value in this register to reflect the number of lanes. You must also.." newline hexmask.long.byte 0x10 12.--15. 1. "RSVDP_12,Reserved for future use." newline hexmask.long.byte 0x10 8.--11. 1. "LINK_RATE,LINK_RATE is an internally reserved field. Do not use. Note: This register field is sticky." newline bitfld.long 0x10 7. "FAST_LINK_MODE,Fast Link Mode. Sets all internal LTSSM millisecond timers to Fast Mode for speeding up simulation. Forces the LTSSM training (link initialization) to use shorter time-outs and to link up faster. The default scaling factor can be changed.." "0,1" newline bitfld.long 0x10 6. "LINK_DISABLE,LINK_DISABLE is an internally reserved field. Do not use. Note: This register field is sticky." "0,1" newline bitfld.long 0x10 5. "DLL_LINK_EN,DLL Link Enable. Enables link initialization. When DLL Link Enable =0 the controller does not transmit InitFC DLLPs and does not establish a link. Note: This register field is sticky." "0,1" newline rbitfld.long 0x10 4. "RSVDP_4,Reserved for future use." "0,1" newline bitfld.long 0x10 3. "RESET_ASSERT,Reset Assert. Triggers a recovery and forces the LTSSM to the hot reset state (downstream port only). Note: This register field is sticky." "0,1" newline bitfld.long 0x10 2. "LOOPBACK_ENABLE,Loopback Enable. Turns on loopback. For more details see 'Loopback'. For M-PCIe to force the master to enter Digital Loopback mode you must set this field to '1' during Configuration.start state(initial discovery/configuration). M-PCIe.." "0,1" newline bitfld.long 0x10 1. "SCRAMBLE_DISABLE,Scramble Disable. Turns off data scrambling. Note: This register field is sticky." "0,1" newline bitfld.long 0x10 0. "VENDOR_SPECIFIC_DLLP_REQ,Vendor Specific DLLP Request. When software writes a '1' to this bit the controller transmits the DLLP contained in the VENDOR_SPEC_DLLP field of VENDOR_SPEC_DLLP_OFF. Reading from this self-clearing register field always.." "0,1" line.long 0x14 "LANE_SKEW_OFF,Lane Skew Register." bitfld.long 0x14 31. "DISABLE_LANE_TO_LANE_DESKEW,Disable Lane-to-Lane Deskew. Causes the controller to disable the internal Lane-to-Lane deskew logic. Note: This register field is sticky." "0,1" newline hexmask.long.byte 0x14 27.--30. 1. "IMPLEMENT_NUM_LANES,Implementation-specific Number of Lanes. Set the implementation-specific number of lanes. Allowed values are: - 4'b0000: 1 lane - 4'b0001: 2 lanes - 4'b0011: 4 lanes - 4'b0111: 8 lanes - 4'b1111: 16 lanes The number of lanes to be.." newline bitfld.long 0x14 26. "ELASTIC_BUFFER_MODE,Selects Elasticity Buffer operating mode: 0: Nominal Half Full Buffer mode 1: Nominal Empty Buffer Mode Note: This register field is sticky." "Nominal Half Full Buffer mode,Nominal Empty Buffer Mode" newline bitfld.long 0x14 25. "ACK_NAK_DISABLE,Ack/Nak Disable. Prevents the controller from sending ACK and NAK DLLPs. Note: This register field is sticky." "0,1" newline bitfld.long 0x14 24. "FLOW_CTRL_DISABLE,Flow Control Disable. Prevents the controller from sending FC DLLPs. Note: This register field is sticky." "0,1" newline hexmask.long.tbyte 0x14 0.--23. 1. "INSERT_LANE_SKEW,INSERT_LANE_SKEW is an internally reserved field. Do not use. Note: This register field is sticky." line.long 0x18 "TIMER_CTRL_MAX_FUNC_NUM_OFF,Timer Control and Max Function Number Register." rbitfld.long 0x18 31. "RSVDP_31,Reserved for future use." "0,1" newline bitfld.long 0x18 29.--30. "FAST_LINK_SCALING_FACTOR,Fast Link Timer Scaling Factor. Sets the scaling factor of LTSSM timer when FAST_LINK_MODE field in PORT_LINK_CTRL_OFF is set to '1'. - 0: Scaling Factor is 1024 (1ms is 1us *a) - 1: Scaling Factor is 256 (1ms is 4us) - 2:.." "Scaling Factor is 1024,Scaling Factor is 256,Scaling Factor is 64,Scaling Factor is 16" newline hexmask.long.byte 0x18 24.--28. 1. "UPDATE_FREQ_TIMER,UPDATE_FREQ_TIMER is an internally reserved field. Do not use. Note: This register field is sticky." newline hexmask.long.byte 0x18 19.--23. 1. "TIMER_MOD_ACK_NAK,Ack Latency Timer Modifier. Increases the timer value for the Ack latency timer in increments of 64 clock cycles. A value of '0' represents no modification to the timer value. For more details see the ROUND_TRIP_LATENCY_TIME_LIMIT.." newline hexmask.long.byte 0x18 14.--18. 1. "TIMER_MOD_REPLAY_TIMER,Replay Timer Limit Modifier. Increases the time-out value for the replay timer in increments of 64 clock cycles at Gen1 or Gen2 speed and in increments of 256 clock cycles at Gen3 speed. A value of '0' represents no modification.." newline hexmask.long.byte 0x18 8.--13. 1. "RSVDP_8,Reserved for future use." newline hexmask.long.byte 0x18 0.--7. 1. "MAX_FUNC_NUM,Maximum function number that can be used in a request. Configuration requests targeted at function numbers above this value are returned with UR (unsupported request). Note: This register field is sticky." line.long 0x1C "SYMBOL_TIMER_FILTER_1_OFF,Symbol Timer Register and Filter Mask 1 Register. The Filter Mask 1 Register modifies the RADM filtering and error handling rules. For more details. see the 'Receive Filtering' section. In each case. '0' applies the associated.." hexmask.long.word 0x1C 16.--31. 1. "MASK_RADM_1,Filter Mask 1. The Filter Mask 1 Register modifies the RADM filtering and error handling rules. For more details see the 'Receive Filtering' section. In each case '0' applies the associated filtering rule and '1' masks the associated.." newline bitfld.long 0x1C 15. "DISABLE_FC_WD_TIMER,Disable FC Watchdog Timer. Note: This register field is sticky." "0,1" newline hexmask.long.byte 0x1C 11.--14. 1. "EIDLE_TIMER,EIDLE_TIMER is an internally reserved field. Do not use. Note: This register field is sticky." newline hexmask.long.word 0x1C 0.--10. 1. "SKP_INT_VAL,SKP Interval Value. The number of symbol times to wait between transmitting SKP ordered sets. Note that the controller actually waits the number of symbol times in this register plus 1 between transmitting SKP ordered sets. Your application.." line.long 0x20 "FILTER_MASK_2_OFF,Filter Mask 2 Register. This register modifies the RADM filtering and error handling rules. For more details. see the 'Receive Filtering' section. In each case. '0' applies the associated filtering rule and '1' masks the associated.." hexmask.long 0x20 0.--31. 1. "MASK_RADM_2,Filter Mask 2. This field modifies the RADM filtering and error handling rules. For more details see the 'Receive Filtering' section. In each case '0' applies the associated filtering rule and '1' masks the associated filtering rule." line.long 0x24 "AMBA_MUL_OB_DECOMP_NP_SUB_REQ_CTRL_OFF,AMBA Multiple Outbound Decomposed NP SubRequests Control Register." hexmask.long 0x24 1.--31. 1. "RSVDP_1,Reserved for future use." newline bitfld.long 0x24 0. "OB_RD_SPLIT_BURST_EN,Enable AMBA Multiple Outbound Decomposed NP SubRequests. This bit when set to '0' disables the possibility of having multiple outstanding non-posted requests that were derived from decomposition of an outbound AMBA request. For more.." "0,1" rgroup.long (0x28+0x700)++0x13 line.long 0x0 "PL_DEBUG0_OFF,Debug Register 0" hexmask.long 0x0 0.--31. 1. "DEB_REG_0,The value on cxpl_debug_info[31:0]." line.long 0x4 "PL_DEBUG1_OFF,Debug Register 1" hexmask.long 0x4 0.--31. 1. "DEB_REG_1,The value on cxpl_debug_info[63:32]." line.long 0x8 "TX_P_FC_CREDIT_STATUS_OFF,Transmit Posted FC Credit Status" hexmask.long.word 0x8 20.--31. 1. "RSVDP_TX_P_FC_CREDIT_STATUS,Reserved for future use." newline hexmask.long.byte 0x8 12.--19. 1. "TX_P_HEADER_FC_CREDIT,Transmit Posted Header FC Credits. The posted Header credits advertised by the receiver at the other end of the link updated with each UpdateFC DLLP. Default value depends on the number of advertised credits for header and data.." newline hexmask.long.word 0x8 0.--11. 1. "TX_P_DATA_FC_CREDIT,Transmit Posted Data FC Credits. The posted Data credits advertised by the receiver at the other end of the link updated with each UpdateFC DLLP. Default value depends on the number of advertised credits for header and data Scaled.." line.long 0xC "TX_NP_FC_CREDIT_STATUS_OFF,Transmit Non-Posted FC Credit Status" hexmask.long.word 0xC 20.--31. 1. "RSVDP_TX_NP_FC_CREDIT_STATUS,Reserved for future use." newline hexmask.long.byte 0xC 12.--19. 1. "TX_NP_HEADER_FC_CREDIT,Transmit Non-Posted Header FC Credits. The non-posted Header credits advertised by the receiver at the other end of the link updated with each UpdateFC DLLP. Default value depends on the number of advertised credits for header and.." newline hexmask.long.word 0xC 0.--11. 1. "TX_NP_DATA_FC_CREDIT,Transmit Non-Posted Data FC Credits. The non-posted Data credits advertised by the receiver at the other end of the link updated with each UpdateFC DLLP. Default value depends on the number of advertised credits for header and data.." line.long 0x10 "TX_CPL_FC_CREDIT_STATUS_OFF,Transmit Completion FC Credit Status" hexmask.long.word 0x10 20.--31. 1. "RSVDP_TX_CPL_FC_CREDIT_STATUS,Reserved for future use." newline hexmask.long.byte 0x10 12.--19. 1. "TX_CPL_HEADER_FC_CREDIT,Transmit Completion Header FC Credits. The Completion Header credits advertised by the receiver at the other end of the link updated with each UpdateFC DLLP. Default value depends on the number of advertised credits for header.." newline hexmask.long.word 0x10 0.--11. 1. "TX_CPL_DATA_FC_CREDIT,Transmit Completion Data FC Credits. The Completion Data credits advertised by the receiver at the other end of the link updated with each UpdateFC DLLP. Default value depends on the number of advertised credits for header and data.." group.long (0x3C+0x700)++0x3 line.long 0x0 "QUEUE_STATUS_OFF,Queue Status" bitfld.long 0x0 31. "TIMER_MOD_FLOW_CONTROL_EN,FC Latency Timer Override Enable. When this bit is set the value from the 'FC Latency Timer Override Value' field in this register will override the FC latency timer value that the controller calculates according to the PCIe.." "0,1" newline rbitfld.long 0x0 29.--30. "RSVDP_29,Reserved for future use." "0,1,2,3" newline hexmask.long.word 0x0 16.--28. 1. "TIMER_MOD_FLOW_CONTROL,FC Latency Timer Override Value. When you set the 'FC Latency Timer Override Enable' in this register the value in this field will override the FC latency timer value that the controller calculates according to the PCIe.." newline rbitfld.long 0x0 13. "RX_SERIALIZATION_Q_NON_EMPTY,Receive Serialization Queue Not Empty. Indicates there is data in the serialization queue." "0,1" newline hexmask.long.word 0x0 4.--12. 1. "RSVDP_4,Reserved for future use." newline bitfld.long 0x0 3. "RX_QUEUE_OVERFLOW,Receive Credit Queue Overflow. Indicates insufficient buffer space available to write to the P/NP/CPL credit queue." "0,1" newline rbitfld.long 0x0 2. "RX_QUEUE_NON_EMPTY,Receive Credit Queue Not Empty. Indicates there is data in one or more of the receive buffers." "0,1" newline rbitfld.long 0x0 1. "TX_RETRY_BUFFER_NE,Transmit Retry Buffer Not Empty. Indicates that there is data in the transmit retry buffer." "0,1" newline rbitfld.long 0x0 0. "RX_TLP_FC_CREDIT_NON_RETURN,Received TLP FC Credits Not Returned. Indicates that the controller has received a TLP but has not yet sent an UpdateFC DLLP indicating that the credits for that TLP have been restored by the receiver at the other end of the.." "0,1" rgroup.long (0x40+0x700)++0x7 line.long 0x0 "VC_TX_ARBI_1_OFF,VC Transmit Arbitration Register 1" hexmask.long.byte 0x0 24.--31. 1. "WRR_WEIGHT_VC_3,WRR Weight for VC3. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R" newline hexmask.long.byte 0x0 16.--23. 1. "WRR_WEIGHT_VC_2,WRR Weight for VC2. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R" newline hexmask.long.byte 0x0 8.--15. 1. "WRR_WEIGHT_VC_1,WRR Weight for VC1. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R" newline hexmask.long.byte 0x0 0.--7. 1. "WRR_WEIGHT_VC_0,WRR Weight for VC0. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R" line.long 0x4 "VC_TX_ARBI_2_OFF,VC Transmit Arbitration Register 2" hexmask.long.byte 0x4 24.--31. 1. "WRR_WEIGHT_VC_7,WRR Weight for VC7. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R" newline hexmask.long.byte 0x4 16.--23. 1. "WRR_WEIGHT_VC_6,WRR Weight for VC6. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R" newline hexmask.long.byte 0x4 8.--15. 1. "WRR_WEIGHT_VC_5,WRR Weight for VC5. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R" newline hexmask.long.byte 0x4 0.--7. 1. "WRR_WEIGHT_VC_4,WRR Weight for VC4. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R" group.long (0x48+0x700)++0xB line.long 0x0 "VC0_P_RX_Q_CTRL_OFF,Segmented-Buffer VC0 Posted Receive Queue Control." bitfld.long 0x0 31. "VC_ORDERING_RX_Q,VC Ordering for Receive Queues. Determines the VC ordering rule for the receive queues used only in the segmented-buffer configuration: - 1: Strict ordering higher numbered VCs have higher priority - 0: Round robin Note: This register.." "Round robin,Strict ordering" newline bitfld.long 0x0 30. "TLP_TYPE_ORDERING_VC0,TLP Type Ordering for VC0. Determines the TLP type ordering rule for VC0 receive queues used only in the segmented-buffer configuration: - 1: PCIe ordering rules (recommended) - 0: Strict ordering: posted completion then.." "Strict ordering: posted,PCIe ordering rules" newline bitfld.long 0x0 28.--29. "RESERVED5,Reserved. Note: This register field is sticky." "0,1,2,3" newline bitfld.long 0x0 26.--27. "VC0_P_DATA_SCALE,VC0 Scale Posted Data Credites. Note: This register field is sticky." "0,1,2,3" newline bitfld.long 0x0 24.--25. "VC0_P_HDR_SCALE,VC0 Scale Posted Header Credites. Note: This register field is sticky." "0,1,2,3" newline bitfld.long 0x0 21.--23. "VC0_P_TLP_Q_MODE,Reserved. Note: This register field is sticky." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 20. "RESERVED4,Reserved. Note: This register field is sticky." "0,1" newline hexmask.long.byte 0x0 12.--19. 1. "VC0_P_HEADER_CREDIT,VC0 Posted Header Credits. The number of initial posted header credits for VC0 used only in the segmented-buffer configuration. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R (sticky) Note: This.." newline hexmask.long.word 0x0 0.--11. 1. "VC0_P_DATA_CREDIT,VC0 Posted Data Credits. The number of initial posted data credits for VC0 used only in the segmented-buffer configuration. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R (sticky) Note: This.." line.long 0x4 "VC0_NP_RX_Q_CTRL_OFF,Segmented-Buffer VC0 Non-Posted Receive Queue Control." hexmask.long.byte 0x4 28.--31. 1. "RESERVED7,Reserved. Note: This register field is sticky." newline bitfld.long 0x4 26.--27. "VC0_NP_DATA_SCALE,VC0 Scale Non-Posted Data Credites. Note: This register field is sticky." "0,1,2,3" newline bitfld.long 0x4 24.--25. "VC0_NP_HDR_SCALE,VC0 Scale Non-Posted Header Credites. Note: This register field is sticky." "0,1,2,3" newline bitfld.long 0x4 21.--23. "VC0_NP_TLP_Q_MODE,Reserved. Note: This register field is sticky." "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 20. "RESERVED6,Reserved. Note: This register field is sticky." "0,1" newline hexmask.long.byte 0x4 12.--19. 1. "VC0_NP_HEADER_CREDIT,VC0 Non-Posted Header Credits. The number of initial non-posted header credits for VC0 used only in the segmented-buffer configuration. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R (sticky).." newline hexmask.long.word 0x4 0.--11. 1. "VC0_NP_DATA_CREDIT,VC0 Non-Posted Data Credits. The number of initial non-posted data credits for VC0 used only in the segmented-buffer configuration. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R (sticky) Note:.." line.long 0x8 "VC0_CPL_RX_Q_CTRL_OFF,Segmented-Buffer VC0 Completion Receive Queue Control." hexmask.long.byte 0x8 28.--31. 1. "RESERVED9,Reserved. Note: This register field is sticky." newline bitfld.long 0x8 26.--27. "VC0_CPL_DATA_SCALE,VC0 Scale CPL Data Credites. Note: This register field is sticky." "0,1,2,3" newline bitfld.long 0x8 24.--25. "VC0_CPL_HDR_SCALE,VC0 Scale CPL Header Credites. Note: This register field is sticky." "0,1,2,3" newline bitfld.long 0x8 21.--23. "VC0_CPL_TLP_Q_MODE,Reserved. Note: This register field is sticky." "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 20. "RESERVED8,Reserved. Note: This register field is sticky." "0,1" newline hexmask.long.byte 0x8 12.--19. 1. "VC0_CPL_HEADER_CREDIT,VC0 Completion Header Credits. The number of initial Completion header credits for VC0 used only in the segmented-buffer configuration. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R (sticky).." newline hexmask.long.word 0x8 0.--11. 1. "VC0_CPL_DATA_CREDIT,VC0 Completion Data Credits. The number of initial Completion data credits for VC0 used only in the segmented-buffer configuration. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R (sticky) Note:.." group.long (0x10C+0x700)++0x3 line.long 0x0 "GEN2_CTRL_OFF,This register is used to control various functions of the controller related to link training. lane reversal. and equalization." rbitfld.long 0x0 31. "RSVDP_31,Reserved for future use." "0,1" newline bitfld.long 0x0 30. "FORCE_LANE_FLIP,Enable to force the LANE_UNDER_TEST physical lane flips to logical lane 0. All the other physical lanes are turned off. The LINK_CAPABLE register must be set to 1 and only x1 link can be formed if the FORCE_LANE_FLIP register is set to 1." "0,1" newline hexmask.long.byte 0x0 24.--27. 1. "LANE_UNDER_TEST,The Lane Under Test is the lane for Forced Lane Flip or for Loopback Eq. The value is from 0 to CX_NL. Only one lane is configured each time. The default of this field is the CX_DEFAULT_LANE_UNDER_TEST configuration parameter. This field.." newline rbitfld.long 0x0 22.--23. "RSVDP_22,Reserved for future use." "0,1,2,3" newline bitfld.long 0x0 21. "GEN1_EI_INFERENCE,Electrical Idle Inference Mode at Gen1 Rate. Programmable mode to determine inferred electrical idle (EI) in Recovery.Speed or Loopback.Active (as slave) state at Gen1 speed by looking for a '1' value on RxElecIdle instead of looking.." "Use RxElecIdle signal to infer Electrical Idle,Use RxValid signal to infer Electrical Idle" newline bitfld.long 0x0 20. "SEL_DEEMPHASIS,Used to set the de-emphasis level for upstream ports. This bit selects the level of de-emphasis the link operates at. - 0: -6 dB - 1: -3.5 dB This field is reserved (fixed to '0') for M-PCIe. Note: The access attributes of this field are.." "0,1" newline bitfld.long 0x0 19. "CONFIG_TX_COMP_RX,Config Tx Compliance Receive Bit. When set to 1 signals LTSSM to transmit TS ordered sets with the compliance receive bit assert (equal to '1'). This field is reserved (fixed to '0') for M-PCIe. Note: The access attributes of this.." "0,1" newline bitfld.long 0x0 18. "CONFIG_PHY_TX_CHANGE,Config PHY Tx Swing. Controls the PHY transmitter voltage swing level. The controller drives the mac_phy_txswing output from this register bit field. - 0: Full Swing - 1: Low Swing This field is reserved (fixed to '0') for M-PCIe." "Full Swing,Low Swing" newline bitfld.long 0x0 17. "DIRECT_SPEED_CHANGE,Directed Speed Change. Writing '1' to this field instructs the LTSSM to initiate a speed change to Gen2 or Gen3 after the link is initialized at Gen1 speed. When the speed change occurs the controller will clear the contents of this.." "0,1" newline bitfld.long 0x0 16. "AUTO_LANE_FLIP_CTRL_EN,Enable Auto flipping of the lanes. You must set the CX_AUTO_LANE_FLIP_CTRL_EN configuration parameter to include the hardware for this feature in the controller. For more details see the 'Lane Reversal' appendix in the Databook." "0,1" newline bitfld.long 0x0 13.--15. "PRE_DET_LANE,Predetermined Lane for Auto Flip. This field defines which physical lane is connected to logical Lane0 by the flip operation performed in Detect. This field is used to restrict the receiver detect procedure to a particular lane when the.." "LANE0,LANE1,LANE3,LANE7,LANE15,?,?,?" newline hexmask.long.byte 0x0 8.--12. 1. "NUM_OF_LANES,Predetermined Number of Lanes. Defines the number of lanes which are connected and not bad. Used to limit the effective link width to ignore 'broken' or 'unused' lanes that detect a receiver. Indicates the number of lanes to check for exit.." newline hexmask.long.byte 0x0 0.--7. 1. "FAST_TRAINING_SEQ,Sets the Number of Fast Training Sequences (N_FTS) that the controller advertises as its N_FTS during Gen2 or Gen3 link training. This value is used to inform the link partner about the PHY's ability to recover synchronization after a.." rgroup.long (0x110+0x700)++0x3 line.long 0x0 "PHY_STATUS_OFF,PHY Status Register. Memory mapped register from phy_cfg_status GPIO input pins." hexmask.long 0x0 0.--31. 1. "PHY_STATUS,PHY Status. Data received directly from the phy_cfg_status bus. These is a GPIO register reflecting the values on the static phy_cfg_status input signals. The usage is left completely to the user and does not in any way influence controller.." group.long (0x114+0x700)++0x3 line.long 0x0 "PHY_CONTROL_OFF,PHY Control Register. Memory mapped register to cfg_phy_control GPIO output pins." hexmask.long 0x0 0.--31. 1. "PHY_CONTROL,PHY Control. Data sent directly to the cfg_phy_control bus. These is a GPIO register driving the values on the static cfg_phy_control output signals. The usage is left completely to the user and does not in any way influence controller.." group.long (0x11C+0x700)++0x77 line.long 0x0 "TRGT_MAP_CTRL_OFF,Programmable Target Map Control Register." hexmask.long.word 0x0 21.--31. 1. "TARGET_MAP_RESERVED_21_31,Reserved. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R (sticky)" newline hexmask.long.byte 0x0 16.--20. 1. "TARGET_MAP_INDEX,The number of the PF Function on which the Target Values are set. This register does not respect the Byte Enable setting. any write will affect all register bits." newline rbitfld.long 0x0 13.--15. "TARGET_MAP_RESERVED_13_15,Reserved. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R (sticky)" "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x0 7.--12. 1. "TARGET_MAP_VF,Target Values for each BAR on the VF Function selected by the index number. This register does not respect the Byte Enable setting. any write will affect all register bits." newline bitfld.long 0x0 6. "TARGET_MAP_ROM,Target Value for the ROM page of the PF Function selected by the index number. This register does not respect the Byte Enable setting. any write will affect all register bits." "0,1" newline hexmask.long.byte 0x0 0.--5. 1. "TARGET_MAP_PF,Target Values for each BAR on the PF Function selected by the index number. This register does not respect the Byte Enable setting. any write will affect all register bits." line.long 0x4 "MSI_CTRL_ADDR_OFF,Integrated MSI Reception Module (iMRM) Address Register." hexmask.long 0x4 0.--31. 1. "MSI_CTRL_ADDR,Integrated MSI Reception Module Address. System specified address for MSI memory write transaction termination. Within the AXI Bridge every received Memory Write request is examined to see if it targets the MSI Address that has been.." line.long 0x8 "MSI_CTRL_UPPER_ADDR_OFF,Integrated MSI Reception Module Upper Address Register." hexmask.long 0x8 0.--31. 1. "MSI_CTRL_UPPER_ADDR,Integrated MSI Reception Module Upper Address. System specified upper address for MSI memory write transaction termination. Allows functions to support a 64-bit MSI address. Note: This register field is sticky." line.long 0xC "MSI_CTRL_INT_0_EN_OFF,Integrated MSI Reception Module Interrupt#i Enable Register." hexmask.long 0xC 0.--31. 1. "MSI_CTRL_INT_0_EN,MSI Interrupt#i Enable. Specifies which interrupts are enabled. When an MSI is received from a disabled interrupt no status bit gets set in MSI controller interrupt status register. Each bit corresponds to a single MSI Interrupt.." line.long 0x10 "MSI_CTRL_INT_0_MASK_OFF,Integrated MSI Reception Module Interrupt#i Mask Register." hexmask.long 0x10 0.--31. 1. "MSI_CTRL_INT_0_MASK,MSI Interrupt#i Mask. Allows enabled interrupts to be masked. When an MSI is received for a masked interrupt the corresponding status bit gets set in the interrupt status register but the msi_ctrl_int output is not set HIGH. Each bit.." line.long 0x14 "MSI_CTRL_INT_0_STATUS_OFF,Integrated MSI Reception Module Interrupt#i Status Register." hexmask.long 0x14 0.--31. 1. "MSI_CTRL_INT_0_STATUS,MSI Interrupt#i Status. When an MSI is detected for EP#i one bit in this register is set. The decoding of the data payload of the MSI Memory Write request determines which bit gets set. A status is bit is cleared by writing a 1 to.." line.long 0x18 "MSI_CTRL_INT_1_EN_OFF,Integrated MSI Reception Module Interrupt#i Enable Register." hexmask.long 0x18 0.--31. 1. "MSI_CTRL_INT_1_EN,MSI Interrupt#i Enable. Specifies which interrupts are enabled. When an MSI is received from a disabled interrupt no status bit gets set in MSI controller interrupt status register. Each bit corresponds to a single MSI Interrupt.." line.long 0x1C "MSI_CTRL_INT_1_MASK_OFF,Integrated MSI Reception Module Interrupt#i Mask Register." hexmask.long 0x1C 0.--31. 1. "MSI_CTRL_INT_1_MASK,MSI Interrupt#i Mask. Allows enabled interrupts to be masked. When an MSI is received for a masked interrupt the corresponding status bit gets set in the interrupt status register but the msi_ctrl_int output is not set HIGH. Each bit.." line.long 0x20 "MSI_CTRL_INT_1_STATUS_OFF,Integrated MSI Reception Module Interrupt#i Status Register." hexmask.long 0x20 0.--31. 1. "MSI_CTRL_INT_1_STATUS,MSI Interrupt#i Status. When an MSI is detected for EP#i one bit in this register is set. The decoding of the data payload of the MSI Memory Write request determines which bit gets set. A status is bit is cleared by writing a 1 to.." line.long 0x24 "MSI_CTRL_INT_2_EN_OFF,Integrated MSI Reception Module Interrupt#i Enable Register." hexmask.long 0x24 0.--31. 1. "MSI_CTRL_INT_2_EN,MSI Interrupt#i Enable. Specifies which interrupts are enabled. When an MSI is received from a disabled interrupt no status bit gets set in MSI controller interrupt status register. Each bit corresponds to a single MSI Interrupt.." line.long 0x28 "MSI_CTRL_INT_2_MASK_OFF,Integrated MSI Reception Module Interrupt#i Mask Register." hexmask.long 0x28 0.--31. 1. "MSI_CTRL_INT_2_MASK,MSI Interrupt#i Mask. Allows enabled interrupts to be masked. When an MSI is received for a masked interrupt the corresponding status bit gets set in the interrupt status register but the msi_ctrl_int output is not set HIGH. Each bit.." line.long 0x2C "MSI_CTRL_INT_2_STATUS_OFF,Integrated MSI Reception Module Interrupt#i Status Register." hexmask.long 0x2C 0.--31. 1. "MSI_CTRL_INT_2_STATUS,MSI Interrupt#i Status. When an MSI is detected for EP#i one bit in this register is set. The decoding of the data payload of the MSI Memory Write request determines which bit gets set. A status is bit is cleared by writing a 1 to.." line.long 0x30 "MSI_CTRL_INT_3_EN_OFF,Integrated MSI Reception Module Interrupt#i Enable Register." hexmask.long 0x30 0.--31. 1. "MSI_CTRL_INT_3_EN,MSI Interrupt#i Enable. Specifies which interrupts are enabled. When an MSI is received from a disabled interrupt no status bit gets set in MSI controller interrupt status register. Each bit corresponds to a single MSI Interrupt.." line.long 0x34 "MSI_CTRL_INT_3_MASK_OFF,Integrated MSI Reception Module Interrupt#i Mask Register." hexmask.long 0x34 0.--31. 1. "MSI_CTRL_INT_3_MASK,MSI Interrupt#i Mask. Allows enabled interrupts to be masked. When an MSI is received for a masked interrupt the corresponding status bit gets set in the interrupt status register but the msi_ctrl_int output is not set HIGH. Each bit.." line.long 0x38 "MSI_CTRL_INT_3_STATUS_OFF,Integrated MSI Reception Module Interrupt#i Status Register." hexmask.long 0x38 0.--31. 1. "MSI_CTRL_INT_3_STATUS,MSI Interrupt#i Status. When an MSI is detected for EP#i one bit in this register is set. The decoding of the data payload of the MSI Memory Write request determines which bit gets set. A status is bit is cleared by writing a 1 to.." line.long 0x3C "MSI_CTRL_INT_4_EN_OFF,Integrated MSI Reception Module Interrupt#i Enable Register." hexmask.long 0x3C 0.--31. 1. "MSI_CTRL_INT_4_EN,MSI Interrupt#i Enable. Specifies which interrupts are enabled. When an MSI is received from a disabled interrupt no status bit gets set in MSI controller interrupt status register. Each bit corresponds to a single MSI Interrupt.." line.long 0x40 "MSI_CTRL_INT_4_MASK_OFF,Integrated MSI Reception Module Interrupt#i Mask Register." hexmask.long 0x40 0.--31. 1. "MSI_CTRL_INT_4_MASK,MSI Interrupt#i Mask. Allows enabled interrupts to be masked. When an MSI is received for a masked interrupt the corresponding status bit gets set in the interrupt status register but the msi_ctrl_int output is not set HIGH. Each bit.." line.long 0x44 "MSI_CTRL_INT_4_STATUS_OFF,Integrated MSI Reception Module Interrupt#i Status Register." hexmask.long 0x44 0.--31. 1. "MSI_CTRL_INT_4_STATUS,MSI Interrupt#i Status. When an MSI is detected for EP#i one bit in this register is set. The decoding of the data payload of the MSI Memory Write request determines which bit gets set. A status is bit is cleared by writing a 1 to.." line.long 0x48 "MSI_CTRL_INT_5_EN_OFF,Integrated MSI Reception Module Interrupt#i Enable Register." hexmask.long 0x48 0.--31. 1. "MSI_CTRL_INT_5_EN,MSI Interrupt#i Enable. Specifies which interrupts are enabled. When an MSI is received from a disabled interrupt no status bit gets set in MSI controller interrupt status register. Each bit corresponds to a single MSI Interrupt.." line.long 0x4C "MSI_CTRL_INT_5_MASK_OFF,Integrated MSI Reception Module Interrupt#i Mask Register." hexmask.long 0x4C 0.--31. 1. "MSI_CTRL_INT_5_MASK,MSI Interrupt#i Mask. Allows enabled interrupts to be masked. When an MSI is received for a masked interrupt the corresponding status bit gets set in the interrupt status register but the msi_ctrl_int output is not set HIGH. Each bit.." line.long 0x50 "MSI_CTRL_INT_5_STATUS_OFF,Integrated MSI Reception Module Interrupt#i Status Register." hexmask.long 0x50 0.--31. 1. "MSI_CTRL_INT_5_STATUS,MSI Interrupt#i Status. When an MSI is detected for EP#i one bit in this register is set. The decoding of the data payload of the MSI Memory Write request determines which bit gets set. A status is bit is cleared by writing a 1 to.." line.long 0x54 "MSI_CTRL_INT_6_EN_OFF,Integrated MSI Reception Module Interrupt#i Enable Register." hexmask.long 0x54 0.--31. 1. "MSI_CTRL_INT_6_EN,MSI Interrupt#i Enable. Specifies which interrupts are enabled. When an MSI is received from a disabled interrupt no status bit gets set in MSI controller interrupt status register. Each bit corresponds to a single MSI Interrupt.." line.long 0x58 "MSI_CTRL_INT_6_MASK_OFF,Integrated MSI Reception Module Interrupt#i Mask Register." hexmask.long 0x58 0.--31. 1. "MSI_CTRL_INT_6_MASK,MSI Interrupt#i Mask. Allows enabled interrupts to be masked. When an MSI is received for a masked interrupt the corresponding status bit gets set in the interrupt status register but the msi_ctrl_int output is not set HIGH. Each bit.." line.long 0x5C "MSI_CTRL_INT_6_STATUS_OFF,Integrated MSI Reception Module Interrupt#i Status Register." hexmask.long 0x5C 0.--31. 1. "MSI_CTRL_INT_6_STATUS,MSI Interrupt#i Status. When an MSI is detected for EP#i one bit in this register is set. The decoding of the data payload of the MSI Memory Write request determines which bit gets set. A status is bit is cleared by writing a 1 to.." line.long 0x60 "MSI_CTRL_INT_7_EN_OFF,Integrated MSI Reception Module Interrupt#i Enable Register." hexmask.long 0x60 0.--31. 1. "MSI_CTRL_INT_7_EN,MSI Interrupt#i Enable. Specifies which interrupts are enabled. When an MSI is received from a disabled interrupt no status bit gets set in MSI controller interrupt status register. Each bit corresponds to a single MSI Interrupt.." line.long 0x64 "MSI_CTRL_INT_7_MASK_OFF,Integrated MSI Reception Module Interrupt#i Mask Register." hexmask.long 0x64 0.--31. 1. "MSI_CTRL_INT_7_MASK,MSI Interrupt#i Mask. Allows enabled interrupts to be masked. When an MSI is received for a masked interrupt the corresponding status bit gets set in the interrupt status register but the msi_ctrl_int output is not set HIGH. Each bit.." line.long 0x68 "MSI_CTRL_INT_7_STATUS_OFF,Integrated MSI Reception Module Interrupt#i Status Register." hexmask.long 0x68 0.--31. 1. "MSI_CTRL_INT_7_STATUS,MSI Interrupt#i Status. When an MSI is detected for EP#i one bit in this register is set. The decoding of the data payload of the MSI Memory Write request determines which bit gets set. A status is bit is cleared by writing a 1 to.." line.long 0x6C "MSI_GPIO_IO_OFF,Integrated MSI Reception Module General Purpose IO Register." hexmask.long 0x6C 0.--31. 1. "MSI_GPIO_REG,MSI GPIO Register. The contents of this register drives the top-level GPIO msi_ctrl_io[31:0] Note: This register field is sticky." line.long 0x70 "CLOCK_GATING_CTRL_OFF,This register enables you to disable dynamic clock gating. By default dynamic clock gating is on. allowing the controller to autonomously enable and disable its clocks. The clock gating is performed in the clock and reset module." hexmask.long 0x70 2.--31. 1. "RSVDP_2,Reserved for future use." newline bitfld.long 0x70 1. "AXI_CLK_GATING_EN,AXI Clock Gating Enable. This register enables the AXI Bridge to autonomously enable and disable the AXI Master clock the AXI Slave clock and the AXI DBI slave clock. The DWC_pcie_clk_rst.v module provides the gated clock.." "Disable,Enable" newline bitfld.long 0x70 0. "RADM_CLK_GATING_EN,RADM Clock Gating Enable. This register if set enables the RADM to autonomously enable and disable its clock. The DWC_pcie_clk_rst.v module provides the gated clock radm_clk_g to the RADM and is enabled when the controllers clock.." "Disable,Enable" line.long 0x74 "GEN3_RELATED_OFF,Gen3 Control Register. There is no Gen3-specific N_FTS field. The N_FTS field in the 'Link Width and Speed Change Control Register' is used for both Gen2 and Gen3 speed modes. There is no Gen3-specific 'Directed Speed Change' field. The.." hexmask.long.byte 0x74 26.--31. 1. "RSVDP_26,Reserved for future use." newline bitfld.long 0x74 23. "GEN3_EQ_INVREQ_EVAL_DIFF_DISABLE,Eq InvalidRequest and RxEqEval Different Time Assertion Disable. Disable the assertion of Eq InvalidRequest and RxEqEval at different time. Note: When CX_GEN4_SPEED/CX_GEN5_SPEED this register is shared for Gen3 and.." "0,1" newline rbitfld.long 0x74 19.--20. "RSVDP_19,Reserved for future use." "0,1,2,3" newline bitfld.long 0x74 18. "GEN3_DC_BALANCE_DISABLE,DC Balance Disable. Disable DC Balance feature. Note: When CX_GEN4_SPEED/CX_GEN5_SPEED this register is shared for Gen3 and Gen4/Gen5 data rate. Note: This register field is sticky." "0,1" newline bitfld.long 0x74 17. "GEN3_DLLP_XMT_DELAY_DISABLE,DLLP Transmission Delay Disable. Disable delay transmission of DLLPs before equalization. Note: When CX_GEN4_SPEED/CX_GEN5_SPEED this register is shared for Gen3 and Gen4/Gen5 data rate. Note: This register field is sticky." "0,1" newline bitfld.long 0x74 16. "GEN3_EQUALIZATION_DISABLE,Equalization Disable. Disable equalization feature. This bit cannot be changed once the LTSSM starts link training. Note: When CX_GEN4_SPEED/CX_GEN5_SPEED this register is shared for Gen3 and Gen4/Gen5 data rate. Note: This.." "0,1" newline rbitfld.long 0x74 14.--15. "RSVDP_14,Reserved for future use." "0,1,2,3" newline bitfld.long 0x74 13. "RXEQ_RGRDLESS_RXTS,When set to '1' the controller as Gen3 EQ master asserts RxEqEval to instruct the PHY to do Rx adaptation and evaluation after a 500ns timeout from a new preset request. - 0: mac_phy_rxeqeval asserts after 1us and 2 TS1 received from.." "mac_phy_rxeqeval asserts after 1us and 2 TS1..,mac_phy_rxeqeval asserts after 500ns regardless.." newline bitfld.long 0x74 12. "RXEQ_PH01_EN,Rx Equalization Phase 0/Phase 1 Hold Enable. When this bit is set the upstream port holds phase 0 (the downstream port holds phase 1) for 10ms. Holding phase 0 or phase 1 can be used to allow sufficient time for Rx Equalization to be.." "Tx equalization only in phase 2/3,No Tx equalization" newline bitfld.long 0x74 11. "EQ_REDO,Equalization Redo Disable. Disable autonomous mechanism for requesting to redo the equalization process. The received presets or coefficients mismatch in Recovery.RcvrLock after Recovery EQ phases causes the EQ redo requests. If the EQ redo is.." "0,1" newline bitfld.long 0x74 10. "EQ_EIEOS_CNT,Equalization EIEOS Count Reset Disable. Disable requesting reset of EIEOS count during equalization. Note: When CX_GEN4_SPEED/CX_GEN5_SPEED this register is shared for Gen3 and Gen4/Gen5 data rate. Note: This register field is sticky." "0,1" newline bitfld.long 0x74 9. "EQ_PHASE_2_3,Equalization Phase 2 and Phase 3 Disable. This applies to downstream ports only. Note: When CX_GEN4_SPEED/CX_GEN5_SPEED this register is shadow register for Gen3 and Gen4/Gen5 data rate. If RATE_SHADOW_SEL==00b this register is for Gen3.." "0,1" newline bitfld.long 0x74 8. "DISABLE_SCRAMBLER_GEN_3,Disable Scrambler for Gen3 and Gen4 Data Rate. The Gen3 and Gen4 scrambler/descrambler within the controller needs to be disabled when the scrambling function is implemented outside of the controller (for example within the PHY)." "0,1" newline hexmask.long.byte 0x74 1.--7. 1. "RSVDP_1,Reserved for future use." newline bitfld.long 0x74 0. "GEN3_ZRXDC_NONCOMPL,Gen3 Receiver Impedance ZRX-DC Not Compliant. Receivers that operate at 8.0 GT/s with an impedance other than the range defined by the ZRX-DC parameter for 2.5 GT/s (40-60 Ohms) must meet additional behavior requirements in the.." "The receiver complies with the ZRX-DC parameter..,The receiver does not comply with the ZRX-DC.." group.long (0x1A8+0x700)++0x7 line.long 0x0 "GEN3_EQ_CONTROL_OFF,Gen3 EQ Control Register. This register controls equalization for Phase2 in an upstream port (USP). or Phase3 in a downstream port (DSP). M-PCIe doesn't have Conventional PCIe Gen3 feature. The registers of this section do not exist." hexmask.long.byte 0x0 27.--31. 1. "RSVDP_27,Reserved for future use." newline bitfld.long 0x0 26. "GEN3_REQ_SEND_CONSEC_EIEOS_FOR_PSET_MAP,Request controller to send back-to-back EIEOS in Recovery.RcvrLock state until presets to coefficients mapping is complete. - 0: Do not request - 1: request Note: Gen3 and Gen4 share the same register bit and have.." "Do not request,request" newline bitfld.long 0x0 25. "GEN3_EQ_PSET_REQ_AS_COEF,GEN3_EQ_PSET_REQ_AS_COEF is an internally reserved field. Do not use. Note: This register field is sticky." "0,1" newline bitfld.long 0x0 24. "GEN3_EQ_FOM_INC_INITIAL_EVAL,Include Initial FOM. Include or not the FOM feedback from the initial preset evaluation performed in the EQ Master when finding the highest FOM among all preset evaluations. - 0: Do not include - 1: Include Note: When.." "Do not include,Include" newline hexmask.long.word 0x0 8.--23. 1. "GEN3_EQ_PSET_REQ_VEC,Preset Request Vector. Requesting of Presets during the initial part of the EQ Master Phase. Encoding scheme is as follows: Bit [15:0] =0x0: No preset is requested and evaluated in EQ Master Phase. Bit [i] =1: 'Preset=i' is requested.." newline rbitfld.long 0x0 7. "RSVDP_7,Reserved for future use." "0,1" newline bitfld.long 0x0 6. "GEN3_LOWER_RATE_EQ_REDO_ENABLE,Support EQ redo and lower rate change: - 0: not support - 1: support Note: Gen3 and Gen4 share the same register bit and have the same feature. Note: This register field is sticky." "not support,support" newline bitfld.long 0x0 5. "GEN3_EQ_EVAL_2MS_DISABLE,Phase2_3 2 ms Timeout Disable. Determine behavior in Phase2 for USP (Phase3 if DSP) when the PHY does not respond within 2ms to the assertion of RxEqEval: - 0: abort the current evaluation stop any attempt to modify the remote.." "abort the current evaluation,ignore the 2ms timeout and continue as normal" newline bitfld.long 0x0 4. "GEN3_EQ_PHASE23_EXIT_MODE,Behavior After 24 ms Timeout (when optimal settings are not found). For a USP: Determine next LTSSM state from Phase2 after 24ms Timeout - 0: Recovery.Speed - 1: Recovery.Equalization.Phase3 When optimal settings are not found.." "Equalization Phase 3 Successful status bit is..,Recovery" newline hexmask.long.byte 0x0 0.--3. 1. "GEN3_EQ_FB_MODE,Feedback Mode. - 0000b: Direction Change - 0001b: Figure Of Merit - 0010b: Reserved - .....: Reserved - 1111b: Reserved Note: When CX_GEN4_SPEED/CX_GEN5_SPEED this register is a shadow register for Gen3 and Gen4/Gen5 data rate. If.." line.long 0x4 "GEN3_EQ_FB_MODE_DIR_CHANGE_OFF,Gen3 EQ Direction Change Feedback Mode Control Register. Equalization controls to be used in Phase2 (USP) or Phase 3 (DSP). when you set the Feedback Mode in 'Gen3 EQ Control Register' to 'Direction Change.' These fields.." hexmask.long.word 0x4 18.--31. 1. "RSVDP_18,Reserved for future use." newline hexmask.long.byte 0x4 14.--17. 1. "GEN3_EQ_FMDC_MAX_POST_CUSROR_DELTA,Convergence Window Aperture for C+1. Post-cursor coefficients maximum delta within the convergence window depth. Allowed range: 0 1 2 ..15. Note: When CX_GEN4_SPEED/CX_GEN5_SPEED this register is shadow register for.." newline hexmask.long.byte 0x4 10.--13. 1. "GEN3_EQ_FMDC_MAX_PRE_CUSROR_DELTA,Convergence Window Aperture for C-1. Pre-cursor coefficients maximum delta within the convergence window depth. Allowed range: 0 1 2 ..15. Note: When CX_GEN4_SPEED/CX_GEN5_SPEED this register is shadow register for Gen3.." newline hexmask.long.byte 0x4 5.--9. 1. "GEN3_EQ_FMDC_N_EVALS,Convergence Window Depth. Number of consecutive evaluations considered in Phase 2/3 when determining if optimal coefficients have been found. Allowed range: 0 1 2 ..16 up to a maximum of CX_GEN3_EQ_COEFQ_DEPTH. When set to 0 EQ.." newline hexmask.long.byte 0x4 0.--4. 1. "GEN3_EQ_FMDC_T_MIN_PHASE23,Minimum Time (in ms) To Remain in EQ Master Phase. The LTSSM stays in EQ Master phase for at least this amount of time before starting to check for convergence of the coefficients. Allowed values 0 1 ... 24. Note: When.." group.long (0x1B4+0x700)++0x27 line.long 0x0 "ORDER_RULE_CTRL_OFF,Order Rule Control Register." hexmask.long.word 0x0 16.--31. 1. "RSVDP_16,Reserved for future use." newline hexmask.long.byte 0x0 8.--15. 1. "CPL_PASS_P,Completion Passing Posted Ordering Rule Control. Determines if CPL can pass halted P queue. - 0: CPL can not pass P (recommended) - 1: CPL can pass P" newline hexmask.long.byte 0x0 0.--7. 1. "NP_PASS_P,Non-Posted Passing Posted Ordering Rule Control. Determines if NP can pass halted P queue. - 0 : NP can not pass P (recommended). - 1 : NP can pass P" line.long 0x4 "PIPE_LOOPBACK_CONTROL_OFF,PIPE Loopback Control Register." bitfld.long 0x4 31. "PIPE_LOOPBACK,PIPE Loopback Enable. Indicates RMMI Loopback if M-PCIe. Note: This register field is sticky." "0,1" newline hexmask.long.byte 0x4 27.--30. 1. "RSVDP_27,Reserved for future use." newline bitfld.long 0x4 24.--26. "RXSTATUS_VALUE,RXSTATUS_VALUE is an internally reserved field. Do not use." "0,1,2,3,4,5,6,7" newline rbitfld.long 0x4 22.--23. "RSVDP_22,Reserved for future use." "0,1,2,3" newline hexmask.long.byte 0x4 16.--21. 1. "RXSTATUS_LANE,RXSTATUS_LANE is an internally reserved field. Do not use. Note: This register field is sticky." newline hexmask.long.word 0x4 0.--15. 1. "LPBK_RXVALID,LPBK_RXVALID is an internally reserved field. Do not use. Note: This register field is sticky." line.long 0x8 "MISC_CONTROL_1_OFF,DBI Read-Only Write Enable Register." hexmask.long.word 0x8 22.--31. 1. "RSVDP_22,Reserved for future use." newline bitfld.long 0x8 21. "P2P_ERR_RPT_CTRL,Determines whether to track completion of transmitted Non-Posted TLPs in P2P mode. - 0: Do not track completion - 1: Track completion Note: This register field is sticky." "Do not track completion,Track completion" newline bitfld.long 0x8 20. "P2P_TRACK_CPL_TO_REG,Determines whether to enable Peer to Peer (P2P) error reporting. - 0: Disable P2P error reporting - 1: Enable P2P error reporting Note: This register field is sticky." "Disable P2P error reporting,Enable P2P error reporting" newline bitfld.long 0x8 18.--19. "TARGET_ABOVE_CONFIG_LIMIT_REG,Configuration requests with an address greater than CONFIG_LIMIT_REG are directed to either ELBI or TRGT1 interface based on the setting of this field. This field can have the following values: - 1: ELBI - 2: TRGT1 Note:.." "?,ELBI,TRGT1,?" newline hexmask.long.word 0x8 8.--17. 1. "CONFIG_LIMIT_REG,Configuration requests are directed either to CDM or ELBI/RTRGT1 based on the value of this field. - Configuration requests with an address less CONFIG_LIMIT_REG are directed to the CDM - Configuration requests with an address greater.." newline bitfld.long 0x8 7. "CFG_TLP_BYPASS_EN_REG,Setting of this field defines which field TARGET_ABOVE_CONFIG_LIMIT_REG or CONFIG_LIMIT_REG decides the destination of Configuration requests. This field can have the following values: - 0: Configuration TLPs are routed according to.." "Configuration TLPs are routed according to the..,Configuration TLPs are routed according to the.." newline bitfld.long 0x8 6. "CPLQ_MNG_EN,This field enables the Completion Queue Management feature. Note: This register field is sticky." "0,1" newline bitfld.long 0x8 5. "ARI_DEVICE_NUMBER,When ARI is enabled this field enables use of the device ID. Note: This register field is sticky." "0,1" newline bitfld.long 0x8 4. "DISABLE_AUTO_LTR_CLR_MSG,Disable the autonomous generation of LTR clear message in upstream port. This field can have the following values: - 0: Allow the autonomous generation of LTR clear message. - 1: Disable the autonomous generation of LTR clear.." "Allow the autonomous generation of LTR clear..,Disable the autonomous generation of LTR clear.." newline bitfld.long 0x8 3. "SIMPLIFIED_REPLAY_TIMER,Enables Simplified Replay Timer (Gen4). For more details see 'Transmit Replay' in 'Transmit TLP Processing' section in the 'Controller Operations' chapter of the Databook. Simplified Replay Timer can have the following Values: -.." "0,1" newline bitfld.long 0x8 2. "UR_CA_MASK_4_TRGT1,When this field is set to '1' the controller suppresses error logging error message generation and CPL generation for non-posted requests TLPs (with UR filtering status) forwarded to your application (that is when DEFAULT_TARGET.." "0,1" newline bitfld.long 0x8 1. "DEFAULT_TARGET,Default target for an IO or MEM request with UR/CA/CRS received. Based on the value of this field the controller either drops or forwards these requests to your application. - 0: The controller drops all incoming I/O or MEM requests (after.." "The controller drops all incoming I/O or MEM..,The controller forwards all incoming I/O or MEM.." newline bitfld.long 0x8 0. "DBI_RO_WR_EN,Write to RO Registers Using DBI. Your application can write to some RO and HwInit register fields through the DBI when you set this field to '1'. For more details see 'Writing to Read-Only Registers' in 'Register Module LBC and DBI'.." "0,1" line.long 0xC "MULTI_LANE_CONTROL_OFF,UpConfigure Multi-lane Control Register. Used when upsizing or downsizing the link width through Configuration state without bringing the link down. For more details. see the 'Link Establishment' section in the 'Controller.." hexmask.long.tbyte 0xC 8.--31. 1. "RSVDP_8,Reserved for future use." newline bitfld.long 0xC 7. "UPCONFIGURE_SUPPORT,Upconfigure Support. The controller sends this value as the Link Upconfigure Capability in TS2 Ordered Sets in Configuration.Complete state. This field is reserved (fixed to '0') for M-PCIe. Note: This register field is sticky." "0,1" newline bitfld.long 0xC 6. "DIRECT_LINK_WIDTH_CHANGE,Directed Link Width Change. The controller always moves to Configuration state through Recovery state when this bit is set to '1'. - If the upconfigure_capable variable is '1' and the PCIE_CAP_HW_AUTO_WIDTH_DISABLE bit in.." "0,1" newline hexmask.long.byte 0xC 0.--5. 1. "TARGET_LINK_WIDTH,Target Link Width. Values correspond to: - 6'b000000: Controller does not start upconfigure or autonomous width downsizing in the Configuration state. - 6'b000001: x1 - 6'b000010: x2 - 6'b000100: x4 - 6'b001000: x8 - 6'b010000: x16 -.." line.long 0x10 "PHY_INTEROP_CTRL_OFF,PHY Interoperability Control Register." hexmask.long.tbyte 0x10 12.--31. 1. "RSVDP_12,Reserved for future use." newline bitfld.long 0x10 10. "L1_CLK_SEL,L1 Clock control bit. This field is reserved for internal use. You should not write to this field and change the default unless specifically instructed by Synopsys support. - 1: Controller does not request aux_clk switch and core_clk gating in.." "Controller requests aux_clk switch and core_clk..,Controller does not request aux_clk switch and.." newline rbitfld.long 0x10 9. "L1_NOWAIT_P1,L1 entry control bit. This field is reserved for internal use. You should not write to this field and change the default unless specifically instructed by Synopsys support. - 1: Controller does not wait for PHY to acknowledge transition to.." "Controller waits for the PHY to acknowledge..,Controller does not wait for PHY to acknowledge.." newline bitfld.long 0x10 8. "L1SUB_EXIT_MODE,L1 Exit Control Using phy_mac_pclkack_n. This field is reserved for internal use. You should not write to this field and change the default unless specifically instructed by Synopsys support. - 1: Controller exits L1 without waiting for.." "Controller waits for the PHY to assert..,Controller exits L1 without waiting for the PHY.." newline rbitfld.long 0x10 7. "RSVDP_7,Reserved for future use." "0,1" newline hexmask.long.byte 0x10 0.--6. 1. "RXSTANDBY_CONTROL,Rxstandby Control. Bits 0..5 determine if the controller asserts the RxStandby signal (mac_phy_rxstandby) in the indicated condition. Bit 6 enables the controller to perform the RxStandby/RxStandbyStatus handshake. This field is.." line.long 0x14 "TRGT_CPL_LUT_DELETE_ENTRY_OFF,TRGT_CPL_LUT Delete Entry Control register. Using this register you can delete one entry in the target completion LUT. You should only use this register when you know that your application will never send the completion.." bitfld.long 0x14 31. "DELETE_EN,This is a one-shot bit. A '1' write to this bit triggers the deletion of the target completion LUT entry that is specified in the LOOK_UP_ID field. This is a self-clearing register field. Reading from this register field always returns a '0'." "0,1" newline hexmask.long 0x14 0.--30. 1. "LOOK_UP_ID,This number selects one entry to delete of the TRGT_CPL_LUT." line.long 0x18 "LINK_FLUSH_CONTROL_OFF,Link Reset Request Flush Control Register." hexmask.long.byte 0x18 24.--31. 1. "RSVD_I_8,This is an internally reserved field. Do not use. Note: This register field is sticky." newline hexmask.long.tbyte 0x18 1.--23. 1. "RSVDP_1,Reserved for future use." newline bitfld.long 0x18 0. "AUTO_FLUSH_EN,Enables automatic flushing of pending requests before sending the reset request to the application logic to reset the PCIe controller and the AXI Bridge. The flushing process is initiated if any of the following events occur: - Hot reset.." "0,1" line.long 0x1C "AMBA_ERROR_RESPONSE_DEFAULT_OFF,AXI Bridge Slave Error Response Register." hexmask.long.word 0x1C 16.--31. 1. "RSVDP_16,Reserved for future use." newline hexmask.long.byte 0x1C 10.--15. 1. "AMBA_ERROR_RESPONSE_MAP,AXI Slave Response Error Map. Allows you to selectively map the errors received from the PCIe completion (for non-posted requests) to the AXI slave responses slv_rresp or slv_bresp. The recommended setting is SLVERR. CRS is.." newline hexmask.long.byte 0x1C 5.--9. 1. "RSVDP_5,Reserved for future use." newline bitfld.long 0x1C 3.--4. "AMBA_ERROR_RESPONSE_CRS,CRS Slave Error Response Mapping. Determines the AXI slave response for CRS completions. For more details see 'Error Handling' in the AXI chapter of the Databook. AHB: - always returns OKAY AXI: - 00: OKAY - 01: OKAY with all.." "OKAY,OKAY with all FFFF_FFFF data for all CRS..,?,?" newline bitfld.long 0x1C 2. "AMBA_ERROR_RESPONSE_VENDORID,Vendor ID Non-existent Slave Error Response Mapping. Determines the AXI slave response for errors on reads to non-existent Vendor ID register. For more details see 'Error Handling' in the AXI chapter of the Databook. AHB: -.." "OKAY,SLVERR/DECERR" newline rbitfld.long 0x1C 1. "RSVDP_1,Reserved for future use." "0,1" newline bitfld.long 0x1C 0. "AMBA_ERROR_RESPONSE_GLOBAL,Global Slave Error Response Mapping. Determines the AXI slave response for all error scenarios on non-posted requests. For more details see 'Error Handling' in the AXI chapter of the Databook. AHB: - 0: OKAY (with FFFF data for.." "OKAY,SLVERR/DECERR" line.long 0x20 "AMBA_LINK_TIMEOUT_OFF,Link Down AXI Bridge Slave Timeout Register. If your application AXI master issues outbound requests to the AXI bridge slave interface before the PCIe link is operational. the controller starts a 'flush' timer. The timeout value of.." hexmask.long.tbyte 0x20 9.--31. 1. "RSVDP_9,Reserved for future use." newline bitfld.long 0x20 8. "LINK_TIMEOUT_ENABLE_DEFAULT,Disable Flush. You can disable the flush feature by setting this field to '1'. Note: This register field is sticky." "0,1" newline hexmask.long.byte 0x20 0.--7. 1. "LINK_TIMEOUT_PERIOD_DEFAULT,Timeout Value (ms). The timer will timeout and then flush the bridge TX request queues after this amount of time. The timer counts when there are pending outbound AXI slave interface requests and the PCIe TX link is not.." line.long 0x24 "AMBA_ORDERING_CTRL_OFF,AMBA Ordering Control." hexmask.long.tbyte 0x24 8.--31. 1. "RSVDP_8,Reserved for future use." newline bitfld.long 0x24 7. "AX_MSTR_ZEROLREAD_FW,AXI Master Zero Length Read Forward to the application. The DW PCIe controller AXI bridge is able to terminate in order with the Posted transactions the zero length read implementing the PCIe express flush semantics of the Posted.." "The zero length Read is terminated at the DW..,The zero length Read is forward to the application" newline rbitfld.long 0x24 5.--6. "RSVDP_5,Reserved for future use." "0,1,2,3" newline bitfld.long 0x24 3.--4. "AX_MSTR_ORDR_P_EVENT_SEL,AXI Master Posted Ordering Event Selector. This field selects how the master interface determines when a P write is completed when enforcing the PCIe ordering rule 'NP must not pass P' at the AXI Master Interface. The AXI.." "B'last event: wait for the all of the write..,AW'last event: wait until the complete Posted..,This setting will not affect:,?" newline rbitfld.long 0x24 2. "RSVDP_2,Reserved for future use." "0,1" newline bitfld.long 0x24 1. "AX_SNP_EN,AXI Serialize Non-Posted Requests Enable. This field enables the AXI Bridge to serialize same ID Non-Posted Read/Write Requests on the wire. Serialization implies one outstanding same ID NP Read or Write on the wire and used to avoid AXI RAR.." "0,1" newline rbitfld.long 0x24 0. "RSVDP_0,Reserved for future use." "0,1" group.long (0x1E0+0x700)++0xB line.long 0x0 "COHERENCY_CONTROL_1_OFF,ACE Cache Coherency Control Register 1" hexmask.long 0x0 2.--31. 1. "CFG_MEMTYPE_BOUNDARY_LOW_ADDR,Boundary Lower Address For Memory Type. Bits [31:0] of dword-aligned address of the boundary for Memory type. The two lower address LSBs are '00'. Addresses up to but not including this value are in the lower address space.." newline rbitfld.long 0x0 1. "RSVDP_1,Reserved for future use." "0,1" newline bitfld.long 0x0 0. "CFG_MEMTYPE_VALUE,Sets the memory type for the lower and upper parts of the address space: - 0: lower = Peripheral; upper = Memory - 1: lower = Memory type; upper = Peripheral Note: This register field is sticky." "lower = Peripheral; upper = Memory,lower = Memory type; upper = Peripheral" line.long 0x4 "COHERENCY_CONTROL_2_OFF,ACE Cache Coherency Control Register 2" hexmask.long 0x4 0.--31. 1. "CFG_MEMTYPE_BOUNDARY_HIGH_ADDR,Boundary Upper Address For Memory Type. Bits [63:32] of the 64-bit dword-aligned address of the boundary for Memory type. Note: This register field is sticky." line.long 0x8 "COHERENCY_CONTROL_3_OFF,ACE Cache Coherency Control Register 3" hexmask.long.byte 0x8 27.--30. 1. "CFG_MSTR_AWCACHE_VALUE,Master Write CACHE Signal Value. Value of the individual bits in mstr_awcache when CFG_MSTR_AWCACHE_MODE is '1'. Note: not applicable to message requests; for message requests the value of mstr_awcache is always '0000' Note: This.." newline hexmask.long.byte 0x8 19.--22. 1. "CFG_MSTR_ARCACHE_VALUE,Master Read CACHE Signal Value. Value of the individual bits in mstr_arcache when CFG_MSTR_ARCACHE_MODE is '1'. Note: This register field is sticky." newline hexmask.long.byte 0x8 11.--14. 1. "CFG_MSTR_AWCACHE_MODE,Master Write CACHE Signal Behavior. Defines how the individual bits in mstr_awcache are controlled: - 0: set automatically by the AXI master - 1: set by the value of the corresponding bit of the CFG_MSTR_AWCACHE_VALUE field Note:.." newline hexmask.long.byte 0x8 3.--6. 1. "CFG_MSTR_ARCACHE_MODE,Master Read CACHE Signal Behavior. Defines how the individual bits in mstr_arcache are controlled: - 0: set automatically by the AXI master - 1: set by the value of the corresponding bit of the CFG_MSTR_ARCACHE_VALUE field Note:.." group.long (0x1F0+0x700)++0x7 line.long 0x0 "AXI_MSTR_MSG_ADDR_LOW_OFF,Lower 20 bits of the programmable AXI address where Messages coming from wire are mapped to. Bits [11:0] of the register are tied to zero for the address to be 4k-aligned. In previous releases. the third and fourth DWORDs of a.." hexmask.long.tbyte 0x0 12.--31. 1. "CFG_AXIMSTR_MSG_ADDR_LOW,Lower 20 bits of the programmable AXI address for Messages. Note: This register field is sticky." newline hexmask.long.word 0x0 0.--11. 1. "CFG_AXIMSTR_MSG_ADDR_LOW_RESERVED,Reserved for future use. Note: This register field is sticky." line.long 0x4 "AXI_MSTR_MSG_ADDR_HIGH_OFF,Upper 32 bits of the programmable AXI address where Messages coming from wire are mapped to." hexmask.long 0x4 0.--31. 1. "CFG_AXIMSTR_MSG_ADDR_HIGH,Upper 32 bits of the programmable AXI address for Messages. Note: This register field is sticky." rgroup.long (0x1F8+0x700)++0x7 line.long 0x0 "PCIE_VERSION_NUMBER_OFF,PCIe Controller IIP Release Version Number. The version number is given in hex format. You should convert each pair of hex characters to ASCII to interpret. Using 4.70a (GA) as an example: - VERSION_NUMBER = 0x3437302a which.." hexmask.long 0x0 0.--31. 1. "VERSION_NUMBER,Version Number." line.long 0x4 "PCIE_VERSION_TYPE_OFF,PCIe Controller IIP Release Version Type. The type is given in hex format. You should convert each pair of hex characters to ASCII to interpret. Using 4.70a (GA) as an example: - VERSION_NUMBER = 0x3437302a which translates to 470*.." hexmask.long 0x4 0.--31. 1. "VERSION_TYPE,Version Type." group.long (0x240+0x700)++0x7 line.long 0x0 "MSIX_ADDRESS_MATCH_LOW_OFF,MSI-X Address Match Low Register. When you enable the MSI-X Table RAM feature (MSIX_TABLE_EN=1). the controller implements the logic and RAM required to generate MSI-X requests. For more details. see the Interrupts section in.." hexmask.long 0x0 2.--31. 1. "MSIX_ADDRESS_MATCH_LOW,MSI-X Address Match Low Address. Note: This register field is sticky." newline rbitfld.long 0x0 1. "MSIX_ADDRESS_MATCH_RESERVED_1,Reserved. Note: This register field is sticky." "0,1" newline bitfld.long 0x0 0. "MSIX_ADDRESS_MATCH_EN,MSI-X Match Enable. Enable the MSI-X Address Match feature when the AXI bridge is present. Note: This register field is sticky." "0,1" line.long 0x4 "MSIX_ADDRESS_MATCH_HIGH_OFF,MSI-X Address Match High Register. When you enable the MSI-X Table RAM feature (MSIX_TABLE_EN=1). the controller implements the logic and RAM required to generate MSI-X requests. For more details. see the Interrupts section in.." hexmask.long 0x4 0.--31. 1. "MSIX_ADDRESS_MATCH_HIGH,MSI-X Address Match High Address. Note: This register field is sticky." wgroup.long (0x248+0x700)++0x3 line.long 0x0 "MSIX_DOORBELL_OFF,MSI-X Doorbell Register. When you enable the MSI-X Table RAM feature (MSIX_TABLE_EN=1). the controller implements the logic and RAM required to generate MSI-X requests. For more details. see the Interrupts section in the 'Controller.." bitfld.long 0x0 29.--31. "MSIX_DOORBELL_RESERVED_29_31,Reserved." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x0 24.--28. 1. "MSIX_DOORBELL_PF,MSIX Doorbell Physical Function. This register determines the Physical Function for the MSI-X transaction." newline hexmask.long.byte 0x0 16.--23. 1. "MSIX_DOORBELL_VF,MSIX Doorbell Virtual Function. This register determines the Virtual Function for the MSI-X transaction." newline bitfld.long 0x0 15. "MSIX_DOORBELL_VF_ACTIVE,MSIX Doorbell Virtual Function Active. This register determines whether a Virtual Function is used to generate the MSI-X transaction." "0,1" newline bitfld.long 0x0 12.--14. "MSIX_DOORBELL_TC,MSIX Doorbell Traffic Class. This register determines which traffic class to generate the MSI-X transaction with." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 11. "MSIX_DOORBELL_RESERVED_11,Reserved." "0,1" newline hexmask.long.word 0x0 0.--10. 1. "MSIX_DOORBELL_VECTOR,MSI-X Doorbell Vector. This register determines which vector to generate the MSI-X transaction for." group.long (0x24C+0x700)++0x3 line.long 0x0 "MSIX_RAM_CTRL_OFF,MSI-X RAM power mode and debug control register. When you enable the MSI-X Table RAM feature (MSIX_TABLE_EN=1). the controller implements the logic and RAM required to generate MSI-X requests. For more details. see the Interrupts.." hexmask.long.byte 0x0 26.--31. 1. "MSIX_RAM_CTRL_RESERVED_26_31,Reserved. Note: This register field is sticky." newline bitfld.long 0x0 25. "MSIX_RAM_CTRL_DBG_PBA,MSIX PBA RAM Debug Mode. Use this bit to activate the debug mode and allow direct read/write access to the PBA. Use can also use the dbg_pba input to activate debug mode. Debug mode turns off the PF/VF/Offset-based addressing into.." "0,1" newline bitfld.long 0x0 24. "MSIX_RAM_CTRL_DBG_TABLE,MSIX Table RAM Debug Mode. Use this bit to activate the debug mode and allow direct read/write access to the Table. Use can also use the dbg_table input to activate debug mode. Debug mode turns off the PF/VF/Offset-based.." "0,1" newline hexmask.long.byte 0x0 17.--23. 1. "MSIX_RAM_CTRL_RESERVED_17_23,Reserved. Note: This register field is sticky." newline bitfld.long 0x0 16. "MSIX_RAM_CTRL_BYPASS,MSIX RAM Control Bypass. The bypass field when set disables the internal generation of low power signals for both RAMs. It is up to the application to ensure the RAMs are in the proper power state before trying to access them." "0,1" newline hexmask.long.byte 0x0 10.--15. 1. "MSIX_RAM_CTRL_RESERVED_10_15,Reserved. Note: This register field is sticky." newline bitfld.long 0x0 9. "MSIX_RAM_CTRL_PBA_SD,MSIX PBA RAM Shut Down. Set this bit to drive the cfg_msix_pba_sd output to signal your external logic to place the MSIX PBA RAM in Shut Down low-power mode. Note: This register field is sticky." "0,1" newline bitfld.long 0x0 8. "MSIX_RAM_CTRL_PBA_DS,MSIX PBA RAM Deep Sleep. Set this bit to drive the cfg_msix_pba_ds output to signal your external logic to place the MSIX PBA RAM in Deep Sleep low-power mode. Note: This register field is sticky." "0,1" newline hexmask.long.byte 0x0 2.--7. 1. "MSIX_RAM_CTRL_RESERVED_2_7,Reserved. Note: This register field is sticky." newline bitfld.long 0x0 1. "MSIX_RAM_CTRL_TABLE_SD,MSIX Table RAM Shut Down. Set this bit to drive the cfg_msix_table_sd output to signal your external logic to place the MSIX Table RAM in Shut Down low-power mode. Note: This register field is sticky." "0,1" newline bitfld.long 0x0 0. "MSIX_RAM_CTRL_TABLE_DS,MSIX Table RAM Deep Sleep. Set this bit to drive the cfg_msix_table_ds output to signal your external logic to place the MSIX Table RAM in Deep Sleep low-power mode. Note: This register field is sticky." "0,1" group.long (0x430+0x700)++0x3 line.long 0x0 "PL_LTR_LATENCY_OFF,LTR Latency Register. The function of this register field (and all other fields in this register) differs between an upstream port and a downstream port. For an upstream port. the register fields capture the corresponding fields in the.." bitfld.long 0x0 31. "NO_SNOOP_LATENCY_REQUIRE,No Snoop Latency Requirement. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" "0,1" newline rbitfld.long 0x0 29.--30. "RSVDP_29,Reserved for future use." "0,1,2,3" newline bitfld.long 0x0 26.--28. "NO_SNOOP_LATENCY_SCALE,No Snoop Latency Scale. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" "0,1,2,3,4,5,6,7" newline hexmask.long.word 0x0 16.--25. 1. "NO_SNOOP_LATENCY_VALUE,No Snoop Latency Value. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" newline bitfld.long 0x0 15. "SNOOP_LATENCY_REQUIRE,Snoop Latency Requirement. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" "0,1" newline rbitfld.long 0x0 13.--14. "RSVDP_13,Reserved for future use." "0,1,2,3" newline bitfld.long 0x0 10.--12. "SNOOP_LATENCY_SCALE,Snoop Latency Scale. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" "0,1,2,3,4,5,6,7" newline hexmask.long.word 0x0 0.--9. 1. "SNOOP_LATENCY_VALUE,Snoop Latency Value. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" group.long (0x440+0x700)++0xB line.long 0x0 "AUX_CLK_FREQ_OFF,Auxiliary Clock Frequency Control Register." hexmask.long.tbyte 0x0 10.--31. 1. "RSVDP_10,Reserved for future use." newline hexmask.long.word 0x0 0.--9. 1. "AUX_CLK_FREQ,The aux_clk frequency in MHz. This value is used to provide a 1 us reference for counting time during low-power states with aux_clk when the PHY has removed the pipe_clk. Frequencies lower than 1 MHz are possible but with a loss of accuracy.." line.long 0x4 "L1_SUBSTATES_OFF,L1 Substates Timing Register." hexmask.long.tbyte 0x4 9.--31. 1. "RSVDP_9,Reserved for future use." newline bitfld.long 0x4 8. "L1SUB_LOW_POWER_CLOCK_SWITCH_MODE,If this bit is set to 1'b1 the reference clock will be running regardless of the CLKREQ# setting. If this bit is set to 1'b0 the reference clock may be gated off when CLKREQ# is de-asserted. If the bit is set to 1'b1 the.." "0,1" newline bitfld.long 0x4 6.--7. "L1SUB_T_PCLKACK,Max delay (in 1us units) between a MAC request to remove the clock on mac_phy_pclkreq_n and a PHY response on phy_mac_pclkack_n. If the PHY does not respond within this time the request is aborted.The actual timeout value will be.." "0,1,2,3" newline hexmask.long.byte 0x4 2.--5. 1. "L1SUB_T_L1_2,Duration (in 1us units) of L1.2. The actual timeout value will be L1SUB_T_L1_2 + 1. Range is 0.15. Note: This register field is sticky." newline bitfld.long 0x4 0.--1. "L1SUB_T_POWER_OFF,Duration (in 1us units) of L1.2.Entry. The actual timeout value will be L1SUB_T_POWER_OFF + 1. Range is 0.3. Note: This register field is sticky." "0,1,2,3" line.long 0x8 "POWERDOWN_CTRL_STATUS_OFF,Powerdown Control and Status Register." hexmask.long.tbyte 0x8 12.--31. 1. "RSVDP_12,Reserved for future use." newline hexmask.long.byte 0x8 8.--11. 1. "POWERDOWN_PHY_POWERDOWN,This field represents the Powerdown value that has been acknowledged by the PHY. It is updated with the value of Powerdown driven by the controller when the PHY has returned the Phystatus acknowledgment for the Powerdown.." newline hexmask.long.byte 0x8 4.--7. 1. "POWERDOWN_MAC_POWERDOWN,This field represents the Powerdown value driven by the controller to the PHY." newline rbitfld.long 0x8 1.--3. "RSVDP_1,Reserved for future use." "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 0. "POWERDOWN_FORCE,This field is a one shot field. Writing a value of 1 to this field causes the controller to complete the P2 Powerdown handshake regardless of whether the PHY has returned Phystatus. This field could be used for debug purposes in event.." "0,1" group.long (0x470+0x700)++0x7 line.long 0x0 "PHY_VIEWPORT_CTLSTS_OFF,PHY Register Viewport Control and Status Register." rbitfld.long 0x0 31. "PHY_VIEWPORT_PENDING,PHY viewport pending. Indicates the access is pending. - 1 : Pending - 0 : Idle This bit is set to 1 when the read/write access has been initiated. This bit is cleared when the access is completed. If phy_reg_clk_g is never activated.." "Idle,Pending" newline rbitfld.long 0x0 30. "PHY_VIEWPORT_STATUS,PHY viewport status. Indicates the status of the latest access. - 1 : Timeout - 0 : No errors If the timeout is detected this bit is set to 1 and PHY_VIEWPORT_PENDING is cleared. This bit is cleared when the read/write access is.." "No errors,Timeout" newline hexmask.long.byte 0x0 23.--29. 1. "RSVDP_23,Reserved for future use." newline bitfld.long 0x0 22. "PHY_VIEWPORT_TIMEOUT_DISABLE,PHY viewport timeout disable. Disables the PHY register access timeout structure. When the timeout is disabled you must ensure that the PHY register accesses are always acknowledged by cr_para_ack. Otherwise.." "0,1" newline bitfld.long 0x0 21. "PHY_VIEWPORT_BCWR,Broadcast write access to all xN sub-blocks. If you need to broadcast the write accesses into all lanes both PHY_VIEWPORT_ADDR[15] and this bit should be 1. Note: This register field is sticky." "0,1" newline bitfld.long 0x0 20. "PHY_VIEWPORT_READ,PHY viewport read. If set a read access is initiated. The value is always 0 when this bit is read. Note: This register field is sticky." "0,1" newline hexmask.long.byte 0x0 16.--19. 1. "PHY_VIEWPORT_NUM,PHY viewport xN sub-block number. Selects one of xN sub-blocks. This register is not used when the write access is initiated with PHY_VIEWPORT_BCWR==1. Note: This register field is sticky." newline hexmask.long.word 0x0 0.--15. 1. "PHY_VIEWPORT_ADDR,PHY viewport address. Indicates the PHY's register address. Please refer to the PHY databook for the address map definition. Note: This register field is sticky." line.long 0x4 "PHY_VIEWPORT_DATA_OFF,PHY Register Viewport Data Register." hexmask.long.word 0x4 16.--31. 1. "RSVDP_16,Reserved for future use." newline hexmask.long.word 0x4 0.--15. 1. "PHY_VIEWPORT_DATA,PHY viewport data. A write access to this register initiates the PHY register write access. By a read access to this register this field returns the latest read data from the PHY register. Note: This register field is sticky." group.long (0x490+0x700)++0x3 line.long 0x0 "PIPE_RELATED_OFF,PIPE Related Register. This register controls the pipe's capabitity. control. and status parameters." hexmask.long.tbyte 0x0 9.--31. 1. "RSVDP_9,Reserved for future use." newline bitfld.long 0x0 8. "PIPE_GARBAGE_DATA_MODE,PIPE Garbage Data Mode. - 0: PIPE Spec compliant mode: The MAC discards any symbols received after the electrical idle ordered-set until RxValid is deasserted. - 1: Special PHY Support mode: The MAC discards any symbols received.." "PIPE Spec compliant mode: The MAC discards any..,Special PHY Support mode: The MAC discards any.." tree.end tree.end tree "PCIE1_VF67" base ad:0x310A0000 tree "PF0_TYPE1_HDR (PCI-Compatible Configuration Space Header Type1)" group.long 0x0++0x2F line.long 0x0 "TYPE1_DEV_ID_VEND_ID_REG,Device ID and Vendor ID Register." hexmask.long.word 0x0 16.--31. 1. "DEVICE_ID,Device ID. The Device ID register identifies the particular Function. This identifier is allocated by the vendor. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else.." newline hexmask.long.word 0x0 0.--15. 1. "VENDOR_ID,Vendor ID. The Vendor ID register identifies the manufacturer of the Function. Valid vendor identifiers are allocated by the PCI-SIG to ensure uniqueness. It is not permitted to populate this register with a value of FFFFh which is an invalid.." line.long 0x4 "TYPE1_STATUS_COMMAND_REG,Status and Command Register." bitfld.long 0x4 31. "DETECTED_PARITY_ERROR,Detected Parity Error. This bit is set by a Function whenever it receives a Poisoned TLP regardless of the state the Parity Error Response bit in the Command register. The bit is set when the Poisoned TLP is received by a.." "0,1" newline bitfld.long 0x4 30. "SIGNALED_SYS_ERROR,Signaled System Error. This bit is set when a Function sends an ERR_FATAL or ERR_NONFATAL Message and the SERR# Enable bit in the Command register is 1b." "0,1" newline bitfld.long 0x4 29. "RCVD_MASTER_ABORT,Received Master Abort. This bit is set when a Requester receives a Completion with Unsupported Request Completion status. The bit is set when the Unsupported Request is received by a Function's primary side." "0,1" newline bitfld.long 0x4 28. "RCVD_TARGET_ABORT,Received Target Abort. This bit is set when a Requester receives a Completion with Completer Abort Completion status. The bit is set when the Completer Abort is received by a Function's primary side." "0,1" newline bitfld.long 0x4 27. "SIGNALED_TARGET_ABORT,Signaled Target Abort. This bit is set when a Function completes a Posted or Non-Posted Request as a Completer Abort error. This applies to a Function when the Completer Abort was generated by its primary side." "0,1" newline rbitfld.long 0x4 25.--26. "DEV_SEL_TIMING,DEVSEL Timing. This field was originally described in the PCI Local Bus Specification. Its functionality does not apply to PCI Express. The controller hardwires it to 00b." "0,1,2,3" newline bitfld.long 0x4 24. "MASTER_DPE,Master Data Parity Error. This bit is set by a Function if the Parity Error Response bit in the Command register is 1b and either of the following two conditions occurs: - Port receives a Poisoned Completion going downstream - Port transmits a.." "0,1" newline rbitfld.long 0x4 23. "FAST_B2B_CAP,Fast Back-to-Back Transactions Capable. This bit was originally described in the PCI Local Bus Specification. Its functionality does not apply to PCI Express. The controller hardwires this bit to 0b." "0,1" newline rbitfld.long 0x4 22. "RSVDP_22,Reserved for future use." "0,1" newline rbitfld.long 0x4 21. "FAST_66MHZ_CAP,66 MHz Capable. This bit was originally described in the PCI Local Bus Specification. Its functionality does not apply to PCI Express. The controller hardwires this bit to 0b." "0,1" newline rbitfld.long 0x4 20. "CAP_LIST,Capabilities List. Indicates the presence of an Extended Capability list item. Since all PCI Express device Functions are required to implement the PCI Express Capability structure the controller hardwires this bit to 1b." "0,1" newline rbitfld.long 0x4 19. "INT_STATUS,Interrupt Status. When set indicates that an INTx emulation interrupt is pending internally in the Function. INTx emulation interrupts forwarded by Functions from the secondary side are not reflected in this bit. Setting the Interrupt Disable.." "0,1" newline rbitfld.long 0x4 17.--18. "RSVDP_17,Reserved for future use." "0,1,2,3" newline bitfld.long 0x4 16. "IMM_READINESS,Immediate Readiness. This optional bit when set indicates the Function is guaranteed to be ready to successfully complete valid configuration accesses at any time following any reset that the host is capable of issuing Configuration.." "0,1" newline hexmask.long.byte 0x4 11.--15. 1. "RESERV,Reserved." newline bitfld.long 0x4 10. "INT_EN,Interrupt Disable. Controls the ability of a Function to generate INTx emulation interrupts. When set Functions are prevented from asserting INTx interrupts. Note: - Any INTx emulation interrupts already asserted by the Function must be.." "0,1" newline rbitfld.long 0x4 9. "RSVDP_9,Reserved for future use." "0,1" newline bitfld.long 0x4 8. "SERREN,SERR# Enable. When set this bit enables reporting upstream of Non-fatal and Fatal errors detected by the Function. Note: The errors are reported if enabled either through this bit or through the PCI Express specific bits in the Device Control.." "0,1" newline rbitfld.long 0x4 7. "IDSEL,IDSEL Stepping/Wait Cycle Control. This bit was originally described in the PCI Local Bus Specification. Its functionality does not apply to PCI Express. The controller hardwires this bit to 0b." "0,1" newline bitfld.long 0x4 6. "PERREN,Parity Error Response. This bit controls the logging of poisoned TLPs in the Master Data Parity Error bit in the Status register. For more details see the 'Error Registers' section of the PCI Express Base Specification." "0,1" newline rbitfld.long 0x4 5. "VGAPS,VGA Palette Snoop. This bit was originally described in the PCI Local Bus Specification and the PCI-to-PCI Bridge Architecture Specification. Its functionality does not apply to PCI Express. The controller hardwires this bit to 0b." "0,1" newline rbitfld.long 0x4 4. "MWI_EN,Memory Write and Invalidate. This bit was originally described in the PCI Local Bus Specification and the PCI-to-PCI Bridge Architecture Specification. Its functionality does not apply to PCI Express. The controller hardwires this bit to 0b. For.." "0,1" newline rbitfld.long 0x4 3. "SCO,Special Cycle Enable. This bit was originally described in the PCI Local Bus Specification. Its functionality does not apply to PCI Express. The controller hardwires this bit to 0b." "0,1" newline bitfld.long 0x4 2. "BME,Bus Master Enable. This bit controls forwarding of Memory or I/O requests by a port in the Upstream direction. When this bit is 0b Memory and I/O Requests received at a Root Port must be handled as Unsupported Requests (UR) For Non-Posted Requests a.." "0,1" newline bitfld.long 0x4 1. "MSE,Memory Space Enable. This bit controls a Function's response to Memory Space accesses received on its primary side. - When set the Function is enabled to decode the address and further process Memory Space accesses. - When clear all received Memory.." "0,1" newline bitfld.long 0x4 0. "IO_EN,IO Space Enable. This bit controls a Function's response to I/O Space accesses received on its primary side. - When set the Function is enabled to decode the address and further process I/O Space accesses. - When clear all received I/O accesses.." "0,1" line.long 0x8 "TYPE1_CLASS_CODE_REV_ID_REG,Class Code and Revision ID Register." hexmask.long.byte 0x8 24.--31. 1. "BASE_CLASS_CODE,Base Class Code. A code that broadly classifies the type of operation the Function performs. Encodings for base class are provided in the PCI Code and ID Assignment Specification. All unspecified encodings are reserved. Note: The access.." newline hexmask.long.byte 0x8 16.--23. 1. "SUBCLASS_CODE,Sub-Class Code. Specifies a base class sub-class which identifies more specifically the operation of the Function. Encodings for sub-class are provided in the PCI Code and ID Assignment Specification. All unspecified encodings are.." newline hexmask.long.byte 0x8 8.--15. 1. "PROGRAM_INTERFACE,Programming Interface. This field identifies a specific register level programming interface (if any) so that device independent software can interact with the Function. Encodings for interface are provided in the PCI Code and ID.." newline hexmask.long.byte 0x8 0.--7. 1. "REVISION_ID,Revision ID. The value of this field specifies a Function specific revision identifier. The value is chosen by the vendor. Zero is an acceptable value. The Revision ID should be viewed as a vendor defined extension to the Device ID. Note: The.." line.long 0xC "TYPE1_BIST_HDR_TYPE_LAT_CACHE_LINE_SIZE_REG,BIST. Header Type. Latency Timer. and Cache Line Size Register." hexmask.long.byte 0xC 24.--31. 1. "BIST,BIST. This register is used for control and status of BIST. Functions that do not support BIST must hardwire the register to 00h. A Function whose BIST is invoked must not prevent normal operation of the PCI Express Link. Bit descriptions: - [31]:.." newline rbitfld.long 0xC 23. "MULTI_FUNC,Multi-Function Device. - When set indicates that the device may contain multiple Functions but not necessarily. Software is permitted to probe for Functions other than Function 0. - When clear software must not probe for Functions other.." "0,1" newline hexmask.long.byte 0xC 16.--22. 1. "HEADER_TYPE,Header Layout. This field identifies the layout of the second part of the predefined header. The controller uses 000 0001b encoding. The encoding 000 0010b is reserved. This encoding was originally described in the PC Card Standard Electrical.." newline hexmask.long.byte 0xC 8.--15. 1. "LATENCY_MASTER_TIMER,Latency Timer. This register is also referred to as Primary Latency Timer. The Latency Timer was originally described in the PCI Local Bus Specification and the PCI-to-PCI Bridge Architecture Specification. Its functionality does not.." newline hexmask.long.byte 0xC 0.--7. 1. "CACHE_LINE_SIZE,Cache Line Size. The Cache Line Size register is programmed by the system firmware or the operating system to system cache line size. However legacy conventional PCI software may not always be able to program this register correctly.." line.long 0x10 "BAR0_REG,BAR0 Register. System software must build a consistent address map before booting the machine to an operating system. This means it has to determine how much memory is in the system. and how much address space the Functions in the system.." hexmask.long 0x10 4.--31. 1. "BAR0_START,BAR0 Base Address. - Memory Space: Base Address. - IO Space: bits[31:2] are used to map the function into IO space/Base. Address. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R(Sticky)/W(Sticky) if.." newline bitfld.long 0x10 3. "BAR0_PREFETCH,BAR0 Prefetchable. - Memory Space: Set to one if data is pre-fetchable. A Function is permitted to mark a range as prefetchable. If there are no side effects on reads the function returns all bytes on reads regardless of the byte enables.." "0,1" newline bitfld.long 0x10 1.--2. "BAR0_TYPE,BAR0 Type. - Memory Space: Base Address registers that map into Memory Space can be 32 bits or 64 bits wide (to support mapping into a 64-bit address space). The bit encoding is as follows: -- 00: Base register is 32 bits wide and can be mapped.." "Base register is 32 bits wide and can be mapped..,Reserved,?,?" newline bitfld.long 0x10 0. "BAR0_MEM_IO,BAR0 Memory Space Indicator. This bit is used to determine whether the register maps into Memory or I/O Space. Base Address registers that map to Memory Space must return a 0b. Base Address registers that map to I/O Space must return a 1b." "0,1" line.long 0x14 "BAR1_REG,BAR1 Register. System software must build a consistent address map before booting the machine to an operating system. This means it has to determine how much memory is in the system. and how much address space the Functions in the system.." hexmask.long 0x14 4.--31. 1. "BAR1_START,BAR1 Base Address. - Memory Space: Base Address. - IO Space: bits[31:2] are used to map the function into IO space/Base. Address. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R(Sticky)/W(Sticky) if.." newline bitfld.long 0x14 3. "BAR1_PREFETCH,BAR1 Prefetchable. - Memory Space: Set to one if data is pre-fetchable. A Function is permitted to mark a range as prefetchable. If there are no side effects on reads the function returns all bytes on reads regardless of the byte enables.." "0,1" newline bitfld.long 0x14 1.--2. "BAR1_TYPE,BAR1 Type. - Memory Space: Base Address registers that map into Memory Space can be 32 bits or 64 bits wide (to support mapping into a 64-bit address space). The bit encoding is as follows: -- 00: Base register is 32 bits wide and can be mapped.." "Base register is 32 bits wide and can be mapped..,Reserved,?,?" newline bitfld.long 0x14 0. "BAR1_MEM_IO,BAR1 Memory Space Indicator. This bit is used to determine whether the register maps into Memory or I/O Space. Base Address registers that map to Memory Space must return a 0b. Base Address registers that map to I/O Space must return a 1b." "0,1" line.long 0x18 "SEC_LAT_TIMER_SUB_BUS_SEC_BUS_PRI_BUS_REG,Secondary Latency Timer. Subordinate Bus Number. Secondary Bus Number. and Primary Bus Number Register." hexmask.long.byte 0x18 24.--31. 1. "SEC_LAT_TIMER,Secondary Latency Timer. This register does not apply to PCI Express. The controller hardwires it to 00h." newline hexmask.long.byte 0x18 16.--23. 1. "SUB_BUS,Subordinate Bus Number. The Subordinate Bus Number register is used to record the bus number of the highest numbered PCI bus segment which is behind (or subordinate to) the bridge. Configuration software programs the value in this register. The.." newline hexmask.long.byte 0x18 8.--15. 1. "SEC_BUS,Secondary Bus Number. The Secondary Bus Number register is used to record the bus number of the PCI bus segment to which the secondary interface of the bridge is connected. Configuration software programs the value in this register. The bridge.." newline hexmask.long.byte 0x18 0.--7. 1. "PRIM_BUS,Primary Bus Number. This register is not used by PCI Express Functions. It is implemented for compatibility with legacy software." line.long 0x1C "SEC_STAT_IO_LIMIT_IO_BASE_REG,Secondary Status. and I/O Limit and Base Register. The I/O Limit and I/O Base registers are optional and define an address range that is used by the bridge to determine when to forward I/O transactions from one interface to.." bitfld.long 0x1C 31. "SEC_STAT_DPE,Detected Parity Error. This bit is set by a Function when a Poisoned TLP is received by its secondary side regardless of the state the Parity Error Response Enable bit in the Bridge Control register." "0,1" newline bitfld.long 0x1C 30. "SEC_STAT_RCVD_SYS_ERR,Received System Error. This bit is set when the secondary side of a Function receives an ERR_FATAL or ERR_NONFATAL message." "0,1" newline bitfld.long 0x1C 29. "SEC_STAT_RCVD_MSTR_ABRT,Received Master Abort. This bit is set when the secondary side of a Function (for requests initiated by the Type 1 header Function itself) receives a Completion with Unsupported Request Completion status." "0,1" newline bitfld.long 0x1C 28. "SEC_STAT_RCVD_TRGT_ABRT,Received Target Abort. This bit is set when the secondary side of a Function (for requests initiated by the Type 1 header Function itself) receives a Completion with Completer Abort Completion status." "0,1" newline bitfld.long 0x1C 27. "SEC_STAT_SIG_TRGT_ABRT,Signaled Target Abort. This bit is set when the secondary side of the Function (for Requests completed by the Type 1 header Function itself) completes a Posted or Non-Posted request as a Completer Abort error." "0,1" newline rbitfld.long 0x1C 25.--26. "RSVDP_25,Reserved for future use." "0,1,2,3" newline bitfld.long 0x1C 24. "SEC_STAT_MDPE,Master Data Parity Error. This bit is set by a Function if the Parity Error Response Enable bit in the Bridge Control register is set and either of the following two conditions occurs: - Port receives a Poisoned Completion coming Upstream.." "0,1" newline rbitfld.long 0x1C 23. "RSVDP_23,Reserved for future use." "0,1" newline hexmask.long.byte 0x1C 16.--22. 1. "SEC_STAT_RESERV,Reserved." newline hexmask.long.byte 0x1C 12.--15. 1. "IO_LIMIT,I/O Limit Address. These bits correspond to the address[15:12] of IO address range. For the purpose of address decoding the bridge assumes that the lower 12 address bits address[11:0] of the I/O limit address (not implemented in the I/O Limit.." newline rbitfld.long 0x1C 9.--11. "IO_RESERV1,Reserved." "0,1,2,3,4,5,6,7" newline bitfld.long 0x1C 8. "IO_DECODE_BIT8,I/O Addressing Encode (IO Limit Address). This bit encodes the IO addressing capability of the bridge. IO_DECODE_BIT8 indicates the following: - 0h: The bridge supports only 16-bit I/O addressing (for ISA compatibility). For the purpose of.." "0,1" newline hexmask.long.byte 0x1C 4.--7. 1. "IO_BASE,I/O Base Address. These bits correspond to the address[15:12] of IO address range. For the purpose of address decoding the bridge assumes that the lower 12 address bits address[11:0] of the I/O base address (not implemented in the I/O Base.." newline rbitfld.long 0x1C 1.--3. "IO_RESERV,Reserved." "0,1,2,3,4,5,6,7" newline bitfld.long 0x1C 0. "IO_DECODE,I/O Addressing Encode (IO Base Address) This bit encodes the IO addressing capability of the bridge. IO_DECODE indicates the following: - 0h: The bridge supports only 16-bit I/O addressing (for ISA compatibility). For the purpose of address.." "0,1" line.long 0x20 "MEM_LIMIT_MEM_BASE_REG,Memory Limit and Base Register. The Memory Limit and Memory Base registers define a memory mapped address range which is used by the bridge to determine when to forward memory transactions from one interface to the other. If there.." hexmask.long.word 0x20 20.--31. 1. "MEM_LIMIT,Memory Limit Address. These bits correspond to the upper 12 address bits Address[31:20] of 32-bit addresses. For the purpose of address decoding the bridge assumes that the lower 20 address bits Address[19:0] of the memory limit address.." newline hexmask.long.byte 0x20 16.--19. 1. "MEM_LIMIT_RESERV,Reserved." newline hexmask.long.word 0x20 4.--15. 1. "MEM_BASE,Memory Base Address. These bits correspond to the upper 12 address bits Address[31:20] of 32-bit addresses. For the purpose of address decoding the bridge assumes that the lower 20 address bits Address[19:0] of the memory base address (not.." newline hexmask.long.byte 0x20 0.--3. 1. "MEM_BASE_RESERV,Reserved." line.long 0x24 "PREF_MEM_LIMIT_PREF_MEM_BASE_REG,Prefetchable Memory Limit and Base Register. The Prefetchable Memory Limit and Prefetchable Memory Base registers must indicate that 64-bit addresses are supported. as defined in PCI-to-PCI Bridge Architecture.." hexmask.long.word 0x24 20.--31. 1. "PREF_MEM_LIMIT,Prefetchable Memory Limit Address. If the Prefetchable Memory Limit register indicates support for 32-bit addressing then the Prefetchable Limit Upper 32 Bits register is implemented as a read-only register that returns zero when read. If.." newline rbitfld.long 0x24 17.--19. "PREF_RESERV1,Reserved." "0,1,2,3,4,5,6,7" newline rbitfld.long 0x24 16. "PREF_MEM_LIMIT_DECODE,Prefetchable Memory Limit Decode. This bit encodes whether or not the bridge supports 64-bit addresses. Note: This bit is a copy of the PREF_MEM_DECODE bit and always reflects the current value of that bit. The value of.." "0,1" newline hexmask.long.word 0x24 4.--15. 1. "PREF_MEM_BASE,Prefetchable Memory Base Address. If the Prefetchable Memory Base register indicates support for 32-bit addressing then the Prefetchable Base Upper 32 Bits register is implemented as a read-only register that returns zero when read. If the.." newline rbitfld.long 0x24 1.--3. "PREF_RESERV,Reserved." "0,1,2,3,4,5,6,7" newline bitfld.long 0x24 0. "PREF_MEM_DECODE,Prefetchable Memory Base Decode. This bit encodes whether or not the bridge supports 64-bit addresses. Note: By default the bit is set to 1'b1 indicating that 64-bit addresses are supported. If the bridge only supports 32-bit prefetchable.." "0,1" line.long 0x28 "PREF_BASE_UPPER_REG,Prefetchable Base Upper 32 Bits Register. The Prefetchable Base Upper 32 Bits register is an optional extension to the Prefetchable Memory Base register." hexmask.long 0x28 0.--31. 1. "PREF_MEM_BASE_UPPER,Prefetchable Base Upper 32 Bit. If the Prefetchable Memory Base register indicates support for 32-bit addressing then this register is implemented as read-only register that returns zero when read. If the Prefetchable Memory Base.." line.long 0x2C "PREF_LIMIT_UPPER_REG,Prefetchable Limit Upper 32 Bits Register. The Prefetchable Limit Upper 32 Bits register is an optional extension to the Prefetchable Memory Limit register." hexmask.long 0x2C 0.--31. 1. "PREF_MEM_LIMIT_UPPER,Prefetchable Limit Upper 32 Bit. If the Prefetchable Memory Limit register indicate support for 64-bit addressing then this register is implemented as read/write register which must be initialized by configuration software. This.." rgroup.long 0x30++0x3 line.long 0x0 "IO_LIMIT_UPPER_IO_BASE_UPPER_REG,I/O Limit and Base Upper 16 Bits Register. The I/O Limit Upper 16 Bits and I/O Base Upper 16 Bits registers are optional extensions to the I/O Limit and I/O Base registers." hexmask.long.word 0x0 16.--31. 1. "IO_LIMIT_UPPER,I/O Limit Upper 16 Bits. If the I/O Limit register indicates support for 16-bit I/O address decoding then this register is implemented as a read-only register which return zero when read. If the I/O Limit register indicates support for.." newline hexmask.long.word 0x0 0.--15. 1. "IO_BASE_UPPER,I/O Base Upper 16 Bits. If the I/O Base register indicates support for 16-bit I/O address decoding then this register is implemented as a read-only register which return zero when read. If the I/O base register indicates support for 32-bit.." group.long 0x34++0xB line.long 0x0 "TYPE1_CAP_PTR_REG,Capabilities Pointer Register." hexmask.long.tbyte 0x0 8.--31. 1. "RSVDP_8,Reserved for future use." newline hexmask.long.byte 0x0 0.--7. 1. "CAP_POINTER,Capabilities Pointer. This register is used to point to a linked list of capabilities implemented by this Function. Since all PCI Express Functions are required to implement the PCI Express Capability structure this register must point to a.." line.long 0x4 "TYPE1_EXP_ROM_BASE_REG,Expansion ROM Base Address Register. This register is defined to handle the base address and size information for this expansion ROM. The mask for this ROM BAR exists (if implemented) as a shadow register at this address. The.." hexmask.long.tbyte 0x4 11.--31. 1. "EXP_ROM_BASE_ADDRESS,Expansion ROM Base Address. Upper 21 bits of the Expansion ROM base address. The number of bits (out of these 21) that a Function actually implements depends on how much address space the Function requires. The mask for this ROM BAR.." newline hexmask.long.word 0x4 1.--10. 1. "RSVDP_1,Reserved for future use." newline bitfld.long 0x4 0. "ROM_BAR_ENABLE,Expansion ROM Enable. This bit controls whether or not the Function accepts accesses to its expansion ROM. When this bit is 0b the Function's expansion ROM address space is disabled. When the bit is 1b address decoding is enabled using.." "0,1" line.long 0x8 "BRIDGE_CTRL_INT_PIN_INT_LINE_REG,Bridge Control. Interrupt Pin. and Interrupt Line Register." hexmask.long.word 0x8 23.--31. 1. "BRIDGE_CTRL_RESERV,Reserved." newline bitfld.long 0x8 22. "SBR,Secondary Bus Reset. Setting this bit triggers a hot reset on the corresponding PCI Express Port. Software must ensure a minimum reset duration (Trst) as defined in the PCI Local Bus Specification. Software and systems must honor.." "0,1" newline rbitfld.long 0x8 21. "MSTR_ABORT_MODE,Master Abort Mode. This bit was originally described in the PCI-to-PCI Bridge Architecture Specification. Its functionality does not apply to PCI Express. The controller hardwires this bit to 0b. Note: The access attributes of this field.." "0,1" newline rbitfld.long 0x8 20. "VGA_16B_DEC,VGA 16 bit decode. This bit only has meaning if VGA Enable bit is set. This bit enables system configuration software to select between 10-bit and 16-bit I/O address decoding for all VGA I/O register accesses that are forwarded from primary.." "0,1" newline rbitfld.long 0x8 19. "VGA_EN,VGA Enable. Modifies the response by the bridge to VGA compatible addresses. If the VGA Enable bit is set the bridge will positively decode and forward the following accesses on the primary interface to the secondary interface (and conversely.." "0,1" newline bitfld.long 0x8 18. "ISA_EN,ISA Enable. Modifies the response by the bridge to ISA I/O addresses. This applies only to I/O addresses that are enabled by the I/O Base and I/O Limit registers and are in the first 64 KB of I/O address space (0000 0000h to 0000 FFFFh). If this.." "?,KB block" newline bitfld.long 0x8 17. "SERR_EN,SERR# Enable. This bit controls forwarding of ERR_COR ERR_NONFATAL and ERR_FATAL from secondary to primary." "0,1" newline bitfld.long 0x8 16. "PERE,Parity Error Response Enable. This bit controls the logging of poisoned TLPs in the Master Data Parity Error bit in the Secondary Status register." "0,1" newline hexmask.long.byte 0x8 8.--15. 1. "INT_PIN,Interrupt PIN. The Interrupt Pin register register that identifies the legacy interrupt Message(s) the Function uses. Valid values are: - 01h 02h 03h and 04h: map to legacy interrupt Messages for INTA INTB INTC and INTD respectively. - 00h:.." newline hexmask.long.byte 0x8 0.--7. 1. "INT_LINE,Interrupt Line. The Interrupt Line register communicates interrupt line routing information. The register must be implemented by any Function that uses an interrupt pin. Values in this register are programmed by system software and are system.." tree.end tree "PF0_SPCIE_CAP (Secondary PCI Express Capability Structure)" group.long (0x0+0x1A0)++0xF line.long 0x0 "SPCIE_CAP_HEADER_REG,SPCIE Capability Header. For a description of this standard PCIe register. see the PCI Express Specification." hexmask.long.word 0x0 20.--31. 1. "NEXT_OFFSET,Next Capability Offset. For a description of this standard PCIe register field see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky).." hexmask.long.byte 0x0 16.--19. 1. "CAP_VERSION,Capability Version. For a description of this standard PCIe register field see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else.." hexmask.long.word 0x0 0.--15. 1. "EXTENDED_CAP_ID,Secondary PCI Express Extended Capability ID. For a description of this standard PCIe register field see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN.." line.long 0x4 "LINK_CONTROL3_REG,Link Control 3 Register. For a description of this standard PCIe register. see the PCI Express Specification." hexmask.long 0x4 2.--31. 1. "RSVDP_2,Reserved for future use." bitfld.long 0x4 1. "EQ_REQ_INT_EN,Link Equalization Request Interrupt Enable. For a description of this standard PCIe register field see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" "0,1" bitfld.long 0x4 0. "PERFORM_EQ,Perform Equalization. For a description of this standard PCIe register field see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" "0,1" line.long 0x8 "LANE_ERR_STATUS_REG,Lane Error Status Register. For a description of this standard PCIe register. see the PCI Express Specification." hexmask.long 0x8 2.--31. 1. "RSVDP_LANE_ERR_STATUS,Reserved for future use." bitfld.long 0x8 0.--1. "LANE_ERR_STATUS,Lane Error Status Bits per Lane. For a description of this standard PCIe register field see the PCI Express Specification." "0,1,2,3" line.long 0xC "SPCIE_CAP_OFF_0CH_REG,Lane Equalization Control Register for lanes 1 and 0. For a description of this standard PCIe register. see the PCI Express Specification." rbitfld.long 0xC 31. "RSVDP_31,Reserved for future use." "0,1" bitfld.long 0xC 28.--30. "USP_RX_PRESET_HINT1,Upstream Port 8.0 GT/s Receiver Preset Hint 1. The write value is gated with the PCIE_CAP_CROSS_LINK_SUPPORT field of LINK_CAPABILITIES2_REG. For a description of this standard PCIe register field see the PCI Express Specification." "0,1,2,3,4,5,6,7" hexmask.long.byte 0xC 24.--27. 1. "USP_TX_PRESET1,Upstream Port 8.0 GT/s Transmitter Preset 1. The write value is gated with the PCIE_CAP_CROSS_LINK_SUPPORT field of LINK_CAPABILITIES2_REG. For a description of this standard PCIe register field see the PCI Express Specification. Note:.." rbitfld.long 0xC 23. "RSVDP_23,Reserved for future use." "0,1" newline bitfld.long 0xC 20.--22. "DSP_RX_PRESET_HINT1,Downstream Port 8.0 GT/s Receiver Preset Hint 1. For a description of this standard PCIe register field see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if.." "0,1,2,3,4,5,6,7" hexmask.long.byte 0xC 16.--19. 1. "DSP_TX_PRESET1,Downstream Port 8.0 GT/s Transmitter Preset 1. For a description of this standard PCIe register field see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN.." rbitfld.long 0xC 15. "RSVDP_15,Reserved for future use." "0,1" bitfld.long 0xC 12.--14. "USP_RX_PRESET_HINT0,Upstream Port 8.0 GT/s Receiver Preset Hint 0. The write value is gated with the PCIE_CAP_CROSS_LINK_SUPPORT field of LINK_CAPABILITIES2_REG. For a description of this standard PCIe register field see the PCI Express Specification." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0xC 8.--11. 1. "USP_TX_PRESET0,Upstream Port 8.0 GT/s Transmitter Preset 0. The write value is gated with the PCIE_CAP_CROSS_LINK_SUPPORT field of LINK_CAPABILITIES2_REG. For a description of this standard PCIe register field see the PCI Express Specification. Note:.." rbitfld.long 0xC 7. "RSVDP_7,Reserved for future use." "0,1" bitfld.long 0xC 4.--6. "DSP_RX_PRESET_HINT0,Downstream Port 8.0 GT/s Receiver Preset Hint 0. For a description of this standard PCIe register field see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if.." "0,1,2,3,4,5,6,7" hexmask.long.byte 0xC 0.--3. 1. "DSP_TX_PRESET0,Downstream Port 8.0 GT/s Transmitter Preset 0. For a description of this standard PCIe register field see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN.." tree.end tree "PF0_L1SUB_CAP (L1 Substates Capability Structure)" group.long (0x0+0x2E8)++0xF line.long 0x0 "L1SUB_CAP_HEADER_REG,L1 Substates Extended Capability Header. This register provides capbility ID. capability version and next offset value for L1 Substates." hexmask.long.word 0x0 20.--31. 1. "NEXT_OFFSET,Next Capability Offset. This field contains the offset to the next PCI Express Capability structure or 000h if no other items exist in the linked list of Capabilities. For Extended Capabilities implemented in Configuration Space this offset.." hexmask.long.byte 0x0 16.--19. 1. "CAP_VERSION,Capability Version. This field is a PCI-SIG defined version number that indicates the version of the Capability structure present. This field is depends on version of the specification. Note: The access attributes of this field are as.." hexmask.long.word 0x0 0.--15. 1. "EXTENDED_CAP_ID,L1SUB Extended Capability ID. This field is a PCI-SIG defined ID number that indicates the nature and format of the Extended Capability. Extended Capability ID for L1 PM Substates is 001Eh. Note: The access attributes of this field are as.." line.long 0x4 "L1SUB_CAPABILITY_REG,L1 Substates Capability Register. This register provides extended capability of L1 Substates." hexmask.long.byte 0x4 24.--31. 1. "RSVDP_24,Reserved for future use." hexmask.long.byte 0x4 19.--23. 1. "PWR_ON_VALUE_SUPPORT,Port T Power On Value. Along with the Port T_POWER_ON Scale field in the L1 PM Substates Capabilities register sets the time (in us) that this Port requires the port on the opposite side of Link to wait in L1.2.Exit after sampling.." rbitfld.long 0x4 18. "RSVDP_18,Reserved for future use." "0,1" bitfld.long 0x4 16.--17. "PWR_ON_SCALE_SUPPORT,Port T Power On Scale. Specifies the scale used for the Port T_POWER_ON Value field in the L1 PM Substates Capabilities register. Range of values are given below. Required for all Ports for which either the PCI-PM L1.2 Supported bit.." "?,?,?,Reserved" newline hexmask.long.byte 0x4 8.--15. 1. "COMM_MODE_SUPPORT,Port Common Mode Restore Time. Time (in us) required for this Port to re-establish common mode. Required for all Ports for which either the PCI-PM L1.2 Supported bit is Set ASPM L1.2 Supported bit is Set or both are Set otherwise.." rbitfld.long 0x4 5.--7. "RSVDP_5,Reserved for future use." "0,1,2,3,4,5,6,7" bitfld.long 0x4 4. "L1_PMSUB_SUPPORT,L1 PM Substates ECN Supported. When Set this bit indicates that this Port supports L1 PM Substates. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W (sticky)" "0,1" bitfld.long 0x4 3. "L1_1_ASPM_SUPPORT,ASPM L11 Supported. When Set this bit indicates that ASPM L1.1 is supported. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W (sticky)" "0,1" newline bitfld.long 0x4 2. "L1_2_ASPM_SUPPORT,ASPM L12 Supported. When Set this bit indicates that ASPM L1.2 is supported. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W (sticky)" "0,1" bitfld.long 0x4 1. "L1_1_PCIPM_SUPPORT,PCI-PM L11 Supported. When Set this bit indicates that PCI-PM L1.1 is supported and must be Set by all Ports implementing L1 PM Substates. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W (sticky)" "0,1" bitfld.long 0x4 0. "L1_2_PCIPM_SUPPORT,PCI-PM L12 Supported. When Set this bit indicates that PCI-PM L1.2 is supported. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W (sticky)" "0,1" line.long 0x8 "L1SUB_CONTROL1_REG,L1 Substates Control 1 Register. This register provides Controls to extended capability." bitfld.long 0x8 29.--31. "L1_2_TH_SCA,LTR L12 Threshold Scale. This field provides a scale for the value contained within the LTR_L1.2_THRESHOLD_Value.The default value for this field is 000b.Hardware operation is undefined if software writes a Not-Permitted value to this field." "0,1,2,3,4,5,6,7" rbitfld.long 0x8 26.--28. "RSVDP_26,Reserved for future use." "0,1,2,3,4,5,6,7" hexmask.long.word 0x8 16.--25. 1. "L1_2_TH_VAL,LTR L12 Threshold Value. Along with the LTR_L1.2_THRESHOLD_Scale this field indicates the LTR threshold used to determine if entry into L1 results in L1.1 (if enabled) or L1.2 (if enabled). The default value for this field is 00 0000 0000b." hexmask.long.byte 0x8 8.--15. 1. "T_COMMON_MODE,Common Mode Restore Time. Sets value of TCOMMONMODE (in us) which must be used by the Downstream Ports for timing the re-establishment of common mode.This field is of type RsvdP for Upstream Ports. Default value is implementation.." newline hexmask.long.byte 0x8 4.--7. 1. "RSVDP_4,Reserved for future use." bitfld.long 0x8 3. "L1_1_ASPM_EN,ASPM L11 Enable. When Set this bit enables ASPM L1.1.For Ports for which the ASPM L1.1 Supported bit is Clear this bit is permitted to be hardwired to 0.Default value is 0b." "0,1" bitfld.long 0x8 2. "L1_2_ASPM_EN,ASPM L12 Enable. When Set this bit enables ASPM L1.2.For Ports for which the ASPM L1.2 Supported bit is Clear this bit is permitted to be hardwired to 0.Default value is 0b." "0,1" bitfld.long 0x8 1. "L1_1_PCIPM_EN,PCI-PM L11 Enable. When Set this bit enables PCI-PM L1.1. Default value is 0b." "0,1" newline bitfld.long 0x8 0. "L1_2_PCIPM_EN,PCI-PM L12 Enable. When Set this bit enables PCI-PM L1.2.For Ports for which the PCI-PM L1.2 Supported bit is Clear this bit is permitted to be hardwired to 0.Default value is 0b." "0,1" line.long 0xC "L1SUB_CONTROL2_REG,L1 Substates Control 2 Register. This register provides Controls to extended capability." hexmask.long.tbyte 0xC 8.--31. 1. "RSVDP_8,Reserved for future use." hexmask.long.byte 0xC 3.--7. 1. "T_POWER_ON_VALUE,T Power On Value. Along with the T_POWER_ON Scale sets the minimum amount of time (in us) that the Port must wait in L1.2.Exit after sampling CLKREQ# asserted before actively driving the interface.Default value is 00101b. T_POWER_ON is.." rbitfld.long 0xC 2. "RSVDP_2,Reserved for future use." "0,1" bitfld.long 0xC 0.--1. "T_POWER_ON_SCALE,T Power On Scale. Specifies the scale used for T_POWER_ON Value. Range of values are given below. Required for all Ports that support L1.2 otherwise this field is of type RsvdP. This field must only be modified when the ASPM L1.2 Enable.." "?,?,?,Reserved" tree.end tree "PF0_RAS_DES_CAP (RAS D.E.S. Capability Structure (VSEC))" group.long (0x0+0x30C)++0x3 line.long 0x0 "RAS_DES_CAP_HEADER_REG,Vendor-Specific Extended Capability Header. For a description of this standard PCIe register. see the PCI Express Specification." hexmask.long.word 0x0 20.--31. 1. "NEXT_OFFSET,Next Capability Offset. For a description of this standard PCIe register field see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky).." newline hexmask.long.byte 0x0 16.--19. 1. "CAP_VERSION,Capability Version. For a description of this standard PCIe register field see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else.." newline hexmask.long.word 0x0 0.--15. 1. "EXTENDED_CAP_ID,PCI Express Extended Capability ID. For a description of this standard PCIe register field see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then.." rgroup.long (0x4+0x30C)++0x3 line.long 0x0 "VENDOR_SPECIFIC_HEADER_REG,Vendor-Specific Header. For a description of this standard PCIe register. see the PCI Express Specification." hexmask.long.word 0x0 20.--31. 1. "VSEC_LENGTH,VSEC Length. For a description of this standard PCIe register field see the PCI Express Specification." newline hexmask.long.byte 0x0 16.--19. 1. "VSEC_REV,VSEC Rev. For a description of this standard PCIe register field see the PCI Express Specification." newline hexmask.long.word 0x0 0.--15. 1. "VSEC_ID,VSEC ID. For a description of this standard PCIe register field see the PCI Express Specification." group.long (0x8+0x30C)++0x3 line.long 0x0 "EVENT_COUNTER_CONTROL_REG,Event Counter Control. This is a viewport control register. - Setting the EVENT_COUNTER_EVENT_SELECT and EVENT_COUNTER_LANE_SELECT fields in this register determine the Event Counter data returned by the EVENT_COUNTER_DATA_REG.." hexmask.long.byte 0x0 28.--31. 1. "RSVDP_28,Reserved for future use." newline hexmask.long.word 0x0 16.--27. 1. "EVENT_COUNTER_EVENT_SELECT,Event Counter Data Select. This field in conjunction with the EVENT_COUNTER_LANE_SELECT field indexes the Event Counter data returned by the EVENT_COUNTER_DATA_REG register. - 27-24: Group number(4-bit: 0..0x7) - 23-16: Event.." newline hexmask.long.byte 0x0 12.--15. 1. "RSVDP_12,Reserved for future use." newline hexmask.long.byte 0x0 8.--11. 1. "EVENT_COUNTER_LANE_SELECT,Event Counter Lane Select. This field in conjunction with EVENT_COUNTER_EVENT_SELECT indexes the Event Counter data returned by the EVENT_COUNTER_DATA_REG register. - 0x0: Lane0 - 0x1: Lane1 - 0x2: Lane2 - .. - 0xF: Lane15 Note:.." newline rbitfld.long 0x0 7. "EVENT_COUNTER_STATUS,Event Counter Status. This register returns the current value of the Event Counter selected by the following fields: - EVENT_COUNTER_EVENT_SELECT - EVENT_COUNTER_LANE_SELECT Note: This register field is sticky." "0,1" newline rbitfld.long 0x0 5.--6. "RSVDP_5,Reserved for future use." "0,1,2,3" newline bitfld.long 0x0 2.--4. "EVENT_COUNTER_ENABLE,Event Counter Enable. Enables/disables the Event Counter selected by the EVENT_COUNTER_EVENT_SELECT and EVENT_COUNTER_LANE_SELECT fields in this register. By default all event counters are disabled. You can enable/disable a specific.." "no change,per event off,?,?,?,?,?,?" newline bitfld.long 0x0 0.--1. "EVENT_COUNTER_CLEAR,Event Counter Clear. Clears the Event Counter selected by the EVENT_COUNTER_EVENT_SELECT and EVENT_COUNTER_LANE_SELECT fields in this register. You can clear the value of a specific Event Counter by writing the 'per clear' code and.." "no change,per clear,?,?" rgroup.long (0xC+0x30C)++0x3 line.long 0x0 "EVENT_COUNTER_DATA_REG,Event Counter Data. This viewport register returns the data selected by the following fields: - EVENT_COUNTER_EVENT_SELECT in EVENT_COUNTER_CONTROL_REG - EVENT_COUNTER_LANE_SELECT in EVENT_COUNTER_CONTROL_REG For more details. see.." hexmask.long 0x0 0.--31. 1. "EVENT_COUNTER_DATA,Event Counter Data. This register returns the data selected by the following fields: - EVENT_COUNTER_EVENT_SELECT in EVENT_COUNTER_CONTROL_REG - EVENT_COUNTER_LANE_SELECT in EVENT_COUNTER_CONTROL_REG Note: This register field is sticky." group.long (0x10+0x30C)++0x3 line.long 0x0 "TIME_BASED_ANALYSIS_CONTROL_REG,Time-based Analysis Control. Used for controlling the measurement of RX/TX data throughput and time spent in each low-power LTSSM state. For more details. see the RAS DES section in the Core Operations chapter of the.." hexmask.long.byte 0x0 24.--31. 1. "TIME_BASED_REPORT_SELECT,Time-based Report Select. Selects what type of data is measured for the selected duration (TIME_BASED_DURATION_SELECT) and returned in TIME_BASED_ANALYSIS_DATA. Each type of data is measured using one of three types of units: -.." newline hexmask.long.byte 0x0 16.--23. 1. "RSVDP_16,Reserved for future use." newline hexmask.long.byte 0x0 8.--15. 1. "TIME_BASED_DURATION_SELECT,Time-based Duration Select. Selects the duration of time-based analysis. When 'manual control' is selected and TIMER_START is set to '1' this analysis never stops until TIMER_STOP is set to '0'. - 0x0: Manual control - 0x1:.." newline hexmask.long.byte 0x0 1.--7. 1. "RSVDP_1,Reserved for future use." newline bitfld.long 0x0 0. "TIMER_START,Timer Start. - 1: Start/Restart - 0: Stop This bit will be cleared automatically when the measurement is finished. Note: The app_ras_des_tba_ctrl input also sets the contents of this field and controls the measurement start/stop. Note: This.." "Stop,Start/Restart" rgroup.long (0x14+0x30C)++0x7 line.long 0x0 "TIME_BASED_ANALYSIS_DATA_REG,Time-based Analysis Data. Contains the measurement results of RX/TX data throughput and time spent in each low-power LTSSM state. This viewport register returns the data selected by the TIME_BASED_REPORT_SELECT field in.." hexmask.long 0x0 0.--31. 1. "TIME_BASED_ANALYSIS_DATA,Time Based Analysis Data. This register returns the data selected by the TIME_BASED_REPORT_SELECT field in TIME_BASED_ANALYSIS_CONTROL_REG. The results are cleared when next measurement starts. Note: This register field is sticky." line.long 0x4 "TIME_BASED_ANALYSIS_DATA_63_32_REG,Upper 32 bits of Time-based Analysis Data. This viewport register returns the data selected by the TIME_BASED_REPORT_SELECT field in TIME_BASED_ANALYSIS_CONTROL_REG. For more details. see the RAS DES section in the Core.." hexmask.long 0x4 0.--31. 1. "TIME_BASED_ANALYSIS_DATA_63_32,Upper 32 bits of Time Based Analysis Data. Note: This register field is sticky." group.long (0x30+0x30C)++0x5F line.long 0x0 "EINJ_ENABLE_REG,Error Injection Enable. Each type of error insertion is enabled by the corresponding bit in this register. The specific injection controls for each type of error are defined in the following registers: - 0: CRC Error: EINJ0_CRC_REG - 1:.." hexmask.long 0x0 7.--31. 1. "RSVDP_7,Reserved for future use." newline bitfld.long 0x0 6. "ERROR_INJECTION6_ENABLE,Error Injection6 Enable (Specific TLP Error). Enables insertion of errors into the packets that you select. You can set this bit to '1' when you have disabled RAS datapath protection (DP) by setting CX_RASDP = CX_RASDP_RAM_PROT.." "0,1" newline bitfld.long 0x0 5. "ERROR_INJECTION5_ENABLE,Error Injection5 Enable (TLP Duplicate/Nullify Error). Enables insertion of duplicate/nullified TLPs. For more details see the EINJ5_SP_TLP_REG register. Note: This register field is sticky." "0,1" newline bitfld.long 0x0 4. "ERROR_INJECTION4_ENABLE,Error Injection4 Enable (FC Credit Update Error). Enables insertion of errors into UpdateFCs. For more details see the EINJ4_FC_REG register. Note: This register field is sticky." "0,1" newline bitfld.long 0x0 3. "ERROR_INJECTION3_ENABLE,Error Injection3 Enable (Symbol DataK Mask Error or Sync Header Error). Enables DataK masking of special symbols or the breaking of the sync header. For more details see the EINJ3_SYMBOL_REG register. Note: This register field is.." "0,1" newline bitfld.long 0x0 2. "ERROR_INJECTION2_ENABLE,Error Injection2 Enable (DLLP Error). Enables insertion of DLLP errors. For more details see the EINJ2_DLLP_REG register. Note: This register field is sticky." "0,1" newline bitfld.long 0x0 1. "ERROR_INJECTION1_ENABLE,Error Injection1 Enable (Sequence Number Error). Enables insertion of errors into sequence numbers. For more details see the EINJ1_SEQNUM_REG register. Note: This register field is sticky." "0,1" newline bitfld.long 0x0 0. "ERROR_INJECTION0_ENABLE,Error Injection0 Enable (CRC Error). Enables insertion of errors into various CRC. For more details see the EINJ0_CRC_REG register. Note: This register field is sticky." "0,1" line.long 0x4 "EINJ0_CRC_REG,Error Injection Control 0 (CRC Error). Controls the insertion of errors into the CRC. and parity of ordered sets for the selected type of the packets as follows: - LCRC. Bad TLP will be detected at the receiver side; receiver responds with.." hexmask.long.tbyte 0x4 12.--31. 1. "RSVDP_12,Reserved for future use." newline hexmask.long.byte 0x4 8.--11. 1. "EINJ0_CRC_TYPE,Error injection type. Selects the type of CRC error to be inserted. Tx Path - 0000b: New TLP's LCRC error injection - 0001b: 16bCRC error injection of ACK/NAK DLLP - 0010b: 16bCRC error injection of Update-FC DLLP - 0011b: New TLP's ECRC.." newline hexmask.long.byte 0x4 0.--7. 1. "EINJ0_COUNT,Error injection count. Indicates the number of errors. This register is decremented when the errors have been inserted. - If the counter value is 0x01 and error is inserted ERROR_INJECTION0_ENABLE in EINJ_ENABLE_REG returns 0b. - If the.." line.long 0x8 "EINJ1_SEQNUM_REG,Error Injection Control 1 (Sequence Number Error). Controls the sequence number of the specific TLPs and ACK/NAK DLLPs. Data Link Protocol Error will be detected at the Rx side of ACK/NAL DLLPs when one of these conditions is true: -.." rbitfld.long 0x8 29.--31. "RSVDP_29,Reserved for future use." "0,1,2,3,4,5,6,7" newline hexmask.long.word 0x8 16.--28. 1. "EINJ1_BAD_SEQNUM,Bad sequence number. Indicates the value to add/subtract from the naturally-assigned sequence numbers. This value is represented by two's complement. - 0x0FFF: +4095 - .. - 0x0002: +2 - 0x0001: +1 - 0x0000: 0 - 0x1FFF: -1 - 0x1FFE: -2 -.." newline hexmask.long.byte 0x8 9.--15. 1. "RSVDP_9,Reserved for future use." newline bitfld.long 0x8 8. "EINJ1_SEQNUM_TYPE,Sequence number type. Selects the type of sequence number. - 0b: Insertion of New TLP's SEQ# error - 1b: Insertion of ACK/NAK DLLP's SEQ# Error Note: This register field is sticky." "0,1" newline hexmask.long.byte 0x8 0.--7. 1. "EINJ1_COUNT,Error injection count. Indicates the number of errors. This register is decremented as the errors are being inserted. - If the counter value is 0x01 and error is inserted ERROR_INJECTION1_ENABLE in EINJ_ENABLE_REG returns '0'. - If the.." line.long 0xC "EINJ2_DLLP_REG,Error Injection Control 2 (DLLP Error). Controls the transmission of DLLPs and inserts the following errors: - If 'ACK/NAK DLLP's transmission block' is selected. replay timeout error will occur at the transmitter of the TLPs and then Data.." hexmask.long.tbyte 0xC 10.--31. 1. "RSVDP_10,Reserved for future use." newline bitfld.long 0xC 8.--9. "EINJ2_DLLP_TYPE,DLLP Type. Selects the type of DLLP errors to be inserted. - 00b: ACK/NAK DLLP's transmission block - 01b: Update FC DLLP's transmission block - 10b: Always Transmission for NAK DLLP - 11b: Reserved Note: This register field is sticky." "0,1,2,3" newline hexmask.long.byte 0xC 0.--7. 1. "EINJ2_COUNT,Error injection count. Indicates the number of errors. This register is decremented as the errors are being inserted. - If the counter value is 0x01 and the error is inserted ERROR_INJECTION2_ENABLE in EINJ_ENABLE_REG returns '0'. - If the.." line.long 0x10 "EINJ3_SYMBOL_REG,Error Injection Control 3 (Symbol Error). When 8b/10b encoding is used. this register controls error insertion into the special (K code) symbols. - If TS1/TS2/FTS/E-Idle/SKP is selected. it affects whole of the ordered set. It might.." hexmask.long.tbyte 0x10 11.--31. 1. "RSVDP_11,Reserved for future use." newline bitfld.long 0x10 8.--10. "EINJ3_SYMBOL_TYPE,Error Type. 8b/10b encoding - Mask K symbol. It is not supported to insert errors into the first ordered-set after exiting from TxElecIdle when CX_FREQ_STEP_EN has been enabled. - 000b: Reserved - 001b: COM/PAD(TS1 Order set) - 010b:.." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x10 0.--7. 1. "EINJ3_COUNT,Error injection count. Indicates the number of errors. This register is decremented as the errors are being inserted. - If the counter value is 0x01 and error is inserted ERROR_INJECTION3_ENABLE in EINJ_ENABLE_REG returns '0'. - If the.." line.long 0x14 "EINJ4_FC_REG,Error Injection Control 4 (FC Credit Error). Controls error insertion into the credit value in the UpdateFCs. It is possible to insert errors for any of the following types: - Posted TLP Header credit - Non-Posted TLP Header credit -.." rbitfld.long 0x14 29.--31. "RSVDP_29,Reserved for future use." "0,1,2,3,4,5,6,7" newline hexmask.long.word 0x14 16.--28. 1. "EINJ4_BAD_UPDFC_VALUE,Bad update-FC credit value. Indicates the value to add/subtract from the UpdateFC credit. This value is represented by two's complement. - 0x0FFF: +4095 - .. - 0x0002: +2 - 0x0001: +1 - 0x0000: 0 - 0x1FFF: -1 - 0x1FFE: -2 - .. -.." newline rbitfld.long 0x14 15. "RSVDP_15,Reserved for future use." "0,1" newline bitfld.long 0x14 12.--14. "EINJ4_VC_NUMBER,VC Number. Indicates target VC Number. Note: This register field is sticky." "0,1,2,3,4,5,6,7" newline rbitfld.long 0x14 11. "RSVDP_11,Reserved for future use." "0,1" newline bitfld.long 0x14 8.--10. "EINJ4_UPDFC_TYPE,Update-FC type. Selects the credit type. - 000b: Posted TLP Header Credit value control - 001b: Non-Posted TLP Header Credit value control - 010b: Completion TLP Header Credit value control - 011b: Reserved - 100b: Posted TLP Data Credit.." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x14 0.--7. 1. "EINJ4_COUNT,Error injection count. Indicates the number of errors. This register is decremented as the errors are being inserted. - If the counter value is 0x01 and error is inserted ERROR_INJECTION4_ENABLE in EINJ_ENABLE_REG returns '0'. - If the.." line.long 0x18 "EINJ5_SP_TLP_REG,Error Injection Control 5 (Specific TLP Error). Controls the generation of specified TLPs. Correctable errors will occur which will be fixed by the PCIe protocol. - For Duplicate TLP. the controller initiates Data Link Retry by handling.." hexmask.long.tbyte 0x18 9.--31. 1. "RSVDP_9,Reserved for future use." newline bitfld.long 0x18 8. "EINJ5_SPECIFIED_TLP,Specified TLP. Selects the specified TLP to be inserted. - 0: Generates duplicate TLPs by handling ACK DLLP as NAK DLLP. - 1: Generates Nullified TLP (Original TLP will be stored in retry buffer). Note: This register field is sticky." "Generates duplicate TLPs by handling ACK DLLP as..,Generates Nullified TLP" newline hexmask.long.byte 0x18 0.--7. 1. "EINJ5_COUNT,Error injection count. Indicates the number of errors. This register is decremented as the errors are being inserted. - If the counter value is 0x01 and error is inserted ERROR_INJECTION5_ENABLE in EINJ_ENABLE_REG returns '0'. - If the.." line.long 0x1C "EINJ6_COMPARE_POINT_H0_REG,Error Injection Control 6 (Compare Point Header DWORD #0). Program this register for the 1st DWORD of TLP header/prefix. It is necessary to carefully consider the endianness when you program this register. Bits [31:0] =.." hexmask.long 0x1C 0.--31. 1. "EINJ6_COMPARE_POINT_H0,Packet Compare Point: 1st DWORD. Specifies which Tx TLP header DWORD#0 bits to compare with the corresponding bits in the Packet Compare Value registers (EINJ6_COMPARE_VALUE*). When all specified bits (in the Tx TLP header and.." line.long 0x20 "EINJ6_COMPARE_POINT_H1_REG,Error Injection Control 6 (Compare Point Header DWORD #1). Program this register for the 2nd DWORD of TLP header/prefix. It is necessary to carefully consider the endianness when you program this register. Bits [31:0] =.." hexmask.long 0x20 0.--31. 1. "EINJ6_COMPARE_POINT_H1,Packet Compare Point: 2nd DWORD. Specifies which Tx TLP header DWORD#1 bits to compare with the corresponding bits in the Packet Compare Value registers (EINJ6_COMPARE_VALUE*). When all specified bits (in the Tx TLP header and.." line.long 0x24 "EINJ6_COMPARE_POINT_H2_REG,Error Injection Control 6 (Compare Point Header DWORD #2). Program this register for the 3rd DWORD of TLP header/prefix. It is necessary to carefully consider the endianness when you program this register. Bits [31:0] =.." hexmask.long 0x24 0.--31. 1. "EINJ6_COMPARE_POINT_H2,Packet Compare Point: 3rd DWORD. Specifies which Tx TLP header DWORD#2 bits to compare with the corresponding bits in the Packet Compare Value registers (EINJ6_COMPARE_VALUE*). When all specified bits (in the Tx TLP header and.." line.long 0x28 "EINJ6_COMPARE_POINT_H3_REG,Error Injection Control 6 (Compare Point Header DWORD #3). Program this register for the 4th DWORD of TLP header/prefix. It is necessary to carefully consider the endianness when you program this register. Bits [31:0] =.." hexmask.long 0x28 0.--31. 1. "EINJ6_COMPARE_POINT_H3,Packet Compare Point: 4th DWORD. Specifies which Tx TLP header DWORD#3 bits to compare with the corresponding bits in the Packet Compare Value registers (EINJ6_COMPARE_VALUE*). When all specified bits (in the Tx TLP header and.." line.long 0x2C "EINJ6_COMPARE_VALUE_H0_REG,Error Injection Control 6 (Compare Value Header DWORD #0). Program this register for the 1st DWORD of TLP header/prefix. It is necessary to carefully consider the endianness when you program this register. Bits [31:0] =.." hexmask.long 0x2C 0.--31. 1. "EINJ6_COMPARE_VALUE_H0,Packet Compare Value: 1st DWORD. Specifies the value to compare against Tx the TLP header DWORD#0 bits specified in the Packet Compare Point registers (EINJ6_COMPARE_POINT*). Note: This register field is sticky." line.long 0x30 "EINJ6_COMPARE_VALUE_H1_REG,Error Injection Control 6 (Compare Value Header DWORD #1). Program this register for the 2nd DWORD of TLP header/prefix. It is necessary to carefully consider the endianness when you program this register. Bits [31:0] =.." hexmask.long 0x30 0.--31. 1. "EINJ6_COMPARE_VALUE_H1,Packet Compare Value: 2nd DWORD. Specifies the value to compare against Tx the TLP header DWORD#1 bits specified in the Packet Compare Point registers (EINJ6_COMPARE_POINT*). Note: This register field is sticky." line.long 0x34 "EINJ6_COMPARE_VALUE_H2_REG,Error Injection Control 6 (Compare Value Header DWORD #2). Program this register for the 3rd DWORD of TLP header/prefix. It is necessary to carefully consider the endianness when you program this register. Bits [31:0] =.." hexmask.long 0x34 0.--31. 1. "EINJ6_COMPARE_VALUE_H2,Packet Compare Value: 3rd DWORD. Specifies the value to compare against Tx the TLP header DWORD#2 bits specified in the Packet Compare Point registers (EINJ6_COMPARE_POINT*). Note: This register field is sticky." line.long 0x38 "EINJ6_COMPARE_VALUE_H3_REG,Error Injection Control 6 (Compare Value Header DWORD #3). Program this register for the 4th DWORD of TLP header/prefix. It is necessary to carefully consider the endianness when you program this register. Bits [31:0] =.." hexmask.long 0x38 0.--31. 1. "EINJ6_COMPARE_VALUE_H3,Packet Compare Value: 4th DWORD. Specifies the value to compare against Tx the TLP header DWORD#3 bits specified in the Packet Compare Point registers (EINJ6_COMPARE_POINT*). Note: This register field is sticky." line.long 0x3C "EINJ6_CHANGE_POINT_H0_REG,Error Injection Control 6 (Change Point Header DWORD #0). Program this register for the 1st DWORD of TLP header/prefix. It is necessary to carefully consider the endianness when you program this register. Bits [31:0] =.." hexmask.long 0x3C 0.--31. 1. "EINJ6_CHANGE_POINT_H0,Packet Change Point: 1st DWORD. Specifies which Tx TLP header DWORD#0 bits to replace with the corresponding bits in the Packet Change Value registers (EINJ6_CHANGE_VALUE*). Note: This register field is sticky." line.long 0x40 "EINJ6_CHANGE_POINT_H1_REG,Error Injection Control 6 (Change Point Header DWORD #1). Program this register for the 2nd DWORD of TLP header/prefix. It is necessary to carefully consider the endianness when you program this register. Bits [31:0] =.." hexmask.long 0x40 0.--31. 1. "EINJ6_CHANGE_POINT_H1,Packet Change Point: 2nd DWORD. Specifies which Tx TLP header DWORD#1 bits to replace with the corresponding bits in the Packet Change Value registers (EINJ6_CHANGE_VALUE*). Note: This register field is sticky." line.long 0x44 "EINJ6_CHANGE_POINT_H2_REG,Error Injection Control 6 (Change Point Header DWORD #2). Program this register for the 3rd DWORD of TLP header/prefix. It is necessary to carefully consider the endianness when you program this register. Bits [31:0] =.." hexmask.long 0x44 0.--31. 1. "EINJ6_CHANGE_POINT_H2,Packet Change Point: 3rd DWORD. Specifies which Tx TLP header DWORD#2 bits to replace with the corresponding bits in the Packet Change Value registers (EINJ6_CHANGE_VALUE*). Note: This register field is sticky." line.long 0x48 "EINJ6_CHANGE_POINT_H3_REG,Error Injection Control 6 (Change Point Header DWORD #3). Program this register for the 4th DWORD of TLP header/prefix. It is necessary to carefully consider the endianness when you program this register. Bits [31:0] =.." hexmask.long 0x48 0.--31. 1. "EINJ6_CHANGE_POINT_H3,Packet Change Point: 4th DWORD. Specifies which Tx TLP header DWORD#3 bits to replace with the corresponding bits in the Packet Change Value registers (EINJ6_CHANGE_VALUE*). Note: This register field is sticky." line.long 0x4C "EINJ6_CHANGE_VALUE_H0_REG,Error Injection Control 6 (Change Value Header DWORD #0). Program this register for the 1st DWORD of TLP header/prefix. It is necessary to carefully consider the endianness when you program this register. Bits [31:0] =.." hexmask.long 0x4C 0.--31. 1. "EINJ6_CHANGE_VALUE_H0,Packet Change Value: 1st DWORD. Specifies replacement values for the Tx TLP header DWORD#0 bits defined in the Packet Change Point registers (EINJ6_CHANGE_POINT*). Only applies when the EINJ6_INVERTED_CONTROL field in EINJ6_TLP_REG.." line.long 0x50 "EINJ6_CHANGE_VALUE_H1_REG,Error Injection Control 6 (Change Value Header DWORD #1). Program this register for the 2nd DWORD of TLP header/prefix. It is necessary to carefully consider the endianness when you program this register. Bits [31:0] =.." hexmask.long 0x50 0.--31. 1. "EINJ6_CHANGE_VALUE_H1,Packet Change Value: 2nd DWORD. Specifies replacement values for the Tx TLP header DWORD#1 bits defined in the Packet Change Point registers (EINJ6_CHANGE_POINT*). Only applies when the EINJ6_INVERTED_CONTROL field in EINJ6_TLP_REG.." line.long 0x54 "EINJ6_CHANGE_VALUE_H2_REG,Error Injection Control 6 (Change Value Header DWORD #2). Program this register for the 3rd DWORD of TLP header/prefix. It is necessary to carefully consider the endianness when you program this register. Bits [31:0] =.." hexmask.long 0x54 0.--31. 1. "EINJ6_CHANGE_VALUE_H2,Packet Change Value: 3rd DWORD. Specifies replacement values for the Tx TLP header DWORD#2 bits defined in the Packet Change Point registers (EINJ6_CHANGE_POINT*). Only applies when the EINJ6_INVERTED_CONTROL field in EINJ6_TLP_REG.." line.long 0x58 "EINJ6_CHANGE_VALUE_H3_REG,Error Injection Control 6 (Change Value Header DWORD #3). Program this register for the 4th DWORD of TLP header/prefix. It is necessary to carefully consider the endianness when you program this register. Bits [31:0] =.." hexmask.long 0x58 0.--31. 1. "EINJ6_CHANGE_VALUE_H3,Packet Change Value: 4th DWORD. Specifies replacement values for the Tx TLP header DWORD#3 bits defined in the Packet Change Point registers (EINJ6_CHANGE_POINT*). Only applies when the EINJ6_INVERTED_CONTROL field in EINJ6_TLP_REG.." line.long 0x5C "EINJ6_TLP_REG,Error Injection Control 6 (Packet Error). The Packet Compare Point registers (EINJ6_COMPARE_POINT*) specify which Tx TLP header bits to compare with the corresponding bits in the Packet Compare Value registers (EINJ6_COMPARE_VALUE*). When.." hexmask.long.tbyte 0x5C 12.--31. 1. "RSVDP_12,Reserved for future use." newline bitfld.long 0x5C 9.--11. "EINJ6_PACKET_TYPE,Packet type. Selects the TLP packets to inject errors into. - 0: TLP Header - 1: TLP Prefix 1st 4-DWORDs - 2: TLP Prefix 2nd -DWORDs - Else: Reserved Note: This register field is sticky." "TLP Header,TLP Prefix 1st 4-DWORDs,TLP Prefix 2nd -DWORDs,?,?,?,?,?" newline bitfld.long 0x5C 8. "EINJ6_INVERTED_CONTROL,Inverted Error Injection Control. - 0: EINJ6_CHANGE_VALUE_H[0/1/2/3] is used to replace bits specified by EINJ6_CHANGE_POINT_H[0/1/2/3]. - 1: EINJ6_CHANGE_VALUE_H[0/1/2/3] is ignored and inverts bits specified by.." "EINJ6_CHANGE_VALUE_H[0/1/2/3] is used to replace..,EINJ6_CHANGE_VALUE_H[0/1/2/3] is ignored and.." newline hexmask.long.byte 0x5C 0.--7. 1. "EINJ6_COUNT,Error Injection Count. Indicates the number of errors to insert. This counter is decremented while errors are been inserted. - If the counter value is 0x01 and error is inserted ERROR_INJECTION6_ENABLE in EINJ_ENABLE_REG returns '0'. - If.." group.long (0xA0+0x30C)++0x7 line.long 0x0 "SD_CONTROL1_REG,Silicon Debug Control 1. For more details. see the RAS DES section in the Core Operations chapter of the Databook." hexmask.long.byte 0x0 24.--31. 1. "RSVDP_24,Reserved for future use." newline bitfld.long 0x0 22.--23. "LOW_POWER_INTERVAL,Low Power Entry Interval Time. Interval Time that the controller starts monitoring RXELECIDLE signal after L0s/L1/L2 entry. You should set the value according to the latency from receiving EIOS to RXELECIDLE assertion at the PHY. -.." "0,1,2,3" newline bitfld.long 0x0 20.--21. "TX_EIOS_NUM,Number of Tx EIOS. This register sets the number of transmit EIOS for L0s/L1 entry and Disable/Loopback/Hot-reset exit. The controller selects the greater value between this register and the value defined by the PCI-SIG specification. 2.5GT/s.." "0,1,2,3" newline rbitfld.long 0x0 17.--19. "RSVDP_17,Reserved for future use." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 16. "FORCE_DETECT_LANE_EN,Force Detect Lane Enable. When this bit is set the controller ignores receiver detection from PHY during LTSSM Detect state and uses FORCE_DETECT_LANE. Note: This register field is sticky." "0,1" newline hexmask.long.word 0x0 0.--15. 1. "FORCE_DETECT_LANE,Force Detect Lane. When the FORCE_DETECT_LANE_EN field is set the controller ignores receiver detection from PHY during LTSSM Detect state and uses this value instead. - 0: Lane0 - 1: Lane1 - 2: Lane2 - .. - 15: Lane15 Note: This.." line.long 0x4 "SD_CONTROL2_REG,Silicon Debug Control 2. For more details. see the RAS DES section in the Core Operations chapter of the Databook." hexmask.long.word 0x4 17.--31. 1. "RSVDP_17,Reserved for future use." newline bitfld.long 0x4 16. "FRAMING_ERR_RECOVERY_DISABLE,Framing Error Recovery Disable. This bit disables a transition to Recovery state when a Framing Error is occurred. Note: This register field is sticky." "0,1" newline hexmask.long.byte 0x4 11.--15. 1. "RSVDP_11,Reserved for future use." newline bitfld.long 0x4 10. "DIRECT_LPBKSLV_TO_EXIT,Direct Loopback Slave To Exit. When this bit is set and the LTSSM is in Loopback Slave Active State the LTSSM transitions to Loopback Slave Exit state. Note: This register field is sticky." "0,1" newline bitfld.long 0x4 9. "DIRECT_POLCOMP_TO_DETECT,Direct Polling.Compliance to Detect. When this bit is set and the LTSSM is in Polling Compliance State the LTSSM transitions to Detect state. Note: This register field is sticky." "0,1" newline bitfld.long 0x4 8. "DIRECT_RECIDLE_TO_CONFIG,Direct Recovery.Idle to Configuration. When this bit is set and the LTSSM is in Recovery Idle State the LTSSM transitions to Configuration state. Note: This register field is sticky." "0,1" newline hexmask.long.byte 0x4 3.--7. 1. "RSVDP_3,Reserved for future use." newline bitfld.long 0x4 2. "NOACK_FORCE_LINKDOWN,Force LinkDown. When this bit is set and the controller detects REPLY_NUM rolling over 4 times the LTSSM transitions to Detect State. Note: This register field is sticky." "0,1" newline bitfld.long 0x4 1. "RECOVERY_REQUEST,Recovery Request. When this bit is set to '1' in L0 or L0s the LTSSM starts transitioning to Recovery State. This request does not cause a speed change or re-equalization." "0,1" newline bitfld.long 0x4 0. "HOLD_LTSSM,Hold and Release LTSSM. For as long as this register is '1' the controller stays in the current LTSSM. Note: This register field is sticky." "0,1" group.long (0xB0+0x30C)++0xB line.long 0x0 "SD_STATUS_L1LANE_REG,Silicon Debug Status(Layer1 Per-lane). This viewport register returns the data selected by the following field: - LANE_SELECT in SD_STATUS_L1LANE_REG For more details. see the RAS DES section in the Core Operations chapter of the.." hexmask.long.byte 0x0 24.--31. 1. "DESKEW_POINTER,Deskew Pointer. Indicates Deskew pointer of internal Deskew buffer of selected lane number(LANE_SELECT). Note: This register field is sticky." newline rbitfld.long 0x0 21.--23. "RSVDP_21,Reserved for future use." "0,1,2,3,4,5,6,7" newline rbitfld.long 0x0 20. "PIPE_TXELECIDLE,PIPE:TxElecIdle. Indicates PIPE TXELECIDLE signal of selected lane number(LANE_SELECT). Note: This register field is sticky." "0,1" newline rbitfld.long 0x0 19. "PIPE_RXELECIDLE,PIPE:RxElecIdle. Indicates PIPE RXELECIDLE signal of selected lane number(LANE_SELECT). Note: This register field is sticky." "0,1" newline rbitfld.long 0x0 18. "PIPE_RXVALID,PIPE:RxValid. Indicates PIPE RXVALID signal of selected lane number(LANE_SELECT). Note: This register field is sticky." "0,1" newline rbitfld.long 0x0 17. "PIPE_DETECT_LANE,PIPE:Detect Lane. Indicates whether PHY indicates receiver detection or not on selected lane number(LANE_SELECT). Note: This register field is sticky." "0,1" newline rbitfld.long 0x0 16. "PIPE_RXPOLARITY,PIPE:RxPolarity. Indicates PIPE RXPOLARITY signal of selected lane number(LANE_SELECT). Note: This register field is sticky." "0,1" newline hexmask.long.word 0x0 4.--15. 1. "RSVDP_4,Reserved for future use." newline hexmask.long.byte 0x0 0.--3. 1. "LANE_SELECT,Lane Select. Lane Select register for Silicon Debug Status Register of Layer1-PerLane. - 0x0: Lane0 - 0x1: Lane1 - 0x2: Lane2 - .. - 0xF: Lane15 Note: This register field is sticky." line.long 0x4 "SD_STATUS_L1LTSSM_REG,Silicon Debug Status(Layer1 LTSSM). For more details. see the RAS DES section in the Core Operations chapter of the Databook." hexmask.long.word 0x4 16.--31. 1. "LTSSM_VARIABLE,LTSSM Variable. Indicates internal LTSSM variables defined in the PCI Express Base Specification. C-PCIe Mode: - 0: directed_speed_change - 1: changed_speed_recovery - 2: successful_speed_negotiation - 3: upconfigure_capable; Set to '1' if.." newline rbitfld.long 0x4 15. "LANE_REVERSAL,Lane Reversal Operation. Receiver detected lane reversal. This field is only valid in the L0 LTSSM state. Note: This register field is sticky." "0,1" newline hexmask.long.byte 0x4 11.--14. 1. "RSVDP_11,Reserved for future use." newline rbitfld.long 0x4 8.--10. "PIPE_POWER_DOWN,PIPE:PowerDown. Indicates PIPE PowerDown signal. Note: This register field is sticky." "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 7. "FRAMING_ERR,Framing Error. Indicates Framing Error detection status." "0,1" newline hexmask.long.byte 0x4 0.--6. 1. "FRAMING_ERR_PTR,First Framing Error Pointer. Identifies the first Framing Error using the following encoding. The field contents are only valid value when FRAMING_ERR =1. Received Unexpected Framing Token - 01h: When non- STP/SDP/IDL Token was received.." line.long 0x8 "SD_STATUS_PM_REG,Silicon Debug Status(PM). For more details. see the RAS DES section in the Core Operations chapter of the Databook." hexmask.long.byte 0x8 24.--31. 1. "RSVDP_24,Reserved for future use." newline hexmask.long.byte 0x8 16.--23. 1. "LATCHED_NFTS,Latched N_FTS. Indicates the value of N_FTS in the received TS Ordered Sets from the Link Partner Note: This register field is sticky." newline rbitfld.long 0x8 13.--15. "L1SUB_STATE,L1Sub State. Indicates internal state machine of L1Sub state. - 0h: S_L1_U : idle state - 1h: S_L1_0 : wait for aux_clk_active - 2h: S_L1_0_WAIT4_ACK : wait for pclkack - 3h: S_L1_0_WAIT4_CLKREQ : wait for clkreq - 4h: S_L1_N_ENTRY : check.." "wait for aux_clk_active,?,?,?,?,?,?,?" newline bitfld.long 0x8 12. "PME_RESEND_FLAG,PME Re-send flag. When the DUT sends a PM_PME message TLP the DUT sets PME_Status bit. If host software does not clear PME_Status bit for 100ms(+50%/-5%) the DUT resends the PM_PME Message. This bit indicates that a PM_PME was resent." "0,1" newline hexmask.long.byte 0x8 8.--11. 1. "INTERNAL_PM_SSTATE,Internal PM State(Slave). Indicates internal state machine of Power Management Slave controller. - 0h: S_IDLE - 1h: S_RESPOND_NAK - 2h: S_BLOCK_TLP - 3h: S_WAIT_LAST_TLP_ACK - 4h: S_WAIT_EIDLE - 5h: S_LINK_ENTR_L1 - 6h: S_L1 - 7h:.." newline rbitfld.long 0x8 5.--7. "RSVDP_5,Reserved for future use." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x8 0.--4. 1. "INTERNAL_PM_MSTATE,Internal PM State(Master). Indicates internal state machine of Power Management Master controller. - 00h: IDLE - 01h: L0 - 02h: L0S - 03h: ENTER_L0S - 04h: L0S_EXIT - 05h: WAIT_PMCSR_CPL_SENT - 08h: L1 - 09h: L1_BLOCK_TLP - 0Ah:.." rgroup.long (0xBC+0x30C)++0x3 line.long 0x0 "SD_STATUS_L2_REG,Silicon Debug Status(Layer2). For more details. see the RAS DES section in the Core Operations chapter of the Databook." hexmask.long.byte 0x0 28.--31. 1. "RSVDP_28,Reserved for future use." newline bitfld.long 0x0 27. "FC_INIT2,FC_INIT2. Indicates the controller is in FC_INIT2(VC0) state. Note: This register field is sticky." "0,1" newline bitfld.long 0x0 26. "FC_INIT1,FC_INIT1. Indicates the controller is in FC_INIT1(VC0) state. Note: This register field is sticky." "0,1" newline bitfld.long 0x0 24.--25. "DLCMSM,DLCMSM. Indicates the current DLCMSM. - 00b: DL_INACTIVE - 01b: DL_FC_INIT - 11b: DL_ACTIVE Note: This register field is sticky." "0,1,2,3" newline hexmask.long.word 0x0 12.--23. 1. "RX_ACK_SEQ_NO,Tx Ack Sequence Number. Indicates ACKD_SEQ which is updated by receiving ACK/NAK DLLP. Note: This register field is sticky." newline hexmask.long.word 0x0 0.--11. 1. "TX_TLP_SEQ_NO,Tx Tlp Sequence Number. Indicates next transmit sequence number for transmit TLP. Note: This register field is sticky." group.long (0xC0+0x30C)++0x7 line.long 0x0 "SD_STATUS_L3FC_REG,Silicon Debug Status(Layer3 FC). The CREDIT_DATA[0/1] fields in this viewport register return the data for the VC and TLP Type selected by the following fields: - CREDIT_SEL_VC - CREDIT_SEL_CREDIT_TYPE - CREDIT_SEL_TLP_TYPE -.." hexmask.long.word 0x0 20.--31. 1. "CREDIT_DATA1,Credit Data1. Current FC credit data selected by the CREDIT_SEL_VC CREDIT_SEL_CREDIT_TYPE CREDIT_SEL_TLP_TYPE and CREDIT_SEL_HD viewport-select fields. - Rx: Credit Allocated Value - Tx: Credit Limit Value. This value is valid when.." newline hexmask.long.word 0x0 8.--19. 1. "CREDIT_DATA0,Credit Data0. Current FC credit data selected by the CREDIT_SEL_VC CREDIT_SEL_CREDIT_TYPE CREDIT_SEL_TLP_TYPE and CREDIT_SEL_HD viewport-select fields. - Rx: Credit Received Value - Tx: Credit Consumed Value Note: This register field is.." newline rbitfld.long 0x0 7. "RSVDP_7,Reserved for future use." "0,1" newline bitfld.long 0x0 6. "CREDIT_SEL_HD,Credit Select(HeaderData). This field in conjunction with the CREDIT_SEL_VC CREDIT_SEL_CREDIT_TYPE and CREDIT_SEL_TLP_TYPE viewport-select fields determines that data that is returned by the CREDIT_DATA0 and CREDIT_DATA1 data fields. -.." "Header Credit,Data Credit" newline bitfld.long 0x0 4.--5. "CREDIT_SEL_TLP_TYPE,Credit Select(TLP Type). This field in conjunction with the CREDIT_SEL_VC CREDIT_SEL_CREDIT_TYPE and CREDIT_SEL_HD viewport-select fields determines that data that is returned by the CREDIT_DATA0 and CREDIT_DATA1 data fields. - 0x0:.." "Posted,Non-Posted,Completion,?" newline bitfld.long 0x0 3. "CREDIT_SEL_CREDIT_TYPE,Credit Select(Credit Type). This field in conjunction with the CREDIT_SEL_VC CREDIT_SEL_TLP_TYPE and CREDIT_SEL_HD viewport-select fields determines that data that is returned by the CREDIT_DATA0 and CREDIT_DATA1 data fields. -.." "Rx,Tx" newline bitfld.long 0x0 0.--2. "CREDIT_SEL_VC,Credit Select(VC). This field in conjunction with the CREDIT_SEL_CREDIT_TYPE CREDIT_SEL_TLP_TYPE and CREDIT_SEL_HD viewport-select fields determines that data that is returned by the CREDIT_DATA0 and CREDIT_DATA1 data fields. - 0x0: VC0 -.." "VC0,VC1,VC2,?,?,?,?,VC7" line.long 0x4 "SD_STATUS_L3_REG,Silicon Debug Status(Layer3). For more details. see the RAS DES section in the Core Operations chapter of the Databook." hexmask.long.tbyte 0x4 8.--31. 1. "RSVDP_8,Reserved for future use." newline bitfld.long 0x4 7. "MFTLP_STATUS,Malformed TLP Status. Indicates malformed TLP has occurred." "0,1" newline hexmask.long.byte 0x4 0.--6. 1. "MFTLP_POINTER,First Malformed TLP Error Pointer. Indicates the element of the received first malformed TLP. This pointer is validated by MFTLP_STATUS. - 01h: AtomicOp address alignment - 02h: AtomicOp operand - 03h: AtomicOp byte enable - 04h: TLP length.." group.long (0xD0+0x30C)++0xB line.long 0x0 "SD_EQ_CONTROL1_REG,Silicon Debug EQ Control 1. This is a viewport control register. Setting the EQ_RATE_SEL and EQ_LANE_SEL fields in this register determine the per-lane Silicon Debug EQ Status data returned by the SD_EQ_STATUS[1/2/3] viewport.." hexmask.long.byte 0x0 24.--31. 1. "FOM_TARGET,FOM Target. Indicates figure of merit target criteria value of EQ Master(DSP in EQ Phase3/USP in EQ Phase2). This field is only valid when GEN3_EQ_FB_MODE is 0001b(Figure Of Merit). Note: This register field is sticky." newline bitfld.long 0x0 23. "FOM_TARGET_ENABLE,FOM Target Enable. Enables the FOM_TARGET fields. Note: This register field is sticky." "0,1" newline hexmask.long.byte 0x0 18.--22. 1. "RSVDP_18,Reserved for future use." newline bitfld.long 0x0 16.--17. "EVAL_INTERVAL_TIME,Eval Interval Time. Indicates interval time of RxEqEval assertion. - 00: 500ns - 01: 1us - 10: 2us - 11: 4us This field is used for EQ Master(DSP in EQ Phase3/USP in EQ Phase2). Note: This register field is sticky." "0,1,2,3" newline hexmask.long.byte 0x0 10.--15. 1. "RSVDP_10,Reserved for future use." newline bitfld.long 0x0 8.--9. "EXT_EQ_TIMEOUT,Extends EQ Phase2/3 Timeout. This field is used when the Ltssm is in Recovery.EQ2/3. When this field is set the value of EQ2/3 timeout is extended. EQ Master(DSP in EQ Phase3/USP in EQ Phase2). - 00: 24ms (default) - 01: 48ms (x2) - 10:.." "0,1,2,3" newline rbitfld.long 0x0 6.--7. "RSVDP_6,Reserved for future use." "0,1,2,3" newline bitfld.long 0x0 4.--5. "EQ_RATE_SEL,EQ Status Rate Select. Setting this field in conjunction with the EQ_LANE_SEL field determines the per-lane Silicon Debug EQ Status data returned by the SD_EQ_CONTROL[2/3] and SD_EQ_STATUS[1/2/3] viewport registers. - 0x0: 8.0GT/s Speed.." "0,1,2,3" newline hexmask.long.byte 0x0 0.--3. 1. "EQ_LANE_SEL,EQ Status Lane Select. Setting this field in conjunction with the EQ_RATE_SEL field determines the per-lane Silicon Debug EQ Status data returned by the SD_EQ_CONTROL[2/3] and SD_EQ_STATUS[1/2/3] viewport registers. - 0x0: Lane0 - 0x1: Lane1.." line.long 0x4 "SD_EQ_CONTROL2_REG,Silicon Debug EQ Control 2. This viewport register returns the value for the rate and lane selected by the EQ_RATE_SEL and EQ_LANE_SEL fields in the SD_EQ_CONTROL1_REG register. For more details. see the RAS DES section in the Core.." rbitfld.long 0x4 31. "RSVDP_31,Reserved for future use." "0,1" newline bitfld.long 0x4 30. "FORCE_LOCAL_TX_PRESET_ENABLE,Force Local Transmitter Preset Enable. Enables the FORCE_LOCAL_TX_PRESET field. If select rate in the EQ_RATE_SEL field is 32.0GT/s Speed this feature is not available. Note: This register field is sticky." "0,1" newline bitfld.long 0x4 29. "FORCE_LOCAL_RX_HINT_ENABLE,Force Local Receiver Preset Hint Enable. Enables the FORCE_LOCAL_RX_HINT field. If select rate in the EQ_RATE_SEL field is other than 8.0GT/s Speed this feature is not available. Note: This register field is sticky." "0,1" newline bitfld.long 0x4 28. "FORCE_LOCAL_TX_COEF_ENABLE,Force Local Transmitter Coefficient Enable. Enables the following fields: - FORCE_LOCAL_TX_PRE_CURSOR - FORCE_LOCAL_TX_CURSOR - FORCE_LOCAL_TX_POST_CURSOR Note: This register field is sticky." "0,1" newline hexmask.long.byte 0x4 24.--27. 1. "FORCE_LOCAL_TX_PRESET,Force Local Transmitter Preset. Indicates initial preset value of USP in EQ Slave(EQ Phase2) instead of receiving EQ TS2. If select rate in the EQ_RATE_SEL field is 32.0GT/s Speed this feature is not available. Note: This register.." newline rbitfld.long 0x4 21.--23. "RSVDP_21,Reserved for future use." "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 18.--20. "FORCE_LOCAL_RX_HINT,Force Local Receiver Preset Hint. Indicates the RxPresetHint value of EQ Slave(DSP in EQ Phase2/USP in EQ Phase3) instead of received or set value. If select rate in the EQ_RATE_SEL field is other than 8.0GT/s Speed this feature is.." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x4 12.--17. 1. "FORCE_LOCAL_TX_POST_CURSOR,Force Local Transmitter Post-Cursor. Indicates the coefficient value of EQ Slave(DSP in EQ Phase2/USP in EQ Phase3) instead of the value instructed from link partner. Note: This register field is sticky." newline hexmask.long.byte 0x4 6.--11. 1. "FORCE_LOCAL_TX_CURSOR,Force Local Transmitter Cursor. Indicates the coefficient value of EQ Slave(DSP in EQ Phase2/USP in EQ Phase3) instead of the value instructed from link partner. Note: This register field is sticky." newline hexmask.long.byte 0x4 0.--5. 1. "FORCE_LOCAL_TX_PRE_CURSOR,Force Local Transmitter Pre-cursor. Indicates the coefficient value of EQ Slave(DSP in EQ Phase2/USP in EQ Phase3) instead of the value instructed from link partner. Note: This register field is sticky." line.long 0x8 "SD_EQ_CONTROL3_REG,Silicon Debug EQ Control 3. This viewport register returns the value for the rate and lane selected by the EQ_RATE_SEL and EQ_LANE_SEL fields in the SD_EQ_CONTROL1_REG register. For more details. see the RAS DES section in the Core.." rbitfld.long 0x8 29.--31. "RSVDP_29,Reserved for future use." "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 28. "FORCE_REMOTE_TX_COEF_ENABLE,Force Remote Transmitter Coefficient Enable. Enables the following fields: - FORCE_REMOTE_TX_PRE_CURSOR - FORCE_REMOTE_TX_CURSOR - FORCE_REMOTE_TX_POST_CURSOR This function can only be used when GEN3_EQ_FB_MODE =.." "0,1" newline hexmask.long.word 0x8 18.--27. 1. "RSVDP_18,Reserved for future use." newline hexmask.long.byte 0x8 12.--17. 1. "FORCE_REMOTE_TX_POST_CURSOR,Force Remote Transmitter Post-Cursor. Indicates the coefficient value of EQ Master(DSP in EQ Phase3/USP in EQ Phase2) instead of the value instructed from local phy in dirchange mode. Note: This register field is sticky." newline hexmask.long.byte 0x8 6.--11. 1. "FORCE_REMOTE_TX_CURSOR,Force Remote Transmitter Cursor. Indicates the coefficient value of EQ Master(DSP in EQ Phase3/USP in EQ Phase2) instead of the value instructed from local phy in dirchange mode. Note: This register field is sticky." newline hexmask.long.byte 0x8 0.--5. 1. "FORCE_REMOTE_TX_PRE_CURSOR,Force Remote Transmitter Pre-Cursor. Indicates the coefficient value of EQ Master(DSP in EQ Phase3/USP in EQ Phase2) instead of the value instructed from local phy in dirchange mode. Note: This register field is sticky." rgroup.long (0xE0+0x30C)++0xB line.long 0x0 "SD_EQ_STATUS1_REG,Silicon Debug EQ Status 1. This viewport register returns the first of three words of Silicon Debug EQ Status data for the rate and lane selected by the EQ_RATE_SEL and EQ_LANE_SEL fields in the SD_EQ_CONTROL1_REG register. The.." hexmask.long.tbyte 0x0 8.--31. 1. "RSVDP_8,Reserved for future use." newline bitfld.long 0x0 7. "EQ_REJECT_EVENT,EQ Reject Event. Indicates that the controller receives two consecutive TS1 OS w/Reject=1b during EQ Master phase(DSP in EQ Phase3/USP in EQ Phase2). This bit is automatically cleared when the controller starts EQ Master phase again." "0,1" newline bitfld.long 0x0 6. "EQ_RULEC_VIOLATION,EQ Rule C Violation. Indicates that coefficients rule C violation is detected in the values provided by PHY using direction change method during EQ Master phase(DSP in EQ Phase3/USP in EQ Phase2). The coefficients rule C correspond to.." "0,1" newline bitfld.long 0x0 5. "EQ_RULEB_VIOLATION,EQ Rule B Violation. Indicates that coefficients rule B violation is detected in the values provided by PHY using direction change method during EQ Master phase(DSP in EQ Phase3/USP in EQ Phase2). The coefficients rules B correspond to.." "0,1" newline bitfld.long 0x0 4. "EQ_RULEA_VIOLATION,EQ Rule A Violation. Indicates that coefficients rule A violation is detected in the values provided by PHY using direction change method during EQ Master phase(DSP in EQ Phase3/USP in EQ Phase2). The coefficients rules A correspond to.." "0,1" newline bitfld.long 0x0 3. "RSVDP_3,Reserved for future use." "0,1" newline bitfld.long 0x0 1.--2. "EQ_CONVERGENCE_INFO,EQ Convergence Info. Indicates equalization convergence information. - 0x0: Equalization is not attempted - 0x1: Equalization finished successfully - 0x2: Equalization finished unsuccessfully - 0x3: Reserved This bit is automatically.." "Equalization is not attempted,Equalization finished successfully,Equalization finished unsuccessfully,Reserved" newline bitfld.long 0x0 0. "EQ_SEQUENCE,EQ Sequence. Indicates that the controller is starting the equalization sequence. Note: This register field is sticky." "0,1" line.long 0x4 "SD_EQ_STATUS2_REG,Silicon Debug EQ Status 2. This viewport register returns the second of three words of Silicon Debug EQ Status data for the rate and lane selected by the EQ_RATE_SEL and EQ_LANE_SEL fields in the SD_EQ_CONTROL1_REG register. Each field.." hexmask.long.byte 0x4 24.--31. 1. "EQ_LOCAL_FOM_VALUE,EQ Local Figure of Merit. Indicates Local maximum Figure of Merit value. Note: This register field is sticky." newline bitfld.long 0x4 21.--23. "RSVDP_21,Reserved for future use." "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 18.--20. "EQ_LOCAL_RX_HINT,EQ Local Receiver Preset Hint. Indicates Local Receiver Preset Hint value. If select rate in the EQ_RATE_SEL field is other than 8.0GT/s Speed this feature is not available. Note: This register field is sticky." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x4 12.--17. 1. "EQ_LOCAL_POST_CURSOR,EQ Local Post-Cursor. Indicates Local post cursor coefficient value. Note: This register field is sticky." newline hexmask.long.byte 0x4 6.--11. 1. "EQ_LOCAL_CURSOR,EQ Local Cursor. Indicates Local cursor coefficient value. Note: This register field is sticky." newline hexmask.long.byte 0x4 0.--5. 1. "EQ_LOCAL_PRE_CURSOR,EQ Local Pre-Cursor. Indicates Local pre cursor coefficient value. Note: This register field is sticky." line.long 0x8 "SD_EQ_STATUS3_REG,Silicon Debug EQ Status 3. This viewport register returns the third of three words of Silicon Debug EQ Status data for the rate and lane selected by the EQ_RATE_SEL and EQ_LANE_SEL fields in the SD_EQ_CONTROL1_REG register. Each field.." bitfld.long 0x8 30.--31. "RSVDP_30,Reserved for future use." "0,1,2,3" newline hexmask.long.byte 0x8 24.--29. 1. "EQ_REMOTE_FS,EQ Remote FS. Indicates Remote FS value. Note: This register field is sticky." newline hexmask.long.byte 0x8 18.--23. 1. "EQ_REMOTE_LF,EQ Remote LF. Indicates Remote LF value. Note: This register field is sticky." newline hexmask.long.byte 0x8 12.--17. 1. "EQ_REMOTE_POST_CURSOR,EQ Remote Post-Cursor. Indicates Remote post cursor coefficient value. Note: This register field is sticky." newline hexmask.long.byte 0x8 6.--11. 1. "EQ_REMOTE_CURSOR,EQ Remote Cursor. Indicates Remote cursor coefficient value. Note: This register field is sticky." newline hexmask.long.byte 0x8 0.--5. 1. "EQ_REMOTE_PRE_CURSOR,EQ Remote Pre-Cursor. Indicates Remote pre cursor coefficient value. Note: This register field is sticky." tree.end tree "PF0_SN_CAP (Device Serial Number Capability Structure)" group.long (0x0+0x170)++0xB line.long 0x0 "SN_BASE,Device Serial Number Extended Capability Header. For a description of this standard PCIe register. see the PCI Express Base Specification." hexmask.long.word 0x0 20.--31. 1. "SN_NEXT_OFFSET,Next Capability Offset. For a description of this standard PCIe register field see the PCI Express Base Specification. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then.." hexmask.long.byte 0x0 16.--19. 1. "SN_CAP_VERSION,Capability Version. For a description of this standard PCIe register field see the PCI Express Base Specification. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky).." hexmask.long.word 0x0 0.--15. 1. "SN_PCIE_EXTENDED_CAP_ID,Serial Number Extended Capability ID. For a description of this standard PCIe register field see the PCI Express Base Specification. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if.." line.long 0x4 "SER_NUM_REG_DW_1,Serial Number 1 Register. For a description of this standard PCIe register. see the PCI Express Base Specification." hexmask.long 0x4 0.--31. 1. "SN_SER_NUM_REG_1_DW,IEEE 64 bit Device Serial Number (DW 1). For a description of this standard PCIe register field see the PCI Express Base Specification. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if.." line.long 0x8 "SER_NUM_REG_DW_2,Serial Number 2 Register. For a description of this standard PCIe register. see the PCI Express Base Specification." hexmask.long 0x8 0.--31. 1. "SN_SER_NUM_REG_2_DW,IEEE 64 bit Device Serial Number (DW 2). For a description of this standard PCIe register field see the PCI Express Base Specification. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if.." tree.end tree "PF0_VSECRAS_CAP (PF RAS Datapath Protection Capability Structure (VSEC))" group.long (0x0+0x480)++0x3 line.long 0x0 "RASDP_EXT_CAP_HDR_OFF,PCIe Extended capability ID. Capability version and Next capability offset. For a description of this standard PCIe register. see the PCI Express Specification." hexmask.long.word 0x0 20.--31. 1. "NEXT_OFFSET,Next Capability Offset. For a description of this standard PCIe register see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else.." newline hexmask.long.byte 0x0 16.--19. 1. "CAP,Capability Version. For a description of this standard PCIe register see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note:.." newline hexmask.long.word 0x0 0.--15. 1. "ID,PCI Express Extended Capability ID. For a description of this standard PCIe register see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else.." rgroup.long (0x4+0x480)++0x3 line.long 0x0 "RASDP_VENDOR_SPECIFIC_HDR_OFF,Vendor Specific Header. For a description of this standard PCIe register. see the PCI Express Specification." hexmask.long.word 0x0 20.--31. 1. "VSEC_LENGTH,VSEC Length. For a description of this standard PCIe register see the PCI Express Specification. Note: This register field is sticky." newline hexmask.long.byte 0x0 16.--19. 1. "VSEC_REV,VSEC Rev. For a description of this standard PCIe register see the PCI Express Specification. Note: This register field is sticky." newline hexmask.long.word 0x0 0.--15. 1. "VSEC_ID,VSEC ID. For a description of this standard PCIe register see the PCI Express Specification. Note: This register field is sticky." group.long (0x8+0x480)++0x7 line.long 0x0 "RASDP_ERROR_PROT_CTRL_OFF,ECC error correction control. Allows you to disable ECC error correction for RAMs and datapath. When the AXI Bridge Module is implemented and the master / slave clocks are asynchronous to the PCIe native controller clock.." hexmask.long.byte 0x0 24.--31. 1. "RSVDP_24,Reserved for future use." newline bitfld.long 0x0 23. "ERROR_PROT_DISABLE_CXS_RX,Error correction disable for CXS Tx path (PCIe Rx path). Note: This register field is sticky." "0,1" newline bitfld.long 0x0 22. "ERROR_PROT_DISABLE_ADM_RX,Error correction disable for ADM Rx path. Note: This register field is sticky." "0,1" newline bitfld.long 0x0 21. "ERROR_PROT_DISABLE_LAYER3_RX,Error correction disable for layer 3 Rx path. Note: This register field is sticky." "0,1" newline bitfld.long 0x0 20. "ERROR_PROT_DISABLE_LAYER2_RX,Error correction disable for layer 2 Rx path. Note: This register field is sticky." "0,1" newline bitfld.long 0x0 19. "ERROR_PROT_DISABLE_DMA_READ,Error correction disable for DMA read engine. Note: This register field is sticky." "0,1" newline bitfld.long 0x0 18. "ERROR_PROT_DISABLE_AXI_BRIDGE_INBOUND_REQUEST,Error correction disable for AXI bridge inbound request path. Note: This register field is sticky." "0,1" newline bitfld.long 0x0 17. "ERROR_PROT_DISABLE_AXI_BRIDGE_INBOUND_COMPLETION,Error correction disable for AXI bridge inbound completion composer. Does not disable the error detection reporting for 1-bit and 2-bit ECC errors. Note: This register field is sticky." "?,bit and 2-bit ECC errors" newline bitfld.long 0x0 16. "ERROR_PROT_DISABLE_RX,Global error correction disable for all Rx layers. Note: This register field is sticky." "0,1" newline hexmask.long.byte 0x0 9.--15. 1. "RSVDP_9,Reserved for future use." newline bitfld.long 0x0 8. "ERROR_PROT_DISABLE_DTIM_TX,Error correction disable for DTIM Tx path. Note: This register field is sticky." "0,1" newline bitfld.long 0x0 7. "ERROR_PROT_DISABLE_CXS_TX,Error correction disable for CXS Rx path (PCIe Tx path). Note: This register field is sticky." "0,1" newline bitfld.long 0x0 6. "ERROR_PROT_DISABLE_ADM_TX,Error correction disable for Adm Tx path. Note: This register field is sticky." "0,1" newline bitfld.long 0x0 5. "ERROR_PROT_DISABLE_LAYER3_TX,Error correction disable for layer 3 Tx path. Note: This register field is sticky." "0,1" newline bitfld.long 0x0 4. "ERROR_PROT_DISABLE_LAYER2_TX,Error correction disable for layer 2 Tx path. Note: This register field is sticky." "0,1" newline bitfld.long 0x0 3. "ERROR_PROT_DISABLE_DMA_WRITE,Error correction disable for DMA write engine. Note: This register field is sticky." "0,1" newline bitfld.long 0x0 2. "ERROR_PROT_DISABLE_AXI_BRIDGE_OUTBOUND,Error correction disable for AXI bridge outbound request path. Note: This register field is sticky." "0,1" newline bitfld.long 0x0 1. "ERROR_PROT_DISABLE_AXI_BRIDGE_MASTER,Error correction disable for AXI bridge master completion buffer. Note: This register field is sticky." "0,1" newline bitfld.long 0x0 0. "ERROR_PROT_DISABLE_TX,Global error correction disable for all Tx layers. Does not disable the error detection reporting for 1-bit and 2-bit ECC errors. Note: This register field is sticky." "?,bit and 2-bit ECC errors" line.long 0x4 "RASDP_CORR_COUNTER_CTRL_OFF,Corrected error (1-bit ECC) counter selection and control. This is a viewport control register. Setting the CORR_COUNTER_SELECTION_REGION and CORR_COUNTER_SELECTION fields in this register determine the counter data returned.." hexmask.long.byte 0x4 24.--31. 1. "CORR_COUNTER_SELECTION,Counter selection. This field selects the counter ID (within the region defined by CORR_COUNTER_SELECTION_REGION) whose contents can be read from the RASDP_CORR_COUNT_REPORT_OFF register. You can cycle this field value from 0 to.." newline hexmask.long.byte 0x4 20.--23. 1. "CORR_COUNTER_SELECTION_REGION,Select correctable counter region: - 0x0: Region select for Adm Rx path - 0x1: Region select for layer 3 Rx path - 0x2: Region select for layer 2 Rx path - 0x3: Region select for DMA inbound path - 0x4: Region select for AXI.." newline hexmask.long.word 0x4 5.--19. 1. "RSVDP_5,Reserved for future use." newline bitfld.long 0x4 4. "CORR_EN_COUNTERS,Enable correctable errors counters. - 1: counters increment when the controller detects a correctable error - 0: counters are frozen The counters are enabled by default." "counters are frozen,counters increment when the controller detects a.." newline rbitfld.long 0x4 1.--3. "RSVDP_1,Reserved for future use." "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 0. "CORR_CLEAR_COUNTERS,Clear all correctable error counters." "0,1" rgroup.long (0x10+0x480)++0x3 line.long 0x0 "RASDP_CORR_COUNT_REPORT_OFF,Corrected error (1-bit ECC) counter data. This viewport register returns the counter data selected by the CORR_COUNTER_SELECTION_REGION and CORR_COUNTER_SELECTION fields in the RASDP_CORR_COUNTER_CTRL_OFF register." hexmask.long.byte 0x0 24.--31. 1. "CORR_COUNTER_SELECTED,Counter selection. Returns the value set in the CORR_COUNTER_SELECTION field of the RASDP_CORR_COUNTER_CTRL_OFF register." newline hexmask.long.byte 0x0 20.--23. 1. "CORR_COUNTER_SELECTED_REGION,Selected correctable counter region: - 0x0: Region select for Adm Rx path - 0x1: Region select for layer 3 Rx path - 0x2: Region select for layer 2 Rx path - 0x3: Region select for DMA inbound path - 0x4: Region select for.." newline hexmask.long.word 0x0 8.--19. 1. "RSVDP_8,Reserved for future use." newline hexmask.long.byte 0x0 0.--7. 1. "CORR_COUNTER,Current corrected error count for the selected counter." group.long (0x14+0x480)++0x3 line.long 0x0 "RASDP_UNCORR_COUNTER_CTRL_OFF,Uncorrected error (2-bit ECC and parity) counter selection and control. This is a viewport control register. Setting the UNCORR_COUNTER_SELECTION_REGION and UNCORR_COUNTER_SELECTION fields in this register determine the.." hexmask.long.byte 0x0 24.--31. 1. "UNCORR_COUNTER_SELECTION,Counter selection. This field selects the counter ID (within the region defined by UNCORR_COUNTER_SELECTION_REGION) whose contents can be read from the RASDP_UNCORR_COUNT_REPORT_OFF register. You can cycle this field value from 0.." newline hexmask.long.byte 0x0 20.--23. 1. "UNCORR_COUNTER_SELECTION_REGION,Select uncorrectable counter region: - 0x0: Region select for Adm Rx path - 0x1: Region select for layer 3 Rx path - 0x2: Region select for layer 2 Rx path - 0x3: Region select for DMA inbound path - 0x4: Region select for.." newline hexmask.long.word 0x0 5.--19. 1. "RSVDP_5,Reserved for future use." newline bitfld.long 0x0 4. "UNCORR_EN_COUNTERS,Enable uncorrectable errors counters. - 1: enables the counters to increment on detected correctable errors - 0: counters are frozen The counters are enabled by default." "counters are frozen,enables the counters to increment on detected.." newline rbitfld.long 0x0 1.--3. "RSVDP_1,Reserved for future use." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 0. "UNCORR_CLEAR_COUNTERS,Clear uncorrectable errors counters. When asserted causes all counters tracking the uncorrectable errors to be cleared." "0,1" rgroup.long (0x18+0x480)++0x3 line.long 0x0 "RASDP_UNCORR_COUNT_REPORT_OFF,Uncorrected error (2-bit ECC and parity) counter data. This viewport register returns the counter data selected by the UNCORR_COUNTER_SELECTION_REGION and UNCORR_COUNTER_SELECTION fields in the RASDP_UNCORR_COUNTER_CTRL_OFF.." hexmask.long.byte 0x0 24.--31. 1. "UNCORR_COUNTER_SELECTED,Counter selection. Returns the value set in the UNCORR_COUNTER_SELECTION field of the RASDP_UNCORR_COUNTER_CTRL_OFF register." newline hexmask.long.byte 0x0 20.--23. 1. "UNCORR_COUNTER_SELECTED_REGION,Selected uncorrectable counter region: - 0x0: Region select for Adm Rx path - 0x1: Region select for layer 3 Rx path - 0x2: Region select for layer 2 Rx path - 0x3: Region select for DMA inbound path - 0x4: Region select.." newline hexmask.long.word 0x0 8.--19. 1. "RSVDP_8,Reserved for future use." newline hexmask.long.byte 0x0 0.--7. 1. "UNCORR_COUNTER,Current uncorrected error count for the selected counter" group.long (0x1C+0x480)++0x3 line.long 0x0 "RASDP_ERROR_INJ_CTRL_OFF,Error injection control for the following features: - 1-bit or 2-bit injection - Continuous or fixed-number (n) injection modes - Global enable/disable - Selectable location where injection occurs" hexmask.long.byte 0x0 24.--31. 1. "RSVDP_24,Reserved for future use." newline hexmask.long.byte 0x0 16.--23. 1. "ERROR_INJ_LOC,Error injection location. Selects where error injection takes place. You can cycle this field value from 0 to 255 to access all locations according to the detailed report of check points at.." newline hexmask.long.byte 0x0 8.--15. 1. "ERROR_INJ_COUNT,Error injection count. - 0: errors are inserted in every TLP until you clear ERROR_INJ_EN. - 1: one errors injected - 2: two errors injected - n: amount of errors injected" newline rbitfld.long 0x0 6.--7. "RSVDP_6,Reserved for future use." "0,1,2,3" newline bitfld.long 0x0 4.--5. "ERROR_INJ_TYPE,Error injection type: - 0: none - 1: 1-bit - 2: 2-bit" "none,bit,bit,?" newline rbitfld.long 0x0 1.--3. "RSVDP_1,Reserved for future use." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 0. "ERROR_INJ_EN,Error injection global enable. When set enables the error insertion logic." "0,1" rgroup.long (0x20+0x480)++0x7 line.long 0x0 "RASDP_CORR_ERROR_LOCATION_OFF,Corrected errors locations. For more details. see the RAS Data Protection (DP) section in the Core Operations chapter of the Databook." hexmask.long.byte 0x0 24.--31. 1. "LOC_LAST_CORR_ERROR,Location/ID of the last corrected error within the region defined by REG_LAST_CORR_ERROR. You can cycle this field value from 0 to 255 to access all counters according to the detailed report of check points at.." newline hexmask.long.byte 0x0 20.--23. 1. "REG_LAST_CORR_ERROR,Region of the last corrected error: - 0x0: Region select for Adm Rx path - 0x1: Region select for layer 3 Rx path - 0x2: Region select for layer 2 Rx path - 0x3: Region select for DMA inbound path - 0x4: Region select for AXI bridge.." newline hexmask.long.byte 0x0 16.--19. 1. "RSVDP_16,Reserved for future use." newline hexmask.long.byte 0x0 8.--15. 1. "LOC_FIRST_CORR_ERROR,Location/ID of the first corrected error within the region defined by REG_FIRST_CORR_ERROR. You can cycle this field value from 0 to 255 to access all counters according to the detailed report of check points at.." newline hexmask.long.byte 0x0 4.--7. 1. "REG_FIRST_CORR_ERROR,Region of the first corrected error: - 0x0: Region select for Adm Rx path - 0x1: Region select for layer 3 Rx path - 0x2: Region select for layer 2 Rx path - 0x3: Region select for DMA inbound path - 0x4: Region select for AXI bridge.." newline hexmask.long.byte 0x0 0.--3. 1. "RSVDP_0,Reserved for future use." line.long 0x4 "RASDP_UNCORR_ERROR_LOCATION_OFF,Uncorrected errors locations. For more details. see the RAS Data Protection (DP) section in the Core Operations chapter of the Databook." hexmask.long.byte 0x4 24.--31. 1. "LOC_LAST_UNCORR_ERROR,Location/ID of the last uncorrected error within the region defined by REG_LAST_UNCORR_ERROR. You can cycle this field value from 0 to 255 to access all counters according to the detailed report of check points at.." newline hexmask.long.byte 0x4 20.--23. 1. "REG_LAST_UNCORR_ERROR,Region of the last uncorrected error: - 0x0: Region select for Adm Rx path - 0x1: Region select for layer 3 Rx path - 0x2: Region select for layer 2 Rx path - 0x3: Region select for DMA inbound path - 0x4: Region select for AXI.." newline hexmask.long.byte 0x4 16.--19. 1. "RSVDP_16,Reserved for future use." newline hexmask.long.byte 0x4 8.--15. 1. "LOC_FIRST_UNCORR_ERROR,Location/ID of the first uncorrected error within the region defined by REG_FIRST_UNCORR_ERROR. You can cycle this field value from 0 to 255 to access all counters according to the detailed report of check points at.." newline hexmask.long.byte 0x4 4.--7. 1. "REG_FIRST_UNCORR_ERROR,Region of the first uncorrected error: - 0x0: Region select for Adm Rx path - 0x1: Region select for layer 3 Rx path - 0x2: Region select for layer 2 Rx path - 0x3: Region select for DMA inbound path - 0x4: Region select for AXI.." newline hexmask.long.byte 0x4 0.--3. 1. "RSVDP_0,Reserved for future use." group.long (0x28+0x480)++0x7 line.long 0x0 "RASDP_ERROR_MODE_EN_OFF,RASDP error mode enable. The controller enters RASDP error mode (if ERROR_MODE_EN =1) upon detection of the first uncorrectable error. During this mode: - Rx TLPs that are forwarded to your application are not guaranteed to be.." hexmask.long 0x0 2.--31. 1. "RSVDP_2,Reserved for future use." newline bitfld.long 0x0 1. "AUTO_LINK_DOWN_EN,Write '1' to enable the controller to bring the link down when the controller enters RASDP error mode. Note: This register field is sticky." "0,1" newline bitfld.long 0x0 0. "ERROR_MODE_EN,Write '1' to enable the controller enter RASDP error mode when it detects an uncorrectable error. Note: This register field is sticky." "0,1" line.long 0x4 "RASDP_ERROR_MODE_CLEAR_OFF,Exit RASDP error mode. For more details. see the RAS Data Protection (DP) section in the Core Operations chapter of the Databook." hexmask.long 0x4 1.--31. 1. "RSVDP_1,Reserved for future use." newline bitfld.long 0x4 0. "ERROR_MODE_CLEAR,Write '1' to take the controller out of RASDP error mode. The controller will then report uncorrectable errors (through AER internal error reporting) and also stop nullifying/discarding TLPs." "0,1" rgroup.long (0x30+0x480)++0x7 line.long 0x0 "RASDP_RAM_ADDR_CORR_ERROR_OFF,RAM Address where a corrected error (1-bit ECC) has been detected. For more details. see the RAS Data Protection (DP) section in the Core Operations chapter of the Databook." hexmask.long.byte 0x0 28.--31. 1. "RAM_INDEX_CORR_ERROR,RAM index where a corrected error (1-bit ECC) has been detected." newline bitfld.long 0x0 27. "RSVDP_27,Reserved for future use." "0,1" newline hexmask.long 0x0 0.--26. 1. "RAM_ADDR_CORR_ERROR,RAM Address where a corrected error (1-bit ECC) has been detected." line.long 0x4 "RASDP_RAM_ADDR_UNCORR_ERROR_OFF,RAM Address where an uncorrected error (2-bit ECC) has been detected. For more details. see the RAS Data Protection (DP) section in the Core Operations chapter of the Databook." hexmask.long.byte 0x4 28.--31. 1. "RAM_INDEX_UNCORR_ERROR,RAM index where an uncorrected error (2-bit ECC) has been detected." newline bitfld.long 0x4 27. "RSVDP_27,Reserved for future use." "0,1" newline hexmask.long 0x4 0.--26. 1. "RAM_ADDR_UNCORR_ERROR,RAM Address where an uncorrected error (2-bit ECC) has been detected." tree.end tree "PF0_RTR_CAP (PF RTR Capability Structure)" group.long (0x0+0x2F8)++0xB line.long 0x0 "RTR_EXT_CAP_HDR_OFF,Readiness Time Reporting PCI Express Extended Capability Header. For a description of this standard PCIe register. see the PCI Express Specification." hexmask.long.word 0x0 20.--31. 1. "RTR_NEXT_OFFSET,Next Capability Offset. For a description of this standard PCIe register field see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky).." hexmask.long.byte 0x0 16.--19. 1. "RTR_CAP_VERSION,Capability Version. For a description of this standard PCIe register field see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky).." hexmask.long.word 0x0 0.--15. 1. "RTR_EXT_CAP_ID,PCI Express Extended Capability ID. For a description of this standard PCIe register field see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then.." line.long 0x4 "READI_TIME_REPORTING1_OFF,Readiness Time Reporting 1. For a description of this standard PCIe register. see the PCI Express Specification." bitfld.long 0x4 31. "RTR_TIME_VALID,Valid. For a description of this standard PCIe register field see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky)" "0,1" hexmask.long.byte 0x4 24.--30. 1. "RSVDP_24,Reserved for future use." hexmask.long.word 0x4 12.--23. 1. "DL_UP_TIME,DL_UP Time. For a description of this standard PCIe register field see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky)" hexmask.long.word 0x4 0.--11. 1. "RESET_TIME,Reset Time. For a description of this standard PCIe register field see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky)" line.long 0x8 "READI_TIME_REPORTING2_OFF,Readiness Time Reporting 2. For a description of this standard PCIe register. see the PCI Express Specification." hexmask.long.byte 0x8 24.--31. 1. "RSVDP_24,Reserved for future use." hexmask.long.word 0x8 12.--23. 1. "D3HOT_D0_TIME,D3hot to D0 Time. For a description of this standard PCIe register field see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else.." hexmask.long.word 0x8 0.--11. 1. "FLR_TIME,FLR Time. For a description of this standard PCIe register field see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky)" tree.end tree "PF0_RTR_CAP_DBI2 (DBI2 Shadow Block: PF RTR Capability Structure)" rgroup.long (0x4+0x12F8)++0x7 line.long 0x0 "SHADOW_READI_TIME_REPORTING1_OFF,Shadow Register Readiness Time Reporting 1. For a description of this standard PCIe register. see the PCI Express Specification." bitfld.long 0x0 31. "RTR_TIME_VALID,Shadow Valid in the shadow register. For a description of this standard PCIe register field see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access - Dbi: No access - Dbi2: if.." "0,1" hexmask.long.tbyte 0x0 12.--30. 1. "RSVDP_12,Reserved for future use." hexmask.long.word 0x0 0.--11. 1. "RESET_TIME,Shadow Reset Time in the shadow register. For a description of this standard PCIe register field see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access - Dbi: No access - Dbi2: if.." line.long 0x4 "SHADOW_READI_TIME_REPORTING2_OFF,Shadow Register Readiness Time Reporting 2. For a description of this standard PCIe register. see the PCI Express Specification." hexmask.long.byte 0x4 24.--31. 1. "RSVDP_24,Reserved for future use." hexmask.long.word 0x4 12.--23. 1. "D3HOT_D0_TIME,Shadow D3hot to D0 Time in the shadow register. For a description of this standard PCIe register field see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access - Dbi: No access - Dbi2:.." hexmask.long.word 0x4 0.--11. 1. "FLR_TIME,Shadow FLR Time in the shadow register. For a description of this standard PCIe register field see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access - Dbi: No access - Dbi2: if.." tree.end tree "PF0_FRSQ_CAP (PF FRSQ Capability Structure)" group.long (0x0+0x2E8)++0xB line.long 0x0 "FRSQ_EXT_CAP_HDR_OFF,FRS Queuing Extended Capability Header. For a description of this standard PCIe register. see the PCI Express Specification." hexmask.long.word 0x0 20.--31. 1. "FRSQ_NEXT_OFFSET,Next Capability Offset. For a description of this standard PCIe register field see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then.." hexmask.long.byte 0x0 16.--19. 1. "FRSQ_CAP_VERSION,Capability Version. For a description of this standard PCIe register field see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky).." hexmask.long.word 0x0 0.--15. 1. "FRSQ_EXT_CAP_ID,PCI Express Extended Capability ID. For a description of this standard PCIe register field see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then.." line.long 0x4 "FRSQ_CAP_OFF,FRS Queuing Capability Register. For a description of this standard PCIe register. see the PCI Express Specification." hexmask.long.word 0x4 21.--31. 1. "RSVDP_21,Reserved for future use." hexmask.long.byte 0x4 16.--20. 1. "FRS_INT_MESSAGE_NUMBER,FRS Interrupt Message Number. For a description of this standard PCIe register field see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1).." hexmask.long.byte 0x4 12.--15. 1. "RSVDP_12,Reserved for future use." hexmask.long.word 0x4 0.--11. 1. "FRSQ_MAX_DEPTH,FRS Queue Max Depth. For a description of this standard PCIe register field see the PCI Express Specification." line.long 0x8 "FRSQ_CONTROL_FRSQ_STATUS_OFF,FRS Queuing Status and Control Register. For a description of this standard PCIe register. see the PCI Express Specification." hexmask.long.word 0x8 17.--31. 1. "RSVDP_17,Reserved for future use." bitfld.long 0x8 16. "FRS_INTERRUPT_ENABLE,FRS Interrupt Enable. For a description of this standard PCIe register field see the PCI Express Specification." "0,1" hexmask.long.word 0x8 2.--15. 1. "RSVDP_2,Reserved for future use." bitfld.long 0x8 1. "FRS_MESSAGE_OVERFLOW,FRS Message Overflow. For a description of this standard PCIe register field see the PCI Express Specification." "0,1" newline bitfld.long 0x8 0. "FRS_MESSAGE_RECEIVED,FRS Message Received. For a description of this standard PCIe register field see the PCI Express Specification." "0,1" rgroup.long (0xC+0x2E8)++0x3 line.long 0x0 "FRS_MESSAGE_QUEUE_OFF,FRS Message Queue Register. For a description of this standard PCIe register. see the PCI Express Specification." hexmask.long.word 0x0 20.--31. 1. "FRS_MESSAGE_QUE_DEPTH,FRS Message Queue Depth. For a description of this standard PCIe register field see the PCI Express Specification." hexmask.long.byte 0x0 16.--19. 1. "FRS_MESSAGE_QUE_REASON,FRS Message Queue Reason. For a description of this standard PCIe register field see the PCI Express Specification." hexmask.long.word 0x0 0.--15. 1. "FRS_MESSAGE_QUE_FUNC_ID,FRS Message Queue Function ID. For a description of this standard PCIe register field see the PCI Express Specification." tree.end tree "PF0_PTM_CAP (PF PTM Capability Structure)" group.long (0x0+0x40C)++0xB line.long 0x0 "PTM_EXT_CAP_HDR_OFF,Precision Time Measurement Capability Header. For a description of this standard PCIe register. see the PCI Express Specification." hexmask.long.word 0x0 20.--31. 1. "PTM_NEXT_OFFSET,Precision Time Measurement PCI Express Extended Capability Next Offset. For a description of this standard PCIe register see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access. -.." hexmask.long.byte 0x0 16.--19. 1. "PTM_CAP_VERSION,Precision Time Measurement PCI Express Extended Capability Version. For a description of this standard PCIe register see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi:.." hexmask.long.word 0x0 0.--15. 1. "PTM_CAP_ID,Precision Time Measurement PCI Express Extended Capability ID. For a description of this standard PCIe register see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if.." line.long 0x4 "PTM_CAP_OFF,PTM Capability Register. For a description of this standard PCIe register. see the PCI Express Specification." hexmask.long.word 0x4 16.--31. 1. "RSVDP_16,Reserved for future use." hexmask.long.byte 0x4 8.--15. 1. "PTM_CLK_GRAN,PTM Local Clock Granularity. For a description of this standard PCIe register see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky).." hexmask.long.byte 0x4 3.--7. 1. "RSVDP_3,Reserved for future use." bitfld.long 0x4 2. "PTM_ROOT_CAPABLE,PTM Root Capable. For a description of this standard PCIe register see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else.." "0,1" bitfld.long 0x4 1. "PTM_RES_CAPABLE,PTM Responder Capable. For a description of this standard PCIe register see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else.." "0,1" newline bitfld.long 0x4 0. "PTM_REQ_CAPABLE,PTM Requester Capable. For a description of this standard PCIe register see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else.." "0,1" line.long 0x8 "PTM_CONTROL_OFF,PTM Control Register. For a description of this standard PCIe register. see the PCI Express Specification." hexmask.long.word 0x8 16.--31. 1. "RSVDP_16,Reserved for future use." hexmask.long.byte 0x8 8.--15. 1. "EFF_GRAN,PTM Effective Granularity. For a description of this standard PCIe register see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: HWINIT" hexmask.long.byte 0x8 2.--7. 1. "RSVDP_2,Reserved for future use." rbitfld.long 0x8 1. "ROOT_SELECT,PTM Root Select. When set this Time Source is the PTM Root. For a description of this standard PCIe register see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: HWINIT" "0,1" bitfld.long 0x8 0. "PTM_ENABLE,PTM Enable. When set this function is permitted to participate in the PTM mechanism. For a description of this standard PCIe register see the PCI Express Specification." "0,1" tree.end tree "PF0_PTM_RES_CAP (PF PTM Responder Capability Structure (VSEC))" group.long (0x0+0x418)++0xB line.long 0x0 "PTM_RES_CAP_HDR_OFF,Precision Time Measurement Responder Capability Header (VSEC). For more details. see the PTM section in the Databook." hexmask.long.word 0x0 20.--31. 1. "PTM_RES_EXT_CAP_NEXT_OFFS,Precision Time Measurement Responder VSEC Next Pointer. For more details see the PTM section in the Databook. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then.." hexmask.long.byte 0x0 16.--19. 1. "PTM_RES_EXT_CAP_VER,Precision Time Measurement Responder VSEC Version. For more details see the PTM section in the Databook. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else.." hexmask.long.word 0x0 0.--15. 1. "PTM_RES_EXT_CAP_ID,Precision Time Measurement Responder VSEC ID. For more details see the PTM section in the Databook. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else.." line.long 0x4 "PTM_RES_HDR_OFF,Precision Time Measurement Responder Vendor Specific Header. For more details. see the PTM section in the Databook." hexmask.long.word 0x4 20.--31. 1. "PTM_RES_VSEC_LENGTH,PTM Responder VSEC Length. For more details see the PTM section in the Databook. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This.." hexmask.long.byte 0x4 16.--19. 1. "PTM_RES_VSEC_REV,PTM Responder VSEC Revision. For more details see the PTM section in the Databook. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This.." hexmask.long.word 0x4 0.--15. 1. "PTM_RES_VSEC_ID,PTM Responder VSEC ID. For more details see the PTM section in the Databook. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register.." line.long 0x8 "PTM_RES_CONTROL_OFF,PTM Responder Control Register. For more details. see the PTM section in the Databook." hexmask.long 0x8 2.--31. 1. "RSVDP_2,Reserved for future use." bitfld.long 0x8 1. "PTM_RES_PDEL_BYTE_REV,PTM Requester Propagation Delay Byte Reversal - Reverse the order of bytes in the PTM Propagation Delay data word of the PTM ResponseD Message for compatibility with previous revisions. For more details see the PTM section in the.." "0,1" bitfld.long 0x8 0. "PTM_RES_CCONTEXT_VALID,PTM Responder Control Context Valid - PTM Local Timing is valid. This bit is set over the DBI. A speed change or aux_clk_active will set this bit low. For more details see the PTM section in the Databook. Note: The access.." "0,1" rgroup.long (0xC+0x418)++0x3 line.long 0x0 "PTM_RES_STATUS_OFF,PTM Responder Status Register. For more details. see the PTM section in the Databook." hexmask.long 0x0 2.--31. 1. "RSVDP_2,Reserved for future use." bitfld.long 0x0 1. "PTM_RES_REQUEST_RECEIVED,PTM 1st Request Received - PTM Responder has received the first PTM Request Message. Upon receipt of a second PTM Request Message a ResponseD message with timing information will be sent from the Responder if the context is.." "0,1" bitfld.long 0x0 0. "PTM_RES_CONTEXT_VALID,PTM Responder Status Context Valid - PTM Local Timing Context is Valid. Value set from upstream port Requester in a Switch. Shadows the same in the control register in all other products. For more details see the PTM section in the.." "0,1" group.long (0x10+0x418)++0x7 line.long 0x0 "PTM_RES_LOCAL_LSB_OFF,PTM Responder Local Clock LSB. For more details. see the PTM section in the Databook." hexmask.long 0x0 0.--31. 1. "PTM_RES_LOCAL_LSB,PTM Responder Local Clock LSB - Lower 32 bits of local timer value. For more details see the PTM section in the Databook. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then.." line.long 0x4 "PTM_RES_LOCAL_MSB_OFF,PTM Responder Local Clock MSB. For more details. see the PTM section in the Databook." hexmask.long 0x4 0.--31. 1. "PTM_RES_LOCAL_MSB,PTM Responder Local Clock MSB - Upper 32 bits of local timer value. For more details see the PTM section in the Databook. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then.." rgroup.long (0x18+0x418)++0x1F line.long 0x0 "PTM_RES_T2_LSB_OFF,PTM Responder T2 Timestamp LSB. For more details. see the PTM section in the Databook." hexmask.long 0x0 0.--31. 1. "PTM_RES_T2_LSB,PTM Responder T2 Timestamp LSB - Lower 32 bits of the T2 Timestamp value. For more details see the PTM section in the Databook. Note: This register field is sticky." line.long 0x4 "PTM_RES_T2_MSB_OFF,PTM Responder T2 Timestamp MSB. For more details. see the PTM section in the Databook." hexmask.long 0x4 0.--31. 1. "PTM_RES_T2_MSB,PTM Responder T2 Timestamp MSB - Upper 32 bits of the T2 Timestamp value. For more details see the PTM section in the Databook. Note: This register field is sticky." line.long 0x8 "PTM_RES_T2P_LSB_OFF,PTM Responder T2 Previous Timestamp LSB. For more details. see the PTM section in the Databook." hexmask.long 0x8 0.--31. 1. "PTM_RES_T2P_LSB,PTM Responder T2 Previous Timestamp LSB - Lower 32 bits of the previously stored T2 Timestamp value. For more details see the PTM section in the Databook. Note: This register field is sticky." line.long 0xC "PTM_RES_T2P_MSB_OFF,PTM Responder T2 Previous Timestamp MSB. For more details. see the PTM section in the Databook." hexmask.long 0xC 0.--31. 1. "PTM_RES_T2P_MSB,PTM Responder T2 Previous Timestamp MSB - Upper 32 bits of the previously stored T2 Timestamp value. For more details see the PTM section in the Databook. Note: This register field is sticky." line.long 0x10 "PTM_RES_T3_LSB_OFF,PTM Responder T3 Timestamp LSB. For more details. see the PTM section in the Databook." hexmask.long 0x10 0.--31. 1. "PTM_RES_T3_LSB,PTM Responder T3 Timestamp LSB - Lower 32 bits of the T3 Timestamp value. For more details see the PTM section in the Databook. Note: This register field is sticky." line.long 0x14 "PTM_RES_T3_MSB_OFF,PTM Responder T3 Timestamp MSB. For more details. see the PTM section in the Databook." hexmask.long 0x14 0.--31. 1. "PTM_RES_T3_MSB,PTM Responder T3 Timestamp MSB - Upper 32 bits of the T2 Timestamp value. For more details see the PTM section in the Databook. Note: This register field is sticky." line.long 0x18 "PTM_RES_T3P_LSB_OFF,PTM Responder T3 Previous Timestamp LSB. For more details. see the PTM section in the Databook." hexmask.long 0x18 0.--31. 1. "PTM_RES_T3P_LSB,PTM Responder T3 Previous Timestamp LSB - Lower 32 bits of the previously stored T3 Timestamp value. For more details see the PTM section in the Databook. Note: This register field is sticky." line.long 0x1C "PTM_RES_T3P_MSB_OFF,PTM Responder T3 Previous Timestamp MSB. For more details. see the PTM section in the Databook." hexmask.long 0x1C 0.--31. 1. "PTM_RES_T3P_MSB,PTM Responder T3 Previous Timestamp MSB - Upper 32 bits of the previously stored T3 Timestamp value. For more details see the PTM section in the Databook. Note: This register field is sticky." group.long (0x38+0x418)++0x7 line.long 0x0 "PTM_RES_TX_LATENCY_OFF,PTM Responder TX Latency. For more details. see the PTM section in the Databook." hexmask.long.tbyte 0x0 12.--31. 1. "RSVDP_12,Reserved for future use." hexmask.long.word 0x0 0.--11. 1. "PTM_RES_TX_LATENCY,PTM Responder TX Latency - Responder Transmit path latency (12 bit wide). For more details see the PTM section in the Databook. Note: This register field is sticky." line.long 0x4 "PTM_RES_RX_LATENCY_OFF,PTM Responder RX Latency. For more details. see the PTM section in the Databook." hexmask.long.tbyte 0x4 12.--31. 1. "RSVDP_12,Reserved for future use." hexmask.long.word 0x4 0.--11. 1. "PTM_RES_RX_LATENCY,PTM Responder RX Latency - Responder Receive path latency (12 bit wide). For more details see the PTM section in the Databook. Note: This register field is sticky." rgroup.long (0x40+0x418)++0x3 line.long 0x0 "PTM_RES_NOM_CLOCK_T_OFF,PTM Responder Nominal Clock Period. For more details. see the PTM section in the Databook." hexmask.long.byte 0x0 24.--31. 1. "RSVDP_24,Reserved for future use." hexmask.long.byte 0x0 16.--23. 1. "PTM_RES_NOM_CLOCK_T_INT,PTM Responder Nominal Clock Period Integral - Integral part of the nominal PTM local clock period in nanoseconds. For more details see the PTM section in the Databook. Note: This register field is sticky." hexmask.long.word 0x0 0.--15. 1. "PTM_RES_NOM_CLOCK_T_FRAC,PTM Responder Nominal Clock Period Fractional - Fractional part of the nominal PTM local clock period. LSB is 1/(2^16) nanoseconds. For more details see the PTM section in the Databook. Note: This register field is sticky." group.long (0x44+0x418)++0x3 line.long 0x0 "PTM_RES_SCALED_CLOCK_T_OFF,PTM Responder Scaled Clock Period. For more details. see the PTM section in the Databook." bitfld.long 0x0 31. "PTM_RES_SCALED_CLOCK_T_EN,PTM Responder Scaled Clock Period Enable - Use the programmed scaled PTM clock period rather than the nominal values. This bit is cleared when the core_clk rate starts to change and can only be set when the clock period change.." "0,1" hexmask.long.byte 0x0 24.--30. 1. "RSVDP_24,Reserved for future use." hexmask.long.byte 0x0 16.--23. 1. "PTM_RES_SCALED_CLOCK_T_INT,PTM Responder Scaled Clock Period Integral - Integral part of the nominal PTM local clock period in nanoseconds. For more details see the PTM section in the Databook. Note: This register field is sticky." newline hexmask.long.word 0x0 0.--15. 1. "PTM_RES_SCALED_CLOCK_T_FRAC,PTM Responder Scaled Clock Period Fractional - Fractional part of the nominal PTM local clock period. LSB is 1/(2^16) nanoseconds. For more details see the PTM section in the Databook. Note: This register field is sticky." tree.end tree "PF0_PM_CAP (PF PCI Power Management Capability Structure)" group.long (0x0+0x40)++0x7 line.long 0x0 "CAP_ID_NXT_PTR_REG,Power Management Capabilities Register." hexmask.long.byte 0x0 27.--31. 1. "PME_SUPPORT,PME_Support. This 5-bit field indicates the power states in which the function may generate a PME and/or forward PME messages. A value of 0b for any bit indicates that the function is not capable of asserting PME while in that power state. -.." bitfld.long 0x0 26. "D2_SUPPORT,D2_Support. If this bit is set this function supports the D2 Power Management state. Functions that do not support D2 must always return a value of 0b for this bit. Note: The access attributes of this field are as follows: - Wire: No access." "0,1" bitfld.long 0x0 25. "D1_SUPPORT,D1_Support. If this bit is set this function supports the D1 Power Management state. Functions that do not support D1 must always return a value of 0b for this bit. Note: The access attributes of this field are as follows: - Wire: No access." "0,1" bitfld.long 0x0 22.--24. "AUX_CURR,Aux_Current. This 3 bit field reports the Vaux auxiliary current requirements for the function. If this function implements the Data Register the controller hardwires this field to 000b. If PME_Support is 0 xxxxb (PME assertion from D3cold is.." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 21. "DSI,Device Specific Initialization. The DSI bit indicates whether special initialization of this function is required. When set indicates that the function requires a device specific initialization sequence following a transition to the D0uninitialized.." "0,1" bitfld.long 0x0 20. "PME_IMM_READI_RETURN_DO,Immediate_Readiness_on_Return_to_D0. - If this bit is a '1' this function is guaranteed to be ready to successfully complete valid accesses immediately after being set to D0. These accesses include configuration cycles and if.." "0,1" rbitfld.long 0x0 19. "PME_CLK,PME Clock. Does not apply to PCI Express the controller hardwires it to 0b. Note: This register field is sticky." "0,1" bitfld.long 0x0 16.--18. "PM_SPEC_VER,Version. This field provides the Power Management specification version. The controller hardwires this field to 011b for functions compliant to PCI Express Base Specification Revision 4.0 Version 1.0>. Note: The access attributes of this.." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x0 8.--15. 1. "PM_NEXT_POINTER,Next Capability Pointer. This field provides an offset into the function's configuration space pointing to the location of next item in the capabilities list. If there are no additional items in the capabilities list this field is set to.." hexmask.long.byte 0x0 0.--7. 1. "PM_CAP_ID,Capability ID. This field returns 01h to indicate that this is the PCI Power Management Capability. Each function may have only one item in its capability list with Capability ID set to 01h." line.long 0x4 "CON_STATUS_REG,Power Management Control and Status Register. This register is used to manage the PCI function's power management state as well as to enable/monitor PMEs." hexmask.long.byte 0x4 24.--31. 1. "DATA_REG_ADD_INFO,Data. This field is used to report the state dependent data requested by the Data_Select field. The value of this field is scaled by the value reported by the Data_Scale field." rbitfld.long 0x4 23. "BUS_PWR_CLK_CON_EN,Bus Power/Clock Control Enable. For a description of this standard PCIe register field see the PCI Express Base Specification." "0,1" rbitfld.long 0x4 22. "B2_B3_SUPPORT,B2B3 Support for D3hot. For a description of this standard PCIe register field see the PCI Express Base Specification." "0,1" hexmask.long.byte 0x4 16.--21. 1. "RSVDP_16,Reserved for future use." newline bitfld.long 0x4 15. "PME_STATUS,PME_Status. This bit is set when the function normally generates a PME signal. The value of this bit is not affected by the value of the PME_En bit. If PME_Support bit 31 of the Power Management Capabilities register is clear this bit is.." "0,1" rbitfld.long 0x4 13.--14. "DATA_SCALE,Data_Scale. This field indicates the scaling factor to be used when interpreting the value of the Data field. The value and meaning of this field varies depending on which data value has been selected by the Data_Select field. For more details.." "0,1,2,3" hexmask.long.byte 0x4 9.--12. 1. "DATA_SELECT,Data_Select. This 4-bit field is used to select which data is to be reported through the Data and Data_Scale field. If the Data field is not implemented this field must be hardwired to 0000b." bitfld.long 0x4 8. "PME_ENABLE,PME_En. - When set the function is permitted to generate a PME. - When clear the function is not permitted to generate a PME. If PME_Support is 1 xxxxb (PME generation from D3cold) or the function consumes Aux power and Aux power is.." "0,1" newline hexmask.long.byte 0x4 4.--7. 1. "RSVDP_4,Reserved for future use." bitfld.long 0x4 3. "NO_SOFT_RST,No_Soft_Reset. This bit indicates the state of the function after writing the PowerState field to transition the function from D3hot to D0. - When set this transition preserves internal function state. The function is in D0Active and no.." "0,1" rbitfld.long 0x4 2. "RSVDP_2,Reserved for future use." "0,1" bitfld.long 0x4 0.--1. "POWER_STATE,PowerState. This 2-bit field is used both to determine the current power state of a function and to set the function into a new power state. The definition of the field values is given below. You can write to this register; however the.." "D0,D1,D2,D3hot" tree.end tree "PF0_PCIE_CAP (PF PCI Express Capability Structure)" group.long (0x0+0x70)++0x33 line.long 0x0 "PCIE_CAP_ID_PCIE_NEXT_CAP_PTR_PCIE_CAP_REG,PCI Express Capabilities. ID. Next Pointer Register." rbitfld.long 0x0 31. "RSVDP_31,Reserved for future use." "0,1" rbitfld.long 0x0 30. "RSVD,Reserved." "0,1" newline hexmask.long.byte 0x0 25.--29. 1. "PCIE_INT_MSG_NUM,PCIE Interrupt Message Number. For a description of this standard PCIe register field see the PCI Express Base Specification. Interrupt Message Number. This field indicates which MSI/MSI-X vector is used for the interrupt message.." bitfld.long 0x0 24. "PCIE_SLOT_IMP,Slot Implemented. When set this bit indicates that the Link associated with this Port is connected to a slot (as compared to being connected to a system-integrated device or being disabled). This bit is valid for Downstream Ports. This bit.." "0,1" newline hexmask.long.byte 0x0 20.--23. 1. "PCIE_DEV_PORT_TYPE,Device/Port Type. Indicates the specific type of this PCI Express function. Note: Different functions in a Multi-Function Device can generally be of different types. Defined encodings for functions that implement a Type 00h PCI.." hexmask.long.byte 0x0 16.--19. 1. "PCIE_CAP_REG,Capability Version. Indicates PCI-SIG defined PCI Express Capability structure version number. A version of the specification that changes the PCI Express Capability structure in a way that is not otherwise identifiable (for example through.." newline hexmask.long.byte 0x0 8.--15. 1. "PCIE_CAP_NEXT_PTR,Next Capability Pointer. This field contains the offset to the next PCI Capability structure or 00h if no other items exist in the linked list of Capabilities. Note: The access attributes of this field are as follows: - Wire: No access." hexmask.long.byte 0x0 0.--7. 1. "PCIE_CAP_ID,Capability ID. Indicates the PCI Express Capability structure. This field must return a Capability ID of 10h indicating that this is a PCI Express Capability structure." line.long 0x4 "DEVICE_CAPABILITIES_REG,Device Capabilities Register. The Device Capabilities register identifies PCI Express device function specific capabilities." hexmask.long.word 0x4 16.--31. 1. "RSVDP_16,Reserved for future use." bitfld.long 0x4 15. "PCIE_CAP_ROLE_BASED_ERR_REPORT,Role-Based Error Reporting. When set this bit indicates that the function implements the functionality originally defined in the Error Reporting ECN for PCI Express Base Specification Revision 1.0a and later incorporated.." "0,1" newline hexmask.long.word 0x4 6.--14. 1. "RSVDP_6,Reserved for future use." bitfld.long 0x4 5. "PCIE_CAP_EXT_TAG_SUPP,Extended Tag Field Supported. This bit in combination with the 10-Bit Tag Requester Supported bit in the Device Capabilities 2 register indicates the maximum supported size of the Tag field as a Requester. This bit must be set if.." "0,1" newline bitfld.long 0x4 3.--4. "PCIE_CAP_PHANTOM_FUNC_SUPPORT,Phantom Functions Supported. This field indicates the support for use of unclaimed function numbers to extend the number of outstanding transactions allowed by logically combining unclaimed function numbers (called Phantom.." "0,1,2,3" bitfld.long 0x4 0.--2. "PCIE_CAP_MAX_PAYLOAD_SIZE,Max_Payload_Size Supported. This field indicates the maximum payload size that the function can support for TLPs. Defined encodings are: - 000b: 128 bytes max payload size - 001b: 256 bytes max payload size - 010b: 512 bytes max.." "0,1,2,3,4,5,6,7" line.long 0x8 "DEVICE_CONTROL_DEVICE_STATUS,Device Control and Device Status Register. This register controls PCI Express device specific parameters and provides information about PCI Express device (function) specific parameters." hexmask.long.word 0x8 22.--31. 1. "RSVDP_22,Reserved for future use." rbitfld.long 0x8 21. "PCIE_CAP_TRANS_PENDING,Transactions Pending. Endpoints: When set this bit indicates that the function has issued Non-Posted Requests that have not been completed. A Function reports this bit cleared only when all outstanding Non-Posted Requests have.." "0,1" newline rbitfld.long 0x8 20. "PCIE_CAP_AUX_POWER_DETECTED,AUX Power Detected. Functions that require Aux power report this bit as set if Aux power is detected by the function. This bit is derived by sampling the sys_aux_pwr_det input." "0,1" bitfld.long 0x8 19. "PCIE_CAP_UNSUPPORTED_REQ_DETECTED,Unsupported Request Detected. This bit indicates that the function received an Unsupported Request. Errors are logged in this register regardless of whether error reporting is enabled or not in the Device Control.." "0,1" newline bitfld.long 0x8 18. "PCIE_CAP_FATAL_ERR_DETECTED,Fatal Error Detected. This bit indicates status of Fatal errors detected. Errors are logged in this register regardless of whether error reporting is enabled or not in the Device Control register. For a Multi-Function device.." "0,1" bitfld.long 0x8 17. "PCIE_CAP_NON_FATAL_ERR_DETECTED,Non-Fatal Error Detected. This bit indicates status of Non-fatal errors detected. Errors are logged in this register regardless of whether error reporting is enabled or not in the Device Control register. For a.." "0,1" newline bitfld.long 0x8 16. "PCIE_CAP_CORR_ERR_DETECTED,Correctable Error Detected. This bit indicates status of correctable errors detected. Errors are logged in this register regardless of whether error reporting is enabled or not in the Device Control register. For a.." "0,1" bitfld.long 0x8 15. "PCIE_CAP_INITIATE_FLR,Initiate Function Level Reset (applicable to Endpoints with Function Level Reset Capability set to 1b). A write of 1b initiates Function Level Reset to the Function. The value read by software from this bit is always 0b." "0,1" newline bitfld.long 0x8 12.--14. "PCIE_CAP_MAX_READ_REQ_SIZE,Max_Read_Request_Size. This field sets the maximum Read Request size for the function as a Requester. The function must not generate Read Requests with a size exceeding the set value. Defined encodings for this field are: -.." "0,1,2,3,4,5,6,7" rbitfld.long 0x8 11. "PCIE_CAP_EN_NO_SNOOP,Enable No Snoop. If this bit is set the function is permitted to Set the No Snoop bit in the Requester Attributes of transactions it initiates that do not require hardware enforced cache coherency (see section 2.2.6.5 in PCI Express.." "0,1" newline bitfld.long 0x8 10. "PCIE_CAP_AUX_POWER_PM_EN,Aux Power PM Enable. This bit is derived by sampling the sys_aux_pwr_det input. When set this bit enables a function to draw Aux power independent of PME Aux power. Functions that require Aux power on legacy operating systems.." "0,1" rbitfld.long 0x8 9. "PCIE_CAP_PHANTOM_FUNC_EN,Phantom Functions Enable. This bit in combination with the 10-Bit Tag Requester Enable bit in the Device Control 2 register determines how many Tag field bits a Requester is permitted to use. When the 10-Bit Tag Requester.." "0,1" newline rbitfld.long 0x8 8. "PCIE_CAP_EXT_TAG_EN,Extended Tag Field Enable. This bit in combination with the 10-Bit Tag Requester Enable bit in the Device Control 2 register determines how many Tag field bits a Requester is permitted to use. When the 10-Bit Tag Requester Enable.." "0,1" bitfld.long 0x8 5.--7. "PCIE_CAP_MAX_PAYLOAD_SIZE_CS,Max_Payload_Size. This field sets maximum TLP payload size for the Function. As a Receiver the Function must handle TLPs as large as the set value. As a Transmitter the Function must not generate TLPs exceeding the set.." "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 4. "PCIE_CAP_EN_REL_ORDER,Enable Relaxed Ordering. If this bit is set the function is permitted to set the Relaxed Ordering bit in the Attributes field of transactions it initiates that do not require strong write ordering (for more details see section.." "0,1" bitfld.long 0x8 3. "PCIE_CAP_UNSUPPORT_REQ_REP_EN,Unsupported Request Reporting Enable. This bit in conjunction with other bits controls the signaling of Unsupported Request Errors by sending error Messages (for more details see section 6.2.5 and section 6.2.6 of PCI.." "0,1" newline bitfld.long 0x8 2. "PCIE_CAP_FATAL_ERR_REPORT_EN,Fatal Error Reporting Enable. This bit in conjunction with other bits controls sending ERR_FATAL Messages (for more details see section 6.2.5 and section 6.2.6 of of PCI Express Base Specification). For a Multi-Function.." "0,1" bitfld.long 0x8 1. "PCIE_CAP_NON_FATAL_ERR_REPORT_EN,Non-Fatal Error Reporting Enable. This bit in conjunction with other bits controls sending ERR_NONFATAL Messages (for more details see section 6.2.5 and Section 6.2.6 of PCI Express Base Specification). For a.." "0,1" newline bitfld.long 0x8 0. "PCIE_CAP_CORR_ERR_REPORT_EN,Correctable Error Reporting Enable. This bit in conjunction with other bits controls sending ERR_COR Messages (for more details see section 6.2.5 section 6.2.6 and section 6.2.10.2 of PCI Express Base Specification). For.." "0,1" line.long 0xC "LINK_CAPABILITIES_REG,Link Capabilities Register. The Link Capabilities register identifies PCI Express Link specific capabilities." hexmask.long.byte 0xC 24.--31. 1. "PCIE_CAP_PORT_NUM,Port Number. This field indicates the PCI Express Port number for the given PCI Express Link. Multi-Function Devices associated with an Upstream Port must report the same value in this field for all functions. Note: The access.." rbitfld.long 0xC 23. "RSVDP_23,Reserved for future use." "0,1" newline bitfld.long 0xC 22. "PCIE_CAP_ASPM_OPT_COMPLIANCE,ASPM Optionality Compliance. This bit must be set to 1b in all functions. Components implemented against certain earlier versions of this specification will have this bit set to 0b. Software is permitted to use the value of.." "0,1" bitfld.long 0xC 21. "PCIE_CAP_LINK_BW_NOT_CAP,Link Bandwidth Notification Capability. A value of 1b indicates support for the Link Bandwidth Notification status and interrupt mechanisms. This capability is required for all Root Ports and Switch Downstream Ports supporting.." "0,1" newline rbitfld.long 0xC 20. "PCIE_CAP_DLL_ACTIVE_REP_CAP,Data Link Layer Link Active Reporting Capable. For a Downstream Port the controller hardwires this bit to 1b if the component supports the optional capability of reporting the DL_Active state of the Data Link Control and.." "0,1" bitfld.long 0xC 19. "PCIE_CAP_SURPRISE_DOWN_ERR_REP_CAP,Surprise Down Error Reporting Capable. For a Downstream Port this bit must be set if the component supports the optional capability of detecting and reporting a Surprise Down error condition. For Upstream Ports and.." "0,1" newline rbitfld.long 0xC 18. "PCIE_CAP_CLOCK_POWER_MAN,Clock Power Management. For Upstream Ports a value of 1b in this bit indicates that the component tolerates the removal of any reference clock(s) via the 'clock request' (CLKREQ#) mechanism when the Link is in the L1 and L2/L3.." "0,1" bitfld.long 0xC 15.--17. "PCIE_CAP_L1_EXIT_LATENCY,L1 Exit Latency. This field indicates the L1 exit latency for the given PCI Express Link. The value reported indicates the length of time this Port requires to complete transition from ASPM L1 to L0. If ASPM L1 is not supported.." "0,1,2,3,4,5,6,7" newline bitfld.long 0xC 12.--14. "PCIE_CAP_L0S_EXIT_LATENCY,L0s Exit Latency. This field indicates the L0s exit latency for the given PCI Express Link. The value reported indicates the length of time this Port requires to complete transition from L0s to L0. If L0s is not supported the.." "0,1,2,3,4,5,6,7" bitfld.long 0xC 10.--11. "PCIE_CAP_ACTIVE_STATE_LINK_PM_SUPPORT,Active State Power Management (ASPM) Support. This field indicates the level of ASPM supported on the given PCI Express Link. For more details on ASPM support requirements see section 5.4.1 of PCI Express Base.." "0,1,2,3" newline hexmask.long.byte 0xC 4.--9. 1. "PCIE_CAP_MAX_LINK_WIDTH,Maximum Link Width. This field indicates the maximum Link width (xN - corresponding to N Lanes) implemented by the component. This value is permitted to exceed the number of Lanes routed to the slot (Downstream Port) adapter.." hexmask.long.byte 0xC 0.--3. 1. "PCIE_CAP_MAX_LINK_SPEED,Max Link Speed. This field indicates the maximum Link speed of the associated Port. The encoded value specifies a bit location in the Supported Link Speeds Vector (in the Link Capabilities 2 register) that corresponds to the.." line.long 0x10 "LINK_CONTROL_LINK_STATUS_REG,Link Control and Link Status Register. This register controls and provides information about PCI Express Link specific parameters." bitfld.long 0x10 31. "PCIE_CAP_LINK_AUTO_BW_STATUS,Link Autonomous Bandwidth Status. This bit is set by hardware to indicate that hardware has autonomously changed Link speed or width without the Port transitioning through DL_Down status for reasons other than to attempt to.." "0,1" bitfld.long 0x10 30. "PCIE_CAP_LINK_BW_MAN_STATUS,Link Bandwidth Management Status. This bit is set by hardware to indicate that either of the following has occurred without the Port transitioning through DL_Down status: - A Link retraining has completed following a write of.." "0,1" newline rbitfld.long 0x10 29. "PCIE_CAP_DLL_ACTIVE,Data Link Layer Link Active. This bit indicates the status of the Data Link Control and Management State Machine. It returns a 1b to indicate the DL_Active state 0b otherwise. This bit must be implemented if the Data Link Layer Link.." "0,1" bitfld.long 0x10 28. "PCIE_CAP_SLOT_CLK_CONFIG,Slot Clock Configuration. This bit indicates that the component uses the same physical reference clock that the platform provides on the connector. If the device uses an independent clock irrespective of the presence of a.." "0,1" newline rbitfld.long 0x10 27. "PCIE_CAP_LINK_TRAINING,Link Training. This read-only bit indicates that the Physical Layer LTSSM is in the Configuration or Recovery state or that 1b was written to the Retrain Link bit but Link training has not yet begun. Hardware clears this bit when.." "0,1" rbitfld.long 0x10 26. "RSVDP_26,Reserved for future use." "0,1" newline hexmask.long.byte 0x10 20.--25. 1. "PCIE_CAP_NEGO_LINK_WIDTH,Negotiated Link Width. This field indicates the negotiated width of the given PCI Express Link. Defined encodings are: -00 0001b: x1 -00 0010b: x2 -00 0100b: x4 -00 1000b: x8 -00 1100b: x12 -01 0000b: x16 -10 0000b: x32 All other.." hexmask.long.byte 0x10 16.--19. 1. "PCIE_CAP_LINK_SPEED,Current Link Speed. This field indicates the negotiated Link speed of the given PCI Express Link. The encoded value specifies a bit location in the Supported Link Speeds Vector (in the Link Capabilities 2 register) that corresponds to.." newline bitfld.long 0x10 14.--15. "PCIE_CAP_DRS_SIGNALING_CONTROL,DRS Signaling Control. Indicates the mechanism used to report reception of a DRS message. Must be implemented for Downstream Ports with the DRS Supported bit Set in the Link Capabilities 2 Register. Encodings are: - 00b:.." "0,1,2,3" rbitfld.long 0x10 12.--13. "RSVDP_12,Reserved for future use." "0,1,2,3" newline bitfld.long 0x10 11. "PCIE_CAP_LINK_AUTO_BW_INT_EN,Link Autonomous Bandwidth Management Interrupt Enable. When set this bit enables the generation of an interrupt to indicate that the Link Autonomous Bandwidth Status bit has been set. The write value is gated with the.." "0,1" bitfld.long 0x10 10. "PCIE_CAP_LINK_BW_MAN_INT_EN,Link Bandwidth Management Interrupt Enable. When set this bit enables the generation of an interrupt to indicate that the Link Bandwidth Management Status bit has been set. The write value is gated with the.." "0,1" newline bitfld.long 0x10 9. "PCIE_CAP_HW_AUTO_WIDTH_DISABLE,Hardware Autonomous Width Disable. When set this bit disables hardware from changing the Link width for reasons other than attempting to correct unreliable Link operation by reducing Link width. For a Multi-Function Device.." "0,1" bitfld.long 0x10 8. "PCIE_CAP_EN_CLK_POWER_MAN,Enable Clock Power Management. Applicable only for Upstream Ports and with form factors that support a 'Clock Request' (CLKREQ#) mechanism this bit operates as follows: - 0b: Clock power management is disabled and device must.." "0,1" newline bitfld.long 0x10 7. "PCIE_CAP_EXTENDED_SYNCH,Extended Synch. When set this bit forces the transmission of additional Ordered Sets when exiting the L0s state (see section 4.2.4.5 of PCI Express Base Specification) and when in the Recovery state (see section 4.2.6.4.1 of PCI.." "0,1" bitfld.long 0x10 6. "PCIE_CAP_COMMON_CLK_CONFIG,Common Clock Configuration. When set this bit indicates that this component and the component at the opposite end of this Link are operating with a distributed common reference clock. A value of 0b indicates that this.." "0,1" newline bitfld.long 0x10 5. "PCIE_CAP_RETRAIN_LINK,Retrain Link. A write of 1b to this bit initiates Link retraining by directing the Physical Layer LTSSM to the Recovery state. If the LTSSM is already in Recovery or Configuration re-entering Recovery is permitted but not required." "0,1" bitfld.long 0x10 4. "PCIE_CAP_LINK_DISABLE,Link Disable. This bit disables the Link by directing the LTSSM to the Disabled state when set; this bit is Reserved on Endpoints PCI Express to PCI/PCI-X bridges and Upstream Ports of Switches. Writes to this bit are immediately.." "0,1" newline bitfld.long 0x10 3. "PCIE_CAP_RCB,Read Completion Boundary (RCB). Root Ports: Indicates the RCB value for the Root Port. Refer to section 2.3.1.1 of PCI Express Base Specification for the definition of the parameter RCB. Defined encodings are: - 0b: 64 byte - 1b: 128 byte.." "0,1" rbitfld.long 0x10 2. "RSVDP_2,Reserved for future use." "0,1" newline bitfld.long 0x10 0.--1. "PCIE_CAP_ACTIVE_STATE_LINK_PM_CONTROL,Active State Power Management (ASPM) Control. This field controls the level of ASPM enabled on the given PCI Express Link. See section 5.4.1.3 of PCI Express Base Specification for requirements on when and how to.." "0,1,2,3" line.long 0x14 "SLOT_CAPABILITIES_REG,Slot Capabilities Register. The Slot Capabilities register identifies PCI Express slot specific capabilities." hexmask.long.word 0x14 19.--31. 1. "PCIE_CAP_PHY_SLOT_NUM,Physical Slot Number. This field indicates the physical slot number attached to this Port. This field must be hardware initialized to a value that assigns a slot number that is unique within the chassis regardless of the form.." bitfld.long 0x14 18. "PCIE_CAP_NO_CMD_CPL_SUPPORT,No Command Completed Support. When set this bit indicates that this slot does not generate software notification when an issued command is completed by the Hot-Plug Controller. This bit is only permitted to be set if the.." "0,1" newline bitfld.long 0x14 17. "PCIE_CAP_ELECTROMECH_INTERLOCK,Electromechanical Interlock Present. When set this bit indicates that an Electromechanical Interlock is implemented on the chassis for this slot. Note: The access attributes of this field are as follows: - Wire: No access." "0,1" bitfld.long 0x14 15.--16. "PCIE_CAP_SLOT_POWER_LIMIT_SCALE,Slot Power Limit Scale. Specifies the scale used for the Slot Power Limit Value (for more details see Section 6.9 of PCI Express Base Specification). Range of Values: - 00b: 1.0x - 01b: 0.1x - 10b: 0.01x - 11b: 0.001x.." "0,1,2,3" newline hexmask.long.byte 0x14 7.--14. 1. "PCIE_CAP_SLOT_POWER_LIMIT_VALUE,Slot Power Limit Value. In combination with the Slot Power Limit Scale value specifies the upper limit on power supplied by the slot (for more detais see Section 6.9 of PCI Express Base Specification) or by other means.." bitfld.long 0x14 6. "PCIE_CAP_HOT_PLUG_CAPABLE,Hot-Plug Capable. When set this bit indicates that this slot is capable of supporting hot-plug operations. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then R/W else R" "0,1" newline bitfld.long 0x14 5. "PCIE_CAP_HOT_PLUG_SURPRISE,Hot-Plug Surprise. When set this bit indicates that an adapter present in this slot might be removed from the system without any prior notification. This is a form factor specific capability. This bit is an indication to the.." "0,1" bitfld.long 0x14 4. "PCIE_CAP_POWER_INDICATOR,Power Indicator Present. When set this bit indicates that a Power Indicator is electrically controlled by the chassis for this slot. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if.." "0,1" newline bitfld.long 0x14 3. "PCIE_CAP_ATTENTION_INDICATOR,Attention Indicator Present. When set this bit indicates that an Attention Indicator is electrically controlled by the chassis. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if.." "0,1" bitfld.long 0x14 2. "PCIE_CAP_MRL_SENSOR,MRL Sensor Present. When set this bit indicates that an MRL Sensor is implemented on the chassis for this slot. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then R/W else R" "0,1" newline bitfld.long 0x14 1. "PCIE_CAP_POWER_CONTROLLER,Power Controller Present. When set this bit indicates that a software programmable Power Controller is implemented for this slot/adapter (depending on form factor). Note: The access attributes of this field are as follows: -.." "0,1" bitfld.long 0x14 0. "PCIE_CAP_ATTENTION_INDICATOR_BUTTON,Attention Button Present. When set this bit indicates that an Attention Button for this slot is electrically controlled by the chassis. Note: The access attributes of this field are as follows: - Wire: No access. -.." "0,1" line.long 0x18 "SLOT_CONTROL_SLOT_STATUS,Slot Control and Status Register. This register controls and provides information about PCI Express Slot specific parameters." hexmask.long.byte 0x18 25.--31. 1. "RSVDP_25,Reserved for future use." bitfld.long 0x18 24. "PCIE_CAP_DLL_STATE_CHANGED,Data Link Layer State Changed. This bit is set when the value reported in the Data Link Layer Link Active bit of the Link Status register is changed. In response to a Data Link Layer State Changed event software must read the.." "0,1" newline rbitfld.long 0x18 23. "PCIE_CAP_ELECTROMECH_INTERLOCK_STATUS,Electromechanical Interlock Status. If an Electromechanical Interlock is implemented this bit indicates the status of the Electromechanical Interlock. Defined encodings are: - 0b: Electromechanical Interlock.." "0,1" rbitfld.long 0x18 22. "PCIE_CAP_PRESENCE_DETECT_STATE,Presence Detect State. This bit indicates the presence of an adapter in the slot reflected by the logical 'OR' of the Physical Layer in-band presence detect mechanism and if present any out-of-band presence detect.." "0,1" newline rbitfld.long 0x18 21. "PCIE_CAP_MRL_SENSOR_STATE,MRL Sensor State. This bit reports the status of the MRL sensor if implemented. Defined encodings are: - 0b: MRL Closed - 1b: MRL Open" "0,1" bitfld.long 0x18 20. "PCIE_CAP_CMD_CPLD,Command Completed. If Command Completed notification is supported (if the No Command Completed Support bit in the Slot Capabilities register is 0b) this bit is set when a hot-plug command has completed and the Hot-Plug Controller is.." "0,1" newline bitfld.long 0x18 19. "PCIE_CAP_PRESENCE_DETECTED_CHANGED,Presence Detect Changed. This bit is set when the value reported in the Presence Detect State bit is changed." "0,1" bitfld.long 0x18 18. "PCIE_CAP_MRL_SENSOR_CHANGED,MRL Sensor Changed. If an MRL sensor is implemented this bit is set when a MRL Sensor state change is detected. If an MRL sensor is not implemented this bit must not be set." "0,1" newline bitfld.long 0x18 17. "PCIE_CAP_POWER_FAULT_DETECTED,Power Fault Detected. If a Power Controller that supports power fault detection is implemented this bit issSet when the Power Controller detects a power fault at this slot. Note: Depending on hardware capability it is.." "0,1" bitfld.long 0x18 16. "PCIE_CAP_ATTENTION_BUTTON_PRESSED,Attention Button Pressed. If an Attention Button is implemented this bit is set when the attention button is pressed. If an Attention Button is not supported this bit must not be set." "0,1" newline rbitfld.long 0x18 14.--15. "RSVDP_14,Reserved for future use." "0,1,2,3" bitfld.long 0x18 12. "PCIE_CAP_DLL_STATE_CHANGED_EN,Data Link Layer State Changed Enable. If the Data Link Layer Link Active Reporting capability is 1b this bit enables software notification when Data Link Layer Link Active bit is changed. If the Data Link Layer Link Active.." "0,1" newline bitfld.long 0x18 11. "PCIE_CAP_ELECTROMECH_INTERLOCK_CTRL,Electromechanical Interlock Control. If an Electromechanical Interlock is implemented a write of 1b to this bit causes the state of the interlock to toggle. A write of 0b to this bit has no effect. A read of this bit.." "0,1" bitfld.long 0x18 10. "PCIE_CAP_POWER_CONTROLLER_CTRL,Power Controller Control. If a Power Controller is implemented this bit when written sets the power state of the slot per the defined encodings. Reads of this bit must reflect the value from the latest write even if the.." "0,1" newline bitfld.long 0x18 8.--9. "PCIE_CAP_POWER_INDICATOR_CTRL,Power Indicator Control. If a Power Indicator is implemented writes to this field set the Power Indicator to the written state. Reads of this field must reflect the value from the latest write even if the corresponding.." "0,1,2,3" bitfld.long 0x18 6.--7. "PCIE_CAP_ATTENTION_INDICATOR_CTRL,Attention Indicator Control. If an Attention Indicator is implemented writes to this field set the Attention Indicator to the written state. Reads of this field must reflect the value from the latest write even if the.." "0,1,2,3" newline bitfld.long 0x18 5. "PCIE_CAP_HOT_PLUG_INT_EN,Hot-Plug Interrupt Enable. When set this bit enables generation of an interrupt on enabled hot-plug events. If the Hot Plug Capable bit in the Slot Capabilities register is clear this bit is permitted to be read-only with a.." "0,1" bitfld.long 0x18 4. "PCIE_CAP_CMD_CPL_INT_EN,Command Completed Interrupt Enable. If Command Completed notification is supported (if the No Command Completed Support bit in the Slot Capabilities register is 0b) when set this bit enables software notification when a hot-plug.." "0,1" newline bitfld.long 0x18 3. "PCIE_CAP_PRESENCE_DETECT_CHANGE_EN,Presence Detect Changed Enable. When set this bit enables software notification on a presence detect changed event (for more details see Section 6.7.3 of PCI Express Base Specification). If the Hot-Plug Capable bit in.." "0,1" bitfld.long 0x18 2. "PCIE_CAP_MRL_SENSOR_CHANGED_EN,MRL Sensor Changed Enable. When set this bit enables software notification on a MRL sensor changed event (for more details see Section 6.7.3 of PCI Express Base Specification). If the MRL Sensor Present bit in the Slot.." "0,1" newline bitfld.long 0x18 1. "PCIE_CAP_POWER_FAULT_DETECTED_EN,Power Fault Detected Enable. When set this bit enables software notification on a power fault event (for more details see Section 6.7.3 of PCI Express Base Specification). If a Power Controller that supports power fault.." "0,1" bitfld.long 0x18 0. "PCIE_CAP_ATTENTION_BUTTON_PRESSED_EN,Attention Button Pressed Enable. When set to 1b this bit enables software notification on an attention button pressed event (for more details see Section 6.7.3 of PCI Express Base Specification). If the Attention.." "0,1" line.long 0x1C "ROOT_CONTROL_ROOT_CAPABILITIES_REG,Root Control and Capabilities Register. This register controls PCI Express Root Complex specific parameters and identifies PCI Express Root Port specific capabilities." hexmask.long.word 0x1C 17.--31. 1. "RSVDP_17,Reserved for future use." bitfld.long 0x1C 16. "PCIE_CAP_CRS_SW_VISIBILITY,CRS Software Visibility Capable. For a description of this standard PCIe register field see the PCI Express Base Specification. CRS Software Visibility. When set this bit indicates that the Root Port is capable of returning.." "0,1" newline hexmask.long.word 0x1C 5.--15. 1. "RSVDP_5,Reserved for future use." bitfld.long 0x1C 4. "PCIE_CAP_CRS_SW_VISIBILITY_EN,CRS Software Visibility Enable. When set this bit enables the Root Port to return Configuration Request Retry Status (CRS) Completion Status to software (for more details see section 2.3.1 of PCI Express Base.." "0,1" newline bitfld.long 0x1C 3. "PCIE_CAP_PME_INT_EN,PME Interrupt Enable. When set this bit enables PME interrupt generation upon receipt of a PME Message as reflected in the PME Status bit (for more details see Table 7-29 of PCI Express Base Specification). A PME interrupt is also.." "0,1" bitfld.long 0x1C 2. "PCIE_CAP_SYS_ERR_ON_FATAL_ERR_EN,System Error on Fatal Error Enable. If set this bit indicates that a System Error should be generated if a Fatal error (ERR_FATAL) is reported by any of the devices in the Hierarchy Domain associated with this Root Port.." "0,1" newline bitfld.long 0x1C 1. "PCIE_CAP_SYS_ERR_ON_NON_FATAL_ERR_EN,System Error on Non-Fatal Error Enable. If set this bit indicates that a System Error should be generated if a Non-fatal error (ERR_NONFATAL) is reported by any of the devices in the Hierarchy Domain associated with.." "0,1" bitfld.long 0x1C 0. "PCIE_CAP_SYS_ERR_ON_CORR_ERR_EN,System Error on Correctable Error Enable. If set this bit indicates that a System Error should be generated if a correctable error (ERR_COR) is reported by any of the devices in the Hierarchy Domain associated with this.." "0,1" line.long 0x20 "ROOT_STATUS_REG,Root Status Register. The Root Status register provides information about PCI Express device specific parameters." hexmask.long.word 0x20 18.--31. 1. "RSVDP_18,Reserved for future use." rbitfld.long 0x20 17. "PCIE_CAP_PME_PENDING,PME Pending. This bit indicates that another PME is pending when the PME Status bit is s et. When the PME Status bit is cleared by software; the PME is delivered by hardware by setting the PME Status bit again and updating the PME.." "0,1" newline bitfld.long 0x20 16. "PCIE_CAP_PME_STATUS,PME Status. This bit indicates that PME was asserted by the PME Requester indicated in the PME Requester ID field. Subsequent PMEs are kept pending until the status register is cleared by software by writing a 1b." "0,1" hexmask.long.word 0x20 0.--15. 1. "PCIE_CAP_PME_REQ_ID,PME Requester ID. This field indicates the PCI Requester ID of the last PME Requester. This field is only valid when the PME Status bit is set." line.long 0x24 "DEVICE_CAPABILITIES2_REG,Device Capabilities 2 Register." bitfld.long 0x24 31. "PCIE_CAP_FRS_SUPPORTED,FRS Supported. When set indicates support for the optional Function Readiness Status (FRS) capability. Must be set for all Functions that support generation or reception capabilities of FRS Messages. Must not be set by Switch.." "0,1" hexmask.long.byte 0x24 24.--30. 1. "RSVDP_24,Reserved for future use." newline bitfld.long 0x24 22.--23. "PCIE_CAP2_CFG_MAX_END2END_TLP_PRFXS,Max End-End TLP Prefixes. Indicates the maximum number of End-End TLP Prefixes supported by this Function. For more details see Section 2.2.10.2 of PCI Express Base Specification. Values are: - 01b: 1 End-End TLP.." "0,1,2,3" bitfld.long 0x24 21. "PCIE_CAP2_CFG_END2END_TLP_PRFX_SUPPORT,End-End TLP Prefix Supported. Indicates whether End-End TLP Prefix support is offered by a Function. Values are: - 0b: No Support - 1b: Support is provided to receive TLPs containing End-End TLP Prefixes. All Ports.." "0,1" newline bitfld.long 0x24 20. "PCIE_CAP2_CFG_EXTND_FMT_SUPPORT,Extended Fmt Field Supported. If set the Function supports the 3-bit definition of the Fmt field. If clear the Function supports a 2-bit definition of the Fmt field. For more details see section 2.2 of PCI Express Base.." "0,1" rbitfld.long 0x24 17. "PCIE_CAP2_10_BIT_TAG_REQ_SUPPORT,10-Bit Tag Requester Supported. If this bit is set the Function supports 10-Bit Tag Requester capability; otherwise the Function does not. This bit must not be set if the 10-Bit Tag Completer Supported bit is clear." "0,1" newline rbitfld.long 0x24 16. "PCIE_CAP2_10_BIT_TAG_COMP_SUPPORT,10-Bit Tag Completer Supported. If this bit is set the Function supports 10-Bit Tag Completer capability; otherwise the Function does not. For more details see section 2.2.6.2. of PCI Express Base Specification." "0,1" rbitfld.long 0x24 13. "PCIE_CAP_TPH_CMPLT_SUPPORT_1,TPH Completer Supported Bit 1." "0,1" newline rbitfld.long 0x24 12. "PCIE_CAP_TPH_CMPLT_SUPPORT_0,TPH Completer Supported Bit 0. Value of this bit along with TPH Completer Supported Bit 1 indicates Completer support for TPH or Extended TPH. Applicable only to Root Ports and Endpoints. For all other Functions this field.." "0,1" bitfld.long 0x24 11. "PCIE_CAP_LTR_SUPP,LTR Mechanism Supported. A value of 1b indicates support for the optional Latency Tolerance Reporting (LTR) mechanism. Root Ports Switches and Endpoints are permitted to implement this capability. For a Multi-Function Device associated.." "0,1" newline rbitfld.long 0x24 10. "PCIE_CAP_NO_RO_EN_PR2PR_PAR,No RO-enabled PR-PR Passing. If this bit is set the routing element never carries out the passing permitted by Table 2-39 of PCI Express Base Specification entry A2b that is associated with the Relaxed Ordering Attribute.." "0,1" rbitfld.long 0x24 9. "PCIE_CAP_128_CAS_CPL_SUPP,128-bit CAS Completer Supported. Applicable to Functions with Memory Space BARs as well as all Root Ports; must be 0b otherwise. This bit must be set to 1b if the Function supports this optional capability. For more details see.." "0,1" newline rbitfld.long 0x24 8. "PCIE_CAP_64_ATOMIC_CPL_SUPP,64-bit AtomicOp Completer Supported. Applicable to Functions with Memory Space BARs as well as all Root Ports; must be 0b otherwise. Includes FetchAdd Swap and CAS AtomicOps. This bit must be set to 1b if the Function.." "0,1" rbitfld.long 0x24 7. "PCIE_CAP_32_ATOMIC_CPL_SUPP,32-bit AtomicOp Completer Supported. Applicable to Functions with Memory Space BARs as well as all Root Ports; must be 0b otherwise. Includes FetchAdd Swap and CAS AtomicOps. This bit must be set to 1b if the Function.." "0,1" newline rbitfld.long 0x24 6. "PCIE_CAP_ATOMIC_ROUTING_SUPP,AtomicOp Routing Supported. Applicable only to Switch Upstream Ports Switch Downstream Ports and Root Ports; must be 0b for other Function types. This bit must be set to 1b if the Port supports this optional capability. For.." "0,1" rbitfld.long 0x24 5. "PCIE_CAP_ARI_FORWARD_SUPPORT,ARI Forwarding Supported. Applicable only to Switch Downstream Ports and Root Ports; must be 0b for other Function types. This bit must be set to 1b if a Switch Downstream Port or Root Port supports this optional capability." "0,1" newline rbitfld.long 0x24 4. "PCIE_CAP_CPL_TIMEOUT_DISABLE_SUPPORT,Completion Timeout Disable Supported. A value of 1b indicates support for the Completion Timeout Disable mechanism. The Completion Timeout Disable mechanism is required for Endpoints that issue Requests on their own.." "0,1" hexmask.long.byte 0x24 0.--3. 1. "PCIE_CAP_CPL_TIMEOUT_RANGE,Completion Timeout Ranges Supported. This field indicates device Function support for the optional Completion Timeout programmability mechanism. This mechanism allows system software to modify the Completion Timeout value. This.." line.long 0x28 "DEVICE_CONTROL2_DEVICE_STATUS2_REG,Device Control 2 and Status 2 Register." hexmask.long.word 0x28 16.--31. 1. "RSVDP_16,Reserved for future use." bitfld.long 0x28 15. "PCIE_CTRL2_CFG_END2END_TLP_PFX_BLCK,End-End TLP Prefix Blocking. Controls whether the routing function is permitted to forward TLPs containing an End-End TLP Prefix. Values are: - 0b: Forwarding Enabled - Function is permitted to send TLPs with End-End.." "0,1" newline rbitfld.long 0x28 11. "RSVDP_11,Reserved for future use." "0,1" bitfld.long 0x28 10. "PCIE_CAP_LTR_EN,LTR Mechanism Enable. When set to 1b this bit enables Upstream Ports to send LTR messages and Downstream Ports to process LTR Messages. For a Multi-Function Device associated with an Upstream Port of a device that implements LTR the bit.." "0,1" newline rbitfld.long 0x28 5. "PCIE_CAP_ARI_FORWARD_SUPPORT_CS,ARI Forwarding Enable. When set the Downstream Port disables its traditional Device Number field being 0 enforcement when turning a Type 1 Configuration Request into a Type 0 Configuration Request permitting access to.." "0,1" bitfld.long 0x28 4. "PCIE_CAP_CPL_TIMEOUT_DISABLE,Completion Timeout Disable. When set this bit disables the Completion Timeout mechanism. This bit is required for all Functions that support the Completion Timeout Disable Capability. Functions that do not support this.." "0,1" newline hexmask.long.byte 0x28 0.--3. 1. "PCIE_CAP_CPL_TIMEOUT_VALUE,Completion Timeout Value. In device Functions that support Completion Timeout programmability this field allows system software to modify the Completion Timeout value. This field is applicable to Root Ports Endpoints that.." line.long 0x2C "LINK_CAPABILITIES2_REG,Link Capabilities 2 Register." bitfld.long 0x2C 31. "DRS_SUPPORTED,DRS Supported. When set indicates support for the optional Device Readiness Status (DRS) capability. Must be Set in Downstream Ports that support DRS. Must be Set in Downstream Ports that support FRS. For Upstream Ports that support DRS.." "0,1" hexmask.long.byte 0x2C 25.--30. 1. "RSVDP_25,Reserved for future use." newline hexmask.long.word 0x2C 9.--22. 1. "RSVDP_9,Reserved for future use." rbitfld.long 0x2C 8. "PCIE_CAP_CROSS_LINK_SUPPORT,Crosslink Supported. When set to 1b this bit indicates that the associated Port supports crosslinks (for more details see section 4.2.6.3.1 of PCI Express Base Specification). When set to 0b on a Port that supports Link.." "0,1" newline hexmask.long.byte 0x2C 1.--7. 1. "PCIE_CAP_SUPPORT_LINK_SPEED_VECTOR,Supported Link Speeds Vector. This field indicates the supported Link speed(s) of the associated Port. For each bit a value of 1b indicates that the corresponding Link speed is supported; otherwise the Link speed is.." rbitfld.long 0x2C 0. "RSVDP_0,Reserved for future use." "0,1" line.long 0x30 "LINK_CONTROL2_LINK_STATUS2_REG,Link Control 2 and Status 2 Register." bitfld.long 0x30 31. "DRS_MESSAGE_RECEIVED,DRS Message Received. This bit must be set whenever the Port receives a DRS Message. This bit must be cleared in DL_Down. This bit must be implemented in any Downstream Port where the DRS Supported bit is Set in the Link Capabilities.." "0,1" rbitfld.long 0x30 28.--30. "DOWNSTREAM_COMPO_PRESENCE,Downstream Component Presence. This field indicates the presence and DRS status for the Downstream Component if any connected to the Link; defined values are: - 000b: Link Down - Presence Not Determined - 001b: Link Down -.." "0,1,2,3,4,5,6,7" newline rbitfld.long 0x30 26.--27. "RSVDP_26,Reserved for future use." "0,1,2,3" bitfld.long 0x30 21. "PCIE_CAP_LINK_EQ_REQ,Link Equalization Request 8.0 GT/s. This bit is set by hardware to request the 8.0 GT/s Link equalization process to be performed on the Link. For more details see sections 4.2.3 and 4.2.6.4.2 of PCI Express Base Specification. For.." "0,1" newline rbitfld.long 0x30 20. "PCIE_CAP_EQ_CPL_P3,EEqualization 8.0 GT/s Phase 3 Successful. When set to 1b this bit indicates that Phase 3 of the 8.0 GT/s Transmitter Equalization procedure has successfully completed. Details of the Transmitter Equalization process and when this bit.." "0,1" rbitfld.long 0x30 19. "PCIE_CAP_EQ_CPL_P2,Equalization 8.0 GT/s Phase 2 Successful. When set to 1b this bit indicates that Phase 2 of the 8.0 GT/s Transmitter Equalization procedure has successfully completed. Details of the Transmitter Equalization process and when this bit.." "0,1" newline rbitfld.long 0x30 18. "PCIE_CAP_EQ_CPL_P1,Equalization 8.0 GT/s Phase 1 Successful. When set to 1b this bit indicates that Phase 1 of the 8.0 GT/s Transmitter Equalization procedure has successfully completed. Details of the Transmitter Equalization process and when this bit.." "0,1" rbitfld.long 0x30 17. "PCIE_CAP_EQ_CPL,Equalization 8.0 GT/s Complete. When set to 1b this bit indicates that the Transmitter Equalization procedure at the 8.0 GT/s data rate has completed. Details of the Transmitter Equalization process and when this bit needs to be set to.." "0,1" newline rbitfld.long 0x30 16. "PCIE_CAP_CURR_DEEMPHASIS,Current De-emphasis Level. When the Link is operating at 5.0 GT/s speed this bit reflects the level of de-emphasis. Encodings: - 1b: -3.5 dB - 0b: -6 dB The value in this bit is undefined when the Link is not operating at 5.0.." "0,1" hexmask.long.byte 0x30 12.--15. 1. "PCIE_CAP_COMPLIANCE_PRESET,Compliance Preset/De-emphasis. For 8.0 GT/s and higher Data Rate: This field sets the Transmitter Preset in Polling.Compliance state if the entry occurred due to the Enter Compliance bit being 1b. The encodings are defined in.." newline bitfld.long 0x30 11. "PCIE_CAP_COMPLIANCE_SOS,Compliance SOS. When set to 1b the LTSSM is required to send SKP Ordered Sets between sequences when sending the Compliance Pattern or Modified Compliance Pattern. For a Multi-Function Device associated with an Upstream Port the.." "0,1" bitfld.long 0x30 10. "PCIE_CAP_ENTER_MODIFIED_COMPLIANCE,Enter Modified Compliance. When this bit is set to 1b the device transmits Modified Compliance Pattern if the LTSSM enters Polling.Compliance substate. Components that support only the 2.5 GT/s speed are permitted to.." "0,1" newline bitfld.long 0x30 7.--9. "PCIE_CAP_TX_MARGIN,Transmit Margin - This field controls the value of the non-deemphasized voltage level at the Transmitter pins. This field is reset to 000b on entry to the LTSSM Polling.Configuration substate (see Chapter 4 of PCI Express Base.." "0,1,2,3,4,5,6,7" bitfld.long 0x30 6. "PCIE_CAP_SEL_DEEMPHASIS,Selectable De-emphasis. When the Link is operating at 5.0 GT/s speed this bit is used to control the transmit de-emphasis of the link in specific situations. For more details see section 4.2.6 of PCI Express Base Specification." "0,1" newline bitfld.long 0x30 5. "PCIE_CAP_HW_AUTO_SPEED_DISABLE,Hardware Autonomous Speed Disable. When set this bit disables hardware from changing the Link speed for device-specific reasons other than attempting to correct unreliable Link operation by reducing Link speed. Initial.." "0,1" bitfld.long 0x30 4. "PCIE_CAP_ENTER_COMPLIANCE,Enter Compliance. Software is permitted to force a Link to enter Compliance mode (at the speed indicated in the Target Link Speed field and the de-emphasis/preset level indicated by the Compliance Preset/De-emphasis field) by.." "0,1" newline hexmask.long.byte 0x30 0.--3. 1. "PCIE_CAP_TARGET_LINK_SPEED,Target Link Speed. For Downstream Ports this field sets an upper limit on Link operational speed by restricting the values advertised by the Upstream component in its training sequences. The encoded value specifies a bit.." tree.end tree "PF0_AER_CAP (PF Advanced Error Reporting Capability Structure)" group.long (0x0+0x100)++0x1B line.long 0x0 "AER_EXT_CAP_HDR_OFF,Advanced Error Reporting Extended Capability Header. For a description of this standard PCIe register. see the PCI Express Specification." hexmask.long.word 0x0 20.--31. 1. "NEXT_OFFSET,Next Capability Offset. For a description of this standard PCIe register field see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky).." hexmask.long.byte 0x0 16.--19. 1. "CAP_VERSION,Capability Version. For a description of this standard PCIe register field see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else.." hexmask.long.word 0x0 0.--15. 1. "CAP_ID,AER Extended Capability ID. For a description of this standard PCIe register field see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else.." line.long 0x4 "UNCORR_ERR_STATUS_OFF,Uncorrectable Error Status Register. For a description of this standard PCIe register. see the PCI Express Specification." hexmask.long.byte 0x4 27.--31. 1. "RSVDP_27,Reserved for future use." bitfld.long 0x4 25. "TLP_PRFX_BLOCKED_ERR_STATUS,TLP Prefix Blocked Error Status. For a description of this standard PCIe register field see the PCI Express Specification. Note: Not supported." "0,1" rbitfld.long 0x4 23. "RSVDP_23,Reserved for future use." "0,1" newline bitfld.long 0x4 22. "INTERNAL_ERR_STATUS,Uncorrectable Internal Error Status. For a description of this standard PCIe register field see the PCI Express Specification. The controller sets this bit when your application asserts app_err_bus[9]. It does not set this bit when.." "0,1" bitfld.long 0x4 20. "UNSUPPORTED_REQ_ERR_STATUS,Unsupported Request Error Status. For a description of this standard PCIe register field see the PCI Express Specification." "0,1" bitfld.long 0x4 19. "ECRC_ERR_STATUS,ECRC Error Status. For a description of this standard PCIe register field see the PCI Express Specification. Note:If CX_ECRC_ENABLE=0 the register field always reads 0." "0,1" newline bitfld.long 0x4 18. "MALF_TLP_ERR_STATUS,Malformed TLP Status. For a description of this standard PCIe register field see the PCI Express Specification." "0,1" bitfld.long 0x4 17. "REC_OVERFLOW_ERR_STATUS,Receiver Overflow Status. For a description of this standard PCIe register field see the PCI Express Specification." "0,1" bitfld.long 0x4 16. "UNEXP_CMPLT_ERR_STATUS,Unexpected Completion Status. For a description of this standard PCIe register field see the PCI Express Specification." "0,1" newline bitfld.long 0x4 15. "CMPLT_ABORT_ERR_STATUS,Completer Abort Status. For a description of this standard PCIe register field see the PCI Express Specification." "0,1" bitfld.long 0x4 14. "CMPLT_TIMEOUT_ERR_STATUS,Completion Timeout Status. For a description of this standard PCIe register field see the PCI Express Specification." "0,1" bitfld.long 0x4 13. "FC_PROTOCOL_ERR_STATUS,Flow Control Protocol Error Status. For a description of this standard PCIe register field see the PCI Express Specification." "0,1" newline bitfld.long 0x4 12. "POIS_TLP_ERR_STATUS,Poisoned TLP Status. For a description of this standard PCIe register field see the PCI Express Specification." "0,1" hexmask.long.byte 0x4 6.--11. 1. "RSVDP_6,Reserved for future use." bitfld.long 0x4 5. "SURPRISE_DOWN_ERR_STATUS,Surprise Down Error Status (Optional). For a description of this standard PCIe register field see the PCI Express Specification." "0,1" newline bitfld.long 0x4 4. "DL_PROTOCOL_ERR_STATUS,Data Link Protocol Error Status. For a description of this standard PCIe register field see the PCI Express Specification." "0,1" hexmask.long.byte 0x4 0.--3. 1. "RSVDP_0,Reserved for future use." line.long 0x8 "UNCORR_ERR_MASK_OFF,Uncorrectable Error Mask Register. For a description of this standard PCIe register. see the PCI Express Specification." hexmask.long.byte 0x8 27.--31. 1. "RSVDP_27,Reserved for future use." bitfld.long 0x8 25. "TLP_PRFX_BLOCKED_ERR_MASK,TLP Prefix Blocked Error Mask. For a description of this standard PCIe register field see the PCI Express Specification. Note: Not supported. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi:.." "0,1" rbitfld.long 0x8 23. "RSVDP_23,Reserved for future use." "0,1" newline bitfld.long 0x8 22. "INTERNAL_ERR_MASK,Uncorrectable Internal Error Mask (Optional). For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." "0,1" rbitfld.long 0x8 21. "ACS_VIOLATION_MASK,ACS Violation Mask. Setting the ACS Violation Mask bit disables error logging and signaling for ACS Violation errors. The bit is Read-Only Zero for upstream ports when ACS P2P Egress Control Enable is not set. For a description of.." "0,1" bitfld.long 0x8 20. "UNSUPPORTED_REQ_ERR_MASK,Unsupported Request Error Mask. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." "0,1" newline bitfld.long 0x8 19. "ECRC_ERR_MASK,ECRC Error Mask (Optional). For a description of this standard PCIe register field see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W (sticky) Note: This register.." "0,1" bitfld.long 0x8 18. "MALF_TLP_ERR_MASK,Malformed TLP Mask. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." "0,1" bitfld.long 0x8 17. "REC_OVERFLOW_ERR_MASK,Receiver Overflow Mask (Optional). For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." "0,1" newline bitfld.long 0x8 16. "UNEXP_CMPLT_ERR_MASK,Unexpected Completion Mask. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." "0,1" bitfld.long 0x8 15. "CMPLT_ABORT_ERR_MASK,Completer Abort Error Mask (Optional). For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." "0,1" bitfld.long 0x8 14. "CMPLT_TIMEOUT_ERR_MASK,Completion Timeout Error Mask. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." "0,1" newline bitfld.long 0x8 13. "FC_PROTOCOL_ERR_MASK,Flow Control Protocol Error Mask. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." "0,1" bitfld.long 0x8 12. "POIS_TLP_ERR_MASK,Poisoned TLP Error Mask. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." "0,1" hexmask.long.byte 0x8 6.--11. 1. "RSVDP_6,Reserved for future use." newline rbitfld.long 0x8 5. "SURPRISE_DOWN_ERR_MASK,Surprise Down Error Mask. For a description of this standard PCIe register field see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi:.." "0,1" bitfld.long 0x8 4. "DL_PROTOCOL_ERR_MASK,Data Link Protocol Error Mask. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." "0,1" hexmask.long.byte 0x8 0.--3. 1. "RSVDP_0,Reserved for future use." line.long 0xC "UNCORR_ERR_SEV_OFF,Uncorrectable Error Severity Register. For a description of this standard PCIe register. see the PCI Express Specification." hexmask.long.byte 0xC 27.--31. 1. "RSVDP_27,Reserved for future use." bitfld.long 0xC 25. "TLP_PRFX_BLOCKED_ERR_SEVERITY,TLP Prefix Blocked Error Severity (Optional). For a description of this standard PCIe register field see the PCI Express Specification. Note: Not supported. Note: The access attributes of this field are as follows: - Wire:.." "0,1" rbitfld.long 0xC 24. "ATOMIC_EGRESS_BLOCKED_ERR_SEVERITY,AtomicOp Egress Blocked Severity (Optional). For a description of this standard PCIe register field see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi:.." "0,1" newline rbitfld.long 0xC 23. "RSVDP_23,Reserved for future use." "0,1" bitfld.long 0xC 22. "INTERNAL_ERR_SEVERITY,Uncorrectable Internal Error Severity (Optional). For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." "0,1" bitfld.long 0xC 20. "UNSUPPORTED_REQ_ERR_SEVERITY,Unsupported Request Error Severity. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." "0,1" newline bitfld.long 0xC 19. "ECRC_ERR_SEVERITY,ECRC Error Severity (Optional). For a description of this standard PCIe register field see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W (sticky) Note: This.." "0,1" bitfld.long 0xC 18. "MALF_TLP_ERR_SEVERITY,Malformed TLP Severity. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." "0,1" bitfld.long 0xC 17. "REC_OVERFLOW_ERR_SEVERITY,Receiver Overflow Error Severity (Optional). For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." "0,1" newline bitfld.long 0xC 16. "UNEXP_CMPLT_ERR_SEVERITY,Unexpected Completion Error Severity. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." "0,1" bitfld.long 0xC 15. "CMPLT_ABORT_ERR_SEVERITY,Completer Abort Error Severity (Optional). For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." "0,1" bitfld.long 0xC 14. "CMPLT_TIMEOUT_ERR_SEVERITY,Completion Timeout Error Severity. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." "0,1" newline bitfld.long 0xC 13. "FC_PROTOCOL_ERR_SEVERITY,Flow Control Protocol Error Severity (Optional). For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." "0,1" bitfld.long 0xC 12. "POIS_TLP_ERR_SEVERITY,Poisoned TLP Severity. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." "0,1" hexmask.long.byte 0xC 6.--11. 1. "RSVDP_6,Reserved for future use." newline rbitfld.long 0xC 5. "SURPRISE_DOWN_ERR_SVRITY,Surprise Down Error Severity (Optional). For a description of this standard PCIe register field see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi:.." "0,1" bitfld.long 0xC 4. "DL_PROTOCOL_ERR_SEVERITY,Data Link Protocol Error Severity. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." "0,1" hexmask.long.byte 0xC 0.--3. 1. "RSVDP_0,Reserved for future use." line.long 0x10 "CORR_ERR_STATUS_OFF,Correctable Error Status Register. For a description of this standard PCIe register. see the PCI Express Specification." hexmask.long.word 0x10 16.--31. 1. "RSVDP_16,Reserved for future use." bitfld.long 0x10 15. "HEADER_LOG_OVERFLOW_STATUS,Header Log Overflow Error Status (Optional). For a description of this standard PCIe register field see the PCI Express Specification." "0,1" bitfld.long 0x10 14. "CORRECTED_INT_ERR_STATUS,Corrected Internal Error Status (Optional). For a description of this standard PCIe register field see the PCI Express Specification." "0,1" newline bitfld.long 0x10 13. "ADVISORY_NON_FATAL_ERR_STATUS,Advisory Non-Fatal Error Status. For a description of this standard PCIe register field see the PCI Express Specification." "0,1" bitfld.long 0x10 12. "RPL_TIMER_TIMEOUT_STATUS,Replay Timer Timeout Status. For a description of this standard PCIe register field see the PCI Express Specification." "0,1" rbitfld.long 0x10 9.--11. "RSVDP_9,Reserved for future use." "0,1,2,3,4,5,6,7" newline bitfld.long 0x10 8. "REPLAY_NO_ROLEOVER_STATUS,REPLAY_NUM Rollover Status. For a description of this standard PCIe register field see the PCI Express Specification." "0,1" bitfld.long 0x10 7. "BAD_DLLP_STATUS,Bad DLLP Status. For a description of this standard PCIe register field see the PCI Express Specification." "0,1" bitfld.long 0x10 6. "BAD_TLP_STATUS,Bad TLP Status. For a description of this standard PCIe register field see the PCI Express Specification." "0,1" newline hexmask.long.byte 0x10 1.--5. 1. "RSVDP_1,Reserved for future use." bitfld.long 0x10 0. "RX_ERR_STATUS,Receiver Error Status (Optional). For a description of this standard PCIe register field see the PCI Express Specification." "0,1" line.long 0x14 "CORR_ERR_MASK_OFF,Correctable Error Mask Register. For a description of this standard PCIe register. see the PCI Express Specification." hexmask.long.word 0x14 16.--31. 1. "RSVDP_16,Reserved for future use." bitfld.long 0x14 15. "HEADER_LOG_OVERFLOW_MASK,Header Log Overflow Error Mask (Optional). For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." "0,1" bitfld.long 0x14 14. "CORRECTED_INT_ERR_MASK,Corrected Internal Error Mask (Optional). For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." "0,1" newline bitfld.long 0x14 13. "ADVISORY_NON_FATAL_ERR_MASK,Advisory Non-Fatal Error Mask. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." "0,1" bitfld.long 0x14 12. "RPL_TIMER_TIMEOUT_MASK,Replay Timer Timeout Mask. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." "0,1" rbitfld.long 0x14 9.--11. "RSVDP_9,Reserved for future use." "0,1,2,3,4,5,6,7" newline bitfld.long 0x14 8. "REPLAY_NO_ROLEOVER_MASK,REPLAY_NUM Rollover Mask. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." "0,1" bitfld.long 0x14 7. "BAD_DLLP_MASK,Bad DLLP Mask. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." "0,1" bitfld.long 0x14 6. "BAD_TLP_MASK,Bad TLP Mask. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." "0,1" newline hexmask.long.byte 0x14 1.--5. 1. "RSVDP_1,Reserved for future use." bitfld.long 0x14 0. "RX_ERR_MASK,Receiver Error Mask (Optional). For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." "0,1" line.long 0x18 "ADV_ERR_CAP_CTRL_OFF,Advanced Error Capabilities and Control Register. For a description of this standard PCIe register. see the PCI Express Specification." hexmask.long.tbyte 0x18 13.--31. 1. "RSVDP_13,Reserved for future use." rbitfld.long 0x18 12. "CTO_PRFX_HDR_LOG_CAP,TLP Prefix Log Present. For a description of this standard PCIe register field see the PCI Express Specification." "0,1" rbitfld.long 0x18 11. "TLP_PRFX_LOG_PRESENT,Completion Timeout Prefix/Header Log Capable. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." "0,1" newline rbitfld.long 0x18 10. "MULTIPLE_HEADER_EN,Multiple Header Recording Enable. For a description of this standard PCIe register field see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R (sticky) Note: This.." "0,1" rbitfld.long 0x18 9. "MULTIPLE_HEADER_CAP,Multiple Header Recording Capable. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." "0,1" bitfld.long 0x18 8. "ECRC_CHECK_EN,ECRC Check Enable. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." "0,1" newline rbitfld.long 0x18 7. "ECRC_CHECK_CAP,ECRC Check Capable. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." "0,1" bitfld.long 0x18 6. "ECRC_GEN_EN,ECRC Generation Enable. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." "0,1" rbitfld.long 0x18 5. "ECRC_GEN_CAP,ECRC Generation Capable. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." "0,1" newline hexmask.long.byte 0x18 0.--4. 1. "FIRST_ERR_POINTER,First Error Pointer. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." rgroup.long (0x1C+0x100)++0xF line.long 0x0 "HDR_LOG_0_OFF,Header Log Register 0. For a description of this standard PCIe register. see the PCI Express Specification." hexmask.long.byte 0x0 24.--31. 1. "FIRST_DWORD_FOURTH_BYTE,Byte 3 of Header log register of First 32 bit Data Word. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." hexmask.long.byte 0x0 16.--23. 1. "FIRST_DWORD_THIRD_BYTE,Byte 2 of Header log register of First 32 bit Data Word. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." hexmask.long.byte 0x0 8.--15. 1. "FIRST_DWORD_SECOND_BYTE,Byte 1 of Header log register of First 32 bit Data Word. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." newline hexmask.long.byte 0x0 0.--7. 1. "FIRST_DWORD_FIRST_BYTE,Byte 0 of Header log register of First 32 bit Data Word. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." line.long 0x4 "HDR_LOG_1_OFF,Header Log Register 1. For a description of this standard PCIe register. see the PCI Express Specification." hexmask.long.byte 0x4 24.--31. 1. "SECOND_DWORD_FOURTH_BYTE,Byte 3 of Header log register of Second 32 bit Data Word. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." hexmask.long.byte 0x4 16.--23. 1. "SECOND_DWORD_THIRD_BYTE,Byte 2 of Header log register of Second 32 bit Data Word. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." hexmask.long.byte 0x4 8.--15. 1. "SECOND_DWORD_SECOND_BYTE,Byte 1 of Header log register of Second 32 bit Data Word. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." newline hexmask.long.byte 0x4 0.--7. 1. "SECOND_DWORD_FIRST_BYTE,Byte 0 of Header log register of Second 32 bit Data Word. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." line.long 0x8 "HDR_LOG_2_OFF,Header Log Register 2. For a description of this standard PCIe register. see the PCI Express Specification." hexmask.long.byte 0x8 24.--31. 1. "THIRD_DWORD_FOURTH_BYTE,Byte 3 of Header log register of Third 32 bit Data Word. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." hexmask.long.byte 0x8 16.--23. 1. "THIRD_DWORD_THIRD_BYTE,Byte 2 of Header log register of Third 32 bit Data Word. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." hexmask.long.byte 0x8 8.--15. 1. "THIRD_DWORD_SECOND_BYTE,Byte 1 of Header log register of Third 32 bit Data Word. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." newline hexmask.long.byte 0x8 0.--7. 1. "THIRD_DWORD_FIRST_BYTE,Byte 0 of Header log register of Third 32 bit Data Word. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." line.long 0xC "HDR_LOG_3_OFF,Header Log Register 3. For a description of this standard PCIe register. see the PCI Express Specification." hexmask.long.byte 0xC 24.--31. 1. "FOURTH_DWORD_FOURTH_BYTE,Byte 3 of Header log register of Fourth 32 bit Data Word. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." hexmask.long.byte 0xC 16.--23. 1. "FOURTH_DWORD_THIRD_BYTE,Byte 2 of Header log register of Fourth 32 bit Data Word. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." hexmask.long.byte 0xC 8.--15. 1. "FOURTH_DWORD_SECOND_BYTE,Byte 1 of Header log register of Fourth 32 bit Data Word. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." newline hexmask.long.byte 0xC 0.--7. 1. "FOURTH_DWORD_FIRST_BYTE,Byte 0 of Header log register of Fourth 32 bit Data Word. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." group.long (0x2C+0x100)++0x7 line.long 0x0 "ROOT_ERR_CMD_OFF,Root Error Command Register. For a description of this standard PCIe register. see the PCI Express Specification." hexmask.long 0x0 3.--31. 1. "RSVDP_3,Reserved for future use." bitfld.long 0x0 2. "FATAL_ERR_REPORTING_EN,Fatal Error Reporting Enable. For a description of this standard PCIe register field see the PCI Express Specification." "0,1" bitfld.long 0x0 1. "NON_FATAL_ERR_REPORTING_EN,Non-Fatal Error Reporting Enable. For a description of this standard PCIe register field see the PCI Express Specification." "0,1" newline bitfld.long 0x0 0. "CORR_ERR_REPORTING_EN,Correctable Error Reporting Enable. For a description of this standard PCIe register field see the PCI Express Specification." "0,1" line.long 0x4 "ROOT_ERR_STATUS_OFF,Root Error Status Register. For a description of this standard PCIe register. see the PCI Express Specification." hexmask.long.byte 0x4 27.--31. 1. "ADV_ERR_INT_MSG_NUM,Advanced Error Interrupt Message Number. For a description of this standard PCIe register field see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN.." hexmask.long.tbyte 0x4 7.--26. 1. "RSVDP_7,Reserved for future use." bitfld.long 0x4 6. "FATAL_ERR_MSG_RX,One or more Fatal Error Messages Received. For a description of this standard PCIe register field see the PCI Express Specification." "0,1" newline bitfld.long 0x4 5. "NON_FATAL_ERR_MSG_RX,One or more Non-Fatal Error Messages Received. For a description of this standard PCIe register field see the PCI Express Specification." "0,1" bitfld.long 0x4 4. "FIRST_UNCORR_FATAL,First Uncorrectable Error is Fatal. For a description of this standard PCIe register field see the PCI Express Specification." "0,1" bitfld.long 0x4 3. "MUL_ERR_FATAL_NON_FATAL_RX,Multiple Fatal or Non-Fatal Errors Received. For a description of this standard PCIe register field see the PCI Express Specification." "0,1" newline bitfld.long 0x4 2. "ERR_FATAL_NON_FATAL_RX,Fatal or Non-Fatal Error Received. For a description of this standard PCIe register field see the PCI Express Specification." "0,1" bitfld.long 0x4 1. "MUL_ERR_COR_RX,Multiple Correctable Errors Received. For a description of this standard PCIe register field see the PCI Express Specification." "0,1" bitfld.long 0x4 0. "ERR_COR_RX,Correctable Error Received. For a description of this standard PCIe register field see the PCI Express Specification." "0,1" rgroup.long (0x34+0x100)++0x13 line.long 0x0 "ERR_SRC_ID_OFF,Error Source Identification Register. For a description of this standard PCIe register. see the PCI Express Specification." hexmask.long.word 0x0 16.--31. 1. "ERR_FATAL_NON_FATAL_SOURCE_ID,Source of Fatal/Non-Fatal Error. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." hexmask.long.word 0x0 0.--15. 1. "ERR_COR_SOURCE_ID,Source of Correctable Error. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." line.long 0x4 "TLP_PREFIX_LOG_1_OFF,TLP Prefix Log Register 1. For a description of this standard PCIe register. see the PCI Express Specification." hexmask.long.byte 0x4 24.--31. 1. "CFG_TLP_PFX_LOG_1_FOURTH_BYTE,Byte 3 of Error TLP Prefix Log 1. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." hexmask.long.byte 0x4 16.--23. 1. "CFG_TLP_PFX_LOG_1_THIRD_BYTE,Byte 2 of Error TLP Prefix Log 1. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." hexmask.long.byte 0x4 8.--15. 1. "CFG_TLP_PFX_LOG_1_SECOND_BYTE,Byte 1 of Error TLP Prefix Log 1. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." newline hexmask.long.byte 0x4 0.--7. 1. "CFG_TLP_PFX_LOG_1_FIRST_BYTE,Byte 0 of Error TLP Prefix Log 1. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." line.long 0x8 "TLP_PREFIX_LOG_2_OFF,TLP Prefix Log Register 2. For a description of this standard PCIe register. see the PCI Express Specification." hexmask.long.byte 0x8 24.--31. 1. "CFG_TLP_PFX_LOG_2_FOURTH_BYTE,Byte 3 Error TLP Prefix Log 2. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." hexmask.long.byte 0x8 16.--23. 1. "CFG_TLP_PFX_LOG_2_THIRD_BYTE,Byte 2 Error TLP Prefix Log 2. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." hexmask.long.byte 0x8 8.--15. 1. "CFG_TLP_PFX_LOG_2_SECOND_BYTE,Byte 1 Error TLP Prefix Log 2. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." newline hexmask.long.byte 0x8 0.--7. 1. "CFG_TLP_PFX_LOG_2_FIRST_BYTE,Byte 0 Error TLP Prefix Log 2. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." line.long 0xC "TLP_PREFIX_LOG_3_OFF,TLP Prefix Log Register 3. For a description of this standard PCIe register. see the PCI Express Specification." hexmask.long.byte 0xC 24.--31. 1. "CFG_TLP_PFX_LOG_3_FOURTH_BYTE,Byte 3 Error TLP Prefix Log 3. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." hexmask.long.byte 0xC 16.--23. 1. "CFG_TLP_PFX_LOG_3_THIRD_BYTE,Byte 2 Error TLP Prefix Log 3. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." hexmask.long.byte 0xC 8.--15. 1. "CFG_TLP_PFX_LOG_3_SECOND_BYTE,Byte 1 Error TLP Prefix Log 3. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." newline hexmask.long.byte 0xC 0.--7. 1. "CFG_TLP_PFX_LOG_3_FIRST_BYTE,Byte 0 Error TLP Prefix Log 3. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." line.long 0x10 "TLP_PREFIX_LOG_4_OFF,TLP Prefix Log Register 4. For a description of this standard PCIe register. see the PCI Express Specification." hexmask.long.byte 0x10 24.--31. 1. "CFG_TLP_PFX_LOG_4_FOURTH_BYTE,Byte 3 Error TLP Prefix Log 4. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." hexmask.long.byte 0x10 16.--23. 1. "CFG_TLP_PFX_LOG_4_THIRD_BYTE,Byte 2 Error TLP Prefix Log 4. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." hexmask.long.byte 0x10 8.--15. 1. "CFG_TLP_PFX_LOG_4_SECOND_BYTE,Byte 1 Error TLP Prefix Log 4. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." newline hexmask.long.byte 0x10 0.--7. 1. "CFG_TLP_PFX_LOG_4_FIRST_BYTE,Byte 0 Error TLP Prefix Log 4. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." tree.end tree "PF0_MSI_CAP (PF MSI Capability Structure)" group.long (0x0+0x50)++0x13 line.long 0x0 "PCI_MSI_CAP_ID_NEXT_CTRL_REG,MSI Capability Header and Message Control Register." hexmask.long.byte 0x0 27.--31. 1. "RSVDP_27,Reserved for future use." bitfld.long 0x0 26. "PCI_MSI_EXT_DATA_EN,Extended Message Data Enable. - If set the function is enabled to provide Extended Message Data. - If clear the function is not enabled to provide Extended Message Data. Note: The access attributes of this field are as follows: -.." "0,1" bitfld.long 0x0 25. "PCI_MSI_EXT_DATA_CAP,Extended Message Data Capable. - If set the function is capable of providing Extended Message Data. - If clear the function does not support providing Extended Message Data. Note: The access attributes of this field are as follows:.." "0,1" newline rbitfld.long 0x0 24. "PCI_PVM_SUPPORT,Per-Vector Masking Capable. - If set the function supports MSI Per-Vector Masking. - If clear the function does not support MSI Per-Vector Masking. This bit must be set if the function is a PF or VF within an SR-IOV Device." "0,1" bitfld.long 0x0 23. "PCI_MSI_64_BIT_ADDR_CAP,64 bit address capable. - If set the function is capable of sending a 64-bit message address. - If clear the function is not capable of sending a 64-bit message address. This bit must be set if the function is a PCI Express.." "0,1" bitfld.long 0x0 20.--22. "PCI_MSI_MULTIPLE_MSG_EN,Multiple Message Enable. Software writes to this field to indicate the number of allocated vectors (equal to or less than the number of requested vectors). The number of allocated vectors is aligned to a power of two. If a.." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 17.--19. "PCI_MSI_MULTIPLE_MSG_CAP,Multiple Message Capable. System software reads this field to determine the number of requested vectors. The number of requested vectors must be aligned to a power of two (if a function requires three vectors it requests four by.." "0,1,2,3,4,5,6,7" bitfld.long 0x0 16. "PCI_MSI_ENABLE,MSI Enable. - If set and the MSI-X Enable bit in the MSI-X Message Control register is clear the function is permitted to use MSI to request service and is prohibited from using INTx interrupts. System configuration software sets this bit.." "0,1" hexmask.long.byte 0x0 8.--15. 1. "PCI_MSI_CAP_NEXT_OFFSET,Next Capability Pointer. This field contains the offset to the next PCI Capability structure or 00h if no other items exist in the linked list of Capabilities. Note: The access attributes of this field are as follows: - Wire: No.." newline hexmask.long.byte 0x0 0.--7. 1. "PCI_MSI_CAP_ID,Capability ID. Indicates the MSI Capability structure. This field returns a Capability ID of 05h indicating that this is an MSI Capability structure." line.long 0x4 "MSI_CAP_OFF_04H_REG,Message Address Register for MSI (Offset 04h)." hexmask.long 0x4 2.--31. 1. "PCI_MSI_CAP_OFF_04H,Message Address - System-specified message address. If the Message Enable bit (bit 16 of the PCI_MSI_CAP_ID_NEXT_CTRL_REG register) is set the contents of this field specify the DWORD-aligned address (Address[31:02]) for the MSI.." rbitfld.long 0x4 0.--1. "RSVDP_0,Reserved for future use." "0,1,2,3" line.long 0x8 "MSI_CAP_OFF_08H_REG,For a function that supports a 32-bit message address. - bits[31:16] of this register represent the Extended Message Data. and - bits[15:0] of this register represent the Message Data For a function that supports a 64-bit message.." hexmask.long.word 0x8 16.--31. 1. "PCI_MSI_CAP_OFF_0AH,For a function that supports a 32-bit message address this field contains Extended Message Data (System-specified message data). For the MSI Capability structures without per-vector masking it must be implemented if the Extended.." hexmask.long.word 0x8 0.--15. 1. "PCI_MSI_CAP_OFF_08H,For a function that supports a 32-bit message address this field contains Message Data (System-specified message data). If the Message Enable bit (bit 16 of the PCI_MSI_CAP_ID_NEXT_CTRL_REG) is set the function sends a DWORD Memory.." line.long 0xC "MSI_CAP_OFF_0CH_REG,For a function that supports a 32-bit message address. this register contains the Mask Bits when the Per-Vector Masking Capable bit (bit 24 of PCI_MSI_CAP_ID_NEXT_CTRL_REG) is set. For a function that supports a 64-bit message.." hexmask.long.word 0xC 16.--31. 1. "PCI_MSI_CAP_OFF_0EH,For a function that supports a 32-bit message address this field contains the upper Mask Bits when the Per Vector Masking Capable bit (PCI_MSI_CAP_ID_NEXT_CTRL_REG.PCI_PVM_SUPPORT) is set. For a function that supports a 64-bit.." hexmask.long.word 0xC 0.--15. 1. "PCI_MSI_CAP_OFF_0CH,For a function that supports a 32-bit message address this field contains the lower Mask Bits when the Per Vector Masking Capable bit (PCI_MSI_CAP_ID_NEXT_CTRL_REG.PCI_PVM_SUPPORT) is set. For a function that supports a 64-bit.." line.long 0x10 "MSI_CAP_OFF_10H_REG,For a function that supports a 32-bit message address. this register contains the Pending Bits when the Per-Vector Masking Capable bit (bit 24 of PCI_MSI_CAP_ID_NEXT_CTRL_REG) is set. For a function that supports a 64-bit message.." hexmask.long 0x10 0.--31. 1. "PCI_MSI_CAP_OFF_10H,Used for MSI when the Per Vector Masking Capable bit (PCI_MSI_CAP_ID_NEXT_CTRL_REG.PCI_PVM_SUPPORT) is set. For 32-bit contains Pending Bits. For 64-bit contains Mask Bits. For a description of this standard PCIe register field see.." rgroup.long (0x14+0x50)++0x3 line.long 0x0 "MSI_CAP_OFF_14H_REG,Pending Bits Register for MSI. This register is used for a function that supports a 64-bit message address when the Per-Vector Masking Capable bit (bit 24 of PCI_MSI_CAP_ID_NEXT_CTRL_REG) is set." hexmask.long 0x0 0.--31. 1. "PCI_MSI_CAP_OFF_14H,Pending Bits. For each pending bit that is set the function has a pending associated message." tree.end tree "PF0_MSIX_CAP (PF MSI-X Capability Structure)" group.long (0x0+0xB0)++0xB line.long 0x0 "PCI_MSIX_CAP_ID_NEXT_CTRL_REG,MSI-X Capability ID. Next Pointer. Control Registers. For a description of this standard PCIe register. see the PCI Express Base Specification." bitfld.long 0x0 31. "PCI_MSIX_ENABLE,MSI-X Enable. For a description of this standard PCIe register field see the PCI Express Base Specification." "0,1" bitfld.long 0x0 30. "PCI_MSIX_FUNCTION_MASK,Function Mask. For a description of this standard PCIe register field see the PCI Express Base Specification. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" "0,1" rbitfld.long 0x0 27.--29. "RSVDP_27,Reserved for future use." "0,1,2,3,4,5,6,7" newline hexmask.long.word 0x0 16.--26. 1. "PCI_MSIX_TABLE_SIZE,MSI-X Table Size. For a description of this standard PCIe register field see the PCI Express Base Specification. SRIOV Note: All VFs in a single PF have the same value for 'MSI-X Table Size' (PCI_MSIX_TABLE_SIZE field in.." hexmask.long.byte 0x0 8.--15. 1. "PCI_MSIX_CAP_NEXT_OFFSET,MSI-X Next Capability Pointer. For a description of this standard PCIe register field see the PCI Express Base Specification. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN.." hexmask.long.byte 0x0 0.--7. 1. "PCI_MSIX_CAP_ID,MSI-X Capability ID. For a description of this standard PCIe register field see the PCI Express Base Specification." line.long 0x4 "MSIX_TABLE_OFFSET_REG,MSI-X Table Offset and BIR Register. For a description of this standard PCIe register. see the PCI Express Base Specification." hexmask.long 0x4 3.--31. 1. "PCI_MSIX_TABLE_OFFSET,MSI-X Table Offset. For a description of this standard PCIe register field see the PCI Express Base Specification. SRIOV Note: All VFs in a single PF have the same value for 'MSI-X Table Offset' (PCI_MSIX_TABLE_OFFSET field in.." bitfld.long 0x4 0.--2. "PCI_MSIX_BIR,MSI-X Table BAR Indicator Register Field. For a description of this standard PCIe register field see the PCI Express Base Specification. SRIOV Note: All VFs in a single PF have the same value for 'MSI-X Table BAR Indicator Register'.." "0,1,2,3,4,5,6,7" line.long 0x8 "MSIX_PBA_OFFSET_REG,MSI-X PBA Offset and BIR Register. For a description of this standard PCIe register. see the PCI Express Base Specification." hexmask.long 0x8 3.--31. 1. "PCI_MSIX_PBA_OFFSET,MSI-X PBA Offset. For a description of this standard PCIe register field see the PCI Express Base Specification. SRIOV Note: All VFs in a single PF have the same value for 'MSI-X PBA Offset' (PCI_MSIX_PBA_OFFSET field in.." bitfld.long 0x8 0.--2. "PCI_MSIX_PBA_BIR,MSI-X PBA BIR. For a description of this standard PCIe register field see the PCI Express Base Specification. SRIOV Note: All VFs in a single PF have the same value for 'MSI-X PBA BIR' (PCI_MSIX_PBA_BIR field in.." "0,1,2,3,4,5,6,7" tree.end tree "PF0_MSIX_CAP_DBI2 (DBI2 Shadow Block: PF MSI-X Capability Structure)" rgroup.long (0x0+0x10B0)++0x3 line.long 0x0 "SHADOW_PCI_MSIX_CAP_ID_NEXT_CTRL_REG,MSI-X Capability ID. Next Pointer. Control Registers. For a description of this standard PCIe register. see the PCI Express Base Specification." hexmask.long.byte 0x0 27.--31. 1. "RSVDP_27,Reserved for future use." hexmask.long.word 0x0 16.--26. 1. "PCI_MSIX_TABLE_SIZE,MSI-X Table Size in the shadow register. Note: The access attributes of this field are as follows: - Wire: No access - Dbi: No access - Dbi2: if (DBI_RO_WR_EN == 1) then R/W else R Note: This register field is sticky." hexmask.long.word 0x0 0.--15. 1. "RSVDP_0,Reserved for future use." group.long 0x4++0x7 line.long 0x0 "SHADOW_MSIX_TABLE_OFFSET_REG,MSI-X Table Offset and BIR Register. For a description of this standard PCIe register. see the PCI Express Base Specification." hexmask.long 0x0 3.--31. 1. "PCI_MSIX_TABLE_OFFSET,MSI-X Table Offset. For a description of this standard PCIe register field see the PCI Express Base Specification. Note: The access attributes of this field are as follows: - Wire: No access - Dbi: No access - Dbi2: if.." bitfld.long 0x0 0.--2. "PCI_MSIX_BIR,MSI-X Table BAR Indicator Register Field. For a description of this standard PCIe register field see the PCI Express Base Specification. Note: The access attributes of this field are as follows: - Wire: No access - Dbi: No access - Dbi2: if.." "?,?,if,?,?,?,?,?" line.long 0x4 "SHADOW_MSIX_PBA_OFFSET_REG,MSI-X PBA Offset and BIR Register. For a description of this standard PCIe register. see the PCI Express Base Specification." hexmask.long 0x4 3.--31. 1. "PCI_MSIX_PBA_OFFSET,MSI-X PBA Offset. For a description of this standard PCIe register field see the PCI Express Base Specification. Note: The access attributes of this field are as follows: - Wire: No access - Dbi: No access - Dbi2: if (DBI_RO_WR_EN ==.." bitfld.long 0x4 0.--2. "PCI_MSIX_PBA_BIR,MSI-X PBA BIR. For a description of this standard PCIe register field see the PCI Express Base Specification. Note: The access attributes of this field are as follows: - Wire: No access - Dbi: No access - Dbi2: if (DBI_RO_WR_EN == 1 &&.." "?,?,if,?,?,?,?,?" tree.end tree "PF0_DMA_CAP (DMA Port Logic Structure)" group.long (0x0+0xC8000)++0x3 line.long 0x0 "DMA_CTRL_DATA_ARB_PRIOR_OFF,DMA Arbitration Scheme for TRGT1 Interface. This register is used to control traffic priorities among various sources that are delivered to your application through TRGT1 where 0x0 represents the highest priority. - Non-DMA Rx.." hexmask.long.tbyte 0x0 12.--31. 1. "RSVDP_12,Reserved for future use." bitfld.long 0x0 9.--11. "RDBUFF_TRGT_WEIGHT,DMA Read Channel MWr Requests. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 6.--8. "RD_CTRL_TRGT_WEIGHT,DMA Read Channel MRd Requests. For LL element/descriptor access. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" "0,1,2,3,4,5,6,7" bitfld.long 0x0 3.--5. "WR_CTRL_TRGT_WEIGHT,DMA Write Channel MRd Requests. For DMA data requests and LL element/descriptor access. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 0.--2. "RTRGT1_WEIGHT,Non-DMA Rx Requests. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" "0,1,2,3,4,5,6,7" group.long (0x8+0xC8000)++0xB line.long 0x0 "DMA_CTRL_OFF,DMA Number of Channels Register." hexmask.long.byte 0x0 26.--31. 1. "RSVDP_26,Reserved for future use." bitfld.long 0x0 25. "DIS_C2W_CACHE_RD,Disable DMA Read Channels 'completion to memory write' context cache pre-fetch function. Note: For internal debugging only. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" "0,1" newline bitfld.long 0x0 24. "DIS_C2W_CACHE_WR,Disable DMA Write Channels 'completion to memory write' context cache pre-fetch function. Note: For internal debugging only. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" "0,1" hexmask.long.byte 0x0 20.--23. 1. "RSVDP_20,Reserved for future use." newline hexmask.long.byte 0x0 16.--19. 1. "NUM_DMA_RD_CHAN,Number of Read Channels. You can read this register to determine the number of read channels the DMA controller has been configured to support." hexmask.long.word 0x0 4.--15. 1. "RSVDP_4,Reserved for future use." newline hexmask.long.byte 0x0 0.--3. 1. "NUM_DMA_WR_CHAN,Number of Write Channels. You can read this register to determine the number of write channels the DMA controller has been configured to support." line.long 0x4 "DMA_WRITE_ENGINE_EN_OFF,DMA Write Engine Enable Register." hexmask.long.byte 0x4 24.--31. 1. "RSVDP_24,Reserved for future use." bitfld.long 0x4 23. "DMA_WRITE_ENGINE_EN_HSHAKE_CH7,Enable Handshake for DMA Write Engine Channel 7. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" "0,1" newline bitfld.long 0x4 22. "DMA_WRITE_ENGINE_EN_HSHAKE_CH6,Enable Handshake for DMA Write Engine Channel 6. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" "0,1" bitfld.long 0x4 21. "DMA_WRITE_ENGINE_EN_HSHAKE_CH5,Enable Handshake for DMA Write Engine Channel 5. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" "0,1" newline bitfld.long 0x4 20. "DMA_WRITE_ENGINE_EN_HSHAKE_CH4,Enable Handshake for DMA Write Engine Channel 4. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" "0,1" bitfld.long 0x4 19. "DMA_WRITE_ENGINE_EN_HSHAKE_CH3,Enable Handshake for DMA Write Engine Channel 3. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" "0,1" newline bitfld.long 0x4 18. "DMA_WRITE_ENGINE_EN_HSHAKE_CH2,Enable Handshake for DMA Write Engine Channel 2. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" "0,1" bitfld.long 0x4 17. "DMA_WRITE_ENGINE_EN_HSHAKE_CH1,Enable Handshake for DMA Write Engine Channel 1. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" "0,1" newline bitfld.long 0x4 16. "DMA_WRITE_ENGINE_EN_HSHAKE_CH0,Enable Handshake for DMA Write Engine Channel 0. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" "0,1" hexmask.long.word 0x4 1.--15. 1. "RSVDP_1,Reserved for future use." newline bitfld.long 0x4 0. "DMA_WRITE_ENGINE,DMA Write Engine Enable. - 1: Enable - 0: Disable (Soft Reset) For normal operation you must initially set this bit to '1' before any other software setup actions. You do not need to toggle or rewrite to this bit during normal.." "Disable,Enable" line.long 0x8 "DMA_WRITE_DOORBELL_OFF,DMA Write Doorbell Register." bitfld.long 0x8 31. "WR_STOP,Stop. Set in conjunction with the Doorbell Number field. The DMA write channel stops issuing requests sets the channel status to 'Stopped' and asserts the 'Abort' interrupt if it is enabled. Before setting the Stop bit you must read the.." "0,1" hexmask.long 0x8 3.--30. 1. "RSVDP_3,Reserved for future use." newline bitfld.long 0x8 0.--2. "WR_DOORBELL_NUM,Doorbell Number. You must write the channel number to this register to start the DMA write transfer for that channel. The DMA detects a write to this register field even if the value of this field does not change. You do not need to.." "0,1,2,3,4,5,6,7" group.long (0x18+0xC8000)++0x7 line.long 0x0 "DMA_WRITE_CHANNEL_ARB_WEIGHT_LOW_OFF,DMA Write Engine Channel Arbitration Weight Low Register. The 5-bit channel weight (for write channels 0-3) specifies the maximum number of TLP requests that the DMA can issue for that channel before it must return to.." hexmask.long.word 0x0 20.--31. 1. "RSVDP_20,Reserved for future use." hexmask.long.byte 0x0 15.--19. 1. "WRITE_CHANNEL3_WEIGHT,Channel 3 Weight. The weight is initialized by software before ringing the doorbell. The value is used by the channel weighted round robin arbiter to select the next channel read request. A value of '0' means that one TLP is issued.." newline hexmask.long.byte 0x0 10.--14. 1. "WRITE_CHANNEL2_WEIGHT,Channel 2 Weight. The weight is initialized by software before ringing the doorbell. The value is used by the channel weighted round robin arbiter to select the next channel read request. A value of '0' means that one TLP is issued.." hexmask.long.byte 0x0 5.--9. 1. "WRITE_CHANNEL1_WEIGHT,Channel 1 Weight. The weight is initialized by software before ringing the doorbell. The value is used by the channel weighted round robin arbiter to select the next channel read request. A value of '0' means that one TLP is issued.." newline hexmask.long.byte 0x0 0.--4. 1. "WRITE_CHANNEL0_WEIGHT,Channel 0 Weight. The weight is initialized by software before ringing the doorbell. The value is used by the channel weighted round robin arbiter to select the next channel read request. A value of '0' means that one TLP is issued.." line.long 0x4 "DMA_WRITE_CHANNEL_ARB_WEIGHT_HIGH_OFF,DMA Write Engine Channel Arbitration Weight High Register. The 5-bit channel weight (for write channels 4-7) specifies the maximum number of TLP requests that the DMA can issue for that channel before it must return.." hexmask.long.word 0x4 20.--31. 1. "RSVDP_20,Reserved for future use." hexmask.long.byte 0x4 15.--19. 1. "WRITE_CHANNEL7_WEIGHT,Channel 7 Weight. The weight is initialized by software before ringing the doorbell. The value is used by the channel weighted round robin arbiter to select the next channel read request. A value of '0' means that one TLP is issued.." newline hexmask.long.byte 0x4 10.--14. 1. "WRITE_CHANNEL6_WEIGHT,Channel 6 Weight. The weight is initialized by software before ringing the doorbell. The value is used by the channel weighted round robin arbiter to select the next channel read request. A value of '0' means that one TLP is issued.." hexmask.long.byte 0x4 5.--9. 1. "WRITE_CHANNEL5_WEIGHT,Channel 5 Weight. The weight is initialized by software before ringing the doorbell. The value is used by the channel weighted round robin arbiter to select the next channel read request. A value of '0' means that one TLP is issued.." newline hexmask.long.byte 0x4 0.--4. 1. "WRITE_CHANNEL4_WEIGHT,Channel 4 Weight. The weight is initialized by software before ringing the doorbell. The value is used by the channel weighted round robin arbiter to select the next channel read request. A value of '0' means that one TLP is issued.." group.long (0x2C+0xC8000)++0x7 line.long 0x0 "DMA_READ_ENGINE_EN_OFF,DMA Read Engine Enable Register." hexmask.long.byte 0x0 24.--31. 1. "RSVDP_24,Reserved for future use." bitfld.long 0x0 23. "DMA_READ_ENGINE_EN_HSHAKE_CH7,Enable Handshake for DMA Read Engine Channel 7. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" "0,1" newline bitfld.long 0x0 22. "DMA_READ_ENGINE_EN_HSHAKE_CH6,Enable Handshake for DMA Read Engine Channel 6. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" "0,1" bitfld.long 0x0 21. "DMA_READ_ENGINE_EN_HSHAKE_CH5,Enable Handshake for DMA Read Engine Channel 5. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" "0,1" newline bitfld.long 0x0 20. "DMA_READ_ENGINE_EN_HSHAKE_CH4,Enable Handshake for DMA Read Engine Channel 4. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" "0,1" bitfld.long 0x0 19. "DMA_READ_ENGINE_EN_HSHAKE_CH3,Enable Handshake for DMA Read Engine Channel 3. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" "0,1" newline bitfld.long 0x0 18. "DMA_READ_ENGINE_EN_HSHAKE_CH2,Enable Handshake for DMA Read Engine Channel 2. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" "0,1" bitfld.long 0x0 17. "DMA_READ_ENGINE_EN_HSHAKE_CH1,Enable Handshake for DMA Read Engine Channel 1. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" "0,1" newline bitfld.long 0x0 16. "DMA_READ_ENGINE_EN_HSHAKE_CH0,Enable Handshake for DMA Read Engine Channel 0. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" "0,1" hexmask.long.word 0x0 1.--15. 1. "RSVDP_1,Reserved for future use." newline bitfld.long 0x0 0. "DMA_READ_ENGINE,DMA Read Engine Enable. - 1: Enable - 0: Disable (Soft Reset) For normal operation you must initially set this bit to '1' before any other software setup actions. You do not need to toggle or rewrite to this bit during normal operation." "Disable,Enable" line.long 0x4 "DMA_READ_DOORBELL_OFF,DMA Read Doorbell Register." bitfld.long 0x4 31. "RD_STOP,Stop. Set in conjunction with the Doorbell Number field. The DMA read channel stops issuing requests sets the channel status to 'Stopped' and asserts the 'Abort' interrupt if it is enabled. Before setting the Stop bit you must read the channel.." "0,1" hexmask.long 0x4 3.--30. 1. "RSVDP_3,Reserved for future use." newline bitfld.long 0x4 0.--2. "RD_DOORBELL_NUM,Doorbell Number. You must write 0x0 to this register to start the DMA read transfer for that channel. The DMA detects a write to this register field even if the value of this field does not change. The range of this field is 0x0 to 0x7.." "0,1,2,3,4,5,6,7" group.long (0x38+0xC8000)++0x7 line.long 0x0 "DMA_READ_CHANNEL_ARB_WEIGHT_LOW_OFF,DMA Read Engine Channel Arbitration Weight Low Register. The 5-bit channel weight (for read channels 0-3) specifies the maximum number of TLP requests that the DMA can issue for that channel before it must return to.." hexmask.long.word 0x0 20.--31. 1. "RSVDP_20,Reserved for future use." hexmask.long.byte 0x0 15.--19. 1. "READ_CHANNEL3_WEIGHT,Channel 3 Weight. The weight is initialized by software before ringing the doorbell. The value is used by the channel weighted round robin arbiter to select the next channel read request. Note: The access attributes of this field are.." newline hexmask.long.byte 0x0 10.--14. 1. "READ_CHANNEL2_WEIGHT,Channel 2 Weight. The weight is initialized by software before ringing the doorbell. The value is used by the channel weighted round robin arbiter to select the next channel read request. Note: The access attributes of this field are.." hexmask.long.byte 0x0 5.--9. 1. "READ_CHANNEL1_WEIGHT,Channel 1 Weight. The weight is initialized by software before ringing the doorbell. The value is used by the channel weighted round robin arbiter to select the next channel read request. Note: The access attributes of this field are.." newline hexmask.long.byte 0x0 0.--4. 1. "READ_CHANNEL0_WEIGHT,Channel 0 Weight. The weight is initialized by software before ringing the doorbell. The value is used by the channel weighted round robin arbiter to select the next channel read request. Note: The access attributes of this field are.." line.long 0x4 "DMA_READ_CHANNEL_ARB_WEIGHT_HIGH_OFF,DMA Read Engine Channel Arbitration Weight High Register. The 5-bit channel weight (for read channels 4-7) specifies the maximum number of TLP requests that the DMA can issue for that channel before it must return to.." hexmask.long.word 0x4 20.--31. 1. "RSVDP_20,Reserved for future use." hexmask.long.byte 0x4 15.--19. 1. "READ_CHANNEL7_WEIGHT,Channel 7 Weight. The weight is initialized by software before ringing the doorbell. The value is used by the channel weighted round robin arbiter to select the next channel read request. Note: The access attributes of this field are.." newline hexmask.long.byte 0x4 10.--14. 1. "READ_CHANNEL6_WEIGHT,Channel 6 Weight. The weight is initialized by software before ringing the doorbell. The value is used by the channel weighted round robin arbiter to select the next channel read request. Note: The access attributes of this field are.." hexmask.long.byte 0x4 5.--9. 1. "READ_CHANNEL5_WEIGHT,Channel 5 Weight. The weight is initialized by software before ringing the doorbell. The value is used by the channel weighted round robin arbiter to select the next channel read request. Note: The access attributes of this field are.." newline hexmask.long.byte 0x4 0.--4. 1. "READ_CHANNEL4_WEIGHT,Channel 4 Weight. The weight is initialized by software before ringing the doorbell. The value is used by the channel weighted round robin arbiter to select the next channel read request. Note: The access attributes of this field are.." group.long (0x4C+0xC8000)++0x3 line.long 0x0 "DMA_WRITE_INT_STATUS_OFF,DMA Write Interrupt Status Register." hexmask.long.byte 0x0 24.--31. 1. "RSVDP_24,Reserved for future use." hexmask.long.byte 0x0 16.--23. 1. "WR_ABORT_INT_STATUS,Abort Interrupt Status. The DMA write channel has detected an error or you manually stopped the transfer as described in 'Error Handling Assistance by Remote Software'. Each bit corresponds to a DMA channel. Bit [0] corresponds to.." newline hexmask.long.byte 0x0 8.--15. 1. "RSVDP_8,Reserved for future use." hexmask.long.byte 0x0 0.--7. 1. "WR_DONE_INT_STATUS,Done Interrupt Status. The DMA write channel has successfully completed the DMA transfer. For more details see 'Interrupts and Error Handling'. Each bit corresponds to a DMA channel. Bit [0] corresponds to channel 0. - Enabling: For.." group.long (0x54+0xC8000)++0x7 line.long 0x0 "DMA_WRITE_INT_MASK_OFF,DMA Write Interrupt Mask Register." hexmask.long.byte 0x0 24.--31. 1. "RSVDP_24,Reserved for future use." hexmask.long.byte 0x0 16.--23. 1. "WR_ABORT_INT_MASK,Abort Interrupt Mask. Prevents the Abort interrupt status field in the DMA write interrupt status register from asserting the edma_int output. Each bit corresponds to a DMA channel. Bit [0] corresponds to channel 0. Note: The access.." newline hexmask.long.byte 0x0 8.--15. 1. "RSVDP_8,Reserved for future use." hexmask.long.byte 0x0 0.--7. 1. "WR_DONE_INT_MASK,Done Interrupt Mask. Prevents the Done interrupt status field in the DMA write interrupt status register from asserting the edma_int output. Each bit corresponds to a DMA channel. Bit [0] corresponds to channel 0. Note: The access.." line.long 0x4 "DMA_WRITE_INT_CLEAR_OFF,DMA Write Interrupt Clear Register." hexmask.long.byte 0x4 24.--31. 1. "RSVDP_24,Reserved for future use." hexmask.long.byte 0x4 16.--23. 1. "WR_ABORT_INT_CLEAR,Abort Interrupt Clear. You must write a 1'b1 to clear the corresponding bit in the Abort interrupt status field of the DMA write interrupt status register. Each bit corresponds to a DMA channel. Bit [0] corresponds to channel 0. Note:.." newline hexmask.long.byte 0x4 8.--15. 1. "RSVDP_8,Reserved for future use." hexmask.long.byte 0x4 0.--7. 1. "WR_DONE_INT_CLEAR,Done Interrupt Clear. You must write a 1'b1 to clear the corresponding bit in the Done interrupt status field of the DMA write interrupt status register. Each bit corresponds to a DMA channel. Bit [0] corresponds to channel 0. Note:.." rgroup.long (0x5C+0xC8000)++0x3 line.long 0x0 "DMA_WRITE_ERR_STATUS_OFF,DMA Write Error Status Register" hexmask.long.byte 0x0 24.--31. 1. "RSVDP_24,Reserved for future use." hexmask.long.byte 0x0 16.--23. 1. "LINKLIST_ELEMENT_FETCH_ERR_DETECT,Linked List Element Fetch Error Detected. The DMA write channel has received an error response from the AXI bus (or TRGT1 interface when the AXI Bridge is not used) while reading a linked list element from local memory." newline hexmask.long.byte 0x0 8.--15. 1. "RSVDP_8,Reserved for future use." hexmask.long.byte 0x0 0.--7. 1. "APP_READ_ERR_DETECT,Application Read Error Detected. The DMA write channel has received an error response from the AXI bus (or TRGT1 interface when the AXI Bridge is not used) while reading data from it. Each bit corresponds to a DMA channel. Bit [0].." group.long (0x60+0xC8000)++0x1F line.long 0x0 "DMA_WRITE_DONE_IMWR_LOW_OFF,DMA Write Done IMWr Address Low Register." hexmask.long 0x0 0.--31. 1. "DMA_WRITE_DONE_LOW_REG,The DMA uses this field to generate bits [31:0] of the address field for the Done IMWr TLP. Bits [1:0] must be '00' as this address must be dword aligned. Note: The access attributes of this field are as follows: - Wire: No access." line.long 0x4 "DMA_WRITE_DONE_IMWR_HIGH_OFF,DMA Write Done IMWr Interrupt Address High Register." hexmask.long 0x4 0.--31. 1. "DMA_WRITE_DONE_HIGH_REG,The DMA uses this field to generate bits [63:32] of the address field for the Done IMWr TLP. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" line.long 0x8 "DMA_WRITE_ABORT_IMWR_LOW_OFF,DMA Write Abort IMWr Address Low Register." hexmask.long 0x8 0.--31. 1. "DMA_WRITE_ABORT_LOW_REG,The DMA uses this field to generate bits [31:0] of the address field for the Abort IMWr TLP it generates. Bits [1:0] must be '00' as this address must be dword aligned. Note: The access attributes of this field are as follows: -.." line.long 0xC "DMA_WRITE_ABORT_IMWR_HIGH_OFF,DMA Write Abort IMWr Address High Register." hexmask.long 0xC 0.--31. 1. "DMA_WRITE_ABORT_HIGH_REG,The DMA uses this field to generate bits [63:32] of the address field for the Abort IMWr TLP. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" line.long 0x10 "DMA_WRITE_CH01_IMWR_DATA_OFF,DMA Write Channel 1 and 0 IMWr Data Register." hexmask.long.word 0x10 16.--31. 1. "WR_CHANNEL_1_DATA,The DMA uses this field to generate the data field for the Done or Abort IMWr TLPs it generates for write channel 1. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" hexmask.long.word 0x10 0.--15. 1. "WR_CHANNEL_0_DATA,The DMA uses this field to generate the data field for the Done or Abort IMWr TLPs it generates for write channel 0. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" line.long 0x14 "DMA_WRITE_CH23_IMWR_DATA_OFF,DMA Write Channel 3 and 2 IMWr Data Register." hexmask.long.word 0x14 16.--31. 1. "WR_CHANNEL_3_DATA,The DMA uses this field to generate the data field for the Done or Abort IMWr TLPs it generates for write channel 3. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" hexmask.long.word 0x14 0.--15. 1. "WR_CHANNEL_2_DATA,The DMA uses this field to generate the data field for the Done or Abort IMWr TLPs it generates for write channel 2. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" line.long 0x18 "DMA_WRITE_CH45_IMWR_DATA_OFF,DMA Write Channel 5 and 4 IMWr Data Register." hexmask.long.word 0x18 16.--31. 1. "WR_CHANNEL_5_DATA,The DMA uses this field to generate the data field for the Done or Abort IMWr TLPs it generates for write channel 5. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" hexmask.long.word 0x18 0.--15. 1. "WR_CHANNEL_4_DATA,The DMA uses this field to generate the data field for the Done or Abort IMWr TLPs it generates for write channel 4. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" line.long 0x1C "DMA_WRITE_CH67_IMWR_DATA_OFF,DMA Write Channel 7 and 6 IMWr Data Register." hexmask.long.word 0x1C 16.--31. 1. "WR_CHANNEL_7_DATA,The DMA uses this field to generate the data field for the Done or Abort IMWr TLPs it generates for write channel 7. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" hexmask.long.word 0x1C 0.--15. 1. "WR_CHANNEL_6_DATA,The DMA uses this field to generate the data field for the Done or Abort IMWr TLPs it generates for write channel 6. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" group.long (0x90+0xC8000)++0x3 line.long 0x0 "DMA_WRITE_LINKED_LIST_ERR_EN_OFF,DMA Write Linked List Error Enable Register. The LIE and RIE bits in the LL element enable the channel 'done' interrupts (local and remote). The LLLAIE and LLRAIE bits enable the channel 'abort' interrupts (local and.." hexmask.long.byte 0x0 24.--31. 1. "RSVDP_24,Reserved for future use." hexmask.long.byte 0x0 16.--23. 1. "WR_CHANNEL_LLLAIE,Write Channel LL Local Abort Interrupt Enable (LLLAIE). You enable the write channel local abort interrupt through this bit. The LIE and RIE bits in the LL element enable the write channel done interrupts. Each bit corresponds to a DMA.." newline hexmask.long.byte 0x0 8.--15. 1. "RSVDP_8,Reserved for future use." hexmask.long.byte 0x0 0.--7. 1. "WR_CHANNEL_LLRAIE,Write Channel LL Remote Abort Interrupt Enable (LLRAIE). You enable the write channel remote abort interrupt through this bit. The LIE and RIE bits in the LL element enable the write channel done interrupts. Each bit corresponds to a.." group.long (0xA0+0xC8000)++0x3 line.long 0x0 "DMA_READ_INT_STATUS_OFF,DMA Read Interrupt Status Register." hexmask.long.byte 0x0 24.--31. 1. "RSVDP_24,Reserved for future use." hexmask.long.byte 0x0 16.--23. 1. "RD_ABORT_INT_STATUS,Abort Interrupt Status. The DMA read channel has detected an error or you manually stopped the transfer as described in 'Stopping the DMA Transfer (Software Stop)'. Each bit corresponds to a DMA channel. Bit [0] corresponds to.." newline hexmask.long.byte 0x0 8.--15. 1. "RSVDP_8,Reserved for future use." hexmask.long.byte 0x0 0.--7. 1. "RD_DONE_INT_STATUS,Done Interrupt Status. The DMA read channel has successfully completed the DMA read transfer. Each bit corresponds to a DMA channel. Bit [0] corresponds to channel 0. - Enabling: For details see 'Interrupts and Error Handling'. -.." group.long (0xA8+0xC8000)++0x7 line.long 0x0 "DMA_READ_INT_MASK_OFF,DMA Read Interrupt Mask Register." hexmask.long.byte 0x0 24.--31. 1. "RSVDP_24,Reserved for future use." hexmask.long.byte 0x0 16.--23. 1. "RD_ABORT_INT_MASK,Abort Interrupt Mask. Prevents the Abort interrupt status field in the DMA read interrupt status register from asserting the edma_int output. Each bit corresponds to a DMA channel. Bit [0] corresponds to channel 0. Note: The access.." newline hexmask.long.byte 0x0 8.--15. 1. "RSVDP_8,Reserved for future use." hexmask.long.byte 0x0 0.--7. 1. "RD_DONE_INT_MASK,Done Interrupt Mask. Prevents the Done interrupt status field in the DMA read interrupt status register from asserting the edma_int output. Each bit corresponds to a DMA channel. Bit [0] corresponds to channel 0. Note: The access.." line.long 0x4 "DMA_READ_INT_CLEAR_OFF,DMA Read Interrupt Clear Register." hexmask.long.byte 0x4 24.--31. 1. "RSVDP_24,Reserved for future use." hexmask.long.byte 0x4 16.--23. 1. "RD_ABORT_INT_CLEAR,Abort Interrupt Clear. You must write a 1'b1 to clear the corresponding bit in the Abort interrupt status field of the DMA read interrupt status register. Each bit corresponds to a DMA channel. Bit [0] corresponds to channel 0. Note:.." newline hexmask.long.byte 0x4 8.--15. 1. "RSVDP_8,Reserved for future use." hexmask.long.byte 0x4 0.--7. 1. "RD_DONE_INT_CLEAR,Done Interrupt Clear. You must write a 1'b1 to clear the corresponding bit in the Done interrupt status field of the DMA read interrupt status register. Each bit corresponds to a DMA channel. Bit [0] corresponds to channel 0. Note:.." rgroup.long (0xB4+0xC8000)++0x7 line.long 0x0 "DMA_READ_ERR_STATUS_LOW_OFF,DMA Read Error Status Low Register." hexmask.long.byte 0x0 24.--31. 1. "RSVDP_24,Reserved for future use." hexmask.long.byte 0x0 16.--23. 1. "LINK_LIST_ELEMENT_FETCH_ERR_DETECT,Linked List Element Fetch Error Detected. - The DMA read channel has received an error response from the AXI bus while reading a linked list element from local memory. Each bit corresponds to a DMA channel. Bit [0].." newline hexmask.long.byte 0x0 8.--15. 1. "RSVDP_8,Reserved for future use." hexmask.long.byte 0x0 0.--7. 1. "APP_WR_ERR_DETECT,Application Write Error Detected. The DMA read channel has received an error response from the AXI bus (or TRGT1 interface when the AXI Bridge is not used) while writing data to it. This error is fatal. You must restart the transfer.." line.long 0x4 "DMA_READ_ERR_STATUS_HIGH_OFF,DMA Read Error Status High Register." hexmask.long.byte 0x4 24.--31. 1. "DATA_POISIONING,Data Poisoning. The DMA read channel has detected data poisoning in the completion from the remote device (in response to the MRd request). The DMA read channel will drop the completion and then be halted. The CX_FLT_MASK_UR_POIS filter.." hexmask.long.byte 0x4 16.--23. 1. "CPL_TIMEOUT,Completion Time Out. The DMA read channel has timed-out while waiting for the remote device to respond to the MRd request or a malformed CplD has been received. For more details see 'Linked List Mode'. Each bit corresponds to a DMA channel." newline hexmask.long.byte 0x4 8.--15. 1. "CPL_ABORT,Completer Abort. The DMA read channel has received a PCIe completer abort completion status from the remote device in response to the MRd request. For more details see 'Linked List Mode'. Each bit corresponds to a DMA channel. Bit [0].." hexmask.long.byte 0x4 0.--7. 1. "UNSUPPORTED_REQ,Unsupported Request. The DMA read channel has received a PCIe unsupported request completion status from the remote device in response to the MRd request. For more details see 'Linked List Mode'. Each bit corresponds to a DMA channel." group.long (0xC4+0xC8000)++0x3 line.long 0x0 "DMA_READ_LINKED_LIST_ERR_EN_OFF,DMA Read Linked List Error Enable Register. The LIE and RIE bits in the LL element enable the channel 'done' interrupts (local and remote). The LLLAIE and LLRAIE bits enable the channel 'abort' interrupts (local and remote)." hexmask.long.byte 0x0 24.--31. 1. "RSVDP_24,Reserved for future use." hexmask.long.byte 0x0 16.--23. 1. "RD_CHANNEL_LLLAIE,Read Channel LL Local Abort Interrupt Enable (LLLAIE). You enable the read channel Local Abort interrupt through this bit. The LIE and RIE bits in the LL element enable the read channel done interrupts. Each bit corresponds to a DMA.." newline hexmask.long.byte 0x0 8.--15. 1. "RSVDP_8,Reserved for future use." hexmask.long.byte 0x0 0.--7. 1. "RD_CHANNEL_LLRAIE,Read Channel LL Remote Abort Interrupt Enable (LLRAIE). You enable the read channel Remote Abort interrupt through this bit. The LIE and RIE bits in the LL element enable the read channel done interrupts. Each bit corresponds to a DMA.." group.long (0xCC+0xC8000)++0x1F line.long 0x0 "DMA_READ_DONE_IMWR_LOW_OFF,DMA Read Done IMWr Address Low Register." hexmask.long 0x0 0.--31. 1. "DMA_READ_DONE_LOW_REG,The DMA uses this field to generate bits [31:0] of the address field for the Done IMWr TLP. Bits [1:0] must be '00' as this address must be dword aligned. Note: The access attributes of this field are as follows: - Wire: No access." line.long 0x4 "DMA_READ_DONE_IMWR_HIGH_OFF,DMA Read Done IMWr Address High Register." hexmask.long 0x4 0.--31. 1. "DMA_READ_DONE_HIGH_REG,The DMA uses this field to generate bits [63:32] of the address field for the Done IMWr TLP. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" line.long 0x8 "DMA_READ_ABORT_IMWR_LOW_OFF,DMA Read Abort IMWr Address Low Register." hexmask.long 0x8 0.--31. 1. "DMA_READ_ABORT_LOW_REG,The DMA uses this field to generate bits [31:0] of the address field for the Abort IMWr TLP. Bits [1:0] must be '00' as this address must be dword aligned. Note: The access attributes of this field are as follows: - Wire: No.." line.long 0xC "DMA_READ_ABORT_IMWR_HIGH_OFF,DMA Read Abort IMWr Address High Register." hexmask.long 0xC 0.--31. 1. "DMA_READ_ABORT_HIGH_REG,The DMA uses this field to generate bits [63:32] of the address field for the Abort IMWr TLP. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" line.long 0x10 "DMA_READ_CH01_IMWR_DATA_OFF,DMA Read Channel 1 and 0 IMWr Data Register." hexmask.long.word 0x10 16.--31. 1. "RD_CHANNEL_1_DATA,The DMA uses this field to generate the data field for the Done or Abort IMWr TLPs it generates for read channel 1. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" hexmask.long.word 0x10 0.--15. 1. "RD_CHANNEL_0_DATA,The DMA uses this field to generate the data field for the Done or Abort IMWr TLPs it generates for read channel 0. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" line.long 0x14 "DMA_READ_CH23_IMWR_DATA_OFF,DMA Read Channel 3 and 2 IMWr Data Register." hexmask.long.word 0x14 16.--31. 1. "RD_CHANNEL_3_DATA,The DMA uses this field to generate the data field for the Done or Abort IMWr TLPs it generates for read channel 3. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" hexmask.long.word 0x14 0.--15. 1. "RD_CHANNEL_2_DATA,The DMA uses this field to generate the data field for the Done or Abort IMWr TLPs it generates for read channel 2. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" line.long 0x18 "DMA_READ_CH45_IMWR_DATA_OFF,DMA Read Channel 5 and 4 IMWr Data Register." hexmask.long.word 0x18 16.--31. 1. "RD_CHANNEL_5_DATA,The DMA uses this field to generate the data field for the Done or Abort IMWr TLPs it generates for read channel 5. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" hexmask.long.word 0x18 0.--15. 1. "RD_CHANNEL_4_DATA,The DMA uses this field to generate the data field for the Done or Abort IMWr TLPs it generates for read channel 4. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" line.long 0x1C "DMA_READ_CH67_IMWR_DATA_OFF,DMA Read Channel 7 and 6 IMWr Data Register." hexmask.long.word 0x1C 16.--31. 1. "RD_CHANNEL_7_DATA,The DMA uses this field to generate the data field for the Done or Abort IMWr TLPs it generates for read channel 7. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" hexmask.long.word 0x1C 0.--15. 1. "RD_CHANNEL_6_DATA,The DMA uses this field to generate the data field for the Done or Abort IMWr TLPs it generates for read channel 6. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" rgroup.long (0x108+0xC8000)++0x7 line.long 0x0 "DMA_WRITE_ENGINE_HSHAKE_CNT_LOW_OFF,DMA Write Engine Handshake Counter Channel 0/1/2/3 Register." bitfld.long 0x0 29.--31. "RSVDP_29,Reserved for future use." "0,1,2,3,4,5,6,7" hexmask.long.byte 0x0 24.--28. 1. "DMA_WRITE_ENGINE_HSHAKE_CNT_CH3,DMA handshake counter for DMA Write Engine Channel 3. If CC_DMA_HSHAKE =1 the data transfer in Linked List mode starts only when the counter is non-zero." newline bitfld.long 0x0 21.--23. "RSVDP_21,Reserved for future use." "0,1,2,3,4,5,6,7" hexmask.long.byte 0x0 16.--20. 1. "DMA_WRITE_ENGINE_HSHAKE_CNT_CH2,DMA handshake counter for DMA Write Engine Channel 2. If CC_DMA_HSHAKE =1 the data transfer in Linked List mode starts only when the counter is non-zero." newline bitfld.long 0x0 13.--15. "RSVDP_13,Reserved for future use." "0,1,2,3,4,5,6,7" hexmask.long.byte 0x0 8.--12. 1. "DMA_WRITE_ENGINE_HSHAKE_CNT_CH1,DMA handshake counter for DMA Write Engine Channel 1. If CC_DMA_HSHAKE =1 the data transfer in Linked List mode starts only when the counter is non-zero." newline bitfld.long 0x0 5.--7. "RSVDP_5,Reserved for future use." "0,1,2,3,4,5,6,7" hexmask.long.byte 0x0 0.--4. 1. "DMA_WRITE_ENGINE_HSHAKE_CNT_CH0,DMA handshake counter for DMA Write Engine Channel 0. If CC_DMA_HSHAKE =1 the data transfer in Linked List mode starts only when the counter is non-zero." line.long 0x4 "DMA_WRITE_ENGINE_HSHAKE_CNT_HIGH_OFF,DMA Write Engine Handshake Counter Channel 4/5/6/7 Register." bitfld.long 0x4 29.--31. "RSVDP_29,Reserved for future use." "0,1,2,3,4,5,6,7" hexmask.long.byte 0x4 24.--28. 1. "DMA_WRITE_ENGINE_HSHAKE_CNT_CH7,DMA handshake counter for DMA Write Engine Channel 7. If CC_DMA_HSHAKE =1 the data transfer in Linked List mode starts only when the counter is non-zero." newline bitfld.long 0x4 21.--23. "RSVDP_21,Reserved for future use." "0,1,2,3,4,5,6,7" hexmask.long.byte 0x4 16.--20. 1. "DMA_WRITE_ENGINE_HSHAKE_CNT_CH6,DMA handshake counter for DMA Write Engine Channel 6. If CC_DMA_HSHAKE =1 the data transfer in Linked List mode starts only when the counter is non-zero." newline bitfld.long 0x4 13.--15. "RSVDP_13,Reserved for future use." "0,1,2,3,4,5,6,7" hexmask.long.byte 0x4 8.--12. 1. "DMA_WRITE_ENGINE_HSHAKE_CNT_CH5,DMA handshake counter for DMA Write Engine Channel 5. If CC_DMA_HSHAKE =1 the data transfer in Linked List mode starts only when the counter is non-zero." newline bitfld.long 0x4 5.--7. "RSVDP_5,Reserved for future use." "0,1,2,3,4,5,6,7" hexmask.long.byte 0x4 0.--4. 1. "DMA_WRITE_ENGINE_HSHAKE_CNT_CH4,DMA handshake counter for DMA Write Engine Channel 4. If CC_DMA_HSHAKE =1 the data transfer in Linked List mode starts only when the counter is non-zero." rgroup.long (0x118+0xC8000)++0x7 line.long 0x0 "DMA_READ_ENGINE_HSHAKE_CNT_LOW_OFF,DMA Read Engine Handshake Counter Channel 0/1/2/3 Register." bitfld.long 0x0 29.--31. "RSVDP_29,Reserved for future use." "0,1,2,3,4,5,6,7" hexmask.long.byte 0x0 24.--28. 1. "DMA_READ_ENGINE_HSHAKE_CNT_CH3,DMA handshake counter for DMA Read Engine Channel 3. If CC_DMA_HSHAKE =1 the data transfer in Linked List mode starts only when the counter is non-zero." newline bitfld.long 0x0 21.--23. "RSVDP_21,Reserved for future use." "0,1,2,3,4,5,6,7" hexmask.long.byte 0x0 16.--20. 1. "DMA_READ_ENGINE_HSHAKE_CNT_CH2,DMA handshake counter for DMA Read Engine Channel 2. If CC_DMA_HSHAKE =1 the data transfer in Linked List mode starts only when the counter is non-zero." newline bitfld.long 0x0 13.--15. "RSVDP_13,Reserved for future use." "0,1,2,3,4,5,6,7" hexmask.long.byte 0x0 8.--12. 1. "DMA_READ_ENGINE_HSHAKE_CNT_CH1,DMA handshake counter for DMA Read Engine Channel 1. If CC_DMA_HSHAKE =1 the data transfer in Linked List mode starts only when the counter is non-zero." newline bitfld.long 0x0 5.--7. "RSVDP_5,Reserved for future use." "0,1,2,3,4,5,6,7" hexmask.long.byte 0x0 0.--4. 1. "DMA_READ_ENGINE_HSHAKE_CNT_CH0,DMA handshake counter for DMA Read Engine Channel 0. If CC_DMA_HSHAKE =1 the data transfer in Linked List mode starts only when the counter is non-zero." line.long 0x4 "DMA_READ_ENGINE_HSHAKE_CNT_HIGH_OFF,DMA Read Engine Handshake Counter Channel 4/5/6/7 Register." bitfld.long 0x4 29.--31. "RSVDP_29,Reserved for future use." "0,1,2,3,4,5,6,7" hexmask.long.byte 0x4 24.--28. 1. "DMA_READ_ENGINE_HSHAKE_CNT_CH7,DMA handshake counter for DMA Read Engine Channel 7. If CC_DMA_HSHAKE =1 the data transfer in Linked List mode starts only when the counter is non-zero." newline bitfld.long 0x4 21.--23. "RSVDP_21,Reserved for future use." "0,1,2,3,4,5,6,7" hexmask.long.byte 0x4 16.--20. 1. "DMA_READ_ENGINE_HSHAKE_CNT_CH6,DMA handshake counter for DMA Read Engine Channel 6. If CC_DMA_HSHAKE =1 the data transfer in Linked List mode starts only when the counter is non-zero." newline bitfld.long 0x4 13.--15. "RSVDP_13,Reserved for future use." "0,1,2,3,4,5,6,7" hexmask.long.byte 0x4 8.--12. 1. "DMA_READ_ENGINE_HSHAKE_CNT_CH5,DMA handshake counter for DMA Read Engine Channel 5. If CC_DMA_HSHAKE =1 the data transfer in Linked List mode starts only when the counter is non-zero." newline bitfld.long 0x4 5.--7. "RSVDP_5,Reserved for future use." "0,1,2,3,4,5,6,7" hexmask.long.byte 0x4 0.--4. 1. "DMA_READ_ENGINE_HSHAKE_CNT_CH4,DMA handshake counter for DMA Read Engine Channel 4. If CC_DMA_HSHAKE =1 the data transfer in Linked List mode starts only when the counter is non-zero." repeat 8. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 )(list 0x0 0x200 0x400 0x600 0x800 0xA00 0xC00 0xE00 ) group.long ($2+0x200+0xC8000)++0x3 line.long 0x0 "DMA_CH_CONTROL1_OFF_WRCH_$1,DMA Write Channel Control 1 Register." bitfld.long 0x0 30.--31. "DMA_AT,Address Translation TLP Header Bit (AT) The DMA uses this TLP header field when generating MRd/MWr (not IMWr) TLPs. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" "0,1,2,3" bitfld.long 0x0 27.--29. "DMA_TC,Traffic Class TLP Header Bit (TC) The DMA uses this TLP header field when generating MRd/MWr (not IMWr) TLPs. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 26. "DMA_RESERVED5,Reserved. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" "0,1" bitfld.long 0x0 25. "DMA_RO,Relaxed Ordering TLP Header Bit (RO) The DMA uses this TLP header field when generating MRd/MWr (not IMWr) TLPs. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" "0,1" newline bitfld.long 0x0 24. "DMA_NS_SRC,Source No Snoop TLP Header Bit (DMA_NS_SRC). The DMA uses this TLP header field when generating MRd (SAR addressing space) (not IMWr) TLPs. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" "0,1" bitfld.long 0x0 23. "DMA_NS_DST,Destination No Snoop TLP Header Bit (DMA_NS_DST). The DMA uses this TLP header field when generating MWr (DAR addressing space) (not IMWr) TLPs. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" "0,1" newline bitfld.long 0x0 22. "DMA_MEM_TYPE,Master AXI ACE-Lite Cache Coherency Control. This field sets the DMA channel memory type of the address space of the data transfer as follows: - 0x0:peripheral type - 0x1:memory type For more details see 'ACE-Lite Features and Limitations'.." "peripheral type,memory type" hexmask.long.byte 0x0 17.--21. 1. "DMA_RESERVED2,Reserved. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" newline hexmask.long.byte 0x0 12.--16. 1. "DMA_FUNC_NUM,Function Number (FN). The controller uses this field when generating the requester ID for the MRd/MWr DMA TLP. When you have enabled SR-IOV then this field is ignored if you have set the VFE field in the 'DMA Write Channel Control 2.." bitfld.long 0x0 10.--11. "DMA_RESERVED1,Reserved. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" "0,1,2,3" newline bitfld.long 0x0 9. "LLE,Linked List Enable (LLE). - 0: Disable linked list operation - 1: Enable linked list operation Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" "Disable linked list operation,Enable linked list operation" bitfld.long 0x0 8. "CCS,Consumer Cycle State (CCS). Used in linked list mode only. It is used to synchronize the producer (software) and the consumer (DMA). For more details see 'PCS-CCS-CB-TCB Producer-Consumer Synchronization'. You must initialize this bit. The DMA.." "0,1" newline bitfld.long 0x0 7. "DMA_RESERVED0,Reserved. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" "0,1" bitfld.long 0x0 5.--6. "CS,Channel Status (CS). The channel status bits identify the current operational state of the DMA channel. The operation state encoding for each DMA channel is a s follows: - 00: Reserved - 01: Running. This channel is active and transferring data. - 10:.." "Reserved,Running,?,?" newline bitfld.long 0x0 4. "RIE,Remote Interrupt Enable (RIE). You must set this bit to enable the generation of the Done or Abort Remote interrupts. For more details see 'Interrupts and Error Handling'. In LL mode the DMA overwrites this with the RIE of the LL element. The RIE.." "0,1" bitfld.long 0x0 3. "LIE,Local Interrupt Enable (LIE). You must set this bit to enable the generation of the Done or Abort Local interrupts. For more details see 'Interrupts and Error Handling'. In LL mode the DMA overwrites this with the LIE of the LL element. The LIE bit.." "0,1" newline bitfld.long 0x0 2. "LLP,Load Link Pointer (LLP). Used in linked list mode only. Indicates that this linked list element is a link element and its LL element pointer dwords are pointing to the next (non-contiguous) element. The DMA loads this field with the LLP of the.." "0,1" bitfld.long 0x0 1. "TCB,Toggle Cycle Bit (TCB). Indicates to the DMA to toggle its interpretation of the CB. Used in linked list mode only. It is used to synchronize the producer (software) and the consumer (DMA). For more details see 'PCS-CCS-CB-TCB Producer-Consumer.." "0,1" newline bitfld.long 0x0 0. "CB,Cycle Bit (CB). Used in linked list mode only. It is used to synchronize the producer (software) and the consumer (DMA). For more details see 'PCS-CCS-CB-TCB Producer-Consumer Synchronization'. The DMA loads this field with the CB of the linked list.." "0,1" repeat.end repeat 8. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 )(list 0x0 0x200 0x400 0x600 0x800 0xA00 0xC00 0xE00 ) group.long ($2+0x208+0xC8000)++0x3 line.long 0x0 "DMA_TRANSFER_SIZE_OFF_WRCH_$1,DMA Write Transfer Size Register." hexmask.long 0x0 0.--31. 1. "DMA_TRANSFER_SIZE,DMA Transfer Size. You program this register with the size of the DMA transfer. The maximum DMA transfer size is 4Gbytes. The minimum transfer size is one byte (0x1). This field is automatically decremented by the DMA as the DMA write.." repeat.end repeat 8. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 )(list 0x0 0x200 0x400 0x600 0x800 0xA00 0xC00 0xE00 ) group.long ($2+0x20C+0xC8000)++0x3 line.long 0x0 "DMA_SAR_LOW_OFF_WRCH_$1,DMA Write SAR Low Register." hexmask.long 0x0 0.--31. 1. "SRC_ADDR_REG_LOW,Source Address Register (Lower 32 bits). Indicates the next address to be read from. The DMA increments the SAR as the DMA transfer progresses. In LL mode the DMA overwrites this with the corresponding dword of the LL element. - DMA.." repeat.end repeat 8. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 )(list 0x0 0x200 0x400 0x600 0x800 0xA00 0xC00 0xE00 ) group.long ($2+0x210+0xC8000)++0x3 line.long 0x0 "DMA_SAR_HIGH_OFF_WRCH_$1,DMA Write SAR High Register." hexmask.long 0x0 0.--31. 1. "SRC_ADDR_REG_HIGH,Source Address Register (Higher 32 bits). In LL mode the DMA overwrites this with the corresponding dword of the LL element. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" repeat.end repeat 8. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 )(list 0x0 0x200 0x400 0x600 0x800 0xA00 0xC00 0xE00 ) group.long ($2+0x214+0xC8000)++0x3 line.long 0x0 "DMA_DAR_LOW_OFF_WRCH_$1,DMA Write DAR Low Register." hexmask.long 0x0 0.--31. 1. "DST_ADDR_REG_LOW,Destination Address Register (Lower 32 bits). Indicates the next address to be written to. The DMA increments the DAR as the DMA transfer progresses. In LL mode the DMA overwrites this with the corresponding dword of the LL element. -.." repeat.end repeat 8. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 )(list 0x0 0x200 0x400 0x600 0x800 0xA00 0xC00 0xE00 ) group.long ($2+0x218+0xC8000)++0x3 line.long 0x0 "DMA_DAR_HIGH_OFF_WRCH_$1,DMA Write DAR High Register." hexmask.long 0x0 0.--31. 1. "DST_ADDR_REG_HIGH,Destination Address Register (Higher 32 bits). In LL mode the DMA overwrites this with the corresponding dword of the LL element. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" repeat.end repeat 8. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 )(list 0x0 0x200 0x400 0x600 0x800 0xA00 0xC00 0xE00 ) group.long ($2+0x21C+0xC8000)++0x3 line.long 0x0 "DMA_LLP_LOW_OFF_WRCH_$1,DMA Write Linked List Pointer Low Register." hexmask.long 0x0 0.--31. 1. "LLP_LOW,Lower bits of the address of the linked list transfer list in local memory. Used in linked list mode only. Updated by the DMA to point to the next element in the transfer list after the previous element is consumed. - When the current element is.." repeat.end repeat 8. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 )(list 0x0 0x200 0x400 0x600 0x800 0xA00 0xC00 0xE00 ) group.long ($2+0x220+0xC8000)++0x3 line.long 0x0 "DMA_LLP_HIGH_OFF_WRCH_$1,DMA Write Linked List Pointer High Register." hexmask.long 0x0 0.--31. 1. "LLP_HIGH,Upper 32 bits of the address of the linked list transfer list in local memory. Used in linked list mode only. Updated by the DMA to point to the next element in the transfer list as elements are consumed. Note: The access attributes of this.." repeat.end repeat 8. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 )(list 0x0 0x200 0x400 0x600 0x800 0xA00 0xC00 0xE00 ) group.long ($2+0x300+0xC8000)++0x3 line.long 0x0 "DMA_CH_CONTROL1_OFF_RDCH_$1,DMA Read Channel Control 1 Register." bitfld.long 0x0 30.--31. "DMA_AT,Address Translation TLP Header Bit (AT) The DMA uses this TLP header field when generating MRd/MWr (not IMWr) TLPs. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" "0,1,2,3" bitfld.long 0x0 27.--29. "DMA_TC,Traffic Class TLP Header Bit (TC) The DMA uses this TLP header field when generating MRd/MWr (not IMWr) TLPs. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 26. "DMA_RESERVED5,Reserved. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" "0,1" bitfld.long 0x0 25. "DMA_RO,Relaxed Ordering TLP Header Bit (RO) The DMA uses this TLP header field when generating MRd/MWr (not IMWr) TLPs. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" "0,1" newline bitfld.long 0x0 24. "DMA_NS_SRC,Source No Snoop TLP Header Bit (DMA_NS_SRC). The DMA uses this TLP header field when generating MRd (SAR addressing space) (not IMWr) TLPs. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" "0,1" bitfld.long 0x0 23. "DMA_NS_DST,Destination No Snoop TLP Header Bit (DMA_NS_DST). The DMA uses this TLP header field when generating MWr (DAR addressing space) (not IMWr) TLPs. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" "0,1" newline bitfld.long 0x0 22. "DMA_MEM_TYPE,Master AXI ACE-Lite Cache Coherency Control. This field sets the DMA channel memory type of the address space of the data transfer as follows: - 0x0:peripheral type - 0x1:memory type For more details see 'ACE-Lite Features and Limitations'.." "peripheral type,memory type" hexmask.long.byte 0x0 17.--21. 1. "DMA_RESERVED2,Reserved. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" newline hexmask.long.byte 0x0 12.--16. 1. "DMA_FUNC_NUM,Function Number (FN). The controller uses this field when generating the requester ID for the MRd/MWr DMA TLP. When you have enabled SR-IOV then this field is ignored if you have set the VFE field in the 'DMA Read Channel Control 2.." bitfld.long 0x0 10.--11. "DMA_RESERVED1,Reserved. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" "0,1,2,3" newline bitfld.long 0x0 9. "LLE,Linked List Enable (LLE). - 0: Disable linked list operation - 1: Enable linked list operation Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" "Disable linked list operation,Enable linked list operation" bitfld.long 0x0 8. "CCS,Consumer Cycle State (CCS). Used in linked list mode only. It is used to synchronize the producer (software) and the consumer (DMA). For more details see 'PCS-CCS-CB-TCB Producer-Consumer Synchronization'. You must initialize this bit. The DMA.." "0,1" newline bitfld.long 0x0 7. "DMA_RESERVED0,Reserved. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" "0,1" bitfld.long 0x0 5.--6. "CS,Channel Status (CS). The channel status bits identify the current operational state of the DMA channel. The operation state encoding for each DMA channel is a s follows: - 00: Reserved - 01: Running. This channel is active and transferring data. - 10:.." "Reserved,Running,?,?" newline bitfld.long 0x0 4. "RIE,Remote Interrupt Enable (RIE). You must set this bit to enable the generation of the Done or Abort Remote interrupts. For more details see 'Interrupts and Error Handling'. In LL mode the DMA overwrites this with the RIE of the LL element. The RIE.." "0,1" bitfld.long 0x0 3. "LIE,Local Interrupt Enable (LIE). You must set this bit to enable the generation of the Done or Abort Local interrupts. For more details see 'Interrupts and Error Handling'. In LL mode the DMA overwrites this with the LIE of the LL element. The LIE bit.." "0,1" newline bitfld.long 0x0 2. "LLP,Load Link Pointer (LLP). Used in linked list mode only. Indicates that this linked list element is a link element and its LL element pointer dwords are pointing to the next (non-contiguous) element. The DMA loads this field with the LLP of the.." "0,1" bitfld.long 0x0 1. "TCB,Toggle Cycle Bit (TCB). Indicates to the DMA to toggle its interpretation of the CB. Used in linked list mode only. It is used to synchronize the producer (software) and the consumer (DMA). For more details see 'PCS-CCS-CB-TCB Producer-Consumer.." "0,1" newline bitfld.long 0x0 0. "CB,Cycle Bit (CB). Used in linked list mode only. It is used to synchronize the producer (software) and the consumer (DMA). For more details see 'PCS-CCS-CB-TCB Producer-Consumer Synchronization'. The DMA loads this field with the CB of the linked list.." "0,1" repeat.end repeat 8. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 )(list 0x0 0x200 0x400 0x600 0x800 0xA00 0xC00 0xE00 ) group.long ($2+0x308+0xC8000)++0x3 line.long 0x0 "DMA_TRANSFER_SIZE_OFF_RDCH_$1,DMA Read Transfer Size Register." hexmask.long 0x0 0.--31. 1. "DMA_TRANSFER_SIZE,DMA Transfer Size. You program this register with the size of the DMA transfer. The maximum DMA transfer size is 4Gbytes. The minimum transfer size is one byte (0x1). This field is automatically decremented by the DMA as the DMA read.." repeat.end repeat 8. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 )(list 0x0 0x200 0x400 0x600 0x800 0xA00 0xC00 0xE00 ) group.long ($2+0x30C+0xC8000)++0x3 line.long 0x0 "DMA_SAR_LOW_OFF_RDCH_$1,DMA Read SAR Low Register." hexmask.long 0x0 0.--31. 1. "SRC_ADDR_REG_LOW,Source Address Register (Lower 32 bits). Indicates the next address to be read from. The DMA increments the SAR as the DMA transfer progresses. In LL mode the DMA overwrites this with the corresponding dword of the LL element. - DMA.." repeat.end repeat 8. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 )(list 0x0 0x200 0x400 0x600 0x800 0xA00 0xC00 0xE00 ) group.long ($2+0x310+0xC8000)++0x3 line.long 0x0 "DMA_SAR_HIGH_OFF_RDCH_$1,DMA Read SAR High Register." hexmask.long 0x0 0.--31. 1. "SRC_ADDR_REG_HIGH,Source Address Register (Higher 32 bits). In LL mode the DMA overwrites this with the corresponding dword of the LL element. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" repeat.end repeat 8. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 )(list 0x0 0x200 0x400 0x600 0x800 0xA00 0xC00 0xE00 ) group.long ($2+0x314+0xC8000)++0x3 line.long 0x0 "DMA_DAR_LOW_OFF_RDCH_$1,DMA Read DAR Low Register." hexmask.long 0x0 0.--31. 1. "DST_ADDR_REG_LOW,Destination Address Register (Lower 32 bits). Indicates the next address to be written to. The DMA increments the DAR as the DMA transfer progresses. In LL mode the DMA overwrites this with the corresponding dword of the LL element. -.." repeat.end repeat 8. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 )(list 0x0 0x200 0x400 0x600 0x800 0xA00 0xC00 0xE00 ) group.long ($2+0x318+0xC8000)++0x3 line.long 0x0 "DMA_DAR_HIGH_OFF_RDCH_$1,DMA Read DAR High Register." hexmask.long 0x0 0.--31. 1. "DST_ADDR_REG_HIGH,Destination Address Register (Higher 32 bits). In LL mode the DMA overwrites this with the corresponding dword of the LL element. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" repeat.end repeat 8. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 )(list 0x0 0x200 0x400 0x600 0x800 0xA00 0xC00 0xE00 ) group.long ($2+0x31C+0xC8000)++0x3 line.long 0x0 "DMA_LLP_LOW_OFF_RDCH_$1,DMA Read Linked List Pointer Low Register." hexmask.long 0x0 0.--31. 1. "LLP_LOW,Lower bits of the address of the linked list transfer list in local memory. Used in linked list mode only. Updated by the DMA to point to the next element in the transfer list after the previous element is consumed. - When the current element is.." repeat.end repeat 8. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 )(list 0x0 0x200 0x400 0x600 0x800 0xA00 0xC00 0xE00 ) group.long ($2+0x320+0xC8000)++0x3 line.long 0x0 "DMA_LLP_HIGH_OFF_RDCH_$1,DMA Read Linked List Pointer High Register." hexmask.long 0x0 0.--31. 1. "LLP_HIGH,Upper 32 bits of the address of the linked list transfer list in local memory. Used in linked list mode only. Updated by the DMA to point to the next element in the transfer list as elements are consumed. Note: The access attributes of this.." repeat.end tree.end tree "PF0_ATU_CAP (ATU Por Logic Structure)" repeat 8. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 )(list 0x0 0x200 0x400 0x600 0x800 0xA00 0xC00 0xE00 ) group.long ($2+0xC0000)++0x3 line.long 0x0 "IATU_REGION_CTRL_1_OFF_OUTBOUND_$1,iATU Region Control 1 Register." bitfld.long 0x0 20. "CTRL_1_FUNC_NUM,Function Number. - When the address of an outbound TLP is matched to this region and the FUNC_BYPASS field in the 'iATU Control 2 Register' is '0' then the function number used in generating the function part of the requester ID (RID).." "0,1" newline bitfld.long 0x0 13. "INCREASE_REGION_SIZE,Increase the maximum ATU Region size. When set the maximum ATU Region size is determined by CX_ATU_MAX_REGION_SIZE. When clear the maximum ATU Region size is 4 GB (default). Note: This register field is sticky." "0,1" newline bitfld.long 0x0 9.--10. "ATTR,When the address of an outbound TLP is matched to this region then the ATTR field of the TLP is changed to the value in this register. Note: This register field is sticky." "0,1,2,3" newline bitfld.long 0x0 8. "TD,This is a reserved field. Do not use. Note: This register field is sticky." "0,1" newline bitfld.long 0x0 5.--7. "TC,When the address of an outbound TLP is matched to this region then the TC field of the TLP is changed to the value in this register. Note: This register field is sticky." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x0 0.--4. 1. "TYPE,When the address of an outbound TLP is matched to this region then the TYPE field of the TLP is changed to the value in this register. Note: This register field is sticky." repeat.end repeat 8. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 )(list 0x0 0x200 0x400 0x600 0x800 0xA00 0xC00 0xE00 ) group.long ($2+0x4+0xC0000)++0x3 line.long 0x0 "IATU_REGION_CTRL_2_OFF_OUTBOUND_$1,iATU Region Control 2 Register." bitfld.long 0x0 31. "REGION_EN,Region Enable. This bit must be set to '1' for address translation to take place. Note: This register field is sticky." "0,1" newline bitfld.long 0x0 29. "INVERT_MODE,Invert Mode. When set the address matching region is inverted. Therefore an address match occurs when the untranslated address is in the region outside the defined range (Base Address to Limit Address). Note: This register field is sticky." "0,1" newline bitfld.long 0x0 28. "CFG_SHIFT_MODE,CFG Shift Mode. The iATU uses bits [27:12] of the untranslated address (on the XALI0/1/2 interface or AXI slave interface address) to form the BDF number of the outgoing CFG TLP. This supports the Enhanced Configuration Address Mapping.." "0,1" newline bitfld.long 0x0 27. "DMA_BYPASS,DMA Bypass Mode. Allows request TLPs which are initiated by the DMA controller to pass through the iATU untranslated. Note: This field is reserved for the SW product. You must set it to '0'. Note: This register field is sticky." "0,1" newline bitfld.long 0x0 23. "HEADER_SUBSTITUTE_EN,Header Substitute Enable. When enabled and region address is matched the iATU fully substitutes bytes 8-11 (for 3 DWORD header) or bytes 12-15 (for 4 DWORD header) of the outbound TLP header with the contents of the LWR_TARGET_RW.." "LWR_TARGET_RW in the..,LWR_TARGET_RW in the.." newline bitfld.long 0x0 22. "INHIBIT_PAYLOAD,Inhibit TLP Payload Data for TLP's in Matched Region; assign iATU region to be TLP without data. When enabled and region address is matched the iATU marks all TLPs as having no payload data by forcing the TLP header Fmt[1] bit =0.." "Fmt[1] =0/1 so that TLPs with or without data..,Fmt[1] =0 so that only TLP type without data is.." newline bitfld.long 0x0 21. "TLP_HEADER_FIELDS_BYPASS,TLP Header Fields Translation Bypass. In this mode header fields of the translated TLP is taken from your application transmit interface or if AMBA is configured from the AMBA sideband bus (slv_awmisc_info) and not from the.." "0,1" newline bitfld.long 0x0 20. "SNP,Serialize Non-Posted Requests. In this mode when the AXI Bridge is populated same AXI ID Non-Posted Read/Write Requests are transmitted on the wire if there are no other same ID Non-Posted Requests outstanding. Note: This register field is sticky." "0,1" newline bitfld.long 0x0 19. "FUNC_BYPASS,Function Number Translation Bypass. In this mode the function number of the translated TLP is taken from your application transmit interface and not from the CTRL_1_FUNC_NUM field of the 'iATU Control 1 Register' or the VF_NUMBER field of.." "0,1" newline bitfld.long 0x0 16. "TAG_SUBSTITUTE_EN,TAG Substitute Enable. When enabled and region address is matched the iATU substitutes the TAG field of the outbound TLP header with the contents of the TAG field in this register. The expected usage scenario is translation from AXI.." "0,1" newline hexmask.long.byte 0x0 8.--15. 1. "TAG,TAG. The substituted TAG field (byte 6) in the outgoing TLP header when TAG_SUBSTITUTE_EN is set. Note: This register field is sticky." newline hexmask.long.byte 0x0 0.--7. 1. "MSG_CODE,MSG TLPs (Message Code). When the address of an outbound TLP is matched to this region and the translated TLP TYPE field is Msg or MsgD; then the message field of the TLP is changed to the value in this register. Memory TLPs: (ST;Steering Tag)." repeat.end repeat 8. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 )(list 0x0 0x200 0x400 0x600 0x800 0xA00 0xC00 0xE00 ) group.long ($2+0x8+0xC0000)++0x3 line.long 0x0 "IATU_LWR_BASE_ADDR_OFF_OUTBOUND_$1,iATU Lower Base Address Register. The CX_ATU_MIN_REGION_SIZE configuration parameter (Value Range: 4 kB. 8 kB. 16 kB. 32 kB. 64 kB defaults to 64 kB) specifies the minimum size of an address translation region. For.." hexmask.long.tbyte 0x0 12.--31. 1. "LWR_BASE_RW,Forms bits [31:n] of the start address of the address region to be translated. n is log2(CX_ATU_MIN_REGION_SIZE) Note: This register field is sticky." newline hexmask.long.word 0x0 0.--11. 1. "LWR_BASE_HW,Forms bits [n-1:0] of the start address of the address region to be translated. The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary so these bits are always 0. A write to this location is ignored by the PCIe controller." repeat.end repeat 8. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 )(list 0x0 0x200 0x400 0x600 0x800 0xA00 0xC00 0xE00 ) group.long ($2+0xC+0xC0000)++0x3 line.long 0x0 "IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_$1,iATU Upper Base Address Register." hexmask.long 0x0 0.--31. 1. "UPPER_BASE_RW,Forms bits [63:32] of the start (and end) address of the address region to be translated. In systems with a 32-bit address space this register is not used and therefore writing to this register has no effect. Note: This register field is.." repeat.end repeat 8. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 )(list 0x0 0x200 0x400 0x600 0x800 0xA00 0xC00 0xE00 ) group.long ($2+0x10+0xC0000)++0x3 line.long 0x0 "IATU_LIMIT_ADDR_OFF_OUTBOUND_$1,iATU Limit Address Register." hexmask.long.tbyte 0x0 12.--31. 1. "LIMIT_ADDR_RW,Forms upper bits of the end address of the address region to be translated. Note: This register field is sticky." newline hexmask.long.word 0x0 0.--11. 1. "LIMIT_ADDR_HW,Forms lower bits of the end address of the address region to be translated. The end address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary so these bits are always all ones. A write to this location is ignored by the PCIe.." repeat.end repeat 8. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 )(list 0x0 0x200 0x400 0x600 0x800 0xA00 0xC00 0xE00 ) group.long ($2+0x14+0xC0000)++0x3 line.long 0x0 "IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_$1,iATU Lower Target Address Register." hexmask.long 0x0 0.--31. 1. "LWR_TARGET_RW_OUTBOUND,When HEADER_SUBSTITUTE_EN in IATU_REGION_CTRL_2_OFF_OUTBOUND_ is '0' (normal operation): - LWR_TARGET_RW[31:n] forms MSB's of the Lower Target part of the new address of the translated region; - LWR_TARGET_RW[n-1:0] are not used." repeat.end repeat 8. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 )(list 0x0 0x200 0x400 0x600 0x800 0xA00 0xC00 0xE00 ) group.long ($2+0x18+0xC0000)++0x3 line.long 0x0 "IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_$1,iATU Upper Target Address Register." hexmask.long 0x0 0.--31. 1. "UPPER_TARGET_RW,Forms bits [63:32] of the start address (Upper Target part) of the new address of the translated region. Note: This register field is sticky." repeat.end repeat 8. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 )(list 0x0 0x200 0x400 0x600 0x800 0xA00 0xC00 0xE00 ) group.long ($2+0x1C+0xC0000)++0x3 line.long 0x0 "IATU_REGION_CTRL_3_OFF_OUTBOUND_$1,iATU Region Control 3 Register." bitfld.long 0x0 31. "VF_ACTIVE,Virtual Function Active. Indicates that all of the outbound accesses are from virtual functions. For more details see VF_ACTIVE field. Note: This register field is sticky." "0,1" newline hexmask.long 0x0 3.--30. 1. "RSVDP_VF_NUMBER,Reserved for future use." newline bitfld.long 0x0 0.--2. "VF_NUMBER,Virtual Function Number. When the address of an outbound TLP is matched to this region and the FUNC_BYPASS field in the 'iATU Control 2 Register' is '0' then this field used in generating the Function part of the requester ID (RID) field of.." "0,1,2,3,4,5,6,7" repeat.end repeat 8. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 )(list 0x0 0x200 0x400 0x600 0x800 0xA00 0xC00 0xE00 ) group.long ($2+0x100+0xC0000)++0x3 line.long 0x0 "IATU_REGION_CTRL_1_OFF_INBOUND_$1,iATU Region Control 1 Register." bitfld.long 0x0 20. "CTRL_1_FUNC_NUM,Function Number. - MEM-I/O: When the Address and BAR matching logic in the controller indicate that a MEM-I/O transaction matches a BAR in the function corresponding to this value then address translation proceeds. This check is only.." "?,When the destination function number as.." newline bitfld.long 0x0 13. "INCREASE_REGION_SIZE,Increase the maximum ATU Region size. When set the maximum ATU Region size is determined by CX_ATU_MAX_REGION_SIZE. When clear the maximum ATU Region size is 4 GB (default). Note: This register field is sticky." "0,1" newline bitfld.long 0x0 9.--10. "ATTR,When the ATTR field of an inbound TLP is matched to this value then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the 'ATTR Match Enable' bit of the 'iATU Control 2 Register' is.." "0,1,2,3" newline bitfld.long 0x0 8. "TD,When the TD field of an inbound TLP is matched to this value then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the 'TD Match Enable' bit of the 'iATU Control 2 Register' is set." "0,1" newline bitfld.long 0x0 5.--7. "TC,When the TC field of an inbound TLP is matched to this value then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the 'TC Match Enable' bit of the 'iATU Control 2 Register' is set." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x0 0.--4. 1. "TYPE,When the TYPE field of an inbound TLP is matched to this value then address translation proceeds (when all other enabled field-matches are successful). Note: This register field is sticky." repeat.end repeat 8. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 )(list 0x0 0x200 0x400 0x600 0x800 0xA00 0xC00 0xE00 ) group.long ($2+0x104+0xC0000)++0x3 line.long 0x0 "IATU_REGION_CTRL_2_OFF_INBOUND_$1,iATU Region Control 2 Register." bitfld.long 0x0 31. "REGION_EN,Region Enable. This bit must be set to '1' for address translation to take place. Note: This register field is sticky." "0,1" newline bitfld.long 0x0 30. "MATCH_MODE,Match Mode. Determines Inbound matching mode for TLPs. The mode depends on the type of TLP that is received as follows: For MEM-I/O TLPs this field is interpreted as follows: - 0: Address Match Mode. The iATU operates using addresses as in.." "Address Match Mode,Vendor ID Match Mode" newline bitfld.long 0x0 29. "INVERT_MODE,Invert Mode. When set the address matching region is inverted. Therefore an address match occurs when the untranslated address is in the region outside the defined range (Base Address to Limit Address). Note: This register field is sticky." "0,1" newline bitfld.long 0x0 28. "CFG_SHIFT_MODE,CFG Shift Mode. This is useful for CFG transactions where the PCIe configuration mechanism maps bits [27:12] of the address to the bus/device and function number. This allows a CFG configuration space to be located in any 256MB window of.." "0,1" newline bitfld.long 0x0 27. "FUZZY_TYPE_MATCH_CODE,Fuzzy Type Match Mode. When enabled the iATU relaxes the matching of the TLP TYPE field against the expected TYPE field so that - CfgRd0 and CfgRd1 TLPs are seen as identical. Similarly with CfgWr0 and CfgWr1. - MWr MRd and MRdLk.." "0,1" newline bitfld.long 0x0 26. "VFBAR_MATCH_MODE_EN,VF BAR Match Mode enable. When set Virtual Function BAR matching is used which allows all VFs in a PF which match a BAR to be matched with a single ATU region. Note: This register field is sticky." "0,1" newline bitfld.long 0x0 24.--25. "RESPONSE_CODE,Response Code. Defines the type of response to give for accesses matching this region. This overrides the normal RADM filter response. Note that this feature is not available for any region where Single Address Location Translate is.." "Normal RADM filter response is used,Unsupported request,?,?" newline bitfld.long 0x0 23. "SINGLE_ADDR_LOC_TRANS_EN,Single Address Location Translate Enable. When enabled Rx TLPs can be translated to a single address location as determined by the target address register of the iATU region. The main usage scenario is translation of Messages.." "0,1" newline bitfld.long 0x0 21. "MSG_CODE_MATCH_EN,Message Code Match Enable (Msg TLPS). Ensures that a successful message Code TLP field comparison match (see Message Code field of the 'iATU Control 2 Register') occurs (in MSG transactions) for address translation to proceed. ST Match.." "0,1" newline bitfld.long 0x0 20. "VF_MATCH_EN,Virtual Function Number Match Enable. Ensures that a successful Virtual Function Number TLP field comparison match (see Virtual Function Number field of the 'iATU Control 3 Register') occurs (in MEM-I/O transactions) for address translation.." "0,1" newline bitfld.long 0x0 19. "FUNC_NUM_MATCH_EN,Function Number Match Enable. Ensures that a successful Function Number TLP field comparison match (see Function Number field of the 'iATU Control 1 Register') occurs (in MEM-I/O and CFG0/CFG1 transactions) for address translation to.." "0,1" newline bitfld.long 0x0 16. "ATTR_MATCH_EN,ATTR Match Enable. Ensures that a successful ATTR TLP field comparison match (see ATTR field of the 'iATU Control 1 Register') occurs for address translation to proceed. Note: This register field is sticky." "0,1" newline bitfld.long 0x0 15. "TD_MATCH_EN,TD Match Enable. Ensures that a successful TD TLP field comparison match (see TD field of the 'iATU Control 1 Register') occurs for address translation to proceed. Note: This register field is sticky." "0,1" newline bitfld.long 0x0 14. "TC_MATCH_EN,TC Match Enable. Ensures that a successful TC TLP field comparison match (see TC field of the 'iATU Control 1 Register') occurs for address translation to proceed. Note: This register field is sticky." "0,1" newline bitfld.long 0x0 13. "MSG_TYPE_MATCH_MODE,Message Type Match Mode. When enabled and if single address location translate enable is set then inbound TLPs of type MSG/MSGd which match the type field of the iatu_region_ctrl_1_OFF_inbound register (=>TYPE[4:3]=2'b10) will be.." "0,1" newline bitfld.long 0x0 8.--10. "BAR_NUM,BAR Number. When the BAR number of an inbound MEM or IO TLP ' that is matched by the normal internal BAR address matching mechanism ' is the same as this field address translation proceeds (when all other enabled field-matches are successful)." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x0 0.--7. 1. "MSG_CODE,MSG TLPs: (Message Code). When the TYPE field of an inbound Msg/MsgD TLP is matched to this value then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the 'Message Code Match.." repeat.end repeat 8. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 )(list 0x0 0x200 0x400 0x600 0x800 0xA00 0xC00 0xE00 ) group.long ($2+0x108+0xC0000)++0x3 line.long 0x0 "IATU_LWR_BASE_ADDR_OFF_INBOUND_$1,iATU Lower Base Address Register. The CX_ATU_MIN_REGION_SIZE configuration parameter (Value Range: 4 kB. 8 kB. 16 kB. 32 kB. 64 kB defaults to 64 kB) specifies the minimum size of an address translation region. For.." hexmask.long.tbyte 0x0 12.--31. 1. "LWR_BASE_RW,Forms bits [31:n] of the start address of the address region to be translated. n is log2(CX_ATU_MIN_REGION_SIZE) Note: This register field is sticky." newline hexmask.long.word 0x0 0.--11. 1. "LWR_BASE_HW,Forms bits [n-1:0] of the start address of the address region to be translated. The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary so these bits are always 0. A write to this location is ignored by the PCIe controller." repeat.end repeat 8. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 )(list 0x0 0x200 0x400 0x600 0x800 0xA00 0xC00 0xE00 ) group.long ($2+0x10C+0xC0000)++0x3 line.long 0x0 "IATU_UPPER_BASE_ADDR_OFF_INBOUND_$1,iATU Upper Base Address Register." hexmask.long 0x0 0.--31. 1. "UPPER_BASE_RW,Forms bits [63:32] of the start (and end) address of the address region to be translated. Note: This register field is sticky." repeat.end repeat 8. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 )(list 0x0 0x200 0x400 0x600 0x800 0xA00 0xC00 0xE00 ) group.long ($2+0x110+0xC0000)++0x3 line.long 0x0 "IATU_LIMIT_ADDR_OFF_INBOUND_$1,iATU Limit Address Register." hexmask.long.tbyte 0x0 12.--31. 1. "LIMIT_ADDR_RW,Forms upper bits of the end address of the address region to be translated. Note: This register field is sticky." newline hexmask.long.word 0x0 0.--11. 1. "LIMIT_ADDR_HW,Forms lower bits of the end address of the address region to be translated. The end address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary so these bits are always all ones. A write to this location is ignored by the PCIe.." repeat.end repeat 8. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 )(list 0x0 0x200 0x400 0x600 0x800 0xA00 0xC00 0xE00 ) group.long ($2+0x114+0xC0000)++0x3 line.long 0x0 "IATU_LWR_TARGET_ADDR_OFF_INBOUND_$1,iATU Lower Target Address Register." hexmask.long.tbyte 0x0 12.--31. 1. "LWR_TARGET_RW,Forms MSB's of the Lower Target part of the new address of the translated region. These bits are always '0'. - Field size depends on log2(CX_ATU_MIN_REGION_SIZE) in address match mode. - Field size depends on log2(BAR_MASK+1) in BAR match.." newline hexmask.long.word 0x0 0.--11. 1. "LWR_TARGET_HW,Forms the LSB's of the Lower Target part of the new address of the translated region. The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary (in address match mode); and to the Bar size boundary (in BAR match mode) so.." repeat.end repeat 8. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 )(list 0x0 0x200 0x400 0x600 0x800 0xA00 0xC00 0xE00 ) group.long ($2+0x118+0xC0000)++0x3 line.long 0x0 "IATU_UPPER_TARGET_ADDR_OFF_INBOUND_$1,iATU Upper Target Address Register." hexmask.long 0x0 0.--31. 1. "UPPER_TARGET_RW,Forms bits [63:32] of the start address (Upper Target part) of the new address of the translated region. In systems with a 32-bit address space this register is not used and therefore writing to this register has no effect. Note: This.." repeat.end repeat 8. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 )(list 0x0 0x200 0x400 0x600 0x800 0xA00 0xC00 0xE00 ) group.long ($2+0x11C+0xC0000)++0x3 line.long 0x0 "IATU_REGION_CTRL_3_OFF_INBOUND_$1,iATU Region Control 3 Register." rbitfld.long 0x0 31. "VF_ACTIVE,Reserved. Not used." "0,1" newline hexmask.long 0x0 3.--30. 1. "RSVDP_VF_NUMBER,Reserved for future use." newline bitfld.long 0x0 0.--2. "VF_NUMBER,Virtual Function Number. When the Address and BAR matching logic in the controller indicates that a MEM-I/O transaction matches a BAR in the virtual function corresponding to this value then address translation proceeds. This check is only.." "0,1,2,3,4,5,6,7" repeat.end tree.end tree "PF0_PORT_LOGIC (Port Logic)" group.long (0x0+0x700)++0x27 line.long 0x0 "ACK_LATENCY_TIMER_OFF,Ack Latency Timer and Replay Timer Register." hexmask.long.word 0x0 16.--31. 1. "REPLAY_TIME_LIMIT,Replay Timer Limit. The replay timer expires when it reaches this limit. The controller initiates a replay upon reception of a NAK or when the replay timer expires. For more details see 'Transmit Replay'. You can modify the effective.." newline hexmask.long.word 0x0 0.--15. 1. "ROUND_TRIP_LATENCY_TIME_LIMIT,Ack Latency Timer Limit. The Ack latency timer expires when it reaches this limit. For more details see 'Ack Scheduling'. You can modify the effective timer limit with the TIMER_MOD_ACK_NAK field of the.." line.long 0x4 "VENDOR_SPEC_DLLP_OFF,Vendor Specific DLLP Register." hexmask.long 0x4 0.--31. 1. "VENDOR_SPEC_DLLP,Vendor Specific DLLP Register. Used to send a specific PCI Express DLLP. Your application writes the 8-bit DLLP Type and 24-bits of Payload data into this register then sets the field VENDOR_SPECIFIC_DLLP_REQ of PORT_LINK_CTRL_OFF to.." line.long 0x8 "PORT_FORCE_OFF,Port Force Link Register." hexmask.long.byte 0x8 24.--31. 1. "RSVDP_24,Reserved for future use." newline bitfld.long 0x8 23. "DO_DESKEW_FOR_SRIS,Use the transitions from TS2 to Logical Idle Symbol SKP OS to Logical Idle Symbol EIEOS to Logical Idle Symbol and FTS Sequence to SKP OS to do deskew instead of using received SKP OS or TS1 to TS2 transition if DO_DESKEW_FOR_SRIS.." "0,1" newline rbitfld.long 0x8 22. "RSVDP_22,Reserved for future use." "0,1" newline hexmask.long.byte 0x8 16.--21. 1. "LINK_STATE,Forced LTSSM State. The LTSSM state that the controller is forced to when you set the FORCE_EN bit (Force Link). LTSSM state encoding is defined by the lts_state variable in workspace/src/Layer1/smlh_ltssm.v. Note: This register field is sticky." newline bitfld.long 0x8 15. "FORCE_EN,Force Link. The controller supports a testing and debug capability to allow your software to force the LTSSM state machine into a specific state and to force the controller to transmit a specific Link Command. Asserting this bit triggers the.." "0,1" newline rbitfld.long 0x8 12.--14. "RSVDP_12,Reserved for future use." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x8 8.--11. 1. "FORCED_LTSSM,Forced Link Command. The link command that the controller is forced to transmit when you set FORCE_EN bit (Force Link). Link command encoding is defined by the ltssm_cmd variable in workspace/src/Layer1/smlh_ltssm.v. Note: This register.." newline hexmask.long.byte 0x8 0.--7. 1. "LINK_NUM,Link Number. Not used for endpoint. Not used for M-PCIe. Note: This register field is sticky." line.long 0xC "ACK_F_ASPM_CTRL_OFF,Ack Frequency and L0-L1 ASPM Control Register." rbitfld.long 0xC 31. "RSVDP_31,Reserved for future use." "0,1" newline bitfld.long 0xC 30. "ENTER_ASPM,ASPM L1 Entry Control. - 1: Controller enters ASPM L1 after a period in which it has been idle. - 0: Controller enters ASPM L1 only after idle period during which both receive and transmit are in L0s. Note: This register field is sticky." "Controller enters ASPM L1 only after idle period..,Controller enters ASPM L1 after a period in.." newline bitfld.long 0xC 27.--29. "L1_ENTRANCE_LATENCY,L1 Entrance Latency. Value range is: - 000: 1 us - 001: 2 us - 010: 4 us - 011: 8 us - 100: 16 us - 101: 32 us - 110 or 111: 64 us Note: Programming this timer with a value greater that 32us has no effect unless extended sync is used.." "0,1,2,3,4,5,6,7" newline bitfld.long 0xC 24.--26. "L0S_ENTRANCE_LATENCY,L0s Entrance Latency. Values correspond to: - 000: 1 us - 001: 2 us - 010: 3 us - 011: 4 us - 100: 5 us - 101: 6 us - 110 or 111: 7 us This field is applicable to STALL while in L0 for M-PCIe. Note: This register field is sticky." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0xC 16.--23. 1. "COMMON_CLK_N_FTS,Common Clock N_FTS. This is the N_FTS when common clock is used. The number of Fast Training Sequence ordered sets to be transmitted when transitioning from L0s to L0. The maximum number of FTS ordered-sets that a component can request.." newline hexmask.long.byte 0xC 8.--15. 1. "ACK_N_FTS,N_FTS. The number of Fast Training Sequence ordered sets to be transmitted when transitioning from L0s to L0. The maximum number of FTS ordered-sets that a component can request is 255. The controller does not support a value of zero; a value.." newline hexmask.long.byte 0xC 0.--7. 1. "ACK_FREQ,Ack Frequency. The controller accumulates the number of pending ACKs specified here (up to 255) before scheduling an ACK DLLP. - 0: Indicates that this Ack Frequency Counter feature is turned off. The controller generates a low-priority ACK.." line.long 0x10 "PORT_LINK_CTRL_OFF,Port Link Control Register." hexmask.long.byte 0x10 28.--31. 1. "RSVDP_28,Reserved for future use." newline bitfld.long 0x10 27. "TRANSMIT_LANE_REVERSALE_ENABLE,TRANSMIT_LANE_REVERSALE_ENABLE is an internally reserved field. Do not use. Note: This register field is sticky." "0,1" newline bitfld.long 0x10 26. "EXTENDED_SYNCH,EXTENDED_SYNCH is an internally reserved field. Do not use. Note: This register field is sticky." "0,1" newline bitfld.long 0x10 25. "CORRUPT_LCRC_ENABLE,CORRUPT_LCRC_ENABLE is an internally reserved field. Do not use. Note: This register field is sticky." "0,1" newline bitfld.long 0x10 24. "BEACON_ENABLE,BEACON_ENABLE is an internally reserved field. Do not use. Note: This register field is sticky." "0,1" newline hexmask.long.byte 0x10 16.--21. 1. "LINK_CAPABLE,Link Mode Enable. Sets the number of lanes in the link that you want to connect to the link partner. When you have unused lanes in your system then you must change the value in this register to reflect the number of lanes. You must also.." newline hexmask.long.byte 0x10 12.--15. 1. "RSVDP_12,Reserved for future use." newline hexmask.long.byte 0x10 8.--11. 1. "LINK_RATE,LINK_RATE is an internally reserved field. Do not use. Note: This register field is sticky." newline bitfld.long 0x10 7. "FAST_LINK_MODE,Fast Link Mode. Sets all internal LTSSM millisecond timers to Fast Mode for speeding up simulation. Forces the LTSSM training (link initialization) to use shorter time-outs and to link up faster. The default scaling factor can be changed.." "0,1" newline bitfld.long 0x10 6. "LINK_DISABLE,LINK_DISABLE is an internally reserved field. Do not use. Note: This register field is sticky." "0,1" newline bitfld.long 0x10 5. "DLL_LINK_EN,DLL Link Enable. Enables link initialization. When DLL Link Enable =0 the controller does not transmit InitFC DLLPs and does not establish a link. Note: This register field is sticky." "0,1" newline rbitfld.long 0x10 4. "RSVDP_4,Reserved for future use." "0,1" newline bitfld.long 0x10 3. "RESET_ASSERT,Reset Assert. Triggers a recovery and forces the LTSSM to the hot reset state (downstream port only). Note: This register field is sticky." "0,1" newline bitfld.long 0x10 2. "LOOPBACK_ENABLE,Loopback Enable. Turns on loopback. For more details see 'Loopback'. For M-PCIe to force the master to enter Digital Loopback mode you must set this field to '1' during Configuration.start state(initial discovery/configuration). M-PCIe.." "0,1" newline bitfld.long 0x10 1. "SCRAMBLE_DISABLE,Scramble Disable. Turns off data scrambling. Note: This register field is sticky." "0,1" newline bitfld.long 0x10 0. "VENDOR_SPECIFIC_DLLP_REQ,Vendor Specific DLLP Request. When software writes a '1' to this bit the controller transmits the DLLP contained in the VENDOR_SPEC_DLLP field of VENDOR_SPEC_DLLP_OFF. Reading from this self-clearing register field always.." "0,1" line.long 0x14 "LANE_SKEW_OFF,Lane Skew Register." bitfld.long 0x14 31. "DISABLE_LANE_TO_LANE_DESKEW,Disable Lane-to-Lane Deskew. Causes the controller to disable the internal Lane-to-Lane deskew logic. Note: This register field is sticky." "0,1" newline hexmask.long.byte 0x14 27.--30. 1. "IMPLEMENT_NUM_LANES,Implementation-specific Number of Lanes. Set the implementation-specific number of lanes. Allowed values are: - 4'b0000: 1 lane - 4'b0001: 2 lanes - 4'b0011: 4 lanes - 4'b0111: 8 lanes - 4'b1111: 16 lanes The number of lanes to be.." newline bitfld.long 0x14 26. "ELASTIC_BUFFER_MODE,Selects Elasticity Buffer operating mode: 0: Nominal Half Full Buffer mode 1: Nominal Empty Buffer Mode Note: This register field is sticky." "Nominal Half Full Buffer mode,Nominal Empty Buffer Mode" newline bitfld.long 0x14 25. "ACK_NAK_DISABLE,Ack/Nak Disable. Prevents the controller from sending ACK and NAK DLLPs. Note: This register field is sticky." "0,1" newline bitfld.long 0x14 24. "FLOW_CTRL_DISABLE,Flow Control Disable. Prevents the controller from sending FC DLLPs. Note: This register field is sticky." "0,1" newline hexmask.long.tbyte 0x14 0.--23. 1. "INSERT_LANE_SKEW,INSERT_LANE_SKEW is an internally reserved field. Do not use. Note: This register field is sticky." line.long 0x18 "TIMER_CTRL_MAX_FUNC_NUM_OFF,Timer Control and Max Function Number Register." rbitfld.long 0x18 31. "RSVDP_31,Reserved for future use." "0,1" newline bitfld.long 0x18 29.--30. "FAST_LINK_SCALING_FACTOR,Fast Link Timer Scaling Factor. Sets the scaling factor of LTSSM timer when FAST_LINK_MODE field in PORT_LINK_CTRL_OFF is set to '1'. - 0: Scaling Factor is 1024 (1ms is 1us *a) - 1: Scaling Factor is 256 (1ms is 4us) - 2:.." "Scaling Factor is 1024,Scaling Factor is 256,Scaling Factor is 64,Scaling Factor is 16" newline hexmask.long.byte 0x18 24.--28. 1. "UPDATE_FREQ_TIMER,UPDATE_FREQ_TIMER is an internally reserved field. Do not use. Note: This register field is sticky." newline hexmask.long.byte 0x18 19.--23. 1. "TIMER_MOD_ACK_NAK,Ack Latency Timer Modifier. Increases the timer value for the Ack latency timer in increments of 64 clock cycles. A value of '0' represents no modification to the timer value. For more details see the ROUND_TRIP_LATENCY_TIME_LIMIT.." newline hexmask.long.byte 0x18 14.--18. 1. "TIMER_MOD_REPLAY_TIMER,Replay Timer Limit Modifier. Increases the time-out value for the replay timer in increments of 64 clock cycles at Gen1 or Gen2 speed and in increments of 256 clock cycles at Gen3 speed. A value of '0' represents no modification.." newline hexmask.long.byte 0x18 8.--13. 1. "RSVDP_8,Reserved for future use." newline hexmask.long.byte 0x18 0.--7. 1. "MAX_FUNC_NUM,Maximum function number that can be used in a request. Configuration requests targeted at function numbers above this value are returned with UR (unsupported request). Note: This register field is sticky." line.long 0x1C "SYMBOL_TIMER_FILTER_1_OFF,Symbol Timer Register and Filter Mask 1 Register. The Filter Mask 1 Register modifies the RADM filtering and error handling rules. For more details. see the 'Receive Filtering' section. In each case. '0' applies the associated.." hexmask.long.word 0x1C 16.--31. 1. "MASK_RADM_1,Filter Mask 1. The Filter Mask 1 Register modifies the RADM filtering and error handling rules. For more details see the 'Receive Filtering' section. In each case '0' applies the associated filtering rule and '1' masks the associated.." newline bitfld.long 0x1C 15. "DISABLE_FC_WD_TIMER,Disable FC Watchdog Timer. Note: This register field is sticky." "0,1" newline hexmask.long.byte 0x1C 11.--14. 1. "EIDLE_TIMER,EIDLE_TIMER is an internally reserved field. Do not use. Note: This register field is sticky." newline hexmask.long.word 0x1C 0.--10. 1. "SKP_INT_VAL,SKP Interval Value. The number of symbol times to wait between transmitting SKP ordered sets. Note that the controller actually waits the number of symbol times in this register plus 1 between transmitting SKP ordered sets. Your application.." line.long 0x20 "FILTER_MASK_2_OFF,Filter Mask 2 Register. This register modifies the RADM filtering and error handling rules. For more details. see the 'Receive Filtering' section. In each case. '0' applies the associated filtering rule and '1' masks the associated.." hexmask.long 0x20 0.--31. 1. "MASK_RADM_2,Filter Mask 2. This field modifies the RADM filtering and error handling rules. For more details see the 'Receive Filtering' section. In each case '0' applies the associated filtering rule and '1' masks the associated filtering rule." line.long 0x24 "AMBA_MUL_OB_DECOMP_NP_SUB_REQ_CTRL_OFF,AMBA Multiple Outbound Decomposed NP SubRequests Control Register." hexmask.long 0x24 1.--31. 1. "RSVDP_1,Reserved for future use." newline bitfld.long 0x24 0. "OB_RD_SPLIT_BURST_EN,Enable AMBA Multiple Outbound Decomposed NP SubRequests. This bit when set to '0' disables the possibility of having multiple outstanding non-posted requests that were derived from decomposition of an outbound AMBA request. For more.." "0,1" rgroup.long (0x28+0x700)++0x13 line.long 0x0 "PL_DEBUG0_OFF,Debug Register 0" hexmask.long 0x0 0.--31. 1. "DEB_REG_0,The value on cxpl_debug_info[31:0]." line.long 0x4 "PL_DEBUG1_OFF,Debug Register 1" hexmask.long 0x4 0.--31. 1. "DEB_REG_1,The value on cxpl_debug_info[63:32]." line.long 0x8 "TX_P_FC_CREDIT_STATUS_OFF,Transmit Posted FC Credit Status" hexmask.long.word 0x8 20.--31. 1. "RSVDP_TX_P_FC_CREDIT_STATUS,Reserved for future use." newline hexmask.long.byte 0x8 12.--19. 1. "TX_P_HEADER_FC_CREDIT,Transmit Posted Header FC Credits. The posted Header credits advertised by the receiver at the other end of the link updated with each UpdateFC DLLP. Default value depends on the number of advertised credits for header and data.." newline hexmask.long.word 0x8 0.--11. 1. "TX_P_DATA_FC_CREDIT,Transmit Posted Data FC Credits. The posted Data credits advertised by the receiver at the other end of the link updated with each UpdateFC DLLP. Default value depends on the number of advertised credits for header and data Scaled.." line.long 0xC "TX_NP_FC_CREDIT_STATUS_OFF,Transmit Non-Posted FC Credit Status" hexmask.long.word 0xC 20.--31. 1. "RSVDP_TX_NP_FC_CREDIT_STATUS,Reserved for future use." newline hexmask.long.byte 0xC 12.--19. 1. "TX_NP_HEADER_FC_CREDIT,Transmit Non-Posted Header FC Credits. The non-posted Header credits advertised by the receiver at the other end of the link updated with each UpdateFC DLLP. Default value depends on the number of advertised credits for header and.." newline hexmask.long.word 0xC 0.--11. 1. "TX_NP_DATA_FC_CREDIT,Transmit Non-Posted Data FC Credits. The non-posted Data credits advertised by the receiver at the other end of the link updated with each UpdateFC DLLP. Default value depends on the number of advertised credits for header and data.." line.long 0x10 "TX_CPL_FC_CREDIT_STATUS_OFF,Transmit Completion FC Credit Status" hexmask.long.word 0x10 20.--31. 1. "RSVDP_TX_CPL_FC_CREDIT_STATUS,Reserved for future use." newline hexmask.long.byte 0x10 12.--19. 1. "TX_CPL_HEADER_FC_CREDIT,Transmit Completion Header FC Credits. The Completion Header credits advertised by the receiver at the other end of the link updated with each UpdateFC DLLP. Default value depends on the number of advertised credits for header.." newline hexmask.long.word 0x10 0.--11. 1. "TX_CPL_DATA_FC_CREDIT,Transmit Completion Data FC Credits. The Completion Data credits advertised by the receiver at the other end of the link updated with each UpdateFC DLLP. Default value depends on the number of advertised credits for header and data.." group.long (0x3C+0x700)++0x3 line.long 0x0 "QUEUE_STATUS_OFF,Queue Status" bitfld.long 0x0 31. "TIMER_MOD_FLOW_CONTROL_EN,FC Latency Timer Override Enable. When this bit is set the value from the 'FC Latency Timer Override Value' field in this register will override the FC latency timer value that the controller calculates according to the PCIe.." "0,1" newline rbitfld.long 0x0 29.--30. "RSVDP_29,Reserved for future use." "0,1,2,3" newline hexmask.long.word 0x0 16.--28. 1. "TIMER_MOD_FLOW_CONTROL,FC Latency Timer Override Value. When you set the 'FC Latency Timer Override Enable' in this register the value in this field will override the FC latency timer value that the controller calculates according to the PCIe.." newline rbitfld.long 0x0 13. "RX_SERIALIZATION_Q_NON_EMPTY,Receive Serialization Queue Not Empty. Indicates there is data in the serialization queue." "0,1" newline hexmask.long.word 0x0 4.--12. 1. "RSVDP_4,Reserved for future use." newline bitfld.long 0x0 3. "RX_QUEUE_OVERFLOW,Receive Credit Queue Overflow. Indicates insufficient buffer space available to write to the P/NP/CPL credit queue." "0,1" newline rbitfld.long 0x0 2. "RX_QUEUE_NON_EMPTY,Receive Credit Queue Not Empty. Indicates there is data in one or more of the receive buffers." "0,1" newline rbitfld.long 0x0 1. "TX_RETRY_BUFFER_NE,Transmit Retry Buffer Not Empty. Indicates that there is data in the transmit retry buffer." "0,1" newline rbitfld.long 0x0 0. "RX_TLP_FC_CREDIT_NON_RETURN,Received TLP FC Credits Not Returned. Indicates that the controller has received a TLP but has not yet sent an UpdateFC DLLP indicating that the credits for that TLP have been restored by the receiver at the other end of the.." "0,1" rgroup.long (0x40+0x700)++0x7 line.long 0x0 "VC_TX_ARBI_1_OFF,VC Transmit Arbitration Register 1" hexmask.long.byte 0x0 24.--31. 1. "WRR_WEIGHT_VC_3,WRR Weight for VC3. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R" newline hexmask.long.byte 0x0 16.--23. 1. "WRR_WEIGHT_VC_2,WRR Weight for VC2. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R" newline hexmask.long.byte 0x0 8.--15. 1. "WRR_WEIGHT_VC_1,WRR Weight for VC1. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R" newline hexmask.long.byte 0x0 0.--7. 1. "WRR_WEIGHT_VC_0,WRR Weight for VC0. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R" line.long 0x4 "VC_TX_ARBI_2_OFF,VC Transmit Arbitration Register 2" hexmask.long.byte 0x4 24.--31. 1. "WRR_WEIGHT_VC_7,WRR Weight for VC7. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R" newline hexmask.long.byte 0x4 16.--23. 1. "WRR_WEIGHT_VC_6,WRR Weight for VC6. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R" newline hexmask.long.byte 0x4 8.--15. 1. "WRR_WEIGHT_VC_5,WRR Weight for VC5. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R" newline hexmask.long.byte 0x4 0.--7. 1. "WRR_WEIGHT_VC_4,WRR Weight for VC4. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R" group.long (0x48+0x700)++0xB line.long 0x0 "VC0_P_RX_Q_CTRL_OFF,Segmented-Buffer VC0 Posted Receive Queue Control." bitfld.long 0x0 31. "VC_ORDERING_RX_Q,VC Ordering for Receive Queues. Determines the VC ordering rule for the receive queues used only in the segmented-buffer configuration: - 1: Strict ordering higher numbered VCs have higher priority - 0: Round robin Note: This register.." "Round robin,Strict ordering" newline bitfld.long 0x0 30. "TLP_TYPE_ORDERING_VC0,TLP Type Ordering for VC0. Determines the TLP type ordering rule for VC0 receive queues used only in the segmented-buffer configuration: - 1: PCIe ordering rules (recommended) - 0: Strict ordering: posted completion then.." "Strict ordering: posted,PCIe ordering rules" newline bitfld.long 0x0 28.--29. "RESERVED5,Reserved. Note: This register field is sticky." "0,1,2,3" newline bitfld.long 0x0 26.--27. "VC0_P_DATA_SCALE,VC0 Scale Posted Data Credites. Note: This register field is sticky." "0,1,2,3" newline bitfld.long 0x0 24.--25. "VC0_P_HDR_SCALE,VC0 Scale Posted Header Credites. Note: This register field is sticky." "0,1,2,3" newline bitfld.long 0x0 21.--23. "VC0_P_TLP_Q_MODE,Reserved. Note: This register field is sticky." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 20. "RESERVED4,Reserved. Note: This register field is sticky." "0,1" newline hexmask.long.byte 0x0 12.--19. 1. "VC0_P_HEADER_CREDIT,VC0 Posted Header Credits. The number of initial posted header credits for VC0 used only in the segmented-buffer configuration. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R (sticky) Note: This.." newline hexmask.long.word 0x0 0.--11. 1. "VC0_P_DATA_CREDIT,VC0 Posted Data Credits. The number of initial posted data credits for VC0 used only in the segmented-buffer configuration. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R (sticky) Note: This.." line.long 0x4 "VC0_NP_RX_Q_CTRL_OFF,Segmented-Buffer VC0 Non-Posted Receive Queue Control." hexmask.long.byte 0x4 28.--31. 1. "RESERVED7,Reserved. Note: This register field is sticky." newline bitfld.long 0x4 26.--27. "VC0_NP_DATA_SCALE,VC0 Scale Non-Posted Data Credites. Note: This register field is sticky." "0,1,2,3" newline bitfld.long 0x4 24.--25. "VC0_NP_HDR_SCALE,VC0 Scale Non-Posted Header Credites. Note: This register field is sticky." "0,1,2,3" newline bitfld.long 0x4 21.--23. "VC0_NP_TLP_Q_MODE,Reserved. Note: This register field is sticky." "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 20. "RESERVED6,Reserved. Note: This register field is sticky." "0,1" newline hexmask.long.byte 0x4 12.--19. 1. "VC0_NP_HEADER_CREDIT,VC0 Non-Posted Header Credits. The number of initial non-posted header credits for VC0 used only in the segmented-buffer configuration. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R (sticky).." newline hexmask.long.word 0x4 0.--11. 1. "VC0_NP_DATA_CREDIT,VC0 Non-Posted Data Credits. The number of initial non-posted data credits for VC0 used only in the segmented-buffer configuration. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R (sticky) Note:.." line.long 0x8 "VC0_CPL_RX_Q_CTRL_OFF,Segmented-Buffer VC0 Completion Receive Queue Control." hexmask.long.byte 0x8 28.--31. 1. "RESERVED9,Reserved. Note: This register field is sticky." newline bitfld.long 0x8 26.--27. "VC0_CPL_DATA_SCALE,VC0 Scale CPL Data Credites. Note: This register field is sticky." "0,1,2,3" newline bitfld.long 0x8 24.--25. "VC0_CPL_HDR_SCALE,VC0 Scale CPL Header Credites. Note: This register field is sticky." "0,1,2,3" newline bitfld.long 0x8 21.--23. "VC0_CPL_TLP_Q_MODE,Reserved. Note: This register field is sticky." "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 20. "RESERVED8,Reserved. Note: This register field is sticky." "0,1" newline hexmask.long.byte 0x8 12.--19. 1. "VC0_CPL_HEADER_CREDIT,VC0 Completion Header Credits. The number of initial Completion header credits for VC0 used only in the segmented-buffer configuration. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R (sticky).." newline hexmask.long.word 0x8 0.--11. 1. "VC0_CPL_DATA_CREDIT,VC0 Completion Data Credits. The number of initial Completion data credits for VC0 used only in the segmented-buffer configuration. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R (sticky) Note:.." group.long (0x10C+0x700)++0x3 line.long 0x0 "GEN2_CTRL_OFF,This register is used to control various functions of the controller related to link training. lane reversal. and equalization." rbitfld.long 0x0 31. "RSVDP_31,Reserved for future use." "0,1" newline bitfld.long 0x0 30. "FORCE_LANE_FLIP,Enable to force the LANE_UNDER_TEST physical lane flips to logical lane 0. All the other physical lanes are turned off. The LINK_CAPABLE register must be set to 1 and only x1 link can be formed if the FORCE_LANE_FLIP register is set to 1." "0,1" newline hexmask.long.byte 0x0 24.--27. 1. "LANE_UNDER_TEST,The Lane Under Test is the lane for Forced Lane Flip or for Loopback Eq. The value is from 0 to CX_NL. Only one lane is configured each time. The default of this field is the CX_DEFAULT_LANE_UNDER_TEST configuration parameter. This field.." newline rbitfld.long 0x0 22.--23. "RSVDP_22,Reserved for future use." "0,1,2,3" newline bitfld.long 0x0 21. "GEN1_EI_INFERENCE,Electrical Idle Inference Mode at Gen1 Rate. Programmable mode to determine inferred electrical idle (EI) in Recovery.Speed or Loopback.Active (as slave) state at Gen1 speed by looking for a '1' value on RxElecIdle instead of looking.." "Use RxElecIdle signal to infer Electrical Idle,Use RxValid signal to infer Electrical Idle" newline bitfld.long 0x0 20. "SEL_DEEMPHASIS,Used to set the de-emphasis level for upstream ports. This bit selects the level of de-emphasis the link operates at. - 0: -6 dB - 1: -3.5 dB This field is reserved (fixed to '0') for M-PCIe. Note: The access attributes of this field are.." "0,1" newline bitfld.long 0x0 19. "CONFIG_TX_COMP_RX,Config Tx Compliance Receive Bit. When set to 1 signals LTSSM to transmit TS ordered sets with the compliance receive bit assert (equal to '1'). This field is reserved (fixed to '0') for M-PCIe. Note: The access attributes of this.." "0,1" newline bitfld.long 0x0 18. "CONFIG_PHY_TX_CHANGE,Config PHY Tx Swing. Controls the PHY transmitter voltage swing level. The controller drives the mac_phy_txswing output from this register bit field. - 0: Full Swing - 1: Low Swing This field is reserved (fixed to '0') for M-PCIe." "Full Swing,Low Swing" newline bitfld.long 0x0 17. "DIRECT_SPEED_CHANGE,Directed Speed Change. Writing '1' to this field instructs the LTSSM to initiate a speed change to Gen2 or Gen3 after the link is initialized at Gen1 speed. When the speed change occurs the controller will clear the contents of this.." "0,1" newline bitfld.long 0x0 16. "AUTO_LANE_FLIP_CTRL_EN,Enable Auto flipping of the lanes. You must set the CX_AUTO_LANE_FLIP_CTRL_EN configuration parameter to include the hardware for this feature in the controller. For more details see the 'Lane Reversal' appendix in the Databook." "0,1" newline bitfld.long 0x0 13.--15. "PRE_DET_LANE,Predetermined Lane for Auto Flip. This field defines which physical lane is connected to logical Lane0 by the flip operation performed in Detect. This field is used to restrict the receiver detect procedure to a particular lane when the.." "LANE0,LANE1,LANE3,LANE7,LANE15,?,?,?" newline hexmask.long.byte 0x0 8.--12. 1. "NUM_OF_LANES,Predetermined Number of Lanes. Defines the number of lanes which are connected and not bad. Used to limit the effective link width to ignore 'broken' or 'unused' lanes that detect a receiver. Indicates the number of lanes to check for exit.." newline hexmask.long.byte 0x0 0.--7. 1. "FAST_TRAINING_SEQ,Sets the Number of Fast Training Sequences (N_FTS) that the controller advertises as its N_FTS during Gen2 or Gen3 link training. This value is used to inform the link partner about the PHY's ability to recover synchronization after a.." rgroup.long (0x110+0x700)++0x3 line.long 0x0 "PHY_STATUS_OFF,PHY Status Register. Memory mapped register from phy_cfg_status GPIO input pins." hexmask.long 0x0 0.--31. 1. "PHY_STATUS,PHY Status. Data received directly from the phy_cfg_status bus. These is a GPIO register reflecting the values on the static phy_cfg_status input signals. The usage is left completely to the user and does not in any way influence controller.." group.long (0x114+0x700)++0x3 line.long 0x0 "PHY_CONTROL_OFF,PHY Control Register. Memory mapped register to cfg_phy_control GPIO output pins." hexmask.long 0x0 0.--31. 1. "PHY_CONTROL,PHY Control. Data sent directly to the cfg_phy_control bus. These is a GPIO register driving the values on the static cfg_phy_control output signals. The usage is left completely to the user and does not in any way influence controller.." group.long (0x11C+0x700)++0x77 line.long 0x0 "TRGT_MAP_CTRL_OFF,Programmable Target Map Control Register." hexmask.long.word 0x0 21.--31. 1. "TARGET_MAP_RESERVED_21_31,Reserved. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R (sticky)" newline hexmask.long.byte 0x0 16.--20. 1. "TARGET_MAP_INDEX,The number of the PF Function on which the Target Values are set. This register does not respect the Byte Enable setting. any write will affect all register bits." newline rbitfld.long 0x0 13.--15. "TARGET_MAP_RESERVED_13_15,Reserved. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R (sticky)" "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x0 7.--12. 1. "TARGET_MAP_VF,Target Values for each BAR on the VF Function selected by the index number. This register does not respect the Byte Enable setting. any write will affect all register bits." newline bitfld.long 0x0 6. "TARGET_MAP_ROM,Target Value for the ROM page of the PF Function selected by the index number. This register does not respect the Byte Enable setting. any write will affect all register bits." "0,1" newline hexmask.long.byte 0x0 0.--5. 1. "TARGET_MAP_PF,Target Values for each BAR on the PF Function selected by the index number. This register does not respect the Byte Enable setting. any write will affect all register bits." line.long 0x4 "MSI_CTRL_ADDR_OFF,Integrated MSI Reception Module (iMRM) Address Register." hexmask.long 0x4 0.--31. 1. "MSI_CTRL_ADDR,Integrated MSI Reception Module Address. System specified address for MSI memory write transaction termination. Within the AXI Bridge every received Memory Write request is examined to see if it targets the MSI Address that has been.." line.long 0x8 "MSI_CTRL_UPPER_ADDR_OFF,Integrated MSI Reception Module Upper Address Register." hexmask.long 0x8 0.--31. 1. "MSI_CTRL_UPPER_ADDR,Integrated MSI Reception Module Upper Address. System specified upper address for MSI memory write transaction termination. Allows functions to support a 64-bit MSI address. Note: This register field is sticky." line.long 0xC "MSI_CTRL_INT_0_EN_OFF,Integrated MSI Reception Module Interrupt#i Enable Register." hexmask.long 0xC 0.--31. 1. "MSI_CTRL_INT_0_EN,MSI Interrupt#i Enable. Specifies which interrupts are enabled. When an MSI is received from a disabled interrupt no status bit gets set in MSI controller interrupt status register. Each bit corresponds to a single MSI Interrupt.." line.long 0x10 "MSI_CTRL_INT_0_MASK_OFF,Integrated MSI Reception Module Interrupt#i Mask Register." hexmask.long 0x10 0.--31. 1. "MSI_CTRL_INT_0_MASK,MSI Interrupt#i Mask. Allows enabled interrupts to be masked. When an MSI is received for a masked interrupt the corresponding status bit gets set in the interrupt status register but the msi_ctrl_int output is not set HIGH. Each bit.." line.long 0x14 "MSI_CTRL_INT_0_STATUS_OFF,Integrated MSI Reception Module Interrupt#i Status Register." hexmask.long 0x14 0.--31. 1. "MSI_CTRL_INT_0_STATUS,MSI Interrupt#i Status. When an MSI is detected for EP#i one bit in this register is set. The decoding of the data payload of the MSI Memory Write request determines which bit gets set. A status is bit is cleared by writing a 1 to.." line.long 0x18 "MSI_CTRL_INT_1_EN_OFF,Integrated MSI Reception Module Interrupt#i Enable Register." hexmask.long 0x18 0.--31. 1. "MSI_CTRL_INT_1_EN,MSI Interrupt#i Enable. Specifies which interrupts are enabled. When an MSI is received from a disabled interrupt no status bit gets set in MSI controller interrupt status register. Each bit corresponds to a single MSI Interrupt.." line.long 0x1C "MSI_CTRL_INT_1_MASK_OFF,Integrated MSI Reception Module Interrupt#i Mask Register." hexmask.long 0x1C 0.--31. 1. "MSI_CTRL_INT_1_MASK,MSI Interrupt#i Mask. Allows enabled interrupts to be masked. When an MSI is received for a masked interrupt the corresponding status bit gets set in the interrupt status register but the msi_ctrl_int output is not set HIGH. Each bit.." line.long 0x20 "MSI_CTRL_INT_1_STATUS_OFF,Integrated MSI Reception Module Interrupt#i Status Register." hexmask.long 0x20 0.--31. 1. "MSI_CTRL_INT_1_STATUS,MSI Interrupt#i Status. When an MSI is detected for EP#i one bit in this register is set. The decoding of the data payload of the MSI Memory Write request determines which bit gets set. A status is bit is cleared by writing a 1 to.." line.long 0x24 "MSI_CTRL_INT_2_EN_OFF,Integrated MSI Reception Module Interrupt#i Enable Register." hexmask.long 0x24 0.--31. 1. "MSI_CTRL_INT_2_EN,MSI Interrupt#i Enable. Specifies which interrupts are enabled. When an MSI is received from a disabled interrupt no status bit gets set in MSI controller interrupt status register. Each bit corresponds to a single MSI Interrupt.." line.long 0x28 "MSI_CTRL_INT_2_MASK_OFF,Integrated MSI Reception Module Interrupt#i Mask Register." hexmask.long 0x28 0.--31. 1. "MSI_CTRL_INT_2_MASK,MSI Interrupt#i Mask. Allows enabled interrupts to be masked. When an MSI is received for a masked interrupt the corresponding status bit gets set in the interrupt status register but the msi_ctrl_int output is not set HIGH. Each bit.." line.long 0x2C "MSI_CTRL_INT_2_STATUS_OFF,Integrated MSI Reception Module Interrupt#i Status Register." hexmask.long 0x2C 0.--31. 1. "MSI_CTRL_INT_2_STATUS,MSI Interrupt#i Status. When an MSI is detected for EP#i one bit in this register is set. The decoding of the data payload of the MSI Memory Write request determines which bit gets set. A status is bit is cleared by writing a 1 to.." line.long 0x30 "MSI_CTRL_INT_3_EN_OFF,Integrated MSI Reception Module Interrupt#i Enable Register." hexmask.long 0x30 0.--31. 1. "MSI_CTRL_INT_3_EN,MSI Interrupt#i Enable. Specifies which interrupts are enabled. When an MSI is received from a disabled interrupt no status bit gets set in MSI controller interrupt status register. Each bit corresponds to a single MSI Interrupt.." line.long 0x34 "MSI_CTRL_INT_3_MASK_OFF,Integrated MSI Reception Module Interrupt#i Mask Register." hexmask.long 0x34 0.--31. 1. "MSI_CTRL_INT_3_MASK,MSI Interrupt#i Mask. Allows enabled interrupts to be masked. When an MSI is received for a masked interrupt the corresponding status bit gets set in the interrupt status register but the msi_ctrl_int output is not set HIGH. Each bit.." line.long 0x38 "MSI_CTRL_INT_3_STATUS_OFF,Integrated MSI Reception Module Interrupt#i Status Register." hexmask.long 0x38 0.--31. 1. "MSI_CTRL_INT_3_STATUS,MSI Interrupt#i Status. When an MSI is detected for EP#i one bit in this register is set. The decoding of the data payload of the MSI Memory Write request determines which bit gets set. A status is bit is cleared by writing a 1 to.." line.long 0x3C "MSI_CTRL_INT_4_EN_OFF,Integrated MSI Reception Module Interrupt#i Enable Register." hexmask.long 0x3C 0.--31. 1. "MSI_CTRL_INT_4_EN,MSI Interrupt#i Enable. Specifies which interrupts are enabled. When an MSI is received from a disabled interrupt no status bit gets set in MSI controller interrupt status register. Each bit corresponds to a single MSI Interrupt.." line.long 0x40 "MSI_CTRL_INT_4_MASK_OFF,Integrated MSI Reception Module Interrupt#i Mask Register." hexmask.long 0x40 0.--31. 1. "MSI_CTRL_INT_4_MASK,MSI Interrupt#i Mask. Allows enabled interrupts to be masked. When an MSI is received for a masked interrupt the corresponding status bit gets set in the interrupt status register but the msi_ctrl_int output is not set HIGH. Each bit.." line.long 0x44 "MSI_CTRL_INT_4_STATUS_OFF,Integrated MSI Reception Module Interrupt#i Status Register." hexmask.long 0x44 0.--31. 1. "MSI_CTRL_INT_4_STATUS,MSI Interrupt#i Status. When an MSI is detected for EP#i one bit in this register is set. The decoding of the data payload of the MSI Memory Write request determines which bit gets set. A status is bit is cleared by writing a 1 to.." line.long 0x48 "MSI_CTRL_INT_5_EN_OFF,Integrated MSI Reception Module Interrupt#i Enable Register." hexmask.long 0x48 0.--31. 1. "MSI_CTRL_INT_5_EN,MSI Interrupt#i Enable. Specifies which interrupts are enabled. When an MSI is received from a disabled interrupt no status bit gets set in MSI controller interrupt status register. Each bit corresponds to a single MSI Interrupt.." line.long 0x4C "MSI_CTRL_INT_5_MASK_OFF,Integrated MSI Reception Module Interrupt#i Mask Register." hexmask.long 0x4C 0.--31. 1. "MSI_CTRL_INT_5_MASK,MSI Interrupt#i Mask. Allows enabled interrupts to be masked. When an MSI is received for a masked interrupt the corresponding status bit gets set in the interrupt status register but the msi_ctrl_int output is not set HIGH. Each bit.." line.long 0x50 "MSI_CTRL_INT_5_STATUS_OFF,Integrated MSI Reception Module Interrupt#i Status Register." hexmask.long 0x50 0.--31. 1. "MSI_CTRL_INT_5_STATUS,MSI Interrupt#i Status. When an MSI is detected for EP#i one bit in this register is set. The decoding of the data payload of the MSI Memory Write request determines which bit gets set. A status is bit is cleared by writing a 1 to.." line.long 0x54 "MSI_CTRL_INT_6_EN_OFF,Integrated MSI Reception Module Interrupt#i Enable Register." hexmask.long 0x54 0.--31. 1. "MSI_CTRL_INT_6_EN,MSI Interrupt#i Enable. Specifies which interrupts are enabled. When an MSI is received from a disabled interrupt no status bit gets set in MSI controller interrupt status register. Each bit corresponds to a single MSI Interrupt.." line.long 0x58 "MSI_CTRL_INT_6_MASK_OFF,Integrated MSI Reception Module Interrupt#i Mask Register." hexmask.long 0x58 0.--31. 1. "MSI_CTRL_INT_6_MASK,MSI Interrupt#i Mask. Allows enabled interrupts to be masked. When an MSI is received for a masked interrupt the corresponding status bit gets set in the interrupt status register but the msi_ctrl_int output is not set HIGH. Each bit.." line.long 0x5C "MSI_CTRL_INT_6_STATUS_OFF,Integrated MSI Reception Module Interrupt#i Status Register." hexmask.long 0x5C 0.--31. 1. "MSI_CTRL_INT_6_STATUS,MSI Interrupt#i Status. When an MSI is detected for EP#i one bit in this register is set. The decoding of the data payload of the MSI Memory Write request determines which bit gets set. A status is bit is cleared by writing a 1 to.." line.long 0x60 "MSI_CTRL_INT_7_EN_OFF,Integrated MSI Reception Module Interrupt#i Enable Register." hexmask.long 0x60 0.--31. 1. "MSI_CTRL_INT_7_EN,MSI Interrupt#i Enable. Specifies which interrupts are enabled. When an MSI is received from a disabled interrupt no status bit gets set in MSI controller interrupt status register. Each bit corresponds to a single MSI Interrupt.." line.long 0x64 "MSI_CTRL_INT_7_MASK_OFF,Integrated MSI Reception Module Interrupt#i Mask Register." hexmask.long 0x64 0.--31. 1. "MSI_CTRL_INT_7_MASK,MSI Interrupt#i Mask. Allows enabled interrupts to be masked. When an MSI is received for a masked interrupt the corresponding status bit gets set in the interrupt status register but the msi_ctrl_int output is not set HIGH. Each bit.." line.long 0x68 "MSI_CTRL_INT_7_STATUS_OFF,Integrated MSI Reception Module Interrupt#i Status Register." hexmask.long 0x68 0.--31. 1. "MSI_CTRL_INT_7_STATUS,MSI Interrupt#i Status. When an MSI is detected for EP#i one bit in this register is set. The decoding of the data payload of the MSI Memory Write request determines which bit gets set. A status is bit is cleared by writing a 1 to.." line.long 0x6C "MSI_GPIO_IO_OFF,Integrated MSI Reception Module General Purpose IO Register." hexmask.long 0x6C 0.--31. 1. "MSI_GPIO_REG,MSI GPIO Register. The contents of this register drives the top-level GPIO msi_ctrl_io[31:0] Note: This register field is sticky." line.long 0x70 "CLOCK_GATING_CTRL_OFF,This register enables you to disable dynamic clock gating. By default dynamic clock gating is on. allowing the controller to autonomously enable and disable its clocks. The clock gating is performed in the clock and reset module." hexmask.long 0x70 2.--31. 1. "RSVDP_2,Reserved for future use." newline bitfld.long 0x70 1. "AXI_CLK_GATING_EN,AXI Clock Gating Enable. This register enables the AXI Bridge to autonomously enable and disable the AXI Master clock the AXI Slave clock and the AXI DBI slave clock. The DWC_pcie_clk_rst.v module provides the gated clock.." "Disable,Enable" newline bitfld.long 0x70 0. "RADM_CLK_GATING_EN,RADM Clock Gating Enable. This register if set enables the RADM to autonomously enable and disable its clock. The DWC_pcie_clk_rst.v module provides the gated clock radm_clk_g to the RADM and is enabled when the controllers clock.." "Disable,Enable" line.long 0x74 "GEN3_RELATED_OFF,Gen3 Control Register. There is no Gen3-specific N_FTS field. The N_FTS field in the 'Link Width and Speed Change Control Register' is used for both Gen2 and Gen3 speed modes. There is no Gen3-specific 'Directed Speed Change' field. The.." hexmask.long.byte 0x74 26.--31. 1. "RSVDP_26,Reserved for future use." newline bitfld.long 0x74 23. "GEN3_EQ_INVREQ_EVAL_DIFF_DISABLE,Eq InvalidRequest and RxEqEval Different Time Assertion Disable. Disable the assertion of Eq InvalidRequest and RxEqEval at different time. Note: When CX_GEN4_SPEED/CX_GEN5_SPEED this register is shared for Gen3 and.." "0,1" newline rbitfld.long 0x74 19.--20. "RSVDP_19,Reserved for future use." "0,1,2,3" newline bitfld.long 0x74 18. "GEN3_DC_BALANCE_DISABLE,DC Balance Disable. Disable DC Balance feature. Note: When CX_GEN4_SPEED/CX_GEN5_SPEED this register is shared for Gen3 and Gen4/Gen5 data rate. Note: This register field is sticky." "0,1" newline bitfld.long 0x74 17. "GEN3_DLLP_XMT_DELAY_DISABLE,DLLP Transmission Delay Disable. Disable delay transmission of DLLPs before equalization. Note: When CX_GEN4_SPEED/CX_GEN5_SPEED this register is shared for Gen3 and Gen4/Gen5 data rate. Note: This register field is sticky." "0,1" newline bitfld.long 0x74 16. "GEN3_EQUALIZATION_DISABLE,Equalization Disable. Disable equalization feature. This bit cannot be changed once the LTSSM starts link training. Note: When CX_GEN4_SPEED/CX_GEN5_SPEED this register is shared for Gen3 and Gen4/Gen5 data rate. Note: This.." "0,1" newline rbitfld.long 0x74 14.--15. "RSVDP_14,Reserved for future use." "0,1,2,3" newline bitfld.long 0x74 13. "RXEQ_RGRDLESS_RXTS,When set to '1' the controller as Gen3 EQ master asserts RxEqEval to instruct the PHY to do Rx adaptation and evaluation after a 500ns timeout from a new preset request. - 0: mac_phy_rxeqeval asserts after 1us and 2 TS1 received from.." "mac_phy_rxeqeval asserts after 1us and 2 TS1..,mac_phy_rxeqeval asserts after 500ns regardless.." newline bitfld.long 0x74 12. "RXEQ_PH01_EN,Rx Equalization Phase 0/Phase 1 Hold Enable. When this bit is set the upstream port holds phase 0 (the downstream port holds phase 1) for 10ms. Holding phase 0 or phase 1 can be used to allow sufficient time for Rx Equalization to be.." "Tx equalization only in phase 2/3,No Tx equalization" newline bitfld.long 0x74 11. "EQ_REDO,Equalization Redo Disable. Disable autonomous mechanism for requesting to redo the equalization process. The received presets or coefficients mismatch in Recovery.RcvrLock after Recovery EQ phases causes the EQ redo requests. If the EQ redo is.." "0,1" newline bitfld.long 0x74 10. "EQ_EIEOS_CNT,Equalization EIEOS Count Reset Disable. Disable requesting reset of EIEOS count during equalization. Note: When CX_GEN4_SPEED/CX_GEN5_SPEED this register is shared for Gen3 and Gen4/Gen5 data rate. Note: This register field is sticky." "0,1" newline bitfld.long 0x74 9. "EQ_PHASE_2_3,Equalization Phase 2 and Phase 3 Disable. This applies to downstream ports only. Note: When CX_GEN4_SPEED/CX_GEN5_SPEED this register is shadow register for Gen3 and Gen4/Gen5 data rate. If RATE_SHADOW_SEL==00b this register is for Gen3.." "0,1" newline bitfld.long 0x74 8. "DISABLE_SCRAMBLER_GEN_3,Disable Scrambler for Gen3 and Gen4 Data Rate. The Gen3 and Gen4 scrambler/descrambler within the controller needs to be disabled when the scrambling function is implemented outside of the controller (for example within the PHY)." "0,1" newline hexmask.long.byte 0x74 1.--7. 1. "RSVDP_1,Reserved for future use." newline bitfld.long 0x74 0. "GEN3_ZRXDC_NONCOMPL,Gen3 Receiver Impedance ZRX-DC Not Compliant. Receivers that operate at 8.0 GT/s with an impedance other than the range defined by the ZRX-DC parameter for 2.5 GT/s (40-60 Ohms) must meet additional behavior requirements in the.." "The receiver complies with the ZRX-DC parameter..,The receiver does not comply with the ZRX-DC.." group.long (0x1A8+0x700)++0x7 line.long 0x0 "GEN3_EQ_CONTROL_OFF,Gen3 EQ Control Register. This register controls equalization for Phase2 in an upstream port (USP). or Phase3 in a downstream port (DSP). M-PCIe doesn't have Conventional PCIe Gen3 feature. The registers of this section do not exist." hexmask.long.byte 0x0 27.--31. 1. "RSVDP_27,Reserved for future use." newline bitfld.long 0x0 26. "GEN3_REQ_SEND_CONSEC_EIEOS_FOR_PSET_MAP,Request controller to send back-to-back EIEOS in Recovery.RcvrLock state until presets to coefficients mapping is complete. - 0: Do not request - 1: request Note: Gen3 and Gen4 share the same register bit and have.." "Do not request,request" newline bitfld.long 0x0 25. "GEN3_EQ_PSET_REQ_AS_COEF,GEN3_EQ_PSET_REQ_AS_COEF is an internally reserved field. Do not use. Note: This register field is sticky." "0,1" newline bitfld.long 0x0 24. "GEN3_EQ_FOM_INC_INITIAL_EVAL,Include Initial FOM. Include or not the FOM feedback from the initial preset evaluation performed in the EQ Master when finding the highest FOM among all preset evaluations. - 0: Do not include - 1: Include Note: When.." "Do not include,Include" newline hexmask.long.word 0x0 8.--23. 1. "GEN3_EQ_PSET_REQ_VEC,Preset Request Vector. Requesting of Presets during the initial part of the EQ Master Phase. Encoding scheme is as follows: Bit [15:0] =0x0: No preset is requested and evaluated in EQ Master Phase. Bit [i] =1: 'Preset=i' is requested.." newline rbitfld.long 0x0 7. "RSVDP_7,Reserved for future use." "0,1" newline bitfld.long 0x0 6. "GEN3_LOWER_RATE_EQ_REDO_ENABLE,Support EQ redo and lower rate change: - 0: not support - 1: support Note: Gen3 and Gen4 share the same register bit and have the same feature. Note: This register field is sticky." "not support,support" newline bitfld.long 0x0 5. "GEN3_EQ_EVAL_2MS_DISABLE,Phase2_3 2 ms Timeout Disable. Determine behavior in Phase2 for USP (Phase3 if DSP) when the PHY does not respond within 2ms to the assertion of RxEqEval: - 0: abort the current evaluation stop any attempt to modify the remote.." "abort the current evaluation,ignore the 2ms timeout and continue as normal" newline bitfld.long 0x0 4. "GEN3_EQ_PHASE23_EXIT_MODE,Behavior After 24 ms Timeout (when optimal settings are not found). For a USP: Determine next LTSSM state from Phase2 after 24ms Timeout - 0: Recovery.Speed - 1: Recovery.Equalization.Phase3 When optimal settings are not found.." "Equalization Phase 3 Successful status bit is..,Recovery" newline hexmask.long.byte 0x0 0.--3. 1. "GEN3_EQ_FB_MODE,Feedback Mode. - 0000b: Direction Change - 0001b: Figure Of Merit - 0010b: Reserved - .....: Reserved - 1111b: Reserved Note: When CX_GEN4_SPEED/CX_GEN5_SPEED this register is a shadow register for Gen3 and Gen4/Gen5 data rate. If.." line.long 0x4 "GEN3_EQ_FB_MODE_DIR_CHANGE_OFF,Gen3 EQ Direction Change Feedback Mode Control Register. Equalization controls to be used in Phase2 (USP) or Phase 3 (DSP). when you set the Feedback Mode in 'Gen3 EQ Control Register' to 'Direction Change.' These fields.." hexmask.long.word 0x4 18.--31. 1. "RSVDP_18,Reserved for future use." newline hexmask.long.byte 0x4 14.--17. 1. "GEN3_EQ_FMDC_MAX_POST_CUSROR_DELTA,Convergence Window Aperture for C+1. Post-cursor coefficients maximum delta within the convergence window depth. Allowed range: 0 1 2 ..15. Note: When CX_GEN4_SPEED/CX_GEN5_SPEED this register is shadow register for.." newline hexmask.long.byte 0x4 10.--13. 1. "GEN3_EQ_FMDC_MAX_PRE_CUSROR_DELTA,Convergence Window Aperture for C-1. Pre-cursor coefficients maximum delta within the convergence window depth. Allowed range: 0 1 2 ..15. Note: When CX_GEN4_SPEED/CX_GEN5_SPEED this register is shadow register for Gen3.." newline hexmask.long.byte 0x4 5.--9. 1. "GEN3_EQ_FMDC_N_EVALS,Convergence Window Depth. Number of consecutive evaluations considered in Phase 2/3 when determining if optimal coefficients have been found. Allowed range: 0 1 2 ..16 up to a maximum of CX_GEN3_EQ_COEFQ_DEPTH. When set to 0 EQ.." newline hexmask.long.byte 0x4 0.--4. 1. "GEN3_EQ_FMDC_T_MIN_PHASE23,Minimum Time (in ms) To Remain in EQ Master Phase. The LTSSM stays in EQ Master phase for at least this amount of time before starting to check for convergence of the coefficients. Allowed values 0 1 ... 24. Note: When.." group.long (0x1B4+0x700)++0x27 line.long 0x0 "ORDER_RULE_CTRL_OFF,Order Rule Control Register." hexmask.long.word 0x0 16.--31. 1. "RSVDP_16,Reserved for future use." newline hexmask.long.byte 0x0 8.--15. 1. "CPL_PASS_P,Completion Passing Posted Ordering Rule Control. Determines if CPL can pass halted P queue. - 0: CPL can not pass P (recommended) - 1: CPL can pass P" newline hexmask.long.byte 0x0 0.--7. 1. "NP_PASS_P,Non-Posted Passing Posted Ordering Rule Control. Determines if NP can pass halted P queue. - 0 : NP can not pass P (recommended). - 1 : NP can pass P" line.long 0x4 "PIPE_LOOPBACK_CONTROL_OFF,PIPE Loopback Control Register." bitfld.long 0x4 31. "PIPE_LOOPBACK,PIPE Loopback Enable. Indicates RMMI Loopback if M-PCIe. Note: This register field is sticky." "0,1" newline hexmask.long.byte 0x4 27.--30. 1. "RSVDP_27,Reserved for future use." newline bitfld.long 0x4 24.--26. "RXSTATUS_VALUE,RXSTATUS_VALUE is an internally reserved field. Do not use." "0,1,2,3,4,5,6,7" newline rbitfld.long 0x4 22.--23. "RSVDP_22,Reserved for future use." "0,1,2,3" newline hexmask.long.byte 0x4 16.--21. 1. "RXSTATUS_LANE,RXSTATUS_LANE is an internally reserved field. Do not use. Note: This register field is sticky." newline hexmask.long.word 0x4 0.--15. 1. "LPBK_RXVALID,LPBK_RXVALID is an internally reserved field. Do not use. Note: This register field is sticky." line.long 0x8 "MISC_CONTROL_1_OFF,DBI Read-Only Write Enable Register." hexmask.long.word 0x8 22.--31. 1. "RSVDP_22,Reserved for future use." newline bitfld.long 0x8 21. "P2P_ERR_RPT_CTRL,Determines whether to track completion of transmitted Non-Posted TLPs in P2P mode. - 0: Do not track completion - 1: Track completion Note: This register field is sticky." "Do not track completion,Track completion" newline bitfld.long 0x8 20. "P2P_TRACK_CPL_TO_REG,Determines whether to enable Peer to Peer (P2P) error reporting. - 0: Disable P2P error reporting - 1: Enable P2P error reporting Note: This register field is sticky." "Disable P2P error reporting,Enable P2P error reporting" newline bitfld.long 0x8 18.--19. "TARGET_ABOVE_CONFIG_LIMIT_REG,Configuration requests with an address greater than CONFIG_LIMIT_REG are directed to either ELBI or TRGT1 interface based on the setting of this field. This field can have the following values: - 1: ELBI - 2: TRGT1 Note:.." "?,ELBI,TRGT1,?" newline hexmask.long.word 0x8 8.--17. 1. "CONFIG_LIMIT_REG,Configuration requests are directed either to CDM or ELBI/RTRGT1 based on the value of this field. - Configuration requests with an address less CONFIG_LIMIT_REG are directed to the CDM - Configuration requests with an address greater.." newline bitfld.long 0x8 7. "CFG_TLP_BYPASS_EN_REG,Setting of this field defines which field TARGET_ABOVE_CONFIG_LIMIT_REG or CONFIG_LIMIT_REG decides the destination of Configuration requests. This field can have the following values: - 0: Configuration TLPs are routed according to.." "Configuration TLPs are routed according to the..,Configuration TLPs are routed according to the.." newline bitfld.long 0x8 6. "CPLQ_MNG_EN,This field enables the Completion Queue Management feature. Note: This register field is sticky." "0,1" newline bitfld.long 0x8 5. "ARI_DEVICE_NUMBER,When ARI is enabled this field enables use of the device ID. Note: This register field is sticky." "0,1" newline bitfld.long 0x8 4. "DISABLE_AUTO_LTR_CLR_MSG,Disable the autonomous generation of LTR clear message in upstream port. This field can have the following values: - 0: Allow the autonomous generation of LTR clear message. - 1: Disable the autonomous generation of LTR clear.." "Allow the autonomous generation of LTR clear..,Disable the autonomous generation of LTR clear.." newline bitfld.long 0x8 3. "SIMPLIFIED_REPLAY_TIMER,Enables Simplified Replay Timer (Gen4). For more details see 'Transmit Replay' in 'Transmit TLP Processing' section in the 'Controller Operations' chapter of the Databook. Simplified Replay Timer can have the following Values: -.." "0,1" newline bitfld.long 0x8 2. "UR_CA_MASK_4_TRGT1,When this field is set to '1' the controller suppresses error logging error message generation and CPL generation for non-posted requests TLPs (with UR filtering status) forwarded to your application (that is when DEFAULT_TARGET.." "0,1" newline bitfld.long 0x8 1. "DEFAULT_TARGET,Default target for an IO or MEM request with UR/CA/CRS received. Based on the value of this field the controller either drops or forwards these requests to your application. - 0: The controller drops all incoming I/O or MEM requests (after.." "The controller drops all incoming I/O or MEM..,The controller forwards all incoming I/O or MEM.." newline bitfld.long 0x8 0. "DBI_RO_WR_EN,Write to RO Registers Using DBI. Your application can write to some RO and HwInit register fields through the DBI when you set this field to '1'. For more details see 'Writing to Read-Only Registers' in 'Register Module LBC and DBI'.." "0,1" line.long 0xC "MULTI_LANE_CONTROL_OFF,UpConfigure Multi-lane Control Register. Used when upsizing or downsizing the link width through Configuration state without bringing the link down. For more details. see the 'Link Establishment' section in the 'Controller.." hexmask.long.tbyte 0xC 8.--31. 1. "RSVDP_8,Reserved for future use." newline bitfld.long 0xC 7. "UPCONFIGURE_SUPPORT,Upconfigure Support. The controller sends this value as the Link Upconfigure Capability in TS2 Ordered Sets in Configuration.Complete state. This field is reserved (fixed to '0') for M-PCIe. Note: This register field is sticky." "0,1" newline bitfld.long 0xC 6. "DIRECT_LINK_WIDTH_CHANGE,Directed Link Width Change. The controller always moves to Configuration state through Recovery state when this bit is set to '1'. - If the upconfigure_capable variable is '1' and the PCIE_CAP_HW_AUTO_WIDTH_DISABLE bit in.." "0,1" newline hexmask.long.byte 0xC 0.--5. 1. "TARGET_LINK_WIDTH,Target Link Width. Values correspond to: - 6'b000000: Controller does not start upconfigure or autonomous width downsizing in the Configuration state. - 6'b000001: x1 - 6'b000010: x2 - 6'b000100: x4 - 6'b001000: x8 - 6'b010000: x16 -.." line.long 0x10 "PHY_INTEROP_CTRL_OFF,PHY Interoperability Control Register." hexmask.long.tbyte 0x10 12.--31. 1. "RSVDP_12,Reserved for future use." newline bitfld.long 0x10 10. "L1_CLK_SEL,L1 Clock control bit. This field is reserved for internal use. You should not write to this field and change the default unless specifically instructed by Synopsys support. - 1: Controller does not request aux_clk switch and core_clk gating in.." "Controller requests aux_clk switch and core_clk..,Controller does not request aux_clk switch and.." newline rbitfld.long 0x10 9. "L1_NOWAIT_P1,L1 entry control bit. This field is reserved for internal use. You should not write to this field and change the default unless specifically instructed by Synopsys support. - 1: Controller does not wait for PHY to acknowledge transition to.." "Controller waits for the PHY to acknowledge..,Controller does not wait for PHY to acknowledge.." newline bitfld.long 0x10 8. "L1SUB_EXIT_MODE,L1 Exit Control Using phy_mac_pclkack_n. This field is reserved for internal use. You should not write to this field and change the default unless specifically instructed by Synopsys support. - 1: Controller exits L1 without waiting for.." "Controller waits for the PHY to assert..,Controller exits L1 without waiting for the PHY.." newline rbitfld.long 0x10 7. "RSVDP_7,Reserved for future use." "0,1" newline hexmask.long.byte 0x10 0.--6. 1. "RXSTANDBY_CONTROL,Rxstandby Control. Bits 0..5 determine if the controller asserts the RxStandby signal (mac_phy_rxstandby) in the indicated condition. Bit 6 enables the controller to perform the RxStandby/RxStandbyStatus handshake. This field is.." line.long 0x14 "TRGT_CPL_LUT_DELETE_ENTRY_OFF,TRGT_CPL_LUT Delete Entry Control register. Using this register you can delete one entry in the target completion LUT. You should only use this register when you know that your application will never send the completion.." bitfld.long 0x14 31. "DELETE_EN,This is a one-shot bit. A '1' write to this bit triggers the deletion of the target completion LUT entry that is specified in the LOOK_UP_ID field. This is a self-clearing register field. Reading from this register field always returns a '0'." "0,1" newline hexmask.long 0x14 0.--30. 1. "LOOK_UP_ID,This number selects one entry to delete of the TRGT_CPL_LUT." line.long 0x18 "LINK_FLUSH_CONTROL_OFF,Link Reset Request Flush Control Register." hexmask.long.byte 0x18 24.--31. 1. "RSVD_I_8,This is an internally reserved field. Do not use. Note: This register field is sticky." newline hexmask.long.tbyte 0x18 1.--23. 1. "RSVDP_1,Reserved for future use." newline bitfld.long 0x18 0. "AUTO_FLUSH_EN,Enables automatic flushing of pending requests before sending the reset request to the application logic to reset the PCIe controller and the AXI Bridge. The flushing process is initiated if any of the following events occur: - Hot reset.." "0,1" line.long 0x1C "AMBA_ERROR_RESPONSE_DEFAULT_OFF,AXI Bridge Slave Error Response Register." hexmask.long.word 0x1C 16.--31. 1. "RSVDP_16,Reserved for future use." newline hexmask.long.byte 0x1C 10.--15. 1. "AMBA_ERROR_RESPONSE_MAP,AXI Slave Response Error Map. Allows you to selectively map the errors received from the PCIe completion (for non-posted requests) to the AXI slave responses slv_rresp or slv_bresp. The recommended setting is SLVERR. CRS is.." newline hexmask.long.byte 0x1C 5.--9. 1. "RSVDP_5,Reserved for future use." newline bitfld.long 0x1C 3.--4. "AMBA_ERROR_RESPONSE_CRS,CRS Slave Error Response Mapping. Determines the AXI slave response for CRS completions. For more details see 'Error Handling' in the AXI chapter of the Databook. AHB: - always returns OKAY AXI: - 00: OKAY - 01: OKAY with all.." "OKAY,OKAY with all FFFF_FFFF data for all CRS..,?,?" newline bitfld.long 0x1C 2. "AMBA_ERROR_RESPONSE_VENDORID,Vendor ID Non-existent Slave Error Response Mapping. Determines the AXI slave response for errors on reads to non-existent Vendor ID register. For more details see 'Error Handling' in the AXI chapter of the Databook. AHB: -.." "OKAY,SLVERR/DECERR" newline rbitfld.long 0x1C 1. "RSVDP_1,Reserved for future use." "0,1" newline bitfld.long 0x1C 0. "AMBA_ERROR_RESPONSE_GLOBAL,Global Slave Error Response Mapping. Determines the AXI slave response for all error scenarios on non-posted requests. For more details see 'Error Handling' in the AXI chapter of the Databook. AHB: - 0: OKAY (with FFFF data for.." "OKAY,SLVERR/DECERR" line.long 0x20 "AMBA_LINK_TIMEOUT_OFF,Link Down AXI Bridge Slave Timeout Register. If your application AXI master issues outbound requests to the AXI bridge slave interface before the PCIe link is operational. the controller starts a 'flush' timer. The timeout value of.." hexmask.long.tbyte 0x20 9.--31. 1. "RSVDP_9,Reserved for future use." newline bitfld.long 0x20 8. "LINK_TIMEOUT_ENABLE_DEFAULT,Disable Flush. You can disable the flush feature by setting this field to '1'. Note: This register field is sticky." "0,1" newline hexmask.long.byte 0x20 0.--7. 1. "LINK_TIMEOUT_PERIOD_DEFAULT,Timeout Value (ms). The timer will timeout and then flush the bridge TX request queues after this amount of time. The timer counts when there are pending outbound AXI slave interface requests and the PCIe TX link is not.." line.long 0x24 "AMBA_ORDERING_CTRL_OFF,AMBA Ordering Control." hexmask.long.tbyte 0x24 8.--31. 1. "RSVDP_8,Reserved for future use." newline bitfld.long 0x24 7. "AX_MSTR_ZEROLREAD_FW,AXI Master Zero Length Read Forward to the application. The DW PCIe controller AXI bridge is able to terminate in order with the Posted transactions the zero length read implementing the PCIe express flush semantics of the Posted.." "The zero length Read is terminated at the DW..,The zero length Read is forward to the application" newline rbitfld.long 0x24 5.--6. "RSVDP_5,Reserved for future use." "0,1,2,3" newline bitfld.long 0x24 3.--4. "AX_MSTR_ORDR_P_EVENT_SEL,AXI Master Posted Ordering Event Selector. This field selects how the master interface determines when a P write is completed when enforcing the PCIe ordering rule 'NP must not pass P' at the AXI Master Interface. The AXI.." "B'last event: wait for the all of the write..,AW'last event: wait until the complete Posted..,This setting will not affect:,?" newline rbitfld.long 0x24 2. "RSVDP_2,Reserved for future use." "0,1" newline bitfld.long 0x24 1. "AX_SNP_EN,AXI Serialize Non-Posted Requests Enable. This field enables the AXI Bridge to serialize same ID Non-Posted Read/Write Requests on the wire. Serialization implies one outstanding same ID NP Read or Write on the wire and used to avoid AXI RAR.." "0,1" newline rbitfld.long 0x24 0. "RSVDP_0,Reserved for future use." "0,1" group.long (0x1E0+0x700)++0xB line.long 0x0 "COHERENCY_CONTROL_1_OFF,ACE Cache Coherency Control Register 1" hexmask.long 0x0 2.--31. 1. "CFG_MEMTYPE_BOUNDARY_LOW_ADDR,Boundary Lower Address For Memory Type. Bits [31:0] of dword-aligned address of the boundary for Memory type. The two lower address LSBs are '00'. Addresses up to but not including this value are in the lower address space.." newline rbitfld.long 0x0 1. "RSVDP_1,Reserved for future use." "0,1" newline bitfld.long 0x0 0. "CFG_MEMTYPE_VALUE,Sets the memory type for the lower and upper parts of the address space: - 0: lower = Peripheral; upper = Memory - 1: lower = Memory type; upper = Peripheral Note: This register field is sticky." "lower = Peripheral; upper = Memory,lower = Memory type; upper = Peripheral" line.long 0x4 "COHERENCY_CONTROL_2_OFF,ACE Cache Coherency Control Register 2" hexmask.long 0x4 0.--31. 1. "CFG_MEMTYPE_BOUNDARY_HIGH_ADDR,Boundary Upper Address For Memory Type. Bits [63:32] of the 64-bit dword-aligned address of the boundary for Memory type. Note: This register field is sticky." line.long 0x8 "COHERENCY_CONTROL_3_OFF,ACE Cache Coherency Control Register 3" hexmask.long.byte 0x8 27.--30. 1. "CFG_MSTR_AWCACHE_VALUE,Master Write CACHE Signal Value. Value of the individual bits in mstr_awcache when CFG_MSTR_AWCACHE_MODE is '1'. Note: not applicable to message requests; for message requests the value of mstr_awcache is always '0000' Note: This.." newline hexmask.long.byte 0x8 19.--22. 1. "CFG_MSTR_ARCACHE_VALUE,Master Read CACHE Signal Value. Value of the individual bits in mstr_arcache when CFG_MSTR_ARCACHE_MODE is '1'. Note: This register field is sticky." newline hexmask.long.byte 0x8 11.--14. 1. "CFG_MSTR_AWCACHE_MODE,Master Write CACHE Signal Behavior. Defines how the individual bits in mstr_awcache are controlled: - 0: set automatically by the AXI master - 1: set by the value of the corresponding bit of the CFG_MSTR_AWCACHE_VALUE field Note:.." newline hexmask.long.byte 0x8 3.--6. 1. "CFG_MSTR_ARCACHE_MODE,Master Read CACHE Signal Behavior. Defines how the individual bits in mstr_arcache are controlled: - 0: set automatically by the AXI master - 1: set by the value of the corresponding bit of the CFG_MSTR_ARCACHE_VALUE field Note:.." group.long (0x1F0+0x700)++0x7 line.long 0x0 "AXI_MSTR_MSG_ADDR_LOW_OFF,Lower 20 bits of the programmable AXI address where Messages coming from wire are mapped to. Bits [11:0] of the register are tied to zero for the address to be 4k-aligned. In previous releases. the third and fourth DWORDs of a.." hexmask.long.tbyte 0x0 12.--31. 1. "CFG_AXIMSTR_MSG_ADDR_LOW,Lower 20 bits of the programmable AXI address for Messages. Note: This register field is sticky." newline hexmask.long.word 0x0 0.--11. 1. "CFG_AXIMSTR_MSG_ADDR_LOW_RESERVED,Reserved for future use. Note: This register field is sticky." line.long 0x4 "AXI_MSTR_MSG_ADDR_HIGH_OFF,Upper 32 bits of the programmable AXI address where Messages coming from wire are mapped to." hexmask.long 0x4 0.--31. 1. "CFG_AXIMSTR_MSG_ADDR_HIGH,Upper 32 bits of the programmable AXI address for Messages. Note: This register field is sticky." rgroup.long (0x1F8+0x700)++0x7 line.long 0x0 "PCIE_VERSION_NUMBER_OFF,PCIe Controller IIP Release Version Number. The version number is given in hex format. You should convert each pair of hex characters to ASCII to interpret. Using 4.70a (GA) as an example: - VERSION_NUMBER = 0x3437302a which.." hexmask.long 0x0 0.--31. 1. "VERSION_NUMBER,Version Number." line.long 0x4 "PCIE_VERSION_TYPE_OFF,PCIe Controller IIP Release Version Type. The type is given in hex format. You should convert each pair of hex characters to ASCII to interpret. Using 4.70a (GA) as an example: - VERSION_NUMBER = 0x3437302a which translates to 470*.." hexmask.long 0x4 0.--31. 1. "VERSION_TYPE,Version Type." group.long (0x240+0x700)++0x7 line.long 0x0 "MSIX_ADDRESS_MATCH_LOW_OFF,MSI-X Address Match Low Register. When you enable the MSI-X Table RAM feature (MSIX_TABLE_EN=1). the controller implements the logic and RAM required to generate MSI-X requests. For more details. see the Interrupts section in.." hexmask.long 0x0 2.--31. 1. "MSIX_ADDRESS_MATCH_LOW,MSI-X Address Match Low Address. Note: This register field is sticky." newline rbitfld.long 0x0 1. "MSIX_ADDRESS_MATCH_RESERVED_1,Reserved. Note: This register field is sticky." "0,1" newline bitfld.long 0x0 0. "MSIX_ADDRESS_MATCH_EN,MSI-X Match Enable. Enable the MSI-X Address Match feature when the AXI bridge is present. Note: This register field is sticky." "0,1" line.long 0x4 "MSIX_ADDRESS_MATCH_HIGH_OFF,MSI-X Address Match High Register. When you enable the MSI-X Table RAM feature (MSIX_TABLE_EN=1). the controller implements the logic and RAM required to generate MSI-X requests. For more details. see the Interrupts section in.." hexmask.long 0x4 0.--31. 1. "MSIX_ADDRESS_MATCH_HIGH,MSI-X Address Match High Address. Note: This register field is sticky." wgroup.long (0x248+0x700)++0x3 line.long 0x0 "MSIX_DOORBELL_OFF,MSI-X Doorbell Register. When you enable the MSI-X Table RAM feature (MSIX_TABLE_EN=1). the controller implements the logic and RAM required to generate MSI-X requests. For more details. see the Interrupts section in the 'Controller.." bitfld.long 0x0 29.--31. "MSIX_DOORBELL_RESERVED_29_31,Reserved." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x0 24.--28. 1. "MSIX_DOORBELL_PF,MSIX Doorbell Physical Function. This register determines the Physical Function for the MSI-X transaction." newline hexmask.long.byte 0x0 16.--23. 1. "MSIX_DOORBELL_VF,MSIX Doorbell Virtual Function. This register determines the Virtual Function for the MSI-X transaction." newline bitfld.long 0x0 15. "MSIX_DOORBELL_VF_ACTIVE,MSIX Doorbell Virtual Function Active. This register determines whether a Virtual Function is used to generate the MSI-X transaction." "0,1" newline bitfld.long 0x0 12.--14. "MSIX_DOORBELL_TC,MSIX Doorbell Traffic Class. This register determines which traffic class to generate the MSI-X transaction with." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 11. "MSIX_DOORBELL_RESERVED_11,Reserved." "0,1" newline hexmask.long.word 0x0 0.--10. 1. "MSIX_DOORBELL_VECTOR,MSI-X Doorbell Vector. This register determines which vector to generate the MSI-X transaction for." group.long (0x24C+0x700)++0x3 line.long 0x0 "MSIX_RAM_CTRL_OFF,MSI-X RAM power mode and debug control register. When you enable the MSI-X Table RAM feature (MSIX_TABLE_EN=1). the controller implements the logic and RAM required to generate MSI-X requests. For more details. see the Interrupts.." hexmask.long.byte 0x0 26.--31. 1. "MSIX_RAM_CTRL_RESERVED_26_31,Reserved. Note: This register field is sticky." newline bitfld.long 0x0 25. "MSIX_RAM_CTRL_DBG_PBA,MSIX PBA RAM Debug Mode. Use this bit to activate the debug mode and allow direct read/write access to the PBA. Use can also use the dbg_pba input to activate debug mode. Debug mode turns off the PF/VF/Offset-based addressing into.." "0,1" newline bitfld.long 0x0 24. "MSIX_RAM_CTRL_DBG_TABLE,MSIX Table RAM Debug Mode. Use this bit to activate the debug mode and allow direct read/write access to the Table. Use can also use the dbg_table input to activate debug mode. Debug mode turns off the PF/VF/Offset-based.." "0,1" newline hexmask.long.byte 0x0 17.--23. 1. "MSIX_RAM_CTRL_RESERVED_17_23,Reserved. Note: This register field is sticky." newline bitfld.long 0x0 16. "MSIX_RAM_CTRL_BYPASS,MSIX RAM Control Bypass. The bypass field when set disables the internal generation of low power signals for both RAMs. It is up to the application to ensure the RAMs are in the proper power state before trying to access them." "0,1" newline hexmask.long.byte 0x0 10.--15. 1. "MSIX_RAM_CTRL_RESERVED_10_15,Reserved. Note: This register field is sticky." newline bitfld.long 0x0 9. "MSIX_RAM_CTRL_PBA_SD,MSIX PBA RAM Shut Down. Set this bit to drive the cfg_msix_pba_sd output to signal your external logic to place the MSIX PBA RAM in Shut Down low-power mode. Note: This register field is sticky." "0,1" newline bitfld.long 0x0 8. "MSIX_RAM_CTRL_PBA_DS,MSIX PBA RAM Deep Sleep. Set this bit to drive the cfg_msix_pba_ds output to signal your external logic to place the MSIX PBA RAM in Deep Sleep low-power mode. Note: This register field is sticky." "0,1" newline hexmask.long.byte 0x0 2.--7. 1. "MSIX_RAM_CTRL_RESERVED_2_7,Reserved. Note: This register field is sticky." newline bitfld.long 0x0 1. "MSIX_RAM_CTRL_TABLE_SD,MSIX Table RAM Shut Down. Set this bit to drive the cfg_msix_table_sd output to signal your external logic to place the MSIX Table RAM in Shut Down low-power mode. Note: This register field is sticky." "0,1" newline bitfld.long 0x0 0. "MSIX_RAM_CTRL_TABLE_DS,MSIX Table RAM Deep Sleep. Set this bit to drive the cfg_msix_table_ds output to signal your external logic to place the MSIX Table RAM in Deep Sleep low-power mode. Note: This register field is sticky." "0,1" group.long (0x430+0x700)++0x3 line.long 0x0 "PL_LTR_LATENCY_OFF,LTR Latency Register. The function of this register field (and all other fields in this register) differs between an upstream port and a downstream port. For an upstream port. the register fields capture the corresponding fields in the.." bitfld.long 0x0 31. "NO_SNOOP_LATENCY_REQUIRE,No Snoop Latency Requirement. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" "0,1" newline rbitfld.long 0x0 29.--30. "RSVDP_29,Reserved for future use." "0,1,2,3" newline bitfld.long 0x0 26.--28. "NO_SNOOP_LATENCY_SCALE,No Snoop Latency Scale. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" "0,1,2,3,4,5,6,7" newline hexmask.long.word 0x0 16.--25. 1. "NO_SNOOP_LATENCY_VALUE,No Snoop Latency Value. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" newline bitfld.long 0x0 15. "SNOOP_LATENCY_REQUIRE,Snoop Latency Requirement. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" "0,1" newline rbitfld.long 0x0 13.--14. "RSVDP_13,Reserved for future use." "0,1,2,3" newline bitfld.long 0x0 10.--12. "SNOOP_LATENCY_SCALE,Snoop Latency Scale. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" "0,1,2,3,4,5,6,7" newline hexmask.long.word 0x0 0.--9. 1. "SNOOP_LATENCY_VALUE,Snoop Latency Value. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" group.long (0x440+0x700)++0xB line.long 0x0 "AUX_CLK_FREQ_OFF,Auxiliary Clock Frequency Control Register." hexmask.long.tbyte 0x0 10.--31. 1. "RSVDP_10,Reserved for future use." newline hexmask.long.word 0x0 0.--9. 1. "AUX_CLK_FREQ,The aux_clk frequency in MHz. This value is used to provide a 1 us reference for counting time during low-power states with aux_clk when the PHY has removed the pipe_clk. Frequencies lower than 1 MHz are possible but with a loss of accuracy.." line.long 0x4 "L1_SUBSTATES_OFF,L1 Substates Timing Register." hexmask.long.tbyte 0x4 9.--31. 1. "RSVDP_9,Reserved for future use." newline bitfld.long 0x4 8. "L1SUB_LOW_POWER_CLOCK_SWITCH_MODE,If this bit is set to 1'b1 the reference clock will be running regardless of the CLKREQ# setting. If this bit is set to 1'b0 the reference clock may be gated off when CLKREQ# is de-asserted. If the bit is set to 1'b1 the.." "0,1" newline bitfld.long 0x4 6.--7. "L1SUB_T_PCLKACK,Max delay (in 1us units) between a MAC request to remove the clock on mac_phy_pclkreq_n and a PHY response on phy_mac_pclkack_n. If the PHY does not respond within this time the request is aborted.The actual timeout value will be.." "0,1,2,3" newline hexmask.long.byte 0x4 2.--5. 1. "L1SUB_T_L1_2,Duration (in 1us units) of L1.2. The actual timeout value will be L1SUB_T_L1_2 + 1. Range is 0.15. Note: This register field is sticky." newline bitfld.long 0x4 0.--1. "L1SUB_T_POWER_OFF,Duration (in 1us units) of L1.2.Entry. The actual timeout value will be L1SUB_T_POWER_OFF + 1. Range is 0.3. Note: This register field is sticky." "0,1,2,3" line.long 0x8 "POWERDOWN_CTRL_STATUS_OFF,Powerdown Control and Status Register." hexmask.long.tbyte 0x8 12.--31. 1. "RSVDP_12,Reserved for future use." newline hexmask.long.byte 0x8 8.--11. 1. "POWERDOWN_PHY_POWERDOWN,This field represents the Powerdown value that has been acknowledged by the PHY. It is updated with the value of Powerdown driven by the controller when the PHY has returned the Phystatus acknowledgment for the Powerdown.." newline hexmask.long.byte 0x8 4.--7. 1. "POWERDOWN_MAC_POWERDOWN,This field represents the Powerdown value driven by the controller to the PHY." newline rbitfld.long 0x8 1.--3. "RSVDP_1,Reserved for future use." "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 0. "POWERDOWN_FORCE,This field is a one shot field. Writing a value of 1 to this field causes the controller to complete the P2 Powerdown handshake regardless of whether the PHY has returned Phystatus. This field could be used for debug purposes in event.." "0,1" group.long (0x470+0x700)++0x7 line.long 0x0 "PHY_VIEWPORT_CTLSTS_OFF,PHY Register Viewport Control and Status Register." rbitfld.long 0x0 31. "PHY_VIEWPORT_PENDING,PHY viewport pending. Indicates the access is pending. - 1 : Pending - 0 : Idle This bit is set to 1 when the read/write access has been initiated. This bit is cleared when the access is completed. If phy_reg_clk_g is never activated.." "Idle,Pending" newline rbitfld.long 0x0 30. "PHY_VIEWPORT_STATUS,PHY viewport status. Indicates the status of the latest access. - 1 : Timeout - 0 : No errors If the timeout is detected this bit is set to 1 and PHY_VIEWPORT_PENDING is cleared. This bit is cleared when the read/write access is.." "No errors,Timeout" newline hexmask.long.byte 0x0 23.--29. 1. "RSVDP_23,Reserved for future use." newline bitfld.long 0x0 22. "PHY_VIEWPORT_TIMEOUT_DISABLE,PHY viewport timeout disable. Disables the PHY register access timeout structure. When the timeout is disabled you must ensure that the PHY register accesses are always acknowledged by cr_para_ack. Otherwise.." "0,1" newline bitfld.long 0x0 21. "PHY_VIEWPORT_BCWR,Broadcast write access to all xN sub-blocks. If you need to broadcast the write accesses into all lanes both PHY_VIEWPORT_ADDR[15] and this bit should be 1. Note: This register field is sticky." "0,1" newline bitfld.long 0x0 20. "PHY_VIEWPORT_READ,PHY viewport read. If set a read access is initiated. The value is always 0 when this bit is read. Note: This register field is sticky." "0,1" newline hexmask.long.byte 0x0 16.--19. 1. "PHY_VIEWPORT_NUM,PHY viewport xN sub-block number. Selects one of xN sub-blocks. This register is not used when the write access is initiated with PHY_VIEWPORT_BCWR==1. Note: This register field is sticky." newline hexmask.long.word 0x0 0.--15. 1. "PHY_VIEWPORT_ADDR,PHY viewport address. Indicates the PHY's register address. Please refer to the PHY databook for the address map definition. Note: This register field is sticky." line.long 0x4 "PHY_VIEWPORT_DATA_OFF,PHY Register Viewport Data Register." hexmask.long.word 0x4 16.--31. 1. "RSVDP_16,Reserved for future use." newline hexmask.long.word 0x4 0.--15. 1. "PHY_VIEWPORT_DATA,PHY viewport data. A write access to this register initiates the PHY register write access. By a read access to this register this field returns the latest read data from the PHY register. Note: This register field is sticky." group.long (0x490+0x700)++0x3 line.long 0x0 "PIPE_RELATED_OFF,PIPE Related Register. This register controls the pipe's capabitity. control. and status parameters." hexmask.long.tbyte 0x0 9.--31. 1. "RSVDP_9,Reserved for future use." newline bitfld.long 0x0 8. "PIPE_GARBAGE_DATA_MODE,PIPE Garbage Data Mode. - 0: PIPE Spec compliant mode: The MAC discards any symbols received after the electrical idle ordered-set until RxValid is deasserted. - 1: Special PHY Support mode: The MAC discards any symbols received.." "PIPE Spec compliant mode: The MAC discards any..,Special PHY Support mode: The MAC discards any.." tree.end tree.end tree "PCIE1_ATU_DMA" base ad:0x310C0000 tree "PF0_TYPE1_HDR (PCI-Compatible Configuration Space Header Type1)" group.long 0x0++0x2F line.long 0x0 "TYPE1_DEV_ID_VEND_ID_REG,Device ID and Vendor ID Register." hexmask.long.word 0x0 16.--31. 1. "DEVICE_ID,Device ID. The Device ID register identifies the particular Function. This identifier is allocated by the vendor. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else.." newline hexmask.long.word 0x0 0.--15. 1. "VENDOR_ID,Vendor ID. The Vendor ID register identifies the manufacturer of the Function. Valid vendor identifiers are allocated by the PCI-SIG to ensure uniqueness. It is not permitted to populate this register with a value of FFFFh which is an invalid.." line.long 0x4 "TYPE1_STATUS_COMMAND_REG,Status and Command Register." bitfld.long 0x4 31. "DETECTED_PARITY_ERROR,Detected Parity Error. This bit is set by a Function whenever it receives a Poisoned TLP regardless of the state the Parity Error Response bit in the Command register. The bit is set when the Poisoned TLP is received by a.." "0,1" newline bitfld.long 0x4 30. "SIGNALED_SYS_ERROR,Signaled System Error. This bit is set when a Function sends an ERR_FATAL or ERR_NONFATAL Message and the SERR# Enable bit in the Command register is 1b." "0,1" newline bitfld.long 0x4 29. "RCVD_MASTER_ABORT,Received Master Abort. This bit is set when a Requester receives a Completion with Unsupported Request Completion status. The bit is set when the Unsupported Request is received by a Function's primary side." "0,1" newline bitfld.long 0x4 28. "RCVD_TARGET_ABORT,Received Target Abort. This bit is set when a Requester receives a Completion with Completer Abort Completion status. The bit is set when the Completer Abort is received by a Function's primary side." "0,1" newline bitfld.long 0x4 27. "SIGNALED_TARGET_ABORT,Signaled Target Abort. This bit is set when a Function completes a Posted or Non-Posted Request as a Completer Abort error. This applies to a Function when the Completer Abort was generated by its primary side." "0,1" newline rbitfld.long 0x4 25.--26. "DEV_SEL_TIMING,DEVSEL Timing. This field was originally described in the PCI Local Bus Specification. Its functionality does not apply to PCI Express. The controller hardwires it to 00b." "0,1,2,3" newline bitfld.long 0x4 24. "MASTER_DPE,Master Data Parity Error. This bit is set by a Function if the Parity Error Response bit in the Command register is 1b and either of the following two conditions occurs: - Port receives a Poisoned Completion going downstream - Port transmits a.." "0,1" newline rbitfld.long 0x4 23. "FAST_B2B_CAP,Fast Back-to-Back Transactions Capable. This bit was originally described in the PCI Local Bus Specification. Its functionality does not apply to PCI Express. The controller hardwires this bit to 0b." "0,1" newline rbitfld.long 0x4 22. "RSVDP_22,Reserved for future use." "0,1" newline rbitfld.long 0x4 21. "FAST_66MHZ_CAP,66 MHz Capable. This bit was originally described in the PCI Local Bus Specification. Its functionality does not apply to PCI Express. The controller hardwires this bit to 0b." "0,1" newline rbitfld.long 0x4 20. "CAP_LIST,Capabilities List. Indicates the presence of an Extended Capability list item. Since all PCI Express device Functions are required to implement the PCI Express Capability structure the controller hardwires this bit to 1b." "0,1" newline rbitfld.long 0x4 19. "INT_STATUS,Interrupt Status. When set indicates that an INTx emulation interrupt is pending internally in the Function. INTx emulation interrupts forwarded by Functions from the secondary side are not reflected in this bit. Setting the Interrupt Disable.." "0,1" newline rbitfld.long 0x4 17.--18. "RSVDP_17,Reserved for future use." "0,1,2,3" newline bitfld.long 0x4 16. "IMM_READINESS,Immediate Readiness. This optional bit when set indicates the Function is guaranteed to be ready to successfully complete valid configuration accesses at any time following any reset that the host is capable of issuing Configuration.." "0,1" newline hexmask.long.byte 0x4 11.--15. 1. "RESERV,Reserved." newline bitfld.long 0x4 10. "INT_EN,Interrupt Disable. Controls the ability of a Function to generate INTx emulation interrupts. When set Functions are prevented from asserting INTx interrupts. Note: - Any INTx emulation interrupts already asserted by the Function must be.." "0,1" newline rbitfld.long 0x4 9. "RSVDP_9,Reserved for future use." "0,1" newline bitfld.long 0x4 8. "SERREN,SERR# Enable. When set this bit enables reporting upstream of Non-fatal and Fatal errors detected by the Function. Note: The errors are reported if enabled either through this bit or through the PCI Express specific bits in the Device Control.." "0,1" newline rbitfld.long 0x4 7. "IDSEL,IDSEL Stepping/Wait Cycle Control. This bit was originally described in the PCI Local Bus Specification. Its functionality does not apply to PCI Express. The controller hardwires this bit to 0b." "0,1" newline bitfld.long 0x4 6. "PERREN,Parity Error Response. This bit controls the logging of poisoned TLPs in the Master Data Parity Error bit in the Status register. For more details see the 'Error Registers' section of the PCI Express Base Specification." "0,1" newline rbitfld.long 0x4 5. "VGAPS,VGA Palette Snoop. This bit was originally described in the PCI Local Bus Specification and the PCI-to-PCI Bridge Architecture Specification. Its functionality does not apply to PCI Express. The controller hardwires this bit to 0b." "0,1" newline rbitfld.long 0x4 4. "MWI_EN,Memory Write and Invalidate. This bit was originally described in the PCI Local Bus Specification and the PCI-to-PCI Bridge Architecture Specification. Its functionality does not apply to PCI Express. The controller hardwires this bit to 0b. For.." "0,1" newline rbitfld.long 0x4 3. "SCO,Special Cycle Enable. This bit was originally described in the PCI Local Bus Specification. Its functionality does not apply to PCI Express. The controller hardwires this bit to 0b." "0,1" newline bitfld.long 0x4 2. "BME,Bus Master Enable. This bit controls forwarding of Memory or I/O requests by a port in the Upstream direction. When this bit is 0b Memory and I/O Requests received at a Root Port must be handled as Unsupported Requests (UR) For Non-Posted Requests a.." "0,1" newline bitfld.long 0x4 1. "MSE,Memory Space Enable. This bit controls a Function's response to Memory Space accesses received on its primary side. - When set the Function is enabled to decode the address and further process Memory Space accesses. - When clear all received Memory.." "0,1" newline bitfld.long 0x4 0. "IO_EN,IO Space Enable. This bit controls a Function's response to I/O Space accesses received on its primary side. - When set the Function is enabled to decode the address and further process I/O Space accesses. - When clear all received I/O accesses.." "0,1" line.long 0x8 "TYPE1_CLASS_CODE_REV_ID_REG,Class Code and Revision ID Register." hexmask.long.byte 0x8 24.--31. 1. "BASE_CLASS_CODE,Base Class Code. A code that broadly classifies the type of operation the Function performs. Encodings for base class are provided in the PCI Code and ID Assignment Specification. All unspecified encodings are reserved. Note: The access.." newline hexmask.long.byte 0x8 16.--23. 1. "SUBCLASS_CODE,Sub-Class Code. Specifies a base class sub-class which identifies more specifically the operation of the Function. Encodings for sub-class are provided in the PCI Code and ID Assignment Specification. All unspecified encodings are.." newline hexmask.long.byte 0x8 8.--15. 1. "PROGRAM_INTERFACE,Programming Interface. This field identifies a specific register level programming interface (if any) so that device independent software can interact with the Function. Encodings for interface are provided in the PCI Code and ID.." newline hexmask.long.byte 0x8 0.--7. 1. "REVISION_ID,Revision ID. The value of this field specifies a Function specific revision identifier. The value is chosen by the vendor. Zero is an acceptable value. The Revision ID should be viewed as a vendor defined extension to the Device ID. Note: The.." line.long 0xC "TYPE1_BIST_HDR_TYPE_LAT_CACHE_LINE_SIZE_REG,BIST. Header Type. Latency Timer. and Cache Line Size Register." hexmask.long.byte 0xC 24.--31. 1. "BIST,BIST. This register is used for control and status of BIST. Functions that do not support BIST must hardwire the register to 00h. A Function whose BIST is invoked must not prevent normal operation of the PCI Express Link. Bit descriptions: - [31]:.." newline rbitfld.long 0xC 23. "MULTI_FUNC,Multi-Function Device. - When set indicates that the device may contain multiple Functions but not necessarily. Software is permitted to probe for Functions other than Function 0. - When clear software must not probe for Functions other.." "0,1" newline hexmask.long.byte 0xC 16.--22. 1. "HEADER_TYPE,Header Layout. This field identifies the layout of the second part of the predefined header. The controller uses 000 0001b encoding. The encoding 000 0010b is reserved. This encoding was originally described in the PC Card Standard Electrical.." newline hexmask.long.byte 0xC 8.--15. 1. "LATENCY_MASTER_TIMER,Latency Timer. This register is also referred to as Primary Latency Timer. The Latency Timer was originally described in the PCI Local Bus Specification and the PCI-to-PCI Bridge Architecture Specification. Its functionality does not.." newline hexmask.long.byte 0xC 0.--7. 1. "CACHE_LINE_SIZE,Cache Line Size. The Cache Line Size register is programmed by the system firmware or the operating system to system cache line size. However legacy conventional PCI software may not always be able to program this register correctly.." line.long 0x10 "BAR0_REG,BAR0 Register. System software must build a consistent address map before booting the machine to an operating system. This means it has to determine how much memory is in the system. and how much address space the Functions in the system.." hexmask.long 0x10 4.--31. 1. "BAR0_START,BAR0 Base Address. - Memory Space: Base Address. - IO Space: bits[31:2] are used to map the function into IO space/Base. Address. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R(Sticky)/W(Sticky) if.." newline bitfld.long 0x10 3. "BAR0_PREFETCH,BAR0 Prefetchable. - Memory Space: Set to one if data is pre-fetchable. A Function is permitted to mark a range as prefetchable. If there are no side effects on reads the function returns all bytes on reads regardless of the byte enables.." "0,1" newline bitfld.long 0x10 1.--2. "BAR0_TYPE,BAR0 Type. - Memory Space: Base Address registers that map into Memory Space can be 32 bits or 64 bits wide (to support mapping into a 64-bit address space). The bit encoding is as follows: -- 00: Base register is 32 bits wide and can be mapped.." "Base register is 32 bits wide and can be mapped..,Reserved,?,?" newline bitfld.long 0x10 0. "BAR0_MEM_IO,BAR0 Memory Space Indicator. This bit is used to determine whether the register maps into Memory or I/O Space. Base Address registers that map to Memory Space must return a 0b. Base Address registers that map to I/O Space must return a 1b." "0,1" line.long 0x14 "BAR1_REG,BAR1 Register. System software must build a consistent address map before booting the machine to an operating system. This means it has to determine how much memory is in the system. and how much address space the Functions in the system.." hexmask.long 0x14 4.--31. 1. "BAR1_START,BAR1 Base Address. - Memory Space: Base Address. - IO Space: bits[31:2] are used to map the function into IO space/Base. Address. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R(Sticky)/W(Sticky) if.." newline bitfld.long 0x14 3. "BAR1_PREFETCH,BAR1 Prefetchable. - Memory Space: Set to one if data is pre-fetchable. A Function is permitted to mark a range as prefetchable. If there are no side effects on reads the function returns all bytes on reads regardless of the byte enables.." "0,1" newline bitfld.long 0x14 1.--2. "BAR1_TYPE,BAR1 Type. - Memory Space: Base Address registers that map into Memory Space can be 32 bits or 64 bits wide (to support mapping into a 64-bit address space). The bit encoding is as follows: -- 00: Base register is 32 bits wide and can be mapped.." "Base register is 32 bits wide and can be mapped..,Reserved,?,?" newline bitfld.long 0x14 0. "BAR1_MEM_IO,BAR1 Memory Space Indicator. This bit is used to determine whether the register maps into Memory or I/O Space. Base Address registers that map to Memory Space must return a 0b. Base Address registers that map to I/O Space must return a 1b." "0,1" line.long 0x18 "SEC_LAT_TIMER_SUB_BUS_SEC_BUS_PRI_BUS_REG,Secondary Latency Timer. Subordinate Bus Number. Secondary Bus Number. and Primary Bus Number Register." hexmask.long.byte 0x18 24.--31. 1. "SEC_LAT_TIMER,Secondary Latency Timer. This register does not apply to PCI Express. The controller hardwires it to 00h." newline hexmask.long.byte 0x18 16.--23. 1. "SUB_BUS,Subordinate Bus Number. The Subordinate Bus Number register is used to record the bus number of the highest numbered PCI bus segment which is behind (or subordinate to) the bridge. Configuration software programs the value in this register. The.." newline hexmask.long.byte 0x18 8.--15. 1. "SEC_BUS,Secondary Bus Number. The Secondary Bus Number register is used to record the bus number of the PCI bus segment to which the secondary interface of the bridge is connected. Configuration software programs the value in this register. The bridge.." newline hexmask.long.byte 0x18 0.--7. 1. "PRIM_BUS,Primary Bus Number. This register is not used by PCI Express Functions. It is implemented for compatibility with legacy software." line.long 0x1C "SEC_STAT_IO_LIMIT_IO_BASE_REG,Secondary Status. and I/O Limit and Base Register. The I/O Limit and I/O Base registers are optional and define an address range that is used by the bridge to determine when to forward I/O transactions from one interface to.." bitfld.long 0x1C 31. "SEC_STAT_DPE,Detected Parity Error. This bit is set by a Function when a Poisoned TLP is received by its secondary side regardless of the state the Parity Error Response Enable bit in the Bridge Control register." "0,1" newline bitfld.long 0x1C 30. "SEC_STAT_RCVD_SYS_ERR,Received System Error. This bit is set when the secondary side of a Function receives an ERR_FATAL or ERR_NONFATAL message." "0,1" newline bitfld.long 0x1C 29. "SEC_STAT_RCVD_MSTR_ABRT,Received Master Abort. This bit is set when the secondary side of a Function (for requests initiated by the Type 1 header Function itself) receives a Completion with Unsupported Request Completion status." "0,1" newline bitfld.long 0x1C 28. "SEC_STAT_RCVD_TRGT_ABRT,Received Target Abort. This bit is set when the secondary side of a Function (for requests initiated by the Type 1 header Function itself) receives a Completion with Completer Abort Completion status." "0,1" newline bitfld.long 0x1C 27. "SEC_STAT_SIG_TRGT_ABRT,Signaled Target Abort. This bit is set when the secondary side of the Function (for Requests completed by the Type 1 header Function itself) completes a Posted or Non-Posted request as a Completer Abort error." "0,1" newline rbitfld.long 0x1C 25.--26. "RSVDP_25,Reserved for future use." "0,1,2,3" newline bitfld.long 0x1C 24. "SEC_STAT_MDPE,Master Data Parity Error. This bit is set by a Function if the Parity Error Response Enable bit in the Bridge Control register is set and either of the following two conditions occurs: - Port receives a Poisoned Completion coming Upstream.." "0,1" newline rbitfld.long 0x1C 23. "RSVDP_23,Reserved for future use." "0,1" newline hexmask.long.byte 0x1C 16.--22. 1. "SEC_STAT_RESERV,Reserved." newline hexmask.long.byte 0x1C 12.--15. 1. "IO_LIMIT,I/O Limit Address. These bits correspond to the address[15:12] of IO address range. For the purpose of address decoding the bridge assumes that the lower 12 address bits address[11:0] of the I/O limit address (not implemented in the I/O Limit.." newline rbitfld.long 0x1C 9.--11. "IO_RESERV1,Reserved." "0,1,2,3,4,5,6,7" newline bitfld.long 0x1C 8. "IO_DECODE_BIT8,I/O Addressing Encode (IO Limit Address). This bit encodes the IO addressing capability of the bridge. IO_DECODE_BIT8 indicates the following: - 0h: The bridge supports only 16-bit I/O addressing (for ISA compatibility). For the purpose of.." "0,1" newline hexmask.long.byte 0x1C 4.--7. 1. "IO_BASE,I/O Base Address. These bits correspond to the address[15:12] of IO address range. For the purpose of address decoding the bridge assumes that the lower 12 address bits address[11:0] of the I/O base address (not implemented in the I/O Base.." newline rbitfld.long 0x1C 1.--3. "IO_RESERV,Reserved." "0,1,2,3,4,5,6,7" newline bitfld.long 0x1C 0. "IO_DECODE,I/O Addressing Encode (IO Base Address) This bit encodes the IO addressing capability of the bridge. IO_DECODE indicates the following: - 0h: The bridge supports only 16-bit I/O addressing (for ISA compatibility). For the purpose of address.." "0,1" line.long 0x20 "MEM_LIMIT_MEM_BASE_REG,Memory Limit and Base Register. The Memory Limit and Memory Base registers define a memory mapped address range which is used by the bridge to determine when to forward memory transactions from one interface to the other. If there.." hexmask.long.word 0x20 20.--31. 1. "MEM_LIMIT,Memory Limit Address. These bits correspond to the upper 12 address bits Address[31:20] of 32-bit addresses. For the purpose of address decoding the bridge assumes that the lower 20 address bits Address[19:0] of the memory limit address.." newline hexmask.long.byte 0x20 16.--19. 1. "MEM_LIMIT_RESERV,Reserved." newline hexmask.long.word 0x20 4.--15. 1. "MEM_BASE,Memory Base Address. These bits correspond to the upper 12 address bits Address[31:20] of 32-bit addresses. For the purpose of address decoding the bridge assumes that the lower 20 address bits Address[19:0] of the memory base address (not.." newline hexmask.long.byte 0x20 0.--3. 1. "MEM_BASE_RESERV,Reserved." line.long 0x24 "PREF_MEM_LIMIT_PREF_MEM_BASE_REG,Prefetchable Memory Limit and Base Register. The Prefetchable Memory Limit and Prefetchable Memory Base registers must indicate that 64-bit addresses are supported. as defined in PCI-to-PCI Bridge Architecture.." hexmask.long.word 0x24 20.--31. 1. "PREF_MEM_LIMIT,Prefetchable Memory Limit Address. If the Prefetchable Memory Limit register indicates support for 32-bit addressing then the Prefetchable Limit Upper 32 Bits register is implemented as a read-only register that returns zero when read. If.." newline rbitfld.long 0x24 17.--19. "PREF_RESERV1,Reserved." "0,1,2,3,4,5,6,7" newline rbitfld.long 0x24 16. "PREF_MEM_LIMIT_DECODE,Prefetchable Memory Limit Decode. This bit encodes whether or not the bridge supports 64-bit addresses. Note: This bit is a copy of the PREF_MEM_DECODE bit and always reflects the current value of that bit. The value of.." "0,1" newline hexmask.long.word 0x24 4.--15. 1. "PREF_MEM_BASE,Prefetchable Memory Base Address. If the Prefetchable Memory Base register indicates support for 32-bit addressing then the Prefetchable Base Upper 32 Bits register is implemented as a read-only register that returns zero when read. If the.." newline rbitfld.long 0x24 1.--3. "PREF_RESERV,Reserved." "0,1,2,3,4,5,6,7" newline bitfld.long 0x24 0. "PREF_MEM_DECODE,Prefetchable Memory Base Decode. This bit encodes whether or not the bridge supports 64-bit addresses. Note: By default the bit is set to 1'b1 indicating that 64-bit addresses are supported. If the bridge only supports 32-bit prefetchable.." "0,1" line.long 0x28 "PREF_BASE_UPPER_REG,Prefetchable Base Upper 32 Bits Register. The Prefetchable Base Upper 32 Bits register is an optional extension to the Prefetchable Memory Base register." hexmask.long 0x28 0.--31. 1. "PREF_MEM_BASE_UPPER,Prefetchable Base Upper 32 Bit. If the Prefetchable Memory Base register indicates support for 32-bit addressing then this register is implemented as read-only register that returns zero when read. If the Prefetchable Memory Base.." line.long 0x2C "PREF_LIMIT_UPPER_REG,Prefetchable Limit Upper 32 Bits Register. The Prefetchable Limit Upper 32 Bits register is an optional extension to the Prefetchable Memory Limit register." hexmask.long 0x2C 0.--31. 1. "PREF_MEM_LIMIT_UPPER,Prefetchable Limit Upper 32 Bit. If the Prefetchable Memory Limit register indicate support for 64-bit addressing then this register is implemented as read/write register which must be initialized by configuration software. This.." rgroup.long 0x30++0x3 line.long 0x0 "IO_LIMIT_UPPER_IO_BASE_UPPER_REG,I/O Limit and Base Upper 16 Bits Register. The I/O Limit Upper 16 Bits and I/O Base Upper 16 Bits registers are optional extensions to the I/O Limit and I/O Base registers." hexmask.long.word 0x0 16.--31. 1. "IO_LIMIT_UPPER,I/O Limit Upper 16 Bits. If the I/O Limit register indicates support for 16-bit I/O address decoding then this register is implemented as a read-only register which return zero when read. If the I/O Limit register indicates support for.." newline hexmask.long.word 0x0 0.--15. 1. "IO_BASE_UPPER,I/O Base Upper 16 Bits. If the I/O Base register indicates support for 16-bit I/O address decoding then this register is implemented as a read-only register which return zero when read. If the I/O base register indicates support for 32-bit.." group.long 0x34++0xB line.long 0x0 "TYPE1_CAP_PTR_REG,Capabilities Pointer Register." hexmask.long.tbyte 0x0 8.--31. 1. "RSVDP_8,Reserved for future use." newline hexmask.long.byte 0x0 0.--7. 1. "CAP_POINTER,Capabilities Pointer. This register is used to point to a linked list of capabilities implemented by this Function. Since all PCI Express Functions are required to implement the PCI Express Capability structure this register must point to a.." line.long 0x4 "TYPE1_EXP_ROM_BASE_REG,Expansion ROM Base Address Register. This register is defined to handle the base address and size information for this expansion ROM. The mask for this ROM BAR exists (if implemented) as a shadow register at this address. The.." hexmask.long.tbyte 0x4 11.--31. 1. "EXP_ROM_BASE_ADDRESS,Expansion ROM Base Address. Upper 21 bits of the Expansion ROM base address. The number of bits (out of these 21) that a Function actually implements depends on how much address space the Function requires. The mask for this ROM BAR.." newline hexmask.long.word 0x4 1.--10. 1. "RSVDP_1,Reserved for future use." newline bitfld.long 0x4 0. "ROM_BAR_ENABLE,Expansion ROM Enable. This bit controls whether or not the Function accepts accesses to its expansion ROM. When this bit is 0b the Function's expansion ROM address space is disabled. When the bit is 1b address decoding is enabled using.." "0,1" line.long 0x8 "BRIDGE_CTRL_INT_PIN_INT_LINE_REG,Bridge Control. Interrupt Pin. and Interrupt Line Register." hexmask.long.word 0x8 23.--31. 1. "BRIDGE_CTRL_RESERV,Reserved." newline bitfld.long 0x8 22. "SBR,Secondary Bus Reset. Setting this bit triggers a hot reset on the corresponding PCI Express Port. Software must ensure a minimum reset duration (Trst) as defined in the PCI Local Bus Specification. Software and systems must honor.." "0,1" newline rbitfld.long 0x8 21. "MSTR_ABORT_MODE,Master Abort Mode. This bit was originally described in the PCI-to-PCI Bridge Architecture Specification. Its functionality does not apply to PCI Express. The controller hardwires this bit to 0b. Note: The access attributes of this field.." "0,1" newline rbitfld.long 0x8 20. "VGA_16B_DEC,VGA 16 bit decode. This bit only has meaning if VGA Enable bit is set. This bit enables system configuration software to select between 10-bit and 16-bit I/O address decoding for all VGA I/O register accesses that are forwarded from primary.." "0,1" newline rbitfld.long 0x8 19. "VGA_EN,VGA Enable. Modifies the response by the bridge to VGA compatible addresses. If the VGA Enable bit is set the bridge will positively decode and forward the following accesses on the primary interface to the secondary interface (and conversely.." "0,1" newline bitfld.long 0x8 18. "ISA_EN,ISA Enable. Modifies the response by the bridge to ISA I/O addresses. This applies only to I/O addresses that are enabled by the I/O Base and I/O Limit registers and are in the first 64 KB of I/O address space (0000 0000h to 0000 FFFFh). If this.." "?,KB block" newline bitfld.long 0x8 17. "SERR_EN,SERR# Enable. This bit controls forwarding of ERR_COR ERR_NONFATAL and ERR_FATAL from secondary to primary." "0,1" newline bitfld.long 0x8 16. "PERE,Parity Error Response Enable. This bit controls the logging of poisoned TLPs in the Master Data Parity Error bit in the Secondary Status register." "0,1" newline hexmask.long.byte 0x8 8.--15. 1. "INT_PIN,Interrupt PIN. The Interrupt Pin register register that identifies the legacy interrupt Message(s) the Function uses. Valid values are: - 01h 02h 03h and 04h: map to legacy interrupt Messages for INTA INTB INTC and INTD respectively. - 00h:.." newline hexmask.long.byte 0x8 0.--7. 1. "INT_LINE,Interrupt Line. The Interrupt Line register communicates interrupt line routing information. The register must be implemented by any Function that uses an interrupt pin. Values in this register are programmed by system software and are system.." tree.end tree "PF0_SPCIE_CAP (Secondary PCI Express Capability Structure)" group.long (0x0+0x1A0)++0xF line.long 0x0 "SPCIE_CAP_HEADER_REG,SPCIE Capability Header. For a description of this standard PCIe register. see the PCI Express Specification." hexmask.long.word 0x0 20.--31. 1. "NEXT_OFFSET,Next Capability Offset. For a description of this standard PCIe register field see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky).." hexmask.long.byte 0x0 16.--19. 1. "CAP_VERSION,Capability Version. For a description of this standard PCIe register field see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else.." hexmask.long.word 0x0 0.--15. 1. "EXTENDED_CAP_ID,Secondary PCI Express Extended Capability ID. For a description of this standard PCIe register field see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN.." line.long 0x4 "LINK_CONTROL3_REG,Link Control 3 Register. For a description of this standard PCIe register. see the PCI Express Specification." hexmask.long 0x4 2.--31. 1. "RSVDP_2,Reserved for future use." bitfld.long 0x4 1. "EQ_REQ_INT_EN,Link Equalization Request Interrupt Enable. For a description of this standard PCIe register field see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" "0,1" bitfld.long 0x4 0. "PERFORM_EQ,Perform Equalization. For a description of this standard PCIe register field see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" "0,1" line.long 0x8 "LANE_ERR_STATUS_REG,Lane Error Status Register. For a description of this standard PCIe register. see the PCI Express Specification." hexmask.long 0x8 2.--31. 1. "RSVDP_LANE_ERR_STATUS,Reserved for future use." bitfld.long 0x8 0.--1. "LANE_ERR_STATUS,Lane Error Status Bits per Lane. For a description of this standard PCIe register field see the PCI Express Specification." "0,1,2,3" line.long 0xC "SPCIE_CAP_OFF_0CH_REG,Lane Equalization Control Register for lanes 1 and 0. For a description of this standard PCIe register. see the PCI Express Specification." rbitfld.long 0xC 31. "RSVDP_31,Reserved for future use." "0,1" bitfld.long 0xC 28.--30. "USP_RX_PRESET_HINT1,Upstream Port 8.0 GT/s Receiver Preset Hint 1. The write value is gated with the PCIE_CAP_CROSS_LINK_SUPPORT field of LINK_CAPABILITIES2_REG. For a description of this standard PCIe register field see the PCI Express Specification." "0,1,2,3,4,5,6,7" hexmask.long.byte 0xC 24.--27. 1. "USP_TX_PRESET1,Upstream Port 8.0 GT/s Transmitter Preset 1. The write value is gated with the PCIE_CAP_CROSS_LINK_SUPPORT field of LINK_CAPABILITIES2_REG. For a description of this standard PCIe register field see the PCI Express Specification. Note:.." rbitfld.long 0xC 23. "RSVDP_23,Reserved for future use." "0,1" newline bitfld.long 0xC 20.--22. "DSP_RX_PRESET_HINT1,Downstream Port 8.0 GT/s Receiver Preset Hint 1. For a description of this standard PCIe register field see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if.." "0,1,2,3,4,5,6,7" hexmask.long.byte 0xC 16.--19. 1. "DSP_TX_PRESET1,Downstream Port 8.0 GT/s Transmitter Preset 1. For a description of this standard PCIe register field see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN.." rbitfld.long 0xC 15. "RSVDP_15,Reserved for future use." "0,1" bitfld.long 0xC 12.--14. "USP_RX_PRESET_HINT0,Upstream Port 8.0 GT/s Receiver Preset Hint 0. The write value is gated with the PCIE_CAP_CROSS_LINK_SUPPORT field of LINK_CAPABILITIES2_REG. For a description of this standard PCIe register field see the PCI Express Specification." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0xC 8.--11. 1. "USP_TX_PRESET0,Upstream Port 8.0 GT/s Transmitter Preset 0. The write value is gated with the PCIE_CAP_CROSS_LINK_SUPPORT field of LINK_CAPABILITIES2_REG. For a description of this standard PCIe register field see the PCI Express Specification. Note:.." rbitfld.long 0xC 7. "RSVDP_7,Reserved for future use." "0,1" bitfld.long 0xC 4.--6. "DSP_RX_PRESET_HINT0,Downstream Port 8.0 GT/s Receiver Preset Hint 0. For a description of this standard PCIe register field see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if.." "0,1,2,3,4,5,6,7" hexmask.long.byte 0xC 0.--3. 1. "DSP_TX_PRESET0,Downstream Port 8.0 GT/s Transmitter Preset 0. For a description of this standard PCIe register field see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN.." tree.end tree "PF0_L1SUB_CAP (L1 Substates Capability Structure)" group.long (0x0+0x2E8)++0xF line.long 0x0 "L1SUB_CAP_HEADER_REG,L1 Substates Extended Capability Header. This register provides capbility ID. capability version and next offset value for L1 Substates." hexmask.long.word 0x0 20.--31. 1. "NEXT_OFFSET,Next Capability Offset. This field contains the offset to the next PCI Express Capability structure or 000h if no other items exist in the linked list of Capabilities. For Extended Capabilities implemented in Configuration Space this offset.." hexmask.long.byte 0x0 16.--19. 1. "CAP_VERSION,Capability Version. This field is a PCI-SIG defined version number that indicates the version of the Capability structure present. This field is depends on version of the specification. Note: The access attributes of this field are as.." hexmask.long.word 0x0 0.--15. 1. "EXTENDED_CAP_ID,L1SUB Extended Capability ID. This field is a PCI-SIG defined ID number that indicates the nature and format of the Extended Capability. Extended Capability ID for L1 PM Substates is 001Eh. Note: The access attributes of this field are as.." line.long 0x4 "L1SUB_CAPABILITY_REG,L1 Substates Capability Register. This register provides extended capability of L1 Substates." hexmask.long.byte 0x4 24.--31. 1. "RSVDP_24,Reserved for future use." hexmask.long.byte 0x4 19.--23. 1. "PWR_ON_VALUE_SUPPORT,Port T Power On Value. Along with the Port T_POWER_ON Scale field in the L1 PM Substates Capabilities register sets the time (in us) that this Port requires the port on the opposite side of Link to wait in L1.2.Exit after sampling.." rbitfld.long 0x4 18. "RSVDP_18,Reserved for future use." "0,1" bitfld.long 0x4 16.--17. "PWR_ON_SCALE_SUPPORT,Port T Power On Scale. Specifies the scale used for the Port T_POWER_ON Value field in the L1 PM Substates Capabilities register. Range of values are given below. Required for all Ports for which either the PCI-PM L1.2 Supported bit.." "?,?,?,Reserved" newline hexmask.long.byte 0x4 8.--15. 1. "COMM_MODE_SUPPORT,Port Common Mode Restore Time. Time (in us) required for this Port to re-establish common mode. Required for all Ports for which either the PCI-PM L1.2 Supported bit is Set ASPM L1.2 Supported bit is Set or both are Set otherwise.." rbitfld.long 0x4 5.--7. "RSVDP_5,Reserved for future use." "0,1,2,3,4,5,6,7" bitfld.long 0x4 4. "L1_PMSUB_SUPPORT,L1 PM Substates ECN Supported. When Set this bit indicates that this Port supports L1 PM Substates. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W (sticky)" "0,1" bitfld.long 0x4 3. "L1_1_ASPM_SUPPORT,ASPM L11 Supported. When Set this bit indicates that ASPM L1.1 is supported. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W (sticky)" "0,1" newline bitfld.long 0x4 2. "L1_2_ASPM_SUPPORT,ASPM L12 Supported. When Set this bit indicates that ASPM L1.2 is supported. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W (sticky)" "0,1" bitfld.long 0x4 1. "L1_1_PCIPM_SUPPORT,PCI-PM L11 Supported. When Set this bit indicates that PCI-PM L1.1 is supported and must be Set by all Ports implementing L1 PM Substates. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W (sticky)" "0,1" bitfld.long 0x4 0. "L1_2_PCIPM_SUPPORT,PCI-PM L12 Supported. When Set this bit indicates that PCI-PM L1.2 is supported. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W (sticky)" "0,1" line.long 0x8 "L1SUB_CONTROL1_REG,L1 Substates Control 1 Register. This register provides Controls to extended capability." bitfld.long 0x8 29.--31. "L1_2_TH_SCA,LTR L12 Threshold Scale. This field provides a scale for the value contained within the LTR_L1.2_THRESHOLD_Value.The default value for this field is 000b.Hardware operation is undefined if software writes a Not-Permitted value to this field." "0,1,2,3,4,5,6,7" rbitfld.long 0x8 26.--28. "RSVDP_26,Reserved for future use." "0,1,2,3,4,5,6,7" hexmask.long.word 0x8 16.--25. 1. "L1_2_TH_VAL,LTR L12 Threshold Value. Along with the LTR_L1.2_THRESHOLD_Scale this field indicates the LTR threshold used to determine if entry into L1 results in L1.1 (if enabled) or L1.2 (if enabled). The default value for this field is 00 0000 0000b." hexmask.long.byte 0x8 8.--15. 1. "T_COMMON_MODE,Common Mode Restore Time. Sets value of TCOMMONMODE (in us) which must be used by the Downstream Ports for timing the re-establishment of common mode.This field is of type RsvdP for Upstream Ports. Default value is implementation.." newline hexmask.long.byte 0x8 4.--7. 1. "RSVDP_4,Reserved for future use." bitfld.long 0x8 3. "L1_1_ASPM_EN,ASPM L11 Enable. When Set this bit enables ASPM L1.1.For Ports for which the ASPM L1.1 Supported bit is Clear this bit is permitted to be hardwired to 0.Default value is 0b." "0,1" bitfld.long 0x8 2. "L1_2_ASPM_EN,ASPM L12 Enable. When Set this bit enables ASPM L1.2.For Ports for which the ASPM L1.2 Supported bit is Clear this bit is permitted to be hardwired to 0.Default value is 0b." "0,1" bitfld.long 0x8 1. "L1_1_PCIPM_EN,PCI-PM L11 Enable. When Set this bit enables PCI-PM L1.1. Default value is 0b." "0,1" newline bitfld.long 0x8 0. "L1_2_PCIPM_EN,PCI-PM L12 Enable. When Set this bit enables PCI-PM L1.2.For Ports for which the PCI-PM L1.2 Supported bit is Clear this bit is permitted to be hardwired to 0.Default value is 0b." "0,1" line.long 0xC "L1SUB_CONTROL2_REG,L1 Substates Control 2 Register. This register provides Controls to extended capability." hexmask.long.tbyte 0xC 8.--31. 1. "RSVDP_8,Reserved for future use." hexmask.long.byte 0xC 3.--7. 1. "T_POWER_ON_VALUE,T Power On Value. Along with the T_POWER_ON Scale sets the minimum amount of time (in us) that the Port must wait in L1.2.Exit after sampling CLKREQ# asserted before actively driving the interface.Default value is 00101b. T_POWER_ON is.." rbitfld.long 0xC 2. "RSVDP_2,Reserved for future use." "0,1" bitfld.long 0xC 0.--1. "T_POWER_ON_SCALE,T Power On Scale. Specifies the scale used for T_POWER_ON Value. Range of values are given below. Required for all Ports that support L1.2 otherwise this field is of type RsvdP. This field must only be modified when the ASPM L1.2 Enable.." "?,?,?,Reserved" tree.end tree "PF0_RAS_DES_CAP (RAS D.E.S. Capability Structure (VSEC))" group.long (0x0+0x30C)++0x3 line.long 0x0 "RAS_DES_CAP_HEADER_REG,Vendor-Specific Extended Capability Header. For a description of this standard PCIe register. see the PCI Express Specification." hexmask.long.word 0x0 20.--31. 1. "NEXT_OFFSET,Next Capability Offset. For a description of this standard PCIe register field see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky).." newline hexmask.long.byte 0x0 16.--19. 1. "CAP_VERSION,Capability Version. For a description of this standard PCIe register field see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else.." newline hexmask.long.word 0x0 0.--15. 1. "EXTENDED_CAP_ID,PCI Express Extended Capability ID. For a description of this standard PCIe register field see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then.." rgroup.long (0x4+0x30C)++0x3 line.long 0x0 "VENDOR_SPECIFIC_HEADER_REG,Vendor-Specific Header. For a description of this standard PCIe register. see the PCI Express Specification." hexmask.long.word 0x0 20.--31. 1. "VSEC_LENGTH,VSEC Length. For a description of this standard PCIe register field see the PCI Express Specification." newline hexmask.long.byte 0x0 16.--19. 1. "VSEC_REV,VSEC Rev. For a description of this standard PCIe register field see the PCI Express Specification." newline hexmask.long.word 0x0 0.--15. 1. "VSEC_ID,VSEC ID. For a description of this standard PCIe register field see the PCI Express Specification." group.long (0x8+0x30C)++0x3 line.long 0x0 "EVENT_COUNTER_CONTROL_REG,Event Counter Control. This is a viewport control register. - Setting the EVENT_COUNTER_EVENT_SELECT and EVENT_COUNTER_LANE_SELECT fields in this register determine the Event Counter data returned by the EVENT_COUNTER_DATA_REG.." hexmask.long.byte 0x0 28.--31. 1. "RSVDP_28,Reserved for future use." newline hexmask.long.word 0x0 16.--27. 1. "EVENT_COUNTER_EVENT_SELECT,Event Counter Data Select. This field in conjunction with the EVENT_COUNTER_LANE_SELECT field indexes the Event Counter data returned by the EVENT_COUNTER_DATA_REG register. - 27-24: Group number(4-bit: 0..0x7) - 23-16: Event.." newline hexmask.long.byte 0x0 12.--15. 1. "RSVDP_12,Reserved for future use." newline hexmask.long.byte 0x0 8.--11. 1. "EVENT_COUNTER_LANE_SELECT,Event Counter Lane Select. This field in conjunction with EVENT_COUNTER_EVENT_SELECT indexes the Event Counter data returned by the EVENT_COUNTER_DATA_REG register. - 0x0: Lane0 - 0x1: Lane1 - 0x2: Lane2 - .. - 0xF: Lane15 Note:.." newline rbitfld.long 0x0 7. "EVENT_COUNTER_STATUS,Event Counter Status. This register returns the current value of the Event Counter selected by the following fields: - EVENT_COUNTER_EVENT_SELECT - EVENT_COUNTER_LANE_SELECT Note: This register field is sticky." "0,1" newline rbitfld.long 0x0 5.--6. "RSVDP_5,Reserved for future use." "0,1,2,3" newline bitfld.long 0x0 2.--4. "EVENT_COUNTER_ENABLE,Event Counter Enable. Enables/disables the Event Counter selected by the EVENT_COUNTER_EVENT_SELECT and EVENT_COUNTER_LANE_SELECT fields in this register. By default all event counters are disabled. You can enable/disable a specific.." "no change,per event off,?,?,?,?,?,?" newline bitfld.long 0x0 0.--1. "EVENT_COUNTER_CLEAR,Event Counter Clear. Clears the Event Counter selected by the EVENT_COUNTER_EVENT_SELECT and EVENT_COUNTER_LANE_SELECT fields in this register. You can clear the value of a specific Event Counter by writing the 'per clear' code and.." "no change,per clear,?,?" rgroup.long (0xC+0x30C)++0x3 line.long 0x0 "EVENT_COUNTER_DATA_REG,Event Counter Data. This viewport register returns the data selected by the following fields: - EVENT_COUNTER_EVENT_SELECT in EVENT_COUNTER_CONTROL_REG - EVENT_COUNTER_LANE_SELECT in EVENT_COUNTER_CONTROL_REG For more details. see.." hexmask.long 0x0 0.--31. 1. "EVENT_COUNTER_DATA,Event Counter Data. This register returns the data selected by the following fields: - EVENT_COUNTER_EVENT_SELECT in EVENT_COUNTER_CONTROL_REG - EVENT_COUNTER_LANE_SELECT in EVENT_COUNTER_CONTROL_REG Note: This register field is sticky." group.long (0x10+0x30C)++0x3 line.long 0x0 "TIME_BASED_ANALYSIS_CONTROL_REG,Time-based Analysis Control. Used for controlling the measurement of RX/TX data throughput and time spent in each low-power LTSSM state. For more details. see the RAS DES section in the Core Operations chapter of the.." hexmask.long.byte 0x0 24.--31. 1. "TIME_BASED_REPORT_SELECT,Time-based Report Select. Selects what type of data is measured for the selected duration (TIME_BASED_DURATION_SELECT) and returned in TIME_BASED_ANALYSIS_DATA. Each type of data is measured using one of three types of units: -.." newline hexmask.long.byte 0x0 16.--23. 1. "RSVDP_16,Reserved for future use." newline hexmask.long.byte 0x0 8.--15. 1. "TIME_BASED_DURATION_SELECT,Time-based Duration Select. Selects the duration of time-based analysis. When 'manual control' is selected and TIMER_START is set to '1' this analysis never stops until TIMER_STOP is set to '0'. - 0x0: Manual control - 0x1:.." newline hexmask.long.byte 0x0 1.--7. 1. "RSVDP_1,Reserved for future use." newline bitfld.long 0x0 0. "TIMER_START,Timer Start. - 1: Start/Restart - 0: Stop This bit will be cleared automatically when the measurement is finished. Note: The app_ras_des_tba_ctrl input also sets the contents of this field and controls the measurement start/stop. Note: This.." "Stop,Start/Restart" rgroup.long (0x14+0x30C)++0x7 line.long 0x0 "TIME_BASED_ANALYSIS_DATA_REG,Time-based Analysis Data. Contains the measurement results of RX/TX data throughput and time spent in each low-power LTSSM state. This viewport register returns the data selected by the TIME_BASED_REPORT_SELECT field in.." hexmask.long 0x0 0.--31. 1. "TIME_BASED_ANALYSIS_DATA,Time Based Analysis Data. This register returns the data selected by the TIME_BASED_REPORT_SELECT field in TIME_BASED_ANALYSIS_CONTROL_REG. The results are cleared when next measurement starts. Note: This register field is sticky." line.long 0x4 "TIME_BASED_ANALYSIS_DATA_63_32_REG,Upper 32 bits of Time-based Analysis Data. This viewport register returns the data selected by the TIME_BASED_REPORT_SELECT field in TIME_BASED_ANALYSIS_CONTROL_REG. For more details. see the RAS DES section in the Core.." hexmask.long 0x4 0.--31. 1. "TIME_BASED_ANALYSIS_DATA_63_32,Upper 32 bits of Time Based Analysis Data. Note: This register field is sticky." group.long (0x30+0x30C)++0x5F line.long 0x0 "EINJ_ENABLE_REG,Error Injection Enable. Each type of error insertion is enabled by the corresponding bit in this register. The specific injection controls for each type of error are defined in the following registers: - 0: CRC Error: EINJ0_CRC_REG - 1:.." hexmask.long 0x0 7.--31. 1. "RSVDP_7,Reserved for future use." newline bitfld.long 0x0 6. "ERROR_INJECTION6_ENABLE,Error Injection6 Enable (Specific TLP Error). Enables insertion of errors into the packets that you select. You can set this bit to '1' when you have disabled RAS datapath protection (DP) by setting CX_RASDP = CX_RASDP_RAM_PROT.." "0,1" newline bitfld.long 0x0 5. "ERROR_INJECTION5_ENABLE,Error Injection5 Enable (TLP Duplicate/Nullify Error). Enables insertion of duplicate/nullified TLPs. For more details see the EINJ5_SP_TLP_REG register. Note: This register field is sticky." "0,1" newline bitfld.long 0x0 4. "ERROR_INJECTION4_ENABLE,Error Injection4 Enable (FC Credit Update Error). Enables insertion of errors into UpdateFCs. For more details see the EINJ4_FC_REG register. Note: This register field is sticky." "0,1" newline bitfld.long 0x0 3. "ERROR_INJECTION3_ENABLE,Error Injection3 Enable (Symbol DataK Mask Error or Sync Header Error). Enables DataK masking of special symbols or the breaking of the sync header. For more details see the EINJ3_SYMBOL_REG register. Note: This register field is.." "0,1" newline bitfld.long 0x0 2. "ERROR_INJECTION2_ENABLE,Error Injection2 Enable (DLLP Error). Enables insertion of DLLP errors. For more details see the EINJ2_DLLP_REG register. Note: This register field is sticky." "0,1" newline bitfld.long 0x0 1. "ERROR_INJECTION1_ENABLE,Error Injection1 Enable (Sequence Number Error). Enables insertion of errors into sequence numbers. For more details see the EINJ1_SEQNUM_REG register. Note: This register field is sticky." "0,1" newline bitfld.long 0x0 0. "ERROR_INJECTION0_ENABLE,Error Injection0 Enable (CRC Error). Enables insertion of errors into various CRC. For more details see the EINJ0_CRC_REG register. Note: This register field is sticky." "0,1" line.long 0x4 "EINJ0_CRC_REG,Error Injection Control 0 (CRC Error). Controls the insertion of errors into the CRC. and parity of ordered sets for the selected type of the packets as follows: - LCRC. Bad TLP will be detected at the receiver side; receiver responds with.." hexmask.long.tbyte 0x4 12.--31. 1. "RSVDP_12,Reserved for future use." newline hexmask.long.byte 0x4 8.--11. 1. "EINJ0_CRC_TYPE,Error injection type. Selects the type of CRC error to be inserted. Tx Path - 0000b: New TLP's LCRC error injection - 0001b: 16bCRC error injection of ACK/NAK DLLP - 0010b: 16bCRC error injection of Update-FC DLLP - 0011b: New TLP's ECRC.." newline hexmask.long.byte 0x4 0.--7. 1. "EINJ0_COUNT,Error injection count. Indicates the number of errors. This register is decremented when the errors have been inserted. - If the counter value is 0x01 and error is inserted ERROR_INJECTION0_ENABLE in EINJ_ENABLE_REG returns 0b. - If the.." line.long 0x8 "EINJ1_SEQNUM_REG,Error Injection Control 1 (Sequence Number Error). Controls the sequence number of the specific TLPs and ACK/NAK DLLPs. Data Link Protocol Error will be detected at the Rx side of ACK/NAL DLLPs when one of these conditions is true: -.." rbitfld.long 0x8 29.--31. "RSVDP_29,Reserved for future use." "0,1,2,3,4,5,6,7" newline hexmask.long.word 0x8 16.--28. 1. "EINJ1_BAD_SEQNUM,Bad sequence number. Indicates the value to add/subtract from the naturally-assigned sequence numbers. This value is represented by two's complement. - 0x0FFF: +4095 - .. - 0x0002: +2 - 0x0001: +1 - 0x0000: 0 - 0x1FFF: -1 - 0x1FFE: -2 -.." newline hexmask.long.byte 0x8 9.--15. 1. "RSVDP_9,Reserved for future use." newline bitfld.long 0x8 8. "EINJ1_SEQNUM_TYPE,Sequence number type. Selects the type of sequence number. - 0b: Insertion of New TLP's SEQ# error - 1b: Insertion of ACK/NAK DLLP's SEQ# Error Note: This register field is sticky." "0,1" newline hexmask.long.byte 0x8 0.--7. 1. "EINJ1_COUNT,Error injection count. Indicates the number of errors. This register is decremented as the errors are being inserted. - If the counter value is 0x01 and error is inserted ERROR_INJECTION1_ENABLE in EINJ_ENABLE_REG returns '0'. - If the.." line.long 0xC "EINJ2_DLLP_REG,Error Injection Control 2 (DLLP Error). Controls the transmission of DLLPs and inserts the following errors: - If 'ACK/NAK DLLP's transmission block' is selected. replay timeout error will occur at the transmitter of the TLPs and then Data.." hexmask.long.tbyte 0xC 10.--31. 1. "RSVDP_10,Reserved for future use." newline bitfld.long 0xC 8.--9. "EINJ2_DLLP_TYPE,DLLP Type. Selects the type of DLLP errors to be inserted. - 00b: ACK/NAK DLLP's transmission block - 01b: Update FC DLLP's transmission block - 10b: Always Transmission for NAK DLLP - 11b: Reserved Note: This register field is sticky." "0,1,2,3" newline hexmask.long.byte 0xC 0.--7. 1. "EINJ2_COUNT,Error injection count. Indicates the number of errors. This register is decremented as the errors are being inserted. - If the counter value is 0x01 and the error is inserted ERROR_INJECTION2_ENABLE in EINJ_ENABLE_REG returns '0'. - If the.." line.long 0x10 "EINJ3_SYMBOL_REG,Error Injection Control 3 (Symbol Error). When 8b/10b encoding is used. this register controls error insertion into the special (K code) symbols. - If TS1/TS2/FTS/E-Idle/SKP is selected. it affects whole of the ordered set. It might.." hexmask.long.tbyte 0x10 11.--31. 1. "RSVDP_11,Reserved for future use." newline bitfld.long 0x10 8.--10. "EINJ3_SYMBOL_TYPE,Error Type. 8b/10b encoding - Mask K symbol. It is not supported to insert errors into the first ordered-set after exiting from TxElecIdle when CX_FREQ_STEP_EN has been enabled. - 000b: Reserved - 001b: COM/PAD(TS1 Order set) - 010b:.." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x10 0.--7. 1. "EINJ3_COUNT,Error injection count. Indicates the number of errors. This register is decremented as the errors are being inserted. - If the counter value is 0x01 and error is inserted ERROR_INJECTION3_ENABLE in EINJ_ENABLE_REG returns '0'. - If the.." line.long 0x14 "EINJ4_FC_REG,Error Injection Control 4 (FC Credit Error). Controls error insertion into the credit value in the UpdateFCs. It is possible to insert errors for any of the following types: - Posted TLP Header credit - Non-Posted TLP Header credit -.." rbitfld.long 0x14 29.--31. "RSVDP_29,Reserved for future use." "0,1,2,3,4,5,6,7" newline hexmask.long.word 0x14 16.--28. 1. "EINJ4_BAD_UPDFC_VALUE,Bad update-FC credit value. Indicates the value to add/subtract from the UpdateFC credit. This value is represented by two's complement. - 0x0FFF: +4095 - .. - 0x0002: +2 - 0x0001: +1 - 0x0000: 0 - 0x1FFF: -1 - 0x1FFE: -2 - .. -.." newline rbitfld.long 0x14 15. "RSVDP_15,Reserved for future use." "0,1" newline bitfld.long 0x14 12.--14. "EINJ4_VC_NUMBER,VC Number. Indicates target VC Number. Note: This register field is sticky." "0,1,2,3,4,5,6,7" newline rbitfld.long 0x14 11. "RSVDP_11,Reserved for future use." "0,1" newline bitfld.long 0x14 8.--10. "EINJ4_UPDFC_TYPE,Update-FC type. Selects the credit type. - 000b: Posted TLP Header Credit value control - 001b: Non-Posted TLP Header Credit value control - 010b: Completion TLP Header Credit value control - 011b: Reserved - 100b: Posted TLP Data Credit.." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x14 0.--7. 1. "EINJ4_COUNT,Error injection count. Indicates the number of errors. This register is decremented as the errors are being inserted. - If the counter value is 0x01 and error is inserted ERROR_INJECTION4_ENABLE in EINJ_ENABLE_REG returns '0'. - If the.." line.long 0x18 "EINJ5_SP_TLP_REG,Error Injection Control 5 (Specific TLP Error). Controls the generation of specified TLPs. Correctable errors will occur which will be fixed by the PCIe protocol. - For Duplicate TLP. the controller initiates Data Link Retry by handling.." hexmask.long.tbyte 0x18 9.--31. 1. "RSVDP_9,Reserved for future use." newline bitfld.long 0x18 8. "EINJ5_SPECIFIED_TLP,Specified TLP. Selects the specified TLP to be inserted. - 0: Generates duplicate TLPs by handling ACK DLLP as NAK DLLP. - 1: Generates Nullified TLP (Original TLP will be stored in retry buffer). Note: This register field is sticky." "Generates duplicate TLPs by handling ACK DLLP as..,Generates Nullified TLP" newline hexmask.long.byte 0x18 0.--7. 1. "EINJ5_COUNT,Error injection count. Indicates the number of errors. This register is decremented as the errors are being inserted. - If the counter value is 0x01 and error is inserted ERROR_INJECTION5_ENABLE in EINJ_ENABLE_REG returns '0'. - If the.." line.long 0x1C "EINJ6_COMPARE_POINT_H0_REG,Error Injection Control 6 (Compare Point Header DWORD #0). Program this register for the 1st DWORD of TLP header/prefix. It is necessary to carefully consider the endianness when you program this register. Bits [31:0] =.." hexmask.long 0x1C 0.--31. 1. "EINJ6_COMPARE_POINT_H0,Packet Compare Point: 1st DWORD. Specifies which Tx TLP header DWORD#0 bits to compare with the corresponding bits in the Packet Compare Value registers (EINJ6_COMPARE_VALUE*). When all specified bits (in the Tx TLP header and.." line.long 0x20 "EINJ6_COMPARE_POINT_H1_REG,Error Injection Control 6 (Compare Point Header DWORD #1). Program this register for the 2nd DWORD of TLP header/prefix. It is necessary to carefully consider the endianness when you program this register. Bits [31:0] =.." hexmask.long 0x20 0.--31. 1. "EINJ6_COMPARE_POINT_H1,Packet Compare Point: 2nd DWORD. Specifies which Tx TLP header DWORD#1 bits to compare with the corresponding bits in the Packet Compare Value registers (EINJ6_COMPARE_VALUE*). When all specified bits (in the Tx TLP header and.." line.long 0x24 "EINJ6_COMPARE_POINT_H2_REG,Error Injection Control 6 (Compare Point Header DWORD #2). Program this register for the 3rd DWORD of TLP header/prefix. It is necessary to carefully consider the endianness when you program this register. Bits [31:0] =.." hexmask.long 0x24 0.--31. 1. "EINJ6_COMPARE_POINT_H2,Packet Compare Point: 3rd DWORD. Specifies which Tx TLP header DWORD#2 bits to compare with the corresponding bits in the Packet Compare Value registers (EINJ6_COMPARE_VALUE*). When all specified bits (in the Tx TLP header and.." line.long 0x28 "EINJ6_COMPARE_POINT_H3_REG,Error Injection Control 6 (Compare Point Header DWORD #3). Program this register for the 4th DWORD of TLP header/prefix. It is necessary to carefully consider the endianness when you program this register. Bits [31:0] =.." hexmask.long 0x28 0.--31. 1. "EINJ6_COMPARE_POINT_H3,Packet Compare Point: 4th DWORD. Specifies which Tx TLP header DWORD#3 bits to compare with the corresponding bits in the Packet Compare Value registers (EINJ6_COMPARE_VALUE*). When all specified bits (in the Tx TLP header and.." line.long 0x2C "EINJ6_COMPARE_VALUE_H0_REG,Error Injection Control 6 (Compare Value Header DWORD #0). Program this register for the 1st DWORD of TLP header/prefix. It is necessary to carefully consider the endianness when you program this register. Bits [31:0] =.." hexmask.long 0x2C 0.--31. 1. "EINJ6_COMPARE_VALUE_H0,Packet Compare Value: 1st DWORD. Specifies the value to compare against Tx the TLP header DWORD#0 bits specified in the Packet Compare Point registers (EINJ6_COMPARE_POINT*). Note: This register field is sticky." line.long 0x30 "EINJ6_COMPARE_VALUE_H1_REG,Error Injection Control 6 (Compare Value Header DWORD #1). Program this register for the 2nd DWORD of TLP header/prefix. It is necessary to carefully consider the endianness when you program this register. Bits [31:0] =.." hexmask.long 0x30 0.--31. 1. "EINJ6_COMPARE_VALUE_H1,Packet Compare Value: 2nd DWORD. Specifies the value to compare against Tx the TLP header DWORD#1 bits specified in the Packet Compare Point registers (EINJ6_COMPARE_POINT*). Note: This register field is sticky." line.long 0x34 "EINJ6_COMPARE_VALUE_H2_REG,Error Injection Control 6 (Compare Value Header DWORD #2). Program this register for the 3rd DWORD of TLP header/prefix. It is necessary to carefully consider the endianness when you program this register. Bits [31:0] =.." hexmask.long 0x34 0.--31. 1. "EINJ6_COMPARE_VALUE_H2,Packet Compare Value: 3rd DWORD. Specifies the value to compare against Tx the TLP header DWORD#2 bits specified in the Packet Compare Point registers (EINJ6_COMPARE_POINT*). Note: This register field is sticky." line.long 0x38 "EINJ6_COMPARE_VALUE_H3_REG,Error Injection Control 6 (Compare Value Header DWORD #3). Program this register for the 4th DWORD of TLP header/prefix. It is necessary to carefully consider the endianness when you program this register. Bits [31:0] =.." hexmask.long 0x38 0.--31. 1. "EINJ6_COMPARE_VALUE_H3,Packet Compare Value: 4th DWORD. Specifies the value to compare against Tx the TLP header DWORD#3 bits specified in the Packet Compare Point registers (EINJ6_COMPARE_POINT*). Note: This register field is sticky." line.long 0x3C "EINJ6_CHANGE_POINT_H0_REG,Error Injection Control 6 (Change Point Header DWORD #0). Program this register for the 1st DWORD of TLP header/prefix. It is necessary to carefully consider the endianness when you program this register. Bits [31:0] =.." hexmask.long 0x3C 0.--31. 1. "EINJ6_CHANGE_POINT_H0,Packet Change Point: 1st DWORD. Specifies which Tx TLP header DWORD#0 bits to replace with the corresponding bits in the Packet Change Value registers (EINJ6_CHANGE_VALUE*). Note: This register field is sticky." line.long 0x40 "EINJ6_CHANGE_POINT_H1_REG,Error Injection Control 6 (Change Point Header DWORD #1). Program this register for the 2nd DWORD of TLP header/prefix. It is necessary to carefully consider the endianness when you program this register. Bits [31:0] =.." hexmask.long 0x40 0.--31. 1. "EINJ6_CHANGE_POINT_H1,Packet Change Point: 2nd DWORD. Specifies which Tx TLP header DWORD#1 bits to replace with the corresponding bits in the Packet Change Value registers (EINJ6_CHANGE_VALUE*). Note: This register field is sticky." line.long 0x44 "EINJ6_CHANGE_POINT_H2_REG,Error Injection Control 6 (Change Point Header DWORD #2). Program this register for the 3rd DWORD of TLP header/prefix. It is necessary to carefully consider the endianness when you program this register. Bits [31:0] =.." hexmask.long 0x44 0.--31. 1. "EINJ6_CHANGE_POINT_H2,Packet Change Point: 3rd DWORD. Specifies which Tx TLP header DWORD#2 bits to replace with the corresponding bits in the Packet Change Value registers (EINJ6_CHANGE_VALUE*). Note: This register field is sticky." line.long 0x48 "EINJ6_CHANGE_POINT_H3_REG,Error Injection Control 6 (Change Point Header DWORD #3). Program this register for the 4th DWORD of TLP header/prefix. It is necessary to carefully consider the endianness when you program this register. Bits [31:0] =.." hexmask.long 0x48 0.--31. 1. "EINJ6_CHANGE_POINT_H3,Packet Change Point: 4th DWORD. Specifies which Tx TLP header DWORD#3 bits to replace with the corresponding bits in the Packet Change Value registers (EINJ6_CHANGE_VALUE*). Note: This register field is sticky." line.long 0x4C "EINJ6_CHANGE_VALUE_H0_REG,Error Injection Control 6 (Change Value Header DWORD #0). Program this register for the 1st DWORD of TLP header/prefix. It is necessary to carefully consider the endianness when you program this register. Bits [31:0] =.." hexmask.long 0x4C 0.--31. 1. "EINJ6_CHANGE_VALUE_H0,Packet Change Value: 1st DWORD. Specifies replacement values for the Tx TLP header DWORD#0 bits defined in the Packet Change Point registers (EINJ6_CHANGE_POINT*). Only applies when the EINJ6_INVERTED_CONTROL field in EINJ6_TLP_REG.." line.long 0x50 "EINJ6_CHANGE_VALUE_H1_REG,Error Injection Control 6 (Change Value Header DWORD #1). Program this register for the 2nd DWORD of TLP header/prefix. It is necessary to carefully consider the endianness when you program this register. Bits [31:0] =.." hexmask.long 0x50 0.--31. 1. "EINJ6_CHANGE_VALUE_H1,Packet Change Value: 2nd DWORD. Specifies replacement values for the Tx TLP header DWORD#1 bits defined in the Packet Change Point registers (EINJ6_CHANGE_POINT*). Only applies when the EINJ6_INVERTED_CONTROL field in EINJ6_TLP_REG.." line.long 0x54 "EINJ6_CHANGE_VALUE_H2_REG,Error Injection Control 6 (Change Value Header DWORD #2). Program this register for the 3rd DWORD of TLP header/prefix. It is necessary to carefully consider the endianness when you program this register. Bits [31:0] =.." hexmask.long 0x54 0.--31. 1. "EINJ6_CHANGE_VALUE_H2,Packet Change Value: 3rd DWORD. Specifies replacement values for the Tx TLP header DWORD#2 bits defined in the Packet Change Point registers (EINJ6_CHANGE_POINT*). Only applies when the EINJ6_INVERTED_CONTROL field in EINJ6_TLP_REG.." line.long 0x58 "EINJ6_CHANGE_VALUE_H3_REG,Error Injection Control 6 (Change Value Header DWORD #3). Program this register for the 4th DWORD of TLP header/prefix. It is necessary to carefully consider the endianness when you program this register. Bits [31:0] =.." hexmask.long 0x58 0.--31. 1. "EINJ6_CHANGE_VALUE_H3,Packet Change Value: 4th DWORD. Specifies replacement values for the Tx TLP header DWORD#3 bits defined in the Packet Change Point registers (EINJ6_CHANGE_POINT*). Only applies when the EINJ6_INVERTED_CONTROL field in EINJ6_TLP_REG.." line.long 0x5C "EINJ6_TLP_REG,Error Injection Control 6 (Packet Error). The Packet Compare Point registers (EINJ6_COMPARE_POINT*) specify which Tx TLP header bits to compare with the corresponding bits in the Packet Compare Value registers (EINJ6_COMPARE_VALUE*). When.." hexmask.long.tbyte 0x5C 12.--31. 1. "RSVDP_12,Reserved for future use." newline bitfld.long 0x5C 9.--11. "EINJ6_PACKET_TYPE,Packet type. Selects the TLP packets to inject errors into. - 0: TLP Header - 1: TLP Prefix 1st 4-DWORDs - 2: TLP Prefix 2nd -DWORDs - Else: Reserved Note: This register field is sticky." "TLP Header,TLP Prefix 1st 4-DWORDs,TLP Prefix 2nd -DWORDs,?,?,?,?,?" newline bitfld.long 0x5C 8. "EINJ6_INVERTED_CONTROL,Inverted Error Injection Control. - 0: EINJ6_CHANGE_VALUE_H[0/1/2/3] is used to replace bits specified by EINJ6_CHANGE_POINT_H[0/1/2/3]. - 1: EINJ6_CHANGE_VALUE_H[0/1/2/3] is ignored and inverts bits specified by.." "EINJ6_CHANGE_VALUE_H[0/1/2/3] is used to replace..,EINJ6_CHANGE_VALUE_H[0/1/2/3] is ignored and.." newline hexmask.long.byte 0x5C 0.--7. 1. "EINJ6_COUNT,Error Injection Count. Indicates the number of errors to insert. This counter is decremented while errors are been inserted. - If the counter value is 0x01 and error is inserted ERROR_INJECTION6_ENABLE in EINJ_ENABLE_REG returns '0'. - If.." group.long (0xA0+0x30C)++0x7 line.long 0x0 "SD_CONTROL1_REG,Silicon Debug Control 1. For more details. see the RAS DES section in the Core Operations chapter of the Databook." hexmask.long.byte 0x0 24.--31. 1. "RSVDP_24,Reserved for future use." newline bitfld.long 0x0 22.--23. "LOW_POWER_INTERVAL,Low Power Entry Interval Time. Interval Time that the controller starts monitoring RXELECIDLE signal after L0s/L1/L2 entry. You should set the value according to the latency from receiving EIOS to RXELECIDLE assertion at the PHY. -.." "0,1,2,3" newline bitfld.long 0x0 20.--21. "TX_EIOS_NUM,Number of Tx EIOS. This register sets the number of transmit EIOS for L0s/L1 entry and Disable/Loopback/Hot-reset exit. The controller selects the greater value between this register and the value defined by the PCI-SIG specification. 2.5GT/s.." "0,1,2,3" newline rbitfld.long 0x0 17.--19. "RSVDP_17,Reserved for future use." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 16. "FORCE_DETECT_LANE_EN,Force Detect Lane Enable. When this bit is set the controller ignores receiver detection from PHY during LTSSM Detect state and uses FORCE_DETECT_LANE. Note: This register field is sticky." "0,1" newline hexmask.long.word 0x0 0.--15. 1. "FORCE_DETECT_LANE,Force Detect Lane. When the FORCE_DETECT_LANE_EN field is set the controller ignores receiver detection from PHY during LTSSM Detect state and uses this value instead. - 0: Lane0 - 1: Lane1 - 2: Lane2 - .. - 15: Lane15 Note: This.." line.long 0x4 "SD_CONTROL2_REG,Silicon Debug Control 2. For more details. see the RAS DES section in the Core Operations chapter of the Databook." hexmask.long.word 0x4 17.--31. 1. "RSVDP_17,Reserved for future use." newline bitfld.long 0x4 16. "FRAMING_ERR_RECOVERY_DISABLE,Framing Error Recovery Disable. This bit disables a transition to Recovery state when a Framing Error is occurred. Note: This register field is sticky." "0,1" newline hexmask.long.byte 0x4 11.--15. 1. "RSVDP_11,Reserved for future use." newline bitfld.long 0x4 10. "DIRECT_LPBKSLV_TO_EXIT,Direct Loopback Slave To Exit. When this bit is set and the LTSSM is in Loopback Slave Active State the LTSSM transitions to Loopback Slave Exit state. Note: This register field is sticky." "0,1" newline bitfld.long 0x4 9. "DIRECT_POLCOMP_TO_DETECT,Direct Polling.Compliance to Detect. When this bit is set and the LTSSM is in Polling Compliance State the LTSSM transitions to Detect state. Note: This register field is sticky." "0,1" newline bitfld.long 0x4 8. "DIRECT_RECIDLE_TO_CONFIG,Direct Recovery.Idle to Configuration. When this bit is set and the LTSSM is in Recovery Idle State the LTSSM transitions to Configuration state. Note: This register field is sticky." "0,1" newline hexmask.long.byte 0x4 3.--7. 1. "RSVDP_3,Reserved for future use." newline bitfld.long 0x4 2. "NOACK_FORCE_LINKDOWN,Force LinkDown. When this bit is set and the controller detects REPLY_NUM rolling over 4 times the LTSSM transitions to Detect State. Note: This register field is sticky." "0,1" newline bitfld.long 0x4 1. "RECOVERY_REQUEST,Recovery Request. When this bit is set to '1' in L0 or L0s the LTSSM starts transitioning to Recovery State. This request does not cause a speed change or re-equalization." "0,1" newline bitfld.long 0x4 0. "HOLD_LTSSM,Hold and Release LTSSM. For as long as this register is '1' the controller stays in the current LTSSM. Note: This register field is sticky." "0,1" group.long (0xB0+0x30C)++0xB line.long 0x0 "SD_STATUS_L1LANE_REG,Silicon Debug Status(Layer1 Per-lane). This viewport register returns the data selected by the following field: - LANE_SELECT in SD_STATUS_L1LANE_REG For more details. see the RAS DES section in the Core Operations chapter of the.." hexmask.long.byte 0x0 24.--31. 1. "DESKEW_POINTER,Deskew Pointer. Indicates Deskew pointer of internal Deskew buffer of selected lane number(LANE_SELECT). Note: This register field is sticky." newline rbitfld.long 0x0 21.--23. "RSVDP_21,Reserved for future use." "0,1,2,3,4,5,6,7" newline rbitfld.long 0x0 20. "PIPE_TXELECIDLE,PIPE:TxElecIdle. Indicates PIPE TXELECIDLE signal of selected lane number(LANE_SELECT). Note: This register field is sticky." "0,1" newline rbitfld.long 0x0 19. "PIPE_RXELECIDLE,PIPE:RxElecIdle. Indicates PIPE RXELECIDLE signal of selected lane number(LANE_SELECT). Note: This register field is sticky." "0,1" newline rbitfld.long 0x0 18. "PIPE_RXVALID,PIPE:RxValid. Indicates PIPE RXVALID signal of selected lane number(LANE_SELECT). Note: This register field is sticky." "0,1" newline rbitfld.long 0x0 17. "PIPE_DETECT_LANE,PIPE:Detect Lane. Indicates whether PHY indicates receiver detection or not on selected lane number(LANE_SELECT). Note: This register field is sticky." "0,1" newline rbitfld.long 0x0 16. "PIPE_RXPOLARITY,PIPE:RxPolarity. Indicates PIPE RXPOLARITY signal of selected lane number(LANE_SELECT). Note: This register field is sticky." "0,1" newline hexmask.long.word 0x0 4.--15. 1. "RSVDP_4,Reserved for future use." newline hexmask.long.byte 0x0 0.--3. 1. "LANE_SELECT,Lane Select. Lane Select register for Silicon Debug Status Register of Layer1-PerLane. - 0x0: Lane0 - 0x1: Lane1 - 0x2: Lane2 - .. - 0xF: Lane15 Note: This register field is sticky." line.long 0x4 "SD_STATUS_L1LTSSM_REG,Silicon Debug Status(Layer1 LTSSM). For more details. see the RAS DES section in the Core Operations chapter of the Databook." hexmask.long.word 0x4 16.--31. 1. "LTSSM_VARIABLE,LTSSM Variable. Indicates internal LTSSM variables defined in the PCI Express Base Specification. C-PCIe Mode: - 0: directed_speed_change - 1: changed_speed_recovery - 2: successful_speed_negotiation - 3: upconfigure_capable; Set to '1' if.." newline rbitfld.long 0x4 15. "LANE_REVERSAL,Lane Reversal Operation. Receiver detected lane reversal. This field is only valid in the L0 LTSSM state. Note: This register field is sticky." "0,1" newline hexmask.long.byte 0x4 11.--14. 1. "RSVDP_11,Reserved for future use." newline rbitfld.long 0x4 8.--10. "PIPE_POWER_DOWN,PIPE:PowerDown. Indicates PIPE PowerDown signal. Note: This register field is sticky." "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 7. "FRAMING_ERR,Framing Error. Indicates Framing Error detection status." "0,1" newline hexmask.long.byte 0x4 0.--6. 1. "FRAMING_ERR_PTR,First Framing Error Pointer. Identifies the first Framing Error using the following encoding. The field contents are only valid value when FRAMING_ERR =1. Received Unexpected Framing Token - 01h: When non- STP/SDP/IDL Token was received.." line.long 0x8 "SD_STATUS_PM_REG,Silicon Debug Status(PM). For more details. see the RAS DES section in the Core Operations chapter of the Databook." hexmask.long.byte 0x8 24.--31. 1. "RSVDP_24,Reserved for future use." newline hexmask.long.byte 0x8 16.--23. 1. "LATCHED_NFTS,Latched N_FTS. Indicates the value of N_FTS in the received TS Ordered Sets from the Link Partner Note: This register field is sticky." newline rbitfld.long 0x8 13.--15. "L1SUB_STATE,L1Sub State. Indicates internal state machine of L1Sub state. - 0h: S_L1_U : idle state - 1h: S_L1_0 : wait for aux_clk_active - 2h: S_L1_0_WAIT4_ACK : wait for pclkack - 3h: S_L1_0_WAIT4_CLKREQ : wait for clkreq - 4h: S_L1_N_ENTRY : check.." "wait for aux_clk_active,?,?,?,?,?,?,?" newline bitfld.long 0x8 12. "PME_RESEND_FLAG,PME Re-send flag. When the DUT sends a PM_PME message TLP the DUT sets PME_Status bit. If host software does not clear PME_Status bit for 100ms(+50%/-5%) the DUT resends the PM_PME Message. This bit indicates that a PM_PME was resent." "0,1" newline hexmask.long.byte 0x8 8.--11. 1. "INTERNAL_PM_SSTATE,Internal PM State(Slave). Indicates internal state machine of Power Management Slave controller. - 0h: S_IDLE - 1h: S_RESPOND_NAK - 2h: S_BLOCK_TLP - 3h: S_WAIT_LAST_TLP_ACK - 4h: S_WAIT_EIDLE - 5h: S_LINK_ENTR_L1 - 6h: S_L1 - 7h:.." newline rbitfld.long 0x8 5.--7. "RSVDP_5,Reserved for future use." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x8 0.--4. 1. "INTERNAL_PM_MSTATE,Internal PM State(Master). Indicates internal state machine of Power Management Master controller. - 00h: IDLE - 01h: L0 - 02h: L0S - 03h: ENTER_L0S - 04h: L0S_EXIT - 05h: WAIT_PMCSR_CPL_SENT - 08h: L1 - 09h: L1_BLOCK_TLP - 0Ah:.." rgroup.long (0xBC+0x30C)++0x3 line.long 0x0 "SD_STATUS_L2_REG,Silicon Debug Status(Layer2). For more details. see the RAS DES section in the Core Operations chapter of the Databook." hexmask.long.byte 0x0 28.--31. 1. "RSVDP_28,Reserved for future use." newline bitfld.long 0x0 27. "FC_INIT2,FC_INIT2. Indicates the controller is in FC_INIT2(VC0) state. Note: This register field is sticky." "0,1" newline bitfld.long 0x0 26. "FC_INIT1,FC_INIT1. Indicates the controller is in FC_INIT1(VC0) state. Note: This register field is sticky." "0,1" newline bitfld.long 0x0 24.--25. "DLCMSM,DLCMSM. Indicates the current DLCMSM. - 00b: DL_INACTIVE - 01b: DL_FC_INIT - 11b: DL_ACTIVE Note: This register field is sticky." "0,1,2,3" newline hexmask.long.word 0x0 12.--23. 1. "RX_ACK_SEQ_NO,Tx Ack Sequence Number. Indicates ACKD_SEQ which is updated by receiving ACK/NAK DLLP. Note: This register field is sticky." newline hexmask.long.word 0x0 0.--11. 1. "TX_TLP_SEQ_NO,Tx Tlp Sequence Number. Indicates next transmit sequence number for transmit TLP. Note: This register field is sticky." group.long (0xC0+0x30C)++0x7 line.long 0x0 "SD_STATUS_L3FC_REG,Silicon Debug Status(Layer3 FC). The CREDIT_DATA[0/1] fields in this viewport register return the data for the VC and TLP Type selected by the following fields: - CREDIT_SEL_VC - CREDIT_SEL_CREDIT_TYPE - CREDIT_SEL_TLP_TYPE -.." hexmask.long.word 0x0 20.--31. 1. "CREDIT_DATA1,Credit Data1. Current FC credit data selected by the CREDIT_SEL_VC CREDIT_SEL_CREDIT_TYPE CREDIT_SEL_TLP_TYPE and CREDIT_SEL_HD viewport-select fields. - Rx: Credit Allocated Value - Tx: Credit Limit Value. This value is valid when.." newline hexmask.long.word 0x0 8.--19. 1. "CREDIT_DATA0,Credit Data0. Current FC credit data selected by the CREDIT_SEL_VC CREDIT_SEL_CREDIT_TYPE CREDIT_SEL_TLP_TYPE and CREDIT_SEL_HD viewport-select fields. - Rx: Credit Received Value - Tx: Credit Consumed Value Note: This register field is.." newline rbitfld.long 0x0 7. "RSVDP_7,Reserved for future use." "0,1" newline bitfld.long 0x0 6. "CREDIT_SEL_HD,Credit Select(HeaderData). This field in conjunction with the CREDIT_SEL_VC CREDIT_SEL_CREDIT_TYPE and CREDIT_SEL_TLP_TYPE viewport-select fields determines that data that is returned by the CREDIT_DATA0 and CREDIT_DATA1 data fields. -.." "Header Credit,Data Credit" newline bitfld.long 0x0 4.--5. "CREDIT_SEL_TLP_TYPE,Credit Select(TLP Type). This field in conjunction with the CREDIT_SEL_VC CREDIT_SEL_CREDIT_TYPE and CREDIT_SEL_HD viewport-select fields determines that data that is returned by the CREDIT_DATA0 and CREDIT_DATA1 data fields. - 0x0:.." "Posted,Non-Posted,Completion,?" newline bitfld.long 0x0 3. "CREDIT_SEL_CREDIT_TYPE,Credit Select(Credit Type). This field in conjunction with the CREDIT_SEL_VC CREDIT_SEL_TLP_TYPE and CREDIT_SEL_HD viewport-select fields determines that data that is returned by the CREDIT_DATA0 and CREDIT_DATA1 data fields. -.." "Rx,Tx" newline bitfld.long 0x0 0.--2. "CREDIT_SEL_VC,Credit Select(VC). This field in conjunction with the CREDIT_SEL_CREDIT_TYPE CREDIT_SEL_TLP_TYPE and CREDIT_SEL_HD viewport-select fields determines that data that is returned by the CREDIT_DATA0 and CREDIT_DATA1 data fields. - 0x0: VC0 -.." "VC0,VC1,VC2,?,?,?,?,VC7" line.long 0x4 "SD_STATUS_L3_REG,Silicon Debug Status(Layer3). For more details. see the RAS DES section in the Core Operations chapter of the Databook." hexmask.long.tbyte 0x4 8.--31. 1. "RSVDP_8,Reserved for future use." newline bitfld.long 0x4 7. "MFTLP_STATUS,Malformed TLP Status. Indicates malformed TLP has occurred." "0,1" newline hexmask.long.byte 0x4 0.--6. 1. "MFTLP_POINTER,First Malformed TLP Error Pointer. Indicates the element of the received first malformed TLP. This pointer is validated by MFTLP_STATUS. - 01h: AtomicOp address alignment - 02h: AtomicOp operand - 03h: AtomicOp byte enable - 04h: TLP length.." group.long (0xD0+0x30C)++0xB line.long 0x0 "SD_EQ_CONTROL1_REG,Silicon Debug EQ Control 1. This is a viewport control register. Setting the EQ_RATE_SEL and EQ_LANE_SEL fields in this register determine the per-lane Silicon Debug EQ Status data returned by the SD_EQ_STATUS[1/2/3] viewport.." hexmask.long.byte 0x0 24.--31. 1. "FOM_TARGET,FOM Target. Indicates figure of merit target criteria value of EQ Master(DSP in EQ Phase3/USP in EQ Phase2). This field is only valid when GEN3_EQ_FB_MODE is 0001b(Figure Of Merit). Note: This register field is sticky." newline bitfld.long 0x0 23. "FOM_TARGET_ENABLE,FOM Target Enable. Enables the FOM_TARGET fields. Note: This register field is sticky." "0,1" newline hexmask.long.byte 0x0 18.--22. 1. "RSVDP_18,Reserved for future use." newline bitfld.long 0x0 16.--17. "EVAL_INTERVAL_TIME,Eval Interval Time. Indicates interval time of RxEqEval assertion. - 00: 500ns - 01: 1us - 10: 2us - 11: 4us This field is used for EQ Master(DSP in EQ Phase3/USP in EQ Phase2). Note: This register field is sticky." "0,1,2,3" newline hexmask.long.byte 0x0 10.--15. 1. "RSVDP_10,Reserved for future use." newline bitfld.long 0x0 8.--9. "EXT_EQ_TIMEOUT,Extends EQ Phase2/3 Timeout. This field is used when the Ltssm is in Recovery.EQ2/3. When this field is set the value of EQ2/3 timeout is extended. EQ Master(DSP in EQ Phase3/USP in EQ Phase2). - 00: 24ms (default) - 01: 48ms (x2) - 10:.." "0,1,2,3" newline rbitfld.long 0x0 6.--7. "RSVDP_6,Reserved for future use." "0,1,2,3" newline bitfld.long 0x0 4.--5. "EQ_RATE_SEL,EQ Status Rate Select. Setting this field in conjunction with the EQ_LANE_SEL field determines the per-lane Silicon Debug EQ Status data returned by the SD_EQ_CONTROL[2/3] and SD_EQ_STATUS[1/2/3] viewport registers. - 0x0: 8.0GT/s Speed.." "0,1,2,3" newline hexmask.long.byte 0x0 0.--3. 1. "EQ_LANE_SEL,EQ Status Lane Select. Setting this field in conjunction with the EQ_RATE_SEL field determines the per-lane Silicon Debug EQ Status data returned by the SD_EQ_CONTROL[2/3] and SD_EQ_STATUS[1/2/3] viewport registers. - 0x0: Lane0 - 0x1: Lane1.." line.long 0x4 "SD_EQ_CONTROL2_REG,Silicon Debug EQ Control 2. This viewport register returns the value for the rate and lane selected by the EQ_RATE_SEL and EQ_LANE_SEL fields in the SD_EQ_CONTROL1_REG register. For more details. see the RAS DES section in the Core.." rbitfld.long 0x4 31. "RSVDP_31,Reserved for future use." "0,1" newline bitfld.long 0x4 30. "FORCE_LOCAL_TX_PRESET_ENABLE,Force Local Transmitter Preset Enable. Enables the FORCE_LOCAL_TX_PRESET field. If select rate in the EQ_RATE_SEL field is 32.0GT/s Speed this feature is not available. Note: This register field is sticky." "0,1" newline bitfld.long 0x4 29. "FORCE_LOCAL_RX_HINT_ENABLE,Force Local Receiver Preset Hint Enable. Enables the FORCE_LOCAL_RX_HINT field. If select rate in the EQ_RATE_SEL field is other than 8.0GT/s Speed this feature is not available. Note: This register field is sticky." "0,1" newline bitfld.long 0x4 28. "FORCE_LOCAL_TX_COEF_ENABLE,Force Local Transmitter Coefficient Enable. Enables the following fields: - FORCE_LOCAL_TX_PRE_CURSOR - FORCE_LOCAL_TX_CURSOR - FORCE_LOCAL_TX_POST_CURSOR Note: This register field is sticky." "0,1" newline hexmask.long.byte 0x4 24.--27. 1. "FORCE_LOCAL_TX_PRESET,Force Local Transmitter Preset. Indicates initial preset value of USP in EQ Slave(EQ Phase2) instead of receiving EQ TS2. If select rate in the EQ_RATE_SEL field is 32.0GT/s Speed this feature is not available. Note: This register.." newline rbitfld.long 0x4 21.--23. "RSVDP_21,Reserved for future use." "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 18.--20. "FORCE_LOCAL_RX_HINT,Force Local Receiver Preset Hint. Indicates the RxPresetHint value of EQ Slave(DSP in EQ Phase2/USP in EQ Phase3) instead of received or set value. If select rate in the EQ_RATE_SEL field is other than 8.0GT/s Speed this feature is.." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x4 12.--17. 1. "FORCE_LOCAL_TX_POST_CURSOR,Force Local Transmitter Post-Cursor. Indicates the coefficient value of EQ Slave(DSP in EQ Phase2/USP in EQ Phase3) instead of the value instructed from link partner. Note: This register field is sticky." newline hexmask.long.byte 0x4 6.--11. 1. "FORCE_LOCAL_TX_CURSOR,Force Local Transmitter Cursor. Indicates the coefficient value of EQ Slave(DSP in EQ Phase2/USP in EQ Phase3) instead of the value instructed from link partner. Note: This register field is sticky." newline hexmask.long.byte 0x4 0.--5. 1. "FORCE_LOCAL_TX_PRE_CURSOR,Force Local Transmitter Pre-cursor. Indicates the coefficient value of EQ Slave(DSP in EQ Phase2/USP in EQ Phase3) instead of the value instructed from link partner. Note: This register field is sticky." line.long 0x8 "SD_EQ_CONTROL3_REG,Silicon Debug EQ Control 3. This viewport register returns the value for the rate and lane selected by the EQ_RATE_SEL and EQ_LANE_SEL fields in the SD_EQ_CONTROL1_REG register. For more details. see the RAS DES section in the Core.." rbitfld.long 0x8 29.--31. "RSVDP_29,Reserved for future use." "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 28. "FORCE_REMOTE_TX_COEF_ENABLE,Force Remote Transmitter Coefficient Enable. Enables the following fields: - FORCE_REMOTE_TX_PRE_CURSOR - FORCE_REMOTE_TX_CURSOR - FORCE_REMOTE_TX_POST_CURSOR This function can only be used when GEN3_EQ_FB_MODE =.." "0,1" newline hexmask.long.word 0x8 18.--27. 1. "RSVDP_18,Reserved for future use." newline hexmask.long.byte 0x8 12.--17. 1. "FORCE_REMOTE_TX_POST_CURSOR,Force Remote Transmitter Post-Cursor. Indicates the coefficient value of EQ Master(DSP in EQ Phase3/USP in EQ Phase2) instead of the value instructed from local phy in dirchange mode. Note: This register field is sticky." newline hexmask.long.byte 0x8 6.--11. 1. "FORCE_REMOTE_TX_CURSOR,Force Remote Transmitter Cursor. Indicates the coefficient value of EQ Master(DSP in EQ Phase3/USP in EQ Phase2) instead of the value instructed from local phy in dirchange mode. Note: This register field is sticky." newline hexmask.long.byte 0x8 0.--5. 1. "FORCE_REMOTE_TX_PRE_CURSOR,Force Remote Transmitter Pre-Cursor. Indicates the coefficient value of EQ Master(DSP in EQ Phase3/USP in EQ Phase2) instead of the value instructed from local phy in dirchange mode. Note: This register field is sticky." rgroup.long (0xE0+0x30C)++0xB line.long 0x0 "SD_EQ_STATUS1_REG,Silicon Debug EQ Status 1. This viewport register returns the first of three words of Silicon Debug EQ Status data for the rate and lane selected by the EQ_RATE_SEL and EQ_LANE_SEL fields in the SD_EQ_CONTROL1_REG register. The.." hexmask.long.tbyte 0x0 8.--31. 1. "RSVDP_8,Reserved for future use." newline bitfld.long 0x0 7. "EQ_REJECT_EVENT,EQ Reject Event. Indicates that the controller receives two consecutive TS1 OS w/Reject=1b during EQ Master phase(DSP in EQ Phase3/USP in EQ Phase2). This bit is automatically cleared when the controller starts EQ Master phase again." "0,1" newline bitfld.long 0x0 6. "EQ_RULEC_VIOLATION,EQ Rule C Violation. Indicates that coefficients rule C violation is detected in the values provided by PHY using direction change method during EQ Master phase(DSP in EQ Phase3/USP in EQ Phase2). The coefficients rule C correspond to.." "0,1" newline bitfld.long 0x0 5. "EQ_RULEB_VIOLATION,EQ Rule B Violation. Indicates that coefficients rule B violation is detected in the values provided by PHY using direction change method during EQ Master phase(DSP in EQ Phase3/USP in EQ Phase2). The coefficients rules B correspond to.." "0,1" newline bitfld.long 0x0 4. "EQ_RULEA_VIOLATION,EQ Rule A Violation. Indicates that coefficients rule A violation is detected in the values provided by PHY using direction change method during EQ Master phase(DSP in EQ Phase3/USP in EQ Phase2). The coefficients rules A correspond to.." "0,1" newline bitfld.long 0x0 3. "RSVDP_3,Reserved for future use." "0,1" newline bitfld.long 0x0 1.--2. "EQ_CONVERGENCE_INFO,EQ Convergence Info. Indicates equalization convergence information. - 0x0: Equalization is not attempted - 0x1: Equalization finished successfully - 0x2: Equalization finished unsuccessfully - 0x3: Reserved This bit is automatically.." "Equalization is not attempted,Equalization finished successfully,Equalization finished unsuccessfully,Reserved" newline bitfld.long 0x0 0. "EQ_SEQUENCE,EQ Sequence. Indicates that the controller is starting the equalization sequence. Note: This register field is sticky." "0,1" line.long 0x4 "SD_EQ_STATUS2_REG,Silicon Debug EQ Status 2. This viewport register returns the second of three words of Silicon Debug EQ Status data for the rate and lane selected by the EQ_RATE_SEL and EQ_LANE_SEL fields in the SD_EQ_CONTROL1_REG register. Each field.." hexmask.long.byte 0x4 24.--31. 1. "EQ_LOCAL_FOM_VALUE,EQ Local Figure of Merit. Indicates Local maximum Figure of Merit value. Note: This register field is sticky." newline bitfld.long 0x4 21.--23. "RSVDP_21,Reserved for future use." "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 18.--20. "EQ_LOCAL_RX_HINT,EQ Local Receiver Preset Hint. Indicates Local Receiver Preset Hint value. If select rate in the EQ_RATE_SEL field is other than 8.0GT/s Speed this feature is not available. Note: This register field is sticky." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x4 12.--17. 1. "EQ_LOCAL_POST_CURSOR,EQ Local Post-Cursor. Indicates Local post cursor coefficient value. Note: This register field is sticky." newline hexmask.long.byte 0x4 6.--11. 1. "EQ_LOCAL_CURSOR,EQ Local Cursor. Indicates Local cursor coefficient value. Note: This register field is sticky." newline hexmask.long.byte 0x4 0.--5. 1. "EQ_LOCAL_PRE_CURSOR,EQ Local Pre-Cursor. Indicates Local pre cursor coefficient value. Note: This register field is sticky." line.long 0x8 "SD_EQ_STATUS3_REG,Silicon Debug EQ Status 3. This viewport register returns the third of three words of Silicon Debug EQ Status data for the rate and lane selected by the EQ_RATE_SEL and EQ_LANE_SEL fields in the SD_EQ_CONTROL1_REG register. Each field.." bitfld.long 0x8 30.--31. "RSVDP_30,Reserved for future use." "0,1,2,3" newline hexmask.long.byte 0x8 24.--29. 1. "EQ_REMOTE_FS,EQ Remote FS. Indicates Remote FS value. Note: This register field is sticky." newline hexmask.long.byte 0x8 18.--23. 1. "EQ_REMOTE_LF,EQ Remote LF. Indicates Remote LF value. Note: This register field is sticky." newline hexmask.long.byte 0x8 12.--17. 1. "EQ_REMOTE_POST_CURSOR,EQ Remote Post-Cursor. Indicates Remote post cursor coefficient value. Note: This register field is sticky." newline hexmask.long.byte 0x8 6.--11. 1. "EQ_REMOTE_CURSOR,EQ Remote Cursor. Indicates Remote cursor coefficient value. Note: This register field is sticky." newline hexmask.long.byte 0x8 0.--5. 1. "EQ_REMOTE_PRE_CURSOR,EQ Remote Pre-Cursor. Indicates Remote pre cursor coefficient value. Note: This register field is sticky." tree.end tree "PF0_SN_CAP (Device Serial Number Capability Structure)" group.long (0x0+0x170)++0xB line.long 0x0 "SN_BASE,Device Serial Number Extended Capability Header. For a description of this standard PCIe register. see the PCI Express Base Specification." hexmask.long.word 0x0 20.--31. 1. "SN_NEXT_OFFSET,Next Capability Offset. For a description of this standard PCIe register field see the PCI Express Base Specification. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then.." hexmask.long.byte 0x0 16.--19. 1. "SN_CAP_VERSION,Capability Version. For a description of this standard PCIe register field see the PCI Express Base Specification. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky).." hexmask.long.word 0x0 0.--15. 1. "SN_PCIE_EXTENDED_CAP_ID,Serial Number Extended Capability ID. For a description of this standard PCIe register field see the PCI Express Base Specification. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if.." line.long 0x4 "SER_NUM_REG_DW_1,Serial Number 1 Register. For a description of this standard PCIe register. see the PCI Express Base Specification." hexmask.long 0x4 0.--31. 1. "SN_SER_NUM_REG_1_DW,IEEE 64 bit Device Serial Number (DW 1). For a description of this standard PCIe register field see the PCI Express Base Specification. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if.." line.long 0x8 "SER_NUM_REG_DW_2,Serial Number 2 Register. For a description of this standard PCIe register. see the PCI Express Base Specification." hexmask.long 0x8 0.--31. 1. "SN_SER_NUM_REG_2_DW,IEEE 64 bit Device Serial Number (DW 2). For a description of this standard PCIe register field see the PCI Express Base Specification. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if.." tree.end tree "PF0_VSECRAS_CAP (PF RAS Datapath Protection Capability Structure (VSEC))" group.long (0x0+0x480)++0x3 line.long 0x0 "RASDP_EXT_CAP_HDR_OFF,PCIe Extended capability ID. Capability version and Next capability offset. For a description of this standard PCIe register. see the PCI Express Specification." hexmask.long.word 0x0 20.--31. 1. "NEXT_OFFSET,Next Capability Offset. For a description of this standard PCIe register see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else.." newline hexmask.long.byte 0x0 16.--19. 1. "CAP,Capability Version. For a description of this standard PCIe register see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note:.." newline hexmask.long.word 0x0 0.--15. 1. "ID,PCI Express Extended Capability ID. For a description of this standard PCIe register see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else.." rgroup.long (0x4+0x480)++0x3 line.long 0x0 "RASDP_VENDOR_SPECIFIC_HDR_OFF,Vendor Specific Header. For a description of this standard PCIe register. see the PCI Express Specification." hexmask.long.word 0x0 20.--31. 1. "VSEC_LENGTH,VSEC Length. For a description of this standard PCIe register see the PCI Express Specification. Note: This register field is sticky." newline hexmask.long.byte 0x0 16.--19. 1. "VSEC_REV,VSEC Rev. For a description of this standard PCIe register see the PCI Express Specification. Note: This register field is sticky." newline hexmask.long.word 0x0 0.--15. 1. "VSEC_ID,VSEC ID. For a description of this standard PCIe register see the PCI Express Specification. Note: This register field is sticky." group.long (0x8+0x480)++0x7 line.long 0x0 "RASDP_ERROR_PROT_CTRL_OFF,ECC error correction control. Allows you to disable ECC error correction for RAMs and datapath. When the AXI Bridge Module is implemented and the master / slave clocks are asynchronous to the PCIe native controller clock.." hexmask.long.byte 0x0 24.--31. 1. "RSVDP_24,Reserved for future use." newline bitfld.long 0x0 23. "ERROR_PROT_DISABLE_CXS_RX,Error correction disable for CXS Tx path (PCIe Rx path). Note: This register field is sticky." "0,1" newline bitfld.long 0x0 22. "ERROR_PROT_DISABLE_ADM_RX,Error correction disable for ADM Rx path. Note: This register field is sticky." "0,1" newline bitfld.long 0x0 21. "ERROR_PROT_DISABLE_LAYER3_RX,Error correction disable for layer 3 Rx path. Note: This register field is sticky." "0,1" newline bitfld.long 0x0 20. "ERROR_PROT_DISABLE_LAYER2_RX,Error correction disable for layer 2 Rx path. Note: This register field is sticky." "0,1" newline bitfld.long 0x0 19. "ERROR_PROT_DISABLE_DMA_READ,Error correction disable for DMA read engine. Note: This register field is sticky." "0,1" newline bitfld.long 0x0 18. "ERROR_PROT_DISABLE_AXI_BRIDGE_INBOUND_REQUEST,Error correction disable for AXI bridge inbound request path. Note: This register field is sticky." "0,1" newline bitfld.long 0x0 17. "ERROR_PROT_DISABLE_AXI_BRIDGE_INBOUND_COMPLETION,Error correction disable for AXI bridge inbound completion composer. Does not disable the error detection reporting for 1-bit and 2-bit ECC errors. Note: This register field is sticky." "?,bit and 2-bit ECC errors" newline bitfld.long 0x0 16. "ERROR_PROT_DISABLE_RX,Global error correction disable for all Rx layers. Note: This register field is sticky." "0,1" newline hexmask.long.byte 0x0 9.--15. 1. "RSVDP_9,Reserved for future use." newline bitfld.long 0x0 8. "ERROR_PROT_DISABLE_DTIM_TX,Error correction disable for DTIM Tx path. Note: This register field is sticky." "0,1" newline bitfld.long 0x0 7. "ERROR_PROT_DISABLE_CXS_TX,Error correction disable for CXS Rx path (PCIe Tx path). Note: This register field is sticky." "0,1" newline bitfld.long 0x0 6. "ERROR_PROT_DISABLE_ADM_TX,Error correction disable for Adm Tx path. Note: This register field is sticky." "0,1" newline bitfld.long 0x0 5. "ERROR_PROT_DISABLE_LAYER3_TX,Error correction disable for layer 3 Tx path. Note: This register field is sticky." "0,1" newline bitfld.long 0x0 4. "ERROR_PROT_DISABLE_LAYER2_TX,Error correction disable for layer 2 Tx path. Note: This register field is sticky." "0,1" newline bitfld.long 0x0 3. "ERROR_PROT_DISABLE_DMA_WRITE,Error correction disable for DMA write engine. Note: This register field is sticky." "0,1" newline bitfld.long 0x0 2. "ERROR_PROT_DISABLE_AXI_BRIDGE_OUTBOUND,Error correction disable for AXI bridge outbound request path. Note: This register field is sticky." "0,1" newline bitfld.long 0x0 1. "ERROR_PROT_DISABLE_AXI_BRIDGE_MASTER,Error correction disable for AXI bridge master completion buffer. Note: This register field is sticky." "0,1" newline bitfld.long 0x0 0. "ERROR_PROT_DISABLE_TX,Global error correction disable for all Tx layers. Does not disable the error detection reporting for 1-bit and 2-bit ECC errors. Note: This register field is sticky." "?,bit and 2-bit ECC errors" line.long 0x4 "RASDP_CORR_COUNTER_CTRL_OFF,Corrected error (1-bit ECC) counter selection and control. This is a viewport control register. Setting the CORR_COUNTER_SELECTION_REGION and CORR_COUNTER_SELECTION fields in this register determine the counter data returned.." hexmask.long.byte 0x4 24.--31. 1. "CORR_COUNTER_SELECTION,Counter selection. This field selects the counter ID (within the region defined by CORR_COUNTER_SELECTION_REGION) whose contents can be read from the RASDP_CORR_COUNT_REPORT_OFF register. You can cycle this field value from 0 to.." newline hexmask.long.byte 0x4 20.--23. 1. "CORR_COUNTER_SELECTION_REGION,Select correctable counter region: - 0x0: Region select for Adm Rx path - 0x1: Region select for layer 3 Rx path - 0x2: Region select for layer 2 Rx path - 0x3: Region select for DMA inbound path - 0x4: Region select for AXI.." newline hexmask.long.word 0x4 5.--19. 1. "RSVDP_5,Reserved for future use." newline bitfld.long 0x4 4. "CORR_EN_COUNTERS,Enable correctable errors counters. - 1: counters increment when the controller detects a correctable error - 0: counters are frozen The counters are enabled by default." "counters are frozen,counters increment when the controller detects a.." newline rbitfld.long 0x4 1.--3. "RSVDP_1,Reserved for future use." "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 0. "CORR_CLEAR_COUNTERS,Clear all correctable error counters." "0,1" rgroup.long (0x10+0x480)++0x3 line.long 0x0 "RASDP_CORR_COUNT_REPORT_OFF,Corrected error (1-bit ECC) counter data. This viewport register returns the counter data selected by the CORR_COUNTER_SELECTION_REGION and CORR_COUNTER_SELECTION fields in the RASDP_CORR_COUNTER_CTRL_OFF register." hexmask.long.byte 0x0 24.--31. 1. "CORR_COUNTER_SELECTED,Counter selection. Returns the value set in the CORR_COUNTER_SELECTION field of the RASDP_CORR_COUNTER_CTRL_OFF register." newline hexmask.long.byte 0x0 20.--23. 1. "CORR_COUNTER_SELECTED_REGION,Selected correctable counter region: - 0x0: Region select for Adm Rx path - 0x1: Region select for layer 3 Rx path - 0x2: Region select for layer 2 Rx path - 0x3: Region select for DMA inbound path - 0x4: Region select for.." newline hexmask.long.word 0x0 8.--19. 1. "RSVDP_8,Reserved for future use." newline hexmask.long.byte 0x0 0.--7. 1. "CORR_COUNTER,Current corrected error count for the selected counter." group.long (0x14+0x480)++0x3 line.long 0x0 "RASDP_UNCORR_COUNTER_CTRL_OFF,Uncorrected error (2-bit ECC and parity) counter selection and control. This is a viewport control register. Setting the UNCORR_COUNTER_SELECTION_REGION and UNCORR_COUNTER_SELECTION fields in this register determine the.." hexmask.long.byte 0x0 24.--31. 1. "UNCORR_COUNTER_SELECTION,Counter selection. This field selects the counter ID (within the region defined by UNCORR_COUNTER_SELECTION_REGION) whose contents can be read from the RASDP_UNCORR_COUNT_REPORT_OFF register. You can cycle this field value from 0.." newline hexmask.long.byte 0x0 20.--23. 1. "UNCORR_COUNTER_SELECTION_REGION,Select uncorrectable counter region: - 0x0: Region select for Adm Rx path - 0x1: Region select for layer 3 Rx path - 0x2: Region select for layer 2 Rx path - 0x3: Region select for DMA inbound path - 0x4: Region select for.." newline hexmask.long.word 0x0 5.--19. 1. "RSVDP_5,Reserved for future use." newline bitfld.long 0x0 4. "UNCORR_EN_COUNTERS,Enable uncorrectable errors counters. - 1: enables the counters to increment on detected correctable errors - 0: counters are frozen The counters are enabled by default." "counters are frozen,enables the counters to increment on detected.." newline rbitfld.long 0x0 1.--3. "RSVDP_1,Reserved for future use." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 0. "UNCORR_CLEAR_COUNTERS,Clear uncorrectable errors counters. When asserted causes all counters tracking the uncorrectable errors to be cleared." "0,1" rgroup.long (0x18+0x480)++0x3 line.long 0x0 "RASDP_UNCORR_COUNT_REPORT_OFF,Uncorrected error (2-bit ECC and parity) counter data. This viewport register returns the counter data selected by the UNCORR_COUNTER_SELECTION_REGION and UNCORR_COUNTER_SELECTION fields in the RASDP_UNCORR_COUNTER_CTRL_OFF.." hexmask.long.byte 0x0 24.--31. 1. "UNCORR_COUNTER_SELECTED,Counter selection. Returns the value set in the UNCORR_COUNTER_SELECTION field of the RASDP_UNCORR_COUNTER_CTRL_OFF register." newline hexmask.long.byte 0x0 20.--23. 1. "UNCORR_COUNTER_SELECTED_REGION,Selected uncorrectable counter region: - 0x0: Region select for Adm Rx path - 0x1: Region select for layer 3 Rx path - 0x2: Region select for layer 2 Rx path - 0x3: Region select for DMA inbound path - 0x4: Region select.." newline hexmask.long.word 0x0 8.--19. 1. "RSVDP_8,Reserved for future use." newline hexmask.long.byte 0x0 0.--7. 1. "UNCORR_COUNTER,Current uncorrected error count for the selected counter" group.long (0x1C+0x480)++0x3 line.long 0x0 "RASDP_ERROR_INJ_CTRL_OFF,Error injection control for the following features: - 1-bit or 2-bit injection - Continuous or fixed-number (n) injection modes - Global enable/disable - Selectable location where injection occurs" hexmask.long.byte 0x0 24.--31. 1. "RSVDP_24,Reserved for future use." newline hexmask.long.byte 0x0 16.--23. 1. "ERROR_INJ_LOC,Error injection location. Selects where error injection takes place. You can cycle this field value from 0 to 255 to access all locations according to the detailed report of check points at.." newline hexmask.long.byte 0x0 8.--15. 1. "ERROR_INJ_COUNT,Error injection count. - 0: errors are inserted in every TLP until you clear ERROR_INJ_EN. - 1: one errors injected - 2: two errors injected - n: amount of errors injected" newline rbitfld.long 0x0 6.--7. "RSVDP_6,Reserved for future use." "0,1,2,3" newline bitfld.long 0x0 4.--5. "ERROR_INJ_TYPE,Error injection type: - 0: none - 1: 1-bit - 2: 2-bit" "none,bit,bit,?" newline rbitfld.long 0x0 1.--3. "RSVDP_1,Reserved for future use." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 0. "ERROR_INJ_EN,Error injection global enable. When set enables the error insertion logic." "0,1" rgroup.long (0x20+0x480)++0x7 line.long 0x0 "RASDP_CORR_ERROR_LOCATION_OFF,Corrected errors locations. For more details. see the RAS Data Protection (DP) section in the Core Operations chapter of the Databook." hexmask.long.byte 0x0 24.--31. 1. "LOC_LAST_CORR_ERROR,Location/ID of the last corrected error within the region defined by REG_LAST_CORR_ERROR. You can cycle this field value from 0 to 255 to access all counters according to the detailed report of check points at.." newline hexmask.long.byte 0x0 20.--23. 1. "REG_LAST_CORR_ERROR,Region of the last corrected error: - 0x0: Region select for Adm Rx path - 0x1: Region select for layer 3 Rx path - 0x2: Region select for layer 2 Rx path - 0x3: Region select for DMA inbound path - 0x4: Region select for AXI bridge.." newline hexmask.long.byte 0x0 16.--19. 1. "RSVDP_16,Reserved for future use." newline hexmask.long.byte 0x0 8.--15. 1. "LOC_FIRST_CORR_ERROR,Location/ID of the first corrected error within the region defined by REG_FIRST_CORR_ERROR. You can cycle this field value from 0 to 255 to access all counters according to the detailed report of check points at.." newline hexmask.long.byte 0x0 4.--7. 1. "REG_FIRST_CORR_ERROR,Region of the first corrected error: - 0x0: Region select for Adm Rx path - 0x1: Region select for layer 3 Rx path - 0x2: Region select for layer 2 Rx path - 0x3: Region select for DMA inbound path - 0x4: Region select for AXI bridge.." newline hexmask.long.byte 0x0 0.--3. 1. "RSVDP_0,Reserved for future use." line.long 0x4 "RASDP_UNCORR_ERROR_LOCATION_OFF,Uncorrected errors locations. For more details. see the RAS Data Protection (DP) section in the Core Operations chapter of the Databook." hexmask.long.byte 0x4 24.--31. 1. "LOC_LAST_UNCORR_ERROR,Location/ID of the last uncorrected error within the region defined by REG_LAST_UNCORR_ERROR. You can cycle this field value from 0 to 255 to access all counters according to the detailed report of check points at.." newline hexmask.long.byte 0x4 20.--23. 1. "REG_LAST_UNCORR_ERROR,Region of the last uncorrected error: - 0x0: Region select for Adm Rx path - 0x1: Region select for layer 3 Rx path - 0x2: Region select for layer 2 Rx path - 0x3: Region select for DMA inbound path - 0x4: Region select for AXI.." newline hexmask.long.byte 0x4 16.--19. 1. "RSVDP_16,Reserved for future use." newline hexmask.long.byte 0x4 8.--15. 1. "LOC_FIRST_UNCORR_ERROR,Location/ID of the first uncorrected error within the region defined by REG_FIRST_UNCORR_ERROR. You can cycle this field value from 0 to 255 to access all counters according to the detailed report of check points at.." newline hexmask.long.byte 0x4 4.--7. 1. "REG_FIRST_UNCORR_ERROR,Region of the first uncorrected error: - 0x0: Region select for Adm Rx path - 0x1: Region select for layer 3 Rx path - 0x2: Region select for layer 2 Rx path - 0x3: Region select for DMA inbound path - 0x4: Region select for AXI.." newline hexmask.long.byte 0x4 0.--3. 1. "RSVDP_0,Reserved for future use." group.long (0x28+0x480)++0x7 line.long 0x0 "RASDP_ERROR_MODE_EN_OFF,RASDP error mode enable. The controller enters RASDP error mode (if ERROR_MODE_EN =1) upon detection of the first uncorrectable error. During this mode: - Rx TLPs that are forwarded to your application are not guaranteed to be.." hexmask.long 0x0 2.--31. 1. "RSVDP_2,Reserved for future use." newline bitfld.long 0x0 1. "AUTO_LINK_DOWN_EN,Write '1' to enable the controller to bring the link down when the controller enters RASDP error mode. Note: This register field is sticky." "0,1" newline bitfld.long 0x0 0. "ERROR_MODE_EN,Write '1' to enable the controller enter RASDP error mode when it detects an uncorrectable error. Note: This register field is sticky." "0,1" line.long 0x4 "RASDP_ERROR_MODE_CLEAR_OFF,Exit RASDP error mode. For more details. see the RAS Data Protection (DP) section in the Core Operations chapter of the Databook." hexmask.long 0x4 1.--31. 1. "RSVDP_1,Reserved for future use." newline bitfld.long 0x4 0. "ERROR_MODE_CLEAR,Write '1' to take the controller out of RASDP error mode. The controller will then report uncorrectable errors (through AER internal error reporting) and also stop nullifying/discarding TLPs." "0,1" rgroup.long (0x30+0x480)++0x7 line.long 0x0 "RASDP_RAM_ADDR_CORR_ERROR_OFF,RAM Address where a corrected error (1-bit ECC) has been detected. For more details. see the RAS Data Protection (DP) section in the Core Operations chapter of the Databook." hexmask.long.byte 0x0 28.--31. 1. "RAM_INDEX_CORR_ERROR,RAM index where a corrected error (1-bit ECC) has been detected." newline bitfld.long 0x0 27. "RSVDP_27,Reserved for future use." "0,1" newline hexmask.long 0x0 0.--26. 1. "RAM_ADDR_CORR_ERROR,RAM Address where a corrected error (1-bit ECC) has been detected." line.long 0x4 "RASDP_RAM_ADDR_UNCORR_ERROR_OFF,RAM Address where an uncorrected error (2-bit ECC) has been detected. For more details. see the RAS Data Protection (DP) section in the Core Operations chapter of the Databook." hexmask.long.byte 0x4 28.--31. 1. "RAM_INDEX_UNCORR_ERROR,RAM index where an uncorrected error (2-bit ECC) has been detected." newline bitfld.long 0x4 27. "RSVDP_27,Reserved for future use." "0,1" newline hexmask.long 0x4 0.--26. 1. "RAM_ADDR_UNCORR_ERROR,RAM Address where an uncorrected error (2-bit ECC) has been detected." tree.end tree "PF0_RTR_CAP (PF RTR Capability Structure)" group.long (0x0+0x2F8)++0xB line.long 0x0 "RTR_EXT_CAP_HDR_OFF,Readiness Time Reporting PCI Express Extended Capability Header. For a description of this standard PCIe register. see the PCI Express Specification." hexmask.long.word 0x0 20.--31. 1. "RTR_NEXT_OFFSET,Next Capability Offset. For a description of this standard PCIe register field see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky).." hexmask.long.byte 0x0 16.--19. 1. "RTR_CAP_VERSION,Capability Version. For a description of this standard PCIe register field see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky).." hexmask.long.word 0x0 0.--15. 1. "RTR_EXT_CAP_ID,PCI Express Extended Capability ID. For a description of this standard PCIe register field see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then.." line.long 0x4 "READI_TIME_REPORTING1_OFF,Readiness Time Reporting 1. For a description of this standard PCIe register. see the PCI Express Specification." bitfld.long 0x4 31. "RTR_TIME_VALID,Valid. For a description of this standard PCIe register field see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky)" "0,1" hexmask.long.byte 0x4 24.--30. 1. "RSVDP_24,Reserved for future use." hexmask.long.word 0x4 12.--23. 1. "DL_UP_TIME,DL_UP Time. For a description of this standard PCIe register field see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky)" hexmask.long.word 0x4 0.--11. 1. "RESET_TIME,Reset Time. For a description of this standard PCIe register field see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky)" line.long 0x8 "READI_TIME_REPORTING2_OFF,Readiness Time Reporting 2. For a description of this standard PCIe register. see the PCI Express Specification." hexmask.long.byte 0x8 24.--31. 1. "RSVDP_24,Reserved for future use." hexmask.long.word 0x8 12.--23. 1. "D3HOT_D0_TIME,D3hot to D0 Time. For a description of this standard PCIe register field see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else.." hexmask.long.word 0x8 0.--11. 1. "FLR_TIME,FLR Time. For a description of this standard PCIe register field see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky)" tree.end tree "PF0_RTR_CAP_DBI2 (DBI2 Shadow Block: PF RTR Capability Structure)" rgroup.long (0x4+0x12F8)++0x7 line.long 0x0 "SHADOW_READI_TIME_REPORTING1_OFF,Shadow Register Readiness Time Reporting 1. For a description of this standard PCIe register. see the PCI Express Specification." bitfld.long 0x0 31. "RTR_TIME_VALID,Shadow Valid in the shadow register. For a description of this standard PCIe register field see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access - Dbi: No access - Dbi2: if.." "0,1" hexmask.long.tbyte 0x0 12.--30. 1. "RSVDP_12,Reserved for future use." hexmask.long.word 0x0 0.--11. 1. "RESET_TIME,Shadow Reset Time in the shadow register. For a description of this standard PCIe register field see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access - Dbi: No access - Dbi2: if.." line.long 0x4 "SHADOW_READI_TIME_REPORTING2_OFF,Shadow Register Readiness Time Reporting 2. For a description of this standard PCIe register. see the PCI Express Specification." hexmask.long.byte 0x4 24.--31. 1. "RSVDP_24,Reserved for future use." hexmask.long.word 0x4 12.--23. 1. "D3HOT_D0_TIME,Shadow D3hot to D0 Time in the shadow register. For a description of this standard PCIe register field see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access - Dbi: No access - Dbi2:.." hexmask.long.word 0x4 0.--11. 1. "FLR_TIME,Shadow FLR Time in the shadow register. For a description of this standard PCIe register field see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access - Dbi: No access - Dbi2: if.." tree.end tree "PF0_FRSQ_CAP (PF FRSQ Capability Structure)" group.long (0x0+0x2E8)++0xB line.long 0x0 "FRSQ_EXT_CAP_HDR_OFF,FRS Queuing Extended Capability Header. For a description of this standard PCIe register. see the PCI Express Specification." hexmask.long.word 0x0 20.--31. 1. "FRSQ_NEXT_OFFSET,Next Capability Offset. For a description of this standard PCIe register field see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then.." hexmask.long.byte 0x0 16.--19. 1. "FRSQ_CAP_VERSION,Capability Version. For a description of this standard PCIe register field see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky).." hexmask.long.word 0x0 0.--15. 1. "FRSQ_EXT_CAP_ID,PCI Express Extended Capability ID. For a description of this standard PCIe register field see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then.." line.long 0x4 "FRSQ_CAP_OFF,FRS Queuing Capability Register. For a description of this standard PCIe register. see the PCI Express Specification." hexmask.long.word 0x4 21.--31. 1. "RSVDP_21,Reserved for future use." hexmask.long.byte 0x4 16.--20. 1. "FRS_INT_MESSAGE_NUMBER,FRS Interrupt Message Number. For a description of this standard PCIe register field see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1).." hexmask.long.byte 0x4 12.--15. 1. "RSVDP_12,Reserved for future use." hexmask.long.word 0x4 0.--11. 1. "FRSQ_MAX_DEPTH,FRS Queue Max Depth. For a description of this standard PCIe register field see the PCI Express Specification." line.long 0x8 "FRSQ_CONTROL_FRSQ_STATUS_OFF,FRS Queuing Status and Control Register. For a description of this standard PCIe register. see the PCI Express Specification." hexmask.long.word 0x8 17.--31. 1. "RSVDP_17,Reserved for future use." bitfld.long 0x8 16. "FRS_INTERRUPT_ENABLE,FRS Interrupt Enable. For a description of this standard PCIe register field see the PCI Express Specification." "0,1" hexmask.long.word 0x8 2.--15. 1. "RSVDP_2,Reserved for future use." bitfld.long 0x8 1. "FRS_MESSAGE_OVERFLOW,FRS Message Overflow. For a description of this standard PCIe register field see the PCI Express Specification." "0,1" newline bitfld.long 0x8 0. "FRS_MESSAGE_RECEIVED,FRS Message Received. For a description of this standard PCIe register field see the PCI Express Specification." "0,1" rgroup.long (0xC+0x2E8)++0x3 line.long 0x0 "FRS_MESSAGE_QUEUE_OFF,FRS Message Queue Register. For a description of this standard PCIe register. see the PCI Express Specification." hexmask.long.word 0x0 20.--31. 1. "FRS_MESSAGE_QUE_DEPTH,FRS Message Queue Depth. For a description of this standard PCIe register field see the PCI Express Specification." hexmask.long.byte 0x0 16.--19. 1. "FRS_MESSAGE_QUE_REASON,FRS Message Queue Reason. For a description of this standard PCIe register field see the PCI Express Specification." hexmask.long.word 0x0 0.--15. 1. "FRS_MESSAGE_QUE_FUNC_ID,FRS Message Queue Function ID. For a description of this standard PCIe register field see the PCI Express Specification." tree.end tree "PF0_PTM_CAP (PF PTM Capability Structure)" group.long (0x0+0x40C)++0xB line.long 0x0 "PTM_EXT_CAP_HDR_OFF,Precision Time Measurement Capability Header. For a description of this standard PCIe register. see the PCI Express Specification." hexmask.long.word 0x0 20.--31. 1. "PTM_NEXT_OFFSET,Precision Time Measurement PCI Express Extended Capability Next Offset. For a description of this standard PCIe register see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access. -.." hexmask.long.byte 0x0 16.--19. 1. "PTM_CAP_VERSION,Precision Time Measurement PCI Express Extended Capability Version. For a description of this standard PCIe register see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi:.." hexmask.long.word 0x0 0.--15. 1. "PTM_CAP_ID,Precision Time Measurement PCI Express Extended Capability ID. For a description of this standard PCIe register see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if.." line.long 0x4 "PTM_CAP_OFF,PTM Capability Register. For a description of this standard PCIe register. see the PCI Express Specification." hexmask.long.word 0x4 16.--31. 1. "RSVDP_16,Reserved for future use." hexmask.long.byte 0x4 8.--15. 1. "PTM_CLK_GRAN,PTM Local Clock Granularity. For a description of this standard PCIe register see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky).." hexmask.long.byte 0x4 3.--7. 1. "RSVDP_3,Reserved for future use." bitfld.long 0x4 2. "PTM_ROOT_CAPABLE,PTM Root Capable. For a description of this standard PCIe register see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else.." "0,1" bitfld.long 0x4 1. "PTM_RES_CAPABLE,PTM Responder Capable. For a description of this standard PCIe register see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else.." "0,1" newline bitfld.long 0x4 0. "PTM_REQ_CAPABLE,PTM Requester Capable. For a description of this standard PCIe register see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else.." "0,1" line.long 0x8 "PTM_CONTROL_OFF,PTM Control Register. For a description of this standard PCIe register. see the PCI Express Specification." hexmask.long.word 0x8 16.--31. 1. "RSVDP_16,Reserved for future use." hexmask.long.byte 0x8 8.--15. 1. "EFF_GRAN,PTM Effective Granularity. For a description of this standard PCIe register see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: HWINIT" hexmask.long.byte 0x8 2.--7. 1. "RSVDP_2,Reserved for future use." rbitfld.long 0x8 1. "ROOT_SELECT,PTM Root Select. When set this Time Source is the PTM Root. For a description of this standard PCIe register see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: HWINIT" "0,1" bitfld.long 0x8 0. "PTM_ENABLE,PTM Enable. When set this function is permitted to participate in the PTM mechanism. For a description of this standard PCIe register see the PCI Express Specification." "0,1" tree.end tree "PF0_PTM_RES_CAP (PF PTM Responder Capability Structure (VSEC))" group.long (0x0+0x418)++0xB line.long 0x0 "PTM_RES_CAP_HDR_OFF,Precision Time Measurement Responder Capability Header (VSEC). For more details. see the PTM section in the Databook." hexmask.long.word 0x0 20.--31. 1. "PTM_RES_EXT_CAP_NEXT_OFFS,Precision Time Measurement Responder VSEC Next Pointer. For more details see the PTM section in the Databook. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then.." hexmask.long.byte 0x0 16.--19. 1. "PTM_RES_EXT_CAP_VER,Precision Time Measurement Responder VSEC Version. For more details see the PTM section in the Databook. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else.." hexmask.long.word 0x0 0.--15. 1. "PTM_RES_EXT_CAP_ID,Precision Time Measurement Responder VSEC ID. For more details see the PTM section in the Databook. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else.." line.long 0x4 "PTM_RES_HDR_OFF,Precision Time Measurement Responder Vendor Specific Header. For more details. see the PTM section in the Databook." hexmask.long.word 0x4 20.--31. 1. "PTM_RES_VSEC_LENGTH,PTM Responder VSEC Length. For more details see the PTM section in the Databook. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This.." hexmask.long.byte 0x4 16.--19. 1. "PTM_RES_VSEC_REV,PTM Responder VSEC Revision. For more details see the PTM section in the Databook. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This.." hexmask.long.word 0x4 0.--15. 1. "PTM_RES_VSEC_ID,PTM Responder VSEC ID. For more details see the PTM section in the Databook. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register.." line.long 0x8 "PTM_RES_CONTROL_OFF,PTM Responder Control Register. For more details. see the PTM section in the Databook." hexmask.long 0x8 2.--31. 1. "RSVDP_2,Reserved for future use." bitfld.long 0x8 1. "PTM_RES_PDEL_BYTE_REV,PTM Requester Propagation Delay Byte Reversal - Reverse the order of bytes in the PTM Propagation Delay data word of the PTM ResponseD Message for compatibility with previous revisions. For more details see the PTM section in the.." "0,1" bitfld.long 0x8 0. "PTM_RES_CCONTEXT_VALID,PTM Responder Control Context Valid - PTM Local Timing is valid. This bit is set over the DBI. A speed change or aux_clk_active will set this bit low. For more details see the PTM section in the Databook. Note: The access.." "0,1" rgroup.long (0xC+0x418)++0x3 line.long 0x0 "PTM_RES_STATUS_OFF,PTM Responder Status Register. For more details. see the PTM section in the Databook." hexmask.long 0x0 2.--31. 1. "RSVDP_2,Reserved for future use." bitfld.long 0x0 1. "PTM_RES_REQUEST_RECEIVED,PTM 1st Request Received - PTM Responder has received the first PTM Request Message. Upon receipt of a second PTM Request Message a ResponseD message with timing information will be sent from the Responder if the context is.." "0,1" bitfld.long 0x0 0. "PTM_RES_CONTEXT_VALID,PTM Responder Status Context Valid - PTM Local Timing Context is Valid. Value set from upstream port Requester in a Switch. Shadows the same in the control register in all other products. For more details see the PTM section in the.." "0,1" group.long (0x10+0x418)++0x7 line.long 0x0 "PTM_RES_LOCAL_LSB_OFF,PTM Responder Local Clock LSB. For more details. see the PTM section in the Databook." hexmask.long 0x0 0.--31. 1. "PTM_RES_LOCAL_LSB,PTM Responder Local Clock LSB - Lower 32 bits of local timer value. For more details see the PTM section in the Databook. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then.." line.long 0x4 "PTM_RES_LOCAL_MSB_OFF,PTM Responder Local Clock MSB. For more details. see the PTM section in the Databook." hexmask.long 0x4 0.--31. 1. "PTM_RES_LOCAL_MSB,PTM Responder Local Clock MSB - Upper 32 bits of local timer value. For more details see the PTM section in the Databook. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then.." rgroup.long (0x18+0x418)++0x1F line.long 0x0 "PTM_RES_T2_LSB_OFF,PTM Responder T2 Timestamp LSB. For more details. see the PTM section in the Databook." hexmask.long 0x0 0.--31. 1. "PTM_RES_T2_LSB,PTM Responder T2 Timestamp LSB - Lower 32 bits of the T2 Timestamp value. For more details see the PTM section in the Databook. Note: This register field is sticky." line.long 0x4 "PTM_RES_T2_MSB_OFF,PTM Responder T2 Timestamp MSB. For more details. see the PTM section in the Databook." hexmask.long 0x4 0.--31. 1. "PTM_RES_T2_MSB,PTM Responder T2 Timestamp MSB - Upper 32 bits of the T2 Timestamp value. For more details see the PTM section in the Databook. Note: This register field is sticky." line.long 0x8 "PTM_RES_T2P_LSB_OFF,PTM Responder T2 Previous Timestamp LSB. For more details. see the PTM section in the Databook." hexmask.long 0x8 0.--31. 1. "PTM_RES_T2P_LSB,PTM Responder T2 Previous Timestamp LSB - Lower 32 bits of the previously stored T2 Timestamp value. For more details see the PTM section in the Databook. Note: This register field is sticky." line.long 0xC "PTM_RES_T2P_MSB_OFF,PTM Responder T2 Previous Timestamp MSB. For more details. see the PTM section in the Databook." hexmask.long 0xC 0.--31. 1. "PTM_RES_T2P_MSB,PTM Responder T2 Previous Timestamp MSB - Upper 32 bits of the previously stored T2 Timestamp value. For more details see the PTM section in the Databook. Note: This register field is sticky." line.long 0x10 "PTM_RES_T3_LSB_OFF,PTM Responder T3 Timestamp LSB. For more details. see the PTM section in the Databook." hexmask.long 0x10 0.--31. 1. "PTM_RES_T3_LSB,PTM Responder T3 Timestamp LSB - Lower 32 bits of the T3 Timestamp value. For more details see the PTM section in the Databook. Note: This register field is sticky." line.long 0x14 "PTM_RES_T3_MSB_OFF,PTM Responder T3 Timestamp MSB. For more details. see the PTM section in the Databook." hexmask.long 0x14 0.--31. 1. "PTM_RES_T3_MSB,PTM Responder T3 Timestamp MSB - Upper 32 bits of the T2 Timestamp value. For more details see the PTM section in the Databook. Note: This register field is sticky." line.long 0x18 "PTM_RES_T3P_LSB_OFF,PTM Responder T3 Previous Timestamp LSB. For more details. see the PTM section in the Databook." hexmask.long 0x18 0.--31. 1. "PTM_RES_T3P_LSB,PTM Responder T3 Previous Timestamp LSB - Lower 32 bits of the previously stored T3 Timestamp value. For more details see the PTM section in the Databook. Note: This register field is sticky." line.long 0x1C "PTM_RES_T3P_MSB_OFF,PTM Responder T3 Previous Timestamp MSB. For more details. see the PTM section in the Databook." hexmask.long 0x1C 0.--31. 1. "PTM_RES_T3P_MSB,PTM Responder T3 Previous Timestamp MSB - Upper 32 bits of the previously stored T3 Timestamp value. For more details see the PTM section in the Databook. Note: This register field is sticky." group.long (0x38+0x418)++0x7 line.long 0x0 "PTM_RES_TX_LATENCY_OFF,PTM Responder TX Latency. For more details. see the PTM section in the Databook." hexmask.long.tbyte 0x0 12.--31. 1. "RSVDP_12,Reserved for future use." hexmask.long.word 0x0 0.--11. 1. "PTM_RES_TX_LATENCY,PTM Responder TX Latency - Responder Transmit path latency (12 bit wide). For more details see the PTM section in the Databook. Note: This register field is sticky." line.long 0x4 "PTM_RES_RX_LATENCY_OFF,PTM Responder RX Latency. For more details. see the PTM section in the Databook." hexmask.long.tbyte 0x4 12.--31. 1. "RSVDP_12,Reserved for future use." hexmask.long.word 0x4 0.--11. 1. "PTM_RES_RX_LATENCY,PTM Responder RX Latency - Responder Receive path latency (12 bit wide). For more details see the PTM section in the Databook. Note: This register field is sticky." rgroup.long (0x40+0x418)++0x3 line.long 0x0 "PTM_RES_NOM_CLOCK_T_OFF,PTM Responder Nominal Clock Period. For more details. see the PTM section in the Databook." hexmask.long.byte 0x0 24.--31. 1. "RSVDP_24,Reserved for future use." hexmask.long.byte 0x0 16.--23. 1. "PTM_RES_NOM_CLOCK_T_INT,PTM Responder Nominal Clock Period Integral - Integral part of the nominal PTM local clock period in nanoseconds. For more details see the PTM section in the Databook. Note: This register field is sticky." hexmask.long.word 0x0 0.--15. 1. "PTM_RES_NOM_CLOCK_T_FRAC,PTM Responder Nominal Clock Period Fractional - Fractional part of the nominal PTM local clock period. LSB is 1/(2^16) nanoseconds. For more details see the PTM section in the Databook. Note: This register field is sticky." group.long (0x44+0x418)++0x3 line.long 0x0 "PTM_RES_SCALED_CLOCK_T_OFF,PTM Responder Scaled Clock Period. For more details. see the PTM section in the Databook." bitfld.long 0x0 31. "PTM_RES_SCALED_CLOCK_T_EN,PTM Responder Scaled Clock Period Enable - Use the programmed scaled PTM clock period rather than the nominal values. This bit is cleared when the core_clk rate starts to change and can only be set when the clock period change.." "0,1" hexmask.long.byte 0x0 24.--30. 1. "RSVDP_24,Reserved for future use." hexmask.long.byte 0x0 16.--23. 1. "PTM_RES_SCALED_CLOCK_T_INT,PTM Responder Scaled Clock Period Integral - Integral part of the nominal PTM local clock period in nanoseconds. For more details see the PTM section in the Databook. Note: This register field is sticky." newline hexmask.long.word 0x0 0.--15. 1. "PTM_RES_SCALED_CLOCK_T_FRAC,PTM Responder Scaled Clock Period Fractional - Fractional part of the nominal PTM local clock period. LSB is 1/(2^16) nanoseconds. For more details see the PTM section in the Databook. Note: This register field is sticky." tree.end tree "PF0_PM_CAP (PF PCI Power Management Capability Structure)" group.long (0x0+0x40)++0x7 line.long 0x0 "CAP_ID_NXT_PTR_REG,Power Management Capabilities Register." hexmask.long.byte 0x0 27.--31. 1. "PME_SUPPORT,PME_Support. This 5-bit field indicates the power states in which the function may generate a PME and/or forward PME messages. A value of 0b for any bit indicates that the function is not capable of asserting PME while in that power state. -.." bitfld.long 0x0 26. "D2_SUPPORT,D2_Support. If this bit is set this function supports the D2 Power Management state. Functions that do not support D2 must always return a value of 0b for this bit. Note: The access attributes of this field are as follows: - Wire: No access." "0,1" bitfld.long 0x0 25. "D1_SUPPORT,D1_Support. If this bit is set this function supports the D1 Power Management state. Functions that do not support D1 must always return a value of 0b for this bit. Note: The access attributes of this field are as follows: - Wire: No access." "0,1" bitfld.long 0x0 22.--24. "AUX_CURR,Aux_Current. This 3 bit field reports the Vaux auxiliary current requirements for the function. If this function implements the Data Register the controller hardwires this field to 000b. If PME_Support is 0 xxxxb (PME assertion from D3cold is.." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 21. "DSI,Device Specific Initialization. The DSI bit indicates whether special initialization of this function is required. When set indicates that the function requires a device specific initialization sequence following a transition to the D0uninitialized.." "0,1" bitfld.long 0x0 20. "PME_IMM_READI_RETURN_DO,Immediate_Readiness_on_Return_to_D0. - If this bit is a '1' this function is guaranteed to be ready to successfully complete valid accesses immediately after being set to D0. These accesses include configuration cycles and if.." "0,1" rbitfld.long 0x0 19. "PME_CLK,PME Clock. Does not apply to PCI Express the controller hardwires it to 0b. Note: This register field is sticky." "0,1" bitfld.long 0x0 16.--18. "PM_SPEC_VER,Version. This field provides the Power Management specification version. The controller hardwires this field to 011b for functions compliant to PCI Express Base Specification Revision 4.0 Version 1.0>. Note: The access attributes of this.." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x0 8.--15. 1. "PM_NEXT_POINTER,Next Capability Pointer. This field provides an offset into the function's configuration space pointing to the location of next item in the capabilities list. If there are no additional items in the capabilities list this field is set to.." hexmask.long.byte 0x0 0.--7. 1. "PM_CAP_ID,Capability ID. This field returns 01h to indicate that this is the PCI Power Management Capability. Each function may have only one item in its capability list with Capability ID set to 01h." line.long 0x4 "CON_STATUS_REG,Power Management Control and Status Register. This register is used to manage the PCI function's power management state as well as to enable/monitor PMEs." hexmask.long.byte 0x4 24.--31. 1. "DATA_REG_ADD_INFO,Data. This field is used to report the state dependent data requested by the Data_Select field. The value of this field is scaled by the value reported by the Data_Scale field." rbitfld.long 0x4 23. "BUS_PWR_CLK_CON_EN,Bus Power/Clock Control Enable. For a description of this standard PCIe register field see the PCI Express Base Specification." "0,1" rbitfld.long 0x4 22. "B2_B3_SUPPORT,B2B3 Support for D3hot. For a description of this standard PCIe register field see the PCI Express Base Specification." "0,1" hexmask.long.byte 0x4 16.--21. 1. "RSVDP_16,Reserved for future use." newline bitfld.long 0x4 15. "PME_STATUS,PME_Status. This bit is set when the function normally generates a PME signal. The value of this bit is not affected by the value of the PME_En bit. If PME_Support bit 31 of the Power Management Capabilities register is clear this bit is.." "0,1" rbitfld.long 0x4 13.--14. "DATA_SCALE,Data_Scale. This field indicates the scaling factor to be used when interpreting the value of the Data field. The value and meaning of this field varies depending on which data value has been selected by the Data_Select field. For more details.." "0,1,2,3" hexmask.long.byte 0x4 9.--12. 1. "DATA_SELECT,Data_Select. This 4-bit field is used to select which data is to be reported through the Data and Data_Scale field. If the Data field is not implemented this field must be hardwired to 0000b." bitfld.long 0x4 8. "PME_ENABLE,PME_En. - When set the function is permitted to generate a PME. - When clear the function is not permitted to generate a PME. If PME_Support is 1 xxxxb (PME generation from D3cold) or the function consumes Aux power and Aux power is.." "0,1" newline hexmask.long.byte 0x4 4.--7. 1. "RSVDP_4,Reserved for future use." bitfld.long 0x4 3. "NO_SOFT_RST,No_Soft_Reset. This bit indicates the state of the function after writing the PowerState field to transition the function from D3hot to D0. - When set this transition preserves internal function state. The function is in D0Active and no.." "0,1" rbitfld.long 0x4 2. "RSVDP_2,Reserved for future use." "0,1" bitfld.long 0x4 0.--1. "POWER_STATE,PowerState. This 2-bit field is used both to determine the current power state of a function and to set the function into a new power state. The definition of the field values is given below. You can write to this register; however the.." "D0,D1,D2,D3hot" tree.end tree "PF0_PCIE_CAP (PF PCI Express Capability Structure)" group.long (0x0+0x70)++0x33 line.long 0x0 "PCIE_CAP_ID_PCIE_NEXT_CAP_PTR_PCIE_CAP_REG,PCI Express Capabilities. ID. Next Pointer Register." rbitfld.long 0x0 31. "RSVDP_31,Reserved for future use." "0,1" rbitfld.long 0x0 30. "RSVD,Reserved." "0,1" newline hexmask.long.byte 0x0 25.--29. 1. "PCIE_INT_MSG_NUM,PCIE Interrupt Message Number. For a description of this standard PCIe register field see the PCI Express Base Specification. Interrupt Message Number. This field indicates which MSI/MSI-X vector is used for the interrupt message.." bitfld.long 0x0 24. "PCIE_SLOT_IMP,Slot Implemented. When set this bit indicates that the Link associated with this Port is connected to a slot (as compared to being connected to a system-integrated device or being disabled). This bit is valid for Downstream Ports. This bit.." "0,1" newline hexmask.long.byte 0x0 20.--23. 1. "PCIE_DEV_PORT_TYPE,Device/Port Type. Indicates the specific type of this PCI Express function. Note: Different functions in a Multi-Function Device can generally be of different types. Defined encodings for functions that implement a Type 00h PCI.." hexmask.long.byte 0x0 16.--19. 1. "PCIE_CAP_REG,Capability Version. Indicates PCI-SIG defined PCI Express Capability structure version number. A version of the specification that changes the PCI Express Capability structure in a way that is not otherwise identifiable (for example through.." newline hexmask.long.byte 0x0 8.--15. 1. "PCIE_CAP_NEXT_PTR,Next Capability Pointer. This field contains the offset to the next PCI Capability structure or 00h if no other items exist in the linked list of Capabilities. Note: The access attributes of this field are as follows: - Wire: No access." hexmask.long.byte 0x0 0.--7. 1. "PCIE_CAP_ID,Capability ID. Indicates the PCI Express Capability structure. This field must return a Capability ID of 10h indicating that this is a PCI Express Capability structure." line.long 0x4 "DEVICE_CAPABILITIES_REG,Device Capabilities Register. The Device Capabilities register identifies PCI Express device function specific capabilities." hexmask.long.word 0x4 16.--31. 1. "RSVDP_16,Reserved for future use." bitfld.long 0x4 15. "PCIE_CAP_ROLE_BASED_ERR_REPORT,Role-Based Error Reporting. When set this bit indicates that the function implements the functionality originally defined in the Error Reporting ECN for PCI Express Base Specification Revision 1.0a and later incorporated.." "0,1" newline hexmask.long.word 0x4 6.--14. 1. "RSVDP_6,Reserved for future use." bitfld.long 0x4 5. "PCIE_CAP_EXT_TAG_SUPP,Extended Tag Field Supported. This bit in combination with the 10-Bit Tag Requester Supported bit in the Device Capabilities 2 register indicates the maximum supported size of the Tag field as a Requester. This bit must be set if.." "0,1" newline bitfld.long 0x4 3.--4. "PCIE_CAP_PHANTOM_FUNC_SUPPORT,Phantom Functions Supported. This field indicates the support for use of unclaimed function numbers to extend the number of outstanding transactions allowed by logically combining unclaimed function numbers (called Phantom.." "0,1,2,3" bitfld.long 0x4 0.--2. "PCIE_CAP_MAX_PAYLOAD_SIZE,Max_Payload_Size Supported. This field indicates the maximum payload size that the function can support for TLPs. Defined encodings are: - 000b: 128 bytes max payload size - 001b: 256 bytes max payload size - 010b: 512 bytes max.." "0,1,2,3,4,5,6,7" line.long 0x8 "DEVICE_CONTROL_DEVICE_STATUS,Device Control and Device Status Register. This register controls PCI Express device specific parameters and provides information about PCI Express device (function) specific parameters." hexmask.long.word 0x8 22.--31. 1. "RSVDP_22,Reserved for future use." rbitfld.long 0x8 21. "PCIE_CAP_TRANS_PENDING,Transactions Pending. Endpoints: When set this bit indicates that the function has issued Non-Posted Requests that have not been completed. A Function reports this bit cleared only when all outstanding Non-Posted Requests have.." "0,1" newline rbitfld.long 0x8 20. "PCIE_CAP_AUX_POWER_DETECTED,AUX Power Detected. Functions that require Aux power report this bit as set if Aux power is detected by the function. This bit is derived by sampling the sys_aux_pwr_det input." "0,1" bitfld.long 0x8 19. "PCIE_CAP_UNSUPPORTED_REQ_DETECTED,Unsupported Request Detected. This bit indicates that the function received an Unsupported Request. Errors are logged in this register regardless of whether error reporting is enabled or not in the Device Control.." "0,1" newline bitfld.long 0x8 18. "PCIE_CAP_FATAL_ERR_DETECTED,Fatal Error Detected. This bit indicates status of Fatal errors detected. Errors are logged in this register regardless of whether error reporting is enabled or not in the Device Control register. For a Multi-Function device.." "0,1" bitfld.long 0x8 17. "PCIE_CAP_NON_FATAL_ERR_DETECTED,Non-Fatal Error Detected. This bit indicates status of Non-fatal errors detected. Errors are logged in this register regardless of whether error reporting is enabled or not in the Device Control register. For a.." "0,1" newline bitfld.long 0x8 16. "PCIE_CAP_CORR_ERR_DETECTED,Correctable Error Detected. This bit indicates status of correctable errors detected. Errors are logged in this register regardless of whether error reporting is enabled or not in the Device Control register. For a.." "0,1" bitfld.long 0x8 15. "PCIE_CAP_INITIATE_FLR,Initiate Function Level Reset (applicable to Endpoints with Function Level Reset Capability set to 1b). A write of 1b initiates Function Level Reset to the Function. The value read by software from this bit is always 0b." "0,1" newline bitfld.long 0x8 12.--14. "PCIE_CAP_MAX_READ_REQ_SIZE,Max_Read_Request_Size. This field sets the maximum Read Request size for the function as a Requester. The function must not generate Read Requests with a size exceeding the set value. Defined encodings for this field are: -.." "0,1,2,3,4,5,6,7" rbitfld.long 0x8 11. "PCIE_CAP_EN_NO_SNOOP,Enable No Snoop. If this bit is set the function is permitted to Set the No Snoop bit in the Requester Attributes of transactions it initiates that do not require hardware enforced cache coherency (see section 2.2.6.5 in PCI Express.." "0,1" newline bitfld.long 0x8 10. "PCIE_CAP_AUX_POWER_PM_EN,Aux Power PM Enable. This bit is derived by sampling the sys_aux_pwr_det input. When set this bit enables a function to draw Aux power independent of PME Aux power. Functions that require Aux power on legacy operating systems.." "0,1" rbitfld.long 0x8 9. "PCIE_CAP_PHANTOM_FUNC_EN,Phantom Functions Enable. This bit in combination with the 10-Bit Tag Requester Enable bit in the Device Control 2 register determines how many Tag field bits a Requester is permitted to use. When the 10-Bit Tag Requester.." "0,1" newline rbitfld.long 0x8 8. "PCIE_CAP_EXT_TAG_EN,Extended Tag Field Enable. This bit in combination with the 10-Bit Tag Requester Enable bit in the Device Control 2 register determines how many Tag field bits a Requester is permitted to use. When the 10-Bit Tag Requester Enable.." "0,1" bitfld.long 0x8 5.--7. "PCIE_CAP_MAX_PAYLOAD_SIZE_CS,Max_Payload_Size. This field sets maximum TLP payload size for the Function. As a Receiver the Function must handle TLPs as large as the set value. As a Transmitter the Function must not generate TLPs exceeding the set.." "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 4. "PCIE_CAP_EN_REL_ORDER,Enable Relaxed Ordering. If this bit is set the function is permitted to set the Relaxed Ordering bit in the Attributes field of transactions it initiates that do not require strong write ordering (for more details see section.." "0,1" bitfld.long 0x8 3. "PCIE_CAP_UNSUPPORT_REQ_REP_EN,Unsupported Request Reporting Enable. This bit in conjunction with other bits controls the signaling of Unsupported Request Errors by sending error Messages (for more details see section 6.2.5 and section 6.2.6 of PCI.." "0,1" newline bitfld.long 0x8 2. "PCIE_CAP_FATAL_ERR_REPORT_EN,Fatal Error Reporting Enable. This bit in conjunction with other bits controls sending ERR_FATAL Messages (for more details see section 6.2.5 and section 6.2.6 of of PCI Express Base Specification). For a Multi-Function.." "0,1" bitfld.long 0x8 1. "PCIE_CAP_NON_FATAL_ERR_REPORT_EN,Non-Fatal Error Reporting Enable. This bit in conjunction with other bits controls sending ERR_NONFATAL Messages (for more details see section 6.2.5 and Section 6.2.6 of PCI Express Base Specification). For a.." "0,1" newline bitfld.long 0x8 0. "PCIE_CAP_CORR_ERR_REPORT_EN,Correctable Error Reporting Enable. This bit in conjunction with other bits controls sending ERR_COR Messages (for more details see section 6.2.5 section 6.2.6 and section 6.2.10.2 of PCI Express Base Specification). For.." "0,1" line.long 0xC "LINK_CAPABILITIES_REG,Link Capabilities Register. The Link Capabilities register identifies PCI Express Link specific capabilities." hexmask.long.byte 0xC 24.--31. 1. "PCIE_CAP_PORT_NUM,Port Number. This field indicates the PCI Express Port number for the given PCI Express Link. Multi-Function Devices associated with an Upstream Port must report the same value in this field for all functions. Note: The access.." rbitfld.long 0xC 23. "RSVDP_23,Reserved for future use." "0,1" newline bitfld.long 0xC 22. "PCIE_CAP_ASPM_OPT_COMPLIANCE,ASPM Optionality Compliance. This bit must be set to 1b in all functions. Components implemented against certain earlier versions of this specification will have this bit set to 0b. Software is permitted to use the value of.." "0,1" bitfld.long 0xC 21. "PCIE_CAP_LINK_BW_NOT_CAP,Link Bandwidth Notification Capability. A value of 1b indicates support for the Link Bandwidth Notification status and interrupt mechanisms. This capability is required for all Root Ports and Switch Downstream Ports supporting.." "0,1" newline rbitfld.long 0xC 20. "PCIE_CAP_DLL_ACTIVE_REP_CAP,Data Link Layer Link Active Reporting Capable. For a Downstream Port the controller hardwires this bit to 1b if the component supports the optional capability of reporting the DL_Active state of the Data Link Control and.." "0,1" bitfld.long 0xC 19. "PCIE_CAP_SURPRISE_DOWN_ERR_REP_CAP,Surprise Down Error Reporting Capable. For a Downstream Port this bit must be set if the component supports the optional capability of detecting and reporting a Surprise Down error condition. For Upstream Ports and.." "0,1" newline rbitfld.long 0xC 18. "PCIE_CAP_CLOCK_POWER_MAN,Clock Power Management. For Upstream Ports a value of 1b in this bit indicates that the component tolerates the removal of any reference clock(s) via the 'clock request' (CLKREQ#) mechanism when the Link is in the L1 and L2/L3.." "0,1" bitfld.long 0xC 15.--17. "PCIE_CAP_L1_EXIT_LATENCY,L1 Exit Latency. This field indicates the L1 exit latency for the given PCI Express Link. The value reported indicates the length of time this Port requires to complete transition from ASPM L1 to L0. If ASPM L1 is not supported.." "0,1,2,3,4,5,6,7" newline bitfld.long 0xC 12.--14. "PCIE_CAP_L0S_EXIT_LATENCY,L0s Exit Latency. This field indicates the L0s exit latency for the given PCI Express Link. The value reported indicates the length of time this Port requires to complete transition from L0s to L0. If L0s is not supported the.." "0,1,2,3,4,5,6,7" bitfld.long 0xC 10.--11. "PCIE_CAP_ACTIVE_STATE_LINK_PM_SUPPORT,Active State Power Management (ASPM) Support. This field indicates the level of ASPM supported on the given PCI Express Link. For more details on ASPM support requirements see section 5.4.1 of PCI Express Base.." "0,1,2,3" newline hexmask.long.byte 0xC 4.--9. 1. "PCIE_CAP_MAX_LINK_WIDTH,Maximum Link Width. This field indicates the maximum Link width (xN - corresponding to N Lanes) implemented by the component. This value is permitted to exceed the number of Lanes routed to the slot (Downstream Port) adapter.." hexmask.long.byte 0xC 0.--3. 1. "PCIE_CAP_MAX_LINK_SPEED,Max Link Speed. This field indicates the maximum Link speed of the associated Port. The encoded value specifies a bit location in the Supported Link Speeds Vector (in the Link Capabilities 2 register) that corresponds to the.." line.long 0x10 "LINK_CONTROL_LINK_STATUS_REG,Link Control and Link Status Register. This register controls and provides information about PCI Express Link specific parameters." bitfld.long 0x10 31. "PCIE_CAP_LINK_AUTO_BW_STATUS,Link Autonomous Bandwidth Status. This bit is set by hardware to indicate that hardware has autonomously changed Link speed or width without the Port transitioning through DL_Down status for reasons other than to attempt to.." "0,1" bitfld.long 0x10 30. "PCIE_CAP_LINK_BW_MAN_STATUS,Link Bandwidth Management Status. This bit is set by hardware to indicate that either of the following has occurred without the Port transitioning through DL_Down status: - A Link retraining has completed following a write of.." "0,1" newline rbitfld.long 0x10 29. "PCIE_CAP_DLL_ACTIVE,Data Link Layer Link Active. This bit indicates the status of the Data Link Control and Management State Machine. It returns a 1b to indicate the DL_Active state 0b otherwise. This bit must be implemented if the Data Link Layer Link.." "0,1" bitfld.long 0x10 28. "PCIE_CAP_SLOT_CLK_CONFIG,Slot Clock Configuration. This bit indicates that the component uses the same physical reference clock that the platform provides on the connector. If the device uses an independent clock irrespective of the presence of a.." "0,1" newline rbitfld.long 0x10 27. "PCIE_CAP_LINK_TRAINING,Link Training. This read-only bit indicates that the Physical Layer LTSSM is in the Configuration or Recovery state or that 1b was written to the Retrain Link bit but Link training has not yet begun. Hardware clears this bit when.." "0,1" rbitfld.long 0x10 26. "RSVDP_26,Reserved for future use." "0,1" newline hexmask.long.byte 0x10 20.--25. 1. "PCIE_CAP_NEGO_LINK_WIDTH,Negotiated Link Width. This field indicates the negotiated width of the given PCI Express Link. Defined encodings are: -00 0001b: x1 -00 0010b: x2 -00 0100b: x4 -00 1000b: x8 -00 1100b: x12 -01 0000b: x16 -10 0000b: x32 All other.." hexmask.long.byte 0x10 16.--19. 1. "PCIE_CAP_LINK_SPEED,Current Link Speed. This field indicates the negotiated Link speed of the given PCI Express Link. The encoded value specifies a bit location in the Supported Link Speeds Vector (in the Link Capabilities 2 register) that corresponds to.." newline bitfld.long 0x10 14.--15. "PCIE_CAP_DRS_SIGNALING_CONTROL,DRS Signaling Control. Indicates the mechanism used to report reception of a DRS message. Must be implemented for Downstream Ports with the DRS Supported bit Set in the Link Capabilities 2 Register. Encodings are: - 00b:.." "0,1,2,3" rbitfld.long 0x10 12.--13. "RSVDP_12,Reserved for future use." "0,1,2,3" newline bitfld.long 0x10 11. "PCIE_CAP_LINK_AUTO_BW_INT_EN,Link Autonomous Bandwidth Management Interrupt Enable. When set this bit enables the generation of an interrupt to indicate that the Link Autonomous Bandwidth Status bit has been set. The write value is gated with the.." "0,1" bitfld.long 0x10 10. "PCIE_CAP_LINK_BW_MAN_INT_EN,Link Bandwidth Management Interrupt Enable. When set this bit enables the generation of an interrupt to indicate that the Link Bandwidth Management Status bit has been set. The write value is gated with the.." "0,1" newline bitfld.long 0x10 9. "PCIE_CAP_HW_AUTO_WIDTH_DISABLE,Hardware Autonomous Width Disable. When set this bit disables hardware from changing the Link width for reasons other than attempting to correct unreliable Link operation by reducing Link width. For a Multi-Function Device.." "0,1" bitfld.long 0x10 8. "PCIE_CAP_EN_CLK_POWER_MAN,Enable Clock Power Management. Applicable only for Upstream Ports and with form factors that support a 'Clock Request' (CLKREQ#) mechanism this bit operates as follows: - 0b: Clock power management is disabled and device must.." "0,1" newline bitfld.long 0x10 7. "PCIE_CAP_EXTENDED_SYNCH,Extended Synch. When set this bit forces the transmission of additional Ordered Sets when exiting the L0s state (see section 4.2.4.5 of PCI Express Base Specification) and when in the Recovery state (see section 4.2.6.4.1 of PCI.." "0,1" bitfld.long 0x10 6. "PCIE_CAP_COMMON_CLK_CONFIG,Common Clock Configuration. When set this bit indicates that this component and the component at the opposite end of this Link are operating with a distributed common reference clock. A value of 0b indicates that this.." "0,1" newline bitfld.long 0x10 5. "PCIE_CAP_RETRAIN_LINK,Retrain Link. A write of 1b to this bit initiates Link retraining by directing the Physical Layer LTSSM to the Recovery state. If the LTSSM is already in Recovery or Configuration re-entering Recovery is permitted but not required." "0,1" bitfld.long 0x10 4. "PCIE_CAP_LINK_DISABLE,Link Disable. This bit disables the Link by directing the LTSSM to the Disabled state when set; this bit is Reserved on Endpoints PCI Express to PCI/PCI-X bridges and Upstream Ports of Switches. Writes to this bit are immediately.." "0,1" newline bitfld.long 0x10 3. "PCIE_CAP_RCB,Read Completion Boundary (RCB). Root Ports: Indicates the RCB value for the Root Port. Refer to section 2.3.1.1 of PCI Express Base Specification for the definition of the parameter RCB. Defined encodings are: - 0b: 64 byte - 1b: 128 byte.." "0,1" rbitfld.long 0x10 2. "RSVDP_2,Reserved for future use." "0,1" newline bitfld.long 0x10 0.--1. "PCIE_CAP_ACTIVE_STATE_LINK_PM_CONTROL,Active State Power Management (ASPM) Control. This field controls the level of ASPM enabled on the given PCI Express Link. See section 5.4.1.3 of PCI Express Base Specification for requirements on when and how to.." "0,1,2,3" line.long 0x14 "SLOT_CAPABILITIES_REG,Slot Capabilities Register. The Slot Capabilities register identifies PCI Express slot specific capabilities." hexmask.long.word 0x14 19.--31. 1. "PCIE_CAP_PHY_SLOT_NUM,Physical Slot Number. This field indicates the physical slot number attached to this Port. This field must be hardware initialized to a value that assigns a slot number that is unique within the chassis regardless of the form.." bitfld.long 0x14 18. "PCIE_CAP_NO_CMD_CPL_SUPPORT,No Command Completed Support. When set this bit indicates that this slot does not generate software notification when an issued command is completed by the Hot-Plug Controller. This bit is only permitted to be set if the.." "0,1" newline bitfld.long 0x14 17. "PCIE_CAP_ELECTROMECH_INTERLOCK,Electromechanical Interlock Present. When set this bit indicates that an Electromechanical Interlock is implemented on the chassis for this slot. Note: The access attributes of this field are as follows: - Wire: No access." "0,1" bitfld.long 0x14 15.--16. "PCIE_CAP_SLOT_POWER_LIMIT_SCALE,Slot Power Limit Scale. Specifies the scale used for the Slot Power Limit Value (for more details see Section 6.9 of PCI Express Base Specification). Range of Values: - 00b: 1.0x - 01b: 0.1x - 10b: 0.01x - 11b: 0.001x.." "0,1,2,3" newline hexmask.long.byte 0x14 7.--14. 1. "PCIE_CAP_SLOT_POWER_LIMIT_VALUE,Slot Power Limit Value. In combination with the Slot Power Limit Scale value specifies the upper limit on power supplied by the slot (for more detais see Section 6.9 of PCI Express Base Specification) or by other means.." bitfld.long 0x14 6. "PCIE_CAP_HOT_PLUG_CAPABLE,Hot-Plug Capable. When set this bit indicates that this slot is capable of supporting hot-plug operations. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then R/W else R" "0,1" newline bitfld.long 0x14 5. "PCIE_CAP_HOT_PLUG_SURPRISE,Hot-Plug Surprise. When set this bit indicates that an adapter present in this slot might be removed from the system without any prior notification. This is a form factor specific capability. This bit is an indication to the.." "0,1" bitfld.long 0x14 4. "PCIE_CAP_POWER_INDICATOR,Power Indicator Present. When set this bit indicates that a Power Indicator is electrically controlled by the chassis for this slot. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if.." "0,1" newline bitfld.long 0x14 3. "PCIE_CAP_ATTENTION_INDICATOR,Attention Indicator Present. When set this bit indicates that an Attention Indicator is electrically controlled by the chassis. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if.." "0,1" bitfld.long 0x14 2. "PCIE_CAP_MRL_SENSOR,MRL Sensor Present. When set this bit indicates that an MRL Sensor is implemented on the chassis for this slot. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then R/W else R" "0,1" newline bitfld.long 0x14 1. "PCIE_CAP_POWER_CONTROLLER,Power Controller Present. When set this bit indicates that a software programmable Power Controller is implemented for this slot/adapter (depending on form factor). Note: The access attributes of this field are as follows: -.." "0,1" bitfld.long 0x14 0. "PCIE_CAP_ATTENTION_INDICATOR_BUTTON,Attention Button Present. When set this bit indicates that an Attention Button for this slot is electrically controlled by the chassis. Note: The access attributes of this field are as follows: - Wire: No access. -.." "0,1" line.long 0x18 "SLOT_CONTROL_SLOT_STATUS,Slot Control and Status Register. This register controls and provides information about PCI Express Slot specific parameters." hexmask.long.byte 0x18 25.--31. 1. "RSVDP_25,Reserved for future use." bitfld.long 0x18 24. "PCIE_CAP_DLL_STATE_CHANGED,Data Link Layer State Changed. This bit is set when the value reported in the Data Link Layer Link Active bit of the Link Status register is changed. In response to a Data Link Layer State Changed event software must read the.." "0,1" newline rbitfld.long 0x18 23. "PCIE_CAP_ELECTROMECH_INTERLOCK_STATUS,Electromechanical Interlock Status. If an Electromechanical Interlock is implemented this bit indicates the status of the Electromechanical Interlock. Defined encodings are: - 0b: Electromechanical Interlock.." "0,1" rbitfld.long 0x18 22. "PCIE_CAP_PRESENCE_DETECT_STATE,Presence Detect State. This bit indicates the presence of an adapter in the slot reflected by the logical 'OR' of the Physical Layer in-band presence detect mechanism and if present any out-of-band presence detect.." "0,1" newline rbitfld.long 0x18 21. "PCIE_CAP_MRL_SENSOR_STATE,MRL Sensor State. This bit reports the status of the MRL sensor if implemented. Defined encodings are: - 0b: MRL Closed - 1b: MRL Open" "0,1" bitfld.long 0x18 20. "PCIE_CAP_CMD_CPLD,Command Completed. If Command Completed notification is supported (if the No Command Completed Support bit in the Slot Capabilities register is 0b) this bit is set when a hot-plug command has completed and the Hot-Plug Controller is.." "0,1" newline bitfld.long 0x18 19. "PCIE_CAP_PRESENCE_DETECTED_CHANGED,Presence Detect Changed. This bit is set when the value reported in the Presence Detect State bit is changed." "0,1" bitfld.long 0x18 18. "PCIE_CAP_MRL_SENSOR_CHANGED,MRL Sensor Changed. If an MRL sensor is implemented this bit is set when a MRL Sensor state change is detected. If an MRL sensor is not implemented this bit must not be set." "0,1" newline bitfld.long 0x18 17. "PCIE_CAP_POWER_FAULT_DETECTED,Power Fault Detected. If a Power Controller that supports power fault detection is implemented this bit issSet when the Power Controller detects a power fault at this slot. Note: Depending on hardware capability it is.." "0,1" bitfld.long 0x18 16. "PCIE_CAP_ATTENTION_BUTTON_PRESSED,Attention Button Pressed. If an Attention Button is implemented this bit is set when the attention button is pressed. If an Attention Button is not supported this bit must not be set." "0,1" newline rbitfld.long 0x18 14.--15. "RSVDP_14,Reserved for future use." "0,1,2,3" bitfld.long 0x18 12. "PCIE_CAP_DLL_STATE_CHANGED_EN,Data Link Layer State Changed Enable. If the Data Link Layer Link Active Reporting capability is 1b this bit enables software notification when Data Link Layer Link Active bit is changed. If the Data Link Layer Link Active.." "0,1" newline bitfld.long 0x18 11. "PCIE_CAP_ELECTROMECH_INTERLOCK_CTRL,Electromechanical Interlock Control. If an Electromechanical Interlock is implemented a write of 1b to this bit causes the state of the interlock to toggle. A write of 0b to this bit has no effect. A read of this bit.." "0,1" bitfld.long 0x18 10. "PCIE_CAP_POWER_CONTROLLER_CTRL,Power Controller Control. If a Power Controller is implemented this bit when written sets the power state of the slot per the defined encodings. Reads of this bit must reflect the value from the latest write even if the.." "0,1" newline bitfld.long 0x18 8.--9. "PCIE_CAP_POWER_INDICATOR_CTRL,Power Indicator Control. If a Power Indicator is implemented writes to this field set the Power Indicator to the written state. Reads of this field must reflect the value from the latest write even if the corresponding.." "0,1,2,3" bitfld.long 0x18 6.--7. "PCIE_CAP_ATTENTION_INDICATOR_CTRL,Attention Indicator Control. If an Attention Indicator is implemented writes to this field set the Attention Indicator to the written state. Reads of this field must reflect the value from the latest write even if the.." "0,1,2,3" newline bitfld.long 0x18 5. "PCIE_CAP_HOT_PLUG_INT_EN,Hot-Plug Interrupt Enable. When set this bit enables generation of an interrupt on enabled hot-plug events. If the Hot Plug Capable bit in the Slot Capabilities register is clear this bit is permitted to be read-only with a.." "0,1" bitfld.long 0x18 4. "PCIE_CAP_CMD_CPL_INT_EN,Command Completed Interrupt Enable. If Command Completed notification is supported (if the No Command Completed Support bit in the Slot Capabilities register is 0b) when set this bit enables software notification when a hot-plug.." "0,1" newline bitfld.long 0x18 3. "PCIE_CAP_PRESENCE_DETECT_CHANGE_EN,Presence Detect Changed Enable. When set this bit enables software notification on a presence detect changed event (for more details see Section 6.7.3 of PCI Express Base Specification). If the Hot-Plug Capable bit in.." "0,1" bitfld.long 0x18 2. "PCIE_CAP_MRL_SENSOR_CHANGED_EN,MRL Sensor Changed Enable. When set this bit enables software notification on a MRL sensor changed event (for more details see Section 6.7.3 of PCI Express Base Specification). If the MRL Sensor Present bit in the Slot.." "0,1" newline bitfld.long 0x18 1. "PCIE_CAP_POWER_FAULT_DETECTED_EN,Power Fault Detected Enable. When set this bit enables software notification on a power fault event (for more details see Section 6.7.3 of PCI Express Base Specification). If a Power Controller that supports power fault.." "0,1" bitfld.long 0x18 0. "PCIE_CAP_ATTENTION_BUTTON_PRESSED_EN,Attention Button Pressed Enable. When set to 1b this bit enables software notification on an attention button pressed event (for more details see Section 6.7.3 of PCI Express Base Specification). If the Attention.." "0,1" line.long 0x1C "ROOT_CONTROL_ROOT_CAPABILITIES_REG,Root Control and Capabilities Register. This register controls PCI Express Root Complex specific parameters and identifies PCI Express Root Port specific capabilities." hexmask.long.word 0x1C 17.--31. 1. "RSVDP_17,Reserved for future use." bitfld.long 0x1C 16. "PCIE_CAP_CRS_SW_VISIBILITY,CRS Software Visibility Capable. For a description of this standard PCIe register field see the PCI Express Base Specification. CRS Software Visibility. When set this bit indicates that the Root Port is capable of returning.." "0,1" newline hexmask.long.word 0x1C 5.--15. 1. "RSVDP_5,Reserved for future use." bitfld.long 0x1C 4. "PCIE_CAP_CRS_SW_VISIBILITY_EN,CRS Software Visibility Enable. When set this bit enables the Root Port to return Configuration Request Retry Status (CRS) Completion Status to software (for more details see section 2.3.1 of PCI Express Base.." "0,1" newline bitfld.long 0x1C 3. "PCIE_CAP_PME_INT_EN,PME Interrupt Enable. When set this bit enables PME interrupt generation upon receipt of a PME Message as reflected in the PME Status bit (for more details see Table 7-29 of PCI Express Base Specification). A PME interrupt is also.." "0,1" bitfld.long 0x1C 2. "PCIE_CAP_SYS_ERR_ON_FATAL_ERR_EN,System Error on Fatal Error Enable. If set this bit indicates that a System Error should be generated if a Fatal error (ERR_FATAL) is reported by any of the devices in the Hierarchy Domain associated with this Root Port.." "0,1" newline bitfld.long 0x1C 1. "PCIE_CAP_SYS_ERR_ON_NON_FATAL_ERR_EN,System Error on Non-Fatal Error Enable. If set this bit indicates that a System Error should be generated if a Non-fatal error (ERR_NONFATAL) is reported by any of the devices in the Hierarchy Domain associated with.." "0,1" bitfld.long 0x1C 0. "PCIE_CAP_SYS_ERR_ON_CORR_ERR_EN,System Error on Correctable Error Enable. If set this bit indicates that a System Error should be generated if a correctable error (ERR_COR) is reported by any of the devices in the Hierarchy Domain associated with this.." "0,1" line.long 0x20 "ROOT_STATUS_REG,Root Status Register. The Root Status register provides information about PCI Express device specific parameters." hexmask.long.word 0x20 18.--31. 1. "RSVDP_18,Reserved for future use." rbitfld.long 0x20 17. "PCIE_CAP_PME_PENDING,PME Pending. This bit indicates that another PME is pending when the PME Status bit is s et. When the PME Status bit is cleared by software; the PME is delivered by hardware by setting the PME Status bit again and updating the PME.." "0,1" newline bitfld.long 0x20 16. "PCIE_CAP_PME_STATUS,PME Status. This bit indicates that PME was asserted by the PME Requester indicated in the PME Requester ID field. Subsequent PMEs are kept pending until the status register is cleared by software by writing a 1b." "0,1" hexmask.long.word 0x20 0.--15. 1. "PCIE_CAP_PME_REQ_ID,PME Requester ID. This field indicates the PCI Requester ID of the last PME Requester. This field is only valid when the PME Status bit is set." line.long 0x24 "DEVICE_CAPABILITIES2_REG,Device Capabilities 2 Register." bitfld.long 0x24 31. "PCIE_CAP_FRS_SUPPORTED,FRS Supported. When set indicates support for the optional Function Readiness Status (FRS) capability. Must be set for all Functions that support generation or reception capabilities of FRS Messages. Must not be set by Switch.." "0,1" hexmask.long.byte 0x24 24.--30. 1. "RSVDP_24,Reserved for future use." newline bitfld.long 0x24 22.--23. "PCIE_CAP2_CFG_MAX_END2END_TLP_PRFXS,Max End-End TLP Prefixes. Indicates the maximum number of End-End TLP Prefixes supported by this Function. For more details see Section 2.2.10.2 of PCI Express Base Specification. Values are: - 01b: 1 End-End TLP.." "0,1,2,3" bitfld.long 0x24 21. "PCIE_CAP2_CFG_END2END_TLP_PRFX_SUPPORT,End-End TLP Prefix Supported. Indicates whether End-End TLP Prefix support is offered by a Function. Values are: - 0b: No Support - 1b: Support is provided to receive TLPs containing End-End TLP Prefixes. All Ports.." "0,1" newline bitfld.long 0x24 20. "PCIE_CAP2_CFG_EXTND_FMT_SUPPORT,Extended Fmt Field Supported. If set the Function supports the 3-bit definition of the Fmt field. If clear the Function supports a 2-bit definition of the Fmt field. For more details see section 2.2 of PCI Express Base.." "0,1" rbitfld.long 0x24 17. "PCIE_CAP2_10_BIT_TAG_REQ_SUPPORT,10-Bit Tag Requester Supported. If this bit is set the Function supports 10-Bit Tag Requester capability; otherwise the Function does not. This bit must not be set if the 10-Bit Tag Completer Supported bit is clear." "0,1" newline rbitfld.long 0x24 16. "PCIE_CAP2_10_BIT_TAG_COMP_SUPPORT,10-Bit Tag Completer Supported. If this bit is set the Function supports 10-Bit Tag Completer capability; otherwise the Function does not. For more details see section 2.2.6.2. of PCI Express Base Specification." "0,1" rbitfld.long 0x24 13. "PCIE_CAP_TPH_CMPLT_SUPPORT_1,TPH Completer Supported Bit 1." "0,1" newline rbitfld.long 0x24 12. "PCIE_CAP_TPH_CMPLT_SUPPORT_0,TPH Completer Supported Bit 0. Value of this bit along with TPH Completer Supported Bit 1 indicates Completer support for TPH or Extended TPH. Applicable only to Root Ports and Endpoints. For all other Functions this field.." "0,1" bitfld.long 0x24 11. "PCIE_CAP_LTR_SUPP,LTR Mechanism Supported. A value of 1b indicates support for the optional Latency Tolerance Reporting (LTR) mechanism. Root Ports Switches and Endpoints are permitted to implement this capability. For a Multi-Function Device associated.." "0,1" newline rbitfld.long 0x24 10. "PCIE_CAP_NO_RO_EN_PR2PR_PAR,No RO-enabled PR-PR Passing. If this bit is set the routing element never carries out the passing permitted by Table 2-39 of PCI Express Base Specification entry A2b that is associated with the Relaxed Ordering Attribute.." "0,1" rbitfld.long 0x24 9. "PCIE_CAP_128_CAS_CPL_SUPP,128-bit CAS Completer Supported. Applicable to Functions with Memory Space BARs as well as all Root Ports; must be 0b otherwise. This bit must be set to 1b if the Function supports this optional capability. For more details see.." "0,1" newline rbitfld.long 0x24 8. "PCIE_CAP_64_ATOMIC_CPL_SUPP,64-bit AtomicOp Completer Supported. Applicable to Functions with Memory Space BARs as well as all Root Ports; must be 0b otherwise. Includes FetchAdd Swap and CAS AtomicOps. This bit must be set to 1b if the Function.." "0,1" rbitfld.long 0x24 7. "PCIE_CAP_32_ATOMIC_CPL_SUPP,32-bit AtomicOp Completer Supported. Applicable to Functions with Memory Space BARs as well as all Root Ports; must be 0b otherwise. Includes FetchAdd Swap and CAS AtomicOps. This bit must be set to 1b if the Function.." "0,1" newline rbitfld.long 0x24 6. "PCIE_CAP_ATOMIC_ROUTING_SUPP,AtomicOp Routing Supported. Applicable only to Switch Upstream Ports Switch Downstream Ports and Root Ports; must be 0b for other Function types. This bit must be set to 1b if the Port supports this optional capability. For.." "0,1" rbitfld.long 0x24 5. "PCIE_CAP_ARI_FORWARD_SUPPORT,ARI Forwarding Supported. Applicable only to Switch Downstream Ports and Root Ports; must be 0b for other Function types. This bit must be set to 1b if a Switch Downstream Port or Root Port supports this optional capability." "0,1" newline rbitfld.long 0x24 4. "PCIE_CAP_CPL_TIMEOUT_DISABLE_SUPPORT,Completion Timeout Disable Supported. A value of 1b indicates support for the Completion Timeout Disable mechanism. The Completion Timeout Disable mechanism is required for Endpoints that issue Requests on their own.." "0,1" hexmask.long.byte 0x24 0.--3. 1. "PCIE_CAP_CPL_TIMEOUT_RANGE,Completion Timeout Ranges Supported. This field indicates device Function support for the optional Completion Timeout programmability mechanism. This mechanism allows system software to modify the Completion Timeout value. This.." line.long 0x28 "DEVICE_CONTROL2_DEVICE_STATUS2_REG,Device Control 2 and Status 2 Register." hexmask.long.word 0x28 16.--31. 1. "RSVDP_16,Reserved for future use." bitfld.long 0x28 15. "PCIE_CTRL2_CFG_END2END_TLP_PFX_BLCK,End-End TLP Prefix Blocking. Controls whether the routing function is permitted to forward TLPs containing an End-End TLP Prefix. Values are: - 0b: Forwarding Enabled - Function is permitted to send TLPs with End-End.." "0,1" newline rbitfld.long 0x28 11. "RSVDP_11,Reserved for future use." "0,1" bitfld.long 0x28 10. "PCIE_CAP_LTR_EN,LTR Mechanism Enable. When set to 1b this bit enables Upstream Ports to send LTR messages and Downstream Ports to process LTR Messages. For a Multi-Function Device associated with an Upstream Port of a device that implements LTR the bit.." "0,1" newline rbitfld.long 0x28 5. "PCIE_CAP_ARI_FORWARD_SUPPORT_CS,ARI Forwarding Enable. When set the Downstream Port disables its traditional Device Number field being 0 enforcement when turning a Type 1 Configuration Request into a Type 0 Configuration Request permitting access to.." "0,1" bitfld.long 0x28 4. "PCIE_CAP_CPL_TIMEOUT_DISABLE,Completion Timeout Disable. When set this bit disables the Completion Timeout mechanism. This bit is required for all Functions that support the Completion Timeout Disable Capability. Functions that do not support this.." "0,1" newline hexmask.long.byte 0x28 0.--3. 1. "PCIE_CAP_CPL_TIMEOUT_VALUE,Completion Timeout Value. In device Functions that support Completion Timeout programmability this field allows system software to modify the Completion Timeout value. This field is applicable to Root Ports Endpoints that.." line.long 0x2C "LINK_CAPABILITIES2_REG,Link Capabilities 2 Register." bitfld.long 0x2C 31. "DRS_SUPPORTED,DRS Supported. When set indicates support for the optional Device Readiness Status (DRS) capability. Must be Set in Downstream Ports that support DRS. Must be Set in Downstream Ports that support FRS. For Upstream Ports that support DRS.." "0,1" hexmask.long.byte 0x2C 25.--30. 1. "RSVDP_25,Reserved for future use." newline hexmask.long.word 0x2C 9.--22. 1. "RSVDP_9,Reserved for future use." rbitfld.long 0x2C 8. "PCIE_CAP_CROSS_LINK_SUPPORT,Crosslink Supported. When set to 1b this bit indicates that the associated Port supports crosslinks (for more details see section 4.2.6.3.1 of PCI Express Base Specification). When set to 0b on a Port that supports Link.." "0,1" newline hexmask.long.byte 0x2C 1.--7. 1. "PCIE_CAP_SUPPORT_LINK_SPEED_VECTOR,Supported Link Speeds Vector. This field indicates the supported Link speed(s) of the associated Port. For each bit a value of 1b indicates that the corresponding Link speed is supported; otherwise the Link speed is.." rbitfld.long 0x2C 0. "RSVDP_0,Reserved for future use." "0,1" line.long 0x30 "LINK_CONTROL2_LINK_STATUS2_REG,Link Control 2 and Status 2 Register." bitfld.long 0x30 31. "DRS_MESSAGE_RECEIVED,DRS Message Received. This bit must be set whenever the Port receives a DRS Message. This bit must be cleared in DL_Down. This bit must be implemented in any Downstream Port where the DRS Supported bit is Set in the Link Capabilities.." "0,1" rbitfld.long 0x30 28.--30. "DOWNSTREAM_COMPO_PRESENCE,Downstream Component Presence. This field indicates the presence and DRS status for the Downstream Component if any connected to the Link; defined values are: - 000b: Link Down - Presence Not Determined - 001b: Link Down -.." "0,1,2,3,4,5,6,7" newline rbitfld.long 0x30 26.--27. "RSVDP_26,Reserved for future use." "0,1,2,3" bitfld.long 0x30 21. "PCIE_CAP_LINK_EQ_REQ,Link Equalization Request 8.0 GT/s. This bit is set by hardware to request the 8.0 GT/s Link equalization process to be performed on the Link. For more details see sections 4.2.3 and 4.2.6.4.2 of PCI Express Base Specification. For.." "0,1" newline rbitfld.long 0x30 20. "PCIE_CAP_EQ_CPL_P3,EEqualization 8.0 GT/s Phase 3 Successful. When set to 1b this bit indicates that Phase 3 of the 8.0 GT/s Transmitter Equalization procedure has successfully completed. Details of the Transmitter Equalization process and when this bit.." "0,1" rbitfld.long 0x30 19. "PCIE_CAP_EQ_CPL_P2,Equalization 8.0 GT/s Phase 2 Successful. When set to 1b this bit indicates that Phase 2 of the 8.0 GT/s Transmitter Equalization procedure has successfully completed. Details of the Transmitter Equalization process and when this bit.." "0,1" newline rbitfld.long 0x30 18. "PCIE_CAP_EQ_CPL_P1,Equalization 8.0 GT/s Phase 1 Successful. When set to 1b this bit indicates that Phase 1 of the 8.0 GT/s Transmitter Equalization procedure has successfully completed. Details of the Transmitter Equalization process and when this bit.." "0,1" rbitfld.long 0x30 17. "PCIE_CAP_EQ_CPL,Equalization 8.0 GT/s Complete. When set to 1b this bit indicates that the Transmitter Equalization procedure at the 8.0 GT/s data rate has completed. Details of the Transmitter Equalization process and when this bit needs to be set to.." "0,1" newline rbitfld.long 0x30 16. "PCIE_CAP_CURR_DEEMPHASIS,Current De-emphasis Level. When the Link is operating at 5.0 GT/s speed this bit reflects the level of de-emphasis. Encodings: - 1b: -3.5 dB - 0b: -6 dB The value in this bit is undefined when the Link is not operating at 5.0.." "0,1" hexmask.long.byte 0x30 12.--15. 1. "PCIE_CAP_COMPLIANCE_PRESET,Compliance Preset/De-emphasis. For 8.0 GT/s and higher Data Rate: This field sets the Transmitter Preset in Polling.Compliance state if the entry occurred due to the Enter Compliance bit being 1b. The encodings are defined in.." newline bitfld.long 0x30 11. "PCIE_CAP_COMPLIANCE_SOS,Compliance SOS. When set to 1b the LTSSM is required to send SKP Ordered Sets between sequences when sending the Compliance Pattern or Modified Compliance Pattern. For a Multi-Function Device associated with an Upstream Port the.." "0,1" bitfld.long 0x30 10. "PCIE_CAP_ENTER_MODIFIED_COMPLIANCE,Enter Modified Compliance. When this bit is set to 1b the device transmits Modified Compliance Pattern if the LTSSM enters Polling.Compliance substate. Components that support only the 2.5 GT/s speed are permitted to.." "0,1" newline bitfld.long 0x30 7.--9. "PCIE_CAP_TX_MARGIN,Transmit Margin - This field controls the value of the non-deemphasized voltage level at the Transmitter pins. This field is reset to 000b on entry to the LTSSM Polling.Configuration substate (see Chapter 4 of PCI Express Base.." "0,1,2,3,4,5,6,7" bitfld.long 0x30 6. "PCIE_CAP_SEL_DEEMPHASIS,Selectable De-emphasis. When the Link is operating at 5.0 GT/s speed this bit is used to control the transmit de-emphasis of the link in specific situations. For more details see section 4.2.6 of PCI Express Base Specification." "0,1" newline bitfld.long 0x30 5. "PCIE_CAP_HW_AUTO_SPEED_DISABLE,Hardware Autonomous Speed Disable. When set this bit disables hardware from changing the Link speed for device-specific reasons other than attempting to correct unreliable Link operation by reducing Link speed. Initial.." "0,1" bitfld.long 0x30 4. "PCIE_CAP_ENTER_COMPLIANCE,Enter Compliance. Software is permitted to force a Link to enter Compliance mode (at the speed indicated in the Target Link Speed field and the de-emphasis/preset level indicated by the Compliance Preset/De-emphasis field) by.." "0,1" newline hexmask.long.byte 0x30 0.--3. 1. "PCIE_CAP_TARGET_LINK_SPEED,Target Link Speed. For Downstream Ports this field sets an upper limit on Link operational speed by restricting the values advertised by the Upstream component in its training sequences. The encoded value specifies a bit.." tree.end tree "PF0_AER_CAP (PF Advanced Error Reporting Capability Structure)" group.long (0x0+0x100)++0x1B line.long 0x0 "AER_EXT_CAP_HDR_OFF,Advanced Error Reporting Extended Capability Header. For a description of this standard PCIe register. see the PCI Express Specification." hexmask.long.word 0x0 20.--31. 1. "NEXT_OFFSET,Next Capability Offset. For a description of this standard PCIe register field see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky).." hexmask.long.byte 0x0 16.--19. 1. "CAP_VERSION,Capability Version. For a description of this standard PCIe register field see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else.." hexmask.long.word 0x0 0.--15. 1. "CAP_ID,AER Extended Capability ID. For a description of this standard PCIe register field see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else.." line.long 0x4 "UNCORR_ERR_STATUS_OFF,Uncorrectable Error Status Register. For a description of this standard PCIe register. see the PCI Express Specification." hexmask.long.byte 0x4 27.--31. 1. "RSVDP_27,Reserved for future use." bitfld.long 0x4 25. "TLP_PRFX_BLOCKED_ERR_STATUS,TLP Prefix Blocked Error Status. For a description of this standard PCIe register field see the PCI Express Specification. Note: Not supported." "0,1" rbitfld.long 0x4 23. "RSVDP_23,Reserved for future use." "0,1" newline bitfld.long 0x4 22. "INTERNAL_ERR_STATUS,Uncorrectable Internal Error Status. For a description of this standard PCIe register field see the PCI Express Specification. The controller sets this bit when your application asserts app_err_bus[9]. It does not set this bit when.." "0,1" bitfld.long 0x4 20. "UNSUPPORTED_REQ_ERR_STATUS,Unsupported Request Error Status. For a description of this standard PCIe register field see the PCI Express Specification." "0,1" bitfld.long 0x4 19. "ECRC_ERR_STATUS,ECRC Error Status. For a description of this standard PCIe register field see the PCI Express Specification. Note:If CX_ECRC_ENABLE=0 the register field always reads 0." "0,1" newline bitfld.long 0x4 18. "MALF_TLP_ERR_STATUS,Malformed TLP Status. For a description of this standard PCIe register field see the PCI Express Specification." "0,1" bitfld.long 0x4 17. "REC_OVERFLOW_ERR_STATUS,Receiver Overflow Status. For a description of this standard PCIe register field see the PCI Express Specification." "0,1" bitfld.long 0x4 16. "UNEXP_CMPLT_ERR_STATUS,Unexpected Completion Status. For a description of this standard PCIe register field see the PCI Express Specification." "0,1" newline bitfld.long 0x4 15. "CMPLT_ABORT_ERR_STATUS,Completer Abort Status. For a description of this standard PCIe register field see the PCI Express Specification." "0,1" bitfld.long 0x4 14. "CMPLT_TIMEOUT_ERR_STATUS,Completion Timeout Status. For a description of this standard PCIe register field see the PCI Express Specification." "0,1" bitfld.long 0x4 13. "FC_PROTOCOL_ERR_STATUS,Flow Control Protocol Error Status. For a description of this standard PCIe register field see the PCI Express Specification." "0,1" newline bitfld.long 0x4 12. "POIS_TLP_ERR_STATUS,Poisoned TLP Status. For a description of this standard PCIe register field see the PCI Express Specification." "0,1" hexmask.long.byte 0x4 6.--11. 1. "RSVDP_6,Reserved for future use." bitfld.long 0x4 5. "SURPRISE_DOWN_ERR_STATUS,Surprise Down Error Status (Optional). For a description of this standard PCIe register field see the PCI Express Specification." "0,1" newline bitfld.long 0x4 4. "DL_PROTOCOL_ERR_STATUS,Data Link Protocol Error Status. For a description of this standard PCIe register field see the PCI Express Specification." "0,1" hexmask.long.byte 0x4 0.--3. 1. "RSVDP_0,Reserved for future use." line.long 0x8 "UNCORR_ERR_MASK_OFF,Uncorrectable Error Mask Register. For a description of this standard PCIe register. see the PCI Express Specification." hexmask.long.byte 0x8 27.--31. 1. "RSVDP_27,Reserved for future use." bitfld.long 0x8 25. "TLP_PRFX_BLOCKED_ERR_MASK,TLP Prefix Blocked Error Mask. For a description of this standard PCIe register field see the PCI Express Specification. Note: Not supported. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi:.." "0,1" rbitfld.long 0x8 23. "RSVDP_23,Reserved for future use." "0,1" newline bitfld.long 0x8 22. "INTERNAL_ERR_MASK,Uncorrectable Internal Error Mask (Optional). For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." "0,1" rbitfld.long 0x8 21. "ACS_VIOLATION_MASK,ACS Violation Mask. Setting the ACS Violation Mask bit disables error logging and signaling for ACS Violation errors. The bit is Read-Only Zero for upstream ports when ACS P2P Egress Control Enable is not set. For a description of.." "0,1" bitfld.long 0x8 20. "UNSUPPORTED_REQ_ERR_MASK,Unsupported Request Error Mask. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." "0,1" newline bitfld.long 0x8 19. "ECRC_ERR_MASK,ECRC Error Mask (Optional). For a description of this standard PCIe register field see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W (sticky) Note: This register.." "0,1" bitfld.long 0x8 18. "MALF_TLP_ERR_MASK,Malformed TLP Mask. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." "0,1" bitfld.long 0x8 17. "REC_OVERFLOW_ERR_MASK,Receiver Overflow Mask (Optional). For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." "0,1" newline bitfld.long 0x8 16. "UNEXP_CMPLT_ERR_MASK,Unexpected Completion Mask. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." "0,1" bitfld.long 0x8 15. "CMPLT_ABORT_ERR_MASK,Completer Abort Error Mask (Optional). For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." "0,1" bitfld.long 0x8 14. "CMPLT_TIMEOUT_ERR_MASK,Completion Timeout Error Mask. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." "0,1" newline bitfld.long 0x8 13. "FC_PROTOCOL_ERR_MASK,Flow Control Protocol Error Mask. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." "0,1" bitfld.long 0x8 12. "POIS_TLP_ERR_MASK,Poisoned TLP Error Mask. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." "0,1" hexmask.long.byte 0x8 6.--11. 1. "RSVDP_6,Reserved for future use." newline rbitfld.long 0x8 5. "SURPRISE_DOWN_ERR_MASK,Surprise Down Error Mask. For a description of this standard PCIe register field see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi:.." "0,1" bitfld.long 0x8 4. "DL_PROTOCOL_ERR_MASK,Data Link Protocol Error Mask. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." "0,1" hexmask.long.byte 0x8 0.--3. 1. "RSVDP_0,Reserved for future use." line.long 0xC "UNCORR_ERR_SEV_OFF,Uncorrectable Error Severity Register. For a description of this standard PCIe register. see the PCI Express Specification." hexmask.long.byte 0xC 27.--31. 1. "RSVDP_27,Reserved for future use." bitfld.long 0xC 25. "TLP_PRFX_BLOCKED_ERR_SEVERITY,TLP Prefix Blocked Error Severity (Optional). For a description of this standard PCIe register field see the PCI Express Specification. Note: Not supported. Note: The access attributes of this field are as follows: - Wire:.." "0,1" rbitfld.long 0xC 24. "ATOMIC_EGRESS_BLOCKED_ERR_SEVERITY,AtomicOp Egress Blocked Severity (Optional). For a description of this standard PCIe register field see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi:.." "0,1" newline rbitfld.long 0xC 23. "RSVDP_23,Reserved for future use." "0,1" bitfld.long 0xC 22. "INTERNAL_ERR_SEVERITY,Uncorrectable Internal Error Severity (Optional). For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." "0,1" bitfld.long 0xC 20. "UNSUPPORTED_REQ_ERR_SEVERITY,Unsupported Request Error Severity. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." "0,1" newline bitfld.long 0xC 19. "ECRC_ERR_SEVERITY,ECRC Error Severity (Optional). For a description of this standard PCIe register field see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W (sticky) Note: This.." "0,1" bitfld.long 0xC 18. "MALF_TLP_ERR_SEVERITY,Malformed TLP Severity. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." "0,1" bitfld.long 0xC 17. "REC_OVERFLOW_ERR_SEVERITY,Receiver Overflow Error Severity (Optional). For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." "0,1" newline bitfld.long 0xC 16. "UNEXP_CMPLT_ERR_SEVERITY,Unexpected Completion Error Severity. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." "0,1" bitfld.long 0xC 15. "CMPLT_ABORT_ERR_SEVERITY,Completer Abort Error Severity (Optional). For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." "0,1" bitfld.long 0xC 14. "CMPLT_TIMEOUT_ERR_SEVERITY,Completion Timeout Error Severity. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." "0,1" newline bitfld.long 0xC 13. "FC_PROTOCOL_ERR_SEVERITY,Flow Control Protocol Error Severity (Optional). For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." "0,1" bitfld.long 0xC 12. "POIS_TLP_ERR_SEVERITY,Poisoned TLP Severity. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." "0,1" hexmask.long.byte 0xC 6.--11. 1. "RSVDP_6,Reserved for future use." newline rbitfld.long 0xC 5. "SURPRISE_DOWN_ERR_SVRITY,Surprise Down Error Severity (Optional). For a description of this standard PCIe register field see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi:.." "0,1" bitfld.long 0xC 4. "DL_PROTOCOL_ERR_SEVERITY,Data Link Protocol Error Severity. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." "0,1" hexmask.long.byte 0xC 0.--3. 1. "RSVDP_0,Reserved for future use." line.long 0x10 "CORR_ERR_STATUS_OFF,Correctable Error Status Register. For a description of this standard PCIe register. see the PCI Express Specification." hexmask.long.word 0x10 16.--31. 1. "RSVDP_16,Reserved for future use." bitfld.long 0x10 15. "HEADER_LOG_OVERFLOW_STATUS,Header Log Overflow Error Status (Optional). For a description of this standard PCIe register field see the PCI Express Specification." "0,1" bitfld.long 0x10 14. "CORRECTED_INT_ERR_STATUS,Corrected Internal Error Status (Optional). For a description of this standard PCIe register field see the PCI Express Specification." "0,1" newline bitfld.long 0x10 13. "ADVISORY_NON_FATAL_ERR_STATUS,Advisory Non-Fatal Error Status. For a description of this standard PCIe register field see the PCI Express Specification." "0,1" bitfld.long 0x10 12. "RPL_TIMER_TIMEOUT_STATUS,Replay Timer Timeout Status. For a description of this standard PCIe register field see the PCI Express Specification." "0,1" rbitfld.long 0x10 9.--11. "RSVDP_9,Reserved for future use." "0,1,2,3,4,5,6,7" newline bitfld.long 0x10 8. "REPLAY_NO_ROLEOVER_STATUS,REPLAY_NUM Rollover Status. For a description of this standard PCIe register field see the PCI Express Specification." "0,1" bitfld.long 0x10 7. "BAD_DLLP_STATUS,Bad DLLP Status. For a description of this standard PCIe register field see the PCI Express Specification." "0,1" bitfld.long 0x10 6. "BAD_TLP_STATUS,Bad TLP Status. For a description of this standard PCIe register field see the PCI Express Specification." "0,1" newline hexmask.long.byte 0x10 1.--5. 1. "RSVDP_1,Reserved for future use." bitfld.long 0x10 0. "RX_ERR_STATUS,Receiver Error Status (Optional). For a description of this standard PCIe register field see the PCI Express Specification." "0,1" line.long 0x14 "CORR_ERR_MASK_OFF,Correctable Error Mask Register. For a description of this standard PCIe register. see the PCI Express Specification." hexmask.long.word 0x14 16.--31. 1. "RSVDP_16,Reserved for future use." bitfld.long 0x14 15. "HEADER_LOG_OVERFLOW_MASK,Header Log Overflow Error Mask (Optional). For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." "0,1" bitfld.long 0x14 14. "CORRECTED_INT_ERR_MASK,Corrected Internal Error Mask (Optional). For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." "0,1" newline bitfld.long 0x14 13. "ADVISORY_NON_FATAL_ERR_MASK,Advisory Non-Fatal Error Mask. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." "0,1" bitfld.long 0x14 12. "RPL_TIMER_TIMEOUT_MASK,Replay Timer Timeout Mask. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." "0,1" rbitfld.long 0x14 9.--11. "RSVDP_9,Reserved for future use." "0,1,2,3,4,5,6,7" newline bitfld.long 0x14 8. "REPLAY_NO_ROLEOVER_MASK,REPLAY_NUM Rollover Mask. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." "0,1" bitfld.long 0x14 7. "BAD_DLLP_MASK,Bad DLLP Mask. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." "0,1" bitfld.long 0x14 6. "BAD_TLP_MASK,Bad TLP Mask. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." "0,1" newline hexmask.long.byte 0x14 1.--5. 1. "RSVDP_1,Reserved for future use." bitfld.long 0x14 0. "RX_ERR_MASK,Receiver Error Mask (Optional). For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." "0,1" line.long 0x18 "ADV_ERR_CAP_CTRL_OFF,Advanced Error Capabilities and Control Register. For a description of this standard PCIe register. see the PCI Express Specification." hexmask.long.tbyte 0x18 13.--31. 1. "RSVDP_13,Reserved for future use." rbitfld.long 0x18 12. "CTO_PRFX_HDR_LOG_CAP,TLP Prefix Log Present. For a description of this standard PCIe register field see the PCI Express Specification." "0,1" rbitfld.long 0x18 11. "TLP_PRFX_LOG_PRESENT,Completion Timeout Prefix/Header Log Capable. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." "0,1" newline rbitfld.long 0x18 10. "MULTIPLE_HEADER_EN,Multiple Header Recording Enable. For a description of this standard PCIe register field see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R (sticky) Note: This.." "0,1" rbitfld.long 0x18 9. "MULTIPLE_HEADER_CAP,Multiple Header Recording Capable. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." "0,1" bitfld.long 0x18 8. "ECRC_CHECK_EN,ECRC Check Enable. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." "0,1" newline rbitfld.long 0x18 7. "ECRC_CHECK_CAP,ECRC Check Capable. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." "0,1" bitfld.long 0x18 6. "ECRC_GEN_EN,ECRC Generation Enable. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." "0,1" rbitfld.long 0x18 5. "ECRC_GEN_CAP,ECRC Generation Capable. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." "0,1" newline hexmask.long.byte 0x18 0.--4. 1. "FIRST_ERR_POINTER,First Error Pointer. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." rgroup.long (0x1C+0x100)++0xF line.long 0x0 "HDR_LOG_0_OFF,Header Log Register 0. For a description of this standard PCIe register. see the PCI Express Specification." hexmask.long.byte 0x0 24.--31. 1. "FIRST_DWORD_FOURTH_BYTE,Byte 3 of Header log register of First 32 bit Data Word. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." hexmask.long.byte 0x0 16.--23. 1. "FIRST_DWORD_THIRD_BYTE,Byte 2 of Header log register of First 32 bit Data Word. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." hexmask.long.byte 0x0 8.--15. 1. "FIRST_DWORD_SECOND_BYTE,Byte 1 of Header log register of First 32 bit Data Word. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." newline hexmask.long.byte 0x0 0.--7. 1. "FIRST_DWORD_FIRST_BYTE,Byte 0 of Header log register of First 32 bit Data Word. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." line.long 0x4 "HDR_LOG_1_OFF,Header Log Register 1. For a description of this standard PCIe register. see the PCI Express Specification." hexmask.long.byte 0x4 24.--31. 1. "SECOND_DWORD_FOURTH_BYTE,Byte 3 of Header log register of Second 32 bit Data Word. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." hexmask.long.byte 0x4 16.--23. 1. "SECOND_DWORD_THIRD_BYTE,Byte 2 of Header log register of Second 32 bit Data Word. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." hexmask.long.byte 0x4 8.--15. 1. "SECOND_DWORD_SECOND_BYTE,Byte 1 of Header log register of Second 32 bit Data Word. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." newline hexmask.long.byte 0x4 0.--7. 1. "SECOND_DWORD_FIRST_BYTE,Byte 0 of Header log register of Second 32 bit Data Word. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." line.long 0x8 "HDR_LOG_2_OFF,Header Log Register 2. For a description of this standard PCIe register. see the PCI Express Specification." hexmask.long.byte 0x8 24.--31. 1. "THIRD_DWORD_FOURTH_BYTE,Byte 3 of Header log register of Third 32 bit Data Word. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." hexmask.long.byte 0x8 16.--23. 1. "THIRD_DWORD_THIRD_BYTE,Byte 2 of Header log register of Third 32 bit Data Word. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." hexmask.long.byte 0x8 8.--15. 1. "THIRD_DWORD_SECOND_BYTE,Byte 1 of Header log register of Third 32 bit Data Word. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." newline hexmask.long.byte 0x8 0.--7. 1. "THIRD_DWORD_FIRST_BYTE,Byte 0 of Header log register of Third 32 bit Data Word. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." line.long 0xC "HDR_LOG_3_OFF,Header Log Register 3. For a description of this standard PCIe register. see the PCI Express Specification." hexmask.long.byte 0xC 24.--31. 1. "FOURTH_DWORD_FOURTH_BYTE,Byte 3 of Header log register of Fourth 32 bit Data Word. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." hexmask.long.byte 0xC 16.--23. 1. "FOURTH_DWORD_THIRD_BYTE,Byte 2 of Header log register of Fourth 32 bit Data Word. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." hexmask.long.byte 0xC 8.--15. 1. "FOURTH_DWORD_SECOND_BYTE,Byte 1 of Header log register of Fourth 32 bit Data Word. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." newline hexmask.long.byte 0xC 0.--7. 1. "FOURTH_DWORD_FIRST_BYTE,Byte 0 of Header log register of Fourth 32 bit Data Word. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." group.long (0x2C+0x100)++0x7 line.long 0x0 "ROOT_ERR_CMD_OFF,Root Error Command Register. For a description of this standard PCIe register. see the PCI Express Specification." hexmask.long 0x0 3.--31. 1. "RSVDP_3,Reserved for future use." bitfld.long 0x0 2. "FATAL_ERR_REPORTING_EN,Fatal Error Reporting Enable. For a description of this standard PCIe register field see the PCI Express Specification." "0,1" bitfld.long 0x0 1. "NON_FATAL_ERR_REPORTING_EN,Non-Fatal Error Reporting Enable. For a description of this standard PCIe register field see the PCI Express Specification." "0,1" newline bitfld.long 0x0 0. "CORR_ERR_REPORTING_EN,Correctable Error Reporting Enable. For a description of this standard PCIe register field see the PCI Express Specification." "0,1" line.long 0x4 "ROOT_ERR_STATUS_OFF,Root Error Status Register. For a description of this standard PCIe register. see the PCI Express Specification." hexmask.long.byte 0x4 27.--31. 1. "ADV_ERR_INT_MSG_NUM,Advanced Error Interrupt Message Number. For a description of this standard PCIe register field see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN.." hexmask.long.tbyte 0x4 7.--26. 1. "RSVDP_7,Reserved for future use." bitfld.long 0x4 6. "FATAL_ERR_MSG_RX,One or more Fatal Error Messages Received. For a description of this standard PCIe register field see the PCI Express Specification." "0,1" newline bitfld.long 0x4 5. "NON_FATAL_ERR_MSG_RX,One or more Non-Fatal Error Messages Received. For a description of this standard PCIe register field see the PCI Express Specification." "0,1" bitfld.long 0x4 4. "FIRST_UNCORR_FATAL,First Uncorrectable Error is Fatal. For a description of this standard PCIe register field see the PCI Express Specification." "0,1" bitfld.long 0x4 3. "MUL_ERR_FATAL_NON_FATAL_RX,Multiple Fatal or Non-Fatal Errors Received. For a description of this standard PCIe register field see the PCI Express Specification." "0,1" newline bitfld.long 0x4 2. "ERR_FATAL_NON_FATAL_RX,Fatal or Non-Fatal Error Received. For a description of this standard PCIe register field see the PCI Express Specification." "0,1" bitfld.long 0x4 1. "MUL_ERR_COR_RX,Multiple Correctable Errors Received. For a description of this standard PCIe register field see the PCI Express Specification." "0,1" bitfld.long 0x4 0. "ERR_COR_RX,Correctable Error Received. For a description of this standard PCIe register field see the PCI Express Specification." "0,1" rgroup.long (0x34+0x100)++0x13 line.long 0x0 "ERR_SRC_ID_OFF,Error Source Identification Register. For a description of this standard PCIe register. see the PCI Express Specification." hexmask.long.word 0x0 16.--31. 1. "ERR_FATAL_NON_FATAL_SOURCE_ID,Source of Fatal/Non-Fatal Error. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." hexmask.long.word 0x0 0.--15. 1. "ERR_COR_SOURCE_ID,Source of Correctable Error. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." line.long 0x4 "TLP_PREFIX_LOG_1_OFF,TLP Prefix Log Register 1. For a description of this standard PCIe register. see the PCI Express Specification." hexmask.long.byte 0x4 24.--31. 1. "CFG_TLP_PFX_LOG_1_FOURTH_BYTE,Byte 3 of Error TLP Prefix Log 1. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." hexmask.long.byte 0x4 16.--23. 1. "CFG_TLP_PFX_LOG_1_THIRD_BYTE,Byte 2 of Error TLP Prefix Log 1. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." hexmask.long.byte 0x4 8.--15. 1. "CFG_TLP_PFX_LOG_1_SECOND_BYTE,Byte 1 of Error TLP Prefix Log 1. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." newline hexmask.long.byte 0x4 0.--7. 1. "CFG_TLP_PFX_LOG_1_FIRST_BYTE,Byte 0 of Error TLP Prefix Log 1. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." line.long 0x8 "TLP_PREFIX_LOG_2_OFF,TLP Prefix Log Register 2. For a description of this standard PCIe register. see the PCI Express Specification." hexmask.long.byte 0x8 24.--31. 1. "CFG_TLP_PFX_LOG_2_FOURTH_BYTE,Byte 3 Error TLP Prefix Log 2. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." hexmask.long.byte 0x8 16.--23. 1. "CFG_TLP_PFX_LOG_2_THIRD_BYTE,Byte 2 Error TLP Prefix Log 2. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." hexmask.long.byte 0x8 8.--15. 1. "CFG_TLP_PFX_LOG_2_SECOND_BYTE,Byte 1 Error TLP Prefix Log 2. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." newline hexmask.long.byte 0x8 0.--7. 1. "CFG_TLP_PFX_LOG_2_FIRST_BYTE,Byte 0 Error TLP Prefix Log 2. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." line.long 0xC "TLP_PREFIX_LOG_3_OFF,TLP Prefix Log Register 3. For a description of this standard PCIe register. see the PCI Express Specification." hexmask.long.byte 0xC 24.--31. 1. "CFG_TLP_PFX_LOG_3_FOURTH_BYTE,Byte 3 Error TLP Prefix Log 3. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." hexmask.long.byte 0xC 16.--23. 1. "CFG_TLP_PFX_LOG_3_THIRD_BYTE,Byte 2 Error TLP Prefix Log 3. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." hexmask.long.byte 0xC 8.--15. 1. "CFG_TLP_PFX_LOG_3_SECOND_BYTE,Byte 1 Error TLP Prefix Log 3. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." newline hexmask.long.byte 0xC 0.--7. 1. "CFG_TLP_PFX_LOG_3_FIRST_BYTE,Byte 0 Error TLP Prefix Log 3. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." line.long 0x10 "TLP_PREFIX_LOG_4_OFF,TLP Prefix Log Register 4. For a description of this standard PCIe register. see the PCI Express Specification." hexmask.long.byte 0x10 24.--31. 1. "CFG_TLP_PFX_LOG_4_FOURTH_BYTE,Byte 3 Error TLP Prefix Log 4. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." hexmask.long.byte 0x10 16.--23. 1. "CFG_TLP_PFX_LOG_4_THIRD_BYTE,Byte 2 Error TLP Prefix Log 4. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." hexmask.long.byte 0x10 8.--15. 1. "CFG_TLP_PFX_LOG_4_SECOND_BYTE,Byte 1 Error TLP Prefix Log 4. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." newline hexmask.long.byte 0x10 0.--7. 1. "CFG_TLP_PFX_LOG_4_FIRST_BYTE,Byte 0 Error TLP Prefix Log 4. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." tree.end tree "PF0_MSI_CAP (PF MSI Capability Structure)" group.long (0x0+0x50)++0x13 line.long 0x0 "PCI_MSI_CAP_ID_NEXT_CTRL_REG,MSI Capability Header and Message Control Register." hexmask.long.byte 0x0 27.--31. 1. "RSVDP_27,Reserved for future use." bitfld.long 0x0 26. "PCI_MSI_EXT_DATA_EN,Extended Message Data Enable. - If set the function is enabled to provide Extended Message Data. - If clear the function is not enabled to provide Extended Message Data. Note: The access attributes of this field are as follows: -.." "0,1" bitfld.long 0x0 25. "PCI_MSI_EXT_DATA_CAP,Extended Message Data Capable. - If set the function is capable of providing Extended Message Data. - If clear the function does not support providing Extended Message Data. Note: The access attributes of this field are as follows:.." "0,1" newline rbitfld.long 0x0 24. "PCI_PVM_SUPPORT,Per-Vector Masking Capable. - If set the function supports MSI Per-Vector Masking. - If clear the function does not support MSI Per-Vector Masking. This bit must be set if the function is a PF or VF within an SR-IOV Device." "0,1" bitfld.long 0x0 23. "PCI_MSI_64_BIT_ADDR_CAP,64 bit address capable. - If set the function is capable of sending a 64-bit message address. - If clear the function is not capable of sending a 64-bit message address. This bit must be set if the function is a PCI Express.." "0,1" bitfld.long 0x0 20.--22. "PCI_MSI_MULTIPLE_MSG_EN,Multiple Message Enable. Software writes to this field to indicate the number of allocated vectors (equal to or less than the number of requested vectors). The number of allocated vectors is aligned to a power of two. If a.." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 17.--19. "PCI_MSI_MULTIPLE_MSG_CAP,Multiple Message Capable. System software reads this field to determine the number of requested vectors. The number of requested vectors must be aligned to a power of two (if a function requires three vectors it requests four by.." "0,1,2,3,4,5,6,7" bitfld.long 0x0 16. "PCI_MSI_ENABLE,MSI Enable. - If set and the MSI-X Enable bit in the MSI-X Message Control register is clear the function is permitted to use MSI to request service and is prohibited from using INTx interrupts. System configuration software sets this bit.." "0,1" hexmask.long.byte 0x0 8.--15. 1. "PCI_MSI_CAP_NEXT_OFFSET,Next Capability Pointer. This field contains the offset to the next PCI Capability structure or 00h if no other items exist in the linked list of Capabilities. Note: The access attributes of this field are as follows: - Wire: No.." newline hexmask.long.byte 0x0 0.--7. 1. "PCI_MSI_CAP_ID,Capability ID. Indicates the MSI Capability structure. This field returns a Capability ID of 05h indicating that this is an MSI Capability structure." line.long 0x4 "MSI_CAP_OFF_04H_REG,Message Address Register for MSI (Offset 04h)." hexmask.long 0x4 2.--31. 1. "PCI_MSI_CAP_OFF_04H,Message Address - System-specified message address. If the Message Enable bit (bit 16 of the PCI_MSI_CAP_ID_NEXT_CTRL_REG register) is set the contents of this field specify the DWORD-aligned address (Address[31:02]) for the MSI.." rbitfld.long 0x4 0.--1. "RSVDP_0,Reserved for future use." "0,1,2,3" line.long 0x8 "MSI_CAP_OFF_08H_REG,For a function that supports a 32-bit message address. - bits[31:16] of this register represent the Extended Message Data. and - bits[15:0] of this register represent the Message Data For a function that supports a 64-bit message.." hexmask.long.word 0x8 16.--31. 1. "PCI_MSI_CAP_OFF_0AH,For a function that supports a 32-bit message address this field contains Extended Message Data (System-specified message data). For the MSI Capability structures without per-vector masking it must be implemented if the Extended.." hexmask.long.word 0x8 0.--15. 1. "PCI_MSI_CAP_OFF_08H,For a function that supports a 32-bit message address this field contains Message Data (System-specified message data). If the Message Enable bit (bit 16 of the PCI_MSI_CAP_ID_NEXT_CTRL_REG) is set the function sends a DWORD Memory.." line.long 0xC "MSI_CAP_OFF_0CH_REG,For a function that supports a 32-bit message address. this register contains the Mask Bits when the Per-Vector Masking Capable bit (bit 24 of PCI_MSI_CAP_ID_NEXT_CTRL_REG) is set. For a function that supports a 64-bit message.." hexmask.long.word 0xC 16.--31. 1. "PCI_MSI_CAP_OFF_0EH,For a function that supports a 32-bit message address this field contains the upper Mask Bits when the Per Vector Masking Capable bit (PCI_MSI_CAP_ID_NEXT_CTRL_REG.PCI_PVM_SUPPORT) is set. For a function that supports a 64-bit.." hexmask.long.word 0xC 0.--15. 1. "PCI_MSI_CAP_OFF_0CH,For a function that supports a 32-bit message address this field contains the lower Mask Bits when the Per Vector Masking Capable bit (PCI_MSI_CAP_ID_NEXT_CTRL_REG.PCI_PVM_SUPPORT) is set. For a function that supports a 64-bit.." line.long 0x10 "MSI_CAP_OFF_10H_REG,For a function that supports a 32-bit message address. this register contains the Pending Bits when the Per-Vector Masking Capable bit (bit 24 of PCI_MSI_CAP_ID_NEXT_CTRL_REG) is set. For a function that supports a 64-bit message.." hexmask.long 0x10 0.--31. 1. "PCI_MSI_CAP_OFF_10H,Used for MSI when the Per Vector Masking Capable bit (PCI_MSI_CAP_ID_NEXT_CTRL_REG.PCI_PVM_SUPPORT) is set. For 32-bit contains Pending Bits. For 64-bit contains Mask Bits. For a description of this standard PCIe register field see.." rgroup.long (0x14+0x50)++0x3 line.long 0x0 "MSI_CAP_OFF_14H_REG,Pending Bits Register for MSI. This register is used for a function that supports a 64-bit message address when the Per-Vector Masking Capable bit (bit 24 of PCI_MSI_CAP_ID_NEXT_CTRL_REG) is set." hexmask.long 0x0 0.--31. 1. "PCI_MSI_CAP_OFF_14H,Pending Bits. For each pending bit that is set the function has a pending associated message." tree.end tree "PF0_MSIX_CAP (PF MSI-X Capability Structure)" group.long (0x0+0xB0)++0xB line.long 0x0 "PCI_MSIX_CAP_ID_NEXT_CTRL_REG,MSI-X Capability ID. Next Pointer. Control Registers. For a description of this standard PCIe register. see the PCI Express Base Specification." bitfld.long 0x0 31. "PCI_MSIX_ENABLE,MSI-X Enable. For a description of this standard PCIe register field see the PCI Express Base Specification." "0,1" bitfld.long 0x0 30. "PCI_MSIX_FUNCTION_MASK,Function Mask. For a description of this standard PCIe register field see the PCI Express Base Specification. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" "0,1" rbitfld.long 0x0 27.--29. "RSVDP_27,Reserved for future use." "0,1,2,3,4,5,6,7" newline hexmask.long.word 0x0 16.--26. 1. "PCI_MSIX_TABLE_SIZE,MSI-X Table Size. For a description of this standard PCIe register field see the PCI Express Base Specification. SRIOV Note: All VFs in a single PF have the same value for 'MSI-X Table Size' (PCI_MSIX_TABLE_SIZE field in.." hexmask.long.byte 0x0 8.--15. 1. "PCI_MSIX_CAP_NEXT_OFFSET,MSI-X Next Capability Pointer. For a description of this standard PCIe register field see the PCI Express Base Specification. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN.." hexmask.long.byte 0x0 0.--7. 1. "PCI_MSIX_CAP_ID,MSI-X Capability ID. For a description of this standard PCIe register field see the PCI Express Base Specification." line.long 0x4 "MSIX_TABLE_OFFSET_REG,MSI-X Table Offset and BIR Register. For a description of this standard PCIe register. see the PCI Express Base Specification." hexmask.long 0x4 3.--31. 1. "PCI_MSIX_TABLE_OFFSET,MSI-X Table Offset. For a description of this standard PCIe register field see the PCI Express Base Specification. SRIOV Note: All VFs in a single PF have the same value for 'MSI-X Table Offset' (PCI_MSIX_TABLE_OFFSET field in.." bitfld.long 0x4 0.--2. "PCI_MSIX_BIR,MSI-X Table BAR Indicator Register Field. For a description of this standard PCIe register field see the PCI Express Base Specification. SRIOV Note: All VFs in a single PF have the same value for 'MSI-X Table BAR Indicator Register'.." "0,1,2,3,4,5,6,7" line.long 0x8 "MSIX_PBA_OFFSET_REG,MSI-X PBA Offset and BIR Register. For a description of this standard PCIe register. see the PCI Express Base Specification." hexmask.long 0x8 3.--31. 1. "PCI_MSIX_PBA_OFFSET,MSI-X PBA Offset. For a description of this standard PCIe register field see the PCI Express Base Specification. SRIOV Note: All VFs in a single PF have the same value for 'MSI-X PBA Offset' (PCI_MSIX_PBA_OFFSET field in.." bitfld.long 0x8 0.--2. "PCI_MSIX_PBA_BIR,MSI-X PBA BIR. For a description of this standard PCIe register field see the PCI Express Base Specification. SRIOV Note: All VFs in a single PF have the same value for 'MSI-X PBA BIR' (PCI_MSIX_PBA_BIR field in.." "0,1,2,3,4,5,6,7" tree.end tree "PF0_MSIX_CAP_DBI2 (DBI2 Shadow Block: PF MSI-X Capability Structure)" rgroup.long (0x0+0x10B0)++0x3 line.long 0x0 "SHADOW_PCI_MSIX_CAP_ID_NEXT_CTRL_REG,MSI-X Capability ID. Next Pointer. Control Registers. For a description of this standard PCIe register. see the PCI Express Base Specification." hexmask.long.byte 0x0 27.--31. 1. "RSVDP_27,Reserved for future use." hexmask.long.word 0x0 16.--26. 1. "PCI_MSIX_TABLE_SIZE,MSI-X Table Size in the shadow register. Note: The access attributes of this field are as follows: - Wire: No access - Dbi: No access - Dbi2: if (DBI_RO_WR_EN == 1) then R/W else R Note: This register field is sticky." hexmask.long.word 0x0 0.--15. 1. "RSVDP_0,Reserved for future use." group.long 0x4++0x7 line.long 0x0 "SHADOW_MSIX_TABLE_OFFSET_REG,MSI-X Table Offset and BIR Register. For a description of this standard PCIe register. see the PCI Express Base Specification." hexmask.long 0x0 3.--31. 1. "PCI_MSIX_TABLE_OFFSET,MSI-X Table Offset. For a description of this standard PCIe register field see the PCI Express Base Specification. Note: The access attributes of this field are as follows: - Wire: No access - Dbi: No access - Dbi2: if.." bitfld.long 0x0 0.--2. "PCI_MSIX_BIR,MSI-X Table BAR Indicator Register Field. For a description of this standard PCIe register field see the PCI Express Base Specification. Note: The access attributes of this field are as follows: - Wire: No access - Dbi: No access - Dbi2: if.." "?,?,if,?,?,?,?,?" line.long 0x4 "SHADOW_MSIX_PBA_OFFSET_REG,MSI-X PBA Offset and BIR Register. For a description of this standard PCIe register. see the PCI Express Base Specification." hexmask.long 0x4 3.--31. 1. "PCI_MSIX_PBA_OFFSET,MSI-X PBA Offset. For a description of this standard PCIe register field see the PCI Express Base Specification. Note: The access attributes of this field are as follows: - Wire: No access - Dbi: No access - Dbi2: if (DBI_RO_WR_EN ==.." bitfld.long 0x4 0.--2. "PCI_MSIX_PBA_BIR,MSI-X PBA BIR. For a description of this standard PCIe register field see the PCI Express Base Specification. Note: The access attributes of this field are as follows: - Wire: No access - Dbi: No access - Dbi2: if (DBI_RO_WR_EN == 1 &&.." "?,?,if,?,?,?,?,?" tree.end tree "PF0_DMA_CAP (DMA Port Logic Structure)" group.long (0x0+0xC8000)++0x3 line.long 0x0 "DMA_CTRL_DATA_ARB_PRIOR_OFF,DMA Arbitration Scheme for TRGT1 Interface. This register is used to control traffic priorities among various sources that are delivered to your application through TRGT1 where 0x0 represents the highest priority. - Non-DMA Rx.." hexmask.long.tbyte 0x0 12.--31. 1. "RSVDP_12,Reserved for future use." bitfld.long 0x0 9.--11. "RDBUFF_TRGT_WEIGHT,DMA Read Channel MWr Requests. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 6.--8. "RD_CTRL_TRGT_WEIGHT,DMA Read Channel MRd Requests. For LL element/descriptor access. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" "0,1,2,3,4,5,6,7" bitfld.long 0x0 3.--5. "WR_CTRL_TRGT_WEIGHT,DMA Write Channel MRd Requests. For DMA data requests and LL element/descriptor access. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 0.--2. "RTRGT1_WEIGHT,Non-DMA Rx Requests. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" "0,1,2,3,4,5,6,7" group.long (0x8+0xC8000)++0xB line.long 0x0 "DMA_CTRL_OFF,DMA Number of Channels Register." hexmask.long.byte 0x0 26.--31. 1. "RSVDP_26,Reserved for future use." bitfld.long 0x0 25. "DIS_C2W_CACHE_RD,Disable DMA Read Channels 'completion to memory write' context cache pre-fetch function. Note: For internal debugging only. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" "0,1" newline bitfld.long 0x0 24. "DIS_C2W_CACHE_WR,Disable DMA Write Channels 'completion to memory write' context cache pre-fetch function. Note: For internal debugging only. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" "0,1" hexmask.long.byte 0x0 20.--23. 1. "RSVDP_20,Reserved for future use." newline hexmask.long.byte 0x0 16.--19. 1. "NUM_DMA_RD_CHAN,Number of Read Channels. You can read this register to determine the number of read channels the DMA controller has been configured to support." hexmask.long.word 0x0 4.--15. 1. "RSVDP_4,Reserved for future use." newline hexmask.long.byte 0x0 0.--3. 1. "NUM_DMA_WR_CHAN,Number of Write Channels. You can read this register to determine the number of write channels the DMA controller has been configured to support." line.long 0x4 "DMA_WRITE_ENGINE_EN_OFF,DMA Write Engine Enable Register." hexmask.long.byte 0x4 24.--31. 1. "RSVDP_24,Reserved for future use." bitfld.long 0x4 23. "DMA_WRITE_ENGINE_EN_HSHAKE_CH7,Enable Handshake for DMA Write Engine Channel 7. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" "0,1" newline bitfld.long 0x4 22. "DMA_WRITE_ENGINE_EN_HSHAKE_CH6,Enable Handshake for DMA Write Engine Channel 6. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" "0,1" bitfld.long 0x4 21. "DMA_WRITE_ENGINE_EN_HSHAKE_CH5,Enable Handshake for DMA Write Engine Channel 5. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" "0,1" newline bitfld.long 0x4 20. "DMA_WRITE_ENGINE_EN_HSHAKE_CH4,Enable Handshake for DMA Write Engine Channel 4. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" "0,1" bitfld.long 0x4 19. "DMA_WRITE_ENGINE_EN_HSHAKE_CH3,Enable Handshake for DMA Write Engine Channel 3. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" "0,1" newline bitfld.long 0x4 18. "DMA_WRITE_ENGINE_EN_HSHAKE_CH2,Enable Handshake for DMA Write Engine Channel 2. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" "0,1" bitfld.long 0x4 17. "DMA_WRITE_ENGINE_EN_HSHAKE_CH1,Enable Handshake for DMA Write Engine Channel 1. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" "0,1" newline bitfld.long 0x4 16. "DMA_WRITE_ENGINE_EN_HSHAKE_CH0,Enable Handshake for DMA Write Engine Channel 0. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" "0,1" hexmask.long.word 0x4 1.--15. 1. "RSVDP_1,Reserved for future use." newline bitfld.long 0x4 0. "DMA_WRITE_ENGINE,DMA Write Engine Enable. - 1: Enable - 0: Disable (Soft Reset) For normal operation you must initially set this bit to '1' before any other software setup actions. You do not need to toggle or rewrite to this bit during normal.." "Disable,Enable" line.long 0x8 "DMA_WRITE_DOORBELL_OFF,DMA Write Doorbell Register." bitfld.long 0x8 31. "WR_STOP,Stop. Set in conjunction with the Doorbell Number field. The DMA write channel stops issuing requests sets the channel status to 'Stopped' and asserts the 'Abort' interrupt if it is enabled. Before setting the Stop bit you must read the.." "0,1" hexmask.long 0x8 3.--30. 1. "RSVDP_3,Reserved for future use." newline bitfld.long 0x8 0.--2. "WR_DOORBELL_NUM,Doorbell Number. You must write the channel number to this register to start the DMA write transfer for that channel. The DMA detects a write to this register field even if the value of this field does not change. You do not need to.." "0,1,2,3,4,5,6,7" group.long (0x18+0xC8000)++0x7 line.long 0x0 "DMA_WRITE_CHANNEL_ARB_WEIGHT_LOW_OFF,DMA Write Engine Channel Arbitration Weight Low Register. The 5-bit channel weight (for write channels 0-3) specifies the maximum number of TLP requests that the DMA can issue for that channel before it must return to.." hexmask.long.word 0x0 20.--31. 1. "RSVDP_20,Reserved for future use." hexmask.long.byte 0x0 15.--19. 1. "WRITE_CHANNEL3_WEIGHT,Channel 3 Weight. The weight is initialized by software before ringing the doorbell. The value is used by the channel weighted round robin arbiter to select the next channel read request. A value of '0' means that one TLP is issued.." newline hexmask.long.byte 0x0 10.--14. 1. "WRITE_CHANNEL2_WEIGHT,Channel 2 Weight. The weight is initialized by software before ringing the doorbell. The value is used by the channel weighted round robin arbiter to select the next channel read request. A value of '0' means that one TLP is issued.." hexmask.long.byte 0x0 5.--9. 1. "WRITE_CHANNEL1_WEIGHT,Channel 1 Weight. The weight is initialized by software before ringing the doorbell. The value is used by the channel weighted round robin arbiter to select the next channel read request. A value of '0' means that one TLP is issued.." newline hexmask.long.byte 0x0 0.--4. 1. "WRITE_CHANNEL0_WEIGHT,Channel 0 Weight. The weight is initialized by software before ringing the doorbell. The value is used by the channel weighted round robin arbiter to select the next channel read request. A value of '0' means that one TLP is issued.." line.long 0x4 "DMA_WRITE_CHANNEL_ARB_WEIGHT_HIGH_OFF,DMA Write Engine Channel Arbitration Weight High Register. The 5-bit channel weight (for write channels 4-7) specifies the maximum number of TLP requests that the DMA can issue for that channel before it must return.." hexmask.long.word 0x4 20.--31. 1. "RSVDP_20,Reserved for future use." hexmask.long.byte 0x4 15.--19. 1. "WRITE_CHANNEL7_WEIGHT,Channel 7 Weight. The weight is initialized by software before ringing the doorbell. The value is used by the channel weighted round robin arbiter to select the next channel read request. A value of '0' means that one TLP is issued.." newline hexmask.long.byte 0x4 10.--14. 1. "WRITE_CHANNEL6_WEIGHT,Channel 6 Weight. The weight is initialized by software before ringing the doorbell. The value is used by the channel weighted round robin arbiter to select the next channel read request. A value of '0' means that one TLP is issued.." hexmask.long.byte 0x4 5.--9. 1. "WRITE_CHANNEL5_WEIGHT,Channel 5 Weight. The weight is initialized by software before ringing the doorbell. The value is used by the channel weighted round robin arbiter to select the next channel read request. A value of '0' means that one TLP is issued.." newline hexmask.long.byte 0x4 0.--4. 1. "WRITE_CHANNEL4_WEIGHT,Channel 4 Weight. The weight is initialized by software before ringing the doorbell. The value is used by the channel weighted round robin arbiter to select the next channel read request. A value of '0' means that one TLP is issued.." group.long (0x2C+0xC8000)++0x7 line.long 0x0 "DMA_READ_ENGINE_EN_OFF,DMA Read Engine Enable Register." hexmask.long.byte 0x0 24.--31. 1. "RSVDP_24,Reserved for future use." bitfld.long 0x0 23. "DMA_READ_ENGINE_EN_HSHAKE_CH7,Enable Handshake for DMA Read Engine Channel 7. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" "0,1" newline bitfld.long 0x0 22. "DMA_READ_ENGINE_EN_HSHAKE_CH6,Enable Handshake for DMA Read Engine Channel 6. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" "0,1" bitfld.long 0x0 21. "DMA_READ_ENGINE_EN_HSHAKE_CH5,Enable Handshake for DMA Read Engine Channel 5. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" "0,1" newline bitfld.long 0x0 20. "DMA_READ_ENGINE_EN_HSHAKE_CH4,Enable Handshake for DMA Read Engine Channel 4. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" "0,1" bitfld.long 0x0 19. "DMA_READ_ENGINE_EN_HSHAKE_CH3,Enable Handshake for DMA Read Engine Channel 3. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" "0,1" newline bitfld.long 0x0 18. "DMA_READ_ENGINE_EN_HSHAKE_CH2,Enable Handshake for DMA Read Engine Channel 2. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" "0,1" bitfld.long 0x0 17. "DMA_READ_ENGINE_EN_HSHAKE_CH1,Enable Handshake for DMA Read Engine Channel 1. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" "0,1" newline bitfld.long 0x0 16. "DMA_READ_ENGINE_EN_HSHAKE_CH0,Enable Handshake for DMA Read Engine Channel 0. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" "0,1" hexmask.long.word 0x0 1.--15. 1. "RSVDP_1,Reserved for future use." newline bitfld.long 0x0 0. "DMA_READ_ENGINE,DMA Read Engine Enable. - 1: Enable - 0: Disable (Soft Reset) For normal operation you must initially set this bit to '1' before any other software setup actions. You do not need to toggle or rewrite to this bit during normal operation." "Disable,Enable" line.long 0x4 "DMA_READ_DOORBELL_OFF,DMA Read Doorbell Register." bitfld.long 0x4 31. "RD_STOP,Stop. Set in conjunction with the Doorbell Number field. The DMA read channel stops issuing requests sets the channel status to 'Stopped' and asserts the 'Abort' interrupt if it is enabled. Before setting the Stop bit you must read the channel.." "0,1" hexmask.long 0x4 3.--30. 1. "RSVDP_3,Reserved for future use." newline bitfld.long 0x4 0.--2. "RD_DOORBELL_NUM,Doorbell Number. You must write 0x0 to this register to start the DMA read transfer for that channel. The DMA detects a write to this register field even if the value of this field does not change. The range of this field is 0x0 to 0x7.." "0,1,2,3,4,5,6,7" group.long (0x38+0xC8000)++0x7 line.long 0x0 "DMA_READ_CHANNEL_ARB_WEIGHT_LOW_OFF,DMA Read Engine Channel Arbitration Weight Low Register. The 5-bit channel weight (for read channels 0-3) specifies the maximum number of TLP requests that the DMA can issue for that channel before it must return to.." hexmask.long.word 0x0 20.--31. 1. "RSVDP_20,Reserved for future use." hexmask.long.byte 0x0 15.--19. 1. "READ_CHANNEL3_WEIGHT,Channel 3 Weight. The weight is initialized by software before ringing the doorbell. The value is used by the channel weighted round robin arbiter to select the next channel read request. Note: The access attributes of this field are.." newline hexmask.long.byte 0x0 10.--14. 1. "READ_CHANNEL2_WEIGHT,Channel 2 Weight. The weight is initialized by software before ringing the doorbell. The value is used by the channel weighted round robin arbiter to select the next channel read request. Note: The access attributes of this field are.." hexmask.long.byte 0x0 5.--9. 1. "READ_CHANNEL1_WEIGHT,Channel 1 Weight. The weight is initialized by software before ringing the doorbell. The value is used by the channel weighted round robin arbiter to select the next channel read request. Note: The access attributes of this field are.." newline hexmask.long.byte 0x0 0.--4. 1. "READ_CHANNEL0_WEIGHT,Channel 0 Weight. The weight is initialized by software before ringing the doorbell. The value is used by the channel weighted round robin arbiter to select the next channel read request. Note: The access attributes of this field are.." line.long 0x4 "DMA_READ_CHANNEL_ARB_WEIGHT_HIGH_OFF,DMA Read Engine Channel Arbitration Weight High Register. The 5-bit channel weight (for read channels 4-7) specifies the maximum number of TLP requests that the DMA can issue for that channel before it must return to.." hexmask.long.word 0x4 20.--31. 1. "RSVDP_20,Reserved for future use." hexmask.long.byte 0x4 15.--19. 1. "READ_CHANNEL7_WEIGHT,Channel 7 Weight. The weight is initialized by software before ringing the doorbell. The value is used by the channel weighted round robin arbiter to select the next channel read request. Note: The access attributes of this field are.." newline hexmask.long.byte 0x4 10.--14. 1. "READ_CHANNEL6_WEIGHT,Channel 6 Weight. The weight is initialized by software before ringing the doorbell. The value is used by the channel weighted round robin arbiter to select the next channel read request. Note: The access attributes of this field are.." hexmask.long.byte 0x4 5.--9. 1. "READ_CHANNEL5_WEIGHT,Channel 5 Weight. The weight is initialized by software before ringing the doorbell. The value is used by the channel weighted round robin arbiter to select the next channel read request. Note: The access attributes of this field are.." newline hexmask.long.byte 0x4 0.--4. 1. "READ_CHANNEL4_WEIGHT,Channel 4 Weight. The weight is initialized by software before ringing the doorbell. The value is used by the channel weighted round robin arbiter to select the next channel read request. Note: The access attributes of this field are.." group.long (0x4C+0xC8000)++0x3 line.long 0x0 "DMA_WRITE_INT_STATUS_OFF,DMA Write Interrupt Status Register." hexmask.long.byte 0x0 24.--31. 1. "RSVDP_24,Reserved for future use." hexmask.long.byte 0x0 16.--23. 1. "WR_ABORT_INT_STATUS,Abort Interrupt Status. The DMA write channel has detected an error or you manually stopped the transfer as described in 'Error Handling Assistance by Remote Software'. Each bit corresponds to a DMA channel. Bit [0] corresponds to.." newline hexmask.long.byte 0x0 8.--15. 1. "RSVDP_8,Reserved for future use." hexmask.long.byte 0x0 0.--7. 1. "WR_DONE_INT_STATUS,Done Interrupt Status. The DMA write channel has successfully completed the DMA transfer. For more details see 'Interrupts and Error Handling'. Each bit corresponds to a DMA channel. Bit [0] corresponds to channel 0. - Enabling: For.." group.long (0x54+0xC8000)++0x7 line.long 0x0 "DMA_WRITE_INT_MASK_OFF,DMA Write Interrupt Mask Register." hexmask.long.byte 0x0 24.--31. 1. "RSVDP_24,Reserved for future use." hexmask.long.byte 0x0 16.--23. 1. "WR_ABORT_INT_MASK,Abort Interrupt Mask. Prevents the Abort interrupt status field in the DMA write interrupt status register from asserting the edma_int output. Each bit corresponds to a DMA channel. Bit [0] corresponds to channel 0. Note: The access.." newline hexmask.long.byte 0x0 8.--15. 1. "RSVDP_8,Reserved for future use." hexmask.long.byte 0x0 0.--7. 1. "WR_DONE_INT_MASK,Done Interrupt Mask. Prevents the Done interrupt status field in the DMA write interrupt status register from asserting the edma_int output. Each bit corresponds to a DMA channel. Bit [0] corresponds to channel 0. Note: The access.." line.long 0x4 "DMA_WRITE_INT_CLEAR_OFF,DMA Write Interrupt Clear Register." hexmask.long.byte 0x4 24.--31. 1. "RSVDP_24,Reserved for future use." hexmask.long.byte 0x4 16.--23. 1. "WR_ABORT_INT_CLEAR,Abort Interrupt Clear. You must write a 1'b1 to clear the corresponding bit in the Abort interrupt status field of the DMA write interrupt status register. Each bit corresponds to a DMA channel. Bit [0] corresponds to channel 0. Note:.." newline hexmask.long.byte 0x4 8.--15. 1. "RSVDP_8,Reserved for future use." hexmask.long.byte 0x4 0.--7. 1. "WR_DONE_INT_CLEAR,Done Interrupt Clear. You must write a 1'b1 to clear the corresponding bit in the Done interrupt status field of the DMA write interrupt status register. Each bit corresponds to a DMA channel. Bit [0] corresponds to channel 0. Note:.." rgroup.long (0x5C+0xC8000)++0x3 line.long 0x0 "DMA_WRITE_ERR_STATUS_OFF,DMA Write Error Status Register" hexmask.long.byte 0x0 24.--31. 1. "RSVDP_24,Reserved for future use." hexmask.long.byte 0x0 16.--23. 1. "LINKLIST_ELEMENT_FETCH_ERR_DETECT,Linked List Element Fetch Error Detected. The DMA write channel has received an error response from the AXI bus (or TRGT1 interface when the AXI Bridge is not used) while reading a linked list element from local memory." newline hexmask.long.byte 0x0 8.--15. 1. "RSVDP_8,Reserved for future use." hexmask.long.byte 0x0 0.--7. 1. "APP_READ_ERR_DETECT,Application Read Error Detected. The DMA write channel has received an error response from the AXI bus (or TRGT1 interface when the AXI Bridge is not used) while reading data from it. Each bit corresponds to a DMA channel. Bit [0].." group.long (0x60+0xC8000)++0x1F line.long 0x0 "DMA_WRITE_DONE_IMWR_LOW_OFF,DMA Write Done IMWr Address Low Register." hexmask.long 0x0 0.--31. 1. "DMA_WRITE_DONE_LOW_REG,The DMA uses this field to generate bits [31:0] of the address field for the Done IMWr TLP. Bits [1:0] must be '00' as this address must be dword aligned. Note: The access attributes of this field are as follows: - Wire: No access." line.long 0x4 "DMA_WRITE_DONE_IMWR_HIGH_OFF,DMA Write Done IMWr Interrupt Address High Register." hexmask.long 0x4 0.--31. 1. "DMA_WRITE_DONE_HIGH_REG,The DMA uses this field to generate bits [63:32] of the address field for the Done IMWr TLP. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" line.long 0x8 "DMA_WRITE_ABORT_IMWR_LOW_OFF,DMA Write Abort IMWr Address Low Register." hexmask.long 0x8 0.--31. 1. "DMA_WRITE_ABORT_LOW_REG,The DMA uses this field to generate bits [31:0] of the address field for the Abort IMWr TLP it generates. Bits [1:0] must be '00' as this address must be dword aligned. Note: The access attributes of this field are as follows: -.." line.long 0xC "DMA_WRITE_ABORT_IMWR_HIGH_OFF,DMA Write Abort IMWr Address High Register." hexmask.long 0xC 0.--31. 1. "DMA_WRITE_ABORT_HIGH_REG,The DMA uses this field to generate bits [63:32] of the address field for the Abort IMWr TLP. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" line.long 0x10 "DMA_WRITE_CH01_IMWR_DATA_OFF,DMA Write Channel 1 and 0 IMWr Data Register." hexmask.long.word 0x10 16.--31. 1. "WR_CHANNEL_1_DATA,The DMA uses this field to generate the data field for the Done or Abort IMWr TLPs it generates for write channel 1. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" hexmask.long.word 0x10 0.--15. 1. "WR_CHANNEL_0_DATA,The DMA uses this field to generate the data field for the Done or Abort IMWr TLPs it generates for write channel 0. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" line.long 0x14 "DMA_WRITE_CH23_IMWR_DATA_OFF,DMA Write Channel 3 and 2 IMWr Data Register." hexmask.long.word 0x14 16.--31. 1. "WR_CHANNEL_3_DATA,The DMA uses this field to generate the data field for the Done or Abort IMWr TLPs it generates for write channel 3. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" hexmask.long.word 0x14 0.--15. 1. "WR_CHANNEL_2_DATA,The DMA uses this field to generate the data field for the Done or Abort IMWr TLPs it generates for write channel 2. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" line.long 0x18 "DMA_WRITE_CH45_IMWR_DATA_OFF,DMA Write Channel 5 and 4 IMWr Data Register." hexmask.long.word 0x18 16.--31. 1. "WR_CHANNEL_5_DATA,The DMA uses this field to generate the data field for the Done or Abort IMWr TLPs it generates for write channel 5. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" hexmask.long.word 0x18 0.--15. 1. "WR_CHANNEL_4_DATA,The DMA uses this field to generate the data field for the Done or Abort IMWr TLPs it generates for write channel 4. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" line.long 0x1C "DMA_WRITE_CH67_IMWR_DATA_OFF,DMA Write Channel 7 and 6 IMWr Data Register." hexmask.long.word 0x1C 16.--31. 1. "WR_CHANNEL_7_DATA,The DMA uses this field to generate the data field for the Done or Abort IMWr TLPs it generates for write channel 7. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" hexmask.long.word 0x1C 0.--15. 1. "WR_CHANNEL_6_DATA,The DMA uses this field to generate the data field for the Done or Abort IMWr TLPs it generates for write channel 6. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" group.long (0x90+0xC8000)++0x3 line.long 0x0 "DMA_WRITE_LINKED_LIST_ERR_EN_OFF,DMA Write Linked List Error Enable Register. The LIE and RIE bits in the LL element enable the channel 'done' interrupts (local and remote). The LLLAIE and LLRAIE bits enable the channel 'abort' interrupts (local and.." hexmask.long.byte 0x0 24.--31. 1. "RSVDP_24,Reserved for future use." hexmask.long.byte 0x0 16.--23. 1. "WR_CHANNEL_LLLAIE,Write Channel LL Local Abort Interrupt Enable (LLLAIE). You enable the write channel local abort interrupt through this bit. The LIE and RIE bits in the LL element enable the write channel done interrupts. Each bit corresponds to a DMA.." newline hexmask.long.byte 0x0 8.--15. 1. "RSVDP_8,Reserved for future use." hexmask.long.byte 0x0 0.--7. 1. "WR_CHANNEL_LLRAIE,Write Channel LL Remote Abort Interrupt Enable (LLRAIE). You enable the write channel remote abort interrupt through this bit. The LIE and RIE bits in the LL element enable the write channel done interrupts. Each bit corresponds to a.." group.long (0xA0+0xC8000)++0x3 line.long 0x0 "DMA_READ_INT_STATUS_OFF,DMA Read Interrupt Status Register." hexmask.long.byte 0x0 24.--31. 1. "RSVDP_24,Reserved for future use." hexmask.long.byte 0x0 16.--23. 1. "RD_ABORT_INT_STATUS,Abort Interrupt Status. The DMA read channel has detected an error or you manually stopped the transfer as described in 'Stopping the DMA Transfer (Software Stop)'. Each bit corresponds to a DMA channel. Bit [0] corresponds to.." newline hexmask.long.byte 0x0 8.--15. 1. "RSVDP_8,Reserved for future use." hexmask.long.byte 0x0 0.--7. 1. "RD_DONE_INT_STATUS,Done Interrupt Status. The DMA read channel has successfully completed the DMA read transfer. Each bit corresponds to a DMA channel. Bit [0] corresponds to channel 0. - Enabling: For details see 'Interrupts and Error Handling'. -.." group.long (0xA8+0xC8000)++0x7 line.long 0x0 "DMA_READ_INT_MASK_OFF,DMA Read Interrupt Mask Register." hexmask.long.byte 0x0 24.--31. 1. "RSVDP_24,Reserved for future use." hexmask.long.byte 0x0 16.--23. 1. "RD_ABORT_INT_MASK,Abort Interrupt Mask. Prevents the Abort interrupt status field in the DMA read interrupt status register from asserting the edma_int output. Each bit corresponds to a DMA channel. Bit [0] corresponds to channel 0. Note: The access.." newline hexmask.long.byte 0x0 8.--15. 1. "RSVDP_8,Reserved for future use." hexmask.long.byte 0x0 0.--7. 1. "RD_DONE_INT_MASK,Done Interrupt Mask. Prevents the Done interrupt status field in the DMA read interrupt status register from asserting the edma_int output. Each bit corresponds to a DMA channel. Bit [0] corresponds to channel 0. Note: The access.." line.long 0x4 "DMA_READ_INT_CLEAR_OFF,DMA Read Interrupt Clear Register." hexmask.long.byte 0x4 24.--31. 1. "RSVDP_24,Reserved for future use." hexmask.long.byte 0x4 16.--23. 1. "RD_ABORT_INT_CLEAR,Abort Interrupt Clear. You must write a 1'b1 to clear the corresponding bit in the Abort interrupt status field of the DMA read interrupt status register. Each bit corresponds to a DMA channel. Bit [0] corresponds to channel 0. Note:.." newline hexmask.long.byte 0x4 8.--15. 1. "RSVDP_8,Reserved for future use." hexmask.long.byte 0x4 0.--7. 1. "RD_DONE_INT_CLEAR,Done Interrupt Clear. You must write a 1'b1 to clear the corresponding bit in the Done interrupt status field of the DMA read interrupt status register. Each bit corresponds to a DMA channel. Bit [0] corresponds to channel 0. Note:.." rgroup.long (0xB4+0xC8000)++0x7 line.long 0x0 "DMA_READ_ERR_STATUS_LOW_OFF,DMA Read Error Status Low Register." hexmask.long.byte 0x0 24.--31. 1. "RSVDP_24,Reserved for future use." hexmask.long.byte 0x0 16.--23. 1. "LINK_LIST_ELEMENT_FETCH_ERR_DETECT,Linked List Element Fetch Error Detected. - The DMA read channel has received an error response from the AXI bus while reading a linked list element from local memory. Each bit corresponds to a DMA channel. Bit [0].." newline hexmask.long.byte 0x0 8.--15. 1. "RSVDP_8,Reserved for future use." hexmask.long.byte 0x0 0.--7. 1. "APP_WR_ERR_DETECT,Application Write Error Detected. The DMA read channel has received an error response from the AXI bus (or TRGT1 interface when the AXI Bridge is not used) while writing data to it. This error is fatal. You must restart the transfer.." line.long 0x4 "DMA_READ_ERR_STATUS_HIGH_OFF,DMA Read Error Status High Register." hexmask.long.byte 0x4 24.--31. 1. "DATA_POISIONING,Data Poisoning. The DMA read channel has detected data poisoning in the completion from the remote device (in response to the MRd request). The DMA read channel will drop the completion and then be halted. The CX_FLT_MASK_UR_POIS filter.." hexmask.long.byte 0x4 16.--23. 1. "CPL_TIMEOUT,Completion Time Out. The DMA read channel has timed-out while waiting for the remote device to respond to the MRd request or a malformed CplD has been received. For more details see 'Linked List Mode'. Each bit corresponds to a DMA channel." newline hexmask.long.byte 0x4 8.--15. 1. "CPL_ABORT,Completer Abort. The DMA read channel has received a PCIe completer abort completion status from the remote device in response to the MRd request. For more details see 'Linked List Mode'. Each bit corresponds to a DMA channel. Bit [0].." hexmask.long.byte 0x4 0.--7. 1. "UNSUPPORTED_REQ,Unsupported Request. The DMA read channel has received a PCIe unsupported request completion status from the remote device in response to the MRd request. For more details see 'Linked List Mode'. Each bit corresponds to a DMA channel." group.long (0xC4+0xC8000)++0x3 line.long 0x0 "DMA_READ_LINKED_LIST_ERR_EN_OFF,DMA Read Linked List Error Enable Register. The LIE and RIE bits in the LL element enable the channel 'done' interrupts (local and remote). The LLLAIE and LLRAIE bits enable the channel 'abort' interrupts (local and remote)." hexmask.long.byte 0x0 24.--31. 1. "RSVDP_24,Reserved for future use." hexmask.long.byte 0x0 16.--23. 1. "RD_CHANNEL_LLLAIE,Read Channel LL Local Abort Interrupt Enable (LLLAIE). You enable the read channel Local Abort interrupt through this bit. The LIE and RIE bits in the LL element enable the read channel done interrupts. Each bit corresponds to a DMA.." newline hexmask.long.byte 0x0 8.--15. 1. "RSVDP_8,Reserved for future use." hexmask.long.byte 0x0 0.--7. 1. "RD_CHANNEL_LLRAIE,Read Channel LL Remote Abort Interrupt Enable (LLRAIE). You enable the read channel Remote Abort interrupt through this bit. The LIE and RIE bits in the LL element enable the read channel done interrupts. Each bit corresponds to a DMA.." group.long (0xCC+0xC8000)++0x1F line.long 0x0 "DMA_READ_DONE_IMWR_LOW_OFF,DMA Read Done IMWr Address Low Register." hexmask.long 0x0 0.--31. 1. "DMA_READ_DONE_LOW_REG,The DMA uses this field to generate bits [31:0] of the address field for the Done IMWr TLP. Bits [1:0] must be '00' as this address must be dword aligned. Note: The access attributes of this field are as follows: - Wire: No access." line.long 0x4 "DMA_READ_DONE_IMWR_HIGH_OFF,DMA Read Done IMWr Address High Register." hexmask.long 0x4 0.--31. 1. "DMA_READ_DONE_HIGH_REG,The DMA uses this field to generate bits [63:32] of the address field for the Done IMWr TLP. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" line.long 0x8 "DMA_READ_ABORT_IMWR_LOW_OFF,DMA Read Abort IMWr Address Low Register." hexmask.long 0x8 0.--31. 1. "DMA_READ_ABORT_LOW_REG,The DMA uses this field to generate bits [31:0] of the address field for the Abort IMWr TLP. Bits [1:0] must be '00' as this address must be dword aligned. Note: The access attributes of this field are as follows: - Wire: No.." line.long 0xC "DMA_READ_ABORT_IMWR_HIGH_OFF,DMA Read Abort IMWr Address High Register." hexmask.long 0xC 0.--31. 1. "DMA_READ_ABORT_HIGH_REG,The DMA uses this field to generate bits [63:32] of the address field for the Abort IMWr TLP. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" line.long 0x10 "DMA_READ_CH01_IMWR_DATA_OFF,DMA Read Channel 1 and 0 IMWr Data Register." hexmask.long.word 0x10 16.--31. 1. "RD_CHANNEL_1_DATA,The DMA uses this field to generate the data field for the Done or Abort IMWr TLPs it generates for read channel 1. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" hexmask.long.word 0x10 0.--15. 1. "RD_CHANNEL_0_DATA,The DMA uses this field to generate the data field for the Done or Abort IMWr TLPs it generates for read channel 0. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" line.long 0x14 "DMA_READ_CH23_IMWR_DATA_OFF,DMA Read Channel 3 and 2 IMWr Data Register." hexmask.long.word 0x14 16.--31. 1. "RD_CHANNEL_3_DATA,The DMA uses this field to generate the data field for the Done or Abort IMWr TLPs it generates for read channel 3. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" hexmask.long.word 0x14 0.--15. 1. "RD_CHANNEL_2_DATA,The DMA uses this field to generate the data field for the Done or Abort IMWr TLPs it generates for read channel 2. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" line.long 0x18 "DMA_READ_CH45_IMWR_DATA_OFF,DMA Read Channel 5 and 4 IMWr Data Register." hexmask.long.word 0x18 16.--31. 1. "RD_CHANNEL_5_DATA,The DMA uses this field to generate the data field for the Done or Abort IMWr TLPs it generates for read channel 5. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" hexmask.long.word 0x18 0.--15. 1. "RD_CHANNEL_4_DATA,The DMA uses this field to generate the data field for the Done or Abort IMWr TLPs it generates for read channel 4. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" line.long 0x1C "DMA_READ_CH67_IMWR_DATA_OFF,DMA Read Channel 7 and 6 IMWr Data Register." hexmask.long.word 0x1C 16.--31. 1. "RD_CHANNEL_7_DATA,The DMA uses this field to generate the data field for the Done or Abort IMWr TLPs it generates for read channel 7. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" hexmask.long.word 0x1C 0.--15. 1. "RD_CHANNEL_6_DATA,The DMA uses this field to generate the data field for the Done or Abort IMWr TLPs it generates for read channel 6. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" rgroup.long (0x108+0xC8000)++0x7 line.long 0x0 "DMA_WRITE_ENGINE_HSHAKE_CNT_LOW_OFF,DMA Write Engine Handshake Counter Channel 0/1/2/3 Register." bitfld.long 0x0 29.--31. "RSVDP_29,Reserved for future use." "0,1,2,3,4,5,6,7" hexmask.long.byte 0x0 24.--28. 1. "DMA_WRITE_ENGINE_HSHAKE_CNT_CH3,DMA handshake counter for DMA Write Engine Channel 3. If CC_DMA_HSHAKE =1 the data transfer in Linked List mode starts only when the counter is non-zero." newline bitfld.long 0x0 21.--23. "RSVDP_21,Reserved for future use." "0,1,2,3,4,5,6,7" hexmask.long.byte 0x0 16.--20. 1. "DMA_WRITE_ENGINE_HSHAKE_CNT_CH2,DMA handshake counter for DMA Write Engine Channel 2. If CC_DMA_HSHAKE =1 the data transfer in Linked List mode starts only when the counter is non-zero." newline bitfld.long 0x0 13.--15. "RSVDP_13,Reserved for future use." "0,1,2,3,4,5,6,7" hexmask.long.byte 0x0 8.--12. 1. "DMA_WRITE_ENGINE_HSHAKE_CNT_CH1,DMA handshake counter for DMA Write Engine Channel 1. If CC_DMA_HSHAKE =1 the data transfer in Linked List mode starts only when the counter is non-zero." newline bitfld.long 0x0 5.--7. "RSVDP_5,Reserved for future use." "0,1,2,3,4,5,6,7" hexmask.long.byte 0x0 0.--4. 1. "DMA_WRITE_ENGINE_HSHAKE_CNT_CH0,DMA handshake counter for DMA Write Engine Channel 0. If CC_DMA_HSHAKE =1 the data transfer in Linked List mode starts only when the counter is non-zero." line.long 0x4 "DMA_WRITE_ENGINE_HSHAKE_CNT_HIGH_OFF,DMA Write Engine Handshake Counter Channel 4/5/6/7 Register." bitfld.long 0x4 29.--31. "RSVDP_29,Reserved for future use." "0,1,2,3,4,5,6,7" hexmask.long.byte 0x4 24.--28. 1. "DMA_WRITE_ENGINE_HSHAKE_CNT_CH7,DMA handshake counter for DMA Write Engine Channel 7. If CC_DMA_HSHAKE =1 the data transfer in Linked List mode starts only when the counter is non-zero." newline bitfld.long 0x4 21.--23. "RSVDP_21,Reserved for future use." "0,1,2,3,4,5,6,7" hexmask.long.byte 0x4 16.--20. 1. "DMA_WRITE_ENGINE_HSHAKE_CNT_CH6,DMA handshake counter for DMA Write Engine Channel 6. If CC_DMA_HSHAKE =1 the data transfer in Linked List mode starts only when the counter is non-zero." newline bitfld.long 0x4 13.--15. "RSVDP_13,Reserved for future use." "0,1,2,3,4,5,6,7" hexmask.long.byte 0x4 8.--12. 1. "DMA_WRITE_ENGINE_HSHAKE_CNT_CH5,DMA handshake counter for DMA Write Engine Channel 5. If CC_DMA_HSHAKE =1 the data transfer in Linked List mode starts only when the counter is non-zero." newline bitfld.long 0x4 5.--7. "RSVDP_5,Reserved for future use." "0,1,2,3,4,5,6,7" hexmask.long.byte 0x4 0.--4. 1. "DMA_WRITE_ENGINE_HSHAKE_CNT_CH4,DMA handshake counter for DMA Write Engine Channel 4. If CC_DMA_HSHAKE =1 the data transfer in Linked List mode starts only when the counter is non-zero." rgroup.long (0x118+0xC8000)++0x7 line.long 0x0 "DMA_READ_ENGINE_HSHAKE_CNT_LOW_OFF,DMA Read Engine Handshake Counter Channel 0/1/2/3 Register." bitfld.long 0x0 29.--31. "RSVDP_29,Reserved for future use." "0,1,2,3,4,5,6,7" hexmask.long.byte 0x0 24.--28. 1. "DMA_READ_ENGINE_HSHAKE_CNT_CH3,DMA handshake counter for DMA Read Engine Channel 3. If CC_DMA_HSHAKE =1 the data transfer in Linked List mode starts only when the counter is non-zero." newline bitfld.long 0x0 21.--23. "RSVDP_21,Reserved for future use." "0,1,2,3,4,5,6,7" hexmask.long.byte 0x0 16.--20. 1. "DMA_READ_ENGINE_HSHAKE_CNT_CH2,DMA handshake counter for DMA Read Engine Channel 2. If CC_DMA_HSHAKE =1 the data transfer in Linked List mode starts only when the counter is non-zero." newline bitfld.long 0x0 13.--15. "RSVDP_13,Reserved for future use." "0,1,2,3,4,5,6,7" hexmask.long.byte 0x0 8.--12. 1. "DMA_READ_ENGINE_HSHAKE_CNT_CH1,DMA handshake counter for DMA Read Engine Channel 1. If CC_DMA_HSHAKE =1 the data transfer in Linked List mode starts only when the counter is non-zero." newline bitfld.long 0x0 5.--7. "RSVDP_5,Reserved for future use." "0,1,2,3,4,5,6,7" hexmask.long.byte 0x0 0.--4. 1. "DMA_READ_ENGINE_HSHAKE_CNT_CH0,DMA handshake counter for DMA Read Engine Channel 0. If CC_DMA_HSHAKE =1 the data transfer in Linked List mode starts only when the counter is non-zero." line.long 0x4 "DMA_READ_ENGINE_HSHAKE_CNT_HIGH_OFF,DMA Read Engine Handshake Counter Channel 4/5/6/7 Register." bitfld.long 0x4 29.--31. "RSVDP_29,Reserved for future use." "0,1,2,3,4,5,6,7" hexmask.long.byte 0x4 24.--28. 1. "DMA_READ_ENGINE_HSHAKE_CNT_CH7,DMA handshake counter for DMA Read Engine Channel 7. If CC_DMA_HSHAKE =1 the data transfer in Linked List mode starts only when the counter is non-zero." newline bitfld.long 0x4 21.--23. "RSVDP_21,Reserved for future use." "0,1,2,3,4,5,6,7" hexmask.long.byte 0x4 16.--20. 1. "DMA_READ_ENGINE_HSHAKE_CNT_CH6,DMA handshake counter for DMA Read Engine Channel 6. If CC_DMA_HSHAKE =1 the data transfer in Linked List mode starts only when the counter is non-zero." newline bitfld.long 0x4 13.--15. "RSVDP_13,Reserved for future use." "0,1,2,3,4,5,6,7" hexmask.long.byte 0x4 8.--12. 1. "DMA_READ_ENGINE_HSHAKE_CNT_CH5,DMA handshake counter for DMA Read Engine Channel 5. If CC_DMA_HSHAKE =1 the data transfer in Linked List mode starts only when the counter is non-zero." newline bitfld.long 0x4 5.--7. "RSVDP_5,Reserved for future use." "0,1,2,3,4,5,6,7" hexmask.long.byte 0x4 0.--4. 1. "DMA_READ_ENGINE_HSHAKE_CNT_CH4,DMA handshake counter for DMA Read Engine Channel 4. If CC_DMA_HSHAKE =1 the data transfer in Linked List mode starts only when the counter is non-zero." repeat 8. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 )(list 0x0 0x200 0x400 0x600 0x800 0xA00 0xC00 0xE00 ) group.long ($2+0x200+0xC8000)++0x3 line.long 0x0 "DMA_CH_CONTROL1_OFF_WRCH_$1,DMA Write Channel Control 1 Register." bitfld.long 0x0 30.--31. "DMA_AT,Address Translation TLP Header Bit (AT) The DMA uses this TLP header field when generating MRd/MWr (not IMWr) TLPs. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" "0,1,2,3" bitfld.long 0x0 27.--29. "DMA_TC,Traffic Class TLP Header Bit (TC) The DMA uses this TLP header field when generating MRd/MWr (not IMWr) TLPs. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 26. "DMA_RESERVED5,Reserved. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" "0,1" bitfld.long 0x0 25. "DMA_RO,Relaxed Ordering TLP Header Bit (RO) The DMA uses this TLP header field when generating MRd/MWr (not IMWr) TLPs. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" "0,1" newline bitfld.long 0x0 24. "DMA_NS_SRC,Source No Snoop TLP Header Bit (DMA_NS_SRC). The DMA uses this TLP header field when generating MRd (SAR addressing space) (not IMWr) TLPs. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" "0,1" bitfld.long 0x0 23. "DMA_NS_DST,Destination No Snoop TLP Header Bit (DMA_NS_DST). The DMA uses this TLP header field when generating MWr (DAR addressing space) (not IMWr) TLPs. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" "0,1" newline bitfld.long 0x0 22. "DMA_MEM_TYPE,Master AXI ACE-Lite Cache Coherency Control. This field sets the DMA channel memory type of the address space of the data transfer as follows: - 0x0:peripheral type - 0x1:memory type For more details see 'ACE-Lite Features and Limitations'.." "peripheral type,memory type" hexmask.long.byte 0x0 17.--21. 1. "DMA_RESERVED2,Reserved. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" newline hexmask.long.byte 0x0 12.--16. 1. "DMA_FUNC_NUM,Function Number (FN). The controller uses this field when generating the requester ID for the MRd/MWr DMA TLP. When you have enabled SR-IOV then this field is ignored if you have set the VFE field in the 'DMA Write Channel Control 2.." bitfld.long 0x0 10.--11. "DMA_RESERVED1,Reserved. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" "0,1,2,3" newline bitfld.long 0x0 9. "LLE,Linked List Enable (LLE). - 0: Disable linked list operation - 1: Enable linked list operation Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" "Disable linked list operation,Enable linked list operation" bitfld.long 0x0 8. "CCS,Consumer Cycle State (CCS). Used in linked list mode only. It is used to synchronize the producer (software) and the consumer (DMA). For more details see 'PCS-CCS-CB-TCB Producer-Consumer Synchronization'. You must initialize this bit. The DMA.." "0,1" newline bitfld.long 0x0 7. "DMA_RESERVED0,Reserved. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" "0,1" bitfld.long 0x0 5.--6. "CS,Channel Status (CS). The channel status bits identify the current operational state of the DMA channel. The operation state encoding for each DMA channel is a s follows: - 00: Reserved - 01: Running. This channel is active and transferring data. - 10:.." "Reserved,Running,?,?" newline bitfld.long 0x0 4. "RIE,Remote Interrupt Enable (RIE). You must set this bit to enable the generation of the Done or Abort Remote interrupts. For more details see 'Interrupts and Error Handling'. In LL mode the DMA overwrites this with the RIE of the LL element. The RIE.." "0,1" bitfld.long 0x0 3. "LIE,Local Interrupt Enable (LIE). You must set this bit to enable the generation of the Done or Abort Local interrupts. For more details see 'Interrupts and Error Handling'. In LL mode the DMA overwrites this with the LIE of the LL element. The LIE bit.." "0,1" newline bitfld.long 0x0 2. "LLP,Load Link Pointer (LLP). Used in linked list mode only. Indicates that this linked list element is a link element and its LL element pointer dwords are pointing to the next (non-contiguous) element. The DMA loads this field with the LLP of the.." "0,1" bitfld.long 0x0 1. "TCB,Toggle Cycle Bit (TCB). Indicates to the DMA to toggle its interpretation of the CB. Used in linked list mode only. It is used to synchronize the producer (software) and the consumer (DMA). For more details see 'PCS-CCS-CB-TCB Producer-Consumer.." "0,1" newline bitfld.long 0x0 0. "CB,Cycle Bit (CB). Used in linked list mode only. It is used to synchronize the producer (software) and the consumer (DMA). For more details see 'PCS-CCS-CB-TCB Producer-Consumer Synchronization'. The DMA loads this field with the CB of the linked list.." "0,1" repeat.end repeat 8. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 )(list 0x0 0x200 0x400 0x600 0x800 0xA00 0xC00 0xE00 ) group.long ($2+0x208+0xC8000)++0x3 line.long 0x0 "DMA_TRANSFER_SIZE_OFF_WRCH_$1,DMA Write Transfer Size Register." hexmask.long 0x0 0.--31. 1. "DMA_TRANSFER_SIZE,DMA Transfer Size. You program this register with the size of the DMA transfer. The maximum DMA transfer size is 4Gbytes. The minimum transfer size is one byte (0x1). This field is automatically decremented by the DMA as the DMA write.." repeat.end repeat 8. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 )(list 0x0 0x200 0x400 0x600 0x800 0xA00 0xC00 0xE00 ) group.long ($2+0x20C+0xC8000)++0x3 line.long 0x0 "DMA_SAR_LOW_OFF_WRCH_$1,DMA Write SAR Low Register." hexmask.long 0x0 0.--31. 1. "SRC_ADDR_REG_LOW,Source Address Register (Lower 32 bits). Indicates the next address to be read from. The DMA increments the SAR as the DMA transfer progresses. In LL mode the DMA overwrites this with the corresponding dword of the LL element. - DMA.." repeat.end repeat 8. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 )(list 0x0 0x200 0x400 0x600 0x800 0xA00 0xC00 0xE00 ) group.long ($2+0x210+0xC8000)++0x3 line.long 0x0 "DMA_SAR_HIGH_OFF_WRCH_$1,DMA Write SAR High Register." hexmask.long 0x0 0.--31. 1. "SRC_ADDR_REG_HIGH,Source Address Register (Higher 32 bits). In LL mode the DMA overwrites this with the corresponding dword of the LL element. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" repeat.end repeat 8. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 )(list 0x0 0x200 0x400 0x600 0x800 0xA00 0xC00 0xE00 ) group.long ($2+0x214+0xC8000)++0x3 line.long 0x0 "DMA_DAR_LOW_OFF_WRCH_$1,DMA Write DAR Low Register." hexmask.long 0x0 0.--31. 1. "DST_ADDR_REG_LOW,Destination Address Register (Lower 32 bits). Indicates the next address to be written to. The DMA increments the DAR as the DMA transfer progresses. In LL mode the DMA overwrites this with the corresponding dword of the LL element. -.." repeat.end repeat 8. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 )(list 0x0 0x200 0x400 0x600 0x800 0xA00 0xC00 0xE00 ) group.long ($2+0x218+0xC8000)++0x3 line.long 0x0 "DMA_DAR_HIGH_OFF_WRCH_$1,DMA Write DAR High Register." hexmask.long 0x0 0.--31. 1. "DST_ADDR_REG_HIGH,Destination Address Register (Higher 32 bits). In LL mode the DMA overwrites this with the corresponding dword of the LL element. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" repeat.end repeat 8. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 )(list 0x0 0x200 0x400 0x600 0x800 0xA00 0xC00 0xE00 ) group.long ($2+0x21C+0xC8000)++0x3 line.long 0x0 "DMA_LLP_LOW_OFF_WRCH_$1,DMA Write Linked List Pointer Low Register." hexmask.long 0x0 0.--31. 1. "LLP_LOW,Lower bits of the address of the linked list transfer list in local memory. Used in linked list mode only. Updated by the DMA to point to the next element in the transfer list after the previous element is consumed. - When the current element is.." repeat.end repeat 8. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 )(list 0x0 0x200 0x400 0x600 0x800 0xA00 0xC00 0xE00 ) group.long ($2+0x220+0xC8000)++0x3 line.long 0x0 "DMA_LLP_HIGH_OFF_WRCH_$1,DMA Write Linked List Pointer High Register." hexmask.long 0x0 0.--31. 1. "LLP_HIGH,Upper 32 bits of the address of the linked list transfer list in local memory. Used in linked list mode only. Updated by the DMA to point to the next element in the transfer list as elements are consumed. Note: The access attributes of this.." repeat.end repeat 8. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 )(list 0x0 0x200 0x400 0x600 0x800 0xA00 0xC00 0xE00 ) group.long ($2+0x300+0xC8000)++0x3 line.long 0x0 "DMA_CH_CONTROL1_OFF_RDCH_$1,DMA Read Channel Control 1 Register." bitfld.long 0x0 30.--31. "DMA_AT,Address Translation TLP Header Bit (AT) The DMA uses this TLP header field when generating MRd/MWr (not IMWr) TLPs. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" "0,1,2,3" bitfld.long 0x0 27.--29. "DMA_TC,Traffic Class TLP Header Bit (TC) The DMA uses this TLP header field when generating MRd/MWr (not IMWr) TLPs. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 26. "DMA_RESERVED5,Reserved. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" "0,1" bitfld.long 0x0 25. "DMA_RO,Relaxed Ordering TLP Header Bit (RO) The DMA uses this TLP header field when generating MRd/MWr (not IMWr) TLPs. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" "0,1" newline bitfld.long 0x0 24. "DMA_NS_SRC,Source No Snoop TLP Header Bit (DMA_NS_SRC). The DMA uses this TLP header field when generating MRd (SAR addressing space) (not IMWr) TLPs. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" "0,1" bitfld.long 0x0 23. "DMA_NS_DST,Destination No Snoop TLP Header Bit (DMA_NS_DST). The DMA uses this TLP header field when generating MWr (DAR addressing space) (not IMWr) TLPs. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" "0,1" newline bitfld.long 0x0 22. "DMA_MEM_TYPE,Master AXI ACE-Lite Cache Coherency Control. This field sets the DMA channel memory type of the address space of the data transfer as follows: - 0x0:peripheral type - 0x1:memory type For more details see 'ACE-Lite Features and Limitations'.." "peripheral type,memory type" hexmask.long.byte 0x0 17.--21. 1. "DMA_RESERVED2,Reserved. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" newline hexmask.long.byte 0x0 12.--16. 1. "DMA_FUNC_NUM,Function Number (FN). The controller uses this field when generating the requester ID for the MRd/MWr DMA TLP. When you have enabled SR-IOV then this field is ignored if you have set the VFE field in the 'DMA Read Channel Control 2.." bitfld.long 0x0 10.--11. "DMA_RESERVED1,Reserved. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" "0,1,2,3" newline bitfld.long 0x0 9. "LLE,Linked List Enable (LLE). - 0: Disable linked list operation - 1: Enable linked list operation Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" "Disable linked list operation,Enable linked list operation" bitfld.long 0x0 8. "CCS,Consumer Cycle State (CCS). Used in linked list mode only. It is used to synchronize the producer (software) and the consumer (DMA). For more details see 'PCS-CCS-CB-TCB Producer-Consumer Synchronization'. You must initialize this bit. The DMA.." "0,1" newline bitfld.long 0x0 7. "DMA_RESERVED0,Reserved. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" "0,1" bitfld.long 0x0 5.--6. "CS,Channel Status (CS). The channel status bits identify the current operational state of the DMA channel. The operation state encoding for each DMA channel is a s follows: - 00: Reserved - 01: Running. This channel is active and transferring data. - 10:.." "Reserved,Running,?,?" newline bitfld.long 0x0 4. "RIE,Remote Interrupt Enable (RIE). You must set this bit to enable the generation of the Done or Abort Remote interrupts. For more details see 'Interrupts and Error Handling'. In LL mode the DMA overwrites this with the RIE of the LL element. The RIE.." "0,1" bitfld.long 0x0 3. "LIE,Local Interrupt Enable (LIE). You must set this bit to enable the generation of the Done or Abort Local interrupts. For more details see 'Interrupts and Error Handling'. In LL mode the DMA overwrites this with the LIE of the LL element. The LIE bit.." "0,1" newline bitfld.long 0x0 2. "LLP,Load Link Pointer (LLP). Used in linked list mode only. Indicates that this linked list element is a link element and its LL element pointer dwords are pointing to the next (non-contiguous) element. The DMA loads this field with the LLP of the.." "0,1" bitfld.long 0x0 1. "TCB,Toggle Cycle Bit (TCB). Indicates to the DMA to toggle its interpretation of the CB. Used in linked list mode only. It is used to synchronize the producer (software) and the consumer (DMA). For more details see 'PCS-CCS-CB-TCB Producer-Consumer.." "0,1" newline bitfld.long 0x0 0. "CB,Cycle Bit (CB). Used in linked list mode only. It is used to synchronize the producer (software) and the consumer (DMA). For more details see 'PCS-CCS-CB-TCB Producer-Consumer Synchronization'. The DMA loads this field with the CB of the linked list.." "0,1" repeat.end repeat 8. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 )(list 0x0 0x200 0x400 0x600 0x800 0xA00 0xC00 0xE00 ) group.long ($2+0x308+0xC8000)++0x3 line.long 0x0 "DMA_TRANSFER_SIZE_OFF_RDCH_$1,DMA Read Transfer Size Register." hexmask.long 0x0 0.--31. 1. "DMA_TRANSFER_SIZE,DMA Transfer Size. You program this register with the size of the DMA transfer. The maximum DMA transfer size is 4Gbytes. The minimum transfer size is one byte (0x1). This field is automatically decremented by the DMA as the DMA read.." repeat.end repeat 8. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 )(list 0x0 0x200 0x400 0x600 0x800 0xA00 0xC00 0xE00 ) group.long ($2+0x30C+0xC8000)++0x3 line.long 0x0 "DMA_SAR_LOW_OFF_RDCH_$1,DMA Read SAR Low Register." hexmask.long 0x0 0.--31. 1. "SRC_ADDR_REG_LOW,Source Address Register (Lower 32 bits). Indicates the next address to be read from. The DMA increments the SAR as the DMA transfer progresses. In LL mode the DMA overwrites this with the corresponding dword of the LL element. - DMA.." repeat.end repeat 8. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 )(list 0x0 0x200 0x400 0x600 0x800 0xA00 0xC00 0xE00 ) group.long ($2+0x310+0xC8000)++0x3 line.long 0x0 "DMA_SAR_HIGH_OFF_RDCH_$1,DMA Read SAR High Register." hexmask.long 0x0 0.--31. 1. "SRC_ADDR_REG_HIGH,Source Address Register (Higher 32 bits). In LL mode the DMA overwrites this with the corresponding dword of the LL element. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" repeat.end repeat 8. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 )(list 0x0 0x200 0x400 0x600 0x800 0xA00 0xC00 0xE00 ) group.long ($2+0x314+0xC8000)++0x3 line.long 0x0 "DMA_DAR_LOW_OFF_RDCH_$1,DMA Read DAR Low Register." hexmask.long 0x0 0.--31. 1. "DST_ADDR_REG_LOW,Destination Address Register (Lower 32 bits). Indicates the next address to be written to. The DMA increments the DAR as the DMA transfer progresses. In LL mode the DMA overwrites this with the corresponding dword of the LL element. -.." repeat.end repeat 8. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 )(list 0x0 0x200 0x400 0x600 0x800 0xA00 0xC00 0xE00 ) group.long ($2+0x318+0xC8000)++0x3 line.long 0x0 "DMA_DAR_HIGH_OFF_RDCH_$1,DMA Read DAR High Register." hexmask.long 0x0 0.--31. 1. "DST_ADDR_REG_HIGH,Destination Address Register (Higher 32 bits). In LL mode the DMA overwrites this with the corresponding dword of the LL element. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" repeat.end repeat 8. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 )(list 0x0 0x200 0x400 0x600 0x800 0xA00 0xC00 0xE00 ) group.long ($2+0x31C+0xC8000)++0x3 line.long 0x0 "DMA_LLP_LOW_OFF_RDCH_$1,DMA Read Linked List Pointer Low Register." hexmask.long 0x0 0.--31. 1. "LLP_LOW,Lower bits of the address of the linked list transfer list in local memory. Used in linked list mode only. Updated by the DMA to point to the next element in the transfer list after the previous element is consumed. - When the current element is.." repeat.end repeat 8. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 )(list 0x0 0x200 0x400 0x600 0x800 0xA00 0xC00 0xE00 ) group.long ($2+0x320+0xC8000)++0x3 line.long 0x0 "DMA_LLP_HIGH_OFF_RDCH_$1,DMA Read Linked List Pointer High Register." hexmask.long 0x0 0.--31. 1. "LLP_HIGH,Upper 32 bits of the address of the linked list transfer list in local memory. Used in linked list mode only. Updated by the DMA to point to the next element in the transfer list as elements are consumed. Note: The access attributes of this.." repeat.end tree.end tree "PF0_ATU_CAP (ATU Por Logic Structure)" repeat 8. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 )(list 0x0 0x200 0x400 0x600 0x800 0xA00 0xC00 0xE00 ) group.long ($2+0xC0000)++0x3 line.long 0x0 "IATU_REGION_CTRL_1_OFF_OUTBOUND_$1,iATU Region Control 1 Register." bitfld.long 0x0 20. "CTRL_1_FUNC_NUM,Function Number. - When the address of an outbound TLP is matched to this region and the FUNC_BYPASS field in the 'iATU Control 2 Register' is '0' then the function number used in generating the function part of the requester ID (RID).." "0,1" newline bitfld.long 0x0 13. "INCREASE_REGION_SIZE,Increase the maximum ATU Region size. When set the maximum ATU Region size is determined by CX_ATU_MAX_REGION_SIZE. When clear the maximum ATU Region size is 4 GB (default). Note: This register field is sticky." "0,1" newline bitfld.long 0x0 9.--10. "ATTR,When the address of an outbound TLP is matched to this region then the ATTR field of the TLP is changed to the value in this register. Note: This register field is sticky." "0,1,2,3" newline bitfld.long 0x0 8. "TD,This is a reserved field. Do not use. Note: This register field is sticky." "0,1" newline bitfld.long 0x0 5.--7. "TC,When the address of an outbound TLP is matched to this region then the TC field of the TLP is changed to the value in this register. Note: This register field is sticky." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x0 0.--4. 1. "TYPE,When the address of an outbound TLP is matched to this region then the TYPE field of the TLP is changed to the value in this register. Note: This register field is sticky." repeat.end repeat 8. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 )(list 0x0 0x200 0x400 0x600 0x800 0xA00 0xC00 0xE00 ) group.long ($2+0x4+0xC0000)++0x3 line.long 0x0 "IATU_REGION_CTRL_2_OFF_OUTBOUND_$1,iATU Region Control 2 Register." bitfld.long 0x0 31. "REGION_EN,Region Enable. This bit must be set to '1' for address translation to take place. Note: This register field is sticky." "0,1" newline bitfld.long 0x0 29. "INVERT_MODE,Invert Mode. When set the address matching region is inverted. Therefore an address match occurs when the untranslated address is in the region outside the defined range (Base Address to Limit Address). Note: This register field is sticky." "0,1" newline bitfld.long 0x0 28. "CFG_SHIFT_MODE,CFG Shift Mode. The iATU uses bits [27:12] of the untranslated address (on the XALI0/1/2 interface or AXI slave interface address) to form the BDF number of the outgoing CFG TLP. This supports the Enhanced Configuration Address Mapping.." "0,1" newline bitfld.long 0x0 27. "DMA_BYPASS,DMA Bypass Mode. Allows request TLPs which are initiated by the DMA controller to pass through the iATU untranslated. Note: This field is reserved for the SW product. You must set it to '0'. Note: This register field is sticky." "0,1" newline bitfld.long 0x0 23. "HEADER_SUBSTITUTE_EN,Header Substitute Enable. When enabled and region address is matched the iATU fully substitutes bytes 8-11 (for 3 DWORD header) or bytes 12-15 (for 4 DWORD header) of the outbound TLP header with the contents of the LWR_TARGET_RW.." "LWR_TARGET_RW in the..,LWR_TARGET_RW in the.." newline bitfld.long 0x0 22. "INHIBIT_PAYLOAD,Inhibit TLP Payload Data for TLP's in Matched Region; assign iATU region to be TLP without data. When enabled and region address is matched the iATU marks all TLPs as having no payload data by forcing the TLP header Fmt[1] bit =0.." "Fmt[1] =0/1 so that TLPs with or without data..,Fmt[1] =0 so that only TLP type without data is.." newline bitfld.long 0x0 21. "TLP_HEADER_FIELDS_BYPASS,TLP Header Fields Translation Bypass. In this mode header fields of the translated TLP is taken from your application transmit interface or if AMBA is configured from the AMBA sideband bus (slv_awmisc_info) and not from the.." "0,1" newline bitfld.long 0x0 20. "SNP,Serialize Non-Posted Requests. In this mode when the AXI Bridge is populated same AXI ID Non-Posted Read/Write Requests are transmitted on the wire if there are no other same ID Non-Posted Requests outstanding. Note: This register field is sticky." "0,1" newline bitfld.long 0x0 19. "FUNC_BYPASS,Function Number Translation Bypass. In this mode the function number of the translated TLP is taken from your application transmit interface and not from the CTRL_1_FUNC_NUM field of the 'iATU Control 1 Register' or the VF_NUMBER field of.." "0,1" newline bitfld.long 0x0 16. "TAG_SUBSTITUTE_EN,TAG Substitute Enable. When enabled and region address is matched the iATU substitutes the TAG field of the outbound TLP header with the contents of the TAG field in this register. The expected usage scenario is translation from AXI.." "0,1" newline hexmask.long.byte 0x0 8.--15. 1. "TAG,TAG. The substituted TAG field (byte 6) in the outgoing TLP header when TAG_SUBSTITUTE_EN is set. Note: This register field is sticky." newline hexmask.long.byte 0x0 0.--7. 1. "MSG_CODE,MSG TLPs (Message Code). When the address of an outbound TLP is matched to this region and the translated TLP TYPE field is Msg or MsgD; then the message field of the TLP is changed to the value in this register. Memory TLPs: (ST;Steering Tag)." repeat.end repeat 8. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 )(list 0x0 0x200 0x400 0x600 0x800 0xA00 0xC00 0xE00 ) group.long ($2+0x8+0xC0000)++0x3 line.long 0x0 "IATU_LWR_BASE_ADDR_OFF_OUTBOUND_$1,iATU Lower Base Address Register. The CX_ATU_MIN_REGION_SIZE configuration parameter (Value Range: 4 kB. 8 kB. 16 kB. 32 kB. 64 kB defaults to 64 kB) specifies the minimum size of an address translation region. For.." hexmask.long.tbyte 0x0 12.--31. 1. "LWR_BASE_RW,Forms bits [31:n] of the start address of the address region to be translated. n is log2(CX_ATU_MIN_REGION_SIZE) Note: This register field is sticky." newline hexmask.long.word 0x0 0.--11. 1. "LWR_BASE_HW,Forms bits [n-1:0] of the start address of the address region to be translated. The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary so these bits are always 0. A write to this location is ignored by the PCIe controller." repeat.end repeat 8. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 )(list 0x0 0x200 0x400 0x600 0x800 0xA00 0xC00 0xE00 ) group.long ($2+0xC+0xC0000)++0x3 line.long 0x0 "IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_$1,iATU Upper Base Address Register." hexmask.long 0x0 0.--31. 1. "UPPER_BASE_RW,Forms bits [63:32] of the start (and end) address of the address region to be translated. In systems with a 32-bit address space this register is not used and therefore writing to this register has no effect. Note: This register field is.." repeat.end repeat 8. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 )(list 0x0 0x200 0x400 0x600 0x800 0xA00 0xC00 0xE00 ) group.long ($2+0x10+0xC0000)++0x3 line.long 0x0 "IATU_LIMIT_ADDR_OFF_OUTBOUND_$1,iATU Limit Address Register." hexmask.long.tbyte 0x0 12.--31. 1. "LIMIT_ADDR_RW,Forms upper bits of the end address of the address region to be translated. Note: This register field is sticky." newline hexmask.long.word 0x0 0.--11. 1. "LIMIT_ADDR_HW,Forms lower bits of the end address of the address region to be translated. The end address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary so these bits are always all ones. A write to this location is ignored by the PCIe.." repeat.end repeat 8. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 )(list 0x0 0x200 0x400 0x600 0x800 0xA00 0xC00 0xE00 ) group.long ($2+0x14+0xC0000)++0x3 line.long 0x0 "IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_$1,iATU Lower Target Address Register." hexmask.long 0x0 0.--31. 1. "LWR_TARGET_RW_OUTBOUND,When HEADER_SUBSTITUTE_EN in IATU_REGION_CTRL_2_OFF_OUTBOUND_ is '0' (normal operation): - LWR_TARGET_RW[31:n] forms MSB's of the Lower Target part of the new address of the translated region; - LWR_TARGET_RW[n-1:0] are not used." repeat.end repeat 8. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 )(list 0x0 0x200 0x400 0x600 0x800 0xA00 0xC00 0xE00 ) group.long ($2+0x18+0xC0000)++0x3 line.long 0x0 "IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_$1,iATU Upper Target Address Register." hexmask.long 0x0 0.--31. 1. "UPPER_TARGET_RW,Forms bits [63:32] of the start address (Upper Target part) of the new address of the translated region. Note: This register field is sticky." repeat.end repeat 8. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 )(list 0x0 0x200 0x400 0x600 0x800 0xA00 0xC00 0xE00 ) group.long ($2+0x1C+0xC0000)++0x3 line.long 0x0 "IATU_REGION_CTRL_3_OFF_OUTBOUND_$1,iATU Region Control 3 Register." bitfld.long 0x0 31. "VF_ACTIVE,Virtual Function Active. Indicates that all of the outbound accesses are from virtual functions. For more details see VF_ACTIVE field. Note: This register field is sticky." "0,1" newline hexmask.long 0x0 3.--30. 1. "RSVDP_VF_NUMBER,Reserved for future use." newline bitfld.long 0x0 0.--2. "VF_NUMBER,Virtual Function Number. When the address of an outbound TLP is matched to this region and the FUNC_BYPASS field in the 'iATU Control 2 Register' is '0' then this field used in generating the Function part of the requester ID (RID) field of.." "0,1,2,3,4,5,6,7" repeat.end repeat 8. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 )(list 0x0 0x200 0x400 0x600 0x800 0xA00 0xC00 0xE00 ) group.long ($2+0x100+0xC0000)++0x3 line.long 0x0 "IATU_REGION_CTRL_1_OFF_INBOUND_$1,iATU Region Control 1 Register." bitfld.long 0x0 20. "CTRL_1_FUNC_NUM,Function Number. - MEM-I/O: When the Address and BAR matching logic in the controller indicate that a MEM-I/O transaction matches a BAR in the function corresponding to this value then address translation proceeds. This check is only.." "?,When the destination function number as.." newline bitfld.long 0x0 13. "INCREASE_REGION_SIZE,Increase the maximum ATU Region size. When set the maximum ATU Region size is determined by CX_ATU_MAX_REGION_SIZE. When clear the maximum ATU Region size is 4 GB (default). Note: This register field is sticky." "0,1" newline bitfld.long 0x0 9.--10. "ATTR,When the ATTR field of an inbound TLP is matched to this value then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the 'ATTR Match Enable' bit of the 'iATU Control 2 Register' is.." "0,1,2,3" newline bitfld.long 0x0 8. "TD,When the TD field of an inbound TLP is matched to this value then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the 'TD Match Enable' bit of the 'iATU Control 2 Register' is set." "0,1" newline bitfld.long 0x0 5.--7. "TC,When the TC field of an inbound TLP is matched to this value then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the 'TC Match Enable' bit of the 'iATU Control 2 Register' is set." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x0 0.--4. 1. "TYPE,When the TYPE field of an inbound TLP is matched to this value then address translation proceeds (when all other enabled field-matches are successful). Note: This register field is sticky." repeat.end repeat 8. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 )(list 0x0 0x200 0x400 0x600 0x800 0xA00 0xC00 0xE00 ) group.long ($2+0x104+0xC0000)++0x3 line.long 0x0 "IATU_REGION_CTRL_2_OFF_INBOUND_$1,iATU Region Control 2 Register." bitfld.long 0x0 31. "REGION_EN,Region Enable. This bit must be set to '1' for address translation to take place. Note: This register field is sticky." "0,1" newline bitfld.long 0x0 30. "MATCH_MODE,Match Mode. Determines Inbound matching mode for TLPs. The mode depends on the type of TLP that is received as follows: For MEM-I/O TLPs this field is interpreted as follows: - 0: Address Match Mode. The iATU operates using addresses as in.." "Address Match Mode,Vendor ID Match Mode" newline bitfld.long 0x0 29. "INVERT_MODE,Invert Mode. When set the address matching region is inverted. Therefore an address match occurs when the untranslated address is in the region outside the defined range (Base Address to Limit Address). Note: This register field is sticky." "0,1" newline bitfld.long 0x0 28. "CFG_SHIFT_MODE,CFG Shift Mode. This is useful for CFG transactions where the PCIe configuration mechanism maps bits [27:12] of the address to the bus/device and function number. This allows a CFG configuration space to be located in any 256MB window of.." "0,1" newline bitfld.long 0x0 27. "FUZZY_TYPE_MATCH_CODE,Fuzzy Type Match Mode. When enabled the iATU relaxes the matching of the TLP TYPE field against the expected TYPE field so that - CfgRd0 and CfgRd1 TLPs are seen as identical. Similarly with CfgWr0 and CfgWr1. - MWr MRd and MRdLk.." "0,1" newline bitfld.long 0x0 26. "VFBAR_MATCH_MODE_EN,VF BAR Match Mode enable. When set Virtual Function BAR matching is used which allows all VFs in a PF which match a BAR to be matched with a single ATU region. Note: This register field is sticky." "0,1" newline bitfld.long 0x0 24.--25. "RESPONSE_CODE,Response Code. Defines the type of response to give for accesses matching this region. This overrides the normal RADM filter response. Note that this feature is not available for any region where Single Address Location Translate is.." "Normal RADM filter response is used,Unsupported request,?,?" newline bitfld.long 0x0 23. "SINGLE_ADDR_LOC_TRANS_EN,Single Address Location Translate Enable. When enabled Rx TLPs can be translated to a single address location as determined by the target address register of the iATU region. The main usage scenario is translation of Messages.." "0,1" newline bitfld.long 0x0 21. "MSG_CODE_MATCH_EN,Message Code Match Enable (Msg TLPS). Ensures that a successful message Code TLP field comparison match (see Message Code field of the 'iATU Control 2 Register') occurs (in MSG transactions) for address translation to proceed. ST Match.." "0,1" newline bitfld.long 0x0 20. "VF_MATCH_EN,Virtual Function Number Match Enable. Ensures that a successful Virtual Function Number TLP field comparison match (see Virtual Function Number field of the 'iATU Control 3 Register') occurs (in MEM-I/O transactions) for address translation.." "0,1" newline bitfld.long 0x0 19. "FUNC_NUM_MATCH_EN,Function Number Match Enable. Ensures that a successful Function Number TLP field comparison match (see Function Number field of the 'iATU Control 1 Register') occurs (in MEM-I/O and CFG0/CFG1 transactions) for address translation to.." "0,1" newline bitfld.long 0x0 16. "ATTR_MATCH_EN,ATTR Match Enable. Ensures that a successful ATTR TLP field comparison match (see ATTR field of the 'iATU Control 1 Register') occurs for address translation to proceed. Note: This register field is sticky." "0,1" newline bitfld.long 0x0 15. "TD_MATCH_EN,TD Match Enable. Ensures that a successful TD TLP field comparison match (see TD field of the 'iATU Control 1 Register') occurs for address translation to proceed. Note: This register field is sticky." "0,1" newline bitfld.long 0x0 14. "TC_MATCH_EN,TC Match Enable. Ensures that a successful TC TLP field comparison match (see TC field of the 'iATU Control 1 Register') occurs for address translation to proceed. Note: This register field is sticky." "0,1" newline bitfld.long 0x0 13. "MSG_TYPE_MATCH_MODE,Message Type Match Mode. When enabled and if single address location translate enable is set then inbound TLPs of type MSG/MSGd which match the type field of the iatu_region_ctrl_1_OFF_inbound register (=>TYPE[4:3]=2'b10) will be.." "0,1" newline bitfld.long 0x0 8.--10. "BAR_NUM,BAR Number. When the BAR number of an inbound MEM or IO TLP ' that is matched by the normal internal BAR address matching mechanism ' is the same as this field address translation proceeds (when all other enabled field-matches are successful)." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x0 0.--7. 1. "MSG_CODE,MSG TLPs: (Message Code). When the TYPE field of an inbound Msg/MsgD TLP is matched to this value then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the 'Message Code Match.." repeat.end repeat 8. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 )(list 0x0 0x200 0x400 0x600 0x800 0xA00 0xC00 0xE00 ) group.long ($2+0x108+0xC0000)++0x3 line.long 0x0 "IATU_LWR_BASE_ADDR_OFF_INBOUND_$1,iATU Lower Base Address Register. The CX_ATU_MIN_REGION_SIZE configuration parameter (Value Range: 4 kB. 8 kB. 16 kB. 32 kB. 64 kB defaults to 64 kB) specifies the minimum size of an address translation region. For.." hexmask.long.tbyte 0x0 12.--31. 1. "LWR_BASE_RW,Forms bits [31:n] of the start address of the address region to be translated. n is log2(CX_ATU_MIN_REGION_SIZE) Note: This register field is sticky." newline hexmask.long.word 0x0 0.--11. 1. "LWR_BASE_HW,Forms bits [n-1:0] of the start address of the address region to be translated. The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary so these bits are always 0. A write to this location is ignored by the PCIe controller." repeat.end repeat 8. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 )(list 0x0 0x200 0x400 0x600 0x800 0xA00 0xC00 0xE00 ) group.long ($2+0x10C+0xC0000)++0x3 line.long 0x0 "IATU_UPPER_BASE_ADDR_OFF_INBOUND_$1,iATU Upper Base Address Register." hexmask.long 0x0 0.--31. 1. "UPPER_BASE_RW,Forms bits [63:32] of the start (and end) address of the address region to be translated. Note: This register field is sticky." repeat.end repeat 8. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 )(list 0x0 0x200 0x400 0x600 0x800 0xA00 0xC00 0xE00 ) group.long ($2+0x110+0xC0000)++0x3 line.long 0x0 "IATU_LIMIT_ADDR_OFF_INBOUND_$1,iATU Limit Address Register." hexmask.long.tbyte 0x0 12.--31. 1. "LIMIT_ADDR_RW,Forms upper bits of the end address of the address region to be translated. Note: This register field is sticky." newline hexmask.long.word 0x0 0.--11. 1. "LIMIT_ADDR_HW,Forms lower bits of the end address of the address region to be translated. The end address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary so these bits are always all ones. A write to this location is ignored by the PCIe.." repeat.end repeat 8. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 )(list 0x0 0x200 0x400 0x600 0x800 0xA00 0xC00 0xE00 ) group.long ($2+0x114+0xC0000)++0x3 line.long 0x0 "IATU_LWR_TARGET_ADDR_OFF_INBOUND_$1,iATU Lower Target Address Register." hexmask.long.tbyte 0x0 12.--31. 1. "LWR_TARGET_RW,Forms MSB's of the Lower Target part of the new address of the translated region. These bits are always '0'. - Field size depends on log2(CX_ATU_MIN_REGION_SIZE) in address match mode. - Field size depends on log2(BAR_MASK+1) in BAR match.." newline hexmask.long.word 0x0 0.--11. 1. "LWR_TARGET_HW,Forms the LSB's of the Lower Target part of the new address of the translated region. The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary (in address match mode); and to the Bar size boundary (in BAR match mode) so.." repeat.end repeat 8. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 )(list 0x0 0x200 0x400 0x600 0x800 0xA00 0xC00 0xE00 ) group.long ($2+0x118+0xC0000)++0x3 line.long 0x0 "IATU_UPPER_TARGET_ADDR_OFF_INBOUND_$1,iATU Upper Target Address Register." hexmask.long 0x0 0.--31. 1. "UPPER_TARGET_RW,Forms bits [63:32] of the start address (Upper Target part) of the new address of the translated region. In systems with a 32-bit address space this register is not used and therefore writing to this register has no effect. Note: This.." repeat.end repeat 8. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 )(list 0x0 0x200 0x400 0x600 0x800 0xA00 0xC00 0xE00 ) group.long ($2+0x11C+0xC0000)++0x3 line.long 0x0 "IATU_REGION_CTRL_3_OFF_INBOUND_$1,iATU Region Control 3 Register." rbitfld.long 0x0 31. "VF_ACTIVE,Reserved. Not used." "0,1" newline hexmask.long 0x0 3.--30. 1. "RSVDP_VF_NUMBER,Reserved for future use." newline bitfld.long 0x0 0.--2. "VF_NUMBER,Virtual Function Number. When the Address and BAR matching logic in the controller indicates that a MEM-I/O transaction matches a BAR in the virtual function corresponding to this value then address translation proceeds. This check is only.." "0,1,2,3,4,5,6,7" repeat.end tree.end tree "PF0_PORT_LOGIC (Port Logic)" group.long (0x0+0x700)++0x27 line.long 0x0 "ACK_LATENCY_TIMER_OFF,Ack Latency Timer and Replay Timer Register." hexmask.long.word 0x0 16.--31. 1. "REPLAY_TIME_LIMIT,Replay Timer Limit. The replay timer expires when it reaches this limit. The controller initiates a replay upon reception of a NAK or when the replay timer expires. For more details see 'Transmit Replay'. You can modify the effective.." newline hexmask.long.word 0x0 0.--15. 1. "ROUND_TRIP_LATENCY_TIME_LIMIT,Ack Latency Timer Limit. The Ack latency timer expires when it reaches this limit. For more details see 'Ack Scheduling'. You can modify the effective timer limit with the TIMER_MOD_ACK_NAK field of the.." line.long 0x4 "VENDOR_SPEC_DLLP_OFF,Vendor Specific DLLP Register." hexmask.long 0x4 0.--31. 1. "VENDOR_SPEC_DLLP,Vendor Specific DLLP Register. Used to send a specific PCI Express DLLP. Your application writes the 8-bit DLLP Type and 24-bits of Payload data into this register then sets the field VENDOR_SPECIFIC_DLLP_REQ of PORT_LINK_CTRL_OFF to.." line.long 0x8 "PORT_FORCE_OFF,Port Force Link Register." hexmask.long.byte 0x8 24.--31. 1. "RSVDP_24,Reserved for future use." newline bitfld.long 0x8 23. "DO_DESKEW_FOR_SRIS,Use the transitions from TS2 to Logical Idle Symbol SKP OS to Logical Idle Symbol EIEOS to Logical Idle Symbol and FTS Sequence to SKP OS to do deskew instead of using received SKP OS or TS1 to TS2 transition if DO_DESKEW_FOR_SRIS.." "0,1" newline rbitfld.long 0x8 22. "RSVDP_22,Reserved for future use." "0,1" newline hexmask.long.byte 0x8 16.--21. 1. "LINK_STATE,Forced LTSSM State. The LTSSM state that the controller is forced to when you set the FORCE_EN bit (Force Link). LTSSM state encoding is defined by the lts_state variable in workspace/src/Layer1/smlh_ltssm.v. Note: This register field is sticky." newline bitfld.long 0x8 15. "FORCE_EN,Force Link. The controller supports a testing and debug capability to allow your software to force the LTSSM state machine into a specific state and to force the controller to transmit a specific Link Command. Asserting this bit triggers the.." "0,1" newline rbitfld.long 0x8 12.--14. "RSVDP_12,Reserved for future use." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x8 8.--11. 1. "FORCED_LTSSM,Forced Link Command. The link command that the controller is forced to transmit when you set FORCE_EN bit (Force Link). Link command encoding is defined by the ltssm_cmd variable in workspace/src/Layer1/smlh_ltssm.v. Note: This register.." newline hexmask.long.byte 0x8 0.--7. 1. "LINK_NUM,Link Number. Not used for endpoint. Not used for M-PCIe. Note: This register field is sticky." line.long 0xC "ACK_F_ASPM_CTRL_OFF,Ack Frequency and L0-L1 ASPM Control Register." rbitfld.long 0xC 31. "RSVDP_31,Reserved for future use." "0,1" newline bitfld.long 0xC 30. "ENTER_ASPM,ASPM L1 Entry Control. - 1: Controller enters ASPM L1 after a period in which it has been idle. - 0: Controller enters ASPM L1 only after idle period during which both receive and transmit are in L0s. Note: This register field is sticky." "Controller enters ASPM L1 only after idle period..,Controller enters ASPM L1 after a period in.." newline bitfld.long 0xC 27.--29. "L1_ENTRANCE_LATENCY,L1 Entrance Latency. Value range is: - 000: 1 us - 001: 2 us - 010: 4 us - 011: 8 us - 100: 16 us - 101: 32 us - 110 or 111: 64 us Note: Programming this timer with a value greater that 32us has no effect unless extended sync is used.." "0,1,2,3,4,5,6,7" newline bitfld.long 0xC 24.--26. "L0S_ENTRANCE_LATENCY,L0s Entrance Latency. Values correspond to: - 000: 1 us - 001: 2 us - 010: 3 us - 011: 4 us - 100: 5 us - 101: 6 us - 110 or 111: 7 us This field is applicable to STALL while in L0 for M-PCIe. Note: This register field is sticky." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0xC 16.--23. 1. "COMMON_CLK_N_FTS,Common Clock N_FTS. This is the N_FTS when common clock is used. The number of Fast Training Sequence ordered sets to be transmitted when transitioning from L0s to L0. The maximum number of FTS ordered-sets that a component can request.." newline hexmask.long.byte 0xC 8.--15. 1. "ACK_N_FTS,N_FTS. The number of Fast Training Sequence ordered sets to be transmitted when transitioning from L0s to L0. The maximum number of FTS ordered-sets that a component can request is 255. The controller does not support a value of zero; a value.." newline hexmask.long.byte 0xC 0.--7. 1. "ACK_FREQ,Ack Frequency. The controller accumulates the number of pending ACKs specified here (up to 255) before scheduling an ACK DLLP. - 0: Indicates that this Ack Frequency Counter feature is turned off. The controller generates a low-priority ACK.." line.long 0x10 "PORT_LINK_CTRL_OFF,Port Link Control Register." hexmask.long.byte 0x10 28.--31. 1. "RSVDP_28,Reserved for future use." newline bitfld.long 0x10 27. "TRANSMIT_LANE_REVERSALE_ENABLE,TRANSMIT_LANE_REVERSALE_ENABLE is an internally reserved field. Do not use. Note: This register field is sticky." "0,1" newline bitfld.long 0x10 26. "EXTENDED_SYNCH,EXTENDED_SYNCH is an internally reserved field. Do not use. Note: This register field is sticky." "0,1" newline bitfld.long 0x10 25. "CORRUPT_LCRC_ENABLE,CORRUPT_LCRC_ENABLE is an internally reserved field. Do not use. Note: This register field is sticky." "0,1" newline bitfld.long 0x10 24. "BEACON_ENABLE,BEACON_ENABLE is an internally reserved field. Do not use. Note: This register field is sticky." "0,1" newline hexmask.long.byte 0x10 16.--21. 1. "LINK_CAPABLE,Link Mode Enable. Sets the number of lanes in the link that you want to connect to the link partner. When you have unused lanes in your system then you must change the value in this register to reflect the number of lanes. You must also.." newline hexmask.long.byte 0x10 12.--15. 1. "RSVDP_12,Reserved for future use." newline hexmask.long.byte 0x10 8.--11. 1. "LINK_RATE,LINK_RATE is an internally reserved field. Do not use. Note: This register field is sticky." newline bitfld.long 0x10 7. "FAST_LINK_MODE,Fast Link Mode. Sets all internal LTSSM millisecond timers to Fast Mode for speeding up simulation. Forces the LTSSM training (link initialization) to use shorter time-outs and to link up faster. The default scaling factor can be changed.." "0,1" newline bitfld.long 0x10 6. "LINK_DISABLE,LINK_DISABLE is an internally reserved field. Do not use. Note: This register field is sticky." "0,1" newline bitfld.long 0x10 5. "DLL_LINK_EN,DLL Link Enable. Enables link initialization. When DLL Link Enable =0 the controller does not transmit InitFC DLLPs and does not establish a link. Note: This register field is sticky." "0,1" newline rbitfld.long 0x10 4. "RSVDP_4,Reserved for future use." "0,1" newline bitfld.long 0x10 3. "RESET_ASSERT,Reset Assert. Triggers a recovery and forces the LTSSM to the hot reset state (downstream port only). Note: This register field is sticky." "0,1" newline bitfld.long 0x10 2. "LOOPBACK_ENABLE,Loopback Enable. Turns on loopback. For more details see 'Loopback'. For M-PCIe to force the master to enter Digital Loopback mode you must set this field to '1' during Configuration.start state(initial discovery/configuration). M-PCIe.." "0,1" newline bitfld.long 0x10 1. "SCRAMBLE_DISABLE,Scramble Disable. Turns off data scrambling. Note: This register field is sticky." "0,1" newline bitfld.long 0x10 0. "VENDOR_SPECIFIC_DLLP_REQ,Vendor Specific DLLP Request. When software writes a '1' to this bit the controller transmits the DLLP contained in the VENDOR_SPEC_DLLP field of VENDOR_SPEC_DLLP_OFF. Reading from this self-clearing register field always.." "0,1" line.long 0x14 "LANE_SKEW_OFF,Lane Skew Register." bitfld.long 0x14 31. "DISABLE_LANE_TO_LANE_DESKEW,Disable Lane-to-Lane Deskew. Causes the controller to disable the internal Lane-to-Lane deskew logic. Note: This register field is sticky." "0,1" newline hexmask.long.byte 0x14 27.--30. 1. "IMPLEMENT_NUM_LANES,Implementation-specific Number of Lanes. Set the implementation-specific number of lanes. Allowed values are: - 4'b0000: 1 lane - 4'b0001: 2 lanes - 4'b0011: 4 lanes - 4'b0111: 8 lanes - 4'b1111: 16 lanes The number of lanes to be.." newline bitfld.long 0x14 26. "ELASTIC_BUFFER_MODE,Selects Elasticity Buffer operating mode: 0: Nominal Half Full Buffer mode 1: Nominal Empty Buffer Mode Note: This register field is sticky." "Nominal Half Full Buffer mode,Nominal Empty Buffer Mode" newline bitfld.long 0x14 25. "ACK_NAK_DISABLE,Ack/Nak Disable. Prevents the controller from sending ACK and NAK DLLPs. Note: This register field is sticky." "0,1" newline bitfld.long 0x14 24. "FLOW_CTRL_DISABLE,Flow Control Disable. Prevents the controller from sending FC DLLPs. Note: This register field is sticky." "0,1" newline hexmask.long.tbyte 0x14 0.--23. 1. "INSERT_LANE_SKEW,INSERT_LANE_SKEW is an internally reserved field. Do not use. Note: This register field is sticky." line.long 0x18 "TIMER_CTRL_MAX_FUNC_NUM_OFF,Timer Control and Max Function Number Register." rbitfld.long 0x18 31. "RSVDP_31,Reserved for future use." "0,1" newline bitfld.long 0x18 29.--30. "FAST_LINK_SCALING_FACTOR,Fast Link Timer Scaling Factor. Sets the scaling factor of LTSSM timer when FAST_LINK_MODE field in PORT_LINK_CTRL_OFF is set to '1'. - 0: Scaling Factor is 1024 (1ms is 1us *a) - 1: Scaling Factor is 256 (1ms is 4us) - 2:.." "Scaling Factor is 1024,Scaling Factor is 256,Scaling Factor is 64,Scaling Factor is 16" newline hexmask.long.byte 0x18 24.--28. 1. "UPDATE_FREQ_TIMER,UPDATE_FREQ_TIMER is an internally reserved field. Do not use. Note: This register field is sticky." newline hexmask.long.byte 0x18 19.--23. 1. "TIMER_MOD_ACK_NAK,Ack Latency Timer Modifier. Increases the timer value for the Ack latency timer in increments of 64 clock cycles. A value of '0' represents no modification to the timer value. For more details see the ROUND_TRIP_LATENCY_TIME_LIMIT.." newline hexmask.long.byte 0x18 14.--18. 1. "TIMER_MOD_REPLAY_TIMER,Replay Timer Limit Modifier. Increases the time-out value for the replay timer in increments of 64 clock cycles at Gen1 or Gen2 speed and in increments of 256 clock cycles at Gen3 speed. A value of '0' represents no modification.." newline hexmask.long.byte 0x18 8.--13. 1. "RSVDP_8,Reserved for future use." newline hexmask.long.byte 0x18 0.--7. 1. "MAX_FUNC_NUM,Maximum function number that can be used in a request. Configuration requests targeted at function numbers above this value are returned with UR (unsupported request). Note: This register field is sticky." line.long 0x1C "SYMBOL_TIMER_FILTER_1_OFF,Symbol Timer Register and Filter Mask 1 Register. The Filter Mask 1 Register modifies the RADM filtering and error handling rules. For more details. see the 'Receive Filtering' section. In each case. '0' applies the associated.." hexmask.long.word 0x1C 16.--31. 1. "MASK_RADM_1,Filter Mask 1. The Filter Mask 1 Register modifies the RADM filtering and error handling rules. For more details see the 'Receive Filtering' section. In each case '0' applies the associated filtering rule and '1' masks the associated.." newline bitfld.long 0x1C 15. "DISABLE_FC_WD_TIMER,Disable FC Watchdog Timer. Note: This register field is sticky." "0,1" newline hexmask.long.byte 0x1C 11.--14. 1. "EIDLE_TIMER,EIDLE_TIMER is an internally reserved field. Do not use. Note: This register field is sticky." newline hexmask.long.word 0x1C 0.--10. 1. "SKP_INT_VAL,SKP Interval Value. The number of symbol times to wait between transmitting SKP ordered sets. Note that the controller actually waits the number of symbol times in this register plus 1 between transmitting SKP ordered sets. Your application.." line.long 0x20 "FILTER_MASK_2_OFF,Filter Mask 2 Register. This register modifies the RADM filtering and error handling rules. For more details. see the 'Receive Filtering' section. In each case. '0' applies the associated filtering rule and '1' masks the associated.." hexmask.long 0x20 0.--31. 1. "MASK_RADM_2,Filter Mask 2. This field modifies the RADM filtering and error handling rules. For more details see the 'Receive Filtering' section. In each case '0' applies the associated filtering rule and '1' masks the associated filtering rule." line.long 0x24 "AMBA_MUL_OB_DECOMP_NP_SUB_REQ_CTRL_OFF,AMBA Multiple Outbound Decomposed NP SubRequests Control Register." hexmask.long 0x24 1.--31. 1. "RSVDP_1,Reserved for future use." newline bitfld.long 0x24 0. "OB_RD_SPLIT_BURST_EN,Enable AMBA Multiple Outbound Decomposed NP SubRequests. This bit when set to '0' disables the possibility of having multiple outstanding non-posted requests that were derived from decomposition of an outbound AMBA request. For more.." "0,1" rgroup.long (0x28+0x700)++0x13 line.long 0x0 "PL_DEBUG0_OFF,Debug Register 0" hexmask.long 0x0 0.--31. 1. "DEB_REG_0,The value on cxpl_debug_info[31:0]." line.long 0x4 "PL_DEBUG1_OFF,Debug Register 1" hexmask.long 0x4 0.--31. 1. "DEB_REG_1,The value on cxpl_debug_info[63:32]." line.long 0x8 "TX_P_FC_CREDIT_STATUS_OFF,Transmit Posted FC Credit Status" hexmask.long.word 0x8 20.--31. 1. "RSVDP_TX_P_FC_CREDIT_STATUS,Reserved for future use." newline hexmask.long.byte 0x8 12.--19. 1. "TX_P_HEADER_FC_CREDIT,Transmit Posted Header FC Credits. The posted Header credits advertised by the receiver at the other end of the link updated with each UpdateFC DLLP. Default value depends on the number of advertised credits for header and data.." newline hexmask.long.word 0x8 0.--11. 1. "TX_P_DATA_FC_CREDIT,Transmit Posted Data FC Credits. The posted Data credits advertised by the receiver at the other end of the link updated with each UpdateFC DLLP. Default value depends on the number of advertised credits for header and data Scaled.." line.long 0xC "TX_NP_FC_CREDIT_STATUS_OFF,Transmit Non-Posted FC Credit Status" hexmask.long.word 0xC 20.--31. 1. "RSVDP_TX_NP_FC_CREDIT_STATUS,Reserved for future use." newline hexmask.long.byte 0xC 12.--19. 1. "TX_NP_HEADER_FC_CREDIT,Transmit Non-Posted Header FC Credits. The non-posted Header credits advertised by the receiver at the other end of the link updated with each UpdateFC DLLP. Default value depends on the number of advertised credits for header and.." newline hexmask.long.word 0xC 0.--11. 1. "TX_NP_DATA_FC_CREDIT,Transmit Non-Posted Data FC Credits. The non-posted Data credits advertised by the receiver at the other end of the link updated with each UpdateFC DLLP. Default value depends on the number of advertised credits for header and data.." line.long 0x10 "TX_CPL_FC_CREDIT_STATUS_OFF,Transmit Completion FC Credit Status" hexmask.long.word 0x10 20.--31. 1. "RSVDP_TX_CPL_FC_CREDIT_STATUS,Reserved for future use." newline hexmask.long.byte 0x10 12.--19. 1. "TX_CPL_HEADER_FC_CREDIT,Transmit Completion Header FC Credits. The Completion Header credits advertised by the receiver at the other end of the link updated with each UpdateFC DLLP. Default value depends on the number of advertised credits for header.." newline hexmask.long.word 0x10 0.--11. 1. "TX_CPL_DATA_FC_CREDIT,Transmit Completion Data FC Credits. The Completion Data credits advertised by the receiver at the other end of the link updated with each UpdateFC DLLP. Default value depends on the number of advertised credits for header and data.." group.long (0x3C+0x700)++0x3 line.long 0x0 "QUEUE_STATUS_OFF,Queue Status" bitfld.long 0x0 31. "TIMER_MOD_FLOW_CONTROL_EN,FC Latency Timer Override Enable. When this bit is set the value from the 'FC Latency Timer Override Value' field in this register will override the FC latency timer value that the controller calculates according to the PCIe.." "0,1" newline rbitfld.long 0x0 29.--30. "RSVDP_29,Reserved for future use." "0,1,2,3" newline hexmask.long.word 0x0 16.--28. 1. "TIMER_MOD_FLOW_CONTROL,FC Latency Timer Override Value. When you set the 'FC Latency Timer Override Enable' in this register the value in this field will override the FC latency timer value that the controller calculates according to the PCIe.." newline rbitfld.long 0x0 13. "RX_SERIALIZATION_Q_NON_EMPTY,Receive Serialization Queue Not Empty. Indicates there is data in the serialization queue." "0,1" newline hexmask.long.word 0x0 4.--12. 1. "RSVDP_4,Reserved for future use." newline bitfld.long 0x0 3. "RX_QUEUE_OVERFLOW,Receive Credit Queue Overflow. Indicates insufficient buffer space available to write to the P/NP/CPL credit queue." "0,1" newline rbitfld.long 0x0 2. "RX_QUEUE_NON_EMPTY,Receive Credit Queue Not Empty. Indicates there is data in one or more of the receive buffers." "0,1" newline rbitfld.long 0x0 1. "TX_RETRY_BUFFER_NE,Transmit Retry Buffer Not Empty. Indicates that there is data in the transmit retry buffer." "0,1" newline rbitfld.long 0x0 0. "RX_TLP_FC_CREDIT_NON_RETURN,Received TLP FC Credits Not Returned. Indicates that the controller has received a TLP but has not yet sent an UpdateFC DLLP indicating that the credits for that TLP have been restored by the receiver at the other end of the.." "0,1" rgroup.long (0x40+0x700)++0x7 line.long 0x0 "VC_TX_ARBI_1_OFF,VC Transmit Arbitration Register 1" hexmask.long.byte 0x0 24.--31. 1. "WRR_WEIGHT_VC_3,WRR Weight for VC3. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R" newline hexmask.long.byte 0x0 16.--23. 1. "WRR_WEIGHT_VC_2,WRR Weight for VC2. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R" newline hexmask.long.byte 0x0 8.--15. 1. "WRR_WEIGHT_VC_1,WRR Weight for VC1. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R" newline hexmask.long.byte 0x0 0.--7. 1. "WRR_WEIGHT_VC_0,WRR Weight for VC0. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R" line.long 0x4 "VC_TX_ARBI_2_OFF,VC Transmit Arbitration Register 2" hexmask.long.byte 0x4 24.--31. 1. "WRR_WEIGHT_VC_7,WRR Weight for VC7. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R" newline hexmask.long.byte 0x4 16.--23. 1. "WRR_WEIGHT_VC_6,WRR Weight for VC6. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R" newline hexmask.long.byte 0x4 8.--15. 1. "WRR_WEIGHT_VC_5,WRR Weight for VC5. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R" newline hexmask.long.byte 0x4 0.--7. 1. "WRR_WEIGHT_VC_4,WRR Weight for VC4. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R" group.long (0x48+0x700)++0xB line.long 0x0 "VC0_P_RX_Q_CTRL_OFF,Segmented-Buffer VC0 Posted Receive Queue Control." bitfld.long 0x0 31. "VC_ORDERING_RX_Q,VC Ordering for Receive Queues. Determines the VC ordering rule for the receive queues used only in the segmented-buffer configuration: - 1: Strict ordering higher numbered VCs have higher priority - 0: Round robin Note: This register.." "Round robin,Strict ordering" newline bitfld.long 0x0 30. "TLP_TYPE_ORDERING_VC0,TLP Type Ordering for VC0. Determines the TLP type ordering rule for VC0 receive queues used only in the segmented-buffer configuration: - 1: PCIe ordering rules (recommended) - 0: Strict ordering: posted completion then.." "Strict ordering: posted,PCIe ordering rules" newline bitfld.long 0x0 28.--29. "RESERVED5,Reserved. Note: This register field is sticky." "0,1,2,3" newline bitfld.long 0x0 26.--27. "VC0_P_DATA_SCALE,VC0 Scale Posted Data Credites. Note: This register field is sticky." "0,1,2,3" newline bitfld.long 0x0 24.--25. "VC0_P_HDR_SCALE,VC0 Scale Posted Header Credites. Note: This register field is sticky." "0,1,2,3" newline bitfld.long 0x0 21.--23. "VC0_P_TLP_Q_MODE,Reserved. Note: This register field is sticky." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 20. "RESERVED4,Reserved. Note: This register field is sticky." "0,1" newline hexmask.long.byte 0x0 12.--19. 1. "VC0_P_HEADER_CREDIT,VC0 Posted Header Credits. The number of initial posted header credits for VC0 used only in the segmented-buffer configuration. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R (sticky) Note: This.." newline hexmask.long.word 0x0 0.--11. 1. "VC0_P_DATA_CREDIT,VC0 Posted Data Credits. The number of initial posted data credits for VC0 used only in the segmented-buffer configuration. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R (sticky) Note: This.." line.long 0x4 "VC0_NP_RX_Q_CTRL_OFF,Segmented-Buffer VC0 Non-Posted Receive Queue Control." hexmask.long.byte 0x4 28.--31. 1. "RESERVED7,Reserved. Note: This register field is sticky." newline bitfld.long 0x4 26.--27. "VC0_NP_DATA_SCALE,VC0 Scale Non-Posted Data Credites. Note: This register field is sticky." "0,1,2,3" newline bitfld.long 0x4 24.--25. "VC0_NP_HDR_SCALE,VC0 Scale Non-Posted Header Credites. Note: This register field is sticky." "0,1,2,3" newline bitfld.long 0x4 21.--23. "VC0_NP_TLP_Q_MODE,Reserved. Note: This register field is sticky." "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 20. "RESERVED6,Reserved. Note: This register field is sticky." "0,1" newline hexmask.long.byte 0x4 12.--19. 1. "VC0_NP_HEADER_CREDIT,VC0 Non-Posted Header Credits. The number of initial non-posted header credits for VC0 used only in the segmented-buffer configuration. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R (sticky).." newline hexmask.long.word 0x4 0.--11. 1. "VC0_NP_DATA_CREDIT,VC0 Non-Posted Data Credits. The number of initial non-posted data credits for VC0 used only in the segmented-buffer configuration. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R (sticky) Note:.." line.long 0x8 "VC0_CPL_RX_Q_CTRL_OFF,Segmented-Buffer VC0 Completion Receive Queue Control." hexmask.long.byte 0x8 28.--31. 1. "RESERVED9,Reserved. Note: This register field is sticky." newline bitfld.long 0x8 26.--27. "VC0_CPL_DATA_SCALE,VC0 Scale CPL Data Credites. Note: This register field is sticky." "0,1,2,3" newline bitfld.long 0x8 24.--25. "VC0_CPL_HDR_SCALE,VC0 Scale CPL Header Credites. Note: This register field is sticky." "0,1,2,3" newline bitfld.long 0x8 21.--23. "VC0_CPL_TLP_Q_MODE,Reserved. Note: This register field is sticky." "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 20. "RESERVED8,Reserved. Note: This register field is sticky." "0,1" newline hexmask.long.byte 0x8 12.--19. 1. "VC0_CPL_HEADER_CREDIT,VC0 Completion Header Credits. The number of initial Completion header credits for VC0 used only in the segmented-buffer configuration. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R (sticky).." newline hexmask.long.word 0x8 0.--11. 1. "VC0_CPL_DATA_CREDIT,VC0 Completion Data Credits. The number of initial Completion data credits for VC0 used only in the segmented-buffer configuration. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R (sticky) Note:.." group.long (0x10C+0x700)++0x3 line.long 0x0 "GEN2_CTRL_OFF,This register is used to control various functions of the controller related to link training. lane reversal. and equalization." rbitfld.long 0x0 31. "RSVDP_31,Reserved for future use." "0,1" newline bitfld.long 0x0 30. "FORCE_LANE_FLIP,Enable to force the LANE_UNDER_TEST physical lane flips to logical lane 0. All the other physical lanes are turned off. The LINK_CAPABLE register must be set to 1 and only x1 link can be formed if the FORCE_LANE_FLIP register is set to 1." "0,1" newline hexmask.long.byte 0x0 24.--27. 1. "LANE_UNDER_TEST,The Lane Under Test is the lane for Forced Lane Flip or for Loopback Eq. The value is from 0 to CX_NL. Only one lane is configured each time. The default of this field is the CX_DEFAULT_LANE_UNDER_TEST configuration parameter. This field.." newline rbitfld.long 0x0 22.--23. "RSVDP_22,Reserved for future use." "0,1,2,3" newline bitfld.long 0x0 21. "GEN1_EI_INFERENCE,Electrical Idle Inference Mode at Gen1 Rate. Programmable mode to determine inferred electrical idle (EI) in Recovery.Speed or Loopback.Active (as slave) state at Gen1 speed by looking for a '1' value on RxElecIdle instead of looking.." "Use RxElecIdle signal to infer Electrical Idle,Use RxValid signal to infer Electrical Idle" newline bitfld.long 0x0 20. "SEL_DEEMPHASIS,Used to set the de-emphasis level for upstream ports. This bit selects the level of de-emphasis the link operates at. - 0: -6 dB - 1: -3.5 dB This field is reserved (fixed to '0') for M-PCIe. Note: The access attributes of this field are.." "0,1" newline bitfld.long 0x0 19. "CONFIG_TX_COMP_RX,Config Tx Compliance Receive Bit. When set to 1 signals LTSSM to transmit TS ordered sets with the compliance receive bit assert (equal to '1'). This field is reserved (fixed to '0') for M-PCIe. Note: The access attributes of this.." "0,1" newline bitfld.long 0x0 18. "CONFIG_PHY_TX_CHANGE,Config PHY Tx Swing. Controls the PHY transmitter voltage swing level. The controller drives the mac_phy_txswing output from this register bit field. - 0: Full Swing - 1: Low Swing This field is reserved (fixed to '0') for M-PCIe." "Full Swing,Low Swing" newline bitfld.long 0x0 17. "DIRECT_SPEED_CHANGE,Directed Speed Change. Writing '1' to this field instructs the LTSSM to initiate a speed change to Gen2 or Gen3 after the link is initialized at Gen1 speed. When the speed change occurs the controller will clear the contents of this.." "0,1" newline bitfld.long 0x0 16. "AUTO_LANE_FLIP_CTRL_EN,Enable Auto flipping of the lanes. You must set the CX_AUTO_LANE_FLIP_CTRL_EN configuration parameter to include the hardware for this feature in the controller. For more details see the 'Lane Reversal' appendix in the Databook." "0,1" newline bitfld.long 0x0 13.--15. "PRE_DET_LANE,Predetermined Lane for Auto Flip. This field defines which physical lane is connected to logical Lane0 by the flip operation performed in Detect. This field is used to restrict the receiver detect procedure to a particular lane when the.." "LANE0,LANE1,LANE3,LANE7,LANE15,?,?,?" newline hexmask.long.byte 0x0 8.--12. 1. "NUM_OF_LANES,Predetermined Number of Lanes. Defines the number of lanes which are connected and not bad. Used to limit the effective link width to ignore 'broken' or 'unused' lanes that detect a receiver. Indicates the number of lanes to check for exit.." newline hexmask.long.byte 0x0 0.--7. 1. "FAST_TRAINING_SEQ,Sets the Number of Fast Training Sequences (N_FTS) that the controller advertises as its N_FTS during Gen2 or Gen3 link training. This value is used to inform the link partner about the PHY's ability to recover synchronization after a.." rgroup.long (0x110+0x700)++0x3 line.long 0x0 "PHY_STATUS_OFF,PHY Status Register. Memory mapped register from phy_cfg_status GPIO input pins." hexmask.long 0x0 0.--31. 1. "PHY_STATUS,PHY Status. Data received directly from the phy_cfg_status bus. These is a GPIO register reflecting the values on the static phy_cfg_status input signals. The usage is left completely to the user and does not in any way influence controller.." group.long (0x114+0x700)++0x3 line.long 0x0 "PHY_CONTROL_OFF,PHY Control Register. Memory mapped register to cfg_phy_control GPIO output pins." hexmask.long 0x0 0.--31. 1. "PHY_CONTROL,PHY Control. Data sent directly to the cfg_phy_control bus. These is a GPIO register driving the values on the static cfg_phy_control output signals. The usage is left completely to the user and does not in any way influence controller.." group.long (0x11C+0x700)++0x77 line.long 0x0 "TRGT_MAP_CTRL_OFF,Programmable Target Map Control Register." hexmask.long.word 0x0 21.--31. 1. "TARGET_MAP_RESERVED_21_31,Reserved. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R (sticky)" newline hexmask.long.byte 0x0 16.--20. 1. "TARGET_MAP_INDEX,The number of the PF Function on which the Target Values are set. This register does not respect the Byte Enable setting. any write will affect all register bits." newline rbitfld.long 0x0 13.--15. "TARGET_MAP_RESERVED_13_15,Reserved. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R (sticky)" "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x0 7.--12. 1. "TARGET_MAP_VF,Target Values for each BAR on the VF Function selected by the index number. This register does not respect the Byte Enable setting. any write will affect all register bits." newline bitfld.long 0x0 6. "TARGET_MAP_ROM,Target Value for the ROM page of the PF Function selected by the index number. This register does not respect the Byte Enable setting. any write will affect all register bits." "0,1" newline hexmask.long.byte 0x0 0.--5. 1. "TARGET_MAP_PF,Target Values for each BAR on the PF Function selected by the index number. This register does not respect the Byte Enable setting. any write will affect all register bits." line.long 0x4 "MSI_CTRL_ADDR_OFF,Integrated MSI Reception Module (iMRM) Address Register." hexmask.long 0x4 0.--31. 1. "MSI_CTRL_ADDR,Integrated MSI Reception Module Address. System specified address for MSI memory write transaction termination. Within the AXI Bridge every received Memory Write request is examined to see if it targets the MSI Address that has been.." line.long 0x8 "MSI_CTRL_UPPER_ADDR_OFF,Integrated MSI Reception Module Upper Address Register." hexmask.long 0x8 0.--31. 1. "MSI_CTRL_UPPER_ADDR,Integrated MSI Reception Module Upper Address. System specified upper address for MSI memory write transaction termination. Allows functions to support a 64-bit MSI address. Note: This register field is sticky." line.long 0xC "MSI_CTRL_INT_0_EN_OFF,Integrated MSI Reception Module Interrupt#i Enable Register." hexmask.long 0xC 0.--31. 1. "MSI_CTRL_INT_0_EN,MSI Interrupt#i Enable. Specifies which interrupts are enabled. When an MSI is received from a disabled interrupt no status bit gets set in MSI controller interrupt status register. Each bit corresponds to a single MSI Interrupt.." line.long 0x10 "MSI_CTRL_INT_0_MASK_OFF,Integrated MSI Reception Module Interrupt#i Mask Register." hexmask.long 0x10 0.--31. 1. "MSI_CTRL_INT_0_MASK,MSI Interrupt#i Mask. Allows enabled interrupts to be masked. When an MSI is received for a masked interrupt the corresponding status bit gets set in the interrupt status register but the msi_ctrl_int output is not set HIGH. Each bit.." line.long 0x14 "MSI_CTRL_INT_0_STATUS_OFF,Integrated MSI Reception Module Interrupt#i Status Register." hexmask.long 0x14 0.--31. 1. "MSI_CTRL_INT_0_STATUS,MSI Interrupt#i Status. When an MSI is detected for EP#i one bit in this register is set. The decoding of the data payload of the MSI Memory Write request determines which bit gets set. A status is bit is cleared by writing a 1 to.." line.long 0x18 "MSI_CTRL_INT_1_EN_OFF,Integrated MSI Reception Module Interrupt#i Enable Register." hexmask.long 0x18 0.--31. 1. "MSI_CTRL_INT_1_EN,MSI Interrupt#i Enable. Specifies which interrupts are enabled. When an MSI is received from a disabled interrupt no status bit gets set in MSI controller interrupt status register. Each bit corresponds to a single MSI Interrupt.." line.long 0x1C "MSI_CTRL_INT_1_MASK_OFF,Integrated MSI Reception Module Interrupt#i Mask Register." hexmask.long 0x1C 0.--31. 1. "MSI_CTRL_INT_1_MASK,MSI Interrupt#i Mask. Allows enabled interrupts to be masked. When an MSI is received for a masked interrupt the corresponding status bit gets set in the interrupt status register but the msi_ctrl_int output is not set HIGH. Each bit.." line.long 0x20 "MSI_CTRL_INT_1_STATUS_OFF,Integrated MSI Reception Module Interrupt#i Status Register." hexmask.long 0x20 0.--31. 1. "MSI_CTRL_INT_1_STATUS,MSI Interrupt#i Status. When an MSI is detected for EP#i one bit in this register is set. The decoding of the data payload of the MSI Memory Write request determines which bit gets set. A status is bit is cleared by writing a 1 to.." line.long 0x24 "MSI_CTRL_INT_2_EN_OFF,Integrated MSI Reception Module Interrupt#i Enable Register." hexmask.long 0x24 0.--31. 1. "MSI_CTRL_INT_2_EN,MSI Interrupt#i Enable. Specifies which interrupts are enabled. When an MSI is received from a disabled interrupt no status bit gets set in MSI controller interrupt status register. Each bit corresponds to a single MSI Interrupt.." line.long 0x28 "MSI_CTRL_INT_2_MASK_OFF,Integrated MSI Reception Module Interrupt#i Mask Register." hexmask.long 0x28 0.--31. 1. "MSI_CTRL_INT_2_MASK,MSI Interrupt#i Mask. Allows enabled interrupts to be masked. When an MSI is received for a masked interrupt the corresponding status bit gets set in the interrupt status register but the msi_ctrl_int output is not set HIGH. Each bit.." line.long 0x2C "MSI_CTRL_INT_2_STATUS_OFF,Integrated MSI Reception Module Interrupt#i Status Register." hexmask.long 0x2C 0.--31. 1. "MSI_CTRL_INT_2_STATUS,MSI Interrupt#i Status. When an MSI is detected for EP#i one bit in this register is set. The decoding of the data payload of the MSI Memory Write request determines which bit gets set. A status is bit is cleared by writing a 1 to.." line.long 0x30 "MSI_CTRL_INT_3_EN_OFF,Integrated MSI Reception Module Interrupt#i Enable Register." hexmask.long 0x30 0.--31. 1. "MSI_CTRL_INT_3_EN,MSI Interrupt#i Enable. Specifies which interrupts are enabled. When an MSI is received from a disabled interrupt no status bit gets set in MSI controller interrupt status register. Each bit corresponds to a single MSI Interrupt.." line.long 0x34 "MSI_CTRL_INT_3_MASK_OFF,Integrated MSI Reception Module Interrupt#i Mask Register." hexmask.long 0x34 0.--31. 1. "MSI_CTRL_INT_3_MASK,MSI Interrupt#i Mask. Allows enabled interrupts to be masked. When an MSI is received for a masked interrupt the corresponding status bit gets set in the interrupt status register but the msi_ctrl_int output is not set HIGH. Each bit.." line.long 0x38 "MSI_CTRL_INT_3_STATUS_OFF,Integrated MSI Reception Module Interrupt#i Status Register." hexmask.long 0x38 0.--31. 1. "MSI_CTRL_INT_3_STATUS,MSI Interrupt#i Status. When an MSI is detected for EP#i one bit in this register is set. The decoding of the data payload of the MSI Memory Write request determines which bit gets set. A status is bit is cleared by writing a 1 to.." line.long 0x3C "MSI_CTRL_INT_4_EN_OFF,Integrated MSI Reception Module Interrupt#i Enable Register." hexmask.long 0x3C 0.--31. 1. "MSI_CTRL_INT_4_EN,MSI Interrupt#i Enable. Specifies which interrupts are enabled. When an MSI is received from a disabled interrupt no status bit gets set in MSI controller interrupt status register. Each bit corresponds to a single MSI Interrupt.." line.long 0x40 "MSI_CTRL_INT_4_MASK_OFF,Integrated MSI Reception Module Interrupt#i Mask Register." hexmask.long 0x40 0.--31. 1. "MSI_CTRL_INT_4_MASK,MSI Interrupt#i Mask. Allows enabled interrupts to be masked. When an MSI is received for a masked interrupt the corresponding status bit gets set in the interrupt status register but the msi_ctrl_int output is not set HIGH. Each bit.." line.long 0x44 "MSI_CTRL_INT_4_STATUS_OFF,Integrated MSI Reception Module Interrupt#i Status Register." hexmask.long 0x44 0.--31. 1. "MSI_CTRL_INT_4_STATUS,MSI Interrupt#i Status. When an MSI is detected for EP#i one bit in this register is set. The decoding of the data payload of the MSI Memory Write request determines which bit gets set. A status is bit is cleared by writing a 1 to.." line.long 0x48 "MSI_CTRL_INT_5_EN_OFF,Integrated MSI Reception Module Interrupt#i Enable Register." hexmask.long 0x48 0.--31. 1. "MSI_CTRL_INT_5_EN,MSI Interrupt#i Enable. Specifies which interrupts are enabled. When an MSI is received from a disabled interrupt no status bit gets set in MSI controller interrupt status register. Each bit corresponds to a single MSI Interrupt.." line.long 0x4C "MSI_CTRL_INT_5_MASK_OFF,Integrated MSI Reception Module Interrupt#i Mask Register." hexmask.long 0x4C 0.--31. 1. "MSI_CTRL_INT_5_MASK,MSI Interrupt#i Mask. Allows enabled interrupts to be masked. When an MSI is received for a masked interrupt the corresponding status bit gets set in the interrupt status register but the msi_ctrl_int output is not set HIGH. Each bit.." line.long 0x50 "MSI_CTRL_INT_5_STATUS_OFF,Integrated MSI Reception Module Interrupt#i Status Register." hexmask.long 0x50 0.--31. 1. "MSI_CTRL_INT_5_STATUS,MSI Interrupt#i Status. When an MSI is detected for EP#i one bit in this register is set. The decoding of the data payload of the MSI Memory Write request determines which bit gets set. A status is bit is cleared by writing a 1 to.." line.long 0x54 "MSI_CTRL_INT_6_EN_OFF,Integrated MSI Reception Module Interrupt#i Enable Register." hexmask.long 0x54 0.--31. 1. "MSI_CTRL_INT_6_EN,MSI Interrupt#i Enable. Specifies which interrupts are enabled. When an MSI is received from a disabled interrupt no status bit gets set in MSI controller interrupt status register. Each bit corresponds to a single MSI Interrupt.." line.long 0x58 "MSI_CTRL_INT_6_MASK_OFF,Integrated MSI Reception Module Interrupt#i Mask Register." hexmask.long 0x58 0.--31. 1. "MSI_CTRL_INT_6_MASK,MSI Interrupt#i Mask. Allows enabled interrupts to be masked. When an MSI is received for a masked interrupt the corresponding status bit gets set in the interrupt status register but the msi_ctrl_int output is not set HIGH. Each bit.." line.long 0x5C "MSI_CTRL_INT_6_STATUS_OFF,Integrated MSI Reception Module Interrupt#i Status Register." hexmask.long 0x5C 0.--31. 1. "MSI_CTRL_INT_6_STATUS,MSI Interrupt#i Status. When an MSI is detected for EP#i one bit in this register is set. The decoding of the data payload of the MSI Memory Write request determines which bit gets set. A status is bit is cleared by writing a 1 to.." line.long 0x60 "MSI_CTRL_INT_7_EN_OFF,Integrated MSI Reception Module Interrupt#i Enable Register." hexmask.long 0x60 0.--31. 1. "MSI_CTRL_INT_7_EN,MSI Interrupt#i Enable. Specifies which interrupts are enabled. When an MSI is received from a disabled interrupt no status bit gets set in MSI controller interrupt status register. Each bit corresponds to a single MSI Interrupt.." line.long 0x64 "MSI_CTRL_INT_7_MASK_OFF,Integrated MSI Reception Module Interrupt#i Mask Register." hexmask.long 0x64 0.--31. 1. "MSI_CTRL_INT_7_MASK,MSI Interrupt#i Mask. Allows enabled interrupts to be masked. When an MSI is received for a masked interrupt the corresponding status bit gets set in the interrupt status register but the msi_ctrl_int output is not set HIGH. Each bit.." line.long 0x68 "MSI_CTRL_INT_7_STATUS_OFF,Integrated MSI Reception Module Interrupt#i Status Register." hexmask.long 0x68 0.--31. 1. "MSI_CTRL_INT_7_STATUS,MSI Interrupt#i Status. When an MSI is detected for EP#i one bit in this register is set. The decoding of the data payload of the MSI Memory Write request determines which bit gets set. A status is bit is cleared by writing a 1 to.." line.long 0x6C "MSI_GPIO_IO_OFF,Integrated MSI Reception Module General Purpose IO Register." hexmask.long 0x6C 0.--31. 1. "MSI_GPIO_REG,MSI GPIO Register. The contents of this register drives the top-level GPIO msi_ctrl_io[31:0] Note: This register field is sticky." line.long 0x70 "CLOCK_GATING_CTRL_OFF,This register enables you to disable dynamic clock gating. By default dynamic clock gating is on. allowing the controller to autonomously enable and disable its clocks. The clock gating is performed in the clock and reset module." hexmask.long 0x70 2.--31. 1. "RSVDP_2,Reserved for future use." newline bitfld.long 0x70 1. "AXI_CLK_GATING_EN,AXI Clock Gating Enable. This register enables the AXI Bridge to autonomously enable and disable the AXI Master clock the AXI Slave clock and the AXI DBI slave clock. The DWC_pcie_clk_rst.v module provides the gated clock.." "Disable,Enable" newline bitfld.long 0x70 0. "RADM_CLK_GATING_EN,RADM Clock Gating Enable. This register if set enables the RADM to autonomously enable and disable its clock. The DWC_pcie_clk_rst.v module provides the gated clock radm_clk_g to the RADM and is enabled when the controllers clock.." "Disable,Enable" line.long 0x74 "GEN3_RELATED_OFF,Gen3 Control Register. There is no Gen3-specific N_FTS field. The N_FTS field in the 'Link Width and Speed Change Control Register' is used for both Gen2 and Gen3 speed modes. There is no Gen3-specific 'Directed Speed Change' field. The.." hexmask.long.byte 0x74 26.--31. 1. "RSVDP_26,Reserved for future use." newline bitfld.long 0x74 23. "GEN3_EQ_INVREQ_EVAL_DIFF_DISABLE,Eq InvalidRequest and RxEqEval Different Time Assertion Disable. Disable the assertion of Eq InvalidRequest and RxEqEval at different time. Note: When CX_GEN4_SPEED/CX_GEN5_SPEED this register is shared for Gen3 and.." "0,1" newline rbitfld.long 0x74 19.--20. "RSVDP_19,Reserved for future use." "0,1,2,3" newline bitfld.long 0x74 18. "GEN3_DC_BALANCE_DISABLE,DC Balance Disable. Disable DC Balance feature. Note: When CX_GEN4_SPEED/CX_GEN5_SPEED this register is shared for Gen3 and Gen4/Gen5 data rate. Note: This register field is sticky." "0,1" newline bitfld.long 0x74 17. "GEN3_DLLP_XMT_DELAY_DISABLE,DLLP Transmission Delay Disable. Disable delay transmission of DLLPs before equalization. Note: When CX_GEN4_SPEED/CX_GEN5_SPEED this register is shared for Gen3 and Gen4/Gen5 data rate. Note: This register field is sticky." "0,1" newline bitfld.long 0x74 16. "GEN3_EQUALIZATION_DISABLE,Equalization Disable. Disable equalization feature. This bit cannot be changed once the LTSSM starts link training. Note: When CX_GEN4_SPEED/CX_GEN5_SPEED this register is shared for Gen3 and Gen4/Gen5 data rate. Note: This.." "0,1" newline rbitfld.long 0x74 14.--15. "RSVDP_14,Reserved for future use." "0,1,2,3" newline bitfld.long 0x74 13. "RXEQ_RGRDLESS_RXTS,When set to '1' the controller as Gen3 EQ master asserts RxEqEval to instruct the PHY to do Rx adaptation and evaluation after a 500ns timeout from a new preset request. - 0: mac_phy_rxeqeval asserts after 1us and 2 TS1 received from.." "mac_phy_rxeqeval asserts after 1us and 2 TS1..,mac_phy_rxeqeval asserts after 500ns regardless.." newline bitfld.long 0x74 12. "RXEQ_PH01_EN,Rx Equalization Phase 0/Phase 1 Hold Enable. When this bit is set the upstream port holds phase 0 (the downstream port holds phase 1) for 10ms. Holding phase 0 or phase 1 can be used to allow sufficient time for Rx Equalization to be.." "Tx equalization only in phase 2/3,No Tx equalization" newline bitfld.long 0x74 11. "EQ_REDO,Equalization Redo Disable. Disable autonomous mechanism for requesting to redo the equalization process. The received presets or coefficients mismatch in Recovery.RcvrLock after Recovery EQ phases causes the EQ redo requests. If the EQ redo is.." "0,1" newline bitfld.long 0x74 10. "EQ_EIEOS_CNT,Equalization EIEOS Count Reset Disable. Disable requesting reset of EIEOS count during equalization. Note: When CX_GEN4_SPEED/CX_GEN5_SPEED this register is shared for Gen3 and Gen4/Gen5 data rate. Note: This register field is sticky." "0,1" newline bitfld.long 0x74 9. "EQ_PHASE_2_3,Equalization Phase 2 and Phase 3 Disable. This applies to downstream ports only. Note: When CX_GEN4_SPEED/CX_GEN5_SPEED this register is shadow register for Gen3 and Gen4/Gen5 data rate. If RATE_SHADOW_SEL==00b this register is for Gen3.." "0,1" newline bitfld.long 0x74 8. "DISABLE_SCRAMBLER_GEN_3,Disable Scrambler for Gen3 and Gen4 Data Rate. The Gen3 and Gen4 scrambler/descrambler within the controller needs to be disabled when the scrambling function is implemented outside of the controller (for example within the PHY)." "0,1" newline hexmask.long.byte 0x74 1.--7. 1. "RSVDP_1,Reserved for future use." newline bitfld.long 0x74 0. "GEN3_ZRXDC_NONCOMPL,Gen3 Receiver Impedance ZRX-DC Not Compliant. Receivers that operate at 8.0 GT/s with an impedance other than the range defined by the ZRX-DC parameter for 2.5 GT/s (40-60 Ohms) must meet additional behavior requirements in the.." "The receiver complies with the ZRX-DC parameter..,The receiver does not comply with the ZRX-DC.." group.long (0x1A8+0x700)++0x7 line.long 0x0 "GEN3_EQ_CONTROL_OFF,Gen3 EQ Control Register. This register controls equalization for Phase2 in an upstream port (USP). or Phase3 in a downstream port (DSP). M-PCIe doesn't have Conventional PCIe Gen3 feature. The registers of this section do not exist." hexmask.long.byte 0x0 27.--31. 1. "RSVDP_27,Reserved for future use." newline bitfld.long 0x0 26. "GEN3_REQ_SEND_CONSEC_EIEOS_FOR_PSET_MAP,Request controller to send back-to-back EIEOS in Recovery.RcvrLock state until presets to coefficients mapping is complete. - 0: Do not request - 1: request Note: Gen3 and Gen4 share the same register bit and have.." "Do not request,request" newline bitfld.long 0x0 25. "GEN3_EQ_PSET_REQ_AS_COEF,GEN3_EQ_PSET_REQ_AS_COEF is an internally reserved field. Do not use. Note: This register field is sticky." "0,1" newline bitfld.long 0x0 24. "GEN3_EQ_FOM_INC_INITIAL_EVAL,Include Initial FOM. Include or not the FOM feedback from the initial preset evaluation performed in the EQ Master when finding the highest FOM among all preset evaluations. - 0: Do not include - 1: Include Note: When.." "Do not include,Include" newline hexmask.long.word 0x0 8.--23. 1. "GEN3_EQ_PSET_REQ_VEC,Preset Request Vector. Requesting of Presets during the initial part of the EQ Master Phase. Encoding scheme is as follows: Bit [15:0] =0x0: No preset is requested and evaluated in EQ Master Phase. Bit [i] =1: 'Preset=i' is requested.." newline rbitfld.long 0x0 7. "RSVDP_7,Reserved for future use." "0,1" newline bitfld.long 0x0 6. "GEN3_LOWER_RATE_EQ_REDO_ENABLE,Support EQ redo and lower rate change: - 0: not support - 1: support Note: Gen3 and Gen4 share the same register bit and have the same feature. Note: This register field is sticky." "not support,support" newline bitfld.long 0x0 5. "GEN3_EQ_EVAL_2MS_DISABLE,Phase2_3 2 ms Timeout Disable. Determine behavior in Phase2 for USP (Phase3 if DSP) when the PHY does not respond within 2ms to the assertion of RxEqEval: - 0: abort the current evaluation stop any attempt to modify the remote.." "abort the current evaluation,ignore the 2ms timeout and continue as normal" newline bitfld.long 0x0 4. "GEN3_EQ_PHASE23_EXIT_MODE,Behavior After 24 ms Timeout (when optimal settings are not found). For a USP: Determine next LTSSM state from Phase2 after 24ms Timeout - 0: Recovery.Speed - 1: Recovery.Equalization.Phase3 When optimal settings are not found.." "Equalization Phase 3 Successful status bit is..,Recovery" newline hexmask.long.byte 0x0 0.--3. 1. "GEN3_EQ_FB_MODE,Feedback Mode. - 0000b: Direction Change - 0001b: Figure Of Merit - 0010b: Reserved - .....: Reserved - 1111b: Reserved Note: When CX_GEN4_SPEED/CX_GEN5_SPEED this register is a shadow register for Gen3 and Gen4/Gen5 data rate. If.." line.long 0x4 "GEN3_EQ_FB_MODE_DIR_CHANGE_OFF,Gen3 EQ Direction Change Feedback Mode Control Register. Equalization controls to be used in Phase2 (USP) or Phase 3 (DSP). when you set the Feedback Mode in 'Gen3 EQ Control Register' to 'Direction Change.' These fields.." hexmask.long.word 0x4 18.--31. 1. "RSVDP_18,Reserved for future use." newline hexmask.long.byte 0x4 14.--17. 1. "GEN3_EQ_FMDC_MAX_POST_CUSROR_DELTA,Convergence Window Aperture for C+1. Post-cursor coefficients maximum delta within the convergence window depth. Allowed range: 0 1 2 ..15. Note: When CX_GEN4_SPEED/CX_GEN5_SPEED this register is shadow register for.." newline hexmask.long.byte 0x4 10.--13. 1. "GEN3_EQ_FMDC_MAX_PRE_CUSROR_DELTA,Convergence Window Aperture for C-1. Pre-cursor coefficients maximum delta within the convergence window depth. Allowed range: 0 1 2 ..15. Note: When CX_GEN4_SPEED/CX_GEN5_SPEED this register is shadow register for Gen3.." newline hexmask.long.byte 0x4 5.--9. 1. "GEN3_EQ_FMDC_N_EVALS,Convergence Window Depth. Number of consecutive evaluations considered in Phase 2/3 when determining if optimal coefficients have been found. Allowed range: 0 1 2 ..16 up to a maximum of CX_GEN3_EQ_COEFQ_DEPTH. When set to 0 EQ.." newline hexmask.long.byte 0x4 0.--4. 1. "GEN3_EQ_FMDC_T_MIN_PHASE23,Minimum Time (in ms) To Remain in EQ Master Phase. The LTSSM stays in EQ Master phase for at least this amount of time before starting to check for convergence of the coefficients. Allowed values 0 1 ... 24. Note: When.." group.long (0x1B4+0x700)++0x27 line.long 0x0 "ORDER_RULE_CTRL_OFF,Order Rule Control Register." hexmask.long.word 0x0 16.--31. 1. "RSVDP_16,Reserved for future use." newline hexmask.long.byte 0x0 8.--15. 1. "CPL_PASS_P,Completion Passing Posted Ordering Rule Control. Determines if CPL can pass halted P queue. - 0: CPL can not pass P (recommended) - 1: CPL can pass P" newline hexmask.long.byte 0x0 0.--7. 1. "NP_PASS_P,Non-Posted Passing Posted Ordering Rule Control. Determines if NP can pass halted P queue. - 0 : NP can not pass P (recommended). - 1 : NP can pass P" line.long 0x4 "PIPE_LOOPBACK_CONTROL_OFF,PIPE Loopback Control Register." bitfld.long 0x4 31. "PIPE_LOOPBACK,PIPE Loopback Enable. Indicates RMMI Loopback if M-PCIe. Note: This register field is sticky." "0,1" newline hexmask.long.byte 0x4 27.--30. 1. "RSVDP_27,Reserved for future use." newline bitfld.long 0x4 24.--26. "RXSTATUS_VALUE,RXSTATUS_VALUE is an internally reserved field. Do not use." "0,1,2,3,4,5,6,7" newline rbitfld.long 0x4 22.--23. "RSVDP_22,Reserved for future use." "0,1,2,3" newline hexmask.long.byte 0x4 16.--21. 1. "RXSTATUS_LANE,RXSTATUS_LANE is an internally reserved field. Do not use. Note: This register field is sticky." newline hexmask.long.word 0x4 0.--15. 1. "LPBK_RXVALID,LPBK_RXVALID is an internally reserved field. Do not use. Note: This register field is sticky." line.long 0x8 "MISC_CONTROL_1_OFF,DBI Read-Only Write Enable Register." hexmask.long.word 0x8 22.--31. 1. "RSVDP_22,Reserved for future use." newline bitfld.long 0x8 21. "P2P_ERR_RPT_CTRL,Determines whether to track completion of transmitted Non-Posted TLPs in P2P mode. - 0: Do not track completion - 1: Track completion Note: This register field is sticky." "Do not track completion,Track completion" newline bitfld.long 0x8 20. "P2P_TRACK_CPL_TO_REG,Determines whether to enable Peer to Peer (P2P) error reporting. - 0: Disable P2P error reporting - 1: Enable P2P error reporting Note: This register field is sticky." "Disable P2P error reporting,Enable P2P error reporting" newline bitfld.long 0x8 18.--19. "TARGET_ABOVE_CONFIG_LIMIT_REG,Configuration requests with an address greater than CONFIG_LIMIT_REG are directed to either ELBI or TRGT1 interface based on the setting of this field. This field can have the following values: - 1: ELBI - 2: TRGT1 Note:.." "?,ELBI,TRGT1,?" newline hexmask.long.word 0x8 8.--17. 1. "CONFIG_LIMIT_REG,Configuration requests are directed either to CDM or ELBI/RTRGT1 based on the value of this field. - Configuration requests with an address less CONFIG_LIMIT_REG are directed to the CDM - Configuration requests with an address greater.." newline bitfld.long 0x8 7. "CFG_TLP_BYPASS_EN_REG,Setting of this field defines which field TARGET_ABOVE_CONFIG_LIMIT_REG or CONFIG_LIMIT_REG decides the destination of Configuration requests. This field can have the following values: - 0: Configuration TLPs are routed according to.." "Configuration TLPs are routed according to the..,Configuration TLPs are routed according to the.." newline bitfld.long 0x8 6. "CPLQ_MNG_EN,This field enables the Completion Queue Management feature. Note: This register field is sticky." "0,1" newline bitfld.long 0x8 5. "ARI_DEVICE_NUMBER,When ARI is enabled this field enables use of the device ID. Note: This register field is sticky." "0,1" newline bitfld.long 0x8 4. "DISABLE_AUTO_LTR_CLR_MSG,Disable the autonomous generation of LTR clear message in upstream port. This field can have the following values: - 0: Allow the autonomous generation of LTR clear message. - 1: Disable the autonomous generation of LTR clear.." "Allow the autonomous generation of LTR clear..,Disable the autonomous generation of LTR clear.." newline bitfld.long 0x8 3. "SIMPLIFIED_REPLAY_TIMER,Enables Simplified Replay Timer (Gen4). For more details see 'Transmit Replay' in 'Transmit TLP Processing' section in the 'Controller Operations' chapter of the Databook. Simplified Replay Timer can have the following Values: -.." "0,1" newline bitfld.long 0x8 2. "UR_CA_MASK_4_TRGT1,When this field is set to '1' the controller suppresses error logging error message generation and CPL generation for non-posted requests TLPs (with UR filtering status) forwarded to your application (that is when DEFAULT_TARGET.." "0,1" newline bitfld.long 0x8 1. "DEFAULT_TARGET,Default target for an IO or MEM request with UR/CA/CRS received. Based on the value of this field the controller either drops or forwards these requests to your application. - 0: The controller drops all incoming I/O or MEM requests (after.." "The controller drops all incoming I/O or MEM..,The controller forwards all incoming I/O or MEM.." newline bitfld.long 0x8 0. "DBI_RO_WR_EN,Write to RO Registers Using DBI. Your application can write to some RO and HwInit register fields through the DBI when you set this field to '1'. For more details see 'Writing to Read-Only Registers' in 'Register Module LBC and DBI'.." "0,1" line.long 0xC "MULTI_LANE_CONTROL_OFF,UpConfigure Multi-lane Control Register. Used when upsizing or downsizing the link width through Configuration state without bringing the link down. For more details. see the 'Link Establishment' section in the 'Controller.." hexmask.long.tbyte 0xC 8.--31. 1. "RSVDP_8,Reserved for future use." newline bitfld.long 0xC 7. "UPCONFIGURE_SUPPORT,Upconfigure Support. The controller sends this value as the Link Upconfigure Capability in TS2 Ordered Sets in Configuration.Complete state. This field is reserved (fixed to '0') for M-PCIe. Note: This register field is sticky." "0,1" newline bitfld.long 0xC 6. "DIRECT_LINK_WIDTH_CHANGE,Directed Link Width Change. The controller always moves to Configuration state through Recovery state when this bit is set to '1'. - If the upconfigure_capable variable is '1' and the PCIE_CAP_HW_AUTO_WIDTH_DISABLE bit in.." "0,1" newline hexmask.long.byte 0xC 0.--5. 1. "TARGET_LINK_WIDTH,Target Link Width. Values correspond to: - 6'b000000: Controller does not start upconfigure or autonomous width downsizing in the Configuration state. - 6'b000001: x1 - 6'b000010: x2 - 6'b000100: x4 - 6'b001000: x8 - 6'b010000: x16 -.." line.long 0x10 "PHY_INTEROP_CTRL_OFF,PHY Interoperability Control Register." hexmask.long.tbyte 0x10 12.--31. 1. "RSVDP_12,Reserved for future use." newline bitfld.long 0x10 10. "L1_CLK_SEL,L1 Clock control bit. This field is reserved for internal use. You should not write to this field and change the default unless specifically instructed by Synopsys support. - 1: Controller does not request aux_clk switch and core_clk gating in.." "Controller requests aux_clk switch and core_clk..,Controller does not request aux_clk switch and.." newline rbitfld.long 0x10 9. "L1_NOWAIT_P1,L1 entry control bit. This field is reserved for internal use. You should not write to this field and change the default unless specifically instructed by Synopsys support. - 1: Controller does not wait for PHY to acknowledge transition to.." "Controller waits for the PHY to acknowledge..,Controller does not wait for PHY to acknowledge.." newline bitfld.long 0x10 8. "L1SUB_EXIT_MODE,L1 Exit Control Using phy_mac_pclkack_n. This field is reserved for internal use. You should not write to this field and change the default unless specifically instructed by Synopsys support. - 1: Controller exits L1 without waiting for.." "Controller waits for the PHY to assert..,Controller exits L1 without waiting for the PHY.." newline rbitfld.long 0x10 7. "RSVDP_7,Reserved for future use." "0,1" newline hexmask.long.byte 0x10 0.--6. 1. "RXSTANDBY_CONTROL,Rxstandby Control. Bits 0..5 determine if the controller asserts the RxStandby signal (mac_phy_rxstandby) in the indicated condition. Bit 6 enables the controller to perform the RxStandby/RxStandbyStatus handshake. This field is.." line.long 0x14 "TRGT_CPL_LUT_DELETE_ENTRY_OFF,TRGT_CPL_LUT Delete Entry Control register. Using this register you can delete one entry in the target completion LUT. You should only use this register when you know that your application will never send the completion.." bitfld.long 0x14 31. "DELETE_EN,This is a one-shot bit. A '1' write to this bit triggers the deletion of the target completion LUT entry that is specified in the LOOK_UP_ID field. This is a self-clearing register field. Reading from this register field always returns a '0'." "0,1" newline hexmask.long 0x14 0.--30. 1. "LOOK_UP_ID,This number selects one entry to delete of the TRGT_CPL_LUT." line.long 0x18 "LINK_FLUSH_CONTROL_OFF,Link Reset Request Flush Control Register." hexmask.long.byte 0x18 24.--31. 1. "RSVD_I_8,This is an internally reserved field. Do not use. Note: This register field is sticky." newline hexmask.long.tbyte 0x18 1.--23. 1. "RSVDP_1,Reserved for future use." newline bitfld.long 0x18 0. "AUTO_FLUSH_EN,Enables automatic flushing of pending requests before sending the reset request to the application logic to reset the PCIe controller and the AXI Bridge. The flushing process is initiated if any of the following events occur: - Hot reset.." "0,1" line.long 0x1C "AMBA_ERROR_RESPONSE_DEFAULT_OFF,AXI Bridge Slave Error Response Register." hexmask.long.word 0x1C 16.--31. 1. "RSVDP_16,Reserved for future use." newline hexmask.long.byte 0x1C 10.--15. 1. "AMBA_ERROR_RESPONSE_MAP,AXI Slave Response Error Map. Allows you to selectively map the errors received from the PCIe completion (for non-posted requests) to the AXI slave responses slv_rresp or slv_bresp. The recommended setting is SLVERR. CRS is.." newline hexmask.long.byte 0x1C 5.--9. 1. "RSVDP_5,Reserved for future use." newline bitfld.long 0x1C 3.--4. "AMBA_ERROR_RESPONSE_CRS,CRS Slave Error Response Mapping. Determines the AXI slave response for CRS completions. For more details see 'Error Handling' in the AXI chapter of the Databook. AHB: - always returns OKAY AXI: - 00: OKAY - 01: OKAY with all.." "OKAY,OKAY with all FFFF_FFFF data for all CRS..,?,?" newline bitfld.long 0x1C 2. "AMBA_ERROR_RESPONSE_VENDORID,Vendor ID Non-existent Slave Error Response Mapping. Determines the AXI slave response for errors on reads to non-existent Vendor ID register. For more details see 'Error Handling' in the AXI chapter of the Databook. AHB: -.." "OKAY,SLVERR/DECERR" newline rbitfld.long 0x1C 1. "RSVDP_1,Reserved for future use." "0,1" newline bitfld.long 0x1C 0. "AMBA_ERROR_RESPONSE_GLOBAL,Global Slave Error Response Mapping. Determines the AXI slave response for all error scenarios on non-posted requests. For more details see 'Error Handling' in the AXI chapter of the Databook. AHB: - 0: OKAY (with FFFF data for.." "OKAY,SLVERR/DECERR" line.long 0x20 "AMBA_LINK_TIMEOUT_OFF,Link Down AXI Bridge Slave Timeout Register. If your application AXI master issues outbound requests to the AXI bridge slave interface before the PCIe link is operational. the controller starts a 'flush' timer. The timeout value of.." hexmask.long.tbyte 0x20 9.--31. 1. "RSVDP_9,Reserved for future use." newline bitfld.long 0x20 8. "LINK_TIMEOUT_ENABLE_DEFAULT,Disable Flush. You can disable the flush feature by setting this field to '1'. Note: This register field is sticky." "0,1" newline hexmask.long.byte 0x20 0.--7. 1. "LINK_TIMEOUT_PERIOD_DEFAULT,Timeout Value (ms). The timer will timeout and then flush the bridge TX request queues after this amount of time. The timer counts when there are pending outbound AXI slave interface requests and the PCIe TX link is not.." line.long 0x24 "AMBA_ORDERING_CTRL_OFF,AMBA Ordering Control." hexmask.long.tbyte 0x24 8.--31. 1. "RSVDP_8,Reserved for future use." newline bitfld.long 0x24 7. "AX_MSTR_ZEROLREAD_FW,AXI Master Zero Length Read Forward to the application. The DW PCIe controller AXI bridge is able to terminate in order with the Posted transactions the zero length read implementing the PCIe express flush semantics of the Posted.." "The zero length Read is terminated at the DW..,The zero length Read is forward to the application" newline rbitfld.long 0x24 5.--6. "RSVDP_5,Reserved for future use." "0,1,2,3" newline bitfld.long 0x24 3.--4. "AX_MSTR_ORDR_P_EVENT_SEL,AXI Master Posted Ordering Event Selector. This field selects how the master interface determines when a P write is completed when enforcing the PCIe ordering rule 'NP must not pass P' at the AXI Master Interface. The AXI.." "B'last event: wait for the all of the write..,AW'last event: wait until the complete Posted..,This setting will not affect:,?" newline rbitfld.long 0x24 2. "RSVDP_2,Reserved for future use." "0,1" newline bitfld.long 0x24 1. "AX_SNP_EN,AXI Serialize Non-Posted Requests Enable. This field enables the AXI Bridge to serialize same ID Non-Posted Read/Write Requests on the wire. Serialization implies one outstanding same ID NP Read or Write on the wire and used to avoid AXI RAR.." "0,1" newline rbitfld.long 0x24 0. "RSVDP_0,Reserved for future use." "0,1" group.long (0x1E0+0x700)++0xB line.long 0x0 "COHERENCY_CONTROL_1_OFF,ACE Cache Coherency Control Register 1" hexmask.long 0x0 2.--31. 1. "CFG_MEMTYPE_BOUNDARY_LOW_ADDR,Boundary Lower Address For Memory Type. Bits [31:0] of dword-aligned address of the boundary for Memory type. The two lower address LSBs are '00'. Addresses up to but not including this value are in the lower address space.." newline rbitfld.long 0x0 1. "RSVDP_1,Reserved for future use." "0,1" newline bitfld.long 0x0 0. "CFG_MEMTYPE_VALUE,Sets the memory type for the lower and upper parts of the address space: - 0: lower = Peripheral; upper = Memory - 1: lower = Memory type; upper = Peripheral Note: This register field is sticky." "lower = Peripheral; upper = Memory,lower = Memory type; upper = Peripheral" line.long 0x4 "COHERENCY_CONTROL_2_OFF,ACE Cache Coherency Control Register 2" hexmask.long 0x4 0.--31. 1. "CFG_MEMTYPE_BOUNDARY_HIGH_ADDR,Boundary Upper Address For Memory Type. Bits [63:32] of the 64-bit dword-aligned address of the boundary for Memory type. Note: This register field is sticky." line.long 0x8 "COHERENCY_CONTROL_3_OFF,ACE Cache Coherency Control Register 3" hexmask.long.byte 0x8 27.--30. 1. "CFG_MSTR_AWCACHE_VALUE,Master Write CACHE Signal Value. Value of the individual bits in mstr_awcache when CFG_MSTR_AWCACHE_MODE is '1'. Note: not applicable to message requests; for message requests the value of mstr_awcache is always '0000' Note: This.." newline hexmask.long.byte 0x8 19.--22. 1. "CFG_MSTR_ARCACHE_VALUE,Master Read CACHE Signal Value. Value of the individual bits in mstr_arcache when CFG_MSTR_ARCACHE_MODE is '1'. Note: This register field is sticky." newline hexmask.long.byte 0x8 11.--14. 1. "CFG_MSTR_AWCACHE_MODE,Master Write CACHE Signal Behavior. Defines how the individual bits in mstr_awcache are controlled: - 0: set automatically by the AXI master - 1: set by the value of the corresponding bit of the CFG_MSTR_AWCACHE_VALUE field Note:.." newline hexmask.long.byte 0x8 3.--6. 1. "CFG_MSTR_ARCACHE_MODE,Master Read CACHE Signal Behavior. Defines how the individual bits in mstr_arcache are controlled: - 0: set automatically by the AXI master - 1: set by the value of the corresponding bit of the CFG_MSTR_ARCACHE_VALUE field Note:.." group.long (0x1F0+0x700)++0x7 line.long 0x0 "AXI_MSTR_MSG_ADDR_LOW_OFF,Lower 20 bits of the programmable AXI address where Messages coming from wire are mapped to. Bits [11:0] of the register are tied to zero for the address to be 4k-aligned. In previous releases. the third and fourth DWORDs of a.." hexmask.long.tbyte 0x0 12.--31. 1. "CFG_AXIMSTR_MSG_ADDR_LOW,Lower 20 bits of the programmable AXI address for Messages. Note: This register field is sticky." newline hexmask.long.word 0x0 0.--11. 1. "CFG_AXIMSTR_MSG_ADDR_LOW_RESERVED,Reserved for future use. Note: This register field is sticky." line.long 0x4 "AXI_MSTR_MSG_ADDR_HIGH_OFF,Upper 32 bits of the programmable AXI address where Messages coming from wire are mapped to." hexmask.long 0x4 0.--31. 1. "CFG_AXIMSTR_MSG_ADDR_HIGH,Upper 32 bits of the programmable AXI address for Messages. Note: This register field is sticky." rgroup.long (0x1F8+0x700)++0x7 line.long 0x0 "PCIE_VERSION_NUMBER_OFF,PCIe Controller IIP Release Version Number. The version number is given in hex format. You should convert each pair of hex characters to ASCII to interpret. Using 4.70a (GA) as an example: - VERSION_NUMBER = 0x3437302a which.." hexmask.long 0x0 0.--31. 1. "VERSION_NUMBER,Version Number." line.long 0x4 "PCIE_VERSION_TYPE_OFF,PCIe Controller IIP Release Version Type. The type is given in hex format. You should convert each pair of hex characters to ASCII to interpret. Using 4.70a (GA) as an example: - VERSION_NUMBER = 0x3437302a which translates to 470*.." hexmask.long 0x4 0.--31. 1. "VERSION_TYPE,Version Type." group.long (0x240+0x700)++0x7 line.long 0x0 "MSIX_ADDRESS_MATCH_LOW_OFF,MSI-X Address Match Low Register. When you enable the MSI-X Table RAM feature (MSIX_TABLE_EN=1). the controller implements the logic and RAM required to generate MSI-X requests. For more details. see the Interrupts section in.." hexmask.long 0x0 2.--31. 1. "MSIX_ADDRESS_MATCH_LOW,MSI-X Address Match Low Address. Note: This register field is sticky." newline rbitfld.long 0x0 1. "MSIX_ADDRESS_MATCH_RESERVED_1,Reserved. Note: This register field is sticky." "0,1" newline bitfld.long 0x0 0. "MSIX_ADDRESS_MATCH_EN,MSI-X Match Enable. Enable the MSI-X Address Match feature when the AXI bridge is present. Note: This register field is sticky." "0,1" line.long 0x4 "MSIX_ADDRESS_MATCH_HIGH_OFF,MSI-X Address Match High Register. When you enable the MSI-X Table RAM feature (MSIX_TABLE_EN=1). the controller implements the logic and RAM required to generate MSI-X requests. For more details. see the Interrupts section in.." hexmask.long 0x4 0.--31. 1. "MSIX_ADDRESS_MATCH_HIGH,MSI-X Address Match High Address. Note: This register field is sticky." wgroup.long (0x248+0x700)++0x3 line.long 0x0 "MSIX_DOORBELL_OFF,MSI-X Doorbell Register. When you enable the MSI-X Table RAM feature (MSIX_TABLE_EN=1). the controller implements the logic and RAM required to generate MSI-X requests. For more details. see the Interrupts section in the 'Controller.." bitfld.long 0x0 29.--31. "MSIX_DOORBELL_RESERVED_29_31,Reserved." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x0 24.--28. 1. "MSIX_DOORBELL_PF,MSIX Doorbell Physical Function. This register determines the Physical Function for the MSI-X transaction." newline hexmask.long.byte 0x0 16.--23. 1. "MSIX_DOORBELL_VF,MSIX Doorbell Virtual Function. This register determines the Virtual Function for the MSI-X transaction." newline bitfld.long 0x0 15. "MSIX_DOORBELL_VF_ACTIVE,MSIX Doorbell Virtual Function Active. This register determines whether a Virtual Function is used to generate the MSI-X transaction." "0,1" newline bitfld.long 0x0 12.--14. "MSIX_DOORBELL_TC,MSIX Doorbell Traffic Class. This register determines which traffic class to generate the MSI-X transaction with." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 11. "MSIX_DOORBELL_RESERVED_11,Reserved." "0,1" newline hexmask.long.word 0x0 0.--10. 1. "MSIX_DOORBELL_VECTOR,MSI-X Doorbell Vector. This register determines which vector to generate the MSI-X transaction for." group.long (0x24C+0x700)++0x3 line.long 0x0 "MSIX_RAM_CTRL_OFF,MSI-X RAM power mode and debug control register. When you enable the MSI-X Table RAM feature (MSIX_TABLE_EN=1). the controller implements the logic and RAM required to generate MSI-X requests. For more details. see the Interrupts.." hexmask.long.byte 0x0 26.--31. 1. "MSIX_RAM_CTRL_RESERVED_26_31,Reserved. Note: This register field is sticky." newline bitfld.long 0x0 25. "MSIX_RAM_CTRL_DBG_PBA,MSIX PBA RAM Debug Mode. Use this bit to activate the debug mode and allow direct read/write access to the PBA. Use can also use the dbg_pba input to activate debug mode. Debug mode turns off the PF/VF/Offset-based addressing into.." "0,1" newline bitfld.long 0x0 24. "MSIX_RAM_CTRL_DBG_TABLE,MSIX Table RAM Debug Mode. Use this bit to activate the debug mode and allow direct read/write access to the Table. Use can also use the dbg_table input to activate debug mode. Debug mode turns off the PF/VF/Offset-based.." "0,1" newline hexmask.long.byte 0x0 17.--23. 1. "MSIX_RAM_CTRL_RESERVED_17_23,Reserved. Note: This register field is sticky." newline bitfld.long 0x0 16. "MSIX_RAM_CTRL_BYPASS,MSIX RAM Control Bypass. The bypass field when set disables the internal generation of low power signals for both RAMs. It is up to the application to ensure the RAMs are in the proper power state before trying to access them." "0,1" newline hexmask.long.byte 0x0 10.--15. 1. "MSIX_RAM_CTRL_RESERVED_10_15,Reserved. Note: This register field is sticky." newline bitfld.long 0x0 9. "MSIX_RAM_CTRL_PBA_SD,MSIX PBA RAM Shut Down. Set this bit to drive the cfg_msix_pba_sd output to signal your external logic to place the MSIX PBA RAM in Shut Down low-power mode. Note: This register field is sticky." "0,1" newline bitfld.long 0x0 8. "MSIX_RAM_CTRL_PBA_DS,MSIX PBA RAM Deep Sleep. Set this bit to drive the cfg_msix_pba_ds output to signal your external logic to place the MSIX PBA RAM in Deep Sleep low-power mode. Note: This register field is sticky." "0,1" newline hexmask.long.byte 0x0 2.--7. 1. "MSIX_RAM_CTRL_RESERVED_2_7,Reserved. Note: This register field is sticky." newline bitfld.long 0x0 1. "MSIX_RAM_CTRL_TABLE_SD,MSIX Table RAM Shut Down. Set this bit to drive the cfg_msix_table_sd output to signal your external logic to place the MSIX Table RAM in Shut Down low-power mode. Note: This register field is sticky." "0,1" newline bitfld.long 0x0 0. "MSIX_RAM_CTRL_TABLE_DS,MSIX Table RAM Deep Sleep. Set this bit to drive the cfg_msix_table_ds output to signal your external logic to place the MSIX Table RAM in Deep Sleep low-power mode. Note: This register field is sticky." "0,1" group.long (0x430+0x700)++0x3 line.long 0x0 "PL_LTR_LATENCY_OFF,LTR Latency Register. The function of this register field (and all other fields in this register) differs between an upstream port and a downstream port. For an upstream port. the register fields capture the corresponding fields in the.." bitfld.long 0x0 31. "NO_SNOOP_LATENCY_REQUIRE,No Snoop Latency Requirement. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" "0,1" newline rbitfld.long 0x0 29.--30. "RSVDP_29,Reserved for future use." "0,1,2,3" newline bitfld.long 0x0 26.--28. "NO_SNOOP_LATENCY_SCALE,No Snoop Latency Scale. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" "0,1,2,3,4,5,6,7" newline hexmask.long.word 0x0 16.--25. 1. "NO_SNOOP_LATENCY_VALUE,No Snoop Latency Value. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" newline bitfld.long 0x0 15. "SNOOP_LATENCY_REQUIRE,Snoop Latency Requirement. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" "0,1" newline rbitfld.long 0x0 13.--14. "RSVDP_13,Reserved for future use." "0,1,2,3" newline bitfld.long 0x0 10.--12. "SNOOP_LATENCY_SCALE,Snoop Latency Scale. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" "0,1,2,3,4,5,6,7" newline hexmask.long.word 0x0 0.--9. 1. "SNOOP_LATENCY_VALUE,Snoop Latency Value. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" group.long (0x440+0x700)++0xB line.long 0x0 "AUX_CLK_FREQ_OFF,Auxiliary Clock Frequency Control Register." hexmask.long.tbyte 0x0 10.--31. 1. "RSVDP_10,Reserved for future use." newline hexmask.long.word 0x0 0.--9. 1. "AUX_CLK_FREQ,The aux_clk frequency in MHz. This value is used to provide a 1 us reference for counting time during low-power states with aux_clk when the PHY has removed the pipe_clk. Frequencies lower than 1 MHz are possible but with a loss of accuracy.." line.long 0x4 "L1_SUBSTATES_OFF,L1 Substates Timing Register." hexmask.long.tbyte 0x4 9.--31. 1. "RSVDP_9,Reserved for future use." newline bitfld.long 0x4 8. "L1SUB_LOW_POWER_CLOCK_SWITCH_MODE,If this bit is set to 1'b1 the reference clock will be running regardless of the CLKREQ# setting. If this bit is set to 1'b0 the reference clock may be gated off when CLKREQ# is de-asserted. If the bit is set to 1'b1 the.." "0,1" newline bitfld.long 0x4 6.--7. "L1SUB_T_PCLKACK,Max delay (in 1us units) between a MAC request to remove the clock on mac_phy_pclkreq_n and a PHY response on phy_mac_pclkack_n. If the PHY does not respond within this time the request is aborted.The actual timeout value will be.." "0,1,2,3" newline hexmask.long.byte 0x4 2.--5. 1. "L1SUB_T_L1_2,Duration (in 1us units) of L1.2. The actual timeout value will be L1SUB_T_L1_2 + 1. Range is 0.15. Note: This register field is sticky." newline bitfld.long 0x4 0.--1. "L1SUB_T_POWER_OFF,Duration (in 1us units) of L1.2.Entry. The actual timeout value will be L1SUB_T_POWER_OFF + 1. Range is 0.3. Note: This register field is sticky." "0,1,2,3" line.long 0x8 "POWERDOWN_CTRL_STATUS_OFF,Powerdown Control and Status Register." hexmask.long.tbyte 0x8 12.--31. 1. "RSVDP_12,Reserved for future use." newline hexmask.long.byte 0x8 8.--11. 1. "POWERDOWN_PHY_POWERDOWN,This field represents the Powerdown value that has been acknowledged by the PHY. It is updated with the value of Powerdown driven by the controller when the PHY has returned the Phystatus acknowledgment for the Powerdown.." newline hexmask.long.byte 0x8 4.--7. 1. "POWERDOWN_MAC_POWERDOWN,This field represents the Powerdown value driven by the controller to the PHY." newline rbitfld.long 0x8 1.--3. "RSVDP_1,Reserved for future use." "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 0. "POWERDOWN_FORCE,This field is a one shot field. Writing a value of 1 to this field causes the controller to complete the P2 Powerdown handshake regardless of whether the PHY has returned Phystatus. This field could be used for debug purposes in event.." "0,1" group.long (0x470+0x700)++0x7 line.long 0x0 "PHY_VIEWPORT_CTLSTS_OFF,PHY Register Viewport Control and Status Register." rbitfld.long 0x0 31. "PHY_VIEWPORT_PENDING,PHY viewport pending. Indicates the access is pending. - 1 : Pending - 0 : Idle This bit is set to 1 when the read/write access has been initiated. This bit is cleared when the access is completed. If phy_reg_clk_g is never activated.." "Idle,Pending" newline rbitfld.long 0x0 30. "PHY_VIEWPORT_STATUS,PHY viewport status. Indicates the status of the latest access. - 1 : Timeout - 0 : No errors If the timeout is detected this bit is set to 1 and PHY_VIEWPORT_PENDING is cleared. This bit is cleared when the read/write access is.." "No errors,Timeout" newline hexmask.long.byte 0x0 23.--29. 1. "RSVDP_23,Reserved for future use." newline bitfld.long 0x0 22. "PHY_VIEWPORT_TIMEOUT_DISABLE,PHY viewport timeout disable. Disables the PHY register access timeout structure. When the timeout is disabled you must ensure that the PHY register accesses are always acknowledged by cr_para_ack. Otherwise.." "0,1" newline bitfld.long 0x0 21. "PHY_VIEWPORT_BCWR,Broadcast write access to all xN sub-blocks. If you need to broadcast the write accesses into all lanes both PHY_VIEWPORT_ADDR[15] and this bit should be 1. Note: This register field is sticky." "0,1" newline bitfld.long 0x0 20. "PHY_VIEWPORT_READ,PHY viewport read. If set a read access is initiated. The value is always 0 when this bit is read. Note: This register field is sticky." "0,1" newline hexmask.long.byte 0x0 16.--19. 1. "PHY_VIEWPORT_NUM,PHY viewport xN sub-block number. Selects one of xN sub-blocks. This register is not used when the write access is initiated with PHY_VIEWPORT_BCWR==1. Note: This register field is sticky." newline hexmask.long.word 0x0 0.--15. 1. "PHY_VIEWPORT_ADDR,PHY viewport address. Indicates the PHY's register address. Please refer to the PHY databook for the address map definition. Note: This register field is sticky." line.long 0x4 "PHY_VIEWPORT_DATA_OFF,PHY Register Viewport Data Register." hexmask.long.word 0x4 16.--31. 1. "RSVDP_16,Reserved for future use." newline hexmask.long.word 0x4 0.--15. 1. "PHY_VIEWPORT_DATA,PHY viewport data. A write access to this register initiates the PHY register write access. By a read access to this register this field returns the latest read data from the PHY register. Note: This register field is sticky." group.long (0x490+0x700)++0x3 line.long 0x0 "PIPE_RELATED_OFF,PIPE Related Register. This register controls the pipe's capabitity. control. and status parameters." hexmask.long.tbyte 0x0 9.--31. 1. "RSVDP_9,Reserved for future use." newline bitfld.long 0x0 8. "PIPE_GARBAGE_DATA_MODE,PIPE Garbage Data Mode. - 0: PIPE Spec compliant mode: The MAC discards any symbols received after the electrical idle ordered-set until RxValid is deasserted. - 1: Special PHY Support mode: The MAC discards any symbols received.." "PIPE Spec compliant mode: The MAC discards any..,Special PHY Support mode: The MAC discards any.." tree.end tree.end tree "PCIE1_NCR" base ad:0x310E0000 group.long 0x0++0x7 line.long 0x0 "INTR_0,INTR_0" bitfld.long 0x0 31. "INTR_PM_XTLH_BLOCK_TLP,Indicates that your application must stop generating new outgoing request TLPs due to the current power management state. Your application can continue to generate completion TLPs." "0,1" newline bitfld.long 0x0 30. "INTR_LINK_REQ_RST_NOT,Reset request because the link has gone down or the controller received a hot-reset request. A low level indicates that the controller is requesting external logic to reset the controller because the PHY link is down. When the AXI.." "0,1" newline bitfld.long 0x0 29. "INTR_SMLH_REQ_RST_NOT,Early version of the link_req_rst_not signal." "0,1" newline bitfld.long 0x0 28. "INTR_SMLH_LINK_UP,PHY Link up/down indicator: 1: Link is up 0: Link is down" "Link is down,Link is up" newline bitfld.long 0x0 27. "INTR_RDLH_LINK_UP,Data link layer up/down indicator: This status from the flow control initialization state machine indicates that flow control has been initiated and the Data link layer is ready to transmit and receive packets. For multi-VC designs.." "Link is down,Link is up" newline bitfld.long 0x0 26. "INTR_VEN_MSI_GRANT,One-cycle pulse that indicates that the controller has accepted the request to send an MSI. After asserting ven_msi_grant for one cycle the controller does not wait for ven_msi_req to be de-asserted then reasserted to generate another.." "0,1" newline bitfld.long 0x0 25. "INTR_VEN_MSG_GRANT,One-cycle pulse that indicates that the controller has accepted the request to send the vendor-defined Message." "0,1" newline bitfld.long 0x0 23.--24. "INTR_CFG_UP_DRS_TO_FRS,DRS to FRS Pulse. The DSP controller asserts the cfg_up_drs_to_frs output and sends an FRS message with the reason code set to 'DRS Message Received' when: It receives a DRS message and PCIE_CAP_DRS_SIGNALING_CONTROL in.." "0,1,2,3" newline bitfld.long 0x0 21.--22. "INTR_CFG_DRS_MSI,DRS Message Received Interrupt Pulse. The DSP controller asserts the cfg_drs_msi output when all of the following are true: It receives a DRS message PCIE_CAP_DRS_SIGNALING_CONTROL in LINK_CONTROL_LINK_STATUS_REG is 2'b01 MSI or MSI-X is.." "0,1,2,3" newline bitfld.long 0x0 19.--20. "INTR_FRSQ_MSI,FRSQ Interrupt Pulse. The RC asserts this output when it receives an FRQ message or when the FRS queue overflows." "0,1,2,3" newline bitfld.long 0x0 17.--18. "INTR_CFG_PME_MSI,The controller asserts cfg_pme_msi (as a one-cycle pulse) when all of the following conditions are true: MSI or MSI-X is enabled. The PME Interrupt Enable bit in the Root Control register is set to 1. The PME Status bit in the Root.." "0,1,2,3" newline bitfld.long 0x0 15.--16. "INTR_HP_MSI,INTR_HP_MSI" "0,1,2,3" newline bitfld.long 0x0 14. "INTR_CFG_LINK_AUTO_BW_MSI,The controller sets this pin when following conditions are true: MSI or MSI-X is enabled. The Link Autonomous Bandwidth Status register (Link Status register bit 15) is updated. The Link Autonomous Bandwidth Interrupt Enable.." "0,1" newline bitfld.long 0x0 13. "INTR_CFG_BW_MGT_MSI,The controller sets this pin when following conditions are true: MSI or MSI-X is enabled. The Link Bandwidth Management Status register (Link Control Status register bit 14) is updated The Link Bandwidth Management Interrupt Enable.." "0,1" newline bitfld.long 0x0 11.--12. "INTR_HP_PME,The controller asserts hp_pme when all of the following conditions are true: The PME Enable bit in the Power Management Control and Status" "0,1,2,3" newline bitfld.long 0x0 10. "INTR_PTM_CLOCK_UPDATED,Indicates that the controller has updated the Local Clock." "0,1" newline bitfld.long 0x0 9. "INTR_PTM_REQ_DUP_RX,PTM Requester Duplicate Received. Single-cycle pulse indicating PTM Requester received a duplicate TLP while PTM Requester is in the process of updating PTM local clock or Following calculation of the update when the PTM context is.." "0,1" newline bitfld.long 0x0 8. "INTR_PTM_REQ_REPLAY_TX,PTM Requester Replay Sent. Single-cycle pulse indicating PTM Requester detected a TLP replay being sent when ResponseD messages are in use while PTM Requester is in the process of updating PTM local clock or Following calculation.." "0,1" newline bitfld.long 0x0 7. "INTR_RADM_MSG_LTR,One-clock-cycle pulse that indicates that the controller received an LTR message. The controller makes the message header available the radm_msg_payload output. It is also available the app_ltr_latency output. When RX_TLP > 1 and when.." "0,1" newline bitfld.long 0x0 6. "INTR_RADM_MSG_UNLOCK,One-cycle pulse that indicates that the controller received an Unlock message. When RX_TLP > 1 and when two messages of the same type are received in the same clock cycle (back-to-back) then no separate indication is given for the.." "0,1" newline bitfld.long 0x0 5. "INTR_RADM_PM_PME,One-clock-cycle pulse that indicates that the controller received a PM_PME message." "0,1" newline bitfld.long 0x0 4. "INTR_RADM_PM_TO_ACK,One-clock-cycle pulse that indicates that the controller received a PME_TO_Ack message. Upstream port: Reserved." "0,1" newline bitfld.long 0x0 3. "INTR_RADM_PM_TURNOFF,One-clock-cycle pulse that indicates that the controller received a PME Turnoff message. When RX_TLP > 1 and when two messages of the same type are received in the same clock cycle (back-to-back) then no indication is given for the.." "0,1" newline bitfld.long 0x0 2. "INTR_RADM_VENDOR_MSG,One-cycle pulse that indicates the controller received a vendor-defined message. The controller makes the message header available the radm_msg_payload output. When FX_TLP > 1 and when two messages of the same type are received in.." "0,1" newline bitfld.long 0x0 1. "INTR_PERSTN,INTR_PERSTN This interrupt status bit indicates PERST# pad input fall edge detected." "0,1" newline bitfld.long 0x0 0. "INTR_WAKEN,INTR_WAKEN This interrupt status bit indicates WAKE# pad input fall edge detected." "0,1" line.long 0x4 "INTR_1,INTR_1" bitfld.long 0x4 31. "INTR_TRGT_CPL_TIMEOUT,Indicates that the application has not generated a completion for an incoming request within the required time interval. Information about the timed out completion is available the trgt_timeout_* outputs listed later.When a.." "0,1" newline bitfld.long 0x4 30. "INTR_RADM_CPL_TIMEOUT,Indicates that the completion TLP for a request has not been received within the expected time window." "0,1" newline hexmask.long.byte 0x4 26.--29. 1. "INTR_INT_D_A,INTR_INT_D_A These Interrupt status bit indicates wheter Legacy A~D transmitted or received by controller. bit 29 : INT_D .. bit26 : INT_A" newline bitfld.long 0x4 24.--25. "INTR_CFG_SEND_F_ERR,Sent Fatal Error. Controller has sent a message towards the Root Complex indicating that an Rx TLP that contained a fatal error and that can not be corrected was received by the EndPoint" "0,1,2,3" newline bitfld.long 0x4 22.--23. "INTR_CFG_SEND_NF_ERR,Sent Non-Fatal Error. Controller has sent a message towards the Root Complex indicating that an Rx TLP that contained an non-fatal error and that can not be corrected was received by the EndPoint" "0,1,2,3" newline bitfld.long 0x4 20.--21. "INTR_CFG_SEND_COR_ERR,Sent Correctable Error. Core has sent a message towards the Root Complex indicating that an Rx TLP that contained an error and that can be corrected was received by the EndPoint" "0,1,2,3" newline bitfld.long 0x4 18.--19. "INTR_CFG_FLR_PF_ACTIVE,Set when the software initiates FLR a physical function by writing to the 'Initiate FLR' register bit of that function. This signal is held asserted until reset of both the application and controller logic has been completed." "0,1,2,3" newline bitfld.long 0x4 16.--17. "INTR_PF_FRS_GRANT,Indicator of when an FRS message for this function has been scheduled for transmission." "0,1,2,3" newline hexmask.long.byte 0x4 8.--15. 1. "INTR_CFG_FLR_VF_ACTIVE,Set when the software initiates FLR a virtual function by writing to the 'Initiate FLR' register bit of that function. This signal is held asserted until the reset of both the application and internal controller logic has been.." newline hexmask.long.byte 0x4 0.--7. 1. "INTR_VF_FRS_GRANT,Indicator of when an FRS message for this VF has been scheduled for transmission." repeat 10. (list 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB )(list 0x0 0x4 0x8 0xC 0x10 0x14 0x18 0x1C 0x20 0x24 ) group.long ($2+0x8)++0x3 line.long 0x0 "INTR_$1,INTR_2" hexmask.long 0x0 0.--31. 1. "INTR_MSI_PF0,INTR_MSI_PF0" repeat.end group.long 0x30++0xB line.long 0x0 "INTR_12,INTR_12" newline hexmask.long.byte 0x0 16.--23. 1. "INTR_RADM_TRGT1_ATU_CBUF_ERR,INTR_RADM_TRGT1_ATU_CBUF_ERR" newline hexmask.long.byte 0x0 8.--15. 1. "INTR_RADM_TRGT1_ATU_SLOC_MATCH,INTR_RADM_TRGT1_ATU_SLOC_MATCH" newline bitfld.long 0x0 7. "INTR_RADM_CORRECTABLE_ERR,INTR_RADM_CORRECTABLE_ERR" "0,1" newline bitfld.long 0x0 6. "INTR_RADM_NONFATAL_ERR,INTR_RADM_NONFATAL_ERR" "0,1" newline bitfld.long 0x0 5. "INTR_RADM_FATAL_ERR,INTR_RADM_FATAL_ERR" "0,1" newline bitfld.long 0x0 3.--4. "INTR_CFG_AER_RC_ERR_MSI,INTR_CFG_AER_RC_ERR_MSI" "0,1,2,3" newline bitfld.long 0x0 1.--2. "INTR_CFG_SYS_ERR_RC,INTR_CFG_SYS_ERR_RC" "0,1,2,3" newline bitfld.long 0x0 0. "INTR_MSTR_AWMISC_INFO_EP,INTR_MSTR_AWMISC_INFO_EP" "0,1" line.long 0x4 "INTEN_0,INTEN_0" bitfld.long 0x4 31. "INTEN_PM_XTLH_BLOCK_TLP,Indicates that your application must stop generating new outgoing request TLPs due to the current power management state. Your application can continue to generate completion TLPs.This output is not used in RC mode." "0,1" newline bitfld.long 0x4 30. "INTEN_LINK_REQ_RST_NOT,Reset request because the link has gone down or the controller received a hot-reset request. A low level indicates that the controller is requesting external logic to reset the controller because the PHY link is down. When the AXI.." "0,1" newline bitfld.long 0x4 29. "INTEN_SMLH_REQ_RST_NOT,Early version of the link_req_rst_not signal." "0,1" newline bitfld.long 0x4 28. "INTEN_SMLH_LINK_UP,PHY Link up/down indicator: 1: Link is up 0: Link is down" "Link is down,Link is up" newline bitfld.long 0x4 27. "INTEN_RDLH_LINK_UP,Data link layer up/down indicator: This status from the flow control initialization state machine indicates that flow control has been initiated and the Data link layer is ready to transmit and receive packets. For multi-VC designs.." "Link is down,Link is up" newline bitfld.long 0x4 26. "INTEN_VEN_MSI_GRANT,One-cycle pulse that indicates that the controller has accepted the request to send an MSI. After asserting ven_msi_grant for one cycle the controller does not wait for ven_msi_req to be de-asserted then reasserted to generate another.." "0,1" newline bitfld.long 0x4 25. "INTEN_VEN_MSG_GRANT,One-cycle pulse that indicates that the controller has accepted the request to send the vendor-defined Message." "0,1" newline bitfld.long 0x4 23.--24. "INTEN_CFG_UP_DRS_TO_FRS,DRS to FRS Pulse. The DSP controller asserts the cfg_up_drs_to_frs output and sends an FRS message with the reason code set to 'DRS Message Received' when: It receives a DRS message and PCIE_CAP_DRS_SIGNALING_CONTROL in.." "0,1,2,3" newline bitfld.long 0x4 21.--22. "INTEN_CFG_DRS_MSI,DRS Message Received Interrupt Pulse. The DSP controller asserts the cfg_drs_msi output when all of the following are true: It receives a DRS message PCIE_CAP_DRS_SIGNALING_CONTROL in LINK_CONTROL_LINK_STATUS_REG is 2'b01 MSI or MSI-X.." "0,1,2,3" newline bitfld.long 0x4 19.--20. "INTEN_FRSQ_MSI,FRSQ Interrupt Pulse. The RC asserts this output when it receives an FRQ message or when the FRS queue overflows." "0,1,2,3" newline bitfld.long 0x4 17.--18. "INTEN_CFG_PME_MSI,The controller asserts cfg_pme_msi (as a one-cycle pulse) when all of the following conditions are true: MSI or MSI-X is enabled. The PME Interrupt Enable bit in the Root Control register is set to 1. The PME Status bit in the Root.." "0,1,2,3" newline bitfld.long 0x4 15.--16. "INTEN_HP_MSI,The controller asserts hp_msi (as a one-cycle pulse) when the logical AND of the following conditions transitions from false to true: MSI or MSI-X is enabled. Hot-Plug interrupts are enabled in the Slot Control register. Any bit in the Slot.." "0,1,2,3" newline bitfld.long 0x4 14. "INTEN_CFG_LINK_AUTO_BW_MSI,The controller sets this pin when following conditions are true: MSI or MSI-X is enabled. The Link Autonomous Bandwidth Status register (Link Status register bit 15) is updated. The Link Autonomous Bandwidth Interrupt Enable.." "0,1" newline bitfld.long 0x4 13. "INTEN_CFG_BW_MGT_MSI,The controller sets this pin when following conditions are true: MSI or MSI-X is enabled. The Link Bandwidth Management Status register (Link Control Status register bit 14) is updated The Link Bandwidth Management Interrupt Enable.." "0,1" newline bitfld.long 0x4 11.--12. "INTEN_HP_PME,The controller asserts hp_pme when all of the following conditions are true: The PME Enable bit in the Power Management Control and Status register is set to 1. Any bit in the Slot Status register transitions from 0 to 1 and the associated.." "0,1,2,3" newline bitfld.long 0x4 10. "INTEN_PTM_CLOCK_UPDATED,Indicates that the controller has updated the Local Clock." "0,1" newline bitfld.long 0x4 9. "INTEN_PTM_REQ_DUP_RX,PTM Requester Duplicate Received. Single-cycle pulse indicating PTM Requester received a duplicate TLP while PTM Requester is in the process of updating PTM local clock or Following calculation of the update when the PTM context.." "0,1" newline bitfld.long 0x4 8. "INTEN_PTM_REQ_REPLAY_TX,PTM Requester Replay Sent. Single-cycle pulse indicating PTM Requester detected a TLP replay being sent when ResponseD messages are in use while PTM Requester is in the process of updating PTM local clock or Following.." "0,1" newline bitfld.long 0x4 7. "INTEN_RADM_MSG_LTR,One-clock-cycle pulse that indicates that the controller received an LTR message. The controller makes the message header available the radm_msg_payload output. It is also available the app_ltr_latency output. When RX_TLP > 1 and when.." "0,1" newline bitfld.long 0x4 6. "INTEN_RADM_MSG_UNLOCK,One-cycle pulse that indicates that the controller received an Unlock message. When RX_TLP > 1 and when two messages of the same type are received in the same clock cycle (back-to-back) then no separate indication is given for the.." "0,1" newline bitfld.long 0x4 5. "INTEN_RADM_PM_PME,One-clock-cycle pulse that indicates that the controller received a PM_PME message." "0,1" newline bitfld.long 0x4 4. "INTEN_RADM_PM_TO_ACK,One-clock-cycle pulse that indicates that the controller received a PME_TO_Ack message. Upstream port: Reserved." "0,1" newline bitfld.long 0x4 3. "INTEN_RADM_PM_TURNOFF,One-clock-cycle pulse that indicates that the controller received a PME Turnoff message. When RX_TLP > 1 and when two messages of the same type are received in the same clock cycle (back-to-back) then no indication is given for the.." "0,1" newline bitfld.long 0x4 2. "INTEN_RADM_VENDOR_MSG,One-cycle pulse that indicates the controller received a vendor-defined message. The controller makes the message header available the radm_msg_payload output. When FX_TLP > 1 and when two messages of the same type are received in.." "0,1" newline bitfld.long 0x4 1. "INTEN_PERSTN,INTEN_PERSTN Interrupt Enable bit for INTR_PERSTN." "0,1" newline bitfld.long 0x4 0. "INTEN_WAKEN,INTEN_WAKEN Interrupt Enable bit for INTR_WAKEN." "0,1" line.long 0x8 "INTEN_1,INTEN_1" bitfld.long 0x8 31. "INTEN_TRGT_CPL_TIMEOUT,Indicates that the application has not generated a completion for an incoming request within the required time interval. Information about the timed out completion is available the trgt_timeout_* outputs listed later.When a.." "0,1" newline bitfld.long 0x8 30. "INTEN_RADM_CPL_TIMEOUT,Indicates that the completion TLP for a request has not been received within the expected time window." "0,1" newline hexmask.long.byte 0x8 26.--29. 1. "INTEN_INT_D_A,INTEN_INT_D_A Interrupt Enable bit for INTR_D_A. Bit 29 : INT_D ... Bit26 : INT_A." newline bitfld.long 0x8 24.--25. "INTEN_CFG_SEND_F_ERR,Sent Fatal Error. Controller has sent a message towards the Root Complex indicating that an Rx TLP that contained a fatal error and that can not be corrected was received by the EndPoint" "0,1,2,3" newline bitfld.long 0x8 22.--23. "INTEN_CFG_SEND_NF_ERR,Sent Non-Fatal Error. Controller has sent a message towards the Root Complex indicating that an Rx TLP that contained an non-fatal error and that can not be corrected was received by the EndPoint" "0,1,2,3" newline bitfld.long 0x8 20.--21. "INTEN_CFG_SEND_COR_ERR,Sent Correctable Error. Core has sent a message towards the Root Complex indicating that an Rx TLP that contained an error and that can be corrected was received by the EndPoint" "0,1,2,3" newline bitfld.long 0x8 18.--19. "INTEN_CFG_FLR_PF_ACTIVE,Set when the software initiates FLR a physical function by writing to the 'Initiate FLR' register bit of that function. This signal is held asserted until reset of both the application and controller logic has been completed." "0,1,2,3" newline bitfld.long 0x8 16.--17. "INTEN_PF_FRS_GRANT,Indicator of when an FRS message for this function has been scheduled for transmission." "0,1,2,3" newline hexmask.long.byte 0x8 8.--15. 1. "INTEN_CFG_FLR_VF_ACTIVE,Set when the software initiates FLR a virtual function by writing to the 'Initiate FLR' register bit of that function. This signal is held asserted until the reset of both the application and internal controller logic has been.." newline hexmask.long.byte 0x8 0.--7. 1. "INTEN_VF_FRS_GRANT,Indicator of when an FRS message for this VF has been scheduled for transmission." repeat 10. (list 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB )(list 0x0 0x4 0x8 0xC 0x10 0x14 0x18 0x1C 0x20 0x24 ) group.long ($2+0x3C)++0x3 line.long 0x0 "INTEN_$1,INTEN_2" hexmask.long 0x0 0.--31. 1. "INTEN_MSI_PF0,INTEN_MSI_PF0" repeat.end group.long 0x64++0x13 line.long 0x0 "INTEN_12,INTEN_12" newline hexmask.long.byte 0x0 16.--23. 1. "INTEN_RADM_TRGT1_ATU_CBUF_ERR,INTEN_RADM_TRGT1_ATU_CBUF_ERR" newline hexmask.long.byte 0x0 8.--15. 1. "INTEN_RADM_TRGT1_ATU_SLOC_MATCH,INTEN_RADM_TRGT1_ATU_SLOC_MATCH" newline bitfld.long 0x0 7. "INTEN_RADM_CORRECTABLE_ERR,INTEN_RADM_CORRECTABLE_ERR" "0,1" newline bitfld.long 0x0 6. "INTEN_RADM_NONFATAL_ERR,INTEN_RADM_NONFATAL_ERR" "0,1" newline bitfld.long 0x0 5. "INTEN_RADM_FATAL_ERR,INTEN_RADM_FATAL_ERR" "0,1" newline bitfld.long 0x0 3.--4. "INTEN_CFG_AER_RC_ERR_MSI,INTEN_CFG_AER_RC_ERR_MSI" "0,1,2,3" newline bitfld.long 0x0 1.--2. "INTEN_CFG_SYS_ERR_RC,INTEN_CFG_SYS_ERR_RC" "0,1,2,3" newline bitfld.long 0x0 0. "INTEN_MSTR_AWMISC_INFO_EP,INTEN_MSTR_AWMISC_INFO_EP" "0,1" line.long 0x4 "CTRL_0,CTRL_0" bitfld.long 0x4 31. "APP_FLR_VF_DONE_7,Indicates that FLR a virtual function has been completed which means the application has completed initializing its data structures for the function and there are no more TLPs associated with this function in the application's transmit.." "0,1" newline bitfld.long 0x4 30. "APP_FLR_VF_DONE_6,Similar to above." "0,1" newline bitfld.long 0x4 29. "APP_FLR_VF_DONE_5,Similar to above." "0,1" newline bitfld.long 0x4 28. "APP_FLR_VF_DONE_4,Similar to above." "0,1" newline bitfld.long 0x4 27. "APP_FLR_VF_DONE_3,Similar to above." "0,1" newline bitfld.long 0x4 26. "APP_FLR_VF_DONE_2,Similar to above." "0,1" newline bitfld.long 0x4 25. "APP_FLR_VF_DONE_1,Similar to above." "0,1" newline bitfld.long 0x4 24. "APP_FLR_VF_DONE_0,Similar to above." "0,1" newline bitfld.long 0x4 23. "APP_FLR_PF_DONE_1,Indicates that FLR a physical function has been completed which means the application has completed initializing its data structures for the function and there are no more TLPs associated with this function in the application's.." "0,1" newline bitfld.long 0x4 22. "APP_FLR_PF_DONE_0,Similar to above." "0,1" newline bitfld.long 0x4 21. "OUTBAND_PWRUP_CMD_1,Wake Up. If PME is enabled and PME support is configured for current PMCSR D-state asserting this signal causes the controller to wake from either L1 or L2 state. When the controller has transitioned back to the L0 state it transmits.." "0,1" newline bitfld.long 0x4 20. "OUTBAND_PWRUP_CMD_0,Similar to above." "0,1" newline bitfld.long 0x4 19. "APP_REQ_EXIT_L1,Application request to Exit L1. Request from your application to exit L1.It is only effective when L1 is enabled." "0,1" newline bitfld.long 0x4 18. "APP_REQ_ENTR_L1,Application request to Enter L1 ASPM state. The app_req_entr_l1 signal is for use by applications that need to control L1 entry instead of using the L1 entry timer as defined in the PCI Express Specification. It is only effective when L1.." "0,1" newline bitfld.long 0x4 17. "APP_UNLOCK_MSG,Request from your application to generate an Unlock message. You must assert this signal for one clock cycle. The controller does not return an acknowledgment or grant signal. You must not pulse the same signal again until the previous.." "0,1" newline bitfld.long 0x4 16. "APP_PM_XMT_PME_1,Wake Up. If PME is enabled and PME support is configured for current PMCSR D-state asserting this signal causes the controller to wake from either L1 or L2 state. When the controller has transitioned back to the L0 state it transmits a.." "0,1" newline bitfld.long 0x4 15. "APP_PM_XMT_PME_0,Similar to above." "0,1" newline bitfld.long 0x4 14. "APP_PM_XMT_TURNOFF,Request from your application to generate a PM_Turn_Off message.You must assert this signal for one clock cycle. The controller does not return an acknowledgment or grant signal. You must not pulse the same signal again until the.." "0,1" newline bitfld.long 0x4 13. "APP_INIT_RST,Request from your application to send a hot reset to the upstream port.The hot reset request is sent when a single cycle pulse is applied to this pin. In an upstream port you should set this input to '0'." "0,1" newline bitfld.long 0x4 12. "APP_HDR_VALID,One-clock-cycle pulse indicating that the data app_hdr_log app_err_bus app_err_func_num and app_tlp_prfx_log is valid." "0,1" newline bitfld.long 0x4 11. "APP_L1SUB_DISABLE,The application can set this input to 1'b1 to prevent entry to L1 Sub-states. This pin is used to gate the L1 sub-state enable bits from the L1 PM Substates Control 1 Register." "0,1" newline bitfld.long 0x4 10. "APP_CLK_PM_EN,Clock PM feature enabled by application. Used to inhibit the programming of the Clock PM in Link Control Register. For more details see 'L1 with Clock PM (L1 with REFCLK removal/PLL Off)'." "0,1" newline bitfld.long 0x4 9. "APP_XFER_PENDING,Indicates that your application has transfers pending and prevents the controller from entering L1. If the entry into L1 is already in progress assertion of app_xfer_pending causes an exit from L1. This is a level signal used to inform.." "0,1" newline bitfld.long 0x4 8. "APP_READY_ENTR_L23,Application Ready to Enter L23. Indication from your application that it is ready to enter the L23 state. The app_ready_entr_l23 signal is provided for applications that must control L23 entry (in case certain tasks must be performed.." "0,1" newline bitfld.long 0x4 7. "APP_CLK_REQ_N,Indicates that the application logic is ready to have reference clock removed. In designs which support reference clock removal through either L1 PM Sub-states or L1 CPM the application should set this signal to 1'b when it is ready to.." "0,1" newline bitfld.long 0x4 6. "APP_HOLD_PHY_RST,Set this signal to one before the de-assertion of power on reset to hold the PHY in reset. This can be used to configure your PHY. Synopsys PHYs can be configured through the PHY Viewport if desired. Please tie this port to zero if your.." "0,1" newline bitfld.long 0x4 5. "APP_SRIS_MODE,SRIS operating mode: 0b: non-SRIS mode 1b: SRIS mode" "0,1" newline bitfld.long 0x4 4. "APP_DBI_RO_WR_DISABLE,DBI Read-only Write Disable 0: MISC_CONTROL_1_OFF.DBI_RO_WR_EN register field is read-write. 1: MISC_CONTROL_1_OFF.DBI_RO_WR_EN register field is forced to 0 and is read-only." "MISC_CONTROL_1_OFF,MISC_CONTROL_1_OFF" newline bitfld.long 0x4 3. "DEVICE_TYPE,Device/port type. Indicates the specific type of this PCI Express function. It is also used to set the 'Device/Port Type' field of the 'PCI Express Capabilities Register'. The controller uses this input to determine the operating mode of the.." "PCI Express endpoint,Legacy PCI Express endpoint" newline bitfld.long 0x4 2. "APP_LTSSM_ENABLE,To do otherwise (that is de-assert it outside of the Detect LTSSM state) causes the controller to be reset and the LTSSM moves immediately back to the Detect state. This transition is outside of the PCIe Specification and it might cause.." "0,1" newline bitfld.long 0x4 0. "APP_ERR_VFUNC_ACTIVE,Indicates the function number in app_err_vfunc_num is valid." "0,1" line.long 0x8 "CTRL_1,CTRL_1" bitfld.long 0x8 29.--31. "APP_ERR_VFUNC_NUM,The number of the virtual function that is reporting the error indicated app_err_bus valid when app_hdr_valid is asserted. Uncorrected Internal errors (app_err_bus[9]) are not recorded for virtual functions.The PCIe SR-IOV.." "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 28. "SLV_ARMISC_INFO_ATU_BYPASS,AXI Slave Read Request Internal ATU Bypass. When set it indicates that this request should not be processed by the internal address translation unit" "0,1" newline hexmask.long.word 0x8 15.--27. 1. "APP_ERR_BUS,The type of error that your application detected. The controller combines the values the app_err_bus bits with the internally-detected error signals to set the corresponding bit in the Uncorrectable or Correctable Error Status Registers:.." newline bitfld.long 0x8 14. "APP_REQ_RETRY_EN,Provides a capability to defer incoming configuration requests until initialization is complete. When app_req_retry_en is asserted the controller completes incoming configuration requests with a configuration request retry status. Other.." "0,1" newline hexmask.long.byte 0x8 6.--13. 1. "APP_VF_REQ_RETRY_EN,Provides a per Virtual Function (VF) capability to defer incoming configuration requests until initialization is complete. When app_vf_req_retry_en is asserted for a certain VF the controller completes incoming configuration requests.." newline bitfld.long 0x8 4.--5. "APP_PF_REQ_RETRY_EN,Provides a per Physical Function (PF) capability to defer incoming configuration requests until initialization is complete. When app_pf_req_retry_en is asserted for a certain PF the controller completes incoming configuration.." "0,1,2,3" newline bitfld.long 0x8 2.--3. "APP_RAS_DES_TBA_CTRL,Controls the start/end of time based analysis. You must only set the pins to the required value for the duration of one clock cycle. This signal must be 2'b00 while the TIMER_START field in TIME_BASED_ANALYSIS_CONTROL_REG register is.." "No action,Start,End,Reserved" newline bitfld.long 0x8 1. "APP_RAS_DES_SD_HOLD_LTSSM,Hold and release LTSSM. For as long as this signal is '1' thecontroller stays in the current LTSSM." "0,1" newline bitfld.long 0x8 0. "SYS_AUX_PWR_DET,Auxiliary Power Detected. Used to report to the host software that auxiliary power (Vaux) is present." "0,1" line.long 0xC "CTRL_2,CTRL_2" bitfld.long 0xC 30.--31. "SYS_PWR_FAULT_DET,Power Fault Detected. Indicates the power controller detected a power fault at this slot. There is a separate sys_pwr_fault_det input bit for each function in your controller configuration." "0,1,2,3" newline bitfld.long 0xC 28.--29. "SYS_MRL_SENSOR_STATE,MRL Sensor State. Indicates the state of the manually-operated retention latch (MRL) sensor: 0: MRL is closed 1: MRL is open There is a separate sys_mrl_sensor_state input bit for each function in your controller configuration." "MRL is closed,MRL is open,?,?" newline bitfld.long 0xC 26.--27. "SYS_PRE_DET_STATE,Presence Detect State. Indicates whether or not a card is present in the slot: 0: Slot is empty 1: Card is present in the slot" "Slot is empty,Card is present in the slot,?,?" newline bitfld.long 0xC 24.--25. "SYS_ATTEN_BUTTON_PRESSED,Attention Button Pressed. Indicates that the system attention button was pressed sets the Attention Button Pressed bit in the Slot Status Register." "0,1,2,3" newline bitfld.long 0xC 23. "TX_LANE_FLIP_EN,Performs manual lane reversal for transmit lanes. For use when automatic lane reversal does not occur because lane 0 is not detected.In most cases tx_lane_flip_en should be wired to a static value at the chip level." "0,1" newline bitfld.long 0xC 22. "RX_LANE_FLIP_EN,Performs manual lane reversal for receive lanes. For use when automatic lane reversal does not occur because lane 0 is not detected.In most cases rx_lane_flip_en should be wired to a static value at the chip level." "0,1" newline bitfld.long 0xC 21. "DBG_PBA,MSIX PBA RAM Debug Mode. Use this input to activate the debug mode and allow direct read/write access to the PBA. You can also use the MSIX_RAM_CTRL_DBG_PBA field in MSIX_RAM_CTRL_OFF to activate debug mode. Debug mode turns off the.." "0,1" newline bitfld.long 0xC 20. "DBG_TABLE,MSIX Table RAM Debug Mode. Use this input to activate the debug mode and allow direct read/write access to the Table." "0,1" newline bitfld.long 0xC 19. "APP_ERR_FUNC_NUM,The number of the function that is reporting the error indicated app_err_bus valid when app_hdr_valid is asserted. Correctable and Uncorrected Internal errors (app_err_bus[10:9]) are not function specific and are recorded for all.." "0,1" newline bitfld.long 0xC 18. "APP_ERR_ADVISORY,Indicates that your application error is an advisory error. Your application should assert app_err_advisory under either of the following conditions: The controller is configured to mask completion timeout errors your application is.." "0,1" newline bitfld.long 0xC 17. "WAKEN_DO_OVRDVAL,WAKEN_DO_OVRDVAL" "0,1" newline bitfld.long 0xC 16. "WAKEN_DO_OVRDEN,WAKEN_DO_OVRDEN" "0,1" newline bitfld.long 0xC 15. "WAKEN_OE_OVRDVAL,WAKEN_OE_OVRDVAL" "0,1" newline bitfld.long 0xC 14. "WAKEN_OE_OVRDEN,WAKEN_OE_OVRDEN" "0,1" newline bitfld.long 0xC 13. "WAKEN_IN_OVRDVAL,WAKEN_IN_OVRDVAL" "0,1" newline bitfld.long 0xC 12. "WAKEN_IN_OVRDEN,WAKEN_IN_OVRDEN" "0,1" newline bitfld.long 0xC 11. "PERSTN_DO_OVRDVAL,PERSTN_DO_OVRDVAL" "0,1" newline bitfld.long 0xC 10. "PERSTN_DO_OVRDEN,PERSTN_DO_OVRDEN" "0,1" newline bitfld.long 0xC 9. "PERSTN_OE_OVRDVAL,PERSTN_OE_OVRDVAL" "0,1" newline bitfld.long 0xC 8. "PERSTN_OE_OVRDEN,PERSTN_OE_OVRDEN" "0,1" newline bitfld.long 0xC 7. "PERSTN_IN_OVRDVAL,PERSTN_IN_OVRDVAL" "0,1" newline bitfld.long 0xC 6. "PERSTN_IN_OVRDEN,PERSTN_IN_OVRDEN" "0,1" newline bitfld.long 0xC 5. "CLKREQN_DO_OVRDVAL,CLKREQN_DO_OVRDVAL" "0,1" newline bitfld.long 0xC 4. "CLKREQN_DO_OVRDEN,CLKREQN_DO_OVRDEN" "0,1" newline bitfld.long 0xC 3. "CLKREQN_OE_OVRDVAL,CLKREQN_OE_OVRDVAL" "0,1" newline bitfld.long 0xC 2. "CLKREQN_OE_OVRDEN,CLKREQN_OE_OVRDEN" "0,1" newline bitfld.long 0xC 1. "CLKREQN_IN_OVRDVAL,CLKREQN_IN_OVRDVAL" "0,1" newline bitfld.long 0xC 0. "CLKREQN_IN_OVRDEN,CLKREQN_IN_OVRDEN" "0,1" line.long 0x10 "CTRL_3,CTRL_3" bitfld.long 0x10 30.--31. "SYS_MRL_SENSOR_CHGED,MRL Sensor Changed. Indicates that the state of MRL sensor has changed. There is a separate sys_mrl_sensor_chged input bit for each function in your controller configuration." "0,1,2,3" newline hexmask.long.word 0x10 20.--29. 1. "VEN_MSG_LEN,The Length field for the vendor-defined Message TLP (indicates length of data payload in dwords).Should be set to 0x0." newline hexmask.long.byte 0x10 15.--19. 1. "VEN_MSG_TYPE,The Type field for the vendor-defined Message TLP." newline bitfld.long 0x10 12.--14. "VEN_MSG_VFUNC_NUM,Number of the virtual function accessing the VMI interface. The PCIe SR-IOV specification starts numbering VFs at 1. To ease timing during synthesis the PCIe controller starts numbering VFs at 0. For example ven_msg_vfunc_num=0 refers.." "0,1,2,3,4,5,6,7" newline bitfld.long 0x10 9.--11. "VEN_MSG_TC,The Traffic Class field for the vendor-defined Message TLP." "0,1,2,3,4,5,6,7" newline bitfld.long 0x10 7.--8. "VEN_MSG_ATTR,The Attributes field for the vendor-defined Message TLP. - Width is three bits when CX_IDO_ENABLE =1 - Width is two bits when CX_IDO_ENABLE =0" "?,Width is two bits when CX_IDO_ENABLE =0,?,?" newline bitfld.long 0x10 5.--6. "VEN_MSG_FMT,The Format field for the vendor-defined Message TLP. Should be set to 0x1." "0,1,2,3" newline bitfld.long 0x10 4. "VEN_MSG_VFUNC_ACTIVE,Indicates that a VF is accessing the VMI. - 0: No VF is active and ven_msg_vfunc_num is invalid. A PF is valid and identified by ven_msg_func_num. - 1: A VF is active and is identified by ven_msg_vfunc_num." "No VF is active and ven_msg_vfunc_num is invalid,A VF is active and is identified by.." newline bitfld.long 0x10 3. "VEN_MSG_FUNC_NUM,Function Number for the vendor-defined Message TLP. Function numbering starts at '0'." "0,1" newline bitfld.long 0x10 2. "VEN_MSG_EP,The Poisoned TLP (EP) bit for the vendor-defined Message TLP." "0,1" newline bitfld.long 0x10 1. "VEN_MSG_TD,The TLP Digest (TD) bit for the vendor-defined Message TLP valid when ven_msg_req is asserted." "0,1" newline bitfld.long 0x10 0. "VEN_MSG_REQ,Request from your application to send a vendor-defined Message. Once asserted ven_msg_req must remain asserted until the controller asserts ven_msg_grant." "0,1" repeat 16. (list 0x4 0x5 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF 0x10 0x11 0x13 0x14 0x15 0x17 )(list 0x0 0x4 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x3C 0x40 0x44 0x4C ) group.long ($2+0x78)++0x3 line.long 0x0 "CTRL_$1,CTRL_4" hexmask.long 0x0 0.--31. 1. "VEN_MSG_DATA_31_0,Third and fourth dwords of the Vendor Defined Message header where: - Bytes 8-11 (third header dword) =ven_msg_data[63:32] - Bytes 12-15 (fourth header dword) =ven_msg_data[31:0] where ven_msg_data[7:0] =byte 15" repeat.end repeat 12. (list 0x19 0x1A 0x1B 0x1D 0x1E 0x1F 0x20 0x21 0x22 0x23 0x24 0x25 )(list 0x54 0x58 0x5C 0x64 0x68 0x6C 0x70 0x74 0x78 0x7C 0x80 0x84 ) group.long ($2+0x78)++0x3 line.long 0x0 "CTRL_$1,CTRL_4" hexmask.long 0x0 0.--31. 1. "VEN_MSG_DATA_31_0,Third and fourth dwords of the Vendor Defined Message header where: - Bytes 8-11 (third header dword) =ven_msg_data[63:32] - Bytes 12-15 (fourth header dword) =ven_msg_data[31:0] where ven_msg_data[7:0] =byte 15" repeat.end group.long 0x80++0x7 line.long 0x0 "CTRL_6,CTRL_6" bitfld.long 0x0 31. "MSI_FNSEL,MSI_FNSEL" "0,1" newline bitfld.long 0x0 30. "VEN_MSI_OVRDEN,VEN_MSI_OVRDEN" "0,1" newline bitfld.long 0x0 29. "VEN_MSI_REQ,Request from your application to send an MSI when MSI is enabled.When MSI-X is enabled instead of MSI assertion of ven_msi_req causes the controller to generate an MSI-X message. Once asserted ven_msi_req must remain asserted until the.." "0,1" newline hexmask.long.byte 0x0 24.--28. 1. "VEN_MSI_VECTOR,Used to modulate the lower five bits of the MSI Data register when multiple message mode is enabled." newline bitfld.long 0x0 21.--23. "VEN_MSI_TC,Traffic Class of the MSI request valid when ven_msi_req is asserted." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 20. "VEN_MSI_VFUNC_ACTIVE,Indicates that the MSI request is coming from a VF. - 0: No VF is active and ven_msi_vfunc_num is invalid. A PF is valid and identified by ven_msi_func_num. - 1: A VF is active and is identified by ven_msi_vfunc_num." "No VF is active and ven_msi_vfunc_num is invalid,A VF is active and is identified by.." newline bitfld.long 0x0 17.--19. "VEN_MSI_VFUNC_NUM,Identifies the VF which is making the MSI request. The PCIe SR-IOV specification starts numbering VFs at 1. To ease timing during synthesis the PCIe controller starts numbering VFs at 0. For example ven_msi_vfunc_num=0 refers to the.." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 16. "VEN_MSI_FUNC_NUM,The function number of the MSI request. Function numbering starts at '0'." "0,1" newline hexmask.long.byte 0x0 8.--15. 1. "VEN_MSG_CODE,The Message Code for the vendor-defined Message TLP." newline hexmask.long.byte 0x0 0.--7. 1. "VEN_MSG_TAG,Tag for the vendor-defined Message TLP." line.long 0x4 "CTRL_7,CTRL_7" hexmask.long.byte 0x4 24.--31. 1. "SLV_AWMISC_INFO_P_TAG,AXI Slave Write Request Tag. Sets the TAG number for output posted requests. It is expected that your application normally sets this to '0' except when generating ATS invalidate requests." newline bitfld.long 0x4 23. "SLV_WMISC_INFO_EP,AXI Slave Write Data transaction related misc information. This is an optional signal that your application can use to poison write requests.When asserted the controller sets the Poisoned TLP (EP) bit in the TLP header of the current.." "0,1" newline bitfld.long 0x4 22. "PTM_AUTO_UPDATE_SIGNAL,Indicates that the controller should update the PTM Requester Context and Clock automatically every 10ms." "0,1" newline bitfld.long 0x4 21. "PTM_MANUAL_UPDATE_PULSE,Indicates that the controller should update the PTM Requester Context and Clock now." "0,1" newline bitfld.long 0x4 20. "PTM_EXTERNAL_MASTER_STROBE,PTM External Master Time Strobe." "0,1" newline hexmask.long.byte 0x4 12.--19. 1. "APP_VF_FRS_READY,Defers FRS messaging for a VF when set to '0'." newline bitfld.long 0x4 10.--11. "APP_PF_FRS_READY,Defers FRS messaging when set to '0'." "0,1,2,3" newline bitfld.long 0x4 9. "APP_DRS_READY,Defers DRS messaging when set to '0'." "0,1" newline bitfld.long 0x4 7.--8. "SYS_EML_INTERLOCK_ENGAGED,System Electromechanical Interlock Engaged. Indicates whether the system electromechanical interlock is engaged and controls the state of the Electromechanical Interlock Status bit in the Slot Status register." "0,1,2,3" newline bitfld.long 0x4 5.--6. "SYS_CMD_CPLED_INT,Command completed Interrupt. Indicates that the Hot-Plug controller completed a command. There is a separate sys_cmd_cpled_int input bit for each function in your controller configuration." "0,1,2,3" newline bitfld.long 0x4 3.--4. "SYS_PRE_DET_CHGED,Presence Detect Changed. Indicates that the state of card present detector has changed. There is a separate sys_pre_det_chged input bit for each function in your controller configuration." "0,1,2,3" newline bitfld.long 0x4 0.--2. "DIAG_CTRL_BUS,Diagnostic Control Bus - x01: Insert LCRC error by inverting the LSB of LCRC - x10: Insert ECRC error by inverting the LSB of ECRC The rising edge of these two signals ([1:0]) enable the controller to assert an LCRC or ECRC to the packet.." "?,Insert LCRC error by inverting the LSB of LCRC,?,?,?,?,?,?" group.long 0xB0++0x3 line.long 0x0 "CTRL_18,CTRL_18" bitfld.long 0x0 31. "SLV_USER_SEL,SLV_USER_SEL" "0,1" newline bitfld.long 0x0 29.--30. "MSTR_ARUSER_OVRDVAL_33_32,MSTR_ARUSER_OVRDVAL_33_32" "0,1,2,3" newline bitfld.long 0x0 27.--28. "MSTR_AWUSER_OVRDVAL_33_32,MSTR_AWUSER_OVRDVAL_33_32" "0,1,2,3" newline bitfld.long 0x0 26. "APP_LTR_MSG_FUNC_NUM,APP_LTR_MSG_FUNC_NUM" "0,1" newline bitfld.long 0x0 25. "APP_LTR_MSG_REQ,APP_LTR_MSG_REQ" "0,1" newline bitfld.long 0x0 24. "APP_PM_VF_XMT_PME_7,APP_PM_VF_XMT_PME_7" "0,1" newline bitfld.long 0x0 23. "APP_PM_VF_XMT_PME_6,APP_PM_VF_XMT_PME_6" "0,1" newline bitfld.long 0x0 22. "APP_PM_VF_XMT_PME_5,APP_PM_VF_XMT_PME_5" "0,1" newline bitfld.long 0x0 21. "APP_PM_VF_XMT_PME_4,APP_PM_VF_XMT_PME_4" "0,1" newline bitfld.long 0x0 20. "APP_PM_VF_XMT_PME_3,APP_PM_VF_XMT_PME_3" "0,1" newline bitfld.long 0x0 19. "APP_PM_VF_XMT_PME_2,APP_PM_VF_XMT_PME_2" "0,1" newline bitfld.long 0x0 18. "APP_PM_VF_XMT_PME_1,APP_PM_VF_XMT_PME_1" "0,1" newline bitfld.long 0x0 17. "APP_PM_VF_XMT_PME_0,APP_PM_VF_XMT_PME_0" "0,1" newline hexmask.long.word 0x0 4.--16. 1. "MSTR_RMISC_INFO,MSTR_RMISC_INFO" newline bitfld.long 0x0 2.--3. "MSTR_RMISC_INFO_CPL_STAT,MSTR_RMISC_INFO_CPL_STAT" "0,1,2,3" newline bitfld.long 0x0 0.--1. "MSTR_BMISC_INFO_CPL_STAT,MSTR_BMISC_INFO_CPL_STAT" "0,1,2,3" group.long 0xC0++0x3 line.long 0x0 "CTRL_22,CTRL_22" bitfld.long 0x0 31. "SLV_WMISC_INFO_SILENTDROP,SLV_WMISC_INFO_SILENTDROP" "0,1" newline bitfld.long 0x0 28.--30. "SLV_AWMISC_INFO_VFUNC_NUM,SLV_AWMISC_INFO_VFUNC_NUM" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 27. "SLV_AWMISC_INFO_VFUNC_ACTIVE,SLV_AWMISC_INFO_VFUNC_ACTIVE" "0,1" newline bitfld.long 0x0 26. "SLV_AWMISC_INFO_FUNC_NUM,SLV_AWMISC_INFO_FUNC_NUM" "0,1" newline bitfld.long 0x0 25. "SLV_AWMISC_INFO_ATU_BYPASS,SLV_AWMISC_INFO_ATU_BYPASS" "0,1" newline hexmask.long 0x0 0.--24. 1. "SLV_AWMISC_INFO,SLV_AWMISC_INFO" group.long 0xC8++0x3 line.long 0x0 "CTRL_24,CTRL_24" bitfld.long 0x0 30.--31. "MSTR_USER_SEL,MSTR_USER_SEL" "0,1,2,3" newline bitfld.long 0x0 27.--29. "SLV_ARMISC_INFO_VFUNC_NUM,SLV_ARMISC_INFO_VFUNC_NUM" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 26. "SLV_ARMISC_INFO_VFUNC_ACTIVE,SLV_ARMISC_INFO_VFUNC_ACTIVE" "0,1" newline bitfld.long 0x0 25. "SLV_ARMISC_INFO_FUNC_NUM,SLV_ARMISC_INFO_FUNC_NUM" "0,1" newline hexmask.long 0x0 0.--24. 1. "SLV_ARMISC_INFO,SLV_ARMISC_INFO" group.long 0xD8++0x3 line.long 0x0 "CTRL_28,CTRL_28" hexmask.long.word 0x0 21.--31. 1. "RSVD0,RSVD0" newline hexmask.long.byte 0x0 13.--20. 1. "APP_BUS_NUM,APP_BUS_NUM" newline hexmask.long.byte 0x0 8.--12. 1. "APP_DEV_NUM,APP_DEV_NUM" newline bitfld.long 0x0 7. "APP_MSI_CTRL_EN,APP_MSI_CTRL_EN" "0,1" newline hexmask.long.byte 0x0 0.--6. 1. "STS_DEBUG_SEL,STS_DEBUG_SEL" repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x4 0x8 0xC 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C ) group.long ($2+0x100)++0x3 line.long 0x0 "MAP_$1,MAP_0" hexmask.long 0x0 0.--31. 1. "LUT_MAP_MID_31_0,LUT_MAP_MID_31_0" repeat.end repeat 16. (list 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1A 0x1B 0x1C 0x1D 0x1E 0x1F )(list 0x40 0x44 0x48 0x4C 0x50 0x54 0x58 0x5C 0x60 0x64 0x68 0x6C 0x70 0x74 0x78 0x7C ) group.long ($2+0x100)++0x3 line.long 0x0 "MAP_$1,MAP_0" hexmask.long 0x0 0.--31. 1. "LUT_MAP_MID_31_0,LUT_MAP_MID_31_0" repeat.end repeat 16. (list 0x20 0x21 0x22 0x23 0x24 0x25 0x26 0x27 0x28 0x29 0x2A 0x2B 0x2C 0x2D 0x2E 0x2F )(list 0x80 0x84 0x88 0x8C 0x90 0x94 0x98 0x9C 0xA0 0xA4 0xA8 0xAC 0xB0 0xB4 0xB8 0xBC ) group.long ($2+0x100)++0x3 line.long 0x0 "MAP_$1,MAP_0" hexmask.long 0x0 0.--31. 1. "LUT_MAP_MID_31_0,LUT_MAP_MID_31_0" repeat.end repeat 16. (list 0x30 0x31 0x32 0x33 0x34 0x35 0x36 0x37 0x38 0x39 0x3A 0x3B 0x3C 0x3D 0x3E 0x3F )(list 0xC0 0xC4 0xC8 0xCC 0xD0 0xD4 0xD8 0xDC 0xE0 0xE4 0xE8 0xEC 0xF0 0xF4 0xF8 0xFC ) group.long ($2+0x100)++0x3 line.long 0x0 "MAP_$1,MAP_0" hexmask.long 0x0 0.--31. 1. "LUT_MAP_MID_31_0,LUT_MAP_MID_31_0" repeat.end rgroup.long 0x200++0x3 line.long 0x0 "STS_0,STS_0" bitfld.long 0x0 29.--31. "PM_L1SUB_STATE,Power management L1 sub-states FSM state" "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x0 24.--28. 1. "PM_MASTER_STATE,Power management master FSM state." newline bitfld.long 0x0 22.--23. "PM_PME_EN,PME Enable bit in the PMCSR. There is 1 bit of pm_pme_en for each configured function." "0,1,2,3" newline hexmask.long.byte 0x0 16.--21. 1. "PM_DSTATE,The current power management D-state of the function: - 000b: D0 - 001b: D1 - 010b: D2 - 011b: D3 - 100b: Uninitialized - Other values: Not applicable" newline bitfld.long 0x0 13.--15. "PM_CURNT_STATE,Indicates the current power state. The pm_curnt_state output is intended for debugging purposes not for system operation." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 12. "PM_L1_ENTRY_STARTED,L1 entry process is in progress." "0,1" newline bitfld.long 0x0 11. "PM_LINKST_IN_L1SUB,Power management is in L1 substate. Indicates when the link has entered L1 substates." "0,1" newline bitfld.long 0x0 10. "PM_LINKST_L2_EXIT,Power management is exiting L2 state. Not applicable for downstream port." "0,1" newline bitfld.long 0x0 9. "PM_LINKST_IN_L2,Power management is in L2 state." "0,1" newline bitfld.long 0x0 8. "PM_LINKST_IN_L1,Power management is in L1 state." "0,1" newline bitfld.long 0x0 7. "PM_LINKST_IN_L0S,Power management is in L0s state. Indicates in L0_STALL state when M-PCIe" "0,1" newline hexmask.long.byte 0x0 1.--6. 1. "SMLH_LTSSM_STATE,Current state of the LTSSM. Encoding is defined as follows: 6'h00: S_DETECT_QUIET 6'h01: S_DETECT_ACT 6'h02: S_POLL_ACTIVE 6'h03: S_POLL_COMPLIANCE 6'h04: S_POLL_CONFIG 6'h05: S_PRE_DETECT_QUIET 6'h06: S_DETECT_WAIT 6'h07:.." newline bitfld.long 0x0 0. "RADM_IDLE,RADM activity status signal. The controller creates the en_radm_clk_g output by gating this signal with the output of the RADM_CLK_GATING_EN field in the CLOCK_GATING_CTRL_OFF register. For debug purposes only." "0,1" group.long 0x204++0xB line.long 0x0 "STS_1,STS_1" bitfld.long 0x0 30.--31. "TRGT_TIMEOUT_CPL_ATTR,The Attributes value of the timed out completion. - Width is three bits when CX_IDO_ENABLE =1 - Width is two bits when CX_IDO_ENABLE =0" "?,Width is two bits when CX_IDO_ENABLE =0,?,?" newline bitfld.long 0x0 27.--29. "TRGT_TIMEOUT_CPL_TC,The TC of the timed out completion." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 26. "TRGT_TIMEOUT_CPL_VFUNC_ACTIVE,Indicates that the timeout is coming from a VF (Virtual function). - 0: No VF is active and trgt_timeout_cpl_vfunc_num is invalid. A PF is valid and identified by trgt_timeout_cpl_func_num - 1: A VF is active and is.." "No VF is active and trgt_timeout_cpl_vfunc_num..,A VF is active and is identified by.." newline bitfld.long 0x0 23.--25. "TRGT_TIMEOUT_CPL_VFUNC_NUM,Indicates which virtual function (VF) timed out. The PCIe SR-IOV specification starts numbering VFs at 1. To ease timing during synthesis the PCIe controller starts numbering VFs at 0. For example trgt_timeout_cpl_ vfunc_num=0.." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 22. "TRGT_TIMEOUT_CPL_FUNC_NUM,TRGT_TIMEOUT_CPL_FUNC_NUM" "0,1" newline hexmask.long.byte 0x0 14.--21. 1. "CFG_FLR_VF_ACTIVE,Set when the software initiates FLR a virtual function by writing to the 'Initiate FLR' register bit of that function. This signal is held asserted until the reset of both the application and internal controller logic has been.." newline rbitfld.long 0x0 12.--13. "CFG_FLR_PF_ACTIVE,Set when the software initiates FLR a physical function by writing to the 'Initiate FLR' register bit of that function. This signal is held asserted until reset of both the application and controller logic has been completed." "0,1,2,3" newline rbitfld.long 0x0 10.--11. "CFG_EML_CONTROL,Electromechanical Interlock Control. The state of the Electromechanical Interlock Control bit in the Slot Control register." "0,1,2,3" newline rbitfld.long 0x0 9. "CFG_L1SUB_EN,Indicates that any of the L1 Substates are enabled in the L1 Substates Control 1 Register. Could be used by your application in a downstream port to determine when not to drive CLKREQ# such as when L1" "0,1" newline rbitfld.long 0x0 7.--8. "AUX_PM_EN,AUX_PM_EN" "0,1,2,3" newline rbitfld.long 0x0 5.--6. "PM_STATUS,PME Status bit from the PMCSR. There is 1 bit of pm_status for each configured function." "0,1,2,3" newline hexmask.long.byte 0x0 0.--4. 1. "PM_SLAVE_STATE,Power management slave FSM state." line.long 0x4 "STS_2,STS_2" bitfld.long 0x4 30.--31. "RADM_TIMEOUT_CPL_ATTR,The Attributes field of the timed out completion" "0,1,2,3" newline rbitfld.long 0x4 29. "RADM_QOVERFLOW,Pulse indicating that one or more of the P/NP/CPL receive queues have overflowed. There is a 1-bit indication for each configured virtual channel. You can connect this output to your internal error reporting mechanism." "?,bit indication for each configured virtual channel" newline rbitfld.long 0x4 28. "RADM_Q_NOT_EMPTY,Level indicating that the receive queues contain TLP header/data." "0,1" newline bitfld.long 0x4 27. "RADM_TIMEOUT_FUNC_NUM,The function Number of the timed out completion. Function numbering starts at '0'." "0,1" newline rbitfld.long 0x4 26. "RADM_XFER_PENDING,Receive request pending status. Indicates Receive TLP requests are pending that is requests sent to the RTRGT1 or RTRGT0 interfaces are awaiting a response from your application." "0,1" newline rbitfld.long 0x4 25. "EDMA_XFER_PENDING,eDMA transfer pending status. Indicates eDMA Write or Read Channel transfers are pending that is DMA Write or Read Channels have not finished transferring data." "0,1" newline rbitfld.long 0x4 24. "BRDG_DBI_XFER_PENDING,AXI Slave DBI transfer pending status. Indicates AXI DBI Slave Read or Write transfers are pending that is AXI Slave transfers are awaiting a response from the controller." "0,1" newline rbitfld.long 0x4 22.--23. "CFG_INT_DISABLE,When high a functions ability to generate INTx messages is Disabled" "0,1,2,3" newline rbitfld.long 0x4 20.--21. "CFG_CMD_CPLED_INT_EN,Slot Control Command Completed Interrupt Enable." "0,1,2,3" newline hexmask.long.byte 0x4 12.--19. 1. "TRGT_TIMEOUT_LOOKUP_ID,The target completion LUT lookup ID of the timed out completion" newline hexmask.long.word 0x4 0.--11. 1. "TRGT_TIMEOUT_CPL_LEN,The Length of the timed out completion." line.long 0x8 "STS_3,STS_3" rbitfld.long 0x8 30.--31. "CFG_PWR_CTRLER_CTRL,Controls the system power controller (from bit 10 of the Slot Control register) per function: - 0: Power On - 1: Power Off" "Power On,Power Off,?,?" newline rbitfld.long 0x8 28.--29. "CFG_END2END_TLP_PFX_BLCK,The value of the End-End TLP Prefix Blocking field in the Device Control 2 register." "0,1,2,3" newline hexmask.long.byte 0x8 23.--27. 1. "CFG_PBUS_DEV_NUM,The device number assigned to the function. The number of bits depends the value of MULTI_DEVICE_AND_BUS_PER_FUNC_EN: - If MULTI_DEVICE_AND_BUS_PER_FUNC_EN =0 there are five bits of cfg_pbus_dev_num ([4:0]) regardless of the number of.." newline hexmask.long.word 0x8 11.--22. 1. "RADM_TIMEOUT_CPL_LEN,Length (in bytes) of the timed out completion. For a split completion it indicates the number of bytes remaining to be delivered when the completion timed out." newline hexmask.long.byte 0x8 3.--10. 1. "RADM_TIMEOUT_CPL_TAG,The Tag field of the timed out completion." newline bitfld.long 0x8 0.--2. "RADM_TIMEOUT_VFUNC_NUM,Indicates which virtual function (VF) had a completion timeout. The PCIe SR-IOV specification starts numbering VFs at '1'. To ease timing during synthesis the PCIe controller starts numbering VFs at '0' ." "0,1,2,3,4,5,6,7" rgroup.long 0x210++0xB line.long 0x0 "STS_4,STS_4" bitfld.long 0x0 31. "SMLH_LTSSM_STATE_RCVRY_EQ,This status signal is asserted during all Recovery Equalization states." "0,1" newline bitfld.long 0x0 29.--30. "CFG_DLL_STATE_CHGED_EN,Slot Control DLL State Change Enable" "0,1,2,3" newline bitfld.long 0x0 27.--28. "CFG_HP_SLOT_CTRL_ACCESS,Slot Control Accessed." "0,1,2,3" newline bitfld.long 0x0 25.--26. "CFG_RELAX_ORDER_EN,Contents of the 'Enable Relaxed Ordering' field(PCIE_CAP_EN_REL_ORDER) in the 'Device Control and Status' register (DEVICE_CONTROL_DEVICE_STATUS) register." "0,1,2,3" newline bitfld.long 0x0 23.--24. "CFG_NO_SNOOP_EN,Contents of the 'Enable No Snoop' field (PCIE_CAP_EN_NO_SNOOP)in the 'Device Control and Status' register(DEVICE_CONTROL_DEVICE_STATUS) register." "0,1,2,3" newline hexmask.long.byte 0x0 15.--22. 1. "PM_VF_STATUS,PME Status bit from the VF PMCSR. There is 1 bit of pm_status for each configured function. Each bit field corresponds to one of the NVF virtual functions." newline bitfld.long 0x0 13.--14. "CFG_VF_EN,Identifies those physical functions that have virtual functions enabled." "0,1,2,3" newline bitfld.long 0x0 11.--12. "CFG_ATTEN_BUTTON_PRESSED_EN,Slot Control Attention Button Pressed Enable." "0,1,2,3" newline bitfld.long 0x0 9.--10. "CFG_PWR_FAULT_DET_EN,Slot Control Power Fault Detect Enable." "0,1,2,3" newline bitfld.long 0x0 7.--8. "CFG_MRL_SENSOR_CHGED_EN,Slot Control MRL Sensor Changed Enable." "0,1,2,3" newline bitfld.long 0x0 5.--6. "CFG_PRE_DET_CHGED_EN,Slot Control Presence Detect Changed Enable." "0,1,2,3" newline bitfld.long 0x0 4. "PTM_REQ_RESPONSE_TIMEOUT,PTM Requester Response Timeout. Single-cycle pulse indicating 100us timeout occurred while waiting for a PTM Response or PTM ResponseD message." "0,1" newline bitfld.long 0x0 3. "PTM_TRIGGER_ALLOWED,Indicates that a PTM Requester manual update trigger is allowed." "0,1" newline bitfld.long 0x0 2. "PTM_UPDATING,Indicates that a PTM update is in progress." "0,1" newline bitfld.long 0x0 1. "PTM_RESPONDER_RDY_TO_VALIDATE,PTM Responder Ready to Validate." "0,1" newline bitfld.long 0x0 0. "PTM_CONTEXT_VALID,O Context Valid." "0,1" line.long 0x4 "STS_5,STS_5" bitfld.long 0x4 30.--31. "CFG_HP_INT_EN,Slot Control Hot Plug Interrupt Enable." "0,1,2,3" newline bitfld.long 0x4 28.--29. "CFG_CRS_SW_VIS_EN,Indicates the value of the CRS Software Visibility enable bit in the Root Control register. Applicable only for RC devices." "0,1,2,3" newline bitfld.long 0x4 26.--27. "CFG_PM_NO_SOFT_RST,This is the value of the No Soft Reset bit in the Power Management Control and Status Register." "0,1,2,3" newline hexmask.long.word 0x4 16.--25. 1. "FRSQ_INT_MSG_NUM,FRSQ Interrupt Message Number." newline hexmask.long.byte 0x4 8.--15. 1. "CFG_PBUS_NUM,The primary bus number assigned to the function. The number of bits depends the value of MULTI_DEVICE_AND_BUS_PER_FUNC_EN: - If MULTI_DEVICE_AND_BUS_PER_FUNC_EN =0 there are eight bits of cfg_pbus_num ([7:0]) regardless of the number of.." newline bitfld.long 0x4 6.--7. "CFG_RCB,The value of the RCB bit in the Link Control register. There is 1 bit of cfg_rcb assigned to each configured function." "0,1,2,3" newline hexmask.long.byte 0x4 0.--5. 1. "CFG_MAX_PAYLOAD_SIZE,The value of the Max_Payload_Size field in the Device Control register.There are 3 bits of cfg_max_payload_size assigned to each configured function." line.long 0x8 "STS_6,STS_6" newline bitfld.long 0x8 2. "BRDG_SLV_XFER_PENDING,AXI Slave non-DBI transfer pending status. Indicates AXI non-DBI Slave Read or Write transfers are pending that is AXI Slave transfers are awaiting a response from the controller." "0,1" newline bitfld.long 0x8 1. "SMLH_LINK_UP,PHY Link up/down indicator: - 1: Link is up - 0: Link is down" "Link is down,Link is up" newline bitfld.long 0x8 0. "RDLH_LINK_UP,Data link layer up/down indicator: This status from the flow control initialization state machine indicates that flow control has been initiated and the Data link layer is ready to transmit and receive packets. For multi-VC designs this.." "Link is down,Link is up" group.long 0x21C++0x7 line.long 0x0 "STS_7,STS_7" bitfld.long 0x0 29.--31. "RADM_TIMEOUT_CPL_TC,The Traffic Class of the timed out completion." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 28. "RADM_TIMEOUT_VFUNC_ACTIVE,Indicates that a virtual function (VF) had a completion timeout. - 0: No VF is active and radm_timeout_vfunc_num is invalid. A PF is valid and identified by radm_timeout_func_num. - 1: A VF is active and is identified by.." "No VF is active and radm_timeout_vfunc_num is..,A VF is active and is identified by.." newline hexmask.long.word 0x0 18.--27. 1. "CFG_PCIE_CAP_INT_MSG_NUM,From bits [13:9] of the PCI Express Capabilities register used when MSI or MSI-X is enabled. Assertion of hp_msi or cfg_pme_msi along with a value cfg_pcie_cap_int_msg_num is equivalent to the controller receiving an MSI with.." newline hexmask.long.word 0x0 8.--17. 1. "CFG_AER_INT_MSG_NUM,From bits [31:27] of the Root Error Status register used when MSI or MSI-X is enabled. Assertion of cfg_aer_rc_err_msi along with a value cfg_aer_int_msg_num is equivalent to the controller receiving an MSI with the.." newline hexmask.long.byte 0x0 0.--7. 1. "CFG_VF_BME,Bus master enable bit from the Control Register in the PCI header of each VF. Each bit field corresponds to one of the NVF virtual functions." line.long 0x4 "STS_8,STS_8" hexmask.long.word 0x4 16.--31. 1. "RADM_MSG_REQ_ID,The requester ID of the received Message. - [15:8]: Bus number - [7:3]: Device number - [2:0]: Function number" newline hexmask.long.word 0x4 0.--15. 1. "CFG_INT_PIN,The cfg_int_pin indicates the configured value for the Interrupt Pin Register field in the BRIDGE_CTRL_INT_PIN_INT_LINE register." repeat 8. (list 0x9 0xA 0xF 0x10 0x11 0x12 0x15 0x16 )(list 0x0 0x4 0x18 0x1C 0x20 0x24 0x30 0x34 ) group.long ($2+0x224)++0x3 line.long 0x0 "STS_$1,STS_9" hexmask.long 0x0 0.--31. 1. "RADM_MSG_PAYLOAD_31_0,Received message header information. When a vendor-defined or ltr messageis received (radm_vendor_msg=1 or radm_ltr_msg=1) the controller maps radm_msg_payload to the Rx TLP header dwords as follows: When RX_TLP =1 - [31:0] = bytes.." repeat.end repeat 16. (list 0xB 0xC 0xD 0xE 0x14 0x17 0x18 0x1C 0x1D 0x1E 0x1F 0x20 0x21 0x22 0x23 0x24 )(list 0x0 0x4 0x8 0xC 0x24 0x30 0x34 0x44 0x48 0x4C 0x50 0x54 0x58 0x5C 0x60 0x64 ) rgroup.long ($2+0x22C)++0x3 line.long 0x0 "STS_$1,STS_11" hexmask.long 0x0 0.--31. 1. "PTM_LOCAL_CLOCK_31_0,PTM_LOCAL_CLOCK_31_0" repeat.end repeat 3. (list 0x25 0x26 0x27 )(list 0x68 0x6C 0x70 ) rgroup.long ($2+0x22C)++0x3 line.long 0x0 "STS_$1,STS_11" hexmask.long 0x0 0.--31. 1. "PTM_LOCAL_CLOCK_31_0,PTM_LOCAL_CLOCK_31_0" repeat.end group.long 0x24C++0x3 line.long 0x0 "STS_19,STS_19" hexmask.long.word 0x0 16.--31. 1. "MSTR_ARMISC_INFO_47_32,MSTR_ARMISC_INFO_47_32" newline hexmask.long.word 0x0 0.--15. 1. "MSTR_AWMISC_INFO_47_32,MSTR_AWMISC_INFO_47_32" rgroup.long 0x264++0xB line.long 0x0 "STS_25,STS_25" bitfld.long 0x0 30.--31. "CFG_MEM_SPACE_EN,CFG_MEM_SPACE_EN" "0,1,2,3" newline hexmask.long.byte 0x0 24.--29. 1. "CFG_MAX_RD_REQ_SIZE,CFG_MAX_RD_REQ_SIZE" newline bitfld.long 0x0 22.--23. "CFG_BUS_MASTER_EN,CFG_BUS_MASTER_EN" "0,1,2,3" newline bitfld.long 0x0 21. "CFG_DISABLE_LTR_CLR_MSG,CFG_DISABLE_LTR_CLR_MSG" "0,1" newline bitfld.long 0x0 20. "CFG_LTR_M_EN,CFG_LTR_M_EN" "0,1" newline hexmask.long.byte 0x0 16.--19. 1. "CFG_ATTEN_IND,CFG_ATTEN_IND" newline hexmask.long.byte 0x0 12.--15. 1. "CFG_PWR_IND,CFG_PWR_IND" newline bitfld.long 0x0 10.--11. "CFG_PF_PASID_PRIV_MODE_EN,CFG_PF_PASID_PRIV_MODE_EN" "0,1,2,3" newline bitfld.long 0x0 8.--9. "CFG_PF_PASID_EXECUTE_PERM_EN,CFG_PF_PASID_EXECUTE_PERM_EN" "0,1,2,3" newline bitfld.long 0x0 6.--7. "CFG_PF_PASID_EN,CFG_PF_PASID_EN" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "CFG_START_VFI,CFG_START_VFI" line.long 0x4 "STS_26,STS_26" hexmask.long.word 0x4 16.--31. 1. "CFG_SUBBUS_NUM,CFG_SUBBUS_NUM" newline hexmask.long.word 0x4 0.--15. 1. "CFG_2NDBUS_NUM,CFG_2NDBUS_NUM" line.long 0x8 "STS_27,STS_27" hexmask.long.byte 0x8 24.--31. 1. "PM_VF_PME_EN,PM_VF_PME_EN" newline hexmask.long.tbyte 0x8 0.--23. 1. "PM_VF_DSTATE,PM_VF_DSTATE" tree.end endif tree.end tree "PCIE2 (PCI Express 2)" sif (CORENAME()=="CORTEXR5F") tree "PCIE2_PF0" base ad:0xF1100000 tree "PF0_TYPE1_HDR (PCI-Compatible Configuration Space Header Type1)" group.long 0x0++0x2F line.long 0x0 "TYPE1_DEV_ID_VEND_ID_REG,Device ID and Vendor ID Register." hexmask.long.word 0x0 16.--31. 1. "DEVICE_ID,Device ID. The Device ID register identifies the particular Function. This identifier is allocated by the vendor. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else.." newline hexmask.long.word 0x0 0.--15. 1. "VENDOR_ID,Vendor ID. The Vendor ID register identifies the manufacturer of the Function. Valid vendor identifiers are allocated by the PCI-SIG to ensure uniqueness. It is not permitted to populate this register with a value of FFFFh which is an invalid.." line.long 0x4 "TYPE1_STATUS_COMMAND_REG,Status and Command Register." bitfld.long 0x4 31. "DETECTED_PARITY_ERROR,Detected Parity Error. This bit is set by a Function whenever it receives a Poisoned TLP regardless of the state the Parity Error Response bit in the Command register. The bit is set when the Poisoned TLP is received by a.." "0,1" newline bitfld.long 0x4 30. "SIGNALED_SYS_ERROR,Signaled System Error. This bit is set when a Function sends an ERR_FATAL or ERR_NONFATAL Message and the SERR# Enable bit in the Command register is 1b." "0,1" newline bitfld.long 0x4 29. "RCVD_MASTER_ABORT,Received Master Abort. This bit is set when a Requester receives a Completion with Unsupported Request Completion status. The bit is set when the Unsupported Request is received by a Function's primary side." "0,1" newline bitfld.long 0x4 28. "RCVD_TARGET_ABORT,Received Target Abort. This bit is set when a Requester receives a Completion with Completer Abort Completion status. The bit is set when the Completer Abort is received by a Function's primary side." "0,1" newline bitfld.long 0x4 27. "SIGNALED_TARGET_ABORT,Signaled Target Abort. This bit is set when a Function completes a Posted or Non-Posted Request as a Completer Abort error. This applies to a Function when the Completer Abort was generated by its primary side." "0,1" newline rbitfld.long 0x4 25.--26. "DEV_SEL_TIMING,DEVSEL Timing. This field was originally described in the PCI Local Bus Specification. Its functionality does not apply to PCI Express. The controller hardwires it to 00b." "0,1,2,3" newline bitfld.long 0x4 24. "MASTER_DPE,Master Data Parity Error. This bit is set by a Function if the Parity Error Response bit in the Command register is 1b and either of the following two conditions occurs: - Port receives a Poisoned Completion going downstream - Port transmits a.." "0,1" newline rbitfld.long 0x4 23. "FAST_B2B_CAP,Fast Back-to-Back Transactions Capable. This bit was originally described in the PCI Local Bus Specification. Its functionality does not apply to PCI Express. The controller hardwires this bit to 0b." "0,1" newline rbitfld.long 0x4 22. "RSVDP_22,Reserved for future use." "0,1" newline rbitfld.long 0x4 21. "FAST_66MHZ_CAP,66 MHz Capable. This bit was originally described in the PCI Local Bus Specification. Its functionality does not apply to PCI Express. The controller hardwires this bit to 0b." "0,1" newline rbitfld.long 0x4 20. "CAP_LIST,Capabilities List. Indicates the presence of an Extended Capability list item. Since all PCI Express device Functions are required to implement the PCI Express Capability structure the controller hardwires this bit to 1b." "0,1" newline rbitfld.long 0x4 19. "INT_STATUS,Interrupt Status. When set indicates that an INTx emulation interrupt is pending internally in the Function. INTx emulation interrupts forwarded by Functions from the secondary side are not reflected in this bit. Setting the Interrupt Disable.." "0,1" newline rbitfld.long 0x4 17.--18. "RSVDP_17,Reserved for future use." "0,1,2,3" newline bitfld.long 0x4 16. "IMM_READINESS,Immediate Readiness. This optional bit when set indicates the Function is guaranteed to be ready to successfully complete valid configuration accesses at any time following any reset that the host is capable of issuing Configuration.." "0,1" newline hexmask.long.byte 0x4 11.--15. 1. "RESERV,Reserved." newline bitfld.long 0x4 10. "INT_EN,Interrupt Disable. Controls the ability of a Function to generate INTx emulation interrupts. When set Functions are prevented from asserting INTx interrupts. Note: - Any INTx emulation interrupts already asserted by the Function must be.." "0,1" newline rbitfld.long 0x4 9. "RSVDP_9,Reserved for future use." "0,1" newline bitfld.long 0x4 8. "SERREN,SERR# Enable. When set this bit enables reporting upstream of Non-fatal and Fatal errors detected by the Function. Note: The errors are reported if enabled either through this bit or through the PCI Express specific bits in the Device Control.." "0,1" newline rbitfld.long 0x4 7. "IDSEL,IDSEL Stepping/Wait Cycle Control. This bit was originally described in the PCI Local Bus Specification. Its functionality does not apply to PCI Express. The controller hardwires this bit to 0b." "0,1" newline bitfld.long 0x4 6. "PERREN,Parity Error Response. This bit controls the logging of poisoned TLPs in the Master Data Parity Error bit in the Status register. For more details see the 'Error Registers' section of the PCI Express Base Specification." "0,1" newline rbitfld.long 0x4 5. "VGAPS,VGA Palette Snoop. This bit was originally described in the PCI Local Bus Specification and the PCI-to-PCI Bridge Architecture Specification. Its functionality does not apply to PCI Express. The controller hardwires this bit to 0b." "0,1" newline rbitfld.long 0x4 4. "MWI_EN,Memory Write and Invalidate. This bit was originally described in the PCI Local Bus Specification and the PCI-to-PCI Bridge Architecture Specification. Its functionality does not apply to PCI Express. The controller hardwires this bit to 0b. For.." "0,1" newline rbitfld.long 0x4 3. "SCO,Special Cycle Enable. This bit was originally described in the PCI Local Bus Specification. Its functionality does not apply to PCI Express. The controller hardwires this bit to 0b." "0,1" newline bitfld.long 0x4 2. "BME,Bus Master Enable. This bit controls forwarding of Memory or I/O requests by a port in the Upstream direction. When this bit is 0b Memory and I/O Requests received at a Root Port must be handled as Unsupported Requests (UR) For Non-Posted Requests a.." "0,1" newline bitfld.long 0x4 1. "MSE,Memory Space Enable. This bit controls a Function's response to Memory Space accesses received on its primary side. - When set the Function is enabled to decode the address and further process Memory Space accesses. - When clear all received Memory.." "0,1" newline bitfld.long 0x4 0. "IO_EN,IO Space Enable. This bit controls a Function's response to I/O Space accesses received on its primary side. - When set the Function is enabled to decode the address and further process I/O Space accesses. - When clear all received I/O accesses.." "0,1" line.long 0x8 "TYPE1_CLASS_CODE_REV_ID_REG,Class Code and Revision ID Register." hexmask.long.byte 0x8 24.--31. 1. "BASE_CLASS_CODE,Base Class Code. A code that broadly classifies the type of operation the Function performs. Encodings for base class are provided in the PCI Code and ID Assignment Specification. All unspecified encodings are reserved. Note: The access.." newline hexmask.long.byte 0x8 16.--23. 1. "SUBCLASS_CODE,Sub-Class Code. Specifies a base class sub-class which identifies more specifically the operation of the Function. Encodings for sub-class are provided in the PCI Code and ID Assignment Specification. All unspecified encodings are.." newline hexmask.long.byte 0x8 8.--15. 1. "PROGRAM_INTERFACE,Programming Interface. This field identifies a specific register level programming interface (if any) so that device independent software can interact with the Function. Encodings for interface are provided in the PCI Code and ID.." newline hexmask.long.byte 0x8 0.--7. 1. "REVISION_ID,Revision ID. The value of this field specifies a Function specific revision identifier. The value is chosen by the vendor. Zero is an acceptable value. The Revision ID should be viewed as a vendor defined extension to the Device ID. Note: The.." line.long 0xC "TYPE1_BIST_HDR_TYPE_LAT_CACHE_LINE_SIZE_REG,BIST. Header Type. Latency Timer. and Cache Line Size Register." hexmask.long.byte 0xC 24.--31. 1. "BIST,BIST. This register is used for control and status of BIST. Functions that do not support BIST must hardwire the register to 00h. A Function whose BIST is invoked must not prevent normal operation of the PCI Express Link. Bit descriptions: - [31]:.." newline rbitfld.long 0xC 23. "MULTI_FUNC,Multi-Function Device. - When set indicates that the device may contain multiple Functions but not necessarily. Software is permitted to probe for Functions other than Function 0. - When clear software must not probe for Functions other.." "0,1" newline hexmask.long.byte 0xC 16.--22. 1. "HEADER_TYPE,Header Layout. This field identifies the layout of the second part of the predefined header. The controller uses 000 0001b encoding. The encoding 000 0010b is reserved. This encoding was originally described in the PC Card Standard Electrical.." newline hexmask.long.byte 0xC 8.--15. 1. "LATENCY_MASTER_TIMER,Latency Timer. This register is also referred to as Primary Latency Timer. The Latency Timer was originally described in the PCI Local Bus Specification and the PCI-to-PCI Bridge Architecture Specification. Its functionality does not.." newline hexmask.long.byte 0xC 0.--7. 1. "CACHE_LINE_SIZE,Cache Line Size. The Cache Line Size register is programmed by the system firmware or the operating system to system cache line size. However legacy conventional PCI software may not always be able to program this register correctly.." line.long 0x10 "BAR0_REG,BAR0 Register. System software must build a consistent address map before booting the machine to an operating system. This means it has to determine how much memory is in the system. and how much address space the Functions in the system.." hexmask.long 0x10 4.--31. 1. "BAR0_START,BAR0 Base Address. - Memory Space: Base Address. - IO Space: bits[31:2] are used to map the function into IO space/Base. Address. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R(Sticky)/W(Sticky) if.." newline bitfld.long 0x10 3. "BAR0_PREFETCH,BAR0 Prefetchable. - Memory Space: Set to one if data is pre-fetchable. A Function is permitted to mark a range as prefetchable. If there are no side effects on reads the function returns all bytes on reads regardless of the byte enables.." "0,1" newline bitfld.long 0x10 1.--2. "BAR0_TYPE,BAR0 Type. - Memory Space: Base Address registers that map into Memory Space can be 32 bits or 64 bits wide (to support mapping into a 64-bit address space). The bit encoding is as follows: -- 00: Base register is 32 bits wide and can be mapped.." "Base register is 32 bits wide and can be mapped..,Reserved,?,?" newline bitfld.long 0x10 0. "BAR0_MEM_IO,BAR0 Memory Space Indicator. This bit is used to determine whether the register maps into Memory or I/O Space. Base Address registers that map to Memory Space must return a 0b. Base Address registers that map to I/O Space must return a 1b." "0,1" line.long 0x14 "BAR1_REG,BAR1 Register. System software must build a consistent address map before booting the machine to an operating system. This means it has to determine how much memory is in the system. and how much address space the Functions in the system.." hexmask.long 0x14 4.--31. 1. "BAR1_START,BAR1 Base Address. - Memory Space: Base Address. - IO Space: bits[31:2] are used to map the function into IO space/Base. Address. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R(Sticky)/W(Sticky) if.." newline bitfld.long 0x14 3. "BAR1_PREFETCH,BAR1 Prefetchable. - Memory Space: Set to one if data is pre-fetchable. A Function is permitted to mark a range as prefetchable. If there are no side effects on reads the function returns all bytes on reads regardless of the byte enables.." "0,1" newline bitfld.long 0x14 1.--2. "BAR1_TYPE,BAR1 Type. - Memory Space: Base Address registers that map into Memory Space can be 32 bits or 64 bits wide (to support mapping into a 64-bit address space). The bit encoding is as follows: -- 00: Base register is 32 bits wide and can be mapped.." "Base register is 32 bits wide and can be mapped..,Reserved,?,?" newline bitfld.long 0x14 0. "BAR1_MEM_IO,BAR1 Memory Space Indicator. This bit is used to determine whether the register maps into Memory or I/O Space. Base Address registers that map to Memory Space must return a 0b. Base Address registers that map to I/O Space must return a 1b." "0,1" line.long 0x18 "SEC_LAT_TIMER_SUB_BUS_SEC_BUS_PRI_BUS_REG,Secondary Latency Timer. Subordinate Bus Number. Secondary Bus Number. and Primary Bus Number Register." hexmask.long.byte 0x18 24.--31. 1. "SEC_LAT_TIMER,Secondary Latency Timer. This register does not apply to PCI Express. The controller hardwires it to 00h." newline hexmask.long.byte 0x18 16.--23. 1. "SUB_BUS,Subordinate Bus Number. The Subordinate Bus Number register is used to record the bus number of the highest numbered PCI bus segment which is behind (or subordinate to) the bridge. Configuration software programs the value in this register. The.." newline hexmask.long.byte 0x18 8.--15. 1. "SEC_BUS,Secondary Bus Number. The Secondary Bus Number register is used to record the bus number of the PCI bus segment to which the secondary interface of the bridge is connected. Configuration software programs the value in this register. The bridge.." newline hexmask.long.byte 0x18 0.--7. 1. "PRIM_BUS,Primary Bus Number. This register is not used by PCI Express Functions. It is implemented for compatibility with legacy software." line.long 0x1C "SEC_STAT_IO_LIMIT_IO_BASE_REG,Secondary Status. and I/O Limit and Base Register. The I/O Limit and I/O Base registers are optional and define an address range that is used by the bridge to determine when to forward I/O transactions from one interface to.." bitfld.long 0x1C 31. "SEC_STAT_DPE,Detected Parity Error. This bit is set by a Function when a Poisoned TLP is received by its secondary side regardless of the state the Parity Error Response Enable bit in the Bridge Control register." "0,1" newline bitfld.long 0x1C 30. "SEC_STAT_RCVD_SYS_ERR,Received System Error. This bit is set when the secondary side of a Function receives an ERR_FATAL or ERR_NONFATAL message." "0,1" newline bitfld.long 0x1C 29. "SEC_STAT_RCVD_MSTR_ABRT,Received Master Abort. This bit is set when the secondary side of a Function (for requests initiated by the Type 1 header Function itself) receives a Completion with Unsupported Request Completion status." "0,1" newline bitfld.long 0x1C 28. "SEC_STAT_RCVD_TRGT_ABRT,Received Target Abort. This bit is set when the secondary side of a Function (for requests initiated by the Type 1 header Function itself) receives a Completion with Completer Abort Completion status." "0,1" newline bitfld.long 0x1C 27. "SEC_STAT_SIG_TRGT_ABRT,Signaled Target Abort. This bit is set when the secondary side of the Function (for Requests completed by the Type 1 header Function itself) completes a Posted or Non-Posted request as a Completer Abort error." "0,1" newline rbitfld.long 0x1C 25.--26. "RSVDP_25,Reserved for future use." "0,1,2,3" newline bitfld.long 0x1C 24. "SEC_STAT_MDPE,Master Data Parity Error. This bit is set by a Function if the Parity Error Response Enable bit in the Bridge Control register is set and either of the following two conditions occurs: - Port receives a Poisoned Completion coming Upstream.." "0,1" newline rbitfld.long 0x1C 23. "RSVDP_23,Reserved for future use." "0,1" newline hexmask.long.byte 0x1C 16.--22. 1. "SEC_STAT_RESERV,Reserved." newline hexmask.long.byte 0x1C 12.--15. 1. "IO_LIMIT,I/O Limit Address. These bits correspond to the address[15:12] of IO address range. For the purpose of address decoding the bridge assumes that the lower 12 address bits address[11:0] of the I/O limit address (not implemented in the I/O Limit.." newline rbitfld.long 0x1C 9.--11. "IO_RESERV1,Reserved." "0,1,2,3,4,5,6,7" newline bitfld.long 0x1C 8. "IO_DECODE_BIT8,I/O Addressing Encode (IO Limit Address). This bit encodes the IO addressing capability of the bridge. IO_DECODE_BIT8 indicates the following: - 0h: The bridge supports only 16-bit I/O addressing (for ISA compatibility). For the purpose of.." "0,1" newline hexmask.long.byte 0x1C 4.--7. 1. "IO_BASE,I/O Base Address. These bits correspond to the address[15:12] of IO address range. For the purpose of address decoding the bridge assumes that the lower 12 address bits address[11:0] of the I/O base address (not implemented in the I/O Base.." newline rbitfld.long 0x1C 1.--3. "IO_RESERV,Reserved." "0,1,2,3,4,5,6,7" newline bitfld.long 0x1C 0. "IO_DECODE,I/O Addressing Encode (IO Base Address) This bit encodes the IO addressing capability of the bridge. IO_DECODE indicates the following: - 0h: The bridge supports only 16-bit I/O addressing (for ISA compatibility). For the purpose of address.." "0,1" line.long 0x20 "MEM_LIMIT_MEM_BASE_REG,Memory Limit and Base Register. The Memory Limit and Memory Base registers define a memory mapped address range which is used by the bridge to determine when to forward memory transactions from one interface to the other. If there.." hexmask.long.word 0x20 20.--31. 1. "MEM_LIMIT,Memory Limit Address. These bits correspond to the upper 12 address bits Address[31:20] of 32-bit addresses. For the purpose of address decoding the bridge assumes that the lower 20 address bits Address[19:0] of the memory limit address.." newline hexmask.long.byte 0x20 16.--19. 1. "MEM_LIMIT_RESERV,Reserved." newline hexmask.long.word 0x20 4.--15. 1. "MEM_BASE,Memory Base Address. These bits correspond to the upper 12 address bits Address[31:20] of 32-bit addresses. For the purpose of address decoding the bridge assumes that the lower 20 address bits Address[19:0] of the memory base address (not.." newline hexmask.long.byte 0x20 0.--3. 1. "MEM_BASE_RESERV,Reserved." line.long 0x24 "PREF_MEM_LIMIT_PREF_MEM_BASE_REG,Prefetchable Memory Limit and Base Register. The Prefetchable Memory Limit and Prefetchable Memory Base registers must indicate that 64-bit addresses are supported. as defined in PCI-to-PCI Bridge Architecture.." hexmask.long.word 0x24 20.--31. 1. "PREF_MEM_LIMIT,Prefetchable Memory Limit Address. If the Prefetchable Memory Limit register indicates support for 32-bit addressing then the Prefetchable Limit Upper 32 Bits register is implemented as a read-only register that returns zero when read. If.." newline rbitfld.long 0x24 17.--19. "PREF_RESERV1,Reserved." "0,1,2,3,4,5,6,7" newline rbitfld.long 0x24 16. "PREF_MEM_LIMIT_DECODE,Prefetchable Memory Limit Decode. This bit encodes whether or not the bridge supports 64-bit addresses. Note: This bit is a copy of the PREF_MEM_DECODE bit and always reflects the current value of that bit. The value of.." "0,1" newline hexmask.long.word 0x24 4.--15. 1. "PREF_MEM_BASE,Prefetchable Memory Base Address. If the Prefetchable Memory Base register indicates support for 32-bit addressing then the Prefetchable Base Upper 32 Bits register is implemented as a read-only register that returns zero when read. If the.." newline rbitfld.long 0x24 1.--3. "PREF_RESERV,Reserved." "0,1,2,3,4,5,6,7" newline bitfld.long 0x24 0. "PREF_MEM_DECODE,Prefetchable Memory Base Decode. This bit encodes whether or not the bridge supports 64-bit addresses. Note: By default the bit is set to 1'b1 indicating that 64-bit addresses are supported. If the bridge only supports 32-bit prefetchable.." "0,1" line.long 0x28 "PREF_BASE_UPPER_REG,Prefetchable Base Upper 32 Bits Register. The Prefetchable Base Upper 32 Bits register is an optional extension to the Prefetchable Memory Base register." hexmask.long 0x28 0.--31. 1. "PREF_MEM_BASE_UPPER,Prefetchable Base Upper 32 Bit. If the Prefetchable Memory Base register indicates support for 32-bit addressing then this register is implemented as read-only register that returns zero when read. If the Prefetchable Memory Base.." line.long 0x2C "PREF_LIMIT_UPPER_REG,Prefetchable Limit Upper 32 Bits Register. The Prefetchable Limit Upper 32 Bits register is an optional extension to the Prefetchable Memory Limit register." hexmask.long 0x2C 0.--31. 1. "PREF_MEM_LIMIT_UPPER,Prefetchable Limit Upper 32 Bit. If the Prefetchable Memory Limit register indicate support for 64-bit addressing then this register is implemented as read/write register which must be initialized by configuration software. This.." rgroup.long 0x30++0x3 line.long 0x0 "IO_LIMIT_UPPER_IO_BASE_UPPER_REG,I/O Limit and Base Upper 16 Bits Register. The I/O Limit Upper 16 Bits and I/O Base Upper 16 Bits registers are optional extensions to the I/O Limit and I/O Base registers." hexmask.long.word 0x0 16.--31. 1. "IO_LIMIT_UPPER,I/O Limit Upper 16 Bits. If the I/O Limit register indicates support for 16-bit I/O address decoding then this register is implemented as a read-only register which return zero when read. If the I/O Limit register indicates support for.." newline hexmask.long.word 0x0 0.--15. 1. "IO_BASE_UPPER,I/O Base Upper 16 Bits. If the I/O Base register indicates support for 16-bit I/O address decoding then this register is implemented as a read-only register which return zero when read. If the I/O base register indicates support for 32-bit.." group.long 0x34++0xB line.long 0x0 "TYPE1_CAP_PTR_REG,Capabilities Pointer Register." hexmask.long.tbyte 0x0 8.--31. 1. "RSVDP_8,Reserved for future use." newline hexmask.long.byte 0x0 0.--7. 1. "CAP_POINTER,Capabilities Pointer. This register is used to point to a linked list of capabilities implemented by this Function. Since all PCI Express Functions are required to implement the PCI Express Capability structure this register must point to a.." line.long 0x4 "TYPE1_EXP_ROM_BASE_REG,Expansion ROM Base Address Register. This register is defined to handle the base address and size information for this expansion ROM. The mask for this ROM BAR exists (if implemented) as a shadow register at this address. The.." hexmask.long.tbyte 0x4 11.--31. 1. "EXP_ROM_BASE_ADDRESS,Expansion ROM Base Address. Upper 21 bits of the Expansion ROM base address. The number of bits (out of these 21) that a Function actually implements depends on how much address space the Function requires. The mask for this ROM BAR.." newline hexmask.long.word 0x4 1.--10. 1. "RSVDP_1,Reserved for future use." newline bitfld.long 0x4 0. "ROM_BAR_ENABLE,Expansion ROM Enable. This bit controls whether or not the Function accepts accesses to its expansion ROM. When this bit is 0b the Function's expansion ROM address space is disabled. When the bit is 1b address decoding is enabled using.." "0,1" line.long 0x8 "BRIDGE_CTRL_INT_PIN_INT_LINE_REG,Bridge Control. Interrupt Pin. and Interrupt Line Register." hexmask.long.word 0x8 23.--31. 1. "BRIDGE_CTRL_RESERV,Reserved." newline bitfld.long 0x8 22. "SBR,Secondary Bus Reset. Setting this bit triggers a hot reset on the corresponding PCI Express Port. Software must ensure a minimum reset duration (Trst) as defined in the PCI Local Bus Specification. Software and systems must honor.." "0,1" newline rbitfld.long 0x8 21. "MSTR_ABORT_MODE,Master Abort Mode. This bit was originally described in the PCI-to-PCI Bridge Architecture Specification. Its functionality does not apply to PCI Express. The controller hardwires this bit to 0b. Note: The access attributes of this field.." "0,1" newline rbitfld.long 0x8 20. "VGA_16B_DEC,VGA 16 bit decode. This bit only has meaning if VGA Enable bit is set. This bit enables system configuration software to select between 10-bit and 16-bit I/O address decoding for all VGA I/O register accesses that are forwarded from primary.." "0,1" newline rbitfld.long 0x8 19. "VGA_EN,VGA Enable. Modifies the response by the bridge to VGA compatible addresses. If the VGA Enable bit is set the bridge will positively decode and forward the following accesses on the primary interface to the secondary interface (and conversely.." "0,1" newline bitfld.long 0x8 18. "ISA_EN,ISA Enable. Modifies the response by the bridge to ISA I/O addresses. This applies only to I/O addresses that are enabled by the I/O Base and I/O Limit registers and are in the first 64 KB of I/O address space (0000 0000h to 0000 FFFFh). If this.." "?,KB block" newline bitfld.long 0x8 17. "SERR_EN,SERR# Enable. This bit controls forwarding of ERR_COR ERR_NONFATAL and ERR_FATAL from secondary to primary." "0,1" newline bitfld.long 0x8 16. "PERE,Parity Error Response Enable. This bit controls the logging of poisoned TLPs in the Master Data Parity Error bit in the Secondary Status register." "0,1" newline hexmask.long.byte 0x8 8.--15. 1. "INT_PIN,Interrupt PIN. The Interrupt Pin register register that identifies the legacy interrupt Message(s) the Function uses. Valid values are: - 01h 02h 03h and 04h: map to legacy interrupt Messages for INTA INTB INTC and INTD respectively. - 00h:.." newline hexmask.long.byte 0x8 0.--7. 1. "INT_LINE,Interrupt Line. The Interrupt Line register communicates interrupt line routing information. The register must be implemented by any Function that uses an interrupt pin. Values in this register are programmed by system software and are system.." tree.end tree "PF0_SPCIE_CAP (Secondary PCI Express Capability Structure)" group.long (0x0+0x1A0)++0xF line.long 0x0 "SPCIE_CAP_HEADER_REG,SPCIE Capability Header. For a description of this standard PCIe register. see the PCI Express Specification." hexmask.long.word 0x0 20.--31. 1. "NEXT_OFFSET,Next Capability Offset. For a description of this standard PCIe register field see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky).." hexmask.long.byte 0x0 16.--19. 1. "CAP_VERSION,Capability Version. For a description of this standard PCIe register field see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else.." hexmask.long.word 0x0 0.--15. 1. "EXTENDED_CAP_ID,Secondary PCI Express Extended Capability ID. For a description of this standard PCIe register field see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN.." line.long 0x4 "LINK_CONTROL3_REG,Link Control 3 Register. For a description of this standard PCIe register. see the PCI Express Specification." hexmask.long 0x4 2.--31. 1. "RSVDP_2,Reserved for future use." bitfld.long 0x4 1. "EQ_REQ_INT_EN,Link Equalization Request Interrupt Enable. For a description of this standard PCIe register field see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" "0,1" bitfld.long 0x4 0. "PERFORM_EQ,Perform Equalization. For a description of this standard PCIe register field see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" "0,1" line.long 0x8 "LANE_ERR_STATUS_REG,Lane Error Status Register. For a description of this standard PCIe register. see the PCI Express Specification." hexmask.long 0x8 1.--31. 1. "RSVDP_LANE_ERR_STATUS,Reserved for future use." bitfld.long 0x8 0. "LANE_ERR_STATUS,Lane Error Status Bits per Lane. For a description of this standard PCIe register field see the PCI Express Specification." "0,1" line.long 0xC "SPCIE_CAP_OFF_0CH_REG,Lane Equalization Control Register for lanes 1 and 0. For a description of this standard PCIe register. see the PCI Express Specification." rbitfld.long 0xC 31. "RSVDP_31,Reserved for future use." "0,1" rbitfld.long 0xC 23. "RSVDP_23,Reserved for future use." "0,1" rbitfld.long 0xC 15. "RSVDP_15,Reserved for future use." "0,1" bitfld.long 0xC 12.--14. "USP_RX_PRESET_HINT0,Upstream Port 8.0 GT/s Receiver Preset Hint 0. The write value is gated with the PCIE_CAP_CROSS_LINK_SUPPORT field of LINK_CAPABILITIES2_REG. For a description of this standard PCIe register field see the PCI Express Specification." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0xC 8.--11. 1. "USP_TX_PRESET0,Upstream Port 8.0 GT/s Transmitter Preset 0. The write value is gated with the PCIE_CAP_CROSS_LINK_SUPPORT field of LINK_CAPABILITIES2_REG. For a description of this standard PCIe register field see the PCI Express Specification. Note:.." rbitfld.long 0xC 7. "RSVDP_7,Reserved for future use." "0,1" bitfld.long 0xC 4.--6. "DSP_RX_PRESET_HINT0,Downstream Port 8.0 GT/s Receiver Preset Hint 0. For a description of this standard PCIe register field see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if.." "0,1,2,3,4,5,6,7" hexmask.long.byte 0xC 0.--3. 1. "DSP_TX_PRESET0,Downstream Port 8.0 GT/s Transmitter Preset 0. For a description of this standard PCIe register field see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN.." tree.end tree "PF0_L1SUB_CAP (L1 Substates Capability Structure)" group.long (0x0+0x2A0)++0xF line.long 0x0 "L1SUB_CAP_HEADER_REG,L1 Substates Extended Capability Header. This register provides capbility ID. capability version and next offset value for L1 Substates." hexmask.long.word 0x0 20.--31. 1. "NEXT_OFFSET,Next Capability Offset. This field contains the offset to the next PCI Express Capability structure or 000h if no other items exist in the linked list of Capabilities. For Extended Capabilities implemented in Configuration Space this offset.." hexmask.long.byte 0x0 16.--19. 1. "CAP_VERSION,Capability Version. This field is a PCI-SIG defined version number that indicates the version of the Capability structure present. This field is depends on version of the specification. Note: The access attributes of this field are as.." hexmask.long.word 0x0 0.--15. 1. "EXTENDED_CAP_ID,L1SUB Extended Capability ID. This field is a PCI-SIG defined ID number that indicates the nature and format of the Extended Capability. Extended Capability ID for L1 PM Substates is 001Eh. Note: The access attributes of this field are as.." line.long 0x4 "L1SUB_CAPABILITY_REG,L1 Substates Capability Register. This register provides extended capability of L1 Substates." hexmask.long.byte 0x4 24.--31. 1. "RSVDP_24,Reserved for future use." hexmask.long.byte 0x4 19.--23. 1. "PWR_ON_VALUE_SUPPORT,Port T Power On Value. Along with the Port T_POWER_ON Scale field in the L1 PM Substates Capabilities register sets the time (in us) that this Port requires the port on the opposite side of Link to wait in L1.2.Exit after sampling.." rbitfld.long 0x4 18. "RSVDP_18,Reserved for future use." "0,1" bitfld.long 0x4 16.--17. "PWR_ON_SCALE_SUPPORT,Port T Power On Scale. Specifies the scale used for the Port T_POWER_ON Value field in the L1 PM Substates Capabilities register. Range of values are given below. Required for all Ports for which either the PCI-PM L1.2 Supported bit.." "?,?,?,Reserved" newline hexmask.long.byte 0x4 8.--15. 1. "COMM_MODE_SUPPORT,Port Common Mode Restore Time. Time (in us) required for this Port to re-establish common mode. Required for all Ports for which either the PCI-PM L1.2 Supported bit is Set ASPM L1.2 Supported bit is Set or both are Set otherwise.." rbitfld.long 0x4 5.--7. "RSVDP_5,Reserved for future use." "0,1,2,3,4,5,6,7" bitfld.long 0x4 4. "L1_PMSUB_SUPPORT,L1 PM Substates ECN Supported. When Set this bit indicates that this Port supports L1 PM Substates. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W (sticky)" "0,1" bitfld.long 0x4 3. "L1_1_ASPM_SUPPORT,ASPM L11 Supported. When Set this bit indicates that ASPM L1.1 is supported. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W (sticky)" "0,1" newline bitfld.long 0x4 2. "L1_2_ASPM_SUPPORT,ASPM L12 Supported. When Set this bit indicates that ASPM L1.2 is supported. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W (sticky)" "0,1" bitfld.long 0x4 1. "L1_1_PCIPM_SUPPORT,PCI-PM L11 Supported. When Set this bit indicates that PCI-PM L1.1 is supported and must be Set by all Ports implementing L1 PM Substates. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W (sticky)" "0,1" bitfld.long 0x4 0. "L1_2_PCIPM_SUPPORT,PCI-PM L12 Supported. When Set this bit indicates that PCI-PM L1.2 is supported. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W (sticky)" "0,1" line.long 0x8 "L1SUB_CONTROL1_REG,L1 Substates Control 1 Register. This register provides Controls to extended capability." bitfld.long 0x8 29.--31. "L1_2_TH_SCA,LTR L12 Threshold Scale. This field provides a scale for the value contained within the LTR_L1.2_THRESHOLD_Value.The default value for this field is 000b.Hardware operation is undefined if software writes a Not-Permitted value to this field." "0,1,2,3,4,5,6,7" rbitfld.long 0x8 26.--28. "RSVDP_26,Reserved for future use." "0,1,2,3,4,5,6,7" hexmask.long.word 0x8 16.--25. 1. "L1_2_TH_VAL,LTR L12 Threshold Value. Along with the LTR_L1.2_THRESHOLD_Scale this field indicates the LTR threshold used to determine if entry into L1 results in L1.1 (if enabled) or L1.2 (if enabled). The default value for this field is 00 0000 0000b." hexmask.long.byte 0x8 8.--15. 1. "T_COMMON_MODE,Common Mode Restore Time. Sets value of TCOMMONMODE (in us) which must be used by the Downstream Ports for timing the re-establishment of common mode.This field is of type RsvdP for Upstream Ports. Default value is implementation.." newline hexmask.long.byte 0x8 4.--7. 1. "RSVDP_4,Reserved for future use." bitfld.long 0x8 3. "L1_1_ASPM_EN,ASPM L11 Enable. When Set this bit enables ASPM L1.1.For Ports for which the ASPM L1.1 Supported bit is Clear this bit is permitted to be hardwired to 0.Default value is 0b." "0,1" bitfld.long 0x8 2. "L1_2_ASPM_EN,ASPM L12 Enable. When Set this bit enables ASPM L1.2.For Ports for which the ASPM L1.2 Supported bit is Clear this bit is permitted to be hardwired to 0.Default value is 0b." "0,1" bitfld.long 0x8 1. "L1_1_PCIPM_EN,PCI-PM L11 Enable. When Set this bit enables PCI-PM L1.1. Default value is 0b." "0,1" newline bitfld.long 0x8 0. "L1_2_PCIPM_EN,PCI-PM L12 Enable. When Set this bit enables PCI-PM L1.2.For Ports for which the PCI-PM L1.2 Supported bit is Clear this bit is permitted to be hardwired to 0.Default value is 0b." "0,1" line.long 0xC "L1SUB_CONTROL2_REG,L1 Substates Control 2 Register. This register provides Controls to extended capability." hexmask.long.tbyte 0xC 8.--31. 1. "RSVDP_8,Reserved for future use." hexmask.long.byte 0xC 3.--7. 1. "T_POWER_ON_VALUE,T Power On Value. Along with the T_POWER_ON Scale sets the minimum amount of time (in us) that the Port must wait in L1.2.Exit after sampling CLKREQ# asserted before actively driving the interface.Default value is 00101b. T_POWER_ON is.." rbitfld.long 0xC 2. "RSVDP_2,Reserved for future use." "0,1" bitfld.long 0xC 0.--1. "T_POWER_ON_SCALE,T Power On Scale. Specifies the scale used for T_POWER_ON Value. Range of values are given below. Required for all Ports that support L1.2 otherwise this field is of type RsvdP. This field must only be modified when the ASPM L1.2 Enable.." "?,?,?,Reserved" tree.end tree "PF0_RAS_DES_CAP (RAS D.E.S. Capability Structure (VSEC))" group.long (0x0+0x30C)++0x3 line.long 0x0 "RAS_DES_CAP_HEADER_REG,Vendor-Specific Extended Capability Header. For a description of this standard PCIe register. see the PCI Express Specification." hexmask.long.word 0x0 20.--31. 1. "NEXT_OFFSET,Next Capability Offset. For a description of this standard PCIe register field see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky).." newline hexmask.long.byte 0x0 16.--19. 1. "CAP_VERSION,Capability Version. For a description of this standard PCIe register field see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else.." newline hexmask.long.word 0x0 0.--15. 1. "EXTENDED_CAP_ID,PCI Express Extended Capability ID. For a description of this standard PCIe register field see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then.." rgroup.long (0x4+0x30C)++0x3 line.long 0x0 "VENDOR_SPECIFIC_HEADER_REG,Vendor-Specific Header. For a description of this standard PCIe register. see the PCI Express Specification." hexmask.long.word 0x0 20.--31. 1. "VSEC_LENGTH,VSEC Length. For a description of this standard PCIe register field see the PCI Express Specification." newline hexmask.long.byte 0x0 16.--19. 1. "VSEC_REV,VSEC Rev. For a description of this standard PCIe register field see the PCI Express Specification." newline hexmask.long.word 0x0 0.--15. 1. "VSEC_ID,VSEC ID. For a description of this standard PCIe register field see the PCI Express Specification." group.long (0x8+0x30C)++0x3 line.long 0x0 "EVENT_COUNTER_CONTROL_REG,Event Counter Control. This is a viewport control register. - Setting the EVENT_COUNTER_EVENT_SELECT and EVENT_COUNTER_LANE_SELECT fields in this register determine the Event Counter data returned by the EVENT_COUNTER_DATA_REG.." hexmask.long.byte 0x0 28.--31. 1. "RSVDP_28,Reserved for future use." newline hexmask.long.word 0x0 16.--27. 1. "EVENT_COUNTER_EVENT_SELECT,Event Counter Data Select. This field in conjunction with the EVENT_COUNTER_LANE_SELECT field indexes the Event Counter data returned by the EVENT_COUNTER_DATA_REG register. - 27-24: Group number(4-bit: 0..0x7) - 23-16: Event.." newline hexmask.long.byte 0x0 12.--15. 1. "RSVDP_12,Reserved for future use." newline hexmask.long.byte 0x0 8.--11. 1. "EVENT_COUNTER_LANE_SELECT,Event Counter Lane Select. This field in conjunction with EVENT_COUNTER_EVENT_SELECT indexes the Event Counter data returned by the EVENT_COUNTER_DATA_REG register. - 0x0: Lane0 - 0x1: Lane1 - 0x2: Lane2 - .. - 0xF: Lane15 Note:.." newline rbitfld.long 0x0 7. "EVENT_COUNTER_STATUS,Event Counter Status. This register returns the current value of the Event Counter selected by the following fields: - EVENT_COUNTER_EVENT_SELECT - EVENT_COUNTER_LANE_SELECT Note: This register field is sticky." "0,1" newline rbitfld.long 0x0 5.--6. "RSVDP_5,Reserved for future use." "0,1,2,3" newline bitfld.long 0x0 2.--4. "EVENT_COUNTER_ENABLE,Event Counter Enable. Enables/disables the Event Counter selected by the EVENT_COUNTER_EVENT_SELECT and EVENT_COUNTER_LANE_SELECT fields in this register. By default all event counters are disabled. You can enable/disable a specific.." "no change,per event off,?,?,?,?,?,?" newline bitfld.long 0x0 0.--1. "EVENT_COUNTER_CLEAR,Event Counter Clear. Clears the Event Counter selected by the EVENT_COUNTER_EVENT_SELECT and EVENT_COUNTER_LANE_SELECT fields in this register. You can clear the value of a specific Event Counter by writing the 'per clear' code and.." "no change,per clear,?,?" rgroup.long (0xC+0x30C)++0x3 line.long 0x0 "EVENT_COUNTER_DATA_REG,Event Counter Data. This viewport register returns the data selected by the following fields: - EVENT_COUNTER_EVENT_SELECT in EVENT_COUNTER_CONTROL_REG - EVENT_COUNTER_LANE_SELECT in EVENT_COUNTER_CONTROL_REG For more details. see.." hexmask.long 0x0 0.--31. 1. "EVENT_COUNTER_DATA,Event Counter Data. This register returns the data selected by the following fields: - EVENT_COUNTER_EVENT_SELECT in EVENT_COUNTER_CONTROL_REG - EVENT_COUNTER_LANE_SELECT in EVENT_COUNTER_CONTROL_REG Note: This register field is sticky." group.long (0x10+0x30C)++0x3 line.long 0x0 "TIME_BASED_ANALYSIS_CONTROL_REG,Time-based Analysis Control. Used for controlling the measurement of RX/TX data throughput and time spent in each low-power LTSSM state. For more details. see the RAS DES section in the Core Operations chapter of the.." hexmask.long.byte 0x0 24.--31. 1. "TIME_BASED_REPORT_SELECT,Time-based Report Select. Selects what type of data is measured for the selected duration (TIME_BASED_DURATION_SELECT) and returned in TIME_BASED_ANALYSIS_DATA. Each type of data is measured using one of three types of units: -.." newline hexmask.long.byte 0x0 16.--23. 1. "RSVDP_16,Reserved for future use." newline hexmask.long.byte 0x0 8.--15. 1. "TIME_BASED_DURATION_SELECT,Time-based Duration Select. Selects the duration of time-based analysis. When 'manual control' is selected and TIMER_START is set to '1' this analysis never stops until TIMER_STOP is set to '0'. - 0x0: Manual control - 0x1:.." newline hexmask.long.byte 0x0 1.--7. 1. "RSVDP_1,Reserved for future use." newline bitfld.long 0x0 0. "TIMER_START,Timer Start. - 1: Start/Restart - 0: Stop This bit will be cleared automatically when the measurement is finished. Note: The app_ras_des_tba_ctrl input also sets the contents of this field and controls the measurement start/stop. Note: This.." "Stop,Start/Restart" rgroup.long (0x14+0x30C)++0x7 line.long 0x0 "TIME_BASED_ANALYSIS_DATA_REG,Time-based Analysis Data. Contains the measurement results of RX/TX data throughput and time spent in each low-power LTSSM state. This viewport register returns the data selected by the TIME_BASED_REPORT_SELECT field in.." hexmask.long 0x0 0.--31. 1. "TIME_BASED_ANALYSIS_DATA,Time Based Analysis Data. This register returns the data selected by the TIME_BASED_REPORT_SELECT field in TIME_BASED_ANALYSIS_CONTROL_REG. The results are cleared when next measurement starts. Note: This register field is sticky." line.long 0x4 "TIME_BASED_ANALYSIS_DATA_63_32_REG,Upper 32 bits of Time-based Analysis Data. This viewport register returns the data selected by the TIME_BASED_REPORT_SELECT field in TIME_BASED_ANALYSIS_CONTROL_REG. For more details. see the RAS DES section in the Core.." hexmask.long 0x4 0.--31. 1. "TIME_BASED_ANALYSIS_DATA_63_32,Upper 32 bits of Time Based Analysis Data. Note: This register field is sticky." group.long (0x30+0x30C)++0x5F line.long 0x0 "EINJ_ENABLE_REG,Error Injection Enable. Each type of error insertion is enabled by the corresponding bit in this register. The specific injection controls for each type of error are defined in the following registers: - 0: CRC Error: EINJ0_CRC_REG - 1:.." hexmask.long 0x0 7.--31. 1. "RSVDP_7,Reserved for future use." newline bitfld.long 0x0 6. "ERROR_INJECTION6_ENABLE,Error Injection6 Enable (Specific TLP Error). Enables insertion of errors into the packets that you select. You can set this bit to '1' when you have disabled RAS datapath protection (DP) by setting CX_RASDP = CX_RASDP_RAM_PROT.." "0,1" newline bitfld.long 0x0 5. "ERROR_INJECTION5_ENABLE,Error Injection5 Enable (TLP Duplicate/Nullify Error). Enables insertion of duplicate/nullified TLPs. For more details see the EINJ5_SP_TLP_REG register. Note: This register field is sticky." "0,1" newline bitfld.long 0x0 4. "ERROR_INJECTION4_ENABLE,Error Injection4 Enable (FC Credit Update Error). Enables insertion of errors into UpdateFCs. For more details see the EINJ4_FC_REG register. Note: This register field is sticky." "0,1" newline bitfld.long 0x0 3. "ERROR_INJECTION3_ENABLE,Error Injection3 Enable (Symbol DataK Mask Error or Sync Header Error). Enables DataK masking of special symbols or the breaking of the sync header. For more details see the EINJ3_SYMBOL_REG register. Note: This register field is.." "0,1" newline bitfld.long 0x0 2. "ERROR_INJECTION2_ENABLE,Error Injection2 Enable (DLLP Error). Enables insertion of DLLP errors. For more details see the EINJ2_DLLP_REG register. Note: This register field is sticky." "0,1" newline bitfld.long 0x0 1. "ERROR_INJECTION1_ENABLE,Error Injection1 Enable (Sequence Number Error). Enables insertion of errors into sequence numbers. For more details see the EINJ1_SEQNUM_REG register. Note: This register field is sticky." "0,1" newline bitfld.long 0x0 0. "ERROR_INJECTION0_ENABLE,Error Injection0 Enable (CRC Error). Enables insertion of errors into various CRC. For more details see the EINJ0_CRC_REG register. Note: This register field is sticky." "0,1" line.long 0x4 "EINJ0_CRC_REG,Error Injection Control 0 (CRC Error). Controls the insertion of errors into the CRC. and parity of ordered sets for the selected type of the packets as follows: - LCRC. Bad TLP will be detected at the receiver side; receiver responds with.." hexmask.long.tbyte 0x4 12.--31. 1. "RSVDP_12,Reserved for future use." newline hexmask.long.byte 0x4 8.--11. 1. "EINJ0_CRC_TYPE,Error injection type. Selects the type of CRC error to be inserted. Tx Path - 0000b: New TLP's LCRC error injection - 0001b: 16bCRC error injection of ACK/NAK DLLP - 0010b: 16bCRC error injection of Update-FC DLLP - 0011b: New TLP's ECRC.." newline hexmask.long.byte 0x4 0.--7. 1. "EINJ0_COUNT,Error injection count. Indicates the number of errors. This register is decremented when the errors have been inserted. - If the counter value is 0x01 and error is inserted ERROR_INJECTION0_ENABLE in EINJ_ENABLE_REG returns 0b. - If the.." line.long 0x8 "EINJ1_SEQNUM_REG,Error Injection Control 1 (Sequence Number Error). Controls the sequence number of the specific TLPs and ACK/NAK DLLPs. Data Link Protocol Error will be detected at the Rx side of ACK/NAL DLLPs when one of these conditions is true: -.." rbitfld.long 0x8 29.--31. "RSVDP_29,Reserved for future use." "0,1,2,3,4,5,6,7" newline hexmask.long.word 0x8 16.--28. 1. "EINJ1_BAD_SEQNUM,Bad sequence number. Indicates the value to add/subtract from the naturally-assigned sequence numbers. This value is represented by two's complement. - 0x0FFF: +4095 - .. - 0x0002: +2 - 0x0001: +1 - 0x0000: 0 - 0x1FFF: -1 - 0x1FFE: -2 -.." newline hexmask.long.byte 0x8 9.--15. 1. "RSVDP_9,Reserved for future use." newline bitfld.long 0x8 8. "EINJ1_SEQNUM_TYPE,Sequence number type. Selects the type of sequence number. - 0b: Insertion of New TLP's SEQ# error - 1b: Insertion of ACK/NAK DLLP's SEQ# Error Note: This register field is sticky." "0,1" newline hexmask.long.byte 0x8 0.--7. 1. "EINJ1_COUNT,Error injection count. Indicates the number of errors. This register is decremented as the errors are being inserted. - If the counter value is 0x01 and error is inserted ERROR_INJECTION1_ENABLE in EINJ_ENABLE_REG returns '0'. - If the.." line.long 0xC "EINJ2_DLLP_REG,Error Injection Control 2 (DLLP Error). Controls the transmission of DLLPs and inserts the following errors: - If 'ACK/NAK DLLP's transmission block' is selected. replay timeout error will occur at the transmitter of the TLPs and then Data.." hexmask.long.tbyte 0xC 10.--31. 1. "RSVDP_10,Reserved for future use." newline bitfld.long 0xC 8.--9. "EINJ2_DLLP_TYPE,DLLP Type. Selects the type of DLLP errors to be inserted. - 00b: ACK/NAK DLLP's transmission block - 01b: Update FC DLLP's transmission block - 10b: Always Transmission for NAK DLLP - 11b: Reserved Note: This register field is sticky." "0,1,2,3" newline hexmask.long.byte 0xC 0.--7. 1. "EINJ2_COUNT,Error injection count. Indicates the number of errors. This register is decremented as the errors are being inserted. - If the counter value is 0x01 and the error is inserted ERROR_INJECTION2_ENABLE in EINJ_ENABLE_REG returns '0'. - If the.." line.long 0x10 "EINJ3_SYMBOL_REG,Error Injection Control 3 (Symbol Error). When 8b/10b encoding is used. this register controls error insertion into the special (K code) symbols. - If TS1/TS2/FTS/E-Idle/SKP is selected. it affects whole of the ordered set. It might.." hexmask.long.tbyte 0x10 11.--31. 1. "RSVDP_11,Reserved for future use." newline bitfld.long 0x10 8.--10. "EINJ3_SYMBOL_TYPE,Error Type. 8b/10b encoding - Mask K symbol. It is not supported to insert errors into the first ordered-set after exiting from TxElecIdle when CX_FREQ_STEP_EN has been enabled. - 000b: Reserved - 001b: COM/PAD(TS1 Order set) - 010b:.." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x10 0.--7. 1. "EINJ3_COUNT,Error injection count. Indicates the number of errors. This register is decremented as the errors are being inserted. - If the counter value is 0x01 and error is inserted ERROR_INJECTION3_ENABLE in EINJ_ENABLE_REG returns '0'. - If the.." line.long 0x14 "EINJ4_FC_REG,Error Injection Control 4 (FC Credit Error). Controls error insertion into the credit value in the UpdateFCs. It is possible to insert errors for any of the following types: - Posted TLP Header credit - Non-Posted TLP Header credit -.." rbitfld.long 0x14 29.--31. "RSVDP_29,Reserved for future use." "0,1,2,3,4,5,6,7" newline hexmask.long.word 0x14 16.--28. 1. "EINJ4_BAD_UPDFC_VALUE,Bad update-FC credit value. Indicates the value to add/subtract from the UpdateFC credit. This value is represented by two's complement. - 0x0FFF: +4095 - .. - 0x0002: +2 - 0x0001: +1 - 0x0000: 0 - 0x1FFF: -1 - 0x1FFE: -2 - .. -.." newline rbitfld.long 0x14 15. "RSVDP_15,Reserved for future use." "0,1" newline bitfld.long 0x14 12.--14. "EINJ4_VC_NUMBER,VC Number. Indicates target VC Number. Note: This register field is sticky." "0,1,2,3,4,5,6,7" newline rbitfld.long 0x14 11. "RSVDP_11,Reserved for future use." "0,1" newline bitfld.long 0x14 8.--10. "EINJ4_UPDFC_TYPE,Update-FC type. Selects the credit type. - 000b: Posted TLP Header Credit value control - 001b: Non-Posted TLP Header Credit value control - 010b: Completion TLP Header Credit value control - 011b: Reserved - 100b: Posted TLP Data Credit.." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x14 0.--7. 1. "EINJ4_COUNT,Error injection count. Indicates the number of errors. This register is decremented as the errors are being inserted. - If the counter value is 0x01 and error is inserted ERROR_INJECTION4_ENABLE in EINJ_ENABLE_REG returns '0'. - If the.." line.long 0x18 "EINJ5_SP_TLP_REG,Error Injection Control 5 (Specific TLP Error). Controls the generation of specified TLPs. Correctable errors will occur which will be fixed by the PCIe protocol. - For Duplicate TLP. the controller initiates Data Link Retry by handling.." hexmask.long.tbyte 0x18 9.--31. 1. "RSVDP_9,Reserved for future use." newline bitfld.long 0x18 8. "EINJ5_SPECIFIED_TLP,Specified TLP. Selects the specified TLP to be inserted. - 0: Generates duplicate TLPs by handling ACK DLLP as NAK DLLP. - 1: Generates Nullified TLP (Original TLP will be stored in retry buffer). Note: This register field is sticky." "Generates duplicate TLPs by handling ACK DLLP as..,Generates Nullified TLP" newline hexmask.long.byte 0x18 0.--7. 1. "EINJ5_COUNT,Error injection count. Indicates the number of errors. This register is decremented as the errors are being inserted. - If the counter value is 0x01 and error is inserted ERROR_INJECTION5_ENABLE in EINJ_ENABLE_REG returns '0'. - If the.." line.long 0x1C "EINJ6_COMPARE_POINT_H0_REG,Error Injection Control 6 (Compare Point Header DWORD #0). Program this register for the 1st DWORD of TLP header/prefix. It is necessary to carefully consider the endianness when you program this register. Bits [31:0] =.." hexmask.long 0x1C 0.--31. 1. "EINJ6_COMPARE_POINT_H0,Packet Compare Point: 1st DWORD. Specifies which Tx TLP header DWORD#0 bits to compare with the corresponding bits in the Packet Compare Value registers (EINJ6_COMPARE_VALUE*). When all specified bits (in the Tx TLP header and.." line.long 0x20 "EINJ6_COMPARE_POINT_H1_REG,Error Injection Control 6 (Compare Point Header DWORD #1). Program this register for the 2nd DWORD of TLP header/prefix. It is necessary to carefully consider the endianness when you program this register. Bits [31:0] =.." hexmask.long 0x20 0.--31. 1. "EINJ6_COMPARE_POINT_H1,Packet Compare Point: 2nd DWORD. Specifies which Tx TLP header DWORD#1 bits to compare with the corresponding bits in the Packet Compare Value registers (EINJ6_COMPARE_VALUE*). When all specified bits (in the Tx TLP header and.." line.long 0x24 "EINJ6_COMPARE_POINT_H2_REG,Error Injection Control 6 (Compare Point Header DWORD #2). Program this register for the 3rd DWORD of TLP header/prefix. It is necessary to carefully consider the endianness when you program this register. Bits [31:0] =.." hexmask.long 0x24 0.--31. 1. "EINJ6_COMPARE_POINT_H2,Packet Compare Point: 3rd DWORD. Specifies which Tx TLP header DWORD#2 bits to compare with the corresponding bits in the Packet Compare Value registers (EINJ6_COMPARE_VALUE*). When all specified bits (in the Tx TLP header and.." line.long 0x28 "EINJ6_COMPARE_POINT_H3_REG,Error Injection Control 6 (Compare Point Header DWORD #3). Program this register for the 4th DWORD of TLP header/prefix. It is necessary to carefully consider the endianness when you program this register. Bits [31:0] =.." hexmask.long 0x28 0.--31. 1. "EINJ6_COMPARE_POINT_H3,Packet Compare Point: 4th DWORD. Specifies which Tx TLP header DWORD#3 bits to compare with the corresponding bits in the Packet Compare Value registers (EINJ6_COMPARE_VALUE*). When all specified bits (in the Tx TLP header and.." line.long 0x2C "EINJ6_COMPARE_VALUE_H0_REG,Error Injection Control 6 (Compare Value Header DWORD #0). Program this register for the 1st DWORD of TLP header/prefix. It is necessary to carefully consider the endianness when you program this register. Bits [31:0] =.." hexmask.long 0x2C 0.--31. 1. "EINJ6_COMPARE_VALUE_H0,Packet Compare Value: 1st DWORD. Specifies the value to compare against Tx the TLP header DWORD#0 bits specified in the Packet Compare Point registers (EINJ6_COMPARE_POINT*). Note: This register field is sticky." line.long 0x30 "EINJ6_COMPARE_VALUE_H1_REG,Error Injection Control 6 (Compare Value Header DWORD #1). Program this register for the 2nd DWORD of TLP header/prefix. It is necessary to carefully consider the endianness when you program this register. Bits [31:0] =.." hexmask.long 0x30 0.--31. 1. "EINJ6_COMPARE_VALUE_H1,Packet Compare Value: 2nd DWORD. Specifies the value to compare against Tx the TLP header DWORD#1 bits specified in the Packet Compare Point registers (EINJ6_COMPARE_POINT*). Note: This register field is sticky." line.long 0x34 "EINJ6_COMPARE_VALUE_H2_REG,Error Injection Control 6 (Compare Value Header DWORD #2). Program this register for the 3rd DWORD of TLP header/prefix. It is necessary to carefully consider the endianness when you program this register. Bits [31:0] =.." hexmask.long 0x34 0.--31. 1. "EINJ6_COMPARE_VALUE_H2,Packet Compare Value: 3rd DWORD. Specifies the value to compare against Tx the TLP header DWORD#2 bits specified in the Packet Compare Point registers (EINJ6_COMPARE_POINT*). Note: This register field is sticky." line.long 0x38 "EINJ6_COMPARE_VALUE_H3_REG,Error Injection Control 6 (Compare Value Header DWORD #3). Program this register for the 4th DWORD of TLP header/prefix. It is necessary to carefully consider the endianness when you program this register. Bits [31:0] =.." hexmask.long 0x38 0.--31. 1. "EINJ6_COMPARE_VALUE_H3,Packet Compare Value: 4th DWORD. Specifies the value to compare against Tx the TLP header DWORD#3 bits specified in the Packet Compare Point registers (EINJ6_COMPARE_POINT*). Note: This register field is sticky." line.long 0x3C "EINJ6_CHANGE_POINT_H0_REG,Error Injection Control 6 (Change Point Header DWORD #0). Program this register for the 1st DWORD of TLP header/prefix. It is necessary to carefully consider the endianness when you program this register. Bits [31:0] =.." hexmask.long 0x3C 0.--31. 1. "EINJ6_CHANGE_POINT_H0,Packet Change Point: 1st DWORD. Specifies which Tx TLP header DWORD#0 bits to replace with the corresponding bits in the Packet Change Value registers (EINJ6_CHANGE_VALUE*). Note: This register field is sticky." line.long 0x40 "EINJ6_CHANGE_POINT_H1_REG,Error Injection Control 6 (Change Point Header DWORD #1). Program this register for the 2nd DWORD of TLP header/prefix. It is necessary to carefully consider the endianness when you program this register. Bits [31:0] =.." hexmask.long 0x40 0.--31. 1. "EINJ6_CHANGE_POINT_H1,Packet Change Point: 2nd DWORD. Specifies which Tx TLP header DWORD#1 bits to replace with the corresponding bits in the Packet Change Value registers (EINJ6_CHANGE_VALUE*). Note: This register field is sticky." line.long 0x44 "EINJ6_CHANGE_POINT_H2_REG,Error Injection Control 6 (Change Point Header DWORD #2). Program this register for the 3rd DWORD of TLP header/prefix. It is necessary to carefully consider the endianness when you program this register. Bits [31:0] =.." hexmask.long 0x44 0.--31. 1. "EINJ6_CHANGE_POINT_H2,Packet Change Point: 3rd DWORD. Specifies which Tx TLP header DWORD#2 bits to replace with the corresponding bits in the Packet Change Value registers (EINJ6_CHANGE_VALUE*). Note: This register field is sticky." line.long 0x48 "EINJ6_CHANGE_POINT_H3_REG,Error Injection Control 6 (Change Point Header DWORD #3). Program this register for the 4th DWORD of TLP header/prefix. It is necessary to carefully consider the endianness when you program this register. Bits [31:0] =.." hexmask.long 0x48 0.--31. 1. "EINJ6_CHANGE_POINT_H3,Packet Change Point: 4th DWORD. Specifies which Tx TLP header DWORD#3 bits to replace with the corresponding bits in the Packet Change Value registers (EINJ6_CHANGE_VALUE*). Note: This register field is sticky." line.long 0x4C "EINJ6_CHANGE_VALUE_H0_REG,Error Injection Control 6 (Change Value Header DWORD #0). Program this register for the 1st DWORD of TLP header/prefix. It is necessary to carefully consider the endianness when you program this register. Bits [31:0] =.." hexmask.long 0x4C 0.--31. 1. "EINJ6_CHANGE_VALUE_H0,Packet Change Value: 1st DWORD. Specifies replacement values for the Tx TLP header DWORD#0 bits defined in the Packet Change Point registers (EINJ6_CHANGE_POINT*). Only applies when the EINJ6_INVERTED_CONTROL field in EINJ6_TLP_REG.." line.long 0x50 "EINJ6_CHANGE_VALUE_H1_REG,Error Injection Control 6 (Change Value Header DWORD #1). Program this register for the 2nd DWORD of TLP header/prefix. It is necessary to carefully consider the endianness when you program this register. Bits [31:0] =.." hexmask.long 0x50 0.--31. 1. "EINJ6_CHANGE_VALUE_H1,Packet Change Value: 2nd DWORD. Specifies replacement values for the Tx TLP header DWORD#1 bits defined in the Packet Change Point registers (EINJ6_CHANGE_POINT*). Only applies when the EINJ6_INVERTED_CONTROL field in EINJ6_TLP_REG.." line.long 0x54 "EINJ6_CHANGE_VALUE_H2_REG,Error Injection Control 6 (Change Value Header DWORD #2). Program this register for the 3rd DWORD of TLP header/prefix. It is necessary to carefully consider the endianness when you program this register. Bits [31:0] =.." hexmask.long 0x54 0.--31. 1. "EINJ6_CHANGE_VALUE_H2,Packet Change Value: 3rd DWORD. Specifies replacement values for the Tx TLP header DWORD#2 bits defined in the Packet Change Point registers (EINJ6_CHANGE_POINT*). Only applies when the EINJ6_INVERTED_CONTROL field in EINJ6_TLP_REG.." line.long 0x58 "EINJ6_CHANGE_VALUE_H3_REG,Error Injection Control 6 (Change Value Header DWORD #3). Program this register for the 4th DWORD of TLP header/prefix. It is necessary to carefully consider the endianness when you program this register. Bits [31:0] =.." hexmask.long 0x58 0.--31. 1. "EINJ6_CHANGE_VALUE_H3,Packet Change Value: 4th DWORD. Specifies replacement values for the Tx TLP header DWORD#3 bits defined in the Packet Change Point registers (EINJ6_CHANGE_POINT*). Only applies when the EINJ6_INVERTED_CONTROL field in EINJ6_TLP_REG.." line.long 0x5C "EINJ6_TLP_REG,Error Injection Control 6 (Packet Error). The Packet Compare Point registers (EINJ6_COMPARE_POINT*) specify which Tx TLP header bits to compare with the corresponding bits in the Packet Compare Value registers (EINJ6_COMPARE_VALUE*). When.." hexmask.long.tbyte 0x5C 12.--31. 1. "RSVDP_12,Reserved for future use." newline bitfld.long 0x5C 9.--11. "EINJ6_PACKET_TYPE,Packet type. Selects the TLP packets to inject errors into. - 0: TLP Header - 1: TLP Prefix 1st 4-DWORDs - 2: TLP Prefix 2nd -DWORDs - Else: Reserved Note: This register field is sticky." "TLP Header,TLP Prefix 1st 4-DWORDs,TLP Prefix 2nd -DWORDs,?,?,?,?,?" newline bitfld.long 0x5C 8. "EINJ6_INVERTED_CONTROL,Inverted Error Injection Control. - 0: EINJ6_CHANGE_VALUE_H[0/1/2/3] is used to replace bits specified by EINJ6_CHANGE_POINT_H[0/1/2/3]. - 1: EINJ6_CHANGE_VALUE_H[0/1/2/3] is ignored and inverts bits specified by.." "EINJ6_CHANGE_VALUE_H[0/1/2/3] is used to replace..,EINJ6_CHANGE_VALUE_H[0/1/2/3] is ignored and.." newline hexmask.long.byte 0x5C 0.--7. 1. "EINJ6_COUNT,Error Injection Count. Indicates the number of errors to insert. This counter is decremented while errors are been inserted. - If the counter value is 0x01 and error is inserted ERROR_INJECTION6_ENABLE in EINJ_ENABLE_REG returns '0'. - If.." group.long (0xA0+0x30C)++0x7 line.long 0x0 "SD_CONTROL1_REG,Silicon Debug Control 1. For more details. see the RAS DES section in the Core Operations chapter of the Databook." hexmask.long.byte 0x0 24.--31. 1. "RSVDP_24,Reserved for future use." newline bitfld.long 0x0 22.--23. "LOW_POWER_INTERVAL,Low Power Entry Interval Time. Interval Time that the controller starts monitoring RXELECIDLE signal after L0s/L1/L2 entry. You should set the value according to the latency from receiving EIOS to RXELECIDLE assertion at the PHY. -.." "0,1,2,3" newline bitfld.long 0x0 20.--21. "TX_EIOS_NUM,Number of Tx EIOS. This register sets the number of transmit EIOS for L0s/L1 entry and Disable/Loopback/Hot-reset exit. The controller selects the greater value between this register and the value defined by the PCI-SIG specification. 2.5GT/s.." "0,1,2,3" newline rbitfld.long 0x0 17.--19. "RSVDP_17,Reserved for future use." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 16. "FORCE_DETECT_LANE_EN,Force Detect Lane Enable. When this bit is set the controller ignores receiver detection from PHY during LTSSM Detect state and uses FORCE_DETECT_LANE. Note: This register field is sticky." "0,1" newline hexmask.long.word 0x0 0.--15. 1. "FORCE_DETECT_LANE,Force Detect Lane. When the FORCE_DETECT_LANE_EN field is set the controller ignores receiver detection from PHY during LTSSM Detect state and uses this value instead. - 0: Lane0 - 1: Lane1 - 2: Lane2 - .. - 15: Lane15 Note: This.." line.long 0x4 "SD_CONTROL2_REG,Silicon Debug Control 2. For more details. see the RAS DES section in the Core Operations chapter of the Databook." hexmask.long.word 0x4 17.--31. 1. "RSVDP_17,Reserved for future use." newline bitfld.long 0x4 16. "FRAMING_ERR_RECOVERY_DISABLE,Framing Error Recovery Disable. This bit disables a transition to Recovery state when a Framing Error is occurred. Note: This register field is sticky." "0,1" newline hexmask.long.byte 0x4 11.--15. 1. "RSVDP_11,Reserved for future use." newline bitfld.long 0x4 10. "DIRECT_LPBKSLV_TO_EXIT,Direct Loopback Slave To Exit. When this bit is set and the LTSSM is in Loopback Slave Active State the LTSSM transitions to Loopback Slave Exit state. Note: This register field is sticky." "0,1" newline bitfld.long 0x4 9. "DIRECT_POLCOMP_TO_DETECT,Direct Polling.Compliance to Detect. When this bit is set and the LTSSM is in Polling Compliance State the LTSSM transitions to Detect state. Note: This register field is sticky." "0,1" newline bitfld.long 0x4 8. "DIRECT_RECIDLE_TO_CONFIG,Direct Recovery.Idle to Configuration. When this bit is set and the LTSSM is in Recovery Idle State the LTSSM transitions to Configuration state. Note: This register field is sticky." "0,1" newline hexmask.long.byte 0x4 3.--7. 1. "RSVDP_3,Reserved for future use." newline bitfld.long 0x4 2. "NOACK_FORCE_LINKDOWN,Force LinkDown. When this bit is set and the controller detects REPLY_NUM rolling over 4 times the LTSSM transitions to Detect State. Note: This register field is sticky." "0,1" newline bitfld.long 0x4 1. "RECOVERY_REQUEST,Recovery Request. When this bit is set to '1' in L0 or L0s the LTSSM starts transitioning to Recovery State. This request does not cause a speed change or re-equalization." "0,1" newline bitfld.long 0x4 0. "HOLD_LTSSM,Hold and Release LTSSM. For as long as this register is '1' the controller stays in the current LTSSM. Note: This register field is sticky." "0,1" group.long (0xB0+0x30C)++0xB line.long 0x0 "SD_STATUS_L1LANE_REG,Silicon Debug Status(Layer1 Per-lane). This viewport register returns the data selected by the following field: - LANE_SELECT in SD_STATUS_L1LANE_REG For more details. see the RAS DES section in the Core Operations chapter of the.." hexmask.long.byte 0x0 24.--31. 1. "DESKEW_POINTER,Deskew Pointer. Indicates Deskew pointer of internal Deskew buffer of selected lane number(LANE_SELECT). Note: This register field is sticky." newline rbitfld.long 0x0 21.--23. "RSVDP_21,Reserved for future use." "0,1,2,3,4,5,6,7" newline rbitfld.long 0x0 20. "PIPE_TXELECIDLE,PIPE:TxElecIdle. Indicates PIPE TXELECIDLE signal of selected lane number(LANE_SELECT). Note: This register field is sticky." "0,1" newline rbitfld.long 0x0 19. "PIPE_RXELECIDLE,PIPE:RxElecIdle. Indicates PIPE RXELECIDLE signal of selected lane number(LANE_SELECT). Note: This register field is sticky." "0,1" newline rbitfld.long 0x0 18. "PIPE_RXVALID,PIPE:RxValid. Indicates PIPE RXVALID signal of selected lane number(LANE_SELECT). Note: This register field is sticky." "0,1" newline rbitfld.long 0x0 17. "PIPE_DETECT_LANE,PIPE:Detect Lane. Indicates whether PHY indicates receiver detection or not on selected lane number(LANE_SELECT). Note: This register field is sticky." "0,1" newline rbitfld.long 0x0 16. "PIPE_RXPOLARITY,PIPE:RxPolarity. Indicates PIPE RXPOLARITY signal of selected lane number(LANE_SELECT). Note: This register field is sticky." "0,1" newline hexmask.long.word 0x0 4.--15. 1. "RSVDP_4,Reserved for future use." newline hexmask.long.byte 0x0 0.--3. 1. "LANE_SELECT,Lane Select. Lane Select register for Silicon Debug Status Register of Layer1-PerLane. - 0x0: Lane0 - 0x1: Lane1 - 0x2: Lane2 - .. - 0xF: Lane15 Note: This register field is sticky." line.long 0x4 "SD_STATUS_L1LTSSM_REG,Silicon Debug Status(Layer1 LTSSM). For more details. see the RAS DES section in the Core Operations chapter of the Databook." hexmask.long.word 0x4 16.--31. 1. "LTSSM_VARIABLE,LTSSM Variable. Indicates internal LTSSM variables defined in the PCI Express Base Specification. C-PCIe Mode: - 0: directed_speed_change - 1: changed_speed_recovery - 2: successful_speed_negotiation - 3: upconfigure_capable; Set to '1' if.." newline rbitfld.long 0x4 15. "LANE_REVERSAL,Lane Reversal Operation. Receiver detected lane reversal. This field is only valid in the L0 LTSSM state. Note: This register field is sticky." "0,1" newline hexmask.long.byte 0x4 11.--14. 1. "RSVDP_11,Reserved for future use." newline rbitfld.long 0x4 8.--10. "PIPE_POWER_DOWN,PIPE:PowerDown. Indicates PIPE PowerDown signal. Note: This register field is sticky." "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 7. "FRAMING_ERR,Framing Error. Indicates Framing Error detection status." "0,1" newline hexmask.long.byte 0x4 0.--6. 1. "FRAMING_ERR_PTR,First Framing Error Pointer. Identifies the first Framing Error using the following encoding. The field contents are only valid value when FRAMING_ERR =1. Received Unexpected Framing Token - 01h: When non- STP/SDP/IDL Token was received.." line.long 0x8 "SD_STATUS_PM_REG,Silicon Debug Status(PM). For more details. see the RAS DES section in the Core Operations chapter of the Databook." hexmask.long.byte 0x8 24.--31. 1. "RSVDP_24,Reserved for future use." newline hexmask.long.byte 0x8 16.--23. 1. "LATCHED_NFTS,Latched N_FTS. Indicates the value of N_FTS in the received TS Ordered Sets from the Link Partner Note: This register field is sticky." newline rbitfld.long 0x8 13.--15. "L1SUB_STATE,L1Sub State. Indicates internal state machine of L1Sub state. - 0h: S_L1_U : idle state - 1h: S_L1_0 : wait for aux_clk_active - 2h: S_L1_0_WAIT4_ACK : wait for pclkack - 3h: S_L1_0_WAIT4_CLKREQ : wait for clkreq - 4h: S_L1_N_ENTRY : check.." "wait for aux_clk_active,?,?,?,?,?,?,?" newline bitfld.long 0x8 12. "PME_RESEND_FLAG,PME Re-send flag. When the DUT sends a PM_PME message TLP the DUT sets PME_Status bit. If host software does not clear PME_Status bit for 100ms(+50%/-5%) the DUT resends the PM_PME Message. This bit indicates that a PM_PME was resent." "0,1" newline hexmask.long.byte 0x8 8.--11. 1. "INTERNAL_PM_SSTATE,Internal PM State(Slave). Indicates internal state machine of Power Management Slave controller. - 0h: S_IDLE - 1h: S_RESPOND_NAK - 2h: S_BLOCK_TLP - 3h: S_WAIT_LAST_TLP_ACK - 4h: S_WAIT_EIDLE - 5h: S_LINK_ENTR_L1 - 6h: S_L1 - 7h:.." newline rbitfld.long 0x8 5.--7. "RSVDP_5,Reserved for future use." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x8 0.--4. 1. "INTERNAL_PM_MSTATE,Internal PM State(Master). Indicates internal state machine of Power Management Master controller. - 00h: IDLE - 01h: L0 - 02h: L0S - 03h: ENTER_L0S - 04h: L0S_EXIT - 05h: WAIT_PMCSR_CPL_SENT - 08h: L1 - 09h: L1_BLOCK_TLP - 0Ah:.." rgroup.long (0xBC+0x30C)++0x3 line.long 0x0 "SD_STATUS_L2_REG,Silicon Debug Status(Layer2). For more details. see the RAS DES section in the Core Operations chapter of the Databook." hexmask.long.byte 0x0 28.--31. 1. "RSVDP_28,Reserved for future use." newline bitfld.long 0x0 27. "FC_INIT2,FC_INIT2. Indicates the controller is in FC_INIT2(VC0) state. Note: This register field is sticky." "0,1" newline bitfld.long 0x0 26. "FC_INIT1,FC_INIT1. Indicates the controller is in FC_INIT1(VC0) state. Note: This register field is sticky." "0,1" newline bitfld.long 0x0 24.--25. "DLCMSM,DLCMSM. Indicates the current DLCMSM. - 00b: DL_INACTIVE - 01b: DL_FC_INIT - 11b: DL_ACTIVE Note: This register field is sticky." "0,1,2,3" newline hexmask.long.word 0x0 12.--23. 1. "RX_ACK_SEQ_NO,Tx Ack Sequence Number. Indicates ACKD_SEQ which is updated by receiving ACK/NAK DLLP. Note: This register field is sticky." newline hexmask.long.word 0x0 0.--11. 1. "TX_TLP_SEQ_NO,Tx Tlp Sequence Number. Indicates next transmit sequence number for transmit TLP. Note: This register field is sticky." group.long (0xC0+0x30C)++0x7 line.long 0x0 "SD_STATUS_L3FC_REG,Silicon Debug Status(Layer3 FC). The CREDIT_DATA[0/1] fields in this viewport register return the data for the VC and TLP Type selected by the following fields: - CREDIT_SEL_VC - CREDIT_SEL_CREDIT_TYPE - CREDIT_SEL_TLP_TYPE -.." hexmask.long.word 0x0 20.--31. 1. "CREDIT_DATA1,Credit Data1. Current FC credit data selected by the CREDIT_SEL_VC CREDIT_SEL_CREDIT_TYPE CREDIT_SEL_TLP_TYPE and CREDIT_SEL_HD viewport-select fields. - Rx: Credit Allocated Value - Tx: Credit Limit Value. This value is valid when.." newline hexmask.long.word 0x0 8.--19. 1. "CREDIT_DATA0,Credit Data0. Current FC credit data selected by the CREDIT_SEL_VC CREDIT_SEL_CREDIT_TYPE CREDIT_SEL_TLP_TYPE and CREDIT_SEL_HD viewport-select fields. - Rx: Credit Received Value - Tx: Credit Consumed Value Note: This register field is.." newline rbitfld.long 0x0 7. "RSVDP_7,Reserved for future use." "0,1" newline bitfld.long 0x0 6. "CREDIT_SEL_HD,Credit Select(HeaderData). This field in conjunction with the CREDIT_SEL_VC CREDIT_SEL_CREDIT_TYPE and CREDIT_SEL_TLP_TYPE viewport-select fields determines that data that is returned by the CREDIT_DATA0 and CREDIT_DATA1 data fields. -.." "Header Credit,Data Credit" newline bitfld.long 0x0 4.--5. "CREDIT_SEL_TLP_TYPE,Credit Select(TLP Type). This field in conjunction with the CREDIT_SEL_VC CREDIT_SEL_CREDIT_TYPE and CREDIT_SEL_HD viewport-select fields determines that data that is returned by the CREDIT_DATA0 and CREDIT_DATA1 data fields. - 0x0:.." "Posted,Non-Posted,Completion,?" newline bitfld.long 0x0 3. "CREDIT_SEL_CREDIT_TYPE,Credit Select(Credit Type). This field in conjunction with the CREDIT_SEL_VC CREDIT_SEL_TLP_TYPE and CREDIT_SEL_HD viewport-select fields determines that data that is returned by the CREDIT_DATA0 and CREDIT_DATA1 data fields. -.." "Rx,Tx" newline bitfld.long 0x0 0.--2. "CREDIT_SEL_VC,Credit Select(VC). This field in conjunction with the CREDIT_SEL_CREDIT_TYPE CREDIT_SEL_TLP_TYPE and CREDIT_SEL_HD viewport-select fields determines that data that is returned by the CREDIT_DATA0 and CREDIT_DATA1 data fields. - 0x0: VC0 -.." "VC0,VC1,VC2,?,?,?,?,VC7" line.long 0x4 "SD_STATUS_L3_REG,Silicon Debug Status(Layer3). For more details. see the RAS DES section in the Core Operations chapter of the Databook." hexmask.long.tbyte 0x4 8.--31. 1. "RSVDP_8,Reserved for future use." newline bitfld.long 0x4 7. "MFTLP_STATUS,Malformed TLP Status. Indicates malformed TLP has occurred." "0,1" newline hexmask.long.byte 0x4 0.--6. 1. "MFTLP_POINTER,First Malformed TLP Error Pointer. Indicates the element of the received first malformed TLP. This pointer is validated by MFTLP_STATUS. - 01h: AtomicOp address alignment - 02h: AtomicOp operand - 03h: AtomicOp byte enable - 04h: TLP length.." group.long (0xD0+0x30C)++0xB line.long 0x0 "SD_EQ_CONTROL1_REG,Silicon Debug EQ Control 1. This is a viewport control register. Setting the EQ_RATE_SEL and EQ_LANE_SEL fields in this register determine the per-lane Silicon Debug EQ Status data returned by the SD_EQ_STATUS[1/2/3] viewport.." hexmask.long.byte 0x0 24.--31. 1. "FOM_TARGET,FOM Target. Indicates figure of merit target criteria value of EQ Master(DSP in EQ Phase3/USP in EQ Phase2). This field is only valid when GEN3_EQ_FB_MODE is 0001b(Figure Of Merit). Note: This register field is sticky." newline bitfld.long 0x0 23. "FOM_TARGET_ENABLE,FOM Target Enable. Enables the FOM_TARGET fields. Note: This register field is sticky." "0,1" newline hexmask.long.byte 0x0 18.--22. 1. "RSVDP_18,Reserved for future use." newline bitfld.long 0x0 16.--17. "EVAL_INTERVAL_TIME,Eval Interval Time. Indicates interval time of RxEqEval assertion. - 00: 500ns - 01: 1us - 10: 2us - 11: 4us This field is used for EQ Master(DSP in EQ Phase3/USP in EQ Phase2). Note: This register field is sticky." "0,1,2,3" newline hexmask.long.byte 0x0 10.--15. 1. "RSVDP_10,Reserved for future use." newline bitfld.long 0x0 8.--9. "EXT_EQ_TIMEOUT,Extends EQ Phase2/3 Timeout. This field is used when the Ltssm is in Recovery.EQ2/3. When this field is set the value of EQ2/3 timeout is extended. EQ Master(DSP in EQ Phase3/USP in EQ Phase2). - 00: 24ms (default) - 01: 48ms (x2) - 10:.." "0,1,2,3" newline rbitfld.long 0x0 6.--7. "RSVDP_6,Reserved for future use." "0,1,2,3" newline bitfld.long 0x0 4.--5. "EQ_RATE_SEL,EQ Status Rate Select. Setting this field in conjunction with the EQ_LANE_SEL field determines the per-lane Silicon Debug EQ Status data returned by the SD_EQ_CONTROL[2/3] and SD_EQ_STATUS[1/2/3] viewport registers. - 0x0: 8.0GT/s Speed.." "0,1,2,3" newline hexmask.long.byte 0x0 0.--3. 1. "EQ_LANE_SEL,EQ Status Lane Select. Setting this field in conjunction with the EQ_RATE_SEL field determines the per-lane Silicon Debug EQ Status data returned by the SD_EQ_CONTROL[2/3] and SD_EQ_STATUS[1/2/3] viewport registers. - 0x0: Lane0 - 0x1: Lane1.." line.long 0x4 "SD_EQ_CONTROL2_REG,Silicon Debug EQ Control 2. This viewport register returns the value for the rate and lane selected by the EQ_RATE_SEL and EQ_LANE_SEL fields in the SD_EQ_CONTROL1_REG register. For more details. see the RAS DES section in the Core.." rbitfld.long 0x4 31. "RSVDP_31,Reserved for future use." "0,1" newline bitfld.long 0x4 30. "FORCE_LOCAL_TX_PRESET_ENABLE,Force Local Transmitter Preset Enable. Enables the FORCE_LOCAL_TX_PRESET field. If select rate in the EQ_RATE_SEL field is 32.0GT/s Speed this feature is not available. Note: This register field is sticky." "0,1" newline bitfld.long 0x4 29. "FORCE_LOCAL_RX_HINT_ENABLE,Force Local Receiver Preset Hint Enable. Enables the FORCE_LOCAL_RX_HINT field. If select rate in the EQ_RATE_SEL field is other than 8.0GT/s Speed this feature is not available. Note: This register field is sticky." "0,1" newline bitfld.long 0x4 28. "FORCE_LOCAL_TX_COEF_ENABLE,Force Local Transmitter Coefficient Enable. Enables the following fields: - FORCE_LOCAL_TX_PRE_CURSOR - FORCE_LOCAL_TX_CURSOR - FORCE_LOCAL_TX_POST_CURSOR Note: This register field is sticky." "0,1" newline hexmask.long.byte 0x4 24.--27. 1. "FORCE_LOCAL_TX_PRESET,Force Local Transmitter Preset. Indicates initial preset value of USP in EQ Slave(EQ Phase2) instead of receiving EQ TS2. If select rate in the EQ_RATE_SEL field is 32.0GT/s Speed this feature is not available. Note: This register.." newline rbitfld.long 0x4 21.--23. "RSVDP_21,Reserved for future use." "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 18.--20. "FORCE_LOCAL_RX_HINT,Force Local Receiver Preset Hint. Indicates the RxPresetHint value of EQ Slave(DSP in EQ Phase2/USP in EQ Phase3) instead of received or set value. If select rate in the EQ_RATE_SEL field is other than 8.0GT/s Speed this feature is.." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x4 12.--17. 1. "FORCE_LOCAL_TX_POST_CURSOR,Force Local Transmitter Post-Cursor. Indicates the coefficient value of EQ Slave(DSP in EQ Phase2/USP in EQ Phase3) instead of the value instructed from link partner. Note: This register field is sticky." newline hexmask.long.byte 0x4 6.--11. 1. "FORCE_LOCAL_TX_CURSOR,Force Local Transmitter Cursor. Indicates the coefficient value of EQ Slave(DSP in EQ Phase2/USP in EQ Phase3) instead of the value instructed from link partner. Note: This register field is sticky." newline hexmask.long.byte 0x4 0.--5. 1. "FORCE_LOCAL_TX_PRE_CURSOR,Force Local Transmitter Pre-cursor. Indicates the coefficient value of EQ Slave(DSP in EQ Phase2/USP in EQ Phase3) instead of the value instructed from link partner. Note: This register field is sticky." line.long 0x8 "SD_EQ_CONTROL3_REG,Silicon Debug EQ Control 3. This viewport register returns the value for the rate and lane selected by the EQ_RATE_SEL and EQ_LANE_SEL fields in the SD_EQ_CONTROL1_REG register. For more details. see the RAS DES section in the Core.." rbitfld.long 0x8 29.--31. "RSVDP_29,Reserved for future use." "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 28. "FORCE_REMOTE_TX_COEF_ENABLE,Force Remote Transmitter Coefficient Enable. Enables the following fields: - FORCE_REMOTE_TX_PRE_CURSOR - FORCE_REMOTE_TX_CURSOR - FORCE_REMOTE_TX_POST_CURSOR This function can only be used when GEN3_EQ_FB_MODE =.." "0,1" newline hexmask.long.word 0x8 18.--27. 1. "RSVDP_18,Reserved for future use." newline hexmask.long.byte 0x8 12.--17. 1. "FORCE_REMOTE_TX_POST_CURSOR,Force Remote Transmitter Post-Cursor. Indicates the coefficient value of EQ Master(DSP in EQ Phase3/USP in EQ Phase2) instead of the value instructed from local phy in dirchange mode. Note: This register field is sticky." newline hexmask.long.byte 0x8 6.--11. 1. "FORCE_REMOTE_TX_CURSOR,Force Remote Transmitter Cursor. Indicates the coefficient value of EQ Master(DSP in EQ Phase3/USP in EQ Phase2) instead of the value instructed from local phy in dirchange mode. Note: This register field is sticky." newline hexmask.long.byte 0x8 0.--5. 1. "FORCE_REMOTE_TX_PRE_CURSOR,Force Remote Transmitter Pre-Cursor. Indicates the coefficient value of EQ Master(DSP in EQ Phase3/USP in EQ Phase2) instead of the value instructed from local phy in dirchange mode. Note: This register field is sticky." rgroup.long (0xE0+0x30C)++0xB line.long 0x0 "SD_EQ_STATUS1_REG,Silicon Debug EQ Status 1. This viewport register returns the first of three words of Silicon Debug EQ Status data for the rate and lane selected by the EQ_RATE_SEL and EQ_LANE_SEL fields in the SD_EQ_CONTROL1_REG register. The.." hexmask.long.tbyte 0x0 8.--31. 1. "RSVDP_8,Reserved for future use." newline bitfld.long 0x0 7. "EQ_REJECT_EVENT,EQ Reject Event. Indicates that the controller receives two consecutive TS1 OS w/Reject=1b during EQ Master phase(DSP in EQ Phase3/USP in EQ Phase2). This bit is automatically cleared when the controller starts EQ Master phase again." "0,1" newline bitfld.long 0x0 6. "EQ_RULEC_VIOLATION,EQ Rule C Violation. Indicates that coefficients rule C violation is detected in the values provided by PHY using direction change method during EQ Master phase(DSP in EQ Phase3/USP in EQ Phase2). The coefficients rule C correspond to.." "0,1" newline bitfld.long 0x0 5. "EQ_RULEB_VIOLATION,EQ Rule B Violation. Indicates that coefficients rule B violation is detected in the values provided by PHY using direction change method during EQ Master phase(DSP in EQ Phase3/USP in EQ Phase2). The coefficients rules B correspond to.." "0,1" newline bitfld.long 0x0 4. "EQ_RULEA_VIOLATION,EQ Rule A Violation. Indicates that coefficients rule A violation is detected in the values provided by PHY using direction change method during EQ Master phase(DSP in EQ Phase3/USP in EQ Phase2). The coefficients rules A correspond to.." "0,1" newline bitfld.long 0x0 3. "RSVDP_3,Reserved for future use." "0,1" newline bitfld.long 0x0 1.--2. "EQ_CONVERGENCE_INFO,EQ Convergence Info. Indicates equalization convergence information. - 0x0: Equalization is not attempted - 0x1: Equalization finished successfully - 0x2: Equalization finished unsuccessfully - 0x3: Reserved This bit is automatically.." "Equalization is not attempted,Equalization finished successfully,Equalization finished unsuccessfully,Reserved" newline bitfld.long 0x0 0. "EQ_SEQUENCE,EQ Sequence. Indicates that the controller is starting the equalization sequence. Note: This register field is sticky." "0,1" line.long 0x4 "SD_EQ_STATUS2_REG,Silicon Debug EQ Status 2. This viewport register returns the second of three words of Silicon Debug EQ Status data for the rate and lane selected by the EQ_RATE_SEL and EQ_LANE_SEL fields in the SD_EQ_CONTROL1_REG register. Each field.." hexmask.long.byte 0x4 24.--31. 1. "EQ_LOCAL_FOM_VALUE,EQ Local Figure of Merit. Indicates Local maximum Figure of Merit value. Note: This register field is sticky." newline bitfld.long 0x4 21.--23. "RSVDP_21,Reserved for future use." "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 18.--20. "EQ_LOCAL_RX_HINT,EQ Local Receiver Preset Hint. Indicates Local Receiver Preset Hint value. If select rate in the EQ_RATE_SEL field is other than 8.0GT/s Speed this feature is not available. Note: This register field is sticky." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x4 12.--17. 1. "EQ_LOCAL_POST_CURSOR,EQ Local Post-Cursor. Indicates Local post cursor coefficient value. Note: This register field is sticky." newline hexmask.long.byte 0x4 6.--11. 1. "EQ_LOCAL_CURSOR,EQ Local Cursor. Indicates Local cursor coefficient value. Note: This register field is sticky." newline hexmask.long.byte 0x4 0.--5. 1. "EQ_LOCAL_PRE_CURSOR,EQ Local Pre-Cursor. Indicates Local pre cursor coefficient value. Note: This register field is sticky." line.long 0x8 "SD_EQ_STATUS3_REG,Silicon Debug EQ Status 3. This viewport register returns the third of three words of Silicon Debug EQ Status data for the rate and lane selected by the EQ_RATE_SEL and EQ_LANE_SEL fields in the SD_EQ_CONTROL1_REG register. Each field.." bitfld.long 0x8 30.--31. "RSVDP_30,Reserved for future use." "0,1,2,3" newline hexmask.long.byte 0x8 24.--29. 1. "EQ_REMOTE_FS,EQ Remote FS. Indicates Remote FS value. Note: This register field is sticky." newline hexmask.long.byte 0x8 18.--23. 1. "EQ_REMOTE_LF,EQ Remote LF. Indicates Remote LF value. Note: This register field is sticky." newline hexmask.long.byte 0x8 12.--17. 1. "EQ_REMOTE_POST_CURSOR,EQ Remote Post-Cursor. Indicates Remote post cursor coefficient value. Note: This register field is sticky." newline hexmask.long.byte 0x8 6.--11. 1. "EQ_REMOTE_CURSOR,EQ Remote Cursor. Indicates Remote cursor coefficient value. Note: This register field is sticky." newline hexmask.long.byte 0x8 0.--5. 1. "EQ_REMOTE_PRE_CURSOR,EQ Remote Pre-Cursor. Indicates Remote pre cursor coefficient value. Note: This register field is sticky." tree.end tree "PF0_SN_CAP (Device Serial Number Capability Structure)" group.long (0x0+0x170)++0xB line.long 0x0 "SN_BASE,Device Serial Number Extended Capability Header. For a description of this standard PCIe register. see the PCI Express Base Specification." hexmask.long.word 0x0 20.--31. 1. "SN_NEXT_OFFSET,Next Capability Offset. For a description of this standard PCIe register field see the PCI Express Base Specification. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then.." hexmask.long.byte 0x0 16.--19. 1. "SN_CAP_VERSION,Capability Version. For a description of this standard PCIe register field see the PCI Express Base Specification. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky).." hexmask.long.word 0x0 0.--15. 1. "SN_PCIE_EXTENDED_CAP_ID,Serial Number Extended Capability ID. For a description of this standard PCIe register field see the PCI Express Base Specification. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if.." line.long 0x4 "SER_NUM_REG_DW_1,Serial Number 1 Register. For a description of this standard PCIe register. see the PCI Express Base Specification." hexmask.long 0x4 0.--31. 1. "SN_SER_NUM_REG_1_DW,IEEE 64 bit Device Serial Number (DW 1). For a description of this standard PCIe register field see the PCI Express Base Specification. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if.." line.long 0x8 "SER_NUM_REG_DW_2,Serial Number 2 Register. For a description of this standard PCIe register. see the PCI Express Base Specification." hexmask.long 0x8 0.--31. 1. "SN_SER_NUM_REG_2_DW,IEEE 64 bit Device Serial Number (DW 2). For a description of this standard PCIe register field see the PCI Express Base Specification. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if.." tree.end tree "PF0_VSECRAS_CAP (PF RAS Datapath Protection Capability Structure (VSEC))" group.long (0x0+0x480)++0x3 line.long 0x0 "RASDP_EXT_CAP_HDR_OFF,PCIe Extended capability ID. Capability version and Next capability offset. For a description of this standard PCIe register. see the PCI Express Specification." hexmask.long.word 0x0 20.--31. 1. "NEXT_OFFSET,Next Capability Offset. For a description of this standard PCIe register see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else.." newline hexmask.long.byte 0x0 16.--19. 1. "CAP,Capability Version. For a description of this standard PCIe register see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note:.." newline hexmask.long.word 0x0 0.--15. 1. "ID,PCI Express Extended Capability ID. For a description of this standard PCIe register see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else.." rgroup.long (0x4+0x480)++0x3 line.long 0x0 "RASDP_VENDOR_SPECIFIC_HDR_OFF,Vendor Specific Header. For a description of this standard PCIe register. see the PCI Express Specification." hexmask.long.word 0x0 20.--31. 1. "VSEC_LENGTH,VSEC Length. For a description of this standard PCIe register see the PCI Express Specification. Note: This register field is sticky." newline hexmask.long.byte 0x0 16.--19. 1. "VSEC_REV,VSEC Rev. For a description of this standard PCIe register see the PCI Express Specification. Note: This register field is sticky." newline hexmask.long.word 0x0 0.--15. 1. "VSEC_ID,VSEC ID. For a description of this standard PCIe register see the PCI Express Specification. Note: This register field is sticky." group.long (0x8+0x480)++0x7 line.long 0x0 "RASDP_ERROR_PROT_CTRL_OFF,ECC error correction control. Allows you to disable ECC error correction for RAMs and datapath. When the AXI Bridge Module is implemented and the master / slave clocks are asynchronous to the PCIe native controller clock.." hexmask.long.byte 0x0 24.--31. 1. "RSVDP_24,Reserved for future use." newline bitfld.long 0x0 23. "ERROR_PROT_DISABLE_CXS_RX,Error correction disable for CXS Tx path (PCIe Rx path). Note: This register field is sticky." "0,1" newline bitfld.long 0x0 22. "ERROR_PROT_DISABLE_ADM_RX,Error correction disable for ADM Rx path. Note: This register field is sticky." "0,1" newline bitfld.long 0x0 21. "ERROR_PROT_DISABLE_LAYER3_RX,Error correction disable for layer 3 Rx path. Note: This register field is sticky." "0,1" newline bitfld.long 0x0 20. "ERROR_PROT_DISABLE_LAYER2_RX,Error correction disable for layer 2 Rx path. Note: This register field is sticky." "0,1" newline bitfld.long 0x0 19. "ERROR_PROT_DISABLE_DMA_READ,Error correction disable for DMA read engine. Note: This register field is sticky." "0,1" newline bitfld.long 0x0 18. "ERROR_PROT_DISABLE_AXI_BRIDGE_INBOUND_REQUEST,Error correction disable for AXI bridge inbound request path. Note: This register field is sticky." "0,1" newline bitfld.long 0x0 17. "ERROR_PROT_DISABLE_AXI_BRIDGE_INBOUND_COMPLETION,Error correction disable for AXI bridge inbound completion composer. Does not disable the error detection reporting for 1-bit and 2-bit ECC errors. Note: This register field is sticky." "?,bit and 2-bit ECC errors" newline bitfld.long 0x0 16. "ERROR_PROT_DISABLE_RX,Global error correction disable for all Rx layers. Note: This register field is sticky." "0,1" newline hexmask.long.byte 0x0 9.--15. 1. "RSVDP_9,Reserved for future use." newline bitfld.long 0x0 8. "ERROR_PROT_DISABLE_DTIM_TX,Error correction disable for DTIM Tx path. Note: This register field is sticky." "0,1" newline bitfld.long 0x0 7. "ERROR_PROT_DISABLE_CXS_TX,Error correction disable for CXS Rx path (PCIe Tx path). Note: This register field is sticky." "0,1" newline bitfld.long 0x0 6. "ERROR_PROT_DISABLE_ADM_TX,Error correction disable for Adm Tx path. Note: This register field is sticky." "0,1" newline bitfld.long 0x0 5. "ERROR_PROT_DISABLE_LAYER3_TX,Error correction disable for layer 3 Tx path. Note: This register field is sticky." "0,1" newline bitfld.long 0x0 4. "ERROR_PROT_DISABLE_LAYER2_TX,Error correction disable for layer 2 Tx path. Note: This register field is sticky." "0,1" newline bitfld.long 0x0 3. "ERROR_PROT_DISABLE_DMA_WRITE,Error correction disable for DMA write engine. Note: This register field is sticky." "0,1" newline bitfld.long 0x0 2. "ERROR_PROT_DISABLE_AXI_BRIDGE_OUTBOUND,Error correction disable for AXI bridge outbound request path. Note: This register field is sticky." "0,1" newline bitfld.long 0x0 1. "ERROR_PROT_DISABLE_AXI_BRIDGE_MASTER,Error correction disable for AXI bridge master completion buffer. Note: This register field is sticky." "0,1" newline bitfld.long 0x0 0. "ERROR_PROT_DISABLE_TX,Global error correction disable for all Tx layers. Does not disable the error detection reporting for 1-bit and 2-bit ECC errors. Note: This register field is sticky." "?,bit and 2-bit ECC errors" line.long 0x4 "RASDP_CORR_COUNTER_CTRL_OFF,Corrected error (1-bit ECC) counter selection and control. This is a viewport control register. Setting the CORR_COUNTER_SELECTION_REGION and CORR_COUNTER_SELECTION fields in this register determine the counter data returned.." hexmask.long.byte 0x4 24.--31. 1. "CORR_COUNTER_SELECTION,Counter selection. This field selects the counter ID (within the region defined by CORR_COUNTER_SELECTION_REGION) whose contents can be read from the RASDP_CORR_COUNT_REPORT_OFF register. You can cycle this field value from 0 to.." newline hexmask.long.byte 0x4 20.--23. 1. "CORR_COUNTER_SELECTION_REGION,Select correctable counter region: - 0x0: Region select for Adm Rx path - 0x1: Region select for layer 3 Rx path - 0x2: Region select for layer 2 Rx path - 0x3: Region select for DMA inbound path - 0x4: Region select for AXI.." newline hexmask.long.word 0x4 5.--19. 1. "RSVDP_5,Reserved for future use." newline bitfld.long 0x4 4. "CORR_EN_COUNTERS,Enable correctable errors counters. - 1: counters increment when the controller detects a correctable error - 0: counters are frozen The counters are enabled by default." "counters are frozen,counters increment when the controller detects a.." newline rbitfld.long 0x4 1.--3. "RSVDP_1,Reserved for future use." "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 0. "CORR_CLEAR_COUNTERS,Clear all correctable error counters." "0,1" rgroup.long (0x10+0x480)++0x3 line.long 0x0 "RASDP_CORR_COUNT_REPORT_OFF,Corrected error (1-bit ECC) counter data. This viewport register returns the counter data selected by the CORR_COUNTER_SELECTION_REGION and CORR_COUNTER_SELECTION fields in the RASDP_CORR_COUNTER_CTRL_OFF register." hexmask.long.byte 0x0 24.--31. 1. "CORR_COUNTER_SELECTED,Counter selection. Returns the value set in the CORR_COUNTER_SELECTION field of the RASDP_CORR_COUNTER_CTRL_OFF register." newline hexmask.long.byte 0x0 20.--23. 1. "CORR_COUNTER_SELECTED_REGION,Selected correctable counter region: - 0x0: Region select for Adm Rx path - 0x1: Region select for layer 3 Rx path - 0x2: Region select for layer 2 Rx path - 0x3: Region select for DMA inbound path - 0x4: Region select for.." newline hexmask.long.word 0x0 8.--19. 1. "RSVDP_8,Reserved for future use." newline hexmask.long.byte 0x0 0.--7. 1. "CORR_COUNTER,Current corrected error count for the selected counter." group.long (0x14+0x480)++0x3 line.long 0x0 "RASDP_UNCORR_COUNTER_CTRL_OFF,Uncorrected error (2-bit ECC and parity) counter selection and control. This is a viewport control register. Setting the UNCORR_COUNTER_SELECTION_REGION and UNCORR_COUNTER_SELECTION fields in this register determine the.." hexmask.long.byte 0x0 24.--31. 1. "UNCORR_COUNTER_SELECTION,Counter selection. This field selects the counter ID (within the region defined by UNCORR_COUNTER_SELECTION_REGION) whose contents can be read from the RASDP_UNCORR_COUNT_REPORT_OFF register. You can cycle this field value from 0.." newline hexmask.long.byte 0x0 20.--23. 1. "UNCORR_COUNTER_SELECTION_REGION,Select uncorrectable counter region: - 0x0: Region select for Adm Rx path - 0x1: Region select for layer 3 Rx path - 0x2: Region select for layer 2 Rx path - 0x3: Region select for DMA inbound path - 0x4: Region select for.." newline hexmask.long.word 0x0 5.--19. 1. "RSVDP_5,Reserved for future use." newline bitfld.long 0x0 4. "UNCORR_EN_COUNTERS,Enable uncorrectable errors counters. - 1: enables the counters to increment on detected correctable errors - 0: counters are frozen The counters are enabled by default." "counters are frozen,enables the counters to increment on detected.." newline rbitfld.long 0x0 1.--3. "RSVDP_1,Reserved for future use." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 0. "UNCORR_CLEAR_COUNTERS,Clear uncorrectable errors counters. When asserted causes all counters tracking the uncorrectable errors to be cleared." "0,1" rgroup.long (0x18+0x480)++0x3 line.long 0x0 "RASDP_UNCORR_COUNT_REPORT_OFF,Uncorrected error (2-bit ECC and parity) counter data. This viewport register returns the counter data selected by the UNCORR_COUNTER_SELECTION_REGION and UNCORR_COUNTER_SELECTION fields in the RASDP_UNCORR_COUNTER_CTRL_OFF.." hexmask.long.byte 0x0 24.--31. 1. "UNCORR_COUNTER_SELECTED,Counter selection. Returns the value set in the UNCORR_COUNTER_SELECTION field of the RASDP_UNCORR_COUNTER_CTRL_OFF register." newline hexmask.long.byte 0x0 20.--23. 1. "UNCORR_COUNTER_SELECTED_REGION,Selected uncorrectable counter region: - 0x0: Region select for Adm Rx path - 0x1: Region select for layer 3 Rx path - 0x2: Region select for layer 2 Rx path - 0x3: Region select for DMA inbound path - 0x4: Region select.." newline hexmask.long.word 0x0 8.--19. 1. "RSVDP_8,Reserved for future use." newline hexmask.long.byte 0x0 0.--7. 1. "UNCORR_COUNTER,Current uncorrected error count for the selected counter" group.long (0x1C+0x480)++0x3 line.long 0x0 "RASDP_ERROR_INJ_CTRL_OFF,Error injection control for the following features: - 1-bit or 2-bit injection - Continuous or fixed-number (n) injection modes - Global enable/disable - Selectable location where injection occurs" hexmask.long.byte 0x0 24.--31. 1. "RSVDP_24,Reserved for future use." newline hexmask.long.byte 0x0 16.--23. 1. "ERROR_INJ_LOC,Error injection location. Selects where error injection takes place. You can cycle this field value from 0 to 255 to access all locations according to the detailed report of check points at.." newline hexmask.long.byte 0x0 8.--15. 1. "ERROR_INJ_COUNT,Error injection count. - 0: errors are inserted in every TLP until you clear ERROR_INJ_EN. - 1: one errors injected - 2: two errors injected - n: amount of errors injected" newline rbitfld.long 0x0 6.--7. "RSVDP_6,Reserved for future use." "0,1,2,3" newline bitfld.long 0x0 4.--5. "ERROR_INJ_TYPE,Error injection type: - 0: none - 1: 1-bit - 2: 2-bit" "none,bit,bit,?" newline rbitfld.long 0x0 1.--3. "RSVDP_1,Reserved for future use." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 0. "ERROR_INJ_EN,Error injection global enable. When set enables the error insertion logic." "0,1" rgroup.long (0x20+0x480)++0x7 line.long 0x0 "RASDP_CORR_ERROR_LOCATION_OFF,Corrected errors locations. For more details. see the RAS Data Protection (DP) section in the Core Operations chapter of the Databook." hexmask.long.byte 0x0 24.--31. 1. "LOC_LAST_CORR_ERROR,Location/ID of the last corrected error within the region defined by REG_LAST_CORR_ERROR. You can cycle this field value from 0 to 255 to access all counters according to the detailed report of check points at.." newline hexmask.long.byte 0x0 20.--23. 1. "REG_LAST_CORR_ERROR,Region of the last corrected error: - 0x0: Region select for Adm Rx path - 0x1: Region select for layer 3 Rx path - 0x2: Region select for layer 2 Rx path - 0x3: Region select for DMA inbound path - 0x4: Region select for AXI bridge.." newline hexmask.long.byte 0x0 16.--19. 1. "RSVDP_16,Reserved for future use." newline hexmask.long.byte 0x0 8.--15. 1. "LOC_FIRST_CORR_ERROR,Location/ID of the first corrected error within the region defined by REG_FIRST_CORR_ERROR. You can cycle this field value from 0 to 255 to access all counters according to the detailed report of check points at.." newline hexmask.long.byte 0x0 4.--7. 1. "REG_FIRST_CORR_ERROR,Region of the first corrected error: - 0x0: Region select for Adm Rx path - 0x1: Region select for layer 3 Rx path - 0x2: Region select for layer 2 Rx path - 0x3: Region select for DMA inbound path - 0x4: Region select for AXI bridge.." newline hexmask.long.byte 0x0 0.--3. 1. "RSVDP_0,Reserved for future use." line.long 0x4 "RASDP_UNCORR_ERROR_LOCATION_OFF,Uncorrected errors locations. For more details. see the RAS Data Protection (DP) section in the Core Operations chapter of the Databook." hexmask.long.byte 0x4 24.--31. 1. "LOC_LAST_UNCORR_ERROR,Location/ID of the last uncorrected error within the region defined by REG_LAST_UNCORR_ERROR. You can cycle this field value from 0 to 255 to access all counters according to the detailed report of check points at.." newline hexmask.long.byte 0x4 20.--23. 1. "REG_LAST_UNCORR_ERROR,Region of the last uncorrected error: - 0x0: Region select for Adm Rx path - 0x1: Region select for layer 3 Rx path - 0x2: Region select for layer 2 Rx path - 0x3: Region select for DMA inbound path - 0x4: Region select for AXI.." newline hexmask.long.byte 0x4 16.--19. 1. "RSVDP_16,Reserved for future use." newline hexmask.long.byte 0x4 8.--15. 1. "LOC_FIRST_UNCORR_ERROR,Location/ID of the first uncorrected error within the region defined by REG_FIRST_UNCORR_ERROR. You can cycle this field value from 0 to 255 to access all counters according to the detailed report of check points at.." newline hexmask.long.byte 0x4 4.--7. 1. "REG_FIRST_UNCORR_ERROR,Region of the first uncorrected error: - 0x0: Region select for Adm Rx path - 0x1: Region select for layer 3 Rx path - 0x2: Region select for layer 2 Rx path - 0x3: Region select for DMA inbound path - 0x4: Region select for AXI.." newline hexmask.long.byte 0x4 0.--3. 1. "RSVDP_0,Reserved for future use." group.long (0x28+0x480)++0x7 line.long 0x0 "RASDP_ERROR_MODE_EN_OFF,RASDP error mode enable. The controller enters RASDP error mode (if ERROR_MODE_EN =1) upon detection of the first uncorrectable error. During this mode: - Rx TLPs that are forwarded to your application are not guaranteed to be.." hexmask.long 0x0 2.--31. 1. "RSVDP_2,Reserved for future use." newline bitfld.long 0x0 1. "AUTO_LINK_DOWN_EN,Write '1' to enable the controller to bring the link down when the controller enters RASDP error mode. Note: This register field is sticky." "0,1" newline bitfld.long 0x0 0. "ERROR_MODE_EN,Write '1' to enable the controller enter RASDP error mode when it detects an uncorrectable error. Note: This register field is sticky." "0,1" line.long 0x4 "RASDP_ERROR_MODE_CLEAR_OFF,Exit RASDP error mode. For more details. see the RAS Data Protection (DP) section in the Core Operations chapter of the Databook." hexmask.long 0x4 1.--31. 1. "RSVDP_1,Reserved for future use." newline bitfld.long 0x4 0. "ERROR_MODE_CLEAR,Write '1' to take the controller out of RASDP error mode. The controller will then report uncorrectable errors (through AER internal error reporting) and also stop nullifying/discarding TLPs." "0,1" rgroup.long (0x30+0x480)++0x7 line.long 0x0 "RASDP_RAM_ADDR_CORR_ERROR_OFF,RAM Address where a corrected error (1-bit ECC) has been detected. For more details. see the RAS Data Protection (DP) section in the Core Operations chapter of the Databook." hexmask.long.byte 0x0 28.--31. 1. "RAM_INDEX_CORR_ERROR,RAM index where a corrected error (1-bit ECC) has been detected." newline bitfld.long 0x0 27. "RSVDP_27,Reserved for future use." "0,1" newline hexmask.long 0x0 0.--26. 1. "RAM_ADDR_CORR_ERROR,RAM Address where a corrected error (1-bit ECC) has been detected." line.long 0x4 "RASDP_RAM_ADDR_UNCORR_ERROR_OFF,RAM Address where an uncorrected error (2-bit ECC) has been detected. For more details. see the RAS Data Protection (DP) section in the Core Operations chapter of the Databook." hexmask.long.byte 0x4 28.--31. 1. "RAM_INDEX_UNCORR_ERROR,RAM index where an uncorrected error (2-bit ECC) has been detected." newline bitfld.long 0x4 27. "RSVDP_27,Reserved for future use." "0,1" newline hexmask.long 0x4 0.--26. 1. "RAM_ADDR_UNCORR_ERROR,RAM Address where an uncorrected error (2-bit ECC) has been detected." tree.end tree "PF0_RTR_CAP (PF RTR Capability Structure)" group.long (0x0+0x2F8)++0xB line.long 0x0 "RTR_EXT_CAP_HDR_OFF,Readiness Time Reporting PCI Express Extended Capability Header. For a description of this standard PCIe register. see the PCI Express Specification." hexmask.long.word 0x0 20.--31. 1. "RTR_NEXT_OFFSET,Next Capability Offset. For a description of this standard PCIe register field see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky).." hexmask.long.byte 0x0 16.--19. 1. "RTR_CAP_VERSION,Capability Version. For a description of this standard PCIe register field see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky).." hexmask.long.word 0x0 0.--15. 1. "RTR_EXT_CAP_ID,PCI Express Extended Capability ID. For a description of this standard PCIe register field see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then.." line.long 0x4 "READI_TIME_REPORTING1_OFF,Readiness Time Reporting 1. For a description of this standard PCIe register. see the PCI Express Specification." bitfld.long 0x4 31. "RTR_TIME_VALID,Valid. For a description of this standard PCIe register field see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky)" "0,1" hexmask.long.byte 0x4 24.--30. 1. "RSVDP_24,Reserved for future use." hexmask.long.word 0x4 12.--23. 1. "DL_UP_TIME,DL_UP Time. For a description of this standard PCIe register field see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky)" hexmask.long.word 0x4 0.--11. 1. "RESET_TIME,Reset Time. For a description of this standard PCIe register field see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky)" line.long 0x8 "READI_TIME_REPORTING2_OFF,Readiness Time Reporting 2. For a description of this standard PCIe register. see the PCI Express Specification." hexmask.long.byte 0x8 24.--31. 1. "RSVDP_24,Reserved for future use." hexmask.long.word 0x8 12.--23. 1. "D3HOT_D0_TIME,D3hot to D0 Time. For a description of this standard PCIe register field see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else.." hexmask.long.word 0x8 0.--11. 1. "FLR_TIME,FLR Time. For a description of this standard PCIe register field see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky)" tree.end tree "PF0_RTR_CAP_DBI2 (DBI2 Shadow Block: PF RTR Capability Structure)" rgroup.long (0x4+0x12F8)++0x7 line.long 0x0 "SHADOW_READI_TIME_REPORTING1_OFF,Shadow Register Readiness Time Reporting 1. For a description of this standard PCIe register. see the PCI Express Specification." bitfld.long 0x0 31. "RTR_TIME_VALID,Shadow Valid in the shadow register. For a description of this standard PCIe register field see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access - Dbi: No access - Dbi2: if.." "0,1" hexmask.long.tbyte 0x0 12.--30. 1. "RSVDP_12,Reserved for future use." hexmask.long.word 0x0 0.--11. 1. "RESET_TIME,Shadow Reset Time in the shadow register. For a description of this standard PCIe register field see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access - Dbi: No access - Dbi2: if.." line.long 0x4 "SHADOW_READI_TIME_REPORTING2_OFF,Shadow Register Readiness Time Reporting 2. For a description of this standard PCIe register. see the PCI Express Specification." hexmask.long.byte 0x4 24.--31. 1. "RSVDP_24,Reserved for future use." hexmask.long.word 0x4 12.--23. 1. "D3HOT_D0_TIME,Shadow D3hot to D0 Time in the shadow register. For a description of this standard PCIe register field see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access - Dbi: No access - Dbi2:.." hexmask.long.word 0x4 0.--11. 1. "FLR_TIME,Shadow FLR Time in the shadow register. For a description of this standard PCIe register field see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access - Dbi: No access - Dbi2: if.." tree.end tree "PF0_FRSQ_CAP (PF FRSQ Capability Structure)" group.long (0x0+0x2E8)++0xB line.long 0x0 "FRSQ_EXT_CAP_HDR_OFF,FRS Queuing Extended Capability Header. For a description of this standard PCIe register. see the PCI Express Specification." hexmask.long.word 0x0 20.--31. 1. "FRSQ_NEXT_OFFSET,Next Capability Offset. For a description of this standard PCIe register field see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then.." hexmask.long.byte 0x0 16.--19. 1. "FRSQ_CAP_VERSION,Capability Version. For a description of this standard PCIe register field see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky).." hexmask.long.word 0x0 0.--15. 1. "FRSQ_EXT_CAP_ID,PCI Express Extended Capability ID. For a description of this standard PCIe register field see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then.." line.long 0x4 "FRSQ_CAP_OFF,FRS Queuing Capability Register. For a description of this standard PCIe register. see the PCI Express Specification." hexmask.long.word 0x4 21.--31. 1. "RSVDP_21,Reserved for future use." hexmask.long.byte 0x4 16.--20. 1. "FRS_INT_MESSAGE_NUMBER,FRS Interrupt Message Number. For a description of this standard PCIe register field see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1).." hexmask.long.byte 0x4 12.--15. 1. "RSVDP_12,Reserved for future use." hexmask.long.word 0x4 0.--11. 1. "FRSQ_MAX_DEPTH,FRS Queue Max Depth. For a description of this standard PCIe register field see the PCI Express Specification." line.long 0x8 "FRSQ_CONTROL_FRSQ_STATUS_OFF,FRS Queuing Status and Control Register. For a description of this standard PCIe register. see the PCI Express Specification." hexmask.long.word 0x8 17.--31. 1. "RSVDP_17,Reserved for future use." bitfld.long 0x8 16. "FRS_INTERRUPT_ENABLE,FRS Interrupt Enable. For a description of this standard PCIe register field see the PCI Express Specification." "0,1" hexmask.long.word 0x8 2.--15. 1. "RSVDP_2,Reserved for future use." bitfld.long 0x8 1. "FRS_MESSAGE_OVERFLOW,FRS Message Overflow. For a description of this standard PCIe register field see the PCI Express Specification." "0,1" newline bitfld.long 0x8 0. "FRS_MESSAGE_RECEIVED,FRS Message Received. For a description of this standard PCIe register field see the PCI Express Specification." "0,1" rgroup.long (0xC+0x2E8)++0x3 line.long 0x0 "FRS_MESSAGE_QUEUE_OFF,FRS Message Queue Register. For a description of this standard PCIe register. see the PCI Express Specification." hexmask.long.word 0x0 20.--31. 1. "FRS_MESSAGE_QUE_DEPTH,FRS Message Queue Depth. For a description of this standard PCIe register field see the PCI Express Specification." hexmask.long.byte 0x0 16.--19. 1. "FRS_MESSAGE_QUE_REASON,FRS Message Queue Reason. For a description of this standard PCIe register field see the PCI Express Specification." hexmask.long.word 0x0 0.--15. 1. "FRS_MESSAGE_QUE_FUNC_ID,FRS Message Queue Function ID. For a description of this standard PCIe register field see the PCI Express Specification." tree.end tree "PF0_PTM_CAP (PF PTM Capability Structure)" group.long (0x0+0x40C)++0xB line.long 0x0 "PTM_EXT_CAP_HDR_OFF,Precision Time Measurement Capability Header. For a description of this standard PCIe register. see the PCI Express Specification." hexmask.long.word 0x0 20.--31. 1. "PTM_NEXT_OFFSET,Precision Time Measurement PCI Express Extended Capability Next Offset. For a description of this standard PCIe register see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access. -.." hexmask.long.byte 0x0 16.--19. 1. "PTM_CAP_VERSION,Precision Time Measurement PCI Express Extended Capability Version. For a description of this standard PCIe register see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi:.." hexmask.long.word 0x0 0.--15. 1. "PTM_CAP_ID,Precision Time Measurement PCI Express Extended Capability ID. For a description of this standard PCIe register see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if.." line.long 0x4 "PTM_CAP_OFF,PTM Capability Register. For a description of this standard PCIe register. see the PCI Express Specification." hexmask.long.word 0x4 16.--31. 1. "RSVDP_16,Reserved for future use." hexmask.long.byte 0x4 8.--15. 1. "PTM_CLK_GRAN,PTM Local Clock Granularity. For a description of this standard PCIe register see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky).." hexmask.long.byte 0x4 3.--7. 1. "RSVDP_3,Reserved for future use." bitfld.long 0x4 2. "PTM_ROOT_CAPABLE,PTM Root Capable. For a description of this standard PCIe register see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else.." "0,1" bitfld.long 0x4 1. "PTM_RES_CAPABLE,PTM Responder Capable. For a description of this standard PCIe register see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else.." "0,1" newline bitfld.long 0x4 0. "PTM_REQ_CAPABLE,PTM Requester Capable. For a description of this standard PCIe register see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else.." "0,1" line.long 0x8 "PTM_CONTROL_OFF,PTM Control Register. For a description of this standard PCIe register. see the PCI Express Specification." hexmask.long.word 0x8 16.--31. 1. "RSVDP_16,Reserved for future use." hexmask.long.byte 0x8 8.--15. 1. "EFF_GRAN,PTM Effective Granularity. For a description of this standard PCIe register see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: HWINIT" hexmask.long.byte 0x8 2.--7. 1. "RSVDP_2,Reserved for future use." rbitfld.long 0x8 1. "ROOT_SELECT,PTM Root Select. When set this Time Source is the PTM Root. For a description of this standard PCIe register see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: HWINIT" "0,1" bitfld.long 0x8 0. "PTM_ENABLE,PTM Enable. When set this function is permitted to participate in the PTM mechanism. For a description of this standard PCIe register see the PCI Express Specification." "0,1" tree.end tree "PF0_PTM_RES_CAP (PF PTM Responder Capability Structure (VSEC))" group.long (0x0+0x418)++0xB line.long 0x0 "PTM_RES_CAP_HDR_OFF,Precision Time Measurement Responder Capability Header (VSEC). For more details. see the PTM section in the Databook." hexmask.long.word 0x0 20.--31. 1. "PTM_RES_EXT_CAP_NEXT_OFFS,Precision Time Measurement Responder VSEC Next Pointer. For more details see the PTM section in the Databook. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then.." hexmask.long.byte 0x0 16.--19. 1. "PTM_RES_EXT_CAP_VER,Precision Time Measurement Responder VSEC Version. For more details see the PTM section in the Databook. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else.." hexmask.long.word 0x0 0.--15. 1. "PTM_RES_EXT_CAP_ID,Precision Time Measurement Responder VSEC ID. For more details see the PTM section in the Databook. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else.." line.long 0x4 "PTM_RES_HDR_OFF,Precision Time Measurement Responder Vendor Specific Header. For more details. see the PTM section in the Databook." hexmask.long.word 0x4 20.--31. 1. "PTM_RES_VSEC_LENGTH,PTM Responder VSEC Length. For more details see the PTM section in the Databook. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This.." hexmask.long.byte 0x4 16.--19. 1. "PTM_RES_VSEC_REV,PTM Responder VSEC Revision. For more details see the PTM section in the Databook. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This.." hexmask.long.word 0x4 0.--15. 1. "PTM_RES_VSEC_ID,PTM Responder VSEC ID. For more details see the PTM section in the Databook. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register.." line.long 0x8 "PTM_RES_CONTROL_OFF,PTM Responder Control Register. For more details. see the PTM section in the Databook." hexmask.long 0x8 2.--31. 1. "RSVDP_2,Reserved for future use." bitfld.long 0x8 1. "PTM_RES_PDEL_BYTE_REV,PTM Requester Propagation Delay Byte Reversal - Reverse the order of bytes in the PTM Propagation Delay data word of the PTM ResponseD Message for compatibility with previous revisions. For more details see the PTM section in the.." "0,1" bitfld.long 0x8 0. "PTM_RES_CCONTEXT_VALID,PTM Responder Control Context Valid - PTM Local Timing is valid. This bit is set over the DBI. A speed change or aux_clk_active will set this bit low. For more details see the PTM section in the Databook. Note: The access.." "0,1" rgroup.long (0xC+0x418)++0x3 line.long 0x0 "PTM_RES_STATUS_OFF,PTM Responder Status Register. For more details. see the PTM section in the Databook." hexmask.long 0x0 2.--31. 1. "RSVDP_2,Reserved for future use." bitfld.long 0x0 1. "PTM_RES_REQUEST_RECEIVED,PTM 1st Request Received - PTM Responder has received the first PTM Request Message. Upon receipt of a second PTM Request Message a ResponseD message with timing information will be sent from the Responder if the context is.." "0,1" bitfld.long 0x0 0. "PTM_RES_CONTEXT_VALID,PTM Responder Status Context Valid - PTM Local Timing Context is Valid. Value set from upstream port Requester in a Switch. Shadows the same in the control register in all other products. For more details see the PTM section in the.." "0,1" group.long (0x10+0x418)++0x7 line.long 0x0 "PTM_RES_LOCAL_LSB_OFF,PTM Responder Local Clock LSB. For more details. see the PTM section in the Databook." hexmask.long 0x0 0.--31. 1. "PTM_RES_LOCAL_LSB,PTM Responder Local Clock LSB - Lower 32 bits of local timer value. For more details see the PTM section in the Databook. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then.." line.long 0x4 "PTM_RES_LOCAL_MSB_OFF,PTM Responder Local Clock MSB. For more details. see the PTM section in the Databook." hexmask.long 0x4 0.--31. 1. "PTM_RES_LOCAL_MSB,PTM Responder Local Clock MSB - Upper 32 bits of local timer value. For more details see the PTM section in the Databook. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then.." rgroup.long (0x18+0x418)++0x1F line.long 0x0 "PTM_RES_T2_LSB_OFF,PTM Responder T2 Timestamp LSB. For more details. see the PTM section in the Databook." hexmask.long 0x0 0.--31. 1. "PTM_RES_T2_LSB,PTM Responder T2 Timestamp LSB - Lower 32 bits of the T2 Timestamp value. For more details see the PTM section in the Databook. Note: This register field is sticky." line.long 0x4 "PTM_RES_T2_MSB_OFF,PTM Responder T2 Timestamp MSB. For more details. see the PTM section in the Databook." hexmask.long 0x4 0.--31. 1. "PTM_RES_T2_MSB,PTM Responder T2 Timestamp MSB - Upper 32 bits of the T2 Timestamp value. For more details see the PTM section in the Databook. Note: This register field is sticky." line.long 0x8 "PTM_RES_T2P_LSB_OFF,PTM Responder T2 Previous Timestamp LSB. For more details. see the PTM section in the Databook." hexmask.long 0x8 0.--31. 1. "PTM_RES_T2P_LSB,PTM Responder T2 Previous Timestamp LSB - Lower 32 bits of the previously stored T2 Timestamp value. For more details see the PTM section in the Databook. Note: This register field is sticky." line.long 0xC "PTM_RES_T2P_MSB_OFF,PTM Responder T2 Previous Timestamp MSB. For more details. see the PTM section in the Databook." hexmask.long 0xC 0.--31. 1. "PTM_RES_T2P_MSB,PTM Responder T2 Previous Timestamp MSB - Upper 32 bits of the previously stored T2 Timestamp value. For more details see the PTM section in the Databook. Note: This register field is sticky." line.long 0x10 "PTM_RES_T3_LSB_OFF,PTM Responder T3 Timestamp LSB. For more details. see the PTM section in the Databook." hexmask.long 0x10 0.--31. 1. "PTM_RES_T3_LSB,PTM Responder T3 Timestamp LSB - Lower 32 bits of the T3 Timestamp value. For more details see the PTM section in the Databook. Note: This register field is sticky." line.long 0x14 "PTM_RES_T3_MSB_OFF,PTM Responder T3 Timestamp MSB. For more details. see the PTM section in the Databook." hexmask.long 0x14 0.--31. 1. "PTM_RES_T3_MSB,PTM Responder T3 Timestamp MSB - Upper 32 bits of the T2 Timestamp value. For more details see the PTM section in the Databook. Note: This register field is sticky." line.long 0x18 "PTM_RES_T3P_LSB_OFF,PTM Responder T3 Previous Timestamp LSB. For more details. see the PTM section in the Databook." hexmask.long 0x18 0.--31. 1. "PTM_RES_T3P_LSB,PTM Responder T3 Previous Timestamp LSB - Lower 32 bits of the previously stored T3 Timestamp value. For more details see the PTM section in the Databook. Note: This register field is sticky." line.long 0x1C "PTM_RES_T3P_MSB_OFF,PTM Responder T3 Previous Timestamp MSB. For more details. see the PTM section in the Databook." hexmask.long 0x1C 0.--31. 1. "PTM_RES_T3P_MSB,PTM Responder T3 Previous Timestamp MSB - Upper 32 bits of the previously stored T3 Timestamp value. For more details see the PTM section in the Databook. Note: This register field is sticky." group.long (0x38+0x418)++0x7 line.long 0x0 "PTM_RES_TX_LATENCY_OFF,PTM Responder TX Latency. For more details. see the PTM section in the Databook." hexmask.long.tbyte 0x0 12.--31. 1. "RSVDP_12,Reserved for future use." hexmask.long.word 0x0 0.--11. 1. "PTM_RES_TX_LATENCY,PTM Responder TX Latency - Responder Transmit path latency (12 bit wide). For more details see the PTM section in the Databook. Note: This register field is sticky." line.long 0x4 "PTM_RES_RX_LATENCY_OFF,PTM Responder RX Latency. For more details. see the PTM section in the Databook." hexmask.long.tbyte 0x4 12.--31. 1. "RSVDP_12,Reserved for future use." hexmask.long.word 0x4 0.--11. 1. "PTM_RES_RX_LATENCY,PTM Responder RX Latency - Responder Receive path latency (12 bit wide). For more details see the PTM section in the Databook. Note: This register field is sticky." rgroup.long (0x40+0x418)++0x3 line.long 0x0 "PTM_RES_NOM_CLOCK_T_OFF,PTM Responder Nominal Clock Period. For more details. see the PTM section in the Databook." hexmask.long.byte 0x0 24.--31. 1. "RSVDP_24,Reserved for future use." hexmask.long.byte 0x0 16.--23. 1. "PTM_RES_NOM_CLOCK_T_INT,PTM Responder Nominal Clock Period Integral - Integral part of the nominal PTM local clock period in nanoseconds. For more details see the PTM section in the Databook. Note: This register field is sticky." hexmask.long.word 0x0 0.--15. 1. "PTM_RES_NOM_CLOCK_T_FRAC,PTM Responder Nominal Clock Period Fractional - Fractional part of the nominal PTM local clock period. LSB is 1/(2^16) nanoseconds. For more details see the PTM section in the Databook. Note: This register field is sticky." group.long (0x44+0x418)++0x3 line.long 0x0 "PTM_RES_SCALED_CLOCK_T_OFF,PTM Responder Scaled Clock Period. For more details. see the PTM section in the Databook." bitfld.long 0x0 31. "PTM_RES_SCALED_CLOCK_T_EN,PTM Responder Scaled Clock Period Enable - Use the programmed scaled PTM clock period rather than the nominal values. This bit is cleared when the core_clk rate starts to change and can only be set when the clock period change.." "0,1" hexmask.long.byte 0x0 24.--30. 1. "RSVDP_24,Reserved for future use." hexmask.long.byte 0x0 16.--23. 1. "PTM_RES_SCALED_CLOCK_T_INT,PTM Responder Scaled Clock Period Integral - Integral part of the nominal PTM local clock period in nanoseconds. For more details see the PTM section in the Databook. Note: This register field is sticky." newline hexmask.long.word 0x0 0.--15. 1. "PTM_RES_SCALED_CLOCK_T_FRAC,PTM Responder Scaled Clock Period Fractional - Fractional part of the nominal PTM local clock period. LSB is 1/(2^16) nanoseconds. For more details see the PTM section in the Databook. Note: This register field is sticky." tree.end tree "PF0_PM_CAP (PF PCI Power Management Capability Structure)" group.long (0x0+0x40)++0x7 line.long 0x0 "CAP_ID_NXT_PTR_REG,Power Management Capabilities Register." hexmask.long.byte 0x0 27.--31. 1. "PME_SUPPORT,PME_Support. This 5-bit field indicates the power states in which the function may generate a PME and/or forward PME messages. A value of 0b for any bit indicates that the function is not capable of asserting PME while in that power state. -.." bitfld.long 0x0 26. "D2_SUPPORT,D2_Support. If this bit is set this function supports the D2 Power Management state. Functions that do not support D2 must always return a value of 0b for this bit. Note: The access attributes of this field are as follows: - Wire: No access." "0,1" bitfld.long 0x0 25. "D1_SUPPORT,D1_Support. If this bit is set this function supports the D1 Power Management state. Functions that do not support D1 must always return a value of 0b for this bit. Note: The access attributes of this field are as follows: - Wire: No access." "0,1" bitfld.long 0x0 22.--24. "AUX_CURR,Aux_Current. This 3 bit field reports the Vaux auxiliary current requirements for the function. If this function implements the Data Register the controller hardwires this field to 000b. If PME_Support is 0 xxxxb (PME assertion from D3cold is.." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 21. "DSI,Device Specific Initialization. The DSI bit indicates whether special initialization of this function is required. When set indicates that the function requires a device specific initialization sequence following a transition to the D0uninitialized.." "0,1" bitfld.long 0x0 20. "PME_IMM_READI_RETURN_DO,Immediate_Readiness_on_Return_to_D0. - If this bit is a '1' this function is guaranteed to be ready to successfully complete valid accesses immediately after being set to D0. These accesses include configuration cycles and if.." "0,1" rbitfld.long 0x0 19. "PME_CLK,PME Clock. Does not apply to PCI Express the controller hardwires it to 0b. Note: This register field is sticky." "0,1" bitfld.long 0x0 16.--18. "PM_SPEC_VER,Version. This field provides the Power Management specification version. The controller hardwires this field to 011b for functions compliant to PCI Express Base Specification Revision 4.0 Version 1.0>. Note: The access attributes of this.." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x0 8.--15. 1. "PM_NEXT_POINTER,Next Capability Pointer. This field provides an offset into the function's configuration space pointing to the location of next item in the capabilities list. If there are no additional items in the capabilities list this field is set to.." hexmask.long.byte 0x0 0.--7. 1. "PM_CAP_ID,Capability ID. This field returns 01h to indicate that this is the PCI Power Management Capability. Each function may have only one item in its capability list with Capability ID set to 01h." line.long 0x4 "CON_STATUS_REG,Power Management Control and Status Register. This register is used to manage the PCI function's power management state as well as to enable/monitor PMEs." hexmask.long.byte 0x4 24.--31. 1. "DATA_REG_ADD_INFO,Data. This field is used to report the state dependent data requested by the Data_Select field. The value of this field is scaled by the value reported by the Data_Scale field." rbitfld.long 0x4 23. "BUS_PWR_CLK_CON_EN,Bus Power/Clock Control Enable. For a description of this standard PCIe register field see the PCI Express Base Specification." "0,1" rbitfld.long 0x4 22. "B2_B3_SUPPORT,B2B3 Support for D3hot. For a description of this standard PCIe register field see the PCI Express Base Specification." "0,1" hexmask.long.byte 0x4 16.--21. 1. "RSVDP_16,Reserved for future use." newline bitfld.long 0x4 15. "PME_STATUS,PME_Status. This bit is set when the function normally generates a PME signal. The value of this bit is not affected by the value of the PME_En bit. If PME_Support bit 31 of the Power Management Capabilities register is clear this bit is.." "0,1" rbitfld.long 0x4 13.--14. "DATA_SCALE,Data_Scale. This field indicates the scaling factor to be used when interpreting the value of the Data field. The value and meaning of this field varies depending on which data value has been selected by the Data_Select field. For more details.." "0,1,2,3" hexmask.long.byte 0x4 9.--12. 1. "DATA_SELECT,Data_Select. This 4-bit field is used to select which data is to be reported through the Data and Data_Scale field. If the Data field is not implemented this field must be hardwired to 0000b." bitfld.long 0x4 8. "PME_ENABLE,PME_En. - When set the function is permitted to generate a PME. - When clear the function is not permitted to generate a PME. If PME_Support is 1 xxxxb (PME generation from D3cold) or the function consumes Aux power and Aux power is.." "0,1" newline hexmask.long.byte 0x4 4.--7. 1. "RSVDP_4,Reserved for future use." bitfld.long 0x4 3. "NO_SOFT_RST,No_Soft_Reset. This bit indicates the state of the function after writing the PowerState field to transition the function from D3hot to D0. - When set this transition preserves internal function state. The function is in D0Active and no.." "0,1" rbitfld.long 0x4 2. "RSVDP_2,Reserved for future use." "0,1" bitfld.long 0x4 0.--1. "POWER_STATE,PowerState. This 2-bit field is used both to determine the current power state of a function and to set the function into a new power state. The definition of the field values is given below. You can write to this register; however the.." "D0,D1,D2,D3hot" tree.end tree "PF0_PCIE_CAP (PF PCI Express Capability Structure)" group.long (0x0+0x70)++0x33 line.long 0x0 "PCIE_CAP_ID_PCIE_NEXT_CAP_PTR_PCIE_CAP_REG,PCI Express Capabilities. ID. Next Pointer Register." rbitfld.long 0x0 31. "RSVDP_31,Reserved for future use." "0,1" rbitfld.long 0x0 30. "RSVD,Reserved." "0,1" newline hexmask.long.byte 0x0 25.--29. 1. "PCIE_INT_MSG_NUM,PCIE Interrupt Message Number. For a description of this standard PCIe register field see the PCI Express Base Specification. Interrupt Message Number. This field indicates which MSI/MSI-X vector is used for the interrupt message.." bitfld.long 0x0 24. "PCIE_SLOT_IMP,Slot Implemented. When set this bit indicates that the Link associated with this Port is connected to a slot (as compared to being connected to a system-integrated device or being disabled). This bit is valid for Downstream Ports. This bit.." "0,1" newline hexmask.long.byte 0x0 20.--23. 1. "PCIE_DEV_PORT_TYPE,Device/Port Type. Indicates the specific type of this PCI Express function. Note: Different functions in a Multi-Function Device can generally be of different types. Defined encodings for functions that implement a Type 00h PCI.." hexmask.long.byte 0x0 16.--19. 1. "PCIE_CAP_REG,Capability Version. Indicates PCI-SIG defined PCI Express Capability structure version number. A version of the specification that changes the PCI Express Capability structure in a way that is not otherwise identifiable (for example through.." newline hexmask.long.byte 0x0 8.--15. 1. "PCIE_CAP_NEXT_PTR,Next Capability Pointer. This field contains the offset to the next PCI Capability structure or 00h if no other items exist in the linked list of Capabilities. Note: The access attributes of this field are as follows: - Wire: No access." hexmask.long.byte 0x0 0.--7. 1. "PCIE_CAP_ID,Capability ID. Indicates the PCI Express Capability structure. This field must return a Capability ID of 10h indicating that this is a PCI Express Capability structure." line.long 0x4 "DEVICE_CAPABILITIES_REG,Device Capabilities Register. The Device Capabilities register identifies PCI Express device function specific capabilities." hexmask.long.word 0x4 16.--31. 1. "RSVDP_16,Reserved for future use." bitfld.long 0x4 15. "PCIE_CAP_ROLE_BASED_ERR_REPORT,Role-Based Error Reporting. When set this bit indicates that the function implements the functionality originally defined in the Error Reporting ECN for PCI Express Base Specification Revision 1.0a and later incorporated.." "0,1" newline hexmask.long.word 0x4 6.--14. 1. "RSVDP_6,Reserved for future use." bitfld.long 0x4 5. "PCIE_CAP_EXT_TAG_SUPP,Extended Tag Field Supported. This bit in combination with the 10-Bit Tag Requester Supported bit in the Device Capabilities 2 register indicates the maximum supported size of the Tag field as a Requester. This bit must be set if.." "0,1" newline bitfld.long 0x4 3.--4. "PCIE_CAP_PHANTOM_FUNC_SUPPORT,Phantom Functions Supported. This field indicates the support for use of unclaimed function numbers to extend the number of outstanding transactions allowed by logically combining unclaimed function numbers (called Phantom.." "0,1,2,3" bitfld.long 0x4 0.--2. "PCIE_CAP_MAX_PAYLOAD_SIZE,Max_Payload_Size Supported. This field indicates the maximum payload size that the function can support for TLPs. Defined encodings are: - 000b: 128 bytes max payload size - 001b: 256 bytes max payload size - 010b: 512 bytes max.." "0,1,2,3,4,5,6,7" line.long 0x8 "DEVICE_CONTROL_DEVICE_STATUS,Device Control and Device Status Register. This register controls PCI Express device specific parameters and provides information about PCI Express device (function) specific parameters." hexmask.long.word 0x8 22.--31. 1. "RSVDP_22,Reserved for future use." rbitfld.long 0x8 21. "PCIE_CAP_TRANS_PENDING,Transactions Pending. Endpoints: When set this bit indicates that the function has issued Non-Posted Requests that have not been completed. A Function reports this bit cleared only when all outstanding Non-Posted Requests have.." "0,1" newline rbitfld.long 0x8 20. "PCIE_CAP_AUX_POWER_DETECTED,AUX Power Detected. Functions that require Aux power report this bit as set if Aux power is detected by the function. This bit is derived by sampling the sys_aux_pwr_det input." "0,1" bitfld.long 0x8 19. "PCIE_CAP_UNSUPPORTED_REQ_DETECTED,Unsupported Request Detected. This bit indicates that the function received an Unsupported Request. Errors are logged in this register regardless of whether error reporting is enabled or not in the Device Control.." "0,1" newline bitfld.long 0x8 17. "PCIE_CAP_NON_FATAL_ERR_DETECTED,Non-Fatal Error Detected. This bit indicates status of Non-fatal errors detected. Errors are logged in this register regardless of whether error reporting is enabled or not in the Device Control register. For a.." "0,1" bitfld.long 0x8 12.--14. "PCIE_CAP_MAX_READ_REQ_SIZE,Max_Read_Request_Size. This field sets the maximum Read Request size for the function as a Requester. The function must not generate Read Requests with a size exceeding the set value. Defined encodings for this field are: -.." "0,1,2,3,4,5,6,7" newline rbitfld.long 0x8 11. "PCIE_CAP_EN_NO_SNOOP,Enable No Snoop. If this bit is set the function is permitted to Set the No Snoop bit in the Requester Attributes of transactions it initiates that do not require hardware enforced cache coherency (see section 2.2.6.5 in PCI Express.." "0,1" bitfld.long 0x8 10. "PCIE_CAP_AUX_POWER_PM_EN,Aux Power PM Enable. This bit is derived by sampling the sys_aux_pwr_det input. When set this bit enables a function to draw Aux power independent of PME Aux power. Functions that require Aux power on legacy operating systems.." "0,1" newline rbitfld.long 0x8 9. "PCIE_CAP_PHANTOM_FUNC_EN,Phantom Functions Enable. This bit in combination with the 10-Bit Tag Requester Enable bit in the Device Control 2 register determines how many Tag field bits a Requester is permitted to use. When the 10-Bit Tag Requester.." "0,1" rbitfld.long 0x8 8. "PCIE_CAP_EXT_TAG_EN,Extended Tag Field Enable. This bit in combination with the 10-Bit Tag Requester Enable bit in the Device Control 2 register determines how many Tag field bits a Requester is permitted to use. When the 10-Bit Tag Requester Enable.." "0,1" newline bitfld.long 0x8 5.--7. "PCIE_CAP_MAX_PAYLOAD_SIZE_CS,Max_Payload_Size. This field sets maximum TLP payload size for the Function. As a Receiver the Function must handle TLPs as large as the set value. As a Transmitter the Function must not generate TLPs exceeding the set.." "0,1,2,3,4,5,6,7" bitfld.long 0x8 4. "PCIE_CAP_EN_REL_ORDER,Enable Relaxed Ordering. If this bit is set the function is permitted to set the Relaxed Ordering bit in the Attributes field of transactions it initiates that do not require strong write ordering (for more details see section.." "0,1" newline bitfld.long 0x8 3. "PCIE_CAP_UNSUPPORT_REQ_REP_EN,Unsupported Request Reporting Enable. This bit in conjunction with other bits controls the signaling of Unsupported Request Errors by sending error Messages (for more details see section 6.2.5 and section 6.2.6 of PCI.." "0,1" bitfld.long 0x8 2. "PCIE_CAP_FATAL_ERR_REPORT_EN,Fatal Error Reporting Enable. This bit in conjunction with other bits controls sending ERR_FATAL Messages (for more details see section 6.2.5 and section 6.2.6 of of PCI Express Base Specification). For a Multi-Function.." "0,1" newline bitfld.long 0x8 1. "PCIE_CAP_NON_FATAL_ERR_REPORT_EN,Non-Fatal Error Reporting Enable. This bit in conjunction with other bits controls sending ERR_NONFATAL Messages (for more details see section 6.2.5 and Section 6.2.6 of PCI Express Base Specification). For a.." "0,1" bitfld.long 0x8 0. "PCIE_CAP_CORR_ERR_REPORT_EN,Correctable Error Reporting Enable. This bit in conjunction with other bits controls sending ERR_COR Messages (for more details see section 6.2.5 section 6.2.6 and section 6.2.10.2 of PCI Express Base Specification). For.." "0,1" line.long 0xC "LINK_CAPABILITIES_REG,Link Capabilities Register. The Link Capabilities register identifies PCI Express Link specific capabilities." hexmask.long.byte 0xC 24.--31. 1. "PCIE_CAP_PORT_NUM,Port Number. This field indicates the PCI Express Port number for the given PCI Express Link. Multi-Function Devices associated with an Upstream Port must report the same value in this field for all functions. Note: The access.." rbitfld.long 0xC 23. "RSVDP_23,Reserved for future use." "0,1" newline bitfld.long 0xC 22. "PCIE_CAP_ASPM_OPT_COMPLIANCE,ASPM Optionality Compliance. This bit must be set to 1b in all functions. Components implemented against certain earlier versions of this specification will have this bit set to 0b. Software is permitted to use the value of.." "0,1" bitfld.long 0xC 21. "PCIE_CAP_LINK_BW_NOT_CAP,Link Bandwidth Notification Capability. A value of 1b indicates support for the Link Bandwidth Notification status and interrupt mechanisms. This capability is required for all Root Ports and Switch Downstream Ports supporting.." "0,1" newline rbitfld.long 0xC 20. "PCIE_CAP_DLL_ACTIVE_REP_CAP,Data Link Layer Link Active Reporting Capable. For a Downstream Port the controller hardwires this bit to 1b if the component supports the optional capability of reporting the DL_Active state of the Data Link Control and.." "0,1" bitfld.long 0xC 19. "PCIE_CAP_SURPRISE_DOWN_ERR_REP_CAP,Surprise Down Error Reporting Capable. For a Downstream Port this bit must be set if the component supports the optional capability of detecting and reporting a Surprise Down error condition. For Upstream Ports and.." "0,1" newline rbitfld.long 0xC 18. "PCIE_CAP_CLOCK_POWER_MAN,Clock Power Management. For Upstream Ports a value of 1b in this bit indicates that the component tolerates the removal of any reference clock(s) via the 'clock request' (CLKREQ#) mechanism when the Link is in the L1 and L2/L3.." "0,1" bitfld.long 0xC 15.--17. "PCIE_CAP_L1_EXIT_LATENCY,L1 Exit Latency. This field indicates the L1 exit latency for the given PCI Express Link. The value reported indicates the length of time this Port requires to complete transition from ASPM L1 to L0. If ASPM L1 is not supported.." "0,1,2,3,4,5,6,7" newline bitfld.long 0xC 12.--14. "PCIE_CAP_L0S_EXIT_LATENCY,L0s Exit Latency. This field indicates the L0s exit latency for the given PCI Express Link. The value reported indicates the length of time this Port requires to complete transition from L0s to L0. If L0s is not supported the.." "0,1,2,3,4,5,6,7" bitfld.long 0xC 10.--11. "PCIE_CAP_ACTIVE_STATE_LINK_PM_SUPPORT,Active State Power Management (ASPM) Support. This field indicates the level of ASPM supported on the given PCI Express Link. For more details on ASPM support requirements see section 5.4.1 of PCI Express Base.." "0,1,2,3" newline hexmask.long.byte 0xC 4.--9. 1. "PCIE_CAP_MAX_LINK_WIDTH,Maximum Link Width. This field indicates the maximum Link width (xN - corresponding to N Lanes) implemented by the component. This value is permitted to exceed the number of Lanes routed to the slot (Downstream Port) adapter.." hexmask.long.byte 0xC 0.--3. 1. "PCIE_CAP_MAX_LINK_SPEED,Max Link Speed. This field indicates the maximum Link speed of the associated Port. The encoded value specifies a bit location in the Supported Link Speeds Vector (in the Link Capabilities 2 register) that corresponds to the.." line.long 0x10 "LINK_CONTROL_LINK_STATUS_REG,Link Control and Link Status Register. This register controls and provides information about PCI Express Link specific parameters." bitfld.long 0x10 31. "PCIE_CAP_LINK_AUTO_BW_STATUS,Link Autonomous Bandwidth Status. This bit is set by hardware to indicate that hardware has autonomously changed Link speed or width without the Port transitioning through DL_Down status for reasons other than to attempt to.." "0,1" bitfld.long 0x10 30. "PCIE_CAP_LINK_BW_MAN_STATUS,Link Bandwidth Management Status. This bit is set by hardware to indicate that either of the following has occurred without the Port transitioning through DL_Down status: - A Link retraining has completed following a write of.." "0,1" newline rbitfld.long 0x10 29. "PCIE_CAP_DLL_ACTIVE,Data Link Layer Link Active. This bit indicates the status of the Data Link Control and Management State Machine. It returns a 1b to indicate the DL_Active state 0b otherwise. This bit must be implemented if the Data Link Layer Link.." "0,1" bitfld.long 0x10 28. "PCIE_CAP_SLOT_CLK_CONFIG,Slot Clock Configuration. This bit indicates that the component uses the same physical reference clock that the platform provides on the connector. If the device uses an independent clock irrespective of the presence of a.." "0,1" newline rbitfld.long 0x10 27. "PCIE_CAP_LINK_TRAINING,Link Training. This read-only bit indicates that the Physical Layer LTSSM is in the Configuration or Recovery state or that 1b was written to the Retrain Link bit but Link training has not yet begun. Hardware clears this bit when.." "0,1" rbitfld.long 0x10 26. "RSVDP_26,Reserved for future use." "0,1" newline hexmask.long.byte 0x10 20.--25. 1. "PCIE_CAP_NEGO_LINK_WIDTH,Negotiated Link Width. This field indicates the negotiated width of the given PCI Express Link. Defined encodings are: -00 0001b: x1 -00 0010b: x2 -00 0100b: x4 -00 1000b: x8 -00 1100b: x12 -01 0000b: x16 -10 0000b: x32 All other.." hexmask.long.byte 0x10 16.--19. 1. "PCIE_CAP_LINK_SPEED,Current Link Speed. This field indicates the negotiated Link speed of the given PCI Express Link. The encoded value specifies a bit location in the Supported Link Speeds Vector (in the Link Capabilities 2 register) that corresponds to.." newline bitfld.long 0x10 14.--15. "PCIE_CAP_DRS_SIGNALING_CONTROL,DRS Signaling Control. Indicates the mechanism used to report reception of a DRS message. Must be implemented for Downstream Ports with the DRS Supported bit Set in the Link Capabilities 2 Register. Encodings are: - 00b:.." "0,1,2,3" rbitfld.long 0x10 12.--13. "RSVDP_12,Reserved for future use." "0,1,2,3" newline bitfld.long 0x10 11. "PCIE_CAP_LINK_AUTO_BW_INT_EN,Link Autonomous Bandwidth Management Interrupt Enable. When set this bit enables the generation of an interrupt to indicate that the Link Autonomous Bandwidth Status bit has been set. The write value is gated with the.." "0,1" bitfld.long 0x10 10. "PCIE_CAP_LINK_BW_MAN_INT_EN,Link Bandwidth Management Interrupt Enable. When set this bit enables the generation of an interrupt to indicate that the Link Bandwidth Management Status bit has been set. The write value is gated with the.." "0,1" newline bitfld.long 0x10 9. "PCIE_CAP_HW_AUTO_WIDTH_DISABLE,Hardware Autonomous Width Disable. When set this bit disables hardware from changing the Link width for reasons other than attempting to correct unreliable Link operation by reducing Link width. For a Multi-Function Device.." "0,1" bitfld.long 0x10 8. "PCIE_CAP_EN_CLK_POWER_MAN,Enable Clock Power Management. Applicable only for Upstream Ports and with form factors that support a 'Clock Request' (CLKREQ#) mechanism this bit operates as follows: - 0b: Clock power management is disabled and device must.." "0,1" newline bitfld.long 0x10 7. "PCIE_CAP_EXTENDED_SYNCH,Extended Synch. When set this bit forces the transmission of additional Ordered Sets when exiting the L0s state (see section 4.2.4.5 of PCI Express Base Specification) and when in the Recovery state (see section 4.2.6.4.1 of PCI.." "0,1" bitfld.long 0x10 6. "PCIE_CAP_COMMON_CLK_CONFIG,Common Clock Configuration. When set this bit indicates that this component and the component at the opposite end of this Link are operating with a distributed common reference clock. A value of 0b indicates that this.." "0,1" newline bitfld.long 0x10 5. "PCIE_CAP_RETRAIN_LINK,Retrain Link. A write of 1b to this bit initiates Link retraining by directing the Physical Layer LTSSM to the Recovery state. If the LTSSM is already in Recovery or Configuration re-entering Recovery is permitted but not required." "0,1" bitfld.long 0x10 4. "PCIE_CAP_LINK_DISABLE,Link Disable. This bit disables the Link by directing the LTSSM to the Disabled state when set; this bit is Reserved on Endpoints PCI Express to PCI/PCI-X bridges and Upstream Ports of Switches. Writes to this bit are immediately.." "0,1" newline bitfld.long 0x10 3. "PCIE_CAP_RCB,Read Completion Boundary (RCB). Root Ports: Indicates the RCB value for the Root Port. Refer to section 2.3.1.1 of PCI Express Base Specification for the definition of the parameter RCB. Defined encodings are: - 0b: 64 byte - 1b: 128 byte.." "0,1" rbitfld.long 0x10 2. "RSVDP_2,Reserved for future use." "0,1" newline bitfld.long 0x10 0.--1. "PCIE_CAP_ACTIVE_STATE_LINK_PM_CONTROL,Active State Power Management (ASPM) Control. This field controls the level of ASPM enabled on the given PCI Express Link. See section 5.4.1.3 of PCI Express Base Specification for requirements on when and how to.." "0,1,2,3" line.long 0x14 "SLOT_CAPABILITIES_REG,Slot Capabilities Register. The Slot Capabilities register identifies PCI Express slot specific capabilities." hexmask.long.word 0x14 19.--31. 1. "PCIE_CAP_PHY_SLOT_NUM,Physical Slot Number. This field indicates the physical slot number attached to this Port. This field must be hardware initialized to a value that assigns a slot number that is unique within the chassis regardless of the form.." bitfld.long 0x14 18. "PCIE_CAP_NO_CMD_CPL_SUPPORT,No Command Completed Support. When set this bit indicates that this slot does not generate software notification when an issued command is completed by the Hot-Plug Controller. This bit is only permitted to be set if the.." "0,1" newline bitfld.long 0x14 17. "PCIE_CAP_ELECTROMECH_INTERLOCK,Electromechanical Interlock Present. When set this bit indicates that an Electromechanical Interlock is implemented on the chassis for this slot. Note: The access attributes of this field are as follows: - Wire: No access." "0,1" bitfld.long 0x14 15.--16. "PCIE_CAP_SLOT_POWER_LIMIT_SCALE,Slot Power Limit Scale. Specifies the scale used for the Slot Power Limit Value (for more details see Section 6.9 of PCI Express Base Specification). Range of Values: - 00b: 1.0x - 01b: 0.1x - 10b: 0.01x - 11b: 0.001x.." "0,1,2,3" newline hexmask.long.byte 0x14 7.--14. 1. "PCIE_CAP_SLOT_POWER_LIMIT_VALUE,Slot Power Limit Value. In combination with the Slot Power Limit Scale value specifies the upper limit on power supplied by the slot (for more detais see Section 6.9 of PCI Express Base Specification) or by other means.." bitfld.long 0x14 6. "PCIE_CAP_HOT_PLUG_CAPABLE,Hot-Plug Capable. When set this bit indicates that this slot is capable of supporting hot-plug operations. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then R/W else R" "0,1" newline bitfld.long 0x14 5. "PCIE_CAP_HOT_PLUG_SURPRISE,Hot-Plug Surprise. When set this bit indicates that an adapter present in this slot might be removed from the system without any prior notification. This is a form factor specific capability. This bit is an indication to the.." "0,1" bitfld.long 0x14 4. "PCIE_CAP_POWER_INDICATOR,Power Indicator Present. When set this bit indicates that a Power Indicator is electrically controlled by the chassis for this slot. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if.." "0,1" newline bitfld.long 0x14 3. "PCIE_CAP_ATTENTION_INDICATOR,Attention Indicator Present. When set this bit indicates that an Attention Indicator is electrically controlled by the chassis. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if.." "0,1" bitfld.long 0x14 2. "PCIE_CAP_MRL_SENSOR,MRL Sensor Present. When set this bit indicates that an MRL Sensor is implemented on the chassis for this slot. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then R/W else R" "0,1" newline bitfld.long 0x14 1. "PCIE_CAP_POWER_CONTROLLER,Power Controller Present. When set this bit indicates that a software programmable Power Controller is implemented for this slot/adapter (depending on form factor). Note: The access attributes of this field are as follows: -.." "0,1" bitfld.long 0x14 0. "PCIE_CAP_ATTENTION_INDICATOR_BUTTON,Attention Button Present. When set this bit indicates that an Attention Button for this slot is electrically controlled by the chassis. Note: The access attributes of this field are as follows: - Wire: No access. -.." "0,1" line.long 0x18 "SLOT_CONTROL_SLOT_STATUS,Slot Control and Status Register. This register controls and provides information about PCI Express Slot specific parameters." hexmask.long.byte 0x18 25.--31. 1. "RSVDP_25,Reserved for future use." bitfld.long 0x18 24. "PCIE_CAP_DLL_STATE_CHANGED,Data Link Layer State Changed. This bit is set when the value reported in the Data Link Layer Link Active bit of the Link Status register is changed. In response to a Data Link Layer State Changed event software must read the.." "0,1" newline rbitfld.long 0x18 23. "PCIE_CAP_ELECTROMECH_INTERLOCK_STATUS,Electromechanical Interlock Status. If an Electromechanical Interlock is implemented this bit indicates the status of the Electromechanical Interlock. Defined encodings are: - 0b: Electromechanical Interlock.." "0,1" rbitfld.long 0x18 22. "PCIE_CAP_PRESENCE_DETECT_STATE,Presence Detect State. This bit indicates the presence of an adapter in the slot reflected by the logical 'OR' of the Physical Layer in-band presence detect mechanism and if present any out-of-band presence detect.." "0,1" newline rbitfld.long 0x18 21. "PCIE_CAP_MRL_SENSOR_STATE,MRL Sensor State. This bit reports the status of the MRL sensor if implemented. Defined encodings are: - 0b: MRL Closed - 1b: MRL Open" "0,1" bitfld.long 0x18 20. "PCIE_CAP_CMD_CPLD,Command Completed. If Command Completed notification is supported (if the No Command Completed Support bit in the Slot Capabilities register is 0b) this bit is set when a hot-plug command has completed and the Hot-Plug Controller is.." "0,1" newline bitfld.long 0x18 19. "PCIE_CAP_PRESENCE_DETECTED_CHANGED,Presence Detect Changed. This bit is set when the value reported in the Presence Detect State bit is changed." "0,1" bitfld.long 0x18 18. "PCIE_CAP_MRL_SENSOR_CHANGED,MRL Sensor Changed. If an MRL sensor is implemented this bit is set when a MRL Sensor state change is detected. If an MRL sensor is not implemented this bit must not be set." "0,1" newline bitfld.long 0x18 17. "PCIE_CAP_POWER_FAULT_DETECTED,Power Fault Detected. If a Power Controller that supports power fault detection is implemented this bit issSet when the Power Controller detects a power fault at this slot. Note: Depending on hardware capability it is.." "0,1" bitfld.long 0x18 16. "PCIE_CAP_ATTENTION_BUTTON_PRESSED,Attention Button Pressed. If an Attention Button is implemented this bit is set when the attention button is pressed. If an Attention Button is not supported this bit must not be set." "0,1" newline rbitfld.long 0x18 14.--15. "RSVDP_14,Reserved for future use." "0,1,2,3" bitfld.long 0x18 12. "PCIE_CAP_DLL_STATE_CHANGED_EN,Data Link Layer State Changed Enable. If the Data Link Layer Link Active Reporting capability is 1b this bit enables software notification when Data Link Layer Link Active bit is changed. If the Data Link Layer Link Active.." "0,1" newline bitfld.long 0x18 11. "PCIE_CAP_ELECTROMECH_INTERLOCK_CTRL,Electromechanical Interlock Control. If an Electromechanical Interlock is implemented a write of 1b to this bit causes the state of the interlock to toggle. A write of 0b to this bit has no effect. A read of this bit.." "0,1" bitfld.long 0x18 10. "PCIE_CAP_POWER_CONTROLLER_CTRL,Power Controller Control. If a Power Controller is implemented this bit when written sets the power state of the slot per the defined encodings. Reads of this bit must reflect the value from the latest write even if the.." "0,1" newline bitfld.long 0x18 8.--9. "PCIE_CAP_POWER_INDICATOR_CTRL,Power Indicator Control. If a Power Indicator is implemented writes to this field set the Power Indicator to the written state. Reads of this field must reflect the value from the latest write even if the corresponding.." "0,1,2,3" bitfld.long 0x18 6.--7. "PCIE_CAP_ATTENTION_INDICATOR_CTRL,Attention Indicator Control. If an Attention Indicator is implemented writes to this field set the Attention Indicator to the written state. Reads of this field must reflect the value from the latest write even if the.." "0,1,2,3" newline bitfld.long 0x18 5. "PCIE_CAP_HOT_PLUG_INT_EN,Hot-Plug Interrupt Enable. When set this bit enables generation of an interrupt on enabled hot-plug events. If the Hot Plug Capable bit in the Slot Capabilities register is clear this bit is permitted to be read-only with a.." "0,1" bitfld.long 0x18 4. "PCIE_CAP_CMD_CPL_INT_EN,Command Completed Interrupt Enable. If Command Completed notification is supported (if the No Command Completed Support bit in the Slot Capabilities register is 0b) when set this bit enables software notification when a hot-plug.." "0,1" newline bitfld.long 0x18 3. "PCIE_CAP_PRESENCE_DETECT_CHANGE_EN,Presence Detect Changed Enable. When set this bit enables software notification on a presence detect changed event (for more details see Section 6.7.3 of PCI Express Base Specification). If the Hot-Plug Capable bit in.." "0,1" bitfld.long 0x18 2. "PCIE_CAP_MRL_SENSOR_CHANGED_EN,MRL Sensor Changed Enable. When set this bit enables software notification on a MRL sensor changed event (for more details see Section 6.7.3 of PCI Express Base Specification). If the MRL Sensor Present bit in the Slot.." "0,1" newline bitfld.long 0x18 1. "PCIE_CAP_POWER_FAULT_DETECTED_EN,Power Fault Detected Enable. When set this bit enables software notification on a power fault event (for more details see Section 6.7.3 of PCI Express Base Specification). If a Power Controller that supports power fault.." "0,1" bitfld.long 0x18 0. "PCIE_CAP_ATTENTION_BUTTON_PRESSED_EN,Attention Button Pressed Enable. When set to 1b this bit enables software notification on an attention button pressed event (for more details see Section 6.7.3 of PCI Express Base Specification). If the Attention.." "0,1" line.long 0x1C "ROOT_CONTROL_ROOT_CAPABILITIES_REG,Root Control and Capabilities Register. This register controls PCI Express Root Complex specific parameters and identifies PCI Express Root Port specific capabilities." hexmask.long.word 0x1C 17.--31. 1. "RSVDP_17,Reserved for future use." bitfld.long 0x1C 16. "PCIE_CAP_CRS_SW_VISIBILITY,CRS Software Visibility Capable. For a description of this standard PCIe register field see the PCI Express Base Specification. CRS Software Visibility. When set this bit indicates that the Root Port is capable of returning.." "0,1" newline hexmask.long.word 0x1C 5.--15. 1. "RSVDP_5,Reserved for future use." bitfld.long 0x1C 4. "PCIE_CAP_CRS_SW_VISIBILITY_EN,CRS Software Visibility Enable. When set this bit enables the Root Port to return Configuration Request Retry Status (CRS) Completion Status to software (for more details see section 2.3.1 of PCI Express Base.." "0,1" newline bitfld.long 0x1C 3. "PCIE_CAP_PME_INT_EN,PME Interrupt Enable. When set this bit enables PME interrupt generation upon receipt of a PME Message as reflected in the PME Status bit (for more details see Table 7-29 of PCI Express Base Specification). A PME interrupt is also.." "0,1" bitfld.long 0x1C 2. "PCIE_CAP_SYS_ERR_ON_FATAL_ERR_EN,System Error on Fatal Error Enable. If set this bit indicates that a System Error should be generated if a Fatal error (ERR_FATAL) is reported by any of the devices in the Hierarchy Domain associated with this Root Port.." "0,1" newline bitfld.long 0x1C 1. "PCIE_CAP_SYS_ERR_ON_NON_FATAL_ERR_EN,System Error on Non-Fatal Error Enable. If set this bit indicates that a System Error should be generated if a Non-fatal error (ERR_NONFATAL) is reported by any of the devices in the Hierarchy Domain associated with.." "0,1" bitfld.long 0x1C 0. "PCIE_CAP_SYS_ERR_ON_CORR_ERR_EN,System Error on Correctable Error Enable. If set this bit indicates that a System Error should be generated if a correctable error (ERR_COR) is reported by any of the devices in the Hierarchy Domain associated with this.." "0,1" line.long 0x20 "ROOT_STATUS_REG,Root Status Register. The Root Status register provides information about PCI Express device specific parameters." hexmask.long.word 0x20 18.--31. 1. "RSVDP_18,Reserved for future use." rbitfld.long 0x20 17. "PCIE_CAP_PME_PENDING,PME Pending. This bit indicates that another PME is pending when the PME Status bit is s et. When the PME Status bit is cleared by software; the PME is delivered by hardware by setting the PME Status bit again and updating the PME.." "0,1" newline bitfld.long 0x20 16. "PCIE_CAP_PME_STATUS,PME Status. This bit indicates that PME was asserted by the PME Requester indicated in the PME Requester ID field. Subsequent PMEs are kept pending until the status register is cleared by software by writing a 1b." "0,1" hexmask.long.word 0x20 0.--15. 1. "PCIE_CAP_PME_REQ_ID,PME Requester ID. This field indicates the PCI Requester ID of the last PME Requester. This field is only valid when the PME Status bit is set." line.long 0x24 "DEVICE_CAPABILITIES2_REG,Device Capabilities 2 Register." bitfld.long 0x24 31. "PCIE_CAP_FRS_SUPPORTED,FRS Supported. When set indicates support for the optional Function Readiness Status (FRS) capability. Must be set for all Functions that support generation or reception capabilities of FRS Messages. Must not be set by Switch.." "0,1" hexmask.long.byte 0x24 24.--30. 1. "RSVDP_24,Reserved for future use." newline rbitfld.long 0x24 17. "PCIE_CAP2_10_BIT_TAG_REQ_SUPPORT,10-Bit Tag Requester Supported. If this bit is set the Function supports 10-Bit Tag Requester capability; otherwise the Function does not. This bit must not be set if the 10-Bit Tag Completer Supported bit is clear." "0,1" rbitfld.long 0x24 16. "PCIE_CAP2_10_BIT_TAG_COMP_SUPPORT,10-Bit Tag Completer Supported. If this bit is set the Function supports 10-Bit Tag Completer capability; otherwise the Function does not. For more details see section 2.2.6.2. of PCI Express Base Specification." "0,1" newline rbitfld.long 0x24 13. "PCIE_CAP_TPH_CMPLT_SUPPORT_1,TPH Completer Supported Bit 1." "0,1" rbitfld.long 0x24 12. "PCIE_CAP_TPH_CMPLT_SUPPORT_0,TPH Completer Supported Bit 0. Value of this bit along with TPH Completer Supported Bit 1 indicates Completer support for TPH or Extended TPH. Applicable only to Root Ports and Endpoints. For all other Functions this field.." "0,1" newline bitfld.long 0x24 11. "PCIE_CAP_LTR_SUPP,LTR Mechanism Supported. A value of 1b indicates support for the optional Latency Tolerance Reporting (LTR) mechanism. Root Ports Switches and Endpoints are permitted to implement this capability. For a Multi-Function Device associated.." "0,1" rbitfld.long 0x24 10. "PCIE_CAP_NO_RO_EN_PR2PR_PAR,No RO-enabled PR-PR Passing. If this bit is set the routing element never carries out the passing permitted by Table 2-39 of PCI Express Base Specification entry A2b that is associated with the Relaxed Ordering Attribute.." "0,1" newline rbitfld.long 0x24 9. "PCIE_CAP_128_CAS_CPL_SUPP,128-bit CAS Completer Supported. Applicable to Functions with Memory Space BARs as well as all Root Ports; must be 0b otherwise. This bit must be set to 1b if the Function supports this optional capability. For more details see.." "0,1" rbitfld.long 0x24 8. "PCIE_CAP_64_ATOMIC_CPL_SUPP,64-bit AtomicOp Completer Supported. Applicable to Functions with Memory Space BARs as well as all Root Ports; must be 0b otherwise. Includes FetchAdd Swap and CAS AtomicOps. This bit must be set to 1b if the Function.." "0,1" newline rbitfld.long 0x24 7. "PCIE_CAP_32_ATOMIC_CPL_SUPP,32-bit AtomicOp Completer Supported. Applicable to Functions with Memory Space BARs as well as all Root Ports; must be 0b otherwise. Includes FetchAdd Swap and CAS AtomicOps. This bit must be set to 1b if the Function.." "0,1" rbitfld.long 0x24 6. "PCIE_CAP_ATOMIC_ROUTING_SUPP,AtomicOp Routing Supported. Applicable only to Switch Upstream Ports Switch Downstream Ports and Root Ports; must be 0b for other Function types. This bit must be set to 1b if the Port supports this optional capability. For.." "0,1" newline rbitfld.long 0x24 5. "PCIE_CAP_ARI_FORWARD_SUPPORT,ARI Forwarding Supported. Applicable only to Switch Downstream Ports and Root Ports; must be 0b for other Function types. This bit must be set to 1b if a Switch Downstream Port or Root Port supports this optional capability." "0,1" rbitfld.long 0x24 4. "PCIE_CAP_CPL_TIMEOUT_DISABLE_SUPPORT,Completion Timeout Disable Supported. A value of 1b indicates support for the Completion Timeout Disable mechanism. The Completion Timeout Disable mechanism is required for Endpoints that issue Requests on their own.." "0,1" newline hexmask.long.byte 0x24 0.--3. 1. "PCIE_CAP_CPL_TIMEOUT_RANGE,Completion Timeout Ranges Supported. This field indicates device Function support for the optional Completion Timeout programmability mechanism. This mechanism allows system software to modify the Completion Timeout value. This.." line.long 0x28 "DEVICE_CONTROL2_DEVICE_STATUS2_REG,Device Control 2 and Status 2 Register." bitfld.long 0x28 10. "PCIE_CAP_LTR_EN,LTR Mechanism Enable. When set to 1b this bit enables Upstream Ports to send LTR messages and Downstream Ports to process LTR Messages. For a Multi-Function Device associated with an Upstream Port of a device that implements LTR the bit.." "0,1" rbitfld.long 0x28 5. "PCIE_CAP_ARI_FORWARD_SUPPORT_CS,ARI Forwarding Enable. When set the Downstream Port disables its traditional Device Number field being 0 enforcement when turning a Type 1 Configuration Request into a Type 0 Configuration Request permitting access to.." "0,1" newline bitfld.long 0x28 4. "PCIE_CAP_CPL_TIMEOUT_DISABLE,Completion Timeout Disable. When set this bit disables the Completion Timeout mechanism. This bit is required for all Functions that support the Completion Timeout Disable Capability. Functions that do not support this.." "0,1" hexmask.long.byte 0x28 0.--3. 1. "PCIE_CAP_CPL_TIMEOUT_VALUE,Completion Timeout Value. In device Functions that support Completion Timeout programmability this field allows system software to modify the Completion Timeout value. This field is applicable to Root Ports Endpoints that.." line.long 0x2C "LINK_CAPABILITIES2_REG,Link Capabilities 2 Register." bitfld.long 0x2C 31. "DRS_SUPPORTED,DRS Supported. When set indicates support for the optional Device Readiness Status (DRS) capability. Must be Set in Downstream Ports that support DRS. Must be Set in Downstream Ports that support FRS. For Upstream Ports that support DRS.." "0,1" hexmask.long.byte 0x2C 25.--30. 1. "RSVDP_25,Reserved for future use." newline hexmask.long.word 0x2C 9.--22. 1. "RSVDP_9,Reserved for future use." rbitfld.long 0x2C 8. "PCIE_CAP_CROSS_LINK_SUPPORT,Crosslink Supported. When set to 1b this bit indicates that the associated Port supports crosslinks (for more details see section 4.2.6.3.1 of PCI Express Base Specification). When set to 0b on a Port that supports Link.." "0,1" newline hexmask.long.byte 0x2C 1.--7. 1. "PCIE_CAP_SUPPORT_LINK_SPEED_VECTOR,Supported Link Speeds Vector. This field indicates the supported Link speed(s) of the associated Port. For each bit a value of 1b indicates that the corresponding Link speed is supported; otherwise the Link speed is.." rbitfld.long 0x2C 0. "RSVDP_0,Reserved for future use." "0,1" line.long 0x30 "LINK_CONTROL2_LINK_STATUS2_REG,Link Control 2 and Status 2 Register." bitfld.long 0x30 31. "DRS_MESSAGE_RECEIVED,DRS Message Received. This bit must be set whenever the Port receives a DRS Message. This bit must be cleared in DL_Down. This bit must be implemented in any Downstream Port where the DRS Supported bit is Set in the Link Capabilities.." "0,1" rbitfld.long 0x30 28.--30. "DOWNSTREAM_COMPO_PRESENCE,Downstream Component Presence. This field indicates the presence and DRS status for the Downstream Component if any connected to the Link; defined values are: - 000b: Link Down - Presence Not Determined - 001b: Link Down -.." "0,1,2,3,4,5,6,7" newline rbitfld.long 0x30 26.--27. "RSVDP_26,Reserved for future use." "0,1,2,3" bitfld.long 0x30 21. "PCIE_CAP_LINK_EQ_REQ,Link Equalization Request 8.0 GT/s. This bit is set by hardware to request the 8.0 GT/s Link equalization process to be performed on the Link. For more details see sections 4.2.3 and 4.2.6.4.2 of PCI Express Base Specification. For.." "0,1" newline rbitfld.long 0x30 20. "PCIE_CAP_EQ_CPL_P3,EEqualization 8.0 GT/s Phase 3 Successful. When set to 1b this bit indicates that Phase 3 of the 8.0 GT/s Transmitter Equalization procedure has successfully completed. Details of the Transmitter Equalization process and when this bit.." "0,1" rbitfld.long 0x30 19. "PCIE_CAP_EQ_CPL_P2,Equalization 8.0 GT/s Phase 2 Successful. When set to 1b this bit indicates that Phase 2 of the 8.0 GT/s Transmitter Equalization procedure has successfully completed. Details of the Transmitter Equalization process and when this bit.." "0,1" newline rbitfld.long 0x30 18. "PCIE_CAP_EQ_CPL_P1,Equalization 8.0 GT/s Phase 1 Successful. When set to 1b this bit indicates that Phase 1 of the 8.0 GT/s Transmitter Equalization procedure has successfully completed. Details of the Transmitter Equalization process and when this bit.." "0,1" rbitfld.long 0x30 17. "PCIE_CAP_EQ_CPL,Equalization 8.0 GT/s Complete. When set to 1b this bit indicates that the Transmitter Equalization procedure at the 8.0 GT/s data rate has completed. Details of the Transmitter Equalization process and when this bit needs to be set to.." "0,1" newline rbitfld.long 0x30 16. "PCIE_CAP_CURR_DEEMPHASIS,Current De-emphasis Level. When the Link is operating at 5.0 GT/s speed this bit reflects the level of de-emphasis. Encodings: - 1b: -3.5 dB - 0b: -6 dB The value in this bit is undefined when the Link is not operating at 5.0.." "0,1" hexmask.long.byte 0x30 12.--15. 1. "PCIE_CAP_COMPLIANCE_PRESET,Compliance Preset/De-emphasis. For 8.0 GT/s and higher Data Rate: This field sets the Transmitter Preset in Polling.Compliance state if the entry occurred due to the Enter Compliance bit being 1b. The encodings are defined in.." newline bitfld.long 0x30 11. "PCIE_CAP_COMPLIANCE_SOS,Compliance SOS. When set to 1b the LTSSM is required to send SKP Ordered Sets between sequences when sending the Compliance Pattern or Modified Compliance Pattern. For a Multi-Function Device associated with an Upstream Port the.." "0,1" bitfld.long 0x30 10. "PCIE_CAP_ENTER_MODIFIED_COMPLIANCE,Enter Modified Compliance. When this bit is set to 1b the device transmits Modified Compliance Pattern if the LTSSM enters Polling.Compliance substate. Components that support only the 2.5 GT/s speed are permitted to.." "0,1" newline bitfld.long 0x30 7.--9. "PCIE_CAP_TX_MARGIN,Transmit Margin - This field controls the value of the non-deemphasized voltage level at the Transmitter pins. This field is reset to 000b on entry to the LTSSM Polling.Configuration substate (see Chapter 4 of PCI Express Base.." "0,1,2,3,4,5,6,7" bitfld.long 0x30 6. "PCIE_CAP_SEL_DEEMPHASIS,Selectable De-emphasis. When the Link is operating at 5.0 GT/s speed this bit is used to control the transmit de-emphasis of the link in specific situations. For more details see section 4.2.6 of PCI Express Base Specification." "0,1" newline bitfld.long 0x30 5. "PCIE_CAP_HW_AUTO_SPEED_DISABLE,Hardware Autonomous Speed Disable. When set this bit disables hardware from changing the Link speed for device-specific reasons other than attempting to correct unreliable Link operation by reducing Link speed. Initial.." "0,1" bitfld.long 0x30 4. "PCIE_CAP_ENTER_COMPLIANCE,Enter Compliance. Software is permitted to force a Link to enter Compliance mode (at the speed indicated in the Target Link Speed field and the de-emphasis/preset level indicated by the Compliance Preset/De-emphasis field) by.." "0,1" newline hexmask.long.byte 0x30 0.--3. 1. "PCIE_CAP_TARGET_LINK_SPEED,Target Link Speed. For Downstream Ports this field sets an upper limit on Link operational speed by restricting the values advertised by the Upstream component in its training sequences. The encoded value specifies a bit.." tree.end tree "PF0_AER_CAP (PF Advanced Error Reporting Capability Structure)" group.long (0x0+0x100)++0x1B line.long 0x0 "AER_EXT_CAP_HDR_OFF,Advanced Error Reporting Extended Capability Header. For a description of this standard PCIe register. see the PCI Express Specification." hexmask.long.word 0x0 20.--31. 1. "NEXT_OFFSET,Next Capability Offset. For a description of this standard PCIe register field see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky).." hexmask.long.byte 0x0 16.--19. 1. "CAP_VERSION,Capability Version. For a description of this standard PCIe register field see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else.." newline hexmask.long.word 0x0 0.--15. 1. "CAP_ID,AER Extended Capability ID. For a description of this standard PCIe register field see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else.." line.long 0x4 "UNCORR_ERR_STATUS_OFF,Uncorrectable Error Status Register. For a description of this standard PCIe register. see the PCI Express Specification." hexmask.long.byte 0x4 27.--31. 1. "RSVDP_27,Reserved for future use." rbitfld.long 0x4 23. "RSVDP_23,Reserved for future use." "0,1" newline bitfld.long 0x4 22. "INTERNAL_ERR_STATUS,Uncorrectable Internal Error Status. For a description of this standard PCIe register field see the PCI Express Specification. The controller sets this bit when your application asserts app_err_bus[9]. It does not set this bit when.." "0,1" bitfld.long 0x4 20. "UNSUPPORTED_REQ_ERR_STATUS,Unsupported Request Error Status. For a description of this standard PCIe register field see the PCI Express Specification." "0,1" newline bitfld.long 0x4 19. "ECRC_ERR_STATUS,ECRC Error Status. For a description of this standard PCIe register field see the PCI Express Specification. Note:If CX_ECRC_ENABLE=0 the register field always reads 0." "0,1" bitfld.long 0x4 18. "MALF_TLP_ERR_STATUS,Malformed TLP Status. For a description of this standard PCIe register field see the PCI Express Specification." "0,1" newline bitfld.long 0x4 17. "REC_OVERFLOW_ERR_STATUS,Receiver Overflow Status. For a description of this standard PCIe register field see the PCI Express Specification." "0,1" bitfld.long 0x4 16. "UNEXP_CMPLT_ERR_STATUS,Unexpected Completion Status. For a description of this standard PCIe register field see the PCI Express Specification." "0,1" newline bitfld.long 0x4 15. "CMPLT_ABORT_ERR_STATUS,Completer Abort Status. For a description of this standard PCIe register field see the PCI Express Specification." "0,1" bitfld.long 0x4 14. "CMPLT_TIMEOUT_ERR_STATUS,Completion Timeout Status. For a description of this standard PCIe register field see the PCI Express Specification." "0,1" newline bitfld.long 0x4 13. "FC_PROTOCOL_ERR_STATUS,Flow Control Protocol Error Status. For a description of this standard PCIe register field see the PCI Express Specification." "0,1" bitfld.long 0x4 12. "POIS_TLP_ERR_STATUS,Poisoned TLP Status. For a description of this standard PCIe register field see the PCI Express Specification." "0,1" newline hexmask.long.byte 0x4 6.--11. 1. "RSVDP_6,Reserved for future use." bitfld.long 0x4 5. "SURPRISE_DOWN_ERR_STATUS,Surprise Down Error Status (Optional). For a description of this standard PCIe register field see the PCI Express Specification." "0,1" newline bitfld.long 0x4 4. "DL_PROTOCOL_ERR_STATUS,Data Link Protocol Error Status. For a description of this standard PCIe register field see the PCI Express Specification." "0,1" hexmask.long.byte 0x4 0.--3. 1. "RSVDP_0,Reserved for future use." line.long 0x8 "UNCORR_ERR_MASK_OFF,Uncorrectable Error Mask Register. For a description of this standard PCIe register. see the PCI Express Specification." hexmask.long.byte 0x8 27.--31. 1. "RSVDP_27,Reserved for future use." rbitfld.long 0x8 23. "RSVDP_23,Reserved for future use." "0,1" newline bitfld.long 0x8 22. "INTERNAL_ERR_MASK,Uncorrectable Internal Error Mask (Optional). For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." "0,1" rbitfld.long 0x8 21. "ACS_VIOLATION_MASK,ACS Violation Mask. Setting the ACS Violation Mask bit disables error logging and signaling for ACS Violation errors. The bit is Read-Only Zero for upstream ports when ACS P2P Egress Control Enable is not set. For a description of.." "0,1" newline bitfld.long 0x8 20. "UNSUPPORTED_REQ_ERR_MASK,Unsupported Request Error Mask. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." "0,1" bitfld.long 0x8 19. "ECRC_ERR_MASK,ECRC Error Mask (Optional). For a description of this standard PCIe register field see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W (sticky) Note: This register.." "0,1" newline bitfld.long 0x8 18. "MALF_TLP_ERR_MASK,Malformed TLP Mask. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." "0,1" bitfld.long 0x8 17. "REC_OVERFLOW_ERR_MASK,Receiver Overflow Mask (Optional). For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." "0,1" newline bitfld.long 0x8 16. "UNEXP_CMPLT_ERR_MASK,Unexpected Completion Mask. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." "0,1" bitfld.long 0x8 15. "CMPLT_ABORT_ERR_MASK,Completer Abort Error Mask (Optional). For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." "0,1" newline bitfld.long 0x8 14. "CMPLT_TIMEOUT_ERR_MASK,Completion Timeout Error Mask. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." "0,1" bitfld.long 0x8 13. "FC_PROTOCOL_ERR_MASK,Flow Control Protocol Error Mask. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." "0,1" newline bitfld.long 0x8 12. "POIS_TLP_ERR_MASK,Poisoned TLP Error Mask. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." "0,1" hexmask.long.byte 0x8 6.--11. 1. "RSVDP_6,Reserved for future use." newline rbitfld.long 0x8 5. "SURPRISE_DOWN_ERR_MASK,Surprise Down Error Mask. For a description of this standard PCIe register field see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi:.." "0,1" bitfld.long 0x8 4. "DL_PROTOCOL_ERR_MASK,Data Link Protocol Error Mask. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." "0,1" newline hexmask.long.byte 0x8 0.--3. 1. "RSVDP_0,Reserved for future use." line.long 0xC "UNCORR_ERR_SEV_OFF,Uncorrectable Error Severity Register. For a description of this standard PCIe register. see the PCI Express Specification." hexmask.long.byte 0xC 27.--31. 1. "RSVDP_27,Reserved for future use." rbitfld.long 0xC 24. "ATOMIC_EGRESS_BLOCKED_ERR_SEVERITY,AtomicOp Egress Blocked Severity (Optional). For a description of this standard PCIe register field see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi:.." "0,1" newline rbitfld.long 0xC 23. "RSVDP_23,Reserved for future use." "0,1" bitfld.long 0xC 22. "INTERNAL_ERR_SEVERITY,Uncorrectable Internal Error Severity (Optional). For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." "0,1" newline bitfld.long 0xC 20. "UNSUPPORTED_REQ_ERR_SEVERITY,Unsupported Request Error Severity. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." "0,1" bitfld.long 0xC 19. "ECRC_ERR_SEVERITY,ECRC Error Severity (Optional). For a description of this standard PCIe register field see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W (sticky) Note: This.." "0,1" newline bitfld.long 0xC 18. "MALF_TLP_ERR_SEVERITY,Malformed TLP Severity. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." "0,1" bitfld.long 0xC 17. "REC_OVERFLOW_ERR_SEVERITY,Receiver Overflow Error Severity (Optional). For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." "0,1" newline bitfld.long 0xC 16. "UNEXP_CMPLT_ERR_SEVERITY,Unexpected Completion Error Severity. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." "0,1" bitfld.long 0xC 15. "CMPLT_ABORT_ERR_SEVERITY,Completer Abort Error Severity (Optional). For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." "0,1" newline bitfld.long 0xC 14. "CMPLT_TIMEOUT_ERR_SEVERITY,Completion Timeout Error Severity. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." "0,1" bitfld.long 0xC 13. "FC_PROTOCOL_ERR_SEVERITY,Flow Control Protocol Error Severity (Optional). For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." "0,1" newline bitfld.long 0xC 12. "POIS_TLP_ERR_SEVERITY,Poisoned TLP Severity. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." "0,1" hexmask.long.byte 0xC 6.--11. 1. "RSVDP_6,Reserved for future use." newline rbitfld.long 0xC 5. "SURPRISE_DOWN_ERR_SVRITY,Surprise Down Error Severity (Optional). For a description of this standard PCIe register field see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi:.." "0,1" bitfld.long 0xC 4. "DL_PROTOCOL_ERR_SEVERITY,Data Link Protocol Error Severity. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." "0,1" newline hexmask.long.byte 0xC 0.--3. 1. "RSVDP_0,Reserved for future use." line.long 0x10 "CORR_ERR_STATUS_OFF,Correctable Error Status Register. For a description of this standard PCIe register. see the PCI Express Specification." hexmask.long.word 0x10 16.--31. 1. "RSVDP_16,Reserved for future use." bitfld.long 0x10 15. "HEADER_LOG_OVERFLOW_STATUS,Header Log Overflow Error Status (Optional). For a description of this standard PCIe register field see the PCI Express Specification." "0,1" newline bitfld.long 0x10 14. "CORRECTED_INT_ERR_STATUS,Corrected Internal Error Status (Optional). For a description of this standard PCIe register field see the PCI Express Specification." "0,1" bitfld.long 0x10 13. "ADVISORY_NON_FATAL_ERR_STATUS,Advisory Non-Fatal Error Status. For a description of this standard PCIe register field see the PCI Express Specification." "0,1" newline bitfld.long 0x10 12. "RPL_TIMER_TIMEOUT_STATUS,Replay Timer Timeout Status. For a description of this standard PCIe register field see the PCI Express Specification." "0,1" rbitfld.long 0x10 9.--11. "RSVDP_9,Reserved for future use." "0,1,2,3,4,5,6,7" newline bitfld.long 0x10 8. "REPLAY_NO_ROLEOVER_STATUS,REPLAY_NUM Rollover Status. For a description of this standard PCIe register field see the PCI Express Specification." "0,1" bitfld.long 0x10 7. "BAD_DLLP_STATUS,Bad DLLP Status. For a description of this standard PCIe register field see the PCI Express Specification." "0,1" newline bitfld.long 0x10 6. "BAD_TLP_STATUS,Bad TLP Status. For a description of this standard PCIe register field see the PCI Express Specification." "0,1" hexmask.long.byte 0x10 1.--5. 1. "RSVDP_1,Reserved for future use." newline bitfld.long 0x10 0. "RX_ERR_STATUS,Receiver Error Status (Optional). For a description of this standard PCIe register field see the PCI Express Specification." "0,1" line.long 0x14 "CORR_ERR_MASK_OFF,Correctable Error Mask Register. For a description of this standard PCIe register. see the PCI Express Specification." hexmask.long.word 0x14 16.--31. 1. "RSVDP_16,Reserved for future use." bitfld.long 0x14 15. "HEADER_LOG_OVERFLOW_MASK,Header Log Overflow Error Mask (Optional). For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." "0,1" newline bitfld.long 0x14 14. "CORRECTED_INT_ERR_MASK,Corrected Internal Error Mask (Optional). For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." "0,1" bitfld.long 0x14 13. "ADVISORY_NON_FATAL_ERR_MASK,Advisory Non-Fatal Error Mask. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." "0,1" newline bitfld.long 0x14 12. "RPL_TIMER_TIMEOUT_MASK,Replay Timer Timeout Mask. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." "0,1" rbitfld.long 0x14 9.--11. "RSVDP_9,Reserved for future use." "0,1,2,3,4,5,6,7" newline bitfld.long 0x14 8. "REPLAY_NO_ROLEOVER_MASK,REPLAY_NUM Rollover Mask. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." "0,1" bitfld.long 0x14 7. "BAD_DLLP_MASK,Bad DLLP Mask. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." "0,1" newline bitfld.long 0x14 6. "BAD_TLP_MASK,Bad TLP Mask. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." "0,1" hexmask.long.byte 0x14 1.--5. 1. "RSVDP_1,Reserved for future use." newline bitfld.long 0x14 0. "RX_ERR_MASK,Receiver Error Mask (Optional). For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." "0,1" line.long 0x18 "ADV_ERR_CAP_CTRL_OFF,Advanced Error Capabilities and Control Register. For a description of this standard PCIe register. see the PCI Express Specification." hexmask.long.tbyte 0x18 13.--31. 1. "RSVDP_13,Reserved for future use." rbitfld.long 0x18 12. "CTO_PRFX_HDR_LOG_CAP,TLP Prefix Log Present. For a description of this standard PCIe register field see the PCI Express Specification." "0,1" newline rbitfld.long 0x18 10. "MULTIPLE_HEADER_EN,Multiple Header Recording Enable. For a description of this standard PCIe register field see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R (sticky) Note: This.." "0,1" rbitfld.long 0x18 9. "MULTIPLE_HEADER_CAP,Multiple Header Recording Capable. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." "0,1" newline bitfld.long 0x18 8. "ECRC_CHECK_EN,ECRC Check Enable. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." "0,1" rbitfld.long 0x18 7. "ECRC_CHECK_CAP,ECRC Check Capable. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." "0,1" newline bitfld.long 0x18 6. "ECRC_GEN_EN,ECRC Generation Enable. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." "0,1" rbitfld.long 0x18 5. "ECRC_GEN_CAP,ECRC Generation Capable. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." "0,1" newline hexmask.long.byte 0x18 0.--4. 1. "FIRST_ERR_POINTER,First Error Pointer. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." rgroup.long (0x1C+0x100)++0xF line.long 0x0 "HDR_LOG_0_OFF,Header Log Register 0. For a description of this standard PCIe register. see the PCI Express Specification." hexmask.long.byte 0x0 24.--31. 1. "FIRST_DWORD_FOURTH_BYTE,Byte 3 of Header log register of First 32 bit Data Word. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." hexmask.long.byte 0x0 16.--23. 1. "FIRST_DWORD_THIRD_BYTE,Byte 2 of Header log register of First 32 bit Data Word. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." newline hexmask.long.byte 0x0 8.--15. 1. "FIRST_DWORD_SECOND_BYTE,Byte 1 of Header log register of First 32 bit Data Word. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." hexmask.long.byte 0x0 0.--7. 1. "FIRST_DWORD_FIRST_BYTE,Byte 0 of Header log register of First 32 bit Data Word. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." line.long 0x4 "HDR_LOG_1_OFF,Header Log Register 1. For a description of this standard PCIe register. see the PCI Express Specification." hexmask.long.byte 0x4 24.--31. 1. "SECOND_DWORD_FOURTH_BYTE,Byte 3 of Header log register of Second 32 bit Data Word. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." hexmask.long.byte 0x4 16.--23. 1. "SECOND_DWORD_THIRD_BYTE,Byte 2 of Header log register of Second 32 bit Data Word. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." newline hexmask.long.byte 0x4 8.--15. 1. "SECOND_DWORD_SECOND_BYTE,Byte 1 of Header log register of Second 32 bit Data Word. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." hexmask.long.byte 0x4 0.--7. 1. "SECOND_DWORD_FIRST_BYTE,Byte 0 of Header log register of Second 32 bit Data Word. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." line.long 0x8 "HDR_LOG_2_OFF,Header Log Register 2. For a description of this standard PCIe register. see the PCI Express Specification." hexmask.long.byte 0x8 24.--31. 1. "THIRD_DWORD_FOURTH_BYTE,Byte 3 of Header log register of Third 32 bit Data Word. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." hexmask.long.byte 0x8 16.--23. 1. "THIRD_DWORD_THIRD_BYTE,Byte 2 of Header log register of Third 32 bit Data Word. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." newline hexmask.long.byte 0x8 8.--15. 1. "THIRD_DWORD_SECOND_BYTE,Byte 1 of Header log register of Third 32 bit Data Word. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." hexmask.long.byte 0x8 0.--7. 1. "THIRD_DWORD_FIRST_BYTE,Byte 0 of Header log register of Third 32 bit Data Word. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." line.long 0xC "HDR_LOG_3_OFF,Header Log Register 3. For a description of this standard PCIe register. see the PCI Express Specification." hexmask.long.byte 0xC 24.--31. 1. "FOURTH_DWORD_FOURTH_BYTE,Byte 3 of Header log register of Fourth 32 bit Data Word. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." hexmask.long.byte 0xC 16.--23. 1. "FOURTH_DWORD_THIRD_BYTE,Byte 2 of Header log register of Fourth 32 bit Data Word. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." newline hexmask.long.byte 0xC 8.--15. 1. "FOURTH_DWORD_SECOND_BYTE,Byte 1 of Header log register of Fourth 32 bit Data Word. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." hexmask.long.byte 0xC 0.--7. 1. "FOURTH_DWORD_FIRST_BYTE,Byte 0 of Header log register of Fourth 32 bit Data Word. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." group.long (0x2C+0x100)++0x7 line.long 0x0 "ROOT_ERR_CMD_OFF,Root Error Command Register. For a description of this standard PCIe register. see the PCI Express Specification." hexmask.long 0x0 3.--31. 1. "RSVDP_3,Reserved for future use." bitfld.long 0x0 2. "FATAL_ERR_REPORTING_EN,Fatal Error Reporting Enable. For a description of this standard PCIe register field see the PCI Express Specification." "0,1" newline bitfld.long 0x0 1. "NON_FATAL_ERR_REPORTING_EN,Non-Fatal Error Reporting Enable. For a description of this standard PCIe register field see the PCI Express Specification." "0,1" bitfld.long 0x0 0. "CORR_ERR_REPORTING_EN,Correctable Error Reporting Enable. For a description of this standard PCIe register field see the PCI Express Specification." "0,1" line.long 0x4 "ROOT_ERR_STATUS_OFF,Root Error Status Register. For a description of this standard PCIe register. see the PCI Express Specification." hexmask.long.byte 0x4 27.--31. 1. "ADV_ERR_INT_MSG_NUM,Advanced Error Interrupt Message Number. For a description of this standard PCIe register field see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN.." hexmask.long.tbyte 0x4 7.--26. 1. "RSVDP_7,Reserved for future use." newline bitfld.long 0x4 6. "FATAL_ERR_MSG_RX,One or more Fatal Error Messages Received. For a description of this standard PCIe register field see the PCI Express Specification." "0,1" bitfld.long 0x4 5. "NON_FATAL_ERR_MSG_RX,One or more Non-Fatal Error Messages Received. For a description of this standard PCIe register field see the PCI Express Specification." "0,1" newline bitfld.long 0x4 4. "FIRST_UNCORR_FATAL,First Uncorrectable Error is Fatal. For a description of this standard PCIe register field see the PCI Express Specification." "0,1" bitfld.long 0x4 3. "MUL_ERR_FATAL_NON_FATAL_RX,Multiple Fatal or Non-Fatal Errors Received. For a description of this standard PCIe register field see the PCI Express Specification." "0,1" newline bitfld.long 0x4 2. "ERR_FATAL_NON_FATAL_RX,Fatal or Non-Fatal Error Received. For a description of this standard PCIe register field see the PCI Express Specification." "0,1" bitfld.long 0x4 1. "MUL_ERR_COR_RX,Multiple Correctable Errors Received. For a description of this standard PCIe register field see the PCI Express Specification." "0,1" newline bitfld.long 0x4 0. "ERR_COR_RX,Correctable Error Received. For a description of this standard PCIe register field see the PCI Express Specification." "0,1" rgroup.long (0x34+0x100)++0x13 line.long 0x0 "ERR_SRC_ID_OFF,Error Source Identification Register. For a description of this standard PCIe register. see the PCI Express Specification." hexmask.long.word 0x0 16.--31. 1. "ERR_FATAL_NON_FATAL_SOURCE_ID,Source of Fatal/Non-Fatal Error. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." hexmask.long.word 0x0 0.--15. 1. "ERR_COR_SOURCE_ID,Source of Correctable Error. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." line.long 0x4 "TLP_PREFIX_LOG_1_OFF,TLP Prefix Log Register 1. For a description of this standard PCIe register. see the PCI Express Specification." hexmask.long.byte 0x4 24.--31. 1. "CFG_TLP_PFX_LOG_1_FOURTH_BYTE,Byte 3 of Error TLP Prefix Log 1. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." hexmask.long.byte 0x4 16.--23. 1. "CFG_TLP_PFX_LOG_1_THIRD_BYTE,Byte 2 of Error TLP Prefix Log 1. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." newline hexmask.long.byte 0x4 8.--15. 1. "CFG_TLP_PFX_LOG_1_SECOND_BYTE,Byte 1 of Error TLP Prefix Log 1. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." hexmask.long.byte 0x4 0.--7. 1. "CFG_TLP_PFX_LOG_1_FIRST_BYTE,Byte 0 of Error TLP Prefix Log 1. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." line.long 0x8 "TLP_PREFIX_LOG_2_OFF,TLP Prefix Log Register 2. For a description of this standard PCIe register. see the PCI Express Specification." hexmask.long.byte 0x8 24.--31. 1. "CFG_TLP_PFX_LOG_2_FOURTH_BYTE,Byte 3 Error TLP Prefix Log 2. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." hexmask.long.byte 0x8 16.--23. 1. "CFG_TLP_PFX_LOG_2_THIRD_BYTE,Byte 2 Error TLP Prefix Log 2. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." newline hexmask.long.byte 0x8 8.--15. 1. "CFG_TLP_PFX_LOG_2_SECOND_BYTE,Byte 1 Error TLP Prefix Log 2. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." hexmask.long.byte 0x8 0.--7. 1. "CFG_TLP_PFX_LOG_2_FIRST_BYTE,Byte 0 Error TLP Prefix Log 2. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." line.long 0xC "TLP_PREFIX_LOG_3_OFF,TLP Prefix Log Register 3. For a description of this standard PCIe register. see the PCI Express Specification." hexmask.long.byte 0xC 24.--31. 1. "CFG_TLP_PFX_LOG_3_FOURTH_BYTE,Byte 3 Error TLP Prefix Log 3. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." hexmask.long.byte 0xC 16.--23. 1. "CFG_TLP_PFX_LOG_3_THIRD_BYTE,Byte 2 Error TLP Prefix Log 3. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." newline hexmask.long.byte 0xC 8.--15. 1. "CFG_TLP_PFX_LOG_3_SECOND_BYTE,Byte 1 Error TLP Prefix Log 3. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." hexmask.long.byte 0xC 0.--7. 1. "CFG_TLP_PFX_LOG_3_FIRST_BYTE,Byte 0 Error TLP Prefix Log 3. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." line.long 0x10 "TLP_PREFIX_LOG_4_OFF,TLP Prefix Log Register 4. For a description of this standard PCIe register. see the PCI Express Specification." hexmask.long.byte 0x10 24.--31. 1. "CFG_TLP_PFX_LOG_4_FOURTH_BYTE,Byte 3 Error TLP Prefix Log 4. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." hexmask.long.byte 0x10 16.--23. 1. "CFG_TLP_PFX_LOG_4_THIRD_BYTE,Byte 2 Error TLP Prefix Log 4. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." newline hexmask.long.byte 0x10 8.--15. 1. "CFG_TLP_PFX_LOG_4_SECOND_BYTE,Byte 1 Error TLP Prefix Log 4. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." hexmask.long.byte 0x10 0.--7. 1. "CFG_TLP_PFX_LOG_4_FIRST_BYTE,Byte 0 Error TLP Prefix Log 4. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." tree.end tree "PF0_MSI_CAP (PF MSI Capability Structure)" group.long (0x0+0x50)++0x13 line.long 0x0 "PCI_MSI_CAP_ID_NEXT_CTRL_REG,MSI Capability Header and Message Control Register." hexmask.long.byte 0x0 27.--31. 1. "RSVDP_27,Reserved for future use." bitfld.long 0x0 26. "PCI_MSI_EXT_DATA_EN,Extended Message Data Enable. - If set the function is enabled to provide Extended Message Data. - If clear the function is not enabled to provide Extended Message Data. Note: The access attributes of this field are as follows: -.." "0,1" bitfld.long 0x0 25. "PCI_MSI_EXT_DATA_CAP,Extended Message Data Capable. - If set the function is capable of providing Extended Message Data. - If clear the function does not support providing Extended Message Data. Note: The access attributes of this field are as follows:.." "0,1" newline rbitfld.long 0x0 24. "PCI_PVM_SUPPORT,Per-Vector Masking Capable. - If set the function supports MSI Per-Vector Masking. - If clear the function does not support MSI Per-Vector Masking. This bit must be set if the function is a PF or VF within an SR-IOV Device." "0,1" bitfld.long 0x0 23. "PCI_MSI_64_BIT_ADDR_CAP,64 bit address capable. - If set the function is capable of sending a 64-bit message address. - If clear the function is not capable of sending a 64-bit message address. This bit must be set if the function is a PCI Express.." "0,1" bitfld.long 0x0 20.--22. "PCI_MSI_MULTIPLE_MSG_EN,Multiple Message Enable. Software writes to this field to indicate the number of allocated vectors (equal to or less than the number of requested vectors). The number of allocated vectors is aligned to a power of two. If a.." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 17.--19. "PCI_MSI_MULTIPLE_MSG_CAP,Multiple Message Capable. System software reads this field to determine the number of requested vectors. The number of requested vectors must be aligned to a power of two (if a function requires three vectors it requests four by.." "0,1,2,3,4,5,6,7" bitfld.long 0x0 16. "PCI_MSI_ENABLE,MSI Enable. - If set and the MSI-X Enable bit in the MSI-X Message Control register is clear the function is permitted to use MSI to request service and is prohibited from using INTx interrupts. System configuration software sets this bit.." "0,1" hexmask.long.byte 0x0 8.--15. 1. "PCI_MSI_CAP_NEXT_OFFSET,Next Capability Pointer. This field contains the offset to the next PCI Capability structure or 00h if no other items exist in the linked list of Capabilities. Note: The access attributes of this field are as follows: - Wire: No.." newline hexmask.long.byte 0x0 0.--7. 1. "PCI_MSI_CAP_ID,Capability ID. Indicates the MSI Capability structure. This field returns a Capability ID of 05h indicating that this is an MSI Capability structure." line.long 0x4 "MSI_CAP_OFF_04H_REG,Message Address Register for MSI (Offset 04h)." hexmask.long 0x4 2.--31. 1. "PCI_MSI_CAP_OFF_04H,Message Address - System-specified message address. If the Message Enable bit (bit 16 of the PCI_MSI_CAP_ID_NEXT_CTRL_REG register) is set the contents of this field specify the DWORD-aligned address (Address[31:02]) for the MSI.." rbitfld.long 0x4 0.--1. "RSVDP_0,Reserved for future use." "0,1,2,3" line.long 0x8 "MSI_CAP_OFF_08H_REG,For a function that supports a 32-bit message address. - bits[31:16] of this register represent the Extended Message Data. and - bits[15:0] of this register represent the Message Data For a function that supports a 64-bit message.." hexmask.long.word 0x8 16.--31. 1. "PCI_MSI_CAP_OFF_0AH,For a function that supports a 32-bit message address this field contains Extended Message Data (System-specified message data). For the MSI Capability structures without per-vector masking it must be implemented if the Extended.." hexmask.long.word 0x8 0.--15. 1. "PCI_MSI_CAP_OFF_08H,For a function that supports a 32-bit message address this field contains Message Data (System-specified message data). If the Message Enable bit (bit 16 of the PCI_MSI_CAP_ID_NEXT_CTRL_REG) is set the function sends a DWORD Memory.." line.long 0xC "MSI_CAP_OFF_0CH_REG,For a function that supports a 32-bit message address. this register contains the Mask Bits when the Per-Vector Masking Capable bit (bit 24 of PCI_MSI_CAP_ID_NEXT_CTRL_REG) is set. For a function that supports a 64-bit message.." hexmask.long.word 0xC 16.--31. 1. "PCI_MSI_CAP_OFF_0EH,For a function that supports a 32-bit message address this field contains the upper Mask Bits when the Per Vector Masking Capable bit (PCI_MSI_CAP_ID_NEXT_CTRL_REG.PCI_PVM_SUPPORT) is set. For a function that supports a 64-bit.." hexmask.long.word 0xC 0.--15. 1. "PCI_MSI_CAP_OFF_0CH,For a function that supports a 32-bit message address this field contains the lower Mask Bits when the Per Vector Masking Capable bit (PCI_MSI_CAP_ID_NEXT_CTRL_REG.PCI_PVM_SUPPORT) is set. For a function that supports a 64-bit.." line.long 0x10 "MSI_CAP_OFF_10H_REG,For a function that supports a 32-bit message address. this register contains the Pending Bits when the Per-Vector Masking Capable bit (bit 24 of PCI_MSI_CAP_ID_NEXT_CTRL_REG) is set. For a function that supports a 64-bit message.." hexmask.long 0x10 0.--31. 1. "PCI_MSI_CAP_OFF_10H,Used for MSI when the Per Vector Masking Capable bit (PCI_MSI_CAP_ID_NEXT_CTRL_REG.PCI_PVM_SUPPORT) is set. For 32-bit contains Pending Bits. For 64-bit contains Mask Bits. For a description of this standard PCIe register field see.." rgroup.long (0x14+0x50)++0x3 line.long 0x0 "MSI_CAP_OFF_14H_REG,Pending Bits Register for MSI. This register is used for a function that supports a 64-bit message address when the Per-Vector Masking Capable bit (bit 24 of PCI_MSI_CAP_ID_NEXT_CTRL_REG) is set." hexmask.long 0x0 0.--31. 1. "PCI_MSI_CAP_OFF_14H,Pending Bits. For each pending bit that is set the function has a pending associated message." tree.end tree "PF0_DMA_CAP (DMA Port Logic Structure)" group.long (0x0+0xC8000)++0x3 line.long 0x0 "DMA_CTRL_DATA_ARB_PRIOR_OFF,DMA Arbitration Scheme for TRGT1 Interface. This register is used to control traffic priorities among various sources that are delivered to your application through TRGT1 where 0x0 represents the highest priority. - Non-DMA Rx.." hexmask.long.tbyte 0x0 12.--31. 1. "RSVDP_12,Reserved for future use." bitfld.long 0x0 9.--11. "RDBUFF_TRGT_WEIGHT,DMA Read Channel MWr Requests. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 6.--8. "RD_CTRL_TRGT_WEIGHT,DMA Read Channel MRd Requests. For LL element/descriptor access. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" "0,1,2,3,4,5,6,7" bitfld.long 0x0 3.--5. "WR_CTRL_TRGT_WEIGHT,DMA Write Channel MRd Requests. For DMA data requests and LL element/descriptor access. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 0.--2. "RTRGT1_WEIGHT,Non-DMA Rx Requests. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" "0,1,2,3,4,5,6,7" group.long (0x8+0xC8000)++0xB line.long 0x0 "DMA_CTRL_OFF,DMA Number of Channels Register." hexmask.long.byte 0x0 26.--31. 1. "RSVDP_26,Reserved for future use." bitfld.long 0x0 25. "DIS_C2W_CACHE_RD,Disable DMA Read Channels 'completion to memory write' context cache pre-fetch function. Note: For internal debugging only. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" "0,1" newline bitfld.long 0x0 24. "DIS_C2W_CACHE_WR,Disable DMA Write Channels 'completion to memory write' context cache pre-fetch function. Note: For internal debugging only. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" "0,1" hexmask.long.byte 0x0 20.--23. 1. "RSVDP_20,Reserved for future use." newline hexmask.long.byte 0x0 16.--19. 1. "NUM_DMA_RD_CHAN,Number of Read Channels. You can read this register to determine the number of read channels the DMA controller has been configured to support." hexmask.long.word 0x0 4.--15. 1. "RSVDP_4,Reserved for future use." newline hexmask.long.byte 0x0 0.--3. 1. "NUM_DMA_WR_CHAN,Number of Write Channels. You can read this register to determine the number of write channels the DMA controller has been configured to support." line.long 0x4 "DMA_WRITE_ENGINE_EN_OFF,DMA Write Engine Enable Register." hexmask.long.byte 0x4 24.--31. 1. "RSVDP_24,Reserved for future use." bitfld.long 0x4 23. "DMA_WRITE_ENGINE_EN_HSHAKE_CH7,Enable Handshake for DMA Write Engine Channel 7. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" "0,1" newline bitfld.long 0x4 22. "DMA_WRITE_ENGINE_EN_HSHAKE_CH6,Enable Handshake for DMA Write Engine Channel 6. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" "0,1" bitfld.long 0x4 21. "DMA_WRITE_ENGINE_EN_HSHAKE_CH5,Enable Handshake for DMA Write Engine Channel 5. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" "0,1" newline bitfld.long 0x4 20. "DMA_WRITE_ENGINE_EN_HSHAKE_CH4,Enable Handshake for DMA Write Engine Channel 4. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" "0,1" bitfld.long 0x4 19. "DMA_WRITE_ENGINE_EN_HSHAKE_CH3,Enable Handshake for DMA Write Engine Channel 3. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" "0,1" newline bitfld.long 0x4 18. "DMA_WRITE_ENGINE_EN_HSHAKE_CH2,Enable Handshake for DMA Write Engine Channel 2. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" "0,1" bitfld.long 0x4 17. "DMA_WRITE_ENGINE_EN_HSHAKE_CH1,Enable Handshake for DMA Write Engine Channel 1. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" "0,1" newline bitfld.long 0x4 16. "DMA_WRITE_ENGINE_EN_HSHAKE_CH0,Enable Handshake for DMA Write Engine Channel 0. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" "0,1" hexmask.long.word 0x4 1.--15. 1. "RSVDP_1,Reserved for future use." newline bitfld.long 0x4 0. "DMA_WRITE_ENGINE,DMA Write Engine Enable. - 1: Enable - 0: Disable (Soft Reset) For normal operation you must initially set this bit to '1' before any other software setup actions. You do not need to toggle or rewrite to this bit during normal.." "Disable,Enable" line.long 0x8 "DMA_WRITE_DOORBELL_OFF,DMA Write Doorbell Register." bitfld.long 0x8 31. "WR_STOP,Stop. Set in conjunction with the Doorbell Number field. The DMA write channel stops issuing requests sets the channel status to 'Stopped' and asserts the 'Abort' interrupt if it is enabled. Before setting the Stop bit you must read the.." "0,1" hexmask.long 0x8 3.--30. 1. "RSVDP_3,Reserved for future use." newline bitfld.long 0x8 0.--2. "WR_DOORBELL_NUM,Doorbell Number. You must write the channel number to this register to start the DMA write transfer for that channel. The DMA detects a write to this register field even if the value of this field does not change. You do not need to.." "0,1,2,3,4,5,6,7" group.long (0x18+0xC8000)++0x7 line.long 0x0 "DMA_WRITE_CHANNEL_ARB_WEIGHT_LOW_OFF,DMA Write Engine Channel Arbitration Weight Low Register. The 5-bit channel weight (for write channels 0-3) specifies the maximum number of TLP requests that the DMA can issue for that channel before it must return to.." hexmask.long.word 0x0 20.--31. 1. "RSVDP_20,Reserved for future use." hexmask.long.byte 0x0 15.--19. 1. "WRITE_CHANNEL3_WEIGHT,Channel 3 Weight. The weight is initialized by software before ringing the doorbell. The value is used by the channel weighted round robin arbiter to select the next channel read request. A value of '0' means that one TLP is issued.." newline hexmask.long.byte 0x0 10.--14. 1. "WRITE_CHANNEL2_WEIGHT,Channel 2 Weight. The weight is initialized by software before ringing the doorbell. The value is used by the channel weighted round robin arbiter to select the next channel read request. A value of '0' means that one TLP is issued.." hexmask.long.byte 0x0 5.--9. 1. "WRITE_CHANNEL1_WEIGHT,Channel 1 Weight. The weight is initialized by software before ringing the doorbell. The value is used by the channel weighted round robin arbiter to select the next channel read request. A value of '0' means that one TLP is issued.." newline hexmask.long.byte 0x0 0.--4. 1. "WRITE_CHANNEL0_WEIGHT,Channel 0 Weight. The weight is initialized by software before ringing the doorbell. The value is used by the channel weighted round robin arbiter to select the next channel read request. A value of '0' means that one TLP is issued.." line.long 0x4 "DMA_WRITE_CHANNEL_ARB_WEIGHT_HIGH_OFF,DMA Write Engine Channel Arbitration Weight High Register. The 5-bit channel weight (for write channels 4-7) specifies the maximum number of TLP requests that the DMA can issue for that channel before it must return.." hexmask.long.word 0x4 20.--31. 1. "RSVDP_20,Reserved for future use." hexmask.long.byte 0x4 15.--19. 1. "WRITE_CHANNEL7_WEIGHT,Channel 7 Weight. The weight is initialized by software before ringing the doorbell. The value is used by the channel weighted round robin arbiter to select the next channel read request. A value of '0' means that one TLP is issued.." newline hexmask.long.byte 0x4 10.--14. 1. "WRITE_CHANNEL6_WEIGHT,Channel 6 Weight. The weight is initialized by software before ringing the doorbell. The value is used by the channel weighted round robin arbiter to select the next channel read request. A value of '0' means that one TLP is issued.." hexmask.long.byte 0x4 5.--9. 1. "WRITE_CHANNEL5_WEIGHT,Channel 5 Weight. The weight is initialized by software before ringing the doorbell. The value is used by the channel weighted round robin arbiter to select the next channel read request. A value of '0' means that one TLP is issued.." newline hexmask.long.byte 0x4 0.--4. 1. "WRITE_CHANNEL4_WEIGHT,Channel 4 Weight. The weight is initialized by software before ringing the doorbell. The value is used by the channel weighted round robin arbiter to select the next channel read request. A value of '0' means that one TLP is issued.." group.long (0x2C+0xC8000)++0x7 line.long 0x0 "DMA_READ_ENGINE_EN_OFF,DMA Read Engine Enable Register." hexmask.long.byte 0x0 24.--31. 1. "RSVDP_24,Reserved for future use." bitfld.long 0x0 23. "DMA_READ_ENGINE_EN_HSHAKE_CH7,Enable Handshake for DMA Read Engine Channel 7. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" "0,1" newline bitfld.long 0x0 22. "DMA_READ_ENGINE_EN_HSHAKE_CH6,Enable Handshake for DMA Read Engine Channel 6. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" "0,1" bitfld.long 0x0 21. "DMA_READ_ENGINE_EN_HSHAKE_CH5,Enable Handshake for DMA Read Engine Channel 5. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" "0,1" newline bitfld.long 0x0 20. "DMA_READ_ENGINE_EN_HSHAKE_CH4,Enable Handshake for DMA Read Engine Channel 4. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" "0,1" bitfld.long 0x0 19. "DMA_READ_ENGINE_EN_HSHAKE_CH3,Enable Handshake for DMA Read Engine Channel 3. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" "0,1" newline bitfld.long 0x0 18. "DMA_READ_ENGINE_EN_HSHAKE_CH2,Enable Handshake for DMA Read Engine Channel 2. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" "0,1" bitfld.long 0x0 17. "DMA_READ_ENGINE_EN_HSHAKE_CH1,Enable Handshake for DMA Read Engine Channel 1. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" "0,1" newline bitfld.long 0x0 16. "DMA_READ_ENGINE_EN_HSHAKE_CH0,Enable Handshake for DMA Read Engine Channel 0. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" "0,1" hexmask.long.word 0x0 1.--15. 1. "RSVDP_1,Reserved for future use." newline bitfld.long 0x0 0. "DMA_READ_ENGINE,DMA Read Engine Enable. - 1: Enable - 0: Disable (Soft Reset) For normal operation you must initially set this bit to '1' before any other software setup actions. You do not need to toggle or rewrite to this bit during normal operation." "Disable,Enable" line.long 0x4 "DMA_READ_DOORBELL_OFF,DMA Read Doorbell Register." bitfld.long 0x4 31. "RD_STOP,Stop. Set in conjunction with the Doorbell Number field. The DMA read channel stops issuing requests sets the channel status to 'Stopped' and asserts the 'Abort' interrupt if it is enabled. Before setting the Stop bit you must read the channel.." "0,1" hexmask.long 0x4 3.--30. 1. "RSVDP_3,Reserved for future use." newline bitfld.long 0x4 0.--2. "RD_DOORBELL_NUM,Doorbell Number. You must write 0x0 to this register to start the DMA read transfer for that channel. The DMA detects a write to this register field even if the value of this field does not change. The range of this field is 0x0 to 0x7.." "0,1,2,3,4,5,6,7" group.long (0x38+0xC8000)++0x7 line.long 0x0 "DMA_READ_CHANNEL_ARB_WEIGHT_LOW_OFF,DMA Read Engine Channel Arbitration Weight Low Register. The 5-bit channel weight (for read channels 0-3) specifies the maximum number of TLP requests that the DMA can issue for that channel before it must return to.." hexmask.long.word 0x0 20.--31. 1. "RSVDP_20,Reserved for future use." hexmask.long.byte 0x0 15.--19. 1. "READ_CHANNEL3_WEIGHT,Channel 3 Weight. The weight is initialized by software before ringing the doorbell. The value is used by the channel weighted round robin arbiter to select the next channel read request. Note: The access attributes of this field are.." newline hexmask.long.byte 0x0 10.--14. 1. "READ_CHANNEL2_WEIGHT,Channel 2 Weight. The weight is initialized by software before ringing the doorbell. The value is used by the channel weighted round robin arbiter to select the next channel read request. Note: The access attributes of this field are.." hexmask.long.byte 0x0 5.--9. 1. "READ_CHANNEL1_WEIGHT,Channel 1 Weight. The weight is initialized by software before ringing the doorbell. The value is used by the channel weighted round robin arbiter to select the next channel read request. Note: The access attributes of this field are.." newline hexmask.long.byte 0x0 0.--4. 1. "READ_CHANNEL0_WEIGHT,Channel 0 Weight. The weight is initialized by software before ringing the doorbell. The value is used by the channel weighted round robin arbiter to select the next channel read request. Note: The access attributes of this field are.." line.long 0x4 "DMA_READ_CHANNEL_ARB_WEIGHT_HIGH_OFF,DMA Read Engine Channel Arbitration Weight High Register. The 5-bit channel weight (for read channels 4-7) specifies the maximum number of TLP requests that the DMA can issue for that channel before it must return to.." hexmask.long.word 0x4 20.--31. 1. "RSVDP_20,Reserved for future use." hexmask.long.byte 0x4 15.--19. 1. "READ_CHANNEL7_WEIGHT,Channel 7 Weight. The weight is initialized by software before ringing the doorbell. The value is used by the channel weighted round robin arbiter to select the next channel read request. Note: The access attributes of this field are.." newline hexmask.long.byte 0x4 10.--14. 1. "READ_CHANNEL6_WEIGHT,Channel 6 Weight. The weight is initialized by software before ringing the doorbell. The value is used by the channel weighted round robin arbiter to select the next channel read request. Note: The access attributes of this field are.." hexmask.long.byte 0x4 5.--9. 1. "READ_CHANNEL5_WEIGHT,Channel 5 Weight. The weight is initialized by software before ringing the doorbell. The value is used by the channel weighted round robin arbiter to select the next channel read request. Note: The access attributes of this field are.." newline hexmask.long.byte 0x4 0.--4. 1. "READ_CHANNEL4_WEIGHT,Channel 4 Weight. The weight is initialized by software before ringing the doorbell. The value is used by the channel weighted round robin arbiter to select the next channel read request. Note: The access attributes of this field are.." group.long (0x4C+0xC8000)++0x3 line.long 0x0 "DMA_WRITE_INT_STATUS_OFF,DMA Write Interrupt Status Register." hexmask.long.byte 0x0 24.--31. 1. "RSVDP_24,Reserved for future use." hexmask.long.byte 0x0 16.--23. 1. "WR_ABORT_INT_STATUS,Abort Interrupt Status. The DMA write channel has detected an error or you manually stopped the transfer as described in 'Error Handling Assistance by Remote Software'. Each bit corresponds to a DMA channel. Bit [0] corresponds to.." newline hexmask.long.byte 0x0 8.--15. 1. "RSVDP_8,Reserved for future use." hexmask.long.byte 0x0 0.--7. 1. "WR_DONE_INT_STATUS,Done Interrupt Status. The DMA write channel has successfully completed the DMA transfer. For more details see 'Interrupts and Error Handling'. Each bit corresponds to a DMA channel. Bit [0] corresponds to channel 0. - Enabling: For.." group.long (0x54+0xC8000)++0x7 line.long 0x0 "DMA_WRITE_INT_MASK_OFF,DMA Write Interrupt Mask Register." hexmask.long.byte 0x0 24.--31. 1. "RSVDP_24,Reserved for future use." hexmask.long.byte 0x0 16.--23. 1. "WR_ABORT_INT_MASK,Abort Interrupt Mask. Prevents the Abort interrupt status field in the DMA write interrupt status register from asserting the edma_int output. Each bit corresponds to a DMA channel. Bit [0] corresponds to channel 0. Note: The access.." newline hexmask.long.byte 0x0 8.--15. 1. "RSVDP_8,Reserved for future use." hexmask.long.byte 0x0 0.--7. 1. "WR_DONE_INT_MASK,Done Interrupt Mask. Prevents the Done interrupt status field in the DMA write interrupt status register from asserting the edma_int output. Each bit corresponds to a DMA channel. Bit [0] corresponds to channel 0. Note: The access.." line.long 0x4 "DMA_WRITE_INT_CLEAR_OFF,DMA Write Interrupt Clear Register." hexmask.long.byte 0x4 24.--31. 1. "RSVDP_24,Reserved for future use." hexmask.long.byte 0x4 16.--23. 1. "WR_ABORT_INT_CLEAR,Abort Interrupt Clear. You must write a 1'b1 to clear the corresponding bit in the Abort interrupt status field of the DMA write interrupt status register. Each bit corresponds to a DMA channel. Bit [0] corresponds to channel 0. Note:.." newline hexmask.long.byte 0x4 8.--15. 1. "RSVDP_8,Reserved for future use." hexmask.long.byte 0x4 0.--7. 1. "WR_DONE_INT_CLEAR,Done Interrupt Clear. You must write a 1'b1 to clear the corresponding bit in the Done interrupt status field of the DMA write interrupt status register. Each bit corresponds to a DMA channel. Bit [0] corresponds to channel 0. Note:.." rgroup.long (0x5C+0xC8000)++0x3 line.long 0x0 "DMA_WRITE_ERR_STATUS_OFF,DMA Write Error Status Register" hexmask.long.byte 0x0 24.--31. 1. "RSVDP_24,Reserved for future use." hexmask.long.byte 0x0 16.--23. 1. "LINKLIST_ELEMENT_FETCH_ERR_DETECT,Linked List Element Fetch Error Detected. The DMA write channel has received an error response from the AXI bus (or TRGT1 interface when the AXI Bridge is not used) while reading a linked list element from local memory." newline hexmask.long.byte 0x0 8.--15. 1. "RSVDP_8,Reserved for future use." hexmask.long.byte 0x0 0.--7. 1. "APP_READ_ERR_DETECT,Application Read Error Detected. The DMA write channel has received an error response from the AXI bus (or TRGT1 interface when the AXI Bridge is not used) while reading data from it. Each bit corresponds to a DMA channel. Bit [0].." group.long (0x60+0xC8000)++0x1F line.long 0x0 "DMA_WRITE_DONE_IMWR_LOW_OFF,DMA Write Done IMWr Address Low Register." hexmask.long 0x0 0.--31. 1. "DMA_WRITE_DONE_LOW_REG,The DMA uses this field to generate bits [31:0] of the address field for the Done IMWr TLP. Bits [1:0] must be '00' as this address must be dword aligned. Note: The access attributes of this field are as follows: - Wire: No access." line.long 0x4 "DMA_WRITE_DONE_IMWR_HIGH_OFF,DMA Write Done IMWr Interrupt Address High Register." hexmask.long 0x4 0.--31. 1. "DMA_WRITE_DONE_HIGH_REG,The DMA uses this field to generate bits [63:32] of the address field for the Done IMWr TLP. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" line.long 0x8 "DMA_WRITE_ABORT_IMWR_LOW_OFF,DMA Write Abort IMWr Address Low Register." hexmask.long 0x8 0.--31. 1. "DMA_WRITE_ABORT_LOW_REG,The DMA uses this field to generate bits [31:0] of the address field for the Abort IMWr TLP it generates. Bits [1:0] must be '00' as this address must be dword aligned. Note: The access attributes of this field are as follows: -.." line.long 0xC "DMA_WRITE_ABORT_IMWR_HIGH_OFF,DMA Write Abort IMWr Address High Register." hexmask.long 0xC 0.--31. 1. "DMA_WRITE_ABORT_HIGH_REG,The DMA uses this field to generate bits [63:32] of the address field for the Abort IMWr TLP. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" line.long 0x10 "DMA_WRITE_CH01_IMWR_DATA_OFF,DMA Write Channel 1 and 0 IMWr Data Register." hexmask.long.word 0x10 16.--31. 1. "WR_CHANNEL_1_DATA,The DMA uses this field to generate the data field for the Done or Abort IMWr TLPs it generates for write channel 1. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" hexmask.long.word 0x10 0.--15. 1. "WR_CHANNEL_0_DATA,The DMA uses this field to generate the data field for the Done or Abort IMWr TLPs it generates for write channel 0. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" line.long 0x14 "DMA_WRITE_CH23_IMWR_DATA_OFF,DMA Write Channel 3 and 2 IMWr Data Register." hexmask.long.word 0x14 16.--31. 1. "WR_CHANNEL_3_DATA,The DMA uses this field to generate the data field for the Done or Abort IMWr TLPs it generates for write channel 3. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" hexmask.long.word 0x14 0.--15. 1. "WR_CHANNEL_2_DATA,The DMA uses this field to generate the data field for the Done or Abort IMWr TLPs it generates for write channel 2. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" line.long 0x18 "DMA_WRITE_CH45_IMWR_DATA_OFF,DMA Write Channel 5 and 4 IMWr Data Register." hexmask.long.word 0x18 16.--31. 1. "WR_CHANNEL_5_DATA,The DMA uses this field to generate the data field for the Done or Abort IMWr TLPs it generates for write channel 5. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" hexmask.long.word 0x18 0.--15. 1. "WR_CHANNEL_4_DATA,The DMA uses this field to generate the data field for the Done or Abort IMWr TLPs it generates for write channel 4. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" line.long 0x1C "DMA_WRITE_CH67_IMWR_DATA_OFF,DMA Write Channel 7 and 6 IMWr Data Register." hexmask.long.word 0x1C 16.--31. 1. "WR_CHANNEL_7_DATA,The DMA uses this field to generate the data field for the Done or Abort IMWr TLPs it generates for write channel 7. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" hexmask.long.word 0x1C 0.--15. 1. "WR_CHANNEL_6_DATA,The DMA uses this field to generate the data field for the Done or Abort IMWr TLPs it generates for write channel 6. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" group.long (0x90+0xC8000)++0x3 line.long 0x0 "DMA_WRITE_LINKED_LIST_ERR_EN_OFF,DMA Write Linked List Error Enable Register. The LIE and RIE bits in the LL element enable the channel 'done' interrupts (local and remote). The LLLAIE and LLRAIE bits enable the channel 'abort' interrupts (local and.." hexmask.long.byte 0x0 24.--31. 1. "RSVDP_24,Reserved for future use." hexmask.long.byte 0x0 16.--23. 1. "WR_CHANNEL_LLLAIE,Write Channel LL Local Abort Interrupt Enable (LLLAIE). You enable the write channel local abort interrupt through this bit. The LIE and RIE bits in the LL element enable the write channel done interrupts. Each bit corresponds to a DMA.." newline hexmask.long.byte 0x0 8.--15. 1. "RSVDP_8,Reserved for future use." hexmask.long.byte 0x0 0.--7. 1. "WR_CHANNEL_LLRAIE,Write Channel LL Remote Abort Interrupt Enable (LLRAIE). You enable the write channel remote abort interrupt through this bit. The LIE and RIE bits in the LL element enable the write channel done interrupts. Each bit corresponds to a.." group.long (0xA0+0xC8000)++0x3 line.long 0x0 "DMA_READ_INT_STATUS_OFF,DMA Read Interrupt Status Register." hexmask.long.byte 0x0 24.--31. 1. "RSVDP_24,Reserved for future use." hexmask.long.byte 0x0 16.--23. 1. "RD_ABORT_INT_STATUS,Abort Interrupt Status. The DMA read channel has detected an error or you manually stopped the transfer as described in 'Stopping the DMA Transfer (Software Stop)'. Each bit corresponds to a DMA channel. Bit [0] corresponds to.." newline hexmask.long.byte 0x0 8.--15. 1. "RSVDP_8,Reserved for future use." hexmask.long.byte 0x0 0.--7. 1. "RD_DONE_INT_STATUS,Done Interrupt Status. The DMA read channel has successfully completed the DMA read transfer. Each bit corresponds to a DMA channel. Bit [0] corresponds to channel 0. - Enabling: For details see 'Interrupts and Error Handling'. -.." group.long (0xA8+0xC8000)++0x7 line.long 0x0 "DMA_READ_INT_MASK_OFF,DMA Read Interrupt Mask Register." hexmask.long.byte 0x0 24.--31. 1. "RSVDP_24,Reserved for future use." hexmask.long.byte 0x0 16.--23. 1. "RD_ABORT_INT_MASK,Abort Interrupt Mask. Prevents the Abort interrupt status field in the DMA read interrupt status register from asserting the edma_int output. Each bit corresponds to a DMA channel. Bit [0] corresponds to channel 0. Note: The access.." newline hexmask.long.byte 0x0 8.--15. 1. "RSVDP_8,Reserved for future use." hexmask.long.byte 0x0 0.--7. 1. "RD_DONE_INT_MASK,Done Interrupt Mask. Prevents the Done interrupt status field in the DMA read interrupt status register from asserting the edma_int output. Each bit corresponds to a DMA channel. Bit [0] corresponds to channel 0. Note: The access.." line.long 0x4 "DMA_READ_INT_CLEAR_OFF,DMA Read Interrupt Clear Register." hexmask.long.byte 0x4 24.--31. 1. "RSVDP_24,Reserved for future use." hexmask.long.byte 0x4 16.--23. 1. "RD_ABORT_INT_CLEAR,Abort Interrupt Clear. You must write a 1'b1 to clear the corresponding bit in the Abort interrupt status field of the DMA read interrupt status register. Each bit corresponds to a DMA channel. Bit [0] corresponds to channel 0. Note:.." newline hexmask.long.byte 0x4 8.--15. 1. "RSVDP_8,Reserved for future use." hexmask.long.byte 0x4 0.--7. 1. "RD_DONE_INT_CLEAR,Done Interrupt Clear. You must write a 1'b1 to clear the corresponding bit in the Done interrupt status field of the DMA read interrupt status register. Each bit corresponds to a DMA channel. Bit [0] corresponds to channel 0. Note:.." rgroup.long (0xB4+0xC8000)++0x7 line.long 0x0 "DMA_READ_ERR_STATUS_LOW_OFF,DMA Read Error Status Low Register." hexmask.long.byte 0x0 24.--31. 1. "RSVDP_24,Reserved for future use." hexmask.long.byte 0x0 16.--23. 1. "LINK_LIST_ELEMENT_FETCH_ERR_DETECT,Linked List Element Fetch Error Detected. - The DMA read channel has received an error response from the AXI bus while reading a linked list element from local memory. Each bit corresponds to a DMA channel. Bit [0].." newline hexmask.long.byte 0x0 8.--15. 1. "RSVDP_8,Reserved for future use." hexmask.long.byte 0x0 0.--7. 1. "APP_WR_ERR_DETECT,Application Write Error Detected. The DMA read channel has received an error response from the AXI bus (or TRGT1 interface when the AXI Bridge is not used) while writing data to it. This error is fatal. You must restart the transfer.." line.long 0x4 "DMA_READ_ERR_STATUS_HIGH_OFF,DMA Read Error Status High Register." hexmask.long.byte 0x4 24.--31. 1. "DATA_POISIONING,Data Poisoning. The DMA read channel has detected data poisoning in the completion from the remote device (in response to the MRd request). The DMA read channel will drop the completion and then be halted. The CX_FLT_MASK_UR_POIS filter.." hexmask.long.byte 0x4 16.--23. 1. "CPL_TIMEOUT,Completion Time Out. The DMA read channel has timed-out while waiting for the remote device to respond to the MRd request or a malformed CplD has been received. For more details see 'Linked List Mode'. Each bit corresponds to a DMA channel." newline hexmask.long.byte 0x4 8.--15. 1. "CPL_ABORT,Completer Abort. The DMA read channel has received a PCIe completer abort completion status from the remote device in response to the MRd request. For more details see 'Linked List Mode'. Each bit corresponds to a DMA channel. Bit [0].." hexmask.long.byte 0x4 0.--7. 1. "UNSUPPORTED_REQ,Unsupported Request. The DMA read channel has received a PCIe unsupported request completion status from the remote device in response to the MRd request. For more details see 'Linked List Mode'. Each bit corresponds to a DMA channel." group.long (0xC4+0xC8000)++0x3 line.long 0x0 "DMA_READ_LINKED_LIST_ERR_EN_OFF,DMA Read Linked List Error Enable Register. The LIE and RIE bits in the LL element enable the channel 'done' interrupts (local and remote). The LLLAIE and LLRAIE bits enable the channel 'abort' interrupts (local and remote)." hexmask.long.byte 0x0 24.--31. 1. "RSVDP_24,Reserved for future use." hexmask.long.byte 0x0 16.--23. 1. "RD_CHANNEL_LLLAIE,Read Channel LL Local Abort Interrupt Enable (LLLAIE). You enable the read channel Local Abort interrupt through this bit. The LIE and RIE bits in the LL element enable the read channel done interrupts. Each bit corresponds to a DMA.." newline hexmask.long.byte 0x0 8.--15. 1. "RSVDP_8,Reserved for future use." hexmask.long.byte 0x0 0.--7. 1. "RD_CHANNEL_LLRAIE,Read Channel LL Remote Abort Interrupt Enable (LLRAIE). You enable the read channel Remote Abort interrupt through this bit. The LIE and RIE bits in the LL element enable the read channel done interrupts. Each bit corresponds to a DMA.." group.long (0xCC+0xC8000)++0x1F line.long 0x0 "DMA_READ_DONE_IMWR_LOW_OFF,DMA Read Done IMWr Address Low Register." hexmask.long 0x0 0.--31. 1. "DMA_READ_DONE_LOW_REG,The DMA uses this field to generate bits [31:0] of the address field for the Done IMWr TLP. Bits [1:0] must be '00' as this address must be dword aligned. Note: The access attributes of this field are as follows: - Wire: No access." line.long 0x4 "DMA_READ_DONE_IMWR_HIGH_OFF,DMA Read Done IMWr Address High Register." hexmask.long 0x4 0.--31. 1. "DMA_READ_DONE_HIGH_REG,The DMA uses this field to generate bits [63:32] of the address field for the Done IMWr TLP. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" line.long 0x8 "DMA_READ_ABORT_IMWR_LOW_OFF,DMA Read Abort IMWr Address Low Register." hexmask.long 0x8 0.--31. 1. "DMA_READ_ABORT_LOW_REG,The DMA uses this field to generate bits [31:0] of the address field for the Abort IMWr TLP. Bits [1:0] must be '00' as this address must be dword aligned. Note: The access attributes of this field are as follows: - Wire: No.." line.long 0xC "DMA_READ_ABORT_IMWR_HIGH_OFF,DMA Read Abort IMWr Address High Register." hexmask.long 0xC 0.--31. 1. "DMA_READ_ABORT_HIGH_REG,The DMA uses this field to generate bits [63:32] of the address field for the Abort IMWr TLP. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" line.long 0x10 "DMA_READ_CH01_IMWR_DATA_OFF,DMA Read Channel 1 and 0 IMWr Data Register." hexmask.long.word 0x10 16.--31. 1. "RD_CHANNEL_1_DATA,The DMA uses this field to generate the data field for the Done or Abort IMWr TLPs it generates for read channel 1. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" hexmask.long.word 0x10 0.--15. 1. "RD_CHANNEL_0_DATA,The DMA uses this field to generate the data field for the Done or Abort IMWr TLPs it generates for read channel 0. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" line.long 0x14 "DMA_READ_CH23_IMWR_DATA_OFF,DMA Read Channel 3 and 2 IMWr Data Register." hexmask.long.word 0x14 16.--31. 1. "RD_CHANNEL_3_DATA,The DMA uses this field to generate the data field for the Done or Abort IMWr TLPs it generates for read channel 3. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" hexmask.long.word 0x14 0.--15. 1. "RD_CHANNEL_2_DATA,The DMA uses this field to generate the data field for the Done or Abort IMWr TLPs it generates for read channel 2. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" line.long 0x18 "DMA_READ_CH45_IMWR_DATA_OFF,DMA Read Channel 5 and 4 IMWr Data Register." hexmask.long.word 0x18 16.--31. 1. "RD_CHANNEL_5_DATA,The DMA uses this field to generate the data field for the Done or Abort IMWr TLPs it generates for read channel 5. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" hexmask.long.word 0x18 0.--15. 1. "RD_CHANNEL_4_DATA,The DMA uses this field to generate the data field for the Done or Abort IMWr TLPs it generates for read channel 4. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" line.long 0x1C "DMA_READ_CH67_IMWR_DATA_OFF,DMA Read Channel 7 and 6 IMWr Data Register." hexmask.long.word 0x1C 16.--31. 1. "RD_CHANNEL_7_DATA,The DMA uses this field to generate the data field for the Done or Abort IMWr TLPs it generates for read channel 7. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" hexmask.long.word 0x1C 0.--15. 1. "RD_CHANNEL_6_DATA,The DMA uses this field to generate the data field for the Done or Abort IMWr TLPs it generates for read channel 6. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" rgroup.long (0x108+0xC8000)++0x7 line.long 0x0 "DMA_WRITE_ENGINE_HSHAKE_CNT_LOW_OFF,DMA Write Engine Handshake Counter Channel 0/1/2/3 Register." bitfld.long 0x0 29.--31. "RSVDP_29,Reserved for future use." "0,1,2,3,4,5,6,7" hexmask.long.byte 0x0 24.--28. 1. "DMA_WRITE_ENGINE_HSHAKE_CNT_CH3,DMA handshake counter for DMA Write Engine Channel 3. If CC_DMA_HSHAKE =1 the data transfer in Linked List mode starts only when the counter is non-zero." newline bitfld.long 0x0 21.--23. "RSVDP_21,Reserved for future use." "0,1,2,3,4,5,6,7" hexmask.long.byte 0x0 16.--20. 1. "DMA_WRITE_ENGINE_HSHAKE_CNT_CH2,DMA handshake counter for DMA Write Engine Channel 2. If CC_DMA_HSHAKE =1 the data transfer in Linked List mode starts only when the counter is non-zero." newline bitfld.long 0x0 13.--15. "RSVDP_13,Reserved for future use." "0,1,2,3,4,5,6,7" hexmask.long.byte 0x0 8.--12. 1. "DMA_WRITE_ENGINE_HSHAKE_CNT_CH1,DMA handshake counter for DMA Write Engine Channel 1. If CC_DMA_HSHAKE =1 the data transfer in Linked List mode starts only when the counter is non-zero." newline bitfld.long 0x0 5.--7. "RSVDP_5,Reserved for future use." "0,1,2,3,4,5,6,7" hexmask.long.byte 0x0 0.--4. 1. "DMA_WRITE_ENGINE_HSHAKE_CNT_CH0,DMA handshake counter for DMA Write Engine Channel 0. If CC_DMA_HSHAKE =1 the data transfer in Linked List mode starts only when the counter is non-zero." line.long 0x4 "DMA_WRITE_ENGINE_HSHAKE_CNT_HIGH_OFF,DMA Write Engine Handshake Counter Channel 4/5/6/7 Register." bitfld.long 0x4 29.--31. "RSVDP_29,Reserved for future use." "0,1,2,3,4,5,6,7" hexmask.long.byte 0x4 24.--28. 1. "DMA_WRITE_ENGINE_HSHAKE_CNT_CH7,DMA handshake counter for DMA Write Engine Channel 7. If CC_DMA_HSHAKE =1 the data transfer in Linked List mode starts only when the counter is non-zero." newline bitfld.long 0x4 21.--23. "RSVDP_21,Reserved for future use." "0,1,2,3,4,5,6,7" hexmask.long.byte 0x4 16.--20. 1. "DMA_WRITE_ENGINE_HSHAKE_CNT_CH6,DMA handshake counter for DMA Write Engine Channel 6. If CC_DMA_HSHAKE =1 the data transfer in Linked List mode starts only when the counter is non-zero." newline bitfld.long 0x4 13.--15. "RSVDP_13,Reserved for future use." "0,1,2,3,4,5,6,7" hexmask.long.byte 0x4 8.--12. 1. "DMA_WRITE_ENGINE_HSHAKE_CNT_CH5,DMA handshake counter for DMA Write Engine Channel 5. If CC_DMA_HSHAKE =1 the data transfer in Linked List mode starts only when the counter is non-zero." newline bitfld.long 0x4 5.--7. "RSVDP_5,Reserved for future use." "0,1,2,3,4,5,6,7" hexmask.long.byte 0x4 0.--4. 1. "DMA_WRITE_ENGINE_HSHAKE_CNT_CH4,DMA handshake counter for DMA Write Engine Channel 4. If CC_DMA_HSHAKE =1 the data transfer in Linked List mode starts only when the counter is non-zero." rgroup.long (0x118+0xC8000)++0x7 line.long 0x0 "DMA_READ_ENGINE_HSHAKE_CNT_LOW_OFF,DMA Read Engine Handshake Counter Channel 0/1/2/3 Register." bitfld.long 0x0 29.--31. "RSVDP_29,Reserved for future use." "0,1,2,3,4,5,6,7" hexmask.long.byte 0x0 24.--28. 1. "DMA_READ_ENGINE_HSHAKE_CNT_CH3,DMA handshake counter for DMA Read Engine Channel 3. If CC_DMA_HSHAKE =1 the data transfer in Linked List mode starts only when the counter is non-zero." newline bitfld.long 0x0 21.--23. "RSVDP_21,Reserved for future use." "0,1,2,3,4,5,6,7" hexmask.long.byte 0x0 16.--20. 1. "DMA_READ_ENGINE_HSHAKE_CNT_CH2,DMA handshake counter for DMA Read Engine Channel 2. If CC_DMA_HSHAKE =1 the data transfer in Linked List mode starts only when the counter is non-zero." newline bitfld.long 0x0 13.--15. "RSVDP_13,Reserved for future use." "0,1,2,3,4,5,6,7" hexmask.long.byte 0x0 8.--12. 1. "DMA_READ_ENGINE_HSHAKE_CNT_CH1,DMA handshake counter for DMA Read Engine Channel 1. If CC_DMA_HSHAKE =1 the data transfer in Linked List mode starts only when the counter is non-zero." newline bitfld.long 0x0 5.--7. "RSVDP_5,Reserved for future use." "0,1,2,3,4,5,6,7" hexmask.long.byte 0x0 0.--4. 1. "DMA_READ_ENGINE_HSHAKE_CNT_CH0,DMA handshake counter for DMA Read Engine Channel 0. If CC_DMA_HSHAKE =1 the data transfer in Linked List mode starts only when the counter is non-zero." line.long 0x4 "DMA_READ_ENGINE_HSHAKE_CNT_HIGH_OFF,DMA Read Engine Handshake Counter Channel 4/5/6/7 Register." bitfld.long 0x4 29.--31. "RSVDP_29,Reserved for future use." "0,1,2,3,4,5,6,7" hexmask.long.byte 0x4 24.--28. 1. "DMA_READ_ENGINE_HSHAKE_CNT_CH7,DMA handshake counter for DMA Read Engine Channel 7. If CC_DMA_HSHAKE =1 the data transfer in Linked List mode starts only when the counter is non-zero." newline bitfld.long 0x4 21.--23. "RSVDP_21,Reserved for future use." "0,1,2,3,4,5,6,7" hexmask.long.byte 0x4 16.--20. 1. "DMA_READ_ENGINE_HSHAKE_CNT_CH6,DMA handshake counter for DMA Read Engine Channel 6. If CC_DMA_HSHAKE =1 the data transfer in Linked List mode starts only when the counter is non-zero." newline bitfld.long 0x4 13.--15. "RSVDP_13,Reserved for future use." "0,1,2,3,4,5,6,7" hexmask.long.byte 0x4 8.--12. 1. "DMA_READ_ENGINE_HSHAKE_CNT_CH5,DMA handshake counter for DMA Read Engine Channel 5. If CC_DMA_HSHAKE =1 the data transfer in Linked List mode starts only when the counter is non-zero." newline bitfld.long 0x4 5.--7. "RSVDP_5,Reserved for future use." "0,1,2,3,4,5,6,7" hexmask.long.byte 0x4 0.--4. 1. "DMA_READ_ENGINE_HSHAKE_CNT_CH4,DMA handshake counter for DMA Read Engine Channel 4. If CC_DMA_HSHAKE =1 the data transfer in Linked List mode starts only when the counter is non-zero." repeat 8. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 )(list 0x0 0x200 0x400 0x600 0x800 0xA00 0xC00 0xE00 ) group.long ($2+0x200+0xC8000)++0x3 line.long 0x0 "DMA_CH_CONTROL1_OFF_WRCH_$1,DMA Write Channel Control 1 Register." bitfld.long 0x0 30.--31. "DMA_AT,Address Translation TLP Header Bit (AT) The DMA uses this TLP header field when generating MRd/MWr (not IMWr) TLPs. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" "0,1,2,3" bitfld.long 0x0 27.--29. "DMA_TC,Traffic Class TLP Header Bit (TC) The DMA uses this TLP header field when generating MRd/MWr (not IMWr) TLPs. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 26. "DMA_RESERVED5,Reserved. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" "0,1" bitfld.long 0x0 25. "DMA_RO,Relaxed Ordering TLP Header Bit (RO) The DMA uses this TLP header field when generating MRd/MWr (not IMWr) TLPs. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" "0,1" newline bitfld.long 0x0 24. "DMA_NS_SRC,Source No Snoop TLP Header Bit (DMA_NS_SRC). The DMA uses this TLP header field when generating MRd (SAR addressing space) (not IMWr) TLPs. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" "0,1" bitfld.long 0x0 23. "DMA_NS_DST,Destination No Snoop TLP Header Bit (DMA_NS_DST). The DMA uses this TLP header field when generating MWr (DAR addressing space) (not IMWr) TLPs. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" "0,1" newline bitfld.long 0x0 22. "DMA_MEM_TYPE,Master AXI ACE-Lite Cache Coherency Control. This field sets the DMA channel memory type of the address space of the data transfer as follows: - 0x0:peripheral type - 0x1:memory type For more details see 'ACE-Lite Features and Limitations'.." "peripheral type,memory type" hexmask.long.byte 0x0 17.--21. 1. "DMA_RESERVED2,Reserved. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" newline hexmask.long.byte 0x0 12.--16. 1. "DMA_FUNC_NUM,Function Number (FN). The controller uses this field when generating the requester ID for the MRd/MWr DMA TLP. When you have enabled SR-IOV then this field is ignored if you have set the VFE field in the 'DMA Write Channel Control 2.." bitfld.long 0x0 10.--11. "DMA_RESERVED1,Reserved. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" "0,1,2,3" newline bitfld.long 0x0 9. "LLE,Linked List Enable (LLE). - 0: Disable linked list operation - 1: Enable linked list operation Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" "Disable linked list operation,Enable linked list operation" bitfld.long 0x0 8. "CCS,Consumer Cycle State (CCS). Used in linked list mode only. It is used to synchronize the producer (software) and the consumer (DMA). For more details see 'PCS-CCS-CB-TCB Producer-Consumer Synchronization'. You must initialize this bit. The DMA.." "0,1" newline bitfld.long 0x0 7. "DMA_RESERVED0,Reserved. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" "0,1" bitfld.long 0x0 5.--6. "CS,Channel Status (CS). The channel status bits identify the current operational state of the DMA channel. The operation state encoding for each DMA channel is a s follows: - 00: Reserved - 01: Running. This channel is active and transferring data. - 10:.." "Reserved,Running,?,?" newline bitfld.long 0x0 4. "RIE,Remote Interrupt Enable (RIE). You must set this bit to enable the generation of the Done or Abort Remote interrupts. For more details see 'Interrupts and Error Handling'. In LL mode the DMA overwrites this with the RIE of the LL element. The RIE.." "0,1" bitfld.long 0x0 3. "LIE,Local Interrupt Enable (LIE). You must set this bit to enable the generation of the Done or Abort Local interrupts. For more details see 'Interrupts and Error Handling'. In LL mode the DMA overwrites this with the LIE of the LL element. The LIE bit.." "0,1" newline bitfld.long 0x0 2. "LLP,Load Link Pointer (LLP). Used in linked list mode only. Indicates that this linked list element is a link element and its LL element pointer dwords are pointing to the next (non-contiguous) element. The DMA loads this field with the LLP of the.." "0,1" bitfld.long 0x0 1. "TCB,Toggle Cycle Bit (TCB). Indicates to the DMA to toggle its interpretation of the CB. Used in linked list mode only. It is used to synchronize the producer (software) and the consumer (DMA). For more details see 'PCS-CCS-CB-TCB Producer-Consumer.." "0,1" newline bitfld.long 0x0 0. "CB,Cycle Bit (CB). Used in linked list mode only. It is used to synchronize the producer (software) and the consumer (DMA). For more details see 'PCS-CCS-CB-TCB Producer-Consumer Synchronization'. The DMA loads this field with the CB of the linked list.." "0,1" repeat.end repeat 8. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 )(list 0x0 0x200 0x400 0x600 0x800 0xA00 0xC00 0xE00 ) group.long ($2+0x208+0xC8000)++0x3 line.long 0x0 "DMA_TRANSFER_SIZE_OFF_WRCH_$1,DMA Write Transfer Size Register." hexmask.long 0x0 0.--31. 1. "DMA_TRANSFER_SIZE,DMA Transfer Size. You program this register with the size of the DMA transfer. The maximum DMA transfer size is 4Gbytes. The minimum transfer size is one byte (0x1). This field is automatically decremented by the DMA as the DMA write.." repeat.end repeat 8. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 )(list 0x0 0x200 0x400 0x600 0x800 0xA00 0xC00 0xE00 ) group.long ($2+0x20C+0xC8000)++0x3 line.long 0x0 "DMA_SAR_LOW_OFF_WRCH_$1,DMA Write SAR Low Register." hexmask.long 0x0 0.--31. 1. "SRC_ADDR_REG_LOW,Source Address Register (Lower 32 bits). Indicates the next address to be read from. The DMA increments the SAR as the DMA transfer progresses. In LL mode the DMA overwrites this with the corresponding dword of the LL element. - DMA.." repeat.end repeat 8. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 )(list 0x0 0x200 0x400 0x600 0x800 0xA00 0xC00 0xE00 ) group.long ($2+0x210+0xC8000)++0x3 line.long 0x0 "DMA_SAR_HIGH_OFF_WRCH_$1,DMA Write SAR High Register." hexmask.long 0x0 0.--31. 1. "SRC_ADDR_REG_HIGH,Source Address Register (Higher 32 bits). In LL mode the DMA overwrites this with the corresponding dword of the LL element. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" repeat.end repeat 8. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 )(list 0x0 0x200 0x400 0x600 0x800 0xA00 0xC00 0xE00 ) group.long ($2+0x214+0xC8000)++0x3 line.long 0x0 "DMA_DAR_LOW_OFF_WRCH_$1,DMA Write DAR Low Register." hexmask.long 0x0 0.--31. 1. "DST_ADDR_REG_LOW,Destination Address Register (Lower 32 bits). Indicates the next address to be written to. The DMA increments the DAR as the DMA transfer progresses. In LL mode the DMA overwrites this with the corresponding dword of the LL element. -.." repeat.end repeat 8. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 )(list 0x0 0x200 0x400 0x600 0x800 0xA00 0xC00 0xE00 ) group.long ($2+0x218+0xC8000)++0x3 line.long 0x0 "DMA_DAR_HIGH_OFF_WRCH_$1,DMA Write DAR High Register." hexmask.long 0x0 0.--31. 1. "DST_ADDR_REG_HIGH,Destination Address Register (Higher 32 bits). In LL mode the DMA overwrites this with the corresponding dword of the LL element. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" repeat.end repeat 8. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 )(list 0x0 0x200 0x400 0x600 0x800 0xA00 0xC00 0xE00 ) group.long ($2+0x21C+0xC8000)++0x3 line.long 0x0 "DMA_LLP_LOW_OFF_WRCH_$1,DMA Write Linked List Pointer Low Register." hexmask.long 0x0 0.--31. 1. "LLP_LOW,Lower bits of the address of the linked list transfer list in local memory. Used in linked list mode only. Updated by the DMA to point to the next element in the transfer list after the previous element is consumed. - When the current element is.." repeat.end repeat 8. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 )(list 0x0 0x200 0x400 0x600 0x800 0xA00 0xC00 0xE00 ) group.long ($2+0x220+0xC8000)++0x3 line.long 0x0 "DMA_LLP_HIGH_OFF_WRCH_$1,DMA Write Linked List Pointer High Register." hexmask.long 0x0 0.--31. 1. "LLP_HIGH,Upper 32 bits of the address of the linked list transfer list in local memory. Used in linked list mode only. Updated by the DMA to point to the next element in the transfer list as elements are consumed. Note: The access attributes of this.." repeat.end repeat 8. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 )(list 0x0 0x200 0x400 0x600 0x800 0xA00 0xC00 0xE00 ) group.long ($2+0x300+0xC8000)++0x3 line.long 0x0 "DMA_CH_CONTROL1_OFF_RDCH_$1,DMA Read Channel Control 1 Register." bitfld.long 0x0 30.--31. "DMA_AT,Address Translation TLP Header Bit (AT) The DMA uses this TLP header field when generating MRd/MWr (not IMWr) TLPs. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" "0,1,2,3" bitfld.long 0x0 27.--29. "DMA_TC,Traffic Class TLP Header Bit (TC) The DMA uses this TLP header field when generating MRd/MWr (not IMWr) TLPs. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 26. "DMA_RESERVED5,Reserved. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" "0,1" bitfld.long 0x0 25. "DMA_RO,Relaxed Ordering TLP Header Bit (RO) The DMA uses this TLP header field when generating MRd/MWr (not IMWr) TLPs. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" "0,1" newline bitfld.long 0x0 24. "DMA_NS_SRC,Source No Snoop TLP Header Bit (DMA_NS_SRC). The DMA uses this TLP header field when generating MRd (SAR addressing space) (not IMWr) TLPs. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" "0,1" bitfld.long 0x0 23. "DMA_NS_DST,Destination No Snoop TLP Header Bit (DMA_NS_DST). The DMA uses this TLP header field when generating MWr (DAR addressing space) (not IMWr) TLPs. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" "0,1" newline bitfld.long 0x0 22. "DMA_MEM_TYPE,Master AXI ACE-Lite Cache Coherency Control. This field sets the DMA channel memory type of the address space of the data transfer as follows: - 0x0:peripheral type - 0x1:memory type For more details see 'ACE-Lite Features and Limitations'.." "peripheral type,memory type" hexmask.long.byte 0x0 17.--21. 1. "DMA_RESERVED2,Reserved. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" newline hexmask.long.byte 0x0 12.--16. 1. "DMA_FUNC_NUM,Function Number (FN). The controller uses this field when generating the requester ID for the MRd/MWr DMA TLP. When you have enabled SR-IOV then this field is ignored if you have set the VFE field in the 'DMA Read Channel Control 2.." bitfld.long 0x0 10.--11. "DMA_RESERVED1,Reserved. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" "0,1,2,3" newline bitfld.long 0x0 9. "LLE,Linked List Enable (LLE). - 0: Disable linked list operation - 1: Enable linked list operation Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" "Disable linked list operation,Enable linked list operation" bitfld.long 0x0 8. "CCS,Consumer Cycle State (CCS). Used in linked list mode only. It is used to synchronize the producer (software) and the consumer (DMA). For more details see 'PCS-CCS-CB-TCB Producer-Consumer Synchronization'. You must initialize this bit. The DMA.." "0,1" newline bitfld.long 0x0 7. "DMA_RESERVED0,Reserved. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" "0,1" bitfld.long 0x0 5.--6. "CS,Channel Status (CS). The channel status bits identify the current operational state of the DMA channel. The operation state encoding for each DMA channel is a s follows: - 00: Reserved - 01: Running. This channel is active and transferring data. - 10:.." "Reserved,Running,?,?" newline bitfld.long 0x0 4. "RIE,Remote Interrupt Enable (RIE). You must set this bit to enable the generation of the Done or Abort Remote interrupts. For more details see 'Interrupts and Error Handling'. In LL mode the DMA overwrites this with the RIE of the LL element. The RIE.." "0,1" bitfld.long 0x0 3. "LIE,Local Interrupt Enable (LIE). You must set this bit to enable the generation of the Done or Abort Local interrupts. For more details see 'Interrupts and Error Handling'. In LL mode the DMA overwrites this with the LIE of the LL element. The LIE bit.." "0,1" newline bitfld.long 0x0 2. "LLP,Load Link Pointer (LLP). Used in linked list mode only. Indicates that this linked list element is a link element and its LL element pointer dwords are pointing to the next (non-contiguous) element. The DMA loads this field with the LLP of the.." "0,1" bitfld.long 0x0 1. "TCB,Toggle Cycle Bit (TCB). Indicates to the DMA to toggle its interpretation of the CB. Used in linked list mode only. It is used to synchronize the producer (software) and the consumer (DMA). For more details see 'PCS-CCS-CB-TCB Producer-Consumer.." "0,1" newline bitfld.long 0x0 0. "CB,Cycle Bit (CB). Used in linked list mode only. It is used to synchronize the producer (software) and the consumer (DMA). For more details see 'PCS-CCS-CB-TCB Producer-Consumer Synchronization'. The DMA loads this field with the CB of the linked list.." "0,1" repeat.end repeat 8. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 )(list 0x0 0x200 0x400 0x600 0x800 0xA00 0xC00 0xE00 ) group.long ($2+0x308+0xC8000)++0x3 line.long 0x0 "DMA_TRANSFER_SIZE_OFF_RDCH_$1,DMA Read Transfer Size Register." hexmask.long 0x0 0.--31. 1. "DMA_TRANSFER_SIZE,DMA Transfer Size. You program this register with the size of the DMA transfer. The maximum DMA transfer size is 4Gbytes. The minimum transfer size is one byte (0x1). This field is automatically decremented by the DMA as the DMA read.." repeat.end repeat 8. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 )(list 0x0 0x200 0x400 0x600 0x800 0xA00 0xC00 0xE00 ) group.long ($2+0x30C+0xC8000)++0x3 line.long 0x0 "DMA_SAR_LOW_OFF_RDCH_$1,DMA Read SAR Low Register." hexmask.long 0x0 0.--31. 1. "SRC_ADDR_REG_LOW,Source Address Register (Lower 32 bits). Indicates the next address to be read from. The DMA increments the SAR as the DMA transfer progresses. In LL mode the DMA overwrites this with the corresponding dword of the LL element. - DMA.." repeat.end repeat 8. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 )(list 0x0 0x200 0x400 0x600 0x800 0xA00 0xC00 0xE00 ) group.long ($2+0x310+0xC8000)++0x3 line.long 0x0 "DMA_SAR_HIGH_OFF_RDCH_$1,DMA Read SAR High Register." hexmask.long 0x0 0.--31. 1. "SRC_ADDR_REG_HIGH,Source Address Register (Higher 32 bits). In LL mode the DMA overwrites this with the corresponding dword of the LL element. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" repeat.end repeat 8. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 )(list 0x0 0x200 0x400 0x600 0x800 0xA00 0xC00 0xE00 ) group.long ($2+0x314+0xC8000)++0x3 line.long 0x0 "DMA_DAR_LOW_OFF_RDCH_$1,DMA Read DAR Low Register." hexmask.long 0x0 0.--31. 1. "DST_ADDR_REG_LOW,Destination Address Register (Lower 32 bits). Indicates the next address to be written to. The DMA increments the DAR as the DMA transfer progresses. In LL mode the DMA overwrites this with the corresponding dword of the LL element. -.." repeat.end repeat 8. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 )(list 0x0 0x200 0x400 0x600 0x800 0xA00 0xC00 0xE00 ) group.long ($2+0x318+0xC8000)++0x3 line.long 0x0 "DMA_DAR_HIGH_OFF_RDCH_$1,DMA Read DAR High Register." hexmask.long 0x0 0.--31. 1. "DST_ADDR_REG_HIGH,Destination Address Register (Higher 32 bits). In LL mode the DMA overwrites this with the corresponding dword of the LL element. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" repeat.end repeat 8. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 )(list 0x0 0x200 0x400 0x600 0x800 0xA00 0xC00 0xE00 ) group.long ($2+0x31C+0xC8000)++0x3 line.long 0x0 "DMA_LLP_LOW_OFF_RDCH_$1,DMA Read Linked List Pointer Low Register." hexmask.long 0x0 0.--31. 1. "LLP_LOW,Lower bits of the address of the linked list transfer list in local memory. Used in linked list mode only. Updated by the DMA to point to the next element in the transfer list after the previous element is consumed. - When the current element is.." repeat.end repeat 8. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 )(list 0x0 0x200 0x400 0x600 0x800 0xA00 0xC00 0xE00 ) group.long ($2+0x320+0xC8000)++0x3 line.long 0x0 "DMA_LLP_HIGH_OFF_RDCH_$1,DMA Read Linked List Pointer High Register." hexmask.long 0x0 0.--31. 1. "LLP_HIGH,Upper 32 bits of the address of the linked list transfer list in local memory. Used in linked list mode only. Updated by the DMA to point to the next element in the transfer list as elements are consumed. Note: The access attributes of this.." repeat.end tree.end tree "PF0_ATU_CAP (ATU Por Logic Structure)" repeat 8. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 )(list 0x0 0x200 0x400 0x600 0x800 0xA00 0xC00 0xE00 ) group.long ($2+0xC0000)++0x3 line.long 0x0 "IATU_REGION_CTRL_1_OFF_OUTBOUND_$1,iATU Region Control 1 Register." bitfld.long 0x0 20. "CTRL_1_FUNC_NUM,Function Number. - When the address of an outbound TLP is matched to this region and the FUNC_BYPASS field in the 'iATU Control 2 Register' is '0' then the function number used in generating the function part of the requester ID (RID).." "0,1" newline bitfld.long 0x0 13. "INCREASE_REGION_SIZE,Increase the maximum ATU Region size. When set the maximum ATU Region size is determined by CX_ATU_MAX_REGION_SIZE. When clear the maximum ATU Region size is 4 GB (default). Note: This register field is sticky." "0,1" newline bitfld.long 0x0 9.--10. "ATTR,When the address of an outbound TLP is matched to this region then the ATTR field of the TLP is changed to the value in this register. Note: This register field is sticky." "0,1,2,3" newline bitfld.long 0x0 8. "TD,This is a reserved field. Do not use. Note: This register field is sticky." "0,1" newline bitfld.long 0x0 5.--7. "TC,When the address of an outbound TLP is matched to this region then the TC field of the TLP is changed to the value in this register. Note: This register field is sticky." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x0 0.--4. 1. "TYPE,When the address of an outbound TLP is matched to this region then the TYPE field of the TLP is changed to the value in this register. Note: This register field is sticky." repeat.end repeat 8. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 )(list 0x0 0x200 0x400 0x600 0x800 0xA00 0xC00 0xE00 ) group.long ($2+0x4+0xC0000)++0x3 line.long 0x0 "IATU_REGION_CTRL_2_OFF_OUTBOUND_$1,iATU Region Control 2 Register." bitfld.long 0x0 31. "REGION_EN,Region Enable. This bit must be set to '1' for address translation to take place. Note: This register field is sticky." "0,1" newline bitfld.long 0x0 29. "INVERT_MODE,Invert Mode. When set the address matching region is inverted. Therefore an address match occurs when the untranslated address is in the region outside the defined range (Base Address to Limit Address). Note: This register field is sticky." "0,1" newline bitfld.long 0x0 28. "CFG_SHIFT_MODE,CFG Shift Mode. The iATU uses bits [27:12] of the untranslated address (on the XALI0/1/2 interface or AXI slave interface address) to form the BDF number of the outgoing CFG TLP. This supports the Enhanced Configuration Address Mapping.." "0,1" newline bitfld.long 0x0 27. "DMA_BYPASS,DMA Bypass Mode. Allows request TLPs which are initiated by the DMA controller to pass through the iATU untranslated. Note: This field is reserved for the SW product. You must set it to '0'. Note: This register field is sticky." "0,1" newline bitfld.long 0x0 23. "HEADER_SUBSTITUTE_EN,Header Substitute Enable. When enabled and region address is matched the iATU fully substitutes bytes 8-11 (for 3 DWORD header) or bytes 12-15 (for 4 DWORD header) of the outbound TLP header with the contents of the LWR_TARGET_RW.." "LWR_TARGET_RW in the..,LWR_TARGET_RW in the.." newline bitfld.long 0x0 22. "INHIBIT_PAYLOAD,Inhibit TLP Payload Data for TLP's in Matched Region; assign iATU region to be TLP without data. When enabled and region address is matched the iATU marks all TLPs as having no payload data by forcing the TLP header Fmt[1] bit =0.." "Fmt[1] =0/1 so that TLPs with or without data..,Fmt[1] =0 so that only TLP type without data is.." newline bitfld.long 0x0 21. "TLP_HEADER_FIELDS_BYPASS,TLP Header Fields Translation Bypass. In this mode header fields of the translated TLP is taken from your application transmit interface or if AMBA is configured from the AMBA sideband bus (slv_awmisc_info) and not from the.." "0,1" newline bitfld.long 0x0 20. "SNP,Serialize Non-Posted Requests. In this mode when the AXI Bridge is populated same AXI ID Non-Posted Read/Write Requests are transmitted on the wire if there are no other same ID Non-Posted Requests outstanding. Note: This register field is sticky." "0,1" newline bitfld.long 0x0 19. "FUNC_BYPASS,Function Number Translation Bypass. In this mode the function number of the translated TLP is taken from your application transmit interface and not from the CTRL_1_FUNC_NUM field of the 'iATU Control 1 Register' or the VF_NUMBER field of.." "0,1" newline bitfld.long 0x0 16. "TAG_SUBSTITUTE_EN,TAG Substitute Enable. When enabled and region address is matched the iATU substitutes the TAG field of the outbound TLP header with the contents of the TAG field in this register. The expected usage scenario is translation from AXI.." "0,1" newline hexmask.long.byte 0x0 8.--15. 1. "TAG,TAG. The substituted TAG field (byte 6) in the outgoing TLP header when TAG_SUBSTITUTE_EN is set. Note: This register field is sticky." newline hexmask.long.byte 0x0 0.--7. 1. "MSG_CODE,MSG TLPs (Message Code). When the address of an outbound TLP is matched to this region and the translated TLP TYPE field is Msg or MsgD; then the message field of the TLP is changed to the value in this register. Memory TLPs: (ST;Steering Tag)." repeat.end repeat 8. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 )(list 0x0 0x200 0x400 0x600 0x800 0xA00 0xC00 0xE00 ) group.long ($2+0x8+0xC0000)++0x3 line.long 0x0 "IATU_LWR_BASE_ADDR_OFF_OUTBOUND_$1,iATU Lower Base Address Register. The CX_ATU_MIN_REGION_SIZE configuration parameter (Value Range: 4 kB. 8 kB. 16 kB. 32 kB. 64 kB defaults to 64 kB) specifies the minimum size of an address translation region. For.." hexmask.long.tbyte 0x0 12.--31. 1. "LWR_BASE_RW,Forms bits [31:n] of the start address of the address region to be translated. n is log2(CX_ATU_MIN_REGION_SIZE) Note: This register field is sticky." newline hexmask.long.word 0x0 0.--11. 1. "LWR_BASE_HW,Forms bits [n-1:0] of the start address of the address region to be translated. The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary so these bits are always 0. A write to this location is ignored by the PCIe controller." repeat.end repeat 8. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 )(list 0x0 0x200 0x400 0x600 0x800 0xA00 0xC00 0xE00 ) group.long ($2+0xC+0xC0000)++0x3 line.long 0x0 "IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_$1,iATU Upper Base Address Register." hexmask.long 0x0 0.--31. 1. "UPPER_BASE_RW,Forms bits [63:32] of the start (and end) address of the address region to be translated. In systems with a 32-bit address space this register is not used and therefore writing to this register has no effect. Note: This register field is.." repeat.end repeat 8. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 )(list 0x0 0x200 0x400 0x600 0x800 0xA00 0xC00 0xE00 ) group.long ($2+0x10+0xC0000)++0x3 line.long 0x0 "IATU_LIMIT_ADDR_OFF_OUTBOUND_$1,iATU Limit Address Register." hexmask.long.tbyte 0x0 12.--31. 1. "LIMIT_ADDR_RW,Forms upper bits of the end address of the address region to be translated. Note: This register field is sticky." newline hexmask.long.word 0x0 0.--11. 1. "LIMIT_ADDR_HW,Forms lower bits of the end address of the address region to be translated. The end address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary so these bits are always all ones. A write to this location is ignored by the PCIe.." repeat.end repeat 8. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 )(list 0x0 0x200 0x400 0x600 0x800 0xA00 0xC00 0xE00 ) group.long ($2+0x14+0xC0000)++0x3 line.long 0x0 "IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_$1,iATU Lower Target Address Register." hexmask.long 0x0 0.--31. 1. "LWR_TARGET_RW_OUTBOUND,When HEADER_SUBSTITUTE_EN in IATU_REGION_CTRL_2_OFF_OUTBOUND_ is '0' (normal operation): - LWR_TARGET_RW[31:n] forms MSB's of the Lower Target part of the new address of the translated region; - LWR_TARGET_RW[n-1:0] are not used." repeat.end repeat 8. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 )(list 0x0 0x200 0x400 0x600 0x800 0xA00 0xC00 0xE00 ) group.long ($2+0x18+0xC0000)++0x3 line.long 0x0 "IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_$1,iATU Upper Target Address Register." hexmask.long 0x0 0.--31. 1. "UPPER_TARGET_RW,Forms bits [63:32] of the start address (Upper Target part) of the new address of the translated region. Note: This register field is sticky." repeat.end repeat 8. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 )(list 0x0 0x200 0x400 0x600 0x800 0xA00 0xC00 0xE00 ) group.long ($2+0x100+0xC0000)++0x3 line.long 0x0 "IATU_REGION_CTRL_1_OFF_INBOUND_$1,iATU Region Control 1 Register." bitfld.long 0x0 20. "CTRL_1_FUNC_NUM,Function Number. - MEM-I/O: When the Address and BAR matching logic in the controller indicate that a MEM-I/O transaction matches a BAR in the function corresponding to this value then address translation proceeds. This check is only.." "?,When the destination function number as.." newline bitfld.long 0x0 13. "INCREASE_REGION_SIZE,Increase the maximum ATU Region size. When set the maximum ATU Region size is determined by CX_ATU_MAX_REGION_SIZE. When clear the maximum ATU Region size is 4 GB (default). Note: This register field is sticky." "0,1" newline bitfld.long 0x0 9.--10. "ATTR,When the ATTR field of an inbound TLP is matched to this value then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the 'ATTR Match Enable' bit of the 'iATU Control 2 Register' is.." "0,1,2,3" newline bitfld.long 0x0 8. "TD,When the TD field of an inbound TLP is matched to this value then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the 'TD Match Enable' bit of the 'iATU Control 2 Register' is set." "0,1" newline bitfld.long 0x0 5.--7. "TC,When the TC field of an inbound TLP is matched to this value then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the 'TC Match Enable' bit of the 'iATU Control 2 Register' is set." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x0 0.--4. 1. "TYPE,When the TYPE field of an inbound TLP is matched to this value then address translation proceeds (when all other enabled field-matches are successful). Note: This register field is sticky." repeat.end repeat 8. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 )(list 0x0 0x200 0x400 0x600 0x800 0xA00 0xC00 0xE00 ) group.long ($2+0x104+0xC0000)++0x3 line.long 0x0 "IATU_REGION_CTRL_2_OFF_INBOUND_$1,iATU Region Control 2 Register." bitfld.long 0x0 31. "REGION_EN,Region Enable. This bit must be set to '1' for address translation to take place. Note: This register field is sticky." "0,1" newline bitfld.long 0x0 30. "MATCH_MODE,Match Mode. Determines Inbound matching mode for TLPs. The mode depends on the type of TLP that is received as follows: For MEM-I/O TLPs this field is interpreted as follows: - 0: Address Match Mode. The iATU operates using addresses as in.." "Address Match Mode,Vendor ID Match Mode" newline bitfld.long 0x0 29. "INVERT_MODE,Invert Mode. When set the address matching region is inverted. Therefore an address match occurs when the untranslated address is in the region outside the defined range (Base Address to Limit Address). Note: This register field is sticky." "0,1" newline bitfld.long 0x0 28. "CFG_SHIFT_MODE,CFG Shift Mode. This is useful for CFG transactions where the PCIe configuration mechanism maps bits [27:12] of the address to the bus/device and function number. This allows a CFG configuration space to be located in any 256MB window of.." "0,1" newline bitfld.long 0x0 27. "FUZZY_TYPE_MATCH_CODE,Fuzzy Type Match Mode. When enabled the iATU relaxes the matching of the TLP TYPE field against the expected TYPE field so that - CfgRd0 and CfgRd1 TLPs are seen as identical. Similarly with CfgWr0 and CfgWr1. - MWr MRd and MRdLk.." "0,1" newline bitfld.long 0x0 24.--25. "RESPONSE_CODE,Response Code. Defines the type of response to give for accesses matching this region. This overrides the normal RADM filter response. Note that this feature is not available for any region where Single Address Location Translate is.." "Normal RADM filter response is used,Unsupported request,?,?" newline bitfld.long 0x0 23. "SINGLE_ADDR_LOC_TRANS_EN,Single Address Location Translate Enable. When enabled Rx TLPs can be translated to a single address location as determined by the target address register of the iATU region. The main usage scenario is translation of Messages.." "0,1" newline bitfld.long 0x0 21. "MSG_CODE_MATCH_EN,Message Code Match Enable (Msg TLPS). Ensures that a successful message Code TLP field comparison match (see Message Code field of the 'iATU Control 2 Register') occurs (in MSG transactions) for address translation to proceed. ST Match.." "0,1" newline bitfld.long 0x0 19. "FUNC_NUM_MATCH_EN,Function Number Match Enable. Ensures that a successful Function Number TLP field comparison match (see Function Number field of the 'iATU Control 1 Register') occurs (in MEM-I/O and CFG0/CFG1 transactions) for address translation to.." "0,1" newline bitfld.long 0x0 16. "ATTR_MATCH_EN,ATTR Match Enable. Ensures that a successful ATTR TLP field comparison match (see ATTR field of the 'iATU Control 1 Register') occurs for address translation to proceed. Note: This register field is sticky." "0,1" newline bitfld.long 0x0 15. "TD_MATCH_EN,TD Match Enable. Ensures that a successful TD TLP field comparison match (see TD field of the 'iATU Control 1 Register') occurs for address translation to proceed. Note: This register field is sticky." "0,1" newline bitfld.long 0x0 14. "TC_MATCH_EN,TC Match Enable. Ensures that a successful TC TLP field comparison match (see TC field of the 'iATU Control 1 Register') occurs for address translation to proceed. Note: This register field is sticky." "0,1" newline bitfld.long 0x0 13. "MSG_TYPE_MATCH_MODE,Message Type Match Mode. When enabled and if single address location translate enable is set then inbound TLPs of type MSG/MSGd which match the type field of the iatu_region_ctrl_1_OFF_inbound register (=>TYPE[4:3]=2'b10) will be.." "0,1" newline bitfld.long 0x0 8.--10. "BAR_NUM,BAR Number. When the BAR number of an inbound MEM or IO TLP ' that is matched by the normal internal BAR address matching mechanism ' is the same as this field address translation proceeds (when all other enabled field-matches are successful)." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x0 0.--7. 1. "MSG_CODE,MSG TLPs: (Message Code). When the TYPE field of an inbound Msg/MsgD TLP is matched to this value then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the 'Message Code Match.." repeat.end repeat 8. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 )(list 0x0 0x200 0x400 0x600 0x800 0xA00 0xC00 0xE00 ) group.long ($2+0x108+0xC0000)++0x3 line.long 0x0 "IATU_LWR_BASE_ADDR_OFF_INBOUND_$1,iATU Lower Base Address Register. The CX_ATU_MIN_REGION_SIZE configuration parameter (Value Range: 4 kB. 8 kB. 16 kB. 32 kB. 64 kB defaults to 64 kB) specifies the minimum size of an address translation region. For.." hexmask.long.tbyte 0x0 12.--31. 1. "LWR_BASE_RW,Forms bits [31:n] of the start address of the address region to be translated. n is log2(CX_ATU_MIN_REGION_SIZE) Note: This register field is sticky." newline hexmask.long.word 0x0 0.--11. 1. "LWR_BASE_HW,Forms bits [n-1:0] of the start address of the address region to be translated. The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary so these bits are always 0. A write to this location is ignored by the PCIe controller." repeat.end repeat 8. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 )(list 0x0 0x200 0x400 0x600 0x800 0xA00 0xC00 0xE00 ) group.long ($2+0x10C+0xC0000)++0x3 line.long 0x0 "IATU_UPPER_BASE_ADDR_OFF_INBOUND_$1,iATU Upper Base Address Register." hexmask.long 0x0 0.--31. 1. "UPPER_BASE_RW,Forms bits [63:32] of the start (and end) address of the address region to be translated. Note: This register field is sticky." repeat.end repeat 8. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 )(list 0x0 0x200 0x400 0x600 0x800 0xA00 0xC00 0xE00 ) group.long ($2+0x110+0xC0000)++0x3 line.long 0x0 "IATU_LIMIT_ADDR_OFF_INBOUND_$1,iATU Limit Address Register." hexmask.long.tbyte 0x0 12.--31. 1. "LIMIT_ADDR_RW,Forms upper bits of the end address of the address region to be translated. Note: This register field is sticky." newline hexmask.long.word 0x0 0.--11. 1. "LIMIT_ADDR_HW,Forms lower bits of the end address of the address region to be translated. The end address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary so these bits are always all ones. A write to this location is ignored by the PCIe.." repeat.end repeat 8. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 )(list 0x0 0x200 0x400 0x600 0x800 0xA00 0xC00 0xE00 ) group.long ($2+0x114+0xC0000)++0x3 line.long 0x0 "IATU_LWR_TARGET_ADDR_OFF_INBOUND_$1,iATU Lower Target Address Register." hexmask.long.tbyte 0x0 12.--31. 1. "LWR_TARGET_RW,Forms MSB's of the Lower Target part of the new address of the translated region. These bits are always '0'. - Field size depends on log2(CX_ATU_MIN_REGION_SIZE) in address match mode. - Field size depends on log2(BAR_MASK+1) in BAR match.." newline hexmask.long.word 0x0 0.--11. 1. "LWR_TARGET_HW,Forms the LSB's of the Lower Target part of the new address of the translated region. The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary (in address match mode); and to the Bar size boundary (in BAR match mode) so.." repeat.end repeat 8. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 )(list 0x0 0x200 0x400 0x600 0x800 0xA00 0xC00 0xE00 ) group.long ($2+0x118+0xC0000)++0x3 line.long 0x0 "IATU_UPPER_TARGET_ADDR_OFF_INBOUND_$1,iATU Upper Target Address Register." hexmask.long 0x0 0.--31. 1. "UPPER_TARGET_RW,Forms bits [63:32] of the start address (Upper Target part) of the new address of the translated region. In systems with a 32-bit address space this register is not used and therefore writing to this register has no effect. Note: This.." repeat.end tree.end tree "PF0_PORT_LOGIC (Port Logic)" group.long (0x0+0x700)++0x27 line.long 0x0 "ACK_LATENCY_TIMER_OFF,Ack Latency Timer and Replay Timer Register." hexmask.long.word 0x0 16.--31. 1. "REPLAY_TIME_LIMIT,Replay Timer Limit. The replay timer expires when it reaches this limit. The controller initiates a replay upon reception of a NAK or when the replay timer expires. For more details see 'Transmit Replay'. You can modify the effective.." newline hexmask.long.word 0x0 0.--15. 1. "ROUND_TRIP_LATENCY_TIME_LIMIT,Ack Latency Timer Limit. The Ack latency timer expires when it reaches this limit. For more details see 'Ack Scheduling'. You can modify the effective timer limit with the TIMER_MOD_ACK_NAK field of the.." line.long 0x4 "VENDOR_SPEC_DLLP_OFF,Vendor Specific DLLP Register." hexmask.long 0x4 0.--31. 1. "VENDOR_SPEC_DLLP,Vendor Specific DLLP Register. Used to send a specific PCI Express DLLP. Your application writes the 8-bit DLLP Type and 24-bits of Payload data into this register then sets the field VENDOR_SPECIFIC_DLLP_REQ of PORT_LINK_CTRL_OFF to.." line.long 0x8 "PORT_FORCE_OFF,Port Force Link Register." hexmask.long.byte 0x8 24.--31. 1. "RSVDP_24,Reserved for future use." newline bitfld.long 0x8 23. "DO_DESKEW_FOR_SRIS,Use the transitions from TS2 to Logical Idle Symbol SKP OS to Logical Idle Symbol EIEOS to Logical Idle Symbol and FTS Sequence to SKP OS to do deskew instead of using received SKP OS or TS1 to TS2 transition if DO_DESKEW_FOR_SRIS.." "0,1" newline rbitfld.long 0x8 22. "RSVDP_22,Reserved for future use." "0,1" newline hexmask.long.byte 0x8 16.--21. 1. "LINK_STATE,Forced LTSSM State. The LTSSM state that the controller is forced to when you set the FORCE_EN bit (Force Link). LTSSM state encoding is defined by the lts_state variable in workspace/src/Layer1/smlh_ltssm.v. Note: This register field is sticky." newline bitfld.long 0x8 15. "FORCE_EN,Force Link. The controller supports a testing and debug capability to allow your software to force the LTSSM state machine into a specific state and to force the controller to transmit a specific Link Command. Asserting this bit triggers the.." "0,1" newline rbitfld.long 0x8 12.--14. "RSVDP_12,Reserved for future use." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x8 8.--11. 1. "FORCED_LTSSM,Forced Link Command. The link command that the controller is forced to transmit when you set FORCE_EN bit (Force Link). Link command encoding is defined by the ltssm_cmd variable in workspace/src/Layer1/smlh_ltssm.v. Note: This register.." newline hexmask.long.byte 0x8 0.--7. 1. "LINK_NUM,Link Number. Not used for endpoint. Not used for M-PCIe. Note: This register field is sticky." line.long 0xC "ACK_F_ASPM_CTRL_OFF,Ack Frequency and L0-L1 ASPM Control Register." rbitfld.long 0xC 31. "RSVDP_31,Reserved for future use." "0,1" newline bitfld.long 0xC 30. "ENTER_ASPM,ASPM L1 Entry Control. - 1: Controller enters ASPM L1 after a period in which it has been idle. - 0: Controller enters ASPM L1 only after idle period during which both receive and transmit are in L0s. Note: This register field is sticky." "Controller enters ASPM L1 only after idle period..,Controller enters ASPM L1 after a period in.." newline bitfld.long 0xC 27.--29. "L1_ENTRANCE_LATENCY,L1 Entrance Latency. Value range is: - 000: 1 us - 001: 2 us - 010: 4 us - 011: 8 us - 100: 16 us - 101: 32 us - 110 or 111: 64 us Note: Programming this timer with a value greater that 32us has no effect unless extended sync is used.." "0,1,2,3,4,5,6,7" newline bitfld.long 0xC 24.--26. "L0S_ENTRANCE_LATENCY,L0s Entrance Latency. Values correspond to: - 000: 1 us - 001: 2 us - 010: 3 us - 011: 4 us - 100: 5 us - 101: 6 us - 110 or 111: 7 us This field is applicable to STALL while in L0 for M-PCIe. Note: This register field is sticky." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0xC 16.--23. 1. "COMMON_CLK_N_FTS,Common Clock N_FTS. This is the N_FTS when common clock is used. The number of Fast Training Sequence ordered sets to be transmitted when transitioning from L0s to L0. The maximum number of FTS ordered-sets that a component can request.." newline hexmask.long.byte 0xC 8.--15. 1. "ACK_N_FTS,N_FTS. The number of Fast Training Sequence ordered sets to be transmitted when transitioning from L0s to L0. The maximum number of FTS ordered-sets that a component can request is 255. The controller does not support a value of zero; a value.." newline hexmask.long.byte 0xC 0.--7. 1. "ACK_FREQ,Ack Frequency. The controller accumulates the number of pending ACKs specified here (up to 255) before scheduling an ACK DLLP. - 0: Indicates that this Ack Frequency Counter feature is turned off. The controller generates a low-priority ACK.." line.long 0x10 "PORT_LINK_CTRL_OFF,Port Link Control Register." hexmask.long.byte 0x10 28.--31. 1. "RSVDP_28,Reserved for future use." newline bitfld.long 0x10 27. "TRANSMIT_LANE_REVERSALE_ENABLE,TRANSMIT_LANE_REVERSALE_ENABLE is an internally reserved field. Do not use. Note: This register field is sticky." "0,1" newline bitfld.long 0x10 26. "EXTENDED_SYNCH,EXTENDED_SYNCH is an internally reserved field. Do not use. Note: This register field is sticky." "0,1" newline bitfld.long 0x10 25. "CORRUPT_LCRC_ENABLE,CORRUPT_LCRC_ENABLE is an internally reserved field. Do not use. Note: This register field is sticky." "0,1" newline bitfld.long 0x10 24. "BEACON_ENABLE,BEACON_ENABLE is an internally reserved field. Do not use. Note: This register field is sticky." "0,1" newline hexmask.long.byte 0x10 16.--21. 1. "LINK_CAPABLE,Link Mode Enable. Sets the number of lanes in the link that you want to connect to the link partner. When you have unused lanes in your system then you must change the value in this register to reflect the number of lanes. You must also.." newline hexmask.long.byte 0x10 12.--15. 1. "RSVDP_12,Reserved for future use." newline hexmask.long.byte 0x10 8.--11. 1. "LINK_RATE,LINK_RATE is an internally reserved field. Do not use. Note: This register field is sticky." newline bitfld.long 0x10 7. "FAST_LINK_MODE,Fast Link Mode. Sets all internal LTSSM millisecond timers to Fast Mode for speeding up simulation. Forces the LTSSM training (link initialization) to use shorter time-outs and to link up faster. The default scaling factor can be changed.." "0,1" newline bitfld.long 0x10 6. "LINK_DISABLE,LINK_DISABLE is an internally reserved field. Do not use. Note: This register field is sticky." "0,1" newline bitfld.long 0x10 5. "DLL_LINK_EN,DLL Link Enable. Enables link initialization. When DLL Link Enable =0 the controller does not transmit InitFC DLLPs and does not establish a link. Note: This register field is sticky." "0,1" newline rbitfld.long 0x10 4. "RSVDP_4,Reserved for future use." "0,1" newline bitfld.long 0x10 3. "RESET_ASSERT,Reset Assert. Triggers a recovery and forces the LTSSM to the hot reset state (downstream port only). Note: This register field is sticky." "0,1" newline bitfld.long 0x10 2. "LOOPBACK_ENABLE,Loopback Enable. Turns on loopback. For more details see 'Loopback'. For M-PCIe to force the master to enter Digital Loopback mode you must set this field to '1' during Configuration.start state(initial discovery/configuration). M-PCIe.." "0,1" newline bitfld.long 0x10 1. "SCRAMBLE_DISABLE,Scramble Disable. Turns off data scrambling. Note: This register field is sticky." "0,1" newline bitfld.long 0x10 0. "VENDOR_SPECIFIC_DLLP_REQ,Vendor Specific DLLP Request. When software writes a '1' to this bit the controller transmits the DLLP contained in the VENDOR_SPEC_DLLP field of VENDOR_SPEC_DLLP_OFF. Reading from this self-clearing register field always.." "0,1" line.long 0x14 "LANE_SKEW_OFF,Lane Skew Register." bitfld.long 0x14 31. "DISABLE_LANE_TO_LANE_DESKEW,Disable Lane-to-Lane Deskew. Causes the controller to disable the internal Lane-to-Lane deskew logic. Note: This register field is sticky." "0,1" newline hexmask.long.byte 0x14 27.--30. 1. "IMPLEMENT_NUM_LANES,Implementation-specific Number of Lanes. Set the implementation-specific number of lanes. Allowed values are: - 4'b0000: 1 lane - 4'b0001: 2 lanes - 4'b0011: 4 lanes - 4'b0111: 8 lanes - 4'b1111: 16 lanes The number of lanes to be.." newline bitfld.long 0x14 26. "ELASTIC_BUFFER_MODE,Selects Elasticity Buffer operating mode: 0: Nominal Half Full Buffer mode 1: Nominal Empty Buffer Mode Note: This register field is sticky." "Nominal Half Full Buffer mode,Nominal Empty Buffer Mode" newline bitfld.long 0x14 25. "ACK_NAK_DISABLE,Ack/Nak Disable. Prevents the controller from sending ACK and NAK DLLPs. Note: This register field is sticky." "0,1" newline bitfld.long 0x14 24. "FLOW_CTRL_DISABLE,Flow Control Disable. Prevents the controller from sending FC DLLPs. Note: This register field is sticky." "0,1" newline hexmask.long.tbyte 0x14 0.--23. 1. "INSERT_LANE_SKEW,INSERT_LANE_SKEW is an internally reserved field. Do not use. Note: This register field is sticky." line.long 0x18 "TIMER_CTRL_MAX_FUNC_NUM_OFF,Timer Control and Max Function Number Register." rbitfld.long 0x18 31. "RSVDP_31,Reserved for future use." "0,1" newline bitfld.long 0x18 29.--30. "FAST_LINK_SCALING_FACTOR,Fast Link Timer Scaling Factor. Sets the scaling factor of LTSSM timer when FAST_LINK_MODE field in PORT_LINK_CTRL_OFF is set to '1'. - 0: Scaling Factor is 1024 (1ms is 1us *a) - 1: Scaling Factor is 256 (1ms is 4us) - 2:.." "Scaling Factor is 1024,Scaling Factor is 256,Scaling Factor is 64,Scaling Factor is 16" newline hexmask.long.byte 0x18 24.--28. 1. "UPDATE_FREQ_TIMER,UPDATE_FREQ_TIMER is an internally reserved field. Do not use. Note: This register field is sticky." newline hexmask.long.byte 0x18 19.--23. 1. "TIMER_MOD_ACK_NAK,Ack Latency Timer Modifier. Increases the timer value for the Ack latency timer in increments of 64 clock cycles. A value of '0' represents no modification to the timer value. For more details see the ROUND_TRIP_LATENCY_TIME_LIMIT.." newline hexmask.long.byte 0x18 14.--18. 1. "TIMER_MOD_REPLAY_TIMER,Replay Timer Limit Modifier. Increases the time-out value for the replay timer in increments of 64 clock cycles at Gen1 or Gen2 speed and in increments of 256 clock cycles at Gen3 speed. A value of '0' represents no modification.." newline hexmask.long.byte 0x18 8.--13. 1. "RSVDP_8,Reserved for future use." newline hexmask.long.byte 0x18 0.--7. 1. "MAX_FUNC_NUM,Maximum function number that can be used in a request. Configuration requests targeted at function numbers above this value are returned with UR (unsupported request). Note: This register field is sticky." line.long 0x1C "SYMBOL_TIMER_FILTER_1_OFF,Symbol Timer Register and Filter Mask 1 Register. The Filter Mask 1 Register modifies the RADM filtering and error handling rules. For more details. see the 'Receive Filtering' section. In each case. '0' applies the associated.." hexmask.long.word 0x1C 16.--31. 1. "MASK_RADM_1,Filter Mask 1. The Filter Mask 1 Register modifies the RADM filtering and error handling rules. For more details see the 'Receive Filtering' section. In each case '0' applies the associated filtering rule and '1' masks the associated.." newline bitfld.long 0x1C 15. "DISABLE_FC_WD_TIMER,Disable FC Watchdog Timer. Note: This register field is sticky." "0,1" newline hexmask.long.byte 0x1C 11.--14. 1. "EIDLE_TIMER,EIDLE_TIMER is an internally reserved field. Do not use. Note: This register field is sticky." newline hexmask.long.word 0x1C 0.--10. 1. "SKP_INT_VAL,SKP Interval Value. The number of symbol times to wait between transmitting SKP ordered sets. Note that the controller actually waits the number of symbol times in this register plus 1 between transmitting SKP ordered sets. Your application.." line.long 0x20 "FILTER_MASK_2_OFF,Filter Mask 2 Register. This register modifies the RADM filtering and error handling rules. For more details. see the 'Receive Filtering' section. In each case. '0' applies the associated filtering rule and '1' masks the associated.." hexmask.long 0x20 0.--31. 1. "MASK_RADM_2,Filter Mask 2. This field modifies the RADM filtering and error handling rules. For more details see the 'Receive Filtering' section. In each case '0' applies the associated filtering rule and '1' masks the associated filtering rule." line.long 0x24 "AMBA_MUL_OB_DECOMP_NP_SUB_REQ_CTRL_OFF,AMBA Multiple Outbound Decomposed NP SubRequests Control Register." hexmask.long 0x24 1.--31. 1. "RSVDP_1,Reserved for future use." newline bitfld.long 0x24 0. "OB_RD_SPLIT_BURST_EN,Enable AMBA Multiple Outbound Decomposed NP SubRequests. This bit when set to '0' disables the possibility of having multiple outstanding non-posted requests that were derived from decomposition of an outbound AMBA request. For more.." "0,1" rgroup.long (0x28+0x700)++0x13 line.long 0x0 "PL_DEBUG0_OFF,Debug Register 0" hexmask.long 0x0 0.--31. 1. "DEB_REG_0,The value on cxpl_debug_info[31:0]." line.long 0x4 "PL_DEBUG1_OFF,Debug Register 1" hexmask.long 0x4 0.--31. 1. "DEB_REG_1,The value on cxpl_debug_info[63:32]." line.long 0x8 "TX_P_FC_CREDIT_STATUS_OFF,Transmit Posted FC Credit Status" hexmask.long.word 0x8 20.--31. 1. "RSVDP_TX_P_FC_CREDIT_STATUS,Reserved for future use." newline hexmask.long.byte 0x8 12.--19. 1. "TX_P_HEADER_FC_CREDIT,Transmit Posted Header FC Credits. The posted Header credits advertised by the receiver at the other end of the link updated with each UpdateFC DLLP. Default value depends on the number of advertised credits for header and data.." newline hexmask.long.word 0x8 0.--11. 1. "TX_P_DATA_FC_CREDIT,Transmit Posted Data FC Credits. The posted Data credits advertised by the receiver at the other end of the link updated with each UpdateFC DLLP. Default value depends on the number of advertised credits for header and data Scaled.." line.long 0xC "TX_NP_FC_CREDIT_STATUS_OFF,Transmit Non-Posted FC Credit Status" hexmask.long.word 0xC 20.--31. 1. "RSVDP_TX_NP_FC_CREDIT_STATUS,Reserved for future use." newline hexmask.long.byte 0xC 12.--19. 1. "TX_NP_HEADER_FC_CREDIT,Transmit Non-Posted Header FC Credits. The non-posted Header credits advertised by the receiver at the other end of the link updated with each UpdateFC DLLP. Default value depends on the number of advertised credits for header and.." newline hexmask.long.word 0xC 0.--11. 1. "TX_NP_DATA_FC_CREDIT,Transmit Non-Posted Data FC Credits. The non-posted Data credits advertised by the receiver at the other end of the link updated with each UpdateFC DLLP. Default value depends on the number of advertised credits for header and data.." line.long 0x10 "TX_CPL_FC_CREDIT_STATUS_OFF,Transmit Completion FC Credit Status" hexmask.long.word 0x10 20.--31. 1. "RSVDP_TX_CPL_FC_CREDIT_STATUS,Reserved for future use." newline hexmask.long.byte 0x10 12.--19. 1. "TX_CPL_HEADER_FC_CREDIT,Transmit Completion Header FC Credits. The Completion Header credits advertised by the receiver at the other end of the link updated with each UpdateFC DLLP. Default value depends on the number of advertised credits for header.." newline hexmask.long.word 0x10 0.--11. 1. "TX_CPL_DATA_FC_CREDIT,Transmit Completion Data FC Credits. The Completion Data credits advertised by the receiver at the other end of the link updated with each UpdateFC DLLP. Default value depends on the number of advertised credits for header and data.." group.long (0x3C+0x700)++0x3 line.long 0x0 "QUEUE_STATUS_OFF,Queue Status" bitfld.long 0x0 31. "TIMER_MOD_FLOW_CONTROL_EN,FC Latency Timer Override Enable. When this bit is set the value from the 'FC Latency Timer Override Value' field in this register will override the FC latency timer value that the controller calculates according to the PCIe.." "0,1" newline rbitfld.long 0x0 29.--30. "RSVDP_29,Reserved for future use." "0,1,2,3" newline hexmask.long.word 0x0 16.--28. 1. "TIMER_MOD_FLOW_CONTROL,FC Latency Timer Override Value. When you set the 'FC Latency Timer Override Enable' in this register the value in this field will override the FC latency timer value that the controller calculates according to the PCIe.." newline rbitfld.long 0x0 13. "RX_SERIALIZATION_Q_NON_EMPTY,Receive Serialization Queue Not Empty. Indicates there is data in the serialization queue." "0,1" newline hexmask.long.word 0x0 4.--12. 1. "RSVDP_4,Reserved for future use." newline bitfld.long 0x0 3. "RX_QUEUE_OVERFLOW,Receive Credit Queue Overflow. Indicates insufficient buffer space available to write to the P/NP/CPL credit queue." "0,1" newline rbitfld.long 0x0 2. "RX_QUEUE_NON_EMPTY,Receive Credit Queue Not Empty. Indicates there is data in one or more of the receive buffers." "0,1" newline rbitfld.long 0x0 1. "TX_RETRY_BUFFER_NE,Transmit Retry Buffer Not Empty. Indicates that there is data in the transmit retry buffer." "0,1" newline rbitfld.long 0x0 0. "RX_TLP_FC_CREDIT_NON_RETURN,Received TLP FC Credits Not Returned. Indicates that the controller has received a TLP but has not yet sent an UpdateFC DLLP indicating that the credits for that TLP have been restored by the receiver at the other end of the.." "0,1" rgroup.long (0x40+0x700)++0x7 line.long 0x0 "VC_TX_ARBI_1_OFF,VC Transmit Arbitration Register 1" hexmask.long.byte 0x0 24.--31. 1. "WRR_WEIGHT_VC_3,WRR Weight for VC3. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R" newline hexmask.long.byte 0x0 16.--23. 1. "WRR_WEIGHT_VC_2,WRR Weight for VC2. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R" newline hexmask.long.byte 0x0 8.--15. 1. "WRR_WEIGHT_VC_1,WRR Weight for VC1. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R" newline hexmask.long.byte 0x0 0.--7. 1. "WRR_WEIGHT_VC_0,WRR Weight for VC0. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R" line.long 0x4 "VC_TX_ARBI_2_OFF,VC Transmit Arbitration Register 2" hexmask.long.byte 0x4 24.--31. 1. "WRR_WEIGHT_VC_7,WRR Weight for VC7. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R" newline hexmask.long.byte 0x4 16.--23. 1. "WRR_WEIGHT_VC_6,WRR Weight for VC6. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R" newline hexmask.long.byte 0x4 8.--15. 1. "WRR_WEIGHT_VC_5,WRR Weight for VC5. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R" newline hexmask.long.byte 0x4 0.--7. 1. "WRR_WEIGHT_VC_4,WRR Weight for VC4. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R" group.long (0x48+0x700)++0xB line.long 0x0 "VC0_P_RX_Q_CTRL_OFF,Segmented-Buffer VC0 Posted Receive Queue Control." bitfld.long 0x0 31. "VC_ORDERING_RX_Q,VC Ordering for Receive Queues. Determines the VC ordering rule for the receive queues used only in the segmented-buffer configuration: - 1: Strict ordering higher numbered VCs have higher priority - 0: Round robin Note: This register.." "Round robin,Strict ordering" newline bitfld.long 0x0 30. "TLP_TYPE_ORDERING_VC0,TLP Type Ordering for VC0. Determines the TLP type ordering rule for VC0 receive queues used only in the segmented-buffer configuration: - 1: PCIe ordering rules (recommended) - 0: Strict ordering: posted completion then.." "Strict ordering: posted,PCIe ordering rules" newline bitfld.long 0x0 28.--29. "RESERVED5,Reserved. Note: This register field is sticky." "0,1,2,3" newline bitfld.long 0x0 26.--27. "VC0_P_DATA_SCALE,VC0 Scale Posted Data Credites. Note: This register field is sticky." "0,1,2,3" newline bitfld.long 0x0 24.--25. "VC0_P_HDR_SCALE,VC0 Scale Posted Header Credites. Note: This register field is sticky." "0,1,2,3" newline bitfld.long 0x0 21.--23. "VC0_P_TLP_Q_MODE,Reserved. Note: This register field is sticky." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 20. "RESERVED4,Reserved. Note: This register field is sticky." "0,1" newline hexmask.long.byte 0x0 12.--19. 1. "VC0_P_HEADER_CREDIT,VC0 Posted Header Credits. The number of initial posted header credits for VC0 used only in the segmented-buffer configuration. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R (sticky) Note: This.." newline hexmask.long.word 0x0 0.--11. 1. "VC0_P_DATA_CREDIT,VC0 Posted Data Credits. The number of initial posted data credits for VC0 used only in the segmented-buffer configuration. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R (sticky) Note: This.." line.long 0x4 "VC0_NP_RX_Q_CTRL_OFF,Segmented-Buffer VC0 Non-Posted Receive Queue Control." hexmask.long.byte 0x4 28.--31. 1. "RESERVED7,Reserved. Note: This register field is sticky." newline bitfld.long 0x4 26.--27. "VC0_NP_DATA_SCALE,VC0 Scale Non-Posted Data Credites. Note: This register field is sticky." "0,1,2,3" newline bitfld.long 0x4 24.--25. "VC0_NP_HDR_SCALE,VC0 Scale Non-Posted Header Credites. Note: This register field is sticky." "0,1,2,3" newline bitfld.long 0x4 21.--23. "VC0_NP_TLP_Q_MODE,Reserved. Note: This register field is sticky." "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 20. "RESERVED6,Reserved. Note: This register field is sticky." "0,1" newline hexmask.long.byte 0x4 12.--19. 1. "VC0_NP_HEADER_CREDIT,VC0 Non-Posted Header Credits. The number of initial non-posted header credits for VC0 used only in the segmented-buffer configuration. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R (sticky).." newline hexmask.long.word 0x4 0.--11. 1. "VC0_NP_DATA_CREDIT,VC0 Non-Posted Data Credits. The number of initial non-posted data credits for VC0 used only in the segmented-buffer configuration. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R (sticky) Note:.." line.long 0x8 "VC0_CPL_RX_Q_CTRL_OFF,Segmented-Buffer VC0 Completion Receive Queue Control." hexmask.long.byte 0x8 28.--31. 1. "RESERVED9,Reserved. Note: This register field is sticky." newline bitfld.long 0x8 26.--27. "VC0_CPL_DATA_SCALE,VC0 Scale CPL Data Credites. Note: This register field is sticky." "0,1,2,3" newline bitfld.long 0x8 24.--25. "VC0_CPL_HDR_SCALE,VC0 Scale CPL Header Credites. Note: This register field is sticky." "0,1,2,3" newline bitfld.long 0x8 21.--23. "VC0_CPL_TLP_Q_MODE,Reserved. Note: This register field is sticky." "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 20. "RESERVED8,Reserved. Note: This register field is sticky." "0,1" newline hexmask.long.byte 0x8 12.--19. 1. "VC0_CPL_HEADER_CREDIT,VC0 Completion Header Credits. The number of initial Completion header credits for VC0 used only in the segmented-buffer configuration. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R (sticky).." newline hexmask.long.word 0x8 0.--11. 1. "VC0_CPL_DATA_CREDIT,VC0 Completion Data Credits. The number of initial Completion data credits for VC0 used only in the segmented-buffer configuration. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R (sticky) Note:.." group.long (0x10C+0x700)++0x3 line.long 0x0 "GEN2_CTRL_OFF,This register is used to control various functions of the controller related to link training. lane reversal. and equalization." rbitfld.long 0x0 31. "RSVDP_31,Reserved for future use." "0,1" newline rbitfld.long 0x0 22.--23. "RSVDP_22,Reserved for future use." "0,1,2,3" newline bitfld.long 0x0 21. "GEN1_EI_INFERENCE,Electrical Idle Inference Mode at Gen1 Rate. Programmable mode to determine inferred electrical idle (EI) in Recovery.Speed or Loopback.Active (as slave) state at Gen1 speed by looking for a '1' value on RxElecIdle instead of looking.." "Use RxElecIdle signal to infer Electrical Idle,Use RxValid signal to infer Electrical Idle" newline bitfld.long 0x0 20. "SEL_DEEMPHASIS,Used to set the de-emphasis level for upstream ports. This bit selects the level of de-emphasis the link operates at. - 0: -6 dB - 1: -3.5 dB This field is reserved (fixed to '0') for M-PCIe. Note: The access attributes of this field are.." "0,1" newline bitfld.long 0x0 19. "CONFIG_TX_COMP_RX,Config Tx Compliance Receive Bit. When set to 1 signals LTSSM to transmit TS ordered sets with the compliance receive bit assert (equal to '1'). This field is reserved (fixed to '0') for M-PCIe. Note: The access attributes of this.." "0,1" newline bitfld.long 0x0 18. "CONFIG_PHY_TX_CHANGE,Config PHY Tx Swing. Controls the PHY transmitter voltage swing level. The controller drives the mac_phy_txswing output from this register bit field. - 0: Full Swing - 1: Low Swing This field is reserved (fixed to '0') for M-PCIe." "Full Swing,Low Swing" newline bitfld.long 0x0 17. "DIRECT_SPEED_CHANGE,Directed Speed Change. Writing '1' to this field instructs the LTSSM to initiate a speed change to Gen2 or Gen3 after the link is initialized at Gen1 speed. When the speed change occurs the controller will clear the contents of this.." "0,1" newline bitfld.long 0x0 16. "AUTO_LANE_FLIP_CTRL_EN,Enable Auto flipping of the lanes. You must set the CX_AUTO_LANE_FLIP_CTRL_EN configuration parameter to include the hardware for this feature in the controller. For more details see the 'Lane Reversal' appendix in the Databook." "0,1" newline bitfld.long 0x0 13.--15. "PRE_DET_LANE,Predetermined Lane for Auto Flip. This field defines which physical lane is connected to logical Lane0 by the flip operation performed in Detect. This field is used to restrict the receiver detect procedure to a particular lane when the.." "LANE0,LANE1,LANE3,LANE7,LANE15,?,?,?" newline hexmask.long.byte 0x0 8.--12. 1. "NUM_OF_LANES,Predetermined Number of Lanes. Defines the number of lanes which are connected and not bad. Used to limit the effective link width to ignore 'broken' or 'unused' lanes that detect a receiver. Indicates the number of lanes to check for exit.." newline hexmask.long.byte 0x0 0.--7. 1. "FAST_TRAINING_SEQ,Sets the Number of Fast Training Sequences (N_FTS) that the controller advertises as its N_FTS during Gen2 or Gen3 link training. This value is used to inform the link partner about the PHY's ability to recover synchronization after a.." rgroup.long (0x110+0x700)++0x3 line.long 0x0 "PHY_STATUS_OFF,PHY Status Register. Memory mapped register from phy_cfg_status GPIO input pins." hexmask.long 0x0 0.--31. 1. "PHY_STATUS,PHY Status. Data received directly from the phy_cfg_status bus. These is a GPIO register reflecting the values on the static phy_cfg_status input signals. The usage is left completely to the user and does not in any way influence controller.." group.long (0x114+0x700)++0x3 line.long 0x0 "PHY_CONTROL_OFF,PHY Control Register. Memory mapped register to cfg_phy_control GPIO output pins." hexmask.long 0x0 0.--31. 1. "PHY_CONTROL,PHY Control. Data sent directly to the cfg_phy_control bus. These is a GPIO register driving the values on the static cfg_phy_control output signals. The usage is left completely to the user and does not in any way influence controller.." group.long (0x11C+0x700)++0x77 line.long 0x0 "TRGT_MAP_CTRL_OFF,Programmable Target Map Control Register." hexmask.long.word 0x0 21.--31. 1. "TARGET_MAP_RESERVED_21_31,Reserved. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R (sticky)" newline hexmask.long.byte 0x0 16.--20. 1. "TARGET_MAP_INDEX,The number of the PF Function on which the Target Values are set. This register does not respect the Byte Enable setting. any write will affect all register bits." newline rbitfld.long 0x0 13.--15. "TARGET_MAP_RESERVED_13_15,Reserved. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R (sticky)" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 6. "TARGET_MAP_ROM,Target Value for the ROM page of the PF Function selected by the index number. This register does not respect the Byte Enable setting. any write will affect all register bits." "0,1" newline hexmask.long.byte 0x0 0.--5. 1. "TARGET_MAP_PF,Target Values for each BAR on the PF Function selected by the index number. This register does not respect the Byte Enable setting. any write will affect all register bits." line.long 0x4 "MSI_CTRL_ADDR_OFF,Integrated MSI Reception Module (iMRM) Address Register." hexmask.long 0x4 0.--31. 1. "MSI_CTRL_ADDR,Integrated MSI Reception Module Address. System specified address for MSI memory write transaction termination. Within the AXI Bridge every received Memory Write request is examined to see if it targets the MSI Address that has been.." line.long 0x8 "MSI_CTRL_UPPER_ADDR_OFF,Integrated MSI Reception Module Upper Address Register." hexmask.long 0x8 0.--31. 1. "MSI_CTRL_UPPER_ADDR,Integrated MSI Reception Module Upper Address. System specified upper address for MSI memory write transaction termination. Allows functions to support a 64-bit MSI address. Note: This register field is sticky." line.long 0xC "MSI_CTRL_INT_0_EN_OFF,Integrated MSI Reception Module Interrupt#i Enable Register." hexmask.long 0xC 0.--31. 1. "MSI_CTRL_INT_0_EN,MSI Interrupt#i Enable. Specifies which interrupts are enabled. When an MSI is received from a disabled interrupt no status bit gets set in MSI controller interrupt status register. Each bit corresponds to a single MSI Interrupt.." line.long 0x10 "MSI_CTRL_INT_0_MASK_OFF,Integrated MSI Reception Module Interrupt#i Mask Register." hexmask.long 0x10 0.--31. 1. "MSI_CTRL_INT_0_MASK,MSI Interrupt#i Mask. Allows enabled interrupts to be masked. When an MSI is received for a masked interrupt the corresponding status bit gets set in the interrupt status register but the msi_ctrl_int output is not set HIGH. Each bit.." line.long 0x14 "MSI_CTRL_INT_0_STATUS_OFF,Integrated MSI Reception Module Interrupt#i Status Register." hexmask.long 0x14 0.--31. 1. "MSI_CTRL_INT_0_STATUS,MSI Interrupt#i Status. When an MSI is detected for EP#i one bit in this register is set. The decoding of the data payload of the MSI Memory Write request determines which bit gets set. A status is bit is cleared by writing a 1 to.." line.long 0x18 "MSI_CTRL_INT_1_EN_OFF,Integrated MSI Reception Module Interrupt#i Enable Register." hexmask.long 0x18 0.--31. 1. "MSI_CTRL_INT_1_EN,MSI Interrupt#i Enable. Specifies which interrupts are enabled. When an MSI is received from a disabled interrupt no status bit gets set in MSI controller interrupt status register. Each bit corresponds to a single MSI Interrupt.." line.long 0x1C "MSI_CTRL_INT_1_MASK_OFF,Integrated MSI Reception Module Interrupt#i Mask Register." hexmask.long 0x1C 0.--31. 1. "MSI_CTRL_INT_1_MASK,MSI Interrupt#i Mask. Allows enabled interrupts to be masked. When an MSI is received for a masked interrupt the corresponding status bit gets set in the interrupt status register but the msi_ctrl_int output is not set HIGH. Each bit.." line.long 0x20 "MSI_CTRL_INT_1_STATUS_OFF,Integrated MSI Reception Module Interrupt#i Status Register." hexmask.long 0x20 0.--31. 1. "MSI_CTRL_INT_1_STATUS,MSI Interrupt#i Status. When an MSI is detected for EP#i one bit in this register is set. The decoding of the data payload of the MSI Memory Write request determines which bit gets set. A status is bit is cleared by writing a 1 to.." line.long 0x24 "MSI_CTRL_INT_2_EN_OFF,Integrated MSI Reception Module Interrupt#i Enable Register." hexmask.long 0x24 0.--31. 1. "MSI_CTRL_INT_2_EN,MSI Interrupt#i Enable. Specifies which interrupts are enabled. When an MSI is received from a disabled interrupt no status bit gets set in MSI controller interrupt status register. Each bit corresponds to a single MSI Interrupt.." line.long 0x28 "MSI_CTRL_INT_2_MASK_OFF,Integrated MSI Reception Module Interrupt#i Mask Register." hexmask.long 0x28 0.--31. 1. "MSI_CTRL_INT_2_MASK,MSI Interrupt#i Mask. Allows enabled interrupts to be masked. When an MSI is received for a masked interrupt the corresponding status bit gets set in the interrupt status register but the msi_ctrl_int output is not set HIGH. Each bit.." line.long 0x2C "MSI_CTRL_INT_2_STATUS_OFF,Integrated MSI Reception Module Interrupt#i Status Register." hexmask.long 0x2C 0.--31. 1. "MSI_CTRL_INT_2_STATUS,MSI Interrupt#i Status. When an MSI is detected for EP#i one bit in this register is set. The decoding of the data payload of the MSI Memory Write request determines which bit gets set. A status is bit is cleared by writing a 1 to.." line.long 0x30 "MSI_CTRL_INT_3_EN_OFF,Integrated MSI Reception Module Interrupt#i Enable Register." hexmask.long 0x30 0.--31. 1. "MSI_CTRL_INT_3_EN,MSI Interrupt#i Enable. Specifies which interrupts are enabled. When an MSI is received from a disabled interrupt no status bit gets set in MSI controller interrupt status register. Each bit corresponds to a single MSI Interrupt.." line.long 0x34 "MSI_CTRL_INT_3_MASK_OFF,Integrated MSI Reception Module Interrupt#i Mask Register." hexmask.long 0x34 0.--31. 1. "MSI_CTRL_INT_3_MASK,MSI Interrupt#i Mask. Allows enabled interrupts to be masked. When an MSI is received for a masked interrupt the corresponding status bit gets set in the interrupt status register but the msi_ctrl_int output is not set HIGH. Each bit.." line.long 0x38 "MSI_CTRL_INT_3_STATUS_OFF,Integrated MSI Reception Module Interrupt#i Status Register." hexmask.long 0x38 0.--31. 1. "MSI_CTRL_INT_3_STATUS,MSI Interrupt#i Status. When an MSI is detected for EP#i one bit in this register is set. The decoding of the data payload of the MSI Memory Write request determines which bit gets set. A status is bit is cleared by writing a 1 to.." line.long 0x3C "MSI_CTRL_INT_4_EN_OFF,Integrated MSI Reception Module Interrupt#i Enable Register." hexmask.long 0x3C 0.--31. 1. "MSI_CTRL_INT_4_EN,MSI Interrupt#i Enable. Specifies which interrupts are enabled. When an MSI is received from a disabled interrupt no status bit gets set in MSI controller interrupt status register. Each bit corresponds to a single MSI Interrupt.." line.long 0x40 "MSI_CTRL_INT_4_MASK_OFF,Integrated MSI Reception Module Interrupt#i Mask Register." hexmask.long 0x40 0.--31. 1. "MSI_CTRL_INT_4_MASK,MSI Interrupt#i Mask. Allows enabled interrupts to be masked. When an MSI is received for a masked interrupt the corresponding status bit gets set in the interrupt status register but the msi_ctrl_int output is not set HIGH. Each bit.." line.long 0x44 "MSI_CTRL_INT_4_STATUS_OFF,Integrated MSI Reception Module Interrupt#i Status Register." hexmask.long 0x44 0.--31. 1. "MSI_CTRL_INT_4_STATUS,MSI Interrupt#i Status. When an MSI is detected for EP#i one bit in this register is set. The decoding of the data payload of the MSI Memory Write request determines which bit gets set. A status is bit is cleared by writing a 1 to.." line.long 0x48 "MSI_CTRL_INT_5_EN_OFF,Integrated MSI Reception Module Interrupt#i Enable Register." hexmask.long 0x48 0.--31. 1. "MSI_CTRL_INT_5_EN,MSI Interrupt#i Enable. Specifies which interrupts are enabled. When an MSI is received from a disabled interrupt no status bit gets set in MSI controller interrupt status register. Each bit corresponds to a single MSI Interrupt.." line.long 0x4C "MSI_CTRL_INT_5_MASK_OFF,Integrated MSI Reception Module Interrupt#i Mask Register." hexmask.long 0x4C 0.--31. 1. "MSI_CTRL_INT_5_MASK,MSI Interrupt#i Mask. Allows enabled interrupts to be masked. When an MSI is received for a masked interrupt the corresponding status bit gets set in the interrupt status register but the msi_ctrl_int output is not set HIGH. Each bit.." line.long 0x50 "MSI_CTRL_INT_5_STATUS_OFF,Integrated MSI Reception Module Interrupt#i Status Register." hexmask.long 0x50 0.--31. 1. "MSI_CTRL_INT_5_STATUS,MSI Interrupt#i Status. When an MSI is detected for EP#i one bit in this register is set. The decoding of the data payload of the MSI Memory Write request determines which bit gets set. A status is bit is cleared by writing a 1 to.." line.long 0x54 "MSI_CTRL_INT_6_EN_OFF,Integrated MSI Reception Module Interrupt#i Enable Register." hexmask.long 0x54 0.--31. 1. "MSI_CTRL_INT_6_EN,MSI Interrupt#i Enable. Specifies which interrupts are enabled. When an MSI is received from a disabled interrupt no status bit gets set in MSI controller interrupt status register. Each bit corresponds to a single MSI Interrupt.." line.long 0x58 "MSI_CTRL_INT_6_MASK_OFF,Integrated MSI Reception Module Interrupt#i Mask Register." hexmask.long 0x58 0.--31. 1. "MSI_CTRL_INT_6_MASK,MSI Interrupt#i Mask. Allows enabled interrupts to be masked. When an MSI is received for a masked interrupt the corresponding status bit gets set in the interrupt status register but the msi_ctrl_int output is not set HIGH. Each bit.." line.long 0x5C "MSI_CTRL_INT_6_STATUS_OFF,Integrated MSI Reception Module Interrupt#i Status Register." hexmask.long 0x5C 0.--31. 1. "MSI_CTRL_INT_6_STATUS,MSI Interrupt#i Status. When an MSI is detected for EP#i one bit in this register is set. The decoding of the data payload of the MSI Memory Write request determines which bit gets set. A status is bit is cleared by writing a 1 to.." line.long 0x60 "MSI_CTRL_INT_7_EN_OFF,Integrated MSI Reception Module Interrupt#i Enable Register." hexmask.long 0x60 0.--31. 1. "MSI_CTRL_INT_7_EN,MSI Interrupt#i Enable. Specifies which interrupts are enabled. When an MSI is received from a disabled interrupt no status bit gets set in MSI controller interrupt status register. Each bit corresponds to a single MSI Interrupt.." line.long 0x64 "MSI_CTRL_INT_7_MASK_OFF,Integrated MSI Reception Module Interrupt#i Mask Register." hexmask.long 0x64 0.--31. 1. "MSI_CTRL_INT_7_MASK,MSI Interrupt#i Mask. Allows enabled interrupts to be masked. When an MSI is received for a masked interrupt the corresponding status bit gets set in the interrupt status register but the msi_ctrl_int output is not set HIGH. Each bit.." line.long 0x68 "MSI_CTRL_INT_7_STATUS_OFF,Integrated MSI Reception Module Interrupt#i Status Register." hexmask.long 0x68 0.--31. 1. "MSI_CTRL_INT_7_STATUS,MSI Interrupt#i Status. When an MSI is detected for EP#i one bit in this register is set. The decoding of the data payload of the MSI Memory Write request determines which bit gets set. A status is bit is cleared by writing a 1 to.." line.long 0x6C "MSI_GPIO_IO_OFF,Integrated MSI Reception Module General Purpose IO Register." hexmask.long 0x6C 0.--31. 1. "MSI_GPIO_REG,MSI GPIO Register. The contents of this register drives the top-level GPIO msi_ctrl_io[31:0] Note: This register field is sticky." line.long 0x70 "CLOCK_GATING_CTRL_OFF,This register enables you to disable dynamic clock gating. By default dynamic clock gating is on. allowing the controller to autonomously enable and disable its clocks. The clock gating is performed in the clock and reset module." hexmask.long 0x70 2.--31. 1. "RSVDP_2,Reserved for future use." newline bitfld.long 0x70 1. "AXI_CLK_GATING_EN,AXI Clock Gating Enable. This register enables the AXI Bridge to autonomously enable and disable the AXI Master clock the AXI Slave clock and the AXI DBI slave clock. The DWC_pcie_clk_rst.v module provides the gated clock.." "Disable,Enable" newline bitfld.long 0x70 0. "RADM_CLK_GATING_EN,RADM Clock Gating Enable. This register if set enables the RADM to autonomously enable and disable its clock. The DWC_pcie_clk_rst.v module provides the gated clock radm_clk_g to the RADM and is enabled when the controllers clock.." "Disable,Enable" line.long 0x74 "GEN3_RELATED_OFF,Gen3 Control Register. There is no Gen3-specific N_FTS field. The N_FTS field in the 'Link Width and Speed Change Control Register' is used for both Gen2 and Gen3 speed modes. There is no Gen3-specific 'Directed Speed Change' field. The.." hexmask.long.byte 0x74 26.--31. 1. "RSVDP_26,Reserved for future use." newline bitfld.long 0x74 23. "GEN3_EQ_INVREQ_EVAL_DIFF_DISABLE,Eq InvalidRequest and RxEqEval Different Time Assertion Disable. Disable the assertion of Eq InvalidRequest and RxEqEval at different time. Note: When CX_GEN4_SPEED/CX_GEN5_SPEED this register is shared for Gen3 and.." "0,1" newline rbitfld.long 0x74 19.--20. "RSVDP_19,Reserved for future use." "0,1,2,3" newline bitfld.long 0x74 18. "GEN3_DC_BALANCE_DISABLE,DC Balance Disable. Disable DC Balance feature. Note: When CX_GEN4_SPEED/CX_GEN5_SPEED this register is shared for Gen3 and Gen4/Gen5 data rate. Note: This register field is sticky." "0,1" newline bitfld.long 0x74 17. "GEN3_DLLP_XMT_DELAY_DISABLE,DLLP Transmission Delay Disable. Disable delay transmission of DLLPs before equalization. Note: When CX_GEN4_SPEED/CX_GEN5_SPEED this register is shared for Gen3 and Gen4/Gen5 data rate. Note: This register field is sticky." "0,1" newline bitfld.long 0x74 16. "GEN3_EQUALIZATION_DISABLE,Equalization Disable. Disable equalization feature. This bit cannot be changed once the LTSSM starts link training. Note: When CX_GEN4_SPEED/CX_GEN5_SPEED this register is shared for Gen3 and Gen4/Gen5 data rate. Note: This.." "0,1" newline rbitfld.long 0x74 14.--15. "RSVDP_14,Reserved for future use." "0,1,2,3" newline bitfld.long 0x74 13. "RXEQ_RGRDLESS_RXTS,When set to '1' the controller as Gen3 EQ master asserts RxEqEval to instruct the PHY to do Rx adaptation and evaluation after a 500ns timeout from a new preset request. - 0: mac_phy_rxeqeval asserts after 1us and 2 TS1 received from.." "mac_phy_rxeqeval asserts after 1us and 2 TS1..,mac_phy_rxeqeval asserts after 500ns regardless.." newline bitfld.long 0x74 12. "RXEQ_PH01_EN,Rx Equalization Phase 0/Phase 1 Hold Enable. When this bit is set the upstream port holds phase 0 (the downstream port holds phase 1) for 10ms. Holding phase 0 or phase 1 can be used to allow sufficient time for Rx Equalization to be.." "Tx equalization only in phase 2/3,No Tx equalization" newline bitfld.long 0x74 11. "EQ_REDO,Equalization Redo Disable. Disable autonomous mechanism for requesting to redo the equalization process. The received presets or coefficients mismatch in Recovery.RcvrLock after Recovery EQ phases causes the EQ redo requests. If the EQ redo is.." "0,1" newline bitfld.long 0x74 10. "EQ_EIEOS_CNT,Equalization EIEOS Count Reset Disable. Disable requesting reset of EIEOS count during equalization. Note: When CX_GEN4_SPEED/CX_GEN5_SPEED this register is shared for Gen3 and Gen4/Gen5 data rate. Note: This register field is sticky." "0,1" newline bitfld.long 0x74 9. "EQ_PHASE_2_3,Equalization Phase 2 and Phase 3 Disable. This applies to downstream ports only. Note: When CX_GEN4_SPEED/CX_GEN5_SPEED this register is shadow register for Gen3 and Gen4/Gen5 data rate. If RATE_SHADOW_SEL==00b this register is for Gen3.." "0,1" newline bitfld.long 0x74 8. "DISABLE_SCRAMBLER_GEN_3,Disable Scrambler for Gen3 and Gen4 Data Rate. The Gen3 and Gen4 scrambler/descrambler within the controller needs to be disabled when the scrambling function is implemented outside of the controller (for example within the PHY)." "0,1" newline hexmask.long.byte 0x74 1.--7. 1. "RSVDP_1,Reserved for future use." newline bitfld.long 0x74 0. "GEN3_ZRXDC_NONCOMPL,Gen3 Receiver Impedance ZRX-DC Not Compliant. Receivers that operate at 8.0 GT/s with an impedance other than the range defined by the ZRX-DC parameter for 2.5 GT/s (40-60 Ohms) must meet additional behavior requirements in the.." "The receiver complies with the ZRX-DC parameter..,The receiver does not comply with the ZRX-DC.." group.long (0x1A8+0x700)++0x7 line.long 0x0 "GEN3_EQ_CONTROL_OFF,Gen3 EQ Control Register. This register controls equalization for Phase2 in an upstream port (USP). or Phase3 in a downstream port (DSP). M-PCIe doesn't have Conventional PCIe Gen3 feature. The registers of this section do not exist." hexmask.long.byte 0x0 27.--31. 1. "RSVDP_27,Reserved for future use." newline bitfld.long 0x0 26. "GEN3_REQ_SEND_CONSEC_EIEOS_FOR_PSET_MAP,Request controller to send back-to-back EIEOS in Recovery.RcvrLock state until presets to coefficients mapping is complete. - 0: Do not request - 1: request Note: Gen3 and Gen4 share the same register bit and have.." "Do not request,request" newline bitfld.long 0x0 25. "GEN3_EQ_PSET_REQ_AS_COEF,GEN3_EQ_PSET_REQ_AS_COEF is an internally reserved field. Do not use. Note: This register field is sticky." "0,1" newline bitfld.long 0x0 24. "GEN3_EQ_FOM_INC_INITIAL_EVAL,Include Initial FOM. Include or not the FOM feedback from the initial preset evaluation performed in the EQ Master when finding the highest FOM among all preset evaluations. - 0: Do not include - 1: Include Note: When.." "Do not include,Include" newline hexmask.long.word 0x0 8.--23. 1. "GEN3_EQ_PSET_REQ_VEC,Preset Request Vector. Requesting of Presets during the initial part of the EQ Master Phase. Encoding scheme is as follows: Bit [15:0] =0x0: No preset is requested and evaluated in EQ Master Phase. Bit [i] =1: 'Preset=i' is requested.." newline rbitfld.long 0x0 7. "RSVDP_7,Reserved for future use." "0,1" newline bitfld.long 0x0 6. "GEN3_LOWER_RATE_EQ_REDO_ENABLE,Support EQ redo and lower rate change: - 0: not support - 1: support Note: Gen3 and Gen4 share the same register bit and have the same feature. Note: This register field is sticky." "not support,support" newline bitfld.long 0x0 5. "GEN3_EQ_EVAL_2MS_DISABLE,Phase2_3 2 ms Timeout Disable. Determine behavior in Phase2 for USP (Phase3 if DSP) when the PHY does not respond within 2ms to the assertion of RxEqEval: - 0: abort the current evaluation stop any attempt to modify the remote.." "abort the current evaluation,ignore the 2ms timeout and continue as normal" newline bitfld.long 0x0 4. "GEN3_EQ_PHASE23_EXIT_MODE,Behavior After 24 ms Timeout (when optimal settings are not found). For a USP: Determine next LTSSM state from Phase2 after 24ms Timeout - 0: Recovery.Speed - 1: Recovery.Equalization.Phase3 When optimal settings are not found.." "Equalization Phase 3 Successful status bit is..,Recovery" newline hexmask.long.byte 0x0 0.--3. 1. "GEN3_EQ_FB_MODE,Feedback Mode. - 0000b: Direction Change - 0001b: Figure Of Merit - 0010b: Reserved - .....: Reserved - 1111b: Reserved Note: When CX_GEN4_SPEED/CX_GEN5_SPEED this register is a shadow register for Gen3 and Gen4/Gen5 data rate. If.." line.long 0x4 "GEN3_EQ_FB_MODE_DIR_CHANGE_OFF,Gen3 EQ Direction Change Feedback Mode Control Register. Equalization controls to be used in Phase2 (USP) or Phase 3 (DSP). when you set the Feedback Mode in 'Gen3 EQ Control Register' to 'Direction Change.' These fields.." hexmask.long.word 0x4 18.--31. 1. "RSVDP_18,Reserved for future use." newline hexmask.long.byte 0x4 14.--17. 1. "GEN3_EQ_FMDC_MAX_POST_CUSROR_DELTA,Convergence Window Aperture for C+1. Post-cursor coefficients maximum delta within the convergence window depth. Allowed range: 0 1 2 ..15. Note: When CX_GEN4_SPEED/CX_GEN5_SPEED this register is shadow register for.." newline hexmask.long.byte 0x4 10.--13. 1. "GEN3_EQ_FMDC_MAX_PRE_CUSROR_DELTA,Convergence Window Aperture for C-1. Pre-cursor coefficients maximum delta within the convergence window depth. Allowed range: 0 1 2 ..15. Note: When CX_GEN4_SPEED/CX_GEN5_SPEED this register is shadow register for Gen3.." newline hexmask.long.byte 0x4 5.--9. 1. "GEN3_EQ_FMDC_N_EVALS,Convergence Window Depth. Number of consecutive evaluations considered in Phase 2/3 when determining if optimal coefficients have been found. Allowed range: 0 1 2 ..16 up to a maximum of CX_GEN3_EQ_COEFQ_DEPTH. When set to 0 EQ.." newline hexmask.long.byte 0x4 0.--4. 1. "GEN3_EQ_FMDC_T_MIN_PHASE23,Minimum Time (in ms) To Remain in EQ Master Phase. The LTSSM stays in EQ Master phase for at least this amount of time before starting to check for convergence of the coefficients. Allowed values 0 1 ... 24. Note: When.." group.long (0x1B4+0x700)++0x27 line.long 0x0 "ORDER_RULE_CTRL_OFF,Order Rule Control Register." hexmask.long.word 0x0 16.--31. 1. "RSVDP_16,Reserved for future use." newline hexmask.long.byte 0x0 8.--15. 1. "CPL_PASS_P,Completion Passing Posted Ordering Rule Control. Determines if CPL can pass halted P queue. - 0: CPL can not pass P (recommended) - 1: CPL can pass P" newline hexmask.long.byte 0x0 0.--7. 1. "NP_PASS_P,Non-Posted Passing Posted Ordering Rule Control. Determines if NP can pass halted P queue. - 0 : NP can not pass P (recommended). - 1 : NP can pass P" line.long 0x4 "PIPE_LOOPBACK_CONTROL_OFF,PIPE Loopback Control Register." bitfld.long 0x4 31. "PIPE_LOOPBACK,PIPE Loopback Enable. Indicates RMMI Loopback if M-PCIe. Note: This register field is sticky." "0,1" newline hexmask.long.byte 0x4 27.--30. 1. "RSVDP_27,Reserved for future use." newline bitfld.long 0x4 24.--26. "RXSTATUS_VALUE,RXSTATUS_VALUE is an internally reserved field. Do not use." "0,1,2,3,4,5,6,7" newline rbitfld.long 0x4 22.--23. "RSVDP_22,Reserved for future use." "0,1,2,3" newline hexmask.long.byte 0x4 16.--21. 1. "RXSTATUS_LANE,RXSTATUS_LANE is an internally reserved field. Do not use. Note: This register field is sticky." newline hexmask.long.word 0x4 0.--15. 1. "LPBK_RXVALID,LPBK_RXVALID is an internally reserved field. Do not use. Note: This register field is sticky." line.long 0x8 "MISC_CONTROL_1_OFF,DBI Read-Only Write Enable Register." hexmask.long.word 0x8 22.--31. 1. "RSVDP_22,Reserved for future use." newline bitfld.long 0x8 21. "P2P_ERR_RPT_CTRL,Determines whether to track completion of transmitted Non-Posted TLPs in P2P mode. - 0: Do not track completion - 1: Track completion Note: This register field is sticky." "Do not track completion,Track completion" newline bitfld.long 0x8 20. "P2P_TRACK_CPL_TO_REG,Determines whether to enable Peer to Peer (P2P) error reporting. - 0: Disable P2P error reporting - 1: Enable P2P error reporting Note: This register field is sticky." "Disable P2P error reporting,Enable P2P error reporting" newline bitfld.long 0x8 18.--19. "TARGET_ABOVE_CONFIG_LIMIT_REG,Configuration requests with an address greater than CONFIG_LIMIT_REG are directed to either ELBI or TRGT1 interface based on the setting of this field. This field can have the following values: - 1: ELBI - 2: TRGT1 Note:.." "?,ELBI,TRGT1,?" newline hexmask.long.word 0x8 8.--17. 1. "CONFIG_LIMIT_REG,Configuration requests are directed either to CDM or ELBI/RTRGT1 based on the value of this field. - Configuration requests with an address less CONFIG_LIMIT_REG are directed to the CDM - Configuration requests with an address greater.." newline bitfld.long 0x8 7. "CFG_TLP_BYPASS_EN_REG,Setting of this field defines which field TARGET_ABOVE_CONFIG_LIMIT_REG or CONFIG_LIMIT_REG decides the destination of Configuration requests. This field can have the following values: - 0: Configuration TLPs are routed according to.." "Configuration TLPs are routed according to the..,Configuration TLPs are routed according to the.." newline bitfld.long 0x8 6. "CPLQ_MNG_EN,This field enables the Completion Queue Management feature. Note: This register field is sticky." "0,1" newline bitfld.long 0x8 5. "ARI_DEVICE_NUMBER,When ARI is enabled this field enables use of the device ID. Note: This register field is sticky." "0,1" newline bitfld.long 0x8 4. "DISABLE_AUTO_LTR_CLR_MSG,Disable the autonomous generation of LTR clear message in upstream port. This field can have the following values: - 0: Allow the autonomous generation of LTR clear message. - 1: Disable the autonomous generation of LTR clear.." "Allow the autonomous generation of LTR clear..,Disable the autonomous generation of LTR clear.." newline bitfld.long 0x8 3. "SIMPLIFIED_REPLAY_TIMER,Enables Simplified Replay Timer (Gen4). For more details see 'Transmit Replay' in 'Transmit TLP Processing' section in the 'Controller Operations' chapter of the Databook. Simplified Replay Timer can have the following Values: -.." "0,1" newline bitfld.long 0x8 2. "UR_CA_MASK_4_TRGT1,When this field is set to '1' the controller suppresses error logging error message generation and CPL generation for non-posted requests TLPs (with UR filtering status) forwarded to your application (that is when DEFAULT_TARGET.." "0,1" newline bitfld.long 0x8 1. "DEFAULT_TARGET,Default target for an IO or MEM request with UR/CA/CRS received. Based on the value of this field the controller either drops or forwards these requests to your application. - 0: The controller drops all incoming I/O or MEM requests (after.." "The controller drops all incoming I/O or MEM..,The controller forwards all incoming I/O or MEM.." newline bitfld.long 0x8 0. "DBI_RO_WR_EN,Write to RO Registers Using DBI. Your application can write to some RO and HwInit register fields through the DBI when you set this field to '1'. For more details see 'Writing to Read-Only Registers' in 'Register Module LBC and DBI'.." "0,1" line.long 0xC "MULTI_LANE_CONTROL_OFF,UpConfigure Multi-lane Control Register. Used when upsizing or downsizing the link width through Configuration state without bringing the link down. For more details. see the 'Link Establishment' section in the 'Controller.." hexmask.long.tbyte 0xC 8.--31. 1. "RSVDP_8,Reserved for future use." newline bitfld.long 0xC 7. "UPCONFIGURE_SUPPORT,Upconfigure Support. The controller sends this value as the Link Upconfigure Capability in TS2 Ordered Sets in Configuration.Complete state. This field is reserved (fixed to '0') for M-PCIe. Note: This register field is sticky." "0,1" newline bitfld.long 0xC 6. "DIRECT_LINK_WIDTH_CHANGE,Directed Link Width Change. The controller always moves to Configuration state through Recovery state when this bit is set to '1'. - If the upconfigure_capable variable is '1' and the PCIE_CAP_HW_AUTO_WIDTH_DISABLE bit in.." "0,1" newline hexmask.long.byte 0xC 0.--5. 1. "TARGET_LINK_WIDTH,Target Link Width. Values correspond to: - 6'b000000: Controller does not start upconfigure or autonomous width downsizing in the Configuration state. - 6'b000001: x1 - 6'b000010: x2 - 6'b000100: x4 - 6'b001000: x8 - 6'b010000: x16 -.." line.long 0x10 "PHY_INTEROP_CTRL_OFF,PHY Interoperability Control Register." hexmask.long.tbyte 0x10 12.--31. 1. "RSVDP_12,Reserved for future use." newline bitfld.long 0x10 10. "L1_CLK_SEL,L1 Clock control bit. This field is reserved for internal use. You should not write to this field and change the default unless specifically instructed by Synopsys support. - 1: Controller does not request aux_clk switch and core_clk gating in.." "Controller requests aux_clk switch and core_clk..,Controller does not request aux_clk switch and.." newline rbitfld.long 0x10 9. "L1_NOWAIT_P1,L1 entry control bit. This field is reserved for internal use. You should not write to this field and change the default unless specifically instructed by Synopsys support. - 1: Controller does not wait for PHY to acknowledge transition to.." "Controller waits for the PHY to acknowledge..,Controller does not wait for PHY to acknowledge.." newline bitfld.long 0x10 8. "L1SUB_EXIT_MODE,L1 Exit Control Using phy_mac_pclkack_n. This field is reserved for internal use. You should not write to this field and change the default unless specifically instructed by Synopsys support. - 1: Controller exits L1 without waiting for.." "Controller waits for the PHY to assert..,Controller exits L1 without waiting for the PHY.." newline rbitfld.long 0x10 7. "RSVDP_7,Reserved for future use." "0,1" newline hexmask.long.byte 0x10 0.--6. 1. "RXSTANDBY_CONTROL,Rxstandby Control. Bits 0..5 determine if the controller asserts the RxStandby signal (mac_phy_rxstandby) in the indicated condition. Bit 6 enables the controller to perform the RxStandby/RxStandbyStatus handshake. This field is.." line.long 0x14 "TRGT_CPL_LUT_DELETE_ENTRY_OFF,TRGT_CPL_LUT Delete Entry Control register. Using this register you can delete one entry in the target completion LUT. You should only use this register when you know that your application will never send the completion.." bitfld.long 0x14 31. "DELETE_EN,This is a one-shot bit. A '1' write to this bit triggers the deletion of the target completion LUT entry that is specified in the LOOK_UP_ID field. This is a self-clearing register field. Reading from this register field always returns a '0'." "0,1" newline hexmask.long 0x14 0.--30. 1. "LOOK_UP_ID,This number selects one entry to delete of the TRGT_CPL_LUT." line.long 0x18 "LINK_FLUSH_CONTROL_OFF,Link Reset Request Flush Control Register." hexmask.long.byte 0x18 24.--31. 1. "RSVD_I_8,This is an internally reserved field. Do not use. Note: This register field is sticky." newline hexmask.long.tbyte 0x18 1.--23. 1. "RSVDP_1,Reserved for future use." newline bitfld.long 0x18 0. "AUTO_FLUSH_EN,Enables automatic flushing of pending requests before sending the reset request to the application logic to reset the PCIe controller and the AXI Bridge. The flushing process is initiated if any of the following events occur: - Hot reset.." "0,1" line.long 0x1C "AMBA_ERROR_RESPONSE_DEFAULT_OFF,AXI Bridge Slave Error Response Register." hexmask.long.word 0x1C 16.--31. 1. "RSVDP_16,Reserved for future use." newline hexmask.long.byte 0x1C 10.--15. 1. "AMBA_ERROR_RESPONSE_MAP,AXI Slave Response Error Map. Allows you to selectively map the errors received from the PCIe completion (for non-posted requests) to the AXI slave responses slv_rresp or slv_bresp. The recommended setting is SLVERR. CRS is.." newline hexmask.long.byte 0x1C 5.--9. 1. "RSVDP_5,Reserved for future use." newline bitfld.long 0x1C 3.--4. "AMBA_ERROR_RESPONSE_CRS,CRS Slave Error Response Mapping. Determines the AXI slave response for CRS completions. For more details see 'Error Handling' in the AXI chapter of the Databook. AHB: - always returns OKAY AXI: - 00: OKAY - 01: OKAY with all.." "OKAY,OKAY with all FFFF_FFFF data for all CRS..,?,?" newline bitfld.long 0x1C 2. "AMBA_ERROR_RESPONSE_VENDORID,Vendor ID Non-existent Slave Error Response Mapping. Determines the AXI slave response for errors on reads to non-existent Vendor ID register. For more details see 'Error Handling' in the AXI chapter of the Databook. AHB: -.." "OKAY,SLVERR/DECERR" newline rbitfld.long 0x1C 1. "RSVDP_1,Reserved for future use." "0,1" newline bitfld.long 0x1C 0. "AMBA_ERROR_RESPONSE_GLOBAL,Global Slave Error Response Mapping. Determines the AXI slave response for all error scenarios on non-posted requests. For more details see 'Error Handling' in the AXI chapter of the Databook. AHB: - 0: OKAY (with FFFF data for.." "OKAY,SLVERR/DECERR" line.long 0x20 "AMBA_LINK_TIMEOUT_OFF,Link Down AXI Bridge Slave Timeout Register. If your application AXI master issues outbound requests to the AXI bridge slave interface before the PCIe link is operational. the controller starts a 'flush' timer. The timeout value of.." hexmask.long.tbyte 0x20 9.--31. 1. "RSVDP_9,Reserved for future use." newline bitfld.long 0x20 8. "LINK_TIMEOUT_ENABLE_DEFAULT,Disable Flush. You can disable the flush feature by setting this field to '1'. Note: This register field is sticky." "0,1" newline hexmask.long.byte 0x20 0.--7. 1. "LINK_TIMEOUT_PERIOD_DEFAULT,Timeout Value (ms). The timer will timeout and then flush the bridge TX request queues after this amount of time. The timer counts when there are pending outbound AXI slave interface requests and the PCIe TX link is not.." line.long 0x24 "AMBA_ORDERING_CTRL_OFF,AMBA Ordering Control." hexmask.long.tbyte 0x24 8.--31. 1. "RSVDP_8,Reserved for future use." newline bitfld.long 0x24 7. "AX_MSTR_ZEROLREAD_FW,AXI Master Zero Length Read Forward to the application. The DW PCIe controller AXI bridge is able to terminate in order with the Posted transactions the zero length read implementing the PCIe express flush semantics of the Posted.." "The zero length Read is terminated at the DW..,The zero length Read is forward to the application" newline rbitfld.long 0x24 5.--6. "RSVDP_5,Reserved for future use." "0,1,2,3" newline bitfld.long 0x24 3.--4. "AX_MSTR_ORDR_P_EVENT_SEL,AXI Master Posted Ordering Event Selector. This field selects how the master interface determines when a P write is completed when enforcing the PCIe ordering rule 'NP must not pass P' at the AXI Master Interface. The AXI.." "B'last event: wait for the all of the write..,AW'last event: wait until the complete Posted..,This setting will not affect:,?" newline rbitfld.long 0x24 2. "RSVDP_2,Reserved for future use." "0,1" newline bitfld.long 0x24 1. "AX_SNP_EN,AXI Serialize Non-Posted Requests Enable. This field enables the AXI Bridge to serialize same ID Non-Posted Read/Write Requests on the wire. Serialization implies one outstanding same ID NP Read or Write on the wire and used to avoid AXI RAR.." "0,1" newline rbitfld.long 0x24 0. "RSVDP_0,Reserved for future use." "0,1" group.long (0x1E0+0x700)++0xB line.long 0x0 "COHERENCY_CONTROL_1_OFF,ACE Cache Coherency Control Register 1" hexmask.long 0x0 2.--31. 1. "CFG_MEMTYPE_BOUNDARY_LOW_ADDR,Boundary Lower Address For Memory Type. Bits [31:0] of dword-aligned address of the boundary for Memory type. The two lower address LSBs are '00'. Addresses up to but not including this value are in the lower address space.." newline rbitfld.long 0x0 1. "RSVDP_1,Reserved for future use." "0,1" newline bitfld.long 0x0 0. "CFG_MEMTYPE_VALUE,Sets the memory type for the lower and upper parts of the address space: - 0: lower = Peripheral; upper = Memory - 1: lower = Memory type; upper = Peripheral Note: This register field is sticky." "lower = Peripheral; upper = Memory,lower = Memory type; upper = Peripheral" line.long 0x4 "COHERENCY_CONTROL_2_OFF,ACE Cache Coherency Control Register 2" hexmask.long 0x4 0.--31. 1. "CFG_MEMTYPE_BOUNDARY_HIGH_ADDR,Boundary Upper Address For Memory Type. Bits [63:32] of the 64-bit dword-aligned address of the boundary for Memory type. Note: This register field is sticky." line.long 0x8 "COHERENCY_CONTROL_3_OFF,ACE Cache Coherency Control Register 3" hexmask.long.byte 0x8 27.--30. 1. "CFG_MSTR_AWCACHE_VALUE,Master Write CACHE Signal Value. Value of the individual bits in mstr_awcache when CFG_MSTR_AWCACHE_MODE is '1'. Note: not applicable to message requests; for message requests the value of mstr_awcache is always '0000' Note: This.." newline hexmask.long.byte 0x8 19.--22. 1. "CFG_MSTR_ARCACHE_VALUE,Master Read CACHE Signal Value. Value of the individual bits in mstr_arcache when CFG_MSTR_ARCACHE_MODE is '1'. Note: This register field is sticky." newline hexmask.long.byte 0x8 11.--14. 1. "CFG_MSTR_AWCACHE_MODE,Master Write CACHE Signal Behavior. Defines how the individual bits in mstr_awcache are controlled: - 0: set automatically by the AXI master - 1: set by the value of the corresponding bit of the CFG_MSTR_AWCACHE_VALUE field Note:.." newline hexmask.long.byte 0x8 3.--6. 1. "CFG_MSTR_ARCACHE_MODE,Master Read CACHE Signal Behavior. Defines how the individual bits in mstr_arcache are controlled: - 0: set automatically by the AXI master - 1: set by the value of the corresponding bit of the CFG_MSTR_ARCACHE_VALUE field Note:.." group.long (0x1F0+0x700)++0x7 line.long 0x0 "AXI_MSTR_MSG_ADDR_LOW_OFF,Lower 20 bits of the programmable AXI address where Messages coming from wire are mapped to. Bits [11:0] of the register are tied to zero for the address to be 4k-aligned. In previous releases. the third and fourth DWORDs of a.." hexmask.long.tbyte 0x0 12.--31. 1. "CFG_AXIMSTR_MSG_ADDR_LOW,Lower 20 bits of the programmable AXI address for Messages. Note: This register field is sticky." newline hexmask.long.word 0x0 0.--11. 1. "CFG_AXIMSTR_MSG_ADDR_LOW_RESERVED,Reserved for future use. Note: This register field is sticky." line.long 0x4 "AXI_MSTR_MSG_ADDR_HIGH_OFF,Upper 32 bits of the programmable AXI address where Messages coming from wire are mapped to." hexmask.long 0x4 0.--31. 1. "CFG_AXIMSTR_MSG_ADDR_HIGH,Upper 32 bits of the programmable AXI address for Messages. Note: This register field is sticky." rgroup.long (0x1F8+0x700)++0x7 line.long 0x0 "PCIE_VERSION_NUMBER_OFF,PCIe Controller IIP Release Version Number. The version number is given in hex format. You should convert each pair of hex characters to ASCII to interpret. Using 4.70a (GA) as an example: - VERSION_NUMBER = 0x3437302a which.." hexmask.long 0x0 0.--31. 1. "VERSION_NUMBER,Version Number." line.long 0x4 "PCIE_VERSION_TYPE_OFF,PCIe Controller IIP Release Version Type. The type is given in hex format. You should convert each pair of hex characters to ASCII to interpret. Using 4.70a (GA) as an example: - VERSION_NUMBER = 0x3437302a which translates to 470*.." hexmask.long 0x4 0.--31. 1. "VERSION_TYPE,Version Type." group.long (0x430+0x700)++0x3 line.long 0x0 "PL_LTR_LATENCY_OFF,LTR Latency Register. The function of this register field (and all other fields in this register) differs between an upstream port and a downstream port. For an upstream port. the register fields capture the corresponding fields in the.." bitfld.long 0x0 31. "NO_SNOOP_LATENCY_REQUIRE,No Snoop Latency Requirement. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" "0,1" newline rbitfld.long 0x0 29.--30. "RSVDP_29,Reserved for future use." "0,1,2,3" newline bitfld.long 0x0 26.--28. "NO_SNOOP_LATENCY_SCALE,No Snoop Latency Scale. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" "0,1,2,3,4,5,6,7" newline hexmask.long.word 0x0 16.--25. 1. "NO_SNOOP_LATENCY_VALUE,No Snoop Latency Value. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" newline bitfld.long 0x0 15. "SNOOP_LATENCY_REQUIRE,Snoop Latency Requirement. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" "0,1" newline rbitfld.long 0x0 13.--14. "RSVDP_13,Reserved for future use." "0,1,2,3" newline bitfld.long 0x0 10.--12. "SNOOP_LATENCY_SCALE,Snoop Latency Scale. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" "0,1,2,3,4,5,6,7" newline hexmask.long.word 0x0 0.--9. 1. "SNOOP_LATENCY_VALUE,Snoop Latency Value. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" group.long (0x440+0x700)++0xB line.long 0x0 "AUX_CLK_FREQ_OFF,Auxiliary Clock Frequency Control Register." hexmask.long.tbyte 0x0 10.--31. 1. "RSVDP_10,Reserved for future use." newline hexmask.long.word 0x0 0.--9. 1. "AUX_CLK_FREQ,The aux_clk frequency in MHz. This value is used to provide a 1 us reference for counting time during low-power states with aux_clk when the PHY has removed the pipe_clk. Frequencies lower than 1 MHz are possible but with a loss of accuracy.." line.long 0x4 "L1_SUBSTATES_OFF,L1 Substates Timing Register." hexmask.long.tbyte 0x4 9.--31. 1. "RSVDP_9,Reserved for future use." newline bitfld.long 0x4 8. "L1SUB_LOW_POWER_CLOCK_SWITCH_MODE,If this bit is set to 1'b1 the reference clock will be running regardless of the CLKREQ# setting. If this bit is set to 1'b0 the reference clock may be gated off when CLKREQ# is de-asserted. If the bit is set to 1'b1 the.." "0,1" newline bitfld.long 0x4 6.--7. "L1SUB_T_PCLKACK,Max delay (in 1us units) between a MAC request to remove the clock on mac_phy_pclkreq_n and a PHY response on phy_mac_pclkack_n. If the PHY does not respond within this time the request is aborted.The actual timeout value will be.." "0,1,2,3" newline hexmask.long.byte 0x4 2.--5. 1. "L1SUB_T_L1_2,Duration (in 1us units) of L1.2. The actual timeout value will be L1SUB_T_L1_2 + 1. Range is 0.15. Note: This register field is sticky." newline bitfld.long 0x4 0.--1. "L1SUB_T_POWER_OFF,Duration (in 1us units) of L1.2.Entry. The actual timeout value will be L1SUB_T_POWER_OFF + 1. Range is 0.3. Note: This register field is sticky." "0,1,2,3" line.long 0x8 "POWERDOWN_CTRL_STATUS_OFF,Powerdown Control and Status Register." hexmask.long.tbyte 0x8 12.--31. 1. "RSVDP_12,Reserved for future use." newline hexmask.long.byte 0x8 8.--11. 1. "POWERDOWN_PHY_POWERDOWN,This field represents the Powerdown value that has been acknowledged by the PHY. It is updated with the value of Powerdown driven by the controller when the PHY has returned the Phystatus acknowledgment for the Powerdown.." newline hexmask.long.byte 0x8 4.--7. 1. "POWERDOWN_MAC_POWERDOWN,This field represents the Powerdown value driven by the controller to the PHY." newline rbitfld.long 0x8 1.--3. "RSVDP_1,Reserved for future use." "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 0. "POWERDOWN_FORCE,This field is a one shot field. Writing a value of 1 to this field causes the controller to complete the P2 Powerdown handshake regardless of whether the PHY has returned Phystatus. This field could be used for debug purposes in event.." "0,1" group.long (0x470+0x700)++0x7 line.long 0x0 "PHY_VIEWPORT_CTLSTS_OFF,PHY Register Viewport Control and Status Register." rbitfld.long 0x0 31. "PHY_VIEWPORT_PENDING,PHY viewport pending. Indicates the access is pending. - 1 : Pending - 0 : Idle This bit is set to 1 when the read/write access has been initiated. This bit is cleared when the access is completed. If phy_reg_clk_g is never activated.." "Idle,Pending" newline rbitfld.long 0x0 30. "PHY_VIEWPORT_STATUS,PHY viewport status. Indicates the status of the latest access. - 1 : Timeout - 0 : No errors If the timeout is detected this bit is set to 1 and PHY_VIEWPORT_PENDING is cleared. This bit is cleared when the read/write access is.." "No errors,Timeout" newline hexmask.long.byte 0x0 23.--29. 1. "RSVDP_23,Reserved for future use." newline bitfld.long 0x0 22. "PHY_VIEWPORT_TIMEOUT_DISABLE,PHY viewport timeout disable. Disables the PHY register access timeout structure. When the timeout is disabled you must ensure that the PHY register accesses are always acknowledged by cr_para_ack. Otherwise.." "0,1" newline bitfld.long 0x0 21. "PHY_VIEWPORT_BCWR,Broadcast write access to all xN sub-blocks. If you need to broadcast the write accesses into all lanes both PHY_VIEWPORT_ADDR[15] and this bit should be 1. Note: This register field is sticky." "0,1" newline bitfld.long 0x0 20. "PHY_VIEWPORT_READ,PHY viewport read. If set a read access is initiated. The value is always 0 when this bit is read. Note: This register field is sticky." "0,1" newline hexmask.long.byte 0x0 16.--19. 1. "PHY_VIEWPORT_NUM,PHY viewport xN sub-block number. Selects one of xN sub-blocks. This register is not used when the write access is initiated with PHY_VIEWPORT_BCWR==1. Note: This register field is sticky." newline hexmask.long.word 0x0 0.--15. 1. "PHY_VIEWPORT_ADDR,PHY viewport address. Indicates the PHY's register address. Please refer to the PHY databook for the address map definition. Note: This register field is sticky." line.long 0x4 "PHY_VIEWPORT_DATA_OFF,PHY Register Viewport Data Register." hexmask.long.word 0x4 16.--31. 1. "RSVDP_16,Reserved for future use." newline hexmask.long.word 0x4 0.--15. 1. "PHY_VIEWPORT_DATA,PHY viewport data. A write access to this register initiates the PHY register write access. By a read access to this register this field returns the latest read data from the PHY register. Note: This register field is sticky." group.long (0x490+0x700)++0x3 line.long 0x0 "PIPE_RELATED_OFF,PIPE Related Register. This register controls the pipe's capabitity. control. and status parameters." hexmask.long.tbyte 0x0 9.--31. 1. "RSVDP_9,Reserved for future use." newline bitfld.long 0x0 8. "PIPE_GARBAGE_DATA_MODE,PIPE Garbage Data Mode. - 0: PIPE Spec compliant mode: The MAC discards any symbols received after the electrical idle ordered-set until RxValid is deasserted. - 1: Special PHY Support mode: The MAC discards any symbols received.." "PIPE Spec compliant mode: The MAC discards any..,Special PHY Support mode: The MAC discards any.." tree.end tree.end tree "PCIE2_ATU_DMA" base ad:0xF11C0000 tree "PF0_TYPE1_HDR (PCI-Compatible Configuration Space Header Type1)" group.long 0x0++0x2F line.long 0x0 "TYPE1_DEV_ID_VEND_ID_REG,Device ID and Vendor ID Register." hexmask.long.word 0x0 16.--31. 1. "DEVICE_ID,Device ID. The Device ID register identifies the particular Function. This identifier is allocated by the vendor. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else.." newline hexmask.long.word 0x0 0.--15. 1. "VENDOR_ID,Vendor ID. The Vendor ID register identifies the manufacturer of the Function. Valid vendor identifiers are allocated by the PCI-SIG to ensure uniqueness. It is not permitted to populate this register with a value of FFFFh which is an invalid.." line.long 0x4 "TYPE1_STATUS_COMMAND_REG,Status and Command Register." bitfld.long 0x4 31. "DETECTED_PARITY_ERROR,Detected Parity Error. This bit is set by a Function whenever it receives a Poisoned TLP regardless of the state the Parity Error Response bit in the Command register. The bit is set when the Poisoned TLP is received by a.." "0,1" newline bitfld.long 0x4 30. "SIGNALED_SYS_ERROR,Signaled System Error. This bit is set when a Function sends an ERR_FATAL or ERR_NONFATAL Message and the SERR# Enable bit in the Command register is 1b." "0,1" newline bitfld.long 0x4 29. "RCVD_MASTER_ABORT,Received Master Abort. This bit is set when a Requester receives a Completion with Unsupported Request Completion status. The bit is set when the Unsupported Request is received by a Function's primary side." "0,1" newline bitfld.long 0x4 28. "RCVD_TARGET_ABORT,Received Target Abort. This bit is set when a Requester receives a Completion with Completer Abort Completion status. The bit is set when the Completer Abort is received by a Function's primary side." "0,1" newline bitfld.long 0x4 27. "SIGNALED_TARGET_ABORT,Signaled Target Abort. This bit is set when a Function completes a Posted or Non-Posted Request as a Completer Abort error. This applies to a Function when the Completer Abort was generated by its primary side." "0,1" newline rbitfld.long 0x4 25.--26. "DEV_SEL_TIMING,DEVSEL Timing. This field was originally described in the PCI Local Bus Specification. Its functionality does not apply to PCI Express. The controller hardwires it to 00b." "0,1,2,3" newline bitfld.long 0x4 24. "MASTER_DPE,Master Data Parity Error. This bit is set by a Function if the Parity Error Response bit in the Command register is 1b and either of the following two conditions occurs: - Port receives a Poisoned Completion going downstream - Port transmits a.." "0,1" newline rbitfld.long 0x4 23. "FAST_B2B_CAP,Fast Back-to-Back Transactions Capable. This bit was originally described in the PCI Local Bus Specification. Its functionality does not apply to PCI Express. The controller hardwires this bit to 0b." "0,1" newline rbitfld.long 0x4 22. "RSVDP_22,Reserved for future use." "0,1" newline rbitfld.long 0x4 21. "FAST_66MHZ_CAP,66 MHz Capable. This bit was originally described in the PCI Local Bus Specification. Its functionality does not apply to PCI Express. The controller hardwires this bit to 0b." "0,1" newline rbitfld.long 0x4 20. "CAP_LIST,Capabilities List. Indicates the presence of an Extended Capability list item. Since all PCI Express device Functions are required to implement the PCI Express Capability structure the controller hardwires this bit to 1b." "0,1" newline rbitfld.long 0x4 19. "INT_STATUS,Interrupt Status. When set indicates that an INTx emulation interrupt is pending internally in the Function. INTx emulation interrupts forwarded by Functions from the secondary side are not reflected in this bit. Setting the Interrupt Disable.." "0,1" newline rbitfld.long 0x4 17.--18. "RSVDP_17,Reserved for future use." "0,1,2,3" newline bitfld.long 0x4 16. "IMM_READINESS,Immediate Readiness. This optional bit when set indicates the Function is guaranteed to be ready to successfully complete valid configuration accesses at any time following any reset that the host is capable of issuing Configuration.." "0,1" newline hexmask.long.byte 0x4 11.--15. 1. "RESERV,Reserved." newline bitfld.long 0x4 10. "INT_EN,Interrupt Disable. Controls the ability of a Function to generate INTx emulation interrupts. When set Functions are prevented from asserting INTx interrupts. Note: - Any INTx emulation interrupts already asserted by the Function must be.." "0,1" newline rbitfld.long 0x4 9. "RSVDP_9,Reserved for future use." "0,1" newline bitfld.long 0x4 8. "SERREN,SERR# Enable. When set this bit enables reporting upstream of Non-fatal and Fatal errors detected by the Function. Note: The errors are reported if enabled either through this bit or through the PCI Express specific bits in the Device Control.." "0,1" newline rbitfld.long 0x4 7. "IDSEL,IDSEL Stepping/Wait Cycle Control. This bit was originally described in the PCI Local Bus Specification. Its functionality does not apply to PCI Express. The controller hardwires this bit to 0b." "0,1" newline bitfld.long 0x4 6. "PERREN,Parity Error Response. This bit controls the logging of poisoned TLPs in the Master Data Parity Error bit in the Status register. For more details see the 'Error Registers' section of the PCI Express Base Specification." "0,1" newline rbitfld.long 0x4 5. "VGAPS,VGA Palette Snoop. This bit was originally described in the PCI Local Bus Specification and the PCI-to-PCI Bridge Architecture Specification. Its functionality does not apply to PCI Express. The controller hardwires this bit to 0b." "0,1" newline rbitfld.long 0x4 4. "MWI_EN,Memory Write and Invalidate. This bit was originally described in the PCI Local Bus Specification and the PCI-to-PCI Bridge Architecture Specification. Its functionality does not apply to PCI Express. The controller hardwires this bit to 0b. For.." "0,1" newline rbitfld.long 0x4 3. "SCO,Special Cycle Enable. This bit was originally described in the PCI Local Bus Specification. Its functionality does not apply to PCI Express. The controller hardwires this bit to 0b." "0,1" newline bitfld.long 0x4 2. "BME,Bus Master Enable. This bit controls forwarding of Memory or I/O requests by a port in the Upstream direction. When this bit is 0b Memory and I/O Requests received at a Root Port must be handled as Unsupported Requests (UR) For Non-Posted Requests a.." "0,1" newline bitfld.long 0x4 1. "MSE,Memory Space Enable. This bit controls a Function's response to Memory Space accesses received on its primary side. - When set the Function is enabled to decode the address and further process Memory Space accesses. - When clear all received Memory.." "0,1" newline bitfld.long 0x4 0. "IO_EN,IO Space Enable. This bit controls a Function's response to I/O Space accesses received on its primary side. - When set the Function is enabled to decode the address and further process I/O Space accesses. - When clear all received I/O accesses.." "0,1" line.long 0x8 "TYPE1_CLASS_CODE_REV_ID_REG,Class Code and Revision ID Register." hexmask.long.byte 0x8 24.--31. 1. "BASE_CLASS_CODE,Base Class Code. A code that broadly classifies the type of operation the Function performs. Encodings for base class are provided in the PCI Code and ID Assignment Specification. All unspecified encodings are reserved. Note: The access.." newline hexmask.long.byte 0x8 16.--23. 1. "SUBCLASS_CODE,Sub-Class Code. Specifies a base class sub-class which identifies more specifically the operation of the Function. Encodings for sub-class are provided in the PCI Code and ID Assignment Specification. All unspecified encodings are.." newline hexmask.long.byte 0x8 8.--15. 1. "PROGRAM_INTERFACE,Programming Interface. This field identifies a specific register level programming interface (if any) so that device independent software can interact with the Function. Encodings for interface are provided in the PCI Code and ID.." newline hexmask.long.byte 0x8 0.--7. 1. "REVISION_ID,Revision ID. The value of this field specifies a Function specific revision identifier. The value is chosen by the vendor. Zero is an acceptable value. The Revision ID should be viewed as a vendor defined extension to the Device ID. Note: The.." line.long 0xC "TYPE1_BIST_HDR_TYPE_LAT_CACHE_LINE_SIZE_REG,BIST. Header Type. Latency Timer. and Cache Line Size Register." hexmask.long.byte 0xC 24.--31. 1. "BIST,BIST. This register is used for control and status of BIST. Functions that do not support BIST must hardwire the register to 00h. A Function whose BIST is invoked must not prevent normal operation of the PCI Express Link. Bit descriptions: - [31]:.." newline rbitfld.long 0xC 23. "MULTI_FUNC,Multi-Function Device. - When set indicates that the device may contain multiple Functions but not necessarily. Software is permitted to probe for Functions other than Function 0. - When clear software must not probe for Functions other.." "0,1" newline hexmask.long.byte 0xC 16.--22. 1. "HEADER_TYPE,Header Layout. This field identifies the layout of the second part of the predefined header. The controller uses 000 0001b encoding. The encoding 000 0010b is reserved. This encoding was originally described in the PC Card Standard Electrical.." newline hexmask.long.byte 0xC 8.--15. 1. "LATENCY_MASTER_TIMER,Latency Timer. This register is also referred to as Primary Latency Timer. The Latency Timer was originally described in the PCI Local Bus Specification and the PCI-to-PCI Bridge Architecture Specification. Its functionality does not.." newline hexmask.long.byte 0xC 0.--7. 1. "CACHE_LINE_SIZE,Cache Line Size. The Cache Line Size register is programmed by the system firmware or the operating system to system cache line size. However legacy conventional PCI software may not always be able to program this register correctly.." line.long 0x10 "BAR0_REG,BAR0 Register. System software must build a consistent address map before booting the machine to an operating system. This means it has to determine how much memory is in the system. and how much address space the Functions in the system.." hexmask.long 0x10 4.--31. 1. "BAR0_START,BAR0 Base Address. - Memory Space: Base Address. - IO Space: bits[31:2] are used to map the function into IO space/Base. Address. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R(Sticky)/W(Sticky) if.." newline bitfld.long 0x10 3. "BAR0_PREFETCH,BAR0 Prefetchable. - Memory Space: Set to one if data is pre-fetchable. A Function is permitted to mark a range as prefetchable. If there are no side effects on reads the function returns all bytes on reads regardless of the byte enables.." "0,1" newline bitfld.long 0x10 1.--2. "BAR0_TYPE,BAR0 Type. - Memory Space: Base Address registers that map into Memory Space can be 32 bits or 64 bits wide (to support mapping into a 64-bit address space). The bit encoding is as follows: -- 00: Base register is 32 bits wide and can be mapped.." "Base register is 32 bits wide and can be mapped..,Reserved,?,?" newline bitfld.long 0x10 0. "BAR0_MEM_IO,BAR0 Memory Space Indicator. This bit is used to determine whether the register maps into Memory or I/O Space. Base Address registers that map to Memory Space must return a 0b. Base Address registers that map to I/O Space must return a 1b." "0,1" line.long 0x14 "BAR1_REG,BAR1 Register. System software must build a consistent address map before booting the machine to an operating system. This means it has to determine how much memory is in the system. and how much address space the Functions in the system.." hexmask.long 0x14 4.--31. 1. "BAR1_START,BAR1 Base Address. - Memory Space: Base Address. - IO Space: bits[31:2] are used to map the function into IO space/Base. Address. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R(Sticky)/W(Sticky) if.." newline bitfld.long 0x14 3. "BAR1_PREFETCH,BAR1 Prefetchable. - Memory Space: Set to one if data is pre-fetchable. A Function is permitted to mark a range as prefetchable. If there are no side effects on reads the function returns all bytes on reads regardless of the byte enables.." "0,1" newline bitfld.long 0x14 1.--2. "BAR1_TYPE,BAR1 Type. - Memory Space: Base Address registers that map into Memory Space can be 32 bits or 64 bits wide (to support mapping into a 64-bit address space). The bit encoding is as follows: -- 00: Base register is 32 bits wide and can be mapped.." "Base register is 32 bits wide and can be mapped..,Reserved,?,?" newline bitfld.long 0x14 0. "BAR1_MEM_IO,BAR1 Memory Space Indicator. This bit is used to determine whether the register maps into Memory or I/O Space. Base Address registers that map to Memory Space must return a 0b. Base Address registers that map to I/O Space must return a 1b." "0,1" line.long 0x18 "SEC_LAT_TIMER_SUB_BUS_SEC_BUS_PRI_BUS_REG,Secondary Latency Timer. Subordinate Bus Number. Secondary Bus Number. and Primary Bus Number Register." hexmask.long.byte 0x18 24.--31. 1. "SEC_LAT_TIMER,Secondary Latency Timer. This register does not apply to PCI Express. The controller hardwires it to 00h." newline hexmask.long.byte 0x18 16.--23. 1. "SUB_BUS,Subordinate Bus Number. The Subordinate Bus Number register is used to record the bus number of the highest numbered PCI bus segment which is behind (or subordinate to) the bridge. Configuration software programs the value in this register. The.." newline hexmask.long.byte 0x18 8.--15. 1. "SEC_BUS,Secondary Bus Number. The Secondary Bus Number register is used to record the bus number of the PCI bus segment to which the secondary interface of the bridge is connected. Configuration software programs the value in this register. The bridge.." newline hexmask.long.byte 0x18 0.--7. 1. "PRIM_BUS,Primary Bus Number. This register is not used by PCI Express Functions. It is implemented for compatibility with legacy software." line.long 0x1C "SEC_STAT_IO_LIMIT_IO_BASE_REG,Secondary Status. and I/O Limit and Base Register. The I/O Limit and I/O Base registers are optional and define an address range that is used by the bridge to determine when to forward I/O transactions from one interface to.." bitfld.long 0x1C 31. "SEC_STAT_DPE,Detected Parity Error. This bit is set by a Function when a Poisoned TLP is received by its secondary side regardless of the state the Parity Error Response Enable bit in the Bridge Control register." "0,1" newline bitfld.long 0x1C 30. "SEC_STAT_RCVD_SYS_ERR,Received System Error. This bit is set when the secondary side of a Function receives an ERR_FATAL or ERR_NONFATAL message." "0,1" newline bitfld.long 0x1C 29. "SEC_STAT_RCVD_MSTR_ABRT,Received Master Abort. This bit is set when the secondary side of a Function (for requests initiated by the Type 1 header Function itself) receives a Completion with Unsupported Request Completion status." "0,1" newline bitfld.long 0x1C 28. "SEC_STAT_RCVD_TRGT_ABRT,Received Target Abort. This bit is set when the secondary side of a Function (for requests initiated by the Type 1 header Function itself) receives a Completion with Completer Abort Completion status." "0,1" newline bitfld.long 0x1C 27. "SEC_STAT_SIG_TRGT_ABRT,Signaled Target Abort. This bit is set when the secondary side of the Function (for Requests completed by the Type 1 header Function itself) completes a Posted or Non-Posted request as a Completer Abort error." "0,1" newline rbitfld.long 0x1C 25.--26. "RSVDP_25,Reserved for future use." "0,1,2,3" newline bitfld.long 0x1C 24. "SEC_STAT_MDPE,Master Data Parity Error. This bit is set by a Function if the Parity Error Response Enable bit in the Bridge Control register is set and either of the following two conditions occurs: - Port receives a Poisoned Completion coming Upstream.." "0,1" newline rbitfld.long 0x1C 23. "RSVDP_23,Reserved for future use." "0,1" newline hexmask.long.byte 0x1C 16.--22. 1. "SEC_STAT_RESERV,Reserved." newline hexmask.long.byte 0x1C 12.--15. 1. "IO_LIMIT,I/O Limit Address. These bits correspond to the address[15:12] of IO address range. For the purpose of address decoding the bridge assumes that the lower 12 address bits address[11:0] of the I/O limit address (not implemented in the I/O Limit.." newline rbitfld.long 0x1C 9.--11. "IO_RESERV1,Reserved." "0,1,2,3,4,5,6,7" newline bitfld.long 0x1C 8. "IO_DECODE_BIT8,I/O Addressing Encode (IO Limit Address). This bit encodes the IO addressing capability of the bridge. IO_DECODE_BIT8 indicates the following: - 0h: The bridge supports only 16-bit I/O addressing (for ISA compatibility). For the purpose of.." "0,1" newline hexmask.long.byte 0x1C 4.--7. 1. "IO_BASE,I/O Base Address. These bits correspond to the address[15:12] of IO address range. For the purpose of address decoding the bridge assumes that the lower 12 address bits address[11:0] of the I/O base address (not implemented in the I/O Base.." newline rbitfld.long 0x1C 1.--3. "IO_RESERV,Reserved." "0,1,2,3,4,5,6,7" newline bitfld.long 0x1C 0. "IO_DECODE,I/O Addressing Encode (IO Base Address) This bit encodes the IO addressing capability of the bridge. IO_DECODE indicates the following: - 0h: The bridge supports only 16-bit I/O addressing (for ISA compatibility). For the purpose of address.." "0,1" line.long 0x20 "MEM_LIMIT_MEM_BASE_REG,Memory Limit and Base Register. The Memory Limit and Memory Base registers define a memory mapped address range which is used by the bridge to determine when to forward memory transactions from one interface to the other. If there.." hexmask.long.word 0x20 20.--31. 1. "MEM_LIMIT,Memory Limit Address. These bits correspond to the upper 12 address bits Address[31:20] of 32-bit addresses. For the purpose of address decoding the bridge assumes that the lower 20 address bits Address[19:0] of the memory limit address.." newline hexmask.long.byte 0x20 16.--19. 1. "MEM_LIMIT_RESERV,Reserved." newline hexmask.long.word 0x20 4.--15. 1. "MEM_BASE,Memory Base Address. These bits correspond to the upper 12 address bits Address[31:20] of 32-bit addresses. For the purpose of address decoding the bridge assumes that the lower 20 address bits Address[19:0] of the memory base address (not.." newline hexmask.long.byte 0x20 0.--3. 1. "MEM_BASE_RESERV,Reserved." line.long 0x24 "PREF_MEM_LIMIT_PREF_MEM_BASE_REG,Prefetchable Memory Limit and Base Register. The Prefetchable Memory Limit and Prefetchable Memory Base registers must indicate that 64-bit addresses are supported. as defined in PCI-to-PCI Bridge Architecture.." hexmask.long.word 0x24 20.--31. 1. "PREF_MEM_LIMIT,Prefetchable Memory Limit Address. If the Prefetchable Memory Limit register indicates support for 32-bit addressing then the Prefetchable Limit Upper 32 Bits register is implemented as a read-only register that returns zero when read. If.." newline rbitfld.long 0x24 17.--19. "PREF_RESERV1,Reserved." "0,1,2,3,4,5,6,7" newline rbitfld.long 0x24 16. "PREF_MEM_LIMIT_DECODE,Prefetchable Memory Limit Decode. This bit encodes whether or not the bridge supports 64-bit addresses. Note: This bit is a copy of the PREF_MEM_DECODE bit and always reflects the current value of that bit. The value of.." "0,1" newline hexmask.long.word 0x24 4.--15. 1. "PREF_MEM_BASE,Prefetchable Memory Base Address. If the Prefetchable Memory Base register indicates support for 32-bit addressing then the Prefetchable Base Upper 32 Bits register is implemented as a read-only register that returns zero when read. If the.." newline rbitfld.long 0x24 1.--3. "PREF_RESERV,Reserved." "0,1,2,3,4,5,6,7" newline bitfld.long 0x24 0. "PREF_MEM_DECODE,Prefetchable Memory Base Decode. This bit encodes whether or not the bridge supports 64-bit addresses. Note: By default the bit is set to 1'b1 indicating that 64-bit addresses are supported. If the bridge only supports 32-bit prefetchable.." "0,1" line.long 0x28 "PREF_BASE_UPPER_REG,Prefetchable Base Upper 32 Bits Register. The Prefetchable Base Upper 32 Bits register is an optional extension to the Prefetchable Memory Base register." hexmask.long 0x28 0.--31. 1. "PREF_MEM_BASE_UPPER,Prefetchable Base Upper 32 Bit. If the Prefetchable Memory Base register indicates support for 32-bit addressing then this register is implemented as read-only register that returns zero when read. If the Prefetchable Memory Base.." line.long 0x2C "PREF_LIMIT_UPPER_REG,Prefetchable Limit Upper 32 Bits Register. The Prefetchable Limit Upper 32 Bits register is an optional extension to the Prefetchable Memory Limit register." hexmask.long 0x2C 0.--31. 1. "PREF_MEM_LIMIT_UPPER,Prefetchable Limit Upper 32 Bit. If the Prefetchable Memory Limit register indicate support for 64-bit addressing then this register is implemented as read/write register which must be initialized by configuration software. This.." rgroup.long 0x30++0x3 line.long 0x0 "IO_LIMIT_UPPER_IO_BASE_UPPER_REG,I/O Limit and Base Upper 16 Bits Register. The I/O Limit Upper 16 Bits and I/O Base Upper 16 Bits registers are optional extensions to the I/O Limit and I/O Base registers." hexmask.long.word 0x0 16.--31. 1. "IO_LIMIT_UPPER,I/O Limit Upper 16 Bits. If the I/O Limit register indicates support for 16-bit I/O address decoding then this register is implemented as a read-only register which return zero when read. If the I/O Limit register indicates support for.." newline hexmask.long.word 0x0 0.--15. 1. "IO_BASE_UPPER,I/O Base Upper 16 Bits. If the I/O Base register indicates support for 16-bit I/O address decoding then this register is implemented as a read-only register which return zero when read. If the I/O base register indicates support for 32-bit.." group.long 0x34++0xB line.long 0x0 "TYPE1_CAP_PTR_REG,Capabilities Pointer Register." hexmask.long.tbyte 0x0 8.--31. 1. "RSVDP_8,Reserved for future use." newline hexmask.long.byte 0x0 0.--7. 1. "CAP_POINTER,Capabilities Pointer. This register is used to point to a linked list of capabilities implemented by this Function. Since all PCI Express Functions are required to implement the PCI Express Capability structure this register must point to a.." line.long 0x4 "TYPE1_EXP_ROM_BASE_REG,Expansion ROM Base Address Register. This register is defined to handle the base address and size information for this expansion ROM. The mask for this ROM BAR exists (if implemented) as a shadow register at this address. The.." hexmask.long.tbyte 0x4 11.--31. 1. "EXP_ROM_BASE_ADDRESS,Expansion ROM Base Address. Upper 21 bits of the Expansion ROM base address. The number of bits (out of these 21) that a Function actually implements depends on how much address space the Function requires. The mask for this ROM BAR.." newline hexmask.long.word 0x4 1.--10. 1. "RSVDP_1,Reserved for future use." newline bitfld.long 0x4 0. "ROM_BAR_ENABLE,Expansion ROM Enable. This bit controls whether or not the Function accepts accesses to its expansion ROM. When this bit is 0b the Function's expansion ROM address space is disabled. When the bit is 1b address decoding is enabled using.." "0,1" line.long 0x8 "BRIDGE_CTRL_INT_PIN_INT_LINE_REG,Bridge Control. Interrupt Pin. and Interrupt Line Register." hexmask.long.word 0x8 23.--31. 1. "BRIDGE_CTRL_RESERV,Reserved." newline bitfld.long 0x8 22. "SBR,Secondary Bus Reset. Setting this bit triggers a hot reset on the corresponding PCI Express Port. Software must ensure a minimum reset duration (Trst) as defined in the PCI Local Bus Specification. Software and systems must honor.." "0,1" newline rbitfld.long 0x8 21. "MSTR_ABORT_MODE,Master Abort Mode. This bit was originally described in the PCI-to-PCI Bridge Architecture Specification. Its functionality does not apply to PCI Express. The controller hardwires this bit to 0b. Note: The access attributes of this field.." "0,1" newline rbitfld.long 0x8 20. "VGA_16B_DEC,VGA 16 bit decode. This bit only has meaning if VGA Enable bit is set. This bit enables system configuration software to select between 10-bit and 16-bit I/O address decoding for all VGA I/O register accesses that are forwarded from primary.." "0,1" newline rbitfld.long 0x8 19. "VGA_EN,VGA Enable. Modifies the response by the bridge to VGA compatible addresses. If the VGA Enable bit is set the bridge will positively decode and forward the following accesses on the primary interface to the secondary interface (and conversely.." "0,1" newline bitfld.long 0x8 18. "ISA_EN,ISA Enable. Modifies the response by the bridge to ISA I/O addresses. This applies only to I/O addresses that are enabled by the I/O Base and I/O Limit registers and are in the first 64 KB of I/O address space (0000 0000h to 0000 FFFFh). If this.." "?,KB block" newline bitfld.long 0x8 17. "SERR_EN,SERR# Enable. This bit controls forwarding of ERR_COR ERR_NONFATAL and ERR_FATAL from secondary to primary." "0,1" newline bitfld.long 0x8 16. "PERE,Parity Error Response Enable. This bit controls the logging of poisoned TLPs in the Master Data Parity Error bit in the Secondary Status register." "0,1" newline hexmask.long.byte 0x8 8.--15. 1. "INT_PIN,Interrupt PIN. The Interrupt Pin register register that identifies the legacy interrupt Message(s) the Function uses. Valid values are: - 01h 02h 03h and 04h: map to legacy interrupt Messages for INTA INTB INTC and INTD respectively. - 00h:.." newline hexmask.long.byte 0x8 0.--7. 1. "INT_LINE,Interrupt Line. The Interrupt Line register communicates interrupt line routing information. The register must be implemented by any Function that uses an interrupt pin. Values in this register are programmed by system software and are system.." tree.end tree "PF0_SPCIE_CAP (Secondary PCI Express Capability Structure)" group.long (0x0+0x1A0)++0xF line.long 0x0 "SPCIE_CAP_HEADER_REG,SPCIE Capability Header. For a description of this standard PCIe register. see the PCI Express Specification." hexmask.long.word 0x0 20.--31. 1. "NEXT_OFFSET,Next Capability Offset. For a description of this standard PCIe register field see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky).." hexmask.long.byte 0x0 16.--19. 1. "CAP_VERSION,Capability Version. For a description of this standard PCIe register field see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else.." hexmask.long.word 0x0 0.--15. 1. "EXTENDED_CAP_ID,Secondary PCI Express Extended Capability ID. For a description of this standard PCIe register field see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN.." line.long 0x4 "LINK_CONTROL3_REG,Link Control 3 Register. For a description of this standard PCIe register. see the PCI Express Specification." hexmask.long 0x4 2.--31. 1. "RSVDP_2,Reserved for future use." bitfld.long 0x4 1. "EQ_REQ_INT_EN,Link Equalization Request Interrupt Enable. For a description of this standard PCIe register field see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" "0,1" bitfld.long 0x4 0. "PERFORM_EQ,Perform Equalization. For a description of this standard PCIe register field see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" "0,1" line.long 0x8 "LANE_ERR_STATUS_REG,Lane Error Status Register. For a description of this standard PCIe register. see the PCI Express Specification." hexmask.long 0x8 1.--31. 1. "RSVDP_LANE_ERR_STATUS,Reserved for future use." bitfld.long 0x8 0. "LANE_ERR_STATUS,Lane Error Status Bits per Lane. For a description of this standard PCIe register field see the PCI Express Specification." "0,1" line.long 0xC "SPCIE_CAP_OFF_0CH_REG,Lane Equalization Control Register for lanes 1 and 0. For a description of this standard PCIe register. see the PCI Express Specification." rbitfld.long 0xC 31. "RSVDP_31,Reserved for future use." "0,1" rbitfld.long 0xC 23. "RSVDP_23,Reserved for future use." "0,1" rbitfld.long 0xC 15. "RSVDP_15,Reserved for future use." "0,1" bitfld.long 0xC 12.--14. "USP_RX_PRESET_HINT0,Upstream Port 8.0 GT/s Receiver Preset Hint 0. The write value is gated with the PCIE_CAP_CROSS_LINK_SUPPORT field of LINK_CAPABILITIES2_REG. For a description of this standard PCIe register field see the PCI Express Specification." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0xC 8.--11. 1. "USP_TX_PRESET0,Upstream Port 8.0 GT/s Transmitter Preset 0. The write value is gated with the PCIE_CAP_CROSS_LINK_SUPPORT field of LINK_CAPABILITIES2_REG. For a description of this standard PCIe register field see the PCI Express Specification. Note:.." rbitfld.long 0xC 7. "RSVDP_7,Reserved for future use." "0,1" bitfld.long 0xC 4.--6. "DSP_RX_PRESET_HINT0,Downstream Port 8.0 GT/s Receiver Preset Hint 0. For a description of this standard PCIe register field see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if.." "0,1,2,3,4,5,6,7" hexmask.long.byte 0xC 0.--3. 1. "DSP_TX_PRESET0,Downstream Port 8.0 GT/s Transmitter Preset 0. For a description of this standard PCIe register field see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN.." tree.end tree "PF0_L1SUB_CAP (L1 Substates Capability Structure)" group.long (0x0+0x2A0)++0xF line.long 0x0 "L1SUB_CAP_HEADER_REG,L1 Substates Extended Capability Header. This register provides capbility ID. capability version and next offset value for L1 Substates." hexmask.long.word 0x0 20.--31. 1. "NEXT_OFFSET,Next Capability Offset. This field contains the offset to the next PCI Express Capability structure or 000h if no other items exist in the linked list of Capabilities. For Extended Capabilities implemented in Configuration Space this offset.." hexmask.long.byte 0x0 16.--19. 1. "CAP_VERSION,Capability Version. This field is a PCI-SIG defined version number that indicates the version of the Capability structure present. This field is depends on version of the specification. Note: The access attributes of this field are as.." hexmask.long.word 0x0 0.--15. 1. "EXTENDED_CAP_ID,L1SUB Extended Capability ID. This field is a PCI-SIG defined ID number that indicates the nature and format of the Extended Capability. Extended Capability ID for L1 PM Substates is 001Eh. Note: The access attributes of this field are as.." line.long 0x4 "L1SUB_CAPABILITY_REG,L1 Substates Capability Register. This register provides extended capability of L1 Substates." hexmask.long.byte 0x4 24.--31. 1. "RSVDP_24,Reserved for future use." hexmask.long.byte 0x4 19.--23. 1. "PWR_ON_VALUE_SUPPORT,Port T Power On Value. Along with the Port T_POWER_ON Scale field in the L1 PM Substates Capabilities register sets the time (in us) that this Port requires the port on the opposite side of Link to wait in L1.2.Exit after sampling.." rbitfld.long 0x4 18. "RSVDP_18,Reserved for future use." "0,1" bitfld.long 0x4 16.--17. "PWR_ON_SCALE_SUPPORT,Port T Power On Scale. Specifies the scale used for the Port T_POWER_ON Value field in the L1 PM Substates Capabilities register. Range of values are given below. Required for all Ports for which either the PCI-PM L1.2 Supported bit.." "?,?,?,Reserved" newline hexmask.long.byte 0x4 8.--15. 1. "COMM_MODE_SUPPORT,Port Common Mode Restore Time. Time (in us) required for this Port to re-establish common mode. Required for all Ports for which either the PCI-PM L1.2 Supported bit is Set ASPM L1.2 Supported bit is Set or both are Set otherwise.." rbitfld.long 0x4 5.--7. "RSVDP_5,Reserved for future use." "0,1,2,3,4,5,6,7" bitfld.long 0x4 4. "L1_PMSUB_SUPPORT,L1 PM Substates ECN Supported. When Set this bit indicates that this Port supports L1 PM Substates. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W (sticky)" "0,1" bitfld.long 0x4 3. "L1_1_ASPM_SUPPORT,ASPM L11 Supported. When Set this bit indicates that ASPM L1.1 is supported. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W (sticky)" "0,1" newline bitfld.long 0x4 2. "L1_2_ASPM_SUPPORT,ASPM L12 Supported. When Set this bit indicates that ASPM L1.2 is supported. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W (sticky)" "0,1" bitfld.long 0x4 1. "L1_1_PCIPM_SUPPORT,PCI-PM L11 Supported. When Set this bit indicates that PCI-PM L1.1 is supported and must be Set by all Ports implementing L1 PM Substates. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W (sticky)" "0,1" bitfld.long 0x4 0. "L1_2_PCIPM_SUPPORT,PCI-PM L12 Supported. When Set this bit indicates that PCI-PM L1.2 is supported. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W (sticky)" "0,1" line.long 0x8 "L1SUB_CONTROL1_REG,L1 Substates Control 1 Register. This register provides Controls to extended capability." bitfld.long 0x8 29.--31. "L1_2_TH_SCA,LTR L12 Threshold Scale. This field provides a scale for the value contained within the LTR_L1.2_THRESHOLD_Value.The default value for this field is 000b.Hardware operation is undefined if software writes a Not-Permitted value to this field." "0,1,2,3,4,5,6,7" rbitfld.long 0x8 26.--28. "RSVDP_26,Reserved for future use." "0,1,2,3,4,5,6,7" hexmask.long.word 0x8 16.--25. 1. "L1_2_TH_VAL,LTR L12 Threshold Value. Along with the LTR_L1.2_THRESHOLD_Scale this field indicates the LTR threshold used to determine if entry into L1 results in L1.1 (if enabled) or L1.2 (if enabled). The default value for this field is 00 0000 0000b." hexmask.long.byte 0x8 8.--15. 1. "T_COMMON_MODE,Common Mode Restore Time. Sets value of TCOMMONMODE (in us) which must be used by the Downstream Ports for timing the re-establishment of common mode.This field is of type RsvdP for Upstream Ports. Default value is implementation.." newline hexmask.long.byte 0x8 4.--7. 1. "RSVDP_4,Reserved for future use." bitfld.long 0x8 3. "L1_1_ASPM_EN,ASPM L11 Enable. When Set this bit enables ASPM L1.1.For Ports for which the ASPM L1.1 Supported bit is Clear this bit is permitted to be hardwired to 0.Default value is 0b." "0,1" bitfld.long 0x8 2. "L1_2_ASPM_EN,ASPM L12 Enable. When Set this bit enables ASPM L1.2.For Ports for which the ASPM L1.2 Supported bit is Clear this bit is permitted to be hardwired to 0.Default value is 0b." "0,1" bitfld.long 0x8 1. "L1_1_PCIPM_EN,PCI-PM L11 Enable. When Set this bit enables PCI-PM L1.1. Default value is 0b." "0,1" newline bitfld.long 0x8 0. "L1_2_PCIPM_EN,PCI-PM L12 Enable. When Set this bit enables PCI-PM L1.2.For Ports for which the PCI-PM L1.2 Supported bit is Clear this bit is permitted to be hardwired to 0.Default value is 0b." "0,1" line.long 0xC "L1SUB_CONTROL2_REG,L1 Substates Control 2 Register. This register provides Controls to extended capability." hexmask.long.tbyte 0xC 8.--31. 1. "RSVDP_8,Reserved for future use." hexmask.long.byte 0xC 3.--7. 1. "T_POWER_ON_VALUE,T Power On Value. Along with the T_POWER_ON Scale sets the minimum amount of time (in us) that the Port must wait in L1.2.Exit after sampling CLKREQ# asserted before actively driving the interface.Default value is 00101b. T_POWER_ON is.." rbitfld.long 0xC 2. "RSVDP_2,Reserved for future use." "0,1" bitfld.long 0xC 0.--1. "T_POWER_ON_SCALE,T Power On Scale. Specifies the scale used for T_POWER_ON Value. Range of values are given below. Required for all Ports that support L1.2 otherwise this field is of type RsvdP. This field must only be modified when the ASPM L1.2 Enable.." "?,?,?,Reserved" tree.end tree "PF0_RAS_DES_CAP (RAS D.E.S. Capability Structure (VSEC))" group.long (0x0+0x30C)++0x3 line.long 0x0 "RAS_DES_CAP_HEADER_REG,Vendor-Specific Extended Capability Header. For a description of this standard PCIe register. see the PCI Express Specification." hexmask.long.word 0x0 20.--31. 1. "NEXT_OFFSET,Next Capability Offset. For a description of this standard PCIe register field see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky).." newline hexmask.long.byte 0x0 16.--19. 1. "CAP_VERSION,Capability Version. For a description of this standard PCIe register field see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else.." newline hexmask.long.word 0x0 0.--15. 1. "EXTENDED_CAP_ID,PCI Express Extended Capability ID. For a description of this standard PCIe register field see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then.." rgroup.long (0x4+0x30C)++0x3 line.long 0x0 "VENDOR_SPECIFIC_HEADER_REG,Vendor-Specific Header. For a description of this standard PCIe register. see the PCI Express Specification." hexmask.long.word 0x0 20.--31. 1. "VSEC_LENGTH,VSEC Length. For a description of this standard PCIe register field see the PCI Express Specification." newline hexmask.long.byte 0x0 16.--19. 1. "VSEC_REV,VSEC Rev. For a description of this standard PCIe register field see the PCI Express Specification." newline hexmask.long.word 0x0 0.--15. 1. "VSEC_ID,VSEC ID. For a description of this standard PCIe register field see the PCI Express Specification." group.long (0x8+0x30C)++0x3 line.long 0x0 "EVENT_COUNTER_CONTROL_REG,Event Counter Control. This is a viewport control register. - Setting the EVENT_COUNTER_EVENT_SELECT and EVENT_COUNTER_LANE_SELECT fields in this register determine the Event Counter data returned by the EVENT_COUNTER_DATA_REG.." hexmask.long.byte 0x0 28.--31. 1. "RSVDP_28,Reserved for future use." newline hexmask.long.word 0x0 16.--27. 1. "EVENT_COUNTER_EVENT_SELECT,Event Counter Data Select. This field in conjunction with the EVENT_COUNTER_LANE_SELECT field indexes the Event Counter data returned by the EVENT_COUNTER_DATA_REG register. - 27-24: Group number(4-bit: 0..0x7) - 23-16: Event.." newline hexmask.long.byte 0x0 12.--15. 1. "RSVDP_12,Reserved for future use." newline hexmask.long.byte 0x0 8.--11. 1. "EVENT_COUNTER_LANE_SELECT,Event Counter Lane Select. This field in conjunction with EVENT_COUNTER_EVENT_SELECT indexes the Event Counter data returned by the EVENT_COUNTER_DATA_REG register. - 0x0: Lane0 - 0x1: Lane1 - 0x2: Lane2 - .. - 0xF: Lane15 Note:.." newline rbitfld.long 0x0 7. "EVENT_COUNTER_STATUS,Event Counter Status. This register returns the current value of the Event Counter selected by the following fields: - EVENT_COUNTER_EVENT_SELECT - EVENT_COUNTER_LANE_SELECT Note: This register field is sticky." "0,1" newline rbitfld.long 0x0 5.--6. "RSVDP_5,Reserved for future use." "0,1,2,3" newline bitfld.long 0x0 2.--4. "EVENT_COUNTER_ENABLE,Event Counter Enable. Enables/disables the Event Counter selected by the EVENT_COUNTER_EVENT_SELECT and EVENT_COUNTER_LANE_SELECT fields in this register. By default all event counters are disabled. You can enable/disable a specific.." "no change,per event off,?,?,?,?,?,?" newline bitfld.long 0x0 0.--1. "EVENT_COUNTER_CLEAR,Event Counter Clear. Clears the Event Counter selected by the EVENT_COUNTER_EVENT_SELECT and EVENT_COUNTER_LANE_SELECT fields in this register. You can clear the value of a specific Event Counter by writing the 'per clear' code and.." "no change,per clear,?,?" rgroup.long (0xC+0x30C)++0x3 line.long 0x0 "EVENT_COUNTER_DATA_REG,Event Counter Data. This viewport register returns the data selected by the following fields: - EVENT_COUNTER_EVENT_SELECT in EVENT_COUNTER_CONTROL_REG - EVENT_COUNTER_LANE_SELECT in EVENT_COUNTER_CONTROL_REG For more details. see.." hexmask.long 0x0 0.--31. 1. "EVENT_COUNTER_DATA,Event Counter Data. This register returns the data selected by the following fields: - EVENT_COUNTER_EVENT_SELECT in EVENT_COUNTER_CONTROL_REG - EVENT_COUNTER_LANE_SELECT in EVENT_COUNTER_CONTROL_REG Note: This register field is sticky." group.long (0x10+0x30C)++0x3 line.long 0x0 "TIME_BASED_ANALYSIS_CONTROL_REG,Time-based Analysis Control. Used for controlling the measurement of RX/TX data throughput and time spent in each low-power LTSSM state. For more details. see the RAS DES section in the Core Operations chapter of the.." hexmask.long.byte 0x0 24.--31. 1. "TIME_BASED_REPORT_SELECT,Time-based Report Select. Selects what type of data is measured for the selected duration (TIME_BASED_DURATION_SELECT) and returned in TIME_BASED_ANALYSIS_DATA. Each type of data is measured using one of three types of units: -.." newline hexmask.long.byte 0x0 16.--23. 1. "RSVDP_16,Reserved for future use." newline hexmask.long.byte 0x0 8.--15. 1. "TIME_BASED_DURATION_SELECT,Time-based Duration Select. Selects the duration of time-based analysis. When 'manual control' is selected and TIMER_START is set to '1' this analysis never stops until TIMER_STOP is set to '0'. - 0x0: Manual control - 0x1:.." newline hexmask.long.byte 0x0 1.--7. 1. "RSVDP_1,Reserved for future use." newline bitfld.long 0x0 0. "TIMER_START,Timer Start. - 1: Start/Restart - 0: Stop This bit will be cleared automatically when the measurement is finished. Note: The app_ras_des_tba_ctrl input also sets the contents of this field and controls the measurement start/stop. Note: This.." "Stop,Start/Restart" rgroup.long (0x14+0x30C)++0x7 line.long 0x0 "TIME_BASED_ANALYSIS_DATA_REG,Time-based Analysis Data. Contains the measurement results of RX/TX data throughput and time spent in each low-power LTSSM state. This viewport register returns the data selected by the TIME_BASED_REPORT_SELECT field in.." hexmask.long 0x0 0.--31. 1. "TIME_BASED_ANALYSIS_DATA,Time Based Analysis Data. This register returns the data selected by the TIME_BASED_REPORT_SELECT field in TIME_BASED_ANALYSIS_CONTROL_REG. The results are cleared when next measurement starts. Note: This register field is sticky." line.long 0x4 "TIME_BASED_ANALYSIS_DATA_63_32_REG,Upper 32 bits of Time-based Analysis Data. This viewport register returns the data selected by the TIME_BASED_REPORT_SELECT field in TIME_BASED_ANALYSIS_CONTROL_REG. For more details. see the RAS DES section in the Core.." hexmask.long 0x4 0.--31. 1. "TIME_BASED_ANALYSIS_DATA_63_32,Upper 32 bits of Time Based Analysis Data. Note: This register field is sticky." group.long (0x30+0x30C)++0x5F line.long 0x0 "EINJ_ENABLE_REG,Error Injection Enable. Each type of error insertion is enabled by the corresponding bit in this register. The specific injection controls for each type of error are defined in the following registers: - 0: CRC Error: EINJ0_CRC_REG - 1:.." hexmask.long 0x0 7.--31. 1. "RSVDP_7,Reserved for future use." newline bitfld.long 0x0 6. "ERROR_INJECTION6_ENABLE,Error Injection6 Enable (Specific TLP Error). Enables insertion of errors into the packets that you select. You can set this bit to '1' when you have disabled RAS datapath protection (DP) by setting CX_RASDP = CX_RASDP_RAM_PROT.." "0,1" newline bitfld.long 0x0 5. "ERROR_INJECTION5_ENABLE,Error Injection5 Enable (TLP Duplicate/Nullify Error). Enables insertion of duplicate/nullified TLPs. For more details see the EINJ5_SP_TLP_REG register. Note: This register field is sticky." "0,1" newline bitfld.long 0x0 4. "ERROR_INJECTION4_ENABLE,Error Injection4 Enable (FC Credit Update Error). Enables insertion of errors into UpdateFCs. For more details see the EINJ4_FC_REG register. Note: This register field is sticky." "0,1" newline bitfld.long 0x0 3. "ERROR_INJECTION3_ENABLE,Error Injection3 Enable (Symbol DataK Mask Error or Sync Header Error). Enables DataK masking of special symbols or the breaking of the sync header. For more details see the EINJ3_SYMBOL_REG register. Note: This register field is.." "0,1" newline bitfld.long 0x0 2. "ERROR_INJECTION2_ENABLE,Error Injection2 Enable (DLLP Error). Enables insertion of DLLP errors. For more details see the EINJ2_DLLP_REG register. Note: This register field is sticky." "0,1" newline bitfld.long 0x0 1. "ERROR_INJECTION1_ENABLE,Error Injection1 Enable (Sequence Number Error). Enables insertion of errors into sequence numbers. For more details see the EINJ1_SEQNUM_REG register. Note: This register field is sticky." "0,1" newline bitfld.long 0x0 0. "ERROR_INJECTION0_ENABLE,Error Injection0 Enable (CRC Error). Enables insertion of errors into various CRC. For more details see the EINJ0_CRC_REG register. Note: This register field is sticky." "0,1" line.long 0x4 "EINJ0_CRC_REG,Error Injection Control 0 (CRC Error). Controls the insertion of errors into the CRC. and parity of ordered sets for the selected type of the packets as follows: - LCRC. Bad TLP will be detected at the receiver side; receiver responds with.." hexmask.long.tbyte 0x4 12.--31. 1. "RSVDP_12,Reserved for future use." newline hexmask.long.byte 0x4 8.--11. 1. "EINJ0_CRC_TYPE,Error injection type. Selects the type of CRC error to be inserted. Tx Path - 0000b: New TLP's LCRC error injection - 0001b: 16bCRC error injection of ACK/NAK DLLP - 0010b: 16bCRC error injection of Update-FC DLLP - 0011b: New TLP's ECRC.." newline hexmask.long.byte 0x4 0.--7. 1. "EINJ0_COUNT,Error injection count. Indicates the number of errors. This register is decremented when the errors have been inserted. - If the counter value is 0x01 and error is inserted ERROR_INJECTION0_ENABLE in EINJ_ENABLE_REG returns 0b. - If the.." line.long 0x8 "EINJ1_SEQNUM_REG,Error Injection Control 1 (Sequence Number Error). Controls the sequence number of the specific TLPs and ACK/NAK DLLPs. Data Link Protocol Error will be detected at the Rx side of ACK/NAL DLLPs when one of these conditions is true: -.." rbitfld.long 0x8 29.--31. "RSVDP_29,Reserved for future use." "0,1,2,3,4,5,6,7" newline hexmask.long.word 0x8 16.--28. 1. "EINJ1_BAD_SEQNUM,Bad sequence number. Indicates the value to add/subtract from the naturally-assigned sequence numbers. This value is represented by two's complement. - 0x0FFF: +4095 - .. - 0x0002: +2 - 0x0001: +1 - 0x0000: 0 - 0x1FFF: -1 - 0x1FFE: -2 -.." newline hexmask.long.byte 0x8 9.--15. 1. "RSVDP_9,Reserved for future use." newline bitfld.long 0x8 8. "EINJ1_SEQNUM_TYPE,Sequence number type. Selects the type of sequence number. - 0b: Insertion of New TLP's SEQ# error - 1b: Insertion of ACK/NAK DLLP's SEQ# Error Note: This register field is sticky." "0,1" newline hexmask.long.byte 0x8 0.--7. 1. "EINJ1_COUNT,Error injection count. Indicates the number of errors. This register is decremented as the errors are being inserted. - If the counter value is 0x01 and error is inserted ERROR_INJECTION1_ENABLE in EINJ_ENABLE_REG returns '0'. - If the.." line.long 0xC "EINJ2_DLLP_REG,Error Injection Control 2 (DLLP Error). Controls the transmission of DLLPs and inserts the following errors: - If 'ACK/NAK DLLP's transmission block' is selected. replay timeout error will occur at the transmitter of the TLPs and then Data.." hexmask.long.tbyte 0xC 10.--31. 1. "RSVDP_10,Reserved for future use." newline bitfld.long 0xC 8.--9. "EINJ2_DLLP_TYPE,DLLP Type. Selects the type of DLLP errors to be inserted. - 00b: ACK/NAK DLLP's transmission block - 01b: Update FC DLLP's transmission block - 10b: Always Transmission for NAK DLLP - 11b: Reserved Note: This register field is sticky." "0,1,2,3" newline hexmask.long.byte 0xC 0.--7. 1. "EINJ2_COUNT,Error injection count. Indicates the number of errors. This register is decremented as the errors are being inserted. - If the counter value is 0x01 and the error is inserted ERROR_INJECTION2_ENABLE in EINJ_ENABLE_REG returns '0'. - If the.." line.long 0x10 "EINJ3_SYMBOL_REG,Error Injection Control 3 (Symbol Error). When 8b/10b encoding is used. this register controls error insertion into the special (K code) symbols. - If TS1/TS2/FTS/E-Idle/SKP is selected. it affects whole of the ordered set. It might.." hexmask.long.tbyte 0x10 11.--31. 1. "RSVDP_11,Reserved for future use." newline bitfld.long 0x10 8.--10. "EINJ3_SYMBOL_TYPE,Error Type. 8b/10b encoding - Mask K symbol. It is not supported to insert errors into the first ordered-set after exiting from TxElecIdle when CX_FREQ_STEP_EN has been enabled. - 000b: Reserved - 001b: COM/PAD(TS1 Order set) - 010b:.." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x10 0.--7. 1. "EINJ3_COUNT,Error injection count. Indicates the number of errors. This register is decremented as the errors are being inserted. - If the counter value is 0x01 and error is inserted ERROR_INJECTION3_ENABLE in EINJ_ENABLE_REG returns '0'. - If the.." line.long 0x14 "EINJ4_FC_REG,Error Injection Control 4 (FC Credit Error). Controls error insertion into the credit value in the UpdateFCs. It is possible to insert errors for any of the following types: - Posted TLP Header credit - Non-Posted TLP Header credit -.." rbitfld.long 0x14 29.--31. "RSVDP_29,Reserved for future use." "0,1,2,3,4,5,6,7" newline hexmask.long.word 0x14 16.--28. 1. "EINJ4_BAD_UPDFC_VALUE,Bad update-FC credit value. Indicates the value to add/subtract from the UpdateFC credit. This value is represented by two's complement. - 0x0FFF: +4095 - .. - 0x0002: +2 - 0x0001: +1 - 0x0000: 0 - 0x1FFF: -1 - 0x1FFE: -2 - .. -.." newline rbitfld.long 0x14 15. "RSVDP_15,Reserved for future use." "0,1" newline bitfld.long 0x14 12.--14. "EINJ4_VC_NUMBER,VC Number. Indicates target VC Number. Note: This register field is sticky." "0,1,2,3,4,5,6,7" newline rbitfld.long 0x14 11. "RSVDP_11,Reserved for future use." "0,1" newline bitfld.long 0x14 8.--10. "EINJ4_UPDFC_TYPE,Update-FC type. Selects the credit type. - 000b: Posted TLP Header Credit value control - 001b: Non-Posted TLP Header Credit value control - 010b: Completion TLP Header Credit value control - 011b: Reserved - 100b: Posted TLP Data Credit.." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x14 0.--7. 1. "EINJ4_COUNT,Error injection count. Indicates the number of errors. This register is decremented as the errors are being inserted. - If the counter value is 0x01 and error is inserted ERROR_INJECTION4_ENABLE in EINJ_ENABLE_REG returns '0'. - If the.." line.long 0x18 "EINJ5_SP_TLP_REG,Error Injection Control 5 (Specific TLP Error). Controls the generation of specified TLPs. Correctable errors will occur which will be fixed by the PCIe protocol. - For Duplicate TLP. the controller initiates Data Link Retry by handling.." hexmask.long.tbyte 0x18 9.--31. 1. "RSVDP_9,Reserved for future use." newline bitfld.long 0x18 8. "EINJ5_SPECIFIED_TLP,Specified TLP. Selects the specified TLP to be inserted. - 0: Generates duplicate TLPs by handling ACK DLLP as NAK DLLP. - 1: Generates Nullified TLP (Original TLP will be stored in retry buffer). Note: This register field is sticky." "Generates duplicate TLPs by handling ACK DLLP as..,Generates Nullified TLP" newline hexmask.long.byte 0x18 0.--7. 1. "EINJ5_COUNT,Error injection count. Indicates the number of errors. This register is decremented as the errors are being inserted. - If the counter value is 0x01 and error is inserted ERROR_INJECTION5_ENABLE in EINJ_ENABLE_REG returns '0'. - If the.." line.long 0x1C "EINJ6_COMPARE_POINT_H0_REG,Error Injection Control 6 (Compare Point Header DWORD #0). Program this register for the 1st DWORD of TLP header/prefix. It is necessary to carefully consider the endianness when you program this register. Bits [31:0] =.." hexmask.long 0x1C 0.--31. 1. "EINJ6_COMPARE_POINT_H0,Packet Compare Point: 1st DWORD. Specifies which Tx TLP header DWORD#0 bits to compare with the corresponding bits in the Packet Compare Value registers (EINJ6_COMPARE_VALUE*). When all specified bits (in the Tx TLP header and.." line.long 0x20 "EINJ6_COMPARE_POINT_H1_REG,Error Injection Control 6 (Compare Point Header DWORD #1). Program this register for the 2nd DWORD of TLP header/prefix. It is necessary to carefully consider the endianness when you program this register. Bits [31:0] =.." hexmask.long 0x20 0.--31. 1. "EINJ6_COMPARE_POINT_H1,Packet Compare Point: 2nd DWORD. Specifies which Tx TLP header DWORD#1 bits to compare with the corresponding bits in the Packet Compare Value registers (EINJ6_COMPARE_VALUE*). When all specified bits (in the Tx TLP header and.." line.long 0x24 "EINJ6_COMPARE_POINT_H2_REG,Error Injection Control 6 (Compare Point Header DWORD #2). Program this register for the 3rd DWORD of TLP header/prefix. It is necessary to carefully consider the endianness when you program this register. Bits [31:0] =.." hexmask.long 0x24 0.--31. 1. "EINJ6_COMPARE_POINT_H2,Packet Compare Point: 3rd DWORD. Specifies which Tx TLP header DWORD#2 bits to compare with the corresponding bits in the Packet Compare Value registers (EINJ6_COMPARE_VALUE*). When all specified bits (in the Tx TLP header and.." line.long 0x28 "EINJ6_COMPARE_POINT_H3_REG,Error Injection Control 6 (Compare Point Header DWORD #3). Program this register for the 4th DWORD of TLP header/prefix. It is necessary to carefully consider the endianness when you program this register. Bits [31:0] =.." hexmask.long 0x28 0.--31. 1. "EINJ6_COMPARE_POINT_H3,Packet Compare Point: 4th DWORD. Specifies which Tx TLP header DWORD#3 bits to compare with the corresponding bits in the Packet Compare Value registers (EINJ6_COMPARE_VALUE*). When all specified bits (in the Tx TLP header and.." line.long 0x2C "EINJ6_COMPARE_VALUE_H0_REG,Error Injection Control 6 (Compare Value Header DWORD #0). Program this register for the 1st DWORD of TLP header/prefix. It is necessary to carefully consider the endianness when you program this register. Bits [31:0] =.." hexmask.long 0x2C 0.--31. 1. "EINJ6_COMPARE_VALUE_H0,Packet Compare Value: 1st DWORD. Specifies the value to compare against Tx the TLP header DWORD#0 bits specified in the Packet Compare Point registers (EINJ6_COMPARE_POINT*). Note: This register field is sticky." line.long 0x30 "EINJ6_COMPARE_VALUE_H1_REG,Error Injection Control 6 (Compare Value Header DWORD #1). Program this register for the 2nd DWORD of TLP header/prefix. It is necessary to carefully consider the endianness when you program this register. Bits [31:0] =.." hexmask.long 0x30 0.--31. 1. "EINJ6_COMPARE_VALUE_H1,Packet Compare Value: 2nd DWORD. Specifies the value to compare against Tx the TLP header DWORD#1 bits specified in the Packet Compare Point registers (EINJ6_COMPARE_POINT*). Note: This register field is sticky." line.long 0x34 "EINJ6_COMPARE_VALUE_H2_REG,Error Injection Control 6 (Compare Value Header DWORD #2). Program this register for the 3rd DWORD of TLP header/prefix. It is necessary to carefully consider the endianness when you program this register. Bits [31:0] =.." hexmask.long 0x34 0.--31. 1. "EINJ6_COMPARE_VALUE_H2,Packet Compare Value: 3rd DWORD. Specifies the value to compare against Tx the TLP header DWORD#2 bits specified in the Packet Compare Point registers (EINJ6_COMPARE_POINT*). Note: This register field is sticky." line.long 0x38 "EINJ6_COMPARE_VALUE_H3_REG,Error Injection Control 6 (Compare Value Header DWORD #3). Program this register for the 4th DWORD of TLP header/prefix. It is necessary to carefully consider the endianness when you program this register. Bits [31:0] =.." hexmask.long 0x38 0.--31. 1. "EINJ6_COMPARE_VALUE_H3,Packet Compare Value: 4th DWORD. Specifies the value to compare against Tx the TLP header DWORD#3 bits specified in the Packet Compare Point registers (EINJ6_COMPARE_POINT*). Note: This register field is sticky." line.long 0x3C "EINJ6_CHANGE_POINT_H0_REG,Error Injection Control 6 (Change Point Header DWORD #0). Program this register for the 1st DWORD of TLP header/prefix. It is necessary to carefully consider the endianness when you program this register. Bits [31:0] =.." hexmask.long 0x3C 0.--31. 1. "EINJ6_CHANGE_POINT_H0,Packet Change Point: 1st DWORD. Specifies which Tx TLP header DWORD#0 bits to replace with the corresponding bits in the Packet Change Value registers (EINJ6_CHANGE_VALUE*). Note: This register field is sticky." line.long 0x40 "EINJ6_CHANGE_POINT_H1_REG,Error Injection Control 6 (Change Point Header DWORD #1). Program this register for the 2nd DWORD of TLP header/prefix. It is necessary to carefully consider the endianness when you program this register. Bits [31:0] =.." hexmask.long 0x40 0.--31. 1. "EINJ6_CHANGE_POINT_H1,Packet Change Point: 2nd DWORD. Specifies which Tx TLP header DWORD#1 bits to replace with the corresponding bits in the Packet Change Value registers (EINJ6_CHANGE_VALUE*). Note: This register field is sticky." line.long 0x44 "EINJ6_CHANGE_POINT_H2_REG,Error Injection Control 6 (Change Point Header DWORD #2). Program this register for the 3rd DWORD of TLP header/prefix. It is necessary to carefully consider the endianness when you program this register. Bits [31:0] =.." hexmask.long 0x44 0.--31. 1. "EINJ6_CHANGE_POINT_H2,Packet Change Point: 3rd DWORD. Specifies which Tx TLP header DWORD#2 bits to replace with the corresponding bits in the Packet Change Value registers (EINJ6_CHANGE_VALUE*). Note: This register field is sticky." line.long 0x48 "EINJ6_CHANGE_POINT_H3_REG,Error Injection Control 6 (Change Point Header DWORD #3). Program this register for the 4th DWORD of TLP header/prefix. It is necessary to carefully consider the endianness when you program this register. Bits [31:0] =.." hexmask.long 0x48 0.--31. 1. "EINJ6_CHANGE_POINT_H3,Packet Change Point: 4th DWORD. Specifies which Tx TLP header DWORD#3 bits to replace with the corresponding bits in the Packet Change Value registers (EINJ6_CHANGE_VALUE*). Note: This register field is sticky." line.long 0x4C "EINJ6_CHANGE_VALUE_H0_REG,Error Injection Control 6 (Change Value Header DWORD #0). Program this register for the 1st DWORD of TLP header/prefix. It is necessary to carefully consider the endianness when you program this register. Bits [31:0] =.." hexmask.long 0x4C 0.--31. 1. "EINJ6_CHANGE_VALUE_H0,Packet Change Value: 1st DWORD. Specifies replacement values for the Tx TLP header DWORD#0 bits defined in the Packet Change Point registers (EINJ6_CHANGE_POINT*). Only applies when the EINJ6_INVERTED_CONTROL field in EINJ6_TLP_REG.." line.long 0x50 "EINJ6_CHANGE_VALUE_H1_REG,Error Injection Control 6 (Change Value Header DWORD #1). Program this register for the 2nd DWORD of TLP header/prefix. It is necessary to carefully consider the endianness when you program this register. Bits [31:0] =.." hexmask.long 0x50 0.--31. 1. "EINJ6_CHANGE_VALUE_H1,Packet Change Value: 2nd DWORD. Specifies replacement values for the Tx TLP header DWORD#1 bits defined in the Packet Change Point registers (EINJ6_CHANGE_POINT*). Only applies when the EINJ6_INVERTED_CONTROL field in EINJ6_TLP_REG.." line.long 0x54 "EINJ6_CHANGE_VALUE_H2_REG,Error Injection Control 6 (Change Value Header DWORD #2). Program this register for the 3rd DWORD of TLP header/prefix. It is necessary to carefully consider the endianness when you program this register. Bits [31:0] =.." hexmask.long 0x54 0.--31. 1. "EINJ6_CHANGE_VALUE_H2,Packet Change Value: 3rd DWORD. Specifies replacement values for the Tx TLP header DWORD#2 bits defined in the Packet Change Point registers (EINJ6_CHANGE_POINT*). Only applies when the EINJ6_INVERTED_CONTROL field in EINJ6_TLP_REG.." line.long 0x58 "EINJ6_CHANGE_VALUE_H3_REG,Error Injection Control 6 (Change Value Header DWORD #3). Program this register for the 4th DWORD of TLP header/prefix. It is necessary to carefully consider the endianness when you program this register. Bits [31:0] =.." hexmask.long 0x58 0.--31. 1. "EINJ6_CHANGE_VALUE_H3,Packet Change Value: 4th DWORD. Specifies replacement values for the Tx TLP header DWORD#3 bits defined in the Packet Change Point registers (EINJ6_CHANGE_POINT*). Only applies when the EINJ6_INVERTED_CONTROL field in EINJ6_TLP_REG.." line.long 0x5C "EINJ6_TLP_REG,Error Injection Control 6 (Packet Error). The Packet Compare Point registers (EINJ6_COMPARE_POINT*) specify which Tx TLP header bits to compare with the corresponding bits in the Packet Compare Value registers (EINJ6_COMPARE_VALUE*). When.." hexmask.long.tbyte 0x5C 12.--31. 1. "RSVDP_12,Reserved for future use." newline bitfld.long 0x5C 9.--11. "EINJ6_PACKET_TYPE,Packet type. Selects the TLP packets to inject errors into. - 0: TLP Header - 1: TLP Prefix 1st 4-DWORDs - 2: TLP Prefix 2nd -DWORDs - Else: Reserved Note: This register field is sticky." "TLP Header,TLP Prefix 1st 4-DWORDs,TLP Prefix 2nd -DWORDs,?,?,?,?,?" newline bitfld.long 0x5C 8. "EINJ6_INVERTED_CONTROL,Inverted Error Injection Control. - 0: EINJ6_CHANGE_VALUE_H[0/1/2/3] is used to replace bits specified by EINJ6_CHANGE_POINT_H[0/1/2/3]. - 1: EINJ6_CHANGE_VALUE_H[0/1/2/3] is ignored and inverts bits specified by.." "EINJ6_CHANGE_VALUE_H[0/1/2/3] is used to replace..,EINJ6_CHANGE_VALUE_H[0/1/2/3] is ignored and.." newline hexmask.long.byte 0x5C 0.--7. 1. "EINJ6_COUNT,Error Injection Count. Indicates the number of errors to insert. This counter is decremented while errors are been inserted. - If the counter value is 0x01 and error is inserted ERROR_INJECTION6_ENABLE in EINJ_ENABLE_REG returns '0'. - If.." group.long (0xA0+0x30C)++0x7 line.long 0x0 "SD_CONTROL1_REG,Silicon Debug Control 1. For more details. see the RAS DES section in the Core Operations chapter of the Databook." hexmask.long.byte 0x0 24.--31. 1. "RSVDP_24,Reserved for future use." newline bitfld.long 0x0 22.--23. "LOW_POWER_INTERVAL,Low Power Entry Interval Time. Interval Time that the controller starts monitoring RXELECIDLE signal after L0s/L1/L2 entry. You should set the value according to the latency from receiving EIOS to RXELECIDLE assertion at the PHY. -.." "0,1,2,3" newline bitfld.long 0x0 20.--21. "TX_EIOS_NUM,Number of Tx EIOS. This register sets the number of transmit EIOS for L0s/L1 entry and Disable/Loopback/Hot-reset exit. The controller selects the greater value between this register and the value defined by the PCI-SIG specification. 2.5GT/s.." "0,1,2,3" newline rbitfld.long 0x0 17.--19. "RSVDP_17,Reserved for future use." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 16. "FORCE_DETECT_LANE_EN,Force Detect Lane Enable. When this bit is set the controller ignores receiver detection from PHY during LTSSM Detect state and uses FORCE_DETECT_LANE. Note: This register field is sticky." "0,1" newline hexmask.long.word 0x0 0.--15. 1. "FORCE_DETECT_LANE,Force Detect Lane. When the FORCE_DETECT_LANE_EN field is set the controller ignores receiver detection from PHY during LTSSM Detect state and uses this value instead. - 0: Lane0 - 1: Lane1 - 2: Lane2 - .. - 15: Lane15 Note: This.." line.long 0x4 "SD_CONTROL2_REG,Silicon Debug Control 2. For more details. see the RAS DES section in the Core Operations chapter of the Databook." hexmask.long.word 0x4 17.--31. 1. "RSVDP_17,Reserved for future use." newline bitfld.long 0x4 16. "FRAMING_ERR_RECOVERY_DISABLE,Framing Error Recovery Disable. This bit disables a transition to Recovery state when a Framing Error is occurred. Note: This register field is sticky." "0,1" newline hexmask.long.byte 0x4 11.--15. 1. "RSVDP_11,Reserved for future use." newline bitfld.long 0x4 10. "DIRECT_LPBKSLV_TO_EXIT,Direct Loopback Slave To Exit. When this bit is set and the LTSSM is in Loopback Slave Active State the LTSSM transitions to Loopback Slave Exit state. Note: This register field is sticky." "0,1" newline bitfld.long 0x4 9. "DIRECT_POLCOMP_TO_DETECT,Direct Polling.Compliance to Detect. When this bit is set and the LTSSM is in Polling Compliance State the LTSSM transitions to Detect state. Note: This register field is sticky." "0,1" newline bitfld.long 0x4 8. "DIRECT_RECIDLE_TO_CONFIG,Direct Recovery.Idle to Configuration. When this bit is set and the LTSSM is in Recovery Idle State the LTSSM transitions to Configuration state. Note: This register field is sticky." "0,1" newline hexmask.long.byte 0x4 3.--7. 1. "RSVDP_3,Reserved for future use." newline bitfld.long 0x4 2. "NOACK_FORCE_LINKDOWN,Force LinkDown. When this bit is set and the controller detects REPLY_NUM rolling over 4 times the LTSSM transitions to Detect State. Note: This register field is sticky." "0,1" newline bitfld.long 0x4 1. "RECOVERY_REQUEST,Recovery Request. When this bit is set to '1' in L0 or L0s the LTSSM starts transitioning to Recovery State. This request does not cause a speed change or re-equalization." "0,1" newline bitfld.long 0x4 0. "HOLD_LTSSM,Hold and Release LTSSM. For as long as this register is '1' the controller stays in the current LTSSM. Note: This register field is sticky." "0,1" group.long (0xB0+0x30C)++0xB line.long 0x0 "SD_STATUS_L1LANE_REG,Silicon Debug Status(Layer1 Per-lane). This viewport register returns the data selected by the following field: - LANE_SELECT in SD_STATUS_L1LANE_REG For more details. see the RAS DES section in the Core Operations chapter of the.." hexmask.long.byte 0x0 24.--31. 1. "DESKEW_POINTER,Deskew Pointer. Indicates Deskew pointer of internal Deskew buffer of selected lane number(LANE_SELECT). Note: This register field is sticky." newline rbitfld.long 0x0 21.--23. "RSVDP_21,Reserved for future use." "0,1,2,3,4,5,6,7" newline rbitfld.long 0x0 20. "PIPE_TXELECIDLE,PIPE:TxElecIdle. Indicates PIPE TXELECIDLE signal of selected lane number(LANE_SELECT). Note: This register field is sticky." "0,1" newline rbitfld.long 0x0 19. "PIPE_RXELECIDLE,PIPE:RxElecIdle. Indicates PIPE RXELECIDLE signal of selected lane number(LANE_SELECT). Note: This register field is sticky." "0,1" newline rbitfld.long 0x0 18. "PIPE_RXVALID,PIPE:RxValid. Indicates PIPE RXVALID signal of selected lane number(LANE_SELECT). Note: This register field is sticky." "0,1" newline rbitfld.long 0x0 17. "PIPE_DETECT_LANE,PIPE:Detect Lane. Indicates whether PHY indicates receiver detection or not on selected lane number(LANE_SELECT). Note: This register field is sticky." "0,1" newline rbitfld.long 0x0 16. "PIPE_RXPOLARITY,PIPE:RxPolarity. Indicates PIPE RXPOLARITY signal of selected lane number(LANE_SELECT). Note: This register field is sticky." "0,1" newline hexmask.long.word 0x0 4.--15. 1. "RSVDP_4,Reserved for future use." newline hexmask.long.byte 0x0 0.--3. 1. "LANE_SELECT,Lane Select. Lane Select register for Silicon Debug Status Register of Layer1-PerLane. - 0x0: Lane0 - 0x1: Lane1 - 0x2: Lane2 - .. - 0xF: Lane15 Note: This register field is sticky." line.long 0x4 "SD_STATUS_L1LTSSM_REG,Silicon Debug Status(Layer1 LTSSM). For more details. see the RAS DES section in the Core Operations chapter of the Databook." hexmask.long.word 0x4 16.--31. 1. "LTSSM_VARIABLE,LTSSM Variable. Indicates internal LTSSM variables defined in the PCI Express Base Specification. C-PCIe Mode: - 0: directed_speed_change - 1: changed_speed_recovery - 2: successful_speed_negotiation - 3: upconfigure_capable; Set to '1' if.." newline rbitfld.long 0x4 15. "LANE_REVERSAL,Lane Reversal Operation. Receiver detected lane reversal. This field is only valid in the L0 LTSSM state. Note: This register field is sticky." "0,1" newline hexmask.long.byte 0x4 11.--14. 1. "RSVDP_11,Reserved for future use." newline rbitfld.long 0x4 8.--10. "PIPE_POWER_DOWN,PIPE:PowerDown. Indicates PIPE PowerDown signal. Note: This register field is sticky." "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 7. "FRAMING_ERR,Framing Error. Indicates Framing Error detection status." "0,1" newline hexmask.long.byte 0x4 0.--6. 1. "FRAMING_ERR_PTR,First Framing Error Pointer. Identifies the first Framing Error using the following encoding. The field contents are only valid value when FRAMING_ERR =1. Received Unexpected Framing Token - 01h: When non- STP/SDP/IDL Token was received.." line.long 0x8 "SD_STATUS_PM_REG,Silicon Debug Status(PM). For more details. see the RAS DES section in the Core Operations chapter of the Databook." hexmask.long.byte 0x8 24.--31. 1. "RSVDP_24,Reserved for future use." newline hexmask.long.byte 0x8 16.--23. 1. "LATCHED_NFTS,Latched N_FTS. Indicates the value of N_FTS in the received TS Ordered Sets from the Link Partner Note: This register field is sticky." newline rbitfld.long 0x8 13.--15. "L1SUB_STATE,L1Sub State. Indicates internal state machine of L1Sub state. - 0h: S_L1_U : idle state - 1h: S_L1_0 : wait for aux_clk_active - 2h: S_L1_0_WAIT4_ACK : wait for pclkack - 3h: S_L1_0_WAIT4_CLKREQ : wait for clkreq - 4h: S_L1_N_ENTRY : check.." "wait for aux_clk_active,?,?,?,?,?,?,?" newline bitfld.long 0x8 12. "PME_RESEND_FLAG,PME Re-send flag. When the DUT sends a PM_PME message TLP the DUT sets PME_Status bit. If host software does not clear PME_Status bit for 100ms(+50%/-5%) the DUT resends the PM_PME Message. This bit indicates that a PM_PME was resent." "0,1" newline hexmask.long.byte 0x8 8.--11. 1. "INTERNAL_PM_SSTATE,Internal PM State(Slave). Indicates internal state machine of Power Management Slave controller. - 0h: S_IDLE - 1h: S_RESPOND_NAK - 2h: S_BLOCK_TLP - 3h: S_WAIT_LAST_TLP_ACK - 4h: S_WAIT_EIDLE - 5h: S_LINK_ENTR_L1 - 6h: S_L1 - 7h:.." newline rbitfld.long 0x8 5.--7. "RSVDP_5,Reserved for future use." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x8 0.--4. 1. "INTERNAL_PM_MSTATE,Internal PM State(Master). Indicates internal state machine of Power Management Master controller. - 00h: IDLE - 01h: L0 - 02h: L0S - 03h: ENTER_L0S - 04h: L0S_EXIT - 05h: WAIT_PMCSR_CPL_SENT - 08h: L1 - 09h: L1_BLOCK_TLP - 0Ah:.." rgroup.long (0xBC+0x30C)++0x3 line.long 0x0 "SD_STATUS_L2_REG,Silicon Debug Status(Layer2). For more details. see the RAS DES section in the Core Operations chapter of the Databook." hexmask.long.byte 0x0 28.--31. 1. "RSVDP_28,Reserved for future use." newline bitfld.long 0x0 27. "FC_INIT2,FC_INIT2. Indicates the controller is in FC_INIT2(VC0) state. Note: This register field is sticky." "0,1" newline bitfld.long 0x0 26. "FC_INIT1,FC_INIT1. Indicates the controller is in FC_INIT1(VC0) state. Note: This register field is sticky." "0,1" newline bitfld.long 0x0 24.--25. "DLCMSM,DLCMSM. Indicates the current DLCMSM. - 00b: DL_INACTIVE - 01b: DL_FC_INIT - 11b: DL_ACTIVE Note: This register field is sticky." "0,1,2,3" newline hexmask.long.word 0x0 12.--23. 1. "RX_ACK_SEQ_NO,Tx Ack Sequence Number. Indicates ACKD_SEQ which is updated by receiving ACK/NAK DLLP. Note: This register field is sticky." newline hexmask.long.word 0x0 0.--11. 1. "TX_TLP_SEQ_NO,Tx Tlp Sequence Number. Indicates next transmit sequence number for transmit TLP. Note: This register field is sticky." group.long (0xC0+0x30C)++0x7 line.long 0x0 "SD_STATUS_L3FC_REG,Silicon Debug Status(Layer3 FC). The CREDIT_DATA[0/1] fields in this viewport register return the data for the VC and TLP Type selected by the following fields: - CREDIT_SEL_VC - CREDIT_SEL_CREDIT_TYPE - CREDIT_SEL_TLP_TYPE -.." hexmask.long.word 0x0 20.--31. 1. "CREDIT_DATA1,Credit Data1. Current FC credit data selected by the CREDIT_SEL_VC CREDIT_SEL_CREDIT_TYPE CREDIT_SEL_TLP_TYPE and CREDIT_SEL_HD viewport-select fields. - Rx: Credit Allocated Value - Tx: Credit Limit Value. This value is valid when.." newline hexmask.long.word 0x0 8.--19. 1. "CREDIT_DATA0,Credit Data0. Current FC credit data selected by the CREDIT_SEL_VC CREDIT_SEL_CREDIT_TYPE CREDIT_SEL_TLP_TYPE and CREDIT_SEL_HD viewport-select fields. - Rx: Credit Received Value - Tx: Credit Consumed Value Note: This register field is.." newline rbitfld.long 0x0 7. "RSVDP_7,Reserved for future use." "0,1" newline bitfld.long 0x0 6. "CREDIT_SEL_HD,Credit Select(HeaderData). This field in conjunction with the CREDIT_SEL_VC CREDIT_SEL_CREDIT_TYPE and CREDIT_SEL_TLP_TYPE viewport-select fields determines that data that is returned by the CREDIT_DATA0 and CREDIT_DATA1 data fields. -.." "Header Credit,Data Credit" newline bitfld.long 0x0 4.--5. "CREDIT_SEL_TLP_TYPE,Credit Select(TLP Type). This field in conjunction with the CREDIT_SEL_VC CREDIT_SEL_CREDIT_TYPE and CREDIT_SEL_HD viewport-select fields determines that data that is returned by the CREDIT_DATA0 and CREDIT_DATA1 data fields. - 0x0:.." "Posted,Non-Posted,Completion,?" newline bitfld.long 0x0 3. "CREDIT_SEL_CREDIT_TYPE,Credit Select(Credit Type). This field in conjunction with the CREDIT_SEL_VC CREDIT_SEL_TLP_TYPE and CREDIT_SEL_HD viewport-select fields determines that data that is returned by the CREDIT_DATA0 and CREDIT_DATA1 data fields. -.." "Rx,Tx" newline bitfld.long 0x0 0.--2. "CREDIT_SEL_VC,Credit Select(VC). This field in conjunction with the CREDIT_SEL_CREDIT_TYPE CREDIT_SEL_TLP_TYPE and CREDIT_SEL_HD viewport-select fields determines that data that is returned by the CREDIT_DATA0 and CREDIT_DATA1 data fields. - 0x0: VC0 -.." "VC0,VC1,VC2,?,?,?,?,VC7" line.long 0x4 "SD_STATUS_L3_REG,Silicon Debug Status(Layer3). For more details. see the RAS DES section in the Core Operations chapter of the Databook." hexmask.long.tbyte 0x4 8.--31. 1. "RSVDP_8,Reserved for future use." newline bitfld.long 0x4 7. "MFTLP_STATUS,Malformed TLP Status. Indicates malformed TLP has occurred." "0,1" newline hexmask.long.byte 0x4 0.--6. 1. "MFTLP_POINTER,First Malformed TLP Error Pointer. Indicates the element of the received first malformed TLP. This pointer is validated by MFTLP_STATUS. - 01h: AtomicOp address alignment - 02h: AtomicOp operand - 03h: AtomicOp byte enable - 04h: TLP length.." group.long (0xD0+0x30C)++0xB line.long 0x0 "SD_EQ_CONTROL1_REG,Silicon Debug EQ Control 1. This is a viewport control register. Setting the EQ_RATE_SEL and EQ_LANE_SEL fields in this register determine the per-lane Silicon Debug EQ Status data returned by the SD_EQ_STATUS[1/2/3] viewport.." hexmask.long.byte 0x0 24.--31. 1. "FOM_TARGET,FOM Target. Indicates figure of merit target criteria value of EQ Master(DSP in EQ Phase3/USP in EQ Phase2). This field is only valid when GEN3_EQ_FB_MODE is 0001b(Figure Of Merit). Note: This register field is sticky." newline bitfld.long 0x0 23. "FOM_TARGET_ENABLE,FOM Target Enable. Enables the FOM_TARGET fields. Note: This register field is sticky." "0,1" newline hexmask.long.byte 0x0 18.--22. 1. "RSVDP_18,Reserved for future use." newline bitfld.long 0x0 16.--17. "EVAL_INTERVAL_TIME,Eval Interval Time. Indicates interval time of RxEqEval assertion. - 00: 500ns - 01: 1us - 10: 2us - 11: 4us This field is used for EQ Master(DSP in EQ Phase3/USP in EQ Phase2). Note: This register field is sticky." "0,1,2,3" newline hexmask.long.byte 0x0 10.--15. 1. "RSVDP_10,Reserved for future use." newline bitfld.long 0x0 8.--9. "EXT_EQ_TIMEOUT,Extends EQ Phase2/3 Timeout. This field is used when the Ltssm is in Recovery.EQ2/3. When this field is set the value of EQ2/3 timeout is extended. EQ Master(DSP in EQ Phase3/USP in EQ Phase2). - 00: 24ms (default) - 01: 48ms (x2) - 10:.." "0,1,2,3" newline rbitfld.long 0x0 6.--7. "RSVDP_6,Reserved for future use." "0,1,2,3" newline bitfld.long 0x0 4.--5. "EQ_RATE_SEL,EQ Status Rate Select. Setting this field in conjunction with the EQ_LANE_SEL field determines the per-lane Silicon Debug EQ Status data returned by the SD_EQ_CONTROL[2/3] and SD_EQ_STATUS[1/2/3] viewport registers. - 0x0: 8.0GT/s Speed.." "0,1,2,3" newline hexmask.long.byte 0x0 0.--3. 1. "EQ_LANE_SEL,EQ Status Lane Select. Setting this field in conjunction with the EQ_RATE_SEL field determines the per-lane Silicon Debug EQ Status data returned by the SD_EQ_CONTROL[2/3] and SD_EQ_STATUS[1/2/3] viewport registers. - 0x0: Lane0 - 0x1: Lane1.." line.long 0x4 "SD_EQ_CONTROL2_REG,Silicon Debug EQ Control 2. This viewport register returns the value for the rate and lane selected by the EQ_RATE_SEL and EQ_LANE_SEL fields in the SD_EQ_CONTROL1_REG register. For more details. see the RAS DES section in the Core.." rbitfld.long 0x4 31. "RSVDP_31,Reserved for future use." "0,1" newline bitfld.long 0x4 30. "FORCE_LOCAL_TX_PRESET_ENABLE,Force Local Transmitter Preset Enable. Enables the FORCE_LOCAL_TX_PRESET field. If select rate in the EQ_RATE_SEL field is 32.0GT/s Speed this feature is not available. Note: This register field is sticky." "0,1" newline bitfld.long 0x4 29. "FORCE_LOCAL_RX_HINT_ENABLE,Force Local Receiver Preset Hint Enable. Enables the FORCE_LOCAL_RX_HINT field. If select rate in the EQ_RATE_SEL field is other than 8.0GT/s Speed this feature is not available. Note: This register field is sticky." "0,1" newline bitfld.long 0x4 28. "FORCE_LOCAL_TX_COEF_ENABLE,Force Local Transmitter Coefficient Enable. Enables the following fields: - FORCE_LOCAL_TX_PRE_CURSOR - FORCE_LOCAL_TX_CURSOR - FORCE_LOCAL_TX_POST_CURSOR Note: This register field is sticky." "0,1" newline hexmask.long.byte 0x4 24.--27. 1. "FORCE_LOCAL_TX_PRESET,Force Local Transmitter Preset. Indicates initial preset value of USP in EQ Slave(EQ Phase2) instead of receiving EQ TS2. If select rate in the EQ_RATE_SEL field is 32.0GT/s Speed this feature is not available. Note: This register.." newline rbitfld.long 0x4 21.--23. "RSVDP_21,Reserved for future use." "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 18.--20. "FORCE_LOCAL_RX_HINT,Force Local Receiver Preset Hint. Indicates the RxPresetHint value of EQ Slave(DSP in EQ Phase2/USP in EQ Phase3) instead of received or set value. If select rate in the EQ_RATE_SEL field is other than 8.0GT/s Speed this feature is.." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x4 12.--17. 1. "FORCE_LOCAL_TX_POST_CURSOR,Force Local Transmitter Post-Cursor. Indicates the coefficient value of EQ Slave(DSP in EQ Phase2/USP in EQ Phase3) instead of the value instructed from link partner. Note: This register field is sticky." newline hexmask.long.byte 0x4 6.--11. 1. "FORCE_LOCAL_TX_CURSOR,Force Local Transmitter Cursor. Indicates the coefficient value of EQ Slave(DSP in EQ Phase2/USP in EQ Phase3) instead of the value instructed from link partner. Note: This register field is sticky." newline hexmask.long.byte 0x4 0.--5. 1. "FORCE_LOCAL_TX_PRE_CURSOR,Force Local Transmitter Pre-cursor. Indicates the coefficient value of EQ Slave(DSP in EQ Phase2/USP in EQ Phase3) instead of the value instructed from link partner. Note: This register field is sticky." line.long 0x8 "SD_EQ_CONTROL3_REG,Silicon Debug EQ Control 3. This viewport register returns the value for the rate and lane selected by the EQ_RATE_SEL and EQ_LANE_SEL fields in the SD_EQ_CONTROL1_REG register. For more details. see the RAS DES section in the Core.." rbitfld.long 0x8 29.--31. "RSVDP_29,Reserved for future use." "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 28. "FORCE_REMOTE_TX_COEF_ENABLE,Force Remote Transmitter Coefficient Enable. Enables the following fields: - FORCE_REMOTE_TX_PRE_CURSOR - FORCE_REMOTE_TX_CURSOR - FORCE_REMOTE_TX_POST_CURSOR This function can only be used when GEN3_EQ_FB_MODE =.." "0,1" newline hexmask.long.word 0x8 18.--27. 1. "RSVDP_18,Reserved for future use." newline hexmask.long.byte 0x8 12.--17. 1. "FORCE_REMOTE_TX_POST_CURSOR,Force Remote Transmitter Post-Cursor. Indicates the coefficient value of EQ Master(DSP in EQ Phase3/USP in EQ Phase2) instead of the value instructed from local phy in dirchange mode. Note: This register field is sticky." newline hexmask.long.byte 0x8 6.--11. 1. "FORCE_REMOTE_TX_CURSOR,Force Remote Transmitter Cursor. Indicates the coefficient value of EQ Master(DSP in EQ Phase3/USP in EQ Phase2) instead of the value instructed from local phy in dirchange mode. Note: This register field is sticky." newline hexmask.long.byte 0x8 0.--5. 1. "FORCE_REMOTE_TX_PRE_CURSOR,Force Remote Transmitter Pre-Cursor. Indicates the coefficient value of EQ Master(DSP in EQ Phase3/USP in EQ Phase2) instead of the value instructed from local phy in dirchange mode. Note: This register field is sticky." rgroup.long (0xE0+0x30C)++0xB line.long 0x0 "SD_EQ_STATUS1_REG,Silicon Debug EQ Status 1. This viewport register returns the first of three words of Silicon Debug EQ Status data for the rate and lane selected by the EQ_RATE_SEL and EQ_LANE_SEL fields in the SD_EQ_CONTROL1_REG register. The.." hexmask.long.tbyte 0x0 8.--31. 1. "RSVDP_8,Reserved for future use." newline bitfld.long 0x0 7. "EQ_REJECT_EVENT,EQ Reject Event. Indicates that the controller receives two consecutive TS1 OS w/Reject=1b during EQ Master phase(DSP in EQ Phase3/USP in EQ Phase2). This bit is automatically cleared when the controller starts EQ Master phase again." "0,1" newline bitfld.long 0x0 6. "EQ_RULEC_VIOLATION,EQ Rule C Violation. Indicates that coefficients rule C violation is detected in the values provided by PHY using direction change method during EQ Master phase(DSP in EQ Phase3/USP in EQ Phase2). The coefficients rule C correspond to.." "0,1" newline bitfld.long 0x0 5. "EQ_RULEB_VIOLATION,EQ Rule B Violation. Indicates that coefficients rule B violation is detected in the values provided by PHY using direction change method during EQ Master phase(DSP in EQ Phase3/USP in EQ Phase2). The coefficients rules B correspond to.." "0,1" newline bitfld.long 0x0 4. "EQ_RULEA_VIOLATION,EQ Rule A Violation. Indicates that coefficients rule A violation is detected in the values provided by PHY using direction change method during EQ Master phase(DSP in EQ Phase3/USP in EQ Phase2). The coefficients rules A correspond to.." "0,1" newline bitfld.long 0x0 3. "RSVDP_3,Reserved for future use." "0,1" newline bitfld.long 0x0 1.--2. "EQ_CONVERGENCE_INFO,EQ Convergence Info. Indicates equalization convergence information. - 0x0: Equalization is not attempted - 0x1: Equalization finished successfully - 0x2: Equalization finished unsuccessfully - 0x3: Reserved This bit is automatically.." "Equalization is not attempted,Equalization finished successfully,Equalization finished unsuccessfully,Reserved" newline bitfld.long 0x0 0. "EQ_SEQUENCE,EQ Sequence. Indicates that the controller is starting the equalization sequence. Note: This register field is sticky." "0,1" line.long 0x4 "SD_EQ_STATUS2_REG,Silicon Debug EQ Status 2. This viewport register returns the second of three words of Silicon Debug EQ Status data for the rate and lane selected by the EQ_RATE_SEL and EQ_LANE_SEL fields in the SD_EQ_CONTROL1_REG register. Each field.." hexmask.long.byte 0x4 24.--31. 1. "EQ_LOCAL_FOM_VALUE,EQ Local Figure of Merit. Indicates Local maximum Figure of Merit value. Note: This register field is sticky." newline bitfld.long 0x4 21.--23. "RSVDP_21,Reserved for future use." "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 18.--20. "EQ_LOCAL_RX_HINT,EQ Local Receiver Preset Hint. Indicates Local Receiver Preset Hint value. If select rate in the EQ_RATE_SEL field is other than 8.0GT/s Speed this feature is not available. Note: This register field is sticky." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x4 12.--17. 1. "EQ_LOCAL_POST_CURSOR,EQ Local Post-Cursor. Indicates Local post cursor coefficient value. Note: This register field is sticky." newline hexmask.long.byte 0x4 6.--11. 1. "EQ_LOCAL_CURSOR,EQ Local Cursor. Indicates Local cursor coefficient value. Note: This register field is sticky." newline hexmask.long.byte 0x4 0.--5. 1. "EQ_LOCAL_PRE_CURSOR,EQ Local Pre-Cursor. Indicates Local pre cursor coefficient value. Note: This register field is sticky." line.long 0x8 "SD_EQ_STATUS3_REG,Silicon Debug EQ Status 3. This viewport register returns the third of three words of Silicon Debug EQ Status data for the rate and lane selected by the EQ_RATE_SEL and EQ_LANE_SEL fields in the SD_EQ_CONTROL1_REG register. Each field.." bitfld.long 0x8 30.--31. "RSVDP_30,Reserved for future use." "0,1,2,3" newline hexmask.long.byte 0x8 24.--29. 1. "EQ_REMOTE_FS,EQ Remote FS. Indicates Remote FS value. Note: This register field is sticky." newline hexmask.long.byte 0x8 18.--23. 1. "EQ_REMOTE_LF,EQ Remote LF. Indicates Remote LF value. Note: This register field is sticky." newline hexmask.long.byte 0x8 12.--17. 1. "EQ_REMOTE_POST_CURSOR,EQ Remote Post-Cursor. Indicates Remote post cursor coefficient value. Note: This register field is sticky." newline hexmask.long.byte 0x8 6.--11. 1. "EQ_REMOTE_CURSOR,EQ Remote Cursor. Indicates Remote cursor coefficient value. Note: This register field is sticky." newline hexmask.long.byte 0x8 0.--5. 1. "EQ_REMOTE_PRE_CURSOR,EQ Remote Pre-Cursor. Indicates Remote pre cursor coefficient value. Note: This register field is sticky." tree.end tree "PF0_SN_CAP (Device Serial Number Capability Structure)" group.long (0x0+0x170)++0xB line.long 0x0 "SN_BASE,Device Serial Number Extended Capability Header. For a description of this standard PCIe register. see the PCI Express Base Specification." hexmask.long.word 0x0 20.--31. 1. "SN_NEXT_OFFSET,Next Capability Offset. For a description of this standard PCIe register field see the PCI Express Base Specification. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then.." hexmask.long.byte 0x0 16.--19. 1. "SN_CAP_VERSION,Capability Version. For a description of this standard PCIe register field see the PCI Express Base Specification. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky).." hexmask.long.word 0x0 0.--15. 1. "SN_PCIE_EXTENDED_CAP_ID,Serial Number Extended Capability ID. For a description of this standard PCIe register field see the PCI Express Base Specification. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if.." line.long 0x4 "SER_NUM_REG_DW_1,Serial Number 1 Register. For a description of this standard PCIe register. see the PCI Express Base Specification." hexmask.long 0x4 0.--31. 1. "SN_SER_NUM_REG_1_DW,IEEE 64 bit Device Serial Number (DW 1). For a description of this standard PCIe register field see the PCI Express Base Specification. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if.." line.long 0x8 "SER_NUM_REG_DW_2,Serial Number 2 Register. For a description of this standard PCIe register. see the PCI Express Base Specification." hexmask.long 0x8 0.--31. 1. "SN_SER_NUM_REG_2_DW,IEEE 64 bit Device Serial Number (DW 2). For a description of this standard PCIe register field see the PCI Express Base Specification. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if.." tree.end tree "PF0_VSECRAS_CAP (PF RAS Datapath Protection Capability Structure (VSEC))" group.long (0x0+0x480)++0x3 line.long 0x0 "RASDP_EXT_CAP_HDR_OFF,PCIe Extended capability ID. Capability version and Next capability offset. For a description of this standard PCIe register. see the PCI Express Specification." hexmask.long.word 0x0 20.--31. 1. "NEXT_OFFSET,Next Capability Offset. For a description of this standard PCIe register see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else.." newline hexmask.long.byte 0x0 16.--19. 1. "CAP,Capability Version. For a description of this standard PCIe register see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note:.." newline hexmask.long.word 0x0 0.--15. 1. "ID,PCI Express Extended Capability ID. For a description of this standard PCIe register see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else.." rgroup.long (0x4+0x480)++0x3 line.long 0x0 "RASDP_VENDOR_SPECIFIC_HDR_OFF,Vendor Specific Header. For a description of this standard PCIe register. see the PCI Express Specification." hexmask.long.word 0x0 20.--31. 1. "VSEC_LENGTH,VSEC Length. For a description of this standard PCIe register see the PCI Express Specification. Note: This register field is sticky." newline hexmask.long.byte 0x0 16.--19. 1. "VSEC_REV,VSEC Rev. For a description of this standard PCIe register see the PCI Express Specification. Note: This register field is sticky." newline hexmask.long.word 0x0 0.--15. 1. "VSEC_ID,VSEC ID. For a description of this standard PCIe register see the PCI Express Specification. Note: This register field is sticky." group.long (0x8+0x480)++0x7 line.long 0x0 "RASDP_ERROR_PROT_CTRL_OFF,ECC error correction control. Allows you to disable ECC error correction for RAMs and datapath. When the AXI Bridge Module is implemented and the master / slave clocks are asynchronous to the PCIe native controller clock.." hexmask.long.byte 0x0 24.--31. 1. "RSVDP_24,Reserved for future use." newline bitfld.long 0x0 23. "ERROR_PROT_DISABLE_CXS_RX,Error correction disable for CXS Tx path (PCIe Rx path). Note: This register field is sticky." "0,1" newline bitfld.long 0x0 22. "ERROR_PROT_DISABLE_ADM_RX,Error correction disable for ADM Rx path. Note: This register field is sticky." "0,1" newline bitfld.long 0x0 21. "ERROR_PROT_DISABLE_LAYER3_RX,Error correction disable for layer 3 Rx path. Note: This register field is sticky." "0,1" newline bitfld.long 0x0 20. "ERROR_PROT_DISABLE_LAYER2_RX,Error correction disable for layer 2 Rx path. Note: This register field is sticky." "0,1" newline bitfld.long 0x0 19. "ERROR_PROT_DISABLE_DMA_READ,Error correction disable for DMA read engine. Note: This register field is sticky." "0,1" newline bitfld.long 0x0 18. "ERROR_PROT_DISABLE_AXI_BRIDGE_INBOUND_REQUEST,Error correction disable for AXI bridge inbound request path. Note: This register field is sticky." "0,1" newline bitfld.long 0x0 17. "ERROR_PROT_DISABLE_AXI_BRIDGE_INBOUND_COMPLETION,Error correction disable for AXI bridge inbound completion composer. Does not disable the error detection reporting for 1-bit and 2-bit ECC errors. Note: This register field is sticky." "?,bit and 2-bit ECC errors" newline bitfld.long 0x0 16. "ERROR_PROT_DISABLE_RX,Global error correction disable for all Rx layers. Note: This register field is sticky." "0,1" newline hexmask.long.byte 0x0 9.--15. 1. "RSVDP_9,Reserved for future use." newline bitfld.long 0x0 8. "ERROR_PROT_DISABLE_DTIM_TX,Error correction disable for DTIM Tx path. Note: This register field is sticky." "0,1" newline bitfld.long 0x0 7. "ERROR_PROT_DISABLE_CXS_TX,Error correction disable for CXS Rx path (PCIe Tx path). Note: This register field is sticky." "0,1" newline bitfld.long 0x0 6. "ERROR_PROT_DISABLE_ADM_TX,Error correction disable for Adm Tx path. Note: This register field is sticky." "0,1" newline bitfld.long 0x0 5. "ERROR_PROT_DISABLE_LAYER3_TX,Error correction disable for layer 3 Tx path. Note: This register field is sticky." "0,1" newline bitfld.long 0x0 4. "ERROR_PROT_DISABLE_LAYER2_TX,Error correction disable for layer 2 Tx path. Note: This register field is sticky." "0,1" newline bitfld.long 0x0 3. "ERROR_PROT_DISABLE_DMA_WRITE,Error correction disable for DMA write engine. Note: This register field is sticky." "0,1" newline bitfld.long 0x0 2. "ERROR_PROT_DISABLE_AXI_BRIDGE_OUTBOUND,Error correction disable for AXI bridge outbound request path. Note: This register field is sticky." "0,1" newline bitfld.long 0x0 1. "ERROR_PROT_DISABLE_AXI_BRIDGE_MASTER,Error correction disable for AXI bridge master completion buffer. Note: This register field is sticky." "0,1" newline bitfld.long 0x0 0. "ERROR_PROT_DISABLE_TX,Global error correction disable for all Tx layers. Does not disable the error detection reporting for 1-bit and 2-bit ECC errors. Note: This register field is sticky." "?,bit and 2-bit ECC errors" line.long 0x4 "RASDP_CORR_COUNTER_CTRL_OFF,Corrected error (1-bit ECC) counter selection and control. This is a viewport control register. Setting the CORR_COUNTER_SELECTION_REGION and CORR_COUNTER_SELECTION fields in this register determine the counter data returned.." hexmask.long.byte 0x4 24.--31. 1. "CORR_COUNTER_SELECTION,Counter selection. This field selects the counter ID (within the region defined by CORR_COUNTER_SELECTION_REGION) whose contents can be read from the RASDP_CORR_COUNT_REPORT_OFF register. You can cycle this field value from 0 to.." newline hexmask.long.byte 0x4 20.--23. 1. "CORR_COUNTER_SELECTION_REGION,Select correctable counter region: - 0x0: Region select for Adm Rx path - 0x1: Region select for layer 3 Rx path - 0x2: Region select for layer 2 Rx path - 0x3: Region select for DMA inbound path - 0x4: Region select for AXI.." newline hexmask.long.word 0x4 5.--19. 1. "RSVDP_5,Reserved for future use." newline bitfld.long 0x4 4. "CORR_EN_COUNTERS,Enable correctable errors counters. - 1: counters increment when the controller detects a correctable error - 0: counters are frozen The counters are enabled by default." "counters are frozen,counters increment when the controller detects a.." newline rbitfld.long 0x4 1.--3. "RSVDP_1,Reserved for future use." "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 0. "CORR_CLEAR_COUNTERS,Clear all correctable error counters." "0,1" rgroup.long (0x10+0x480)++0x3 line.long 0x0 "RASDP_CORR_COUNT_REPORT_OFF,Corrected error (1-bit ECC) counter data. This viewport register returns the counter data selected by the CORR_COUNTER_SELECTION_REGION and CORR_COUNTER_SELECTION fields in the RASDP_CORR_COUNTER_CTRL_OFF register." hexmask.long.byte 0x0 24.--31. 1. "CORR_COUNTER_SELECTED,Counter selection. Returns the value set in the CORR_COUNTER_SELECTION field of the RASDP_CORR_COUNTER_CTRL_OFF register." newline hexmask.long.byte 0x0 20.--23. 1. "CORR_COUNTER_SELECTED_REGION,Selected correctable counter region: - 0x0: Region select for Adm Rx path - 0x1: Region select for layer 3 Rx path - 0x2: Region select for layer 2 Rx path - 0x3: Region select for DMA inbound path - 0x4: Region select for.." newline hexmask.long.word 0x0 8.--19. 1. "RSVDP_8,Reserved for future use." newline hexmask.long.byte 0x0 0.--7. 1. "CORR_COUNTER,Current corrected error count for the selected counter." group.long (0x14+0x480)++0x3 line.long 0x0 "RASDP_UNCORR_COUNTER_CTRL_OFF,Uncorrected error (2-bit ECC and parity) counter selection and control. This is a viewport control register. Setting the UNCORR_COUNTER_SELECTION_REGION and UNCORR_COUNTER_SELECTION fields in this register determine the.." hexmask.long.byte 0x0 24.--31. 1. "UNCORR_COUNTER_SELECTION,Counter selection. This field selects the counter ID (within the region defined by UNCORR_COUNTER_SELECTION_REGION) whose contents can be read from the RASDP_UNCORR_COUNT_REPORT_OFF register. You can cycle this field value from 0.." newline hexmask.long.byte 0x0 20.--23. 1. "UNCORR_COUNTER_SELECTION_REGION,Select uncorrectable counter region: - 0x0: Region select for Adm Rx path - 0x1: Region select for layer 3 Rx path - 0x2: Region select for layer 2 Rx path - 0x3: Region select for DMA inbound path - 0x4: Region select for.." newline hexmask.long.word 0x0 5.--19. 1. "RSVDP_5,Reserved for future use." newline bitfld.long 0x0 4. "UNCORR_EN_COUNTERS,Enable uncorrectable errors counters. - 1: enables the counters to increment on detected correctable errors - 0: counters are frozen The counters are enabled by default." "counters are frozen,enables the counters to increment on detected.." newline rbitfld.long 0x0 1.--3. "RSVDP_1,Reserved for future use." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 0. "UNCORR_CLEAR_COUNTERS,Clear uncorrectable errors counters. When asserted causes all counters tracking the uncorrectable errors to be cleared." "0,1" rgroup.long (0x18+0x480)++0x3 line.long 0x0 "RASDP_UNCORR_COUNT_REPORT_OFF,Uncorrected error (2-bit ECC and parity) counter data. This viewport register returns the counter data selected by the UNCORR_COUNTER_SELECTION_REGION and UNCORR_COUNTER_SELECTION fields in the RASDP_UNCORR_COUNTER_CTRL_OFF.." hexmask.long.byte 0x0 24.--31. 1. "UNCORR_COUNTER_SELECTED,Counter selection. Returns the value set in the UNCORR_COUNTER_SELECTION field of the RASDP_UNCORR_COUNTER_CTRL_OFF register." newline hexmask.long.byte 0x0 20.--23. 1. "UNCORR_COUNTER_SELECTED_REGION,Selected uncorrectable counter region: - 0x0: Region select for Adm Rx path - 0x1: Region select for layer 3 Rx path - 0x2: Region select for layer 2 Rx path - 0x3: Region select for DMA inbound path - 0x4: Region select.." newline hexmask.long.word 0x0 8.--19. 1. "RSVDP_8,Reserved for future use." newline hexmask.long.byte 0x0 0.--7. 1. "UNCORR_COUNTER,Current uncorrected error count for the selected counter" group.long (0x1C+0x480)++0x3 line.long 0x0 "RASDP_ERROR_INJ_CTRL_OFF,Error injection control for the following features: - 1-bit or 2-bit injection - Continuous or fixed-number (n) injection modes - Global enable/disable - Selectable location where injection occurs" hexmask.long.byte 0x0 24.--31. 1. "RSVDP_24,Reserved for future use." newline hexmask.long.byte 0x0 16.--23. 1. "ERROR_INJ_LOC,Error injection location. Selects where error injection takes place. You can cycle this field value from 0 to 255 to access all locations according to the detailed report of check points at.." newline hexmask.long.byte 0x0 8.--15. 1. "ERROR_INJ_COUNT,Error injection count. - 0: errors are inserted in every TLP until you clear ERROR_INJ_EN. - 1: one errors injected - 2: two errors injected - n: amount of errors injected" newline rbitfld.long 0x0 6.--7. "RSVDP_6,Reserved for future use." "0,1,2,3" newline bitfld.long 0x0 4.--5. "ERROR_INJ_TYPE,Error injection type: - 0: none - 1: 1-bit - 2: 2-bit" "none,bit,bit,?" newline rbitfld.long 0x0 1.--3. "RSVDP_1,Reserved for future use." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 0. "ERROR_INJ_EN,Error injection global enable. When set enables the error insertion logic." "0,1" rgroup.long (0x20+0x480)++0x7 line.long 0x0 "RASDP_CORR_ERROR_LOCATION_OFF,Corrected errors locations. For more details. see the RAS Data Protection (DP) section in the Core Operations chapter of the Databook." hexmask.long.byte 0x0 24.--31. 1. "LOC_LAST_CORR_ERROR,Location/ID of the last corrected error within the region defined by REG_LAST_CORR_ERROR. You can cycle this field value from 0 to 255 to access all counters according to the detailed report of check points at.." newline hexmask.long.byte 0x0 20.--23. 1. "REG_LAST_CORR_ERROR,Region of the last corrected error: - 0x0: Region select for Adm Rx path - 0x1: Region select for layer 3 Rx path - 0x2: Region select for layer 2 Rx path - 0x3: Region select for DMA inbound path - 0x4: Region select for AXI bridge.." newline hexmask.long.byte 0x0 16.--19. 1. "RSVDP_16,Reserved for future use." newline hexmask.long.byte 0x0 8.--15. 1. "LOC_FIRST_CORR_ERROR,Location/ID of the first corrected error within the region defined by REG_FIRST_CORR_ERROR. You can cycle this field value from 0 to 255 to access all counters according to the detailed report of check points at.." newline hexmask.long.byte 0x0 4.--7. 1. "REG_FIRST_CORR_ERROR,Region of the first corrected error: - 0x0: Region select for Adm Rx path - 0x1: Region select for layer 3 Rx path - 0x2: Region select for layer 2 Rx path - 0x3: Region select for DMA inbound path - 0x4: Region select for AXI bridge.." newline hexmask.long.byte 0x0 0.--3. 1. "RSVDP_0,Reserved for future use." line.long 0x4 "RASDP_UNCORR_ERROR_LOCATION_OFF,Uncorrected errors locations. For more details. see the RAS Data Protection (DP) section in the Core Operations chapter of the Databook." hexmask.long.byte 0x4 24.--31. 1. "LOC_LAST_UNCORR_ERROR,Location/ID of the last uncorrected error within the region defined by REG_LAST_UNCORR_ERROR. You can cycle this field value from 0 to 255 to access all counters according to the detailed report of check points at.." newline hexmask.long.byte 0x4 20.--23. 1. "REG_LAST_UNCORR_ERROR,Region of the last uncorrected error: - 0x0: Region select for Adm Rx path - 0x1: Region select for layer 3 Rx path - 0x2: Region select for layer 2 Rx path - 0x3: Region select for DMA inbound path - 0x4: Region select for AXI.." newline hexmask.long.byte 0x4 16.--19. 1. "RSVDP_16,Reserved for future use." newline hexmask.long.byte 0x4 8.--15. 1. "LOC_FIRST_UNCORR_ERROR,Location/ID of the first uncorrected error within the region defined by REG_FIRST_UNCORR_ERROR. You can cycle this field value from 0 to 255 to access all counters according to the detailed report of check points at.." newline hexmask.long.byte 0x4 4.--7. 1. "REG_FIRST_UNCORR_ERROR,Region of the first uncorrected error: - 0x0: Region select for Adm Rx path - 0x1: Region select for layer 3 Rx path - 0x2: Region select for layer 2 Rx path - 0x3: Region select for DMA inbound path - 0x4: Region select for AXI.." newline hexmask.long.byte 0x4 0.--3. 1. "RSVDP_0,Reserved for future use." group.long (0x28+0x480)++0x7 line.long 0x0 "RASDP_ERROR_MODE_EN_OFF,RASDP error mode enable. The controller enters RASDP error mode (if ERROR_MODE_EN =1) upon detection of the first uncorrectable error. During this mode: - Rx TLPs that are forwarded to your application are not guaranteed to be.." hexmask.long 0x0 2.--31. 1. "RSVDP_2,Reserved for future use." newline bitfld.long 0x0 1. "AUTO_LINK_DOWN_EN,Write '1' to enable the controller to bring the link down when the controller enters RASDP error mode. Note: This register field is sticky." "0,1" newline bitfld.long 0x0 0. "ERROR_MODE_EN,Write '1' to enable the controller enter RASDP error mode when it detects an uncorrectable error. Note: This register field is sticky." "0,1" line.long 0x4 "RASDP_ERROR_MODE_CLEAR_OFF,Exit RASDP error mode. For more details. see the RAS Data Protection (DP) section in the Core Operations chapter of the Databook." hexmask.long 0x4 1.--31. 1. "RSVDP_1,Reserved for future use." newline bitfld.long 0x4 0. "ERROR_MODE_CLEAR,Write '1' to take the controller out of RASDP error mode. The controller will then report uncorrectable errors (through AER internal error reporting) and also stop nullifying/discarding TLPs." "0,1" rgroup.long (0x30+0x480)++0x7 line.long 0x0 "RASDP_RAM_ADDR_CORR_ERROR_OFF,RAM Address where a corrected error (1-bit ECC) has been detected. For more details. see the RAS Data Protection (DP) section in the Core Operations chapter of the Databook." hexmask.long.byte 0x0 28.--31. 1. "RAM_INDEX_CORR_ERROR,RAM index where a corrected error (1-bit ECC) has been detected." newline bitfld.long 0x0 27. "RSVDP_27,Reserved for future use." "0,1" newline hexmask.long 0x0 0.--26. 1. "RAM_ADDR_CORR_ERROR,RAM Address where a corrected error (1-bit ECC) has been detected." line.long 0x4 "RASDP_RAM_ADDR_UNCORR_ERROR_OFF,RAM Address where an uncorrected error (2-bit ECC) has been detected. For more details. see the RAS Data Protection (DP) section in the Core Operations chapter of the Databook." hexmask.long.byte 0x4 28.--31. 1. "RAM_INDEX_UNCORR_ERROR,RAM index where an uncorrected error (2-bit ECC) has been detected." newline bitfld.long 0x4 27. "RSVDP_27,Reserved for future use." "0,1" newline hexmask.long 0x4 0.--26. 1. "RAM_ADDR_UNCORR_ERROR,RAM Address where an uncorrected error (2-bit ECC) has been detected." tree.end tree "PF0_RTR_CAP (PF RTR Capability Structure)" group.long (0x0+0x2F8)++0xB line.long 0x0 "RTR_EXT_CAP_HDR_OFF,Readiness Time Reporting PCI Express Extended Capability Header. For a description of this standard PCIe register. see the PCI Express Specification." hexmask.long.word 0x0 20.--31. 1. "RTR_NEXT_OFFSET,Next Capability Offset. For a description of this standard PCIe register field see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky).." hexmask.long.byte 0x0 16.--19. 1. "RTR_CAP_VERSION,Capability Version. For a description of this standard PCIe register field see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky).." hexmask.long.word 0x0 0.--15. 1. "RTR_EXT_CAP_ID,PCI Express Extended Capability ID. For a description of this standard PCIe register field see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then.." line.long 0x4 "READI_TIME_REPORTING1_OFF,Readiness Time Reporting 1. For a description of this standard PCIe register. see the PCI Express Specification." bitfld.long 0x4 31. "RTR_TIME_VALID,Valid. For a description of this standard PCIe register field see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky)" "0,1" hexmask.long.byte 0x4 24.--30. 1. "RSVDP_24,Reserved for future use." hexmask.long.word 0x4 12.--23. 1. "DL_UP_TIME,DL_UP Time. For a description of this standard PCIe register field see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky)" hexmask.long.word 0x4 0.--11. 1. "RESET_TIME,Reset Time. For a description of this standard PCIe register field see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky)" line.long 0x8 "READI_TIME_REPORTING2_OFF,Readiness Time Reporting 2. For a description of this standard PCIe register. see the PCI Express Specification." hexmask.long.byte 0x8 24.--31. 1. "RSVDP_24,Reserved for future use." hexmask.long.word 0x8 12.--23. 1. "D3HOT_D0_TIME,D3hot to D0 Time. For a description of this standard PCIe register field see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else.." hexmask.long.word 0x8 0.--11. 1. "FLR_TIME,FLR Time. For a description of this standard PCIe register field see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky)" tree.end tree "PF0_RTR_CAP_DBI2 (DBI2 Shadow Block: PF RTR Capability Structure)" rgroup.long (0x4+0x12F8)++0x7 line.long 0x0 "SHADOW_READI_TIME_REPORTING1_OFF,Shadow Register Readiness Time Reporting 1. For a description of this standard PCIe register. see the PCI Express Specification." bitfld.long 0x0 31. "RTR_TIME_VALID,Shadow Valid in the shadow register. For a description of this standard PCIe register field see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access - Dbi: No access - Dbi2: if.." "0,1" hexmask.long.tbyte 0x0 12.--30. 1. "RSVDP_12,Reserved for future use." hexmask.long.word 0x0 0.--11. 1. "RESET_TIME,Shadow Reset Time in the shadow register. For a description of this standard PCIe register field see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access - Dbi: No access - Dbi2: if.." line.long 0x4 "SHADOW_READI_TIME_REPORTING2_OFF,Shadow Register Readiness Time Reporting 2. For a description of this standard PCIe register. see the PCI Express Specification." hexmask.long.byte 0x4 24.--31. 1. "RSVDP_24,Reserved for future use." hexmask.long.word 0x4 12.--23. 1. "D3HOT_D0_TIME,Shadow D3hot to D0 Time in the shadow register. For a description of this standard PCIe register field see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access - Dbi: No access - Dbi2:.." hexmask.long.word 0x4 0.--11. 1. "FLR_TIME,Shadow FLR Time in the shadow register. For a description of this standard PCIe register field see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access - Dbi: No access - Dbi2: if.." tree.end tree "PF0_FRSQ_CAP (PF FRSQ Capability Structure)" group.long (0x0+0x2E8)++0xB line.long 0x0 "FRSQ_EXT_CAP_HDR_OFF,FRS Queuing Extended Capability Header. For a description of this standard PCIe register. see the PCI Express Specification." hexmask.long.word 0x0 20.--31. 1. "FRSQ_NEXT_OFFSET,Next Capability Offset. For a description of this standard PCIe register field see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then.." hexmask.long.byte 0x0 16.--19. 1. "FRSQ_CAP_VERSION,Capability Version. For a description of this standard PCIe register field see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky).." hexmask.long.word 0x0 0.--15. 1. "FRSQ_EXT_CAP_ID,PCI Express Extended Capability ID. For a description of this standard PCIe register field see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then.." line.long 0x4 "FRSQ_CAP_OFF,FRS Queuing Capability Register. For a description of this standard PCIe register. see the PCI Express Specification." hexmask.long.word 0x4 21.--31. 1. "RSVDP_21,Reserved for future use." hexmask.long.byte 0x4 16.--20. 1. "FRS_INT_MESSAGE_NUMBER,FRS Interrupt Message Number. For a description of this standard PCIe register field see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1).." hexmask.long.byte 0x4 12.--15. 1. "RSVDP_12,Reserved for future use." hexmask.long.word 0x4 0.--11. 1. "FRSQ_MAX_DEPTH,FRS Queue Max Depth. For a description of this standard PCIe register field see the PCI Express Specification." line.long 0x8 "FRSQ_CONTROL_FRSQ_STATUS_OFF,FRS Queuing Status and Control Register. For a description of this standard PCIe register. see the PCI Express Specification." hexmask.long.word 0x8 17.--31. 1. "RSVDP_17,Reserved for future use." bitfld.long 0x8 16. "FRS_INTERRUPT_ENABLE,FRS Interrupt Enable. For a description of this standard PCIe register field see the PCI Express Specification." "0,1" hexmask.long.word 0x8 2.--15. 1. "RSVDP_2,Reserved for future use." bitfld.long 0x8 1. "FRS_MESSAGE_OVERFLOW,FRS Message Overflow. For a description of this standard PCIe register field see the PCI Express Specification." "0,1" newline bitfld.long 0x8 0. "FRS_MESSAGE_RECEIVED,FRS Message Received. For a description of this standard PCIe register field see the PCI Express Specification." "0,1" rgroup.long (0xC+0x2E8)++0x3 line.long 0x0 "FRS_MESSAGE_QUEUE_OFF,FRS Message Queue Register. For a description of this standard PCIe register. see the PCI Express Specification." hexmask.long.word 0x0 20.--31. 1. "FRS_MESSAGE_QUE_DEPTH,FRS Message Queue Depth. For a description of this standard PCIe register field see the PCI Express Specification." hexmask.long.byte 0x0 16.--19. 1. "FRS_MESSAGE_QUE_REASON,FRS Message Queue Reason. For a description of this standard PCIe register field see the PCI Express Specification." hexmask.long.word 0x0 0.--15. 1. "FRS_MESSAGE_QUE_FUNC_ID,FRS Message Queue Function ID. For a description of this standard PCIe register field see the PCI Express Specification." tree.end tree "PF0_PTM_CAP (PF PTM Capability Structure)" group.long (0x0+0x40C)++0xB line.long 0x0 "PTM_EXT_CAP_HDR_OFF,Precision Time Measurement Capability Header. For a description of this standard PCIe register. see the PCI Express Specification." hexmask.long.word 0x0 20.--31. 1. "PTM_NEXT_OFFSET,Precision Time Measurement PCI Express Extended Capability Next Offset. For a description of this standard PCIe register see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access. -.." hexmask.long.byte 0x0 16.--19. 1. "PTM_CAP_VERSION,Precision Time Measurement PCI Express Extended Capability Version. For a description of this standard PCIe register see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi:.." hexmask.long.word 0x0 0.--15. 1. "PTM_CAP_ID,Precision Time Measurement PCI Express Extended Capability ID. For a description of this standard PCIe register see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if.." line.long 0x4 "PTM_CAP_OFF,PTM Capability Register. For a description of this standard PCIe register. see the PCI Express Specification." hexmask.long.word 0x4 16.--31. 1. "RSVDP_16,Reserved for future use." hexmask.long.byte 0x4 8.--15. 1. "PTM_CLK_GRAN,PTM Local Clock Granularity. For a description of this standard PCIe register see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky).." hexmask.long.byte 0x4 3.--7. 1. "RSVDP_3,Reserved for future use." bitfld.long 0x4 2. "PTM_ROOT_CAPABLE,PTM Root Capable. For a description of this standard PCIe register see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else.." "0,1" bitfld.long 0x4 1. "PTM_RES_CAPABLE,PTM Responder Capable. For a description of this standard PCIe register see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else.." "0,1" newline bitfld.long 0x4 0. "PTM_REQ_CAPABLE,PTM Requester Capable. For a description of this standard PCIe register see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else.." "0,1" line.long 0x8 "PTM_CONTROL_OFF,PTM Control Register. For a description of this standard PCIe register. see the PCI Express Specification." hexmask.long.word 0x8 16.--31. 1. "RSVDP_16,Reserved for future use." hexmask.long.byte 0x8 8.--15. 1. "EFF_GRAN,PTM Effective Granularity. For a description of this standard PCIe register see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: HWINIT" hexmask.long.byte 0x8 2.--7. 1. "RSVDP_2,Reserved for future use." rbitfld.long 0x8 1. "ROOT_SELECT,PTM Root Select. When set this Time Source is the PTM Root. For a description of this standard PCIe register see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: HWINIT" "0,1" bitfld.long 0x8 0. "PTM_ENABLE,PTM Enable. When set this function is permitted to participate in the PTM mechanism. For a description of this standard PCIe register see the PCI Express Specification." "0,1" tree.end tree "PF0_PTM_RES_CAP (PF PTM Responder Capability Structure (VSEC))" group.long (0x0+0x418)++0xB line.long 0x0 "PTM_RES_CAP_HDR_OFF,Precision Time Measurement Responder Capability Header (VSEC). For more details. see the PTM section in the Databook." hexmask.long.word 0x0 20.--31. 1. "PTM_RES_EXT_CAP_NEXT_OFFS,Precision Time Measurement Responder VSEC Next Pointer. For more details see the PTM section in the Databook. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then.." hexmask.long.byte 0x0 16.--19. 1. "PTM_RES_EXT_CAP_VER,Precision Time Measurement Responder VSEC Version. For more details see the PTM section in the Databook. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else.." hexmask.long.word 0x0 0.--15. 1. "PTM_RES_EXT_CAP_ID,Precision Time Measurement Responder VSEC ID. For more details see the PTM section in the Databook. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else.." line.long 0x4 "PTM_RES_HDR_OFF,Precision Time Measurement Responder Vendor Specific Header. For more details. see the PTM section in the Databook." hexmask.long.word 0x4 20.--31. 1. "PTM_RES_VSEC_LENGTH,PTM Responder VSEC Length. For more details see the PTM section in the Databook. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This.." hexmask.long.byte 0x4 16.--19. 1. "PTM_RES_VSEC_REV,PTM Responder VSEC Revision. For more details see the PTM section in the Databook. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This.." hexmask.long.word 0x4 0.--15. 1. "PTM_RES_VSEC_ID,PTM Responder VSEC ID. For more details see the PTM section in the Databook. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register.." line.long 0x8 "PTM_RES_CONTROL_OFF,PTM Responder Control Register. For more details. see the PTM section in the Databook." hexmask.long 0x8 2.--31. 1. "RSVDP_2,Reserved for future use." bitfld.long 0x8 1. "PTM_RES_PDEL_BYTE_REV,PTM Requester Propagation Delay Byte Reversal - Reverse the order of bytes in the PTM Propagation Delay data word of the PTM ResponseD Message for compatibility with previous revisions. For more details see the PTM section in the.." "0,1" bitfld.long 0x8 0. "PTM_RES_CCONTEXT_VALID,PTM Responder Control Context Valid - PTM Local Timing is valid. This bit is set over the DBI. A speed change or aux_clk_active will set this bit low. For more details see the PTM section in the Databook. Note: The access.." "0,1" rgroup.long (0xC+0x418)++0x3 line.long 0x0 "PTM_RES_STATUS_OFF,PTM Responder Status Register. For more details. see the PTM section in the Databook." hexmask.long 0x0 2.--31. 1. "RSVDP_2,Reserved for future use." bitfld.long 0x0 1. "PTM_RES_REQUEST_RECEIVED,PTM 1st Request Received - PTM Responder has received the first PTM Request Message. Upon receipt of a second PTM Request Message a ResponseD message with timing information will be sent from the Responder if the context is.." "0,1" bitfld.long 0x0 0. "PTM_RES_CONTEXT_VALID,PTM Responder Status Context Valid - PTM Local Timing Context is Valid. Value set from upstream port Requester in a Switch. Shadows the same in the control register in all other products. For more details see the PTM section in the.." "0,1" group.long (0x10+0x418)++0x7 line.long 0x0 "PTM_RES_LOCAL_LSB_OFF,PTM Responder Local Clock LSB. For more details. see the PTM section in the Databook." hexmask.long 0x0 0.--31. 1. "PTM_RES_LOCAL_LSB,PTM Responder Local Clock LSB - Lower 32 bits of local timer value. For more details see the PTM section in the Databook. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then.." line.long 0x4 "PTM_RES_LOCAL_MSB_OFF,PTM Responder Local Clock MSB. For more details. see the PTM section in the Databook." hexmask.long 0x4 0.--31. 1. "PTM_RES_LOCAL_MSB,PTM Responder Local Clock MSB - Upper 32 bits of local timer value. For more details see the PTM section in the Databook. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then.." rgroup.long (0x18+0x418)++0x1F line.long 0x0 "PTM_RES_T2_LSB_OFF,PTM Responder T2 Timestamp LSB. For more details. see the PTM section in the Databook." hexmask.long 0x0 0.--31. 1. "PTM_RES_T2_LSB,PTM Responder T2 Timestamp LSB - Lower 32 bits of the T2 Timestamp value. For more details see the PTM section in the Databook. Note: This register field is sticky." line.long 0x4 "PTM_RES_T2_MSB_OFF,PTM Responder T2 Timestamp MSB. For more details. see the PTM section in the Databook." hexmask.long 0x4 0.--31. 1. "PTM_RES_T2_MSB,PTM Responder T2 Timestamp MSB - Upper 32 bits of the T2 Timestamp value. For more details see the PTM section in the Databook. Note: This register field is sticky." line.long 0x8 "PTM_RES_T2P_LSB_OFF,PTM Responder T2 Previous Timestamp LSB. For more details. see the PTM section in the Databook." hexmask.long 0x8 0.--31. 1. "PTM_RES_T2P_LSB,PTM Responder T2 Previous Timestamp LSB - Lower 32 bits of the previously stored T2 Timestamp value. For more details see the PTM section in the Databook. Note: This register field is sticky." line.long 0xC "PTM_RES_T2P_MSB_OFF,PTM Responder T2 Previous Timestamp MSB. For more details. see the PTM section in the Databook." hexmask.long 0xC 0.--31. 1. "PTM_RES_T2P_MSB,PTM Responder T2 Previous Timestamp MSB - Upper 32 bits of the previously stored T2 Timestamp value. For more details see the PTM section in the Databook. Note: This register field is sticky." line.long 0x10 "PTM_RES_T3_LSB_OFF,PTM Responder T3 Timestamp LSB. For more details. see the PTM section in the Databook." hexmask.long 0x10 0.--31. 1. "PTM_RES_T3_LSB,PTM Responder T3 Timestamp LSB - Lower 32 bits of the T3 Timestamp value. For more details see the PTM section in the Databook. Note: This register field is sticky." line.long 0x14 "PTM_RES_T3_MSB_OFF,PTM Responder T3 Timestamp MSB. For more details. see the PTM section in the Databook." hexmask.long 0x14 0.--31. 1. "PTM_RES_T3_MSB,PTM Responder T3 Timestamp MSB - Upper 32 bits of the T2 Timestamp value. For more details see the PTM section in the Databook. Note: This register field is sticky." line.long 0x18 "PTM_RES_T3P_LSB_OFF,PTM Responder T3 Previous Timestamp LSB. For more details. see the PTM section in the Databook." hexmask.long 0x18 0.--31. 1. "PTM_RES_T3P_LSB,PTM Responder T3 Previous Timestamp LSB - Lower 32 bits of the previously stored T3 Timestamp value. For more details see the PTM section in the Databook. Note: This register field is sticky." line.long 0x1C "PTM_RES_T3P_MSB_OFF,PTM Responder T3 Previous Timestamp MSB. For more details. see the PTM section in the Databook." hexmask.long 0x1C 0.--31. 1. "PTM_RES_T3P_MSB,PTM Responder T3 Previous Timestamp MSB - Upper 32 bits of the previously stored T3 Timestamp value. For more details see the PTM section in the Databook. Note: This register field is sticky." group.long (0x38+0x418)++0x7 line.long 0x0 "PTM_RES_TX_LATENCY_OFF,PTM Responder TX Latency. For more details. see the PTM section in the Databook." hexmask.long.tbyte 0x0 12.--31. 1. "RSVDP_12,Reserved for future use." hexmask.long.word 0x0 0.--11. 1. "PTM_RES_TX_LATENCY,PTM Responder TX Latency - Responder Transmit path latency (12 bit wide). For more details see the PTM section in the Databook. Note: This register field is sticky." line.long 0x4 "PTM_RES_RX_LATENCY_OFF,PTM Responder RX Latency. For more details. see the PTM section in the Databook." hexmask.long.tbyte 0x4 12.--31. 1. "RSVDP_12,Reserved for future use." hexmask.long.word 0x4 0.--11. 1. "PTM_RES_RX_LATENCY,PTM Responder RX Latency - Responder Receive path latency (12 bit wide). For more details see the PTM section in the Databook. Note: This register field is sticky." rgroup.long (0x40+0x418)++0x3 line.long 0x0 "PTM_RES_NOM_CLOCK_T_OFF,PTM Responder Nominal Clock Period. For more details. see the PTM section in the Databook." hexmask.long.byte 0x0 24.--31. 1. "RSVDP_24,Reserved for future use." hexmask.long.byte 0x0 16.--23. 1. "PTM_RES_NOM_CLOCK_T_INT,PTM Responder Nominal Clock Period Integral - Integral part of the nominal PTM local clock period in nanoseconds. For more details see the PTM section in the Databook. Note: This register field is sticky." hexmask.long.word 0x0 0.--15. 1. "PTM_RES_NOM_CLOCK_T_FRAC,PTM Responder Nominal Clock Period Fractional - Fractional part of the nominal PTM local clock period. LSB is 1/(2^16) nanoseconds. For more details see the PTM section in the Databook. Note: This register field is sticky." group.long (0x44+0x418)++0x3 line.long 0x0 "PTM_RES_SCALED_CLOCK_T_OFF,PTM Responder Scaled Clock Period. For more details. see the PTM section in the Databook." bitfld.long 0x0 31. "PTM_RES_SCALED_CLOCK_T_EN,PTM Responder Scaled Clock Period Enable - Use the programmed scaled PTM clock period rather than the nominal values. This bit is cleared when the core_clk rate starts to change and can only be set when the clock period change.." "0,1" hexmask.long.byte 0x0 24.--30. 1. "RSVDP_24,Reserved for future use." hexmask.long.byte 0x0 16.--23. 1. "PTM_RES_SCALED_CLOCK_T_INT,PTM Responder Scaled Clock Period Integral - Integral part of the nominal PTM local clock period in nanoseconds. For more details see the PTM section in the Databook. Note: This register field is sticky." newline hexmask.long.word 0x0 0.--15. 1. "PTM_RES_SCALED_CLOCK_T_FRAC,PTM Responder Scaled Clock Period Fractional - Fractional part of the nominal PTM local clock period. LSB is 1/(2^16) nanoseconds. For more details see the PTM section in the Databook. Note: This register field is sticky." tree.end tree "PF0_PM_CAP (PF PCI Power Management Capability Structure)" group.long (0x0+0x40)++0x7 line.long 0x0 "CAP_ID_NXT_PTR_REG,Power Management Capabilities Register." hexmask.long.byte 0x0 27.--31. 1. "PME_SUPPORT,PME_Support. This 5-bit field indicates the power states in which the function may generate a PME and/or forward PME messages. A value of 0b for any bit indicates that the function is not capable of asserting PME while in that power state. -.." bitfld.long 0x0 26. "D2_SUPPORT,D2_Support. If this bit is set this function supports the D2 Power Management state. Functions that do not support D2 must always return a value of 0b for this bit. Note: The access attributes of this field are as follows: - Wire: No access." "0,1" bitfld.long 0x0 25. "D1_SUPPORT,D1_Support. If this bit is set this function supports the D1 Power Management state. Functions that do not support D1 must always return a value of 0b for this bit. Note: The access attributes of this field are as follows: - Wire: No access." "0,1" bitfld.long 0x0 22.--24. "AUX_CURR,Aux_Current. This 3 bit field reports the Vaux auxiliary current requirements for the function. If this function implements the Data Register the controller hardwires this field to 000b. If PME_Support is 0 xxxxb (PME assertion from D3cold is.." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 21. "DSI,Device Specific Initialization. The DSI bit indicates whether special initialization of this function is required. When set indicates that the function requires a device specific initialization sequence following a transition to the D0uninitialized.." "0,1" bitfld.long 0x0 20. "PME_IMM_READI_RETURN_DO,Immediate_Readiness_on_Return_to_D0. - If this bit is a '1' this function is guaranteed to be ready to successfully complete valid accesses immediately after being set to D0. These accesses include configuration cycles and if.." "0,1" rbitfld.long 0x0 19. "PME_CLK,PME Clock. Does not apply to PCI Express the controller hardwires it to 0b. Note: This register field is sticky." "0,1" bitfld.long 0x0 16.--18. "PM_SPEC_VER,Version. This field provides the Power Management specification version. The controller hardwires this field to 011b for functions compliant to PCI Express Base Specification Revision 4.0 Version 1.0>. Note: The access attributes of this.." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x0 8.--15. 1. "PM_NEXT_POINTER,Next Capability Pointer. This field provides an offset into the function's configuration space pointing to the location of next item in the capabilities list. If there are no additional items in the capabilities list this field is set to.." hexmask.long.byte 0x0 0.--7. 1. "PM_CAP_ID,Capability ID. This field returns 01h to indicate that this is the PCI Power Management Capability. Each function may have only one item in its capability list with Capability ID set to 01h." line.long 0x4 "CON_STATUS_REG,Power Management Control and Status Register. This register is used to manage the PCI function's power management state as well as to enable/monitor PMEs." hexmask.long.byte 0x4 24.--31. 1. "DATA_REG_ADD_INFO,Data. This field is used to report the state dependent data requested by the Data_Select field. The value of this field is scaled by the value reported by the Data_Scale field." rbitfld.long 0x4 23. "BUS_PWR_CLK_CON_EN,Bus Power/Clock Control Enable. For a description of this standard PCIe register field see the PCI Express Base Specification." "0,1" rbitfld.long 0x4 22. "B2_B3_SUPPORT,B2B3 Support for D3hot. For a description of this standard PCIe register field see the PCI Express Base Specification." "0,1" hexmask.long.byte 0x4 16.--21. 1. "RSVDP_16,Reserved for future use." newline bitfld.long 0x4 15. "PME_STATUS,PME_Status. This bit is set when the function normally generates a PME signal. The value of this bit is not affected by the value of the PME_En bit. If PME_Support bit 31 of the Power Management Capabilities register is clear this bit is.." "0,1" rbitfld.long 0x4 13.--14. "DATA_SCALE,Data_Scale. This field indicates the scaling factor to be used when interpreting the value of the Data field. The value and meaning of this field varies depending on which data value has been selected by the Data_Select field. For more details.." "0,1,2,3" hexmask.long.byte 0x4 9.--12. 1. "DATA_SELECT,Data_Select. This 4-bit field is used to select which data is to be reported through the Data and Data_Scale field. If the Data field is not implemented this field must be hardwired to 0000b." bitfld.long 0x4 8. "PME_ENABLE,PME_En. - When set the function is permitted to generate a PME. - When clear the function is not permitted to generate a PME. If PME_Support is 1 xxxxb (PME generation from D3cold) or the function consumes Aux power and Aux power is.." "0,1" newline hexmask.long.byte 0x4 4.--7. 1. "RSVDP_4,Reserved for future use." bitfld.long 0x4 3. "NO_SOFT_RST,No_Soft_Reset. This bit indicates the state of the function after writing the PowerState field to transition the function from D3hot to D0. - When set this transition preserves internal function state. The function is in D0Active and no.." "0,1" rbitfld.long 0x4 2. "RSVDP_2,Reserved for future use." "0,1" bitfld.long 0x4 0.--1. "POWER_STATE,PowerState. This 2-bit field is used both to determine the current power state of a function and to set the function into a new power state. The definition of the field values is given below. You can write to this register; however the.." "D0,D1,D2,D3hot" tree.end tree "PF0_PCIE_CAP (PF PCI Express Capability Structure)" group.long (0x0+0x70)++0x33 line.long 0x0 "PCIE_CAP_ID_PCIE_NEXT_CAP_PTR_PCIE_CAP_REG,PCI Express Capabilities. ID. Next Pointer Register." rbitfld.long 0x0 31. "RSVDP_31,Reserved for future use." "0,1" rbitfld.long 0x0 30. "RSVD,Reserved." "0,1" newline hexmask.long.byte 0x0 25.--29. 1. "PCIE_INT_MSG_NUM,PCIE Interrupt Message Number. For a description of this standard PCIe register field see the PCI Express Base Specification. Interrupt Message Number. This field indicates which MSI/MSI-X vector is used for the interrupt message.." bitfld.long 0x0 24. "PCIE_SLOT_IMP,Slot Implemented. When set this bit indicates that the Link associated with this Port is connected to a slot (as compared to being connected to a system-integrated device or being disabled). This bit is valid for Downstream Ports. This bit.." "0,1" newline hexmask.long.byte 0x0 20.--23. 1. "PCIE_DEV_PORT_TYPE,Device/Port Type. Indicates the specific type of this PCI Express function. Note: Different functions in a Multi-Function Device can generally be of different types. Defined encodings for functions that implement a Type 00h PCI.." hexmask.long.byte 0x0 16.--19. 1. "PCIE_CAP_REG,Capability Version. Indicates PCI-SIG defined PCI Express Capability structure version number. A version of the specification that changes the PCI Express Capability structure in a way that is not otherwise identifiable (for example through.." newline hexmask.long.byte 0x0 8.--15. 1. "PCIE_CAP_NEXT_PTR,Next Capability Pointer. This field contains the offset to the next PCI Capability structure or 00h if no other items exist in the linked list of Capabilities. Note: The access attributes of this field are as follows: - Wire: No access." hexmask.long.byte 0x0 0.--7. 1. "PCIE_CAP_ID,Capability ID. Indicates the PCI Express Capability structure. This field must return a Capability ID of 10h indicating that this is a PCI Express Capability structure." line.long 0x4 "DEVICE_CAPABILITIES_REG,Device Capabilities Register. The Device Capabilities register identifies PCI Express device function specific capabilities." hexmask.long.word 0x4 16.--31. 1. "RSVDP_16,Reserved for future use." bitfld.long 0x4 15. "PCIE_CAP_ROLE_BASED_ERR_REPORT,Role-Based Error Reporting. When set this bit indicates that the function implements the functionality originally defined in the Error Reporting ECN for PCI Express Base Specification Revision 1.0a and later incorporated.." "0,1" newline hexmask.long.word 0x4 6.--14. 1. "RSVDP_6,Reserved for future use." bitfld.long 0x4 5. "PCIE_CAP_EXT_TAG_SUPP,Extended Tag Field Supported. This bit in combination with the 10-Bit Tag Requester Supported bit in the Device Capabilities 2 register indicates the maximum supported size of the Tag field as a Requester. This bit must be set if.." "0,1" newline bitfld.long 0x4 3.--4. "PCIE_CAP_PHANTOM_FUNC_SUPPORT,Phantom Functions Supported. This field indicates the support for use of unclaimed function numbers to extend the number of outstanding transactions allowed by logically combining unclaimed function numbers (called Phantom.." "0,1,2,3" bitfld.long 0x4 0.--2. "PCIE_CAP_MAX_PAYLOAD_SIZE,Max_Payload_Size Supported. This field indicates the maximum payload size that the function can support for TLPs. Defined encodings are: - 000b: 128 bytes max payload size - 001b: 256 bytes max payload size - 010b: 512 bytes max.." "0,1,2,3,4,5,6,7" line.long 0x8 "DEVICE_CONTROL_DEVICE_STATUS,Device Control and Device Status Register. This register controls PCI Express device specific parameters and provides information about PCI Express device (function) specific parameters." hexmask.long.word 0x8 22.--31. 1. "RSVDP_22,Reserved for future use." rbitfld.long 0x8 21. "PCIE_CAP_TRANS_PENDING,Transactions Pending. Endpoints: When set this bit indicates that the function has issued Non-Posted Requests that have not been completed. A Function reports this bit cleared only when all outstanding Non-Posted Requests have.." "0,1" newline rbitfld.long 0x8 20. "PCIE_CAP_AUX_POWER_DETECTED,AUX Power Detected. Functions that require Aux power report this bit as set if Aux power is detected by the function. This bit is derived by sampling the sys_aux_pwr_det input." "0,1" bitfld.long 0x8 19. "PCIE_CAP_UNSUPPORTED_REQ_DETECTED,Unsupported Request Detected. This bit indicates that the function received an Unsupported Request. Errors are logged in this register regardless of whether error reporting is enabled or not in the Device Control.." "0,1" newline bitfld.long 0x8 17. "PCIE_CAP_NON_FATAL_ERR_DETECTED,Non-Fatal Error Detected. This bit indicates status of Non-fatal errors detected. Errors are logged in this register regardless of whether error reporting is enabled or not in the Device Control register. For a.." "0,1" bitfld.long 0x8 12.--14. "PCIE_CAP_MAX_READ_REQ_SIZE,Max_Read_Request_Size. This field sets the maximum Read Request size for the function as a Requester. The function must not generate Read Requests with a size exceeding the set value. Defined encodings for this field are: -.." "0,1,2,3,4,5,6,7" newline rbitfld.long 0x8 11. "PCIE_CAP_EN_NO_SNOOP,Enable No Snoop. If this bit is set the function is permitted to Set the No Snoop bit in the Requester Attributes of transactions it initiates that do not require hardware enforced cache coherency (see section 2.2.6.5 in PCI Express.." "0,1" bitfld.long 0x8 10. "PCIE_CAP_AUX_POWER_PM_EN,Aux Power PM Enable. This bit is derived by sampling the sys_aux_pwr_det input. When set this bit enables a function to draw Aux power independent of PME Aux power. Functions that require Aux power on legacy operating systems.." "0,1" newline rbitfld.long 0x8 9. "PCIE_CAP_PHANTOM_FUNC_EN,Phantom Functions Enable. This bit in combination with the 10-Bit Tag Requester Enable bit in the Device Control 2 register determines how many Tag field bits a Requester is permitted to use. When the 10-Bit Tag Requester.." "0,1" rbitfld.long 0x8 8. "PCIE_CAP_EXT_TAG_EN,Extended Tag Field Enable. This bit in combination with the 10-Bit Tag Requester Enable bit in the Device Control 2 register determines how many Tag field bits a Requester is permitted to use. When the 10-Bit Tag Requester Enable.." "0,1" newline bitfld.long 0x8 5.--7. "PCIE_CAP_MAX_PAYLOAD_SIZE_CS,Max_Payload_Size. This field sets maximum TLP payload size for the Function. As a Receiver the Function must handle TLPs as large as the set value. As a Transmitter the Function must not generate TLPs exceeding the set.." "0,1,2,3,4,5,6,7" bitfld.long 0x8 4. "PCIE_CAP_EN_REL_ORDER,Enable Relaxed Ordering. If this bit is set the function is permitted to set the Relaxed Ordering bit in the Attributes field of transactions it initiates that do not require strong write ordering (for more details see section.." "0,1" newline bitfld.long 0x8 3. "PCIE_CAP_UNSUPPORT_REQ_REP_EN,Unsupported Request Reporting Enable. This bit in conjunction with other bits controls the signaling of Unsupported Request Errors by sending error Messages (for more details see section 6.2.5 and section 6.2.6 of PCI.." "0,1" bitfld.long 0x8 2. "PCIE_CAP_FATAL_ERR_REPORT_EN,Fatal Error Reporting Enable. This bit in conjunction with other bits controls sending ERR_FATAL Messages (for more details see section 6.2.5 and section 6.2.6 of of PCI Express Base Specification). For a Multi-Function.." "0,1" newline bitfld.long 0x8 1. "PCIE_CAP_NON_FATAL_ERR_REPORT_EN,Non-Fatal Error Reporting Enable. This bit in conjunction with other bits controls sending ERR_NONFATAL Messages (for more details see section 6.2.5 and Section 6.2.6 of PCI Express Base Specification). For a.." "0,1" bitfld.long 0x8 0. "PCIE_CAP_CORR_ERR_REPORT_EN,Correctable Error Reporting Enable. This bit in conjunction with other bits controls sending ERR_COR Messages (for more details see section 6.2.5 section 6.2.6 and section 6.2.10.2 of PCI Express Base Specification). For.." "0,1" line.long 0xC "LINK_CAPABILITIES_REG,Link Capabilities Register. The Link Capabilities register identifies PCI Express Link specific capabilities." hexmask.long.byte 0xC 24.--31. 1. "PCIE_CAP_PORT_NUM,Port Number. This field indicates the PCI Express Port number for the given PCI Express Link. Multi-Function Devices associated with an Upstream Port must report the same value in this field for all functions. Note: The access.." rbitfld.long 0xC 23. "RSVDP_23,Reserved for future use." "0,1" newline bitfld.long 0xC 22. "PCIE_CAP_ASPM_OPT_COMPLIANCE,ASPM Optionality Compliance. This bit must be set to 1b in all functions. Components implemented against certain earlier versions of this specification will have this bit set to 0b. Software is permitted to use the value of.." "0,1" bitfld.long 0xC 21. "PCIE_CAP_LINK_BW_NOT_CAP,Link Bandwidth Notification Capability. A value of 1b indicates support for the Link Bandwidth Notification status and interrupt mechanisms. This capability is required for all Root Ports and Switch Downstream Ports supporting.." "0,1" newline rbitfld.long 0xC 20. "PCIE_CAP_DLL_ACTIVE_REP_CAP,Data Link Layer Link Active Reporting Capable. For a Downstream Port the controller hardwires this bit to 1b if the component supports the optional capability of reporting the DL_Active state of the Data Link Control and.." "0,1" bitfld.long 0xC 19. "PCIE_CAP_SURPRISE_DOWN_ERR_REP_CAP,Surprise Down Error Reporting Capable. For a Downstream Port this bit must be set if the component supports the optional capability of detecting and reporting a Surprise Down error condition. For Upstream Ports and.." "0,1" newline rbitfld.long 0xC 18. "PCIE_CAP_CLOCK_POWER_MAN,Clock Power Management. For Upstream Ports a value of 1b in this bit indicates that the component tolerates the removal of any reference clock(s) via the 'clock request' (CLKREQ#) mechanism when the Link is in the L1 and L2/L3.." "0,1" bitfld.long 0xC 15.--17. "PCIE_CAP_L1_EXIT_LATENCY,L1 Exit Latency. This field indicates the L1 exit latency for the given PCI Express Link. The value reported indicates the length of time this Port requires to complete transition from ASPM L1 to L0. If ASPM L1 is not supported.." "0,1,2,3,4,5,6,7" newline bitfld.long 0xC 12.--14. "PCIE_CAP_L0S_EXIT_LATENCY,L0s Exit Latency. This field indicates the L0s exit latency for the given PCI Express Link. The value reported indicates the length of time this Port requires to complete transition from L0s to L0. If L0s is not supported the.." "0,1,2,3,4,5,6,7" bitfld.long 0xC 10.--11. "PCIE_CAP_ACTIVE_STATE_LINK_PM_SUPPORT,Active State Power Management (ASPM) Support. This field indicates the level of ASPM supported on the given PCI Express Link. For more details on ASPM support requirements see section 5.4.1 of PCI Express Base.." "0,1,2,3" newline hexmask.long.byte 0xC 4.--9. 1. "PCIE_CAP_MAX_LINK_WIDTH,Maximum Link Width. This field indicates the maximum Link width (xN - corresponding to N Lanes) implemented by the component. This value is permitted to exceed the number of Lanes routed to the slot (Downstream Port) adapter.." hexmask.long.byte 0xC 0.--3. 1. "PCIE_CAP_MAX_LINK_SPEED,Max Link Speed. This field indicates the maximum Link speed of the associated Port. The encoded value specifies a bit location in the Supported Link Speeds Vector (in the Link Capabilities 2 register) that corresponds to the.." line.long 0x10 "LINK_CONTROL_LINK_STATUS_REG,Link Control and Link Status Register. This register controls and provides information about PCI Express Link specific parameters." bitfld.long 0x10 31. "PCIE_CAP_LINK_AUTO_BW_STATUS,Link Autonomous Bandwidth Status. This bit is set by hardware to indicate that hardware has autonomously changed Link speed or width without the Port transitioning through DL_Down status for reasons other than to attempt to.." "0,1" bitfld.long 0x10 30. "PCIE_CAP_LINK_BW_MAN_STATUS,Link Bandwidth Management Status. This bit is set by hardware to indicate that either of the following has occurred without the Port transitioning through DL_Down status: - A Link retraining has completed following a write of.." "0,1" newline rbitfld.long 0x10 29. "PCIE_CAP_DLL_ACTIVE,Data Link Layer Link Active. This bit indicates the status of the Data Link Control and Management State Machine. It returns a 1b to indicate the DL_Active state 0b otherwise. This bit must be implemented if the Data Link Layer Link.." "0,1" bitfld.long 0x10 28. "PCIE_CAP_SLOT_CLK_CONFIG,Slot Clock Configuration. This bit indicates that the component uses the same physical reference clock that the platform provides on the connector. If the device uses an independent clock irrespective of the presence of a.." "0,1" newline rbitfld.long 0x10 27. "PCIE_CAP_LINK_TRAINING,Link Training. This read-only bit indicates that the Physical Layer LTSSM is in the Configuration or Recovery state or that 1b was written to the Retrain Link bit but Link training has not yet begun. Hardware clears this bit when.." "0,1" rbitfld.long 0x10 26. "RSVDP_26,Reserved for future use." "0,1" newline hexmask.long.byte 0x10 20.--25. 1. "PCIE_CAP_NEGO_LINK_WIDTH,Negotiated Link Width. This field indicates the negotiated width of the given PCI Express Link. Defined encodings are: -00 0001b: x1 -00 0010b: x2 -00 0100b: x4 -00 1000b: x8 -00 1100b: x12 -01 0000b: x16 -10 0000b: x32 All other.." hexmask.long.byte 0x10 16.--19. 1. "PCIE_CAP_LINK_SPEED,Current Link Speed. This field indicates the negotiated Link speed of the given PCI Express Link. The encoded value specifies a bit location in the Supported Link Speeds Vector (in the Link Capabilities 2 register) that corresponds to.." newline bitfld.long 0x10 14.--15. "PCIE_CAP_DRS_SIGNALING_CONTROL,DRS Signaling Control. Indicates the mechanism used to report reception of a DRS message. Must be implemented for Downstream Ports with the DRS Supported bit Set in the Link Capabilities 2 Register. Encodings are: - 00b:.." "0,1,2,3" rbitfld.long 0x10 12.--13. "RSVDP_12,Reserved for future use." "0,1,2,3" newline bitfld.long 0x10 11. "PCIE_CAP_LINK_AUTO_BW_INT_EN,Link Autonomous Bandwidth Management Interrupt Enable. When set this bit enables the generation of an interrupt to indicate that the Link Autonomous Bandwidth Status bit has been set. The write value is gated with the.." "0,1" bitfld.long 0x10 10. "PCIE_CAP_LINK_BW_MAN_INT_EN,Link Bandwidth Management Interrupt Enable. When set this bit enables the generation of an interrupt to indicate that the Link Bandwidth Management Status bit has been set. The write value is gated with the.." "0,1" newline bitfld.long 0x10 9. "PCIE_CAP_HW_AUTO_WIDTH_DISABLE,Hardware Autonomous Width Disable. When set this bit disables hardware from changing the Link width for reasons other than attempting to correct unreliable Link operation by reducing Link width. For a Multi-Function Device.." "0,1" bitfld.long 0x10 8. "PCIE_CAP_EN_CLK_POWER_MAN,Enable Clock Power Management. Applicable only for Upstream Ports and with form factors that support a 'Clock Request' (CLKREQ#) mechanism this bit operates as follows: - 0b: Clock power management is disabled and device must.." "0,1" newline bitfld.long 0x10 7. "PCIE_CAP_EXTENDED_SYNCH,Extended Synch. When set this bit forces the transmission of additional Ordered Sets when exiting the L0s state (see section 4.2.4.5 of PCI Express Base Specification) and when in the Recovery state (see section 4.2.6.4.1 of PCI.." "0,1" bitfld.long 0x10 6. "PCIE_CAP_COMMON_CLK_CONFIG,Common Clock Configuration. When set this bit indicates that this component and the component at the opposite end of this Link are operating with a distributed common reference clock. A value of 0b indicates that this.." "0,1" newline bitfld.long 0x10 5. "PCIE_CAP_RETRAIN_LINK,Retrain Link. A write of 1b to this bit initiates Link retraining by directing the Physical Layer LTSSM to the Recovery state. If the LTSSM is already in Recovery or Configuration re-entering Recovery is permitted but not required." "0,1" bitfld.long 0x10 4. "PCIE_CAP_LINK_DISABLE,Link Disable. This bit disables the Link by directing the LTSSM to the Disabled state when set; this bit is Reserved on Endpoints PCI Express to PCI/PCI-X bridges and Upstream Ports of Switches. Writes to this bit are immediately.." "0,1" newline bitfld.long 0x10 3. "PCIE_CAP_RCB,Read Completion Boundary (RCB). Root Ports: Indicates the RCB value for the Root Port. Refer to section 2.3.1.1 of PCI Express Base Specification for the definition of the parameter RCB. Defined encodings are: - 0b: 64 byte - 1b: 128 byte.." "0,1" rbitfld.long 0x10 2. "RSVDP_2,Reserved for future use." "0,1" newline bitfld.long 0x10 0.--1. "PCIE_CAP_ACTIVE_STATE_LINK_PM_CONTROL,Active State Power Management (ASPM) Control. This field controls the level of ASPM enabled on the given PCI Express Link. See section 5.4.1.3 of PCI Express Base Specification for requirements on when and how to.." "0,1,2,3" line.long 0x14 "SLOT_CAPABILITIES_REG,Slot Capabilities Register. The Slot Capabilities register identifies PCI Express slot specific capabilities." hexmask.long.word 0x14 19.--31. 1. "PCIE_CAP_PHY_SLOT_NUM,Physical Slot Number. This field indicates the physical slot number attached to this Port. This field must be hardware initialized to a value that assigns a slot number that is unique within the chassis regardless of the form.." bitfld.long 0x14 18. "PCIE_CAP_NO_CMD_CPL_SUPPORT,No Command Completed Support. When set this bit indicates that this slot does not generate software notification when an issued command is completed by the Hot-Plug Controller. This bit is only permitted to be set if the.." "0,1" newline bitfld.long 0x14 17. "PCIE_CAP_ELECTROMECH_INTERLOCK,Electromechanical Interlock Present. When set this bit indicates that an Electromechanical Interlock is implemented on the chassis for this slot. Note: The access attributes of this field are as follows: - Wire: No access." "0,1" bitfld.long 0x14 15.--16. "PCIE_CAP_SLOT_POWER_LIMIT_SCALE,Slot Power Limit Scale. Specifies the scale used for the Slot Power Limit Value (for more details see Section 6.9 of PCI Express Base Specification). Range of Values: - 00b: 1.0x - 01b: 0.1x - 10b: 0.01x - 11b: 0.001x.." "0,1,2,3" newline hexmask.long.byte 0x14 7.--14. 1. "PCIE_CAP_SLOT_POWER_LIMIT_VALUE,Slot Power Limit Value. In combination with the Slot Power Limit Scale value specifies the upper limit on power supplied by the slot (for more detais see Section 6.9 of PCI Express Base Specification) or by other means.." bitfld.long 0x14 6. "PCIE_CAP_HOT_PLUG_CAPABLE,Hot-Plug Capable. When set this bit indicates that this slot is capable of supporting hot-plug operations. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then R/W else R" "0,1" newline bitfld.long 0x14 5. "PCIE_CAP_HOT_PLUG_SURPRISE,Hot-Plug Surprise. When set this bit indicates that an adapter present in this slot might be removed from the system without any prior notification. This is a form factor specific capability. This bit is an indication to the.." "0,1" bitfld.long 0x14 4. "PCIE_CAP_POWER_INDICATOR,Power Indicator Present. When set this bit indicates that a Power Indicator is electrically controlled by the chassis for this slot. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if.." "0,1" newline bitfld.long 0x14 3. "PCIE_CAP_ATTENTION_INDICATOR,Attention Indicator Present. When set this bit indicates that an Attention Indicator is electrically controlled by the chassis. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if.." "0,1" bitfld.long 0x14 2. "PCIE_CAP_MRL_SENSOR,MRL Sensor Present. When set this bit indicates that an MRL Sensor is implemented on the chassis for this slot. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then R/W else R" "0,1" newline bitfld.long 0x14 1. "PCIE_CAP_POWER_CONTROLLER,Power Controller Present. When set this bit indicates that a software programmable Power Controller is implemented for this slot/adapter (depending on form factor). Note: The access attributes of this field are as follows: -.." "0,1" bitfld.long 0x14 0. "PCIE_CAP_ATTENTION_INDICATOR_BUTTON,Attention Button Present. When set this bit indicates that an Attention Button for this slot is electrically controlled by the chassis. Note: The access attributes of this field are as follows: - Wire: No access. -.." "0,1" line.long 0x18 "SLOT_CONTROL_SLOT_STATUS,Slot Control and Status Register. This register controls and provides information about PCI Express Slot specific parameters." hexmask.long.byte 0x18 25.--31. 1. "RSVDP_25,Reserved for future use." bitfld.long 0x18 24. "PCIE_CAP_DLL_STATE_CHANGED,Data Link Layer State Changed. This bit is set when the value reported in the Data Link Layer Link Active bit of the Link Status register is changed. In response to a Data Link Layer State Changed event software must read the.." "0,1" newline rbitfld.long 0x18 23. "PCIE_CAP_ELECTROMECH_INTERLOCK_STATUS,Electromechanical Interlock Status. If an Electromechanical Interlock is implemented this bit indicates the status of the Electromechanical Interlock. Defined encodings are: - 0b: Electromechanical Interlock.." "0,1" rbitfld.long 0x18 22. "PCIE_CAP_PRESENCE_DETECT_STATE,Presence Detect State. This bit indicates the presence of an adapter in the slot reflected by the logical 'OR' of the Physical Layer in-band presence detect mechanism and if present any out-of-band presence detect.." "0,1" newline rbitfld.long 0x18 21. "PCIE_CAP_MRL_SENSOR_STATE,MRL Sensor State. This bit reports the status of the MRL sensor if implemented. Defined encodings are: - 0b: MRL Closed - 1b: MRL Open" "0,1" bitfld.long 0x18 20. "PCIE_CAP_CMD_CPLD,Command Completed. If Command Completed notification is supported (if the No Command Completed Support bit in the Slot Capabilities register is 0b) this bit is set when a hot-plug command has completed and the Hot-Plug Controller is.." "0,1" newline bitfld.long 0x18 19. "PCIE_CAP_PRESENCE_DETECTED_CHANGED,Presence Detect Changed. This bit is set when the value reported in the Presence Detect State bit is changed." "0,1" bitfld.long 0x18 18. "PCIE_CAP_MRL_SENSOR_CHANGED,MRL Sensor Changed. If an MRL sensor is implemented this bit is set when a MRL Sensor state change is detected. If an MRL sensor is not implemented this bit must not be set." "0,1" newline bitfld.long 0x18 17. "PCIE_CAP_POWER_FAULT_DETECTED,Power Fault Detected. If a Power Controller that supports power fault detection is implemented this bit issSet when the Power Controller detects a power fault at this slot. Note: Depending on hardware capability it is.." "0,1" bitfld.long 0x18 16. "PCIE_CAP_ATTENTION_BUTTON_PRESSED,Attention Button Pressed. If an Attention Button is implemented this bit is set when the attention button is pressed. If an Attention Button is not supported this bit must not be set." "0,1" newline rbitfld.long 0x18 14.--15. "RSVDP_14,Reserved for future use." "0,1,2,3" bitfld.long 0x18 12. "PCIE_CAP_DLL_STATE_CHANGED_EN,Data Link Layer State Changed Enable. If the Data Link Layer Link Active Reporting capability is 1b this bit enables software notification when Data Link Layer Link Active bit is changed. If the Data Link Layer Link Active.." "0,1" newline bitfld.long 0x18 11. "PCIE_CAP_ELECTROMECH_INTERLOCK_CTRL,Electromechanical Interlock Control. If an Electromechanical Interlock is implemented a write of 1b to this bit causes the state of the interlock to toggle. A write of 0b to this bit has no effect. A read of this bit.." "0,1" bitfld.long 0x18 10. "PCIE_CAP_POWER_CONTROLLER_CTRL,Power Controller Control. If a Power Controller is implemented this bit when written sets the power state of the slot per the defined encodings. Reads of this bit must reflect the value from the latest write even if the.." "0,1" newline bitfld.long 0x18 8.--9. "PCIE_CAP_POWER_INDICATOR_CTRL,Power Indicator Control. If a Power Indicator is implemented writes to this field set the Power Indicator to the written state. Reads of this field must reflect the value from the latest write even if the corresponding.." "0,1,2,3" bitfld.long 0x18 6.--7. "PCIE_CAP_ATTENTION_INDICATOR_CTRL,Attention Indicator Control. If an Attention Indicator is implemented writes to this field set the Attention Indicator to the written state. Reads of this field must reflect the value from the latest write even if the.." "0,1,2,3" newline bitfld.long 0x18 5. "PCIE_CAP_HOT_PLUG_INT_EN,Hot-Plug Interrupt Enable. When set this bit enables generation of an interrupt on enabled hot-plug events. If the Hot Plug Capable bit in the Slot Capabilities register is clear this bit is permitted to be read-only with a.." "0,1" bitfld.long 0x18 4. "PCIE_CAP_CMD_CPL_INT_EN,Command Completed Interrupt Enable. If Command Completed notification is supported (if the No Command Completed Support bit in the Slot Capabilities register is 0b) when set this bit enables software notification when a hot-plug.." "0,1" newline bitfld.long 0x18 3. "PCIE_CAP_PRESENCE_DETECT_CHANGE_EN,Presence Detect Changed Enable. When set this bit enables software notification on a presence detect changed event (for more details see Section 6.7.3 of PCI Express Base Specification). If the Hot-Plug Capable bit in.." "0,1" bitfld.long 0x18 2. "PCIE_CAP_MRL_SENSOR_CHANGED_EN,MRL Sensor Changed Enable. When set this bit enables software notification on a MRL sensor changed event (for more details see Section 6.7.3 of PCI Express Base Specification). If the MRL Sensor Present bit in the Slot.." "0,1" newline bitfld.long 0x18 1. "PCIE_CAP_POWER_FAULT_DETECTED_EN,Power Fault Detected Enable. When set this bit enables software notification on a power fault event (for more details see Section 6.7.3 of PCI Express Base Specification). If a Power Controller that supports power fault.." "0,1" bitfld.long 0x18 0. "PCIE_CAP_ATTENTION_BUTTON_PRESSED_EN,Attention Button Pressed Enable. When set to 1b this bit enables software notification on an attention button pressed event (for more details see Section 6.7.3 of PCI Express Base Specification). If the Attention.." "0,1" line.long 0x1C "ROOT_CONTROL_ROOT_CAPABILITIES_REG,Root Control and Capabilities Register. This register controls PCI Express Root Complex specific parameters and identifies PCI Express Root Port specific capabilities." hexmask.long.word 0x1C 17.--31. 1. "RSVDP_17,Reserved for future use." bitfld.long 0x1C 16. "PCIE_CAP_CRS_SW_VISIBILITY,CRS Software Visibility Capable. For a description of this standard PCIe register field see the PCI Express Base Specification. CRS Software Visibility. When set this bit indicates that the Root Port is capable of returning.." "0,1" newline hexmask.long.word 0x1C 5.--15. 1. "RSVDP_5,Reserved for future use." bitfld.long 0x1C 4. "PCIE_CAP_CRS_SW_VISIBILITY_EN,CRS Software Visibility Enable. When set this bit enables the Root Port to return Configuration Request Retry Status (CRS) Completion Status to software (for more details see section 2.3.1 of PCI Express Base.." "0,1" newline bitfld.long 0x1C 3. "PCIE_CAP_PME_INT_EN,PME Interrupt Enable. When set this bit enables PME interrupt generation upon receipt of a PME Message as reflected in the PME Status bit (for more details see Table 7-29 of PCI Express Base Specification). A PME interrupt is also.." "0,1" bitfld.long 0x1C 2. "PCIE_CAP_SYS_ERR_ON_FATAL_ERR_EN,System Error on Fatal Error Enable. If set this bit indicates that a System Error should be generated if a Fatal error (ERR_FATAL) is reported by any of the devices in the Hierarchy Domain associated with this Root Port.." "0,1" newline bitfld.long 0x1C 1. "PCIE_CAP_SYS_ERR_ON_NON_FATAL_ERR_EN,System Error on Non-Fatal Error Enable. If set this bit indicates that a System Error should be generated if a Non-fatal error (ERR_NONFATAL) is reported by any of the devices in the Hierarchy Domain associated with.." "0,1" bitfld.long 0x1C 0. "PCIE_CAP_SYS_ERR_ON_CORR_ERR_EN,System Error on Correctable Error Enable. If set this bit indicates that a System Error should be generated if a correctable error (ERR_COR) is reported by any of the devices in the Hierarchy Domain associated with this.." "0,1" line.long 0x20 "ROOT_STATUS_REG,Root Status Register. The Root Status register provides information about PCI Express device specific parameters." hexmask.long.word 0x20 18.--31. 1. "RSVDP_18,Reserved for future use." rbitfld.long 0x20 17. "PCIE_CAP_PME_PENDING,PME Pending. This bit indicates that another PME is pending when the PME Status bit is s et. When the PME Status bit is cleared by software; the PME is delivered by hardware by setting the PME Status bit again and updating the PME.." "0,1" newline bitfld.long 0x20 16. "PCIE_CAP_PME_STATUS,PME Status. This bit indicates that PME was asserted by the PME Requester indicated in the PME Requester ID field. Subsequent PMEs are kept pending until the status register is cleared by software by writing a 1b." "0,1" hexmask.long.word 0x20 0.--15. 1. "PCIE_CAP_PME_REQ_ID,PME Requester ID. This field indicates the PCI Requester ID of the last PME Requester. This field is only valid when the PME Status bit is set." line.long 0x24 "DEVICE_CAPABILITIES2_REG,Device Capabilities 2 Register." bitfld.long 0x24 31. "PCIE_CAP_FRS_SUPPORTED,FRS Supported. When set indicates support for the optional Function Readiness Status (FRS) capability. Must be set for all Functions that support generation or reception capabilities of FRS Messages. Must not be set by Switch.." "0,1" hexmask.long.byte 0x24 24.--30. 1. "RSVDP_24,Reserved for future use." newline rbitfld.long 0x24 17. "PCIE_CAP2_10_BIT_TAG_REQ_SUPPORT,10-Bit Tag Requester Supported. If this bit is set the Function supports 10-Bit Tag Requester capability; otherwise the Function does not. This bit must not be set if the 10-Bit Tag Completer Supported bit is clear." "0,1" rbitfld.long 0x24 16. "PCIE_CAP2_10_BIT_TAG_COMP_SUPPORT,10-Bit Tag Completer Supported. If this bit is set the Function supports 10-Bit Tag Completer capability; otherwise the Function does not. For more details see section 2.2.6.2. of PCI Express Base Specification." "0,1" newline rbitfld.long 0x24 13. "PCIE_CAP_TPH_CMPLT_SUPPORT_1,TPH Completer Supported Bit 1." "0,1" rbitfld.long 0x24 12. "PCIE_CAP_TPH_CMPLT_SUPPORT_0,TPH Completer Supported Bit 0. Value of this bit along with TPH Completer Supported Bit 1 indicates Completer support for TPH or Extended TPH. Applicable only to Root Ports and Endpoints. For all other Functions this field.." "0,1" newline bitfld.long 0x24 11. "PCIE_CAP_LTR_SUPP,LTR Mechanism Supported. A value of 1b indicates support for the optional Latency Tolerance Reporting (LTR) mechanism. Root Ports Switches and Endpoints are permitted to implement this capability. For a Multi-Function Device associated.." "0,1" rbitfld.long 0x24 10. "PCIE_CAP_NO_RO_EN_PR2PR_PAR,No RO-enabled PR-PR Passing. If this bit is set the routing element never carries out the passing permitted by Table 2-39 of PCI Express Base Specification entry A2b that is associated with the Relaxed Ordering Attribute.." "0,1" newline rbitfld.long 0x24 9. "PCIE_CAP_128_CAS_CPL_SUPP,128-bit CAS Completer Supported. Applicable to Functions with Memory Space BARs as well as all Root Ports; must be 0b otherwise. This bit must be set to 1b if the Function supports this optional capability. For more details see.." "0,1" rbitfld.long 0x24 8. "PCIE_CAP_64_ATOMIC_CPL_SUPP,64-bit AtomicOp Completer Supported. Applicable to Functions with Memory Space BARs as well as all Root Ports; must be 0b otherwise. Includes FetchAdd Swap and CAS AtomicOps. This bit must be set to 1b if the Function.." "0,1" newline rbitfld.long 0x24 7. "PCIE_CAP_32_ATOMIC_CPL_SUPP,32-bit AtomicOp Completer Supported. Applicable to Functions with Memory Space BARs as well as all Root Ports; must be 0b otherwise. Includes FetchAdd Swap and CAS AtomicOps. This bit must be set to 1b if the Function.." "0,1" rbitfld.long 0x24 6. "PCIE_CAP_ATOMIC_ROUTING_SUPP,AtomicOp Routing Supported. Applicable only to Switch Upstream Ports Switch Downstream Ports and Root Ports; must be 0b for other Function types. This bit must be set to 1b if the Port supports this optional capability. For.." "0,1" newline rbitfld.long 0x24 5. "PCIE_CAP_ARI_FORWARD_SUPPORT,ARI Forwarding Supported. Applicable only to Switch Downstream Ports and Root Ports; must be 0b for other Function types. This bit must be set to 1b if a Switch Downstream Port or Root Port supports this optional capability." "0,1" rbitfld.long 0x24 4. "PCIE_CAP_CPL_TIMEOUT_DISABLE_SUPPORT,Completion Timeout Disable Supported. A value of 1b indicates support for the Completion Timeout Disable mechanism. The Completion Timeout Disable mechanism is required for Endpoints that issue Requests on their own.." "0,1" newline hexmask.long.byte 0x24 0.--3. 1. "PCIE_CAP_CPL_TIMEOUT_RANGE,Completion Timeout Ranges Supported. This field indicates device Function support for the optional Completion Timeout programmability mechanism. This mechanism allows system software to modify the Completion Timeout value. This.." line.long 0x28 "DEVICE_CONTROL2_DEVICE_STATUS2_REG,Device Control 2 and Status 2 Register." bitfld.long 0x28 10. "PCIE_CAP_LTR_EN,LTR Mechanism Enable. When set to 1b this bit enables Upstream Ports to send LTR messages and Downstream Ports to process LTR Messages. For a Multi-Function Device associated with an Upstream Port of a device that implements LTR the bit.." "0,1" rbitfld.long 0x28 5. "PCIE_CAP_ARI_FORWARD_SUPPORT_CS,ARI Forwarding Enable. When set the Downstream Port disables its traditional Device Number field being 0 enforcement when turning a Type 1 Configuration Request into a Type 0 Configuration Request permitting access to.." "0,1" newline bitfld.long 0x28 4. "PCIE_CAP_CPL_TIMEOUT_DISABLE,Completion Timeout Disable. When set this bit disables the Completion Timeout mechanism. This bit is required for all Functions that support the Completion Timeout Disable Capability. Functions that do not support this.." "0,1" hexmask.long.byte 0x28 0.--3. 1. "PCIE_CAP_CPL_TIMEOUT_VALUE,Completion Timeout Value. In device Functions that support Completion Timeout programmability this field allows system software to modify the Completion Timeout value. This field is applicable to Root Ports Endpoints that.." line.long 0x2C "LINK_CAPABILITIES2_REG,Link Capabilities 2 Register." bitfld.long 0x2C 31. "DRS_SUPPORTED,DRS Supported. When set indicates support for the optional Device Readiness Status (DRS) capability. Must be Set in Downstream Ports that support DRS. Must be Set in Downstream Ports that support FRS. For Upstream Ports that support DRS.." "0,1" hexmask.long.byte 0x2C 25.--30. 1. "RSVDP_25,Reserved for future use." newline hexmask.long.word 0x2C 9.--22. 1. "RSVDP_9,Reserved for future use." rbitfld.long 0x2C 8. "PCIE_CAP_CROSS_LINK_SUPPORT,Crosslink Supported. When set to 1b this bit indicates that the associated Port supports crosslinks (for more details see section 4.2.6.3.1 of PCI Express Base Specification). When set to 0b on a Port that supports Link.." "0,1" newline hexmask.long.byte 0x2C 1.--7. 1. "PCIE_CAP_SUPPORT_LINK_SPEED_VECTOR,Supported Link Speeds Vector. This field indicates the supported Link speed(s) of the associated Port. For each bit a value of 1b indicates that the corresponding Link speed is supported; otherwise the Link speed is.." rbitfld.long 0x2C 0. "RSVDP_0,Reserved for future use." "0,1" line.long 0x30 "LINK_CONTROL2_LINK_STATUS2_REG,Link Control 2 and Status 2 Register." bitfld.long 0x30 31. "DRS_MESSAGE_RECEIVED,DRS Message Received. This bit must be set whenever the Port receives a DRS Message. This bit must be cleared in DL_Down. This bit must be implemented in any Downstream Port where the DRS Supported bit is Set in the Link Capabilities.." "0,1" rbitfld.long 0x30 28.--30. "DOWNSTREAM_COMPO_PRESENCE,Downstream Component Presence. This field indicates the presence and DRS status for the Downstream Component if any connected to the Link; defined values are: - 000b: Link Down - Presence Not Determined - 001b: Link Down -.." "0,1,2,3,4,5,6,7" newline rbitfld.long 0x30 26.--27. "RSVDP_26,Reserved for future use." "0,1,2,3" bitfld.long 0x30 21. "PCIE_CAP_LINK_EQ_REQ,Link Equalization Request 8.0 GT/s. This bit is set by hardware to request the 8.0 GT/s Link equalization process to be performed on the Link. For more details see sections 4.2.3 and 4.2.6.4.2 of PCI Express Base Specification. For.." "0,1" newline rbitfld.long 0x30 20. "PCIE_CAP_EQ_CPL_P3,EEqualization 8.0 GT/s Phase 3 Successful. When set to 1b this bit indicates that Phase 3 of the 8.0 GT/s Transmitter Equalization procedure has successfully completed. Details of the Transmitter Equalization process and when this bit.." "0,1" rbitfld.long 0x30 19. "PCIE_CAP_EQ_CPL_P2,Equalization 8.0 GT/s Phase 2 Successful. When set to 1b this bit indicates that Phase 2 of the 8.0 GT/s Transmitter Equalization procedure has successfully completed. Details of the Transmitter Equalization process and when this bit.." "0,1" newline rbitfld.long 0x30 18. "PCIE_CAP_EQ_CPL_P1,Equalization 8.0 GT/s Phase 1 Successful. When set to 1b this bit indicates that Phase 1 of the 8.0 GT/s Transmitter Equalization procedure has successfully completed. Details of the Transmitter Equalization process and when this bit.." "0,1" rbitfld.long 0x30 17. "PCIE_CAP_EQ_CPL,Equalization 8.0 GT/s Complete. When set to 1b this bit indicates that the Transmitter Equalization procedure at the 8.0 GT/s data rate has completed. Details of the Transmitter Equalization process and when this bit needs to be set to.." "0,1" newline rbitfld.long 0x30 16. "PCIE_CAP_CURR_DEEMPHASIS,Current De-emphasis Level. When the Link is operating at 5.0 GT/s speed this bit reflects the level of de-emphasis. Encodings: - 1b: -3.5 dB - 0b: -6 dB The value in this bit is undefined when the Link is not operating at 5.0.." "0,1" hexmask.long.byte 0x30 12.--15. 1. "PCIE_CAP_COMPLIANCE_PRESET,Compliance Preset/De-emphasis. For 8.0 GT/s and higher Data Rate: This field sets the Transmitter Preset in Polling.Compliance state if the entry occurred due to the Enter Compliance bit being 1b. The encodings are defined in.." newline bitfld.long 0x30 11. "PCIE_CAP_COMPLIANCE_SOS,Compliance SOS. When set to 1b the LTSSM is required to send SKP Ordered Sets between sequences when sending the Compliance Pattern or Modified Compliance Pattern. For a Multi-Function Device associated with an Upstream Port the.." "0,1" bitfld.long 0x30 10. "PCIE_CAP_ENTER_MODIFIED_COMPLIANCE,Enter Modified Compliance. When this bit is set to 1b the device transmits Modified Compliance Pattern if the LTSSM enters Polling.Compliance substate. Components that support only the 2.5 GT/s speed are permitted to.." "0,1" newline bitfld.long 0x30 7.--9. "PCIE_CAP_TX_MARGIN,Transmit Margin - This field controls the value of the non-deemphasized voltage level at the Transmitter pins. This field is reset to 000b on entry to the LTSSM Polling.Configuration substate (see Chapter 4 of PCI Express Base.." "0,1,2,3,4,5,6,7" bitfld.long 0x30 6. "PCIE_CAP_SEL_DEEMPHASIS,Selectable De-emphasis. When the Link is operating at 5.0 GT/s speed this bit is used to control the transmit de-emphasis of the link in specific situations. For more details see section 4.2.6 of PCI Express Base Specification." "0,1" newline bitfld.long 0x30 5. "PCIE_CAP_HW_AUTO_SPEED_DISABLE,Hardware Autonomous Speed Disable. When set this bit disables hardware from changing the Link speed for device-specific reasons other than attempting to correct unreliable Link operation by reducing Link speed. Initial.." "0,1" bitfld.long 0x30 4. "PCIE_CAP_ENTER_COMPLIANCE,Enter Compliance. Software is permitted to force a Link to enter Compliance mode (at the speed indicated in the Target Link Speed field and the de-emphasis/preset level indicated by the Compliance Preset/De-emphasis field) by.." "0,1" newline hexmask.long.byte 0x30 0.--3. 1. "PCIE_CAP_TARGET_LINK_SPEED,Target Link Speed. For Downstream Ports this field sets an upper limit on Link operational speed by restricting the values advertised by the Upstream component in its training sequences. The encoded value specifies a bit.." tree.end tree "PF0_AER_CAP (PF Advanced Error Reporting Capability Structure)" group.long (0x0+0x100)++0x1B line.long 0x0 "AER_EXT_CAP_HDR_OFF,Advanced Error Reporting Extended Capability Header. For a description of this standard PCIe register. see the PCI Express Specification." hexmask.long.word 0x0 20.--31. 1. "NEXT_OFFSET,Next Capability Offset. For a description of this standard PCIe register field see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky).." hexmask.long.byte 0x0 16.--19. 1. "CAP_VERSION,Capability Version. For a description of this standard PCIe register field see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else.." newline hexmask.long.word 0x0 0.--15. 1. "CAP_ID,AER Extended Capability ID. For a description of this standard PCIe register field see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else.." line.long 0x4 "UNCORR_ERR_STATUS_OFF,Uncorrectable Error Status Register. For a description of this standard PCIe register. see the PCI Express Specification." hexmask.long.byte 0x4 27.--31. 1. "RSVDP_27,Reserved for future use." rbitfld.long 0x4 23. "RSVDP_23,Reserved for future use." "0,1" newline bitfld.long 0x4 22. "INTERNAL_ERR_STATUS,Uncorrectable Internal Error Status. For a description of this standard PCIe register field see the PCI Express Specification. The controller sets this bit when your application asserts app_err_bus[9]. It does not set this bit when.." "0,1" bitfld.long 0x4 20. "UNSUPPORTED_REQ_ERR_STATUS,Unsupported Request Error Status. For a description of this standard PCIe register field see the PCI Express Specification." "0,1" newline bitfld.long 0x4 19. "ECRC_ERR_STATUS,ECRC Error Status. For a description of this standard PCIe register field see the PCI Express Specification. Note:If CX_ECRC_ENABLE=0 the register field always reads 0." "0,1" bitfld.long 0x4 18. "MALF_TLP_ERR_STATUS,Malformed TLP Status. For a description of this standard PCIe register field see the PCI Express Specification." "0,1" newline bitfld.long 0x4 17. "REC_OVERFLOW_ERR_STATUS,Receiver Overflow Status. For a description of this standard PCIe register field see the PCI Express Specification." "0,1" bitfld.long 0x4 16. "UNEXP_CMPLT_ERR_STATUS,Unexpected Completion Status. For a description of this standard PCIe register field see the PCI Express Specification." "0,1" newline bitfld.long 0x4 15. "CMPLT_ABORT_ERR_STATUS,Completer Abort Status. For a description of this standard PCIe register field see the PCI Express Specification." "0,1" bitfld.long 0x4 14. "CMPLT_TIMEOUT_ERR_STATUS,Completion Timeout Status. For a description of this standard PCIe register field see the PCI Express Specification." "0,1" newline bitfld.long 0x4 13. "FC_PROTOCOL_ERR_STATUS,Flow Control Protocol Error Status. For a description of this standard PCIe register field see the PCI Express Specification." "0,1" bitfld.long 0x4 12. "POIS_TLP_ERR_STATUS,Poisoned TLP Status. For a description of this standard PCIe register field see the PCI Express Specification." "0,1" newline hexmask.long.byte 0x4 6.--11. 1. "RSVDP_6,Reserved for future use." bitfld.long 0x4 5. "SURPRISE_DOWN_ERR_STATUS,Surprise Down Error Status (Optional). For a description of this standard PCIe register field see the PCI Express Specification." "0,1" newline bitfld.long 0x4 4. "DL_PROTOCOL_ERR_STATUS,Data Link Protocol Error Status. For a description of this standard PCIe register field see the PCI Express Specification." "0,1" hexmask.long.byte 0x4 0.--3. 1. "RSVDP_0,Reserved for future use." line.long 0x8 "UNCORR_ERR_MASK_OFF,Uncorrectable Error Mask Register. For a description of this standard PCIe register. see the PCI Express Specification." hexmask.long.byte 0x8 27.--31. 1. "RSVDP_27,Reserved for future use." rbitfld.long 0x8 23. "RSVDP_23,Reserved for future use." "0,1" newline bitfld.long 0x8 22. "INTERNAL_ERR_MASK,Uncorrectable Internal Error Mask (Optional). For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." "0,1" rbitfld.long 0x8 21. "ACS_VIOLATION_MASK,ACS Violation Mask. Setting the ACS Violation Mask bit disables error logging and signaling for ACS Violation errors. The bit is Read-Only Zero for upstream ports when ACS P2P Egress Control Enable is not set. For a description of.." "0,1" newline bitfld.long 0x8 20. "UNSUPPORTED_REQ_ERR_MASK,Unsupported Request Error Mask. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." "0,1" bitfld.long 0x8 19. "ECRC_ERR_MASK,ECRC Error Mask (Optional). For a description of this standard PCIe register field see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W (sticky) Note: This register.." "0,1" newline bitfld.long 0x8 18. "MALF_TLP_ERR_MASK,Malformed TLP Mask. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." "0,1" bitfld.long 0x8 17. "REC_OVERFLOW_ERR_MASK,Receiver Overflow Mask (Optional). For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." "0,1" newline bitfld.long 0x8 16. "UNEXP_CMPLT_ERR_MASK,Unexpected Completion Mask. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." "0,1" bitfld.long 0x8 15. "CMPLT_ABORT_ERR_MASK,Completer Abort Error Mask (Optional). For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." "0,1" newline bitfld.long 0x8 14. "CMPLT_TIMEOUT_ERR_MASK,Completion Timeout Error Mask. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." "0,1" bitfld.long 0x8 13. "FC_PROTOCOL_ERR_MASK,Flow Control Protocol Error Mask. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." "0,1" newline bitfld.long 0x8 12. "POIS_TLP_ERR_MASK,Poisoned TLP Error Mask. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." "0,1" hexmask.long.byte 0x8 6.--11. 1. "RSVDP_6,Reserved for future use." newline rbitfld.long 0x8 5. "SURPRISE_DOWN_ERR_MASK,Surprise Down Error Mask. For a description of this standard PCIe register field see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi:.." "0,1" bitfld.long 0x8 4. "DL_PROTOCOL_ERR_MASK,Data Link Protocol Error Mask. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." "0,1" newline hexmask.long.byte 0x8 0.--3. 1. "RSVDP_0,Reserved for future use." line.long 0xC "UNCORR_ERR_SEV_OFF,Uncorrectable Error Severity Register. For a description of this standard PCIe register. see the PCI Express Specification." hexmask.long.byte 0xC 27.--31. 1. "RSVDP_27,Reserved for future use." rbitfld.long 0xC 24. "ATOMIC_EGRESS_BLOCKED_ERR_SEVERITY,AtomicOp Egress Blocked Severity (Optional). For a description of this standard PCIe register field see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi:.." "0,1" newline rbitfld.long 0xC 23. "RSVDP_23,Reserved for future use." "0,1" bitfld.long 0xC 22. "INTERNAL_ERR_SEVERITY,Uncorrectable Internal Error Severity (Optional). For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." "0,1" newline bitfld.long 0xC 20. "UNSUPPORTED_REQ_ERR_SEVERITY,Unsupported Request Error Severity. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." "0,1" bitfld.long 0xC 19. "ECRC_ERR_SEVERITY,ECRC Error Severity (Optional). For a description of this standard PCIe register field see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W (sticky) Note: This.." "0,1" newline bitfld.long 0xC 18. "MALF_TLP_ERR_SEVERITY,Malformed TLP Severity. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." "0,1" bitfld.long 0xC 17. "REC_OVERFLOW_ERR_SEVERITY,Receiver Overflow Error Severity (Optional). For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." "0,1" newline bitfld.long 0xC 16. "UNEXP_CMPLT_ERR_SEVERITY,Unexpected Completion Error Severity. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." "0,1" bitfld.long 0xC 15. "CMPLT_ABORT_ERR_SEVERITY,Completer Abort Error Severity (Optional). For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." "0,1" newline bitfld.long 0xC 14. "CMPLT_TIMEOUT_ERR_SEVERITY,Completion Timeout Error Severity. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." "0,1" bitfld.long 0xC 13. "FC_PROTOCOL_ERR_SEVERITY,Flow Control Protocol Error Severity (Optional). For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." "0,1" newline bitfld.long 0xC 12. "POIS_TLP_ERR_SEVERITY,Poisoned TLP Severity. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." "0,1" hexmask.long.byte 0xC 6.--11. 1. "RSVDP_6,Reserved for future use." newline rbitfld.long 0xC 5. "SURPRISE_DOWN_ERR_SVRITY,Surprise Down Error Severity (Optional). For a description of this standard PCIe register field see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi:.." "0,1" bitfld.long 0xC 4. "DL_PROTOCOL_ERR_SEVERITY,Data Link Protocol Error Severity. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." "0,1" newline hexmask.long.byte 0xC 0.--3. 1. "RSVDP_0,Reserved for future use." line.long 0x10 "CORR_ERR_STATUS_OFF,Correctable Error Status Register. For a description of this standard PCIe register. see the PCI Express Specification." hexmask.long.word 0x10 16.--31. 1. "RSVDP_16,Reserved for future use." bitfld.long 0x10 15. "HEADER_LOG_OVERFLOW_STATUS,Header Log Overflow Error Status (Optional). For a description of this standard PCIe register field see the PCI Express Specification." "0,1" newline bitfld.long 0x10 14. "CORRECTED_INT_ERR_STATUS,Corrected Internal Error Status (Optional). For a description of this standard PCIe register field see the PCI Express Specification." "0,1" bitfld.long 0x10 13. "ADVISORY_NON_FATAL_ERR_STATUS,Advisory Non-Fatal Error Status. For a description of this standard PCIe register field see the PCI Express Specification." "0,1" newline bitfld.long 0x10 12. "RPL_TIMER_TIMEOUT_STATUS,Replay Timer Timeout Status. For a description of this standard PCIe register field see the PCI Express Specification." "0,1" rbitfld.long 0x10 9.--11. "RSVDP_9,Reserved for future use." "0,1,2,3,4,5,6,7" newline bitfld.long 0x10 8. "REPLAY_NO_ROLEOVER_STATUS,REPLAY_NUM Rollover Status. For a description of this standard PCIe register field see the PCI Express Specification." "0,1" bitfld.long 0x10 7. "BAD_DLLP_STATUS,Bad DLLP Status. For a description of this standard PCIe register field see the PCI Express Specification." "0,1" newline bitfld.long 0x10 6. "BAD_TLP_STATUS,Bad TLP Status. For a description of this standard PCIe register field see the PCI Express Specification." "0,1" hexmask.long.byte 0x10 1.--5. 1. "RSVDP_1,Reserved for future use." newline bitfld.long 0x10 0. "RX_ERR_STATUS,Receiver Error Status (Optional). For a description of this standard PCIe register field see the PCI Express Specification." "0,1" line.long 0x14 "CORR_ERR_MASK_OFF,Correctable Error Mask Register. For a description of this standard PCIe register. see the PCI Express Specification." hexmask.long.word 0x14 16.--31. 1. "RSVDP_16,Reserved for future use." bitfld.long 0x14 15. "HEADER_LOG_OVERFLOW_MASK,Header Log Overflow Error Mask (Optional). For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." "0,1" newline bitfld.long 0x14 14. "CORRECTED_INT_ERR_MASK,Corrected Internal Error Mask (Optional). For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." "0,1" bitfld.long 0x14 13. "ADVISORY_NON_FATAL_ERR_MASK,Advisory Non-Fatal Error Mask. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." "0,1" newline bitfld.long 0x14 12. "RPL_TIMER_TIMEOUT_MASK,Replay Timer Timeout Mask. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." "0,1" rbitfld.long 0x14 9.--11. "RSVDP_9,Reserved for future use." "0,1,2,3,4,5,6,7" newline bitfld.long 0x14 8. "REPLAY_NO_ROLEOVER_MASK,REPLAY_NUM Rollover Mask. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." "0,1" bitfld.long 0x14 7. "BAD_DLLP_MASK,Bad DLLP Mask. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." "0,1" newline bitfld.long 0x14 6. "BAD_TLP_MASK,Bad TLP Mask. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." "0,1" hexmask.long.byte 0x14 1.--5. 1. "RSVDP_1,Reserved for future use." newline bitfld.long 0x14 0. "RX_ERR_MASK,Receiver Error Mask (Optional). For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." "0,1" line.long 0x18 "ADV_ERR_CAP_CTRL_OFF,Advanced Error Capabilities and Control Register. For a description of this standard PCIe register. see the PCI Express Specification." hexmask.long.tbyte 0x18 13.--31. 1. "RSVDP_13,Reserved for future use." rbitfld.long 0x18 12. "CTO_PRFX_HDR_LOG_CAP,TLP Prefix Log Present. For a description of this standard PCIe register field see the PCI Express Specification." "0,1" newline rbitfld.long 0x18 10. "MULTIPLE_HEADER_EN,Multiple Header Recording Enable. For a description of this standard PCIe register field see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R (sticky) Note: This.." "0,1" rbitfld.long 0x18 9. "MULTIPLE_HEADER_CAP,Multiple Header Recording Capable. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." "0,1" newline bitfld.long 0x18 8. "ECRC_CHECK_EN,ECRC Check Enable. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." "0,1" rbitfld.long 0x18 7. "ECRC_CHECK_CAP,ECRC Check Capable. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." "0,1" newline bitfld.long 0x18 6. "ECRC_GEN_EN,ECRC Generation Enable. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." "0,1" rbitfld.long 0x18 5. "ECRC_GEN_CAP,ECRC Generation Capable. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." "0,1" newline hexmask.long.byte 0x18 0.--4. 1. "FIRST_ERR_POINTER,First Error Pointer. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." rgroup.long (0x1C+0x100)++0xF line.long 0x0 "HDR_LOG_0_OFF,Header Log Register 0. For a description of this standard PCIe register. see the PCI Express Specification." hexmask.long.byte 0x0 24.--31. 1. "FIRST_DWORD_FOURTH_BYTE,Byte 3 of Header log register of First 32 bit Data Word. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." hexmask.long.byte 0x0 16.--23. 1. "FIRST_DWORD_THIRD_BYTE,Byte 2 of Header log register of First 32 bit Data Word. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." newline hexmask.long.byte 0x0 8.--15. 1. "FIRST_DWORD_SECOND_BYTE,Byte 1 of Header log register of First 32 bit Data Word. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." hexmask.long.byte 0x0 0.--7. 1. "FIRST_DWORD_FIRST_BYTE,Byte 0 of Header log register of First 32 bit Data Word. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." line.long 0x4 "HDR_LOG_1_OFF,Header Log Register 1. For a description of this standard PCIe register. see the PCI Express Specification." hexmask.long.byte 0x4 24.--31. 1. "SECOND_DWORD_FOURTH_BYTE,Byte 3 of Header log register of Second 32 bit Data Word. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." hexmask.long.byte 0x4 16.--23. 1. "SECOND_DWORD_THIRD_BYTE,Byte 2 of Header log register of Second 32 bit Data Word. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." newline hexmask.long.byte 0x4 8.--15. 1. "SECOND_DWORD_SECOND_BYTE,Byte 1 of Header log register of Second 32 bit Data Word. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." hexmask.long.byte 0x4 0.--7. 1. "SECOND_DWORD_FIRST_BYTE,Byte 0 of Header log register of Second 32 bit Data Word. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." line.long 0x8 "HDR_LOG_2_OFF,Header Log Register 2. For a description of this standard PCIe register. see the PCI Express Specification." hexmask.long.byte 0x8 24.--31. 1. "THIRD_DWORD_FOURTH_BYTE,Byte 3 of Header log register of Third 32 bit Data Word. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." hexmask.long.byte 0x8 16.--23. 1. "THIRD_DWORD_THIRD_BYTE,Byte 2 of Header log register of Third 32 bit Data Word. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." newline hexmask.long.byte 0x8 8.--15. 1. "THIRD_DWORD_SECOND_BYTE,Byte 1 of Header log register of Third 32 bit Data Word. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." hexmask.long.byte 0x8 0.--7. 1. "THIRD_DWORD_FIRST_BYTE,Byte 0 of Header log register of Third 32 bit Data Word. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." line.long 0xC "HDR_LOG_3_OFF,Header Log Register 3. For a description of this standard PCIe register. see the PCI Express Specification." hexmask.long.byte 0xC 24.--31. 1. "FOURTH_DWORD_FOURTH_BYTE,Byte 3 of Header log register of Fourth 32 bit Data Word. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." hexmask.long.byte 0xC 16.--23. 1. "FOURTH_DWORD_THIRD_BYTE,Byte 2 of Header log register of Fourth 32 bit Data Word. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." newline hexmask.long.byte 0xC 8.--15. 1. "FOURTH_DWORD_SECOND_BYTE,Byte 1 of Header log register of Fourth 32 bit Data Word. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." hexmask.long.byte 0xC 0.--7. 1. "FOURTH_DWORD_FIRST_BYTE,Byte 0 of Header log register of Fourth 32 bit Data Word. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." group.long (0x2C+0x100)++0x7 line.long 0x0 "ROOT_ERR_CMD_OFF,Root Error Command Register. For a description of this standard PCIe register. see the PCI Express Specification." hexmask.long 0x0 3.--31. 1. "RSVDP_3,Reserved for future use." bitfld.long 0x0 2. "FATAL_ERR_REPORTING_EN,Fatal Error Reporting Enable. For a description of this standard PCIe register field see the PCI Express Specification." "0,1" newline bitfld.long 0x0 1. "NON_FATAL_ERR_REPORTING_EN,Non-Fatal Error Reporting Enable. For a description of this standard PCIe register field see the PCI Express Specification." "0,1" bitfld.long 0x0 0. "CORR_ERR_REPORTING_EN,Correctable Error Reporting Enable. For a description of this standard PCIe register field see the PCI Express Specification." "0,1" line.long 0x4 "ROOT_ERR_STATUS_OFF,Root Error Status Register. For a description of this standard PCIe register. see the PCI Express Specification." hexmask.long.byte 0x4 27.--31. 1. "ADV_ERR_INT_MSG_NUM,Advanced Error Interrupt Message Number. For a description of this standard PCIe register field see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN.." hexmask.long.tbyte 0x4 7.--26. 1. "RSVDP_7,Reserved for future use." newline bitfld.long 0x4 6. "FATAL_ERR_MSG_RX,One or more Fatal Error Messages Received. For a description of this standard PCIe register field see the PCI Express Specification." "0,1" bitfld.long 0x4 5. "NON_FATAL_ERR_MSG_RX,One or more Non-Fatal Error Messages Received. For a description of this standard PCIe register field see the PCI Express Specification." "0,1" newline bitfld.long 0x4 4. "FIRST_UNCORR_FATAL,First Uncorrectable Error is Fatal. For a description of this standard PCIe register field see the PCI Express Specification." "0,1" bitfld.long 0x4 3. "MUL_ERR_FATAL_NON_FATAL_RX,Multiple Fatal or Non-Fatal Errors Received. For a description of this standard PCIe register field see the PCI Express Specification." "0,1" newline bitfld.long 0x4 2. "ERR_FATAL_NON_FATAL_RX,Fatal or Non-Fatal Error Received. For a description of this standard PCIe register field see the PCI Express Specification." "0,1" bitfld.long 0x4 1. "MUL_ERR_COR_RX,Multiple Correctable Errors Received. For a description of this standard PCIe register field see the PCI Express Specification." "0,1" newline bitfld.long 0x4 0. "ERR_COR_RX,Correctable Error Received. For a description of this standard PCIe register field see the PCI Express Specification." "0,1" rgroup.long (0x34+0x100)++0x13 line.long 0x0 "ERR_SRC_ID_OFF,Error Source Identification Register. For a description of this standard PCIe register. see the PCI Express Specification." hexmask.long.word 0x0 16.--31. 1. "ERR_FATAL_NON_FATAL_SOURCE_ID,Source of Fatal/Non-Fatal Error. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." hexmask.long.word 0x0 0.--15. 1. "ERR_COR_SOURCE_ID,Source of Correctable Error. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." line.long 0x4 "TLP_PREFIX_LOG_1_OFF,TLP Prefix Log Register 1. For a description of this standard PCIe register. see the PCI Express Specification." hexmask.long.byte 0x4 24.--31. 1. "CFG_TLP_PFX_LOG_1_FOURTH_BYTE,Byte 3 of Error TLP Prefix Log 1. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." hexmask.long.byte 0x4 16.--23. 1. "CFG_TLP_PFX_LOG_1_THIRD_BYTE,Byte 2 of Error TLP Prefix Log 1. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." newline hexmask.long.byte 0x4 8.--15. 1. "CFG_TLP_PFX_LOG_1_SECOND_BYTE,Byte 1 of Error TLP Prefix Log 1. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." hexmask.long.byte 0x4 0.--7. 1. "CFG_TLP_PFX_LOG_1_FIRST_BYTE,Byte 0 of Error TLP Prefix Log 1. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." line.long 0x8 "TLP_PREFIX_LOG_2_OFF,TLP Prefix Log Register 2. For a description of this standard PCIe register. see the PCI Express Specification." hexmask.long.byte 0x8 24.--31. 1. "CFG_TLP_PFX_LOG_2_FOURTH_BYTE,Byte 3 Error TLP Prefix Log 2. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." hexmask.long.byte 0x8 16.--23. 1. "CFG_TLP_PFX_LOG_2_THIRD_BYTE,Byte 2 Error TLP Prefix Log 2. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." newline hexmask.long.byte 0x8 8.--15. 1. "CFG_TLP_PFX_LOG_2_SECOND_BYTE,Byte 1 Error TLP Prefix Log 2. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." hexmask.long.byte 0x8 0.--7. 1. "CFG_TLP_PFX_LOG_2_FIRST_BYTE,Byte 0 Error TLP Prefix Log 2. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." line.long 0xC "TLP_PREFIX_LOG_3_OFF,TLP Prefix Log Register 3. For a description of this standard PCIe register. see the PCI Express Specification." hexmask.long.byte 0xC 24.--31. 1. "CFG_TLP_PFX_LOG_3_FOURTH_BYTE,Byte 3 Error TLP Prefix Log 3. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." hexmask.long.byte 0xC 16.--23. 1. "CFG_TLP_PFX_LOG_3_THIRD_BYTE,Byte 2 Error TLP Prefix Log 3. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." newline hexmask.long.byte 0xC 8.--15. 1. "CFG_TLP_PFX_LOG_3_SECOND_BYTE,Byte 1 Error TLP Prefix Log 3. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." hexmask.long.byte 0xC 0.--7. 1. "CFG_TLP_PFX_LOG_3_FIRST_BYTE,Byte 0 Error TLP Prefix Log 3. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." line.long 0x10 "TLP_PREFIX_LOG_4_OFF,TLP Prefix Log Register 4. For a description of this standard PCIe register. see the PCI Express Specification." hexmask.long.byte 0x10 24.--31. 1. "CFG_TLP_PFX_LOG_4_FOURTH_BYTE,Byte 3 Error TLP Prefix Log 4. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." hexmask.long.byte 0x10 16.--23. 1. "CFG_TLP_PFX_LOG_4_THIRD_BYTE,Byte 2 Error TLP Prefix Log 4. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." newline hexmask.long.byte 0x10 8.--15. 1. "CFG_TLP_PFX_LOG_4_SECOND_BYTE,Byte 1 Error TLP Prefix Log 4. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." hexmask.long.byte 0x10 0.--7. 1. "CFG_TLP_PFX_LOG_4_FIRST_BYTE,Byte 0 Error TLP Prefix Log 4. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." tree.end tree "PF0_MSI_CAP (PF MSI Capability Structure)" group.long (0x0+0x50)++0x13 line.long 0x0 "PCI_MSI_CAP_ID_NEXT_CTRL_REG,MSI Capability Header and Message Control Register." hexmask.long.byte 0x0 27.--31. 1. "RSVDP_27,Reserved for future use." bitfld.long 0x0 26. "PCI_MSI_EXT_DATA_EN,Extended Message Data Enable. - If set the function is enabled to provide Extended Message Data. - If clear the function is not enabled to provide Extended Message Data. Note: The access attributes of this field are as follows: -.." "0,1" bitfld.long 0x0 25. "PCI_MSI_EXT_DATA_CAP,Extended Message Data Capable. - If set the function is capable of providing Extended Message Data. - If clear the function does not support providing Extended Message Data. Note: The access attributes of this field are as follows:.." "0,1" newline rbitfld.long 0x0 24. "PCI_PVM_SUPPORT,Per-Vector Masking Capable. - If set the function supports MSI Per-Vector Masking. - If clear the function does not support MSI Per-Vector Masking. This bit must be set if the function is a PF or VF within an SR-IOV Device." "0,1" bitfld.long 0x0 23. "PCI_MSI_64_BIT_ADDR_CAP,64 bit address capable. - If set the function is capable of sending a 64-bit message address. - If clear the function is not capable of sending a 64-bit message address. This bit must be set if the function is a PCI Express.." "0,1" bitfld.long 0x0 20.--22. "PCI_MSI_MULTIPLE_MSG_EN,Multiple Message Enable. Software writes to this field to indicate the number of allocated vectors (equal to or less than the number of requested vectors). The number of allocated vectors is aligned to a power of two. If a.." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 17.--19. "PCI_MSI_MULTIPLE_MSG_CAP,Multiple Message Capable. System software reads this field to determine the number of requested vectors. The number of requested vectors must be aligned to a power of two (if a function requires three vectors it requests four by.." "0,1,2,3,4,5,6,7" bitfld.long 0x0 16. "PCI_MSI_ENABLE,MSI Enable. - If set and the MSI-X Enable bit in the MSI-X Message Control register is clear the function is permitted to use MSI to request service and is prohibited from using INTx interrupts. System configuration software sets this bit.." "0,1" hexmask.long.byte 0x0 8.--15. 1. "PCI_MSI_CAP_NEXT_OFFSET,Next Capability Pointer. This field contains the offset to the next PCI Capability structure or 00h if no other items exist in the linked list of Capabilities. Note: The access attributes of this field are as follows: - Wire: No.." newline hexmask.long.byte 0x0 0.--7. 1. "PCI_MSI_CAP_ID,Capability ID. Indicates the MSI Capability structure. This field returns a Capability ID of 05h indicating that this is an MSI Capability structure." line.long 0x4 "MSI_CAP_OFF_04H_REG,Message Address Register for MSI (Offset 04h)." hexmask.long 0x4 2.--31. 1. "PCI_MSI_CAP_OFF_04H,Message Address - System-specified message address. If the Message Enable bit (bit 16 of the PCI_MSI_CAP_ID_NEXT_CTRL_REG register) is set the contents of this field specify the DWORD-aligned address (Address[31:02]) for the MSI.." rbitfld.long 0x4 0.--1. "RSVDP_0,Reserved for future use." "0,1,2,3" line.long 0x8 "MSI_CAP_OFF_08H_REG,For a function that supports a 32-bit message address. - bits[31:16] of this register represent the Extended Message Data. and - bits[15:0] of this register represent the Message Data For a function that supports a 64-bit message.." hexmask.long.word 0x8 16.--31. 1. "PCI_MSI_CAP_OFF_0AH,For a function that supports a 32-bit message address this field contains Extended Message Data (System-specified message data). For the MSI Capability structures without per-vector masking it must be implemented if the Extended.." hexmask.long.word 0x8 0.--15. 1. "PCI_MSI_CAP_OFF_08H,For a function that supports a 32-bit message address this field contains Message Data (System-specified message data). If the Message Enable bit (bit 16 of the PCI_MSI_CAP_ID_NEXT_CTRL_REG) is set the function sends a DWORD Memory.." line.long 0xC "MSI_CAP_OFF_0CH_REG,For a function that supports a 32-bit message address. this register contains the Mask Bits when the Per-Vector Masking Capable bit (bit 24 of PCI_MSI_CAP_ID_NEXT_CTRL_REG) is set. For a function that supports a 64-bit message.." hexmask.long.word 0xC 16.--31. 1. "PCI_MSI_CAP_OFF_0EH,For a function that supports a 32-bit message address this field contains the upper Mask Bits when the Per Vector Masking Capable bit (PCI_MSI_CAP_ID_NEXT_CTRL_REG.PCI_PVM_SUPPORT) is set. For a function that supports a 64-bit.." hexmask.long.word 0xC 0.--15. 1. "PCI_MSI_CAP_OFF_0CH,For a function that supports a 32-bit message address this field contains the lower Mask Bits when the Per Vector Masking Capable bit (PCI_MSI_CAP_ID_NEXT_CTRL_REG.PCI_PVM_SUPPORT) is set. For a function that supports a 64-bit.." line.long 0x10 "MSI_CAP_OFF_10H_REG,For a function that supports a 32-bit message address. this register contains the Pending Bits when the Per-Vector Masking Capable bit (bit 24 of PCI_MSI_CAP_ID_NEXT_CTRL_REG) is set. For a function that supports a 64-bit message.." hexmask.long 0x10 0.--31. 1. "PCI_MSI_CAP_OFF_10H,Used for MSI when the Per Vector Masking Capable bit (PCI_MSI_CAP_ID_NEXT_CTRL_REG.PCI_PVM_SUPPORT) is set. For 32-bit contains Pending Bits. For 64-bit contains Mask Bits. For a description of this standard PCIe register field see.." rgroup.long (0x14+0x50)++0x3 line.long 0x0 "MSI_CAP_OFF_14H_REG,Pending Bits Register for MSI. This register is used for a function that supports a 64-bit message address when the Per-Vector Masking Capable bit (bit 24 of PCI_MSI_CAP_ID_NEXT_CTRL_REG) is set." hexmask.long 0x0 0.--31. 1. "PCI_MSI_CAP_OFF_14H,Pending Bits. For each pending bit that is set the function has a pending associated message." tree.end tree "PF0_DMA_CAP (DMA Port Logic Structure)" group.long (0x0+0xC8000)++0x3 line.long 0x0 "DMA_CTRL_DATA_ARB_PRIOR_OFF,DMA Arbitration Scheme for TRGT1 Interface. This register is used to control traffic priorities among various sources that are delivered to your application through TRGT1 where 0x0 represents the highest priority. - Non-DMA Rx.." hexmask.long.tbyte 0x0 12.--31. 1. "RSVDP_12,Reserved for future use." bitfld.long 0x0 9.--11. "RDBUFF_TRGT_WEIGHT,DMA Read Channel MWr Requests. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 6.--8. "RD_CTRL_TRGT_WEIGHT,DMA Read Channel MRd Requests. For LL element/descriptor access. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" "0,1,2,3,4,5,6,7" bitfld.long 0x0 3.--5. "WR_CTRL_TRGT_WEIGHT,DMA Write Channel MRd Requests. For DMA data requests and LL element/descriptor access. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 0.--2. "RTRGT1_WEIGHT,Non-DMA Rx Requests. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" "0,1,2,3,4,5,6,7" group.long (0x8+0xC8000)++0xB line.long 0x0 "DMA_CTRL_OFF,DMA Number of Channels Register." hexmask.long.byte 0x0 26.--31. 1. "RSVDP_26,Reserved for future use." bitfld.long 0x0 25. "DIS_C2W_CACHE_RD,Disable DMA Read Channels 'completion to memory write' context cache pre-fetch function. Note: For internal debugging only. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" "0,1" newline bitfld.long 0x0 24. "DIS_C2W_CACHE_WR,Disable DMA Write Channels 'completion to memory write' context cache pre-fetch function. Note: For internal debugging only. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" "0,1" hexmask.long.byte 0x0 20.--23. 1. "RSVDP_20,Reserved for future use." newline hexmask.long.byte 0x0 16.--19. 1. "NUM_DMA_RD_CHAN,Number of Read Channels. You can read this register to determine the number of read channels the DMA controller has been configured to support." hexmask.long.word 0x0 4.--15. 1. "RSVDP_4,Reserved for future use." newline hexmask.long.byte 0x0 0.--3. 1. "NUM_DMA_WR_CHAN,Number of Write Channels. You can read this register to determine the number of write channels the DMA controller has been configured to support." line.long 0x4 "DMA_WRITE_ENGINE_EN_OFF,DMA Write Engine Enable Register." hexmask.long.byte 0x4 24.--31. 1. "RSVDP_24,Reserved for future use." bitfld.long 0x4 23. "DMA_WRITE_ENGINE_EN_HSHAKE_CH7,Enable Handshake for DMA Write Engine Channel 7. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" "0,1" newline bitfld.long 0x4 22. "DMA_WRITE_ENGINE_EN_HSHAKE_CH6,Enable Handshake for DMA Write Engine Channel 6. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" "0,1" bitfld.long 0x4 21. "DMA_WRITE_ENGINE_EN_HSHAKE_CH5,Enable Handshake for DMA Write Engine Channel 5. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" "0,1" newline bitfld.long 0x4 20. "DMA_WRITE_ENGINE_EN_HSHAKE_CH4,Enable Handshake for DMA Write Engine Channel 4. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" "0,1" bitfld.long 0x4 19. "DMA_WRITE_ENGINE_EN_HSHAKE_CH3,Enable Handshake for DMA Write Engine Channel 3. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" "0,1" newline bitfld.long 0x4 18. "DMA_WRITE_ENGINE_EN_HSHAKE_CH2,Enable Handshake for DMA Write Engine Channel 2. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" "0,1" bitfld.long 0x4 17. "DMA_WRITE_ENGINE_EN_HSHAKE_CH1,Enable Handshake for DMA Write Engine Channel 1. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" "0,1" newline bitfld.long 0x4 16. "DMA_WRITE_ENGINE_EN_HSHAKE_CH0,Enable Handshake for DMA Write Engine Channel 0. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" "0,1" hexmask.long.word 0x4 1.--15. 1. "RSVDP_1,Reserved for future use." newline bitfld.long 0x4 0. "DMA_WRITE_ENGINE,DMA Write Engine Enable. - 1: Enable - 0: Disable (Soft Reset) For normal operation you must initially set this bit to '1' before any other software setup actions. You do not need to toggle or rewrite to this bit during normal.." "Disable,Enable" line.long 0x8 "DMA_WRITE_DOORBELL_OFF,DMA Write Doorbell Register." bitfld.long 0x8 31. "WR_STOP,Stop. Set in conjunction with the Doorbell Number field. The DMA write channel stops issuing requests sets the channel status to 'Stopped' and asserts the 'Abort' interrupt if it is enabled. Before setting the Stop bit you must read the.." "0,1" hexmask.long 0x8 3.--30. 1. "RSVDP_3,Reserved for future use." newline bitfld.long 0x8 0.--2. "WR_DOORBELL_NUM,Doorbell Number. You must write the channel number to this register to start the DMA write transfer for that channel. The DMA detects a write to this register field even if the value of this field does not change. You do not need to.." "0,1,2,3,4,5,6,7" group.long (0x18+0xC8000)++0x7 line.long 0x0 "DMA_WRITE_CHANNEL_ARB_WEIGHT_LOW_OFF,DMA Write Engine Channel Arbitration Weight Low Register. The 5-bit channel weight (for write channels 0-3) specifies the maximum number of TLP requests that the DMA can issue for that channel before it must return to.." hexmask.long.word 0x0 20.--31. 1. "RSVDP_20,Reserved for future use." hexmask.long.byte 0x0 15.--19. 1. "WRITE_CHANNEL3_WEIGHT,Channel 3 Weight. The weight is initialized by software before ringing the doorbell. The value is used by the channel weighted round robin arbiter to select the next channel read request. A value of '0' means that one TLP is issued.." newline hexmask.long.byte 0x0 10.--14. 1. "WRITE_CHANNEL2_WEIGHT,Channel 2 Weight. The weight is initialized by software before ringing the doorbell. The value is used by the channel weighted round robin arbiter to select the next channel read request. A value of '0' means that one TLP is issued.." hexmask.long.byte 0x0 5.--9. 1. "WRITE_CHANNEL1_WEIGHT,Channel 1 Weight. The weight is initialized by software before ringing the doorbell. The value is used by the channel weighted round robin arbiter to select the next channel read request. A value of '0' means that one TLP is issued.." newline hexmask.long.byte 0x0 0.--4. 1. "WRITE_CHANNEL0_WEIGHT,Channel 0 Weight. The weight is initialized by software before ringing the doorbell. The value is used by the channel weighted round robin arbiter to select the next channel read request. A value of '0' means that one TLP is issued.." line.long 0x4 "DMA_WRITE_CHANNEL_ARB_WEIGHT_HIGH_OFF,DMA Write Engine Channel Arbitration Weight High Register. The 5-bit channel weight (for write channels 4-7) specifies the maximum number of TLP requests that the DMA can issue for that channel before it must return.." hexmask.long.word 0x4 20.--31. 1. "RSVDP_20,Reserved for future use." hexmask.long.byte 0x4 15.--19. 1. "WRITE_CHANNEL7_WEIGHT,Channel 7 Weight. The weight is initialized by software before ringing the doorbell. The value is used by the channel weighted round robin arbiter to select the next channel read request. A value of '0' means that one TLP is issued.." newline hexmask.long.byte 0x4 10.--14. 1. "WRITE_CHANNEL6_WEIGHT,Channel 6 Weight. The weight is initialized by software before ringing the doorbell. The value is used by the channel weighted round robin arbiter to select the next channel read request. A value of '0' means that one TLP is issued.." hexmask.long.byte 0x4 5.--9. 1. "WRITE_CHANNEL5_WEIGHT,Channel 5 Weight. The weight is initialized by software before ringing the doorbell. The value is used by the channel weighted round robin arbiter to select the next channel read request. A value of '0' means that one TLP is issued.." newline hexmask.long.byte 0x4 0.--4. 1. "WRITE_CHANNEL4_WEIGHT,Channel 4 Weight. The weight is initialized by software before ringing the doorbell. The value is used by the channel weighted round robin arbiter to select the next channel read request. A value of '0' means that one TLP is issued.." group.long (0x2C+0xC8000)++0x7 line.long 0x0 "DMA_READ_ENGINE_EN_OFF,DMA Read Engine Enable Register." hexmask.long.byte 0x0 24.--31. 1. "RSVDP_24,Reserved for future use." bitfld.long 0x0 23. "DMA_READ_ENGINE_EN_HSHAKE_CH7,Enable Handshake for DMA Read Engine Channel 7. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" "0,1" newline bitfld.long 0x0 22. "DMA_READ_ENGINE_EN_HSHAKE_CH6,Enable Handshake for DMA Read Engine Channel 6. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" "0,1" bitfld.long 0x0 21. "DMA_READ_ENGINE_EN_HSHAKE_CH5,Enable Handshake for DMA Read Engine Channel 5. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" "0,1" newline bitfld.long 0x0 20. "DMA_READ_ENGINE_EN_HSHAKE_CH4,Enable Handshake for DMA Read Engine Channel 4. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" "0,1" bitfld.long 0x0 19. "DMA_READ_ENGINE_EN_HSHAKE_CH3,Enable Handshake for DMA Read Engine Channel 3. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" "0,1" newline bitfld.long 0x0 18. "DMA_READ_ENGINE_EN_HSHAKE_CH2,Enable Handshake for DMA Read Engine Channel 2. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" "0,1" bitfld.long 0x0 17. "DMA_READ_ENGINE_EN_HSHAKE_CH1,Enable Handshake for DMA Read Engine Channel 1. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" "0,1" newline bitfld.long 0x0 16. "DMA_READ_ENGINE_EN_HSHAKE_CH0,Enable Handshake for DMA Read Engine Channel 0. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" "0,1" hexmask.long.word 0x0 1.--15. 1. "RSVDP_1,Reserved for future use." newline bitfld.long 0x0 0. "DMA_READ_ENGINE,DMA Read Engine Enable. - 1: Enable - 0: Disable (Soft Reset) For normal operation you must initially set this bit to '1' before any other software setup actions. You do not need to toggle or rewrite to this bit during normal operation." "Disable,Enable" line.long 0x4 "DMA_READ_DOORBELL_OFF,DMA Read Doorbell Register." bitfld.long 0x4 31. "RD_STOP,Stop. Set in conjunction with the Doorbell Number field. The DMA read channel stops issuing requests sets the channel status to 'Stopped' and asserts the 'Abort' interrupt if it is enabled. Before setting the Stop bit you must read the channel.." "0,1" hexmask.long 0x4 3.--30. 1. "RSVDP_3,Reserved for future use." newline bitfld.long 0x4 0.--2. "RD_DOORBELL_NUM,Doorbell Number. You must write 0x0 to this register to start the DMA read transfer for that channel. The DMA detects a write to this register field even if the value of this field does not change. The range of this field is 0x0 to 0x7.." "0,1,2,3,4,5,6,7" group.long (0x38+0xC8000)++0x7 line.long 0x0 "DMA_READ_CHANNEL_ARB_WEIGHT_LOW_OFF,DMA Read Engine Channel Arbitration Weight Low Register. The 5-bit channel weight (for read channels 0-3) specifies the maximum number of TLP requests that the DMA can issue for that channel before it must return to.." hexmask.long.word 0x0 20.--31. 1. "RSVDP_20,Reserved for future use." hexmask.long.byte 0x0 15.--19. 1. "READ_CHANNEL3_WEIGHT,Channel 3 Weight. The weight is initialized by software before ringing the doorbell. The value is used by the channel weighted round robin arbiter to select the next channel read request. Note: The access attributes of this field are.." newline hexmask.long.byte 0x0 10.--14. 1. "READ_CHANNEL2_WEIGHT,Channel 2 Weight. The weight is initialized by software before ringing the doorbell. The value is used by the channel weighted round robin arbiter to select the next channel read request. Note: The access attributes of this field are.." hexmask.long.byte 0x0 5.--9. 1. "READ_CHANNEL1_WEIGHT,Channel 1 Weight. The weight is initialized by software before ringing the doorbell. The value is used by the channel weighted round robin arbiter to select the next channel read request. Note: The access attributes of this field are.." newline hexmask.long.byte 0x0 0.--4. 1. "READ_CHANNEL0_WEIGHT,Channel 0 Weight. The weight is initialized by software before ringing the doorbell. The value is used by the channel weighted round robin arbiter to select the next channel read request. Note: The access attributes of this field are.." line.long 0x4 "DMA_READ_CHANNEL_ARB_WEIGHT_HIGH_OFF,DMA Read Engine Channel Arbitration Weight High Register. The 5-bit channel weight (for read channels 4-7) specifies the maximum number of TLP requests that the DMA can issue for that channel before it must return to.." hexmask.long.word 0x4 20.--31. 1. "RSVDP_20,Reserved for future use." hexmask.long.byte 0x4 15.--19. 1. "READ_CHANNEL7_WEIGHT,Channel 7 Weight. The weight is initialized by software before ringing the doorbell. The value is used by the channel weighted round robin arbiter to select the next channel read request. Note: The access attributes of this field are.." newline hexmask.long.byte 0x4 10.--14. 1. "READ_CHANNEL6_WEIGHT,Channel 6 Weight. The weight is initialized by software before ringing the doorbell. The value is used by the channel weighted round robin arbiter to select the next channel read request. Note: The access attributes of this field are.." hexmask.long.byte 0x4 5.--9. 1. "READ_CHANNEL5_WEIGHT,Channel 5 Weight. The weight is initialized by software before ringing the doorbell. The value is used by the channel weighted round robin arbiter to select the next channel read request. Note: The access attributes of this field are.." newline hexmask.long.byte 0x4 0.--4. 1. "READ_CHANNEL4_WEIGHT,Channel 4 Weight. The weight is initialized by software before ringing the doorbell. The value is used by the channel weighted round robin arbiter to select the next channel read request. Note: The access attributes of this field are.." group.long (0x4C+0xC8000)++0x3 line.long 0x0 "DMA_WRITE_INT_STATUS_OFF,DMA Write Interrupt Status Register." hexmask.long.byte 0x0 24.--31. 1. "RSVDP_24,Reserved for future use." hexmask.long.byte 0x0 16.--23. 1. "WR_ABORT_INT_STATUS,Abort Interrupt Status. The DMA write channel has detected an error or you manually stopped the transfer as described in 'Error Handling Assistance by Remote Software'. Each bit corresponds to a DMA channel. Bit [0] corresponds to.." newline hexmask.long.byte 0x0 8.--15. 1. "RSVDP_8,Reserved for future use." hexmask.long.byte 0x0 0.--7. 1. "WR_DONE_INT_STATUS,Done Interrupt Status. The DMA write channel has successfully completed the DMA transfer. For more details see 'Interrupts and Error Handling'. Each bit corresponds to a DMA channel. Bit [0] corresponds to channel 0. - Enabling: For.." group.long (0x54+0xC8000)++0x7 line.long 0x0 "DMA_WRITE_INT_MASK_OFF,DMA Write Interrupt Mask Register." hexmask.long.byte 0x0 24.--31. 1. "RSVDP_24,Reserved for future use." hexmask.long.byte 0x0 16.--23. 1. "WR_ABORT_INT_MASK,Abort Interrupt Mask. Prevents the Abort interrupt status field in the DMA write interrupt status register from asserting the edma_int output. Each bit corresponds to a DMA channel. Bit [0] corresponds to channel 0. Note: The access.." newline hexmask.long.byte 0x0 8.--15. 1. "RSVDP_8,Reserved for future use." hexmask.long.byte 0x0 0.--7. 1. "WR_DONE_INT_MASK,Done Interrupt Mask. Prevents the Done interrupt status field in the DMA write interrupt status register from asserting the edma_int output. Each bit corresponds to a DMA channel. Bit [0] corresponds to channel 0. Note: The access.." line.long 0x4 "DMA_WRITE_INT_CLEAR_OFF,DMA Write Interrupt Clear Register." hexmask.long.byte 0x4 24.--31. 1. "RSVDP_24,Reserved for future use." hexmask.long.byte 0x4 16.--23. 1. "WR_ABORT_INT_CLEAR,Abort Interrupt Clear. You must write a 1'b1 to clear the corresponding bit in the Abort interrupt status field of the DMA write interrupt status register. Each bit corresponds to a DMA channel. Bit [0] corresponds to channel 0. Note:.." newline hexmask.long.byte 0x4 8.--15. 1. "RSVDP_8,Reserved for future use." hexmask.long.byte 0x4 0.--7. 1. "WR_DONE_INT_CLEAR,Done Interrupt Clear. You must write a 1'b1 to clear the corresponding bit in the Done interrupt status field of the DMA write interrupt status register. Each bit corresponds to a DMA channel. Bit [0] corresponds to channel 0. Note:.." rgroup.long (0x5C+0xC8000)++0x3 line.long 0x0 "DMA_WRITE_ERR_STATUS_OFF,DMA Write Error Status Register" hexmask.long.byte 0x0 24.--31. 1. "RSVDP_24,Reserved for future use." hexmask.long.byte 0x0 16.--23. 1. "LINKLIST_ELEMENT_FETCH_ERR_DETECT,Linked List Element Fetch Error Detected. The DMA write channel has received an error response from the AXI bus (or TRGT1 interface when the AXI Bridge is not used) while reading a linked list element from local memory." newline hexmask.long.byte 0x0 8.--15. 1. "RSVDP_8,Reserved for future use." hexmask.long.byte 0x0 0.--7. 1. "APP_READ_ERR_DETECT,Application Read Error Detected. The DMA write channel has received an error response from the AXI bus (or TRGT1 interface when the AXI Bridge is not used) while reading data from it. Each bit corresponds to a DMA channel. Bit [0].." group.long (0x60+0xC8000)++0x1F line.long 0x0 "DMA_WRITE_DONE_IMWR_LOW_OFF,DMA Write Done IMWr Address Low Register." hexmask.long 0x0 0.--31. 1. "DMA_WRITE_DONE_LOW_REG,The DMA uses this field to generate bits [31:0] of the address field for the Done IMWr TLP. Bits [1:0] must be '00' as this address must be dword aligned. Note: The access attributes of this field are as follows: - Wire: No access." line.long 0x4 "DMA_WRITE_DONE_IMWR_HIGH_OFF,DMA Write Done IMWr Interrupt Address High Register." hexmask.long 0x4 0.--31. 1. "DMA_WRITE_DONE_HIGH_REG,The DMA uses this field to generate bits [63:32] of the address field for the Done IMWr TLP. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" line.long 0x8 "DMA_WRITE_ABORT_IMWR_LOW_OFF,DMA Write Abort IMWr Address Low Register." hexmask.long 0x8 0.--31. 1. "DMA_WRITE_ABORT_LOW_REG,The DMA uses this field to generate bits [31:0] of the address field for the Abort IMWr TLP it generates. Bits [1:0] must be '00' as this address must be dword aligned. Note: The access attributes of this field are as follows: -.." line.long 0xC "DMA_WRITE_ABORT_IMWR_HIGH_OFF,DMA Write Abort IMWr Address High Register." hexmask.long 0xC 0.--31. 1. "DMA_WRITE_ABORT_HIGH_REG,The DMA uses this field to generate bits [63:32] of the address field for the Abort IMWr TLP. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" line.long 0x10 "DMA_WRITE_CH01_IMWR_DATA_OFF,DMA Write Channel 1 and 0 IMWr Data Register." hexmask.long.word 0x10 16.--31. 1. "WR_CHANNEL_1_DATA,The DMA uses this field to generate the data field for the Done or Abort IMWr TLPs it generates for write channel 1. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" hexmask.long.word 0x10 0.--15. 1. "WR_CHANNEL_0_DATA,The DMA uses this field to generate the data field for the Done or Abort IMWr TLPs it generates for write channel 0. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" line.long 0x14 "DMA_WRITE_CH23_IMWR_DATA_OFF,DMA Write Channel 3 and 2 IMWr Data Register." hexmask.long.word 0x14 16.--31. 1. "WR_CHANNEL_3_DATA,The DMA uses this field to generate the data field for the Done or Abort IMWr TLPs it generates for write channel 3. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" hexmask.long.word 0x14 0.--15. 1. "WR_CHANNEL_2_DATA,The DMA uses this field to generate the data field for the Done or Abort IMWr TLPs it generates for write channel 2. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" line.long 0x18 "DMA_WRITE_CH45_IMWR_DATA_OFF,DMA Write Channel 5 and 4 IMWr Data Register." hexmask.long.word 0x18 16.--31. 1. "WR_CHANNEL_5_DATA,The DMA uses this field to generate the data field for the Done or Abort IMWr TLPs it generates for write channel 5. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" hexmask.long.word 0x18 0.--15. 1. "WR_CHANNEL_4_DATA,The DMA uses this field to generate the data field for the Done or Abort IMWr TLPs it generates for write channel 4. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" line.long 0x1C "DMA_WRITE_CH67_IMWR_DATA_OFF,DMA Write Channel 7 and 6 IMWr Data Register." hexmask.long.word 0x1C 16.--31. 1. "WR_CHANNEL_7_DATA,The DMA uses this field to generate the data field for the Done or Abort IMWr TLPs it generates for write channel 7. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" hexmask.long.word 0x1C 0.--15. 1. "WR_CHANNEL_6_DATA,The DMA uses this field to generate the data field for the Done or Abort IMWr TLPs it generates for write channel 6. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" group.long (0x90+0xC8000)++0x3 line.long 0x0 "DMA_WRITE_LINKED_LIST_ERR_EN_OFF,DMA Write Linked List Error Enable Register. The LIE and RIE bits in the LL element enable the channel 'done' interrupts (local and remote). The LLLAIE and LLRAIE bits enable the channel 'abort' interrupts (local and.." hexmask.long.byte 0x0 24.--31. 1. "RSVDP_24,Reserved for future use." hexmask.long.byte 0x0 16.--23. 1. "WR_CHANNEL_LLLAIE,Write Channel LL Local Abort Interrupt Enable (LLLAIE). You enable the write channel local abort interrupt through this bit. The LIE and RIE bits in the LL element enable the write channel done interrupts. Each bit corresponds to a DMA.." newline hexmask.long.byte 0x0 8.--15. 1. "RSVDP_8,Reserved for future use." hexmask.long.byte 0x0 0.--7. 1. "WR_CHANNEL_LLRAIE,Write Channel LL Remote Abort Interrupt Enable (LLRAIE). You enable the write channel remote abort interrupt through this bit. The LIE and RIE bits in the LL element enable the write channel done interrupts. Each bit corresponds to a.." group.long (0xA0+0xC8000)++0x3 line.long 0x0 "DMA_READ_INT_STATUS_OFF,DMA Read Interrupt Status Register." hexmask.long.byte 0x0 24.--31. 1. "RSVDP_24,Reserved for future use." hexmask.long.byte 0x0 16.--23. 1. "RD_ABORT_INT_STATUS,Abort Interrupt Status. The DMA read channel has detected an error or you manually stopped the transfer as described in 'Stopping the DMA Transfer (Software Stop)'. Each bit corresponds to a DMA channel. Bit [0] corresponds to.." newline hexmask.long.byte 0x0 8.--15. 1. "RSVDP_8,Reserved for future use." hexmask.long.byte 0x0 0.--7. 1. "RD_DONE_INT_STATUS,Done Interrupt Status. The DMA read channel has successfully completed the DMA read transfer. Each bit corresponds to a DMA channel. Bit [0] corresponds to channel 0. - Enabling: For details see 'Interrupts and Error Handling'. -.." group.long (0xA8+0xC8000)++0x7 line.long 0x0 "DMA_READ_INT_MASK_OFF,DMA Read Interrupt Mask Register." hexmask.long.byte 0x0 24.--31. 1. "RSVDP_24,Reserved for future use." hexmask.long.byte 0x0 16.--23. 1. "RD_ABORT_INT_MASK,Abort Interrupt Mask. Prevents the Abort interrupt status field in the DMA read interrupt status register from asserting the edma_int output. Each bit corresponds to a DMA channel. Bit [0] corresponds to channel 0. Note: The access.." newline hexmask.long.byte 0x0 8.--15. 1. "RSVDP_8,Reserved for future use." hexmask.long.byte 0x0 0.--7. 1. "RD_DONE_INT_MASK,Done Interrupt Mask. Prevents the Done interrupt status field in the DMA read interrupt status register from asserting the edma_int output. Each bit corresponds to a DMA channel. Bit [0] corresponds to channel 0. Note: The access.." line.long 0x4 "DMA_READ_INT_CLEAR_OFF,DMA Read Interrupt Clear Register." hexmask.long.byte 0x4 24.--31. 1. "RSVDP_24,Reserved for future use." hexmask.long.byte 0x4 16.--23. 1. "RD_ABORT_INT_CLEAR,Abort Interrupt Clear. You must write a 1'b1 to clear the corresponding bit in the Abort interrupt status field of the DMA read interrupt status register. Each bit corresponds to a DMA channel. Bit [0] corresponds to channel 0. Note:.." newline hexmask.long.byte 0x4 8.--15. 1. "RSVDP_8,Reserved for future use." hexmask.long.byte 0x4 0.--7. 1. "RD_DONE_INT_CLEAR,Done Interrupt Clear. You must write a 1'b1 to clear the corresponding bit in the Done interrupt status field of the DMA read interrupt status register. Each bit corresponds to a DMA channel. Bit [0] corresponds to channel 0. Note:.." rgroup.long (0xB4+0xC8000)++0x7 line.long 0x0 "DMA_READ_ERR_STATUS_LOW_OFF,DMA Read Error Status Low Register." hexmask.long.byte 0x0 24.--31. 1. "RSVDP_24,Reserved for future use." hexmask.long.byte 0x0 16.--23. 1. "LINK_LIST_ELEMENT_FETCH_ERR_DETECT,Linked List Element Fetch Error Detected. - The DMA read channel has received an error response from the AXI bus while reading a linked list element from local memory. Each bit corresponds to a DMA channel. Bit [0].." newline hexmask.long.byte 0x0 8.--15. 1. "RSVDP_8,Reserved for future use." hexmask.long.byte 0x0 0.--7. 1. "APP_WR_ERR_DETECT,Application Write Error Detected. The DMA read channel has received an error response from the AXI bus (or TRGT1 interface when the AXI Bridge is not used) while writing data to it. This error is fatal. You must restart the transfer.." line.long 0x4 "DMA_READ_ERR_STATUS_HIGH_OFF,DMA Read Error Status High Register." hexmask.long.byte 0x4 24.--31. 1. "DATA_POISIONING,Data Poisoning. The DMA read channel has detected data poisoning in the completion from the remote device (in response to the MRd request). The DMA read channel will drop the completion and then be halted. The CX_FLT_MASK_UR_POIS filter.." hexmask.long.byte 0x4 16.--23. 1. "CPL_TIMEOUT,Completion Time Out. The DMA read channel has timed-out while waiting for the remote device to respond to the MRd request or a malformed CplD has been received. For more details see 'Linked List Mode'. Each bit corresponds to a DMA channel." newline hexmask.long.byte 0x4 8.--15. 1. "CPL_ABORT,Completer Abort. The DMA read channel has received a PCIe completer abort completion status from the remote device in response to the MRd request. For more details see 'Linked List Mode'. Each bit corresponds to a DMA channel. Bit [0].." hexmask.long.byte 0x4 0.--7. 1. "UNSUPPORTED_REQ,Unsupported Request. The DMA read channel has received a PCIe unsupported request completion status from the remote device in response to the MRd request. For more details see 'Linked List Mode'. Each bit corresponds to a DMA channel." group.long (0xC4+0xC8000)++0x3 line.long 0x0 "DMA_READ_LINKED_LIST_ERR_EN_OFF,DMA Read Linked List Error Enable Register. The LIE and RIE bits in the LL element enable the channel 'done' interrupts (local and remote). The LLLAIE and LLRAIE bits enable the channel 'abort' interrupts (local and remote)." hexmask.long.byte 0x0 24.--31. 1. "RSVDP_24,Reserved for future use." hexmask.long.byte 0x0 16.--23. 1. "RD_CHANNEL_LLLAIE,Read Channel LL Local Abort Interrupt Enable (LLLAIE). You enable the read channel Local Abort interrupt through this bit. The LIE and RIE bits in the LL element enable the read channel done interrupts. Each bit corresponds to a DMA.." newline hexmask.long.byte 0x0 8.--15. 1. "RSVDP_8,Reserved for future use." hexmask.long.byte 0x0 0.--7. 1. "RD_CHANNEL_LLRAIE,Read Channel LL Remote Abort Interrupt Enable (LLRAIE). You enable the read channel Remote Abort interrupt through this bit. The LIE and RIE bits in the LL element enable the read channel done interrupts. Each bit corresponds to a DMA.." group.long (0xCC+0xC8000)++0x1F line.long 0x0 "DMA_READ_DONE_IMWR_LOW_OFF,DMA Read Done IMWr Address Low Register." hexmask.long 0x0 0.--31. 1. "DMA_READ_DONE_LOW_REG,The DMA uses this field to generate bits [31:0] of the address field for the Done IMWr TLP. Bits [1:0] must be '00' as this address must be dword aligned. Note: The access attributes of this field are as follows: - Wire: No access." line.long 0x4 "DMA_READ_DONE_IMWR_HIGH_OFF,DMA Read Done IMWr Address High Register." hexmask.long 0x4 0.--31. 1. "DMA_READ_DONE_HIGH_REG,The DMA uses this field to generate bits [63:32] of the address field for the Done IMWr TLP. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" line.long 0x8 "DMA_READ_ABORT_IMWR_LOW_OFF,DMA Read Abort IMWr Address Low Register." hexmask.long 0x8 0.--31. 1. "DMA_READ_ABORT_LOW_REG,The DMA uses this field to generate bits [31:0] of the address field for the Abort IMWr TLP. Bits [1:0] must be '00' as this address must be dword aligned. Note: The access attributes of this field are as follows: - Wire: No.." line.long 0xC "DMA_READ_ABORT_IMWR_HIGH_OFF,DMA Read Abort IMWr Address High Register." hexmask.long 0xC 0.--31. 1. "DMA_READ_ABORT_HIGH_REG,The DMA uses this field to generate bits [63:32] of the address field for the Abort IMWr TLP. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" line.long 0x10 "DMA_READ_CH01_IMWR_DATA_OFF,DMA Read Channel 1 and 0 IMWr Data Register." hexmask.long.word 0x10 16.--31. 1. "RD_CHANNEL_1_DATA,The DMA uses this field to generate the data field for the Done or Abort IMWr TLPs it generates for read channel 1. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" hexmask.long.word 0x10 0.--15. 1. "RD_CHANNEL_0_DATA,The DMA uses this field to generate the data field for the Done or Abort IMWr TLPs it generates for read channel 0. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" line.long 0x14 "DMA_READ_CH23_IMWR_DATA_OFF,DMA Read Channel 3 and 2 IMWr Data Register." hexmask.long.word 0x14 16.--31. 1. "RD_CHANNEL_3_DATA,The DMA uses this field to generate the data field for the Done or Abort IMWr TLPs it generates for read channel 3. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" hexmask.long.word 0x14 0.--15. 1. "RD_CHANNEL_2_DATA,The DMA uses this field to generate the data field for the Done or Abort IMWr TLPs it generates for read channel 2. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" line.long 0x18 "DMA_READ_CH45_IMWR_DATA_OFF,DMA Read Channel 5 and 4 IMWr Data Register." hexmask.long.word 0x18 16.--31. 1. "RD_CHANNEL_5_DATA,The DMA uses this field to generate the data field for the Done or Abort IMWr TLPs it generates for read channel 5. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" hexmask.long.word 0x18 0.--15. 1. "RD_CHANNEL_4_DATA,The DMA uses this field to generate the data field for the Done or Abort IMWr TLPs it generates for read channel 4. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" line.long 0x1C "DMA_READ_CH67_IMWR_DATA_OFF,DMA Read Channel 7 and 6 IMWr Data Register." hexmask.long.word 0x1C 16.--31. 1. "RD_CHANNEL_7_DATA,The DMA uses this field to generate the data field for the Done or Abort IMWr TLPs it generates for read channel 7. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" hexmask.long.word 0x1C 0.--15. 1. "RD_CHANNEL_6_DATA,The DMA uses this field to generate the data field for the Done or Abort IMWr TLPs it generates for read channel 6. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" rgroup.long (0x108+0xC8000)++0x7 line.long 0x0 "DMA_WRITE_ENGINE_HSHAKE_CNT_LOW_OFF,DMA Write Engine Handshake Counter Channel 0/1/2/3 Register." bitfld.long 0x0 29.--31. "RSVDP_29,Reserved for future use." "0,1,2,3,4,5,6,7" hexmask.long.byte 0x0 24.--28. 1. "DMA_WRITE_ENGINE_HSHAKE_CNT_CH3,DMA handshake counter for DMA Write Engine Channel 3. If CC_DMA_HSHAKE =1 the data transfer in Linked List mode starts only when the counter is non-zero." newline bitfld.long 0x0 21.--23. "RSVDP_21,Reserved for future use." "0,1,2,3,4,5,6,7" hexmask.long.byte 0x0 16.--20. 1. "DMA_WRITE_ENGINE_HSHAKE_CNT_CH2,DMA handshake counter for DMA Write Engine Channel 2. If CC_DMA_HSHAKE =1 the data transfer in Linked List mode starts only when the counter is non-zero." newline bitfld.long 0x0 13.--15. "RSVDP_13,Reserved for future use." "0,1,2,3,4,5,6,7" hexmask.long.byte 0x0 8.--12. 1. "DMA_WRITE_ENGINE_HSHAKE_CNT_CH1,DMA handshake counter for DMA Write Engine Channel 1. If CC_DMA_HSHAKE =1 the data transfer in Linked List mode starts only when the counter is non-zero." newline bitfld.long 0x0 5.--7. "RSVDP_5,Reserved for future use." "0,1,2,3,4,5,6,7" hexmask.long.byte 0x0 0.--4. 1. "DMA_WRITE_ENGINE_HSHAKE_CNT_CH0,DMA handshake counter for DMA Write Engine Channel 0. If CC_DMA_HSHAKE =1 the data transfer in Linked List mode starts only when the counter is non-zero." line.long 0x4 "DMA_WRITE_ENGINE_HSHAKE_CNT_HIGH_OFF,DMA Write Engine Handshake Counter Channel 4/5/6/7 Register." bitfld.long 0x4 29.--31. "RSVDP_29,Reserved for future use." "0,1,2,3,4,5,6,7" hexmask.long.byte 0x4 24.--28. 1. "DMA_WRITE_ENGINE_HSHAKE_CNT_CH7,DMA handshake counter for DMA Write Engine Channel 7. If CC_DMA_HSHAKE =1 the data transfer in Linked List mode starts only when the counter is non-zero." newline bitfld.long 0x4 21.--23. "RSVDP_21,Reserved for future use." "0,1,2,3,4,5,6,7" hexmask.long.byte 0x4 16.--20. 1. "DMA_WRITE_ENGINE_HSHAKE_CNT_CH6,DMA handshake counter for DMA Write Engine Channel 6. If CC_DMA_HSHAKE =1 the data transfer in Linked List mode starts only when the counter is non-zero." newline bitfld.long 0x4 13.--15. "RSVDP_13,Reserved for future use." "0,1,2,3,4,5,6,7" hexmask.long.byte 0x4 8.--12. 1. "DMA_WRITE_ENGINE_HSHAKE_CNT_CH5,DMA handshake counter for DMA Write Engine Channel 5. If CC_DMA_HSHAKE =1 the data transfer in Linked List mode starts only when the counter is non-zero." newline bitfld.long 0x4 5.--7. "RSVDP_5,Reserved for future use." "0,1,2,3,4,5,6,7" hexmask.long.byte 0x4 0.--4. 1. "DMA_WRITE_ENGINE_HSHAKE_CNT_CH4,DMA handshake counter for DMA Write Engine Channel 4. If CC_DMA_HSHAKE =1 the data transfer in Linked List mode starts only when the counter is non-zero." rgroup.long (0x118+0xC8000)++0x7 line.long 0x0 "DMA_READ_ENGINE_HSHAKE_CNT_LOW_OFF,DMA Read Engine Handshake Counter Channel 0/1/2/3 Register." bitfld.long 0x0 29.--31. "RSVDP_29,Reserved for future use." "0,1,2,3,4,5,6,7" hexmask.long.byte 0x0 24.--28. 1. "DMA_READ_ENGINE_HSHAKE_CNT_CH3,DMA handshake counter for DMA Read Engine Channel 3. If CC_DMA_HSHAKE =1 the data transfer in Linked List mode starts only when the counter is non-zero." newline bitfld.long 0x0 21.--23. "RSVDP_21,Reserved for future use." "0,1,2,3,4,5,6,7" hexmask.long.byte 0x0 16.--20. 1. "DMA_READ_ENGINE_HSHAKE_CNT_CH2,DMA handshake counter for DMA Read Engine Channel 2. If CC_DMA_HSHAKE =1 the data transfer in Linked List mode starts only when the counter is non-zero." newline bitfld.long 0x0 13.--15. "RSVDP_13,Reserved for future use." "0,1,2,3,4,5,6,7" hexmask.long.byte 0x0 8.--12. 1. "DMA_READ_ENGINE_HSHAKE_CNT_CH1,DMA handshake counter for DMA Read Engine Channel 1. If CC_DMA_HSHAKE =1 the data transfer in Linked List mode starts only when the counter is non-zero." newline bitfld.long 0x0 5.--7. "RSVDP_5,Reserved for future use." "0,1,2,3,4,5,6,7" hexmask.long.byte 0x0 0.--4. 1. "DMA_READ_ENGINE_HSHAKE_CNT_CH0,DMA handshake counter for DMA Read Engine Channel 0. If CC_DMA_HSHAKE =1 the data transfer in Linked List mode starts only when the counter is non-zero." line.long 0x4 "DMA_READ_ENGINE_HSHAKE_CNT_HIGH_OFF,DMA Read Engine Handshake Counter Channel 4/5/6/7 Register." bitfld.long 0x4 29.--31. "RSVDP_29,Reserved for future use." "0,1,2,3,4,5,6,7" hexmask.long.byte 0x4 24.--28. 1. "DMA_READ_ENGINE_HSHAKE_CNT_CH7,DMA handshake counter for DMA Read Engine Channel 7. If CC_DMA_HSHAKE =1 the data transfer in Linked List mode starts only when the counter is non-zero." newline bitfld.long 0x4 21.--23. "RSVDP_21,Reserved for future use." "0,1,2,3,4,5,6,7" hexmask.long.byte 0x4 16.--20. 1. "DMA_READ_ENGINE_HSHAKE_CNT_CH6,DMA handshake counter for DMA Read Engine Channel 6. If CC_DMA_HSHAKE =1 the data transfer in Linked List mode starts only when the counter is non-zero." newline bitfld.long 0x4 13.--15. "RSVDP_13,Reserved for future use." "0,1,2,3,4,5,6,7" hexmask.long.byte 0x4 8.--12. 1. "DMA_READ_ENGINE_HSHAKE_CNT_CH5,DMA handshake counter for DMA Read Engine Channel 5. If CC_DMA_HSHAKE =1 the data transfer in Linked List mode starts only when the counter is non-zero." newline bitfld.long 0x4 5.--7. "RSVDP_5,Reserved for future use." "0,1,2,3,4,5,6,7" hexmask.long.byte 0x4 0.--4. 1. "DMA_READ_ENGINE_HSHAKE_CNT_CH4,DMA handshake counter for DMA Read Engine Channel 4. If CC_DMA_HSHAKE =1 the data transfer in Linked List mode starts only when the counter is non-zero." repeat 8. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 )(list 0x0 0x200 0x400 0x600 0x800 0xA00 0xC00 0xE00 ) group.long ($2+0x200+0xC8000)++0x3 line.long 0x0 "DMA_CH_CONTROL1_OFF_WRCH_$1,DMA Write Channel Control 1 Register." bitfld.long 0x0 30.--31. "DMA_AT,Address Translation TLP Header Bit (AT) The DMA uses this TLP header field when generating MRd/MWr (not IMWr) TLPs. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" "0,1,2,3" bitfld.long 0x0 27.--29. "DMA_TC,Traffic Class TLP Header Bit (TC) The DMA uses this TLP header field when generating MRd/MWr (not IMWr) TLPs. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 26. "DMA_RESERVED5,Reserved. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" "0,1" bitfld.long 0x0 25. "DMA_RO,Relaxed Ordering TLP Header Bit (RO) The DMA uses this TLP header field when generating MRd/MWr (not IMWr) TLPs. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" "0,1" newline bitfld.long 0x0 24. "DMA_NS_SRC,Source No Snoop TLP Header Bit (DMA_NS_SRC). The DMA uses this TLP header field when generating MRd (SAR addressing space) (not IMWr) TLPs. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" "0,1" bitfld.long 0x0 23. "DMA_NS_DST,Destination No Snoop TLP Header Bit (DMA_NS_DST). The DMA uses this TLP header field when generating MWr (DAR addressing space) (not IMWr) TLPs. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" "0,1" newline bitfld.long 0x0 22. "DMA_MEM_TYPE,Master AXI ACE-Lite Cache Coherency Control. This field sets the DMA channel memory type of the address space of the data transfer as follows: - 0x0:peripheral type - 0x1:memory type For more details see 'ACE-Lite Features and Limitations'.." "peripheral type,memory type" hexmask.long.byte 0x0 17.--21. 1. "DMA_RESERVED2,Reserved. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" newline hexmask.long.byte 0x0 12.--16. 1. "DMA_FUNC_NUM,Function Number (FN). The controller uses this field when generating the requester ID for the MRd/MWr DMA TLP. When you have enabled SR-IOV then this field is ignored if you have set the VFE field in the 'DMA Write Channel Control 2.." bitfld.long 0x0 10.--11. "DMA_RESERVED1,Reserved. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" "0,1,2,3" newline bitfld.long 0x0 9. "LLE,Linked List Enable (LLE). - 0: Disable linked list operation - 1: Enable linked list operation Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" "Disable linked list operation,Enable linked list operation" bitfld.long 0x0 8. "CCS,Consumer Cycle State (CCS). Used in linked list mode only. It is used to synchronize the producer (software) and the consumer (DMA). For more details see 'PCS-CCS-CB-TCB Producer-Consumer Synchronization'. You must initialize this bit. The DMA.." "0,1" newline bitfld.long 0x0 7. "DMA_RESERVED0,Reserved. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" "0,1" bitfld.long 0x0 5.--6. "CS,Channel Status (CS). The channel status bits identify the current operational state of the DMA channel. The operation state encoding for each DMA channel is a s follows: - 00: Reserved - 01: Running. This channel is active and transferring data. - 10:.." "Reserved,Running,?,?" newline bitfld.long 0x0 4. "RIE,Remote Interrupt Enable (RIE). You must set this bit to enable the generation of the Done or Abort Remote interrupts. For more details see 'Interrupts and Error Handling'. In LL mode the DMA overwrites this with the RIE of the LL element. The RIE.." "0,1" bitfld.long 0x0 3. "LIE,Local Interrupt Enable (LIE). You must set this bit to enable the generation of the Done or Abort Local interrupts. For more details see 'Interrupts and Error Handling'. In LL mode the DMA overwrites this with the LIE of the LL element. The LIE bit.." "0,1" newline bitfld.long 0x0 2. "LLP,Load Link Pointer (LLP). Used in linked list mode only. Indicates that this linked list element is a link element and its LL element pointer dwords are pointing to the next (non-contiguous) element. The DMA loads this field with the LLP of the.." "0,1" bitfld.long 0x0 1. "TCB,Toggle Cycle Bit (TCB). Indicates to the DMA to toggle its interpretation of the CB. Used in linked list mode only. It is used to synchronize the producer (software) and the consumer (DMA). For more details see 'PCS-CCS-CB-TCB Producer-Consumer.." "0,1" newline bitfld.long 0x0 0. "CB,Cycle Bit (CB). Used in linked list mode only. It is used to synchronize the producer (software) and the consumer (DMA). For more details see 'PCS-CCS-CB-TCB Producer-Consumer Synchronization'. The DMA loads this field with the CB of the linked list.." "0,1" repeat.end repeat 8. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 )(list 0x0 0x200 0x400 0x600 0x800 0xA00 0xC00 0xE00 ) group.long ($2+0x208+0xC8000)++0x3 line.long 0x0 "DMA_TRANSFER_SIZE_OFF_WRCH_$1,DMA Write Transfer Size Register." hexmask.long 0x0 0.--31. 1. "DMA_TRANSFER_SIZE,DMA Transfer Size. You program this register with the size of the DMA transfer. The maximum DMA transfer size is 4Gbytes. The minimum transfer size is one byte (0x1). This field is automatically decremented by the DMA as the DMA write.." repeat.end repeat 8. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 )(list 0x0 0x200 0x400 0x600 0x800 0xA00 0xC00 0xE00 ) group.long ($2+0x20C+0xC8000)++0x3 line.long 0x0 "DMA_SAR_LOW_OFF_WRCH_$1,DMA Write SAR Low Register." hexmask.long 0x0 0.--31. 1. "SRC_ADDR_REG_LOW,Source Address Register (Lower 32 bits). Indicates the next address to be read from. The DMA increments the SAR as the DMA transfer progresses. In LL mode the DMA overwrites this with the corresponding dword of the LL element. - DMA.." repeat.end repeat 8. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 )(list 0x0 0x200 0x400 0x600 0x800 0xA00 0xC00 0xE00 ) group.long ($2+0x210+0xC8000)++0x3 line.long 0x0 "DMA_SAR_HIGH_OFF_WRCH_$1,DMA Write SAR High Register." hexmask.long 0x0 0.--31. 1. "SRC_ADDR_REG_HIGH,Source Address Register (Higher 32 bits). In LL mode the DMA overwrites this with the corresponding dword of the LL element. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" repeat.end repeat 8. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 )(list 0x0 0x200 0x400 0x600 0x800 0xA00 0xC00 0xE00 ) group.long ($2+0x214+0xC8000)++0x3 line.long 0x0 "DMA_DAR_LOW_OFF_WRCH_$1,DMA Write DAR Low Register." hexmask.long 0x0 0.--31. 1. "DST_ADDR_REG_LOW,Destination Address Register (Lower 32 bits). Indicates the next address to be written to. The DMA increments the DAR as the DMA transfer progresses. In LL mode the DMA overwrites this with the corresponding dword of the LL element. -.." repeat.end repeat 8. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 )(list 0x0 0x200 0x400 0x600 0x800 0xA00 0xC00 0xE00 ) group.long ($2+0x218+0xC8000)++0x3 line.long 0x0 "DMA_DAR_HIGH_OFF_WRCH_$1,DMA Write DAR High Register." hexmask.long 0x0 0.--31. 1. "DST_ADDR_REG_HIGH,Destination Address Register (Higher 32 bits). In LL mode the DMA overwrites this with the corresponding dword of the LL element. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" repeat.end repeat 8. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 )(list 0x0 0x200 0x400 0x600 0x800 0xA00 0xC00 0xE00 ) group.long ($2+0x21C+0xC8000)++0x3 line.long 0x0 "DMA_LLP_LOW_OFF_WRCH_$1,DMA Write Linked List Pointer Low Register." hexmask.long 0x0 0.--31. 1. "LLP_LOW,Lower bits of the address of the linked list transfer list in local memory. Used in linked list mode only. Updated by the DMA to point to the next element in the transfer list after the previous element is consumed. - When the current element is.." repeat.end repeat 8. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 )(list 0x0 0x200 0x400 0x600 0x800 0xA00 0xC00 0xE00 ) group.long ($2+0x220+0xC8000)++0x3 line.long 0x0 "DMA_LLP_HIGH_OFF_WRCH_$1,DMA Write Linked List Pointer High Register." hexmask.long 0x0 0.--31. 1. "LLP_HIGH,Upper 32 bits of the address of the linked list transfer list in local memory. Used in linked list mode only. Updated by the DMA to point to the next element in the transfer list as elements are consumed. Note: The access attributes of this.." repeat.end repeat 8. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 )(list 0x0 0x200 0x400 0x600 0x800 0xA00 0xC00 0xE00 ) group.long ($2+0x300+0xC8000)++0x3 line.long 0x0 "DMA_CH_CONTROL1_OFF_RDCH_$1,DMA Read Channel Control 1 Register." bitfld.long 0x0 30.--31. "DMA_AT,Address Translation TLP Header Bit (AT) The DMA uses this TLP header field when generating MRd/MWr (not IMWr) TLPs. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" "0,1,2,3" bitfld.long 0x0 27.--29. "DMA_TC,Traffic Class TLP Header Bit (TC) The DMA uses this TLP header field when generating MRd/MWr (not IMWr) TLPs. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 26. "DMA_RESERVED5,Reserved. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" "0,1" bitfld.long 0x0 25. "DMA_RO,Relaxed Ordering TLP Header Bit (RO) The DMA uses this TLP header field when generating MRd/MWr (not IMWr) TLPs. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" "0,1" newline bitfld.long 0x0 24. "DMA_NS_SRC,Source No Snoop TLP Header Bit (DMA_NS_SRC). The DMA uses this TLP header field when generating MRd (SAR addressing space) (not IMWr) TLPs. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" "0,1" bitfld.long 0x0 23. "DMA_NS_DST,Destination No Snoop TLP Header Bit (DMA_NS_DST). The DMA uses this TLP header field when generating MWr (DAR addressing space) (not IMWr) TLPs. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" "0,1" newline bitfld.long 0x0 22. "DMA_MEM_TYPE,Master AXI ACE-Lite Cache Coherency Control. This field sets the DMA channel memory type of the address space of the data transfer as follows: - 0x0:peripheral type - 0x1:memory type For more details see 'ACE-Lite Features and Limitations'.." "peripheral type,memory type" hexmask.long.byte 0x0 17.--21. 1. "DMA_RESERVED2,Reserved. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" newline hexmask.long.byte 0x0 12.--16. 1. "DMA_FUNC_NUM,Function Number (FN). The controller uses this field when generating the requester ID for the MRd/MWr DMA TLP. When you have enabled SR-IOV then this field is ignored if you have set the VFE field in the 'DMA Read Channel Control 2.." bitfld.long 0x0 10.--11. "DMA_RESERVED1,Reserved. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" "0,1,2,3" newline bitfld.long 0x0 9. "LLE,Linked List Enable (LLE). - 0: Disable linked list operation - 1: Enable linked list operation Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" "Disable linked list operation,Enable linked list operation" bitfld.long 0x0 8. "CCS,Consumer Cycle State (CCS). Used in linked list mode only. It is used to synchronize the producer (software) and the consumer (DMA). For more details see 'PCS-CCS-CB-TCB Producer-Consumer Synchronization'. You must initialize this bit. The DMA.." "0,1" newline bitfld.long 0x0 7. "DMA_RESERVED0,Reserved. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" "0,1" bitfld.long 0x0 5.--6. "CS,Channel Status (CS). The channel status bits identify the current operational state of the DMA channel. The operation state encoding for each DMA channel is a s follows: - 00: Reserved - 01: Running. This channel is active and transferring data. - 10:.." "Reserved,Running,?,?" newline bitfld.long 0x0 4. "RIE,Remote Interrupt Enable (RIE). You must set this bit to enable the generation of the Done or Abort Remote interrupts. For more details see 'Interrupts and Error Handling'. In LL mode the DMA overwrites this with the RIE of the LL element. The RIE.." "0,1" bitfld.long 0x0 3. "LIE,Local Interrupt Enable (LIE). You must set this bit to enable the generation of the Done or Abort Local interrupts. For more details see 'Interrupts and Error Handling'. In LL mode the DMA overwrites this with the LIE of the LL element. The LIE bit.." "0,1" newline bitfld.long 0x0 2. "LLP,Load Link Pointer (LLP). Used in linked list mode only. Indicates that this linked list element is a link element and its LL element pointer dwords are pointing to the next (non-contiguous) element. The DMA loads this field with the LLP of the.." "0,1" bitfld.long 0x0 1. "TCB,Toggle Cycle Bit (TCB). Indicates to the DMA to toggle its interpretation of the CB. Used in linked list mode only. It is used to synchronize the producer (software) and the consumer (DMA). For more details see 'PCS-CCS-CB-TCB Producer-Consumer.." "0,1" newline bitfld.long 0x0 0. "CB,Cycle Bit (CB). Used in linked list mode only. It is used to synchronize the producer (software) and the consumer (DMA). For more details see 'PCS-CCS-CB-TCB Producer-Consumer Synchronization'. The DMA loads this field with the CB of the linked list.." "0,1" repeat.end repeat 8. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 )(list 0x0 0x200 0x400 0x600 0x800 0xA00 0xC00 0xE00 ) group.long ($2+0x308+0xC8000)++0x3 line.long 0x0 "DMA_TRANSFER_SIZE_OFF_RDCH_$1,DMA Read Transfer Size Register." hexmask.long 0x0 0.--31. 1. "DMA_TRANSFER_SIZE,DMA Transfer Size. You program this register with the size of the DMA transfer. The maximum DMA transfer size is 4Gbytes. The minimum transfer size is one byte (0x1). This field is automatically decremented by the DMA as the DMA read.." repeat.end repeat 8. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 )(list 0x0 0x200 0x400 0x600 0x800 0xA00 0xC00 0xE00 ) group.long ($2+0x30C+0xC8000)++0x3 line.long 0x0 "DMA_SAR_LOW_OFF_RDCH_$1,DMA Read SAR Low Register." hexmask.long 0x0 0.--31. 1. "SRC_ADDR_REG_LOW,Source Address Register (Lower 32 bits). Indicates the next address to be read from. The DMA increments the SAR as the DMA transfer progresses. In LL mode the DMA overwrites this with the corresponding dword of the LL element. - DMA.." repeat.end repeat 8. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 )(list 0x0 0x200 0x400 0x600 0x800 0xA00 0xC00 0xE00 ) group.long ($2+0x310+0xC8000)++0x3 line.long 0x0 "DMA_SAR_HIGH_OFF_RDCH_$1,DMA Read SAR High Register." hexmask.long 0x0 0.--31. 1. "SRC_ADDR_REG_HIGH,Source Address Register (Higher 32 bits). In LL mode the DMA overwrites this with the corresponding dword of the LL element. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" repeat.end repeat 8. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 )(list 0x0 0x200 0x400 0x600 0x800 0xA00 0xC00 0xE00 ) group.long ($2+0x314+0xC8000)++0x3 line.long 0x0 "DMA_DAR_LOW_OFF_RDCH_$1,DMA Read DAR Low Register." hexmask.long 0x0 0.--31. 1. "DST_ADDR_REG_LOW,Destination Address Register (Lower 32 bits). Indicates the next address to be written to. The DMA increments the DAR as the DMA transfer progresses. In LL mode the DMA overwrites this with the corresponding dword of the LL element. -.." repeat.end repeat 8. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 )(list 0x0 0x200 0x400 0x600 0x800 0xA00 0xC00 0xE00 ) group.long ($2+0x318+0xC8000)++0x3 line.long 0x0 "DMA_DAR_HIGH_OFF_RDCH_$1,DMA Read DAR High Register." hexmask.long 0x0 0.--31. 1. "DST_ADDR_REG_HIGH,Destination Address Register (Higher 32 bits). In LL mode the DMA overwrites this with the corresponding dword of the LL element. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" repeat.end repeat 8. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 )(list 0x0 0x200 0x400 0x600 0x800 0xA00 0xC00 0xE00 ) group.long ($2+0x31C+0xC8000)++0x3 line.long 0x0 "DMA_LLP_LOW_OFF_RDCH_$1,DMA Read Linked List Pointer Low Register." hexmask.long 0x0 0.--31. 1. "LLP_LOW,Lower bits of the address of the linked list transfer list in local memory. Used in linked list mode only. Updated by the DMA to point to the next element in the transfer list after the previous element is consumed. - When the current element is.." repeat.end repeat 8. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 )(list 0x0 0x200 0x400 0x600 0x800 0xA00 0xC00 0xE00 ) group.long ($2+0x320+0xC8000)++0x3 line.long 0x0 "DMA_LLP_HIGH_OFF_RDCH_$1,DMA Read Linked List Pointer High Register." hexmask.long 0x0 0.--31. 1. "LLP_HIGH,Upper 32 bits of the address of the linked list transfer list in local memory. Used in linked list mode only. Updated by the DMA to point to the next element in the transfer list as elements are consumed. Note: The access attributes of this.." repeat.end tree.end tree "PF0_ATU_CAP (ATU Por Logic Structure)" repeat 8. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 )(list 0x0 0x200 0x400 0x600 0x800 0xA00 0xC00 0xE00 ) group.long ($2+0xC0000)++0x3 line.long 0x0 "IATU_REGION_CTRL_1_OFF_OUTBOUND_$1,iATU Region Control 1 Register." bitfld.long 0x0 20. "CTRL_1_FUNC_NUM,Function Number. - When the address of an outbound TLP is matched to this region and the FUNC_BYPASS field in the 'iATU Control 2 Register' is '0' then the function number used in generating the function part of the requester ID (RID).." "0,1" newline bitfld.long 0x0 13. "INCREASE_REGION_SIZE,Increase the maximum ATU Region size. When set the maximum ATU Region size is determined by CX_ATU_MAX_REGION_SIZE. When clear the maximum ATU Region size is 4 GB (default). Note: This register field is sticky." "0,1" newline bitfld.long 0x0 9.--10. "ATTR,When the address of an outbound TLP is matched to this region then the ATTR field of the TLP is changed to the value in this register. Note: This register field is sticky." "0,1,2,3" newline bitfld.long 0x0 8. "TD,This is a reserved field. Do not use. Note: This register field is sticky." "0,1" newline bitfld.long 0x0 5.--7. "TC,When the address of an outbound TLP is matched to this region then the TC field of the TLP is changed to the value in this register. Note: This register field is sticky." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x0 0.--4. 1. "TYPE,When the address of an outbound TLP is matched to this region then the TYPE field of the TLP is changed to the value in this register. Note: This register field is sticky." repeat.end repeat 8. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 )(list 0x0 0x200 0x400 0x600 0x800 0xA00 0xC00 0xE00 ) group.long ($2+0x4+0xC0000)++0x3 line.long 0x0 "IATU_REGION_CTRL_2_OFF_OUTBOUND_$1,iATU Region Control 2 Register." bitfld.long 0x0 31. "REGION_EN,Region Enable. This bit must be set to '1' for address translation to take place. Note: This register field is sticky." "0,1" newline bitfld.long 0x0 29. "INVERT_MODE,Invert Mode. When set the address matching region is inverted. Therefore an address match occurs when the untranslated address is in the region outside the defined range (Base Address to Limit Address). Note: This register field is sticky." "0,1" newline bitfld.long 0x0 28. "CFG_SHIFT_MODE,CFG Shift Mode. The iATU uses bits [27:12] of the untranslated address (on the XALI0/1/2 interface or AXI slave interface address) to form the BDF number of the outgoing CFG TLP. This supports the Enhanced Configuration Address Mapping.." "0,1" newline bitfld.long 0x0 27. "DMA_BYPASS,DMA Bypass Mode. Allows request TLPs which are initiated by the DMA controller to pass through the iATU untranslated. Note: This field is reserved for the SW product. You must set it to '0'. Note: This register field is sticky." "0,1" newline bitfld.long 0x0 23. "HEADER_SUBSTITUTE_EN,Header Substitute Enable. When enabled and region address is matched the iATU fully substitutes bytes 8-11 (for 3 DWORD header) or bytes 12-15 (for 4 DWORD header) of the outbound TLP header with the contents of the LWR_TARGET_RW.." "LWR_TARGET_RW in the..,LWR_TARGET_RW in the.." newline bitfld.long 0x0 22. "INHIBIT_PAYLOAD,Inhibit TLP Payload Data for TLP's in Matched Region; assign iATU region to be TLP without data. When enabled and region address is matched the iATU marks all TLPs as having no payload data by forcing the TLP header Fmt[1] bit =0.." "Fmt[1] =0/1 so that TLPs with or without data..,Fmt[1] =0 so that only TLP type without data is.." newline bitfld.long 0x0 21. "TLP_HEADER_FIELDS_BYPASS,TLP Header Fields Translation Bypass. In this mode header fields of the translated TLP is taken from your application transmit interface or if AMBA is configured from the AMBA sideband bus (slv_awmisc_info) and not from the.." "0,1" newline bitfld.long 0x0 20. "SNP,Serialize Non-Posted Requests. In this mode when the AXI Bridge is populated same AXI ID Non-Posted Read/Write Requests are transmitted on the wire if there are no other same ID Non-Posted Requests outstanding. Note: This register field is sticky." "0,1" newline bitfld.long 0x0 19. "FUNC_BYPASS,Function Number Translation Bypass. In this mode the function number of the translated TLP is taken from your application transmit interface and not from the CTRL_1_FUNC_NUM field of the 'iATU Control 1 Register' or the VF_NUMBER field of.." "0,1" newline bitfld.long 0x0 16. "TAG_SUBSTITUTE_EN,TAG Substitute Enable. When enabled and region address is matched the iATU substitutes the TAG field of the outbound TLP header with the contents of the TAG field in this register. The expected usage scenario is translation from AXI.." "0,1" newline hexmask.long.byte 0x0 8.--15. 1. "TAG,TAG. The substituted TAG field (byte 6) in the outgoing TLP header when TAG_SUBSTITUTE_EN is set. Note: This register field is sticky." newline hexmask.long.byte 0x0 0.--7. 1. "MSG_CODE,MSG TLPs (Message Code). When the address of an outbound TLP is matched to this region and the translated TLP TYPE field is Msg or MsgD; then the message field of the TLP is changed to the value in this register. Memory TLPs: (ST;Steering Tag)." repeat.end repeat 8. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 )(list 0x0 0x200 0x400 0x600 0x800 0xA00 0xC00 0xE00 ) group.long ($2+0x8+0xC0000)++0x3 line.long 0x0 "IATU_LWR_BASE_ADDR_OFF_OUTBOUND_$1,iATU Lower Base Address Register. The CX_ATU_MIN_REGION_SIZE configuration parameter (Value Range: 4 kB. 8 kB. 16 kB. 32 kB. 64 kB defaults to 64 kB) specifies the minimum size of an address translation region. For.." hexmask.long.tbyte 0x0 12.--31. 1. "LWR_BASE_RW,Forms bits [31:n] of the start address of the address region to be translated. n is log2(CX_ATU_MIN_REGION_SIZE) Note: This register field is sticky." newline hexmask.long.word 0x0 0.--11. 1. "LWR_BASE_HW,Forms bits [n-1:0] of the start address of the address region to be translated. The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary so these bits are always 0. A write to this location is ignored by the PCIe controller." repeat.end repeat 8. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 )(list 0x0 0x200 0x400 0x600 0x800 0xA00 0xC00 0xE00 ) group.long ($2+0xC+0xC0000)++0x3 line.long 0x0 "IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_$1,iATU Upper Base Address Register." hexmask.long 0x0 0.--31. 1. "UPPER_BASE_RW,Forms bits [63:32] of the start (and end) address of the address region to be translated. In systems with a 32-bit address space this register is not used and therefore writing to this register has no effect. Note: This register field is.." repeat.end repeat 8. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 )(list 0x0 0x200 0x400 0x600 0x800 0xA00 0xC00 0xE00 ) group.long ($2+0x10+0xC0000)++0x3 line.long 0x0 "IATU_LIMIT_ADDR_OFF_OUTBOUND_$1,iATU Limit Address Register." hexmask.long.tbyte 0x0 12.--31. 1. "LIMIT_ADDR_RW,Forms upper bits of the end address of the address region to be translated. Note: This register field is sticky." newline hexmask.long.word 0x0 0.--11. 1. "LIMIT_ADDR_HW,Forms lower bits of the end address of the address region to be translated. The end address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary so these bits are always all ones. A write to this location is ignored by the PCIe.." repeat.end repeat 8. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 )(list 0x0 0x200 0x400 0x600 0x800 0xA00 0xC00 0xE00 ) group.long ($2+0x14+0xC0000)++0x3 line.long 0x0 "IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_$1,iATU Lower Target Address Register." hexmask.long 0x0 0.--31. 1. "LWR_TARGET_RW_OUTBOUND,When HEADER_SUBSTITUTE_EN in IATU_REGION_CTRL_2_OFF_OUTBOUND_ is '0' (normal operation): - LWR_TARGET_RW[31:n] forms MSB's of the Lower Target part of the new address of the translated region; - LWR_TARGET_RW[n-1:0] are not used." repeat.end repeat 8. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 )(list 0x0 0x200 0x400 0x600 0x800 0xA00 0xC00 0xE00 ) group.long ($2+0x18+0xC0000)++0x3 line.long 0x0 "IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_$1,iATU Upper Target Address Register." hexmask.long 0x0 0.--31. 1. "UPPER_TARGET_RW,Forms bits [63:32] of the start address (Upper Target part) of the new address of the translated region. Note: This register field is sticky." repeat.end repeat 8. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 )(list 0x0 0x200 0x400 0x600 0x800 0xA00 0xC00 0xE00 ) group.long ($2+0x100+0xC0000)++0x3 line.long 0x0 "IATU_REGION_CTRL_1_OFF_INBOUND_$1,iATU Region Control 1 Register." bitfld.long 0x0 20. "CTRL_1_FUNC_NUM,Function Number. - MEM-I/O: When the Address and BAR matching logic in the controller indicate that a MEM-I/O transaction matches a BAR in the function corresponding to this value then address translation proceeds. This check is only.." "?,When the destination function number as.." newline bitfld.long 0x0 13. "INCREASE_REGION_SIZE,Increase the maximum ATU Region size. When set the maximum ATU Region size is determined by CX_ATU_MAX_REGION_SIZE. When clear the maximum ATU Region size is 4 GB (default). Note: This register field is sticky." "0,1" newline bitfld.long 0x0 9.--10. "ATTR,When the ATTR field of an inbound TLP is matched to this value then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the 'ATTR Match Enable' bit of the 'iATU Control 2 Register' is.." "0,1,2,3" newline bitfld.long 0x0 8. "TD,When the TD field of an inbound TLP is matched to this value then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the 'TD Match Enable' bit of the 'iATU Control 2 Register' is set." "0,1" newline bitfld.long 0x0 5.--7. "TC,When the TC field of an inbound TLP is matched to this value then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the 'TC Match Enable' bit of the 'iATU Control 2 Register' is set." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x0 0.--4. 1. "TYPE,When the TYPE field of an inbound TLP is matched to this value then address translation proceeds (when all other enabled field-matches are successful). Note: This register field is sticky." repeat.end repeat 8. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 )(list 0x0 0x200 0x400 0x600 0x800 0xA00 0xC00 0xE00 ) group.long ($2+0x104+0xC0000)++0x3 line.long 0x0 "IATU_REGION_CTRL_2_OFF_INBOUND_$1,iATU Region Control 2 Register." bitfld.long 0x0 31. "REGION_EN,Region Enable. This bit must be set to '1' for address translation to take place. Note: This register field is sticky." "0,1" newline bitfld.long 0x0 30. "MATCH_MODE,Match Mode. Determines Inbound matching mode for TLPs. The mode depends on the type of TLP that is received as follows: For MEM-I/O TLPs this field is interpreted as follows: - 0: Address Match Mode. The iATU operates using addresses as in.." "Address Match Mode,Vendor ID Match Mode" newline bitfld.long 0x0 29. "INVERT_MODE,Invert Mode. When set the address matching region is inverted. Therefore an address match occurs when the untranslated address is in the region outside the defined range (Base Address to Limit Address). Note: This register field is sticky." "0,1" newline bitfld.long 0x0 28. "CFG_SHIFT_MODE,CFG Shift Mode. This is useful for CFG transactions where the PCIe configuration mechanism maps bits [27:12] of the address to the bus/device and function number. This allows a CFG configuration space to be located in any 256MB window of.." "0,1" newline bitfld.long 0x0 27. "FUZZY_TYPE_MATCH_CODE,Fuzzy Type Match Mode. When enabled the iATU relaxes the matching of the TLP TYPE field against the expected TYPE field so that - CfgRd0 and CfgRd1 TLPs are seen as identical. Similarly with CfgWr0 and CfgWr1. - MWr MRd and MRdLk.." "0,1" newline bitfld.long 0x0 24.--25. "RESPONSE_CODE,Response Code. Defines the type of response to give for accesses matching this region. This overrides the normal RADM filter response. Note that this feature is not available for any region where Single Address Location Translate is.." "Normal RADM filter response is used,Unsupported request,?,?" newline bitfld.long 0x0 23. "SINGLE_ADDR_LOC_TRANS_EN,Single Address Location Translate Enable. When enabled Rx TLPs can be translated to a single address location as determined by the target address register of the iATU region. The main usage scenario is translation of Messages.." "0,1" newline bitfld.long 0x0 21. "MSG_CODE_MATCH_EN,Message Code Match Enable (Msg TLPS). Ensures that a successful message Code TLP field comparison match (see Message Code field of the 'iATU Control 2 Register') occurs (in MSG transactions) for address translation to proceed. ST Match.." "0,1" newline bitfld.long 0x0 19. "FUNC_NUM_MATCH_EN,Function Number Match Enable. Ensures that a successful Function Number TLP field comparison match (see Function Number field of the 'iATU Control 1 Register') occurs (in MEM-I/O and CFG0/CFG1 transactions) for address translation to.." "0,1" newline bitfld.long 0x0 16. "ATTR_MATCH_EN,ATTR Match Enable. Ensures that a successful ATTR TLP field comparison match (see ATTR field of the 'iATU Control 1 Register') occurs for address translation to proceed. Note: This register field is sticky." "0,1" newline bitfld.long 0x0 15. "TD_MATCH_EN,TD Match Enable. Ensures that a successful TD TLP field comparison match (see TD field of the 'iATU Control 1 Register') occurs for address translation to proceed. Note: This register field is sticky." "0,1" newline bitfld.long 0x0 14. "TC_MATCH_EN,TC Match Enable. Ensures that a successful TC TLP field comparison match (see TC field of the 'iATU Control 1 Register') occurs for address translation to proceed. Note: This register field is sticky." "0,1" newline bitfld.long 0x0 13. "MSG_TYPE_MATCH_MODE,Message Type Match Mode. When enabled and if single address location translate enable is set then inbound TLPs of type MSG/MSGd which match the type field of the iatu_region_ctrl_1_OFF_inbound register (=>TYPE[4:3]=2'b10) will be.." "0,1" newline bitfld.long 0x0 8.--10. "BAR_NUM,BAR Number. When the BAR number of an inbound MEM or IO TLP ' that is matched by the normal internal BAR address matching mechanism ' is the same as this field address translation proceeds (when all other enabled field-matches are successful)." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x0 0.--7. 1. "MSG_CODE,MSG TLPs: (Message Code). When the TYPE field of an inbound Msg/MsgD TLP is matched to this value then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the 'Message Code Match.." repeat.end repeat 8. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 )(list 0x0 0x200 0x400 0x600 0x800 0xA00 0xC00 0xE00 ) group.long ($2+0x108+0xC0000)++0x3 line.long 0x0 "IATU_LWR_BASE_ADDR_OFF_INBOUND_$1,iATU Lower Base Address Register. The CX_ATU_MIN_REGION_SIZE configuration parameter (Value Range: 4 kB. 8 kB. 16 kB. 32 kB. 64 kB defaults to 64 kB) specifies the minimum size of an address translation region. For.." hexmask.long.tbyte 0x0 12.--31. 1. "LWR_BASE_RW,Forms bits [31:n] of the start address of the address region to be translated. n is log2(CX_ATU_MIN_REGION_SIZE) Note: This register field is sticky." newline hexmask.long.word 0x0 0.--11. 1. "LWR_BASE_HW,Forms bits [n-1:0] of the start address of the address region to be translated. The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary so these bits are always 0. A write to this location is ignored by the PCIe controller." repeat.end repeat 8. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 )(list 0x0 0x200 0x400 0x600 0x800 0xA00 0xC00 0xE00 ) group.long ($2+0x10C+0xC0000)++0x3 line.long 0x0 "IATU_UPPER_BASE_ADDR_OFF_INBOUND_$1,iATU Upper Base Address Register." hexmask.long 0x0 0.--31. 1. "UPPER_BASE_RW,Forms bits [63:32] of the start (and end) address of the address region to be translated. Note: This register field is sticky." repeat.end repeat 8. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 )(list 0x0 0x200 0x400 0x600 0x800 0xA00 0xC00 0xE00 ) group.long ($2+0x110+0xC0000)++0x3 line.long 0x0 "IATU_LIMIT_ADDR_OFF_INBOUND_$1,iATU Limit Address Register." hexmask.long.tbyte 0x0 12.--31. 1. "LIMIT_ADDR_RW,Forms upper bits of the end address of the address region to be translated. Note: This register field is sticky." newline hexmask.long.word 0x0 0.--11. 1. "LIMIT_ADDR_HW,Forms lower bits of the end address of the address region to be translated. The end address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary so these bits are always all ones. A write to this location is ignored by the PCIe.." repeat.end repeat 8. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 )(list 0x0 0x200 0x400 0x600 0x800 0xA00 0xC00 0xE00 ) group.long ($2+0x114+0xC0000)++0x3 line.long 0x0 "IATU_LWR_TARGET_ADDR_OFF_INBOUND_$1,iATU Lower Target Address Register." hexmask.long.tbyte 0x0 12.--31. 1. "LWR_TARGET_RW,Forms MSB's of the Lower Target part of the new address of the translated region. These bits are always '0'. - Field size depends on log2(CX_ATU_MIN_REGION_SIZE) in address match mode. - Field size depends on log2(BAR_MASK+1) in BAR match.." newline hexmask.long.word 0x0 0.--11. 1. "LWR_TARGET_HW,Forms the LSB's of the Lower Target part of the new address of the translated region. The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary (in address match mode); and to the Bar size boundary (in BAR match mode) so.." repeat.end repeat 8. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 )(list 0x0 0x200 0x400 0x600 0x800 0xA00 0xC00 0xE00 ) group.long ($2+0x118+0xC0000)++0x3 line.long 0x0 "IATU_UPPER_TARGET_ADDR_OFF_INBOUND_$1,iATU Upper Target Address Register." hexmask.long 0x0 0.--31. 1. "UPPER_TARGET_RW,Forms bits [63:32] of the start address (Upper Target part) of the new address of the translated region. In systems with a 32-bit address space this register is not used and therefore writing to this register has no effect. Note: This.." repeat.end tree.end tree "PF0_PORT_LOGIC (Port Logic)" group.long (0x0+0x700)++0x27 line.long 0x0 "ACK_LATENCY_TIMER_OFF,Ack Latency Timer and Replay Timer Register." hexmask.long.word 0x0 16.--31. 1. "REPLAY_TIME_LIMIT,Replay Timer Limit. The replay timer expires when it reaches this limit. The controller initiates a replay upon reception of a NAK or when the replay timer expires. For more details see 'Transmit Replay'. You can modify the effective.." newline hexmask.long.word 0x0 0.--15. 1. "ROUND_TRIP_LATENCY_TIME_LIMIT,Ack Latency Timer Limit. The Ack latency timer expires when it reaches this limit. For more details see 'Ack Scheduling'. You can modify the effective timer limit with the TIMER_MOD_ACK_NAK field of the.." line.long 0x4 "VENDOR_SPEC_DLLP_OFF,Vendor Specific DLLP Register." hexmask.long 0x4 0.--31. 1. "VENDOR_SPEC_DLLP,Vendor Specific DLLP Register. Used to send a specific PCI Express DLLP. Your application writes the 8-bit DLLP Type and 24-bits of Payload data into this register then sets the field VENDOR_SPECIFIC_DLLP_REQ of PORT_LINK_CTRL_OFF to.." line.long 0x8 "PORT_FORCE_OFF,Port Force Link Register." hexmask.long.byte 0x8 24.--31. 1. "RSVDP_24,Reserved for future use." newline bitfld.long 0x8 23. "DO_DESKEW_FOR_SRIS,Use the transitions from TS2 to Logical Idle Symbol SKP OS to Logical Idle Symbol EIEOS to Logical Idle Symbol and FTS Sequence to SKP OS to do deskew instead of using received SKP OS or TS1 to TS2 transition if DO_DESKEW_FOR_SRIS.." "0,1" newline rbitfld.long 0x8 22. "RSVDP_22,Reserved for future use." "0,1" newline hexmask.long.byte 0x8 16.--21. 1. "LINK_STATE,Forced LTSSM State. The LTSSM state that the controller is forced to when you set the FORCE_EN bit (Force Link). LTSSM state encoding is defined by the lts_state variable in workspace/src/Layer1/smlh_ltssm.v. Note: This register field is sticky." newline bitfld.long 0x8 15. "FORCE_EN,Force Link. The controller supports a testing and debug capability to allow your software to force the LTSSM state machine into a specific state and to force the controller to transmit a specific Link Command. Asserting this bit triggers the.." "0,1" newline rbitfld.long 0x8 12.--14. "RSVDP_12,Reserved for future use." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x8 8.--11. 1. "FORCED_LTSSM,Forced Link Command. The link command that the controller is forced to transmit when you set FORCE_EN bit (Force Link). Link command encoding is defined by the ltssm_cmd variable in workspace/src/Layer1/smlh_ltssm.v. Note: This register.." newline hexmask.long.byte 0x8 0.--7. 1. "LINK_NUM,Link Number. Not used for endpoint. Not used for M-PCIe. Note: This register field is sticky." line.long 0xC "ACK_F_ASPM_CTRL_OFF,Ack Frequency and L0-L1 ASPM Control Register." rbitfld.long 0xC 31. "RSVDP_31,Reserved for future use." "0,1" newline bitfld.long 0xC 30. "ENTER_ASPM,ASPM L1 Entry Control. - 1: Controller enters ASPM L1 after a period in which it has been idle. - 0: Controller enters ASPM L1 only after idle period during which both receive and transmit are in L0s. Note: This register field is sticky." "Controller enters ASPM L1 only after idle period..,Controller enters ASPM L1 after a period in.." newline bitfld.long 0xC 27.--29. "L1_ENTRANCE_LATENCY,L1 Entrance Latency. Value range is: - 000: 1 us - 001: 2 us - 010: 4 us - 011: 8 us - 100: 16 us - 101: 32 us - 110 or 111: 64 us Note: Programming this timer with a value greater that 32us has no effect unless extended sync is used.." "0,1,2,3,4,5,6,7" newline bitfld.long 0xC 24.--26. "L0S_ENTRANCE_LATENCY,L0s Entrance Latency. Values correspond to: - 000: 1 us - 001: 2 us - 010: 3 us - 011: 4 us - 100: 5 us - 101: 6 us - 110 or 111: 7 us This field is applicable to STALL while in L0 for M-PCIe. Note: This register field is sticky." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0xC 16.--23. 1. "COMMON_CLK_N_FTS,Common Clock N_FTS. This is the N_FTS when common clock is used. The number of Fast Training Sequence ordered sets to be transmitted when transitioning from L0s to L0. The maximum number of FTS ordered-sets that a component can request.." newline hexmask.long.byte 0xC 8.--15. 1. "ACK_N_FTS,N_FTS. The number of Fast Training Sequence ordered sets to be transmitted when transitioning from L0s to L0. The maximum number of FTS ordered-sets that a component can request is 255. The controller does not support a value of zero; a value.." newline hexmask.long.byte 0xC 0.--7. 1. "ACK_FREQ,Ack Frequency. The controller accumulates the number of pending ACKs specified here (up to 255) before scheduling an ACK DLLP. - 0: Indicates that this Ack Frequency Counter feature is turned off. The controller generates a low-priority ACK.." line.long 0x10 "PORT_LINK_CTRL_OFF,Port Link Control Register." hexmask.long.byte 0x10 28.--31. 1. "RSVDP_28,Reserved for future use." newline bitfld.long 0x10 27. "TRANSMIT_LANE_REVERSALE_ENABLE,TRANSMIT_LANE_REVERSALE_ENABLE is an internally reserved field. Do not use. Note: This register field is sticky." "0,1" newline bitfld.long 0x10 26. "EXTENDED_SYNCH,EXTENDED_SYNCH is an internally reserved field. Do not use. Note: This register field is sticky." "0,1" newline bitfld.long 0x10 25. "CORRUPT_LCRC_ENABLE,CORRUPT_LCRC_ENABLE is an internally reserved field. Do not use. Note: This register field is sticky." "0,1" newline bitfld.long 0x10 24. "BEACON_ENABLE,BEACON_ENABLE is an internally reserved field. Do not use. Note: This register field is sticky." "0,1" newline hexmask.long.byte 0x10 16.--21. 1. "LINK_CAPABLE,Link Mode Enable. Sets the number of lanes in the link that you want to connect to the link partner. When you have unused lanes in your system then you must change the value in this register to reflect the number of lanes. You must also.." newline hexmask.long.byte 0x10 12.--15. 1. "RSVDP_12,Reserved for future use." newline hexmask.long.byte 0x10 8.--11. 1. "LINK_RATE,LINK_RATE is an internally reserved field. Do not use. Note: This register field is sticky." newline bitfld.long 0x10 7. "FAST_LINK_MODE,Fast Link Mode. Sets all internal LTSSM millisecond timers to Fast Mode for speeding up simulation. Forces the LTSSM training (link initialization) to use shorter time-outs and to link up faster. The default scaling factor can be changed.." "0,1" newline bitfld.long 0x10 6. "LINK_DISABLE,LINK_DISABLE is an internally reserved field. Do not use. Note: This register field is sticky." "0,1" newline bitfld.long 0x10 5. "DLL_LINK_EN,DLL Link Enable. Enables link initialization. When DLL Link Enable =0 the controller does not transmit InitFC DLLPs and does not establish a link. Note: This register field is sticky." "0,1" newline rbitfld.long 0x10 4. "RSVDP_4,Reserved for future use." "0,1" newline bitfld.long 0x10 3. "RESET_ASSERT,Reset Assert. Triggers a recovery and forces the LTSSM to the hot reset state (downstream port only). Note: This register field is sticky." "0,1" newline bitfld.long 0x10 2. "LOOPBACK_ENABLE,Loopback Enable. Turns on loopback. For more details see 'Loopback'. For M-PCIe to force the master to enter Digital Loopback mode you must set this field to '1' during Configuration.start state(initial discovery/configuration). M-PCIe.." "0,1" newline bitfld.long 0x10 1. "SCRAMBLE_DISABLE,Scramble Disable. Turns off data scrambling. Note: This register field is sticky." "0,1" newline bitfld.long 0x10 0. "VENDOR_SPECIFIC_DLLP_REQ,Vendor Specific DLLP Request. When software writes a '1' to this bit the controller transmits the DLLP contained in the VENDOR_SPEC_DLLP field of VENDOR_SPEC_DLLP_OFF. Reading from this self-clearing register field always.." "0,1" line.long 0x14 "LANE_SKEW_OFF,Lane Skew Register." bitfld.long 0x14 31. "DISABLE_LANE_TO_LANE_DESKEW,Disable Lane-to-Lane Deskew. Causes the controller to disable the internal Lane-to-Lane deskew logic. Note: This register field is sticky." "0,1" newline hexmask.long.byte 0x14 27.--30. 1. "IMPLEMENT_NUM_LANES,Implementation-specific Number of Lanes. Set the implementation-specific number of lanes. Allowed values are: - 4'b0000: 1 lane - 4'b0001: 2 lanes - 4'b0011: 4 lanes - 4'b0111: 8 lanes - 4'b1111: 16 lanes The number of lanes to be.." newline bitfld.long 0x14 26. "ELASTIC_BUFFER_MODE,Selects Elasticity Buffer operating mode: 0: Nominal Half Full Buffer mode 1: Nominal Empty Buffer Mode Note: This register field is sticky." "Nominal Half Full Buffer mode,Nominal Empty Buffer Mode" newline bitfld.long 0x14 25. "ACK_NAK_DISABLE,Ack/Nak Disable. Prevents the controller from sending ACK and NAK DLLPs. Note: This register field is sticky." "0,1" newline bitfld.long 0x14 24. "FLOW_CTRL_DISABLE,Flow Control Disable. Prevents the controller from sending FC DLLPs. Note: This register field is sticky." "0,1" newline hexmask.long.tbyte 0x14 0.--23. 1. "INSERT_LANE_SKEW,INSERT_LANE_SKEW is an internally reserved field. Do not use. Note: This register field is sticky." line.long 0x18 "TIMER_CTRL_MAX_FUNC_NUM_OFF,Timer Control and Max Function Number Register." rbitfld.long 0x18 31. "RSVDP_31,Reserved for future use." "0,1" newline bitfld.long 0x18 29.--30. "FAST_LINK_SCALING_FACTOR,Fast Link Timer Scaling Factor. Sets the scaling factor of LTSSM timer when FAST_LINK_MODE field in PORT_LINK_CTRL_OFF is set to '1'. - 0: Scaling Factor is 1024 (1ms is 1us *a) - 1: Scaling Factor is 256 (1ms is 4us) - 2:.." "Scaling Factor is 1024,Scaling Factor is 256,Scaling Factor is 64,Scaling Factor is 16" newline hexmask.long.byte 0x18 24.--28. 1. "UPDATE_FREQ_TIMER,UPDATE_FREQ_TIMER is an internally reserved field. Do not use. Note: This register field is sticky." newline hexmask.long.byte 0x18 19.--23. 1. "TIMER_MOD_ACK_NAK,Ack Latency Timer Modifier. Increases the timer value for the Ack latency timer in increments of 64 clock cycles. A value of '0' represents no modification to the timer value. For more details see the ROUND_TRIP_LATENCY_TIME_LIMIT.." newline hexmask.long.byte 0x18 14.--18. 1. "TIMER_MOD_REPLAY_TIMER,Replay Timer Limit Modifier. Increases the time-out value for the replay timer in increments of 64 clock cycles at Gen1 or Gen2 speed and in increments of 256 clock cycles at Gen3 speed. A value of '0' represents no modification.." newline hexmask.long.byte 0x18 8.--13. 1. "RSVDP_8,Reserved for future use." newline hexmask.long.byte 0x18 0.--7. 1. "MAX_FUNC_NUM,Maximum function number that can be used in a request. Configuration requests targeted at function numbers above this value are returned with UR (unsupported request). Note: This register field is sticky." line.long 0x1C "SYMBOL_TIMER_FILTER_1_OFF,Symbol Timer Register and Filter Mask 1 Register. The Filter Mask 1 Register modifies the RADM filtering and error handling rules. For more details. see the 'Receive Filtering' section. In each case. '0' applies the associated.." hexmask.long.word 0x1C 16.--31. 1. "MASK_RADM_1,Filter Mask 1. The Filter Mask 1 Register modifies the RADM filtering and error handling rules. For more details see the 'Receive Filtering' section. In each case '0' applies the associated filtering rule and '1' masks the associated.." newline bitfld.long 0x1C 15. "DISABLE_FC_WD_TIMER,Disable FC Watchdog Timer. Note: This register field is sticky." "0,1" newline hexmask.long.byte 0x1C 11.--14. 1. "EIDLE_TIMER,EIDLE_TIMER is an internally reserved field. Do not use. Note: This register field is sticky." newline hexmask.long.word 0x1C 0.--10. 1. "SKP_INT_VAL,SKP Interval Value. The number of symbol times to wait between transmitting SKP ordered sets. Note that the controller actually waits the number of symbol times in this register plus 1 between transmitting SKP ordered sets. Your application.." line.long 0x20 "FILTER_MASK_2_OFF,Filter Mask 2 Register. This register modifies the RADM filtering and error handling rules. For more details. see the 'Receive Filtering' section. In each case. '0' applies the associated filtering rule and '1' masks the associated.." hexmask.long 0x20 0.--31. 1. "MASK_RADM_2,Filter Mask 2. This field modifies the RADM filtering and error handling rules. For more details see the 'Receive Filtering' section. In each case '0' applies the associated filtering rule and '1' masks the associated filtering rule." line.long 0x24 "AMBA_MUL_OB_DECOMP_NP_SUB_REQ_CTRL_OFF,AMBA Multiple Outbound Decomposed NP SubRequests Control Register." hexmask.long 0x24 1.--31. 1. "RSVDP_1,Reserved for future use." newline bitfld.long 0x24 0. "OB_RD_SPLIT_BURST_EN,Enable AMBA Multiple Outbound Decomposed NP SubRequests. This bit when set to '0' disables the possibility of having multiple outstanding non-posted requests that were derived from decomposition of an outbound AMBA request. For more.." "0,1" rgroup.long (0x28+0x700)++0x13 line.long 0x0 "PL_DEBUG0_OFF,Debug Register 0" hexmask.long 0x0 0.--31. 1. "DEB_REG_0,The value on cxpl_debug_info[31:0]." line.long 0x4 "PL_DEBUG1_OFF,Debug Register 1" hexmask.long 0x4 0.--31. 1. "DEB_REG_1,The value on cxpl_debug_info[63:32]." line.long 0x8 "TX_P_FC_CREDIT_STATUS_OFF,Transmit Posted FC Credit Status" hexmask.long.word 0x8 20.--31. 1. "RSVDP_TX_P_FC_CREDIT_STATUS,Reserved for future use." newline hexmask.long.byte 0x8 12.--19. 1. "TX_P_HEADER_FC_CREDIT,Transmit Posted Header FC Credits. The posted Header credits advertised by the receiver at the other end of the link updated with each UpdateFC DLLP. Default value depends on the number of advertised credits for header and data.." newline hexmask.long.word 0x8 0.--11. 1. "TX_P_DATA_FC_CREDIT,Transmit Posted Data FC Credits. The posted Data credits advertised by the receiver at the other end of the link updated with each UpdateFC DLLP. Default value depends on the number of advertised credits for header and data Scaled.." line.long 0xC "TX_NP_FC_CREDIT_STATUS_OFF,Transmit Non-Posted FC Credit Status" hexmask.long.word 0xC 20.--31. 1. "RSVDP_TX_NP_FC_CREDIT_STATUS,Reserved for future use." newline hexmask.long.byte 0xC 12.--19. 1. "TX_NP_HEADER_FC_CREDIT,Transmit Non-Posted Header FC Credits. The non-posted Header credits advertised by the receiver at the other end of the link updated with each UpdateFC DLLP. Default value depends on the number of advertised credits for header and.." newline hexmask.long.word 0xC 0.--11. 1. "TX_NP_DATA_FC_CREDIT,Transmit Non-Posted Data FC Credits. The non-posted Data credits advertised by the receiver at the other end of the link updated with each UpdateFC DLLP. Default value depends on the number of advertised credits for header and data.." line.long 0x10 "TX_CPL_FC_CREDIT_STATUS_OFF,Transmit Completion FC Credit Status" hexmask.long.word 0x10 20.--31. 1. "RSVDP_TX_CPL_FC_CREDIT_STATUS,Reserved for future use." newline hexmask.long.byte 0x10 12.--19. 1. "TX_CPL_HEADER_FC_CREDIT,Transmit Completion Header FC Credits. The Completion Header credits advertised by the receiver at the other end of the link updated with each UpdateFC DLLP. Default value depends on the number of advertised credits for header.." newline hexmask.long.word 0x10 0.--11. 1. "TX_CPL_DATA_FC_CREDIT,Transmit Completion Data FC Credits. The Completion Data credits advertised by the receiver at the other end of the link updated with each UpdateFC DLLP. Default value depends on the number of advertised credits for header and data.." group.long (0x3C+0x700)++0x3 line.long 0x0 "QUEUE_STATUS_OFF,Queue Status" bitfld.long 0x0 31. "TIMER_MOD_FLOW_CONTROL_EN,FC Latency Timer Override Enable. When this bit is set the value from the 'FC Latency Timer Override Value' field in this register will override the FC latency timer value that the controller calculates according to the PCIe.." "0,1" newline rbitfld.long 0x0 29.--30. "RSVDP_29,Reserved for future use." "0,1,2,3" newline hexmask.long.word 0x0 16.--28. 1. "TIMER_MOD_FLOW_CONTROL,FC Latency Timer Override Value. When you set the 'FC Latency Timer Override Enable' in this register the value in this field will override the FC latency timer value that the controller calculates according to the PCIe.." newline rbitfld.long 0x0 13. "RX_SERIALIZATION_Q_NON_EMPTY,Receive Serialization Queue Not Empty. Indicates there is data in the serialization queue." "0,1" newline hexmask.long.word 0x0 4.--12. 1. "RSVDP_4,Reserved for future use." newline bitfld.long 0x0 3. "RX_QUEUE_OVERFLOW,Receive Credit Queue Overflow. Indicates insufficient buffer space available to write to the P/NP/CPL credit queue." "0,1" newline rbitfld.long 0x0 2. "RX_QUEUE_NON_EMPTY,Receive Credit Queue Not Empty. Indicates there is data in one or more of the receive buffers." "0,1" newline rbitfld.long 0x0 1. "TX_RETRY_BUFFER_NE,Transmit Retry Buffer Not Empty. Indicates that there is data in the transmit retry buffer." "0,1" newline rbitfld.long 0x0 0. "RX_TLP_FC_CREDIT_NON_RETURN,Received TLP FC Credits Not Returned. Indicates that the controller has received a TLP but has not yet sent an UpdateFC DLLP indicating that the credits for that TLP have been restored by the receiver at the other end of the.." "0,1" rgroup.long (0x40+0x700)++0x7 line.long 0x0 "VC_TX_ARBI_1_OFF,VC Transmit Arbitration Register 1" hexmask.long.byte 0x0 24.--31. 1. "WRR_WEIGHT_VC_3,WRR Weight for VC3. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R" newline hexmask.long.byte 0x0 16.--23. 1. "WRR_WEIGHT_VC_2,WRR Weight for VC2. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R" newline hexmask.long.byte 0x0 8.--15. 1. "WRR_WEIGHT_VC_1,WRR Weight for VC1. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R" newline hexmask.long.byte 0x0 0.--7. 1. "WRR_WEIGHT_VC_0,WRR Weight for VC0. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R" line.long 0x4 "VC_TX_ARBI_2_OFF,VC Transmit Arbitration Register 2" hexmask.long.byte 0x4 24.--31. 1. "WRR_WEIGHT_VC_7,WRR Weight for VC7. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R" newline hexmask.long.byte 0x4 16.--23. 1. "WRR_WEIGHT_VC_6,WRR Weight for VC6. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R" newline hexmask.long.byte 0x4 8.--15. 1. "WRR_WEIGHT_VC_5,WRR Weight for VC5. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R" newline hexmask.long.byte 0x4 0.--7. 1. "WRR_WEIGHT_VC_4,WRR Weight for VC4. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R" group.long (0x48+0x700)++0xB line.long 0x0 "VC0_P_RX_Q_CTRL_OFF,Segmented-Buffer VC0 Posted Receive Queue Control." bitfld.long 0x0 31. "VC_ORDERING_RX_Q,VC Ordering for Receive Queues. Determines the VC ordering rule for the receive queues used only in the segmented-buffer configuration: - 1: Strict ordering higher numbered VCs have higher priority - 0: Round robin Note: This register.." "Round robin,Strict ordering" newline bitfld.long 0x0 30. "TLP_TYPE_ORDERING_VC0,TLP Type Ordering for VC0. Determines the TLP type ordering rule for VC0 receive queues used only in the segmented-buffer configuration: - 1: PCIe ordering rules (recommended) - 0: Strict ordering: posted completion then.." "Strict ordering: posted,PCIe ordering rules" newline bitfld.long 0x0 28.--29. "RESERVED5,Reserved. Note: This register field is sticky." "0,1,2,3" newline bitfld.long 0x0 26.--27. "VC0_P_DATA_SCALE,VC0 Scale Posted Data Credites. Note: This register field is sticky." "0,1,2,3" newline bitfld.long 0x0 24.--25. "VC0_P_HDR_SCALE,VC0 Scale Posted Header Credites. Note: This register field is sticky." "0,1,2,3" newline bitfld.long 0x0 21.--23. "VC0_P_TLP_Q_MODE,Reserved. Note: This register field is sticky." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 20. "RESERVED4,Reserved. Note: This register field is sticky." "0,1" newline hexmask.long.byte 0x0 12.--19. 1. "VC0_P_HEADER_CREDIT,VC0 Posted Header Credits. The number of initial posted header credits for VC0 used only in the segmented-buffer configuration. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R (sticky) Note: This.." newline hexmask.long.word 0x0 0.--11. 1. "VC0_P_DATA_CREDIT,VC0 Posted Data Credits. The number of initial posted data credits for VC0 used only in the segmented-buffer configuration. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R (sticky) Note: This.." line.long 0x4 "VC0_NP_RX_Q_CTRL_OFF,Segmented-Buffer VC0 Non-Posted Receive Queue Control." hexmask.long.byte 0x4 28.--31. 1. "RESERVED7,Reserved. Note: This register field is sticky." newline bitfld.long 0x4 26.--27. "VC0_NP_DATA_SCALE,VC0 Scale Non-Posted Data Credites. Note: This register field is sticky." "0,1,2,3" newline bitfld.long 0x4 24.--25. "VC0_NP_HDR_SCALE,VC0 Scale Non-Posted Header Credites. Note: This register field is sticky." "0,1,2,3" newline bitfld.long 0x4 21.--23. "VC0_NP_TLP_Q_MODE,Reserved. Note: This register field is sticky." "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 20. "RESERVED6,Reserved. Note: This register field is sticky." "0,1" newline hexmask.long.byte 0x4 12.--19. 1. "VC0_NP_HEADER_CREDIT,VC0 Non-Posted Header Credits. The number of initial non-posted header credits for VC0 used only in the segmented-buffer configuration. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R (sticky).." newline hexmask.long.word 0x4 0.--11. 1. "VC0_NP_DATA_CREDIT,VC0 Non-Posted Data Credits. The number of initial non-posted data credits for VC0 used only in the segmented-buffer configuration. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R (sticky) Note:.." line.long 0x8 "VC0_CPL_RX_Q_CTRL_OFF,Segmented-Buffer VC0 Completion Receive Queue Control." hexmask.long.byte 0x8 28.--31. 1. "RESERVED9,Reserved. Note: This register field is sticky." newline bitfld.long 0x8 26.--27. "VC0_CPL_DATA_SCALE,VC0 Scale CPL Data Credites. Note: This register field is sticky." "0,1,2,3" newline bitfld.long 0x8 24.--25. "VC0_CPL_HDR_SCALE,VC0 Scale CPL Header Credites. Note: This register field is sticky." "0,1,2,3" newline bitfld.long 0x8 21.--23. "VC0_CPL_TLP_Q_MODE,Reserved. Note: This register field is sticky." "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 20. "RESERVED8,Reserved. Note: This register field is sticky." "0,1" newline hexmask.long.byte 0x8 12.--19. 1. "VC0_CPL_HEADER_CREDIT,VC0 Completion Header Credits. The number of initial Completion header credits for VC0 used only in the segmented-buffer configuration. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R (sticky).." newline hexmask.long.word 0x8 0.--11. 1. "VC0_CPL_DATA_CREDIT,VC0 Completion Data Credits. The number of initial Completion data credits for VC0 used only in the segmented-buffer configuration. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R (sticky) Note:.." group.long (0x10C+0x700)++0x3 line.long 0x0 "GEN2_CTRL_OFF,This register is used to control various functions of the controller related to link training. lane reversal. and equalization." rbitfld.long 0x0 31. "RSVDP_31,Reserved for future use." "0,1" newline rbitfld.long 0x0 22.--23. "RSVDP_22,Reserved for future use." "0,1,2,3" newline bitfld.long 0x0 21. "GEN1_EI_INFERENCE,Electrical Idle Inference Mode at Gen1 Rate. Programmable mode to determine inferred electrical idle (EI) in Recovery.Speed or Loopback.Active (as slave) state at Gen1 speed by looking for a '1' value on RxElecIdle instead of looking.." "Use RxElecIdle signal to infer Electrical Idle,Use RxValid signal to infer Electrical Idle" newline bitfld.long 0x0 20. "SEL_DEEMPHASIS,Used to set the de-emphasis level for upstream ports. This bit selects the level of de-emphasis the link operates at. - 0: -6 dB - 1: -3.5 dB This field is reserved (fixed to '0') for M-PCIe. Note: The access attributes of this field are.." "0,1" newline bitfld.long 0x0 19. "CONFIG_TX_COMP_RX,Config Tx Compliance Receive Bit. When set to 1 signals LTSSM to transmit TS ordered sets with the compliance receive bit assert (equal to '1'). This field is reserved (fixed to '0') for M-PCIe. Note: The access attributes of this.." "0,1" newline bitfld.long 0x0 18. "CONFIG_PHY_TX_CHANGE,Config PHY Tx Swing. Controls the PHY transmitter voltage swing level. The controller drives the mac_phy_txswing output from this register bit field. - 0: Full Swing - 1: Low Swing This field is reserved (fixed to '0') for M-PCIe." "Full Swing,Low Swing" newline bitfld.long 0x0 17. "DIRECT_SPEED_CHANGE,Directed Speed Change. Writing '1' to this field instructs the LTSSM to initiate a speed change to Gen2 or Gen3 after the link is initialized at Gen1 speed. When the speed change occurs the controller will clear the contents of this.." "0,1" newline bitfld.long 0x0 16. "AUTO_LANE_FLIP_CTRL_EN,Enable Auto flipping of the lanes. You must set the CX_AUTO_LANE_FLIP_CTRL_EN configuration parameter to include the hardware for this feature in the controller. For more details see the 'Lane Reversal' appendix in the Databook." "0,1" newline bitfld.long 0x0 13.--15. "PRE_DET_LANE,Predetermined Lane for Auto Flip. This field defines which physical lane is connected to logical Lane0 by the flip operation performed in Detect. This field is used to restrict the receiver detect procedure to a particular lane when the.." "LANE0,LANE1,LANE3,LANE7,LANE15,?,?,?" newline hexmask.long.byte 0x0 8.--12. 1. "NUM_OF_LANES,Predetermined Number of Lanes. Defines the number of lanes which are connected and not bad. Used to limit the effective link width to ignore 'broken' or 'unused' lanes that detect a receiver. Indicates the number of lanes to check for exit.." newline hexmask.long.byte 0x0 0.--7. 1. "FAST_TRAINING_SEQ,Sets the Number of Fast Training Sequences (N_FTS) that the controller advertises as its N_FTS during Gen2 or Gen3 link training. This value is used to inform the link partner about the PHY's ability to recover synchronization after a.." rgroup.long (0x110+0x700)++0x3 line.long 0x0 "PHY_STATUS_OFF,PHY Status Register. Memory mapped register from phy_cfg_status GPIO input pins." hexmask.long 0x0 0.--31. 1. "PHY_STATUS,PHY Status. Data received directly from the phy_cfg_status bus. These is a GPIO register reflecting the values on the static phy_cfg_status input signals. The usage is left completely to the user and does not in any way influence controller.." group.long (0x114+0x700)++0x3 line.long 0x0 "PHY_CONTROL_OFF,PHY Control Register. Memory mapped register to cfg_phy_control GPIO output pins." hexmask.long 0x0 0.--31. 1. "PHY_CONTROL,PHY Control. Data sent directly to the cfg_phy_control bus. These is a GPIO register driving the values on the static cfg_phy_control output signals. The usage is left completely to the user and does not in any way influence controller.." group.long (0x11C+0x700)++0x77 line.long 0x0 "TRGT_MAP_CTRL_OFF,Programmable Target Map Control Register." hexmask.long.word 0x0 21.--31. 1. "TARGET_MAP_RESERVED_21_31,Reserved. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R (sticky)" newline hexmask.long.byte 0x0 16.--20. 1. "TARGET_MAP_INDEX,The number of the PF Function on which the Target Values are set. This register does not respect the Byte Enable setting. any write will affect all register bits." newline rbitfld.long 0x0 13.--15. "TARGET_MAP_RESERVED_13_15,Reserved. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R (sticky)" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 6. "TARGET_MAP_ROM,Target Value for the ROM page of the PF Function selected by the index number. This register does not respect the Byte Enable setting. any write will affect all register bits." "0,1" newline hexmask.long.byte 0x0 0.--5. 1. "TARGET_MAP_PF,Target Values for each BAR on the PF Function selected by the index number. This register does not respect the Byte Enable setting. any write will affect all register bits." line.long 0x4 "MSI_CTRL_ADDR_OFF,Integrated MSI Reception Module (iMRM) Address Register." hexmask.long 0x4 0.--31. 1. "MSI_CTRL_ADDR,Integrated MSI Reception Module Address. System specified address for MSI memory write transaction termination. Within the AXI Bridge every received Memory Write request is examined to see if it targets the MSI Address that has been.." line.long 0x8 "MSI_CTRL_UPPER_ADDR_OFF,Integrated MSI Reception Module Upper Address Register." hexmask.long 0x8 0.--31. 1. "MSI_CTRL_UPPER_ADDR,Integrated MSI Reception Module Upper Address. System specified upper address for MSI memory write transaction termination. Allows functions to support a 64-bit MSI address. Note: This register field is sticky." line.long 0xC "MSI_CTRL_INT_0_EN_OFF,Integrated MSI Reception Module Interrupt#i Enable Register." hexmask.long 0xC 0.--31. 1. "MSI_CTRL_INT_0_EN,MSI Interrupt#i Enable. Specifies which interrupts are enabled. When an MSI is received from a disabled interrupt no status bit gets set in MSI controller interrupt status register. Each bit corresponds to a single MSI Interrupt.." line.long 0x10 "MSI_CTRL_INT_0_MASK_OFF,Integrated MSI Reception Module Interrupt#i Mask Register." hexmask.long 0x10 0.--31. 1. "MSI_CTRL_INT_0_MASK,MSI Interrupt#i Mask. Allows enabled interrupts to be masked. When an MSI is received for a masked interrupt the corresponding status bit gets set in the interrupt status register but the msi_ctrl_int output is not set HIGH. Each bit.." line.long 0x14 "MSI_CTRL_INT_0_STATUS_OFF,Integrated MSI Reception Module Interrupt#i Status Register." hexmask.long 0x14 0.--31. 1. "MSI_CTRL_INT_0_STATUS,MSI Interrupt#i Status. When an MSI is detected for EP#i one bit in this register is set. The decoding of the data payload of the MSI Memory Write request determines which bit gets set. A status is bit is cleared by writing a 1 to.." line.long 0x18 "MSI_CTRL_INT_1_EN_OFF,Integrated MSI Reception Module Interrupt#i Enable Register." hexmask.long 0x18 0.--31. 1. "MSI_CTRL_INT_1_EN,MSI Interrupt#i Enable. Specifies which interrupts are enabled. When an MSI is received from a disabled interrupt no status bit gets set in MSI controller interrupt status register. Each bit corresponds to a single MSI Interrupt.." line.long 0x1C "MSI_CTRL_INT_1_MASK_OFF,Integrated MSI Reception Module Interrupt#i Mask Register." hexmask.long 0x1C 0.--31. 1. "MSI_CTRL_INT_1_MASK,MSI Interrupt#i Mask. Allows enabled interrupts to be masked. When an MSI is received for a masked interrupt the corresponding status bit gets set in the interrupt status register but the msi_ctrl_int output is not set HIGH. Each bit.." line.long 0x20 "MSI_CTRL_INT_1_STATUS_OFF,Integrated MSI Reception Module Interrupt#i Status Register." hexmask.long 0x20 0.--31. 1. "MSI_CTRL_INT_1_STATUS,MSI Interrupt#i Status. When an MSI is detected for EP#i one bit in this register is set. The decoding of the data payload of the MSI Memory Write request determines which bit gets set. A status is bit is cleared by writing a 1 to.." line.long 0x24 "MSI_CTRL_INT_2_EN_OFF,Integrated MSI Reception Module Interrupt#i Enable Register." hexmask.long 0x24 0.--31. 1. "MSI_CTRL_INT_2_EN,MSI Interrupt#i Enable. Specifies which interrupts are enabled. When an MSI is received from a disabled interrupt no status bit gets set in MSI controller interrupt status register. Each bit corresponds to a single MSI Interrupt.." line.long 0x28 "MSI_CTRL_INT_2_MASK_OFF,Integrated MSI Reception Module Interrupt#i Mask Register." hexmask.long 0x28 0.--31. 1. "MSI_CTRL_INT_2_MASK,MSI Interrupt#i Mask. Allows enabled interrupts to be masked. When an MSI is received for a masked interrupt the corresponding status bit gets set in the interrupt status register but the msi_ctrl_int output is not set HIGH. Each bit.." line.long 0x2C "MSI_CTRL_INT_2_STATUS_OFF,Integrated MSI Reception Module Interrupt#i Status Register." hexmask.long 0x2C 0.--31. 1. "MSI_CTRL_INT_2_STATUS,MSI Interrupt#i Status. When an MSI is detected for EP#i one bit in this register is set. The decoding of the data payload of the MSI Memory Write request determines which bit gets set. A status is bit is cleared by writing a 1 to.." line.long 0x30 "MSI_CTRL_INT_3_EN_OFF,Integrated MSI Reception Module Interrupt#i Enable Register." hexmask.long 0x30 0.--31. 1. "MSI_CTRL_INT_3_EN,MSI Interrupt#i Enable. Specifies which interrupts are enabled. When an MSI is received from a disabled interrupt no status bit gets set in MSI controller interrupt status register. Each bit corresponds to a single MSI Interrupt.." line.long 0x34 "MSI_CTRL_INT_3_MASK_OFF,Integrated MSI Reception Module Interrupt#i Mask Register." hexmask.long 0x34 0.--31. 1. "MSI_CTRL_INT_3_MASK,MSI Interrupt#i Mask. Allows enabled interrupts to be masked. When an MSI is received for a masked interrupt the corresponding status bit gets set in the interrupt status register but the msi_ctrl_int output is not set HIGH. Each bit.." line.long 0x38 "MSI_CTRL_INT_3_STATUS_OFF,Integrated MSI Reception Module Interrupt#i Status Register." hexmask.long 0x38 0.--31. 1. "MSI_CTRL_INT_3_STATUS,MSI Interrupt#i Status. When an MSI is detected for EP#i one bit in this register is set. The decoding of the data payload of the MSI Memory Write request determines which bit gets set. A status is bit is cleared by writing a 1 to.." line.long 0x3C "MSI_CTRL_INT_4_EN_OFF,Integrated MSI Reception Module Interrupt#i Enable Register." hexmask.long 0x3C 0.--31. 1. "MSI_CTRL_INT_4_EN,MSI Interrupt#i Enable. Specifies which interrupts are enabled. When an MSI is received from a disabled interrupt no status bit gets set in MSI controller interrupt status register. Each bit corresponds to a single MSI Interrupt.." line.long 0x40 "MSI_CTRL_INT_4_MASK_OFF,Integrated MSI Reception Module Interrupt#i Mask Register." hexmask.long 0x40 0.--31. 1. "MSI_CTRL_INT_4_MASK,MSI Interrupt#i Mask. Allows enabled interrupts to be masked. When an MSI is received for a masked interrupt the corresponding status bit gets set in the interrupt status register but the msi_ctrl_int output is not set HIGH. Each bit.." line.long 0x44 "MSI_CTRL_INT_4_STATUS_OFF,Integrated MSI Reception Module Interrupt#i Status Register." hexmask.long 0x44 0.--31. 1. "MSI_CTRL_INT_4_STATUS,MSI Interrupt#i Status. When an MSI is detected for EP#i one bit in this register is set. The decoding of the data payload of the MSI Memory Write request determines which bit gets set. A status is bit is cleared by writing a 1 to.." line.long 0x48 "MSI_CTRL_INT_5_EN_OFF,Integrated MSI Reception Module Interrupt#i Enable Register." hexmask.long 0x48 0.--31. 1. "MSI_CTRL_INT_5_EN,MSI Interrupt#i Enable. Specifies which interrupts are enabled. When an MSI is received from a disabled interrupt no status bit gets set in MSI controller interrupt status register. Each bit corresponds to a single MSI Interrupt.." line.long 0x4C "MSI_CTRL_INT_5_MASK_OFF,Integrated MSI Reception Module Interrupt#i Mask Register." hexmask.long 0x4C 0.--31. 1. "MSI_CTRL_INT_5_MASK,MSI Interrupt#i Mask. Allows enabled interrupts to be masked. When an MSI is received for a masked interrupt the corresponding status bit gets set in the interrupt status register but the msi_ctrl_int output is not set HIGH. Each bit.." line.long 0x50 "MSI_CTRL_INT_5_STATUS_OFF,Integrated MSI Reception Module Interrupt#i Status Register." hexmask.long 0x50 0.--31. 1. "MSI_CTRL_INT_5_STATUS,MSI Interrupt#i Status. When an MSI is detected for EP#i one bit in this register is set. The decoding of the data payload of the MSI Memory Write request determines which bit gets set. A status is bit is cleared by writing a 1 to.." line.long 0x54 "MSI_CTRL_INT_6_EN_OFF,Integrated MSI Reception Module Interrupt#i Enable Register." hexmask.long 0x54 0.--31. 1. "MSI_CTRL_INT_6_EN,MSI Interrupt#i Enable. Specifies which interrupts are enabled. When an MSI is received from a disabled interrupt no status bit gets set in MSI controller interrupt status register. Each bit corresponds to a single MSI Interrupt.." line.long 0x58 "MSI_CTRL_INT_6_MASK_OFF,Integrated MSI Reception Module Interrupt#i Mask Register." hexmask.long 0x58 0.--31. 1. "MSI_CTRL_INT_6_MASK,MSI Interrupt#i Mask. Allows enabled interrupts to be masked. When an MSI is received for a masked interrupt the corresponding status bit gets set in the interrupt status register but the msi_ctrl_int output is not set HIGH. Each bit.." line.long 0x5C "MSI_CTRL_INT_6_STATUS_OFF,Integrated MSI Reception Module Interrupt#i Status Register." hexmask.long 0x5C 0.--31. 1. "MSI_CTRL_INT_6_STATUS,MSI Interrupt#i Status. When an MSI is detected for EP#i one bit in this register is set. The decoding of the data payload of the MSI Memory Write request determines which bit gets set. A status is bit is cleared by writing a 1 to.." line.long 0x60 "MSI_CTRL_INT_7_EN_OFF,Integrated MSI Reception Module Interrupt#i Enable Register." hexmask.long 0x60 0.--31. 1. "MSI_CTRL_INT_7_EN,MSI Interrupt#i Enable. Specifies which interrupts are enabled. When an MSI is received from a disabled interrupt no status bit gets set in MSI controller interrupt status register. Each bit corresponds to a single MSI Interrupt.." line.long 0x64 "MSI_CTRL_INT_7_MASK_OFF,Integrated MSI Reception Module Interrupt#i Mask Register." hexmask.long 0x64 0.--31. 1. "MSI_CTRL_INT_7_MASK,MSI Interrupt#i Mask. Allows enabled interrupts to be masked. When an MSI is received for a masked interrupt the corresponding status bit gets set in the interrupt status register but the msi_ctrl_int output is not set HIGH. Each bit.." line.long 0x68 "MSI_CTRL_INT_7_STATUS_OFF,Integrated MSI Reception Module Interrupt#i Status Register." hexmask.long 0x68 0.--31. 1. "MSI_CTRL_INT_7_STATUS,MSI Interrupt#i Status. When an MSI is detected for EP#i one bit in this register is set. The decoding of the data payload of the MSI Memory Write request determines which bit gets set. A status is bit is cleared by writing a 1 to.." line.long 0x6C "MSI_GPIO_IO_OFF,Integrated MSI Reception Module General Purpose IO Register." hexmask.long 0x6C 0.--31. 1. "MSI_GPIO_REG,MSI GPIO Register. The contents of this register drives the top-level GPIO msi_ctrl_io[31:0] Note: This register field is sticky." line.long 0x70 "CLOCK_GATING_CTRL_OFF,This register enables you to disable dynamic clock gating. By default dynamic clock gating is on. allowing the controller to autonomously enable and disable its clocks. The clock gating is performed in the clock and reset module." hexmask.long 0x70 2.--31. 1. "RSVDP_2,Reserved for future use." newline bitfld.long 0x70 1. "AXI_CLK_GATING_EN,AXI Clock Gating Enable. This register enables the AXI Bridge to autonomously enable and disable the AXI Master clock the AXI Slave clock and the AXI DBI slave clock. The DWC_pcie_clk_rst.v module provides the gated clock.." "Disable,Enable" newline bitfld.long 0x70 0. "RADM_CLK_GATING_EN,RADM Clock Gating Enable. This register if set enables the RADM to autonomously enable and disable its clock. The DWC_pcie_clk_rst.v module provides the gated clock radm_clk_g to the RADM and is enabled when the controllers clock.." "Disable,Enable" line.long 0x74 "GEN3_RELATED_OFF,Gen3 Control Register. There is no Gen3-specific N_FTS field. The N_FTS field in the 'Link Width and Speed Change Control Register' is used for both Gen2 and Gen3 speed modes. There is no Gen3-specific 'Directed Speed Change' field. The.." hexmask.long.byte 0x74 26.--31. 1. "RSVDP_26,Reserved for future use." newline bitfld.long 0x74 23. "GEN3_EQ_INVREQ_EVAL_DIFF_DISABLE,Eq InvalidRequest and RxEqEval Different Time Assertion Disable. Disable the assertion of Eq InvalidRequest and RxEqEval at different time. Note: When CX_GEN4_SPEED/CX_GEN5_SPEED this register is shared for Gen3 and.." "0,1" newline rbitfld.long 0x74 19.--20. "RSVDP_19,Reserved for future use." "0,1,2,3" newline bitfld.long 0x74 18. "GEN3_DC_BALANCE_DISABLE,DC Balance Disable. Disable DC Balance feature. Note: When CX_GEN4_SPEED/CX_GEN5_SPEED this register is shared for Gen3 and Gen4/Gen5 data rate. Note: This register field is sticky." "0,1" newline bitfld.long 0x74 17. "GEN3_DLLP_XMT_DELAY_DISABLE,DLLP Transmission Delay Disable. Disable delay transmission of DLLPs before equalization. Note: When CX_GEN4_SPEED/CX_GEN5_SPEED this register is shared for Gen3 and Gen4/Gen5 data rate. Note: This register field is sticky." "0,1" newline bitfld.long 0x74 16. "GEN3_EQUALIZATION_DISABLE,Equalization Disable. Disable equalization feature. This bit cannot be changed once the LTSSM starts link training. Note: When CX_GEN4_SPEED/CX_GEN5_SPEED this register is shared for Gen3 and Gen4/Gen5 data rate. Note: This.." "0,1" newline rbitfld.long 0x74 14.--15. "RSVDP_14,Reserved for future use." "0,1,2,3" newline bitfld.long 0x74 13. "RXEQ_RGRDLESS_RXTS,When set to '1' the controller as Gen3 EQ master asserts RxEqEval to instruct the PHY to do Rx adaptation and evaluation after a 500ns timeout from a new preset request. - 0: mac_phy_rxeqeval asserts after 1us and 2 TS1 received from.." "mac_phy_rxeqeval asserts after 1us and 2 TS1..,mac_phy_rxeqeval asserts after 500ns regardless.." newline bitfld.long 0x74 12. "RXEQ_PH01_EN,Rx Equalization Phase 0/Phase 1 Hold Enable. When this bit is set the upstream port holds phase 0 (the downstream port holds phase 1) for 10ms. Holding phase 0 or phase 1 can be used to allow sufficient time for Rx Equalization to be.." "Tx equalization only in phase 2/3,No Tx equalization" newline bitfld.long 0x74 11. "EQ_REDO,Equalization Redo Disable. Disable autonomous mechanism for requesting to redo the equalization process. The received presets or coefficients mismatch in Recovery.RcvrLock after Recovery EQ phases causes the EQ redo requests. If the EQ redo is.." "0,1" newline bitfld.long 0x74 10. "EQ_EIEOS_CNT,Equalization EIEOS Count Reset Disable. Disable requesting reset of EIEOS count during equalization. Note: When CX_GEN4_SPEED/CX_GEN5_SPEED this register is shared for Gen3 and Gen4/Gen5 data rate. Note: This register field is sticky." "0,1" newline bitfld.long 0x74 9. "EQ_PHASE_2_3,Equalization Phase 2 and Phase 3 Disable. This applies to downstream ports only. Note: When CX_GEN4_SPEED/CX_GEN5_SPEED this register is shadow register for Gen3 and Gen4/Gen5 data rate. If RATE_SHADOW_SEL==00b this register is for Gen3.." "0,1" newline bitfld.long 0x74 8. "DISABLE_SCRAMBLER_GEN_3,Disable Scrambler for Gen3 and Gen4 Data Rate. The Gen3 and Gen4 scrambler/descrambler within the controller needs to be disabled when the scrambling function is implemented outside of the controller (for example within the PHY)." "0,1" newline hexmask.long.byte 0x74 1.--7. 1. "RSVDP_1,Reserved for future use." newline bitfld.long 0x74 0. "GEN3_ZRXDC_NONCOMPL,Gen3 Receiver Impedance ZRX-DC Not Compliant. Receivers that operate at 8.0 GT/s with an impedance other than the range defined by the ZRX-DC parameter for 2.5 GT/s (40-60 Ohms) must meet additional behavior requirements in the.." "The receiver complies with the ZRX-DC parameter..,The receiver does not comply with the ZRX-DC.." group.long (0x1A8+0x700)++0x7 line.long 0x0 "GEN3_EQ_CONTROL_OFF,Gen3 EQ Control Register. This register controls equalization for Phase2 in an upstream port (USP). or Phase3 in a downstream port (DSP). M-PCIe doesn't have Conventional PCIe Gen3 feature. The registers of this section do not exist." hexmask.long.byte 0x0 27.--31. 1. "RSVDP_27,Reserved for future use." newline bitfld.long 0x0 26. "GEN3_REQ_SEND_CONSEC_EIEOS_FOR_PSET_MAP,Request controller to send back-to-back EIEOS in Recovery.RcvrLock state until presets to coefficients mapping is complete. - 0: Do not request - 1: request Note: Gen3 and Gen4 share the same register bit and have.." "Do not request,request" newline bitfld.long 0x0 25. "GEN3_EQ_PSET_REQ_AS_COEF,GEN3_EQ_PSET_REQ_AS_COEF is an internally reserved field. Do not use. Note: This register field is sticky." "0,1" newline bitfld.long 0x0 24. "GEN3_EQ_FOM_INC_INITIAL_EVAL,Include Initial FOM. Include or not the FOM feedback from the initial preset evaluation performed in the EQ Master when finding the highest FOM among all preset evaluations. - 0: Do not include - 1: Include Note: When.." "Do not include,Include" newline hexmask.long.word 0x0 8.--23. 1. "GEN3_EQ_PSET_REQ_VEC,Preset Request Vector. Requesting of Presets during the initial part of the EQ Master Phase. Encoding scheme is as follows: Bit [15:0] =0x0: No preset is requested and evaluated in EQ Master Phase. Bit [i] =1: 'Preset=i' is requested.." newline rbitfld.long 0x0 7. "RSVDP_7,Reserved for future use." "0,1" newline bitfld.long 0x0 6. "GEN3_LOWER_RATE_EQ_REDO_ENABLE,Support EQ redo and lower rate change: - 0: not support - 1: support Note: Gen3 and Gen4 share the same register bit and have the same feature. Note: This register field is sticky." "not support,support" newline bitfld.long 0x0 5. "GEN3_EQ_EVAL_2MS_DISABLE,Phase2_3 2 ms Timeout Disable. Determine behavior in Phase2 for USP (Phase3 if DSP) when the PHY does not respond within 2ms to the assertion of RxEqEval: - 0: abort the current evaluation stop any attempt to modify the remote.." "abort the current evaluation,ignore the 2ms timeout and continue as normal" newline bitfld.long 0x0 4. "GEN3_EQ_PHASE23_EXIT_MODE,Behavior After 24 ms Timeout (when optimal settings are not found). For a USP: Determine next LTSSM state from Phase2 after 24ms Timeout - 0: Recovery.Speed - 1: Recovery.Equalization.Phase3 When optimal settings are not found.." "Equalization Phase 3 Successful status bit is..,Recovery" newline hexmask.long.byte 0x0 0.--3. 1. "GEN3_EQ_FB_MODE,Feedback Mode. - 0000b: Direction Change - 0001b: Figure Of Merit - 0010b: Reserved - .....: Reserved - 1111b: Reserved Note: When CX_GEN4_SPEED/CX_GEN5_SPEED this register is a shadow register for Gen3 and Gen4/Gen5 data rate. If.." line.long 0x4 "GEN3_EQ_FB_MODE_DIR_CHANGE_OFF,Gen3 EQ Direction Change Feedback Mode Control Register. Equalization controls to be used in Phase2 (USP) or Phase 3 (DSP). when you set the Feedback Mode in 'Gen3 EQ Control Register' to 'Direction Change.' These fields.." hexmask.long.word 0x4 18.--31. 1. "RSVDP_18,Reserved for future use." newline hexmask.long.byte 0x4 14.--17. 1. "GEN3_EQ_FMDC_MAX_POST_CUSROR_DELTA,Convergence Window Aperture for C+1. Post-cursor coefficients maximum delta within the convergence window depth. Allowed range: 0 1 2 ..15. Note: When CX_GEN4_SPEED/CX_GEN5_SPEED this register is shadow register for.." newline hexmask.long.byte 0x4 10.--13. 1. "GEN3_EQ_FMDC_MAX_PRE_CUSROR_DELTA,Convergence Window Aperture for C-1. Pre-cursor coefficients maximum delta within the convergence window depth. Allowed range: 0 1 2 ..15. Note: When CX_GEN4_SPEED/CX_GEN5_SPEED this register is shadow register for Gen3.." newline hexmask.long.byte 0x4 5.--9. 1. "GEN3_EQ_FMDC_N_EVALS,Convergence Window Depth. Number of consecutive evaluations considered in Phase 2/3 when determining if optimal coefficients have been found. Allowed range: 0 1 2 ..16 up to a maximum of CX_GEN3_EQ_COEFQ_DEPTH. When set to 0 EQ.." newline hexmask.long.byte 0x4 0.--4. 1. "GEN3_EQ_FMDC_T_MIN_PHASE23,Minimum Time (in ms) To Remain in EQ Master Phase. The LTSSM stays in EQ Master phase for at least this amount of time before starting to check for convergence of the coefficients. Allowed values 0 1 ... 24. Note: When.." group.long (0x1B4+0x700)++0x27 line.long 0x0 "ORDER_RULE_CTRL_OFF,Order Rule Control Register." hexmask.long.word 0x0 16.--31. 1. "RSVDP_16,Reserved for future use." newline hexmask.long.byte 0x0 8.--15. 1. "CPL_PASS_P,Completion Passing Posted Ordering Rule Control. Determines if CPL can pass halted P queue. - 0: CPL can not pass P (recommended) - 1: CPL can pass P" newline hexmask.long.byte 0x0 0.--7. 1. "NP_PASS_P,Non-Posted Passing Posted Ordering Rule Control. Determines if NP can pass halted P queue. - 0 : NP can not pass P (recommended). - 1 : NP can pass P" line.long 0x4 "PIPE_LOOPBACK_CONTROL_OFF,PIPE Loopback Control Register." bitfld.long 0x4 31. "PIPE_LOOPBACK,PIPE Loopback Enable. Indicates RMMI Loopback if M-PCIe. Note: This register field is sticky." "0,1" newline hexmask.long.byte 0x4 27.--30. 1. "RSVDP_27,Reserved for future use." newline bitfld.long 0x4 24.--26. "RXSTATUS_VALUE,RXSTATUS_VALUE is an internally reserved field. Do not use." "0,1,2,3,4,5,6,7" newline rbitfld.long 0x4 22.--23. "RSVDP_22,Reserved for future use." "0,1,2,3" newline hexmask.long.byte 0x4 16.--21. 1. "RXSTATUS_LANE,RXSTATUS_LANE is an internally reserved field. Do not use. Note: This register field is sticky." newline hexmask.long.word 0x4 0.--15. 1. "LPBK_RXVALID,LPBK_RXVALID is an internally reserved field. Do not use. Note: This register field is sticky." line.long 0x8 "MISC_CONTROL_1_OFF,DBI Read-Only Write Enable Register." hexmask.long.word 0x8 22.--31. 1. "RSVDP_22,Reserved for future use." newline bitfld.long 0x8 21. "P2P_ERR_RPT_CTRL,Determines whether to track completion of transmitted Non-Posted TLPs in P2P mode. - 0: Do not track completion - 1: Track completion Note: This register field is sticky." "Do not track completion,Track completion" newline bitfld.long 0x8 20. "P2P_TRACK_CPL_TO_REG,Determines whether to enable Peer to Peer (P2P) error reporting. - 0: Disable P2P error reporting - 1: Enable P2P error reporting Note: This register field is sticky." "Disable P2P error reporting,Enable P2P error reporting" newline bitfld.long 0x8 18.--19. "TARGET_ABOVE_CONFIG_LIMIT_REG,Configuration requests with an address greater than CONFIG_LIMIT_REG are directed to either ELBI or TRGT1 interface based on the setting of this field. This field can have the following values: - 1: ELBI - 2: TRGT1 Note:.." "?,ELBI,TRGT1,?" newline hexmask.long.word 0x8 8.--17. 1. "CONFIG_LIMIT_REG,Configuration requests are directed either to CDM or ELBI/RTRGT1 based on the value of this field. - Configuration requests with an address less CONFIG_LIMIT_REG are directed to the CDM - Configuration requests with an address greater.." newline bitfld.long 0x8 7. "CFG_TLP_BYPASS_EN_REG,Setting of this field defines which field TARGET_ABOVE_CONFIG_LIMIT_REG or CONFIG_LIMIT_REG decides the destination of Configuration requests. This field can have the following values: - 0: Configuration TLPs are routed according to.." "Configuration TLPs are routed according to the..,Configuration TLPs are routed according to the.." newline bitfld.long 0x8 6. "CPLQ_MNG_EN,This field enables the Completion Queue Management feature. Note: This register field is sticky." "0,1" newline bitfld.long 0x8 5. "ARI_DEVICE_NUMBER,When ARI is enabled this field enables use of the device ID. Note: This register field is sticky." "0,1" newline bitfld.long 0x8 4. "DISABLE_AUTO_LTR_CLR_MSG,Disable the autonomous generation of LTR clear message in upstream port. This field can have the following values: - 0: Allow the autonomous generation of LTR clear message. - 1: Disable the autonomous generation of LTR clear.." "Allow the autonomous generation of LTR clear..,Disable the autonomous generation of LTR clear.." newline bitfld.long 0x8 3. "SIMPLIFIED_REPLAY_TIMER,Enables Simplified Replay Timer (Gen4). For more details see 'Transmit Replay' in 'Transmit TLP Processing' section in the 'Controller Operations' chapter of the Databook. Simplified Replay Timer can have the following Values: -.." "0,1" newline bitfld.long 0x8 2. "UR_CA_MASK_4_TRGT1,When this field is set to '1' the controller suppresses error logging error message generation and CPL generation for non-posted requests TLPs (with UR filtering status) forwarded to your application (that is when DEFAULT_TARGET.." "0,1" newline bitfld.long 0x8 1. "DEFAULT_TARGET,Default target for an IO or MEM request with UR/CA/CRS received. Based on the value of this field the controller either drops or forwards these requests to your application. - 0: The controller drops all incoming I/O or MEM requests (after.." "The controller drops all incoming I/O or MEM..,The controller forwards all incoming I/O or MEM.." newline bitfld.long 0x8 0. "DBI_RO_WR_EN,Write to RO Registers Using DBI. Your application can write to some RO and HwInit register fields through the DBI when you set this field to '1'. For more details see 'Writing to Read-Only Registers' in 'Register Module LBC and DBI'.." "0,1" line.long 0xC "MULTI_LANE_CONTROL_OFF,UpConfigure Multi-lane Control Register. Used when upsizing or downsizing the link width through Configuration state without bringing the link down. For more details. see the 'Link Establishment' section in the 'Controller.." hexmask.long.tbyte 0xC 8.--31. 1. "RSVDP_8,Reserved for future use." newline bitfld.long 0xC 7. "UPCONFIGURE_SUPPORT,Upconfigure Support. The controller sends this value as the Link Upconfigure Capability in TS2 Ordered Sets in Configuration.Complete state. This field is reserved (fixed to '0') for M-PCIe. Note: This register field is sticky." "0,1" newline bitfld.long 0xC 6. "DIRECT_LINK_WIDTH_CHANGE,Directed Link Width Change. The controller always moves to Configuration state through Recovery state when this bit is set to '1'. - If the upconfigure_capable variable is '1' and the PCIE_CAP_HW_AUTO_WIDTH_DISABLE bit in.." "0,1" newline hexmask.long.byte 0xC 0.--5. 1. "TARGET_LINK_WIDTH,Target Link Width. Values correspond to: - 6'b000000: Controller does not start upconfigure or autonomous width downsizing in the Configuration state. - 6'b000001: x1 - 6'b000010: x2 - 6'b000100: x4 - 6'b001000: x8 - 6'b010000: x16 -.." line.long 0x10 "PHY_INTEROP_CTRL_OFF,PHY Interoperability Control Register." hexmask.long.tbyte 0x10 12.--31. 1. "RSVDP_12,Reserved for future use." newline bitfld.long 0x10 10. "L1_CLK_SEL,L1 Clock control bit. This field is reserved for internal use. You should not write to this field and change the default unless specifically instructed by Synopsys support. - 1: Controller does not request aux_clk switch and core_clk gating in.." "Controller requests aux_clk switch and core_clk..,Controller does not request aux_clk switch and.." newline rbitfld.long 0x10 9. "L1_NOWAIT_P1,L1 entry control bit. This field is reserved for internal use. You should not write to this field and change the default unless specifically instructed by Synopsys support. - 1: Controller does not wait for PHY to acknowledge transition to.." "Controller waits for the PHY to acknowledge..,Controller does not wait for PHY to acknowledge.." newline bitfld.long 0x10 8. "L1SUB_EXIT_MODE,L1 Exit Control Using phy_mac_pclkack_n. This field is reserved for internal use. You should not write to this field and change the default unless specifically instructed by Synopsys support. - 1: Controller exits L1 without waiting for.." "Controller waits for the PHY to assert..,Controller exits L1 without waiting for the PHY.." newline rbitfld.long 0x10 7. "RSVDP_7,Reserved for future use." "0,1" newline hexmask.long.byte 0x10 0.--6. 1. "RXSTANDBY_CONTROL,Rxstandby Control. Bits 0..5 determine if the controller asserts the RxStandby signal (mac_phy_rxstandby) in the indicated condition. Bit 6 enables the controller to perform the RxStandby/RxStandbyStatus handshake. This field is.." line.long 0x14 "TRGT_CPL_LUT_DELETE_ENTRY_OFF,TRGT_CPL_LUT Delete Entry Control register. Using this register you can delete one entry in the target completion LUT. You should only use this register when you know that your application will never send the completion.." bitfld.long 0x14 31. "DELETE_EN,This is a one-shot bit. A '1' write to this bit triggers the deletion of the target completion LUT entry that is specified in the LOOK_UP_ID field. This is a self-clearing register field. Reading from this register field always returns a '0'." "0,1" newline hexmask.long 0x14 0.--30. 1. "LOOK_UP_ID,This number selects one entry to delete of the TRGT_CPL_LUT." line.long 0x18 "LINK_FLUSH_CONTROL_OFF,Link Reset Request Flush Control Register." hexmask.long.byte 0x18 24.--31. 1. "RSVD_I_8,This is an internally reserved field. Do not use. Note: This register field is sticky." newline hexmask.long.tbyte 0x18 1.--23. 1. "RSVDP_1,Reserved for future use." newline bitfld.long 0x18 0. "AUTO_FLUSH_EN,Enables automatic flushing of pending requests before sending the reset request to the application logic to reset the PCIe controller and the AXI Bridge. The flushing process is initiated if any of the following events occur: - Hot reset.." "0,1" line.long 0x1C "AMBA_ERROR_RESPONSE_DEFAULT_OFF,AXI Bridge Slave Error Response Register." hexmask.long.word 0x1C 16.--31. 1. "RSVDP_16,Reserved for future use." newline hexmask.long.byte 0x1C 10.--15. 1. "AMBA_ERROR_RESPONSE_MAP,AXI Slave Response Error Map. Allows you to selectively map the errors received from the PCIe completion (for non-posted requests) to the AXI slave responses slv_rresp or slv_bresp. The recommended setting is SLVERR. CRS is.." newline hexmask.long.byte 0x1C 5.--9. 1. "RSVDP_5,Reserved for future use." newline bitfld.long 0x1C 3.--4. "AMBA_ERROR_RESPONSE_CRS,CRS Slave Error Response Mapping. Determines the AXI slave response for CRS completions. For more details see 'Error Handling' in the AXI chapter of the Databook. AHB: - always returns OKAY AXI: - 00: OKAY - 01: OKAY with all.." "OKAY,OKAY with all FFFF_FFFF data for all CRS..,?,?" newline bitfld.long 0x1C 2. "AMBA_ERROR_RESPONSE_VENDORID,Vendor ID Non-existent Slave Error Response Mapping. Determines the AXI slave response for errors on reads to non-existent Vendor ID register. For more details see 'Error Handling' in the AXI chapter of the Databook. AHB: -.." "OKAY,SLVERR/DECERR" newline rbitfld.long 0x1C 1. "RSVDP_1,Reserved for future use." "0,1" newline bitfld.long 0x1C 0. "AMBA_ERROR_RESPONSE_GLOBAL,Global Slave Error Response Mapping. Determines the AXI slave response for all error scenarios on non-posted requests. For more details see 'Error Handling' in the AXI chapter of the Databook. AHB: - 0: OKAY (with FFFF data for.." "OKAY,SLVERR/DECERR" line.long 0x20 "AMBA_LINK_TIMEOUT_OFF,Link Down AXI Bridge Slave Timeout Register. If your application AXI master issues outbound requests to the AXI bridge slave interface before the PCIe link is operational. the controller starts a 'flush' timer. The timeout value of.." hexmask.long.tbyte 0x20 9.--31. 1. "RSVDP_9,Reserved for future use." newline bitfld.long 0x20 8. "LINK_TIMEOUT_ENABLE_DEFAULT,Disable Flush. You can disable the flush feature by setting this field to '1'. Note: This register field is sticky." "0,1" newline hexmask.long.byte 0x20 0.--7. 1. "LINK_TIMEOUT_PERIOD_DEFAULT,Timeout Value (ms). The timer will timeout and then flush the bridge TX request queues after this amount of time. The timer counts when there are pending outbound AXI slave interface requests and the PCIe TX link is not.." line.long 0x24 "AMBA_ORDERING_CTRL_OFF,AMBA Ordering Control." hexmask.long.tbyte 0x24 8.--31. 1. "RSVDP_8,Reserved for future use." newline bitfld.long 0x24 7. "AX_MSTR_ZEROLREAD_FW,AXI Master Zero Length Read Forward to the application. The DW PCIe controller AXI bridge is able to terminate in order with the Posted transactions the zero length read implementing the PCIe express flush semantics of the Posted.." "The zero length Read is terminated at the DW..,The zero length Read is forward to the application" newline rbitfld.long 0x24 5.--6. "RSVDP_5,Reserved for future use." "0,1,2,3" newline bitfld.long 0x24 3.--4. "AX_MSTR_ORDR_P_EVENT_SEL,AXI Master Posted Ordering Event Selector. This field selects how the master interface determines when a P write is completed when enforcing the PCIe ordering rule 'NP must not pass P' at the AXI Master Interface. The AXI.." "B'last event: wait for the all of the write..,AW'last event: wait until the complete Posted..,This setting will not affect:,?" newline rbitfld.long 0x24 2. "RSVDP_2,Reserved for future use." "0,1" newline bitfld.long 0x24 1. "AX_SNP_EN,AXI Serialize Non-Posted Requests Enable. This field enables the AXI Bridge to serialize same ID Non-Posted Read/Write Requests on the wire. Serialization implies one outstanding same ID NP Read or Write on the wire and used to avoid AXI RAR.." "0,1" newline rbitfld.long 0x24 0. "RSVDP_0,Reserved for future use." "0,1" group.long (0x1E0+0x700)++0xB line.long 0x0 "COHERENCY_CONTROL_1_OFF,ACE Cache Coherency Control Register 1" hexmask.long 0x0 2.--31. 1. "CFG_MEMTYPE_BOUNDARY_LOW_ADDR,Boundary Lower Address For Memory Type. Bits [31:0] of dword-aligned address of the boundary for Memory type. The two lower address LSBs are '00'. Addresses up to but not including this value are in the lower address space.." newline rbitfld.long 0x0 1. "RSVDP_1,Reserved for future use." "0,1" newline bitfld.long 0x0 0. "CFG_MEMTYPE_VALUE,Sets the memory type for the lower and upper parts of the address space: - 0: lower = Peripheral; upper = Memory - 1: lower = Memory type; upper = Peripheral Note: This register field is sticky." "lower = Peripheral; upper = Memory,lower = Memory type; upper = Peripheral" line.long 0x4 "COHERENCY_CONTROL_2_OFF,ACE Cache Coherency Control Register 2" hexmask.long 0x4 0.--31. 1. "CFG_MEMTYPE_BOUNDARY_HIGH_ADDR,Boundary Upper Address For Memory Type. Bits [63:32] of the 64-bit dword-aligned address of the boundary for Memory type. Note: This register field is sticky." line.long 0x8 "COHERENCY_CONTROL_3_OFF,ACE Cache Coherency Control Register 3" hexmask.long.byte 0x8 27.--30. 1. "CFG_MSTR_AWCACHE_VALUE,Master Write CACHE Signal Value. Value of the individual bits in mstr_awcache when CFG_MSTR_AWCACHE_MODE is '1'. Note: not applicable to message requests; for message requests the value of mstr_awcache is always '0000' Note: This.." newline hexmask.long.byte 0x8 19.--22. 1. "CFG_MSTR_ARCACHE_VALUE,Master Read CACHE Signal Value. Value of the individual bits in mstr_arcache when CFG_MSTR_ARCACHE_MODE is '1'. Note: This register field is sticky." newline hexmask.long.byte 0x8 11.--14. 1. "CFG_MSTR_AWCACHE_MODE,Master Write CACHE Signal Behavior. Defines how the individual bits in mstr_awcache are controlled: - 0: set automatically by the AXI master - 1: set by the value of the corresponding bit of the CFG_MSTR_AWCACHE_VALUE field Note:.." newline hexmask.long.byte 0x8 3.--6. 1. "CFG_MSTR_ARCACHE_MODE,Master Read CACHE Signal Behavior. Defines how the individual bits in mstr_arcache are controlled: - 0: set automatically by the AXI master - 1: set by the value of the corresponding bit of the CFG_MSTR_ARCACHE_VALUE field Note:.." group.long (0x1F0+0x700)++0x7 line.long 0x0 "AXI_MSTR_MSG_ADDR_LOW_OFF,Lower 20 bits of the programmable AXI address where Messages coming from wire are mapped to. Bits [11:0] of the register are tied to zero for the address to be 4k-aligned. In previous releases. the third and fourth DWORDs of a.." hexmask.long.tbyte 0x0 12.--31. 1. "CFG_AXIMSTR_MSG_ADDR_LOW,Lower 20 bits of the programmable AXI address for Messages. Note: This register field is sticky." newline hexmask.long.word 0x0 0.--11. 1. "CFG_AXIMSTR_MSG_ADDR_LOW_RESERVED,Reserved for future use. Note: This register field is sticky." line.long 0x4 "AXI_MSTR_MSG_ADDR_HIGH_OFF,Upper 32 bits of the programmable AXI address where Messages coming from wire are mapped to." hexmask.long 0x4 0.--31. 1. "CFG_AXIMSTR_MSG_ADDR_HIGH,Upper 32 bits of the programmable AXI address for Messages. Note: This register field is sticky." rgroup.long (0x1F8+0x700)++0x7 line.long 0x0 "PCIE_VERSION_NUMBER_OFF,PCIe Controller IIP Release Version Number. The version number is given in hex format. You should convert each pair of hex characters to ASCII to interpret. Using 4.70a (GA) as an example: - VERSION_NUMBER = 0x3437302a which.." hexmask.long 0x0 0.--31. 1. "VERSION_NUMBER,Version Number." line.long 0x4 "PCIE_VERSION_TYPE_OFF,PCIe Controller IIP Release Version Type. The type is given in hex format. You should convert each pair of hex characters to ASCII to interpret. Using 4.70a (GA) as an example: - VERSION_NUMBER = 0x3437302a which translates to 470*.." hexmask.long 0x4 0.--31. 1. "VERSION_TYPE,Version Type." group.long (0x430+0x700)++0x3 line.long 0x0 "PL_LTR_LATENCY_OFF,LTR Latency Register. The function of this register field (and all other fields in this register) differs between an upstream port and a downstream port. For an upstream port. the register fields capture the corresponding fields in the.." bitfld.long 0x0 31. "NO_SNOOP_LATENCY_REQUIRE,No Snoop Latency Requirement. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" "0,1" newline rbitfld.long 0x0 29.--30. "RSVDP_29,Reserved for future use." "0,1,2,3" newline bitfld.long 0x0 26.--28. "NO_SNOOP_LATENCY_SCALE,No Snoop Latency Scale. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" "0,1,2,3,4,5,6,7" newline hexmask.long.word 0x0 16.--25. 1. "NO_SNOOP_LATENCY_VALUE,No Snoop Latency Value. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" newline bitfld.long 0x0 15. "SNOOP_LATENCY_REQUIRE,Snoop Latency Requirement. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" "0,1" newline rbitfld.long 0x0 13.--14. "RSVDP_13,Reserved for future use." "0,1,2,3" newline bitfld.long 0x0 10.--12. "SNOOP_LATENCY_SCALE,Snoop Latency Scale. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" "0,1,2,3,4,5,6,7" newline hexmask.long.word 0x0 0.--9. 1. "SNOOP_LATENCY_VALUE,Snoop Latency Value. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" group.long (0x440+0x700)++0xB line.long 0x0 "AUX_CLK_FREQ_OFF,Auxiliary Clock Frequency Control Register." hexmask.long.tbyte 0x0 10.--31. 1. "RSVDP_10,Reserved for future use." newline hexmask.long.word 0x0 0.--9. 1. "AUX_CLK_FREQ,The aux_clk frequency in MHz. This value is used to provide a 1 us reference for counting time during low-power states with aux_clk when the PHY has removed the pipe_clk. Frequencies lower than 1 MHz are possible but with a loss of accuracy.." line.long 0x4 "L1_SUBSTATES_OFF,L1 Substates Timing Register." hexmask.long.tbyte 0x4 9.--31. 1. "RSVDP_9,Reserved for future use." newline bitfld.long 0x4 8. "L1SUB_LOW_POWER_CLOCK_SWITCH_MODE,If this bit is set to 1'b1 the reference clock will be running regardless of the CLKREQ# setting. If this bit is set to 1'b0 the reference clock may be gated off when CLKREQ# is de-asserted. If the bit is set to 1'b1 the.." "0,1" newline bitfld.long 0x4 6.--7. "L1SUB_T_PCLKACK,Max delay (in 1us units) between a MAC request to remove the clock on mac_phy_pclkreq_n and a PHY response on phy_mac_pclkack_n. If the PHY does not respond within this time the request is aborted.The actual timeout value will be.." "0,1,2,3" newline hexmask.long.byte 0x4 2.--5. 1. "L1SUB_T_L1_2,Duration (in 1us units) of L1.2. The actual timeout value will be L1SUB_T_L1_2 + 1. Range is 0.15. Note: This register field is sticky." newline bitfld.long 0x4 0.--1. "L1SUB_T_POWER_OFF,Duration (in 1us units) of L1.2.Entry. The actual timeout value will be L1SUB_T_POWER_OFF + 1. Range is 0.3. Note: This register field is sticky." "0,1,2,3" line.long 0x8 "POWERDOWN_CTRL_STATUS_OFF,Powerdown Control and Status Register." hexmask.long.tbyte 0x8 12.--31. 1. "RSVDP_12,Reserved for future use." newline hexmask.long.byte 0x8 8.--11. 1. "POWERDOWN_PHY_POWERDOWN,This field represents the Powerdown value that has been acknowledged by the PHY. It is updated with the value of Powerdown driven by the controller when the PHY has returned the Phystatus acknowledgment for the Powerdown.." newline hexmask.long.byte 0x8 4.--7. 1. "POWERDOWN_MAC_POWERDOWN,This field represents the Powerdown value driven by the controller to the PHY." newline rbitfld.long 0x8 1.--3. "RSVDP_1,Reserved for future use." "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 0. "POWERDOWN_FORCE,This field is a one shot field. Writing a value of 1 to this field causes the controller to complete the P2 Powerdown handshake regardless of whether the PHY has returned Phystatus. This field could be used for debug purposes in event.." "0,1" group.long (0x470+0x700)++0x7 line.long 0x0 "PHY_VIEWPORT_CTLSTS_OFF,PHY Register Viewport Control and Status Register." rbitfld.long 0x0 31. "PHY_VIEWPORT_PENDING,PHY viewport pending. Indicates the access is pending. - 1 : Pending - 0 : Idle This bit is set to 1 when the read/write access has been initiated. This bit is cleared when the access is completed. If phy_reg_clk_g is never activated.." "Idle,Pending" newline rbitfld.long 0x0 30. "PHY_VIEWPORT_STATUS,PHY viewport status. Indicates the status of the latest access. - 1 : Timeout - 0 : No errors If the timeout is detected this bit is set to 1 and PHY_VIEWPORT_PENDING is cleared. This bit is cleared when the read/write access is.." "No errors,Timeout" newline hexmask.long.byte 0x0 23.--29. 1. "RSVDP_23,Reserved for future use." newline bitfld.long 0x0 22. "PHY_VIEWPORT_TIMEOUT_DISABLE,PHY viewport timeout disable. Disables the PHY register access timeout structure. When the timeout is disabled you must ensure that the PHY register accesses are always acknowledged by cr_para_ack. Otherwise.." "0,1" newline bitfld.long 0x0 21. "PHY_VIEWPORT_BCWR,Broadcast write access to all xN sub-blocks. If you need to broadcast the write accesses into all lanes both PHY_VIEWPORT_ADDR[15] and this bit should be 1. Note: This register field is sticky." "0,1" newline bitfld.long 0x0 20. "PHY_VIEWPORT_READ,PHY viewport read. If set a read access is initiated. The value is always 0 when this bit is read. Note: This register field is sticky." "0,1" newline hexmask.long.byte 0x0 16.--19. 1. "PHY_VIEWPORT_NUM,PHY viewport xN sub-block number. Selects one of xN sub-blocks. This register is not used when the write access is initiated with PHY_VIEWPORT_BCWR==1. Note: This register field is sticky." newline hexmask.long.word 0x0 0.--15. 1. "PHY_VIEWPORT_ADDR,PHY viewport address. Indicates the PHY's register address. Please refer to the PHY databook for the address map definition. Note: This register field is sticky." line.long 0x4 "PHY_VIEWPORT_DATA_OFF,PHY Register Viewport Data Register." hexmask.long.word 0x4 16.--31. 1. "RSVDP_16,Reserved for future use." newline hexmask.long.word 0x4 0.--15. 1. "PHY_VIEWPORT_DATA,PHY viewport data. A write access to this register initiates the PHY register write access. By a read access to this register this field returns the latest read data from the PHY register. Note: This register field is sticky." group.long (0x490+0x700)++0x3 line.long 0x0 "PIPE_RELATED_OFF,PIPE Related Register. This register controls the pipe's capabitity. control. and status parameters." hexmask.long.tbyte 0x0 9.--31. 1. "RSVDP_9,Reserved for future use." newline bitfld.long 0x0 8. "PIPE_GARBAGE_DATA_MODE,PIPE Garbage Data Mode. - 0: PIPE Spec compliant mode: The MAC discards any symbols received after the electrical idle ordered-set until RxValid is deasserted. - 1: Special PHY Support mode: The MAC discards any symbols received.." "PIPE Spec compliant mode: The MAC discards any..,Special PHY Support mode: The MAC discards any.." tree.end tree.end tree "PCIE2_NCR" base ad:0xF11E0000 group.long 0x0++0x7 line.long 0x0 "INTR_0,INTR_0" bitfld.long 0x0 31. "INTR_PM_XTLH_BLOCK_TLP,Indicates that your application must stop generating new outgoing request TLPs due to the current power management state. Your application can continue to generate completion TLPs." "0,1" newline bitfld.long 0x0 30. "INTR_LINK_REQ_RST_NOT,Reset request because the link has gone down or the controller received a hot-reset request. A low level indicates that the controller is requesting external logic to reset the controller because the PHY link is down. When the AXI.." "0,1" newline bitfld.long 0x0 29. "INTR_SMLH_REQ_RST_NOT,Early version of the link_req_rst_not signal." "0,1" newline bitfld.long 0x0 28. "INTR_SMLH_LINK_UP,PHY Link up/down indicator: 1: Link is up 0: Link is down" "Link is down,Link is up" newline bitfld.long 0x0 27. "INTR_RDLH_LINK_UP,Data link layer up/down indicator: This status from the flow control initialization state machine indicates that flow control has been initiated and the Data link layer is ready to transmit and receive packets. For multi-VC designs.." "Link is down,Link is up" newline bitfld.long 0x0 26. "INTR_VEN_MSI_GRANT,One-cycle pulse that indicates that the controller has accepted the request to send an MSI. After asserting ven_msi_grant for one cycle the controller does not wait for ven_msi_req to be de-asserted then reasserted to generate another.." "0,1" newline bitfld.long 0x0 25. "INTR_VEN_MSG_GRANT,One-cycle pulse that indicates that the controller has accepted the request to send the vendor-defined Message." "0,1" newline bitfld.long 0x0 23.--24. "INTR_CFG_UP_DRS_TO_FRS,DRS to FRS Pulse. The DSP controller asserts the cfg_up_drs_to_frs output and sends an FRS message with the reason code set to 'DRS Message Received' when: It receives a DRS message and PCIE_CAP_DRS_SIGNALING_CONTROL in.." "0,1,2,3" newline bitfld.long 0x0 21.--22. "INTR_CFG_DRS_MSI,DRS Message Received Interrupt Pulse. The DSP controller asserts the cfg_drs_msi output when all of the following are true: It receives a DRS message PCIE_CAP_DRS_SIGNALING_CONTROL in LINK_CONTROL_LINK_STATUS_REG is 2'b01 MSI or MSI-X is.." "0,1,2,3" newline bitfld.long 0x0 19.--20. "INTR_FRSQ_MSI,FRSQ Interrupt Pulse. The RC asserts this output when it receives an FRQ message or when the FRS queue overflows." "0,1,2,3" newline bitfld.long 0x0 17.--18. "INTR_CFG_PME_MSI,The controller asserts cfg_pme_msi (as a one-cycle pulse) when all of the following conditions are true: MSI or MSI-X is enabled. The PME Interrupt Enable bit in the Root Control register is set to 1. The PME Status bit in the Root.." "0,1,2,3" newline bitfld.long 0x0 15.--16. "INTR_HP_MSI,INTR_HP_MSI" "0,1,2,3" newline bitfld.long 0x0 14. "INTR_CFG_LINK_AUTO_BW_MSI,The controller sets this pin when following conditions are true: MSI or MSI-X is enabled. The Link Autonomous Bandwidth Status register (Link Status register bit 15) is updated. The Link Autonomous Bandwidth Interrupt Enable.." "0,1" newline bitfld.long 0x0 13. "INTR_CFG_BW_MGT_MSI,The controller sets this pin when following conditions are true: MSI or MSI-X is enabled. The Link Bandwidth Management Status register (Link Control Status register bit 14) is updated The Link Bandwidth Management Interrupt Enable.." "0,1" newline bitfld.long 0x0 11.--12. "INTR_HP_PME,The controller asserts hp_pme when all of the following conditions are true: The PME Enable bit in the Power Management Control and Status" "0,1,2,3" newline bitfld.long 0x0 10. "INTR_PTM_CLOCK_UPDATED,Indicates that the controller has updated the Local Clock." "0,1" newline bitfld.long 0x0 9. "INTR_PTM_REQ_DUP_RX,PTM Requester Duplicate Received. Single-cycle pulse indicating PTM Requester received a duplicate TLP while PTM Requester is in the process of updating PTM local clock or Following calculation of the update when the PTM context is.." "0,1" newline bitfld.long 0x0 8. "INTR_PTM_REQ_REPLAY_TX,PTM Requester Replay Sent. Single-cycle pulse indicating PTM Requester detected a TLP replay being sent when ResponseD messages are in use while PTM Requester is in the process of updating PTM local clock or Following calculation.." "0,1" newline bitfld.long 0x0 7. "INTR_RADM_MSG_LTR,One-clock-cycle pulse that indicates that the controller received an LTR message. The controller makes the message header available the radm_msg_payload output. It is also available the app_ltr_latency output. When RX_TLP > 1 and when.." "0,1" newline bitfld.long 0x0 6. "INTR_RADM_MSG_UNLOCK,One-cycle pulse that indicates that the controller received an Unlock message. When RX_TLP > 1 and when two messages of the same type are received in the same clock cycle (back-to-back) then no separate indication is given for the.." "0,1" newline bitfld.long 0x0 5. "INTR_RADM_PM_PME,One-clock-cycle pulse that indicates that the controller received a PM_PME message." "0,1" newline bitfld.long 0x0 4. "INTR_RADM_PM_TO_ACK,One-clock-cycle pulse that indicates that the controller received a PME_TO_Ack message. Upstream port: Reserved." "0,1" newline bitfld.long 0x0 3. "INTR_RADM_PM_TURNOFF,One-clock-cycle pulse that indicates that the controller received a PME Turnoff message. When RX_TLP > 1 and when two messages of the same type are received in the same clock cycle (back-to-back) then no indication is given for the.." "0,1" newline bitfld.long 0x0 2. "INTR_RADM_VENDOR_MSG,One-cycle pulse that indicates the controller received a vendor-defined message. The controller makes the message header available the radm_msg_payload output. When FX_TLP > 1 and when two messages of the same type are received in.." "0,1" newline bitfld.long 0x0 1. "INTR_PERSTN,INTR_PERSTN This interrupt status bit indicates PERST# pad input fall edge detected." "0,1" newline bitfld.long 0x0 0. "INTR_WAKEN,INTR_WAKEN This interrupt status bit indicates WAKE# pad input fall edge detected." "0,1" line.long 0x4 "INTR_1,INTR_1" bitfld.long 0x4 31. "INTR_TRGT_CPL_TIMEOUT,Indicates that the application has not generated a completion for an incoming request within the required time interval. Information about the timed out completion is available the trgt_timeout_* outputs listed later.When a.." "0,1" newline bitfld.long 0x4 30. "INTR_RADM_CPL_TIMEOUT,Indicates that the completion TLP for a request has not been received within the expected time window." "0,1" newline hexmask.long.byte 0x4 26.--29. 1. "INTR_INT_D_A,INTR_INT_D_A These Interrupt status bit indicates wheter Legacy A~D transmitted or received by controller. bit 29 : INT_D .. bit26 : INT_A" newline bitfld.long 0x4 24.--25. "INTR_CFG_SEND_F_ERR,Sent Fatal Error. Controller has sent a message towards the Root Complex indicating that an Rx TLP that contained a fatal error and that can not be corrected was received by the EndPoint" "0,1,2,3" newline bitfld.long 0x4 22.--23. "INTR_CFG_SEND_NF_ERR,Sent Non-Fatal Error. Controller has sent a message towards the Root Complex indicating that an Rx TLP that contained an non-fatal error and that can not be corrected was received by the EndPoint" "0,1,2,3" newline bitfld.long 0x4 20.--21. "INTR_CFG_SEND_COR_ERR,Sent Correctable Error. Core has sent a message towards the Root Complex indicating that an Rx TLP that contained an error and that can be corrected was received by the EndPoint" "0,1,2,3" newline bitfld.long 0x4 18.--19. "INTR_CFG_FLR_PF_ACTIVE,Set when the software initiates FLR a physical function by writing to the 'Initiate FLR' register bit of that function. This signal is held asserted until reset of both the application and controller logic has been completed." "0,1,2,3" newline bitfld.long 0x4 16.--17. "INTR_PF_FRS_GRANT,Indicator of when an FRS message for this function has been scheduled for transmission." "0,1,2,3" newline hexmask.long.byte 0x4 8.--15. 1. "INTR_CFG_FLR_VF_ACTIVE,Set when the software initiates FLR a virtual function by writing to the 'Initiate FLR' register bit of that function. This signal is held asserted until the reset of both the application and internal controller logic has been.." newline hexmask.long.byte 0x4 0.--7. 1. "INTR_VF_FRS_GRANT,Indicator of when an FRS message for this VF has been scheduled for transmission." repeat 10. (list 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB )(list 0x0 0x4 0x8 0xC 0x10 0x14 0x18 0x1C 0x20 0x24 ) group.long ($2+0x8)++0x3 line.long 0x0 "INTR_$1,INTR_2" hexmask.long 0x0 0.--31. 1. "INTR_MSI_PF0,INTR_MSI_PF0" repeat.end group.long 0x30++0xB line.long 0x0 "INTR_12,INTR_12" newline hexmask.long.byte 0x0 16.--23. 1. "INTR_RADM_TRGT1_ATU_CBUF_ERR,INTR_RADM_TRGT1_ATU_CBUF_ERR" newline hexmask.long.byte 0x0 8.--15. 1. "INTR_RADM_TRGT1_ATU_SLOC_MATCH,INTR_RADM_TRGT1_ATU_SLOC_MATCH" newline bitfld.long 0x0 7. "INTR_RADM_CORRECTABLE_ERR,INTR_RADM_CORRECTABLE_ERR" "0,1" newline bitfld.long 0x0 6. "INTR_RADM_NONFATAL_ERR,INTR_RADM_NONFATAL_ERR" "0,1" newline bitfld.long 0x0 5. "INTR_RADM_FATAL_ERR,INTR_RADM_FATAL_ERR" "0,1" newline bitfld.long 0x0 3.--4. "INTR_CFG_AER_RC_ERR_MSI,INTR_CFG_AER_RC_ERR_MSI" "0,1,2,3" newline bitfld.long 0x0 1.--2. "INTR_CFG_SYS_ERR_RC,INTR_CFG_SYS_ERR_RC" "0,1,2,3" newline bitfld.long 0x0 0. "INTR_MSTR_AWMISC_INFO_EP,INTR_MSTR_AWMISC_INFO_EP" "0,1" line.long 0x4 "INTEN_0,INTEN_0" bitfld.long 0x4 31. "INTEN_PM_XTLH_BLOCK_TLP,Indicates that your application must stop generating new outgoing request TLPs due to the current power management state. Your application can continue to generate completion TLPs.This output is not used in RC mode." "0,1" newline bitfld.long 0x4 30. "INTEN_LINK_REQ_RST_NOT,Reset request because the link has gone down or the controller received a hot-reset request. A low level indicates that the controller is requesting external logic to reset the controller because the PHY link is down. When the AXI.." "0,1" newline bitfld.long 0x4 29. "INTEN_SMLH_REQ_RST_NOT,Early version of the link_req_rst_not signal." "0,1" newline bitfld.long 0x4 28. "INTEN_SMLH_LINK_UP,PHY Link up/down indicator: 1: Link is up 0: Link is down" "Link is down,Link is up" newline bitfld.long 0x4 27. "INTEN_RDLH_LINK_UP,Data link layer up/down indicator: This status from the flow control initialization state machine indicates that flow control has been initiated and the Data link layer is ready to transmit and receive packets. For multi-VC designs.." "Link is down,Link is up" newline bitfld.long 0x4 26. "INTEN_VEN_MSI_GRANT,One-cycle pulse that indicates that the controller has accepted the request to send an MSI. After asserting ven_msi_grant for one cycle the controller does not wait for ven_msi_req to be de-asserted then reasserted to generate another.." "0,1" newline bitfld.long 0x4 25. "INTEN_VEN_MSG_GRANT,One-cycle pulse that indicates that the controller has accepted the request to send the vendor-defined Message." "0,1" newline bitfld.long 0x4 23.--24. "INTEN_CFG_UP_DRS_TO_FRS,DRS to FRS Pulse. The DSP controller asserts the cfg_up_drs_to_frs output and sends an FRS message with the reason code set to 'DRS Message Received' when: It receives a DRS message and PCIE_CAP_DRS_SIGNALING_CONTROL in.." "0,1,2,3" newline bitfld.long 0x4 21.--22. "INTEN_CFG_DRS_MSI,DRS Message Received Interrupt Pulse. The DSP controller asserts the cfg_drs_msi output when all of the following are true: It receives a DRS message PCIE_CAP_DRS_SIGNALING_CONTROL in LINK_CONTROL_LINK_STATUS_REG is 2'b01 MSI or MSI-X.." "0,1,2,3" newline bitfld.long 0x4 19.--20. "INTEN_FRSQ_MSI,FRSQ Interrupt Pulse. The RC asserts this output when it receives an FRQ message or when the FRS queue overflows." "0,1,2,3" newline bitfld.long 0x4 17.--18. "INTEN_CFG_PME_MSI,The controller asserts cfg_pme_msi (as a one-cycle pulse) when all of the following conditions are true: MSI or MSI-X is enabled. The PME Interrupt Enable bit in the Root Control register is set to 1. The PME Status bit in the Root.." "0,1,2,3" newline bitfld.long 0x4 15.--16. "INTEN_HP_MSI,The controller asserts hp_msi (as a one-cycle pulse) when the logical AND of the following conditions transitions from false to true: MSI or MSI-X is enabled. Hot-Plug interrupts are enabled in the Slot Control register. Any bit in the Slot.." "0,1,2,3" newline bitfld.long 0x4 14. "INTEN_CFG_LINK_AUTO_BW_MSI,The controller sets this pin when following conditions are true: MSI or MSI-X is enabled. The Link Autonomous Bandwidth Status register (Link Status register bit 15) is updated. The Link Autonomous Bandwidth Interrupt Enable.." "0,1" newline bitfld.long 0x4 13. "INTEN_CFG_BW_MGT_MSI,The controller sets this pin when following conditions are true: MSI or MSI-X is enabled. The Link Bandwidth Management Status register (Link Control Status register bit 14) is updated The Link Bandwidth Management Interrupt Enable.." "0,1" newline bitfld.long 0x4 11.--12. "INTEN_HP_PME,The controller asserts hp_pme when all of the following conditions are true: The PME Enable bit in the Power Management Control and Status register is set to 1. Any bit in the Slot Status register transitions from 0 to 1 and the associated.." "0,1,2,3" newline bitfld.long 0x4 10. "INTEN_PTM_CLOCK_UPDATED,Indicates that the controller has updated the Local Clock." "0,1" newline bitfld.long 0x4 9. "INTEN_PTM_REQ_DUP_RX,PTM Requester Duplicate Received. Single-cycle pulse indicating PTM Requester received a duplicate TLP while PTM Requester is in the process of updating PTM local clock or Following calculation of the update when the PTM context.." "0,1" newline bitfld.long 0x4 8. "INTEN_PTM_REQ_REPLAY_TX,PTM Requester Replay Sent. Single-cycle pulse indicating PTM Requester detected a TLP replay being sent when ResponseD messages are in use while PTM Requester is in the process of updating PTM local clock or Following.." "0,1" newline bitfld.long 0x4 7. "INTEN_RADM_MSG_LTR,One-clock-cycle pulse that indicates that the controller received an LTR message. The controller makes the message header available the radm_msg_payload output. It is also available the app_ltr_latency output. When RX_TLP > 1 and when.." "0,1" newline bitfld.long 0x4 6. "INTEN_RADM_MSG_UNLOCK,One-cycle pulse that indicates that the controller received an Unlock message. When RX_TLP > 1 and when two messages of the same type are received in the same clock cycle (back-to-back) then no separate indication is given for the.." "0,1" newline bitfld.long 0x4 5. "INTEN_RADM_PM_PME,One-clock-cycle pulse that indicates that the controller received a PM_PME message." "0,1" newline bitfld.long 0x4 4. "INTEN_RADM_PM_TO_ACK,One-clock-cycle pulse that indicates that the controller received a PME_TO_Ack message. Upstream port: Reserved." "0,1" newline bitfld.long 0x4 3. "INTEN_RADM_PM_TURNOFF,One-clock-cycle pulse that indicates that the controller received a PME Turnoff message. When RX_TLP > 1 and when two messages of the same type are received in the same clock cycle (back-to-back) then no indication is given for the.." "0,1" newline bitfld.long 0x4 2. "INTEN_RADM_VENDOR_MSG,One-cycle pulse that indicates the controller received a vendor-defined message. The controller makes the message header available the radm_msg_payload output. When FX_TLP > 1 and when two messages of the same type are received in.." "0,1" newline bitfld.long 0x4 1. "INTEN_PERSTN,INTEN_PERSTN Interrupt Enable bit for INTR_PERSTN." "0,1" newline bitfld.long 0x4 0. "INTEN_WAKEN,INTEN_WAKEN Interrupt Enable bit for INTR_WAKEN." "0,1" line.long 0x8 "INTEN_1,INTEN_1" bitfld.long 0x8 31. "INTEN_TRGT_CPL_TIMEOUT,Indicates that the application has not generated a completion for an incoming request within the required time interval. Information about the timed out completion is available the trgt_timeout_* outputs listed later.When a.." "0,1" newline bitfld.long 0x8 30. "INTEN_RADM_CPL_TIMEOUT,Indicates that the completion TLP for a request has not been received within the expected time window." "0,1" newline hexmask.long.byte 0x8 26.--29. 1. "INTEN_INT_D_A,INTEN_INT_D_A Interrupt Enable bit for INTR_D_A. Bit 29 : INT_D ... Bit26 : INT_A." newline bitfld.long 0x8 24.--25. "INTEN_CFG_SEND_F_ERR,Sent Fatal Error. Controller has sent a message towards the Root Complex indicating that an Rx TLP that contained a fatal error and that can not be corrected was received by the EndPoint" "0,1,2,3" newline bitfld.long 0x8 22.--23. "INTEN_CFG_SEND_NF_ERR,Sent Non-Fatal Error. Controller has sent a message towards the Root Complex indicating that an Rx TLP that contained an non-fatal error and that can not be corrected was received by the EndPoint" "0,1,2,3" newline bitfld.long 0x8 20.--21. "INTEN_CFG_SEND_COR_ERR,Sent Correctable Error. Core has sent a message towards the Root Complex indicating that an Rx TLP that contained an error and that can be corrected was received by the EndPoint" "0,1,2,3" newline bitfld.long 0x8 18.--19. "INTEN_CFG_FLR_PF_ACTIVE,Set when the software initiates FLR a physical function by writing to the 'Initiate FLR' register bit of that function. This signal is held asserted until reset of both the application and controller logic has been completed." "0,1,2,3" newline bitfld.long 0x8 16.--17. "INTEN_PF_FRS_GRANT,Indicator of when an FRS message for this function has been scheduled for transmission." "0,1,2,3" newline hexmask.long.byte 0x8 8.--15. 1. "INTEN_CFG_FLR_VF_ACTIVE,Set when the software initiates FLR a virtual function by writing to the 'Initiate FLR' register bit of that function. This signal is held asserted until the reset of both the application and internal controller logic has been.." newline hexmask.long.byte 0x8 0.--7. 1. "INTEN_VF_FRS_GRANT,Indicator of when an FRS message for this VF has been scheduled for transmission." repeat 10. (list 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB )(list 0x0 0x4 0x8 0xC 0x10 0x14 0x18 0x1C 0x20 0x24 ) group.long ($2+0x3C)++0x3 line.long 0x0 "INTEN_$1,INTEN_2" hexmask.long 0x0 0.--31. 1. "INTEN_MSI_PF0,INTEN_MSI_PF0" repeat.end group.long 0x64++0x13 line.long 0x0 "INTEN_12,INTEN_12" newline hexmask.long.byte 0x0 16.--23. 1. "INTEN_RADM_TRGT1_ATU_CBUF_ERR,INTEN_RADM_TRGT1_ATU_CBUF_ERR" newline hexmask.long.byte 0x0 8.--15. 1. "INTEN_RADM_TRGT1_ATU_SLOC_MATCH,INTEN_RADM_TRGT1_ATU_SLOC_MATCH" newline bitfld.long 0x0 7. "INTEN_RADM_CORRECTABLE_ERR,INTEN_RADM_CORRECTABLE_ERR" "0,1" newline bitfld.long 0x0 6. "INTEN_RADM_NONFATAL_ERR,INTEN_RADM_NONFATAL_ERR" "0,1" newline bitfld.long 0x0 5. "INTEN_RADM_FATAL_ERR,INTEN_RADM_FATAL_ERR" "0,1" newline bitfld.long 0x0 3.--4. "INTEN_CFG_AER_RC_ERR_MSI,INTEN_CFG_AER_RC_ERR_MSI" "0,1,2,3" newline bitfld.long 0x0 1.--2. "INTEN_CFG_SYS_ERR_RC,INTEN_CFG_SYS_ERR_RC" "0,1,2,3" newline bitfld.long 0x0 0. "INTEN_MSTR_AWMISC_INFO_EP,INTEN_MSTR_AWMISC_INFO_EP" "0,1" line.long 0x4 "CTRL_0,CTRL_0" bitfld.long 0x4 31. "APP_FLR_VF_DONE_7,Indicates that FLR a virtual function has been completed which means the application has completed initializing its data structures for the function and there are no more TLPs associated with this function in the application's transmit.." "0,1" newline bitfld.long 0x4 30. "APP_FLR_VF_DONE_6,Similar to above." "0,1" newline bitfld.long 0x4 29. "APP_FLR_VF_DONE_5,Similar to above." "0,1" newline bitfld.long 0x4 28. "APP_FLR_VF_DONE_4,Similar to above." "0,1" newline bitfld.long 0x4 27. "APP_FLR_VF_DONE_3,Similar to above." "0,1" newline bitfld.long 0x4 26. "APP_FLR_VF_DONE_2,Similar to above." "0,1" newline bitfld.long 0x4 25. "APP_FLR_VF_DONE_1,Similar to above." "0,1" newline bitfld.long 0x4 24. "APP_FLR_VF_DONE_0,Similar to above." "0,1" newline bitfld.long 0x4 23. "APP_FLR_PF_DONE_1,Indicates that FLR a physical function has been completed which means the application has completed initializing its data structures for the function and there are no more TLPs associated with this function in the application's.." "0,1" newline bitfld.long 0x4 22. "APP_FLR_PF_DONE_0,Similar to above." "0,1" newline bitfld.long 0x4 21. "OUTBAND_PWRUP_CMD_1,Wake Up. If PME is enabled and PME support is configured for current PMCSR D-state asserting this signal causes the controller to wake from either L1 or L2 state. When the controller has transitioned back to the L0 state it transmits.." "0,1" newline bitfld.long 0x4 20. "OUTBAND_PWRUP_CMD_0,Similar to above." "0,1" newline bitfld.long 0x4 19. "APP_REQ_EXIT_L1,Application request to Exit L1. Request from your application to exit L1.It is only effective when L1 is enabled." "0,1" newline bitfld.long 0x4 18. "APP_REQ_ENTR_L1,Application request to Enter L1 ASPM state. The app_req_entr_l1 signal is for use by applications that need to control L1 entry instead of using the L1 entry timer as defined in the PCI Express Specification. It is only effective when L1.." "0,1" newline bitfld.long 0x4 17. "APP_UNLOCK_MSG,Request from your application to generate an Unlock message. You must assert this signal for one clock cycle. The controller does not return an acknowledgment or grant signal. You must not pulse the same signal again until the previous.." "0,1" newline bitfld.long 0x4 16. "APP_PM_XMT_PME_1,Wake Up. If PME is enabled and PME support is configured for current PMCSR D-state asserting this signal causes the controller to wake from either L1 or L2 state. When the controller has transitioned back to the L0 state it transmits a.." "0,1" newline bitfld.long 0x4 15. "APP_PM_XMT_PME_0,Similar to above." "0,1" newline bitfld.long 0x4 14. "APP_PM_XMT_TURNOFF,Request from your application to generate a PM_Turn_Off message.You must assert this signal for one clock cycle. The controller does not return an acknowledgment or grant signal. You must not pulse the same signal again until the.." "0,1" newline bitfld.long 0x4 13. "APP_INIT_RST,Request from your application to send a hot reset to the upstream port.The hot reset request is sent when a single cycle pulse is applied to this pin. In an upstream port you should set this input to '0'." "0,1" newline bitfld.long 0x4 12. "APP_HDR_VALID,One-clock-cycle pulse indicating that the data app_hdr_log app_err_bus app_err_func_num and app_tlp_prfx_log is valid." "0,1" newline bitfld.long 0x4 11. "APP_L1SUB_DISABLE,The application can set this input to 1'b1 to prevent entry to L1 Sub-states. This pin is used to gate the L1 sub-state enable bits from the L1 PM Substates Control 1 Register." "0,1" newline bitfld.long 0x4 10. "APP_CLK_PM_EN,Clock PM feature enabled by application. Used to inhibit the programming of the Clock PM in Link Control Register. For more details see 'L1 with Clock PM (L1 with REFCLK removal/PLL Off)'." "0,1" newline bitfld.long 0x4 9. "APP_XFER_PENDING,Indicates that your application has transfers pending and prevents the controller from entering L1. If the entry into L1 is already in progress assertion of app_xfer_pending causes an exit from L1. This is a level signal used to inform.." "0,1" newline bitfld.long 0x4 8. "APP_READY_ENTR_L23,Application Ready to Enter L23. Indication from your application that it is ready to enter the L23 state. The app_ready_entr_l23 signal is provided for applications that must control L23 entry (in case certain tasks must be performed.." "0,1" newline bitfld.long 0x4 7. "APP_CLK_REQ_N,Indicates that the application logic is ready to have reference clock removed. In designs which support reference clock removal through either L1 PM Sub-states or L1 CPM the application should set this signal to 1'b when it is ready to.." "0,1" newline bitfld.long 0x4 6. "APP_HOLD_PHY_RST,Set this signal to one before the de-assertion of power on reset to hold the PHY in reset. This can be used to configure your PHY. Synopsys PHYs can be configured through the PHY Viewport if desired. Please tie this port to zero if your.." "0,1" newline bitfld.long 0x4 5. "APP_SRIS_MODE,SRIS operating mode: 0b: non-SRIS mode 1b: SRIS mode" "0,1" newline bitfld.long 0x4 4. "APP_DBI_RO_WR_DISABLE,DBI Read-only Write Disable 0: MISC_CONTROL_1_OFF.DBI_RO_WR_EN register field is read-write. 1: MISC_CONTROL_1_OFF.DBI_RO_WR_EN register field is forced to 0 and is read-only." "MISC_CONTROL_1_OFF,MISC_CONTROL_1_OFF" newline bitfld.long 0x4 3. "DEVICE_TYPE,Device/port type. Indicates the specific type of this PCI Express function. It is also used to set the 'Device/Port Type' field of the 'PCI Express Capabilities Register'. The controller uses this input to determine the operating mode of the.." "PCI Express endpoint,Legacy PCI Express endpoint" newline bitfld.long 0x4 2. "APP_LTSSM_ENABLE,To do otherwise (that is de-assert it outside of the Detect LTSSM state) causes the controller to be reset and the LTSSM moves immediately back to the Detect state. This transition is outside of the PCIe Specification and it might cause.." "0,1" newline bitfld.long 0x4 0. "APP_ERR_VFUNC_ACTIVE,Indicates the function number in app_err_vfunc_num is valid." "0,1" line.long 0x8 "CTRL_1,CTRL_1" bitfld.long 0x8 29.--31. "APP_ERR_VFUNC_NUM,The number of the virtual function that is reporting the error indicated app_err_bus valid when app_hdr_valid is asserted. Uncorrected Internal errors (app_err_bus[9]) are not recorded for virtual functions.The PCIe SR-IOV.." "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 28. "SLV_ARMISC_INFO_ATU_BYPASS,AXI Slave Read Request Internal ATU Bypass. When set it indicates that this request should not be processed by the internal address translation unit" "0,1" newline hexmask.long.word 0x8 15.--27. 1. "APP_ERR_BUS,The type of error that your application detected. The controller combines the values the app_err_bus bits with the internally-detected error signals to set the corresponding bit in the Uncorrectable or Correctable Error Status Registers:.." newline bitfld.long 0x8 14. "APP_REQ_RETRY_EN,Provides a capability to defer incoming configuration requests until initialization is complete. When app_req_retry_en is asserted the controller completes incoming configuration requests with a configuration request retry status. Other.." "0,1" newline hexmask.long.byte 0x8 6.--13. 1. "APP_VF_REQ_RETRY_EN,Provides a per Virtual Function (VF) capability to defer incoming configuration requests until initialization is complete. When app_vf_req_retry_en is asserted for a certain VF the controller completes incoming configuration requests.." newline bitfld.long 0x8 4.--5. "APP_PF_REQ_RETRY_EN,Provides a per Physical Function (PF) capability to defer incoming configuration requests until initialization is complete. When app_pf_req_retry_en is asserted for a certain PF the controller completes incoming configuration.." "0,1,2,3" newline bitfld.long 0x8 2.--3. "APP_RAS_DES_TBA_CTRL,Controls the start/end of time based analysis. You must only set the pins to the required value for the duration of one clock cycle. This signal must be 2'b00 while the TIMER_START field in TIME_BASED_ANALYSIS_CONTROL_REG register is.." "No action,Start,End,Reserved" newline bitfld.long 0x8 1. "APP_RAS_DES_SD_HOLD_LTSSM,Hold and release LTSSM. For as long as this signal is '1' thecontroller stays in the current LTSSM." "0,1" newline bitfld.long 0x8 0. "SYS_AUX_PWR_DET,Auxiliary Power Detected. Used to report to the host software that auxiliary power (Vaux) is present." "0,1" line.long 0xC "CTRL_2,CTRL_2" bitfld.long 0xC 30.--31. "SYS_PWR_FAULT_DET,Power Fault Detected. Indicates the power controller detected a power fault at this slot. There is a separate sys_pwr_fault_det input bit for each function in your controller configuration." "0,1,2,3" newline bitfld.long 0xC 28.--29. "SYS_MRL_SENSOR_STATE,MRL Sensor State. Indicates the state of the manually-operated retention latch (MRL) sensor: 0: MRL is closed 1: MRL is open There is a separate sys_mrl_sensor_state input bit for each function in your controller configuration." "MRL is closed,MRL is open,?,?" newline bitfld.long 0xC 26.--27. "SYS_PRE_DET_STATE,Presence Detect State. Indicates whether or not a card is present in the slot: 0: Slot is empty 1: Card is present in the slot" "Slot is empty,Card is present in the slot,?,?" newline bitfld.long 0xC 24.--25. "SYS_ATTEN_BUTTON_PRESSED,Attention Button Pressed. Indicates that the system attention button was pressed sets the Attention Button Pressed bit in the Slot Status Register." "0,1,2,3" newline bitfld.long 0xC 23. "TX_LANE_FLIP_EN,Performs manual lane reversal for transmit lanes. For use when automatic lane reversal does not occur because lane 0 is not detected.In most cases tx_lane_flip_en should be wired to a static value at the chip level." "0,1" newline bitfld.long 0xC 22. "RX_LANE_FLIP_EN,Performs manual lane reversal for receive lanes. For use when automatic lane reversal does not occur because lane 0 is not detected.In most cases rx_lane_flip_en should be wired to a static value at the chip level." "0,1" newline bitfld.long 0xC 21. "DBG_PBA,MSIX PBA RAM Debug Mode. Use this input to activate the debug mode and allow direct read/write access to the PBA. You can also use the MSIX_RAM_CTRL_DBG_PBA field in MSIX_RAM_CTRL_OFF to activate debug mode. Debug mode turns off the.." "0,1" newline bitfld.long 0xC 20. "DBG_TABLE,MSIX Table RAM Debug Mode. Use this input to activate the debug mode and allow direct read/write access to the Table." "0,1" newline bitfld.long 0xC 19. "APP_ERR_FUNC_NUM,The number of the function that is reporting the error indicated app_err_bus valid when app_hdr_valid is asserted. Correctable and Uncorrected Internal errors (app_err_bus[10:9]) are not function specific and are recorded for all.." "0,1" newline bitfld.long 0xC 18. "APP_ERR_ADVISORY,Indicates that your application error is an advisory error. Your application should assert app_err_advisory under either of the following conditions: The controller is configured to mask completion timeout errors your application is.." "0,1" newline bitfld.long 0xC 17. "WAKEN_DO_OVRDVAL,WAKEN_DO_OVRDVAL" "0,1" newline bitfld.long 0xC 16. "WAKEN_DO_OVRDEN,WAKEN_DO_OVRDEN" "0,1" newline bitfld.long 0xC 15. "WAKEN_OE_OVRDVAL,WAKEN_OE_OVRDVAL" "0,1" newline bitfld.long 0xC 14. "WAKEN_OE_OVRDEN,WAKEN_OE_OVRDEN" "0,1" newline bitfld.long 0xC 13. "WAKEN_IN_OVRDVAL,WAKEN_IN_OVRDVAL" "0,1" newline bitfld.long 0xC 12. "WAKEN_IN_OVRDEN,WAKEN_IN_OVRDEN" "0,1" newline bitfld.long 0xC 11. "PERSTN_DO_OVRDVAL,PERSTN_DO_OVRDVAL" "0,1" newline bitfld.long 0xC 10. "PERSTN_DO_OVRDEN,PERSTN_DO_OVRDEN" "0,1" newline bitfld.long 0xC 9. "PERSTN_OE_OVRDVAL,PERSTN_OE_OVRDVAL" "0,1" newline bitfld.long 0xC 8. "PERSTN_OE_OVRDEN,PERSTN_OE_OVRDEN" "0,1" newline bitfld.long 0xC 7. "PERSTN_IN_OVRDVAL,PERSTN_IN_OVRDVAL" "0,1" newline bitfld.long 0xC 6. "PERSTN_IN_OVRDEN,PERSTN_IN_OVRDEN" "0,1" newline bitfld.long 0xC 5. "CLKREQN_DO_OVRDVAL,CLKREQN_DO_OVRDVAL" "0,1" newline bitfld.long 0xC 4. "CLKREQN_DO_OVRDEN,CLKREQN_DO_OVRDEN" "0,1" newline bitfld.long 0xC 3. "CLKREQN_OE_OVRDVAL,CLKREQN_OE_OVRDVAL" "0,1" newline bitfld.long 0xC 2. "CLKREQN_OE_OVRDEN,CLKREQN_OE_OVRDEN" "0,1" newline bitfld.long 0xC 1. "CLKREQN_IN_OVRDVAL,CLKREQN_IN_OVRDVAL" "0,1" newline bitfld.long 0xC 0. "CLKREQN_IN_OVRDEN,CLKREQN_IN_OVRDEN" "0,1" line.long 0x10 "CTRL_3,CTRL_3" bitfld.long 0x10 30.--31. "SYS_MRL_SENSOR_CHGED,MRL Sensor Changed. Indicates that the state of MRL sensor has changed. There is a separate sys_mrl_sensor_chged input bit for each function in your controller configuration." "0,1,2,3" newline hexmask.long.word 0x10 20.--29. 1. "VEN_MSG_LEN,The Length field for the vendor-defined Message TLP (indicates length of data payload in dwords).Should be set to 0x0." newline hexmask.long.byte 0x10 15.--19. 1. "VEN_MSG_TYPE,The Type field for the vendor-defined Message TLP." newline bitfld.long 0x10 12.--14. "VEN_MSG_VFUNC_NUM,Number of the virtual function accessing the VMI interface. The PCIe SR-IOV specification starts numbering VFs at 1. To ease timing during synthesis the PCIe controller starts numbering VFs at 0. For example ven_msg_vfunc_num=0 refers.." "0,1,2,3,4,5,6,7" newline bitfld.long 0x10 9.--11. "VEN_MSG_TC,The Traffic Class field for the vendor-defined Message TLP." "0,1,2,3,4,5,6,7" newline bitfld.long 0x10 7.--8. "VEN_MSG_ATTR,The Attributes field for the vendor-defined Message TLP. - Width is three bits when CX_IDO_ENABLE =1 - Width is two bits when CX_IDO_ENABLE =0" "?,Width is two bits when CX_IDO_ENABLE =0,?,?" newline bitfld.long 0x10 5.--6. "VEN_MSG_FMT,The Format field for the vendor-defined Message TLP. Should be set to 0x1." "0,1,2,3" newline bitfld.long 0x10 4. "VEN_MSG_VFUNC_ACTIVE,Indicates that a VF is accessing the VMI. - 0: No VF is active and ven_msg_vfunc_num is invalid. A PF is valid and identified by ven_msg_func_num. - 1: A VF is active and is identified by ven_msg_vfunc_num." "No VF is active and ven_msg_vfunc_num is invalid,A VF is active and is identified by.." newline bitfld.long 0x10 3. "VEN_MSG_FUNC_NUM,Function Number for the vendor-defined Message TLP. Function numbering starts at '0'." "0,1" newline bitfld.long 0x10 2. "VEN_MSG_EP,The Poisoned TLP (EP) bit for the vendor-defined Message TLP." "0,1" newline bitfld.long 0x10 1. "VEN_MSG_TD,The TLP Digest (TD) bit for the vendor-defined Message TLP valid when ven_msg_req is asserted." "0,1" newline bitfld.long 0x10 0. "VEN_MSG_REQ,Request from your application to send a vendor-defined Message. Once asserted ven_msg_req must remain asserted until the controller asserts ven_msg_grant." "0,1" repeat 16. (list 0x4 0x5 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF 0x10 0x11 0x13 0x14 0x15 0x17 )(list 0x0 0x4 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x3C 0x40 0x44 0x4C ) group.long ($2+0x78)++0x3 line.long 0x0 "CTRL_$1,CTRL_4" hexmask.long 0x0 0.--31. 1. "VEN_MSG_DATA_31_0,Third and fourth dwords of the Vendor Defined Message header where: - Bytes 8-11 (third header dword) =ven_msg_data[63:32] - Bytes 12-15 (fourth header dword) =ven_msg_data[31:0] where ven_msg_data[7:0] =byte 15" repeat.end repeat 12. (list 0x19 0x1A 0x1B 0x1D 0x1E 0x1F 0x20 0x21 0x22 0x23 0x24 0x25 )(list 0x54 0x58 0x5C 0x64 0x68 0x6C 0x70 0x74 0x78 0x7C 0x80 0x84 ) group.long ($2+0x78)++0x3 line.long 0x0 "CTRL_$1,CTRL_4" hexmask.long 0x0 0.--31. 1. "VEN_MSG_DATA_31_0,Third and fourth dwords of the Vendor Defined Message header where: - Bytes 8-11 (third header dword) =ven_msg_data[63:32] - Bytes 12-15 (fourth header dword) =ven_msg_data[31:0] where ven_msg_data[7:0] =byte 15" repeat.end group.long 0x80++0x7 line.long 0x0 "CTRL_6,CTRL_6" bitfld.long 0x0 31. "MSI_FNSEL,MSI_FNSEL" "0,1" newline bitfld.long 0x0 30. "VEN_MSI_OVRDEN,VEN_MSI_OVRDEN" "0,1" newline bitfld.long 0x0 29. "VEN_MSI_REQ,Request from your application to send an MSI when MSI is enabled.When MSI-X is enabled instead of MSI assertion of ven_msi_req causes the controller to generate an MSI-X message. Once asserted ven_msi_req must remain asserted until the.." "0,1" newline hexmask.long.byte 0x0 24.--28. 1. "VEN_MSI_VECTOR,Used to modulate the lower five bits of the MSI Data register when multiple message mode is enabled." newline bitfld.long 0x0 21.--23. "VEN_MSI_TC,Traffic Class of the MSI request valid when ven_msi_req is asserted." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 20. "VEN_MSI_VFUNC_ACTIVE,Indicates that the MSI request is coming from a VF. - 0: No VF is active and ven_msi_vfunc_num is invalid. A PF is valid and identified by ven_msi_func_num. - 1: A VF is active and is identified by ven_msi_vfunc_num." "No VF is active and ven_msi_vfunc_num is invalid,A VF is active and is identified by.." newline bitfld.long 0x0 17.--19. "VEN_MSI_VFUNC_NUM,Identifies the VF which is making the MSI request. The PCIe SR-IOV specification starts numbering VFs at 1. To ease timing during synthesis the PCIe controller starts numbering VFs at 0. For example ven_msi_vfunc_num=0 refers to the.." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 16. "VEN_MSI_FUNC_NUM,The function number of the MSI request. Function numbering starts at '0'." "0,1" newline hexmask.long.byte 0x0 8.--15. 1. "VEN_MSG_CODE,The Message Code for the vendor-defined Message TLP." newline hexmask.long.byte 0x0 0.--7. 1. "VEN_MSG_TAG,Tag for the vendor-defined Message TLP." line.long 0x4 "CTRL_7,CTRL_7" hexmask.long.byte 0x4 24.--31. 1. "SLV_AWMISC_INFO_P_TAG,AXI Slave Write Request Tag. Sets the TAG number for output posted requests. It is expected that your application normally sets this to '0' except when generating ATS invalidate requests." newline bitfld.long 0x4 23. "SLV_WMISC_INFO_EP,AXI Slave Write Data transaction related misc information. This is an optional signal that your application can use to poison write requests.When asserted the controller sets the Poisoned TLP (EP) bit in the TLP header of the current.." "0,1" newline bitfld.long 0x4 22. "PTM_AUTO_UPDATE_SIGNAL,Indicates that the controller should update the PTM Requester Context and Clock automatically every 10ms." "0,1" newline bitfld.long 0x4 21. "PTM_MANUAL_UPDATE_PULSE,Indicates that the controller should update the PTM Requester Context and Clock now." "0,1" newline bitfld.long 0x4 20. "PTM_EXTERNAL_MASTER_STROBE,PTM External Master Time Strobe." "0,1" newline hexmask.long.byte 0x4 12.--19. 1. "APP_VF_FRS_READY,Defers FRS messaging for a VF when set to '0'." newline bitfld.long 0x4 10.--11. "APP_PF_FRS_READY,Defers FRS messaging when set to '0'." "0,1,2,3" newline bitfld.long 0x4 9. "APP_DRS_READY,Defers DRS messaging when set to '0'." "0,1" newline bitfld.long 0x4 7.--8. "SYS_EML_INTERLOCK_ENGAGED,System Electromechanical Interlock Engaged. Indicates whether the system electromechanical interlock is engaged and controls the state of the Electromechanical Interlock Status bit in the Slot Status register." "0,1,2,3" newline bitfld.long 0x4 5.--6. "SYS_CMD_CPLED_INT,Command completed Interrupt. Indicates that the Hot-Plug controller completed a command. There is a separate sys_cmd_cpled_int input bit for each function in your controller configuration." "0,1,2,3" newline bitfld.long 0x4 3.--4. "SYS_PRE_DET_CHGED,Presence Detect Changed. Indicates that the state of card present detector has changed. There is a separate sys_pre_det_chged input bit for each function in your controller configuration." "0,1,2,3" newline bitfld.long 0x4 0.--2. "DIAG_CTRL_BUS,Diagnostic Control Bus - x01: Insert LCRC error by inverting the LSB of LCRC - x10: Insert ECRC error by inverting the LSB of ECRC The rising edge of these two signals ([1:0]) enable the controller to assert an LCRC or ECRC to the packet.." "?,Insert LCRC error by inverting the LSB of LCRC,?,?,?,?,?,?" group.long 0xB0++0x3 line.long 0x0 "CTRL_18,CTRL_18" bitfld.long 0x0 31. "SLV_USER_SEL,SLV_USER_SEL" "0,1" newline bitfld.long 0x0 29.--30. "MSTR_ARUSER_OVRDVAL_33_32,MSTR_ARUSER_OVRDVAL_33_32" "0,1,2,3" newline bitfld.long 0x0 27.--28. "MSTR_AWUSER_OVRDVAL_33_32,MSTR_AWUSER_OVRDVAL_33_32" "0,1,2,3" newline bitfld.long 0x0 26. "APP_LTR_MSG_FUNC_NUM,APP_LTR_MSG_FUNC_NUM" "0,1" newline bitfld.long 0x0 25. "APP_LTR_MSG_REQ,APP_LTR_MSG_REQ" "0,1" newline bitfld.long 0x0 24. "APP_PM_VF_XMT_PME_7,APP_PM_VF_XMT_PME_7" "0,1" newline bitfld.long 0x0 23. "APP_PM_VF_XMT_PME_6,APP_PM_VF_XMT_PME_6" "0,1" newline bitfld.long 0x0 22. "APP_PM_VF_XMT_PME_5,APP_PM_VF_XMT_PME_5" "0,1" newline bitfld.long 0x0 21. "APP_PM_VF_XMT_PME_4,APP_PM_VF_XMT_PME_4" "0,1" newline bitfld.long 0x0 20. "APP_PM_VF_XMT_PME_3,APP_PM_VF_XMT_PME_3" "0,1" newline bitfld.long 0x0 19. "APP_PM_VF_XMT_PME_2,APP_PM_VF_XMT_PME_2" "0,1" newline bitfld.long 0x0 18. "APP_PM_VF_XMT_PME_1,APP_PM_VF_XMT_PME_1" "0,1" newline bitfld.long 0x0 17. "APP_PM_VF_XMT_PME_0,APP_PM_VF_XMT_PME_0" "0,1" newline hexmask.long.word 0x0 4.--16. 1. "MSTR_RMISC_INFO,MSTR_RMISC_INFO" newline bitfld.long 0x0 2.--3. "MSTR_RMISC_INFO_CPL_STAT,MSTR_RMISC_INFO_CPL_STAT" "0,1,2,3" newline bitfld.long 0x0 0.--1. "MSTR_BMISC_INFO_CPL_STAT,MSTR_BMISC_INFO_CPL_STAT" "0,1,2,3" group.long 0xC0++0x3 line.long 0x0 "CTRL_22,CTRL_22" bitfld.long 0x0 31. "SLV_WMISC_INFO_SILENTDROP,SLV_WMISC_INFO_SILENTDROP" "0,1" newline bitfld.long 0x0 28.--30. "SLV_AWMISC_INFO_VFUNC_NUM,SLV_AWMISC_INFO_VFUNC_NUM" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 27. "SLV_AWMISC_INFO_VFUNC_ACTIVE,SLV_AWMISC_INFO_VFUNC_ACTIVE" "0,1" newline bitfld.long 0x0 26. "SLV_AWMISC_INFO_FUNC_NUM,SLV_AWMISC_INFO_FUNC_NUM" "0,1" newline bitfld.long 0x0 25. "SLV_AWMISC_INFO_ATU_BYPASS,SLV_AWMISC_INFO_ATU_BYPASS" "0,1" newline hexmask.long 0x0 0.--24. 1. "SLV_AWMISC_INFO,SLV_AWMISC_INFO" group.long 0xC8++0x3 line.long 0x0 "CTRL_24,CTRL_24" bitfld.long 0x0 30.--31. "MSTR_USER_SEL,MSTR_USER_SEL" "0,1,2,3" newline bitfld.long 0x0 27.--29. "SLV_ARMISC_INFO_VFUNC_NUM,SLV_ARMISC_INFO_VFUNC_NUM" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 26. "SLV_ARMISC_INFO_VFUNC_ACTIVE,SLV_ARMISC_INFO_VFUNC_ACTIVE" "0,1" newline bitfld.long 0x0 25. "SLV_ARMISC_INFO_FUNC_NUM,SLV_ARMISC_INFO_FUNC_NUM" "0,1" newline hexmask.long 0x0 0.--24. 1. "SLV_ARMISC_INFO,SLV_ARMISC_INFO" group.long 0xD8++0x3 line.long 0x0 "CTRL_28,CTRL_28" hexmask.long.word 0x0 21.--31. 1. "RSVD0,RSVD0" newline hexmask.long.byte 0x0 13.--20. 1. "APP_BUS_NUM,APP_BUS_NUM" newline hexmask.long.byte 0x0 8.--12. 1. "APP_DEV_NUM,APP_DEV_NUM" newline bitfld.long 0x0 7. "APP_MSI_CTRL_EN,APP_MSI_CTRL_EN" "0,1" newline hexmask.long.byte 0x0 0.--6. 1. "STS_DEBUG_SEL,STS_DEBUG_SEL" repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x4 0x8 0xC 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C ) group.long ($2+0x100)++0x3 line.long 0x0 "MAP_$1,MAP_0" hexmask.long 0x0 0.--31. 1. "LUT_MAP_MID_31_0,LUT_MAP_MID_31_0" repeat.end repeat 16. (list 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1A 0x1B 0x1C 0x1D 0x1E 0x1F )(list 0x40 0x44 0x48 0x4C 0x50 0x54 0x58 0x5C 0x60 0x64 0x68 0x6C 0x70 0x74 0x78 0x7C ) group.long ($2+0x100)++0x3 line.long 0x0 "MAP_$1,MAP_0" hexmask.long 0x0 0.--31. 1. "LUT_MAP_MID_31_0,LUT_MAP_MID_31_0" repeat.end repeat 16. (list 0x20 0x21 0x22 0x23 0x24 0x25 0x26 0x27 0x28 0x29 0x2A 0x2B 0x2C 0x2D 0x2E 0x2F )(list 0x80 0x84 0x88 0x8C 0x90 0x94 0x98 0x9C 0xA0 0xA4 0xA8 0xAC 0xB0 0xB4 0xB8 0xBC ) group.long ($2+0x100)++0x3 line.long 0x0 "MAP_$1,MAP_0" hexmask.long 0x0 0.--31. 1. "LUT_MAP_MID_31_0,LUT_MAP_MID_31_0" repeat.end repeat 16. (list 0x30 0x31 0x32 0x33 0x34 0x35 0x36 0x37 0x38 0x39 0x3A 0x3B 0x3C 0x3D 0x3E 0x3F )(list 0xC0 0xC4 0xC8 0xCC 0xD0 0xD4 0xD8 0xDC 0xE0 0xE4 0xE8 0xEC 0xF0 0xF4 0xF8 0xFC ) group.long ($2+0x100)++0x3 line.long 0x0 "MAP_$1,MAP_0" hexmask.long 0x0 0.--31. 1. "LUT_MAP_MID_31_0,LUT_MAP_MID_31_0" repeat.end rgroup.long 0x200++0x3 line.long 0x0 "STS_0,STS_0" bitfld.long 0x0 29.--31. "PM_L1SUB_STATE,Power management L1 sub-states FSM state" "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x0 24.--28. 1. "PM_MASTER_STATE,Power management master FSM state." newline bitfld.long 0x0 22.--23. "PM_PME_EN,PME Enable bit in the PMCSR. There is 1 bit of pm_pme_en for each configured function." "0,1,2,3" newline hexmask.long.byte 0x0 16.--21. 1. "PM_DSTATE,The current power management D-state of the function: - 000b: D0 - 001b: D1 - 010b: D2 - 011b: D3 - 100b: Uninitialized - Other values: Not applicable" newline bitfld.long 0x0 13.--15. "PM_CURNT_STATE,Indicates the current power state. The pm_curnt_state output is intended for debugging purposes not for system operation." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 12. "PM_L1_ENTRY_STARTED,L1 entry process is in progress." "0,1" newline bitfld.long 0x0 11. "PM_LINKST_IN_L1SUB,Power management is in L1 substate. Indicates when the link has entered L1 substates." "0,1" newline bitfld.long 0x0 10. "PM_LINKST_L2_EXIT,Power management is exiting L2 state. Not applicable for downstream port." "0,1" newline bitfld.long 0x0 9. "PM_LINKST_IN_L2,Power management is in L2 state." "0,1" newline bitfld.long 0x0 8. "PM_LINKST_IN_L1,Power management is in L1 state." "0,1" newline bitfld.long 0x0 7. "PM_LINKST_IN_L0S,Power management is in L0s state. Indicates in L0_STALL state when M-PCIe" "0,1" newline hexmask.long.byte 0x0 1.--6. 1. "SMLH_LTSSM_STATE,Current state of the LTSSM. Encoding is defined as follows: 6'h00: S_DETECT_QUIET 6'h01: S_DETECT_ACT 6'h02: S_POLL_ACTIVE 6'h03: S_POLL_COMPLIANCE 6'h04: S_POLL_CONFIG 6'h05: S_PRE_DETECT_QUIET 6'h06: S_DETECT_WAIT 6'h07:.." newline bitfld.long 0x0 0. "RADM_IDLE,RADM activity status signal. The controller creates the en_radm_clk_g output by gating this signal with the output of the RADM_CLK_GATING_EN field in the CLOCK_GATING_CTRL_OFF register. For debug purposes only." "0,1" group.long 0x204++0xB line.long 0x0 "STS_1,STS_1" bitfld.long 0x0 30.--31. "TRGT_TIMEOUT_CPL_ATTR,The Attributes value of the timed out completion. - Width is three bits when CX_IDO_ENABLE =1 - Width is two bits when CX_IDO_ENABLE =0" "?,Width is two bits when CX_IDO_ENABLE =0,?,?" newline bitfld.long 0x0 27.--29. "TRGT_TIMEOUT_CPL_TC,The TC of the timed out completion." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 26. "TRGT_TIMEOUT_CPL_VFUNC_ACTIVE,Indicates that the timeout is coming from a VF (Virtual function). - 0: No VF is active and trgt_timeout_cpl_vfunc_num is invalid. A PF is valid and identified by trgt_timeout_cpl_func_num - 1: A VF is active and is.." "No VF is active and trgt_timeout_cpl_vfunc_num..,A VF is active and is identified by.." newline bitfld.long 0x0 23.--25. "TRGT_TIMEOUT_CPL_VFUNC_NUM,Indicates which virtual function (VF) timed out. The PCIe SR-IOV specification starts numbering VFs at 1. To ease timing during synthesis the PCIe controller starts numbering VFs at 0. For example trgt_timeout_cpl_ vfunc_num=0.." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 22. "TRGT_TIMEOUT_CPL_FUNC_NUM,TRGT_TIMEOUT_CPL_FUNC_NUM" "0,1" newline hexmask.long.byte 0x0 14.--21. 1. "CFG_FLR_VF_ACTIVE,Set when the software initiates FLR a virtual function by writing to the 'Initiate FLR' register bit of that function. This signal is held asserted until the reset of both the application and internal controller logic has been.." newline rbitfld.long 0x0 12.--13. "CFG_FLR_PF_ACTIVE,Set when the software initiates FLR a physical function by writing to the 'Initiate FLR' register bit of that function. This signal is held asserted until reset of both the application and controller logic has been completed." "0,1,2,3" newline rbitfld.long 0x0 10.--11. "CFG_EML_CONTROL,Electromechanical Interlock Control. The state of the Electromechanical Interlock Control bit in the Slot Control register." "0,1,2,3" newline rbitfld.long 0x0 9. "CFG_L1SUB_EN,Indicates that any of the L1 Substates are enabled in the L1 Substates Control 1 Register. Could be used by your application in a downstream port to determine when not to drive CLKREQ# such as when L1" "0,1" newline rbitfld.long 0x0 7.--8. "AUX_PM_EN,AUX_PM_EN" "0,1,2,3" newline rbitfld.long 0x0 5.--6. "PM_STATUS,PME Status bit from the PMCSR. There is 1 bit of pm_status for each configured function." "0,1,2,3" newline hexmask.long.byte 0x0 0.--4. 1. "PM_SLAVE_STATE,Power management slave FSM state." line.long 0x4 "STS_2,STS_2" bitfld.long 0x4 30.--31. "RADM_TIMEOUT_CPL_ATTR,The Attributes field of the timed out completion" "0,1,2,3" newline rbitfld.long 0x4 29. "RADM_QOVERFLOW,Pulse indicating that one or more of the P/NP/CPL receive queues have overflowed. There is a 1-bit indication for each configured virtual channel. You can connect this output to your internal error reporting mechanism." "?,bit indication for each configured virtual channel" newline rbitfld.long 0x4 28. "RADM_Q_NOT_EMPTY,Level indicating that the receive queues contain TLP header/data." "0,1" newline bitfld.long 0x4 27. "RADM_TIMEOUT_FUNC_NUM,The function Number of the timed out completion. Function numbering starts at '0'." "0,1" newline rbitfld.long 0x4 26. "RADM_XFER_PENDING,Receive request pending status. Indicates Receive TLP requests are pending that is requests sent to the RTRGT1 or RTRGT0 interfaces are awaiting a response from your application." "0,1" newline rbitfld.long 0x4 25. "EDMA_XFER_PENDING,eDMA transfer pending status. Indicates eDMA Write or Read Channel transfers are pending that is DMA Write or Read Channels have not finished transferring data." "0,1" newline rbitfld.long 0x4 24. "BRDG_DBI_XFER_PENDING,AXI Slave DBI transfer pending status. Indicates AXI DBI Slave Read or Write transfers are pending that is AXI Slave transfers are awaiting a response from the controller." "0,1" newline rbitfld.long 0x4 22.--23. "CFG_INT_DISABLE,When high a functions ability to generate INTx messages is Disabled" "0,1,2,3" newline rbitfld.long 0x4 20.--21. "CFG_CMD_CPLED_INT_EN,Slot Control Command Completed Interrupt Enable." "0,1,2,3" newline hexmask.long.byte 0x4 12.--19. 1. "TRGT_TIMEOUT_LOOKUP_ID,The target completion LUT lookup ID of the timed out completion" newline hexmask.long.word 0x4 0.--11. 1. "TRGT_TIMEOUT_CPL_LEN,The Length of the timed out completion." line.long 0x8 "STS_3,STS_3" rbitfld.long 0x8 30.--31. "CFG_PWR_CTRLER_CTRL,Controls the system power controller (from bit 10 of the Slot Control register) per function: - 0: Power On - 1: Power Off" "Power On,Power Off,?,?" newline rbitfld.long 0x8 28.--29. "CFG_END2END_TLP_PFX_BLCK,The value of the End-End TLP Prefix Blocking field in the Device Control 2 register." "0,1,2,3" newline hexmask.long.byte 0x8 23.--27. 1. "CFG_PBUS_DEV_NUM,The device number assigned to the function. The number of bits depends the value of MULTI_DEVICE_AND_BUS_PER_FUNC_EN: - If MULTI_DEVICE_AND_BUS_PER_FUNC_EN =0 there are five bits of cfg_pbus_dev_num ([4:0]) regardless of the number of.." newline hexmask.long.word 0x8 11.--22. 1. "RADM_TIMEOUT_CPL_LEN,Length (in bytes) of the timed out completion. For a split completion it indicates the number of bytes remaining to be delivered when the completion timed out." newline hexmask.long.byte 0x8 3.--10. 1. "RADM_TIMEOUT_CPL_TAG,The Tag field of the timed out completion." newline bitfld.long 0x8 0.--2. "RADM_TIMEOUT_VFUNC_NUM,Indicates which virtual function (VF) had a completion timeout. The PCIe SR-IOV specification starts numbering VFs at '1'. To ease timing during synthesis the PCIe controller starts numbering VFs at '0' ." "0,1,2,3,4,5,6,7" rgroup.long 0x210++0xB line.long 0x0 "STS_4,STS_4" bitfld.long 0x0 31. "SMLH_LTSSM_STATE_RCVRY_EQ,This status signal is asserted during all Recovery Equalization states." "0,1" newline bitfld.long 0x0 29.--30. "CFG_DLL_STATE_CHGED_EN,Slot Control DLL State Change Enable" "0,1,2,3" newline bitfld.long 0x0 27.--28. "CFG_HP_SLOT_CTRL_ACCESS,Slot Control Accessed." "0,1,2,3" newline bitfld.long 0x0 25.--26. "CFG_RELAX_ORDER_EN,Contents of the 'Enable Relaxed Ordering' field(PCIE_CAP_EN_REL_ORDER) in the 'Device Control and Status' register (DEVICE_CONTROL_DEVICE_STATUS) register." "0,1,2,3" newline bitfld.long 0x0 23.--24. "CFG_NO_SNOOP_EN,Contents of the 'Enable No Snoop' field (PCIE_CAP_EN_NO_SNOOP)in the 'Device Control and Status' register(DEVICE_CONTROL_DEVICE_STATUS) register." "0,1,2,3" newline hexmask.long.byte 0x0 15.--22. 1. "PM_VF_STATUS,PME Status bit from the VF PMCSR. There is 1 bit of pm_status for each configured function. Each bit field corresponds to one of the NVF virtual functions." newline bitfld.long 0x0 13.--14. "CFG_VF_EN,Identifies those physical functions that have virtual functions enabled." "0,1,2,3" newline bitfld.long 0x0 11.--12. "CFG_ATTEN_BUTTON_PRESSED_EN,Slot Control Attention Button Pressed Enable." "0,1,2,3" newline bitfld.long 0x0 9.--10. "CFG_PWR_FAULT_DET_EN,Slot Control Power Fault Detect Enable." "0,1,2,3" newline bitfld.long 0x0 7.--8. "CFG_MRL_SENSOR_CHGED_EN,Slot Control MRL Sensor Changed Enable." "0,1,2,3" newline bitfld.long 0x0 5.--6. "CFG_PRE_DET_CHGED_EN,Slot Control Presence Detect Changed Enable." "0,1,2,3" newline bitfld.long 0x0 4. "PTM_REQ_RESPONSE_TIMEOUT,PTM Requester Response Timeout. Single-cycle pulse indicating 100us timeout occurred while waiting for a PTM Response or PTM ResponseD message." "0,1" newline bitfld.long 0x0 3. "PTM_TRIGGER_ALLOWED,Indicates that a PTM Requester manual update trigger is allowed." "0,1" newline bitfld.long 0x0 2. "PTM_UPDATING,Indicates that a PTM update is in progress." "0,1" newline bitfld.long 0x0 1. "PTM_RESPONDER_RDY_TO_VALIDATE,PTM Responder Ready to Validate." "0,1" newline bitfld.long 0x0 0. "PTM_CONTEXT_VALID,O Context Valid." "0,1" line.long 0x4 "STS_5,STS_5" bitfld.long 0x4 30.--31. "CFG_HP_INT_EN,Slot Control Hot Plug Interrupt Enable." "0,1,2,3" newline bitfld.long 0x4 28.--29. "CFG_CRS_SW_VIS_EN,Indicates the value of the CRS Software Visibility enable bit in the Root Control register. Applicable only for RC devices." "0,1,2,3" newline bitfld.long 0x4 26.--27. "CFG_PM_NO_SOFT_RST,This is the value of the No Soft Reset bit in the Power Management Control and Status Register." "0,1,2,3" newline hexmask.long.word 0x4 16.--25. 1. "FRSQ_INT_MSG_NUM,FRSQ Interrupt Message Number." newline hexmask.long.byte 0x4 8.--15. 1. "CFG_PBUS_NUM,The primary bus number assigned to the function. The number of bits depends the value of MULTI_DEVICE_AND_BUS_PER_FUNC_EN: - If MULTI_DEVICE_AND_BUS_PER_FUNC_EN =0 there are eight bits of cfg_pbus_num ([7:0]) regardless of the number of.." newline bitfld.long 0x4 6.--7. "CFG_RCB,The value of the RCB bit in the Link Control register. There is 1 bit of cfg_rcb assigned to each configured function." "0,1,2,3" newline hexmask.long.byte 0x4 0.--5. 1. "CFG_MAX_PAYLOAD_SIZE,The value of the Max_Payload_Size field in the Device Control register.There are 3 bits of cfg_max_payload_size assigned to each configured function." line.long 0x8 "STS_6,STS_6" newline bitfld.long 0x8 2. "BRDG_SLV_XFER_PENDING,AXI Slave non-DBI transfer pending status. Indicates AXI non-DBI Slave Read or Write transfers are pending that is AXI Slave transfers are awaiting a response from the controller." "0,1" newline bitfld.long 0x8 1. "SMLH_LINK_UP,PHY Link up/down indicator: - 1: Link is up - 0: Link is down" "Link is down,Link is up" newline bitfld.long 0x8 0. "RDLH_LINK_UP,Data link layer up/down indicator: This status from the flow control initialization state machine indicates that flow control has been initiated and the Data link layer is ready to transmit and receive packets. For multi-VC designs this.." "Link is down,Link is up" group.long 0x21C++0x7 line.long 0x0 "STS_7,STS_7" bitfld.long 0x0 29.--31. "RADM_TIMEOUT_CPL_TC,The Traffic Class of the timed out completion." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 28. "RADM_TIMEOUT_VFUNC_ACTIVE,Indicates that a virtual function (VF) had a completion timeout. - 0: No VF is active and radm_timeout_vfunc_num is invalid. A PF is valid and identified by radm_timeout_func_num. - 1: A VF is active and is identified by.." "No VF is active and radm_timeout_vfunc_num is..,A VF is active and is identified by.." newline hexmask.long.word 0x0 18.--27. 1. "CFG_PCIE_CAP_INT_MSG_NUM,From bits [13:9] of the PCI Express Capabilities register used when MSI or MSI-X is enabled. Assertion of hp_msi or cfg_pme_msi along with a value cfg_pcie_cap_int_msg_num is equivalent to the controller receiving an MSI with.." newline hexmask.long.word 0x0 8.--17. 1. "CFG_AER_INT_MSG_NUM,From bits [31:27] of the Root Error Status register used when MSI or MSI-X is enabled. Assertion of cfg_aer_rc_err_msi along with a value cfg_aer_int_msg_num is equivalent to the controller receiving an MSI with the.." newline hexmask.long.byte 0x0 0.--7. 1. "CFG_VF_BME,Bus master enable bit from the Control Register in the PCI header of each VF. Each bit field corresponds to one of the NVF virtual functions." line.long 0x4 "STS_8,STS_8" hexmask.long.word 0x4 16.--31. 1. "RADM_MSG_REQ_ID,The requester ID of the received Message. - [15:8]: Bus number - [7:3]: Device number - [2:0]: Function number" newline hexmask.long.word 0x4 0.--15. 1. "CFG_INT_PIN,The cfg_int_pin indicates the configured value for the Interrupt Pin Register field in the BRIDGE_CTRL_INT_PIN_INT_LINE register." repeat 8. (list 0x9 0xA 0xF 0x10 0x11 0x12 0x15 0x16 )(list 0x0 0x4 0x18 0x1C 0x20 0x24 0x30 0x34 ) group.long ($2+0x224)++0x3 line.long 0x0 "STS_$1,STS_9" hexmask.long 0x0 0.--31. 1. "RADM_MSG_PAYLOAD_31_0,Received message header information. When a vendor-defined or ltr messageis received (radm_vendor_msg=1 or radm_ltr_msg=1) the controller maps radm_msg_payload to the Rx TLP header dwords as follows: When RX_TLP =1 - [31:0] = bytes.." repeat.end repeat 16. (list 0xB 0xC 0xD 0xE 0x14 0x17 0x18 0x1C 0x1D 0x1E 0x1F 0x20 0x21 0x22 0x23 0x24 )(list 0x0 0x4 0x8 0xC 0x24 0x30 0x34 0x44 0x48 0x4C 0x50 0x54 0x58 0x5C 0x60 0x64 ) rgroup.long ($2+0x22C)++0x3 line.long 0x0 "STS_$1,STS_11" hexmask.long 0x0 0.--31. 1. "PTM_LOCAL_CLOCK_31_0,PTM_LOCAL_CLOCK_31_0" repeat.end repeat 3. (list 0x25 0x26 0x27 )(list 0x68 0x6C 0x70 ) rgroup.long ($2+0x22C)++0x3 line.long 0x0 "STS_$1,STS_11" hexmask.long 0x0 0.--31. 1. "PTM_LOCAL_CLOCK_31_0,PTM_LOCAL_CLOCK_31_0" repeat.end group.long 0x24C++0x3 line.long 0x0 "STS_19,STS_19" hexmask.long.word 0x0 16.--31. 1. "MSTR_ARMISC_INFO_47_32,MSTR_ARMISC_INFO_47_32" newline hexmask.long.word 0x0 0.--15. 1. "MSTR_AWMISC_INFO_47_32,MSTR_AWMISC_INFO_47_32" rgroup.long 0x264++0xB line.long 0x0 "STS_25,STS_25" bitfld.long 0x0 30.--31. "CFG_MEM_SPACE_EN,CFG_MEM_SPACE_EN" "0,1,2,3" newline hexmask.long.byte 0x0 24.--29. 1. "CFG_MAX_RD_REQ_SIZE,CFG_MAX_RD_REQ_SIZE" newline bitfld.long 0x0 22.--23. "CFG_BUS_MASTER_EN,CFG_BUS_MASTER_EN" "0,1,2,3" newline bitfld.long 0x0 21. "CFG_DISABLE_LTR_CLR_MSG,CFG_DISABLE_LTR_CLR_MSG" "0,1" newline bitfld.long 0x0 20. "CFG_LTR_M_EN,CFG_LTR_M_EN" "0,1" newline hexmask.long.byte 0x0 16.--19. 1. "CFG_ATTEN_IND,CFG_ATTEN_IND" newline hexmask.long.byte 0x0 12.--15. 1. "CFG_PWR_IND,CFG_PWR_IND" newline bitfld.long 0x0 10.--11. "CFG_PF_PASID_PRIV_MODE_EN,CFG_PF_PASID_PRIV_MODE_EN" "0,1,2,3" newline bitfld.long 0x0 8.--9. "CFG_PF_PASID_EXECUTE_PERM_EN,CFG_PF_PASID_EXECUTE_PERM_EN" "0,1,2,3" newline bitfld.long 0x0 6.--7. "CFG_PF_PASID_EN,CFG_PF_PASID_EN" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "CFG_START_VFI,CFG_START_VFI" line.long 0x4 "STS_26,STS_26" hexmask.long.word 0x4 16.--31. 1. "CFG_SUBBUS_NUM,CFG_SUBBUS_NUM" newline hexmask.long.word 0x4 0.--15. 1. "CFG_2NDBUS_NUM,CFG_2NDBUS_NUM" line.long 0x8 "STS_27,STS_27" hexmask.long.byte 0x8 24.--31. 1. "PM_VF_PME_EN,PM_VF_PME_EN" newline hexmask.long.tbyte 0x8 0.--23. 1. "PM_VF_DSTATE,PM_VF_DSTATE" tree.end elif (CORENAME()=="CORTEXA55") tree "PCIE2_PF0" base ad:0x31100000 tree "PF0_TYPE1_HDR (PCI-Compatible Configuration Space Header Type1)" group.long 0x0++0x2F line.long 0x0 "TYPE1_DEV_ID_VEND_ID_REG,Device ID and Vendor ID Register." hexmask.long.word 0x0 16.--31. 1. "DEVICE_ID,Device ID. The Device ID register identifies the particular Function. This identifier is allocated by the vendor. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else.." newline hexmask.long.word 0x0 0.--15. 1. "VENDOR_ID,Vendor ID. The Vendor ID register identifies the manufacturer of the Function. Valid vendor identifiers are allocated by the PCI-SIG to ensure uniqueness. It is not permitted to populate this register with a value of FFFFh which is an invalid.." line.long 0x4 "TYPE1_STATUS_COMMAND_REG,Status and Command Register." bitfld.long 0x4 31. "DETECTED_PARITY_ERROR,Detected Parity Error. This bit is set by a Function whenever it receives a Poisoned TLP regardless of the state the Parity Error Response bit in the Command register. The bit is set when the Poisoned TLP is received by a.." "0,1" newline bitfld.long 0x4 30. "SIGNALED_SYS_ERROR,Signaled System Error. This bit is set when a Function sends an ERR_FATAL or ERR_NONFATAL Message and the SERR# Enable bit in the Command register is 1b." "0,1" newline bitfld.long 0x4 29. "RCVD_MASTER_ABORT,Received Master Abort. This bit is set when a Requester receives a Completion with Unsupported Request Completion status. The bit is set when the Unsupported Request is received by a Function's primary side." "0,1" newline bitfld.long 0x4 28. "RCVD_TARGET_ABORT,Received Target Abort. This bit is set when a Requester receives a Completion with Completer Abort Completion status. The bit is set when the Completer Abort is received by a Function's primary side." "0,1" newline bitfld.long 0x4 27. "SIGNALED_TARGET_ABORT,Signaled Target Abort. This bit is set when a Function completes a Posted or Non-Posted Request as a Completer Abort error. This applies to a Function when the Completer Abort was generated by its primary side." "0,1" newline rbitfld.long 0x4 25.--26. "DEV_SEL_TIMING,DEVSEL Timing. This field was originally described in the PCI Local Bus Specification. Its functionality does not apply to PCI Express. The controller hardwires it to 00b." "0,1,2,3" newline bitfld.long 0x4 24. "MASTER_DPE,Master Data Parity Error. This bit is set by a Function if the Parity Error Response bit in the Command register is 1b and either of the following two conditions occurs: - Port receives a Poisoned Completion going downstream - Port transmits a.." "0,1" newline rbitfld.long 0x4 23. "FAST_B2B_CAP,Fast Back-to-Back Transactions Capable. This bit was originally described in the PCI Local Bus Specification. Its functionality does not apply to PCI Express. The controller hardwires this bit to 0b." "0,1" newline rbitfld.long 0x4 22. "RSVDP_22,Reserved for future use." "0,1" newline rbitfld.long 0x4 21. "FAST_66MHZ_CAP,66 MHz Capable. This bit was originally described in the PCI Local Bus Specification. Its functionality does not apply to PCI Express. The controller hardwires this bit to 0b." "0,1" newline rbitfld.long 0x4 20. "CAP_LIST,Capabilities List. Indicates the presence of an Extended Capability list item. Since all PCI Express device Functions are required to implement the PCI Express Capability structure the controller hardwires this bit to 1b." "0,1" newline rbitfld.long 0x4 19. "INT_STATUS,Interrupt Status. When set indicates that an INTx emulation interrupt is pending internally in the Function. INTx emulation interrupts forwarded by Functions from the secondary side are not reflected in this bit. Setting the Interrupt Disable.." "0,1" newline rbitfld.long 0x4 17.--18. "RSVDP_17,Reserved for future use." "0,1,2,3" newline bitfld.long 0x4 16. "IMM_READINESS,Immediate Readiness. This optional bit when set indicates the Function is guaranteed to be ready to successfully complete valid configuration accesses at any time following any reset that the host is capable of issuing Configuration.." "0,1" newline hexmask.long.byte 0x4 11.--15. 1. "RESERV,Reserved." newline bitfld.long 0x4 10. "INT_EN,Interrupt Disable. Controls the ability of a Function to generate INTx emulation interrupts. When set Functions are prevented from asserting INTx interrupts. Note: - Any INTx emulation interrupts already asserted by the Function must be.." "0,1" newline rbitfld.long 0x4 9. "RSVDP_9,Reserved for future use." "0,1" newline bitfld.long 0x4 8. "SERREN,SERR# Enable. When set this bit enables reporting upstream of Non-fatal and Fatal errors detected by the Function. Note: The errors are reported if enabled either through this bit or through the PCI Express specific bits in the Device Control.." "0,1" newline rbitfld.long 0x4 7. "IDSEL,IDSEL Stepping/Wait Cycle Control. This bit was originally described in the PCI Local Bus Specification. Its functionality does not apply to PCI Express. The controller hardwires this bit to 0b." "0,1" newline bitfld.long 0x4 6. "PERREN,Parity Error Response. This bit controls the logging of poisoned TLPs in the Master Data Parity Error bit in the Status register. For more details see the 'Error Registers' section of the PCI Express Base Specification." "0,1" newline rbitfld.long 0x4 5. "VGAPS,VGA Palette Snoop. This bit was originally described in the PCI Local Bus Specification and the PCI-to-PCI Bridge Architecture Specification. Its functionality does not apply to PCI Express. The controller hardwires this bit to 0b." "0,1" newline rbitfld.long 0x4 4. "MWI_EN,Memory Write and Invalidate. This bit was originally described in the PCI Local Bus Specification and the PCI-to-PCI Bridge Architecture Specification. Its functionality does not apply to PCI Express. The controller hardwires this bit to 0b. For.." "0,1" newline rbitfld.long 0x4 3. "SCO,Special Cycle Enable. This bit was originally described in the PCI Local Bus Specification. Its functionality does not apply to PCI Express. The controller hardwires this bit to 0b." "0,1" newline bitfld.long 0x4 2. "BME,Bus Master Enable. This bit controls forwarding of Memory or I/O requests by a port in the Upstream direction. When this bit is 0b Memory and I/O Requests received at a Root Port must be handled as Unsupported Requests (UR) For Non-Posted Requests a.." "0,1" newline bitfld.long 0x4 1. "MSE,Memory Space Enable. This bit controls a Function's response to Memory Space accesses received on its primary side. - When set the Function is enabled to decode the address and further process Memory Space accesses. - When clear all received Memory.." "0,1" newline bitfld.long 0x4 0. "IO_EN,IO Space Enable. This bit controls a Function's response to I/O Space accesses received on its primary side. - When set the Function is enabled to decode the address and further process I/O Space accesses. - When clear all received I/O accesses.." "0,1" line.long 0x8 "TYPE1_CLASS_CODE_REV_ID_REG,Class Code and Revision ID Register." hexmask.long.byte 0x8 24.--31. 1. "BASE_CLASS_CODE,Base Class Code. A code that broadly classifies the type of operation the Function performs. Encodings for base class are provided in the PCI Code and ID Assignment Specification. All unspecified encodings are reserved. Note: The access.." newline hexmask.long.byte 0x8 16.--23. 1. "SUBCLASS_CODE,Sub-Class Code. Specifies a base class sub-class which identifies more specifically the operation of the Function. Encodings for sub-class are provided in the PCI Code and ID Assignment Specification. All unspecified encodings are.." newline hexmask.long.byte 0x8 8.--15. 1. "PROGRAM_INTERFACE,Programming Interface. This field identifies a specific register level programming interface (if any) so that device independent software can interact with the Function. Encodings for interface are provided in the PCI Code and ID.." newline hexmask.long.byte 0x8 0.--7. 1. "REVISION_ID,Revision ID. The value of this field specifies a Function specific revision identifier. The value is chosen by the vendor. Zero is an acceptable value. The Revision ID should be viewed as a vendor defined extension to the Device ID. Note: The.." line.long 0xC "TYPE1_BIST_HDR_TYPE_LAT_CACHE_LINE_SIZE_REG,BIST. Header Type. Latency Timer. and Cache Line Size Register." hexmask.long.byte 0xC 24.--31. 1. "BIST,BIST. This register is used for control and status of BIST. Functions that do not support BIST must hardwire the register to 00h. A Function whose BIST is invoked must not prevent normal operation of the PCI Express Link. Bit descriptions: - [31]:.." newline rbitfld.long 0xC 23. "MULTI_FUNC,Multi-Function Device. - When set indicates that the device may contain multiple Functions but not necessarily. Software is permitted to probe for Functions other than Function 0. - When clear software must not probe for Functions other.." "0,1" newline hexmask.long.byte 0xC 16.--22. 1. "HEADER_TYPE,Header Layout. This field identifies the layout of the second part of the predefined header. The controller uses 000 0001b encoding. The encoding 000 0010b is reserved. This encoding was originally described in the PC Card Standard Electrical.." newline hexmask.long.byte 0xC 8.--15. 1. "LATENCY_MASTER_TIMER,Latency Timer. This register is also referred to as Primary Latency Timer. The Latency Timer was originally described in the PCI Local Bus Specification and the PCI-to-PCI Bridge Architecture Specification. Its functionality does not.." newline hexmask.long.byte 0xC 0.--7. 1. "CACHE_LINE_SIZE,Cache Line Size. The Cache Line Size register is programmed by the system firmware or the operating system to system cache line size. However legacy conventional PCI software may not always be able to program this register correctly.." line.long 0x10 "BAR0_REG,BAR0 Register. System software must build a consistent address map before booting the machine to an operating system. This means it has to determine how much memory is in the system. and how much address space the Functions in the system.." hexmask.long 0x10 4.--31. 1. "BAR0_START,BAR0 Base Address. - Memory Space: Base Address. - IO Space: bits[31:2] are used to map the function into IO space/Base. Address. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R(Sticky)/W(Sticky) if.." newline bitfld.long 0x10 3. "BAR0_PREFETCH,BAR0 Prefetchable. - Memory Space: Set to one if data is pre-fetchable. A Function is permitted to mark a range as prefetchable. If there are no side effects on reads the function returns all bytes on reads regardless of the byte enables.." "0,1" newline bitfld.long 0x10 1.--2. "BAR0_TYPE,BAR0 Type. - Memory Space: Base Address registers that map into Memory Space can be 32 bits or 64 bits wide (to support mapping into a 64-bit address space). The bit encoding is as follows: -- 00: Base register is 32 bits wide and can be mapped.." "Base register is 32 bits wide and can be mapped..,Reserved,?,?" newline bitfld.long 0x10 0. "BAR0_MEM_IO,BAR0 Memory Space Indicator. This bit is used to determine whether the register maps into Memory or I/O Space. Base Address registers that map to Memory Space must return a 0b. Base Address registers that map to I/O Space must return a 1b." "0,1" line.long 0x14 "BAR1_REG,BAR1 Register. System software must build a consistent address map before booting the machine to an operating system. This means it has to determine how much memory is in the system. and how much address space the Functions in the system.." hexmask.long 0x14 4.--31. 1. "BAR1_START,BAR1 Base Address. - Memory Space: Base Address. - IO Space: bits[31:2] are used to map the function into IO space/Base. Address. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R(Sticky)/W(Sticky) if.." newline bitfld.long 0x14 3. "BAR1_PREFETCH,BAR1 Prefetchable. - Memory Space: Set to one if data is pre-fetchable. A Function is permitted to mark a range as prefetchable. If there are no side effects on reads the function returns all bytes on reads regardless of the byte enables.." "0,1" newline bitfld.long 0x14 1.--2. "BAR1_TYPE,BAR1 Type. - Memory Space: Base Address registers that map into Memory Space can be 32 bits or 64 bits wide (to support mapping into a 64-bit address space). The bit encoding is as follows: -- 00: Base register is 32 bits wide and can be mapped.." "Base register is 32 bits wide and can be mapped..,Reserved,?,?" newline bitfld.long 0x14 0. "BAR1_MEM_IO,BAR1 Memory Space Indicator. This bit is used to determine whether the register maps into Memory or I/O Space. Base Address registers that map to Memory Space must return a 0b. Base Address registers that map to I/O Space must return a 1b." "0,1" line.long 0x18 "SEC_LAT_TIMER_SUB_BUS_SEC_BUS_PRI_BUS_REG,Secondary Latency Timer. Subordinate Bus Number. Secondary Bus Number. and Primary Bus Number Register." hexmask.long.byte 0x18 24.--31. 1. "SEC_LAT_TIMER,Secondary Latency Timer. This register does not apply to PCI Express. The controller hardwires it to 00h." newline hexmask.long.byte 0x18 16.--23. 1. "SUB_BUS,Subordinate Bus Number. The Subordinate Bus Number register is used to record the bus number of the highest numbered PCI bus segment which is behind (or subordinate to) the bridge. Configuration software programs the value in this register. The.." newline hexmask.long.byte 0x18 8.--15. 1. "SEC_BUS,Secondary Bus Number. The Secondary Bus Number register is used to record the bus number of the PCI bus segment to which the secondary interface of the bridge is connected. Configuration software programs the value in this register. The bridge.." newline hexmask.long.byte 0x18 0.--7. 1. "PRIM_BUS,Primary Bus Number. This register is not used by PCI Express Functions. It is implemented for compatibility with legacy software." line.long 0x1C "SEC_STAT_IO_LIMIT_IO_BASE_REG,Secondary Status. and I/O Limit and Base Register. The I/O Limit and I/O Base registers are optional and define an address range that is used by the bridge to determine when to forward I/O transactions from one interface to.." bitfld.long 0x1C 31. "SEC_STAT_DPE,Detected Parity Error. This bit is set by a Function when a Poisoned TLP is received by its secondary side regardless of the state the Parity Error Response Enable bit in the Bridge Control register." "0,1" newline bitfld.long 0x1C 30. "SEC_STAT_RCVD_SYS_ERR,Received System Error. This bit is set when the secondary side of a Function receives an ERR_FATAL or ERR_NONFATAL message." "0,1" newline bitfld.long 0x1C 29. "SEC_STAT_RCVD_MSTR_ABRT,Received Master Abort. This bit is set when the secondary side of a Function (for requests initiated by the Type 1 header Function itself) receives a Completion with Unsupported Request Completion status." "0,1" newline bitfld.long 0x1C 28. "SEC_STAT_RCVD_TRGT_ABRT,Received Target Abort. This bit is set when the secondary side of a Function (for requests initiated by the Type 1 header Function itself) receives a Completion with Completer Abort Completion status." "0,1" newline bitfld.long 0x1C 27. "SEC_STAT_SIG_TRGT_ABRT,Signaled Target Abort. This bit is set when the secondary side of the Function (for Requests completed by the Type 1 header Function itself) completes a Posted or Non-Posted request as a Completer Abort error." "0,1" newline rbitfld.long 0x1C 25.--26. "RSVDP_25,Reserved for future use." "0,1,2,3" newline bitfld.long 0x1C 24. "SEC_STAT_MDPE,Master Data Parity Error. This bit is set by a Function if the Parity Error Response Enable bit in the Bridge Control register is set and either of the following two conditions occurs: - Port receives a Poisoned Completion coming Upstream.." "0,1" newline rbitfld.long 0x1C 23. "RSVDP_23,Reserved for future use." "0,1" newline hexmask.long.byte 0x1C 16.--22. 1. "SEC_STAT_RESERV,Reserved." newline hexmask.long.byte 0x1C 12.--15. 1. "IO_LIMIT,I/O Limit Address. These bits correspond to the address[15:12] of IO address range. For the purpose of address decoding the bridge assumes that the lower 12 address bits address[11:0] of the I/O limit address (not implemented in the I/O Limit.." newline rbitfld.long 0x1C 9.--11. "IO_RESERV1,Reserved." "0,1,2,3,4,5,6,7" newline bitfld.long 0x1C 8. "IO_DECODE_BIT8,I/O Addressing Encode (IO Limit Address). This bit encodes the IO addressing capability of the bridge. IO_DECODE_BIT8 indicates the following: - 0h: The bridge supports only 16-bit I/O addressing (for ISA compatibility). For the purpose of.." "0,1" newline hexmask.long.byte 0x1C 4.--7. 1. "IO_BASE,I/O Base Address. These bits correspond to the address[15:12] of IO address range. For the purpose of address decoding the bridge assumes that the lower 12 address bits address[11:0] of the I/O base address (not implemented in the I/O Base.." newline rbitfld.long 0x1C 1.--3. "IO_RESERV,Reserved." "0,1,2,3,4,5,6,7" newline bitfld.long 0x1C 0. "IO_DECODE,I/O Addressing Encode (IO Base Address) This bit encodes the IO addressing capability of the bridge. IO_DECODE indicates the following: - 0h: The bridge supports only 16-bit I/O addressing (for ISA compatibility). For the purpose of address.." "0,1" line.long 0x20 "MEM_LIMIT_MEM_BASE_REG,Memory Limit and Base Register. The Memory Limit and Memory Base registers define a memory mapped address range which is used by the bridge to determine when to forward memory transactions from one interface to the other. If there.." hexmask.long.word 0x20 20.--31. 1. "MEM_LIMIT,Memory Limit Address. These bits correspond to the upper 12 address bits Address[31:20] of 32-bit addresses. For the purpose of address decoding the bridge assumes that the lower 20 address bits Address[19:0] of the memory limit address.." newline hexmask.long.byte 0x20 16.--19. 1. "MEM_LIMIT_RESERV,Reserved." newline hexmask.long.word 0x20 4.--15. 1. "MEM_BASE,Memory Base Address. These bits correspond to the upper 12 address bits Address[31:20] of 32-bit addresses. For the purpose of address decoding the bridge assumes that the lower 20 address bits Address[19:0] of the memory base address (not.." newline hexmask.long.byte 0x20 0.--3. 1. "MEM_BASE_RESERV,Reserved." line.long 0x24 "PREF_MEM_LIMIT_PREF_MEM_BASE_REG,Prefetchable Memory Limit and Base Register. The Prefetchable Memory Limit and Prefetchable Memory Base registers must indicate that 64-bit addresses are supported. as defined in PCI-to-PCI Bridge Architecture.." hexmask.long.word 0x24 20.--31. 1. "PREF_MEM_LIMIT,Prefetchable Memory Limit Address. If the Prefetchable Memory Limit register indicates support for 32-bit addressing then the Prefetchable Limit Upper 32 Bits register is implemented as a read-only register that returns zero when read. If.." newline rbitfld.long 0x24 17.--19. "PREF_RESERV1,Reserved." "0,1,2,3,4,5,6,7" newline rbitfld.long 0x24 16. "PREF_MEM_LIMIT_DECODE,Prefetchable Memory Limit Decode. This bit encodes whether or not the bridge supports 64-bit addresses. Note: This bit is a copy of the PREF_MEM_DECODE bit and always reflects the current value of that bit. The value of.." "0,1" newline hexmask.long.word 0x24 4.--15. 1. "PREF_MEM_BASE,Prefetchable Memory Base Address. If the Prefetchable Memory Base register indicates support for 32-bit addressing then the Prefetchable Base Upper 32 Bits register is implemented as a read-only register that returns zero when read. If the.." newline rbitfld.long 0x24 1.--3. "PREF_RESERV,Reserved." "0,1,2,3,4,5,6,7" newline bitfld.long 0x24 0. "PREF_MEM_DECODE,Prefetchable Memory Base Decode. This bit encodes whether or not the bridge supports 64-bit addresses. Note: By default the bit is set to 1'b1 indicating that 64-bit addresses are supported. If the bridge only supports 32-bit prefetchable.." "0,1" line.long 0x28 "PREF_BASE_UPPER_REG,Prefetchable Base Upper 32 Bits Register. The Prefetchable Base Upper 32 Bits register is an optional extension to the Prefetchable Memory Base register." hexmask.long 0x28 0.--31. 1. "PREF_MEM_BASE_UPPER,Prefetchable Base Upper 32 Bit. If the Prefetchable Memory Base register indicates support for 32-bit addressing then this register is implemented as read-only register that returns zero when read. If the Prefetchable Memory Base.." line.long 0x2C "PREF_LIMIT_UPPER_REG,Prefetchable Limit Upper 32 Bits Register. The Prefetchable Limit Upper 32 Bits register is an optional extension to the Prefetchable Memory Limit register." hexmask.long 0x2C 0.--31. 1. "PREF_MEM_LIMIT_UPPER,Prefetchable Limit Upper 32 Bit. If the Prefetchable Memory Limit register indicate support for 64-bit addressing then this register is implemented as read/write register which must be initialized by configuration software. This.." rgroup.long 0x30++0x3 line.long 0x0 "IO_LIMIT_UPPER_IO_BASE_UPPER_REG,I/O Limit and Base Upper 16 Bits Register. The I/O Limit Upper 16 Bits and I/O Base Upper 16 Bits registers are optional extensions to the I/O Limit and I/O Base registers." hexmask.long.word 0x0 16.--31. 1. "IO_LIMIT_UPPER,I/O Limit Upper 16 Bits. If the I/O Limit register indicates support for 16-bit I/O address decoding then this register is implemented as a read-only register which return zero when read. If the I/O Limit register indicates support for.." newline hexmask.long.word 0x0 0.--15. 1. "IO_BASE_UPPER,I/O Base Upper 16 Bits. If the I/O Base register indicates support for 16-bit I/O address decoding then this register is implemented as a read-only register which return zero when read. If the I/O base register indicates support for 32-bit.." group.long 0x34++0xB line.long 0x0 "TYPE1_CAP_PTR_REG,Capabilities Pointer Register." hexmask.long.tbyte 0x0 8.--31. 1. "RSVDP_8,Reserved for future use." newline hexmask.long.byte 0x0 0.--7. 1. "CAP_POINTER,Capabilities Pointer. This register is used to point to a linked list of capabilities implemented by this Function. Since all PCI Express Functions are required to implement the PCI Express Capability structure this register must point to a.." line.long 0x4 "TYPE1_EXP_ROM_BASE_REG,Expansion ROM Base Address Register. This register is defined to handle the base address and size information for this expansion ROM. The mask for this ROM BAR exists (if implemented) as a shadow register at this address. The.." hexmask.long.tbyte 0x4 11.--31. 1. "EXP_ROM_BASE_ADDRESS,Expansion ROM Base Address. Upper 21 bits of the Expansion ROM base address. The number of bits (out of these 21) that a Function actually implements depends on how much address space the Function requires. The mask for this ROM BAR.." newline hexmask.long.word 0x4 1.--10. 1. "RSVDP_1,Reserved for future use." newline bitfld.long 0x4 0. "ROM_BAR_ENABLE,Expansion ROM Enable. This bit controls whether or not the Function accepts accesses to its expansion ROM. When this bit is 0b the Function's expansion ROM address space is disabled. When the bit is 1b address decoding is enabled using.." "0,1" line.long 0x8 "BRIDGE_CTRL_INT_PIN_INT_LINE_REG,Bridge Control. Interrupt Pin. and Interrupt Line Register." hexmask.long.word 0x8 23.--31. 1. "BRIDGE_CTRL_RESERV,Reserved." newline bitfld.long 0x8 22. "SBR,Secondary Bus Reset. Setting this bit triggers a hot reset on the corresponding PCI Express Port. Software must ensure a minimum reset duration (Trst) as defined in the PCI Local Bus Specification. Software and systems must honor.." "0,1" newline rbitfld.long 0x8 21. "MSTR_ABORT_MODE,Master Abort Mode. This bit was originally described in the PCI-to-PCI Bridge Architecture Specification. Its functionality does not apply to PCI Express. The controller hardwires this bit to 0b. Note: The access attributes of this field.." "0,1" newline rbitfld.long 0x8 20. "VGA_16B_DEC,VGA 16 bit decode. This bit only has meaning if VGA Enable bit is set. This bit enables system configuration software to select between 10-bit and 16-bit I/O address decoding for all VGA I/O register accesses that are forwarded from primary.." "0,1" newline rbitfld.long 0x8 19. "VGA_EN,VGA Enable. Modifies the response by the bridge to VGA compatible addresses. If the VGA Enable bit is set the bridge will positively decode and forward the following accesses on the primary interface to the secondary interface (and conversely.." "0,1" newline bitfld.long 0x8 18. "ISA_EN,ISA Enable. Modifies the response by the bridge to ISA I/O addresses. This applies only to I/O addresses that are enabled by the I/O Base and I/O Limit registers and are in the first 64 KB of I/O address space (0000 0000h to 0000 FFFFh). If this.." "?,KB block" newline bitfld.long 0x8 17. "SERR_EN,SERR# Enable. This bit controls forwarding of ERR_COR ERR_NONFATAL and ERR_FATAL from secondary to primary." "0,1" newline bitfld.long 0x8 16. "PERE,Parity Error Response Enable. This bit controls the logging of poisoned TLPs in the Master Data Parity Error bit in the Secondary Status register." "0,1" newline hexmask.long.byte 0x8 8.--15. 1. "INT_PIN,Interrupt PIN. The Interrupt Pin register register that identifies the legacy interrupt Message(s) the Function uses. Valid values are: - 01h 02h 03h and 04h: map to legacy interrupt Messages for INTA INTB INTC and INTD respectively. - 00h:.." newline hexmask.long.byte 0x8 0.--7. 1. "INT_LINE,Interrupt Line. The Interrupt Line register communicates interrupt line routing information. The register must be implemented by any Function that uses an interrupt pin. Values in this register are programmed by system software and are system.." tree.end tree "PF0_SPCIE_CAP (Secondary PCI Express Capability Structure)" group.long (0x0+0x1A0)++0xF line.long 0x0 "SPCIE_CAP_HEADER_REG,SPCIE Capability Header. For a description of this standard PCIe register. see the PCI Express Specification." hexmask.long.word 0x0 20.--31. 1. "NEXT_OFFSET,Next Capability Offset. For a description of this standard PCIe register field see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky).." hexmask.long.byte 0x0 16.--19. 1. "CAP_VERSION,Capability Version. For a description of this standard PCIe register field see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else.." hexmask.long.word 0x0 0.--15. 1. "EXTENDED_CAP_ID,Secondary PCI Express Extended Capability ID. For a description of this standard PCIe register field see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN.." line.long 0x4 "LINK_CONTROL3_REG,Link Control 3 Register. For a description of this standard PCIe register. see the PCI Express Specification." hexmask.long 0x4 2.--31. 1. "RSVDP_2,Reserved for future use." bitfld.long 0x4 1. "EQ_REQ_INT_EN,Link Equalization Request Interrupt Enable. For a description of this standard PCIe register field see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" "0,1" bitfld.long 0x4 0. "PERFORM_EQ,Perform Equalization. For a description of this standard PCIe register field see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" "0,1" line.long 0x8 "LANE_ERR_STATUS_REG,Lane Error Status Register. For a description of this standard PCIe register. see the PCI Express Specification." hexmask.long 0x8 1.--31. 1. "RSVDP_LANE_ERR_STATUS,Reserved for future use." bitfld.long 0x8 0. "LANE_ERR_STATUS,Lane Error Status Bits per Lane. For a description of this standard PCIe register field see the PCI Express Specification." "0,1" line.long 0xC "SPCIE_CAP_OFF_0CH_REG,Lane Equalization Control Register for lanes 1 and 0. For a description of this standard PCIe register. see the PCI Express Specification." rbitfld.long 0xC 31. "RSVDP_31,Reserved for future use." "0,1" rbitfld.long 0xC 23. "RSVDP_23,Reserved for future use." "0,1" rbitfld.long 0xC 15. "RSVDP_15,Reserved for future use." "0,1" bitfld.long 0xC 12.--14. "USP_RX_PRESET_HINT0,Upstream Port 8.0 GT/s Receiver Preset Hint 0. The write value is gated with the PCIE_CAP_CROSS_LINK_SUPPORT field of LINK_CAPABILITIES2_REG. For a description of this standard PCIe register field see the PCI Express Specification." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0xC 8.--11. 1. "USP_TX_PRESET0,Upstream Port 8.0 GT/s Transmitter Preset 0. The write value is gated with the PCIE_CAP_CROSS_LINK_SUPPORT field of LINK_CAPABILITIES2_REG. For a description of this standard PCIe register field see the PCI Express Specification. Note:.." rbitfld.long 0xC 7. "RSVDP_7,Reserved for future use." "0,1" bitfld.long 0xC 4.--6. "DSP_RX_PRESET_HINT0,Downstream Port 8.0 GT/s Receiver Preset Hint 0. For a description of this standard PCIe register field see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if.." "0,1,2,3,4,5,6,7" hexmask.long.byte 0xC 0.--3. 1. "DSP_TX_PRESET0,Downstream Port 8.0 GT/s Transmitter Preset 0. For a description of this standard PCIe register field see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN.." tree.end tree "PF0_L1SUB_CAP (L1 Substates Capability Structure)" group.long (0x0+0x2A0)++0xF line.long 0x0 "L1SUB_CAP_HEADER_REG,L1 Substates Extended Capability Header. This register provides capbility ID. capability version and next offset value for L1 Substates." hexmask.long.word 0x0 20.--31. 1. "NEXT_OFFSET,Next Capability Offset. This field contains the offset to the next PCI Express Capability structure or 000h if no other items exist in the linked list of Capabilities. For Extended Capabilities implemented in Configuration Space this offset.." hexmask.long.byte 0x0 16.--19. 1. "CAP_VERSION,Capability Version. This field is a PCI-SIG defined version number that indicates the version of the Capability structure present. This field is depends on version of the specification. Note: The access attributes of this field are as.." hexmask.long.word 0x0 0.--15. 1. "EXTENDED_CAP_ID,L1SUB Extended Capability ID. This field is a PCI-SIG defined ID number that indicates the nature and format of the Extended Capability. Extended Capability ID for L1 PM Substates is 001Eh. Note: The access attributes of this field are as.." line.long 0x4 "L1SUB_CAPABILITY_REG,L1 Substates Capability Register. This register provides extended capability of L1 Substates." hexmask.long.byte 0x4 24.--31. 1. "RSVDP_24,Reserved for future use." hexmask.long.byte 0x4 19.--23. 1. "PWR_ON_VALUE_SUPPORT,Port T Power On Value. Along with the Port T_POWER_ON Scale field in the L1 PM Substates Capabilities register sets the time (in us) that this Port requires the port on the opposite side of Link to wait in L1.2.Exit after sampling.." rbitfld.long 0x4 18. "RSVDP_18,Reserved for future use." "0,1" bitfld.long 0x4 16.--17. "PWR_ON_SCALE_SUPPORT,Port T Power On Scale. Specifies the scale used for the Port T_POWER_ON Value field in the L1 PM Substates Capabilities register. Range of values are given below. Required for all Ports for which either the PCI-PM L1.2 Supported bit.." "?,?,?,Reserved" newline hexmask.long.byte 0x4 8.--15. 1. "COMM_MODE_SUPPORT,Port Common Mode Restore Time. Time (in us) required for this Port to re-establish common mode. Required for all Ports for which either the PCI-PM L1.2 Supported bit is Set ASPM L1.2 Supported bit is Set or both are Set otherwise.." rbitfld.long 0x4 5.--7. "RSVDP_5,Reserved for future use." "0,1,2,3,4,5,6,7" bitfld.long 0x4 4. "L1_PMSUB_SUPPORT,L1 PM Substates ECN Supported. When Set this bit indicates that this Port supports L1 PM Substates. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W (sticky)" "0,1" bitfld.long 0x4 3. "L1_1_ASPM_SUPPORT,ASPM L11 Supported. When Set this bit indicates that ASPM L1.1 is supported. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W (sticky)" "0,1" newline bitfld.long 0x4 2. "L1_2_ASPM_SUPPORT,ASPM L12 Supported. When Set this bit indicates that ASPM L1.2 is supported. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W (sticky)" "0,1" bitfld.long 0x4 1. "L1_1_PCIPM_SUPPORT,PCI-PM L11 Supported. When Set this bit indicates that PCI-PM L1.1 is supported and must be Set by all Ports implementing L1 PM Substates. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W (sticky)" "0,1" bitfld.long 0x4 0. "L1_2_PCIPM_SUPPORT,PCI-PM L12 Supported. When Set this bit indicates that PCI-PM L1.2 is supported. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W (sticky)" "0,1" line.long 0x8 "L1SUB_CONTROL1_REG,L1 Substates Control 1 Register. This register provides Controls to extended capability." bitfld.long 0x8 29.--31. "L1_2_TH_SCA,LTR L12 Threshold Scale. This field provides a scale for the value contained within the LTR_L1.2_THRESHOLD_Value.The default value for this field is 000b.Hardware operation is undefined if software writes a Not-Permitted value to this field." "0,1,2,3,4,5,6,7" rbitfld.long 0x8 26.--28. "RSVDP_26,Reserved for future use." "0,1,2,3,4,5,6,7" hexmask.long.word 0x8 16.--25. 1. "L1_2_TH_VAL,LTR L12 Threshold Value. Along with the LTR_L1.2_THRESHOLD_Scale this field indicates the LTR threshold used to determine if entry into L1 results in L1.1 (if enabled) or L1.2 (if enabled). The default value for this field is 00 0000 0000b." hexmask.long.byte 0x8 8.--15. 1. "T_COMMON_MODE,Common Mode Restore Time. Sets value of TCOMMONMODE (in us) which must be used by the Downstream Ports for timing the re-establishment of common mode.This field is of type RsvdP for Upstream Ports. Default value is implementation.." newline hexmask.long.byte 0x8 4.--7. 1. "RSVDP_4,Reserved for future use." bitfld.long 0x8 3. "L1_1_ASPM_EN,ASPM L11 Enable. When Set this bit enables ASPM L1.1.For Ports for which the ASPM L1.1 Supported bit is Clear this bit is permitted to be hardwired to 0.Default value is 0b." "0,1" bitfld.long 0x8 2. "L1_2_ASPM_EN,ASPM L12 Enable. When Set this bit enables ASPM L1.2.For Ports for which the ASPM L1.2 Supported bit is Clear this bit is permitted to be hardwired to 0.Default value is 0b." "0,1" bitfld.long 0x8 1. "L1_1_PCIPM_EN,PCI-PM L11 Enable. When Set this bit enables PCI-PM L1.1. Default value is 0b." "0,1" newline bitfld.long 0x8 0. "L1_2_PCIPM_EN,PCI-PM L12 Enable. When Set this bit enables PCI-PM L1.2.For Ports for which the PCI-PM L1.2 Supported bit is Clear this bit is permitted to be hardwired to 0.Default value is 0b." "0,1" line.long 0xC "L1SUB_CONTROL2_REG,L1 Substates Control 2 Register. This register provides Controls to extended capability." hexmask.long.tbyte 0xC 8.--31. 1. "RSVDP_8,Reserved for future use." hexmask.long.byte 0xC 3.--7. 1. "T_POWER_ON_VALUE,T Power On Value. Along with the T_POWER_ON Scale sets the minimum amount of time (in us) that the Port must wait in L1.2.Exit after sampling CLKREQ# asserted before actively driving the interface.Default value is 00101b. T_POWER_ON is.." rbitfld.long 0xC 2. "RSVDP_2,Reserved for future use." "0,1" bitfld.long 0xC 0.--1. "T_POWER_ON_SCALE,T Power On Scale. Specifies the scale used for T_POWER_ON Value. Range of values are given below. Required for all Ports that support L1.2 otherwise this field is of type RsvdP. This field must only be modified when the ASPM L1.2 Enable.." "?,?,?,Reserved" tree.end tree "PF0_RAS_DES_CAP (RAS D.E.S. Capability Structure (VSEC))" group.long (0x0+0x30C)++0x3 line.long 0x0 "RAS_DES_CAP_HEADER_REG,Vendor-Specific Extended Capability Header. For a description of this standard PCIe register. see the PCI Express Specification." hexmask.long.word 0x0 20.--31. 1. "NEXT_OFFSET,Next Capability Offset. For a description of this standard PCIe register field see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky).." newline hexmask.long.byte 0x0 16.--19. 1. "CAP_VERSION,Capability Version. For a description of this standard PCIe register field see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else.." newline hexmask.long.word 0x0 0.--15. 1. "EXTENDED_CAP_ID,PCI Express Extended Capability ID. For a description of this standard PCIe register field see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then.." rgroup.long (0x4+0x30C)++0x3 line.long 0x0 "VENDOR_SPECIFIC_HEADER_REG,Vendor-Specific Header. For a description of this standard PCIe register. see the PCI Express Specification." hexmask.long.word 0x0 20.--31. 1. "VSEC_LENGTH,VSEC Length. For a description of this standard PCIe register field see the PCI Express Specification." newline hexmask.long.byte 0x0 16.--19. 1. "VSEC_REV,VSEC Rev. For a description of this standard PCIe register field see the PCI Express Specification." newline hexmask.long.word 0x0 0.--15. 1. "VSEC_ID,VSEC ID. For a description of this standard PCIe register field see the PCI Express Specification." group.long (0x8+0x30C)++0x3 line.long 0x0 "EVENT_COUNTER_CONTROL_REG,Event Counter Control. This is a viewport control register. - Setting the EVENT_COUNTER_EVENT_SELECT and EVENT_COUNTER_LANE_SELECT fields in this register determine the Event Counter data returned by the EVENT_COUNTER_DATA_REG.." hexmask.long.byte 0x0 28.--31. 1. "RSVDP_28,Reserved for future use." newline hexmask.long.word 0x0 16.--27. 1. "EVENT_COUNTER_EVENT_SELECT,Event Counter Data Select. This field in conjunction with the EVENT_COUNTER_LANE_SELECT field indexes the Event Counter data returned by the EVENT_COUNTER_DATA_REG register. - 27-24: Group number(4-bit: 0..0x7) - 23-16: Event.." newline hexmask.long.byte 0x0 12.--15. 1. "RSVDP_12,Reserved for future use." newline hexmask.long.byte 0x0 8.--11. 1. "EVENT_COUNTER_LANE_SELECT,Event Counter Lane Select. This field in conjunction with EVENT_COUNTER_EVENT_SELECT indexes the Event Counter data returned by the EVENT_COUNTER_DATA_REG register. - 0x0: Lane0 - 0x1: Lane1 - 0x2: Lane2 - .. - 0xF: Lane15 Note:.." newline rbitfld.long 0x0 7. "EVENT_COUNTER_STATUS,Event Counter Status. This register returns the current value of the Event Counter selected by the following fields: - EVENT_COUNTER_EVENT_SELECT - EVENT_COUNTER_LANE_SELECT Note: This register field is sticky." "0,1" newline rbitfld.long 0x0 5.--6. "RSVDP_5,Reserved for future use." "0,1,2,3" newline bitfld.long 0x0 2.--4. "EVENT_COUNTER_ENABLE,Event Counter Enable. Enables/disables the Event Counter selected by the EVENT_COUNTER_EVENT_SELECT and EVENT_COUNTER_LANE_SELECT fields in this register. By default all event counters are disabled. You can enable/disable a specific.." "no change,per event off,?,?,?,?,?,?" newline bitfld.long 0x0 0.--1. "EVENT_COUNTER_CLEAR,Event Counter Clear. Clears the Event Counter selected by the EVENT_COUNTER_EVENT_SELECT and EVENT_COUNTER_LANE_SELECT fields in this register. You can clear the value of a specific Event Counter by writing the 'per clear' code and.." "no change,per clear,?,?" rgroup.long (0xC+0x30C)++0x3 line.long 0x0 "EVENT_COUNTER_DATA_REG,Event Counter Data. This viewport register returns the data selected by the following fields: - EVENT_COUNTER_EVENT_SELECT in EVENT_COUNTER_CONTROL_REG - EVENT_COUNTER_LANE_SELECT in EVENT_COUNTER_CONTROL_REG For more details. see.." hexmask.long 0x0 0.--31. 1. "EVENT_COUNTER_DATA,Event Counter Data. This register returns the data selected by the following fields: - EVENT_COUNTER_EVENT_SELECT in EVENT_COUNTER_CONTROL_REG - EVENT_COUNTER_LANE_SELECT in EVENT_COUNTER_CONTROL_REG Note: This register field is sticky." group.long (0x10+0x30C)++0x3 line.long 0x0 "TIME_BASED_ANALYSIS_CONTROL_REG,Time-based Analysis Control. Used for controlling the measurement of RX/TX data throughput and time spent in each low-power LTSSM state. For more details. see the RAS DES section in the Core Operations chapter of the.." hexmask.long.byte 0x0 24.--31. 1. "TIME_BASED_REPORT_SELECT,Time-based Report Select. Selects what type of data is measured for the selected duration (TIME_BASED_DURATION_SELECT) and returned in TIME_BASED_ANALYSIS_DATA. Each type of data is measured using one of three types of units: -.." newline hexmask.long.byte 0x0 16.--23. 1. "RSVDP_16,Reserved for future use." newline hexmask.long.byte 0x0 8.--15. 1. "TIME_BASED_DURATION_SELECT,Time-based Duration Select. Selects the duration of time-based analysis. When 'manual control' is selected and TIMER_START is set to '1' this analysis never stops until TIMER_STOP is set to '0'. - 0x0: Manual control - 0x1:.." newline hexmask.long.byte 0x0 1.--7. 1. "RSVDP_1,Reserved for future use." newline bitfld.long 0x0 0. "TIMER_START,Timer Start. - 1: Start/Restart - 0: Stop This bit will be cleared automatically when the measurement is finished. Note: The app_ras_des_tba_ctrl input also sets the contents of this field and controls the measurement start/stop. Note: This.." "Stop,Start/Restart" rgroup.long (0x14+0x30C)++0x7 line.long 0x0 "TIME_BASED_ANALYSIS_DATA_REG,Time-based Analysis Data. Contains the measurement results of RX/TX data throughput and time spent in each low-power LTSSM state. This viewport register returns the data selected by the TIME_BASED_REPORT_SELECT field in.." hexmask.long 0x0 0.--31. 1. "TIME_BASED_ANALYSIS_DATA,Time Based Analysis Data. This register returns the data selected by the TIME_BASED_REPORT_SELECT field in TIME_BASED_ANALYSIS_CONTROL_REG. The results are cleared when next measurement starts. Note: This register field is sticky." line.long 0x4 "TIME_BASED_ANALYSIS_DATA_63_32_REG,Upper 32 bits of Time-based Analysis Data. This viewport register returns the data selected by the TIME_BASED_REPORT_SELECT field in TIME_BASED_ANALYSIS_CONTROL_REG. For more details. see the RAS DES section in the Core.." hexmask.long 0x4 0.--31. 1. "TIME_BASED_ANALYSIS_DATA_63_32,Upper 32 bits of Time Based Analysis Data. Note: This register field is sticky." group.long (0x30+0x30C)++0x5F line.long 0x0 "EINJ_ENABLE_REG,Error Injection Enable. Each type of error insertion is enabled by the corresponding bit in this register. The specific injection controls for each type of error are defined in the following registers: - 0: CRC Error: EINJ0_CRC_REG - 1:.." hexmask.long 0x0 7.--31. 1. "RSVDP_7,Reserved for future use." newline bitfld.long 0x0 6. "ERROR_INJECTION6_ENABLE,Error Injection6 Enable (Specific TLP Error). Enables insertion of errors into the packets that you select. You can set this bit to '1' when you have disabled RAS datapath protection (DP) by setting CX_RASDP = CX_RASDP_RAM_PROT.." "0,1" newline bitfld.long 0x0 5. "ERROR_INJECTION5_ENABLE,Error Injection5 Enable (TLP Duplicate/Nullify Error). Enables insertion of duplicate/nullified TLPs. For more details see the EINJ5_SP_TLP_REG register. Note: This register field is sticky." "0,1" newline bitfld.long 0x0 4. "ERROR_INJECTION4_ENABLE,Error Injection4 Enable (FC Credit Update Error). Enables insertion of errors into UpdateFCs. For more details see the EINJ4_FC_REG register. Note: This register field is sticky." "0,1" newline bitfld.long 0x0 3. "ERROR_INJECTION3_ENABLE,Error Injection3 Enable (Symbol DataK Mask Error or Sync Header Error). Enables DataK masking of special symbols or the breaking of the sync header. For more details see the EINJ3_SYMBOL_REG register. Note: This register field is.." "0,1" newline bitfld.long 0x0 2. "ERROR_INJECTION2_ENABLE,Error Injection2 Enable (DLLP Error). Enables insertion of DLLP errors. For more details see the EINJ2_DLLP_REG register. Note: This register field is sticky." "0,1" newline bitfld.long 0x0 1. "ERROR_INJECTION1_ENABLE,Error Injection1 Enable (Sequence Number Error). Enables insertion of errors into sequence numbers. For more details see the EINJ1_SEQNUM_REG register. Note: This register field is sticky." "0,1" newline bitfld.long 0x0 0. "ERROR_INJECTION0_ENABLE,Error Injection0 Enable (CRC Error). Enables insertion of errors into various CRC. For more details see the EINJ0_CRC_REG register. Note: This register field is sticky." "0,1" line.long 0x4 "EINJ0_CRC_REG,Error Injection Control 0 (CRC Error). Controls the insertion of errors into the CRC. and parity of ordered sets for the selected type of the packets as follows: - LCRC. Bad TLP will be detected at the receiver side; receiver responds with.." hexmask.long.tbyte 0x4 12.--31. 1. "RSVDP_12,Reserved for future use." newline hexmask.long.byte 0x4 8.--11. 1. "EINJ0_CRC_TYPE,Error injection type. Selects the type of CRC error to be inserted. Tx Path - 0000b: New TLP's LCRC error injection - 0001b: 16bCRC error injection of ACK/NAK DLLP - 0010b: 16bCRC error injection of Update-FC DLLP - 0011b: New TLP's ECRC.." newline hexmask.long.byte 0x4 0.--7. 1. "EINJ0_COUNT,Error injection count. Indicates the number of errors. This register is decremented when the errors have been inserted. - If the counter value is 0x01 and error is inserted ERROR_INJECTION0_ENABLE in EINJ_ENABLE_REG returns 0b. - If the.." line.long 0x8 "EINJ1_SEQNUM_REG,Error Injection Control 1 (Sequence Number Error). Controls the sequence number of the specific TLPs and ACK/NAK DLLPs. Data Link Protocol Error will be detected at the Rx side of ACK/NAL DLLPs when one of these conditions is true: -.." rbitfld.long 0x8 29.--31. "RSVDP_29,Reserved for future use." "0,1,2,3,4,5,6,7" newline hexmask.long.word 0x8 16.--28. 1. "EINJ1_BAD_SEQNUM,Bad sequence number. Indicates the value to add/subtract from the naturally-assigned sequence numbers. This value is represented by two's complement. - 0x0FFF: +4095 - .. - 0x0002: +2 - 0x0001: +1 - 0x0000: 0 - 0x1FFF: -1 - 0x1FFE: -2 -.." newline hexmask.long.byte 0x8 9.--15. 1. "RSVDP_9,Reserved for future use." newline bitfld.long 0x8 8. "EINJ1_SEQNUM_TYPE,Sequence number type. Selects the type of sequence number. - 0b: Insertion of New TLP's SEQ# error - 1b: Insertion of ACK/NAK DLLP's SEQ# Error Note: This register field is sticky." "0,1" newline hexmask.long.byte 0x8 0.--7. 1. "EINJ1_COUNT,Error injection count. Indicates the number of errors. This register is decremented as the errors are being inserted. - If the counter value is 0x01 and error is inserted ERROR_INJECTION1_ENABLE in EINJ_ENABLE_REG returns '0'. - If the.." line.long 0xC "EINJ2_DLLP_REG,Error Injection Control 2 (DLLP Error). Controls the transmission of DLLPs and inserts the following errors: - If 'ACK/NAK DLLP's transmission block' is selected. replay timeout error will occur at the transmitter of the TLPs and then Data.." hexmask.long.tbyte 0xC 10.--31. 1. "RSVDP_10,Reserved for future use." newline bitfld.long 0xC 8.--9. "EINJ2_DLLP_TYPE,DLLP Type. Selects the type of DLLP errors to be inserted. - 00b: ACK/NAK DLLP's transmission block - 01b: Update FC DLLP's transmission block - 10b: Always Transmission for NAK DLLP - 11b: Reserved Note: This register field is sticky." "0,1,2,3" newline hexmask.long.byte 0xC 0.--7. 1. "EINJ2_COUNT,Error injection count. Indicates the number of errors. This register is decremented as the errors are being inserted. - If the counter value is 0x01 and the error is inserted ERROR_INJECTION2_ENABLE in EINJ_ENABLE_REG returns '0'. - If the.." line.long 0x10 "EINJ3_SYMBOL_REG,Error Injection Control 3 (Symbol Error). When 8b/10b encoding is used. this register controls error insertion into the special (K code) symbols. - If TS1/TS2/FTS/E-Idle/SKP is selected. it affects whole of the ordered set. It might.." hexmask.long.tbyte 0x10 11.--31. 1. "RSVDP_11,Reserved for future use." newline bitfld.long 0x10 8.--10. "EINJ3_SYMBOL_TYPE,Error Type. 8b/10b encoding - Mask K symbol. It is not supported to insert errors into the first ordered-set after exiting from TxElecIdle when CX_FREQ_STEP_EN has been enabled. - 000b: Reserved - 001b: COM/PAD(TS1 Order set) - 010b:.." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x10 0.--7. 1. "EINJ3_COUNT,Error injection count. Indicates the number of errors. This register is decremented as the errors are being inserted. - If the counter value is 0x01 and error is inserted ERROR_INJECTION3_ENABLE in EINJ_ENABLE_REG returns '0'. - If the.." line.long 0x14 "EINJ4_FC_REG,Error Injection Control 4 (FC Credit Error). Controls error insertion into the credit value in the UpdateFCs. It is possible to insert errors for any of the following types: - Posted TLP Header credit - Non-Posted TLP Header credit -.." rbitfld.long 0x14 29.--31. "RSVDP_29,Reserved for future use." "0,1,2,3,4,5,6,7" newline hexmask.long.word 0x14 16.--28. 1. "EINJ4_BAD_UPDFC_VALUE,Bad update-FC credit value. Indicates the value to add/subtract from the UpdateFC credit. This value is represented by two's complement. - 0x0FFF: +4095 - .. - 0x0002: +2 - 0x0001: +1 - 0x0000: 0 - 0x1FFF: -1 - 0x1FFE: -2 - .. -.." newline rbitfld.long 0x14 15. "RSVDP_15,Reserved for future use." "0,1" newline bitfld.long 0x14 12.--14. "EINJ4_VC_NUMBER,VC Number. Indicates target VC Number. Note: This register field is sticky." "0,1,2,3,4,5,6,7" newline rbitfld.long 0x14 11. "RSVDP_11,Reserved for future use." "0,1" newline bitfld.long 0x14 8.--10. "EINJ4_UPDFC_TYPE,Update-FC type. Selects the credit type. - 000b: Posted TLP Header Credit value control - 001b: Non-Posted TLP Header Credit value control - 010b: Completion TLP Header Credit value control - 011b: Reserved - 100b: Posted TLP Data Credit.." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x14 0.--7. 1. "EINJ4_COUNT,Error injection count. Indicates the number of errors. This register is decremented as the errors are being inserted. - If the counter value is 0x01 and error is inserted ERROR_INJECTION4_ENABLE in EINJ_ENABLE_REG returns '0'. - If the.." line.long 0x18 "EINJ5_SP_TLP_REG,Error Injection Control 5 (Specific TLP Error). Controls the generation of specified TLPs. Correctable errors will occur which will be fixed by the PCIe protocol. - For Duplicate TLP. the controller initiates Data Link Retry by handling.." hexmask.long.tbyte 0x18 9.--31. 1. "RSVDP_9,Reserved for future use." newline bitfld.long 0x18 8. "EINJ5_SPECIFIED_TLP,Specified TLP. Selects the specified TLP to be inserted. - 0: Generates duplicate TLPs by handling ACK DLLP as NAK DLLP. - 1: Generates Nullified TLP (Original TLP will be stored in retry buffer). Note: This register field is sticky." "Generates duplicate TLPs by handling ACK DLLP as..,Generates Nullified TLP" newline hexmask.long.byte 0x18 0.--7. 1. "EINJ5_COUNT,Error injection count. Indicates the number of errors. This register is decremented as the errors are being inserted. - If the counter value is 0x01 and error is inserted ERROR_INJECTION5_ENABLE in EINJ_ENABLE_REG returns '0'. - If the.." line.long 0x1C "EINJ6_COMPARE_POINT_H0_REG,Error Injection Control 6 (Compare Point Header DWORD #0). Program this register for the 1st DWORD of TLP header/prefix. It is necessary to carefully consider the endianness when you program this register. Bits [31:0] =.." hexmask.long 0x1C 0.--31. 1. "EINJ6_COMPARE_POINT_H0,Packet Compare Point: 1st DWORD. Specifies which Tx TLP header DWORD#0 bits to compare with the corresponding bits in the Packet Compare Value registers (EINJ6_COMPARE_VALUE*). When all specified bits (in the Tx TLP header and.." line.long 0x20 "EINJ6_COMPARE_POINT_H1_REG,Error Injection Control 6 (Compare Point Header DWORD #1). Program this register for the 2nd DWORD of TLP header/prefix. It is necessary to carefully consider the endianness when you program this register. Bits [31:0] =.." hexmask.long 0x20 0.--31. 1. "EINJ6_COMPARE_POINT_H1,Packet Compare Point: 2nd DWORD. Specifies which Tx TLP header DWORD#1 bits to compare with the corresponding bits in the Packet Compare Value registers (EINJ6_COMPARE_VALUE*). When all specified bits (in the Tx TLP header and.." line.long 0x24 "EINJ6_COMPARE_POINT_H2_REG,Error Injection Control 6 (Compare Point Header DWORD #2). Program this register for the 3rd DWORD of TLP header/prefix. It is necessary to carefully consider the endianness when you program this register. Bits [31:0] =.." hexmask.long 0x24 0.--31. 1. "EINJ6_COMPARE_POINT_H2,Packet Compare Point: 3rd DWORD. Specifies which Tx TLP header DWORD#2 bits to compare with the corresponding bits in the Packet Compare Value registers (EINJ6_COMPARE_VALUE*). When all specified bits (in the Tx TLP header and.." line.long 0x28 "EINJ6_COMPARE_POINT_H3_REG,Error Injection Control 6 (Compare Point Header DWORD #3). Program this register for the 4th DWORD of TLP header/prefix. It is necessary to carefully consider the endianness when you program this register. Bits [31:0] =.." hexmask.long 0x28 0.--31. 1. "EINJ6_COMPARE_POINT_H3,Packet Compare Point: 4th DWORD. Specifies which Tx TLP header DWORD#3 bits to compare with the corresponding bits in the Packet Compare Value registers (EINJ6_COMPARE_VALUE*). When all specified bits (in the Tx TLP header and.." line.long 0x2C "EINJ6_COMPARE_VALUE_H0_REG,Error Injection Control 6 (Compare Value Header DWORD #0). Program this register for the 1st DWORD of TLP header/prefix. It is necessary to carefully consider the endianness when you program this register. Bits [31:0] =.." hexmask.long 0x2C 0.--31. 1. "EINJ6_COMPARE_VALUE_H0,Packet Compare Value: 1st DWORD. Specifies the value to compare against Tx the TLP header DWORD#0 bits specified in the Packet Compare Point registers (EINJ6_COMPARE_POINT*). Note: This register field is sticky." line.long 0x30 "EINJ6_COMPARE_VALUE_H1_REG,Error Injection Control 6 (Compare Value Header DWORD #1). Program this register for the 2nd DWORD of TLP header/prefix. It is necessary to carefully consider the endianness when you program this register. Bits [31:0] =.." hexmask.long 0x30 0.--31. 1. "EINJ6_COMPARE_VALUE_H1,Packet Compare Value: 2nd DWORD. Specifies the value to compare against Tx the TLP header DWORD#1 bits specified in the Packet Compare Point registers (EINJ6_COMPARE_POINT*). Note: This register field is sticky." line.long 0x34 "EINJ6_COMPARE_VALUE_H2_REG,Error Injection Control 6 (Compare Value Header DWORD #2). Program this register for the 3rd DWORD of TLP header/prefix. It is necessary to carefully consider the endianness when you program this register. Bits [31:0] =.." hexmask.long 0x34 0.--31. 1. "EINJ6_COMPARE_VALUE_H2,Packet Compare Value: 3rd DWORD. Specifies the value to compare against Tx the TLP header DWORD#2 bits specified in the Packet Compare Point registers (EINJ6_COMPARE_POINT*). Note: This register field is sticky." line.long 0x38 "EINJ6_COMPARE_VALUE_H3_REG,Error Injection Control 6 (Compare Value Header DWORD #3). Program this register for the 4th DWORD of TLP header/prefix. It is necessary to carefully consider the endianness when you program this register. Bits [31:0] =.." hexmask.long 0x38 0.--31. 1. "EINJ6_COMPARE_VALUE_H3,Packet Compare Value: 4th DWORD. Specifies the value to compare against Tx the TLP header DWORD#3 bits specified in the Packet Compare Point registers (EINJ6_COMPARE_POINT*). Note: This register field is sticky." line.long 0x3C "EINJ6_CHANGE_POINT_H0_REG,Error Injection Control 6 (Change Point Header DWORD #0). Program this register for the 1st DWORD of TLP header/prefix. It is necessary to carefully consider the endianness when you program this register. Bits [31:0] =.." hexmask.long 0x3C 0.--31. 1. "EINJ6_CHANGE_POINT_H0,Packet Change Point: 1st DWORD. Specifies which Tx TLP header DWORD#0 bits to replace with the corresponding bits in the Packet Change Value registers (EINJ6_CHANGE_VALUE*). Note: This register field is sticky." line.long 0x40 "EINJ6_CHANGE_POINT_H1_REG,Error Injection Control 6 (Change Point Header DWORD #1). Program this register for the 2nd DWORD of TLP header/prefix. It is necessary to carefully consider the endianness when you program this register. Bits [31:0] =.." hexmask.long 0x40 0.--31. 1. "EINJ6_CHANGE_POINT_H1,Packet Change Point: 2nd DWORD. Specifies which Tx TLP header DWORD#1 bits to replace with the corresponding bits in the Packet Change Value registers (EINJ6_CHANGE_VALUE*). Note: This register field is sticky." line.long 0x44 "EINJ6_CHANGE_POINT_H2_REG,Error Injection Control 6 (Change Point Header DWORD #2). Program this register for the 3rd DWORD of TLP header/prefix. It is necessary to carefully consider the endianness when you program this register. Bits [31:0] =.." hexmask.long 0x44 0.--31. 1. "EINJ6_CHANGE_POINT_H2,Packet Change Point: 3rd DWORD. Specifies which Tx TLP header DWORD#2 bits to replace with the corresponding bits in the Packet Change Value registers (EINJ6_CHANGE_VALUE*). Note: This register field is sticky." line.long 0x48 "EINJ6_CHANGE_POINT_H3_REG,Error Injection Control 6 (Change Point Header DWORD #3). Program this register for the 4th DWORD of TLP header/prefix. It is necessary to carefully consider the endianness when you program this register. Bits [31:0] =.." hexmask.long 0x48 0.--31. 1. "EINJ6_CHANGE_POINT_H3,Packet Change Point: 4th DWORD. Specifies which Tx TLP header DWORD#3 bits to replace with the corresponding bits in the Packet Change Value registers (EINJ6_CHANGE_VALUE*). Note: This register field is sticky." line.long 0x4C "EINJ6_CHANGE_VALUE_H0_REG,Error Injection Control 6 (Change Value Header DWORD #0). Program this register for the 1st DWORD of TLP header/prefix. It is necessary to carefully consider the endianness when you program this register. Bits [31:0] =.." hexmask.long 0x4C 0.--31. 1. "EINJ6_CHANGE_VALUE_H0,Packet Change Value: 1st DWORD. Specifies replacement values for the Tx TLP header DWORD#0 bits defined in the Packet Change Point registers (EINJ6_CHANGE_POINT*). Only applies when the EINJ6_INVERTED_CONTROL field in EINJ6_TLP_REG.." line.long 0x50 "EINJ6_CHANGE_VALUE_H1_REG,Error Injection Control 6 (Change Value Header DWORD #1). Program this register for the 2nd DWORD of TLP header/prefix. It is necessary to carefully consider the endianness when you program this register. Bits [31:0] =.." hexmask.long 0x50 0.--31. 1. "EINJ6_CHANGE_VALUE_H1,Packet Change Value: 2nd DWORD. Specifies replacement values for the Tx TLP header DWORD#1 bits defined in the Packet Change Point registers (EINJ6_CHANGE_POINT*). Only applies when the EINJ6_INVERTED_CONTROL field in EINJ6_TLP_REG.." line.long 0x54 "EINJ6_CHANGE_VALUE_H2_REG,Error Injection Control 6 (Change Value Header DWORD #2). Program this register for the 3rd DWORD of TLP header/prefix. It is necessary to carefully consider the endianness when you program this register. Bits [31:0] =.." hexmask.long 0x54 0.--31. 1. "EINJ6_CHANGE_VALUE_H2,Packet Change Value: 3rd DWORD. Specifies replacement values for the Tx TLP header DWORD#2 bits defined in the Packet Change Point registers (EINJ6_CHANGE_POINT*). Only applies when the EINJ6_INVERTED_CONTROL field in EINJ6_TLP_REG.." line.long 0x58 "EINJ6_CHANGE_VALUE_H3_REG,Error Injection Control 6 (Change Value Header DWORD #3). Program this register for the 4th DWORD of TLP header/prefix. It is necessary to carefully consider the endianness when you program this register. Bits [31:0] =.." hexmask.long 0x58 0.--31. 1. "EINJ6_CHANGE_VALUE_H3,Packet Change Value: 4th DWORD. Specifies replacement values for the Tx TLP header DWORD#3 bits defined in the Packet Change Point registers (EINJ6_CHANGE_POINT*). Only applies when the EINJ6_INVERTED_CONTROL field in EINJ6_TLP_REG.." line.long 0x5C "EINJ6_TLP_REG,Error Injection Control 6 (Packet Error). The Packet Compare Point registers (EINJ6_COMPARE_POINT*) specify which Tx TLP header bits to compare with the corresponding bits in the Packet Compare Value registers (EINJ6_COMPARE_VALUE*). When.." hexmask.long.tbyte 0x5C 12.--31. 1. "RSVDP_12,Reserved for future use." newline bitfld.long 0x5C 9.--11. "EINJ6_PACKET_TYPE,Packet type. Selects the TLP packets to inject errors into. - 0: TLP Header - 1: TLP Prefix 1st 4-DWORDs - 2: TLP Prefix 2nd -DWORDs - Else: Reserved Note: This register field is sticky." "TLP Header,TLP Prefix 1st 4-DWORDs,TLP Prefix 2nd -DWORDs,?,?,?,?,?" newline bitfld.long 0x5C 8. "EINJ6_INVERTED_CONTROL,Inverted Error Injection Control. - 0: EINJ6_CHANGE_VALUE_H[0/1/2/3] is used to replace bits specified by EINJ6_CHANGE_POINT_H[0/1/2/3]. - 1: EINJ6_CHANGE_VALUE_H[0/1/2/3] is ignored and inverts bits specified by.." "EINJ6_CHANGE_VALUE_H[0/1/2/3] is used to replace..,EINJ6_CHANGE_VALUE_H[0/1/2/3] is ignored and.." newline hexmask.long.byte 0x5C 0.--7. 1. "EINJ6_COUNT,Error Injection Count. Indicates the number of errors to insert. This counter is decremented while errors are been inserted. - If the counter value is 0x01 and error is inserted ERROR_INJECTION6_ENABLE in EINJ_ENABLE_REG returns '0'. - If.." group.long (0xA0+0x30C)++0x7 line.long 0x0 "SD_CONTROL1_REG,Silicon Debug Control 1. For more details. see the RAS DES section in the Core Operations chapter of the Databook." hexmask.long.byte 0x0 24.--31. 1. "RSVDP_24,Reserved for future use." newline bitfld.long 0x0 22.--23. "LOW_POWER_INTERVAL,Low Power Entry Interval Time. Interval Time that the controller starts monitoring RXELECIDLE signal after L0s/L1/L2 entry. You should set the value according to the latency from receiving EIOS to RXELECIDLE assertion at the PHY. -.." "0,1,2,3" newline bitfld.long 0x0 20.--21. "TX_EIOS_NUM,Number of Tx EIOS. This register sets the number of transmit EIOS for L0s/L1 entry and Disable/Loopback/Hot-reset exit. The controller selects the greater value between this register and the value defined by the PCI-SIG specification. 2.5GT/s.." "0,1,2,3" newline rbitfld.long 0x0 17.--19. "RSVDP_17,Reserved for future use." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 16. "FORCE_DETECT_LANE_EN,Force Detect Lane Enable. When this bit is set the controller ignores receiver detection from PHY during LTSSM Detect state and uses FORCE_DETECT_LANE. Note: This register field is sticky." "0,1" newline hexmask.long.word 0x0 0.--15. 1. "FORCE_DETECT_LANE,Force Detect Lane. When the FORCE_DETECT_LANE_EN field is set the controller ignores receiver detection from PHY during LTSSM Detect state and uses this value instead. - 0: Lane0 - 1: Lane1 - 2: Lane2 - .. - 15: Lane15 Note: This.." line.long 0x4 "SD_CONTROL2_REG,Silicon Debug Control 2. For more details. see the RAS DES section in the Core Operations chapter of the Databook." hexmask.long.word 0x4 17.--31. 1. "RSVDP_17,Reserved for future use." newline bitfld.long 0x4 16. "FRAMING_ERR_RECOVERY_DISABLE,Framing Error Recovery Disable. This bit disables a transition to Recovery state when a Framing Error is occurred. Note: This register field is sticky." "0,1" newline hexmask.long.byte 0x4 11.--15. 1. "RSVDP_11,Reserved for future use." newline bitfld.long 0x4 10. "DIRECT_LPBKSLV_TO_EXIT,Direct Loopback Slave To Exit. When this bit is set and the LTSSM is in Loopback Slave Active State the LTSSM transitions to Loopback Slave Exit state. Note: This register field is sticky." "0,1" newline bitfld.long 0x4 9. "DIRECT_POLCOMP_TO_DETECT,Direct Polling.Compliance to Detect. When this bit is set and the LTSSM is in Polling Compliance State the LTSSM transitions to Detect state. Note: This register field is sticky." "0,1" newline bitfld.long 0x4 8. "DIRECT_RECIDLE_TO_CONFIG,Direct Recovery.Idle to Configuration. When this bit is set and the LTSSM is in Recovery Idle State the LTSSM transitions to Configuration state. Note: This register field is sticky." "0,1" newline hexmask.long.byte 0x4 3.--7. 1. "RSVDP_3,Reserved for future use." newline bitfld.long 0x4 2. "NOACK_FORCE_LINKDOWN,Force LinkDown. When this bit is set and the controller detects REPLY_NUM rolling over 4 times the LTSSM transitions to Detect State. Note: This register field is sticky." "0,1" newline bitfld.long 0x4 1. "RECOVERY_REQUEST,Recovery Request. When this bit is set to '1' in L0 or L0s the LTSSM starts transitioning to Recovery State. This request does not cause a speed change or re-equalization." "0,1" newline bitfld.long 0x4 0. "HOLD_LTSSM,Hold and Release LTSSM. For as long as this register is '1' the controller stays in the current LTSSM. Note: This register field is sticky." "0,1" group.long (0xB0+0x30C)++0xB line.long 0x0 "SD_STATUS_L1LANE_REG,Silicon Debug Status(Layer1 Per-lane). This viewport register returns the data selected by the following field: - LANE_SELECT in SD_STATUS_L1LANE_REG For more details. see the RAS DES section in the Core Operations chapter of the.." hexmask.long.byte 0x0 24.--31. 1. "DESKEW_POINTER,Deskew Pointer. Indicates Deskew pointer of internal Deskew buffer of selected lane number(LANE_SELECT). Note: This register field is sticky." newline rbitfld.long 0x0 21.--23. "RSVDP_21,Reserved for future use." "0,1,2,3,4,5,6,7" newline rbitfld.long 0x0 20. "PIPE_TXELECIDLE,PIPE:TxElecIdle. Indicates PIPE TXELECIDLE signal of selected lane number(LANE_SELECT). Note: This register field is sticky." "0,1" newline rbitfld.long 0x0 19. "PIPE_RXELECIDLE,PIPE:RxElecIdle. Indicates PIPE RXELECIDLE signal of selected lane number(LANE_SELECT). Note: This register field is sticky." "0,1" newline rbitfld.long 0x0 18. "PIPE_RXVALID,PIPE:RxValid. Indicates PIPE RXVALID signal of selected lane number(LANE_SELECT). Note: This register field is sticky." "0,1" newline rbitfld.long 0x0 17. "PIPE_DETECT_LANE,PIPE:Detect Lane. Indicates whether PHY indicates receiver detection or not on selected lane number(LANE_SELECT). Note: This register field is sticky." "0,1" newline rbitfld.long 0x0 16. "PIPE_RXPOLARITY,PIPE:RxPolarity. Indicates PIPE RXPOLARITY signal of selected lane number(LANE_SELECT). Note: This register field is sticky." "0,1" newline hexmask.long.word 0x0 4.--15. 1. "RSVDP_4,Reserved for future use." newline hexmask.long.byte 0x0 0.--3. 1. "LANE_SELECT,Lane Select. Lane Select register for Silicon Debug Status Register of Layer1-PerLane. - 0x0: Lane0 - 0x1: Lane1 - 0x2: Lane2 - .. - 0xF: Lane15 Note: This register field is sticky." line.long 0x4 "SD_STATUS_L1LTSSM_REG,Silicon Debug Status(Layer1 LTSSM). For more details. see the RAS DES section in the Core Operations chapter of the Databook." hexmask.long.word 0x4 16.--31. 1. "LTSSM_VARIABLE,LTSSM Variable. Indicates internal LTSSM variables defined in the PCI Express Base Specification. C-PCIe Mode: - 0: directed_speed_change - 1: changed_speed_recovery - 2: successful_speed_negotiation - 3: upconfigure_capable; Set to '1' if.." newline rbitfld.long 0x4 15. "LANE_REVERSAL,Lane Reversal Operation. Receiver detected lane reversal. This field is only valid in the L0 LTSSM state. Note: This register field is sticky." "0,1" newline hexmask.long.byte 0x4 11.--14. 1. "RSVDP_11,Reserved for future use." newline rbitfld.long 0x4 8.--10. "PIPE_POWER_DOWN,PIPE:PowerDown. Indicates PIPE PowerDown signal. Note: This register field is sticky." "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 7. "FRAMING_ERR,Framing Error. Indicates Framing Error detection status." "0,1" newline hexmask.long.byte 0x4 0.--6. 1. "FRAMING_ERR_PTR,First Framing Error Pointer. Identifies the first Framing Error using the following encoding. The field contents are only valid value when FRAMING_ERR =1. Received Unexpected Framing Token - 01h: When non- STP/SDP/IDL Token was received.." line.long 0x8 "SD_STATUS_PM_REG,Silicon Debug Status(PM). For more details. see the RAS DES section in the Core Operations chapter of the Databook." hexmask.long.byte 0x8 24.--31. 1. "RSVDP_24,Reserved for future use." newline hexmask.long.byte 0x8 16.--23. 1. "LATCHED_NFTS,Latched N_FTS. Indicates the value of N_FTS in the received TS Ordered Sets from the Link Partner Note: This register field is sticky." newline rbitfld.long 0x8 13.--15. "L1SUB_STATE,L1Sub State. Indicates internal state machine of L1Sub state. - 0h: S_L1_U : idle state - 1h: S_L1_0 : wait for aux_clk_active - 2h: S_L1_0_WAIT4_ACK : wait for pclkack - 3h: S_L1_0_WAIT4_CLKREQ : wait for clkreq - 4h: S_L1_N_ENTRY : check.." "wait for aux_clk_active,?,?,?,?,?,?,?" newline bitfld.long 0x8 12. "PME_RESEND_FLAG,PME Re-send flag. When the DUT sends a PM_PME message TLP the DUT sets PME_Status bit. If host software does not clear PME_Status bit for 100ms(+50%/-5%) the DUT resends the PM_PME Message. This bit indicates that a PM_PME was resent." "0,1" newline hexmask.long.byte 0x8 8.--11. 1. "INTERNAL_PM_SSTATE,Internal PM State(Slave). Indicates internal state machine of Power Management Slave controller. - 0h: S_IDLE - 1h: S_RESPOND_NAK - 2h: S_BLOCK_TLP - 3h: S_WAIT_LAST_TLP_ACK - 4h: S_WAIT_EIDLE - 5h: S_LINK_ENTR_L1 - 6h: S_L1 - 7h:.." newline rbitfld.long 0x8 5.--7. "RSVDP_5,Reserved for future use." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x8 0.--4. 1. "INTERNAL_PM_MSTATE,Internal PM State(Master). Indicates internal state machine of Power Management Master controller. - 00h: IDLE - 01h: L0 - 02h: L0S - 03h: ENTER_L0S - 04h: L0S_EXIT - 05h: WAIT_PMCSR_CPL_SENT - 08h: L1 - 09h: L1_BLOCK_TLP - 0Ah:.." rgroup.long (0xBC+0x30C)++0x3 line.long 0x0 "SD_STATUS_L2_REG,Silicon Debug Status(Layer2). For more details. see the RAS DES section in the Core Operations chapter of the Databook." hexmask.long.byte 0x0 28.--31. 1. "RSVDP_28,Reserved for future use." newline bitfld.long 0x0 27. "FC_INIT2,FC_INIT2. Indicates the controller is in FC_INIT2(VC0) state. Note: This register field is sticky." "0,1" newline bitfld.long 0x0 26. "FC_INIT1,FC_INIT1. Indicates the controller is in FC_INIT1(VC0) state. Note: This register field is sticky." "0,1" newline bitfld.long 0x0 24.--25. "DLCMSM,DLCMSM. Indicates the current DLCMSM. - 00b: DL_INACTIVE - 01b: DL_FC_INIT - 11b: DL_ACTIVE Note: This register field is sticky." "0,1,2,3" newline hexmask.long.word 0x0 12.--23. 1. "RX_ACK_SEQ_NO,Tx Ack Sequence Number. Indicates ACKD_SEQ which is updated by receiving ACK/NAK DLLP. Note: This register field is sticky." newline hexmask.long.word 0x0 0.--11. 1. "TX_TLP_SEQ_NO,Tx Tlp Sequence Number. Indicates next transmit sequence number for transmit TLP. Note: This register field is sticky." group.long (0xC0+0x30C)++0x7 line.long 0x0 "SD_STATUS_L3FC_REG,Silicon Debug Status(Layer3 FC). The CREDIT_DATA[0/1] fields in this viewport register return the data for the VC and TLP Type selected by the following fields: - CREDIT_SEL_VC - CREDIT_SEL_CREDIT_TYPE - CREDIT_SEL_TLP_TYPE -.." hexmask.long.word 0x0 20.--31. 1. "CREDIT_DATA1,Credit Data1. Current FC credit data selected by the CREDIT_SEL_VC CREDIT_SEL_CREDIT_TYPE CREDIT_SEL_TLP_TYPE and CREDIT_SEL_HD viewport-select fields. - Rx: Credit Allocated Value - Tx: Credit Limit Value. This value is valid when.." newline hexmask.long.word 0x0 8.--19. 1. "CREDIT_DATA0,Credit Data0. Current FC credit data selected by the CREDIT_SEL_VC CREDIT_SEL_CREDIT_TYPE CREDIT_SEL_TLP_TYPE and CREDIT_SEL_HD viewport-select fields. - Rx: Credit Received Value - Tx: Credit Consumed Value Note: This register field is.." newline rbitfld.long 0x0 7. "RSVDP_7,Reserved for future use." "0,1" newline bitfld.long 0x0 6. "CREDIT_SEL_HD,Credit Select(HeaderData). This field in conjunction with the CREDIT_SEL_VC CREDIT_SEL_CREDIT_TYPE and CREDIT_SEL_TLP_TYPE viewport-select fields determines that data that is returned by the CREDIT_DATA0 and CREDIT_DATA1 data fields. -.." "Header Credit,Data Credit" newline bitfld.long 0x0 4.--5. "CREDIT_SEL_TLP_TYPE,Credit Select(TLP Type). This field in conjunction with the CREDIT_SEL_VC CREDIT_SEL_CREDIT_TYPE and CREDIT_SEL_HD viewport-select fields determines that data that is returned by the CREDIT_DATA0 and CREDIT_DATA1 data fields. - 0x0:.." "Posted,Non-Posted,Completion,?" newline bitfld.long 0x0 3. "CREDIT_SEL_CREDIT_TYPE,Credit Select(Credit Type). This field in conjunction with the CREDIT_SEL_VC CREDIT_SEL_TLP_TYPE and CREDIT_SEL_HD viewport-select fields determines that data that is returned by the CREDIT_DATA0 and CREDIT_DATA1 data fields. -.." "Rx,Tx" newline bitfld.long 0x0 0.--2. "CREDIT_SEL_VC,Credit Select(VC). This field in conjunction with the CREDIT_SEL_CREDIT_TYPE CREDIT_SEL_TLP_TYPE and CREDIT_SEL_HD viewport-select fields determines that data that is returned by the CREDIT_DATA0 and CREDIT_DATA1 data fields. - 0x0: VC0 -.." "VC0,VC1,VC2,?,?,?,?,VC7" line.long 0x4 "SD_STATUS_L3_REG,Silicon Debug Status(Layer3). For more details. see the RAS DES section in the Core Operations chapter of the Databook." hexmask.long.tbyte 0x4 8.--31. 1. "RSVDP_8,Reserved for future use." newline bitfld.long 0x4 7. "MFTLP_STATUS,Malformed TLP Status. Indicates malformed TLP has occurred." "0,1" newline hexmask.long.byte 0x4 0.--6. 1. "MFTLP_POINTER,First Malformed TLP Error Pointer. Indicates the element of the received first malformed TLP. This pointer is validated by MFTLP_STATUS. - 01h: AtomicOp address alignment - 02h: AtomicOp operand - 03h: AtomicOp byte enable - 04h: TLP length.." group.long (0xD0+0x30C)++0xB line.long 0x0 "SD_EQ_CONTROL1_REG,Silicon Debug EQ Control 1. This is a viewport control register. Setting the EQ_RATE_SEL and EQ_LANE_SEL fields in this register determine the per-lane Silicon Debug EQ Status data returned by the SD_EQ_STATUS[1/2/3] viewport.." hexmask.long.byte 0x0 24.--31. 1. "FOM_TARGET,FOM Target. Indicates figure of merit target criteria value of EQ Master(DSP in EQ Phase3/USP in EQ Phase2). This field is only valid when GEN3_EQ_FB_MODE is 0001b(Figure Of Merit). Note: This register field is sticky." newline bitfld.long 0x0 23. "FOM_TARGET_ENABLE,FOM Target Enable. Enables the FOM_TARGET fields. Note: This register field is sticky." "0,1" newline hexmask.long.byte 0x0 18.--22. 1. "RSVDP_18,Reserved for future use." newline bitfld.long 0x0 16.--17. "EVAL_INTERVAL_TIME,Eval Interval Time. Indicates interval time of RxEqEval assertion. - 00: 500ns - 01: 1us - 10: 2us - 11: 4us This field is used for EQ Master(DSP in EQ Phase3/USP in EQ Phase2). Note: This register field is sticky." "0,1,2,3" newline hexmask.long.byte 0x0 10.--15. 1. "RSVDP_10,Reserved for future use." newline bitfld.long 0x0 8.--9. "EXT_EQ_TIMEOUT,Extends EQ Phase2/3 Timeout. This field is used when the Ltssm is in Recovery.EQ2/3. When this field is set the value of EQ2/3 timeout is extended. EQ Master(DSP in EQ Phase3/USP in EQ Phase2). - 00: 24ms (default) - 01: 48ms (x2) - 10:.." "0,1,2,3" newline rbitfld.long 0x0 6.--7. "RSVDP_6,Reserved for future use." "0,1,2,3" newline bitfld.long 0x0 4.--5. "EQ_RATE_SEL,EQ Status Rate Select. Setting this field in conjunction with the EQ_LANE_SEL field determines the per-lane Silicon Debug EQ Status data returned by the SD_EQ_CONTROL[2/3] and SD_EQ_STATUS[1/2/3] viewport registers. - 0x0: 8.0GT/s Speed.." "0,1,2,3" newline hexmask.long.byte 0x0 0.--3. 1. "EQ_LANE_SEL,EQ Status Lane Select. Setting this field in conjunction with the EQ_RATE_SEL field determines the per-lane Silicon Debug EQ Status data returned by the SD_EQ_CONTROL[2/3] and SD_EQ_STATUS[1/2/3] viewport registers. - 0x0: Lane0 - 0x1: Lane1.." line.long 0x4 "SD_EQ_CONTROL2_REG,Silicon Debug EQ Control 2. This viewport register returns the value for the rate and lane selected by the EQ_RATE_SEL and EQ_LANE_SEL fields in the SD_EQ_CONTROL1_REG register. For more details. see the RAS DES section in the Core.." rbitfld.long 0x4 31. "RSVDP_31,Reserved for future use." "0,1" newline bitfld.long 0x4 30. "FORCE_LOCAL_TX_PRESET_ENABLE,Force Local Transmitter Preset Enable. Enables the FORCE_LOCAL_TX_PRESET field. If select rate in the EQ_RATE_SEL field is 32.0GT/s Speed this feature is not available. Note: This register field is sticky." "0,1" newline bitfld.long 0x4 29. "FORCE_LOCAL_RX_HINT_ENABLE,Force Local Receiver Preset Hint Enable. Enables the FORCE_LOCAL_RX_HINT field. If select rate in the EQ_RATE_SEL field is other than 8.0GT/s Speed this feature is not available. Note: This register field is sticky." "0,1" newline bitfld.long 0x4 28. "FORCE_LOCAL_TX_COEF_ENABLE,Force Local Transmitter Coefficient Enable. Enables the following fields: - FORCE_LOCAL_TX_PRE_CURSOR - FORCE_LOCAL_TX_CURSOR - FORCE_LOCAL_TX_POST_CURSOR Note: This register field is sticky." "0,1" newline hexmask.long.byte 0x4 24.--27. 1. "FORCE_LOCAL_TX_PRESET,Force Local Transmitter Preset. Indicates initial preset value of USP in EQ Slave(EQ Phase2) instead of receiving EQ TS2. If select rate in the EQ_RATE_SEL field is 32.0GT/s Speed this feature is not available. Note: This register.." newline rbitfld.long 0x4 21.--23. "RSVDP_21,Reserved for future use." "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 18.--20. "FORCE_LOCAL_RX_HINT,Force Local Receiver Preset Hint. Indicates the RxPresetHint value of EQ Slave(DSP in EQ Phase2/USP in EQ Phase3) instead of received or set value. If select rate in the EQ_RATE_SEL field is other than 8.0GT/s Speed this feature is.." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x4 12.--17. 1. "FORCE_LOCAL_TX_POST_CURSOR,Force Local Transmitter Post-Cursor. Indicates the coefficient value of EQ Slave(DSP in EQ Phase2/USP in EQ Phase3) instead of the value instructed from link partner. Note: This register field is sticky." newline hexmask.long.byte 0x4 6.--11. 1. "FORCE_LOCAL_TX_CURSOR,Force Local Transmitter Cursor. Indicates the coefficient value of EQ Slave(DSP in EQ Phase2/USP in EQ Phase3) instead of the value instructed from link partner. Note: This register field is sticky." newline hexmask.long.byte 0x4 0.--5. 1. "FORCE_LOCAL_TX_PRE_CURSOR,Force Local Transmitter Pre-cursor. Indicates the coefficient value of EQ Slave(DSP in EQ Phase2/USP in EQ Phase3) instead of the value instructed from link partner. Note: This register field is sticky." line.long 0x8 "SD_EQ_CONTROL3_REG,Silicon Debug EQ Control 3. This viewport register returns the value for the rate and lane selected by the EQ_RATE_SEL and EQ_LANE_SEL fields in the SD_EQ_CONTROL1_REG register. For more details. see the RAS DES section in the Core.." rbitfld.long 0x8 29.--31. "RSVDP_29,Reserved for future use." "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 28. "FORCE_REMOTE_TX_COEF_ENABLE,Force Remote Transmitter Coefficient Enable. Enables the following fields: - FORCE_REMOTE_TX_PRE_CURSOR - FORCE_REMOTE_TX_CURSOR - FORCE_REMOTE_TX_POST_CURSOR This function can only be used when GEN3_EQ_FB_MODE =.." "0,1" newline hexmask.long.word 0x8 18.--27. 1. "RSVDP_18,Reserved for future use." newline hexmask.long.byte 0x8 12.--17. 1. "FORCE_REMOTE_TX_POST_CURSOR,Force Remote Transmitter Post-Cursor. Indicates the coefficient value of EQ Master(DSP in EQ Phase3/USP in EQ Phase2) instead of the value instructed from local phy in dirchange mode. Note: This register field is sticky." newline hexmask.long.byte 0x8 6.--11. 1. "FORCE_REMOTE_TX_CURSOR,Force Remote Transmitter Cursor. Indicates the coefficient value of EQ Master(DSP in EQ Phase3/USP in EQ Phase2) instead of the value instructed from local phy in dirchange mode. Note: This register field is sticky." newline hexmask.long.byte 0x8 0.--5. 1. "FORCE_REMOTE_TX_PRE_CURSOR,Force Remote Transmitter Pre-Cursor. Indicates the coefficient value of EQ Master(DSP in EQ Phase3/USP in EQ Phase2) instead of the value instructed from local phy in dirchange mode. Note: This register field is sticky." rgroup.long (0xE0+0x30C)++0xB line.long 0x0 "SD_EQ_STATUS1_REG,Silicon Debug EQ Status 1. This viewport register returns the first of three words of Silicon Debug EQ Status data for the rate and lane selected by the EQ_RATE_SEL and EQ_LANE_SEL fields in the SD_EQ_CONTROL1_REG register. The.." hexmask.long.tbyte 0x0 8.--31. 1. "RSVDP_8,Reserved for future use." newline bitfld.long 0x0 7. "EQ_REJECT_EVENT,EQ Reject Event. Indicates that the controller receives two consecutive TS1 OS w/Reject=1b during EQ Master phase(DSP in EQ Phase3/USP in EQ Phase2). This bit is automatically cleared when the controller starts EQ Master phase again." "0,1" newline bitfld.long 0x0 6. "EQ_RULEC_VIOLATION,EQ Rule C Violation. Indicates that coefficients rule C violation is detected in the values provided by PHY using direction change method during EQ Master phase(DSP in EQ Phase3/USP in EQ Phase2). The coefficients rule C correspond to.." "0,1" newline bitfld.long 0x0 5. "EQ_RULEB_VIOLATION,EQ Rule B Violation. Indicates that coefficients rule B violation is detected in the values provided by PHY using direction change method during EQ Master phase(DSP in EQ Phase3/USP in EQ Phase2). The coefficients rules B correspond to.." "0,1" newline bitfld.long 0x0 4. "EQ_RULEA_VIOLATION,EQ Rule A Violation. Indicates that coefficients rule A violation is detected in the values provided by PHY using direction change method during EQ Master phase(DSP in EQ Phase3/USP in EQ Phase2). The coefficients rules A correspond to.." "0,1" newline bitfld.long 0x0 3. "RSVDP_3,Reserved for future use." "0,1" newline bitfld.long 0x0 1.--2. "EQ_CONVERGENCE_INFO,EQ Convergence Info. Indicates equalization convergence information. - 0x0: Equalization is not attempted - 0x1: Equalization finished successfully - 0x2: Equalization finished unsuccessfully - 0x3: Reserved This bit is automatically.." "Equalization is not attempted,Equalization finished successfully,Equalization finished unsuccessfully,Reserved" newline bitfld.long 0x0 0. "EQ_SEQUENCE,EQ Sequence. Indicates that the controller is starting the equalization sequence. Note: This register field is sticky." "0,1" line.long 0x4 "SD_EQ_STATUS2_REG,Silicon Debug EQ Status 2. This viewport register returns the second of three words of Silicon Debug EQ Status data for the rate and lane selected by the EQ_RATE_SEL and EQ_LANE_SEL fields in the SD_EQ_CONTROL1_REG register. Each field.." hexmask.long.byte 0x4 24.--31. 1. "EQ_LOCAL_FOM_VALUE,EQ Local Figure of Merit. Indicates Local maximum Figure of Merit value. Note: This register field is sticky." newline bitfld.long 0x4 21.--23. "RSVDP_21,Reserved for future use." "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 18.--20. "EQ_LOCAL_RX_HINT,EQ Local Receiver Preset Hint. Indicates Local Receiver Preset Hint value. If select rate in the EQ_RATE_SEL field is other than 8.0GT/s Speed this feature is not available. Note: This register field is sticky." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x4 12.--17. 1. "EQ_LOCAL_POST_CURSOR,EQ Local Post-Cursor. Indicates Local post cursor coefficient value. Note: This register field is sticky." newline hexmask.long.byte 0x4 6.--11. 1. "EQ_LOCAL_CURSOR,EQ Local Cursor. Indicates Local cursor coefficient value. Note: This register field is sticky." newline hexmask.long.byte 0x4 0.--5. 1. "EQ_LOCAL_PRE_CURSOR,EQ Local Pre-Cursor. Indicates Local pre cursor coefficient value. Note: This register field is sticky." line.long 0x8 "SD_EQ_STATUS3_REG,Silicon Debug EQ Status 3. This viewport register returns the third of three words of Silicon Debug EQ Status data for the rate and lane selected by the EQ_RATE_SEL and EQ_LANE_SEL fields in the SD_EQ_CONTROL1_REG register. Each field.." bitfld.long 0x8 30.--31. "RSVDP_30,Reserved for future use." "0,1,2,3" newline hexmask.long.byte 0x8 24.--29. 1. "EQ_REMOTE_FS,EQ Remote FS. Indicates Remote FS value. Note: This register field is sticky." newline hexmask.long.byte 0x8 18.--23. 1. "EQ_REMOTE_LF,EQ Remote LF. Indicates Remote LF value. Note: This register field is sticky." newline hexmask.long.byte 0x8 12.--17. 1. "EQ_REMOTE_POST_CURSOR,EQ Remote Post-Cursor. Indicates Remote post cursor coefficient value. Note: This register field is sticky." newline hexmask.long.byte 0x8 6.--11. 1. "EQ_REMOTE_CURSOR,EQ Remote Cursor. Indicates Remote cursor coefficient value. Note: This register field is sticky." newline hexmask.long.byte 0x8 0.--5. 1. "EQ_REMOTE_PRE_CURSOR,EQ Remote Pre-Cursor. Indicates Remote pre cursor coefficient value. Note: This register field is sticky." tree.end tree "PF0_SN_CAP (Device Serial Number Capability Structure)" group.long (0x0+0x170)++0xB line.long 0x0 "SN_BASE,Device Serial Number Extended Capability Header. For a description of this standard PCIe register. see the PCI Express Base Specification." hexmask.long.word 0x0 20.--31. 1. "SN_NEXT_OFFSET,Next Capability Offset. For a description of this standard PCIe register field see the PCI Express Base Specification. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then.." hexmask.long.byte 0x0 16.--19. 1. "SN_CAP_VERSION,Capability Version. For a description of this standard PCIe register field see the PCI Express Base Specification. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky).." hexmask.long.word 0x0 0.--15. 1. "SN_PCIE_EXTENDED_CAP_ID,Serial Number Extended Capability ID. For a description of this standard PCIe register field see the PCI Express Base Specification. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if.." line.long 0x4 "SER_NUM_REG_DW_1,Serial Number 1 Register. For a description of this standard PCIe register. see the PCI Express Base Specification." hexmask.long 0x4 0.--31. 1. "SN_SER_NUM_REG_1_DW,IEEE 64 bit Device Serial Number (DW 1). For a description of this standard PCIe register field see the PCI Express Base Specification. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if.." line.long 0x8 "SER_NUM_REG_DW_2,Serial Number 2 Register. For a description of this standard PCIe register. see the PCI Express Base Specification." hexmask.long 0x8 0.--31. 1. "SN_SER_NUM_REG_2_DW,IEEE 64 bit Device Serial Number (DW 2). For a description of this standard PCIe register field see the PCI Express Base Specification. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if.." tree.end tree "PF0_VSECRAS_CAP (PF RAS Datapath Protection Capability Structure (VSEC))" group.long (0x0+0x480)++0x3 line.long 0x0 "RASDP_EXT_CAP_HDR_OFF,PCIe Extended capability ID. Capability version and Next capability offset. For a description of this standard PCIe register. see the PCI Express Specification." hexmask.long.word 0x0 20.--31. 1. "NEXT_OFFSET,Next Capability Offset. For a description of this standard PCIe register see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else.." newline hexmask.long.byte 0x0 16.--19. 1. "CAP,Capability Version. For a description of this standard PCIe register see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note:.." newline hexmask.long.word 0x0 0.--15. 1. "ID,PCI Express Extended Capability ID. For a description of this standard PCIe register see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else.." rgroup.long (0x4+0x480)++0x3 line.long 0x0 "RASDP_VENDOR_SPECIFIC_HDR_OFF,Vendor Specific Header. For a description of this standard PCIe register. see the PCI Express Specification." hexmask.long.word 0x0 20.--31. 1. "VSEC_LENGTH,VSEC Length. For a description of this standard PCIe register see the PCI Express Specification. Note: This register field is sticky." newline hexmask.long.byte 0x0 16.--19. 1. "VSEC_REV,VSEC Rev. For a description of this standard PCIe register see the PCI Express Specification. Note: This register field is sticky." newline hexmask.long.word 0x0 0.--15. 1. "VSEC_ID,VSEC ID. For a description of this standard PCIe register see the PCI Express Specification. Note: This register field is sticky." group.long (0x8+0x480)++0x7 line.long 0x0 "RASDP_ERROR_PROT_CTRL_OFF,ECC error correction control. Allows you to disable ECC error correction for RAMs and datapath. When the AXI Bridge Module is implemented and the master / slave clocks are asynchronous to the PCIe native controller clock.." hexmask.long.byte 0x0 24.--31. 1. "RSVDP_24,Reserved for future use." newline bitfld.long 0x0 23. "ERROR_PROT_DISABLE_CXS_RX,Error correction disable for CXS Tx path (PCIe Rx path). Note: This register field is sticky." "0,1" newline bitfld.long 0x0 22. "ERROR_PROT_DISABLE_ADM_RX,Error correction disable for ADM Rx path. Note: This register field is sticky." "0,1" newline bitfld.long 0x0 21. "ERROR_PROT_DISABLE_LAYER3_RX,Error correction disable for layer 3 Rx path. Note: This register field is sticky." "0,1" newline bitfld.long 0x0 20. "ERROR_PROT_DISABLE_LAYER2_RX,Error correction disable for layer 2 Rx path. Note: This register field is sticky." "0,1" newline bitfld.long 0x0 19. "ERROR_PROT_DISABLE_DMA_READ,Error correction disable for DMA read engine. Note: This register field is sticky." "0,1" newline bitfld.long 0x0 18. "ERROR_PROT_DISABLE_AXI_BRIDGE_INBOUND_REQUEST,Error correction disable for AXI bridge inbound request path. Note: This register field is sticky." "0,1" newline bitfld.long 0x0 17. "ERROR_PROT_DISABLE_AXI_BRIDGE_INBOUND_COMPLETION,Error correction disable for AXI bridge inbound completion composer. Does not disable the error detection reporting for 1-bit and 2-bit ECC errors. Note: This register field is sticky." "?,bit and 2-bit ECC errors" newline bitfld.long 0x0 16. "ERROR_PROT_DISABLE_RX,Global error correction disable for all Rx layers. Note: This register field is sticky." "0,1" newline hexmask.long.byte 0x0 9.--15. 1. "RSVDP_9,Reserved for future use." newline bitfld.long 0x0 8. "ERROR_PROT_DISABLE_DTIM_TX,Error correction disable for DTIM Tx path. Note: This register field is sticky." "0,1" newline bitfld.long 0x0 7. "ERROR_PROT_DISABLE_CXS_TX,Error correction disable for CXS Rx path (PCIe Tx path). Note: This register field is sticky." "0,1" newline bitfld.long 0x0 6. "ERROR_PROT_DISABLE_ADM_TX,Error correction disable for Adm Tx path. Note: This register field is sticky." "0,1" newline bitfld.long 0x0 5. "ERROR_PROT_DISABLE_LAYER3_TX,Error correction disable for layer 3 Tx path. Note: This register field is sticky." "0,1" newline bitfld.long 0x0 4. "ERROR_PROT_DISABLE_LAYER2_TX,Error correction disable for layer 2 Tx path. Note: This register field is sticky." "0,1" newline bitfld.long 0x0 3. "ERROR_PROT_DISABLE_DMA_WRITE,Error correction disable for DMA write engine. Note: This register field is sticky." "0,1" newline bitfld.long 0x0 2. "ERROR_PROT_DISABLE_AXI_BRIDGE_OUTBOUND,Error correction disable for AXI bridge outbound request path. Note: This register field is sticky." "0,1" newline bitfld.long 0x0 1. "ERROR_PROT_DISABLE_AXI_BRIDGE_MASTER,Error correction disable for AXI bridge master completion buffer. Note: This register field is sticky." "0,1" newline bitfld.long 0x0 0. "ERROR_PROT_DISABLE_TX,Global error correction disable for all Tx layers. Does not disable the error detection reporting for 1-bit and 2-bit ECC errors. Note: This register field is sticky." "?,bit and 2-bit ECC errors" line.long 0x4 "RASDP_CORR_COUNTER_CTRL_OFF,Corrected error (1-bit ECC) counter selection and control. This is a viewport control register. Setting the CORR_COUNTER_SELECTION_REGION and CORR_COUNTER_SELECTION fields in this register determine the counter data returned.." hexmask.long.byte 0x4 24.--31. 1. "CORR_COUNTER_SELECTION,Counter selection. This field selects the counter ID (within the region defined by CORR_COUNTER_SELECTION_REGION) whose contents can be read from the RASDP_CORR_COUNT_REPORT_OFF register. You can cycle this field value from 0 to.." newline hexmask.long.byte 0x4 20.--23. 1. "CORR_COUNTER_SELECTION_REGION,Select correctable counter region: - 0x0: Region select for Adm Rx path - 0x1: Region select for layer 3 Rx path - 0x2: Region select for layer 2 Rx path - 0x3: Region select for DMA inbound path - 0x4: Region select for AXI.." newline hexmask.long.word 0x4 5.--19. 1. "RSVDP_5,Reserved for future use." newline bitfld.long 0x4 4. "CORR_EN_COUNTERS,Enable correctable errors counters. - 1: counters increment when the controller detects a correctable error - 0: counters are frozen The counters are enabled by default." "counters are frozen,counters increment when the controller detects a.." newline rbitfld.long 0x4 1.--3. "RSVDP_1,Reserved for future use." "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 0. "CORR_CLEAR_COUNTERS,Clear all correctable error counters." "0,1" rgroup.long (0x10+0x480)++0x3 line.long 0x0 "RASDP_CORR_COUNT_REPORT_OFF,Corrected error (1-bit ECC) counter data. This viewport register returns the counter data selected by the CORR_COUNTER_SELECTION_REGION and CORR_COUNTER_SELECTION fields in the RASDP_CORR_COUNTER_CTRL_OFF register." hexmask.long.byte 0x0 24.--31. 1. "CORR_COUNTER_SELECTED,Counter selection. Returns the value set in the CORR_COUNTER_SELECTION field of the RASDP_CORR_COUNTER_CTRL_OFF register." newline hexmask.long.byte 0x0 20.--23. 1. "CORR_COUNTER_SELECTED_REGION,Selected correctable counter region: - 0x0: Region select for Adm Rx path - 0x1: Region select for layer 3 Rx path - 0x2: Region select for layer 2 Rx path - 0x3: Region select for DMA inbound path - 0x4: Region select for.." newline hexmask.long.word 0x0 8.--19. 1. "RSVDP_8,Reserved for future use." newline hexmask.long.byte 0x0 0.--7. 1. "CORR_COUNTER,Current corrected error count for the selected counter." group.long (0x14+0x480)++0x3 line.long 0x0 "RASDP_UNCORR_COUNTER_CTRL_OFF,Uncorrected error (2-bit ECC and parity) counter selection and control. This is a viewport control register. Setting the UNCORR_COUNTER_SELECTION_REGION and UNCORR_COUNTER_SELECTION fields in this register determine the.." hexmask.long.byte 0x0 24.--31. 1. "UNCORR_COUNTER_SELECTION,Counter selection. This field selects the counter ID (within the region defined by UNCORR_COUNTER_SELECTION_REGION) whose contents can be read from the RASDP_UNCORR_COUNT_REPORT_OFF register. You can cycle this field value from 0.." newline hexmask.long.byte 0x0 20.--23. 1. "UNCORR_COUNTER_SELECTION_REGION,Select uncorrectable counter region: - 0x0: Region select for Adm Rx path - 0x1: Region select for layer 3 Rx path - 0x2: Region select for layer 2 Rx path - 0x3: Region select for DMA inbound path - 0x4: Region select for.." newline hexmask.long.word 0x0 5.--19. 1. "RSVDP_5,Reserved for future use." newline bitfld.long 0x0 4. "UNCORR_EN_COUNTERS,Enable uncorrectable errors counters. - 1: enables the counters to increment on detected correctable errors - 0: counters are frozen The counters are enabled by default." "counters are frozen,enables the counters to increment on detected.." newline rbitfld.long 0x0 1.--3. "RSVDP_1,Reserved for future use." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 0. "UNCORR_CLEAR_COUNTERS,Clear uncorrectable errors counters. When asserted causes all counters tracking the uncorrectable errors to be cleared." "0,1" rgroup.long (0x18+0x480)++0x3 line.long 0x0 "RASDP_UNCORR_COUNT_REPORT_OFF,Uncorrected error (2-bit ECC and parity) counter data. This viewport register returns the counter data selected by the UNCORR_COUNTER_SELECTION_REGION and UNCORR_COUNTER_SELECTION fields in the RASDP_UNCORR_COUNTER_CTRL_OFF.." hexmask.long.byte 0x0 24.--31. 1. "UNCORR_COUNTER_SELECTED,Counter selection. Returns the value set in the UNCORR_COUNTER_SELECTION field of the RASDP_UNCORR_COUNTER_CTRL_OFF register." newline hexmask.long.byte 0x0 20.--23. 1. "UNCORR_COUNTER_SELECTED_REGION,Selected uncorrectable counter region: - 0x0: Region select for Adm Rx path - 0x1: Region select for layer 3 Rx path - 0x2: Region select for layer 2 Rx path - 0x3: Region select for DMA inbound path - 0x4: Region select.." newline hexmask.long.word 0x0 8.--19. 1. "RSVDP_8,Reserved for future use." newline hexmask.long.byte 0x0 0.--7. 1. "UNCORR_COUNTER,Current uncorrected error count for the selected counter" group.long (0x1C+0x480)++0x3 line.long 0x0 "RASDP_ERROR_INJ_CTRL_OFF,Error injection control for the following features: - 1-bit or 2-bit injection - Continuous or fixed-number (n) injection modes - Global enable/disable - Selectable location where injection occurs" hexmask.long.byte 0x0 24.--31. 1. "RSVDP_24,Reserved for future use." newline hexmask.long.byte 0x0 16.--23. 1. "ERROR_INJ_LOC,Error injection location. Selects where error injection takes place. You can cycle this field value from 0 to 255 to access all locations according to the detailed report of check points at.." newline hexmask.long.byte 0x0 8.--15. 1. "ERROR_INJ_COUNT,Error injection count. - 0: errors are inserted in every TLP until you clear ERROR_INJ_EN. - 1: one errors injected - 2: two errors injected - n: amount of errors injected" newline rbitfld.long 0x0 6.--7. "RSVDP_6,Reserved for future use." "0,1,2,3" newline bitfld.long 0x0 4.--5. "ERROR_INJ_TYPE,Error injection type: - 0: none - 1: 1-bit - 2: 2-bit" "none,bit,bit,?" newline rbitfld.long 0x0 1.--3. "RSVDP_1,Reserved for future use." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 0. "ERROR_INJ_EN,Error injection global enable. When set enables the error insertion logic." "0,1" rgroup.long (0x20+0x480)++0x7 line.long 0x0 "RASDP_CORR_ERROR_LOCATION_OFF,Corrected errors locations. For more details. see the RAS Data Protection (DP) section in the Core Operations chapter of the Databook." hexmask.long.byte 0x0 24.--31. 1. "LOC_LAST_CORR_ERROR,Location/ID of the last corrected error within the region defined by REG_LAST_CORR_ERROR. You can cycle this field value from 0 to 255 to access all counters according to the detailed report of check points at.." newline hexmask.long.byte 0x0 20.--23. 1. "REG_LAST_CORR_ERROR,Region of the last corrected error: - 0x0: Region select for Adm Rx path - 0x1: Region select for layer 3 Rx path - 0x2: Region select for layer 2 Rx path - 0x3: Region select for DMA inbound path - 0x4: Region select for AXI bridge.." newline hexmask.long.byte 0x0 16.--19. 1. "RSVDP_16,Reserved for future use." newline hexmask.long.byte 0x0 8.--15. 1. "LOC_FIRST_CORR_ERROR,Location/ID of the first corrected error within the region defined by REG_FIRST_CORR_ERROR. You can cycle this field value from 0 to 255 to access all counters according to the detailed report of check points at.." newline hexmask.long.byte 0x0 4.--7. 1. "REG_FIRST_CORR_ERROR,Region of the first corrected error: - 0x0: Region select for Adm Rx path - 0x1: Region select for layer 3 Rx path - 0x2: Region select for layer 2 Rx path - 0x3: Region select for DMA inbound path - 0x4: Region select for AXI bridge.." newline hexmask.long.byte 0x0 0.--3. 1. "RSVDP_0,Reserved for future use." line.long 0x4 "RASDP_UNCORR_ERROR_LOCATION_OFF,Uncorrected errors locations. For more details. see the RAS Data Protection (DP) section in the Core Operations chapter of the Databook." hexmask.long.byte 0x4 24.--31. 1. "LOC_LAST_UNCORR_ERROR,Location/ID of the last uncorrected error within the region defined by REG_LAST_UNCORR_ERROR. You can cycle this field value from 0 to 255 to access all counters according to the detailed report of check points at.." newline hexmask.long.byte 0x4 20.--23. 1. "REG_LAST_UNCORR_ERROR,Region of the last uncorrected error: - 0x0: Region select for Adm Rx path - 0x1: Region select for layer 3 Rx path - 0x2: Region select for layer 2 Rx path - 0x3: Region select for DMA inbound path - 0x4: Region select for AXI.." newline hexmask.long.byte 0x4 16.--19. 1. "RSVDP_16,Reserved for future use." newline hexmask.long.byte 0x4 8.--15. 1. "LOC_FIRST_UNCORR_ERROR,Location/ID of the first uncorrected error within the region defined by REG_FIRST_UNCORR_ERROR. You can cycle this field value from 0 to 255 to access all counters according to the detailed report of check points at.." newline hexmask.long.byte 0x4 4.--7. 1. "REG_FIRST_UNCORR_ERROR,Region of the first uncorrected error: - 0x0: Region select for Adm Rx path - 0x1: Region select for layer 3 Rx path - 0x2: Region select for layer 2 Rx path - 0x3: Region select for DMA inbound path - 0x4: Region select for AXI.." newline hexmask.long.byte 0x4 0.--3. 1. "RSVDP_0,Reserved for future use." group.long (0x28+0x480)++0x7 line.long 0x0 "RASDP_ERROR_MODE_EN_OFF,RASDP error mode enable. The controller enters RASDP error mode (if ERROR_MODE_EN =1) upon detection of the first uncorrectable error. During this mode: - Rx TLPs that are forwarded to your application are not guaranteed to be.." hexmask.long 0x0 2.--31. 1. "RSVDP_2,Reserved for future use." newline bitfld.long 0x0 1. "AUTO_LINK_DOWN_EN,Write '1' to enable the controller to bring the link down when the controller enters RASDP error mode. Note: This register field is sticky." "0,1" newline bitfld.long 0x0 0. "ERROR_MODE_EN,Write '1' to enable the controller enter RASDP error mode when it detects an uncorrectable error. Note: This register field is sticky." "0,1" line.long 0x4 "RASDP_ERROR_MODE_CLEAR_OFF,Exit RASDP error mode. For more details. see the RAS Data Protection (DP) section in the Core Operations chapter of the Databook." hexmask.long 0x4 1.--31. 1. "RSVDP_1,Reserved for future use." newline bitfld.long 0x4 0. "ERROR_MODE_CLEAR,Write '1' to take the controller out of RASDP error mode. The controller will then report uncorrectable errors (through AER internal error reporting) and also stop nullifying/discarding TLPs." "0,1" rgroup.long (0x30+0x480)++0x7 line.long 0x0 "RASDP_RAM_ADDR_CORR_ERROR_OFF,RAM Address where a corrected error (1-bit ECC) has been detected. For more details. see the RAS Data Protection (DP) section in the Core Operations chapter of the Databook." hexmask.long.byte 0x0 28.--31. 1. "RAM_INDEX_CORR_ERROR,RAM index where a corrected error (1-bit ECC) has been detected." newline bitfld.long 0x0 27. "RSVDP_27,Reserved for future use." "0,1" newline hexmask.long 0x0 0.--26. 1. "RAM_ADDR_CORR_ERROR,RAM Address where a corrected error (1-bit ECC) has been detected." line.long 0x4 "RASDP_RAM_ADDR_UNCORR_ERROR_OFF,RAM Address where an uncorrected error (2-bit ECC) has been detected. For more details. see the RAS Data Protection (DP) section in the Core Operations chapter of the Databook." hexmask.long.byte 0x4 28.--31. 1. "RAM_INDEX_UNCORR_ERROR,RAM index where an uncorrected error (2-bit ECC) has been detected." newline bitfld.long 0x4 27. "RSVDP_27,Reserved for future use." "0,1" newline hexmask.long 0x4 0.--26. 1. "RAM_ADDR_UNCORR_ERROR,RAM Address where an uncorrected error (2-bit ECC) has been detected." tree.end tree "PF0_RTR_CAP (PF RTR Capability Structure)" group.long (0x0+0x2F8)++0xB line.long 0x0 "RTR_EXT_CAP_HDR_OFF,Readiness Time Reporting PCI Express Extended Capability Header. For a description of this standard PCIe register. see the PCI Express Specification." hexmask.long.word 0x0 20.--31. 1. "RTR_NEXT_OFFSET,Next Capability Offset. For a description of this standard PCIe register field see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky).." hexmask.long.byte 0x0 16.--19. 1. "RTR_CAP_VERSION,Capability Version. For a description of this standard PCIe register field see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky).." hexmask.long.word 0x0 0.--15. 1. "RTR_EXT_CAP_ID,PCI Express Extended Capability ID. For a description of this standard PCIe register field see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then.." line.long 0x4 "READI_TIME_REPORTING1_OFF,Readiness Time Reporting 1. For a description of this standard PCIe register. see the PCI Express Specification." bitfld.long 0x4 31. "RTR_TIME_VALID,Valid. For a description of this standard PCIe register field see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky)" "0,1" hexmask.long.byte 0x4 24.--30. 1. "RSVDP_24,Reserved for future use." hexmask.long.word 0x4 12.--23. 1. "DL_UP_TIME,DL_UP Time. For a description of this standard PCIe register field see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky)" hexmask.long.word 0x4 0.--11. 1. "RESET_TIME,Reset Time. For a description of this standard PCIe register field see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky)" line.long 0x8 "READI_TIME_REPORTING2_OFF,Readiness Time Reporting 2. For a description of this standard PCIe register. see the PCI Express Specification." hexmask.long.byte 0x8 24.--31. 1. "RSVDP_24,Reserved for future use." hexmask.long.word 0x8 12.--23. 1. "D3HOT_D0_TIME,D3hot to D0 Time. For a description of this standard PCIe register field see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else.." hexmask.long.word 0x8 0.--11. 1. "FLR_TIME,FLR Time. For a description of this standard PCIe register field see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky)" tree.end tree "PF0_RTR_CAP_DBI2 (DBI2 Shadow Block: PF RTR Capability Structure)" rgroup.long (0x4+0x12F8)++0x7 line.long 0x0 "SHADOW_READI_TIME_REPORTING1_OFF,Shadow Register Readiness Time Reporting 1. For a description of this standard PCIe register. see the PCI Express Specification." bitfld.long 0x0 31. "RTR_TIME_VALID,Shadow Valid in the shadow register. For a description of this standard PCIe register field see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access - Dbi: No access - Dbi2: if.." "0,1" hexmask.long.tbyte 0x0 12.--30. 1. "RSVDP_12,Reserved for future use." hexmask.long.word 0x0 0.--11. 1. "RESET_TIME,Shadow Reset Time in the shadow register. For a description of this standard PCIe register field see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access - Dbi: No access - Dbi2: if.." line.long 0x4 "SHADOW_READI_TIME_REPORTING2_OFF,Shadow Register Readiness Time Reporting 2. For a description of this standard PCIe register. see the PCI Express Specification." hexmask.long.byte 0x4 24.--31. 1. "RSVDP_24,Reserved for future use." hexmask.long.word 0x4 12.--23. 1. "D3HOT_D0_TIME,Shadow D3hot to D0 Time in the shadow register. For a description of this standard PCIe register field see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access - Dbi: No access - Dbi2:.." hexmask.long.word 0x4 0.--11. 1. "FLR_TIME,Shadow FLR Time in the shadow register. For a description of this standard PCIe register field see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access - Dbi: No access - Dbi2: if.." tree.end tree "PF0_FRSQ_CAP (PF FRSQ Capability Structure)" group.long (0x0+0x2E8)++0xB line.long 0x0 "FRSQ_EXT_CAP_HDR_OFF,FRS Queuing Extended Capability Header. For a description of this standard PCIe register. see the PCI Express Specification." hexmask.long.word 0x0 20.--31. 1. "FRSQ_NEXT_OFFSET,Next Capability Offset. For a description of this standard PCIe register field see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then.." hexmask.long.byte 0x0 16.--19. 1. "FRSQ_CAP_VERSION,Capability Version. For a description of this standard PCIe register field see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky).." hexmask.long.word 0x0 0.--15. 1. "FRSQ_EXT_CAP_ID,PCI Express Extended Capability ID. For a description of this standard PCIe register field see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then.." line.long 0x4 "FRSQ_CAP_OFF,FRS Queuing Capability Register. For a description of this standard PCIe register. see the PCI Express Specification." hexmask.long.word 0x4 21.--31. 1. "RSVDP_21,Reserved for future use." hexmask.long.byte 0x4 16.--20. 1. "FRS_INT_MESSAGE_NUMBER,FRS Interrupt Message Number. For a description of this standard PCIe register field see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1).." hexmask.long.byte 0x4 12.--15. 1. "RSVDP_12,Reserved for future use." hexmask.long.word 0x4 0.--11. 1. "FRSQ_MAX_DEPTH,FRS Queue Max Depth. For a description of this standard PCIe register field see the PCI Express Specification." line.long 0x8 "FRSQ_CONTROL_FRSQ_STATUS_OFF,FRS Queuing Status and Control Register. For a description of this standard PCIe register. see the PCI Express Specification." hexmask.long.word 0x8 17.--31. 1. "RSVDP_17,Reserved for future use." bitfld.long 0x8 16. "FRS_INTERRUPT_ENABLE,FRS Interrupt Enable. For a description of this standard PCIe register field see the PCI Express Specification." "0,1" hexmask.long.word 0x8 2.--15. 1. "RSVDP_2,Reserved for future use." bitfld.long 0x8 1. "FRS_MESSAGE_OVERFLOW,FRS Message Overflow. For a description of this standard PCIe register field see the PCI Express Specification." "0,1" newline bitfld.long 0x8 0. "FRS_MESSAGE_RECEIVED,FRS Message Received. For a description of this standard PCIe register field see the PCI Express Specification." "0,1" rgroup.long (0xC+0x2E8)++0x3 line.long 0x0 "FRS_MESSAGE_QUEUE_OFF,FRS Message Queue Register. For a description of this standard PCIe register. see the PCI Express Specification." hexmask.long.word 0x0 20.--31. 1. "FRS_MESSAGE_QUE_DEPTH,FRS Message Queue Depth. For a description of this standard PCIe register field see the PCI Express Specification." hexmask.long.byte 0x0 16.--19. 1. "FRS_MESSAGE_QUE_REASON,FRS Message Queue Reason. For a description of this standard PCIe register field see the PCI Express Specification." hexmask.long.word 0x0 0.--15. 1. "FRS_MESSAGE_QUE_FUNC_ID,FRS Message Queue Function ID. For a description of this standard PCIe register field see the PCI Express Specification." tree.end tree "PF0_PTM_CAP (PF PTM Capability Structure)" group.long (0x0+0x40C)++0xB line.long 0x0 "PTM_EXT_CAP_HDR_OFF,Precision Time Measurement Capability Header. For a description of this standard PCIe register. see the PCI Express Specification." hexmask.long.word 0x0 20.--31. 1. "PTM_NEXT_OFFSET,Precision Time Measurement PCI Express Extended Capability Next Offset. For a description of this standard PCIe register see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access. -.." hexmask.long.byte 0x0 16.--19. 1. "PTM_CAP_VERSION,Precision Time Measurement PCI Express Extended Capability Version. For a description of this standard PCIe register see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi:.." hexmask.long.word 0x0 0.--15. 1. "PTM_CAP_ID,Precision Time Measurement PCI Express Extended Capability ID. For a description of this standard PCIe register see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if.." line.long 0x4 "PTM_CAP_OFF,PTM Capability Register. For a description of this standard PCIe register. see the PCI Express Specification." hexmask.long.word 0x4 16.--31. 1. "RSVDP_16,Reserved for future use." hexmask.long.byte 0x4 8.--15. 1. "PTM_CLK_GRAN,PTM Local Clock Granularity. For a description of this standard PCIe register see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky).." hexmask.long.byte 0x4 3.--7. 1. "RSVDP_3,Reserved for future use." bitfld.long 0x4 2. "PTM_ROOT_CAPABLE,PTM Root Capable. For a description of this standard PCIe register see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else.." "0,1" bitfld.long 0x4 1. "PTM_RES_CAPABLE,PTM Responder Capable. For a description of this standard PCIe register see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else.." "0,1" newline bitfld.long 0x4 0. "PTM_REQ_CAPABLE,PTM Requester Capable. For a description of this standard PCIe register see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else.." "0,1" line.long 0x8 "PTM_CONTROL_OFF,PTM Control Register. For a description of this standard PCIe register. see the PCI Express Specification." hexmask.long.word 0x8 16.--31. 1. "RSVDP_16,Reserved for future use." hexmask.long.byte 0x8 8.--15. 1. "EFF_GRAN,PTM Effective Granularity. For a description of this standard PCIe register see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: HWINIT" hexmask.long.byte 0x8 2.--7. 1. "RSVDP_2,Reserved for future use." rbitfld.long 0x8 1. "ROOT_SELECT,PTM Root Select. When set this Time Source is the PTM Root. For a description of this standard PCIe register see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: HWINIT" "0,1" bitfld.long 0x8 0. "PTM_ENABLE,PTM Enable. When set this function is permitted to participate in the PTM mechanism. For a description of this standard PCIe register see the PCI Express Specification." "0,1" tree.end tree "PF0_PTM_RES_CAP (PF PTM Responder Capability Structure (VSEC))" group.long (0x0+0x418)++0xB line.long 0x0 "PTM_RES_CAP_HDR_OFF,Precision Time Measurement Responder Capability Header (VSEC). For more details. see the PTM section in the Databook." hexmask.long.word 0x0 20.--31. 1. "PTM_RES_EXT_CAP_NEXT_OFFS,Precision Time Measurement Responder VSEC Next Pointer. For more details see the PTM section in the Databook. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then.." hexmask.long.byte 0x0 16.--19. 1. "PTM_RES_EXT_CAP_VER,Precision Time Measurement Responder VSEC Version. For more details see the PTM section in the Databook. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else.." hexmask.long.word 0x0 0.--15. 1. "PTM_RES_EXT_CAP_ID,Precision Time Measurement Responder VSEC ID. For more details see the PTM section in the Databook. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else.." line.long 0x4 "PTM_RES_HDR_OFF,Precision Time Measurement Responder Vendor Specific Header. For more details. see the PTM section in the Databook." hexmask.long.word 0x4 20.--31. 1. "PTM_RES_VSEC_LENGTH,PTM Responder VSEC Length. For more details see the PTM section in the Databook. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This.." hexmask.long.byte 0x4 16.--19. 1. "PTM_RES_VSEC_REV,PTM Responder VSEC Revision. For more details see the PTM section in the Databook. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This.." hexmask.long.word 0x4 0.--15. 1. "PTM_RES_VSEC_ID,PTM Responder VSEC ID. For more details see the PTM section in the Databook. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register.." line.long 0x8 "PTM_RES_CONTROL_OFF,PTM Responder Control Register. For more details. see the PTM section in the Databook." hexmask.long 0x8 2.--31. 1. "RSVDP_2,Reserved for future use." bitfld.long 0x8 1. "PTM_RES_PDEL_BYTE_REV,PTM Requester Propagation Delay Byte Reversal - Reverse the order of bytes in the PTM Propagation Delay data word of the PTM ResponseD Message for compatibility with previous revisions. For more details see the PTM section in the.." "0,1" bitfld.long 0x8 0. "PTM_RES_CCONTEXT_VALID,PTM Responder Control Context Valid - PTM Local Timing is valid. This bit is set over the DBI. A speed change or aux_clk_active will set this bit low. For more details see the PTM section in the Databook. Note: The access.." "0,1" rgroup.long (0xC+0x418)++0x3 line.long 0x0 "PTM_RES_STATUS_OFF,PTM Responder Status Register. For more details. see the PTM section in the Databook." hexmask.long 0x0 2.--31. 1. "RSVDP_2,Reserved for future use." bitfld.long 0x0 1. "PTM_RES_REQUEST_RECEIVED,PTM 1st Request Received - PTM Responder has received the first PTM Request Message. Upon receipt of a second PTM Request Message a ResponseD message with timing information will be sent from the Responder if the context is.." "0,1" bitfld.long 0x0 0. "PTM_RES_CONTEXT_VALID,PTM Responder Status Context Valid - PTM Local Timing Context is Valid. Value set from upstream port Requester in a Switch. Shadows the same in the control register in all other products. For more details see the PTM section in the.." "0,1" group.long (0x10+0x418)++0x7 line.long 0x0 "PTM_RES_LOCAL_LSB_OFF,PTM Responder Local Clock LSB. For more details. see the PTM section in the Databook." hexmask.long 0x0 0.--31. 1. "PTM_RES_LOCAL_LSB,PTM Responder Local Clock LSB - Lower 32 bits of local timer value. For more details see the PTM section in the Databook. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then.." line.long 0x4 "PTM_RES_LOCAL_MSB_OFF,PTM Responder Local Clock MSB. For more details. see the PTM section in the Databook." hexmask.long 0x4 0.--31. 1. "PTM_RES_LOCAL_MSB,PTM Responder Local Clock MSB - Upper 32 bits of local timer value. For more details see the PTM section in the Databook. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then.." rgroup.long (0x18+0x418)++0x1F line.long 0x0 "PTM_RES_T2_LSB_OFF,PTM Responder T2 Timestamp LSB. For more details. see the PTM section in the Databook." hexmask.long 0x0 0.--31. 1. "PTM_RES_T2_LSB,PTM Responder T2 Timestamp LSB - Lower 32 bits of the T2 Timestamp value. For more details see the PTM section in the Databook. Note: This register field is sticky." line.long 0x4 "PTM_RES_T2_MSB_OFF,PTM Responder T2 Timestamp MSB. For more details. see the PTM section in the Databook." hexmask.long 0x4 0.--31. 1. "PTM_RES_T2_MSB,PTM Responder T2 Timestamp MSB - Upper 32 bits of the T2 Timestamp value. For more details see the PTM section in the Databook. Note: This register field is sticky." line.long 0x8 "PTM_RES_T2P_LSB_OFF,PTM Responder T2 Previous Timestamp LSB. For more details. see the PTM section in the Databook." hexmask.long 0x8 0.--31. 1. "PTM_RES_T2P_LSB,PTM Responder T2 Previous Timestamp LSB - Lower 32 bits of the previously stored T2 Timestamp value. For more details see the PTM section in the Databook. Note: This register field is sticky." line.long 0xC "PTM_RES_T2P_MSB_OFF,PTM Responder T2 Previous Timestamp MSB. For more details. see the PTM section in the Databook." hexmask.long 0xC 0.--31. 1. "PTM_RES_T2P_MSB,PTM Responder T2 Previous Timestamp MSB - Upper 32 bits of the previously stored T2 Timestamp value. For more details see the PTM section in the Databook. Note: This register field is sticky." line.long 0x10 "PTM_RES_T3_LSB_OFF,PTM Responder T3 Timestamp LSB. For more details. see the PTM section in the Databook." hexmask.long 0x10 0.--31. 1. "PTM_RES_T3_LSB,PTM Responder T3 Timestamp LSB - Lower 32 bits of the T3 Timestamp value. For more details see the PTM section in the Databook. Note: This register field is sticky." line.long 0x14 "PTM_RES_T3_MSB_OFF,PTM Responder T3 Timestamp MSB. For more details. see the PTM section in the Databook." hexmask.long 0x14 0.--31. 1. "PTM_RES_T3_MSB,PTM Responder T3 Timestamp MSB - Upper 32 bits of the T2 Timestamp value. For more details see the PTM section in the Databook. Note: This register field is sticky." line.long 0x18 "PTM_RES_T3P_LSB_OFF,PTM Responder T3 Previous Timestamp LSB. For more details. see the PTM section in the Databook." hexmask.long 0x18 0.--31. 1. "PTM_RES_T3P_LSB,PTM Responder T3 Previous Timestamp LSB - Lower 32 bits of the previously stored T3 Timestamp value. For more details see the PTM section in the Databook. Note: This register field is sticky." line.long 0x1C "PTM_RES_T3P_MSB_OFF,PTM Responder T3 Previous Timestamp MSB. For more details. see the PTM section in the Databook." hexmask.long 0x1C 0.--31. 1. "PTM_RES_T3P_MSB,PTM Responder T3 Previous Timestamp MSB - Upper 32 bits of the previously stored T3 Timestamp value. For more details see the PTM section in the Databook. Note: This register field is sticky." group.long (0x38+0x418)++0x7 line.long 0x0 "PTM_RES_TX_LATENCY_OFF,PTM Responder TX Latency. For more details. see the PTM section in the Databook." hexmask.long.tbyte 0x0 12.--31. 1. "RSVDP_12,Reserved for future use." hexmask.long.word 0x0 0.--11. 1. "PTM_RES_TX_LATENCY,PTM Responder TX Latency - Responder Transmit path latency (12 bit wide). For more details see the PTM section in the Databook. Note: This register field is sticky." line.long 0x4 "PTM_RES_RX_LATENCY_OFF,PTM Responder RX Latency. For more details. see the PTM section in the Databook." hexmask.long.tbyte 0x4 12.--31. 1. "RSVDP_12,Reserved for future use." hexmask.long.word 0x4 0.--11. 1. "PTM_RES_RX_LATENCY,PTM Responder RX Latency - Responder Receive path latency (12 bit wide). For more details see the PTM section in the Databook. Note: This register field is sticky." rgroup.long (0x40+0x418)++0x3 line.long 0x0 "PTM_RES_NOM_CLOCK_T_OFF,PTM Responder Nominal Clock Period. For more details. see the PTM section in the Databook." hexmask.long.byte 0x0 24.--31. 1. "RSVDP_24,Reserved for future use." hexmask.long.byte 0x0 16.--23. 1. "PTM_RES_NOM_CLOCK_T_INT,PTM Responder Nominal Clock Period Integral - Integral part of the nominal PTM local clock period in nanoseconds. For more details see the PTM section in the Databook. Note: This register field is sticky." hexmask.long.word 0x0 0.--15. 1. "PTM_RES_NOM_CLOCK_T_FRAC,PTM Responder Nominal Clock Period Fractional - Fractional part of the nominal PTM local clock period. LSB is 1/(2^16) nanoseconds. For more details see the PTM section in the Databook. Note: This register field is sticky." group.long (0x44+0x418)++0x3 line.long 0x0 "PTM_RES_SCALED_CLOCK_T_OFF,PTM Responder Scaled Clock Period. For more details. see the PTM section in the Databook." bitfld.long 0x0 31. "PTM_RES_SCALED_CLOCK_T_EN,PTM Responder Scaled Clock Period Enable - Use the programmed scaled PTM clock period rather than the nominal values. This bit is cleared when the core_clk rate starts to change and can only be set when the clock period change.." "0,1" hexmask.long.byte 0x0 24.--30. 1. "RSVDP_24,Reserved for future use." hexmask.long.byte 0x0 16.--23. 1. "PTM_RES_SCALED_CLOCK_T_INT,PTM Responder Scaled Clock Period Integral - Integral part of the nominal PTM local clock period in nanoseconds. For more details see the PTM section in the Databook. Note: This register field is sticky." newline hexmask.long.word 0x0 0.--15. 1. "PTM_RES_SCALED_CLOCK_T_FRAC,PTM Responder Scaled Clock Period Fractional - Fractional part of the nominal PTM local clock period. LSB is 1/(2^16) nanoseconds. For more details see the PTM section in the Databook. Note: This register field is sticky." tree.end tree "PF0_PM_CAP (PF PCI Power Management Capability Structure)" group.long (0x0+0x40)++0x7 line.long 0x0 "CAP_ID_NXT_PTR_REG,Power Management Capabilities Register." hexmask.long.byte 0x0 27.--31. 1. "PME_SUPPORT,PME_Support. This 5-bit field indicates the power states in which the function may generate a PME and/or forward PME messages. A value of 0b for any bit indicates that the function is not capable of asserting PME while in that power state. -.." bitfld.long 0x0 26. "D2_SUPPORT,D2_Support. If this bit is set this function supports the D2 Power Management state. Functions that do not support D2 must always return a value of 0b for this bit. Note: The access attributes of this field are as follows: - Wire: No access." "0,1" bitfld.long 0x0 25. "D1_SUPPORT,D1_Support. If this bit is set this function supports the D1 Power Management state. Functions that do not support D1 must always return a value of 0b for this bit. Note: The access attributes of this field are as follows: - Wire: No access." "0,1" bitfld.long 0x0 22.--24. "AUX_CURR,Aux_Current. This 3 bit field reports the Vaux auxiliary current requirements for the function. If this function implements the Data Register the controller hardwires this field to 000b. If PME_Support is 0 xxxxb (PME assertion from D3cold is.." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 21. "DSI,Device Specific Initialization. The DSI bit indicates whether special initialization of this function is required. When set indicates that the function requires a device specific initialization sequence following a transition to the D0uninitialized.." "0,1" bitfld.long 0x0 20. "PME_IMM_READI_RETURN_DO,Immediate_Readiness_on_Return_to_D0. - If this bit is a '1' this function is guaranteed to be ready to successfully complete valid accesses immediately after being set to D0. These accesses include configuration cycles and if.." "0,1" rbitfld.long 0x0 19. "PME_CLK,PME Clock. Does not apply to PCI Express the controller hardwires it to 0b. Note: This register field is sticky." "0,1" bitfld.long 0x0 16.--18. "PM_SPEC_VER,Version. This field provides the Power Management specification version. The controller hardwires this field to 011b for functions compliant to PCI Express Base Specification Revision 4.0 Version 1.0>. Note: The access attributes of this.." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x0 8.--15. 1. "PM_NEXT_POINTER,Next Capability Pointer. This field provides an offset into the function's configuration space pointing to the location of next item in the capabilities list. If there are no additional items in the capabilities list this field is set to.." hexmask.long.byte 0x0 0.--7. 1. "PM_CAP_ID,Capability ID. This field returns 01h to indicate that this is the PCI Power Management Capability. Each function may have only one item in its capability list with Capability ID set to 01h." line.long 0x4 "CON_STATUS_REG,Power Management Control and Status Register. This register is used to manage the PCI function's power management state as well as to enable/monitor PMEs." hexmask.long.byte 0x4 24.--31. 1. "DATA_REG_ADD_INFO,Data. This field is used to report the state dependent data requested by the Data_Select field. The value of this field is scaled by the value reported by the Data_Scale field." rbitfld.long 0x4 23. "BUS_PWR_CLK_CON_EN,Bus Power/Clock Control Enable. For a description of this standard PCIe register field see the PCI Express Base Specification." "0,1" rbitfld.long 0x4 22. "B2_B3_SUPPORT,B2B3 Support for D3hot. For a description of this standard PCIe register field see the PCI Express Base Specification." "0,1" hexmask.long.byte 0x4 16.--21. 1. "RSVDP_16,Reserved for future use." newline bitfld.long 0x4 15. "PME_STATUS,PME_Status. This bit is set when the function normally generates a PME signal. The value of this bit is not affected by the value of the PME_En bit. If PME_Support bit 31 of the Power Management Capabilities register is clear this bit is.." "0,1" rbitfld.long 0x4 13.--14. "DATA_SCALE,Data_Scale. This field indicates the scaling factor to be used when interpreting the value of the Data field. The value and meaning of this field varies depending on which data value has been selected by the Data_Select field. For more details.." "0,1,2,3" hexmask.long.byte 0x4 9.--12. 1. "DATA_SELECT,Data_Select. This 4-bit field is used to select which data is to be reported through the Data and Data_Scale field. If the Data field is not implemented this field must be hardwired to 0000b." bitfld.long 0x4 8. "PME_ENABLE,PME_En. - When set the function is permitted to generate a PME. - When clear the function is not permitted to generate a PME. If PME_Support is 1 xxxxb (PME generation from D3cold) or the function consumes Aux power and Aux power is.." "0,1" newline hexmask.long.byte 0x4 4.--7. 1. "RSVDP_4,Reserved for future use." bitfld.long 0x4 3. "NO_SOFT_RST,No_Soft_Reset. This bit indicates the state of the function after writing the PowerState field to transition the function from D3hot to D0. - When set this transition preserves internal function state. The function is in D0Active and no.." "0,1" rbitfld.long 0x4 2. "RSVDP_2,Reserved for future use." "0,1" bitfld.long 0x4 0.--1. "POWER_STATE,PowerState. This 2-bit field is used both to determine the current power state of a function and to set the function into a new power state. The definition of the field values is given below. You can write to this register; however the.." "D0,D1,D2,D3hot" tree.end tree "PF0_PCIE_CAP (PF PCI Express Capability Structure)" group.long (0x0+0x70)++0x33 line.long 0x0 "PCIE_CAP_ID_PCIE_NEXT_CAP_PTR_PCIE_CAP_REG,PCI Express Capabilities. ID. Next Pointer Register." rbitfld.long 0x0 31. "RSVDP_31,Reserved for future use." "0,1" rbitfld.long 0x0 30. "RSVD,Reserved." "0,1" newline hexmask.long.byte 0x0 25.--29. 1. "PCIE_INT_MSG_NUM,PCIE Interrupt Message Number. For a description of this standard PCIe register field see the PCI Express Base Specification. Interrupt Message Number. This field indicates which MSI/MSI-X vector is used for the interrupt message.." bitfld.long 0x0 24. "PCIE_SLOT_IMP,Slot Implemented. When set this bit indicates that the Link associated with this Port is connected to a slot (as compared to being connected to a system-integrated device or being disabled). This bit is valid for Downstream Ports. This bit.." "0,1" newline hexmask.long.byte 0x0 20.--23. 1. "PCIE_DEV_PORT_TYPE,Device/Port Type. Indicates the specific type of this PCI Express function. Note: Different functions in a Multi-Function Device can generally be of different types. Defined encodings for functions that implement a Type 00h PCI.." hexmask.long.byte 0x0 16.--19. 1. "PCIE_CAP_REG,Capability Version. Indicates PCI-SIG defined PCI Express Capability structure version number. A version of the specification that changes the PCI Express Capability structure in a way that is not otherwise identifiable (for example through.." newline hexmask.long.byte 0x0 8.--15. 1. "PCIE_CAP_NEXT_PTR,Next Capability Pointer. This field contains the offset to the next PCI Capability structure or 00h if no other items exist in the linked list of Capabilities. Note: The access attributes of this field are as follows: - Wire: No access." hexmask.long.byte 0x0 0.--7. 1. "PCIE_CAP_ID,Capability ID. Indicates the PCI Express Capability structure. This field must return a Capability ID of 10h indicating that this is a PCI Express Capability structure." line.long 0x4 "DEVICE_CAPABILITIES_REG,Device Capabilities Register. The Device Capabilities register identifies PCI Express device function specific capabilities." hexmask.long.word 0x4 16.--31. 1. "RSVDP_16,Reserved for future use." bitfld.long 0x4 15. "PCIE_CAP_ROLE_BASED_ERR_REPORT,Role-Based Error Reporting. When set this bit indicates that the function implements the functionality originally defined in the Error Reporting ECN for PCI Express Base Specification Revision 1.0a and later incorporated.." "0,1" newline hexmask.long.word 0x4 6.--14. 1. "RSVDP_6,Reserved for future use." bitfld.long 0x4 5. "PCIE_CAP_EXT_TAG_SUPP,Extended Tag Field Supported. This bit in combination with the 10-Bit Tag Requester Supported bit in the Device Capabilities 2 register indicates the maximum supported size of the Tag field as a Requester. This bit must be set if.." "0,1" newline bitfld.long 0x4 3.--4. "PCIE_CAP_PHANTOM_FUNC_SUPPORT,Phantom Functions Supported. This field indicates the support for use of unclaimed function numbers to extend the number of outstanding transactions allowed by logically combining unclaimed function numbers (called Phantom.." "0,1,2,3" bitfld.long 0x4 0.--2. "PCIE_CAP_MAX_PAYLOAD_SIZE,Max_Payload_Size Supported. This field indicates the maximum payload size that the function can support for TLPs. Defined encodings are: - 000b: 128 bytes max payload size - 001b: 256 bytes max payload size - 010b: 512 bytes max.." "0,1,2,3,4,5,6,7" line.long 0x8 "DEVICE_CONTROL_DEVICE_STATUS,Device Control and Device Status Register. This register controls PCI Express device specific parameters and provides information about PCI Express device (function) specific parameters." hexmask.long.word 0x8 22.--31. 1. "RSVDP_22,Reserved for future use." rbitfld.long 0x8 21. "PCIE_CAP_TRANS_PENDING,Transactions Pending. Endpoints: When set this bit indicates that the function has issued Non-Posted Requests that have not been completed. A Function reports this bit cleared only when all outstanding Non-Posted Requests have.." "0,1" newline rbitfld.long 0x8 20. "PCIE_CAP_AUX_POWER_DETECTED,AUX Power Detected. Functions that require Aux power report this bit as set if Aux power is detected by the function. This bit is derived by sampling the sys_aux_pwr_det input." "0,1" bitfld.long 0x8 19. "PCIE_CAP_UNSUPPORTED_REQ_DETECTED,Unsupported Request Detected. This bit indicates that the function received an Unsupported Request. Errors are logged in this register regardless of whether error reporting is enabled or not in the Device Control.." "0,1" newline bitfld.long 0x8 17. "PCIE_CAP_NON_FATAL_ERR_DETECTED,Non-Fatal Error Detected. This bit indicates status of Non-fatal errors detected. Errors are logged in this register regardless of whether error reporting is enabled or not in the Device Control register. For a.." "0,1" bitfld.long 0x8 12.--14. "PCIE_CAP_MAX_READ_REQ_SIZE,Max_Read_Request_Size. This field sets the maximum Read Request size for the function as a Requester. The function must not generate Read Requests with a size exceeding the set value. Defined encodings for this field are: -.." "0,1,2,3,4,5,6,7" newline rbitfld.long 0x8 11. "PCIE_CAP_EN_NO_SNOOP,Enable No Snoop. If this bit is set the function is permitted to Set the No Snoop bit in the Requester Attributes of transactions it initiates that do not require hardware enforced cache coherency (see section 2.2.6.5 in PCI Express.." "0,1" bitfld.long 0x8 10. "PCIE_CAP_AUX_POWER_PM_EN,Aux Power PM Enable. This bit is derived by sampling the sys_aux_pwr_det input. When set this bit enables a function to draw Aux power independent of PME Aux power. Functions that require Aux power on legacy operating systems.." "0,1" newline rbitfld.long 0x8 9. "PCIE_CAP_PHANTOM_FUNC_EN,Phantom Functions Enable. This bit in combination with the 10-Bit Tag Requester Enable bit in the Device Control 2 register determines how many Tag field bits a Requester is permitted to use. When the 10-Bit Tag Requester.." "0,1" rbitfld.long 0x8 8. "PCIE_CAP_EXT_TAG_EN,Extended Tag Field Enable. This bit in combination with the 10-Bit Tag Requester Enable bit in the Device Control 2 register determines how many Tag field bits a Requester is permitted to use. When the 10-Bit Tag Requester Enable.." "0,1" newline bitfld.long 0x8 5.--7. "PCIE_CAP_MAX_PAYLOAD_SIZE_CS,Max_Payload_Size. This field sets maximum TLP payload size for the Function. As a Receiver the Function must handle TLPs as large as the set value. As a Transmitter the Function must not generate TLPs exceeding the set.." "0,1,2,3,4,5,6,7" bitfld.long 0x8 4. "PCIE_CAP_EN_REL_ORDER,Enable Relaxed Ordering. If this bit is set the function is permitted to set the Relaxed Ordering bit in the Attributes field of transactions it initiates that do not require strong write ordering (for more details see section.." "0,1" newline bitfld.long 0x8 3. "PCIE_CAP_UNSUPPORT_REQ_REP_EN,Unsupported Request Reporting Enable. This bit in conjunction with other bits controls the signaling of Unsupported Request Errors by sending error Messages (for more details see section 6.2.5 and section 6.2.6 of PCI.." "0,1" bitfld.long 0x8 2. "PCIE_CAP_FATAL_ERR_REPORT_EN,Fatal Error Reporting Enable. This bit in conjunction with other bits controls sending ERR_FATAL Messages (for more details see section 6.2.5 and section 6.2.6 of of PCI Express Base Specification). For a Multi-Function.." "0,1" newline bitfld.long 0x8 1. "PCIE_CAP_NON_FATAL_ERR_REPORT_EN,Non-Fatal Error Reporting Enable. This bit in conjunction with other bits controls sending ERR_NONFATAL Messages (for more details see section 6.2.5 and Section 6.2.6 of PCI Express Base Specification). For a.." "0,1" bitfld.long 0x8 0. "PCIE_CAP_CORR_ERR_REPORT_EN,Correctable Error Reporting Enable. This bit in conjunction with other bits controls sending ERR_COR Messages (for more details see section 6.2.5 section 6.2.6 and section 6.2.10.2 of PCI Express Base Specification). For.." "0,1" line.long 0xC "LINK_CAPABILITIES_REG,Link Capabilities Register. The Link Capabilities register identifies PCI Express Link specific capabilities." hexmask.long.byte 0xC 24.--31. 1. "PCIE_CAP_PORT_NUM,Port Number. This field indicates the PCI Express Port number for the given PCI Express Link. Multi-Function Devices associated with an Upstream Port must report the same value in this field for all functions. Note: The access.." rbitfld.long 0xC 23. "RSVDP_23,Reserved for future use." "0,1" newline bitfld.long 0xC 22. "PCIE_CAP_ASPM_OPT_COMPLIANCE,ASPM Optionality Compliance. This bit must be set to 1b in all functions. Components implemented against certain earlier versions of this specification will have this bit set to 0b. Software is permitted to use the value of.." "0,1" bitfld.long 0xC 21. "PCIE_CAP_LINK_BW_NOT_CAP,Link Bandwidth Notification Capability. A value of 1b indicates support for the Link Bandwidth Notification status and interrupt mechanisms. This capability is required for all Root Ports and Switch Downstream Ports supporting.." "0,1" newline rbitfld.long 0xC 20. "PCIE_CAP_DLL_ACTIVE_REP_CAP,Data Link Layer Link Active Reporting Capable. For a Downstream Port the controller hardwires this bit to 1b if the component supports the optional capability of reporting the DL_Active state of the Data Link Control and.." "0,1" bitfld.long 0xC 19. "PCIE_CAP_SURPRISE_DOWN_ERR_REP_CAP,Surprise Down Error Reporting Capable. For a Downstream Port this bit must be set if the component supports the optional capability of detecting and reporting a Surprise Down error condition. For Upstream Ports and.." "0,1" newline rbitfld.long 0xC 18. "PCIE_CAP_CLOCK_POWER_MAN,Clock Power Management. For Upstream Ports a value of 1b in this bit indicates that the component tolerates the removal of any reference clock(s) via the 'clock request' (CLKREQ#) mechanism when the Link is in the L1 and L2/L3.." "0,1" bitfld.long 0xC 15.--17. "PCIE_CAP_L1_EXIT_LATENCY,L1 Exit Latency. This field indicates the L1 exit latency for the given PCI Express Link. The value reported indicates the length of time this Port requires to complete transition from ASPM L1 to L0. If ASPM L1 is not supported.." "0,1,2,3,4,5,6,7" newline bitfld.long 0xC 12.--14. "PCIE_CAP_L0S_EXIT_LATENCY,L0s Exit Latency. This field indicates the L0s exit latency for the given PCI Express Link. The value reported indicates the length of time this Port requires to complete transition from L0s to L0. If L0s is not supported the.." "0,1,2,3,4,5,6,7" bitfld.long 0xC 10.--11. "PCIE_CAP_ACTIVE_STATE_LINK_PM_SUPPORT,Active State Power Management (ASPM) Support. This field indicates the level of ASPM supported on the given PCI Express Link. For more details on ASPM support requirements see section 5.4.1 of PCI Express Base.." "0,1,2,3" newline hexmask.long.byte 0xC 4.--9. 1. "PCIE_CAP_MAX_LINK_WIDTH,Maximum Link Width. This field indicates the maximum Link width (xN - corresponding to N Lanes) implemented by the component. This value is permitted to exceed the number of Lanes routed to the slot (Downstream Port) adapter.." hexmask.long.byte 0xC 0.--3. 1. "PCIE_CAP_MAX_LINK_SPEED,Max Link Speed. This field indicates the maximum Link speed of the associated Port. The encoded value specifies a bit location in the Supported Link Speeds Vector (in the Link Capabilities 2 register) that corresponds to the.." line.long 0x10 "LINK_CONTROL_LINK_STATUS_REG,Link Control and Link Status Register. This register controls and provides information about PCI Express Link specific parameters." bitfld.long 0x10 31. "PCIE_CAP_LINK_AUTO_BW_STATUS,Link Autonomous Bandwidth Status. This bit is set by hardware to indicate that hardware has autonomously changed Link speed or width without the Port transitioning through DL_Down status for reasons other than to attempt to.." "0,1" bitfld.long 0x10 30. "PCIE_CAP_LINK_BW_MAN_STATUS,Link Bandwidth Management Status. This bit is set by hardware to indicate that either of the following has occurred without the Port transitioning through DL_Down status: - A Link retraining has completed following a write of.." "0,1" newline rbitfld.long 0x10 29. "PCIE_CAP_DLL_ACTIVE,Data Link Layer Link Active. This bit indicates the status of the Data Link Control and Management State Machine. It returns a 1b to indicate the DL_Active state 0b otherwise. This bit must be implemented if the Data Link Layer Link.." "0,1" bitfld.long 0x10 28. "PCIE_CAP_SLOT_CLK_CONFIG,Slot Clock Configuration. This bit indicates that the component uses the same physical reference clock that the platform provides on the connector. If the device uses an independent clock irrespective of the presence of a.." "0,1" newline rbitfld.long 0x10 27. "PCIE_CAP_LINK_TRAINING,Link Training. This read-only bit indicates that the Physical Layer LTSSM is in the Configuration or Recovery state or that 1b was written to the Retrain Link bit but Link training has not yet begun. Hardware clears this bit when.." "0,1" rbitfld.long 0x10 26. "RSVDP_26,Reserved for future use." "0,1" newline hexmask.long.byte 0x10 20.--25. 1. "PCIE_CAP_NEGO_LINK_WIDTH,Negotiated Link Width. This field indicates the negotiated width of the given PCI Express Link. Defined encodings are: -00 0001b: x1 -00 0010b: x2 -00 0100b: x4 -00 1000b: x8 -00 1100b: x12 -01 0000b: x16 -10 0000b: x32 All other.." hexmask.long.byte 0x10 16.--19. 1. "PCIE_CAP_LINK_SPEED,Current Link Speed. This field indicates the negotiated Link speed of the given PCI Express Link. The encoded value specifies a bit location in the Supported Link Speeds Vector (in the Link Capabilities 2 register) that corresponds to.." newline bitfld.long 0x10 14.--15. "PCIE_CAP_DRS_SIGNALING_CONTROL,DRS Signaling Control. Indicates the mechanism used to report reception of a DRS message. Must be implemented for Downstream Ports with the DRS Supported bit Set in the Link Capabilities 2 Register. Encodings are: - 00b:.." "0,1,2,3" rbitfld.long 0x10 12.--13. "RSVDP_12,Reserved for future use." "0,1,2,3" newline bitfld.long 0x10 11. "PCIE_CAP_LINK_AUTO_BW_INT_EN,Link Autonomous Bandwidth Management Interrupt Enable. When set this bit enables the generation of an interrupt to indicate that the Link Autonomous Bandwidth Status bit has been set. The write value is gated with the.." "0,1" bitfld.long 0x10 10. "PCIE_CAP_LINK_BW_MAN_INT_EN,Link Bandwidth Management Interrupt Enable. When set this bit enables the generation of an interrupt to indicate that the Link Bandwidth Management Status bit has been set. The write value is gated with the.." "0,1" newline bitfld.long 0x10 9. "PCIE_CAP_HW_AUTO_WIDTH_DISABLE,Hardware Autonomous Width Disable. When set this bit disables hardware from changing the Link width for reasons other than attempting to correct unreliable Link operation by reducing Link width. For a Multi-Function Device.." "0,1" bitfld.long 0x10 8. "PCIE_CAP_EN_CLK_POWER_MAN,Enable Clock Power Management. Applicable only for Upstream Ports and with form factors that support a 'Clock Request' (CLKREQ#) mechanism this bit operates as follows: - 0b: Clock power management is disabled and device must.." "0,1" newline bitfld.long 0x10 7. "PCIE_CAP_EXTENDED_SYNCH,Extended Synch. When set this bit forces the transmission of additional Ordered Sets when exiting the L0s state (see section 4.2.4.5 of PCI Express Base Specification) and when in the Recovery state (see section 4.2.6.4.1 of PCI.." "0,1" bitfld.long 0x10 6. "PCIE_CAP_COMMON_CLK_CONFIG,Common Clock Configuration. When set this bit indicates that this component and the component at the opposite end of this Link are operating with a distributed common reference clock. A value of 0b indicates that this.." "0,1" newline bitfld.long 0x10 5. "PCIE_CAP_RETRAIN_LINK,Retrain Link. A write of 1b to this bit initiates Link retraining by directing the Physical Layer LTSSM to the Recovery state. If the LTSSM is already in Recovery or Configuration re-entering Recovery is permitted but not required." "0,1" bitfld.long 0x10 4. "PCIE_CAP_LINK_DISABLE,Link Disable. This bit disables the Link by directing the LTSSM to the Disabled state when set; this bit is Reserved on Endpoints PCI Express to PCI/PCI-X bridges and Upstream Ports of Switches. Writes to this bit are immediately.." "0,1" newline bitfld.long 0x10 3. "PCIE_CAP_RCB,Read Completion Boundary (RCB). Root Ports: Indicates the RCB value for the Root Port. Refer to section 2.3.1.1 of PCI Express Base Specification for the definition of the parameter RCB. Defined encodings are: - 0b: 64 byte - 1b: 128 byte.." "0,1" rbitfld.long 0x10 2. "RSVDP_2,Reserved for future use." "0,1" newline bitfld.long 0x10 0.--1. "PCIE_CAP_ACTIVE_STATE_LINK_PM_CONTROL,Active State Power Management (ASPM) Control. This field controls the level of ASPM enabled on the given PCI Express Link. See section 5.4.1.3 of PCI Express Base Specification for requirements on when and how to.." "0,1,2,3" line.long 0x14 "SLOT_CAPABILITIES_REG,Slot Capabilities Register. The Slot Capabilities register identifies PCI Express slot specific capabilities." hexmask.long.word 0x14 19.--31. 1. "PCIE_CAP_PHY_SLOT_NUM,Physical Slot Number. This field indicates the physical slot number attached to this Port. This field must be hardware initialized to a value that assigns a slot number that is unique within the chassis regardless of the form.." bitfld.long 0x14 18. "PCIE_CAP_NO_CMD_CPL_SUPPORT,No Command Completed Support. When set this bit indicates that this slot does not generate software notification when an issued command is completed by the Hot-Plug Controller. This bit is only permitted to be set if the.." "0,1" newline bitfld.long 0x14 17. "PCIE_CAP_ELECTROMECH_INTERLOCK,Electromechanical Interlock Present. When set this bit indicates that an Electromechanical Interlock is implemented on the chassis for this slot. Note: The access attributes of this field are as follows: - Wire: No access." "0,1" bitfld.long 0x14 15.--16. "PCIE_CAP_SLOT_POWER_LIMIT_SCALE,Slot Power Limit Scale. Specifies the scale used for the Slot Power Limit Value (for more details see Section 6.9 of PCI Express Base Specification). Range of Values: - 00b: 1.0x - 01b: 0.1x - 10b: 0.01x - 11b: 0.001x.." "0,1,2,3" newline hexmask.long.byte 0x14 7.--14. 1. "PCIE_CAP_SLOT_POWER_LIMIT_VALUE,Slot Power Limit Value. In combination with the Slot Power Limit Scale value specifies the upper limit on power supplied by the slot (for more detais see Section 6.9 of PCI Express Base Specification) or by other means.." bitfld.long 0x14 6. "PCIE_CAP_HOT_PLUG_CAPABLE,Hot-Plug Capable. When set this bit indicates that this slot is capable of supporting hot-plug operations. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then R/W else R" "0,1" newline bitfld.long 0x14 5. "PCIE_CAP_HOT_PLUG_SURPRISE,Hot-Plug Surprise. When set this bit indicates that an adapter present in this slot might be removed from the system without any prior notification. This is a form factor specific capability. This bit is an indication to the.." "0,1" bitfld.long 0x14 4. "PCIE_CAP_POWER_INDICATOR,Power Indicator Present. When set this bit indicates that a Power Indicator is electrically controlled by the chassis for this slot. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if.." "0,1" newline bitfld.long 0x14 3. "PCIE_CAP_ATTENTION_INDICATOR,Attention Indicator Present. When set this bit indicates that an Attention Indicator is electrically controlled by the chassis. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if.." "0,1" bitfld.long 0x14 2. "PCIE_CAP_MRL_SENSOR,MRL Sensor Present. When set this bit indicates that an MRL Sensor is implemented on the chassis for this slot. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then R/W else R" "0,1" newline bitfld.long 0x14 1. "PCIE_CAP_POWER_CONTROLLER,Power Controller Present. When set this bit indicates that a software programmable Power Controller is implemented for this slot/adapter (depending on form factor). Note: The access attributes of this field are as follows: -.." "0,1" bitfld.long 0x14 0. "PCIE_CAP_ATTENTION_INDICATOR_BUTTON,Attention Button Present. When set this bit indicates that an Attention Button for this slot is electrically controlled by the chassis. Note: The access attributes of this field are as follows: - Wire: No access. -.." "0,1" line.long 0x18 "SLOT_CONTROL_SLOT_STATUS,Slot Control and Status Register. This register controls and provides information about PCI Express Slot specific parameters." hexmask.long.byte 0x18 25.--31. 1. "RSVDP_25,Reserved for future use." bitfld.long 0x18 24. "PCIE_CAP_DLL_STATE_CHANGED,Data Link Layer State Changed. This bit is set when the value reported in the Data Link Layer Link Active bit of the Link Status register is changed. In response to a Data Link Layer State Changed event software must read the.." "0,1" newline rbitfld.long 0x18 23. "PCIE_CAP_ELECTROMECH_INTERLOCK_STATUS,Electromechanical Interlock Status. If an Electromechanical Interlock is implemented this bit indicates the status of the Electromechanical Interlock. Defined encodings are: - 0b: Electromechanical Interlock.." "0,1" rbitfld.long 0x18 22. "PCIE_CAP_PRESENCE_DETECT_STATE,Presence Detect State. This bit indicates the presence of an adapter in the slot reflected by the logical 'OR' of the Physical Layer in-band presence detect mechanism and if present any out-of-band presence detect.." "0,1" newline rbitfld.long 0x18 21. "PCIE_CAP_MRL_SENSOR_STATE,MRL Sensor State. This bit reports the status of the MRL sensor if implemented. Defined encodings are: - 0b: MRL Closed - 1b: MRL Open" "0,1" bitfld.long 0x18 20. "PCIE_CAP_CMD_CPLD,Command Completed. If Command Completed notification is supported (if the No Command Completed Support bit in the Slot Capabilities register is 0b) this bit is set when a hot-plug command has completed and the Hot-Plug Controller is.." "0,1" newline bitfld.long 0x18 19. "PCIE_CAP_PRESENCE_DETECTED_CHANGED,Presence Detect Changed. This bit is set when the value reported in the Presence Detect State bit is changed." "0,1" bitfld.long 0x18 18. "PCIE_CAP_MRL_SENSOR_CHANGED,MRL Sensor Changed. If an MRL sensor is implemented this bit is set when a MRL Sensor state change is detected. If an MRL sensor is not implemented this bit must not be set." "0,1" newline bitfld.long 0x18 17. "PCIE_CAP_POWER_FAULT_DETECTED,Power Fault Detected. If a Power Controller that supports power fault detection is implemented this bit issSet when the Power Controller detects a power fault at this slot. Note: Depending on hardware capability it is.." "0,1" bitfld.long 0x18 16. "PCIE_CAP_ATTENTION_BUTTON_PRESSED,Attention Button Pressed. If an Attention Button is implemented this bit is set when the attention button is pressed. If an Attention Button is not supported this bit must not be set." "0,1" newline rbitfld.long 0x18 14.--15. "RSVDP_14,Reserved for future use." "0,1,2,3" bitfld.long 0x18 12. "PCIE_CAP_DLL_STATE_CHANGED_EN,Data Link Layer State Changed Enable. If the Data Link Layer Link Active Reporting capability is 1b this bit enables software notification when Data Link Layer Link Active bit is changed. If the Data Link Layer Link Active.." "0,1" newline bitfld.long 0x18 11. "PCIE_CAP_ELECTROMECH_INTERLOCK_CTRL,Electromechanical Interlock Control. If an Electromechanical Interlock is implemented a write of 1b to this bit causes the state of the interlock to toggle. A write of 0b to this bit has no effect. A read of this bit.." "0,1" bitfld.long 0x18 10. "PCIE_CAP_POWER_CONTROLLER_CTRL,Power Controller Control. If a Power Controller is implemented this bit when written sets the power state of the slot per the defined encodings. Reads of this bit must reflect the value from the latest write even if the.." "0,1" newline bitfld.long 0x18 8.--9. "PCIE_CAP_POWER_INDICATOR_CTRL,Power Indicator Control. If a Power Indicator is implemented writes to this field set the Power Indicator to the written state. Reads of this field must reflect the value from the latest write even if the corresponding.." "0,1,2,3" bitfld.long 0x18 6.--7. "PCIE_CAP_ATTENTION_INDICATOR_CTRL,Attention Indicator Control. If an Attention Indicator is implemented writes to this field set the Attention Indicator to the written state. Reads of this field must reflect the value from the latest write even if the.." "0,1,2,3" newline bitfld.long 0x18 5. "PCIE_CAP_HOT_PLUG_INT_EN,Hot-Plug Interrupt Enable. When set this bit enables generation of an interrupt on enabled hot-plug events. If the Hot Plug Capable bit in the Slot Capabilities register is clear this bit is permitted to be read-only with a.." "0,1" bitfld.long 0x18 4. "PCIE_CAP_CMD_CPL_INT_EN,Command Completed Interrupt Enable. If Command Completed notification is supported (if the No Command Completed Support bit in the Slot Capabilities register is 0b) when set this bit enables software notification when a hot-plug.." "0,1" newline bitfld.long 0x18 3. "PCIE_CAP_PRESENCE_DETECT_CHANGE_EN,Presence Detect Changed Enable. When set this bit enables software notification on a presence detect changed event (for more details see Section 6.7.3 of PCI Express Base Specification). If the Hot-Plug Capable bit in.." "0,1" bitfld.long 0x18 2. "PCIE_CAP_MRL_SENSOR_CHANGED_EN,MRL Sensor Changed Enable. When set this bit enables software notification on a MRL sensor changed event (for more details see Section 6.7.3 of PCI Express Base Specification). If the MRL Sensor Present bit in the Slot.." "0,1" newline bitfld.long 0x18 1. "PCIE_CAP_POWER_FAULT_DETECTED_EN,Power Fault Detected Enable. When set this bit enables software notification on a power fault event (for more details see Section 6.7.3 of PCI Express Base Specification). If a Power Controller that supports power fault.." "0,1" bitfld.long 0x18 0. "PCIE_CAP_ATTENTION_BUTTON_PRESSED_EN,Attention Button Pressed Enable. When set to 1b this bit enables software notification on an attention button pressed event (for more details see Section 6.7.3 of PCI Express Base Specification). If the Attention.." "0,1" line.long 0x1C "ROOT_CONTROL_ROOT_CAPABILITIES_REG,Root Control and Capabilities Register. This register controls PCI Express Root Complex specific parameters and identifies PCI Express Root Port specific capabilities." hexmask.long.word 0x1C 17.--31. 1. "RSVDP_17,Reserved for future use." bitfld.long 0x1C 16. "PCIE_CAP_CRS_SW_VISIBILITY,CRS Software Visibility Capable. For a description of this standard PCIe register field see the PCI Express Base Specification. CRS Software Visibility. When set this bit indicates that the Root Port is capable of returning.." "0,1" newline hexmask.long.word 0x1C 5.--15. 1. "RSVDP_5,Reserved for future use." bitfld.long 0x1C 4. "PCIE_CAP_CRS_SW_VISIBILITY_EN,CRS Software Visibility Enable. When set this bit enables the Root Port to return Configuration Request Retry Status (CRS) Completion Status to software (for more details see section 2.3.1 of PCI Express Base.." "0,1" newline bitfld.long 0x1C 3. "PCIE_CAP_PME_INT_EN,PME Interrupt Enable. When set this bit enables PME interrupt generation upon receipt of a PME Message as reflected in the PME Status bit (for more details see Table 7-29 of PCI Express Base Specification). A PME interrupt is also.." "0,1" bitfld.long 0x1C 2. "PCIE_CAP_SYS_ERR_ON_FATAL_ERR_EN,System Error on Fatal Error Enable. If set this bit indicates that a System Error should be generated if a Fatal error (ERR_FATAL) is reported by any of the devices in the Hierarchy Domain associated with this Root Port.." "0,1" newline bitfld.long 0x1C 1. "PCIE_CAP_SYS_ERR_ON_NON_FATAL_ERR_EN,System Error on Non-Fatal Error Enable. If set this bit indicates that a System Error should be generated if a Non-fatal error (ERR_NONFATAL) is reported by any of the devices in the Hierarchy Domain associated with.." "0,1" bitfld.long 0x1C 0. "PCIE_CAP_SYS_ERR_ON_CORR_ERR_EN,System Error on Correctable Error Enable. If set this bit indicates that a System Error should be generated if a correctable error (ERR_COR) is reported by any of the devices in the Hierarchy Domain associated with this.." "0,1" line.long 0x20 "ROOT_STATUS_REG,Root Status Register. The Root Status register provides information about PCI Express device specific parameters." hexmask.long.word 0x20 18.--31. 1. "RSVDP_18,Reserved for future use." rbitfld.long 0x20 17. "PCIE_CAP_PME_PENDING,PME Pending. This bit indicates that another PME is pending when the PME Status bit is s et. When the PME Status bit is cleared by software; the PME is delivered by hardware by setting the PME Status bit again and updating the PME.." "0,1" newline bitfld.long 0x20 16. "PCIE_CAP_PME_STATUS,PME Status. This bit indicates that PME was asserted by the PME Requester indicated in the PME Requester ID field. Subsequent PMEs are kept pending until the status register is cleared by software by writing a 1b." "0,1" hexmask.long.word 0x20 0.--15. 1. "PCIE_CAP_PME_REQ_ID,PME Requester ID. This field indicates the PCI Requester ID of the last PME Requester. This field is only valid when the PME Status bit is set." line.long 0x24 "DEVICE_CAPABILITIES2_REG,Device Capabilities 2 Register." bitfld.long 0x24 31. "PCIE_CAP_FRS_SUPPORTED,FRS Supported. When set indicates support for the optional Function Readiness Status (FRS) capability. Must be set for all Functions that support generation or reception capabilities of FRS Messages. Must not be set by Switch.." "0,1" hexmask.long.byte 0x24 24.--30. 1. "RSVDP_24,Reserved for future use." newline rbitfld.long 0x24 17. "PCIE_CAP2_10_BIT_TAG_REQ_SUPPORT,10-Bit Tag Requester Supported. If this bit is set the Function supports 10-Bit Tag Requester capability; otherwise the Function does not. This bit must not be set if the 10-Bit Tag Completer Supported bit is clear." "0,1" rbitfld.long 0x24 16. "PCIE_CAP2_10_BIT_TAG_COMP_SUPPORT,10-Bit Tag Completer Supported. If this bit is set the Function supports 10-Bit Tag Completer capability; otherwise the Function does not. For more details see section 2.2.6.2. of PCI Express Base Specification." "0,1" newline rbitfld.long 0x24 13. "PCIE_CAP_TPH_CMPLT_SUPPORT_1,TPH Completer Supported Bit 1." "0,1" rbitfld.long 0x24 12. "PCIE_CAP_TPH_CMPLT_SUPPORT_0,TPH Completer Supported Bit 0. Value of this bit along with TPH Completer Supported Bit 1 indicates Completer support for TPH or Extended TPH. Applicable only to Root Ports and Endpoints. For all other Functions this field.." "0,1" newline bitfld.long 0x24 11. "PCIE_CAP_LTR_SUPP,LTR Mechanism Supported. A value of 1b indicates support for the optional Latency Tolerance Reporting (LTR) mechanism. Root Ports Switches and Endpoints are permitted to implement this capability. For a Multi-Function Device associated.." "0,1" rbitfld.long 0x24 10. "PCIE_CAP_NO_RO_EN_PR2PR_PAR,No RO-enabled PR-PR Passing. If this bit is set the routing element never carries out the passing permitted by Table 2-39 of PCI Express Base Specification entry A2b that is associated with the Relaxed Ordering Attribute.." "0,1" newline rbitfld.long 0x24 9. "PCIE_CAP_128_CAS_CPL_SUPP,128-bit CAS Completer Supported. Applicable to Functions with Memory Space BARs as well as all Root Ports; must be 0b otherwise. This bit must be set to 1b if the Function supports this optional capability. For more details see.." "0,1" rbitfld.long 0x24 8. "PCIE_CAP_64_ATOMIC_CPL_SUPP,64-bit AtomicOp Completer Supported. Applicable to Functions with Memory Space BARs as well as all Root Ports; must be 0b otherwise. Includes FetchAdd Swap and CAS AtomicOps. This bit must be set to 1b if the Function.." "0,1" newline rbitfld.long 0x24 7. "PCIE_CAP_32_ATOMIC_CPL_SUPP,32-bit AtomicOp Completer Supported. Applicable to Functions with Memory Space BARs as well as all Root Ports; must be 0b otherwise. Includes FetchAdd Swap and CAS AtomicOps. This bit must be set to 1b if the Function.." "0,1" rbitfld.long 0x24 6. "PCIE_CAP_ATOMIC_ROUTING_SUPP,AtomicOp Routing Supported. Applicable only to Switch Upstream Ports Switch Downstream Ports and Root Ports; must be 0b for other Function types. This bit must be set to 1b if the Port supports this optional capability. For.." "0,1" newline rbitfld.long 0x24 5. "PCIE_CAP_ARI_FORWARD_SUPPORT,ARI Forwarding Supported. Applicable only to Switch Downstream Ports and Root Ports; must be 0b for other Function types. This bit must be set to 1b if a Switch Downstream Port or Root Port supports this optional capability." "0,1" rbitfld.long 0x24 4. "PCIE_CAP_CPL_TIMEOUT_DISABLE_SUPPORT,Completion Timeout Disable Supported. A value of 1b indicates support for the Completion Timeout Disable mechanism. The Completion Timeout Disable mechanism is required for Endpoints that issue Requests on their own.." "0,1" newline hexmask.long.byte 0x24 0.--3. 1. "PCIE_CAP_CPL_TIMEOUT_RANGE,Completion Timeout Ranges Supported. This field indicates device Function support for the optional Completion Timeout programmability mechanism. This mechanism allows system software to modify the Completion Timeout value. This.." line.long 0x28 "DEVICE_CONTROL2_DEVICE_STATUS2_REG,Device Control 2 and Status 2 Register." bitfld.long 0x28 10. "PCIE_CAP_LTR_EN,LTR Mechanism Enable. When set to 1b this bit enables Upstream Ports to send LTR messages and Downstream Ports to process LTR Messages. For a Multi-Function Device associated with an Upstream Port of a device that implements LTR the bit.." "0,1" rbitfld.long 0x28 5. "PCIE_CAP_ARI_FORWARD_SUPPORT_CS,ARI Forwarding Enable. When set the Downstream Port disables its traditional Device Number field being 0 enforcement when turning a Type 1 Configuration Request into a Type 0 Configuration Request permitting access to.." "0,1" newline bitfld.long 0x28 4. "PCIE_CAP_CPL_TIMEOUT_DISABLE,Completion Timeout Disable. When set this bit disables the Completion Timeout mechanism. This bit is required for all Functions that support the Completion Timeout Disable Capability. Functions that do not support this.." "0,1" hexmask.long.byte 0x28 0.--3. 1. "PCIE_CAP_CPL_TIMEOUT_VALUE,Completion Timeout Value. In device Functions that support Completion Timeout programmability this field allows system software to modify the Completion Timeout value. This field is applicable to Root Ports Endpoints that.." line.long 0x2C "LINK_CAPABILITIES2_REG,Link Capabilities 2 Register." bitfld.long 0x2C 31. "DRS_SUPPORTED,DRS Supported. When set indicates support for the optional Device Readiness Status (DRS) capability. Must be Set in Downstream Ports that support DRS. Must be Set in Downstream Ports that support FRS. For Upstream Ports that support DRS.." "0,1" hexmask.long.byte 0x2C 25.--30. 1. "RSVDP_25,Reserved for future use." newline hexmask.long.word 0x2C 9.--22. 1. "RSVDP_9,Reserved for future use." rbitfld.long 0x2C 8. "PCIE_CAP_CROSS_LINK_SUPPORT,Crosslink Supported. When set to 1b this bit indicates that the associated Port supports crosslinks (for more details see section 4.2.6.3.1 of PCI Express Base Specification). When set to 0b on a Port that supports Link.." "0,1" newline hexmask.long.byte 0x2C 1.--7. 1. "PCIE_CAP_SUPPORT_LINK_SPEED_VECTOR,Supported Link Speeds Vector. This field indicates the supported Link speed(s) of the associated Port. For each bit a value of 1b indicates that the corresponding Link speed is supported; otherwise the Link speed is.." rbitfld.long 0x2C 0. "RSVDP_0,Reserved for future use." "0,1" line.long 0x30 "LINK_CONTROL2_LINK_STATUS2_REG,Link Control 2 and Status 2 Register." bitfld.long 0x30 31. "DRS_MESSAGE_RECEIVED,DRS Message Received. This bit must be set whenever the Port receives a DRS Message. This bit must be cleared in DL_Down. This bit must be implemented in any Downstream Port where the DRS Supported bit is Set in the Link Capabilities.." "0,1" rbitfld.long 0x30 28.--30. "DOWNSTREAM_COMPO_PRESENCE,Downstream Component Presence. This field indicates the presence and DRS status for the Downstream Component if any connected to the Link; defined values are: - 000b: Link Down - Presence Not Determined - 001b: Link Down -.." "0,1,2,3,4,5,6,7" newline rbitfld.long 0x30 26.--27. "RSVDP_26,Reserved for future use." "0,1,2,3" bitfld.long 0x30 21. "PCIE_CAP_LINK_EQ_REQ,Link Equalization Request 8.0 GT/s. This bit is set by hardware to request the 8.0 GT/s Link equalization process to be performed on the Link. For more details see sections 4.2.3 and 4.2.6.4.2 of PCI Express Base Specification. For.." "0,1" newline rbitfld.long 0x30 20. "PCIE_CAP_EQ_CPL_P3,EEqualization 8.0 GT/s Phase 3 Successful. When set to 1b this bit indicates that Phase 3 of the 8.0 GT/s Transmitter Equalization procedure has successfully completed. Details of the Transmitter Equalization process and when this bit.." "0,1" rbitfld.long 0x30 19. "PCIE_CAP_EQ_CPL_P2,Equalization 8.0 GT/s Phase 2 Successful. When set to 1b this bit indicates that Phase 2 of the 8.0 GT/s Transmitter Equalization procedure has successfully completed. Details of the Transmitter Equalization process and when this bit.." "0,1" newline rbitfld.long 0x30 18. "PCIE_CAP_EQ_CPL_P1,Equalization 8.0 GT/s Phase 1 Successful. When set to 1b this bit indicates that Phase 1 of the 8.0 GT/s Transmitter Equalization procedure has successfully completed. Details of the Transmitter Equalization process and when this bit.." "0,1" rbitfld.long 0x30 17. "PCIE_CAP_EQ_CPL,Equalization 8.0 GT/s Complete. When set to 1b this bit indicates that the Transmitter Equalization procedure at the 8.0 GT/s data rate has completed. Details of the Transmitter Equalization process and when this bit needs to be set to.." "0,1" newline rbitfld.long 0x30 16. "PCIE_CAP_CURR_DEEMPHASIS,Current De-emphasis Level. When the Link is operating at 5.0 GT/s speed this bit reflects the level of de-emphasis. Encodings: - 1b: -3.5 dB - 0b: -6 dB The value in this bit is undefined when the Link is not operating at 5.0.." "0,1" hexmask.long.byte 0x30 12.--15. 1. "PCIE_CAP_COMPLIANCE_PRESET,Compliance Preset/De-emphasis. For 8.0 GT/s and higher Data Rate: This field sets the Transmitter Preset in Polling.Compliance state if the entry occurred due to the Enter Compliance bit being 1b. The encodings are defined in.." newline bitfld.long 0x30 11. "PCIE_CAP_COMPLIANCE_SOS,Compliance SOS. When set to 1b the LTSSM is required to send SKP Ordered Sets between sequences when sending the Compliance Pattern or Modified Compliance Pattern. For a Multi-Function Device associated with an Upstream Port the.." "0,1" bitfld.long 0x30 10. "PCIE_CAP_ENTER_MODIFIED_COMPLIANCE,Enter Modified Compliance. When this bit is set to 1b the device transmits Modified Compliance Pattern if the LTSSM enters Polling.Compliance substate. Components that support only the 2.5 GT/s speed are permitted to.." "0,1" newline bitfld.long 0x30 7.--9. "PCIE_CAP_TX_MARGIN,Transmit Margin - This field controls the value of the non-deemphasized voltage level at the Transmitter pins. This field is reset to 000b on entry to the LTSSM Polling.Configuration substate (see Chapter 4 of PCI Express Base.." "0,1,2,3,4,5,6,7" bitfld.long 0x30 6. "PCIE_CAP_SEL_DEEMPHASIS,Selectable De-emphasis. When the Link is operating at 5.0 GT/s speed this bit is used to control the transmit de-emphasis of the link in specific situations. For more details see section 4.2.6 of PCI Express Base Specification." "0,1" newline bitfld.long 0x30 5. "PCIE_CAP_HW_AUTO_SPEED_DISABLE,Hardware Autonomous Speed Disable. When set this bit disables hardware from changing the Link speed for device-specific reasons other than attempting to correct unreliable Link operation by reducing Link speed. Initial.." "0,1" bitfld.long 0x30 4. "PCIE_CAP_ENTER_COMPLIANCE,Enter Compliance. Software is permitted to force a Link to enter Compliance mode (at the speed indicated in the Target Link Speed field and the de-emphasis/preset level indicated by the Compliance Preset/De-emphasis field) by.." "0,1" newline hexmask.long.byte 0x30 0.--3. 1. "PCIE_CAP_TARGET_LINK_SPEED,Target Link Speed. For Downstream Ports this field sets an upper limit on Link operational speed by restricting the values advertised by the Upstream component in its training sequences. The encoded value specifies a bit.." tree.end tree "PF0_AER_CAP (PF Advanced Error Reporting Capability Structure)" group.long (0x0+0x100)++0x1B line.long 0x0 "AER_EXT_CAP_HDR_OFF,Advanced Error Reporting Extended Capability Header. For a description of this standard PCIe register. see the PCI Express Specification." hexmask.long.word 0x0 20.--31. 1. "NEXT_OFFSET,Next Capability Offset. For a description of this standard PCIe register field see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky).." hexmask.long.byte 0x0 16.--19. 1. "CAP_VERSION,Capability Version. For a description of this standard PCIe register field see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else.." newline hexmask.long.word 0x0 0.--15. 1. "CAP_ID,AER Extended Capability ID. For a description of this standard PCIe register field see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else.." line.long 0x4 "UNCORR_ERR_STATUS_OFF,Uncorrectable Error Status Register. For a description of this standard PCIe register. see the PCI Express Specification." hexmask.long.byte 0x4 27.--31. 1. "RSVDP_27,Reserved for future use." rbitfld.long 0x4 23. "RSVDP_23,Reserved for future use." "0,1" newline bitfld.long 0x4 22. "INTERNAL_ERR_STATUS,Uncorrectable Internal Error Status. For a description of this standard PCIe register field see the PCI Express Specification. The controller sets this bit when your application asserts app_err_bus[9]. It does not set this bit when.." "0,1" bitfld.long 0x4 20. "UNSUPPORTED_REQ_ERR_STATUS,Unsupported Request Error Status. For a description of this standard PCIe register field see the PCI Express Specification." "0,1" newline bitfld.long 0x4 19. "ECRC_ERR_STATUS,ECRC Error Status. For a description of this standard PCIe register field see the PCI Express Specification. Note:If CX_ECRC_ENABLE=0 the register field always reads 0." "0,1" bitfld.long 0x4 18. "MALF_TLP_ERR_STATUS,Malformed TLP Status. For a description of this standard PCIe register field see the PCI Express Specification." "0,1" newline bitfld.long 0x4 17. "REC_OVERFLOW_ERR_STATUS,Receiver Overflow Status. For a description of this standard PCIe register field see the PCI Express Specification." "0,1" bitfld.long 0x4 16. "UNEXP_CMPLT_ERR_STATUS,Unexpected Completion Status. For a description of this standard PCIe register field see the PCI Express Specification." "0,1" newline bitfld.long 0x4 15. "CMPLT_ABORT_ERR_STATUS,Completer Abort Status. For a description of this standard PCIe register field see the PCI Express Specification." "0,1" bitfld.long 0x4 14. "CMPLT_TIMEOUT_ERR_STATUS,Completion Timeout Status. For a description of this standard PCIe register field see the PCI Express Specification." "0,1" newline bitfld.long 0x4 13. "FC_PROTOCOL_ERR_STATUS,Flow Control Protocol Error Status. For a description of this standard PCIe register field see the PCI Express Specification." "0,1" bitfld.long 0x4 12. "POIS_TLP_ERR_STATUS,Poisoned TLP Status. For a description of this standard PCIe register field see the PCI Express Specification." "0,1" newline hexmask.long.byte 0x4 6.--11. 1. "RSVDP_6,Reserved for future use." bitfld.long 0x4 5. "SURPRISE_DOWN_ERR_STATUS,Surprise Down Error Status (Optional). For a description of this standard PCIe register field see the PCI Express Specification." "0,1" newline bitfld.long 0x4 4. "DL_PROTOCOL_ERR_STATUS,Data Link Protocol Error Status. For a description of this standard PCIe register field see the PCI Express Specification." "0,1" hexmask.long.byte 0x4 0.--3. 1. "RSVDP_0,Reserved for future use." line.long 0x8 "UNCORR_ERR_MASK_OFF,Uncorrectable Error Mask Register. For a description of this standard PCIe register. see the PCI Express Specification." hexmask.long.byte 0x8 27.--31. 1. "RSVDP_27,Reserved for future use." rbitfld.long 0x8 23. "RSVDP_23,Reserved for future use." "0,1" newline bitfld.long 0x8 22. "INTERNAL_ERR_MASK,Uncorrectable Internal Error Mask (Optional). For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." "0,1" rbitfld.long 0x8 21. "ACS_VIOLATION_MASK,ACS Violation Mask. Setting the ACS Violation Mask bit disables error logging and signaling for ACS Violation errors. The bit is Read-Only Zero for upstream ports when ACS P2P Egress Control Enable is not set. For a description of.." "0,1" newline bitfld.long 0x8 20. "UNSUPPORTED_REQ_ERR_MASK,Unsupported Request Error Mask. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." "0,1" bitfld.long 0x8 19. "ECRC_ERR_MASK,ECRC Error Mask (Optional). For a description of this standard PCIe register field see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W (sticky) Note: This register.." "0,1" newline bitfld.long 0x8 18. "MALF_TLP_ERR_MASK,Malformed TLP Mask. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." "0,1" bitfld.long 0x8 17. "REC_OVERFLOW_ERR_MASK,Receiver Overflow Mask (Optional). For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." "0,1" newline bitfld.long 0x8 16. "UNEXP_CMPLT_ERR_MASK,Unexpected Completion Mask. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." "0,1" bitfld.long 0x8 15. "CMPLT_ABORT_ERR_MASK,Completer Abort Error Mask (Optional). For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." "0,1" newline bitfld.long 0x8 14. "CMPLT_TIMEOUT_ERR_MASK,Completion Timeout Error Mask. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." "0,1" bitfld.long 0x8 13. "FC_PROTOCOL_ERR_MASK,Flow Control Protocol Error Mask. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." "0,1" newline bitfld.long 0x8 12. "POIS_TLP_ERR_MASK,Poisoned TLP Error Mask. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." "0,1" hexmask.long.byte 0x8 6.--11. 1. "RSVDP_6,Reserved for future use." newline rbitfld.long 0x8 5. "SURPRISE_DOWN_ERR_MASK,Surprise Down Error Mask. For a description of this standard PCIe register field see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi:.." "0,1" bitfld.long 0x8 4. "DL_PROTOCOL_ERR_MASK,Data Link Protocol Error Mask. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." "0,1" newline hexmask.long.byte 0x8 0.--3. 1. "RSVDP_0,Reserved for future use." line.long 0xC "UNCORR_ERR_SEV_OFF,Uncorrectable Error Severity Register. For a description of this standard PCIe register. see the PCI Express Specification." hexmask.long.byte 0xC 27.--31. 1. "RSVDP_27,Reserved for future use." rbitfld.long 0xC 24. "ATOMIC_EGRESS_BLOCKED_ERR_SEVERITY,AtomicOp Egress Blocked Severity (Optional). For a description of this standard PCIe register field see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi:.." "0,1" newline rbitfld.long 0xC 23. "RSVDP_23,Reserved for future use." "0,1" bitfld.long 0xC 22. "INTERNAL_ERR_SEVERITY,Uncorrectable Internal Error Severity (Optional). For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." "0,1" newline bitfld.long 0xC 20. "UNSUPPORTED_REQ_ERR_SEVERITY,Unsupported Request Error Severity. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." "0,1" bitfld.long 0xC 19. "ECRC_ERR_SEVERITY,ECRC Error Severity (Optional). For a description of this standard PCIe register field see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W (sticky) Note: This.." "0,1" newline bitfld.long 0xC 18. "MALF_TLP_ERR_SEVERITY,Malformed TLP Severity. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." "0,1" bitfld.long 0xC 17. "REC_OVERFLOW_ERR_SEVERITY,Receiver Overflow Error Severity (Optional). For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." "0,1" newline bitfld.long 0xC 16. "UNEXP_CMPLT_ERR_SEVERITY,Unexpected Completion Error Severity. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." "0,1" bitfld.long 0xC 15. "CMPLT_ABORT_ERR_SEVERITY,Completer Abort Error Severity (Optional). For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." "0,1" newline bitfld.long 0xC 14. "CMPLT_TIMEOUT_ERR_SEVERITY,Completion Timeout Error Severity. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." "0,1" bitfld.long 0xC 13. "FC_PROTOCOL_ERR_SEVERITY,Flow Control Protocol Error Severity (Optional). For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." "0,1" newline bitfld.long 0xC 12. "POIS_TLP_ERR_SEVERITY,Poisoned TLP Severity. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." "0,1" hexmask.long.byte 0xC 6.--11. 1. "RSVDP_6,Reserved for future use." newline rbitfld.long 0xC 5. "SURPRISE_DOWN_ERR_SVRITY,Surprise Down Error Severity (Optional). For a description of this standard PCIe register field see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi:.." "0,1" bitfld.long 0xC 4. "DL_PROTOCOL_ERR_SEVERITY,Data Link Protocol Error Severity. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." "0,1" newline hexmask.long.byte 0xC 0.--3. 1. "RSVDP_0,Reserved for future use." line.long 0x10 "CORR_ERR_STATUS_OFF,Correctable Error Status Register. For a description of this standard PCIe register. see the PCI Express Specification." hexmask.long.word 0x10 16.--31. 1. "RSVDP_16,Reserved for future use." bitfld.long 0x10 15. "HEADER_LOG_OVERFLOW_STATUS,Header Log Overflow Error Status (Optional). For a description of this standard PCIe register field see the PCI Express Specification." "0,1" newline bitfld.long 0x10 14. "CORRECTED_INT_ERR_STATUS,Corrected Internal Error Status (Optional). For a description of this standard PCIe register field see the PCI Express Specification." "0,1" bitfld.long 0x10 13. "ADVISORY_NON_FATAL_ERR_STATUS,Advisory Non-Fatal Error Status. For a description of this standard PCIe register field see the PCI Express Specification." "0,1" newline bitfld.long 0x10 12. "RPL_TIMER_TIMEOUT_STATUS,Replay Timer Timeout Status. For a description of this standard PCIe register field see the PCI Express Specification." "0,1" rbitfld.long 0x10 9.--11. "RSVDP_9,Reserved for future use." "0,1,2,3,4,5,6,7" newline bitfld.long 0x10 8. "REPLAY_NO_ROLEOVER_STATUS,REPLAY_NUM Rollover Status. For a description of this standard PCIe register field see the PCI Express Specification." "0,1" bitfld.long 0x10 7. "BAD_DLLP_STATUS,Bad DLLP Status. For a description of this standard PCIe register field see the PCI Express Specification." "0,1" newline bitfld.long 0x10 6. "BAD_TLP_STATUS,Bad TLP Status. For a description of this standard PCIe register field see the PCI Express Specification." "0,1" hexmask.long.byte 0x10 1.--5. 1. "RSVDP_1,Reserved for future use." newline bitfld.long 0x10 0. "RX_ERR_STATUS,Receiver Error Status (Optional). For a description of this standard PCIe register field see the PCI Express Specification." "0,1" line.long 0x14 "CORR_ERR_MASK_OFF,Correctable Error Mask Register. For a description of this standard PCIe register. see the PCI Express Specification." hexmask.long.word 0x14 16.--31. 1. "RSVDP_16,Reserved for future use." bitfld.long 0x14 15. "HEADER_LOG_OVERFLOW_MASK,Header Log Overflow Error Mask (Optional). For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." "0,1" newline bitfld.long 0x14 14. "CORRECTED_INT_ERR_MASK,Corrected Internal Error Mask (Optional). For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." "0,1" bitfld.long 0x14 13. "ADVISORY_NON_FATAL_ERR_MASK,Advisory Non-Fatal Error Mask. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." "0,1" newline bitfld.long 0x14 12. "RPL_TIMER_TIMEOUT_MASK,Replay Timer Timeout Mask. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." "0,1" rbitfld.long 0x14 9.--11. "RSVDP_9,Reserved for future use." "0,1,2,3,4,5,6,7" newline bitfld.long 0x14 8. "REPLAY_NO_ROLEOVER_MASK,REPLAY_NUM Rollover Mask. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." "0,1" bitfld.long 0x14 7. "BAD_DLLP_MASK,Bad DLLP Mask. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." "0,1" newline bitfld.long 0x14 6. "BAD_TLP_MASK,Bad TLP Mask. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." "0,1" hexmask.long.byte 0x14 1.--5. 1. "RSVDP_1,Reserved for future use." newline bitfld.long 0x14 0. "RX_ERR_MASK,Receiver Error Mask (Optional). For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." "0,1" line.long 0x18 "ADV_ERR_CAP_CTRL_OFF,Advanced Error Capabilities and Control Register. For a description of this standard PCIe register. see the PCI Express Specification." hexmask.long.tbyte 0x18 13.--31. 1. "RSVDP_13,Reserved for future use." rbitfld.long 0x18 12. "CTO_PRFX_HDR_LOG_CAP,TLP Prefix Log Present. For a description of this standard PCIe register field see the PCI Express Specification." "0,1" newline rbitfld.long 0x18 10. "MULTIPLE_HEADER_EN,Multiple Header Recording Enable. For a description of this standard PCIe register field see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R (sticky) Note: This.." "0,1" rbitfld.long 0x18 9. "MULTIPLE_HEADER_CAP,Multiple Header Recording Capable. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." "0,1" newline bitfld.long 0x18 8. "ECRC_CHECK_EN,ECRC Check Enable. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." "0,1" rbitfld.long 0x18 7. "ECRC_CHECK_CAP,ECRC Check Capable. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." "0,1" newline bitfld.long 0x18 6. "ECRC_GEN_EN,ECRC Generation Enable. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." "0,1" rbitfld.long 0x18 5. "ECRC_GEN_CAP,ECRC Generation Capable. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." "0,1" newline hexmask.long.byte 0x18 0.--4. 1. "FIRST_ERR_POINTER,First Error Pointer. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." rgroup.long (0x1C+0x100)++0xF line.long 0x0 "HDR_LOG_0_OFF,Header Log Register 0. For a description of this standard PCIe register. see the PCI Express Specification." hexmask.long.byte 0x0 24.--31. 1. "FIRST_DWORD_FOURTH_BYTE,Byte 3 of Header log register of First 32 bit Data Word. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." hexmask.long.byte 0x0 16.--23. 1. "FIRST_DWORD_THIRD_BYTE,Byte 2 of Header log register of First 32 bit Data Word. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." newline hexmask.long.byte 0x0 8.--15. 1. "FIRST_DWORD_SECOND_BYTE,Byte 1 of Header log register of First 32 bit Data Word. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." hexmask.long.byte 0x0 0.--7. 1. "FIRST_DWORD_FIRST_BYTE,Byte 0 of Header log register of First 32 bit Data Word. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." line.long 0x4 "HDR_LOG_1_OFF,Header Log Register 1. For a description of this standard PCIe register. see the PCI Express Specification." hexmask.long.byte 0x4 24.--31. 1. "SECOND_DWORD_FOURTH_BYTE,Byte 3 of Header log register of Second 32 bit Data Word. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." hexmask.long.byte 0x4 16.--23. 1. "SECOND_DWORD_THIRD_BYTE,Byte 2 of Header log register of Second 32 bit Data Word. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." newline hexmask.long.byte 0x4 8.--15. 1. "SECOND_DWORD_SECOND_BYTE,Byte 1 of Header log register of Second 32 bit Data Word. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." hexmask.long.byte 0x4 0.--7. 1. "SECOND_DWORD_FIRST_BYTE,Byte 0 of Header log register of Second 32 bit Data Word. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." line.long 0x8 "HDR_LOG_2_OFF,Header Log Register 2. For a description of this standard PCIe register. see the PCI Express Specification." hexmask.long.byte 0x8 24.--31. 1. "THIRD_DWORD_FOURTH_BYTE,Byte 3 of Header log register of Third 32 bit Data Word. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." hexmask.long.byte 0x8 16.--23. 1. "THIRD_DWORD_THIRD_BYTE,Byte 2 of Header log register of Third 32 bit Data Word. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." newline hexmask.long.byte 0x8 8.--15. 1. "THIRD_DWORD_SECOND_BYTE,Byte 1 of Header log register of Third 32 bit Data Word. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." hexmask.long.byte 0x8 0.--7. 1. "THIRD_DWORD_FIRST_BYTE,Byte 0 of Header log register of Third 32 bit Data Word. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." line.long 0xC "HDR_LOG_3_OFF,Header Log Register 3. For a description of this standard PCIe register. see the PCI Express Specification." hexmask.long.byte 0xC 24.--31. 1. "FOURTH_DWORD_FOURTH_BYTE,Byte 3 of Header log register of Fourth 32 bit Data Word. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." hexmask.long.byte 0xC 16.--23. 1. "FOURTH_DWORD_THIRD_BYTE,Byte 2 of Header log register of Fourth 32 bit Data Word. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." newline hexmask.long.byte 0xC 8.--15. 1. "FOURTH_DWORD_SECOND_BYTE,Byte 1 of Header log register of Fourth 32 bit Data Word. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." hexmask.long.byte 0xC 0.--7. 1. "FOURTH_DWORD_FIRST_BYTE,Byte 0 of Header log register of Fourth 32 bit Data Word. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." group.long (0x2C+0x100)++0x7 line.long 0x0 "ROOT_ERR_CMD_OFF,Root Error Command Register. For a description of this standard PCIe register. see the PCI Express Specification." hexmask.long 0x0 3.--31. 1. "RSVDP_3,Reserved for future use." bitfld.long 0x0 2. "FATAL_ERR_REPORTING_EN,Fatal Error Reporting Enable. For a description of this standard PCIe register field see the PCI Express Specification." "0,1" newline bitfld.long 0x0 1. "NON_FATAL_ERR_REPORTING_EN,Non-Fatal Error Reporting Enable. For a description of this standard PCIe register field see the PCI Express Specification." "0,1" bitfld.long 0x0 0. "CORR_ERR_REPORTING_EN,Correctable Error Reporting Enable. For a description of this standard PCIe register field see the PCI Express Specification." "0,1" line.long 0x4 "ROOT_ERR_STATUS_OFF,Root Error Status Register. For a description of this standard PCIe register. see the PCI Express Specification." hexmask.long.byte 0x4 27.--31. 1. "ADV_ERR_INT_MSG_NUM,Advanced Error Interrupt Message Number. For a description of this standard PCIe register field see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN.." hexmask.long.tbyte 0x4 7.--26. 1. "RSVDP_7,Reserved for future use." newline bitfld.long 0x4 6. "FATAL_ERR_MSG_RX,One or more Fatal Error Messages Received. For a description of this standard PCIe register field see the PCI Express Specification." "0,1" bitfld.long 0x4 5. "NON_FATAL_ERR_MSG_RX,One or more Non-Fatal Error Messages Received. For a description of this standard PCIe register field see the PCI Express Specification." "0,1" newline bitfld.long 0x4 4. "FIRST_UNCORR_FATAL,First Uncorrectable Error is Fatal. For a description of this standard PCIe register field see the PCI Express Specification." "0,1" bitfld.long 0x4 3. "MUL_ERR_FATAL_NON_FATAL_RX,Multiple Fatal or Non-Fatal Errors Received. For a description of this standard PCIe register field see the PCI Express Specification." "0,1" newline bitfld.long 0x4 2. "ERR_FATAL_NON_FATAL_RX,Fatal or Non-Fatal Error Received. For a description of this standard PCIe register field see the PCI Express Specification." "0,1" bitfld.long 0x4 1. "MUL_ERR_COR_RX,Multiple Correctable Errors Received. For a description of this standard PCIe register field see the PCI Express Specification." "0,1" newline bitfld.long 0x4 0. "ERR_COR_RX,Correctable Error Received. For a description of this standard PCIe register field see the PCI Express Specification." "0,1" rgroup.long (0x34+0x100)++0x13 line.long 0x0 "ERR_SRC_ID_OFF,Error Source Identification Register. For a description of this standard PCIe register. see the PCI Express Specification." hexmask.long.word 0x0 16.--31. 1. "ERR_FATAL_NON_FATAL_SOURCE_ID,Source of Fatal/Non-Fatal Error. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." hexmask.long.word 0x0 0.--15. 1. "ERR_COR_SOURCE_ID,Source of Correctable Error. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." line.long 0x4 "TLP_PREFIX_LOG_1_OFF,TLP Prefix Log Register 1. For a description of this standard PCIe register. see the PCI Express Specification." hexmask.long.byte 0x4 24.--31. 1. "CFG_TLP_PFX_LOG_1_FOURTH_BYTE,Byte 3 of Error TLP Prefix Log 1. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." hexmask.long.byte 0x4 16.--23. 1. "CFG_TLP_PFX_LOG_1_THIRD_BYTE,Byte 2 of Error TLP Prefix Log 1. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." newline hexmask.long.byte 0x4 8.--15. 1. "CFG_TLP_PFX_LOG_1_SECOND_BYTE,Byte 1 of Error TLP Prefix Log 1. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." hexmask.long.byte 0x4 0.--7. 1. "CFG_TLP_PFX_LOG_1_FIRST_BYTE,Byte 0 of Error TLP Prefix Log 1. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." line.long 0x8 "TLP_PREFIX_LOG_2_OFF,TLP Prefix Log Register 2. For a description of this standard PCIe register. see the PCI Express Specification." hexmask.long.byte 0x8 24.--31. 1. "CFG_TLP_PFX_LOG_2_FOURTH_BYTE,Byte 3 Error TLP Prefix Log 2. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." hexmask.long.byte 0x8 16.--23. 1. "CFG_TLP_PFX_LOG_2_THIRD_BYTE,Byte 2 Error TLP Prefix Log 2. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." newline hexmask.long.byte 0x8 8.--15. 1. "CFG_TLP_PFX_LOG_2_SECOND_BYTE,Byte 1 Error TLP Prefix Log 2. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." hexmask.long.byte 0x8 0.--7. 1. "CFG_TLP_PFX_LOG_2_FIRST_BYTE,Byte 0 Error TLP Prefix Log 2. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." line.long 0xC "TLP_PREFIX_LOG_3_OFF,TLP Prefix Log Register 3. For a description of this standard PCIe register. see the PCI Express Specification." hexmask.long.byte 0xC 24.--31. 1. "CFG_TLP_PFX_LOG_3_FOURTH_BYTE,Byte 3 Error TLP Prefix Log 3. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." hexmask.long.byte 0xC 16.--23. 1. "CFG_TLP_PFX_LOG_3_THIRD_BYTE,Byte 2 Error TLP Prefix Log 3. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." newline hexmask.long.byte 0xC 8.--15. 1. "CFG_TLP_PFX_LOG_3_SECOND_BYTE,Byte 1 Error TLP Prefix Log 3. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." hexmask.long.byte 0xC 0.--7. 1. "CFG_TLP_PFX_LOG_3_FIRST_BYTE,Byte 0 Error TLP Prefix Log 3. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." line.long 0x10 "TLP_PREFIX_LOG_4_OFF,TLP Prefix Log Register 4. For a description of this standard PCIe register. see the PCI Express Specification." hexmask.long.byte 0x10 24.--31. 1. "CFG_TLP_PFX_LOG_4_FOURTH_BYTE,Byte 3 Error TLP Prefix Log 4. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." hexmask.long.byte 0x10 16.--23. 1. "CFG_TLP_PFX_LOG_4_THIRD_BYTE,Byte 2 Error TLP Prefix Log 4. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." newline hexmask.long.byte 0x10 8.--15. 1. "CFG_TLP_PFX_LOG_4_SECOND_BYTE,Byte 1 Error TLP Prefix Log 4. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." hexmask.long.byte 0x10 0.--7. 1. "CFG_TLP_PFX_LOG_4_FIRST_BYTE,Byte 0 Error TLP Prefix Log 4. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." tree.end tree "PF0_MSI_CAP (PF MSI Capability Structure)" group.long (0x0+0x50)++0x13 line.long 0x0 "PCI_MSI_CAP_ID_NEXT_CTRL_REG,MSI Capability Header and Message Control Register." hexmask.long.byte 0x0 27.--31. 1. "RSVDP_27,Reserved for future use." bitfld.long 0x0 26. "PCI_MSI_EXT_DATA_EN,Extended Message Data Enable. - If set the function is enabled to provide Extended Message Data. - If clear the function is not enabled to provide Extended Message Data. Note: The access attributes of this field are as follows: -.." "0,1" bitfld.long 0x0 25. "PCI_MSI_EXT_DATA_CAP,Extended Message Data Capable. - If set the function is capable of providing Extended Message Data. - If clear the function does not support providing Extended Message Data. Note: The access attributes of this field are as follows:.." "0,1" newline rbitfld.long 0x0 24. "PCI_PVM_SUPPORT,Per-Vector Masking Capable. - If set the function supports MSI Per-Vector Masking. - If clear the function does not support MSI Per-Vector Masking. This bit must be set if the function is a PF or VF within an SR-IOV Device." "0,1" bitfld.long 0x0 23. "PCI_MSI_64_BIT_ADDR_CAP,64 bit address capable. - If set the function is capable of sending a 64-bit message address. - If clear the function is not capable of sending a 64-bit message address. This bit must be set if the function is a PCI Express.." "0,1" bitfld.long 0x0 20.--22. "PCI_MSI_MULTIPLE_MSG_EN,Multiple Message Enable. Software writes to this field to indicate the number of allocated vectors (equal to or less than the number of requested vectors). The number of allocated vectors is aligned to a power of two. If a.." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 17.--19. "PCI_MSI_MULTIPLE_MSG_CAP,Multiple Message Capable. System software reads this field to determine the number of requested vectors. The number of requested vectors must be aligned to a power of two (if a function requires three vectors it requests four by.." "0,1,2,3,4,5,6,7" bitfld.long 0x0 16. "PCI_MSI_ENABLE,MSI Enable. - If set and the MSI-X Enable bit in the MSI-X Message Control register is clear the function is permitted to use MSI to request service and is prohibited from using INTx interrupts. System configuration software sets this bit.." "0,1" hexmask.long.byte 0x0 8.--15. 1. "PCI_MSI_CAP_NEXT_OFFSET,Next Capability Pointer. This field contains the offset to the next PCI Capability structure or 00h if no other items exist in the linked list of Capabilities. Note: The access attributes of this field are as follows: - Wire: No.." newline hexmask.long.byte 0x0 0.--7. 1. "PCI_MSI_CAP_ID,Capability ID. Indicates the MSI Capability structure. This field returns a Capability ID of 05h indicating that this is an MSI Capability structure." line.long 0x4 "MSI_CAP_OFF_04H_REG,Message Address Register for MSI (Offset 04h)." hexmask.long 0x4 2.--31. 1. "PCI_MSI_CAP_OFF_04H,Message Address - System-specified message address. If the Message Enable bit (bit 16 of the PCI_MSI_CAP_ID_NEXT_CTRL_REG register) is set the contents of this field specify the DWORD-aligned address (Address[31:02]) for the MSI.." rbitfld.long 0x4 0.--1. "RSVDP_0,Reserved for future use." "0,1,2,3" line.long 0x8 "MSI_CAP_OFF_08H_REG,For a function that supports a 32-bit message address. - bits[31:16] of this register represent the Extended Message Data. and - bits[15:0] of this register represent the Message Data For a function that supports a 64-bit message.." hexmask.long.word 0x8 16.--31. 1. "PCI_MSI_CAP_OFF_0AH,For a function that supports a 32-bit message address this field contains Extended Message Data (System-specified message data). For the MSI Capability structures without per-vector masking it must be implemented if the Extended.." hexmask.long.word 0x8 0.--15. 1. "PCI_MSI_CAP_OFF_08H,For a function that supports a 32-bit message address this field contains Message Data (System-specified message data). If the Message Enable bit (bit 16 of the PCI_MSI_CAP_ID_NEXT_CTRL_REG) is set the function sends a DWORD Memory.." line.long 0xC "MSI_CAP_OFF_0CH_REG,For a function that supports a 32-bit message address. this register contains the Mask Bits when the Per-Vector Masking Capable bit (bit 24 of PCI_MSI_CAP_ID_NEXT_CTRL_REG) is set. For a function that supports a 64-bit message.." hexmask.long.word 0xC 16.--31. 1. "PCI_MSI_CAP_OFF_0EH,For a function that supports a 32-bit message address this field contains the upper Mask Bits when the Per Vector Masking Capable bit (PCI_MSI_CAP_ID_NEXT_CTRL_REG.PCI_PVM_SUPPORT) is set. For a function that supports a 64-bit.." hexmask.long.word 0xC 0.--15. 1. "PCI_MSI_CAP_OFF_0CH,For a function that supports a 32-bit message address this field contains the lower Mask Bits when the Per Vector Masking Capable bit (PCI_MSI_CAP_ID_NEXT_CTRL_REG.PCI_PVM_SUPPORT) is set. For a function that supports a 64-bit.." line.long 0x10 "MSI_CAP_OFF_10H_REG,For a function that supports a 32-bit message address. this register contains the Pending Bits when the Per-Vector Masking Capable bit (bit 24 of PCI_MSI_CAP_ID_NEXT_CTRL_REG) is set. For a function that supports a 64-bit message.." hexmask.long 0x10 0.--31. 1. "PCI_MSI_CAP_OFF_10H,Used for MSI when the Per Vector Masking Capable bit (PCI_MSI_CAP_ID_NEXT_CTRL_REG.PCI_PVM_SUPPORT) is set. For 32-bit contains Pending Bits. For 64-bit contains Mask Bits. For a description of this standard PCIe register field see.." rgroup.long (0x14+0x50)++0x3 line.long 0x0 "MSI_CAP_OFF_14H_REG,Pending Bits Register for MSI. This register is used for a function that supports a 64-bit message address when the Per-Vector Masking Capable bit (bit 24 of PCI_MSI_CAP_ID_NEXT_CTRL_REG) is set." hexmask.long 0x0 0.--31. 1. "PCI_MSI_CAP_OFF_14H,Pending Bits. For each pending bit that is set the function has a pending associated message." tree.end tree "PF0_DMA_CAP (DMA Port Logic Structure)" group.long (0x0+0xC8000)++0x3 line.long 0x0 "DMA_CTRL_DATA_ARB_PRIOR_OFF,DMA Arbitration Scheme for TRGT1 Interface. This register is used to control traffic priorities among various sources that are delivered to your application through TRGT1 where 0x0 represents the highest priority. - Non-DMA Rx.." hexmask.long.tbyte 0x0 12.--31. 1. "RSVDP_12,Reserved for future use." bitfld.long 0x0 9.--11. "RDBUFF_TRGT_WEIGHT,DMA Read Channel MWr Requests. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 6.--8. "RD_CTRL_TRGT_WEIGHT,DMA Read Channel MRd Requests. For LL element/descriptor access. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" "0,1,2,3,4,5,6,7" bitfld.long 0x0 3.--5. "WR_CTRL_TRGT_WEIGHT,DMA Write Channel MRd Requests. For DMA data requests and LL element/descriptor access. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 0.--2. "RTRGT1_WEIGHT,Non-DMA Rx Requests. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" "0,1,2,3,4,5,6,7" group.long (0x8+0xC8000)++0xB line.long 0x0 "DMA_CTRL_OFF,DMA Number of Channels Register." hexmask.long.byte 0x0 26.--31. 1. "RSVDP_26,Reserved for future use." bitfld.long 0x0 25. "DIS_C2W_CACHE_RD,Disable DMA Read Channels 'completion to memory write' context cache pre-fetch function. Note: For internal debugging only. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" "0,1" newline bitfld.long 0x0 24. "DIS_C2W_CACHE_WR,Disable DMA Write Channels 'completion to memory write' context cache pre-fetch function. Note: For internal debugging only. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" "0,1" hexmask.long.byte 0x0 20.--23. 1. "RSVDP_20,Reserved for future use." newline hexmask.long.byte 0x0 16.--19. 1. "NUM_DMA_RD_CHAN,Number of Read Channels. You can read this register to determine the number of read channels the DMA controller has been configured to support." hexmask.long.word 0x0 4.--15. 1. "RSVDP_4,Reserved for future use." newline hexmask.long.byte 0x0 0.--3. 1. "NUM_DMA_WR_CHAN,Number of Write Channels. You can read this register to determine the number of write channels the DMA controller has been configured to support." line.long 0x4 "DMA_WRITE_ENGINE_EN_OFF,DMA Write Engine Enable Register." hexmask.long.byte 0x4 24.--31. 1. "RSVDP_24,Reserved for future use." bitfld.long 0x4 23. "DMA_WRITE_ENGINE_EN_HSHAKE_CH7,Enable Handshake for DMA Write Engine Channel 7. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" "0,1" newline bitfld.long 0x4 22. "DMA_WRITE_ENGINE_EN_HSHAKE_CH6,Enable Handshake for DMA Write Engine Channel 6. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" "0,1" bitfld.long 0x4 21. "DMA_WRITE_ENGINE_EN_HSHAKE_CH5,Enable Handshake for DMA Write Engine Channel 5. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" "0,1" newline bitfld.long 0x4 20. "DMA_WRITE_ENGINE_EN_HSHAKE_CH4,Enable Handshake for DMA Write Engine Channel 4. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" "0,1" bitfld.long 0x4 19. "DMA_WRITE_ENGINE_EN_HSHAKE_CH3,Enable Handshake for DMA Write Engine Channel 3. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" "0,1" newline bitfld.long 0x4 18. "DMA_WRITE_ENGINE_EN_HSHAKE_CH2,Enable Handshake for DMA Write Engine Channel 2. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" "0,1" bitfld.long 0x4 17. "DMA_WRITE_ENGINE_EN_HSHAKE_CH1,Enable Handshake for DMA Write Engine Channel 1. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" "0,1" newline bitfld.long 0x4 16. "DMA_WRITE_ENGINE_EN_HSHAKE_CH0,Enable Handshake for DMA Write Engine Channel 0. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" "0,1" hexmask.long.word 0x4 1.--15. 1. "RSVDP_1,Reserved for future use." newline bitfld.long 0x4 0. "DMA_WRITE_ENGINE,DMA Write Engine Enable. - 1: Enable - 0: Disable (Soft Reset) For normal operation you must initially set this bit to '1' before any other software setup actions. You do not need to toggle or rewrite to this bit during normal.." "Disable,Enable" line.long 0x8 "DMA_WRITE_DOORBELL_OFF,DMA Write Doorbell Register." bitfld.long 0x8 31. "WR_STOP,Stop. Set in conjunction with the Doorbell Number field. The DMA write channel stops issuing requests sets the channel status to 'Stopped' and asserts the 'Abort' interrupt if it is enabled. Before setting the Stop bit you must read the.." "0,1" hexmask.long 0x8 3.--30. 1. "RSVDP_3,Reserved for future use." newline bitfld.long 0x8 0.--2. "WR_DOORBELL_NUM,Doorbell Number. You must write the channel number to this register to start the DMA write transfer for that channel. The DMA detects a write to this register field even if the value of this field does not change. You do not need to.." "0,1,2,3,4,5,6,7" group.long (0x18+0xC8000)++0x7 line.long 0x0 "DMA_WRITE_CHANNEL_ARB_WEIGHT_LOW_OFF,DMA Write Engine Channel Arbitration Weight Low Register. The 5-bit channel weight (for write channels 0-3) specifies the maximum number of TLP requests that the DMA can issue for that channel before it must return to.." hexmask.long.word 0x0 20.--31. 1. "RSVDP_20,Reserved for future use." hexmask.long.byte 0x0 15.--19. 1. "WRITE_CHANNEL3_WEIGHT,Channel 3 Weight. The weight is initialized by software before ringing the doorbell. The value is used by the channel weighted round robin arbiter to select the next channel read request. A value of '0' means that one TLP is issued.." newline hexmask.long.byte 0x0 10.--14. 1. "WRITE_CHANNEL2_WEIGHT,Channel 2 Weight. The weight is initialized by software before ringing the doorbell. The value is used by the channel weighted round robin arbiter to select the next channel read request. A value of '0' means that one TLP is issued.." hexmask.long.byte 0x0 5.--9. 1. "WRITE_CHANNEL1_WEIGHT,Channel 1 Weight. The weight is initialized by software before ringing the doorbell. The value is used by the channel weighted round robin arbiter to select the next channel read request. A value of '0' means that one TLP is issued.." newline hexmask.long.byte 0x0 0.--4. 1. "WRITE_CHANNEL0_WEIGHT,Channel 0 Weight. The weight is initialized by software before ringing the doorbell. The value is used by the channel weighted round robin arbiter to select the next channel read request. A value of '0' means that one TLP is issued.." line.long 0x4 "DMA_WRITE_CHANNEL_ARB_WEIGHT_HIGH_OFF,DMA Write Engine Channel Arbitration Weight High Register. The 5-bit channel weight (for write channels 4-7) specifies the maximum number of TLP requests that the DMA can issue for that channel before it must return.." hexmask.long.word 0x4 20.--31. 1. "RSVDP_20,Reserved for future use." hexmask.long.byte 0x4 15.--19. 1. "WRITE_CHANNEL7_WEIGHT,Channel 7 Weight. The weight is initialized by software before ringing the doorbell. The value is used by the channel weighted round robin arbiter to select the next channel read request. A value of '0' means that one TLP is issued.." newline hexmask.long.byte 0x4 10.--14. 1. "WRITE_CHANNEL6_WEIGHT,Channel 6 Weight. The weight is initialized by software before ringing the doorbell. The value is used by the channel weighted round robin arbiter to select the next channel read request. A value of '0' means that one TLP is issued.." hexmask.long.byte 0x4 5.--9. 1. "WRITE_CHANNEL5_WEIGHT,Channel 5 Weight. The weight is initialized by software before ringing the doorbell. The value is used by the channel weighted round robin arbiter to select the next channel read request. A value of '0' means that one TLP is issued.." newline hexmask.long.byte 0x4 0.--4. 1. "WRITE_CHANNEL4_WEIGHT,Channel 4 Weight. The weight is initialized by software before ringing the doorbell. The value is used by the channel weighted round robin arbiter to select the next channel read request. A value of '0' means that one TLP is issued.." group.long (0x2C+0xC8000)++0x7 line.long 0x0 "DMA_READ_ENGINE_EN_OFF,DMA Read Engine Enable Register." hexmask.long.byte 0x0 24.--31. 1. "RSVDP_24,Reserved for future use." bitfld.long 0x0 23. "DMA_READ_ENGINE_EN_HSHAKE_CH7,Enable Handshake for DMA Read Engine Channel 7. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" "0,1" newline bitfld.long 0x0 22. "DMA_READ_ENGINE_EN_HSHAKE_CH6,Enable Handshake for DMA Read Engine Channel 6. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" "0,1" bitfld.long 0x0 21. "DMA_READ_ENGINE_EN_HSHAKE_CH5,Enable Handshake for DMA Read Engine Channel 5. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" "0,1" newline bitfld.long 0x0 20. "DMA_READ_ENGINE_EN_HSHAKE_CH4,Enable Handshake for DMA Read Engine Channel 4. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" "0,1" bitfld.long 0x0 19. "DMA_READ_ENGINE_EN_HSHAKE_CH3,Enable Handshake for DMA Read Engine Channel 3. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" "0,1" newline bitfld.long 0x0 18. "DMA_READ_ENGINE_EN_HSHAKE_CH2,Enable Handshake for DMA Read Engine Channel 2. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" "0,1" bitfld.long 0x0 17. "DMA_READ_ENGINE_EN_HSHAKE_CH1,Enable Handshake for DMA Read Engine Channel 1. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" "0,1" newline bitfld.long 0x0 16. "DMA_READ_ENGINE_EN_HSHAKE_CH0,Enable Handshake for DMA Read Engine Channel 0. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" "0,1" hexmask.long.word 0x0 1.--15. 1. "RSVDP_1,Reserved for future use." newline bitfld.long 0x0 0. "DMA_READ_ENGINE,DMA Read Engine Enable. - 1: Enable - 0: Disable (Soft Reset) For normal operation you must initially set this bit to '1' before any other software setup actions. You do not need to toggle or rewrite to this bit during normal operation." "Disable,Enable" line.long 0x4 "DMA_READ_DOORBELL_OFF,DMA Read Doorbell Register." bitfld.long 0x4 31. "RD_STOP,Stop. Set in conjunction with the Doorbell Number field. The DMA read channel stops issuing requests sets the channel status to 'Stopped' and asserts the 'Abort' interrupt if it is enabled. Before setting the Stop bit you must read the channel.." "0,1" hexmask.long 0x4 3.--30. 1. "RSVDP_3,Reserved for future use." newline bitfld.long 0x4 0.--2. "RD_DOORBELL_NUM,Doorbell Number. You must write 0x0 to this register to start the DMA read transfer for that channel. The DMA detects a write to this register field even if the value of this field does not change. The range of this field is 0x0 to 0x7.." "0,1,2,3,4,5,6,7" group.long (0x38+0xC8000)++0x7 line.long 0x0 "DMA_READ_CHANNEL_ARB_WEIGHT_LOW_OFF,DMA Read Engine Channel Arbitration Weight Low Register. The 5-bit channel weight (for read channels 0-3) specifies the maximum number of TLP requests that the DMA can issue for that channel before it must return to.." hexmask.long.word 0x0 20.--31. 1. "RSVDP_20,Reserved for future use." hexmask.long.byte 0x0 15.--19. 1. "READ_CHANNEL3_WEIGHT,Channel 3 Weight. The weight is initialized by software before ringing the doorbell. The value is used by the channel weighted round robin arbiter to select the next channel read request. Note: The access attributes of this field are.." newline hexmask.long.byte 0x0 10.--14. 1. "READ_CHANNEL2_WEIGHT,Channel 2 Weight. The weight is initialized by software before ringing the doorbell. The value is used by the channel weighted round robin arbiter to select the next channel read request. Note: The access attributes of this field are.." hexmask.long.byte 0x0 5.--9. 1. "READ_CHANNEL1_WEIGHT,Channel 1 Weight. The weight is initialized by software before ringing the doorbell. The value is used by the channel weighted round robin arbiter to select the next channel read request. Note: The access attributes of this field are.." newline hexmask.long.byte 0x0 0.--4. 1. "READ_CHANNEL0_WEIGHT,Channel 0 Weight. The weight is initialized by software before ringing the doorbell. The value is used by the channel weighted round robin arbiter to select the next channel read request. Note: The access attributes of this field are.." line.long 0x4 "DMA_READ_CHANNEL_ARB_WEIGHT_HIGH_OFF,DMA Read Engine Channel Arbitration Weight High Register. The 5-bit channel weight (for read channels 4-7) specifies the maximum number of TLP requests that the DMA can issue for that channel before it must return to.." hexmask.long.word 0x4 20.--31. 1. "RSVDP_20,Reserved for future use." hexmask.long.byte 0x4 15.--19. 1. "READ_CHANNEL7_WEIGHT,Channel 7 Weight. The weight is initialized by software before ringing the doorbell. The value is used by the channel weighted round robin arbiter to select the next channel read request. Note: The access attributes of this field are.." newline hexmask.long.byte 0x4 10.--14. 1. "READ_CHANNEL6_WEIGHT,Channel 6 Weight. The weight is initialized by software before ringing the doorbell. The value is used by the channel weighted round robin arbiter to select the next channel read request. Note: The access attributes of this field are.." hexmask.long.byte 0x4 5.--9. 1. "READ_CHANNEL5_WEIGHT,Channel 5 Weight. The weight is initialized by software before ringing the doorbell. The value is used by the channel weighted round robin arbiter to select the next channel read request. Note: The access attributes of this field are.." newline hexmask.long.byte 0x4 0.--4. 1. "READ_CHANNEL4_WEIGHT,Channel 4 Weight. The weight is initialized by software before ringing the doorbell. The value is used by the channel weighted round robin arbiter to select the next channel read request. Note: The access attributes of this field are.." group.long (0x4C+0xC8000)++0x3 line.long 0x0 "DMA_WRITE_INT_STATUS_OFF,DMA Write Interrupt Status Register." hexmask.long.byte 0x0 24.--31. 1. "RSVDP_24,Reserved for future use." hexmask.long.byte 0x0 16.--23. 1. "WR_ABORT_INT_STATUS,Abort Interrupt Status. The DMA write channel has detected an error or you manually stopped the transfer as described in 'Error Handling Assistance by Remote Software'. Each bit corresponds to a DMA channel. Bit [0] corresponds to.." newline hexmask.long.byte 0x0 8.--15. 1. "RSVDP_8,Reserved for future use." hexmask.long.byte 0x0 0.--7. 1. "WR_DONE_INT_STATUS,Done Interrupt Status. The DMA write channel has successfully completed the DMA transfer. For more details see 'Interrupts and Error Handling'. Each bit corresponds to a DMA channel. Bit [0] corresponds to channel 0. - Enabling: For.." group.long (0x54+0xC8000)++0x7 line.long 0x0 "DMA_WRITE_INT_MASK_OFF,DMA Write Interrupt Mask Register." hexmask.long.byte 0x0 24.--31. 1. "RSVDP_24,Reserved for future use." hexmask.long.byte 0x0 16.--23. 1. "WR_ABORT_INT_MASK,Abort Interrupt Mask. Prevents the Abort interrupt status field in the DMA write interrupt status register from asserting the edma_int output. Each bit corresponds to a DMA channel. Bit [0] corresponds to channel 0. Note: The access.." newline hexmask.long.byte 0x0 8.--15. 1. "RSVDP_8,Reserved for future use." hexmask.long.byte 0x0 0.--7. 1. "WR_DONE_INT_MASK,Done Interrupt Mask. Prevents the Done interrupt status field in the DMA write interrupt status register from asserting the edma_int output. Each bit corresponds to a DMA channel. Bit [0] corresponds to channel 0. Note: The access.." line.long 0x4 "DMA_WRITE_INT_CLEAR_OFF,DMA Write Interrupt Clear Register." hexmask.long.byte 0x4 24.--31. 1. "RSVDP_24,Reserved for future use." hexmask.long.byte 0x4 16.--23. 1. "WR_ABORT_INT_CLEAR,Abort Interrupt Clear. You must write a 1'b1 to clear the corresponding bit in the Abort interrupt status field of the DMA write interrupt status register. Each bit corresponds to a DMA channel. Bit [0] corresponds to channel 0. Note:.." newline hexmask.long.byte 0x4 8.--15. 1. "RSVDP_8,Reserved for future use." hexmask.long.byte 0x4 0.--7. 1. "WR_DONE_INT_CLEAR,Done Interrupt Clear. You must write a 1'b1 to clear the corresponding bit in the Done interrupt status field of the DMA write interrupt status register. Each bit corresponds to a DMA channel. Bit [0] corresponds to channel 0. Note:.." rgroup.long (0x5C+0xC8000)++0x3 line.long 0x0 "DMA_WRITE_ERR_STATUS_OFF,DMA Write Error Status Register" hexmask.long.byte 0x0 24.--31. 1. "RSVDP_24,Reserved for future use." hexmask.long.byte 0x0 16.--23. 1. "LINKLIST_ELEMENT_FETCH_ERR_DETECT,Linked List Element Fetch Error Detected. The DMA write channel has received an error response from the AXI bus (or TRGT1 interface when the AXI Bridge is not used) while reading a linked list element from local memory." newline hexmask.long.byte 0x0 8.--15. 1. "RSVDP_8,Reserved for future use." hexmask.long.byte 0x0 0.--7. 1. "APP_READ_ERR_DETECT,Application Read Error Detected. The DMA write channel has received an error response from the AXI bus (or TRGT1 interface when the AXI Bridge is not used) while reading data from it. Each bit corresponds to a DMA channel. Bit [0].." group.long (0x60+0xC8000)++0x1F line.long 0x0 "DMA_WRITE_DONE_IMWR_LOW_OFF,DMA Write Done IMWr Address Low Register." hexmask.long 0x0 0.--31. 1. "DMA_WRITE_DONE_LOW_REG,The DMA uses this field to generate bits [31:0] of the address field for the Done IMWr TLP. Bits [1:0] must be '00' as this address must be dword aligned. Note: The access attributes of this field are as follows: - Wire: No access." line.long 0x4 "DMA_WRITE_DONE_IMWR_HIGH_OFF,DMA Write Done IMWr Interrupt Address High Register." hexmask.long 0x4 0.--31. 1. "DMA_WRITE_DONE_HIGH_REG,The DMA uses this field to generate bits [63:32] of the address field for the Done IMWr TLP. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" line.long 0x8 "DMA_WRITE_ABORT_IMWR_LOW_OFF,DMA Write Abort IMWr Address Low Register." hexmask.long 0x8 0.--31. 1. "DMA_WRITE_ABORT_LOW_REG,The DMA uses this field to generate bits [31:0] of the address field for the Abort IMWr TLP it generates. Bits [1:0] must be '00' as this address must be dword aligned. Note: The access attributes of this field are as follows: -.." line.long 0xC "DMA_WRITE_ABORT_IMWR_HIGH_OFF,DMA Write Abort IMWr Address High Register." hexmask.long 0xC 0.--31. 1. "DMA_WRITE_ABORT_HIGH_REG,The DMA uses this field to generate bits [63:32] of the address field for the Abort IMWr TLP. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" line.long 0x10 "DMA_WRITE_CH01_IMWR_DATA_OFF,DMA Write Channel 1 and 0 IMWr Data Register." hexmask.long.word 0x10 16.--31. 1. "WR_CHANNEL_1_DATA,The DMA uses this field to generate the data field for the Done or Abort IMWr TLPs it generates for write channel 1. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" hexmask.long.word 0x10 0.--15. 1. "WR_CHANNEL_0_DATA,The DMA uses this field to generate the data field for the Done or Abort IMWr TLPs it generates for write channel 0. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" line.long 0x14 "DMA_WRITE_CH23_IMWR_DATA_OFF,DMA Write Channel 3 and 2 IMWr Data Register." hexmask.long.word 0x14 16.--31. 1. "WR_CHANNEL_3_DATA,The DMA uses this field to generate the data field for the Done or Abort IMWr TLPs it generates for write channel 3. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" hexmask.long.word 0x14 0.--15. 1. "WR_CHANNEL_2_DATA,The DMA uses this field to generate the data field for the Done or Abort IMWr TLPs it generates for write channel 2. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" line.long 0x18 "DMA_WRITE_CH45_IMWR_DATA_OFF,DMA Write Channel 5 and 4 IMWr Data Register." hexmask.long.word 0x18 16.--31. 1. "WR_CHANNEL_5_DATA,The DMA uses this field to generate the data field for the Done or Abort IMWr TLPs it generates for write channel 5. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" hexmask.long.word 0x18 0.--15. 1. "WR_CHANNEL_4_DATA,The DMA uses this field to generate the data field for the Done or Abort IMWr TLPs it generates for write channel 4. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" line.long 0x1C "DMA_WRITE_CH67_IMWR_DATA_OFF,DMA Write Channel 7 and 6 IMWr Data Register." hexmask.long.word 0x1C 16.--31. 1. "WR_CHANNEL_7_DATA,The DMA uses this field to generate the data field for the Done or Abort IMWr TLPs it generates for write channel 7. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" hexmask.long.word 0x1C 0.--15. 1. "WR_CHANNEL_6_DATA,The DMA uses this field to generate the data field for the Done or Abort IMWr TLPs it generates for write channel 6. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" group.long (0x90+0xC8000)++0x3 line.long 0x0 "DMA_WRITE_LINKED_LIST_ERR_EN_OFF,DMA Write Linked List Error Enable Register. The LIE and RIE bits in the LL element enable the channel 'done' interrupts (local and remote). The LLLAIE and LLRAIE bits enable the channel 'abort' interrupts (local and.." hexmask.long.byte 0x0 24.--31. 1. "RSVDP_24,Reserved for future use." hexmask.long.byte 0x0 16.--23. 1. "WR_CHANNEL_LLLAIE,Write Channel LL Local Abort Interrupt Enable (LLLAIE). You enable the write channel local abort interrupt through this bit. The LIE and RIE bits in the LL element enable the write channel done interrupts. Each bit corresponds to a DMA.." newline hexmask.long.byte 0x0 8.--15. 1. "RSVDP_8,Reserved for future use." hexmask.long.byte 0x0 0.--7. 1. "WR_CHANNEL_LLRAIE,Write Channel LL Remote Abort Interrupt Enable (LLRAIE). You enable the write channel remote abort interrupt through this bit. The LIE and RIE bits in the LL element enable the write channel done interrupts. Each bit corresponds to a.." group.long (0xA0+0xC8000)++0x3 line.long 0x0 "DMA_READ_INT_STATUS_OFF,DMA Read Interrupt Status Register." hexmask.long.byte 0x0 24.--31. 1. "RSVDP_24,Reserved for future use." hexmask.long.byte 0x0 16.--23. 1. "RD_ABORT_INT_STATUS,Abort Interrupt Status. The DMA read channel has detected an error or you manually stopped the transfer as described in 'Stopping the DMA Transfer (Software Stop)'. Each bit corresponds to a DMA channel. Bit [0] corresponds to.." newline hexmask.long.byte 0x0 8.--15. 1. "RSVDP_8,Reserved for future use." hexmask.long.byte 0x0 0.--7. 1. "RD_DONE_INT_STATUS,Done Interrupt Status. The DMA read channel has successfully completed the DMA read transfer. Each bit corresponds to a DMA channel. Bit [0] corresponds to channel 0. - Enabling: For details see 'Interrupts and Error Handling'. -.." group.long (0xA8+0xC8000)++0x7 line.long 0x0 "DMA_READ_INT_MASK_OFF,DMA Read Interrupt Mask Register." hexmask.long.byte 0x0 24.--31. 1. "RSVDP_24,Reserved for future use." hexmask.long.byte 0x0 16.--23. 1. "RD_ABORT_INT_MASK,Abort Interrupt Mask. Prevents the Abort interrupt status field in the DMA read interrupt status register from asserting the edma_int output. Each bit corresponds to a DMA channel. Bit [0] corresponds to channel 0. Note: The access.." newline hexmask.long.byte 0x0 8.--15. 1. "RSVDP_8,Reserved for future use." hexmask.long.byte 0x0 0.--7. 1. "RD_DONE_INT_MASK,Done Interrupt Mask. Prevents the Done interrupt status field in the DMA read interrupt status register from asserting the edma_int output. Each bit corresponds to a DMA channel. Bit [0] corresponds to channel 0. Note: The access.." line.long 0x4 "DMA_READ_INT_CLEAR_OFF,DMA Read Interrupt Clear Register." hexmask.long.byte 0x4 24.--31. 1. "RSVDP_24,Reserved for future use." hexmask.long.byte 0x4 16.--23. 1. "RD_ABORT_INT_CLEAR,Abort Interrupt Clear. You must write a 1'b1 to clear the corresponding bit in the Abort interrupt status field of the DMA read interrupt status register. Each bit corresponds to a DMA channel. Bit [0] corresponds to channel 0. Note:.." newline hexmask.long.byte 0x4 8.--15. 1. "RSVDP_8,Reserved for future use." hexmask.long.byte 0x4 0.--7. 1. "RD_DONE_INT_CLEAR,Done Interrupt Clear. You must write a 1'b1 to clear the corresponding bit in the Done interrupt status field of the DMA read interrupt status register. Each bit corresponds to a DMA channel. Bit [0] corresponds to channel 0. Note:.." rgroup.long (0xB4+0xC8000)++0x7 line.long 0x0 "DMA_READ_ERR_STATUS_LOW_OFF,DMA Read Error Status Low Register." hexmask.long.byte 0x0 24.--31. 1. "RSVDP_24,Reserved for future use." hexmask.long.byte 0x0 16.--23. 1. "LINK_LIST_ELEMENT_FETCH_ERR_DETECT,Linked List Element Fetch Error Detected. - The DMA read channel has received an error response from the AXI bus while reading a linked list element from local memory. Each bit corresponds to a DMA channel. Bit [0].." newline hexmask.long.byte 0x0 8.--15. 1. "RSVDP_8,Reserved for future use." hexmask.long.byte 0x0 0.--7. 1. "APP_WR_ERR_DETECT,Application Write Error Detected. The DMA read channel has received an error response from the AXI bus (or TRGT1 interface when the AXI Bridge is not used) while writing data to it. This error is fatal. You must restart the transfer.." line.long 0x4 "DMA_READ_ERR_STATUS_HIGH_OFF,DMA Read Error Status High Register." hexmask.long.byte 0x4 24.--31. 1. "DATA_POISIONING,Data Poisoning. The DMA read channel has detected data poisoning in the completion from the remote device (in response to the MRd request). The DMA read channel will drop the completion and then be halted. The CX_FLT_MASK_UR_POIS filter.." hexmask.long.byte 0x4 16.--23. 1. "CPL_TIMEOUT,Completion Time Out. The DMA read channel has timed-out while waiting for the remote device to respond to the MRd request or a malformed CplD has been received. For more details see 'Linked List Mode'. Each bit corresponds to a DMA channel." newline hexmask.long.byte 0x4 8.--15. 1. "CPL_ABORT,Completer Abort. The DMA read channel has received a PCIe completer abort completion status from the remote device in response to the MRd request. For more details see 'Linked List Mode'. Each bit corresponds to a DMA channel. Bit [0].." hexmask.long.byte 0x4 0.--7. 1. "UNSUPPORTED_REQ,Unsupported Request. The DMA read channel has received a PCIe unsupported request completion status from the remote device in response to the MRd request. For more details see 'Linked List Mode'. Each bit corresponds to a DMA channel." group.long (0xC4+0xC8000)++0x3 line.long 0x0 "DMA_READ_LINKED_LIST_ERR_EN_OFF,DMA Read Linked List Error Enable Register. The LIE and RIE bits in the LL element enable the channel 'done' interrupts (local and remote). The LLLAIE and LLRAIE bits enable the channel 'abort' interrupts (local and remote)." hexmask.long.byte 0x0 24.--31. 1. "RSVDP_24,Reserved for future use." hexmask.long.byte 0x0 16.--23. 1. "RD_CHANNEL_LLLAIE,Read Channel LL Local Abort Interrupt Enable (LLLAIE). You enable the read channel Local Abort interrupt through this bit. The LIE and RIE bits in the LL element enable the read channel done interrupts. Each bit corresponds to a DMA.." newline hexmask.long.byte 0x0 8.--15. 1. "RSVDP_8,Reserved for future use." hexmask.long.byte 0x0 0.--7. 1. "RD_CHANNEL_LLRAIE,Read Channel LL Remote Abort Interrupt Enable (LLRAIE). You enable the read channel Remote Abort interrupt through this bit. The LIE and RIE bits in the LL element enable the read channel done interrupts. Each bit corresponds to a DMA.." group.long (0xCC+0xC8000)++0x1F line.long 0x0 "DMA_READ_DONE_IMWR_LOW_OFF,DMA Read Done IMWr Address Low Register." hexmask.long 0x0 0.--31. 1. "DMA_READ_DONE_LOW_REG,The DMA uses this field to generate bits [31:0] of the address field for the Done IMWr TLP. Bits [1:0] must be '00' as this address must be dword aligned. Note: The access attributes of this field are as follows: - Wire: No access." line.long 0x4 "DMA_READ_DONE_IMWR_HIGH_OFF,DMA Read Done IMWr Address High Register." hexmask.long 0x4 0.--31. 1. "DMA_READ_DONE_HIGH_REG,The DMA uses this field to generate bits [63:32] of the address field for the Done IMWr TLP. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" line.long 0x8 "DMA_READ_ABORT_IMWR_LOW_OFF,DMA Read Abort IMWr Address Low Register." hexmask.long 0x8 0.--31. 1. "DMA_READ_ABORT_LOW_REG,The DMA uses this field to generate bits [31:0] of the address field for the Abort IMWr TLP. Bits [1:0] must be '00' as this address must be dword aligned. Note: The access attributes of this field are as follows: - Wire: No.." line.long 0xC "DMA_READ_ABORT_IMWR_HIGH_OFF,DMA Read Abort IMWr Address High Register." hexmask.long 0xC 0.--31. 1. "DMA_READ_ABORT_HIGH_REG,The DMA uses this field to generate bits [63:32] of the address field for the Abort IMWr TLP. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" line.long 0x10 "DMA_READ_CH01_IMWR_DATA_OFF,DMA Read Channel 1 and 0 IMWr Data Register." hexmask.long.word 0x10 16.--31. 1. "RD_CHANNEL_1_DATA,The DMA uses this field to generate the data field for the Done or Abort IMWr TLPs it generates for read channel 1. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" hexmask.long.word 0x10 0.--15. 1. "RD_CHANNEL_0_DATA,The DMA uses this field to generate the data field for the Done or Abort IMWr TLPs it generates for read channel 0. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" line.long 0x14 "DMA_READ_CH23_IMWR_DATA_OFF,DMA Read Channel 3 and 2 IMWr Data Register." hexmask.long.word 0x14 16.--31. 1. "RD_CHANNEL_3_DATA,The DMA uses this field to generate the data field for the Done or Abort IMWr TLPs it generates for read channel 3. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" hexmask.long.word 0x14 0.--15. 1. "RD_CHANNEL_2_DATA,The DMA uses this field to generate the data field for the Done or Abort IMWr TLPs it generates for read channel 2. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" line.long 0x18 "DMA_READ_CH45_IMWR_DATA_OFF,DMA Read Channel 5 and 4 IMWr Data Register." hexmask.long.word 0x18 16.--31. 1. "RD_CHANNEL_5_DATA,The DMA uses this field to generate the data field for the Done or Abort IMWr TLPs it generates for read channel 5. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" hexmask.long.word 0x18 0.--15. 1. "RD_CHANNEL_4_DATA,The DMA uses this field to generate the data field for the Done or Abort IMWr TLPs it generates for read channel 4. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" line.long 0x1C "DMA_READ_CH67_IMWR_DATA_OFF,DMA Read Channel 7 and 6 IMWr Data Register." hexmask.long.word 0x1C 16.--31. 1. "RD_CHANNEL_7_DATA,The DMA uses this field to generate the data field for the Done or Abort IMWr TLPs it generates for read channel 7. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" hexmask.long.word 0x1C 0.--15. 1. "RD_CHANNEL_6_DATA,The DMA uses this field to generate the data field for the Done or Abort IMWr TLPs it generates for read channel 6. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" rgroup.long (0x108+0xC8000)++0x7 line.long 0x0 "DMA_WRITE_ENGINE_HSHAKE_CNT_LOW_OFF,DMA Write Engine Handshake Counter Channel 0/1/2/3 Register." bitfld.long 0x0 29.--31. "RSVDP_29,Reserved for future use." "0,1,2,3,4,5,6,7" hexmask.long.byte 0x0 24.--28. 1. "DMA_WRITE_ENGINE_HSHAKE_CNT_CH3,DMA handshake counter for DMA Write Engine Channel 3. If CC_DMA_HSHAKE =1 the data transfer in Linked List mode starts only when the counter is non-zero." newline bitfld.long 0x0 21.--23. "RSVDP_21,Reserved for future use." "0,1,2,3,4,5,6,7" hexmask.long.byte 0x0 16.--20. 1. "DMA_WRITE_ENGINE_HSHAKE_CNT_CH2,DMA handshake counter for DMA Write Engine Channel 2. If CC_DMA_HSHAKE =1 the data transfer in Linked List mode starts only when the counter is non-zero." newline bitfld.long 0x0 13.--15. "RSVDP_13,Reserved for future use." "0,1,2,3,4,5,6,7" hexmask.long.byte 0x0 8.--12. 1. "DMA_WRITE_ENGINE_HSHAKE_CNT_CH1,DMA handshake counter for DMA Write Engine Channel 1. If CC_DMA_HSHAKE =1 the data transfer in Linked List mode starts only when the counter is non-zero." newline bitfld.long 0x0 5.--7. "RSVDP_5,Reserved for future use." "0,1,2,3,4,5,6,7" hexmask.long.byte 0x0 0.--4. 1. "DMA_WRITE_ENGINE_HSHAKE_CNT_CH0,DMA handshake counter for DMA Write Engine Channel 0. If CC_DMA_HSHAKE =1 the data transfer in Linked List mode starts only when the counter is non-zero." line.long 0x4 "DMA_WRITE_ENGINE_HSHAKE_CNT_HIGH_OFF,DMA Write Engine Handshake Counter Channel 4/5/6/7 Register." bitfld.long 0x4 29.--31. "RSVDP_29,Reserved for future use." "0,1,2,3,4,5,6,7" hexmask.long.byte 0x4 24.--28. 1. "DMA_WRITE_ENGINE_HSHAKE_CNT_CH7,DMA handshake counter for DMA Write Engine Channel 7. If CC_DMA_HSHAKE =1 the data transfer in Linked List mode starts only when the counter is non-zero." newline bitfld.long 0x4 21.--23. "RSVDP_21,Reserved for future use." "0,1,2,3,4,5,6,7" hexmask.long.byte 0x4 16.--20. 1. "DMA_WRITE_ENGINE_HSHAKE_CNT_CH6,DMA handshake counter for DMA Write Engine Channel 6. If CC_DMA_HSHAKE =1 the data transfer in Linked List mode starts only when the counter is non-zero." newline bitfld.long 0x4 13.--15. "RSVDP_13,Reserved for future use." "0,1,2,3,4,5,6,7" hexmask.long.byte 0x4 8.--12. 1. "DMA_WRITE_ENGINE_HSHAKE_CNT_CH5,DMA handshake counter for DMA Write Engine Channel 5. If CC_DMA_HSHAKE =1 the data transfer in Linked List mode starts only when the counter is non-zero." newline bitfld.long 0x4 5.--7. "RSVDP_5,Reserved for future use." "0,1,2,3,4,5,6,7" hexmask.long.byte 0x4 0.--4. 1. "DMA_WRITE_ENGINE_HSHAKE_CNT_CH4,DMA handshake counter for DMA Write Engine Channel 4. If CC_DMA_HSHAKE =1 the data transfer in Linked List mode starts only when the counter is non-zero." rgroup.long (0x118+0xC8000)++0x7 line.long 0x0 "DMA_READ_ENGINE_HSHAKE_CNT_LOW_OFF,DMA Read Engine Handshake Counter Channel 0/1/2/3 Register." bitfld.long 0x0 29.--31. "RSVDP_29,Reserved for future use." "0,1,2,3,4,5,6,7" hexmask.long.byte 0x0 24.--28. 1. "DMA_READ_ENGINE_HSHAKE_CNT_CH3,DMA handshake counter for DMA Read Engine Channel 3. If CC_DMA_HSHAKE =1 the data transfer in Linked List mode starts only when the counter is non-zero." newline bitfld.long 0x0 21.--23. "RSVDP_21,Reserved for future use." "0,1,2,3,4,5,6,7" hexmask.long.byte 0x0 16.--20. 1. "DMA_READ_ENGINE_HSHAKE_CNT_CH2,DMA handshake counter for DMA Read Engine Channel 2. If CC_DMA_HSHAKE =1 the data transfer in Linked List mode starts only when the counter is non-zero." newline bitfld.long 0x0 13.--15. "RSVDP_13,Reserved for future use." "0,1,2,3,4,5,6,7" hexmask.long.byte 0x0 8.--12. 1. "DMA_READ_ENGINE_HSHAKE_CNT_CH1,DMA handshake counter for DMA Read Engine Channel 1. If CC_DMA_HSHAKE =1 the data transfer in Linked List mode starts only when the counter is non-zero." newline bitfld.long 0x0 5.--7. "RSVDP_5,Reserved for future use." "0,1,2,3,4,5,6,7" hexmask.long.byte 0x0 0.--4. 1. "DMA_READ_ENGINE_HSHAKE_CNT_CH0,DMA handshake counter for DMA Read Engine Channel 0. If CC_DMA_HSHAKE =1 the data transfer in Linked List mode starts only when the counter is non-zero." line.long 0x4 "DMA_READ_ENGINE_HSHAKE_CNT_HIGH_OFF,DMA Read Engine Handshake Counter Channel 4/5/6/7 Register." bitfld.long 0x4 29.--31. "RSVDP_29,Reserved for future use." "0,1,2,3,4,5,6,7" hexmask.long.byte 0x4 24.--28. 1. "DMA_READ_ENGINE_HSHAKE_CNT_CH7,DMA handshake counter for DMA Read Engine Channel 7. If CC_DMA_HSHAKE =1 the data transfer in Linked List mode starts only when the counter is non-zero." newline bitfld.long 0x4 21.--23. "RSVDP_21,Reserved for future use." "0,1,2,3,4,5,6,7" hexmask.long.byte 0x4 16.--20. 1. "DMA_READ_ENGINE_HSHAKE_CNT_CH6,DMA handshake counter for DMA Read Engine Channel 6. If CC_DMA_HSHAKE =1 the data transfer in Linked List mode starts only when the counter is non-zero." newline bitfld.long 0x4 13.--15. "RSVDP_13,Reserved for future use." "0,1,2,3,4,5,6,7" hexmask.long.byte 0x4 8.--12. 1. "DMA_READ_ENGINE_HSHAKE_CNT_CH5,DMA handshake counter for DMA Read Engine Channel 5. If CC_DMA_HSHAKE =1 the data transfer in Linked List mode starts only when the counter is non-zero." newline bitfld.long 0x4 5.--7. "RSVDP_5,Reserved for future use." "0,1,2,3,4,5,6,7" hexmask.long.byte 0x4 0.--4. 1. "DMA_READ_ENGINE_HSHAKE_CNT_CH4,DMA handshake counter for DMA Read Engine Channel 4. If CC_DMA_HSHAKE =1 the data transfer in Linked List mode starts only when the counter is non-zero." repeat 8. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 )(list 0x0 0x200 0x400 0x600 0x800 0xA00 0xC00 0xE00 ) group.long ($2+0x200+0xC8000)++0x3 line.long 0x0 "DMA_CH_CONTROL1_OFF_WRCH_$1,DMA Write Channel Control 1 Register." bitfld.long 0x0 30.--31. "DMA_AT,Address Translation TLP Header Bit (AT) The DMA uses this TLP header field when generating MRd/MWr (not IMWr) TLPs. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" "0,1,2,3" bitfld.long 0x0 27.--29. "DMA_TC,Traffic Class TLP Header Bit (TC) The DMA uses this TLP header field when generating MRd/MWr (not IMWr) TLPs. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 26. "DMA_RESERVED5,Reserved. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" "0,1" bitfld.long 0x0 25. "DMA_RO,Relaxed Ordering TLP Header Bit (RO) The DMA uses this TLP header field when generating MRd/MWr (not IMWr) TLPs. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" "0,1" newline bitfld.long 0x0 24. "DMA_NS_SRC,Source No Snoop TLP Header Bit (DMA_NS_SRC). The DMA uses this TLP header field when generating MRd (SAR addressing space) (not IMWr) TLPs. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" "0,1" bitfld.long 0x0 23. "DMA_NS_DST,Destination No Snoop TLP Header Bit (DMA_NS_DST). The DMA uses this TLP header field when generating MWr (DAR addressing space) (not IMWr) TLPs. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" "0,1" newline bitfld.long 0x0 22. "DMA_MEM_TYPE,Master AXI ACE-Lite Cache Coherency Control. This field sets the DMA channel memory type of the address space of the data transfer as follows: - 0x0:peripheral type - 0x1:memory type For more details see 'ACE-Lite Features and Limitations'.." "peripheral type,memory type" hexmask.long.byte 0x0 17.--21. 1. "DMA_RESERVED2,Reserved. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" newline hexmask.long.byte 0x0 12.--16. 1. "DMA_FUNC_NUM,Function Number (FN). The controller uses this field when generating the requester ID for the MRd/MWr DMA TLP. When you have enabled SR-IOV then this field is ignored if you have set the VFE field in the 'DMA Write Channel Control 2.." bitfld.long 0x0 10.--11. "DMA_RESERVED1,Reserved. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" "0,1,2,3" newline bitfld.long 0x0 9. "LLE,Linked List Enable (LLE). - 0: Disable linked list operation - 1: Enable linked list operation Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" "Disable linked list operation,Enable linked list operation" bitfld.long 0x0 8. "CCS,Consumer Cycle State (CCS). Used in linked list mode only. It is used to synchronize the producer (software) and the consumer (DMA). For more details see 'PCS-CCS-CB-TCB Producer-Consumer Synchronization'. You must initialize this bit. The DMA.." "0,1" newline bitfld.long 0x0 7. "DMA_RESERVED0,Reserved. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" "0,1" bitfld.long 0x0 5.--6. "CS,Channel Status (CS). The channel status bits identify the current operational state of the DMA channel. The operation state encoding for each DMA channel is a s follows: - 00: Reserved - 01: Running. This channel is active and transferring data. - 10:.." "Reserved,Running,?,?" newline bitfld.long 0x0 4. "RIE,Remote Interrupt Enable (RIE). You must set this bit to enable the generation of the Done or Abort Remote interrupts. For more details see 'Interrupts and Error Handling'. In LL mode the DMA overwrites this with the RIE of the LL element. The RIE.." "0,1" bitfld.long 0x0 3. "LIE,Local Interrupt Enable (LIE). You must set this bit to enable the generation of the Done or Abort Local interrupts. For more details see 'Interrupts and Error Handling'. In LL mode the DMA overwrites this with the LIE of the LL element. The LIE bit.." "0,1" newline bitfld.long 0x0 2. "LLP,Load Link Pointer (LLP). Used in linked list mode only. Indicates that this linked list element is a link element and its LL element pointer dwords are pointing to the next (non-contiguous) element. The DMA loads this field with the LLP of the.." "0,1" bitfld.long 0x0 1. "TCB,Toggle Cycle Bit (TCB). Indicates to the DMA to toggle its interpretation of the CB. Used in linked list mode only. It is used to synchronize the producer (software) and the consumer (DMA). For more details see 'PCS-CCS-CB-TCB Producer-Consumer.." "0,1" newline bitfld.long 0x0 0. "CB,Cycle Bit (CB). Used in linked list mode only. It is used to synchronize the producer (software) and the consumer (DMA). For more details see 'PCS-CCS-CB-TCB Producer-Consumer Synchronization'. The DMA loads this field with the CB of the linked list.." "0,1" repeat.end repeat 8. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 )(list 0x0 0x200 0x400 0x600 0x800 0xA00 0xC00 0xE00 ) group.long ($2+0x208+0xC8000)++0x3 line.long 0x0 "DMA_TRANSFER_SIZE_OFF_WRCH_$1,DMA Write Transfer Size Register." hexmask.long 0x0 0.--31. 1. "DMA_TRANSFER_SIZE,DMA Transfer Size. You program this register with the size of the DMA transfer. The maximum DMA transfer size is 4Gbytes. The minimum transfer size is one byte (0x1). This field is automatically decremented by the DMA as the DMA write.." repeat.end repeat 8. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 )(list 0x0 0x200 0x400 0x600 0x800 0xA00 0xC00 0xE00 ) group.long ($2+0x20C+0xC8000)++0x3 line.long 0x0 "DMA_SAR_LOW_OFF_WRCH_$1,DMA Write SAR Low Register." hexmask.long 0x0 0.--31. 1. "SRC_ADDR_REG_LOW,Source Address Register (Lower 32 bits). Indicates the next address to be read from. The DMA increments the SAR as the DMA transfer progresses. In LL mode the DMA overwrites this with the corresponding dword of the LL element. - DMA.." repeat.end repeat 8. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 )(list 0x0 0x200 0x400 0x600 0x800 0xA00 0xC00 0xE00 ) group.long ($2+0x210+0xC8000)++0x3 line.long 0x0 "DMA_SAR_HIGH_OFF_WRCH_$1,DMA Write SAR High Register." hexmask.long 0x0 0.--31. 1. "SRC_ADDR_REG_HIGH,Source Address Register (Higher 32 bits). In LL mode the DMA overwrites this with the corresponding dword of the LL element. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" repeat.end repeat 8. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 )(list 0x0 0x200 0x400 0x600 0x800 0xA00 0xC00 0xE00 ) group.long ($2+0x214+0xC8000)++0x3 line.long 0x0 "DMA_DAR_LOW_OFF_WRCH_$1,DMA Write DAR Low Register." hexmask.long 0x0 0.--31. 1. "DST_ADDR_REG_LOW,Destination Address Register (Lower 32 bits). Indicates the next address to be written to. The DMA increments the DAR as the DMA transfer progresses. In LL mode the DMA overwrites this with the corresponding dword of the LL element. -.." repeat.end repeat 8. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 )(list 0x0 0x200 0x400 0x600 0x800 0xA00 0xC00 0xE00 ) group.long ($2+0x218+0xC8000)++0x3 line.long 0x0 "DMA_DAR_HIGH_OFF_WRCH_$1,DMA Write DAR High Register." hexmask.long 0x0 0.--31. 1. "DST_ADDR_REG_HIGH,Destination Address Register (Higher 32 bits). In LL mode the DMA overwrites this with the corresponding dword of the LL element. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" repeat.end repeat 8. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 )(list 0x0 0x200 0x400 0x600 0x800 0xA00 0xC00 0xE00 ) group.long ($2+0x21C+0xC8000)++0x3 line.long 0x0 "DMA_LLP_LOW_OFF_WRCH_$1,DMA Write Linked List Pointer Low Register." hexmask.long 0x0 0.--31. 1. "LLP_LOW,Lower bits of the address of the linked list transfer list in local memory. Used in linked list mode only. Updated by the DMA to point to the next element in the transfer list after the previous element is consumed. - When the current element is.." repeat.end repeat 8. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 )(list 0x0 0x200 0x400 0x600 0x800 0xA00 0xC00 0xE00 ) group.long ($2+0x220+0xC8000)++0x3 line.long 0x0 "DMA_LLP_HIGH_OFF_WRCH_$1,DMA Write Linked List Pointer High Register." hexmask.long 0x0 0.--31. 1. "LLP_HIGH,Upper 32 bits of the address of the linked list transfer list in local memory. Used in linked list mode only. Updated by the DMA to point to the next element in the transfer list as elements are consumed. Note: The access attributes of this.." repeat.end repeat 8. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 )(list 0x0 0x200 0x400 0x600 0x800 0xA00 0xC00 0xE00 ) group.long ($2+0x300+0xC8000)++0x3 line.long 0x0 "DMA_CH_CONTROL1_OFF_RDCH_$1,DMA Read Channel Control 1 Register." bitfld.long 0x0 30.--31. "DMA_AT,Address Translation TLP Header Bit (AT) The DMA uses this TLP header field when generating MRd/MWr (not IMWr) TLPs. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" "0,1,2,3" bitfld.long 0x0 27.--29. "DMA_TC,Traffic Class TLP Header Bit (TC) The DMA uses this TLP header field when generating MRd/MWr (not IMWr) TLPs. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 26. "DMA_RESERVED5,Reserved. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" "0,1" bitfld.long 0x0 25. "DMA_RO,Relaxed Ordering TLP Header Bit (RO) The DMA uses this TLP header field when generating MRd/MWr (not IMWr) TLPs. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" "0,1" newline bitfld.long 0x0 24. "DMA_NS_SRC,Source No Snoop TLP Header Bit (DMA_NS_SRC). The DMA uses this TLP header field when generating MRd (SAR addressing space) (not IMWr) TLPs. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" "0,1" bitfld.long 0x0 23. "DMA_NS_DST,Destination No Snoop TLP Header Bit (DMA_NS_DST). The DMA uses this TLP header field when generating MWr (DAR addressing space) (not IMWr) TLPs. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" "0,1" newline bitfld.long 0x0 22. "DMA_MEM_TYPE,Master AXI ACE-Lite Cache Coherency Control. This field sets the DMA channel memory type of the address space of the data transfer as follows: - 0x0:peripheral type - 0x1:memory type For more details see 'ACE-Lite Features and Limitations'.." "peripheral type,memory type" hexmask.long.byte 0x0 17.--21. 1. "DMA_RESERVED2,Reserved. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" newline hexmask.long.byte 0x0 12.--16. 1. "DMA_FUNC_NUM,Function Number (FN). The controller uses this field when generating the requester ID for the MRd/MWr DMA TLP. When you have enabled SR-IOV then this field is ignored if you have set the VFE field in the 'DMA Read Channel Control 2.." bitfld.long 0x0 10.--11. "DMA_RESERVED1,Reserved. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" "0,1,2,3" newline bitfld.long 0x0 9. "LLE,Linked List Enable (LLE). - 0: Disable linked list operation - 1: Enable linked list operation Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" "Disable linked list operation,Enable linked list operation" bitfld.long 0x0 8. "CCS,Consumer Cycle State (CCS). Used in linked list mode only. It is used to synchronize the producer (software) and the consumer (DMA). For more details see 'PCS-CCS-CB-TCB Producer-Consumer Synchronization'. You must initialize this bit. The DMA.." "0,1" newline bitfld.long 0x0 7. "DMA_RESERVED0,Reserved. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" "0,1" bitfld.long 0x0 5.--6. "CS,Channel Status (CS). The channel status bits identify the current operational state of the DMA channel. The operation state encoding for each DMA channel is a s follows: - 00: Reserved - 01: Running. This channel is active and transferring data. - 10:.." "Reserved,Running,?,?" newline bitfld.long 0x0 4. "RIE,Remote Interrupt Enable (RIE). You must set this bit to enable the generation of the Done or Abort Remote interrupts. For more details see 'Interrupts and Error Handling'. In LL mode the DMA overwrites this with the RIE of the LL element. The RIE.." "0,1" bitfld.long 0x0 3. "LIE,Local Interrupt Enable (LIE). You must set this bit to enable the generation of the Done or Abort Local interrupts. For more details see 'Interrupts and Error Handling'. In LL mode the DMA overwrites this with the LIE of the LL element. The LIE bit.." "0,1" newline bitfld.long 0x0 2. "LLP,Load Link Pointer (LLP). Used in linked list mode only. Indicates that this linked list element is a link element and its LL element pointer dwords are pointing to the next (non-contiguous) element. The DMA loads this field with the LLP of the.." "0,1" bitfld.long 0x0 1. "TCB,Toggle Cycle Bit (TCB). Indicates to the DMA to toggle its interpretation of the CB. Used in linked list mode only. It is used to synchronize the producer (software) and the consumer (DMA). For more details see 'PCS-CCS-CB-TCB Producer-Consumer.." "0,1" newline bitfld.long 0x0 0. "CB,Cycle Bit (CB). Used in linked list mode only. It is used to synchronize the producer (software) and the consumer (DMA). For more details see 'PCS-CCS-CB-TCB Producer-Consumer Synchronization'. The DMA loads this field with the CB of the linked list.." "0,1" repeat.end repeat 8. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 )(list 0x0 0x200 0x400 0x600 0x800 0xA00 0xC00 0xE00 ) group.long ($2+0x308+0xC8000)++0x3 line.long 0x0 "DMA_TRANSFER_SIZE_OFF_RDCH_$1,DMA Read Transfer Size Register." hexmask.long 0x0 0.--31. 1. "DMA_TRANSFER_SIZE,DMA Transfer Size. You program this register with the size of the DMA transfer. The maximum DMA transfer size is 4Gbytes. The minimum transfer size is one byte (0x1). This field is automatically decremented by the DMA as the DMA read.." repeat.end repeat 8. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 )(list 0x0 0x200 0x400 0x600 0x800 0xA00 0xC00 0xE00 ) group.long ($2+0x30C+0xC8000)++0x3 line.long 0x0 "DMA_SAR_LOW_OFF_RDCH_$1,DMA Read SAR Low Register." hexmask.long 0x0 0.--31. 1. "SRC_ADDR_REG_LOW,Source Address Register (Lower 32 bits). Indicates the next address to be read from. The DMA increments the SAR as the DMA transfer progresses. In LL mode the DMA overwrites this with the corresponding dword of the LL element. - DMA.." repeat.end repeat 8. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 )(list 0x0 0x200 0x400 0x600 0x800 0xA00 0xC00 0xE00 ) group.long ($2+0x310+0xC8000)++0x3 line.long 0x0 "DMA_SAR_HIGH_OFF_RDCH_$1,DMA Read SAR High Register." hexmask.long 0x0 0.--31. 1. "SRC_ADDR_REG_HIGH,Source Address Register (Higher 32 bits). In LL mode the DMA overwrites this with the corresponding dword of the LL element. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" repeat.end repeat 8. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 )(list 0x0 0x200 0x400 0x600 0x800 0xA00 0xC00 0xE00 ) group.long ($2+0x314+0xC8000)++0x3 line.long 0x0 "DMA_DAR_LOW_OFF_RDCH_$1,DMA Read DAR Low Register." hexmask.long 0x0 0.--31. 1. "DST_ADDR_REG_LOW,Destination Address Register (Lower 32 bits). Indicates the next address to be written to. The DMA increments the DAR as the DMA transfer progresses. In LL mode the DMA overwrites this with the corresponding dword of the LL element. -.." repeat.end repeat 8. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 )(list 0x0 0x200 0x400 0x600 0x800 0xA00 0xC00 0xE00 ) group.long ($2+0x318+0xC8000)++0x3 line.long 0x0 "DMA_DAR_HIGH_OFF_RDCH_$1,DMA Read DAR High Register." hexmask.long 0x0 0.--31. 1. "DST_ADDR_REG_HIGH,Destination Address Register (Higher 32 bits). In LL mode the DMA overwrites this with the corresponding dword of the LL element. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" repeat.end repeat 8. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 )(list 0x0 0x200 0x400 0x600 0x800 0xA00 0xC00 0xE00 ) group.long ($2+0x31C+0xC8000)++0x3 line.long 0x0 "DMA_LLP_LOW_OFF_RDCH_$1,DMA Read Linked List Pointer Low Register." hexmask.long 0x0 0.--31. 1. "LLP_LOW,Lower bits of the address of the linked list transfer list in local memory. Used in linked list mode only. Updated by the DMA to point to the next element in the transfer list after the previous element is consumed. - When the current element is.." repeat.end repeat 8. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 )(list 0x0 0x200 0x400 0x600 0x800 0xA00 0xC00 0xE00 ) group.long ($2+0x320+0xC8000)++0x3 line.long 0x0 "DMA_LLP_HIGH_OFF_RDCH_$1,DMA Read Linked List Pointer High Register." hexmask.long 0x0 0.--31. 1. "LLP_HIGH,Upper 32 bits of the address of the linked list transfer list in local memory. Used in linked list mode only. Updated by the DMA to point to the next element in the transfer list as elements are consumed. Note: The access attributes of this.." repeat.end tree.end tree "PF0_ATU_CAP (ATU Por Logic Structure)" repeat 8. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 )(list 0x0 0x200 0x400 0x600 0x800 0xA00 0xC00 0xE00 ) group.long ($2+0xC0000)++0x3 line.long 0x0 "IATU_REGION_CTRL_1_OFF_OUTBOUND_$1,iATU Region Control 1 Register." bitfld.long 0x0 20. "CTRL_1_FUNC_NUM,Function Number. - When the address of an outbound TLP is matched to this region and the FUNC_BYPASS field in the 'iATU Control 2 Register' is '0' then the function number used in generating the function part of the requester ID (RID).." "0,1" newline bitfld.long 0x0 13. "INCREASE_REGION_SIZE,Increase the maximum ATU Region size. When set the maximum ATU Region size is determined by CX_ATU_MAX_REGION_SIZE. When clear the maximum ATU Region size is 4 GB (default). Note: This register field is sticky." "0,1" newline bitfld.long 0x0 9.--10. "ATTR,When the address of an outbound TLP is matched to this region then the ATTR field of the TLP is changed to the value in this register. Note: This register field is sticky." "0,1,2,3" newline bitfld.long 0x0 8. "TD,This is a reserved field. Do not use. Note: This register field is sticky." "0,1" newline bitfld.long 0x0 5.--7. "TC,When the address of an outbound TLP is matched to this region then the TC field of the TLP is changed to the value in this register. Note: This register field is sticky." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x0 0.--4. 1. "TYPE,When the address of an outbound TLP is matched to this region then the TYPE field of the TLP is changed to the value in this register. Note: This register field is sticky." repeat.end repeat 8. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 )(list 0x0 0x200 0x400 0x600 0x800 0xA00 0xC00 0xE00 ) group.long ($2+0x4+0xC0000)++0x3 line.long 0x0 "IATU_REGION_CTRL_2_OFF_OUTBOUND_$1,iATU Region Control 2 Register." bitfld.long 0x0 31. "REGION_EN,Region Enable. This bit must be set to '1' for address translation to take place. Note: This register field is sticky." "0,1" newline bitfld.long 0x0 29. "INVERT_MODE,Invert Mode. When set the address matching region is inverted. Therefore an address match occurs when the untranslated address is in the region outside the defined range (Base Address to Limit Address). Note: This register field is sticky." "0,1" newline bitfld.long 0x0 28. "CFG_SHIFT_MODE,CFG Shift Mode. The iATU uses bits [27:12] of the untranslated address (on the XALI0/1/2 interface or AXI slave interface address) to form the BDF number of the outgoing CFG TLP. This supports the Enhanced Configuration Address Mapping.." "0,1" newline bitfld.long 0x0 27. "DMA_BYPASS,DMA Bypass Mode. Allows request TLPs which are initiated by the DMA controller to pass through the iATU untranslated. Note: This field is reserved for the SW product. You must set it to '0'. Note: This register field is sticky." "0,1" newline bitfld.long 0x0 23. "HEADER_SUBSTITUTE_EN,Header Substitute Enable. When enabled and region address is matched the iATU fully substitutes bytes 8-11 (for 3 DWORD header) or bytes 12-15 (for 4 DWORD header) of the outbound TLP header with the contents of the LWR_TARGET_RW.." "LWR_TARGET_RW in the..,LWR_TARGET_RW in the.." newline bitfld.long 0x0 22. "INHIBIT_PAYLOAD,Inhibit TLP Payload Data for TLP's in Matched Region; assign iATU region to be TLP without data. When enabled and region address is matched the iATU marks all TLPs as having no payload data by forcing the TLP header Fmt[1] bit =0.." "Fmt[1] =0/1 so that TLPs with or without data..,Fmt[1] =0 so that only TLP type without data is.." newline bitfld.long 0x0 21. "TLP_HEADER_FIELDS_BYPASS,TLP Header Fields Translation Bypass. In this mode header fields of the translated TLP is taken from your application transmit interface or if AMBA is configured from the AMBA sideband bus (slv_awmisc_info) and not from the.." "0,1" newline bitfld.long 0x0 20. "SNP,Serialize Non-Posted Requests. In this mode when the AXI Bridge is populated same AXI ID Non-Posted Read/Write Requests are transmitted on the wire if there are no other same ID Non-Posted Requests outstanding. Note: This register field is sticky." "0,1" newline bitfld.long 0x0 19. "FUNC_BYPASS,Function Number Translation Bypass. In this mode the function number of the translated TLP is taken from your application transmit interface and not from the CTRL_1_FUNC_NUM field of the 'iATU Control 1 Register' or the VF_NUMBER field of.." "0,1" newline bitfld.long 0x0 16. "TAG_SUBSTITUTE_EN,TAG Substitute Enable. When enabled and region address is matched the iATU substitutes the TAG field of the outbound TLP header with the contents of the TAG field in this register. The expected usage scenario is translation from AXI.." "0,1" newline hexmask.long.byte 0x0 8.--15. 1. "TAG,TAG. The substituted TAG field (byte 6) in the outgoing TLP header when TAG_SUBSTITUTE_EN is set. Note: This register field is sticky." newline hexmask.long.byte 0x0 0.--7. 1. "MSG_CODE,MSG TLPs (Message Code). When the address of an outbound TLP is matched to this region and the translated TLP TYPE field is Msg or MsgD; then the message field of the TLP is changed to the value in this register. Memory TLPs: (ST;Steering Tag)." repeat.end repeat 8. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 )(list 0x0 0x200 0x400 0x600 0x800 0xA00 0xC00 0xE00 ) group.long ($2+0x8+0xC0000)++0x3 line.long 0x0 "IATU_LWR_BASE_ADDR_OFF_OUTBOUND_$1,iATU Lower Base Address Register. The CX_ATU_MIN_REGION_SIZE configuration parameter (Value Range: 4 kB. 8 kB. 16 kB. 32 kB. 64 kB defaults to 64 kB) specifies the minimum size of an address translation region. For.." hexmask.long.tbyte 0x0 12.--31. 1. "LWR_BASE_RW,Forms bits [31:n] of the start address of the address region to be translated. n is log2(CX_ATU_MIN_REGION_SIZE) Note: This register field is sticky." newline hexmask.long.word 0x0 0.--11. 1. "LWR_BASE_HW,Forms bits [n-1:0] of the start address of the address region to be translated. The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary so these bits are always 0. A write to this location is ignored by the PCIe controller." repeat.end repeat 8. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 )(list 0x0 0x200 0x400 0x600 0x800 0xA00 0xC00 0xE00 ) group.long ($2+0xC+0xC0000)++0x3 line.long 0x0 "IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_$1,iATU Upper Base Address Register." hexmask.long 0x0 0.--31. 1. "UPPER_BASE_RW,Forms bits [63:32] of the start (and end) address of the address region to be translated. In systems with a 32-bit address space this register is not used and therefore writing to this register has no effect. Note: This register field is.." repeat.end repeat 8. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 )(list 0x0 0x200 0x400 0x600 0x800 0xA00 0xC00 0xE00 ) group.long ($2+0x10+0xC0000)++0x3 line.long 0x0 "IATU_LIMIT_ADDR_OFF_OUTBOUND_$1,iATU Limit Address Register." hexmask.long.tbyte 0x0 12.--31. 1. "LIMIT_ADDR_RW,Forms upper bits of the end address of the address region to be translated. Note: This register field is sticky." newline hexmask.long.word 0x0 0.--11. 1. "LIMIT_ADDR_HW,Forms lower bits of the end address of the address region to be translated. The end address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary so these bits are always all ones. A write to this location is ignored by the PCIe.." repeat.end repeat 8. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 )(list 0x0 0x200 0x400 0x600 0x800 0xA00 0xC00 0xE00 ) group.long ($2+0x14+0xC0000)++0x3 line.long 0x0 "IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_$1,iATU Lower Target Address Register." hexmask.long 0x0 0.--31. 1. "LWR_TARGET_RW_OUTBOUND,When HEADER_SUBSTITUTE_EN in IATU_REGION_CTRL_2_OFF_OUTBOUND_ is '0' (normal operation): - LWR_TARGET_RW[31:n] forms MSB's of the Lower Target part of the new address of the translated region; - LWR_TARGET_RW[n-1:0] are not used." repeat.end repeat 8. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 )(list 0x0 0x200 0x400 0x600 0x800 0xA00 0xC00 0xE00 ) group.long ($2+0x18+0xC0000)++0x3 line.long 0x0 "IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_$1,iATU Upper Target Address Register." hexmask.long 0x0 0.--31. 1. "UPPER_TARGET_RW,Forms bits [63:32] of the start address (Upper Target part) of the new address of the translated region. Note: This register field is sticky." repeat.end repeat 8. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 )(list 0x0 0x200 0x400 0x600 0x800 0xA00 0xC00 0xE00 ) group.long ($2+0x100+0xC0000)++0x3 line.long 0x0 "IATU_REGION_CTRL_1_OFF_INBOUND_$1,iATU Region Control 1 Register." bitfld.long 0x0 20. "CTRL_1_FUNC_NUM,Function Number. - MEM-I/O: When the Address and BAR matching logic in the controller indicate that a MEM-I/O transaction matches a BAR in the function corresponding to this value then address translation proceeds. This check is only.." "?,When the destination function number as.." newline bitfld.long 0x0 13. "INCREASE_REGION_SIZE,Increase the maximum ATU Region size. When set the maximum ATU Region size is determined by CX_ATU_MAX_REGION_SIZE. When clear the maximum ATU Region size is 4 GB (default). Note: This register field is sticky." "0,1" newline bitfld.long 0x0 9.--10. "ATTR,When the ATTR field of an inbound TLP is matched to this value then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the 'ATTR Match Enable' bit of the 'iATU Control 2 Register' is.." "0,1,2,3" newline bitfld.long 0x0 8. "TD,When the TD field of an inbound TLP is matched to this value then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the 'TD Match Enable' bit of the 'iATU Control 2 Register' is set." "0,1" newline bitfld.long 0x0 5.--7. "TC,When the TC field of an inbound TLP is matched to this value then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the 'TC Match Enable' bit of the 'iATU Control 2 Register' is set." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x0 0.--4. 1. "TYPE,When the TYPE field of an inbound TLP is matched to this value then address translation proceeds (when all other enabled field-matches are successful). Note: This register field is sticky." repeat.end repeat 8. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 )(list 0x0 0x200 0x400 0x600 0x800 0xA00 0xC00 0xE00 ) group.long ($2+0x104+0xC0000)++0x3 line.long 0x0 "IATU_REGION_CTRL_2_OFF_INBOUND_$1,iATU Region Control 2 Register." bitfld.long 0x0 31. "REGION_EN,Region Enable. This bit must be set to '1' for address translation to take place. Note: This register field is sticky." "0,1" newline bitfld.long 0x0 30. "MATCH_MODE,Match Mode. Determines Inbound matching mode for TLPs. The mode depends on the type of TLP that is received as follows: For MEM-I/O TLPs this field is interpreted as follows: - 0: Address Match Mode. The iATU operates using addresses as in.." "Address Match Mode,Vendor ID Match Mode" newline bitfld.long 0x0 29. "INVERT_MODE,Invert Mode. When set the address matching region is inverted. Therefore an address match occurs when the untranslated address is in the region outside the defined range (Base Address to Limit Address). Note: This register field is sticky." "0,1" newline bitfld.long 0x0 28. "CFG_SHIFT_MODE,CFG Shift Mode. This is useful for CFG transactions where the PCIe configuration mechanism maps bits [27:12] of the address to the bus/device and function number. This allows a CFG configuration space to be located in any 256MB window of.." "0,1" newline bitfld.long 0x0 27. "FUZZY_TYPE_MATCH_CODE,Fuzzy Type Match Mode. When enabled the iATU relaxes the matching of the TLP TYPE field against the expected TYPE field so that - CfgRd0 and CfgRd1 TLPs are seen as identical. Similarly with CfgWr0 and CfgWr1. - MWr MRd and MRdLk.." "0,1" newline bitfld.long 0x0 24.--25. "RESPONSE_CODE,Response Code. Defines the type of response to give for accesses matching this region. This overrides the normal RADM filter response. Note that this feature is not available for any region where Single Address Location Translate is.." "Normal RADM filter response is used,Unsupported request,?,?" newline bitfld.long 0x0 23. "SINGLE_ADDR_LOC_TRANS_EN,Single Address Location Translate Enable. When enabled Rx TLPs can be translated to a single address location as determined by the target address register of the iATU region. The main usage scenario is translation of Messages.." "0,1" newline bitfld.long 0x0 21. "MSG_CODE_MATCH_EN,Message Code Match Enable (Msg TLPS). Ensures that a successful message Code TLP field comparison match (see Message Code field of the 'iATU Control 2 Register') occurs (in MSG transactions) for address translation to proceed. ST Match.." "0,1" newline bitfld.long 0x0 19. "FUNC_NUM_MATCH_EN,Function Number Match Enable. Ensures that a successful Function Number TLP field comparison match (see Function Number field of the 'iATU Control 1 Register') occurs (in MEM-I/O and CFG0/CFG1 transactions) for address translation to.." "0,1" newline bitfld.long 0x0 16. "ATTR_MATCH_EN,ATTR Match Enable. Ensures that a successful ATTR TLP field comparison match (see ATTR field of the 'iATU Control 1 Register') occurs for address translation to proceed. Note: This register field is sticky." "0,1" newline bitfld.long 0x0 15. "TD_MATCH_EN,TD Match Enable. Ensures that a successful TD TLP field comparison match (see TD field of the 'iATU Control 1 Register') occurs for address translation to proceed. Note: This register field is sticky." "0,1" newline bitfld.long 0x0 14. "TC_MATCH_EN,TC Match Enable. Ensures that a successful TC TLP field comparison match (see TC field of the 'iATU Control 1 Register') occurs for address translation to proceed. Note: This register field is sticky." "0,1" newline bitfld.long 0x0 13. "MSG_TYPE_MATCH_MODE,Message Type Match Mode. When enabled and if single address location translate enable is set then inbound TLPs of type MSG/MSGd which match the type field of the iatu_region_ctrl_1_OFF_inbound register (=>TYPE[4:3]=2'b10) will be.." "0,1" newline bitfld.long 0x0 8.--10. "BAR_NUM,BAR Number. When the BAR number of an inbound MEM or IO TLP ' that is matched by the normal internal BAR address matching mechanism ' is the same as this field address translation proceeds (when all other enabled field-matches are successful)." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x0 0.--7. 1. "MSG_CODE,MSG TLPs: (Message Code). When the TYPE field of an inbound Msg/MsgD TLP is matched to this value then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the 'Message Code Match.." repeat.end repeat 8. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 )(list 0x0 0x200 0x400 0x600 0x800 0xA00 0xC00 0xE00 ) group.long ($2+0x108+0xC0000)++0x3 line.long 0x0 "IATU_LWR_BASE_ADDR_OFF_INBOUND_$1,iATU Lower Base Address Register. The CX_ATU_MIN_REGION_SIZE configuration parameter (Value Range: 4 kB. 8 kB. 16 kB. 32 kB. 64 kB defaults to 64 kB) specifies the minimum size of an address translation region. For.." hexmask.long.tbyte 0x0 12.--31. 1. "LWR_BASE_RW,Forms bits [31:n] of the start address of the address region to be translated. n is log2(CX_ATU_MIN_REGION_SIZE) Note: This register field is sticky." newline hexmask.long.word 0x0 0.--11. 1. "LWR_BASE_HW,Forms bits [n-1:0] of the start address of the address region to be translated. The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary so these bits are always 0. A write to this location is ignored by the PCIe controller." repeat.end repeat 8. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 )(list 0x0 0x200 0x400 0x600 0x800 0xA00 0xC00 0xE00 ) group.long ($2+0x10C+0xC0000)++0x3 line.long 0x0 "IATU_UPPER_BASE_ADDR_OFF_INBOUND_$1,iATU Upper Base Address Register." hexmask.long 0x0 0.--31. 1. "UPPER_BASE_RW,Forms bits [63:32] of the start (and end) address of the address region to be translated. Note: This register field is sticky." repeat.end repeat 8. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 )(list 0x0 0x200 0x400 0x600 0x800 0xA00 0xC00 0xE00 ) group.long ($2+0x110+0xC0000)++0x3 line.long 0x0 "IATU_LIMIT_ADDR_OFF_INBOUND_$1,iATU Limit Address Register." hexmask.long.tbyte 0x0 12.--31. 1. "LIMIT_ADDR_RW,Forms upper bits of the end address of the address region to be translated. Note: This register field is sticky." newline hexmask.long.word 0x0 0.--11. 1. "LIMIT_ADDR_HW,Forms lower bits of the end address of the address region to be translated. The end address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary so these bits are always all ones. A write to this location is ignored by the PCIe.." repeat.end repeat 8. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 )(list 0x0 0x200 0x400 0x600 0x800 0xA00 0xC00 0xE00 ) group.long ($2+0x114+0xC0000)++0x3 line.long 0x0 "IATU_LWR_TARGET_ADDR_OFF_INBOUND_$1,iATU Lower Target Address Register." hexmask.long.tbyte 0x0 12.--31. 1. "LWR_TARGET_RW,Forms MSB's of the Lower Target part of the new address of the translated region. These bits are always '0'. - Field size depends on log2(CX_ATU_MIN_REGION_SIZE) in address match mode. - Field size depends on log2(BAR_MASK+1) in BAR match.." newline hexmask.long.word 0x0 0.--11. 1. "LWR_TARGET_HW,Forms the LSB's of the Lower Target part of the new address of the translated region. The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary (in address match mode); and to the Bar size boundary (in BAR match mode) so.." repeat.end repeat 8. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 )(list 0x0 0x200 0x400 0x600 0x800 0xA00 0xC00 0xE00 ) group.long ($2+0x118+0xC0000)++0x3 line.long 0x0 "IATU_UPPER_TARGET_ADDR_OFF_INBOUND_$1,iATU Upper Target Address Register." hexmask.long 0x0 0.--31. 1. "UPPER_TARGET_RW,Forms bits [63:32] of the start address (Upper Target part) of the new address of the translated region. In systems with a 32-bit address space this register is not used and therefore writing to this register has no effect. Note: This.." repeat.end tree.end tree "PF0_PORT_LOGIC (Port Logic)" group.long (0x0+0x700)++0x27 line.long 0x0 "ACK_LATENCY_TIMER_OFF,Ack Latency Timer and Replay Timer Register." hexmask.long.word 0x0 16.--31. 1. "REPLAY_TIME_LIMIT,Replay Timer Limit. The replay timer expires when it reaches this limit. The controller initiates a replay upon reception of a NAK or when the replay timer expires. For more details see 'Transmit Replay'. You can modify the effective.." newline hexmask.long.word 0x0 0.--15. 1. "ROUND_TRIP_LATENCY_TIME_LIMIT,Ack Latency Timer Limit. The Ack latency timer expires when it reaches this limit. For more details see 'Ack Scheduling'. You can modify the effective timer limit with the TIMER_MOD_ACK_NAK field of the.." line.long 0x4 "VENDOR_SPEC_DLLP_OFF,Vendor Specific DLLP Register." hexmask.long 0x4 0.--31. 1. "VENDOR_SPEC_DLLP,Vendor Specific DLLP Register. Used to send a specific PCI Express DLLP. Your application writes the 8-bit DLLP Type and 24-bits of Payload data into this register then sets the field VENDOR_SPECIFIC_DLLP_REQ of PORT_LINK_CTRL_OFF to.." line.long 0x8 "PORT_FORCE_OFF,Port Force Link Register." hexmask.long.byte 0x8 24.--31. 1. "RSVDP_24,Reserved for future use." newline bitfld.long 0x8 23. "DO_DESKEW_FOR_SRIS,Use the transitions from TS2 to Logical Idle Symbol SKP OS to Logical Idle Symbol EIEOS to Logical Idle Symbol and FTS Sequence to SKP OS to do deskew instead of using received SKP OS or TS1 to TS2 transition if DO_DESKEW_FOR_SRIS.." "0,1" newline rbitfld.long 0x8 22. "RSVDP_22,Reserved for future use." "0,1" newline hexmask.long.byte 0x8 16.--21. 1. "LINK_STATE,Forced LTSSM State. The LTSSM state that the controller is forced to when you set the FORCE_EN bit (Force Link). LTSSM state encoding is defined by the lts_state variable in workspace/src/Layer1/smlh_ltssm.v. Note: This register field is sticky." newline bitfld.long 0x8 15. "FORCE_EN,Force Link. The controller supports a testing and debug capability to allow your software to force the LTSSM state machine into a specific state and to force the controller to transmit a specific Link Command. Asserting this bit triggers the.." "0,1" newline rbitfld.long 0x8 12.--14. "RSVDP_12,Reserved for future use." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x8 8.--11. 1. "FORCED_LTSSM,Forced Link Command. The link command that the controller is forced to transmit when you set FORCE_EN bit (Force Link). Link command encoding is defined by the ltssm_cmd variable in workspace/src/Layer1/smlh_ltssm.v. Note: This register.." newline hexmask.long.byte 0x8 0.--7. 1. "LINK_NUM,Link Number. Not used for endpoint. Not used for M-PCIe. Note: This register field is sticky." line.long 0xC "ACK_F_ASPM_CTRL_OFF,Ack Frequency and L0-L1 ASPM Control Register." rbitfld.long 0xC 31. "RSVDP_31,Reserved for future use." "0,1" newline bitfld.long 0xC 30. "ENTER_ASPM,ASPM L1 Entry Control. - 1: Controller enters ASPM L1 after a period in which it has been idle. - 0: Controller enters ASPM L1 only after idle period during which both receive and transmit are in L0s. Note: This register field is sticky." "Controller enters ASPM L1 only after idle period..,Controller enters ASPM L1 after a period in.." newline bitfld.long 0xC 27.--29. "L1_ENTRANCE_LATENCY,L1 Entrance Latency. Value range is: - 000: 1 us - 001: 2 us - 010: 4 us - 011: 8 us - 100: 16 us - 101: 32 us - 110 or 111: 64 us Note: Programming this timer with a value greater that 32us has no effect unless extended sync is used.." "0,1,2,3,4,5,6,7" newline bitfld.long 0xC 24.--26. "L0S_ENTRANCE_LATENCY,L0s Entrance Latency. Values correspond to: - 000: 1 us - 001: 2 us - 010: 3 us - 011: 4 us - 100: 5 us - 101: 6 us - 110 or 111: 7 us This field is applicable to STALL while in L0 for M-PCIe. Note: This register field is sticky." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0xC 16.--23. 1. "COMMON_CLK_N_FTS,Common Clock N_FTS. This is the N_FTS when common clock is used. The number of Fast Training Sequence ordered sets to be transmitted when transitioning from L0s to L0. The maximum number of FTS ordered-sets that a component can request.." newline hexmask.long.byte 0xC 8.--15. 1. "ACK_N_FTS,N_FTS. The number of Fast Training Sequence ordered sets to be transmitted when transitioning from L0s to L0. The maximum number of FTS ordered-sets that a component can request is 255. The controller does not support a value of zero; a value.." newline hexmask.long.byte 0xC 0.--7. 1. "ACK_FREQ,Ack Frequency. The controller accumulates the number of pending ACKs specified here (up to 255) before scheduling an ACK DLLP. - 0: Indicates that this Ack Frequency Counter feature is turned off. The controller generates a low-priority ACK.." line.long 0x10 "PORT_LINK_CTRL_OFF,Port Link Control Register." hexmask.long.byte 0x10 28.--31. 1. "RSVDP_28,Reserved for future use." newline bitfld.long 0x10 27. "TRANSMIT_LANE_REVERSALE_ENABLE,TRANSMIT_LANE_REVERSALE_ENABLE is an internally reserved field. Do not use. Note: This register field is sticky." "0,1" newline bitfld.long 0x10 26. "EXTENDED_SYNCH,EXTENDED_SYNCH is an internally reserved field. Do not use. Note: This register field is sticky." "0,1" newline bitfld.long 0x10 25. "CORRUPT_LCRC_ENABLE,CORRUPT_LCRC_ENABLE is an internally reserved field. Do not use. Note: This register field is sticky." "0,1" newline bitfld.long 0x10 24. "BEACON_ENABLE,BEACON_ENABLE is an internally reserved field. Do not use. Note: This register field is sticky." "0,1" newline hexmask.long.byte 0x10 16.--21. 1. "LINK_CAPABLE,Link Mode Enable. Sets the number of lanes in the link that you want to connect to the link partner. When you have unused lanes in your system then you must change the value in this register to reflect the number of lanes. You must also.." newline hexmask.long.byte 0x10 12.--15. 1. "RSVDP_12,Reserved for future use." newline hexmask.long.byte 0x10 8.--11. 1. "LINK_RATE,LINK_RATE is an internally reserved field. Do not use. Note: This register field is sticky." newline bitfld.long 0x10 7. "FAST_LINK_MODE,Fast Link Mode. Sets all internal LTSSM millisecond timers to Fast Mode for speeding up simulation. Forces the LTSSM training (link initialization) to use shorter time-outs and to link up faster. The default scaling factor can be changed.." "0,1" newline bitfld.long 0x10 6. "LINK_DISABLE,LINK_DISABLE is an internally reserved field. Do not use. Note: This register field is sticky." "0,1" newline bitfld.long 0x10 5. "DLL_LINK_EN,DLL Link Enable. Enables link initialization. When DLL Link Enable =0 the controller does not transmit InitFC DLLPs and does not establish a link. Note: This register field is sticky." "0,1" newline rbitfld.long 0x10 4. "RSVDP_4,Reserved for future use." "0,1" newline bitfld.long 0x10 3. "RESET_ASSERT,Reset Assert. Triggers a recovery and forces the LTSSM to the hot reset state (downstream port only). Note: This register field is sticky." "0,1" newline bitfld.long 0x10 2. "LOOPBACK_ENABLE,Loopback Enable. Turns on loopback. For more details see 'Loopback'. For M-PCIe to force the master to enter Digital Loopback mode you must set this field to '1' during Configuration.start state(initial discovery/configuration). M-PCIe.." "0,1" newline bitfld.long 0x10 1. "SCRAMBLE_DISABLE,Scramble Disable. Turns off data scrambling. Note: This register field is sticky." "0,1" newline bitfld.long 0x10 0. "VENDOR_SPECIFIC_DLLP_REQ,Vendor Specific DLLP Request. When software writes a '1' to this bit the controller transmits the DLLP contained in the VENDOR_SPEC_DLLP field of VENDOR_SPEC_DLLP_OFF. Reading from this self-clearing register field always.." "0,1" line.long 0x14 "LANE_SKEW_OFF,Lane Skew Register." bitfld.long 0x14 31. "DISABLE_LANE_TO_LANE_DESKEW,Disable Lane-to-Lane Deskew. Causes the controller to disable the internal Lane-to-Lane deskew logic. Note: This register field is sticky." "0,1" newline hexmask.long.byte 0x14 27.--30. 1. "IMPLEMENT_NUM_LANES,Implementation-specific Number of Lanes. Set the implementation-specific number of lanes. Allowed values are: - 4'b0000: 1 lane - 4'b0001: 2 lanes - 4'b0011: 4 lanes - 4'b0111: 8 lanes - 4'b1111: 16 lanes The number of lanes to be.." newline bitfld.long 0x14 26. "ELASTIC_BUFFER_MODE,Selects Elasticity Buffer operating mode: 0: Nominal Half Full Buffer mode 1: Nominal Empty Buffer Mode Note: This register field is sticky." "Nominal Half Full Buffer mode,Nominal Empty Buffer Mode" newline bitfld.long 0x14 25. "ACK_NAK_DISABLE,Ack/Nak Disable. Prevents the controller from sending ACK and NAK DLLPs. Note: This register field is sticky." "0,1" newline bitfld.long 0x14 24. "FLOW_CTRL_DISABLE,Flow Control Disable. Prevents the controller from sending FC DLLPs. Note: This register field is sticky." "0,1" newline hexmask.long.tbyte 0x14 0.--23. 1. "INSERT_LANE_SKEW,INSERT_LANE_SKEW is an internally reserved field. Do not use. Note: This register field is sticky." line.long 0x18 "TIMER_CTRL_MAX_FUNC_NUM_OFF,Timer Control and Max Function Number Register." rbitfld.long 0x18 31. "RSVDP_31,Reserved for future use." "0,1" newline bitfld.long 0x18 29.--30. "FAST_LINK_SCALING_FACTOR,Fast Link Timer Scaling Factor. Sets the scaling factor of LTSSM timer when FAST_LINK_MODE field in PORT_LINK_CTRL_OFF is set to '1'. - 0: Scaling Factor is 1024 (1ms is 1us *a) - 1: Scaling Factor is 256 (1ms is 4us) - 2:.." "Scaling Factor is 1024,Scaling Factor is 256,Scaling Factor is 64,Scaling Factor is 16" newline hexmask.long.byte 0x18 24.--28. 1. "UPDATE_FREQ_TIMER,UPDATE_FREQ_TIMER is an internally reserved field. Do not use. Note: This register field is sticky." newline hexmask.long.byte 0x18 19.--23. 1. "TIMER_MOD_ACK_NAK,Ack Latency Timer Modifier. Increases the timer value for the Ack latency timer in increments of 64 clock cycles. A value of '0' represents no modification to the timer value. For more details see the ROUND_TRIP_LATENCY_TIME_LIMIT.." newline hexmask.long.byte 0x18 14.--18. 1. "TIMER_MOD_REPLAY_TIMER,Replay Timer Limit Modifier. Increases the time-out value for the replay timer in increments of 64 clock cycles at Gen1 or Gen2 speed and in increments of 256 clock cycles at Gen3 speed. A value of '0' represents no modification.." newline hexmask.long.byte 0x18 8.--13. 1. "RSVDP_8,Reserved for future use." newline hexmask.long.byte 0x18 0.--7. 1. "MAX_FUNC_NUM,Maximum function number that can be used in a request. Configuration requests targeted at function numbers above this value are returned with UR (unsupported request). Note: This register field is sticky." line.long 0x1C "SYMBOL_TIMER_FILTER_1_OFF,Symbol Timer Register and Filter Mask 1 Register. The Filter Mask 1 Register modifies the RADM filtering and error handling rules. For more details. see the 'Receive Filtering' section. In each case. '0' applies the associated.." hexmask.long.word 0x1C 16.--31. 1. "MASK_RADM_1,Filter Mask 1. The Filter Mask 1 Register modifies the RADM filtering and error handling rules. For more details see the 'Receive Filtering' section. In each case '0' applies the associated filtering rule and '1' masks the associated.." newline bitfld.long 0x1C 15. "DISABLE_FC_WD_TIMER,Disable FC Watchdog Timer. Note: This register field is sticky." "0,1" newline hexmask.long.byte 0x1C 11.--14. 1. "EIDLE_TIMER,EIDLE_TIMER is an internally reserved field. Do not use. Note: This register field is sticky." newline hexmask.long.word 0x1C 0.--10. 1. "SKP_INT_VAL,SKP Interval Value. The number of symbol times to wait between transmitting SKP ordered sets. Note that the controller actually waits the number of symbol times in this register plus 1 between transmitting SKP ordered sets. Your application.." line.long 0x20 "FILTER_MASK_2_OFF,Filter Mask 2 Register. This register modifies the RADM filtering and error handling rules. For more details. see the 'Receive Filtering' section. In each case. '0' applies the associated filtering rule and '1' masks the associated.." hexmask.long 0x20 0.--31. 1. "MASK_RADM_2,Filter Mask 2. This field modifies the RADM filtering and error handling rules. For more details see the 'Receive Filtering' section. In each case '0' applies the associated filtering rule and '1' masks the associated filtering rule." line.long 0x24 "AMBA_MUL_OB_DECOMP_NP_SUB_REQ_CTRL_OFF,AMBA Multiple Outbound Decomposed NP SubRequests Control Register." hexmask.long 0x24 1.--31. 1. "RSVDP_1,Reserved for future use." newline bitfld.long 0x24 0. "OB_RD_SPLIT_BURST_EN,Enable AMBA Multiple Outbound Decomposed NP SubRequests. This bit when set to '0' disables the possibility of having multiple outstanding non-posted requests that were derived from decomposition of an outbound AMBA request. For more.." "0,1" rgroup.long (0x28+0x700)++0x13 line.long 0x0 "PL_DEBUG0_OFF,Debug Register 0" hexmask.long 0x0 0.--31. 1. "DEB_REG_0,The value on cxpl_debug_info[31:0]." line.long 0x4 "PL_DEBUG1_OFF,Debug Register 1" hexmask.long 0x4 0.--31. 1. "DEB_REG_1,The value on cxpl_debug_info[63:32]." line.long 0x8 "TX_P_FC_CREDIT_STATUS_OFF,Transmit Posted FC Credit Status" hexmask.long.word 0x8 20.--31. 1. "RSVDP_TX_P_FC_CREDIT_STATUS,Reserved for future use." newline hexmask.long.byte 0x8 12.--19. 1. "TX_P_HEADER_FC_CREDIT,Transmit Posted Header FC Credits. The posted Header credits advertised by the receiver at the other end of the link updated with each UpdateFC DLLP. Default value depends on the number of advertised credits for header and data.." newline hexmask.long.word 0x8 0.--11. 1. "TX_P_DATA_FC_CREDIT,Transmit Posted Data FC Credits. The posted Data credits advertised by the receiver at the other end of the link updated with each UpdateFC DLLP. Default value depends on the number of advertised credits for header and data Scaled.." line.long 0xC "TX_NP_FC_CREDIT_STATUS_OFF,Transmit Non-Posted FC Credit Status" hexmask.long.word 0xC 20.--31. 1. "RSVDP_TX_NP_FC_CREDIT_STATUS,Reserved for future use." newline hexmask.long.byte 0xC 12.--19. 1. "TX_NP_HEADER_FC_CREDIT,Transmit Non-Posted Header FC Credits. The non-posted Header credits advertised by the receiver at the other end of the link updated with each UpdateFC DLLP. Default value depends on the number of advertised credits for header and.." newline hexmask.long.word 0xC 0.--11. 1. "TX_NP_DATA_FC_CREDIT,Transmit Non-Posted Data FC Credits. The non-posted Data credits advertised by the receiver at the other end of the link updated with each UpdateFC DLLP. Default value depends on the number of advertised credits for header and data.." line.long 0x10 "TX_CPL_FC_CREDIT_STATUS_OFF,Transmit Completion FC Credit Status" hexmask.long.word 0x10 20.--31. 1. "RSVDP_TX_CPL_FC_CREDIT_STATUS,Reserved for future use." newline hexmask.long.byte 0x10 12.--19. 1. "TX_CPL_HEADER_FC_CREDIT,Transmit Completion Header FC Credits. The Completion Header credits advertised by the receiver at the other end of the link updated with each UpdateFC DLLP. Default value depends on the number of advertised credits for header.." newline hexmask.long.word 0x10 0.--11. 1. "TX_CPL_DATA_FC_CREDIT,Transmit Completion Data FC Credits. The Completion Data credits advertised by the receiver at the other end of the link updated with each UpdateFC DLLP. Default value depends on the number of advertised credits for header and data.." group.long (0x3C+0x700)++0x3 line.long 0x0 "QUEUE_STATUS_OFF,Queue Status" bitfld.long 0x0 31. "TIMER_MOD_FLOW_CONTROL_EN,FC Latency Timer Override Enable. When this bit is set the value from the 'FC Latency Timer Override Value' field in this register will override the FC latency timer value that the controller calculates according to the PCIe.." "0,1" newline rbitfld.long 0x0 29.--30. "RSVDP_29,Reserved for future use." "0,1,2,3" newline hexmask.long.word 0x0 16.--28. 1. "TIMER_MOD_FLOW_CONTROL,FC Latency Timer Override Value. When you set the 'FC Latency Timer Override Enable' in this register the value in this field will override the FC latency timer value that the controller calculates according to the PCIe.." newline rbitfld.long 0x0 13. "RX_SERIALIZATION_Q_NON_EMPTY,Receive Serialization Queue Not Empty. Indicates there is data in the serialization queue." "0,1" newline hexmask.long.word 0x0 4.--12. 1. "RSVDP_4,Reserved for future use." newline bitfld.long 0x0 3. "RX_QUEUE_OVERFLOW,Receive Credit Queue Overflow. Indicates insufficient buffer space available to write to the P/NP/CPL credit queue." "0,1" newline rbitfld.long 0x0 2. "RX_QUEUE_NON_EMPTY,Receive Credit Queue Not Empty. Indicates there is data in one or more of the receive buffers." "0,1" newline rbitfld.long 0x0 1. "TX_RETRY_BUFFER_NE,Transmit Retry Buffer Not Empty. Indicates that there is data in the transmit retry buffer." "0,1" newline rbitfld.long 0x0 0. "RX_TLP_FC_CREDIT_NON_RETURN,Received TLP FC Credits Not Returned. Indicates that the controller has received a TLP but has not yet sent an UpdateFC DLLP indicating that the credits for that TLP have been restored by the receiver at the other end of the.." "0,1" rgroup.long (0x40+0x700)++0x7 line.long 0x0 "VC_TX_ARBI_1_OFF,VC Transmit Arbitration Register 1" hexmask.long.byte 0x0 24.--31. 1. "WRR_WEIGHT_VC_3,WRR Weight for VC3. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R" newline hexmask.long.byte 0x0 16.--23. 1. "WRR_WEIGHT_VC_2,WRR Weight for VC2. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R" newline hexmask.long.byte 0x0 8.--15. 1. "WRR_WEIGHT_VC_1,WRR Weight for VC1. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R" newline hexmask.long.byte 0x0 0.--7. 1. "WRR_WEIGHT_VC_0,WRR Weight for VC0. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R" line.long 0x4 "VC_TX_ARBI_2_OFF,VC Transmit Arbitration Register 2" hexmask.long.byte 0x4 24.--31. 1. "WRR_WEIGHT_VC_7,WRR Weight for VC7. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R" newline hexmask.long.byte 0x4 16.--23. 1. "WRR_WEIGHT_VC_6,WRR Weight for VC6. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R" newline hexmask.long.byte 0x4 8.--15. 1. "WRR_WEIGHT_VC_5,WRR Weight for VC5. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R" newline hexmask.long.byte 0x4 0.--7. 1. "WRR_WEIGHT_VC_4,WRR Weight for VC4. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R" group.long (0x48+0x700)++0xB line.long 0x0 "VC0_P_RX_Q_CTRL_OFF,Segmented-Buffer VC0 Posted Receive Queue Control." bitfld.long 0x0 31. "VC_ORDERING_RX_Q,VC Ordering for Receive Queues. Determines the VC ordering rule for the receive queues used only in the segmented-buffer configuration: - 1: Strict ordering higher numbered VCs have higher priority - 0: Round robin Note: This register.." "Round robin,Strict ordering" newline bitfld.long 0x0 30. "TLP_TYPE_ORDERING_VC0,TLP Type Ordering for VC0. Determines the TLP type ordering rule for VC0 receive queues used only in the segmented-buffer configuration: - 1: PCIe ordering rules (recommended) - 0: Strict ordering: posted completion then.." "Strict ordering: posted,PCIe ordering rules" newline bitfld.long 0x0 28.--29. "RESERVED5,Reserved. Note: This register field is sticky." "0,1,2,3" newline bitfld.long 0x0 26.--27. "VC0_P_DATA_SCALE,VC0 Scale Posted Data Credites. Note: This register field is sticky." "0,1,2,3" newline bitfld.long 0x0 24.--25. "VC0_P_HDR_SCALE,VC0 Scale Posted Header Credites. Note: This register field is sticky." "0,1,2,3" newline bitfld.long 0x0 21.--23. "VC0_P_TLP_Q_MODE,Reserved. Note: This register field is sticky." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 20. "RESERVED4,Reserved. Note: This register field is sticky." "0,1" newline hexmask.long.byte 0x0 12.--19. 1. "VC0_P_HEADER_CREDIT,VC0 Posted Header Credits. The number of initial posted header credits for VC0 used only in the segmented-buffer configuration. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R (sticky) Note: This.." newline hexmask.long.word 0x0 0.--11. 1. "VC0_P_DATA_CREDIT,VC0 Posted Data Credits. The number of initial posted data credits for VC0 used only in the segmented-buffer configuration. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R (sticky) Note: This.." line.long 0x4 "VC0_NP_RX_Q_CTRL_OFF,Segmented-Buffer VC0 Non-Posted Receive Queue Control." hexmask.long.byte 0x4 28.--31. 1. "RESERVED7,Reserved. Note: This register field is sticky." newline bitfld.long 0x4 26.--27. "VC0_NP_DATA_SCALE,VC0 Scale Non-Posted Data Credites. Note: This register field is sticky." "0,1,2,3" newline bitfld.long 0x4 24.--25. "VC0_NP_HDR_SCALE,VC0 Scale Non-Posted Header Credites. Note: This register field is sticky." "0,1,2,3" newline bitfld.long 0x4 21.--23. "VC0_NP_TLP_Q_MODE,Reserved. Note: This register field is sticky." "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 20. "RESERVED6,Reserved. Note: This register field is sticky." "0,1" newline hexmask.long.byte 0x4 12.--19. 1. "VC0_NP_HEADER_CREDIT,VC0 Non-Posted Header Credits. The number of initial non-posted header credits for VC0 used only in the segmented-buffer configuration. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R (sticky).." newline hexmask.long.word 0x4 0.--11. 1. "VC0_NP_DATA_CREDIT,VC0 Non-Posted Data Credits. The number of initial non-posted data credits for VC0 used only in the segmented-buffer configuration. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R (sticky) Note:.." line.long 0x8 "VC0_CPL_RX_Q_CTRL_OFF,Segmented-Buffer VC0 Completion Receive Queue Control." hexmask.long.byte 0x8 28.--31. 1. "RESERVED9,Reserved. Note: This register field is sticky." newline bitfld.long 0x8 26.--27. "VC0_CPL_DATA_SCALE,VC0 Scale CPL Data Credites. Note: This register field is sticky." "0,1,2,3" newline bitfld.long 0x8 24.--25. "VC0_CPL_HDR_SCALE,VC0 Scale CPL Header Credites. Note: This register field is sticky." "0,1,2,3" newline bitfld.long 0x8 21.--23. "VC0_CPL_TLP_Q_MODE,Reserved. Note: This register field is sticky." "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 20. "RESERVED8,Reserved. Note: This register field is sticky." "0,1" newline hexmask.long.byte 0x8 12.--19. 1. "VC0_CPL_HEADER_CREDIT,VC0 Completion Header Credits. The number of initial Completion header credits for VC0 used only in the segmented-buffer configuration. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R (sticky).." newline hexmask.long.word 0x8 0.--11. 1. "VC0_CPL_DATA_CREDIT,VC0 Completion Data Credits. The number of initial Completion data credits for VC0 used only in the segmented-buffer configuration. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R (sticky) Note:.." group.long (0x10C+0x700)++0x3 line.long 0x0 "GEN2_CTRL_OFF,This register is used to control various functions of the controller related to link training. lane reversal. and equalization." rbitfld.long 0x0 31. "RSVDP_31,Reserved for future use." "0,1" newline rbitfld.long 0x0 22.--23. "RSVDP_22,Reserved for future use." "0,1,2,3" newline bitfld.long 0x0 21. "GEN1_EI_INFERENCE,Electrical Idle Inference Mode at Gen1 Rate. Programmable mode to determine inferred electrical idle (EI) in Recovery.Speed or Loopback.Active (as slave) state at Gen1 speed by looking for a '1' value on RxElecIdle instead of looking.." "Use RxElecIdle signal to infer Electrical Idle,Use RxValid signal to infer Electrical Idle" newline bitfld.long 0x0 20. "SEL_DEEMPHASIS,Used to set the de-emphasis level for upstream ports. This bit selects the level of de-emphasis the link operates at. - 0: -6 dB - 1: -3.5 dB This field is reserved (fixed to '0') for M-PCIe. Note: The access attributes of this field are.." "0,1" newline bitfld.long 0x0 19. "CONFIG_TX_COMP_RX,Config Tx Compliance Receive Bit. When set to 1 signals LTSSM to transmit TS ordered sets with the compliance receive bit assert (equal to '1'). This field is reserved (fixed to '0') for M-PCIe. Note: The access attributes of this.." "0,1" newline bitfld.long 0x0 18. "CONFIG_PHY_TX_CHANGE,Config PHY Tx Swing. Controls the PHY transmitter voltage swing level. The controller drives the mac_phy_txswing output from this register bit field. - 0: Full Swing - 1: Low Swing This field is reserved (fixed to '0') for M-PCIe." "Full Swing,Low Swing" newline bitfld.long 0x0 17. "DIRECT_SPEED_CHANGE,Directed Speed Change. Writing '1' to this field instructs the LTSSM to initiate a speed change to Gen2 or Gen3 after the link is initialized at Gen1 speed. When the speed change occurs the controller will clear the contents of this.." "0,1" newline bitfld.long 0x0 16. "AUTO_LANE_FLIP_CTRL_EN,Enable Auto flipping of the lanes. You must set the CX_AUTO_LANE_FLIP_CTRL_EN configuration parameter to include the hardware for this feature in the controller. For more details see the 'Lane Reversal' appendix in the Databook." "0,1" newline bitfld.long 0x0 13.--15. "PRE_DET_LANE,Predetermined Lane for Auto Flip. This field defines which physical lane is connected to logical Lane0 by the flip operation performed in Detect. This field is used to restrict the receiver detect procedure to a particular lane when the.." "LANE0,LANE1,LANE3,LANE7,LANE15,?,?,?" newline hexmask.long.byte 0x0 8.--12. 1. "NUM_OF_LANES,Predetermined Number of Lanes. Defines the number of lanes which are connected and not bad. Used to limit the effective link width to ignore 'broken' or 'unused' lanes that detect a receiver. Indicates the number of lanes to check for exit.." newline hexmask.long.byte 0x0 0.--7. 1. "FAST_TRAINING_SEQ,Sets the Number of Fast Training Sequences (N_FTS) that the controller advertises as its N_FTS during Gen2 or Gen3 link training. This value is used to inform the link partner about the PHY's ability to recover synchronization after a.." rgroup.long (0x110+0x700)++0x3 line.long 0x0 "PHY_STATUS_OFF,PHY Status Register. Memory mapped register from phy_cfg_status GPIO input pins." hexmask.long 0x0 0.--31. 1. "PHY_STATUS,PHY Status. Data received directly from the phy_cfg_status bus. These is a GPIO register reflecting the values on the static phy_cfg_status input signals. The usage is left completely to the user and does not in any way influence controller.." group.long (0x114+0x700)++0x3 line.long 0x0 "PHY_CONTROL_OFF,PHY Control Register. Memory mapped register to cfg_phy_control GPIO output pins." hexmask.long 0x0 0.--31. 1. "PHY_CONTROL,PHY Control. Data sent directly to the cfg_phy_control bus. These is a GPIO register driving the values on the static cfg_phy_control output signals. The usage is left completely to the user and does not in any way influence controller.." group.long (0x11C+0x700)++0x77 line.long 0x0 "TRGT_MAP_CTRL_OFF,Programmable Target Map Control Register." hexmask.long.word 0x0 21.--31. 1. "TARGET_MAP_RESERVED_21_31,Reserved. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R (sticky)" newline hexmask.long.byte 0x0 16.--20. 1. "TARGET_MAP_INDEX,The number of the PF Function on which the Target Values are set. This register does not respect the Byte Enable setting. any write will affect all register bits." newline rbitfld.long 0x0 13.--15. "TARGET_MAP_RESERVED_13_15,Reserved. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R (sticky)" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 6. "TARGET_MAP_ROM,Target Value for the ROM page of the PF Function selected by the index number. This register does not respect the Byte Enable setting. any write will affect all register bits." "0,1" newline hexmask.long.byte 0x0 0.--5. 1. "TARGET_MAP_PF,Target Values for each BAR on the PF Function selected by the index number. This register does not respect the Byte Enable setting. any write will affect all register bits." line.long 0x4 "MSI_CTRL_ADDR_OFF,Integrated MSI Reception Module (iMRM) Address Register." hexmask.long 0x4 0.--31. 1. "MSI_CTRL_ADDR,Integrated MSI Reception Module Address. System specified address for MSI memory write transaction termination. Within the AXI Bridge every received Memory Write request is examined to see if it targets the MSI Address that has been.." line.long 0x8 "MSI_CTRL_UPPER_ADDR_OFF,Integrated MSI Reception Module Upper Address Register." hexmask.long 0x8 0.--31. 1. "MSI_CTRL_UPPER_ADDR,Integrated MSI Reception Module Upper Address. System specified upper address for MSI memory write transaction termination. Allows functions to support a 64-bit MSI address. Note: This register field is sticky." line.long 0xC "MSI_CTRL_INT_0_EN_OFF,Integrated MSI Reception Module Interrupt#i Enable Register." hexmask.long 0xC 0.--31. 1. "MSI_CTRL_INT_0_EN,MSI Interrupt#i Enable. Specifies which interrupts are enabled. When an MSI is received from a disabled interrupt no status bit gets set in MSI controller interrupt status register. Each bit corresponds to a single MSI Interrupt.." line.long 0x10 "MSI_CTRL_INT_0_MASK_OFF,Integrated MSI Reception Module Interrupt#i Mask Register." hexmask.long 0x10 0.--31. 1. "MSI_CTRL_INT_0_MASK,MSI Interrupt#i Mask. Allows enabled interrupts to be masked. When an MSI is received for a masked interrupt the corresponding status bit gets set in the interrupt status register but the msi_ctrl_int output is not set HIGH. Each bit.." line.long 0x14 "MSI_CTRL_INT_0_STATUS_OFF,Integrated MSI Reception Module Interrupt#i Status Register." hexmask.long 0x14 0.--31. 1. "MSI_CTRL_INT_0_STATUS,MSI Interrupt#i Status. When an MSI is detected for EP#i one bit in this register is set. The decoding of the data payload of the MSI Memory Write request determines which bit gets set. A status is bit is cleared by writing a 1 to.." line.long 0x18 "MSI_CTRL_INT_1_EN_OFF,Integrated MSI Reception Module Interrupt#i Enable Register." hexmask.long 0x18 0.--31. 1. "MSI_CTRL_INT_1_EN,MSI Interrupt#i Enable. Specifies which interrupts are enabled. When an MSI is received from a disabled interrupt no status bit gets set in MSI controller interrupt status register. Each bit corresponds to a single MSI Interrupt.." line.long 0x1C "MSI_CTRL_INT_1_MASK_OFF,Integrated MSI Reception Module Interrupt#i Mask Register." hexmask.long 0x1C 0.--31. 1. "MSI_CTRL_INT_1_MASK,MSI Interrupt#i Mask. Allows enabled interrupts to be masked. When an MSI is received for a masked interrupt the corresponding status bit gets set in the interrupt status register but the msi_ctrl_int output is not set HIGH. Each bit.." line.long 0x20 "MSI_CTRL_INT_1_STATUS_OFF,Integrated MSI Reception Module Interrupt#i Status Register." hexmask.long 0x20 0.--31. 1. "MSI_CTRL_INT_1_STATUS,MSI Interrupt#i Status. When an MSI is detected for EP#i one bit in this register is set. The decoding of the data payload of the MSI Memory Write request determines which bit gets set. A status is bit is cleared by writing a 1 to.." line.long 0x24 "MSI_CTRL_INT_2_EN_OFF,Integrated MSI Reception Module Interrupt#i Enable Register." hexmask.long 0x24 0.--31. 1. "MSI_CTRL_INT_2_EN,MSI Interrupt#i Enable. Specifies which interrupts are enabled. When an MSI is received from a disabled interrupt no status bit gets set in MSI controller interrupt status register. Each bit corresponds to a single MSI Interrupt.." line.long 0x28 "MSI_CTRL_INT_2_MASK_OFF,Integrated MSI Reception Module Interrupt#i Mask Register." hexmask.long 0x28 0.--31. 1. "MSI_CTRL_INT_2_MASK,MSI Interrupt#i Mask. Allows enabled interrupts to be masked. When an MSI is received for a masked interrupt the corresponding status bit gets set in the interrupt status register but the msi_ctrl_int output is not set HIGH. Each bit.." line.long 0x2C "MSI_CTRL_INT_2_STATUS_OFF,Integrated MSI Reception Module Interrupt#i Status Register." hexmask.long 0x2C 0.--31. 1. "MSI_CTRL_INT_2_STATUS,MSI Interrupt#i Status. When an MSI is detected for EP#i one bit in this register is set. The decoding of the data payload of the MSI Memory Write request determines which bit gets set. A status is bit is cleared by writing a 1 to.." line.long 0x30 "MSI_CTRL_INT_3_EN_OFF,Integrated MSI Reception Module Interrupt#i Enable Register." hexmask.long 0x30 0.--31. 1. "MSI_CTRL_INT_3_EN,MSI Interrupt#i Enable. Specifies which interrupts are enabled. When an MSI is received from a disabled interrupt no status bit gets set in MSI controller interrupt status register. Each bit corresponds to a single MSI Interrupt.." line.long 0x34 "MSI_CTRL_INT_3_MASK_OFF,Integrated MSI Reception Module Interrupt#i Mask Register." hexmask.long 0x34 0.--31. 1. "MSI_CTRL_INT_3_MASK,MSI Interrupt#i Mask. Allows enabled interrupts to be masked. When an MSI is received for a masked interrupt the corresponding status bit gets set in the interrupt status register but the msi_ctrl_int output is not set HIGH. Each bit.." line.long 0x38 "MSI_CTRL_INT_3_STATUS_OFF,Integrated MSI Reception Module Interrupt#i Status Register." hexmask.long 0x38 0.--31. 1. "MSI_CTRL_INT_3_STATUS,MSI Interrupt#i Status. When an MSI is detected for EP#i one bit in this register is set. The decoding of the data payload of the MSI Memory Write request determines which bit gets set. A status is bit is cleared by writing a 1 to.." line.long 0x3C "MSI_CTRL_INT_4_EN_OFF,Integrated MSI Reception Module Interrupt#i Enable Register." hexmask.long 0x3C 0.--31. 1. "MSI_CTRL_INT_4_EN,MSI Interrupt#i Enable. Specifies which interrupts are enabled. When an MSI is received from a disabled interrupt no status bit gets set in MSI controller interrupt status register. Each bit corresponds to a single MSI Interrupt.." line.long 0x40 "MSI_CTRL_INT_4_MASK_OFF,Integrated MSI Reception Module Interrupt#i Mask Register." hexmask.long 0x40 0.--31. 1. "MSI_CTRL_INT_4_MASK,MSI Interrupt#i Mask. Allows enabled interrupts to be masked. When an MSI is received for a masked interrupt the corresponding status bit gets set in the interrupt status register but the msi_ctrl_int output is not set HIGH. Each bit.." line.long 0x44 "MSI_CTRL_INT_4_STATUS_OFF,Integrated MSI Reception Module Interrupt#i Status Register." hexmask.long 0x44 0.--31. 1. "MSI_CTRL_INT_4_STATUS,MSI Interrupt#i Status. When an MSI is detected for EP#i one bit in this register is set. The decoding of the data payload of the MSI Memory Write request determines which bit gets set. A status is bit is cleared by writing a 1 to.." line.long 0x48 "MSI_CTRL_INT_5_EN_OFF,Integrated MSI Reception Module Interrupt#i Enable Register." hexmask.long 0x48 0.--31. 1. "MSI_CTRL_INT_5_EN,MSI Interrupt#i Enable. Specifies which interrupts are enabled. When an MSI is received from a disabled interrupt no status bit gets set in MSI controller interrupt status register. Each bit corresponds to a single MSI Interrupt.." line.long 0x4C "MSI_CTRL_INT_5_MASK_OFF,Integrated MSI Reception Module Interrupt#i Mask Register." hexmask.long 0x4C 0.--31. 1. "MSI_CTRL_INT_5_MASK,MSI Interrupt#i Mask. Allows enabled interrupts to be masked. When an MSI is received for a masked interrupt the corresponding status bit gets set in the interrupt status register but the msi_ctrl_int output is not set HIGH. Each bit.." line.long 0x50 "MSI_CTRL_INT_5_STATUS_OFF,Integrated MSI Reception Module Interrupt#i Status Register." hexmask.long 0x50 0.--31. 1. "MSI_CTRL_INT_5_STATUS,MSI Interrupt#i Status. When an MSI is detected for EP#i one bit in this register is set. The decoding of the data payload of the MSI Memory Write request determines which bit gets set. A status is bit is cleared by writing a 1 to.." line.long 0x54 "MSI_CTRL_INT_6_EN_OFF,Integrated MSI Reception Module Interrupt#i Enable Register." hexmask.long 0x54 0.--31. 1. "MSI_CTRL_INT_6_EN,MSI Interrupt#i Enable. Specifies which interrupts are enabled. When an MSI is received from a disabled interrupt no status bit gets set in MSI controller interrupt status register. Each bit corresponds to a single MSI Interrupt.." line.long 0x58 "MSI_CTRL_INT_6_MASK_OFF,Integrated MSI Reception Module Interrupt#i Mask Register." hexmask.long 0x58 0.--31. 1. "MSI_CTRL_INT_6_MASK,MSI Interrupt#i Mask. Allows enabled interrupts to be masked. When an MSI is received for a masked interrupt the corresponding status bit gets set in the interrupt status register but the msi_ctrl_int output is not set HIGH. Each bit.." line.long 0x5C "MSI_CTRL_INT_6_STATUS_OFF,Integrated MSI Reception Module Interrupt#i Status Register." hexmask.long 0x5C 0.--31. 1. "MSI_CTRL_INT_6_STATUS,MSI Interrupt#i Status. When an MSI is detected for EP#i one bit in this register is set. The decoding of the data payload of the MSI Memory Write request determines which bit gets set. A status is bit is cleared by writing a 1 to.." line.long 0x60 "MSI_CTRL_INT_7_EN_OFF,Integrated MSI Reception Module Interrupt#i Enable Register." hexmask.long 0x60 0.--31. 1. "MSI_CTRL_INT_7_EN,MSI Interrupt#i Enable. Specifies which interrupts are enabled. When an MSI is received from a disabled interrupt no status bit gets set in MSI controller interrupt status register. Each bit corresponds to a single MSI Interrupt.." line.long 0x64 "MSI_CTRL_INT_7_MASK_OFF,Integrated MSI Reception Module Interrupt#i Mask Register." hexmask.long 0x64 0.--31. 1. "MSI_CTRL_INT_7_MASK,MSI Interrupt#i Mask. Allows enabled interrupts to be masked. When an MSI is received for a masked interrupt the corresponding status bit gets set in the interrupt status register but the msi_ctrl_int output is not set HIGH. Each bit.." line.long 0x68 "MSI_CTRL_INT_7_STATUS_OFF,Integrated MSI Reception Module Interrupt#i Status Register." hexmask.long 0x68 0.--31. 1. "MSI_CTRL_INT_7_STATUS,MSI Interrupt#i Status. When an MSI is detected for EP#i one bit in this register is set. The decoding of the data payload of the MSI Memory Write request determines which bit gets set. A status is bit is cleared by writing a 1 to.." line.long 0x6C "MSI_GPIO_IO_OFF,Integrated MSI Reception Module General Purpose IO Register." hexmask.long 0x6C 0.--31. 1. "MSI_GPIO_REG,MSI GPIO Register. The contents of this register drives the top-level GPIO msi_ctrl_io[31:0] Note: This register field is sticky." line.long 0x70 "CLOCK_GATING_CTRL_OFF,This register enables you to disable dynamic clock gating. By default dynamic clock gating is on. allowing the controller to autonomously enable and disable its clocks. The clock gating is performed in the clock and reset module." hexmask.long 0x70 2.--31. 1. "RSVDP_2,Reserved for future use." newline bitfld.long 0x70 1. "AXI_CLK_GATING_EN,AXI Clock Gating Enable. This register enables the AXI Bridge to autonomously enable and disable the AXI Master clock the AXI Slave clock and the AXI DBI slave clock. The DWC_pcie_clk_rst.v module provides the gated clock.." "Disable,Enable" newline bitfld.long 0x70 0. "RADM_CLK_GATING_EN,RADM Clock Gating Enable. This register if set enables the RADM to autonomously enable and disable its clock. The DWC_pcie_clk_rst.v module provides the gated clock radm_clk_g to the RADM and is enabled when the controllers clock.." "Disable,Enable" line.long 0x74 "GEN3_RELATED_OFF,Gen3 Control Register. There is no Gen3-specific N_FTS field. The N_FTS field in the 'Link Width and Speed Change Control Register' is used for both Gen2 and Gen3 speed modes. There is no Gen3-specific 'Directed Speed Change' field. The.." hexmask.long.byte 0x74 26.--31. 1. "RSVDP_26,Reserved for future use." newline bitfld.long 0x74 23. "GEN3_EQ_INVREQ_EVAL_DIFF_DISABLE,Eq InvalidRequest and RxEqEval Different Time Assertion Disable. Disable the assertion of Eq InvalidRequest and RxEqEval at different time. Note: When CX_GEN4_SPEED/CX_GEN5_SPEED this register is shared for Gen3 and.." "0,1" newline rbitfld.long 0x74 19.--20. "RSVDP_19,Reserved for future use." "0,1,2,3" newline bitfld.long 0x74 18. "GEN3_DC_BALANCE_DISABLE,DC Balance Disable. Disable DC Balance feature. Note: When CX_GEN4_SPEED/CX_GEN5_SPEED this register is shared for Gen3 and Gen4/Gen5 data rate. Note: This register field is sticky." "0,1" newline bitfld.long 0x74 17. "GEN3_DLLP_XMT_DELAY_DISABLE,DLLP Transmission Delay Disable. Disable delay transmission of DLLPs before equalization. Note: When CX_GEN4_SPEED/CX_GEN5_SPEED this register is shared for Gen3 and Gen4/Gen5 data rate. Note: This register field is sticky." "0,1" newline bitfld.long 0x74 16. "GEN3_EQUALIZATION_DISABLE,Equalization Disable. Disable equalization feature. This bit cannot be changed once the LTSSM starts link training. Note: When CX_GEN4_SPEED/CX_GEN5_SPEED this register is shared for Gen3 and Gen4/Gen5 data rate. Note: This.." "0,1" newline rbitfld.long 0x74 14.--15. "RSVDP_14,Reserved for future use." "0,1,2,3" newline bitfld.long 0x74 13. "RXEQ_RGRDLESS_RXTS,When set to '1' the controller as Gen3 EQ master asserts RxEqEval to instruct the PHY to do Rx adaptation and evaluation after a 500ns timeout from a new preset request. - 0: mac_phy_rxeqeval asserts after 1us and 2 TS1 received from.." "mac_phy_rxeqeval asserts after 1us and 2 TS1..,mac_phy_rxeqeval asserts after 500ns regardless.." newline bitfld.long 0x74 12. "RXEQ_PH01_EN,Rx Equalization Phase 0/Phase 1 Hold Enable. When this bit is set the upstream port holds phase 0 (the downstream port holds phase 1) for 10ms. Holding phase 0 or phase 1 can be used to allow sufficient time for Rx Equalization to be.." "Tx equalization only in phase 2/3,No Tx equalization" newline bitfld.long 0x74 11. "EQ_REDO,Equalization Redo Disable. Disable autonomous mechanism for requesting to redo the equalization process. The received presets or coefficients mismatch in Recovery.RcvrLock after Recovery EQ phases causes the EQ redo requests. If the EQ redo is.." "0,1" newline bitfld.long 0x74 10. "EQ_EIEOS_CNT,Equalization EIEOS Count Reset Disable. Disable requesting reset of EIEOS count during equalization. Note: When CX_GEN4_SPEED/CX_GEN5_SPEED this register is shared for Gen3 and Gen4/Gen5 data rate. Note: This register field is sticky." "0,1" newline bitfld.long 0x74 9. "EQ_PHASE_2_3,Equalization Phase 2 and Phase 3 Disable. This applies to downstream ports only. Note: When CX_GEN4_SPEED/CX_GEN5_SPEED this register is shadow register for Gen3 and Gen4/Gen5 data rate. If RATE_SHADOW_SEL==00b this register is for Gen3.." "0,1" newline bitfld.long 0x74 8. "DISABLE_SCRAMBLER_GEN_3,Disable Scrambler for Gen3 and Gen4 Data Rate. The Gen3 and Gen4 scrambler/descrambler within the controller needs to be disabled when the scrambling function is implemented outside of the controller (for example within the PHY)." "0,1" newline hexmask.long.byte 0x74 1.--7. 1. "RSVDP_1,Reserved for future use." newline bitfld.long 0x74 0. "GEN3_ZRXDC_NONCOMPL,Gen3 Receiver Impedance ZRX-DC Not Compliant. Receivers that operate at 8.0 GT/s with an impedance other than the range defined by the ZRX-DC parameter for 2.5 GT/s (40-60 Ohms) must meet additional behavior requirements in the.." "The receiver complies with the ZRX-DC parameter..,The receiver does not comply with the ZRX-DC.." group.long (0x1A8+0x700)++0x7 line.long 0x0 "GEN3_EQ_CONTROL_OFF,Gen3 EQ Control Register. This register controls equalization for Phase2 in an upstream port (USP). or Phase3 in a downstream port (DSP). M-PCIe doesn't have Conventional PCIe Gen3 feature. The registers of this section do not exist." hexmask.long.byte 0x0 27.--31. 1. "RSVDP_27,Reserved for future use." newline bitfld.long 0x0 26. "GEN3_REQ_SEND_CONSEC_EIEOS_FOR_PSET_MAP,Request controller to send back-to-back EIEOS in Recovery.RcvrLock state until presets to coefficients mapping is complete. - 0: Do not request - 1: request Note: Gen3 and Gen4 share the same register bit and have.." "Do not request,request" newline bitfld.long 0x0 25. "GEN3_EQ_PSET_REQ_AS_COEF,GEN3_EQ_PSET_REQ_AS_COEF is an internally reserved field. Do not use. Note: This register field is sticky." "0,1" newline bitfld.long 0x0 24. "GEN3_EQ_FOM_INC_INITIAL_EVAL,Include Initial FOM. Include or not the FOM feedback from the initial preset evaluation performed in the EQ Master when finding the highest FOM among all preset evaluations. - 0: Do not include - 1: Include Note: When.." "Do not include,Include" newline hexmask.long.word 0x0 8.--23. 1. "GEN3_EQ_PSET_REQ_VEC,Preset Request Vector. Requesting of Presets during the initial part of the EQ Master Phase. Encoding scheme is as follows: Bit [15:0] =0x0: No preset is requested and evaluated in EQ Master Phase. Bit [i] =1: 'Preset=i' is requested.." newline rbitfld.long 0x0 7. "RSVDP_7,Reserved for future use." "0,1" newline bitfld.long 0x0 6. "GEN3_LOWER_RATE_EQ_REDO_ENABLE,Support EQ redo and lower rate change: - 0: not support - 1: support Note: Gen3 and Gen4 share the same register bit and have the same feature. Note: This register field is sticky." "not support,support" newline bitfld.long 0x0 5. "GEN3_EQ_EVAL_2MS_DISABLE,Phase2_3 2 ms Timeout Disable. Determine behavior in Phase2 for USP (Phase3 if DSP) when the PHY does not respond within 2ms to the assertion of RxEqEval: - 0: abort the current evaluation stop any attempt to modify the remote.." "abort the current evaluation,ignore the 2ms timeout and continue as normal" newline bitfld.long 0x0 4. "GEN3_EQ_PHASE23_EXIT_MODE,Behavior After 24 ms Timeout (when optimal settings are not found). For a USP: Determine next LTSSM state from Phase2 after 24ms Timeout - 0: Recovery.Speed - 1: Recovery.Equalization.Phase3 When optimal settings are not found.." "Equalization Phase 3 Successful status bit is..,Recovery" newline hexmask.long.byte 0x0 0.--3. 1. "GEN3_EQ_FB_MODE,Feedback Mode. - 0000b: Direction Change - 0001b: Figure Of Merit - 0010b: Reserved - .....: Reserved - 1111b: Reserved Note: When CX_GEN4_SPEED/CX_GEN5_SPEED this register is a shadow register for Gen3 and Gen4/Gen5 data rate. If.." line.long 0x4 "GEN3_EQ_FB_MODE_DIR_CHANGE_OFF,Gen3 EQ Direction Change Feedback Mode Control Register. Equalization controls to be used in Phase2 (USP) or Phase 3 (DSP). when you set the Feedback Mode in 'Gen3 EQ Control Register' to 'Direction Change.' These fields.." hexmask.long.word 0x4 18.--31. 1. "RSVDP_18,Reserved for future use." newline hexmask.long.byte 0x4 14.--17. 1. "GEN3_EQ_FMDC_MAX_POST_CUSROR_DELTA,Convergence Window Aperture for C+1. Post-cursor coefficients maximum delta within the convergence window depth. Allowed range: 0 1 2 ..15. Note: When CX_GEN4_SPEED/CX_GEN5_SPEED this register is shadow register for.." newline hexmask.long.byte 0x4 10.--13. 1. "GEN3_EQ_FMDC_MAX_PRE_CUSROR_DELTA,Convergence Window Aperture for C-1. Pre-cursor coefficients maximum delta within the convergence window depth. Allowed range: 0 1 2 ..15. Note: When CX_GEN4_SPEED/CX_GEN5_SPEED this register is shadow register for Gen3.." newline hexmask.long.byte 0x4 5.--9. 1. "GEN3_EQ_FMDC_N_EVALS,Convergence Window Depth. Number of consecutive evaluations considered in Phase 2/3 when determining if optimal coefficients have been found. Allowed range: 0 1 2 ..16 up to a maximum of CX_GEN3_EQ_COEFQ_DEPTH. When set to 0 EQ.." newline hexmask.long.byte 0x4 0.--4. 1. "GEN3_EQ_FMDC_T_MIN_PHASE23,Minimum Time (in ms) To Remain in EQ Master Phase. The LTSSM stays in EQ Master phase for at least this amount of time before starting to check for convergence of the coefficients. Allowed values 0 1 ... 24. Note: When.." group.long (0x1B4+0x700)++0x27 line.long 0x0 "ORDER_RULE_CTRL_OFF,Order Rule Control Register." hexmask.long.word 0x0 16.--31. 1. "RSVDP_16,Reserved for future use." newline hexmask.long.byte 0x0 8.--15. 1. "CPL_PASS_P,Completion Passing Posted Ordering Rule Control. Determines if CPL can pass halted P queue. - 0: CPL can not pass P (recommended) - 1: CPL can pass P" newline hexmask.long.byte 0x0 0.--7. 1. "NP_PASS_P,Non-Posted Passing Posted Ordering Rule Control. Determines if NP can pass halted P queue. - 0 : NP can not pass P (recommended). - 1 : NP can pass P" line.long 0x4 "PIPE_LOOPBACK_CONTROL_OFF,PIPE Loopback Control Register." bitfld.long 0x4 31. "PIPE_LOOPBACK,PIPE Loopback Enable. Indicates RMMI Loopback if M-PCIe. Note: This register field is sticky." "0,1" newline hexmask.long.byte 0x4 27.--30. 1. "RSVDP_27,Reserved for future use." newline bitfld.long 0x4 24.--26. "RXSTATUS_VALUE,RXSTATUS_VALUE is an internally reserved field. Do not use." "0,1,2,3,4,5,6,7" newline rbitfld.long 0x4 22.--23. "RSVDP_22,Reserved for future use." "0,1,2,3" newline hexmask.long.byte 0x4 16.--21. 1. "RXSTATUS_LANE,RXSTATUS_LANE is an internally reserved field. Do not use. Note: This register field is sticky." newline hexmask.long.word 0x4 0.--15. 1. "LPBK_RXVALID,LPBK_RXVALID is an internally reserved field. Do not use. Note: This register field is sticky." line.long 0x8 "MISC_CONTROL_1_OFF,DBI Read-Only Write Enable Register." hexmask.long.word 0x8 22.--31. 1. "RSVDP_22,Reserved for future use." newline bitfld.long 0x8 21. "P2P_ERR_RPT_CTRL,Determines whether to track completion of transmitted Non-Posted TLPs in P2P mode. - 0: Do not track completion - 1: Track completion Note: This register field is sticky." "Do not track completion,Track completion" newline bitfld.long 0x8 20. "P2P_TRACK_CPL_TO_REG,Determines whether to enable Peer to Peer (P2P) error reporting. - 0: Disable P2P error reporting - 1: Enable P2P error reporting Note: This register field is sticky." "Disable P2P error reporting,Enable P2P error reporting" newline bitfld.long 0x8 18.--19. "TARGET_ABOVE_CONFIG_LIMIT_REG,Configuration requests with an address greater than CONFIG_LIMIT_REG are directed to either ELBI or TRGT1 interface based on the setting of this field. This field can have the following values: - 1: ELBI - 2: TRGT1 Note:.." "?,ELBI,TRGT1,?" newline hexmask.long.word 0x8 8.--17. 1. "CONFIG_LIMIT_REG,Configuration requests are directed either to CDM or ELBI/RTRGT1 based on the value of this field. - Configuration requests with an address less CONFIG_LIMIT_REG are directed to the CDM - Configuration requests with an address greater.." newline bitfld.long 0x8 7. "CFG_TLP_BYPASS_EN_REG,Setting of this field defines which field TARGET_ABOVE_CONFIG_LIMIT_REG or CONFIG_LIMIT_REG decides the destination of Configuration requests. This field can have the following values: - 0: Configuration TLPs are routed according to.." "Configuration TLPs are routed according to the..,Configuration TLPs are routed according to the.." newline bitfld.long 0x8 6. "CPLQ_MNG_EN,This field enables the Completion Queue Management feature. Note: This register field is sticky." "0,1" newline bitfld.long 0x8 5. "ARI_DEVICE_NUMBER,When ARI is enabled this field enables use of the device ID. Note: This register field is sticky." "0,1" newline bitfld.long 0x8 4. "DISABLE_AUTO_LTR_CLR_MSG,Disable the autonomous generation of LTR clear message in upstream port. This field can have the following values: - 0: Allow the autonomous generation of LTR clear message. - 1: Disable the autonomous generation of LTR clear.." "Allow the autonomous generation of LTR clear..,Disable the autonomous generation of LTR clear.." newline bitfld.long 0x8 3. "SIMPLIFIED_REPLAY_TIMER,Enables Simplified Replay Timer (Gen4). For more details see 'Transmit Replay' in 'Transmit TLP Processing' section in the 'Controller Operations' chapter of the Databook. Simplified Replay Timer can have the following Values: -.." "0,1" newline bitfld.long 0x8 2. "UR_CA_MASK_4_TRGT1,When this field is set to '1' the controller suppresses error logging error message generation and CPL generation for non-posted requests TLPs (with UR filtering status) forwarded to your application (that is when DEFAULT_TARGET.." "0,1" newline bitfld.long 0x8 1. "DEFAULT_TARGET,Default target for an IO or MEM request with UR/CA/CRS received. Based on the value of this field the controller either drops or forwards these requests to your application. - 0: The controller drops all incoming I/O or MEM requests (after.." "The controller drops all incoming I/O or MEM..,The controller forwards all incoming I/O or MEM.." newline bitfld.long 0x8 0. "DBI_RO_WR_EN,Write to RO Registers Using DBI. Your application can write to some RO and HwInit register fields through the DBI when you set this field to '1'. For more details see 'Writing to Read-Only Registers' in 'Register Module LBC and DBI'.." "0,1" line.long 0xC "MULTI_LANE_CONTROL_OFF,UpConfigure Multi-lane Control Register. Used when upsizing or downsizing the link width through Configuration state without bringing the link down. For more details. see the 'Link Establishment' section in the 'Controller.." hexmask.long.tbyte 0xC 8.--31. 1. "RSVDP_8,Reserved for future use." newline bitfld.long 0xC 7. "UPCONFIGURE_SUPPORT,Upconfigure Support. The controller sends this value as the Link Upconfigure Capability in TS2 Ordered Sets in Configuration.Complete state. This field is reserved (fixed to '0') for M-PCIe. Note: This register field is sticky." "0,1" newline bitfld.long 0xC 6. "DIRECT_LINK_WIDTH_CHANGE,Directed Link Width Change. The controller always moves to Configuration state through Recovery state when this bit is set to '1'. - If the upconfigure_capable variable is '1' and the PCIE_CAP_HW_AUTO_WIDTH_DISABLE bit in.." "0,1" newline hexmask.long.byte 0xC 0.--5. 1. "TARGET_LINK_WIDTH,Target Link Width. Values correspond to: - 6'b000000: Controller does not start upconfigure or autonomous width downsizing in the Configuration state. - 6'b000001: x1 - 6'b000010: x2 - 6'b000100: x4 - 6'b001000: x8 - 6'b010000: x16 -.." line.long 0x10 "PHY_INTEROP_CTRL_OFF,PHY Interoperability Control Register." hexmask.long.tbyte 0x10 12.--31. 1. "RSVDP_12,Reserved for future use." newline bitfld.long 0x10 10. "L1_CLK_SEL,L1 Clock control bit. This field is reserved for internal use. You should not write to this field and change the default unless specifically instructed by Synopsys support. - 1: Controller does not request aux_clk switch and core_clk gating in.." "Controller requests aux_clk switch and core_clk..,Controller does not request aux_clk switch and.." newline rbitfld.long 0x10 9. "L1_NOWAIT_P1,L1 entry control bit. This field is reserved for internal use. You should not write to this field and change the default unless specifically instructed by Synopsys support. - 1: Controller does not wait for PHY to acknowledge transition to.." "Controller waits for the PHY to acknowledge..,Controller does not wait for PHY to acknowledge.." newline bitfld.long 0x10 8. "L1SUB_EXIT_MODE,L1 Exit Control Using phy_mac_pclkack_n. This field is reserved for internal use. You should not write to this field and change the default unless specifically instructed by Synopsys support. - 1: Controller exits L1 without waiting for.." "Controller waits for the PHY to assert..,Controller exits L1 without waiting for the PHY.." newline rbitfld.long 0x10 7. "RSVDP_7,Reserved for future use." "0,1" newline hexmask.long.byte 0x10 0.--6. 1. "RXSTANDBY_CONTROL,Rxstandby Control. Bits 0..5 determine if the controller asserts the RxStandby signal (mac_phy_rxstandby) in the indicated condition. Bit 6 enables the controller to perform the RxStandby/RxStandbyStatus handshake. This field is.." line.long 0x14 "TRGT_CPL_LUT_DELETE_ENTRY_OFF,TRGT_CPL_LUT Delete Entry Control register. Using this register you can delete one entry in the target completion LUT. You should only use this register when you know that your application will never send the completion.." bitfld.long 0x14 31. "DELETE_EN,This is a one-shot bit. A '1' write to this bit triggers the deletion of the target completion LUT entry that is specified in the LOOK_UP_ID field. This is a self-clearing register field. Reading from this register field always returns a '0'." "0,1" newline hexmask.long 0x14 0.--30. 1. "LOOK_UP_ID,This number selects one entry to delete of the TRGT_CPL_LUT." line.long 0x18 "LINK_FLUSH_CONTROL_OFF,Link Reset Request Flush Control Register." hexmask.long.byte 0x18 24.--31. 1. "RSVD_I_8,This is an internally reserved field. Do not use. Note: This register field is sticky." newline hexmask.long.tbyte 0x18 1.--23. 1. "RSVDP_1,Reserved for future use." newline bitfld.long 0x18 0. "AUTO_FLUSH_EN,Enables automatic flushing of pending requests before sending the reset request to the application logic to reset the PCIe controller and the AXI Bridge. The flushing process is initiated if any of the following events occur: - Hot reset.." "0,1" line.long 0x1C "AMBA_ERROR_RESPONSE_DEFAULT_OFF,AXI Bridge Slave Error Response Register." hexmask.long.word 0x1C 16.--31. 1. "RSVDP_16,Reserved for future use." newline hexmask.long.byte 0x1C 10.--15. 1. "AMBA_ERROR_RESPONSE_MAP,AXI Slave Response Error Map. Allows you to selectively map the errors received from the PCIe completion (for non-posted requests) to the AXI slave responses slv_rresp or slv_bresp. The recommended setting is SLVERR. CRS is.." newline hexmask.long.byte 0x1C 5.--9. 1. "RSVDP_5,Reserved for future use." newline bitfld.long 0x1C 3.--4. "AMBA_ERROR_RESPONSE_CRS,CRS Slave Error Response Mapping. Determines the AXI slave response for CRS completions. For more details see 'Error Handling' in the AXI chapter of the Databook. AHB: - always returns OKAY AXI: - 00: OKAY - 01: OKAY with all.." "OKAY,OKAY with all FFFF_FFFF data for all CRS..,?,?" newline bitfld.long 0x1C 2. "AMBA_ERROR_RESPONSE_VENDORID,Vendor ID Non-existent Slave Error Response Mapping. Determines the AXI slave response for errors on reads to non-existent Vendor ID register. For more details see 'Error Handling' in the AXI chapter of the Databook. AHB: -.." "OKAY,SLVERR/DECERR" newline rbitfld.long 0x1C 1. "RSVDP_1,Reserved for future use." "0,1" newline bitfld.long 0x1C 0. "AMBA_ERROR_RESPONSE_GLOBAL,Global Slave Error Response Mapping. Determines the AXI slave response for all error scenarios on non-posted requests. For more details see 'Error Handling' in the AXI chapter of the Databook. AHB: - 0: OKAY (with FFFF data for.." "OKAY,SLVERR/DECERR" line.long 0x20 "AMBA_LINK_TIMEOUT_OFF,Link Down AXI Bridge Slave Timeout Register. If your application AXI master issues outbound requests to the AXI bridge slave interface before the PCIe link is operational. the controller starts a 'flush' timer. The timeout value of.." hexmask.long.tbyte 0x20 9.--31. 1. "RSVDP_9,Reserved for future use." newline bitfld.long 0x20 8. "LINK_TIMEOUT_ENABLE_DEFAULT,Disable Flush. You can disable the flush feature by setting this field to '1'. Note: This register field is sticky." "0,1" newline hexmask.long.byte 0x20 0.--7. 1. "LINK_TIMEOUT_PERIOD_DEFAULT,Timeout Value (ms). The timer will timeout and then flush the bridge TX request queues after this amount of time. The timer counts when there are pending outbound AXI slave interface requests and the PCIe TX link is not.." line.long 0x24 "AMBA_ORDERING_CTRL_OFF,AMBA Ordering Control." hexmask.long.tbyte 0x24 8.--31. 1. "RSVDP_8,Reserved for future use." newline bitfld.long 0x24 7. "AX_MSTR_ZEROLREAD_FW,AXI Master Zero Length Read Forward to the application. The DW PCIe controller AXI bridge is able to terminate in order with the Posted transactions the zero length read implementing the PCIe express flush semantics of the Posted.." "The zero length Read is terminated at the DW..,The zero length Read is forward to the application" newline rbitfld.long 0x24 5.--6. "RSVDP_5,Reserved for future use." "0,1,2,3" newline bitfld.long 0x24 3.--4. "AX_MSTR_ORDR_P_EVENT_SEL,AXI Master Posted Ordering Event Selector. This field selects how the master interface determines when a P write is completed when enforcing the PCIe ordering rule 'NP must not pass P' at the AXI Master Interface. The AXI.." "B'last event: wait for the all of the write..,AW'last event: wait until the complete Posted..,This setting will not affect:,?" newline rbitfld.long 0x24 2. "RSVDP_2,Reserved for future use." "0,1" newline bitfld.long 0x24 1. "AX_SNP_EN,AXI Serialize Non-Posted Requests Enable. This field enables the AXI Bridge to serialize same ID Non-Posted Read/Write Requests on the wire. Serialization implies one outstanding same ID NP Read or Write on the wire and used to avoid AXI RAR.." "0,1" newline rbitfld.long 0x24 0. "RSVDP_0,Reserved for future use." "0,1" group.long (0x1E0+0x700)++0xB line.long 0x0 "COHERENCY_CONTROL_1_OFF,ACE Cache Coherency Control Register 1" hexmask.long 0x0 2.--31. 1. "CFG_MEMTYPE_BOUNDARY_LOW_ADDR,Boundary Lower Address For Memory Type. Bits [31:0] of dword-aligned address of the boundary for Memory type. The two lower address LSBs are '00'. Addresses up to but not including this value are in the lower address space.." newline rbitfld.long 0x0 1. "RSVDP_1,Reserved for future use." "0,1" newline bitfld.long 0x0 0. "CFG_MEMTYPE_VALUE,Sets the memory type for the lower and upper parts of the address space: - 0: lower = Peripheral; upper = Memory - 1: lower = Memory type; upper = Peripheral Note: This register field is sticky." "lower = Peripheral; upper = Memory,lower = Memory type; upper = Peripheral" line.long 0x4 "COHERENCY_CONTROL_2_OFF,ACE Cache Coherency Control Register 2" hexmask.long 0x4 0.--31. 1. "CFG_MEMTYPE_BOUNDARY_HIGH_ADDR,Boundary Upper Address For Memory Type. Bits [63:32] of the 64-bit dword-aligned address of the boundary for Memory type. Note: This register field is sticky." line.long 0x8 "COHERENCY_CONTROL_3_OFF,ACE Cache Coherency Control Register 3" hexmask.long.byte 0x8 27.--30. 1. "CFG_MSTR_AWCACHE_VALUE,Master Write CACHE Signal Value. Value of the individual bits in mstr_awcache when CFG_MSTR_AWCACHE_MODE is '1'. Note: not applicable to message requests; for message requests the value of mstr_awcache is always '0000' Note: This.." newline hexmask.long.byte 0x8 19.--22. 1. "CFG_MSTR_ARCACHE_VALUE,Master Read CACHE Signal Value. Value of the individual bits in mstr_arcache when CFG_MSTR_ARCACHE_MODE is '1'. Note: This register field is sticky." newline hexmask.long.byte 0x8 11.--14. 1. "CFG_MSTR_AWCACHE_MODE,Master Write CACHE Signal Behavior. Defines how the individual bits in mstr_awcache are controlled: - 0: set automatically by the AXI master - 1: set by the value of the corresponding bit of the CFG_MSTR_AWCACHE_VALUE field Note:.." newline hexmask.long.byte 0x8 3.--6. 1. "CFG_MSTR_ARCACHE_MODE,Master Read CACHE Signal Behavior. Defines how the individual bits in mstr_arcache are controlled: - 0: set automatically by the AXI master - 1: set by the value of the corresponding bit of the CFG_MSTR_ARCACHE_VALUE field Note:.." group.long (0x1F0+0x700)++0x7 line.long 0x0 "AXI_MSTR_MSG_ADDR_LOW_OFF,Lower 20 bits of the programmable AXI address where Messages coming from wire are mapped to. Bits [11:0] of the register are tied to zero for the address to be 4k-aligned. In previous releases. the third and fourth DWORDs of a.." hexmask.long.tbyte 0x0 12.--31. 1. "CFG_AXIMSTR_MSG_ADDR_LOW,Lower 20 bits of the programmable AXI address for Messages. Note: This register field is sticky." newline hexmask.long.word 0x0 0.--11. 1. "CFG_AXIMSTR_MSG_ADDR_LOW_RESERVED,Reserved for future use. Note: This register field is sticky." line.long 0x4 "AXI_MSTR_MSG_ADDR_HIGH_OFF,Upper 32 bits of the programmable AXI address where Messages coming from wire are mapped to." hexmask.long 0x4 0.--31. 1. "CFG_AXIMSTR_MSG_ADDR_HIGH,Upper 32 bits of the programmable AXI address for Messages. Note: This register field is sticky." rgroup.long (0x1F8+0x700)++0x7 line.long 0x0 "PCIE_VERSION_NUMBER_OFF,PCIe Controller IIP Release Version Number. The version number is given in hex format. You should convert each pair of hex characters to ASCII to interpret. Using 4.70a (GA) as an example: - VERSION_NUMBER = 0x3437302a which.." hexmask.long 0x0 0.--31. 1. "VERSION_NUMBER,Version Number." line.long 0x4 "PCIE_VERSION_TYPE_OFF,PCIe Controller IIP Release Version Type. The type is given in hex format. You should convert each pair of hex characters to ASCII to interpret. Using 4.70a (GA) as an example: - VERSION_NUMBER = 0x3437302a which translates to 470*.." hexmask.long 0x4 0.--31. 1. "VERSION_TYPE,Version Type." group.long (0x430+0x700)++0x3 line.long 0x0 "PL_LTR_LATENCY_OFF,LTR Latency Register. The function of this register field (and all other fields in this register) differs between an upstream port and a downstream port. For an upstream port. the register fields capture the corresponding fields in the.." bitfld.long 0x0 31. "NO_SNOOP_LATENCY_REQUIRE,No Snoop Latency Requirement. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" "0,1" newline rbitfld.long 0x0 29.--30. "RSVDP_29,Reserved for future use." "0,1,2,3" newline bitfld.long 0x0 26.--28. "NO_SNOOP_LATENCY_SCALE,No Snoop Latency Scale. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" "0,1,2,3,4,5,6,7" newline hexmask.long.word 0x0 16.--25. 1. "NO_SNOOP_LATENCY_VALUE,No Snoop Latency Value. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" newline bitfld.long 0x0 15. "SNOOP_LATENCY_REQUIRE,Snoop Latency Requirement. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" "0,1" newline rbitfld.long 0x0 13.--14. "RSVDP_13,Reserved for future use." "0,1,2,3" newline bitfld.long 0x0 10.--12. "SNOOP_LATENCY_SCALE,Snoop Latency Scale. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" "0,1,2,3,4,5,6,7" newline hexmask.long.word 0x0 0.--9. 1. "SNOOP_LATENCY_VALUE,Snoop Latency Value. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" group.long (0x440+0x700)++0xB line.long 0x0 "AUX_CLK_FREQ_OFF,Auxiliary Clock Frequency Control Register." hexmask.long.tbyte 0x0 10.--31. 1. "RSVDP_10,Reserved for future use." newline hexmask.long.word 0x0 0.--9. 1. "AUX_CLK_FREQ,The aux_clk frequency in MHz. This value is used to provide a 1 us reference for counting time during low-power states with aux_clk when the PHY has removed the pipe_clk. Frequencies lower than 1 MHz are possible but with a loss of accuracy.." line.long 0x4 "L1_SUBSTATES_OFF,L1 Substates Timing Register." hexmask.long.tbyte 0x4 9.--31. 1. "RSVDP_9,Reserved for future use." newline bitfld.long 0x4 8. "L1SUB_LOW_POWER_CLOCK_SWITCH_MODE,If this bit is set to 1'b1 the reference clock will be running regardless of the CLKREQ# setting. If this bit is set to 1'b0 the reference clock may be gated off when CLKREQ# is de-asserted. If the bit is set to 1'b1 the.." "0,1" newline bitfld.long 0x4 6.--7. "L1SUB_T_PCLKACK,Max delay (in 1us units) between a MAC request to remove the clock on mac_phy_pclkreq_n and a PHY response on phy_mac_pclkack_n. If the PHY does not respond within this time the request is aborted.The actual timeout value will be.." "0,1,2,3" newline hexmask.long.byte 0x4 2.--5. 1. "L1SUB_T_L1_2,Duration (in 1us units) of L1.2. The actual timeout value will be L1SUB_T_L1_2 + 1. Range is 0.15. Note: This register field is sticky." newline bitfld.long 0x4 0.--1. "L1SUB_T_POWER_OFF,Duration (in 1us units) of L1.2.Entry. The actual timeout value will be L1SUB_T_POWER_OFF + 1. Range is 0.3. Note: This register field is sticky." "0,1,2,3" line.long 0x8 "POWERDOWN_CTRL_STATUS_OFF,Powerdown Control and Status Register." hexmask.long.tbyte 0x8 12.--31. 1. "RSVDP_12,Reserved for future use." newline hexmask.long.byte 0x8 8.--11. 1. "POWERDOWN_PHY_POWERDOWN,This field represents the Powerdown value that has been acknowledged by the PHY. It is updated with the value of Powerdown driven by the controller when the PHY has returned the Phystatus acknowledgment for the Powerdown.." newline hexmask.long.byte 0x8 4.--7. 1. "POWERDOWN_MAC_POWERDOWN,This field represents the Powerdown value driven by the controller to the PHY." newline rbitfld.long 0x8 1.--3. "RSVDP_1,Reserved for future use." "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 0. "POWERDOWN_FORCE,This field is a one shot field. Writing a value of 1 to this field causes the controller to complete the P2 Powerdown handshake regardless of whether the PHY has returned Phystatus. This field could be used for debug purposes in event.." "0,1" group.long (0x470+0x700)++0x7 line.long 0x0 "PHY_VIEWPORT_CTLSTS_OFF,PHY Register Viewport Control and Status Register." rbitfld.long 0x0 31. "PHY_VIEWPORT_PENDING,PHY viewport pending. Indicates the access is pending. - 1 : Pending - 0 : Idle This bit is set to 1 when the read/write access has been initiated. This bit is cleared when the access is completed. If phy_reg_clk_g is never activated.." "Idle,Pending" newline rbitfld.long 0x0 30. "PHY_VIEWPORT_STATUS,PHY viewport status. Indicates the status of the latest access. - 1 : Timeout - 0 : No errors If the timeout is detected this bit is set to 1 and PHY_VIEWPORT_PENDING is cleared. This bit is cleared when the read/write access is.." "No errors,Timeout" newline hexmask.long.byte 0x0 23.--29. 1. "RSVDP_23,Reserved for future use." newline bitfld.long 0x0 22. "PHY_VIEWPORT_TIMEOUT_DISABLE,PHY viewport timeout disable. Disables the PHY register access timeout structure. When the timeout is disabled you must ensure that the PHY register accesses are always acknowledged by cr_para_ack. Otherwise.." "0,1" newline bitfld.long 0x0 21. "PHY_VIEWPORT_BCWR,Broadcast write access to all xN sub-blocks. If you need to broadcast the write accesses into all lanes both PHY_VIEWPORT_ADDR[15] and this bit should be 1. Note: This register field is sticky." "0,1" newline bitfld.long 0x0 20. "PHY_VIEWPORT_READ,PHY viewport read. If set a read access is initiated. The value is always 0 when this bit is read. Note: This register field is sticky." "0,1" newline hexmask.long.byte 0x0 16.--19. 1. "PHY_VIEWPORT_NUM,PHY viewport xN sub-block number. Selects one of xN sub-blocks. This register is not used when the write access is initiated with PHY_VIEWPORT_BCWR==1. Note: This register field is sticky." newline hexmask.long.word 0x0 0.--15. 1. "PHY_VIEWPORT_ADDR,PHY viewport address. Indicates the PHY's register address. Please refer to the PHY databook for the address map definition. Note: This register field is sticky." line.long 0x4 "PHY_VIEWPORT_DATA_OFF,PHY Register Viewport Data Register." hexmask.long.word 0x4 16.--31. 1. "RSVDP_16,Reserved for future use." newline hexmask.long.word 0x4 0.--15. 1. "PHY_VIEWPORT_DATA,PHY viewport data. A write access to this register initiates the PHY register write access. By a read access to this register this field returns the latest read data from the PHY register. Note: This register field is sticky." group.long (0x490+0x700)++0x3 line.long 0x0 "PIPE_RELATED_OFF,PIPE Related Register. This register controls the pipe's capabitity. control. and status parameters." hexmask.long.tbyte 0x0 9.--31. 1. "RSVDP_9,Reserved for future use." newline bitfld.long 0x0 8. "PIPE_GARBAGE_DATA_MODE,PIPE Garbage Data Mode. - 0: PIPE Spec compliant mode: The MAC discards any symbols received after the electrical idle ordered-set until RxValid is deasserted. - 1: Special PHY Support mode: The MAC discards any symbols received.." "PIPE Spec compliant mode: The MAC discards any..,Special PHY Support mode: The MAC discards any.." tree.end tree.end tree "PCIE2_ATU_DMA" base ad:0x311C0000 tree "PF0_TYPE1_HDR (PCI-Compatible Configuration Space Header Type1)" group.long 0x0++0x2F line.long 0x0 "TYPE1_DEV_ID_VEND_ID_REG,Device ID and Vendor ID Register." hexmask.long.word 0x0 16.--31. 1. "DEVICE_ID,Device ID. The Device ID register identifies the particular Function. This identifier is allocated by the vendor. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else.." newline hexmask.long.word 0x0 0.--15. 1. "VENDOR_ID,Vendor ID. The Vendor ID register identifies the manufacturer of the Function. Valid vendor identifiers are allocated by the PCI-SIG to ensure uniqueness. It is not permitted to populate this register with a value of FFFFh which is an invalid.." line.long 0x4 "TYPE1_STATUS_COMMAND_REG,Status and Command Register." bitfld.long 0x4 31. "DETECTED_PARITY_ERROR,Detected Parity Error. This bit is set by a Function whenever it receives a Poisoned TLP regardless of the state the Parity Error Response bit in the Command register. The bit is set when the Poisoned TLP is received by a.." "0,1" newline bitfld.long 0x4 30. "SIGNALED_SYS_ERROR,Signaled System Error. This bit is set when a Function sends an ERR_FATAL or ERR_NONFATAL Message and the SERR# Enable bit in the Command register is 1b." "0,1" newline bitfld.long 0x4 29. "RCVD_MASTER_ABORT,Received Master Abort. This bit is set when a Requester receives a Completion with Unsupported Request Completion status. The bit is set when the Unsupported Request is received by a Function's primary side." "0,1" newline bitfld.long 0x4 28. "RCVD_TARGET_ABORT,Received Target Abort. This bit is set when a Requester receives a Completion with Completer Abort Completion status. The bit is set when the Completer Abort is received by a Function's primary side." "0,1" newline bitfld.long 0x4 27. "SIGNALED_TARGET_ABORT,Signaled Target Abort. This bit is set when a Function completes a Posted or Non-Posted Request as a Completer Abort error. This applies to a Function when the Completer Abort was generated by its primary side." "0,1" newline rbitfld.long 0x4 25.--26. "DEV_SEL_TIMING,DEVSEL Timing. This field was originally described in the PCI Local Bus Specification. Its functionality does not apply to PCI Express. The controller hardwires it to 00b." "0,1,2,3" newline bitfld.long 0x4 24. "MASTER_DPE,Master Data Parity Error. This bit is set by a Function if the Parity Error Response bit in the Command register is 1b and either of the following two conditions occurs: - Port receives a Poisoned Completion going downstream - Port transmits a.." "0,1" newline rbitfld.long 0x4 23. "FAST_B2B_CAP,Fast Back-to-Back Transactions Capable. This bit was originally described in the PCI Local Bus Specification. Its functionality does not apply to PCI Express. The controller hardwires this bit to 0b." "0,1" newline rbitfld.long 0x4 22. "RSVDP_22,Reserved for future use." "0,1" newline rbitfld.long 0x4 21. "FAST_66MHZ_CAP,66 MHz Capable. This bit was originally described in the PCI Local Bus Specification. Its functionality does not apply to PCI Express. The controller hardwires this bit to 0b." "0,1" newline rbitfld.long 0x4 20. "CAP_LIST,Capabilities List. Indicates the presence of an Extended Capability list item. Since all PCI Express device Functions are required to implement the PCI Express Capability structure the controller hardwires this bit to 1b." "0,1" newline rbitfld.long 0x4 19. "INT_STATUS,Interrupt Status. When set indicates that an INTx emulation interrupt is pending internally in the Function. INTx emulation interrupts forwarded by Functions from the secondary side are not reflected in this bit. Setting the Interrupt Disable.." "0,1" newline rbitfld.long 0x4 17.--18. "RSVDP_17,Reserved for future use." "0,1,2,3" newline bitfld.long 0x4 16. "IMM_READINESS,Immediate Readiness. This optional bit when set indicates the Function is guaranteed to be ready to successfully complete valid configuration accesses at any time following any reset that the host is capable of issuing Configuration.." "0,1" newline hexmask.long.byte 0x4 11.--15. 1. "RESERV,Reserved." newline bitfld.long 0x4 10. "INT_EN,Interrupt Disable. Controls the ability of a Function to generate INTx emulation interrupts. When set Functions are prevented from asserting INTx interrupts. Note: - Any INTx emulation interrupts already asserted by the Function must be.." "0,1" newline rbitfld.long 0x4 9. "RSVDP_9,Reserved for future use." "0,1" newline bitfld.long 0x4 8. "SERREN,SERR# Enable. When set this bit enables reporting upstream of Non-fatal and Fatal errors detected by the Function. Note: The errors are reported if enabled either through this bit or through the PCI Express specific bits in the Device Control.." "0,1" newline rbitfld.long 0x4 7. "IDSEL,IDSEL Stepping/Wait Cycle Control. This bit was originally described in the PCI Local Bus Specification. Its functionality does not apply to PCI Express. The controller hardwires this bit to 0b." "0,1" newline bitfld.long 0x4 6. "PERREN,Parity Error Response. This bit controls the logging of poisoned TLPs in the Master Data Parity Error bit in the Status register. For more details see the 'Error Registers' section of the PCI Express Base Specification." "0,1" newline rbitfld.long 0x4 5. "VGAPS,VGA Palette Snoop. This bit was originally described in the PCI Local Bus Specification and the PCI-to-PCI Bridge Architecture Specification. Its functionality does not apply to PCI Express. The controller hardwires this bit to 0b." "0,1" newline rbitfld.long 0x4 4. "MWI_EN,Memory Write and Invalidate. This bit was originally described in the PCI Local Bus Specification and the PCI-to-PCI Bridge Architecture Specification. Its functionality does not apply to PCI Express. The controller hardwires this bit to 0b. For.." "0,1" newline rbitfld.long 0x4 3. "SCO,Special Cycle Enable. This bit was originally described in the PCI Local Bus Specification. Its functionality does not apply to PCI Express. The controller hardwires this bit to 0b." "0,1" newline bitfld.long 0x4 2. "BME,Bus Master Enable. This bit controls forwarding of Memory or I/O requests by a port in the Upstream direction. When this bit is 0b Memory and I/O Requests received at a Root Port must be handled as Unsupported Requests (UR) For Non-Posted Requests a.." "0,1" newline bitfld.long 0x4 1. "MSE,Memory Space Enable. This bit controls a Function's response to Memory Space accesses received on its primary side. - When set the Function is enabled to decode the address and further process Memory Space accesses. - When clear all received Memory.." "0,1" newline bitfld.long 0x4 0. "IO_EN,IO Space Enable. This bit controls a Function's response to I/O Space accesses received on its primary side. - When set the Function is enabled to decode the address and further process I/O Space accesses. - When clear all received I/O accesses.." "0,1" line.long 0x8 "TYPE1_CLASS_CODE_REV_ID_REG,Class Code and Revision ID Register." hexmask.long.byte 0x8 24.--31. 1. "BASE_CLASS_CODE,Base Class Code. A code that broadly classifies the type of operation the Function performs. Encodings for base class are provided in the PCI Code and ID Assignment Specification. All unspecified encodings are reserved. Note: The access.." newline hexmask.long.byte 0x8 16.--23. 1. "SUBCLASS_CODE,Sub-Class Code. Specifies a base class sub-class which identifies more specifically the operation of the Function. Encodings for sub-class are provided in the PCI Code and ID Assignment Specification. All unspecified encodings are.." newline hexmask.long.byte 0x8 8.--15. 1. "PROGRAM_INTERFACE,Programming Interface. This field identifies a specific register level programming interface (if any) so that device independent software can interact with the Function. Encodings for interface are provided in the PCI Code and ID.." newline hexmask.long.byte 0x8 0.--7. 1. "REVISION_ID,Revision ID. The value of this field specifies a Function specific revision identifier. The value is chosen by the vendor. Zero is an acceptable value. The Revision ID should be viewed as a vendor defined extension to the Device ID. Note: The.." line.long 0xC "TYPE1_BIST_HDR_TYPE_LAT_CACHE_LINE_SIZE_REG,BIST. Header Type. Latency Timer. and Cache Line Size Register." hexmask.long.byte 0xC 24.--31. 1. "BIST,BIST. This register is used for control and status of BIST. Functions that do not support BIST must hardwire the register to 00h. A Function whose BIST is invoked must not prevent normal operation of the PCI Express Link. Bit descriptions: - [31]:.." newline rbitfld.long 0xC 23. "MULTI_FUNC,Multi-Function Device. - When set indicates that the device may contain multiple Functions but not necessarily. Software is permitted to probe for Functions other than Function 0. - When clear software must not probe for Functions other.." "0,1" newline hexmask.long.byte 0xC 16.--22. 1. "HEADER_TYPE,Header Layout. This field identifies the layout of the second part of the predefined header. The controller uses 000 0001b encoding. The encoding 000 0010b is reserved. This encoding was originally described in the PC Card Standard Electrical.." newline hexmask.long.byte 0xC 8.--15. 1. "LATENCY_MASTER_TIMER,Latency Timer. This register is also referred to as Primary Latency Timer. The Latency Timer was originally described in the PCI Local Bus Specification and the PCI-to-PCI Bridge Architecture Specification. Its functionality does not.." newline hexmask.long.byte 0xC 0.--7. 1. "CACHE_LINE_SIZE,Cache Line Size. The Cache Line Size register is programmed by the system firmware or the operating system to system cache line size. However legacy conventional PCI software may not always be able to program this register correctly.." line.long 0x10 "BAR0_REG,BAR0 Register. System software must build a consistent address map before booting the machine to an operating system. This means it has to determine how much memory is in the system. and how much address space the Functions in the system.." hexmask.long 0x10 4.--31. 1. "BAR0_START,BAR0 Base Address. - Memory Space: Base Address. - IO Space: bits[31:2] are used to map the function into IO space/Base. Address. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R(Sticky)/W(Sticky) if.." newline bitfld.long 0x10 3. "BAR0_PREFETCH,BAR0 Prefetchable. - Memory Space: Set to one if data is pre-fetchable. A Function is permitted to mark a range as prefetchable. If there are no side effects on reads the function returns all bytes on reads regardless of the byte enables.." "0,1" newline bitfld.long 0x10 1.--2. "BAR0_TYPE,BAR0 Type. - Memory Space: Base Address registers that map into Memory Space can be 32 bits or 64 bits wide (to support mapping into a 64-bit address space). The bit encoding is as follows: -- 00: Base register is 32 bits wide and can be mapped.." "Base register is 32 bits wide and can be mapped..,Reserved,?,?" newline bitfld.long 0x10 0. "BAR0_MEM_IO,BAR0 Memory Space Indicator. This bit is used to determine whether the register maps into Memory or I/O Space. Base Address registers that map to Memory Space must return a 0b. Base Address registers that map to I/O Space must return a 1b." "0,1" line.long 0x14 "BAR1_REG,BAR1 Register. System software must build a consistent address map before booting the machine to an operating system. This means it has to determine how much memory is in the system. and how much address space the Functions in the system.." hexmask.long 0x14 4.--31. 1. "BAR1_START,BAR1 Base Address. - Memory Space: Base Address. - IO Space: bits[31:2] are used to map the function into IO space/Base. Address. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R(Sticky)/W(Sticky) if.." newline bitfld.long 0x14 3. "BAR1_PREFETCH,BAR1 Prefetchable. - Memory Space: Set to one if data is pre-fetchable. A Function is permitted to mark a range as prefetchable. If there are no side effects on reads the function returns all bytes on reads regardless of the byte enables.." "0,1" newline bitfld.long 0x14 1.--2. "BAR1_TYPE,BAR1 Type. - Memory Space: Base Address registers that map into Memory Space can be 32 bits or 64 bits wide (to support mapping into a 64-bit address space). The bit encoding is as follows: -- 00: Base register is 32 bits wide and can be mapped.." "Base register is 32 bits wide and can be mapped..,Reserved,?,?" newline bitfld.long 0x14 0. "BAR1_MEM_IO,BAR1 Memory Space Indicator. This bit is used to determine whether the register maps into Memory or I/O Space. Base Address registers that map to Memory Space must return a 0b. Base Address registers that map to I/O Space must return a 1b." "0,1" line.long 0x18 "SEC_LAT_TIMER_SUB_BUS_SEC_BUS_PRI_BUS_REG,Secondary Latency Timer. Subordinate Bus Number. Secondary Bus Number. and Primary Bus Number Register." hexmask.long.byte 0x18 24.--31. 1. "SEC_LAT_TIMER,Secondary Latency Timer. This register does not apply to PCI Express. The controller hardwires it to 00h." newline hexmask.long.byte 0x18 16.--23. 1. "SUB_BUS,Subordinate Bus Number. The Subordinate Bus Number register is used to record the bus number of the highest numbered PCI bus segment which is behind (or subordinate to) the bridge. Configuration software programs the value in this register. The.." newline hexmask.long.byte 0x18 8.--15. 1. "SEC_BUS,Secondary Bus Number. The Secondary Bus Number register is used to record the bus number of the PCI bus segment to which the secondary interface of the bridge is connected. Configuration software programs the value in this register. The bridge.." newline hexmask.long.byte 0x18 0.--7. 1. "PRIM_BUS,Primary Bus Number. This register is not used by PCI Express Functions. It is implemented for compatibility with legacy software." line.long 0x1C "SEC_STAT_IO_LIMIT_IO_BASE_REG,Secondary Status. and I/O Limit and Base Register. The I/O Limit and I/O Base registers are optional and define an address range that is used by the bridge to determine when to forward I/O transactions from one interface to.." bitfld.long 0x1C 31. "SEC_STAT_DPE,Detected Parity Error. This bit is set by a Function when a Poisoned TLP is received by its secondary side regardless of the state the Parity Error Response Enable bit in the Bridge Control register." "0,1" newline bitfld.long 0x1C 30. "SEC_STAT_RCVD_SYS_ERR,Received System Error. This bit is set when the secondary side of a Function receives an ERR_FATAL or ERR_NONFATAL message." "0,1" newline bitfld.long 0x1C 29. "SEC_STAT_RCVD_MSTR_ABRT,Received Master Abort. This bit is set when the secondary side of a Function (for requests initiated by the Type 1 header Function itself) receives a Completion with Unsupported Request Completion status." "0,1" newline bitfld.long 0x1C 28. "SEC_STAT_RCVD_TRGT_ABRT,Received Target Abort. This bit is set when the secondary side of a Function (for requests initiated by the Type 1 header Function itself) receives a Completion with Completer Abort Completion status." "0,1" newline bitfld.long 0x1C 27. "SEC_STAT_SIG_TRGT_ABRT,Signaled Target Abort. This bit is set when the secondary side of the Function (for Requests completed by the Type 1 header Function itself) completes a Posted or Non-Posted request as a Completer Abort error." "0,1" newline rbitfld.long 0x1C 25.--26. "RSVDP_25,Reserved for future use." "0,1,2,3" newline bitfld.long 0x1C 24. "SEC_STAT_MDPE,Master Data Parity Error. This bit is set by a Function if the Parity Error Response Enable bit in the Bridge Control register is set and either of the following two conditions occurs: - Port receives a Poisoned Completion coming Upstream.." "0,1" newline rbitfld.long 0x1C 23. "RSVDP_23,Reserved for future use." "0,1" newline hexmask.long.byte 0x1C 16.--22. 1. "SEC_STAT_RESERV,Reserved." newline hexmask.long.byte 0x1C 12.--15. 1. "IO_LIMIT,I/O Limit Address. These bits correspond to the address[15:12] of IO address range. For the purpose of address decoding the bridge assumes that the lower 12 address bits address[11:0] of the I/O limit address (not implemented in the I/O Limit.." newline rbitfld.long 0x1C 9.--11. "IO_RESERV1,Reserved." "0,1,2,3,4,5,6,7" newline bitfld.long 0x1C 8. "IO_DECODE_BIT8,I/O Addressing Encode (IO Limit Address). This bit encodes the IO addressing capability of the bridge. IO_DECODE_BIT8 indicates the following: - 0h: The bridge supports only 16-bit I/O addressing (for ISA compatibility). For the purpose of.." "0,1" newline hexmask.long.byte 0x1C 4.--7. 1. "IO_BASE,I/O Base Address. These bits correspond to the address[15:12] of IO address range. For the purpose of address decoding the bridge assumes that the lower 12 address bits address[11:0] of the I/O base address (not implemented in the I/O Base.." newline rbitfld.long 0x1C 1.--3. "IO_RESERV,Reserved." "0,1,2,3,4,5,6,7" newline bitfld.long 0x1C 0. "IO_DECODE,I/O Addressing Encode (IO Base Address) This bit encodes the IO addressing capability of the bridge. IO_DECODE indicates the following: - 0h: The bridge supports only 16-bit I/O addressing (for ISA compatibility). For the purpose of address.." "0,1" line.long 0x20 "MEM_LIMIT_MEM_BASE_REG,Memory Limit and Base Register. The Memory Limit and Memory Base registers define a memory mapped address range which is used by the bridge to determine when to forward memory transactions from one interface to the other. If there.." hexmask.long.word 0x20 20.--31. 1. "MEM_LIMIT,Memory Limit Address. These bits correspond to the upper 12 address bits Address[31:20] of 32-bit addresses. For the purpose of address decoding the bridge assumes that the lower 20 address bits Address[19:0] of the memory limit address.." newline hexmask.long.byte 0x20 16.--19. 1. "MEM_LIMIT_RESERV,Reserved." newline hexmask.long.word 0x20 4.--15. 1. "MEM_BASE,Memory Base Address. These bits correspond to the upper 12 address bits Address[31:20] of 32-bit addresses. For the purpose of address decoding the bridge assumes that the lower 20 address bits Address[19:0] of the memory base address (not.." newline hexmask.long.byte 0x20 0.--3. 1. "MEM_BASE_RESERV,Reserved." line.long 0x24 "PREF_MEM_LIMIT_PREF_MEM_BASE_REG,Prefetchable Memory Limit and Base Register. The Prefetchable Memory Limit and Prefetchable Memory Base registers must indicate that 64-bit addresses are supported. as defined in PCI-to-PCI Bridge Architecture.." hexmask.long.word 0x24 20.--31. 1. "PREF_MEM_LIMIT,Prefetchable Memory Limit Address. If the Prefetchable Memory Limit register indicates support for 32-bit addressing then the Prefetchable Limit Upper 32 Bits register is implemented as a read-only register that returns zero when read. If.." newline rbitfld.long 0x24 17.--19. "PREF_RESERV1,Reserved." "0,1,2,3,4,5,6,7" newline rbitfld.long 0x24 16. "PREF_MEM_LIMIT_DECODE,Prefetchable Memory Limit Decode. This bit encodes whether or not the bridge supports 64-bit addresses. Note: This bit is a copy of the PREF_MEM_DECODE bit and always reflects the current value of that bit. The value of.." "0,1" newline hexmask.long.word 0x24 4.--15. 1. "PREF_MEM_BASE,Prefetchable Memory Base Address. If the Prefetchable Memory Base register indicates support for 32-bit addressing then the Prefetchable Base Upper 32 Bits register is implemented as a read-only register that returns zero when read. If the.." newline rbitfld.long 0x24 1.--3. "PREF_RESERV,Reserved." "0,1,2,3,4,5,6,7" newline bitfld.long 0x24 0. "PREF_MEM_DECODE,Prefetchable Memory Base Decode. This bit encodes whether or not the bridge supports 64-bit addresses. Note: By default the bit is set to 1'b1 indicating that 64-bit addresses are supported. If the bridge only supports 32-bit prefetchable.." "0,1" line.long 0x28 "PREF_BASE_UPPER_REG,Prefetchable Base Upper 32 Bits Register. The Prefetchable Base Upper 32 Bits register is an optional extension to the Prefetchable Memory Base register." hexmask.long 0x28 0.--31. 1. "PREF_MEM_BASE_UPPER,Prefetchable Base Upper 32 Bit. If the Prefetchable Memory Base register indicates support for 32-bit addressing then this register is implemented as read-only register that returns zero when read. If the Prefetchable Memory Base.." line.long 0x2C "PREF_LIMIT_UPPER_REG,Prefetchable Limit Upper 32 Bits Register. The Prefetchable Limit Upper 32 Bits register is an optional extension to the Prefetchable Memory Limit register." hexmask.long 0x2C 0.--31. 1. "PREF_MEM_LIMIT_UPPER,Prefetchable Limit Upper 32 Bit. If the Prefetchable Memory Limit register indicate support for 64-bit addressing then this register is implemented as read/write register which must be initialized by configuration software. This.." rgroup.long 0x30++0x3 line.long 0x0 "IO_LIMIT_UPPER_IO_BASE_UPPER_REG,I/O Limit and Base Upper 16 Bits Register. The I/O Limit Upper 16 Bits and I/O Base Upper 16 Bits registers are optional extensions to the I/O Limit and I/O Base registers." hexmask.long.word 0x0 16.--31. 1. "IO_LIMIT_UPPER,I/O Limit Upper 16 Bits. If the I/O Limit register indicates support for 16-bit I/O address decoding then this register is implemented as a read-only register which return zero when read. If the I/O Limit register indicates support for.." newline hexmask.long.word 0x0 0.--15. 1. "IO_BASE_UPPER,I/O Base Upper 16 Bits. If the I/O Base register indicates support for 16-bit I/O address decoding then this register is implemented as a read-only register which return zero when read. If the I/O base register indicates support for 32-bit.." group.long 0x34++0xB line.long 0x0 "TYPE1_CAP_PTR_REG,Capabilities Pointer Register." hexmask.long.tbyte 0x0 8.--31. 1. "RSVDP_8,Reserved for future use." newline hexmask.long.byte 0x0 0.--7. 1. "CAP_POINTER,Capabilities Pointer. This register is used to point to a linked list of capabilities implemented by this Function. Since all PCI Express Functions are required to implement the PCI Express Capability structure this register must point to a.." line.long 0x4 "TYPE1_EXP_ROM_BASE_REG,Expansion ROM Base Address Register. This register is defined to handle the base address and size information for this expansion ROM. The mask for this ROM BAR exists (if implemented) as a shadow register at this address. The.." hexmask.long.tbyte 0x4 11.--31. 1. "EXP_ROM_BASE_ADDRESS,Expansion ROM Base Address. Upper 21 bits of the Expansion ROM base address. The number of bits (out of these 21) that a Function actually implements depends on how much address space the Function requires. The mask for this ROM BAR.." newline hexmask.long.word 0x4 1.--10. 1. "RSVDP_1,Reserved for future use." newline bitfld.long 0x4 0. "ROM_BAR_ENABLE,Expansion ROM Enable. This bit controls whether or not the Function accepts accesses to its expansion ROM. When this bit is 0b the Function's expansion ROM address space is disabled. When the bit is 1b address decoding is enabled using.." "0,1" line.long 0x8 "BRIDGE_CTRL_INT_PIN_INT_LINE_REG,Bridge Control. Interrupt Pin. and Interrupt Line Register." hexmask.long.word 0x8 23.--31. 1. "BRIDGE_CTRL_RESERV,Reserved." newline bitfld.long 0x8 22. "SBR,Secondary Bus Reset. Setting this bit triggers a hot reset on the corresponding PCI Express Port. Software must ensure a minimum reset duration (Trst) as defined in the PCI Local Bus Specification. Software and systems must honor.." "0,1" newline rbitfld.long 0x8 21. "MSTR_ABORT_MODE,Master Abort Mode. This bit was originally described in the PCI-to-PCI Bridge Architecture Specification. Its functionality does not apply to PCI Express. The controller hardwires this bit to 0b. Note: The access attributes of this field.." "0,1" newline rbitfld.long 0x8 20. "VGA_16B_DEC,VGA 16 bit decode. This bit only has meaning if VGA Enable bit is set. This bit enables system configuration software to select between 10-bit and 16-bit I/O address decoding for all VGA I/O register accesses that are forwarded from primary.." "0,1" newline rbitfld.long 0x8 19. "VGA_EN,VGA Enable. Modifies the response by the bridge to VGA compatible addresses. If the VGA Enable bit is set the bridge will positively decode and forward the following accesses on the primary interface to the secondary interface (and conversely.." "0,1" newline bitfld.long 0x8 18. "ISA_EN,ISA Enable. Modifies the response by the bridge to ISA I/O addresses. This applies only to I/O addresses that are enabled by the I/O Base and I/O Limit registers and are in the first 64 KB of I/O address space (0000 0000h to 0000 FFFFh). If this.." "?,KB block" newline bitfld.long 0x8 17. "SERR_EN,SERR# Enable. This bit controls forwarding of ERR_COR ERR_NONFATAL and ERR_FATAL from secondary to primary." "0,1" newline bitfld.long 0x8 16. "PERE,Parity Error Response Enable. This bit controls the logging of poisoned TLPs in the Master Data Parity Error bit in the Secondary Status register." "0,1" newline hexmask.long.byte 0x8 8.--15. 1. "INT_PIN,Interrupt PIN. The Interrupt Pin register register that identifies the legacy interrupt Message(s) the Function uses. Valid values are: - 01h 02h 03h and 04h: map to legacy interrupt Messages for INTA INTB INTC and INTD respectively. - 00h:.." newline hexmask.long.byte 0x8 0.--7. 1. "INT_LINE,Interrupt Line. The Interrupt Line register communicates interrupt line routing information. The register must be implemented by any Function that uses an interrupt pin. Values in this register are programmed by system software and are system.." tree.end tree "PF0_SPCIE_CAP (Secondary PCI Express Capability Structure)" group.long (0x0+0x1A0)++0xF line.long 0x0 "SPCIE_CAP_HEADER_REG,SPCIE Capability Header. For a description of this standard PCIe register. see the PCI Express Specification." hexmask.long.word 0x0 20.--31. 1. "NEXT_OFFSET,Next Capability Offset. For a description of this standard PCIe register field see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky).." hexmask.long.byte 0x0 16.--19. 1. "CAP_VERSION,Capability Version. For a description of this standard PCIe register field see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else.." hexmask.long.word 0x0 0.--15. 1. "EXTENDED_CAP_ID,Secondary PCI Express Extended Capability ID. For a description of this standard PCIe register field see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN.." line.long 0x4 "LINK_CONTROL3_REG,Link Control 3 Register. For a description of this standard PCIe register. see the PCI Express Specification." hexmask.long 0x4 2.--31. 1. "RSVDP_2,Reserved for future use." bitfld.long 0x4 1. "EQ_REQ_INT_EN,Link Equalization Request Interrupt Enable. For a description of this standard PCIe register field see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" "0,1" bitfld.long 0x4 0. "PERFORM_EQ,Perform Equalization. For a description of this standard PCIe register field see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" "0,1" line.long 0x8 "LANE_ERR_STATUS_REG,Lane Error Status Register. For a description of this standard PCIe register. see the PCI Express Specification." hexmask.long 0x8 1.--31. 1. "RSVDP_LANE_ERR_STATUS,Reserved for future use." bitfld.long 0x8 0. "LANE_ERR_STATUS,Lane Error Status Bits per Lane. For a description of this standard PCIe register field see the PCI Express Specification." "0,1" line.long 0xC "SPCIE_CAP_OFF_0CH_REG,Lane Equalization Control Register for lanes 1 and 0. For a description of this standard PCIe register. see the PCI Express Specification." rbitfld.long 0xC 31. "RSVDP_31,Reserved for future use." "0,1" rbitfld.long 0xC 23. "RSVDP_23,Reserved for future use." "0,1" rbitfld.long 0xC 15. "RSVDP_15,Reserved for future use." "0,1" bitfld.long 0xC 12.--14. "USP_RX_PRESET_HINT0,Upstream Port 8.0 GT/s Receiver Preset Hint 0. The write value is gated with the PCIE_CAP_CROSS_LINK_SUPPORT field of LINK_CAPABILITIES2_REG. For a description of this standard PCIe register field see the PCI Express Specification." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0xC 8.--11. 1. "USP_TX_PRESET0,Upstream Port 8.0 GT/s Transmitter Preset 0. The write value is gated with the PCIE_CAP_CROSS_LINK_SUPPORT field of LINK_CAPABILITIES2_REG. For a description of this standard PCIe register field see the PCI Express Specification. Note:.." rbitfld.long 0xC 7. "RSVDP_7,Reserved for future use." "0,1" bitfld.long 0xC 4.--6. "DSP_RX_PRESET_HINT0,Downstream Port 8.0 GT/s Receiver Preset Hint 0. For a description of this standard PCIe register field see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if.." "0,1,2,3,4,5,6,7" hexmask.long.byte 0xC 0.--3. 1. "DSP_TX_PRESET0,Downstream Port 8.0 GT/s Transmitter Preset 0. For a description of this standard PCIe register field see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN.." tree.end tree "PF0_L1SUB_CAP (L1 Substates Capability Structure)" group.long (0x0+0x2A0)++0xF line.long 0x0 "L1SUB_CAP_HEADER_REG,L1 Substates Extended Capability Header. This register provides capbility ID. capability version and next offset value for L1 Substates." hexmask.long.word 0x0 20.--31. 1. "NEXT_OFFSET,Next Capability Offset. This field contains the offset to the next PCI Express Capability structure or 000h if no other items exist in the linked list of Capabilities. For Extended Capabilities implemented in Configuration Space this offset.." hexmask.long.byte 0x0 16.--19. 1. "CAP_VERSION,Capability Version. This field is a PCI-SIG defined version number that indicates the version of the Capability structure present. This field is depends on version of the specification. Note: The access attributes of this field are as.." hexmask.long.word 0x0 0.--15. 1. "EXTENDED_CAP_ID,L1SUB Extended Capability ID. This field is a PCI-SIG defined ID number that indicates the nature and format of the Extended Capability. Extended Capability ID for L1 PM Substates is 001Eh. Note: The access attributes of this field are as.." line.long 0x4 "L1SUB_CAPABILITY_REG,L1 Substates Capability Register. This register provides extended capability of L1 Substates." hexmask.long.byte 0x4 24.--31. 1. "RSVDP_24,Reserved for future use." hexmask.long.byte 0x4 19.--23. 1. "PWR_ON_VALUE_SUPPORT,Port T Power On Value. Along with the Port T_POWER_ON Scale field in the L1 PM Substates Capabilities register sets the time (in us) that this Port requires the port on the opposite side of Link to wait in L1.2.Exit after sampling.." rbitfld.long 0x4 18. "RSVDP_18,Reserved for future use." "0,1" bitfld.long 0x4 16.--17. "PWR_ON_SCALE_SUPPORT,Port T Power On Scale. Specifies the scale used for the Port T_POWER_ON Value field in the L1 PM Substates Capabilities register. Range of values are given below. Required for all Ports for which either the PCI-PM L1.2 Supported bit.." "?,?,?,Reserved" newline hexmask.long.byte 0x4 8.--15. 1. "COMM_MODE_SUPPORT,Port Common Mode Restore Time. Time (in us) required for this Port to re-establish common mode. Required for all Ports for which either the PCI-PM L1.2 Supported bit is Set ASPM L1.2 Supported bit is Set or both are Set otherwise.." rbitfld.long 0x4 5.--7. "RSVDP_5,Reserved for future use." "0,1,2,3,4,5,6,7" bitfld.long 0x4 4. "L1_PMSUB_SUPPORT,L1 PM Substates ECN Supported. When Set this bit indicates that this Port supports L1 PM Substates. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W (sticky)" "0,1" bitfld.long 0x4 3. "L1_1_ASPM_SUPPORT,ASPM L11 Supported. When Set this bit indicates that ASPM L1.1 is supported. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W (sticky)" "0,1" newline bitfld.long 0x4 2. "L1_2_ASPM_SUPPORT,ASPM L12 Supported. When Set this bit indicates that ASPM L1.2 is supported. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W (sticky)" "0,1" bitfld.long 0x4 1. "L1_1_PCIPM_SUPPORT,PCI-PM L11 Supported. When Set this bit indicates that PCI-PM L1.1 is supported and must be Set by all Ports implementing L1 PM Substates. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W (sticky)" "0,1" bitfld.long 0x4 0. "L1_2_PCIPM_SUPPORT,PCI-PM L12 Supported. When Set this bit indicates that PCI-PM L1.2 is supported. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W (sticky)" "0,1" line.long 0x8 "L1SUB_CONTROL1_REG,L1 Substates Control 1 Register. This register provides Controls to extended capability." bitfld.long 0x8 29.--31. "L1_2_TH_SCA,LTR L12 Threshold Scale. This field provides a scale for the value contained within the LTR_L1.2_THRESHOLD_Value.The default value for this field is 000b.Hardware operation is undefined if software writes a Not-Permitted value to this field." "0,1,2,3,4,5,6,7" rbitfld.long 0x8 26.--28. "RSVDP_26,Reserved for future use." "0,1,2,3,4,5,6,7" hexmask.long.word 0x8 16.--25. 1. "L1_2_TH_VAL,LTR L12 Threshold Value. Along with the LTR_L1.2_THRESHOLD_Scale this field indicates the LTR threshold used to determine if entry into L1 results in L1.1 (if enabled) or L1.2 (if enabled). The default value for this field is 00 0000 0000b." hexmask.long.byte 0x8 8.--15. 1. "T_COMMON_MODE,Common Mode Restore Time. Sets value of TCOMMONMODE (in us) which must be used by the Downstream Ports for timing the re-establishment of common mode.This field is of type RsvdP for Upstream Ports. Default value is implementation.." newline hexmask.long.byte 0x8 4.--7. 1. "RSVDP_4,Reserved for future use." bitfld.long 0x8 3. "L1_1_ASPM_EN,ASPM L11 Enable. When Set this bit enables ASPM L1.1.For Ports for which the ASPM L1.1 Supported bit is Clear this bit is permitted to be hardwired to 0.Default value is 0b." "0,1" bitfld.long 0x8 2. "L1_2_ASPM_EN,ASPM L12 Enable. When Set this bit enables ASPM L1.2.For Ports for which the ASPM L1.2 Supported bit is Clear this bit is permitted to be hardwired to 0.Default value is 0b." "0,1" bitfld.long 0x8 1. "L1_1_PCIPM_EN,PCI-PM L11 Enable. When Set this bit enables PCI-PM L1.1. Default value is 0b." "0,1" newline bitfld.long 0x8 0. "L1_2_PCIPM_EN,PCI-PM L12 Enable. When Set this bit enables PCI-PM L1.2.For Ports for which the PCI-PM L1.2 Supported bit is Clear this bit is permitted to be hardwired to 0.Default value is 0b." "0,1" line.long 0xC "L1SUB_CONTROL2_REG,L1 Substates Control 2 Register. This register provides Controls to extended capability." hexmask.long.tbyte 0xC 8.--31. 1. "RSVDP_8,Reserved for future use." hexmask.long.byte 0xC 3.--7. 1. "T_POWER_ON_VALUE,T Power On Value. Along with the T_POWER_ON Scale sets the minimum amount of time (in us) that the Port must wait in L1.2.Exit after sampling CLKREQ# asserted before actively driving the interface.Default value is 00101b. T_POWER_ON is.." rbitfld.long 0xC 2. "RSVDP_2,Reserved for future use." "0,1" bitfld.long 0xC 0.--1. "T_POWER_ON_SCALE,T Power On Scale. Specifies the scale used for T_POWER_ON Value. Range of values are given below. Required for all Ports that support L1.2 otherwise this field is of type RsvdP. This field must only be modified when the ASPM L1.2 Enable.." "?,?,?,Reserved" tree.end tree "PF0_RAS_DES_CAP (RAS D.E.S. Capability Structure (VSEC))" group.long (0x0+0x30C)++0x3 line.long 0x0 "RAS_DES_CAP_HEADER_REG,Vendor-Specific Extended Capability Header. For a description of this standard PCIe register. see the PCI Express Specification." hexmask.long.word 0x0 20.--31. 1. "NEXT_OFFSET,Next Capability Offset. For a description of this standard PCIe register field see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky).." newline hexmask.long.byte 0x0 16.--19. 1. "CAP_VERSION,Capability Version. For a description of this standard PCIe register field see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else.." newline hexmask.long.word 0x0 0.--15. 1. "EXTENDED_CAP_ID,PCI Express Extended Capability ID. For a description of this standard PCIe register field see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then.." rgroup.long (0x4+0x30C)++0x3 line.long 0x0 "VENDOR_SPECIFIC_HEADER_REG,Vendor-Specific Header. For a description of this standard PCIe register. see the PCI Express Specification." hexmask.long.word 0x0 20.--31. 1. "VSEC_LENGTH,VSEC Length. For a description of this standard PCIe register field see the PCI Express Specification." newline hexmask.long.byte 0x0 16.--19. 1. "VSEC_REV,VSEC Rev. For a description of this standard PCIe register field see the PCI Express Specification." newline hexmask.long.word 0x0 0.--15. 1. "VSEC_ID,VSEC ID. For a description of this standard PCIe register field see the PCI Express Specification." group.long (0x8+0x30C)++0x3 line.long 0x0 "EVENT_COUNTER_CONTROL_REG,Event Counter Control. This is a viewport control register. - Setting the EVENT_COUNTER_EVENT_SELECT and EVENT_COUNTER_LANE_SELECT fields in this register determine the Event Counter data returned by the EVENT_COUNTER_DATA_REG.." hexmask.long.byte 0x0 28.--31. 1. "RSVDP_28,Reserved for future use." newline hexmask.long.word 0x0 16.--27. 1. "EVENT_COUNTER_EVENT_SELECT,Event Counter Data Select. This field in conjunction with the EVENT_COUNTER_LANE_SELECT field indexes the Event Counter data returned by the EVENT_COUNTER_DATA_REG register. - 27-24: Group number(4-bit: 0..0x7) - 23-16: Event.." newline hexmask.long.byte 0x0 12.--15. 1. "RSVDP_12,Reserved for future use." newline hexmask.long.byte 0x0 8.--11. 1. "EVENT_COUNTER_LANE_SELECT,Event Counter Lane Select. This field in conjunction with EVENT_COUNTER_EVENT_SELECT indexes the Event Counter data returned by the EVENT_COUNTER_DATA_REG register. - 0x0: Lane0 - 0x1: Lane1 - 0x2: Lane2 - .. - 0xF: Lane15 Note:.." newline rbitfld.long 0x0 7. "EVENT_COUNTER_STATUS,Event Counter Status. This register returns the current value of the Event Counter selected by the following fields: - EVENT_COUNTER_EVENT_SELECT - EVENT_COUNTER_LANE_SELECT Note: This register field is sticky." "0,1" newline rbitfld.long 0x0 5.--6. "RSVDP_5,Reserved for future use." "0,1,2,3" newline bitfld.long 0x0 2.--4. "EVENT_COUNTER_ENABLE,Event Counter Enable. Enables/disables the Event Counter selected by the EVENT_COUNTER_EVENT_SELECT and EVENT_COUNTER_LANE_SELECT fields in this register. By default all event counters are disabled. You can enable/disable a specific.." "no change,per event off,?,?,?,?,?,?" newline bitfld.long 0x0 0.--1. "EVENT_COUNTER_CLEAR,Event Counter Clear. Clears the Event Counter selected by the EVENT_COUNTER_EVENT_SELECT and EVENT_COUNTER_LANE_SELECT fields in this register. You can clear the value of a specific Event Counter by writing the 'per clear' code and.." "no change,per clear,?,?" rgroup.long (0xC+0x30C)++0x3 line.long 0x0 "EVENT_COUNTER_DATA_REG,Event Counter Data. This viewport register returns the data selected by the following fields: - EVENT_COUNTER_EVENT_SELECT in EVENT_COUNTER_CONTROL_REG - EVENT_COUNTER_LANE_SELECT in EVENT_COUNTER_CONTROL_REG For more details. see.." hexmask.long 0x0 0.--31. 1. "EVENT_COUNTER_DATA,Event Counter Data. This register returns the data selected by the following fields: - EVENT_COUNTER_EVENT_SELECT in EVENT_COUNTER_CONTROL_REG - EVENT_COUNTER_LANE_SELECT in EVENT_COUNTER_CONTROL_REG Note: This register field is sticky." group.long (0x10+0x30C)++0x3 line.long 0x0 "TIME_BASED_ANALYSIS_CONTROL_REG,Time-based Analysis Control. Used for controlling the measurement of RX/TX data throughput and time spent in each low-power LTSSM state. For more details. see the RAS DES section in the Core Operations chapter of the.." hexmask.long.byte 0x0 24.--31. 1. "TIME_BASED_REPORT_SELECT,Time-based Report Select. Selects what type of data is measured for the selected duration (TIME_BASED_DURATION_SELECT) and returned in TIME_BASED_ANALYSIS_DATA. Each type of data is measured using one of three types of units: -.." newline hexmask.long.byte 0x0 16.--23. 1. "RSVDP_16,Reserved for future use." newline hexmask.long.byte 0x0 8.--15. 1. "TIME_BASED_DURATION_SELECT,Time-based Duration Select. Selects the duration of time-based analysis. When 'manual control' is selected and TIMER_START is set to '1' this analysis never stops until TIMER_STOP is set to '0'. - 0x0: Manual control - 0x1:.." newline hexmask.long.byte 0x0 1.--7. 1. "RSVDP_1,Reserved for future use." newline bitfld.long 0x0 0. "TIMER_START,Timer Start. - 1: Start/Restart - 0: Stop This bit will be cleared automatically when the measurement is finished. Note: The app_ras_des_tba_ctrl input also sets the contents of this field and controls the measurement start/stop. Note: This.." "Stop,Start/Restart" rgroup.long (0x14+0x30C)++0x7 line.long 0x0 "TIME_BASED_ANALYSIS_DATA_REG,Time-based Analysis Data. Contains the measurement results of RX/TX data throughput and time spent in each low-power LTSSM state. This viewport register returns the data selected by the TIME_BASED_REPORT_SELECT field in.." hexmask.long 0x0 0.--31. 1. "TIME_BASED_ANALYSIS_DATA,Time Based Analysis Data. This register returns the data selected by the TIME_BASED_REPORT_SELECT field in TIME_BASED_ANALYSIS_CONTROL_REG. The results are cleared when next measurement starts. Note: This register field is sticky." line.long 0x4 "TIME_BASED_ANALYSIS_DATA_63_32_REG,Upper 32 bits of Time-based Analysis Data. This viewport register returns the data selected by the TIME_BASED_REPORT_SELECT field in TIME_BASED_ANALYSIS_CONTROL_REG. For more details. see the RAS DES section in the Core.." hexmask.long 0x4 0.--31. 1. "TIME_BASED_ANALYSIS_DATA_63_32,Upper 32 bits of Time Based Analysis Data. Note: This register field is sticky." group.long (0x30+0x30C)++0x5F line.long 0x0 "EINJ_ENABLE_REG,Error Injection Enable. Each type of error insertion is enabled by the corresponding bit in this register. The specific injection controls for each type of error are defined in the following registers: - 0: CRC Error: EINJ0_CRC_REG - 1:.." hexmask.long 0x0 7.--31. 1. "RSVDP_7,Reserved for future use." newline bitfld.long 0x0 6. "ERROR_INJECTION6_ENABLE,Error Injection6 Enable (Specific TLP Error). Enables insertion of errors into the packets that you select. You can set this bit to '1' when you have disabled RAS datapath protection (DP) by setting CX_RASDP = CX_RASDP_RAM_PROT.." "0,1" newline bitfld.long 0x0 5. "ERROR_INJECTION5_ENABLE,Error Injection5 Enable (TLP Duplicate/Nullify Error). Enables insertion of duplicate/nullified TLPs. For more details see the EINJ5_SP_TLP_REG register. Note: This register field is sticky." "0,1" newline bitfld.long 0x0 4. "ERROR_INJECTION4_ENABLE,Error Injection4 Enable (FC Credit Update Error). Enables insertion of errors into UpdateFCs. For more details see the EINJ4_FC_REG register. Note: This register field is sticky." "0,1" newline bitfld.long 0x0 3. "ERROR_INJECTION3_ENABLE,Error Injection3 Enable (Symbol DataK Mask Error or Sync Header Error). Enables DataK masking of special symbols or the breaking of the sync header. For more details see the EINJ3_SYMBOL_REG register. Note: This register field is.." "0,1" newline bitfld.long 0x0 2. "ERROR_INJECTION2_ENABLE,Error Injection2 Enable (DLLP Error). Enables insertion of DLLP errors. For more details see the EINJ2_DLLP_REG register. Note: This register field is sticky." "0,1" newline bitfld.long 0x0 1. "ERROR_INJECTION1_ENABLE,Error Injection1 Enable (Sequence Number Error). Enables insertion of errors into sequence numbers. For more details see the EINJ1_SEQNUM_REG register. Note: This register field is sticky." "0,1" newline bitfld.long 0x0 0. "ERROR_INJECTION0_ENABLE,Error Injection0 Enable (CRC Error). Enables insertion of errors into various CRC. For more details see the EINJ0_CRC_REG register. Note: This register field is sticky." "0,1" line.long 0x4 "EINJ0_CRC_REG,Error Injection Control 0 (CRC Error). Controls the insertion of errors into the CRC. and parity of ordered sets for the selected type of the packets as follows: - LCRC. Bad TLP will be detected at the receiver side; receiver responds with.." hexmask.long.tbyte 0x4 12.--31. 1. "RSVDP_12,Reserved for future use." newline hexmask.long.byte 0x4 8.--11. 1. "EINJ0_CRC_TYPE,Error injection type. Selects the type of CRC error to be inserted. Tx Path - 0000b: New TLP's LCRC error injection - 0001b: 16bCRC error injection of ACK/NAK DLLP - 0010b: 16bCRC error injection of Update-FC DLLP - 0011b: New TLP's ECRC.." newline hexmask.long.byte 0x4 0.--7. 1. "EINJ0_COUNT,Error injection count. Indicates the number of errors. This register is decremented when the errors have been inserted. - If the counter value is 0x01 and error is inserted ERROR_INJECTION0_ENABLE in EINJ_ENABLE_REG returns 0b. - If the.." line.long 0x8 "EINJ1_SEQNUM_REG,Error Injection Control 1 (Sequence Number Error). Controls the sequence number of the specific TLPs and ACK/NAK DLLPs. Data Link Protocol Error will be detected at the Rx side of ACK/NAL DLLPs when one of these conditions is true: -.." rbitfld.long 0x8 29.--31. "RSVDP_29,Reserved for future use." "0,1,2,3,4,5,6,7" newline hexmask.long.word 0x8 16.--28. 1. "EINJ1_BAD_SEQNUM,Bad sequence number. Indicates the value to add/subtract from the naturally-assigned sequence numbers. This value is represented by two's complement. - 0x0FFF: +4095 - .. - 0x0002: +2 - 0x0001: +1 - 0x0000: 0 - 0x1FFF: -1 - 0x1FFE: -2 -.." newline hexmask.long.byte 0x8 9.--15. 1. "RSVDP_9,Reserved for future use." newline bitfld.long 0x8 8. "EINJ1_SEQNUM_TYPE,Sequence number type. Selects the type of sequence number. - 0b: Insertion of New TLP's SEQ# error - 1b: Insertion of ACK/NAK DLLP's SEQ# Error Note: This register field is sticky." "0,1" newline hexmask.long.byte 0x8 0.--7. 1. "EINJ1_COUNT,Error injection count. Indicates the number of errors. This register is decremented as the errors are being inserted. - If the counter value is 0x01 and error is inserted ERROR_INJECTION1_ENABLE in EINJ_ENABLE_REG returns '0'. - If the.." line.long 0xC "EINJ2_DLLP_REG,Error Injection Control 2 (DLLP Error). Controls the transmission of DLLPs and inserts the following errors: - If 'ACK/NAK DLLP's transmission block' is selected. replay timeout error will occur at the transmitter of the TLPs and then Data.." hexmask.long.tbyte 0xC 10.--31. 1. "RSVDP_10,Reserved for future use." newline bitfld.long 0xC 8.--9. "EINJ2_DLLP_TYPE,DLLP Type. Selects the type of DLLP errors to be inserted. - 00b: ACK/NAK DLLP's transmission block - 01b: Update FC DLLP's transmission block - 10b: Always Transmission for NAK DLLP - 11b: Reserved Note: This register field is sticky." "0,1,2,3" newline hexmask.long.byte 0xC 0.--7. 1. "EINJ2_COUNT,Error injection count. Indicates the number of errors. This register is decremented as the errors are being inserted. - If the counter value is 0x01 and the error is inserted ERROR_INJECTION2_ENABLE in EINJ_ENABLE_REG returns '0'. - If the.." line.long 0x10 "EINJ3_SYMBOL_REG,Error Injection Control 3 (Symbol Error). When 8b/10b encoding is used. this register controls error insertion into the special (K code) symbols. - If TS1/TS2/FTS/E-Idle/SKP is selected. it affects whole of the ordered set. It might.." hexmask.long.tbyte 0x10 11.--31. 1. "RSVDP_11,Reserved for future use." newline bitfld.long 0x10 8.--10. "EINJ3_SYMBOL_TYPE,Error Type. 8b/10b encoding - Mask K symbol. It is not supported to insert errors into the first ordered-set after exiting from TxElecIdle when CX_FREQ_STEP_EN has been enabled. - 000b: Reserved - 001b: COM/PAD(TS1 Order set) - 010b:.." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x10 0.--7. 1. "EINJ3_COUNT,Error injection count. Indicates the number of errors. This register is decremented as the errors are being inserted. - If the counter value is 0x01 and error is inserted ERROR_INJECTION3_ENABLE in EINJ_ENABLE_REG returns '0'. - If the.." line.long 0x14 "EINJ4_FC_REG,Error Injection Control 4 (FC Credit Error). Controls error insertion into the credit value in the UpdateFCs. It is possible to insert errors for any of the following types: - Posted TLP Header credit - Non-Posted TLP Header credit -.." rbitfld.long 0x14 29.--31. "RSVDP_29,Reserved for future use." "0,1,2,3,4,5,6,7" newline hexmask.long.word 0x14 16.--28. 1. "EINJ4_BAD_UPDFC_VALUE,Bad update-FC credit value. Indicates the value to add/subtract from the UpdateFC credit. This value is represented by two's complement. - 0x0FFF: +4095 - .. - 0x0002: +2 - 0x0001: +1 - 0x0000: 0 - 0x1FFF: -1 - 0x1FFE: -2 - .. -.." newline rbitfld.long 0x14 15. "RSVDP_15,Reserved for future use." "0,1" newline bitfld.long 0x14 12.--14. "EINJ4_VC_NUMBER,VC Number. Indicates target VC Number. Note: This register field is sticky." "0,1,2,3,4,5,6,7" newline rbitfld.long 0x14 11. "RSVDP_11,Reserved for future use." "0,1" newline bitfld.long 0x14 8.--10. "EINJ4_UPDFC_TYPE,Update-FC type. Selects the credit type. - 000b: Posted TLP Header Credit value control - 001b: Non-Posted TLP Header Credit value control - 010b: Completion TLP Header Credit value control - 011b: Reserved - 100b: Posted TLP Data Credit.." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x14 0.--7. 1. "EINJ4_COUNT,Error injection count. Indicates the number of errors. This register is decremented as the errors are being inserted. - If the counter value is 0x01 and error is inserted ERROR_INJECTION4_ENABLE in EINJ_ENABLE_REG returns '0'. - If the.." line.long 0x18 "EINJ5_SP_TLP_REG,Error Injection Control 5 (Specific TLP Error). Controls the generation of specified TLPs. Correctable errors will occur which will be fixed by the PCIe protocol. - For Duplicate TLP. the controller initiates Data Link Retry by handling.." hexmask.long.tbyte 0x18 9.--31. 1. "RSVDP_9,Reserved for future use." newline bitfld.long 0x18 8. "EINJ5_SPECIFIED_TLP,Specified TLP. Selects the specified TLP to be inserted. - 0: Generates duplicate TLPs by handling ACK DLLP as NAK DLLP. - 1: Generates Nullified TLP (Original TLP will be stored in retry buffer). Note: This register field is sticky." "Generates duplicate TLPs by handling ACK DLLP as..,Generates Nullified TLP" newline hexmask.long.byte 0x18 0.--7. 1. "EINJ5_COUNT,Error injection count. Indicates the number of errors. This register is decremented as the errors are being inserted. - If the counter value is 0x01 and error is inserted ERROR_INJECTION5_ENABLE in EINJ_ENABLE_REG returns '0'. - If the.." line.long 0x1C "EINJ6_COMPARE_POINT_H0_REG,Error Injection Control 6 (Compare Point Header DWORD #0). Program this register for the 1st DWORD of TLP header/prefix. It is necessary to carefully consider the endianness when you program this register. Bits [31:0] =.." hexmask.long 0x1C 0.--31. 1. "EINJ6_COMPARE_POINT_H0,Packet Compare Point: 1st DWORD. Specifies which Tx TLP header DWORD#0 bits to compare with the corresponding bits in the Packet Compare Value registers (EINJ6_COMPARE_VALUE*). When all specified bits (in the Tx TLP header and.." line.long 0x20 "EINJ6_COMPARE_POINT_H1_REG,Error Injection Control 6 (Compare Point Header DWORD #1). Program this register for the 2nd DWORD of TLP header/prefix. It is necessary to carefully consider the endianness when you program this register. Bits [31:0] =.." hexmask.long 0x20 0.--31. 1. "EINJ6_COMPARE_POINT_H1,Packet Compare Point: 2nd DWORD. Specifies which Tx TLP header DWORD#1 bits to compare with the corresponding bits in the Packet Compare Value registers (EINJ6_COMPARE_VALUE*). When all specified bits (in the Tx TLP header and.." line.long 0x24 "EINJ6_COMPARE_POINT_H2_REG,Error Injection Control 6 (Compare Point Header DWORD #2). Program this register for the 3rd DWORD of TLP header/prefix. It is necessary to carefully consider the endianness when you program this register. Bits [31:0] =.." hexmask.long 0x24 0.--31. 1. "EINJ6_COMPARE_POINT_H2,Packet Compare Point: 3rd DWORD. Specifies which Tx TLP header DWORD#2 bits to compare with the corresponding bits in the Packet Compare Value registers (EINJ6_COMPARE_VALUE*). When all specified bits (in the Tx TLP header and.." line.long 0x28 "EINJ6_COMPARE_POINT_H3_REG,Error Injection Control 6 (Compare Point Header DWORD #3). Program this register for the 4th DWORD of TLP header/prefix. It is necessary to carefully consider the endianness when you program this register. Bits [31:0] =.." hexmask.long 0x28 0.--31. 1. "EINJ6_COMPARE_POINT_H3,Packet Compare Point: 4th DWORD. Specifies which Tx TLP header DWORD#3 bits to compare with the corresponding bits in the Packet Compare Value registers (EINJ6_COMPARE_VALUE*). When all specified bits (in the Tx TLP header and.." line.long 0x2C "EINJ6_COMPARE_VALUE_H0_REG,Error Injection Control 6 (Compare Value Header DWORD #0). Program this register for the 1st DWORD of TLP header/prefix. It is necessary to carefully consider the endianness when you program this register. Bits [31:0] =.." hexmask.long 0x2C 0.--31. 1. "EINJ6_COMPARE_VALUE_H0,Packet Compare Value: 1st DWORD. Specifies the value to compare against Tx the TLP header DWORD#0 bits specified in the Packet Compare Point registers (EINJ6_COMPARE_POINT*). Note: This register field is sticky." line.long 0x30 "EINJ6_COMPARE_VALUE_H1_REG,Error Injection Control 6 (Compare Value Header DWORD #1). Program this register for the 2nd DWORD of TLP header/prefix. It is necessary to carefully consider the endianness when you program this register. Bits [31:0] =.." hexmask.long 0x30 0.--31. 1. "EINJ6_COMPARE_VALUE_H1,Packet Compare Value: 2nd DWORD. Specifies the value to compare against Tx the TLP header DWORD#1 bits specified in the Packet Compare Point registers (EINJ6_COMPARE_POINT*). Note: This register field is sticky." line.long 0x34 "EINJ6_COMPARE_VALUE_H2_REG,Error Injection Control 6 (Compare Value Header DWORD #2). Program this register for the 3rd DWORD of TLP header/prefix. It is necessary to carefully consider the endianness when you program this register. Bits [31:0] =.." hexmask.long 0x34 0.--31. 1. "EINJ6_COMPARE_VALUE_H2,Packet Compare Value: 3rd DWORD. Specifies the value to compare against Tx the TLP header DWORD#2 bits specified in the Packet Compare Point registers (EINJ6_COMPARE_POINT*). Note: This register field is sticky." line.long 0x38 "EINJ6_COMPARE_VALUE_H3_REG,Error Injection Control 6 (Compare Value Header DWORD #3). Program this register for the 4th DWORD of TLP header/prefix. It is necessary to carefully consider the endianness when you program this register. Bits [31:0] =.." hexmask.long 0x38 0.--31. 1. "EINJ6_COMPARE_VALUE_H3,Packet Compare Value: 4th DWORD. Specifies the value to compare against Tx the TLP header DWORD#3 bits specified in the Packet Compare Point registers (EINJ6_COMPARE_POINT*). Note: This register field is sticky." line.long 0x3C "EINJ6_CHANGE_POINT_H0_REG,Error Injection Control 6 (Change Point Header DWORD #0). Program this register for the 1st DWORD of TLP header/prefix. It is necessary to carefully consider the endianness when you program this register. Bits [31:0] =.." hexmask.long 0x3C 0.--31. 1. "EINJ6_CHANGE_POINT_H0,Packet Change Point: 1st DWORD. Specifies which Tx TLP header DWORD#0 bits to replace with the corresponding bits in the Packet Change Value registers (EINJ6_CHANGE_VALUE*). Note: This register field is sticky." line.long 0x40 "EINJ6_CHANGE_POINT_H1_REG,Error Injection Control 6 (Change Point Header DWORD #1). Program this register for the 2nd DWORD of TLP header/prefix. It is necessary to carefully consider the endianness when you program this register. Bits [31:0] =.." hexmask.long 0x40 0.--31. 1. "EINJ6_CHANGE_POINT_H1,Packet Change Point: 2nd DWORD. Specifies which Tx TLP header DWORD#1 bits to replace with the corresponding bits in the Packet Change Value registers (EINJ6_CHANGE_VALUE*). Note: This register field is sticky." line.long 0x44 "EINJ6_CHANGE_POINT_H2_REG,Error Injection Control 6 (Change Point Header DWORD #2). Program this register for the 3rd DWORD of TLP header/prefix. It is necessary to carefully consider the endianness when you program this register. Bits [31:0] =.." hexmask.long 0x44 0.--31. 1. "EINJ6_CHANGE_POINT_H2,Packet Change Point: 3rd DWORD. Specifies which Tx TLP header DWORD#2 bits to replace with the corresponding bits in the Packet Change Value registers (EINJ6_CHANGE_VALUE*). Note: This register field is sticky." line.long 0x48 "EINJ6_CHANGE_POINT_H3_REG,Error Injection Control 6 (Change Point Header DWORD #3). Program this register for the 4th DWORD of TLP header/prefix. It is necessary to carefully consider the endianness when you program this register. Bits [31:0] =.." hexmask.long 0x48 0.--31. 1. "EINJ6_CHANGE_POINT_H3,Packet Change Point: 4th DWORD. Specifies which Tx TLP header DWORD#3 bits to replace with the corresponding bits in the Packet Change Value registers (EINJ6_CHANGE_VALUE*). Note: This register field is sticky." line.long 0x4C "EINJ6_CHANGE_VALUE_H0_REG,Error Injection Control 6 (Change Value Header DWORD #0). Program this register for the 1st DWORD of TLP header/prefix. It is necessary to carefully consider the endianness when you program this register. Bits [31:0] =.." hexmask.long 0x4C 0.--31. 1. "EINJ6_CHANGE_VALUE_H0,Packet Change Value: 1st DWORD. Specifies replacement values for the Tx TLP header DWORD#0 bits defined in the Packet Change Point registers (EINJ6_CHANGE_POINT*). Only applies when the EINJ6_INVERTED_CONTROL field in EINJ6_TLP_REG.." line.long 0x50 "EINJ6_CHANGE_VALUE_H1_REG,Error Injection Control 6 (Change Value Header DWORD #1). Program this register for the 2nd DWORD of TLP header/prefix. It is necessary to carefully consider the endianness when you program this register. Bits [31:0] =.." hexmask.long 0x50 0.--31. 1. "EINJ6_CHANGE_VALUE_H1,Packet Change Value: 2nd DWORD. Specifies replacement values for the Tx TLP header DWORD#1 bits defined in the Packet Change Point registers (EINJ6_CHANGE_POINT*). Only applies when the EINJ6_INVERTED_CONTROL field in EINJ6_TLP_REG.." line.long 0x54 "EINJ6_CHANGE_VALUE_H2_REG,Error Injection Control 6 (Change Value Header DWORD #2). Program this register for the 3rd DWORD of TLP header/prefix. It is necessary to carefully consider the endianness when you program this register. Bits [31:0] =.." hexmask.long 0x54 0.--31. 1. "EINJ6_CHANGE_VALUE_H2,Packet Change Value: 3rd DWORD. Specifies replacement values for the Tx TLP header DWORD#2 bits defined in the Packet Change Point registers (EINJ6_CHANGE_POINT*). Only applies when the EINJ6_INVERTED_CONTROL field in EINJ6_TLP_REG.." line.long 0x58 "EINJ6_CHANGE_VALUE_H3_REG,Error Injection Control 6 (Change Value Header DWORD #3). Program this register for the 4th DWORD of TLP header/prefix. It is necessary to carefully consider the endianness when you program this register. Bits [31:0] =.." hexmask.long 0x58 0.--31. 1. "EINJ6_CHANGE_VALUE_H3,Packet Change Value: 4th DWORD. Specifies replacement values for the Tx TLP header DWORD#3 bits defined in the Packet Change Point registers (EINJ6_CHANGE_POINT*). Only applies when the EINJ6_INVERTED_CONTROL field in EINJ6_TLP_REG.." line.long 0x5C "EINJ6_TLP_REG,Error Injection Control 6 (Packet Error). The Packet Compare Point registers (EINJ6_COMPARE_POINT*) specify which Tx TLP header bits to compare with the corresponding bits in the Packet Compare Value registers (EINJ6_COMPARE_VALUE*). When.." hexmask.long.tbyte 0x5C 12.--31. 1. "RSVDP_12,Reserved for future use." newline bitfld.long 0x5C 9.--11. "EINJ6_PACKET_TYPE,Packet type. Selects the TLP packets to inject errors into. - 0: TLP Header - 1: TLP Prefix 1st 4-DWORDs - 2: TLP Prefix 2nd -DWORDs - Else: Reserved Note: This register field is sticky." "TLP Header,TLP Prefix 1st 4-DWORDs,TLP Prefix 2nd -DWORDs,?,?,?,?,?" newline bitfld.long 0x5C 8. "EINJ6_INVERTED_CONTROL,Inverted Error Injection Control. - 0: EINJ6_CHANGE_VALUE_H[0/1/2/3] is used to replace bits specified by EINJ6_CHANGE_POINT_H[0/1/2/3]. - 1: EINJ6_CHANGE_VALUE_H[0/1/2/3] is ignored and inverts bits specified by.." "EINJ6_CHANGE_VALUE_H[0/1/2/3] is used to replace..,EINJ6_CHANGE_VALUE_H[0/1/2/3] is ignored and.." newline hexmask.long.byte 0x5C 0.--7. 1. "EINJ6_COUNT,Error Injection Count. Indicates the number of errors to insert. This counter is decremented while errors are been inserted. - If the counter value is 0x01 and error is inserted ERROR_INJECTION6_ENABLE in EINJ_ENABLE_REG returns '0'. - If.." group.long (0xA0+0x30C)++0x7 line.long 0x0 "SD_CONTROL1_REG,Silicon Debug Control 1. For more details. see the RAS DES section in the Core Operations chapter of the Databook." hexmask.long.byte 0x0 24.--31. 1. "RSVDP_24,Reserved for future use." newline bitfld.long 0x0 22.--23. "LOW_POWER_INTERVAL,Low Power Entry Interval Time. Interval Time that the controller starts monitoring RXELECIDLE signal after L0s/L1/L2 entry. You should set the value according to the latency from receiving EIOS to RXELECIDLE assertion at the PHY. -.." "0,1,2,3" newline bitfld.long 0x0 20.--21. "TX_EIOS_NUM,Number of Tx EIOS. This register sets the number of transmit EIOS for L0s/L1 entry and Disable/Loopback/Hot-reset exit. The controller selects the greater value between this register and the value defined by the PCI-SIG specification. 2.5GT/s.." "0,1,2,3" newline rbitfld.long 0x0 17.--19. "RSVDP_17,Reserved for future use." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 16. "FORCE_DETECT_LANE_EN,Force Detect Lane Enable. When this bit is set the controller ignores receiver detection from PHY during LTSSM Detect state and uses FORCE_DETECT_LANE. Note: This register field is sticky." "0,1" newline hexmask.long.word 0x0 0.--15. 1. "FORCE_DETECT_LANE,Force Detect Lane. When the FORCE_DETECT_LANE_EN field is set the controller ignores receiver detection from PHY during LTSSM Detect state and uses this value instead. - 0: Lane0 - 1: Lane1 - 2: Lane2 - .. - 15: Lane15 Note: This.." line.long 0x4 "SD_CONTROL2_REG,Silicon Debug Control 2. For more details. see the RAS DES section in the Core Operations chapter of the Databook." hexmask.long.word 0x4 17.--31. 1. "RSVDP_17,Reserved for future use." newline bitfld.long 0x4 16. "FRAMING_ERR_RECOVERY_DISABLE,Framing Error Recovery Disable. This bit disables a transition to Recovery state when a Framing Error is occurred. Note: This register field is sticky." "0,1" newline hexmask.long.byte 0x4 11.--15. 1. "RSVDP_11,Reserved for future use." newline bitfld.long 0x4 10. "DIRECT_LPBKSLV_TO_EXIT,Direct Loopback Slave To Exit. When this bit is set and the LTSSM is in Loopback Slave Active State the LTSSM transitions to Loopback Slave Exit state. Note: This register field is sticky." "0,1" newline bitfld.long 0x4 9. "DIRECT_POLCOMP_TO_DETECT,Direct Polling.Compliance to Detect. When this bit is set and the LTSSM is in Polling Compliance State the LTSSM transitions to Detect state. Note: This register field is sticky." "0,1" newline bitfld.long 0x4 8. "DIRECT_RECIDLE_TO_CONFIG,Direct Recovery.Idle to Configuration. When this bit is set and the LTSSM is in Recovery Idle State the LTSSM transitions to Configuration state. Note: This register field is sticky." "0,1" newline hexmask.long.byte 0x4 3.--7. 1. "RSVDP_3,Reserved for future use." newline bitfld.long 0x4 2. "NOACK_FORCE_LINKDOWN,Force LinkDown. When this bit is set and the controller detects REPLY_NUM rolling over 4 times the LTSSM transitions to Detect State. Note: This register field is sticky." "0,1" newline bitfld.long 0x4 1. "RECOVERY_REQUEST,Recovery Request. When this bit is set to '1' in L0 or L0s the LTSSM starts transitioning to Recovery State. This request does not cause a speed change or re-equalization." "0,1" newline bitfld.long 0x4 0. "HOLD_LTSSM,Hold and Release LTSSM. For as long as this register is '1' the controller stays in the current LTSSM. Note: This register field is sticky." "0,1" group.long (0xB0+0x30C)++0xB line.long 0x0 "SD_STATUS_L1LANE_REG,Silicon Debug Status(Layer1 Per-lane). This viewport register returns the data selected by the following field: - LANE_SELECT in SD_STATUS_L1LANE_REG For more details. see the RAS DES section in the Core Operations chapter of the.." hexmask.long.byte 0x0 24.--31. 1. "DESKEW_POINTER,Deskew Pointer. Indicates Deskew pointer of internal Deskew buffer of selected lane number(LANE_SELECT). Note: This register field is sticky." newline rbitfld.long 0x0 21.--23. "RSVDP_21,Reserved for future use." "0,1,2,3,4,5,6,7" newline rbitfld.long 0x0 20. "PIPE_TXELECIDLE,PIPE:TxElecIdle. Indicates PIPE TXELECIDLE signal of selected lane number(LANE_SELECT). Note: This register field is sticky." "0,1" newline rbitfld.long 0x0 19. "PIPE_RXELECIDLE,PIPE:RxElecIdle. Indicates PIPE RXELECIDLE signal of selected lane number(LANE_SELECT). Note: This register field is sticky." "0,1" newline rbitfld.long 0x0 18. "PIPE_RXVALID,PIPE:RxValid. Indicates PIPE RXVALID signal of selected lane number(LANE_SELECT). Note: This register field is sticky." "0,1" newline rbitfld.long 0x0 17. "PIPE_DETECT_LANE,PIPE:Detect Lane. Indicates whether PHY indicates receiver detection or not on selected lane number(LANE_SELECT). Note: This register field is sticky." "0,1" newline rbitfld.long 0x0 16. "PIPE_RXPOLARITY,PIPE:RxPolarity. Indicates PIPE RXPOLARITY signal of selected lane number(LANE_SELECT). Note: This register field is sticky." "0,1" newline hexmask.long.word 0x0 4.--15. 1. "RSVDP_4,Reserved for future use." newline hexmask.long.byte 0x0 0.--3. 1. "LANE_SELECT,Lane Select. Lane Select register for Silicon Debug Status Register of Layer1-PerLane. - 0x0: Lane0 - 0x1: Lane1 - 0x2: Lane2 - .. - 0xF: Lane15 Note: This register field is sticky." line.long 0x4 "SD_STATUS_L1LTSSM_REG,Silicon Debug Status(Layer1 LTSSM). For more details. see the RAS DES section in the Core Operations chapter of the Databook." hexmask.long.word 0x4 16.--31. 1. "LTSSM_VARIABLE,LTSSM Variable. Indicates internal LTSSM variables defined in the PCI Express Base Specification. C-PCIe Mode: - 0: directed_speed_change - 1: changed_speed_recovery - 2: successful_speed_negotiation - 3: upconfigure_capable; Set to '1' if.." newline rbitfld.long 0x4 15. "LANE_REVERSAL,Lane Reversal Operation. Receiver detected lane reversal. This field is only valid in the L0 LTSSM state. Note: This register field is sticky." "0,1" newline hexmask.long.byte 0x4 11.--14. 1. "RSVDP_11,Reserved for future use." newline rbitfld.long 0x4 8.--10. "PIPE_POWER_DOWN,PIPE:PowerDown. Indicates PIPE PowerDown signal. Note: This register field is sticky." "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 7. "FRAMING_ERR,Framing Error. Indicates Framing Error detection status." "0,1" newline hexmask.long.byte 0x4 0.--6. 1. "FRAMING_ERR_PTR,First Framing Error Pointer. Identifies the first Framing Error using the following encoding. The field contents are only valid value when FRAMING_ERR =1. Received Unexpected Framing Token - 01h: When non- STP/SDP/IDL Token was received.." line.long 0x8 "SD_STATUS_PM_REG,Silicon Debug Status(PM). For more details. see the RAS DES section in the Core Operations chapter of the Databook." hexmask.long.byte 0x8 24.--31. 1. "RSVDP_24,Reserved for future use." newline hexmask.long.byte 0x8 16.--23. 1. "LATCHED_NFTS,Latched N_FTS. Indicates the value of N_FTS in the received TS Ordered Sets from the Link Partner Note: This register field is sticky." newline rbitfld.long 0x8 13.--15. "L1SUB_STATE,L1Sub State. Indicates internal state machine of L1Sub state. - 0h: S_L1_U : idle state - 1h: S_L1_0 : wait for aux_clk_active - 2h: S_L1_0_WAIT4_ACK : wait for pclkack - 3h: S_L1_0_WAIT4_CLKREQ : wait for clkreq - 4h: S_L1_N_ENTRY : check.." "wait for aux_clk_active,?,?,?,?,?,?,?" newline bitfld.long 0x8 12. "PME_RESEND_FLAG,PME Re-send flag. When the DUT sends a PM_PME message TLP the DUT sets PME_Status bit. If host software does not clear PME_Status bit for 100ms(+50%/-5%) the DUT resends the PM_PME Message. This bit indicates that a PM_PME was resent." "0,1" newline hexmask.long.byte 0x8 8.--11. 1. "INTERNAL_PM_SSTATE,Internal PM State(Slave). Indicates internal state machine of Power Management Slave controller. - 0h: S_IDLE - 1h: S_RESPOND_NAK - 2h: S_BLOCK_TLP - 3h: S_WAIT_LAST_TLP_ACK - 4h: S_WAIT_EIDLE - 5h: S_LINK_ENTR_L1 - 6h: S_L1 - 7h:.." newline rbitfld.long 0x8 5.--7. "RSVDP_5,Reserved for future use." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x8 0.--4. 1. "INTERNAL_PM_MSTATE,Internal PM State(Master). Indicates internal state machine of Power Management Master controller. - 00h: IDLE - 01h: L0 - 02h: L0S - 03h: ENTER_L0S - 04h: L0S_EXIT - 05h: WAIT_PMCSR_CPL_SENT - 08h: L1 - 09h: L1_BLOCK_TLP - 0Ah:.." rgroup.long (0xBC+0x30C)++0x3 line.long 0x0 "SD_STATUS_L2_REG,Silicon Debug Status(Layer2). For more details. see the RAS DES section in the Core Operations chapter of the Databook." hexmask.long.byte 0x0 28.--31. 1. "RSVDP_28,Reserved for future use." newline bitfld.long 0x0 27. "FC_INIT2,FC_INIT2. Indicates the controller is in FC_INIT2(VC0) state. Note: This register field is sticky." "0,1" newline bitfld.long 0x0 26. "FC_INIT1,FC_INIT1. Indicates the controller is in FC_INIT1(VC0) state. Note: This register field is sticky." "0,1" newline bitfld.long 0x0 24.--25. "DLCMSM,DLCMSM. Indicates the current DLCMSM. - 00b: DL_INACTIVE - 01b: DL_FC_INIT - 11b: DL_ACTIVE Note: This register field is sticky." "0,1,2,3" newline hexmask.long.word 0x0 12.--23. 1. "RX_ACK_SEQ_NO,Tx Ack Sequence Number. Indicates ACKD_SEQ which is updated by receiving ACK/NAK DLLP. Note: This register field is sticky." newline hexmask.long.word 0x0 0.--11. 1. "TX_TLP_SEQ_NO,Tx Tlp Sequence Number. Indicates next transmit sequence number for transmit TLP. Note: This register field is sticky." group.long (0xC0+0x30C)++0x7 line.long 0x0 "SD_STATUS_L3FC_REG,Silicon Debug Status(Layer3 FC). The CREDIT_DATA[0/1] fields in this viewport register return the data for the VC and TLP Type selected by the following fields: - CREDIT_SEL_VC - CREDIT_SEL_CREDIT_TYPE - CREDIT_SEL_TLP_TYPE -.." hexmask.long.word 0x0 20.--31. 1. "CREDIT_DATA1,Credit Data1. Current FC credit data selected by the CREDIT_SEL_VC CREDIT_SEL_CREDIT_TYPE CREDIT_SEL_TLP_TYPE and CREDIT_SEL_HD viewport-select fields. - Rx: Credit Allocated Value - Tx: Credit Limit Value. This value is valid when.." newline hexmask.long.word 0x0 8.--19. 1. "CREDIT_DATA0,Credit Data0. Current FC credit data selected by the CREDIT_SEL_VC CREDIT_SEL_CREDIT_TYPE CREDIT_SEL_TLP_TYPE and CREDIT_SEL_HD viewport-select fields. - Rx: Credit Received Value - Tx: Credit Consumed Value Note: This register field is.." newline rbitfld.long 0x0 7. "RSVDP_7,Reserved for future use." "0,1" newline bitfld.long 0x0 6. "CREDIT_SEL_HD,Credit Select(HeaderData). This field in conjunction with the CREDIT_SEL_VC CREDIT_SEL_CREDIT_TYPE and CREDIT_SEL_TLP_TYPE viewport-select fields determines that data that is returned by the CREDIT_DATA0 and CREDIT_DATA1 data fields. -.." "Header Credit,Data Credit" newline bitfld.long 0x0 4.--5. "CREDIT_SEL_TLP_TYPE,Credit Select(TLP Type). This field in conjunction with the CREDIT_SEL_VC CREDIT_SEL_CREDIT_TYPE and CREDIT_SEL_HD viewport-select fields determines that data that is returned by the CREDIT_DATA0 and CREDIT_DATA1 data fields. - 0x0:.." "Posted,Non-Posted,Completion,?" newline bitfld.long 0x0 3. "CREDIT_SEL_CREDIT_TYPE,Credit Select(Credit Type). This field in conjunction with the CREDIT_SEL_VC CREDIT_SEL_TLP_TYPE and CREDIT_SEL_HD viewport-select fields determines that data that is returned by the CREDIT_DATA0 and CREDIT_DATA1 data fields. -.." "Rx,Tx" newline bitfld.long 0x0 0.--2. "CREDIT_SEL_VC,Credit Select(VC). This field in conjunction with the CREDIT_SEL_CREDIT_TYPE CREDIT_SEL_TLP_TYPE and CREDIT_SEL_HD viewport-select fields determines that data that is returned by the CREDIT_DATA0 and CREDIT_DATA1 data fields. - 0x0: VC0 -.." "VC0,VC1,VC2,?,?,?,?,VC7" line.long 0x4 "SD_STATUS_L3_REG,Silicon Debug Status(Layer3). For more details. see the RAS DES section in the Core Operations chapter of the Databook." hexmask.long.tbyte 0x4 8.--31. 1. "RSVDP_8,Reserved for future use." newline bitfld.long 0x4 7. "MFTLP_STATUS,Malformed TLP Status. Indicates malformed TLP has occurred." "0,1" newline hexmask.long.byte 0x4 0.--6. 1. "MFTLP_POINTER,First Malformed TLP Error Pointer. Indicates the element of the received first malformed TLP. This pointer is validated by MFTLP_STATUS. - 01h: AtomicOp address alignment - 02h: AtomicOp operand - 03h: AtomicOp byte enable - 04h: TLP length.." group.long (0xD0+0x30C)++0xB line.long 0x0 "SD_EQ_CONTROL1_REG,Silicon Debug EQ Control 1. This is a viewport control register. Setting the EQ_RATE_SEL and EQ_LANE_SEL fields in this register determine the per-lane Silicon Debug EQ Status data returned by the SD_EQ_STATUS[1/2/3] viewport.." hexmask.long.byte 0x0 24.--31. 1. "FOM_TARGET,FOM Target. Indicates figure of merit target criteria value of EQ Master(DSP in EQ Phase3/USP in EQ Phase2). This field is only valid when GEN3_EQ_FB_MODE is 0001b(Figure Of Merit). Note: This register field is sticky." newline bitfld.long 0x0 23. "FOM_TARGET_ENABLE,FOM Target Enable. Enables the FOM_TARGET fields. Note: This register field is sticky." "0,1" newline hexmask.long.byte 0x0 18.--22. 1. "RSVDP_18,Reserved for future use." newline bitfld.long 0x0 16.--17. "EVAL_INTERVAL_TIME,Eval Interval Time. Indicates interval time of RxEqEval assertion. - 00: 500ns - 01: 1us - 10: 2us - 11: 4us This field is used for EQ Master(DSP in EQ Phase3/USP in EQ Phase2). Note: This register field is sticky." "0,1,2,3" newline hexmask.long.byte 0x0 10.--15. 1. "RSVDP_10,Reserved for future use." newline bitfld.long 0x0 8.--9. "EXT_EQ_TIMEOUT,Extends EQ Phase2/3 Timeout. This field is used when the Ltssm is in Recovery.EQ2/3. When this field is set the value of EQ2/3 timeout is extended. EQ Master(DSP in EQ Phase3/USP in EQ Phase2). - 00: 24ms (default) - 01: 48ms (x2) - 10:.." "0,1,2,3" newline rbitfld.long 0x0 6.--7. "RSVDP_6,Reserved for future use." "0,1,2,3" newline bitfld.long 0x0 4.--5. "EQ_RATE_SEL,EQ Status Rate Select. Setting this field in conjunction with the EQ_LANE_SEL field determines the per-lane Silicon Debug EQ Status data returned by the SD_EQ_CONTROL[2/3] and SD_EQ_STATUS[1/2/3] viewport registers. - 0x0: 8.0GT/s Speed.." "0,1,2,3" newline hexmask.long.byte 0x0 0.--3. 1. "EQ_LANE_SEL,EQ Status Lane Select. Setting this field in conjunction with the EQ_RATE_SEL field determines the per-lane Silicon Debug EQ Status data returned by the SD_EQ_CONTROL[2/3] and SD_EQ_STATUS[1/2/3] viewport registers. - 0x0: Lane0 - 0x1: Lane1.." line.long 0x4 "SD_EQ_CONTROL2_REG,Silicon Debug EQ Control 2. This viewport register returns the value for the rate and lane selected by the EQ_RATE_SEL and EQ_LANE_SEL fields in the SD_EQ_CONTROL1_REG register. For more details. see the RAS DES section in the Core.." rbitfld.long 0x4 31. "RSVDP_31,Reserved for future use." "0,1" newline bitfld.long 0x4 30. "FORCE_LOCAL_TX_PRESET_ENABLE,Force Local Transmitter Preset Enable. Enables the FORCE_LOCAL_TX_PRESET field. If select rate in the EQ_RATE_SEL field is 32.0GT/s Speed this feature is not available. Note: This register field is sticky." "0,1" newline bitfld.long 0x4 29. "FORCE_LOCAL_RX_HINT_ENABLE,Force Local Receiver Preset Hint Enable. Enables the FORCE_LOCAL_RX_HINT field. If select rate in the EQ_RATE_SEL field is other than 8.0GT/s Speed this feature is not available. Note: This register field is sticky." "0,1" newline bitfld.long 0x4 28. "FORCE_LOCAL_TX_COEF_ENABLE,Force Local Transmitter Coefficient Enable. Enables the following fields: - FORCE_LOCAL_TX_PRE_CURSOR - FORCE_LOCAL_TX_CURSOR - FORCE_LOCAL_TX_POST_CURSOR Note: This register field is sticky." "0,1" newline hexmask.long.byte 0x4 24.--27. 1. "FORCE_LOCAL_TX_PRESET,Force Local Transmitter Preset. Indicates initial preset value of USP in EQ Slave(EQ Phase2) instead of receiving EQ TS2. If select rate in the EQ_RATE_SEL field is 32.0GT/s Speed this feature is not available. Note: This register.." newline rbitfld.long 0x4 21.--23. "RSVDP_21,Reserved for future use." "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 18.--20. "FORCE_LOCAL_RX_HINT,Force Local Receiver Preset Hint. Indicates the RxPresetHint value of EQ Slave(DSP in EQ Phase2/USP in EQ Phase3) instead of received or set value. If select rate in the EQ_RATE_SEL field is other than 8.0GT/s Speed this feature is.." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x4 12.--17. 1. "FORCE_LOCAL_TX_POST_CURSOR,Force Local Transmitter Post-Cursor. Indicates the coefficient value of EQ Slave(DSP in EQ Phase2/USP in EQ Phase3) instead of the value instructed from link partner. Note: This register field is sticky." newline hexmask.long.byte 0x4 6.--11. 1. "FORCE_LOCAL_TX_CURSOR,Force Local Transmitter Cursor. Indicates the coefficient value of EQ Slave(DSP in EQ Phase2/USP in EQ Phase3) instead of the value instructed from link partner. Note: This register field is sticky." newline hexmask.long.byte 0x4 0.--5. 1. "FORCE_LOCAL_TX_PRE_CURSOR,Force Local Transmitter Pre-cursor. Indicates the coefficient value of EQ Slave(DSP in EQ Phase2/USP in EQ Phase3) instead of the value instructed from link partner. Note: This register field is sticky." line.long 0x8 "SD_EQ_CONTROL3_REG,Silicon Debug EQ Control 3. This viewport register returns the value for the rate and lane selected by the EQ_RATE_SEL and EQ_LANE_SEL fields in the SD_EQ_CONTROL1_REG register. For more details. see the RAS DES section in the Core.." rbitfld.long 0x8 29.--31. "RSVDP_29,Reserved for future use." "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 28. "FORCE_REMOTE_TX_COEF_ENABLE,Force Remote Transmitter Coefficient Enable. Enables the following fields: - FORCE_REMOTE_TX_PRE_CURSOR - FORCE_REMOTE_TX_CURSOR - FORCE_REMOTE_TX_POST_CURSOR This function can only be used when GEN3_EQ_FB_MODE =.." "0,1" newline hexmask.long.word 0x8 18.--27. 1. "RSVDP_18,Reserved for future use." newline hexmask.long.byte 0x8 12.--17. 1. "FORCE_REMOTE_TX_POST_CURSOR,Force Remote Transmitter Post-Cursor. Indicates the coefficient value of EQ Master(DSP in EQ Phase3/USP in EQ Phase2) instead of the value instructed from local phy in dirchange mode. Note: This register field is sticky." newline hexmask.long.byte 0x8 6.--11. 1. "FORCE_REMOTE_TX_CURSOR,Force Remote Transmitter Cursor. Indicates the coefficient value of EQ Master(DSP in EQ Phase3/USP in EQ Phase2) instead of the value instructed from local phy in dirchange mode. Note: This register field is sticky." newline hexmask.long.byte 0x8 0.--5. 1. "FORCE_REMOTE_TX_PRE_CURSOR,Force Remote Transmitter Pre-Cursor. Indicates the coefficient value of EQ Master(DSP in EQ Phase3/USP in EQ Phase2) instead of the value instructed from local phy in dirchange mode. Note: This register field is sticky." rgroup.long (0xE0+0x30C)++0xB line.long 0x0 "SD_EQ_STATUS1_REG,Silicon Debug EQ Status 1. This viewport register returns the first of three words of Silicon Debug EQ Status data for the rate and lane selected by the EQ_RATE_SEL and EQ_LANE_SEL fields in the SD_EQ_CONTROL1_REG register. The.." hexmask.long.tbyte 0x0 8.--31. 1. "RSVDP_8,Reserved for future use." newline bitfld.long 0x0 7. "EQ_REJECT_EVENT,EQ Reject Event. Indicates that the controller receives two consecutive TS1 OS w/Reject=1b during EQ Master phase(DSP in EQ Phase3/USP in EQ Phase2). This bit is automatically cleared when the controller starts EQ Master phase again." "0,1" newline bitfld.long 0x0 6. "EQ_RULEC_VIOLATION,EQ Rule C Violation. Indicates that coefficients rule C violation is detected in the values provided by PHY using direction change method during EQ Master phase(DSP in EQ Phase3/USP in EQ Phase2). The coefficients rule C correspond to.." "0,1" newline bitfld.long 0x0 5. "EQ_RULEB_VIOLATION,EQ Rule B Violation. Indicates that coefficients rule B violation is detected in the values provided by PHY using direction change method during EQ Master phase(DSP in EQ Phase3/USP in EQ Phase2). The coefficients rules B correspond to.." "0,1" newline bitfld.long 0x0 4. "EQ_RULEA_VIOLATION,EQ Rule A Violation. Indicates that coefficients rule A violation is detected in the values provided by PHY using direction change method during EQ Master phase(DSP in EQ Phase3/USP in EQ Phase2). The coefficients rules A correspond to.." "0,1" newline bitfld.long 0x0 3. "RSVDP_3,Reserved for future use." "0,1" newline bitfld.long 0x0 1.--2. "EQ_CONVERGENCE_INFO,EQ Convergence Info. Indicates equalization convergence information. - 0x0: Equalization is not attempted - 0x1: Equalization finished successfully - 0x2: Equalization finished unsuccessfully - 0x3: Reserved This bit is automatically.." "Equalization is not attempted,Equalization finished successfully,Equalization finished unsuccessfully,Reserved" newline bitfld.long 0x0 0. "EQ_SEQUENCE,EQ Sequence. Indicates that the controller is starting the equalization sequence. Note: This register field is sticky." "0,1" line.long 0x4 "SD_EQ_STATUS2_REG,Silicon Debug EQ Status 2. This viewport register returns the second of three words of Silicon Debug EQ Status data for the rate and lane selected by the EQ_RATE_SEL and EQ_LANE_SEL fields in the SD_EQ_CONTROL1_REG register. Each field.." hexmask.long.byte 0x4 24.--31. 1. "EQ_LOCAL_FOM_VALUE,EQ Local Figure of Merit. Indicates Local maximum Figure of Merit value. Note: This register field is sticky." newline bitfld.long 0x4 21.--23. "RSVDP_21,Reserved for future use." "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 18.--20. "EQ_LOCAL_RX_HINT,EQ Local Receiver Preset Hint. Indicates Local Receiver Preset Hint value. If select rate in the EQ_RATE_SEL field is other than 8.0GT/s Speed this feature is not available. Note: This register field is sticky." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x4 12.--17. 1. "EQ_LOCAL_POST_CURSOR,EQ Local Post-Cursor. Indicates Local post cursor coefficient value. Note: This register field is sticky." newline hexmask.long.byte 0x4 6.--11. 1. "EQ_LOCAL_CURSOR,EQ Local Cursor. Indicates Local cursor coefficient value. Note: This register field is sticky." newline hexmask.long.byte 0x4 0.--5. 1. "EQ_LOCAL_PRE_CURSOR,EQ Local Pre-Cursor. Indicates Local pre cursor coefficient value. Note: This register field is sticky." line.long 0x8 "SD_EQ_STATUS3_REG,Silicon Debug EQ Status 3. This viewport register returns the third of three words of Silicon Debug EQ Status data for the rate and lane selected by the EQ_RATE_SEL and EQ_LANE_SEL fields in the SD_EQ_CONTROL1_REG register. Each field.." bitfld.long 0x8 30.--31. "RSVDP_30,Reserved for future use." "0,1,2,3" newline hexmask.long.byte 0x8 24.--29. 1. "EQ_REMOTE_FS,EQ Remote FS. Indicates Remote FS value. Note: This register field is sticky." newline hexmask.long.byte 0x8 18.--23. 1. "EQ_REMOTE_LF,EQ Remote LF. Indicates Remote LF value. Note: This register field is sticky." newline hexmask.long.byte 0x8 12.--17. 1. "EQ_REMOTE_POST_CURSOR,EQ Remote Post-Cursor. Indicates Remote post cursor coefficient value. Note: This register field is sticky." newline hexmask.long.byte 0x8 6.--11. 1. "EQ_REMOTE_CURSOR,EQ Remote Cursor. Indicates Remote cursor coefficient value. Note: This register field is sticky." newline hexmask.long.byte 0x8 0.--5. 1. "EQ_REMOTE_PRE_CURSOR,EQ Remote Pre-Cursor. Indicates Remote pre cursor coefficient value. Note: This register field is sticky." tree.end tree "PF0_SN_CAP (Device Serial Number Capability Structure)" group.long (0x0+0x170)++0xB line.long 0x0 "SN_BASE,Device Serial Number Extended Capability Header. For a description of this standard PCIe register. see the PCI Express Base Specification." hexmask.long.word 0x0 20.--31. 1. "SN_NEXT_OFFSET,Next Capability Offset. For a description of this standard PCIe register field see the PCI Express Base Specification. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then.." hexmask.long.byte 0x0 16.--19. 1. "SN_CAP_VERSION,Capability Version. For a description of this standard PCIe register field see the PCI Express Base Specification. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky).." hexmask.long.word 0x0 0.--15. 1. "SN_PCIE_EXTENDED_CAP_ID,Serial Number Extended Capability ID. For a description of this standard PCIe register field see the PCI Express Base Specification. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if.." line.long 0x4 "SER_NUM_REG_DW_1,Serial Number 1 Register. For a description of this standard PCIe register. see the PCI Express Base Specification." hexmask.long 0x4 0.--31. 1. "SN_SER_NUM_REG_1_DW,IEEE 64 bit Device Serial Number (DW 1). For a description of this standard PCIe register field see the PCI Express Base Specification. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if.." line.long 0x8 "SER_NUM_REG_DW_2,Serial Number 2 Register. For a description of this standard PCIe register. see the PCI Express Base Specification." hexmask.long 0x8 0.--31. 1. "SN_SER_NUM_REG_2_DW,IEEE 64 bit Device Serial Number (DW 2). For a description of this standard PCIe register field see the PCI Express Base Specification. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if.." tree.end tree "PF0_VSECRAS_CAP (PF RAS Datapath Protection Capability Structure (VSEC))" group.long (0x0+0x480)++0x3 line.long 0x0 "RASDP_EXT_CAP_HDR_OFF,PCIe Extended capability ID. Capability version and Next capability offset. For a description of this standard PCIe register. see the PCI Express Specification." hexmask.long.word 0x0 20.--31. 1. "NEXT_OFFSET,Next Capability Offset. For a description of this standard PCIe register see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else.." newline hexmask.long.byte 0x0 16.--19. 1. "CAP,Capability Version. For a description of this standard PCIe register see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note:.." newline hexmask.long.word 0x0 0.--15. 1. "ID,PCI Express Extended Capability ID. For a description of this standard PCIe register see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else.." rgroup.long (0x4+0x480)++0x3 line.long 0x0 "RASDP_VENDOR_SPECIFIC_HDR_OFF,Vendor Specific Header. For a description of this standard PCIe register. see the PCI Express Specification." hexmask.long.word 0x0 20.--31. 1. "VSEC_LENGTH,VSEC Length. For a description of this standard PCIe register see the PCI Express Specification. Note: This register field is sticky." newline hexmask.long.byte 0x0 16.--19. 1. "VSEC_REV,VSEC Rev. For a description of this standard PCIe register see the PCI Express Specification. Note: This register field is sticky." newline hexmask.long.word 0x0 0.--15. 1. "VSEC_ID,VSEC ID. For a description of this standard PCIe register see the PCI Express Specification. Note: This register field is sticky." group.long (0x8+0x480)++0x7 line.long 0x0 "RASDP_ERROR_PROT_CTRL_OFF,ECC error correction control. Allows you to disable ECC error correction for RAMs and datapath. When the AXI Bridge Module is implemented and the master / slave clocks are asynchronous to the PCIe native controller clock.." hexmask.long.byte 0x0 24.--31. 1. "RSVDP_24,Reserved for future use." newline bitfld.long 0x0 23. "ERROR_PROT_DISABLE_CXS_RX,Error correction disable for CXS Tx path (PCIe Rx path). Note: This register field is sticky." "0,1" newline bitfld.long 0x0 22. "ERROR_PROT_DISABLE_ADM_RX,Error correction disable for ADM Rx path. Note: This register field is sticky." "0,1" newline bitfld.long 0x0 21. "ERROR_PROT_DISABLE_LAYER3_RX,Error correction disable for layer 3 Rx path. Note: This register field is sticky." "0,1" newline bitfld.long 0x0 20. "ERROR_PROT_DISABLE_LAYER2_RX,Error correction disable for layer 2 Rx path. Note: This register field is sticky." "0,1" newline bitfld.long 0x0 19. "ERROR_PROT_DISABLE_DMA_READ,Error correction disable for DMA read engine. Note: This register field is sticky." "0,1" newline bitfld.long 0x0 18. "ERROR_PROT_DISABLE_AXI_BRIDGE_INBOUND_REQUEST,Error correction disable for AXI bridge inbound request path. Note: This register field is sticky." "0,1" newline bitfld.long 0x0 17. "ERROR_PROT_DISABLE_AXI_BRIDGE_INBOUND_COMPLETION,Error correction disable for AXI bridge inbound completion composer. Does not disable the error detection reporting for 1-bit and 2-bit ECC errors. Note: This register field is sticky." "?,bit and 2-bit ECC errors" newline bitfld.long 0x0 16. "ERROR_PROT_DISABLE_RX,Global error correction disable for all Rx layers. Note: This register field is sticky." "0,1" newline hexmask.long.byte 0x0 9.--15. 1. "RSVDP_9,Reserved for future use." newline bitfld.long 0x0 8. "ERROR_PROT_DISABLE_DTIM_TX,Error correction disable for DTIM Tx path. Note: This register field is sticky." "0,1" newline bitfld.long 0x0 7. "ERROR_PROT_DISABLE_CXS_TX,Error correction disable for CXS Rx path (PCIe Tx path). Note: This register field is sticky." "0,1" newline bitfld.long 0x0 6. "ERROR_PROT_DISABLE_ADM_TX,Error correction disable for Adm Tx path. Note: This register field is sticky." "0,1" newline bitfld.long 0x0 5. "ERROR_PROT_DISABLE_LAYER3_TX,Error correction disable for layer 3 Tx path. Note: This register field is sticky." "0,1" newline bitfld.long 0x0 4. "ERROR_PROT_DISABLE_LAYER2_TX,Error correction disable for layer 2 Tx path. Note: This register field is sticky." "0,1" newline bitfld.long 0x0 3. "ERROR_PROT_DISABLE_DMA_WRITE,Error correction disable for DMA write engine. Note: This register field is sticky." "0,1" newline bitfld.long 0x0 2. "ERROR_PROT_DISABLE_AXI_BRIDGE_OUTBOUND,Error correction disable for AXI bridge outbound request path. Note: This register field is sticky." "0,1" newline bitfld.long 0x0 1. "ERROR_PROT_DISABLE_AXI_BRIDGE_MASTER,Error correction disable for AXI bridge master completion buffer. Note: This register field is sticky." "0,1" newline bitfld.long 0x0 0. "ERROR_PROT_DISABLE_TX,Global error correction disable for all Tx layers. Does not disable the error detection reporting for 1-bit and 2-bit ECC errors. Note: This register field is sticky." "?,bit and 2-bit ECC errors" line.long 0x4 "RASDP_CORR_COUNTER_CTRL_OFF,Corrected error (1-bit ECC) counter selection and control. This is a viewport control register. Setting the CORR_COUNTER_SELECTION_REGION and CORR_COUNTER_SELECTION fields in this register determine the counter data returned.." hexmask.long.byte 0x4 24.--31. 1. "CORR_COUNTER_SELECTION,Counter selection. This field selects the counter ID (within the region defined by CORR_COUNTER_SELECTION_REGION) whose contents can be read from the RASDP_CORR_COUNT_REPORT_OFF register. You can cycle this field value from 0 to.." newline hexmask.long.byte 0x4 20.--23. 1. "CORR_COUNTER_SELECTION_REGION,Select correctable counter region: - 0x0: Region select for Adm Rx path - 0x1: Region select for layer 3 Rx path - 0x2: Region select for layer 2 Rx path - 0x3: Region select for DMA inbound path - 0x4: Region select for AXI.." newline hexmask.long.word 0x4 5.--19. 1. "RSVDP_5,Reserved for future use." newline bitfld.long 0x4 4. "CORR_EN_COUNTERS,Enable correctable errors counters. - 1: counters increment when the controller detects a correctable error - 0: counters are frozen The counters are enabled by default." "counters are frozen,counters increment when the controller detects a.." newline rbitfld.long 0x4 1.--3. "RSVDP_1,Reserved for future use." "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 0. "CORR_CLEAR_COUNTERS,Clear all correctable error counters." "0,1" rgroup.long (0x10+0x480)++0x3 line.long 0x0 "RASDP_CORR_COUNT_REPORT_OFF,Corrected error (1-bit ECC) counter data. This viewport register returns the counter data selected by the CORR_COUNTER_SELECTION_REGION and CORR_COUNTER_SELECTION fields in the RASDP_CORR_COUNTER_CTRL_OFF register." hexmask.long.byte 0x0 24.--31. 1. "CORR_COUNTER_SELECTED,Counter selection. Returns the value set in the CORR_COUNTER_SELECTION field of the RASDP_CORR_COUNTER_CTRL_OFF register." newline hexmask.long.byte 0x0 20.--23. 1. "CORR_COUNTER_SELECTED_REGION,Selected correctable counter region: - 0x0: Region select for Adm Rx path - 0x1: Region select for layer 3 Rx path - 0x2: Region select for layer 2 Rx path - 0x3: Region select for DMA inbound path - 0x4: Region select for.." newline hexmask.long.word 0x0 8.--19. 1. "RSVDP_8,Reserved for future use." newline hexmask.long.byte 0x0 0.--7. 1. "CORR_COUNTER,Current corrected error count for the selected counter." group.long (0x14+0x480)++0x3 line.long 0x0 "RASDP_UNCORR_COUNTER_CTRL_OFF,Uncorrected error (2-bit ECC and parity) counter selection and control. This is a viewport control register. Setting the UNCORR_COUNTER_SELECTION_REGION and UNCORR_COUNTER_SELECTION fields in this register determine the.." hexmask.long.byte 0x0 24.--31. 1. "UNCORR_COUNTER_SELECTION,Counter selection. This field selects the counter ID (within the region defined by UNCORR_COUNTER_SELECTION_REGION) whose contents can be read from the RASDP_UNCORR_COUNT_REPORT_OFF register. You can cycle this field value from 0.." newline hexmask.long.byte 0x0 20.--23. 1. "UNCORR_COUNTER_SELECTION_REGION,Select uncorrectable counter region: - 0x0: Region select for Adm Rx path - 0x1: Region select for layer 3 Rx path - 0x2: Region select for layer 2 Rx path - 0x3: Region select for DMA inbound path - 0x4: Region select for.." newline hexmask.long.word 0x0 5.--19. 1. "RSVDP_5,Reserved for future use." newline bitfld.long 0x0 4. "UNCORR_EN_COUNTERS,Enable uncorrectable errors counters. - 1: enables the counters to increment on detected correctable errors - 0: counters are frozen The counters are enabled by default." "counters are frozen,enables the counters to increment on detected.." newline rbitfld.long 0x0 1.--3. "RSVDP_1,Reserved for future use." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 0. "UNCORR_CLEAR_COUNTERS,Clear uncorrectable errors counters. When asserted causes all counters tracking the uncorrectable errors to be cleared." "0,1" rgroup.long (0x18+0x480)++0x3 line.long 0x0 "RASDP_UNCORR_COUNT_REPORT_OFF,Uncorrected error (2-bit ECC and parity) counter data. This viewport register returns the counter data selected by the UNCORR_COUNTER_SELECTION_REGION and UNCORR_COUNTER_SELECTION fields in the RASDP_UNCORR_COUNTER_CTRL_OFF.." hexmask.long.byte 0x0 24.--31. 1. "UNCORR_COUNTER_SELECTED,Counter selection. Returns the value set in the UNCORR_COUNTER_SELECTION field of the RASDP_UNCORR_COUNTER_CTRL_OFF register." newline hexmask.long.byte 0x0 20.--23. 1. "UNCORR_COUNTER_SELECTED_REGION,Selected uncorrectable counter region: - 0x0: Region select for Adm Rx path - 0x1: Region select for layer 3 Rx path - 0x2: Region select for layer 2 Rx path - 0x3: Region select for DMA inbound path - 0x4: Region select.." newline hexmask.long.word 0x0 8.--19. 1. "RSVDP_8,Reserved for future use." newline hexmask.long.byte 0x0 0.--7. 1. "UNCORR_COUNTER,Current uncorrected error count for the selected counter" group.long (0x1C+0x480)++0x3 line.long 0x0 "RASDP_ERROR_INJ_CTRL_OFF,Error injection control for the following features: - 1-bit or 2-bit injection - Continuous or fixed-number (n) injection modes - Global enable/disable - Selectable location where injection occurs" hexmask.long.byte 0x0 24.--31. 1. "RSVDP_24,Reserved for future use." newline hexmask.long.byte 0x0 16.--23. 1. "ERROR_INJ_LOC,Error injection location. Selects where error injection takes place. You can cycle this field value from 0 to 255 to access all locations according to the detailed report of check points at.." newline hexmask.long.byte 0x0 8.--15. 1. "ERROR_INJ_COUNT,Error injection count. - 0: errors are inserted in every TLP until you clear ERROR_INJ_EN. - 1: one errors injected - 2: two errors injected - n: amount of errors injected" newline rbitfld.long 0x0 6.--7. "RSVDP_6,Reserved for future use." "0,1,2,3" newline bitfld.long 0x0 4.--5. "ERROR_INJ_TYPE,Error injection type: - 0: none - 1: 1-bit - 2: 2-bit" "none,bit,bit,?" newline rbitfld.long 0x0 1.--3. "RSVDP_1,Reserved for future use." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 0. "ERROR_INJ_EN,Error injection global enable. When set enables the error insertion logic." "0,1" rgroup.long (0x20+0x480)++0x7 line.long 0x0 "RASDP_CORR_ERROR_LOCATION_OFF,Corrected errors locations. For more details. see the RAS Data Protection (DP) section in the Core Operations chapter of the Databook." hexmask.long.byte 0x0 24.--31. 1. "LOC_LAST_CORR_ERROR,Location/ID of the last corrected error within the region defined by REG_LAST_CORR_ERROR. You can cycle this field value from 0 to 255 to access all counters according to the detailed report of check points at.." newline hexmask.long.byte 0x0 20.--23. 1. "REG_LAST_CORR_ERROR,Region of the last corrected error: - 0x0: Region select for Adm Rx path - 0x1: Region select for layer 3 Rx path - 0x2: Region select for layer 2 Rx path - 0x3: Region select for DMA inbound path - 0x4: Region select for AXI bridge.." newline hexmask.long.byte 0x0 16.--19. 1. "RSVDP_16,Reserved for future use." newline hexmask.long.byte 0x0 8.--15. 1. "LOC_FIRST_CORR_ERROR,Location/ID of the first corrected error within the region defined by REG_FIRST_CORR_ERROR. You can cycle this field value from 0 to 255 to access all counters according to the detailed report of check points at.." newline hexmask.long.byte 0x0 4.--7. 1. "REG_FIRST_CORR_ERROR,Region of the first corrected error: - 0x0: Region select for Adm Rx path - 0x1: Region select for layer 3 Rx path - 0x2: Region select for layer 2 Rx path - 0x3: Region select for DMA inbound path - 0x4: Region select for AXI bridge.." newline hexmask.long.byte 0x0 0.--3. 1. "RSVDP_0,Reserved for future use." line.long 0x4 "RASDP_UNCORR_ERROR_LOCATION_OFF,Uncorrected errors locations. For more details. see the RAS Data Protection (DP) section in the Core Operations chapter of the Databook." hexmask.long.byte 0x4 24.--31. 1. "LOC_LAST_UNCORR_ERROR,Location/ID of the last uncorrected error within the region defined by REG_LAST_UNCORR_ERROR. You can cycle this field value from 0 to 255 to access all counters according to the detailed report of check points at.." newline hexmask.long.byte 0x4 20.--23. 1. "REG_LAST_UNCORR_ERROR,Region of the last uncorrected error: - 0x0: Region select for Adm Rx path - 0x1: Region select for layer 3 Rx path - 0x2: Region select for layer 2 Rx path - 0x3: Region select for DMA inbound path - 0x4: Region select for AXI.." newline hexmask.long.byte 0x4 16.--19. 1. "RSVDP_16,Reserved for future use." newline hexmask.long.byte 0x4 8.--15. 1. "LOC_FIRST_UNCORR_ERROR,Location/ID of the first uncorrected error within the region defined by REG_FIRST_UNCORR_ERROR. You can cycle this field value from 0 to 255 to access all counters according to the detailed report of check points at.." newline hexmask.long.byte 0x4 4.--7. 1. "REG_FIRST_UNCORR_ERROR,Region of the first uncorrected error: - 0x0: Region select for Adm Rx path - 0x1: Region select for layer 3 Rx path - 0x2: Region select for layer 2 Rx path - 0x3: Region select for DMA inbound path - 0x4: Region select for AXI.." newline hexmask.long.byte 0x4 0.--3. 1. "RSVDP_0,Reserved for future use." group.long (0x28+0x480)++0x7 line.long 0x0 "RASDP_ERROR_MODE_EN_OFF,RASDP error mode enable. The controller enters RASDP error mode (if ERROR_MODE_EN =1) upon detection of the first uncorrectable error. During this mode: - Rx TLPs that are forwarded to your application are not guaranteed to be.." hexmask.long 0x0 2.--31. 1. "RSVDP_2,Reserved for future use." newline bitfld.long 0x0 1. "AUTO_LINK_DOWN_EN,Write '1' to enable the controller to bring the link down when the controller enters RASDP error mode. Note: This register field is sticky." "0,1" newline bitfld.long 0x0 0. "ERROR_MODE_EN,Write '1' to enable the controller enter RASDP error mode when it detects an uncorrectable error. Note: This register field is sticky." "0,1" line.long 0x4 "RASDP_ERROR_MODE_CLEAR_OFF,Exit RASDP error mode. For more details. see the RAS Data Protection (DP) section in the Core Operations chapter of the Databook." hexmask.long 0x4 1.--31. 1. "RSVDP_1,Reserved for future use." newline bitfld.long 0x4 0. "ERROR_MODE_CLEAR,Write '1' to take the controller out of RASDP error mode. The controller will then report uncorrectable errors (through AER internal error reporting) and also stop nullifying/discarding TLPs." "0,1" rgroup.long (0x30+0x480)++0x7 line.long 0x0 "RASDP_RAM_ADDR_CORR_ERROR_OFF,RAM Address where a corrected error (1-bit ECC) has been detected. For more details. see the RAS Data Protection (DP) section in the Core Operations chapter of the Databook." hexmask.long.byte 0x0 28.--31. 1. "RAM_INDEX_CORR_ERROR,RAM index where a corrected error (1-bit ECC) has been detected." newline bitfld.long 0x0 27. "RSVDP_27,Reserved for future use." "0,1" newline hexmask.long 0x0 0.--26. 1. "RAM_ADDR_CORR_ERROR,RAM Address where a corrected error (1-bit ECC) has been detected." line.long 0x4 "RASDP_RAM_ADDR_UNCORR_ERROR_OFF,RAM Address where an uncorrected error (2-bit ECC) has been detected. For more details. see the RAS Data Protection (DP) section in the Core Operations chapter of the Databook." hexmask.long.byte 0x4 28.--31. 1. "RAM_INDEX_UNCORR_ERROR,RAM index where an uncorrected error (2-bit ECC) has been detected." newline bitfld.long 0x4 27. "RSVDP_27,Reserved for future use." "0,1" newline hexmask.long 0x4 0.--26. 1. "RAM_ADDR_UNCORR_ERROR,RAM Address where an uncorrected error (2-bit ECC) has been detected." tree.end tree "PF0_RTR_CAP (PF RTR Capability Structure)" group.long (0x0+0x2F8)++0xB line.long 0x0 "RTR_EXT_CAP_HDR_OFF,Readiness Time Reporting PCI Express Extended Capability Header. For a description of this standard PCIe register. see the PCI Express Specification." hexmask.long.word 0x0 20.--31. 1. "RTR_NEXT_OFFSET,Next Capability Offset. For a description of this standard PCIe register field see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky).." hexmask.long.byte 0x0 16.--19. 1. "RTR_CAP_VERSION,Capability Version. For a description of this standard PCIe register field see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky).." hexmask.long.word 0x0 0.--15. 1. "RTR_EXT_CAP_ID,PCI Express Extended Capability ID. For a description of this standard PCIe register field see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then.." line.long 0x4 "READI_TIME_REPORTING1_OFF,Readiness Time Reporting 1. For a description of this standard PCIe register. see the PCI Express Specification." bitfld.long 0x4 31. "RTR_TIME_VALID,Valid. For a description of this standard PCIe register field see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky)" "0,1" hexmask.long.byte 0x4 24.--30. 1. "RSVDP_24,Reserved for future use." hexmask.long.word 0x4 12.--23. 1. "DL_UP_TIME,DL_UP Time. For a description of this standard PCIe register field see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky)" hexmask.long.word 0x4 0.--11. 1. "RESET_TIME,Reset Time. For a description of this standard PCIe register field see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky)" line.long 0x8 "READI_TIME_REPORTING2_OFF,Readiness Time Reporting 2. For a description of this standard PCIe register. see the PCI Express Specification." hexmask.long.byte 0x8 24.--31. 1. "RSVDP_24,Reserved for future use." hexmask.long.word 0x8 12.--23. 1. "D3HOT_D0_TIME,D3hot to D0 Time. For a description of this standard PCIe register field see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else.." hexmask.long.word 0x8 0.--11. 1. "FLR_TIME,FLR Time. For a description of this standard PCIe register field see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky)" tree.end tree "PF0_RTR_CAP_DBI2 (DBI2 Shadow Block: PF RTR Capability Structure)" rgroup.long (0x4+0x12F8)++0x7 line.long 0x0 "SHADOW_READI_TIME_REPORTING1_OFF,Shadow Register Readiness Time Reporting 1. For a description of this standard PCIe register. see the PCI Express Specification." bitfld.long 0x0 31. "RTR_TIME_VALID,Shadow Valid in the shadow register. For a description of this standard PCIe register field see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access - Dbi: No access - Dbi2: if.." "0,1" hexmask.long.tbyte 0x0 12.--30. 1. "RSVDP_12,Reserved for future use." hexmask.long.word 0x0 0.--11. 1. "RESET_TIME,Shadow Reset Time in the shadow register. For a description of this standard PCIe register field see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access - Dbi: No access - Dbi2: if.." line.long 0x4 "SHADOW_READI_TIME_REPORTING2_OFF,Shadow Register Readiness Time Reporting 2. For a description of this standard PCIe register. see the PCI Express Specification." hexmask.long.byte 0x4 24.--31. 1. "RSVDP_24,Reserved for future use." hexmask.long.word 0x4 12.--23. 1. "D3HOT_D0_TIME,Shadow D3hot to D0 Time in the shadow register. For a description of this standard PCIe register field see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access - Dbi: No access - Dbi2:.." hexmask.long.word 0x4 0.--11. 1. "FLR_TIME,Shadow FLR Time in the shadow register. For a description of this standard PCIe register field see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access - Dbi: No access - Dbi2: if.." tree.end tree "PF0_FRSQ_CAP (PF FRSQ Capability Structure)" group.long (0x0+0x2E8)++0xB line.long 0x0 "FRSQ_EXT_CAP_HDR_OFF,FRS Queuing Extended Capability Header. For a description of this standard PCIe register. see the PCI Express Specification." hexmask.long.word 0x0 20.--31. 1. "FRSQ_NEXT_OFFSET,Next Capability Offset. For a description of this standard PCIe register field see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then.." hexmask.long.byte 0x0 16.--19. 1. "FRSQ_CAP_VERSION,Capability Version. For a description of this standard PCIe register field see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky).." hexmask.long.word 0x0 0.--15. 1. "FRSQ_EXT_CAP_ID,PCI Express Extended Capability ID. For a description of this standard PCIe register field see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then.." line.long 0x4 "FRSQ_CAP_OFF,FRS Queuing Capability Register. For a description of this standard PCIe register. see the PCI Express Specification." hexmask.long.word 0x4 21.--31. 1. "RSVDP_21,Reserved for future use." hexmask.long.byte 0x4 16.--20. 1. "FRS_INT_MESSAGE_NUMBER,FRS Interrupt Message Number. For a description of this standard PCIe register field see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1).." hexmask.long.byte 0x4 12.--15. 1. "RSVDP_12,Reserved for future use." hexmask.long.word 0x4 0.--11. 1. "FRSQ_MAX_DEPTH,FRS Queue Max Depth. For a description of this standard PCIe register field see the PCI Express Specification." line.long 0x8 "FRSQ_CONTROL_FRSQ_STATUS_OFF,FRS Queuing Status and Control Register. For a description of this standard PCIe register. see the PCI Express Specification." hexmask.long.word 0x8 17.--31. 1. "RSVDP_17,Reserved for future use." bitfld.long 0x8 16. "FRS_INTERRUPT_ENABLE,FRS Interrupt Enable. For a description of this standard PCIe register field see the PCI Express Specification." "0,1" hexmask.long.word 0x8 2.--15. 1. "RSVDP_2,Reserved for future use." bitfld.long 0x8 1. "FRS_MESSAGE_OVERFLOW,FRS Message Overflow. For a description of this standard PCIe register field see the PCI Express Specification." "0,1" newline bitfld.long 0x8 0. "FRS_MESSAGE_RECEIVED,FRS Message Received. For a description of this standard PCIe register field see the PCI Express Specification." "0,1" rgroup.long (0xC+0x2E8)++0x3 line.long 0x0 "FRS_MESSAGE_QUEUE_OFF,FRS Message Queue Register. For a description of this standard PCIe register. see the PCI Express Specification." hexmask.long.word 0x0 20.--31. 1. "FRS_MESSAGE_QUE_DEPTH,FRS Message Queue Depth. For a description of this standard PCIe register field see the PCI Express Specification." hexmask.long.byte 0x0 16.--19. 1. "FRS_MESSAGE_QUE_REASON,FRS Message Queue Reason. For a description of this standard PCIe register field see the PCI Express Specification." hexmask.long.word 0x0 0.--15. 1. "FRS_MESSAGE_QUE_FUNC_ID,FRS Message Queue Function ID. For a description of this standard PCIe register field see the PCI Express Specification." tree.end tree "PF0_PTM_CAP (PF PTM Capability Structure)" group.long (0x0+0x40C)++0xB line.long 0x0 "PTM_EXT_CAP_HDR_OFF,Precision Time Measurement Capability Header. For a description of this standard PCIe register. see the PCI Express Specification." hexmask.long.word 0x0 20.--31. 1. "PTM_NEXT_OFFSET,Precision Time Measurement PCI Express Extended Capability Next Offset. For a description of this standard PCIe register see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access. -.." hexmask.long.byte 0x0 16.--19. 1. "PTM_CAP_VERSION,Precision Time Measurement PCI Express Extended Capability Version. For a description of this standard PCIe register see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi:.." hexmask.long.word 0x0 0.--15. 1. "PTM_CAP_ID,Precision Time Measurement PCI Express Extended Capability ID. For a description of this standard PCIe register see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if.." line.long 0x4 "PTM_CAP_OFF,PTM Capability Register. For a description of this standard PCIe register. see the PCI Express Specification." hexmask.long.word 0x4 16.--31. 1. "RSVDP_16,Reserved for future use." hexmask.long.byte 0x4 8.--15. 1. "PTM_CLK_GRAN,PTM Local Clock Granularity. For a description of this standard PCIe register see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky).." hexmask.long.byte 0x4 3.--7. 1. "RSVDP_3,Reserved for future use." bitfld.long 0x4 2. "PTM_ROOT_CAPABLE,PTM Root Capable. For a description of this standard PCIe register see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else.." "0,1" bitfld.long 0x4 1. "PTM_RES_CAPABLE,PTM Responder Capable. For a description of this standard PCIe register see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else.." "0,1" newline bitfld.long 0x4 0. "PTM_REQ_CAPABLE,PTM Requester Capable. For a description of this standard PCIe register see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else.." "0,1" line.long 0x8 "PTM_CONTROL_OFF,PTM Control Register. For a description of this standard PCIe register. see the PCI Express Specification." hexmask.long.word 0x8 16.--31. 1. "RSVDP_16,Reserved for future use." hexmask.long.byte 0x8 8.--15. 1. "EFF_GRAN,PTM Effective Granularity. For a description of this standard PCIe register see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: HWINIT" hexmask.long.byte 0x8 2.--7. 1. "RSVDP_2,Reserved for future use." rbitfld.long 0x8 1. "ROOT_SELECT,PTM Root Select. When set this Time Source is the PTM Root. For a description of this standard PCIe register see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: HWINIT" "0,1" bitfld.long 0x8 0. "PTM_ENABLE,PTM Enable. When set this function is permitted to participate in the PTM mechanism. For a description of this standard PCIe register see the PCI Express Specification." "0,1" tree.end tree "PF0_PTM_RES_CAP (PF PTM Responder Capability Structure (VSEC))" group.long (0x0+0x418)++0xB line.long 0x0 "PTM_RES_CAP_HDR_OFF,Precision Time Measurement Responder Capability Header (VSEC). For more details. see the PTM section in the Databook." hexmask.long.word 0x0 20.--31. 1. "PTM_RES_EXT_CAP_NEXT_OFFS,Precision Time Measurement Responder VSEC Next Pointer. For more details see the PTM section in the Databook. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then.." hexmask.long.byte 0x0 16.--19. 1. "PTM_RES_EXT_CAP_VER,Precision Time Measurement Responder VSEC Version. For more details see the PTM section in the Databook. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else.." hexmask.long.word 0x0 0.--15. 1. "PTM_RES_EXT_CAP_ID,Precision Time Measurement Responder VSEC ID. For more details see the PTM section in the Databook. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else.." line.long 0x4 "PTM_RES_HDR_OFF,Precision Time Measurement Responder Vendor Specific Header. For more details. see the PTM section in the Databook." hexmask.long.word 0x4 20.--31. 1. "PTM_RES_VSEC_LENGTH,PTM Responder VSEC Length. For more details see the PTM section in the Databook. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This.." hexmask.long.byte 0x4 16.--19. 1. "PTM_RES_VSEC_REV,PTM Responder VSEC Revision. For more details see the PTM section in the Databook. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This.." hexmask.long.word 0x4 0.--15. 1. "PTM_RES_VSEC_ID,PTM Responder VSEC ID. For more details see the PTM section in the Databook. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else R(sticky) Note: This register.." line.long 0x8 "PTM_RES_CONTROL_OFF,PTM Responder Control Register. For more details. see the PTM section in the Databook." hexmask.long 0x8 2.--31. 1. "RSVDP_2,Reserved for future use." bitfld.long 0x8 1. "PTM_RES_PDEL_BYTE_REV,PTM Requester Propagation Delay Byte Reversal - Reverse the order of bytes in the PTM Propagation Delay data word of the PTM ResponseD Message for compatibility with previous revisions. For more details see the PTM section in the.." "0,1" bitfld.long 0x8 0. "PTM_RES_CCONTEXT_VALID,PTM Responder Control Context Valid - PTM Local Timing is valid. This bit is set over the DBI. A speed change or aux_clk_active will set this bit low. For more details see the PTM section in the Databook. Note: The access.." "0,1" rgroup.long (0xC+0x418)++0x3 line.long 0x0 "PTM_RES_STATUS_OFF,PTM Responder Status Register. For more details. see the PTM section in the Databook." hexmask.long 0x0 2.--31. 1. "RSVDP_2,Reserved for future use." bitfld.long 0x0 1. "PTM_RES_REQUEST_RECEIVED,PTM 1st Request Received - PTM Responder has received the first PTM Request Message. Upon receipt of a second PTM Request Message a ResponseD message with timing information will be sent from the Responder if the context is.." "0,1" bitfld.long 0x0 0. "PTM_RES_CONTEXT_VALID,PTM Responder Status Context Valid - PTM Local Timing Context is Valid. Value set from upstream port Requester in a Switch. Shadows the same in the control register in all other products. For more details see the PTM section in the.." "0,1" group.long (0x10+0x418)++0x7 line.long 0x0 "PTM_RES_LOCAL_LSB_OFF,PTM Responder Local Clock LSB. For more details. see the PTM section in the Databook." hexmask.long 0x0 0.--31. 1. "PTM_RES_LOCAL_LSB,PTM Responder Local Clock LSB - Lower 32 bits of local timer value. For more details see the PTM section in the Databook. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then.." line.long 0x4 "PTM_RES_LOCAL_MSB_OFF,PTM Responder Local Clock MSB. For more details. see the PTM section in the Databook." hexmask.long 0x4 0.--31. 1. "PTM_RES_LOCAL_MSB,PTM Responder Local Clock MSB - Upper 32 bits of local timer value. For more details see the PTM section in the Databook. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then.." rgroup.long (0x18+0x418)++0x1F line.long 0x0 "PTM_RES_T2_LSB_OFF,PTM Responder T2 Timestamp LSB. For more details. see the PTM section in the Databook." hexmask.long 0x0 0.--31. 1. "PTM_RES_T2_LSB,PTM Responder T2 Timestamp LSB - Lower 32 bits of the T2 Timestamp value. For more details see the PTM section in the Databook. Note: This register field is sticky." line.long 0x4 "PTM_RES_T2_MSB_OFF,PTM Responder T2 Timestamp MSB. For more details. see the PTM section in the Databook." hexmask.long 0x4 0.--31. 1. "PTM_RES_T2_MSB,PTM Responder T2 Timestamp MSB - Upper 32 bits of the T2 Timestamp value. For more details see the PTM section in the Databook. Note: This register field is sticky." line.long 0x8 "PTM_RES_T2P_LSB_OFF,PTM Responder T2 Previous Timestamp LSB. For more details. see the PTM section in the Databook." hexmask.long 0x8 0.--31. 1. "PTM_RES_T2P_LSB,PTM Responder T2 Previous Timestamp LSB - Lower 32 bits of the previously stored T2 Timestamp value. For more details see the PTM section in the Databook. Note: This register field is sticky." line.long 0xC "PTM_RES_T2P_MSB_OFF,PTM Responder T2 Previous Timestamp MSB. For more details. see the PTM section in the Databook." hexmask.long 0xC 0.--31. 1. "PTM_RES_T2P_MSB,PTM Responder T2 Previous Timestamp MSB - Upper 32 bits of the previously stored T2 Timestamp value. For more details see the PTM section in the Databook. Note: This register field is sticky." line.long 0x10 "PTM_RES_T3_LSB_OFF,PTM Responder T3 Timestamp LSB. For more details. see the PTM section in the Databook." hexmask.long 0x10 0.--31. 1. "PTM_RES_T3_LSB,PTM Responder T3 Timestamp LSB - Lower 32 bits of the T3 Timestamp value. For more details see the PTM section in the Databook. Note: This register field is sticky." line.long 0x14 "PTM_RES_T3_MSB_OFF,PTM Responder T3 Timestamp MSB. For more details. see the PTM section in the Databook." hexmask.long 0x14 0.--31. 1. "PTM_RES_T3_MSB,PTM Responder T3 Timestamp MSB - Upper 32 bits of the T2 Timestamp value. For more details see the PTM section in the Databook. Note: This register field is sticky." line.long 0x18 "PTM_RES_T3P_LSB_OFF,PTM Responder T3 Previous Timestamp LSB. For more details. see the PTM section in the Databook." hexmask.long 0x18 0.--31. 1. "PTM_RES_T3P_LSB,PTM Responder T3 Previous Timestamp LSB - Lower 32 bits of the previously stored T3 Timestamp value. For more details see the PTM section in the Databook. Note: This register field is sticky." line.long 0x1C "PTM_RES_T3P_MSB_OFF,PTM Responder T3 Previous Timestamp MSB. For more details. see the PTM section in the Databook." hexmask.long 0x1C 0.--31. 1. "PTM_RES_T3P_MSB,PTM Responder T3 Previous Timestamp MSB - Upper 32 bits of the previously stored T3 Timestamp value. For more details see the PTM section in the Databook. Note: This register field is sticky." group.long (0x38+0x418)++0x7 line.long 0x0 "PTM_RES_TX_LATENCY_OFF,PTM Responder TX Latency. For more details. see the PTM section in the Databook." hexmask.long.tbyte 0x0 12.--31. 1. "RSVDP_12,Reserved for future use." hexmask.long.word 0x0 0.--11. 1. "PTM_RES_TX_LATENCY,PTM Responder TX Latency - Responder Transmit path latency (12 bit wide). For more details see the PTM section in the Databook. Note: This register field is sticky." line.long 0x4 "PTM_RES_RX_LATENCY_OFF,PTM Responder RX Latency. For more details. see the PTM section in the Databook." hexmask.long.tbyte 0x4 12.--31. 1. "RSVDP_12,Reserved for future use." hexmask.long.word 0x4 0.--11. 1. "PTM_RES_RX_LATENCY,PTM Responder RX Latency - Responder Receive path latency (12 bit wide). For more details see the PTM section in the Databook. Note: This register field is sticky." rgroup.long (0x40+0x418)++0x3 line.long 0x0 "PTM_RES_NOM_CLOCK_T_OFF,PTM Responder Nominal Clock Period. For more details. see the PTM section in the Databook." hexmask.long.byte 0x0 24.--31. 1. "RSVDP_24,Reserved for future use." hexmask.long.byte 0x0 16.--23. 1. "PTM_RES_NOM_CLOCK_T_INT,PTM Responder Nominal Clock Period Integral - Integral part of the nominal PTM local clock period in nanoseconds. For more details see the PTM section in the Databook. Note: This register field is sticky." hexmask.long.word 0x0 0.--15. 1. "PTM_RES_NOM_CLOCK_T_FRAC,PTM Responder Nominal Clock Period Fractional - Fractional part of the nominal PTM local clock period. LSB is 1/(2^16) nanoseconds. For more details see the PTM section in the Databook. Note: This register field is sticky." group.long (0x44+0x418)++0x3 line.long 0x0 "PTM_RES_SCALED_CLOCK_T_OFF,PTM Responder Scaled Clock Period. For more details. see the PTM section in the Databook." bitfld.long 0x0 31. "PTM_RES_SCALED_CLOCK_T_EN,PTM Responder Scaled Clock Period Enable - Use the programmed scaled PTM clock period rather than the nominal values. This bit is cleared when the core_clk rate starts to change and can only be set when the clock period change.." "0,1" hexmask.long.byte 0x0 24.--30. 1. "RSVDP_24,Reserved for future use." hexmask.long.byte 0x0 16.--23. 1. "PTM_RES_SCALED_CLOCK_T_INT,PTM Responder Scaled Clock Period Integral - Integral part of the nominal PTM local clock period in nanoseconds. For more details see the PTM section in the Databook. Note: This register field is sticky." newline hexmask.long.word 0x0 0.--15. 1. "PTM_RES_SCALED_CLOCK_T_FRAC,PTM Responder Scaled Clock Period Fractional - Fractional part of the nominal PTM local clock period. LSB is 1/(2^16) nanoseconds. For more details see the PTM section in the Databook. Note: This register field is sticky." tree.end tree "PF0_PM_CAP (PF PCI Power Management Capability Structure)" group.long (0x0+0x40)++0x7 line.long 0x0 "CAP_ID_NXT_PTR_REG,Power Management Capabilities Register." hexmask.long.byte 0x0 27.--31. 1. "PME_SUPPORT,PME_Support. This 5-bit field indicates the power states in which the function may generate a PME and/or forward PME messages. A value of 0b for any bit indicates that the function is not capable of asserting PME while in that power state. -.." bitfld.long 0x0 26. "D2_SUPPORT,D2_Support. If this bit is set this function supports the D2 Power Management state. Functions that do not support D2 must always return a value of 0b for this bit. Note: The access attributes of this field are as follows: - Wire: No access." "0,1" bitfld.long 0x0 25. "D1_SUPPORT,D1_Support. If this bit is set this function supports the D1 Power Management state. Functions that do not support D1 must always return a value of 0b for this bit. Note: The access attributes of this field are as follows: - Wire: No access." "0,1" bitfld.long 0x0 22.--24. "AUX_CURR,Aux_Current. This 3 bit field reports the Vaux auxiliary current requirements for the function. If this function implements the Data Register the controller hardwires this field to 000b. If PME_Support is 0 xxxxb (PME assertion from D3cold is.." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 21. "DSI,Device Specific Initialization. The DSI bit indicates whether special initialization of this function is required. When set indicates that the function requires a device specific initialization sequence following a transition to the D0uninitialized.." "0,1" bitfld.long 0x0 20. "PME_IMM_READI_RETURN_DO,Immediate_Readiness_on_Return_to_D0. - If this bit is a '1' this function is guaranteed to be ready to successfully complete valid accesses immediately after being set to D0. These accesses include configuration cycles and if.." "0,1" rbitfld.long 0x0 19. "PME_CLK,PME Clock. Does not apply to PCI Express the controller hardwires it to 0b. Note: This register field is sticky." "0,1" bitfld.long 0x0 16.--18. "PM_SPEC_VER,Version. This field provides the Power Management specification version. The controller hardwires this field to 011b for functions compliant to PCI Express Base Specification Revision 4.0 Version 1.0>. Note: The access attributes of this.." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x0 8.--15. 1. "PM_NEXT_POINTER,Next Capability Pointer. This field provides an offset into the function's configuration space pointing to the location of next item in the capabilities list. If there are no additional items in the capabilities list this field is set to.." hexmask.long.byte 0x0 0.--7. 1. "PM_CAP_ID,Capability ID. This field returns 01h to indicate that this is the PCI Power Management Capability. Each function may have only one item in its capability list with Capability ID set to 01h." line.long 0x4 "CON_STATUS_REG,Power Management Control and Status Register. This register is used to manage the PCI function's power management state as well as to enable/monitor PMEs." hexmask.long.byte 0x4 24.--31. 1. "DATA_REG_ADD_INFO,Data. This field is used to report the state dependent data requested by the Data_Select field. The value of this field is scaled by the value reported by the Data_Scale field." rbitfld.long 0x4 23. "BUS_PWR_CLK_CON_EN,Bus Power/Clock Control Enable. For a description of this standard PCIe register field see the PCI Express Base Specification." "0,1" rbitfld.long 0x4 22. "B2_B3_SUPPORT,B2B3 Support for D3hot. For a description of this standard PCIe register field see the PCI Express Base Specification." "0,1" hexmask.long.byte 0x4 16.--21. 1. "RSVDP_16,Reserved for future use." newline bitfld.long 0x4 15. "PME_STATUS,PME_Status. This bit is set when the function normally generates a PME signal. The value of this bit is not affected by the value of the PME_En bit. If PME_Support bit 31 of the Power Management Capabilities register is clear this bit is.." "0,1" rbitfld.long 0x4 13.--14. "DATA_SCALE,Data_Scale. This field indicates the scaling factor to be used when interpreting the value of the Data field. The value and meaning of this field varies depending on which data value has been selected by the Data_Select field. For more details.." "0,1,2,3" hexmask.long.byte 0x4 9.--12. 1. "DATA_SELECT,Data_Select. This 4-bit field is used to select which data is to be reported through the Data and Data_Scale field. If the Data field is not implemented this field must be hardwired to 0000b." bitfld.long 0x4 8. "PME_ENABLE,PME_En. - When set the function is permitted to generate a PME. - When clear the function is not permitted to generate a PME. If PME_Support is 1 xxxxb (PME generation from D3cold) or the function consumes Aux power and Aux power is.." "0,1" newline hexmask.long.byte 0x4 4.--7. 1. "RSVDP_4,Reserved for future use." bitfld.long 0x4 3. "NO_SOFT_RST,No_Soft_Reset. This bit indicates the state of the function after writing the PowerState field to transition the function from D3hot to D0. - When set this transition preserves internal function state. The function is in D0Active and no.." "0,1" rbitfld.long 0x4 2. "RSVDP_2,Reserved for future use." "0,1" bitfld.long 0x4 0.--1. "POWER_STATE,PowerState. This 2-bit field is used both to determine the current power state of a function and to set the function into a new power state. The definition of the field values is given below. You can write to this register; however the.." "D0,D1,D2,D3hot" tree.end tree "PF0_PCIE_CAP (PF PCI Express Capability Structure)" group.long (0x0+0x70)++0x33 line.long 0x0 "PCIE_CAP_ID_PCIE_NEXT_CAP_PTR_PCIE_CAP_REG,PCI Express Capabilities. ID. Next Pointer Register." rbitfld.long 0x0 31. "RSVDP_31,Reserved for future use." "0,1" rbitfld.long 0x0 30. "RSVD,Reserved." "0,1" newline hexmask.long.byte 0x0 25.--29. 1. "PCIE_INT_MSG_NUM,PCIE Interrupt Message Number. For a description of this standard PCIe register field see the PCI Express Base Specification. Interrupt Message Number. This field indicates which MSI/MSI-X vector is used for the interrupt message.." bitfld.long 0x0 24. "PCIE_SLOT_IMP,Slot Implemented. When set this bit indicates that the Link associated with this Port is connected to a slot (as compared to being connected to a system-integrated device or being disabled). This bit is valid for Downstream Ports. This bit.." "0,1" newline hexmask.long.byte 0x0 20.--23. 1. "PCIE_DEV_PORT_TYPE,Device/Port Type. Indicates the specific type of this PCI Express function. Note: Different functions in a Multi-Function Device can generally be of different types. Defined encodings for functions that implement a Type 00h PCI.." hexmask.long.byte 0x0 16.--19. 1. "PCIE_CAP_REG,Capability Version. Indicates PCI-SIG defined PCI Express Capability structure version number. A version of the specification that changes the PCI Express Capability structure in a way that is not otherwise identifiable (for example through.." newline hexmask.long.byte 0x0 8.--15. 1. "PCIE_CAP_NEXT_PTR,Next Capability Pointer. This field contains the offset to the next PCI Capability structure or 00h if no other items exist in the linked list of Capabilities. Note: The access attributes of this field are as follows: - Wire: No access." hexmask.long.byte 0x0 0.--7. 1. "PCIE_CAP_ID,Capability ID. Indicates the PCI Express Capability structure. This field must return a Capability ID of 10h indicating that this is a PCI Express Capability structure." line.long 0x4 "DEVICE_CAPABILITIES_REG,Device Capabilities Register. The Device Capabilities register identifies PCI Express device function specific capabilities." hexmask.long.word 0x4 16.--31. 1. "RSVDP_16,Reserved for future use." bitfld.long 0x4 15. "PCIE_CAP_ROLE_BASED_ERR_REPORT,Role-Based Error Reporting. When set this bit indicates that the function implements the functionality originally defined in the Error Reporting ECN for PCI Express Base Specification Revision 1.0a and later incorporated.." "0,1" newline hexmask.long.word 0x4 6.--14. 1. "RSVDP_6,Reserved for future use." bitfld.long 0x4 5. "PCIE_CAP_EXT_TAG_SUPP,Extended Tag Field Supported. This bit in combination with the 10-Bit Tag Requester Supported bit in the Device Capabilities 2 register indicates the maximum supported size of the Tag field as a Requester. This bit must be set if.." "0,1" newline bitfld.long 0x4 3.--4. "PCIE_CAP_PHANTOM_FUNC_SUPPORT,Phantom Functions Supported. This field indicates the support for use of unclaimed function numbers to extend the number of outstanding transactions allowed by logically combining unclaimed function numbers (called Phantom.." "0,1,2,3" bitfld.long 0x4 0.--2. "PCIE_CAP_MAX_PAYLOAD_SIZE,Max_Payload_Size Supported. This field indicates the maximum payload size that the function can support for TLPs. Defined encodings are: - 000b: 128 bytes max payload size - 001b: 256 bytes max payload size - 010b: 512 bytes max.." "0,1,2,3,4,5,6,7" line.long 0x8 "DEVICE_CONTROL_DEVICE_STATUS,Device Control and Device Status Register. This register controls PCI Express device specific parameters and provides information about PCI Express device (function) specific parameters." hexmask.long.word 0x8 22.--31. 1. "RSVDP_22,Reserved for future use." rbitfld.long 0x8 21. "PCIE_CAP_TRANS_PENDING,Transactions Pending. Endpoints: When set this bit indicates that the function has issued Non-Posted Requests that have not been completed. A Function reports this bit cleared only when all outstanding Non-Posted Requests have.." "0,1" newline rbitfld.long 0x8 20. "PCIE_CAP_AUX_POWER_DETECTED,AUX Power Detected. Functions that require Aux power report this bit as set if Aux power is detected by the function. This bit is derived by sampling the sys_aux_pwr_det input." "0,1" bitfld.long 0x8 19. "PCIE_CAP_UNSUPPORTED_REQ_DETECTED,Unsupported Request Detected. This bit indicates that the function received an Unsupported Request. Errors are logged in this register regardless of whether error reporting is enabled or not in the Device Control.." "0,1" newline bitfld.long 0x8 17. "PCIE_CAP_NON_FATAL_ERR_DETECTED,Non-Fatal Error Detected. This bit indicates status of Non-fatal errors detected. Errors are logged in this register regardless of whether error reporting is enabled or not in the Device Control register. For a.." "0,1" bitfld.long 0x8 12.--14. "PCIE_CAP_MAX_READ_REQ_SIZE,Max_Read_Request_Size. This field sets the maximum Read Request size for the function as a Requester. The function must not generate Read Requests with a size exceeding the set value. Defined encodings for this field are: -.." "0,1,2,3,4,5,6,7" newline rbitfld.long 0x8 11. "PCIE_CAP_EN_NO_SNOOP,Enable No Snoop. If this bit is set the function is permitted to Set the No Snoop bit in the Requester Attributes of transactions it initiates that do not require hardware enforced cache coherency (see section 2.2.6.5 in PCI Express.." "0,1" bitfld.long 0x8 10. "PCIE_CAP_AUX_POWER_PM_EN,Aux Power PM Enable. This bit is derived by sampling the sys_aux_pwr_det input. When set this bit enables a function to draw Aux power independent of PME Aux power. Functions that require Aux power on legacy operating systems.." "0,1" newline rbitfld.long 0x8 9. "PCIE_CAP_PHANTOM_FUNC_EN,Phantom Functions Enable. This bit in combination with the 10-Bit Tag Requester Enable bit in the Device Control 2 register determines how many Tag field bits a Requester is permitted to use. When the 10-Bit Tag Requester.." "0,1" rbitfld.long 0x8 8. "PCIE_CAP_EXT_TAG_EN,Extended Tag Field Enable. This bit in combination with the 10-Bit Tag Requester Enable bit in the Device Control 2 register determines how many Tag field bits a Requester is permitted to use. When the 10-Bit Tag Requester Enable.." "0,1" newline bitfld.long 0x8 5.--7. "PCIE_CAP_MAX_PAYLOAD_SIZE_CS,Max_Payload_Size. This field sets maximum TLP payload size for the Function. As a Receiver the Function must handle TLPs as large as the set value. As a Transmitter the Function must not generate TLPs exceeding the set.." "0,1,2,3,4,5,6,7" bitfld.long 0x8 4. "PCIE_CAP_EN_REL_ORDER,Enable Relaxed Ordering. If this bit is set the function is permitted to set the Relaxed Ordering bit in the Attributes field of transactions it initiates that do not require strong write ordering (for more details see section.." "0,1" newline bitfld.long 0x8 3. "PCIE_CAP_UNSUPPORT_REQ_REP_EN,Unsupported Request Reporting Enable. This bit in conjunction with other bits controls the signaling of Unsupported Request Errors by sending error Messages (for more details see section 6.2.5 and section 6.2.6 of PCI.." "0,1" bitfld.long 0x8 2. "PCIE_CAP_FATAL_ERR_REPORT_EN,Fatal Error Reporting Enable. This bit in conjunction with other bits controls sending ERR_FATAL Messages (for more details see section 6.2.5 and section 6.2.6 of of PCI Express Base Specification). For a Multi-Function.." "0,1" newline bitfld.long 0x8 1. "PCIE_CAP_NON_FATAL_ERR_REPORT_EN,Non-Fatal Error Reporting Enable. This bit in conjunction with other bits controls sending ERR_NONFATAL Messages (for more details see section 6.2.5 and Section 6.2.6 of PCI Express Base Specification). For a.." "0,1" bitfld.long 0x8 0. "PCIE_CAP_CORR_ERR_REPORT_EN,Correctable Error Reporting Enable. This bit in conjunction with other bits controls sending ERR_COR Messages (for more details see section 6.2.5 section 6.2.6 and section 6.2.10.2 of PCI Express Base Specification). For.." "0,1" line.long 0xC "LINK_CAPABILITIES_REG,Link Capabilities Register. The Link Capabilities register identifies PCI Express Link specific capabilities." hexmask.long.byte 0xC 24.--31. 1. "PCIE_CAP_PORT_NUM,Port Number. This field indicates the PCI Express Port number for the given PCI Express Link. Multi-Function Devices associated with an Upstream Port must report the same value in this field for all functions. Note: The access.." rbitfld.long 0xC 23. "RSVDP_23,Reserved for future use." "0,1" newline bitfld.long 0xC 22. "PCIE_CAP_ASPM_OPT_COMPLIANCE,ASPM Optionality Compliance. This bit must be set to 1b in all functions. Components implemented against certain earlier versions of this specification will have this bit set to 0b. Software is permitted to use the value of.." "0,1" bitfld.long 0xC 21. "PCIE_CAP_LINK_BW_NOT_CAP,Link Bandwidth Notification Capability. A value of 1b indicates support for the Link Bandwidth Notification status and interrupt mechanisms. This capability is required for all Root Ports and Switch Downstream Ports supporting.." "0,1" newline rbitfld.long 0xC 20. "PCIE_CAP_DLL_ACTIVE_REP_CAP,Data Link Layer Link Active Reporting Capable. For a Downstream Port the controller hardwires this bit to 1b if the component supports the optional capability of reporting the DL_Active state of the Data Link Control and.." "0,1" bitfld.long 0xC 19. "PCIE_CAP_SURPRISE_DOWN_ERR_REP_CAP,Surprise Down Error Reporting Capable. For a Downstream Port this bit must be set if the component supports the optional capability of detecting and reporting a Surprise Down error condition. For Upstream Ports and.." "0,1" newline rbitfld.long 0xC 18. "PCIE_CAP_CLOCK_POWER_MAN,Clock Power Management. For Upstream Ports a value of 1b in this bit indicates that the component tolerates the removal of any reference clock(s) via the 'clock request' (CLKREQ#) mechanism when the Link is in the L1 and L2/L3.." "0,1" bitfld.long 0xC 15.--17. "PCIE_CAP_L1_EXIT_LATENCY,L1 Exit Latency. This field indicates the L1 exit latency for the given PCI Express Link. The value reported indicates the length of time this Port requires to complete transition from ASPM L1 to L0. If ASPM L1 is not supported.." "0,1,2,3,4,5,6,7" newline bitfld.long 0xC 12.--14. "PCIE_CAP_L0S_EXIT_LATENCY,L0s Exit Latency. This field indicates the L0s exit latency for the given PCI Express Link. The value reported indicates the length of time this Port requires to complete transition from L0s to L0. If L0s is not supported the.." "0,1,2,3,4,5,6,7" bitfld.long 0xC 10.--11. "PCIE_CAP_ACTIVE_STATE_LINK_PM_SUPPORT,Active State Power Management (ASPM) Support. This field indicates the level of ASPM supported on the given PCI Express Link. For more details on ASPM support requirements see section 5.4.1 of PCI Express Base.." "0,1,2,3" newline hexmask.long.byte 0xC 4.--9. 1. "PCIE_CAP_MAX_LINK_WIDTH,Maximum Link Width. This field indicates the maximum Link width (xN - corresponding to N Lanes) implemented by the component. This value is permitted to exceed the number of Lanes routed to the slot (Downstream Port) adapter.." hexmask.long.byte 0xC 0.--3. 1. "PCIE_CAP_MAX_LINK_SPEED,Max Link Speed. This field indicates the maximum Link speed of the associated Port. The encoded value specifies a bit location in the Supported Link Speeds Vector (in the Link Capabilities 2 register) that corresponds to the.." line.long 0x10 "LINK_CONTROL_LINK_STATUS_REG,Link Control and Link Status Register. This register controls and provides information about PCI Express Link specific parameters." bitfld.long 0x10 31. "PCIE_CAP_LINK_AUTO_BW_STATUS,Link Autonomous Bandwidth Status. This bit is set by hardware to indicate that hardware has autonomously changed Link speed or width without the Port transitioning through DL_Down status for reasons other than to attempt to.." "0,1" bitfld.long 0x10 30. "PCIE_CAP_LINK_BW_MAN_STATUS,Link Bandwidth Management Status. This bit is set by hardware to indicate that either of the following has occurred without the Port transitioning through DL_Down status: - A Link retraining has completed following a write of.." "0,1" newline rbitfld.long 0x10 29. "PCIE_CAP_DLL_ACTIVE,Data Link Layer Link Active. This bit indicates the status of the Data Link Control and Management State Machine. It returns a 1b to indicate the DL_Active state 0b otherwise. This bit must be implemented if the Data Link Layer Link.." "0,1" bitfld.long 0x10 28. "PCIE_CAP_SLOT_CLK_CONFIG,Slot Clock Configuration. This bit indicates that the component uses the same physical reference clock that the platform provides on the connector. If the device uses an independent clock irrespective of the presence of a.." "0,1" newline rbitfld.long 0x10 27. "PCIE_CAP_LINK_TRAINING,Link Training. This read-only bit indicates that the Physical Layer LTSSM is in the Configuration or Recovery state or that 1b was written to the Retrain Link bit but Link training has not yet begun. Hardware clears this bit when.." "0,1" rbitfld.long 0x10 26. "RSVDP_26,Reserved for future use." "0,1" newline hexmask.long.byte 0x10 20.--25. 1. "PCIE_CAP_NEGO_LINK_WIDTH,Negotiated Link Width. This field indicates the negotiated width of the given PCI Express Link. Defined encodings are: -00 0001b: x1 -00 0010b: x2 -00 0100b: x4 -00 1000b: x8 -00 1100b: x12 -01 0000b: x16 -10 0000b: x32 All other.." hexmask.long.byte 0x10 16.--19. 1. "PCIE_CAP_LINK_SPEED,Current Link Speed. This field indicates the negotiated Link speed of the given PCI Express Link. The encoded value specifies a bit location in the Supported Link Speeds Vector (in the Link Capabilities 2 register) that corresponds to.." newline bitfld.long 0x10 14.--15. "PCIE_CAP_DRS_SIGNALING_CONTROL,DRS Signaling Control. Indicates the mechanism used to report reception of a DRS message. Must be implemented for Downstream Ports with the DRS Supported bit Set in the Link Capabilities 2 Register. Encodings are: - 00b:.." "0,1,2,3" rbitfld.long 0x10 12.--13. "RSVDP_12,Reserved for future use." "0,1,2,3" newline bitfld.long 0x10 11. "PCIE_CAP_LINK_AUTO_BW_INT_EN,Link Autonomous Bandwidth Management Interrupt Enable. When set this bit enables the generation of an interrupt to indicate that the Link Autonomous Bandwidth Status bit has been set. The write value is gated with the.." "0,1" bitfld.long 0x10 10. "PCIE_CAP_LINK_BW_MAN_INT_EN,Link Bandwidth Management Interrupt Enable. When set this bit enables the generation of an interrupt to indicate that the Link Bandwidth Management Status bit has been set. The write value is gated with the.." "0,1" newline bitfld.long 0x10 9. "PCIE_CAP_HW_AUTO_WIDTH_DISABLE,Hardware Autonomous Width Disable. When set this bit disables hardware from changing the Link width for reasons other than attempting to correct unreliable Link operation by reducing Link width. For a Multi-Function Device.." "0,1" bitfld.long 0x10 8. "PCIE_CAP_EN_CLK_POWER_MAN,Enable Clock Power Management. Applicable only for Upstream Ports and with form factors that support a 'Clock Request' (CLKREQ#) mechanism this bit operates as follows: - 0b: Clock power management is disabled and device must.." "0,1" newline bitfld.long 0x10 7. "PCIE_CAP_EXTENDED_SYNCH,Extended Synch. When set this bit forces the transmission of additional Ordered Sets when exiting the L0s state (see section 4.2.4.5 of PCI Express Base Specification) and when in the Recovery state (see section 4.2.6.4.1 of PCI.." "0,1" bitfld.long 0x10 6. "PCIE_CAP_COMMON_CLK_CONFIG,Common Clock Configuration. When set this bit indicates that this component and the component at the opposite end of this Link are operating with a distributed common reference clock. A value of 0b indicates that this.." "0,1" newline bitfld.long 0x10 5. "PCIE_CAP_RETRAIN_LINK,Retrain Link. A write of 1b to this bit initiates Link retraining by directing the Physical Layer LTSSM to the Recovery state. If the LTSSM is already in Recovery or Configuration re-entering Recovery is permitted but not required." "0,1" bitfld.long 0x10 4. "PCIE_CAP_LINK_DISABLE,Link Disable. This bit disables the Link by directing the LTSSM to the Disabled state when set; this bit is Reserved on Endpoints PCI Express to PCI/PCI-X bridges and Upstream Ports of Switches. Writes to this bit are immediately.." "0,1" newline bitfld.long 0x10 3. "PCIE_CAP_RCB,Read Completion Boundary (RCB). Root Ports: Indicates the RCB value for the Root Port. Refer to section 2.3.1.1 of PCI Express Base Specification for the definition of the parameter RCB. Defined encodings are: - 0b: 64 byte - 1b: 128 byte.." "0,1" rbitfld.long 0x10 2. "RSVDP_2,Reserved for future use." "0,1" newline bitfld.long 0x10 0.--1. "PCIE_CAP_ACTIVE_STATE_LINK_PM_CONTROL,Active State Power Management (ASPM) Control. This field controls the level of ASPM enabled on the given PCI Express Link. See section 5.4.1.3 of PCI Express Base Specification for requirements on when and how to.." "0,1,2,3" line.long 0x14 "SLOT_CAPABILITIES_REG,Slot Capabilities Register. The Slot Capabilities register identifies PCI Express slot specific capabilities." hexmask.long.word 0x14 19.--31. 1. "PCIE_CAP_PHY_SLOT_NUM,Physical Slot Number. This field indicates the physical slot number attached to this Port. This field must be hardware initialized to a value that assigns a slot number that is unique within the chassis regardless of the form.." bitfld.long 0x14 18. "PCIE_CAP_NO_CMD_CPL_SUPPORT,No Command Completed Support. When set this bit indicates that this slot does not generate software notification when an issued command is completed by the Hot-Plug Controller. This bit is only permitted to be set if the.." "0,1" newline bitfld.long 0x14 17. "PCIE_CAP_ELECTROMECH_INTERLOCK,Electromechanical Interlock Present. When set this bit indicates that an Electromechanical Interlock is implemented on the chassis for this slot. Note: The access attributes of this field are as follows: - Wire: No access." "0,1" bitfld.long 0x14 15.--16. "PCIE_CAP_SLOT_POWER_LIMIT_SCALE,Slot Power Limit Scale. Specifies the scale used for the Slot Power Limit Value (for more details see Section 6.9 of PCI Express Base Specification). Range of Values: - 00b: 1.0x - 01b: 0.1x - 10b: 0.01x - 11b: 0.001x.." "0,1,2,3" newline hexmask.long.byte 0x14 7.--14. 1. "PCIE_CAP_SLOT_POWER_LIMIT_VALUE,Slot Power Limit Value. In combination with the Slot Power Limit Scale value specifies the upper limit on power supplied by the slot (for more detais see Section 6.9 of PCI Express Base Specification) or by other means.." bitfld.long 0x14 6. "PCIE_CAP_HOT_PLUG_CAPABLE,Hot-Plug Capable. When set this bit indicates that this slot is capable of supporting hot-plug operations. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then R/W else R" "0,1" newline bitfld.long 0x14 5. "PCIE_CAP_HOT_PLUG_SURPRISE,Hot-Plug Surprise. When set this bit indicates that an adapter present in this slot might be removed from the system without any prior notification. This is a form factor specific capability. This bit is an indication to the.." "0,1" bitfld.long 0x14 4. "PCIE_CAP_POWER_INDICATOR,Power Indicator Present. When set this bit indicates that a Power Indicator is electrically controlled by the chassis for this slot. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if.." "0,1" newline bitfld.long 0x14 3. "PCIE_CAP_ATTENTION_INDICATOR,Attention Indicator Present. When set this bit indicates that an Attention Indicator is electrically controlled by the chassis. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if.." "0,1" bitfld.long 0x14 2. "PCIE_CAP_MRL_SENSOR,MRL Sensor Present. When set this bit indicates that an MRL Sensor is implemented on the chassis for this slot. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then R/W else R" "0,1" newline bitfld.long 0x14 1. "PCIE_CAP_POWER_CONTROLLER,Power Controller Present. When set this bit indicates that a software programmable Power Controller is implemented for this slot/adapter (depending on form factor). Note: The access attributes of this field are as follows: -.." "0,1" bitfld.long 0x14 0. "PCIE_CAP_ATTENTION_INDICATOR_BUTTON,Attention Button Present. When set this bit indicates that an Attention Button for this slot is electrically controlled by the chassis. Note: The access attributes of this field are as follows: - Wire: No access. -.." "0,1" line.long 0x18 "SLOT_CONTROL_SLOT_STATUS,Slot Control and Status Register. This register controls and provides information about PCI Express Slot specific parameters." hexmask.long.byte 0x18 25.--31. 1. "RSVDP_25,Reserved for future use." bitfld.long 0x18 24. "PCIE_CAP_DLL_STATE_CHANGED,Data Link Layer State Changed. This bit is set when the value reported in the Data Link Layer Link Active bit of the Link Status register is changed. In response to a Data Link Layer State Changed event software must read the.." "0,1" newline rbitfld.long 0x18 23. "PCIE_CAP_ELECTROMECH_INTERLOCK_STATUS,Electromechanical Interlock Status. If an Electromechanical Interlock is implemented this bit indicates the status of the Electromechanical Interlock. Defined encodings are: - 0b: Electromechanical Interlock.." "0,1" rbitfld.long 0x18 22. "PCIE_CAP_PRESENCE_DETECT_STATE,Presence Detect State. This bit indicates the presence of an adapter in the slot reflected by the logical 'OR' of the Physical Layer in-band presence detect mechanism and if present any out-of-band presence detect.." "0,1" newline rbitfld.long 0x18 21. "PCIE_CAP_MRL_SENSOR_STATE,MRL Sensor State. This bit reports the status of the MRL sensor if implemented. Defined encodings are: - 0b: MRL Closed - 1b: MRL Open" "0,1" bitfld.long 0x18 20. "PCIE_CAP_CMD_CPLD,Command Completed. If Command Completed notification is supported (if the No Command Completed Support bit in the Slot Capabilities register is 0b) this bit is set when a hot-plug command has completed and the Hot-Plug Controller is.." "0,1" newline bitfld.long 0x18 19. "PCIE_CAP_PRESENCE_DETECTED_CHANGED,Presence Detect Changed. This bit is set when the value reported in the Presence Detect State bit is changed." "0,1" bitfld.long 0x18 18. "PCIE_CAP_MRL_SENSOR_CHANGED,MRL Sensor Changed. If an MRL sensor is implemented this bit is set when a MRL Sensor state change is detected. If an MRL sensor is not implemented this bit must not be set." "0,1" newline bitfld.long 0x18 17. "PCIE_CAP_POWER_FAULT_DETECTED,Power Fault Detected. If a Power Controller that supports power fault detection is implemented this bit issSet when the Power Controller detects a power fault at this slot. Note: Depending on hardware capability it is.." "0,1" bitfld.long 0x18 16. "PCIE_CAP_ATTENTION_BUTTON_PRESSED,Attention Button Pressed. If an Attention Button is implemented this bit is set when the attention button is pressed. If an Attention Button is not supported this bit must not be set." "0,1" newline rbitfld.long 0x18 14.--15. "RSVDP_14,Reserved for future use." "0,1,2,3" bitfld.long 0x18 12. "PCIE_CAP_DLL_STATE_CHANGED_EN,Data Link Layer State Changed Enable. If the Data Link Layer Link Active Reporting capability is 1b this bit enables software notification when Data Link Layer Link Active bit is changed. If the Data Link Layer Link Active.." "0,1" newline bitfld.long 0x18 11. "PCIE_CAP_ELECTROMECH_INTERLOCK_CTRL,Electromechanical Interlock Control. If an Electromechanical Interlock is implemented a write of 1b to this bit causes the state of the interlock to toggle. A write of 0b to this bit has no effect. A read of this bit.." "0,1" bitfld.long 0x18 10. "PCIE_CAP_POWER_CONTROLLER_CTRL,Power Controller Control. If a Power Controller is implemented this bit when written sets the power state of the slot per the defined encodings. Reads of this bit must reflect the value from the latest write even if the.." "0,1" newline bitfld.long 0x18 8.--9. "PCIE_CAP_POWER_INDICATOR_CTRL,Power Indicator Control. If a Power Indicator is implemented writes to this field set the Power Indicator to the written state. Reads of this field must reflect the value from the latest write even if the corresponding.." "0,1,2,3" bitfld.long 0x18 6.--7. "PCIE_CAP_ATTENTION_INDICATOR_CTRL,Attention Indicator Control. If an Attention Indicator is implemented writes to this field set the Attention Indicator to the written state. Reads of this field must reflect the value from the latest write even if the.." "0,1,2,3" newline bitfld.long 0x18 5. "PCIE_CAP_HOT_PLUG_INT_EN,Hot-Plug Interrupt Enable. When set this bit enables generation of an interrupt on enabled hot-plug events. If the Hot Plug Capable bit in the Slot Capabilities register is clear this bit is permitted to be read-only with a.." "0,1" bitfld.long 0x18 4. "PCIE_CAP_CMD_CPL_INT_EN,Command Completed Interrupt Enable. If Command Completed notification is supported (if the No Command Completed Support bit in the Slot Capabilities register is 0b) when set this bit enables software notification when a hot-plug.." "0,1" newline bitfld.long 0x18 3. "PCIE_CAP_PRESENCE_DETECT_CHANGE_EN,Presence Detect Changed Enable. When set this bit enables software notification on a presence detect changed event (for more details see Section 6.7.3 of PCI Express Base Specification). If the Hot-Plug Capable bit in.." "0,1" bitfld.long 0x18 2. "PCIE_CAP_MRL_SENSOR_CHANGED_EN,MRL Sensor Changed Enable. When set this bit enables software notification on a MRL sensor changed event (for more details see Section 6.7.3 of PCI Express Base Specification). If the MRL Sensor Present bit in the Slot.." "0,1" newline bitfld.long 0x18 1. "PCIE_CAP_POWER_FAULT_DETECTED_EN,Power Fault Detected Enable. When set this bit enables software notification on a power fault event (for more details see Section 6.7.3 of PCI Express Base Specification). If a Power Controller that supports power fault.." "0,1" bitfld.long 0x18 0. "PCIE_CAP_ATTENTION_BUTTON_PRESSED_EN,Attention Button Pressed Enable. When set to 1b this bit enables software notification on an attention button pressed event (for more details see Section 6.7.3 of PCI Express Base Specification). If the Attention.." "0,1" line.long 0x1C "ROOT_CONTROL_ROOT_CAPABILITIES_REG,Root Control and Capabilities Register. This register controls PCI Express Root Complex specific parameters and identifies PCI Express Root Port specific capabilities." hexmask.long.word 0x1C 17.--31. 1. "RSVDP_17,Reserved for future use." bitfld.long 0x1C 16. "PCIE_CAP_CRS_SW_VISIBILITY,CRS Software Visibility Capable. For a description of this standard PCIe register field see the PCI Express Base Specification. CRS Software Visibility. When set this bit indicates that the Root Port is capable of returning.." "0,1" newline hexmask.long.word 0x1C 5.--15. 1. "RSVDP_5,Reserved for future use." bitfld.long 0x1C 4. "PCIE_CAP_CRS_SW_VISIBILITY_EN,CRS Software Visibility Enable. When set this bit enables the Root Port to return Configuration Request Retry Status (CRS) Completion Status to software (for more details see section 2.3.1 of PCI Express Base.." "0,1" newline bitfld.long 0x1C 3. "PCIE_CAP_PME_INT_EN,PME Interrupt Enable. When set this bit enables PME interrupt generation upon receipt of a PME Message as reflected in the PME Status bit (for more details see Table 7-29 of PCI Express Base Specification). A PME interrupt is also.." "0,1" bitfld.long 0x1C 2. "PCIE_CAP_SYS_ERR_ON_FATAL_ERR_EN,System Error on Fatal Error Enable. If set this bit indicates that a System Error should be generated if a Fatal error (ERR_FATAL) is reported by any of the devices in the Hierarchy Domain associated with this Root Port.." "0,1" newline bitfld.long 0x1C 1. "PCIE_CAP_SYS_ERR_ON_NON_FATAL_ERR_EN,System Error on Non-Fatal Error Enable. If set this bit indicates that a System Error should be generated if a Non-fatal error (ERR_NONFATAL) is reported by any of the devices in the Hierarchy Domain associated with.." "0,1" bitfld.long 0x1C 0. "PCIE_CAP_SYS_ERR_ON_CORR_ERR_EN,System Error on Correctable Error Enable. If set this bit indicates that a System Error should be generated if a correctable error (ERR_COR) is reported by any of the devices in the Hierarchy Domain associated with this.." "0,1" line.long 0x20 "ROOT_STATUS_REG,Root Status Register. The Root Status register provides information about PCI Express device specific parameters." hexmask.long.word 0x20 18.--31. 1. "RSVDP_18,Reserved for future use." rbitfld.long 0x20 17. "PCIE_CAP_PME_PENDING,PME Pending. This bit indicates that another PME is pending when the PME Status bit is s et. When the PME Status bit is cleared by software; the PME is delivered by hardware by setting the PME Status bit again and updating the PME.." "0,1" newline bitfld.long 0x20 16. "PCIE_CAP_PME_STATUS,PME Status. This bit indicates that PME was asserted by the PME Requester indicated in the PME Requester ID field. Subsequent PMEs are kept pending until the status register is cleared by software by writing a 1b." "0,1" hexmask.long.word 0x20 0.--15. 1. "PCIE_CAP_PME_REQ_ID,PME Requester ID. This field indicates the PCI Requester ID of the last PME Requester. This field is only valid when the PME Status bit is set." line.long 0x24 "DEVICE_CAPABILITIES2_REG,Device Capabilities 2 Register." bitfld.long 0x24 31. "PCIE_CAP_FRS_SUPPORTED,FRS Supported. When set indicates support for the optional Function Readiness Status (FRS) capability. Must be set for all Functions that support generation or reception capabilities of FRS Messages. Must not be set by Switch.." "0,1" hexmask.long.byte 0x24 24.--30. 1. "RSVDP_24,Reserved for future use." newline rbitfld.long 0x24 17. "PCIE_CAP2_10_BIT_TAG_REQ_SUPPORT,10-Bit Tag Requester Supported. If this bit is set the Function supports 10-Bit Tag Requester capability; otherwise the Function does not. This bit must not be set if the 10-Bit Tag Completer Supported bit is clear." "0,1" rbitfld.long 0x24 16. "PCIE_CAP2_10_BIT_TAG_COMP_SUPPORT,10-Bit Tag Completer Supported. If this bit is set the Function supports 10-Bit Tag Completer capability; otherwise the Function does not. For more details see section 2.2.6.2. of PCI Express Base Specification." "0,1" newline rbitfld.long 0x24 13. "PCIE_CAP_TPH_CMPLT_SUPPORT_1,TPH Completer Supported Bit 1." "0,1" rbitfld.long 0x24 12. "PCIE_CAP_TPH_CMPLT_SUPPORT_0,TPH Completer Supported Bit 0. Value of this bit along with TPH Completer Supported Bit 1 indicates Completer support for TPH or Extended TPH. Applicable only to Root Ports and Endpoints. For all other Functions this field.." "0,1" newline bitfld.long 0x24 11. "PCIE_CAP_LTR_SUPP,LTR Mechanism Supported. A value of 1b indicates support for the optional Latency Tolerance Reporting (LTR) mechanism. Root Ports Switches and Endpoints are permitted to implement this capability. For a Multi-Function Device associated.." "0,1" rbitfld.long 0x24 10. "PCIE_CAP_NO_RO_EN_PR2PR_PAR,No RO-enabled PR-PR Passing. If this bit is set the routing element never carries out the passing permitted by Table 2-39 of PCI Express Base Specification entry A2b that is associated with the Relaxed Ordering Attribute.." "0,1" newline rbitfld.long 0x24 9. "PCIE_CAP_128_CAS_CPL_SUPP,128-bit CAS Completer Supported. Applicable to Functions with Memory Space BARs as well as all Root Ports; must be 0b otherwise. This bit must be set to 1b if the Function supports this optional capability. For more details see.." "0,1" rbitfld.long 0x24 8. "PCIE_CAP_64_ATOMIC_CPL_SUPP,64-bit AtomicOp Completer Supported. Applicable to Functions with Memory Space BARs as well as all Root Ports; must be 0b otherwise. Includes FetchAdd Swap and CAS AtomicOps. This bit must be set to 1b if the Function.." "0,1" newline rbitfld.long 0x24 7. "PCIE_CAP_32_ATOMIC_CPL_SUPP,32-bit AtomicOp Completer Supported. Applicable to Functions with Memory Space BARs as well as all Root Ports; must be 0b otherwise. Includes FetchAdd Swap and CAS AtomicOps. This bit must be set to 1b if the Function.." "0,1" rbitfld.long 0x24 6. "PCIE_CAP_ATOMIC_ROUTING_SUPP,AtomicOp Routing Supported. Applicable only to Switch Upstream Ports Switch Downstream Ports and Root Ports; must be 0b for other Function types. This bit must be set to 1b if the Port supports this optional capability. For.." "0,1" newline rbitfld.long 0x24 5. "PCIE_CAP_ARI_FORWARD_SUPPORT,ARI Forwarding Supported. Applicable only to Switch Downstream Ports and Root Ports; must be 0b for other Function types. This bit must be set to 1b if a Switch Downstream Port or Root Port supports this optional capability." "0,1" rbitfld.long 0x24 4. "PCIE_CAP_CPL_TIMEOUT_DISABLE_SUPPORT,Completion Timeout Disable Supported. A value of 1b indicates support for the Completion Timeout Disable mechanism. The Completion Timeout Disable mechanism is required for Endpoints that issue Requests on their own.." "0,1" newline hexmask.long.byte 0x24 0.--3. 1. "PCIE_CAP_CPL_TIMEOUT_RANGE,Completion Timeout Ranges Supported. This field indicates device Function support for the optional Completion Timeout programmability mechanism. This mechanism allows system software to modify the Completion Timeout value. This.." line.long 0x28 "DEVICE_CONTROL2_DEVICE_STATUS2_REG,Device Control 2 and Status 2 Register." bitfld.long 0x28 10. "PCIE_CAP_LTR_EN,LTR Mechanism Enable. When set to 1b this bit enables Upstream Ports to send LTR messages and Downstream Ports to process LTR Messages. For a Multi-Function Device associated with an Upstream Port of a device that implements LTR the bit.." "0,1" rbitfld.long 0x28 5. "PCIE_CAP_ARI_FORWARD_SUPPORT_CS,ARI Forwarding Enable. When set the Downstream Port disables its traditional Device Number field being 0 enforcement when turning a Type 1 Configuration Request into a Type 0 Configuration Request permitting access to.." "0,1" newline bitfld.long 0x28 4. "PCIE_CAP_CPL_TIMEOUT_DISABLE,Completion Timeout Disable. When set this bit disables the Completion Timeout mechanism. This bit is required for all Functions that support the Completion Timeout Disable Capability. Functions that do not support this.." "0,1" hexmask.long.byte 0x28 0.--3. 1. "PCIE_CAP_CPL_TIMEOUT_VALUE,Completion Timeout Value. In device Functions that support Completion Timeout programmability this field allows system software to modify the Completion Timeout value. This field is applicable to Root Ports Endpoints that.." line.long 0x2C "LINK_CAPABILITIES2_REG,Link Capabilities 2 Register." bitfld.long 0x2C 31. "DRS_SUPPORTED,DRS Supported. When set indicates support for the optional Device Readiness Status (DRS) capability. Must be Set in Downstream Ports that support DRS. Must be Set in Downstream Ports that support FRS. For Upstream Ports that support DRS.." "0,1" hexmask.long.byte 0x2C 25.--30. 1. "RSVDP_25,Reserved for future use." newline hexmask.long.word 0x2C 9.--22. 1. "RSVDP_9,Reserved for future use." rbitfld.long 0x2C 8. "PCIE_CAP_CROSS_LINK_SUPPORT,Crosslink Supported. When set to 1b this bit indicates that the associated Port supports crosslinks (for more details see section 4.2.6.3.1 of PCI Express Base Specification). When set to 0b on a Port that supports Link.." "0,1" newline hexmask.long.byte 0x2C 1.--7. 1. "PCIE_CAP_SUPPORT_LINK_SPEED_VECTOR,Supported Link Speeds Vector. This field indicates the supported Link speed(s) of the associated Port. For each bit a value of 1b indicates that the corresponding Link speed is supported; otherwise the Link speed is.." rbitfld.long 0x2C 0. "RSVDP_0,Reserved for future use." "0,1" line.long 0x30 "LINK_CONTROL2_LINK_STATUS2_REG,Link Control 2 and Status 2 Register." bitfld.long 0x30 31. "DRS_MESSAGE_RECEIVED,DRS Message Received. This bit must be set whenever the Port receives a DRS Message. This bit must be cleared in DL_Down. This bit must be implemented in any Downstream Port where the DRS Supported bit is Set in the Link Capabilities.." "0,1" rbitfld.long 0x30 28.--30. "DOWNSTREAM_COMPO_PRESENCE,Downstream Component Presence. This field indicates the presence and DRS status for the Downstream Component if any connected to the Link; defined values are: - 000b: Link Down - Presence Not Determined - 001b: Link Down -.." "0,1,2,3,4,5,6,7" newline rbitfld.long 0x30 26.--27. "RSVDP_26,Reserved for future use." "0,1,2,3" bitfld.long 0x30 21. "PCIE_CAP_LINK_EQ_REQ,Link Equalization Request 8.0 GT/s. This bit is set by hardware to request the 8.0 GT/s Link equalization process to be performed on the Link. For more details see sections 4.2.3 and 4.2.6.4.2 of PCI Express Base Specification. For.." "0,1" newline rbitfld.long 0x30 20. "PCIE_CAP_EQ_CPL_P3,EEqualization 8.0 GT/s Phase 3 Successful. When set to 1b this bit indicates that Phase 3 of the 8.0 GT/s Transmitter Equalization procedure has successfully completed. Details of the Transmitter Equalization process and when this bit.." "0,1" rbitfld.long 0x30 19. "PCIE_CAP_EQ_CPL_P2,Equalization 8.0 GT/s Phase 2 Successful. When set to 1b this bit indicates that Phase 2 of the 8.0 GT/s Transmitter Equalization procedure has successfully completed. Details of the Transmitter Equalization process and when this bit.." "0,1" newline rbitfld.long 0x30 18. "PCIE_CAP_EQ_CPL_P1,Equalization 8.0 GT/s Phase 1 Successful. When set to 1b this bit indicates that Phase 1 of the 8.0 GT/s Transmitter Equalization procedure has successfully completed. Details of the Transmitter Equalization process and when this bit.." "0,1" rbitfld.long 0x30 17. "PCIE_CAP_EQ_CPL,Equalization 8.0 GT/s Complete. When set to 1b this bit indicates that the Transmitter Equalization procedure at the 8.0 GT/s data rate has completed. Details of the Transmitter Equalization process and when this bit needs to be set to.." "0,1" newline rbitfld.long 0x30 16. "PCIE_CAP_CURR_DEEMPHASIS,Current De-emphasis Level. When the Link is operating at 5.0 GT/s speed this bit reflects the level of de-emphasis. Encodings: - 1b: -3.5 dB - 0b: -6 dB The value in this bit is undefined when the Link is not operating at 5.0.." "0,1" hexmask.long.byte 0x30 12.--15. 1. "PCIE_CAP_COMPLIANCE_PRESET,Compliance Preset/De-emphasis. For 8.0 GT/s and higher Data Rate: This field sets the Transmitter Preset in Polling.Compliance state if the entry occurred due to the Enter Compliance bit being 1b. The encodings are defined in.." newline bitfld.long 0x30 11. "PCIE_CAP_COMPLIANCE_SOS,Compliance SOS. When set to 1b the LTSSM is required to send SKP Ordered Sets between sequences when sending the Compliance Pattern or Modified Compliance Pattern. For a Multi-Function Device associated with an Upstream Port the.." "0,1" bitfld.long 0x30 10. "PCIE_CAP_ENTER_MODIFIED_COMPLIANCE,Enter Modified Compliance. When this bit is set to 1b the device transmits Modified Compliance Pattern if the LTSSM enters Polling.Compliance substate. Components that support only the 2.5 GT/s speed are permitted to.." "0,1" newline bitfld.long 0x30 7.--9. "PCIE_CAP_TX_MARGIN,Transmit Margin - This field controls the value of the non-deemphasized voltage level at the Transmitter pins. This field is reset to 000b on entry to the LTSSM Polling.Configuration substate (see Chapter 4 of PCI Express Base.." "0,1,2,3,4,5,6,7" bitfld.long 0x30 6. "PCIE_CAP_SEL_DEEMPHASIS,Selectable De-emphasis. When the Link is operating at 5.0 GT/s speed this bit is used to control the transmit de-emphasis of the link in specific situations. For more details see section 4.2.6 of PCI Express Base Specification." "0,1" newline bitfld.long 0x30 5. "PCIE_CAP_HW_AUTO_SPEED_DISABLE,Hardware Autonomous Speed Disable. When set this bit disables hardware from changing the Link speed for device-specific reasons other than attempting to correct unreliable Link operation by reducing Link speed. Initial.." "0,1" bitfld.long 0x30 4. "PCIE_CAP_ENTER_COMPLIANCE,Enter Compliance. Software is permitted to force a Link to enter Compliance mode (at the speed indicated in the Target Link Speed field and the de-emphasis/preset level indicated by the Compliance Preset/De-emphasis field) by.." "0,1" newline hexmask.long.byte 0x30 0.--3. 1. "PCIE_CAP_TARGET_LINK_SPEED,Target Link Speed. For Downstream Ports this field sets an upper limit on Link operational speed by restricting the values advertised by the Upstream component in its training sequences. The encoded value specifies a bit.." tree.end tree "PF0_AER_CAP (PF Advanced Error Reporting Capability Structure)" group.long (0x0+0x100)++0x1B line.long 0x0 "AER_EXT_CAP_HDR_OFF,Advanced Error Reporting Extended Capability Header. For a description of this standard PCIe register. see the PCI Express Specification." hexmask.long.word 0x0 20.--31. 1. "NEXT_OFFSET,Next Capability Offset. For a description of this standard PCIe register field see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky).." hexmask.long.byte 0x0 16.--19. 1. "CAP_VERSION,Capability Version. For a description of this standard PCIe register field see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else.." newline hexmask.long.word 0x0 0.--15. 1. "CAP_ID,AER Extended Capability ID. For a description of this standard PCIe register field see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN == 1) then R/W(sticky) else.." line.long 0x4 "UNCORR_ERR_STATUS_OFF,Uncorrectable Error Status Register. For a description of this standard PCIe register. see the PCI Express Specification." hexmask.long.byte 0x4 27.--31. 1. "RSVDP_27,Reserved for future use." rbitfld.long 0x4 23. "RSVDP_23,Reserved for future use." "0,1" newline bitfld.long 0x4 22. "INTERNAL_ERR_STATUS,Uncorrectable Internal Error Status. For a description of this standard PCIe register field see the PCI Express Specification. The controller sets this bit when your application asserts app_err_bus[9]. It does not set this bit when.." "0,1" bitfld.long 0x4 20. "UNSUPPORTED_REQ_ERR_STATUS,Unsupported Request Error Status. For a description of this standard PCIe register field see the PCI Express Specification." "0,1" newline bitfld.long 0x4 19. "ECRC_ERR_STATUS,ECRC Error Status. For a description of this standard PCIe register field see the PCI Express Specification. Note:If CX_ECRC_ENABLE=0 the register field always reads 0." "0,1" bitfld.long 0x4 18. "MALF_TLP_ERR_STATUS,Malformed TLP Status. For a description of this standard PCIe register field see the PCI Express Specification." "0,1" newline bitfld.long 0x4 17. "REC_OVERFLOW_ERR_STATUS,Receiver Overflow Status. For a description of this standard PCIe register field see the PCI Express Specification." "0,1" bitfld.long 0x4 16. "UNEXP_CMPLT_ERR_STATUS,Unexpected Completion Status. For a description of this standard PCIe register field see the PCI Express Specification." "0,1" newline bitfld.long 0x4 15. "CMPLT_ABORT_ERR_STATUS,Completer Abort Status. For a description of this standard PCIe register field see the PCI Express Specification." "0,1" bitfld.long 0x4 14. "CMPLT_TIMEOUT_ERR_STATUS,Completion Timeout Status. For a description of this standard PCIe register field see the PCI Express Specification." "0,1" newline bitfld.long 0x4 13. "FC_PROTOCOL_ERR_STATUS,Flow Control Protocol Error Status. For a description of this standard PCIe register field see the PCI Express Specification." "0,1" bitfld.long 0x4 12. "POIS_TLP_ERR_STATUS,Poisoned TLP Status. For a description of this standard PCIe register field see the PCI Express Specification." "0,1" newline hexmask.long.byte 0x4 6.--11. 1. "RSVDP_6,Reserved for future use." bitfld.long 0x4 5. "SURPRISE_DOWN_ERR_STATUS,Surprise Down Error Status (Optional). For a description of this standard PCIe register field see the PCI Express Specification." "0,1" newline bitfld.long 0x4 4. "DL_PROTOCOL_ERR_STATUS,Data Link Protocol Error Status. For a description of this standard PCIe register field see the PCI Express Specification." "0,1" hexmask.long.byte 0x4 0.--3. 1. "RSVDP_0,Reserved for future use." line.long 0x8 "UNCORR_ERR_MASK_OFF,Uncorrectable Error Mask Register. For a description of this standard PCIe register. see the PCI Express Specification." hexmask.long.byte 0x8 27.--31. 1. "RSVDP_27,Reserved for future use." rbitfld.long 0x8 23. "RSVDP_23,Reserved for future use." "0,1" newline bitfld.long 0x8 22. "INTERNAL_ERR_MASK,Uncorrectable Internal Error Mask (Optional). For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." "0,1" rbitfld.long 0x8 21. "ACS_VIOLATION_MASK,ACS Violation Mask. Setting the ACS Violation Mask bit disables error logging and signaling for ACS Violation errors. The bit is Read-Only Zero for upstream ports when ACS P2P Egress Control Enable is not set. For a description of.." "0,1" newline bitfld.long 0x8 20. "UNSUPPORTED_REQ_ERR_MASK,Unsupported Request Error Mask. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." "0,1" bitfld.long 0x8 19. "ECRC_ERR_MASK,ECRC Error Mask (Optional). For a description of this standard PCIe register field see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W (sticky) Note: This register.." "0,1" newline bitfld.long 0x8 18. "MALF_TLP_ERR_MASK,Malformed TLP Mask. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." "0,1" bitfld.long 0x8 17. "REC_OVERFLOW_ERR_MASK,Receiver Overflow Mask (Optional). For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." "0,1" newline bitfld.long 0x8 16. "UNEXP_CMPLT_ERR_MASK,Unexpected Completion Mask. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." "0,1" bitfld.long 0x8 15. "CMPLT_ABORT_ERR_MASK,Completer Abort Error Mask (Optional). For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." "0,1" newline bitfld.long 0x8 14. "CMPLT_TIMEOUT_ERR_MASK,Completion Timeout Error Mask. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." "0,1" bitfld.long 0x8 13. "FC_PROTOCOL_ERR_MASK,Flow Control Protocol Error Mask. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." "0,1" newline bitfld.long 0x8 12. "POIS_TLP_ERR_MASK,Poisoned TLP Error Mask. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." "0,1" hexmask.long.byte 0x8 6.--11. 1. "RSVDP_6,Reserved for future use." newline rbitfld.long 0x8 5. "SURPRISE_DOWN_ERR_MASK,Surprise Down Error Mask. For a description of this standard PCIe register field see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi:.." "0,1" bitfld.long 0x8 4. "DL_PROTOCOL_ERR_MASK,Data Link Protocol Error Mask. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." "0,1" newline hexmask.long.byte 0x8 0.--3. 1. "RSVDP_0,Reserved for future use." line.long 0xC "UNCORR_ERR_SEV_OFF,Uncorrectable Error Severity Register. For a description of this standard PCIe register. see the PCI Express Specification." hexmask.long.byte 0xC 27.--31. 1. "RSVDP_27,Reserved for future use." rbitfld.long 0xC 24. "ATOMIC_EGRESS_BLOCKED_ERR_SEVERITY,AtomicOp Egress Blocked Severity (Optional). For a description of this standard PCIe register field see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi:.." "0,1" newline rbitfld.long 0xC 23. "RSVDP_23,Reserved for future use." "0,1" bitfld.long 0xC 22. "INTERNAL_ERR_SEVERITY,Uncorrectable Internal Error Severity (Optional). For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." "0,1" newline bitfld.long 0xC 20. "UNSUPPORTED_REQ_ERR_SEVERITY,Unsupported Request Error Severity. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." "0,1" bitfld.long 0xC 19. "ECRC_ERR_SEVERITY,ECRC Error Severity (Optional). For a description of this standard PCIe register field see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W (sticky) Note: This.." "0,1" newline bitfld.long 0xC 18. "MALF_TLP_ERR_SEVERITY,Malformed TLP Severity. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." "0,1" bitfld.long 0xC 17. "REC_OVERFLOW_ERR_SEVERITY,Receiver Overflow Error Severity (Optional). For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." "0,1" newline bitfld.long 0xC 16. "UNEXP_CMPLT_ERR_SEVERITY,Unexpected Completion Error Severity. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." "0,1" bitfld.long 0xC 15. "CMPLT_ABORT_ERR_SEVERITY,Completer Abort Error Severity (Optional). For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." "0,1" newline bitfld.long 0xC 14. "CMPLT_TIMEOUT_ERR_SEVERITY,Completion Timeout Error Severity. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." "0,1" bitfld.long 0xC 13. "FC_PROTOCOL_ERR_SEVERITY,Flow Control Protocol Error Severity (Optional). For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." "0,1" newline bitfld.long 0xC 12. "POIS_TLP_ERR_SEVERITY,Poisoned TLP Severity. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." "0,1" hexmask.long.byte 0xC 6.--11. 1. "RSVDP_6,Reserved for future use." newline rbitfld.long 0xC 5. "SURPRISE_DOWN_ERR_SVRITY,Surprise Down Error Severity (Optional). For a description of this standard PCIe register field see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi:.." "0,1" bitfld.long 0xC 4. "DL_PROTOCOL_ERR_SEVERITY,Data Link Protocol Error Severity. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." "0,1" newline hexmask.long.byte 0xC 0.--3. 1. "RSVDP_0,Reserved for future use." line.long 0x10 "CORR_ERR_STATUS_OFF,Correctable Error Status Register. For a description of this standard PCIe register. see the PCI Express Specification." hexmask.long.word 0x10 16.--31. 1. "RSVDP_16,Reserved for future use." bitfld.long 0x10 15. "HEADER_LOG_OVERFLOW_STATUS,Header Log Overflow Error Status (Optional). For a description of this standard PCIe register field see the PCI Express Specification." "0,1" newline bitfld.long 0x10 14. "CORRECTED_INT_ERR_STATUS,Corrected Internal Error Status (Optional). For a description of this standard PCIe register field see the PCI Express Specification." "0,1" bitfld.long 0x10 13. "ADVISORY_NON_FATAL_ERR_STATUS,Advisory Non-Fatal Error Status. For a description of this standard PCIe register field see the PCI Express Specification." "0,1" newline bitfld.long 0x10 12. "RPL_TIMER_TIMEOUT_STATUS,Replay Timer Timeout Status. For a description of this standard PCIe register field see the PCI Express Specification." "0,1" rbitfld.long 0x10 9.--11. "RSVDP_9,Reserved for future use." "0,1,2,3,4,5,6,7" newline bitfld.long 0x10 8. "REPLAY_NO_ROLEOVER_STATUS,REPLAY_NUM Rollover Status. For a description of this standard PCIe register field see the PCI Express Specification." "0,1" bitfld.long 0x10 7. "BAD_DLLP_STATUS,Bad DLLP Status. For a description of this standard PCIe register field see the PCI Express Specification." "0,1" newline bitfld.long 0x10 6. "BAD_TLP_STATUS,Bad TLP Status. For a description of this standard PCIe register field see the PCI Express Specification." "0,1" hexmask.long.byte 0x10 1.--5. 1. "RSVDP_1,Reserved for future use." newline bitfld.long 0x10 0. "RX_ERR_STATUS,Receiver Error Status (Optional). For a description of this standard PCIe register field see the PCI Express Specification." "0,1" line.long 0x14 "CORR_ERR_MASK_OFF,Correctable Error Mask Register. For a description of this standard PCIe register. see the PCI Express Specification." hexmask.long.word 0x14 16.--31. 1. "RSVDP_16,Reserved for future use." bitfld.long 0x14 15. "HEADER_LOG_OVERFLOW_MASK,Header Log Overflow Error Mask (Optional). For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." "0,1" newline bitfld.long 0x14 14. "CORRECTED_INT_ERR_MASK,Corrected Internal Error Mask (Optional). For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." "0,1" bitfld.long 0x14 13. "ADVISORY_NON_FATAL_ERR_MASK,Advisory Non-Fatal Error Mask. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." "0,1" newline bitfld.long 0x14 12. "RPL_TIMER_TIMEOUT_MASK,Replay Timer Timeout Mask. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." "0,1" rbitfld.long 0x14 9.--11. "RSVDP_9,Reserved for future use." "0,1,2,3,4,5,6,7" newline bitfld.long 0x14 8. "REPLAY_NO_ROLEOVER_MASK,REPLAY_NUM Rollover Mask. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." "0,1" bitfld.long 0x14 7. "BAD_DLLP_MASK,Bad DLLP Mask. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." "0,1" newline bitfld.long 0x14 6. "BAD_TLP_MASK,Bad TLP Mask. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." "0,1" hexmask.long.byte 0x14 1.--5. 1. "RSVDP_1,Reserved for future use." newline bitfld.long 0x14 0. "RX_ERR_MASK,Receiver Error Mask (Optional). For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." "0,1" line.long 0x18 "ADV_ERR_CAP_CTRL_OFF,Advanced Error Capabilities and Control Register. For a description of this standard PCIe register. see the PCI Express Specification." hexmask.long.tbyte 0x18 13.--31. 1. "RSVDP_13,Reserved for future use." rbitfld.long 0x18 12. "CTO_PRFX_HDR_LOG_CAP,TLP Prefix Log Present. For a description of this standard PCIe register field see the PCI Express Specification." "0,1" newline rbitfld.long 0x18 10. "MULTIPLE_HEADER_EN,Multiple Header Recording Enable. For a description of this standard PCIe register field see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R (sticky) Note: This.." "0,1" rbitfld.long 0x18 9. "MULTIPLE_HEADER_CAP,Multiple Header Recording Capable. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." "0,1" newline bitfld.long 0x18 8. "ECRC_CHECK_EN,ECRC Check Enable. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." "0,1" rbitfld.long 0x18 7. "ECRC_CHECK_CAP,ECRC Check Capable. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." "0,1" newline bitfld.long 0x18 6. "ECRC_GEN_EN,ECRC Generation Enable. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." "0,1" rbitfld.long 0x18 5. "ECRC_GEN_CAP,ECRC Generation Capable. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." "0,1" newline hexmask.long.byte 0x18 0.--4. 1. "FIRST_ERR_POINTER,First Error Pointer. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." rgroup.long (0x1C+0x100)++0xF line.long 0x0 "HDR_LOG_0_OFF,Header Log Register 0. For a description of this standard PCIe register. see the PCI Express Specification." hexmask.long.byte 0x0 24.--31. 1. "FIRST_DWORD_FOURTH_BYTE,Byte 3 of Header log register of First 32 bit Data Word. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." hexmask.long.byte 0x0 16.--23. 1. "FIRST_DWORD_THIRD_BYTE,Byte 2 of Header log register of First 32 bit Data Word. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." newline hexmask.long.byte 0x0 8.--15. 1. "FIRST_DWORD_SECOND_BYTE,Byte 1 of Header log register of First 32 bit Data Word. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." hexmask.long.byte 0x0 0.--7. 1. "FIRST_DWORD_FIRST_BYTE,Byte 0 of Header log register of First 32 bit Data Word. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." line.long 0x4 "HDR_LOG_1_OFF,Header Log Register 1. For a description of this standard PCIe register. see the PCI Express Specification." hexmask.long.byte 0x4 24.--31. 1. "SECOND_DWORD_FOURTH_BYTE,Byte 3 of Header log register of Second 32 bit Data Word. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." hexmask.long.byte 0x4 16.--23. 1. "SECOND_DWORD_THIRD_BYTE,Byte 2 of Header log register of Second 32 bit Data Word. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." newline hexmask.long.byte 0x4 8.--15. 1. "SECOND_DWORD_SECOND_BYTE,Byte 1 of Header log register of Second 32 bit Data Word. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." hexmask.long.byte 0x4 0.--7. 1. "SECOND_DWORD_FIRST_BYTE,Byte 0 of Header log register of Second 32 bit Data Word. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." line.long 0x8 "HDR_LOG_2_OFF,Header Log Register 2. For a description of this standard PCIe register. see the PCI Express Specification." hexmask.long.byte 0x8 24.--31. 1. "THIRD_DWORD_FOURTH_BYTE,Byte 3 of Header log register of Third 32 bit Data Word. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." hexmask.long.byte 0x8 16.--23. 1. "THIRD_DWORD_THIRD_BYTE,Byte 2 of Header log register of Third 32 bit Data Word. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." newline hexmask.long.byte 0x8 8.--15. 1. "THIRD_DWORD_SECOND_BYTE,Byte 1 of Header log register of Third 32 bit Data Word. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." hexmask.long.byte 0x8 0.--7. 1. "THIRD_DWORD_FIRST_BYTE,Byte 0 of Header log register of Third 32 bit Data Word. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." line.long 0xC "HDR_LOG_3_OFF,Header Log Register 3. For a description of this standard PCIe register. see the PCI Express Specification." hexmask.long.byte 0xC 24.--31. 1. "FOURTH_DWORD_FOURTH_BYTE,Byte 3 of Header log register of Fourth 32 bit Data Word. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." hexmask.long.byte 0xC 16.--23. 1. "FOURTH_DWORD_THIRD_BYTE,Byte 2 of Header log register of Fourth 32 bit Data Word. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." newline hexmask.long.byte 0xC 8.--15. 1. "FOURTH_DWORD_SECOND_BYTE,Byte 1 of Header log register of Fourth 32 bit Data Word. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." hexmask.long.byte 0xC 0.--7. 1. "FOURTH_DWORD_FIRST_BYTE,Byte 0 of Header log register of Fourth 32 bit Data Word. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." group.long (0x2C+0x100)++0x7 line.long 0x0 "ROOT_ERR_CMD_OFF,Root Error Command Register. For a description of this standard PCIe register. see the PCI Express Specification." hexmask.long 0x0 3.--31. 1. "RSVDP_3,Reserved for future use." bitfld.long 0x0 2. "FATAL_ERR_REPORTING_EN,Fatal Error Reporting Enable. For a description of this standard PCIe register field see the PCI Express Specification." "0,1" newline bitfld.long 0x0 1. "NON_FATAL_ERR_REPORTING_EN,Non-Fatal Error Reporting Enable. For a description of this standard PCIe register field see the PCI Express Specification." "0,1" bitfld.long 0x0 0. "CORR_ERR_REPORTING_EN,Correctable Error Reporting Enable. For a description of this standard PCIe register field see the PCI Express Specification." "0,1" line.long 0x4 "ROOT_ERR_STATUS_OFF,Root Error Status Register. For a description of this standard PCIe register. see the PCI Express Specification." hexmask.long.byte 0x4 27.--31. 1. "ADV_ERR_INT_MSG_NUM,Advanced Error Interrupt Message Number. For a description of this standard PCIe register field see the PCI Express Specification. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: if (DBI_RO_WR_EN.." hexmask.long.tbyte 0x4 7.--26. 1. "RSVDP_7,Reserved for future use." newline bitfld.long 0x4 6. "FATAL_ERR_MSG_RX,One or more Fatal Error Messages Received. For a description of this standard PCIe register field see the PCI Express Specification." "0,1" bitfld.long 0x4 5. "NON_FATAL_ERR_MSG_RX,One or more Non-Fatal Error Messages Received. For a description of this standard PCIe register field see the PCI Express Specification." "0,1" newline bitfld.long 0x4 4. "FIRST_UNCORR_FATAL,First Uncorrectable Error is Fatal. For a description of this standard PCIe register field see the PCI Express Specification." "0,1" bitfld.long 0x4 3. "MUL_ERR_FATAL_NON_FATAL_RX,Multiple Fatal or Non-Fatal Errors Received. For a description of this standard PCIe register field see the PCI Express Specification." "0,1" newline bitfld.long 0x4 2. "ERR_FATAL_NON_FATAL_RX,Fatal or Non-Fatal Error Received. For a description of this standard PCIe register field see the PCI Express Specification." "0,1" bitfld.long 0x4 1. "MUL_ERR_COR_RX,Multiple Correctable Errors Received. For a description of this standard PCIe register field see the PCI Express Specification." "0,1" newline bitfld.long 0x4 0. "ERR_COR_RX,Correctable Error Received. For a description of this standard PCIe register field see the PCI Express Specification." "0,1" rgroup.long (0x34+0x100)++0x13 line.long 0x0 "ERR_SRC_ID_OFF,Error Source Identification Register. For a description of this standard PCIe register. see the PCI Express Specification." hexmask.long.word 0x0 16.--31. 1. "ERR_FATAL_NON_FATAL_SOURCE_ID,Source of Fatal/Non-Fatal Error. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." hexmask.long.word 0x0 0.--15. 1. "ERR_COR_SOURCE_ID,Source of Correctable Error. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." line.long 0x4 "TLP_PREFIX_LOG_1_OFF,TLP Prefix Log Register 1. For a description of this standard PCIe register. see the PCI Express Specification." hexmask.long.byte 0x4 24.--31. 1. "CFG_TLP_PFX_LOG_1_FOURTH_BYTE,Byte 3 of Error TLP Prefix Log 1. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." hexmask.long.byte 0x4 16.--23. 1. "CFG_TLP_PFX_LOG_1_THIRD_BYTE,Byte 2 of Error TLP Prefix Log 1. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." newline hexmask.long.byte 0x4 8.--15. 1. "CFG_TLP_PFX_LOG_1_SECOND_BYTE,Byte 1 of Error TLP Prefix Log 1. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." hexmask.long.byte 0x4 0.--7. 1. "CFG_TLP_PFX_LOG_1_FIRST_BYTE,Byte 0 of Error TLP Prefix Log 1. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." line.long 0x8 "TLP_PREFIX_LOG_2_OFF,TLP Prefix Log Register 2. For a description of this standard PCIe register. see the PCI Express Specification." hexmask.long.byte 0x8 24.--31. 1. "CFG_TLP_PFX_LOG_2_FOURTH_BYTE,Byte 3 Error TLP Prefix Log 2. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." hexmask.long.byte 0x8 16.--23. 1. "CFG_TLP_PFX_LOG_2_THIRD_BYTE,Byte 2 Error TLP Prefix Log 2. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." newline hexmask.long.byte 0x8 8.--15. 1. "CFG_TLP_PFX_LOG_2_SECOND_BYTE,Byte 1 Error TLP Prefix Log 2. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." hexmask.long.byte 0x8 0.--7. 1. "CFG_TLP_PFX_LOG_2_FIRST_BYTE,Byte 0 Error TLP Prefix Log 2. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." line.long 0xC "TLP_PREFIX_LOG_3_OFF,TLP Prefix Log Register 3. For a description of this standard PCIe register. see the PCI Express Specification." hexmask.long.byte 0xC 24.--31. 1. "CFG_TLP_PFX_LOG_3_FOURTH_BYTE,Byte 3 Error TLP Prefix Log 3. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." hexmask.long.byte 0xC 16.--23. 1. "CFG_TLP_PFX_LOG_3_THIRD_BYTE,Byte 2 Error TLP Prefix Log 3. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." newline hexmask.long.byte 0xC 8.--15. 1. "CFG_TLP_PFX_LOG_3_SECOND_BYTE,Byte 1 Error TLP Prefix Log 3. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." hexmask.long.byte 0xC 0.--7. 1. "CFG_TLP_PFX_LOG_3_FIRST_BYTE,Byte 0 Error TLP Prefix Log 3. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." line.long 0x10 "TLP_PREFIX_LOG_4_OFF,TLP Prefix Log Register 4. For a description of this standard PCIe register. see the PCI Express Specification." hexmask.long.byte 0x10 24.--31. 1. "CFG_TLP_PFX_LOG_4_FOURTH_BYTE,Byte 3 Error TLP Prefix Log 4. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." hexmask.long.byte 0x10 16.--23. 1. "CFG_TLP_PFX_LOG_4_THIRD_BYTE,Byte 2 Error TLP Prefix Log 4. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." newline hexmask.long.byte 0x10 8.--15. 1. "CFG_TLP_PFX_LOG_4_SECOND_BYTE,Byte 1 Error TLP Prefix Log 4. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." hexmask.long.byte 0x10 0.--7. 1. "CFG_TLP_PFX_LOG_4_FIRST_BYTE,Byte 0 Error TLP Prefix Log 4. For a description of this standard PCIe register field see the PCI Express Specification. Note: This register field is sticky." tree.end tree "PF0_MSI_CAP (PF MSI Capability Structure)" group.long (0x0+0x50)++0x13 line.long 0x0 "PCI_MSI_CAP_ID_NEXT_CTRL_REG,MSI Capability Header and Message Control Register." hexmask.long.byte 0x0 27.--31. 1. "RSVDP_27,Reserved for future use." bitfld.long 0x0 26. "PCI_MSI_EXT_DATA_EN,Extended Message Data Enable. - If set the function is enabled to provide Extended Message Data. - If clear the function is not enabled to provide Extended Message Data. Note: The access attributes of this field are as follows: -.." "0,1" bitfld.long 0x0 25. "PCI_MSI_EXT_DATA_CAP,Extended Message Data Capable. - If set the function is capable of providing Extended Message Data. - If clear the function does not support providing Extended Message Data. Note: The access attributes of this field are as follows:.." "0,1" newline rbitfld.long 0x0 24. "PCI_PVM_SUPPORT,Per-Vector Masking Capable. - If set the function supports MSI Per-Vector Masking. - If clear the function does not support MSI Per-Vector Masking. This bit must be set if the function is a PF or VF within an SR-IOV Device." "0,1" bitfld.long 0x0 23. "PCI_MSI_64_BIT_ADDR_CAP,64 bit address capable. - If set the function is capable of sending a 64-bit message address. - If clear the function is not capable of sending a 64-bit message address. This bit must be set if the function is a PCI Express.." "0,1" bitfld.long 0x0 20.--22. "PCI_MSI_MULTIPLE_MSG_EN,Multiple Message Enable. Software writes to this field to indicate the number of allocated vectors (equal to or less than the number of requested vectors). The number of allocated vectors is aligned to a power of two. If a.." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 17.--19. "PCI_MSI_MULTIPLE_MSG_CAP,Multiple Message Capable. System software reads this field to determine the number of requested vectors. The number of requested vectors must be aligned to a power of two (if a function requires three vectors it requests four by.." "0,1,2,3,4,5,6,7" bitfld.long 0x0 16. "PCI_MSI_ENABLE,MSI Enable. - If set and the MSI-X Enable bit in the MSI-X Message Control register is clear the function is permitted to use MSI to request service and is prohibited from using INTx interrupts. System configuration software sets this bit.." "0,1" hexmask.long.byte 0x0 8.--15. 1. "PCI_MSI_CAP_NEXT_OFFSET,Next Capability Pointer. This field contains the offset to the next PCI Capability structure or 00h if no other items exist in the linked list of Capabilities. Note: The access attributes of this field are as follows: - Wire: No.." newline hexmask.long.byte 0x0 0.--7. 1. "PCI_MSI_CAP_ID,Capability ID. Indicates the MSI Capability structure. This field returns a Capability ID of 05h indicating that this is an MSI Capability structure." line.long 0x4 "MSI_CAP_OFF_04H_REG,Message Address Register for MSI (Offset 04h)." hexmask.long 0x4 2.--31. 1. "PCI_MSI_CAP_OFF_04H,Message Address - System-specified message address. If the Message Enable bit (bit 16 of the PCI_MSI_CAP_ID_NEXT_CTRL_REG register) is set the contents of this field specify the DWORD-aligned address (Address[31:02]) for the MSI.." rbitfld.long 0x4 0.--1. "RSVDP_0,Reserved for future use." "0,1,2,3" line.long 0x8 "MSI_CAP_OFF_08H_REG,For a function that supports a 32-bit message address. - bits[31:16] of this register represent the Extended Message Data. and - bits[15:0] of this register represent the Message Data For a function that supports a 64-bit message.." hexmask.long.word 0x8 16.--31. 1. "PCI_MSI_CAP_OFF_0AH,For a function that supports a 32-bit message address this field contains Extended Message Data (System-specified message data). For the MSI Capability structures without per-vector masking it must be implemented if the Extended.." hexmask.long.word 0x8 0.--15. 1. "PCI_MSI_CAP_OFF_08H,For a function that supports a 32-bit message address this field contains Message Data (System-specified message data). If the Message Enable bit (bit 16 of the PCI_MSI_CAP_ID_NEXT_CTRL_REG) is set the function sends a DWORD Memory.." line.long 0xC "MSI_CAP_OFF_0CH_REG,For a function that supports a 32-bit message address. this register contains the Mask Bits when the Per-Vector Masking Capable bit (bit 24 of PCI_MSI_CAP_ID_NEXT_CTRL_REG) is set. For a function that supports a 64-bit message.." hexmask.long.word 0xC 16.--31. 1. "PCI_MSI_CAP_OFF_0EH,For a function that supports a 32-bit message address this field contains the upper Mask Bits when the Per Vector Masking Capable bit (PCI_MSI_CAP_ID_NEXT_CTRL_REG.PCI_PVM_SUPPORT) is set. For a function that supports a 64-bit.." hexmask.long.word 0xC 0.--15. 1. "PCI_MSI_CAP_OFF_0CH,For a function that supports a 32-bit message address this field contains the lower Mask Bits when the Per Vector Masking Capable bit (PCI_MSI_CAP_ID_NEXT_CTRL_REG.PCI_PVM_SUPPORT) is set. For a function that supports a 64-bit.." line.long 0x10 "MSI_CAP_OFF_10H_REG,For a function that supports a 32-bit message address. this register contains the Pending Bits when the Per-Vector Masking Capable bit (bit 24 of PCI_MSI_CAP_ID_NEXT_CTRL_REG) is set. For a function that supports a 64-bit message.." hexmask.long 0x10 0.--31. 1. "PCI_MSI_CAP_OFF_10H,Used for MSI when the Per Vector Masking Capable bit (PCI_MSI_CAP_ID_NEXT_CTRL_REG.PCI_PVM_SUPPORT) is set. For 32-bit contains Pending Bits. For 64-bit contains Mask Bits. For a description of this standard PCIe register field see.." rgroup.long (0x14+0x50)++0x3 line.long 0x0 "MSI_CAP_OFF_14H_REG,Pending Bits Register for MSI. This register is used for a function that supports a 64-bit message address when the Per-Vector Masking Capable bit (bit 24 of PCI_MSI_CAP_ID_NEXT_CTRL_REG) is set." hexmask.long 0x0 0.--31. 1. "PCI_MSI_CAP_OFF_14H,Pending Bits. For each pending bit that is set the function has a pending associated message." tree.end tree "PF0_DMA_CAP (DMA Port Logic Structure)" group.long (0x0+0xC8000)++0x3 line.long 0x0 "DMA_CTRL_DATA_ARB_PRIOR_OFF,DMA Arbitration Scheme for TRGT1 Interface. This register is used to control traffic priorities among various sources that are delivered to your application through TRGT1 where 0x0 represents the highest priority. - Non-DMA Rx.." hexmask.long.tbyte 0x0 12.--31. 1. "RSVDP_12,Reserved for future use." bitfld.long 0x0 9.--11. "RDBUFF_TRGT_WEIGHT,DMA Read Channel MWr Requests. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 6.--8. "RD_CTRL_TRGT_WEIGHT,DMA Read Channel MRd Requests. For LL element/descriptor access. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" "0,1,2,3,4,5,6,7" bitfld.long 0x0 3.--5. "WR_CTRL_TRGT_WEIGHT,DMA Write Channel MRd Requests. For DMA data requests and LL element/descriptor access. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 0.--2. "RTRGT1_WEIGHT,Non-DMA Rx Requests. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" "0,1,2,3,4,5,6,7" group.long (0x8+0xC8000)++0xB line.long 0x0 "DMA_CTRL_OFF,DMA Number of Channels Register." hexmask.long.byte 0x0 26.--31. 1. "RSVDP_26,Reserved for future use." bitfld.long 0x0 25. "DIS_C2W_CACHE_RD,Disable DMA Read Channels 'completion to memory write' context cache pre-fetch function. Note: For internal debugging only. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" "0,1" newline bitfld.long 0x0 24. "DIS_C2W_CACHE_WR,Disable DMA Write Channels 'completion to memory write' context cache pre-fetch function. Note: For internal debugging only. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" "0,1" hexmask.long.byte 0x0 20.--23. 1. "RSVDP_20,Reserved for future use." newline hexmask.long.byte 0x0 16.--19. 1. "NUM_DMA_RD_CHAN,Number of Read Channels. You can read this register to determine the number of read channels the DMA controller has been configured to support." hexmask.long.word 0x0 4.--15. 1. "RSVDP_4,Reserved for future use." newline hexmask.long.byte 0x0 0.--3. 1. "NUM_DMA_WR_CHAN,Number of Write Channels. You can read this register to determine the number of write channels the DMA controller has been configured to support." line.long 0x4 "DMA_WRITE_ENGINE_EN_OFF,DMA Write Engine Enable Register." hexmask.long.byte 0x4 24.--31. 1. "RSVDP_24,Reserved for future use." bitfld.long 0x4 23. "DMA_WRITE_ENGINE_EN_HSHAKE_CH7,Enable Handshake for DMA Write Engine Channel 7. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" "0,1" newline bitfld.long 0x4 22. "DMA_WRITE_ENGINE_EN_HSHAKE_CH6,Enable Handshake for DMA Write Engine Channel 6. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" "0,1" bitfld.long 0x4 21. "DMA_WRITE_ENGINE_EN_HSHAKE_CH5,Enable Handshake for DMA Write Engine Channel 5. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" "0,1" newline bitfld.long 0x4 20. "DMA_WRITE_ENGINE_EN_HSHAKE_CH4,Enable Handshake for DMA Write Engine Channel 4. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" "0,1" bitfld.long 0x4 19. "DMA_WRITE_ENGINE_EN_HSHAKE_CH3,Enable Handshake for DMA Write Engine Channel 3. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" "0,1" newline bitfld.long 0x4 18. "DMA_WRITE_ENGINE_EN_HSHAKE_CH2,Enable Handshake for DMA Write Engine Channel 2. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" "0,1" bitfld.long 0x4 17. "DMA_WRITE_ENGINE_EN_HSHAKE_CH1,Enable Handshake for DMA Write Engine Channel 1. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" "0,1" newline bitfld.long 0x4 16. "DMA_WRITE_ENGINE_EN_HSHAKE_CH0,Enable Handshake for DMA Write Engine Channel 0. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" "0,1" hexmask.long.word 0x4 1.--15. 1. "RSVDP_1,Reserved for future use." newline bitfld.long 0x4 0. "DMA_WRITE_ENGINE,DMA Write Engine Enable. - 1: Enable - 0: Disable (Soft Reset) For normal operation you must initially set this bit to '1' before any other software setup actions. You do not need to toggle or rewrite to this bit during normal.." "Disable,Enable" line.long 0x8 "DMA_WRITE_DOORBELL_OFF,DMA Write Doorbell Register." bitfld.long 0x8 31. "WR_STOP,Stop. Set in conjunction with the Doorbell Number field. The DMA write channel stops issuing requests sets the channel status to 'Stopped' and asserts the 'Abort' interrupt if it is enabled. Before setting the Stop bit you must read the.." "0,1" hexmask.long 0x8 3.--30. 1. "RSVDP_3,Reserved for future use." newline bitfld.long 0x8 0.--2. "WR_DOORBELL_NUM,Doorbell Number. You must write the channel number to this register to start the DMA write transfer for that channel. The DMA detects a write to this register field even if the value of this field does not change. You do not need to.." "0,1,2,3,4,5,6,7" group.long (0x18+0xC8000)++0x7 line.long 0x0 "DMA_WRITE_CHANNEL_ARB_WEIGHT_LOW_OFF,DMA Write Engine Channel Arbitration Weight Low Register. The 5-bit channel weight (for write channels 0-3) specifies the maximum number of TLP requests that the DMA can issue for that channel before it must return to.." hexmask.long.word 0x0 20.--31. 1. "RSVDP_20,Reserved for future use." hexmask.long.byte 0x0 15.--19. 1. "WRITE_CHANNEL3_WEIGHT,Channel 3 Weight. The weight is initialized by software before ringing the doorbell. The value is used by the channel weighted round robin arbiter to select the next channel read request. A value of '0' means that one TLP is issued.." newline hexmask.long.byte 0x0 10.--14. 1. "WRITE_CHANNEL2_WEIGHT,Channel 2 Weight. The weight is initialized by software before ringing the doorbell. The value is used by the channel weighted round robin arbiter to select the next channel read request. A value of '0' means that one TLP is issued.." hexmask.long.byte 0x0 5.--9. 1. "WRITE_CHANNEL1_WEIGHT,Channel 1 Weight. The weight is initialized by software before ringing the doorbell. The value is used by the channel weighted round robin arbiter to select the next channel read request. A value of '0' means that one TLP is issued.." newline hexmask.long.byte 0x0 0.--4. 1. "WRITE_CHANNEL0_WEIGHT,Channel 0 Weight. The weight is initialized by software before ringing the doorbell. The value is used by the channel weighted round robin arbiter to select the next channel read request. A value of '0' means that one TLP is issued.." line.long 0x4 "DMA_WRITE_CHANNEL_ARB_WEIGHT_HIGH_OFF,DMA Write Engine Channel Arbitration Weight High Register. The 5-bit channel weight (for write channels 4-7) specifies the maximum number of TLP requests that the DMA can issue for that channel before it must return.." hexmask.long.word 0x4 20.--31. 1. "RSVDP_20,Reserved for future use." hexmask.long.byte 0x4 15.--19. 1. "WRITE_CHANNEL7_WEIGHT,Channel 7 Weight. The weight is initialized by software before ringing the doorbell. The value is used by the channel weighted round robin arbiter to select the next channel read request. A value of '0' means that one TLP is issued.." newline hexmask.long.byte 0x4 10.--14. 1. "WRITE_CHANNEL6_WEIGHT,Channel 6 Weight. The weight is initialized by software before ringing the doorbell. The value is used by the channel weighted round robin arbiter to select the next channel read request. A value of '0' means that one TLP is issued.." hexmask.long.byte 0x4 5.--9. 1. "WRITE_CHANNEL5_WEIGHT,Channel 5 Weight. The weight is initialized by software before ringing the doorbell. The value is used by the channel weighted round robin arbiter to select the next channel read request. A value of '0' means that one TLP is issued.." newline hexmask.long.byte 0x4 0.--4. 1. "WRITE_CHANNEL4_WEIGHT,Channel 4 Weight. The weight is initialized by software before ringing the doorbell. The value is used by the channel weighted round robin arbiter to select the next channel read request. A value of '0' means that one TLP is issued.." group.long (0x2C+0xC8000)++0x7 line.long 0x0 "DMA_READ_ENGINE_EN_OFF,DMA Read Engine Enable Register." hexmask.long.byte 0x0 24.--31. 1. "RSVDP_24,Reserved for future use." bitfld.long 0x0 23. "DMA_READ_ENGINE_EN_HSHAKE_CH7,Enable Handshake for DMA Read Engine Channel 7. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" "0,1" newline bitfld.long 0x0 22. "DMA_READ_ENGINE_EN_HSHAKE_CH6,Enable Handshake for DMA Read Engine Channel 6. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" "0,1" bitfld.long 0x0 21. "DMA_READ_ENGINE_EN_HSHAKE_CH5,Enable Handshake for DMA Read Engine Channel 5. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" "0,1" newline bitfld.long 0x0 20. "DMA_READ_ENGINE_EN_HSHAKE_CH4,Enable Handshake for DMA Read Engine Channel 4. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" "0,1" bitfld.long 0x0 19. "DMA_READ_ENGINE_EN_HSHAKE_CH3,Enable Handshake for DMA Read Engine Channel 3. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" "0,1" newline bitfld.long 0x0 18. "DMA_READ_ENGINE_EN_HSHAKE_CH2,Enable Handshake for DMA Read Engine Channel 2. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" "0,1" bitfld.long 0x0 17. "DMA_READ_ENGINE_EN_HSHAKE_CH1,Enable Handshake for DMA Read Engine Channel 1. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" "0,1" newline bitfld.long 0x0 16. "DMA_READ_ENGINE_EN_HSHAKE_CH0,Enable Handshake for DMA Read Engine Channel 0. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" "0,1" hexmask.long.word 0x0 1.--15. 1. "RSVDP_1,Reserved for future use." newline bitfld.long 0x0 0. "DMA_READ_ENGINE,DMA Read Engine Enable. - 1: Enable - 0: Disable (Soft Reset) For normal operation you must initially set this bit to '1' before any other software setup actions. You do not need to toggle or rewrite to this bit during normal operation." "Disable,Enable" line.long 0x4 "DMA_READ_DOORBELL_OFF,DMA Read Doorbell Register." bitfld.long 0x4 31. "RD_STOP,Stop. Set in conjunction with the Doorbell Number field. The DMA read channel stops issuing requests sets the channel status to 'Stopped' and asserts the 'Abort' interrupt if it is enabled. Before setting the Stop bit you must read the channel.." "0,1" hexmask.long 0x4 3.--30. 1. "RSVDP_3,Reserved for future use." newline bitfld.long 0x4 0.--2. "RD_DOORBELL_NUM,Doorbell Number. You must write 0x0 to this register to start the DMA read transfer for that channel. The DMA detects a write to this register field even if the value of this field does not change. The range of this field is 0x0 to 0x7.." "0,1,2,3,4,5,6,7" group.long (0x38+0xC8000)++0x7 line.long 0x0 "DMA_READ_CHANNEL_ARB_WEIGHT_LOW_OFF,DMA Read Engine Channel Arbitration Weight Low Register. The 5-bit channel weight (for read channels 0-3) specifies the maximum number of TLP requests that the DMA can issue for that channel before it must return to.." hexmask.long.word 0x0 20.--31. 1. "RSVDP_20,Reserved for future use." hexmask.long.byte 0x0 15.--19. 1. "READ_CHANNEL3_WEIGHT,Channel 3 Weight. The weight is initialized by software before ringing the doorbell. The value is used by the channel weighted round robin arbiter to select the next channel read request. Note: The access attributes of this field are.." newline hexmask.long.byte 0x0 10.--14. 1. "READ_CHANNEL2_WEIGHT,Channel 2 Weight. The weight is initialized by software before ringing the doorbell. The value is used by the channel weighted round robin arbiter to select the next channel read request. Note: The access attributes of this field are.." hexmask.long.byte 0x0 5.--9. 1. "READ_CHANNEL1_WEIGHT,Channel 1 Weight. The weight is initialized by software before ringing the doorbell. The value is used by the channel weighted round robin arbiter to select the next channel read request. Note: The access attributes of this field are.." newline hexmask.long.byte 0x0 0.--4. 1. "READ_CHANNEL0_WEIGHT,Channel 0 Weight. The weight is initialized by software before ringing the doorbell. The value is used by the channel weighted round robin arbiter to select the next channel read request. Note: The access attributes of this field are.." line.long 0x4 "DMA_READ_CHANNEL_ARB_WEIGHT_HIGH_OFF,DMA Read Engine Channel Arbitration Weight High Register. The 5-bit channel weight (for read channels 4-7) specifies the maximum number of TLP requests that the DMA can issue for that channel before it must return to.." hexmask.long.word 0x4 20.--31. 1. "RSVDP_20,Reserved for future use." hexmask.long.byte 0x4 15.--19. 1. "READ_CHANNEL7_WEIGHT,Channel 7 Weight. The weight is initialized by software before ringing the doorbell. The value is used by the channel weighted round robin arbiter to select the next channel read request. Note: The access attributes of this field are.." newline hexmask.long.byte 0x4 10.--14. 1. "READ_CHANNEL6_WEIGHT,Channel 6 Weight. The weight is initialized by software before ringing the doorbell. The value is used by the channel weighted round robin arbiter to select the next channel read request. Note: The access attributes of this field are.." hexmask.long.byte 0x4 5.--9. 1. "READ_CHANNEL5_WEIGHT,Channel 5 Weight. The weight is initialized by software before ringing the doorbell. The value is used by the channel weighted round robin arbiter to select the next channel read request. Note: The access attributes of this field are.." newline hexmask.long.byte 0x4 0.--4. 1. "READ_CHANNEL4_WEIGHT,Channel 4 Weight. The weight is initialized by software before ringing the doorbell. The value is used by the channel weighted round robin arbiter to select the next channel read request. Note: The access attributes of this field are.." group.long (0x4C+0xC8000)++0x3 line.long 0x0 "DMA_WRITE_INT_STATUS_OFF,DMA Write Interrupt Status Register." hexmask.long.byte 0x0 24.--31. 1. "RSVDP_24,Reserved for future use." hexmask.long.byte 0x0 16.--23. 1. "WR_ABORT_INT_STATUS,Abort Interrupt Status. The DMA write channel has detected an error or you manually stopped the transfer as described in 'Error Handling Assistance by Remote Software'. Each bit corresponds to a DMA channel. Bit [0] corresponds to.." newline hexmask.long.byte 0x0 8.--15. 1. "RSVDP_8,Reserved for future use." hexmask.long.byte 0x0 0.--7. 1. "WR_DONE_INT_STATUS,Done Interrupt Status. The DMA write channel has successfully completed the DMA transfer. For more details see 'Interrupts and Error Handling'. Each bit corresponds to a DMA channel. Bit [0] corresponds to channel 0. - Enabling: For.." group.long (0x54+0xC8000)++0x7 line.long 0x0 "DMA_WRITE_INT_MASK_OFF,DMA Write Interrupt Mask Register." hexmask.long.byte 0x0 24.--31. 1. "RSVDP_24,Reserved for future use." hexmask.long.byte 0x0 16.--23. 1. "WR_ABORT_INT_MASK,Abort Interrupt Mask. Prevents the Abort interrupt status field in the DMA write interrupt status register from asserting the edma_int output. Each bit corresponds to a DMA channel. Bit [0] corresponds to channel 0. Note: The access.." newline hexmask.long.byte 0x0 8.--15. 1. "RSVDP_8,Reserved for future use." hexmask.long.byte 0x0 0.--7. 1. "WR_DONE_INT_MASK,Done Interrupt Mask. Prevents the Done interrupt status field in the DMA write interrupt status register from asserting the edma_int output. Each bit corresponds to a DMA channel. Bit [0] corresponds to channel 0. Note: The access.." line.long 0x4 "DMA_WRITE_INT_CLEAR_OFF,DMA Write Interrupt Clear Register." hexmask.long.byte 0x4 24.--31. 1. "RSVDP_24,Reserved for future use." hexmask.long.byte 0x4 16.--23. 1. "WR_ABORT_INT_CLEAR,Abort Interrupt Clear. You must write a 1'b1 to clear the corresponding bit in the Abort interrupt status field of the DMA write interrupt status register. Each bit corresponds to a DMA channel. Bit [0] corresponds to channel 0. Note:.." newline hexmask.long.byte 0x4 8.--15. 1. "RSVDP_8,Reserved for future use." hexmask.long.byte 0x4 0.--7. 1. "WR_DONE_INT_CLEAR,Done Interrupt Clear. You must write a 1'b1 to clear the corresponding bit in the Done interrupt status field of the DMA write interrupt status register. Each bit corresponds to a DMA channel. Bit [0] corresponds to channel 0. Note:.." rgroup.long (0x5C+0xC8000)++0x3 line.long 0x0 "DMA_WRITE_ERR_STATUS_OFF,DMA Write Error Status Register" hexmask.long.byte 0x0 24.--31. 1. "RSVDP_24,Reserved for future use." hexmask.long.byte 0x0 16.--23. 1. "LINKLIST_ELEMENT_FETCH_ERR_DETECT,Linked List Element Fetch Error Detected. The DMA write channel has received an error response from the AXI bus (or TRGT1 interface when the AXI Bridge is not used) while reading a linked list element from local memory." newline hexmask.long.byte 0x0 8.--15. 1. "RSVDP_8,Reserved for future use." hexmask.long.byte 0x0 0.--7. 1. "APP_READ_ERR_DETECT,Application Read Error Detected. The DMA write channel has received an error response from the AXI bus (or TRGT1 interface when the AXI Bridge is not used) while reading data from it. Each bit corresponds to a DMA channel. Bit [0].." group.long (0x60+0xC8000)++0x1F line.long 0x0 "DMA_WRITE_DONE_IMWR_LOW_OFF,DMA Write Done IMWr Address Low Register." hexmask.long 0x0 0.--31. 1. "DMA_WRITE_DONE_LOW_REG,The DMA uses this field to generate bits [31:0] of the address field for the Done IMWr TLP. Bits [1:0] must be '00' as this address must be dword aligned. Note: The access attributes of this field are as follows: - Wire: No access." line.long 0x4 "DMA_WRITE_DONE_IMWR_HIGH_OFF,DMA Write Done IMWr Interrupt Address High Register." hexmask.long 0x4 0.--31. 1. "DMA_WRITE_DONE_HIGH_REG,The DMA uses this field to generate bits [63:32] of the address field for the Done IMWr TLP. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" line.long 0x8 "DMA_WRITE_ABORT_IMWR_LOW_OFF,DMA Write Abort IMWr Address Low Register." hexmask.long 0x8 0.--31. 1. "DMA_WRITE_ABORT_LOW_REG,The DMA uses this field to generate bits [31:0] of the address field for the Abort IMWr TLP it generates. Bits [1:0] must be '00' as this address must be dword aligned. Note: The access attributes of this field are as follows: -.." line.long 0xC "DMA_WRITE_ABORT_IMWR_HIGH_OFF,DMA Write Abort IMWr Address High Register." hexmask.long 0xC 0.--31. 1. "DMA_WRITE_ABORT_HIGH_REG,The DMA uses this field to generate bits [63:32] of the address field for the Abort IMWr TLP. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" line.long 0x10 "DMA_WRITE_CH01_IMWR_DATA_OFF,DMA Write Channel 1 and 0 IMWr Data Register." hexmask.long.word 0x10 16.--31. 1. "WR_CHANNEL_1_DATA,The DMA uses this field to generate the data field for the Done or Abort IMWr TLPs it generates for write channel 1. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" hexmask.long.word 0x10 0.--15. 1. "WR_CHANNEL_0_DATA,The DMA uses this field to generate the data field for the Done or Abort IMWr TLPs it generates for write channel 0. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" line.long 0x14 "DMA_WRITE_CH23_IMWR_DATA_OFF,DMA Write Channel 3 and 2 IMWr Data Register." hexmask.long.word 0x14 16.--31. 1. "WR_CHANNEL_3_DATA,The DMA uses this field to generate the data field for the Done or Abort IMWr TLPs it generates for write channel 3. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" hexmask.long.word 0x14 0.--15. 1. "WR_CHANNEL_2_DATA,The DMA uses this field to generate the data field for the Done or Abort IMWr TLPs it generates for write channel 2. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" line.long 0x18 "DMA_WRITE_CH45_IMWR_DATA_OFF,DMA Write Channel 5 and 4 IMWr Data Register." hexmask.long.word 0x18 16.--31. 1. "WR_CHANNEL_5_DATA,The DMA uses this field to generate the data field for the Done or Abort IMWr TLPs it generates for write channel 5. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" hexmask.long.word 0x18 0.--15. 1. "WR_CHANNEL_4_DATA,The DMA uses this field to generate the data field for the Done or Abort IMWr TLPs it generates for write channel 4. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" line.long 0x1C "DMA_WRITE_CH67_IMWR_DATA_OFF,DMA Write Channel 7 and 6 IMWr Data Register." hexmask.long.word 0x1C 16.--31. 1. "WR_CHANNEL_7_DATA,The DMA uses this field to generate the data field for the Done or Abort IMWr TLPs it generates for write channel 7. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" hexmask.long.word 0x1C 0.--15. 1. "WR_CHANNEL_6_DATA,The DMA uses this field to generate the data field for the Done or Abort IMWr TLPs it generates for write channel 6. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" group.long (0x90+0xC8000)++0x3 line.long 0x0 "DMA_WRITE_LINKED_LIST_ERR_EN_OFF,DMA Write Linked List Error Enable Register. The LIE and RIE bits in the LL element enable the channel 'done' interrupts (local and remote). The LLLAIE and LLRAIE bits enable the channel 'abort' interrupts (local and.." hexmask.long.byte 0x0 24.--31. 1. "RSVDP_24,Reserved for future use." hexmask.long.byte 0x0 16.--23. 1. "WR_CHANNEL_LLLAIE,Write Channel LL Local Abort Interrupt Enable (LLLAIE). You enable the write channel local abort interrupt through this bit. The LIE and RIE bits in the LL element enable the write channel done interrupts. Each bit corresponds to a DMA.." newline hexmask.long.byte 0x0 8.--15. 1. "RSVDP_8,Reserved for future use." hexmask.long.byte 0x0 0.--7. 1. "WR_CHANNEL_LLRAIE,Write Channel LL Remote Abort Interrupt Enable (LLRAIE). You enable the write channel remote abort interrupt through this bit. The LIE and RIE bits in the LL element enable the write channel done interrupts. Each bit corresponds to a.." group.long (0xA0+0xC8000)++0x3 line.long 0x0 "DMA_READ_INT_STATUS_OFF,DMA Read Interrupt Status Register." hexmask.long.byte 0x0 24.--31. 1. "RSVDP_24,Reserved for future use." hexmask.long.byte 0x0 16.--23. 1. "RD_ABORT_INT_STATUS,Abort Interrupt Status. The DMA read channel has detected an error or you manually stopped the transfer as described in 'Stopping the DMA Transfer (Software Stop)'. Each bit corresponds to a DMA channel. Bit [0] corresponds to.." newline hexmask.long.byte 0x0 8.--15. 1. "RSVDP_8,Reserved for future use." hexmask.long.byte 0x0 0.--7. 1. "RD_DONE_INT_STATUS,Done Interrupt Status. The DMA read channel has successfully completed the DMA read transfer. Each bit corresponds to a DMA channel. Bit [0] corresponds to channel 0. - Enabling: For details see 'Interrupts and Error Handling'. -.." group.long (0xA8+0xC8000)++0x7 line.long 0x0 "DMA_READ_INT_MASK_OFF,DMA Read Interrupt Mask Register." hexmask.long.byte 0x0 24.--31. 1. "RSVDP_24,Reserved for future use." hexmask.long.byte 0x0 16.--23. 1. "RD_ABORT_INT_MASK,Abort Interrupt Mask. Prevents the Abort interrupt status field in the DMA read interrupt status register from asserting the edma_int output. Each bit corresponds to a DMA channel. Bit [0] corresponds to channel 0. Note: The access.." newline hexmask.long.byte 0x0 8.--15. 1. "RSVDP_8,Reserved for future use." hexmask.long.byte 0x0 0.--7. 1. "RD_DONE_INT_MASK,Done Interrupt Mask. Prevents the Done interrupt status field in the DMA read interrupt status register from asserting the edma_int output. Each bit corresponds to a DMA channel. Bit [0] corresponds to channel 0. Note: The access.." line.long 0x4 "DMA_READ_INT_CLEAR_OFF,DMA Read Interrupt Clear Register." hexmask.long.byte 0x4 24.--31. 1. "RSVDP_24,Reserved for future use." hexmask.long.byte 0x4 16.--23. 1. "RD_ABORT_INT_CLEAR,Abort Interrupt Clear. You must write a 1'b1 to clear the corresponding bit in the Abort interrupt status field of the DMA read interrupt status register. Each bit corresponds to a DMA channel. Bit [0] corresponds to channel 0. Note:.." newline hexmask.long.byte 0x4 8.--15. 1. "RSVDP_8,Reserved for future use." hexmask.long.byte 0x4 0.--7. 1. "RD_DONE_INT_CLEAR,Done Interrupt Clear. You must write a 1'b1 to clear the corresponding bit in the Done interrupt status field of the DMA read interrupt status register. Each bit corresponds to a DMA channel. Bit [0] corresponds to channel 0. Note:.." rgroup.long (0xB4+0xC8000)++0x7 line.long 0x0 "DMA_READ_ERR_STATUS_LOW_OFF,DMA Read Error Status Low Register." hexmask.long.byte 0x0 24.--31. 1. "RSVDP_24,Reserved for future use." hexmask.long.byte 0x0 16.--23. 1. "LINK_LIST_ELEMENT_FETCH_ERR_DETECT,Linked List Element Fetch Error Detected. - The DMA read channel has received an error response from the AXI bus while reading a linked list element from local memory. Each bit corresponds to a DMA channel. Bit [0].." newline hexmask.long.byte 0x0 8.--15. 1. "RSVDP_8,Reserved for future use." hexmask.long.byte 0x0 0.--7. 1. "APP_WR_ERR_DETECT,Application Write Error Detected. The DMA read channel has received an error response from the AXI bus (or TRGT1 interface when the AXI Bridge is not used) while writing data to it. This error is fatal. You must restart the transfer.." line.long 0x4 "DMA_READ_ERR_STATUS_HIGH_OFF,DMA Read Error Status High Register." hexmask.long.byte 0x4 24.--31. 1. "DATA_POISIONING,Data Poisoning. The DMA read channel has detected data poisoning in the completion from the remote device (in response to the MRd request). The DMA read channel will drop the completion and then be halted. The CX_FLT_MASK_UR_POIS filter.." hexmask.long.byte 0x4 16.--23. 1. "CPL_TIMEOUT,Completion Time Out. The DMA read channel has timed-out while waiting for the remote device to respond to the MRd request or a malformed CplD has been received. For more details see 'Linked List Mode'. Each bit corresponds to a DMA channel." newline hexmask.long.byte 0x4 8.--15. 1. "CPL_ABORT,Completer Abort. The DMA read channel has received a PCIe completer abort completion status from the remote device in response to the MRd request. For more details see 'Linked List Mode'. Each bit corresponds to a DMA channel. Bit [0].." hexmask.long.byte 0x4 0.--7. 1. "UNSUPPORTED_REQ,Unsupported Request. The DMA read channel has received a PCIe unsupported request completion status from the remote device in response to the MRd request. For more details see 'Linked List Mode'. Each bit corresponds to a DMA channel." group.long (0xC4+0xC8000)++0x3 line.long 0x0 "DMA_READ_LINKED_LIST_ERR_EN_OFF,DMA Read Linked List Error Enable Register. The LIE and RIE bits in the LL element enable the channel 'done' interrupts (local and remote). The LLLAIE and LLRAIE bits enable the channel 'abort' interrupts (local and remote)." hexmask.long.byte 0x0 24.--31. 1. "RSVDP_24,Reserved for future use." hexmask.long.byte 0x0 16.--23. 1. "RD_CHANNEL_LLLAIE,Read Channel LL Local Abort Interrupt Enable (LLLAIE). You enable the read channel Local Abort interrupt through this bit. The LIE and RIE bits in the LL element enable the read channel done interrupts. Each bit corresponds to a DMA.." newline hexmask.long.byte 0x0 8.--15. 1. "RSVDP_8,Reserved for future use." hexmask.long.byte 0x0 0.--7. 1. "RD_CHANNEL_LLRAIE,Read Channel LL Remote Abort Interrupt Enable (LLRAIE). You enable the read channel Remote Abort interrupt through this bit. The LIE and RIE bits in the LL element enable the read channel done interrupts. Each bit corresponds to a DMA.." group.long (0xCC+0xC8000)++0x1F line.long 0x0 "DMA_READ_DONE_IMWR_LOW_OFF,DMA Read Done IMWr Address Low Register." hexmask.long 0x0 0.--31. 1. "DMA_READ_DONE_LOW_REG,The DMA uses this field to generate bits [31:0] of the address field for the Done IMWr TLP. Bits [1:0] must be '00' as this address must be dword aligned. Note: The access attributes of this field are as follows: - Wire: No access." line.long 0x4 "DMA_READ_DONE_IMWR_HIGH_OFF,DMA Read Done IMWr Address High Register." hexmask.long 0x4 0.--31. 1. "DMA_READ_DONE_HIGH_REG,The DMA uses this field to generate bits [63:32] of the address field for the Done IMWr TLP. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" line.long 0x8 "DMA_READ_ABORT_IMWR_LOW_OFF,DMA Read Abort IMWr Address Low Register." hexmask.long 0x8 0.--31. 1. "DMA_READ_ABORT_LOW_REG,The DMA uses this field to generate bits [31:0] of the address field for the Abort IMWr TLP. Bits [1:0] must be '00' as this address must be dword aligned. Note: The access attributes of this field are as follows: - Wire: No.." line.long 0xC "DMA_READ_ABORT_IMWR_HIGH_OFF,DMA Read Abort IMWr Address High Register." hexmask.long 0xC 0.--31. 1. "DMA_READ_ABORT_HIGH_REG,The DMA uses this field to generate bits [63:32] of the address field for the Abort IMWr TLP. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" line.long 0x10 "DMA_READ_CH01_IMWR_DATA_OFF,DMA Read Channel 1 and 0 IMWr Data Register." hexmask.long.word 0x10 16.--31. 1. "RD_CHANNEL_1_DATA,The DMA uses this field to generate the data field for the Done or Abort IMWr TLPs it generates for read channel 1. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" hexmask.long.word 0x10 0.--15. 1. "RD_CHANNEL_0_DATA,The DMA uses this field to generate the data field for the Done or Abort IMWr TLPs it generates for read channel 0. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" line.long 0x14 "DMA_READ_CH23_IMWR_DATA_OFF,DMA Read Channel 3 and 2 IMWr Data Register." hexmask.long.word 0x14 16.--31. 1. "RD_CHANNEL_3_DATA,The DMA uses this field to generate the data field for the Done or Abort IMWr TLPs it generates for read channel 3. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" hexmask.long.word 0x14 0.--15. 1. "RD_CHANNEL_2_DATA,The DMA uses this field to generate the data field for the Done or Abort IMWr TLPs it generates for read channel 2. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" line.long 0x18 "DMA_READ_CH45_IMWR_DATA_OFF,DMA Read Channel 5 and 4 IMWr Data Register." hexmask.long.word 0x18 16.--31. 1. "RD_CHANNEL_5_DATA,The DMA uses this field to generate the data field for the Done or Abort IMWr TLPs it generates for read channel 5. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" hexmask.long.word 0x18 0.--15. 1. "RD_CHANNEL_4_DATA,The DMA uses this field to generate the data field for the Done or Abort IMWr TLPs it generates for read channel 4. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" line.long 0x1C "DMA_READ_CH67_IMWR_DATA_OFF,DMA Read Channel 7 and 6 IMWr Data Register." hexmask.long.word 0x1C 16.--31. 1. "RD_CHANNEL_7_DATA,The DMA uses this field to generate the data field for the Done or Abort IMWr TLPs it generates for read channel 7. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" hexmask.long.word 0x1C 0.--15. 1. "RD_CHANNEL_6_DATA,The DMA uses this field to generate the data field for the Done or Abort IMWr TLPs it generates for read channel 6. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" rgroup.long (0x108+0xC8000)++0x7 line.long 0x0 "DMA_WRITE_ENGINE_HSHAKE_CNT_LOW_OFF,DMA Write Engine Handshake Counter Channel 0/1/2/3 Register." bitfld.long 0x0 29.--31. "RSVDP_29,Reserved for future use." "0,1,2,3,4,5,6,7" hexmask.long.byte 0x0 24.--28. 1. "DMA_WRITE_ENGINE_HSHAKE_CNT_CH3,DMA handshake counter for DMA Write Engine Channel 3. If CC_DMA_HSHAKE =1 the data transfer in Linked List mode starts only when the counter is non-zero." newline bitfld.long 0x0 21.--23. "RSVDP_21,Reserved for future use." "0,1,2,3,4,5,6,7" hexmask.long.byte 0x0 16.--20. 1. "DMA_WRITE_ENGINE_HSHAKE_CNT_CH2,DMA handshake counter for DMA Write Engine Channel 2. If CC_DMA_HSHAKE =1 the data transfer in Linked List mode starts only when the counter is non-zero." newline bitfld.long 0x0 13.--15. "RSVDP_13,Reserved for future use." "0,1,2,3,4,5,6,7" hexmask.long.byte 0x0 8.--12. 1. "DMA_WRITE_ENGINE_HSHAKE_CNT_CH1,DMA handshake counter for DMA Write Engine Channel 1. If CC_DMA_HSHAKE =1 the data transfer in Linked List mode starts only when the counter is non-zero." newline bitfld.long 0x0 5.--7. "RSVDP_5,Reserved for future use." "0,1,2,3,4,5,6,7" hexmask.long.byte 0x0 0.--4. 1. "DMA_WRITE_ENGINE_HSHAKE_CNT_CH0,DMA handshake counter for DMA Write Engine Channel 0. If CC_DMA_HSHAKE =1 the data transfer in Linked List mode starts only when the counter is non-zero." line.long 0x4 "DMA_WRITE_ENGINE_HSHAKE_CNT_HIGH_OFF,DMA Write Engine Handshake Counter Channel 4/5/6/7 Register." bitfld.long 0x4 29.--31. "RSVDP_29,Reserved for future use." "0,1,2,3,4,5,6,7" hexmask.long.byte 0x4 24.--28. 1. "DMA_WRITE_ENGINE_HSHAKE_CNT_CH7,DMA handshake counter for DMA Write Engine Channel 7. If CC_DMA_HSHAKE =1 the data transfer in Linked List mode starts only when the counter is non-zero." newline bitfld.long 0x4 21.--23. "RSVDP_21,Reserved for future use." "0,1,2,3,4,5,6,7" hexmask.long.byte 0x4 16.--20. 1. "DMA_WRITE_ENGINE_HSHAKE_CNT_CH6,DMA handshake counter for DMA Write Engine Channel 6. If CC_DMA_HSHAKE =1 the data transfer in Linked List mode starts only when the counter is non-zero." newline bitfld.long 0x4 13.--15. "RSVDP_13,Reserved for future use." "0,1,2,3,4,5,6,7" hexmask.long.byte 0x4 8.--12. 1. "DMA_WRITE_ENGINE_HSHAKE_CNT_CH5,DMA handshake counter for DMA Write Engine Channel 5. If CC_DMA_HSHAKE =1 the data transfer in Linked List mode starts only when the counter is non-zero." newline bitfld.long 0x4 5.--7. "RSVDP_5,Reserved for future use." "0,1,2,3,4,5,6,7" hexmask.long.byte 0x4 0.--4. 1. "DMA_WRITE_ENGINE_HSHAKE_CNT_CH4,DMA handshake counter for DMA Write Engine Channel 4. If CC_DMA_HSHAKE =1 the data transfer in Linked List mode starts only when the counter is non-zero." rgroup.long (0x118+0xC8000)++0x7 line.long 0x0 "DMA_READ_ENGINE_HSHAKE_CNT_LOW_OFF,DMA Read Engine Handshake Counter Channel 0/1/2/3 Register." bitfld.long 0x0 29.--31. "RSVDP_29,Reserved for future use." "0,1,2,3,4,5,6,7" hexmask.long.byte 0x0 24.--28. 1. "DMA_READ_ENGINE_HSHAKE_CNT_CH3,DMA handshake counter for DMA Read Engine Channel 3. If CC_DMA_HSHAKE =1 the data transfer in Linked List mode starts only when the counter is non-zero." newline bitfld.long 0x0 21.--23. "RSVDP_21,Reserved for future use." "0,1,2,3,4,5,6,7" hexmask.long.byte 0x0 16.--20. 1. "DMA_READ_ENGINE_HSHAKE_CNT_CH2,DMA handshake counter for DMA Read Engine Channel 2. If CC_DMA_HSHAKE =1 the data transfer in Linked List mode starts only when the counter is non-zero." newline bitfld.long 0x0 13.--15. "RSVDP_13,Reserved for future use." "0,1,2,3,4,5,6,7" hexmask.long.byte 0x0 8.--12. 1. "DMA_READ_ENGINE_HSHAKE_CNT_CH1,DMA handshake counter for DMA Read Engine Channel 1. If CC_DMA_HSHAKE =1 the data transfer in Linked List mode starts only when the counter is non-zero." newline bitfld.long 0x0 5.--7. "RSVDP_5,Reserved for future use." "0,1,2,3,4,5,6,7" hexmask.long.byte 0x0 0.--4. 1. "DMA_READ_ENGINE_HSHAKE_CNT_CH0,DMA handshake counter for DMA Read Engine Channel 0. If CC_DMA_HSHAKE =1 the data transfer in Linked List mode starts only when the counter is non-zero." line.long 0x4 "DMA_READ_ENGINE_HSHAKE_CNT_HIGH_OFF,DMA Read Engine Handshake Counter Channel 4/5/6/7 Register." bitfld.long 0x4 29.--31. "RSVDP_29,Reserved for future use." "0,1,2,3,4,5,6,7" hexmask.long.byte 0x4 24.--28. 1. "DMA_READ_ENGINE_HSHAKE_CNT_CH7,DMA handshake counter for DMA Read Engine Channel 7. If CC_DMA_HSHAKE =1 the data transfer in Linked List mode starts only when the counter is non-zero." newline bitfld.long 0x4 21.--23. "RSVDP_21,Reserved for future use." "0,1,2,3,4,5,6,7" hexmask.long.byte 0x4 16.--20. 1. "DMA_READ_ENGINE_HSHAKE_CNT_CH6,DMA handshake counter for DMA Read Engine Channel 6. If CC_DMA_HSHAKE =1 the data transfer in Linked List mode starts only when the counter is non-zero." newline bitfld.long 0x4 13.--15. "RSVDP_13,Reserved for future use." "0,1,2,3,4,5,6,7" hexmask.long.byte 0x4 8.--12. 1. "DMA_READ_ENGINE_HSHAKE_CNT_CH5,DMA handshake counter for DMA Read Engine Channel 5. If CC_DMA_HSHAKE =1 the data transfer in Linked List mode starts only when the counter is non-zero." newline bitfld.long 0x4 5.--7. "RSVDP_5,Reserved for future use." "0,1,2,3,4,5,6,7" hexmask.long.byte 0x4 0.--4. 1. "DMA_READ_ENGINE_HSHAKE_CNT_CH4,DMA handshake counter for DMA Read Engine Channel 4. If CC_DMA_HSHAKE =1 the data transfer in Linked List mode starts only when the counter is non-zero." repeat 8. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 )(list 0x0 0x200 0x400 0x600 0x800 0xA00 0xC00 0xE00 ) group.long ($2+0x200+0xC8000)++0x3 line.long 0x0 "DMA_CH_CONTROL1_OFF_WRCH_$1,DMA Write Channel Control 1 Register." bitfld.long 0x0 30.--31. "DMA_AT,Address Translation TLP Header Bit (AT) The DMA uses this TLP header field when generating MRd/MWr (not IMWr) TLPs. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" "0,1,2,3" bitfld.long 0x0 27.--29. "DMA_TC,Traffic Class TLP Header Bit (TC) The DMA uses this TLP header field when generating MRd/MWr (not IMWr) TLPs. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 26. "DMA_RESERVED5,Reserved. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" "0,1" bitfld.long 0x0 25. "DMA_RO,Relaxed Ordering TLP Header Bit (RO) The DMA uses this TLP header field when generating MRd/MWr (not IMWr) TLPs. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" "0,1" newline bitfld.long 0x0 24. "DMA_NS_SRC,Source No Snoop TLP Header Bit (DMA_NS_SRC). The DMA uses this TLP header field when generating MRd (SAR addressing space) (not IMWr) TLPs. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" "0,1" bitfld.long 0x0 23. "DMA_NS_DST,Destination No Snoop TLP Header Bit (DMA_NS_DST). The DMA uses this TLP header field when generating MWr (DAR addressing space) (not IMWr) TLPs. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" "0,1" newline bitfld.long 0x0 22. "DMA_MEM_TYPE,Master AXI ACE-Lite Cache Coherency Control. This field sets the DMA channel memory type of the address space of the data transfer as follows: - 0x0:peripheral type - 0x1:memory type For more details see 'ACE-Lite Features and Limitations'.." "peripheral type,memory type" hexmask.long.byte 0x0 17.--21. 1. "DMA_RESERVED2,Reserved. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" newline hexmask.long.byte 0x0 12.--16. 1. "DMA_FUNC_NUM,Function Number (FN). The controller uses this field when generating the requester ID for the MRd/MWr DMA TLP. When you have enabled SR-IOV then this field is ignored if you have set the VFE field in the 'DMA Write Channel Control 2.." bitfld.long 0x0 10.--11. "DMA_RESERVED1,Reserved. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" "0,1,2,3" newline bitfld.long 0x0 9. "LLE,Linked List Enable (LLE). - 0: Disable linked list operation - 1: Enable linked list operation Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" "Disable linked list operation,Enable linked list operation" bitfld.long 0x0 8. "CCS,Consumer Cycle State (CCS). Used in linked list mode only. It is used to synchronize the producer (software) and the consumer (DMA). For more details see 'PCS-CCS-CB-TCB Producer-Consumer Synchronization'. You must initialize this bit. The DMA.." "0,1" newline bitfld.long 0x0 7. "DMA_RESERVED0,Reserved. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" "0,1" bitfld.long 0x0 5.--6. "CS,Channel Status (CS). The channel status bits identify the current operational state of the DMA channel. The operation state encoding for each DMA channel is a s follows: - 00: Reserved - 01: Running. This channel is active and transferring data. - 10:.." "Reserved,Running,?,?" newline bitfld.long 0x0 4. "RIE,Remote Interrupt Enable (RIE). You must set this bit to enable the generation of the Done or Abort Remote interrupts. For more details see 'Interrupts and Error Handling'. In LL mode the DMA overwrites this with the RIE of the LL element. The RIE.." "0,1" bitfld.long 0x0 3. "LIE,Local Interrupt Enable (LIE). You must set this bit to enable the generation of the Done or Abort Local interrupts. For more details see 'Interrupts and Error Handling'. In LL mode the DMA overwrites this with the LIE of the LL element. The LIE bit.." "0,1" newline bitfld.long 0x0 2. "LLP,Load Link Pointer (LLP). Used in linked list mode only. Indicates that this linked list element is a link element and its LL element pointer dwords are pointing to the next (non-contiguous) element. The DMA loads this field with the LLP of the.." "0,1" bitfld.long 0x0 1. "TCB,Toggle Cycle Bit (TCB). Indicates to the DMA to toggle its interpretation of the CB. Used in linked list mode only. It is used to synchronize the producer (software) and the consumer (DMA). For more details see 'PCS-CCS-CB-TCB Producer-Consumer.." "0,1" newline bitfld.long 0x0 0. "CB,Cycle Bit (CB). Used in linked list mode only. It is used to synchronize the producer (software) and the consumer (DMA). For more details see 'PCS-CCS-CB-TCB Producer-Consumer Synchronization'. The DMA loads this field with the CB of the linked list.." "0,1" repeat.end repeat 8. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 )(list 0x0 0x200 0x400 0x600 0x800 0xA00 0xC00 0xE00 ) group.long ($2+0x208+0xC8000)++0x3 line.long 0x0 "DMA_TRANSFER_SIZE_OFF_WRCH_$1,DMA Write Transfer Size Register." hexmask.long 0x0 0.--31. 1. "DMA_TRANSFER_SIZE,DMA Transfer Size. You program this register with the size of the DMA transfer. The maximum DMA transfer size is 4Gbytes. The minimum transfer size is one byte (0x1). This field is automatically decremented by the DMA as the DMA write.." repeat.end repeat 8. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 )(list 0x0 0x200 0x400 0x600 0x800 0xA00 0xC00 0xE00 ) group.long ($2+0x20C+0xC8000)++0x3 line.long 0x0 "DMA_SAR_LOW_OFF_WRCH_$1,DMA Write SAR Low Register." hexmask.long 0x0 0.--31. 1. "SRC_ADDR_REG_LOW,Source Address Register (Lower 32 bits). Indicates the next address to be read from. The DMA increments the SAR as the DMA transfer progresses. In LL mode the DMA overwrites this with the corresponding dword of the LL element. - DMA.." repeat.end repeat 8. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 )(list 0x0 0x200 0x400 0x600 0x800 0xA00 0xC00 0xE00 ) group.long ($2+0x210+0xC8000)++0x3 line.long 0x0 "DMA_SAR_HIGH_OFF_WRCH_$1,DMA Write SAR High Register." hexmask.long 0x0 0.--31. 1. "SRC_ADDR_REG_HIGH,Source Address Register (Higher 32 bits). In LL mode the DMA overwrites this with the corresponding dword of the LL element. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" repeat.end repeat 8. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 )(list 0x0 0x200 0x400 0x600 0x800 0xA00 0xC00 0xE00 ) group.long ($2+0x214+0xC8000)++0x3 line.long 0x0 "DMA_DAR_LOW_OFF_WRCH_$1,DMA Write DAR Low Register." hexmask.long 0x0 0.--31. 1. "DST_ADDR_REG_LOW,Destination Address Register (Lower 32 bits). Indicates the next address to be written to. The DMA increments the DAR as the DMA transfer progresses. In LL mode the DMA overwrites this with the corresponding dword of the LL element. -.." repeat.end repeat 8. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 )(list 0x0 0x200 0x400 0x600 0x800 0xA00 0xC00 0xE00 ) group.long ($2+0x218+0xC8000)++0x3 line.long 0x0 "DMA_DAR_HIGH_OFF_WRCH_$1,DMA Write DAR High Register." hexmask.long 0x0 0.--31. 1. "DST_ADDR_REG_HIGH,Destination Address Register (Higher 32 bits). In LL mode the DMA overwrites this with the corresponding dword of the LL element. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" repeat.end repeat 8. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 )(list 0x0 0x200 0x400 0x600 0x800 0xA00 0xC00 0xE00 ) group.long ($2+0x21C+0xC8000)++0x3 line.long 0x0 "DMA_LLP_LOW_OFF_WRCH_$1,DMA Write Linked List Pointer Low Register." hexmask.long 0x0 0.--31. 1. "LLP_LOW,Lower bits of the address of the linked list transfer list in local memory. Used in linked list mode only. Updated by the DMA to point to the next element in the transfer list after the previous element is consumed. - When the current element is.." repeat.end repeat 8. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 )(list 0x0 0x200 0x400 0x600 0x800 0xA00 0xC00 0xE00 ) group.long ($2+0x220+0xC8000)++0x3 line.long 0x0 "DMA_LLP_HIGH_OFF_WRCH_$1,DMA Write Linked List Pointer High Register." hexmask.long 0x0 0.--31. 1. "LLP_HIGH,Upper 32 bits of the address of the linked list transfer list in local memory. Used in linked list mode only. Updated by the DMA to point to the next element in the transfer list as elements are consumed. Note: The access attributes of this.." repeat.end repeat 8. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 )(list 0x0 0x200 0x400 0x600 0x800 0xA00 0xC00 0xE00 ) group.long ($2+0x300+0xC8000)++0x3 line.long 0x0 "DMA_CH_CONTROL1_OFF_RDCH_$1,DMA Read Channel Control 1 Register." bitfld.long 0x0 30.--31. "DMA_AT,Address Translation TLP Header Bit (AT) The DMA uses this TLP header field when generating MRd/MWr (not IMWr) TLPs. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" "0,1,2,3" bitfld.long 0x0 27.--29. "DMA_TC,Traffic Class TLP Header Bit (TC) The DMA uses this TLP header field when generating MRd/MWr (not IMWr) TLPs. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 26. "DMA_RESERVED5,Reserved. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" "0,1" bitfld.long 0x0 25. "DMA_RO,Relaxed Ordering TLP Header Bit (RO) The DMA uses this TLP header field when generating MRd/MWr (not IMWr) TLPs. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" "0,1" newline bitfld.long 0x0 24. "DMA_NS_SRC,Source No Snoop TLP Header Bit (DMA_NS_SRC). The DMA uses this TLP header field when generating MRd (SAR addressing space) (not IMWr) TLPs. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" "0,1" bitfld.long 0x0 23. "DMA_NS_DST,Destination No Snoop TLP Header Bit (DMA_NS_DST). The DMA uses this TLP header field when generating MWr (DAR addressing space) (not IMWr) TLPs. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" "0,1" newline bitfld.long 0x0 22. "DMA_MEM_TYPE,Master AXI ACE-Lite Cache Coherency Control. This field sets the DMA channel memory type of the address space of the data transfer as follows: - 0x0:peripheral type - 0x1:memory type For more details see 'ACE-Lite Features and Limitations'.." "peripheral type,memory type" hexmask.long.byte 0x0 17.--21. 1. "DMA_RESERVED2,Reserved. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" newline hexmask.long.byte 0x0 12.--16. 1. "DMA_FUNC_NUM,Function Number (FN). The controller uses this field when generating the requester ID for the MRd/MWr DMA TLP. When you have enabled SR-IOV then this field is ignored if you have set the VFE field in the 'DMA Read Channel Control 2.." bitfld.long 0x0 10.--11. "DMA_RESERVED1,Reserved. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" "0,1,2,3" newline bitfld.long 0x0 9. "LLE,Linked List Enable (LLE). - 0: Disable linked list operation - 1: Enable linked list operation Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" "Disable linked list operation,Enable linked list operation" bitfld.long 0x0 8. "CCS,Consumer Cycle State (CCS). Used in linked list mode only. It is used to synchronize the producer (software) and the consumer (DMA). For more details see 'PCS-CCS-CB-TCB Producer-Consumer Synchronization'. You must initialize this bit. The DMA.." "0,1" newline bitfld.long 0x0 7. "DMA_RESERVED0,Reserved. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" "0,1" bitfld.long 0x0 5.--6. "CS,Channel Status (CS). The channel status bits identify the current operational state of the DMA channel. The operation state encoding for each DMA channel is a s follows: - 00: Reserved - 01: Running. This channel is active and transferring data. - 10:.." "Reserved,Running,?,?" newline bitfld.long 0x0 4. "RIE,Remote Interrupt Enable (RIE). You must set this bit to enable the generation of the Done or Abort Remote interrupts. For more details see 'Interrupts and Error Handling'. In LL mode the DMA overwrites this with the RIE of the LL element. The RIE.." "0,1" bitfld.long 0x0 3. "LIE,Local Interrupt Enable (LIE). You must set this bit to enable the generation of the Done or Abort Local interrupts. For more details see 'Interrupts and Error Handling'. In LL mode the DMA overwrites this with the LIE of the LL element. The LIE bit.." "0,1" newline bitfld.long 0x0 2. "LLP,Load Link Pointer (LLP). Used in linked list mode only. Indicates that this linked list element is a link element and its LL element pointer dwords are pointing to the next (non-contiguous) element. The DMA loads this field with the LLP of the.." "0,1" bitfld.long 0x0 1. "TCB,Toggle Cycle Bit (TCB). Indicates to the DMA to toggle its interpretation of the CB. Used in linked list mode only. It is used to synchronize the producer (software) and the consumer (DMA). For more details see 'PCS-CCS-CB-TCB Producer-Consumer.." "0,1" newline bitfld.long 0x0 0. "CB,Cycle Bit (CB). Used in linked list mode only. It is used to synchronize the producer (software) and the consumer (DMA). For more details see 'PCS-CCS-CB-TCB Producer-Consumer Synchronization'. The DMA loads this field with the CB of the linked list.." "0,1" repeat.end repeat 8. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 )(list 0x0 0x200 0x400 0x600 0x800 0xA00 0xC00 0xE00 ) group.long ($2+0x308+0xC8000)++0x3 line.long 0x0 "DMA_TRANSFER_SIZE_OFF_RDCH_$1,DMA Read Transfer Size Register." hexmask.long 0x0 0.--31. 1. "DMA_TRANSFER_SIZE,DMA Transfer Size. You program this register with the size of the DMA transfer. The maximum DMA transfer size is 4Gbytes. The minimum transfer size is one byte (0x1). This field is automatically decremented by the DMA as the DMA read.." repeat.end repeat 8. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 )(list 0x0 0x200 0x400 0x600 0x800 0xA00 0xC00 0xE00 ) group.long ($2+0x30C+0xC8000)++0x3 line.long 0x0 "DMA_SAR_LOW_OFF_RDCH_$1,DMA Read SAR Low Register." hexmask.long 0x0 0.--31. 1. "SRC_ADDR_REG_LOW,Source Address Register (Lower 32 bits). Indicates the next address to be read from. The DMA increments the SAR as the DMA transfer progresses. In LL mode the DMA overwrites this with the corresponding dword of the LL element. - DMA.." repeat.end repeat 8. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 )(list 0x0 0x200 0x400 0x600 0x800 0xA00 0xC00 0xE00 ) group.long ($2+0x310+0xC8000)++0x3 line.long 0x0 "DMA_SAR_HIGH_OFF_RDCH_$1,DMA Read SAR High Register." hexmask.long 0x0 0.--31. 1. "SRC_ADDR_REG_HIGH,Source Address Register (Higher 32 bits). In LL mode the DMA overwrites this with the corresponding dword of the LL element. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" repeat.end repeat 8. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 )(list 0x0 0x200 0x400 0x600 0x800 0xA00 0xC00 0xE00 ) group.long ($2+0x314+0xC8000)++0x3 line.long 0x0 "DMA_DAR_LOW_OFF_RDCH_$1,DMA Read DAR Low Register." hexmask.long 0x0 0.--31. 1. "DST_ADDR_REG_LOW,Destination Address Register (Lower 32 bits). Indicates the next address to be written to. The DMA increments the DAR as the DMA transfer progresses. In LL mode the DMA overwrites this with the corresponding dword of the LL element. -.." repeat.end repeat 8. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 )(list 0x0 0x200 0x400 0x600 0x800 0xA00 0xC00 0xE00 ) group.long ($2+0x318+0xC8000)++0x3 line.long 0x0 "DMA_DAR_HIGH_OFF_RDCH_$1,DMA Read DAR High Register." hexmask.long 0x0 0.--31. 1. "DST_ADDR_REG_HIGH,Destination Address Register (Higher 32 bits). In LL mode the DMA overwrites this with the corresponding dword of the LL element. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" repeat.end repeat 8. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 )(list 0x0 0x200 0x400 0x600 0x800 0xA00 0xC00 0xE00 ) group.long ($2+0x31C+0xC8000)++0x3 line.long 0x0 "DMA_LLP_LOW_OFF_RDCH_$1,DMA Read Linked List Pointer Low Register." hexmask.long 0x0 0.--31. 1. "LLP_LOW,Lower bits of the address of the linked list transfer list in local memory. Used in linked list mode only. Updated by the DMA to point to the next element in the transfer list after the previous element is consumed. - When the current element is.." repeat.end repeat 8. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 )(list 0x0 0x200 0x400 0x600 0x800 0xA00 0xC00 0xE00 ) group.long ($2+0x320+0xC8000)++0x3 line.long 0x0 "DMA_LLP_HIGH_OFF_RDCH_$1,DMA Read Linked List Pointer High Register." hexmask.long 0x0 0.--31. 1. "LLP_HIGH,Upper 32 bits of the address of the linked list transfer list in local memory. Used in linked list mode only. Updated by the DMA to point to the next element in the transfer list as elements are consumed. Note: The access attributes of this.." repeat.end tree.end tree "PF0_ATU_CAP (ATU Por Logic Structure)" repeat 8. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 )(list 0x0 0x200 0x400 0x600 0x800 0xA00 0xC00 0xE00 ) group.long ($2+0xC0000)++0x3 line.long 0x0 "IATU_REGION_CTRL_1_OFF_OUTBOUND_$1,iATU Region Control 1 Register." bitfld.long 0x0 20. "CTRL_1_FUNC_NUM,Function Number. - When the address of an outbound TLP is matched to this region and the FUNC_BYPASS field in the 'iATU Control 2 Register' is '0' then the function number used in generating the function part of the requester ID (RID).." "0,1" newline bitfld.long 0x0 13. "INCREASE_REGION_SIZE,Increase the maximum ATU Region size. When set the maximum ATU Region size is determined by CX_ATU_MAX_REGION_SIZE. When clear the maximum ATU Region size is 4 GB (default). Note: This register field is sticky." "0,1" newline bitfld.long 0x0 9.--10. "ATTR,When the address of an outbound TLP is matched to this region then the ATTR field of the TLP is changed to the value in this register. Note: This register field is sticky." "0,1,2,3" newline bitfld.long 0x0 8. "TD,This is a reserved field. Do not use. Note: This register field is sticky." "0,1" newline bitfld.long 0x0 5.--7. "TC,When the address of an outbound TLP is matched to this region then the TC field of the TLP is changed to the value in this register. Note: This register field is sticky." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x0 0.--4. 1. "TYPE,When the address of an outbound TLP is matched to this region then the TYPE field of the TLP is changed to the value in this register. Note: This register field is sticky." repeat.end repeat 8. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 )(list 0x0 0x200 0x400 0x600 0x800 0xA00 0xC00 0xE00 ) group.long ($2+0x4+0xC0000)++0x3 line.long 0x0 "IATU_REGION_CTRL_2_OFF_OUTBOUND_$1,iATU Region Control 2 Register." bitfld.long 0x0 31. "REGION_EN,Region Enable. This bit must be set to '1' for address translation to take place. Note: This register field is sticky." "0,1" newline bitfld.long 0x0 29. "INVERT_MODE,Invert Mode. When set the address matching region is inverted. Therefore an address match occurs when the untranslated address is in the region outside the defined range (Base Address to Limit Address). Note: This register field is sticky." "0,1" newline bitfld.long 0x0 28. "CFG_SHIFT_MODE,CFG Shift Mode. The iATU uses bits [27:12] of the untranslated address (on the XALI0/1/2 interface or AXI slave interface address) to form the BDF number of the outgoing CFG TLP. This supports the Enhanced Configuration Address Mapping.." "0,1" newline bitfld.long 0x0 27. "DMA_BYPASS,DMA Bypass Mode. Allows request TLPs which are initiated by the DMA controller to pass through the iATU untranslated. Note: This field is reserved for the SW product. You must set it to '0'. Note: This register field is sticky." "0,1" newline bitfld.long 0x0 23. "HEADER_SUBSTITUTE_EN,Header Substitute Enable. When enabled and region address is matched the iATU fully substitutes bytes 8-11 (for 3 DWORD header) or bytes 12-15 (for 4 DWORD header) of the outbound TLP header with the contents of the LWR_TARGET_RW.." "LWR_TARGET_RW in the..,LWR_TARGET_RW in the.." newline bitfld.long 0x0 22. "INHIBIT_PAYLOAD,Inhibit TLP Payload Data for TLP's in Matched Region; assign iATU region to be TLP without data. When enabled and region address is matched the iATU marks all TLPs as having no payload data by forcing the TLP header Fmt[1] bit =0.." "Fmt[1] =0/1 so that TLPs with or without data..,Fmt[1] =0 so that only TLP type without data is.." newline bitfld.long 0x0 21. "TLP_HEADER_FIELDS_BYPASS,TLP Header Fields Translation Bypass. In this mode header fields of the translated TLP is taken from your application transmit interface or if AMBA is configured from the AMBA sideband bus (slv_awmisc_info) and not from the.." "0,1" newline bitfld.long 0x0 20. "SNP,Serialize Non-Posted Requests. In this mode when the AXI Bridge is populated same AXI ID Non-Posted Read/Write Requests are transmitted on the wire if there are no other same ID Non-Posted Requests outstanding. Note: This register field is sticky." "0,1" newline bitfld.long 0x0 19. "FUNC_BYPASS,Function Number Translation Bypass. In this mode the function number of the translated TLP is taken from your application transmit interface and not from the CTRL_1_FUNC_NUM field of the 'iATU Control 1 Register' or the VF_NUMBER field of.." "0,1" newline bitfld.long 0x0 16. "TAG_SUBSTITUTE_EN,TAG Substitute Enable. When enabled and region address is matched the iATU substitutes the TAG field of the outbound TLP header with the contents of the TAG field in this register. The expected usage scenario is translation from AXI.." "0,1" newline hexmask.long.byte 0x0 8.--15. 1. "TAG,TAG. The substituted TAG field (byte 6) in the outgoing TLP header when TAG_SUBSTITUTE_EN is set. Note: This register field is sticky." newline hexmask.long.byte 0x0 0.--7. 1. "MSG_CODE,MSG TLPs (Message Code). When the address of an outbound TLP is matched to this region and the translated TLP TYPE field is Msg or MsgD; then the message field of the TLP is changed to the value in this register. Memory TLPs: (ST;Steering Tag)." repeat.end repeat 8. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 )(list 0x0 0x200 0x400 0x600 0x800 0xA00 0xC00 0xE00 ) group.long ($2+0x8+0xC0000)++0x3 line.long 0x0 "IATU_LWR_BASE_ADDR_OFF_OUTBOUND_$1,iATU Lower Base Address Register. The CX_ATU_MIN_REGION_SIZE configuration parameter (Value Range: 4 kB. 8 kB. 16 kB. 32 kB. 64 kB defaults to 64 kB) specifies the minimum size of an address translation region. For.." hexmask.long.tbyte 0x0 12.--31. 1. "LWR_BASE_RW,Forms bits [31:n] of the start address of the address region to be translated. n is log2(CX_ATU_MIN_REGION_SIZE) Note: This register field is sticky." newline hexmask.long.word 0x0 0.--11. 1. "LWR_BASE_HW,Forms bits [n-1:0] of the start address of the address region to be translated. The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary so these bits are always 0. A write to this location is ignored by the PCIe controller." repeat.end repeat 8. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 )(list 0x0 0x200 0x400 0x600 0x800 0xA00 0xC00 0xE00 ) group.long ($2+0xC+0xC0000)++0x3 line.long 0x0 "IATU_UPPER_BASE_ADDR_OFF_OUTBOUND_$1,iATU Upper Base Address Register." hexmask.long 0x0 0.--31. 1. "UPPER_BASE_RW,Forms bits [63:32] of the start (and end) address of the address region to be translated. In systems with a 32-bit address space this register is not used and therefore writing to this register has no effect. Note: This register field is.." repeat.end repeat 8. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 )(list 0x0 0x200 0x400 0x600 0x800 0xA00 0xC00 0xE00 ) group.long ($2+0x10+0xC0000)++0x3 line.long 0x0 "IATU_LIMIT_ADDR_OFF_OUTBOUND_$1,iATU Limit Address Register." hexmask.long.tbyte 0x0 12.--31. 1. "LIMIT_ADDR_RW,Forms upper bits of the end address of the address region to be translated. Note: This register field is sticky." newline hexmask.long.word 0x0 0.--11. 1. "LIMIT_ADDR_HW,Forms lower bits of the end address of the address region to be translated. The end address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary so these bits are always all ones. A write to this location is ignored by the PCIe.." repeat.end repeat 8. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 )(list 0x0 0x200 0x400 0x600 0x800 0xA00 0xC00 0xE00 ) group.long ($2+0x14+0xC0000)++0x3 line.long 0x0 "IATU_LWR_TARGET_ADDR_OFF_OUTBOUND_$1,iATU Lower Target Address Register." hexmask.long 0x0 0.--31. 1. "LWR_TARGET_RW_OUTBOUND,When HEADER_SUBSTITUTE_EN in IATU_REGION_CTRL_2_OFF_OUTBOUND_ is '0' (normal operation): - LWR_TARGET_RW[31:n] forms MSB's of the Lower Target part of the new address of the translated region; - LWR_TARGET_RW[n-1:0] are not used." repeat.end repeat 8. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 )(list 0x0 0x200 0x400 0x600 0x800 0xA00 0xC00 0xE00 ) group.long ($2+0x18+0xC0000)++0x3 line.long 0x0 "IATU_UPPER_TARGET_ADDR_OFF_OUTBOUND_$1,iATU Upper Target Address Register." hexmask.long 0x0 0.--31. 1. "UPPER_TARGET_RW,Forms bits [63:32] of the start address (Upper Target part) of the new address of the translated region. Note: This register field is sticky." repeat.end repeat 8. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 )(list 0x0 0x200 0x400 0x600 0x800 0xA00 0xC00 0xE00 ) group.long ($2+0x100+0xC0000)++0x3 line.long 0x0 "IATU_REGION_CTRL_1_OFF_INBOUND_$1,iATU Region Control 1 Register." bitfld.long 0x0 20. "CTRL_1_FUNC_NUM,Function Number. - MEM-I/O: When the Address and BAR matching logic in the controller indicate that a MEM-I/O transaction matches a BAR in the function corresponding to this value then address translation proceeds. This check is only.." "?,When the destination function number as.." newline bitfld.long 0x0 13. "INCREASE_REGION_SIZE,Increase the maximum ATU Region size. When set the maximum ATU Region size is determined by CX_ATU_MAX_REGION_SIZE. When clear the maximum ATU Region size is 4 GB (default). Note: This register field is sticky." "0,1" newline bitfld.long 0x0 9.--10. "ATTR,When the ATTR field of an inbound TLP is matched to this value then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the 'ATTR Match Enable' bit of the 'iATU Control 2 Register' is.." "0,1,2,3" newline bitfld.long 0x0 8. "TD,When the TD field of an inbound TLP is matched to this value then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the 'TD Match Enable' bit of the 'iATU Control 2 Register' is set." "0,1" newline bitfld.long 0x0 5.--7. "TC,When the TC field of an inbound TLP is matched to this value then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the 'TC Match Enable' bit of the 'iATU Control 2 Register' is set." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x0 0.--4. 1. "TYPE,When the TYPE field of an inbound TLP is matched to this value then address translation proceeds (when all other enabled field-matches are successful). Note: This register field is sticky." repeat.end repeat 8. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 )(list 0x0 0x200 0x400 0x600 0x800 0xA00 0xC00 0xE00 ) group.long ($2+0x104+0xC0000)++0x3 line.long 0x0 "IATU_REGION_CTRL_2_OFF_INBOUND_$1,iATU Region Control 2 Register." bitfld.long 0x0 31. "REGION_EN,Region Enable. This bit must be set to '1' for address translation to take place. Note: This register field is sticky." "0,1" newline bitfld.long 0x0 30. "MATCH_MODE,Match Mode. Determines Inbound matching mode for TLPs. The mode depends on the type of TLP that is received as follows: For MEM-I/O TLPs this field is interpreted as follows: - 0: Address Match Mode. The iATU operates using addresses as in.." "Address Match Mode,Vendor ID Match Mode" newline bitfld.long 0x0 29. "INVERT_MODE,Invert Mode. When set the address matching region is inverted. Therefore an address match occurs when the untranslated address is in the region outside the defined range (Base Address to Limit Address). Note: This register field is sticky." "0,1" newline bitfld.long 0x0 28. "CFG_SHIFT_MODE,CFG Shift Mode. This is useful for CFG transactions where the PCIe configuration mechanism maps bits [27:12] of the address to the bus/device and function number. This allows a CFG configuration space to be located in any 256MB window of.." "0,1" newline bitfld.long 0x0 27. "FUZZY_TYPE_MATCH_CODE,Fuzzy Type Match Mode. When enabled the iATU relaxes the matching of the TLP TYPE field against the expected TYPE field so that - CfgRd0 and CfgRd1 TLPs are seen as identical. Similarly with CfgWr0 and CfgWr1. - MWr MRd and MRdLk.." "0,1" newline bitfld.long 0x0 24.--25. "RESPONSE_CODE,Response Code. Defines the type of response to give for accesses matching this region. This overrides the normal RADM filter response. Note that this feature is not available for any region where Single Address Location Translate is.." "Normal RADM filter response is used,Unsupported request,?,?" newline bitfld.long 0x0 23. "SINGLE_ADDR_LOC_TRANS_EN,Single Address Location Translate Enable. When enabled Rx TLPs can be translated to a single address location as determined by the target address register of the iATU region. The main usage scenario is translation of Messages.." "0,1" newline bitfld.long 0x0 21. "MSG_CODE_MATCH_EN,Message Code Match Enable (Msg TLPS). Ensures that a successful message Code TLP field comparison match (see Message Code field of the 'iATU Control 2 Register') occurs (in MSG transactions) for address translation to proceed. ST Match.." "0,1" newline bitfld.long 0x0 19. "FUNC_NUM_MATCH_EN,Function Number Match Enable. Ensures that a successful Function Number TLP field comparison match (see Function Number field of the 'iATU Control 1 Register') occurs (in MEM-I/O and CFG0/CFG1 transactions) for address translation to.." "0,1" newline bitfld.long 0x0 16. "ATTR_MATCH_EN,ATTR Match Enable. Ensures that a successful ATTR TLP field comparison match (see ATTR field of the 'iATU Control 1 Register') occurs for address translation to proceed. Note: This register field is sticky." "0,1" newline bitfld.long 0x0 15. "TD_MATCH_EN,TD Match Enable. Ensures that a successful TD TLP field comparison match (see TD field of the 'iATU Control 1 Register') occurs for address translation to proceed. Note: This register field is sticky." "0,1" newline bitfld.long 0x0 14. "TC_MATCH_EN,TC Match Enable. Ensures that a successful TC TLP field comparison match (see TC field of the 'iATU Control 1 Register') occurs for address translation to proceed. Note: This register field is sticky." "0,1" newline bitfld.long 0x0 13. "MSG_TYPE_MATCH_MODE,Message Type Match Mode. When enabled and if single address location translate enable is set then inbound TLPs of type MSG/MSGd which match the type field of the iatu_region_ctrl_1_OFF_inbound register (=>TYPE[4:3]=2'b10) will be.." "0,1" newline bitfld.long 0x0 8.--10. "BAR_NUM,BAR Number. When the BAR number of an inbound MEM or IO TLP ' that is matched by the normal internal BAR address matching mechanism ' is the same as this field address translation proceeds (when all other enabled field-matches are successful)." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x0 0.--7. 1. "MSG_CODE,MSG TLPs: (Message Code). When the TYPE field of an inbound Msg/MsgD TLP is matched to this value then address translation proceeds (when all other enabled field-matches are successful). This check is only performed if the 'Message Code Match.." repeat.end repeat 8. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 )(list 0x0 0x200 0x400 0x600 0x800 0xA00 0xC00 0xE00 ) group.long ($2+0x108+0xC0000)++0x3 line.long 0x0 "IATU_LWR_BASE_ADDR_OFF_INBOUND_$1,iATU Lower Base Address Register. The CX_ATU_MIN_REGION_SIZE configuration parameter (Value Range: 4 kB. 8 kB. 16 kB. 32 kB. 64 kB defaults to 64 kB) specifies the minimum size of an address translation region. For.." hexmask.long.tbyte 0x0 12.--31. 1. "LWR_BASE_RW,Forms bits [31:n] of the start address of the address region to be translated. n is log2(CX_ATU_MIN_REGION_SIZE) Note: This register field is sticky." newline hexmask.long.word 0x0 0.--11. 1. "LWR_BASE_HW,Forms bits [n-1:0] of the start address of the address region to be translated. The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary so these bits are always 0. A write to this location is ignored by the PCIe controller." repeat.end repeat 8. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 )(list 0x0 0x200 0x400 0x600 0x800 0xA00 0xC00 0xE00 ) group.long ($2+0x10C+0xC0000)++0x3 line.long 0x0 "IATU_UPPER_BASE_ADDR_OFF_INBOUND_$1,iATU Upper Base Address Register." hexmask.long 0x0 0.--31. 1. "UPPER_BASE_RW,Forms bits [63:32] of the start (and end) address of the address region to be translated. Note: This register field is sticky." repeat.end repeat 8. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 )(list 0x0 0x200 0x400 0x600 0x800 0xA00 0xC00 0xE00 ) group.long ($2+0x110+0xC0000)++0x3 line.long 0x0 "IATU_LIMIT_ADDR_OFF_INBOUND_$1,iATU Limit Address Register." hexmask.long.tbyte 0x0 12.--31. 1. "LIMIT_ADDR_RW,Forms upper bits of the end address of the address region to be translated. Note: This register field is sticky." newline hexmask.long.word 0x0 0.--11. 1. "LIMIT_ADDR_HW,Forms lower bits of the end address of the address region to be translated. The end address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary so these bits are always all ones. A write to this location is ignored by the PCIe.." repeat.end repeat 8. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 )(list 0x0 0x200 0x400 0x600 0x800 0xA00 0xC00 0xE00 ) group.long ($2+0x114+0xC0000)++0x3 line.long 0x0 "IATU_LWR_TARGET_ADDR_OFF_INBOUND_$1,iATU Lower Target Address Register." hexmask.long.tbyte 0x0 12.--31. 1. "LWR_TARGET_RW,Forms MSB's of the Lower Target part of the new address of the translated region. These bits are always '0'. - Field size depends on log2(CX_ATU_MIN_REGION_SIZE) in address match mode. - Field size depends on log2(BAR_MASK+1) in BAR match.." newline hexmask.long.word 0x0 0.--11. 1. "LWR_TARGET_HW,Forms the LSB's of the Lower Target part of the new address of the translated region. The start address must be aligned to a CX_ATU_MIN_REGION_SIZE kB boundary (in address match mode); and to the Bar size boundary (in BAR match mode) so.." repeat.end repeat 8. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 )(list 0x0 0x200 0x400 0x600 0x800 0xA00 0xC00 0xE00 ) group.long ($2+0x118+0xC0000)++0x3 line.long 0x0 "IATU_UPPER_TARGET_ADDR_OFF_INBOUND_$1,iATU Upper Target Address Register." hexmask.long 0x0 0.--31. 1. "UPPER_TARGET_RW,Forms bits [63:32] of the start address (Upper Target part) of the new address of the translated region. In systems with a 32-bit address space this register is not used and therefore writing to this register has no effect. Note: This.." repeat.end tree.end tree "PF0_PORT_LOGIC (Port Logic)" group.long (0x0+0x700)++0x27 line.long 0x0 "ACK_LATENCY_TIMER_OFF,Ack Latency Timer and Replay Timer Register." hexmask.long.word 0x0 16.--31. 1. "REPLAY_TIME_LIMIT,Replay Timer Limit. The replay timer expires when it reaches this limit. The controller initiates a replay upon reception of a NAK or when the replay timer expires. For more details see 'Transmit Replay'. You can modify the effective.." newline hexmask.long.word 0x0 0.--15. 1. "ROUND_TRIP_LATENCY_TIME_LIMIT,Ack Latency Timer Limit. The Ack latency timer expires when it reaches this limit. For more details see 'Ack Scheduling'. You can modify the effective timer limit with the TIMER_MOD_ACK_NAK field of the.." line.long 0x4 "VENDOR_SPEC_DLLP_OFF,Vendor Specific DLLP Register." hexmask.long 0x4 0.--31. 1. "VENDOR_SPEC_DLLP,Vendor Specific DLLP Register. Used to send a specific PCI Express DLLP. Your application writes the 8-bit DLLP Type and 24-bits of Payload data into this register then sets the field VENDOR_SPECIFIC_DLLP_REQ of PORT_LINK_CTRL_OFF to.." line.long 0x8 "PORT_FORCE_OFF,Port Force Link Register." hexmask.long.byte 0x8 24.--31. 1. "RSVDP_24,Reserved for future use." newline bitfld.long 0x8 23. "DO_DESKEW_FOR_SRIS,Use the transitions from TS2 to Logical Idle Symbol SKP OS to Logical Idle Symbol EIEOS to Logical Idle Symbol and FTS Sequence to SKP OS to do deskew instead of using received SKP OS or TS1 to TS2 transition if DO_DESKEW_FOR_SRIS.." "0,1" newline rbitfld.long 0x8 22. "RSVDP_22,Reserved for future use." "0,1" newline hexmask.long.byte 0x8 16.--21. 1. "LINK_STATE,Forced LTSSM State. The LTSSM state that the controller is forced to when you set the FORCE_EN bit (Force Link). LTSSM state encoding is defined by the lts_state variable in workspace/src/Layer1/smlh_ltssm.v. Note: This register field is sticky." newline bitfld.long 0x8 15. "FORCE_EN,Force Link. The controller supports a testing and debug capability to allow your software to force the LTSSM state machine into a specific state and to force the controller to transmit a specific Link Command. Asserting this bit triggers the.." "0,1" newline rbitfld.long 0x8 12.--14. "RSVDP_12,Reserved for future use." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x8 8.--11. 1. "FORCED_LTSSM,Forced Link Command. The link command that the controller is forced to transmit when you set FORCE_EN bit (Force Link). Link command encoding is defined by the ltssm_cmd variable in workspace/src/Layer1/smlh_ltssm.v. Note: This register.." newline hexmask.long.byte 0x8 0.--7. 1. "LINK_NUM,Link Number. Not used for endpoint. Not used for M-PCIe. Note: This register field is sticky." line.long 0xC "ACK_F_ASPM_CTRL_OFF,Ack Frequency and L0-L1 ASPM Control Register." rbitfld.long 0xC 31. "RSVDP_31,Reserved for future use." "0,1" newline bitfld.long 0xC 30. "ENTER_ASPM,ASPM L1 Entry Control. - 1: Controller enters ASPM L1 after a period in which it has been idle. - 0: Controller enters ASPM L1 only after idle period during which both receive and transmit are in L0s. Note: This register field is sticky." "Controller enters ASPM L1 only after idle period..,Controller enters ASPM L1 after a period in.." newline bitfld.long 0xC 27.--29. "L1_ENTRANCE_LATENCY,L1 Entrance Latency. Value range is: - 000: 1 us - 001: 2 us - 010: 4 us - 011: 8 us - 100: 16 us - 101: 32 us - 110 or 111: 64 us Note: Programming this timer with a value greater that 32us has no effect unless extended sync is used.." "0,1,2,3,4,5,6,7" newline bitfld.long 0xC 24.--26. "L0S_ENTRANCE_LATENCY,L0s Entrance Latency. Values correspond to: - 000: 1 us - 001: 2 us - 010: 3 us - 011: 4 us - 100: 5 us - 101: 6 us - 110 or 111: 7 us This field is applicable to STALL while in L0 for M-PCIe. Note: This register field is sticky." "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0xC 16.--23. 1. "COMMON_CLK_N_FTS,Common Clock N_FTS. This is the N_FTS when common clock is used. The number of Fast Training Sequence ordered sets to be transmitted when transitioning from L0s to L0. The maximum number of FTS ordered-sets that a component can request.." newline hexmask.long.byte 0xC 8.--15. 1. "ACK_N_FTS,N_FTS. The number of Fast Training Sequence ordered sets to be transmitted when transitioning from L0s to L0. The maximum number of FTS ordered-sets that a component can request is 255. The controller does not support a value of zero; a value.." newline hexmask.long.byte 0xC 0.--7. 1. "ACK_FREQ,Ack Frequency. The controller accumulates the number of pending ACKs specified here (up to 255) before scheduling an ACK DLLP. - 0: Indicates that this Ack Frequency Counter feature is turned off. The controller generates a low-priority ACK.." line.long 0x10 "PORT_LINK_CTRL_OFF,Port Link Control Register." hexmask.long.byte 0x10 28.--31. 1. "RSVDP_28,Reserved for future use." newline bitfld.long 0x10 27. "TRANSMIT_LANE_REVERSALE_ENABLE,TRANSMIT_LANE_REVERSALE_ENABLE is an internally reserved field. Do not use. Note: This register field is sticky." "0,1" newline bitfld.long 0x10 26. "EXTENDED_SYNCH,EXTENDED_SYNCH is an internally reserved field. Do not use. Note: This register field is sticky." "0,1" newline bitfld.long 0x10 25. "CORRUPT_LCRC_ENABLE,CORRUPT_LCRC_ENABLE is an internally reserved field. Do not use. Note: This register field is sticky." "0,1" newline bitfld.long 0x10 24. "BEACON_ENABLE,BEACON_ENABLE is an internally reserved field. Do not use. Note: This register field is sticky." "0,1" newline hexmask.long.byte 0x10 16.--21. 1. "LINK_CAPABLE,Link Mode Enable. Sets the number of lanes in the link that you want to connect to the link partner. When you have unused lanes in your system then you must change the value in this register to reflect the number of lanes. You must also.." newline hexmask.long.byte 0x10 12.--15. 1. "RSVDP_12,Reserved for future use." newline hexmask.long.byte 0x10 8.--11. 1. "LINK_RATE,LINK_RATE is an internally reserved field. Do not use. Note: This register field is sticky." newline bitfld.long 0x10 7. "FAST_LINK_MODE,Fast Link Mode. Sets all internal LTSSM millisecond timers to Fast Mode for speeding up simulation. Forces the LTSSM training (link initialization) to use shorter time-outs and to link up faster. The default scaling factor can be changed.." "0,1" newline bitfld.long 0x10 6. "LINK_DISABLE,LINK_DISABLE is an internally reserved field. Do not use. Note: This register field is sticky." "0,1" newline bitfld.long 0x10 5. "DLL_LINK_EN,DLL Link Enable. Enables link initialization. When DLL Link Enable =0 the controller does not transmit InitFC DLLPs and does not establish a link. Note: This register field is sticky." "0,1" newline rbitfld.long 0x10 4. "RSVDP_4,Reserved for future use." "0,1" newline bitfld.long 0x10 3. "RESET_ASSERT,Reset Assert. Triggers a recovery and forces the LTSSM to the hot reset state (downstream port only). Note: This register field is sticky." "0,1" newline bitfld.long 0x10 2. "LOOPBACK_ENABLE,Loopback Enable. Turns on loopback. For more details see 'Loopback'. For M-PCIe to force the master to enter Digital Loopback mode you must set this field to '1' during Configuration.start state(initial discovery/configuration). M-PCIe.." "0,1" newline bitfld.long 0x10 1. "SCRAMBLE_DISABLE,Scramble Disable. Turns off data scrambling. Note: This register field is sticky." "0,1" newline bitfld.long 0x10 0. "VENDOR_SPECIFIC_DLLP_REQ,Vendor Specific DLLP Request. When software writes a '1' to this bit the controller transmits the DLLP contained in the VENDOR_SPEC_DLLP field of VENDOR_SPEC_DLLP_OFF. Reading from this self-clearing register field always.." "0,1" line.long 0x14 "LANE_SKEW_OFF,Lane Skew Register." bitfld.long 0x14 31. "DISABLE_LANE_TO_LANE_DESKEW,Disable Lane-to-Lane Deskew. Causes the controller to disable the internal Lane-to-Lane deskew logic. Note: This register field is sticky." "0,1" newline hexmask.long.byte 0x14 27.--30. 1. "IMPLEMENT_NUM_LANES,Implementation-specific Number of Lanes. Set the implementation-specific number of lanes. Allowed values are: - 4'b0000: 1 lane - 4'b0001: 2 lanes - 4'b0011: 4 lanes - 4'b0111: 8 lanes - 4'b1111: 16 lanes The number of lanes to be.." newline bitfld.long 0x14 26. "ELASTIC_BUFFER_MODE,Selects Elasticity Buffer operating mode: 0: Nominal Half Full Buffer mode 1: Nominal Empty Buffer Mode Note: This register field is sticky." "Nominal Half Full Buffer mode,Nominal Empty Buffer Mode" newline bitfld.long 0x14 25. "ACK_NAK_DISABLE,Ack/Nak Disable. Prevents the controller from sending ACK and NAK DLLPs. Note: This register field is sticky." "0,1" newline bitfld.long 0x14 24. "FLOW_CTRL_DISABLE,Flow Control Disable. Prevents the controller from sending FC DLLPs. Note: This register field is sticky." "0,1" newline hexmask.long.tbyte 0x14 0.--23. 1. "INSERT_LANE_SKEW,INSERT_LANE_SKEW is an internally reserved field. Do not use. Note: This register field is sticky." line.long 0x18 "TIMER_CTRL_MAX_FUNC_NUM_OFF,Timer Control and Max Function Number Register." rbitfld.long 0x18 31. "RSVDP_31,Reserved for future use." "0,1" newline bitfld.long 0x18 29.--30. "FAST_LINK_SCALING_FACTOR,Fast Link Timer Scaling Factor. Sets the scaling factor of LTSSM timer when FAST_LINK_MODE field in PORT_LINK_CTRL_OFF is set to '1'. - 0: Scaling Factor is 1024 (1ms is 1us *a) - 1: Scaling Factor is 256 (1ms is 4us) - 2:.." "Scaling Factor is 1024,Scaling Factor is 256,Scaling Factor is 64,Scaling Factor is 16" newline hexmask.long.byte 0x18 24.--28. 1. "UPDATE_FREQ_TIMER,UPDATE_FREQ_TIMER is an internally reserved field. Do not use. Note: This register field is sticky." newline hexmask.long.byte 0x18 19.--23. 1. "TIMER_MOD_ACK_NAK,Ack Latency Timer Modifier. Increases the timer value for the Ack latency timer in increments of 64 clock cycles. A value of '0' represents no modification to the timer value. For more details see the ROUND_TRIP_LATENCY_TIME_LIMIT.." newline hexmask.long.byte 0x18 14.--18. 1. "TIMER_MOD_REPLAY_TIMER,Replay Timer Limit Modifier. Increases the time-out value for the replay timer in increments of 64 clock cycles at Gen1 or Gen2 speed and in increments of 256 clock cycles at Gen3 speed. A value of '0' represents no modification.." newline hexmask.long.byte 0x18 8.--13. 1. "RSVDP_8,Reserved for future use." newline hexmask.long.byte 0x18 0.--7. 1. "MAX_FUNC_NUM,Maximum function number that can be used in a request. Configuration requests targeted at function numbers above this value are returned with UR (unsupported request). Note: This register field is sticky." line.long 0x1C "SYMBOL_TIMER_FILTER_1_OFF,Symbol Timer Register and Filter Mask 1 Register. The Filter Mask 1 Register modifies the RADM filtering and error handling rules. For more details. see the 'Receive Filtering' section. In each case. '0' applies the associated.." hexmask.long.word 0x1C 16.--31. 1. "MASK_RADM_1,Filter Mask 1. The Filter Mask 1 Register modifies the RADM filtering and error handling rules. For more details see the 'Receive Filtering' section. In each case '0' applies the associated filtering rule and '1' masks the associated.." newline bitfld.long 0x1C 15. "DISABLE_FC_WD_TIMER,Disable FC Watchdog Timer. Note: This register field is sticky." "0,1" newline hexmask.long.byte 0x1C 11.--14. 1. "EIDLE_TIMER,EIDLE_TIMER is an internally reserved field. Do not use. Note: This register field is sticky." newline hexmask.long.word 0x1C 0.--10. 1. "SKP_INT_VAL,SKP Interval Value. The number of symbol times to wait between transmitting SKP ordered sets. Note that the controller actually waits the number of symbol times in this register plus 1 between transmitting SKP ordered sets. Your application.." line.long 0x20 "FILTER_MASK_2_OFF,Filter Mask 2 Register. This register modifies the RADM filtering and error handling rules. For more details. see the 'Receive Filtering' section. In each case. '0' applies the associated filtering rule and '1' masks the associated.." hexmask.long 0x20 0.--31. 1. "MASK_RADM_2,Filter Mask 2. This field modifies the RADM filtering and error handling rules. For more details see the 'Receive Filtering' section. In each case '0' applies the associated filtering rule and '1' masks the associated filtering rule." line.long 0x24 "AMBA_MUL_OB_DECOMP_NP_SUB_REQ_CTRL_OFF,AMBA Multiple Outbound Decomposed NP SubRequests Control Register." hexmask.long 0x24 1.--31. 1. "RSVDP_1,Reserved for future use." newline bitfld.long 0x24 0. "OB_RD_SPLIT_BURST_EN,Enable AMBA Multiple Outbound Decomposed NP SubRequests. This bit when set to '0' disables the possibility of having multiple outstanding non-posted requests that were derived from decomposition of an outbound AMBA request. For more.." "0,1" rgroup.long (0x28+0x700)++0x13 line.long 0x0 "PL_DEBUG0_OFF,Debug Register 0" hexmask.long 0x0 0.--31. 1. "DEB_REG_0,The value on cxpl_debug_info[31:0]." line.long 0x4 "PL_DEBUG1_OFF,Debug Register 1" hexmask.long 0x4 0.--31. 1. "DEB_REG_1,The value on cxpl_debug_info[63:32]." line.long 0x8 "TX_P_FC_CREDIT_STATUS_OFF,Transmit Posted FC Credit Status" hexmask.long.word 0x8 20.--31. 1. "RSVDP_TX_P_FC_CREDIT_STATUS,Reserved for future use." newline hexmask.long.byte 0x8 12.--19. 1. "TX_P_HEADER_FC_CREDIT,Transmit Posted Header FC Credits. The posted Header credits advertised by the receiver at the other end of the link updated with each UpdateFC DLLP. Default value depends on the number of advertised credits for header and data.." newline hexmask.long.word 0x8 0.--11. 1. "TX_P_DATA_FC_CREDIT,Transmit Posted Data FC Credits. The posted Data credits advertised by the receiver at the other end of the link updated with each UpdateFC DLLP. Default value depends on the number of advertised credits for header and data Scaled.." line.long 0xC "TX_NP_FC_CREDIT_STATUS_OFF,Transmit Non-Posted FC Credit Status" hexmask.long.word 0xC 20.--31. 1. "RSVDP_TX_NP_FC_CREDIT_STATUS,Reserved for future use." newline hexmask.long.byte 0xC 12.--19. 1. "TX_NP_HEADER_FC_CREDIT,Transmit Non-Posted Header FC Credits. The non-posted Header credits advertised by the receiver at the other end of the link updated with each UpdateFC DLLP. Default value depends on the number of advertised credits for header and.." newline hexmask.long.word 0xC 0.--11. 1. "TX_NP_DATA_FC_CREDIT,Transmit Non-Posted Data FC Credits. The non-posted Data credits advertised by the receiver at the other end of the link updated with each UpdateFC DLLP. Default value depends on the number of advertised credits for header and data.." line.long 0x10 "TX_CPL_FC_CREDIT_STATUS_OFF,Transmit Completion FC Credit Status" hexmask.long.word 0x10 20.--31. 1. "RSVDP_TX_CPL_FC_CREDIT_STATUS,Reserved for future use." newline hexmask.long.byte 0x10 12.--19. 1. "TX_CPL_HEADER_FC_CREDIT,Transmit Completion Header FC Credits. The Completion Header credits advertised by the receiver at the other end of the link updated with each UpdateFC DLLP. Default value depends on the number of advertised credits for header.." newline hexmask.long.word 0x10 0.--11. 1. "TX_CPL_DATA_FC_CREDIT,Transmit Completion Data FC Credits. The Completion Data credits advertised by the receiver at the other end of the link updated with each UpdateFC DLLP. Default value depends on the number of advertised credits for header and data.." group.long (0x3C+0x700)++0x3 line.long 0x0 "QUEUE_STATUS_OFF,Queue Status" bitfld.long 0x0 31. "TIMER_MOD_FLOW_CONTROL_EN,FC Latency Timer Override Enable. When this bit is set the value from the 'FC Latency Timer Override Value' field in this register will override the FC latency timer value that the controller calculates according to the PCIe.." "0,1" newline rbitfld.long 0x0 29.--30. "RSVDP_29,Reserved for future use." "0,1,2,3" newline hexmask.long.word 0x0 16.--28. 1. "TIMER_MOD_FLOW_CONTROL,FC Latency Timer Override Value. When you set the 'FC Latency Timer Override Enable' in this register the value in this field will override the FC latency timer value that the controller calculates according to the PCIe.." newline rbitfld.long 0x0 13. "RX_SERIALIZATION_Q_NON_EMPTY,Receive Serialization Queue Not Empty. Indicates there is data in the serialization queue." "0,1" newline hexmask.long.word 0x0 4.--12. 1. "RSVDP_4,Reserved for future use." newline bitfld.long 0x0 3. "RX_QUEUE_OVERFLOW,Receive Credit Queue Overflow. Indicates insufficient buffer space available to write to the P/NP/CPL credit queue." "0,1" newline rbitfld.long 0x0 2. "RX_QUEUE_NON_EMPTY,Receive Credit Queue Not Empty. Indicates there is data in one or more of the receive buffers." "0,1" newline rbitfld.long 0x0 1. "TX_RETRY_BUFFER_NE,Transmit Retry Buffer Not Empty. Indicates that there is data in the transmit retry buffer." "0,1" newline rbitfld.long 0x0 0. "RX_TLP_FC_CREDIT_NON_RETURN,Received TLP FC Credits Not Returned. Indicates that the controller has received a TLP but has not yet sent an UpdateFC DLLP indicating that the credits for that TLP have been restored by the receiver at the other end of the.." "0,1" rgroup.long (0x40+0x700)++0x7 line.long 0x0 "VC_TX_ARBI_1_OFF,VC Transmit Arbitration Register 1" hexmask.long.byte 0x0 24.--31. 1. "WRR_WEIGHT_VC_3,WRR Weight for VC3. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R" newline hexmask.long.byte 0x0 16.--23. 1. "WRR_WEIGHT_VC_2,WRR Weight for VC2. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R" newline hexmask.long.byte 0x0 8.--15. 1. "WRR_WEIGHT_VC_1,WRR Weight for VC1. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R" newline hexmask.long.byte 0x0 0.--7. 1. "WRR_WEIGHT_VC_0,WRR Weight for VC0. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R" line.long 0x4 "VC_TX_ARBI_2_OFF,VC Transmit Arbitration Register 2" hexmask.long.byte 0x4 24.--31. 1. "WRR_WEIGHT_VC_7,WRR Weight for VC7. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R" newline hexmask.long.byte 0x4 16.--23. 1. "WRR_WEIGHT_VC_6,WRR Weight for VC6. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R" newline hexmask.long.byte 0x4 8.--15. 1. "WRR_WEIGHT_VC_5,WRR Weight for VC5. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R" newline hexmask.long.byte 0x4 0.--7. 1. "WRR_WEIGHT_VC_4,WRR Weight for VC4. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R" group.long (0x48+0x700)++0xB line.long 0x0 "VC0_P_RX_Q_CTRL_OFF,Segmented-Buffer VC0 Posted Receive Queue Control." bitfld.long 0x0 31. "VC_ORDERING_RX_Q,VC Ordering for Receive Queues. Determines the VC ordering rule for the receive queues used only in the segmented-buffer configuration: - 1: Strict ordering higher numbered VCs have higher priority - 0: Round robin Note: This register.." "Round robin,Strict ordering" newline bitfld.long 0x0 30. "TLP_TYPE_ORDERING_VC0,TLP Type Ordering for VC0. Determines the TLP type ordering rule for VC0 receive queues used only in the segmented-buffer configuration: - 1: PCIe ordering rules (recommended) - 0: Strict ordering: posted completion then.." "Strict ordering: posted,PCIe ordering rules" newline bitfld.long 0x0 28.--29. "RESERVED5,Reserved. Note: This register field is sticky." "0,1,2,3" newline bitfld.long 0x0 26.--27. "VC0_P_DATA_SCALE,VC0 Scale Posted Data Credites. Note: This register field is sticky." "0,1,2,3" newline bitfld.long 0x0 24.--25. "VC0_P_HDR_SCALE,VC0 Scale Posted Header Credites. Note: This register field is sticky." "0,1,2,3" newline bitfld.long 0x0 21.--23. "VC0_P_TLP_Q_MODE,Reserved. Note: This register field is sticky." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 20. "RESERVED4,Reserved. Note: This register field is sticky." "0,1" newline hexmask.long.byte 0x0 12.--19. 1. "VC0_P_HEADER_CREDIT,VC0 Posted Header Credits. The number of initial posted header credits for VC0 used only in the segmented-buffer configuration. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R (sticky) Note: This.." newline hexmask.long.word 0x0 0.--11. 1. "VC0_P_DATA_CREDIT,VC0 Posted Data Credits. The number of initial posted data credits for VC0 used only in the segmented-buffer configuration. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R (sticky) Note: This.." line.long 0x4 "VC0_NP_RX_Q_CTRL_OFF,Segmented-Buffer VC0 Non-Posted Receive Queue Control." hexmask.long.byte 0x4 28.--31. 1. "RESERVED7,Reserved. Note: This register field is sticky." newline bitfld.long 0x4 26.--27. "VC0_NP_DATA_SCALE,VC0 Scale Non-Posted Data Credites. Note: This register field is sticky." "0,1,2,3" newline bitfld.long 0x4 24.--25. "VC0_NP_HDR_SCALE,VC0 Scale Non-Posted Header Credites. Note: This register field is sticky." "0,1,2,3" newline bitfld.long 0x4 21.--23. "VC0_NP_TLP_Q_MODE,Reserved. Note: This register field is sticky." "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 20. "RESERVED6,Reserved. Note: This register field is sticky." "0,1" newline hexmask.long.byte 0x4 12.--19. 1. "VC0_NP_HEADER_CREDIT,VC0 Non-Posted Header Credits. The number of initial non-posted header credits for VC0 used only in the segmented-buffer configuration. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R (sticky).." newline hexmask.long.word 0x4 0.--11. 1. "VC0_NP_DATA_CREDIT,VC0 Non-Posted Data Credits. The number of initial non-posted data credits for VC0 used only in the segmented-buffer configuration. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R (sticky) Note:.." line.long 0x8 "VC0_CPL_RX_Q_CTRL_OFF,Segmented-Buffer VC0 Completion Receive Queue Control." hexmask.long.byte 0x8 28.--31. 1. "RESERVED9,Reserved. Note: This register field is sticky." newline bitfld.long 0x8 26.--27. "VC0_CPL_DATA_SCALE,VC0 Scale CPL Data Credites. Note: This register field is sticky." "0,1,2,3" newline bitfld.long 0x8 24.--25. "VC0_CPL_HDR_SCALE,VC0 Scale CPL Header Credites. Note: This register field is sticky." "0,1,2,3" newline bitfld.long 0x8 21.--23. "VC0_CPL_TLP_Q_MODE,Reserved. Note: This register field is sticky." "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 20. "RESERVED8,Reserved. Note: This register field is sticky." "0,1" newline hexmask.long.byte 0x8 12.--19. 1. "VC0_CPL_HEADER_CREDIT,VC0 Completion Header Credits. The number of initial Completion header credits for VC0 used only in the segmented-buffer configuration. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R (sticky).." newline hexmask.long.word 0x8 0.--11. 1. "VC0_CPL_DATA_CREDIT,VC0 Completion Data Credits. The number of initial Completion data credits for VC0 used only in the segmented-buffer configuration. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R (sticky) Note:.." group.long (0x10C+0x700)++0x3 line.long 0x0 "GEN2_CTRL_OFF,This register is used to control various functions of the controller related to link training. lane reversal. and equalization." rbitfld.long 0x0 31. "RSVDP_31,Reserved for future use." "0,1" newline rbitfld.long 0x0 22.--23. "RSVDP_22,Reserved for future use." "0,1,2,3" newline bitfld.long 0x0 21. "GEN1_EI_INFERENCE,Electrical Idle Inference Mode at Gen1 Rate. Programmable mode to determine inferred electrical idle (EI) in Recovery.Speed or Loopback.Active (as slave) state at Gen1 speed by looking for a '1' value on RxElecIdle instead of looking.." "Use RxElecIdle signal to infer Electrical Idle,Use RxValid signal to infer Electrical Idle" newline bitfld.long 0x0 20. "SEL_DEEMPHASIS,Used to set the de-emphasis level for upstream ports. This bit selects the level of de-emphasis the link operates at. - 0: -6 dB - 1: -3.5 dB This field is reserved (fixed to '0') for M-PCIe. Note: The access attributes of this field are.." "0,1" newline bitfld.long 0x0 19. "CONFIG_TX_COMP_RX,Config Tx Compliance Receive Bit. When set to 1 signals LTSSM to transmit TS ordered sets with the compliance receive bit assert (equal to '1'). This field is reserved (fixed to '0') for M-PCIe. Note: The access attributes of this.." "0,1" newline bitfld.long 0x0 18. "CONFIG_PHY_TX_CHANGE,Config PHY Tx Swing. Controls the PHY transmitter voltage swing level. The controller drives the mac_phy_txswing output from this register bit field. - 0: Full Swing - 1: Low Swing This field is reserved (fixed to '0') for M-PCIe." "Full Swing,Low Swing" newline bitfld.long 0x0 17. "DIRECT_SPEED_CHANGE,Directed Speed Change. Writing '1' to this field instructs the LTSSM to initiate a speed change to Gen2 or Gen3 after the link is initialized at Gen1 speed. When the speed change occurs the controller will clear the contents of this.." "0,1" newline bitfld.long 0x0 16. "AUTO_LANE_FLIP_CTRL_EN,Enable Auto flipping of the lanes. You must set the CX_AUTO_LANE_FLIP_CTRL_EN configuration parameter to include the hardware for this feature in the controller. For more details see the 'Lane Reversal' appendix in the Databook." "0,1" newline bitfld.long 0x0 13.--15. "PRE_DET_LANE,Predetermined Lane for Auto Flip. This field defines which physical lane is connected to logical Lane0 by the flip operation performed in Detect. This field is used to restrict the receiver detect procedure to a particular lane when the.." "LANE0,LANE1,LANE3,LANE7,LANE15,?,?,?" newline hexmask.long.byte 0x0 8.--12. 1. "NUM_OF_LANES,Predetermined Number of Lanes. Defines the number of lanes which are connected and not bad. Used to limit the effective link width to ignore 'broken' or 'unused' lanes that detect a receiver. Indicates the number of lanes to check for exit.." newline hexmask.long.byte 0x0 0.--7. 1. "FAST_TRAINING_SEQ,Sets the Number of Fast Training Sequences (N_FTS) that the controller advertises as its N_FTS during Gen2 or Gen3 link training. This value is used to inform the link partner about the PHY's ability to recover synchronization after a.." rgroup.long (0x110+0x700)++0x3 line.long 0x0 "PHY_STATUS_OFF,PHY Status Register. Memory mapped register from phy_cfg_status GPIO input pins." hexmask.long 0x0 0.--31. 1. "PHY_STATUS,PHY Status. Data received directly from the phy_cfg_status bus. These is a GPIO register reflecting the values on the static phy_cfg_status input signals. The usage is left completely to the user and does not in any way influence controller.." group.long (0x114+0x700)++0x3 line.long 0x0 "PHY_CONTROL_OFF,PHY Control Register. Memory mapped register to cfg_phy_control GPIO output pins." hexmask.long 0x0 0.--31. 1. "PHY_CONTROL,PHY Control. Data sent directly to the cfg_phy_control bus. These is a GPIO register driving the values on the static cfg_phy_control output signals. The usage is left completely to the user and does not in any way influence controller.." group.long (0x11C+0x700)++0x77 line.long 0x0 "TRGT_MAP_CTRL_OFF,Programmable Target Map Control Register." hexmask.long.word 0x0 21.--31. 1. "TARGET_MAP_RESERVED_21_31,Reserved. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R (sticky)" newline hexmask.long.byte 0x0 16.--20. 1. "TARGET_MAP_INDEX,The number of the PF Function on which the Target Values are set. This register does not respect the Byte Enable setting. any write will affect all register bits." newline rbitfld.long 0x0 13.--15. "TARGET_MAP_RESERVED_13_15,Reserved. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R (sticky)" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 6. "TARGET_MAP_ROM,Target Value for the ROM page of the PF Function selected by the index number. This register does not respect the Byte Enable setting. any write will affect all register bits." "0,1" newline hexmask.long.byte 0x0 0.--5. 1. "TARGET_MAP_PF,Target Values for each BAR on the PF Function selected by the index number. This register does not respect the Byte Enable setting. any write will affect all register bits." line.long 0x4 "MSI_CTRL_ADDR_OFF,Integrated MSI Reception Module (iMRM) Address Register." hexmask.long 0x4 0.--31. 1. "MSI_CTRL_ADDR,Integrated MSI Reception Module Address. System specified address for MSI memory write transaction termination. Within the AXI Bridge every received Memory Write request is examined to see if it targets the MSI Address that has been.." line.long 0x8 "MSI_CTRL_UPPER_ADDR_OFF,Integrated MSI Reception Module Upper Address Register." hexmask.long 0x8 0.--31. 1. "MSI_CTRL_UPPER_ADDR,Integrated MSI Reception Module Upper Address. System specified upper address for MSI memory write transaction termination. Allows functions to support a 64-bit MSI address. Note: This register field is sticky." line.long 0xC "MSI_CTRL_INT_0_EN_OFF,Integrated MSI Reception Module Interrupt#i Enable Register." hexmask.long 0xC 0.--31. 1. "MSI_CTRL_INT_0_EN,MSI Interrupt#i Enable. Specifies which interrupts are enabled. When an MSI is received from a disabled interrupt no status bit gets set in MSI controller interrupt status register. Each bit corresponds to a single MSI Interrupt.." line.long 0x10 "MSI_CTRL_INT_0_MASK_OFF,Integrated MSI Reception Module Interrupt#i Mask Register." hexmask.long 0x10 0.--31. 1. "MSI_CTRL_INT_0_MASK,MSI Interrupt#i Mask. Allows enabled interrupts to be masked. When an MSI is received for a masked interrupt the corresponding status bit gets set in the interrupt status register but the msi_ctrl_int output is not set HIGH. Each bit.." line.long 0x14 "MSI_CTRL_INT_0_STATUS_OFF,Integrated MSI Reception Module Interrupt#i Status Register." hexmask.long 0x14 0.--31. 1. "MSI_CTRL_INT_0_STATUS,MSI Interrupt#i Status. When an MSI is detected for EP#i one bit in this register is set. The decoding of the data payload of the MSI Memory Write request determines which bit gets set. A status is bit is cleared by writing a 1 to.." line.long 0x18 "MSI_CTRL_INT_1_EN_OFF,Integrated MSI Reception Module Interrupt#i Enable Register." hexmask.long 0x18 0.--31. 1. "MSI_CTRL_INT_1_EN,MSI Interrupt#i Enable. Specifies which interrupts are enabled. When an MSI is received from a disabled interrupt no status bit gets set in MSI controller interrupt status register. Each bit corresponds to a single MSI Interrupt.." line.long 0x1C "MSI_CTRL_INT_1_MASK_OFF,Integrated MSI Reception Module Interrupt#i Mask Register." hexmask.long 0x1C 0.--31. 1. "MSI_CTRL_INT_1_MASK,MSI Interrupt#i Mask. Allows enabled interrupts to be masked. When an MSI is received for a masked interrupt the corresponding status bit gets set in the interrupt status register but the msi_ctrl_int output is not set HIGH. Each bit.." line.long 0x20 "MSI_CTRL_INT_1_STATUS_OFF,Integrated MSI Reception Module Interrupt#i Status Register." hexmask.long 0x20 0.--31. 1. "MSI_CTRL_INT_1_STATUS,MSI Interrupt#i Status. When an MSI is detected for EP#i one bit in this register is set. The decoding of the data payload of the MSI Memory Write request determines which bit gets set. A status is bit is cleared by writing a 1 to.." line.long 0x24 "MSI_CTRL_INT_2_EN_OFF,Integrated MSI Reception Module Interrupt#i Enable Register." hexmask.long 0x24 0.--31. 1. "MSI_CTRL_INT_2_EN,MSI Interrupt#i Enable. Specifies which interrupts are enabled. When an MSI is received from a disabled interrupt no status bit gets set in MSI controller interrupt status register. Each bit corresponds to a single MSI Interrupt.." line.long 0x28 "MSI_CTRL_INT_2_MASK_OFF,Integrated MSI Reception Module Interrupt#i Mask Register." hexmask.long 0x28 0.--31. 1. "MSI_CTRL_INT_2_MASK,MSI Interrupt#i Mask. Allows enabled interrupts to be masked. When an MSI is received for a masked interrupt the corresponding status bit gets set in the interrupt status register but the msi_ctrl_int output is not set HIGH. Each bit.." line.long 0x2C "MSI_CTRL_INT_2_STATUS_OFF,Integrated MSI Reception Module Interrupt#i Status Register." hexmask.long 0x2C 0.--31. 1. "MSI_CTRL_INT_2_STATUS,MSI Interrupt#i Status. When an MSI is detected for EP#i one bit in this register is set. The decoding of the data payload of the MSI Memory Write request determines which bit gets set. A status is bit is cleared by writing a 1 to.." line.long 0x30 "MSI_CTRL_INT_3_EN_OFF,Integrated MSI Reception Module Interrupt#i Enable Register." hexmask.long 0x30 0.--31. 1. "MSI_CTRL_INT_3_EN,MSI Interrupt#i Enable. Specifies which interrupts are enabled. When an MSI is received from a disabled interrupt no status bit gets set in MSI controller interrupt status register. Each bit corresponds to a single MSI Interrupt.." line.long 0x34 "MSI_CTRL_INT_3_MASK_OFF,Integrated MSI Reception Module Interrupt#i Mask Register." hexmask.long 0x34 0.--31. 1. "MSI_CTRL_INT_3_MASK,MSI Interrupt#i Mask. Allows enabled interrupts to be masked. When an MSI is received for a masked interrupt the corresponding status bit gets set in the interrupt status register but the msi_ctrl_int output is not set HIGH. Each bit.." line.long 0x38 "MSI_CTRL_INT_3_STATUS_OFF,Integrated MSI Reception Module Interrupt#i Status Register." hexmask.long 0x38 0.--31. 1. "MSI_CTRL_INT_3_STATUS,MSI Interrupt#i Status. When an MSI is detected for EP#i one bit in this register is set. The decoding of the data payload of the MSI Memory Write request determines which bit gets set. A status is bit is cleared by writing a 1 to.." line.long 0x3C "MSI_CTRL_INT_4_EN_OFF,Integrated MSI Reception Module Interrupt#i Enable Register." hexmask.long 0x3C 0.--31. 1. "MSI_CTRL_INT_4_EN,MSI Interrupt#i Enable. Specifies which interrupts are enabled. When an MSI is received from a disabled interrupt no status bit gets set in MSI controller interrupt status register. Each bit corresponds to a single MSI Interrupt.." line.long 0x40 "MSI_CTRL_INT_4_MASK_OFF,Integrated MSI Reception Module Interrupt#i Mask Register." hexmask.long 0x40 0.--31. 1. "MSI_CTRL_INT_4_MASK,MSI Interrupt#i Mask. Allows enabled interrupts to be masked. When an MSI is received for a masked interrupt the corresponding status bit gets set in the interrupt status register but the msi_ctrl_int output is not set HIGH. Each bit.." line.long 0x44 "MSI_CTRL_INT_4_STATUS_OFF,Integrated MSI Reception Module Interrupt#i Status Register." hexmask.long 0x44 0.--31. 1. "MSI_CTRL_INT_4_STATUS,MSI Interrupt#i Status. When an MSI is detected for EP#i one bit in this register is set. The decoding of the data payload of the MSI Memory Write request determines which bit gets set. A status is bit is cleared by writing a 1 to.." line.long 0x48 "MSI_CTRL_INT_5_EN_OFF,Integrated MSI Reception Module Interrupt#i Enable Register." hexmask.long 0x48 0.--31. 1. "MSI_CTRL_INT_5_EN,MSI Interrupt#i Enable. Specifies which interrupts are enabled. When an MSI is received from a disabled interrupt no status bit gets set in MSI controller interrupt status register. Each bit corresponds to a single MSI Interrupt.." line.long 0x4C "MSI_CTRL_INT_5_MASK_OFF,Integrated MSI Reception Module Interrupt#i Mask Register." hexmask.long 0x4C 0.--31. 1. "MSI_CTRL_INT_5_MASK,MSI Interrupt#i Mask. Allows enabled interrupts to be masked. When an MSI is received for a masked interrupt the corresponding status bit gets set in the interrupt status register but the msi_ctrl_int output is not set HIGH. Each bit.." line.long 0x50 "MSI_CTRL_INT_5_STATUS_OFF,Integrated MSI Reception Module Interrupt#i Status Register." hexmask.long 0x50 0.--31. 1. "MSI_CTRL_INT_5_STATUS,MSI Interrupt#i Status. When an MSI is detected for EP#i one bit in this register is set. The decoding of the data payload of the MSI Memory Write request determines which bit gets set. A status is bit is cleared by writing a 1 to.." line.long 0x54 "MSI_CTRL_INT_6_EN_OFF,Integrated MSI Reception Module Interrupt#i Enable Register." hexmask.long 0x54 0.--31. 1. "MSI_CTRL_INT_6_EN,MSI Interrupt#i Enable. Specifies which interrupts are enabled. When an MSI is received from a disabled interrupt no status bit gets set in MSI controller interrupt status register. Each bit corresponds to a single MSI Interrupt.." line.long 0x58 "MSI_CTRL_INT_6_MASK_OFF,Integrated MSI Reception Module Interrupt#i Mask Register." hexmask.long 0x58 0.--31. 1. "MSI_CTRL_INT_6_MASK,MSI Interrupt#i Mask. Allows enabled interrupts to be masked. When an MSI is received for a masked interrupt the corresponding status bit gets set in the interrupt status register but the msi_ctrl_int output is not set HIGH. Each bit.." line.long 0x5C "MSI_CTRL_INT_6_STATUS_OFF,Integrated MSI Reception Module Interrupt#i Status Register." hexmask.long 0x5C 0.--31. 1. "MSI_CTRL_INT_6_STATUS,MSI Interrupt#i Status. When an MSI is detected for EP#i one bit in this register is set. The decoding of the data payload of the MSI Memory Write request determines which bit gets set. A status is bit is cleared by writing a 1 to.." line.long 0x60 "MSI_CTRL_INT_7_EN_OFF,Integrated MSI Reception Module Interrupt#i Enable Register." hexmask.long 0x60 0.--31. 1. "MSI_CTRL_INT_7_EN,MSI Interrupt#i Enable. Specifies which interrupts are enabled. When an MSI is received from a disabled interrupt no status bit gets set in MSI controller interrupt status register. Each bit corresponds to a single MSI Interrupt.." line.long 0x64 "MSI_CTRL_INT_7_MASK_OFF,Integrated MSI Reception Module Interrupt#i Mask Register." hexmask.long 0x64 0.--31. 1. "MSI_CTRL_INT_7_MASK,MSI Interrupt#i Mask. Allows enabled interrupts to be masked. When an MSI is received for a masked interrupt the corresponding status bit gets set in the interrupt status register but the msi_ctrl_int output is not set HIGH. Each bit.." line.long 0x68 "MSI_CTRL_INT_7_STATUS_OFF,Integrated MSI Reception Module Interrupt#i Status Register." hexmask.long 0x68 0.--31. 1. "MSI_CTRL_INT_7_STATUS,MSI Interrupt#i Status. When an MSI is detected for EP#i one bit in this register is set. The decoding of the data payload of the MSI Memory Write request determines which bit gets set. A status is bit is cleared by writing a 1 to.." line.long 0x6C "MSI_GPIO_IO_OFF,Integrated MSI Reception Module General Purpose IO Register." hexmask.long 0x6C 0.--31. 1. "MSI_GPIO_REG,MSI GPIO Register. The contents of this register drives the top-level GPIO msi_ctrl_io[31:0] Note: This register field is sticky." line.long 0x70 "CLOCK_GATING_CTRL_OFF,This register enables you to disable dynamic clock gating. By default dynamic clock gating is on. allowing the controller to autonomously enable and disable its clocks. The clock gating is performed in the clock and reset module." hexmask.long 0x70 2.--31. 1. "RSVDP_2,Reserved for future use." newline bitfld.long 0x70 1. "AXI_CLK_GATING_EN,AXI Clock Gating Enable. This register enables the AXI Bridge to autonomously enable and disable the AXI Master clock the AXI Slave clock and the AXI DBI slave clock. The DWC_pcie_clk_rst.v module provides the gated clock.." "Disable,Enable" newline bitfld.long 0x70 0. "RADM_CLK_GATING_EN,RADM Clock Gating Enable. This register if set enables the RADM to autonomously enable and disable its clock. The DWC_pcie_clk_rst.v module provides the gated clock radm_clk_g to the RADM and is enabled when the controllers clock.." "Disable,Enable" line.long 0x74 "GEN3_RELATED_OFF,Gen3 Control Register. There is no Gen3-specific N_FTS field. The N_FTS field in the 'Link Width and Speed Change Control Register' is used for both Gen2 and Gen3 speed modes. There is no Gen3-specific 'Directed Speed Change' field. The.." hexmask.long.byte 0x74 26.--31. 1. "RSVDP_26,Reserved for future use." newline bitfld.long 0x74 23. "GEN3_EQ_INVREQ_EVAL_DIFF_DISABLE,Eq InvalidRequest and RxEqEval Different Time Assertion Disable. Disable the assertion of Eq InvalidRequest and RxEqEval at different time. Note: When CX_GEN4_SPEED/CX_GEN5_SPEED this register is shared for Gen3 and.." "0,1" newline rbitfld.long 0x74 19.--20. "RSVDP_19,Reserved for future use." "0,1,2,3" newline bitfld.long 0x74 18. "GEN3_DC_BALANCE_DISABLE,DC Balance Disable. Disable DC Balance feature. Note: When CX_GEN4_SPEED/CX_GEN5_SPEED this register is shared for Gen3 and Gen4/Gen5 data rate. Note: This register field is sticky." "0,1" newline bitfld.long 0x74 17. "GEN3_DLLP_XMT_DELAY_DISABLE,DLLP Transmission Delay Disable. Disable delay transmission of DLLPs before equalization. Note: When CX_GEN4_SPEED/CX_GEN5_SPEED this register is shared for Gen3 and Gen4/Gen5 data rate. Note: This register field is sticky." "0,1" newline bitfld.long 0x74 16. "GEN3_EQUALIZATION_DISABLE,Equalization Disable. Disable equalization feature. This bit cannot be changed once the LTSSM starts link training. Note: When CX_GEN4_SPEED/CX_GEN5_SPEED this register is shared for Gen3 and Gen4/Gen5 data rate. Note: This.." "0,1" newline rbitfld.long 0x74 14.--15. "RSVDP_14,Reserved for future use." "0,1,2,3" newline bitfld.long 0x74 13. "RXEQ_RGRDLESS_RXTS,When set to '1' the controller as Gen3 EQ master asserts RxEqEval to instruct the PHY to do Rx adaptation and evaluation after a 500ns timeout from a new preset request. - 0: mac_phy_rxeqeval asserts after 1us and 2 TS1 received from.." "mac_phy_rxeqeval asserts after 1us and 2 TS1..,mac_phy_rxeqeval asserts after 500ns regardless.." newline bitfld.long 0x74 12. "RXEQ_PH01_EN,Rx Equalization Phase 0/Phase 1 Hold Enable. When this bit is set the upstream port holds phase 0 (the downstream port holds phase 1) for 10ms. Holding phase 0 or phase 1 can be used to allow sufficient time for Rx Equalization to be.." "Tx equalization only in phase 2/3,No Tx equalization" newline bitfld.long 0x74 11. "EQ_REDO,Equalization Redo Disable. Disable autonomous mechanism for requesting to redo the equalization process. The received presets or coefficients mismatch in Recovery.RcvrLock after Recovery EQ phases causes the EQ redo requests. If the EQ redo is.." "0,1" newline bitfld.long 0x74 10. "EQ_EIEOS_CNT,Equalization EIEOS Count Reset Disable. Disable requesting reset of EIEOS count during equalization. Note: When CX_GEN4_SPEED/CX_GEN5_SPEED this register is shared for Gen3 and Gen4/Gen5 data rate. Note: This register field is sticky." "0,1" newline bitfld.long 0x74 9. "EQ_PHASE_2_3,Equalization Phase 2 and Phase 3 Disable. This applies to downstream ports only. Note: When CX_GEN4_SPEED/CX_GEN5_SPEED this register is shadow register for Gen3 and Gen4/Gen5 data rate. If RATE_SHADOW_SEL==00b this register is for Gen3.." "0,1" newline bitfld.long 0x74 8. "DISABLE_SCRAMBLER_GEN_3,Disable Scrambler for Gen3 and Gen4 Data Rate. The Gen3 and Gen4 scrambler/descrambler within the controller needs to be disabled when the scrambling function is implemented outside of the controller (for example within the PHY)." "0,1" newline hexmask.long.byte 0x74 1.--7. 1. "RSVDP_1,Reserved for future use." newline bitfld.long 0x74 0. "GEN3_ZRXDC_NONCOMPL,Gen3 Receiver Impedance ZRX-DC Not Compliant. Receivers that operate at 8.0 GT/s with an impedance other than the range defined by the ZRX-DC parameter for 2.5 GT/s (40-60 Ohms) must meet additional behavior requirements in the.." "The receiver complies with the ZRX-DC parameter..,The receiver does not comply with the ZRX-DC.." group.long (0x1A8+0x700)++0x7 line.long 0x0 "GEN3_EQ_CONTROL_OFF,Gen3 EQ Control Register. This register controls equalization for Phase2 in an upstream port (USP). or Phase3 in a downstream port (DSP). M-PCIe doesn't have Conventional PCIe Gen3 feature. The registers of this section do not exist." hexmask.long.byte 0x0 27.--31. 1. "RSVDP_27,Reserved for future use." newline bitfld.long 0x0 26. "GEN3_REQ_SEND_CONSEC_EIEOS_FOR_PSET_MAP,Request controller to send back-to-back EIEOS in Recovery.RcvrLock state until presets to coefficients mapping is complete. - 0: Do not request - 1: request Note: Gen3 and Gen4 share the same register bit and have.." "Do not request,request" newline bitfld.long 0x0 25. "GEN3_EQ_PSET_REQ_AS_COEF,GEN3_EQ_PSET_REQ_AS_COEF is an internally reserved field. Do not use. Note: This register field is sticky." "0,1" newline bitfld.long 0x0 24. "GEN3_EQ_FOM_INC_INITIAL_EVAL,Include Initial FOM. Include or not the FOM feedback from the initial preset evaluation performed in the EQ Master when finding the highest FOM among all preset evaluations. - 0: Do not include - 1: Include Note: When.." "Do not include,Include" newline hexmask.long.word 0x0 8.--23. 1. "GEN3_EQ_PSET_REQ_VEC,Preset Request Vector. Requesting of Presets during the initial part of the EQ Master Phase. Encoding scheme is as follows: Bit [15:0] =0x0: No preset is requested and evaluated in EQ Master Phase. Bit [i] =1: 'Preset=i' is requested.." newline rbitfld.long 0x0 7. "RSVDP_7,Reserved for future use." "0,1" newline bitfld.long 0x0 6. "GEN3_LOWER_RATE_EQ_REDO_ENABLE,Support EQ redo and lower rate change: - 0: not support - 1: support Note: Gen3 and Gen4 share the same register bit and have the same feature. Note: This register field is sticky." "not support,support" newline bitfld.long 0x0 5. "GEN3_EQ_EVAL_2MS_DISABLE,Phase2_3 2 ms Timeout Disable. Determine behavior in Phase2 for USP (Phase3 if DSP) when the PHY does not respond within 2ms to the assertion of RxEqEval: - 0: abort the current evaluation stop any attempt to modify the remote.." "abort the current evaluation,ignore the 2ms timeout and continue as normal" newline bitfld.long 0x0 4. "GEN3_EQ_PHASE23_EXIT_MODE,Behavior After 24 ms Timeout (when optimal settings are not found). For a USP: Determine next LTSSM state from Phase2 after 24ms Timeout - 0: Recovery.Speed - 1: Recovery.Equalization.Phase3 When optimal settings are not found.." "Equalization Phase 3 Successful status bit is..,Recovery" newline hexmask.long.byte 0x0 0.--3. 1. "GEN3_EQ_FB_MODE,Feedback Mode. - 0000b: Direction Change - 0001b: Figure Of Merit - 0010b: Reserved - .....: Reserved - 1111b: Reserved Note: When CX_GEN4_SPEED/CX_GEN5_SPEED this register is a shadow register for Gen3 and Gen4/Gen5 data rate. If.." line.long 0x4 "GEN3_EQ_FB_MODE_DIR_CHANGE_OFF,Gen3 EQ Direction Change Feedback Mode Control Register. Equalization controls to be used in Phase2 (USP) or Phase 3 (DSP). when you set the Feedback Mode in 'Gen3 EQ Control Register' to 'Direction Change.' These fields.." hexmask.long.word 0x4 18.--31. 1. "RSVDP_18,Reserved for future use." newline hexmask.long.byte 0x4 14.--17. 1. "GEN3_EQ_FMDC_MAX_POST_CUSROR_DELTA,Convergence Window Aperture for C+1. Post-cursor coefficients maximum delta within the convergence window depth. Allowed range: 0 1 2 ..15. Note: When CX_GEN4_SPEED/CX_GEN5_SPEED this register is shadow register for.." newline hexmask.long.byte 0x4 10.--13. 1. "GEN3_EQ_FMDC_MAX_PRE_CUSROR_DELTA,Convergence Window Aperture for C-1. Pre-cursor coefficients maximum delta within the convergence window depth. Allowed range: 0 1 2 ..15. Note: When CX_GEN4_SPEED/CX_GEN5_SPEED this register is shadow register for Gen3.." newline hexmask.long.byte 0x4 5.--9. 1. "GEN3_EQ_FMDC_N_EVALS,Convergence Window Depth. Number of consecutive evaluations considered in Phase 2/3 when determining if optimal coefficients have been found. Allowed range: 0 1 2 ..16 up to a maximum of CX_GEN3_EQ_COEFQ_DEPTH. When set to 0 EQ.." newline hexmask.long.byte 0x4 0.--4. 1. "GEN3_EQ_FMDC_T_MIN_PHASE23,Minimum Time (in ms) To Remain in EQ Master Phase. The LTSSM stays in EQ Master phase for at least this amount of time before starting to check for convergence of the coefficients. Allowed values 0 1 ... 24. Note: When.." group.long (0x1B4+0x700)++0x27 line.long 0x0 "ORDER_RULE_CTRL_OFF,Order Rule Control Register." hexmask.long.word 0x0 16.--31. 1. "RSVDP_16,Reserved for future use." newline hexmask.long.byte 0x0 8.--15. 1. "CPL_PASS_P,Completion Passing Posted Ordering Rule Control. Determines if CPL can pass halted P queue. - 0: CPL can not pass P (recommended) - 1: CPL can pass P" newline hexmask.long.byte 0x0 0.--7. 1. "NP_PASS_P,Non-Posted Passing Posted Ordering Rule Control. Determines if NP can pass halted P queue. - 0 : NP can not pass P (recommended). - 1 : NP can pass P" line.long 0x4 "PIPE_LOOPBACK_CONTROL_OFF,PIPE Loopback Control Register." bitfld.long 0x4 31. "PIPE_LOOPBACK,PIPE Loopback Enable. Indicates RMMI Loopback if M-PCIe. Note: This register field is sticky." "0,1" newline hexmask.long.byte 0x4 27.--30. 1. "RSVDP_27,Reserved for future use." newline bitfld.long 0x4 24.--26. "RXSTATUS_VALUE,RXSTATUS_VALUE is an internally reserved field. Do not use." "0,1,2,3,4,5,6,7" newline rbitfld.long 0x4 22.--23. "RSVDP_22,Reserved for future use." "0,1,2,3" newline hexmask.long.byte 0x4 16.--21. 1. "RXSTATUS_LANE,RXSTATUS_LANE is an internally reserved field. Do not use. Note: This register field is sticky." newline hexmask.long.word 0x4 0.--15. 1. "LPBK_RXVALID,LPBK_RXVALID is an internally reserved field. Do not use. Note: This register field is sticky." line.long 0x8 "MISC_CONTROL_1_OFF,DBI Read-Only Write Enable Register." hexmask.long.word 0x8 22.--31. 1. "RSVDP_22,Reserved for future use." newline bitfld.long 0x8 21. "P2P_ERR_RPT_CTRL,Determines whether to track completion of transmitted Non-Posted TLPs in P2P mode. - 0: Do not track completion - 1: Track completion Note: This register field is sticky." "Do not track completion,Track completion" newline bitfld.long 0x8 20. "P2P_TRACK_CPL_TO_REG,Determines whether to enable Peer to Peer (P2P) error reporting. - 0: Disable P2P error reporting - 1: Enable P2P error reporting Note: This register field is sticky." "Disable P2P error reporting,Enable P2P error reporting" newline bitfld.long 0x8 18.--19. "TARGET_ABOVE_CONFIG_LIMIT_REG,Configuration requests with an address greater than CONFIG_LIMIT_REG are directed to either ELBI or TRGT1 interface based on the setting of this field. This field can have the following values: - 1: ELBI - 2: TRGT1 Note:.." "?,ELBI,TRGT1,?" newline hexmask.long.word 0x8 8.--17. 1. "CONFIG_LIMIT_REG,Configuration requests are directed either to CDM or ELBI/RTRGT1 based on the value of this field. - Configuration requests with an address less CONFIG_LIMIT_REG are directed to the CDM - Configuration requests with an address greater.." newline bitfld.long 0x8 7. "CFG_TLP_BYPASS_EN_REG,Setting of this field defines which field TARGET_ABOVE_CONFIG_LIMIT_REG or CONFIG_LIMIT_REG decides the destination of Configuration requests. This field can have the following values: - 0: Configuration TLPs are routed according to.." "Configuration TLPs are routed according to the..,Configuration TLPs are routed according to the.." newline bitfld.long 0x8 6. "CPLQ_MNG_EN,This field enables the Completion Queue Management feature. Note: This register field is sticky." "0,1" newline bitfld.long 0x8 5. "ARI_DEVICE_NUMBER,When ARI is enabled this field enables use of the device ID. Note: This register field is sticky." "0,1" newline bitfld.long 0x8 4. "DISABLE_AUTO_LTR_CLR_MSG,Disable the autonomous generation of LTR clear message in upstream port. This field can have the following values: - 0: Allow the autonomous generation of LTR clear message. - 1: Disable the autonomous generation of LTR clear.." "Allow the autonomous generation of LTR clear..,Disable the autonomous generation of LTR clear.." newline bitfld.long 0x8 3. "SIMPLIFIED_REPLAY_TIMER,Enables Simplified Replay Timer (Gen4). For more details see 'Transmit Replay' in 'Transmit TLP Processing' section in the 'Controller Operations' chapter of the Databook. Simplified Replay Timer can have the following Values: -.." "0,1" newline bitfld.long 0x8 2. "UR_CA_MASK_4_TRGT1,When this field is set to '1' the controller suppresses error logging error message generation and CPL generation for non-posted requests TLPs (with UR filtering status) forwarded to your application (that is when DEFAULT_TARGET.." "0,1" newline bitfld.long 0x8 1. "DEFAULT_TARGET,Default target for an IO or MEM request with UR/CA/CRS received. Based on the value of this field the controller either drops or forwards these requests to your application. - 0: The controller drops all incoming I/O or MEM requests (after.." "The controller drops all incoming I/O or MEM..,The controller forwards all incoming I/O or MEM.." newline bitfld.long 0x8 0. "DBI_RO_WR_EN,Write to RO Registers Using DBI. Your application can write to some RO and HwInit register fields through the DBI when you set this field to '1'. For more details see 'Writing to Read-Only Registers' in 'Register Module LBC and DBI'.." "0,1" line.long 0xC "MULTI_LANE_CONTROL_OFF,UpConfigure Multi-lane Control Register. Used when upsizing or downsizing the link width through Configuration state without bringing the link down. For more details. see the 'Link Establishment' section in the 'Controller.." hexmask.long.tbyte 0xC 8.--31. 1. "RSVDP_8,Reserved for future use." newline bitfld.long 0xC 7. "UPCONFIGURE_SUPPORT,Upconfigure Support. The controller sends this value as the Link Upconfigure Capability in TS2 Ordered Sets in Configuration.Complete state. This field is reserved (fixed to '0') for M-PCIe. Note: This register field is sticky." "0,1" newline bitfld.long 0xC 6. "DIRECT_LINK_WIDTH_CHANGE,Directed Link Width Change. The controller always moves to Configuration state through Recovery state when this bit is set to '1'. - If the upconfigure_capable variable is '1' and the PCIE_CAP_HW_AUTO_WIDTH_DISABLE bit in.." "0,1" newline hexmask.long.byte 0xC 0.--5. 1. "TARGET_LINK_WIDTH,Target Link Width. Values correspond to: - 6'b000000: Controller does not start upconfigure or autonomous width downsizing in the Configuration state. - 6'b000001: x1 - 6'b000010: x2 - 6'b000100: x4 - 6'b001000: x8 - 6'b010000: x16 -.." line.long 0x10 "PHY_INTEROP_CTRL_OFF,PHY Interoperability Control Register." hexmask.long.tbyte 0x10 12.--31. 1. "RSVDP_12,Reserved for future use." newline bitfld.long 0x10 10. "L1_CLK_SEL,L1 Clock control bit. This field is reserved for internal use. You should not write to this field and change the default unless specifically instructed by Synopsys support. - 1: Controller does not request aux_clk switch and core_clk gating in.." "Controller requests aux_clk switch and core_clk..,Controller does not request aux_clk switch and.." newline rbitfld.long 0x10 9. "L1_NOWAIT_P1,L1 entry control bit. This field is reserved for internal use. You should not write to this field and change the default unless specifically instructed by Synopsys support. - 1: Controller does not wait for PHY to acknowledge transition to.." "Controller waits for the PHY to acknowledge..,Controller does not wait for PHY to acknowledge.." newline bitfld.long 0x10 8. "L1SUB_EXIT_MODE,L1 Exit Control Using phy_mac_pclkack_n. This field is reserved for internal use. You should not write to this field and change the default unless specifically instructed by Synopsys support. - 1: Controller exits L1 without waiting for.." "Controller waits for the PHY to assert..,Controller exits L1 without waiting for the PHY.." newline rbitfld.long 0x10 7. "RSVDP_7,Reserved for future use." "0,1" newline hexmask.long.byte 0x10 0.--6. 1. "RXSTANDBY_CONTROL,Rxstandby Control. Bits 0..5 determine if the controller asserts the RxStandby signal (mac_phy_rxstandby) in the indicated condition. Bit 6 enables the controller to perform the RxStandby/RxStandbyStatus handshake. This field is.." line.long 0x14 "TRGT_CPL_LUT_DELETE_ENTRY_OFF,TRGT_CPL_LUT Delete Entry Control register. Using this register you can delete one entry in the target completion LUT. You should only use this register when you know that your application will never send the completion.." bitfld.long 0x14 31. "DELETE_EN,This is a one-shot bit. A '1' write to this bit triggers the deletion of the target completion LUT entry that is specified in the LOOK_UP_ID field. This is a self-clearing register field. Reading from this register field always returns a '0'." "0,1" newline hexmask.long 0x14 0.--30. 1. "LOOK_UP_ID,This number selects one entry to delete of the TRGT_CPL_LUT." line.long 0x18 "LINK_FLUSH_CONTROL_OFF,Link Reset Request Flush Control Register." hexmask.long.byte 0x18 24.--31. 1. "RSVD_I_8,This is an internally reserved field. Do not use. Note: This register field is sticky." newline hexmask.long.tbyte 0x18 1.--23. 1. "RSVDP_1,Reserved for future use." newline bitfld.long 0x18 0. "AUTO_FLUSH_EN,Enables automatic flushing of pending requests before sending the reset request to the application logic to reset the PCIe controller and the AXI Bridge. The flushing process is initiated if any of the following events occur: - Hot reset.." "0,1" line.long 0x1C "AMBA_ERROR_RESPONSE_DEFAULT_OFF,AXI Bridge Slave Error Response Register." hexmask.long.word 0x1C 16.--31. 1. "RSVDP_16,Reserved for future use." newline hexmask.long.byte 0x1C 10.--15. 1. "AMBA_ERROR_RESPONSE_MAP,AXI Slave Response Error Map. Allows you to selectively map the errors received from the PCIe completion (for non-posted requests) to the AXI slave responses slv_rresp or slv_bresp. The recommended setting is SLVERR. CRS is.." newline hexmask.long.byte 0x1C 5.--9. 1. "RSVDP_5,Reserved for future use." newline bitfld.long 0x1C 3.--4. "AMBA_ERROR_RESPONSE_CRS,CRS Slave Error Response Mapping. Determines the AXI slave response for CRS completions. For more details see 'Error Handling' in the AXI chapter of the Databook. AHB: - always returns OKAY AXI: - 00: OKAY - 01: OKAY with all.." "OKAY,OKAY with all FFFF_FFFF data for all CRS..,?,?" newline bitfld.long 0x1C 2. "AMBA_ERROR_RESPONSE_VENDORID,Vendor ID Non-existent Slave Error Response Mapping. Determines the AXI slave response for errors on reads to non-existent Vendor ID register. For more details see 'Error Handling' in the AXI chapter of the Databook. AHB: -.." "OKAY,SLVERR/DECERR" newline rbitfld.long 0x1C 1. "RSVDP_1,Reserved for future use." "0,1" newline bitfld.long 0x1C 0. "AMBA_ERROR_RESPONSE_GLOBAL,Global Slave Error Response Mapping. Determines the AXI slave response for all error scenarios on non-posted requests. For more details see 'Error Handling' in the AXI chapter of the Databook. AHB: - 0: OKAY (with FFFF data for.." "OKAY,SLVERR/DECERR" line.long 0x20 "AMBA_LINK_TIMEOUT_OFF,Link Down AXI Bridge Slave Timeout Register. If your application AXI master issues outbound requests to the AXI bridge slave interface before the PCIe link is operational. the controller starts a 'flush' timer. The timeout value of.." hexmask.long.tbyte 0x20 9.--31. 1. "RSVDP_9,Reserved for future use." newline bitfld.long 0x20 8. "LINK_TIMEOUT_ENABLE_DEFAULT,Disable Flush. You can disable the flush feature by setting this field to '1'. Note: This register field is sticky." "0,1" newline hexmask.long.byte 0x20 0.--7. 1. "LINK_TIMEOUT_PERIOD_DEFAULT,Timeout Value (ms). The timer will timeout and then flush the bridge TX request queues after this amount of time. The timer counts when there are pending outbound AXI slave interface requests and the PCIe TX link is not.." line.long 0x24 "AMBA_ORDERING_CTRL_OFF,AMBA Ordering Control." hexmask.long.tbyte 0x24 8.--31. 1. "RSVDP_8,Reserved for future use." newline bitfld.long 0x24 7. "AX_MSTR_ZEROLREAD_FW,AXI Master Zero Length Read Forward to the application. The DW PCIe controller AXI bridge is able to terminate in order with the Posted transactions the zero length read implementing the PCIe express flush semantics of the Posted.." "The zero length Read is terminated at the DW..,The zero length Read is forward to the application" newline rbitfld.long 0x24 5.--6. "RSVDP_5,Reserved for future use." "0,1,2,3" newline bitfld.long 0x24 3.--4. "AX_MSTR_ORDR_P_EVENT_SEL,AXI Master Posted Ordering Event Selector. This field selects how the master interface determines when a P write is completed when enforcing the PCIe ordering rule 'NP must not pass P' at the AXI Master Interface. The AXI.." "B'last event: wait for the all of the write..,AW'last event: wait until the complete Posted..,This setting will not affect:,?" newline rbitfld.long 0x24 2. "RSVDP_2,Reserved for future use." "0,1" newline bitfld.long 0x24 1. "AX_SNP_EN,AXI Serialize Non-Posted Requests Enable. This field enables the AXI Bridge to serialize same ID Non-Posted Read/Write Requests on the wire. Serialization implies one outstanding same ID NP Read or Write on the wire and used to avoid AXI RAR.." "0,1" newline rbitfld.long 0x24 0. "RSVDP_0,Reserved for future use." "0,1" group.long (0x1E0+0x700)++0xB line.long 0x0 "COHERENCY_CONTROL_1_OFF,ACE Cache Coherency Control Register 1" hexmask.long 0x0 2.--31. 1. "CFG_MEMTYPE_BOUNDARY_LOW_ADDR,Boundary Lower Address For Memory Type. Bits [31:0] of dword-aligned address of the boundary for Memory type. The two lower address LSBs are '00'. Addresses up to but not including this value are in the lower address space.." newline rbitfld.long 0x0 1. "RSVDP_1,Reserved for future use." "0,1" newline bitfld.long 0x0 0. "CFG_MEMTYPE_VALUE,Sets the memory type for the lower and upper parts of the address space: - 0: lower = Peripheral; upper = Memory - 1: lower = Memory type; upper = Peripheral Note: This register field is sticky." "lower = Peripheral; upper = Memory,lower = Memory type; upper = Peripheral" line.long 0x4 "COHERENCY_CONTROL_2_OFF,ACE Cache Coherency Control Register 2" hexmask.long 0x4 0.--31. 1. "CFG_MEMTYPE_BOUNDARY_HIGH_ADDR,Boundary Upper Address For Memory Type. Bits [63:32] of the 64-bit dword-aligned address of the boundary for Memory type. Note: This register field is sticky." line.long 0x8 "COHERENCY_CONTROL_3_OFF,ACE Cache Coherency Control Register 3" hexmask.long.byte 0x8 27.--30. 1. "CFG_MSTR_AWCACHE_VALUE,Master Write CACHE Signal Value. Value of the individual bits in mstr_awcache when CFG_MSTR_AWCACHE_MODE is '1'. Note: not applicable to message requests; for message requests the value of mstr_awcache is always '0000' Note: This.." newline hexmask.long.byte 0x8 19.--22. 1. "CFG_MSTR_ARCACHE_VALUE,Master Read CACHE Signal Value. Value of the individual bits in mstr_arcache when CFG_MSTR_ARCACHE_MODE is '1'. Note: This register field is sticky." newline hexmask.long.byte 0x8 11.--14. 1. "CFG_MSTR_AWCACHE_MODE,Master Write CACHE Signal Behavior. Defines how the individual bits in mstr_awcache are controlled: - 0: set automatically by the AXI master - 1: set by the value of the corresponding bit of the CFG_MSTR_AWCACHE_VALUE field Note:.." newline hexmask.long.byte 0x8 3.--6. 1. "CFG_MSTR_ARCACHE_MODE,Master Read CACHE Signal Behavior. Defines how the individual bits in mstr_arcache are controlled: - 0: set automatically by the AXI master - 1: set by the value of the corresponding bit of the CFG_MSTR_ARCACHE_VALUE field Note:.." group.long (0x1F0+0x700)++0x7 line.long 0x0 "AXI_MSTR_MSG_ADDR_LOW_OFF,Lower 20 bits of the programmable AXI address where Messages coming from wire are mapped to. Bits [11:0] of the register are tied to zero for the address to be 4k-aligned. In previous releases. the third and fourth DWORDs of a.." hexmask.long.tbyte 0x0 12.--31. 1. "CFG_AXIMSTR_MSG_ADDR_LOW,Lower 20 bits of the programmable AXI address for Messages. Note: This register field is sticky." newline hexmask.long.word 0x0 0.--11. 1. "CFG_AXIMSTR_MSG_ADDR_LOW_RESERVED,Reserved for future use. Note: This register field is sticky." line.long 0x4 "AXI_MSTR_MSG_ADDR_HIGH_OFF,Upper 32 bits of the programmable AXI address where Messages coming from wire are mapped to." hexmask.long 0x4 0.--31. 1. "CFG_AXIMSTR_MSG_ADDR_HIGH,Upper 32 bits of the programmable AXI address for Messages. Note: This register field is sticky." rgroup.long (0x1F8+0x700)++0x7 line.long 0x0 "PCIE_VERSION_NUMBER_OFF,PCIe Controller IIP Release Version Number. The version number is given in hex format. You should convert each pair of hex characters to ASCII to interpret. Using 4.70a (GA) as an example: - VERSION_NUMBER = 0x3437302a which.." hexmask.long 0x0 0.--31. 1. "VERSION_NUMBER,Version Number." line.long 0x4 "PCIE_VERSION_TYPE_OFF,PCIe Controller IIP Release Version Type. The type is given in hex format. You should convert each pair of hex characters to ASCII to interpret. Using 4.70a (GA) as an example: - VERSION_NUMBER = 0x3437302a which translates to 470*.." hexmask.long 0x4 0.--31. 1. "VERSION_TYPE,Version Type." group.long (0x430+0x700)++0x3 line.long 0x0 "PL_LTR_LATENCY_OFF,LTR Latency Register. The function of this register field (and all other fields in this register) differs between an upstream port and a downstream port. For an upstream port. the register fields capture the corresponding fields in the.." bitfld.long 0x0 31. "NO_SNOOP_LATENCY_REQUIRE,No Snoop Latency Requirement. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" "0,1" newline rbitfld.long 0x0 29.--30. "RSVDP_29,Reserved for future use." "0,1,2,3" newline bitfld.long 0x0 26.--28. "NO_SNOOP_LATENCY_SCALE,No Snoop Latency Scale. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" "0,1,2,3,4,5,6,7" newline hexmask.long.word 0x0 16.--25. 1. "NO_SNOOP_LATENCY_VALUE,No Snoop Latency Value. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" newline bitfld.long 0x0 15. "SNOOP_LATENCY_REQUIRE,Snoop Latency Requirement. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" "0,1" newline rbitfld.long 0x0 13.--14. "RSVDP_13,Reserved for future use." "0,1,2,3" newline bitfld.long 0x0 10.--12. "SNOOP_LATENCY_SCALE,Snoop Latency Scale. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" "0,1,2,3,4,5,6,7" newline hexmask.long.word 0x0 0.--9. 1. "SNOOP_LATENCY_VALUE,Snoop Latency Value. Note: The access attributes of this field are as follows: - Wire: No access. - Dbi: R/W" group.long (0x440+0x700)++0xB line.long 0x0 "AUX_CLK_FREQ_OFF,Auxiliary Clock Frequency Control Register." hexmask.long.tbyte 0x0 10.--31. 1. "RSVDP_10,Reserved for future use." newline hexmask.long.word 0x0 0.--9. 1. "AUX_CLK_FREQ,The aux_clk frequency in MHz. This value is used to provide a 1 us reference for counting time during low-power states with aux_clk when the PHY has removed the pipe_clk. Frequencies lower than 1 MHz are possible but with a loss of accuracy.." line.long 0x4 "L1_SUBSTATES_OFF,L1 Substates Timing Register." hexmask.long.tbyte 0x4 9.--31. 1. "RSVDP_9,Reserved for future use." newline bitfld.long 0x4 8. "L1SUB_LOW_POWER_CLOCK_SWITCH_MODE,If this bit is set to 1'b1 the reference clock will be running regardless of the CLKREQ# setting. If this bit is set to 1'b0 the reference clock may be gated off when CLKREQ# is de-asserted. If the bit is set to 1'b1 the.." "0,1" newline bitfld.long 0x4 6.--7. "L1SUB_T_PCLKACK,Max delay (in 1us units) between a MAC request to remove the clock on mac_phy_pclkreq_n and a PHY response on phy_mac_pclkack_n. If the PHY does not respond within this time the request is aborted.The actual timeout value will be.." "0,1,2,3" newline hexmask.long.byte 0x4 2.--5. 1. "L1SUB_T_L1_2,Duration (in 1us units) of L1.2. The actual timeout value will be L1SUB_T_L1_2 + 1. Range is 0.15. Note: This register field is sticky." newline bitfld.long 0x4 0.--1. "L1SUB_T_POWER_OFF,Duration (in 1us units) of L1.2.Entry. The actual timeout value will be L1SUB_T_POWER_OFF + 1. Range is 0.3. Note: This register field is sticky." "0,1,2,3" line.long 0x8 "POWERDOWN_CTRL_STATUS_OFF,Powerdown Control and Status Register." hexmask.long.tbyte 0x8 12.--31. 1. "RSVDP_12,Reserved for future use." newline hexmask.long.byte 0x8 8.--11. 1. "POWERDOWN_PHY_POWERDOWN,This field represents the Powerdown value that has been acknowledged by the PHY. It is updated with the value of Powerdown driven by the controller when the PHY has returned the Phystatus acknowledgment for the Powerdown.." newline hexmask.long.byte 0x8 4.--7. 1. "POWERDOWN_MAC_POWERDOWN,This field represents the Powerdown value driven by the controller to the PHY." newline rbitfld.long 0x8 1.--3. "RSVDP_1,Reserved for future use." "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 0. "POWERDOWN_FORCE,This field is a one shot field. Writing a value of 1 to this field causes the controller to complete the P2 Powerdown handshake regardless of whether the PHY has returned Phystatus. This field could be used for debug purposes in event.." "0,1" group.long (0x470+0x700)++0x7 line.long 0x0 "PHY_VIEWPORT_CTLSTS_OFF,PHY Register Viewport Control and Status Register." rbitfld.long 0x0 31. "PHY_VIEWPORT_PENDING,PHY viewport pending. Indicates the access is pending. - 1 : Pending - 0 : Idle This bit is set to 1 when the read/write access has been initiated. This bit is cleared when the access is completed. If phy_reg_clk_g is never activated.." "Idle,Pending" newline rbitfld.long 0x0 30. "PHY_VIEWPORT_STATUS,PHY viewport status. Indicates the status of the latest access. - 1 : Timeout - 0 : No errors If the timeout is detected this bit is set to 1 and PHY_VIEWPORT_PENDING is cleared. This bit is cleared when the read/write access is.." "No errors,Timeout" newline hexmask.long.byte 0x0 23.--29. 1. "RSVDP_23,Reserved for future use." newline bitfld.long 0x0 22. "PHY_VIEWPORT_TIMEOUT_DISABLE,PHY viewport timeout disable. Disables the PHY register access timeout structure. When the timeout is disabled you must ensure that the PHY register accesses are always acknowledged by cr_para_ack. Otherwise.." "0,1" newline bitfld.long 0x0 21. "PHY_VIEWPORT_BCWR,Broadcast write access to all xN sub-blocks. If you need to broadcast the write accesses into all lanes both PHY_VIEWPORT_ADDR[15] and this bit should be 1. Note: This register field is sticky." "0,1" newline bitfld.long 0x0 20. "PHY_VIEWPORT_READ,PHY viewport read. If set a read access is initiated. The value is always 0 when this bit is read. Note: This register field is sticky." "0,1" newline hexmask.long.byte 0x0 16.--19. 1. "PHY_VIEWPORT_NUM,PHY viewport xN sub-block number. Selects one of xN sub-blocks. This register is not used when the write access is initiated with PHY_VIEWPORT_BCWR==1. Note: This register field is sticky." newline hexmask.long.word 0x0 0.--15. 1. "PHY_VIEWPORT_ADDR,PHY viewport address. Indicates the PHY's register address. Please refer to the PHY databook for the address map definition. Note: This register field is sticky." line.long 0x4 "PHY_VIEWPORT_DATA_OFF,PHY Register Viewport Data Register." hexmask.long.word 0x4 16.--31. 1. "RSVDP_16,Reserved for future use." newline hexmask.long.word 0x4 0.--15. 1. "PHY_VIEWPORT_DATA,PHY viewport data. A write access to this register initiates the PHY register write access. By a read access to this register this field returns the latest read data from the PHY register. Note: This register field is sticky." group.long (0x490+0x700)++0x3 line.long 0x0 "PIPE_RELATED_OFF,PIPE Related Register. This register controls the pipe's capabitity. control. and status parameters." hexmask.long.tbyte 0x0 9.--31. 1. "RSVDP_9,Reserved for future use." newline bitfld.long 0x0 8. "PIPE_GARBAGE_DATA_MODE,PIPE Garbage Data Mode. - 0: PIPE Spec compliant mode: The MAC discards any symbols received after the electrical idle ordered-set until RxValid is deasserted. - 1: Special PHY Support mode: The MAC discards any symbols received.." "PIPE Spec compliant mode: The MAC discards any..,Special PHY Support mode: The MAC discards any.." tree.end tree.end tree "PCIE2_NCR" base ad:0x311E0000 group.long 0x0++0x7 line.long 0x0 "INTR_0,INTR_0" bitfld.long 0x0 31. "INTR_PM_XTLH_BLOCK_TLP,Indicates that your application must stop generating new outgoing request TLPs due to the current power management state. Your application can continue to generate completion TLPs." "0,1" newline bitfld.long 0x0 30. "INTR_LINK_REQ_RST_NOT,Reset request because the link has gone down or the controller received a hot-reset request. A low level indicates that the controller is requesting external logic to reset the controller because the PHY link is down. When the AXI.." "0,1" newline bitfld.long 0x0 29. "INTR_SMLH_REQ_RST_NOT,Early version of the link_req_rst_not signal." "0,1" newline bitfld.long 0x0 28. "INTR_SMLH_LINK_UP,PHY Link up/down indicator: 1: Link is up 0: Link is down" "Link is down,Link is up" newline bitfld.long 0x0 27. "INTR_RDLH_LINK_UP,Data link layer up/down indicator: This status from the flow control initialization state machine indicates that flow control has been initiated and the Data link layer is ready to transmit and receive packets. For multi-VC designs.." "Link is down,Link is up" newline bitfld.long 0x0 26. "INTR_VEN_MSI_GRANT,One-cycle pulse that indicates that the controller has accepted the request to send an MSI. After asserting ven_msi_grant for one cycle the controller does not wait for ven_msi_req to be de-asserted then reasserted to generate another.." "0,1" newline bitfld.long 0x0 25. "INTR_VEN_MSG_GRANT,One-cycle pulse that indicates that the controller has accepted the request to send the vendor-defined Message." "0,1" newline bitfld.long 0x0 23.--24. "INTR_CFG_UP_DRS_TO_FRS,DRS to FRS Pulse. The DSP controller asserts the cfg_up_drs_to_frs output and sends an FRS message with the reason code set to 'DRS Message Received' when: It receives a DRS message and PCIE_CAP_DRS_SIGNALING_CONTROL in.." "0,1,2,3" newline bitfld.long 0x0 21.--22. "INTR_CFG_DRS_MSI,DRS Message Received Interrupt Pulse. The DSP controller asserts the cfg_drs_msi output when all of the following are true: It receives a DRS message PCIE_CAP_DRS_SIGNALING_CONTROL in LINK_CONTROL_LINK_STATUS_REG is 2'b01 MSI or MSI-X is.." "0,1,2,3" newline bitfld.long 0x0 19.--20. "INTR_FRSQ_MSI,FRSQ Interrupt Pulse. The RC asserts this output when it receives an FRQ message or when the FRS queue overflows." "0,1,2,3" newline bitfld.long 0x0 17.--18. "INTR_CFG_PME_MSI,The controller asserts cfg_pme_msi (as a one-cycle pulse) when all of the following conditions are true: MSI or MSI-X is enabled. The PME Interrupt Enable bit in the Root Control register is set to 1. The PME Status bit in the Root.." "0,1,2,3" newline bitfld.long 0x0 15.--16. "INTR_HP_MSI,INTR_HP_MSI" "0,1,2,3" newline bitfld.long 0x0 14. "INTR_CFG_LINK_AUTO_BW_MSI,The controller sets this pin when following conditions are true: MSI or MSI-X is enabled. The Link Autonomous Bandwidth Status register (Link Status register bit 15) is updated. The Link Autonomous Bandwidth Interrupt Enable.." "0,1" newline bitfld.long 0x0 13. "INTR_CFG_BW_MGT_MSI,The controller sets this pin when following conditions are true: MSI or MSI-X is enabled. The Link Bandwidth Management Status register (Link Control Status register bit 14) is updated The Link Bandwidth Management Interrupt Enable.." "0,1" newline bitfld.long 0x0 11.--12. "INTR_HP_PME,The controller asserts hp_pme when all of the following conditions are true: The PME Enable bit in the Power Management Control and Status" "0,1,2,3" newline bitfld.long 0x0 10. "INTR_PTM_CLOCK_UPDATED,Indicates that the controller has updated the Local Clock." "0,1" newline bitfld.long 0x0 9. "INTR_PTM_REQ_DUP_RX,PTM Requester Duplicate Received. Single-cycle pulse indicating PTM Requester received a duplicate TLP while PTM Requester is in the process of updating PTM local clock or Following calculation of the update when the PTM context is.." "0,1" newline bitfld.long 0x0 8. "INTR_PTM_REQ_REPLAY_TX,PTM Requester Replay Sent. Single-cycle pulse indicating PTM Requester detected a TLP replay being sent when ResponseD messages are in use while PTM Requester is in the process of updating PTM local clock or Following calculation.." "0,1" newline bitfld.long 0x0 7. "INTR_RADM_MSG_LTR,One-clock-cycle pulse that indicates that the controller received an LTR message. The controller makes the message header available the radm_msg_payload output. It is also available the app_ltr_latency output. When RX_TLP > 1 and when.." "0,1" newline bitfld.long 0x0 6. "INTR_RADM_MSG_UNLOCK,One-cycle pulse that indicates that the controller received an Unlock message. When RX_TLP > 1 and when two messages of the same type are received in the same clock cycle (back-to-back) then no separate indication is given for the.." "0,1" newline bitfld.long 0x0 5. "INTR_RADM_PM_PME,One-clock-cycle pulse that indicates that the controller received a PM_PME message." "0,1" newline bitfld.long 0x0 4. "INTR_RADM_PM_TO_ACK,One-clock-cycle pulse that indicates that the controller received a PME_TO_Ack message. Upstream port: Reserved." "0,1" newline bitfld.long 0x0 3. "INTR_RADM_PM_TURNOFF,One-clock-cycle pulse that indicates that the controller received a PME Turnoff message. When RX_TLP > 1 and when two messages of the same type are received in the same clock cycle (back-to-back) then no indication is given for the.." "0,1" newline bitfld.long 0x0 2. "INTR_RADM_VENDOR_MSG,One-cycle pulse that indicates the controller received a vendor-defined message. The controller makes the message header available the radm_msg_payload output. When FX_TLP > 1 and when two messages of the same type are received in.." "0,1" newline bitfld.long 0x0 1. "INTR_PERSTN,INTR_PERSTN This interrupt status bit indicates PERST# pad input fall edge detected." "0,1" newline bitfld.long 0x0 0. "INTR_WAKEN,INTR_WAKEN This interrupt status bit indicates WAKE# pad input fall edge detected." "0,1" line.long 0x4 "INTR_1,INTR_1" bitfld.long 0x4 31. "INTR_TRGT_CPL_TIMEOUT,Indicates that the application has not generated a completion for an incoming request within the required time interval. Information about the timed out completion is available the trgt_timeout_* outputs listed later.When a.." "0,1" newline bitfld.long 0x4 30. "INTR_RADM_CPL_TIMEOUT,Indicates that the completion TLP for a request has not been received within the expected time window." "0,1" newline hexmask.long.byte 0x4 26.--29. 1. "INTR_INT_D_A,INTR_INT_D_A These Interrupt status bit indicates wheter Legacy A~D transmitted or received by controller. bit 29 : INT_D .. bit26 : INT_A" newline bitfld.long 0x4 24.--25. "INTR_CFG_SEND_F_ERR,Sent Fatal Error. Controller has sent a message towards the Root Complex indicating that an Rx TLP that contained a fatal error and that can not be corrected was received by the EndPoint" "0,1,2,3" newline bitfld.long 0x4 22.--23. "INTR_CFG_SEND_NF_ERR,Sent Non-Fatal Error. Controller has sent a message towards the Root Complex indicating that an Rx TLP that contained an non-fatal error and that can not be corrected was received by the EndPoint" "0,1,2,3" newline bitfld.long 0x4 20.--21. "INTR_CFG_SEND_COR_ERR,Sent Correctable Error. Core has sent a message towards the Root Complex indicating that an Rx TLP that contained an error and that can be corrected was received by the EndPoint" "0,1,2,3" newline bitfld.long 0x4 18.--19. "INTR_CFG_FLR_PF_ACTIVE,Set when the software initiates FLR a physical function by writing to the 'Initiate FLR' register bit of that function. This signal is held asserted until reset of both the application and controller logic has been completed." "0,1,2,3" newline bitfld.long 0x4 16.--17. "INTR_PF_FRS_GRANT,Indicator of when an FRS message for this function has been scheduled for transmission." "0,1,2,3" newline hexmask.long.byte 0x4 8.--15. 1. "INTR_CFG_FLR_VF_ACTIVE,Set when the software initiates FLR a virtual function by writing to the 'Initiate FLR' register bit of that function. This signal is held asserted until the reset of both the application and internal controller logic has been.." newline hexmask.long.byte 0x4 0.--7. 1. "INTR_VF_FRS_GRANT,Indicator of when an FRS message for this VF has been scheduled for transmission." repeat 10. (list 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB )(list 0x0 0x4 0x8 0xC 0x10 0x14 0x18 0x1C 0x20 0x24 ) group.long ($2+0x8)++0x3 line.long 0x0 "INTR_$1,INTR_2" hexmask.long 0x0 0.--31. 1. "INTR_MSI_PF0,INTR_MSI_PF0" repeat.end group.long 0x30++0xB line.long 0x0 "INTR_12,INTR_12" newline hexmask.long.byte 0x0 16.--23. 1. "INTR_RADM_TRGT1_ATU_CBUF_ERR,INTR_RADM_TRGT1_ATU_CBUF_ERR" newline hexmask.long.byte 0x0 8.--15. 1. "INTR_RADM_TRGT1_ATU_SLOC_MATCH,INTR_RADM_TRGT1_ATU_SLOC_MATCH" newline bitfld.long 0x0 7. "INTR_RADM_CORRECTABLE_ERR,INTR_RADM_CORRECTABLE_ERR" "0,1" newline bitfld.long 0x0 6. "INTR_RADM_NONFATAL_ERR,INTR_RADM_NONFATAL_ERR" "0,1" newline bitfld.long 0x0 5. "INTR_RADM_FATAL_ERR,INTR_RADM_FATAL_ERR" "0,1" newline bitfld.long 0x0 3.--4. "INTR_CFG_AER_RC_ERR_MSI,INTR_CFG_AER_RC_ERR_MSI" "0,1,2,3" newline bitfld.long 0x0 1.--2. "INTR_CFG_SYS_ERR_RC,INTR_CFG_SYS_ERR_RC" "0,1,2,3" newline bitfld.long 0x0 0. "INTR_MSTR_AWMISC_INFO_EP,INTR_MSTR_AWMISC_INFO_EP" "0,1" line.long 0x4 "INTEN_0,INTEN_0" bitfld.long 0x4 31. "INTEN_PM_XTLH_BLOCK_TLP,Indicates that your application must stop generating new outgoing request TLPs due to the current power management state. Your application can continue to generate completion TLPs.This output is not used in RC mode." "0,1" newline bitfld.long 0x4 30. "INTEN_LINK_REQ_RST_NOT,Reset request because the link has gone down or the controller received a hot-reset request. A low level indicates that the controller is requesting external logic to reset the controller because the PHY link is down. When the AXI.." "0,1" newline bitfld.long 0x4 29. "INTEN_SMLH_REQ_RST_NOT,Early version of the link_req_rst_not signal." "0,1" newline bitfld.long 0x4 28. "INTEN_SMLH_LINK_UP,PHY Link up/down indicator: 1: Link is up 0: Link is down" "Link is down,Link is up" newline bitfld.long 0x4 27. "INTEN_RDLH_LINK_UP,Data link layer up/down indicator: This status from the flow control initialization state machine indicates that flow control has been initiated and the Data link layer is ready to transmit and receive packets. For multi-VC designs.." "Link is down,Link is up" newline bitfld.long 0x4 26. "INTEN_VEN_MSI_GRANT,One-cycle pulse that indicates that the controller has accepted the request to send an MSI. After asserting ven_msi_grant for one cycle the controller does not wait for ven_msi_req to be de-asserted then reasserted to generate another.." "0,1" newline bitfld.long 0x4 25. "INTEN_VEN_MSG_GRANT,One-cycle pulse that indicates that the controller has accepted the request to send the vendor-defined Message." "0,1" newline bitfld.long 0x4 23.--24. "INTEN_CFG_UP_DRS_TO_FRS,DRS to FRS Pulse. The DSP controller asserts the cfg_up_drs_to_frs output and sends an FRS message with the reason code set to 'DRS Message Received' when: It receives a DRS message and PCIE_CAP_DRS_SIGNALING_CONTROL in.." "0,1,2,3" newline bitfld.long 0x4 21.--22. "INTEN_CFG_DRS_MSI,DRS Message Received Interrupt Pulse. The DSP controller asserts the cfg_drs_msi output when all of the following are true: It receives a DRS message PCIE_CAP_DRS_SIGNALING_CONTROL in LINK_CONTROL_LINK_STATUS_REG is 2'b01 MSI or MSI-X.." "0,1,2,3" newline bitfld.long 0x4 19.--20. "INTEN_FRSQ_MSI,FRSQ Interrupt Pulse. The RC asserts this output when it receives an FRQ message or when the FRS queue overflows." "0,1,2,3" newline bitfld.long 0x4 17.--18. "INTEN_CFG_PME_MSI,The controller asserts cfg_pme_msi (as a one-cycle pulse) when all of the following conditions are true: MSI or MSI-X is enabled. The PME Interrupt Enable bit in the Root Control register is set to 1. The PME Status bit in the Root.." "0,1,2,3" newline bitfld.long 0x4 15.--16. "INTEN_HP_MSI,The controller asserts hp_msi (as a one-cycle pulse) when the logical AND of the following conditions transitions from false to true: MSI or MSI-X is enabled. Hot-Plug interrupts are enabled in the Slot Control register. Any bit in the Slot.." "0,1,2,3" newline bitfld.long 0x4 14. "INTEN_CFG_LINK_AUTO_BW_MSI,The controller sets this pin when following conditions are true: MSI or MSI-X is enabled. The Link Autonomous Bandwidth Status register (Link Status register bit 15) is updated. The Link Autonomous Bandwidth Interrupt Enable.." "0,1" newline bitfld.long 0x4 13. "INTEN_CFG_BW_MGT_MSI,The controller sets this pin when following conditions are true: MSI or MSI-X is enabled. The Link Bandwidth Management Status register (Link Control Status register bit 14) is updated The Link Bandwidth Management Interrupt Enable.." "0,1" newline bitfld.long 0x4 11.--12. "INTEN_HP_PME,The controller asserts hp_pme when all of the following conditions are true: The PME Enable bit in the Power Management Control and Status register is set to 1. Any bit in the Slot Status register transitions from 0 to 1 and the associated.." "0,1,2,3" newline bitfld.long 0x4 10. "INTEN_PTM_CLOCK_UPDATED,Indicates that the controller has updated the Local Clock." "0,1" newline bitfld.long 0x4 9. "INTEN_PTM_REQ_DUP_RX,PTM Requester Duplicate Received. Single-cycle pulse indicating PTM Requester received a duplicate TLP while PTM Requester is in the process of updating PTM local clock or Following calculation of the update when the PTM context.." "0,1" newline bitfld.long 0x4 8. "INTEN_PTM_REQ_REPLAY_TX,PTM Requester Replay Sent. Single-cycle pulse indicating PTM Requester detected a TLP replay being sent when ResponseD messages are in use while PTM Requester is in the process of updating PTM local clock or Following.." "0,1" newline bitfld.long 0x4 7. "INTEN_RADM_MSG_LTR,One-clock-cycle pulse that indicates that the controller received an LTR message. The controller makes the message header available the radm_msg_payload output. It is also available the app_ltr_latency output. When RX_TLP > 1 and when.." "0,1" newline bitfld.long 0x4 6. "INTEN_RADM_MSG_UNLOCK,One-cycle pulse that indicates that the controller received an Unlock message. When RX_TLP > 1 and when two messages of the same type are received in the same clock cycle (back-to-back) then no separate indication is given for the.." "0,1" newline bitfld.long 0x4 5. "INTEN_RADM_PM_PME,One-clock-cycle pulse that indicates that the controller received a PM_PME message." "0,1" newline bitfld.long 0x4 4. "INTEN_RADM_PM_TO_ACK,One-clock-cycle pulse that indicates that the controller received a PME_TO_Ack message. Upstream port: Reserved." "0,1" newline bitfld.long 0x4 3. "INTEN_RADM_PM_TURNOFF,One-clock-cycle pulse that indicates that the controller received a PME Turnoff message. When RX_TLP > 1 and when two messages of the same type are received in the same clock cycle (back-to-back) then no indication is given for the.." "0,1" newline bitfld.long 0x4 2. "INTEN_RADM_VENDOR_MSG,One-cycle pulse that indicates the controller received a vendor-defined message. The controller makes the message header available the radm_msg_payload output. When FX_TLP > 1 and when two messages of the same type are received in.." "0,1" newline bitfld.long 0x4 1. "INTEN_PERSTN,INTEN_PERSTN Interrupt Enable bit for INTR_PERSTN." "0,1" newline bitfld.long 0x4 0. "INTEN_WAKEN,INTEN_WAKEN Interrupt Enable bit for INTR_WAKEN." "0,1" line.long 0x8 "INTEN_1,INTEN_1" bitfld.long 0x8 31. "INTEN_TRGT_CPL_TIMEOUT,Indicates that the application has not generated a completion for an incoming request within the required time interval. Information about the timed out completion is available the trgt_timeout_* outputs listed later.When a.." "0,1" newline bitfld.long 0x8 30. "INTEN_RADM_CPL_TIMEOUT,Indicates that the completion TLP for a request has not been received within the expected time window." "0,1" newline hexmask.long.byte 0x8 26.--29. 1. "INTEN_INT_D_A,INTEN_INT_D_A Interrupt Enable bit for INTR_D_A. Bit 29 : INT_D ... Bit26 : INT_A." newline bitfld.long 0x8 24.--25. "INTEN_CFG_SEND_F_ERR,Sent Fatal Error. Controller has sent a message towards the Root Complex indicating that an Rx TLP that contained a fatal error and that can not be corrected was received by the EndPoint" "0,1,2,3" newline bitfld.long 0x8 22.--23. "INTEN_CFG_SEND_NF_ERR,Sent Non-Fatal Error. Controller has sent a message towards the Root Complex indicating that an Rx TLP that contained an non-fatal error and that can not be corrected was received by the EndPoint" "0,1,2,3" newline bitfld.long 0x8 20.--21. "INTEN_CFG_SEND_COR_ERR,Sent Correctable Error. Core has sent a message towards the Root Complex indicating that an Rx TLP that contained an error and that can be corrected was received by the EndPoint" "0,1,2,3" newline bitfld.long 0x8 18.--19. "INTEN_CFG_FLR_PF_ACTIVE,Set when the software initiates FLR a physical function by writing to the 'Initiate FLR' register bit of that function. This signal is held asserted until reset of both the application and controller logic has been completed." "0,1,2,3" newline bitfld.long 0x8 16.--17. "INTEN_PF_FRS_GRANT,Indicator of when an FRS message for this function has been scheduled for transmission." "0,1,2,3" newline hexmask.long.byte 0x8 8.--15. 1. "INTEN_CFG_FLR_VF_ACTIVE,Set when the software initiates FLR a virtual function by writing to the 'Initiate FLR' register bit of that function. This signal is held asserted until the reset of both the application and internal controller logic has been.." newline hexmask.long.byte 0x8 0.--7. 1. "INTEN_VF_FRS_GRANT,Indicator of when an FRS message for this VF has been scheduled for transmission." repeat 10. (list 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB )(list 0x0 0x4 0x8 0xC 0x10 0x14 0x18 0x1C 0x20 0x24 ) group.long ($2+0x3C)++0x3 line.long 0x0 "INTEN_$1,INTEN_2" hexmask.long 0x0 0.--31. 1. "INTEN_MSI_PF0,INTEN_MSI_PF0" repeat.end group.long 0x64++0x13 line.long 0x0 "INTEN_12,INTEN_12" newline hexmask.long.byte 0x0 16.--23. 1. "INTEN_RADM_TRGT1_ATU_CBUF_ERR,INTEN_RADM_TRGT1_ATU_CBUF_ERR" newline hexmask.long.byte 0x0 8.--15. 1. "INTEN_RADM_TRGT1_ATU_SLOC_MATCH,INTEN_RADM_TRGT1_ATU_SLOC_MATCH" newline bitfld.long 0x0 7. "INTEN_RADM_CORRECTABLE_ERR,INTEN_RADM_CORRECTABLE_ERR" "0,1" newline bitfld.long 0x0 6. "INTEN_RADM_NONFATAL_ERR,INTEN_RADM_NONFATAL_ERR" "0,1" newline bitfld.long 0x0 5. "INTEN_RADM_FATAL_ERR,INTEN_RADM_FATAL_ERR" "0,1" newline bitfld.long 0x0 3.--4. "INTEN_CFG_AER_RC_ERR_MSI,INTEN_CFG_AER_RC_ERR_MSI" "0,1,2,3" newline bitfld.long 0x0 1.--2. "INTEN_CFG_SYS_ERR_RC,INTEN_CFG_SYS_ERR_RC" "0,1,2,3" newline bitfld.long 0x0 0. "INTEN_MSTR_AWMISC_INFO_EP,INTEN_MSTR_AWMISC_INFO_EP" "0,1" line.long 0x4 "CTRL_0,CTRL_0" bitfld.long 0x4 31. "APP_FLR_VF_DONE_7,Indicates that FLR a virtual function has been completed which means the application has completed initializing its data structures for the function and there are no more TLPs associated with this function in the application's transmit.." "0,1" newline bitfld.long 0x4 30. "APP_FLR_VF_DONE_6,Similar to above." "0,1" newline bitfld.long 0x4 29. "APP_FLR_VF_DONE_5,Similar to above." "0,1" newline bitfld.long 0x4 28. "APP_FLR_VF_DONE_4,Similar to above." "0,1" newline bitfld.long 0x4 27. "APP_FLR_VF_DONE_3,Similar to above." "0,1" newline bitfld.long 0x4 26. "APP_FLR_VF_DONE_2,Similar to above." "0,1" newline bitfld.long 0x4 25. "APP_FLR_VF_DONE_1,Similar to above." "0,1" newline bitfld.long 0x4 24. "APP_FLR_VF_DONE_0,Similar to above." "0,1" newline bitfld.long 0x4 23. "APP_FLR_PF_DONE_1,Indicates that FLR a physical function has been completed which means the application has completed initializing its data structures for the function and there are no more TLPs associated with this function in the application's.." "0,1" newline bitfld.long 0x4 22. "APP_FLR_PF_DONE_0,Similar to above." "0,1" newline bitfld.long 0x4 21. "OUTBAND_PWRUP_CMD_1,Wake Up. If PME is enabled and PME support is configured for current PMCSR D-state asserting this signal causes the controller to wake from either L1 or L2 state. When the controller has transitioned back to the L0 state it transmits.." "0,1" newline bitfld.long 0x4 20. "OUTBAND_PWRUP_CMD_0,Similar to above." "0,1" newline bitfld.long 0x4 19. "APP_REQ_EXIT_L1,Application request to Exit L1. Request from your application to exit L1.It is only effective when L1 is enabled." "0,1" newline bitfld.long 0x4 18. "APP_REQ_ENTR_L1,Application request to Enter L1 ASPM state. The app_req_entr_l1 signal is for use by applications that need to control L1 entry instead of using the L1 entry timer as defined in the PCI Express Specification. It is only effective when L1.." "0,1" newline bitfld.long 0x4 17. "APP_UNLOCK_MSG,Request from your application to generate an Unlock message. You must assert this signal for one clock cycle. The controller does not return an acknowledgment or grant signal. You must not pulse the same signal again until the previous.." "0,1" newline bitfld.long 0x4 16. "APP_PM_XMT_PME_1,Wake Up. If PME is enabled and PME support is configured for current PMCSR D-state asserting this signal causes the controller to wake from either L1 or L2 state. When the controller has transitioned back to the L0 state it transmits a.." "0,1" newline bitfld.long 0x4 15. "APP_PM_XMT_PME_0,Similar to above." "0,1" newline bitfld.long 0x4 14. "APP_PM_XMT_TURNOFF,Request from your application to generate a PM_Turn_Off message.You must assert this signal for one clock cycle. The controller does not return an acknowledgment or grant signal. You must not pulse the same signal again until the.." "0,1" newline bitfld.long 0x4 13. "APP_INIT_RST,Request from your application to send a hot reset to the upstream port.The hot reset request is sent when a single cycle pulse is applied to this pin. In an upstream port you should set this input to '0'." "0,1" newline bitfld.long 0x4 12. "APP_HDR_VALID,One-clock-cycle pulse indicating that the data app_hdr_log app_err_bus app_err_func_num and app_tlp_prfx_log is valid." "0,1" newline bitfld.long 0x4 11. "APP_L1SUB_DISABLE,The application can set this input to 1'b1 to prevent entry to L1 Sub-states. This pin is used to gate the L1 sub-state enable bits from the L1 PM Substates Control 1 Register." "0,1" newline bitfld.long 0x4 10. "APP_CLK_PM_EN,Clock PM feature enabled by application. Used to inhibit the programming of the Clock PM in Link Control Register. For more details see 'L1 with Clock PM (L1 with REFCLK removal/PLL Off)'." "0,1" newline bitfld.long 0x4 9. "APP_XFER_PENDING,Indicates that your application has transfers pending and prevents the controller from entering L1. If the entry into L1 is already in progress assertion of app_xfer_pending causes an exit from L1. This is a level signal used to inform.." "0,1" newline bitfld.long 0x4 8. "APP_READY_ENTR_L23,Application Ready to Enter L23. Indication from your application that it is ready to enter the L23 state. The app_ready_entr_l23 signal is provided for applications that must control L23 entry (in case certain tasks must be performed.." "0,1" newline bitfld.long 0x4 7. "APP_CLK_REQ_N,Indicates that the application logic is ready to have reference clock removed. In designs which support reference clock removal through either L1 PM Sub-states or L1 CPM the application should set this signal to 1'b when it is ready to.." "0,1" newline bitfld.long 0x4 6. "APP_HOLD_PHY_RST,Set this signal to one before the de-assertion of power on reset to hold the PHY in reset. This can be used to configure your PHY. Synopsys PHYs can be configured through the PHY Viewport if desired. Please tie this port to zero if your.." "0,1" newline bitfld.long 0x4 5. "APP_SRIS_MODE,SRIS operating mode: 0b: non-SRIS mode 1b: SRIS mode" "0,1" newline bitfld.long 0x4 4. "APP_DBI_RO_WR_DISABLE,DBI Read-only Write Disable 0: MISC_CONTROL_1_OFF.DBI_RO_WR_EN register field is read-write. 1: MISC_CONTROL_1_OFF.DBI_RO_WR_EN register field is forced to 0 and is read-only." "MISC_CONTROL_1_OFF,MISC_CONTROL_1_OFF" newline bitfld.long 0x4 3. "DEVICE_TYPE,Device/port type. Indicates the specific type of this PCI Express function. It is also used to set the 'Device/Port Type' field of the 'PCI Express Capabilities Register'. The controller uses this input to determine the operating mode of the.." "PCI Express endpoint,Legacy PCI Express endpoint" newline bitfld.long 0x4 2. "APP_LTSSM_ENABLE,To do otherwise (that is de-assert it outside of the Detect LTSSM state) causes the controller to be reset and the LTSSM moves immediately back to the Detect state. This transition is outside of the PCIe Specification and it might cause.." "0,1" newline bitfld.long 0x4 0. "APP_ERR_VFUNC_ACTIVE,Indicates the function number in app_err_vfunc_num is valid." "0,1" line.long 0x8 "CTRL_1,CTRL_1" bitfld.long 0x8 29.--31. "APP_ERR_VFUNC_NUM,The number of the virtual function that is reporting the error indicated app_err_bus valid when app_hdr_valid is asserted. Uncorrected Internal errors (app_err_bus[9]) are not recorded for virtual functions.The PCIe SR-IOV.." "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 28. "SLV_ARMISC_INFO_ATU_BYPASS,AXI Slave Read Request Internal ATU Bypass. When set it indicates that this request should not be processed by the internal address translation unit" "0,1" newline hexmask.long.word 0x8 15.--27. 1. "APP_ERR_BUS,The type of error that your application detected. The controller combines the values the app_err_bus bits with the internally-detected error signals to set the corresponding bit in the Uncorrectable or Correctable Error Status Registers:.." newline bitfld.long 0x8 14. "APP_REQ_RETRY_EN,Provides a capability to defer incoming configuration requests until initialization is complete. When app_req_retry_en is asserted the controller completes incoming configuration requests with a configuration request retry status. Other.." "0,1" newline hexmask.long.byte 0x8 6.--13. 1. "APP_VF_REQ_RETRY_EN,Provides a per Virtual Function (VF) capability to defer incoming configuration requests until initialization is complete. When app_vf_req_retry_en is asserted for a certain VF the controller completes incoming configuration requests.." newline bitfld.long 0x8 4.--5. "APP_PF_REQ_RETRY_EN,Provides a per Physical Function (PF) capability to defer incoming configuration requests until initialization is complete. When app_pf_req_retry_en is asserted for a certain PF the controller completes incoming configuration.." "0,1,2,3" newline bitfld.long 0x8 2.--3. "APP_RAS_DES_TBA_CTRL,Controls the start/end of time based analysis. You must only set the pins to the required value for the duration of one clock cycle. This signal must be 2'b00 while the TIMER_START field in TIME_BASED_ANALYSIS_CONTROL_REG register is.." "No action,Start,End,Reserved" newline bitfld.long 0x8 1. "APP_RAS_DES_SD_HOLD_LTSSM,Hold and release LTSSM. For as long as this signal is '1' thecontroller stays in the current LTSSM." "0,1" newline bitfld.long 0x8 0. "SYS_AUX_PWR_DET,Auxiliary Power Detected. Used to report to the host software that auxiliary power (Vaux) is present." "0,1" line.long 0xC "CTRL_2,CTRL_2" bitfld.long 0xC 30.--31. "SYS_PWR_FAULT_DET,Power Fault Detected. Indicates the power controller detected a power fault at this slot. There is a separate sys_pwr_fault_det input bit for each function in your controller configuration." "0,1,2,3" newline bitfld.long 0xC 28.--29. "SYS_MRL_SENSOR_STATE,MRL Sensor State. Indicates the state of the manually-operated retention latch (MRL) sensor: 0: MRL is closed 1: MRL is open There is a separate sys_mrl_sensor_state input bit for each function in your controller configuration." "MRL is closed,MRL is open,?,?" newline bitfld.long 0xC 26.--27. "SYS_PRE_DET_STATE,Presence Detect State. Indicates whether or not a card is present in the slot: 0: Slot is empty 1: Card is present in the slot" "Slot is empty,Card is present in the slot,?,?" newline bitfld.long 0xC 24.--25. "SYS_ATTEN_BUTTON_PRESSED,Attention Button Pressed. Indicates that the system attention button was pressed sets the Attention Button Pressed bit in the Slot Status Register." "0,1,2,3" newline bitfld.long 0xC 23. "TX_LANE_FLIP_EN,Performs manual lane reversal for transmit lanes. For use when automatic lane reversal does not occur because lane 0 is not detected.In most cases tx_lane_flip_en should be wired to a static value at the chip level." "0,1" newline bitfld.long 0xC 22. "RX_LANE_FLIP_EN,Performs manual lane reversal for receive lanes. For use when automatic lane reversal does not occur because lane 0 is not detected.In most cases rx_lane_flip_en should be wired to a static value at the chip level." "0,1" newline bitfld.long 0xC 21. "DBG_PBA,MSIX PBA RAM Debug Mode. Use this input to activate the debug mode and allow direct read/write access to the PBA. You can also use the MSIX_RAM_CTRL_DBG_PBA field in MSIX_RAM_CTRL_OFF to activate debug mode. Debug mode turns off the.." "0,1" newline bitfld.long 0xC 20. "DBG_TABLE,MSIX Table RAM Debug Mode. Use this input to activate the debug mode and allow direct read/write access to the Table." "0,1" newline bitfld.long 0xC 19. "APP_ERR_FUNC_NUM,The number of the function that is reporting the error indicated app_err_bus valid when app_hdr_valid is asserted. Correctable and Uncorrected Internal errors (app_err_bus[10:9]) are not function specific and are recorded for all.." "0,1" newline bitfld.long 0xC 18. "APP_ERR_ADVISORY,Indicates that your application error is an advisory error. Your application should assert app_err_advisory under either of the following conditions: The controller is configured to mask completion timeout errors your application is.." "0,1" newline bitfld.long 0xC 17. "WAKEN_DO_OVRDVAL,WAKEN_DO_OVRDVAL" "0,1" newline bitfld.long 0xC 16. "WAKEN_DO_OVRDEN,WAKEN_DO_OVRDEN" "0,1" newline bitfld.long 0xC 15. "WAKEN_OE_OVRDVAL,WAKEN_OE_OVRDVAL" "0,1" newline bitfld.long 0xC 14. "WAKEN_OE_OVRDEN,WAKEN_OE_OVRDEN" "0,1" newline bitfld.long 0xC 13. "WAKEN_IN_OVRDVAL,WAKEN_IN_OVRDVAL" "0,1" newline bitfld.long 0xC 12. "WAKEN_IN_OVRDEN,WAKEN_IN_OVRDEN" "0,1" newline bitfld.long 0xC 11. "PERSTN_DO_OVRDVAL,PERSTN_DO_OVRDVAL" "0,1" newline bitfld.long 0xC 10. "PERSTN_DO_OVRDEN,PERSTN_DO_OVRDEN" "0,1" newline bitfld.long 0xC 9. "PERSTN_OE_OVRDVAL,PERSTN_OE_OVRDVAL" "0,1" newline bitfld.long 0xC 8. "PERSTN_OE_OVRDEN,PERSTN_OE_OVRDEN" "0,1" newline bitfld.long 0xC 7. "PERSTN_IN_OVRDVAL,PERSTN_IN_OVRDVAL" "0,1" newline bitfld.long 0xC 6. "PERSTN_IN_OVRDEN,PERSTN_IN_OVRDEN" "0,1" newline bitfld.long 0xC 5. "CLKREQN_DO_OVRDVAL,CLKREQN_DO_OVRDVAL" "0,1" newline bitfld.long 0xC 4. "CLKREQN_DO_OVRDEN,CLKREQN_DO_OVRDEN" "0,1" newline bitfld.long 0xC 3. "CLKREQN_OE_OVRDVAL,CLKREQN_OE_OVRDVAL" "0,1" newline bitfld.long 0xC 2. "CLKREQN_OE_OVRDEN,CLKREQN_OE_OVRDEN" "0,1" newline bitfld.long 0xC 1. "CLKREQN_IN_OVRDVAL,CLKREQN_IN_OVRDVAL" "0,1" newline bitfld.long 0xC 0. "CLKREQN_IN_OVRDEN,CLKREQN_IN_OVRDEN" "0,1" line.long 0x10 "CTRL_3,CTRL_3" bitfld.long 0x10 30.--31. "SYS_MRL_SENSOR_CHGED,MRL Sensor Changed. Indicates that the state of MRL sensor has changed. There is a separate sys_mrl_sensor_chged input bit for each function in your controller configuration." "0,1,2,3" newline hexmask.long.word 0x10 20.--29. 1. "VEN_MSG_LEN,The Length field for the vendor-defined Message TLP (indicates length of data payload in dwords).Should be set to 0x0." newline hexmask.long.byte 0x10 15.--19. 1. "VEN_MSG_TYPE,The Type field for the vendor-defined Message TLP." newline bitfld.long 0x10 12.--14. "VEN_MSG_VFUNC_NUM,Number of the virtual function accessing the VMI interface. The PCIe SR-IOV specification starts numbering VFs at 1. To ease timing during synthesis the PCIe controller starts numbering VFs at 0. For example ven_msg_vfunc_num=0 refers.." "0,1,2,3,4,5,6,7" newline bitfld.long 0x10 9.--11. "VEN_MSG_TC,The Traffic Class field for the vendor-defined Message TLP." "0,1,2,3,4,5,6,7" newline bitfld.long 0x10 7.--8. "VEN_MSG_ATTR,The Attributes field for the vendor-defined Message TLP. - Width is three bits when CX_IDO_ENABLE =1 - Width is two bits when CX_IDO_ENABLE =0" "?,Width is two bits when CX_IDO_ENABLE =0,?,?" newline bitfld.long 0x10 5.--6. "VEN_MSG_FMT,The Format field for the vendor-defined Message TLP. Should be set to 0x1." "0,1,2,3" newline bitfld.long 0x10 4. "VEN_MSG_VFUNC_ACTIVE,Indicates that a VF is accessing the VMI. - 0: No VF is active and ven_msg_vfunc_num is invalid. A PF is valid and identified by ven_msg_func_num. - 1: A VF is active and is identified by ven_msg_vfunc_num." "No VF is active and ven_msg_vfunc_num is invalid,A VF is active and is identified by.." newline bitfld.long 0x10 3. "VEN_MSG_FUNC_NUM,Function Number for the vendor-defined Message TLP. Function numbering starts at '0'." "0,1" newline bitfld.long 0x10 2. "VEN_MSG_EP,The Poisoned TLP (EP) bit for the vendor-defined Message TLP." "0,1" newline bitfld.long 0x10 1. "VEN_MSG_TD,The TLP Digest (TD) bit for the vendor-defined Message TLP valid when ven_msg_req is asserted." "0,1" newline bitfld.long 0x10 0. "VEN_MSG_REQ,Request from your application to send a vendor-defined Message. Once asserted ven_msg_req must remain asserted until the controller asserts ven_msg_grant." "0,1" repeat 16. (list 0x4 0x5 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF 0x10 0x11 0x13 0x14 0x15 0x17 )(list 0x0 0x4 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x3C 0x40 0x44 0x4C ) group.long ($2+0x78)++0x3 line.long 0x0 "CTRL_$1,CTRL_4" hexmask.long 0x0 0.--31. 1. "VEN_MSG_DATA_31_0,Third and fourth dwords of the Vendor Defined Message header where: - Bytes 8-11 (third header dword) =ven_msg_data[63:32] - Bytes 12-15 (fourth header dword) =ven_msg_data[31:0] where ven_msg_data[7:0] =byte 15" repeat.end repeat 12. (list 0x19 0x1A 0x1B 0x1D 0x1E 0x1F 0x20 0x21 0x22 0x23 0x24 0x25 )(list 0x54 0x58 0x5C 0x64 0x68 0x6C 0x70 0x74 0x78 0x7C 0x80 0x84 ) group.long ($2+0x78)++0x3 line.long 0x0 "CTRL_$1,CTRL_4" hexmask.long 0x0 0.--31. 1. "VEN_MSG_DATA_31_0,Third and fourth dwords of the Vendor Defined Message header where: - Bytes 8-11 (third header dword) =ven_msg_data[63:32] - Bytes 12-15 (fourth header dword) =ven_msg_data[31:0] where ven_msg_data[7:0] =byte 15" repeat.end group.long 0x80++0x7 line.long 0x0 "CTRL_6,CTRL_6" bitfld.long 0x0 31. "MSI_FNSEL,MSI_FNSEL" "0,1" newline bitfld.long 0x0 30. "VEN_MSI_OVRDEN,VEN_MSI_OVRDEN" "0,1" newline bitfld.long 0x0 29. "VEN_MSI_REQ,Request from your application to send an MSI when MSI is enabled.When MSI-X is enabled instead of MSI assertion of ven_msi_req causes the controller to generate an MSI-X message. Once asserted ven_msi_req must remain asserted until the.." "0,1" newline hexmask.long.byte 0x0 24.--28. 1. "VEN_MSI_VECTOR,Used to modulate the lower five bits of the MSI Data register when multiple message mode is enabled." newline bitfld.long 0x0 21.--23. "VEN_MSI_TC,Traffic Class of the MSI request valid when ven_msi_req is asserted." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 20. "VEN_MSI_VFUNC_ACTIVE,Indicates that the MSI request is coming from a VF. - 0: No VF is active and ven_msi_vfunc_num is invalid. A PF is valid and identified by ven_msi_func_num. - 1: A VF is active and is identified by ven_msi_vfunc_num." "No VF is active and ven_msi_vfunc_num is invalid,A VF is active and is identified by.." newline bitfld.long 0x0 17.--19. "VEN_MSI_VFUNC_NUM,Identifies the VF which is making the MSI request. The PCIe SR-IOV specification starts numbering VFs at 1. To ease timing during synthesis the PCIe controller starts numbering VFs at 0. For example ven_msi_vfunc_num=0 refers to the.." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 16. "VEN_MSI_FUNC_NUM,The function number of the MSI request. Function numbering starts at '0'." "0,1" newline hexmask.long.byte 0x0 8.--15. 1. "VEN_MSG_CODE,The Message Code for the vendor-defined Message TLP." newline hexmask.long.byte 0x0 0.--7. 1. "VEN_MSG_TAG,Tag for the vendor-defined Message TLP." line.long 0x4 "CTRL_7,CTRL_7" hexmask.long.byte 0x4 24.--31. 1. "SLV_AWMISC_INFO_P_TAG,AXI Slave Write Request Tag. Sets the TAG number for output posted requests. It is expected that your application normally sets this to '0' except when generating ATS invalidate requests." newline bitfld.long 0x4 23. "SLV_WMISC_INFO_EP,AXI Slave Write Data transaction related misc information. This is an optional signal that your application can use to poison write requests.When asserted the controller sets the Poisoned TLP (EP) bit in the TLP header of the current.." "0,1" newline bitfld.long 0x4 22. "PTM_AUTO_UPDATE_SIGNAL,Indicates that the controller should update the PTM Requester Context and Clock automatically every 10ms." "0,1" newline bitfld.long 0x4 21. "PTM_MANUAL_UPDATE_PULSE,Indicates that the controller should update the PTM Requester Context and Clock now." "0,1" newline bitfld.long 0x4 20. "PTM_EXTERNAL_MASTER_STROBE,PTM External Master Time Strobe." "0,1" newline hexmask.long.byte 0x4 12.--19. 1. "APP_VF_FRS_READY,Defers FRS messaging for a VF when set to '0'." newline bitfld.long 0x4 10.--11. "APP_PF_FRS_READY,Defers FRS messaging when set to '0'." "0,1,2,3" newline bitfld.long 0x4 9. "APP_DRS_READY,Defers DRS messaging when set to '0'." "0,1" newline bitfld.long 0x4 7.--8. "SYS_EML_INTERLOCK_ENGAGED,System Electromechanical Interlock Engaged. Indicates whether the system electromechanical interlock is engaged and controls the state of the Electromechanical Interlock Status bit in the Slot Status register." "0,1,2,3" newline bitfld.long 0x4 5.--6. "SYS_CMD_CPLED_INT,Command completed Interrupt. Indicates that the Hot-Plug controller completed a command. There is a separate sys_cmd_cpled_int input bit for each function in your controller configuration." "0,1,2,3" newline bitfld.long 0x4 3.--4. "SYS_PRE_DET_CHGED,Presence Detect Changed. Indicates that the state of card present detector has changed. There is a separate sys_pre_det_chged input bit for each function in your controller configuration." "0,1,2,3" newline bitfld.long 0x4 0.--2. "DIAG_CTRL_BUS,Diagnostic Control Bus - x01: Insert LCRC error by inverting the LSB of LCRC - x10: Insert ECRC error by inverting the LSB of ECRC The rising edge of these two signals ([1:0]) enable the controller to assert an LCRC or ECRC to the packet.." "?,Insert LCRC error by inverting the LSB of LCRC,?,?,?,?,?,?" group.long 0xB0++0x3 line.long 0x0 "CTRL_18,CTRL_18" bitfld.long 0x0 31. "SLV_USER_SEL,SLV_USER_SEL" "0,1" newline bitfld.long 0x0 29.--30. "MSTR_ARUSER_OVRDVAL_33_32,MSTR_ARUSER_OVRDVAL_33_32" "0,1,2,3" newline bitfld.long 0x0 27.--28. "MSTR_AWUSER_OVRDVAL_33_32,MSTR_AWUSER_OVRDVAL_33_32" "0,1,2,3" newline bitfld.long 0x0 26. "APP_LTR_MSG_FUNC_NUM,APP_LTR_MSG_FUNC_NUM" "0,1" newline bitfld.long 0x0 25. "APP_LTR_MSG_REQ,APP_LTR_MSG_REQ" "0,1" newline bitfld.long 0x0 24. "APP_PM_VF_XMT_PME_7,APP_PM_VF_XMT_PME_7" "0,1" newline bitfld.long 0x0 23. "APP_PM_VF_XMT_PME_6,APP_PM_VF_XMT_PME_6" "0,1" newline bitfld.long 0x0 22. "APP_PM_VF_XMT_PME_5,APP_PM_VF_XMT_PME_5" "0,1" newline bitfld.long 0x0 21. "APP_PM_VF_XMT_PME_4,APP_PM_VF_XMT_PME_4" "0,1" newline bitfld.long 0x0 20. "APP_PM_VF_XMT_PME_3,APP_PM_VF_XMT_PME_3" "0,1" newline bitfld.long 0x0 19. "APP_PM_VF_XMT_PME_2,APP_PM_VF_XMT_PME_2" "0,1" newline bitfld.long 0x0 18. "APP_PM_VF_XMT_PME_1,APP_PM_VF_XMT_PME_1" "0,1" newline bitfld.long 0x0 17. "APP_PM_VF_XMT_PME_0,APP_PM_VF_XMT_PME_0" "0,1" newline hexmask.long.word 0x0 4.--16. 1. "MSTR_RMISC_INFO,MSTR_RMISC_INFO" newline bitfld.long 0x0 2.--3. "MSTR_RMISC_INFO_CPL_STAT,MSTR_RMISC_INFO_CPL_STAT" "0,1,2,3" newline bitfld.long 0x0 0.--1. "MSTR_BMISC_INFO_CPL_STAT,MSTR_BMISC_INFO_CPL_STAT" "0,1,2,3" group.long 0xC0++0x3 line.long 0x0 "CTRL_22,CTRL_22" bitfld.long 0x0 31. "SLV_WMISC_INFO_SILENTDROP,SLV_WMISC_INFO_SILENTDROP" "0,1" newline bitfld.long 0x0 28.--30. "SLV_AWMISC_INFO_VFUNC_NUM,SLV_AWMISC_INFO_VFUNC_NUM" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 27. "SLV_AWMISC_INFO_VFUNC_ACTIVE,SLV_AWMISC_INFO_VFUNC_ACTIVE" "0,1" newline bitfld.long 0x0 26. "SLV_AWMISC_INFO_FUNC_NUM,SLV_AWMISC_INFO_FUNC_NUM" "0,1" newline bitfld.long 0x0 25. "SLV_AWMISC_INFO_ATU_BYPASS,SLV_AWMISC_INFO_ATU_BYPASS" "0,1" newline hexmask.long 0x0 0.--24. 1. "SLV_AWMISC_INFO,SLV_AWMISC_INFO" group.long 0xC8++0x3 line.long 0x0 "CTRL_24,CTRL_24" bitfld.long 0x0 30.--31. "MSTR_USER_SEL,MSTR_USER_SEL" "0,1,2,3" newline bitfld.long 0x0 27.--29. "SLV_ARMISC_INFO_VFUNC_NUM,SLV_ARMISC_INFO_VFUNC_NUM" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 26. "SLV_ARMISC_INFO_VFUNC_ACTIVE,SLV_ARMISC_INFO_VFUNC_ACTIVE" "0,1" newline bitfld.long 0x0 25. "SLV_ARMISC_INFO_FUNC_NUM,SLV_ARMISC_INFO_FUNC_NUM" "0,1" newline hexmask.long 0x0 0.--24. 1. "SLV_ARMISC_INFO,SLV_ARMISC_INFO" group.long 0xD8++0x3 line.long 0x0 "CTRL_28,CTRL_28" hexmask.long.word 0x0 21.--31. 1. "RSVD0,RSVD0" newline hexmask.long.byte 0x0 13.--20. 1. "APP_BUS_NUM,APP_BUS_NUM" newline hexmask.long.byte 0x0 8.--12. 1. "APP_DEV_NUM,APP_DEV_NUM" newline bitfld.long 0x0 7. "APP_MSI_CTRL_EN,APP_MSI_CTRL_EN" "0,1" newline hexmask.long.byte 0x0 0.--6. 1. "STS_DEBUG_SEL,STS_DEBUG_SEL" repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x4 0x8 0xC 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C ) group.long ($2+0x100)++0x3 line.long 0x0 "MAP_$1,MAP_0" hexmask.long 0x0 0.--31. 1. "LUT_MAP_MID_31_0,LUT_MAP_MID_31_0" repeat.end repeat 16. (list 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1A 0x1B 0x1C 0x1D 0x1E 0x1F )(list 0x40 0x44 0x48 0x4C 0x50 0x54 0x58 0x5C 0x60 0x64 0x68 0x6C 0x70 0x74 0x78 0x7C ) group.long ($2+0x100)++0x3 line.long 0x0 "MAP_$1,MAP_0" hexmask.long 0x0 0.--31. 1. "LUT_MAP_MID_31_0,LUT_MAP_MID_31_0" repeat.end repeat 16. (list 0x20 0x21 0x22 0x23 0x24 0x25 0x26 0x27 0x28 0x29 0x2A 0x2B 0x2C 0x2D 0x2E 0x2F )(list 0x80 0x84 0x88 0x8C 0x90 0x94 0x98 0x9C 0xA0 0xA4 0xA8 0xAC 0xB0 0xB4 0xB8 0xBC ) group.long ($2+0x100)++0x3 line.long 0x0 "MAP_$1,MAP_0" hexmask.long 0x0 0.--31. 1. "LUT_MAP_MID_31_0,LUT_MAP_MID_31_0" repeat.end repeat 16. (list 0x30 0x31 0x32 0x33 0x34 0x35 0x36 0x37 0x38 0x39 0x3A 0x3B 0x3C 0x3D 0x3E 0x3F )(list 0xC0 0xC4 0xC8 0xCC 0xD0 0xD4 0xD8 0xDC 0xE0 0xE4 0xE8 0xEC 0xF0 0xF4 0xF8 0xFC ) group.long ($2+0x100)++0x3 line.long 0x0 "MAP_$1,MAP_0" hexmask.long 0x0 0.--31. 1. "LUT_MAP_MID_31_0,LUT_MAP_MID_31_0" repeat.end rgroup.long 0x200++0x3 line.long 0x0 "STS_0,STS_0" bitfld.long 0x0 29.--31. "PM_L1SUB_STATE,Power management L1 sub-states FSM state" "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x0 24.--28. 1. "PM_MASTER_STATE,Power management master FSM state." newline bitfld.long 0x0 22.--23. "PM_PME_EN,PME Enable bit in the PMCSR. There is 1 bit of pm_pme_en for each configured function." "0,1,2,3" newline hexmask.long.byte 0x0 16.--21. 1. "PM_DSTATE,The current power management D-state of the function: - 000b: D0 - 001b: D1 - 010b: D2 - 011b: D3 - 100b: Uninitialized - Other values: Not applicable" newline bitfld.long 0x0 13.--15. "PM_CURNT_STATE,Indicates the current power state. The pm_curnt_state output is intended for debugging purposes not for system operation." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 12. "PM_L1_ENTRY_STARTED,L1 entry process is in progress." "0,1" newline bitfld.long 0x0 11. "PM_LINKST_IN_L1SUB,Power management is in L1 substate. Indicates when the link has entered L1 substates." "0,1" newline bitfld.long 0x0 10. "PM_LINKST_L2_EXIT,Power management is exiting L2 state. Not applicable for downstream port." "0,1" newline bitfld.long 0x0 9. "PM_LINKST_IN_L2,Power management is in L2 state." "0,1" newline bitfld.long 0x0 8. "PM_LINKST_IN_L1,Power management is in L1 state." "0,1" newline bitfld.long 0x0 7. "PM_LINKST_IN_L0S,Power management is in L0s state. Indicates in L0_STALL state when M-PCIe" "0,1" newline hexmask.long.byte 0x0 1.--6. 1. "SMLH_LTSSM_STATE,Current state of the LTSSM. Encoding is defined as follows: 6'h00: S_DETECT_QUIET 6'h01: S_DETECT_ACT 6'h02: S_POLL_ACTIVE 6'h03: S_POLL_COMPLIANCE 6'h04: S_POLL_CONFIG 6'h05: S_PRE_DETECT_QUIET 6'h06: S_DETECT_WAIT 6'h07:.." newline bitfld.long 0x0 0. "RADM_IDLE,RADM activity status signal. The controller creates the en_radm_clk_g output by gating this signal with the output of the RADM_CLK_GATING_EN field in the CLOCK_GATING_CTRL_OFF register. For debug purposes only." "0,1" group.long 0x204++0xB line.long 0x0 "STS_1,STS_1" bitfld.long 0x0 30.--31. "TRGT_TIMEOUT_CPL_ATTR,The Attributes value of the timed out completion. - Width is three bits when CX_IDO_ENABLE =1 - Width is two bits when CX_IDO_ENABLE =0" "?,Width is two bits when CX_IDO_ENABLE =0,?,?" newline bitfld.long 0x0 27.--29. "TRGT_TIMEOUT_CPL_TC,The TC of the timed out completion." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 26. "TRGT_TIMEOUT_CPL_VFUNC_ACTIVE,Indicates that the timeout is coming from a VF (Virtual function). - 0: No VF is active and trgt_timeout_cpl_vfunc_num is invalid. A PF is valid and identified by trgt_timeout_cpl_func_num - 1: A VF is active and is.." "No VF is active and trgt_timeout_cpl_vfunc_num..,A VF is active and is identified by.." newline bitfld.long 0x0 23.--25. "TRGT_TIMEOUT_CPL_VFUNC_NUM,Indicates which virtual function (VF) timed out. The PCIe SR-IOV specification starts numbering VFs at 1. To ease timing during synthesis the PCIe controller starts numbering VFs at 0. For example trgt_timeout_cpl_ vfunc_num=0.." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 22. "TRGT_TIMEOUT_CPL_FUNC_NUM,TRGT_TIMEOUT_CPL_FUNC_NUM" "0,1" newline hexmask.long.byte 0x0 14.--21. 1. "CFG_FLR_VF_ACTIVE,Set when the software initiates FLR a virtual function by writing to the 'Initiate FLR' register bit of that function. This signal is held asserted until the reset of both the application and internal controller logic has been.." newline rbitfld.long 0x0 12.--13. "CFG_FLR_PF_ACTIVE,Set when the software initiates FLR a physical function by writing to the 'Initiate FLR' register bit of that function. This signal is held asserted until reset of both the application and controller logic has been completed." "0,1,2,3" newline rbitfld.long 0x0 10.--11. "CFG_EML_CONTROL,Electromechanical Interlock Control. The state of the Electromechanical Interlock Control bit in the Slot Control register." "0,1,2,3" newline rbitfld.long 0x0 9. "CFG_L1SUB_EN,Indicates that any of the L1 Substates are enabled in the L1 Substates Control 1 Register. Could be used by your application in a downstream port to determine when not to drive CLKREQ# such as when L1" "0,1" newline rbitfld.long 0x0 7.--8. "AUX_PM_EN,AUX_PM_EN" "0,1,2,3" newline rbitfld.long 0x0 5.--6. "PM_STATUS,PME Status bit from the PMCSR. There is 1 bit of pm_status for each configured function." "0,1,2,3" newline hexmask.long.byte 0x0 0.--4. 1. "PM_SLAVE_STATE,Power management slave FSM state." line.long 0x4 "STS_2,STS_2" bitfld.long 0x4 30.--31. "RADM_TIMEOUT_CPL_ATTR,The Attributes field of the timed out completion" "0,1,2,3" newline rbitfld.long 0x4 29. "RADM_QOVERFLOW,Pulse indicating that one or more of the P/NP/CPL receive queues have overflowed. There is a 1-bit indication for each configured virtual channel. You can connect this output to your internal error reporting mechanism." "?,bit indication for each configured virtual channel" newline rbitfld.long 0x4 28. "RADM_Q_NOT_EMPTY,Level indicating that the receive queues contain TLP header/data." "0,1" newline bitfld.long 0x4 27. "RADM_TIMEOUT_FUNC_NUM,The function Number of the timed out completion. Function numbering starts at '0'." "0,1" newline rbitfld.long 0x4 26. "RADM_XFER_PENDING,Receive request pending status. Indicates Receive TLP requests are pending that is requests sent to the RTRGT1 or RTRGT0 interfaces are awaiting a response from your application." "0,1" newline rbitfld.long 0x4 25. "EDMA_XFER_PENDING,eDMA transfer pending status. Indicates eDMA Write or Read Channel transfers are pending that is DMA Write or Read Channels have not finished transferring data." "0,1" newline rbitfld.long 0x4 24. "BRDG_DBI_XFER_PENDING,AXI Slave DBI transfer pending status. Indicates AXI DBI Slave Read or Write transfers are pending that is AXI Slave transfers are awaiting a response from the controller." "0,1" newline rbitfld.long 0x4 22.--23. "CFG_INT_DISABLE,When high a functions ability to generate INTx messages is Disabled" "0,1,2,3" newline rbitfld.long 0x4 20.--21. "CFG_CMD_CPLED_INT_EN,Slot Control Command Completed Interrupt Enable." "0,1,2,3" newline hexmask.long.byte 0x4 12.--19. 1. "TRGT_TIMEOUT_LOOKUP_ID,The target completion LUT lookup ID of the timed out completion" newline hexmask.long.word 0x4 0.--11. 1. "TRGT_TIMEOUT_CPL_LEN,The Length of the timed out completion." line.long 0x8 "STS_3,STS_3" rbitfld.long 0x8 30.--31. "CFG_PWR_CTRLER_CTRL,Controls the system power controller (from bit 10 of the Slot Control register) per function: - 0: Power On - 1: Power Off" "Power On,Power Off,?,?" newline rbitfld.long 0x8 28.--29. "CFG_END2END_TLP_PFX_BLCK,The value of the End-End TLP Prefix Blocking field in the Device Control 2 register." "0,1,2,3" newline hexmask.long.byte 0x8 23.--27. 1. "CFG_PBUS_DEV_NUM,The device number assigned to the function. The number of bits depends the value of MULTI_DEVICE_AND_BUS_PER_FUNC_EN: - If MULTI_DEVICE_AND_BUS_PER_FUNC_EN =0 there are five bits of cfg_pbus_dev_num ([4:0]) regardless of the number of.." newline hexmask.long.word 0x8 11.--22. 1. "RADM_TIMEOUT_CPL_LEN,Length (in bytes) of the timed out completion. For a split completion it indicates the number of bytes remaining to be delivered when the completion timed out." newline hexmask.long.byte 0x8 3.--10. 1. "RADM_TIMEOUT_CPL_TAG,The Tag field of the timed out completion." newline bitfld.long 0x8 0.--2. "RADM_TIMEOUT_VFUNC_NUM,Indicates which virtual function (VF) had a completion timeout. The PCIe SR-IOV specification starts numbering VFs at '1'. To ease timing during synthesis the PCIe controller starts numbering VFs at '0' ." "0,1,2,3,4,5,6,7" rgroup.long 0x210++0xB line.long 0x0 "STS_4,STS_4" bitfld.long 0x0 31. "SMLH_LTSSM_STATE_RCVRY_EQ,This status signal is asserted during all Recovery Equalization states." "0,1" newline bitfld.long 0x0 29.--30. "CFG_DLL_STATE_CHGED_EN,Slot Control DLL State Change Enable" "0,1,2,3" newline bitfld.long 0x0 27.--28. "CFG_HP_SLOT_CTRL_ACCESS,Slot Control Accessed." "0,1,2,3" newline bitfld.long 0x0 25.--26. "CFG_RELAX_ORDER_EN,Contents of the 'Enable Relaxed Ordering' field(PCIE_CAP_EN_REL_ORDER) in the 'Device Control and Status' register (DEVICE_CONTROL_DEVICE_STATUS) register." "0,1,2,3" newline bitfld.long 0x0 23.--24. "CFG_NO_SNOOP_EN,Contents of the 'Enable No Snoop' field (PCIE_CAP_EN_NO_SNOOP)in the 'Device Control and Status' register(DEVICE_CONTROL_DEVICE_STATUS) register." "0,1,2,3" newline hexmask.long.byte 0x0 15.--22. 1. "PM_VF_STATUS,PME Status bit from the VF PMCSR. There is 1 bit of pm_status for each configured function. Each bit field corresponds to one of the NVF virtual functions." newline bitfld.long 0x0 13.--14. "CFG_VF_EN,Identifies those physical functions that have virtual functions enabled." "0,1,2,3" newline bitfld.long 0x0 11.--12. "CFG_ATTEN_BUTTON_PRESSED_EN,Slot Control Attention Button Pressed Enable." "0,1,2,3" newline bitfld.long 0x0 9.--10. "CFG_PWR_FAULT_DET_EN,Slot Control Power Fault Detect Enable." "0,1,2,3" newline bitfld.long 0x0 7.--8. "CFG_MRL_SENSOR_CHGED_EN,Slot Control MRL Sensor Changed Enable." "0,1,2,3" newline bitfld.long 0x0 5.--6. "CFG_PRE_DET_CHGED_EN,Slot Control Presence Detect Changed Enable." "0,1,2,3" newline bitfld.long 0x0 4. "PTM_REQ_RESPONSE_TIMEOUT,PTM Requester Response Timeout. Single-cycle pulse indicating 100us timeout occurred while waiting for a PTM Response or PTM ResponseD message." "0,1" newline bitfld.long 0x0 3. "PTM_TRIGGER_ALLOWED,Indicates that a PTM Requester manual update trigger is allowed." "0,1" newline bitfld.long 0x0 2. "PTM_UPDATING,Indicates that a PTM update is in progress." "0,1" newline bitfld.long 0x0 1. "PTM_RESPONDER_RDY_TO_VALIDATE,PTM Responder Ready to Validate." "0,1" newline bitfld.long 0x0 0. "PTM_CONTEXT_VALID,O Context Valid." "0,1" line.long 0x4 "STS_5,STS_5" bitfld.long 0x4 30.--31. "CFG_HP_INT_EN,Slot Control Hot Plug Interrupt Enable." "0,1,2,3" newline bitfld.long 0x4 28.--29. "CFG_CRS_SW_VIS_EN,Indicates the value of the CRS Software Visibility enable bit in the Root Control register. Applicable only for RC devices." "0,1,2,3" newline bitfld.long 0x4 26.--27. "CFG_PM_NO_SOFT_RST,This is the value of the No Soft Reset bit in the Power Management Control and Status Register." "0,1,2,3" newline hexmask.long.word 0x4 16.--25. 1. "FRSQ_INT_MSG_NUM,FRSQ Interrupt Message Number." newline hexmask.long.byte 0x4 8.--15. 1. "CFG_PBUS_NUM,The primary bus number assigned to the function. The number of bits depends the value of MULTI_DEVICE_AND_BUS_PER_FUNC_EN: - If MULTI_DEVICE_AND_BUS_PER_FUNC_EN =0 there are eight bits of cfg_pbus_num ([7:0]) regardless of the number of.." newline bitfld.long 0x4 6.--7. "CFG_RCB,The value of the RCB bit in the Link Control register. There is 1 bit of cfg_rcb assigned to each configured function." "0,1,2,3" newline hexmask.long.byte 0x4 0.--5. 1. "CFG_MAX_PAYLOAD_SIZE,The value of the Max_Payload_Size field in the Device Control register.There are 3 bits of cfg_max_payload_size assigned to each configured function." line.long 0x8 "STS_6,STS_6" newline bitfld.long 0x8 2. "BRDG_SLV_XFER_PENDING,AXI Slave non-DBI transfer pending status. Indicates AXI non-DBI Slave Read or Write transfers are pending that is AXI Slave transfers are awaiting a response from the controller." "0,1" newline bitfld.long 0x8 1. "SMLH_LINK_UP,PHY Link up/down indicator: - 1: Link is up - 0: Link is down" "Link is down,Link is up" newline bitfld.long 0x8 0. "RDLH_LINK_UP,Data link layer up/down indicator: This status from the flow control initialization state machine indicates that flow control has been initiated and the Data link layer is ready to transmit and receive packets. For multi-VC designs this.." "Link is down,Link is up" group.long 0x21C++0x7 line.long 0x0 "STS_7,STS_7" bitfld.long 0x0 29.--31. "RADM_TIMEOUT_CPL_TC,The Traffic Class of the timed out completion." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 28. "RADM_TIMEOUT_VFUNC_ACTIVE,Indicates that a virtual function (VF) had a completion timeout. - 0: No VF is active and radm_timeout_vfunc_num is invalid. A PF is valid and identified by radm_timeout_func_num. - 1: A VF is active and is identified by.." "No VF is active and radm_timeout_vfunc_num is..,A VF is active and is identified by.." newline hexmask.long.word 0x0 18.--27. 1. "CFG_PCIE_CAP_INT_MSG_NUM,From bits [13:9] of the PCI Express Capabilities register used when MSI or MSI-X is enabled. Assertion of hp_msi or cfg_pme_msi along with a value cfg_pcie_cap_int_msg_num is equivalent to the controller receiving an MSI with.." newline hexmask.long.word 0x0 8.--17. 1. "CFG_AER_INT_MSG_NUM,From bits [31:27] of the Root Error Status register used when MSI or MSI-X is enabled. Assertion of cfg_aer_rc_err_msi along with a value cfg_aer_int_msg_num is equivalent to the controller receiving an MSI with the.." newline hexmask.long.byte 0x0 0.--7. 1. "CFG_VF_BME,Bus master enable bit from the Control Register in the PCI header of each VF. Each bit field corresponds to one of the NVF virtual functions." line.long 0x4 "STS_8,STS_8" hexmask.long.word 0x4 16.--31. 1. "RADM_MSG_REQ_ID,The requester ID of the received Message. - [15:8]: Bus number - [7:3]: Device number - [2:0]: Function number" newline hexmask.long.word 0x4 0.--15. 1. "CFG_INT_PIN,The cfg_int_pin indicates the configured value for the Interrupt Pin Register field in the BRIDGE_CTRL_INT_PIN_INT_LINE register." repeat 8. (list 0x9 0xA 0xF 0x10 0x11 0x12 0x15 0x16 )(list 0x0 0x4 0x18 0x1C 0x20 0x24 0x30 0x34 ) group.long ($2+0x224)++0x3 line.long 0x0 "STS_$1,STS_9" hexmask.long 0x0 0.--31. 1. "RADM_MSG_PAYLOAD_31_0,Received message header information. When a vendor-defined or ltr messageis received (radm_vendor_msg=1 or radm_ltr_msg=1) the controller maps radm_msg_payload to the Rx TLP header dwords as follows: When RX_TLP =1 - [31:0] = bytes.." repeat.end repeat 16. (list 0xB 0xC 0xD 0xE 0x14 0x17 0x18 0x1C 0x1D 0x1E 0x1F 0x20 0x21 0x22 0x23 0x24 )(list 0x0 0x4 0x8 0xC 0x24 0x30 0x34 0x44 0x48 0x4C 0x50 0x54 0x58 0x5C 0x60 0x64 ) rgroup.long ($2+0x22C)++0x3 line.long 0x0 "STS_$1,STS_11" hexmask.long 0x0 0.--31. 1. "PTM_LOCAL_CLOCK_31_0,PTM_LOCAL_CLOCK_31_0" repeat.end repeat 3. (list 0x25 0x26 0x27 )(list 0x68 0x6C 0x70 ) rgroup.long ($2+0x22C)++0x3 line.long 0x0 "STS_$1,STS_11" hexmask.long 0x0 0.--31. 1. "PTM_LOCAL_CLOCK_31_0,PTM_LOCAL_CLOCK_31_0" repeat.end group.long 0x24C++0x3 line.long 0x0 "STS_19,STS_19" hexmask.long.word 0x0 16.--31. 1. "MSTR_ARMISC_INFO_47_32,MSTR_ARMISC_INFO_47_32" newline hexmask.long.word 0x0 0.--15. 1. "MSTR_AWMISC_INFO_47_32,MSTR_AWMISC_INFO_47_32" rgroup.long 0x264++0xB line.long 0x0 "STS_25,STS_25" bitfld.long 0x0 30.--31. "CFG_MEM_SPACE_EN,CFG_MEM_SPACE_EN" "0,1,2,3" newline hexmask.long.byte 0x0 24.--29. 1. "CFG_MAX_RD_REQ_SIZE,CFG_MAX_RD_REQ_SIZE" newline bitfld.long 0x0 22.--23. "CFG_BUS_MASTER_EN,CFG_BUS_MASTER_EN" "0,1,2,3" newline bitfld.long 0x0 21. "CFG_DISABLE_LTR_CLR_MSG,CFG_DISABLE_LTR_CLR_MSG" "0,1" newline bitfld.long 0x0 20. "CFG_LTR_M_EN,CFG_LTR_M_EN" "0,1" newline hexmask.long.byte 0x0 16.--19. 1. "CFG_ATTEN_IND,CFG_ATTEN_IND" newline hexmask.long.byte 0x0 12.--15. 1. "CFG_PWR_IND,CFG_PWR_IND" newline bitfld.long 0x0 10.--11. "CFG_PF_PASID_PRIV_MODE_EN,CFG_PF_PASID_PRIV_MODE_EN" "0,1,2,3" newline bitfld.long 0x0 8.--9. "CFG_PF_PASID_EXECUTE_PERM_EN,CFG_PF_PASID_EXECUTE_PERM_EN" "0,1,2,3" newline bitfld.long 0x0 6.--7. "CFG_PF_PASID_EN,CFG_PF_PASID_EN" "0,1,2,3" newline hexmask.long.byte 0x0 0.--5. 1. "CFG_START_VFI,CFG_START_VFI" line.long 0x4 "STS_26,STS_26" hexmask.long.word 0x4 16.--31. 1. "CFG_SUBBUS_NUM,CFG_SUBBUS_NUM" newline hexmask.long.word 0x4 0.--15. 1. "CFG_2NDBUS_NUM,CFG_2NDBUS_NUM" line.long 0x8 "STS_27,STS_27" hexmask.long.byte 0x8 24.--31. 1. "PM_VF_PME_EN,PM_VF_PME_EN" newline hexmask.long.tbyte 0x8 0.--23. 1. "PM_VF_DSTATE,PM_VF_DSTATE" tree.end endif tree.end tree "PCIE_PHY (PCIe PHY Configuration)" sif (CORENAME()=="CORTEXR5F") tree "PCIE_PHY" base ad:0xF1200000 rgroup.word 0x0++0x1 line.word 0x0 "SUP_DIG_IDCODE_LO,Low 16 bits of IDCODE" newline hexmask.word 0x0 0.--15. 1. "DATA," rgroup.word 0x4++0x1 line.word 0x0 "SUP_DIG_IDCODE_HI,High 16 bits of IDCODE" newline hexmask.word 0x0 0.--15. 1. "DATA," group.word 0x8++0x1 line.word 0x0 "SUP_DIG_REFCLK_OVRD_IN,Override values for incoming REFCLK and RESET controls from ASIC" newline rbitfld.word 0x0 14.--15. "RESERVED_15_14,Reserved for Future use" "0,1,2,3" newline bitfld.word 0x0 13. "BG_EN_OVRD_EN,Enable override for bg_en" "0,1" newline bitfld.word 0x0 12. "BG_EN,Override value for bg_en" "0,1" newline bitfld.word 0x0 11. "REF_CLK_RANGE_OVRD_EN,Enable override for ref_range" "0,1" newline bitfld.word 0x0 8.--10. "REF_CLK_RANGE,Override value for ref_range" "0,1,2,3,4,5,6,7" newline bitfld.word 0x0 7. "REF_REPEAT_CLK_EN_OVRD_EN,Enable override for ref_repeat_clk_en" "0,1" newline bitfld.word 0x0 6. "REF_REPEAT_CLK_EN,Override value for ref_repeat_clk_en" "0,1" newline bitfld.word 0x0 5. "REF_USE_PAD_OVRD_EN,Enable override for ref_use_pad" "0,1" newline bitfld.word 0x0 4. "REF_USE_PAD,Override value for ref_use_pad" "0,1" newline bitfld.word 0x0 3. "REF_CLK_DIV2_EN_OVRD_EN,Enable override for ref_clk_div2_en" "0,1" newline bitfld.word 0x0 2. "REF_CLK_DIV2_EN,Override value for ref_clk_div2_en" "0,1" newline bitfld.word 0x0 1. "REF_CLK_EN_OVRD_EN,Enable override for ref_clk_en" "0,1" newline bitfld.word 0x0 0. "REF_CLK_EN,Override value for ref_clk_en" "0,1" group.word 0xC++0x1 line.word 0x0 "SUP_DIG_MPLLA_DIV_CLK_OVRD_IN,Override values for incoming MPLLA_DIV_CLK controls from ASIC" newline hexmask.word.byte 0x0 10.--15. 1. "RESERVED_15_10,Reserved for Future use" newline bitfld.word 0x0 9. "MPLLA_DIV_OVRD_EN,Enable overrides for MPLLA Div clock" "0,1" newline hexmask.word.byte 0x0 1.--8. 1. "MPLLA_DIV_MULTIPLIER,Override value for mplla_div_multiplier" newline bitfld.word 0x0 0. "MPLLA_DIV_CLK_EN,Override value for mplla_div_clk_en" "0,1" group.word 0x10++0x1 line.word 0x0 "SUP_DIG_MPLLB_DIV_CLK_OVRD_IN,Override values for incoming MPLLB_DIV_CLK controls from ASIC" newline hexmask.word.byte 0x0 10.--15. 1. "RESERVED_15_10,Reserved for Future use" newline bitfld.word 0x0 9. "MPLLB_DIV_OVRD_EN,Enable overrides for MPLLB Div clock" "0,1" newline hexmask.word.byte 0x0 1.--8. 1. "MPLLB_DIV_MULTIPLIER,Override value for mpllb_div_multiplier" newline bitfld.word 0x0 0. "MPLLB_DIV_CLK_EN,Override value for mpllb_div_clk_en" "0,1" group.word 0x14++0x1 line.word 0x0 "SUP_DIG_MPLLA_OVRD_IN_0,Override values for incoming MPLLA controls from ASIC" newline bitfld.word 0x0 15. "OVRD_EN,Enable override values for all inputs controlled by this register (mplla_word_div2_en)" "0,1" newline bitfld.word 0x0 12.--14. "MPLLA_TX_CLK_DIV,Override value for mplla_tx_clk_div" "0,1,2,3,4,5,6,7" newline hexmask.word.byte 0x0 4.--11. 1. "MPLLA_MULTIPLIER,Override value for mplla_multiplier" newline bitfld.word 0x0 3. "MPLLA_DIV10_CLK_EN,Override value for mplla_div10_clk_en" "0,1" newline bitfld.word 0x0 2. "MPLLA_DIV8_CLK_EN,Override value for mplla_div8_clk_en" "0,1" newline bitfld.word 0x0 1. "REF_CLK_MPLLA_DIV2_EN,Override value for ref_clk_mplla_div2_en" "0,1" newline bitfld.word 0x0 0. "MPLLA_EN,Override value for mplla_en" "0,1" group.word 0x18++0x1 line.word 0x0 "SUP_DIG_MPLLA_OVRD_IN_1,Override values for incoming MPLLA controls from ASIC" newline hexmask.word.byte 0x0 9.--15. 1. "RESERVED_15_9,Reserved for Future use" newline bitfld.word 0x0 8. "MPLLA_WORD_DIV2_EN,Override value for mplla_word_div2_en" "0,1" newline bitfld.word 0x0 7. "MPLLA_SSC_OVRD_EN,Enable override values for MPLLA SSC inputs" "0,1" newline bitfld.word 0x0 4.--6. "MPLLA_SSC_CLK_SEL,Override value for mplla_ssc_clk_sel" "0,1,2,3,4,5,6,7" newline bitfld.word 0x0 1.--3. "MPLLA_SSC_RANGE,Override value for mplla_ssc_range" "0,1,2,3,4,5,6,7" newline bitfld.word 0x0 0. "MPLLA_SSC_EN,Override value for mplla_ssc_en" "0,1" group.word 0x1C++0x1 line.word 0x0 "SUP_DIG_MPLLA_OVRD_IN_2,Override values for incoming MPLLA controls from ASIC" newline hexmask.word.byte 0x0 11.--15. 1. "RESERVED_15_11,Reserved for Future use" newline hexmask.word 0x0 0.--10. 1. "MPLLA_FRACN_CTRL,Override value for mplla_fracn_ctrl" group.word 0x20++0x1 line.word 0x0 "SUP_DIG_MPLLA_BANDWIDTH_OVRD_IN,Override values for incoming MPLLA bandwidth controls from ASIC" newline hexmask.word 0x0 0.--15. 1. "MPLLA_BANDWIDTH,Override value for mplla_bandwidth[15:0]" group.word 0x24++0x1 line.word 0x0 "SUP_DIG_MPLLB_OVRD_IN_0,Override values for incoming MPLLB controls from ASIC" newline bitfld.word 0x0 15. "OVRD_EN,Enable override values for all inputs controlled by this register" "0,1" newline bitfld.word 0x0 12.--14. "MPLLB_TX_CLK_DIV,Override value for mpllb_tx_clk_div" "0,1,2,3,4,5,6,7" newline hexmask.word.byte 0x0 4.--11. 1. "MPLLB_MULTIPLIER,Override value for mpllb_multiplier" newline bitfld.word 0x0 3. "MPLLB_DIV10_CLK_EN,Override value for mpllb_div10_clk_en" "0,1" newline bitfld.word 0x0 2. "MPLLB_DIV8_CLK_EN,Override value for mpllb_div8_clk_en" "0,1" newline bitfld.word 0x0 1. "REF_CLK_MPLLB_DIV2_EN,Override value for ref_clk_mpllb_div2_en" "0,1" newline bitfld.word 0x0 0. "MPLLB_EN,Override value for mpllb_en" "0,1" group.word 0x28++0x1 line.word 0x0 "SUP_DIG_MPLLB_OVRD_IN_1,Override values for incoming MPLLB controls from ASIC" newline hexmask.word.byte 0x0 9.--15. 1. "RESERVED_15_9,Reserved for Future use" newline bitfld.word 0x0 8. "MPLLB_WORD_DIV2_EN,Override value for mpllb_word_div2_en" "0,1" newline bitfld.word 0x0 7. "MPLLB_SSC_OVRD_EN,Enable override values for MPLLB SSC inputs" "0,1" newline bitfld.word 0x0 4.--6. "MPLLB_SSC_CLK_SEL,Override value for mpllb_ssc_clk_sel[2:0]" "0,1,2,3,4,5,6,7" newline bitfld.word 0x0 1.--3. "MPLLB_SSC_RANGE,Override value for mpllb_ssc_range" "0,1,2,3,4,5,6,7" newline bitfld.word 0x0 0. "MPLLB_SSC_EN,Override value for mpllb_ssc_en" "0,1" group.word 0x2C++0x1 line.word 0x0 "SUP_DIG_MPLLB_OVRD_IN_2,Override values for incoming MPLLB controls from ASIC" newline hexmask.word.byte 0x0 11.--15. 1. "RESERVED_15_11,Reserved for Future use" newline hexmask.word 0x0 0.--10. 1. "MPLLB_FRACN_CTRL,Override value for mpllb_fracn_ctrl" group.word 0x30++0x1 line.word 0x0 "SUP_DIG_MPLLB_BANDWIDTH_OVRD_IN,Override values for incoming MPLLB bandwidth controls from ASIC" newline hexmask.word 0x0 0.--15. 1. "MPLLB_BANDWIDTH,Override value for mpllb_bandwidth[15:0]" group.word 0x34++0x1 line.word 0x0 "SUP_DIG_SUP_OVRD_IN,Override values for support block ASIC inputs" newline hexmask.word 0x0 5.--15. 1. "RESERVED_15_5,Reserved for Future use" newline bitfld.word 0x0 4. "RES_OVRD_EN,Enable override of res_req_in and res_ack_in" "0,1" newline bitfld.word 0x0 3. "RES_ACK_IN,Override value for res_ack_in" "0,1" newline bitfld.word 0x0 2. "RES_REQ_IN,Override value for res_req_in" "0,1" newline bitfld.word 0x0 1. "RTUNE_OVRD_EN,Enable override of rtune_req" "0,1" newline bitfld.word 0x0 0. "RTUNE_REQ,Override value for rtune_req" "0,1" group.word 0x38++0x1 line.word 0x0 "SUP_DIG_SUP_OVRD_OUT,Override values for support block ASIC outputs" newline rbitfld.word 0x0 14.--15. "RESERVED_15_14,Reserved for Future use" "0,1,2,3" newline bitfld.word 0x0 13. "BG_SUP_STATE_OVRD_EN,Enable override for bg_sup_state signal" "0,1" newline bitfld.word 0x0 12. "BG_SUP_STATE,Override value for bg_sup_state signal" "0,1" newline bitfld.word 0x0 11. "BG_LANE_STATE_OVRD_EN,Enable override for bg_lane_state signal" "0,1" newline bitfld.word 0x0 10. "BG_LANE_STATE,Override value for bg_lane_state signal" "0,1" newline bitfld.word 0x0 9. "MPLLB_STATE_OVRD_EN,Enable override for mpllb_state output" "0,1" newline bitfld.word 0x0 8. "MPLLB_STATE,Override value for mpllb_state output" "0,1" newline bitfld.word 0x0 7. "MPLLA_STATE_OVRD_EN,Enable override for mplla_state output" "0,1" newline bitfld.word 0x0 6. "MPLLA_STATE,Override value for mplla_state output" "0,1" newline bitfld.word 0x0 5. "RES_ACK_OUT_OVRD_EN,Enable override for res_ack_out output" "0,1" newline bitfld.word 0x0 4. "RES_ACK_OUT,Override value for res_ack_out output" "0,1" newline bitfld.word 0x0 3. "RES_REQ_OUT_OVRD_EN,Enable override for res_req_out output" "0,1" newline bitfld.word 0x0 2. "RES_REQ_OUT,Override value for res_req_out output" "0,1" newline bitfld.word 0x0 1. "RTUNE_ACK_OVRD_EN,Enable override for rtune_ack output" "0,1" newline bitfld.word 0x0 0. "RTUNE_ACK,Override value for rtune_ack output" "0,1" group.word 0x3C++0x1 line.word 0x0 "SUP_DIG_LVL_OVRD_IN,Override values for level settings" newline hexmask.word.byte 0x0 10.--15. 1. "RESERVED_15_10,Reserved for Future use" newline bitfld.word 0x0 9. "TX_VBOOST_LVL_EN,Enable override value for tx_vboost_lvl" "0,1" newline bitfld.word 0x0 6.--8. "TX_VBOOST_LVL,Override value for tx_vboost_lvl" "0,1,2,3,4,5,6,7" newline bitfld.word 0x0 5. "RX_VREF_CTRL_EN,Enable override value for rx_vref_ctrl" "0,1" newline hexmask.word.byte 0x0 0.--4. 1. "RX_VREF_CTRL,Override value for rx_vref_ctrl" group.word 0x40++0x1 line.word 0x0 "SUP_DIG_DEBUG,Debug controls" newline hexmask.word 0x0 3.--15. 1. "RESERVED_15_3,Reserved for Future use" newline bitfld.word 0x0 0.--2. "DTB_SEL,The lane DTB's are OR'd together with the support DTB signals selected with the below encodings 0 - none 1 - mplla DTB output 2 - mpllb DTB output 3 - rtune DTB output" "none,mplla DTB output,mpllb DTB output,rtune DTB output,?,?,?,?" rgroup.word 0x44++0x1 line.word 0x0 "SUP_DIG_MPLLA_ASIC_IN_0,Current values for incoming MPLLA controls from ASIC" newline bitfld.word 0x0 15. "RESERVED_15_15,Reserved for Future use" "0,1" newline bitfld.word 0x0 12.--14. "MPLLA_TX_CLK_DIV,Value from ASIC for mplla_tx_clk_div" "0,1,2,3,4,5,6,7" newline hexmask.word.byte 0x0 4.--11. 1. "MPLLA_MULTIPLIER,Value from ASIC for mplla_multiplier" newline bitfld.word 0x0 3. "MPLLA_DIV10_CLK_EN,Value from ASIC for mplla_div10_clk_en" "0,1" newline bitfld.word 0x0 2. "MPLLA_DIV8_CLK_EN,Value from ASIC for mplla_div8_clk_en" "0,1" newline bitfld.word 0x0 1. "REF_CLK_MPLLA_DIV2_EN,Value from ASIC for ref_clk_mplla_div2_en" "0,1" newline bitfld.word 0x0 0. "MPLLA_EN,Value from ASIC for mplla_en" "0,1" rgroup.word 0x48++0x1 line.word 0x0 "SUP_DIG_MPLLA_ASIC_IN_1,Current values for incoming MPLLA controls from ASIC" newline hexmask.word.byte 0x0 8.--15. 1. "RESERVED_15_8,Reserved for Future use" newline bitfld.word 0x0 7. "MPLLA_WORD_DIV2_EN,Value from mplla_word_div2_en" "0,1" newline bitfld.word 0x0 4.--6. "MPLLA_SSC_CLK_SEL,Value from mplla_ssc_clk_sel" "0,1,2,3,4,5,6,7" newline bitfld.word 0x0 1.--3. "MPLLA_SSC_RANGE,Value from mplla_ssc_range" "0,1,2,3,4,5,6,7" newline bitfld.word 0x0 0. "MPLLA_SSC_EN,Value from mplla_ssc_en" "0,1" rgroup.word 0x4C++0x1 line.word 0x0 "SUP_DIG_MPLLA_ASIC_IN_2,Current values for incoming MPLLA controls from ASIC" newline hexmask.word.byte 0x0 11.--15. 1. "RESERVED_15_11,Reserved for Future use" newline hexmask.word 0x0 0.--10. 1. "MPLLA_FRACN_CTRL,Value from mplla_fracn_ctrl" rgroup.word 0x50++0x1 line.word 0x0 "SUP_DIG_MPLLB_ASIC_IN_0,Current values for incoming MPLLB controls from ASIC" newline bitfld.word 0x0 15. "RESERVED_15_15,Reserved for Future use" "0,1" newline bitfld.word 0x0 12.--14. "MPLLB_TX_CLK_DIV,Value from ASIC for mpllb_tx_clk_div" "0,1,2,3,4,5,6,7" newline hexmask.word.byte 0x0 4.--11. 1. "MPLLB_MULTIPLIER,Value from ASIC for mpllb_multiplier" newline bitfld.word 0x0 3. "MPLLB_DIV10_CLK_EN,Value from ASIC for mpllb_div10_clk_en" "0,1" newline bitfld.word 0x0 2. "MPLLB_DIV8_CLK_EN,Value from ASIC for mpllb_div8_clk_en" "0,1" newline bitfld.word 0x0 1. "REF_CLK_MPLLB_DIV2_EN,Value from ASIC for ref_clk_mpllb_div2_en" "0,1" newline bitfld.word 0x0 0. "MPLLB_EN,Value from ASIC for mpllb_en" "0,1" rgroup.word 0x54++0x1 line.word 0x0 "SUP_DIG_MPLLB_ASIC_IN_1,Current values for incoming MPLLB controls from ASIC" newline hexmask.word.byte 0x0 8.--15. 1. "RESERVED_15_8,Reserved for Future use" newline bitfld.word 0x0 7. "MPLLB_WORD_DIV2_EN,Value from mpllb_word_div2_en" "0,1" newline bitfld.word 0x0 4.--6. "MPLLB_SSC_CLK_SEL,Value from mpllb_ssc_clk_sel" "0,1,2,3,4,5,6,7" newline bitfld.word 0x0 1.--3. "MPLLB_SSC_RANGE,Value from mpllb_ssc_range" "0,1,2,3,4,5,6,7" newline bitfld.word 0x0 0. "MPLLB_SSC_EN,Value from mpllb_ssc_en" "0,1" rgroup.word 0x58++0x1 line.word 0x0 "SUP_DIG_MPLLB_ASIC_IN_2,Current values for incoming MPLLB controls from ASIC" newline hexmask.word.byte 0x0 11.--15. 1. "RESERVED_15_11,Reserved for Future use" newline hexmask.word 0x0 0.--10. 1. "MPLLB_FRACN_CTRL,Value from mpllb_fracn_ctrl" rgroup.word 0x5C++0x1 line.word 0x0 "SUP_DIG_MPLLA_DIV_CLK_ASIC_IN,Current values for incoming MPLLA_DIV_CLK controls from ASIC" newline hexmask.word.byte 0x0 9.--15. 1. "RESERVED_15_9,Reserved for Future use" newline hexmask.word.byte 0x0 1.--8. 1. "MPLLA_DIV_MULTIPLIER,Value from mplla_div_multiplier" newline bitfld.word 0x0 0. "MPLLA_DIV_CLK_EN,Value from mplla_div_clk_en" "0,1" rgroup.word 0x60++0x1 line.word 0x0 "SUP_DIG_MPLLB_DIV_CLK_ASIC_IN,Current values for incoming MPLLB_DIV_CLK controls from ASIC" newline hexmask.word.byte 0x0 9.--15. 1. "RESERVED_15_9,Reserved for Future use" newline hexmask.word.byte 0x0 1.--8. 1. "MPLLB_DIV_MULTIPLIER,Value from mpllb_div_multiplier" newline bitfld.word 0x0 0. "MPLLB_DIV_CLK_EN,Value from mpllb_div_clk_en" "0,1" rgroup.word 0x64++0x1 line.word 0x0 "SUP_DIG_ASIC_IN,Current values for incoming SUP control signals from ASIC" newline bitfld.word 0x0 15. "TEST_TX_REF_CLK_EN,Value from ASIC for test_tx_refclk_en" "0,1" newline bitfld.word 0x0 14. "MPLLB_STATE,Value to ASIC for mpllb_state_i" "0,1" newline bitfld.word 0x0 13. "MPLLA_STATE,Value to ASIC for mplla_state_i" "0,1" newline bitfld.word 0x0 12. "RES_ACK_OUT,Value to ASIC for res_ack_out_i" "0,1" newline bitfld.word 0x0 11. "RES_ACK_IN,Value from ASIC for res_req_in" "0,1" newline bitfld.word 0x0 10. "RES_REQ_OUT,Value to ASIC for res_ack_out_i" "0,1" newline bitfld.word 0x0 9. "RES_REQ_IN,Value from ASIC for res_req_in" "0,1" newline bitfld.word 0x0 8. "RTUNE_ACK,Value to ASIC for rtune_ack_i" "0,1" newline bitfld.word 0x0 7. "RTUNE_REQ,Value from ASIC for rtune_req" "0,1" newline bitfld.word 0x0 6. "TEST_POWERDOWN,Value from ASIC for test_powerdown" "0,1" newline bitfld.word 0x0 5. "TEST_BURNIN,Value from ASIC for test_burnin" "0,1" newline bitfld.word 0x0 4. "REF_USE_PAD,Value from ASIC for ref_use_pad" "0,1" newline bitfld.word 0x0 3. "REF_REPEAT_CLK_EN,Value from ASIC for ref_repeat_clk_en" "0,1" newline bitfld.word 0x0 2. "REF_CLK_DIV2_EN,Value from ASIC for ref_clk_div2_en" "0,1" newline bitfld.word 0x0 1. "REF_CLK_EN,Value from ASIC for ref_clk_en" "0,1" newline bitfld.word 0x0 0. "PHY_RESET,Value from ASIC for phy_reset" "0,1" rgroup.word 0x68++0x1 line.word 0x0 "SUP_DIG_LVL_ASIC_IN,Current values for incoming level controls from ASIC" newline hexmask.word.byte 0x0 8.--15. 1. "RESERVED_15_8,Reserved for Future use" newline bitfld.word 0x0 5.--7. "TX_VBOOST_LVL,Value from ASIC for tx_vboost_lvl" "0,1,2,3,4,5,6,7" newline hexmask.word.byte 0x0 0.--4. 1. "RX_VREF_CTRL,Value from ASIC for rx_vref_ctrl" rgroup.word 0x6C++0x1 line.word 0x0 "SUP_DIG_BANDGAP_ASIC_IN,Current values for incoming bandgap control from ASIC" newline hexmask.word 0x0 1.--15. 1. "RESERVED_15_1,Reserved for Future use" newline bitfld.word 0x0 0. "BG_EN,Value from ASIC for bg_en" "0,1" rgroup.word 0x70++0x1 line.word 0x0 "SUP_DIG_MPLLA_BANDWIDTH_ASIC_IN,Current values for incoming MPLLA bandwidth controls from ASIC" newline hexmask.word 0x0 0.--15. 1. "MPLLA_BANDWIDTH,Value from ASIC for mplla_bandwidth" rgroup.word 0x74++0x1 line.word 0x0 "SUP_DIG_MPLLB_BANDWIDTH_ASIC_IN,Current values for incoming MPLLB bandwidth controls from ASIC" newline hexmask.word 0x0 0.--15. 1. "MPLLB_BANDWIDTH,Value from ASIC for mpllb_bandwidth" group.word 0x80++0x1 line.word 0x0 "SUP_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL,MPLL Calibration controls" newline bitfld.word 0x0 15. "EXT_CAL_DONE,Set the external calibration status to done" "0,1" newline hexmask.word.byte 0x0 7.--14. 1. "EXT_COARSE_TUNE,Value of mpll_ana_coarse_tune_i[7:0] in external calibration mode" newline bitfld.word 0x0 6. "EXT_CHKFRQ_EN,Check the frequency of the MPLL Only valid in external calibration mode" "0,1" newline bitfld.word 0x0 5. "MPLL_EXTCAL,Enable external calibration of MPLL" "0,1" newline bitfld.word 0x0 4. "MPLL_SKIPCAL,Skip automatic (internal) calibration of MPLL (and also skip external calibration if it is enabled) If skipcal is enabled then MPLL_SKIPCAL_COARSE_TUNE is used." "0,1" newline hexmask.word.byte 0x0 0.--3. 1. "LOAD_CNT,MSBs for the CHKFRQ FSM ld_val[10:0] load value 0x0 - gives a ld_val of 0 no PPM difference can be detected 0x8 - gives a load value of 1024 3000PPM resolution possible 0xA - gives a load value of 1280 2343PPM resolution possible 0xB - gives.." group.word 0x84++0x1 line.word 0x0 "SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD,MPLL override controls" newline hexmask.word.byte 0x0 10.--15. 1. "RESERVED_15_10,Reserved for Future use" newline hexmask.word.byte 0x0 5.--9. 1. "DTB_SEL,DTB select for MPLL dtb signals" newline bitfld.word 0x0 4. "FAST_MPLL_LOCK,Enable fast MPLL locking" "0,1" newline bitfld.word 0x0 3. "FAST_MPLL_PWRUP,Enable fast MPLL powerup" "0,1" newline bitfld.word 0x0 2. "MPLL_PCLK_EN,Overrides the PWR FSM mpll_pclk_en signal" "0,1" newline bitfld.word 0x0 1. "MPLL_FBDIGCLK_EN,Overrides the PWR FSM mpll_fb_dig_clk_en signal" "0,1" newline bitfld.word 0x0 0. "OVRD_SEL,Override enable bit" "0,1" rgroup.word 0x88++0x1 line.word 0x0 "SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT,MPLL status register" newline bitfld.word 0x0 15. "RESERVED_15_15,Reserved for Future use" "0,1" newline bitfld.word 0x0 14. "MPLL_ANA_EN,Current value of mpll_ana_en_i" "0,1" newline bitfld.word 0x0 13. "MPLL_RST,Current value of mpll_ana_rst_i" "0,1" newline bitfld.word 0x0 12. "MPLL_CAL,Current value of mpll_ana_cal_i" "0,1" newline bitfld.word 0x0 11. "MPLL_FBCLK_EN,Current value of mpll_ana_fb_clk_en_i" "0,1" newline bitfld.word 0x0 10. "MPLL_OUTPUT_EN,Current value of mpll_ana_output_en_i" "0,1" newline bitfld.word 0x0 9. "MPLL_PCLK_EN,Current value of mpll_pclk_en" "0,1" newline bitfld.word 0x0 8. "MPLL_L_LANES,Current value of lane_mpll_l" "0,1" newline bitfld.word 0x0 7. "MPLL_R_LANES,Current value of lane_mpll_r" "0,1" newline bitfld.word 0x0 6. "MPLL_CAL_RDY,Current value of mpll_cal_rdy" "0,1" newline bitfld.word 0x0 5. "CHKFRQ_DONE,Current value of mpll_chkfrq_done" "0,1" newline bitfld.word 0x0 4. "MPLL_TOOSLOW,Current value of mpll_tooslow" "0,1" newline hexmask.word.byte 0x0 0.--3. 1. "FSM_STATE,Current value of the PWR FSM state register" group.word 0x8C++0x1 line.word 0x0 "SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_MISC_TIME_THRESHOLD,Thresholds for MPLL CAL Update timer and MPLL VCO Stabilization timer" newline rbitfld.word 0x0 13.--15. "RESERVED_15_13,Reserved for Future use" "0,1,2,3,4,5,6,7" newline hexmask.word.byte 0x0 9.--12. 1. "MPLL_CAL_UPDATE_TIME_THRESHOLD,Threshold for the MPLL calibration control word update timer in terms of number of ref_rang_clk cycles" newline hexmask.word 0x0 0.--8. 1. "VCO_STABILIZATION_TIME_THRESHOLD,Threshold for the VCO stabilization timer in terms of number of reference clock cycles Here the reference clock means the one that is fed to the phase detector of the corresponding PLL not the raw reference clock." group.word 0x90++0x1 line.word 0x0 "SUP_DIG_MPLLA_MPLL_PWR_CTL_PCLK_EN_AND_VCO_CLK_STABILIZATION_TIME_THRESHOLD,Thresholds for PCLK enable and MPLL VCO Clock Stabilization timer" newline hexmask.word.byte 0x0 11.--15. 1. "PCLK_EN_TIME_THRESHOLD,Threshold for the PCLK enable timer in terms of number of ref_range_clk cycles" newline hexmask.word 0x0 0.--10. 1. "VCO_CLK_STABILIZATION_TIME_THRESHOLD,Threshold for the VCO clock stabilization timer in terms of number of reference clock cycles Here the reference clock means the one that is fed to the phase detector of the corresponding PLL not the raw reference clock." group.word 0x94++0x1 line.word 0x0 "SUP_DIG_MPLLA_MPLL_PWR_CTL_PCLK_DIS_AND_MPLL_VCO_PWRDN_THRESHOLD,Thresholds for PCLK disable and MPLL VCO POWER DOWN timer" newline hexmask.word.byte 0x0 10.--15. 1. "RESERVED_15_10,Reserved for Future use" newline hexmask.word.byte 0x0 5.--9. 1. "MPLL_VCO_PWRDN_TIME_THRESHOLD,Threshold for the MPLL VCO power down timer in terms of number of ref_range_clk cycles" newline hexmask.word.byte 0x0 0.--4. 1. "PCLK_DIS_TIME_THRESHOLD,Threshold for the PCLK disable timer in terms of number of ref_range_clk cycles" group.word 0x98++0x1 line.word 0x0 "SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_FBCLK_EN_AND_MPLL_FBDIGCLK_DIS_AND_MPLL_ANA_PWRUP_TIME_THRESHOLD,Thresholds for MPLL feedback clock enable and MPLL feedback digital clock disable and MPLL ANA POWER UP timer" newline rbitfld.word 0x0 15. "RESERVED_15_15,Reserved for Future use" "0,1" newline hexmask.word.byte 0x0 8.--14. 1. "MPLL_ANA_PWRUP_TIME_THRESHOLD,Threshold for the MPLL analog power up timer in terms of number of ref_range_clk cycles" newline hexmask.word.byte 0x0 4.--7. 1. "MPLL_FBDIGCLK_DIS_TIME_THRESHOLD,Threshold for the MPLL feedback digital clock disable timer in terms of number of ref_range_clk cycles" newline hexmask.word.byte 0x0 0.--3. 1. "MPLL_FBCLK_EN_TIME_THRESHOLD,Threshold for the MPLL feedback clock enable timer in terms of number of ref_range_clk cycles" rgroup.word 0x9C++0x1 line.word 0x0 "SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_COARSE_TUNE_VAL,MPLL coarse_tune value register" newline hexmask.word.byte 0x0 8.--15. 1. "RESERVED_15_8,Reserved for Future use" newline hexmask.word.byte 0x0 0.--7. 1. "MPLL_COARSE_TUNE_VAL,Current value of mpll_ana_coarse_tune_i" rgroup.word 0xA0++0x1 line.word 0x0 "SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_SKIPCAL_COARSE_TUNE,Value for MPLL coarse_tune when skipping calibration" newline hexmask.word.byte 0x0 8.--15. 1. "RESERVED_15_8,Reserved for Future use" newline hexmask.word.byte 0x0 0.--7. 1. "MPLL_SKIPCAL_COARSE_TUNE,Value for MPLL coarse_tune when calibration is skipped" group.word 0xA4++0x1 line.word 0x0 "SUP_DIG_MPLLA_SSC_SS_PHASE,Current MPLL phase selector value" newline hexmask.word.byte 0x0 12.--15. 1. "RESERVED_15_12,Reserved for Future use" newline bitfld.word 0x0 11. "ZERO_FREQ,Zero frequency register. NOTES: Must be set for PHASE writes to stick (2 reads needed to read value)" "0,1" newline hexmask.word 0x0 2.--10. 1. "VAL,Phase value from zero reference (2 reads needed to read value)" newline bitfld.word 0x0 0.--1. "DTHR,Bits below the useful resolution (2 reads needed to read value)" "0,1,2,3" group.word 0xA8++0x1 line.word 0x0 "SUP_DIG_MPLLA_SSC_SS_FREQ_0,Frequency Control for Spread Spectrum #0" newline rbitfld.word 0x0 13.--15. "RESERVED_15_13,Reserved for Future use" "0,1,2,3,4,5,6,7" newline bitfld.word 0x0 12. "FREQ_0_OVRD,Frequency Reigster Override. NOTE: Must be set for PHASE writes to stick" "0,1" newline hexmask.word 0x0 0.--11. 1. "FREQ_CNT_INIT,Initial Frequency Counter Value" group.word 0xAC++0x1 line.word 0x0 "SUP_DIG_MPLLA_SSC_SS_FREQ_1,Frequency Control for Spread Spectrum #1" newline hexmask.word.byte 0x0 9.--15. 1. "RESERVED_15_9,Reserved for Future use" newline bitfld.word 0x0 8. "FREQ_1_OVRD,Frequency Reigster Override. NOTE: Must be set for PHASE writes to stick" "0,1" newline hexmask.word.byte 0x0 0.--7. 1. "FREQ_PK,Peak Frequency Value (for changing direction)" group.word 0xB0++0x1 line.word 0x0 "SUP_DIG_MPLLB_MPLL_PWR_CTL_CAL_CTRL,MPLL Calibration controls" newline bitfld.word 0x0 15. "EXT_CAL_DONE,Set the external calibration status to done" "0,1" newline hexmask.word.byte 0x0 7.--14. 1. "EXT_COARSE_TUNE,Value of mpll_ana_coarse_tune_i[7:0] in external calibration mode" newline bitfld.word 0x0 6. "EXT_CHKFRQ_EN,Check the frequency of the MPLL Only valid in external calibration mode" "0,1" newline bitfld.word 0x0 5. "MPLL_EXTCAL,Enable external calibration of MPLL" "0,1" newline bitfld.word 0x0 4. "MPLL_SKIPCAL,Skip automatic (internal) calibration of MPLL (and also skip external calibration if it is enabled) If skipcal is enabled then MPLL_SKIPCAL_COARSE_TUNE is used." "0,1" newline hexmask.word.byte 0x0 0.--3. 1. "LOAD_CNT,MSBs for the CHKFRQ FSM ld_val[10:0] load value 0x0 - gives a ld_val of 0 no PPM difference can be detected 0x8 - gives a load value of 1024 3000PPM resolution possible 0xA - gives a load value of 1280 2343PPM resolution possible 0xB - gives.." group.word 0xB4++0x1 line.word 0x0 "SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD,MPLL override controls" newline hexmask.word.byte 0x0 10.--15. 1. "RESERVED_15_10,Reserved for Future use" newline hexmask.word.byte 0x0 5.--9. 1. "DTB_SEL,DTB select for MPLL dtb signals" newline bitfld.word 0x0 4. "FAST_MPLL_LOCK,Enable fast MPLL locking" "0,1" newline bitfld.word 0x0 3. "FAST_MPLL_PWRUP,Enable fast MPLL powerup" "0,1" newline bitfld.word 0x0 2. "MPLL_PCLK_EN,Overrides the PWR FSM mpll_pclk_en signal" "0,1" newline bitfld.word 0x0 1. "MPLL_FBDIGCLK_EN,Overrides the PWR FSM mpll_fb_dig_clk_en signal" "0,1" newline bitfld.word 0x0 0. "OVRD_SEL,Override enable bit" "0,1" rgroup.word 0xB8++0x1 line.word 0x0 "SUP_DIG_MPLLB_MPLL_PWR_CTL_STAT,MPLL status register" newline bitfld.word 0x0 15. "RESERVED_15_15,Reserved for Future use" "0,1" newline bitfld.word 0x0 14. "MPLL_ANA_EN,Current value of mpll_ana_en_i" "0,1" newline bitfld.word 0x0 13. "MPLL_RST,Current value of mpll_ana_rst_i" "0,1" newline bitfld.word 0x0 12. "MPLL_CAL,Current value of mpll_ana_cal_i" "0,1" newline bitfld.word 0x0 11. "MPLL_FBCLK_EN,Current value of mpll_ana_fb_clk_en_i" "0,1" newline bitfld.word 0x0 10. "MPLL_OUTPUT_EN,Current value of mpll_ana_output_en_i" "0,1" newline bitfld.word 0x0 9. "MPLL_PCLK_EN,Current value of mpll_pclk_en" "0,1" newline bitfld.word 0x0 8. "MPLL_L_LANES,Current value of lane_mpll_l" "0,1" newline bitfld.word 0x0 7. "MPLL_R_LANES,Current value of lane_mpll_r" "0,1" newline bitfld.word 0x0 6. "MPLL_CAL_RDY,Current value of mpll_cal_rdy" "0,1" newline bitfld.word 0x0 5. "CHKFRQ_DONE,Current value of mpll_chkfrq_done" "0,1" newline bitfld.word 0x0 4. "MPLL_TOOSLOW,Current value of mpll_tooslow" "0,1" newline hexmask.word.byte 0x0 0.--3. 1. "FSM_STATE,Current value of the PWR FSM state register" group.word 0xBC++0x1 line.word 0x0 "SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_MISC_TIME_THRESHOLD,Thresholds for MPLL CAL Update timer and MPLL VCO Stabilization timer" newline rbitfld.word 0x0 13.--15. "RESERVED_15_13,Reserved for Future use" "0,1,2,3,4,5,6,7" newline hexmask.word.byte 0x0 9.--12. 1. "MPLL_CAL_UPDATE_TIME_THRESHOLD,Threshold for the MPLL calibration control word update timer in terms of number of ref_rang_clk cycles" newline hexmask.word 0x0 0.--8. 1. "VCO_STABILIZATION_TIME_THRESHOLD,Threshold for the VCO stabilization timer in terms of number of reference clock cycles Here the reference clock means the one that is fed to the phase detector of the corresponding PLL not the raw reference clock." group.word 0xC0++0x1 line.word 0x0 "SUP_DIG_MPLLB_MPLL_PWR_CTL_PCLK_EN_AND_VCO_CLK_STABILIZATION_TIME_THRESHOLD,Thresholds for PCLK enable and MPLL VCO Clock Stabilization timer" newline hexmask.word.byte 0x0 11.--15. 1. "PCLK_EN_TIME_THRESHOLD,Threshold for the PCLK enable timer in terms of number of ref_range_clk cycles" newline hexmask.word 0x0 0.--10. 1. "VCO_CLK_STABILIZATION_TIME_THRESHOLD,Threshold for the VCO clock stabilization timer in terms of number of reference clock cycles Here the reference clock means the one that is fed to the phase detector of the corresponding PLL not the raw reference clock." group.word 0xC4++0x1 line.word 0x0 "SUP_DIG_MPLLB_MPLL_PWR_CTL_PCLK_DIS_AND_MPLL_VCO_PWRDN_THRESHOLD,Thresholds for PCLK disable and MPLL VCO POWER DOWN timer" newline hexmask.word.byte 0x0 10.--15. 1. "RESERVED_15_10,Reserved for Future use" newline hexmask.word.byte 0x0 5.--9. 1. "MPLL_VCO_PWRDN_TIME_THRESHOLD,Threshold for the MPLL VCO power down timer in terms of number of ref_range_clk cycles" newline hexmask.word.byte 0x0 0.--4. 1. "PCLK_DIS_TIME_THRESHOLD,Threshold for the PCLK disable timer in terms of number of ref_range_clk cycles" group.word 0xC8++0x1 line.word 0x0 "SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_FBCLK_EN_AND_MPLL_FBDIGCLK_DIS_AND_MPLL_ANA_PWRUP_TIME_THRESHOLD,Thresholds for MPLL feedback clock enable and MPLL feedback digital clock disable and MPLL ANA POWER UP timer" newline rbitfld.word 0x0 15. "RESERVED_15_15,Reserved for Future use" "0,1" newline hexmask.word.byte 0x0 8.--14. 1. "MPLL_ANA_PWRUP_TIME_THRESHOLD,Threshold for the MPLL analog power up timer in terms of number of ref_range_clk cycles" newline hexmask.word.byte 0x0 4.--7. 1. "MPLL_FBDIGCLK_DIS_TIME_THRESHOLD,Threshold for the MPLL feedback digital clock disable timer in terms of number of ref_range_clk cycles" newline hexmask.word.byte 0x0 0.--3. 1. "MPLL_FBCLK_EN_TIME_THRESHOLD,Threshold for the MPLL feedback clock enable timer in terms of number of ref_range_clk cycles" rgroup.word 0xCC++0x1 line.word 0x0 "SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_COARSE_TUNE_VAL,MPLL coarse_tune value register" newline hexmask.word.byte 0x0 8.--15. 1. "RESERVED_15_8,Reserved for Future use" newline hexmask.word.byte 0x0 0.--7. 1. "MPLL_COARSE_TUNE_VAL,Current value of mpll_ana_coarse_tune_i" rgroup.word 0xD0++0x1 line.word 0x0 "SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_SKIPCAL_COARSE_TUNE,Value for MPLL coarse_tune when skipping calibration" newline hexmask.word.byte 0x0 8.--15. 1. "RESERVED_15_8,Reserved for Future use" newline hexmask.word.byte 0x0 0.--7. 1. "MPLL_SKIPCAL_COARSE_TUNE,Value for MPLL coarse_tune when calibration is skipped" group.word 0xD4++0x1 line.word 0x0 "SUP_DIG_MPLLB_SSC_SS_PHASE,Current MPLL phase selector value" newline hexmask.word.byte 0x0 12.--15. 1. "RESERVED_15_12,Reserved for Future use" newline bitfld.word 0x0 11. "ZERO_FREQ,Zero frequency register. NOTES: Must be set for PHASE writes to stick (2 reads needed to read value)" "0,1" newline hexmask.word 0x0 2.--10. 1. "VAL,Phase value from zero reference (2 reads needed to read value)" newline bitfld.word 0x0 0.--1. "DTHR,Bits below the useful resolution (2 reads needed to read value)" "0,1,2,3" group.word 0xD8++0x1 line.word 0x0 "SUP_DIG_MPLLB_SSC_SS_FREQ_0,Frequency Control for Spread Spectrum #0" newline rbitfld.word 0x0 13.--15. "RESERVED_15_13,Reserved for Future use" "0,1,2,3,4,5,6,7" newline bitfld.word 0x0 12. "FREQ_0_OVRD,Frequency Reigster Override. NOTE: Must be set for PHASE writes to stick" "0,1" newline hexmask.word 0x0 0.--11. 1. "FREQ_CNT_INIT,Initial Frequency Counter Value" group.word 0xDC++0x1 line.word 0x0 "SUP_DIG_MPLLB_SSC_SS_FREQ_1,Frequency Control for Spread Spectrum #1" newline hexmask.word.byte 0x0 9.--15. 1. "RESERVED_15_9,Reserved for Future use" newline bitfld.word 0x0 8. "FREQ_1_OVRD,Frequency Reigster Override. NOTE: Must be set for PHASE writes to stick" "0,1" newline hexmask.word.byte 0x0 0.--7. 1. "FREQ_PK,Peak Frequency Value (for changing direction)" group.word 0xE0++0x1 line.word 0x0 "SUP_DIG_CLK_RST_BG_PWRUP_TIME_0,BG Power UP Time Register #0" newline hexmask.word.byte 0x0 10.--15. 1. "RESERVED_15_10,Reserved for Future use" newline bitfld.word 0x0 9. "FAST_BG_WAIT,Enable fast BG times (simulation only)" "0,1" newline hexmask.word 0x0 0.--8. 1. "BG_SUP_EN_TIME,Power up time (in ref_range cycles) for bandgap in SUP (spec >=5us)" group.word 0xE4++0x1 line.word 0x0 "SUP_DIG_CLK_RST_BG_PWRUP_TIME_1,BG Power UP Time Register #1" newline hexmask.word.byte 0x0 10.--15. 1. "RESERVED_15_10,Reserved for Future use" newline hexmask.word 0x0 0.--9. 1. "BG_LANE_EN_TIME,Power up time (in ref_range cycles) for bandgap in LANE (spec >= 20us)" group.word 0x100++0x1 line.word 0x0 "SUP_ANA_MPLLA_MISC,MPLLA_MISC" newline hexmask.word.byte 0x0 8.--15. 1. "RESERVED_15_8,Reserved for Future use" newline hexmask.word.byte 0x0 4.--7. 1. "NC7_4,Reserved" newline bitfld.word 0x0 3. "PR_BYPASS,If ovrd_pr_bypass is enabled: PR_BYPASS Function 1 stops SSC and disables PMIX 0 enables SSC and PMIX" "0,1" newline bitfld.word 0x0 2. "MODE_OLD_SSC,Uses just two bits for SSC interpolation" "0,1" newline bitfld.word 0x0 1. "OVRD_PR_BYPASS,If asserted pr_bypass take effect on phase rotator bypass control" "0,1" newline bitfld.word 0x0 0. "BYPASS_BUF,To bypass CP buffers." "0,1" group.word 0x104++0x1 line.word 0x0 "SUP_ANA_MPLLA_OVRD,MPLLA_OVRD" newline hexmask.word.byte 0x0 8.--15. 1. "RESERVED_15_8,Reserved for Future use" newline bitfld.word 0x0 7. "RESET_REG,set local reset control to ON" "0,1" newline bitfld.word 0x0 6. "OVRD_RESET,enable local control of reset signal (mpll_rst)" "0,1" newline bitfld.word 0x0 5. "FB_CLK_EN_REG,set local feedback clock control to ON" "0,1" newline bitfld.word 0x0 4. "OVRD_FB_CLK_EN,enable local control of feedback clock control signal (mpll_fb_clk_en)" "0,1" newline bitfld.word 0x0 3. "CAL_REG,set local calibration control to ON" "0,1" newline bitfld.word 0x0 2. "OVRD_CAL,enable local control of calibration signal (mpll_cal)" "0,1" newline bitfld.word 0x0 1. "ENABLE_REG,set local enable control to ON" "0,1" newline bitfld.word 0x0 0. "OVRD_ENABLE,enable local control of enable signal (mpll_en)" "0,1" repeat 3. (list 0x1 0x2 0x3 )(list 0x0 0x4 0x8 ) group.word ($2+0x108)++0x1 line.word 0x0 "SUP_ANA_MPLLA_ATB$1,MPLLA_ATB1" newline hexmask.word.byte 0x0 8.--15. 1. "RESERVED_15_8,Reserved for Future use" newline bitfld.word 0x0 7. "MEAS_VREG_L,Measure vreg_left (atb_s_p)" "0,1" newline bitfld.word 0x0 6. "MEAS_VREG_S,Measure vreg_s in MPLL voltage regulator (atb_s_p)" "0,1" newline bitfld.word 0x0 5. "MEAS_VREG_VCO,Measure vreg_vco (atb_s_p)" "0,1" newline bitfld.word 0x0 4. "OVERRIDE_VREG_CP,Override vreg_cp to be 4/3X of voltage on atb_s_m." "0,1" newline bitfld.word 0x0 3. "OVERRIDE_VREG_VP,Override vreg_vp to be 4/3X of voltage on atb_s_m" "0,1" newline bitfld.word 0x0 2. "OVERRIDE_VREG_LEFT,Override vreg_left to be 4/3X of voltage on atb_s_m" "0,1" newline bitfld.word 0x0 1. "OVERRIDE_VREG_RIGHT,Override vreg_right to be 4/3X of voltage on atb_s_m" "0,1" newline bitfld.word 0x0 0. "OVERRIDE_VREG_VCO,Override vreg_vco to be 4/3X of voltage on atb_s_m" "0,1" repeat.end group.word 0x114++0x1 line.word 0x0 "SUP_ANA_MPLLB_MISC,MPLLB_MISC" newline hexmask.word.byte 0x0 8.--15. 1. "RESERVED_15_8,Reserved for Future use" newline hexmask.word.byte 0x0 4.--7. 1. "NC7_4,Reserved" newline bitfld.word 0x0 3. "PR_BYPASS,If ovrd_pr_bypass is enabled: PR_BYPASS Function 1 stops SSC and disables PMIX 0 enables SSC and PMIX" "0,1" newline bitfld.word 0x0 2. "MODE_OLD_SSC,Uses just two bits for SSC interpolation" "0,1" newline bitfld.word 0x0 1. "OVRD_PR_BYPASS,If asserted pr_bypass take effect on phase rotator bypass control" "0,1" newline bitfld.word 0x0 0. "BYPASS_BUF,To bypass CP buffers." "0,1" group.word 0x118++0x1 line.word 0x0 "SUP_ANA_MPLLB_OVRD,MPLLB_OVRD" newline hexmask.word.byte 0x0 8.--15. 1. "RESERVED_15_8,Reserved for Future use" newline bitfld.word 0x0 7. "RESET_REG,set local reset control to ON" "0,1" newline bitfld.word 0x0 6. "OVRD_RESET,enable local control of reset signal (mpll_rst)" "0,1" newline bitfld.word 0x0 5. "FB_CLK_EN_REG,set local feedback clock control to ON" "0,1" newline bitfld.word 0x0 4. "OVRD_FB_CLK_EN,enable local control of feedback clock control signal (mpll_fb_clk_en)" "0,1" newline bitfld.word 0x0 3. "CAL_REG,set local calibration control to ON" "0,1" newline bitfld.word 0x0 2. "OVRD_CAL,enable local control of calibration signal (mpll_cal)" "0,1" newline bitfld.word 0x0 1. "ENABLE_REG,set local enable control to ON" "0,1" newline bitfld.word 0x0 0. "OVRD_ENABLE,enable local control of enable signal (mpll_en)" "0,1" repeat 3. (list 0x1 0x2 0x3 )(list 0x0 0x4 0x8 ) group.word ($2+0x11C)++0x1 line.word 0x0 "SUP_ANA_MPLLB_ATB$1,MPLLB_ATB1" newline hexmask.word.byte 0x0 8.--15. 1. "RESERVED_15_8,Reserved for Future use" newline bitfld.word 0x0 7. "MEAS_VREG_L,Measure vreg_left (atb_s_p)" "0,1" newline bitfld.word 0x0 6. "MEAS_VREG_S,Measure vreg_s in MPLL voltage regulator (atb_s_p)" "0,1" newline bitfld.word 0x0 5. "MEAS_VREG_VCO,Measure vreg_vco (atb_s_p)" "0,1" newline bitfld.word 0x0 4. "OVERRIDE_VREG_CP,Override vreg_cp to be 4/3X of voltage on atb_s_m." "0,1" newline bitfld.word 0x0 3. "OVERRIDE_VREG_VP,Override vreg_vp to be 4/3X of voltage on atb_s_m" "0,1" newline bitfld.word 0x0 2. "OVERRIDE_VREG_LEFT,Override vreg_left to be 4/3X of voltage on atb_s_m" "0,1" newline bitfld.word 0x0 1. "OVERRIDE_VREG_RIGHT,Override vreg_right to be 4/3X of voltage on atb_s_m" "0,1" newline bitfld.word 0x0 0. "OVERRIDE_VREG_VCO,Override vreg_vco to be 4/3X of voltage on atb_s_m" "0,1" repeat.end group.word 0x128++0x1 line.word 0x0 "SUP_ANA_RTUNE_CTRL,RTUNE_CTRL" newline hexmask.word.byte 0x0 8.--15. 1. "RESERVED_15_8,Reserved for Future use" newline bitfld.word 0x0 7. "RT_EN_FRCON,Local rtune block enable control force rtune block on if asserted" "0,1" newline bitfld.word 0x0 6. "NC6,Reserved" "0,1" newline bitfld.word 0x0 4.--5. "RT_DAC_MODE,Margin DAC mode control bits." "0,1,2,3" newline bitfld.word 0x0 3. "RT_DAC_CHOP,[RT_DAC_CHOP RT_DAC_MODE] Function 00 Margin DAC power down 01 Margin DAC single ended output drives atb_s_m 10 Margin DAC power down 11 Margin DAC single ended output drives atb_s_p" "0,1" newline bitfld.word 0x0 2. "RT_ATB,RTUNE ATB mode control. Combines with rt_ana_mode[1:0] to perform different functions." "0,1" newline bitfld.word 0x0 1. "RT_SEL_ATBP,RTUNE ATB input select: RT_SEL_ATBP Function 1 select atb_s_p 0 select atb_s_m" "0,1" newline bitfld.word 0x0 0. "RT_SEL_ATBF,RTUNE ATB input select: RT_SEL_ATBF Function 1 select gd as input 0 select atb_s_p/m as input" "0,1" group.word 0x12C++0x1 line.word 0x0 "SUP_ANA_SWITCH_PWR_MEAS,SWITCH_PWR_MEAS" newline hexmask.word.byte 0x0 8.--15. 1. "RESERVED_15_8,Reserved for Future use" newline bitfld.word 0x0 7. "NC7,Reserved" "0,1" newline bitfld.word 0x0 6. "ATB_SW,Connect atb_s_p to atb_s_m if asserted" "0,1" newline bitfld.word 0x0 5. "ATB_SW_HALF_VPH,Connect atb_s_p to vph/2 if asserted. In this mode bit 1 should be 0." "0,1" newline bitfld.word 0x0 4. "ATB_SW_GD,Connect atb_s_m to gd if asserted" "0,1" newline bitfld.word 0x0 3. "ATB_SW_VP,Connect atb_s_p to vp if asserted" "0,1" newline bitfld.word 0x0 2. "ATB_SW_VBG_VREF,Connect vbg_vref to atb_s_p if asserted" "0,1" newline bitfld.word 0x0 1. "ATB_SW_VPH,Connect atb_s_p to vph if bit 5 is asserted Connect atb_s_p to vph/2 if bit 5 is asserted (not recommended)" "0,1" newline bitfld.word 0x0 0. "ATB_SW_VBG_BIAS_REF,Connect vbg_bias_ref to atb_s_p If asserted" "0,1" group.word 0x130++0x1 line.word 0x0 "SUP_ANA_SWITCH_MISC_MEAS,SWITCH_MISC_MEAS" newline hexmask.word.byte 0x0 8.--15. 1. "RESERVED_15_8,Reserved for Future use" newline bitfld.word 0x0 6.--7. "NC7_6,Reserved" "0,1,2,3" newline bitfld.word 0x0 5. "TEMP_MEAS,If asserted enable temperature measurement. Vbe is sent to atb_s_m vbg is sent to atb_s_p." "0,1" newline bitfld.word 0x0 4. "NC4,Reserved" "0,1" newline bitfld.word 0x0 2.--3. "SEL_VPLL_REF,Select the reference voltage for the MPLL 00 vpll_ref = 707mV 01 vpll_ref = 731mV 10 vpll_ref = 756mV (default) 11 vpll_ref = 780mV" "0,1,2,3" newline bitfld.word 0x0 0.--1. "HYST_REF,Function 00 No hysteresis 01 18mVpp hysteresis 10 35mVpp hysteresis (default) 11 50mVpp hysteresis" "0,1,2,3" group.word 0x134++0x1 line.word 0x0 "SUP_ANA_BG,BG" newline hexmask.word.byte 0x0 8.--15. 1. "RESERVED_15_8,Reserved for Future use" newline bitfld.word 0x0 5.--7. "NC7_5,Reserved" "0,1,2,3,4,5,6,7" newline bitfld.word 0x0 4. "POR_START_KICK_EN,Enable fast startup using bg kick voltage for POR bandgap outputs" "0,1" newline bitfld.word 0x0 3. "CHOP_EN,Enable chopper clock for bandgap" "0,1" newline bitfld.word 0x0 1.--2. "SEL_VBG_VREF,vbg_vref voltage level select 00 vbg_vref = 658mV 01 vbg_vref = 683mV 10 vbg_vref = 707mV (default) 11 vbg_vref = 731mV" "0,1,2,3" newline bitfld.word 0x0 0. "BYPASS_BG,Bypass bandgap with VP" "0,1" group.word 0x138++0x1 line.word 0x0 "SUP_ANA_PRESCALER_CTRL,PRESCALER_CTRL" newline hexmask.word.byte 0x0 8.--15. 1. "RESERVED_15_8,Reserved for Future use" newline hexmask.word.byte 0x0 3.--7. 1. "NC7_3,Reserved" newline bitfld.word 0x0 2. "ATB_SELECT,Connect internal ATB_S signals to external ATB_S signals" "0,1" newline bitfld.word 0x0 1. "NC1,Reserved" "0,1" newline bitfld.word 0x0 0. "MEAS_VREG,If asserted measure sup_prescaler regulator output voltage (vp_lcl) through atb_s_p" "0,1" group.word 0x180++0x1 line.word 0x0 "SUP_DIG_RTUNE_DEBUG,Resistor tuning debug controls" newline bitfld.word 0x0 15. "TXUP_GO,Enable TxUP tune to continue in manual tune mode when TYPE is TxUP tune. When in non TxUP manual tune mode this bit must be 0. When in TxUP manual tune mode and after TxUP manual tune is triggered if the read only register.." "0,1" newline hexmask.word 0x0 5.--14. 1. "VALUE,Value to use when triggering SET_VAL field only the 6 LSB's are used when setting rx cal values" newline bitfld.word 0x0 3.--4. "TYPE,Type of manual tuning or register read/write to execute 0 - ADC or read/write rt_value 1 - Rx tune or read/write rx_cal_val (only 6 bits) 2 - TxDN tune or read/write txdn_cal_val (10 bits) 3 - TxUP tune or read/write txup_cal_val (10 bits) or.." "ADC,Rx tune,TxDN tune,TxUP tune" newline bitfld.word 0x0 2. "SET_VAL,Set value Write to a 1 to manually write the register specified by the TYPE field to the value in the VALUE field" "0,1" newline bitfld.word 0x0 1. "MAN_TUNE,Write to a 1 to do a manual tuning specified by TYPE field starting a manual tune while a tune is currently running can cause unpredictable results. For use only when you know what the part is doing (w.r.t. resistor tuning)" "0,1" newline bitfld.word 0x0 0. "FLIP_COMP,Invert analog comparator output" "0,1" group.word 0x184++0x1 line.word 0x0 "SUP_DIG_RTUNE_CONFIG,Configure Rtune Operation" newline hexmask.word 0x0 6.--15. 1. "RESERVED_15_6,Reserved for Future use" newline bitfld.word 0x0 3.--5. "SUP_ANA_TERM_CTRL,Set the reference resistor in the analog Value Impedence (Ohms) 000 54 001 52 010 50 (default) 011 48 100 46 101 44 110 42 111 40" "0,1,2,3,4,5,6,7" newline bitfld.word 0x0 2. "TX_CAL_EN,Enable calibration of TX resistor" "0,1" newline bitfld.word 0x0 1. "FAST_RTUNE,Enable fast resitor tuning (simulation only)" "0,1" newline bitfld.word 0x0 0. "RX_CAL_EN,Enable calibration of RX resistor" "0,1" rgroup.word 0x188++0x1 line.word 0x0 "SUP_DIG_RTUNE_STAT,Resistor tuning register status" newline hexmask.word.byte 0x0 12.--15. 1. "RESERVED_15_12,Reserved for Future use" newline bitfld.word 0x0 10.--11. "DTB_RTUNE,DTB sampling for rtune" "0,1,2,3" newline hexmask.word 0x0 0.--9. 1. "STAT,Current value of the register specifed by the DEBUG.TYPE field" group.word 0x18C++0x1 line.word 0x0 "SUP_DIG_RTUNE_RX_SET_VAL,Set value of RX Resistor" newline hexmask.word 0x0 6.--15. 1. "RESERVED_15_6,Reserved for Future use" newline hexmask.word.byte 0x0 0.--5. 1. "RX_SET_VAL,Set value of rx resistor Writing a value to this register will set the rx resistor value." group.word 0x190++0x1 line.word 0x0 "SUP_DIG_RTUNE_TXDN_SET_VAL,Set value of TX-DN Resistor" newline hexmask.word.byte 0x0 10.--15. 1. "RESERVED_15_10,Reserved for Future use" newline hexmask.word 0x0 0.--9. 1. "TXDN_SET_VAL,Set value of tx-dn resistor Writing a value to this register will set the tx-dn resistor value." group.word 0x194++0x1 line.word 0x0 "SUP_DIG_RTUNE_TXUP_SET_VAL,Set value of TX-UP Resistor" newline hexmask.word.byte 0x0 10.--15. 1. "RESERVED_15_10,Reserved for Future use" newline hexmask.word 0x0 0.--9. 1. "TXUP_SET_VAL,Set value of tx-up resistor Writing a value to this register will set the tx-up resistor value." rgroup.word 0x198++0x1 line.word 0x0 "SUP_DIG_RTUNE_RX_STAT,RX Resistor tuning register status" newline hexmask.word 0x0 6.--15. 1. "RESERVED_15_6,Reserved for Future use" newline hexmask.word.byte 0x0 0.--5. 1. "RX_STAT,Current value of the rx resistor tuning register" rgroup.word 0x19C++0x1 line.word 0x0 "SUP_DIG_RTUNE_TXDN_STAT,TX-DN Resistor tuning register status" newline hexmask.word.byte 0x0 10.--15. 1. "RESERVED_15_10,Reserved for Future use" newline hexmask.word 0x0 0.--9. 1. "TXDN_STAT,Current value of the tx-dn resistor tuning register" rgroup.word 0x1A0++0x1 line.word 0x0 "SUP_DIG_RTUNE_TXUP_STAT,TX-UP Resistor tuning register status" newline hexmask.word.byte 0x0 10.--15. 1. "RESERVED_15_10,Reserved for Future use" newline hexmask.word 0x0 0.--9. 1. "TXUP_STAT,Current value of the tx-up resistor tuning register" group.word 0x1A4++0x1 line.word 0x0 "SUP_DIG_ANA_MPLLA_OVRD_OUT,Override value for mplla signals going to ANA" newline rbitfld.word 0x0 15. "RESERVED_15_15,Reserved for Future use" "0,1" newline bitfld.word 0x0 14. "OVRD_SEL,Override bit for mplla_ana outputs" "0,1" newline bitfld.word 0x0 13. "MPLLA_DIV_CLK_EN,Overrides the mplla_ana_div_clk_en signal" "0,1" newline hexmask.word.byte 0x0 9.--12. 1. "RESERVED," newline bitfld.word 0x0 8. "MPLLA_FBCLK_EN,Overrides the mplla_fb_clk_en signal" "0,1" newline bitfld.word 0x0 7. "MPLLA_DIV10_CLK_EN,Overrides the mplla_ana_div10_clk_en signal" "0,1" newline bitfld.word 0x0 6. "MPLLA_DIV8_CLK_EN,Overrides the mplla_ana_div8_clk_en signal" "0,1" newline bitfld.word 0x0 5. "MPLLA_OUTPUT_R_EN,Overrides the mplla_ana_output_r_en signal" "0,1" newline bitfld.word 0x0 4. "MPLLA_OUTPUT_L_EN,Overrides the mplla_ana_output_l_en signal" "0,1" newline bitfld.word 0x0 3. "MPLLA_OUTPUT_EN,Overrides the mplla_ana_output_en signal" "0,1" newline bitfld.word 0x0 2. "MPLLA_CAL,Overrides the mplla_ana_cal signal" "0,1" newline bitfld.word 0x0 1. "MPLLA_RST,Overrides the mplla_ana_rst signal" "0,1" newline bitfld.word 0x0 0. "MPLLA_ANA_EN,Overrides the mplla_ana_en signal" "0,1" group.word 0x1A8++0x1 line.word 0x0 "SUP_DIG_ANA_MPLLB_OVRD_OUT,Override value for mpllb signals going to ANA" newline rbitfld.word 0x0 15. "RESERVED_15_15,Reserved for Future use" "0,1" newline bitfld.word 0x0 14. "OVRD_SEL,Override bit for mpllb_ana outputs" "0,1" newline bitfld.word 0x0 13. "MPLLB_DIV_CLK_EN,Overrides the mpllb_ana_div_clk_en signal" "0,1" newline hexmask.word.byte 0x0 9.--12. 1. "RESERVED," newline bitfld.word 0x0 8. "MPLLB_FBCLK_EN,Overrides the mpllb_fb_clk_en signal" "0,1" newline bitfld.word 0x0 7. "MPLLB_DIV10_CLK_EN,Overrides the mpllb_ana_div10_clk_en signal" "0,1" newline bitfld.word 0x0 6. "MPLLB_DIV8_CLK_EN,Overrides the mpllb_ana_div8_clk_en signal" "0,1" newline bitfld.word 0x0 5. "MPLLB_OUTPUT_R_EN,Overrides the mpllb_ana_output_r_en signal" "0,1" newline bitfld.word 0x0 4. "MPLLB_OUTPUT_L_EN,Overrides the mpllb_ana_output_l_en signal" "0,1" newline bitfld.word 0x0 3. "MPLLB_OUTPUT_EN,Overrides the mpllb_ana_output_en signal" "0,1" newline bitfld.word 0x0 2. "MPLLB_CAL,Overrides the mpllb_ana_cal signal" "0,1" newline bitfld.word 0x0 1. "MPLLB_RST,Overrides the mpllb_ana_rst signal" "0,1" newline bitfld.word 0x0 0. "MPLLB_ANA_EN,Overrides the mpllb_ana_en signal" "0,1" group.word 0x1AC++0x1 line.word 0x0 "SUP_DIG_ANA_RTUNE_OVRD_OUT,Override value for RTUNE signals going to ANA" newline rbitfld.word 0x0 15. "RESERVED_15_15,Reserved for Future use" "0,1" newline bitfld.word 0x0 14. "RTUNE_OVRD_EN,Override bit for rtune (rt_ana_* and term) outputs" "0,1" newline hexmask.word 0x0 4.--13. 1. "RTUNE_VALUE,Overrides the rt_ana_value[9:0] signal" newline bitfld.word 0x0 3. "RTUNE_EN,Overrides the rt_ana_en signal" "0,1" newline bitfld.word 0x0 1.--2. "RTUNE_MODE,Overrides the rt_ana_mode[1:0] signal" "0,1,2,3" newline bitfld.word 0x0 0. "RTUNE_COMP_RST,Overrides the rt_ana_comp_rst signal" "0,1" rgroup.word 0x1B0++0x1 line.word 0x0 "SUP_DIG_ANA_STAT,SUP input status register for SUP ANA outputs" newline hexmask.word 0x0 1.--15. 1. "RESERVED_15_1,Reserved for Future use" newline bitfld.word 0x0 0. "RT_ANA_COMP_RESULT,Value from ANA for rt_ana_comp_result" "0,1" group.word 0x1B4++0x1 line.word 0x0 "SUP_DIG_ANA_ANA_OVRD_OUT,Override values for ana_async_rst and bandgap signals going to ANA" newline hexmask.word 0x0 5.--15. 1. "RESERVED_15_5,Reserved for Future use" newline bitfld.word 0x0 4. "ANA_ASYNC_RST_OVRD_EN,Override enable for ana_async_rst" "0,1" newline bitfld.word 0x0 3. "ANA_ASYNC_RST,Override value for reset register for analog latches" "0,1" newline bitfld.word 0x0 2. "BG_OVRD_EN,Override bit for bandgap outputs" "0,1" newline bitfld.word 0x0 1. "BG_EN,Overrides the bg_ana_en signal" "0,1" newline bitfld.word 0x0 0. "BG_FAST_START,Overrides the bg_ana_fast_start signal" "0,1" group.word 0x1B8++0x1 line.word 0x0 "SUP_DIG_ANA_MPLLA_PMIX_OVRD_OUT,Override value for mplla pmix signals going to ANA" newline hexmask.word.byte 0x0 11.--15. 1. "RESERVED_15_11,Reserved for Future use" newline bitfld.word 0x0 10. "MPLLA_PMIX_EN_OVRD_EN,Override bit for mplla_ana_pmix_en signal" "0,1" newline bitfld.word 0x0 9. "MPLLA_PMIX_SEL_OVRD_EN,Override bit for mplla_ana_pmix_sel signal" "0,1" newline bitfld.word 0x0 8. "MPLLA_PMIX_EN,Override bit for mplla_ana_pmix_en signal" "0,1" newline hexmask.word.byte 0x0 0.--7. 1. "MPLLA_PMIX_SEL,Overrides the mplla_ana_pmix_sel signal" group.word 0x1BC++0x1 line.word 0x0 "SUP_DIG_ANA_MPLLB_PMIX_OVRD_OUT,Override value for mpllb pmix signals going to ANA" newline hexmask.word.byte 0x0 11.--15. 1. "RESERVED_15_11,Reserved for Future use" newline bitfld.word 0x0 10. "MPLLB_PMIX_EN_OVRD_EN,Override bit for mpllb_ana_pmix_en signal" "0,1" newline bitfld.word 0x0 9. "MPLLB_PMIX_SEL_OVRD_EN,Override bit for mpllb_ana_pmix_sel signal" "0,1" newline bitfld.word 0x0 8. "MPLLB_PMIX_EN,Override bit for mpllb_ana_pmix_en signal" "0,1" newline hexmask.word.byte 0x0 0.--7. 1. "MPLLB_PMIX_SEL,Overrides the mpllb_ana_pmix_sel signal" group.word 0x4000++0x1 line.word 0x0 "LANE0_DIG_ASIC_LANE_OVRD_IN,Override values for incoming LANE controls from ASIC" newline hexmask.word 0x0 3.--15. 1. "RESERVED_15_3,Reserved for Future use" newline bitfld.word 0x0 2. "EN,Enable override values for all inputs controlled by this register" "0,1" newline bitfld.word 0x0 1. "LANE_RX2TX_PAR_LB,Override value for lane_rx2tx_par_lb_en_r" "0,1" newline bitfld.word 0x0 0. "LANE_TX2RX_SER_LB,Override value for lane_tx2rx_ser_lb_en_r" "0,1" group.word 0x4004++0x1 line.word 0x0 "LANE0_DIG_ASIC_TX_OVRD_IN_0,Override values for incoming TX controls from ASIC. register #0" newline bitfld.word 0x0 15. "DATA_EN_OVRD_EN,Enable override for tx_data_en" "0,1" newline bitfld.word 0x0 14. "DATA_EN,Override value for tx_data_en" "0,1" newline bitfld.word 0x0 13. "MPLLB_SEL_OVRD_EN,Enable override for tx_mpllb_sel" "0,1" newline bitfld.word 0x0 12. "MPLLB_SEL,Override value for tx_mpllb_sel" "0,1" newline bitfld.word 0x0 11. "WIDTH_OVRD_EN,Enable override for tx_width[1:0]" "0,1" newline bitfld.word 0x0 9.--10. "WIDTH,Override value for tx_width[1:0]" "0,1,2,3" newline bitfld.word 0x0 8. "RATE_OVRD_EN,Enable override for tx_rate[2:0]" "0,1" newline bitfld.word 0x0 5.--7. "RATE,Override value for tx_rate[2:0]" "0,1,2,3,4,5,6,7" newline bitfld.word 0x0 4. "PSTATE_OVRD_EN,Enable override for tx_pstate[1:0]" "0,1" newline bitfld.word 0x0 2.--3. "PSTATE,Override value for tx_pstate[1:0]" "0,1,2,3" newline bitfld.word 0x0 1. "REQ_OVRD_EN,Enable override for tx_req" "0,1" newline bitfld.word 0x0 0. "REQ,Override value for tx_req" "0,1" group.word 0x4008++0x1 line.word 0x0 "LANE0_DIG_ASIC_TX_OVRD_IN_1,Override values for incoming TX drive controls from ASIC. register #1" newline bitfld.word 0x0 15. "MAIN_OVRD_EN,Enable override values for TX EQ main input" "0,1" newline hexmask.word.byte 0x0 9.--14. 1. "TX_MAIN_CURSOR,Override value for tx_eq_main" newline bitfld.word 0x0 8. "EN,Enable override values for inputs below controlled by this register" "0,1" newline bitfld.word 0x0 7. "VBOOST_EN,Override value for tx_vboost_en" "0,1" newline hexmask.word.byte 0x0 3.--6. 1. "IBOOST_LVL,Override value for tx_iboost_lvl" newline bitfld.word 0x0 2. "BEACON_EN,Override value for tx_beacon_en" "0,1" newline bitfld.word 0x0 1. "DISABLE,Override value for tx_disable" "0,1" newline bitfld.word 0x0 0. "NYQUIST_DATA,Override incoming data to nyquist" "0,1" group.word 0x400C++0x1 line.word 0x0 "LANE0_DIG_ASIC_TX_OVRD_IN_2,Override values for incoming TX drive controls from ASIC. register #2" newline rbitfld.word 0x0 14.--15. "RESERVED_15_14,Reserved for Future use" "0,1,2,3" newline bitfld.word 0x0 13. "POST_OVRD_EN,Enable override values for TX EQ post input" "0,1" newline hexmask.word.byte 0x0 7.--12. 1. "TX_POST_CURSOR,Override value for tx_eq_post" newline bitfld.word 0x0 6. "PRE_OVRD_EN,Enable override values for TX EQ pre input" "0,1" newline hexmask.word.byte 0x0 0.--5. 1. "TX_PRE_CURSOR,Override value for tx_eq_pre" group.word 0x4010++0x1 line.word 0x0 "LANE0_DIG_ASIC_TX_OVRD_IN_3,Override values for incoming TX drive controls from ASIC. register #3" newline hexmask.word.byte 0x0 8.--15. 1. "RESERVED_15_8,Reserved for Future use" newline bitfld.word 0x0 7. "LPD_OVRD_EN,Enable override for tx_lpd" "0,1" newline bitfld.word 0x0 6. "LPD,Override value for tx_lpd" "0,1" newline bitfld.word 0x0 5. "INVERT_OVRD_EN,Enable override for tx_invert" "0,1" newline bitfld.word 0x0 4. "INVERT,Override value for tx_invert" "0,1" newline bitfld.word 0x0 3. "DETECT_RX_REQ_OVRD_EN,Enable override for tx_detrx_req" "0,1" newline bitfld.word 0x0 2. "DETECT_RX_REQ,Override value for tx_detrx_req" "0,1" newline bitfld.word 0x0 1. "CLK_RDY_OVRD_EN,Enable override for tx_clk_rdy" "0,1" newline bitfld.word 0x0 0. "CLK_RDY,Override value for tx_clk_rdy" "0,1" group.word 0x4014++0x1 line.word 0x0 "LANE0_DIG_ASIC_TX_OVRD_IN_4,Override values for incoming TX drive controls from ASIC. register #4" newline hexmask.word 0x0 2.--15. 1. "RESERVED_15_2,Reserved for Future use" newline bitfld.word 0x0 1. "RESET_OVRD_EN,Enable override for tx_reset" "0,1" newline bitfld.word 0x0 0. "RESET,Override value for tx_reset" "0,1" group.word 0x4018++0x1 line.word 0x0 "LANE0_DIG_ASIC_TX_OVRD_OUT,Override values for outgoing TX controls to ASIC" newline hexmask.word 0x0 4.--15. 1. "RESERVED_15_4,Reserved for Future use" newline bitfld.word 0x0 3. "EN_DETRX_RESULT,Enable for override value for tx_detrx_result" "0,1" newline bitfld.word 0x0 2. "DETRX_RESULT,Override value for tx_detrx_result" "0,1" newline bitfld.word 0x0 1. "EN_TX_ACK,Enable for override value for tx_ack" "0,1" newline bitfld.word 0x0 0. "TX_ACK,Override value for tx_ack" "0,1" group.word 0x401C++0x1 line.word 0x0 "LANE0_DIG_ASIC_RX_OVRD_IN_0,Override values for incoming RX controls from ASIC. register #0" newline rbitfld.word 0x0 13.--15. "RESERVED_15_13,Reserved for Future use" "0,1,2,3,4,5,6,7" newline bitfld.word 0x0 12. "WIDTH_OVRD_EN,Enable override for rx_width" "0,1" newline bitfld.word 0x0 10.--11. "WIDTH,Override value for rx_width" "0,1,2,3" newline bitfld.word 0x0 9. "RATE_OVRD_EN,Enable override value for rx_rate" "0,1" newline bitfld.word 0x0 7.--8. "RATE,Override value for rx_rate" "0,1,2,3" newline bitfld.word 0x0 6. "PSTATE_OVRD_EN,Enable override value for rx_pstate" "0,1" newline bitfld.word 0x0 4.--5. "PSTATE,Override value for rx_pstate" "0,1,2,3" newline bitfld.word 0x0 3. "DATA_EN_OVRD_EN,Enable override value for rx_data_en" "0,1" newline bitfld.word 0x0 2. "DATA_EN,Override value for rx_data_en" "0,1" newline bitfld.word 0x0 1. "REQ_OVRD_EN,Enable override value for rx_req" "0,1" newline bitfld.word 0x0 0. "REQ,Override value for rx_req" "0,1" group.word 0x4020++0x1 line.word 0x0 "LANE0_DIG_ASIC_RX_OVRD_IN_1,Override values for incoming RX controls from ASIC. register #1" newline hexmask.word.byte 0x0 9.--15. 1. "RESERVED_15_9,Reserved for Future use" newline bitfld.word 0x0 8. "RX_REF_LD_VAL_6,Override value for rx_ref_ld_val[6]" "0,1" newline bitfld.word 0x0 7. "EN,Enable override values for all inputs controlled by this register" "0,1" newline bitfld.word 0x0 6. "RX_CDR_VCO_LOWFREQ,Override value for rx_cdr_vco_lowfreq" "0,1" newline hexmask.word.byte 0x0 0.--5. 1. "RX_REF_LD_VAL_5_0,Override value for rx_ref_ld_val[5:0]" group.word 0x4024++0x1 line.word 0x0 "LANE0_DIG_ASIC_RX_OVRD_IN_2,Override values for incoming RX controls from ASIC. register #2" newline rbitfld.word 0x0 14.--15. "RESERVED_15_14,Reserved for Future use" "0,1,2,3" newline bitfld.word 0x0 13. "EN,Enable override values for all inputs controlled by this register" "0,1" newline hexmask.word 0x0 0.--12. 1. "RX_VCO_LD_VAL,Override value for rx_vco_ld_val" group.word 0x4028++0x1 line.word 0x0 "LANE0_DIG_ASIC_RX_OVRD_IN_3,Override values for incoming RX controls from ASIC. register #3" newline rbitfld.word 0x0 15. "RESERVED_15_15,Reserved for Future use" "0,1" newline bitfld.word 0x0 14. "LOS_OVRD_EN,Enable override for rx_los_lfps_en and rx_los_threshold" "0,1" newline bitfld.word 0x0 13. "LOS_LPFS_EN,Override value for rx_los_lfps_en" "0,1" newline bitfld.word 0x0 10.--12. "LOS_THRSHLD,Override value for rx_los_threshold" "0,1,2,3,4,5,6,7" newline bitfld.word 0x0 9. "DISABLE_OVRD_EN,Enable override for rx_disable" "0,1" newline bitfld.word 0x0 8. "DISABLE,Override value for rx_disable" "0,1" newline bitfld.word 0x0 7. "CLK_SHIFT_OVRD_EN,Enable override for rx_clk_shift" "0,1" newline bitfld.word 0x0 6. "CLK_SHIFT,Override value for rx_clk_shift" "0,1" newline bitfld.word 0x0 5. "ALIGN_EN_OVRD_EN,Enable override for rx_align_en" "0,1" newline bitfld.word 0x0 4. "ALIGN_EN,Override value for rx_align_en" "0,1" newline bitfld.word 0x0 3. "CDR_SSC_EN_OVRD_EN,Enable override value for rx_cdr_ssc_en" "0,1" newline bitfld.word 0x0 2. "CDR_SSC_EN,Override value for rx_cdr_ssc_en" "0,1" newline bitfld.word 0x0 1. "CDR_TRACK_EN_OVRD_EN,Enable override value for rx_cdr_track_en" "0,1" newline bitfld.word 0x0 0. "CDR_TRACK_EN,Override value for rx_cdr_track_en" "0,1" group.word 0x402C++0x1 line.word 0x0 "LANE0_DIG_ASIC_RX_OVRD_IN_4,Override values for incoming RX controls from ASIC. register #4" newline hexmask.word.byte 0x0 10.--15. 1. "RESERVED_15_10,Reserved for Future use" newline bitfld.word 0x0 9. "TERM_OVRD_EN,Enable override for rx_term_acdc and rx_term_en" "0,1" newline bitfld.word 0x0 8. "TERM_ACDC,Override value for rx_term_acdc" "0,1" newline bitfld.word 0x0 7. "TERM_EN,Override value for rx_term_en" "0,1" newline bitfld.word 0x0 6. "ADPT_OVRD_EN,Enable override for rx_adpt_dfe_en and rx_adpt_afe_en" "0,1" newline bitfld.word 0x0 5. "ADAPT_DFE_EN,Override value for rx_adapt_dfe_en" "0,1" newline bitfld.word 0x0 4. "ADAPT_AFE_EN,Override value for rx_adapt_afe_en" "0,1" newline bitfld.word 0x0 3. "INVERT_OVRD_EN,Enable override for rx_invert" "0,1" newline bitfld.word 0x0 2. "INVERT,Override value for rx_invert" "0,1" newline bitfld.word 0x0 1. "LPD_OVRD_EN,Enable override for rx_lpd" "0,1" newline bitfld.word 0x0 0. "LPD,Override value for rx_lpd" "0,1" group.word 0x4030++0x1 line.word 0x0 "LANE0_DIG_ASIC_RX_OVRD_IN_5,Override values for incoming RX controls from ASIC. register #5" newline hexmask.word 0x0 2.--15. 1. "RESERVED_15_2,Reserved for Future use" newline bitfld.word 0x0 1. "RESET_OVRD_EN,Enable override for rx_reset" "0,1" newline bitfld.word 0x0 0. "RESET,Override value for rx_reset" "0,1" group.word 0x4034++0x1 line.word 0x0 "LANE0_DIG_ASIC_RX_OVRD_EQ_IN_0,Override values for incoming RX EQ controls from ASIC. register #0" newline hexmask.word.byte 0x0 11.--15. 1. "EQ_CTLE_BOOST,Override value for rx_eq_ctle_boost" newline hexmask.word.byte 0x0 7.--10. 1. "RESERVED," newline hexmask.word.byte 0x0 3.--6. 1. "EQ_AFE_GAIN,Override value for rx_eq_afe_gain" newline bitfld.word 0x0 0.--2. "EQ_ATT_LVL,Override value for rx_eq_att_lvl" "0,1,2,3,4,5,6,7" group.word 0x4038++0x1 line.word 0x0 "LANE0_DIG_ASIC_RX_OVRD_EQ_IN_1,Override values for incoming RX EQ controls from ASIC. register #1" newline bitfld.word 0x0 15. "EQ_OVRD_EN,Enable override value for rx_eq_* inputs" "0,1" newline hexmask.word.byte 0x0 7.--14. 1. "EQ_DFE_TAP1,Override value for rx_eq_dfe_tap1" newline hexmask.word.byte 0x0 0.--6. 1. "EQ_DFE_TAP2,Override value for rx_eq_dfe_tap2" group.word 0x403C++0x1 line.word 0x0 "LANE0_DIG_ASIC_RX_OVRD_OUT_0,Override values for outgoing RX controls to ASIC. register #0" newline hexmask.word 0x0 7.--15. 1. "RESERVED_15_7,Reserved for Future use" newline bitfld.word 0x0 6. "ADAPT_STS_OVRD_EN,Enable override for rx_adapt_sts" "0,1" newline bitfld.word 0x0 4.--5. "ADAPT_STS,Override value for rx_adapt_sts" "0,1,2,3" newline bitfld.word 0x0 3. "LOS_OUT_OVRD_EN,Enable override for rx_los_r" "0,1" newline bitfld.word 0x0 2. "LOS,Override value for rx_los" "0,1" newline bitfld.word 0x0 1. "ACK_OVRD_EN,Enable override for rx_ack" "0,1" newline bitfld.word 0x0 0. "ACK,Override value for rx_ack" "0,1" rgroup.word 0x4040++0x1 line.word 0x0 "LANE0_DIG_ASIC_LANE_ASIC_IN,Current values for incoming LANE controls from ASIC" newline hexmask.word 0x0 2.--15. 1. "RESERVED_15_2,Reserved for Future use" newline bitfld.word 0x0 1. "LANE_RX2TX_PAR_LB,Value from ASIC for lane_rx2tx_par_lb_en_r" "0,1" newline bitfld.word 0x0 0. "LANE_TX2RX_SER_LB,Value from ASIC for lane_tx2rx_ser_lb_en_r" "0,1" rgroup.word 0x4044++0x1 line.word 0x0 "LANE0_DIG_ASIC_TX_ASIC_IN_0,Current values for incoming TX controls from ASIC. register #0" newline bitfld.word 0x0 15. "DISABLE,Value from ASIC for tx_disable" "0,1" newline bitfld.word 0x0 14. "DETECT_RX_REQ,Value from ASIC for tx_detrx_req" "0,1" newline bitfld.word 0x0 13. "MPLLB_SEL,Value from ASIC for tx_mpllb_sel" "0,1" newline bitfld.word 0x0 11.--12. "WIDTH,Value from ASIC for tx_width[1:0]" "0,1,2,3" newline bitfld.word 0x0 8.--10. "RATE,Value from ASIC for tx_rate[2:0]" "0,1,2,3,4,5,6,7" newline bitfld.word 0x0 6.--7. "PSTATE,Value from ASIC for tx_pstate[1:0]" "0,1,2,3" newline bitfld.word 0x0 5. "LPD,Value from ASIC for tx_lpd" "0,1" newline bitfld.word 0x0 4. "REQ,Value from ASIC for tx_req" "0,1" newline bitfld.word 0x0 3. "DATA_EN,Value from ASIC for tx_data_en" "0,1" newline bitfld.word 0x0 2. "INVERT,Value from ASIC for tx_invert" "0,1" newline bitfld.word 0x0 1. "RESET,Value from ASIC for tx_reset" "0,1" newline bitfld.word 0x0 0. "CLK_RDY,Value from ASIC for tx_clk_rdy" "0,1" rgroup.word 0x4048++0x1 line.word 0x0 "LANE0_DIG_ASIC_TX_ASIC_IN_1,Current values for incoming TX controls from ASIC. register #1" newline hexmask.word.byte 0x0 12.--15. 1. "RESERVED_15_12,Reserved for Future use" newline hexmask.word.byte 0x0 6.--11. 1. "TX_MAIN_CURSOR,Value from ASIC for tx_eq_main" newline bitfld.word 0x0 5. "VBOOST_EN,Value from ASIC for tx_vboost_en" "0,1" newline hexmask.word.byte 0x0 1.--4. 1. "IBOOST_LVL,Value from ASIC for tx_iboost_lvl" newline bitfld.word 0x0 0. "BEACON_EN,Value from ASIC for tx_beacon_en" "0,1" rgroup.word 0x404C++0x1 line.word 0x0 "LANE0_DIG_ASIC_TX_ASIC_IN_2,Current values for incoming TX controls from ASIC. register #2" newline hexmask.word.byte 0x0 12.--15. 1. "RESERVED_15_12,Reserved for Future use" newline hexmask.word.byte 0x0 6.--11. 1. "TX_POST_CURSOR,Value from ASIC for tx_eq_post" newline hexmask.word.byte 0x0 0.--5. 1. "TX_PRE_CURSOR,Value from ASIC for tx_eq_pre" rgroup.word 0x4050++0x1 line.word 0x0 "LANE0_DIG_ASIC_TX_ASIC_OUT,Current values for outgoing TX status controls from PHY" newline hexmask.word 0x0 2.--15. 1. "RESERVED_15_2,Reserved for Future use" newline bitfld.word 0x0 1. "DETRX_RESULT,Value from PHY for tx_detrx_result" "0,1" newline bitfld.word 0x0 0. "TX_ACK,Value from PHY for tx_ack" "0,1" rgroup.word 0x4054++0x1 line.word 0x0 "LANE0_DIG_ASIC_RX_ASIC_IN_0,Current values for incoming RX controls from ASIC. register #0" newline bitfld.word 0x0 15. "RESERVED_15_15,Reserved for Future use" "0,1" newline bitfld.word 0x0 14. "CDR_TRACK_EN,Value from ASIC for rx_cdr_track_en" "0,1" newline bitfld.word 0x0 13. "ADAPT_DFE_EN,Value from ASIC for rx_adapt_dfe_en" "0,1" newline bitfld.word 0x0 12. "ADAPT_AFE_EN,Value from ASIC for rx_adapt_afe_en" "0,1" newline bitfld.word 0x0 11. "RESERVED," "0,1" newline bitfld.word 0x0 9.--10. "WIDTH,Value from ASIC for rx_width" "0,1,2,3" newline bitfld.word 0x0 7.--8. "RATE,Value from ASIC for rx_rate" "0,1,2,3" newline bitfld.word 0x0 5.--6. "PSTATE,Value from ASIC for rx_pstate" "0,1,2,3" newline bitfld.word 0x0 4. "LPD,Value from ASIC for rx_lpd" "0,1" newline bitfld.word 0x0 3. "REQ,Value from ASIC for rx_req" "0,1" newline bitfld.word 0x0 2. "DATA_EN,Value from ASIC for rx_data_en" "0,1" newline bitfld.word 0x0 1. "INVERT,Value from ASIC for rx_invert" "0,1" newline bitfld.word 0x0 0. "RESET,Value from ASIC for rx_reset" "0,1" rgroup.word 0x4058++0x1 line.word 0x0 "LANE0_DIG_ASIC_RX_ASIC_IN_1,Current values for incoming RX controls from ASIC. register #1" newline hexmask.word.byte 0x0 10.--15. 1. "RESERVED_15_10,Reserved for Future use" newline bitfld.word 0x0 9. "RX_TERM_ACDC,Value from ASIC for rx_term_acdc" "0,1" newline bitfld.word 0x0 8. "RX_TERM_EN,Value from ASIC for rx_term_en" "0,1" newline bitfld.word 0x0 7. "LOS_LPFS_EN,Value from ASIC for rx_los_lfps_en" "0,1" newline bitfld.word 0x0 4.--6. "LOS_THRSHLD,Value from ASIC for rx_los_threshold" "0,1,2,3,4,5,6,7" newline bitfld.word 0x0 3. "DISABLE,Value from ASIC for rx_disable" "0,1" newline bitfld.word 0x0 2. "CLK_SHIFT,Value from ASIC for rx_clk_shift" "0,1" newline bitfld.word 0x0 1. "ALIGN_EN,Value from ASIC for rx_align_en" "0,1" newline bitfld.word 0x0 0. "CDR_SSC_EN,Value from ASIC for rx_cdr_ssc_en" "0,1" rgroup.word 0x405C++0x1 line.word 0x0 "LANE0_DIG_ASIC_RX_EQ_ASIC_IN_0,Current values for incoming RX EQ controls from ASIC. register #0" newline hexmask.word.byte 0x0 11.--15. 1. "EQ_CTLE_BOOST,Value from ASIC for rx_eq_ctle_boost" newline hexmask.word.byte 0x0 7.--10. 1. "RESERVED," newline hexmask.word.byte 0x0 3.--6. 1. "EQ_AFE_GAIN,Value from ASIC for rx_eq_afe_gain" newline bitfld.word 0x0 0.--2. "EQ_ATT_LVL,Value from ASIC for rx_eq_att_lvl" "0,1,2,3,4,5,6,7" rgroup.word 0x4060++0x1 line.word 0x0 "LANE0_DIG_ASIC_RX_EQ_ASIC_IN_1,Current values for incoming RX EQ controls from ASIC. register #1" newline bitfld.word 0x0 15. "RESERVED_15_15,Reserved for Future use" "0,1" newline hexmask.word.byte 0x0 7.--14. 1. "EQ_DFE_TAP1,Value from ASIC for rx_eq_dfe_tap1" newline hexmask.word.byte 0x0 0.--6. 1. "EQ_DFE_TAP2,Value from ASIC for rx_eq_dfe_tap2" rgroup.word 0x4064++0x1 line.word 0x0 "LANE0_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0,Current values for incoming RX CDR VCO controls from ASIC. register #0" newline hexmask.word.byte 0x0 8.--15. 1. "RESERVED_15_8,Reserved for Future use" newline hexmask.word.byte 0x0 1.--7. 1. "RX_REF_LD_VAL,Value from ASIC for rx_ref_ld_val" newline bitfld.word 0x0 0. "RX_CDR_VCO_LOWFREQ,Value from ASIC for rx_cdr_vco_lowfreq" "0,1" rgroup.word 0x4068++0x1 line.word 0x0 "LANE0_DIG_ASIC_RX_CDR_VCO_ASIC_IN_1,Current values for incoming RX CDR VCO controls from ASIC. register #1" newline bitfld.word 0x0 13.--15. "RESERVED_15_13,Reserved for Future use" "0,1,2,3,4,5,6,7" newline hexmask.word 0x0 0.--12. 1. "RX_VCO_LD_VAL,Value from ASIC for rx_vco_ld_val" rgroup.word 0x406C++0x1 line.word 0x0 "LANE0_DIG_ASIC_RX_ASIC_OUT_0,Current values for outgoing RX status controls from PHY. register #0" newline hexmask.word 0x0 5.--15. 1. "RESERVED_15_5,Reserved for Future use" newline bitfld.word 0x0 3.--4. "ADAPT_STS,Value from PHY for rx_adapt_sts" "0,1,2,3" newline bitfld.word 0x0 2. "VALID,Value from PHY for rx_valid" "0,1" newline bitfld.word 0x0 1. "LOS,Value from PHY for rx_los" "0,1" newline bitfld.word 0x0 0. "ACK,Value from PHY for rx_ack" "0,1" repeat 2. (list 0x0 0x1 )(list 0x0 0x8 ) group.word ($2+0x4080)++0x1 line.word 0x0 "LANE0_DIG_TX_PWRCTL_TX_PSTATE_P$1,TX Power State Control Register for P0" newline hexmask.word.byte 0x0 9.--15. 1. "RESERVED_15_9,Reserved for Future use" newline bitfld.word 0x0 8. "TX_P0_ALLOW_RXDET,If asserted then rxdet request is allowed in P0" "0,1" newline bitfld.word 0x0 7. "TX_P0_DATA_EN,This is ANDed with top-level tx_data_en asic input" "0,1" newline bitfld.word 0x0 6. "TX_P0_DIG_CLK_EN,Enable/Disable TX digital clocks in P0" "0,1" newline bitfld.word 0x0 5. "TX_P0_ANA_SERIAL_EN,Value of TX ana serial_en in P0" "0,1" newline bitfld.word 0x0 4. "TX_P0_ANA_RESET,Value of TX ana reset in P0" "0,1" newline bitfld.word 0x0 3. "TX_P0_ANA_WORD_CLK_EN,Value of TX ana word_clk_en in P0" "0,1" newline bitfld.word 0x0 2. "TX_P0_ANA_CLK_EN,Value of TX ana clk_en in P0" "0,1" newline bitfld.word 0x0 1. "TX_P0_ANA_VCM_HOLD,Value of TX ana vcm_hold in P0" "0,1" newline bitfld.word 0x0 0. "TX_P0_ANA_REFGEN_EN,Value of TX ana refgen_en in P0" "0,1" repeat.end group.word 0x4084++0x1 line.word 0x0 "LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S,TX Power State Control Register for P0S" newline hexmask.word.byte 0x0 9.--15. 1. "RESERVED_15_9,Reserved for Future use" newline bitfld.word 0x0 8. "TX_P0S_ALLOW_RXDET,If asserted then rxdet request is allowed in P0S" "0,1" newline bitfld.word 0x0 7. "TX_P0S_DATA_EN,This is ANDed with top-level tx_data_en asic input" "0,1" newline bitfld.word 0x0 6. "TX_P0S_DIG_CLK_EN,Enable/Disable TX digital clocks in P0S" "0,1" newline bitfld.word 0x0 5. "TX_P0S_ANA_SERIAL_EN,Value of TX ana serial_en in P0S" "0,1" newline bitfld.word 0x0 4. "TX_P0S_ANA_RESET,Value of TX ana reset in P0S" "0,1" newline bitfld.word 0x0 3. "TX_P0S_ANA_WORD_CLK_EN,Value of TX ana word_clk_en in P0S" "0,1" newline bitfld.word 0x0 2. "TX_P0S_ANA_CLK_EN,Value of TX ana clk_en in P0S" "0,1" newline bitfld.word 0x0 1. "TX_P0S_ANA_VCM_HOLD,Value of TX ana vcm_hold in P0S" "0,1" newline bitfld.word 0x0 0. "TX_P0S_ANA_REFGEN_EN,Value of TX ana refgen_en in P0S" "0,1" group.word 0x408C++0x1 line.word 0x0 "LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2,TX Power State Control Register for P2" newline hexmask.word.byte 0x0 10.--15. 1. "RESERVED_15_10,Reserved for Future use" newline bitfld.word 0x0 9. "TX_P2_ALLOW_VBOOST,If asserted then vboost is allowed in P2" "0,1" newline bitfld.word 0x0 8. "TX_P2_ALLOW_RXDET,If asserted then rxdet request is allowed" "0,1" newline bitfld.word 0x0 7. "TX_P2_DATA_EN,This is ANDed with top-level tx_data_en asic input" "0,1" newline bitfld.word 0x0 6. "TX_P2_DIG_CLK_EN,Enable/Disable TX digital clocks in P2" "0,1" newline bitfld.word 0x0 5. "TX_P2_ANA_SERIAL_EN,Value of TX ana serial_en in P2" "0,1" newline bitfld.word 0x0 4. "TX_P2_ANA_RESET,Value of TX ana reset in P2" "0,1" newline bitfld.word 0x0 3. "TX_P2_ANA_WORD_CLK_EN,Value of TX ana word_clk_en in P2" "0,1" newline bitfld.word 0x0 2. "TX_P2_ANA_CLK_EN,Value of TX ana clk_en in P2" "0,1" newline bitfld.word 0x0 1. "TX_P2_ANA_VCM_HOLD,Value of TX ana vcm_hold in P2" "0,1" newline bitfld.word 0x0 0. "TX_P2_ANA_REFGEN_EN,Value of TX ana refgen_en in P2" "0,1" group.word 0x4090++0x1 line.word 0x0 "LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_0,TX Power UP Time Register #0" newline hexmask.word.byte 0x0 8.--15. 1. "TX_CLK_EN,Power up time (in ref_range cycles) for TX ana clock enable (spec: >=1us)" newline hexmask.word.byte 0x0 0.--7. 1. "TX_REFGEN_EN_TIME,Power up time (in ref_range cycles) for TX ana refgen enable (spec: >=500ns)" group.word 0x4094++0x1 line.word 0x0 "LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_1,TX Power UP Time Register #1" newline bitfld.word 0x0 15. "SKIP_TX_VCM_HOLD_WAIT,Skip wait for TX common mode hold power up" "0,1" newline hexmask.word 0x0 0.--14. 1. "TX_VCM_HOLD_TIME_14_0,Power up time (in ref_range cycles) for TX common mode (spec: >=800us) (bits 14:0)" group.word 0x4098++0x1 line.word 0x0 "LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_2,TX Power UP Time Register #2" newline bitfld.word 0x0 13.--15. "DTB_SEL,Selects data to drive on DTB 0 - disabled 1 - tx_ack and tx_pwrsm_state[0] 2 - tx_ana_rxdetp_result_i tx_ana_rxdetm_result_i 3 - tx_ana_reset_i tx_ana_clk_en_i 4 - analog/asic clocks 5 - asic early signal / clock aligner shift 6 - tx_clk_state.." "disabled,tx_ack and tx_pwrsm_state[0],tx_ana_rxdetp_result_i,tx_ana_reset_i,analog/asic clocks,asic early signal / clock aligner shift,tx_clk_state counter / lbert strobe,ref_dig_rst/tx_dig_rst" newline hexmask.word 0x0 0.--12. 1. "TX_VBOOST_DIS_TIME_12_0,TX vboost disable time (in ref_range cycles) (spec: >=200us) (bits 12:0)" group.word 0x409C++0x1 line.word 0x0 "LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_3,TX Power UP Time Register #3" newline hexmask.word 0x0 4.--15. 1. "RESERVED_15_4,Reserved for Future use" newline bitfld.word 0x0 3. "TX_VBOOST_DIS_TIME_13,TX vboost disable time (in ref_range cycles) (spec: >=200us) (bit 13)" "0,1" newline bitfld.word 0x0 0.--2. "TX_VCM_HOLD_TIME_17_15,Power up time (in ref_range cycles) for TX common mode (spec: >=800us) (bits 17:15)" "0,1,2,3,4,5,6,7" group.word 0x40A0++0x1 line.word 0x0 "LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_4,TX Power UP Time Register #4" newline rbitfld.word 0x0 15. "RESERVED_15_15,Reserved for Future use" "0,1" newline hexmask.word 0x0 0.--14. 1. "TX_VCM_HOLD_GS_TIME,TX common mode gear-shift time (in ref range cycles) (spec: >=400us)" group.word 0x40A4++0x1 line.word 0x0 "LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_5,TX Power UP Time Register #5" newline rbitfld.word 0x0 15. "RESERVED_15_15,Reserved for Future use" "0,1" newline bitfld.word 0x0 13.--14. "TX_SERIAL_EN_TIME,Power up time (in ref_range cycles) for TX ana serial enable (spec: >=50ns)" "0,1,2,3" newline bitfld.word 0x0 11.--12. "TX_RESET_TIME,TX Reset deassertion time (in ref_range cycles) (spec: >=50ns)" "0,1,2,3" newline bitfld.word 0x0 10. "FAST_TX_RXDET,Enable fast TX RX-detection (simulation only)" "0,1" newline hexmask.word 0x0 0.--9. 1. "TX_RXDET_TIME,RX Detect up time (in ref_range cycles) starting from asserting rxdet_en (spec: from 3.55us to 25.9us)" group.word 0x40A8++0x1 line.word 0x0 "LANE0_DIG_TX_LBERT_CTL,Pattern Generator controls" newline rbitfld.word 0x0 15. "RESERVED_15_15,Reserved for Future use" "0,1" newline hexmask.word 0x0 5.--14. 1. "PAT0,Pattern for modes 3-5" newline bitfld.word 0x0 4. "TRIGGER_ERR,Insert a single error into a lsb Any write of a 1 to this bit will insert an error" "0,1" newline hexmask.word.byte 0x0 0.--3. 1. "MODE,Pattern to generate When changing modes you must change to disabled first 0 - Disabled 1 - lfsr31: X^31 + X^28 + 1 2 - lfsr23: X^23 + X^18 + 1 3 - lfsr23: x^23 + x^21 + x^16 + x^8 + x^5 + x^2 + 1 4 - lfsr16: x^16 + x^5 + x^4 + x^3 + 1 5 - lfsr15:.." group.word 0x40AC++0x1 line.word 0x0 "LANE0_DIG_TX_CLK_ALIGN_TX_CTL_0,TX Clock Alignment Control Register #0" newline hexmask.word.byte 0x0 9.--15. 1. "RESERVED_15_9,Reserved for Future use" newline bitfld.word 0x0 8. "TX_FIFO_BYPASS,By-pass TX datapath FIFO" "0,1" newline hexmask.word.byte 0x0 4.--7. 1. "TX_NUM_2UI_SHIFTS_20B_MODE," newline hexmask.word.byte 0x0 0.--3. 1. "TX_NUM_2UI_SHIFTS_16B_MODE," repeat 3. (list 0x0 0x1 0x2 )(list 0x0 0x8 0xC ) group.word ($2+0x4100)++0x1 line.word 0x0 "LANE0_DIG_RX_PWRCTL_RX_PSTATE_P$1,RX Power State Control Register for P0" newline hexmask.word.byte 0x0 12.--15. 1. "RESERVED_15_12,Reserved for Future use" newline bitfld.word 0x0 11. "RX_P0_DIG_CLK_EN,Enable/Disable RX digital clocks in P0" "0,1" newline bitfld.word 0x0 10. "RX_P0_VCO_CONTCAL_EN,Enable/Disable continous calibration of the RX VCO in P0 If RX_P0_DIG_CLK_EN and the top-level rx_data_en are both asserted then contiuous calibration is turned off and this value is ignored" "0,1" newline bitfld.word 0x0 9. "RX_P0_VCO_CAL_RST,Enable/Disable resetting the RX VCO in P0" "0,1" newline bitfld.word 0x0 8. "RX_P0_VCO_FREQ_RST,Enable/Disable resetting the RX VCO frequency in P0" "0,1" newline bitfld.word 0x0 7. "RX_P0_ANA_CDR_EN,Value of RX ana cdr_en in P0" "0,1" newline bitfld.word 0x0 6. "RX_P0_ANA_DESER_EN,Value of RX ana deserial_en in P0" "0,1" newline bitfld.word 0x0 5. "RX_P0_ANA_CLK_DCC_EN,Value of RX ana CLK_DCC_EN in P0" "0,1" newline bitfld.word 0x0 4. "RX_P0_ANA_CLK_EN,Value of RX ana clk_en in P0" "0,1" newline bitfld.word 0x0 3. "RESERVED," "0,1" newline bitfld.word 0x0 2. "RX_P0_ANA_CLK_VREG_EN,Value of RX ana clk_vreg_en in P0" "0,1" newline bitfld.word 0x0 1. "RX_P0_ANA_AFE_EN,Value of RX ana afe_en in P0" "0,1" newline bitfld.word 0x0 0. "RX_P0_ANA_LOS_EN,Value of RX ana los_en in P0" "0,1" repeat.end group.word 0x4104++0x1 line.word 0x0 "LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0S,RX Power State Control Register for P0S" newline hexmask.word.byte 0x0 12.--15. 1. "RESERVED_15_12,Reserved for Future use" newline bitfld.word 0x0 11. "RX_P0S_DIG_CLK_EN,Enable/Disable RX digital clocks in P0S" "0,1" newline bitfld.word 0x0 10. "RX_P0S_VCO_CONTCAL_EN,Enable/Disable continous calibration of the RX VCO in P0S If RX_P0S_DIG_CLK_EN and the top-level rx_data_en are both asserted then contiuous calibration is turned off and this value is ignored" "0,1" newline bitfld.word 0x0 9. "RX_P0S_VCO_CAL_RST,Enable/Disable resetting the RX VCO in P0S" "0,1" newline bitfld.word 0x0 8. "RX_P0S_VCO_FREQ_RST,Enable/Disable resetting the RX VCO frequency in P0S" "0,1" newline bitfld.word 0x0 7. "RX_P0S_ANA_CDR_EN,Value of RX ana cdr_en in P0S" "0,1" newline bitfld.word 0x0 6. "RX_P0S_ANA_DESER_EN,Value of RX ana deserial_en in P0S" "0,1" newline bitfld.word 0x0 5. "RX_P0S_ANA_CLK_DCC_EN,Value of RX ana CLK_DCC_EN in P0S" "0,1" newline bitfld.word 0x0 4. "RX_P0S_ANA_CLK_EN,Value of RX ana clk_en in P0S" "0,1" newline bitfld.word 0x0 3. "RESERVED," "0,1" newline bitfld.word 0x0 2. "RX_P0S_ANA_CLK_VREG_EN,Value of RX ana clk_vreg_en in P0S" "0,1" newline bitfld.word 0x0 1. "RX_P0S_ANA_AFE_EN,Value of RX ana afe_en in P0S" "0,1" newline bitfld.word 0x0 0. "RX_P0S_ANA_LOS_EN,Value of RX ana los_en in P0S" "0,1" group.word 0x4110++0x1 line.word 0x0 "LANE0_DIG_RX_PWRCTL_RX_PWRUP_TIME_0,RX Power UP Time Register #0" newline hexmask.word.byte 0x0 10.--15. 1. "RESERVED_15_10,Reserved for Future use" newline bitfld.word 0x0 9. "SKIP_RX_LOS_EN_WAIT,Skip wait for RX LOS enable" "0,1" newline hexmask.word 0x0 0.--8. 1. "RX_LOS_EN_TIME,Power up time (in ref_range cycles) for RX ana los enable (spec >=10us)" group.word 0x4114++0x1 line.word 0x0 "LANE0_DIG_RX_PWRCTL_RX_PWRUP_TIME_1,RX Power UP Time Register #1" newline rbitfld.word 0x0 14.--15. "RESERVED_15_14,Reserved for Future use" "0,1,2,3" newline bitfld.word 0x0 13. "FAST_RX_VREG_EN,Enable fast RX VREG enable (simulation only)" "0,1" newline hexmask.word.byte 0x0 7.--12. 1. "RX_VREG_EN_TIME,Power up time (in ref_range cycles) for RX ana vreg enable (spec 500ns)" newline bitfld.word 0x0 6. "FAST_RX_AFE_EN,Enable fast RX AFE enable (simulation only)" "0,1" newline hexmask.word.byte 0x0 0.--5. 1. "RX_AFE_EN_TIME,Power up time (in ref_range cycles) for RX ana AFE enable (spec >=1us)" group.word 0x4118++0x1 line.word 0x0 "LANE0_DIG_RX_PWRCTL_RX_PWRUP_TIME_2,RX Power UP Time Register #2" newline hexmask.word 0x0 7.--15. 1. "RESERVED_15_7,Reserved for Future use" newline bitfld.word 0x0 6. "FAST_RX_CLK_EN,Enable fast RX clock enable (simulation only)" "0,1" newline hexmask.word.byte 0x0 0.--5. 1. "RX_CLK_EN_TIME,Power up time (in ref_range cycles) for RX ana clk (or dcc) enable (spec >1us)" group.word 0x411C++0x1 line.word 0x0 "LANE0_DIG_RX_PWRCTL_RX_PWRUP_TIME_3,RX Power UP Time Register #3" newline bitfld.word 0x0 14.--15. "RX_DESER_DIS_TIME,Power down time in (ref_range cycles) for RX ana deserial enable" "0,1,2,3" newline bitfld.word 0x0 12.--13. "RX_DESER_EN_TIME,Power up time (in ref_range cycles) for RX ana deserial enable" "0,1,2,3" newline hexmask.word.byte 0x0 8.--11. 1. "RX_CDR_EN_TIME,Power up time (in ref_range cycles) for RX ana cdr (or dfe/dfe_taps) enable (spec 0ns)" newline hexmask.word.byte 0x0 2.--7. 1. "RSVD_3_7_2,Reserved" newline bitfld.word 0x0 0.--1. "RX_RATE_TIME,Power up time (in ref_range cycles) for RX ana rate or width change" "0,1,2,3" group.word 0x4120++0x1 line.word 0x0 "LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0,RX VCO calibration controls register #0" newline hexmask.word.byte 0x0 12.--15. 1. "RESERVED_15_12,Reserved for Future use" newline bitfld.word 0x0 9.--11. "INT_GAIN_CAL_BOUNCE_CNT,Number of bounces (i.e. direction changes) on the int_gain code before indicating that the RX VCO calibration is done" "0,1,2,3,4,5,6,7" newline bitfld.word 0x0 6.--8. "INT_GAIN_CAL_CNT_SHIFT,Number of shifts to apply to ld_cnt inputs when performing int_gain code calibration" "0,1,2,3,4,5,6,7" newline bitfld.word 0x0 5. "INT_GAIN_CAL_FIXED_CNT_EN,Enable a fixed count (instead of bounce count) for int_gain code calibration" "0,1" newline hexmask.word.byte 0x0 0.--4. 1. "INT_GAIN_CAL_FIXED_CNT,Number of steps done during int_gain code calibration when INT_GAIN_CAL_FIXED_CNT_EN is enabled." group.word 0x4124++0x1 line.word 0x0 "LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1,RX VCO calibration controls register #1" newline hexmask.word.byte 0x0 9.--15. 1. "DTB_SEL,DTB select for RX VCO dtb signals 7'h01 - {chkfrq_en ref_dig_clk} 7'h02 - {rx_ana_cdr_vco_en_i rx_ana_cdr_startup_i} 7'h04 - {rx_vco_up dpll_freq_rst} 7'h08 - {rx_vco_contcal_en rx_vco_cal_rst} 7'h10 - {chkfrq_done vcoclk_too_fast} 7'h20 -.." newline hexmask.word.byte 0x0 5.--8. 1. "DPLL_CAL_UG,DPLL calibration update on int_gain code 3'h0 - 0 Else - (1/16)*2^(DPLL_CAL_UG-1) LSB/update Maximum DPLL_CAL_UG=10 i.e. 32 LSB/update" newline bitfld.word 0x0 4. "DISABLE_INT_CAL_MODE,When asserted then the DPLL frequency register is never modified by the RX VCO calibration FSM (even if DPLL_CAL_UG is non-zero). In this case the calibration will always be performed on the VCO freq_tune code. This allows.." "0,1" newline bitfld.word 0x0 3. "RX_VCO_CONTCAL_EN,Override value for the continous calibration enable from the RX PWRSM" "0,1" newline bitfld.word 0x0 2. "RX_VCO_CAL_RST,Override value for the calibration reset from the RX PWRSM" "0,1" newline bitfld.word 0x0 1. "RX_VCO_FREQ_RST,Override value for the frequency reset from the RX PWRSM" "0,1" newline bitfld.word 0x0 0. "RX_VCO_OVRD_SEL,Override the calibration controls from the RX PWRSM" "0,1" group.word 0x4128++0x1 line.word 0x0 "LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2,RX VCO calibration controls register #2" newline bitfld.word 0x0 15. "SKIP_RX_VCO_CAL,Skip RX VCO calibration altogether" "0,1" newline bitfld.word 0x0 14. "SKIP_RX_VCO_FREQ_TUNE_CAL,Skip RX VCO coarse calibration" "0,1" newline hexmask.word.byte 0x0 10.--13. 1. "FREQ_TUNE_CAL_STEPS,Number of cal steps of freq tune" newline hexmask.word 0x0 0.--9. 1. "FREQ_TUNE_START_VAL,Starting value of freq tune code" group.word 0x412C++0x1 line.word 0x0 "LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0,RX Power UP Time Register #0" newline bitfld.word 0x0 15. "FAST_RX_VCO_WAIT,Enable fast RX VCO power up (simulation only)" "0,1" newline hexmask.word.byte 0x0 11.--14. 1. "RX_VCO_CNTR_PWRUP_TIME,Power up time (in ref_range cycles) for Rx ana vco cnter (spec >200ns)" newline hexmask.word.byte 0x0 7.--10. 1. "RX_VCO_UPDATE_TIME,Settle time (in ref_range cycles) for RX ana vco update (freq_tune or int_gain) (spec >200ns)" newline hexmask.word.byte 0x0 0.--6. 1. "RX_VCO_STARTUP_TIME,Power up time (in ref_range cycles) for RX ana vco startup (spec >1us)" group.word 0x4130++0x1 line.word 0x0 "LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1,RX Power UP Time Register #1" newline hexmask.word 0x0 3.--15. 1. "RESERVED_15_3,Reserved for Future use" newline bitfld.word 0x0 0.--2. "RX_VCO_CNTR_SETTLE_TIME,RX VCO counter value settling time in (ref_dig_clk cycles) (spec: 3 ref_dig_clk cycle)" "0,1,2,3,4,5,6,7" rgroup.word 0x4134++0x1 line.word 0x0 "LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_0,RX VCO status register #0" newline bitfld.word 0x0 14.--15. "RESERVED_15_14,Reserved for Future use" "0,1,2,3" newline bitfld.word 0x0 13. "RX_ANA_CDR_VCO_EN,Current value of rx_ana_cdr_vco_en_i" "0,1" newline bitfld.word 0x0 12. "RX_ANA_CDR_STARTUP,Current value of rx_ana_cdr_startup_i" "0,1" newline bitfld.word 0x0 11. "RX_ANA_VCO_CNTR_EN,Current value of rx_ana_vco_cntr_en_i" "0,1" newline bitfld.word 0x0 10. "RX_ANA_VCO_CNTR_PD,Current value of rx_ana_vco_cntr_pd_i" "0,1" newline hexmask.word 0x0 0.--9. 1. "RX_ANA_CDR_FREQ_TUNE,Current value of rx_ana_cdr_freq_tune_i" rgroup.word 0x4138++0x1 line.word 0x0 "LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_1,RX VCO status register #1" newline hexmask.word.byte 0x0 9.--15. 1. "RESERVED_15_9,Reserved for Future use" newline bitfld.word 0x0 8. "DPLL_FREQ_RST,Indicates that the RX integral frequency is reset or not" "0,1" newline bitfld.word 0x0 7. "RX_VCO_CAL_DONE,Indicates that the RX VCO has completed calibration" "0,1" newline bitfld.word 0x0 6. "RX_VCO_CONTCAL_EN,Value of the continous calibration enable from the RX PWRSM" "0,1" newline bitfld.word 0x0 5. "RX_VCO_CAL_RST,Value of the calibration reset from the RX PWRSM" "0,1" newline bitfld.word 0x0 4. "RX_VCO_FREQ_RST,Value of the RX VCO frequency reset from the RX PWRSM" "0,1" newline hexmask.word.byte 0x0 0.--3. 1. "RX_VCO_FSM_STATE,Value of the RX VCO CAL FSM" rgroup.word 0x413C++0x1 line.word 0x0 "LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_2,RX VCO status register #2" newline bitfld.word 0x0 15. "RX_VCO_UP,Indicates that the RX VCO is ready" "0,1" newline bitfld.word 0x0 14. "RX_VCO_CORRECT,Indicates that the RX VCO clock has the correct frequency" "0,1" newline bitfld.word 0x0 13. "VCOCLK_TOO_FAST,Indicates that the RX VCO clock frequency is too fast" "0,1" newline hexmask.word 0x0 0.--12. 1. "VCO_CNTR_FINAL,Value of Rx VCO counter when refclk counter expired" group.word 0x4140++0x1 line.word 0x0 "LANE0_DIG_RX_RX_ALIGN_XAUI_COMM_MASK,XAUI_COMMA Mask" newline hexmask.word.byte 0x0 10.--15. 1. "RESERVED_15_10,Reserved for Future use" newline hexmask.word 0x0 0.--9. 1. "XAUI_COMM_MASK,XAUI_COMMA Mask. For 10-bit COMMA set the mask to 0x3FF and for 7-bit COMMA set the mask to 0x3F8" group.word 0x4144++0x1 line.word 0x0 "LANE0_DIG_RX_LBERT_CTL,Pattern Matcher controls" newline hexmask.word 0x0 5.--15. 1. "RESERVED_15_5,Reserved for Future use" newline bitfld.word 0x0 4. "SYNC,Synchronize pattern matcher LFSR with incoming data A write of a one to this bit will reset the error counter and start a synchronization of the PM. There is no need to write this back to zero to run normally." "0,1" newline hexmask.word.byte 0x0 0.--3. 1. "MODE,Pattern to match When changing modes you must change to disabled first 0 - Disabled 1 - lfsr31: X^31 + X^28 + 1 2 - lfsr23: X^23 + X^18 + 1 3 - lfsr23: x^23 + x^21 + x^16 + x^8 + x^5 + x^2 + 1 4 - lfsr16: x^16 + x^5 + x^4 + x^3 + 1 5 - lfsr15: X^15.." group.word 0x4148++0x1 line.word 0x0 "LANE0_DIG_RX_LBERT_ERR,Pattern match error counter" newline bitfld.word 0x0 15. "OV14,If active multiply COUNT by 128. If OV14=1 and COUNT=2^15-1 signals overflow of counter (2 reads needed to read value)" "0,1" newline hexmask.word 0x0 0.--14. 1. "COUNT,A read of this register or a sync of the PM resets the error count. Current error count If OV14 field is active then multiply count by 128 (2 reads needed to read value)" group.word 0x414C++0x1 line.word 0x0 "LANE0_DIG_RX_CDR_CDR_CTL_0,Control bits for receiver in recovered domain" newline hexmask.word.byte 0x0 11.--15. 1. "RESERVED_15_11,Reserved for Future use" newline hexmask.word.byte 0x0 7.--10. 1. "DTB_SEL,Select to drive various signals onto the dtb 0 - disabled 1 - rx_pr_stable rx_afe_stable from rx_ana_ctl 2 - com_good com_bad from rx_align 3 - shift_in_prog ana_odd_data from rx_align 4 - 2 msb's of XAUI align FSM state 5 - 2 lsb's of XAUI.." newline bitfld.word 0x0 6. "ALWAYS_REALIGN,Realign on any misaligned comma" "0,1" newline bitfld.word 0x0 5. "PHDET_EN_PR_MODE,Enable partial response phase detector mode" "0,1" newline bitfld.word 0x0 4. "PHDET_POL,Reverse polarity of phase error" "0,1" newline bitfld.word 0x0 2.--3. "PHDET_EDGE,Edges to use for phase detection. 10 - Use both edges 01 - Use rising edges only 11 - Use falling edges only 00 - Ignore all edges" "Ignore all edges,Use rising edges only,?,?" newline bitfld.word 0x0 0.--1. "PHDET_EN,Enable phase detector. top bit is odd slicers bottom is even" "0,1,2,3" group.word 0x4150++0x1 line.word 0x0 "LANE0_DIG_RX_CDR_CDR_CTL_1,CDR Control Register #1" newline hexmask.word.byte 0x0 10.--15. 1. "SSC_OFF_CNT1,When SSC mode is disabled the 12-bit word count in gain stage 1 is: (SSC_OFF_CNT1 * 4) in 20b mode (SSC_OFF_CNT1 * 5) in 16b mode" newline hexmask.word 0x0 0.--9. 1. "SSC_OFF_CNT0,When SSC mode is disabled the 12-bit word count in gain stage 0 is: (SSC_OFF_CNT0 * 4) in 20b mode (SSC_OFF_CNT0 * 5) in 16b mode" group.word 0x4154++0x1 line.word 0x0 "LANE0_DIG_RX_CDR_CDR_CTL_2,CDR Control Register #2" newline hexmask.word.byte 0x0 9.--15. 1. "SSC_ON_CNT1,When SSC mode is enabled the 12-bit word count in gain stage 1 is: (SSC_ON_CNT1 * 8) in 20b mode (SSC_ON_CNT1 * 10) in 16b mode" newline hexmask.word 0x0 0.--8. 1. "SSC_ON_CNT0,When SSC mode is enabled the 12-bit word count in gain stage 0 is: (SSC_ON_CNT0 * 8) in 20b mode (SSC_ON_CNT0 * 10) in 16b mode" group.word 0x4158++0x1 line.word 0x0 "LANE0_DIG_RX_CDR_CDR_CTL_3,CDR Control Register #3" newline bitfld.word 0x0 13.--15. "FRUG_OVRD_VALUE,Override value for FRUG (frequency update gain) 3'h0 - 0 3'h1 - 1/16 LSB/update 3'h2 - 1/8 LSB/update 3'h3 - 1/4 LSB/update 3'h4 - 1/2 LSB/update 3'h5 - 1 LSB/update 3'h6 - 2 LSB/update 3'h7 - 4 LSB/update" "0,1,2,3,4,5,6,7" newline bitfld.word 0x0 10.--12. "PHUG_OVRD_VALUE,Override value for PHUG (phase update gain) 3'h0 - 0 3'h1 - 1000 ppm 3'h2 - 2000 ppm 3'h3 - 3000 ppm 3'h4 - 4000 ppm 3'h5 - 5000 ppm 3'h6 - 6000 ppm 3'h7 - 7000 ppm" "0,1,2,3,4,5,6,7" newline bitfld.word 0x0 9. "OVRD_DPLL_GAIN,Override PHUG and FRUG values" "0,1" newline bitfld.word 0x0 6.--8. "SSC_OFF_FRUG0,When SSC mode is disabled the frug value in gain stage 0 is SSC_OFF_FRUG0" "0,1,2,3,4,5,6,7" newline bitfld.word 0x0 3.--5. "SSC_OFF_PHUG1,When SSC mode is disabled the phug value in gain stage 1 is SSC_OFF_PHUG1" "0,1,2,3,4,5,6,7" newline bitfld.word 0x0 0.--2. "SSC_OFF_PHUG0,When SSC mode is disabled the phug value in gain stage 0 is SSC_OFF_PHUG0" "0,1,2,3,4,5,6,7" group.word 0x415C++0x1 line.word 0x0 "LANE0_DIG_RX_CDR_CDR_CTL_4,CDR Control Register #4" newline rbitfld.word 0x0 15. "RESERVED_15_15,Reserved for Future use" "0,1" newline bitfld.word 0x0 12.--14. "SSC_ON_PHUG1,When SSC mode is enabled the phug value in gain stage 1 is SSC_ON_PHUG1" "0,1,2,3,4,5,6,7" newline bitfld.word 0x0 9.--11. "SSC_ON_PHUG0,When SSC mode is enabled the phug value in gain stage 0 is SSC_ON_PHUG0" "0,1,2,3,4,5,6,7" newline bitfld.word 0x0 6.--8. "SSC_ON_FRUG1,When SSC mode is enabled the frug value in gain stage 1 is SSC_ON_FRUG1" "0,1,2,3,4,5,6,7" newline bitfld.word 0x0 3.--5. "SSC_ON_FRUG0,When SSC mode is enabled the frug value in gain stage 0 is SSC_ON_FRUG0" "0,1,2,3,4,5,6,7" newline bitfld.word 0x0 0.--2. "SSC_OFF_FRUG1,When SSC mode is disabled the frug value in gain stage 1 is SSC_OFF_FRUG1" "0,1,2,3,4,5,6,7" rgroup.word 0x4160++0x1 line.word 0x0 "LANE0_DIG_RX_CDR_STAT,Current output values to dpll (phug. frug)" newline hexmask.word 0x0 6.--15. 1. "RESERVED_15_6,Reserved for Future use" newline bitfld.word 0x0 3.--5. "FRUG_VALUE,NOTES: Current value for dpll_frug[2:0]" "0,1,2,3,4,5,6,7" newline bitfld.word 0x0 0.--2. "PHUG_VALUE,NOTES: Current value for dpll_phug[2:0]" "0,1,2,3,4,5,6,7" group.word 0x4164++0x1 line.word 0x0 "LANE0_DIG_RX_DPLL_FREQ,Current frequency integrator value." newline rbitfld.word 0x0 14.--15. "RESERVED_15_14,Reserved for Future use" "0,1,2,3" newline hexmask.word 0x0 0.--13. 1. "VAL,Freq is 125*VAL ppm from the reference (2 reads needed to read value)" group.word 0x4168++0x1 line.word 0x0 "LANE0_DIG_RX_DPLL_FREQ_BOUND_0,Frequency Bounds for incoming data stream #0" newline hexmask.word.byte 0x0 11.--15. 1. "RESERVED_15_11,Reserved for Future use" newline hexmask.word 0x0 1.--10. 1. "UPPER_FREQ_BOUND,Upper frequency bound in terms of LSBs of the integral control code" newline bitfld.word 0x0 0. "FREQ_BOUND_EN,Enable the frequency bounds feature" "0,1" group.word 0x416C++0x1 line.word 0x0 "LANE0_DIG_RX_DPLL_FREQ_BOUND_1,Frequency Bounds for incoming data stream #1" newline hexmask.word.byte 0x0 10.--15. 1. "RESERVED_15_10,Reserved for Future use" newline hexmask.word 0x0 0.--9. 1. "LOWER_FREQ_BOUND,Lower frequency bound in terms of LSBs of the integral control code" group.word 0x4180++0x1 line.word 0x0 "LANE0_DIG_RX_ADPTCTL_ADPT_CFG_0,Adaptation Configuration Register #0" newline bitfld.word 0x0 15. "ADPT_CLK_DIV4_EN,Set the adaptation clock to be divided by 4 (default is div2)" "0,1" newline bitfld.word 0x0 14. "START_ASM1,Start adaptation state machine #1 (VGA CTLE DFE EYEH) This register-bit is self-clearing" "0,1" newline hexmask.word.byte 0x0 10.--13. 1. "N_TGG_ASM1,Number of toggle loop iterations for ASM1" newline hexmask.word 0x0 0.--9. 1. "N_TOP_ASM1,Number of top level loop iterations for ASM1" group.word 0x4184++0x1 line.word 0x0 "LANE0_DIG_RX_ADPTCTL_ADPT_CFG_1,Adaptation Configuration Register #1" newline hexmask.word.byte 0x0 12.--15. 1. "RESERVED_15_12,Reserved for Future use" newline bitfld.word 0x0 11. "CTLE_POLE_OVRD_EN,Override CTLE pole value (only valid if adaptation is run)" "0,1" newline bitfld.word 0x0 8.--10. "CTLE_POLE_OVRD_VAL,CTLE Pole override value to load at start of adaptation" "0,1,2,3,4,5,6,7" newline bitfld.word 0x0 7. "FAST_AFE_DFE_SETTLE,Enable fast AFE and DFE settling time (simulation only)" "0,1" newline hexmask.word.byte 0x0 0.--6. 1. "N_WAIT_ASM1,Number of wait cycles for Adaptation SM #1" group.word 0x4188++0x1 line.word 0x0 "LANE0_DIG_RX_ADPTCTL_ADPT_CFG_2,Adaptation Configuration Register #2" newline hexmask.word.byte 0x0 10.--15. 1. "RESERVED_15_10,Reserved for Future use" newline hexmask.word.byte 0x0 5.--9. 1. "TGG_PTTRN_1,Pattern for the second toggle loop Error slicer is moved upward by Data tap1 if this pattern is matched" newline hexmask.word.byte 0x0 0.--4. 1. "TGG_PTTRN_0,Pattern for the first toggle loop Error slicer is moved downward by Data tap1 if this pattern is matched" group.word 0x418C++0x1 line.word 0x0 "LANE0_DIG_RX_ADPTCTL_ADPT_CFG_3,Adaptation Configuration Register #3" newline bitfld.word 0x0 15. "ESL_TWICE_DSL,Assert if error slicer has twice the voltage range as the data slicer (for the same 8 bits)." "0,1" newline bitfld.word 0x0 14. "TGG_EN,Enable toggling of the error slicer" "0,1" newline bitfld.word 0x0 13. "EYEHO_EN,Enable eye height measurement using odd error slicer" "0,1" newline bitfld.word 0x0 12. "EYEHE_EN,Enable eye height measurement using even error slicer" "0,1" newline hexmask.word.byte 0x0 7.--11. 1. "DFE_EN,Enable DFE adaptation for taps 5-1" newline bitfld.word 0x0 6. "ATT_EN,Enable ATT adaptation" "0,1" newline bitfld.word 0x0 5. "VGA_EN,Enable VGA adaptation" "0,1" newline hexmask.word.byte 0x0 0.--4. 1. "CTLE_EN,Enable CTLE boost adaptation The five bits determine which correlators are used to adapt the CTLE" repeat 2. (list 0x4 0x5 )(list 0x0 0x4 ) group.word ($2+0x4190)++0x1 line.word 0x0 "LANE0_DIG_RX_ADPTCTL_ADPT_CFG_$1,Adaptation Configuration Register #4" newline hexmask.word.byte 0x0 12.--15. 1. "DFE2_TH,DFE Tap2 correlation decision threshold (2^N-1)" newline hexmask.word.byte 0x0 8.--11. 1. "DFE1_TH,DFE Tap1 correlation decision threshold (2^N-1)" newline hexmask.word.byte 0x0 4.--7. 1. "VGA_TH,VGA correlation decision threshold (2^N-1) During eye height measurement the VGA_TH is repurporsed for error slicer updates." newline hexmask.word.byte 0x0 0.--3. 1. "CTLE_TH,CTLE correlation decision threshold (2^N-1)" repeat.end group.word 0x4198++0x1 line.word 0x0 "LANE0_DIG_RX_ADPTCTL_ADPT_CFG_6,Adaptation Configuration Register #6" newline bitfld.word 0x0 13.--15. "ATT_LOW_TH,ATT low threshold" "0,1,2,3,4,5,6,7" newline bitfld.word 0x0 12. "VGA_SAT_CNT_STICKY,If deasserted then VGA saturation counts must be consecutive to change ATT" "0,1" newline bitfld.word 0x0 9.--11. "VGA_SAT_CNT,VGA saturation count" "0,1,2,3,4,5,6,7" newline bitfld.word 0x0 6.--8. "ATT_MU,ATT gain code update gain (2^N)" "0,1,2,3,4,5,6,7" newline bitfld.word 0x0 3.--5. "VGA_MU,VGA gain code update gain (2^N) During eye height measurement the VGA_MU is repurporsed for error slicer updates." "0,1,2,3,4,5,6,7" newline bitfld.word 0x0 0.--2. "CTLE_MU,CTLE Boost code update gain (2^N)" "0,1,2,3,4,5,6,7" group.word 0x419C++0x1 line.word 0x0 "LANE0_DIG_RX_ADPTCTL_ADPT_CFG_7,Adaptation Configuration Register #7" newline rbitfld.word 0x0 15. "RESERVED_15_15,Reserved for Future use" "0,1" newline hexmask.word.byte 0x0 10.--14. 1. "VGA_LEV_LOW,VGA level low saturation limit" newline hexmask.word.byte 0x0 5.--9. 1. "VGA_LEV_HIGH,VGA level high saturation limit" newline hexmask.word.byte 0x0 0.--4. 1. "VGA_MIN_SAT,VGA minimum saturation limit" group.word 0x41A0++0x1 line.word 0x0 "LANE0_DIG_RX_ADPTCTL_ADPT_CFG_8,Adaptation Configuration Register #8" newline rbitfld.word 0x0 15. "RESERVED_15_15,Reserved for Future use" "0,1" newline bitfld.word 0x0 12.--14. "DFE5_MU,DFE tap5 code update gain (2^N)" "0,1,2,3,4,5,6,7" newline bitfld.word 0x0 9.--11. "DFE4_MU,DFE tap4 code update gain (2^N)" "0,1,2,3,4,5,6,7" newline bitfld.word 0x0 6.--8. "DFE3_MU,DFE tap3 code update gain (2^N)" "0,1,2,3,4,5,6,7" newline bitfld.word 0x0 3.--5. "DFE2_MU,DFE tap2 code update gain (2^N)" "0,1,2,3,4,5,6,7" newline bitfld.word 0x0 0.--2. "DFE1_MU,DFE tap1 code update gain (2^N)" "0,1,2,3,4,5,6,7" group.word 0x41A4++0x1 line.word 0x0 "LANE0_DIG_RX_ADPTCTL_ADPT_CFG_9,Adaptation Configuration Register #9" newline hexmask.word.byte 0x0 8.--15. 1. "ERR_SLO_ADPT_INIT,The error odd slicer is initialized to this value at the start of a new adaptation request." newline hexmask.word.byte 0x0 0.--7. 1. "ERR_SLE_ADPT_INIT,The error even slicer is initialized to this value at the start of a new adaptation request." group.word 0x41A8++0x1 line.word 0x0 "LANE0_DIG_RX_ADPTCTL_RST_ADPT_CFG,Reset Adaptation Configuration Register" newline hexmask.word 0x0 5.--15. 1. "RESERVED_15_5,Reserved for Future use" newline bitfld.word 0x0 4. "RST_ADPT_TAP1,Reset Data Tap1 when turning off DFE adaptation (Taps 2-5 are always turned off when DFE adaptation is turned off)" "0,1" newline bitfld.word 0x0 3. "RST_ADPT_CTLE_POLE,Reset CTLE Pole when turning off AFE adaptation" "0,1" newline bitfld.word 0x0 2. "RST_ADPT_CTLE_BOOST,Reset CTLE Boost when turning off AFE adaptation" "0,1" newline bitfld.word 0x0 1. "RST_ADPT_VGA,Reset VGA when turning off AFE adaptation" "0,1" newline bitfld.word 0x0 0. "RST_ADPT_ATT,Reset ATT when turning off AFE adaptation" "0,1" rgroup.word 0x41AC++0x1 line.word 0x0 "LANE0_DIG_RX_ADPTCTL_ATT_STATUS,Value of ATT Adaptation code" newline hexmask.word.byte 0x0 9.--15. 1. "RESERVED_15_9,Reserved for Future use" newline bitfld.word 0x0 8. "ASM1_DON,Asserts when Adaptation state machine #1 is done" "0,1" newline hexmask.word.byte 0x0 0.--7. 1. "ATT_ADPT_CODE,Value of ATT adaptation code" rgroup.word 0x41B0++0x1 line.word 0x0 "LANE0_DIG_RX_ADPTCTL_VGA_STATUS,Value of VGA Adaptation code" newline hexmask.word.byte 0x0 11.--15. 1. "RESERVED_15_11,Reserved for Future use" newline bitfld.word 0x0 10. "ASM1_DONE,Asserts when Adaptation state machine #1 is done" "0,1" newline hexmask.word 0x0 0.--9. 1. "VGA_ADPT_CODE,Value of VGA adaptation code" rgroup.word 0x41B4++0x1 line.word 0x0 "LANE0_DIG_RX_ADPTCTL_CTLE_STATUS,Value of CTLE Adaptation code" newline bitfld.word 0x0 14.--15. "RESERVED_15_14,Reserved for Future use" "0,1,2,3" newline bitfld.word 0x0 13. "ASM1_DONE,Asserts when Adaptation state machine #1 is done" "0,1" newline bitfld.word 0x0 10.--12. "CTLE_POLE_ADPT_CODE,Value of CTLE Pole adaptation code" "0,1,2,3,4,5,6,7" newline hexmask.word 0x0 0.--9. 1. "CTLE_BOOST_ADPT_CODE,Value of CTLE Boost adaptation code" rgroup.word 0x41B8++0x1 line.word 0x0 "LANE0_DIG_RX_ADPTCTL_DFE_TAP1_STATUS,Value of DFE Tap1 Adaptation code" newline bitfld.word 0x0 14.--15. "RESERVED_15_14,Reserved for Future use" "0,1,2,3" newline bitfld.word 0x0 13. "ASM1_DONE,Asserts when Adaptation state machine #1 is done" "0,1" newline hexmask.word 0x0 0.--12. 1. "DFE_TAP1_ADPT_CODE,Value of DFE tap1 adaptation code" rgroup.word 0x41BC++0x1 line.word 0x0 "LANE0_DIG_RX_ADPTCTL_DFE_TAP2_STATUS,Value of DFE Tap2 Adaptation code" newline bitfld.word 0x0 13.--15. "RESERVED_15_13,Reserved for Future use" "0,1,2,3,4,5,6,7" newline bitfld.word 0x0 12. "ASM1_DONE,Asserts when Adaptation state machine #1 is done" "0,1" newline hexmask.word 0x0 0.--11. 1. "DFE_TAP2_ADPT_CODE,Value of DFE tap2 adaptation code" rgroup.word 0x41C0++0x1 line.word 0x0 "LANE0_DIG_RX_ADPTCTL_DFE_TAP3_STATUS,Value of DFE Tap3 Adaptation code" newline bitfld.word 0x0 13.--15. "RESERVED_15_13,Reserved for Future use" "0,1,2,3,4,5,6,7" newline bitfld.word 0x0 12. "ASM1_DONE,Asserts when Adaptation state machine #1 is done" "0,1" newline hexmask.word 0x0 0.--11. 1. "DFE_TAP3_ADPT_CODE,Value of DFE tap3 adaptation code" rgroup.word 0x41C4++0x1 line.word 0x0 "LANE0_DIG_RX_ADPTCTL_DFE_TAP4_STATUS,Value of DFE Tap4 Adaptation code" newline bitfld.word 0x0 13.--15. "RESERVED_15_13,Reserved for Future use" "0,1,2,3,4,5,6,7" newline bitfld.word 0x0 12. "ASM1_DONE,Asserts when Adaptation state machine #1 is done" "0,1" newline hexmask.word 0x0 0.--11. 1. "DFE_TAP4_ADPT_CODE,Value of DFE tap4 adaptation code" rgroup.word 0x41C8++0x1 line.word 0x0 "LANE0_DIG_RX_ADPTCTL_DFE_TAP5_STATUS,Value of DFE Tap5 Adaptation code" newline bitfld.word 0x0 13.--15. "RESERVED_15_13,Reserved for Future use" "0,1,2,3,4,5,6,7" newline bitfld.word 0x0 12. "ASM1_DONE,Asserts when Adaptation state machine #1 is done" "0,1" newline hexmask.word 0x0 0.--11. 1. "DFE_TAP5_ADPT_CODE,Value of DFE tap5 adaptation code" group.word 0x41CC++0x1 line.word 0x0 "LANE0_DIG_RX_ADPTCTL_DFE_DATA_EVEN_VDAC_OFST,Offset values for RX DFE Data Even vDAC" newline hexmask.word.byte 0x0 8.--15. 1. "RESERVED_15_8,Reserved for Future use" newline hexmask.word.byte 0x0 0.--7. 1. "DFE_DATA_EVEN_VDAC_OFST,Offset value for DFE Data Even vDAC" group.word 0x41D0++0x1 line.word 0x0 "LANE0_DIG_RX_ADPTCTL_DFE_DATA_ODD_VDAC_OFST,Offset values for RX DFE Data Odd vDAC" newline hexmask.word.byte 0x0 8.--15. 1. "RESERVED_15_8,Reserved for Future use" newline hexmask.word.byte 0x0 0.--7. 1. "DFE_DATA_ODD_VDAC_OFST,Offset value for DFE Data Odd vDAC" group.word 0x41D4++0x1 line.word 0x0 "LANE0_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN,Sets values for RX SLICER CTRL EVEN signals going to ANA" newline hexmask.word 0x0 4.--15. 1. "RESERVED_15_4,Reserved for Future use" newline hexmask.word.byte 0x0 0.--3. 1. "RX_ANA_SLICER_CTRL_E,Value for rx_ana_slicer_ctrl_e[3:0]" group.word 0x41D8++0x1 line.word 0x0 "LANE0_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD,Sets values for RX SLICER CTRL ODD signals going to ANA" newline hexmask.word 0x0 4.--15. 1. "RESERVED_15_4,Reserved for Future use" newline hexmask.word.byte 0x0 0.--3. 1. "RX_ANA_SLICER_CTRL_O,Value for rx_ana_slicer_ctrl_o[3:0]" group.word 0x41DC++0x1 line.word 0x0 "LANE0_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST,Offset values for RX DFE Error Even vDAC" newline hexmask.word.byte 0x0 8.--15. 1. "RESERVED_15_8,Reserved for Future use" newline hexmask.word.byte 0x0 0.--7. 1. "DFE_ERROR_EVEN_VDAC_OFST,Offset value for DFE Error Even vDAC" group.word 0x41E0++0x1 line.word 0x0 "LANE0_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST,Offset values for RX DFE Error Odd vDAC" newline hexmask.word.byte 0x0 8.--15. 1. "RESERVED_15_8,Reserved for Future use" newline hexmask.word.byte 0x0 0.--7. 1. "DFE_ERROR_ODD_VDAC_OFST,Offset value for DFE Error Odd vDAC" rgroup.word 0x41E4++0x1 line.word 0x0 "LANE0_DIG_RX_ADPTCTL_ERROR_SLICER_LEVEL,Value of Error Slicer Level" newline hexmask.word.byte 0x0 8.--15. 1. "E_SLE_LVL,Even Error Slicer Level" newline hexmask.word.byte 0x0 0.--7. 1. "E_SLO_LVL,Odd Error Slicer Level" group.word 0x41E8++0x1 line.word 0x0 "LANE0_DIG_RX_ADPTCTL_ADPT_RESET,Adaptation reset register" newline hexmask.word 0x0 1.--15. 1. "RESERVED_15_1,Reserved for Future use" newline bitfld.word 0x0 0. "RESET_ASM1,Resets adaptation state machine (ASM1) as well as the stats capture block. This is a self-clearing bit and requires re-start of ASM1." "0,1" group.word 0x4200++0x1 line.word 0x0 "LANE0_DIG_RX_STAT_LD_VAL_1,Stat load value for the sample counter #1" newline bitfld.word 0x0 15. "SC1_START,Start sample counter #1 This is a self-clearing bit" "0,1" newline hexmask.word 0x0 0.--14. 1. "SC1_LD_VAL,Sample counter #1 load value" group.word 0x4204++0x1 line.word 0x0 "LANE0_DIG_RX_STAT_DATA_MSK,Stat data mask bits [15:0]" newline hexmask.word 0x0 0.--15. 1. "DATA_MSK_15_0,Value of data_msk_r[15:0]" group.word 0x4208++0x1 line.word 0x0 "LANE0_DIG_RX_STAT_MATCH_CTL0,Stat match controls register #0" newline bitfld.word 0x0 14.--15. "SCOPE_DLY,# of clock cycle delays on scope_data_rx_clk An additional MSB is added in SCOPE_DLY_2" "0,1,2,3" newline hexmask.word.byte 0x0 10.--13. 1. "DATA_MSK_19_16,Value of data_msk_r[19:16]" newline hexmask.word.byte 0x0 5.--9. 1. "PTTRN_CR1A_4_0,Value of pattern A for 1st correlator (bits 4:0)" newline hexmask.word.byte 0x0 0.--4. 1. "PTTRN_MSK_CR1A_4_0,Value of pattern A mask for 1st correlator (bits 4:0)" group.word 0x420C++0x1 line.word 0x0 "LANE0_DIG_RX_STAT_MATCH_CTL1,Stat match controls register #1" newline hexmask.word.byte 0x0 12.--15. 1. "RESERVED_15_12,Reserved for Future use" newline bitfld.word 0x0 11. "PTTRN_CR1A_ADPT_EN,Enable ORing of adapation pattern with pattern CR1A" "0,1" newline hexmask.word.byte 0x0 6.--10. 1. "PTTRN_CR1B_4_0,Value of pattern B for 1st correlator (bits 4:0)" newline hexmask.word.byte 0x0 1.--5. 1. "PTTRN_MSK_CR1B_4_0,Value of pattern B mask for 1st correlator (bits 4:0)" newline bitfld.word 0x0 0. "PTTRN_CR1B_EN,Enable pattern B matching for 1st correlator" "0,1" group.word 0x4210++0x1 line.word 0x0 "LANE0_DIG_RX_STAT_STAT_CTL0,Stat controls register #0" newline bitfld.word 0x0 15. "SKIP_EN,Value of skip_en_r" "0,1" newline bitfld.word 0x0 14. "SC_TIMER_MODE,Sample counter operation mode 0x0 - counts number of matched samples 0x1 - counts clock cycles (i.e. a timer)" "counts number of matched samples,counts clock cycles" newline bitfld.word 0x0 13. "STAT_RXCLK_SEL,Select stat clock 0x0 - ref_range_clk 0x1 - rx_dig_clk (i.e. rx dword clk) Before changing stat_rxclk_sel_r from 1->0 the rx_dig_clk must be active (i.e. enabled)" "ref_range_clk,rx_dig_clk" newline bitfld.word 0x0 10.--12. "STAT_SRC_SEL,Select stat source input 0x0 - {20{rx_cal_result}} 0x1 - {{20{scope_data_rxclk_dly_s01}} {20{scope_data_rxclk_dly}}} 0x2 - rx_phase[39:0] 0x3 - rx_error[39:0] 0x4 - rx_data[39:0] 0x5 - rx_phdir[39:0] 0x6 - 40'hFF_FFFF_FFFF" "?,?,rx_phase[39:0],rx_error[39:0],rx_data[39:0],rx_phdir[39:0],?,?" newline hexmask.word.byte 0x0 6.--9. 1. "STAT_SHFT_SEL,Select stat source shift value 0x0 - Correlate N-1 -> N+3 (use N for offset calibration) 0x1 - Correlate N+1 -> N+5 (for taps1-5) 0x2 - Correlate N+6 -> N+10 0x3 - Correlate N+11 -> N+15 0x4 - Correlate N+16 -> N+20 0x5 - Correlate N+21 ->.." newline bitfld.word 0x0 5. "CORR_MODE_EN,Enable correlation mode" "0,1" newline bitfld.word 0x0 3.--4. "CORR_SRC_SEL,Select correlation input source 0x0 - rx_error[39:0] 0x1 - rx_phase[39:0] 0x2 - {{20{scope_data_rxclk_dly_s01}} {20{scope_data_rxclk_dly}}} 0x3 - No correlation" "rx_error[39:0],rx_phase[39:0],?,No correlation" newline bitfld.word 0x0 2. "CORR_SHFT_SEL,Select shift for phase. 0:none 1:>>1" "none,?" newline bitfld.word 0x0 1. "CORR_SHFT_SEL_VGA,Select shift for error going to VGA. 0:none 1:>>1" "none,?" newline bitfld.word 0x0 0. "RESERVED_0,Reserved bit" "0,1" group.word 0x4214++0x1 line.word 0x0 "LANE0_DIG_RX_STAT_STAT_CTL1,Stat controls register #1" newline bitfld.word 0x0 14.--15. "VLD_CTL,Gating configuration of stats collection 0x0 - ignore both cdr_valid and rx_valid 0x1 - gate stats collection with cdr_valid 0x2 - gate stats collection with rx_valid 0x3 - ignore both cdr_valid and rx_valid" "ignore both cdr_valid and rx_valid,gate stats collection with cdr_valid,gate stats collection with rx_valid,ignore both cdr_valid and rx_valid" newline bitfld.word 0x0 13. "VLD_LOSS_CLR,Clearing of stats collection upon loss of valid 0x0 - hold sample and stat counters 0x1 - clear sample and stat counters" "hold sample and stat counters,clear sample and stat counters" newline bitfld.word 0x0 11.--12. "DATA_DLY_SEL,# of clock cycle delays on rx_data[19:0] An additional MSB is added in DATA_DLY_SEL_2" "0,1,2,3" newline bitfld.word 0x0 10. "STAT_CLK_EN,Clock gate enable for stat clock" "0,1" newline bitfld.word 0x0 9. "SC_PAUSE,Pause the sample counter and stat counters" "0,1" newline bitfld.word 0x0 7.--8. "RESERVED_8_7,Reserved bits" "0,1,2,3" newline bitfld.word 0x0 6. "STAT_CNT_6_EN,Enable for stat counter 6" "0,1" newline bitfld.word 0x0 5. "STAT_CNT_5_EN,Enable for stat counter 5" "0,1" newline bitfld.word 0x0 4. "STAT_CNT_4_EN,Enable for stat counter 4" "0,1" newline bitfld.word 0x0 3. "STAT_CNT_3_EN,Enable for stat counter 3 Only counter to be enabled by default since used for offset calibration" "0,1" newline bitfld.word 0x0 2. "STAT_CNT_2_EN,Enable for stat counter 2" "0,1" newline bitfld.word 0x0 1. "STAT_CNT_1_EN,Enable for stat counter 1" "0,1" newline bitfld.word 0x0 0. "STAT_CNT_0_EN,Enable for stat counter 0" "0,1" rgroup.word 0x4218++0x1 line.word 0x0 "LANE0_DIG_RX_STAT_SMPL_CNT1,Sample Counter #1 Status" newline bitfld.word 0x0 15. "SMPL_CNT1_DONE,Status of sample counter #1" "0,1" newline hexmask.word 0x0 0.--14. 1. "SMPL_CNT1,Current value of sample counter #1" rgroup.word 0x421C++0x1 line.word 0x0 "LANE0_DIG_RX_STAT_STAT_CNT_0,Stat Counter 0 Status" newline bitfld.word 0x0 15. "SMPL_CNT1_DONE,Status of sample counter #1" "0,1" newline hexmask.word 0x0 0.--14. 1. "STAT_CNT_0,Current value of stat counter #0" rgroup.word 0x4220++0x1 line.word 0x0 "LANE0_DIG_RX_STAT_STAT_CNT_1,Stat Counter 1 Status" newline bitfld.word 0x0 15. "SMPL_CNT1_DONE,Status of sample counter #1" "0,1" newline hexmask.word 0x0 0.--14. 1. "STAT_CNT_1,Current value of stat counter #1" rgroup.word 0x4224++0x1 line.word 0x0 "LANE0_DIG_RX_STAT_STAT_CNT_2,Stat Counter 2 Status" newline bitfld.word 0x0 15. "SMPL_CNT1_DONE,Status of sample counter #1" "0,1" newline hexmask.word 0x0 0.--14. 1. "STAT_CNT_2,Current value of stat counter #2" rgroup.word 0x4228++0x1 line.word 0x0 "LANE0_DIG_RX_STAT_STAT_CNT_3,Stat Counter 3 Status" newline bitfld.word 0x0 15. "SMPL_CNT1_DONE,Status of sample counter #1" "0,1" newline hexmask.word 0x0 0.--14. 1. "STAT_CNT_3,Current value of stat counter #3" rgroup.word 0x422C++0x1 line.word 0x0 "LANE0_DIG_RX_STAT_STAT_CNT_4,Stat Counter 4 Status" newline bitfld.word 0x0 15. "SMPL_CNT1_DONE,Status of sample counter #1" "0,1" newline hexmask.word 0x0 0.--14. 1. "STAT_CNT_4,Current value of stat counter #4" rgroup.word 0x4230++0x1 line.word 0x0 "LANE0_DIG_RX_STAT_STAT_CNT_5,Stat Counter 5 Status" newline bitfld.word 0x0 15. "SMPL_CNT1_DONE,Status of sample counter #1" "0,1" newline hexmask.word 0x0 0.--14. 1. "STAT_CNT_5,Current value of stat counter #5" rgroup.word 0x4234++0x1 line.word 0x0 "LANE0_DIG_RX_STAT_STAT_CNT_6,Stat Counter 6 Status" newline bitfld.word 0x0 15. "SMPL_CNT1_DONE,Status of sample counter #1" "0,1" newline hexmask.word 0x0 0.--14. 1. "STAT_CNT_6,Current value of stat counter #6" group.word 0x4238++0x1 line.word 0x0 "LANE0_DIG_RX_STAT_CAL_COMP_CLK_CTL,Calibration Comparator Control" newline hexmask.word 0x0 6.--15. 1. "RESERVED_15_6,Reserved for Future use" newline bitfld.word 0x0 3.--5. "REF_DIV_CNT,Ref range clock count (e.g. 5'd3 = 4 ref_range cycles)" "0,1,2,3,4,5,6,7" newline bitfld.word 0x0 0.--2. "PRECHRGE_CNT,Precharge Count (e.g. 5'd1 = 2 ref_range cycles)" "0,1,2,3,4,5,6,7" repeat 4. (list 0x2 0x3 0x4 0x5 )(list 0x0 0x4 0x8 0xC ) group.word ($2+0x423C)++0x1 line.word 0x0 "LANE0_DIG_RX_STAT_MATCH_CTL$1,Stat match controls register #2" newline rbitfld.word 0x0 15. "RESERVED_15_15,Reserved for Future use" "0,1" newline hexmask.word 0x0 0.--14. 1. "PTTRN_CR1A_19_5,Value of pattern A for 1st correlator (bits 19:5)" repeat.end group.word 0x424C++0x1 line.word 0x0 "LANE0_DIG_RX_STAT_STAT_CTL2,Stat controls register #2" newline hexmask.word 0x0 2.--15. 1. "RESERVED_15_2,Reserved for Future use" newline bitfld.word 0x0 1. "SCOPE_DLY_2,Additional MSB bit for SCOPE_DLY to extend the delay range to 0->7" "0,1" newline bitfld.word 0x0 0. "DATA_DLY_SEL_2,Additional MSB bit for DATA_DLY_SEL to extend the delay range to 0->7" "0,1" group.word 0x4250++0x1 line.word 0x0 "LANE0_DIG_RX_STAT_STAT_STOP,Stat stop register" newline hexmask.word 0x0 1.--15. 1. "RESERVED_15_1,Reserved for Future use" newline bitfld.word 0x0 0. "SC1_STOP,Stop sample counters #1 and associated stat counters. This is a self-clearing bit and requires re-start of sample counter #1." "0,1" group.word 0x4280++0x1 line.word 0x0 "LANE0_DIG_ANA_TX_OVRD_OUT,Override values for TX signals going to ANA" newline bitfld.word 0x0 15. "TX_OVRD_EN,Enable override values for all outputs controlled by this register" "0,1" newline bitfld.word 0x0 14. "TX_RXDET_EN,Override value for tx_ana_rxdet_en" "0,1" newline bitfld.word 0x0 13. "TX_DIV4_EN,Override value for tx_ana_div4_en" "0,1" newline bitfld.word 0x0 12. "RESERVED," "0,1" newline bitfld.word 0x0 10.--11. "TX_ANA_DATA_RATE,Override value for tx_ana_data_rate" "0,1,2,3" newline bitfld.word 0x0 9. "TX_ANA_SERIAL_EN,Override value for tx_ana_serial_en" "0,1" newline bitfld.word 0x0 8. "TX_ANA_RESET,Override value for tx_ana_reset" "0,1" newline bitfld.word 0x0 7. "TX_ANA_MPLLB_CLK_EN,Override value for tx_ana_mpllb_clk_en" "0,1" newline bitfld.word 0x0 6. "TX_ANA_MPLLA_CLK_EN,Override value for tx_ana_mplla_clk_en" "0,1" newline bitfld.word 0x0 5. "TX_ANA_WORD_CLK_EN,Override value for tx_ana_word_clk_en" "0,1" newline bitfld.word 0x0 4. "TX_ANA_CLK_EN,Override value for tx_ana_clk_en" "0,1" newline bitfld.word 0x0 3. "TX_ANA_VCM_HOLD,Override value for tx_ana_vcm_hold" "0,1" newline bitfld.word 0x0 2. "TX_ANA_REFGEN_EN,Override value for tx_ana_refgen_en" "0,1" newline bitfld.word 0x0 1. "TX_ANA_DATA_EN,Override value for tx_ana_data_en" "0,1" newline bitfld.word 0x0 0. "TX_ANA_CLK_SHIFT,Override value for tx_ana_clk_shift" "0,1" group.word 0x4284++0x1 line.word 0x0 "LANE0_DIG_ANA_TX_TERM_CODE_OVRD_OUT,Override value for TX termination code going to ANA" newline hexmask.word.byte 0x0 12.--15. 1. "RESERVED_15_12,Reserved for Future use" newline bitfld.word 0x0 11. "TX_CLK_LB_EN,Override value for tx_ana_clk_lb_en (override enabled by TX_OVRD_EN)." "0,1" newline bitfld.word 0x0 10. "TX_TERM_OVRD_EN,Override enable for the tx_ana_term_code[9:0] signal" "0,1" newline hexmask.word 0x0 0.--9. 1. "TX_TERM_CODE,Overrides the tx_ana_term_code[9:0] signal" group.word 0x4288++0x1 line.word 0x0 "LANE0_DIG_ANA_TX_TERM_CODE_CLK_OVRD_OUT,Override value for TX termination code clocks going to ANA" newline hexmask.word 0x0 3.--15. 1. "RESERVED_15_3,Reserved for Future use" newline bitfld.word 0x0 2. "TX_TERM_CLK_SELF_CLEAR_DISABLE,Disable self-clearing for the tx_ana_term_up/dn_clk register" "0,1" newline bitfld.word 0x0 1. "TX_TERM_UP_CLK,Override for TX term UP clock This bit is self-clearing (4 cr_clks later)." "0,1" newline bitfld.word 0x0 0. "TX_TERM_DN_CLK,Override for TX term DN clock - This bit is self_clearing (4 cr_clks later)." "0,1" group.word 0x428C++0x1 line.word 0x0 "LANE0_DIG_ANA_TX_EQ_OVRD_OUT_0,Override values for TX EQ signals going to ANA register #0" newline bitfld.word 0x0 15. "TX_EQ_OVRD_EN,Override enable for tx eq signals" "0,1" newline hexmask.word 0x0 1.--14. 1. "TX_ANA_CTRL_ATTEN_13_0,Override value for tx_ana_ctrl_atten[13:0]" newline bitfld.word 0x0 0. "TX_ANA_LOAD_CLK,Override value for tx_ana_load_clk" "0,1" group.word 0x4290++0x1 line.word 0x0 "LANE0_DIG_ANA_TX_EQ_OVRD_OUT_1,Override values for TX EQ signals going to ANA register #1" newline hexmask.word 0x0 6.--15. 1. "RESERVED_15_6,Reserved for Future use" newline hexmask.word.byte 0x0 0.--5. 1. "TX_ANA_CTRL_ATTEN_19_14,Override value for tx_ana_ctrl_atten[19:14]" group.word 0x4294++0x1 line.word 0x0 "LANE0_DIG_ANA_TX_EQ_OVRD_OUT_2,Override values for TX EQ signals going to ANA register #2" newline rbitfld.word 0x0 13.--15. "RESERVED_15_13,Reserved for Future use" "0,1,2,3,4,5,6,7" newline hexmask.word.byte 0x0 7.--12. 1. "TX_ANA_CTRL_PRE,Override value for tx_ana_ctrl_pre[5:0]" newline hexmask.word.byte 0x0 0.--6. 1. "RESERVED," group.word 0x4298++0x1 line.word 0x0 "LANE0_DIG_ANA_TX_EQ_OVRD_OUT_3,Override values for TX EQ signals going to ANA register #3" newline hexmask.word.byte 0x0 8.--15. 1. "RESERVED_15_8,Reserved for Future use" newline hexmask.word.byte 0x0 0.--7. 1. "TX_ANA_CTRL_POST,Override value for tx_ana_ctrl_post[7:0]" group.word 0x429C++0x1 line.word 0x0 "LANE0_DIG_ANA_RX_CTL_OVRD_OUT,Override values for RX control signals going to ANA" newline hexmask.word.byte 0x0 9.--15. 1. "RESERVED_15_9,Reserved for Future use" newline bitfld.word 0x0 8. "RX_CTL_OVRD_EN,Enable override values for outputs [8-0] below" "0,1" newline bitfld.word 0x0 7. "RX_LBK_CLK_EN,Override value for rx_ana_loopback_clk_en" "0,1" newline bitfld.word 0x0 6. "RX_ANA_ADAPTATION_EN,Override value for rx_ana_adaptation_en" "0,1" newline bitfld.word 0x0 5. "RX_ANA_DFE_TAPS_EN,Override value for rx_ana_dfe_taps_en" "0,1" newline bitfld.word 0x0 4. "RX_ANA_DIV4_EN,Override value for rx_ana_div4_en" "0,1" newline bitfld.word 0x0 3. "RX_ANA_WORD_CLK_EN,Override value for rx_ana_word_clk_en" "0,1" newline bitfld.word 0x0 1.--2. "RX_ANA_DATA_RATE,Override value for rx_ana_data_rate" "0,1,2,3" newline bitfld.word 0x0 0. "RESERVED," "0,1" group.word 0x42A0++0x1 line.word 0x0 "LANE0_DIG_ANA_RX_PWR_OVRD_OUT,Override values for RX PWR UP/DN signals going to ANA" newline hexmask.word.byte 0x0 8.--15. 1. "RESERVED_15_8,Reserved for Future use" newline bitfld.word 0x0 7. "RX_PWR_OVRD_EN,Enable override values for all outputs controlled by this register" "0,1" newline bitfld.word 0x0 6. "RX_ANA_DESERIAL_EN,Override value for rx_ana_deserial_en" "0,1" newline bitfld.word 0x0 5. "RX_ANA_CDR_EN,Override value for rx_ana_cdr_en" "0,1" newline bitfld.word 0x0 4. "RX_ANA_CLK_EN,Override value for rx_ana_clk_en" "0,1" newline bitfld.word 0x0 3. "RX_ANA_CLK_DCC_EN,Override value for rx_ana_clk_dcc_en" "0,1" newline bitfld.word 0x0 2. "RX_ANA_CLK_VREG_EN,Override value for rx_ana_clk_vreg_en" "0,1" newline bitfld.word 0x0 1. "RX_ANA_AFE_EN,Override value for rx_ana_afe_en" "0,1" newline bitfld.word 0x0 0. "RX_ANA_LOS_EN,Override value for rx_ana_los_en" "0,1" group.word 0x42A4++0x1 line.word 0x0 "LANE0_DIG_ANA_RX_VCO_OVRD_OUT_0,Override values for RX VCO signals going to ANA #0" newline bitfld.word 0x0 15. "RX_CDR_FREQ_TUNE_OVRD_EN,Enable override value for rx_ana_cdr_freq_tune" "0,1" newline bitfld.word 0x0 14. "RX_ANA_VCO_CNTR_CLK,Override value for rx_ana_vco_cntr_clk" "0,1" newline bitfld.word 0x0 13. "RX_ANA_VCO_CNTR_EN,Override value for rx_ana_vco_cntr_en" "0,1" newline hexmask.word 0x0 3.--12. 1. "RX_ANA_CDR_FREQ_TUNE,Override value for rx_ana_cdr_freq_tune" newline bitfld.word 0x0 2. "RX_VCO_CDR_OVRD_EN,Enable override values for cdr_vco_en and cdr_startup" "0,1" newline bitfld.word 0x0 1. "RX_ANA_CDR_STARTUP,Override value for rx_ana_cdr_startup" "0,1" newline bitfld.word 0x0 0. "RX_ANA_CDR_VCO_EN,Override value for rx_ana_cdr_vco_en" "0,1" repeat 2. (list 0x1 0x2 )(list 0x0 0x4 ) group.word ($2+0x42A8)++0x1 line.word 0x0 "LANE0_DIG_ANA_RX_VCO_OVRD_OUT_$1,Override values for RX VCO signals going to ANA #1" newline hexmask.word 0x0 2.--15. 1. "RESERVED_15_2,Reserved for Future use" newline bitfld.word 0x0 1. "RX_ANA_VCO_CNTR_PD,Override value for rx_ana_vco_cntr_pd" "0,1" newline bitfld.word 0x0 0. "RX_ANA_CDR_VCO_LOWFREQ,Override value for rx_ana_cdr_vco_lowfreq" "0,1" repeat.end group.word 0x42B0++0x1 line.word 0x0 "LANE0_DIG_ANA_RX_CAL,Sets values for RX CAL signals going to ANA register" newline bitfld.word 0x0 15. "RX_ANA_CAL_COMP_EN,Value for rx_ana_cal_comp_en" "0,1" newline bitfld.word 0x0 13.--14. "RX_ANA_CAL_MODE,Value for rx_ana_cal_mode[1:0] 00 Dual differential comparison ( [vip2 - vim2] greater than [vip1 - vim1] ) 01 Differential comparison on input2 (vip2 greater than vim2) 10 Single-ended comparison negative node to negative node (vim1.." "?,?,vim2] greater than [vip1,?" newline bitfld.word 0x0 12. "RX_ANA_SLICER_CAL_EN,Value for rx_ana_slicer_cal_en" "0,1" newline bitfld.word 0x0 11. "RESERVED," "0,1" newline bitfld.word 0x0 10. "RX_ANA_CAL_LPFBYP_EN,Value for rx_ana_cal_lpfbyp_en" "0,1" newline hexmask.word.byte 0x0 5.--9. 1. "RX_ANA_CAL_MUXB_SEL,Value for rx_ana_cal_muxb_sel[4:0]" newline hexmask.word.byte 0x0 0.--4. 1. "RX_ANA_CAL_MUXA_SEL,Value for rx_ana_cal_muxa_sel[4:0]" group.word 0x42B4++0x1 line.word 0x0 "LANE0_DIG_ANA_RX_DAC_CTRL,Sets values for RX DAC CTRL value going to ANA" newline hexmask.word.byte 0x0 8.--15. 1. "RESERVED_15_8,Reserved for Future use" newline hexmask.word.byte 0x0 0.--7. 1. "RX_ANA_CAL_DAC_CTRL,Value for rx_ana_cal_dac_ctrl[7:0]" group.word 0x42B8++0x1 line.word 0x0 "LANE0_DIG_ANA_RX_DAC_CTRL_OVRD,Overrides RX DAC CTRL bus (en/val/sel) going to ANA" newline hexmask.word 0x0 1.--15. 1. "RESERVED_15_1,Reserved for Future use" newline bitfld.word 0x0 0. "RX_CAL_DAC_CTRL_OVRD,Override enable for Cal DAC control" "0,1" group.word 0x42BC++0x1 line.word 0x0 "LANE0_DIG_ANA_RX_DAC_CTRL_SEL,Sets values for RX DAC CTRL Select signal going to ANA" newline hexmask.word 0x0 5.--15. 1. "RESERVED_15_5,Reserved for Future use" newline hexmask.word.byte 0x0 0.--4. 1. "RX_ANA_CAL_DAC_CTRL_SEL,Value for rx_ana_cal_dac_ctrl_sel[4:0]" group.word 0x42C0++0x1 line.word 0x0 "LANE0_DIG_ANA_RX_AFE_ATT_VGA,Value for RX AFE ATT & VGA signals going to ANA" newline hexmask.word.byte 0x0 12.--15. 1. "RESERVED_15_12,Reserved for Future use" newline bitfld.word 0x0 11. "RX_AFE_OVRD_EN,Override enable for AFE control" "0,1" newline hexmask.word.byte 0x0 7.--10. 1. "RESERVED," newline hexmask.word.byte 0x0 3.--6. 1. "RX_ANA_AFE_GAIN,Value for rx_ana_afe_gain[3:0]" newline bitfld.word 0x0 0.--2. "RX_ANA_AFE_ATT_LVL,Value for rx_ana_afe_att_lvl[2:0]" "0,1,2,3,4,5,6,7" group.word 0x42C4++0x1 line.word 0x0 "LANE0_DIG_ANA_RX_AFE_CTLE,Values for RX AFE CTLE signals going to ANA" newline hexmask.word.byte 0x0 8.--15. 1. "RESERVED_15_8,Reserved for Future use" newline hexmask.word.byte 0x0 3.--7. 1. "RX_ANA_AFE_CTLE_BOOST,Value for rx_ana_afe_ctle_boost[4:0]" newline bitfld.word 0x0 0.--2. "RESERVED," "0,1,2,3,4,5,6,7" group.word 0x42C8++0x1 line.word 0x0 "LANE0_DIG_ANA_RX_SCOPE,Values for RX SCOPE signals going to ANA" newline rbitfld.word 0x0 14.--15. "RESERVED_15_14,Reserved for Future use" "0,1,2,3" newline bitfld.word 0x0 13. "RX_SCOPE_SELF_CLEAR_DISABLE,Disable the self-clearing for rx_ana_scope_ph_clk register" "0,1" newline bitfld.word 0x0 12. "RX_ANA_SCOPE_CLK_EN,Enable the scope clocks going to the scope slicer and the lane digital part" "0,1" newline hexmask.word.byte 0x0 4.--11. 1. "RX_ANA_SCOPE_PHASE,Sets value for rx_ana_scope_phase[7:0]" newline bitfld.word 0x0 3. "RX_ANA_SCOPE_PH_CLK,Sets value for rx_ana_scope_ph_clk - This bit is self-clearing (i.e. only asserts for one cr_clk cycle)" "0,1" newline bitfld.word 0x0 1.--2. "RX_ANA_SCOPE_SEL,Sets value for rx_ana_scope_sel 00 - AFE scope selected 01 - DFE even scope selected 10 - DFE odd scope selected 11 - DFE bypass/AFE buffer scope selected" "AFE scope selected,DFE even scope selected,?,?" newline bitfld.word 0x0 0. "RX_ANA_SCOPE_EN,Sets value for rx_ana_scope_en" "0,1" group.word 0x42CC++0x1 line.word 0x0 "LANE0_DIG_ANA_RX_SLICER_CTRL,Sets values for RX Slicer Ctrl signals going to ANA register" newline hexmask.word.byte 0x0 9.--15. 1. "RESERVED_15_9,Reserved for Future use" newline bitfld.word 0x0 8. "RX_ANA_SLICER_CTRL_OVRD_EN,Override enable for Rx ANA Slicer Ctrl" "0,1" newline hexmask.word.byte 0x0 4.--7. 1. "RX_ANA_SLICER_CTRL_O,Value for rx_ana_slicer_ctrl_o[3:0]" newline hexmask.word.byte 0x0 0.--3. 1. "RX_ANA_SLICER_CTRL_E,Value for rx_ana_slicer_ctrl_e[3:0]" group.word 0x42D0++0x1 line.word 0x0 "LANE0_DIG_ANA_RX_ANA_IQ_PHASE_ADJUST,Sets values for RX ANA IQ PHASE Adjust signal going to ANA register" newline hexmask.word 0x0 7.--15. 1. "RESERVED_15_7,Reserved for Future use" newline hexmask.word.byte 0x0 0.--6. 1. "RX_ANA_IQ_PHASE_ADJUST,Value for rx_ana_iq_phase_adjust[6:0]" group.word 0x42D4++0x1 line.word 0x0 "LANE0_DIG_ANA_RX_ANA_IQ_SENSE_EN,Sets values for RX ANA IQ SENSE signal" newline hexmask.word 0x0 1.--15. 1. "RESERVED_15_1,Reserved for Future use" newline bitfld.word 0x0 0. "RX_ANA_IQ_SENSE_EN,Value for rx_ana_iq_sense_en" "0,1" group.word 0x42D8++0x1 line.word 0x0 "LANE0_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN,DAC CTRL enable signal" newline hexmask.word 0x0 2.--15. 1. "RESERVED_15_2,Reserved for Future use" newline bitfld.word 0x0 1. "DAC_CTRL_SELF_CLEAR_DISABLE,Disable self-clearing for the rx_ana_cal_dac_ctrl_en register" "0,1" newline bitfld.word 0x0 0. "RX_ANA_CAL_DAC_CTRL_EN,Value for rx_ana_cal_dac_ctrl_en - If DAC_CTRL_SELF_CLEAR_DISABLE=0 then this bit is self-clearing (i.e. only asserts for one cr_clk cycle)" "0,1" group.word 0x42DC++0x1 line.word 0x0 "LANE0_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE,Afe update enable signal" newline hexmask.word 0x0 2.--15. 1. "RESERVED_15_2,Reserved for Future use" newline bitfld.word 0x0 1. "AFE_UPDATE_SELF_CLEAR_DISABLE,Disable self-clearing for the rx_ana_afe_update_en register" "0,1" newline bitfld.word 0x0 0. "RX_ANA_AFE_UPDATE_EN,Value for rx_ana_afe_update_en - If AFE_UPDATE_SELF_CLEAR_DISABLE=0 then this bit is self-clearing (i.e. only asserts for one cr_clk cycle)" "0,1" group.word 0x42E0++0x1 line.word 0x0 "LANE0_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK,Phase adjust clock signal" newline hexmask.word 0x0 2.--15. 1. "RESERVED_15_2,Reserved for Future use" newline bitfld.word 0x0 1. "PHASE_ADJUST_SELF_CLEAR_DISABLE,Disable self-clearing for the rx_ana_iq_phase_adjust_clk register" "0,1" newline bitfld.word 0x0 0. "RX_ANA_IQ_PHASE_ADJUST_CLK,Value for rx_ana_iq_phase_adjust_clk - If PHASE_ADJUST_SELF_CLEAR_DISABLE=0 then this bit is self-clearing (i.e. only asserts for one cr_clk cycle)" "0,1" rgroup.word 0x42E4++0x1 line.word 0x0 "LANE0_DIG_ANA_STATUS_0,Lane input status register #0" newline hexmask.word.byte 0x0 8.--15. 1. "RESERVED_15_8,Reserved for Future use" newline bitfld.word 0x0 7. "RX_ANA_SCOPE_DATA,Value from ANA for rx_ana_scope_data" "0,1" newline bitfld.word 0x0 6. "RX_ANA_CAL_RESULT,Value from ANA for rx_ana_cal_result" "0,1" newline bitfld.word 0x0 5. "RX_ANA_LOS,Value from ANA for rx_ana_los" "0,1" newline bitfld.word 0x0 4. "TX_ANA_CLK_LB_EN,Value of tx_ana_clk_lb_en" "0,1" newline bitfld.word 0x0 3. "TX_ANA_LOOPBACK_EN,Value of tx_ana_loopback_en" "0,1" newline bitfld.word 0x0 2. "TX_ANA_RXDETM_RESULT,Value from ANA for tx_ana_rxdetm_result" "0,1" newline bitfld.word 0x0 1. "TX_ANA_RXDETP_RESULT,Value from ANA for tx_ana_rxdetp_result" "0,1" newline bitfld.word 0x0 0. "TX_ANA_CLK_SHIFT_ACK,Value from ANA for tx_ana_clk_shift_ack" "0,1" rgroup.word 0x42E8++0x1 line.word 0x0 "LANE0_DIG_ANA_STATUS_1,Lane input status register #1" newline bitfld.word 0x0 13.--15. "RESERVED_15_13,Reserved for Future use" "0,1,2,3,4,5,6,7" newline hexmask.word 0x0 0.--12. 1. "RX_ANA_VCO_CNTR,Value from ANA for rx_ana_vco_cntr" group.word 0x42EC++0x1 line.word 0x0 "LANE0_DIG_ANA_RX_TERM_CODE_OVRD_OUT,Override value for RX termination code going to ANA" newline hexmask.word 0x0 7.--15. 1. "RESERVED_15_7,Reserved for Future use" newline bitfld.word 0x0 6. "RX_TERM_OVRD_EN,Override enable for the rx_ana_term_code[5:0] signal" "0,1" newline hexmask.word.byte 0x0 0.--5. 1. "RX_TERM_CODE,Overrides the rx_ana_term_code[5:0] signal" group.word 0x42F0++0x1 line.word 0x0 "LANE0_DIG_ANA_RX_TERM_CODE_CLK_OVRD_OUT,Override value for RX termination code clock going to ANA" newline hexmask.word 0x0 2.--15. 1. "RESERVED_15_2,Reserved for Future use" newline bitfld.word 0x0 1. "RX_TERM_CLK_SELF_CLEAR_DISABLE,Disable the self-clearing of rx_ana_term_clk register" "0,1" newline bitfld.word 0x0 0. "RX_TERM_CLK,Override for TX term DN clock - This bit is self_clearing (4 cr_clks later)." "0,1" group.word 0x4300++0x1 line.word 0x0 "LANE0_ANA_TX_OVRD_MEAS,TX_OVRD_MEAS" newline hexmask.word.byte 0x0 8.--15. 1. "RESERVED_15_8,Reserved for Future use" newline bitfld.word 0x0 7. "PULL_DN_REG,Pull down TX output if asserted" "0,1" newline bitfld.word 0x0 6. "PULL_UP_REG,Pull up TX output if asserted" "0,1" newline bitfld.word 0x0 5. "VCM_HOLD_REG,Set Tx in common mode if asserted together with bit 4" "0,1" newline bitfld.word 0x0 4. "OVRD_VCM_HOLD,If asserted bit 5 take effect on control Tx common mode" "0,1" newline bitfld.word 0x0 3. "MEAS_SAMP_P,Measure clock p DCD through atb_s_p on clock psample" "0,1" newline bitfld.word 0x0 2. "MEAS_SAMP_M,Measure clock m DCD through atb_s_p on clock m sample" "0,1" newline bitfld.word 0x0 1. "CLK_SHIFT_REG,Controls clock shift if asserted with bit 0" "0,1" newline bitfld.word 0x0 0. "OVRD_CLK_SHIFT,If asserted allow analog register to control clock shift function" "0,1" group.word 0x4304++0x1 line.word 0x0 "LANE0_ANA_TX_PWR_OVRD,TX_PWR_OVRD" newline hexmask.word.byte 0x0 8.--15. 1. "RESERVED_15_8,Reserved for Future use" newline bitfld.word 0x0 7. "OVRD_EN,Enable analog register to take control TX power state if asserted" "0,1" newline bitfld.word 0x0 6. "SERIAL_EN_REG,Enable TX serializer if assered with bit 7" "0,1" newline bitfld.word 0x0 5. "CLK_EN_REG,Enable TX clock if asserted with bit 7" "0,1" newline bitfld.word 0x0 4. "DATA_EN_REG,Enable TX driver data path if asserted with bit 7" "0,1" newline bitfld.word 0x0 3. "CLK_DIV_EN_REG,Enable TX divider if asserted with bit 7 overrides !tx_reset" "0,1" newline bitfld.word 0x0 2. "REFGEN_EN_REG,Enable TX biasing if asserted with bit 7" "0,1" newline bitfld.word 0x0 1. "LOOPBACK_EN_REG,Enable TX loopback path to RX if asserted along with bit 0" "0,1" newline bitfld.word 0x0 0. "OVRD_TX_LOOPBACK,Enable Tx loopback mode over ridden by analog register if asserted" "0,1" group.word 0x4308++0x1 line.word 0x0 "LANE0_ANA_TX_ALT_BUS,TX_ALT_BUS" newline hexmask.word.byte 0x0 8.--15. 1. "RESERVED_15_8,Reserved for Future use" newline bitfld.word 0x0 7. "JTAG_DATA_REG,When bit 2 is asserted it replace jtag data" "0,1" newline bitfld.word 0x0 4.--6. "TX_ALT_RINGO,Three bit select of the ALT path test oscillators 000 no oscillators enabled 001 osc_vp_ulvt oscillator enabled 010 osc_vptx_lvt oscillator enabled 011 osc_vp_lvt oscillator enabled 100 Reserved 101 Reserved 110 Reserved 111 osc_vph_hv.." "0,1,2,3,4,5,6,7" newline bitfld.word 0x0 3. "NC3,Reserved" "0,1" newline bitfld.word 0x0 2. "OVRD_ALT_BUS,If asserted jtag data and TX data source selection are controlled by bits [1:0] and bit 7" "0,1" newline bitfld.word 0x0 0.--1. "DRV_SOURCE_REG,When bit 2 is asserted drv_source_reg[1:0] takes control of TX function overrides tx_data_source[1:0]" "0,1,2,3" repeat 2. (list 0x1 0x2 )(list 0x0 0x4 ) group.word ($2+0x430C)++0x1 line.word 0x0 "LANE0_ANA_TX_ATB$1,TX_ATB1" newline hexmask.word.byte 0x0 8.--15. 1. "RESERVED_15_8,Reserved for Future use" newline bitfld.word 0x0 7. "NC7,Reserved" "0,1" newline bitfld.word 0x0 6. "ATB_VREG1,Put TX regulator 1 output on atb_s_p when asserted" "0,1" newline bitfld.word 0x0 5. "ATB_VREG0,Put TX regulator 0 output on atb_s_p when asserted" "0,1" newline bitfld.word 0x0 4. "OVERRIDE_REGREF_0,Use atb_s_m as TX regulator 0 reference voltage when asserted" "0,1" newline bitfld.word 0x0 3. "ATB_VPTX,Put TX driver local vptx on atb_s_p when asserted" "0,1" newline bitfld.word 0x0 2. "ATB_VDCCP,Put DCC control voltage p on atb_s_p when asserted" "0,1" newline bitfld.word 0x0 1. "ATB_VDCCM,Put DCC control voltage m on atb_s_p when asserted" "0,1" newline bitfld.word 0x0 0. "ATB_GD,Put tx local gd on atb_s_p when asserted" "0,1" repeat.end group.word 0x4314++0x1 line.word 0x0 "LANE0_ANA_TX_VBOOST,TX_VBOOST" newline hexmask.word.byte 0x0 8.--15. 1. "RESERVED_15_8,Reserved for Future use" newline bitfld.word 0x0 7. "OVRD_VBOOST_EN,Enable TX boost mode to be override by bit 6" "0,1" newline bitfld.word 0x0 6. "VBOOST_EN_REG,If bit 7 is set to 1 analog register takes control of Tx vboost enable/disable" "0,1" newline bitfld.word 0x0 5. "BOOST_VPTX_MODE_N,If asserted TX boost mode becomes a direct boost mode. VdIffpp=vptx+0.05*(2.5*(1+iboost_code)*(2*tx_vboost_vref) in default TX boost mode" "0,1" newline bitfld.word 0x0 4. "ATB_VBOOST,Measure vptx/2 through atb_s_p when TX boost is enabled" "0,1" newline bitfld.word 0x0 3. "ATB_VBOOST_VREF,Measure tx boost reference voltage through atb_s_p" "0,1" newline bitfld.word 0x0 2. "OVERRIDE_VREF_BOOST_REF,If enabled atb_s_m is used to provide Tx boost reference voltage instead of bandgap voltage tx_vboost_vref" "0,1" newline bitfld.word 0x0 1. "ATB_S_ENABLE,Enables TX atb function if asserted This bit has to be set to 1 in order to make TX atb_s_p/m visible" "0,1" newline bitfld.word 0x0 0. "MEAS_ATB_VPH_HALF,Measure vph/2 on atb_s_p" "0,1" group.word 0x4318++0x1 line.word 0x0 "LANE0_ANA_TX_TERM_CODE,TX_TERM_CODE" newline hexmask.word.byte 0x0 8.--15. 1. "RESERVED_15_8,Reserved for Future use" newline hexmask.word.byte 0x0 1.--7. 1. "TERM_CODE_REG,TX leg biasing register (7 MSBs) this is Term_code_reg[9:3]" newline bitfld.word 0x0 0. "TERM_CODE_OVRD,Enable analog register to overdrive TX leg biasing" "0,1" group.word 0x431C++0x1 line.word 0x0 "LANE0_ANA_TX_TERM_CODE_CTRL,TX_TERM_CODE_CTRL" newline hexmask.word.byte 0x0 8.--15. 1. "RESERVED_15_8,Reserved for Future use" newline bitfld.word 0x0 7. "RESET_TERM_REG,Resets the tx termination code DACs" "0,1" newline bitfld.word 0x0 6. "RESET_TERM_OVRD,Enable analog register to reset termination code DACs" "0,1" newline bitfld.word 0x0 5. "UPDATE_TERM_UP_REG,Register control to update the pullup TX terminations" "0,1" newline bitfld.word 0x0 4. "UPDATE_TERM_UP_OVRD,Enables analog register control to update the pullup TX terminations" "0,1" newline bitfld.word 0x0 3. "UPDATE_TERM_DN_REG,Register control to update the pulldown TX terminations" "0,1" newline bitfld.word 0x0 2. "UPDATE_TERM_DN_OVRD,Enables analog register control to update the pulldown TX terminations" "0,1" newline bitfld.word 0x0 1. "TX_PWR_EN_REG,Register control over the power gating of blocks within the TX" "0,1" newline bitfld.word 0x0 0. "TX_PWR_EN_OVRD,Enables analog register control over the power gating of blocks within the TX" "0,1" group.word 0x4320++0x1 line.word 0x0 "LANE0_ANA_TX_IBOOST_CODE,TX_IBOOST_CODE" newline hexmask.word.byte 0x0 8.--15. 1. "RESERVED_15_8,Reserved for Future use" newline hexmask.word.byte 0x0 4.--7. 1. "IBOOST_CODE_REG,When TX boost is enabled and bit 3 is asserted these 4 bits take control of TX boost. VdIffpp=vptx+0.05*(2.5*(1+iboost_code)*(2*tx_vboost_vref-vptx/2) in default TX boost mode" newline bitfld.word 0x0 3. "IBOOST_CODE_OVRD,Enable analog register overdrive for TX boost" "0,1" newline bitfld.word 0x0 1.--2. "TERM_CODE_REG,TX leg biasing register bit 2 & 1 this is term_code_reg[2:1]" "0,1,2,3" newline bitfld.word 0x0 0. "LFPS_HIGH_PRIORITY,If asserted lfps/beacon enable has higher priority than data enable" "0,1" group.word 0x4324++0x1 line.word 0x0 "LANE0_ANA_TX_OVRD_CLK,TX_OVRD_CLK" newline hexmask.word.byte 0x0 8.--15. 1. "RESERVED_15_8,Reserved for Future use" newline bitfld.word 0x0 7. "OVRD_WORD_CLK_EN,If asserted it allows bit 6 to override tx word clock enable" "0,1" newline bitfld.word 0x0 6. "WORD_CLK_EN_REG,Tx word clock enable/disable when bit 7 is asserted" "0,1" newline bitfld.word 0x0 5. "OVRD_MPLLAB_EN,If asserted it allows bit 3 or 4 to take control of selecting MPLL clocks" "0,1" newline bitfld.word 0x0 4. "MPLLA_CLK_EN_REG,When asserted with bit 5 selects MPLLA clock as TX data output clock Only bit 3 or bit 4 or bit 1 can be asserted" "0,1" newline bitfld.word 0x0 3. "MPLLB_CLK_EN_REG,When asserted with bit 5 selects MPLLB clock as TX data output clock Only bit 3 or bit 4 or bit 1 can be asserted" "0,1" newline bitfld.word 0x0 2. "OVRD_LB_EN,If asserted it allows bit 1 takes control of RX clock loopback to TX" "0,1" newline bitfld.word 0x0 1. "CLK_LB_EN_REG,When asserted with bit 2 selects RX clock for TX data output clock" "0,1" newline bitfld.word 0x0 0. "OVERRIDE_REGREF_1,Use atb_s_m to over ride TX regulator reference voltage when asserted" "0,1" group.word 0x4328++0x1 line.word 0x0 "LANE0_ANA_TX_MISC,TX_MISC" newline hexmask.word.byte 0x0 8.--15. 1. "RESERVED_15_8,Reserved for Future use" newline bitfld.word 0x0 7. "OVERRIDE_RXDETREF,If asserted atb_s_m is used to override RX detection reference voltage" "0,1" newline bitfld.word 0x0 6. "MEAS_ATB_BIAS_VPTX,Measure TX bias local vptx through atb_s_p when asserted" "0,1" newline bitfld.word 0x0 5. "OSC_DIV4_EN,If asserted divides tx_alt oscillator output frequency by 4" "0,1" newline hexmask.word.byte 0x0 0.--4. 1. "NC4_0,Reserved" group.word 0x432C++0x1 line.word 0x0 "LANE0_ANA_RX_ATB_IQSKEW,RX_ATB_IQSKEW" newline hexmask.word.byte 0x0 8.--15. 1. "RESERVED_15_8,Reserved for Future use" newline bitfld.word 0x0 7. "MASTER_ATB_EN,If asserted enable RX ATB sensing bus atb_s_p/m visible externally.The exception is bit 5 which dont require this bit to be asserted" "0,1" newline bitfld.word 0x0 6. "MEAS_ATB_RX_SCOPE_REG,If asserted enable scope linearity characterization through atb_s_p/m" "0,1" newline bitfld.word 0x0 5. "MEAS_ATB_VP,If asserted vp is measured through atb_s_p" "0,1" newline hexmask.word.byte 0x0 0.--4. 1. "IQ_PHASE_ADJUST_REG,If ovrd_iq_phase_adjust is enabled these bits control the main PMIX" group.word 0x4330++0x1 line.word 0x0 "LANE0_ANA_RX_DCC_OVRD,RX_DCC_OVRD" newline hexmask.word.byte 0x0 8.--15. 1. "RESERVED_15_8,Reserved for Future use" newline bitfld.word 0x0 7. "DCC_EN_REG,When bit 6 is asserted this bit takes control of RX DCC enable" "0,1" newline bitfld.word 0x0 6. "OVRD_DCCANDAFE_EN,When asserted override RX DCC enable by analog register" "0,1" newline bitfld.word 0x0 5. "RX_LOOPBACK_CLK_REG,When bit 4 asserted this bit takes control of RX clock loopback enable/disable" "0,1" newline bitfld.word 0x0 4. "OVRD_RX_LOOPBACK_CLK,When asserted override rx clock loopback by analog register" "0,1" newline bitfld.word 0x0 2.--3. "MEAS_ATB_VDCC,meas_atb_vdcc[1:0] 00 Disable atb measurement 01 measure vdcc_i_p/m through atb_s_p/m 10 measure vdcc_q_p/m through atb_s_p/m 11 measure vdcc_i/q through atb_s_p/m" "0,1,2,3" newline bitfld.word 0x0 0.--1. "NC1_0,Reserved" "0,1,2,3" repeat 2. (list 0x1 0x2 )(list 0x0 0xC ) group.word ($2+0x4334)++0x1 line.word 0x0 "LANE0_ANA_RX_PWR_CTRL$1,RX_PWR_CTRL1" newline hexmask.word.byte 0x0 8.--15. 1. "RESERVED_15_8,Reserved for Future use" newline bitfld.word 0x0 7. "AFE_EN_REG,When asserted with bit 6 enables AFE" "0,1" newline bitfld.word 0x0 6. "OVRD_AFE_EN,If asserted bit 7 take control of AFE enable/disable" "0,1" newline bitfld.word 0x0 5. "LOS_EN_REG,When asserted with bit 4 enables LOS" "0,1" newline bitfld.word 0x0 4. "OVRD_LOS_EN,If asserted bit 5 take control of LOS enable/disable" "0,1" newline bitfld.word 0x0 3. "CLK_EN_REG,When asserted with bit 2 enables RX clock" "0,1" newline bitfld.word 0x0 2. "OVRD_CLK_EN,If asserted bit 3 take control of RX clock enable/disable" "0,1" newline bitfld.word 0x0 1. "ACJT_EN_REG,When asserted with bit 0 enables ACJTAG" "0,1" newline bitfld.word 0x0 0. "OVRD_ACJT_EN,If asserted bit 1 take control of ACJTAG enable/disable" "0,1" repeat.end group.word 0x4338++0x1 line.word 0x0 "LANE0_ANA_RX_ATB_REGREF,RX_ATB_REGREF" newline hexmask.word.byte 0x0 8.--15. 1. "RESERVED_15_8,Reserved for Future use" newline bitfld.word 0x0 5.--7. "MEAS_ATB_CAL_MUX,Meas_atb_cal_mux is 3 bit signal Meas_atb_cal_mux[2:0] If Meas_atb_cal_mux[2] asserted RX offset calibration comparator first stage differential outputs are measured through atb_s_p/m If Meas_atb_cal_mux[1] asserted atb_s_p/m.." "0,1,2,3,4,5,6,7" newline bitfld.word 0x0 4. "OVERRIDE_REGREF_CLK,If asserted RX clock regulator reference is overridden through atb_s_m" "0,1" newline bitfld.word 0x0 3. "OVERRIDE_REGREF_SCOPE,If asserted RX scope regulator reference is overridden through atb_s_m" "0,1" newline bitfld.word 0x0 2. "NC2,Reserved" "0,1" newline bitfld.word 0x0 0.--1. "MEAS_ATB_SAMP,meas_atb_samp[1:0] 00 Disable atb measurement 01 measure clk_i_p/m sampling node through atb_s_p/m 10 measure clk_q_p/m sampling node through atb_s_p/m 11 measure clk_i/q sampling node through atb_s_p/m" "0,1,2,3" group.word 0x433C++0x1 line.word 0x0 "LANE0_ANA_RX_CDR_AFE,RX_CDR_AFE" newline hexmask.word.byte 0x0 8.--15. 1. "RESERVED_15_8,Reserved for Future use" newline bitfld.word 0x0 6.--7. "NC7_6,Reserved" "0,1,2,3" newline bitfld.word 0x0 5. "PHDET_EVEN_REG,If asserted CDR phase detector uses even data path" "0,1" newline bitfld.word 0x0 4. "PHDET_ODD_REG,If asserted CDR phase detector uses odd data path" "0,1" newline hexmask.word.byte 0x0 0.--3. 1. "MEAS_ATB_RX,This is meas_atb_rx[9:6] bit each bit correspond to ==> meas_atb_rx[9] If asserted AFE biasing vbp is measured through atb_s_p meas_atb_rx[8] If asserted AFE biasing vbn is measured through atb_s_m meas_atb_rx[7] If asserted rx_p is.." group.word 0x4344++0x1 line.word 0x0 "LANE0_ANA_RX_MISC_OVRD,RX_MISC_OVRD" newline hexmask.word.byte 0x0 8.--15. 1. "RESERVED_15_8,Reserved for Future use" newline bitfld.word 0x0 7. "OVERRIDE_VREG_PRECHG_REG,If asserted the overvoltage compensation circuit in rx_vregs disabled" "0,1" newline bitfld.word 0x0 6. "CTLE_OFFSET_CAL_ENB,If asserted the offset calibration currents in the CTLE are disabled" "0,1" newline bitfld.word 0x0 5. "OVRD_RX_LOS_LFPS_EN,If asserted bit 4 enable/disables RX true LFPS detection" "0,1" newline bitfld.word 0x0 4. "RX_LOS_LFPS_EN_REG,If asserted with bit 5 enables true LFPS detection" "0,1" newline bitfld.word 0x0 2.--3. "NC3_2,Reserved" "0,1,2,3" newline bitfld.word 0x0 1. "WORD_CLK_EN_REG,If asserted with bit 0 enables rx word clock" "0,1" newline bitfld.word 0x0 0. "OVRD_WORD_CLK_EN,If asserted bit 1 takes control of word clock enable/disable" "0,1" group.word 0x4348++0x1 line.word 0x0 "LANE0_ANA_RX_CAL_MUXA,RX_CAL_MUXA" newline hexmask.word.byte 0x0 8.--15. 1. "RESERVED_15_8,Reserved for Future use" newline bitfld.word 0x0 7. "OVRD_CAL_MUXA_SEL,If asserted selects analog register setting to control RX calibration path A" "0,1" newline hexmask.word.byte 0x0 2.--6. 1. "CAL_MUXA_SEL_REG,Analog registers to control RX calibration path A if bit 7 is asserted this is cal_muxa_sel_reg[4:0]" newline bitfld.word 0x0 1. "MEAS_ATB_VIBIAS_VCO,If asserted measure CDR VCO bias current through atb_s_p (25uA)" "0,1" newline bitfld.word 0x0 0. "MEAS_ATB_VCO_200U,If asserted measure CDR VCO bias current through atb_s_m (200uA)" "0,1" group.word 0x434C++0x1 line.word 0x0 "LANE0_ANA_RX_ATB_MEAS1,RX_ATB_MEAS1" newline hexmask.word.byte 0x0 8.--15. 1. "RESERVED_15_8,Reserved for Future use" newline bitfld.word 0x0 7. "ATB_FRC_VLOS,If asserted force los detection reference voltage through atb_s_m" "0,1" newline hexmask.word.byte 0x0 1.--6. 1. "MEAS_ATB_RX,This is meas_atb_rx[5:0] bits where each bit correspond to meas_atb_rx[5] If asserted rx_m is driven by atb_f_m meas_atb_rx[4] If asserted rx_m is sensed through atb_s_m meas_atb_rx[3] If asserted measure RX LOS detection threshold.." newline bitfld.word 0x0 0. "NC0,Reserved" "0,1" group.word 0x4350++0x1 line.word 0x0 "LANE0_ANA_RX_ATB_MEAS2,RX_ATB_MEAS2" newline hexmask.word.byte 0x0 8.--15. 1. "RESERVED_15_8,Reserved for Future use" newline bitfld.word 0x0 7. "MEAS_GD,If asserted measure RX regulator local gd through atb_s_p" "0,1" newline bitfld.word 0x0 6. "NC6,Reserved" "0,1" newline bitfld.word 0x0 5. "MEAS_VREG_CLK,If asserted measure RX clock regulator output voltage through atb_s_p" "0,1" newline bitfld.word 0x0 4. "NC4,Reserved" "0,1" newline bitfld.word 0x0 3. "MEAS_VREG_SCOPE,If asserted measure RX scope regulator output voltage through atb_s_p" "0,1" newline bitfld.word 0x0 2. "MEAS_ATB_OVRD_CDR_EN,If asserted enables CDR regardless of the digital control" "0,1" newline bitfld.word 0x0 1. "MEAS_ATB_VCO_GD,If asserted measure CDR VCO local gd through atb_s_m" "0,1" newline bitfld.word 0x0 0. "MEAS_ATB_VCO_VOSC,If asserted measure CDR VCO oscillation bias current through atb_s_m" "0,1" group.word 0x4354++0x1 line.word 0x0 "LANE0_ANA_RX_CAL_MUXB,RX_CAL_MUXB" newline hexmask.word.byte 0x0 8.--15. 1. "RESERVED_15_8,Reserved for Future use" newline bitfld.word 0x0 7. "OVRD_CAL_MUXB_SEL,If asserted selects analog register setting to control RX calibration path B" "0,1" newline hexmask.word.byte 0x0 2.--6. 1. "CAL_MUXB_SEL_REG,Analog registers to control RX calibration path B if bit 7 is asserted this is cal_muxb_sel_reg[4:0]" newline bitfld.word 0x0 1. "OVRD_DFE_TAPS_EN,If asserted allows bit 0 to enable/disable dfe taps 1 and 2" "0,1" newline bitfld.word 0x0 0. "DFE_TAPS_EN_REG,If bit 1 is asserted controls DFE tap 1 and 2" "0,1" group.word 0x4358++0x1 line.word 0x0 "LANE0_ANA_RX_TERM,RX_TERM" newline hexmask.word.byte 0x0 8.--15. 1. "RESERVED_15_8,Reserved for Future use" newline bitfld.word 0x0 6.--7. "AFE_CM_SEL,Added to make AFE CM voltage controllable (below values are for TT vp=0.8V) 00 vcm=662mV 01 vcm=627mV (default) 10 vcm=593mV 11 vcm=558mV" "0,1,2,3" newline bitfld.word 0x0 5. "OVRD_RX_TERM_GD_EN,If asserted the ground termination enable value is controlled via registers" "0,1" newline bitfld.word 0x0 4. "RX_TERM_GD_EN_REG,If termination override is asserted controls the ground termination enable" "0,1" newline bitfld.word 0x0 3. "OVRD_IQ_PHASE_ADJUST,If asserted the iq_phase_adjust value is controlled via registers" "0,1" newline bitfld.word 0x0 2. "VCO_TEMP_COMP_EN,If asserted the RX-VCO temperature compensation circuit is enabled" "0,1" newline bitfld.word 0x0 0.--1. "CDR_VCO_STARTUP_CODE_REG,RX_VCO startup current over-ride cdr_vco_startup_code Startup override 00 cdr_freq_code_int[9:7] = cdr_freq_code[9:7] 01 when startup = 1 -> cdr_freq_code_int[9] = 1 10 when startup = 1 -> cdr_freq_code_int[8] = 1 11 when startup.." "?,cdr_freq_code_int[7] = 1,?,?" group.word 0x435C++0x1 line.word 0x0 "LANE0_ANA_RX_SLC_CTRL,RX_SLC_CTRL" newline hexmask.word.byte 0x0 8.--15. 1. "RESERVED_15_8,Reserved for Future use" newline hexmask.word.byte 0x0 4.--7. 1. "RX_SLICER_CTRL_E_REG,If ovrd_rx_slicer_ctrl_reg is asserted controls the even slicer configuration" newline hexmask.word.byte 0x0 0.--3. 1. "RX_SLICER_CTRL_O_REG,If ovrd_rx_slicer_ctrl_reg is asserted controls the odd slicer configuration" group.word 0x4360++0x1 line.word 0x0 "LANE0_ANA_RX_ATB_VREG,RX_ATB_VREG" newline hexmask.word.byte 0x0 8.--15. 1. "RESERVED_15_8,Reserved for Future use" newline bitfld.word 0x0 7. "OVRD_REGREF_IQC,If asserted main PMIX regulator reference is overridden through atb_s_m" "0,1" newline bitfld.word 0x0 6. "OVRD_REGREF_IQC_SCOPE,If asserted scope PMIX regulator reference is overridden through atb_s_m" "0,1" newline bitfld.word 0x0 5. "MEAS_ATB_VREG_DFE,If asserted measure RX DFE regulator output voltage through atb_s_p" "0,1" newline bitfld.word 0x0 4. "NC4,Reserved" "0,1" newline bitfld.word 0x0 3. "MEAS_ATB_VREG_IQC,If asserted measure RX main PMIX regulator output voltage through atb_s_p" "0,1" newline bitfld.word 0x0 2. "MEAS_ATB_VREG_IQC_SCOPE,If asserted measure RX scope PMIX regulator output voltage through atb_s_p" "0,1" newline bitfld.word 0x0 1. "OVRD_IQC_VREF_SEL,If asserted the vref on the iqc regulator is controlled via vbg_vref which can be controlled via registers" "0,1" newline bitfld.word 0x0 0. "OVRD_RX_SLICER_CTRL_REG,If asserted the slicer configuration value is controlled via registers (LANE.RX_SLC_CTRL)" "0,1" group.word 0x4400++0x1 line.word 0x0 "LANE1_DIG_ASIC_LANE_OVRD_IN,Override values for incoming LANE controls from ASIC" newline hexmask.word 0x0 3.--15. 1. "RESERVED_15_3,Reserved for Future use" newline bitfld.word 0x0 2. "EN,Enable override values for all inputs controlled by this register" "0,1" newline bitfld.word 0x0 1. "LANE_RX2TX_PAR_LB,Override value for lane_rx2tx_par_lb_en_r" "0,1" newline bitfld.word 0x0 0. "LANE_TX2RX_SER_LB,Override value for lane_tx2rx_ser_lb_en_r" "0,1" group.word 0x4404++0x1 line.word 0x0 "LANE1_DIG_ASIC_TX_OVRD_IN_0,Override values for incoming TX controls from ASIC. register #0" newline bitfld.word 0x0 15. "DATA_EN_OVRD_EN,Enable override for tx_data_en" "0,1" newline bitfld.word 0x0 14. "DATA_EN,Override value for tx_data_en" "0,1" newline bitfld.word 0x0 13. "MPLLB_SEL_OVRD_EN,Enable override for tx_mpllb_sel" "0,1" newline bitfld.word 0x0 12. "MPLLB_SEL,Override value for tx_mpllb_sel" "0,1" newline bitfld.word 0x0 11. "WIDTH_OVRD_EN,Enable override for tx_width[1:0]" "0,1" newline bitfld.word 0x0 9.--10. "WIDTH,Override value for tx_width[1:0]" "0,1,2,3" newline bitfld.word 0x0 8. "RATE_OVRD_EN,Enable override for tx_rate[2:0]" "0,1" newline bitfld.word 0x0 5.--7. "RATE,Override value for tx_rate[2:0]" "0,1,2,3,4,5,6,7" newline bitfld.word 0x0 4. "PSTATE_OVRD_EN,Enable override for tx_pstate[1:0]" "0,1" newline bitfld.word 0x0 2.--3. "PSTATE,Override value for tx_pstate[1:0]" "0,1,2,3" newline bitfld.word 0x0 1. "REQ_OVRD_EN,Enable override for tx_req" "0,1" newline bitfld.word 0x0 0. "REQ,Override value for tx_req" "0,1" group.word 0x4408++0x1 line.word 0x0 "LANE1_DIG_ASIC_TX_OVRD_IN_1,Override values for incoming TX drive controls from ASIC. register #1" newline bitfld.word 0x0 15. "MAIN_OVRD_EN,Enable override values for TX EQ main input" "0,1" newline hexmask.word.byte 0x0 9.--14. 1. "TX_MAIN_CURSOR,Override value for tx_eq_main" newline bitfld.word 0x0 8. "EN,Enable override values for inputs below controlled by this register" "0,1" newline bitfld.word 0x0 7. "VBOOST_EN,Override value for tx_vboost_en" "0,1" newline hexmask.word.byte 0x0 3.--6. 1. "IBOOST_LVL,Override value for tx_iboost_lvl" newline bitfld.word 0x0 2. "BEACON_EN,Override value for tx_beacon_en" "0,1" newline bitfld.word 0x0 1. "DISABLE,Override value for tx_disable" "0,1" newline bitfld.word 0x0 0. "NYQUIST_DATA,Override incoming data to nyquist" "0,1" group.word 0x440C++0x1 line.word 0x0 "LANE1_DIG_ASIC_TX_OVRD_IN_2,Override values for incoming TX drive controls from ASIC. register #2" newline rbitfld.word 0x0 14.--15. "RESERVED_15_14,Reserved for Future use" "0,1,2,3" newline bitfld.word 0x0 13. "POST_OVRD_EN,Enable override values for TX EQ post input" "0,1" newline hexmask.word.byte 0x0 7.--12. 1. "TX_POST_CURSOR,Override value for tx_eq_post" newline bitfld.word 0x0 6. "PRE_OVRD_EN,Enable override values for TX EQ pre input" "0,1" newline hexmask.word.byte 0x0 0.--5. 1. "TX_PRE_CURSOR,Override value for tx_eq_pre" group.word 0x4410++0x1 line.word 0x0 "LANE1_DIG_ASIC_TX_OVRD_IN_3,Override values for incoming TX drive controls from ASIC. register #3" newline hexmask.word.byte 0x0 8.--15. 1. "RESERVED_15_8,Reserved for Future use" newline bitfld.word 0x0 7. "LPD_OVRD_EN,Enable override for tx_lpd" "0,1" newline bitfld.word 0x0 6. "LPD,Override value for tx_lpd" "0,1" newline bitfld.word 0x0 5. "INVERT_OVRD_EN,Enable override for tx_invert" "0,1" newline bitfld.word 0x0 4. "INVERT,Override value for tx_invert" "0,1" newline bitfld.word 0x0 3. "DETECT_RX_REQ_OVRD_EN,Enable override for tx_detrx_req" "0,1" newline bitfld.word 0x0 2. "DETECT_RX_REQ,Override value for tx_detrx_req" "0,1" newline bitfld.word 0x0 1. "CLK_RDY_OVRD_EN,Enable override for tx_clk_rdy" "0,1" newline bitfld.word 0x0 0. "CLK_RDY,Override value for tx_clk_rdy" "0,1" group.word 0x4414++0x1 line.word 0x0 "LANE1_DIG_ASIC_TX_OVRD_IN_4,Override values for incoming TX drive controls from ASIC. register #4" newline hexmask.word 0x0 2.--15. 1. "RESERVED_15_2,Reserved for Future use" newline bitfld.word 0x0 1. "RESET_OVRD_EN,Enable override for tx_reset" "0,1" newline bitfld.word 0x0 0. "RESET,Override value for tx_reset" "0,1" group.word 0x4418++0x1 line.word 0x0 "LANE1_DIG_ASIC_TX_OVRD_OUT,Override values for outgoing TX controls to ASIC" newline hexmask.word 0x0 4.--15. 1. "RESERVED_15_4,Reserved for Future use" newline bitfld.word 0x0 3. "EN_DETRX_RESULT,Enable for override value for tx_detrx_result" "0,1" newline bitfld.word 0x0 2. "DETRX_RESULT,Override value for tx_detrx_result" "0,1" newline bitfld.word 0x0 1. "EN_TX_ACK,Enable for override value for tx_ack" "0,1" newline bitfld.word 0x0 0. "TX_ACK,Override value for tx_ack" "0,1" group.word 0x441C++0x1 line.word 0x0 "LANE1_DIG_ASIC_RX_OVRD_IN_0,Override values for incoming RX controls from ASIC. register #0" newline rbitfld.word 0x0 13.--15. "RESERVED_15_13,Reserved for Future use" "0,1,2,3,4,5,6,7" newline bitfld.word 0x0 12. "WIDTH_OVRD_EN,Enable override for rx_width" "0,1" newline bitfld.word 0x0 10.--11. "WIDTH,Override value for rx_width" "0,1,2,3" newline bitfld.word 0x0 9. "RATE_OVRD_EN,Enable override value for rx_rate" "0,1" newline bitfld.word 0x0 7.--8. "RATE,Override value for rx_rate" "0,1,2,3" newline bitfld.word 0x0 6. "PSTATE_OVRD_EN,Enable override value for rx_pstate" "0,1" newline bitfld.word 0x0 4.--5. "PSTATE,Override value for rx_pstate" "0,1,2,3" newline bitfld.word 0x0 3. "DATA_EN_OVRD_EN,Enable override value for rx_data_en" "0,1" newline bitfld.word 0x0 2. "DATA_EN,Override value for rx_data_en" "0,1" newline bitfld.word 0x0 1. "REQ_OVRD_EN,Enable override value for rx_req" "0,1" newline bitfld.word 0x0 0. "REQ,Override value for rx_req" "0,1" group.word 0x4420++0x1 line.word 0x0 "LANE1_DIG_ASIC_RX_OVRD_IN_1,Override values for incoming RX controls from ASIC. register #1" newline hexmask.word.byte 0x0 9.--15. 1. "RESERVED_15_9,Reserved for Future use" newline bitfld.word 0x0 8. "RX_REF_LD_VAL_6,Override value for rx_ref_ld_val[6]" "0,1" newline bitfld.word 0x0 7. "EN,Enable override values for all inputs controlled by this register" "0,1" newline bitfld.word 0x0 6. "RX_CDR_VCO_LOWFREQ,Override value for rx_cdr_vco_lowfreq" "0,1" newline hexmask.word.byte 0x0 0.--5. 1. "RX_REF_LD_VAL_5_0,Override value for rx_ref_ld_val[5:0]" group.word 0x4424++0x1 line.word 0x0 "LANE1_DIG_ASIC_RX_OVRD_IN_2,Override values for incoming RX controls from ASIC. register #2" newline rbitfld.word 0x0 14.--15. "RESERVED_15_14,Reserved for Future use" "0,1,2,3" newline bitfld.word 0x0 13. "EN,Enable override values for all inputs controlled by this register" "0,1" newline hexmask.word 0x0 0.--12. 1. "RX_VCO_LD_VAL,Override value for rx_vco_ld_val" group.word 0x4428++0x1 line.word 0x0 "LANE1_DIG_ASIC_RX_OVRD_IN_3,Override values for incoming RX controls from ASIC. register #3" newline rbitfld.word 0x0 15. "RESERVED_15_15,Reserved for Future use" "0,1" newline bitfld.word 0x0 14. "LOS_OVRD_EN,Enable override for rx_los_lfps_en and rx_los_threshold" "0,1" newline bitfld.word 0x0 13. "LOS_LPFS_EN,Override value for rx_los_lfps_en" "0,1" newline bitfld.word 0x0 10.--12. "LOS_THRSHLD,Override value for rx_los_threshold" "0,1,2,3,4,5,6,7" newline bitfld.word 0x0 9. "DISABLE_OVRD_EN,Enable override for rx_disable" "0,1" newline bitfld.word 0x0 8. "DISABLE,Override value for rx_disable" "0,1" newline bitfld.word 0x0 7. "CLK_SHIFT_OVRD_EN,Enable override for rx_clk_shift" "0,1" newline bitfld.word 0x0 6. "CLK_SHIFT,Override value for rx_clk_shift" "0,1" newline bitfld.word 0x0 5. "ALIGN_EN_OVRD_EN,Enable override for rx_align_en" "0,1" newline bitfld.word 0x0 4. "ALIGN_EN,Override value for rx_align_en" "0,1" newline bitfld.word 0x0 3. "CDR_SSC_EN_OVRD_EN,Enable override value for rx_cdr_ssc_en" "0,1" newline bitfld.word 0x0 2. "CDR_SSC_EN,Override value for rx_cdr_ssc_en" "0,1" newline bitfld.word 0x0 1. "CDR_TRACK_EN_OVRD_EN,Enable override value for rx_cdr_track_en" "0,1" newline bitfld.word 0x0 0. "CDR_TRACK_EN,Override value for rx_cdr_track_en" "0,1" group.word 0x442C++0x1 line.word 0x0 "LANE1_DIG_ASIC_RX_OVRD_IN_4,Override values for incoming RX controls from ASIC. register #4" newline hexmask.word.byte 0x0 10.--15. 1. "RESERVED_15_10,Reserved for Future use" newline bitfld.word 0x0 9. "TERM_OVRD_EN,Enable override for rx_term_acdc and rx_term_en" "0,1" newline bitfld.word 0x0 8. "TERM_ACDC,Override value for rx_term_acdc" "0,1" newline bitfld.word 0x0 7. "TERM_EN,Override value for rx_term_en" "0,1" newline bitfld.word 0x0 6. "ADPT_OVRD_EN,Enable override for rx_adpt_dfe_en and rx_adpt_afe_en" "0,1" newline bitfld.word 0x0 5. "ADAPT_DFE_EN,Override value for rx_adapt_dfe_en" "0,1" newline bitfld.word 0x0 4. "ADAPT_AFE_EN,Override value for rx_adapt_afe_en" "0,1" newline bitfld.word 0x0 3. "INVERT_OVRD_EN,Enable override for rx_invert" "0,1" newline bitfld.word 0x0 2. "INVERT,Override value for rx_invert" "0,1" newline bitfld.word 0x0 1. "LPD_OVRD_EN,Enable override for rx_lpd" "0,1" newline bitfld.word 0x0 0. "LPD,Override value for rx_lpd" "0,1" group.word 0x4430++0x1 line.word 0x0 "LANE1_DIG_ASIC_RX_OVRD_IN_5,Override values for incoming RX controls from ASIC. register #5" newline hexmask.word 0x0 2.--15. 1. "RESERVED_15_2,Reserved for Future use" newline bitfld.word 0x0 1. "RESET_OVRD_EN,Enable override for rx_reset" "0,1" newline bitfld.word 0x0 0. "RESET,Override value for rx_reset" "0,1" group.word 0x4434++0x1 line.word 0x0 "LANE1_DIG_ASIC_RX_OVRD_EQ_IN_0,Override values for incoming RX EQ controls from ASIC. register #0" newline hexmask.word.byte 0x0 11.--15. 1. "EQ_CTLE_BOOST,Override value for rx_eq_ctle_boost" newline hexmask.word.byte 0x0 7.--10. 1. "RESERVED," newline hexmask.word.byte 0x0 3.--6. 1. "EQ_AFE_GAIN,Override value for rx_eq_afe_gain" newline bitfld.word 0x0 0.--2. "EQ_ATT_LVL,Override value for rx_eq_att_lvl" "0,1,2,3,4,5,6,7" group.word 0x4438++0x1 line.word 0x0 "LANE1_DIG_ASIC_RX_OVRD_EQ_IN_1,Override values for incoming RX EQ controls from ASIC. register #1" newline bitfld.word 0x0 15. "EQ_OVRD_EN,Enable override value for rx_eq_* inputs" "0,1" newline hexmask.word.byte 0x0 7.--14. 1. "EQ_DFE_TAP1,Override value for rx_eq_dfe_tap1" newline hexmask.word.byte 0x0 0.--6. 1. "EQ_DFE_TAP2,Override value for rx_eq_dfe_tap2" group.word 0x443C++0x1 line.word 0x0 "LANE1_DIG_ASIC_RX_OVRD_OUT_0,Override values for outgoing RX controls to ASIC. register #0" newline hexmask.word 0x0 7.--15. 1. "RESERVED_15_7,Reserved for Future use" newline bitfld.word 0x0 6. "ADAPT_STS_OVRD_EN,Enable override for rx_adapt_sts" "0,1" newline bitfld.word 0x0 4.--5. "ADAPT_STS,Override value for rx_adapt_sts" "0,1,2,3" newline bitfld.word 0x0 3. "LOS_OUT_OVRD_EN,Enable override for rx_los_r" "0,1" newline bitfld.word 0x0 2. "LOS,Override value for rx_los" "0,1" newline bitfld.word 0x0 1. "ACK_OVRD_EN,Enable override for rx_ack" "0,1" newline bitfld.word 0x0 0. "ACK,Override value for rx_ack" "0,1" rgroup.word 0x4440++0x1 line.word 0x0 "LANE1_DIG_ASIC_LANE_ASIC_IN,Current values for incoming LANE controls from ASIC" newline hexmask.word 0x0 2.--15. 1. "RESERVED_15_2,Reserved for Future use" newline bitfld.word 0x0 1. "LANE_RX2TX_PAR_LB,Value from ASIC for lane_rx2tx_par_lb_en_r" "0,1" newline bitfld.word 0x0 0. "LANE_TX2RX_SER_LB,Value from ASIC for lane_tx2rx_ser_lb_en_r" "0,1" rgroup.word 0x4444++0x1 line.word 0x0 "LANE1_DIG_ASIC_TX_ASIC_IN_0,Current values for incoming TX controls from ASIC. register #0" newline bitfld.word 0x0 15. "DISABLE,Value from ASIC for tx_disable" "0,1" newline bitfld.word 0x0 14. "DETECT_RX_REQ,Value from ASIC for tx_detrx_req" "0,1" newline bitfld.word 0x0 13. "MPLLB_SEL,Value from ASIC for tx_mpllb_sel" "0,1" newline bitfld.word 0x0 11.--12. "WIDTH,Value from ASIC for tx_width[1:0]" "0,1,2,3" newline bitfld.word 0x0 8.--10. "RATE,Value from ASIC for tx_rate[2:0]" "0,1,2,3,4,5,6,7" newline bitfld.word 0x0 6.--7. "PSTATE,Value from ASIC for tx_pstate[1:0]" "0,1,2,3" newline bitfld.word 0x0 5. "LPD,Value from ASIC for tx_lpd" "0,1" newline bitfld.word 0x0 4. "REQ,Value from ASIC for tx_req" "0,1" newline bitfld.word 0x0 3. "DATA_EN,Value from ASIC for tx_data_en" "0,1" newline bitfld.word 0x0 2. "INVERT,Value from ASIC for tx_invert" "0,1" newline bitfld.word 0x0 1. "RESET,Value from ASIC for tx_reset" "0,1" newline bitfld.word 0x0 0. "CLK_RDY,Value from ASIC for tx_clk_rdy" "0,1" rgroup.word 0x4448++0x1 line.word 0x0 "LANE1_DIG_ASIC_TX_ASIC_IN_1,Current values for incoming TX controls from ASIC. register #1" newline hexmask.word.byte 0x0 12.--15. 1. "RESERVED_15_12,Reserved for Future use" newline hexmask.word.byte 0x0 6.--11. 1. "TX_MAIN_CURSOR,Value from ASIC for tx_eq_main" newline bitfld.word 0x0 5. "VBOOST_EN,Value from ASIC for tx_vboost_en" "0,1" newline hexmask.word.byte 0x0 1.--4. 1. "IBOOST_LVL,Value from ASIC for tx_iboost_lvl" newline bitfld.word 0x0 0. "BEACON_EN,Value from ASIC for tx_beacon_en" "0,1" rgroup.word 0x444C++0x1 line.word 0x0 "LANE1_DIG_ASIC_TX_ASIC_IN_2,Current values for incoming TX controls from ASIC. register #2" newline hexmask.word.byte 0x0 12.--15. 1. "RESERVED_15_12,Reserved for Future use" newline hexmask.word.byte 0x0 6.--11. 1. "TX_POST_CURSOR,Value from ASIC for tx_eq_post" newline hexmask.word.byte 0x0 0.--5. 1. "TX_PRE_CURSOR,Value from ASIC for tx_eq_pre" rgroup.word 0x4450++0x1 line.word 0x0 "LANE1_DIG_ASIC_TX_ASIC_OUT,Current values for outgoing TX status controls from PHY" newline hexmask.word 0x0 2.--15. 1. "RESERVED_15_2,Reserved for Future use" newline bitfld.word 0x0 1. "DETRX_RESULT,Value from PHY for tx_detrx_result" "0,1" newline bitfld.word 0x0 0. "TX_ACK,Value from PHY for tx_ack" "0,1" rgroup.word 0x4454++0x1 line.word 0x0 "LANE1_DIG_ASIC_RX_ASIC_IN_0,Current values for incoming RX controls from ASIC. register #0" newline bitfld.word 0x0 15. "RESERVED_15_15,Reserved for Future use" "0,1" newline bitfld.word 0x0 14. "CDR_TRACK_EN,Value from ASIC for rx_cdr_track_en" "0,1" newline bitfld.word 0x0 13. "ADAPT_DFE_EN,Value from ASIC for rx_adapt_dfe_en" "0,1" newline bitfld.word 0x0 12. "ADAPT_AFE_EN,Value from ASIC for rx_adapt_afe_en" "0,1" newline bitfld.word 0x0 11. "RESERVED," "0,1" newline bitfld.word 0x0 9.--10. "WIDTH,Value from ASIC for rx_width" "0,1,2,3" newline bitfld.word 0x0 7.--8. "RATE,Value from ASIC for rx_rate" "0,1,2,3" newline bitfld.word 0x0 5.--6. "PSTATE,Value from ASIC for rx_pstate" "0,1,2,3" newline bitfld.word 0x0 4. "LPD,Value from ASIC for rx_lpd" "0,1" newline bitfld.word 0x0 3. "REQ,Value from ASIC for rx_req" "0,1" newline bitfld.word 0x0 2. "DATA_EN,Value from ASIC for rx_data_en" "0,1" newline bitfld.word 0x0 1. "INVERT,Value from ASIC for rx_invert" "0,1" newline bitfld.word 0x0 0. "RESET,Value from ASIC for rx_reset" "0,1" rgroup.word 0x4458++0x1 line.word 0x0 "LANE1_DIG_ASIC_RX_ASIC_IN_1,Current values for incoming RX controls from ASIC. register #1" newline hexmask.word.byte 0x0 10.--15. 1. "RESERVED_15_10,Reserved for Future use" newline bitfld.word 0x0 9. "RX_TERM_ACDC,Value from ASIC for rx_term_acdc" "0,1" newline bitfld.word 0x0 8. "RX_TERM_EN,Value from ASIC for rx_term_en" "0,1" newline bitfld.word 0x0 7. "LOS_LPFS_EN,Value from ASIC for rx_los_lfps_en" "0,1" newline bitfld.word 0x0 4.--6. "LOS_THRSHLD,Value from ASIC for rx_los_threshold" "0,1,2,3,4,5,6,7" newline bitfld.word 0x0 3. "DISABLE,Value from ASIC for rx_disable" "0,1" newline bitfld.word 0x0 2. "CLK_SHIFT,Value from ASIC for rx_clk_shift" "0,1" newline bitfld.word 0x0 1. "ALIGN_EN,Value from ASIC for rx_align_en" "0,1" newline bitfld.word 0x0 0. "CDR_SSC_EN,Value from ASIC for rx_cdr_ssc_en" "0,1" rgroup.word 0x445C++0x1 line.word 0x0 "LANE1_DIG_ASIC_RX_EQ_ASIC_IN_0,Current values for incoming RX EQ controls from ASIC. register #0" newline hexmask.word.byte 0x0 11.--15. 1. "EQ_CTLE_BOOST,Value from ASIC for rx_eq_ctle_boost" newline hexmask.word.byte 0x0 7.--10. 1. "RESERVED," newline hexmask.word.byte 0x0 3.--6. 1. "EQ_AFE_GAIN,Value from ASIC for rx_eq_afe_gain" newline bitfld.word 0x0 0.--2. "EQ_ATT_LVL,Value from ASIC for rx_eq_att_lvl" "0,1,2,3,4,5,6,7" rgroup.word 0x4460++0x1 line.word 0x0 "LANE1_DIG_ASIC_RX_EQ_ASIC_IN_1,Current values for incoming RX EQ controls from ASIC. register #1" newline bitfld.word 0x0 15. "RESERVED_15_15,Reserved for Future use" "0,1" newline hexmask.word.byte 0x0 7.--14. 1. "EQ_DFE_TAP1,Value from ASIC for rx_eq_dfe_tap1" newline hexmask.word.byte 0x0 0.--6. 1. "EQ_DFE_TAP2,Value from ASIC for rx_eq_dfe_tap2" rgroup.word 0x4464++0x1 line.word 0x0 "LANE1_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0,Current values for incoming RX CDR VCO controls from ASIC. register #0" newline hexmask.word.byte 0x0 8.--15. 1. "RESERVED_15_8,Reserved for Future use" newline hexmask.word.byte 0x0 1.--7. 1. "RX_REF_LD_VAL,Value from ASIC for rx_ref_ld_val" newline bitfld.word 0x0 0. "RX_CDR_VCO_LOWFREQ,Value from ASIC for rx_cdr_vco_lowfreq" "0,1" rgroup.word 0x4468++0x1 line.word 0x0 "LANE1_DIG_ASIC_RX_CDR_VCO_ASIC_IN_1,Current values for incoming RX CDR VCO controls from ASIC. register #1" newline bitfld.word 0x0 13.--15. "RESERVED_15_13,Reserved for Future use" "0,1,2,3,4,5,6,7" newline hexmask.word 0x0 0.--12. 1. "RX_VCO_LD_VAL,Value from ASIC for rx_vco_ld_val" rgroup.word 0x446C++0x1 line.word 0x0 "LANE1_DIG_ASIC_RX_ASIC_OUT_0,Current values for outgoing RX status controls from PHY. register #0" newline hexmask.word 0x0 5.--15. 1. "RESERVED_15_5,Reserved for Future use" newline bitfld.word 0x0 3.--4. "ADAPT_STS,Value from PHY for rx_adapt_sts" "0,1,2,3" newline bitfld.word 0x0 2. "VALID,Value from PHY for rx_valid" "0,1" newline bitfld.word 0x0 1. "LOS,Value from PHY for rx_los" "0,1" newline bitfld.word 0x0 0. "ACK,Value from PHY for rx_ack" "0,1" repeat 2. (list 0x0 0x1 )(list 0x0 0x8 ) group.word ($2+0x4480)++0x1 line.word 0x0 "LANE1_DIG_TX_PWRCTL_TX_PSTATE_P$1,TX Power State Control Register for P0" newline hexmask.word.byte 0x0 9.--15. 1. "RESERVED_15_9,Reserved for Future use" newline bitfld.word 0x0 8. "TX_P0_ALLOW_RXDET,If asserted then rxdet request is allowed in P0" "0,1" newline bitfld.word 0x0 7. "TX_P0_DATA_EN,This is ANDed with top-level tx_data_en asic input" "0,1" newline bitfld.word 0x0 6. "TX_P0_DIG_CLK_EN,Enable/Disable TX digital clocks in P0" "0,1" newline bitfld.word 0x0 5. "TX_P0_ANA_SERIAL_EN,Value of TX ana serial_en in P0" "0,1" newline bitfld.word 0x0 4. "TX_P0_ANA_RESET,Value of TX ana reset in P0" "0,1" newline bitfld.word 0x0 3. "TX_P0_ANA_WORD_CLK_EN,Value of TX ana word_clk_en in P0" "0,1" newline bitfld.word 0x0 2. "TX_P0_ANA_CLK_EN,Value of TX ana clk_en in P0" "0,1" newline bitfld.word 0x0 1. "TX_P0_ANA_VCM_HOLD,Value of TX ana vcm_hold in P0" "0,1" newline bitfld.word 0x0 0. "TX_P0_ANA_REFGEN_EN,Value of TX ana refgen_en in P0" "0,1" repeat.end group.word 0x4484++0x1 line.word 0x0 "LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S,TX Power State Control Register for P0S" newline hexmask.word.byte 0x0 9.--15. 1. "RESERVED_15_9,Reserved for Future use" newline bitfld.word 0x0 8. "TX_P0S_ALLOW_RXDET,If asserted then rxdet request is allowed in P0S" "0,1" newline bitfld.word 0x0 7. "TX_P0S_DATA_EN,This is ANDed with top-level tx_data_en asic input" "0,1" newline bitfld.word 0x0 6. "TX_P0S_DIG_CLK_EN,Enable/Disable TX digital clocks in P0S" "0,1" newline bitfld.word 0x0 5. "TX_P0S_ANA_SERIAL_EN,Value of TX ana serial_en in P0S" "0,1" newline bitfld.word 0x0 4. "TX_P0S_ANA_RESET,Value of TX ana reset in P0S" "0,1" newline bitfld.word 0x0 3. "TX_P0S_ANA_WORD_CLK_EN,Value of TX ana word_clk_en in P0S" "0,1" newline bitfld.word 0x0 2. "TX_P0S_ANA_CLK_EN,Value of TX ana clk_en in P0S" "0,1" newline bitfld.word 0x0 1. "TX_P0S_ANA_VCM_HOLD,Value of TX ana vcm_hold in P0S" "0,1" newline bitfld.word 0x0 0. "TX_P0S_ANA_REFGEN_EN,Value of TX ana refgen_en in P0S" "0,1" group.word 0x448C++0x1 line.word 0x0 "LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2,TX Power State Control Register for P2" newline hexmask.word.byte 0x0 10.--15. 1. "RESERVED_15_10,Reserved for Future use" newline bitfld.word 0x0 9. "TX_P2_ALLOW_VBOOST,If asserted then vboost is allowed in P2" "0,1" newline bitfld.word 0x0 8. "TX_P2_ALLOW_RXDET,If asserted then rxdet request is allowed" "0,1" newline bitfld.word 0x0 7. "TX_P2_DATA_EN,This is ANDed with top-level tx_data_en asic input" "0,1" newline bitfld.word 0x0 6. "TX_P2_DIG_CLK_EN,Enable/Disable TX digital clocks in P2" "0,1" newline bitfld.word 0x0 5. "TX_P2_ANA_SERIAL_EN,Value of TX ana serial_en in P2" "0,1" newline bitfld.word 0x0 4. "TX_P2_ANA_RESET,Value of TX ana reset in P2" "0,1" newline bitfld.word 0x0 3. "TX_P2_ANA_WORD_CLK_EN,Value of TX ana word_clk_en in P2" "0,1" newline bitfld.word 0x0 2. "TX_P2_ANA_CLK_EN,Value of TX ana clk_en in P2" "0,1" newline bitfld.word 0x0 1. "TX_P2_ANA_VCM_HOLD,Value of TX ana vcm_hold in P2" "0,1" newline bitfld.word 0x0 0. "TX_P2_ANA_REFGEN_EN,Value of TX ana refgen_en in P2" "0,1" group.word 0x4490++0x1 line.word 0x0 "LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_0,TX Power UP Time Register #0" newline hexmask.word.byte 0x0 8.--15. 1. "TX_CLK_EN,Power up time (in ref_range cycles) for TX ana clock enable (spec: >=1us)" newline hexmask.word.byte 0x0 0.--7. 1. "TX_REFGEN_EN_TIME,Power up time (in ref_range cycles) for TX ana refgen enable (spec: >=500ns)" group.word 0x4494++0x1 line.word 0x0 "LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_1,TX Power UP Time Register #1" newline bitfld.word 0x0 15. "SKIP_TX_VCM_HOLD_WAIT,Skip wait for TX common mode hold power up" "0,1" newline hexmask.word 0x0 0.--14. 1. "TX_VCM_HOLD_TIME_14_0,Power up time (in ref_range cycles) for TX common mode (spec: >=800us) (bits 14:0)" group.word 0x4498++0x1 line.word 0x0 "LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_2,TX Power UP Time Register #2" newline bitfld.word 0x0 13.--15. "DTB_SEL,Selects data to drive on DTB 0 - disabled 1 - tx_ack and tx_pwrsm_state[0] 2 - tx_ana_rxdetp_result_i tx_ana_rxdetm_result_i 3 - tx_ana_reset_i tx_ana_clk_en_i 4 - analog/asic clocks 5 - asic early signal / clock aligner shift 6 - tx_clk_state.." "disabled,tx_ack and tx_pwrsm_state[0],tx_ana_rxdetp_result_i,tx_ana_reset_i,analog/asic clocks,asic early signal / clock aligner shift,tx_clk_state counter / lbert strobe,ref_dig_rst/tx_dig_rst" newline hexmask.word 0x0 0.--12. 1. "TX_VBOOST_DIS_TIME_12_0,TX vboost disable time (in ref_range cycles) (spec: >=200us) (bits 12:0)" group.word 0x449C++0x1 line.word 0x0 "LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_3,TX Power UP Time Register #3" newline hexmask.word 0x0 4.--15. 1. "RESERVED_15_4,Reserved for Future use" newline bitfld.word 0x0 3. "TX_VBOOST_DIS_TIME_13,TX vboost disable time (in ref_range cycles) (spec: >=200us) (bit 13)" "0,1" newline bitfld.word 0x0 0.--2. "TX_VCM_HOLD_TIME_17_15,Power up time (in ref_range cycles) for TX common mode (spec: >=800us) (bits 17:15)" "0,1,2,3,4,5,6,7" group.word 0x44A0++0x1 line.word 0x0 "LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_4,TX Power UP Time Register #4" newline rbitfld.word 0x0 15. "RESERVED_15_15,Reserved for Future use" "0,1" newline hexmask.word 0x0 0.--14. 1. "TX_VCM_HOLD_GS_TIME,TX common mode gear-shift time (in ref range cycles) (spec: >=400us)" group.word 0x44A4++0x1 line.word 0x0 "LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_5,TX Power UP Time Register #5" newline rbitfld.word 0x0 15. "RESERVED_15_15,Reserved for Future use" "0,1" newline bitfld.word 0x0 13.--14. "TX_SERIAL_EN_TIME,Power up time (in ref_range cycles) for TX ana serial enable (spec: >=50ns)" "0,1,2,3" newline bitfld.word 0x0 11.--12. "TX_RESET_TIME,TX Reset deassertion time (in ref_range cycles) (spec: >=50ns)" "0,1,2,3" newline bitfld.word 0x0 10. "FAST_TX_RXDET,Enable fast TX RX-detection (simulation only)" "0,1" newline hexmask.word 0x0 0.--9. 1. "TX_RXDET_TIME,RX Detect up time (in ref_range cycles) starting from asserting rxdet_en (spec: from 3.55us to 25.9us)" group.word 0x44A8++0x1 line.word 0x0 "LANE1_DIG_TX_LBERT_CTL,Pattern Generator controls" newline rbitfld.word 0x0 15. "RESERVED_15_15,Reserved for Future use" "0,1" newline hexmask.word 0x0 5.--14. 1. "PAT0,Pattern for modes 3-5" newline bitfld.word 0x0 4. "TRIGGER_ERR,Insert a single error into a lsb Any write of a 1 to this bit will insert an error" "0,1" newline hexmask.word.byte 0x0 0.--3. 1. "MODE,Pattern to generate When changing modes you must change to disabled first 0 - Disabled 1 - lfsr31: X^31 + X^28 + 1 2 - lfsr23: X^23 + X^18 + 1 3 - lfsr23: x^23 + x^21 + x^16 + x^8 + x^5 + x^2 + 1 4 - lfsr16: x^16 + x^5 + x^4 + x^3 + 1 5 - lfsr15:.." group.word 0x44AC++0x1 line.word 0x0 "LANE1_DIG_TX_CLK_ALIGN_TX_CTL_0,TX Clock Alignment Control Register #0" newline hexmask.word.byte 0x0 9.--15. 1. "RESERVED_15_9,Reserved for Future use" newline bitfld.word 0x0 8. "TX_FIFO_BYPASS,By-pass TX datapath FIFO" "0,1" newline hexmask.word.byte 0x0 4.--7. 1. "TX_NUM_2UI_SHIFTS_20B_MODE," newline hexmask.word.byte 0x0 0.--3. 1. "TX_NUM_2UI_SHIFTS_16B_MODE," repeat 3. (list 0x0 0x1 0x2 )(list 0x0 0x8 0xC ) group.word ($2+0x4500)++0x1 line.word 0x0 "LANE1_DIG_RX_PWRCTL_RX_PSTATE_P$1,RX Power State Control Register for P0" newline hexmask.word.byte 0x0 12.--15. 1. "RESERVED_15_12,Reserved for Future use" newline bitfld.word 0x0 11. "RX_P0_DIG_CLK_EN,Enable/Disable RX digital clocks in P0" "0,1" newline bitfld.word 0x0 10. "RX_P0_VCO_CONTCAL_EN,Enable/Disable continous calibration of the RX VCO in P0 If RX_P0_DIG_CLK_EN and the top-level rx_data_en are both asserted then contiuous calibration is turned off and this value is ignored" "0,1" newline bitfld.word 0x0 9. "RX_P0_VCO_CAL_RST,Enable/Disable resetting the RX VCO in P0" "0,1" newline bitfld.word 0x0 8. "RX_P0_VCO_FREQ_RST,Enable/Disable resetting the RX VCO frequency in P0" "0,1" newline bitfld.word 0x0 7. "RX_P0_ANA_CDR_EN,Value of RX ana cdr_en in P0" "0,1" newline bitfld.word 0x0 6. "RX_P0_ANA_DESER_EN,Value of RX ana deserial_en in P0" "0,1" newline bitfld.word 0x0 5. "RX_P0_ANA_CLK_DCC_EN,Value of RX ana CLK_DCC_EN in P0" "0,1" newline bitfld.word 0x0 4. "RX_P0_ANA_CLK_EN,Value of RX ana clk_en in P0" "0,1" newline bitfld.word 0x0 3. "RESERVED," "0,1" newline bitfld.word 0x0 2. "RX_P0_ANA_CLK_VREG_EN,Value of RX ana clk_vreg_en in P0" "0,1" newline bitfld.word 0x0 1. "RX_P0_ANA_AFE_EN,Value of RX ana afe_en in P0" "0,1" newline bitfld.word 0x0 0. "RX_P0_ANA_LOS_EN,Value of RX ana los_en in P0" "0,1" repeat.end group.word 0x4504++0x1 line.word 0x0 "LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S,RX Power State Control Register for P0S" newline hexmask.word.byte 0x0 12.--15. 1. "RESERVED_15_12,Reserved for Future use" newline bitfld.word 0x0 11. "RX_P0S_DIG_CLK_EN,Enable/Disable RX digital clocks in P0S" "0,1" newline bitfld.word 0x0 10. "RX_P0S_VCO_CONTCAL_EN,Enable/Disable continous calibration of the RX VCO in P0S If RX_P0S_DIG_CLK_EN and the top-level rx_data_en are both asserted then contiuous calibration is turned off and this value is ignored" "0,1" newline bitfld.word 0x0 9. "RX_P0S_VCO_CAL_RST,Enable/Disable resetting the RX VCO in P0S" "0,1" newline bitfld.word 0x0 8. "RX_P0S_VCO_FREQ_RST,Enable/Disable resetting the RX VCO frequency in P0S" "0,1" newline bitfld.word 0x0 7. "RX_P0S_ANA_CDR_EN,Value of RX ana cdr_en in P0S" "0,1" newline bitfld.word 0x0 6. "RX_P0S_ANA_DESER_EN,Value of RX ana deserial_en in P0S" "0,1" newline bitfld.word 0x0 5. "RX_P0S_ANA_CLK_DCC_EN,Value of RX ana CLK_DCC_EN in P0S" "0,1" newline bitfld.word 0x0 4. "RX_P0S_ANA_CLK_EN,Value of RX ana clk_en in P0S" "0,1" newline bitfld.word 0x0 3. "RESERVED," "0,1" newline bitfld.word 0x0 2. "RX_P0S_ANA_CLK_VREG_EN,Value of RX ana clk_vreg_en in P0S" "0,1" newline bitfld.word 0x0 1. "RX_P0S_ANA_AFE_EN,Value of RX ana afe_en in P0S" "0,1" newline bitfld.word 0x0 0. "RX_P0S_ANA_LOS_EN,Value of RX ana los_en in P0S" "0,1" group.word 0x4510++0x1 line.word 0x0 "LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_0,RX Power UP Time Register #0" newline hexmask.word.byte 0x0 10.--15. 1. "RESERVED_15_10,Reserved for Future use" newline bitfld.word 0x0 9. "SKIP_RX_LOS_EN_WAIT,Skip wait for RX LOS enable" "0,1" newline hexmask.word 0x0 0.--8. 1. "RX_LOS_EN_TIME,Power up time (in ref_range cycles) for RX ana los enable (spec >=10us)" group.word 0x4514++0x1 line.word 0x0 "LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_1,RX Power UP Time Register #1" newline rbitfld.word 0x0 14.--15. "RESERVED_15_14,Reserved for Future use" "0,1,2,3" newline bitfld.word 0x0 13. "FAST_RX_VREG_EN,Enable fast RX VREG enable (simulation only)" "0,1" newline hexmask.word.byte 0x0 7.--12. 1. "RX_VREG_EN_TIME,Power up time (in ref_range cycles) for RX ana vreg enable (spec 500ns)" newline bitfld.word 0x0 6. "FAST_RX_AFE_EN,Enable fast RX AFE enable (simulation only)" "0,1" newline hexmask.word.byte 0x0 0.--5. 1. "RX_AFE_EN_TIME,Power up time (in ref_range cycles) for RX ana AFE enable (spec >=1us)" group.word 0x4518++0x1 line.word 0x0 "LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_2,RX Power UP Time Register #2" newline hexmask.word 0x0 7.--15. 1. "RESERVED_15_7,Reserved for Future use" newline bitfld.word 0x0 6. "FAST_RX_CLK_EN,Enable fast RX clock enable (simulation only)" "0,1" newline hexmask.word.byte 0x0 0.--5. 1. "RX_CLK_EN_TIME,Power up time (in ref_range cycles) for RX ana clk (or dcc) enable (spec >1us)" group.word 0x451C++0x1 line.word 0x0 "LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_3,RX Power UP Time Register #3" newline bitfld.word 0x0 14.--15. "RX_DESER_DIS_TIME,Power down time in (ref_range cycles) for RX ana deserial enable" "0,1,2,3" newline bitfld.word 0x0 12.--13. "RX_DESER_EN_TIME,Power up time (in ref_range cycles) for RX ana deserial enable" "0,1,2,3" newline hexmask.word.byte 0x0 8.--11. 1. "RX_CDR_EN_TIME,Power up time (in ref_range cycles) for RX ana cdr (or dfe/dfe_taps) enable (spec 0ns)" newline hexmask.word.byte 0x0 2.--7. 1. "RSVD_3_7_2,Reserved" newline bitfld.word 0x0 0.--1. "RX_RATE_TIME,Power up time (in ref_range cycles) for RX ana rate or width change" "0,1,2,3" group.word 0x4520++0x1 line.word 0x0 "LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0,RX VCO calibration controls register #0" newline hexmask.word.byte 0x0 12.--15. 1. "RESERVED_15_12,Reserved for Future use" newline bitfld.word 0x0 9.--11. "INT_GAIN_CAL_BOUNCE_CNT,Number of bounces (i.e. direction changes) on the int_gain code before indicating that the RX VCO calibration is done" "0,1,2,3,4,5,6,7" newline bitfld.word 0x0 6.--8. "INT_GAIN_CAL_CNT_SHIFT,Number of shifts to apply to ld_cnt inputs when performing int_gain code calibration" "0,1,2,3,4,5,6,7" newline bitfld.word 0x0 5. "INT_GAIN_CAL_FIXED_CNT_EN,Enable a fixed count (instead of bounce count) for int_gain code calibration" "0,1" newline hexmask.word.byte 0x0 0.--4. 1. "INT_GAIN_CAL_FIXED_CNT,Number of steps done during int_gain code calibration when INT_GAIN_CAL_FIXED_CNT_EN is enabled." group.word 0x4524++0x1 line.word 0x0 "LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1,RX VCO calibration controls register #1" newline hexmask.word.byte 0x0 9.--15. 1. "DTB_SEL,DTB select for RX VCO dtb signals 7'h01 - {chkfrq_en ref_dig_clk} 7'h02 - {rx_ana_cdr_vco_en_i rx_ana_cdr_startup_i} 7'h04 - {rx_vco_up dpll_freq_rst} 7'h08 - {rx_vco_contcal_en rx_vco_cal_rst} 7'h10 - {chkfrq_done vcoclk_too_fast} 7'h20 -.." newline hexmask.word.byte 0x0 5.--8. 1. "DPLL_CAL_UG,DPLL calibration update on int_gain code 3'h0 - 0 Else - (1/16)*2^(DPLL_CAL_UG-1) LSB/update Maximum DPLL_CAL_UG=10 i.e. 32 LSB/update" newline bitfld.word 0x0 4. "DISABLE_INT_CAL_MODE,When asserted then the DPLL frequency register is never modified by the RX VCO calibration FSM (even if DPLL_CAL_UG is non-zero). In this case the calibration will always be performed on the VCO freq_tune code. This allows.." "0,1" newline bitfld.word 0x0 3. "RX_VCO_CONTCAL_EN,Override value for the continous calibration enable from the RX PWRSM" "0,1" newline bitfld.word 0x0 2. "RX_VCO_CAL_RST,Override value for the calibration reset from the RX PWRSM" "0,1" newline bitfld.word 0x0 1. "RX_VCO_FREQ_RST,Override value for the frequency reset from the RX PWRSM" "0,1" newline bitfld.word 0x0 0. "RX_VCO_OVRD_SEL,Override the calibration controls from the RX PWRSM" "0,1" group.word 0x4528++0x1 line.word 0x0 "LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2,RX VCO calibration controls register #2" newline bitfld.word 0x0 15. "SKIP_RX_VCO_CAL,Skip RX VCO calibration altogether" "0,1" newline bitfld.word 0x0 14. "SKIP_RX_VCO_FREQ_TUNE_CAL,Skip RX VCO coarse calibration" "0,1" newline hexmask.word.byte 0x0 10.--13. 1. "FREQ_TUNE_CAL_STEPS,Number of cal steps of freq tune" newline hexmask.word 0x0 0.--9. 1. "FREQ_TUNE_START_VAL,Starting value of freq tune code" group.word 0x452C++0x1 line.word 0x0 "LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0,RX Power UP Time Register #0" newline bitfld.word 0x0 15. "FAST_RX_VCO_WAIT,Enable fast RX VCO power up (simulation only)" "0,1" newline hexmask.word.byte 0x0 11.--14. 1. "RX_VCO_CNTR_PWRUP_TIME,Power up time (in ref_range cycles) for Rx ana vco cnter (spec >200ns)" newline hexmask.word.byte 0x0 7.--10. 1. "RX_VCO_UPDATE_TIME,Settle time (in ref_range cycles) for RX ana vco update (freq_tune or int_gain) (spec >200ns)" newline hexmask.word.byte 0x0 0.--6. 1. "RX_VCO_STARTUP_TIME,Power up time (in ref_range cycles) for RX ana vco startup (spec >1us)" group.word 0x4530++0x1 line.word 0x0 "LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1,RX Power UP Time Register #1" newline hexmask.word 0x0 3.--15. 1. "RESERVED_15_3,Reserved for Future use" newline bitfld.word 0x0 0.--2. "RX_VCO_CNTR_SETTLE_TIME,RX VCO counter value settling time in (ref_dig_clk cycles) (spec: 3 ref_dig_clk cycle)" "0,1,2,3,4,5,6,7" rgroup.word 0x4534++0x1 line.word 0x0 "LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_0,RX VCO status register #0" newline bitfld.word 0x0 14.--15. "RESERVED_15_14,Reserved for Future use" "0,1,2,3" newline bitfld.word 0x0 13. "RX_ANA_CDR_VCO_EN,Current value of rx_ana_cdr_vco_en_i" "0,1" newline bitfld.word 0x0 12. "RX_ANA_CDR_STARTUP,Current value of rx_ana_cdr_startup_i" "0,1" newline bitfld.word 0x0 11. "RX_ANA_VCO_CNTR_EN,Current value of rx_ana_vco_cntr_en_i" "0,1" newline bitfld.word 0x0 10. "RX_ANA_VCO_CNTR_PD,Current value of rx_ana_vco_cntr_pd_i" "0,1" newline hexmask.word 0x0 0.--9. 1. "RX_ANA_CDR_FREQ_TUNE,Current value of rx_ana_cdr_freq_tune_i" rgroup.word 0x4538++0x1 line.word 0x0 "LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_1,RX VCO status register #1" newline hexmask.word.byte 0x0 9.--15. 1. "RESERVED_15_9,Reserved for Future use" newline bitfld.word 0x0 8. "DPLL_FREQ_RST,Indicates that the RX integral frequency is reset or not" "0,1" newline bitfld.word 0x0 7. "RX_VCO_CAL_DONE,Indicates that the RX VCO has completed calibration" "0,1" newline bitfld.word 0x0 6. "RX_VCO_CONTCAL_EN,Value of the continous calibration enable from the RX PWRSM" "0,1" newline bitfld.word 0x0 5. "RX_VCO_CAL_RST,Value of the calibration reset from the RX PWRSM" "0,1" newline bitfld.word 0x0 4. "RX_VCO_FREQ_RST,Value of the RX VCO frequency reset from the RX PWRSM" "0,1" newline hexmask.word.byte 0x0 0.--3. 1. "RX_VCO_FSM_STATE,Value of the RX VCO CAL FSM" rgroup.word 0x453C++0x1 line.word 0x0 "LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_2,RX VCO status register #2" newline bitfld.word 0x0 15. "RX_VCO_UP,Indicates that the RX VCO is ready" "0,1" newline bitfld.word 0x0 14. "RX_VCO_CORRECT,Indicates that the RX VCO clock has the correct frequency" "0,1" newline bitfld.word 0x0 13. "VCOCLK_TOO_FAST,Indicates that the RX VCO clock frequency is too fast" "0,1" newline hexmask.word 0x0 0.--12. 1. "VCO_CNTR_FINAL,Value of Rx VCO counter when refclk counter expired" group.word 0x4540++0x1 line.word 0x0 "LANE1_DIG_RX_RX_ALIGN_XAUI_COMM_MASK,XAUI_COMMA Mask" newline hexmask.word.byte 0x0 10.--15. 1. "RESERVED_15_10,Reserved for Future use" newline hexmask.word 0x0 0.--9. 1. "XAUI_COMM_MASK,XAUI_COMMA Mask. For 10-bit COMMA set the mask to 0x3FF and for 7-bit COMMA set the mask to 0x3F8" group.word 0x4544++0x1 line.word 0x0 "LANE1_DIG_RX_LBERT_CTL,Pattern Matcher controls" newline hexmask.word 0x0 5.--15. 1. "RESERVED_15_5,Reserved for Future use" newline bitfld.word 0x0 4. "SYNC,Synchronize pattern matcher LFSR with incoming data A write of a one to this bit will reset the error counter and start a synchronization of the PM. There is no need to write this back to zero to run normally." "0,1" newline hexmask.word.byte 0x0 0.--3. 1. "MODE,Pattern to match When changing modes you must change to disabled first 0 - Disabled 1 - lfsr31: X^31 + X^28 + 1 2 - lfsr23: X^23 + X^18 + 1 3 - lfsr23: x^23 + x^21 + x^16 + x^8 + x^5 + x^2 + 1 4 - lfsr16: x^16 + x^5 + x^4 + x^3 + 1 5 - lfsr15: X^15.." group.word 0x4548++0x1 line.word 0x0 "LANE1_DIG_RX_LBERT_ERR,Pattern match error counter" newline bitfld.word 0x0 15. "OV14,If active multiply COUNT by 128. If OV14=1 and COUNT=2^15-1 signals overflow of counter (2 reads needed to read value)" "0,1" newline hexmask.word 0x0 0.--14. 1. "COUNT,A read of this register or a sync of the PM resets the error count. Current error count If OV14 field is active then multiply count by 128 (2 reads needed to read value)" group.word 0x454C++0x1 line.word 0x0 "LANE1_DIG_RX_CDR_CDR_CTL_0,Control bits for receiver in recovered domain" newline hexmask.word.byte 0x0 11.--15. 1. "RESERVED_15_11,Reserved for Future use" newline hexmask.word.byte 0x0 7.--10. 1. "DTB_SEL,Select to drive various signals onto the dtb 0 - disabled 1 - rx_pr_stable rx_afe_stable from rx_ana_ctl 2 - com_good com_bad from rx_align 3 - shift_in_prog ana_odd_data from rx_align 4 - 2 msb's of XAUI align FSM state 5 - 2 lsb's of XAUI.." newline bitfld.word 0x0 6. "ALWAYS_REALIGN,Realign on any misaligned comma" "0,1" newline bitfld.word 0x0 5. "PHDET_EN_PR_MODE,Enable partial response phase detector mode" "0,1" newline bitfld.word 0x0 4. "PHDET_POL,Reverse polarity of phase error" "0,1" newline bitfld.word 0x0 2.--3. "PHDET_EDGE,Edges to use for phase detection. 10 - Use both edges 01 - Use rising edges only 11 - Use falling edges only 00 - Ignore all edges" "Ignore all edges,Use rising edges only,?,?" newline bitfld.word 0x0 0.--1. "PHDET_EN,Enable phase detector. top bit is odd slicers bottom is even" "0,1,2,3" group.word 0x4550++0x1 line.word 0x0 "LANE1_DIG_RX_CDR_CDR_CTL_1,CDR Control Register #1" newline hexmask.word.byte 0x0 10.--15. 1. "SSC_OFF_CNT1,When SSC mode is disabled the 12-bit word count in gain stage 1 is: (SSC_OFF_CNT1 * 4) in 20b mode (SSC_OFF_CNT1 * 5) in 16b mode" newline hexmask.word 0x0 0.--9. 1. "SSC_OFF_CNT0,When SSC mode is disabled the 12-bit word count in gain stage 0 is: (SSC_OFF_CNT0 * 4) in 20b mode (SSC_OFF_CNT0 * 5) in 16b mode" group.word 0x4554++0x1 line.word 0x0 "LANE1_DIG_RX_CDR_CDR_CTL_2,CDR Control Register #2" newline hexmask.word.byte 0x0 9.--15. 1. "SSC_ON_CNT1,When SSC mode is enabled the 12-bit word count in gain stage 1 is: (SSC_ON_CNT1 * 8) in 20b mode (SSC_ON_CNT1 * 10) in 16b mode" newline hexmask.word 0x0 0.--8. 1. "SSC_ON_CNT0,When SSC mode is enabled the 12-bit word count in gain stage 0 is: (SSC_ON_CNT0 * 8) in 20b mode (SSC_ON_CNT0 * 10) in 16b mode" group.word 0x4558++0x1 line.word 0x0 "LANE1_DIG_RX_CDR_CDR_CTL_3,CDR Control Register #3" newline bitfld.word 0x0 13.--15. "FRUG_OVRD_VALUE,Override value for FRUG (frequency update gain) 3'h0 - 0 3'h1 - 1/16 LSB/update 3'h2 - 1/8 LSB/update 3'h3 - 1/4 LSB/update 3'h4 - 1/2 LSB/update 3'h5 - 1 LSB/update 3'h6 - 2 LSB/update 3'h7 - 4 LSB/update" "0,1,2,3,4,5,6,7" newline bitfld.word 0x0 10.--12. "PHUG_OVRD_VALUE,Override value for PHUG (phase update gain) 3'h0 - 0 3'h1 - 1000 ppm 3'h2 - 2000 ppm 3'h3 - 3000 ppm 3'h4 - 4000 ppm 3'h5 - 5000 ppm 3'h6 - 6000 ppm 3'h7 - 7000 ppm" "0,1,2,3,4,5,6,7" newline bitfld.word 0x0 9. "OVRD_DPLL_GAIN,Override PHUG and FRUG values" "0,1" newline bitfld.word 0x0 6.--8. "SSC_OFF_FRUG0,When SSC mode is disabled the frug value in gain stage 0 is SSC_OFF_FRUG0" "0,1,2,3,4,5,6,7" newline bitfld.word 0x0 3.--5. "SSC_OFF_PHUG1,When SSC mode is disabled the phug value in gain stage 1 is SSC_OFF_PHUG1" "0,1,2,3,4,5,6,7" newline bitfld.word 0x0 0.--2. "SSC_OFF_PHUG0,When SSC mode is disabled the phug value in gain stage 0 is SSC_OFF_PHUG0" "0,1,2,3,4,5,6,7" group.word 0x455C++0x1 line.word 0x0 "LANE1_DIG_RX_CDR_CDR_CTL_4,CDR Control Register #4" newline rbitfld.word 0x0 15. "RESERVED_15_15,Reserved for Future use" "0,1" newline bitfld.word 0x0 12.--14. "SSC_ON_PHUG1,When SSC mode is enabled the phug value in gain stage 1 is SSC_ON_PHUG1" "0,1,2,3,4,5,6,7" newline bitfld.word 0x0 9.--11. "SSC_ON_PHUG0,When SSC mode is enabled the phug value in gain stage 0 is SSC_ON_PHUG0" "0,1,2,3,4,5,6,7" newline bitfld.word 0x0 6.--8. "SSC_ON_FRUG1,When SSC mode is enabled the frug value in gain stage 1 is SSC_ON_FRUG1" "0,1,2,3,4,5,6,7" newline bitfld.word 0x0 3.--5. "SSC_ON_FRUG0,When SSC mode is enabled the frug value in gain stage 0 is SSC_ON_FRUG0" "0,1,2,3,4,5,6,7" newline bitfld.word 0x0 0.--2. "SSC_OFF_FRUG1,When SSC mode is disabled the frug value in gain stage 1 is SSC_OFF_FRUG1" "0,1,2,3,4,5,6,7" rgroup.word 0x4560++0x1 line.word 0x0 "LANE1_DIG_RX_CDR_STAT,Current output values to dpll (phug. frug)" newline hexmask.word 0x0 6.--15. 1. "RESERVED_15_6,Reserved for Future use" newline bitfld.word 0x0 3.--5. "FRUG_VALUE,NOTES: Current value for dpll_frug[2:0]" "0,1,2,3,4,5,6,7" newline bitfld.word 0x0 0.--2. "PHUG_VALUE,NOTES: Current value for dpll_phug[2:0]" "0,1,2,3,4,5,6,7" group.word 0x4564++0x1 line.word 0x0 "LANE1_DIG_RX_DPLL_FREQ,Current frequency integrator value." newline rbitfld.word 0x0 14.--15. "RESERVED_15_14,Reserved for Future use" "0,1,2,3" newline hexmask.word 0x0 0.--13. 1. "VAL,Freq is 125*VAL ppm from the reference (2 reads needed to read value)" group.word 0x4568++0x1 line.word 0x0 "LANE1_DIG_RX_DPLL_FREQ_BOUND_0,Frequency Bounds for incoming data stream #0" newline hexmask.word.byte 0x0 11.--15. 1. "RESERVED_15_11,Reserved for Future use" newline hexmask.word 0x0 1.--10. 1. "UPPER_FREQ_BOUND,Upper frequency bound in terms of LSBs of the integral control code" newline bitfld.word 0x0 0. "FREQ_BOUND_EN,Enable the frequency bounds feature" "0,1" group.word 0x456C++0x1 line.word 0x0 "LANE1_DIG_RX_DPLL_FREQ_BOUND_1,Frequency Bounds for incoming data stream #1" newline hexmask.word.byte 0x0 10.--15. 1. "RESERVED_15_10,Reserved for Future use" newline hexmask.word 0x0 0.--9. 1. "LOWER_FREQ_BOUND,Lower frequency bound in terms of LSBs of the integral control code" group.word 0x4580++0x1 line.word 0x0 "LANE1_DIG_RX_ADPTCTL_ADPT_CFG_0,Adaptation Configuration Register #0" newline bitfld.word 0x0 15. "ADPT_CLK_DIV4_EN,Set the adaptation clock to be divided by 4 (default is div2)" "0,1" newline bitfld.word 0x0 14. "START_ASM1,Start adaptation state machine #1 (VGA CTLE DFE EYEH) This register-bit is self-clearing" "0,1" newline hexmask.word.byte 0x0 10.--13. 1. "N_TGG_ASM1,Number of toggle loop iterations for ASM1" newline hexmask.word 0x0 0.--9. 1. "N_TOP_ASM1,Number of top level loop iterations for ASM1" group.word 0x4584++0x1 line.word 0x0 "LANE1_DIG_RX_ADPTCTL_ADPT_CFG_1,Adaptation Configuration Register #1" newline hexmask.word.byte 0x0 12.--15. 1. "RESERVED_15_12,Reserved for Future use" newline bitfld.word 0x0 11. "CTLE_POLE_OVRD_EN,Override CTLE pole value (only valid if adaptation is run)" "0,1" newline bitfld.word 0x0 8.--10. "CTLE_POLE_OVRD_VAL,CTLE Pole override value to load at start of adaptation" "0,1,2,3,4,5,6,7" newline bitfld.word 0x0 7. "FAST_AFE_DFE_SETTLE,Enable fast AFE and DFE settling time (simulation only)" "0,1" newline hexmask.word.byte 0x0 0.--6. 1. "N_WAIT_ASM1,Number of wait cycles for Adaptation SM #1" group.word 0x4588++0x1 line.word 0x0 "LANE1_DIG_RX_ADPTCTL_ADPT_CFG_2,Adaptation Configuration Register #2" newline hexmask.word.byte 0x0 10.--15. 1. "RESERVED_15_10,Reserved for Future use" newline hexmask.word.byte 0x0 5.--9. 1. "TGG_PTTRN_1,Pattern for the second toggle loop Error slicer is moved upward by Data tap1 if this pattern is matched" newline hexmask.word.byte 0x0 0.--4. 1. "TGG_PTTRN_0,Pattern for the first toggle loop Error slicer is moved downward by Data tap1 if this pattern is matched" group.word 0x458C++0x1 line.word 0x0 "LANE1_DIG_RX_ADPTCTL_ADPT_CFG_3,Adaptation Configuration Register #3" newline bitfld.word 0x0 15. "ESL_TWICE_DSL,Assert if error slicer has twice the voltage range as the data slicer (for the same 8 bits)." "0,1" newline bitfld.word 0x0 14. "TGG_EN,Enable toggling of the error slicer" "0,1" newline bitfld.word 0x0 13. "EYEHO_EN,Enable eye height measurement using odd error slicer" "0,1" newline bitfld.word 0x0 12. "EYEHE_EN,Enable eye height measurement using even error slicer" "0,1" newline hexmask.word.byte 0x0 7.--11. 1. "DFE_EN,Enable DFE adaptation for taps 5-1" newline bitfld.word 0x0 6. "ATT_EN,Enable ATT adaptation" "0,1" newline bitfld.word 0x0 5. "VGA_EN,Enable VGA adaptation" "0,1" newline hexmask.word.byte 0x0 0.--4. 1. "CTLE_EN,Enable CTLE boost adaptation The five bits determine which correlators are used to adapt the CTLE" repeat 2. (list 0x4 0x5 )(list 0x0 0x4 ) group.word ($2+0x4590)++0x1 line.word 0x0 "LANE1_DIG_RX_ADPTCTL_ADPT_CFG_$1,Adaptation Configuration Register #4" newline hexmask.word.byte 0x0 12.--15. 1. "DFE2_TH,DFE Tap2 correlation decision threshold (2^N-1)" newline hexmask.word.byte 0x0 8.--11. 1. "DFE1_TH,DFE Tap1 correlation decision threshold (2^N-1)" newline hexmask.word.byte 0x0 4.--7. 1. "VGA_TH,VGA correlation decision threshold (2^N-1) During eye height measurement the VGA_TH is repurporsed for error slicer updates." newline hexmask.word.byte 0x0 0.--3. 1. "CTLE_TH,CTLE correlation decision threshold (2^N-1)" repeat.end group.word 0x4598++0x1 line.word 0x0 "LANE1_DIG_RX_ADPTCTL_ADPT_CFG_6,Adaptation Configuration Register #6" newline bitfld.word 0x0 13.--15. "ATT_LOW_TH,ATT low threshold" "0,1,2,3,4,5,6,7" newline bitfld.word 0x0 12. "VGA_SAT_CNT_STICKY,If deasserted then VGA saturation counts must be consecutive to change ATT" "0,1" newline bitfld.word 0x0 9.--11. "VGA_SAT_CNT,VGA saturation count" "0,1,2,3,4,5,6,7" newline bitfld.word 0x0 6.--8. "ATT_MU,ATT gain code update gain (2^N)" "0,1,2,3,4,5,6,7" newline bitfld.word 0x0 3.--5. "VGA_MU,VGA gain code update gain (2^N) During eye height measurement the VGA_MU is repurporsed for error slicer updates." "0,1,2,3,4,5,6,7" newline bitfld.word 0x0 0.--2. "CTLE_MU,CTLE Boost code update gain (2^N)" "0,1,2,3,4,5,6,7" group.word 0x459C++0x1 line.word 0x0 "LANE1_DIG_RX_ADPTCTL_ADPT_CFG_7,Adaptation Configuration Register #7" newline rbitfld.word 0x0 15. "RESERVED_15_15,Reserved for Future use" "0,1" newline hexmask.word.byte 0x0 10.--14. 1. "VGA_LEV_LOW,VGA level low saturation limit" newline hexmask.word.byte 0x0 5.--9. 1. "VGA_LEV_HIGH,VGA level high saturation limit" newline hexmask.word.byte 0x0 0.--4. 1. "VGA_MIN_SAT,VGA minimum saturation limit" group.word 0x45A0++0x1 line.word 0x0 "LANE1_DIG_RX_ADPTCTL_ADPT_CFG_8,Adaptation Configuration Register #8" newline rbitfld.word 0x0 15. "RESERVED_15_15,Reserved for Future use" "0,1" newline bitfld.word 0x0 12.--14. "DFE5_MU,DFE tap5 code update gain (2^N)" "0,1,2,3,4,5,6,7" newline bitfld.word 0x0 9.--11. "DFE4_MU,DFE tap4 code update gain (2^N)" "0,1,2,3,4,5,6,7" newline bitfld.word 0x0 6.--8. "DFE3_MU,DFE tap3 code update gain (2^N)" "0,1,2,3,4,5,6,7" newline bitfld.word 0x0 3.--5. "DFE2_MU,DFE tap2 code update gain (2^N)" "0,1,2,3,4,5,6,7" newline bitfld.word 0x0 0.--2. "DFE1_MU,DFE tap1 code update gain (2^N)" "0,1,2,3,4,5,6,7" group.word 0x45A4++0x1 line.word 0x0 "LANE1_DIG_RX_ADPTCTL_ADPT_CFG_9,Adaptation Configuration Register #9" newline hexmask.word.byte 0x0 8.--15. 1. "ERR_SLO_ADPT_INIT,The error odd slicer is initialized to this value at the start of a new adaptation request." newline hexmask.word.byte 0x0 0.--7. 1. "ERR_SLE_ADPT_INIT,The error even slicer is initialized to this value at the start of a new adaptation request." group.word 0x45A8++0x1 line.word 0x0 "LANE1_DIG_RX_ADPTCTL_RST_ADPT_CFG,Reset Adaptation Configuration Register" newline hexmask.word 0x0 5.--15. 1. "RESERVED_15_5,Reserved for Future use" newline bitfld.word 0x0 4. "RST_ADPT_TAP1,Reset Data Tap1 when turning off DFE adaptation (Taps 2-5 are always turned off when DFE adaptation is turned off)" "0,1" newline bitfld.word 0x0 3. "RST_ADPT_CTLE_POLE,Reset CTLE Pole when turning off AFE adaptation" "0,1" newline bitfld.word 0x0 2. "RST_ADPT_CTLE_BOOST,Reset CTLE Boost when turning off AFE adaptation" "0,1" newline bitfld.word 0x0 1. "RST_ADPT_VGA,Reset VGA when turning off AFE adaptation" "0,1" newline bitfld.word 0x0 0. "RST_ADPT_ATT,Reset ATT when turning off AFE adaptation" "0,1" rgroup.word 0x45AC++0x1 line.word 0x0 "LANE1_DIG_RX_ADPTCTL_ATT_STATUS,Value of ATT Adaptation code" newline hexmask.word.byte 0x0 9.--15. 1. "RESERVED_15_9,Reserved for Future use" newline bitfld.word 0x0 8. "ASM1_DON,Asserts when Adaptation state machine #1 is done" "0,1" newline hexmask.word.byte 0x0 0.--7. 1. "ATT_ADPT_CODE,Value of ATT adaptation code" rgroup.word 0x45B0++0x1 line.word 0x0 "LANE1_DIG_RX_ADPTCTL_VGA_STATUS,Value of VGA Adaptation code" newline hexmask.word.byte 0x0 11.--15. 1. "RESERVED_15_11,Reserved for Future use" newline bitfld.word 0x0 10. "ASM1_DONE,Asserts when Adaptation state machine #1 is done" "0,1" newline hexmask.word 0x0 0.--9. 1. "VGA_ADPT_CODE,Value of VGA adaptation code" rgroup.word 0x45B4++0x1 line.word 0x0 "LANE1_DIG_RX_ADPTCTL_CTLE_STATUS,Value of CTLE Adaptation code" newline bitfld.word 0x0 14.--15. "RESERVED_15_14,Reserved for Future use" "0,1,2,3" newline bitfld.word 0x0 13. "ASM1_DONE,Asserts when Adaptation state machine #1 is done" "0,1" newline bitfld.word 0x0 10.--12. "CTLE_POLE_ADPT_CODE,Value of CTLE Pole adaptation code" "0,1,2,3,4,5,6,7" newline hexmask.word 0x0 0.--9. 1. "CTLE_BOOST_ADPT_CODE,Value of CTLE Boost adaptation code" rgroup.word 0x45B8++0x1 line.word 0x0 "LANE1_DIG_RX_ADPTCTL_DFE_TAP1_STATUS,Value of DFE Tap1 Adaptation code" newline bitfld.word 0x0 14.--15. "RESERVED_15_14,Reserved for Future use" "0,1,2,3" newline bitfld.word 0x0 13. "ASM1_DONE,Asserts when Adaptation state machine #1 is done" "0,1" newline hexmask.word 0x0 0.--12. 1. "DFE_TAP1_ADPT_CODE,Value of DFE tap1 adaptation code" rgroup.word 0x45BC++0x1 line.word 0x0 "LANE1_DIG_RX_ADPTCTL_DFE_TAP2_STATUS,Value of DFE Tap2 Adaptation code" newline bitfld.word 0x0 13.--15. "RESERVED_15_13,Reserved for Future use" "0,1,2,3,4,5,6,7" newline bitfld.word 0x0 12. "ASM1_DONE,Asserts when Adaptation state machine #1 is done" "0,1" newline hexmask.word 0x0 0.--11. 1. "DFE_TAP2_ADPT_CODE,Value of DFE tap2 adaptation code" rgroup.word 0x45C0++0x1 line.word 0x0 "LANE1_DIG_RX_ADPTCTL_DFE_TAP3_STATUS,Value of DFE Tap3 Adaptation code" newline bitfld.word 0x0 13.--15. "RESERVED_15_13,Reserved for Future use" "0,1,2,3,4,5,6,7" newline bitfld.word 0x0 12. "ASM1_DONE,Asserts when Adaptation state machine #1 is done" "0,1" newline hexmask.word 0x0 0.--11. 1. "DFE_TAP3_ADPT_CODE,Value of DFE tap3 adaptation code" rgroup.word 0x45C4++0x1 line.word 0x0 "LANE1_DIG_RX_ADPTCTL_DFE_TAP4_STATUS,Value of DFE Tap4 Adaptation code" newline bitfld.word 0x0 13.--15. "RESERVED_15_13,Reserved for Future use" "0,1,2,3,4,5,6,7" newline bitfld.word 0x0 12. "ASM1_DONE,Asserts when Adaptation state machine #1 is done" "0,1" newline hexmask.word 0x0 0.--11. 1. "DFE_TAP4_ADPT_CODE,Value of DFE tap4 adaptation code" rgroup.word 0x45C8++0x1 line.word 0x0 "LANE1_DIG_RX_ADPTCTL_DFE_TAP5_STATUS,Value of DFE Tap5 Adaptation code" newline bitfld.word 0x0 13.--15. "RESERVED_15_13,Reserved for Future use" "0,1,2,3,4,5,6,7" newline bitfld.word 0x0 12. "ASM1_DONE,Asserts when Adaptation state machine #1 is done" "0,1" newline hexmask.word 0x0 0.--11. 1. "DFE_TAP5_ADPT_CODE,Value of DFE tap5 adaptation code" group.word 0x45CC++0x1 line.word 0x0 "LANE1_DIG_RX_ADPTCTL_DFE_DATA_EVEN_VDAC_OFST,Offset values for RX DFE Data Even vDAC" newline hexmask.word.byte 0x0 8.--15. 1. "RESERVED_15_8,Reserved for Future use" newline hexmask.word.byte 0x0 0.--7. 1. "DFE_DATA_EVEN_VDAC_OFST,Offset value for DFE Data Even vDAC" group.word 0x45D0++0x1 line.word 0x0 "LANE1_DIG_RX_ADPTCTL_DFE_DATA_ODD_VDAC_OFST,Offset values for RX DFE Data Odd vDAC" newline hexmask.word.byte 0x0 8.--15. 1. "RESERVED_15_8,Reserved for Future use" newline hexmask.word.byte 0x0 0.--7. 1. "DFE_DATA_ODD_VDAC_OFST,Offset value for DFE Data Odd vDAC" group.word 0x45D4++0x1 line.word 0x0 "LANE1_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN,Sets values for RX SLICER CTRL EVEN signals going to ANA" newline hexmask.word 0x0 4.--15. 1. "RESERVED_15_4,Reserved for Future use" newline hexmask.word.byte 0x0 0.--3. 1. "RX_ANA_SLICER_CTRL_E,Value for rx_ana_slicer_ctrl_e[3:0]" group.word 0x45D8++0x1 line.word 0x0 "LANE1_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD,Sets values for RX SLICER CTRL ODD signals going to ANA" newline hexmask.word 0x0 4.--15. 1. "RESERVED_15_4,Reserved for Future use" newline hexmask.word.byte 0x0 0.--3. 1. "RX_ANA_SLICER_CTRL_O,Value for rx_ana_slicer_ctrl_o[3:0]" group.word 0x45DC++0x1 line.word 0x0 "LANE1_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST,Offset values for RX DFE Error Even vDAC" newline hexmask.word.byte 0x0 8.--15. 1. "RESERVED_15_8,Reserved for Future use" newline hexmask.word.byte 0x0 0.--7. 1. "DFE_ERROR_EVEN_VDAC_OFST,Offset value for DFE Error Even vDAC" group.word 0x45E0++0x1 line.word 0x0 "LANE1_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST,Offset values for RX DFE Error Odd vDAC" newline hexmask.word.byte 0x0 8.--15. 1. "RESERVED_15_8,Reserved for Future use" newline hexmask.word.byte 0x0 0.--7. 1. "DFE_ERROR_ODD_VDAC_OFST,Offset value for DFE Error Odd vDAC" rgroup.word 0x45E4++0x1 line.word 0x0 "LANE1_DIG_RX_ADPTCTL_ERROR_SLICER_LEVEL,Value of Error Slicer Level" newline hexmask.word.byte 0x0 8.--15. 1. "E_SLE_LVL,Even Error Slicer Level" newline hexmask.word.byte 0x0 0.--7. 1. "E_SLO_LVL,Odd Error Slicer Level" group.word 0x45E8++0x1 line.word 0x0 "LANE1_DIG_RX_ADPTCTL_ADPT_RESET,Adaptation reset register" newline hexmask.word 0x0 1.--15. 1. "RESERVED_15_1,Reserved for Future use" newline bitfld.word 0x0 0. "RESET_ASM1,Resets adaptation state machine (ASM1) as well as the stats capture block. This is a self-clearing bit and requires re-start of ASM1." "0,1" group.word 0x4600++0x1 line.word 0x0 "LANE1_DIG_RX_STAT_LD_VAL_1,Stat load value for the sample counter #1" newline bitfld.word 0x0 15. "SC1_START,Start sample counter #1 This is a self-clearing bit" "0,1" newline hexmask.word 0x0 0.--14. 1. "SC1_LD_VAL,Sample counter #1 load value" group.word 0x4604++0x1 line.word 0x0 "LANE1_DIG_RX_STAT_DATA_MSK,Stat data mask bits [15:0]" newline hexmask.word 0x0 0.--15. 1. "DATA_MSK_15_0,Value of data_msk_r[15:0]" group.word 0x4608++0x1 line.word 0x0 "LANE1_DIG_RX_STAT_MATCH_CTL0,Stat match controls register #0" newline bitfld.word 0x0 14.--15. "SCOPE_DLY,# of clock cycle delays on scope_data_rx_clk An additional MSB is added in SCOPE_DLY_2" "0,1,2,3" newline hexmask.word.byte 0x0 10.--13. 1. "DATA_MSK_19_16,Value of data_msk_r[19:16]" newline hexmask.word.byte 0x0 5.--9. 1. "PTTRN_CR1A_4_0,Value of pattern A for 1st correlator (bits 4:0)" newline hexmask.word.byte 0x0 0.--4. 1. "PTTRN_MSK_CR1A_4_0,Value of pattern A mask for 1st correlator (bits 4:0)" group.word 0x460C++0x1 line.word 0x0 "LANE1_DIG_RX_STAT_MATCH_CTL1,Stat match controls register #1" newline hexmask.word.byte 0x0 12.--15. 1. "RESERVED_15_12,Reserved for Future use" newline bitfld.word 0x0 11. "PTTRN_CR1A_ADPT_EN,Enable ORing of adapation pattern with pattern CR1A" "0,1" newline hexmask.word.byte 0x0 6.--10. 1. "PTTRN_CR1B_4_0,Value of pattern B for 1st correlator (bits 4:0)" newline hexmask.word.byte 0x0 1.--5. 1. "PTTRN_MSK_CR1B_4_0,Value of pattern B mask for 1st correlator (bits 4:0)" newline bitfld.word 0x0 0. "PTTRN_CR1B_EN,Enable pattern B matching for 1st correlator" "0,1" group.word 0x4610++0x1 line.word 0x0 "LANE1_DIG_RX_STAT_STAT_CTL0,Stat controls register #0" newline bitfld.word 0x0 15. "SKIP_EN,Value of skip_en_r" "0,1" newline bitfld.word 0x0 14. "SC_TIMER_MODE,Sample counter operation mode 0x0 - counts number of matched samples 0x1 - counts clock cycles (i.e. a timer)" "counts number of matched samples,counts clock cycles" newline bitfld.word 0x0 13. "STAT_RXCLK_SEL,Select stat clock 0x0 - ref_range_clk 0x1 - rx_dig_clk (i.e. rx dword clk) Before changing stat_rxclk_sel_r from 1->0 the rx_dig_clk must be active (i.e. enabled)" "ref_range_clk,rx_dig_clk" newline bitfld.word 0x0 10.--12. "STAT_SRC_SEL,Select stat source input 0x0 - {20{rx_cal_result}} 0x1 - {{20{scope_data_rxclk_dly_s01}} {20{scope_data_rxclk_dly}}} 0x2 - rx_phase[39:0] 0x3 - rx_error[39:0] 0x4 - rx_data[39:0] 0x5 - rx_phdir[39:0] 0x6 - 40'hFF_FFFF_FFFF" "?,?,rx_phase[39:0],rx_error[39:0],rx_data[39:0],rx_phdir[39:0],?,?" newline hexmask.word.byte 0x0 6.--9. 1. "STAT_SHFT_SEL,Select stat source shift value 0x0 - Correlate N-1 -> N+3 (use N for offset calibration) 0x1 - Correlate N+1 -> N+5 (for taps1-5) 0x2 - Correlate N+6 -> N+10 0x3 - Correlate N+11 -> N+15 0x4 - Correlate N+16 -> N+20 0x5 - Correlate N+21 ->.." newline bitfld.word 0x0 5. "CORR_MODE_EN,Enable correlation mode" "0,1" newline bitfld.word 0x0 3.--4. "CORR_SRC_SEL,Select correlation input source 0x0 - rx_error[39:0] 0x1 - rx_phase[39:0] 0x2 - {{20{scope_data_rxclk_dly_s01}} {20{scope_data_rxclk_dly}}} 0x3 - No correlation" "rx_error[39:0],rx_phase[39:0],?,No correlation" newline bitfld.word 0x0 2. "CORR_SHFT_SEL,Select shift for phase. 0:none 1:>>1" "none,?" newline bitfld.word 0x0 1. "CORR_SHFT_SEL_VGA,Select shift for error going to VGA. 0:none 1:>>1" "none,?" newline bitfld.word 0x0 0. "RESERVED_0,Reserved bit" "0,1" group.word 0x4614++0x1 line.word 0x0 "LANE1_DIG_RX_STAT_STAT_CTL1,Stat controls register #1" newline bitfld.word 0x0 14.--15. "VLD_CTL,Gating configuration of stats collection 0x0 - ignore both cdr_valid and rx_valid 0x1 - gate stats collection with cdr_valid 0x2 - gate stats collection with rx_valid 0x3 - ignore both cdr_valid and rx_valid" "ignore both cdr_valid and rx_valid,gate stats collection with cdr_valid,gate stats collection with rx_valid,ignore both cdr_valid and rx_valid" newline bitfld.word 0x0 13. "VLD_LOSS_CLR,Clearing of stats collection upon loss of valid 0x0 - hold sample and stat counters 0x1 - clear sample and stat counters" "hold sample and stat counters,clear sample and stat counters" newline bitfld.word 0x0 11.--12. "DATA_DLY_SEL,# of clock cycle delays on rx_data[19:0] An additional MSB is added in DATA_DLY_SEL_2" "0,1,2,3" newline bitfld.word 0x0 10. "STAT_CLK_EN,Clock gate enable for stat clock" "0,1" newline bitfld.word 0x0 9. "SC_PAUSE,Pause the sample counter and stat counters" "0,1" newline bitfld.word 0x0 7.--8. "RESERVED_8_7,Reserved bits" "0,1,2,3" newline bitfld.word 0x0 6. "STAT_CNT_6_EN,Enable for stat counter 6" "0,1" newline bitfld.word 0x0 5. "STAT_CNT_5_EN,Enable for stat counter 5" "0,1" newline bitfld.word 0x0 4. "STAT_CNT_4_EN,Enable for stat counter 4" "0,1" newline bitfld.word 0x0 3. "STAT_CNT_3_EN,Enable for stat counter 3 Only counter to be enabled by default since used for offset calibration" "0,1" newline bitfld.word 0x0 2. "STAT_CNT_2_EN,Enable for stat counter 2" "0,1" newline bitfld.word 0x0 1. "STAT_CNT_1_EN,Enable for stat counter 1" "0,1" newline bitfld.word 0x0 0. "STAT_CNT_0_EN,Enable for stat counter 0" "0,1" rgroup.word 0x4618++0x1 line.word 0x0 "LANE1_DIG_RX_STAT_SMPL_CNT1,Sample Counter #1 Status" newline bitfld.word 0x0 15. "SMPL_CNT1_DONE,Status of sample counter #1" "0,1" newline hexmask.word 0x0 0.--14. 1. "SMPL_CNT1,Current value of sample counter #1" rgroup.word 0x461C++0x1 line.word 0x0 "LANE1_DIG_RX_STAT_STAT_CNT_0,Stat Counter 0 Status" newline bitfld.word 0x0 15. "SMPL_CNT1_DONE,Status of sample counter #1" "0,1" newline hexmask.word 0x0 0.--14. 1. "STAT_CNT_0,Current value of stat counter #0" rgroup.word 0x4620++0x1 line.word 0x0 "LANE1_DIG_RX_STAT_STAT_CNT_1,Stat Counter 1 Status" newline bitfld.word 0x0 15. "SMPL_CNT1_DONE,Status of sample counter #1" "0,1" newline hexmask.word 0x0 0.--14. 1. "STAT_CNT_1,Current value of stat counter #1" rgroup.word 0x4624++0x1 line.word 0x0 "LANE1_DIG_RX_STAT_STAT_CNT_2,Stat Counter 2 Status" newline bitfld.word 0x0 15. "SMPL_CNT1_DONE,Status of sample counter #1" "0,1" newline hexmask.word 0x0 0.--14. 1. "STAT_CNT_2,Current value of stat counter #2" rgroup.word 0x4628++0x1 line.word 0x0 "LANE1_DIG_RX_STAT_STAT_CNT_3,Stat Counter 3 Status" newline bitfld.word 0x0 15. "SMPL_CNT1_DONE,Status of sample counter #1" "0,1" newline hexmask.word 0x0 0.--14. 1. "STAT_CNT_3,Current value of stat counter #3" rgroup.word 0x462C++0x1 line.word 0x0 "LANE1_DIG_RX_STAT_STAT_CNT_4,Stat Counter 4 Status" newline bitfld.word 0x0 15. "SMPL_CNT1_DONE,Status of sample counter #1" "0,1" newline hexmask.word 0x0 0.--14. 1. "STAT_CNT_4,Current value of stat counter #4" rgroup.word 0x4630++0x1 line.word 0x0 "LANE1_DIG_RX_STAT_STAT_CNT_5,Stat Counter 5 Status" newline bitfld.word 0x0 15. "SMPL_CNT1_DONE,Status of sample counter #1" "0,1" newline hexmask.word 0x0 0.--14. 1. "STAT_CNT_5,Current value of stat counter #5" rgroup.word 0x4634++0x1 line.word 0x0 "LANE1_DIG_RX_STAT_STAT_CNT_6,Stat Counter 6 Status" newline bitfld.word 0x0 15. "SMPL_CNT1_DONE,Status of sample counter #1" "0,1" newline hexmask.word 0x0 0.--14. 1. "STAT_CNT_6,Current value of stat counter #6" group.word 0x4638++0x1 line.word 0x0 "LANE1_DIG_RX_STAT_CAL_COMP_CLK_CTL,Calibration Comparator Control" newline hexmask.word 0x0 6.--15. 1. "RESERVED_15_6,Reserved for Future use" newline bitfld.word 0x0 3.--5. "REF_DIV_CNT,Ref range clock count (e.g. 5'd3 = 4 ref_range cycles)" "0,1,2,3,4,5,6,7" newline bitfld.word 0x0 0.--2. "PRECHRGE_CNT,Precharge Count (e.g. 5'd1 = 2 ref_range cycles)" "0,1,2,3,4,5,6,7" repeat 4. (list 0x2 0x3 0x4 0x5 )(list 0x0 0x4 0x8 0xC ) group.word ($2+0x463C)++0x1 line.word 0x0 "LANE1_DIG_RX_STAT_MATCH_CTL$1,Stat match controls register #2" newline rbitfld.word 0x0 15. "RESERVED_15_15,Reserved for Future use" "0,1" newline hexmask.word 0x0 0.--14. 1. "PTTRN_CR1A_19_5,Value of pattern A for 1st correlator (bits 19:5)" repeat.end group.word 0x464C++0x1 line.word 0x0 "LANE1_DIG_RX_STAT_STAT_CTL2,Stat controls register #2" newline hexmask.word 0x0 2.--15. 1. "RESERVED_15_2,Reserved for Future use" newline bitfld.word 0x0 1. "SCOPE_DLY_2,Additional MSB bit for SCOPE_DLY to extend the delay range to 0->7" "0,1" newline bitfld.word 0x0 0. "DATA_DLY_SEL_2,Additional MSB bit for DATA_DLY_SEL to extend the delay range to 0->7" "0,1" group.word 0x4650++0x1 line.word 0x0 "LANE1_DIG_RX_STAT_STAT_STOP,Stat stop register" newline hexmask.word 0x0 1.--15. 1. "RESERVED_15_1,Reserved for Future use" newline bitfld.word 0x0 0. "SC1_STOP,Stop sample counters #1 and associated stat counters. This is a self-clearing bit and requires re-start of sample counter #1." "0,1" group.word 0x4680++0x1 line.word 0x0 "LANE1_DIG_ANA_TX_OVRD_OUT,Override values for TX signals going to ANA" newline bitfld.word 0x0 15. "TX_OVRD_EN,Enable override values for all outputs controlled by this register" "0,1" newline bitfld.word 0x0 14. "TX_RXDET_EN,Override value for tx_ana_rxdet_en" "0,1" newline bitfld.word 0x0 13. "TX_DIV4_EN,Override value for tx_ana_div4_en" "0,1" newline bitfld.word 0x0 12. "RESERVED," "0,1" newline bitfld.word 0x0 10.--11. "TX_ANA_DATA_RATE,Override value for tx_ana_data_rate" "0,1,2,3" newline bitfld.word 0x0 9. "TX_ANA_SERIAL_EN,Override value for tx_ana_serial_en" "0,1" newline bitfld.word 0x0 8. "TX_ANA_RESET,Override value for tx_ana_reset" "0,1" newline bitfld.word 0x0 7. "TX_ANA_MPLLB_CLK_EN,Override value for tx_ana_mpllb_clk_en" "0,1" newline bitfld.word 0x0 6. "TX_ANA_MPLLA_CLK_EN,Override value for tx_ana_mplla_clk_en" "0,1" newline bitfld.word 0x0 5. "TX_ANA_WORD_CLK_EN,Override value for tx_ana_word_clk_en" "0,1" newline bitfld.word 0x0 4. "TX_ANA_CLK_EN,Override value for tx_ana_clk_en" "0,1" newline bitfld.word 0x0 3. "TX_ANA_VCM_HOLD,Override value for tx_ana_vcm_hold" "0,1" newline bitfld.word 0x0 2. "TX_ANA_REFGEN_EN,Override value for tx_ana_refgen_en" "0,1" newline bitfld.word 0x0 1. "TX_ANA_DATA_EN,Override value for tx_ana_data_en" "0,1" newline bitfld.word 0x0 0. "TX_ANA_CLK_SHIFT,Override value for tx_ana_clk_shift" "0,1" group.word 0x4684++0x1 line.word 0x0 "LANE1_DIG_ANA_TX_TERM_CODE_OVRD_OUT,Override value for TX termination code going to ANA" newline hexmask.word.byte 0x0 12.--15. 1. "RESERVED_15_12,Reserved for Future use" newline bitfld.word 0x0 11. "TX_CLK_LB_EN,Override value for tx_ana_clk_lb_en (override enabled by TX_OVRD_EN)." "0,1" newline bitfld.word 0x0 10. "TX_TERM_OVRD_EN,Override enable for the tx_ana_term_code[9:0] signal" "0,1" newline hexmask.word 0x0 0.--9. 1. "TX_TERM_CODE,Overrides the tx_ana_term_code[9:0] signal" group.word 0x4688++0x1 line.word 0x0 "LANE1_DIG_ANA_TX_TERM_CODE_CLK_OVRD_OUT,Override value for TX termination code clocks going to ANA" newline hexmask.word 0x0 3.--15. 1. "RESERVED_15_3,Reserved for Future use" newline bitfld.word 0x0 2. "TX_TERM_CLK_SELF_CLEAR_DISABLE,Disable self-clearing for the tx_ana_term_up/dn_clk register" "0,1" newline bitfld.word 0x0 1. "TX_TERM_UP_CLK,Override for TX term UP clock This bit is self-clearing (4 cr_clks later)." "0,1" newline bitfld.word 0x0 0. "TX_TERM_DN_CLK,Override for TX term DN clock - This bit is self_clearing (4 cr_clks later)." "0,1" group.word 0x468C++0x1 line.word 0x0 "LANE1_DIG_ANA_TX_EQ_OVRD_OUT_0,Override values for TX EQ signals going to ANA register #0" newline bitfld.word 0x0 15. "TX_EQ_OVRD_EN,Override enable for tx eq signals" "0,1" newline hexmask.word 0x0 1.--14. 1. "TX_ANA_CTRL_ATTEN_13_0,Override value for tx_ana_ctrl_atten[13:0]" newline bitfld.word 0x0 0. "TX_ANA_LOAD_CLK,Override value for tx_ana_load_clk" "0,1" group.word 0x4690++0x1 line.word 0x0 "LANE1_DIG_ANA_TX_EQ_OVRD_OUT_1,Override values for TX EQ signals going to ANA register #1" newline hexmask.word 0x0 6.--15. 1. "RESERVED_15_6,Reserved for Future use" newline hexmask.word.byte 0x0 0.--5. 1. "TX_ANA_CTRL_ATTEN_19_14,Override value for tx_ana_ctrl_atten[19:14]" group.word 0x4694++0x1 line.word 0x0 "LANE1_DIG_ANA_TX_EQ_OVRD_OUT_2,Override values for TX EQ signals going to ANA register #2" newline rbitfld.word 0x0 13.--15. "RESERVED_15_13,Reserved for Future use" "0,1,2,3,4,5,6,7" newline hexmask.word.byte 0x0 7.--12. 1. "TX_ANA_CTRL_PRE,Override value for tx_ana_ctrl_pre[5:0]" newline hexmask.word.byte 0x0 0.--6. 1. "RESERVED," group.word 0x4698++0x1 line.word 0x0 "LANE1_DIG_ANA_TX_EQ_OVRD_OUT_3,Override values for TX EQ signals going to ANA register #3" newline hexmask.word.byte 0x0 8.--15. 1. "RESERVED_15_8,Reserved for Future use" newline hexmask.word.byte 0x0 0.--7. 1. "TX_ANA_CTRL_POST,Override value for tx_ana_ctrl_post[7:0]" group.word 0x469C++0x1 line.word 0x0 "LANE1_DIG_ANA_RX_CTL_OVRD_OUT,Override values for RX control signals going to ANA" newline hexmask.word.byte 0x0 9.--15. 1. "RESERVED_15_9,Reserved for Future use" newline bitfld.word 0x0 8. "RX_CTL_OVRD_EN,Enable override values for outputs [8-0] below" "0,1" newline bitfld.word 0x0 7. "RX_LBK_CLK_EN,Override value for rx_ana_loopback_clk_en" "0,1" newline bitfld.word 0x0 6. "RX_ANA_ADAPTATION_EN,Override value for rx_ana_adaptation_en" "0,1" newline bitfld.word 0x0 5. "RX_ANA_DFE_TAPS_EN,Override value for rx_ana_dfe_taps_en" "0,1" newline bitfld.word 0x0 4. "RX_ANA_DIV4_EN,Override value for rx_ana_div4_en" "0,1" newline bitfld.word 0x0 3. "RX_ANA_WORD_CLK_EN,Override value for rx_ana_word_clk_en" "0,1" newline bitfld.word 0x0 1.--2. "RX_ANA_DATA_RATE,Override value for rx_ana_data_rate" "0,1,2,3" newline bitfld.word 0x0 0. "RESERVED," "0,1" group.word 0x46A0++0x1 line.word 0x0 "LANE1_DIG_ANA_RX_PWR_OVRD_OUT,Override values for RX PWR UP/DN signals going to ANA" newline hexmask.word.byte 0x0 8.--15. 1. "RESERVED_15_8,Reserved for Future use" newline bitfld.word 0x0 7. "RX_PWR_OVRD_EN,Enable override values for all outputs controlled by this register" "0,1" newline bitfld.word 0x0 6. "RX_ANA_DESERIAL_EN,Override value for rx_ana_deserial_en" "0,1" newline bitfld.word 0x0 5. "RX_ANA_CDR_EN,Override value for rx_ana_cdr_en" "0,1" newline bitfld.word 0x0 4. "RX_ANA_CLK_EN,Override value for rx_ana_clk_en" "0,1" newline bitfld.word 0x0 3. "RX_ANA_CLK_DCC_EN,Override value for rx_ana_clk_dcc_en" "0,1" newline bitfld.word 0x0 2. "RX_ANA_CLK_VREG_EN,Override value for rx_ana_clk_vreg_en" "0,1" newline bitfld.word 0x0 1. "RX_ANA_AFE_EN,Override value for rx_ana_afe_en" "0,1" newline bitfld.word 0x0 0. "RX_ANA_LOS_EN,Override value for rx_ana_los_en" "0,1" group.word 0x46A4++0x1 line.word 0x0 "LANE1_DIG_ANA_RX_VCO_OVRD_OUT_0,Override values for RX VCO signals going to ANA #0" newline bitfld.word 0x0 15. "RX_CDR_FREQ_TUNE_OVRD_EN,Enable override value for rx_ana_cdr_freq_tune" "0,1" newline bitfld.word 0x0 14. "RX_ANA_VCO_CNTR_CLK,Override value for rx_ana_vco_cntr_clk" "0,1" newline bitfld.word 0x0 13. "RX_ANA_VCO_CNTR_EN,Override value for rx_ana_vco_cntr_en" "0,1" newline hexmask.word 0x0 3.--12. 1. "RX_ANA_CDR_FREQ_TUNE,Override value for rx_ana_cdr_freq_tune" newline bitfld.word 0x0 2. "RX_VCO_CDR_OVRD_EN,Enable override values for cdr_vco_en and cdr_startup" "0,1" newline bitfld.word 0x0 1. "RX_ANA_CDR_STARTUP,Override value for rx_ana_cdr_startup" "0,1" newline bitfld.word 0x0 0. "RX_ANA_CDR_VCO_EN,Override value for rx_ana_cdr_vco_en" "0,1" repeat 2. (list 0x1 0x2 )(list 0x0 0x4 ) group.word ($2+0x46A8)++0x1 line.word 0x0 "LANE1_DIG_ANA_RX_VCO_OVRD_OUT_$1,Override values for RX VCO signals going to ANA #1" newline hexmask.word 0x0 2.--15. 1. "RESERVED_15_2,Reserved for Future use" newline bitfld.word 0x0 1. "RX_ANA_VCO_CNTR_PD,Override value for rx_ana_vco_cntr_pd" "0,1" newline bitfld.word 0x0 0. "RX_ANA_CDR_VCO_LOWFREQ,Override value for rx_ana_cdr_vco_lowfreq" "0,1" repeat.end group.word 0x46B0++0x1 line.word 0x0 "LANE1_DIG_ANA_RX_CAL,Sets values for RX CAL signals going to ANA register" newline bitfld.word 0x0 15. "RX_ANA_CAL_COMP_EN,Value for rx_ana_cal_comp_en" "0,1" newline bitfld.word 0x0 13.--14. "RX_ANA_CAL_MODE,Value for rx_ana_cal_mode[1:0] 00 Dual differential comparison ( [vip2 - vim2] greater than [vip1 - vim1] ) 01 Differential comparison on input2 (vip2 greater than vim2) 10 Single-ended comparison negative node to negative node (vim1.." "?,?,vim2] greater than [vip1,?" newline bitfld.word 0x0 12. "RX_ANA_SLICER_CAL_EN,Value for rx_ana_slicer_cal_en" "0,1" newline bitfld.word 0x0 11. "RESERVED," "0,1" newline bitfld.word 0x0 10. "RX_ANA_CAL_LPFBYP_EN,Value for rx_ana_cal_lpfbyp_en" "0,1" newline hexmask.word.byte 0x0 5.--9. 1. "RX_ANA_CAL_MUXB_SEL,Value for rx_ana_cal_muxb_sel[4:0]" newline hexmask.word.byte 0x0 0.--4. 1. "RX_ANA_CAL_MUXA_SEL,Value for rx_ana_cal_muxa_sel[4:0]" group.word 0x46B4++0x1 line.word 0x0 "LANE1_DIG_ANA_RX_DAC_CTRL,Sets values for RX DAC CTRL value going to ANA" newline hexmask.word.byte 0x0 8.--15. 1. "RESERVED_15_8,Reserved for Future use" newline hexmask.word.byte 0x0 0.--7. 1. "RX_ANA_CAL_DAC_CTRL,Value for rx_ana_cal_dac_ctrl[7:0]" group.word 0x46B8++0x1 line.word 0x0 "LANE1_DIG_ANA_RX_DAC_CTRL_OVRD,Overrides RX DAC CTRL bus (en/val/sel) going to ANA" newline hexmask.word 0x0 1.--15. 1. "RESERVED_15_1,Reserved for Future use" newline bitfld.word 0x0 0. "RX_CAL_DAC_CTRL_OVRD,Override enable for Cal DAC control" "0,1" group.word 0x46BC++0x1 line.word 0x0 "LANE1_DIG_ANA_RX_DAC_CTRL_SEL,Sets values for RX DAC CTRL Select signal going to ANA" newline hexmask.word 0x0 5.--15. 1. "RESERVED_15_5,Reserved for Future use" newline hexmask.word.byte 0x0 0.--4. 1. "RX_ANA_CAL_DAC_CTRL_SEL,Value for rx_ana_cal_dac_ctrl_sel[4:0]" group.word 0x46C0++0x1 line.word 0x0 "LANE1_DIG_ANA_RX_AFE_ATT_VGA,Value for RX AFE ATT & VGA signals going to ANA" newline hexmask.word.byte 0x0 12.--15. 1. "RESERVED_15_12,Reserved for Future use" newline bitfld.word 0x0 11. "RX_AFE_OVRD_EN,Override enable for AFE control" "0,1" newline hexmask.word.byte 0x0 7.--10. 1. "RESERVED," newline hexmask.word.byte 0x0 3.--6. 1. "RX_ANA_AFE_GAIN,Value for rx_ana_afe_gain[3:0]" newline bitfld.word 0x0 0.--2. "RX_ANA_AFE_ATT_LVL,Value for rx_ana_afe_att_lvl[2:0]" "0,1,2,3,4,5,6,7" group.word 0x46C4++0x1 line.word 0x0 "LANE1_DIG_ANA_RX_AFE_CTLE,Values for RX AFE CTLE signals going to ANA" newline hexmask.word.byte 0x0 8.--15. 1. "RESERVED_15_8,Reserved for Future use" newline hexmask.word.byte 0x0 3.--7. 1. "RX_ANA_AFE_CTLE_BOOST,Value for rx_ana_afe_ctle_boost[4:0]" newline bitfld.word 0x0 0.--2. "RESERVED," "0,1,2,3,4,5,6,7" group.word 0x46C8++0x1 line.word 0x0 "LANE1_DIG_ANA_RX_SCOPE,Values for RX SCOPE signals going to ANA" newline rbitfld.word 0x0 14.--15. "RESERVED_15_14,Reserved for Future use" "0,1,2,3" newline bitfld.word 0x0 13. "RX_SCOPE_SELF_CLEAR_DISABLE,Disable the self-clearing for rx_ana_scope_ph_clk register" "0,1" newline bitfld.word 0x0 12. "RX_ANA_SCOPE_CLK_EN,Enable the scope clocks going to the scope slicer and the lane digital part" "0,1" newline hexmask.word.byte 0x0 4.--11. 1. "RX_ANA_SCOPE_PHASE,Sets value for rx_ana_scope_phase[7:0]" newline bitfld.word 0x0 3. "RX_ANA_SCOPE_PH_CLK,Sets value for rx_ana_scope_ph_clk - This bit is self-clearing (i.e. only asserts for one cr_clk cycle)" "0,1" newline bitfld.word 0x0 1.--2. "RX_ANA_SCOPE_SEL,Sets value for rx_ana_scope_sel 00 - AFE scope selected 01 - DFE even scope selected 10 - DFE odd scope selected 11 - DFE bypass/AFE buffer scope selected" "AFE scope selected,DFE even scope selected,?,?" newline bitfld.word 0x0 0. "RX_ANA_SCOPE_EN,Sets value for rx_ana_scope_en" "0,1" group.word 0x46CC++0x1 line.word 0x0 "LANE1_DIG_ANA_RX_SLICER_CTRL,Sets values for RX Slicer Ctrl signals going to ANA register" newline hexmask.word.byte 0x0 9.--15. 1. "RESERVED_15_9,Reserved for Future use" newline bitfld.word 0x0 8. "RX_ANA_SLICER_CTRL_OVRD_EN,Override enable for Rx ANA Slicer Ctrl" "0,1" newline hexmask.word.byte 0x0 4.--7. 1. "RX_ANA_SLICER_CTRL_O,Value for rx_ana_slicer_ctrl_o[3:0]" newline hexmask.word.byte 0x0 0.--3. 1. "RX_ANA_SLICER_CTRL_E,Value for rx_ana_slicer_ctrl_e[3:0]" group.word 0x46D0++0x1 line.word 0x0 "LANE1_DIG_ANA_RX_ANA_IQ_PHASE_ADJUST,Sets values for RX ANA IQ PHASE Adjust signal going to ANA register" newline hexmask.word 0x0 7.--15. 1. "RESERVED_15_7,Reserved for Future use" newline hexmask.word.byte 0x0 0.--6. 1. "RX_ANA_IQ_PHASE_ADJUST,Value for rx_ana_iq_phase_adjust[6:0]" group.word 0x46D4++0x1 line.word 0x0 "LANE1_DIG_ANA_RX_ANA_IQ_SENSE_EN,Sets values for RX ANA IQ SENSE signal" newline hexmask.word 0x0 1.--15. 1. "RESERVED_15_1,Reserved for Future use" newline bitfld.word 0x0 0. "RX_ANA_IQ_SENSE_EN,Value for rx_ana_iq_sense_en" "0,1" group.word 0x46D8++0x1 line.word 0x0 "LANE1_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN,DAC CTRL enable signal" newline hexmask.word 0x0 2.--15. 1. "RESERVED_15_2,Reserved for Future use" newline bitfld.word 0x0 1. "DAC_CTRL_SELF_CLEAR_DISABLE,Disable self-clearing for the rx_ana_cal_dac_ctrl_en register" "0,1" newline bitfld.word 0x0 0. "RX_ANA_CAL_DAC_CTRL_EN,Value for rx_ana_cal_dac_ctrl_en - If DAC_CTRL_SELF_CLEAR_DISABLE=0 then this bit is self-clearing (i.e. only asserts for one cr_clk cycle)" "0,1" group.word 0x46DC++0x1 line.word 0x0 "LANE1_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE,Afe update enable signal" newline hexmask.word 0x0 2.--15. 1. "RESERVED_15_2,Reserved for Future use" newline bitfld.word 0x0 1. "AFE_UPDATE_SELF_CLEAR_DISABLE,Disable self-clearing for the rx_ana_afe_update_en register" "0,1" newline bitfld.word 0x0 0. "RX_ANA_AFE_UPDATE_EN,Value for rx_ana_afe_update_en - If AFE_UPDATE_SELF_CLEAR_DISABLE=0 then this bit is self-clearing (i.e. only asserts for one cr_clk cycle)" "0,1" group.word 0x46E0++0x1 line.word 0x0 "LANE1_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK,Phase adjust clock signal" newline hexmask.word 0x0 2.--15. 1. "RESERVED_15_2,Reserved for Future use" newline bitfld.word 0x0 1. "PHASE_ADJUST_SELF_CLEAR_DISABLE,Disable self-clearing for the rx_ana_iq_phase_adjust_clk register" "0,1" newline bitfld.word 0x0 0. "RX_ANA_IQ_PHASE_ADJUST_CLK,Value for rx_ana_iq_phase_adjust_clk - If PHASE_ADJUST_SELF_CLEAR_DISABLE=0 then this bit is self-clearing (i.e. only asserts for one cr_clk cycle)" "0,1" rgroup.word 0x46E4++0x1 line.word 0x0 "LANE1_DIG_ANA_STATUS_0,Lane input status register #0" newline hexmask.word.byte 0x0 8.--15. 1. "RESERVED_15_8,Reserved for Future use" newline bitfld.word 0x0 7. "RX_ANA_SCOPE_DATA,Value from ANA for rx_ana_scope_data" "0,1" newline bitfld.word 0x0 6. "RX_ANA_CAL_RESULT,Value from ANA for rx_ana_cal_result" "0,1" newline bitfld.word 0x0 5. "RX_ANA_LOS,Value from ANA for rx_ana_los" "0,1" newline bitfld.word 0x0 4. "TX_ANA_CLK_LB_EN,Value of tx_ana_clk_lb_en" "0,1" newline bitfld.word 0x0 3. "TX_ANA_LOOPBACK_EN,Value of tx_ana_loopback_en" "0,1" newline bitfld.word 0x0 2. "TX_ANA_RXDETM_RESULT,Value from ANA for tx_ana_rxdetm_result" "0,1" newline bitfld.word 0x0 1. "TX_ANA_RXDETP_RESULT,Value from ANA for tx_ana_rxdetp_result" "0,1" newline bitfld.word 0x0 0. "TX_ANA_CLK_SHIFT_ACK,Value from ANA for tx_ana_clk_shift_ack" "0,1" rgroup.word 0x46E8++0x1 line.word 0x0 "LANE1_DIG_ANA_STATUS_1,Lane input status register #1" newline bitfld.word 0x0 13.--15. "RESERVED_15_13,Reserved for Future use" "0,1,2,3,4,5,6,7" newline hexmask.word 0x0 0.--12. 1. "RX_ANA_VCO_CNTR,Value from ANA for rx_ana_vco_cntr" group.word 0x46EC++0x1 line.word 0x0 "LANE1_DIG_ANA_RX_TERM_CODE_OVRD_OUT,Override value for RX termination code going to ANA" newline hexmask.word 0x0 7.--15. 1. "RESERVED_15_7,Reserved for Future use" newline bitfld.word 0x0 6. "RX_TERM_OVRD_EN,Override enable for the rx_ana_term_code[5:0] signal" "0,1" newline hexmask.word.byte 0x0 0.--5. 1. "RX_TERM_CODE,Overrides the rx_ana_term_code[5:0] signal" group.word 0x46F0++0x1 line.word 0x0 "LANE1_DIG_ANA_RX_TERM_CODE_CLK_OVRD_OUT,Override value for RX termination code clock going to ANA" newline hexmask.word 0x0 2.--15. 1. "RESERVED_15_2,Reserved for Future use" newline bitfld.word 0x0 1. "RX_TERM_CLK_SELF_CLEAR_DISABLE,Disable the self-clearing of rx_ana_term_clk register" "0,1" newline bitfld.word 0x0 0. "RX_TERM_CLK,Override for TX term DN clock - This bit is self_clearing (4 cr_clks later)." "0,1" group.word 0x4700++0x1 line.word 0x0 "LANE1_ANA_TX_OVRD_MEAS,TX_OVRD_MEAS" newline hexmask.word.byte 0x0 8.--15. 1. "RESERVED_15_8,Reserved for Future use" newline bitfld.word 0x0 7. "PULL_DN_REG,Pull down TX output if asserted" "0,1" newline bitfld.word 0x0 6. "PULL_UP_REG,Pull up TX output if asserted" "0,1" newline bitfld.word 0x0 5. "VCM_HOLD_REG,Set Tx in common mode if asserted together with bit 4" "0,1" newline bitfld.word 0x0 4. "OVRD_VCM_HOLD,If asserted bit 5 take effect on control Tx common mode" "0,1" newline bitfld.word 0x0 3. "MEAS_SAMP_P,Measure clock p DCD through atb_s_p on clock psample" "0,1" newline bitfld.word 0x0 2. "MEAS_SAMP_M,Measure clock m DCD through atb_s_p on clock m sample" "0,1" newline bitfld.word 0x0 1. "CLK_SHIFT_REG,Controls clock shift if asserted with bit 0" "0,1" newline bitfld.word 0x0 0. "OVRD_CLK_SHIFT,If asserted allow analog register to control clock shift function" "0,1" group.word 0x4704++0x1 line.word 0x0 "LANE1_ANA_TX_PWR_OVRD,TX_PWR_OVRD" newline hexmask.word.byte 0x0 8.--15. 1. "RESERVED_15_8,Reserved for Future use" newline bitfld.word 0x0 7. "OVRD_EN,Enable analog register to take control TX power state if asserted" "0,1" newline bitfld.word 0x0 6. "SERIAL_EN_REG,Enable TX serializer if assered with bit 7" "0,1" newline bitfld.word 0x0 5. "CLK_EN_REG,Enable TX clock if asserted with bit 7" "0,1" newline bitfld.word 0x0 4. "DATA_EN_REG,Enable TX driver data path if asserted with bit 7" "0,1" newline bitfld.word 0x0 3. "CLK_DIV_EN_REG,Enable TX divider if asserted with bit 7 overrides !tx_reset" "0,1" newline bitfld.word 0x0 2. "REFGEN_EN_REG,Enable TX biasing if asserted with bit 7" "0,1" newline bitfld.word 0x0 1. "LOOPBACK_EN_REG,Enable TX loopback path to RX if asserted along with bit 0" "0,1" newline bitfld.word 0x0 0. "OVRD_TX_LOOPBACK,Enable Tx loopback mode over ridden by analog register if asserted" "0,1" group.word 0x4708++0x1 line.word 0x0 "LANE1_ANA_TX_ALT_BUS,TX_ALT_BUS" newline hexmask.word.byte 0x0 8.--15. 1. "RESERVED_15_8,Reserved for Future use" newline bitfld.word 0x0 7. "JTAG_DATA_REG,When bit 2 is asserted it replace jtag data" "0,1" newline bitfld.word 0x0 4.--6. "TX_ALT_RINGO,Three bit select of the ALT path test oscillators 000 no oscillators enabled 001 osc_vp_ulvt oscillator enabled 010 osc_vptx_lvt oscillator enabled 011 osc_vp_lvt oscillator enabled 100 Reserved 101 Reserved 110 Reserved 111 osc_vph_hv.." "0,1,2,3,4,5,6,7" newline bitfld.word 0x0 3. "NC3,Reserved" "0,1" newline bitfld.word 0x0 2. "OVRD_ALT_BUS,If asserted jtag data and TX data source selection are controlled by bits [1:0] and bit 7" "0,1" newline bitfld.word 0x0 0.--1. "DRV_SOURCE_REG,When bit 2 is asserted drv_source_reg[1:0] takes control of TX function overrides tx_data_source[1:0]" "0,1,2,3" repeat 2. (list 0x1 0x2 )(list 0x0 0x4 ) group.word ($2+0x470C)++0x1 line.word 0x0 "LANE1_ANA_TX_ATB$1,TX_ATB1" newline hexmask.word.byte 0x0 8.--15. 1. "RESERVED_15_8,Reserved for Future use" newline bitfld.word 0x0 7. "NC7,Reserved" "0,1" newline bitfld.word 0x0 6. "ATB_VREG1,Put TX regulator 1 output on atb_s_p when asserted" "0,1" newline bitfld.word 0x0 5. "ATB_VREG0,Put TX regulator 0 output on atb_s_p when asserted" "0,1" newline bitfld.word 0x0 4. "OVERRIDE_REGREF_0,Use atb_s_m as TX regulator 0 reference voltage when asserted" "0,1" newline bitfld.word 0x0 3. "ATB_VPTX,Put TX driver local vptx on atb_s_p when asserted" "0,1" newline bitfld.word 0x0 2. "ATB_VDCCP,Put DCC control voltage p on atb_s_p when asserted" "0,1" newline bitfld.word 0x0 1. "ATB_VDCCM,Put DCC control voltage m on atb_s_p when asserted" "0,1" newline bitfld.word 0x0 0. "ATB_GD,Put tx local gd on atb_s_p when asserted" "0,1" repeat.end group.word 0x4714++0x1 line.word 0x0 "LANE1_ANA_TX_VBOOST,TX_VBOOST" newline hexmask.word.byte 0x0 8.--15. 1. "RESERVED_15_8,Reserved for Future use" newline bitfld.word 0x0 7. "OVRD_VBOOST_EN,Enable TX boost mode to be override by bit 6" "0,1" newline bitfld.word 0x0 6. "VBOOST_EN_REG,If bit 7 is set to 1 analog register takes control of Tx vboost enable/disable" "0,1" newline bitfld.word 0x0 5. "BOOST_VPTX_MODE_N,If asserted TX boost mode becomes a direct boost mode. VdIffpp=vptx+0.05*(2.5*(1+iboost_code)*(2*tx_vboost_vref) in default TX boost mode" "0,1" newline bitfld.word 0x0 4. "ATB_VBOOST,Measure vptx/2 through atb_s_p when TX boost is enabled" "0,1" newline bitfld.word 0x0 3. "ATB_VBOOST_VREF,Measure tx boost reference voltage through atb_s_p" "0,1" newline bitfld.word 0x0 2. "OVERRIDE_VREF_BOOST_REF,If enabled atb_s_m is used to provide Tx boost reference voltage instead of bandgap voltage tx_vboost_vref" "0,1" newline bitfld.word 0x0 1. "ATB_S_ENABLE,Enables TX atb function if asserted This bit has to be set to 1 in order to make TX atb_s_p/m visible" "0,1" newline bitfld.word 0x0 0. "MEAS_ATB_VPH_HALF,Measure vph/2 on atb_s_p" "0,1" group.word 0x4718++0x1 line.word 0x0 "LANE1_ANA_TX_TERM_CODE,TX_TERM_CODE" newline hexmask.word.byte 0x0 8.--15. 1. "RESERVED_15_8,Reserved for Future use" newline hexmask.word.byte 0x0 1.--7. 1. "TERM_CODE_REG,TX leg biasing register (7 MSBs) this is Term_code_reg[9:3]" newline bitfld.word 0x0 0. "TERM_CODE_OVRD,Enable analog register to overdrive TX leg biasing" "0,1" group.word 0x471C++0x1 line.word 0x0 "LANE1_ANA_TX_TERM_CODE_CTRL,TX_TERM_CODE_CTRL" newline hexmask.word.byte 0x0 8.--15. 1. "RESERVED_15_8,Reserved for Future use" newline bitfld.word 0x0 7. "RESET_TERM_REG,Resets the tx termination code DACs" "0,1" newline bitfld.word 0x0 6. "RESET_TERM_OVRD,Enable analog register to reset termination code DACs" "0,1" newline bitfld.word 0x0 5. "UPDATE_TERM_UP_REG,Register control to update the pullup TX terminations" "0,1" newline bitfld.word 0x0 4. "UPDATE_TERM_UP_OVRD,Enables analog register control to update the pullup TX terminations" "0,1" newline bitfld.word 0x0 3. "UPDATE_TERM_DN_REG,Register control to update the pulldown TX terminations" "0,1" newline bitfld.word 0x0 2. "UPDATE_TERM_DN_OVRD,Enables analog register control to update the pulldown TX terminations" "0,1" newline bitfld.word 0x0 1. "TX_PWR_EN_REG,Register control over the power gating of blocks within the TX" "0,1" newline bitfld.word 0x0 0. "TX_PWR_EN_OVRD,Enables analog register control over the power gating of blocks within the TX" "0,1" group.word 0x4720++0x1 line.word 0x0 "LANE1_ANA_TX_IBOOST_CODE,TX_IBOOST_CODE" newline hexmask.word.byte 0x0 8.--15. 1. "RESERVED_15_8,Reserved for Future use" newline hexmask.word.byte 0x0 4.--7. 1. "IBOOST_CODE_REG,When TX boost is enabled and bit 3 is asserted these 4 bits take control of TX boost. VdIffpp=vptx+0.05*(2.5*(1+iboost_code)*(2*tx_vboost_vref-vptx/2) in default TX boost mode" newline bitfld.word 0x0 3. "IBOOST_CODE_OVRD,Enable analog register overdrive for TX boost" "0,1" newline bitfld.word 0x0 1.--2. "TERM_CODE_REG,TX leg biasing register bit 2 & 1 this is term_code_reg[2:1]" "0,1,2,3" newline bitfld.word 0x0 0. "LFPS_HIGH_PRIORITY,If asserted lfps/beacon enable has higher priority than data enable" "0,1" group.word 0x4724++0x1 line.word 0x0 "LANE1_ANA_TX_OVRD_CLK,TX_OVRD_CLK" newline hexmask.word.byte 0x0 8.--15. 1. "RESERVED_15_8,Reserved for Future use" newline bitfld.word 0x0 7. "OVRD_WORD_CLK_EN,If asserted it allows bit 6 to override tx word clock enable" "0,1" newline bitfld.word 0x0 6. "WORD_CLK_EN_REG,Tx word clock enable/disable when bit 7 is asserted" "0,1" newline bitfld.word 0x0 5. "OVRD_MPLLAB_EN,If asserted it allows bit 3 or 4 to take control of selecting MPLL clocks" "0,1" newline bitfld.word 0x0 4. "MPLLA_CLK_EN_REG,When asserted with bit 5 selects MPLLA clock as TX data output clock Only bit 3 or bit 4 or bit 1 can be asserted" "0,1" newline bitfld.word 0x0 3. "MPLLB_CLK_EN_REG,When asserted with bit 5 selects MPLLB clock as TX data output clock Only bit 3 or bit 4 or bit 1 can be asserted" "0,1" newline bitfld.word 0x0 2. "OVRD_LB_EN,If asserted it allows bit 1 takes control of RX clock loopback to TX" "0,1" newline bitfld.word 0x0 1. "CLK_LB_EN_REG,When asserted with bit 2 selects RX clock for TX data output clock" "0,1" newline bitfld.word 0x0 0. "OVERRIDE_REGREF_1,Use atb_s_m to over ride TX regulator reference voltage when asserted" "0,1" group.word 0x4728++0x1 line.word 0x0 "LANE1_ANA_TX_MISC,TX_MISC" newline hexmask.word.byte 0x0 8.--15. 1. "RESERVED_15_8,Reserved for Future use" newline bitfld.word 0x0 7. "OVERRIDE_RXDETREF,If asserted atb_s_m is used to override RX detection reference voltage" "0,1" newline bitfld.word 0x0 6. "MEAS_ATB_BIAS_VPTX,Measure TX bias local vptx through atb_s_p when asserted" "0,1" newline bitfld.word 0x0 5. "OSC_DIV4_EN,If asserted divides tx_alt oscillator output frequency by 4" "0,1" newline hexmask.word.byte 0x0 0.--4. 1. "NC4_0,Reserved" group.word 0x472C++0x1 line.word 0x0 "LANE1_ANA_RX_ATB_IQSKEW,RX_ATB_IQSKEW" newline hexmask.word.byte 0x0 8.--15. 1. "RESERVED_15_8,Reserved for Future use" newline bitfld.word 0x0 7. "MASTER_ATB_EN,If asserted enable RX ATB sensing bus atb_s_p/m visible externally.The exception is bit 5 which dont require this bit to be asserted" "0,1" newline bitfld.word 0x0 6. "MEAS_ATB_RX_SCOPE_REG,If asserted enable scope linearity characterization through atb_s_p/m" "0,1" newline bitfld.word 0x0 5. "MEAS_ATB_VP,If asserted vp is measured through atb_s_p" "0,1" newline hexmask.word.byte 0x0 0.--4. 1. "IQ_PHASE_ADJUST_REG,If ovrd_iq_phase_adjust is enabled these bits control the main PMIX" group.word 0x4730++0x1 line.word 0x0 "LANE1_ANA_RX_DCC_OVRD,RX_DCC_OVRD" newline hexmask.word.byte 0x0 8.--15. 1. "RESERVED_15_8,Reserved for Future use" newline bitfld.word 0x0 7. "DCC_EN_REG,When bit 6 is asserted this bit takes control of RX DCC enable" "0,1" newline bitfld.word 0x0 6. "OVRD_DCCANDAFE_EN,When asserted override RX DCC enable by analog register" "0,1" newline bitfld.word 0x0 5. "RX_LOOPBACK_CLK_REG,When bit 4 asserted this bit takes control of RX clock loopback enable/disable" "0,1" newline bitfld.word 0x0 4. "OVRD_RX_LOOPBACK_CLK,When asserted override rx clock loopback by analog register" "0,1" newline bitfld.word 0x0 2.--3. "MEAS_ATB_VDCC,meas_atb_vdcc[1:0] 00 Disable atb measurement 01 measure vdcc_i_p/m through atb_s_p/m 10 measure vdcc_q_p/m through atb_s_p/m 11 measure vdcc_i/q through atb_s_p/m" "0,1,2,3" newline bitfld.word 0x0 0.--1. "NC1_0,Reserved" "0,1,2,3" repeat 2. (list 0x1 0x2 )(list 0x0 0xC ) group.word ($2+0x4734)++0x1 line.word 0x0 "LANE1_ANA_RX_PWR_CTRL$1,RX_PWR_CTRL1" newline hexmask.word.byte 0x0 8.--15. 1. "RESERVED_15_8,Reserved for Future use" newline bitfld.word 0x0 7. "AFE_EN_REG,When asserted with bit 6 enables AFE" "0,1" newline bitfld.word 0x0 6. "OVRD_AFE_EN,If asserted bit 7 take control of AFE enable/disable" "0,1" newline bitfld.word 0x0 5. "LOS_EN_REG,When asserted with bit 4 enables LOS" "0,1" newline bitfld.word 0x0 4. "OVRD_LOS_EN,If asserted bit 5 take control of LOS enable/disable" "0,1" newline bitfld.word 0x0 3. "CLK_EN_REG,When asserted with bit 2 enables RX clock" "0,1" newline bitfld.word 0x0 2. "OVRD_CLK_EN,If asserted bit 3 take control of RX clock enable/disable" "0,1" newline bitfld.word 0x0 1. "ACJT_EN_REG,When asserted with bit 0 enables ACJTAG" "0,1" newline bitfld.word 0x0 0. "OVRD_ACJT_EN,If asserted bit 1 take control of ACJTAG enable/disable" "0,1" repeat.end group.word 0x4738++0x1 line.word 0x0 "LANE1_ANA_RX_ATB_REGREF,RX_ATB_REGREF" newline hexmask.word.byte 0x0 8.--15. 1. "RESERVED_15_8,Reserved for Future use" newline bitfld.word 0x0 5.--7. "MEAS_ATB_CAL_MUX,Meas_atb_cal_mux is 3 bit signal Meas_atb_cal_mux[2:0] If Meas_atb_cal_mux[2] asserted RX offset calibration comparator first stage differential outputs are measured through atb_s_p/m If Meas_atb_cal_mux[1] asserted atb_s_p/m.." "0,1,2,3,4,5,6,7" newline bitfld.word 0x0 4. "OVERRIDE_REGREF_CLK,If asserted RX clock regulator reference is overridden through atb_s_m" "0,1" newline bitfld.word 0x0 3. "OVERRIDE_REGREF_SCOPE,If asserted RX scope regulator reference is overridden through atb_s_m" "0,1" newline bitfld.word 0x0 2. "NC2,Reserved" "0,1" newline bitfld.word 0x0 0.--1. "MEAS_ATB_SAMP,meas_atb_samp[1:0] 00 Disable atb measurement 01 measure clk_i_p/m sampling node through atb_s_p/m 10 measure clk_q_p/m sampling node through atb_s_p/m 11 measure clk_i/q sampling node through atb_s_p/m" "0,1,2,3" group.word 0x473C++0x1 line.word 0x0 "LANE1_ANA_RX_CDR_AFE,RX_CDR_AFE" newline hexmask.word.byte 0x0 8.--15. 1. "RESERVED_15_8,Reserved for Future use" newline bitfld.word 0x0 6.--7. "NC7_6,Reserved" "0,1,2,3" newline bitfld.word 0x0 5. "PHDET_EVEN_REG,If asserted CDR phase detector uses even data path" "0,1" newline bitfld.word 0x0 4. "PHDET_ODD_REG,If asserted CDR phase detector uses odd data path" "0,1" newline hexmask.word.byte 0x0 0.--3. 1. "MEAS_ATB_RX,This is meas_atb_rx[9:6] bit each bit correspond to ==> meas_atb_rx[9] If asserted AFE biasing vbp is measured through atb_s_p meas_atb_rx[8] If asserted AFE biasing vbn is measured through atb_s_m meas_atb_rx[7] If asserted rx_p is.." group.word 0x4744++0x1 line.word 0x0 "LANE1_ANA_RX_MISC_OVRD,RX_MISC_OVRD" newline hexmask.word.byte 0x0 8.--15. 1. "RESERVED_15_8,Reserved for Future use" newline bitfld.word 0x0 7. "OVERRIDE_VREG_PRECHG_REG,If asserted the overvoltage compensation circuit in rx_vregs disabled" "0,1" newline bitfld.word 0x0 6. "CTLE_OFFSET_CAL_ENB,If asserted the offset calibration currents in the CTLE are disabled" "0,1" newline bitfld.word 0x0 5. "OVRD_RX_LOS_LFPS_EN,If asserted bit 4 enable/disables RX true LFPS detection" "0,1" newline bitfld.word 0x0 4. "RX_LOS_LFPS_EN_REG,If asserted with bit 5 enables true LFPS detection" "0,1" newline bitfld.word 0x0 2.--3. "NC3_2,Reserved" "0,1,2,3" newline bitfld.word 0x0 1. "WORD_CLK_EN_REG,If asserted with bit 0 enables rx word clock" "0,1" newline bitfld.word 0x0 0. "OVRD_WORD_CLK_EN,If asserted bit 1 takes control of word clock enable/disable" "0,1" group.word 0x4748++0x1 line.word 0x0 "LANE1_ANA_RX_CAL_MUXA,RX_CAL_MUXA" newline hexmask.word.byte 0x0 8.--15. 1. "RESERVED_15_8,Reserved for Future use" newline bitfld.word 0x0 7. "OVRD_CAL_MUXA_SEL,If asserted selects analog register setting to control RX calibration path A" "0,1" newline hexmask.word.byte 0x0 2.--6. 1. "CAL_MUXA_SEL_REG,Analog registers to control RX calibration path A if bit 7 is asserted this is cal_muxa_sel_reg[4:0]" newline bitfld.word 0x0 1. "MEAS_ATB_VIBIAS_VCO,If asserted measure CDR VCO bias current through atb_s_p (25uA)" "0,1" newline bitfld.word 0x0 0. "MEAS_ATB_VCO_200U,If asserted measure CDR VCO bias current through atb_s_m (200uA)" "0,1" group.word 0x474C++0x1 line.word 0x0 "LANE1_ANA_RX_ATB_MEAS1,RX_ATB_MEAS1" newline hexmask.word.byte 0x0 8.--15. 1. "RESERVED_15_8,Reserved for Future use" newline bitfld.word 0x0 7. "ATB_FRC_VLOS,If asserted force los detection reference voltage through atb_s_m" "0,1" newline hexmask.word.byte 0x0 1.--6. 1. "MEAS_ATB_RX,This is meas_atb_rx[5:0] bits where each bit correspond to meas_atb_rx[5] If asserted rx_m is driven by atb_f_m meas_atb_rx[4] If asserted rx_m is sensed through atb_s_m meas_atb_rx[3] If asserted measure RX LOS detection threshold.." newline bitfld.word 0x0 0. "NC0,Reserved" "0,1" group.word 0x4750++0x1 line.word 0x0 "LANE1_ANA_RX_ATB_MEAS2,RX_ATB_MEAS2" newline hexmask.word.byte 0x0 8.--15. 1. "RESERVED_15_8,Reserved for Future use" newline bitfld.word 0x0 7. "MEAS_GD,If asserted measure RX regulator local gd through atb_s_p" "0,1" newline bitfld.word 0x0 6. "NC6,Reserved" "0,1" newline bitfld.word 0x0 5. "MEAS_VREG_CLK,If asserted measure RX clock regulator output voltage through atb_s_p" "0,1" newline bitfld.word 0x0 4. "NC4,Reserved" "0,1" newline bitfld.word 0x0 3. "MEAS_VREG_SCOPE,If asserted measure RX scope regulator output voltage through atb_s_p" "0,1" newline bitfld.word 0x0 2. "MEAS_ATB_OVRD_CDR_EN,If asserted enables CDR regardless of the digital control" "0,1" newline bitfld.word 0x0 1. "MEAS_ATB_VCO_GD,If asserted measure CDR VCO local gd through atb_s_m" "0,1" newline bitfld.word 0x0 0. "MEAS_ATB_VCO_VOSC,If asserted measure CDR VCO oscillation bias current through atb_s_m" "0,1" group.word 0x4754++0x1 line.word 0x0 "LANE1_ANA_RX_CAL_MUXB,RX_CAL_MUXB" newline hexmask.word.byte 0x0 8.--15. 1. "RESERVED_15_8,Reserved for Future use" newline bitfld.word 0x0 7. "OVRD_CAL_MUXB_SEL,If asserted selects analog register setting to control RX calibration path B" "0,1" newline hexmask.word.byte 0x0 2.--6. 1. "CAL_MUXB_SEL_REG,Analog registers to control RX calibration path B if bit 7 is asserted this is cal_muxb_sel_reg[4:0]" newline bitfld.word 0x0 1. "OVRD_DFE_TAPS_EN,If asserted allows bit 0 to enable/disable dfe taps 1 and 2" "0,1" newline bitfld.word 0x0 0. "DFE_TAPS_EN_REG,If bit 1 is asserted controls DFE tap 1 and 2" "0,1" group.word 0x4758++0x1 line.word 0x0 "LANE1_ANA_RX_TERM,RX_TERM" newline hexmask.word.byte 0x0 8.--15. 1. "RESERVED_15_8,Reserved for Future use" newline bitfld.word 0x0 6.--7. "AFE_CM_SEL,Added to make AFE CM voltage controllable (below values are for TT vp=0.8V) 00 vcm=662mV 01 vcm=627mV (default) 10 vcm=593mV 11 vcm=558mV" "0,1,2,3" newline bitfld.word 0x0 5. "OVRD_RX_TERM_GD_EN,If asserted the ground termination enable value is controlled via registers" "0,1" newline bitfld.word 0x0 4. "RX_TERM_GD_EN_REG,If termination override is asserted controls the ground termination enable" "0,1" newline bitfld.word 0x0 3. "OVRD_IQ_PHASE_ADJUST,If asserted the iq_phase_adjust value is controlled via registers" "0,1" newline bitfld.word 0x0 2. "VCO_TEMP_COMP_EN,If asserted the RX-VCO temperature compensation circuit is enabled" "0,1" newline bitfld.word 0x0 0.--1. "CDR_VCO_STARTUP_CODE_REG,RX_VCO startup current over-ride cdr_vco_startup_code Startup override 00 cdr_freq_code_int[9:7] = cdr_freq_code[9:7] 01 when startup = 1 -> cdr_freq_code_int[9] = 1 10 when startup = 1 -> cdr_freq_code_int[8] = 1 11 when startup.." "?,cdr_freq_code_int[7] = 1,?,?" group.word 0x475C++0x1 line.word 0x0 "LANE1_ANA_RX_SLC_CTRL,RX_SLC_CTRL" newline hexmask.word.byte 0x0 8.--15. 1. "RESERVED_15_8,Reserved for Future use" newline hexmask.word.byte 0x0 4.--7. 1. "RX_SLICER_CTRL_E_REG,If ovrd_rx_slicer_ctrl_reg is asserted controls the even slicer configuration" newline hexmask.word.byte 0x0 0.--3. 1. "RX_SLICER_CTRL_O_REG,If ovrd_rx_slicer_ctrl_reg is asserted controls the odd slicer configuration" group.word 0x4760++0x1 line.word 0x0 "LANE1_ANA_RX_ATB_VREG,RX_ATB_VREG" newline hexmask.word.byte 0x0 8.--15. 1. "RESERVED_15_8,Reserved for Future use" newline bitfld.word 0x0 7. "OVRD_REGREF_IQC,If asserted main PMIX regulator reference is overridden through atb_s_m" "0,1" newline bitfld.word 0x0 6. "OVRD_REGREF_IQC_SCOPE,If asserted scope PMIX regulator reference is overridden through atb_s_m" "0,1" newline bitfld.word 0x0 5. "MEAS_ATB_VREG_DFE,If asserted measure RX DFE regulator output voltage through atb_s_p" "0,1" newline bitfld.word 0x0 4. "NC4,Reserved" "0,1" newline bitfld.word 0x0 3. "MEAS_ATB_VREG_IQC,If asserted measure RX main PMIX regulator output voltage through atb_s_p" "0,1" newline bitfld.word 0x0 2. "MEAS_ATB_VREG_IQC_SCOPE,If asserted measure RX scope PMIX regulator output voltage through atb_s_p" "0,1" newline bitfld.word 0x0 1. "OVRD_IQC_VREF_SEL,If asserted the vref on the iqc regulator is controlled via vbg_vref which can be controlled via registers" "0,1" newline bitfld.word 0x0 0. "OVRD_RX_SLICER_CTRL_REG,If asserted the slicer configuration value is controlled via registers (LANE.RX_SLC_CTRL)" "0,1" group.word 0x8000++0x1 line.word 0x0 "RAWCMN_DIG_CMN_CTL,Common control register" newline hexmask.word 0x0 1.--15. 1. "RESERVED_15_1,Reserved for Future use" newline bitfld.word 0x0 0. "PHY_FUNC_RST,Resets the PHY except registers in the Raw PCS common and always-on registers. Useful for resetting the PHY after reloading the Memory and without resetting the Memory." "0,1" group.word 0x8004++0x1 line.word 0x0 "RAWCMN_DIG_MPLLA_OVRD_IN,Override values for incoming MPLLA signals" newline hexmask.word.byte 0x0 11.--15. 1. "RESERVED_15_11,Reserved for Future use" newline bitfld.word 0x0 10. "MPLLA_BW_OVRD_EN,Override enable for mplla_bandwidth[15:0]" "0,1" newline bitfld.word 0x0 9. "MPLLA_DIV8_CLK_EN_OVRD_EN,Override enable for mplla_div8_clk_en" "0,1" newline bitfld.word 0x0 8. "MPLLA_DIV8_CLK_EN_OVRD_VAL,Override value for mplla_div8_clk_en" "0,1" newline bitfld.word 0x0 7. "MPLLA_DIV10_CLK_EN_OVRD_EN,Override enable for mplla_div10_clk_en" "0,1" newline bitfld.word 0x0 6. "MPLLA_DIV10_CLK_EN_OVRD_VAL,Override value for mplla_div10_clk_en" "0,1" newline bitfld.word 0x0 5. "MPLLA_TX_CLK_DIV_OVRD_EN,Override enable for mplla_tx_clk_div[2:0]" "0,1" newline bitfld.word 0x0 2.--4. "MPLLA_TX_CLK_DIV_OVRD_VAL,Override value for mplla_tx_clk_div[2:0]" "0,1,2,3,4,5,6,7" newline bitfld.word 0x0 1. "MPLLA_WORD_DIV2_EN_OVRD_EN,Override enable for mplla_word_div2_en" "0,1" newline bitfld.word 0x0 0. "MPLLA_WORD_DIV2_EN_OVRD_VAL,Override value for mplla_word_div2_en" "0,1" group.word 0x8008++0x1 line.word 0x0 "RAWCMN_DIG_MPLLA_BW_OVRD_IN,Override values for incoming MPLLA bandwidth" newline hexmask.word 0x0 0.--15. 1. "MPLLA_BW_OVRD_VAL,Override value for mplla_bandwidth[15:0]" group.word 0x800C++0x1 line.word 0x0 "RAWCMN_DIG_MPLLA_SSC_CTL_OVRD_IN_0,Override values for incoming MPLLA SSC control settings" newline hexmask.word.byte 0x0 10.--15. 1. "RESERVED_15_10,Reserved for Future use" newline bitfld.word 0x0 9. "MPLLA_SSC_EN_OVRD_EN,Override enable for mplla_ssc_en" "0,1" newline bitfld.word 0x0 8. "MPLLA_SSC_EN_OVRD_VAL,Override value for mplla_ssc_en" "0,1" newline bitfld.word 0x0 7. "MPLLA_SSC_CLK_SEL_OVRD_EN,Override enable for mplla_ssc_clk_sel[2:0]" "0,1" newline bitfld.word 0x0 4.--6. "MPLLA_SSC_CLK_SEL_OVRD_VAL,Override value for mplla_ssc_clk_sel[2:0]" "0,1,2,3,4,5,6,7" newline bitfld.word 0x0 3. "MPLLA_SSC_RANGE_OVRD_EN,Override enable for mplla_ssc_range[2:0]" "0,1" newline bitfld.word 0x0 0.--2. "MPLLA_SSC_RANGE_OVRD_VAL,Override value for mplla_ssc_range[2:0]" "0,1,2,3,4,5,6,7" group.word 0x8010++0x1 line.word 0x0 "RAWCMN_DIG_MPLLB_OVRD_IN,Override values for incoming MPLLB signals" newline hexmask.word.byte 0x0 11.--15. 1. "RESERVED_15_11,Reserved for Future use" newline bitfld.word 0x0 10. "MPLLB_BW_OVRD_EN,Override enable for mpllb_bandwidth[15:0]" "0,1" newline bitfld.word 0x0 9. "MPLLB_DIV8_CLK_EN_OVRD_EN,Override enable for mpllb_div8_clk_en" "0,1" newline bitfld.word 0x0 8. "MPLLB_DIV8_CLK_EN_OVRD_VAL,Override value for mpllb_div8_clk_en" "0,1" newline bitfld.word 0x0 7. "MPLLB_DIV10_CLK_EN_OVRD_EN,Override enable for mpllb_div10_clk_en" "0,1" newline bitfld.word 0x0 6. "MPLLB_DIV10_CLK_EN_OVRD_VAL,Override value for mpllb_div10_clk_en" "0,1" newline bitfld.word 0x0 5. "MPLLB_TX_CLK_DIV_OVRD_EN,Override enable for mpllb_tx_clk_div[2:0]" "0,1" newline bitfld.word 0x0 2.--4. "MPLLB_TX_CLK_DIV_OVRD_VAL,Override value for mpllb_tx_clk_div[2:0]" "0,1,2,3,4,5,6,7" newline bitfld.word 0x0 1. "MPLLB_WORD_DIV2_EN_OVRD_EN,Override enable for mpllb_word_div2_en" "0,1" newline bitfld.word 0x0 0. "MPLLB_WORD_DIV2_EN_OVRD_VAL,Override value for mpllb_word_div2_en" "0,1" group.word 0x8014++0x1 line.word 0x0 "RAWCMN_DIG_MPLLB_BW_OVRD_IN,Override values for incoming MPLLB bandwidth" newline hexmask.word 0x0 0.--15. 1. "MPLLB_BW_OVRD_VAL,Override value for mpllb_bandwidth[15:0]" group.word 0x8018++0x1 line.word 0x0 "RAWCMN_DIG_MPLLB_SSC_CTL_OVRD_IN_0,Override values for incoming MPLLB SSC control settings" newline hexmask.word.byte 0x0 10.--15. 1. "RESERVED_15_10,Reserved for Future use" newline bitfld.word 0x0 9. "MPLLB_SSC_EN_OVRD_EN,Override enable for mpllb_ssc_en" "0,1" newline bitfld.word 0x0 8. "MPLLB_SSC_EN_OVRD_VAL,Override value for mpllb_ssc_en" "0,1" newline bitfld.word 0x0 7. "MPLLB_SSC_CLK_SEL_OVRD_EN,Override enable for mpllb_ssc_clk_sel[2:0]" "0,1" newline bitfld.word 0x0 4.--6. "MPLLB_SSC_CLK_SEL_OVRD_VAL,Override value for mpllb_ssc_clk_sel[2:0]" "0,1,2,3,4,5,6,7" newline bitfld.word 0x0 3. "MPLLB_SSC_RANGE_OVRD_EN,Override enable for mpllb_ssc_range[2:0]" "0,1" newline bitfld.word 0x0 0.--2. "MPLLB_SSC_RANGE_OVRD_VAL,Override value for mpllb_ssc_range[2:0]" "0,1,2,3,4,5,6,7" group.word 0x801C++0x1 line.word 0x0 "RAWCMN_DIG_LANE_FSM_OP_XTND,Lane FSM OP XTND control register" newline hexmask.word 0x0 1.--15. 1. "RESERVED_15_1,Reserved for Future use" newline bitfld.word 0x0 0. "DATA,Required to prevent timing violations while accessing through external interface." "0,1" group.word 0x8020++0x1 line.word 0x0 "RAWCMN_DIG_MPLLA_SSC_CTL_OVRD_IN_1,Override values for incoming MPLLA SSC control settings" newline hexmask.word.byte 0x0 12.--15. 1. "RESERVED_15_12,Reserved for Future use" newline bitfld.word 0x0 11. "MPLLA_FRACN_CTRL_OVRD_EN,Override enable for mplla_fracn_ctrl[10:0]" "0,1" newline hexmask.word 0x0 0.--10. 1. "MPLLA_FRACN_CTRL_OVRD_VAL,Override value for mplla_fracn_ctrl[10:0]" group.word 0x8024++0x1 line.word 0x0 "RAWCMN_DIG_MPLLB_SSC_CTL_OVRD_IN_1,Override values for incoming MPLLB SSC control settings" newline hexmask.word.byte 0x0 12.--15. 1. "RESERVED_15_12,Reserved for Future use" newline bitfld.word 0x0 11. "MPLLB_FRACN_CTRL_OVRD_EN,Override enable for mpllb_fracn_ctrl[10:0]" "0,1" newline hexmask.word 0x0 0.--10. 1. "MPLLB_FRACN_CTRL_OVRD_VAL,Override value for mpllb_fracn_ctrl[10:0]" group.word 0x8028++0x1 line.word 0x0 "RAWCMN_DIG_CMN_CTL_1,Common control register 1" newline hexmask.word 0x0 6.--15. 1. "RESERVED_15_6,Reserved for Future use" newline bitfld.word 0x0 5. "RTUNE_REQ_OVRD_EN,Override enable for rtune_req" "0,1" newline bitfld.word 0x0 4. "RTUNE_REQ_OVRD_VAL,Override value for rtune_req" "0,1" newline bitfld.word 0x0 3. "MPLLB_INIT_CAL_DISABLE_OVRD_EN,Override enable for mpllb_init_cal_disable" "0,1" newline bitfld.word 0x0 2. "MPLLB_INIT_CAL_DISABLE_OVRD_VAL,Override value for mpllb_init_cal_disable" "0,1" newline bitfld.word 0x0 1. "MPLLA_INIT_CAL_DISABLE_OVRD_EN,Override enable for mplla_init_cal_disable" "0,1" newline bitfld.word 0x0 0. "MPLLA_INIT_CAL_DISABLE_OVRD_VAL,Override value for mplla_init_cal_disable" "0,1" group.word 0x802C++0x1 line.word 0x0 "RAWCMN_DIG_CMN_CTL_2,Common control register 2" newline hexmask.word 0x0 7.--15. 1. "RESERVED_15_7,Reserved for Future use" newline bitfld.word 0x0 6. "FW_PWRUP_DONE,Indicates whether Firmware power-up has completed or not. After PG exit restore value from AON and assign it after coarse tune is restored in PG Exit sequence." "0,1" newline hexmask.word.byte 0x0 0.--5. 1. "TX_WAIT_MPLL_OFF_TIME,Number of ref_range cycles to wait for MPLL to turn off" repeat 8. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 )(list 0x0 0xC 0x18 0x24 0x30 0x3C 0x48 0x54 ) group.word ($2+0x8080)++0x1 line.word 0x0 "RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_$1,Resistor Tune RX Value 0" newline hexmask.word 0x0 6.--15. 1. "RESERVED_15_6,Reserved for Future use" newline hexmask.word.byte 0x0 0.--5. 1. "RTUNE_RX_VAL_0,Stored resister tune RX value 0" repeat.end repeat 8. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 )(list 0x0 0xC 0x18 0x24 0x30 0x3C 0x48 0x54 ) group.word ($2+0x8084)++0x1 line.word 0x0 "RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_$1,Resistor Tune TX Down Value 0" newline hexmask.word.byte 0x0 10.--15. 1. "RESERVED_15_10,Reserved for Future use" newline hexmask.word 0x0 0.--9. 1. "RTUNE_TXDN_VAL_0,Stored resister tune TX down value 0" repeat.end repeat 8. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 )(list 0x0 0xC 0x18 0x24 0x30 0x3C 0x48 0x54 ) group.word ($2+0x8088)++0x1 line.word 0x0 "RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_$1,Resistor Tune TX Up Value 0" newline hexmask.word.byte 0x0 10.--15. 1. "RESERVED_15_10,Reserved for Future use" newline hexmask.word 0x0 0.--9. 1. "RTUNE_TXUP_VAL_0,Stored resister tune TX up value 0" repeat.end group.word 0x80E0++0x1 line.word 0x0 "RAWCMN_DIG_AON_CMN_SRAM_PGATE_BL_EN,Enable SRAM bootloader on power-gated exit" newline hexmask.word 0x0 1.--15. 1. "RESERVED_15_1,Reserved for Future use" newline bitfld.word 0x0 0. "SRAM_PGATE_BL_EN,Enable SRAM bootloader on power-gated exit." "0,1" group.word 0x80E4++0x1 line.word 0x0 "RAWCMN_DIG_AON_CMN_PG_OVRD_IN,Override values for incoming power-gating signals" newline hexmask.word 0x0 6.--15. 1. "RESERVED_15_6,Reserved for Future use" newline bitfld.word 0x0 5. "PG_MODE_EN_OVRD_EN,Override enable for pg_mode_en." "0,1" newline bitfld.word 0x0 4. "PG_MODE_EN_OVRD_VAL,Override value for pg_mode_en." "0,1" newline bitfld.word 0x0 3. "PG_RESET_OVRD_EN,Override enable for pg_reset." "0,1" newline bitfld.word 0x0 2. "PG_RESET_OVRD_VAL,Override value for pg_reset." "0,1" newline bitfld.word 0x0 1. "PCS_PWR_STABLE_OVRD,Enable overriding pcs_pwr_stable to 1'b1." "0,1" newline bitfld.word 0x0 0. "PMA_PWR_STABLE_OVRD,Enable overriding pma_pwr_stable to 1'b1." "0,1" group.word 0x80E8++0x1 line.word 0x0 "RAWCMN_DIG_AON_CMN_PG_OVRD_OUT,Override values for outgoing power-gating signals" newline hexmask.word 0x0 2.--15. 1. "RESERVED_15_2,Reserved for Future use" newline bitfld.word 0x0 1. "PCS_PWR_EN_OVRD,Enable overriding pcs_pwr_en to 1'b1." "0,1" newline bitfld.word 0x0 0. "PMA_PWR_EN_OVRD,Enable overriding pma_pwr_en to 1'b1." "0,1" group.word 0x80EC++0x1 line.word 0x0 "RAWCMN_DIG_AON_CMN_SUP_OVRD_IN,Override values for incoming SUP signals" newline hexmask.word 0x0 6.--15. 1. "RESERVED_15_6,Reserved for Future use" newline bitfld.word 0x0 5. "REF_CLK_EN_OVRD_EN,Override enable for ref_clk_en" "0,1" newline bitfld.word 0x0 4. "REF_CLK_EN_OVRD_VAL,Override value for ref_clk_en" "0,1" newline bitfld.word 0x0 3. "MPLLB_FORCE_EN_OVRD_EN,Override enable for mpllb_force_en" "0,1" newline bitfld.word 0x0 2. "MPLLB_FORCE_EN_OVRD_VAL,Override value for mpllb_force_en" "0,1" newline bitfld.word 0x0 1. "MPLLA_FORCE_EN_OVRD_EN,Override enable for mplla_force_en" "0,1" newline bitfld.word 0x0 0. "MPLLA_FORCE_EN_OVRD_VAL,Override value for mplla_force_en" "0,1" group.word 0x80F0++0x1 line.word 0x0 "RAWCMN_DIG_AON_CMN_FW_PWRUP_DONE,Firmware Power-Up Done Status" newline hexmask.word 0x0 1.--15. 1. "RESERVED_15_1,Reserved for Future use" newline bitfld.word 0x0 0. "FW_PWRUP_DONE,Indicates whether Firmware power-up has completed or not." "0,1" repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) group.word ($2+0x80F4)++0x1 line.word 0x0 "RAWCMN_DIG_AON_CMN_FW_VERSION_$1,Firmware version register #0" newline hexmask.word 0x0 0.--15. 1. "FW_VERSION_0,Firmware version" repeat.end group.word 0xC000++0x1 line.word 0x0 "RAWLANE0_DIG_PCS_XF_TX_OVRD_IN,Override values for incoming TX controls from PCS" newline rbitfld.word 0x0 13.--15. "RESERVED_15_13,Reserved for Future use" "0,1,2,3,4,5,6,7" newline bitfld.word 0x0 12. "OVRD_EN,Override enable for all input signals below" "0,1" newline bitfld.word 0x0 11. "MSTR_MPLLB_STATE,Override value for tx_master_mpllb_state" "0,1" newline bitfld.word 0x0 10. "MSTR_MPLLA_STATE,Override value for tx_master_mplla_state" "0,1" newline bitfld.word 0x0 9. "MPLL_EN,Override value for tx_mpll_en" "0,1" newline bitfld.word 0x0 8. "MPLLB_SEL,Override value for tx_mpllb_sel" "0,1" newline bitfld.word 0x0 5.--7. "RATE,Override value for tx_rate" "0,1,2,3,4,5,6,7" newline bitfld.word 0x0 3.--4. "WIDTH,Override value for tx_width" "0,1,2,3" newline bitfld.word 0x0 2. "LPD,Override value for tx_lpd" "0,1" newline bitfld.word 0x0 0.--1. "PSTATE,Override value for tx_pstate" "0,1,2,3" group.word 0xC004++0x1 line.word 0x0 "RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_1,Override values for incoming TX controls from PCS. register #1" newline rbitfld.word 0x0 13.--15. "RESERVED_15_13,Reserved for Future use" "0,1,2,3,4,5,6,7" newline bitfld.word 0x0 12. "IBOOST_LVL_OVRD_EN,Override enable for tx_iboost_lvl[3:0]" "0,1" newline hexmask.word.byte 0x0 8.--11. 1. "IBOOST_LVL_OVRD_VAL,Override value for tx_iboost_lvl[3:0]" newline bitfld.word 0x0 7. "VBOOST_EN_OVRD_EN,Override enable for tx_vboost_en" "0,1" newline bitfld.word 0x0 6. "VBOOST_EN_OVRD_VAL,Override value for tx_vboost_en" "0,1" newline bitfld.word 0x0 5. "DETRX_REQ_OVRD_EN,Override enable for tx_detrx_req" "0,1" newline bitfld.word 0x0 4. "DETRX_REQ_OVRD_VAL,Override value for tx_detrx_req" "0,1" newline bitfld.word 0x0 3. "REQ_OVRD_EN,Override enable for tx_req" "0,1" newline bitfld.word 0x0 2. "REQ_OVRD_VAL,Override value for tx_req" "0,1" newline bitfld.word 0x0 1. "RESET_OVRD_EN,Override enable for tx_reset" "0,1" newline bitfld.word 0x0 0. "RESET_OVRD_VAL,Override value for tx_reset" "0,1" rgroup.word 0xC008++0x1 line.word 0x0 "RAWLANE0_DIG_PCS_XF_TX_PCS_IN,Current values for incoming TX controls from PCS" newline bitfld.word 0x0 15. "RESERVED_15_15,Reserved for Future use" "0,1" newline bitfld.word 0x0 14. "DETRX_REQ,Value from PCS for tx_detrx_req" "0,1" newline bitfld.word 0x0 13. "MSTR_MPLLB_STATE,Value from PCS for tx_master_mpllb_state" "0,1" newline bitfld.word 0x0 12. "MSTR_MPLLA_STATE,Value from PCS for tx_master_mplla_state" "0,1" newline bitfld.word 0x0 11. "MPLL_EN,Value from PCS for tx_mpll_en" "0,1" newline bitfld.word 0x0 10. "MPLLB_SEL,Value from PCS for tx_mpllb_sel" "0,1" newline bitfld.word 0x0 7.--9. "RATE,Value from PCS for tx_rate" "0,1,2,3,4,5,6,7" newline bitfld.word 0x0 5.--6. "WIDTH,Value from PCS for tx_width" "0,1,2,3" newline bitfld.word 0x0 4. "LPD,Value from PCS for tx_lpd" "0,1" newline bitfld.word 0x0 2.--3. "PSTATE,Value from PCS for tx_pstate" "0,1,2,3" newline bitfld.word 0x0 1. "REQ,Value from PCS for tx_req" "0,1" newline bitfld.word 0x0 0. "RESET,Value from PCS for tx_reset" "0,1" group.word 0xC00C++0x1 line.word 0x0 "RAWLANE0_DIG_PCS_XF_TX_OVRD_OUT,Override values for outgoing TX controls to PCS" newline hexmask.word 0x0 3.--15. 1. "RESERVED_15_3,Reserved for Future use" newline bitfld.word 0x0 2. "EN_CTL,Enable override values for all control outputs of this register" "0,1" newline bitfld.word 0x0 1. "DETRX_RESULT,Override value for tx_detrx_result" "0,1" newline bitfld.word 0x0 0. "ACK,Override value for tx_ack" "0,1" rgroup.word 0xC010++0x1 line.word 0x0 "RAWLANE0_DIG_PCS_XF_TX_PCS_OUT,Current values for outgoing TX status controls from Raw PCS" newline hexmask.word 0x0 1.--15. 1. "RESERVED_15_1,Reserved for Future use" newline bitfld.word 0x0 0. "ACK,Value from Raw PCS for tx_ack" "0,1" group.word 0xC014++0x1 line.word 0x0 "RAWLANE0_DIG_PCS_XF_RX_OVRD_IN,Override values for incoming RX controls from PCS" newline hexmask.word.byte 0x0 10.--15. 1. "RESERVED_15_10,Reserved for Future use" newline bitfld.word 0x0 9. "ADAPT_DFE_EN,Override value for rx_adapt_dfe_en" "0,1" newline bitfld.word 0x0 8. "ADAPT_AFE_EN,Override value for rx_adapt_afe_en" "0,1" newline bitfld.word 0x0 7. "OVRD_EN,Enable override values for all fields in this register" "0,1" newline bitfld.word 0x0 6. "LPD,Override value for rx_lpd" "0,1" newline bitfld.word 0x0 4.--5. "PSTATE,Override value for rx_pstate" "0,1,2,3" newline bitfld.word 0x0 2.--3. "WIDTH,Override value for rx_width" "0,1,2,3" newline bitfld.word 0x0 0.--1. "RATE,Override value for rx_rate" "0,1,2,3" group.word 0xC018++0x1 line.word 0x0 "RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_1,Override values for incoming RX controls from PCS. register #1" newline hexmask.word 0x0 4.--15. 1. "RESERVED_15_4,Reserved for Future use" newline bitfld.word 0x0 3. "REQ_OVRD_EN,Override enable for rx_req" "0,1" newline bitfld.word 0x0 2. "REQ_OVRD_VAL,Override value for rx_req" "0,1" newline bitfld.word 0x0 1. "RESET_OVRD_EN,Override enable for rx_reset" "0,1" newline bitfld.word 0x0 0. "RESET_OVRD_VAL,Override value for rx_reset" "0,1" group.word 0xC01C++0x1 line.word 0x0 "RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_2,Override values for incoming RX controls from PCS. register #2" newline bitfld.word 0x0 15. "VCO_LOWFREQ_VAL_OVRD_EN,Enable override for rx_cdr_vco_lowfreq" "0,1" newline bitfld.word 0x0 14. "VCO_LOWFREQ_VAL_OVRD,Override value for rx_cdr_vco_lowfreq" "0,1" newline bitfld.word 0x0 13. "VCO_LD_VAL_OVRD_EN,Enable override for rx_vco_ld_val" "0,1" newline hexmask.word 0x0 0.--12. 1. "VCO_LD_VAL_OVRD,Override value for rx_vco_ld_val" group.word 0xC020++0x1 line.word 0x0 "RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_3,Override values for incoming RX controls from PCS. register #3" newline bitfld.word 0x0 15. "CONT_OVRD_EN,Enable override values for rx_adapt_cont and rx_offcan_cont" "0,1" newline bitfld.word 0x0 14. "OFFCAN_CONT,Override value for rx_offcan_cont" "0,1" newline bitfld.word 0x0 13. "ADAPT_CONT,Override value for rx_adapt_cont" "0,1" newline bitfld.word 0x0 12. "ADAPT_REQ_OVRD_EN,Enable override values for rx_adapt_req" "0,1" newline bitfld.word 0x0 11. "ADAPT_REQ,Override value for rx_adapt_req" "0,1" newline bitfld.word 0x0 10. "REF_LD_VAL_OVRD_EN,Enable override for rx_ref_ld_val" "0,1" newline hexmask.word.byte 0x0 4.--9. 1. "REF_LD_VAL_OVRD,Override value for rx_ref_ld_val" newline bitfld.word 0x0 3. "RX_LOS_THRSHLD_OVRD_EN,Enable override for rx_los_threshold" "0,1" newline bitfld.word 0x0 0.--2. "RX_LOS_THRSHLD_OVRD_VAL,Override value for rx_los_threshold" "0,1,2,3,4,5,6,7" rgroup.word 0xC024++0x1 line.word 0x0 "RAWLANE0_DIG_PCS_XF_RX_PCS_IN,Current values for incoming RX controls from PCS" newline bitfld.word 0x0 15. "RESERVED_15_15,Reserved for Future use" "0,1" newline bitfld.word 0x0 14. "RESET,Value from PCS for rx_reset" "0,1" newline bitfld.word 0x0 13. "OFFCAN_CONT,Value from PCS for rx_offcan_cont" "0,1" newline bitfld.word 0x0 12. "ADAPT_CONT,Value from PCS for rx_adapt_cont" "0,1" newline bitfld.word 0x0 11. "ADAPT_REQ,Value from PCS for rx_adapt_req" "0,1" newline bitfld.word 0x0 10. "ADAPT_DFE_EN,Value from PCS for rx_adapt_dfe_en" "0,1" newline bitfld.word 0x0 9. "ADAPT_AFE_EN,Value from PCS for rx_adapt_afe_en" "0,1" newline bitfld.word 0x0 8. "CDR_VCO_LOWFREQ,Value from PCS for rx_cdr_vco_lowfreq" "0,1" newline bitfld.word 0x0 7. "LPD,Value from PCS for rx_lpd" "0,1" newline bitfld.word 0x0 5.--6. "PSTATE,Value from PCS for rx_pstate" "0,1,2,3" newline bitfld.word 0x0 3.--4. "WIDTH,Value from PCS for rx_width" "0,1,2,3" newline bitfld.word 0x0 1.--2. "RATE,Value from PCS for rx_rate" "0,1,2,3" newline bitfld.word 0x0 0. "REQ,Value from PCS for rx_req" "0,1" rgroup.word 0xC028++0x1 line.word 0x0 "RAWLANE0_DIG_PCS_XF_RX_PCS_IN_1,Current values for incoming RX controls from PCS. register #1" newline hexmask.word 0x0 6.--15. 1. "RESERVED_15_6,Reserved for Future use" newline hexmask.word.byte 0x0 0.--5. 1. "REF_LD_VAL,Value from PCS for rx_ref_ld_val" rgroup.word 0xC02C++0x1 line.word 0x0 "RAWLANE0_DIG_PCS_XF_RX_PCS_IN_2,Current values for incoming RX controls from PCS. register #2" newline bitfld.word 0x0 13.--15. "RESERVED_15_13,Reserved for Future use" "0,1,2,3,4,5,6,7" newline hexmask.word 0x0 0.--12. 1. "VCO_LD_VAL,Value from PCS for rx_vco_ld_val" rgroup.word 0xC030++0x1 line.word 0x0 "RAWLANE0_DIG_PCS_XF_RX_PCS_IN_3,Current values for incoming RX controls from PCS. register #3" newline hexmask.word.byte 0x0 11.--15. 1. "EQ_CTLE_BOOST,Value from ASIC for rx_eq_ctle_boost" newline hexmask.word.byte 0x0 7.--10. 1. "EQ_VGA2_GAIN,Value from ASIC for rx_eq_vga2_gain" newline hexmask.word.byte 0x0 3.--6. 1. "EQ_VGA1_GAIN,Value from ASIC for rx_eq_vga1_gain" newline bitfld.word 0x0 0.--2. "EQ_ATT_LVL,Value from ASIC for rx_eq_att_lvl" "0,1,2,3,4,5,6,7" rgroup.word 0xC034++0x1 line.word 0x0 "RAWLANE0_DIG_PCS_XF_RX_PCS_IN_4,Current values for incoming RX controls from PCS. register #4" newline hexmask.word.byte 0x0 11.--15. 1. "RESERVED_15_11,Reserved for Future use" newline hexmask.word.byte 0x0 3.--10. 1. "EQ_DFE_TAP1,Value from ASIC for rx_eq_dfe_tap1" newline bitfld.word 0x0 0.--2. "EQ_CTLE_POLE,Value from ASIC for rx_eq_ctle_pole" "0,1,2,3,4,5,6,7" group.word 0xC038++0x1 line.word 0x0 "RAWLANE0_DIG_PCS_XF_RX_OVRD_OUT,Override values for outgoing RX controls to PCS" newline hexmask.word 0x0 2.--15. 1. "RESERVED_15_2,Reserved for Future use" newline bitfld.word 0x0 1. "EN_CTL,Enable override values for all control outputs of this register" "0,1" newline bitfld.word 0x0 0. "ACK,Override value for rx_ack" "0,1" rgroup.word 0xC03C++0x1 line.word 0x0 "RAWLANE0_DIG_PCS_XF_RX_PCS_OUT,Current values for outgoing RX status controls from Raw PCS" newline hexmask.word 0x0 1.--15. 1. "RESERVED_15_1,Reserved for Future use" newline bitfld.word 0x0 0. "ACK,Value from Raw PCS for rx_ack" "0,1" group.word 0xC040++0x1 line.word 0x0 "RAWLANE0_DIG_PCS_XF_RX_ADAPT_ACK,RX Adaptation Acknowledge" newline hexmask.word 0x0 1.--15. 1. "RESERVED_15_1,Reserved for Future use" newline bitfld.word 0x0 0. "RX_ADAPT_ACK,RX Adaptation Acknowledge" "0,1" group.word 0xC044++0x1 line.word 0x0 "RAWLANE0_DIG_PCS_XF_RX_ADAPT_FOM,RX Adaptation Figure of Merit" newline hexmask.word.byte 0x0 8.--15. 1. "RESERVED_15_8,Reserved for Future use" newline hexmask.word.byte 0x0 0.--7. 1. "RX_ADAPT_FOM,RX Adaptation Figure of Merit" group.word 0xC048++0x1 line.word 0x0 "RAWLANE0_DIG_PCS_XF_RX_TXPRE_DIR,RX calculated direction for TX-pre" newline hexmask.word 0x0 2.--15. 1. "RESERVED_15_2,Reserved for Future use" newline bitfld.word 0x0 0.--1. "RX_TXPRE_DIR,RX calculated direction for TX-pre 00 - No change 01 - Increment 10 - Decrement 11 - Reserved" "No change,Increment,?,?" group.word 0xC04C++0x1 line.word 0x0 "RAWLANE0_DIG_PCS_XF_RX_TXMAIN_DIR,RX calculated direction for TX-Main" newline hexmask.word 0x0 2.--15. 1. "RESERVED_15_2,Reserved for Future use" newline bitfld.word 0x0 0.--1. "RX_TXMAIN_DIR,RX calculated direction for TX-Main 00 - No change 01 - Increment 10 - Decrement 11 - Reserved" "No change,Increment,?,?" group.word 0xC050++0x1 line.word 0x0 "RAWLANE0_DIG_PCS_XF_RX_TXPOST_DIR,RX calculated direction for TX-Post" newline hexmask.word 0x0 2.--15. 1. "RESERVED_15_2,Reserved for Future use" newline bitfld.word 0x0 0.--1. "RX_TXPOST_DIR,RX calculated direction for TX-Post 00 - No change 01 - Increment 10 - Decrement 11 - Reserved" "No change,Increment,?,?" rgroup.word 0xC054++0x1 line.word 0x0 "RAWLANE0_DIG_PCS_XF_LANE_NUMBER,Current lane number" newline hexmask.word 0x0 4.--15. 1. "RESERVED_15_4,Reserved for Future use" newline hexmask.word.byte 0x0 0.--3. 1. "LANE_NUMBER,Current lane number" group.word 0xC058++0x1 line.word 0x0 "RAWLANE0_DIG_PCS_XF_LANE_XCVR_MODE_OVRD_IN,Override incoming values for lane_xcvr_mode" newline hexmask.word 0x0 3.--15. 1. "RESERVED_15_3,Reserved for Future use" newline bitfld.word 0x0 2. "LANE_XCVR_MODE_OVRD_EN,Enable override value for lane_xcvr_mode" "0,1" newline bitfld.word 0x0 0.--1. "LANE_XCVR_MODE_OVRD_VAL,Override value for lane_xcvr_mode" "0,1,2,3" rgroup.word 0xC05C++0x1 line.word 0x0 "RAWLANE0_DIG_PCS_XF_LANE_XCVR_MODE_IN,Lane transceiver mode status" newline hexmask.word 0x0 2.--15. 1. "RESERVED_15_2,Reserved for Future use" newline bitfld.word 0x0 0.--1. "LANE_XCVR_MODE,Lane transceiver mode Determines whether this lane is being used as Tx Rx or Tx/Rx 00 - Reserved 01 - Lane is used for Tx only 10 - Lane is used for Rx only 11 - Lane is used for Tx/Rx" "Reserved,Lane is used for Tx only,?,?" group.word 0xC060++0x1 line.word 0x0 "RAWLANE0_DIG_PCS_XF_ATE_OVRD_IN,ATE Override input to control top-level inputs" newline hexmask.word.byte 0x0 12.--15. 1. "RESERVED_15_12,Reserved for Future use" newline bitfld.word 0x0 11. "RX_ADAPT_DFE_EN_OVRD_EN,Enable override value for rx_adapt_dfe_en input" "0,1" newline bitfld.word 0x0 10. "RX_ADAPT_DFE_EN_OVRD_VAL,Override value for rx_adapt_dfe_en input" "0,1" newline bitfld.word 0x0 9. "RX_ADAPT_AFE_EN_OVRD_EN,Enable override value for rx_adapt_afe_en input" "0,1" newline bitfld.word 0x0 8. "RX_ADAPT_AFE_EN_OVRD_VAL,Override value for rx_adapt_afe_en input" "0,1" newline bitfld.word 0x0 7. "TX_REQ_ATE_OVRD_EN,Enable override value for tx_req input" "0,1" newline bitfld.word 0x0 6. "TX_REQ_ATE_OVRD_VAL,Override value for top-level tx_req input" "0,1" newline bitfld.word 0x0 5. "RX_REQ_ATE_OVRD_EN,Enable override value for rx_req input" "0,1" newline bitfld.word 0x0 4. "RX_REQ_ATE_OVRD_VAL,Override value for top-level rx_req input" "0,1" newline bitfld.word 0x0 3. "TX_RESET_ATE_OVRD_EN,Enable override value for tx_reset input" "0,1" newline bitfld.word 0x0 2. "TX_RESET_ATE_OVRD_VAL,Override value for top-level tx_reset input" "0,1" newline bitfld.word 0x0 1. "RX_RESET_ATE_OVRD_EN,Enable override value for rx_reset input" "0,1" newline bitfld.word 0x0 0. "RX_RESET_ATE_OVRD_VAL,Override value for top-level rx_reset input" "0,1" group.word 0xC064++0x1 line.word 0x0 "RAWLANE0_DIG_PCS_XF_RX_EQ_DELTA_IQ_OVRD_IN,Override incoming values for rx_eq_delta_iq" newline hexmask.word 0x0 5.--15. 1. "RESERVED_15_5,Reserved for Future use" newline bitfld.word 0x0 4. "RX_EQ_DELTA_IQ_OVRD_EN,Enable override value for rx_eq_delta_iq" "0,1" newline hexmask.word.byte 0x0 0.--3. 1. "RX_EQ_DELTA_IQ_OVRD_VAL,Override value for rx_eq_delta_iq" group.word 0xC068++0x1 line.word 0x0 "RAWLANE0_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN,Override incoming values for tx/rx_term_ctrl" newline hexmask.word.byte 0x0 8.--15. 1. "RESERVED_15_8,Reserved for Future use" newline bitfld.word 0x0 7. "TX_TERM_CTRL_OVRD_EN,Enable override value for tx_term_ctrl" "0,1" newline bitfld.word 0x0 4.--6. "TX_TERM_CTRL_OVRD_VAL,Override value for tx_term_ctrl" "0,1,2,3,4,5,6,7" newline bitfld.word 0x0 3. "RX_TERM_CTRL_OVRD_EN,Enable override value for rx_term_ctrl" "0,1" newline bitfld.word 0x0 0.--2. "RX_TERM_CTRL_OVRD_VAL,Override value for rx_term_ctrl" "0,1,2,3,4,5,6,7" rgroup.word 0xC06C++0x1 line.word 0x0 "RAWLANE0_DIG_PCS_XF_TXRX_TERM_CTRL_IN,tx/rx_term_ctrl status" newline hexmask.word 0x0 6.--15. 1. "RESERVED_15_6,Reserved for Future use" newline bitfld.word 0x0 3.--5. "TX_TERM_CTRL,tx_term_ctrl value" "0,1,2,3,4,5,6,7" newline bitfld.word 0x0 0.--2. "RX_TERM_CTRL,tx_term_ctrl value" "0,1,2,3,4,5,6,7" group.word 0xC070++0x1 line.word 0x0 "RAWLANE0_DIG_PCS_XF_RX_OVRD_OUT_1,Override values for outgoing RX controls to PCS. register #1" newline hexmask.word 0x0 1.--15. 1. "RESERVED_15_1,Reserved for Future use" newline bitfld.word 0x0 0. "RX_CLK_EN,Enable the outging rx_clk" "0,1" group.word 0xC074++0x1 line.word 0x0 "RAWLANE0_DIG_PCS_XF_RX_EQ_OVRD_IN_1,Override values for incoming RX EQ controls from PCS. register #1" newline hexmask.word.byte 0x0 8.--15. 1. "RESERVED_15_8,Reserved for Future use" newline bitfld.word 0x0 7. "RX_EQ_OVRD_EN,Enable override values for all RX EQ settings" "0,1" newline bitfld.word 0x0 4.--6. "RX_EQ_ATT_LVL_OVRD_VAL,Override value for rx_eq_att_lvl[2:0]" "0,1,2,3,4,5,6,7" newline hexmask.word.byte 0x0 0.--3. 1. "RX_EQ_AFE_GAIN_OVRD_VAL,Override value for rx_eq_afe_gain[3:0]" group.word 0xC078++0x1 line.word 0x0 "RAWLANE0_DIG_PCS_XF_RX_EQ_OVRD_IN_2,Override values for incoming RX EQ controls from PCS. register #2" newline rbitfld.word 0x0 13.--15. "RESERVED_15_13,Reserved for Future use" "0,1,2,3,4,5,6,7" newline hexmask.word.byte 0x0 8.--12. 1. "RX_EQ_CTLE_BOOST_OVRD_VAL,Override value for rx_eq_ctle_boost[4:0]" newline hexmask.word.byte 0x0 0.--7. 1. "RX_EQ_DFE_TAP1_OVRD_VAL,Override value for rx_eq_dfe_tap1[7:0]" group.word 0xC07C++0x1 line.word 0x0 "RAWLANE0_DIG_PCS_XF_RX_OVRD_OUT_2,Override value for RX VALID/DATA_EN/DATA_EN_ATE signal from PCS" newline hexmask.word.byte 0x0 11.--15. 1. "RESERVED_15_11,Reserved for Future use" newline bitfld.word 0x0 10. "RX_RATE_ATE_OVRD_EN,Override enable for rx_rate_ate" "0,1" newline bitfld.word 0x0 8.--9. "RX_RATE_ATE_OVRD_VAL,Override value for rx_rate_ate" "0,1,2,3" newline bitfld.word 0x0 7. "RX_CDR_TRACK_EN_ATE_OVRD_EN,Override enable for rx_cdr_track_en_ate" "0,1" newline bitfld.word 0x0 6. "RX_CDR_TRACK_EN_ATE_OVRD_VAL,Override value for rx_cdr_track_en_ate" "0,1" newline bitfld.word 0x0 5. "RX_DATA_EN_ATE_OVRD_EN,Override enable for rx_data_en_ate" "0,1" newline bitfld.word 0x0 4. "RX_DATA_EN_ATE_OVRD_VAL,Override value for rx_data_en_ate" "0,1" newline bitfld.word 0x0 3. "RX_DATA_EN_OVRD_EN,Override enable for rx_data_en" "0,1" newline bitfld.word 0x0 2. "RX_DATA_EN_OVRD_VAL,Override value for rx_data_en" "0,1" newline bitfld.word 0x0 1. "RX_VALID_OVRD_EN,Override enable for rx_valid" "0,1" newline bitfld.word 0x0 0. "RX_VALID_OVRD_VAL,Override value for rx_valid" "0,1" group.word 0xC080++0x1 line.word 0x0 "RAWLANE0_DIG_FSM_FSM_OVRD_CTL,FSM override control register" newline rbitfld.word 0x0 15. "RESERVED_15_15,Reserved for Future use" "0,1" newline bitfld.word 0x0 14. "FSM_OVRD_EN,Enable overriding the FSM execution of commands Must be asserted to use FSM_CMD_START and FSM_JMP_EN features" "0,1" newline bitfld.word 0x0 13. "FSM_CMD_START,Start executing the new command This is a self-clearing bit" "0,1" newline bitfld.word 0x0 12. "FSM_JMP_EN,Force the FSM to jump to FSM_JMP_ADDR in the program memory Is applied when FSM_CMD_START is pulsed." "0,1" newline hexmask.word 0x0 0.--11. 1. "FSM_JMP_ADDR,The jump address used when FSM_JUMP_EN=1 The address is encoded as follows: [11:8] mem_lane [7:5] bank [4:0] register" rgroup.word 0xC084++0x1 line.word 0x0 "RAWLANE0_DIG_FSM_MEM_ADDR_MON,Memory Address Monitor" newline hexmask.word 0x0 0.--15. 1. "MEM_ADDR,Current value of memory address used in Lane FSM" rgroup.word 0xC088++0x1 line.word 0x0 "RAWLANE0_DIG_FSM_STATUS_MON,FSM Status Monitor" newline hexmask.word.byte 0x0 11.--15. 1. "RESERVED_15_11,Reserved for Future use" newline bitfld.word 0x0 10. "RDMSK_DISABLED,Check if read mask is currently disabled (i.e. mask is all ones)" "0,1" newline bitfld.word 0x0 9. "WRMSK_DISABLED,Check if write mask is currently disabled (i.e. mask is all ones)" "0,1" newline bitfld.word 0x0 8. "WAIT_CNT_EQ0,Check if wait counter currently equals zero" "0,1" newline bitfld.word 0x0 7. "ALU_RES_EQ0,Check if ALU result register currently equals zero" "0,1" newline bitfld.word 0x0 6. "ALU_OVFLW,Current value of ALU overflow bit" "0,1" newline bitfld.word 0x0 5. "CMD_RDY,New command is ready for execution (applicable when FSM_OVRD_EN=1)" "0,1" newline hexmask.word.byte 0x0 0.--4. 1. "STATE,Current state of Lane FSM" rgroup.word 0xC08C++0x1 line.word 0x0 "RAWLANE0_DIG_FSM_FAST_RX_STARTUP_CAL,Status of Fast RX Start Up Calibration" newline hexmask.word 0x0 1.--15. 1. "RESERVED_15_1,Reserved for Future use" newline bitfld.word 0x0 0. "FAST_RX_STARTUP_CAL,Status of fast RX start-up calibration" "0,1" rgroup.word 0xC090++0x1 line.word 0x0 "RAWLANE0_DIG_FSM_FAST_RX_ADAPT,Status of Fast RX Adaptation" newline hexmask.word 0x0 1.--15. 1. "RESERVED_15_1,Reserved for Future use" newline bitfld.word 0x0 0. "FAST_RX_ADAPT,Status of fast RX adaptation" "0,1" rgroup.word 0xC094++0x1 line.word 0x0 "RAWLANE0_DIG_FSM_FAST_RX_AFE_CAL,Status of Fast RX AFE Calibration" newline hexmask.word 0x0 1.--15. 1. "RESERVED_15_1,Reserved for Future use" newline bitfld.word 0x0 0. "FAST_RX_AFE_CAL,Status of fast RX AFE DAC start-up calibration" "0,1" rgroup.word 0xC098++0x1 line.word 0x0 "RAWLANE0_DIG_FSM_FAST_RX_DFE_CAL,Status of Fast RX DFE Calibration" newline hexmask.word 0x0 1.--15. 1. "RESERVED_15_1,Reserved for Future use" newline bitfld.word 0x0 0. "FAST_RX_DFE_CAL,Status of fast RX DFE slicer start-up calibration" "0,1" rgroup.word 0xC09C++0x1 line.word 0x0 "RAWLANE0_DIG_FSM_FAST_RX_DFE_RE_ADAPT,Enables fast RX DFE re -adaptation" newline hexmask.word 0x0 1.--15. 1. "RESERVED_15_1,Reserved for Future use" newline bitfld.word 0x0 0. "FAST_RX_DFE_RE_ADAPT,Enables fast RX DFE re -adaptation" "0,1" rgroup.word 0xC0A0++0x1 line.word 0x0 "RAWLANE0_DIG_FSM_FAST_RX_REFLVL_CAL,Status of Fast RX Reference Level Calibration" newline hexmask.word 0x0 1.--15. 1. "RESERVED_15_1,Reserved for Future use" newline bitfld.word 0x0 0. "FAST_RX_REFLVL_CAL,Status of fast RX reference level (100mv 125mv 150mv) start-up calibration" "0,1" rgroup.word 0xC0A4++0x1 line.word 0x0 "RAWLANE0_DIG_FSM_FAST_RX_IQ_CAL,Status of Fast RX IQ Calibration" newline hexmask.word 0x0 1.--15. 1. "RESERVED_15_1,Reserved for Future use" newline bitfld.word 0x0 0. "FAST_RX_IQ_CAL,Status of fast RX IQ start-up calibration" "0,1" rgroup.word 0xC0A8++0x1 line.word 0x0 "RAWLANE0_DIG_FSM_FAST_RX_AFE_ADAPT,Status of Fast RX AFE Adaptation" newline hexmask.word 0x0 1.--15. 1. "RESERVED_15_1,Reserved for Future use" newline bitfld.word 0x0 0. "FAST_RX_AFE_ADAPT,Status of fast RX AFE DAC start-up adaptation" "0,1" rgroup.word 0xC0AC++0x1 line.word 0x0 "RAWLANE0_DIG_FSM_FAST_RX_DFE_ADAPT,Status of Fast RX DFE Adaptation" newline hexmask.word 0x0 1.--15. 1. "RESERVED_15_1,Reserved for Future use" newline bitfld.word 0x0 0. "FAST_RX_DFE_ADAPT,Status of fast RX DFE DAC start-up adaptation" "0,1" rgroup.word 0xC0B0++0x1 line.word 0x0 "RAWLANE0_DIG_FSM_FAST_SUP,Status of Fast Support block" newline hexmask.word 0x0 1.--15. 1. "RESERVED_15_1,Reserved for Future use" newline bitfld.word 0x0 0. "FAST_SUP,Status of fast Support block (MPLL and Rtune)" "0,1" rgroup.word 0xC0B4++0x1 line.word 0x0 "RAWLANE0_DIG_FSM_FAST_TX_CMN_MODE,Status of Fast TX Common-mode Charge-up" newline hexmask.word 0x0 1.--15. 1. "RESERVED_15_1,Reserved for Future use" newline bitfld.word 0x0 0. "FAST_TX_CMN_MODE,Status of fast TX Common-mode Charge-up" "0,1" rgroup.word 0xC0B8++0x1 line.word 0x0 "RAWLANE0_DIG_FSM_FAST_TX_RXDET,Status of Fast TX detect RX" newline hexmask.word 0x0 1.--15. 1. "RESERVED_15_1,Reserved for Future use" newline bitfld.word 0x0 0. "FAST_TX_RXDET,Status of fast TX detect RX" "0,1" rgroup.word 0xC0BC++0x1 line.word 0x0 "RAWLANE0_DIG_FSM_FAST_RX_PWRUP,Status of Fast RX Power-up" newline hexmask.word 0x0 1.--15. 1. "RESERVED_15_1,Reserved for Future use" newline bitfld.word 0x0 0. "FAST_RX_PWRUP,Status of fast RX Power-up (LOS VREG/AFE and DCC)" "0,1" rgroup.word 0xC0C0++0x1 line.word 0x0 "RAWLANE0_DIG_FSM_FAST_RX_VCO_WAIT,Status of Fast RX VCO Wait Times" newline hexmask.word 0x0 1.--15. 1. "RESERVED_15_1,Reserved for Future use" newline bitfld.word 0x0 0. "FAST_RX_VCO_WAIT,Status of fast RX VCO wait times" "0,1" rgroup.word 0xC0C4++0x1 line.word 0x0 "RAWLANE0_DIG_FSM_FAST_RX_VCO_CAL,Status of Fast RX VCO Calibration" newline hexmask.word 0x0 1.--15. 1. "RESERVED_15_1,Reserved for Future use" newline bitfld.word 0x0 0. "FAST_RX_VCO_CAL,Status of fast RX VCO Calibration" "0,1" rgroup.word 0xC0C8++0x1 line.word 0x0 "RAWLANE0_DIG_FSM_CMNCAL_MPLL_STATUS,Status of MPLL common calibration initiation" newline hexmask.word 0x0 2.--15. 1. "RESERVED_15_2,Reserved for Future use" newline bitfld.word 0x0 1. "CMNCAL_MPLL_DONE,Indicates whether MPLL common calibration has been completed by any lane or not." "0,1" newline bitfld.word 0x0 0. "CMNCAL_MPLL_INIT,Indicates whether MPLL common calibration has been started by any lane or not. ---------------------------------------------------------------------" "0,1" rgroup.word 0xC0CC++0x1 line.word 0x0 "RAWLANE0_DIG_FSM_FAST_RX_CONT_CAL_ADAPT,Status of Fast RX Continuous Calibration/Adaptation" newline hexmask.word 0x0 1.--15. 1. "RESERVED_15_1,Reserved for Future use" newline bitfld.word 0x0 0. "FAST_RX_CONT_CAL_ADAPT,Status of fast RX continuous calibration/adaptation" "0,1" rgroup.word 0xC0D0++0x1 line.word 0x0 "RAWLANE0_DIG_FSM_FAST_RX_CONT_ADAPT,Status of Fast RX Continuous Adaptation" newline hexmask.word 0x0 1.--15. 1. "RESERVED_15_1,Reserved for Future use" newline bitfld.word 0x0 0. "FAST_RX_CONT_ADAPT,Status of fast RX continuous adaptation" "0,1" rgroup.word 0xC0D4++0x1 line.word 0x0 "RAWLANE0_DIG_FSM_FAST_RX_CONT_DATA_CAL,Status of Fast RX Continuous Data Calibration" newline hexmask.word 0x0 1.--15. 1. "RESERVED_15_1,Reserved for Future use" newline bitfld.word 0x0 0. "FAST_RX_CONT_DATA_CAL,Status of fast RX continuous data calibration" "0,1" rgroup.word 0xC0D8++0x1 line.word 0x0 "RAWLANE0_DIG_FSM_FAST_RX_CONT_PHASE_CAL,Status of Fast RX Continuous Phase Calibration" newline hexmask.word 0x0 1.--15. 1. "RESERVED_15_1,Reserved for Future use" newline bitfld.word 0x0 0. "FAST_RX_CONT_PHASE_CAL,Status of fast RX continuous phase calibration" "0,1" rgroup.word 0xC0DC++0x1 line.word 0x0 "RAWLANE0_DIG_FSM_FAST_RX_CONT_AFE_CAL,Status of Fast RX Continuous AFE Calibration" newline hexmask.word 0x0 1.--15. 1. "RESERVED_15_1,Reserved for Future use" newline bitfld.word 0x0 0. "FAST_RX_CONT_AFE_CAL,Status of fast RX continuous AFE calibration" "0,1" rgroup.word 0xC0E0++0x1 line.word 0x0 "RAWLANE0_DIG_FSM_FAST_RX_IQ_ADAPT,Status of Fast RX IQ_ADAPT" newline hexmask.word 0x0 1.--15. 1. "RESERVED_15_1,Reserved for Future use" newline bitfld.word 0x0 0. "FAST_RX_IQ_ADAPT,Status of Fast RX IQ_ADAPT" "0,1" rgroup.word 0xC0E4++0x1 line.word 0x0 "RAWLANE0_DIG_FSM_RX_IQ_DELTA_ADD,Status of RX Delta addition" newline hexmask.word 0x0 1.--15. 1. "RESERVED_15_1,Reserved for Future use" newline bitfld.word 0x0 0. "RX_IQ_DELTA_ADD,Reserved" "0,1" rgroup.word 0xC0E8++0x1 line.word 0x0 "RAWLANE0_DIG_FSM_FAST_RX_ATT_ADAPT,Enables fast RX ATT adaptation" newline hexmask.word 0x0 1.--15. 1. "RESERVED_15_1,Reserved for Future use" newline bitfld.word 0x0 0. "FAST_RX_ATT_ADAPT,Enables fast RX ATT adaptation" "0,1" rgroup.word 0xC0EC++0x1 line.word 0x0 "RAWLANE0_DIG_FSM_FAST_RX_CTLE_ADAPT,Enables fast RX CTLE adaptation" newline hexmask.word 0x0 1.--15. 1. "RESERVED_15_1,Reserved for Future use" newline bitfld.word 0x0 0. "FAST_RX_CTLE_ADAPT,Enables fast RX CTLE adaptation" "0,1" group.word 0xC0F0++0x1 line.word 0x0 "RAWLANE0_DIG_FSM_CR_REG_OP_XTND_EN,CR interface timing extension enable" newline hexmask.word 0x0 1.--15. 1. "RESERVED_15_1,Reserved for Future use" newline bitfld.word 0x0 0. "CR_REG_OP_XTND_EN,CR interface timing extension enable 1'b0 - No Timing extension 1'b1 - Timing extension" "No Timing extension,Timing extension" group.word 0xC0F4++0x1 line.word 0x0 "RAWLANE0_DIG_FSM_TX_EQ_UPDATE_FLAG,TX Eq update flag" newline hexmask.word 0x0 1.--15. 1. "RESERVED_15_1,Reserved for Future use" newline bitfld.word 0x0 0. "TX_EQ_UPDATE_FLAG,Tx Eq update flag 1'b0 - Update tx eq post 1'b1 - Update tx eq pre" "Update tx eq post,Update tx eq pre" rgroup.word 0xC0F8++0x1 line.word 0x0 "RAWLANE0_DIG_FSM_CMNCAL_RCAL_STATUS,Status of RTUNE common calibration initiation" newline hexmask.word 0x0 2.--15. 1. "RESERVED_15_2,Reserved for Future use" newline bitfld.word 0x0 1. "CMNCAL_RCAL_DONE,Indicates whether RTUNE common calibration has been completed by any lane or not." "0,1" newline bitfld.word 0x0 0. "CMNCAL_RCAL_INIT,Indicates whether RTUNE common calibration has been started by any lane or not. ---------------------------------------------------------------------" "0,1" rgroup.word 0xC0FC++0x1 line.word 0x0 "RAWLANE0_DIG_FSM_RX_IQ_PHASE_OFFSET,Offset value for IQ Phase Calculation" newline hexmask.word 0x0 4.--15. 1. "RESERVED_15_4,Reserved for Future use" newline hexmask.word.byte 0x0 0.--3. 1. "RX_IQ_PHASE_OFFSET,Offset value for IQ Phase Calculation" group.word 0xC100++0x1 line.word 0x0 "RAWLANE0_DIG_AON_AFE_ATT_IDAC_OFST,Offset value for RX AFE ATT iDAC" newline hexmask.word.byte 0x0 8.--15. 1. "RESERVED_15_8,Reserved for Future use" newline hexmask.word.byte 0x0 0.--7. 1. "AFE_ATT_IDAC_OFST,Offset value for AFE ATT iDAC" group.word 0xC104++0x1 line.word 0x0 "RAWLANE0_DIG_AON_AFE_CTLE_IDAC_OFST,Offset value for RX AFE CTLE iDAC" newline hexmask.word.byte 0x0 8.--15. 1. "RESERVED_15_8,Reserved for Future use" newline hexmask.word.byte 0x0 0.--7. 1. "AFE_CTLE_IDAC_OFST,Offset value for AFE CTLE iDAC" group.word 0xC108++0x1 line.word 0x0 "RAWLANE0_DIG_AON_ADAPT_REF_LVL_DAC_CODE,Reference level for RX AFE Adaptation" newline hexmask.word.byte 0x0 8.--15. 1. "RESERVED_15_8,Reserved for Future use" newline hexmask.word.byte 0x0 0.--7. 1. "ADAPT_REF_LVL_DAC_CODE,Reference level for RX AFE Adaptation" group.word 0xC10C++0x1 line.word 0x0 "RAWLANE0_DIG_AON_RX_ADAPT_FOM,Adaptation Figure of Merit (FOM)" newline hexmask.word.byte 0x0 8.--15. 1. "RESERVED_15_8,Reserved for Future use" newline hexmask.word.byte 0x0 0.--7. 1. "RX_ADAPT_FOM,Adaptation Figure of Merit (FOM)" group.word 0xC110++0x1 line.word 0x0 "RAWLANE0_DIG_AON_AFE_CTLE_LBK_IDAC_OFST,Offset values for RX CTLE Loopback path iDAC" newline hexmask.word.byte 0x0 8.--15. 1. "RESERVED_15_8,Reserved for Future use" newline hexmask.word.byte 0x0 0.--7. 1. "AFE_CTLE_LBK_IDAC_OFST,Offset value for RX CTLE Loopback path iDAC" group.word 0xC114++0x1 line.word 0x0 "RAWLANE0_DIG_AON_DFE_PHASE_EVEN_VDAC_OFST,Offset values for RX DFE Phase Even vDAC" newline hexmask.word.byte 0x0 8.--15. 1. "RESERVED_15_8,Reserved for Future use" newline hexmask.word.byte 0x0 0.--7. 1. "DFE_PHASE_EVEN_VDAC_OFST,Offset value for DFE Phase Even vDAC" group.word 0xC118++0x1 line.word 0x0 "RAWLANE0_DIG_AON_DFE_PHASE_ODD_VDAC_OFST,Offset values for RX DFE Phase Odd vDAC" newline hexmask.word.byte 0x0 8.--15. 1. "RESERVED_15_8,Reserved for Future use" newline hexmask.word.byte 0x0 0.--7. 1. "DFE_PHASE_ODD_VDAC_OFST,Offset value for DFE Phase Odd vDAC" group.word 0xC11C++0x1 line.word 0x0 "RAWLANE0_DIG_AON_DFE_EVEN_REF_LVL,DFE Even reference level" newline hexmask.word.byte 0x0 8.--15. 1. "RESERVED_15_8,Reserved for Future use" newline hexmask.word.byte 0x0 0.--7. 1. "DFE_EVEN_REF_LVL,DFE Even reference level" group.word 0xC120++0x1 line.word 0x0 "RAWLANE0_DIG_AON_DFE_ODD_REF_LVL,DFE Odd reference level" newline hexmask.word.byte 0x0 8.--15. 1. "RESERVED_15_8,Reserved for Future use" newline hexmask.word.byte 0x0 0.--7. 1. "DFE_ODD_REF_LVL,DFE Odd reference level" group.word 0xC124++0x1 line.word 0x0 "RAWLANE0_DIG_AON_RX_PHSADJ_LIN,RX Phase Adjust Linear Value" newline hexmask.word 0x0 5.--15. 1. "RESERVED_15_5,Reserved for Future use" newline hexmask.word.byte 0x0 0.--4. 1. "RX_PHSADJ_LIN,Linear value for RX phase adjust" rgroup.word 0xC128++0x1 line.word 0x0 "RAWLANE0_DIG_AON_RX_PHSADJ_MAP,RX Phase Adjust Mapped Value" newline hexmask.word 0x0 5.--15. 1. "RESERVED_15_5,Reserved for Future use" newline hexmask.word.byte 0x0 0.--4. 1. "RX_PHSADJ_MAP,Mapped value for RX phase adjust" group.word 0xC12C++0x1 line.word 0x0 "RAWLANE0_DIG_AON_DFE_DATA_EVEN_HIGH_VDAC_OFST,Offset values for RX DFE Data Even High vDAC" newline hexmask.word.byte 0x0 8.--15. 1. "RESERVED_15_8,Reserved for Future use" newline hexmask.word.byte 0x0 0.--7. 1. "DFE_DATA_EVEN_HIGH_VDAC_OFST,Offset value for DFE Data Even High vDAC" group.word 0xC130++0x1 line.word 0x0 "RAWLANE0_DIG_AON_DFE_DATA_EVEN_LOW_VDAC_OFST,Offset values for RX DFE Data Even Low vDAC" newline hexmask.word 0x0 0.--15. 1. "DFE_DATA_EVEN_LOW_VDAC_OFST,Offset value for DFE Data Even Low vDAC" group.word 0xC134++0x1 line.word 0x0 "RAWLANE0_DIG_AON_DFE_DATA_ODD_HIGH_VDAC_OFST,Offset values for RX DFE Data Odd High vDAC" newline hexmask.word.byte 0x0 8.--15. 1. "RESERVED_15_8,Reserved for Future use" newline hexmask.word.byte 0x0 0.--7. 1. "DFE_DATA_ODD_HIGH_VDAC_OFST,Offset value for DFE Data Odd High vDAC" group.word 0xC138++0x1 line.word 0x0 "RAWLANE0_DIG_AON_DFE_DATA_ODD_LOW_VDAC_OFST,Offset values for RX DFE Data Odd Low vDAC" newline hexmask.word 0x0 0.--15. 1. "DFE_DATA_ODD_LOW_VDAC_OFST,Offset value for DFE Data Odd Low vDAC" group.word 0xC13C++0x1 line.word 0x0 "RAWLANE0_DIG_AON_DFE_BYPASS_EVEN_VDAC_OFST,Offset values for RX DFE By-Pass Even vDAC" newline hexmask.word.byte 0x0 8.--15. 1. "RESERVED_15_8,Reserved for Future use" newline hexmask.word.byte 0x0 0.--7. 1. "DFE_BYPASS_EVEN_VDAC_OFST,Offset value for DFE By-Pass Even vDAC" group.word 0xC140++0x1 line.word 0x0 "RAWLANE0_DIG_AON_DFE_BYPASS_ODD_VDAC_OFST,Offset values for RX DFE By-Pass Odd vDAC" newline hexmask.word.byte 0x0 8.--15. 1. "RESERVED_15_8,Reserved for Future use" newline hexmask.word.byte 0x0 0.--7. 1. "DFE_BYPASS_ODD_VDAC_OFST,Offset value for DFE By-Pass Odd vDAC" group.word 0xC144++0x1 line.word 0x0 "RAWLANE0_DIG_AON_DFE_ERROR_EVEN_VDAC_OFST,Offset values for RX DFE Error Even vDAC" newline hexmask.word.byte 0x0 8.--15. 1. "RESERVED_15_8,Reserved for Future use" newline hexmask.word.byte 0x0 0.--7. 1. "DFE_ERROR_EVEN_VDAC_OFST,Offset value for DFE Error Even vDAC" group.word 0xC148++0x1 line.word 0x0 "RAWLANE0_DIG_AON_DFE_ERROR_ODD_VDAC_OFST,Offset values for RX DFE Error Odd vDAC" newline hexmask.word.byte 0x0 8.--15. 1. "RESERVED_15_8,Reserved for Future use" newline hexmask.word.byte 0x0 0.--7. 1. "DFE_ERROR_ODD_VDAC_OFST,Offset value for DFE Error Odd vDAC" group.word 0xC14C++0x1 line.word 0x0 "RAWLANE0_DIG_AON_RX_IQ_PHASE_ADJUST,Value for RX IQ PHASE Adjust" newline hexmask.word 0x0 7.--15. 1. "RESERVED_15_7,Reserved for Future use" newline hexmask.word.byte 0x0 0.--6. 1. "RX_IQ_PHASE_ADJUST,Value for RX IQ PHASE Adjust" group.word 0xC150++0x1 line.word 0x0 "RAWLANE0_DIG_AON_MPLLA_COARSE_TUNE,MPLLA_COARSE_TUNE" newline hexmask.word.byte 0x0 8.--15. 1. "RESERVED_15_8,Reserved for Future use" newline hexmask.word.byte 0x0 0.--7. 1. "MPLLA_COARSE_TUNE,Stored coarse tune value for MPLLA" group.word 0xC154++0x1 line.word 0x0 "RAWLANE0_DIG_AON_MPLLB_COARSE_TUNE,MPLLB_COARSE_TUNE" newline hexmask.word.byte 0x0 8.--15. 1. "RESERVED_15_8,Reserved for Future use" newline hexmask.word.byte 0x0 0.--7. 1. "MPLLB_COARSE_TUNE,Stored coarse tune value for MPLLB" group.word 0xC158++0x1 line.word 0x0 "RAWLANE0_DIG_AON_INIT_PWRUP_DONE,Initial Power-Up Done Status" newline hexmask.word 0x0 1.--15. 1. "RESERVED_15_1,Reserved for Future use" newline bitfld.word 0x0 0. "INIT_PWRUP_DONE,Indicates whether initial power-up has completed or not." "0,1" group.word 0xC15C++0x1 line.word 0x0 "RAWLANE0_DIG_AON_RX_ADPT_ATT,RX Adapted value of ATT" newline hexmask.word.byte 0x0 8.--15. 1. "RESERVED_15_8,Reserved for Future use" newline hexmask.word.byte 0x0 0.--7. 1. "ATT_ADPT_VAL,Stored RX adapted ATT value" group.word 0xC160++0x1 line.word 0x0 "RAWLANE0_DIG_AON_RX_ADPT_VGA,RX Adapted value of VGA" newline hexmask.word.byte 0x0 10.--15. 1. "RESERVED_15_10,Reserved for Future use" newline hexmask.word 0x0 0.--9. 1. "VGA_ADPT_VAL,Stored RX adapted VGA value" group.word 0xC164++0x1 line.word 0x0 "RAWLANE0_DIG_AON_RX_ADPT_CTLE,RX Adapted value of CTLE" newline rbitfld.word 0x0 13.--15. "RESERVED_15_13,Reserved for Future use" "0,1,2,3,4,5,6,7" newline bitfld.word 0x0 10.--12. "CTLE_POLE_ADPT_VAL,Stored RX adapted CTLE pole value" "0,1,2,3,4,5,6,7" newline hexmask.word 0x0 0.--9. 1. "CTLE_BOOST_ADPT_VAL,Stored RX adapted CTLE boost value" group.word 0xC168++0x1 line.word 0x0 "RAWLANE0_DIG_AON_RX_ADPT_DFE_TAP1,RX Adapted value of DFE TAP1" newline rbitfld.word 0x0 13.--15. "RESERVED_15_13,Reserved for Future use" "0,1,2,3,4,5,6,7" newline hexmask.word 0x0 0.--12. 1. "DFE_TAP1_ADPT_VAL,Stored RX adapted DFE TAP1 value" group.word 0xC16C++0x1 line.word 0x0 "RAWLANE0_DIG_AON_RX_ADAPT_DONE,RX Adaptation Done Status" newline hexmask.word 0x0 1.--15. 1. "RESERVED_15_1,Reserved for Future use" newline bitfld.word 0x0 0. "RX_ADAPT_DONE,Indicates whether RX adaptation has completed or not." "0,1" group.word 0xC170++0x1 line.word 0x0 "RAWLANE0_DIG_AON_FAST_FLAGS,Fast flags for simulation only" newline rbitfld.word 0x0 15. "RESERVED_15_15,Reserved for Future use" "0,1" newline bitfld.word 0x0 14. "FAST_RX_VCO_CAL,Enable fast RX VCO Calibration" "0,1" newline bitfld.word 0x0 13. "FAST_RX_VCO_WAIT,Enable fast RX VCO wait times" "0,1" newline bitfld.word 0x0 12. "FAST_RX_PWRUP,Enable fast RX power-up (LOS VREG/AFE and DCC)" "0,1" newline bitfld.word 0x0 11. "FAST_TX_RXDET,Enable fast TX Detect RX" "0,1" newline bitfld.word 0x0 10. "FAST_TX_CMN_MODE,Enable fast TX Common Mode Charge-up" "0,1" newline bitfld.word 0x0 9. "FAST_SUP,Enable fast Support block (MPLL and Rtune)" "0,1" newline bitfld.word 0x0 8. "FAST_RX_DFE_ADAPT,Enables fast RX DFE DAC start-up adaptation" "0,1" newline bitfld.word 0x0 7. "FAST_RX_AFE_ADAPT,Enables fast RX AFE DAC start-up adaptation" "0,1" newline bitfld.word 0x0 6. "FAST_RX_IQ_CAL,Enables fast RX IQ start-up calibration" "0,1" newline bitfld.word 0x0 5. "FAST_RX_REFLVL_CAL,Enables fast RX reference level (100mv 125mv 150mv) start-up calibration" "0,1" newline bitfld.word 0x0 4. "FAST_RX_DFE_RE_ADAPT,Enables fast RX DFE re -adaptation" "0,1" newline bitfld.word 0x0 3. "FAST_RX_DFE_CAL,Enables fast RX DFE slicer start-up calibration" "0,1" newline bitfld.word 0x0 2. "FAST_RX_AFE_CAL,Enables fast RX AFE DAC start-up calibration" "0,1" newline bitfld.word 0x0 1. "FAST_RX_ADAPT,Enables fast RX adaptation" "0,1" newline bitfld.word 0x0 0. "FAST_RX_STARTUP_CAL,Enables fast RX start-up calibration" "0,1" group.word 0xC174++0x1 line.word 0x0 "RAWLANE0_DIG_AON_RX_ADPT_DFE_TAP2,RX Adapted value of DFE TAP2" newline hexmask.word.byte 0x0 12.--15. 1. "RESERVED_15_12,Reserved for Future use" newline hexmask.word 0x0 0.--11. 1. "DFE_TAP2_ADPT_VAL,Stored RX adapted DFE TAP2 value" group.word 0xC178++0x1 line.word 0x0 "RAWLANE0_DIG_AON_RX_PHSADJ_LIN_RIGHT,RX last stable iq phase of Right of the eye" newline hexmask.word.byte 0x0 8.--15. 1. "RESERVED,Reserved bits" newline hexmask.word.byte 0x0 0.--7. 1. "RX_PHSADJ_LIN_RIGHT,Stored RX iq phase right edge" group.word 0xC17C++0x1 line.word 0x0 "RAWLANE0_DIG_AON_RX_PHSADJ_LIN_LEFT,RX last stable iq phase of Left of the eye" newline hexmask.word.byte 0x0 8.--15. 1. "RESERVED,Reserved bits" newline hexmask.word.byte 0x0 0.--7. 1. "RX_PHSADJ_LIN_LEFT,Stored RX iq phase left edge" group.word 0xC180++0x1 line.word 0x0 "RAWLANE0_DIG_AON_RX_PHSADJ_LIN_ADAPT,RX Adapted value of PHASE IQ" newline hexmask.word.byte 0x0 8.--15. 1. "RESERVED,Reserved bits" newline hexmask.word.byte 0x0 0.--7. 1. "RX_PHSADJ_LIN_ADAPT,Stored RX adapted IQ value" group.word 0xC184++0x1 line.word 0x0 "RAWLANE0_DIG_AON_RX_SLICER_CTRL_EVEN,Sets values for RX SLICER CTRL EVEN signals going to ANA" newline hexmask.word 0x0 4.--15. 1. "RESERVED_15_4,Reserved for Future use" newline hexmask.word.byte 0x0 0.--3. 1. "RX_ANA_SLICER_CTRL_E,Value for rx_ana_slicer_ctrl_e[3:0]" group.word 0xC188++0x1 line.word 0x0 "RAWLANE0_DIG_AON_RX_SLICER_CTRL_ODD,Sets values for RX SLICER CTRL ODD signals going to ANA" newline hexmask.word 0x0 4.--15. 1. "RESERVED_15_4,Reserved for Future use" newline hexmask.word.byte 0x0 0.--3. 1. "RX_ANA_SLICER_CTRL_O,Value for rx_ana_slicer_ctrl_o[3:0]" group.word 0xC18C++0x1 line.word 0x0 "RAWLANE0_DIG_AON_LANE_CMNCAL_MPLL_STATUS,MPLL Common Calibration Status" newline hexmask.word 0x0 2.--15. 1. "RESERVED_15_2,Reserved for Future use" newline bitfld.word 0x0 1. "LANE_CMNCAL_MPLL_DONE,Indicates whether MPLL common calibration has been completed by this lane or not." "0,1" newline bitfld.word 0x0 0. "LANE_CMNCAL_MPLL_INIT,Indicates whether MPLL common calibration has been started by this lane or not." "0,1" repeat 8. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 )(list 0x0 0x4 0x8 0xC 0x10 0x14 0x18 0x1C ) group.word ($2+0xC190)++0x1 line.word 0x0 "RAWLANE0_DIG_AON_ADPT_CTL_$1,Adaptation Control register #0" newline hexmask.word 0x0 0.--15. 1. "VAL,Value of adaptation control" repeat.end group.word 0xC1B0++0x1 line.word 0x0 "RAWLANE0_DIG_AON_MPLL_DISABLE,LANE_MPLLA/B_DISABLE override" newline hexmask.word 0x0 2.--15. 1. "RESERVED_15_2,Reserved for Future use" newline bitfld.word 0x0 1. "LANE_MPLLB_DISABLE,Disable MPLLB" "0,1" newline bitfld.word 0x0 0. "LANE_MPLLA_DISABLE,Disable MPLLA" "0,1" group.word 0xC1B4++0x1 line.word 0x0 "RAWLANE0_DIG_AON_FAST_FLAGS_2,Fast flags for simulation only" newline hexmask.word.byte 0x0 12.--15. 1. "RSVD_FAST_FLAGS,Reserved fast flags" newline bitfld.word 0x0 11. "SKIP_IQ_STEP_SKIP,Skip the IQ step skip option" "0,1" newline bitfld.word 0x0 10. "SKIP_250US_WAIT,Skip bit for USB Gen1 250us wait FW WA" "0,1" newline bitfld.word 0x0 9. "WA_ATT_VCM_ISSUE_MODE,Workaround en or disable STAR 9001169835" "0,1" newline bitfld.word 0x0 8. "FAST_RX_CTLE_ADAPT,Enables fast RX CTLE adaptation" "0,1" newline bitfld.word 0x0 7. "FAST_RX_ATT_ADAPT,Enables fast RX ATT adaptation" "0,1" newline bitfld.word 0x0 6. "RX_IQ_DELTA_ADD,Enables RX IQ DELTA addition" "0,1" newline bitfld.word 0x0 5. "FAST_RX_IQ_ADAPT,Enables fast RX IQ ADAPT" "0,1" newline bitfld.word 0x0 4. "FAST_RX_CONT_AFE_CAL,Enables fast RX continuous AFE calibration" "0,1" newline bitfld.word 0x0 3. "FAST_RX_CONT_PHASE_CAL,Enables fast RX continuous phase calibration" "0,1" newline bitfld.word 0x0 2. "FAST_RX_CONT_DATA_CAL,Enables fast RX continuous data calibration" "0,1" newline bitfld.word 0x0 1. "FAST_RX_CONT_ADAPT,Enables fast RX continuous adaptation" "0,1" newline bitfld.word 0x0 0. "FAST_RX_CONT_CAL_ADAPT,Enables fast RX continuous calibration/adaptation" "0,1" group.word 0xC1B8++0x1 line.word 0x0 "RAWLANE0_DIG_AON_LANE_CMNCAL_RCAL_STATUS,RTUNE Common Calibration Status" newline hexmask.word 0x0 2.--15. 1. "RESERVED_15_2,Reserved for Future use" newline bitfld.word 0x0 1. "LANE_CMNCAL_RCAL_DONE,Indicates whether RTUNE common calibration has been completed by this lane or not." "0,1" newline bitfld.word 0x0 0. "LANE_CMNCAL_RCAL_INIT,Indicates whether RTUNE common calibration has been started by this lane or not." "0,1" group.word 0xC1BC++0x1 line.word 0x0 "RAWLANE0_DIG_AON_TXRX_OVRD_IN,Override values for incoming AON TX/RX controls from PCS" newline hexmask.word 0x0 4.--15. 1. "RESERVED_15_4,Reserved for Future use" newline bitfld.word 0x0 3. "TX_DISABLE_OVRD_EN,Override enable for tx_disable" "0,1" newline bitfld.word 0x0 2. "TX_DISABLE_OVRD_VAL,Override value for tx_disable" "0,1" newline bitfld.word 0x0 1. "RX_DISABLE_OVRD_EN,Override enable for rx_disable" "0,1" newline bitfld.word 0x0 0. "RX_DISABLE_OVRD_VAL,Override value for rx_disable" "0,1" group.word 0xC1C0++0x1 line.word 0x0 "RAWLANE0_DIG_AON_AFE_ATT_2_IDAC_OFST,Offset value for RX AFE ATT_2 iDAC" newline hexmask.word.byte 0x0 8.--15. 1. "RESERVED_15_8,Reserved for Future use" newline hexmask.word.byte 0x0 0.--7. 1. "AFE_ATT_2_IDAC_OFST,Offset value for AFE ATT_2 iDAC when cc is 1 in ana typec projects" group.word 0xC1C4++0x1 line.word 0x0 "RAWLANE0_DIG_AON_RXTX_CC_OVRD_IN,Override incoming values for rxtx_cc" newline hexmask.word 0x0 2.--15. 1. "RESERVED_15_2,Reserved for Future use" newline bitfld.word 0x0 1. "RXTX_CC_OVRD_EN,Enable override value for rxtx_cc" "0,1" newline bitfld.word 0x0 0. "RXTX_CC_OVRD_VAL,Override value for rxtx_cc" "0,1" rgroup.word 0xC1C8++0x1 line.word 0x0 "RAWLANE0_DIG_AON_RXTX_CC_STATUS_IN,Incoming value of CC status from TCA" newline hexmask.word 0x0 1.--15. 1. "RESERVED_15_1,Reserved for Future use" newline bitfld.word 0x0 0. "RXTX_CC_IN_I,Value from TCA of cc" "0,1" rgroup.word 0xC1CC++0x1 line.word 0x0 "RAWLANE0_DIG_AON_RXTX_CC_STATUS_OUT,Current values for outgoing CC status to PMA" newline hexmask.word 0x0 1.--15. 1. "RESERVED_15_1,Reserved for Future use" newline bitfld.word 0x0 0. "RXTX_CC_OUT,Value to PMA of cc" "0,1" group.word 0xC200++0x1 line.word 0x0 "RAWLANE0_DIG_IRQ_CTL_RESET_RTN_REQ,Reset routine request" newline hexmask.word 0x0 1.--15. 1. "RESERVED_15_1,Reserved for Future use" newline bitfld.word 0x0 0. "RESET_RTN_REQ,Reset routine request" "0,1" rgroup.word 0xC204++0x1 line.word 0x0 "RAWLANE0_DIG_IRQ_CTL_RX_RESET_IRQ,Rx reset interrupt" newline hexmask.word 0x0 1.--15. 1. "RESERVED_15_1,Reserved for Future use" newline bitfld.word 0x0 0. "RX_RESET,Rx reset interrupt" "0,1" rgroup.word 0xC208++0x1 line.word 0x0 "RAWLANE0_DIG_IRQ_CTL_RX_REQ_IRQ,Rx request interrupt" newline hexmask.word 0x0 1.--15. 1. "RESERVED_15_1,Reserved for Future use" newline bitfld.word 0x0 0. "RX_REQ,Rx request interrupt" "0,1" rgroup.word 0xC20C++0x1 line.word 0x0 "RAWLANE0_DIG_IRQ_CTL_RX_RATE_IRQ,Rx rate change interrupt request" newline hexmask.word 0x0 1.--15. 1. "RESERVED_15_1,Reserved for Future use" newline bitfld.word 0x0 0. "RX_RATE_IRQ,Rx rate change interrupt request" "0,1" rgroup.word 0xC210++0x1 line.word 0x0 "RAWLANE0_DIG_IRQ_CTL_RX_PSTATE_IRQ,Rx pstate change interrupt request" newline hexmask.word 0x0 1.--15. 1. "RESERVED_15_1,Reserved for Future use" newline bitfld.word 0x0 0. "RX_PSTATE_IRQ,Rx pstate change interrupt request" "0,1" rgroup.word 0xC214++0x1 line.word 0x0 "RAWLANE0_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ,Rx adaptation request interrupt" newline hexmask.word 0x0 1.--15. 1. "RESERVED_15_1,Reserved for Future use" newline bitfld.word 0x0 0. "RX_ADAPT_REQ_IRQ,Rx adaptation request interrupt" "0,1" rgroup.word 0xC218++0x1 line.word 0x0 "RAWLANE0_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ,Rx adaptation disable interrupt" newline hexmask.word 0x0 1.--15. 1. "RESERVED_15_1,Reserved for Future use" newline bitfld.word 0x0 0. "RX_ADAPT_DIS_IRQ,Rx adaptation disable interrupt" "0,1" group.word 0xC21C++0x1 line.word 0x0 "RAWLANE0_DIG_IRQ_CTL_RX_RESET_IRQ_CLR,RX reset interrupt clear" newline hexmask.word 0x0 1.--15. 1. "RESERVED_15_1,Reserved for Future use" newline bitfld.word 0x0 0. "RX_RESET_IRQ_CLR,RX reset interrupt clear (self-clearing)" "0,1" group.word 0xC220++0x1 line.word 0x0 "RAWLANE0_DIG_IRQ_CTL_RX_REQ_IRQ_CLR,RX request interrupt clear" newline hexmask.word 0x0 1.--15. 1. "RESERVED_15_1,Reserved for Future use" newline bitfld.word 0x0 0. "RX_REQ_IRQ_CLR,RX request interrupt clear (self-clearing)" "0,1" group.word 0xC224++0x1 line.word 0x0 "RAWLANE0_DIG_IRQ_CTL_RX_RATE_IRQ_CLR,RX rate change interrupt clear" newline hexmask.word 0x0 1.--15. 1. "RESERVED_15_1,Reserved for Future use" newline bitfld.word 0x0 0. "RX_RATE_IRQ_CLR,RX rate change interrupt clear (self-clearing)" "0,1" group.word 0xC228++0x1 line.word 0x0 "RAWLANE0_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR,RX pstate change interrupt clear" newline hexmask.word 0x0 1.--15. 1. "RESERVED_15_1,Reserved for Future use" newline bitfld.word 0x0 0. "RX_PSTATE_IRQ_CLR,RX pstate change interrupt clear (self-clearing)" "0,1" group.word 0xC22C++0x1 line.word 0x0 "RAWLANE0_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR,RX adaptation request interrupt clear" newline hexmask.word 0x0 1.--15. 1. "RESERVED_15_1,Reserved for Future use" newline bitfld.word 0x0 0. "RX_ADAPT_REQ_IRQ_CLR,RX adaptation request interrupt clear (self-clearing)" "0,1" group.word 0xC230++0x1 line.word 0x0 "RAWLANE0_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR,RX adaptation disable interrupt clear" newline hexmask.word 0x0 1.--15. 1. "RESERVED_15_1,Reserved for Future use" newline bitfld.word 0x0 0. "RX_ADAPT_DIS_IRQ_CLR,RX adaptation disable interrupt clear (self-clearing)" "0,1" group.word 0xC234++0x1 line.word 0x0 "RAWLANE0_DIG_IRQ_CTL_IRQ_MASK,Interrupt Mask" newline hexmask.word 0x0 7.--15. 1. "RESERVED_15_7,Reserved for Future use" newline bitfld.word 0x0 6. "LANE_XCVR_MODE_IRQ_MSK,Mask for lane_xcvr_mode interrupt (0 = cannot interrupt)" "cannot interrupt),?" newline bitfld.word 0x0 5. "RX_RESET_IRQ_MSK,Mask for Rx reset interrupt (0 = cannot interrupt)" "cannot interrupt),?" newline bitfld.word 0x0 4. "RX_ADAPT_DIS_IRQ_MSK,Mask for Rx adaptation disable interrupt (0 = cannot interrupt)" "cannot interrupt),?" newline bitfld.word 0x0 3. "RX_ADAPT_REQ_IRQ_MSK,Mask for Rx adaptation request interrupt (0 = cannot interrupt)" "cannot interrupt),?" newline bitfld.word 0x0 2. "RX_PSTATE_IRQ_MSK,Mask for Rx pstate change interrupt (0 = cannot interrupt)" "cannot interrupt),?" newline bitfld.word 0x0 1. "RX_RATE_IRQ_MSK,Mask for Rx rate change interrupt (0 = cannot interrupt)" "cannot interrupt),?" newline bitfld.word 0x0 0. "RX_REQ_IRQ_MSK,Mask for Rx request interrupt (0 = cannot interrupt)" "cannot interrupt),?" rgroup.word 0xC238++0x1 line.word 0x0 "RAWLANE0_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ,Lane transceiver mode interrupt" newline hexmask.word 0x0 1.--15. 1. "RESERVED_15_1,Reserved for Future use" newline bitfld.word 0x0 0. "LANE_XCVR_MODE_IRQ,Lane transceiver mode interrupt" "0,1" group.word 0xC23C++0x1 line.word 0x0 "RAWLANE0_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR,Lane transceiver mode interrupt clear" newline hexmask.word 0x0 1.--15. 1. "RESERVED_15_1,Reserved for Future use" newline bitfld.word 0x0 0. "LANE_XCVR_MODE_IRQ_CLR,Lane transceiver mode interrupt clear (self-clearing)" "0,1" group.word 0xC280++0x1 line.word 0x0 "RAWLANE0_DIG_PMA_XF_LANE_OVRD_IN,Override values for incoming LANE controls" newline hexmask.word 0x0 3.--15. 1. "RESERVED_15_3,Reserved for Future use" newline bitfld.word 0x0 2. "LANE_OVRD_EN,Override enable for signals in this register" "0,1" newline bitfld.word 0x0 1. "LANE_MPLLB_EN_IN,Override value for lane_mpllb_en_in" "0,1" newline bitfld.word 0x0 0. "LANE_MPLLA_EN_IN,Override value for lane_mplla_en_in" "0,1" group.word 0xC284++0x1 line.word 0x0 "RAWLANE0_DIG_PMA_XF_LANE_OVRD_OUT,Override values for outgoing LANE controls" newline hexmask.word 0x0 3.--15. 1. "RESERVED_15_3,Reserved for Future use" newline bitfld.word 0x0 2. "LANE_OVRD_EN,Override enable for signals in this register" "0,1" newline bitfld.word 0x0 1. "LANE_MPLLB_EN_OUT,Override value for lane_mpllb_en_out" "0,1" newline bitfld.word 0x0 0. "LANE_MPLLA_EN_OUT,Override value for lane_mplla_en_out" "0,1" group.word 0xC288++0x1 line.word 0x0 "RAWLANE0_DIG_PMA_XF_SUP_OVRD_IN,Override values for incoming SUP controls from PMA" newline hexmask.word 0x0 3.--15. 1. "RESERVED_15_3,Reserved for Future use" newline bitfld.word 0x0 2. "SUP_STATE_OVRD_EN,Override enable for signals in this register" "0,1" newline bitfld.word 0x0 1. "MPLLB_STATE,Override value for mpllb_state" "0,1" newline bitfld.word 0x0 0. "MPLLA_STATE,Override value for mplla_state" "0,1" rgroup.word 0xC28C++0x1 line.word 0x0 "RAWLANE0_DIG_PMA_XF_SUP_PMA_IN,Current values for incoming MPLL status controls from PMA" newline hexmask.word 0x0 2.--15. 1. "RESERVED_15_2,Reserved for Future use" newline bitfld.word 0x0 1. "MPLLB_STATE,Value from PMA for mpllb_state" "0,1" newline bitfld.word 0x0 0. "MPLLA_STATE,Value from PMA for mplla_state" "0,1" group.word 0xC290++0x1 line.word 0x0 "RAWLANE0_DIG_PMA_XF_TX_OVRD_OUT,Override values for outgoing TX controls to PMA" newline hexmask.word 0x0 4.--15. 1. "RESERVED_15_4,Reserved for Future use" newline bitfld.word 0x0 3. "TX_RESET_OVRD_EN,Override enable for tx_reset" "0,1" newline bitfld.word 0x0 2. "TX_RESET_OVRD_VAL,Override value for tx_reset" "0,1" newline bitfld.word 0x0 1. "TX_REQ_OVRD_EN,Override enable for tx_req" "0,1" newline bitfld.word 0x0 0. "TX_REQ_OVRD_VAL,Override value for tx_req" "0,1" rgroup.word 0xC294++0x1 line.word 0x0 "RAWLANE0_DIG_PMA_XF_TX_PMA_IN,Current values for coming TX status controls from PMA" newline hexmask.word 0x0 1.--15. 1. "RESERVED_15_1,Reserved for Future use" newline bitfld.word 0x0 0. "ACK,Value from PMA for tx_ack" "0,1" group.word 0xC298++0x1 line.word 0x0 "RAWLANE0_DIG_PMA_XF_RX_OVRD_OUT,Override values for outgoing RX controls to PMA" newline hexmask.word 0x0 4.--15. 1. "RESERVED_15_4,Reserved for Future use" newline bitfld.word 0x0 3. "RX_RESET_OVRD_EN,Override enable for rx_reset" "0,1" newline bitfld.word 0x0 2. "RX_RESET_OVRD_VAL,Override value for rx_reset" "0,1" newline bitfld.word 0x0 1. "RX_REQ_OVRD_EN,Override enable for rx_req" "0,1" newline bitfld.word 0x0 0. "RX_REQ_OVRD_VAL,Override value for rx_req" "0,1" rgroup.word 0xC29C++0x1 line.word 0x0 "RAWLANE0_DIG_PMA_XF_RX_PMA_IN,Current values for coming RX status controls from PMA" newline hexmask.word 0x0 1.--15. 1. "RESERVED_15_1,Reserved for Future use" newline bitfld.word 0x0 0. "ACK,Value from PMA for rx_ack" "0,1" group.word 0xC2A0++0x1 line.word 0x0 "RAWLANE0_DIG_PMA_XF_LANE_RTUNE_CTL,Lane Rtune Controls" newline hexmask.word 0x0 1.--15. 1. "RESERVED_15_1,Reserved for Future use" newline bitfld.word 0x0 0. "LANE_RTUNE_REQ,Lane value for rtune_req" "0,1" rgroup.word 0xC2A4++0x1 line.word 0x0 "RAWLANE0_DIG_PMA_XF_SUP_PMA_IN_1,Current values for incoming RTUNE status controls from PMA" newline hexmask.word 0x0 1.--15. 1. "RESERVED_15_1,Reserved for Future use" newline bitfld.word 0x0 0. "RTUNE_ACK,Value from PMA for rtune_ack" "0,1" rgroup.word 0xC2A8++0x1 line.word 0x0 "RAWLANE0_DIG_PMA_XF_SUP_PMA_RX_VALID,Current value of RX valid from PMA" newline hexmask.word 0x0 1.--15. 1. "RESERVED_15_1,Reserved for Future use" newline bitfld.word 0x0 0. "RX_VALID,Value of RX_VALID" "0,1" group.word 0xC300++0x1 line.word 0x0 "RAWLANE0_DIG_TX_CTL_TX_FSM_CTL,TX FSM Control" newline hexmask.word.byte 0x0 10.--15. 1. "RESERVED_15_10,Reserved for Future use" newline bitfld.word 0x0 9. "TX_P0_ALLOW_RXDET,If asserted then rxdet request is allowed in P0" "0,1" newline bitfld.word 0x0 8. "TX_P0S_ALLOW_RXDET,If asserted then rxdet request is allowed in P0S" "0,1" newline bitfld.word 0x0 7. "TX_P1_ALLOW_RXDET,If asserted then rxdet request is allowed in P1" "0,1" newline bitfld.word 0x0 6. "TX_P2_ALLOW_RXDET,If asserted then rxdet request is allowed in P2" "0,1" newline hexmask.word.byte 0x0 0.--5. 1. "TX_WAIT_MPLL_OFF_TIME,Number of ref_range cycles to wait for MPLL to turn off (When entering P2)." group.word 0xC304++0x1 line.word 0x0 "RAWLANE0_DIG_TX_CTL_TX_CLK_CTL,Select clock to act as TX input clock" newline hexmask.word 0x0 5.--15. 1. "RESERVED_15_5,Reserved for Future use" newline hexmask.word.byte 0x0 1.--4. 1. "TX_CLK_SEL,Select clock source for tx_pma_clk 0 - tx_pcs_clk (input clock from pcs) 1 - mplla_word_clk 2 - mplla_dword_clk 3 - mplla_qword_clk 4 - mplla_oword_clk 5 - mplla_div_clk 6 - mpllb_word_clk 7 - mpllb_dword_clk 8 - mpllb_qword_clk 9 -.." newline bitfld.word 0x0 0. "TX_CLK_EN,Enable the tx_clk to pma tx lane TX_CLK_EN must be deasserted when switching TX_CLK_SEL" "0,1" group.word 0xC380++0x1 line.word 0x0 "RAWLANE0_DIG_RX_CTL_RX_FSM_CTL,RX FSM control register" newline hexmask.word 0x0 2.--15. 1. "RESERVED_15_2,Reserved for Future use" newline bitfld.word 0x0 1. "RATE_CHG_IN_P1,When asserted then a rate change in P0/P0s will be sequenced such that the RX is put in P1 the rate change is applied and then the RX is returned to P0/P0s." "0,1" newline bitfld.word 0x0 0. "EN_RX_CTL_FSM,Enable the RX control FSM in the Raw PCS If enabled then when FSM detects a rate change it moves the RX to P1 does the rate change then goes back to P0/P0s. If not enabled then FSM is by-passed." "0,1" group.word 0xC384++0x1 line.word 0x0 "RAWLANE0_DIG_RX_CTL_RX_LOS_MASK_CTL,RX LOS Mask Control" newline hexmask.word.byte 0x0 9.--15. 1. "RESERVED_15_9,Reserved for Future use" newline hexmask.word 0x0 0.--8. 1. "RX_LOS_MASK_CNT,Number of cycles (ref_range_clk) to mask out the rx_los output from the time the los is powered-on. Default set for minimum 10us." group.word 0xC388++0x1 line.word 0x0 "RAWLANE0_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL,RX Data Enable Override Control" newline hexmask.word 0x0 5.--15. 1. "INT_REF_TRCK_CNT,Number of ref_range cycles to wait for integral reference tracking to settle." newline hexmask.word.byte 0x0 0.--4. 1. "RX_DATA_EN_OVRD_CNT,Number of ref_range cycles to override rx_data_en to 1." rgroup.word 0xC38C++0x1 line.word 0x0 "RAWLANE0_DIG_RX_CTL_OFFCAN_CONT_STATUS,RX continuous offset cancellation status" newline hexmask.word 0x0 1.--15. 1. "RESERVED_15_1,Reserved for Future use" newline bitfld.word 0x0 0. "ENABLE,Enable status for rx continous offset cancellation" "0,1" rgroup.word 0xC390++0x1 line.word 0x0 "RAWLANE0_DIG_RX_CTL_ADAPT_CONT_STATUS,RX continuous adaptation status" newline hexmask.word 0x0 1.--15. 1. "RESERVED_15_1,Reserved for Future use" newline bitfld.word 0x0 0. "ENABLE,Enable status for rx continous adaptation" "0,1" group.word 0xC400++0x1 line.word 0x0 "RAWLANE1_DIG_PCS_XF_TX_OVRD_IN,Override values for incoming TX controls from PCS" newline rbitfld.word 0x0 13.--15. "RESERVED_15_13,Reserved for Future use" "0,1,2,3,4,5,6,7" newline bitfld.word 0x0 12. "OVRD_EN,Override enable for all input signals below" "0,1" newline bitfld.word 0x0 11. "MSTR_MPLLB_STATE,Override value for tx_master_mpllb_state" "0,1" newline bitfld.word 0x0 10. "MSTR_MPLLA_STATE,Override value for tx_master_mplla_state" "0,1" newline bitfld.word 0x0 9. "MPLL_EN,Override value for tx_mpll_en" "0,1" newline bitfld.word 0x0 8. "MPLLB_SEL,Override value for tx_mpllb_sel" "0,1" newline bitfld.word 0x0 5.--7. "RATE,Override value for tx_rate" "0,1,2,3,4,5,6,7" newline bitfld.word 0x0 3.--4. "WIDTH,Override value for tx_width" "0,1,2,3" newline bitfld.word 0x0 2. "LPD,Override value for tx_lpd" "0,1" newline bitfld.word 0x0 0.--1. "PSTATE,Override value for tx_pstate" "0,1,2,3" group.word 0xC404++0x1 line.word 0x0 "RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_1,Override values for incoming TX controls from PCS. register #1" newline rbitfld.word 0x0 13.--15. "RESERVED_15_13,Reserved for Future use" "0,1,2,3,4,5,6,7" newline bitfld.word 0x0 12. "IBOOST_LVL_OVRD_EN,Override enable for tx_iboost_lvl[3:0]" "0,1" newline hexmask.word.byte 0x0 8.--11. 1. "IBOOST_LVL_OVRD_VAL,Override value for tx_iboost_lvl[3:0]" newline bitfld.word 0x0 7. "VBOOST_EN_OVRD_EN,Override enable for tx_vboost_en" "0,1" newline bitfld.word 0x0 6. "VBOOST_EN_OVRD_VAL,Override value for tx_vboost_en" "0,1" newline bitfld.word 0x0 5. "DETRX_REQ_OVRD_EN,Override enable for tx_detrx_req" "0,1" newline bitfld.word 0x0 4. "DETRX_REQ_OVRD_VAL,Override value for tx_detrx_req" "0,1" newline bitfld.word 0x0 3. "REQ_OVRD_EN,Override enable for tx_req" "0,1" newline bitfld.word 0x0 2. "REQ_OVRD_VAL,Override value for tx_req" "0,1" newline bitfld.word 0x0 1. "RESET_OVRD_EN,Override enable for tx_reset" "0,1" newline bitfld.word 0x0 0. "RESET_OVRD_VAL,Override value for tx_reset" "0,1" rgroup.word 0xC408++0x1 line.word 0x0 "RAWLANE1_DIG_PCS_XF_TX_PCS_IN,Current values for incoming TX controls from PCS" newline bitfld.word 0x0 15. "RESERVED_15_15,Reserved for Future use" "0,1" newline bitfld.word 0x0 14. "DETRX_REQ,Value from PCS for tx_detrx_req" "0,1" newline bitfld.word 0x0 13. "MSTR_MPLLB_STATE,Value from PCS for tx_master_mpllb_state" "0,1" newline bitfld.word 0x0 12. "MSTR_MPLLA_STATE,Value from PCS for tx_master_mplla_state" "0,1" newline bitfld.word 0x0 11. "MPLL_EN,Value from PCS for tx_mpll_en" "0,1" newline bitfld.word 0x0 10. "MPLLB_SEL,Value from PCS for tx_mpllb_sel" "0,1" newline bitfld.word 0x0 7.--9. "RATE,Value from PCS for tx_rate" "0,1,2,3,4,5,6,7" newline bitfld.word 0x0 5.--6. "WIDTH,Value from PCS for tx_width" "0,1,2,3" newline bitfld.word 0x0 4. "LPD,Value from PCS for tx_lpd" "0,1" newline bitfld.word 0x0 2.--3. "PSTATE,Value from PCS for tx_pstate" "0,1,2,3" newline bitfld.word 0x0 1. "REQ,Value from PCS for tx_req" "0,1" newline bitfld.word 0x0 0. "RESET,Value from PCS for tx_reset" "0,1" group.word 0xC40C++0x1 line.word 0x0 "RAWLANE1_DIG_PCS_XF_TX_OVRD_OUT,Override values for outgoing TX controls to PCS" newline hexmask.word 0x0 3.--15. 1. "RESERVED_15_3,Reserved for Future use" newline bitfld.word 0x0 2. "EN_CTL,Enable override values for all control outputs of this register" "0,1" newline bitfld.word 0x0 1. "DETRX_RESULT,Override value for tx_detrx_result" "0,1" newline bitfld.word 0x0 0. "ACK,Override value for tx_ack" "0,1" rgroup.word 0xC410++0x1 line.word 0x0 "RAWLANE1_DIG_PCS_XF_TX_PCS_OUT,Current values for outgoing TX status controls from Raw PCS" newline hexmask.word 0x0 1.--15. 1. "RESERVED_15_1,Reserved for Future use" newline bitfld.word 0x0 0. "ACK,Value from Raw PCS for tx_ack" "0,1" group.word 0xC414++0x1 line.word 0x0 "RAWLANE1_DIG_PCS_XF_RX_OVRD_IN,Override values for incoming RX controls from PCS" newline hexmask.word.byte 0x0 10.--15. 1. "RESERVED_15_10,Reserved for Future use" newline bitfld.word 0x0 9. "ADAPT_DFE_EN,Override value for rx_adapt_dfe_en" "0,1" newline bitfld.word 0x0 8. "ADAPT_AFE_EN,Override value for rx_adapt_afe_en" "0,1" newline bitfld.word 0x0 7. "OVRD_EN,Enable override values for all fields in this register" "0,1" newline bitfld.word 0x0 6. "LPD,Override value for rx_lpd" "0,1" newline bitfld.word 0x0 4.--5. "PSTATE,Override value for rx_pstate" "0,1,2,3" newline bitfld.word 0x0 2.--3. "WIDTH,Override value for rx_width" "0,1,2,3" newline bitfld.word 0x0 0.--1. "RATE,Override value for rx_rate" "0,1,2,3" group.word 0xC418++0x1 line.word 0x0 "RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_1,Override values for incoming RX controls from PCS. register #1" newline hexmask.word 0x0 4.--15. 1. "RESERVED_15_4,Reserved for Future use" newline bitfld.word 0x0 3. "REQ_OVRD_EN,Override enable for rx_req" "0,1" newline bitfld.word 0x0 2. "REQ_OVRD_VAL,Override value for rx_req" "0,1" newline bitfld.word 0x0 1. "RESET_OVRD_EN,Override enable for rx_reset" "0,1" newline bitfld.word 0x0 0. "RESET_OVRD_VAL,Override value for rx_reset" "0,1" group.word 0xC41C++0x1 line.word 0x0 "RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_2,Override values for incoming RX controls from PCS. register #2" newline bitfld.word 0x0 15. "VCO_LOWFREQ_VAL_OVRD_EN,Enable override for rx_cdr_vco_lowfreq" "0,1" newline bitfld.word 0x0 14. "VCO_LOWFREQ_VAL_OVRD,Override value for rx_cdr_vco_lowfreq" "0,1" newline bitfld.word 0x0 13. "VCO_LD_VAL_OVRD_EN,Enable override for rx_vco_ld_val" "0,1" newline hexmask.word 0x0 0.--12. 1. "VCO_LD_VAL_OVRD,Override value for rx_vco_ld_val" group.word 0xC420++0x1 line.word 0x0 "RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_3,Override values for incoming RX controls from PCS. register #3" newline bitfld.word 0x0 15. "CONT_OVRD_EN,Enable override values for rx_adapt_cont and rx_offcan_cont" "0,1" newline bitfld.word 0x0 14. "OFFCAN_CONT,Override value for rx_offcan_cont" "0,1" newline bitfld.word 0x0 13. "ADAPT_CONT,Override value for rx_adapt_cont" "0,1" newline bitfld.word 0x0 12. "ADAPT_REQ_OVRD_EN,Enable override values for rx_adapt_req" "0,1" newline bitfld.word 0x0 11. "ADAPT_REQ,Override value for rx_adapt_req" "0,1" newline bitfld.word 0x0 10. "REF_LD_VAL_OVRD_EN,Enable override for rx_ref_ld_val" "0,1" newline hexmask.word.byte 0x0 4.--9. 1. "REF_LD_VAL_OVRD,Override value for rx_ref_ld_val" newline bitfld.word 0x0 3. "RX_LOS_THRSHLD_OVRD_EN,Enable override for rx_los_threshold" "0,1" newline bitfld.word 0x0 0.--2. "RX_LOS_THRSHLD_OVRD_VAL,Override value for rx_los_threshold" "0,1,2,3,4,5,6,7" rgroup.word 0xC424++0x1 line.word 0x0 "RAWLANE1_DIG_PCS_XF_RX_PCS_IN,Current values for incoming RX controls from PCS" newline bitfld.word 0x0 15. "RESERVED_15_15,Reserved for Future use" "0,1" newline bitfld.word 0x0 14. "RESET,Value from PCS for rx_reset" "0,1" newline bitfld.word 0x0 13. "OFFCAN_CONT,Value from PCS for rx_offcan_cont" "0,1" newline bitfld.word 0x0 12. "ADAPT_CONT,Value from PCS for rx_adapt_cont" "0,1" newline bitfld.word 0x0 11. "ADAPT_REQ,Value from PCS for rx_adapt_req" "0,1" newline bitfld.word 0x0 10. "ADAPT_DFE_EN,Value from PCS for rx_adapt_dfe_en" "0,1" newline bitfld.word 0x0 9. "ADAPT_AFE_EN,Value from PCS for rx_adapt_afe_en" "0,1" newline bitfld.word 0x0 8. "CDR_VCO_LOWFREQ,Value from PCS for rx_cdr_vco_lowfreq" "0,1" newline bitfld.word 0x0 7. "LPD,Value from PCS for rx_lpd" "0,1" newline bitfld.word 0x0 5.--6. "PSTATE,Value from PCS for rx_pstate" "0,1,2,3" newline bitfld.word 0x0 3.--4. "WIDTH,Value from PCS for rx_width" "0,1,2,3" newline bitfld.word 0x0 1.--2. "RATE,Value from PCS for rx_rate" "0,1,2,3" newline bitfld.word 0x0 0. "REQ,Value from PCS for rx_req" "0,1" rgroup.word 0xC428++0x1 line.word 0x0 "RAWLANE1_DIG_PCS_XF_RX_PCS_IN_1,Current values for incoming RX controls from PCS. register #1" newline hexmask.word 0x0 6.--15. 1. "RESERVED_15_6,Reserved for Future use" newline hexmask.word.byte 0x0 0.--5. 1. "REF_LD_VAL,Value from PCS for rx_ref_ld_val" rgroup.word 0xC42C++0x1 line.word 0x0 "RAWLANE1_DIG_PCS_XF_RX_PCS_IN_2,Current values for incoming RX controls from PCS. register #2" newline bitfld.word 0x0 13.--15. "RESERVED_15_13,Reserved for Future use" "0,1,2,3,4,5,6,7" newline hexmask.word 0x0 0.--12. 1. "VCO_LD_VAL,Value from PCS for rx_vco_ld_val" rgroup.word 0xC430++0x1 line.word 0x0 "RAWLANE1_DIG_PCS_XF_RX_PCS_IN_3,Current values for incoming RX controls from PCS. register #3" newline hexmask.word.byte 0x0 11.--15. 1. "EQ_CTLE_BOOST,Value from ASIC for rx_eq_ctle_boost" newline hexmask.word.byte 0x0 7.--10. 1. "EQ_VGA2_GAIN,Value from ASIC for rx_eq_vga2_gain" newline hexmask.word.byte 0x0 3.--6. 1. "EQ_VGA1_GAIN,Value from ASIC for rx_eq_vga1_gain" newline bitfld.word 0x0 0.--2. "EQ_ATT_LVL,Value from ASIC for rx_eq_att_lvl" "0,1,2,3,4,5,6,7" rgroup.word 0xC434++0x1 line.word 0x0 "RAWLANE1_DIG_PCS_XF_RX_PCS_IN_4,Current values for incoming RX controls from PCS. register #4" newline hexmask.word.byte 0x0 11.--15. 1. "RESERVED_15_11,Reserved for Future use" newline hexmask.word.byte 0x0 3.--10. 1. "EQ_DFE_TAP1,Value from ASIC for rx_eq_dfe_tap1" newline bitfld.word 0x0 0.--2. "EQ_CTLE_POLE,Value from ASIC for rx_eq_ctle_pole" "0,1,2,3,4,5,6,7" group.word 0xC438++0x1 line.word 0x0 "RAWLANE1_DIG_PCS_XF_RX_OVRD_OUT,Override values for outgoing RX controls to PCS" newline hexmask.word 0x0 2.--15. 1. "RESERVED_15_2,Reserved for Future use" newline bitfld.word 0x0 1. "EN_CTL,Enable override values for all control outputs of this register" "0,1" newline bitfld.word 0x0 0. "ACK,Override value for rx_ack" "0,1" rgroup.word 0xC43C++0x1 line.word 0x0 "RAWLANE1_DIG_PCS_XF_RX_PCS_OUT,Current values for outgoing RX status controls from Raw PCS" newline hexmask.word 0x0 1.--15. 1. "RESERVED_15_1,Reserved for Future use" newline bitfld.word 0x0 0. "ACK,Value from Raw PCS for rx_ack" "0,1" group.word 0xC440++0x1 line.word 0x0 "RAWLANE1_DIG_PCS_XF_RX_ADAPT_ACK,RX Adaptation Acknowledge" newline hexmask.word 0x0 1.--15. 1. "RESERVED_15_1,Reserved for Future use" newline bitfld.word 0x0 0. "RX_ADAPT_ACK,RX Adaptation Acknowledge" "0,1" group.word 0xC444++0x1 line.word 0x0 "RAWLANE1_DIG_PCS_XF_RX_ADAPT_FOM,RX Adaptation Figure of Merit" newline hexmask.word.byte 0x0 8.--15. 1. "RESERVED_15_8,Reserved for Future use" newline hexmask.word.byte 0x0 0.--7. 1. "RX_ADAPT_FOM,RX Adaptation Figure of Merit" group.word 0xC448++0x1 line.word 0x0 "RAWLANE1_DIG_PCS_XF_RX_TXPRE_DIR,RX calculated direction for TX-pre" newline hexmask.word 0x0 2.--15. 1. "RESERVED_15_2,Reserved for Future use" newline bitfld.word 0x0 0.--1. "RX_TXPRE_DIR,RX calculated direction for TX-pre 00 - No change 01 - Increment 10 - Decrement 11 - Reserved" "No change,Increment,?,?" group.word 0xC44C++0x1 line.word 0x0 "RAWLANE1_DIG_PCS_XF_RX_TXMAIN_DIR,RX calculated direction for TX-Main" newline hexmask.word 0x0 2.--15. 1. "RESERVED_15_2,Reserved for Future use" newline bitfld.word 0x0 0.--1. "RX_TXMAIN_DIR,RX calculated direction for TX-Main 00 - No change 01 - Increment 10 - Decrement 11 - Reserved" "No change,Increment,?,?" group.word 0xC450++0x1 line.word 0x0 "RAWLANE1_DIG_PCS_XF_RX_TXPOST_DIR,RX calculated direction for TX-Post" newline hexmask.word 0x0 2.--15. 1. "RESERVED_15_2,Reserved for Future use" newline bitfld.word 0x0 0.--1. "RX_TXPOST_DIR,RX calculated direction for TX-Post 00 - No change 01 - Increment 10 - Decrement 11 - Reserved" "No change,Increment,?,?" rgroup.word 0xC454++0x1 line.word 0x0 "RAWLANE1_DIG_PCS_XF_LANE_NUMBER,Current lane number" newline hexmask.word 0x0 4.--15. 1. "RESERVED_15_4,Reserved for Future use" newline hexmask.word.byte 0x0 0.--3. 1. "LANE_NUMBER,Current lane number" group.word 0xC458++0x1 line.word 0x0 "RAWLANE1_DIG_PCS_XF_LANE_XCVR_MODE_OVRD_IN,Override incoming values for lane_xcvr_mode" newline hexmask.word 0x0 3.--15. 1. "RESERVED_15_3,Reserved for Future use" newline bitfld.word 0x0 2. "LANE_XCVR_MODE_OVRD_EN,Enable override value for lane_xcvr_mode" "0,1" newline bitfld.word 0x0 0.--1. "LANE_XCVR_MODE_OVRD_VAL,Override value for lane_xcvr_mode" "0,1,2,3" rgroup.word 0xC45C++0x1 line.word 0x0 "RAWLANE1_DIG_PCS_XF_LANE_XCVR_MODE_IN,Lane transceiver mode status" newline hexmask.word 0x0 2.--15. 1. "RESERVED_15_2,Reserved for Future use" newline bitfld.word 0x0 0.--1. "LANE_XCVR_MODE,Lane transceiver mode Determines whether this lane is being used as Tx Rx or Tx/Rx 00 - Reserved 01 - Lane is used for Tx only 10 - Lane is used for Rx only 11 - Lane is used for Tx/Rx" "Reserved,Lane is used for Tx only,?,?" group.word 0xC460++0x1 line.word 0x0 "RAWLANE1_DIG_PCS_XF_ATE_OVRD_IN,ATE Override input to control top-level inputs" newline hexmask.word.byte 0x0 12.--15. 1. "RESERVED_15_12,Reserved for Future use" newline bitfld.word 0x0 11. "RX_ADAPT_DFE_EN_OVRD_EN,Enable override value for rx_adapt_dfe_en input" "0,1" newline bitfld.word 0x0 10. "RX_ADAPT_DFE_EN_OVRD_VAL,Override value for rx_adapt_dfe_en input" "0,1" newline bitfld.word 0x0 9. "RX_ADAPT_AFE_EN_OVRD_EN,Enable override value for rx_adapt_afe_en input" "0,1" newline bitfld.word 0x0 8. "RX_ADAPT_AFE_EN_OVRD_VAL,Override value for rx_adapt_afe_en input" "0,1" newline bitfld.word 0x0 7. "TX_REQ_ATE_OVRD_EN,Enable override value for tx_req input" "0,1" newline bitfld.word 0x0 6. "TX_REQ_ATE_OVRD_VAL,Override value for top-level tx_req input" "0,1" newline bitfld.word 0x0 5. "RX_REQ_ATE_OVRD_EN,Enable override value for rx_req input" "0,1" newline bitfld.word 0x0 4. "RX_REQ_ATE_OVRD_VAL,Override value for top-level rx_req input" "0,1" newline bitfld.word 0x0 3. "TX_RESET_ATE_OVRD_EN,Enable override value for tx_reset input" "0,1" newline bitfld.word 0x0 2. "TX_RESET_ATE_OVRD_VAL,Override value for top-level tx_reset input" "0,1" newline bitfld.word 0x0 1. "RX_RESET_ATE_OVRD_EN,Enable override value for rx_reset input" "0,1" newline bitfld.word 0x0 0. "RX_RESET_ATE_OVRD_VAL,Override value for top-level rx_reset input" "0,1" group.word 0xC464++0x1 line.word 0x0 "RAWLANE1_DIG_PCS_XF_RX_EQ_DELTA_IQ_OVRD_IN,Override incoming values for rx_eq_delta_iq" newline hexmask.word 0x0 5.--15. 1. "RESERVED_15_5,Reserved for Future use" newline bitfld.word 0x0 4. "RX_EQ_DELTA_IQ_OVRD_EN,Enable override value for rx_eq_delta_iq" "0,1" newline hexmask.word.byte 0x0 0.--3. 1. "RX_EQ_DELTA_IQ_OVRD_VAL,Override value for rx_eq_delta_iq" group.word 0xC468++0x1 line.word 0x0 "RAWLANE1_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN,Override incoming values for tx/rx_term_ctrl" newline hexmask.word.byte 0x0 8.--15. 1. "RESERVED_15_8,Reserved for Future use" newline bitfld.word 0x0 7. "TX_TERM_CTRL_OVRD_EN,Enable override value for tx_term_ctrl" "0,1" newline bitfld.word 0x0 4.--6. "TX_TERM_CTRL_OVRD_VAL,Override value for tx_term_ctrl" "0,1,2,3,4,5,6,7" newline bitfld.word 0x0 3. "RX_TERM_CTRL_OVRD_EN,Enable override value for rx_term_ctrl" "0,1" newline bitfld.word 0x0 0.--2. "RX_TERM_CTRL_OVRD_VAL,Override value for rx_term_ctrl" "0,1,2,3,4,5,6,7" rgroup.word 0xC46C++0x1 line.word 0x0 "RAWLANE1_DIG_PCS_XF_TXRX_TERM_CTRL_IN,tx/rx_term_ctrl status" newline hexmask.word 0x0 6.--15. 1. "RESERVED_15_6,Reserved for Future use" newline bitfld.word 0x0 3.--5. "TX_TERM_CTRL,tx_term_ctrl value" "0,1,2,3,4,5,6,7" newline bitfld.word 0x0 0.--2. "RX_TERM_CTRL,tx_term_ctrl value" "0,1,2,3,4,5,6,7" group.word 0xC470++0x1 line.word 0x0 "RAWLANE1_DIG_PCS_XF_RX_OVRD_OUT_1,Override values for outgoing RX controls to PCS. register #1" newline hexmask.word 0x0 1.--15. 1. "RESERVED_15_1,Reserved for Future use" newline bitfld.word 0x0 0. "RX_CLK_EN,Enable the outging rx_clk" "0,1" group.word 0xC474++0x1 line.word 0x0 "RAWLANE1_DIG_PCS_XF_RX_EQ_OVRD_IN_1,Override values for incoming RX EQ controls from PCS. register #1" newline hexmask.word.byte 0x0 8.--15. 1. "RESERVED_15_8,Reserved for Future use" newline bitfld.word 0x0 7. "RX_EQ_OVRD_EN,Enable override values for all RX EQ settings" "0,1" newline bitfld.word 0x0 4.--6. "RX_EQ_ATT_LVL_OVRD_VAL,Override value for rx_eq_att_lvl[2:0]" "0,1,2,3,4,5,6,7" newline hexmask.word.byte 0x0 0.--3. 1. "RX_EQ_AFE_GAIN_OVRD_VAL,Override value for rx_eq_afe_gain[3:0]" group.word 0xC478++0x1 line.word 0x0 "RAWLANE1_DIG_PCS_XF_RX_EQ_OVRD_IN_2,Override values for incoming RX EQ controls from PCS. register #2" newline rbitfld.word 0x0 13.--15. "RESERVED_15_13,Reserved for Future use" "0,1,2,3,4,5,6,7" newline hexmask.word.byte 0x0 8.--12. 1. "RX_EQ_CTLE_BOOST_OVRD_VAL,Override value for rx_eq_ctle_boost[4:0]" newline hexmask.word.byte 0x0 0.--7. 1. "RX_EQ_DFE_TAP1_OVRD_VAL,Override value for rx_eq_dfe_tap1[7:0]" group.word 0xC47C++0x1 line.word 0x0 "RAWLANE1_DIG_PCS_XF_RX_OVRD_OUT_2,Override value for RX VALID/DATA_EN/DATA_EN_ATE signal from PCS" newline hexmask.word.byte 0x0 11.--15. 1. "RESERVED_15_11,Reserved for Future use" newline bitfld.word 0x0 10. "RX_RATE_ATE_OVRD_EN,Override enable for rx_rate_ate" "0,1" newline bitfld.word 0x0 8.--9. "RX_RATE_ATE_OVRD_VAL,Override value for rx_rate_ate" "0,1,2,3" newline bitfld.word 0x0 7. "RX_CDR_TRACK_EN_ATE_OVRD_EN,Override enable for rx_cdr_track_en_ate" "0,1" newline bitfld.word 0x0 6. "RX_CDR_TRACK_EN_ATE_OVRD_VAL,Override value for rx_cdr_track_en_ate" "0,1" newline bitfld.word 0x0 5. "RX_DATA_EN_ATE_OVRD_EN,Override enable for rx_data_en_ate" "0,1" newline bitfld.word 0x0 4. "RX_DATA_EN_ATE_OVRD_VAL,Override value for rx_data_en_ate" "0,1" newline bitfld.word 0x0 3. "RX_DATA_EN_OVRD_EN,Override enable for rx_data_en" "0,1" newline bitfld.word 0x0 2. "RX_DATA_EN_OVRD_VAL,Override value for rx_data_en" "0,1" newline bitfld.word 0x0 1. "RX_VALID_OVRD_EN,Override enable for rx_valid" "0,1" newline bitfld.word 0x0 0. "RX_VALID_OVRD_VAL,Override value for rx_valid" "0,1" group.word 0xC480++0x1 line.word 0x0 "RAWLANE1_DIG_FSM_FSM_OVRD_CTL,FSM override control register" newline rbitfld.word 0x0 15. "RESERVED_15_15,Reserved for Future use" "0,1" newline bitfld.word 0x0 14. "FSM_OVRD_EN,Enable overriding the FSM execution of commands Must be asserted to use FSM_CMD_START and FSM_JMP_EN features" "0,1" newline bitfld.word 0x0 13. "FSM_CMD_START,Start executing the new command This is a self-clearing bit" "0,1" newline bitfld.word 0x0 12. "FSM_JMP_EN,Force the FSM to jump to FSM_JMP_ADDR in the program memory Is applied when FSM_CMD_START is pulsed." "0,1" newline hexmask.word 0x0 0.--11. 1. "FSM_JMP_ADDR,The jump address used when FSM_JUMP_EN=1 The address is encoded as follows: [11:8] mem_lane [7:5] bank [4:0] register" rgroup.word 0xC484++0x1 line.word 0x0 "RAWLANE1_DIG_FSM_MEM_ADDR_MON,Memory Address Monitor" newline hexmask.word 0x0 0.--15. 1. "MEM_ADDR,Current value of memory address used in Lane FSM" rgroup.word 0xC488++0x1 line.word 0x0 "RAWLANE1_DIG_FSM_STATUS_MON,FSM Status Monitor" newline hexmask.word.byte 0x0 11.--15. 1. "RESERVED_15_11,Reserved for Future use" newline bitfld.word 0x0 10. "RDMSK_DISABLED,Check if read mask is currently disabled (i.e. mask is all ones)" "0,1" newline bitfld.word 0x0 9. "WRMSK_DISABLED,Check if write mask is currently disabled (i.e. mask is all ones)" "0,1" newline bitfld.word 0x0 8. "WAIT_CNT_EQ0,Check if wait counter currently equals zero" "0,1" newline bitfld.word 0x0 7. "ALU_RES_EQ0,Check if ALU result register currently equals zero" "0,1" newline bitfld.word 0x0 6. "ALU_OVFLW,Current value of ALU overflow bit" "0,1" newline bitfld.word 0x0 5. "CMD_RDY,New command is ready for execution (applicable when FSM_OVRD_EN=1)" "0,1" newline hexmask.word.byte 0x0 0.--4. 1. "STATE,Current state of Lane FSM" rgroup.word 0xC48C++0x1 line.word 0x0 "RAWLANE1_DIG_FSM_FAST_RX_STARTUP_CAL,Status of Fast RX Start Up Calibration" newline hexmask.word 0x0 1.--15. 1. "RESERVED_15_1,Reserved for Future use" newline bitfld.word 0x0 0. "FAST_RX_STARTUP_CAL,Status of fast RX start-up calibration" "0,1" rgroup.word 0xC490++0x1 line.word 0x0 "RAWLANE1_DIG_FSM_FAST_RX_ADAPT,Status of Fast RX Adaptation" newline hexmask.word 0x0 1.--15. 1. "RESERVED_15_1,Reserved for Future use" newline bitfld.word 0x0 0. "FAST_RX_ADAPT,Status of fast RX adaptation" "0,1" rgroup.word 0xC494++0x1 line.word 0x0 "RAWLANE1_DIG_FSM_FAST_RX_AFE_CAL,Status of Fast RX AFE Calibration" newline hexmask.word 0x0 1.--15. 1. "RESERVED_15_1,Reserved for Future use" newline bitfld.word 0x0 0. "FAST_RX_AFE_CAL,Status of fast RX AFE DAC start-up calibration" "0,1" rgroup.word 0xC498++0x1 line.word 0x0 "RAWLANE1_DIG_FSM_FAST_RX_DFE_CAL,Status of Fast RX DFE Calibration" newline hexmask.word 0x0 1.--15. 1. "RESERVED_15_1,Reserved for Future use" newline bitfld.word 0x0 0. "FAST_RX_DFE_CAL,Status of fast RX DFE slicer start-up calibration" "0,1" rgroup.word 0xC49C++0x1 line.word 0x0 "RAWLANE1_DIG_FSM_FAST_RX_DFE_RE_ADAPT,Enables fast RX DFE re -adaptation" newline hexmask.word 0x0 1.--15. 1. "RESERVED_15_1,Reserved for Future use" newline bitfld.word 0x0 0. "FAST_RX_DFE_RE_ADAPT,Enables fast RX DFE re -adaptation" "0,1" rgroup.word 0xC4A0++0x1 line.word 0x0 "RAWLANE1_DIG_FSM_FAST_RX_REFLVL_CAL,Status of Fast RX Reference Level Calibration" newline hexmask.word 0x0 1.--15. 1. "RESERVED_15_1,Reserved for Future use" newline bitfld.word 0x0 0. "FAST_RX_REFLVL_CAL,Status of fast RX reference level (100mv 125mv 150mv) start-up calibration" "0,1" rgroup.word 0xC4A4++0x1 line.word 0x0 "RAWLANE1_DIG_FSM_FAST_RX_IQ_CAL,Status of Fast RX IQ Calibration" newline hexmask.word 0x0 1.--15. 1. "RESERVED_15_1,Reserved for Future use" newline bitfld.word 0x0 0. "FAST_RX_IQ_CAL,Status of fast RX IQ start-up calibration" "0,1" rgroup.word 0xC4A8++0x1 line.word 0x0 "RAWLANE1_DIG_FSM_FAST_RX_AFE_ADAPT,Status of Fast RX AFE Adaptation" newline hexmask.word 0x0 1.--15. 1. "RESERVED_15_1,Reserved for Future use" newline bitfld.word 0x0 0. "FAST_RX_AFE_ADAPT,Status of fast RX AFE DAC start-up adaptation" "0,1" rgroup.word 0xC4AC++0x1 line.word 0x0 "RAWLANE1_DIG_FSM_FAST_RX_DFE_ADAPT,Status of Fast RX DFE Adaptation" newline hexmask.word 0x0 1.--15. 1. "RESERVED_15_1,Reserved for Future use" newline bitfld.word 0x0 0. "FAST_RX_DFE_ADAPT,Status of fast RX DFE DAC start-up adaptation" "0,1" rgroup.word 0xC4B0++0x1 line.word 0x0 "RAWLANE1_DIG_FSM_FAST_SUP,Status of Fast Support block" newline hexmask.word 0x0 1.--15. 1. "RESERVED_15_1,Reserved for Future use" newline bitfld.word 0x0 0. "FAST_SUP,Status of fast Support block (MPLL and Rtune)" "0,1" rgroup.word 0xC4B4++0x1 line.word 0x0 "RAWLANE1_DIG_FSM_FAST_TX_CMN_MODE,Status of Fast TX Common-mode Charge-up" newline hexmask.word 0x0 1.--15. 1. "RESERVED_15_1,Reserved for Future use" newline bitfld.word 0x0 0. "FAST_TX_CMN_MODE,Status of fast TX Common-mode Charge-up" "0,1" rgroup.word 0xC4B8++0x1 line.word 0x0 "RAWLANE1_DIG_FSM_FAST_TX_RXDET,Status of Fast TX detect RX" newline hexmask.word 0x0 1.--15. 1. "RESERVED_15_1,Reserved for Future use" newline bitfld.word 0x0 0. "FAST_TX_RXDET,Status of fast TX detect RX" "0,1" rgroup.word 0xC4BC++0x1 line.word 0x0 "RAWLANE1_DIG_FSM_FAST_RX_PWRUP,Status of Fast RX Power-up" newline hexmask.word 0x0 1.--15. 1. "RESERVED_15_1,Reserved for Future use" newline bitfld.word 0x0 0. "FAST_RX_PWRUP,Status of fast RX Power-up (LOS VREG/AFE and DCC)" "0,1" rgroup.word 0xC4C0++0x1 line.word 0x0 "RAWLANE1_DIG_FSM_FAST_RX_VCO_WAIT,Status of Fast RX VCO Wait Times" newline hexmask.word 0x0 1.--15. 1. "RESERVED_15_1,Reserved for Future use" newline bitfld.word 0x0 0. "FAST_RX_VCO_WAIT,Status of fast RX VCO wait times" "0,1" rgroup.word 0xC4C4++0x1 line.word 0x0 "RAWLANE1_DIG_FSM_FAST_RX_VCO_CAL,Status of Fast RX VCO Calibration" newline hexmask.word 0x0 1.--15. 1. "RESERVED_15_1,Reserved for Future use" newline bitfld.word 0x0 0. "FAST_RX_VCO_CAL,Status of fast RX VCO Calibration" "0,1" rgroup.word 0xC4C8++0x1 line.word 0x0 "RAWLANE1_DIG_FSM_CMNCAL_MPLL_STATUS,Status of MPLL common calibration initiation" newline hexmask.word 0x0 2.--15. 1. "RESERVED_15_2,Reserved for Future use" newline bitfld.word 0x0 1. "CMNCAL_MPLL_DONE,Indicates whether MPLL common calibration has been completed by any lane or not." "0,1" newline bitfld.word 0x0 0. "CMNCAL_MPLL_INIT,Indicates whether MPLL common calibration has been started by any lane or not. ---------------------------------------------------------------------" "0,1" rgroup.word 0xC4CC++0x1 line.word 0x0 "RAWLANE1_DIG_FSM_FAST_RX_CONT_CAL_ADAPT,Status of Fast RX Continuous Calibration/Adaptation" newline hexmask.word 0x0 1.--15. 1. "RESERVED_15_1,Reserved for Future use" newline bitfld.word 0x0 0. "FAST_RX_CONT_CAL_ADAPT,Status of fast RX continuous calibration/adaptation" "0,1" rgroup.word 0xC4D0++0x1 line.word 0x0 "RAWLANE1_DIG_FSM_FAST_RX_CONT_ADAPT,Status of Fast RX Continuous Adaptation" newline hexmask.word 0x0 1.--15. 1. "RESERVED_15_1,Reserved for Future use" newline bitfld.word 0x0 0. "FAST_RX_CONT_ADAPT,Status of fast RX continuous adaptation" "0,1" rgroup.word 0xC4D4++0x1 line.word 0x0 "RAWLANE1_DIG_FSM_FAST_RX_CONT_DATA_CAL,Status of Fast RX Continuous Data Calibration" newline hexmask.word 0x0 1.--15. 1. "RESERVED_15_1,Reserved for Future use" newline bitfld.word 0x0 0. "FAST_RX_CONT_DATA_CAL,Status of fast RX continuous data calibration" "0,1" rgroup.word 0xC4D8++0x1 line.word 0x0 "RAWLANE1_DIG_FSM_FAST_RX_CONT_PHASE_CAL,Status of Fast RX Continuous Phase Calibration" newline hexmask.word 0x0 1.--15. 1. "RESERVED_15_1,Reserved for Future use" newline bitfld.word 0x0 0. "FAST_RX_CONT_PHASE_CAL,Status of fast RX continuous phase calibration" "0,1" rgroup.word 0xC4DC++0x1 line.word 0x0 "RAWLANE1_DIG_FSM_FAST_RX_CONT_AFE_CAL,Status of Fast RX Continuous AFE Calibration" newline hexmask.word 0x0 1.--15. 1. "RESERVED_15_1,Reserved for Future use" newline bitfld.word 0x0 0. "FAST_RX_CONT_AFE_CAL,Status of fast RX continuous AFE calibration" "0,1" rgroup.word 0xC4E0++0x1 line.word 0x0 "RAWLANE1_DIG_FSM_FAST_RX_IQ_ADAPT,Status of Fast RX IQ_ADAPT" newline hexmask.word 0x0 1.--15. 1. "RESERVED_15_1,Reserved for Future use" newline bitfld.word 0x0 0. "FAST_RX_IQ_ADAPT,Status of Fast RX IQ_ADAPT" "0,1" rgroup.word 0xC4E4++0x1 line.word 0x0 "RAWLANE1_DIG_FSM_RX_IQ_DELTA_ADD,Status of RX Delta addition" newline hexmask.word 0x0 1.--15. 1. "RESERVED_15_1,Reserved for Future use" newline bitfld.word 0x0 0. "RX_IQ_DELTA_ADD,Reserved" "0,1" rgroup.word 0xC4E8++0x1 line.word 0x0 "RAWLANE1_DIG_FSM_FAST_RX_ATT_ADAPT,Enables fast RX ATT adaptation" newline hexmask.word 0x0 1.--15. 1. "RESERVED_15_1,Reserved for Future use" newline bitfld.word 0x0 0. "FAST_RX_ATT_ADAPT,Enables fast RX ATT adaptation" "0,1" rgroup.word 0xC4EC++0x1 line.word 0x0 "RAWLANE1_DIG_FSM_FAST_RX_CTLE_ADAPT,Enables fast RX CTLE adaptation" newline hexmask.word 0x0 1.--15. 1. "RESERVED_15_1,Reserved for Future use" newline bitfld.word 0x0 0. "FAST_RX_CTLE_ADAPT,Enables fast RX CTLE adaptation" "0,1" group.word 0xC4F0++0x1 line.word 0x0 "RAWLANE1_DIG_FSM_CR_REG_OP_XTND_EN,CR interface timing extension enable" newline hexmask.word 0x0 1.--15. 1. "RESERVED_15_1,Reserved for Future use" newline bitfld.word 0x0 0. "CR_REG_OP_XTND_EN,CR interface timing extension enable 1'b0 - No Timing extension 1'b1 - Timing extension" "No Timing extension,Timing extension" group.word 0xC4F4++0x1 line.word 0x0 "RAWLANE1_DIG_FSM_TX_EQ_UPDATE_FLAG,TX Eq update flag" newline hexmask.word 0x0 1.--15. 1. "RESERVED_15_1,Reserved for Future use" newline bitfld.word 0x0 0. "TX_EQ_UPDATE_FLAG,Tx Eq update flag 1'b0 - Update tx eq post 1'b1 - Update tx eq pre" "Update tx eq post,Update tx eq pre" rgroup.word 0xC4F8++0x1 line.word 0x0 "RAWLANE1_DIG_FSM_CMNCAL_RCAL_STATUS,Status of RTUNE common calibration initiation" newline hexmask.word 0x0 2.--15. 1. "RESERVED_15_2,Reserved for Future use" newline bitfld.word 0x0 1. "CMNCAL_RCAL_DONE,Indicates whether RTUNE common calibration has been completed by any lane or not." "0,1" newline bitfld.word 0x0 0. "CMNCAL_RCAL_INIT,Indicates whether RTUNE common calibration has been started by any lane or not. ---------------------------------------------------------------------" "0,1" rgroup.word 0xC4FC++0x1 line.word 0x0 "RAWLANE1_DIG_FSM_RX_IQ_PHASE_OFFSET,Offset value for IQ Phase Calculation" newline hexmask.word 0x0 4.--15. 1. "RESERVED_15_4,Reserved for Future use" newline hexmask.word.byte 0x0 0.--3. 1. "RX_IQ_PHASE_OFFSET,Offset value for IQ Phase Calculation" group.word 0xC500++0x1 line.word 0x0 "RAWLANE1_DIG_AON_AFE_ATT_IDAC_OFST,Offset value for RX AFE ATT iDAC" newline hexmask.word.byte 0x0 8.--15. 1. "RESERVED_15_8,Reserved for Future use" newline hexmask.word.byte 0x0 0.--7. 1. "AFE_ATT_IDAC_OFST,Offset value for AFE ATT iDAC" group.word 0xC504++0x1 line.word 0x0 "RAWLANE1_DIG_AON_AFE_CTLE_IDAC_OFST,Offset value for RX AFE CTLE iDAC" newline hexmask.word.byte 0x0 8.--15. 1. "RESERVED_15_8,Reserved for Future use" newline hexmask.word.byte 0x0 0.--7. 1. "AFE_CTLE_IDAC_OFST,Offset value for AFE CTLE iDAC" group.word 0xC508++0x1 line.word 0x0 "RAWLANE1_DIG_AON_ADAPT_REF_LVL_DAC_CODE,Reference level for RX AFE Adaptation" newline hexmask.word.byte 0x0 8.--15. 1. "RESERVED_15_8,Reserved for Future use" newline hexmask.word.byte 0x0 0.--7. 1. "ADAPT_REF_LVL_DAC_CODE,Reference level for RX AFE Adaptation" group.word 0xC50C++0x1 line.word 0x0 "RAWLANE1_DIG_AON_RX_ADAPT_FOM,Adaptation Figure of Merit (FOM)" newline hexmask.word.byte 0x0 8.--15. 1. "RESERVED_15_8,Reserved for Future use" newline hexmask.word.byte 0x0 0.--7. 1. "RX_ADAPT_FOM,Adaptation Figure of Merit (FOM)" group.word 0xC510++0x1 line.word 0x0 "RAWLANE1_DIG_AON_AFE_CTLE_LBK_IDAC_OFST,Offset values for RX CTLE Loopback path iDAC" newline hexmask.word.byte 0x0 8.--15. 1. "RESERVED_15_8,Reserved for Future use" newline hexmask.word.byte 0x0 0.--7. 1. "AFE_CTLE_LBK_IDAC_OFST,Offset value for RX CTLE Loopback path iDAC" group.word 0xC514++0x1 line.word 0x0 "RAWLANE1_DIG_AON_DFE_PHASE_EVEN_VDAC_OFST,Offset values for RX DFE Phase Even vDAC" newline hexmask.word.byte 0x0 8.--15. 1. "RESERVED_15_8,Reserved for Future use" newline hexmask.word.byte 0x0 0.--7. 1. "DFE_PHASE_EVEN_VDAC_OFST,Offset value for DFE Phase Even vDAC" group.word 0xC518++0x1 line.word 0x0 "RAWLANE1_DIG_AON_DFE_PHASE_ODD_VDAC_OFST,Offset values for RX DFE Phase Odd vDAC" newline hexmask.word.byte 0x0 8.--15. 1. "RESERVED_15_8,Reserved for Future use" newline hexmask.word.byte 0x0 0.--7. 1. "DFE_PHASE_ODD_VDAC_OFST,Offset value for DFE Phase Odd vDAC" group.word 0xC51C++0x1 line.word 0x0 "RAWLANE1_DIG_AON_DFE_EVEN_REF_LVL,DFE Even reference level" newline hexmask.word.byte 0x0 8.--15. 1. "RESERVED_15_8,Reserved for Future use" newline hexmask.word.byte 0x0 0.--7. 1. "DFE_EVEN_REF_LVL,DFE Even reference level" group.word 0xC520++0x1 line.word 0x0 "RAWLANE1_DIG_AON_DFE_ODD_REF_LVL,DFE Odd reference level" newline hexmask.word.byte 0x0 8.--15. 1. "RESERVED_15_8,Reserved for Future use" newline hexmask.word.byte 0x0 0.--7. 1. "DFE_ODD_REF_LVL,DFE Odd reference level" group.word 0xC524++0x1 line.word 0x0 "RAWLANE1_DIG_AON_RX_PHSADJ_LIN,RX Phase Adjust Linear Value" newline hexmask.word 0x0 5.--15. 1. "RESERVED_15_5,Reserved for Future use" newline hexmask.word.byte 0x0 0.--4. 1. "RX_PHSADJ_LIN,Linear value for RX phase adjust" rgroup.word 0xC528++0x1 line.word 0x0 "RAWLANE1_DIG_AON_RX_PHSADJ_MAP,RX Phase Adjust Mapped Value" newline hexmask.word 0x0 5.--15. 1. "RESERVED_15_5,Reserved for Future use" newline hexmask.word.byte 0x0 0.--4. 1. "RX_PHSADJ_MAP,Mapped value for RX phase adjust" group.word 0xC52C++0x1 line.word 0x0 "RAWLANE1_DIG_AON_DFE_DATA_EVEN_HIGH_VDAC_OFST,Offset values for RX DFE Data Even High vDAC" newline hexmask.word.byte 0x0 8.--15. 1. "RESERVED_15_8,Reserved for Future use" newline hexmask.word.byte 0x0 0.--7. 1. "DFE_DATA_EVEN_HIGH_VDAC_OFST,Offset value for DFE Data Even High vDAC" group.word 0xC530++0x1 line.word 0x0 "RAWLANE1_DIG_AON_DFE_DATA_EVEN_LOW_VDAC_OFST,Offset values for RX DFE Data Even Low vDAC" newline hexmask.word 0x0 0.--15. 1. "DFE_DATA_EVEN_LOW_VDAC_OFST,Offset value for DFE Data Even Low vDAC" group.word 0xC534++0x1 line.word 0x0 "RAWLANE1_DIG_AON_DFE_DATA_ODD_HIGH_VDAC_OFST,Offset values for RX DFE Data Odd High vDAC" newline hexmask.word.byte 0x0 8.--15. 1. "RESERVED_15_8,Reserved for Future use" newline hexmask.word.byte 0x0 0.--7. 1. "DFE_DATA_ODD_HIGH_VDAC_OFST,Offset value for DFE Data Odd High vDAC" group.word 0xC538++0x1 line.word 0x0 "RAWLANE1_DIG_AON_DFE_DATA_ODD_LOW_VDAC_OFST,Offset values for RX DFE Data Odd Low vDAC" newline hexmask.word 0x0 0.--15. 1. "DFE_DATA_ODD_LOW_VDAC_OFST,Offset value for DFE Data Odd Low vDAC" group.word 0xC53C++0x1 line.word 0x0 "RAWLANE1_DIG_AON_DFE_BYPASS_EVEN_VDAC_OFST,Offset values for RX DFE By-Pass Even vDAC" newline hexmask.word.byte 0x0 8.--15. 1. "RESERVED_15_8,Reserved for Future use" newline hexmask.word.byte 0x0 0.--7. 1. "DFE_BYPASS_EVEN_VDAC_OFST,Offset value for DFE By-Pass Even vDAC" group.word 0xC540++0x1 line.word 0x0 "RAWLANE1_DIG_AON_DFE_BYPASS_ODD_VDAC_OFST,Offset values for RX DFE By-Pass Odd vDAC" newline hexmask.word.byte 0x0 8.--15. 1. "RESERVED_15_8,Reserved for Future use" newline hexmask.word.byte 0x0 0.--7. 1. "DFE_BYPASS_ODD_VDAC_OFST,Offset value for DFE By-Pass Odd vDAC" group.word 0xC544++0x1 line.word 0x0 "RAWLANE1_DIG_AON_DFE_ERROR_EVEN_VDAC_OFST,Offset values for RX DFE Error Even vDAC" newline hexmask.word.byte 0x0 8.--15. 1. "RESERVED_15_8,Reserved for Future use" newline hexmask.word.byte 0x0 0.--7. 1. "DFE_ERROR_EVEN_VDAC_OFST,Offset value for DFE Error Even vDAC" group.word 0xC548++0x1 line.word 0x0 "RAWLANE1_DIG_AON_DFE_ERROR_ODD_VDAC_OFST,Offset values for RX DFE Error Odd vDAC" newline hexmask.word.byte 0x0 8.--15. 1. "RESERVED_15_8,Reserved for Future use" newline hexmask.word.byte 0x0 0.--7. 1. "DFE_ERROR_ODD_VDAC_OFST,Offset value for DFE Error Odd vDAC" group.word 0xC54C++0x1 line.word 0x0 "RAWLANE1_DIG_AON_RX_IQ_PHASE_ADJUST,Value for RX IQ PHASE Adjust" newline hexmask.word 0x0 7.--15. 1. "RESERVED_15_7,Reserved for Future use" newline hexmask.word.byte 0x0 0.--6. 1. "RX_IQ_PHASE_ADJUST,Value for RX IQ PHASE Adjust" group.word 0xC550++0x1 line.word 0x0 "RAWLANE1_DIG_AON_MPLLA_COARSE_TUNE,MPLLA_COARSE_TUNE" newline hexmask.word.byte 0x0 8.--15. 1. "RESERVED_15_8,Reserved for Future use" newline hexmask.word.byte 0x0 0.--7. 1. "MPLLA_COARSE_TUNE,Stored coarse tune value for MPLLA" group.word 0xC554++0x1 line.word 0x0 "RAWLANE1_DIG_AON_MPLLB_COARSE_TUNE,MPLLB_COARSE_TUNE" newline hexmask.word.byte 0x0 8.--15. 1. "RESERVED_15_8,Reserved for Future use" newline hexmask.word.byte 0x0 0.--7. 1. "MPLLB_COARSE_TUNE,Stored coarse tune value for MPLLB" group.word 0xC558++0x1 line.word 0x0 "RAWLANE1_DIG_AON_INIT_PWRUP_DONE,Initial Power-Up Done Status" newline hexmask.word 0x0 1.--15. 1. "RESERVED_15_1,Reserved for Future use" newline bitfld.word 0x0 0. "INIT_PWRUP_DONE,Indicates whether initial power-up has completed or not." "0,1" group.word 0xC55C++0x1 line.word 0x0 "RAWLANE1_DIG_AON_RX_ADPT_ATT,RX Adapted value of ATT" newline hexmask.word.byte 0x0 8.--15. 1. "RESERVED_15_8,Reserved for Future use" newline hexmask.word.byte 0x0 0.--7. 1. "ATT_ADPT_VAL,Stored RX adapted ATT value" group.word 0xC560++0x1 line.word 0x0 "RAWLANE1_DIG_AON_RX_ADPT_VGA,RX Adapted value of VGA" newline hexmask.word.byte 0x0 10.--15. 1. "RESERVED_15_10,Reserved for Future use" newline hexmask.word 0x0 0.--9. 1. "VGA_ADPT_VAL,Stored RX adapted VGA value" group.word 0xC564++0x1 line.word 0x0 "RAWLANE1_DIG_AON_RX_ADPT_CTLE,RX Adapted value of CTLE" newline rbitfld.word 0x0 13.--15. "RESERVED_15_13,Reserved for Future use" "0,1,2,3,4,5,6,7" newline bitfld.word 0x0 10.--12. "CTLE_POLE_ADPT_VAL,Stored RX adapted CTLE pole value" "0,1,2,3,4,5,6,7" newline hexmask.word 0x0 0.--9. 1. "CTLE_BOOST_ADPT_VAL,Stored RX adapted CTLE boost value" group.word 0xC568++0x1 line.word 0x0 "RAWLANE1_DIG_AON_RX_ADPT_DFE_TAP1,RX Adapted value of DFE TAP1" newline rbitfld.word 0x0 13.--15. "RESERVED_15_13,Reserved for Future use" "0,1,2,3,4,5,6,7" newline hexmask.word 0x0 0.--12. 1. "DFE_TAP1_ADPT_VAL,Stored RX adapted DFE TAP1 value" group.word 0xC56C++0x1 line.word 0x0 "RAWLANE1_DIG_AON_RX_ADAPT_DONE,RX Adaptation Done Status" newline hexmask.word 0x0 1.--15. 1. "RESERVED_15_1,Reserved for Future use" newline bitfld.word 0x0 0. "RX_ADAPT_DONE,Indicates whether RX adaptation has completed or not." "0,1" group.word 0xC570++0x1 line.word 0x0 "RAWLANE1_DIG_AON_FAST_FLAGS,Fast flags for simulation only" newline rbitfld.word 0x0 15. "RESERVED_15_15,Reserved for Future use" "0,1" newline bitfld.word 0x0 14. "FAST_RX_VCO_CAL,Enable fast RX VCO Calibration" "0,1" newline bitfld.word 0x0 13. "FAST_RX_VCO_WAIT,Enable fast RX VCO wait times" "0,1" newline bitfld.word 0x0 12. "FAST_RX_PWRUP,Enable fast RX power-up (LOS VREG/AFE and DCC)" "0,1" newline bitfld.word 0x0 11. "FAST_TX_RXDET,Enable fast TX Detect RX" "0,1" newline bitfld.word 0x0 10. "FAST_TX_CMN_MODE,Enable fast TX Common Mode Charge-up" "0,1" newline bitfld.word 0x0 9. "FAST_SUP,Enable fast Support block (MPLL and Rtune)" "0,1" newline bitfld.word 0x0 8. "FAST_RX_DFE_ADAPT,Enables fast RX DFE DAC start-up adaptation" "0,1" newline bitfld.word 0x0 7. "FAST_RX_AFE_ADAPT,Enables fast RX AFE DAC start-up adaptation" "0,1" newline bitfld.word 0x0 6. "FAST_RX_IQ_CAL,Enables fast RX IQ start-up calibration" "0,1" newline bitfld.word 0x0 5. "FAST_RX_REFLVL_CAL,Enables fast RX reference level (100mv 125mv 150mv) start-up calibration" "0,1" newline bitfld.word 0x0 4. "FAST_RX_DFE_RE_ADAPT,Enables fast RX DFE re -adaptation" "0,1" newline bitfld.word 0x0 3. "FAST_RX_DFE_CAL,Enables fast RX DFE slicer start-up calibration" "0,1" newline bitfld.word 0x0 2. "FAST_RX_AFE_CAL,Enables fast RX AFE DAC start-up calibration" "0,1" newline bitfld.word 0x0 1. "FAST_RX_ADAPT,Enables fast RX adaptation" "0,1" newline bitfld.word 0x0 0. "FAST_RX_STARTUP_CAL,Enables fast RX start-up calibration" "0,1" group.word 0xC574++0x1 line.word 0x0 "RAWLANE1_DIG_AON_RX_ADPT_DFE_TAP2,RX Adapted value of DFE TAP2" newline hexmask.word.byte 0x0 12.--15. 1. "RESERVED_15_12,Reserved for Future use" newline hexmask.word 0x0 0.--11. 1. "DFE_TAP2_ADPT_VAL,Stored RX adapted DFE TAP2 value" group.word 0xC578++0x1 line.word 0x0 "RAWLANE1_DIG_AON_RX_PHSADJ_LIN_RIGHT,RX last stable iq phase of Right of the eye" newline hexmask.word.byte 0x0 8.--15. 1. "RESERVED,Reserved bits" newline hexmask.word.byte 0x0 0.--7. 1. "RX_PHSADJ_LIN_RIGHT,Stored RX iq phase right edge" group.word 0xC57C++0x1 line.word 0x0 "RAWLANE1_DIG_AON_RX_PHSADJ_LIN_LEFT,RX last stable iq phase of Left of the eye" newline hexmask.word.byte 0x0 8.--15. 1. "RESERVED,Reserved bits" newline hexmask.word.byte 0x0 0.--7. 1. "RX_PHSADJ_LIN_LEFT,Stored RX iq phase left edge" group.word 0xC580++0x1 line.word 0x0 "RAWLANE1_DIG_AON_RX_PHSADJ_LIN_ADAPT,RX Adapted value of PHASE IQ" newline hexmask.word.byte 0x0 8.--15. 1. "RESERVED,Reserved bits" newline hexmask.word.byte 0x0 0.--7. 1. "RX_PHSADJ_LIN_ADAPT,Stored RX adapted IQ value" group.word 0xC584++0x1 line.word 0x0 "RAWLANE1_DIG_AON_RX_SLICER_CTRL_EVEN,Sets values for RX SLICER CTRL EVEN signals going to ANA" newline hexmask.word 0x0 4.--15. 1. "RESERVED_15_4,Reserved for Future use" newline hexmask.word.byte 0x0 0.--3. 1. "RX_ANA_SLICER_CTRL_E,Value for rx_ana_slicer_ctrl_e[3:0]" group.word 0xC588++0x1 line.word 0x0 "RAWLANE1_DIG_AON_RX_SLICER_CTRL_ODD,Sets values for RX SLICER CTRL ODD signals going to ANA" newline hexmask.word 0x0 4.--15. 1. "RESERVED_15_4,Reserved for Future use" newline hexmask.word.byte 0x0 0.--3. 1. "RX_ANA_SLICER_CTRL_O,Value for rx_ana_slicer_ctrl_o[3:0]" group.word 0xC58C++0x1 line.word 0x0 "RAWLANE1_DIG_AON_LANE_CMNCAL_MPLL_STATUS,MPLL Common Calibration Status" newline hexmask.word 0x0 2.--15. 1. "RESERVED_15_2,Reserved for Future use" newline bitfld.word 0x0 1. "LANE_CMNCAL_MPLL_DONE,Indicates whether MPLL common calibration has been completed by this lane or not." "0,1" newline bitfld.word 0x0 0. "LANE_CMNCAL_MPLL_INIT,Indicates whether MPLL common calibration has been started by this lane or not." "0,1" repeat 8. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 )(list 0x0 0x4 0x8 0xC 0x10 0x14 0x18 0x1C ) group.word ($2+0xC590)++0x1 line.word 0x0 "RAWLANE1_DIG_AON_ADPT_CTL_$1,Adaptation Control register #0" newline hexmask.word 0x0 0.--15. 1. "VAL,Value of adaptation control" repeat.end group.word 0xC5B0++0x1 line.word 0x0 "RAWLANE1_DIG_AON_MPLL_DISABLE,LANE_MPLLA/B_DISABLE override" newline hexmask.word 0x0 2.--15. 1. "RESERVED_15_2,Reserved for Future use" newline bitfld.word 0x0 1. "LANE_MPLLB_DISABLE,Disable MPLLB" "0,1" newline bitfld.word 0x0 0. "LANE_MPLLA_DISABLE,Disable MPLLA" "0,1" group.word 0xC5B4++0x1 line.word 0x0 "RAWLANE1_DIG_AON_FAST_FLAGS_2,Fast flags for simulation only" newline hexmask.word.byte 0x0 12.--15. 1. "RSVD_FAST_FLAGS,Reserved fast flags" newline bitfld.word 0x0 11. "SKIP_IQ_STEP_SKIP,Skip the IQ step skip option" "0,1" newline bitfld.word 0x0 10. "SKIP_250US_WAIT,Skip bit for USB Gen1 250us wait FW WA" "0,1" newline bitfld.word 0x0 9. "WA_ATT_VCM_ISSUE_MODE,Workaround en or disable STAR 9001169835" "0,1" newline bitfld.word 0x0 8. "FAST_RX_CTLE_ADAPT,Enables fast RX CTLE adaptation" "0,1" newline bitfld.word 0x0 7. "FAST_RX_ATT_ADAPT,Enables fast RX ATT adaptation" "0,1" newline bitfld.word 0x0 6. "RX_IQ_DELTA_ADD,Enables RX IQ DELTA addition" "0,1" newline bitfld.word 0x0 5. "FAST_RX_IQ_ADAPT,Enables fast RX IQ ADAPT" "0,1" newline bitfld.word 0x0 4. "FAST_RX_CONT_AFE_CAL,Enables fast RX continuous AFE calibration" "0,1" newline bitfld.word 0x0 3. "FAST_RX_CONT_PHASE_CAL,Enables fast RX continuous phase calibration" "0,1" newline bitfld.word 0x0 2. "FAST_RX_CONT_DATA_CAL,Enables fast RX continuous data calibration" "0,1" newline bitfld.word 0x0 1. "FAST_RX_CONT_ADAPT,Enables fast RX continuous adaptation" "0,1" newline bitfld.word 0x0 0. "FAST_RX_CONT_CAL_ADAPT,Enables fast RX continuous calibration/adaptation" "0,1" group.word 0xC5B8++0x1 line.word 0x0 "RAWLANE1_DIG_AON_LANE_CMNCAL_RCAL_STATUS,RTUNE Common Calibration Status" newline hexmask.word 0x0 2.--15. 1. "RESERVED_15_2,Reserved for Future use" newline bitfld.word 0x0 1. "LANE_CMNCAL_RCAL_DONE,Indicates whether RTUNE common calibration has been completed by this lane or not." "0,1" newline bitfld.word 0x0 0. "LANE_CMNCAL_RCAL_INIT,Indicates whether RTUNE common calibration has been started by this lane or not." "0,1" group.word 0xC5BC++0x1 line.word 0x0 "RAWLANE1_DIG_AON_TXRX_OVRD_IN,Override values for incoming AON TX/RX controls from PCS" newline hexmask.word 0x0 4.--15. 1. "RESERVED_15_4,Reserved for Future use" newline bitfld.word 0x0 3. "TX_DISABLE_OVRD_EN,Override enable for tx_disable" "0,1" newline bitfld.word 0x0 2. "TX_DISABLE_OVRD_VAL,Override value for tx_disable" "0,1" newline bitfld.word 0x0 1. "RX_DISABLE_OVRD_EN,Override enable for rx_disable" "0,1" newline bitfld.word 0x0 0. "RX_DISABLE_OVRD_VAL,Override value for rx_disable" "0,1" group.word 0xC5C0++0x1 line.word 0x0 "RAWLANE1_DIG_AON_AFE_ATT_2_IDAC_OFST,Offset value for RX AFE ATT_2 iDAC" newline hexmask.word.byte 0x0 8.--15. 1. "RESERVED_15_8,Reserved for Future use" newline hexmask.word.byte 0x0 0.--7. 1. "AFE_ATT_2_IDAC_OFST,Offset value for AFE ATT_2 iDAC when cc is 1 in ana typec projects" group.word 0xC5C4++0x1 line.word 0x0 "RAWLANE1_DIG_AON_RXTX_CC_OVRD_IN,Override incoming values for rxtx_cc" newline hexmask.word 0x0 2.--15. 1. "RESERVED_15_2,Reserved for Future use" newline bitfld.word 0x0 1. "RXTX_CC_OVRD_EN,Enable override value for rxtx_cc" "0,1" newline bitfld.word 0x0 0. "RXTX_CC_OVRD_VAL,Override value for rxtx_cc" "0,1" rgroup.word 0xC5C8++0x1 line.word 0x0 "RAWLANE1_DIG_AON_RXTX_CC_STATUS_IN,Incoming value of CC status from TCA" newline hexmask.word 0x0 1.--15. 1. "RESERVED_15_1,Reserved for Future use" newline bitfld.word 0x0 0. "RXTX_CC_IN_I,Value from TCA of cc" "0,1" rgroup.word 0xC5CC++0x1 line.word 0x0 "RAWLANE1_DIG_AON_RXTX_CC_STATUS_OUT,Current values for outgoing CC status to PMA" newline hexmask.word 0x0 1.--15. 1. "RESERVED_15_1,Reserved for Future use" newline bitfld.word 0x0 0. "RXTX_CC_OUT,Value to PMA of cc" "0,1" group.word 0xC600++0x1 line.word 0x0 "RAWLANE1_DIG_IRQ_CTL_RESET_RTN_REQ,Reset routine request" newline hexmask.word 0x0 1.--15. 1. "RESERVED_15_1,Reserved for Future use" newline bitfld.word 0x0 0. "RESET_RTN_REQ,Reset routine request" "0,1" rgroup.word 0xC604++0x1 line.word 0x0 "RAWLANE1_DIG_IRQ_CTL_RX_RESET_IRQ,Rx reset interrupt" newline hexmask.word 0x0 1.--15. 1. "RESERVED_15_1,Reserved for Future use" newline bitfld.word 0x0 0. "RX_RESET,Rx reset interrupt" "0,1" rgroup.word 0xC608++0x1 line.word 0x0 "RAWLANE1_DIG_IRQ_CTL_RX_REQ_IRQ,Rx request interrupt" newline hexmask.word 0x0 1.--15. 1. "RESERVED_15_1,Reserved for Future use" newline bitfld.word 0x0 0. "RX_REQ,Rx request interrupt" "0,1" rgroup.word 0xC60C++0x1 line.word 0x0 "RAWLANE1_DIG_IRQ_CTL_RX_RATE_IRQ,Rx rate change interrupt request" newline hexmask.word 0x0 1.--15. 1. "RESERVED_15_1,Reserved for Future use" newline bitfld.word 0x0 0. "RX_RATE_IRQ,Rx rate change interrupt request" "0,1" rgroup.word 0xC610++0x1 line.word 0x0 "RAWLANE1_DIG_IRQ_CTL_RX_PSTATE_IRQ,Rx pstate change interrupt request" newline hexmask.word 0x0 1.--15. 1. "RESERVED_15_1,Reserved for Future use" newline bitfld.word 0x0 0. "RX_PSTATE_IRQ,Rx pstate change interrupt request" "0,1" rgroup.word 0xC614++0x1 line.word 0x0 "RAWLANE1_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ,Rx adaptation request interrupt" newline hexmask.word 0x0 1.--15. 1. "RESERVED_15_1,Reserved for Future use" newline bitfld.word 0x0 0. "RX_ADAPT_REQ_IRQ,Rx adaptation request interrupt" "0,1" rgroup.word 0xC618++0x1 line.word 0x0 "RAWLANE1_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ,Rx adaptation disable interrupt" newline hexmask.word 0x0 1.--15. 1. "RESERVED_15_1,Reserved for Future use" newline bitfld.word 0x0 0. "RX_ADAPT_DIS_IRQ,Rx adaptation disable interrupt" "0,1" group.word 0xC61C++0x1 line.word 0x0 "RAWLANE1_DIG_IRQ_CTL_RX_RESET_IRQ_CLR,RX reset interrupt clear" newline hexmask.word 0x0 1.--15. 1. "RESERVED_15_1,Reserved for Future use" newline bitfld.word 0x0 0. "RX_RESET_IRQ_CLR,RX reset interrupt clear (self-clearing)" "0,1" group.word 0xC620++0x1 line.word 0x0 "RAWLANE1_DIG_IRQ_CTL_RX_REQ_IRQ_CLR,RX request interrupt clear" newline hexmask.word 0x0 1.--15. 1. "RESERVED_15_1,Reserved for Future use" newline bitfld.word 0x0 0. "RX_REQ_IRQ_CLR,RX request interrupt clear (self-clearing)" "0,1" group.word 0xC624++0x1 line.word 0x0 "RAWLANE1_DIG_IRQ_CTL_RX_RATE_IRQ_CLR,RX rate change interrupt clear" newline hexmask.word 0x0 1.--15. 1. "RESERVED_15_1,Reserved for Future use" newline bitfld.word 0x0 0. "RX_RATE_IRQ_CLR,RX rate change interrupt clear (self-clearing)" "0,1" group.word 0xC628++0x1 line.word 0x0 "RAWLANE1_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR,RX pstate change interrupt clear" newline hexmask.word 0x0 1.--15. 1. "RESERVED_15_1,Reserved for Future use" newline bitfld.word 0x0 0. "RX_PSTATE_IRQ_CLR,RX pstate change interrupt clear (self-clearing)" "0,1" group.word 0xC62C++0x1 line.word 0x0 "RAWLANE1_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR,RX adaptation request interrupt clear" newline hexmask.word 0x0 1.--15. 1. "RESERVED_15_1,Reserved for Future use" newline bitfld.word 0x0 0. "RX_ADAPT_REQ_IRQ_CLR,RX adaptation request interrupt clear (self-clearing)" "0,1" group.word 0xC630++0x1 line.word 0x0 "RAWLANE1_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR,RX adaptation disable interrupt clear" newline hexmask.word 0x0 1.--15. 1. "RESERVED_15_1,Reserved for Future use" newline bitfld.word 0x0 0. "RX_ADAPT_DIS_IRQ_CLR,RX adaptation disable interrupt clear (self-clearing)" "0,1" group.word 0xC634++0x1 line.word 0x0 "RAWLANE1_DIG_IRQ_CTL_IRQ_MASK,Interrupt Mask" newline hexmask.word 0x0 7.--15. 1. "RESERVED_15_7,Reserved for Future use" newline bitfld.word 0x0 6. "LANE_XCVR_MODE_IRQ_MSK,Mask for lane_xcvr_mode interrupt (0 = cannot interrupt)" "cannot interrupt),?" newline bitfld.word 0x0 5. "RX_RESET_IRQ_MSK,Mask for Rx reset interrupt (0 = cannot interrupt)" "cannot interrupt),?" newline bitfld.word 0x0 4. "RX_ADAPT_DIS_IRQ_MSK,Mask for Rx adaptation disable interrupt (0 = cannot interrupt)" "cannot interrupt),?" newline bitfld.word 0x0 3. "RX_ADAPT_REQ_IRQ_MSK,Mask for Rx adaptation request interrupt (0 = cannot interrupt)" "cannot interrupt),?" newline bitfld.word 0x0 2. "RX_PSTATE_IRQ_MSK,Mask for Rx pstate change interrupt (0 = cannot interrupt)" "cannot interrupt),?" newline bitfld.word 0x0 1. "RX_RATE_IRQ_MSK,Mask for Rx rate change interrupt (0 = cannot interrupt)" "cannot interrupt),?" newline bitfld.word 0x0 0. "RX_REQ_IRQ_MSK,Mask for Rx request interrupt (0 = cannot interrupt)" "cannot interrupt),?" rgroup.word 0xC638++0x1 line.word 0x0 "RAWLANE1_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ,Lane transceiver mode interrupt" newline hexmask.word 0x0 1.--15. 1. "RESERVED_15_1,Reserved for Future use" newline bitfld.word 0x0 0. "LANE_XCVR_MODE_IRQ,Lane transceiver mode interrupt" "0,1" group.word 0xC63C++0x1 line.word 0x0 "RAWLANE1_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR,Lane transceiver mode interrupt clear" newline hexmask.word 0x0 1.--15. 1. "RESERVED_15_1,Reserved for Future use" newline bitfld.word 0x0 0. "LANE_XCVR_MODE_IRQ_CLR,Lane transceiver mode interrupt clear (self-clearing)" "0,1" group.word 0xC680++0x1 line.word 0x0 "RAWLANE1_DIG_PMA_XF_LANE_OVRD_IN,Override values for incoming LANE controls" newline hexmask.word 0x0 3.--15. 1. "RESERVED_15_3,Reserved for Future use" newline bitfld.word 0x0 2. "LANE_OVRD_EN,Override enable for signals in this register" "0,1" newline bitfld.word 0x0 1. "LANE_MPLLB_EN_IN,Override value for lane_mpllb_en_in" "0,1" newline bitfld.word 0x0 0. "LANE_MPLLA_EN_IN,Override value for lane_mplla_en_in" "0,1" group.word 0xC684++0x1 line.word 0x0 "RAWLANE1_DIG_PMA_XF_LANE_OVRD_OUT,Override values for outgoing LANE controls" newline hexmask.word 0x0 3.--15. 1. "RESERVED_15_3,Reserved for Future use" newline bitfld.word 0x0 2. "LANE_OVRD_EN,Override enable for signals in this register" "0,1" newline bitfld.word 0x0 1. "LANE_MPLLB_EN_OUT,Override value for lane_mpllb_en_out" "0,1" newline bitfld.word 0x0 0. "LANE_MPLLA_EN_OUT,Override value for lane_mplla_en_out" "0,1" group.word 0xC688++0x1 line.word 0x0 "RAWLANE1_DIG_PMA_XF_SUP_OVRD_IN,Override values for incoming SUP controls from PMA" newline hexmask.word 0x0 3.--15. 1. "RESERVED_15_3,Reserved for Future use" newline bitfld.word 0x0 2. "SUP_STATE_OVRD_EN,Override enable for signals in this register" "0,1" newline bitfld.word 0x0 1. "MPLLB_STATE,Override value for mpllb_state" "0,1" newline bitfld.word 0x0 0. "MPLLA_STATE,Override value for mplla_state" "0,1" rgroup.word 0xC68C++0x1 line.word 0x0 "RAWLANE1_DIG_PMA_XF_SUP_PMA_IN,Current values for incoming MPLL status controls from PMA" newline hexmask.word 0x0 2.--15. 1. "RESERVED_15_2,Reserved for Future use" newline bitfld.word 0x0 1. "MPLLB_STATE,Value from PMA for mpllb_state" "0,1" newline bitfld.word 0x0 0. "MPLLA_STATE,Value from PMA for mplla_state" "0,1" group.word 0xC690++0x1 line.word 0x0 "RAWLANE1_DIG_PMA_XF_TX_OVRD_OUT,Override values for outgoing TX controls to PMA" newline hexmask.word 0x0 4.--15. 1. "RESERVED_15_4,Reserved for Future use" newline bitfld.word 0x0 3. "TX_RESET_OVRD_EN,Override enable for tx_reset" "0,1" newline bitfld.word 0x0 2. "TX_RESET_OVRD_VAL,Override value for tx_reset" "0,1" newline bitfld.word 0x0 1. "TX_REQ_OVRD_EN,Override enable for tx_req" "0,1" newline bitfld.word 0x0 0. "TX_REQ_OVRD_VAL,Override value for tx_req" "0,1" rgroup.word 0xC694++0x1 line.word 0x0 "RAWLANE1_DIG_PMA_XF_TX_PMA_IN,Current values for coming TX status controls from PMA" newline hexmask.word 0x0 1.--15. 1. "RESERVED_15_1,Reserved for Future use" newline bitfld.word 0x0 0. "ACK,Value from PMA for tx_ack" "0,1" group.word 0xC698++0x1 line.word 0x0 "RAWLANE1_DIG_PMA_XF_RX_OVRD_OUT,Override values for outgoing RX controls to PMA" newline hexmask.word 0x0 4.--15. 1. "RESERVED_15_4,Reserved for Future use" newline bitfld.word 0x0 3. "RX_RESET_OVRD_EN,Override enable for rx_reset" "0,1" newline bitfld.word 0x0 2. "RX_RESET_OVRD_VAL,Override value for rx_reset" "0,1" newline bitfld.word 0x0 1. "RX_REQ_OVRD_EN,Override enable for rx_req" "0,1" newline bitfld.word 0x0 0. "RX_REQ_OVRD_VAL,Override value for rx_req" "0,1" rgroup.word 0xC69C++0x1 line.word 0x0 "RAWLANE1_DIG_PMA_XF_RX_PMA_IN,Current values for coming RX status controls from PMA" newline hexmask.word 0x0 1.--15. 1. "RESERVED_15_1,Reserved for Future use" newline bitfld.word 0x0 0. "ACK,Value from PMA for rx_ack" "0,1" group.word 0xC6A0++0x1 line.word 0x0 "RAWLANE1_DIG_PMA_XF_LANE_RTUNE_CTL,Lane Rtune Controls" newline hexmask.word 0x0 1.--15. 1. "RESERVED_15_1,Reserved for Future use" newline bitfld.word 0x0 0. "LANE_RTUNE_REQ,Lane value for rtune_req" "0,1" rgroup.word 0xC6A4++0x1 line.word 0x0 "RAWLANE1_DIG_PMA_XF_SUP_PMA_IN_1,Current values for incoming RTUNE status controls from PMA" newline hexmask.word 0x0 1.--15. 1. "RESERVED_15_1,Reserved for Future use" newline bitfld.word 0x0 0. "RTUNE_ACK,Value from PMA for rtune_ack" "0,1" rgroup.word 0xC6A8++0x1 line.word 0x0 "RAWLANE1_DIG_PMA_XF_SUP_PMA_RX_VALID,Current value of RX valid from PMA" newline hexmask.word 0x0 1.--15. 1. "RESERVED_15_1,Reserved for Future use" newline bitfld.word 0x0 0. "RX_VALID,Value of RX_VALID" "0,1" group.word 0xC700++0x1 line.word 0x0 "RAWLANE1_DIG_TX_CTL_TX_FSM_CTL,TX FSM Control" newline hexmask.word.byte 0x0 10.--15. 1. "RESERVED_15_10,Reserved for Future use" newline bitfld.word 0x0 9. "TX_P0_ALLOW_RXDET,If asserted then rxdet request is allowed in P0" "0,1" newline bitfld.word 0x0 8. "TX_P0S_ALLOW_RXDET,If asserted then rxdet request is allowed in P0S" "0,1" newline bitfld.word 0x0 7. "TX_P1_ALLOW_RXDET,If asserted then rxdet request is allowed in P1" "0,1" newline bitfld.word 0x0 6. "TX_P2_ALLOW_RXDET,If asserted then rxdet request is allowed in P2" "0,1" newline hexmask.word.byte 0x0 0.--5. 1. "TX_WAIT_MPLL_OFF_TIME,Number of ref_range cycles to wait for MPLL to turn off (When entering P2)." group.word 0xC704++0x1 line.word 0x0 "RAWLANE1_DIG_TX_CTL_TX_CLK_CTL,Select clock to act as TX input clock" newline hexmask.word 0x0 5.--15. 1. "RESERVED_15_5,Reserved for Future use" newline hexmask.word.byte 0x0 1.--4. 1. "TX_CLK_SEL,Select clock source for tx_pma_clk 0 - tx_pcs_clk (input clock from pcs) 1 - mplla_word_clk 2 - mplla_dword_clk 3 - mplla_qword_clk 4 - mplla_oword_clk 5 - mplla_div_clk 6 - mpllb_word_clk 7 - mpllb_dword_clk 8 - mpllb_qword_clk 9 -.." newline bitfld.word 0x0 0. "TX_CLK_EN,Enable the tx_clk to pma tx lane TX_CLK_EN must be deasserted when switching TX_CLK_SEL" "0,1" group.word 0xC780++0x1 line.word 0x0 "RAWLANE1_DIG_RX_CTL_RX_FSM_CTL,RX FSM control register" newline hexmask.word 0x0 2.--15. 1. "RESERVED_15_2,Reserved for Future use" newline bitfld.word 0x0 1. "RATE_CHG_IN_P1,When asserted then a rate change in P0/P0s will be sequenced such that the RX is put in P1 the rate change is applied and then the RX is returned to P0/P0s." "0,1" newline bitfld.word 0x0 0. "EN_RX_CTL_FSM,Enable the RX control FSM in the Raw PCS If enabled then when FSM detects a rate change it moves the RX to P1 does the rate change then goes back to P0/P0s. If not enabled then FSM is by-passed." "0,1" group.word 0xC784++0x1 line.word 0x0 "RAWLANE1_DIG_RX_CTL_RX_LOS_MASK_CTL,RX LOS Mask Control" newline hexmask.word.byte 0x0 9.--15. 1. "RESERVED_15_9,Reserved for Future use" newline hexmask.word 0x0 0.--8. 1. "RX_LOS_MASK_CNT,Number of cycles (ref_range_clk) to mask out the rx_los output from the time the los is powered-on. Default set for minimum 10us." group.word 0xC788++0x1 line.word 0x0 "RAWLANE1_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL,RX Data Enable Override Control" newline hexmask.word 0x0 5.--15. 1. "INT_REF_TRCK_CNT,Number of ref_range cycles to wait for integral reference tracking to settle." newline hexmask.word.byte 0x0 0.--4. 1. "RX_DATA_EN_OVRD_CNT,Number of ref_range cycles to override rx_data_en to 1." rgroup.word 0xC78C++0x1 line.word 0x0 "RAWLANE1_DIG_RX_CTL_OFFCAN_CONT_STATUS,RX continuous offset cancellation status" newline hexmask.word 0x0 1.--15. 1. "RESERVED_15_1,Reserved for Future use" newline bitfld.word 0x0 0. "ENABLE,Enable status for rx continous offset cancellation" "0,1" rgroup.word 0xC790++0x1 line.word 0x0 "RAWLANE1_DIG_RX_CTL_ADAPT_CONT_STATUS,RX continuous adaptation status" newline hexmask.word 0x0 1.--15. 1. "RESERVED_15_1,Reserved for Future use" newline bitfld.word 0x0 0. "ENABLE,Enable status for rx continous adaptation" "0,1" tree.end tree "PCIE_PHY_NCR" base ad:0xF1210000 group.long 0x0++0x3B line.long 0x0 "CTRL_0,CTRL_0" newline bitfld.long 0x0 24. "CR_CKEN,CR_CKEN This bit enable CR clock. 0x0 : CR clock disabled 0x1 : CR clock enabled Software need to enable this bit before any CR register access thourgh CR port." "CR clock disabled,CR clock enabled" newline bitfld.long 0x0 22.--23. "CR_PARA_SEL,Control Register (CR) parallel interface select Function: Controls selection between JTAG and CR interfaces: 0 : JTAG 1: Control Register (CR) This input can only be changed when the cr_para_clk and jtag_tck clock inputs are disabled." "JTAG,Control Register,?,?" newline bitfld.long 0x0 21. "PHY_SRAM_EXT_LD_DONE,SRAM external load done.Function: Signal asserted by user after any updates to the SRAM have been loaded." "0,1" newline bitfld.long 0x0 20. "PHY_SRAM_BYPASS,SRAM bypass Function: Control signal when asserted bypasses the SRAM interface. In this case the adaptation and calibration algorithms are executed from the hard wired values within the Raw PCS. If SRAM is not bypassed the internal.." "0,1" newline bitfld.long 0x0 19. "PG_MODE_EN,Power gating support enable. Function: Control input to enable the power gating support.When de-asserted. the control inputs related to power gating are ignored." "0,1" newline hexmask.long.word 0x0 3.--18. 1. "UPCS_PIPE_CONFIG,PCS PIPE configuration.When upcs_pipe_config[0] is set to 1 the PCS ignores lane-off via PIPE specification method (TxElecIdle = 1 and TxCompliance = 1) and responds to power-down/rate/width changes. Otherwise until the MAC deasserts.." newline bitfld.long 0x0 2. "PCS_EXT_PCLK_REQ,External PCLK request.When asserted the MPLL clock sources in the PHY are powered up and pcs_laneX_pclk outputs stay active regardless of the pcs_laneX_powerdown[3:0] inputs." "0,1" newline bitfld.long 0x0 1. "BIF_EN,BIF_EN 0x0 : Bifurcation disabled (Both Lane #0 and Lane #1 used for PCIEX2 core) 0x1 : Bifurcation enabled (Lane #0 used for PCIEX2 core and Lane #1 used for PCIEX1 core)" "Bifurcation disabled,Bifurcation enabled" newline bitfld.long 0x0 0. "PHY_RESET,PHY reset.Function: Asynchronously resets the core and all state machines.Asserting phy_reset resets all sequential elements in the design including control registers. As a result any register programming needs to be redone after phy_reset is.." "0,1" line.long 0x4 "CTRL_1,CTRL_1" newline bitfld.long 0x4 27. "PIPE_TX0_ONES_ZEROS,USB TX compliance pattern enable for lane 0" "0,1" newline bitfld.long 0x4 26. "PIPE_RX0_TERMINATION,RX termination enable for lane 0.When asserted the RX terminations are enabled." "0,1" newline bitfld.long 0x4 25. "PIPE_RX0_EQ_TRAINING,RX equalization training mode enable for lane 0" "0,1" newline bitfld.long 0x4 24. "PIPE_LANE0_CLKREQ_N,Clock request for lane 0" "0,1" newline bitfld.long 0x4 23. "PIPE_LANE0_TX2RX_LOOPBK,TX-to-RX loopback enable for lane 0.When asserted this input turns on the TX-to-RX serial loopback within the PHY.This signal is for debug purposes only." "0,1" newline hexmask.long.byte 0x4 19.--22. 1. "PIPE_LANE0_LINK_NUM,Reserved for future." newline bitfld.long 0x4 18. "PHY_TEST_TX_REF_CLK_EN,TX ref clock output enable.Function: Enables the reference clock inputs (ref_pad_clk_\{p m\} or ref_alt_clk_\{p m\}) to be directly output on txN_\{p m\}. For additional information see 'PHY Test Mode Selection' ." "0,1" newline bitfld.long 0x4 17. "PHY_TEST_STOP_CLK_EN,Stop-clock test mode enable.Function: Reserved" "0,1" newline bitfld.long 0x4 16. "PHY_MPLLB_SSC_EN,Spread spectrum enable.Function: Enables spread-spectrum clock (SSC) generation on the mpllb_div_clk output. If the reference clock already has spread spectrum applied mpllb_ssc_en must be de-asserted.These inputs can only be changed.." "0,1" newline bitfld.long 0x4 15. "PHY_MPLLB_FORCE_EN,MPLLB force enable.Function: When asserted the corresponding MPLL is forced to bepowered up irrespective of the txX_mpll_en input.This input is used for applications whehe a free-running MPLL clock output is required. There are no.." "0,1" newline bitfld.long 0x4 14. "PHY_MPLLA_SSC_EN,Spread spectrum enable.Function:Enables spread-spectrum clock (SSC) generation on the mplla_div_clk output. If the reference clock already has spread spectrum applied mplla_ssc_en must be de-asserted.These inputs can only be changed.." "0,1" newline bitfld.long 0x4 13. "PHY_MPLLA_FORCE_EN,MPLLA force enable.Function: When asserted the corresponding MPLL is forced to be powered up irrespective of the txX_mpll_en input.This input is used for applications where a free-running MPLL clock output is required. There are no.." "0,1" newline bitfld.long 0x4 12. "PHY_RX1_TERM_ACDC,Receiver termination control.Function: Reserved; tie off to 1'b1" "0,1" newline bitfld.long 0x4 11. "PHY_LANE1_RX2TX_PAR_LB_EN,Parallel (RX to TX) loopback enable.Function: When this signal is asserted recovered parallel data from the receiver is looped back to the transmit serializer." "0,1" newline bitfld.long 0x4 10. "PHY_RX0_TERM_ACDC,Receiver termination control.Function: Reserved; tie off to 1'b1" "0,1" newline bitfld.long 0x4 9. "PHY_LANE0_RX2TX_PAR_LB_EN,Parallel (RX to TX) loopback enable.Function: When this signal is asserted recovered parallel data from the receiver is looped back to the transmit serializer." "0,1" newline bitfld.long 0x4 8. "PHY_REF_ALT_CLK_SEL,PHY_REF_ALT_CLK_SEL 0x0 : PHY ref_alt_clk_p input from internal SoC PLL (100MHz). 0x1 : PHY ref_alt_clk_p input from Differential Buffer (100MHz)" "PHY ref_alt_clk_p input from internal SoC PLL,PHY ref_alt_clk_p input from Differential Buffer" newline bitfld.long 0x4 7. "PHY_LANE_POWER_PRESENT,VBUS power present.Signal from external VBUS detection circuit." "0,1" newline bitfld.long 0x4 6. "PHY_REF_REPEAT_CLK_EN,Repeat reference clock enable.Function: Enables the CMOS output clocks ref_repeat_clk_\{p m\}.This pair of clocks can be used as reference clocks for other on-chip PHYs." "0,1" newline bitfld.long 0x4 5. "PHY_REF_USE_PAD,Select reference clock connected to ref_pad_clk_p/ref_pad_clk_m.Function: Selects the external ref_pad_clk_p and ref_pad_clk_m inputs as the reference clock source when asserted. When deasserted ref_alt_clk_p and ref_alt_clk_m are the.." "0,1" newline bitfld.long 0x4 4. "PHY_TEST_POWERDOWN,All circuits power-down control.Function: Powers down all circuitry in the PHY for IDDQ testing Note:The PHY is not functional in this mode and must be reset after this signal is de-asserted." "0,1" newline bitfld.long 0x4 3. "PHY_TEST_BURNIN,All circuits activator." "0,1" newline bitfld.long 0x4 2. "PHY_RTUNE_REQ,Resistor tune request.Function: Assertion triggers a resistor tune request (if one is not already in progress)." "0,1" newline bitfld.long 0x4 0.--1. "CR_CKDIV,CR_CKDIV Clock divider for CR Bus clock. 0x0 : div 1 from APB bus clock 0x1 : div 2 from APB bus clock ...0x3: div4 from APB bus clock" "div 1 from APB bus clock,div 2 from APB bus clock,?,div4 from APB bus clock" line.long 0x8 "CTRL_2,CTRL_2" newline hexmask.long.byte 0x8 23.--27. 1. "PROTOCOL0_EXT_BS_RX_LEVEL,PROTOCOL0_EXT_BS_RX_LEVEL" newline bitfld.long 0x8 22. "PROTOCOL0_EXT_BS_TX_LOWSWING,PROTOCOL0_EXT_BS_TX_LOWSWING" "0,1" newline bitfld.long 0x8 21. "PROTOCOL0_EXT_BS_RX_BIGSWING,PROTOCOL0_EXT_BS_RX_BIGSWING" "0,1" newline bitfld.long 0x8 20. "PROTOCOL0_EXT_RX_LOS_LFPS_EN,PROTOCOL0_EXT_RX_LOS_LFPS_EN" "0,1" newline bitfld.long 0x8 17.--19. "PROTOCOL0_EXT_REF_RANGE,PROTOCOL0_EXT_REF_RANGE" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 16. "PROTOCOL0_EXT_REF_CLK_MPLLB_DIV2_EN,PROTOCOL0_EXT_REF_CLK_MPLLB_DIV2_EN" "0,1" newline bitfld.long 0x8 15. "PROTOCOL0_EXT_REF_CLK_MPLLA_DIV2_EN,PROTOCOL0_EXT_REF_CLK_MPLLA_DIV2_EN" "0,1" newline bitfld.long 0x8 14. "PROTOCOL0_EXT_REF_CLK_DIV2_EN,PROTOCOL0_EXT_REF_CLK_DIV2_EN" "0,1" newline bitfld.long 0x8 13. "PHY_EXT_CTRL_SEL,PHY_EXT_CTRL_SEL" "0,1" newline bitfld.long 0x8 11.--12. "PIPE_TX1_PATTERN,PIPE_TX1_PATTERN" "0,1,2,3" newline bitfld.long 0x8 10. "PIPE_TX1_ONES_ZEROS,PIPE_TX1_ONES_ZEROS" "0,1" newline bitfld.long 0x8 9. "PIPE_RX1_TERMINATION,PIPE_RX1_TERMINATION" "0,1" newline bitfld.long 0x8 8. "PIPE_RX1_EQ_TRAINING,PIPE_RX1_EQ_TRAINING" "0,1" newline bitfld.long 0x8 7. "PIPE_LANE1_TX2RX_LOOPBK,PIPE_LANE1_TX2RX_LOOPBK" "0,1" newline hexmask.long.byte 0x8 3.--6. 1. "PIPE_LANE1_LINK_NUM,PIPE_LANE1_LINK_NUM" newline bitfld.long 0x8 2. "PIPE_LANE1_CLKREQ_N,PIPE_LANE1_CLKREQ_N" "0,1" newline bitfld.long 0x8 0.--1. "PIPE_TX0_PATTERN,PIPE_TX0_PATTERN" "0,1,2,3" line.long 0xC "CTRL_3,CTRL_3" newline hexmask.long.byte 0xC 22.--29. 1. "PROTOCOL0_EXT_MPLLA_DIV_MULTIPLIER,PROTOCOL0_EXT_MPLLA_DIV_MULTIPLIER" newline hexmask.long.word 0xC 6.--21. 1. "PROTOCOL0_EXT_MPLLA_BANDWIDTH,PROTOCOL0_EXT_MPLLA_BANDWIDTH" newline bitfld.long 0xC 5. "PROTOCOL0_EXT_MPLLA_WORD_DIV2_EN,PROTOCOL0_EXT_MPLLA_WORD_DIV2_EN" "0,1" newline bitfld.long 0xC 4. "PROTOCOL0_EXT_MPLLA_SSC_FREQ_CNT_OVRD_EN,PROTOCOL0_EXT_MPLLA_SSC_FREQ_CNT_OVRD_EN" "0,1" newline bitfld.long 0xC 3. "PROTOCOL0_EXT_MPLLA_DIV_CLK_EN,PROTOCOL0_EXT_MPLLA_DIV_CLK_EN" "0,1" newline bitfld.long 0xC 2. "PROTOCOL0_EXT_MPLLA_DIV8_CLK_EN,PROTOCOL0_EXT_MPLLA_DIV8_CLK_EN" "0,1" newline bitfld.long 0xC 1. "PIPE_RX_RECAL_CONT_EN,PIPE_RX_RECAL_CONT_EN" "0,1" newline bitfld.long 0xC 0. "PROTOCOL0_EXT_MPLLA_DIV10_CLK_EN,PROTOCOL0_EXT_MPLLA_DIV10_CLK_EN" "0,1" line.long 0x10 "CTRL_4,CTRL_4" bitfld.long 0x10 30.--31. "CR_ADDR_BIT15_14,CR_ADDR_BIT15_14" "0,1,2,3" newline bitfld.long 0x10 29. "CR_ADDR_MODE,CR_ADDR_MODE" "0,1" newline bitfld.long 0x10 26.--28. "PROTOCOL0_EXT_MPLLA_SSC_CLK_SEL,PROTOCOL0_EXT_MPLLA_SSC_CLK_SEL" "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x10 18.--25. 1. "PROTOCOL0_EXT_MPLLA_MULTIPLIER,PROTOCOL0_EXT_MPLLA_MULTIPLIER" newline hexmask.long.word 0x10 7.--17. 1. "PROTOCOL0_EXT_MPLLA_FRACN_CTRL,PROTOCOL0_EXT_MPLLA_FRACN_CTRL" newline bitfld.long 0x10 6. "PROTOCOL0_EXT_MPLLB_DIV10_CLK_EN,PROTOCOL0_EXT_MPLLB_DIV10_CLK_EN" "0,1" newline bitfld.long 0x10 3.--5. "PROTOCOL0_EXT_MPLLA_TX_CLK_DIV,PROTOCOL0_EXT_MPLLA_TX_CLK_DIV" "0,1,2,3,4,5,6,7" newline bitfld.long 0x10 0.--2. "PROTOCOL0_EXT_MPLLA_SSC_RANGE,PROTOCOL0_EXT_MPLLA_SSC_RANGE" "0,1,2,3,4,5,6,7" line.long 0x14 "CTRL_5,CTRL_5" hexmask.long.byte 0x14 26.--31. 1. "PIPE_RX0_IDLE_LOS_CNT,PIPE_RX0_IDLE_LOS_CNT" newline bitfld.long 0x14 24. "PIPE_RX0_CMN_REFCLK_MODE,PIPE_RX0_CMN_REFCLK_MODE" "0,1" newline bitfld.long 0x14 23. "PROTOCOL0_EXT_MPLLB_WORD_DIV2_EN,PROTOCOL0_EXT_MPLLB_WORD_DIV2_EN" "0,1" newline hexmask.long.word 0x14 11.--22. 1. "PROTOCOL0_EXT_MPLLA_SSC_FREQ_CNT_INIT,PROTOCOL0_EXT_MPLLA_SSC_FREQ_CNT_INIT" newline bitfld.long 0x14 10. "PROTOCOL0_EXT_MPLLB_SSC_FREQ_CNT_OVRD_EN,PROTOCOL0_EXT_MPLLB_SSC_FREQ_CNT_OVRD_EN" "0,1" newline bitfld.long 0x14 9. "PROTOCOL0_EXT_MPLLB_DIV_CLK_EN,PROTOCOL0_EXT_MPLLB_DIV_CLK_EN" "0,1" newline bitfld.long 0x14 8. "PROTOCOL0_EXT_MPLLB_DIV8_CLK_EN,PROTOCOL0_EXT_MPLLB_DIV8_CLK_EN" "0,1" newline hexmask.long.byte 0x14 0.--7. 1. "PROTOCOL0_EXT_MPLLA_SSC_FREQ_CNT_PEAK,PROTOCOL0_EXT_MPLLA_SSC_FREQ_CNT_PEAK" line.long 0x18 "CTRL_6,CTRL_6" newline hexmask.long.byte 0x18 18.--25. 1. "PROTOCOL0_EXT_MPLLB_DIV_MULTIPLIER,PROTOCOL0_EXT_MPLLB_DIV_MULTIPLIER" newline bitfld.long 0x18 16.--17. "PROTOCOL0_EXT_RX_ADAPT_AFE_EN_G1,PROTOCOL0_EXT_RX_ADAPT_AFE_EN_G1" "0,1,2,3" newline hexmask.long.word 0x18 0.--15. 1. "PROTOCOL0_EXT_MPLLB_BANDWIDTH,PROTOCOL0_EXT_MPLLB_BANDWIDTH" line.long 0x1C "CTRL_7,CTRL_7" hexmask.long.byte 0x1C 26.--31. 1. "PIPE_RX1_IDLE_LOS_CNT,PIPE_RX1_IDLE_LOS_CNT" newline bitfld.long 0x1C 24. "PIPE_RX1_CMN_REFCLK_MODE,PIPE_RX1_CMN_REFCLK_MODE" "0,1" newline bitfld.long 0x1C 22.--23. "PROTOCOL0_EXT_RX_ADAPT_AFE_EN_G2,PROTOCOL0_EXT_RX_ADAPT_AFE_EN_G2" "0,1,2,3" newline bitfld.long 0x1C 19.--21. "PROTOCOL0_EXT_MPLLB_SSC_CLK_SEL,PROTOCOL0_EXT_MPLLB_SSC_CLK_SEL" "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x1C 11.--18. 1. "PROTOCOL0_EXT_MPLLB_MULTIPLIER,PROTOCOL0_EXT_MPLLB_MULTIPLIER" newline hexmask.long.word 0x1C 0.--10. 1. "PROTOCOL0_EXT_MPLLB_FRACN_CTRL,PROTOCOL0_EXT_MPLLB_FRACN_CTRL" line.long 0x20 "CTRL_8,CTRL_8" bitfld.long 0x20 30.--31. "PROTOCOL0_EXT_RX_ADAPT_DFE_EN_G1,PROTOCOL0_EXT_RX_ADAPT_DFE_EN_G1" "0,1,2,3" newline bitfld.long 0x20 26.--27. "PROTOCOL0_EXT_RX_ADAPT_AFE_EN_G3,PROTOCOL0_EXT_RX_ADAPT_AFE_EN_G3" "0,1,2,3" newline bitfld.long 0x20 23.--25. "PROTOCOL0_EXT_MPLLB_TX_CLK_DIV,PROTOCOL0_EXT_MPLLB_TX_CLK_DIV" "0,1,2,3,4,5,6,7" newline bitfld.long 0x20 20.--22. "PROTOCOL0_EXT_MPLLB_SSC_RANGE,PROTOCOL0_EXT_MPLLB_SSC_RANGE" "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x20 12.--19. 1. "PROTOCOL0_EXT_MPLLB_SSC_FREQ_CNT_PEAK,PROTOCOL0_EXT_MPLLB_SSC_FREQ_CNT_PEAK" newline hexmask.long.word 0x20 0.--11. 1. "PROTOCOL0_EXT_MPLLB_SSC_FREQ_CNT_INIT,PROTOCOL0_EXT_MPLLB_SSC_FREQ_CNT_INIT" line.long 0x24 "CTRL_9,CTRL_9" newline hexmask.long.byte 0x24 20.--27. 1. "PROTOCOL0_EXT_RX_EQ_AFE_GAIN_G3,PROTOCOL0_EXT_RX_EQ_AFE_GAIN_G3" newline hexmask.long.byte 0x24 12.--19. 1. "PROTOCOL0_EXT_RX_EQ_AFE_GAIN_G2,PROTOCOL0_EXT_RX_EQ_AFE_GAIN_G2" newline hexmask.long.byte 0x24 4.--11. 1. "PROTOCOL0_EXT_RX_EQ_AFE_GAIN_G1,PROTOCOL0_EXT_RX_EQ_AFE_GAIN_G1" newline bitfld.long 0x24 2.--3. "PROTOCOL0_EXT_RX_ADAPT_DFE_EN_G3,PROTOCOL0_EXT_RX_ADAPT_DFE_EN_G3" "0,1,2,3" newline bitfld.long 0x24 0.--1. "PROTOCOL0_EXT_RX_ADAPT_DFE_EN_G2,PROTOCOL0_EXT_RX_ADAPT_DFE_EN_G2" "0,1,2,3" line.long 0x28 "CTRL_10,CTRL_10" newline bitfld.long 0x28 22.--23. "PROTOCOL0_EXT_RX_CDR_VCO_LOWFREQ_G3,PROTOCOL0_EXT_RX_CDR_VCO_LOWFREQ_G3" "0,1,2,3" newline bitfld.long 0x28 20.--21. "PROTOCOL0_EXT_RX_CDR_VCO_LOWFREQ_G2,PROTOCOL0_EXT_RX_CDR_VCO_LOWFREQ_G2" "0,1,2,3" newline bitfld.long 0x28 18.--19. "PROTOCOL0_EXT_RX_CDR_VCO_LOWFREQ_G1,PROTOCOL0_EXT_RX_CDR_VCO_LOWFREQ_G1" "0,1,2,3" newline hexmask.long.byte 0x28 12.--17. 1. "PROTOCOL0_EXT_RX_EQ_ATT_LVL_G3,PROTOCOL0_EXT_RX_EQ_ATT_LVL_G3" newline hexmask.long.byte 0x28 6.--11. 1. "PROTOCOL0_EXT_RX_EQ_ATT_LVL_G2,PROTOCOL0_EXT_RX_EQ_ATT_LVL_G2" newline hexmask.long.byte 0x28 0.--5. 1. "PROTOCOL0_EXT_RX_EQ_ATT_LVL_G1,PROTOCOL0_EXT_RX_EQ_ATT_LVL_G1" line.long 0x2C "CTRL_11,CTRL_11" newline hexmask.long.word 0x2C 20.--29. 1. "PROTOCOL0_EXT_RX_EQ_CTLE_BOOST_G3,PROTOCOL0_EXT_RX_EQ_CTLE_BOOST_G3" newline hexmask.long.word 0x2C 10.--19. 1. "PROTOCOL0_EXT_RX_EQ_CTLE_BOOST_G2,PROTOCOL0_EXT_RX_EQ_CTLE_BOOST_G2" newline hexmask.long.word 0x2C 0.--9. 1. "PROTOCOL0_EXT_RX_EQ_CTLE_BOOST_G1,PROTOCOL0_EXT_RX_EQ_CTLE_BOOST_G1" line.long 0x30 "CTRL_12,CTRL_12" newline hexmask.long.byte 0x30 8.--15. 1. "PROTOCOL0_EXT_RX_EQ_DELTA_IQ_G2,PROTOCOL0_EXT_RX_EQ_DELTA_IQ_G2" newline hexmask.long.byte 0x30 0.--7. 1. "PROTOCOL0_EXT_RX_EQ_DELTA_IQ_G1,PROTOCOL0_EXT_RX_EQ_DELTA_IQ_G1" line.long 0x34 "CTRL_13,CTRL_13" newline hexmask.long.word 0x34 8.--23. 1. "PROTOCOL0_EXT_RX_EQ_DFE_TAP1_G1,PROTOCOL0_EXT_RX_EQ_DFE_TAP1_G1" newline hexmask.long.byte 0x34 0.--7. 1. "PROTOCOL0_EXT_RX_EQ_DELTA_IQ_G3,PROTOCOL0_EXT_RX_EQ_DELTA_IQ_G3" line.long 0x38 "CTRL_14,CTRL_14" hexmask.long.word 0x38 16.--31. 1. "PROTOCOL0_EXT_RX_EQ_DFE_TAP1_G3,PROTOCOL0_EXT_RX_EQ_DFE_TAP1_G3" newline hexmask.long.word 0x38 0.--15. 1. "PROTOCOL0_EXT_RX_EQ_DFE_TAP1_G2,PROTOCOL0_EXT_RX_EQ_DFE_TAP1_G2" repeat 6. (list 0xF 0x17 0x18 0x19 0x1A 0x1B )(list 0x0 0x20 0x24 0x28 0x2C 0x30 ) group.long ($2+0x3C)++0x3 line.long 0x0 "CTRL_$1,CTRL_15" hexmask.long 0x0 0.--31. 1. "RSVD0,RSVD0" repeat.end group.long 0x40++0x1B line.long 0x0 "CTRL_16,CTRL_16" newline hexmask.long.byte 0x0 18.--23. 1. "PROTOCOL0_EXT_RX_REF_LD_VAL_G3,PROTOCOL0_EXT_RX_REF_LD_VAL_G3" newline hexmask.long.byte 0x0 12.--17. 1. "PROTOCOL0_EXT_RX_REF_LD_VAL_G2,PROTOCOL0_EXT_RX_REF_LD_VAL_G2" newline hexmask.long.byte 0x0 6.--11. 1. "PROTOCOL0_EXT_RX_REF_LD_VAL_G1,PROTOCOL0_EXT_RX_REF_LD_VAL_G1" newline hexmask.long.byte 0x0 0.--5. 1. "PROTOCOL0_EXT_RX_LOS_THRESHOLD,PROTOCOL0_EXT_RX_LOS_THRESHOLD" line.long 0x4 "CTRL_17,CTRL_17" newline hexmask.long.word 0x4 16.--28. 1. "PROTOCOL0_EXT_RX_VCO_LD_VAL_G2,PROTOCOL0_EXT_RX_VCO_LD_VAL_G2" newline hexmask.long.word 0x4 3.--15. 1. "PROTOCOL0_EXT_RX_VCO_LD_VAL_G1,PROTOCOL0_EXT_RX_VCO_LD_VAL_G1" newline bitfld.long 0x4 0.--2. "PROTOCOL0_EXT_RX_TERM_CTRL,PROTOCOL0_EXT_RX_TERM_CTRL" "0,1,2,3,4,5,6,7" line.long 0x8 "CTRL_18,CTRL_18" newline hexmask.long.byte 0x8 13.--17. 1. "PROTOCOL0_EXT_RX_VREF_CTRL,PROTOCOL0_EXT_RX_VREF_CTRL" newline hexmask.long.word 0x8 0.--12. 1. "PROTOCOL0_EXT_RX_VCO_LD_VAL_G3,PROTOCOL0_EXT_RX_VCO_LD_VAL_G3" line.long 0xC "CTRL_19,CTRL_19" newline hexmask.long.word 0xC 16.--25. 1. "PROTOCOL0_EXT_TX_EQ_MAIN_G2,PROTOCOL0_EXT_TX_EQ_MAIN_G2" newline hexmask.long.word 0xC 6.--15. 1. "PROTOCOL0_EXT_TX_EQ_MAIN_G1,PROTOCOL0_EXT_TX_EQ_MAIN_G1" newline bitfld.long 0xC 4.--5. "PROTOCOL0_EXT_TX_EQ_OVRD_G3,PROTOCOL0_EXT_TX_EQ_OVRD_G3" "0,1,2,3" newline bitfld.long 0xC 2.--3. "PROTOCOL0_EXT_TX_EQ_OVRD_G2,PROTOCOL0_EXT_TX_EQ_OVRD_G2" "0,1,2,3" newline bitfld.long 0xC 0.--1. "PROTOCOL0_EXT_TX_EQ_OVRD_G1,PROTOCOL0_EXT_TX_EQ_OVRD_G1" "0,1,2,3" line.long 0x10 "CTRL_20,CTRL_20" newline hexmask.long.byte 0x10 18.--25. 1. "PROTOCOL0_EXT_TX_EQ_POST_G2,PROTOCOL0_EXT_TX_EQ_POST_G2" newline hexmask.long.byte 0x10 10.--17. 1. "PROTOCOL0_EXT_TX_EQ_POST_G1,PROTOCOL0_EXT_TX_EQ_POST_G1" newline hexmask.long.word 0x10 0.--9. 1. "PROTOCOL0_EXT_TX_EQ_MAIN_G3,PROTOCOL0_EXT_TX_EQ_MAIN_G3" line.long 0x14 "CTRL_21,CTRL_21" hexmask.long.byte 0x14 24.--31. 1. "PROTOCOL0_EXT_TX_EQ_PRE_G3,PROTOCOL0_EXT_TX_EQ_PRE_G3" newline hexmask.long.byte 0x14 16.--23. 1. "PROTOCOL0_EXT_TX_EQ_PRE_G2,PROTOCOL0_EXT_TX_EQ_PRE_G2" newline hexmask.long.byte 0x14 8.--15. 1. "PROTOCOL0_EXT_TX_EQ_PRE_G1,PROTOCOL0_EXT_TX_EQ_PRE_G1" newline hexmask.long.byte 0x14 0.--7. 1. "PROTOCOL0_EXT_TX_EQ_POST_G3,PROTOCOL0_EXT_TX_EQ_POST_G3" line.long 0x18 "CTRL_22,CTRL_22" hexmask.long.word 0x18 16.--31. 1. "DEBUG_CTL_79_64,DEBUG_CTL_79_64" newline bitfld.long 0x18 11.--13. "PROTOCOL0_EXT_TX_VBOOST_LVL,PROTOCOL0_EXT_TX_VBOOST_LVL" "0,1,2,3,4,5,6,7" newline bitfld.long 0x18 8.--10. "PROTOCOL0_EXT_TX_TERM_CTRL,PROTOCOL0_EXT_TX_TERM_CTRL" "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x18 0.--7. 1. "PROTOCOL0_EXT_TX_IBOOST_LVL,PROTOCOL0_EXT_TX_IBOOST_LVL" rgroup.long 0x80++0x7 line.long 0x0 "STS_0,STS_0" bitfld.long 0x0 31. "PIPE_RX1_ALIGN_DETECT,RX ALIGN symbol detected for lane 1;indicates receiver detection of an Align." "0,1" newline hexmask.long.word 0x0 22.--30. 1. "PIPE_RX1_EBUFF_LOCATION,Entries in elastic buffer for lane 1.Encodes the number of entries currently in the elastic buffer." newline bitfld.long 0x0 21. "PIPE_LANE1_POWER_PRESENT,Reserved." "0,1" newline bitfld.long 0x0 19.--20. "PIPE_LANE1_DATABUSWIDTH,Bus width configuration for lane 1.This field reports the width of the data bus configured for the PHY." "0,1,2,3" newline hexmask.long.word 0x0 10.--18. 1. "PIPE_RX0_EBUFF_LOCATION,Similar to PIPE_RX1_EBUFF_LOCATION." newline bitfld.long 0x0 9. "PIPE_RX0_ALIGN_DETECT,Similar to PIPE_RX1_ALIGN_DETECT." "0,1" newline bitfld.long 0x0 8. "PIPE_LANE1_CLKACK_N,Clock acknowledge for lane 1" "0,1" newline bitfld.long 0x0 7. "PIPE_LANE0_CLKACK_N,Similar to PIPE_LANE1_CLKACK_N" "0,1" newline bitfld.long 0x0 6. "PIPE_LANE0_POWER_PRESENT,Similar to PIPE_LANE1_POWER_PRESENT" "0,1" newline bitfld.long 0x0 4.--5. "PIPE_LANE0_DATABUSWIDTH,Similar to PIPE_LANE1_DATABUSWIDTH" "0,1,2,3" newline bitfld.long 0x0 3. "PHY_ANA_PWR_STABLE,Internal PMA switch stable.Function: Stable status signal from the PMA power switch." "0,1" newline bitfld.long 0x0 2. "PHY_RTUNE_ACK,Resistor tune acknowledge.Function: Indicates that a resistor tune has completed" "0,1" newline bitfld.long 0x0 1. "PHY_MPLLB_STATE,MPLLB state indicator.Function: Indicates the state of mpllb. This signal is asserted when MPLLB is powered up and phase-locked." "0,1" newline bitfld.long 0x0 0. "PHY_MPLLA_STATE,MPLLA state indicator.Function: Indicates the state of mplla. This signal is asserted when MPLLA is powered up and phase-locked." "0,1" line.long 0x4 "STS_1,STS_1" hexmask.long 0x4 4.--31. 1. "RSVD0,RSVD0" newline bitfld.long 0x4 3. "UPCS_PWR_EN,Power enable for PCS power switch(es).Enable signal for external switch(es) to supply power to the power-gated logic in the PCS" "0,1" newline bitfld.long 0x4 2. "PHY_PCS_PWR_EN,Power enable for Raw PCS power switches.Function: Enable signal for external switches to supply power to the power gated logic in Raw PCS." "0,1" newline bitfld.long 0x4 1. "PHY_PMA_PWR_EN,Power enable for PMA power switch Function: Enable signal for PMA power switch (external) to supply power to the PMA." "0,1" newline bitfld.long 0x4 0. "PHY_SRAM_INIT_DONE,SRAM Initialization done Function: Signal indicating that the SRAM has been initialized by the boot loader in the Raw PCS.This signal will not assert if sram_bypass is asserted." "0,1" repeat 6. (list 0x2 0x3 0x4 0x5 0x6 0x7 )(list 0x0 0x4 0x8 0xC 0x10 0x14 ) rgroup.long ($2+0x88)++0x3 line.long 0x0 "STS_$1,STS_2" hexmask.long 0x0 0.--31. 1. "RSVD0,RSVD0" repeat.end tree.end elif (CORENAME()=="CORTEXA55") tree "PCIE_PHY" base ad:0x31200000 rgroup.word 0x0++0x1 line.word 0x0 "SUP_DIG_IDCODE_LO,Low 16 bits of IDCODE" newline hexmask.word 0x0 0.--15. 1. "DATA," rgroup.word 0x4++0x1 line.word 0x0 "SUP_DIG_IDCODE_HI,High 16 bits of IDCODE" newline hexmask.word 0x0 0.--15. 1. "DATA," group.word 0x8++0x1 line.word 0x0 "SUP_DIG_REFCLK_OVRD_IN,Override values for incoming REFCLK and RESET controls from ASIC" newline rbitfld.word 0x0 14.--15. "RESERVED_15_14,Reserved for Future use" "0,1,2,3" newline bitfld.word 0x0 13. "BG_EN_OVRD_EN,Enable override for bg_en" "0,1" newline bitfld.word 0x0 12. "BG_EN,Override value for bg_en" "0,1" newline bitfld.word 0x0 11. "REF_CLK_RANGE_OVRD_EN,Enable override for ref_range" "0,1" newline bitfld.word 0x0 8.--10. "REF_CLK_RANGE,Override value for ref_range" "0,1,2,3,4,5,6,7" newline bitfld.word 0x0 7. "REF_REPEAT_CLK_EN_OVRD_EN,Enable override for ref_repeat_clk_en" "0,1" newline bitfld.word 0x0 6. "REF_REPEAT_CLK_EN,Override value for ref_repeat_clk_en" "0,1" newline bitfld.word 0x0 5. "REF_USE_PAD_OVRD_EN,Enable override for ref_use_pad" "0,1" newline bitfld.word 0x0 4. "REF_USE_PAD,Override value for ref_use_pad" "0,1" newline bitfld.word 0x0 3. "REF_CLK_DIV2_EN_OVRD_EN,Enable override for ref_clk_div2_en" "0,1" newline bitfld.word 0x0 2. "REF_CLK_DIV2_EN,Override value for ref_clk_div2_en" "0,1" newline bitfld.word 0x0 1. "REF_CLK_EN_OVRD_EN,Enable override for ref_clk_en" "0,1" newline bitfld.word 0x0 0. "REF_CLK_EN,Override value for ref_clk_en" "0,1" group.word 0xC++0x1 line.word 0x0 "SUP_DIG_MPLLA_DIV_CLK_OVRD_IN,Override values for incoming MPLLA_DIV_CLK controls from ASIC" newline hexmask.word.byte 0x0 10.--15. 1. "RESERVED_15_10,Reserved for Future use" newline bitfld.word 0x0 9. "MPLLA_DIV_OVRD_EN,Enable overrides for MPLLA Div clock" "0,1" newline hexmask.word.byte 0x0 1.--8. 1. "MPLLA_DIV_MULTIPLIER,Override value for mplla_div_multiplier" newline bitfld.word 0x0 0. "MPLLA_DIV_CLK_EN,Override value for mplla_div_clk_en" "0,1" group.word 0x10++0x1 line.word 0x0 "SUP_DIG_MPLLB_DIV_CLK_OVRD_IN,Override values for incoming MPLLB_DIV_CLK controls from ASIC" newline hexmask.word.byte 0x0 10.--15. 1. "RESERVED_15_10,Reserved for Future use" newline bitfld.word 0x0 9. "MPLLB_DIV_OVRD_EN,Enable overrides for MPLLB Div clock" "0,1" newline hexmask.word.byte 0x0 1.--8. 1. "MPLLB_DIV_MULTIPLIER,Override value for mpllb_div_multiplier" newline bitfld.word 0x0 0. "MPLLB_DIV_CLK_EN,Override value for mpllb_div_clk_en" "0,1" group.word 0x14++0x1 line.word 0x0 "SUP_DIG_MPLLA_OVRD_IN_0,Override values for incoming MPLLA controls from ASIC" newline bitfld.word 0x0 15. "OVRD_EN,Enable override values for all inputs controlled by this register (mplla_word_div2_en)" "0,1" newline bitfld.word 0x0 12.--14. "MPLLA_TX_CLK_DIV,Override value for mplla_tx_clk_div" "0,1,2,3,4,5,6,7" newline hexmask.word.byte 0x0 4.--11. 1. "MPLLA_MULTIPLIER,Override value for mplla_multiplier" newline bitfld.word 0x0 3. "MPLLA_DIV10_CLK_EN,Override value for mplla_div10_clk_en" "0,1" newline bitfld.word 0x0 2. "MPLLA_DIV8_CLK_EN,Override value for mplla_div8_clk_en" "0,1" newline bitfld.word 0x0 1. "REF_CLK_MPLLA_DIV2_EN,Override value for ref_clk_mplla_div2_en" "0,1" newline bitfld.word 0x0 0. "MPLLA_EN,Override value for mplla_en" "0,1" group.word 0x18++0x1 line.word 0x0 "SUP_DIG_MPLLA_OVRD_IN_1,Override values for incoming MPLLA controls from ASIC" newline hexmask.word.byte 0x0 9.--15. 1. "RESERVED_15_9,Reserved for Future use" newline bitfld.word 0x0 8. "MPLLA_WORD_DIV2_EN,Override value for mplla_word_div2_en" "0,1" newline bitfld.word 0x0 7. "MPLLA_SSC_OVRD_EN,Enable override values for MPLLA SSC inputs" "0,1" newline bitfld.word 0x0 4.--6. "MPLLA_SSC_CLK_SEL,Override value for mplla_ssc_clk_sel" "0,1,2,3,4,5,6,7" newline bitfld.word 0x0 1.--3. "MPLLA_SSC_RANGE,Override value for mplla_ssc_range" "0,1,2,3,4,5,6,7" newline bitfld.word 0x0 0. "MPLLA_SSC_EN,Override value for mplla_ssc_en" "0,1" group.word 0x1C++0x1 line.word 0x0 "SUP_DIG_MPLLA_OVRD_IN_2,Override values for incoming MPLLA controls from ASIC" newline hexmask.word.byte 0x0 11.--15. 1. "RESERVED_15_11,Reserved for Future use" newline hexmask.word 0x0 0.--10. 1. "MPLLA_FRACN_CTRL,Override value for mplla_fracn_ctrl" group.word 0x20++0x1 line.word 0x0 "SUP_DIG_MPLLA_BANDWIDTH_OVRD_IN,Override values for incoming MPLLA bandwidth controls from ASIC" newline hexmask.word 0x0 0.--15. 1. "MPLLA_BANDWIDTH,Override value for mplla_bandwidth[15:0]" group.word 0x24++0x1 line.word 0x0 "SUP_DIG_MPLLB_OVRD_IN_0,Override values for incoming MPLLB controls from ASIC" newline bitfld.word 0x0 15. "OVRD_EN,Enable override values for all inputs controlled by this register" "0,1" newline bitfld.word 0x0 12.--14. "MPLLB_TX_CLK_DIV,Override value for mpllb_tx_clk_div" "0,1,2,3,4,5,6,7" newline hexmask.word.byte 0x0 4.--11. 1. "MPLLB_MULTIPLIER,Override value for mpllb_multiplier" newline bitfld.word 0x0 3. "MPLLB_DIV10_CLK_EN,Override value for mpllb_div10_clk_en" "0,1" newline bitfld.word 0x0 2. "MPLLB_DIV8_CLK_EN,Override value for mpllb_div8_clk_en" "0,1" newline bitfld.word 0x0 1. "REF_CLK_MPLLB_DIV2_EN,Override value for ref_clk_mpllb_div2_en" "0,1" newline bitfld.word 0x0 0. "MPLLB_EN,Override value for mpllb_en" "0,1" group.word 0x28++0x1 line.word 0x0 "SUP_DIG_MPLLB_OVRD_IN_1,Override values for incoming MPLLB controls from ASIC" newline hexmask.word.byte 0x0 9.--15. 1. "RESERVED_15_9,Reserved for Future use" newline bitfld.word 0x0 8. "MPLLB_WORD_DIV2_EN,Override value for mpllb_word_div2_en" "0,1" newline bitfld.word 0x0 7. "MPLLB_SSC_OVRD_EN,Enable override values for MPLLB SSC inputs" "0,1" newline bitfld.word 0x0 4.--6. "MPLLB_SSC_CLK_SEL,Override value for mpllb_ssc_clk_sel[2:0]" "0,1,2,3,4,5,6,7" newline bitfld.word 0x0 1.--3. "MPLLB_SSC_RANGE,Override value for mpllb_ssc_range" "0,1,2,3,4,5,6,7" newline bitfld.word 0x0 0. "MPLLB_SSC_EN,Override value for mpllb_ssc_en" "0,1" group.word 0x2C++0x1 line.word 0x0 "SUP_DIG_MPLLB_OVRD_IN_2,Override values for incoming MPLLB controls from ASIC" newline hexmask.word.byte 0x0 11.--15. 1. "RESERVED_15_11,Reserved for Future use" newline hexmask.word 0x0 0.--10. 1. "MPLLB_FRACN_CTRL,Override value for mpllb_fracn_ctrl" group.word 0x30++0x1 line.word 0x0 "SUP_DIG_MPLLB_BANDWIDTH_OVRD_IN,Override values for incoming MPLLB bandwidth controls from ASIC" newline hexmask.word 0x0 0.--15. 1. "MPLLB_BANDWIDTH,Override value for mpllb_bandwidth[15:0]" group.word 0x34++0x1 line.word 0x0 "SUP_DIG_SUP_OVRD_IN,Override values for support block ASIC inputs" newline hexmask.word 0x0 5.--15. 1. "RESERVED_15_5,Reserved for Future use" newline bitfld.word 0x0 4. "RES_OVRD_EN,Enable override of res_req_in and res_ack_in" "0,1" newline bitfld.word 0x0 3. "RES_ACK_IN,Override value for res_ack_in" "0,1" newline bitfld.word 0x0 2. "RES_REQ_IN,Override value for res_req_in" "0,1" newline bitfld.word 0x0 1. "RTUNE_OVRD_EN,Enable override of rtune_req" "0,1" newline bitfld.word 0x0 0. "RTUNE_REQ,Override value for rtune_req" "0,1" group.word 0x38++0x1 line.word 0x0 "SUP_DIG_SUP_OVRD_OUT,Override values for support block ASIC outputs" newline rbitfld.word 0x0 14.--15. "RESERVED_15_14,Reserved for Future use" "0,1,2,3" newline bitfld.word 0x0 13. "BG_SUP_STATE_OVRD_EN,Enable override for bg_sup_state signal" "0,1" newline bitfld.word 0x0 12. "BG_SUP_STATE,Override value for bg_sup_state signal" "0,1" newline bitfld.word 0x0 11. "BG_LANE_STATE_OVRD_EN,Enable override for bg_lane_state signal" "0,1" newline bitfld.word 0x0 10. "BG_LANE_STATE,Override value for bg_lane_state signal" "0,1" newline bitfld.word 0x0 9. "MPLLB_STATE_OVRD_EN,Enable override for mpllb_state output" "0,1" newline bitfld.word 0x0 8. "MPLLB_STATE,Override value for mpllb_state output" "0,1" newline bitfld.word 0x0 7. "MPLLA_STATE_OVRD_EN,Enable override for mplla_state output" "0,1" newline bitfld.word 0x0 6. "MPLLA_STATE,Override value for mplla_state output" "0,1" newline bitfld.word 0x0 5. "RES_ACK_OUT_OVRD_EN,Enable override for res_ack_out output" "0,1" newline bitfld.word 0x0 4. "RES_ACK_OUT,Override value for res_ack_out output" "0,1" newline bitfld.word 0x0 3. "RES_REQ_OUT_OVRD_EN,Enable override for res_req_out output" "0,1" newline bitfld.word 0x0 2. "RES_REQ_OUT,Override value for res_req_out output" "0,1" newline bitfld.word 0x0 1. "RTUNE_ACK_OVRD_EN,Enable override for rtune_ack output" "0,1" newline bitfld.word 0x0 0. "RTUNE_ACK,Override value for rtune_ack output" "0,1" group.word 0x3C++0x1 line.word 0x0 "SUP_DIG_LVL_OVRD_IN,Override values for level settings" newline hexmask.word.byte 0x0 10.--15. 1. "RESERVED_15_10,Reserved for Future use" newline bitfld.word 0x0 9. "TX_VBOOST_LVL_EN,Enable override value for tx_vboost_lvl" "0,1" newline bitfld.word 0x0 6.--8. "TX_VBOOST_LVL,Override value for tx_vboost_lvl" "0,1,2,3,4,5,6,7" newline bitfld.word 0x0 5. "RX_VREF_CTRL_EN,Enable override value for rx_vref_ctrl" "0,1" newline hexmask.word.byte 0x0 0.--4. 1. "RX_VREF_CTRL,Override value for rx_vref_ctrl" group.word 0x40++0x1 line.word 0x0 "SUP_DIG_DEBUG,Debug controls" newline hexmask.word 0x0 3.--15. 1. "RESERVED_15_3,Reserved for Future use" newline bitfld.word 0x0 0.--2. "DTB_SEL,The lane DTB's are OR'd together with the support DTB signals selected with the below encodings 0 - none 1 - mplla DTB output 2 - mpllb DTB output 3 - rtune DTB output" "none,mplla DTB output,mpllb DTB output,rtune DTB output,?,?,?,?" rgroup.word 0x44++0x1 line.word 0x0 "SUP_DIG_MPLLA_ASIC_IN_0,Current values for incoming MPLLA controls from ASIC" newline bitfld.word 0x0 15. "RESERVED_15_15,Reserved for Future use" "0,1" newline bitfld.word 0x0 12.--14. "MPLLA_TX_CLK_DIV,Value from ASIC for mplla_tx_clk_div" "0,1,2,3,4,5,6,7" newline hexmask.word.byte 0x0 4.--11. 1. "MPLLA_MULTIPLIER,Value from ASIC for mplla_multiplier" newline bitfld.word 0x0 3. "MPLLA_DIV10_CLK_EN,Value from ASIC for mplla_div10_clk_en" "0,1" newline bitfld.word 0x0 2. "MPLLA_DIV8_CLK_EN,Value from ASIC for mplla_div8_clk_en" "0,1" newline bitfld.word 0x0 1. "REF_CLK_MPLLA_DIV2_EN,Value from ASIC for ref_clk_mplla_div2_en" "0,1" newline bitfld.word 0x0 0. "MPLLA_EN,Value from ASIC for mplla_en" "0,1" rgroup.word 0x48++0x1 line.word 0x0 "SUP_DIG_MPLLA_ASIC_IN_1,Current values for incoming MPLLA controls from ASIC" newline hexmask.word.byte 0x0 8.--15. 1. "RESERVED_15_8,Reserved for Future use" newline bitfld.word 0x0 7. "MPLLA_WORD_DIV2_EN,Value from mplla_word_div2_en" "0,1" newline bitfld.word 0x0 4.--6. "MPLLA_SSC_CLK_SEL,Value from mplla_ssc_clk_sel" "0,1,2,3,4,5,6,7" newline bitfld.word 0x0 1.--3. "MPLLA_SSC_RANGE,Value from mplla_ssc_range" "0,1,2,3,4,5,6,7" newline bitfld.word 0x0 0. "MPLLA_SSC_EN,Value from mplla_ssc_en" "0,1" rgroup.word 0x4C++0x1 line.word 0x0 "SUP_DIG_MPLLA_ASIC_IN_2,Current values for incoming MPLLA controls from ASIC" newline hexmask.word.byte 0x0 11.--15. 1. "RESERVED_15_11,Reserved for Future use" newline hexmask.word 0x0 0.--10. 1. "MPLLA_FRACN_CTRL,Value from mplla_fracn_ctrl" rgroup.word 0x50++0x1 line.word 0x0 "SUP_DIG_MPLLB_ASIC_IN_0,Current values for incoming MPLLB controls from ASIC" newline bitfld.word 0x0 15. "RESERVED_15_15,Reserved for Future use" "0,1" newline bitfld.word 0x0 12.--14. "MPLLB_TX_CLK_DIV,Value from ASIC for mpllb_tx_clk_div" "0,1,2,3,4,5,6,7" newline hexmask.word.byte 0x0 4.--11. 1. "MPLLB_MULTIPLIER,Value from ASIC for mpllb_multiplier" newline bitfld.word 0x0 3. "MPLLB_DIV10_CLK_EN,Value from ASIC for mpllb_div10_clk_en" "0,1" newline bitfld.word 0x0 2. "MPLLB_DIV8_CLK_EN,Value from ASIC for mpllb_div8_clk_en" "0,1" newline bitfld.word 0x0 1. "REF_CLK_MPLLB_DIV2_EN,Value from ASIC for ref_clk_mpllb_div2_en" "0,1" newline bitfld.word 0x0 0. "MPLLB_EN,Value from ASIC for mpllb_en" "0,1" rgroup.word 0x54++0x1 line.word 0x0 "SUP_DIG_MPLLB_ASIC_IN_1,Current values for incoming MPLLB controls from ASIC" newline hexmask.word.byte 0x0 8.--15. 1. "RESERVED_15_8,Reserved for Future use" newline bitfld.word 0x0 7. "MPLLB_WORD_DIV2_EN,Value from mpllb_word_div2_en" "0,1" newline bitfld.word 0x0 4.--6. "MPLLB_SSC_CLK_SEL,Value from mpllb_ssc_clk_sel" "0,1,2,3,4,5,6,7" newline bitfld.word 0x0 1.--3. "MPLLB_SSC_RANGE,Value from mpllb_ssc_range" "0,1,2,3,4,5,6,7" newline bitfld.word 0x0 0. "MPLLB_SSC_EN,Value from mpllb_ssc_en" "0,1" rgroup.word 0x58++0x1 line.word 0x0 "SUP_DIG_MPLLB_ASIC_IN_2,Current values for incoming MPLLB controls from ASIC" newline hexmask.word.byte 0x0 11.--15. 1. "RESERVED_15_11,Reserved for Future use" newline hexmask.word 0x0 0.--10. 1. "MPLLB_FRACN_CTRL,Value from mpllb_fracn_ctrl" rgroup.word 0x5C++0x1 line.word 0x0 "SUP_DIG_MPLLA_DIV_CLK_ASIC_IN,Current values for incoming MPLLA_DIV_CLK controls from ASIC" newline hexmask.word.byte 0x0 9.--15. 1. "RESERVED_15_9,Reserved for Future use" newline hexmask.word.byte 0x0 1.--8. 1. "MPLLA_DIV_MULTIPLIER,Value from mplla_div_multiplier" newline bitfld.word 0x0 0. "MPLLA_DIV_CLK_EN,Value from mplla_div_clk_en" "0,1" rgroup.word 0x60++0x1 line.word 0x0 "SUP_DIG_MPLLB_DIV_CLK_ASIC_IN,Current values for incoming MPLLB_DIV_CLK controls from ASIC" newline hexmask.word.byte 0x0 9.--15. 1. "RESERVED_15_9,Reserved for Future use" newline hexmask.word.byte 0x0 1.--8. 1. "MPLLB_DIV_MULTIPLIER,Value from mpllb_div_multiplier" newline bitfld.word 0x0 0. "MPLLB_DIV_CLK_EN,Value from mpllb_div_clk_en" "0,1" rgroup.word 0x64++0x1 line.word 0x0 "SUP_DIG_ASIC_IN,Current values for incoming SUP control signals from ASIC" newline bitfld.word 0x0 15. "TEST_TX_REF_CLK_EN,Value from ASIC for test_tx_refclk_en" "0,1" newline bitfld.word 0x0 14. "MPLLB_STATE,Value to ASIC for mpllb_state_i" "0,1" newline bitfld.word 0x0 13. "MPLLA_STATE,Value to ASIC for mplla_state_i" "0,1" newline bitfld.word 0x0 12. "RES_ACK_OUT,Value to ASIC for res_ack_out_i" "0,1" newline bitfld.word 0x0 11. "RES_ACK_IN,Value from ASIC for res_req_in" "0,1" newline bitfld.word 0x0 10. "RES_REQ_OUT,Value to ASIC for res_ack_out_i" "0,1" newline bitfld.word 0x0 9. "RES_REQ_IN,Value from ASIC for res_req_in" "0,1" newline bitfld.word 0x0 8. "RTUNE_ACK,Value to ASIC for rtune_ack_i" "0,1" newline bitfld.word 0x0 7. "RTUNE_REQ,Value from ASIC for rtune_req" "0,1" newline bitfld.word 0x0 6. "TEST_POWERDOWN,Value from ASIC for test_powerdown" "0,1" newline bitfld.word 0x0 5. "TEST_BURNIN,Value from ASIC for test_burnin" "0,1" newline bitfld.word 0x0 4. "REF_USE_PAD,Value from ASIC for ref_use_pad" "0,1" newline bitfld.word 0x0 3. "REF_REPEAT_CLK_EN,Value from ASIC for ref_repeat_clk_en" "0,1" newline bitfld.word 0x0 2. "REF_CLK_DIV2_EN,Value from ASIC for ref_clk_div2_en" "0,1" newline bitfld.word 0x0 1. "REF_CLK_EN,Value from ASIC for ref_clk_en" "0,1" newline bitfld.word 0x0 0. "PHY_RESET,Value from ASIC for phy_reset" "0,1" rgroup.word 0x68++0x1 line.word 0x0 "SUP_DIG_LVL_ASIC_IN,Current values for incoming level controls from ASIC" newline hexmask.word.byte 0x0 8.--15. 1. "RESERVED_15_8,Reserved for Future use" newline bitfld.word 0x0 5.--7. "TX_VBOOST_LVL,Value from ASIC for tx_vboost_lvl" "0,1,2,3,4,5,6,7" newline hexmask.word.byte 0x0 0.--4. 1. "RX_VREF_CTRL,Value from ASIC for rx_vref_ctrl" rgroup.word 0x6C++0x1 line.word 0x0 "SUP_DIG_BANDGAP_ASIC_IN,Current values for incoming bandgap control from ASIC" newline hexmask.word 0x0 1.--15. 1. "RESERVED_15_1,Reserved for Future use" newline bitfld.word 0x0 0. "BG_EN,Value from ASIC for bg_en" "0,1" rgroup.word 0x70++0x1 line.word 0x0 "SUP_DIG_MPLLA_BANDWIDTH_ASIC_IN,Current values for incoming MPLLA bandwidth controls from ASIC" newline hexmask.word 0x0 0.--15. 1. "MPLLA_BANDWIDTH,Value from ASIC for mplla_bandwidth" rgroup.word 0x74++0x1 line.word 0x0 "SUP_DIG_MPLLB_BANDWIDTH_ASIC_IN,Current values for incoming MPLLB bandwidth controls from ASIC" newline hexmask.word 0x0 0.--15. 1. "MPLLB_BANDWIDTH,Value from ASIC for mpllb_bandwidth" group.word 0x80++0x1 line.word 0x0 "SUP_DIG_MPLLA_MPLL_PWR_CTL_CAL_CTRL,MPLL Calibration controls" newline bitfld.word 0x0 15. "EXT_CAL_DONE,Set the external calibration status to done" "0,1" newline hexmask.word.byte 0x0 7.--14. 1. "EXT_COARSE_TUNE,Value of mpll_ana_coarse_tune_i[7:0] in external calibration mode" newline bitfld.word 0x0 6. "EXT_CHKFRQ_EN,Check the frequency of the MPLL Only valid in external calibration mode" "0,1" newline bitfld.word 0x0 5. "MPLL_EXTCAL,Enable external calibration of MPLL" "0,1" newline bitfld.word 0x0 4. "MPLL_SKIPCAL,Skip automatic (internal) calibration of MPLL (and also skip external calibration if it is enabled) If skipcal is enabled then MPLL_SKIPCAL_COARSE_TUNE is used." "0,1" newline hexmask.word.byte 0x0 0.--3. 1. "LOAD_CNT,MSBs for the CHKFRQ FSM ld_val[10:0] load value 0x0 - gives a ld_val of 0 no PPM difference can be detected 0x8 - gives a load value of 1024 3000PPM resolution possible 0xA - gives a load value of 1280 2343PPM resolution possible 0xB - gives.." group.word 0x84++0x1 line.word 0x0 "SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_OVRD,MPLL override controls" newline hexmask.word.byte 0x0 10.--15. 1. "RESERVED_15_10,Reserved for Future use" newline hexmask.word.byte 0x0 5.--9. 1. "DTB_SEL,DTB select for MPLL dtb signals" newline bitfld.word 0x0 4. "FAST_MPLL_LOCK,Enable fast MPLL locking" "0,1" newline bitfld.word 0x0 3. "FAST_MPLL_PWRUP,Enable fast MPLL powerup" "0,1" newline bitfld.word 0x0 2. "MPLL_PCLK_EN,Overrides the PWR FSM mpll_pclk_en signal" "0,1" newline bitfld.word 0x0 1. "MPLL_FBDIGCLK_EN,Overrides the PWR FSM mpll_fb_dig_clk_en signal" "0,1" newline bitfld.word 0x0 0. "OVRD_SEL,Override enable bit" "0,1" rgroup.word 0x88++0x1 line.word 0x0 "SUP_DIG_MPLLA_MPLL_PWR_CTL_STAT,MPLL status register" newline bitfld.word 0x0 15. "RESERVED_15_15,Reserved for Future use" "0,1" newline bitfld.word 0x0 14. "MPLL_ANA_EN,Current value of mpll_ana_en_i" "0,1" newline bitfld.word 0x0 13. "MPLL_RST,Current value of mpll_ana_rst_i" "0,1" newline bitfld.word 0x0 12. "MPLL_CAL,Current value of mpll_ana_cal_i" "0,1" newline bitfld.word 0x0 11. "MPLL_FBCLK_EN,Current value of mpll_ana_fb_clk_en_i" "0,1" newline bitfld.word 0x0 10. "MPLL_OUTPUT_EN,Current value of mpll_ana_output_en_i" "0,1" newline bitfld.word 0x0 9. "MPLL_PCLK_EN,Current value of mpll_pclk_en" "0,1" newline bitfld.word 0x0 8. "MPLL_L_LANES,Current value of lane_mpll_l" "0,1" newline bitfld.word 0x0 7. "MPLL_R_LANES,Current value of lane_mpll_r" "0,1" newline bitfld.word 0x0 6. "MPLL_CAL_RDY,Current value of mpll_cal_rdy" "0,1" newline bitfld.word 0x0 5. "CHKFRQ_DONE,Current value of mpll_chkfrq_done" "0,1" newline bitfld.word 0x0 4. "MPLL_TOOSLOW,Current value of mpll_tooslow" "0,1" newline hexmask.word.byte 0x0 0.--3. 1. "FSM_STATE,Current value of the PWR FSM state register" group.word 0x8C++0x1 line.word 0x0 "SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_MISC_TIME_THRESHOLD,Thresholds for MPLL CAL Update timer and MPLL VCO Stabilization timer" newline rbitfld.word 0x0 13.--15. "RESERVED_15_13,Reserved for Future use" "0,1,2,3,4,5,6,7" newline hexmask.word.byte 0x0 9.--12. 1. "MPLL_CAL_UPDATE_TIME_THRESHOLD,Threshold for the MPLL calibration control word update timer in terms of number of ref_rang_clk cycles" newline hexmask.word 0x0 0.--8. 1. "VCO_STABILIZATION_TIME_THRESHOLD,Threshold for the VCO stabilization timer in terms of number of reference clock cycles Here the reference clock means the one that is fed to the phase detector of the corresponding PLL not the raw reference clock." group.word 0x90++0x1 line.word 0x0 "SUP_DIG_MPLLA_MPLL_PWR_CTL_PCLK_EN_AND_VCO_CLK_STABILIZATION_TIME_THRESHOLD,Thresholds for PCLK enable and MPLL VCO Clock Stabilization timer" newline hexmask.word.byte 0x0 11.--15. 1. "PCLK_EN_TIME_THRESHOLD,Threshold for the PCLK enable timer in terms of number of ref_range_clk cycles" newline hexmask.word 0x0 0.--10. 1. "VCO_CLK_STABILIZATION_TIME_THRESHOLD,Threshold for the VCO clock stabilization timer in terms of number of reference clock cycles Here the reference clock means the one that is fed to the phase detector of the corresponding PLL not the raw reference clock." group.word 0x94++0x1 line.word 0x0 "SUP_DIG_MPLLA_MPLL_PWR_CTL_PCLK_DIS_AND_MPLL_VCO_PWRDN_THRESHOLD,Thresholds for PCLK disable and MPLL VCO POWER DOWN timer" newline hexmask.word.byte 0x0 10.--15. 1. "RESERVED_15_10,Reserved for Future use" newline hexmask.word.byte 0x0 5.--9. 1. "MPLL_VCO_PWRDN_TIME_THRESHOLD,Threshold for the MPLL VCO power down timer in terms of number of ref_range_clk cycles" newline hexmask.word.byte 0x0 0.--4. 1. "PCLK_DIS_TIME_THRESHOLD,Threshold for the PCLK disable timer in terms of number of ref_range_clk cycles" group.word 0x98++0x1 line.word 0x0 "SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_FBCLK_EN_AND_MPLL_FBDIGCLK_DIS_AND_MPLL_ANA_PWRUP_TIME_THRESHOLD,Thresholds for MPLL feedback clock enable and MPLL feedback digital clock disable and MPLL ANA POWER UP timer" newline rbitfld.word 0x0 15. "RESERVED_15_15,Reserved for Future use" "0,1" newline hexmask.word.byte 0x0 8.--14. 1. "MPLL_ANA_PWRUP_TIME_THRESHOLD,Threshold for the MPLL analog power up timer in terms of number of ref_range_clk cycles" newline hexmask.word.byte 0x0 4.--7. 1. "MPLL_FBDIGCLK_DIS_TIME_THRESHOLD,Threshold for the MPLL feedback digital clock disable timer in terms of number of ref_range_clk cycles" newline hexmask.word.byte 0x0 0.--3. 1. "MPLL_FBCLK_EN_TIME_THRESHOLD,Threshold for the MPLL feedback clock enable timer in terms of number of ref_range_clk cycles" rgroup.word 0x9C++0x1 line.word 0x0 "SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_COARSE_TUNE_VAL,MPLL coarse_tune value register" newline hexmask.word.byte 0x0 8.--15. 1. "RESERVED_15_8,Reserved for Future use" newline hexmask.word.byte 0x0 0.--7. 1. "MPLL_COARSE_TUNE_VAL,Current value of mpll_ana_coarse_tune_i" rgroup.word 0xA0++0x1 line.word 0x0 "SUP_DIG_MPLLA_MPLL_PWR_CTL_MPLL_SKIPCAL_COARSE_TUNE,Value for MPLL coarse_tune when skipping calibration" newline hexmask.word.byte 0x0 8.--15. 1. "RESERVED_15_8,Reserved for Future use" newline hexmask.word.byte 0x0 0.--7. 1. "MPLL_SKIPCAL_COARSE_TUNE,Value for MPLL coarse_tune when calibration is skipped" group.word 0xA4++0x1 line.word 0x0 "SUP_DIG_MPLLA_SSC_SS_PHASE,Current MPLL phase selector value" newline hexmask.word.byte 0x0 12.--15. 1. "RESERVED_15_12,Reserved for Future use" newline bitfld.word 0x0 11. "ZERO_FREQ,Zero frequency register. NOTES: Must be set for PHASE writes to stick (2 reads needed to read value)" "0,1" newline hexmask.word 0x0 2.--10. 1. "VAL,Phase value from zero reference (2 reads needed to read value)" newline bitfld.word 0x0 0.--1. "DTHR,Bits below the useful resolution (2 reads needed to read value)" "0,1,2,3" group.word 0xA8++0x1 line.word 0x0 "SUP_DIG_MPLLA_SSC_SS_FREQ_0,Frequency Control for Spread Spectrum #0" newline rbitfld.word 0x0 13.--15. "RESERVED_15_13,Reserved for Future use" "0,1,2,3,4,5,6,7" newline bitfld.word 0x0 12. "FREQ_0_OVRD,Frequency Reigster Override. NOTE: Must be set for PHASE writes to stick" "0,1" newline hexmask.word 0x0 0.--11. 1. "FREQ_CNT_INIT,Initial Frequency Counter Value" group.word 0xAC++0x1 line.word 0x0 "SUP_DIG_MPLLA_SSC_SS_FREQ_1,Frequency Control for Spread Spectrum #1" newline hexmask.word.byte 0x0 9.--15. 1. "RESERVED_15_9,Reserved for Future use" newline bitfld.word 0x0 8. "FREQ_1_OVRD,Frequency Reigster Override. NOTE: Must be set for PHASE writes to stick" "0,1" newline hexmask.word.byte 0x0 0.--7. 1. "FREQ_PK,Peak Frequency Value (for changing direction)" group.word 0xB0++0x1 line.word 0x0 "SUP_DIG_MPLLB_MPLL_PWR_CTL_CAL_CTRL,MPLL Calibration controls" newline bitfld.word 0x0 15. "EXT_CAL_DONE,Set the external calibration status to done" "0,1" newline hexmask.word.byte 0x0 7.--14. 1. "EXT_COARSE_TUNE,Value of mpll_ana_coarse_tune_i[7:0] in external calibration mode" newline bitfld.word 0x0 6. "EXT_CHKFRQ_EN,Check the frequency of the MPLL Only valid in external calibration mode" "0,1" newline bitfld.word 0x0 5. "MPLL_EXTCAL,Enable external calibration of MPLL" "0,1" newline bitfld.word 0x0 4. "MPLL_SKIPCAL,Skip automatic (internal) calibration of MPLL (and also skip external calibration if it is enabled) If skipcal is enabled then MPLL_SKIPCAL_COARSE_TUNE is used." "0,1" newline hexmask.word.byte 0x0 0.--3. 1. "LOAD_CNT,MSBs for the CHKFRQ FSM ld_val[10:0] load value 0x0 - gives a ld_val of 0 no PPM difference can be detected 0x8 - gives a load value of 1024 3000PPM resolution possible 0xA - gives a load value of 1280 2343PPM resolution possible 0xB - gives.." group.word 0xB4++0x1 line.word 0x0 "SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_OVRD,MPLL override controls" newline hexmask.word.byte 0x0 10.--15. 1. "RESERVED_15_10,Reserved for Future use" newline hexmask.word.byte 0x0 5.--9. 1. "DTB_SEL,DTB select for MPLL dtb signals" newline bitfld.word 0x0 4. "FAST_MPLL_LOCK,Enable fast MPLL locking" "0,1" newline bitfld.word 0x0 3. "FAST_MPLL_PWRUP,Enable fast MPLL powerup" "0,1" newline bitfld.word 0x0 2. "MPLL_PCLK_EN,Overrides the PWR FSM mpll_pclk_en signal" "0,1" newline bitfld.word 0x0 1. "MPLL_FBDIGCLK_EN,Overrides the PWR FSM mpll_fb_dig_clk_en signal" "0,1" newline bitfld.word 0x0 0. "OVRD_SEL,Override enable bit" "0,1" rgroup.word 0xB8++0x1 line.word 0x0 "SUP_DIG_MPLLB_MPLL_PWR_CTL_STAT,MPLL status register" newline bitfld.word 0x0 15. "RESERVED_15_15,Reserved for Future use" "0,1" newline bitfld.word 0x0 14. "MPLL_ANA_EN,Current value of mpll_ana_en_i" "0,1" newline bitfld.word 0x0 13. "MPLL_RST,Current value of mpll_ana_rst_i" "0,1" newline bitfld.word 0x0 12. "MPLL_CAL,Current value of mpll_ana_cal_i" "0,1" newline bitfld.word 0x0 11. "MPLL_FBCLK_EN,Current value of mpll_ana_fb_clk_en_i" "0,1" newline bitfld.word 0x0 10. "MPLL_OUTPUT_EN,Current value of mpll_ana_output_en_i" "0,1" newline bitfld.word 0x0 9. "MPLL_PCLK_EN,Current value of mpll_pclk_en" "0,1" newline bitfld.word 0x0 8. "MPLL_L_LANES,Current value of lane_mpll_l" "0,1" newline bitfld.word 0x0 7. "MPLL_R_LANES,Current value of lane_mpll_r" "0,1" newline bitfld.word 0x0 6. "MPLL_CAL_RDY,Current value of mpll_cal_rdy" "0,1" newline bitfld.word 0x0 5. "CHKFRQ_DONE,Current value of mpll_chkfrq_done" "0,1" newline bitfld.word 0x0 4. "MPLL_TOOSLOW,Current value of mpll_tooslow" "0,1" newline hexmask.word.byte 0x0 0.--3. 1. "FSM_STATE,Current value of the PWR FSM state register" group.word 0xBC++0x1 line.word 0x0 "SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_MISC_TIME_THRESHOLD,Thresholds for MPLL CAL Update timer and MPLL VCO Stabilization timer" newline rbitfld.word 0x0 13.--15. "RESERVED_15_13,Reserved for Future use" "0,1,2,3,4,5,6,7" newline hexmask.word.byte 0x0 9.--12. 1. "MPLL_CAL_UPDATE_TIME_THRESHOLD,Threshold for the MPLL calibration control word update timer in terms of number of ref_rang_clk cycles" newline hexmask.word 0x0 0.--8. 1. "VCO_STABILIZATION_TIME_THRESHOLD,Threshold for the VCO stabilization timer in terms of number of reference clock cycles Here the reference clock means the one that is fed to the phase detector of the corresponding PLL not the raw reference clock." group.word 0xC0++0x1 line.word 0x0 "SUP_DIG_MPLLB_MPLL_PWR_CTL_PCLK_EN_AND_VCO_CLK_STABILIZATION_TIME_THRESHOLD,Thresholds for PCLK enable and MPLL VCO Clock Stabilization timer" newline hexmask.word.byte 0x0 11.--15. 1. "PCLK_EN_TIME_THRESHOLD,Threshold for the PCLK enable timer in terms of number of ref_range_clk cycles" newline hexmask.word 0x0 0.--10. 1. "VCO_CLK_STABILIZATION_TIME_THRESHOLD,Threshold for the VCO clock stabilization timer in terms of number of reference clock cycles Here the reference clock means the one that is fed to the phase detector of the corresponding PLL not the raw reference clock." group.word 0xC4++0x1 line.word 0x0 "SUP_DIG_MPLLB_MPLL_PWR_CTL_PCLK_DIS_AND_MPLL_VCO_PWRDN_THRESHOLD,Thresholds for PCLK disable and MPLL VCO POWER DOWN timer" newline hexmask.word.byte 0x0 10.--15. 1. "RESERVED_15_10,Reserved for Future use" newline hexmask.word.byte 0x0 5.--9. 1. "MPLL_VCO_PWRDN_TIME_THRESHOLD,Threshold for the MPLL VCO power down timer in terms of number of ref_range_clk cycles" newline hexmask.word.byte 0x0 0.--4. 1. "PCLK_DIS_TIME_THRESHOLD,Threshold for the PCLK disable timer in terms of number of ref_range_clk cycles" group.word 0xC8++0x1 line.word 0x0 "SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_FBCLK_EN_AND_MPLL_FBDIGCLK_DIS_AND_MPLL_ANA_PWRUP_TIME_THRESHOLD,Thresholds for MPLL feedback clock enable and MPLL feedback digital clock disable and MPLL ANA POWER UP timer" newline rbitfld.word 0x0 15. "RESERVED_15_15,Reserved for Future use" "0,1" newline hexmask.word.byte 0x0 8.--14. 1. "MPLL_ANA_PWRUP_TIME_THRESHOLD,Threshold for the MPLL analog power up timer in terms of number of ref_range_clk cycles" newline hexmask.word.byte 0x0 4.--7. 1. "MPLL_FBDIGCLK_DIS_TIME_THRESHOLD,Threshold for the MPLL feedback digital clock disable timer in terms of number of ref_range_clk cycles" newline hexmask.word.byte 0x0 0.--3. 1. "MPLL_FBCLK_EN_TIME_THRESHOLD,Threshold for the MPLL feedback clock enable timer in terms of number of ref_range_clk cycles" rgroup.word 0xCC++0x1 line.word 0x0 "SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_COARSE_TUNE_VAL,MPLL coarse_tune value register" newline hexmask.word.byte 0x0 8.--15. 1. "RESERVED_15_8,Reserved for Future use" newline hexmask.word.byte 0x0 0.--7. 1. "MPLL_COARSE_TUNE_VAL,Current value of mpll_ana_coarse_tune_i" rgroup.word 0xD0++0x1 line.word 0x0 "SUP_DIG_MPLLB_MPLL_PWR_CTL_MPLL_SKIPCAL_COARSE_TUNE,Value for MPLL coarse_tune when skipping calibration" newline hexmask.word.byte 0x0 8.--15. 1. "RESERVED_15_8,Reserved for Future use" newline hexmask.word.byte 0x0 0.--7. 1. "MPLL_SKIPCAL_COARSE_TUNE,Value for MPLL coarse_tune when calibration is skipped" group.word 0xD4++0x1 line.word 0x0 "SUP_DIG_MPLLB_SSC_SS_PHASE,Current MPLL phase selector value" newline hexmask.word.byte 0x0 12.--15. 1. "RESERVED_15_12,Reserved for Future use" newline bitfld.word 0x0 11. "ZERO_FREQ,Zero frequency register. NOTES: Must be set for PHASE writes to stick (2 reads needed to read value)" "0,1" newline hexmask.word 0x0 2.--10. 1. "VAL,Phase value from zero reference (2 reads needed to read value)" newline bitfld.word 0x0 0.--1. "DTHR,Bits below the useful resolution (2 reads needed to read value)" "0,1,2,3" group.word 0xD8++0x1 line.word 0x0 "SUP_DIG_MPLLB_SSC_SS_FREQ_0,Frequency Control for Spread Spectrum #0" newline rbitfld.word 0x0 13.--15. "RESERVED_15_13,Reserved for Future use" "0,1,2,3,4,5,6,7" newline bitfld.word 0x0 12. "FREQ_0_OVRD,Frequency Reigster Override. NOTE: Must be set for PHASE writes to stick" "0,1" newline hexmask.word 0x0 0.--11. 1. "FREQ_CNT_INIT,Initial Frequency Counter Value" group.word 0xDC++0x1 line.word 0x0 "SUP_DIG_MPLLB_SSC_SS_FREQ_1,Frequency Control for Spread Spectrum #1" newline hexmask.word.byte 0x0 9.--15. 1. "RESERVED_15_9,Reserved for Future use" newline bitfld.word 0x0 8. "FREQ_1_OVRD,Frequency Reigster Override. NOTE: Must be set for PHASE writes to stick" "0,1" newline hexmask.word.byte 0x0 0.--7. 1. "FREQ_PK,Peak Frequency Value (for changing direction)" group.word 0xE0++0x1 line.word 0x0 "SUP_DIG_CLK_RST_BG_PWRUP_TIME_0,BG Power UP Time Register #0" newline hexmask.word.byte 0x0 10.--15. 1. "RESERVED_15_10,Reserved for Future use" newline bitfld.word 0x0 9. "FAST_BG_WAIT,Enable fast BG times (simulation only)" "0,1" newline hexmask.word 0x0 0.--8. 1. "BG_SUP_EN_TIME,Power up time (in ref_range cycles) for bandgap in SUP (spec >=5us)" group.word 0xE4++0x1 line.word 0x0 "SUP_DIG_CLK_RST_BG_PWRUP_TIME_1,BG Power UP Time Register #1" newline hexmask.word.byte 0x0 10.--15. 1. "RESERVED_15_10,Reserved for Future use" newline hexmask.word 0x0 0.--9. 1. "BG_LANE_EN_TIME,Power up time (in ref_range cycles) for bandgap in LANE (spec >= 20us)" group.word 0x100++0x1 line.word 0x0 "SUP_ANA_MPLLA_MISC,MPLLA_MISC" newline hexmask.word.byte 0x0 8.--15. 1. "RESERVED_15_8,Reserved for Future use" newline hexmask.word.byte 0x0 4.--7. 1. "NC7_4,Reserved" newline bitfld.word 0x0 3. "PR_BYPASS,If ovrd_pr_bypass is enabled: PR_BYPASS Function 1 stops SSC and disables PMIX 0 enables SSC and PMIX" "0,1" newline bitfld.word 0x0 2. "MODE_OLD_SSC,Uses just two bits for SSC interpolation" "0,1" newline bitfld.word 0x0 1. "OVRD_PR_BYPASS,If asserted pr_bypass take effect on phase rotator bypass control" "0,1" newline bitfld.word 0x0 0. "BYPASS_BUF,To bypass CP buffers." "0,1" group.word 0x104++0x1 line.word 0x0 "SUP_ANA_MPLLA_OVRD,MPLLA_OVRD" newline hexmask.word.byte 0x0 8.--15. 1. "RESERVED_15_8,Reserved for Future use" newline bitfld.word 0x0 7. "RESET_REG,set local reset control to ON" "0,1" newline bitfld.word 0x0 6. "OVRD_RESET,enable local control of reset signal (mpll_rst)" "0,1" newline bitfld.word 0x0 5. "FB_CLK_EN_REG,set local feedback clock control to ON" "0,1" newline bitfld.word 0x0 4. "OVRD_FB_CLK_EN,enable local control of feedback clock control signal (mpll_fb_clk_en)" "0,1" newline bitfld.word 0x0 3. "CAL_REG,set local calibration control to ON" "0,1" newline bitfld.word 0x0 2. "OVRD_CAL,enable local control of calibration signal (mpll_cal)" "0,1" newline bitfld.word 0x0 1. "ENABLE_REG,set local enable control to ON" "0,1" newline bitfld.word 0x0 0. "OVRD_ENABLE,enable local control of enable signal (mpll_en)" "0,1" repeat 3. (list 0x1 0x2 0x3 )(list 0x0 0x4 0x8 ) group.word ($2+0x108)++0x1 line.word 0x0 "SUP_ANA_MPLLA_ATB$1,MPLLA_ATB1" newline hexmask.word.byte 0x0 8.--15. 1. "RESERVED_15_8,Reserved for Future use" newline bitfld.word 0x0 7. "MEAS_VREG_L,Measure vreg_left (atb_s_p)" "0,1" newline bitfld.word 0x0 6. "MEAS_VREG_S,Measure vreg_s in MPLL voltage regulator (atb_s_p)" "0,1" newline bitfld.word 0x0 5. "MEAS_VREG_VCO,Measure vreg_vco (atb_s_p)" "0,1" newline bitfld.word 0x0 4. "OVERRIDE_VREG_CP,Override vreg_cp to be 4/3X of voltage on atb_s_m." "0,1" newline bitfld.word 0x0 3. "OVERRIDE_VREG_VP,Override vreg_vp to be 4/3X of voltage on atb_s_m" "0,1" newline bitfld.word 0x0 2. "OVERRIDE_VREG_LEFT,Override vreg_left to be 4/3X of voltage on atb_s_m" "0,1" newline bitfld.word 0x0 1. "OVERRIDE_VREG_RIGHT,Override vreg_right to be 4/3X of voltage on atb_s_m" "0,1" newline bitfld.word 0x0 0. "OVERRIDE_VREG_VCO,Override vreg_vco to be 4/3X of voltage on atb_s_m" "0,1" repeat.end group.word 0x114++0x1 line.word 0x0 "SUP_ANA_MPLLB_MISC,MPLLB_MISC" newline hexmask.word.byte 0x0 8.--15. 1. "RESERVED_15_8,Reserved for Future use" newline hexmask.word.byte 0x0 4.--7. 1. "NC7_4,Reserved" newline bitfld.word 0x0 3. "PR_BYPASS,If ovrd_pr_bypass is enabled: PR_BYPASS Function 1 stops SSC and disables PMIX 0 enables SSC and PMIX" "0,1" newline bitfld.word 0x0 2. "MODE_OLD_SSC,Uses just two bits for SSC interpolation" "0,1" newline bitfld.word 0x0 1. "OVRD_PR_BYPASS,If asserted pr_bypass take effect on phase rotator bypass control" "0,1" newline bitfld.word 0x0 0. "BYPASS_BUF,To bypass CP buffers." "0,1" group.word 0x118++0x1 line.word 0x0 "SUP_ANA_MPLLB_OVRD,MPLLB_OVRD" newline hexmask.word.byte 0x0 8.--15. 1. "RESERVED_15_8,Reserved for Future use" newline bitfld.word 0x0 7. "RESET_REG,set local reset control to ON" "0,1" newline bitfld.word 0x0 6. "OVRD_RESET,enable local control of reset signal (mpll_rst)" "0,1" newline bitfld.word 0x0 5. "FB_CLK_EN_REG,set local feedback clock control to ON" "0,1" newline bitfld.word 0x0 4. "OVRD_FB_CLK_EN,enable local control of feedback clock control signal (mpll_fb_clk_en)" "0,1" newline bitfld.word 0x0 3. "CAL_REG,set local calibration control to ON" "0,1" newline bitfld.word 0x0 2. "OVRD_CAL,enable local control of calibration signal (mpll_cal)" "0,1" newline bitfld.word 0x0 1. "ENABLE_REG,set local enable control to ON" "0,1" newline bitfld.word 0x0 0. "OVRD_ENABLE,enable local control of enable signal (mpll_en)" "0,1" repeat 3. (list 0x1 0x2 0x3 )(list 0x0 0x4 0x8 ) group.word ($2+0x11C)++0x1 line.word 0x0 "SUP_ANA_MPLLB_ATB$1,MPLLB_ATB1" newline hexmask.word.byte 0x0 8.--15. 1. "RESERVED_15_8,Reserved for Future use" newline bitfld.word 0x0 7. "MEAS_VREG_L,Measure vreg_left (atb_s_p)" "0,1" newline bitfld.word 0x0 6. "MEAS_VREG_S,Measure vreg_s in MPLL voltage regulator (atb_s_p)" "0,1" newline bitfld.word 0x0 5. "MEAS_VREG_VCO,Measure vreg_vco (atb_s_p)" "0,1" newline bitfld.word 0x0 4. "OVERRIDE_VREG_CP,Override vreg_cp to be 4/3X of voltage on atb_s_m." "0,1" newline bitfld.word 0x0 3. "OVERRIDE_VREG_VP,Override vreg_vp to be 4/3X of voltage on atb_s_m" "0,1" newline bitfld.word 0x0 2. "OVERRIDE_VREG_LEFT,Override vreg_left to be 4/3X of voltage on atb_s_m" "0,1" newline bitfld.word 0x0 1. "OVERRIDE_VREG_RIGHT,Override vreg_right to be 4/3X of voltage on atb_s_m" "0,1" newline bitfld.word 0x0 0. "OVERRIDE_VREG_VCO,Override vreg_vco to be 4/3X of voltage on atb_s_m" "0,1" repeat.end group.word 0x128++0x1 line.word 0x0 "SUP_ANA_RTUNE_CTRL,RTUNE_CTRL" newline hexmask.word.byte 0x0 8.--15. 1. "RESERVED_15_8,Reserved for Future use" newline bitfld.word 0x0 7. "RT_EN_FRCON,Local rtune block enable control force rtune block on if asserted" "0,1" newline bitfld.word 0x0 6. "NC6,Reserved" "0,1" newline bitfld.word 0x0 4.--5. "RT_DAC_MODE,Margin DAC mode control bits." "0,1,2,3" newline bitfld.word 0x0 3. "RT_DAC_CHOP,[RT_DAC_CHOP RT_DAC_MODE] Function 00 Margin DAC power down 01 Margin DAC single ended output drives atb_s_m 10 Margin DAC power down 11 Margin DAC single ended output drives atb_s_p" "0,1" newline bitfld.word 0x0 2. "RT_ATB,RTUNE ATB mode control. Combines with rt_ana_mode[1:0] to perform different functions." "0,1" newline bitfld.word 0x0 1. "RT_SEL_ATBP,RTUNE ATB input select: RT_SEL_ATBP Function 1 select atb_s_p 0 select atb_s_m" "0,1" newline bitfld.word 0x0 0. "RT_SEL_ATBF,RTUNE ATB input select: RT_SEL_ATBF Function 1 select gd as input 0 select atb_s_p/m as input" "0,1" group.word 0x12C++0x1 line.word 0x0 "SUP_ANA_SWITCH_PWR_MEAS,SWITCH_PWR_MEAS" newline hexmask.word.byte 0x0 8.--15. 1. "RESERVED_15_8,Reserved for Future use" newline bitfld.word 0x0 7. "NC7,Reserved" "0,1" newline bitfld.word 0x0 6. "ATB_SW,Connect atb_s_p to atb_s_m if asserted" "0,1" newline bitfld.word 0x0 5. "ATB_SW_HALF_VPH,Connect atb_s_p to vph/2 if asserted. In this mode bit 1 should be 0." "0,1" newline bitfld.word 0x0 4. "ATB_SW_GD,Connect atb_s_m to gd if asserted" "0,1" newline bitfld.word 0x0 3. "ATB_SW_VP,Connect atb_s_p to vp if asserted" "0,1" newline bitfld.word 0x0 2. "ATB_SW_VBG_VREF,Connect vbg_vref to atb_s_p if asserted" "0,1" newline bitfld.word 0x0 1. "ATB_SW_VPH,Connect atb_s_p to vph if bit 5 is asserted Connect atb_s_p to vph/2 if bit 5 is asserted (not recommended)" "0,1" newline bitfld.word 0x0 0. "ATB_SW_VBG_BIAS_REF,Connect vbg_bias_ref to atb_s_p If asserted" "0,1" group.word 0x130++0x1 line.word 0x0 "SUP_ANA_SWITCH_MISC_MEAS,SWITCH_MISC_MEAS" newline hexmask.word.byte 0x0 8.--15. 1. "RESERVED_15_8,Reserved for Future use" newline bitfld.word 0x0 6.--7. "NC7_6,Reserved" "0,1,2,3" newline bitfld.word 0x0 5. "TEMP_MEAS,If asserted enable temperature measurement. Vbe is sent to atb_s_m vbg is sent to atb_s_p." "0,1" newline bitfld.word 0x0 4. "NC4,Reserved" "0,1" newline bitfld.word 0x0 2.--3. "SEL_VPLL_REF,Select the reference voltage for the MPLL 00 vpll_ref = 707mV 01 vpll_ref = 731mV 10 vpll_ref = 756mV (default) 11 vpll_ref = 780mV" "0,1,2,3" newline bitfld.word 0x0 0.--1. "HYST_REF,Function 00 No hysteresis 01 18mVpp hysteresis 10 35mVpp hysteresis (default) 11 50mVpp hysteresis" "0,1,2,3" group.word 0x134++0x1 line.word 0x0 "SUP_ANA_BG,BG" newline hexmask.word.byte 0x0 8.--15. 1. "RESERVED_15_8,Reserved for Future use" newline bitfld.word 0x0 5.--7. "NC7_5,Reserved" "0,1,2,3,4,5,6,7" newline bitfld.word 0x0 4. "POR_START_KICK_EN,Enable fast startup using bg kick voltage for POR bandgap outputs" "0,1" newline bitfld.word 0x0 3. "CHOP_EN,Enable chopper clock for bandgap" "0,1" newline bitfld.word 0x0 1.--2. "SEL_VBG_VREF,vbg_vref voltage level select 00 vbg_vref = 658mV 01 vbg_vref = 683mV 10 vbg_vref = 707mV (default) 11 vbg_vref = 731mV" "0,1,2,3" newline bitfld.word 0x0 0. "BYPASS_BG,Bypass bandgap with VP" "0,1" group.word 0x138++0x1 line.word 0x0 "SUP_ANA_PRESCALER_CTRL,PRESCALER_CTRL" newline hexmask.word.byte 0x0 8.--15. 1. "RESERVED_15_8,Reserved for Future use" newline hexmask.word.byte 0x0 3.--7. 1. "NC7_3,Reserved" newline bitfld.word 0x0 2. "ATB_SELECT,Connect internal ATB_S signals to external ATB_S signals" "0,1" newline bitfld.word 0x0 1. "NC1,Reserved" "0,1" newline bitfld.word 0x0 0. "MEAS_VREG,If asserted measure sup_prescaler regulator output voltage (vp_lcl) through atb_s_p" "0,1" group.word 0x180++0x1 line.word 0x0 "SUP_DIG_RTUNE_DEBUG,Resistor tuning debug controls" newline bitfld.word 0x0 15. "TXUP_GO,Enable TxUP tune to continue in manual tune mode when TYPE is TxUP tune. When in non TxUP manual tune mode this bit must be 0. When in TxUP manual tune mode and after TxUP manual tune is triggered if the read only register.." "0,1" newline hexmask.word 0x0 5.--14. 1. "VALUE,Value to use when triggering SET_VAL field only the 6 LSB's are used when setting rx cal values" newline bitfld.word 0x0 3.--4. "TYPE,Type of manual tuning or register read/write to execute 0 - ADC or read/write rt_value 1 - Rx tune or read/write rx_cal_val (only 6 bits) 2 - TxDN tune or read/write txdn_cal_val (10 bits) 3 - TxUP tune or read/write txup_cal_val (10 bits) or.." "ADC,Rx tune,TxDN tune,TxUP tune" newline bitfld.word 0x0 2. "SET_VAL,Set value Write to a 1 to manually write the register specified by the TYPE field to the value in the VALUE field" "0,1" newline bitfld.word 0x0 1. "MAN_TUNE,Write to a 1 to do a manual tuning specified by TYPE field starting a manual tune while a tune is currently running can cause unpredictable results. For use only when you know what the part is doing (w.r.t. resistor tuning)" "0,1" newline bitfld.word 0x0 0. "FLIP_COMP,Invert analog comparator output" "0,1" group.word 0x184++0x1 line.word 0x0 "SUP_DIG_RTUNE_CONFIG,Configure Rtune Operation" newline hexmask.word 0x0 6.--15. 1. "RESERVED_15_6,Reserved for Future use" newline bitfld.word 0x0 3.--5. "SUP_ANA_TERM_CTRL,Set the reference resistor in the analog Value Impedence (Ohms) 000 54 001 52 010 50 (default) 011 48 100 46 101 44 110 42 111 40" "0,1,2,3,4,5,6,7" newline bitfld.word 0x0 2. "TX_CAL_EN,Enable calibration of TX resistor" "0,1" newline bitfld.word 0x0 1. "FAST_RTUNE,Enable fast resitor tuning (simulation only)" "0,1" newline bitfld.word 0x0 0. "RX_CAL_EN,Enable calibration of RX resistor" "0,1" rgroup.word 0x188++0x1 line.word 0x0 "SUP_DIG_RTUNE_STAT,Resistor tuning register status" newline hexmask.word.byte 0x0 12.--15. 1. "RESERVED_15_12,Reserved for Future use" newline bitfld.word 0x0 10.--11. "DTB_RTUNE,DTB sampling for rtune" "0,1,2,3" newline hexmask.word 0x0 0.--9. 1. "STAT,Current value of the register specifed by the DEBUG.TYPE field" group.word 0x18C++0x1 line.word 0x0 "SUP_DIG_RTUNE_RX_SET_VAL,Set value of RX Resistor" newline hexmask.word 0x0 6.--15. 1. "RESERVED_15_6,Reserved for Future use" newline hexmask.word.byte 0x0 0.--5. 1. "RX_SET_VAL,Set value of rx resistor Writing a value to this register will set the rx resistor value." group.word 0x190++0x1 line.word 0x0 "SUP_DIG_RTUNE_TXDN_SET_VAL,Set value of TX-DN Resistor" newline hexmask.word.byte 0x0 10.--15. 1. "RESERVED_15_10,Reserved for Future use" newline hexmask.word 0x0 0.--9. 1. "TXDN_SET_VAL,Set value of tx-dn resistor Writing a value to this register will set the tx-dn resistor value." group.word 0x194++0x1 line.word 0x0 "SUP_DIG_RTUNE_TXUP_SET_VAL,Set value of TX-UP Resistor" newline hexmask.word.byte 0x0 10.--15. 1. "RESERVED_15_10,Reserved for Future use" newline hexmask.word 0x0 0.--9. 1. "TXUP_SET_VAL,Set value of tx-up resistor Writing a value to this register will set the tx-up resistor value." rgroup.word 0x198++0x1 line.word 0x0 "SUP_DIG_RTUNE_RX_STAT,RX Resistor tuning register status" newline hexmask.word 0x0 6.--15. 1. "RESERVED_15_6,Reserved for Future use" newline hexmask.word.byte 0x0 0.--5. 1. "RX_STAT,Current value of the rx resistor tuning register" rgroup.word 0x19C++0x1 line.word 0x0 "SUP_DIG_RTUNE_TXDN_STAT,TX-DN Resistor tuning register status" newline hexmask.word.byte 0x0 10.--15. 1. "RESERVED_15_10,Reserved for Future use" newline hexmask.word 0x0 0.--9. 1. "TXDN_STAT,Current value of the tx-dn resistor tuning register" rgroup.word 0x1A0++0x1 line.word 0x0 "SUP_DIG_RTUNE_TXUP_STAT,TX-UP Resistor tuning register status" newline hexmask.word.byte 0x0 10.--15. 1. "RESERVED_15_10,Reserved for Future use" newline hexmask.word 0x0 0.--9. 1. "TXUP_STAT,Current value of the tx-up resistor tuning register" group.word 0x1A4++0x1 line.word 0x0 "SUP_DIG_ANA_MPLLA_OVRD_OUT,Override value for mplla signals going to ANA" newline rbitfld.word 0x0 15. "RESERVED_15_15,Reserved for Future use" "0,1" newline bitfld.word 0x0 14. "OVRD_SEL,Override bit for mplla_ana outputs" "0,1" newline bitfld.word 0x0 13. "MPLLA_DIV_CLK_EN,Overrides the mplla_ana_div_clk_en signal" "0,1" newline hexmask.word.byte 0x0 9.--12. 1. "RESERVED," newline bitfld.word 0x0 8. "MPLLA_FBCLK_EN,Overrides the mplla_fb_clk_en signal" "0,1" newline bitfld.word 0x0 7. "MPLLA_DIV10_CLK_EN,Overrides the mplla_ana_div10_clk_en signal" "0,1" newline bitfld.word 0x0 6. "MPLLA_DIV8_CLK_EN,Overrides the mplla_ana_div8_clk_en signal" "0,1" newline bitfld.word 0x0 5. "MPLLA_OUTPUT_R_EN,Overrides the mplla_ana_output_r_en signal" "0,1" newline bitfld.word 0x0 4. "MPLLA_OUTPUT_L_EN,Overrides the mplla_ana_output_l_en signal" "0,1" newline bitfld.word 0x0 3. "MPLLA_OUTPUT_EN,Overrides the mplla_ana_output_en signal" "0,1" newline bitfld.word 0x0 2. "MPLLA_CAL,Overrides the mplla_ana_cal signal" "0,1" newline bitfld.word 0x0 1. "MPLLA_RST,Overrides the mplla_ana_rst signal" "0,1" newline bitfld.word 0x0 0. "MPLLA_ANA_EN,Overrides the mplla_ana_en signal" "0,1" group.word 0x1A8++0x1 line.word 0x0 "SUP_DIG_ANA_MPLLB_OVRD_OUT,Override value for mpllb signals going to ANA" newline rbitfld.word 0x0 15. "RESERVED_15_15,Reserved for Future use" "0,1" newline bitfld.word 0x0 14. "OVRD_SEL,Override bit for mpllb_ana outputs" "0,1" newline bitfld.word 0x0 13. "MPLLB_DIV_CLK_EN,Overrides the mpllb_ana_div_clk_en signal" "0,1" newline hexmask.word.byte 0x0 9.--12. 1. "RESERVED," newline bitfld.word 0x0 8. "MPLLB_FBCLK_EN,Overrides the mpllb_fb_clk_en signal" "0,1" newline bitfld.word 0x0 7. "MPLLB_DIV10_CLK_EN,Overrides the mpllb_ana_div10_clk_en signal" "0,1" newline bitfld.word 0x0 6. "MPLLB_DIV8_CLK_EN,Overrides the mpllb_ana_div8_clk_en signal" "0,1" newline bitfld.word 0x0 5. "MPLLB_OUTPUT_R_EN,Overrides the mpllb_ana_output_r_en signal" "0,1" newline bitfld.word 0x0 4. "MPLLB_OUTPUT_L_EN,Overrides the mpllb_ana_output_l_en signal" "0,1" newline bitfld.word 0x0 3. "MPLLB_OUTPUT_EN,Overrides the mpllb_ana_output_en signal" "0,1" newline bitfld.word 0x0 2. "MPLLB_CAL,Overrides the mpllb_ana_cal signal" "0,1" newline bitfld.word 0x0 1. "MPLLB_RST,Overrides the mpllb_ana_rst signal" "0,1" newline bitfld.word 0x0 0. "MPLLB_ANA_EN,Overrides the mpllb_ana_en signal" "0,1" group.word 0x1AC++0x1 line.word 0x0 "SUP_DIG_ANA_RTUNE_OVRD_OUT,Override value for RTUNE signals going to ANA" newline rbitfld.word 0x0 15. "RESERVED_15_15,Reserved for Future use" "0,1" newline bitfld.word 0x0 14. "RTUNE_OVRD_EN,Override bit for rtune (rt_ana_* and term) outputs" "0,1" newline hexmask.word 0x0 4.--13. 1. "RTUNE_VALUE,Overrides the rt_ana_value[9:0] signal" newline bitfld.word 0x0 3. "RTUNE_EN,Overrides the rt_ana_en signal" "0,1" newline bitfld.word 0x0 1.--2. "RTUNE_MODE,Overrides the rt_ana_mode[1:0] signal" "0,1,2,3" newline bitfld.word 0x0 0. "RTUNE_COMP_RST,Overrides the rt_ana_comp_rst signal" "0,1" rgroup.word 0x1B0++0x1 line.word 0x0 "SUP_DIG_ANA_STAT,SUP input status register for SUP ANA outputs" newline hexmask.word 0x0 1.--15. 1. "RESERVED_15_1,Reserved for Future use" newline bitfld.word 0x0 0. "RT_ANA_COMP_RESULT,Value from ANA for rt_ana_comp_result" "0,1" group.word 0x1B4++0x1 line.word 0x0 "SUP_DIG_ANA_ANA_OVRD_OUT,Override values for ana_async_rst and bandgap signals going to ANA" newline hexmask.word 0x0 5.--15. 1. "RESERVED_15_5,Reserved for Future use" newline bitfld.word 0x0 4. "ANA_ASYNC_RST_OVRD_EN,Override enable for ana_async_rst" "0,1" newline bitfld.word 0x0 3. "ANA_ASYNC_RST,Override value for reset register for analog latches" "0,1" newline bitfld.word 0x0 2. "BG_OVRD_EN,Override bit for bandgap outputs" "0,1" newline bitfld.word 0x0 1. "BG_EN,Overrides the bg_ana_en signal" "0,1" newline bitfld.word 0x0 0. "BG_FAST_START,Overrides the bg_ana_fast_start signal" "0,1" group.word 0x1B8++0x1 line.word 0x0 "SUP_DIG_ANA_MPLLA_PMIX_OVRD_OUT,Override value for mplla pmix signals going to ANA" newline hexmask.word.byte 0x0 11.--15. 1. "RESERVED_15_11,Reserved for Future use" newline bitfld.word 0x0 10. "MPLLA_PMIX_EN_OVRD_EN,Override bit for mplla_ana_pmix_en signal" "0,1" newline bitfld.word 0x0 9. "MPLLA_PMIX_SEL_OVRD_EN,Override bit for mplla_ana_pmix_sel signal" "0,1" newline bitfld.word 0x0 8. "MPLLA_PMIX_EN,Override bit for mplla_ana_pmix_en signal" "0,1" newline hexmask.word.byte 0x0 0.--7. 1. "MPLLA_PMIX_SEL,Overrides the mplla_ana_pmix_sel signal" group.word 0x1BC++0x1 line.word 0x0 "SUP_DIG_ANA_MPLLB_PMIX_OVRD_OUT,Override value for mpllb pmix signals going to ANA" newline hexmask.word.byte 0x0 11.--15. 1. "RESERVED_15_11,Reserved for Future use" newline bitfld.word 0x0 10. "MPLLB_PMIX_EN_OVRD_EN,Override bit for mpllb_ana_pmix_en signal" "0,1" newline bitfld.word 0x0 9. "MPLLB_PMIX_SEL_OVRD_EN,Override bit for mpllb_ana_pmix_sel signal" "0,1" newline bitfld.word 0x0 8. "MPLLB_PMIX_EN,Override bit for mpllb_ana_pmix_en signal" "0,1" newline hexmask.word.byte 0x0 0.--7. 1. "MPLLB_PMIX_SEL,Overrides the mpllb_ana_pmix_sel signal" group.word 0x4000++0x1 line.word 0x0 "LANE0_DIG_ASIC_LANE_OVRD_IN,Override values for incoming LANE controls from ASIC" newline hexmask.word 0x0 3.--15. 1. "RESERVED_15_3,Reserved for Future use" newline bitfld.word 0x0 2. "EN,Enable override values for all inputs controlled by this register" "0,1" newline bitfld.word 0x0 1. "LANE_RX2TX_PAR_LB,Override value for lane_rx2tx_par_lb_en_r" "0,1" newline bitfld.word 0x0 0. "LANE_TX2RX_SER_LB,Override value for lane_tx2rx_ser_lb_en_r" "0,1" group.word 0x4004++0x1 line.word 0x0 "LANE0_DIG_ASIC_TX_OVRD_IN_0,Override values for incoming TX controls from ASIC. register #0" newline bitfld.word 0x0 15. "DATA_EN_OVRD_EN,Enable override for tx_data_en" "0,1" newline bitfld.word 0x0 14. "DATA_EN,Override value for tx_data_en" "0,1" newline bitfld.word 0x0 13. "MPLLB_SEL_OVRD_EN,Enable override for tx_mpllb_sel" "0,1" newline bitfld.word 0x0 12. "MPLLB_SEL,Override value for tx_mpllb_sel" "0,1" newline bitfld.word 0x0 11. "WIDTH_OVRD_EN,Enable override for tx_width[1:0]" "0,1" newline bitfld.word 0x0 9.--10. "WIDTH,Override value for tx_width[1:0]" "0,1,2,3" newline bitfld.word 0x0 8. "RATE_OVRD_EN,Enable override for tx_rate[2:0]" "0,1" newline bitfld.word 0x0 5.--7. "RATE,Override value for tx_rate[2:0]" "0,1,2,3,4,5,6,7" newline bitfld.word 0x0 4. "PSTATE_OVRD_EN,Enable override for tx_pstate[1:0]" "0,1" newline bitfld.word 0x0 2.--3. "PSTATE,Override value for tx_pstate[1:0]" "0,1,2,3" newline bitfld.word 0x0 1. "REQ_OVRD_EN,Enable override for tx_req" "0,1" newline bitfld.word 0x0 0. "REQ,Override value for tx_req" "0,1" group.word 0x4008++0x1 line.word 0x0 "LANE0_DIG_ASIC_TX_OVRD_IN_1,Override values for incoming TX drive controls from ASIC. register #1" newline bitfld.word 0x0 15. "MAIN_OVRD_EN,Enable override values for TX EQ main input" "0,1" newline hexmask.word.byte 0x0 9.--14. 1. "TX_MAIN_CURSOR,Override value for tx_eq_main" newline bitfld.word 0x0 8. "EN,Enable override values for inputs below controlled by this register" "0,1" newline bitfld.word 0x0 7. "VBOOST_EN,Override value for tx_vboost_en" "0,1" newline hexmask.word.byte 0x0 3.--6. 1. "IBOOST_LVL,Override value for tx_iboost_lvl" newline bitfld.word 0x0 2. "BEACON_EN,Override value for tx_beacon_en" "0,1" newline bitfld.word 0x0 1. "DISABLE,Override value for tx_disable" "0,1" newline bitfld.word 0x0 0. "NYQUIST_DATA,Override incoming data to nyquist" "0,1" group.word 0x400C++0x1 line.word 0x0 "LANE0_DIG_ASIC_TX_OVRD_IN_2,Override values for incoming TX drive controls from ASIC. register #2" newline rbitfld.word 0x0 14.--15. "RESERVED_15_14,Reserved for Future use" "0,1,2,3" newline bitfld.word 0x0 13. "POST_OVRD_EN,Enable override values for TX EQ post input" "0,1" newline hexmask.word.byte 0x0 7.--12. 1. "TX_POST_CURSOR,Override value for tx_eq_post" newline bitfld.word 0x0 6. "PRE_OVRD_EN,Enable override values for TX EQ pre input" "0,1" newline hexmask.word.byte 0x0 0.--5. 1. "TX_PRE_CURSOR,Override value for tx_eq_pre" group.word 0x4010++0x1 line.word 0x0 "LANE0_DIG_ASIC_TX_OVRD_IN_3,Override values for incoming TX drive controls from ASIC. register #3" newline hexmask.word.byte 0x0 8.--15. 1. "RESERVED_15_8,Reserved for Future use" newline bitfld.word 0x0 7. "LPD_OVRD_EN,Enable override for tx_lpd" "0,1" newline bitfld.word 0x0 6. "LPD,Override value for tx_lpd" "0,1" newline bitfld.word 0x0 5. "INVERT_OVRD_EN,Enable override for tx_invert" "0,1" newline bitfld.word 0x0 4. "INVERT,Override value for tx_invert" "0,1" newline bitfld.word 0x0 3. "DETECT_RX_REQ_OVRD_EN,Enable override for tx_detrx_req" "0,1" newline bitfld.word 0x0 2. "DETECT_RX_REQ,Override value for tx_detrx_req" "0,1" newline bitfld.word 0x0 1. "CLK_RDY_OVRD_EN,Enable override for tx_clk_rdy" "0,1" newline bitfld.word 0x0 0. "CLK_RDY,Override value for tx_clk_rdy" "0,1" group.word 0x4014++0x1 line.word 0x0 "LANE0_DIG_ASIC_TX_OVRD_IN_4,Override values for incoming TX drive controls from ASIC. register #4" newline hexmask.word 0x0 2.--15. 1. "RESERVED_15_2,Reserved for Future use" newline bitfld.word 0x0 1. "RESET_OVRD_EN,Enable override for tx_reset" "0,1" newline bitfld.word 0x0 0. "RESET,Override value for tx_reset" "0,1" group.word 0x4018++0x1 line.word 0x0 "LANE0_DIG_ASIC_TX_OVRD_OUT,Override values for outgoing TX controls to ASIC" newline hexmask.word 0x0 4.--15. 1. "RESERVED_15_4,Reserved for Future use" newline bitfld.word 0x0 3. "EN_DETRX_RESULT,Enable for override value for tx_detrx_result" "0,1" newline bitfld.word 0x0 2. "DETRX_RESULT,Override value for tx_detrx_result" "0,1" newline bitfld.word 0x0 1. "EN_TX_ACK,Enable for override value for tx_ack" "0,1" newline bitfld.word 0x0 0. "TX_ACK,Override value for tx_ack" "0,1" group.word 0x401C++0x1 line.word 0x0 "LANE0_DIG_ASIC_RX_OVRD_IN_0,Override values for incoming RX controls from ASIC. register #0" newline rbitfld.word 0x0 13.--15. "RESERVED_15_13,Reserved for Future use" "0,1,2,3,4,5,6,7" newline bitfld.word 0x0 12. "WIDTH_OVRD_EN,Enable override for rx_width" "0,1" newline bitfld.word 0x0 10.--11. "WIDTH,Override value for rx_width" "0,1,2,3" newline bitfld.word 0x0 9. "RATE_OVRD_EN,Enable override value for rx_rate" "0,1" newline bitfld.word 0x0 7.--8. "RATE,Override value for rx_rate" "0,1,2,3" newline bitfld.word 0x0 6. "PSTATE_OVRD_EN,Enable override value for rx_pstate" "0,1" newline bitfld.word 0x0 4.--5. "PSTATE,Override value for rx_pstate" "0,1,2,3" newline bitfld.word 0x0 3. "DATA_EN_OVRD_EN,Enable override value for rx_data_en" "0,1" newline bitfld.word 0x0 2. "DATA_EN,Override value for rx_data_en" "0,1" newline bitfld.word 0x0 1. "REQ_OVRD_EN,Enable override value for rx_req" "0,1" newline bitfld.word 0x0 0. "REQ,Override value for rx_req" "0,1" group.word 0x4020++0x1 line.word 0x0 "LANE0_DIG_ASIC_RX_OVRD_IN_1,Override values for incoming RX controls from ASIC. register #1" newline hexmask.word.byte 0x0 9.--15. 1. "RESERVED_15_9,Reserved for Future use" newline bitfld.word 0x0 8. "RX_REF_LD_VAL_6,Override value for rx_ref_ld_val[6]" "0,1" newline bitfld.word 0x0 7. "EN,Enable override values for all inputs controlled by this register" "0,1" newline bitfld.word 0x0 6. "RX_CDR_VCO_LOWFREQ,Override value for rx_cdr_vco_lowfreq" "0,1" newline hexmask.word.byte 0x0 0.--5. 1. "RX_REF_LD_VAL_5_0,Override value for rx_ref_ld_val[5:0]" group.word 0x4024++0x1 line.word 0x0 "LANE0_DIG_ASIC_RX_OVRD_IN_2,Override values for incoming RX controls from ASIC. register #2" newline rbitfld.word 0x0 14.--15. "RESERVED_15_14,Reserved for Future use" "0,1,2,3" newline bitfld.word 0x0 13. "EN,Enable override values for all inputs controlled by this register" "0,1" newline hexmask.word 0x0 0.--12. 1. "RX_VCO_LD_VAL,Override value for rx_vco_ld_val" group.word 0x4028++0x1 line.word 0x0 "LANE0_DIG_ASIC_RX_OVRD_IN_3,Override values for incoming RX controls from ASIC. register #3" newline rbitfld.word 0x0 15. "RESERVED_15_15,Reserved for Future use" "0,1" newline bitfld.word 0x0 14. "LOS_OVRD_EN,Enable override for rx_los_lfps_en and rx_los_threshold" "0,1" newline bitfld.word 0x0 13. "LOS_LPFS_EN,Override value for rx_los_lfps_en" "0,1" newline bitfld.word 0x0 10.--12. "LOS_THRSHLD,Override value for rx_los_threshold" "0,1,2,3,4,5,6,7" newline bitfld.word 0x0 9. "DISABLE_OVRD_EN,Enable override for rx_disable" "0,1" newline bitfld.word 0x0 8. "DISABLE,Override value for rx_disable" "0,1" newline bitfld.word 0x0 7. "CLK_SHIFT_OVRD_EN,Enable override for rx_clk_shift" "0,1" newline bitfld.word 0x0 6. "CLK_SHIFT,Override value for rx_clk_shift" "0,1" newline bitfld.word 0x0 5. "ALIGN_EN_OVRD_EN,Enable override for rx_align_en" "0,1" newline bitfld.word 0x0 4. "ALIGN_EN,Override value for rx_align_en" "0,1" newline bitfld.word 0x0 3. "CDR_SSC_EN_OVRD_EN,Enable override value for rx_cdr_ssc_en" "0,1" newline bitfld.word 0x0 2. "CDR_SSC_EN,Override value for rx_cdr_ssc_en" "0,1" newline bitfld.word 0x0 1. "CDR_TRACK_EN_OVRD_EN,Enable override value for rx_cdr_track_en" "0,1" newline bitfld.word 0x0 0. "CDR_TRACK_EN,Override value for rx_cdr_track_en" "0,1" group.word 0x402C++0x1 line.word 0x0 "LANE0_DIG_ASIC_RX_OVRD_IN_4,Override values for incoming RX controls from ASIC. register #4" newline hexmask.word.byte 0x0 10.--15. 1. "RESERVED_15_10,Reserved for Future use" newline bitfld.word 0x0 9. "TERM_OVRD_EN,Enable override for rx_term_acdc and rx_term_en" "0,1" newline bitfld.word 0x0 8. "TERM_ACDC,Override value for rx_term_acdc" "0,1" newline bitfld.word 0x0 7. "TERM_EN,Override value for rx_term_en" "0,1" newline bitfld.word 0x0 6. "ADPT_OVRD_EN,Enable override for rx_adpt_dfe_en and rx_adpt_afe_en" "0,1" newline bitfld.word 0x0 5. "ADAPT_DFE_EN,Override value for rx_adapt_dfe_en" "0,1" newline bitfld.word 0x0 4. "ADAPT_AFE_EN,Override value for rx_adapt_afe_en" "0,1" newline bitfld.word 0x0 3. "INVERT_OVRD_EN,Enable override for rx_invert" "0,1" newline bitfld.word 0x0 2. "INVERT,Override value for rx_invert" "0,1" newline bitfld.word 0x0 1. "LPD_OVRD_EN,Enable override for rx_lpd" "0,1" newline bitfld.word 0x0 0. "LPD,Override value for rx_lpd" "0,1" group.word 0x4030++0x1 line.word 0x0 "LANE0_DIG_ASIC_RX_OVRD_IN_5,Override values for incoming RX controls from ASIC. register #5" newline hexmask.word 0x0 2.--15. 1. "RESERVED_15_2,Reserved for Future use" newline bitfld.word 0x0 1. "RESET_OVRD_EN,Enable override for rx_reset" "0,1" newline bitfld.word 0x0 0. "RESET,Override value for rx_reset" "0,1" group.word 0x4034++0x1 line.word 0x0 "LANE0_DIG_ASIC_RX_OVRD_EQ_IN_0,Override values for incoming RX EQ controls from ASIC. register #0" newline hexmask.word.byte 0x0 11.--15. 1. "EQ_CTLE_BOOST,Override value for rx_eq_ctle_boost" newline hexmask.word.byte 0x0 7.--10. 1. "RESERVED," newline hexmask.word.byte 0x0 3.--6. 1. "EQ_AFE_GAIN,Override value for rx_eq_afe_gain" newline bitfld.word 0x0 0.--2. "EQ_ATT_LVL,Override value for rx_eq_att_lvl" "0,1,2,3,4,5,6,7" group.word 0x4038++0x1 line.word 0x0 "LANE0_DIG_ASIC_RX_OVRD_EQ_IN_1,Override values for incoming RX EQ controls from ASIC. register #1" newline bitfld.word 0x0 15. "EQ_OVRD_EN,Enable override value for rx_eq_* inputs" "0,1" newline hexmask.word.byte 0x0 7.--14. 1. "EQ_DFE_TAP1,Override value for rx_eq_dfe_tap1" newline hexmask.word.byte 0x0 0.--6. 1. "EQ_DFE_TAP2,Override value for rx_eq_dfe_tap2" group.word 0x403C++0x1 line.word 0x0 "LANE0_DIG_ASIC_RX_OVRD_OUT_0,Override values for outgoing RX controls to ASIC. register #0" newline hexmask.word 0x0 7.--15. 1. "RESERVED_15_7,Reserved for Future use" newline bitfld.word 0x0 6. "ADAPT_STS_OVRD_EN,Enable override for rx_adapt_sts" "0,1" newline bitfld.word 0x0 4.--5. "ADAPT_STS,Override value for rx_adapt_sts" "0,1,2,3" newline bitfld.word 0x0 3. "LOS_OUT_OVRD_EN,Enable override for rx_los_r" "0,1" newline bitfld.word 0x0 2. "LOS,Override value for rx_los" "0,1" newline bitfld.word 0x0 1. "ACK_OVRD_EN,Enable override for rx_ack" "0,1" newline bitfld.word 0x0 0. "ACK,Override value for rx_ack" "0,1" rgroup.word 0x4040++0x1 line.word 0x0 "LANE0_DIG_ASIC_LANE_ASIC_IN,Current values for incoming LANE controls from ASIC" newline hexmask.word 0x0 2.--15. 1. "RESERVED_15_2,Reserved for Future use" newline bitfld.word 0x0 1. "LANE_RX2TX_PAR_LB,Value from ASIC for lane_rx2tx_par_lb_en_r" "0,1" newline bitfld.word 0x0 0. "LANE_TX2RX_SER_LB,Value from ASIC for lane_tx2rx_ser_lb_en_r" "0,1" rgroup.word 0x4044++0x1 line.word 0x0 "LANE0_DIG_ASIC_TX_ASIC_IN_0,Current values for incoming TX controls from ASIC. register #0" newline bitfld.word 0x0 15. "DISABLE,Value from ASIC for tx_disable" "0,1" newline bitfld.word 0x0 14. "DETECT_RX_REQ,Value from ASIC for tx_detrx_req" "0,1" newline bitfld.word 0x0 13. "MPLLB_SEL,Value from ASIC for tx_mpllb_sel" "0,1" newline bitfld.word 0x0 11.--12. "WIDTH,Value from ASIC for tx_width[1:0]" "0,1,2,3" newline bitfld.word 0x0 8.--10. "RATE,Value from ASIC for tx_rate[2:0]" "0,1,2,3,4,5,6,7" newline bitfld.word 0x0 6.--7. "PSTATE,Value from ASIC for tx_pstate[1:0]" "0,1,2,3" newline bitfld.word 0x0 5. "LPD,Value from ASIC for tx_lpd" "0,1" newline bitfld.word 0x0 4. "REQ,Value from ASIC for tx_req" "0,1" newline bitfld.word 0x0 3. "DATA_EN,Value from ASIC for tx_data_en" "0,1" newline bitfld.word 0x0 2. "INVERT,Value from ASIC for tx_invert" "0,1" newline bitfld.word 0x0 1. "RESET,Value from ASIC for tx_reset" "0,1" newline bitfld.word 0x0 0. "CLK_RDY,Value from ASIC for tx_clk_rdy" "0,1" rgroup.word 0x4048++0x1 line.word 0x0 "LANE0_DIG_ASIC_TX_ASIC_IN_1,Current values for incoming TX controls from ASIC. register #1" newline hexmask.word.byte 0x0 12.--15. 1. "RESERVED_15_12,Reserved for Future use" newline hexmask.word.byte 0x0 6.--11. 1. "TX_MAIN_CURSOR,Value from ASIC for tx_eq_main" newline bitfld.word 0x0 5. "VBOOST_EN,Value from ASIC for tx_vboost_en" "0,1" newline hexmask.word.byte 0x0 1.--4. 1. "IBOOST_LVL,Value from ASIC for tx_iboost_lvl" newline bitfld.word 0x0 0. "BEACON_EN,Value from ASIC for tx_beacon_en" "0,1" rgroup.word 0x404C++0x1 line.word 0x0 "LANE0_DIG_ASIC_TX_ASIC_IN_2,Current values for incoming TX controls from ASIC. register #2" newline hexmask.word.byte 0x0 12.--15. 1. "RESERVED_15_12,Reserved for Future use" newline hexmask.word.byte 0x0 6.--11. 1. "TX_POST_CURSOR,Value from ASIC for tx_eq_post" newline hexmask.word.byte 0x0 0.--5. 1. "TX_PRE_CURSOR,Value from ASIC for tx_eq_pre" rgroup.word 0x4050++0x1 line.word 0x0 "LANE0_DIG_ASIC_TX_ASIC_OUT,Current values for outgoing TX status controls from PHY" newline hexmask.word 0x0 2.--15. 1. "RESERVED_15_2,Reserved for Future use" newline bitfld.word 0x0 1. "DETRX_RESULT,Value from PHY for tx_detrx_result" "0,1" newline bitfld.word 0x0 0. "TX_ACK,Value from PHY for tx_ack" "0,1" rgroup.word 0x4054++0x1 line.word 0x0 "LANE0_DIG_ASIC_RX_ASIC_IN_0,Current values for incoming RX controls from ASIC. register #0" newline bitfld.word 0x0 15. "RESERVED_15_15,Reserved for Future use" "0,1" newline bitfld.word 0x0 14. "CDR_TRACK_EN,Value from ASIC for rx_cdr_track_en" "0,1" newline bitfld.word 0x0 13. "ADAPT_DFE_EN,Value from ASIC for rx_adapt_dfe_en" "0,1" newline bitfld.word 0x0 12. "ADAPT_AFE_EN,Value from ASIC for rx_adapt_afe_en" "0,1" newline bitfld.word 0x0 11. "RESERVED," "0,1" newline bitfld.word 0x0 9.--10. "WIDTH,Value from ASIC for rx_width" "0,1,2,3" newline bitfld.word 0x0 7.--8. "RATE,Value from ASIC for rx_rate" "0,1,2,3" newline bitfld.word 0x0 5.--6. "PSTATE,Value from ASIC for rx_pstate" "0,1,2,3" newline bitfld.word 0x0 4. "LPD,Value from ASIC for rx_lpd" "0,1" newline bitfld.word 0x0 3. "REQ,Value from ASIC for rx_req" "0,1" newline bitfld.word 0x0 2. "DATA_EN,Value from ASIC for rx_data_en" "0,1" newline bitfld.word 0x0 1. "INVERT,Value from ASIC for rx_invert" "0,1" newline bitfld.word 0x0 0. "RESET,Value from ASIC for rx_reset" "0,1" rgroup.word 0x4058++0x1 line.word 0x0 "LANE0_DIG_ASIC_RX_ASIC_IN_1,Current values for incoming RX controls from ASIC. register #1" newline hexmask.word.byte 0x0 10.--15. 1. "RESERVED_15_10,Reserved for Future use" newline bitfld.word 0x0 9. "RX_TERM_ACDC,Value from ASIC for rx_term_acdc" "0,1" newline bitfld.word 0x0 8. "RX_TERM_EN,Value from ASIC for rx_term_en" "0,1" newline bitfld.word 0x0 7. "LOS_LPFS_EN,Value from ASIC for rx_los_lfps_en" "0,1" newline bitfld.word 0x0 4.--6. "LOS_THRSHLD,Value from ASIC for rx_los_threshold" "0,1,2,3,4,5,6,7" newline bitfld.word 0x0 3. "DISABLE,Value from ASIC for rx_disable" "0,1" newline bitfld.word 0x0 2. "CLK_SHIFT,Value from ASIC for rx_clk_shift" "0,1" newline bitfld.word 0x0 1. "ALIGN_EN,Value from ASIC for rx_align_en" "0,1" newline bitfld.word 0x0 0. "CDR_SSC_EN,Value from ASIC for rx_cdr_ssc_en" "0,1" rgroup.word 0x405C++0x1 line.word 0x0 "LANE0_DIG_ASIC_RX_EQ_ASIC_IN_0,Current values for incoming RX EQ controls from ASIC. register #0" newline hexmask.word.byte 0x0 11.--15. 1. "EQ_CTLE_BOOST,Value from ASIC for rx_eq_ctle_boost" newline hexmask.word.byte 0x0 7.--10. 1. "RESERVED," newline hexmask.word.byte 0x0 3.--6. 1. "EQ_AFE_GAIN,Value from ASIC for rx_eq_afe_gain" newline bitfld.word 0x0 0.--2. "EQ_ATT_LVL,Value from ASIC for rx_eq_att_lvl" "0,1,2,3,4,5,6,7" rgroup.word 0x4060++0x1 line.word 0x0 "LANE0_DIG_ASIC_RX_EQ_ASIC_IN_1,Current values for incoming RX EQ controls from ASIC. register #1" newline bitfld.word 0x0 15. "RESERVED_15_15,Reserved for Future use" "0,1" newline hexmask.word.byte 0x0 7.--14. 1. "EQ_DFE_TAP1,Value from ASIC for rx_eq_dfe_tap1" newline hexmask.word.byte 0x0 0.--6. 1. "EQ_DFE_TAP2,Value from ASIC for rx_eq_dfe_tap2" rgroup.word 0x4064++0x1 line.word 0x0 "LANE0_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0,Current values for incoming RX CDR VCO controls from ASIC. register #0" newline hexmask.word.byte 0x0 8.--15. 1. "RESERVED_15_8,Reserved for Future use" newline hexmask.word.byte 0x0 1.--7. 1. "RX_REF_LD_VAL,Value from ASIC for rx_ref_ld_val" newline bitfld.word 0x0 0. "RX_CDR_VCO_LOWFREQ,Value from ASIC for rx_cdr_vco_lowfreq" "0,1" rgroup.word 0x4068++0x1 line.word 0x0 "LANE0_DIG_ASIC_RX_CDR_VCO_ASIC_IN_1,Current values for incoming RX CDR VCO controls from ASIC. register #1" newline bitfld.word 0x0 13.--15. "RESERVED_15_13,Reserved for Future use" "0,1,2,3,4,5,6,7" newline hexmask.word 0x0 0.--12. 1. "RX_VCO_LD_VAL,Value from ASIC for rx_vco_ld_val" rgroup.word 0x406C++0x1 line.word 0x0 "LANE0_DIG_ASIC_RX_ASIC_OUT_0,Current values for outgoing RX status controls from PHY. register #0" newline hexmask.word 0x0 5.--15. 1. "RESERVED_15_5,Reserved for Future use" newline bitfld.word 0x0 3.--4. "ADAPT_STS,Value from PHY for rx_adapt_sts" "0,1,2,3" newline bitfld.word 0x0 2. "VALID,Value from PHY for rx_valid" "0,1" newline bitfld.word 0x0 1. "LOS,Value from PHY for rx_los" "0,1" newline bitfld.word 0x0 0. "ACK,Value from PHY for rx_ack" "0,1" repeat 2. (list 0x0 0x1 )(list 0x0 0x8 ) group.word ($2+0x4080)++0x1 line.word 0x0 "LANE0_DIG_TX_PWRCTL_TX_PSTATE_P$1,TX Power State Control Register for P0" newline hexmask.word.byte 0x0 9.--15. 1. "RESERVED_15_9,Reserved for Future use" newline bitfld.word 0x0 8. "TX_P0_ALLOW_RXDET,If asserted then rxdet request is allowed in P0" "0,1" newline bitfld.word 0x0 7. "TX_P0_DATA_EN,This is ANDed with top-level tx_data_en asic input" "0,1" newline bitfld.word 0x0 6. "TX_P0_DIG_CLK_EN,Enable/Disable TX digital clocks in P0" "0,1" newline bitfld.word 0x0 5. "TX_P0_ANA_SERIAL_EN,Value of TX ana serial_en in P0" "0,1" newline bitfld.word 0x0 4. "TX_P0_ANA_RESET,Value of TX ana reset in P0" "0,1" newline bitfld.word 0x0 3. "TX_P0_ANA_WORD_CLK_EN,Value of TX ana word_clk_en in P0" "0,1" newline bitfld.word 0x0 2. "TX_P0_ANA_CLK_EN,Value of TX ana clk_en in P0" "0,1" newline bitfld.word 0x0 1. "TX_P0_ANA_VCM_HOLD,Value of TX ana vcm_hold in P0" "0,1" newline bitfld.word 0x0 0. "TX_P0_ANA_REFGEN_EN,Value of TX ana refgen_en in P0" "0,1" repeat.end group.word 0x4084++0x1 line.word 0x0 "LANE0_DIG_TX_PWRCTL_TX_PSTATE_P0S,TX Power State Control Register for P0S" newline hexmask.word.byte 0x0 9.--15. 1. "RESERVED_15_9,Reserved for Future use" newline bitfld.word 0x0 8. "TX_P0S_ALLOW_RXDET,If asserted then rxdet request is allowed in P0S" "0,1" newline bitfld.word 0x0 7. "TX_P0S_DATA_EN,This is ANDed with top-level tx_data_en asic input" "0,1" newline bitfld.word 0x0 6. "TX_P0S_DIG_CLK_EN,Enable/Disable TX digital clocks in P0S" "0,1" newline bitfld.word 0x0 5. "TX_P0S_ANA_SERIAL_EN,Value of TX ana serial_en in P0S" "0,1" newline bitfld.word 0x0 4. "TX_P0S_ANA_RESET,Value of TX ana reset in P0S" "0,1" newline bitfld.word 0x0 3. "TX_P0S_ANA_WORD_CLK_EN,Value of TX ana word_clk_en in P0S" "0,1" newline bitfld.word 0x0 2. "TX_P0S_ANA_CLK_EN,Value of TX ana clk_en in P0S" "0,1" newline bitfld.word 0x0 1. "TX_P0S_ANA_VCM_HOLD,Value of TX ana vcm_hold in P0S" "0,1" newline bitfld.word 0x0 0. "TX_P0S_ANA_REFGEN_EN,Value of TX ana refgen_en in P0S" "0,1" group.word 0x408C++0x1 line.word 0x0 "LANE0_DIG_TX_PWRCTL_TX_PSTATE_P2,TX Power State Control Register for P2" newline hexmask.word.byte 0x0 10.--15. 1. "RESERVED_15_10,Reserved for Future use" newline bitfld.word 0x0 9. "TX_P2_ALLOW_VBOOST,If asserted then vboost is allowed in P2" "0,1" newline bitfld.word 0x0 8. "TX_P2_ALLOW_RXDET,If asserted then rxdet request is allowed" "0,1" newline bitfld.word 0x0 7. "TX_P2_DATA_EN,This is ANDed with top-level tx_data_en asic input" "0,1" newline bitfld.word 0x0 6. "TX_P2_DIG_CLK_EN,Enable/Disable TX digital clocks in P2" "0,1" newline bitfld.word 0x0 5. "TX_P2_ANA_SERIAL_EN,Value of TX ana serial_en in P2" "0,1" newline bitfld.word 0x0 4. "TX_P2_ANA_RESET,Value of TX ana reset in P2" "0,1" newline bitfld.word 0x0 3. "TX_P2_ANA_WORD_CLK_EN,Value of TX ana word_clk_en in P2" "0,1" newline bitfld.word 0x0 2. "TX_P2_ANA_CLK_EN,Value of TX ana clk_en in P2" "0,1" newline bitfld.word 0x0 1. "TX_P2_ANA_VCM_HOLD,Value of TX ana vcm_hold in P2" "0,1" newline bitfld.word 0x0 0. "TX_P2_ANA_REFGEN_EN,Value of TX ana refgen_en in P2" "0,1" group.word 0x4090++0x1 line.word 0x0 "LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_0,TX Power UP Time Register #0" newline hexmask.word.byte 0x0 8.--15. 1. "TX_CLK_EN,Power up time (in ref_range cycles) for TX ana clock enable (spec: >=1us)" newline hexmask.word.byte 0x0 0.--7. 1. "TX_REFGEN_EN_TIME,Power up time (in ref_range cycles) for TX ana refgen enable (spec: >=500ns)" group.word 0x4094++0x1 line.word 0x0 "LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_1,TX Power UP Time Register #1" newline bitfld.word 0x0 15. "SKIP_TX_VCM_HOLD_WAIT,Skip wait for TX common mode hold power up" "0,1" newline hexmask.word 0x0 0.--14. 1. "TX_VCM_HOLD_TIME_14_0,Power up time (in ref_range cycles) for TX common mode (spec: >=800us) (bits 14:0)" group.word 0x4098++0x1 line.word 0x0 "LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_2,TX Power UP Time Register #2" newline bitfld.word 0x0 13.--15. "DTB_SEL,Selects data to drive on DTB 0 - disabled 1 - tx_ack and tx_pwrsm_state[0] 2 - tx_ana_rxdetp_result_i tx_ana_rxdetm_result_i 3 - tx_ana_reset_i tx_ana_clk_en_i 4 - analog/asic clocks 5 - asic early signal / clock aligner shift 6 - tx_clk_state.." "disabled,tx_ack and tx_pwrsm_state[0],tx_ana_rxdetp_result_i,tx_ana_reset_i,analog/asic clocks,asic early signal / clock aligner shift,tx_clk_state counter / lbert strobe,ref_dig_rst/tx_dig_rst" newline hexmask.word 0x0 0.--12. 1. "TX_VBOOST_DIS_TIME_12_0,TX vboost disable time (in ref_range cycles) (spec: >=200us) (bits 12:0)" group.word 0x409C++0x1 line.word 0x0 "LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_3,TX Power UP Time Register #3" newline hexmask.word 0x0 4.--15. 1. "RESERVED_15_4,Reserved for Future use" newline bitfld.word 0x0 3. "TX_VBOOST_DIS_TIME_13,TX vboost disable time (in ref_range cycles) (spec: >=200us) (bit 13)" "0,1" newline bitfld.word 0x0 0.--2. "TX_VCM_HOLD_TIME_17_15,Power up time (in ref_range cycles) for TX common mode (spec: >=800us) (bits 17:15)" "0,1,2,3,4,5,6,7" group.word 0x40A0++0x1 line.word 0x0 "LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_4,TX Power UP Time Register #4" newline rbitfld.word 0x0 15. "RESERVED_15_15,Reserved for Future use" "0,1" newline hexmask.word 0x0 0.--14. 1. "TX_VCM_HOLD_GS_TIME,TX common mode gear-shift time (in ref range cycles) (spec: >=400us)" group.word 0x40A4++0x1 line.word 0x0 "LANE0_DIG_TX_PWRCTL_TX_PWRUP_TIME_5,TX Power UP Time Register #5" newline rbitfld.word 0x0 15. "RESERVED_15_15,Reserved for Future use" "0,1" newline bitfld.word 0x0 13.--14. "TX_SERIAL_EN_TIME,Power up time (in ref_range cycles) for TX ana serial enable (spec: >=50ns)" "0,1,2,3" newline bitfld.word 0x0 11.--12. "TX_RESET_TIME,TX Reset deassertion time (in ref_range cycles) (spec: >=50ns)" "0,1,2,3" newline bitfld.word 0x0 10. "FAST_TX_RXDET,Enable fast TX RX-detection (simulation only)" "0,1" newline hexmask.word 0x0 0.--9. 1. "TX_RXDET_TIME,RX Detect up time (in ref_range cycles) starting from asserting rxdet_en (spec: from 3.55us to 25.9us)" group.word 0x40A8++0x1 line.word 0x0 "LANE0_DIG_TX_LBERT_CTL,Pattern Generator controls" newline rbitfld.word 0x0 15. "RESERVED_15_15,Reserved for Future use" "0,1" newline hexmask.word 0x0 5.--14. 1. "PAT0,Pattern for modes 3-5" newline bitfld.word 0x0 4. "TRIGGER_ERR,Insert a single error into a lsb Any write of a 1 to this bit will insert an error" "0,1" newline hexmask.word.byte 0x0 0.--3. 1. "MODE,Pattern to generate When changing modes you must change to disabled first 0 - Disabled 1 - lfsr31: X^31 + X^28 + 1 2 - lfsr23: X^23 + X^18 + 1 3 - lfsr23: x^23 + x^21 + x^16 + x^8 + x^5 + x^2 + 1 4 - lfsr16: x^16 + x^5 + x^4 + x^3 + 1 5 - lfsr15:.." group.word 0x40AC++0x1 line.word 0x0 "LANE0_DIG_TX_CLK_ALIGN_TX_CTL_0,TX Clock Alignment Control Register #0" newline hexmask.word.byte 0x0 9.--15. 1. "RESERVED_15_9,Reserved for Future use" newline bitfld.word 0x0 8. "TX_FIFO_BYPASS,By-pass TX datapath FIFO" "0,1" newline hexmask.word.byte 0x0 4.--7. 1. "TX_NUM_2UI_SHIFTS_20B_MODE," newline hexmask.word.byte 0x0 0.--3. 1. "TX_NUM_2UI_SHIFTS_16B_MODE," repeat 3. (list 0x0 0x1 0x2 )(list 0x0 0x8 0xC ) group.word ($2+0x4100)++0x1 line.word 0x0 "LANE0_DIG_RX_PWRCTL_RX_PSTATE_P$1,RX Power State Control Register for P0" newline hexmask.word.byte 0x0 12.--15. 1. "RESERVED_15_12,Reserved for Future use" newline bitfld.word 0x0 11. "RX_P0_DIG_CLK_EN,Enable/Disable RX digital clocks in P0" "0,1" newline bitfld.word 0x0 10. "RX_P0_VCO_CONTCAL_EN,Enable/Disable continous calibration of the RX VCO in P0 If RX_P0_DIG_CLK_EN and the top-level rx_data_en are both asserted then contiuous calibration is turned off and this value is ignored" "0,1" newline bitfld.word 0x0 9. "RX_P0_VCO_CAL_RST,Enable/Disable resetting the RX VCO in P0" "0,1" newline bitfld.word 0x0 8. "RX_P0_VCO_FREQ_RST,Enable/Disable resetting the RX VCO frequency in P0" "0,1" newline bitfld.word 0x0 7. "RX_P0_ANA_CDR_EN,Value of RX ana cdr_en in P0" "0,1" newline bitfld.word 0x0 6. "RX_P0_ANA_DESER_EN,Value of RX ana deserial_en in P0" "0,1" newline bitfld.word 0x0 5. "RX_P0_ANA_CLK_DCC_EN,Value of RX ana CLK_DCC_EN in P0" "0,1" newline bitfld.word 0x0 4. "RX_P0_ANA_CLK_EN,Value of RX ana clk_en in P0" "0,1" newline bitfld.word 0x0 3. "RESERVED," "0,1" newline bitfld.word 0x0 2. "RX_P0_ANA_CLK_VREG_EN,Value of RX ana clk_vreg_en in P0" "0,1" newline bitfld.word 0x0 1. "RX_P0_ANA_AFE_EN,Value of RX ana afe_en in P0" "0,1" newline bitfld.word 0x0 0. "RX_P0_ANA_LOS_EN,Value of RX ana los_en in P0" "0,1" repeat.end group.word 0x4104++0x1 line.word 0x0 "LANE0_DIG_RX_PWRCTL_RX_PSTATE_P0S,RX Power State Control Register for P0S" newline hexmask.word.byte 0x0 12.--15. 1. "RESERVED_15_12,Reserved for Future use" newline bitfld.word 0x0 11. "RX_P0S_DIG_CLK_EN,Enable/Disable RX digital clocks in P0S" "0,1" newline bitfld.word 0x0 10. "RX_P0S_VCO_CONTCAL_EN,Enable/Disable continous calibration of the RX VCO in P0S If RX_P0S_DIG_CLK_EN and the top-level rx_data_en are both asserted then contiuous calibration is turned off and this value is ignored" "0,1" newline bitfld.word 0x0 9. "RX_P0S_VCO_CAL_RST,Enable/Disable resetting the RX VCO in P0S" "0,1" newline bitfld.word 0x0 8. "RX_P0S_VCO_FREQ_RST,Enable/Disable resetting the RX VCO frequency in P0S" "0,1" newline bitfld.word 0x0 7. "RX_P0S_ANA_CDR_EN,Value of RX ana cdr_en in P0S" "0,1" newline bitfld.word 0x0 6. "RX_P0S_ANA_DESER_EN,Value of RX ana deserial_en in P0S" "0,1" newline bitfld.word 0x0 5. "RX_P0S_ANA_CLK_DCC_EN,Value of RX ana CLK_DCC_EN in P0S" "0,1" newline bitfld.word 0x0 4. "RX_P0S_ANA_CLK_EN,Value of RX ana clk_en in P0S" "0,1" newline bitfld.word 0x0 3. "RESERVED," "0,1" newline bitfld.word 0x0 2. "RX_P0S_ANA_CLK_VREG_EN,Value of RX ana clk_vreg_en in P0S" "0,1" newline bitfld.word 0x0 1. "RX_P0S_ANA_AFE_EN,Value of RX ana afe_en in P0S" "0,1" newline bitfld.word 0x0 0. "RX_P0S_ANA_LOS_EN,Value of RX ana los_en in P0S" "0,1" group.word 0x4110++0x1 line.word 0x0 "LANE0_DIG_RX_PWRCTL_RX_PWRUP_TIME_0,RX Power UP Time Register #0" newline hexmask.word.byte 0x0 10.--15. 1. "RESERVED_15_10,Reserved for Future use" newline bitfld.word 0x0 9. "SKIP_RX_LOS_EN_WAIT,Skip wait for RX LOS enable" "0,1" newline hexmask.word 0x0 0.--8. 1. "RX_LOS_EN_TIME,Power up time (in ref_range cycles) for RX ana los enable (spec >=10us)" group.word 0x4114++0x1 line.word 0x0 "LANE0_DIG_RX_PWRCTL_RX_PWRUP_TIME_1,RX Power UP Time Register #1" newline rbitfld.word 0x0 14.--15. "RESERVED_15_14,Reserved for Future use" "0,1,2,3" newline bitfld.word 0x0 13. "FAST_RX_VREG_EN,Enable fast RX VREG enable (simulation only)" "0,1" newline hexmask.word.byte 0x0 7.--12. 1. "RX_VREG_EN_TIME,Power up time (in ref_range cycles) for RX ana vreg enable (spec 500ns)" newline bitfld.word 0x0 6. "FAST_RX_AFE_EN,Enable fast RX AFE enable (simulation only)" "0,1" newline hexmask.word.byte 0x0 0.--5. 1. "RX_AFE_EN_TIME,Power up time (in ref_range cycles) for RX ana AFE enable (spec >=1us)" group.word 0x4118++0x1 line.word 0x0 "LANE0_DIG_RX_PWRCTL_RX_PWRUP_TIME_2,RX Power UP Time Register #2" newline hexmask.word 0x0 7.--15. 1. "RESERVED_15_7,Reserved for Future use" newline bitfld.word 0x0 6. "FAST_RX_CLK_EN,Enable fast RX clock enable (simulation only)" "0,1" newline hexmask.word.byte 0x0 0.--5. 1. "RX_CLK_EN_TIME,Power up time (in ref_range cycles) for RX ana clk (or dcc) enable (spec >1us)" group.word 0x411C++0x1 line.word 0x0 "LANE0_DIG_RX_PWRCTL_RX_PWRUP_TIME_3,RX Power UP Time Register #3" newline bitfld.word 0x0 14.--15. "RX_DESER_DIS_TIME,Power down time in (ref_range cycles) for RX ana deserial enable" "0,1,2,3" newline bitfld.word 0x0 12.--13. "RX_DESER_EN_TIME,Power up time (in ref_range cycles) for RX ana deserial enable" "0,1,2,3" newline hexmask.word.byte 0x0 8.--11. 1. "RX_CDR_EN_TIME,Power up time (in ref_range cycles) for RX ana cdr (or dfe/dfe_taps) enable (spec 0ns)" newline hexmask.word.byte 0x0 2.--7. 1. "RSVD_3_7_2,Reserved" newline bitfld.word 0x0 0.--1. "RX_RATE_TIME,Power up time (in ref_range cycles) for RX ana rate or width change" "0,1,2,3" group.word 0x4120++0x1 line.word 0x0 "LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0,RX VCO calibration controls register #0" newline hexmask.word.byte 0x0 12.--15. 1. "RESERVED_15_12,Reserved for Future use" newline bitfld.word 0x0 9.--11. "INT_GAIN_CAL_BOUNCE_CNT,Number of bounces (i.e. direction changes) on the int_gain code before indicating that the RX VCO calibration is done" "0,1,2,3,4,5,6,7" newline bitfld.word 0x0 6.--8. "INT_GAIN_CAL_CNT_SHIFT,Number of shifts to apply to ld_cnt inputs when performing int_gain code calibration" "0,1,2,3,4,5,6,7" newline bitfld.word 0x0 5. "INT_GAIN_CAL_FIXED_CNT_EN,Enable a fixed count (instead of bounce count) for int_gain code calibration" "0,1" newline hexmask.word.byte 0x0 0.--4. 1. "INT_GAIN_CAL_FIXED_CNT,Number of steps done during int_gain code calibration when INT_GAIN_CAL_FIXED_CNT_EN is enabled." group.word 0x4124++0x1 line.word 0x0 "LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1,RX VCO calibration controls register #1" newline hexmask.word.byte 0x0 9.--15. 1. "DTB_SEL,DTB select for RX VCO dtb signals 7'h01 - {chkfrq_en ref_dig_clk} 7'h02 - {rx_ana_cdr_vco_en_i rx_ana_cdr_startup_i} 7'h04 - {rx_vco_up dpll_freq_rst} 7'h08 - {rx_vco_contcal_en rx_vco_cal_rst} 7'h10 - {chkfrq_done vcoclk_too_fast} 7'h20 -.." newline hexmask.word.byte 0x0 5.--8. 1. "DPLL_CAL_UG,DPLL calibration update on int_gain code 3'h0 - 0 Else - (1/16)*2^(DPLL_CAL_UG-1) LSB/update Maximum DPLL_CAL_UG=10 i.e. 32 LSB/update" newline bitfld.word 0x0 4. "DISABLE_INT_CAL_MODE,When asserted then the DPLL frequency register is never modified by the RX VCO calibration FSM (even if DPLL_CAL_UG is non-zero). In this case the calibration will always be performed on the VCO freq_tune code. This allows.." "0,1" newline bitfld.word 0x0 3. "RX_VCO_CONTCAL_EN,Override value for the continous calibration enable from the RX PWRSM" "0,1" newline bitfld.word 0x0 2. "RX_VCO_CAL_RST,Override value for the calibration reset from the RX PWRSM" "0,1" newline bitfld.word 0x0 1. "RX_VCO_FREQ_RST,Override value for the frequency reset from the RX PWRSM" "0,1" newline bitfld.word 0x0 0. "RX_VCO_OVRD_SEL,Override the calibration controls from the RX PWRSM" "0,1" group.word 0x4128++0x1 line.word 0x0 "LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2,RX VCO calibration controls register #2" newline bitfld.word 0x0 15. "SKIP_RX_VCO_CAL,Skip RX VCO calibration altogether" "0,1" newline bitfld.word 0x0 14. "SKIP_RX_VCO_FREQ_TUNE_CAL,Skip RX VCO coarse calibration" "0,1" newline hexmask.word.byte 0x0 10.--13. 1. "FREQ_TUNE_CAL_STEPS,Number of cal steps of freq tune" newline hexmask.word 0x0 0.--9. 1. "FREQ_TUNE_START_VAL,Starting value of freq tune code" group.word 0x412C++0x1 line.word 0x0 "LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0,RX Power UP Time Register #0" newline bitfld.word 0x0 15. "FAST_RX_VCO_WAIT,Enable fast RX VCO power up (simulation only)" "0,1" newline hexmask.word.byte 0x0 11.--14. 1. "RX_VCO_CNTR_PWRUP_TIME,Power up time (in ref_range cycles) for Rx ana vco cnter (spec >200ns)" newline hexmask.word.byte 0x0 7.--10. 1. "RX_VCO_UPDATE_TIME,Settle time (in ref_range cycles) for RX ana vco update (freq_tune or int_gain) (spec >200ns)" newline hexmask.word.byte 0x0 0.--6. 1. "RX_VCO_STARTUP_TIME,Power up time (in ref_range cycles) for RX ana vco startup (spec >1us)" group.word 0x4130++0x1 line.word 0x0 "LANE0_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1,RX Power UP Time Register #1" newline hexmask.word 0x0 3.--15. 1. "RESERVED_15_3,Reserved for Future use" newline bitfld.word 0x0 0.--2. "RX_VCO_CNTR_SETTLE_TIME,RX VCO counter value settling time in (ref_dig_clk cycles) (spec: 3 ref_dig_clk cycle)" "0,1,2,3,4,5,6,7" rgroup.word 0x4134++0x1 line.word 0x0 "LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_0,RX VCO status register #0" newline bitfld.word 0x0 14.--15. "RESERVED_15_14,Reserved for Future use" "0,1,2,3" newline bitfld.word 0x0 13. "RX_ANA_CDR_VCO_EN,Current value of rx_ana_cdr_vco_en_i" "0,1" newline bitfld.word 0x0 12. "RX_ANA_CDR_STARTUP,Current value of rx_ana_cdr_startup_i" "0,1" newline bitfld.word 0x0 11. "RX_ANA_VCO_CNTR_EN,Current value of rx_ana_vco_cntr_en_i" "0,1" newline bitfld.word 0x0 10. "RX_ANA_VCO_CNTR_PD,Current value of rx_ana_vco_cntr_pd_i" "0,1" newline hexmask.word 0x0 0.--9. 1. "RX_ANA_CDR_FREQ_TUNE,Current value of rx_ana_cdr_freq_tune_i" rgroup.word 0x4138++0x1 line.word 0x0 "LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_1,RX VCO status register #1" newline hexmask.word.byte 0x0 9.--15. 1. "RESERVED_15_9,Reserved for Future use" newline bitfld.word 0x0 8. "DPLL_FREQ_RST,Indicates that the RX integral frequency is reset or not" "0,1" newline bitfld.word 0x0 7. "RX_VCO_CAL_DONE,Indicates that the RX VCO has completed calibration" "0,1" newline bitfld.word 0x0 6. "RX_VCO_CONTCAL_EN,Value of the continous calibration enable from the RX PWRSM" "0,1" newline bitfld.word 0x0 5. "RX_VCO_CAL_RST,Value of the calibration reset from the RX PWRSM" "0,1" newline bitfld.word 0x0 4. "RX_VCO_FREQ_RST,Value of the RX VCO frequency reset from the RX PWRSM" "0,1" newline hexmask.word.byte 0x0 0.--3. 1. "RX_VCO_FSM_STATE,Value of the RX VCO CAL FSM" rgroup.word 0x413C++0x1 line.word 0x0 "LANE0_DIG_RX_VCOCAL_RX_VCO_STAT_2,RX VCO status register #2" newline bitfld.word 0x0 15. "RX_VCO_UP,Indicates that the RX VCO is ready" "0,1" newline bitfld.word 0x0 14. "RX_VCO_CORRECT,Indicates that the RX VCO clock has the correct frequency" "0,1" newline bitfld.word 0x0 13. "VCOCLK_TOO_FAST,Indicates that the RX VCO clock frequency is too fast" "0,1" newline hexmask.word 0x0 0.--12. 1. "VCO_CNTR_FINAL,Value of Rx VCO counter when refclk counter expired" group.word 0x4140++0x1 line.word 0x0 "LANE0_DIG_RX_RX_ALIGN_XAUI_COMM_MASK,XAUI_COMMA Mask" newline hexmask.word.byte 0x0 10.--15. 1. "RESERVED_15_10,Reserved for Future use" newline hexmask.word 0x0 0.--9. 1. "XAUI_COMM_MASK,XAUI_COMMA Mask. For 10-bit COMMA set the mask to 0x3FF and for 7-bit COMMA set the mask to 0x3F8" group.word 0x4144++0x1 line.word 0x0 "LANE0_DIG_RX_LBERT_CTL,Pattern Matcher controls" newline hexmask.word 0x0 5.--15. 1. "RESERVED_15_5,Reserved for Future use" newline bitfld.word 0x0 4. "SYNC,Synchronize pattern matcher LFSR with incoming data A write of a one to this bit will reset the error counter and start a synchronization of the PM. There is no need to write this back to zero to run normally." "0,1" newline hexmask.word.byte 0x0 0.--3. 1. "MODE,Pattern to match When changing modes you must change to disabled first 0 - Disabled 1 - lfsr31: X^31 + X^28 + 1 2 - lfsr23: X^23 + X^18 + 1 3 - lfsr23: x^23 + x^21 + x^16 + x^8 + x^5 + x^2 + 1 4 - lfsr16: x^16 + x^5 + x^4 + x^3 + 1 5 - lfsr15: X^15.." group.word 0x4148++0x1 line.word 0x0 "LANE0_DIG_RX_LBERT_ERR,Pattern match error counter" newline bitfld.word 0x0 15. "OV14,If active multiply COUNT by 128. If OV14=1 and COUNT=2^15-1 signals overflow of counter (2 reads needed to read value)" "0,1" newline hexmask.word 0x0 0.--14. 1. "COUNT,A read of this register or a sync of the PM resets the error count. Current error count If OV14 field is active then multiply count by 128 (2 reads needed to read value)" group.word 0x414C++0x1 line.word 0x0 "LANE0_DIG_RX_CDR_CDR_CTL_0,Control bits for receiver in recovered domain" newline hexmask.word.byte 0x0 11.--15. 1. "RESERVED_15_11,Reserved for Future use" newline hexmask.word.byte 0x0 7.--10. 1. "DTB_SEL,Select to drive various signals onto the dtb 0 - disabled 1 - rx_pr_stable rx_afe_stable from rx_ana_ctl 2 - com_good com_bad from rx_align 3 - shift_in_prog ana_odd_data from rx_align 4 - 2 msb's of XAUI align FSM state 5 - 2 lsb's of XAUI.." newline bitfld.word 0x0 6. "ALWAYS_REALIGN,Realign on any misaligned comma" "0,1" newline bitfld.word 0x0 5. "PHDET_EN_PR_MODE,Enable partial response phase detector mode" "0,1" newline bitfld.word 0x0 4. "PHDET_POL,Reverse polarity of phase error" "0,1" newline bitfld.word 0x0 2.--3. "PHDET_EDGE,Edges to use for phase detection. 10 - Use both edges 01 - Use rising edges only 11 - Use falling edges only 00 - Ignore all edges" "Ignore all edges,Use rising edges only,?,?" newline bitfld.word 0x0 0.--1. "PHDET_EN,Enable phase detector. top bit is odd slicers bottom is even" "0,1,2,3" group.word 0x4150++0x1 line.word 0x0 "LANE0_DIG_RX_CDR_CDR_CTL_1,CDR Control Register #1" newline hexmask.word.byte 0x0 10.--15. 1. "SSC_OFF_CNT1,When SSC mode is disabled the 12-bit word count in gain stage 1 is: (SSC_OFF_CNT1 * 4) in 20b mode (SSC_OFF_CNT1 * 5) in 16b mode" newline hexmask.word 0x0 0.--9. 1. "SSC_OFF_CNT0,When SSC mode is disabled the 12-bit word count in gain stage 0 is: (SSC_OFF_CNT0 * 4) in 20b mode (SSC_OFF_CNT0 * 5) in 16b mode" group.word 0x4154++0x1 line.word 0x0 "LANE0_DIG_RX_CDR_CDR_CTL_2,CDR Control Register #2" newline hexmask.word.byte 0x0 9.--15. 1. "SSC_ON_CNT1,When SSC mode is enabled the 12-bit word count in gain stage 1 is: (SSC_ON_CNT1 * 8) in 20b mode (SSC_ON_CNT1 * 10) in 16b mode" newline hexmask.word 0x0 0.--8. 1. "SSC_ON_CNT0,When SSC mode is enabled the 12-bit word count in gain stage 0 is: (SSC_ON_CNT0 * 8) in 20b mode (SSC_ON_CNT0 * 10) in 16b mode" group.word 0x4158++0x1 line.word 0x0 "LANE0_DIG_RX_CDR_CDR_CTL_3,CDR Control Register #3" newline bitfld.word 0x0 13.--15. "FRUG_OVRD_VALUE,Override value for FRUG (frequency update gain) 3'h0 - 0 3'h1 - 1/16 LSB/update 3'h2 - 1/8 LSB/update 3'h3 - 1/4 LSB/update 3'h4 - 1/2 LSB/update 3'h5 - 1 LSB/update 3'h6 - 2 LSB/update 3'h7 - 4 LSB/update" "0,1,2,3,4,5,6,7" newline bitfld.word 0x0 10.--12. "PHUG_OVRD_VALUE,Override value for PHUG (phase update gain) 3'h0 - 0 3'h1 - 1000 ppm 3'h2 - 2000 ppm 3'h3 - 3000 ppm 3'h4 - 4000 ppm 3'h5 - 5000 ppm 3'h6 - 6000 ppm 3'h7 - 7000 ppm" "0,1,2,3,4,5,6,7" newline bitfld.word 0x0 9. "OVRD_DPLL_GAIN,Override PHUG and FRUG values" "0,1" newline bitfld.word 0x0 6.--8. "SSC_OFF_FRUG0,When SSC mode is disabled the frug value in gain stage 0 is SSC_OFF_FRUG0" "0,1,2,3,4,5,6,7" newline bitfld.word 0x0 3.--5. "SSC_OFF_PHUG1,When SSC mode is disabled the phug value in gain stage 1 is SSC_OFF_PHUG1" "0,1,2,3,4,5,6,7" newline bitfld.word 0x0 0.--2. "SSC_OFF_PHUG0,When SSC mode is disabled the phug value in gain stage 0 is SSC_OFF_PHUG0" "0,1,2,3,4,5,6,7" group.word 0x415C++0x1 line.word 0x0 "LANE0_DIG_RX_CDR_CDR_CTL_4,CDR Control Register #4" newline rbitfld.word 0x0 15. "RESERVED_15_15,Reserved for Future use" "0,1" newline bitfld.word 0x0 12.--14. "SSC_ON_PHUG1,When SSC mode is enabled the phug value in gain stage 1 is SSC_ON_PHUG1" "0,1,2,3,4,5,6,7" newline bitfld.word 0x0 9.--11. "SSC_ON_PHUG0,When SSC mode is enabled the phug value in gain stage 0 is SSC_ON_PHUG0" "0,1,2,3,4,5,6,7" newline bitfld.word 0x0 6.--8. "SSC_ON_FRUG1,When SSC mode is enabled the frug value in gain stage 1 is SSC_ON_FRUG1" "0,1,2,3,4,5,6,7" newline bitfld.word 0x0 3.--5. "SSC_ON_FRUG0,When SSC mode is enabled the frug value in gain stage 0 is SSC_ON_FRUG0" "0,1,2,3,4,5,6,7" newline bitfld.word 0x0 0.--2. "SSC_OFF_FRUG1,When SSC mode is disabled the frug value in gain stage 1 is SSC_OFF_FRUG1" "0,1,2,3,4,5,6,7" rgroup.word 0x4160++0x1 line.word 0x0 "LANE0_DIG_RX_CDR_STAT,Current output values to dpll (phug. frug)" newline hexmask.word 0x0 6.--15. 1. "RESERVED_15_6,Reserved for Future use" newline bitfld.word 0x0 3.--5. "FRUG_VALUE,NOTES: Current value for dpll_frug[2:0]" "0,1,2,3,4,5,6,7" newline bitfld.word 0x0 0.--2. "PHUG_VALUE,NOTES: Current value for dpll_phug[2:0]" "0,1,2,3,4,5,6,7" group.word 0x4164++0x1 line.word 0x0 "LANE0_DIG_RX_DPLL_FREQ,Current frequency integrator value." newline rbitfld.word 0x0 14.--15. "RESERVED_15_14,Reserved for Future use" "0,1,2,3" newline hexmask.word 0x0 0.--13. 1. "VAL,Freq is 125*VAL ppm from the reference (2 reads needed to read value)" group.word 0x4168++0x1 line.word 0x0 "LANE0_DIG_RX_DPLL_FREQ_BOUND_0,Frequency Bounds for incoming data stream #0" newline hexmask.word.byte 0x0 11.--15. 1. "RESERVED_15_11,Reserved for Future use" newline hexmask.word 0x0 1.--10. 1. "UPPER_FREQ_BOUND,Upper frequency bound in terms of LSBs of the integral control code" newline bitfld.word 0x0 0. "FREQ_BOUND_EN,Enable the frequency bounds feature" "0,1" group.word 0x416C++0x1 line.word 0x0 "LANE0_DIG_RX_DPLL_FREQ_BOUND_1,Frequency Bounds for incoming data stream #1" newline hexmask.word.byte 0x0 10.--15. 1. "RESERVED_15_10,Reserved for Future use" newline hexmask.word 0x0 0.--9. 1. "LOWER_FREQ_BOUND,Lower frequency bound in terms of LSBs of the integral control code" group.word 0x4180++0x1 line.word 0x0 "LANE0_DIG_RX_ADPTCTL_ADPT_CFG_0,Adaptation Configuration Register #0" newline bitfld.word 0x0 15. "ADPT_CLK_DIV4_EN,Set the adaptation clock to be divided by 4 (default is div2)" "0,1" newline bitfld.word 0x0 14. "START_ASM1,Start adaptation state machine #1 (VGA CTLE DFE EYEH) This register-bit is self-clearing" "0,1" newline hexmask.word.byte 0x0 10.--13. 1. "N_TGG_ASM1,Number of toggle loop iterations for ASM1" newline hexmask.word 0x0 0.--9. 1. "N_TOP_ASM1,Number of top level loop iterations for ASM1" group.word 0x4184++0x1 line.word 0x0 "LANE0_DIG_RX_ADPTCTL_ADPT_CFG_1,Adaptation Configuration Register #1" newline hexmask.word.byte 0x0 12.--15. 1. "RESERVED_15_12,Reserved for Future use" newline bitfld.word 0x0 11. "CTLE_POLE_OVRD_EN,Override CTLE pole value (only valid if adaptation is run)" "0,1" newline bitfld.word 0x0 8.--10. "CTLE_POLE_OVRD_VAL,CTLE Pole override value to load at start of adaptation" "0,1,2,3,4,5,6,7" newline bitfld.word 0x0 7. "FAST_AFE_DFE_SETTLE,Enable fast AFE and DFE settling time (simulation only)" "0,1" newline hexmask.word.byte 0x0 0.--6. 1. "N_WAIT_ASM1,Number of wait cycles for Adaptation SM #1" group.word 0x4188++0x1 line.word 0x0 "LANE0_DIG_RX_ADPTCTL_ADPT_CFG_2,Adaptation Configuration Register #2" newline hexmask.word.byte 0x0 10.--15. 1. "RESERVED_15_10,Reserved for Future use" newline hexmask.word.byte 0x0 5.--9. 1. "TGG_PTTRN_1,Pattern for the second toggle loop Error slicer is moved upward by Data tap1 if this pattern is matched" newline hexmask.word.byte 0x0 0.--4. 1. "TGG_PTTRN_0,Pattern for the first toggle loop Error slicer is moved downward by Data tap1 if this pattern is matched" group.word 0x418C++0x1 line.word 0x0 "LANE0_DIG_RX_ADPTCTL_ADPT_CFG_3,Adaptation Configuration Register #3" newline bitfld.word 0x0 15. "ESL_TWICE_DSL,Assert if error slicer has twice the voltage range as the data slicer (for the same 8 bits)." "0,1" newline bitfld.word 0x0 14. "TGG_EN,Enable toggling of the error slicer" "0,1" newline bitfld.word 0x0 13. "EYEHO_EN,Enable eye height measurement using odd error slicer" "0,1" newline bitfld.word 0x0 12. "EYEHE_EN,Enable eye height measurement using even error slicer" "0,1" newline hexmask.word.byte 0x0 7.--11. 1. "DFE_EN,Enable DFE adaptation for taps 5-1" newline bitfld.word 0x0 6. "ATT_EN,Enable ATT adaptation" "0,1" newline bitfld.word 0x0 5. "VGA_EN,Enable VGA adaptation" "0,1" newline hexmask.word.byte 0x0 0.--4. 1. "CTLE_EN,Enable CTLE boost adaptation The five bits determine which correlators are used to adapt the CTLE" repeat 2. (list 0x4 0x5 )(list 0x0 0x4 ) group.word ($2+0x4190)++0x1 line.word 0x0 "LANE0_DIG_RX_ADPTCTL_ADPT_CFG_$1,Adaptation Configuration Register #4" newline hexmask.word.byte 0x0 12.--15. 1. "DFE2_TH,DFE Tap2 correlation decision threshold (2^N-1)" newline hexmask.word.byte 0x0 8.--11. 1. "DFE1_TH,DFE Tap1 correlation decision threshold (2^N-1)" newline hexmask.word.byte 0x0 4.--7. 1. "VGA_TH,VGA correlation decision threshold (2^N-1) During eye height measurement the VGA_TH is repurporsed for error slicer updates." newline hexmask.word.byte 0x0 0.--3. 1. "CTLE_TH,CTLE correlation decision threshold (2^N-1)" repeat.end group.word 0x4198++0x1 line.word 0x0 "LANE0_DIG_RX_ADPTCTL_ADPT_CFG_6,Adaptation Configuration Register #6" newline bitfld.word 0x0 13.--15. "ATT_LOW_TH,ATT low threshold" "0,1,2,3,4,5,6,7" newline bitfld.word 0x0 12. "VGA_SAT_CNT_STICKY,If deasserted then VGA saturation counts must be consecutive to change ATT" "0,1" newline bitfld.word 0x0 9.--11. "VGA_SAT_CNT,VGA saturation count" "0,1,2,3,4,5,6,7" newline bitfld.word 0x0 6.--8. "ATT_MU,ATT gain code update gain (2^N)" "0,1,2,3,4,5,6,7" newline bitfld.word 0x0 3.--5. "VGA_MU,VGA gain code update gain (2^N) During eye height measurement the VGA_MU is repurporsed for error slicer updates." "0,1,2,3,4,5,6,7" newline bitfld.word 0x0 0.--2. "CTLE_MU,CTLE Boost code update gain (2^N)" "0,1,2,3,4,5,6,7" group.word 0x419C++0x1 line.word 0x0 "LANE0_DIG_RX_ADPTCTL_ADPT_CFG_7,Adaptation Configuration Register #7" newline rbitfld.word 0x0 15. "RESERVED_15_15,Reserved for Future use" "0,1" newline hexmask.word.byte 0x0 10.--14. 1. "VGA_LEV_LOW,VGA level low saturation limit" newline hexmask.word.byte 0x0 5.--9. 1. "VGA_LEV_HIGH,VGA level high saturation limit" newline hexmask.word.byte 0x0 0.--4. 1. "VGA_MIN_SAT,VGA minimum saturation limit" group.word 0x41A0++0x1 line.word 0x0 "LANE0_DIG_RX_ADPTCTL_ADPT_CFG_8,Adaptation Configuration Register #8" newline rbitfld.word 0x0 15. "RESERVED_15_15,Reserved for Future use" "0,1" newline bitfld.word 0x0 12.--14. "DFE5_MU,DFE tap5 code update gain (2^N)" "0,1,2,3,4,5,6,7" newline bitfld.word 0x0 9.--11. "DFE4_MU,DFE tap4 code update gain (2^N)" "0,1,2,3,4,5,6,7" newline bitfld.word 0x0 6.--8. "DFE3_MU,DFE tap3 code update gain (2^N)" "0,1,2,3,4,5,6,7" newline bitfld.word 0x0 3.--5. "DFE2_MU,DFE tap2 code update gain (2^N)" "0,1,2,3,4,5,6,7" newline bitfld.word 0x0 0.--2. "DFE1_MU,DFE tap1 code update gain (2^N)" "0,1,2,3,4,5,6,7" group.word 0x41A4++0x1 line.word 0x0 "LANE0_DIG_RX_ADPTCTL_ADPT_CFG_9,Adaptation Configuration Register #9" newline hexmask.word.byte 0x0 8.--15. 1. "ERR_SLO_ADPT_INIT,The error odd slicer is initialized to this value at the start of a new adaptation request." newline hexmask.word.byte 0x0 0.--7. 1. "ERR_SLE_ADPT_INIT,The error even slicer is initialized to this value at the start of a new adaptation request." group.word 0x41A8++0x1 line.word 0x0 "LANE0_DIG_RX_ADPTCTL_RST_ADPT_CFG,Reset Adaptation Configuration Register" newline hexmask.word 0x0 5.--15. 1. "RESERVED_15_5,Reserved for Future use" newline bitfld.word 0x0 4. "RST_ADPT_TAP1,Reset Data Tap1 when turning off DFE adaptation (Taps 2-5 are always turned off when DFE adaptation is turned off)" "0,1" newline bitfld.word 0x0 3. "RST_ADPT_CTLE_POLE,Reset CTLE Pole when turning off AFE adaptation" "0,1" newline bitfld.word 0x0 2. "RST_ADPT_CTLE_BOOST,Reset CTLE Boost when turning off AFE adaptation" "0,1" newline bitfld.word 0x0 1. "RST_ADPT_VGA,Reset VGA when turning off AFE adaptation" "0,1" newline bitfld.word 0x0 0. "RST_ADPT_ATT,Reset ATT when turning off AFE adaptation" "0,1" rgroup.word 0x41AC++0x1 line.word 0x0 "LANE0_DIG_RX_ADPTCTL_ATT_STATUS,Value of ATT Adaptation code" newline hexmask.word.byte 0x0 9.--15. 1. "RESERVED_15_9,Reserved for Future use" newline bitfld.word 0x0 8. "ASM1_DON,Asserts when Adaptation state machine #1 is done" "0,1" newline hexmask.word.byte 0x0 0.--7. 1. "ATT_ADPT_CODE,Value of ATT adaptation code" rgroup.word 0x41B0++0x1 line.word 0x0 "LANE0_DIG_RX_ADPTCTL_VGA_STATUS,Value of VGA Adaptation code" newline hexmask.word.byte 0x0 11.--15. 1. "RESERVED_15_11,Reserved for Future use" newline bitfld.word 0x0 10. "ASM1_DONE,Asserts when Adaptation state machine #1 is done" "0,1" newline hexmask.word 0x0 0.--9. 1. "VGA_ADPT_CODE,Value of VGA adaptation code" rgroup.word 0x41B4++0x1 line.word 0x0 "LANE0_DIG_RX_ADPTCTL_CTLE_STATUS,Value of CTLE Adaptation code" newline bitfld.word 0x0 14.--15. "RESERVED_15_14,Reserved for Future use" "0,1,2,3" newline bitfld.word 0x0 13. "ASM1_DONE,Asserts when Adaptation state machine #1 is done" "0,1" newline bitfld.word 0x0 10.--12. "CTLE_POLE_ADPT_CODE,Value of CTLE Pole adaptation code" "0,1,2,3,4,5,6,7" newline hexmask.word 0x0 0.--9. 1. "CTLE_BOOST_ADPT_CODE,Value of CTLE Boost adaptation code" rgroup.word 0x41B8++0x1 line.word 0x0 "LANE0_DIG_RX_ADPTCTL_DFE_TAP1_STATUS,Value of DFE Tap1 Adaptation code" newline bitfld.word 0x0 14.--15. "RESERVED_15_14,Reserved for Future use" "0,1,2,3" newline bitfld.word 0x0 13. "ASM1_DONE,Asserts when Adaptation state machine #1 is done" "0,1" newline hexmask.word 0x0 0.--12. 1. "DFE_TAP1_ADPT_CODE,Value of DFE tap1 adaptation code" rgroup.word 0x41BC++0x1 line.word 0x0 "LANE0_DIG_RX_ADPTCTL_DFE_TAP2_STATUS,Value of DFE Tap2 Adaptation code" newline bitfld.word 0x0 13.--15. "RESERVED_15_13,Reserved for Future use" "0,1,2,3,4,5,6,7" newline bitfld.word 0x0 12. "ASM1_DONE,Asserts when Adaptation state machine #1 is done" "0,1" newline hexmask.word 0x0 0.--11. 1. "DFE_TAP2_ADPT_CODE,Value of DFE tap2 adaptation code" rgroup.word 0x41C0++0x1 line.word 0x0 "LANE0_DIG_RX_ADPTCTL_DFE_TAP3_STATUS,Value of DFE Tap3 Adaptation code" newline bitfld.word 0x0 13.--15. "RESERVED_15_13,Reserved for Future use" "0,1,2,3,4,5,6,7" newline bitfld.word 0x0 12. "ASM1_DONE,Asserts when Adaptation state machine #1 is done" "0,1" newline hexmask.word 0x0 0.--11. 1. "DFE_TAP3_ADPT_CODE,Value of DFE tap3 adaptation code" rgroup.word 0x41C4++0x1 line.word 0x0 "LANE0_DIG_RX_ADPTCTL_DFE_TAP4_STATUS,Value of DFE Tap4 Adaptation code" newline bitfld.word 0x0 13.--15. "RESERVED_15_13,Reserved for Future use" "0,1,2,3,4,5,6,7" newline bitfld.word 0x0 12. "ASM1_DONE,Asserts when Adaptation state machine #1 is done" "0,1" newline hexmask.word 0x0 0.--11. 1. "DFE_TAP4_ADPT_CODE,Value of DFE tap4 adaptation code" rgroup.word 0x41C8++0x1 line.word 0x0 "LANE0_DIG_RX_ADPTCTL_DFE_TAP5_STATUS,Value of DFE Tap5 Adaptation code" newline bitfld.word 0x0 13.--15. "RESERVED_15_13,Reserved for Future use" "0,1,2,3,4,5,6,7" newline bitfld.word 0x0 12. "ASM1_DONE,Asserts when Adaptation state machine #1 is done" "0,1" newline hexmask.word 0x0 0.--11. 1. "DFE_TAP5_ADPT_CODE,Value of DFE tap5 adaptation code" group.word 0x41CC++0x1 line.word 0x0 "LANE0_DIG_RX_ADPTCTL_DFE_DATA_EVEN_VDAC_OFST,Offset values for RX DFE Data Even vDAC" newline hexmask.word.byte 0x0 8.--15. 1. "RESERVED_15_8,Reserved for Future use" newline hexmask.word.byte 0x0 0.--7. 1. "DFE_DATA_EVEN_VDAC_OFST,Offset value for DFE Data Even vDAC" group.word 0x41D0++0x1 line.word 0x0 "LANE0_DIG_RX_ADPTCTL_DFE_DATA_ODD_VDAC_OFST,Offset values for RX DFE Data Odd vDAC" newline hexmask.word.byte 0x0 8.--15. 1. "RESERVED_15_8,Reserved for Future use" newline hexmask.word.byte 0x0 0.--7. 1. "DFE_DATA_ODD_VDAC_OFST,Offset value for DFE Data Odd vDAC" group.word 0x41D4++0x1 line.word 0x0 "LANE0_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN,Sets values for RX SLICER CTRL EVEN signals going to ANA" newline hexmask.word 0x0 4.--15. 1. "RESERVED_15_4,Reserved for Future use" newline hexmask.word.byte 0x0 0.--3. 1. "RX_ANA_SLICER_CTRL_E,Value for rx_ana_slicer_ctrl_e[3:0]" group.word 0x41D8++0x1 line.word 0x0 "LANE0_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD,Sets values for RX SLICER CTRL ODD signals going to ANA" newline hexmask.word 0x0 4.--15. 1. "RESERVED_15_4,Reserved for Future use" newline hexmask.word.byte 0x0 0.--3. 1. "RX_ANA_SLICER_CTRL_O,Value for rx_ana_slicer_ctrl_o[3:0]" group.word 0x41DC++0x1 line.word 0x0 "LANE0_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST,Offset values for RX DFE Error Even vDAC" newline hexmask.word.byte 0x0 8.--15. 1. "RESERVED_15_8,Reserved for Future use" newline hexmask.word.byte 0x0 0.--7. 1. "DFE_ERROR_EVEN_VDAC_OFST,Offset value for DFE Error Even vDAC" group.word 0x41E0++0x1 line.word 0x0 "LANE0_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST,Offset values for RX DFE Error Odd vDAC" newline hexmask.word.byte 0x0 8.--15. 1. "RESERVED_15_8,Reserved for Future use" newline hexmask.word.byte 0x0 0.--7. 1. "DFE_ERROR_ODD_VDAC_OFST,Offset value for DFE Error Odd vDAC" rgroup.word 0x41E4++0x1 line.word 0x0 "LANE0_DIG_RX_ADPTCTL_ERROR_SLICER_LEVEL,Value of Error Slicer Level" newline hexmask.word.byte 0x0 8.--15. 1. "E_SLE_LVL,Even Error Slicer Level" newline hexmask.word.byte 0x0 0.--7. 1. "E_SLO_LVL,Odd Error Slicer Level" group.word 0x41E8++0x1 line.word 0x0 "LANE0_DIG_RX_ADPTCTL_ADPT_RESET,Adaptation reset register" newline hexmask.word 0x0 1.--15. 1. "RESERVED_15_1,Reserved for Future use" newline bitfld.word 0x0 0. "RESET_ASM1,Resets adaptation state machine (ASM1) as well as the stats capture block. This is a self-clearing bit and requires re-start of ASM1." "0,1" group.word 0x4200++0x1 line.word 0x0 "LANE0_DIG_RX_STAT_LD_VAL_1,Stat load value for the sample counter #1" newline bitfld.word 0x0 15. "SC1_START,Start sample counter #1 This is a self-clearing bit" "0,1" newline hexmask.word 0x0 0.--14. 1. "SC1_LD_VAL,Sample counter #1 load value" group.word 0x4204++0x1 line.word 0x0 "LANE0_DIG_RX_STAT_DATA_MSK,Stat data mask bits [15:0]" newline hexmask.word 0x0 0.--15. 1. "DATA_MSK_15_0,Value of data_msk_r[15:0]" group.word 0x4208++0x1 line.word 0x0 "LANE0_DIG_RX_STAT_MATCH_CTL0,Stat match controls register #0" newline bitfld.word 0x0 14.--15. "SCOPE_DLY,# of clock cycle delays on scope_data_rx_clk An additional MSB is added in SCOPE_DLY_2" "0,1,2,3" newline hexmask.word.byte 0x0 10.--13. 1. "DATA_MSK_19_16,Value of data_msk_r[19:16]" newline hexmask.word.byte 0x0 5.--9. 1. "PTTRN_CR1A_4_0,Value of pattern A for 1st correlator (bits 4:0)" newline hexmask.word.byte 0x0 0.--4. 1. "PTTRN_MSK_CR1A_4_0,Value of pattern A mask for 1st correlator (bits 4:0)" group.word 0x420C++0x1 line.word 0x0 "LANE0_DIG_RX_STAT_MATCH_CTL1,Stat match controls register #1" newline hexmask.word.byte 0x0 12.--15. 1. "RESERVED_15_12,Reserved for Future use" newline bitfld.word 0x0 11. "PTTRN_CR1A_ADPT_EN,Enable ORing of adapation pattern with pattern CR1A" "0,1" newline hexmask.word.byte 0x0 6.--10. 1. "PTTRN_CR1B_4_0,Value of pattern B for 1st correlator (bits 4:0)" newline hexmask.word.byte 0x0 1.--5. 1. "PTTRN_MSK_CR1B_4_0,Value of pattern B mask for 1st correlator (bits 4:0)" newline bitfld.word 0x0 0. "PTTRN_CR1B_EN,Enable pattern B matching for 1st correlator" "0,1" group.word 0x4210++0x1 line.word 0x0 "LANE0_DIG_RX_STAT_STAT_CTL0,Stat controls register #0" newline bitfld.word 0x0 15. "SKIP_EN,Value of skip_en_r" "0,1" newline bitfld.word 0x0 14. "SC_TIMER_MODE,Sample counter operation mode 0x0 - counts number of matched samples 0x1 - counts clock cycles (i.e. a timer)" "counts number of matched samples,counts clock cycles" newline bitfld.word 0x0 13. "STAT_RXCLK_SEL,Select stat clock 0x0 - ref_range_clk 0x1 - rx_dig_clk (i.e. rx dword clk) Before changing stat_rxclk_sel_r from 1->0 the rx_dig_clk must be active (i.e. enabled)" "ref_range_clk,rx_dig_clk" newline bitfld.word 0x0 10.--12. "STAT_SRC_SEL,Select stat source input 0x0 - {20{rx_cal_result}} 0x1 - {{20{scope_data_rxclk_dly_s01}} {20{scope_data_rxclk_dly}}} 0x2 - rx_phase[39:0] 0x3 - rx_error[39:0] 0x4 - rx_data[39:0] 0x5 - rx_phdir[39:0] 0x6 - 40'hFF_FFFF_FFFF" "?,?,rx_phase[39:0],rx_error[39:0],rx_data[39:0],rx_phdir[39:0],?,?" newline hexmask.word.byte 0x0 6.--9. 1. "STAT_SHFT_SEL,Select stat source shift value 0x0 - Correlate N-1 -> N+3 (use N for offset calibration) 0x1 - Correlate N+1 -> N+5 (for taps1-5) 0x2 - Correlate N+6 -> N+10 0x3 - Correlate N+11 -> N+15 0x4 - Correlate N+16 -> N+20 0x5 - Correlate N+21 ->.." newline bitfld.word 0x0 5. "CORR_MODE_EN,Enable correlation mode" "0,1" newline bitfld.word 0x0 3.--4. "CORR_SRC_SEL,Select correlation input source 0x0 - rx_error[39:0] 0x1 - rx_phase[39:0] 0x2 - {{20{scope_data_rxclk_dly_s01}} {20{scope_data_rxclk_dly}}} 0x3 - No correlation" "rx_error[39:0],rx_phase[39:0],?,No correlation" newline bitfld.word 0x0 2. "CORR_SHFT_SEL,Select shift for phase. 0:none 1:>>1" "none,?" newline bitfld.word 0x0 1. "CORR_SHFT_SEL_VGA,Select shift for error going to VGA. 0:none 1:>>1" "none,?" newline bitfld.word 0x0 0. "RESERVED_0,Reserved bit" "0,1" group.word 0x4214++0x1 line.word 0x0 "LANE0_DIG_RX_STAT_STAT_CTL1,Stat controls register #1" newline bitfld.word 0x0 14.--15. "VLD_CTL,Gating configuration of stats collection 0x0 - ignore both cdr_valid and rx_valid 0x1 - gate stats collection with cdr_valid 0x2 - gate stats collection with rx_valid 0x3 - ignore both cdr_valid and rx_valid" "ignore both cdr_valid and rx_valid,gate stats collection with cdr_valid,gate stats collection with rx_valid,ignore both cdr_valid and rx_valid" newline bitfld.word 0x0 13. "VLD_LOSS_CLR,Clearing of stats collection upon loss of valid 0x0 - hold sample and stat counters 0x1 - clear sample and stat counters" "hold sample and stat counters,clear sample and stat counters" newline bitfld.word 0x0 11.--12. "DATA_DLY_SEL,# of clock cycle delays on rx_data[19:0] An additional MSB is added in DATA_DLY_SEL_2" "0,1,2,3" newline bitfld.word 0x0 10. "STAT_CLK_EN,Clock gate enable for stat clock" "0,1" newline bitfld.word 0x0 9. "SC_PAUSE,Pause the sample counter and stat counters" "0,1" newline bitfld.word 0x0 7.--8. "RESERVED_8_7,Reserved bits" "0,1,2,3" newline bitfld.word 0x0 6. "STAT_CNT_6_EN,Enable for stat counter 6" "0,1" newline bitfld.word 0x0 5. "STAT_CNT_5_EN,Enable for stat counter 5" "0,1" newline bitfld.word 0x0 4. "STAT_CNT_4_EN,Enable for stat counter 4" "0,1" newline bitfld.word 0x0 3. "STAT_CNT_3_EN,Enable for stat counter 3 Only counter to be enabled by default since used for offset calibration" "0,1" newline bitfld.word 0x0 2. "STAT_CNT_2_EN,Enable for stat counter 2" "0,1" newline bitfld.word 0x0 1. "STAT_CNT_1_EN,Enable for stat counter 1" "0,1" newline bitfld.word 0x0 0. "STAT_CNT_0_EN,Enable for stat counter 0" "0,1" rgroup.word 0x4218++0x1 line.word 0x0 "LANE0_DIG_RX_STAT_SMPL_CNT1,Sample Counter #1 Status" newline bitfld.word 0x0 15. "SMPL_CNT1_DONE,Status of sample counter #1" "0,1" newline hexmask.word 0x0 0.--14. 1. "SMPL_CNT1,Current value of sample counter #1" rgroup.word 0x421C++0x1 line.word 0x0 "LANE0_DIG_RX_STAT_STAT_CNT_0,Stat Counter 0 Status" newline bitfld.word 0x0 15. "SMPL_CNT1_DONE,Status of sample counter #1" "0,1" newline hexmask.word 0x0 0.--14. 1. "STAT_CNT_0,Current value of stat counter #0" rgroup.word 0x4220++0x1 line.word 0x0 "LANE0_DIG_RX_STAT_STAT_CNT_1,Stat Counter 1 Status" newline bitfld.word 0x0 15. "SMPL_CNT1_DONE,Status of sample counter #1" "0,1" newline hexmask.word 0x0 0.--14. 1. "STAT_CNT_1,Current value of stat counter #1" rgroup.word 0x4224++0x1 line.word 0x0 "LANE0_DIG_RX_STAT_STAT_CNT_2,Stat Counter 2 Status" newline bitfld.word 0x0 15. "SMPL_CNT1_DONE,Status of sample counter #1" "0,1" newline hexmask.word 0x0 0.--14. 1. "STAT_CNT_2,Current value of stat counter #2" rgroup.word 0x4228++0x1 line.word 0x0 "LANE0_DIG_RX_STAT_STAT_CNT_3,Stat Counter 3 Status" newline bitfld.word 0x0 15. "SMPL_CNT1_DONE,Status of sample counter #1" "0,1" newline hexmask.word 0x0 0.--14. 1. "STAT_CNT_3,Current value of stat counter #3" rgroup.word 0x422C++0x1 line.word 0x0 "LANE0_DIG_RX_STAT_STAT_CNT_4,Stat Counter 4 Status" newline bitfld.word 0x0 15. "SMPL_CNT1_DONE,Status of sample counter #1" "0,1" newline hexmask.word 0x0 0.--14. 1. "STAT_CNT_4,Current value of stat counter #4" rgroup.word 0x4230++0x1 line.word 0x0 "LANE0_DIG_RX_STAT_STAT_CNT_5,Stat Counter 5 Status" newline bitfld.word 0x0 15. "SMPL_CNT1_DONE,Status of sample counter #1" "0,1" newline hexmask.word 0x0 0.--14. 1. "STAT_CNT_5,Current value of stat counter #5" rgroup.word 0x4234++0x1 line.word 0x0 "LANE0_DIG_RX_STAT_STAT_CNT_6,Stat Counter 6 Status" newline bitfld.word 0x0 15. "SMPL_CNT1_DONE,Status of sample counter #1" "0,1" newline hexmask.word 0x0 0.--14. 1. "STAT_CNT_6,Current value of stat counter #6" group.word 0x4238++0x1 line.word 0x0 "LANE0_DIG_RX_STAT_CAL_COMP_CLK_CTL,Calibration Comparator Control" newline hexmask.word 0x0 6.--15. 1. "RESERVED_15_6,Reserved for Future use" newline bitfld.word 0x0 3.--5. "REF_DIV_CNT,Ref range clock count (e.g. 5'd3 = 4 ref_range cycles)" "0,1,2,3,4,5,6,7" newline bitfld.word 0x0 0.--2. "PRECHRGE_CNT,Precharge Count (e.g. 5'd1 = 2 ref_range cycles)" "0,1,2,3,4,5,6,7" repeat 4. (list 0x2 0x3 0x4 0x5 )(list 0x0 0x4 0x8 0xC ) group.word ($2+0x423C)++0x1 line.word 0x0 "LANE0_DIG_RX_STAT_MATCH_CTL$1,Stat match controls register #2" newline rbitfld.word 0x0 15. "RESERVED_15_15,Reserved for Future use" "0,1" newline hexmask.word 0x0 0.--14. 1. "PTTRN_CR1A_19_5,Value of pattern A for 1st correlator (bits 19:5)" repeat.end group.word 0x424C++0x1 line.word 0x0 "LANE0_DIG_RX_STAT_STAT_CTL2,Stat controls register #2" newline hexmask.word 0x0 2.--15. 1. "RESERVED_15_2,Reserved for Future use" newline bitfld.word 0x0 1. "SCOPE_DLY_2,Additional MSB bit for SCOPE_DLY to extend the delay range to 0->7" "0,1" newline bitfld.word 0x0 0. "DATA_DLY_SEL_2,Additional MSB bit for DATA_DLY_SEL to extend the delay range to 0->7" "0,1" group.word 0x4250++0x1 line.word 0x0 "LANE0_DIG_RX_STAT_STAT_STOP,Stat stop register" newline hexmask.word 0x0 1.--15. 1. "RESERVED_15_1,Reserved for Future use" newline bitfld.word 0x0 0. "SC1_STOP,Stop sample counters #1 and associated stat counters. This is a self-clearing bit and requires re-start of sample counter #1." "0,1" group.word 0x4280++0x1 line.word 0x0 "LANE0_DIG_ANA_TX_OVRD_OUT,Override values for TX signals going to ANA" newline bitfld.word 0x0 15. "TX_OVRD_EN,Enable override values for all outputs controlled by this register" "0,1" newline bitfld.word 0x0 14. "TX_RXDET_EN,Override value for tx_ana_rxdet_en" "0,1" newline bitfld.word 0x0 13. "TX_DIV4_EN,Override value for tx_ana_div4_en" "0,1" newline bitfld.word 0x0 12. "RESERVED," "0,1" newline bitfld.word 0x0 10.--11. "TX_ANA_DATA_RATE,Override value for tx_ana_data_rate" "0,1,2,3" newline bitfld.word 0x0 9. "TX_ANA_SERIAL_EN,Override value for tx_ana_serial_en" "0,1" newline bitfld.word 0x0 8. "TX_ANA_RESET,Override value for tx_ana_reset" "0,1" newline bitfld.word 0x0 7. "TX_ANA_MPLLB_CLK_EN,Override value for tx_ana_mpllb_clk_en" "0,1" newline bitfld.word 0x0 6. "TX_ANA_MPLLA_CLK_EN,Override value for tx_ana_mplla_clk_en" "0,1" newline bitfld.word 0x0 5. "TX_ANA_WORD_CLK_EN,Override value for tx_ana_word_clk_en" "0,1" newline bitfld.word 0x0 4. "TX_ANA_CLK_EN,Override value for tx_ana_clk_en" "0,1" newline bitfld.word 0x0 3. "TX_ANA_VCM_HOLD,Override value for tx_ana_vcm_hold" "0,1" newline bitfld.word 0x0 2. "TX_ANA_REFGEN_EN,Override value for tx_ana_refgen_en" "0,1" newline bitfld.word 0x0 1. "TX_ANA_DATA_EN,Override value for tx_ana_data_en" "0,1" newline bitfld.word 0x0 0. "TX_ANA_CLK_SHIFT,Override value for tx_ana_clk_shift" "0,1" group.word 0x4284++0x1 line.word 0x0 "LANE0_DIG_ANA_TX_TERM_CODE_OVRD_OUT,Override value for TX termination code going to ANA" newline hexmask.word.byte 0x0 12.--15. 1. "RESERVED_15_12,Reserved for Future use" newline bitfld.word 0x0 11. "TX_CLK_LB_EN,Override value for tx_ana_clk_lb_en (override enabled by TX_OVRD_EN)." "0,1" newline bitfld.word 0x0 10. "TX_TERM_OVRD_EN,Override enable for the tx_ana_term_code[9:0] signal" "0,1" newline hexmask.word 0x0 0.--9. 1. "TX_TERM_CODE,Overrides the tx_ana_term_code[9:0] signal" group.word 0x4288++0x1 line.word 0x0 "LANE0_DIG_ANA_TX_TERM_CODE_CLK_OVRD_OUT,Override value for TX termination code clocks going to ANA" newline hexmask.word 0x0 3.--15. 1. "RESERVED_15_3,Reserved for Future use" newline bitfld.word 0x0 2. "TX_TERM_CLK_SELF_CLEAR_DISABLE,Disable self-clearing for the tx_ana_term_up/dn_clk register" "0,1" newline bitfld.word 0x0 1. "TX_TERM_UP_CLK,Override for TX term UP clock This bit is self-clearing (4 cr_clks later)." "0,1" newline bitfld.word 0x0 0. "TX_TERM_DN_CLK,Override for TX term DN clock - This bit is self_clearing (4 cr_clks later)." "0,1" group.word 0x428C++0x1 line.word 0x0 "LANE0_DIG_ANA_TX_EQ_OVRD_OUT_0,Override values for TX EQ signals going to ANA register #0" newline bitfld.word 0x0 15. "TX_EQ_OVRD_EN,Override enable for tx eq signals" "0,1" newline hexmask.word 0x0 1.--14. 1. "TX_ANA_CTRL_ATTEN_13_0,Override value for tx_ana_ctrl_atten[13:0]" newline bitfld.word 0x0 0. "TX_ANA_LOAD_CLK,Override value for tx_ana_load_clk" "0,1" group.word 0x4290++0x1 line.word 0x0 "LANE0_DIG_ANA_TX_EQ_OVRD_OUT_1,Override values for TX EQ signals going to ANA register #1" newline hexmask.word 0x0 6.--15. 1. "RESERVED_15_6,Reserved for Future use" newline hexmask.word.byte 0x0 0.--5. 1. "TX_ANA_CTRL_ATTEN_19_14,Override value for tx_ana_ctrl_atten[19:14]" group.word 0x4294++0x1 line.word 0x0 "LANE0_DIG_ANA_TX_EQ_OVRD_OUT_2,Override values for TX EQ signals going to ANA register #2" newline rbitfld.word 0x0 13.--15. "RESERVED_15_13,Reserved for Future use" "0,1,2,3,4,5,6,7" newline hexmask.word.byte 0x0 7.--12. 1. "TX_ANA_CTRL_PRE,Override value for tx_ana_ctrl_pre[5:0]" newline hexmask.word.byte 0x0 0.--6. 1. "RESERVED," group.word 0x4298++0x1 line.word 0x0 "LANE0_DIG_ANA_TX_EQ_OVRD_OUT_3,Override values for TX EQ signals going to ANA register #3" newline hexmask.word.byte 0x0 8.--15. 1. "RESERVED_15_8,Reserved for Future use" newline hexmask.word.byte 0x0 0.--7. 1. "TX_ANA_CTRL_POST,Override value for tx_ana_ctrl_post[7:0]" group.word 0x429C++0x1 line.word 0x0 "LANE0_DIG_ANA_RX_CTL_OVRD_OUT,Override values for RX control signals going to ANA" newline hexmask.word.byte 0x0 9.--15. 1. "RESERVED_15_9,Reserved for Future use" newline bitfld.word 0x0 8. "RX_CTL_OVRD_EN,Enable override values for outputs [8-0] below" "0,1" newline bitfld.word 0x0 7. "RX_LBK_CLK_EN,Override value for rx_ana_loopback_clk_en" "0,1" newline bitfld.word 0x0 6. "RX_ANA_ADAPTATION_EN,Override value for rx_ana_adaptation_en" "0,1" newline bitfld.word 0x0 5. "RX_ANA_DFE_TAPS_EN,Override value for rx_ana_dfe_taps_en" "0,1" newline bitfld.word 0x0 4. "RX_ANA_DIV4_EN,Override value for rx_ana_div4_en" "0,1" newline bitfld.word 0x0 3. "RX_ANA_WORD_CLK_EN,Override value for rx_ana_word_clk_en" "0,1" newline bitfld.word 0x0 1.--2. "RX_ANA_DATA_RATE,Override value for rx_ana_data_rate" "0,1,2,3" newline bitfld.word 0x0 0. "RESERVED," "0,1" group.word 0x42A0++0x1 line.word 0x0 "LANE0_DIG_ANA_RX_PWR_OVRD_OUT,Override values for RX PWR UP/DN signals going to ANA" newline hexmask.word.byte 0x0 8.--15. 1. "RESERVED_15_8,Reserved for Future use" newline bitfld.word 0x0 7. "RX_PWR_OVRD_EN,Enable override values for all outputs controlled by this register" "0,1" newline bitfld.word 0x0 6. "RX_ANA_DESERIAL_EN,Override value for rx_ana_deserial_en" "0,1" newline bitfld.word 0x0 5. "RX_ANA_CDR_EN,Override value for rx_ana_cdr_en" "0,1" newline bitfld.word 0x0 4. "RX_ANA_CLK_EN,Override value for rx_ana_clk_en" "0,1" newline bitfld.word 0x0 3. "RX_ANA_CLK_DCC_EN,Override value for rx_ana_clk_dcc_en" "0,1" newline bitfld.word 0x0 2. "RX_ANA_CLK_VREG_EN,Override value for rx_ana_clk_vreg_en" "0,1" newline bitfld.word 0x0 1. "RX_ANA_AFE_EN,Override value for rx_ana_afe_en" "0,1" newline bitfld.word 0x0 0. "RX_ANA_LOS_EN,Override value for rx_ana_los_en" "0,1" group.word 0x42A4++0x1 line.word 0x0 "LANE0_DIG_ANA_RX_VCO_OVRD_OUT_0,Override values for RX VCO signals going to ANA #0" newline bitfld.word 0x0 15. "RX_CDR_FREQ_TUNE_OVRD_EN,Enable override value for rx_ana_cdr_freq_tune" "0,1" newline bitfld.word 0x0 14. "RX_ANA_VCO_CNTR_CLK,Override value for rx_ana_vco_cntr_clk" "0,1" newline bitfld.word 0x0 13. "RX_ANA_VCO_CNTR_EN,Override value for rx_ana_vco_cntr_en" "0,1" newline hexmask.word 0x0 3.--12. 1. "RX_ANA_CDR_FREQ_TUNE,Override value for rx_ana_cdr_freq_tune" newline bitfld.word 0x0 2. "RX_VCO_CDR_OVRD_EN,Enable override values for cdr_vco_en and cdr_startup" "0,1" newline bitfld.word 0x0 1. "RX_ANA_CDR_STARTUP,Override value for rx_ana_cdr_startup" "0,1" newline bitfld.word 0x0 0. "RX_ANA_CDR_VCO_EN,Override value for rx_ana_cdr_vco_en" "0,1" repeat 2. (list 0x1 0x2 )(list 0x0 0x4 ) group.word ($2+0x42A8)++0x1 line.word 0x0 "LANE0_DIG_ANA_RX_VCO_OVRD_OUT_$1,Override values for RX VCO signals going to ANA #1" newline hexmask.word 0x0 2.--15. 1. "RESERVED_15_2,Reserved for Future use" newline bitfld.word 0x0 1. "RX_ANA_VCO_CNTR_PD,Override value for rx_ana_vco_cntr_pd" "0,1" newline bitfld.word 0x0 0. "RX_ANA_CDR_VCO_LOWFREQ,Override value for rx_ana_cdr_vco_lowfreq" "0,1" repeat.end group.word 0x42B0++0x1 line.word 0x0 "LANE0_DIG_ANA_RX_CAL,Sets values for RX CAL signals going to ANA register" newline bitfld.word 0x0 15. "RX_ANA_CAL_COMP_EN,Value for rx_ana_cal_comp_en" "0,1" newline bitfld.word 0x0 13.--14. "RX_ANA_CAL_MODE,Value for rx_ana_cal_mode[1:0] 00 Dual differential comparison ( [vip2 - vim2] greater than [vip1 - vim1] ) 01 Differential comparison on input2 (vip2 greater than vim2) 10 Single-ended comparison negative node to negative node (vim1.." "?,?,vim2] greater than [vip1,?" newline bitfld.word 0x0 12. "RX_ANA_SLICER_CAL_EN,Value for rx_ana_slicer_cal_en" "0,1" newline bitfld.word 0x0 11. "RESERVED," "0,1" newline bitfld.word 0x0 10. "RX_ANA_CAL_LPFBYP_EN,Value for rx_ana_cal_lpfbyp_en" "0,1" newline hexmask.word.byte 0x0 5.--9. 1. "RX_ANA_CAL_MUXB_SEL,Value for rx_ana_cal_muxb_sel[4:0]" newline hexmask.word.byte 0x0 0.--4. 1. "RX_ANA_CAL_MUXA_SEL,Value for rx_ana_cal_muxa_sel[4:0]" group.word 0x42B4++0x1 line.word 0x0 "LANE0_DIG_ANA_RX_DAC_CTRL,Sets values for RX DAC CTRL value going to ANA" newline hexmask.word.byte 0x0 8.--15. 1. "RESERVED_15_8,Reserved for Future use" newline hexmask.word.byte 0x0 0.--7. 1. "RX_ANA_CAL_DAC_CTRL,Value for rx_ana_cal_dac_ctrl[7:0]" group.word 0x42B8++0x1 line.word 0x0 "LANE0_DIG_ANA_RX_DAC_CTRL_OVRD,Overrides RX DAC CTRL bus (en/val/sel) going to ANA" newline hexmask.word 0x0 1.--15. 1. "RESERVED_15_1,Reserved for Future use" newline bitfld.word 0x0 0. "RX_CAL_DAC_CTRL_OVRD,Override enable for Cal DAC control" "0,1" group.word 0x42BC++0x1 line.word 0x0 "LANE0_DIG_ANA_RX_DAC_CTRL_SEL,Sets values for RX DAC CTRL Select signal going to ANA" newline hexmask.word 0x0 5.--15. 1. "RESERVED_15_5,Reserved for Future use" newline hexmask.word.byte 0x0 0.--4. 1. "RX_ANA_CAL_DAC_CTRL_SEL,Value for rx_ana_cal_dac_ctrl_sel[4:0]" group.word 0x42C0++0x1 line.word 0x0 "LANE0_DIG_ANA_RX_AFE_ATT_VGA,Value for RX AFE ATT & VGA signals going to ANA" newline hexmask.word.byte 0x0 12.--15. 1. "RESERVED_15_12,Reserved for Future use" newline bitfld.word 0x0 11. "RX_AFE_OVRD_EN,Override enable for AFE control" "0,1" newline hexmask.word.byte 0x0 7.--10. 1. "RESERVED," newline hexmask.word.byte 0x0 3.--6. 1. "RX_ANA_AFE_GAIN,Value for rx_ana_afe_gain[3:0]" newline bitfld.word 0x0 0.--2. "RX_ANA_AFE_ATT_LVL,Value for rx_ana_afe_att_lvl[2:0]" "0,1,2,3,4,5,6,7" group.word 0x42C4++0x1 line.word 0x0 "LANE0_DIG_ANA_RX_AFE_CTLE,Values for RX AFE CTLE signals going to ANA" newline hexmask.word.byte 0x0 8.--15. 1. "RESERVED_15_8,Reserved for Future use" newline hexmask.word.byte 0x0 3.--7. 1. "RX_ANA_AFE_CTLE_BOOST,Value for rx_ana_afe_ctle_boost[4:0]" newline bitfld.word 0x0 0.--2. "RESERVED," "0,1,2,3,4,5,6,7" group.word 0x42C8++0x1 line.word 0x0 "LANE0_DIG_ANA_RX_SCOPE,Values for RX SCOPE signals going to ANA" newline rbitfld.word 0x0 14.--15. "RESERVED_15_14,Reserved for Future use" "0,1,2,3" newline bitfld.word 0x0 13. "RX_SCOPE_SELF_CLEAR_DISABLE,Disable the self-clearing for rx_ana_scope_ph_clk register" "0,1" newline bitfld.word 0x0 12. "RX_ANA_SCOPE_CLK_EN,Enable the scope clocks going to the scope slicer and the lane digital part" "0,1" newline hexmask.word.byte 0x0 4.--11. 1. "RX_ANA_SCOPE_PHASE,Sets value for rx_ana_scope_phase[7:0]" newline bitfld.word 0x0 3. "RX_ANA_SCOPE_PH_CLK,Sets value for rx_ana_scope_ph_clk - This bit is self-clearing (i.e. only asserts for one cr_clk cycle)" "0,1" newline bitfld.word 0x0 1.--2. "RX_ANA_SCOPE_SEL,Sets value for rx_ana_scope_sel 00 - AFE scope selected 01 - DFE even scope selected 10 - DFE odd scope selected 11 - DFE bypass/AFE buffer scope selected" "AFE scope selected,DFE even scope selected,?,?" newline bitfld.word 0x0 0. "RX_ANA_SCOPE_EN,Sets value for rx_ana_scope_en" "0,1" group.word 0x42CC++0x1 line.word 0x0 "LANE0_DIG_ANA_RX_SLICER_CTRL,Sets values for RX Slicer Ctrl signals going to ANA register" newline hexmask.word.byte 0x0 9.--15. 1. "RESERVED_15_9,Reserved for Future use" newline bitfld.word 0x0 8. "RX_ANA_SLICER_CTRL_OVRD_EN,Override enable for Rx ANA Slicer Ctrl" "0,1" newline hexmask.word.byte 0x0 4.--7. 1. "RX_ANA_SLICER_CTRL_O,Value for rx_ana_slicer_ctrl_o[3:0]" newline hexmask.word.byte 0x0 0.--3. 1. "RX_ANA_SLICER_CTRL_E,Value for rx_ana_slicer_ctrl_e[3:0]" group.word 0x42D0++0x1 line.word 0x0 "LANE0_DIG_ANA_RX_ANA_IQ_PHASE_ADJUST,Sets values for RX ANA IQ PHASE Adjust signal going to ANA register" newline hexmask.word 0x0 7.--15. 1. "RESERVED_15_7,Reserved for Future use" newline hexmask.word.byte 0x0 0.--6. 1. "RX_ANA_IQ_PHASE_ADJUST,Value for rx_ana_iq_phase_adjust[6:0]" group.word 0x42D4++0x1 line.word 0x0 "LANE0_DIG_ANA_RX_ANA_IQ_SENSE_EN,Sets values for RX ANA IQ SENSE signal" newline hexmask.word 0x0 1.--15. 1. "RESERVED_15_1,Reserved for Future use" newline bitfld.word 0x0 0. "RX_ANA_IQ_SENSE_EN,Value for rx_ana_iq_sense_en" "0,1" group.word 0x42D8++0x1 line.word 0x0 "LANE0_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN,DAC CTRL enable signal" newline hexmask.word 0x0 2.--15. 1. "RESERVED_15_2,Reserved for Future use" newline bitfld.word 0x0 1. "DAC_CTRL_SELF_CLEAR_DISABLE,Disable self-clearing for the rx_ana_cal_dac_ctrl_en register" "0,1" newline bitfld.word 0x0 0. "RX_ANA_CAL_DAC_CTRL_EN,Value for rx_ana_cal_dac_ctrl_en - If DAC_CTRL_SELF_CLEAR_DISABLE=0 then this bit is self-clearing (i.e. only asserts for one cr_clk cycle)" "0,1" group.word 0x42DC++0x1 line.word 0x0 "LANE0_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE,Afe update enable signal" newline hexmask.word 0x0 2.--15. 1. "RESERVED_15_2,Reserved for Future use" newline bitfld.word 0x0 1. "AFE_UPDATE_SELF_CLEAR_DISABLE,Disable self-clearing for the rx_ana_afe_update_en register" "0,1" newline bitfld.word 0x0 0. "RX_ANA_AFE_UPDATE_EN,Value for rx_ana_afe_update_en - If AFE_UPDATE_SELF_CLEAR_DISABLE=0 then this bit is self-clearing (i.e. only asserts for one cr_clk cycle)" "0,1" group.word 0x42E0++0x1 line.word 0x0 "LANE0_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK,Phase adjust clock signal" newline hexmask.word 0x0 2.--15. 1. "RESERVED_15_2,Reserved for Future use" newline bitfld.word 0x0 1. "PHASE_ADJUST_SELF_CLEAR_DISABLE,Disable self-clearing for the rx_ana_iq_phase_adjust_clk register" "0,1" newline bitfld.word 0x0 0. "RX_ANA_IQ_PHASE_ADJUST_CLK,Value for rx_ana_iq_phase_adjust_clk - If PHASE_ADJUST_SELF_CLEAR_DISABLE=0 then this bit is self-clearing (i.e. only asserts for one cr_clk cycle)" "0,1" rgroup.word 0x42E4++0x1 line.word 0x0 "LANE0_DIG_ANA_STATUS_0,Lane input status register #0" newline hexmask.word.byte 0x0 8.--15. 1. "RESERVED_15_8,Reserved for Future use" newline bitfld.word 0x0 7. "RX_ANA_SCOPE_DATA,Value from ANA for rx_ana_scope_data" "0,1" newline bitfld.word 0x0 6. "RX_ANA_CAL_RESULT,Value from ANA for rx_ana_cal_result" "0,1" newline bitfld.word 0x0 5. "RX_ANA_LOS,Value from ANA for rx_ana_los" "0,1" newline bitfld.word 0x0 4. "TX_ANA_CLK_LB_EN,Value of tx_ana_clk_lb_en" "0,1" newline bitfld.word 0x0 3. "TX_ANA_LOOPBACK_EN,Value of tx_ana_loopback_en" "0,1" newline bitfld.word 0x0 2. "TX_ANA_RXDETM_RESULT,Value from ANA for tx_ana_rxdetm_result" "0,1" newline bitfld.word 0x0 1. "TX_ANA_RXDETP_RESULT,Value from ANA for tx_ana_rxdetp_result" "0,1" newline bitfld.word 0x0 0. "TX_ANA_CLK_SHIFT_ACK,Value from ANA for tx_ana_clk_shift_ack" "0,1" rgroup.word 0x42E8++0x1 line.word 0x0 "LANE0_DIG_ANA_STATUS_1,Lane input status register #1" newline bitfld.word 0x0 13.--15. "RESERVED_15_13,Reserved for Future use" "0,1,2,3,4,5,6,7" newline hexmask.word 0x0 0.--12. 1. "RX_ANA_VCO_CNTR,Value from ANA for rx_ana_vco_cntr" group.word 0x42EC++0x1 line.word 0x0 "LANE0_DIG_ANA_RX_TERM_CODE_OVRD_OUT,Override value for RX termination code going to ANA" newline hexmask.word 0x0 7.--15. 1. "RESERVED_15_7,Reserved for Future use" newline bitfld.word 0x0 6. "RX_TERM_OVRD_EN,Override enable for the rx_ana_term_code[5:0] signal" "0,1" newline hexmask.word.byte 0x0 0.--5. 1. "RX_TERM_CODE,Overrides the rx_ana_term_code[5:0] signal" group.word 0x42F0++0x1 line.word 0x0 "LANE0_DIG_ANA_RX_TERM_CODE_CLK_OVRD_OUT,Override value for RX termination code clock going to ANA" newline hexmask.word 0x0 2.--15. 1. "RESERVED_15_2,Reserved for Future use" newline bitfld.word 0x0 1. "RX_TERM_CLK_SELF_CLEAR_DISABLE,Disable the self-clearing of rx_ana_term_clk register" "0,1" newline bitfld.word 0x0 0. "RX_TERM_CLK,Override for TX term DN clock - This bit is self_clearing (4 cr_clks later)." "0,1" group.word 0x4300++0x1 line.word 0x0 "LANE0_ANA_TX_OVRD_MEAS,TX_OVRD_MEAS" newline hexmask.word.byte 0x0 8.--15. 1. "RESERVED_15_8,Reserved for Future use" newline bitfld.word 0x0 7. "PULL_DN_REG,Pull down TX output if asserted" "0,1" newline bitfld.word 0x0 6. "PULL_UP_REG,Pull up TX output if asserted" "0,1" newline bitfld.word 0x0 5. "VCM_HOLD_REG,Set Tx in common mode if asserted together with bit 4" "0,1" newline bitfld.word 0x0 4. "OVRD_VCM_HOLD,If asserted bit 5 take effect on control Tx common mode" "0,1" newline bitfld.word 0x0 3. "MEAS_SAMP_P,Measure clock p DCD through atb_s_p on clock psample" "0,1" newline bitfld.word 0x0 2. "MEAS_SAMP_M,Measure clock m DCD through atb_s_p on clock m sample" "0,1" newline bitfld.word 0x0 1. "CLK_SHIFT_REG,Controls clock shift if asserted with bit 0" "0,1" newline bitfld.word 0x0 0. "OVRD_CLK_SHIFT,If asserted allow analog register to control clock shift function" "0,1" group.word 0x4304++0x1 line.word 0x0 "LANE0_ANA_TX_PWR_OVRD,TX_PWR_OVRD" newline hexmask.word.byte 0x0 8.--15. 1. "RESERVED_15_8,Reserved for Future use" newline bitfld.word 0x0 7. "OVRD_EN,Enable analog register to take control TX power state if asserted" "0,1" newline bitfld.word 0x0 6. "SERIAL_EN_REG,Enable TX serializer if assered with bit 7" "0,1" newline bitfld.word 0x0 5. "CLK_EN_REG,Enable TX clock if asserted with bit 7" "0,1" newline bitfld.word 0x0 4. "DATA_EN_REG,Enable TX driver data path if asserted with bit 7" "0,1" newline bitfld.word 0x0 3. "CLK_DIV_EN_REG,Enable TX divider if asserted with bit 7 overrides !tx_reset" "0,1" newline bitfld.word 0x0 2. "REFGEN_EN_REG,Enable TX biasing if asserted with bit 7" "0,1" newline bitfld.word 0x0 1. "LOOPBACK_EN_REG,Enable TX loopback path to RX if asserted along with bit 0" "0,1" newline bitfld.word 0x0 0. "OVRD_TX_LOOPBACK,Enable Tx loopback mode over ridden by analog register if asserted" "0,1" group.word 0x4308++0x1 line.word 0x0 "LANE0_ANA_TX_ALT_BUS,TX_ALT_BUS" newline hexmask.word.byte 0x0 8.--15. 1. "RESERVED_15_8,Reserved for Future use" newline bitfld.word 0x0 7. "JTAG_DATA_REG,When bit 2 is asserted it replace jtag data" "0,1" newline bitfld.word 0x0 4.--6. "TX_ALT_RINGO,Three bit select of the ALT path test oscillators 000 no oscillators enabled 001 osc_vp_ulvt oscillator enabled 010 osc_vptx_lvt oscillator enabled 011 osc_vp_lvt oscillator enabled 100 Reserved 101 Reserved 110 Reserved 111 osc_vph_hv.." "0,1,2,3,4,5,6,7" newline bitfld.word 0x0 3. "NC3,Reserved" "0,1" newline bitfld.word 0x0 2. "OVRD_ALT_BUS,If asserted jtag data and TX data source selection are controlled by bits [1:0] and bit 7" "0,1" newline bitfld.word 0x0 0.--1. "DRV_SOURCE_REG,When bit 2 is asserted drv_source_reg[1:0] takes control of TX function overrides tx_data_source[1:0]" "0,1,2,3" repeat 2. (list 0x1 0x2 )(list 0x0 0x4 ) group.word ($2+0x430C)++0x1 line.word 0x0 "LANE0_ANA_TX_ATB$1,TX_ATB1" newline hexmask.word.byte 0x0 8.--15. 1. "RESERVED_15_8,Reserved for Future use" newline bitfld.word 0x0 7. "NC7,Reserved" "0,1" newline bitfld.word 0x0 6. "ATB_VREG1,Put TX regulator 1 output on atb_s_p when asserted" "0,1" newline bitfld.word 0x0 5. "ATB_VREG0,Put TX regulator 0 output on atb_s_p when asserted" "0,1" newline bitfld.word 0x0 4. "OVERRIDE_REGREF_0,Use atb_s_m as TX regulator 0 reference voltage when asserted" "0,1" newline bitfld.word 0x0 3. "ATB_VPTX,Put TX driver local vptx on atb_s_p when asserted" "0,1" newline bitfld.word 0x0 2. "ATB_VDCCP,Put DCC control voltage p on atb_s_p when asserted" "0,1" newline bitfld.word 0x0 1. "ATB_VDCCM,Put DCC control voltage m on atb_s_p when asserted" "0,1" newline bitfld.word 0x0 0. "ATB_GD,Put tx local gd on atb_s_p when asserted" "0,1" repeat.end group.word 0x4314++0x1 line.word 0x0 "LANE0_ANA_TX_VBOOST,TX_VBOOST" newline hexmask.word.byte 0x0 8.--15. 1. "RESERVED_15_8,Reserved for Future use" newline bitfld.word 0x0 7. "OVRD_VBOOST_EN,Enable TX boost mode to be override by bit 6" "0,1" newline bitfld.word 0x0 6. "VBOOST_EN_REG,If bit 7 is set to 1 analog register takes control of Tx vboost enable/disable" "0,1" newline bitfld.word 0x0 5. "BOOST_VPTX_MODE_N,If asserted TX boost mode becomes a direct boost mode. VdIffpp=vptx+0.05*(2.5*(1+iboost_code)*(2*tx_vboost_vref) in default TX boost mode" "0,1" newline bitfld.word 0x0 4. "ATB_VBOOST,Measure vptx/2 through atb_s_p when TX boost is enabled" "0,1" newline bitfld.word 0x0 3. "ATB_VBOOST_VREF,Measure tx boost reference voltage through atb_s_p" "0,1" newline bitfld.word 0x0 2. "OVERRIDE_VREF_BOOST_REF,If enabled atb_s_m is used to provide Tx boost reference voltage instead of bandgap voltage tx_vboost_vref" "0,1" newline bitfld.word 0x0 1. "ATB_S_ENABLE,Enables TX atb function if asserted This bit has to be set to 1 in order to make TX atb_s_p/m visible" "0,1" newline bitfld.word 0x0 0. "MEAS_ATB_VPH_HALF,Measure vph/2 on atb_s_p" "0,1" group.word 0x4318++0x1 line.word 0x0 "LANE0_ANA_TX_TERM_CODE,TX_TERM_CODE" newline hexmask.word.byte 0x0 8.--15. 1. "RESERVED_15_8,Reserved for Future use" newline hexmask.word.byte 0x0 1.--7. 1. "TERM_CODE_REG,TX leg biasing register (7 MSBs) this is Term_code_reg[9:3]" newline bitfld.word 0x0 0. "TERM_CODE_OVRD,Enable analog register to overdrive TX leg biasing" "0,1" group.word 0x431C++0x1 line.word 0x0 "LANE0_ANA_TX_TERM_CODE_CTRL,TX_TERM_CODE_CTRL" newline hexmask.word.byte 0x0 8.--15. 1. "RESERVED_15_8,Reserved for Future use" newline bitfld.word 0x0 7. "RESET_TERM_REG,Resets the tx termination code DACs" "0,1" newline bitfld.word 0x0 6. "RESET_TERM_OVRD,Enable analog register to reset termination code DACs" "0,1" newline bitfld.word 0x0 5. "UPDATE_TERM_UP_REG,Register control to update the pullup TX terminations" "0,1" newline bitfld.word 0x0 4. "UPDATE_TERM_UP_OVRD,Enables analog register control to update the pullup TX terminations" "0,1" newline bitfld.word 0x0 3. "UPDATE_TERM_DN_REG,Register control to update the pulldown TX terminations" "0,1" newline bitfld.word 0x0 2. "UPDATE_TERM_DN_OVRD,Enables analog register control to update the pulldown TX terminations" "0,1" newline bitfld.word 0x0 1. "TX_PWR_EN_REG,Register control over the power gating of blocks within the TX" "0,1" newline bitfld.word 0x0 0. "TX_PWR_EN_OVRD,Enables analog register control over the power gating of blocks within the TX" "0,1" group.word 0x4320++0x1 line.word 0x0 "LANE0_ANA_TX_IBOOST_CODE,TX_IBOOST_CODE" newline hexmask.word.byte 0x0 8.--15. 1. "RESERVED_15_8,Reserved for Future use" newline hexmask.word.byte 0x0 4.--7. 1. "IBOOST_CODE_REG,When TX boost is enabled and bit 3 is asserted these 4 bits take control of TX boost. VdIffpp=vptx+0.05*(2.5*(1+iboost_code)*(2*tx_vboost_vref-vptx/2) in default TX boost mode" newline bitfld.word 0x0 3. "IBOOST_CODE_OVRD,Enable analog register overdrive for TX boost" "0,1" newline bitfld.word 0x0 1.--2. "TERM_CODE_REG,TX leg biasing register bit 2 & 1 this is term_code_reg[2:1]" "0,1,2,3" newline bitfld.word 0x0 0. "LFPS_HIGH_PRIORITY,If asserted lfps/beacon enable has higher priority than data enable" "0,1" group.word 0x4324++0x1 line.word 0x0 "LANE0_ANA_TX_OVRD_CLK,TX_OVRD_CLK" newline hexmask.word.byte 0x0 8.--15. 1. "RESERVED_15_8,Reserved for Future use" newline bitfld.word 0x0 7. "OVRD_WORD_CLK_EN,If asserted it allows bit 6 to override tx word clock enable" "0,1" newline bitfld.word 0x0 6. "WORD_CLK_EN_REG,Tx word clock enable/disable when bit 7 is asserted" "0,1" newline bitfld.word 0x0 5. "OVRD_MPLLAB_EN,If asserted it allows bit 3 or 4 to take control of selecting MPLL clocks" "0,1" newline bitfld.word 0x0 4. "MPLLA_CLK_EN_REG,When asserted with bit 5 selects MPLLA clock as TX data output clock Only bit 3 or bit 4 or bit 1 can be asserted" "0,1" newline bitfld.word 0x0 3. "MPLLB_CLK_EN_REG,When asserted with bit 5 selects MPLLB clock as TX data output clock Only bit 3 or bit 4 or bit 1 can be asserted" "0,1" newline bitfld.word 0x0 2. "OVRD_LB_EN,If asserted it allows bit 1 takes control of RX clock loopback to TX" "0,1" newline bitfld.word 0x0 1. "CLK_LB_EN_REG,When asserted with bit 2 selects RX clock for TX data output clock" "0,1" newline bitfld.word 0x0 0. "OVERRIDE_REGREF_1,Use atb_s_m to over ride TX regulator reference voltage when asserted" "0,1" group.word 0x4328++0x1 line.word 0x0 "LANE0_ANA_TX_MISC,TX_MISC" newline hexmask.word.byte 0x0 8.--15. 1. "RESERVED_15_8,Reserved for Future use" newline bitfld.word 0x0 7. "OVERRIDE_RXDETREF,If asserted atb_s_m is used to override RX detection reference voltage" "0,1" newline bitfld.word 0x0 6. "MEAS_ATB_BIAS_VPTX,Measure TX bias local vptx through atb_s_p when asserted" "0,1" newline bitfld.word 0x0 5. "OSC_DIV4_EN,If asserted divides tx_alt oscillator output frequency by 4" "0,1" newline hexmask.word.byte 0x0 0.--4. 1. "NC4_0,Reserved" group.word 0x432C++0x1 line.word 0x0 "LANE0_ANA_RX_ATB_IQSKEW,RX_ATB_IQSKEW" newline hexmask.word.byte 0x0 8.--15. 1. "RESERVED_15_8,Reserved for Future use" newline bitfld.word 0x0 7. "MASTER_ATB_EN,If asserted enable RX ATB sensing bus atb_s_p/m visible externally.The exception is bit 5 which dont require this bit to be asserted" "0,1" newline bitfld.word 0x0 6. "MEAS_ATB_RX_SCOPE_REG,If asserted enable scope linearity characterization through atb_s_p/m" "0,1" newline bitfld.word 0x0 5. "MEAS_ATB_VP,If asserted vp is measured through atb_s_p" "0,1" newline hexmask.word.byte 0x0 0.--4. 1. "IQ_PHASE_ADJUST_REG,If ovrd_iq_phase_adjust is enabled these bits control the main PMIX" group.word 0x4330++0x1 line.word 0x0 "LANE0_ANA_RX_DCC_OVRD,RX_DCC_OVRD" newline hexmask.word.byte 0x0 8.--15. 1. "RESERVED_15_8,Reserved for Future use" newline bitfld.word 0x0 7. "DCC_EN_REG,When bit 6 is asserted this bit takes control of RX DCC enable" "0,1" newline bitfld.word 0x0 6. "OVRD_DCCANDAFE_EN,When asserted override RX DCC enable by analog register" "0,1" newline bitfld.word 0x0 5. "RX_LOOPBACK_CLK_REG,When bit 4 asserted this bit takes control of RX clock loopback enable/disable" "0,1" newline bitfld.word 0x0 4. "OVRD_RX_LOOPBACK_CLK,When asserted override rx clock loopback by analog register" "0,1" newline bitfld.word 0x0 2.--3. "MEAS_ATB_VDCC,meas_atb_vdcc[1:0] 00 Disable atb measurement 01 measure vdcc_i_p/m through atb_s_p/m 10 measure vdcc_q_p/m through atb_s_p/m 11 measure vdcc_i/q through atb_s_p/m" "0,1,2,3" newline bitfld.word 0x0 0.--1. "NC1_0,Reserved" "0,1,2,3" repeat 2. (list 0x1 0x2 )(list 0x0 0xC ) group.word ($2+0x4334)++0x1 line.word 0x0 "LANE0_ANA_RX_PWR_CTRL$1,RX_PWR_CTRL1" newline hexmask.word.byte 0x0 8.--15. 1. "RESERVED_15_8,Reserved for Future use" newline bitfld.word 0x0 7. "AFE_EN_REG,When asserted with bit 6 enables AFE" "0,1" newline bitfld.word 0x0 6. "OVRD_AFE_EN,If asserted bit 7 take control of AFE enable/disable" "0,1" newline bitfld.word 0x0 5. "LOS_EN_REG,When asserted with bit 4 enables LOS" "0,1" newline bitfld.word 0x0 4. "OVRD_LOS_EN,If asserted bit 5 take control of LOS enable/disable" "0,1" newline bitfld.word 0x0 3. "CLK_EN_REG,When asserted with bit 2 enables RX clock" "0,1" newline bitfld.word 0x0 2. "OVRD_CLK_EN,If asserted bit 3 take control of RX clock enable/disable" "0,1" newline bitfld.word 0x0 1. "ACJT_EN_REG,When asserted with bit 0 enables ACJTAG" "0,1" newline bitfld.word 0x0 0. "OVRD_ACJT_EN,If asserted bit 1 take control of ACJTAG enable/disable" "0,1" repeat.end group.word 0x4338++0x1 line.word 0x0 "LANE0_ANA_RX_ATB_REGREF,RX_ATB_REGREF" newline hexmask.word.byte 0x0 8.--15. 1. "RESERVED_15_8,Reserved for Future use" newline bitfld.word 0x0 5.--7. "MEAS_ATB_CAL_MUX,Meas_atb_cal_mux is 3 bit signal Meas_atb_cal_mux[2:0] If Meas_atb_cal_mux[2] asserted RX offset calibration comparator first stage differential outputs are measured through atb_s_p/m If Meas_atb_cal_mux[1] asserted atb_s_p/m.." "0,1,2,3,4,5,6,7" newline bitfld.word 0x0 4. "OVERRIDE_REGREF_CLK,If asserted RX clock regulator reference is overridden through atb_s_m" "0,1" newline bitfld.word 0x0 3. "OVERRIDE_REGREF_SCOPE,If asserted RX scope regulator reference is overridden through atb_s_m" "0,1" newline bitfld.word 0x0 2. "NC2,Reserved" "0,1" newline bitfld.word 0x0 0.--1. "MEAS_ATB_SAMP,meas_atb_samp[1:0] 00 Disable atb measurement 01 measure clk_i_p/m sampling node through atb_s_p/m 10 measure clk_q_p/m sampling node through atb_s_p/m 11 measure clk_i/q sampling node through atb_s_p/m" "0,1,2,3" group.word 0x433C++0x1 line.word 0x0 "LANE0_ANA_RX_CDR_AFE,RX_CDR_AFE" newline hexmask.word.byte 0x0 8.--15. 1. "RESERVED_15_8,Reserved for Future use" newline bitfld.word 0x0 6.--7. "NC7_6,Reserved" "0,1,2,3" newline bitfld.word 0x0 5. "PHDET_EVEN_REG,If asserted CDR phase detector uses even data path" "0,1" newline bitfld.word 0x0 4. "PHDET_ODD_REG,If asserted CDR phase detector uses odd data path" "0,1" newline hexmask.word.byte 0x0 0.--3. 1. "MEAS_ATB_RX,This is meas_atb_rx[9:6] bit each bit correspond to ==> meas_atb_rx[9] If asserted AFE biasing vbp is measured through atb_s_p meas_atb_rx[8] If asserted AFE biasing vbn is measured through atb_s_m meas_atb_rx[7] If asserted rx_p is.." group.word 0x4344++0x1 line.word 0x0 "LANE0_ANA_RX_MISC_OVRD,RX_MISC_OVRD" newline hexmask.word.byte 0x0 8.--15. 1. "RESERVED_15_8,Reserved for Future use" newline bitfld.word 0x0 7. "OVERRIDE_VREG_PRECHG_REG,If asserted the overvoltage compensation circuit in rx_vregs disabled" "0,1" newline bitfld.word 0x0 6. "CTLE_OFFSET_CAL_ENB,If asserted the offset calibration currents in the CTLE are disabled" "0,1" newline bitfld.word 0x0 5. "OVRD_RX_LOS_LFPS_EN,If asserted bit 4 enable/disables RX true LFPS detection" "0,1" newline bitfld.word 0x0 4. "RX_LOS_LFPS_EN_REG,If asserted with bit 5 enables true LFPS detection" "0,1" newline bitfld.word 0x0 2.--3. "NC3_2,Reserved" "0,1,2,3" newline bitfld.word 0x0 1. "WORD_CLK_EN_REG,If asserted with bit 0 enables rx word clock" "0,1" newline bitfld.word 0x0 0. "OVRD_WORD_CLK_EN,If asserted bit 1 takes control of word clock enable/disable" "0,1" group.word 0x4348++0x1 line.word 0x0 "LANE0_ANA_RX_CAL_MUXA,RX_CAL_MUXA" newline hexmask.word.byte 0x0 8.--15. 1. "RESERVED_15_8,Reserved for Future use" newline bitfld.word 0x0 7. "OVRD_CAL_MUXA_SEL,If asserted selects analog register setting to control RX calibration path A" "0,1" newline hexmask.word.byte 0x0 2.--6. 1. "CAL_MUXA_SEL_REG,Analog registers to control RX calibration path A if bit 7 is asserted this is cal_muxa_sel_reg[4:0]" newline bitfld.word 0x0 1. "MEAS_ATB_VIBIAS_VCO,If asserted measure CDR VCO bias current through atb_s_p (25uA)" "0,1" newline bitfld.word 0x0 0. "MEAS_ATB_VCO_200U,If asserted measure CDR VCO bias current through atb_s_m (200uA)" "0,1" group.word 0x434C++0x1 line.word 0x0 "LANE0_ANA_RX_ATB_MEAS1,RX_ATB_MEAS1" newline hexmask.word.byte 0x0 8.--15. 1. "RESERVED_15_8,Reserved for Future use" newline bitfld.word 0x0 7. "ATB_FRC_VLOS,If asserted force los detection reference voltage through atb_s_m" "0,1" newline hexmask.word.byte 0x0 1.--6. 1. "MEAS_ATB_RX,This is meas_atb_rx[5:0] bits where each bit correspond to meas_atb_rx[5] If asserted rx_m is driven by atb_f_m meas_atb_rx[4] If asserted rx_m is sensed through atb_s_m meas_atb_rx[3] If asserted measure RX LOS detection threshold.." newline bitfld.word 0x0 0. "NC0,Reserved" "0,1" group.word 0x4350++0x1 line.word 0x0 "LANE0_ANA_RX_ATB_MEAS2,RX_ATB_MEAS2" newline hexmask.word.byte 0x0 8.--15. 1. "RESERVED_15_8,Reserved for Future use" newline bitfld.word 0x0 7. "MEAS_GD,If asserted measure RX regulator local gd through atb_s_p" "0,1" newline bitfld.word 0x0 6. "NC6,Reserved" "0,1" newline bitfld.word 0x0 5. "MEAS_VREG_CLK,If asserted measure RX clock regulator output voltage through atb_s_p" "0,1" newline bitfld.word 0x0 4. "NC4,Reserved" "0,1" newline bitfld.word 0x0 3. "MEAS_VREG_SCOPE,If asserted measure RX scope regulator output voltage through atb_s_p" "0,1" newline bitfld.word 0x0 2. "MEAS_ATB_OVRD_CDR_EN,If asserted enables CDR regardless of the digital control" "0,1" newline bitfld.word 0x0 1. "MEAS_ATB_VCO_GD,If asserted measure CDR VCO local gd through atb_s_m" "0,1" newline bitfld.word 0x0 0. "MEAS_ATB_VCO_VOSC,If asserted measure CDR VCO oscillation bias current through atb_s_m" "0,1" group.word 0x4354++0x1 line.word 0x0 "LANE0_ANA_RX_CAL_MUXB,RX_CAL_MUXB" newline hexmask.word.byte 0x0 8.--15. 1. "RESERVED_15_8,Reserved for Future use" newline bitfld.word 0x0 7. "OVRD_CAL_MUXB_SEL,If asserted selects analog register setting to control RX calibration path B" "0,1" newline hexmask.word.byte 0x0 2.--6. 1. "CAL_MUXB_SEL_REG,Analog registers to control RX calibration path B if bit 7 is asserted this is cal_muxb_sel_reg[4:0]" newline bitfld.word 0x0 1. "OVRD_DFE_TAPS_EN,If asserted allows bit 0 to enable/disable dfe taps 1 and 2" "0,1" newline bitfld.word 0x0 0. "DFE_TAPS_EN_REG,If bit 1 is asserted controls DFE tap 1 and 2" "0,1" group.word 0x4358++0x1 line.word 0x0 "LANE0_ANA_RX_TERM,RX_TERM" newline hexmask.word.byte 0x0 8.--15. 1. "RESERVED_15_8,Reserved for Future use" newline bitfld.word 0x0 6.--7. "AFE_CM_SEL,Added to make AFE CM voltage controllable (below values are for TT vp=0.8V) 00 vcm=662mV 01 vcm=627mV (default) 10 vcm=593mV 11 vcm=558mV" "0,1,2,3" newline bitfld.word 0x0 5. "OVRD_RX_TERM_GD_EN,If asserted the ground termination enable value is controlled via registers" "0,1" newline bitfld.word 0x0 4. "RX_TERM_GD_EN_REG,If termination override is asserted controls the ground termination enable" "0,1" newline bitfld.word 0x0 3. "OVRD_IQ_PHASE_ADJUST,If asserted the iq_phase_adjust value is controlled via registers" "0,1" newline bitfld.word 0x0 2. "VCO_TEMP_COMP_EN,If asserted the RX-VCO temperature compensation circuit is enabled" "0,1" newline bitfld.word 0x0 0.--1. "CDR_VCO_STARTUP_CODE_REG,RX_VCO startup current over-ride cdr_vco_startup_code Startup override 00 cdr_freq_code_int[9:7] = cdr_freq_code[9:7] 01 when startup = 1 -> cdr_freq_code_int[9] = 1 10 when startup = 1 -> cdr_freq_code_int[8] = 1 11 when startup.." "?,cdr_freq_code_int[7] = 1,?,?" group.word 0x435C++0x1 line.word 0x0 "LANE0_ANA_RX_SLC_CTRL,RX_SLC_CTRL" newline hexmask.word.byte 0x0 8.--15. 1. "RESERVED_15_8,Reserved for Future use" newline hexmask.word.byte 0x0 4.--7. 1. "RX_SLICER_CTRL_E_REG,If ovrd_rx_slicer_ctrl_reg is asserted controls the even slicer configuration" newline hexmask.word.byte 0x0 0.--3. 1. "RX_SLICER_CTRL_O_REG,If ovrd_rx_slicer_ctrl_reg is asserted controls the odd slicer configuration" group.word 0x4360++0x1 line.word 0x0 "LANE0_ANA_RX_ATB_VREG,RX_ATB_VREG" newline hexmask.word.byte 0x0 8.--15. 1. "RESERVED_15_8,Reserved for Future use" newline bitfld.word 0x0 7. "OVRD_REGREF_IQC,If asserted main PMIX regulator reference is overridden through atb_s_m" "0,1" newline bitfld.word 0x0 6. "OVRD_REGREF_IQC_SCOPE,If asserted scope PMIX regulator reference is overridden through atb_s_m" "0,1" newline bitfld.word 0x0 5. "MEAS_ATB_VREG_DFE,If asserted measure RX DFE regulator output voltage through atb_s_p" "0,1" newline bitfld.word 0x0 4. "NC4,Reserved" "0,1" newline bitfld.word 0x0 3. "MEAS_ATB_VREG_IQC,If asserted measure RX main PMIX regulator output voltage through atb_s_p" "0,1" newline bitfld.word 0x0 2. "MEAS_ATB_VREG_IQC_SCOPE,If asserted measure RX scope PMIX regulator output voltage through atb_s_p" "0,1" newline bitfld.word 0x0 1. "OVRD_IQC_VREF_SEL,If asserted the vref on the iqc regulator is controlled via vbg_vref which can be controlled via registers" "0,1" newline bitfld.word 0x0 0. "OVRD_RX_SLICER_CTRL_REG,If asserted the slicer configuration value is controlled via registers (LANE.RX_SLC_CTRL)" "0,1" group.word 0x4400++0x1 line.word 0x0 "LANE1_DIG_ASIC_LANE_OVRD_IN,Override values for incoming LANE controls from ASIC" newline hexmask.word 0x0 3.--15. 1. "RESERVED_15_3,Reserved for Future use" newline bitfld.word 0x0 2. "EN,Enable override values for all inputs controlled by this register" "0,1" newline bitfld.word 0x0 1. "LANE_RX2TX_PAR_LB,Override value for lane_rx2tx_par_lb_en_r" "0,1" newline bitfld.word 0x0 0. "LANE_TX2RX_SER_LB,Override value for lane_tx2rx_ser_lb_en_r" "0,1" group.word 0x4404++0x1 line.word 0x0 "LANE1_DIG_ASIC_TX_OVRD_IN_0,Override values for incoming TX controls from ASIC. register #0" newline bitfld.word 0x0 15. "DATA_EN_OVRD_EN,Enable override for tx_data_en" "0,1" newline bitfld.word 0x0 14. "DATA_EN,Override value for tx_data_en" "0,1" newline bitfld.word 0x0 13. "MPLLB_SEL_OVRD_EN,Enable override for tx_mpllb_sel" "0,1" newline bitfld.word 0x0 12. "MPLLB_SEL,Override value for tx_mpllb_sel" "0,1" newline bitfld.word 0x0 11. "WIDTH_OVRD_EN,Enable override for tx_width[1:0]" "0,1" newline bitfld.word 0x0 9.--10. "WIDTH,Override value for tx_width[1:0]" "0,1,2,3" newline bitfld.word 0x0 8. "RATE_OVRD_EN,Enable override for tx_rate[2:0]" "0,1" newline bitfld.word 0x0 5.--7. "RATE,Override value for tx_rate[2:0]" "0,1,2,3,4,5,6,7" newline bitfld.word 0x0 4. "PSTATE_OVRD_EN,Enable override for tx_pstate[1:0]" "0,1" newline bitfld.word 0x0 2.--3. "PSTATE,Override value for tx_pstate[1:0]" "0,1,2,3" newline bitfld.word 0x0 1. "REQ_OVRD_EN,Enable override for tx_req" "0,1" newline bitfld.word 0x0 0. "REQ,Override value for tx_req" "0,1" group.word 0x4408++0x1 line.word 0x0 "LANE1_DIG_ASIC_TX_OVRD_IN_1,Override values for incoming TX drive controls from ASIC. register #1" newline bitfld.word 0x0 15. "MAIN_OVRD_EN,Enable override values for TX EQ main input" "0,1" newline hexmask.word.byte 0x0 9.--14. 1. "TX_MAIN_CURSOR,Override value for tx_eq_main" newline bitfld.word 0x0 8. "EN,Enable override values for inputs below controlled by this register" "0,1" newline bitfld.word 0x0 7. "VBOOST_EN,Override value for tx_vboost_en" "0,1" newline hexmask.word.byte 0x0 3.--6. 1. "IBOOST_LVL,Override value for tx_iboost_lvl" newline bitfld.word 0x0 2. "BEACON_EN,Override value for tx_beacon_en" "0,1" newline bitfld.word 0x0 1. "DISABLE,Override value for tx_disable" "0,1" newline bitfld.word 0x0 0. "NYQUIST_DATA,Override incoming data to nyquist" "0,1" group.word 0x440C++0x1 line.word 0x0 "LANE1_DIG_ASIC_TX_OVRD_IN_2,Override values for incoming TX drive controls from ASIC. register #2" newline rbitfld.word 0x0 14.--15. "RESERVED_15_14,Reserved for Future use" "0,1,2,3" newline bitfld.word 0x0 13. "POST_OVRD_EN,Enable override values for TX EQ post input" "0,1" newline hexmask.word.byte 0x0 7.--12. 1. "TX_POST_CURSOR,Override value for tx_eq_post" newline bitfld.word 0x0 6. "PRE_OVRD_EN,Enable override values for TX EQ pre input" "0,1" newline hexmask.word.byte 0x0 0.--5. 1. "TX_PRE_CURSOR,Override value for tx_eq_pre" group.word 0x4410++0x1 line.word 0x0 "LANE1_DIG_ASIC_TX_OVRD_IN_3,Override values for incoming TX drive controls from ASIC. register #3" newline hexmask.word.byte 0x0 8.--15. 1. "RESERVED_15_8,Reserved for Future use" newline bitfld.word 0x0 7. "LPD_OVRD_EN,Enable override for tx_lpd" "0,1" newline bitfld.word 0x0 6. "LPD,Override value for tx_lpd" "0,1" newline bitfld.word 0x0 5. "INVERT_OVRD_EN,Enable override for tx_invert" "0,1" newline bitfld.word 0x0 4. "INVERT,Override value for tx_invert" "0,1" newline bitfld.word 0x0 3. "DETECT_RX_REQ_OVRD_EN,Enable override for tx_detrx_req" "0,1" newline bitfld.word 0x0 2. "DETECT_RX_REQ,Override value for tx_detrx_req" "0,1" newline bitfld.word 0x0 1. "CLK_RDY_OVRD_EN,Enable override for tx_clk_rdy" "0,1" newline bitfld.word 0x0 0. "CLK_RDY,Override value for tx_clk_rdy" "0,1" group.word 0x4414++0x1 line.word 0x0 "LANE1_DIG_ASIC_TX_OVRD_IN_4,Override values for incoming TX drive controls from ASIC. register #4" newline hexmask.word 0x0 2.--15. 1. "RESERVED_15_2,Reserved for Future use" newline bitfld.word 0x0 1. "RESET_OVRD_EN,Enable override for tx_reset" "0,1" newline bitfld.word 0x0 0. "RESET,Override value for tx_reset" "0,1" group.word 0x4418++0x1 line.word 0x0 "LANE1_DIG_ASIC_TX_OVRD_OUT,Override values for outgoing TX controls to ASIC" newline hexmask.word 0x0 4.--15. 1. "RESERVED_15_4,Reserved for Future use" newline bitfld.word 0x0 3. "EN_DETRX_RESULT,Enable for override value for tx_detrx_result" "0,1" newline bitfld.word 0x0 2. "DETRX_RESULT,Override value for tx_detrx_result" "0,1" newline bitfld.word 0x0 1. "EN_TX_ACK,Enable for override value for tx_ack" "0,1" newline bitfld.word 0x0 0. "TX_ACK,Override value for tx_ack" "0,1" group.word 0x441C++0x1 line.word 0x0 "LANE1_DIG_ASIC_RX_OVRD_IN_0,Override values for incoming RX controls from ASIC. register #0" newline rbitfld.word 0x0 13.--15. "RESERVED_15_13,Reserved for Future use" "0,1,2,3,4,5,6,7" newline bitfld.word 0x0 12. "WIDTH_OVRD_EN,Enable override for rx_width" "0,1" newline bitfld.word 0x0 10.--11. "WIDTH,Override value for rx_width" "0,1,2,3" newline bitfld.word 0x0 9. "RATE_OVRD_EN,Enable override value for rx_rate" "0,1" newline bitfld.word 0x0 7.--8. "RATE,Override value for rx_rate" "0,1,2,3" newline bitfld.word 0x0 6. "PSTATE_OVRD_EN,Enable override value for rx_pstate" "0,1" newline bitfld.word 0x0 4.--5. "PSTATE,Override value for rx_pstate" "0,1,2,3" newline bitfld.word 0x0 3. "DATA_EN_OVRD_EN,Enable override value for rx_data_en" "0,1" newline bitfld.word 0x0 2. "DATA_EN,Override value for rx_data_en" "0,1" newline bitfld.word 0x0 1. "REQ_OVRD_EN,Enable override value for rx_req" "0,1" newline bitfld.word 0x0 0. "REQ,Override value for rx_req" "0,1" group.word 0x4420++0x1 line.word 0x0 "LANE1_DIG_ASIC_RX_OVRD_IN_1,Override values for incoming RX controls from ASIC. register #1" newline hexmask.word.byte 0x0 9.--15. 1. "RESERVED_15_9,Reserved for Future use" newline bitfld.word 0x0 8. "RX_REF_LD_VAL_6,Override value for rx_ref_ld_val[6]" "0,1" newline bitfld.word 0x0 7. "EN,Enable override values for all inputs controlled by this register" "0,1" newline bitfld.word 0x0 6. "RX_CDR_VCO_LOWFREQ,Override value for rx_cdr_vco_lowfreq" "0,1" newline hexmask.word.byte 0x0 0.--5. 1. "RX_REF_LD_VAL_5_0,Override value for rx_ref_ld_val[5:0]" group.word 0x4424++0x1 line.word 0x0 "LANE1_DIG_ASIC_RX_OVRD_IN_2,Override values for incoming RX controls from ASIC. register #2" newline rbitfld.word 0x0 14.--15. "RESERVED_15_14,Reserved for Future use" "0,1,2,3" newline bitfld.word 0x0 13. "EN,Enable override values for all inputs controlled by this register" "0,1" newline hexmask.word 0x0 0.--12. 1. "RX_VCO_LD_VAL,Override value for rx_vco_ld_val" group.word 0x4428++0x1 line.word 0x0 "LANE1_DIG_ASIC_RX_OVRD_IN_3,Override values for incoming RX controls from ASIC. register #3" newline rbitfld.word 0x0 15. "RESERVED_15_15,Reserved for Future use" "0,1" newline bitfld.word 0x0 14. "LOS_OVRD_EN,Enable override for rx_los_lfps_en and rx_los_threshold" "0,1" newline bitfld.word 0x0 13. "LOS_LPFS_EN,Override value for rx_los_lfps_en" "0,1" newline bitfld.word 0x0 10.--12. "LOS_THRSHLD,Override value for rx_los_threshold" "0,1,2,3,4,5,6,7" newline bitfld.word 0x0 9. "DISABLE_OVRD_EN,Enable override for rx_disable" "0,1" newline bitfld.word 0x0 8. "DISABLE,Override value for rx_disable" "0,1" newline bitfld.word 0x0 7. "CLK_SHIFT_OVRD_EN,Enable override for rx_clk_shift" "0,1" newline bitfld.word 0x0 6. "CLK_SHIFT,Override value for rx_clk_shift" "0,1" newline bitfld.word 0x0 5. "ALIGN_EN_OVRD_EN,Enable override for rx_align_en" "0,1" newline bitfld.word 0x0 4. "ALIGN_EN,Override value for rx_align_en" "0,1" newline bitfld.word 0x0 3. "CDR_SSC_EN_OVRD_EN,Enable override value for rx_cdr_ssc_en" "0,1" newline bitfld.word 0x0 2. "CDR_SSC_EN,Override value for rx_cdr_ssc_en" "0,1" newline bitfld.word 0x0 1. "CDR_TRACK_EN_OVRD_EN,Enable override value for rx_cdr_track_en" "0,1" newline bitfld.word 0x0 0. "CDR_TRACK_EN,Override value for rx_cdr_track_en" "0,1" group.word 0x442C++0x1 line.word 0x0 "LANE1_DIG_ASIC_RX_OVRD_IN_4,Override values for incoming RX controls from ASIC. register #4" newline hexmask.word.byte 0x0 10.--15. 1. "RESERVED_15_10,Reserved for Future use" newline bitfld.word 0x0 9. "TERM_OVRD_EN,Enable override for rx_term_acdc and rx_term_en" "0,1" newline bitfld.word 0x0 8. "TERM_ACDC,Override value for rx_term_acdc" "0,1" newline bitfld.word 0x0 7. "TERM_EN,Override value for rx_term_en" "0,1" newline bitfld.word 0x0 6. "ADPT_OVRD_EN,Enable override for rx_adpt_dfe_en and rx_adpt_afe_en" "0,1" newline bitfld.word 0x0 5. "ADAPT_DFE_EN,Override value for rx_adapt_dfe_en" "0,1" newline bitfld.word 0x0 4. "ADAPT_AFE_EN,Override value for rx_adapt_afe_en" "0,1" newline bitfld.word 0x0 3. "INVERT_OVRD_EN,Enable override for rx_invert" "0,1" newline bitfld.word 0x0 2. "INVERT,Override value for rx_invert" "0,1" newline bitfld.word 0x0 1. "LPD_OVRD_EN,Enable override for rx_lpd" "0,1" newline bitfld.word 0x0 0. "LPD,Override value for rx_lpd" "0,1" group.word 0x4430++0x1 line.word 0x0 "LANE1_DIG_ASIC_RX_OVRD_IN_5,Override values for incoming RX controls from ASIC. register #5" newline hexmask.word 0x0 2.--15. 1. "RESERVED_15_2,Reserved for Future use" newline bitfld.word 0x0 1. "RESET_OVRD_EN,Enable override for rx_reset" "0,1" newline bitfld.word 0x0 0. "RESET,Override value for rx_reset" "0,1" group.word 0x4434++0x1 line.word 0x0 "LANE1_DIG_ASIC_RX_OVRD_EQ_IN_0,Override values for incoming RX EQ controls from ASIC. register #0" newline hexmask.word.byte 0x0 11.--15. 1. "EQ_CTLE_BOOST,Override value for rx_eq_ctle_boost" newline hexmask.word.byte 0x0 7.--10. 1. "RESERVED," newline hexmask.word.byte 0x0 3.--6. 1. "EQ_AFE_GAIN,Override value for rx_eq_afe_gain" newline bitfld.word 0x0 0.--2. "EQ_ATT_LVL,Override value for rx_eq_att_lvl" "0,1,2,3,4,5,6,7" group.word 0x4438++0x1 line.word 0x0 "LANE1_DIG_ASIC_RX_OVRD_EQ_IN_1,Override values for incoming RX EQ controls from ASIC. register #1" newline bitfld.word 0x0 15. "EQ_OVRD_EN,Enable override value for rx_eq_* inputs" "0,1" newline hexmask.word.byte 0x0 7.--14. 1. "EQ_DFE_TAP1,Override value for rx_eq_dfe_tap1" newline hexmask.word.byte 0x0 0.--6. 1. "EQ_DFE_TAP2,Override value for rx_eq_dfe_tap2" group.word 0x443C++0x1 line.word 0x0 "LANE1_DIG_ASIC_RX_OVRD_OUT_0,Override values for outgoing RX controls to ASIC. register #0" newline hexmask.word 0x0 7.--15. 1. "RESERVED_15_7,Reserved for Future use" newline bitfld.word 0x0 6. "ADAPT_STS_OVRD_EN,Enable override for rx_adapt_sts" "0,1" newline bitfld.word 0x0 4.--5. "ADAPT_STS,Override value for rx_adapt_sts" "0,1,2,3" newline bitfld.word 0x0 3. "LOS_OUT_OVRD_EN,Enable override for rx_los_r" "0,1" newline bitfld.word 0x0 2. "LOS,Override value for rx_los" "0,1" newline bitfld.word 0x0 1. "ACK_OVRD_EN,Enable override for rx_ack" "0,1" newline bitfld.word 0x0 0. "ACK,Override value for rx_ack" "0,1" rgroup.word 0x4440++0x1 line.word 0x0 "LANE1_DIG_ASIC_LANE_ASIC_IN,Current values for incoming LANE controls from ASIC" newline hexmask.word 0x0 2.--15. 1. "RESERVED_15_2,Reserved for Future use" newline bitfld.word 0x0 1. "LANE_RX2TX_PAR_LB,Value from ASIC for lane_rx2tx_par_lb_en_r" "0,1" newline bitfld.word 0x0 0. "LANE_TX2RX_SER_LB,Value from ASIC for lane_tx2rx_ser_lb_en_r" "0,1" rgroup.word 0x4444++0x1 line.word 0x0 "LANE1_DIG_ASIC_TX_ASIC_IN_0,Current values for incoming TX controls from ASIC. register #0" newline bitfld.word 0x0 15. "DISABLE,Value from ASIC for tx_disable" "0,1" newline bitfld.word 0x0 14. "DETECT_RX_REQ,Value from ASIC for tx_detrx_req" "0,1" newline bitfld.word 0x0 13. "MPLLB_SEL,Value from ASIC for tx_mpllb_sel" "0,1" newline bitfld.word 0x0 11.--12. "WIDTH,Value from ASIC for tx_width[1:0]" "0,1,2,3" newline bitfld.word 0x0 8.--10. "RATE,Value from ASIC for tx_rate[2:0]" "0,1,2,3,4,5,6,7" newline bitfld.word 0x0 6.--7. "PSTATE,Value from ASIC for tx_pstate[1:0]" "0,1,2,3" newline bitfld.word 0x0 5. "LPD,Value from ASIC for tx_lpd" "0,1" newline bitfld.word 0x0 4. "REQ,Value from ASIC for tx_req" "0,1" newline bitfld.word 0x0 3. "DATA_EN,Value from ASIC for tx_data_en" "0,1" newline bitfld.word 0x0 2. "INVERT,Value from ASIC for tx_invert" "0,1" newline bitfld.word 0x0 1. "RESET,Value from ASIC for tx_reset" "0,1" newline bitfld.word 0x0 0. "CLK_RDY,Value from ASIC for tx_clk_rdy" "0,1" rgroup.word 0x4448++0x1 line.word 0x0 "LANE1_DIG_ASIC_TX_ASIC_IN_1,Current values for incoming TX controls from ASIC. register #1" newline hexmask.word.byte 0x0 12.--15. 1. "RESERVED_15_12,Reserved for Future use" newline hexmask.word.byte 0x0 6.--11. 1. "TX_MAIN_CURSOR,Value from ASIC for tx_eq_main" newline bitfld.word 0x0 5. "VBOOST_EN,Value from ASIC for tx_vboost_en" "0,1" newline hexmask.word.byte 0x0 1.--4. 1. "IBOOST_LVL,Value from ASIC for tx_iboost_lvl" newline bitfld.word 0x0 0. "BEACON_EN,Value from ASIC for tx_beacon_en" "0,1" rgroup.word 0x444C++0x1 line.word 0x0 "LANE1_DIG_ASIC_TX_ASIC_IN_2,Current values for incoming TX controls from ASIC. register #2" newline hexmask.word.byte 0x0 12.--15. 1. "RESERVED_15_12,Reserved for Future use" newline hexmask.word.byte 0x0 6.--11. 1. "TX_POST_CURSOR,Value from ASIC for tx_eq_post" newline hexmask.word.byte 0x0 0.--5. 1. "TX_PRE_CURSOR,Value from ASIC for tx_eq_pre" rgroup.word 0x4450++0x1 line.word 0x0 "LANE1_DIG_ASIC_TX_ASIC_OUT,Current values for outgoing TX status controls from PHY" newline hexmask.word 0x0 2.--15. 1. "RESERVED_15_2,Reserved for Future use" newline bitfld.word 0x0 1. "DETRX_RESULT,Value from PHY for tx_detrx_result" "0,1" newline bitfld.word 0x0 0. "TX_ACK,Value from PHY for tx_ack" "0,1" rgroup.word 0x4454++0x1 line.word 0x0 "LANE1_DIG_ASIC_RX_ASIC_IN_0,Current values for incoming RX controls from ASIC. register #0" newline bitfld.word 0x0 15. "RESERVED_15_15,Reserved for Future use" "0,1" newline bitfld.word 0x0 14. "CDR_TRACK_EN,Value from ASIC for rx_cdr_track_en" "0,1" newline bitfld.word 0x0 13. "ADAPT_DFE_EN,Value from ASIC for rx_adapt_dfe_en" "0,1" newline bitfld.word 0x0 12. "ADAPT_AFE_EN,Value from ASIC for rx_adapt_afe_en" "0,1" newline bitfld.word 0x0 11. "RESERVED," "0,1" newline bitfld.word 0x0 9.--10. "WIDTH,Value from ASIC for rx_width" "0,1,2,3" newline bitfld.word 0x0 7.--8. "RATE,Value from ASIC for rx_rate" "0,1,2,3" newline bitfld.word 0x0 5.--6. "PSTATE,Value from ASIC for rx_pstate" "0,1,2,3" newline bitfld.word 0x0 4. "LPD,Value from ASIC for rx_lpd" "0,1" newline bitfld.word 0x0 3. "REQ,Value from ASIC for rx_req" "0,1" newline bitfld.word 0x0 2. "DATA_EN,Value from ASIC for rx_data_en" "0,1" newline bitfld.word 0x0 1. "INVERT,Value from ASIC for rx_invert" "0,1" newline bitfld.word 0x0 0. "RESET,Value from ASIC for rx_reset" "0,1" rgroup.word 0x4458++0x1 line.word 0x0 "LANE1_DIG_ASIC_RX_ASIC_IN_1,Current values for incoming RX controls from ASIC. register #1" newline hexmask.word.byte 0x0 10.--15. 1. "RESERVED_15_10,Reserved for Future use" newline bitfld.word 0x0 9. "RX_TERM_ACDC,Value from ASIC for rx_term_acdc" "0,1" newline bitfld.word 0x0 8. "RX_TERM_EN,Value from ASIC for rx_term_en" "0,1" newline bitfld.word 0x0 7. "LOS_LPFS_EN,Value from ASIC for rx_los_lfps_en" "0,1" newline bitfld.word 0x0 4.--6. "LOS_THRSHLD,Value from ASIC for rx_los_threshold" "0,1,2,3,4,5,6,7" newline bitfld.word 0x0 3. "DISABLE,Value from ASIC for rx_disable" "0,1" newline bitfld.word 0x0 2. "CLK_SHIFT,Value from ASIC for rx_clk_shift" "0,1" newline bitfld.word 0x0 1. "ALIGN_EN,Value from ASIC for rx_align_en" "0,1" newline bitfld.word 0x0 0. "CDR_SSC_EN,Value from ASIC for rx_cdr_ssc_en" "0,1" rgroup.word 0x445C++0x1 line.word 0x0 "LANE1_DIG_ASIC_RX_EQ_ASIC_IN_0,Current values for incoming RX EQ controls from ASIC. register #0" newline hexmask.word.byte 0x0 11.--15. 1. "EQ_CTLE_BOOST,Value from ASIC for rx_eq_ctle_boost" newline hexmask.word.byte 0x0 7.--10. 1. "RESERVED," newline hexmask.word.byte 0x0 3.--6. 1. "EQ_AFE_GAIN,Value from ASIC for rx_eq_afe_gain" newline bitfld.word 0x0 0.--2. "EQ_ATT_LVL,Value from ASIC for rx_eq_att_lvl" "0,1,2,3,4,5,6,7" rgroup.word 0x4460++0x1 line.word 0x0 "LANE1_DIG_ASIC_RX_EQ_ASIC_IN_1,Current values for incoming RX EQ controls from ASIC. register #1" newline bitfld.word 0x0 15. "RESERVED_15_15,Reserved for Future use" "0,1" newline hexmask.word.byte 0x0 7.--14. 1. "EQ_DFE_TAP1,Value from ASIC for rx_eq_dfe_tap1" newline hexmask.word.byte 0x0 0.--6. 1. "EQ_DFE_TAP2,Value from ASIC for rx_eq_dfe_tap2" rgroup.word 0x4464++0x1 line.word 0x0 "LANE1_DIG_ASIC_RX_CDR_VCO_ASIC_IN_0,Current values for incoming RX CDR VCO controls from ASIC. register #0" newline hexmask.word.byte 0x0 8.--15. 1. "RESERVED_15_8,Reserved for Future use" newline hexmask.word.byte 0x0 1.--7. 1. "RX_REF_LD_VAL,Value from ASIC for rx_ref_ld_val" newline bitfld.word 0x0 0. "RX_CDR_VCO_LOWFREQ,Value from ASIC for rx_cdr_vco_lowfreq" "0,1" rgroup.word 0x4468++0x1 line.word 0x0 "LANE1_DIG_ASIC_RX_CDR_VCO_ASIC_IN_1,Current values for incoming RX CDR VCO controls from ASIC. register #1" newline bitfld.word 0x0 13.--15. "RESERVED_15_13,Reserved for Future use" "0,1,2,3,4,5,6,7" newline hexmask.word 0x0 0.--12. 1. "RX_VCO_LD_VAL,Value from ASIC for rx_vco_ld_val" rgroup.word 0x446C++0x1 line.word 0x0 "LANE1_DIG_ASIC_RX_ASIC_OUT_0,Current values for outgoing RX status controls from PHY. register #0" newline hexmask.word 0x0 5.--15. 1. "RESERVED_15_5,Reserved for Future use" newline bitfld.word 0x0 3.--4. "ADAPT_STS,Value from PHY for rx_adapt_sts" "0,1,2,3" newline bitfld.word 0x0 2. "VALID,Value from PHY for rx_valid" "0,1" newline bitfld.word 0x0 1. "LOS,Value from PHY for rx_los" "0,1" newline bitfld.word 0x0 0. "ACK,Value from PHY for rx_ack" "0,1" repeat 2. (list 0x0 0x1 )(list 0x0 0x8 ) group.word ($2+0x4480)++0x1 line.word 0x0 "LANE1_DIG_TX_PWRCTL_TX_PSTATE_P$1,TX Power State Control Register for P0" newline hexmask.word.byte 0x0 9.--15. 1. "RESERVED_15_9,Reserved for Future use" newline bitfld.word 0x0 8. "TX_P0_ALLOW_RXDET,If asserted then rxdet request is allowed in P0" "0,1" newline bitfld.word 0x0 7. "TX_P0_DATA_EN,This is ANDed with top-level tx_data_en asic input" "0,1" newline bitfld.word 0x0 6. "TX_P0_DIG_CLK_EN,Enable/Disable TX digital clocks in P0" "0,1" newline bitfld.word 0x0 5. "TX_P0_ANA_SERIAL_EN,Value of TX ana serial_en in P0" "0,1" newline bitfld.word 0x0 4. "TX_P0_ANA_RESET,Value of TX ana reset in P0" "0,1" newline bitfld.word 0x0 3. "TX_P0_ANA_WORD_CLK_EN,Value of TX ana word_clk_en in P0" "0,1" newline bitfld.word 0x0 2. "TX_P0_ANA_CLK_EN,Value of TX ana clk_en in P0" "0,1" newline bitfld.word 0x0 1. "TX_P0_ANA_VCM_HOLD,Value of TX ana vcm_hold in P0" "0,1" newline bitfld.word 0x0 0. "TX_P0_ANA_REFGEN_EN,Value of TX ana refgen_en in P0" "0,1" repeat.end group.word 0x4484++0x1 line.word 0x0 "LANE1_DIG_TX_PWRCTL_TX_PSTATE_P0S,TX Power State Control Register for P0S" newline hexmask.word.byte 0x0 9.--15. 1. "RESERVED_15_9,Reserved for Future use" newline bitfld.word 0x0 8. "TX_P0S_ALLOW_RXDET,If asserted then rxdet request is allowed in P0S" "0,1" newline bitfld.word 0x0 7. "TX_P0S_DATA_EN,This is ANDed with top-level tx_data_en asic input" "0,1" newline bitfld.word 0x0 6. "TX_P0S_DIG_CLK_EN,Enable/Disable TX digital clocks in P0S" "0,1" newline bitfld.word 0x0 5. "TX_P0S_ANA_SERIAL_EN,Value of TX ana serial_en in P0S" "0,1" newline bitfld.word 0x0 4. "TX_P0S_ANA_RESET,Value of TX ana reset in P0S" "0,1" newline bitfld.word 0x0 3. "TX_P0S_ANA_WORD_CLK_EN,Value of TX ana word_clk_en in P0S" "0,1" newline bitfld.word 0x0 2. "TX_P0S_ANA_CLK_EN,Value of TX ana clk_en in P0S" "0,1" newline bitfld.word 0x0 1. "TX_P0S_ANA_VCM_HOLD,Value of TX ana vcm_hold in P0S" "0,1" newline bitfld.word 0x0 0. "TX_P0S_ANA_REFGEN_EN,Value of TX ana refgen_en in P0S" "0,1" group.word 0x448C++0x1 line.word 0x0 "LANE1_DIG_TX_PWRCTL_TX_PSTATE_P2,TX Power State Control Register for P2" newline hexmask.word.byte 0x0 10.--15. 1. "RESERVED_15_10,Reserved for Future use" newline bitfld.word 0x0 9. "TX_P2_ALLOW_VBOOST,If asserted then vboost is allowed in P2" "0,1" newline bitfld.word 0x0 8. "TX_P2_ALLOW_RXDET,If asserted then rxdet request is allowed" "0,1" newline bitfld.word 0x0 7. "TX_P2_DATA_EN,This is ANDed with top-level tx_data_en asic input" "0,1" newline bitfld.word 0x0 6. "TX_P2_DIG_CLK_EN,Enable/Disable TX digital clocks in P2" "0,1" newline bitfld.word 0x0 5. "TX_P2_ANA_SERIAL_EN,Value of TX ana serial_en in P2" "0,1" newline bitfld.word 0x0 4. "TX_P2_ANA_RESET,Value of TX ana reset in P2" "0,1" newline bitfld.word 0x0 3. "TX_P2_ANA_WORD_CLK_EN,Value of TX ana word_clk_en in P2" "0,1" newline bitfld.word 0x0 2. "TX_P2_ANA_CLK_EN,Value of TX ana clk_en in P2" "0,1" newline bitfld.word 0x0 1. "TX_P2_ANA_VCM_HOLD,Value of TX ana vcm_hold in P2" "0,1" newline bitfld.word 0x0 0. "TX_P2_ANA_REFGEN_EN,Value of TX ana refgen_en in P2" "0,1" group.word 0x4490++0x1 line.word 0x0 "LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_0,TX Power UP Time Register #0" newline hexmask.word.byte 0x0 8.--15. 1. "TX_CLK_EN,Power up time (in ref_range cycles) for TX ana clock enable (spec: >=1us)" newline hexmask.word.byte 0x0 0.--7. 1. "TX_REFGEN_EN_TIME,Power up time (in ref_range cycles) for TX ana refgen enable (spec: >=500ns)" group.word 0x4494++0x1 line.word 0x0 "LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_1,TX Power UP Time Register #1" newline bitfld.word 0x0 15. "SKIP_TX_VCM_HOLD_WAIT,Skip wait for TX common mode hold power up" "0,1" newline hexmask.word 0x0 0.--14. 1. "TX_VCM_HOLD_TIME_14_0,Power up time (in ref_range cycles) for TX common mode (spec: >=800us) (bits 14:0)" group.word 0x4498++0x1 line.word 0x0 "LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_2,TX Power UP Time Register #2" newline bitfld.word 0x0 13.--15. "DTB_SEL,Selects data to drive on DTB 0 - disabled 1 - tx_ack and tx_pwrsm_state[0] 2 - tx_ana_rxdetp_result_i tx_ana_rxdetm_result_i 3 - tx_ana_reset_i tx_ana_clk_en_i 4 - analog/asic clocks 5 - asic early signal / clock aligner shift 6 - tx_clk_state.." "disabled,tx_ack and tx_pwrsm_state[0],tx_ana_rxdetp_result_i,tx_ana_reset_i,analog/asic clocks,asic early signal / clock aligner shift,tx_clk_state counter / lbert strobe,ref_dig_rst/tx_dig_rst" newline hexmask.word 0x0 0.--12. 1. "TX_VBOOST_DIS_TIME_12_0,TX vboost disable time (in ref_range cycles) (spec: >=200us) (bits 12:0)" group.word 0x449C++0x1 line.word 0x0 "LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_3,TX Power UP Time Register #3" newline hexmask.word 0x0 4.--15. 1. "RESERVED_15_4,Reserved for Future use" newline bitfld.word 0x0 3. "TX_VBOOST_DIS_TIME_13,TX vboost disable time (in ref_range cycles) (spec: >=200us) (bit 13)" "0,1" newline bitfld.word 0x0 0.--2. "TX_VCM_HOLD_TIME_17_15,Power up time (in ref_range cycles) for TX common mode (spec: >=800us) (bits 17:15)" "0,1,2,3,4,5,6,7" group.word 0x44A0++0x1 line.word 0x0 "LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_4,TX Power UP Time Register #4" newline rbitfld.word 0x0 15. "RESERVED_15_15,Reserved for Future use" "0,1" newline hexmask.word 0x0 0.--14. 1. "TX_VCM_HOLD_GS_TIME,TX common mode gear-shift time (in ref range cycles) (spec: >=400us)" group.word 0x44A4++0x1 line.word 0x0 "LANE1_DIG_TX_PWRCTL_TX_PWRUP_TIME_5,TX Power UP Time Register #5" newline rbitfld.word 0x0 15. "RESERVED_15_15,Reserved for Future use" "0,1" newline bitfld.word 0x0 13.--14. "TX_SERIAL_EN_TIME,Power up time (in ref_range cycles) for TX ana serial enable (spec: >=50ns)" "0,1,2,3" newline bitfld.word 0x0 11.--12. "TX_RESET_TIME,TX Reset deassertion time (in ref_range cycles) (spec: >=50ns)" "0,1,2,3" newline bitfld.word 0x0 10. "FAST_TX_RXDET,Enable fast TX RX-detection (simulation only)" "0,1" newline hexmask.word 0x0 0.--9. 1. "TX_RXDET_TIME,RX Detect up time (in ref_range cycles) starting from asserting rxdet_en (spec: from 3.55us to 25.9us)" group.word 0x44A8++0x1 line.word 0x0 "LANE1_DIG_TX_LBERT_CTL,Pattern Generator controls" newline rbitfld.word 0x0 15. "RESERVED_15_15,Reserved for Future use" "0,1" newline hexmask.word 0x0 5.--14. 1. "PAT0,Pattern for modes 3-5" newline bitfld.word 0x0 4. "TRIGGER_ERR,Insert a single error into a lsb Any write of a 1 to this bit will insert an error" "0,1" newline hexmask.word.byte 0x0 0.--3. 1. "MODE,Pattern to generate When changing modes you must change to disabled first 0 - Disabled 1 - lfsr31: X^31 + X^28 + 1 2 - lfsr23: X^23 + X^18 + 1 3 - lfsr23: x^23 + x^21 + x^16 + x^8 + x^5 + x^2 + 1 4 - lfsr16: x^16 + x^5 + x^4 + x^3 + 1 5 - lfsr15:.." group.word 0x44AC++0x1 line.word 0x0 "LANE1_DIG_TX_CLK_ALIGN_TX_CTL_0,TX Clock Alignment Control Register #0" newline hexmask.word.byte 0x0 9.--15. 1. "RESERVED_15_9,Reserved for Future use" newline bitfld.word 0x0 8. "TX_FIFO_BYPASS,By-pass TX datapath FIFO" "0,1" newline hexmask.word.byte 0x0 4.--7. 1. "TX_NUM_2UI_SHIFTS_20B_MODE," newline hexmask.word.byte 0x0 0.--3. 1. "TX_NUM_2UI_SHIFTS_16B_MODE," repeat 3. (list 0x0 0x1 0x2 )(list 0x0 0x8 0xC ) group.word ($2+0x4500)++0x1 line.word 0x0 "LANE1_DIG_RX_PWRCTL_RX_PSTATE_P$1,RX Power State Control Register for P0" newline hexmask.word.byte 0x0 12.--15. 1. "RESERVED_15_12,Reserved for Future use" newline bitfld.word 0x0 11. "RX_P0_DIG_CLK_EN,Enable/Disable RX digital clocks in P0" "0,1" newline bitfld.word 0x0 10. "RX_P0_VCO_CONTCAL_EN,Enable/Disable continous calibration of the RX VCO in P0 If RX_P0_DIG_CLK_EN and the top-level rx_data_en are both asserted then contiuous calibration is turned off and this value is ignored" "0,1" newline bitfld.word 0x0 9. "RX_P0_VCO_CAL_RST,Enable/Disable resetting the RX VCO in P0" "0,1" newline bitfld.word 0x0 8. "RX_P0_VCO_FREQ_RST,Enable/Disable resetting the RX VCO frequency in P0" "0,1" newline bitfld.word 0x0 7. "RX_P0_ANA_CDR_EN,Value of RX ana cdr_en in P0" "0,1" newline bitfld.word 0x0 6. "RX_P0_ANA_DESER_EN,Value of RX ana deserial_en in P0" "0,1" newline bitfld.word 0x0 5. "RX_P0_ANA_CLK_DCC_EN,Value of RX ana CLK_DCC_EN in P0" "0,1" newline bitfld.word 0x0 4. "RX_P0_ANA_CLK_EN,Value of RX ana clk_en in P0" "0,1" newline bitfld.word 0x0 3. "RESERVED," "0,1" newline bitfld.word 0x0 2. "RX_P0_ANA_CLK_VREG_EN,Value of RX ana clk_vreg_en in P0" "0,1" newline bitfld.word 0x0 1. "RX_P0_ANA_AFE_EN,Value of RX ana afe_en in P0" "0,1" newline bitfld.word 0x0 0. "RX_P0_ANA_LOS_EN,Value of RX ana los_en in P0" "0,1" repeat.end group.word 0x4504++0x1 line.word 0x0 "LANE1_DIG_RX_PWRCTL_RX_PSTATE_P0S,RX Power State Control Register for P0S" newline hexmask.word.byte 0x0 12.--15. 1. "RESERVED_15_12,Reserved for Future use" newline bitfld.word 0x0 11. "RX_P0S_DIG_CLK_EN,Enable/Disable RX digital clocks in P0S" "0,1" newline bitfld.word 0x0 10. "RX_P0S_VCO_CONTCAL_EN,Enable/Disable continous calibration of the RX VCO in P0S If RX_P0S_DIG_CLK_EN and the top-level rx_data_en are both asserted then contiuous calibration is turned off and this value is ignored" "0,1" newline bitfld.word 0x0 9. "RX_P0S_VCO_CAL_RST,Enable/Disable resetting the RX VCO in P0S" "0,1" newline bitfld.word 0x0 8. "RX_P0S_VCO_FREQ_RST,Enable/Disable resetting the RX VCO frequency in P0S" "0,1" newline bitfld.word 0x0 7. "RX_P0S_ANA_CDR_EN,Value of RX ana cdr_en in P0S" "0,1" newline bitfld.word 0x0 6. "RX_P0S_ANA_DESER_EN,Value of RX ana deserial_en in P0S" "0,1" newline bitfld.word 0x0 5. "RX_P0S_ANA_CLK_DCC_EN,Value of RX ana CLK_DCC_EN in P0S" "0,1" newline bitfld.word 0x0 4. "RX_P0S_ANA_CLK_EN,Value of RX ana clk_en in P0S" "0,1" newline bitfld.word 0x0 3. "RESERVED," "0,1" newline bitfld.word 0x0 2. "RX_P0S_ANA_CLK_VREG_EN,Value of RX ana clk_vreg_en in P0S" "0,1" newline bitfld.word 0x0 1. "RX_P0S_ANA_AFE_EN,Value of RX ana afe_en in P0S" "0,1" newline bitfld.word 0x0 0. "RX_P0S_ANA_LOS_EN,Value of RX ana los_en in P0S" "0,1" group.word 0x4510++0x1 line.word 0x0 "LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_0,RX Power UP Time Register #0" newline hexmask.word.byte 0x0 10.--15. 1. "RESERVED_15_10,Reserved for Future use" newline bitfld.word 0x0 9. "SKIP_RX_LOS_EN_WAIT,Skip wait for RX LOS enable" "0,1" newline hexmask.word 0x0 0.--8. 1. "RX_LOS_EN_TIME,Power up time (in ref_range cycles) for RX ana los enable (spec >=10us)" group.word 0x4514++0x1 line.word 0x0 "LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_1,RX Power UP Time Register #1" newline rbitfld.word 0x0 14.--15. "RESERVED_15_14,Reserved for Future use" "0,1,2,3" newline bitfld.word 0x0 13. "FAST_RX_VREG_EN,Enable fast RX VREG enable (simulation only)" "0,1" newline hexmask.word.byte 0x0 7.--12. 1. "RX_VREG_EN_TIME,Power up time (in ref_range cycles) for RX ana vreg enable (spec 500ns)" newline bitfld.word 0x0 6. "FAST_RX_AFE_EN,Enable fast RX AFE enable (simulation only)" "0,1" newline hexmask.word.byte 0x0 0.--5. 1. "RX_AFE_EN_TIME,Power up time (in ref_range cycles) for RX ana AFE enable (spec >=1us)" group.word 0x4518++0x1 line.word 0x0 "LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_2,RX Power UP Time Register #2" newline hexmask.word 0x0 7.--15. 1. "RESERVED_15_7,Reserved for Future use" newline bitfld.word 0x0 6. "FAST_RX_CLK_EN,Enable fast RX clock enable (simulation only)" "0,1" newline hexmask.word.byte 0x0 0.--5. 1. "RX_CLK_EN_TIME,Power up time (in ref_range cycles) for RX ana clk (or dcc) enable (spec >1us)" group.word 0x451C++0x1 line.word 0x0 "LANE1_DIG_RX_PWRCTL_RX_PWRUP_TIME_3,RX Power UP Time Register #3" newline bitfld.word 0x0 14.--15. "RX_DESER_DIS_TIME,Power down time in (ref_range cycles) for RX ana deserial enable" "0,1,2,3" newline bitfld.word 0x0 12.--13. "RX_DESER_EN_TIME,Power up time (in ref_range cycles) for RX ana deserial enable" "0,1,2,3" newline hexmask.word.byte 0x0 8.--11. 1. "RX_CDR_EN_TIME,Power up time (in ref_range cycles) for RX ana cdr (or dfe/dfe_taps) enable (spec 0ns)" newline hexmask.word.byte 0x0 2.--7. 1. "RSVD_3_7_2,Reserved" newline bitfld.word 0x0 0.--1. "RX_RATE_TIME,Power up time (in ref_range cycles) for RX ana rate or width change" "0,1,2,3" group.word 0x4520++0x1 line.word 0x0 "LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_0,RX VCO calibration controls register #0" newline hexmask.word.byte 0x0 12.--15. 1. "RESERVED_15_12,Reserved for Future use" newline bitfld.word 0x0 9.--11. "INT_GAIN_CAL_BOUNCE_CNT,Number of bounces (i.e. direction changes) on the int_gain code before indicating that the RX VCO calibration is done" "0,1,2,3,4,5,6,7" newline bitfld.word 0x0 6.--8. "INT_GAIN_CAL_CNT_SHIFT,Number of shifts to apply to ld_cnt inputs when performing int_gain code calibration" "0,1,2,3,4,5,6,7" newline bitfld.word 0x0 5. "INT_GAIN_CAL_FIXED_CNT_EN,Enable a fixed count (instead of bounce count) for int_gain code calibration" "0,1" newline hexmask.word.byte 0x0 0.--4. 1. "INT_GAIN_CAL_FIXED_CNT,Number of steps done during int_gain code calibration when INT_GAIN_CAL_FIXED_CNT_EN is enabled." group.word 0x4524++0x1 line.word 0x0 "LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_1,RX VCO calibration controls register #1" newline hexmask.word.byte 0x0 9.--15. 1. "DTB_SEL,DTB select for RX VCO dtb signals 7'h01 - {chkfrq_en ref_dig_clk} 7'h02 - {rx_ana_cdr_vco_en_i rx_ana_cdr_startup_i} 7'h04 - {rx_vco_up dpll_freq_rst} 7'h08 - {rx_vco_contcal_en rx_vco_cal_rst} 7'h10 - {chkfrq_done vcoclk_too_fast} 7'h20 -.." newline hexmask.word.byte 0x0 5.--8. 1. "DPLL_CAL_UG,DPLL calibration update on int_gain code 3'h0 - 0 Else - (1/16)*2^(DPLL_CAL_UG-1) LSB/update Maximum DPLL_CAL_UG=10 i.e. 32 LSB/update" newline bitfld.word 0x0 4. "DISABLE_INT_CAL_MODE,When asserted then the DPLL frequency register is never modified by the RX VCO calibration FSM (even if DPLL_CAL_UG is non-zero). In this case the calibration will always be performed on the VCO freq_tune code. This allows.." "0,1" newline bitfld.word 0x0 3. "RX_VCO_CONTCAL_EN,Override value for the continous calibration enable from the RX PWRSM" "0,1" newline bitfld.word 0x0 2. "RX_VCO_CAL_RST,Override value for the calibration reset from the RX PWRSM" "0,1" newline bitfld.word 0x0 1. "RX_VCO_FREQ_RST,Override value for the frequency reset from the RX PWRSM" "0,1" newline bitfld.word 0x0 0. "RX_VCO_OVRD_SEL,Override the calibration controls from the RX PWRSM" "0,1" group.word 0x4528++0x1 line.word 0x0 "LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_CTRL_2,RX VCO calibration controls register #2" newline bitfld.word 0x0 15. "SKIP_RX_VCO_CAL,Skip RX VCO calibration altogether" "0,1" newline bitfld.word 0x0 14. "SKIP_RX_VCO_FREQ_TUNE_CAL,Skip RX VCO coarse calibration" "0,1" newline hexmask.word.byte 0x0 10.--13. 1. "FREQ_TUNE_CAL_STEPS,Number of cal steps of freq tune" newline hexmask.word 0x0 0.--9. 1. "FREQ_TUNE_START_VAL,Starting value of freq tune code" group.word 0x452C++0x1 line.word 0x0 "LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_0,RX Power UP Time Register #0" newline bitfld.word 0x0 15. "FAST_RX_VCO_WAIT,Enable fast RX VCO power up (simulation only)" "0,1" newline hexmask.word.byte 0x0 11.--14. 1. "RX_VCO_CNTR_PWRUP_TIME,Power up time (in ref_range cycles) for Rx ana vco cnter (spec >200ns)" newline hexmask.word.byte 0x0 7.--10. 1. "RX_VCO_UPDATE_TIME,Settle time (in ref_range cycles) for RX ana vco update (freq_tune or int_gain) (spec >200ns)" newline hexmask.word.byte 0x0 0.--6. 1. "RX_VCO_STARTUP_TIME,Power up time (in ref_range cycles) for RX ana vco startup (spec >1us)" group.word 0x4530++0x1 line.word 0x0 "LANE1_DIG_RX_VCOCAL_RX_VCO_CAL_TIME_1,RX Power UP Time Register #1" newline hexmask.word 0x0 3.--15. 1. "RESERVED_15_3,Reserved for Future use" newline bitfld.word 0x0 0.--2. "RX_VCO_CNTR_SETTLE_TIME,RX VCO counter value settling time in (ref_dig_clk cycles) (spec: 3 ref_dig_clk cycle)" "0,1,2,3,4,5,6,7" rgroup.word 0x4534++0x1 line.word 0x0 "LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_0,RX VCO status register #0" newline bitfld.word 0x0 14.--15. "RESERVED_15_14,Reserved for Future use" "0,1,2,3" newline bitfld.word 0x0 13. "RX_ANA_CDR_VCO_EN,Current value of rx_ana_cdr_vco_en_i" "0,1" newline bitfld.word 0x0 12. "RX_ANA_CDR_STARTUP,Current value of rx_ana_cdr_startup_i" "0,1" newline bitfld.word 0x0 11. "RX_ANA_VCO_CNTR_EN,Current value of rx_ana_vco_cntr_en_i" "0,1" newline bitfld.word 0x0 10. "RX_ANA_VCO_CNTR_PD,Current value of rx_ana_vco_cntr_pd_i" "0,1" newline hexmask.word 0x0 0.--9. 1. "RX_ANA_CDR_FREQ_TUNE,Current value of rx_ana_cdr_freq_tune_i" rgroup.word 0x4538++0x1 line.word 0x0 "LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_1,RX VCO status register #1" newline hexmask.word.byte 0x0 9.--15. 1. "RESERVED_15_9,Reserved for Future use" newline bitfld.word 0x0 8. "DPLL_FREQ_RST,Indicates that the RX integral frequency is reset or not" "0,1" newline bitfld.word 0x0 7. "RX_VCO_CAL_DONE,Indicates that the RX VCO has completed calibration" "0,1" newline bitfld.word 0x0 6. "RX_VCO_CONTCAL_EN,Value of the continous calibration enable from the RX PWRSM" "0,1" newline bitfld.word 0x0 5. "RX_VCO_CAL_RST,Value of the calibration reset from the RX PWRSM" "0,1" newline bitfld.word 0x0 4. "RX_VCO_FREQ_RST,Value of the RX VCO frequency reset from the RX PWRSM" "0,1" newline hexmask.word.byte 0x0 0.--3. 1. "RX_VCO_FSM_STATE,Value of the RX VCO CAL FSM" rgroup.word 0x453C++0x1 line.word 0x0 "LANE1_DIG_RX_VCOCAL_RX_VCO_STAT_2,RX VCO status register #2" newline bitfld.word 0x0 15. "RX_VCO_UP,Indicates that the RX VCO is ready" "0,1" newline bitfld.word 0x0 14. "RX_VCO_CORRECT,Indicates that the RX VCO clock has the correct frequency" "0,1" newline bitfld.word 0x0 13. "VCOCLK_TOO_FAST,Indicates that the RX VCO clock frequency is too fast" "0,1" newline hexmask.word 0x0 0.--12. 1. "VCO_CNTR_FINAL,Value of Rx VCO counter when refclk counter expired" group.word 0x4540++0x1 line.word 0x0 "LANE1_DIG_RX_RX_ALIGN_XAUI_COMM_MASK,XAUI_COMMA Mask" newline hexmask.word.byte 0x0 10.--15. 1. "RESERVED_15_10,Reserved for Future use" newline hexmask.word 0x0 0.--9. 1. "XAUI_COMM_MASK,XAUI_COMMA Mask. For 10-bit COMMA set the mask to 0x3FF and for 7-bit COMMA set the mask to 0x3F8" group.word 0x4544++0x1 line.word 0x0 "LANE1_DIG_RX_LBERT_CTL,Pattern Matcher controls" newline hexmask.word 0x0 5.--15. 1. "RESERVED_15_5,Reserved for Future use" newline bitfld.word 0x0 4. "SYNC,Synchronize pattern matcher LFSR with incoming data A write of a one to this bit will reset the error counter and start a synchronization of the PM. There is no need to write this back to zero to run normally." "0,1" newline hexmask.word.byte 0x0 0.--3. 1. "MODE,Pattern to match When changing modes you must change to disabled first 0 - Disabled 1 - lfsr31: X^31 + X^28 + 1 2 - lfsr23: X^23 + X^18 + 1 3 - lfsr23: x^23 + x^21 + x^16 + x^8 + x^5 + x^2 + 1 4 - lfsr16: x^16 + x^5 + x^4 + x^3 + 1 5 - lfsr15: X^15.." group.word 0x4548++0x1 line.word 0x0 "LANE1_DIG_RX_LBERT_ERR,Pattern match error counter" newline bitfld.word 0x0 15. "OV14,If active multiply COUNT by 128. If OV14=1 and COUNT=2^15-1 signals overflow of counter (2 reads needed to read value)" "0,1" newline hexmask.word 0x0 0.--14. 1. "COUNT,A read of this register or a sync of the PM resets the error count. Current error count If OV14 field is active then multiply count by 128 (2 reads needed to read value)" group.word 0x454C++0x1 line.word 0x0 "LANE1_DIG_RX_CDR_CDR_CTL_0,Control bits for receiver in recovered domain" newline hexmask.word.byte 0x0 11.--15. 1. "RESERVED_15_11,Reserved for Future use" newline hexmask.word.byte 0x0 7.--10. 1. "DTB_SEL,Select to drive various signals onto the dtb 0 - disabled 1 - rx_pr_stable rx_afe_stable from rx_ana_ctl 2 - com_good com_bad from rx_align 3 - shift_in_prog ana_odd_data from rx_align 4 - 2 msb's of XAUI align FSM state 5 - 2 lsb's of XAUI.." newline bitfld.word 0x0 6. "ALWAYS_REALIGN,Realign on any misaligned comma" "0,1" newline bitfld.word 0x0 5. "PHDET_EN_PR_MODE,Enable partial response phase detector mode" "0,1" newline bitfld.word 0x0 4. "PHDET_POL,Reverse polarity of phase error" "0,1" newline bitfld.word 0x0 2.--3. "PHDET_EDGE,Edges to use for phase detection. 10 - Use both edges 01 - Use rising edges only 11 - Use falling edges only 00 - Ignore all edges" "Ignore all edges,Use rising edges only,?,?" newline bitfld.word 0x0 0.--1. "PHDET_EN,Enable phase detector. top bit is odd slicers bottom is even" "0,1,2,3" group.word 0x4550++0x1 line.word 0x0 "LANE1_DIG_RX_CDR_CDR_CTL_1,CDR Control Register #1" newline hexmask.word.byte 0x0 10.--15. 1. "SSC_OFF_CNT1,When SSC mode is disabled the 12-bit word count in gain stage 1 is: (SSC_OFF_CNT1 * 4) in 20b mode (SSC_OFF_CNT1 * 5) in 16b mode" newline hexmask.word 0x0 0.--9. 1. "SSC_OFF_CNT0,When SSC mode is disabled the 12-bit word count in gain stage 0 is: (SSC_OFF_CNT0 * 4) in 20b mode (SSC_OFF_CNT0 * 5) in 16b mode" group.word 0x4554++0x1 line.word 0x0 "LANE1_DIG_RX_CDR_CDR_CTL_2,CDR Control Register #2" newline hexmask.word.byte 0x0 9.--15. 1. "SSC_ON_CNT1,When SSC mode is enabled the 12-bit word count in gain stage 1 is: (SSC_ON_CNT1 * 8) in 20b mode (SSC_ON_CNT1 * 10) in 16b mode" newline hexmask.word 0x0 0.--8. 1. "SSC_ON_CNT0,When SSC mode is enabled the 12-bit word count in gain stage 0 is: (SSC_ON_CNT0 * 8) in 20b mode (SSC_ON_CNT0 * 10) in 16b mode" group.word 0x4558++0x1 line.word 0x0 "LANE1_DIG_RX_CDR_CDR_CTL_3,CDR Control Register #3" newline bitfld.word 0x0 13.--15. "FRUG_OVRD_VALUE,Override value for FRUG (frequency update gain) 3'h0 - 0 3'h1 - 1/16 LSB/update 3'h2 - 1/8 LSB/update 3'h3 - 1/4 LSB/update 3'h4 - 1/2 LSB/update 3'h5 - 1 LSB/update 3'h6 - 2 LSB/update 3'h7 - 4 LSB/update" "0,1,2,3,4,5,6,7" newline bitfld.word 0x0 10.--12. "PHUG_OVRD_VALUE,Override value for PHUG (phase update gain) 3'h0 - 0 3'h1 - 1000 ppm 3'h2 - 2000 ppm 3'h3 - 3000 ppm 3'h4 - 4000 ppm 3'h5 - 5000 ppm 3'h6 - 6000 ppm 3'h7 - 7000 ppm" "0,1,2,3,4,5,6,7" newline bitfld.word 0x0 9. "OVRD_DPLL_GAIN,Override PHUG and FRUG values" "0,1" newline bitfld.word 0x0 6.--8. "SSC_OFF_FRUG0,When SSC mode is disabled the frug value in gain stage 0 is SSC_OFF_FRUG0" "0,1,2,3,4,5,6,7" newline bitfld.word 0x0 3.--5. "SSC_OFF_PHUG1,When SSC mode is disabled the phug value in gain stage 1 is SSC_OFF_PHUG1" "0,1,2,3,4,5,6,7" newline bitfld.word 0x0 0.--2. "SSC_OFF_PHUG0,When SSC mode is disabled the phug value in gain stage 0 is SSC_OFF_PHUG0" "0,1,2,3,4,5,6,7" group.word 0x455C++0x1 line.word 0x0 "LANE1_DIG_RX_CDR_CDR_CTL_4,CDR Control Register #4" newline rbitfld.word 0x0 15. "RESERVED_15_15,Reserved for Future use" "0,1" newline bitfld.word 0x0 12.--14. "SSC_ON_PHUG1,When SSC mode is enabled the phug value in gain stage 1 is SSC_ON_PHUG1" "0,1,2,3,4,5,6,7" newline bitfld.word 0x0 9.--11. "SSC_ON_PHUG0,When SSC mode is enabled the phug value in gain stage 0 is SSC_ON_PHUG0" "0,1,2,3,4,5,6,7" newline bitfld.word 0x0 6.--8. "SSC_ON_FRUG1,When SSC mode is enabled the frug value in gain stage 1 is SSC_ON_FRUG1" "0,1,2,3,4,5,6,7" newline bitfld.word 0x0 3.--5. "SSC_ON_FRUG0,When SSC mode is enabled the frug value in gain stage 0 is SSC_ON_FRUG0" "0,1,2,3,4,5,6,7" newline bitfld.word 0x0 0.--2. "SSC_OFF_FRUG1,When SSC mode is disabled the frug value in gain stage 1 is SSC_OFF_FRUG1" "0,1,2,3,4,5,6,7" rgroup.word 0x4560++0x1 line.word 0x0 "LANE1_DIG_RX_CDR_STAT,Current output values to dpll (phug. frug)" newline hexmask.word 0x0 6.--15. 1. "RESERVED_15_6,Reserved for Future use" newline bitfld.word 0x0 3.--5. "FRUG_VALUE,NOTES: Current value for dpll_frug[2:0]" "0,1,2,3,4,5,6,7" newline bitfld.word 0x0 0.--2. "PHUG_VALUE,NOTES: Current value for dpll_phug[2:0]" "0,1,2,3,4,5,6,7" group.word 0x4564++0x1 line.word 0x0 "LANE1_DIG_RX_DPLL_FREQ,Current frequency integrator value." newline rbitfld.word 0x0 14.--15. "RESERVED_15_14,Reserved for Future use" "0,1,2,3" newline hexmask.word 0x0 0.--13. 1. "VAL,Freq is 125*VAL ppm from the reference (2 reads needed to read value)" group.word 0x4568++0x1 line.word 0x0 "LANE1_DIG_RX_DPLL_FREQ_BOUND_0,Frequency Bounds for incoming data stream #0" newline hexmask.word.byte 0x0 11.--15. 1. "RESERVED_15_11,Reserved for Future use" newline hexmask.word 0x0 1.--10. 1. "UPPER_FREQ_BOUND,Upper frequency bound in terms of LSBs of the integral control code" newline bitfld.word 0x0 0. "FREQ_BOUND_EN,Enable the frequency bounds feature" "0,1" group.word 0x456C++0x1 line.word 0x0 "LANE1_DIG_RX_DPLL_FREQ_BOUND_1,Frequency Bounds for incoming data stream #1" newline hexmask.word.byte 0x0 10.--15. 1. "RESERVED_15_10,Reserved for Future use" newline hexmask.word 0x0 0.--9. 1. "LOWER_FREQ_BOUND,Lower frequency bound in terms of LSBs of the integral control code" group.word 0x4580++0x1 line.word 0x0 "LANE1_DIG_RX_ADPTCTL_ADPT_CFG_0,Adaptation Configuration Register #0" newline bitfld.word 0x0 15. "ADPT_CLK_DIV4_EN,Set the adaptation clock to be divided by 4 (default is div2)" "0,1" newline bitfld.word 0x0 14. "START_ASM1,Start adaptation state machine #1 (VGA CTLE DFE EYEH) This register-bit is self-clearing" "0,1" newline hexmask.word.byte 0x0 10.--13. 1. "N_TGG_ASM1,Number of toggle loop iterations for ASM1" newline hexmask.word 0x0 0.--9. 1. "N_TOP_ASM1,Number of top level loop iterations for ASM1" group.word 0x4584++0x1 line.word 0x0 "LANE1_DIG_RX_ADPTCTL_ADPT_CFG_1,Adaptation Configuration Register #1" newline hexmask.word.byte 0x0 12.--15. 1. "RESERVED_15_12,Reserved for Future use" newline bitfld.word 0x0 11. "CTLE_POLE_OVRD_EN,Override CTLE pole value (only valid if adaptation is run)" "0,1" newline bitfld.word 0x0 8.--10. "CTLE_POLE_OVRD_VAL,CTLE Pole override value to load at start of adaptation" "0,1,2,3,4,5,6,7" newline bitfld.word 0x0 7. "FAST_AFE_DFE_SETTLE,Enable fast AFE and DFE settling time (simulation only)" "0,1" newline hexmask.word.byte 0x0 0.--6. 1. "N_WAIT_ASM1,Number of wait cycles for Adaptation SM #1" group.word 0x4588++0x1 line.word 0x0 "LANE1_DIG_RX_ADPTCTL_ADPT_CFG_2,Adaptation Configuration Register #2" newline hexmask.word.byte 0x0 10.--15. 1. "RESERVED_15_10,Reserved for Future use" newline hexmask.word.byte 0x0 5.--9. 1. "TGG_PTTRN_1,Pattern for the second toggle loop Error slicer is moved upward by Data tap1 if this pattern is matched" newline hexmask.word.byte 0x0 0.--4. 1. "TGG_PTTRN_0,Pattern for the first toggle loop Error slicer is moved downward by Data tap1 if this pattern is matched" group.word 0x458C++0x1 line.word 0x0 "LANE1_DIG_RX_ADPTCTL_ADPT_CFG_3,Adaptation Configuration Register #3" newline bitfld.word 0x0 15. "ESL_TWICE_DSL,Assert if error slicer has twice the voltage range as the data slicer (for the same 8 bits)." "0,1" newline bitfld.word 0x0 14. "TGG_EN,Enable toggling of the error slicer" "0,1" newline bitfld.word 0x0 13. "EYEHO_EN,Enable eye height measurement using odd error slicer" "0,1" newline bitfld.word 0x0 12. "EYEHE_EN,Enable eye height measurement using even error slicer" "0,1" newline hexmask.word.byte 0x0 7.--11. 1. "DFE_EN,Enable DFE adaptation for taps 5-1" newline bitfld.word 0x0 6. "ATT_EN,Enable ATT adaptation" "0,1" newline bitfld.word 0x0 5. "VGA_EN,Enable VGA adaptation" "0,1" newline hexmask.word.byte 0x0 0.--4. 1. "CTLE_EN,Enable CTLE boost adaptation The five bits determine which correlators are used to adapt the CTLE" repeat 2. (list 0x4 0x5 )(list 0x0 0x4 ) group.word ($2+0x4590)++0x1 line.word 0x0 "LANE1_DIG_RX_ADPTCTL_ADPT_CFG_$1,Adaptation Configuration Register #4" newline hexmask.word.byte 0x0 12.--15. 1. "DFE2_TH,DFE Tap2 correlation decision threshold (2^N-1)" newline hexmask.word.byte 0x0 8.--11. 1. "DFE1_TH,DFE Tap1 correlation decision threshold (2^N-1)" newline hexmask.word.byte 0x0 4.--7. 1. "VGA_TH,VGA correlation decision threshold (2^N-1) During eye height measurement the VGA_TH is repurporsed for error slicer updates." newline hexmask.word.byte 0x0 0.--3. 1. "CTLE_TH,CTLE correlation decision threshold (2^N-1)" repeat.end group.word 0x4598++0x1 line.word 0x0 "LANE1_DIG_RX_ADPTCTL_ADPT_CFG_6,Adaptation Configuration Register #6" newline bitfld.word 0x0 13.--15. "ATT_LOW_TH,ATT low threshold" "0,1,2,3,4,5,6,7" newline bitfld.word 0x0 12. "VGA_SAT_CNT_STICKY,If deasserted then VGA saturation counts must be consecutive to change ATT" "0,1" newline bitfld.word 0x0 9.--11. "VGA_SAT_CNT,VGA saturation count" "0,1,2,3,4,5,6,7" newline bitfld.word 0x0 6.--8. "ATT_MU,ATT gain code update gain (2^N)" "0,1,2,3,4,5,6,7" newline bitfld.word 0x0 3.--5. "VGA_MU,VGA gain code update gain (2^N) During eye height measurement the VGA_MU is repurporsed for error slicer updates." "0,1,2,3,4,5,6,7" newline bitfld.word 0x0 0.--2. "CTLE_MU,CTLE Boost code update gain (2^N)" "0,1,2,3,4,5,6,7" group.word 0x459C++0x1 line.word 0x0 "LANE1_DIG_RX_ADPTCTL_ADPT_CFG_7,Adaptation Configuration Register #7" newline rbitfld.word 0x0 15. "RESERVED_15_15,Reserved for Future use" "0,1" newline hexmask.word.byte 0x0 10.--14. 1. "VGA_LEV_LOW,VGA level low saturation limit" newline hexmask.word.byte 0x0 5.--9. 1. "VGA_LEV_HIGH,VGA level high saturation limit" newline hexmask.word.byte 0x0 0.--4. 1. "VGA_MIN_SAT,VGA minimum saturation limit" group.word 0x45A0++0x1 line.word 0x0 "LANE1_DIG_RX_ADPTCTL_ADPT_CFG_8,Adaptation Configuration Register #8" newline rbitfld.word 0x0 15. "RESERVED_15_15,Reserved for Future use" "0,1" newline bitfld.word 0x0 12.--14. "DFE5_MU,DFE tap5 code update gain (2^N)" "0,1,2,3,4,5,6,7" newline bitfld.word 0x0 9.--11. "DFE4_MU,DFE tap4 code update gain (2^N)" "0,1,2,3,4,5,6,7" newline bitfld.word 0x0 6.--8. "DFE3_MU,DFE tap3 code update gain (2^N)" "0,1,2,3,4,5,6,7" newline bitfld.word 0x0 3.--5. "DFE2_MU,DFE tap2 code update gain (2^N)" "0,1,2,3,4,5,6,7" newline bitfld.word 0x0 0.--2. "DFE1_MU,DFE tap1 code update gain (2^N)" "0,1,2,3,4,5,6,7" group.word 0x45A4++0x1 line.word 0x0 "LANE1_DIG_RX_ADPTCTL_ADPT_CFG_9,Adaptation Configuration Register #9" newline hexmask.word.byte 0x0 8.--15. 1. "ERR_SLO_ADPT_INIT,The error odd slicer is initialized to this value at the start of a new adaptation request." newline hexmask.word.byte 0x0 0.--7. 1. "ERR_SLE_ADPT_INIT,The error even slicer is initialized to this value at the start of a new adaptation request." group.word 0x45A8++0x1 line.word 0x0 "LANE1_DIG_RX_ADPTCTL_RST_ADPT_CFG,Reset Adaptation Configuration Register" newline hexmask.word 0x0 5.--15. 1. "RESERVED_15_5,Reserved for Future use" newline bitfld.word 0x0 4. "RST_ADPT_TAP1,Reset Data Tap1 when turning off DFE adaptation (Taps 2-5 are always turned off when DFE adaptation is turned off)" "0,1" newline bitfld.word 0x0 3. "RST_ADPT_CTLE_POLE,Reset CTLE Pole when turning off AFE adaptation" "0,1" newline bitfld.word 0x0 2. "RST_ADPT_CTLE_BOOST,Reset CTLE Boost when turning off AFE adaptation" "0,1" newline bitfld.word 0x0 1. "RST_ADPT_VGA,Reset VGA when turning off AFE adaptation" "0,1" newline bitfld.word 0x0 0. "RST_ADPT_ATT,Reset ATT when turning off AFE adaptation" "0,1" rgroup.word 0x45AC++0x1 line.word 0x0 "LANE1_DIG_RX_ADPTCTL_ATT_STATUS,Value of ATT Adaptation code" newline hexmask.word.byte 0x0 9.--15. 1. "RESERVED_15_9,Reserved for Future use" newline bitfld.word 0x0 8. "ASM1_DON,Asserts when Adaptation state machine #1 is done" "0,1" newline hexmask.word.byte 0x0 0.--7. 1. "ATT_ADPT_CODE,Value of ATT adaptation code" rgroup.word 0x45B0++0x1 line.word 0x0 "LANE1_DIG_RX_ADPTCTL_VGA_STATUS,Value of VGA Adaptation code" newline hexmask.word.byte 0x0 11.--15. 1. "RESERVED_15_11,Reserved for Future use" newline bitfld.word 0x0 10. "ASM1_DONE,Asserts when Adaptation state machine #1 is done" "0,1" newline hexmask.word 0x0 0.--9. 1. "VGA_ADPT_CODE,Value of VGA adaptation code" rgroup.word 0x45B4++0x1 line.word 0x0 "LANE1_DIG_RX_ADPTCTL_CTLE_STATUS,Value of CTLE Adaptation code" newline bitfld.word 0x0 14.--15. "RESERVED_15_14,Reserved for Future use" "0,1,2,3" newline bitfld.word 0x0 13. "ASM1_DONE,Asserts when Adaptation state machine #1 is done" "0,1" newline bitfld.word 0x0 10.--12. "CTLE_POLE_ADPT_CODE,Value of CTLE Pole adaptation code" "0,1,2,3,4,5,6,7" newline hexmask.word 0x0 0.--9. 1. "CTLE_BOOST_ADPT_CODE,Value of CTLE Boost adaptation code" rgroup.word 0x45B8++0x1 line.word 0x0 "LANE1_DIG_RX_ADPTCTL_DFE_TAP1_STATUS,Value of DFE Tap1 Adaptation code" newline bitfld.word 0x0 14.--15. "RESERVED_15_14,Reserved for Future use" "0,1,2,3" newline bitfld.word 0x0 13. "ASM1_DONE,Asserts when Adaptation state machine #1 is done" "0,1" newline hexmask.word 0x0 0.--12. 1. "DFE_TAP1_ADPT_CODE,Value of DFE tap1 adaptation code" rgroup.word 0x45BC++0x1 line.word 0x0 "LANE1_DIG_RX_ADPTCTL_DFE_TAP2_STATUS,Value of DFE Tap2 Adaptation code" newline bitfld.word 0x0 13.--15. "RESERVED_15_13,Reserved for Future use" "0,1,2,3,4,5,6,7" newline bitfld.word 0x0 12. "ASM1_DONE,Asserts when Adaptation state machine #1 is done" "0,1" newline hexmask.word 0x0 0.--11. 1. "DFE_TAP2_ADPT_CODE,Value of DFE tap2 adaptation code" rgroup.word 0x45C0++0x1 line.word 0x0 "LANE1_DIG_RX_ADPTCTL_DFE_TAP3_STATUS,Value of DFE Tap3 Adaptation code" newline bitfld.word 0x0 13.--15. "RESERVED_15_13,Reserved for Future use" "0,1,2,3,4,5,6,7" newline bitfld.word 0x0 12. "ASM1_DONE,Asserts when Adaptation state machine #1 is done" "0,1" newline hexmask.word 0x0 0.--11. 1. "DFE_TAP3_ADPT_CODE,Value of DFE tap3 adaptation code" rgroup.word 0x45C4++0x1 line.word 0x0 "LANE1_DIG_RX_ADPTCTL_DFE_TAP4_STATUS,Value of DFE Tap4 Adaptation code" newline bitfld.word 0x0 13.--15. "RESERVED_15_13,Reserved for Future use" "0,1,2,3,4,5,6,7" newline bitfld.word 0x0 12. "ASM1_DONE,Asserts when Adaptation state machine #1 is done" "0,1" newline hexmask.word 0x0 0.--11. 1. "DFE_TAP4_ADPT_CODE,Value of DFE tap4 adaptation code" rgroup.word 0x45C8++0x1 line.word 0x0 "LANE1_DIG_RX_ADPTCTL_DFE_TAP5_STATUS,Value of DFE Tap5 Adaptation code" newline bitfld.word 0x0 13.--15. "RESERVED_15_13,Reserved for Future use" "0,1,2,3,4,5,6,7" newline bitfld.word 0x0 12. "ASM1_DONE,Asserts when Adaptation state machine #1 is done" "0,1" newline hexmask.word 0x0 0.--11. 1. "DFE_TAP5_ADPT_CODE,Value of DFE tap5 adaptation code" group.word 0x45CC++0x1 line.word 0x0 "LANE1_DIG_RX_ADPTCTL_DFE_DATA_EVEN_VDAC_OFST,Offset values for RX DFE Data Even vDAC" newline hexmask.word.byte 0x0 8.--15. 1. "RESERVED_15_8,Reserved for Future use" newline hexmask.word.byte 0x0 0.--7. 1. "DFE_DATA_EVEN_VDAC_OFST,Offset value for DFE Data Even vDAC" group.word 0x45D0++0x1 line.word 0x0 "LANE1_DIG_RX_ADPTCTL_DFE_DATA_ODD_VDAC_OFST,Offset values for RX DFE Data Odd vDAC" newline hexmask.word.byte 0x0 8.--15. 1. "RESERVED_15_8,Reserved for Future use" newline hexmask.word.byte 0x0 0.--7. 1. "DFE_DATA_ODD_VDAC_OFST,Offset value for DFE Data Odd vDAC" group.word 0x45D4++0x1 line.word 0x0 "LANE1_DIG_RX_ADPTCTL_RX_SLICER_CTRL_EVEN,Sets values for RX SLICER CTRL EVEN signals going to ANA" newline hexmask.word 0x0 4.--15. 1. "RESERVED_15_4,Reserved for Future use" newline hexmask.word.byte 0x0 0.--3. 1. "RX_ANA_SLICER_CTRL_E,Value for rx_ana_slicer_ctrl_e[3:0]" group.word 0x45D8++0x1 line.word 0x0 "LANE1_DIG_RX_ADPTCTL_RX_SLICER_CTRL_ODD,Sets values for RX SLICER CTRL ODD signals going to ANA" newline hexmask.word 0x0 4.--15. 1. "RESERVED_15_4,Reserved for Future use" newline hexmask.word.byte 0x0 0.--3. 1. "RX_ANA_SLICER_CTRL_O,Value for rx_ana_slicer_ctrl_o[3:0]" group.word 0x45DC++0x1 line.word 0x0 "LANE1_DIG_RX_ADPTCTL_DFE_ERROR_EVEN_VDAC_OFST,Offset values for RX DFE Error Even vDAC" newline hexmask.word.byte 0x0 8.--15. 1. "RESERVED_15_8,Reserved for Future use" newline hexmask.word.byte 0x0 0.--7. 1. "DFE_ERROR_EVEN_VDAC_OFST,Offset value for DFE Error Even vDAC" group.word 0x45E0++0x1 line.word 0x0 "LANE1_DIG_RX_ADPTCTL_DFE_ERROR_ODD_VDAC_OFST,Offset values for RX DFE Error Odd vDAC" newline hexmask.word.byte 0x0 8.--15. 1. "RESERVED_15_8,Reserved for Future use" newline hexmask.word.byte 0x0 0.--7. 1. "DFE_ERROR_ODD_VDAC_OFST,Offset value for DFE Error Odd vDAC" rgroup.word 0x45E4++0x1 line.word 0x0 "LANE1_DIG_RX_ADPTCTL_ERROR_SLICER_LEVEL,Value of Error Slicer Level" newline hexmask.word.byte 0x0 8.--15. 1. "E_SLE_LVL,Even Error Slicer Level" newline hexmask.word.byte 0x0 0.--7. 1. "E_SLO_LVL,Odd Error Slicer Level" group.word 0x45E8++0x1 line.word 0x0 "LANE1_DIG_RX_ADPTCTL_ADPT_RESET,Adaptation reset register" newline hexmask.word 0x0 1.--15. 1. "RESERVED_15_1,Reserved for Future use" newline bitfld.word 0x0 0. "RESET_ASM1,Resets adaptation state machine (ASM1) as well as the stats capture block. This is a self-clearing bit and requires re-start of ASM1." "0,1" group.word 0x4600++0x1 line.word 0x0 "LANE1_DIG_RX_STAT_LD_VAL_1,Stat load value for the sample counter #1" newline bitfld.word 0x0 15. "SC1_START,Start sample counter #1 This is a self-clearing bit" "0,1" newline hexmask.word 0x0 0.--14. 1. "SC1_LD_VAL,Sample counter #1 load value" group.word 0x4604++0x1 line.word 0x0 "LANE1_DIG_RX_STAT_DATA_MSK,Stat data mask bits [15:0]" newline hexmask.word 0x0 0.--15. 1. "DATA_MSK_15_0,Value of data_msk_r[15:0]" group.word 0x4608++0x1 line.word 0x0 "LANE1_DIG_RX_STAT_MATCH_CTL0,Stat match controls register #0" newline bitfld.word 0x0 14.--15. "SCOPE_DLY,# of clock cycle delays on scope_data_rx_clk An additional MSB is added in SCOPE_DLY_2" "0,1,2,3" newline hexmask.word.byte 0x0 10.--13. 1. "DATA_MSK_19_16,Value of data_msk_r[19:16]" newline hexmask.word.byte 0x0 5.--9. 1. "PTTRN_CR1A_4_0,Value of pattern A for 1st correlator (bits 4:0)" newline hexmask.word.byte 0x0 0.--4. 1. "PTTRN_MSK_CR1A_4_0,Value of pattern A mask for 1st correlator (bits 4:0)" group.word 0x460C++0x1 line.word 0x0 "LANE1_DIG_RX_STAT_MATCH_CTL1,Stat match controls register #1" newline hexmask.word.byte 0x0 12.--15. 1. "RESERVED_15_12,Reserved for Future use" newline bitfld.word 0x0 11. "PTTRN_CR1A_ADPT_EN,Enable ORing of adapation pattern with pattern CR1A" "0,1" newline hexmask.word.byte 0x0 6.--10. 1. "PTTRN_CR1B_4_0,Value of pattern B for 1st correlator (bits 4:0)" newline hexmask.word.byte 0x0 1.--5. 1. "PTTRN_MSK_CR1B_4_0,Value of pattern B mask for 1st correlator (bits 4:0)" newline bitfld.word 0x0 0. "PTTRN_CR1B_EN,Enable pattern B matching for 1st correlator" "0,1" group.word 0x4610++0x1 line.word 0x0 "LANE1_DIG_RX_STAT_STAT_CTL0,Stat controls register #0" newline bitfld.word 0x0 15. "SKIP_EN,Value of skip_en_r" "0,1" newline bitfld.word 0x0 14. "SC_TIMER_MODE,Sample counter operation mode 0x0 - counts number of matched samples 0x1 - counts clock cycles (i.e. a timer)" "counts number of matched samples,counts clock cycles" newline bitfld.word 0x0 13. "STAT_RXCLK_SEL,Select stat clock 0x0 - ref_range_clk 0x1 - rx_dig_clk (i.e. rx dword clk) Before changing stat_rxclk_sel_r from 1->0 the rx_dig_clk must be active (i.e. enabled)" "ref_range_clk,rx_dig_clk" newline bitfld.word 0x0 10.--12. "STAT_SRC_SEL,Select stat source input 0x0 - {20{rx_cal_result}} 0x1 - {{20{scope_data_rxclk_dly_s01}} {20{scope_data_rxclk_dly}}} 0x2 - rx_phase[39:0] 0x3 - rx_error[39:0] 0x4 - rx_data[39:0] 0x5 - rx_phdir[39:0] 0x6 - 40'hFF_FFFF_FFFF" "?,?,rx_phase[39:0],rx_error[39:0],rx_data[39:0],rx_phdir[39:0],?,?" newline hexmask.word.byte 0x0 6.--9. 1. "STAT_SHFT_SEL,Select stat source shift value 0x0 - Correlate N-1 -> N+3 (use N for offset calibration) 0x1 - Correlate N+1 -> N+5 (for taps1-5) 0x2 - Correlate N+6 -> N+10 0x3 - Correlate N+11 -> N+15 0x4 - Correlate N+16 -> N+20 0x5 - Correlate N+21 ->.." newline bitfld.word 0x0 5. "CORR_MODE_EN,Enable correlation mode" "0,1" newline bitfld.word 0x0 3.--4. "CORR_SRC_SEL,Select correlation input source 0x0 - rx_error[39:0] 0x1 - rx_phase[39:0] 0x2 - {{20{scope_data_rxclk_dly_s01}} {20{scope_data_rxclk_dly}}} 0x3 - No correlation" "rx_error[39:0],rx_phase[39:0],?,No correlation" newline bitfld.word 0x0 2. "CORR_SHFT_SEL,Select shift for phase. 0:none 1:>>1" "none,?" newline bitfld.word 0x0 1. "CORR_SHFT_SEL_VGA,Select shift for error going to VGA. 0:none 1:>>1" "none,?" newline bitfld.word 0x0 0. "RESERVED_0,Reserved bit" "0,1" group.word 0x4614++0x1 line.word 0x0 "LANE1_DIG_RX_STAT_STAT_CTL1,Stat controls register #1" newline bitfld.word 0x0 14.--15. "VLD_CTL,Gating configuration of stats collection 0x0 - ignore both cdr_valid and rx_valid 0x1 - gate stats collection with cdr_valid 0x2 - gate stats collection with rx_valid 0x3 - ignore both cdr_valid and rx_valid" "ignore both cdr_valid and rx_valid,gate stats collection with cdr_valid,gate stats collection with rx_valid,ignore both cdr_valid and rx_valid" newline bitfld.word 0x0 13. "VLD_LOSS_CLR,Clearing of stats collection upon loss of valid 0x0 - hold sample and stat counters 0x1 - clear sample and stat counters" "hold sample and stat counters,clear sample and stat counters" newline bitfld.word 0x0 11.--12. "DATA_DLY_SEL,# of clock cycle delays on rx_data[19:0] An additional MSB is added in DATA_DLY_SEL_2" "0,1,2,3" newline bitfld.word 0x0 10. "STAT_CLK_EN,Clock gate enable for stat clock" "0,1" newline bitfld.word 0x0 9. "SC_PAUSE,Pause the sample counter and stat counters" "0,1" newline bitfld.word 0x0 7.--8. "RESERVED_8_7,Reserved bits" "0,1,2,3" newline bitfld.word 0x0 6. "STAT_CNT_6_EN,Enable for stat counter 6" "0,1" newline bitfld.word 0x0 5. "STAT_CNT_5_EN,Enable for stat counter 5" "0,1" newline bitfld.word 0x0 4. "STAT_CNT_4_EN,Enable for stat counter 4" "0,1" newline bitfld.word 0x0 3. "STAT_CNT_3_EN,Enable for stat counter 3 Only counter to be enabled by default since used for offset calibration" "0,1" newline bitfld.word 0x0 2. "STAT_CNT_2_EN,Enable for stat counter 2" "0,1" newline bitfld.word 0x0 1. "STAT_CNT_1_EN,Enable for stat counter 1" "0,1" newline bitfld.word 0x0 0. "STAT_CNT_0_EN,Enable for stat counter 0" "0,1" rgroup.word 0x4618++0x1 line.word 0x0 "LANE1_DIG_RX_STAT_SMPL_CNT1,Sample Counter #1 Status" newline bitfld.word 0x0 15. "SMPL_CNT1_DONE,Status of sample counter #1" "0,1" newline hexmask.word 0x0 0.--14. 1. "SMPL_CNT1,Current value of sample counter #1" rgroup.word 0x461C++0x1 line.word 0x0 "LANE1_DIG_RX_STAT_STAT_CNT_0,Stat Counter 0 Status" newline bitfld.word 0x0 15. "SMPL_CNT1_DONE,Status of sample counter #1" "0,1" newline hexmask.word 0x0 0.--14. 1. "STAT_CNT_0,Current value of stat counter #0" rgroup.word 0x4620++0x1 line.word 0x0 "LANE1_DIG_RX_STAT_STAT_CNT_1,Stat Counter 1 Status" newline bitfld.word 0x0 15. "SMPL_CNT1_DONE,Status of sample counter #1" "0,1" newline hexmask.word 0x0 0.--14. 1. "STAT_CNT_1,Current value of stat counter #1" rgroup.word 0x4624++0x1 line.word 0x0 "LANE1_DIG_RX_STAT_STAT_CNT_2,Stat Counter 2 Status" newline bitfld.word 0x0 15. "SMPL_CNT1_DONE,Status of sample counter #1" "0,1" newline hexmask.word 0x0 0.--14. 1. "STAT_CNT_2,Current value of stat counter #2" rgroup.word 0x4628++0x1 line.word 0x0 "LANE1_DIG_RX_STAT_STAT_CNT_3,Stat Counter 3 Status" newline bitfld.word 0x0 15. "SMPL_CNT1_DONE,Status of sample counter #1" "0,1" newline hexmask.word 0x0 0.--14. 1. "STAT_CNT_3,Current value of stat counter #3" rgroup.word 0x462C++0x1 line.word 0x0 "LANE1_DIG_RX_STAT_STAT_CNT_4,Stat Counter 4 Status" newline bitfld.word 0x0 15. "SMPL_CNT1_DONE,Status of sample counter #1" "0,1" newline hexmask.word 0x0 0.--14. 1. "STAT_CNT_4,Current value of stat counter #4" rgroup.word 0x4630++0x1 line.word 0x0 "LANE1_DIG_RX_STAT_STAT_CNT_5,Stat Counter 5 Status" newline bitfld.word 0x0 15. "SMPL_CNT1_DONE,Status of sample counter #1" "0,1" newline hexmask.word 0x0 0.--14. 1. "STAT_CNT_5,Current value of stat counter #5" rgroup.word 0x4634++0x1 line.word 0x0 "LANE1_DIG_RX_STAT_STAT_CNT_6,Stat Counter 6 Status" newline bitfld.word 0x0 15. "SMPL_CNT1_DONE,Status of sample counter #1" "0,1" newline hexmask.word 0x0 0.--14. 1. "STAT_CNT_6,Current value of stat counter #6" group.word 0x4638++0x1 line.word 0x0 "LANE1_DIG_RX_STAT_CAL_COMP_CLK_CTL,Calibration Comparator Control" newline hexmask.word 0x0 6.--15. 1. "RESERVED_15_6,Reserved for Future use" newline bitfld.word 0x0 3.--5. "REF_DIV_CNT,Ref range clock count (e.g. 5'd3 = 4 ref_range cycles)" "0,1,2,3,4,5,6,7" newline bitfld.word 0x0 0.--2. "PRECHRGE_CNT,Precharge Count (e.g. 5'd1 = 2 ref_range cycles)" "0,1,2,3,4,5,6,7" repeat 4. (list 0x2 0x3 0x4 0x5 )(list 0x0 0x4 0x8 0xC ) group.word ($2+0x463C)++0x1 line.word 0x0 "LANE1_DIG_RX_STAT_MATCH_CTL$1,Stat match controls register #2" newline rbitfld.word 0x0 15. "RESERVED_15_15,Reserved for Future use" "0,1" newline hexmask.word 0x0 0.--14. 1. "PTTRN_CR1A_19_5,Value of pattern A for 1st correlator (bits 19:5)" repeat.end group.word 0x464C++0x1 line.word 0x0 "LANE1_DIG_RX_STAT_STAT_CTL2,Stat controls register #2" newline hexmask.word 0x0 2.--15. 1. "RESERVED_15_2,Reserved for Future use" newline bitfld.word 0x0 1. "SCOPE_DLY_2,Additional MSB bit for SCOPE_DLY to extend the delay range to 0->7" "0,1" newline bitfld.word 0x0 0. "DATA_DLY_SEL_2,Additional MSB bit for DATA_DLY_SEL to extend the delay range to 0->7" "0,1" group.word 0x4650++0x1 line.word 0x0 "LANE1_DIG_RX_STAT_STAT_STOP,Stat stop register" newline hexmask.word 0x0 1.--15. 1. "RESERVED_15_1,Reserved for Future use" newline bitfld.word 0x0 0. "SC1_STOP,Stop sample counters #1 and associated stat counters. This is a self-clearing bit and requires re-start of sample counter #1." "0,1" group.word 0x4680++0x1 line.word 0x0 "LANE1_DIG_ANA_TX_OVRD_OUT,Override values for TX signals going to ANA" newline bitfld.word 0x0 15. "TX_OVRD_EN,Enable override values for all outputs controlled by this register" "0,1" newline bitfld.word 0x0 14. "TX_RXDET_EN,Override value for tx_ana_rxdet_en" "0,1" newline bitfld.word 0x0 13. "TX_DIV4_EN,Override value for tx_ana_div4_en" "0,1" newline bitfld.word 0x0 12. "RESERVED," "0,1" newline bitfld.word 0x0 10.--11. "TX_ANA_DATA_RATE,Override value for tx_ana_data_rate" "0,1,2,3" newline bitfld.word 0x0 9. "TX_ANA_SERIAL_EN,Override value for tx_ana_serial_en" "0,1" newline bitfld.word 0x0 8. "TX_ANA_RESET,Override value for tx_ana_reset" "0,1" newline bitfld.word 0x0 7. "TX_ANA_MPLLB_CLK_EN,Override value for tx_ana_mpllb_clk_en" "0,1" newline bitfld.word 0x0 6. "TX_ANA_MPLLA_CLK_EN,Override value for tx_ana_mplla_clk_en" "0,1" newline bitfld.word 0x0 5. "TX_ANA_WORD_CLK_EN,Override value for tx_ana_word_clk_en" "0,1" newline bitfld.word 0x0 4. "TX_ANA_CLK_EN,Override value for tx_ana_clk_en" "0,1" newline bitfld.word 0x0 3. "TX_ANA_VCM_HOLD,Override value for tx_ana_vcm_hold" "0,1" newline bitfld.word 0x0 2. "TX_ANA_REFGEN_EN,Override value for tx_ana_refgen_en" "0,1" newline bitfld.word 0x0 1. "TX_ANA_DATA_EN,Override value for tx_ana_data_en" "0,1" newline bitfld.word 0x0 0. "TX_ANA_CLK_SHIFT,Override value for tx_ana_clk_shift" "0,1" group.word 0x4684++0x1 line.word 0x0 "LANE1_DIG_ANA_TX_TERM_CODE_OVRD_OUT,Override value for TX termination code going to ANA" newline hexmask.word.byte 0x0 12.--15. 1. "RESERVED_15_12,Reserved for Future use" newline bitfld.word 0x0 11. "TX_CLK_LB_EN,Override value for tx_ana_clk_lb_en (override enabled by TX_OVRD_EN)." "0,1" newline bitfld.word 0x0 10. "TX_TERM_OVRD_EN,Override enable for the tx_ana_term_code[9:0] signal" "0,1" newline hexmask.word 0x0 0.--9. 1. "TX_TERM_CODE,Overrides the tx_ana_term_code[9:0] signal" group.word 0x4688++0x1 line.word 0x0 "LANE1_DIG_ANA_TX_TERM_CODE_CLK_OVRD_OUT,Override value for TX termination code clocks going to ANA" newline hexmask.word 0x0 3.--15. 1. "RESERVED_15_3,Reserved for Future use" newline bitfld.word 0x0 2. "TX_TERM_CLK_SELF_CLEAR_DISABLE,Disable self-clearing for the tx_ana_term_up/dn_clk register" "0,1" newline bitfld.word 0x0 1. "TX_TERM_UP_CLK,Override for TX term UP clock This bit is self-clearing (4 cr_clks later)." "0,1" newline bitfld.word 0x0 0. "TX_TERM_DN_CLK,Override for TX term DN clock - This bit is self_clearing (4 cr_clks later)." "0,1" group.word 0x468C++0x1 line.word 0x0 "LANE1_DIG_ANA_TX_EQ_OVRD_OUT_0,Override values for TX EQ signals going to ANA register #0" newline bitfld.word 0x0 15. "TX_EQ_OVRD_EN,Override enable for tx eq signals" "0,1" newline hexmask.word 0x0 1.--14. 1. "TX_ANA_CTRL_ATTEN_13_0,Override value for tx_ana_ctrl_atten[13:0]" newline bitfld.word 0x0 0. "TX_ANA_LOAD_CLK,Override value for tx_ana_load_clk" "0,1" group.word 0x4690++0x1 line.word 0x0 "LANE1_DIG_ANA_TX_EQ_OVRD_OUT_1,Override values for TX EQ signals going to ANA register #1" newline hexmask.word 0x0 6.--15. 1. "RESERVED_15_6,Reserved for Future use" newline hexmask.word.byte 0x0 0.--5. 1. "TX_ANA_CTRL_ATTEN_19_14,Override value for tx_ana_ctrl_atten[19:14]" group.word 0x4694++0x1 line.word 0x0 "LANE1_DIG_ANA_TX_EQ_OVRD_OUT_2,Override values for TX EQ signals going to ANA register #2" newline rbitfld.word 0x0 13.--15. "RESERVED_15_13,Reserved for Future use" "0,1,2,3,4,5,6,7" newline hexmask.word.byte 0x0 7.--12. 1. "TX_ANA_CTRL_PRE,Override value for tx_ana_ctrl_pre[5:0]" newline hexmask.word.byte 0x0 0.--6. 1. "RESERVED," group.word 0x4698++0x1 line.word 0x0 "LANE1_DIG_ANA_TX_EQ_OVRD_OUT_3,Override values for TX EQ signals going to ANA register #3" newline hexmask.word.byte 0x0 8.--15. 1. "RESERVED_15_8,Reserved for Future use" newline hexmask.word.byte 0x0 0.--7. 1. "TX_ANA_CTRL_POST,Override value for tx_ana_ctrl_post[7:0]" group.word 0x469C++0x1 line.word 0x0 "LANE1_DIG_ANA_RX_CTL_OVRD_OUT,Override values for RX control signals going to ANA" newline hexmask.word.byte 0x0 9.--15. 1. "RESERVED_15_9,Reserved for Future use" newline bitfld.word 0x0 8. "RX_CTL_OVRD_EN,Enable override values for outputs [8-0] below" "0,1" newline bitfld.word 0x0 7. "RX_LBK_CLK_EN,Override value for rx_ana_loopback_clk_en" "0,1" newline bitfld.word 0x0 6. "RX_ANA_ADAPTATION_EN,Override value for rx_ana_adaptation_en" "0,1" newline bitfld.word 0x0 5. "RX_ANA_DFE_TAPS_EN,Override value for rx_ana_dfe_taps_en" "0,1" newline bitfld.word 0x0 4. "RX_ANA_DIV4_EN,Override value for rx_ana_div4_en" "0,1" newline bitfld.word 0x0 3. "RX_ANA_WORD_CLK_EN,Override value for rx_ana_word_clk_en" "0,1" newline bitfld.word 0x0 1.--2. "RX_ANA_DATA_RATE,Override value for rx_ana_data_rate" "0,1,2,3" newline bitfld.word 0x0 0. "RESERVED," "0,1" group.word 0x46A0++0x1 line.word 0x0 "LANE1_DIG_ANA_RX_PWR_OVRD_OUT,Override values for RX PWR UP/DN signals going to ANA" newline hexmask.word.byte 0x0 8.--15. 1. "RESERVED_15_8,Reserved for Future use" newline bitfld.word 0x0 7. "RX_PWR_OVRD_EN,Enable override values for all outputs controlled by this register" "0,1" newline bitfld.word 0x0 6. "RX_ANA_DESERIAL_EN,Override value for rx_ana_deserial_en" "0,1" newline bitfld.word 0x0 5. "RX_ANA_CDR_EN,Override value for rx_ana_cdr_en" "0,1" newline bitfld.word 0x0 4. "RX_ANA_CLK_EN,Override value for rx_ana_clk_en" "0,1" newline bitfld.word 0x0 3. "RX_ANA_CLK_DCC_EN,Override value for rx_ana_clk_dcc_en" "0,1" newline bitfld.word 0x0 2. "RX_ANA_CLK_VREG_EN,Override value for rx_ana_clk_vreg_en" "0,1" newline bitfld.word 0x0 1. "RX_ANA_AFE_EN,Override value for rx_ana_afe_en" "0,1" newline bitfld.word 0x0 0. "RX_ANA_LOS_EN,Override value for rx_ana_los_en" "0,1" group.word 0x46A4++0x1 line.word 0x0 "LANE1_DIG_ANA_RX_VCO_OVRD_OUT_0,Override values for RX VCO signals going to ANA #0" newline bitfld.word 0x0 15. "RX_CDR_FREQ_TUNE_OVRD_EN,Enable override value for rx_ana_cdr_freq_tune" "0,1" newline bitfld.word 0x0 14. "RX_ANA_VCO_CNTR_CLK,Override value for rx_ana_vco_cntr_clk" "0,1" newline bitfld.word 0x0 13. "RX_ANA_VCO_CNTR_EN,Override value for rx_ana_vco_cntr_en" "0,1" newline hexmask.word 0x0 3.--12. 1. "RX_ANA_CDR_FREQ_TUNE,Override value for rx_ana_cdr_freq_tune" newline bitfld.word 0x0 2. "RX_VCO_CDR_OVRD_EN,Enable override values for cdr_vco_en and cdr_startup" "0,1" newline bitfld.word 0x0 1. "RX_ANA_CDR_STARTUP,Override value for rx_ana_cdr_startup" "0,1" newline bitfld.word 0x0 0. "RX_ANA_CDR_VCO_EN,Override value for rx_ana_cdr_vco_en" "0,1" repeat 2. (list 0x1 0x2 )(list 0x0 0x4 ) group.word ($2+0x46A8)++0x1 line.word 0x0 "LANE1_DIG_ANA_RX_VCO_OVRD_OUT_$1,Override values for RX VCO signals going to ANA #1" newline hexmask.word 0x0 2.--15. 1. "RESERVED_15_2,Reserved for Future use" newline bitfld.word 0x0 1. "RX_ANA_VCO_CNTR_PD,Override value for rx_ana_vco_cntr_pd" "0,1" newline bitfld.word 0x0 0. "RX_ANA_CDR_VCO_LOWFREQ,Override value for rx_ana_cdr_vco_lowfreq" "0,1" repeat.end group.word 0x46B0++0x1 line.word 0x0 "LANE1_DIG_ANA_RX_CAL,Sets values for RX CAL signals going to ANA register" newline bitfld.word 0x0 15. "RX_ANA_CAL_COMP_EN,Value for rx_ana_cal_comp_en" "0,1" newline bitfld.word 0x0 13.--14. "RX_ANA_CAL_MODE,Value for rx_ana_cal_mode[1:0] 00 Dual differential comparison ( [vip2 - vim2] greater than [vip1 - vim1] ) 01 Differential comparison on input2 (vip2 greater than vim2) 10 Single-ended comparison negative node to negative node (vim1.." "?,?,vim2] greater than [vip1,?" newline bitfld.word 0x0 12. "RX_ANA_SLICER_CAL_EN,Value for rx_ana_slicer_cal_en" "0,1" newline bitfld.word 0x0 11. "RESERVED," "0,1" newline bitfld.word 0x0 10. "RX_ANA_CAL_LPFBYP_EN,Value for rx_ana_cal_lpfbyp_en" "0,1" newline hexmask.word.byte 0x0 5.--9. 1. "RX_ANA_CAL_MUXB_SEL,Value for rx_ana_cal_muxb_sel[4:0]" newline hexmask.word.byte 0x0 0.--4. 1. "RX_ANA_CAL_MUXA_SEL,Value for rx_ana_cal_muxa_sel[4:0]" group.word 0x46B4++0x1 line.word 0x0 "LANE1_DIG_ANA_RX_DAC_CTRL,Sets values for RX DAC CTRL value going to ANA" newline hexmask.word.byte 0x0 8.--15. 1. "RESERVED_15_8,Reserved for Future use" newline hexmask.word.byte 0x0 0.--7. 1. "RX_ANA_CAL_DAC_CTRL,Value for rx_ana_cal_dac_ctrl[7:0]" group.word 0x46B8++0x1 line.word 0x0 "LANE1_DIG_ANA_RX_DAC_CTRL_OVRD,Overrides RX DAC CTRL bus (en/val/sel) going to ANA" newline hexmask.word 0x0 1.--15. 1. "RESERVED_15_1,Reserved for Future use" newline bitfld.word 0x0 0. "RX_CAL_DAC_CTRL_OVRD,Override enable for Cal DAC control" "0,1" group.word 0x46BC++0x1 line.word 0x0 "LANE1_DIG_ANA_RX_DAC_CTRL_SEL,Sets values for RX DAC CTRL Select signal going to ANA" newline hexmask.word 0x0 5.--15. 1. "RESERVED_15_5,Reserved for Future use" newline hexmask.word.byte 0x0 0.--4. 1. "RX_ANA_CAL_DAC_CTRL_SEL,Value for rx_ana_cal_dac_ctrl_sel[4:0]" group.word 0x46C0++0x1 line.word 0x0 "LANE1_DIG_ANA_RX_AFE_ATT_VGA,Value for RX AFE ATT & VGA signals going to ANA" newline hexmask.word.byte 0x0 12.--15. 1. "RESERVED_15_12,Reserved for Future use" newline bitfld.word 0x0 11. "RX_AFE_OVRD_EN,Override enable for AFE control" "0,1" newline hexmask.word.byte 0x0 7.--10. 1. "RESERVED," newline hexmask.word.byte 0x0 3.--6. 1. "RX_ANA_AFE_GAIN,Value for rx_ana_afe_gain[3:0]" newline bitfld.word 0x0 0.--2. "RX_ANA_AFE_ATT_LVL,Value for rx_ana_afe_att_lvl[2:0]" "0,1,2,3,4,5,6,7" group.word 0x46C4++0x1 line.word 0x0 "LANE1_DIG_ANA_RX_AFE_CTLE,Values for RX AFE CTLE signals going to ANA" newline hexmask.word.byte 0x0 8.--15. 1. "RESERVED_15_8,Reserved for Future use" newline hexmask.word.byte 0x0 3.--7. 1. "RX_ANA_AFE_CTLE_BOOST,Value for rx_ana_afe_ctle_boost[4:0]" newline bitfld.word 0x0 0.--2. "RESERVED," "0,1,2,3,4,5,6,7" group.word 0x46C8++0x1 line.word 0x0 "LANE1_DIG_ANA_RX_SCOPE,Values for RX SCOPE signals going to ANA" newline rbitfld.word 0x0 14.--15. "RESERVED_15_14,Reserved for Future use" "0,1,2,3" newline bitfld.word 0x0 13. "RX_SCOPE_SELF_CLEAR_DISABLE,Disable the self-clearing for rx_ana_scope_ph_clk register" "0,1" newline bitfld.word 0x0 12. "RX_ANA_SCOPE_CLK_EN,Enable the scope clocks going to the scope slicer and the lane digital part" "0,1" newline hexmask.word.byte 0x0 4.--11. 1. "RX_ANA_SCOPE_PHASE,Sets value for rx_ana_scope_phase[7:0]" newline bitfld.word 0x0 3. "RX_ANA_SCOPE_PH_CLK,Sets value for rx_ana_scope_ph_clk - This bit is self-clearing (i.e. only asserts for one cr_clk cycle)" "0,1" newline bitfld.word 0x0 1.--2. "RX_ANA_SCOPE_SEL,Sets value for rx_ana_scope_sel 00 - AFE scope selected 01 - DFE even scope selected 10 - DFE odd scope selected 11 - DFE bypass/AFE buffer scope selected" "AFE scope selected,DFE even scope selected,?,?" newline bitfld.word 0x0 0. "RX_ANA_SCOPE_EN,Sets value for rx_ana_scope_en" "0,1" group.word 0x46CC++0x1 line.word 0x0 "LANE1_DIG_ANA_RX_SLICER_CTRL,Sets values for RX Slicer Ctrl signals going to ANA register" newline hexmask.word.byte 0x0 9.--15. 1. "RESERVED_15_9,Reserved for Future use" newline bitfld.word 0x0 8. "RX_ANA_SLICER_CTRL_OVRD_EN,Override enable for Rx ANA Slicer Ctrl" "0,1" newline hexmask.word.byte 0x0 4.--7. 1. "RX_ANA_SLICER_CTRL_O,Value for rx_ana_slicer_ctrl_o[3:0]" newline hexmask.word.byte 0x0 0.--3. 1. "RX_ANA_SLICER_CTRL_E,Value for rx_ana_slicer_ctrl_e[3:0]" group.word 0x46D0++0x1 line.word 0x0 "LANE1_DIG_ANA_RX_ANA_IQ_PHASE_ADJUST,Sets values for RX ANA IQ PHASE Adjust signal going to ANA register" newline hexmask.word 0x0 7.--15. 1. "RESERVED_15_7,Reserved for Future use" newline hexmask.word.byte 0x0 0.--6. 1. "RX_ANA_IQ_PHASE_ADJUST,Value for rx_ana_iq_phase_adjust[6:0]" group.word 0x46D4++0x1 line.word 0x0 "LANE1_DIG_ANA_RX_ANA_IQ_SENSE_EN,Sets values for RX ANA IQ SENSE signal" newline hexmask.word 0x0 1.--15. 1. "RESERVED_15_1,Reserved for Future use" newline bitfld.word 0x0 0. "RX_ANA_IQ_SENSE_EN,Value for rx_ana_iq_sense_en" "0,1" group.word 0x46D8++0x1 line.word 0x0 "LANE1_DIG_ANA_RX_ANA_CAL_DAC_CTRL_EN,DAC CTRL enable signal" newline hexmask.word 0x0 2.--15. 1. "RESERVED_15_2,Reserved for Future use" newline bitfld.word 0x0 1. "DAC_CTRL_SELF_CLEAR_DISABLE,Disable self-clearing for the rx_ana_cal_dac_ctrl_en register" "0,1" newline bitfld.word 0x0 0. "RX_ANA_CAL_DAC_CTRL_EN,Value for rx_ana_cal_dac_ctrl_en - If DAC_CTRL_SELF_CLEAR_DISABLE=0 then this bit is self-clearing (i.e. only asserts for one cr_clk cycle)" "0,1" group.word 0x46DC++0x1 line.word 0x0 "LANE1_DIG_ANA_RX_ANA_SIGNALS_CHANGES_ENABLE,Afe update enable signal" newline hexmask.word 0x0 2.--15. 1. "RESERVED_15_2,Reserved for Future use" newline bitfld.word 0x0 1. "AFE_UPDATE_SELF_CLEAR_DISABLE,Disable self-clearing for the rx_ana_afe_update_en register" "0,1" newline bitfld.word 0x0 0. "RX_ANA_AFE_UPDATE_EN,Value for rx_ana_afe_update_en - If AFE_UPDATE_SELF_CLEAR_DISABLE=0 then this bit is self-clearing (i.e. only asserts for one cr_clk cycle)" "0,1" group.word 0x46E0++0x1 line.word 0x0 "LANE1_DIG_ANA_RX_ANA_PHASE_ADJUST_CLK,Phase adjust clock signal" newline hexmask.word 0x0 2.--15. 1. "RESERVED_15_2,Reserved for Future use" newline bitfld.word 0x0 1. "PHASE_ADJUST_SELF_CLEAR_DISABLE,Disable self-clearing for the rx_ana_iq_phase_adjust_clk register" "0,1" newline bitfld.word 0x0 0. "RX_ANA_IQ_PHASE_ADJUST_CLK,Value for rx_ana_iq_phase_adjust_clk - If PHASE_ADJUST_SELF_CLEAR_DISABLE=0 then this bit is self-clearing (i.e. only asserts for one cr_clk cycle)" "0,1" rgroup.word 0x46E4++0x1 line.word 0x0 "LANE1_DIG_ANA_STATUS_0,Lane input status register #0" newline hexmask.word.byte 0x0 8.--15. 1. "RESERVED_15_8,Reserved for Future use" newline bitfld.word 0x0 7. "RX_ANA_SCOPE_DATA,Value from ANA for rx_ana_scope_data" "0,1" newline bitfld.word 0x0 6. "RX_ANA_CAL_RESULT,Value from ANA for rx_ana_cal_result" "0,1" newline bitfld.word 0x0 5. "RX_ANA_LOS,Value from ANA for rx_ana_los" "0,1" newline bitfld.word 0x0 4. "TX_ANA_CLK_LB_EN,Value of tx_ana_clk_lb_en" "0,1" newline bitfld.word 0x0 3. "TX_ANA_LOOPBACK_EN,Value of tx_ana_loopback_en" "0,1" newline bitfld.word 0x0 2. "TX_ANA_RXDETM_RESULT,Value from ANA for tx_ana_rxdetm_result" "0,1" newline bitfld.word 0x0 1. "TX_ANA_RXDETP_RESULT,Value from ANA for tx_ana_rxdetp_result" "0,1" newline bitfld.word 0x0 0. "TX_ANA_CLK_SHIFT_ACK,Value from ANA for tx_ana_clk_shift_ack" "0,1" rgroup.word 0x46E8++0x1 line.word 0x0 "LANE1_DIG_ANA_STATUS_1,Lane input status register #1" newline bitfld.word 0x0 13.--15. "RESERVED_15_13,Reserved for Future use" "0,1,2,3,4,5,6,7" newline hexmask.word 0x0 0.--12. 1. "RX_ANA_VCO_CNTR,Value from ANA for rx_ana_vco_cntr" group.word 0x46EC++0x1 line.word 0x0 "LANE1_DIG_ANA_RX_TERM_CODE_OVRD_OUT,Override value for RX termination code going to ANA" newline hexmask.word 0x0 7.--15. 1. "RESERVED_15_7,Reserved for Future use" newline bitfld.word 0x0 6. "RX_TERM_OVRD_EN,Override enable for the rx_ana_term_code[5:0] signal" "0,1" newline hexmask.word.byte 0x0 0.--5. 1. "RX_TERM_CODE,Overrides the rx_ana_term_code[5:0] signal" group.word 0x46F0++0x1 line.word 0x0 "LANE1_DIG_ANA_RX_TERM_CODE_CLK_OVRD_OUT,Override value for RX termination code clock going to ANA" newline hexmask.word 0x0 2.--15. 1. "RESERVED_15_2,Reserved for Future use" newline bitfld.word 0x0 1. "RX_TERM_CLK_SELF_CLEAR_DISABLE,Disable the self-clearing of rx_ana_term_clk register" "0,1" newline bitfld.word 0x0 0. "RX_TERM_CLK,Override for TX term DN clock - This bit is self_clearing (4 cr_clks later)." "0,1" group.word 0x4700++0x1 line.word 0x0 "LANE1_ANA_TX_OVRD_MEAS,TX_OVRD_MEAS" newline hexmask.word.byte 0x0 8.--15. 1. "RESERVED_15_8,Reserved for Future use" newline bitfld.word 0x0 7. "PULL_DN_REG,Pull down TX output if asserted" "0,1" newline bitfld.word 0x0 6. "PULL_UP_REG,Pull up TX output if asserted" "0,1" newline bitfld.word 0x0 5. "VCM_HOLD_REG,Set Tx in common mode if asserted together with bit 4" "0,1" newline bitfld.word 0x0 4. "OVRD_VCM_HOLD,If asserted bit 5 take effect on control Tx common mode" "0,1" newline bitfld.word 0x0 3. "MEAS_SAMP_P,Measure clock p DCD through atb_s_p on clock psample" "0,1" newline bitfld.word 0x0 2. "MEAS_SAMP_M,Measure clock m DCD through atb_s_p on clock m sample" "0,1" newline bitfld.word 0x0 1. "CLK_SHIFT_REG,Controls clock shift if asserted with bit 0" "0,1" newline bitfld.word 0x0 0. "OVRD_CLK_SHIFT,If asserted allow analog register to control clock shift function" "0,1" group.word 0x4704++0x1 line.word 0x0 "LANE1_ANA_TX_PWR_OVRD,TX_PWR_OVRD" newline hexmask.word.byte 0x0 8.--15. 1. "RESERVED_15_8,Reserved for Future use" newline bitfld.word 0x0 7. "OVRD_EN,Enable analog register to take control TX power state if asserted" "0,1" newline bitfld.word 0x0 6. "SERIAL_EN_REG,Enable TX serializer if assered with bit 7" "0,1" newline bitfld.word 0x0 5. "CLK_EN_REG,Enable TX clock if asserted with bit 7" "0,1" newline bitfld.word 0x0 4. "DATA_EN_REG,Enable TX driver data path if asserted with bit 7" "0,1" newline bitfld.word 0x0 3. "CLK_DIV_EN_REG,Enable TX divider if asserted with bit 7 overrides !tx_reset" "0,1" newline bitfld.word 0x0 2. "REFGEN_EN_REG,Enable TX biasing if asserted with bit 7" "0,1" newline bitfld.word 0x0 1. "LOOPBACK_EN_REG,Enable TX loopback path to RX if asserted along with bit 0" "0,1" newline bitfld.word 0x0 0. "OVRD_TX_LOOPBACK,Enable Tx loopback mode over ridden by analog register if asserted" "0,1" group.word 0x4708++0x1 line.word 0x0 "LANE1_ANA_TX_ALT_BUS,TX_ALT_BUS" newline hexmask.word.byte 0x0 8.--15. 1. "RESERVED_15_8,Reserved for Future use" newline bitfld.word 0x0 7. "JTAG_DATA_REG,When bit 2 is asserted it replace jtag data" "0,1" newline bitfld.word 0x0 4.--6. "TX_ALT_RINGO,Three bit select of the ALT path test oscillators 000 no oscillators enabled 001 osc_vp_ulvt oscillator enabled 010 osc_vptx_lvt oscillator enabled 011 osc_vp_lvt oscillator enabled 100 Reserved 101 Reserved 110 Reserved 111 osc_vph_hv.." "0,1,2,3,4,5,6,7" newline bitfld.word 0x0 3. "NC3,Reserved" "0,1" newline bitfld.word 0x0 2. "OVRD_ALT_BUS,If asserted jtag data and TX data source selection are controlled by bits [1:0] and bit 7" "0,1" newline bitfld.word 0x0 0.--1. "DRV_SOURCE_REG,When bit 2 is asserted drv_source_reg[1:0] takes control of TX function overrides tx_data_source[1:0]" "0,1,2,3" repeat 2. (list 0x1 0x2 )(list 0x0 0x4 ) group.word ($2+0x470C)++0x1 line.word 0x0 "LANE1_ANA_TX_ATB$1,TX_ATB1" newline hexmask.word.byte 0x0 8.--15. 1. "RESERVED_15_8,Reserved for Future use" newline bitfld.word 0x0 7. "NC7,Reserved" "0,1" newline bitfld.word 0x0 6. "ATB_VREG1,Put TX regulator 1 output on atb_s_p when asserted" "0,1" newline bitfld.word 0x0 5. "ATB_VREG0,Put TX regulator 0 output on atb_s_p when asserted" "0,1" newline bitfld.word 0x0 4. "OVERRIDE_REGREF_0,Use atb_s_m as TX regulator 0 reference voltage when asserted" "0,1" newline bitfld.word 0x0 3. "ATB_VPTX,Put TX driver local vptx on atb_s_p when asserted" "0,1" newline bitfld.word 0x0 2. "ATB_VDCCP,Put DCC control voltage p on atb_s_p when asserted" "0,1" newline bitfld.word 0x0 1. "ATB_VDCCM,Put DCC control voltage m on atb_s_p when asserted" "0,1" newline bitfld.word 0x0 0. "ATB_GD,Put tx local gd on atb_s_p when asserted" "0,1" repeat.end group.word 0x4714++0x1 line.word 0x0 "LANE1_ANA_TX_VBOOST,TX_VBOOST" newline hexmask.word.byte 0x0 8.--15. 1. "RESERVED_15_8,Reserved for Future use" newline bitfld.word 0x0 7. "OVRD_VBOOST_EN,Enable TX boost mode to be override by bit 6" "0,1" newline bitfld.word 0x0 6. "VBOOST_EN_REG,If bit 7 is set to 1 analog register takes control of Tx vboost enable/disable" "0,1" newline bitfld.word 0x0 5. "BOOST_VPTX_MODE_N,If asserted TX boost mode becomes a direct boost mode. VdIffpp=vptx+0.05*(2.5*(1+iboost_code)*(2*tx_vboost_vref) in default TX boost mode" "0,1" newline bitfld.word 0x0 4. "ATB_VBOOST,Measure vptx/2 through atb_s_p when TX boost is enabled" "0,1" newline bitfld.word 0x0 3. "ATB_VBOOST_VREF,Measure tx boost reference voltage through atb_s_p" "0,1" newline bitfld.word 0x0 2. "OVERRIDE_VREF_BOOST_REF,If enabled atb_s_m is used to provide Tx boost reference voltage instead of bandgap voltage tx_vboost_vref" "0,1" newline bitfld.word 0x0 1. "ATB_S_ENABLE,Enables TX atb function if asserted This bit has to be set to 1 in order to make TX atb_s_p/m visible" "0,1" newline bitfld.word 0x0 0. "MEAS_ATB_VPH_HALF,Measure vph/2 on atb_s_p" "0,1" group.word 0x4718++0x1 line.word 0x0 "LANE1_ANA_TX_TERM_CODE,TX_TERM_CODE" newline hexmask.word.byte 0x0 8.--15. 1. "RESERVED_15_8,Reserved for Future use" newline hexmask.word.byte 0x0 1.--7. 1. "TERM_CODE_REG,TX leg biasing register (7 MSBs) this is Term_code_reg[9:3]" newline bitfld.word 0x0 0. "TERM_CODE_OVRD,Enable analog register to overdrive TX leg biasing" "0,1" group.word 0x471C++0x1 line.word 0x0 "LANE1_ANA_TX_TERM_CODE_CTRL,TX_TERM_CODE_CTRL" newline hexmask.word.byte 0x0 8.--15. 1. "RESERVED_15_8,Reserved for Future use" newline bitfld.word 0x0 7. "RESET_TERM_REG,Resets the tx termination code DACs" "0,1" newline bitfld.word 0x0 6. "RESET_TERM_OVRD,Enable analog register to reset termination code DACs" "0,1" newline bitfld.word 0x0 5. "UPDATE_TERM_UP_REG,Register control to update the pullup TX terminations" "0,1" newline bitfld.word 0x0 4. "UPDATE_TERM_UP_OVRD,Enables analog register control to update the pullup TX terminations" "0,1" newline bitfld.word 0x0 3. "UPDATE_TERM_DN_REG,Register control to update the pulldown TX terminations" "0,1" newline bitfld.word 0x0 2. "UPDATE_TERM_DN_OVRD,Enables analog register control to update the pulldown TX terminations" "0,1" newline bitfld.word 0x0 1. "TX_PWR_EN_REG,Register control over the power gating of blocks within the TX" "0,1" newline bitfld.word 0x0 0. "TX_PWR_EN_OVRD,Enables analog register control over the power gating of blocks within the TX" "0,1" group.word 0x4720++0x1 line.word 0x0 "LANE1_ANA_TX_IBOOST_CODE,TX_IBOOST_CODE" newline hexmask.word.byte 0x0 8.--15. 1. "RESERVED_15_8,Reserved for Future use" newline hexmask.word.byte 0x0 4.--7. 1. "IBOOST_CODE_REG,When TX boost is enabled and bit 3 is asserted these 4 bits take control of TX boost. VdIffpp=vptx+0.05*(2.5*(1+iboost_code)*(2*tx_vboost_vref-vptx/2) in default TX boost mode" newline bitfld.word 0x0 3. "IBOOST_CODE_OVRD,Enable analog register overdrive for TX boost" "0,1" newline bitfld.word 0x0 1.--2. "TERM_CODE_REG,TX leg biasing register bit 2 & 1 this is term_code_reg[2:1]" "0,1,2,3" newline bitfld.word 0x0 0. "LFPS_HIGH_PRIORITY,If asserted lfps/beacon enable has higher priority than data enable" "0,1" group.word 0x4724++0x1 line.word 0x0 "LANE1_ANA_TX_OVRD_CLK,TX_OVRD_CLK" newline hexmask.word.byte 0x0 8.--15. 1. "RESERVED_15_8,Reserved for Future use" newline bitfld.word 0x0 7. "OVRD_WORD_CLK_EN,If asserted it allows bit 6 to override tx word clock enable" "0,1" newline bitfld.word 0x0 6. "WORD_CLK_EN_REG,Tx word clock enable/disable when bit 7 is asserted" "0,1" newline bitfld.word 0x0 5. "OVRD_MPLLAB_EN,If asserted it allows bit 3 or 4 to take control of selecting MPLL clocks" "0,1" newline bitfld.word 0x0 4. "MPLLA_CLK_EN_REG,When asserted with bit 5 selects MPLLA clock as TX data output clock Only bit 3 or bit 4 or bit 1 can be asserted" "0,1" newline bitfld.word 0x0 3. "MPLLB_CLK_EN_REG,When asserted with bit 5 selects MPLLB clock as TX data output clock Only bit 3 or bit 4 or bit 1 can be asserted" "0,1" newline bitfld.word 0x0 2. "OVRD_LB_EN,If asserted it allows bit 1 takes control of RX clock loopback to TX" "0,1" newline bitfld.word 0x0 1. "CLK_LB_EN_REG,When asserted with bit 2 selects RX clock for TX data output clock" "0,1" newline bitfld.word 0x0 0. "OVERRIDE_REGREF_1,Use atb_s_m to over ride TX regulator reference voltage when asserted" "0,1" group.word 0x4728++0x1 line.word 0x0 "LANE1_ANA_TX_MISC,TX_MISC" newline hexmask.word.byte 0x0 8.--15. 1. "RESERVED_15_8,Reserved for Future use" newline bitfld.word 0x0 7. "OVERRIDE_RXDETREF,If asserted atb_s_m is used to override RX detection reference voltage" "0,1" newline bitfld.word 0x0 6. "MEAS_ATB_BIAS_VPTX,Measure TX bias local vptx through atb_s_p when asserted" "0,1" newline bitfld.word 0x0 5. "OSC_DIV4_EN,If asserted divides tx_alt oscillator output frequency by 4" "0,1" newline hexmask.word.byte 0x0 0.--4. 1. "NC4_0,Reserved" group.word 0x472C++0x1 line.word 0x0 "LANE1_ANA_RX_ATB_IQSKEW,RX_ATB_IQSKEW" newline hexmask.word.byte 0x0 8.--15. 1. "RESERVED_15_8,Reserved for Future use" newline bitfld.word 0x0 7. "MASTER_ATB_EN,If asserted enable RX ATB sensing bus atb_s_p/m visible externally.The exception is bit 5 which dont require this bit to be asserted" "0,1" newline bitfld.word 0x0 6. "MEAS_ATB_RX_SCOPE_REG,If asserted enable scope linearity characterization through atb_s_p/m" "0,1" newline bitfld.word 0x0 5. "MEAS_ATB_VP,If asserted vp is measured through atb_s_p" "0,1" newline hexmask.word.byte 0x0 0.--4. 1. "IQ_PHASE_ADJUST_REG,If ovrd_iq_phase_adjust is enabled these bits control the main PMIX" group.word 0x4730++0x1 line.word 0x0 "LANE1_ANA_RX_DCC_OVRD,RX_DCC_OVRD" newline hexmask.word.byte 0x0 8.--15. 1. "RESERVED_15_8,Reserved for Future use" newline bitfld.word 0x0 7. "DCC_EN_REG,When bit 6 is asserted this bit takes control of RX DCC enable" "0,1" newline bitfld.word 0x0 6. "OVRD_DCCANDAFE_EN,When asserted override RX DCC enable by analog register" "0,1" newline bitfld.word 0x0 5. "RX_LOOPBACK_CLK_REG,When bit 4 asserted this bit takes control of RX clock loopback enable/disable" "0,1" newline bitfld.word 0x0 4. "OVRD_RX_LOOPBACK_CLK,When asserted override rx clock loopback by analog register" "0,1" newline bitfld.word 0x0 2.--3. "MEAS_ATB_VDCC,meas_atb_vdcc[1:0] 00 Disable atb measurement 01 measure vdcc_i_p/m through atb_s_p/m 10 measure vdcc_q_p/m through atb_s_p/m 11 measure vdcc_i/q through atb_s_p/m" "0,1,2,3" newline bitfld.word 0x0 0.--1. "NC1_0,Reserved" "0,1,2,3" repeat 2. (list 0x1 0x2 )(list 0x0 0xC ) group.word ($2+0x4734)++0x1 line.word 0x0 "LANE1_ANA_RX_PWR_CTRL$1,RX_PWR_CTRL1" newline hexmask.word.byte 0x0 8.--15. 1. "RESERVED_15_8,Reserved for Future use" newline bitfld.word 0x0 7. "AFE_EN_REG,When asserted with bit 6 enables AFE" "0,1" newline bitfld.word 0x0 6. "OVRD_AFE_EN,If asserted bit 7 take control of AFE enable/disable" "0,1" newline bitfld.word 0x0 5. "LOS_EN_REG,When asserted with bit 4 enables LOS" "0,1" newline bitfld.word 0x0 4. "OVRD_LOS_EN,If asserted bit 5 take control of LOS enable/disable" "0,1" newline bitfld.word 0x0 3. "CLK_EN_REG,When asserted with bit 2 enables RX clock" "0,1" newline bitfld.word 0x0 2. "OVRD_CLK_EN,If asserted bit 3 take control of RX clock enable/disable" "0,1" newline bitfld.word 0x0 1. "ACJT_EN_REG,When asserted with bit 0 enables ACJTAG" "0,1" newline bitfld.word 0x0 0. "OVRD_ACJT_EN,If asserted bit 1 take control of ACJTAG enable/disable" "0,1" repeat.end group.word 0x4738++0x1 line.word 0x0 "LANE1_ANA_RX_ATB_REGREF,RX_ATB_REGREF" newline hexmask.word.byte 0x0 8.--15. 1. "RESERVED_15_8,Reserved for Future use" newline bitfld.word 0x0 5.--7. "MEAS_ATB_CAL_MUX,Meas_atb_cal_mux is 3 bit signal Meas_atb_cal_mux[2:0] If Meas_atb_cal_mux[2] asserted RX offset calibration comparator first stage differential outputs are measured through atb_s_p/m If Meas_atb_cal_mux[1] asserted atb_s_p/m.." "0,1,2,3,4,5,6,7" newline bitfld.word 0x0 4. "OVERRIDE_REGREF_CLK,If asserted RX clock regulator reference is overridden through atb_s_m" "0,1" newline bitfld.word 0x0 3. "OVERRIDE_REGREF_SCOPE,If asserted RX scope regulator reference is overridden through atb_s_m" "0,1" newline bitfld.word 0x0 2. "NC2,Reserved" "0,1" newline bitfld.word 0x0 0.--1. "MEAS_ATB_SAMP,meas_atb_samp[1:0] 00 Disable atb measurement 01 measure clk_i_p/m sampling node through atb_s_p/m 10 measure clk_q_p/m sampling node through atb_s_p/m 11 measure clk_i/q sampling node through atb_s_p/m" "0,1,2,3" group.word 0x473C++0x1 line.word 0x0 "LANE1_ANA_RX_CDR_AFE,RX_CDR_AFE" newline hexmask.word.byte 0x0 8.--15. 1. "RESERVED_15_8,Reserved for Future use" newline bitfld.word 0x0 6.--7. "NC7_6,Reserved" "0,1,2,3" newline bitfld.word 0x0 5. "PHDET_EVEN_REG,If asserted CDR phase detector uses even data path" "0,1" newline bitfld.word 0x0 4. "PHDET_ODD_REG,If asserted CDR phase detector uses odd data path" "0,1" newline hexmask.word.byte 0x0 0.--3. 1. "MEAS_ATB_RX,This is meas_atb_rx[9:6] bit each bit correspond to ==> meas_atb_rx[9] If asserted AFE biasing vbp is measured through atb_s_p meas_atb_rx[8] If asserted AFE biasing vbn is measured through atb_s_m meas_atb_rx[7] If asserted rx_p is.." group.word 0x4744++0x1 line.word 0x0 "LANE1_ANA_RX_MISC_OVRD,RX_MISC_OVRD" newline hexmask.word.byte 0x0 8.--15. 1. "RESERVED_15_8,Reserved for Future use" newline bitfld.word 0x0 7. "OVERRIDE_VREG_PRECHG_REG,If asserted the overvoltage compensation circuit in rx_vregs disabled" "0,1" newline bitfld.word 0x0 6. "CTLE_OFFSET_CAL_ENB,If asserted the offset calibration currents in the CTLE are disabled" "0,1" newline bitfld.word 0x0 5. "OVRD_RX_LOS_LFPS_EN,If asserted bit 4 enable/disables RX true LFPS detection" "0,1" newline bitfld.word 0x0 4. "RX_LOS_LFPS_EN_REG,If asserted with bit 5 enables true LFPS detection" "0,1" newline bitfld.word 0x0 2.--3. "NC3_2,Reserved" "0,1,2,3" newline bitfld.word 0x0 1. "WORD_CLK_EN_REG,If asserted with bit 0 enables rx word clock" "0,1" newline bitfld.word 0x0 0. "OVRD_WORD_CLK_EN,If asserted bit 1 takes control of word clock enable/disable" "0,1" group.word 0x4748++0x1 line.word 0x0 "LANE1_ANA_RX_CAL_MUXA,RX_CAL_MUXA" newline hexmask.word.byte 0x0 8.--15. 1. "RESERVED_15_8,Reserved for Future use" newline bitfld.word 0x0 7. "OVRD_CAL_MUXA_SEL,If asserted selects analog register setting to control RX calibration path A" "0,1" newline hexmask.word.byte 0x0 2.--6. 1. "CAL_MUXA_SEL_REG,Analog registers to control RX calibration path A if bit 7 is asserted this is cal_muxa_sel_reg[4:0]" newline bitfld.word 0x0 1. "MEAS_ATB_VIBIAS_VCO,If asserted measure CDR VCO bias current through atb_s_p (25uA)" "0,1" newline bitfld.word 0x0 0. "MEAS_ATB_VCO_200U,If asserted measure CDR VCO bias current through atb_s_m (200uA)" "0,1" group.word 0x474C++0x1 line.word 0x0 "LANE1_ANA_RX_ATB_MEAS1,RX_ATB_MEAS1" newline hexmask.word.byte 0x0 8.--15. 1. "RESERVED_15_8,Reserved for Future use" newline bitfld.word 0x0 7. "ATB_FRC_VLOS,If asserted force los detection reference voltage through atb_s_m" "0,1" newline hexmask.word.byte 0x0 1.--6. 1. "MEAS_ATB_RX,This is meas_atb_rx[5:0] bits where each bit correspond to meas_atb_rx[5] If asserted rx_m is driven by atb_f_m meas_atb_rx[4] If asserted rx_m is sensed through atb_s_m meas_atb_rx[3] If asserted measure RX LOS detection threshold.." newline bitfld.word 0x0 0. "NC0,Reserved" "0,1" group.word 0x4750++0x1 line.word 0x0 "LANE1_ANA_RX_ATB_MEAS2,RX_ATB_MEAS2" newline hexmask.word.byte 0x0 8.--15. 1. "RESERVED_15_8,Reserved for Future use" newline bitfld.word 0x0 7. "MEAS_GD,If asserted measure RX regulator local gd through atb_s_p" "0,1" newline bitfld.word 0x0 6. "NC6,Reserved" "0,1" newline bitfld.word 0x0 5. "MEAS_VREG_CLK,If asserted measure RX clock regulator output voltage through atb_s_p" "0,1" newline bitfld.word 0x0 4. "NC4,Reserved" "0,1" newline bitfld.word 0x0 3. "MEAS_VREG_SCOPE,If asserted measure RX scope regulator output voltage through atb_s_p" "0,1" newline bitfld.word 0x0 2. "MEAS_ATB_OVRD_CDR_EN,If asserted enables CDR regardless of the digital control" "0,1" newline bitfld.word 0x0 1. "MEAS_ATB_VCO_GD,If asserted measure CDR VCO local gd through atb_s_m" "0,1" newline bitfld.word 0x0 0. "MEAS_ATB_VCO_VOSC,If asserted measure CDR VCO oscillation bias current through atb_s_m" "0,1" group.word 0x4754++0x1 line.word 0x0 "LANE1_ANA_RX_CAL_MUXB,RX_CAL_MUXB" newline hexmask.word.byte 0x0 8.--15. 1. "RESERVED_15_8,Reserved for Future use" newline bitfld.word 0x0 7. "OVRD_CAL_MUXB_SEL,If asserted selects analog register setting to control RX calibration path B" "0,1" newline hexmask.word.byte 0x0 2.--6. 1. "CAL_MUXB_SEL_REG,Analog registers to control RX calibration path B if bit 7 is asserted this is cal_muxb_sel_reg[4:0]" newline bitfld.word 0x0 1. "OVRD_DFE_TAPS_EN,If asserted allows bit 0 to enable/disable dfe taps 1 and 2" "0,1" newline bitfld.word 0x0 0. "DFE_TAPS_EN_REG,If bit 1 is asserted controls DFE tap 1 and 2" "0,1" group.word 0x4758++0x1 line.word 0x0 "LANE1_ANA_RX_TERM,RX_TERM" newline hexmask.word.byte 0x0 8.--15. 1. "RESERVED_15_8,Reserved for Future use" newline bitfld.word 0x0 6.--7. "AFE_CM_SEL,Added to make AFE CM voltage controllable (below values are for TT vp=0.8V) 00 vcm=662mV 01 vcm=627mV (default) 10 vcm=593mV 11 vcm=558mV" "0,1,2,3" newline bitfld.word 0x0 5. "OVRD_RX_TERM_GD_EN,If asserted the ground termination enable value is controlled via registers" "0,1" newline bitfld.word 0x0 4. "RX_TERM_GD_EN_REG,If termination override is asserted controls the ground termination enable" "0,1" newline bitfld.word 0x0 3. "OVRD_IQ_PHASE_ADJUST,If asserted the iq_phase_adjust value is controlled via registers" "0,1" newline bitfld.word 0x0 2. "VCO_TEMP_COMP_EN,If asserted the RX-VCO temperature compensation circuit is enabled" "0,1" newline bitfld.word 0x0 0.--1. "CDR_VCO_STARTUP_CODE_REG,RX_VCO startup current over-ride cdr_vco_startup_code Startup override 00 cdr_freq_code_int[9:7] = cdr_freq_code[9:7] 01 when startup = 1 -> cdr_freq_code_int[9] = 1 10 when startup = 1 -> cdr_freq_code_int[8] = 1 11 when startup.." "?,cdr_freq_code_int[7] = 1,?,?" group.word 0x475C++0x1 line.word 0x0 "LANE1_ANA_RX_SLC_CTRL,RX_SLC_CTRL" newline hexmask.word.byte 0x0 8.--15. 1. "RESERVED_15_8,Reserved for Future use" newline hexmask.word.byte 0x0 4.--7. 1. "RX_SLICER_CTRL_E_REG,If ovrd_rx_slicer_ctrl_reg is asserted controls the even slicer configuration" newline hexmask.word.byte 0x0 0.--3. 1. "RX_SLICER_CTRL_O_REG,If ovrd_rx_slicer_ctrl_reg is asserted controls the odd slicer configuration" group.word 0x4760++0x1 line.word 0x0 "LANE1_ANA_RX_ATB_VREG,RX_ATB_VREG" newline hexmask.word.byte 0x0 8.--15. 1. "RESERVED_15_8,Reserved for Future use" newline bitfld.word 0x0 7. "OVRD_REGREF_IQC,If asserted main PMIX regulator reference is overridden through atb_s_m" "0,1" newline bitfld.word 0x0 6. "OVRD_REGREF_IQC_SCOPE,If asserted scope PMIX regulator reference is overridden through atb_s_m" "0,1" newline bitfld.word 0x0 5. "MEAS_ATB_VREG_DFE,If asserted measure RX DFE regulator output voltage through atb_s_p" "0,1" newline bitfld.word 0x0 4. "NC4,Reserved" "0,1" newline bitfld.word 0x0 3. "MEAS_ATB_VREG_IQC,If asserted measure RX main PMIX regulator output voltage through atb_s_p" "0,1" newline bitfld.word 0x0 2. "MEAS_ATB_VREG_IQC_SCOPE,If asserted measure RX scope PMIX regulator output voltage through atb_s_p" "0,1" newline bitfld.word 0x0 1. "OVRD_IQC_VREF_SEL,If asserted the vref on the iqc regulator is controlled via vbg_vref which can be controlled via registers" "0,1" newline bitfld.word 0x0 0. "OVRD_RX_SLICER_CTRL_REG,If asserted the slicer configuration value is controlled via registers (LANE.RX_SLC_CTRL)" "0,1" group.word 0x8000++0x1 line.word 0x0 "RAWCMN_DIG_CMN_CTL,Common control register" newline hexmask.word 0x0 1.--15. 1. "RESERVED_15_1,Reserved for Future use" newline bitfld.word 0x0 0. "PHY_FUNC_RST,Resets the PHY except registers in the Raw PCS common and always-on registers. Useful for resetting the PHY after reloading the Memory and without resetting the Memory." "0,1" group.word 0x8004++0x1 line.word 0x0 "RAWCMN_DIG_MPLLA_OVRD_IN,Override values for incoming MPLLA signals" newline hexmask.word.byte 0x0 11.--15. 1. "RESERVED_15_11,Reserved for Future use" newline bitfld.word 0x0 10. "MPLLA_BW_OVRD_EN,Override enable for mplla_bandwidth[15:0]" "0,1" newline bitfld.word 0x0 9. "MPLLA_DIV8_CLK_EN_OVRD_EN,Override enable for mplla_div8_clk_en" "0,1" newline bitfld.word 0x0 8. "MPLLA_DIV8_CLK_EN_OVRD_VAL,Override value for mplla_div8_clk_en" "0,1" newline bitfld.word 0x0 7. "MPLLA_DIV10_CLK_EN_OVRD_EN,Override enable for mplla_div10_clk_en" "0,1" newline bitfld.word 0x0 6. "MPLLA_DIV10_CLK_EN_OVRD_VAL,Override value for mplla_div10_clk_en" "0,1" newline bitfld.word 0x0 5. "MPLLA_TX_CLK_DIV_OVRD_EN,Override enable for mplla_tx_clk_div[2:0]" "0,1" newline bitfld.word 0x0 2.--4. "MPLLA_TX_CLK_DIV_OVRD_VAL,Override value for mplla_tx_clk_div[2:0]" "0,1,2,3,4,5,6,7" newline bitfld.word 0x0 1. "MPLLA_WORD_DIV2_EN_OVRD_EN,Override enable for mplla_word_div2_en" "0,1" newline bitfld.word 0x0 0. "MPLLA_WORD_DIV2_EN_OVRD_VAL,Override value for mplla_word_div2_en" "0,1" group.word 0x8008++0x1 line.word 0x0 "RAWCMN_DIG_MPLLA_BW_OVRD_IN,Override values for incoming MPLLA bandwidth" newline hexmask.word 0x0 0.--15. 1. "MPLLA_BW_OVRD_VAL,Override value for mplla_bandwidth[15:0]" group.word 0x800C++0x1 line.word 0x0 "RAWCMN_DIG_MPLLA_SSC_CTL_OVRD_IN_0,Override values for incoming MPLLA SSC control settings" newline hexmask.word.byte 0x0 10.--15. 1. "RESERVED_15_10,Reserved for Future use" newline bitfld.word 0x0 9. "MPLLA_SSC_EN_OVRD_EN,Override enable for mplla_ssc_en" "0,1" newline bitfld.word 0x0 8. "MPLLA_SSC_EN_OVRD_VAL,Override value for mplla_ssc_en" "0,1" newline bitfld.word 0x0 7. "MPLLA_SSC_CLK_SEL_OVRD_EN,Override enable for mplla_ssc_clk_sel[2:0]" "0,1" newline bitfld.word 0x0 4.--6. "MPLLA_SSC_CLK_SEL_OVRD_VAL,Override value for mplla_ssc_clk_sel[2:0]" "0,1,2,3,4,5,6,7" newline bitfld.word 0x0 3. "MPLLA_SSC_RANGE_OVRD_EN,Override enable for mplla_ssc_range[2:0]" "0,1" newline bitfld.word 0x0 0.--2. "MPLLA_SSC_RANGE_OVRD_VAL,Override value for mplla_ssc_range[2:0]" "0,1,2,3,4,5,6,7" group.word 0x8010++0x1 line.word 0x0 "RAWCMN_DIG_MPLLB_OVRD_IN,Override values for incoming MPLLB signals" newline hexmask.word.byte 0x0 11.--15. 1. "RESERVED_15_11,Reserved for Future use" newline bitfld.word 0x0 10. "MPLLB_BW_OVRD_EN,Override enable for mpllb_bandwidth[15:0]" "0,1" newline bitfld.word 0x0 9. "MPLLB_DIV8_CLK_EN_OVRD_EN,Override enable for mpllb_div8_clk_en" "0,1" newline bitfld.word 0x0 8. "MPLLB_DIV8_CLK_EN_OVRD_VAL,Override value for mpllb_div8_clk_en" "0,1" newline bitfld.word 0x0 7. "MPLLB_DIV10_CLK_EN_OVRD_EN,Override enable for mpllb_div10_clk_en" "0,1" newline bitfld.word 0x0 6. "MPLLB_DIV10_CLK_EN_OVRD_VAL,Override value for mpllb_div10_clk_en" "0,1" newline bitfld.word 0x0 5. "MPLLB_TX_CLK_DIV_OVRD_EN,Override enable for mpllb_tx_clk_div[2:0]" "0,1" newline bitfld.word 0x0 2.--4. "MPLLB_TX_CLK_DIV_OVRD_VAL,Override value for mpllb_tx_clk_div[2:0]" "0,1,2,3,4,5,6,7" newline bitfld.word 0x0 1. "MPLLB_WORD_DIV2_EN_OVRD_EN,Override enable for mpllb_word_div2_en" "0,1" newline bitfld.word 0x0 0. "MPLLB_WORD_DIV2_EN_OVRD_VAL,Override value for mpllb_word_div2_en" "0,1" group.word 0x8014++0x1 line.word 0x0 "RAWCMN_DIG_MPLLB_BW_OVRD_IN,Override values for incoming MPLLB bandwidth" newline hexmask.word 0x0 0.--15. 1. "MPLLB_BW_OVRD_VAL,Override value for mpllb_bandwidth[15:0]" group.word 0x8018++0x1 line.word 0x0 "RAWCMN_DIG_MPLLB_SSC_CTL_OVRD_IN_0,Override values for incoming MPLLB SSC control settings" newline hexmask.word.byte 0x0 10.--15. 1. "RESERVED_15_10,Reserved for Future use" newline bitfld.word 0x0 9. "MPLLB_SSC_EN_OVRD_EN,Override enable for mpllb_ssc_en" "0,1" newline bitfld.word 0x0 8. "MPLLB_SSC_EN_OVRD_VAL,Override value for mpllb_ssc_en" "0,1" newline bitfld.word 0x0 7. "MPLLB_SSC_CLK_SEL_OVRD_EN,Override enable for mpllb_ssc_clk_sel[2:0]" "0,1" newline bitfld.word 0x0 4.--6. "MPLLB_SSC_CLK_SEL_OVRD_VAL,Override value for mpllb_ssc_clk_sel[2:0]" "0,1,2,3,4,5,6,7" newline bitfld.word 0x0 3. "MPLLB_SSC_RANGE_OVRD_EN,Override enable for mpllb_ssc_range[2:0]" "0,1" newline bitfld.word 0x0 0.--2. "MPLLB_SSC_RANGE_OVRD_VAL,Override value for mpllb_ssc_range[2:0]" "0,1,2,3,4,5,6,7" group.word 0x801C++0x1 line.word 0x0 "RAWCMN_DIG_LANE_FSM_OP_XTND,Lane FSM OP XTND control register" newline hexmask.word 0x0 1.--15. 1. "RESERVED_15_1,Reserved for Future use" newline bitfld.word 0x0 0. "DATA,Required to prevent timing violations while accessing through external interface." "0,1" group.word 0x8020++0x1 line.word 0x0 "RAWCMN_DIG_MPLLA_SSC_CTL_OVRD_IN_1,Override values for incoming MPLLA SSC control settings" newline hexmask.word.byte 0x0 12.--15. 1. "RESERVED_15_12,Reserved for Future use" newline bitfld.word 0x0 11. "MPLLA_FRACN_CTRL_OVRD_EN,Override enable for mplla_fracn_ctrl[10:0]" "0,1" newline hexmask.word 0x0 0.--10. 1. "MPLLA_FRACN_CTRL_OVRD_VAL,Override value for mplla_fracn_ctrl[10:0]" group.word 0x8024++0x1 line.word 0x0 "RAWCMN_DIG_MPLLB_SSC_CTL_OVRD_IN_1,Override values for incoming MPLLB SSC control settings" newline hexmask.word.byte 0x0 12.--15. 1. "RESERVED_15_12,Reserved for Future use" newline bitfld.word 0x0 11. "MPLLB_FRACN_CTRL_OVRD_EN,Override enable for mpllb_fracn_ctrl[10:0]" "0,1" newline hexmask.word 0x0 0.--10. 1. "MPLLB_FRACN_CTRL_OVRD_VAL,Override value for mpllb_fracn_ctrl[10:0]" group.word 0x8028++0x1 line.word 0x0 "RAWCMN_DIG_CMN_CTL_1,Common control register 1" newline hexmask.word 0x0 6.--15. 1. "RESERVED_15_6,Reserved for Future use" newline bitfld.word 0x0 5. "RTUNE_REQ_OVRD_EN,Override enable for rtune_req" "0,1" newline bitfld.word 0x0 4. "RTUNE_REQ_OVRD_VAL,Override value for rtune_req" "0,1" newline bitfld.word 0x0 3. "MPLLB_INIT_CAL_DISABLE_OVRD_EN,Override enable for mpllb_init_cal_disable" "0,1" newline bitfld.word 0x0 2. "MPLLB_INIT_CAL_DISABLE_OVRD_VAL,Override value for mpllb_init_cal_disable" "0,1" newline bitfld.word 0x0 1. "MPLLA_INIT_CAL_DISABLE_OVRD_EN,Override enable for mplla_init_cal_disable" "0,1" newline bitfld.word 0x0 0. "MPLLA_INIT_CAL_DISABLE_OVRD_VAL,Override value for mplla_init_cal_disable" "0,1" group.word 0x802C++0x1 line.word 0x0 "RAWCMN_DIG_CMN_CTL_2,Common control register 2" newline hexmask.word 0x0 7.--15. 1. "RESERVED_15_7,Reserved for Future use" newline bitfld.word 0x0 6. "FW_PWRUP_DONE,Indicates whether Firmware power-up has completed or not. After PG exit restore value from AON and assign it after coarse tune is restored in PG Exit sequence." "0,1" newline hexmask.word.byte 0x0 0.--5. 1. "TX_WAIT_MPLL_OFF_TIME,Number of ref_range cycles to wait for MPLL to turn off" repeat 8. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 )(list 0x0 0xC 0x18 0x24 0x30 0x3C 0x48 0x54 ) group.word ($2+0x8080)++0x1 line.word 0x0 "RAWCMN_DIG_AON_CMN_RTUNE_RX_VAL_$1,Resistor Tune RX Value 0" newline hexmask.word 0x0 6.--15. 1. "RESERVED_15_6,Reserved for Future use" newline hexmask.word.byte 0x0 0.--5. 1. "RTUNE_RX_VAL_0,Stored resister tune RX value 0" repeat.end repeat 8. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 )(list 0x0 0xC 0x18 0x24 0x30 0x3C 0x48 0x54 ) group.word ($2+0x8084)++0x1 line.word 0x0 "RAWCMN_DIG_AON_CMN_RTUNE_TXDN_VAL_$1,Resistor Tune TX Down Value 0" newline hexmask.word.byte 0x0 10.--15. 1. "RESERVED_15_10,Reserved for Future use" newline hexmask.word 0x0 0.--9. 1. "RTUNE_TXDN_VAL_0,Stored resister tune TX down value 0" repeat.end repeat 8. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 )(list 0x0 0xC 0x18 0x24 0x30 0x3C 0x48 0x54 ) group.word ($2+0x8088)++0x1 line.word 0x0 "RAWCMN_DIG_AON_CMN_RTUNE_TXUP_VAL_$1,Resistor Tune TX Up Value 0" newline hexmask.word.byte 0x0 10.--15. 1. "RESERVED_15_10,Reserved for Future use" newline hexmask.word 0x0 0.--9. 1. "RTUNE_TXUP_VAL_0,Stored resister tune TX up value 0" repeat.end group.word 0x80E0++0x1 line.word 0x0 "RAWCMN_DIG_AON_CMN_SRAM_PGATE_BL_EN,Enable SRAM bootloader on power-gated exit" newline hexmask.word 0x0 1.--15. 1. "RESERVED_15_1,Reserved for Future use" newline bitfld.word 0x0 0. "SRAM_PGATE_BL_EN,Enable SRAM bootloader on power-gated exit." "0,1" group.word 0x80E4++0x1 line.word 0x0 "RAWCMN_DIG_AON_CMN_PG_OVRD_IN,Override values for incoming power-gating signals" newline hexmask.word 0x0 6.--15. 1. "RESERVED_15_6,Reserved for Future use" newline bitfld.word 0x0 5. "PG_MODE_EN_OVRD_EN,Override enable for pg_mode_en." "0,1" newline bitfld.word 0x0 4. "PG_MODE_EN_OVRD_VAL,Override value for pg_mode_en." "0,1" newline bitfld.word 0x0 3. "PG_RESET_OVRD_EN,Override enable for pg_reset." "0,1" newline bitfld.word 0x0 2. "PG_RESET_OVRD_VAL,Override value for pg_reset." "0,1" newline bitfld.word 0x0 1. "PCS_PWR_STABLE_OVRD,Enable overriding pcs_pwr_stable to 1'b1." "0,1" newline bitfld.word 0x0 0. "PMA_PWR_STABLE_OVRD,Enable overriding pma_pwr_stable to 1'b1." "0,1" group.word 0x80E8++0x1 line.word 0x0 "RAWCMN_DIG_AON_CMN_PG_OVRD_OUT,Override values for outgoing power-gating signals" newline hexmask.word 0x0 2.--15. 1. "RESERVED_15_2,Reserved for Future use" newline bitfld.word 0x0 1. "PCS_PWR_EN_OVRD,Enable overriding pcs_pwr_en to 1'b1." "0,1" newline bitfld.word 0x0 0. "PMA_PWR_EN_OVRD,Enable overriding pma_pwr_en to 1'b1." "0,1" group.word 0x80EC++0x1 line.word 0x0 "RAWCMN_DIG_AON_CMN_SUP_OVRD_IN,Override values for incoming SUP signals" newline hexmask.word 0x0 6.--15. 1. "RESERVED_15_6,Reserved for Future use" newline bitfld.word 0x0 5. "REF_CLK_EN_OVRD_EN,Override enable for ref_clk_en" "0,1" newline bitfld.word 0x0 4. "REF_CLK_EN_OVRD_VAL,Override value for ref_clk_en" "0,1" newline bitfld.word 0x0 3. "MPLLB_FORCE_EN_OVRD_EN,Override enable for mpllb_force_en" "0,1" newline bitfld.word 0x0 2. "MPLLB_FORCE_EN_OVRD_VAL,Override value for mpllb_force_en" "0,1" newline bitfld.word 0x0 1. "MPLLA_FORCE_EN_OVRD_EN,Override enable for mplla_force_en" "0,1" newline bitfld.word 0x0 0. "MPLLA_FORCE_EN_OVRD_VAL,Override value for mplla_force_en" "0,1" group.word 0x80F0++0x1 line.word 0x0 "RAWCMN_DIG_AON_CMN_FW_PWRUP_DONE,Firmware Power-Up Done Status" newline hexmask.word 0x0 1.--15. 1. "RESERVED_15_1,Reserved for Future use" newline bitfld.word 0x0 0. "FW_PWRUP_DONE,Indicates whether Firmware power-up has completed or not." "0,1" repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) group.word ($2+0x80F4)++0x1 line.word 0x0 "RAWCMN_DIG_AON_CMN_FW_VERSION_$1,Firmware version register #0" newline hexmask.word 0x0 0.--15. 1. "FW_VERSION_0,Firmware version" repeat.end group.word 0xC000++0x1 line.word 0x0 "RAWLANE0_DIG_PCS_XF_TX_OVRD_IN,Override values for incoming TX controls from PCS" newline rbitfld.word 0x0 13.--15. "RESERVED_15_13,Reserved for Future use" "0,1,2,3,4,5,6,7" newline bitfld.word 0x0 12. "OVRD_EN,Override enable for all input signals below" "0,1" newline bitfld.word 0x0 11. "MSTR_MPLLB_STATE,Override value for tx_master_mpllb_state" "0,1" newline bitfld.word 0x0 10. "MSTR_MPLLA_STATE,Override value for tx_master_mplla_state" "0,1" newline bitfld.word 0x0 9. "MPLL_EN,Override value for tx_mpll_en" "0,1" newline bitfld.word 0x0 8. "MPLLB_SEL,Override value for tx_mpllb_sel" "0,1" newline bitfld.word 0x0 5.--7. "RATE,Override value for tx_rate" "0,1,2,3,4,5,6,7" newline bitfld.word 0x0 3.--4. "WIDTH,Override value for tx_width" "0,1,2,3" newline bitfld.word 0x0 2. "LPD,Override value for tx_lpd" "0,1" newline bitfld.word 0x0 0.--1. "PSTATE,Override value for tx_pstate" "0,1,2,3" group.word 0xC004++0x1 line.word 0x0 "RAWLANE0_DIG_PCS_XF_TX_OVRD_IN_1,Override values for incoming TX controls from PCS. register #1" newline rbitfld.word 0x0 13.--15. "RESERVED_15_13,Reserved for Future use" "0,1,2,3,4,5,6,7" newline bitfld.word 0x0 12. "IBOOST_LVL_OVRD_EN,Override enable for tx_iboost_lvl[3:0]" "0,1" newline hexmask.word.byte 0x0 8.--11. 1. "IBOOST_LVL_OVRD_VAL,Override value for tx_iboost_lvl[3:0]" newline bitfld.word 0x0 7. "VBOOST_EN_OVRD_EN,Override enable for tx_vboost_en" "0,1" newline bitfld.word 0x0 6. "VBOOST_EN_OVRD_VAL,Override value for tx_vboost_en" "0,1" newline bitfld.word 0x0 5. "DETRX_REQ_OVRD_EN,Override enable for tx_detrx_req" "0,1" newline bitfld.word 0x0 4. "DETRX_REQ_OVRD_VAL,Override value for tx_detrx_req" "0,1" newline bitfld.word 0x0 3. "REQ_OVRD_EN,Override enable for tx_req" "0,1" newline bitfld.word 0x0 2. "REQ_OVRD_VAL,Override value for tx_req" "0,1" newline bitfld.word 0x0 1. "RESET_OVRD_EN,Override enable for tx_reset" "0,1" newline bitfld.word 0x0 0. "RESET_OVRD_VAL,Override value for tx_reset" "0,1" rgroup.word 0xC008++0x1 line.word 0x0 "RAWLANE0_DIG_PCS_XF_TX_PCS_IN,Current values for incoming TX controls from PCS" newline bitfld.word 0x0 15. "RESERVED_15_15,Reserved for Future use" "0,1" newline bitfld.word 0x0 14. "DETRX_REQ,Value from PCS for tx_detrx_req" "0,1" newline bitfld.word 0x0 13. "MSTR_MPLLB_STATE,Value from PCS for tx_master_mpllb_state" "0,1" newline bitfld.word 0x0 12. "MSTR_MPLLA_STATE,Value from PCS for tx_master_mplla_state" "0,1" newline bitfld.word 0x0 11. "MPLL_EN,Value from PCS for tx_mpll_en" "0,1" newline bitfld.word 0x0 10. "MPLLB_SEL,Value from PCS for tx_mpllb_sel" "0,1" newline bitfld.word 0x0 7.--9. "RATE,Value from PCS for tx_rate" "0,1,2,3,4,5,6,7" newline bitfld.word 0x0 5.--6. "WIDTH,Value from PCS for tx_width" "0,1,2,3" newline bitfld.word 0x0 4. "LPD,Value from PCS for tx_lpd" "0,1" newline bitfld.word 0x0 2.--3. "PSTATE,Value from PCS for tx_pstate" "0,1,2,3" newline bitfld.word 0x0 1. "REQ,Value from PCS for tx_req" "0,1" newline bitfld.word 0x0 0. "RESET,Value from PCS for tx_reset" "0,1" group.word 0xC00C++0x1 line.word 0x0 "RAWLANE0_DIG_PCS_XF_TX_OVRD_OUT,Override values for outgoing TX controls to PCS" newline hexmask.word 0x0 3.--15. 1. "RESERVED_15_3,Reserved for Future use" newline bitfld.word 0x0 2. "EN_CTL,Enable override values for all control outputs of this register" "0,1" newline bitfld.word 0x0 1. "DETRX_RESULT,Override value for tx_detrx_result" "0,1" newline bitfld.word 0x0 0. "ACK,Override value for tx_ack" "0,1" rgroup.word 0xC010++0x1 line.word 0x0 "RAWLANE0_DIG_PCS_XF_TX_PCS_OUT,Current values for outgoing TX status controls from Raw PCS" newline hexmask.word 0x0 1.--15. 1. "RESERVED_15_1,Reserved for Future use" newline bitfld.word 0x0 0. "ACK,Value from Raw PCS for tx_ack" "0,1" group.word 0xC014++0x1 line.word 0x0 "RAWLANE0_DIG_PCS_XF_RX_OVRD_IN,Override values for incoming RX controls from PCS" newline hexmask.word.byte 0x0 10.--15. 1. "RESERVED_15_10,Reserved for Future use" newline bitfld.word 0x0 9. "ADAPT_DFE_EN,Override value for rx_adapt_dfe_en" "0,1" newline bitfld.word 0x0 8. "ADAPT_AFE_EN,Override value for rx_adapt_afe_en" "0,1" newline bitfld.word 0x0 7. "OVRD_EN,Enable override values for all fields in this register" "0,1" newline bitfld.word 0x0 6. "LPD,Override value for rx_lpd" "0,1" newline bitfld.word 0x0 4.--5. "PSTATE,Override value for rx_pstate" "0,1,2,3" newline bitfld.word 0x0 2.--3. "WIDTH,Override value for rx_width" "0,1,2,3" newline bitfld.word 0x0 0.--1. "RATE,Override value for rx_rate" "0,1,2,3" group.word 0xC018++0x1 line.word 0x0 "RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_1,Override values for incoming RX controls from PCS. register #1" newline hexmask.word 0x0 4.--15. 1. "RESERVED_15_4,Reserved for Future use" newline bitfld.word 0x0 3. "REQ_OVRD_EN,Override enable for rx_req" "0,1" newline bitfld.word 0x0 2. "REQ_OVRD_VAL,Override value for rx_req" "0,1" newline bitfld.word 0x0 1. "RESET_OVRD_EN,Override enable for rx_reset" "0,1" newline bitfld.word 0x0 0. "RESET_OVRD_VAL,Override value for rx_reset" "0,1" group.word 0xC01C++0x1 line.word 0x0 "RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_2,Override values for incoming RX controls from PCS. register #2" newline bitfld.word 0x0 15. "VCO_LOWFREQ_VAL_OVRD_EN,Enable override for rx_cdr_vco_lowfreq" "0,1" newline bitfld.word 0x0 14. "VCO_LOWFREQ_VAL_OVRD,Override value for rx_cdr_vco_lowfreq" "0,1" newline bitfld.word 0x0 13. "VCO_LD_VAL_OVRD_EN,Enable override for rx_vco_ld_val" "0,1" newline hexmask.word 0x0 0.--12. 1. "VCO_LD_VAL_OVRD,Override value for rx_vco_ld_val" group.word 0xC020++0x1 line.word 0x0 "RAWLANE0_DIG_PCS_XF_RX_OVRD_IN_3,Override values for incoming RX controls from PCS. register #3" newline bitfld.word 0x0 15. "CONT_OVRD_EN,Enable override values for rx_adapt_cont and rx_offcan_cont" "0,1" newline bitfld.word 0x0 14. "OFFCAN_CONT,Override value for rx_offcan_cont" "0,1" newline bitfld.word 0x0 13. "ADAPT_CONT,Override value for rx_adapt_cont" "0,1" newline bitfld.word 0x0 12. "ADAPT_REQ_OVRD_EN,Enable override values for rx_adapt_req" "0,1" newline bitfld.word 0x0 11. "ADAPT_REQ,Override value for rx_adapt_req" "0,1" newline bitfld.word 0x0 10. "REF_LD_VAL_OVRD_EN,Enable override for rx_ref_ld_val" "0,1" newline hexmask.word.byte 0x0 4.--9. 1. "REF_LD_VAL_OVRD,Override value for rx_ref_ld_val" newline bitfld.word 0x0 3. "RX_LOS_THRSHLD_OVRD_EN,Enable override for rx_los_threshold" "0,1" newline bitfld.word 0x0 0.--2. "RX_LOS_THRSHLD_OVRD_VAL,Override value for rx_los_threshold" "0,1,2,3,4,5,6,7" rgroup.word 0xC024++0x1 line.word 0x0 "RAWLANE0_DIG_PCS_XF_RX_PCS_IN,Current values for incoming RX controls from PCS" newline bitfld.word 0x0 15. "RESERVED_15_15,Reserved for Future use" "0,1" newline bitfld.word 0x0 14. "RESET,Value from PCS for rx_reset" "0,1" newline bitfld.word 0x0 13. "OFFCAN_CONT,Value from PCS for rx_offcan_cont" "0,1" newline bitfld.word 0x0 12. "ADAPT_CONT,Value from PCS for rx_adapt_cont" "0,1" newline bitfld.word 0x0 11. "ADAPT_REQ,Value from PCS for rx_adapt_req" "0,1" newline bitfld.word 0x0 10. "ADAPT_DFE_EN,Value from PCS for rx_adapt_dfe_en" "0,1" newline bitfld.word 0x0 9. "ADAPT_AFE_EN,Value from PCS for rx_adapt_afe_en" "0,1" newline bitfld.word 0x0 8. "CDR_VCO_LOWFREQ,Value from PCS for rx_cdr_vco_lowfreq" "0,1" newline bitfld.word 0x0 7. "LPD,Value from PCS for rx_lpd" "0,1" newline bitfld.word 0x0 5.--6. "PSTATE,Value from PCS for rx_pstate" "0,1,2,3" newline bitfld.word 0x0 3.--4. "WIDTH,Value from PCS for rx_width" "0,1,2,3" newline bitfld.word 0x0 1.--2. "RATE,Value from PCS for rx_rate" "0,1,2,3" newline bitfld.word 0x0 0. "REQ,Value from PCS for rx_req" "0,1" rgroup.word 0xC028++0x1 line.word 0x0 "RAWLANE0_DIG_PCS_XF_RX_PCS_IN_1,Current values for incoming RX controls from PCS. register #1" newline hexmask.word 0x0 6.--15. 1. "RESERVED_15_6,Reserved for Future use" newline hexmask.word.byte 0x0 0.--5. 1. "REF_LD_VAL,Value from PCS for rx_ref_ld_val" rgroup.word 0xC02C++0x1 line.word 0x0 "RAWLANE0_DIG_PCS_XF_RX_PCS_IN_2,Current values for incoming RX controls from PCS. register #2" newline bitfld.word 0x0 13.--15. "RESERVED_15_13,Reserved for Future use" "0,1,2,3,4,5,6,7" newline hexmask.word 0x0 0.--12. 1. "VCO_LD_VAL,Value from PCS for rx_vco_ld_val" rgroup.word 0xC030++0x1 line.word 0x0 "RAWLANE0_DIG_PCS_XF_RX_PCS_IN_3,Current values for incoming RX controls from PCS. register #3" newline hexmask.word.byte 0x0 11.--15. 1. "EQ_CTLE_BOOST,Value from ASIC for rx_eq_ctle_boost" newline hexmask.word.byte 0x0 7.--10. 1. "EQ_VGA2_GAIN,Value from ASIC for rx_eq_vga2_gain" newline hexmask.word.byte 0x0 3.--6. 1. "EQ_VGA1_GAIN,Value from ASIC for rx_eq_vga1_gain" newline bitfld.word 0x0 0.--2. "EQ_ATT_LVL,Value from ASIC for rx_eq_att_lvl" "0,1,2,3,4,5,6,7" rgroup.word 0xC034++0x1 line.word 0x0 "RAWLANE0_DIG_PCS_XF_RX_PCS_IN_4,Current values for incoming RX controls from PCS. register #4" newline hexmask.word.byte 0x0 11.--15. 1. "RESERVED_15_11,Reserved for Future use" newline hexmask.word.byte 0x0 3.--10. 1. "EQ_DFE_TAP1,Value from ASIC for rx_eq_dfe_tap1" newline bitfld.word 0x0 0.--2. "EQ_CTLE_POLE,Value from ASIC for rx_eq_ctle_pole" "0,1,2,3,4,5,6,7" group.word 0xC038++0x1 line.word 0x0 "RAWLANE0_DIG_PCS_XF_RX_OVRD_OUT,Override values for outgoing RX controls to PCS" newline hexmask.word 0x0 2.--15. 1. "RESERVED_15_2,Reserved for Future use" newline bitfld.word 0x0 1. "EN_CTL,Enable override values for all control outputs of this register" "0,1" newline bitfld.word 0x0 0. "ACK,Override value for rx_ack" "0,1" rgroup.word 0xC03C++0x1 line.word 0x0 "RAWLANE0_DIG_PCS_XF_RX_PCS_OUT,Current values for outgoing RX status controls from Raw PCS" newline hexmask.word 0x0 1.--15. 1. "RESERVED_15_1,Reserved for Future use" newline bitfld.word 0x0 0. "ACK,Value from Raw PCS for rx_ack" "0,1" group.word 0xC040++0x1 line.word 0x0 "RAWLANE0_DIG_PCS_XF_RX_ADAPT_ACK,RX Adaptation Acknowledge" newline hexmask.word 0x0 1.--15. 1. "RESERVED_15_1,Reserved for Future use" newline bitfld.word 0x0 0. "RX_ADAPT_ACK,RX Adaptation Acknowledge" "0,1" group.word 0xC044++0x1 line.word 0x0 "RAWLANE0_DIG_PCS_XF_RX_ADAPT_FOM,RX Adaptation Figure of Merit" newline hexmask.word.byte 0x0 8.--15. 1. "RESERVED_15_8,Reserved for Future use" newline hexmask.word.byte 0x0 0.--7. 1. "RX_ADAPT_FOM,RX Adaptation Figure of Merit" group.word 0xC048++0x1 line.word 0x0 "RAWLANE0_DIG_PCS_XF_RX_TXPRE_DIR,RX calculated direction for TX-pre" newline hexmask.word 0x0 2.--15. 1. "RESERVED_15_2,Reserved for Future use" newline bitfld.word 0x0 0.--1. "RX_TXPRE_DIR,RX calculated direction for TX-pre 00 - No change 01 - Increment 10 - Decrement 11 - Reserved" "No change,Increment,?,?" group.word 0xC04C++0x1 line.word 0x0 "RAWLANE0_DIG_PCS_XF_RX_TXMAIN_DIR,RX calculated direction for TX-Main" newline hexmask.word 0x0 2.--15. 1. "RESERVED_15_2,Reserved for Future use" newline bitfld.word 0x0 0.--1. "RX_TXMAIN_DIR,RX calculated direction for TX-Main 00 - No change 01 - Increment 10 - Decrement 11 - Reserved" "No change,Increment,?,?" group.word 0xC050++0x1 line.word 0x0 "RAWLANE0_DIG_PCS_XF_RX_TXPOST_DIR,RX calculated direction for TX-Post" newline hexmask.word 0x0 2.--15. 1. "RESERVED_15_2,Reserved for Future use" newline bitfld.word 0x0 0.--1. "RX_TXPOST_DIR,RX calculated direction for TX-Post 00 - No change 01 - Increment 10 - Decrement 11 - Reserved" "No change,Increment,?,?" rgroup.word 0xC054++0x1 line.word 0x0 "RAWLANE0_DIG_PCS_XF_LANE_NUMBER,Current lane number" newline hexmask.word 0x0 4.--15. 1. "RESERVED_15_4,Reserved for Future use" newline hexmask.word.byte 0x0 0.--3. 1. "LANE_NUMBER,Current lane number" group.word 0xC058++0x1 line.word 0x0 "RAWLANE0_DIG_PCS_XF_LANE_XCVR_MODE_OVRD_IN,Override incoming values for lane_xcvr_mode" newline hexmask.word 0x0 3.--15. 1. "RESERVED_15_3,Reserved for Future use" newline bitfld.word 0x0 2. "LANE_XCVR_MODE_OVRD_EN,Enable override value for lane_xcvr_mode" "0,1" newline bitfld.word 0x0 0.--1. "LANE_XCVR_MODE_OVRD_VAL,Override value for lane_xcvr_mode" "0,1,2,3" rgroup.word 0xC05C++0x1 line.word 0x0 "RAWLANE0_DIG_PCS_XF_LANE_XCVR_MODE_IN,Lane transceiver mode status" newline hexmask.word 0x0 2.--15. 1. "RESERVED_15_2,Reserved for Future use" newline bitfld.word 0x0 0.--1. "LANE_XCVR_MODE,Lane transceiver mode Determines whether this lane is being used as Tx Rx or Tx/Rx 00 - Reserved 01 - Lane is used for Tx only 10 - Lane is used for Rx only 11 - Lane is used for Tx/Rx" "Reserved,Lane is used for Tx only,?,?" group.word 0xC060++0x1 line.word 0x0 "RAWLANE0_DIG_PCS_XF_ATE_OVRD_IN,ATE Override input to control top-level inputs" newline hexmask.word.byte 0x0 12.--15. 1. "RESERVED_15_12,Reserved for Future use" newline bitfld.word 0x0 11. "RX_ADAPT_DFE_EN_OVRD_EN,Enable override value for rx_adapt_dfe_en input" "0,1" newline bitfld.word 0x0 10. "RX_ADAPT_DFE_EN_OVRD_VAL,Override value for rx_adapt_dfe_en input" "0,1" newline bitfld.word 0x0 9. "RX_ADAPT_AFE_EN_OVRD_EN,Enable override value for rx_adapt_afe_en input" "0,1" newline bitfld.word 0x0 8. "RX_ADAPT_AFE_EN_OVRD_VAL,Override value for rx_adapt_afe_en input" "0,1" newline bitfld.word 0x0 7. "TX_REQ_ATE_OVRD_EN,Enable override value for tx_req input" "0,1" newline bitfld.word 0x0 6. "TX_REQ_ATE_OVRD_VAL,Override value for top-level tx_req input" "0,1" newline bitfld.word 0x0 5. "RX_REQ_ATE_OVRD_EN,Enable override value for rx_req input" "0,1" newline bitfld.word 0x0 4. "RX_REQ_ATE_OVRD_VAL,Override value for top-level rx_req input" "0,1" newline bitfld.word 0x0 3. "TX_RESET_ATE_OVRD_EN,Enable override value for tx_reset input" "0,1" newline bitfld.word 0x0 2. "TX_RESET_ATE_OVRD_VAL,Override value for top-level tx_reset input" "0,1" newline bitfld.word 0x0 1. "RX_RESET_ATE_OVRD_EN,Enable override value for rx_reset input" "0,1" newline bitfld.word 0x0 0. "RX_RESET_ATE_OVRD_VAL,Override value for top-level rx_reset input" "0,1" group.word 0xC064++0x1 line.word 0x0 "RAWLANE0_DIG_PCS_XF_RX_EQ_DELTA_IQ_OVRD_IN,Override incoming values for rx_eq_delta_iq" newline hexmask.word 0x0 5.--15. 1. "RESERVED_15_5,Reserved for Future use" newline bitfld.word 0x0 4. "RX_EQ_DELTA_IQ_OVRD_EN,Enable override value for rx_eq_delta_iq" "0,1" newline hexmask.word.byte 0x0 0.--3. 1. "RX_EQ_DELTA_IQ_OVRD_VAL,Override value for rx_eq_delta_iq" group.word 0xC068++0x1 line.word 0x0 "RAWLANE0_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN,Override incoming values for tx/rx_term_ctrl" newline hexmask.word.byte 0x0 8.--15. 1. "RESERVED_15_8,Reserved for Future use" newline bitfld.word 0x0 7. "TX_TERM_CTRL_OVRD_EN,Enable override value for tx_term_ctrl" "0,1" newline bitfld.word 0x0 4.--6. "TX_TERM_CTRL_OVRD_VAL,Override value for tx_term_ctrl" "0,1,2,3,4,5,6,7" newline bitfld.word 0x0 3. "RX_TERM_CTRL_OVRD_EN,Enable override value for rx_term_ctrl" "0,1" newline bitfld.word 0x0 0.--2. "RX_TERM_CTRL_OVRD_VAL,Override value for rx_term_ctrl" "0,1,2,3,4,5,6,7" rgroup.word 0xC06C++0x1 line.word 0x0 "RAWLANE0_DIG_PCS_XF_TXRX_TERM_CTRL_IN,tx/rx_term_ctrl status" newline hexmask.word 0x0 6.--15. 1. "RESERVED_15_6,Reserved for Future use" newline bitfld.word 0x0 3.--5. "TX_TERM_CTRL,tx_term_ctrl value" "0,1,2,3,4,5,6,7" newline bitfld.word 0x0 0.--2. "RX_TERM_CTRL,tx_term_ctrl value" "0,1,2,3,4,5,6,7" group.word 0xC070++0x1 line.word 0x0 "RAWLANE0_DIG_PCS_XF_RX_OVRD_OUT_1,Override values for outgoing RX controls to PCS. register #1" newline hexmask.word 0x0 1.--15. 1. "RESERVED_15_1,Reserved for Future use" newline bitfld.word 0x0 0. "RX_CLK_EN,Enable the outging rx_clk" "0,1" group.word 0xC074++0x1 line.word 0x0 "RAWLANE0_DIG_PCS_XF_RX_EQ_OVRD_IN_1,Override values for incoming RX EQ controls from PCS. register #1" newline hexmask.word.byte 0x0 8.--15. 1. "RESERVED_15_8,Reserved for Future use" newline bitfld.word 0x0 7. "RX_EQ_OVRD_EN,Enable override values for all RX EQ settings" "0,1" newline bitfld.word 0x0 4.--6. "RX_EQ_ATT_LVL_OVRD_VAL,Override value for rx_eq_att_lvl[2:0]" "0,1,2,3,4,5,6,7" newline hexmask.word.byte 0x0 0.--3. 1. "RX_EQ_AFE_GAIN_OVRD_VAL,Override value for rx_eq_afe_gain[3:0]" group.word 0xC078++0x1 line.word 0x0 "RAWLANE0_DIG_PCS_XF_RX_EQ_OVRD_IN_2,Override values for incoming RX EQ controls from PCS. register #2" newline rbitfld.word 0x0 13.--15. "RESERVED_15_13,Reserved for Future use" "0,1,2,3,4,5,6,7" newline hexmask.word.byte 0x0 8.--12. 1. "RX_EQ_CTLE_BOOST_OVRD_VAL,Override value for rx_eq_ctle_boost[4:0]" newline hexmask.word.byte 0x0 0.--7. 1. "RX_EQ_DFE_TAP1_OVRD_VAL,Override value for rx_eq_dfe_tap1[7:0]" group.word 0xC07C++0x1 line.word 0x0 "RAWLANE0_DIG_PCS_XF_RX_OVRD_OUT_2,Override value for RX VALID/DATA_EN/DATA_EN_ATE signal from PCS" newline hexmask.word.byte 0x0 11.--15. 1. "RESERVED_15_11,Reserved for Future use" newline bitfld.word 0x0 10. "RX_RATE_ATE_OVRD_EN,Override enable for rx_rate_ate" "0,1" newline bitfld.word 0x0 8.--9. "RX_RATE_ATE_OVRD_VAL,Override value for rx_rate_ate" "0,1,2,3" newline bitfld.word 0x0 7. "RX_CDR_TRACK_EN_ATE_OVRD_EN,Override enable for rx_cdr_track_en_ate" "0,1" newline bitfld.word 0x0 6. "RX_CDR_TRACK_EN_ATE_OVRD_VAL,Override value for rx_cdr_track_en_ate" "0,1" newline bitfld.word 0x0 5. "RX_DATA_EN_ATE_OVRD_EN,Override enable for rx_data_en_ate" "0,1" newline bitfld.word 0x0 4. "RX_DATA_EN_ATE_OVRD_VAL,Override value for rx_data_en_ate" "0,1" newline bitfld.word 0x0 3. "RX_DATA_EN_OVRD_EN,Override enable for rx_data_en" "0,1" newline bitfld.word 0x0 2. "RX_DATA_EN_OVRD_VAL,Override value for rx_data_en" "0,1" newline bitfld.word 0x0 1. "RX_VALID_OVRD_EN,Override enable for rx_valid" "0,1" newline bitfld.word 0x0 0. "RX_VALID_OVRD_VAL,Override value for rx_valid" "0,1" group.word 0xC080++0x1 line.word 0x0 "RAWLANE0_DIG_FSM_FSM_OVRD_CTL,FSM override control register" newline rbitfld.word 0x0 15. "RESERVED_15_15,Reserved for Future use" "0,1" newline bitfld.word 0x0 14. "FSM_OVRD_EN,Enable overriding the FSM execution of commands Must be asserted to use FSM_CMD_START and FSM_JMP_EN features" "0,1" newline bitfld.word 0x0 13. "FSM_CMD_START,Start executing the new command This is a self-clearing bit" "0,1" newline bitfld.word 0x0 12. "FSM_JMP_EN,Force the FSM to jump to FSM_JMP_ADDR in the program memory Is applied when FSM_CMD_START is pulsed." "0,1" newline hexmask.word 0x0 0.--11. 1. "FSM_JMP_ADDR,The jump address used when FSM_JUMP_EN=1 The address is encoded as follows: [11:8] mem_lane [7:5] bank [4:0] register" rgroup.word 0xC084++0x1 line.word 0x0 "RAWLANE0_DIG_FSM_MEM_ADDR_MON,Memory Address Monitor" newline hexmask.word 0x0 0.--15. 1. "MEM_ADDR,Current value of memory address used in Lane FSM" rgroup.word 0xC088++0x1 line.word 0x0 "RAWLANE0_DIG_FSM_STATUS_MON,FSM Status Monitor" newline hexmask.word.byte 0x0 11.--15. 1. "RESERVED_15_11,Reserved for Future use" newline bitfld.word 0x0 10. "RDMSK_DISABLED,Check if read mask is currently disabled (i.e. mask is all ones)" "0,1" newline bitfld.word 0x0 9. "WRMSK_DISABLED,Check if write mask is currently disabled (i.e. mask is all ones)" "0,1" newline bitfld.word 0x0 8. "WAIT_CNT_EQ0,Check if wait counter currently equals zero" "0,1" newline bitfld.word 0x0 7. "ALU_RES_EQ0,Check if ALU result register currently equals zero" "0,1" newline bitfld.word 0x0 6. "ALU_OVFLW,Current value of ALU overflow bit" "0,1" newline bitfld.word 0x0 5. "CMD_RDY,New command is ready for execution (applicable when FSM_OVRD_EN=1)" "0,1" newline hexmask.word.byte 0x0 0.--4. 1. "STATE,Current state of Lane FSM" rgroup.word 0xC08C++0x1 line.word 0x0 "RAWLANE0_DIG_FSM_FAST_RX_STARTUP_CAL,Status of Fast RX Start Up Calibration" newline hexmask.word 0x0 1.--15. 1. "RESERVED_15_1,Reserved for Future use" newline bitfld.word 0x0 0. "FAST_RX_STARTUP_CAL,Status of fast RX start-up calibration" "0,1" rgroup.word 0xC090++0x1 line.word 0x0 "RAWLANE0_DIG_FSM_FAST_RX_ADAPT,Status of Fast RX Adaptation" newline hexmask.word 0x0 1.--15. 1. "RESERVED_15_1,Reserved for Future use" newline bitfld.word 0x0 0. "FAST_RX_ADAPT,Status of fast RX adaptation" "0,1" rgroup.word 0xC094++0x1 line.word 0x0 "RAWLANE0_DIG_FSM_FAST_RX_AFE_CAL,Status of Fast RX AFE Calibration" newline hexmask.word 0x0 1.--15. 1. "RESERVED_15_1,Reserved for Future use" newline bitfld.word 0x0 0. "FAST_RX_AFE_CAL,Status of fast RX AFE DAC start-up calibration" "0,1" rgroup.word 0xC098++0x1 line.word 0x0 "RAWLANE0_DIG_FSM_FAST_RX_DFE_CAL,Status of Fast RX DFE Calibration" newline hexmask.word 0x0 1.--15. 1. "RESERVED_15_1,Reserved for Future use" newline bitfld.word 0x0 0. "FAST_RX_DFE_CAL,Status of fast RX DFE slicer start-up calibration" "0,1" rgroup.word 0xC09C++0x1 line.word 0x0 "RAWLANE0_DIG_FSM_FAST_RX_DFE_RE_ADAPT,Enables fast RX DFE re -adaptation" newline hexmask.word 0x0 1.--15. 1. "RESERVED_15_1,Reserved for Future use" newline bitfld.word 0x0 0. "FAST_RX_DFE_RE_ADAPT,Enables fast RX DFE re -adaptation" "0,1" rgroup.word 0xC0A0++0x1 line.word 0x0 "RAWLANE0_DIG_FSM_FAST_RX_REFLVL_CAL,Status of Fast RX Reference Level Calibration" newline hexmask.word 0x0 1.--15. 1. "RESERVED_15_1,Reserved for Future use" newline bitfld.word 0x0 0. "FAST_RX_REFLVL_CAL,Status of fast RX reference level (100mv 125mv 150mv) start-up calibration" "0,1" rgroup.word 0xC0A4++0x1 line.word 0x0 "RAWLANE0_DIG_FSM_FAST_RX_IQ_CAL,Status of Fast RX IQ Calibration" newline hexmask.word 0x0 1.--15. 1. "RESERVED_15_1,Reserved for Future use" newline bitfld.word 0x0 0. "FAST_RX_IQ_CAL,Status of fast RX IQ start-up calibration" "0,1" rgroup.word 0xC0A8++0x1 line.word 0x0 "RAWLANE0_DIG_FSM_FAST_RX_AFE_ADAPT,Status of Fast RX AFE Adaptation" newline hexmask.word 0x0 1.--15. 1. "RESERVED_15_1,Reserved for Future use" newline bitfld.word 0x0 0. "FAST_RX_AFE_ADAPT,Status of fast RX AFE DAC start-up adaptation" "0,1" rgroup.word 0xC0AC++0x1 line.word 0x0 "RAWLANE0_DIG_FSM_FAST_RX_DFE_ADAPT,Status of Fast RX DFE Adaptation" newline hexmask.word 0x0 1.--15. 1. "RESERVED_15_1,Reserved for Future use" newline bitfld.word 0x0 0. "FAST_RX_DFE_ADAPT,Status of fast RX DFE DAC start-up adaptation" "0,1" rgroup.word 0xC0B0++0x1 line.word 0x0 "RAWLANE0_DIG_FSM_FAST_SUP,Status of Fast Support block" newline hexmask.word 0x0 1.--15. 1. "RESERVED_15_1,Reserved for Future use" newline bitfld.word 0x0 0. "FAST_SUP,Status of fast Support block (MPLL and Rtune)" "0,1" rgroup.word 0xC0B4++0x1 line.word 0x0 "RAWLANE0_DIG_FSM_FAST_TX_CMN_MODE,Status of Fast TX Common-mode Charge-up" newline hexmask.word 0x0 1.--15. 1. "RESERVED_15_1,Reserved for Future use" newline bitfld.word 0x0 0. "FAST_TX_CMN_MODE,Status of fast TX Common-mode Charge-up" "0,1" rgroup.word 0xC0B8++0x1 line.word 0x0 "RAWLANE0_DIG_FSM_FAST_TX_RXDET,Status of Fast TX detect RX" newline hexmask.word 0x0 1.--15. 1. "RESERVED_15_1,Reserved for Future use" newline bitfld.word 0x0 0. "FAST_TX_RXDET,Status of fast TX detect RX" "0,1" rgroup.word 0xC0BC++0x1 line.word 0x0 "RAWLANE0_DIG_FSM_FAST_RX_PWRUP,Status of Fast RX Power-up" newline hexmask.word 0x0 1.--15. 1. "RESERVED_15_1,Reserved for Future use" newline bitfld.word 0x0 0. "FAST_RX_PWRUP,Status of fast RX Power-up (LOS VREG/AFE and DCC)" "0,1" rgroup.word 0xC0C0++0x1 line.word 0x0 "RAWLANE0_DIG_FSM_FAST_RX_VCO_WAIT,Status of Fast RX VCO Wait Times" newline hexmask.word 0x0 1.--15. 1. "RESERVED_15_1,Reserved for Future use" newline bitfld.word 0x0 0. "FAST_RX_VCO_WAIT,Status of fast RX VCO wait times" "0,1" rgroup.word 0xC0C4++0x1 line.word 0x0 "RAWLANE0_DIG_FSM_FAST_RX_VCO_CAL,Status of Fast RX VCO Calibration" newline hexmask.word 0x0 1.--15. 1. "RESERVED_15_1,Reserved for Future use" newline bitfld.word 0x0 0. "FAST_RX_VCO_CAL,Status of fast RX VCO Calibration" "0,1" rgroup.word 0xC0C8++0x1 line.word 0x0 "RAWLANE0_DIG_FSM_CMNCAL_MPLL_STATUS,Status of MPLL common calibration initiation" newline hexmask.word 0x0 2.--15. 1. "RESERVED_15_2,Reserved for Future use" newline bitfld.word 0x0 1. "CMNCAL_MPLL_DONE,Indicates whether MPLL common calibration has been completed by any lane or not." "0,1" newline bitfld.word 0x0 0. "CMNCAL_MPLL_INIT,Indicates whether MPLL common calibration has been started by any lane or not. ---------------------------------------------------------------------" "0,1" rgroup.word 0xC0CC++0x1 line.word 0x0 "RAWLANE0_DIG_FSM_FAST_RX_CONT_CAL_ADAPT,Status of Fast RX Continuous Calibration/Adaptation" newline hexmask.word 0x0 1.--15. 1. "RESERVED_15_1,Reserved for Future use" newline bitfld.word 0x0 0. "FAST_RX_CONT_CAL_ADAPT,Status of fast RX continuous calibration/adaptation" "0,1" rgroup.word 0xC0D0++0x1 line.word 0x0 "RAWLANE0_DIG_FSM_FAST_RX_CONT_ADAPT,Status of Fast RX Continuous Adaptation" newline hexmask.word 0x0 1.--15. 1. "RESERVED_15_1,Reserved for Future use" newline bitfld.word 0x0 0. "FAST_RX_CONT_ADAPT,Status of fast RX continuous adaptation" "0,1" rgroup.word 0xC0D4++0x1 line.word 0x0 "RAWLANE0_DIG_FSM_FAST_RX_CONT_DATA_CAL,Status of Fast RX Continuous Data Calibration" newline hexmask.word 0x0 1.--15. 1. "RESERVED_15_1,Reserved for Future use" newline bitfld.word 0x0 0. "FAST_RX_CONT_DATA_CAL,Status of fast RX continuous data calibration" "0,1" rgroup.word 0xC0D8++0x1 line.word 0x0 "RAWLANE0_DIG_FSM_FAST_RX_CONT_PHASE_CAL,Status of Fast RX Continuous Phase Calibration" newline hexmask.word 0x0 1.--15. 1. "RESERVED_15_1,Reserved for Future use" newline bitfld.word 0x0 0. "FAST_RX_CONT_PHASE_CAL,Status of fast RX continuous phase calibration" "0,1" rgroup.word 0xC0DC++0x1 line.word 0x0 "RAWLANE0_DIG_FSM_FAST_RX_CONT_AFE_CAL,Status of Fast RX Continuous AFE Calibration" newline hexmask.word 0x0 1.--15. 1. "RESERVED_15_1,Reserved for Future use" newline bitfld.word 0x0 0. "FAST_RX_CONT_AFE_CAL,Status of fast RX continuous AFE calibration" "0,1" rgroup.word 0xC0E0++0x1 line.word 0x0 "RAWLANE0_DIG_FSM_FAST_RX_IQ_ADAPT,Status of Fast RX IQ_ADAPT" newline hexmask.word 0x0 1.--15. 1. "RESERVED_15_1,Reserved for Future use" newline bitfld.word 0x0 0. "FAST_RX_IQ_ADAPT,Status of Fast RX IQ_ADAPT" "0,1" rgroup.word 0xC0E4++0x1 line.word 0x0 "RAWLANE0_DIG_FSM_RX_IQ_DELTA_ADD,Status of RX Delta addition" newline hexmask.word 0x0 1.--15. 1. "RESERVED_15_1,Reserved for Future use" newline bitfld.word 0x0 0. "RX_IQ_DELTA_ADD,Reserved" "0,1" rgroup.word 0xC0E8++0x1 line.word 0x0 "RAWLANE0_DIG_FSM_FAST_RX_ATT_ADAPT,Enables fast RX ATT adaptation" newline hexmask.word 0x0 1.--15. 1. "RESERVED_15_1,Reserved for Future use" newline bitfld.word 0x0 0. "FAST_RX_ATT_ADAPT,Enables fast RX ATT adaptation" "0,1" rgroup.word 0xC0EC++0x1 line.word 0x0 "RAWLANE0_DIG_FSM_FAST_RX_CTLE_ADAPT,Enables fast RX CTLE adaptation" newline hexmask.word 0x0 1.--15. 1. "RESERVED_15_1,Reserved for Future use" newline bitfld.word 0x0 0. "FAST_RX_CTLE_ADAPT,Enables fast RX CTLE adaptation" "0,1" group.word 0xC0F0++0x1 line.word 0x0 "RAWLANE0_DIG_FSM_CR_REG_OP_XTND_EN,CR interface timing extension enable" newline hexmask.word 0x0 1.--15. 1. "RESERVED_15_1,Reserved for Future use" newline bitfld.word 0x0 0. "CR_REG_OP_XTND_EN,CR interface timing extension enable 1'b0 - No Timing extension 1'b1 - Timing extension" "No Timing extension,Timing extension" group.word 0xC0F4++0x1 line.word 0x0 "RAWLANE0_DIG_FSM_TX_EQ_UPDATE_FLAG,TX Eq update flag" newline hexmask.word 0x0 1.--15. 1. "RESERVED_15_1,Reserved for Future use" newline bitfld.word 0x0 0. "TX_EQ_UPDATE_FLAG,Tx Eq update flag 1'b0 - Update tx eq post 1'b1 - Update tx eq pre" "Update tx eq post,Update tx eq pre" rgroup.word 0xC0F8++0x1 line.word 0x0 "RAWLANE0_DIG_FSM_CMNCAL_RCAL_STATUS,Status of RTUNE common calibration initiation" newline hexmask.word 0x0 2.--15. 1. "RESERVED_15_2,Reserved for Future use" newline bitfld.word 0x0 1. "CMNCAL_RCAL_DONE,Indicates whether RTUNE common calibration has been completed by any lane or not." "0,1" newline bitfld.word 0x0 0. "CMNCAL_RCAL_INIT,Indicates whether RTUNE common calibration has been started by any lane or not. ---------------------------------------------------------------------" "0,1" rgroup.word 0xC0FC++0x1 line.word 0x0 "RAWLANE0_DIG_FSM_RX_IQ_PHASE_OFFSET,Offset value for IQ Phase Calculation" newline hexmask.word 0x0 4.--15. 1. "RESERVED_15_4,Reserved for Future use" newline hexmask.word.byte 0x0 0.--3. 1. "RX_IQ_PHASE_OFFSET,Offset value for IQ Phase Calculation" group.word 0xC100++0x1 line.word 0x0 "RAWLANE0_DIG_AON_AFE_ATT_IDAC_OFST,Offset value for RX AFE ATT iDAC" newline hexmask.word.byte 0x0 8.--15. 1. "RESERVED_15_8,Reserved for Future use" newline hexmask.word.byte 0x0 0.--7. 1. "AFE_ATT_IDAC_OFST,Offset value for AFE ATT iDAC" group.word 0xC104++0x1 line.word 0x0 "RAWLANE0_DIG_AON_AFE_CTLE_IDAC_OFST,Offset value for RX AFE CTLE iDAC" newline hexmask.word.byte 0x0 8.--15. 1. "RESERVED_15_8,Reserved for Future use" newline hexmask.word.byte 0x0 0.--7. 1. "AFE_CTLE_IDAC_OFST,Offset value for AFE CTLE iDAC" group.word 0xC108++0x1 line.word 0x0 "RAWLANE0_DIG_AON_ADAPT_REF_LVL_DAC_CODE,Reference level for RX AFE Adaptation" newline hexmask.word.byte 0x0 8.--15. 1. "RESERVED_15_8,Reserved for Future use" newline hexmask.word.byte 0x0 0.--7. 1. "ADAPT_REF_LVL_DAC_CODE,Reference level for RX AFE Adaptation" group.word 0xC10C++0x1 line.word 0x0 "RAWLANE0_DIG_AON_RX_ADAPT_FOM,Adaptation Figure of Merit (FOM)" newline hexmask.word.byte 0x0 8.--15. 1. "RESERVED_15_8,Reserved for Future use" newline hexmask.word.byte 0x0 0.--7. 1. "RX_ADAPT_FOM,Adaptation Figure of Merit (FOM)" group.word 0xC110++0x1 line.word 0x0 "RAWLANE0_DIG_AON_AFE_CTLE_LBK_IDAC_OFST,Offset values for RX CTLE Loopback path iDAC" newline hexmask.word.byte 0x0 8.--15. 1. "RESERVED_15_8,Reserved for Future use" newline hexmask.word.byte 0x0 0.--7. 1. "AFE_CTLE_LBK_IDAC_OFST,Offset value for RX CTLE Loopback path iDAC" group.word 0xC114++0x1 line.word 0x0 "RAWLANE0_DIG_AON_DFE_PHASE_EVEN_VDAC_OFST,Offset values for RX DFE Phase Even vDAC" newline hexmask.word.byte 0x0 8.--15. 1. "RESERVED_15_8,Reserved for Future use" newline hexmask.word.byte 0x0 0.--7. 1. "DFE_PHASE_EVEN_VDAC_OFST,Offset value for DFE Phase Even vDAC" group.word 0xC118++0x1 line.word 0x0 "RAWLANE0_DIG_AON_DFE_PHASE_ODD_VDAC_OFST,Offset values for RX DFE Phase Odd vDAC" newline hexmask.word.byte 0x0 8.--15. 1. "RESERVED_15_8,Reserved for Future use" newline hexmask.word.byte 0x0 0.--7. 1. "DFE_PHASE_ODD_VDAC_OFST,Offset value for DFE Phase Odd vDAC" group.word 0xC11C++0x1 line.word 0x0 "RAWLANE0_DIG_AON_DFE_EVEN_REF_LVL,DFE Even reference level" newline hexmask.word.byte 0x0 8.--15. 1. "RESERVED_15_8,Reserved for Future use" newline hexmask.word.byte 0x0 0.--7. 1. "DFE_EVEN_REF_LVL,DFE Even reference level" group.word 0xC120++0x1 line.word 0x0 "RAWLANE0_DIG_AON_DFE_ODD_REF_LVL,DFE Odd reference level" newline hexmask.word.byte 0x0 8.--15. 1. "RESERVED_15_8,Reserved for Future use" newline hexmask.word.byte 0x0 0.--7. 1. "DFE_ODD_REF_LVL,DFE Odd reference level" group.word 0xC124++0x1 line.word 0x0 "RAWLANE0_DIG_AON_RX_PHSADJ_LIN,RX Phase Adjust Linear Value" newline hexmask.word 0x0 5.--15. 1. "RESERVED_15_5,Reserved for Future use" newline hexmask.word.byte 0x0 0.--4. 1. "RX_PHSADJ_LIN,Linear value for RX phase adjust" rgroup.word 0xC128++0x1 line.word 0x0 "RAWLANE0_DIG_AON_RX_PHSADJ_MAP,RX Phase Adjust Mapped Value" newline hexmask.word 0x0 5.--15. 1. "RESERVED_15_5,Reserved for Future use" newline hexmask.word.byte 0x0 0.--4. 1. "RX_PHSADJ_MAP,Mapped value for RX phase adjust" group.word 0xC12C++0x1 line.word 0x0 "RAWLANE0_DIG_AON_DFE_DATA_EVEN_HIGH_VDAC_OFST,Offset values for RX DFE Data Even High vDAC" newline hexmask.word.byte 0x0 8.--15. 1. "RESERVED_15_8,Reserved for Future use" newline hexmask.word.byte 0x0 0.--7. 1. "DFE_DATA_EVEN_HIGH_VDAC_OFST,Offset value for DFE Data Even High vDAC" group.word 0xC130++0x1 line.word 0x0 "RAWLANE0_DIG_AON_DFE_DATA_EVEN_LOW_VDAC_OFST,Offset values for RX DFE Data Even Low vDAC" newline hexmask.word 0x0 0.--15. 1. "DFE_DATA_EVEN_LOW_VDAC_OFST,Offset value for DFE Data Even Low vDAC" group.word 0xC134++0x1 line.word 0x0 "RAWLANE0_DIG_AON_DFE_DATA_ODD_HIGH_VDAC_OFST,Offset values for RX DFE Data Odd High vDAC" newline hexmask.word.byte 0x0 8.--15. 1. "RESERVED_15_8,Reserved for Future use" newline hexmask.word.byte 0x0 0.--7. 1. "DFE_DATA_ODD_HIGH_VDAC_OFST,Offset value for DFE Data Odd High vDAC" group.word 0xC138++0x1 line.word 0x0 "RAWLANE0_DIG_AON_DFE_DATA_ODD_LOW_VDAC_OFST,Offset values for RX DFE Data Odd Low vDAC" newline hexmask.word 0x0 0.--15. 1. "DFE_DATA_ODD_LOW_VDAC_OFST,Offset value for DFE Data Odd Low vDAC" group.word 0xC13C++0x1 line.word 0x0 "RAWLANE0_DIG_AON_DFE_BYPASS_EVEN_VDAC_OFST,Offset values for RX DFE By-Pass Even vDAC" newline hexmask.word.byte 0x0 8.--15. 1. "RESERVED_15_8,Reserved for Future use" newline hexmask.word.byte 0x0 0.--7. 1. "DFE_BYPASS_EVEN_VDAC_OFST,Offset value for DFE By-Pass Even vDAC" group.word 0xC140++0x1 line.word 0x0 "RAWLANE0_DIG_AON_DFE_BYPASS_ODD_VDAC_OFST,Offset values for RX DFE By-Pass Odd vDAC" newline hexmask.word.byte 0x0 8.--15. 1. "RESERVED_15_8,Reserved for Future use" newline hexmask.word.byte 0x0 0.--7. 1. "DFE_BYPASS_ODD_VDAC_OFST,Offset value for DFE By-Pass Odd vDAC" group.word 0xC144++0x1 line.word 0x0 "RAWLANE0_DIG_AON_DFE_ERROR_EVEN_VDAC_OFST,Offset values for RX DFE Error Even vDAC" newline hexmask.word.byte 0x0 8.--15. 1. "RESERVED_15_8,Reserved for Future use" newline hexmask.word.byte 0x0 0.--7. 1. "DFE_ERROR_EVEN_VDAC_OFST,Offset value for DFE Error Even vDAC" group.word 0xC148++0x1 line.word 0x0 "RAWLANE0_DIG_AON_DFE_ERROR_ODD_VDAC_OFST,Offset values for RX DFE Error Odd vDAC" newline hexmask.word.byte 0x0 8.--15. 1. "RESERVED_15_8,Reserved for Future use" newline hexmask.word.byte 0x0 0.--7. 1. "DFE_ERROR_ODD_VDAC_OFST,Offset value for DFE Error Odd vDAC" group.word 0xC14C++0x1 line.word 0x0 "RAWLANE0_DIG_AON_RX_IQ_PHASE_ADJUST,Value for RX IQ PHASE Adjust" newline hexmask.word 0x0 7.--15. 1. "RESERVED_15_7,Reserved for Future use" newline hexmask.word.byte 0x0 0.--6. 1. "RX_IQ_PHASE_ADJUST,Value for RX IQ PHASE Adjust" group.word 0xC150++0x1 line.word 0x0 "RAWLANE0_DIG_AON_MPLLA_COARSE_TUNE,MPLLA_COARSE_TUNE" newline hexmask.word.byte 0x0 8.--15. 1. "RESERVED_15_8,Reserved for Future use" newline hexmask.word.byte 0x0 0.--7. 1. "MPLLA_COARSE_TUNE,Stored coarse tune value for MPLLA" group.word 0xC154++0x1 line.word 0x0 "RAWLANE0_DIG_AON_MPLLB_COARSE_TUNE,MPLLB_COARSE_TUNE" newline hexmask.word.byte 0x0 8.--15. 1. "RESERVED_15_8,Reserved for Future use" newline hexmask.word.byte 0x0 0.--7. 1. "MPLLB_COARSE_TUNE,Stored coarse tune value for MPLLB" group.word 0xC158++0x1 line.word 0x0 "RAWLANE0_DIG_AON_INIT_PWRUP_DONE,Initial Power-Up Done Status" newline hexmask.word 0x0 1.--15. 1. "RESERVED_15_1,Reserved for Future use" newline bitfld.word 0x0 0. "INIT_PWRUP_DONE,Indicates whether initial power-up has completed or not." "0,1" group.word 0xC15C++0x1 line.word 0x0 "RAWLANE0_DIG_AON_RX_ADPT_ATT,RX Adapted value of ATT" newline hexmask.word.byte 0x0 8.--15. 1. "RESERVED_15_8,Reserved for Future use" newline hexmask.word.byte 0x0 0.--7. 1. "ATT_ADPT_VAL,Stored RX adapted ATT value" group.word 0xC160++0x1 line.word 0x0 "RAWLANE0_DIG_AON_RX_ADPT_VGA,RX Adapted value of VGA" newline hexmask.word.byte 0x0 10.--15. 1. "RESERVED_15_10,Reserved for Future use" newline hexmask.word 0x0 0.--9. 1. "VGA_ADPT_VAL,Stored RX adapted VGA value" group.word 0xC164++0x1 line.word 0x0 "RAWLANE0_DIG_AON_RX_ADPT_CTLE,RX Adapted value of CTLE" newline rbitfld.word 0x0 13.--15. "RESERVED_15_13,Reserved for Future use" "0,1,2,3,4,5,6,7" newline bitfld.word 0x0 10.--12. "CTLE_POLE_ADPT_VAL,Stored RX adapted CTLE pole value" "0,1,2,3,4,5,6,7" newline hexmask.word 0x0 0.--9. 1. "CTLE_BOOST_ADPT_VAL,Stored RX adapted CTLE boost value" group.word 0xC168++0x1 line.word 0x0 "RAWLANE0_DIG_AON_RX_ADPT_DFE_TAP1,RX Adapted value of DFE TAP1" newline rbitfld.word 0x0 13.--15. "RESERVED_15_13,Reserved for Future use" "0,1,2,3,4,5,6,7" newline hexmask.word 0x0 0.--12. 1. "DFE_TAP1_ADPT_VAL,Stored RX adapted DFE TAP1 value" group.word 0xC16C++0x1 line.word 0x0 "RAWLANE0_DIG_AON_RX_ADAPT_DONE,RX Adaptation Done Status" newline hexmask.word 0x0 1.--15. 1. "RESERVED_15_1,Reserved for Future use" newline bitfld.word 0x0 0. "RX_ADAPT_DONE,Indicates whether RX adaptation has completed or not." "0,1" group.word 0xC170++0x1 line.word 0x0 "RAWLANE0_DIG_AON_FAST_FLAGS,Fast flags for simulation only" newline rbitfld.word 0x0 15. "RESERVED_15_15,Reserved for Future use" "0,1" newline bitfld.word 0x0 14. "FAST_RX_VCO_CAL,Enable fast RX VCO Calibration" "0,1" newline bitfld.word 0x0 13. "FAST_RX_VCO_WAIT,Enable fast RX VCO wait times" "0,1" newline bitfld.word 0x0 12. "FAST_RX_PWRUP,Enable fast RX power-up (LOS VREG/AFE and DCC)" "0,1" newline bitfld.word 0x0 11. "FAST_TX_RXDET,Enable fast TX Detect RX" "0,1" newline bitfld.word 0x0 10. "FAST_TX_CMN_MODE,Enable fast TX Common Mode Charge-up" "0,1" newline bitfld.word 0x0 9. "FAST_SUP,Enable fast Support block (MPLL and Rtune)" "0,1" newline bitfld.word 0x0 8. "FAST_RX_DFE_ADAPT,Enables fast RX DFE DAC start-up adaptation" "0,1" newline bitfld.word 0x0 7. "FAST_RX_AFE_ADAPT,Enables fast RX AFE DAC start-up adaptation" "0,1" newline bitfld.word 0x0 6. "FAST_RX_IQ_CAL,Enables fast RX IQ start-up calibration" "0,1" newline bitfld.word 0x0 5. "FAST_RX_REFLVL_CAL,Enables fast RX reference level (100mv 125mv 150mv) start-up calibration" "0,1" newline bitfld.word 0x0 4. "FAST_RX_DFE_RE_ADAPT,Enables fast RX DFE re -adaptation" "0,1" newline bitfld.word 0x0 3. "FAST_RX_DFE_CAL,Enables fast RX DFE slicer start-up calibration" "0,1" newline bitfld.word 0x0 2. "FAST_RX_AFE_CAL,Enables fast RX AFE DAC start-up calibration" "0,1" newline bitfld.word 0x0 1. "FAST_RX_ADAPT,Enables fast RX adaptation" "0,1" newline bitfld.word 0x0 0. "FAST_RX_STARTUP_CAL,Enables fast RX start-up calibration" "0,1" group.word 0xC174++0x1 line.word 0x0 "RAWLANE0_DIG_AON_RX_ADPT_DFE_TAP2,RX Adapted value of DFE TAP2" newline hexmask.word.byte 0x0 12.--15. 1. "RESERVED_15_12,Reserved for Future use" newline hexmask.word 0x0 0.--11. 1. "DFE_TAP2_ADPT_VAL,Stored RX adapted DFE TAP2 value" group.word 0xC178++0x1 line.word 0x0 "RAWLANE0_DIG_AON_RX_PHSADJ_LIN_RIGHT,RX last stable iq phase of Right of the eye" newline hexmask.word.byte 0x0 8.--15. 1. "RESERVED,Reserved bits" newline hexmask.word.byte 0x0 0.--7. 1. "RX_PHSADJ_LIN_RIGHT,Stored RX iq phase right edge" group.word 0xC17C++0x1 line.word 0x0 "RAWLANE0_DIG_AON_RX_PHSADJ_LIN_LEFT,RX last stable iq phase of Left of the eye" newline hexmask.word.byte 0x0 8.--15. 1. "RESERVED,Reserved bits" newline hexmask.word.byte 0x0 0.--7. 1. "RX_PHSADJ_LIN_LEFT,Stored RX iq phase left edge" group.word 0xC180++0x1 line.word 0x0 "RAWLANE0_DIG_AON_RX_PHSADJ_LIN_ADAPT,RX Adapted value of PHASE IQ" newline hexmask.word.byte 0x0 8.--15. 1. "RESERVED,Reserved bits" newline hexmask.word.byte 0x0 0.--7. 1. "RX_PHSADJ_LIN_ADAPT,Stored RX adapted IQ value" group.word 0xC184++0x1 line.word 0x0 "RAWLANE0_DIG_AON_RX_SLICER_CTRL_EVEN,Sets values for RX SLICER CTRL EVEN signals going to ANA" newline hexmask.word 0x0 4.--15. 1. "RESERVED_15_4,Reserved for Future use" newline hexmask.word.byte 0x0 0.--3. 1. "RX_ANA_SLICER_CTRL_E,Value for rx_ana_slicer_ctrl_e[3:0]" group.word 0xC188++0x1 line.word 0x0 "RAWLANE0_DIG_AON_RX_SLICER_CTRL_ODD,Sets values for RX SLICER CTRL ODD signals going to ANA" newline hexmask.word 0x0 4.--15. 1. "RESERVED_15_4,Reserved for Future use" newline hexmask.word.byte 0x0 0.--3. 1. "RX_ANA_SLICER_CTRL_O,Value for rx_ana_slicer_ctrl_o[3:0]" group.word 0xC18C++0x1 line.word 0x0 "RAWLANE0_DIG_AON_LANE_CMNCAL_MPLL_STATUS,MPLL Common Calibration Status" newline hexmask.word 0x0 2.--15. 1. "RESERVED_15_2,Reserved for Future use" newline bitfld.word 0x0 1. "LANE_CMNCAL_MPLL_DONE,Indicates whether MPLL common calibration has been completed by this lane or not." "0,1" newline bitfld.word 0x0 0. "LANE_CMNCAL_MPLL_INIT,Indicates whether MPLL common calibration has been started by this lane or not." "0,1" repeat 8. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 )(list 0x0 0x4 0x8 0xC 0x10 0x14 0x18 0x1C ) group.word ($2+0xC190)++0x1 line.word 0x0 "RAWLANE0_DIG_AON_ADPT_CTL_$1,Adaptation Control register #0" newline hexmask.word 0x0 0.--15. 1. "VAL,Value of adaptation control" repeat.end group.word 0xC1B0++0x1 line.word 0x0 "RAWLANE0_DIG_AON_MPLL_DISABLE,LANE_MPLLA/B_DISABLE override" newline hexmask.word 0x0 2.--15. 1. "RESERVED_15_2,Reserved for Future use" newline bitfld.word 0x0 1. "LANE_MPLLB_DISABLE,Disable MPLLB" "0,1" newline bitfld.word 0x0 0. "LANE_MPLLA_DISABLE,Disable MPLLA" "0,1" group.word 0xC1B4++0x1 line.word 0x0 "RAWLANE0_DIG_AON_FAST_FLAGS_2,Fast flags for simulation only" newline hexmask.word.byte 0x0 12.--15. 1. "RSVD_FAST_FLAGS,Reserved fast flags" newline bitfld.word 0x0 11. "SKIP_IQ_STEP_SKIP,Skip the IQ step skip option" "0,1" newline bitfld.word 0x0 10. "SKIP_250US_WAIT,Skip bit for USB Gen1 250us wait FW WA" "0,1" newline bitfld.word 0x0 9. "WA_ATT_VCM_ISSUE_MODE,Workaround en or disable STAR 9001169835" "0,1" newline bitfld.word 0x0 8. "FAST_RX_CTLE_ADAPT,Enables fast RX CTLE adaptation" "0,1" newline bitfld.word 0x0 7. "FAST_RX_ATT_ADAPT,Enables fast RX ATT adaptation" "0,1" newline bitfld.word 0x0 6. "RX_IQ_DELTA_ADD,Enables RX IQ DELTA addition" "0,1" newline bitfld.word 0x0 5. "FAST_RX_IQ_ADAPT,Enables fast RX IQ ADAPT" "0,1" newline bitfld.word 0x0 4. "FAST_RX_CONT_AFE_CAL,Enables fast RX continuous AFE calibration" "0,1" newline bitfld.word 0x0 3. "FAST_RX_CONT_PHASE_CAL,Enables fast RX continuous phase calibration" "0,1" newline bitfld.word 0x0 2. "FAST_RX_CONT_DATA_CAL,Enables fast RX continuous data calibration" "0,1" newline bitfld.word 0x0 1. "FAST_RX_CONT_ADAPT,Enables fast RX continuous adaptation" "0,1" newline bitfld.word 0x0 0. "FAST_RX_CONT_CAL_ADAPT,Enables fast RX continuous calibration/adaptation" "0,1" group.word 0xC1B8++0x1 line.word 0x0 "RAWLANE0_DIG_AON_LANE_CMNCAL_RCAL_STATUS,RTUNE Common Calibration Status" newline hexmask.word 0x0 2.--15. 1. "RESERVED_15_2,Reserved for Future use" newline bitfld.word 0x0 1. "LANE_CMNCAL_RCAL_DONE,Indicates whether RTUNE common calibration has been completed by this lane or not." "0,1" newline bitfld.word 0x0 0. "LANE_CMNCAL_RCAL_INIT,Indicates whether RTUNE common calibration has been started by this lane or not." "0,1" group.word 0xC1BC++0x1 line.word 0x0 "RAWLANE0_DIG_AON_TXRX_OVRD_IN,Override values for incoming AON TX/RX controls from PCS" newline hexmask.word 0x0 4.--15. 1. "RESERVED_15_4,Reserved for Future use" newline bitfld.word 0x0 3. "TX_DISABLE_OVRD_EN,Override enable for tx_disable" "0,1" newline bitfld.word 0x0 2. "TX_DISABLE_OVRD_VAL,Override value for tx_disable" "0,1" newline bitfld.word 0x0 1. "RX_DISABLE_OVRD_EN,Override enable for rx_disable" "0,1" newline bitfld.word 0x0 0. "RX_DISABLE_OVRD_VAL,Override value for rx_disable" "0,1" group.word 0xC1C0++0x1 line.word 0x0 "RAWLANE0_DIG_AON_AFE_ATT_2_IDAC_OFST,Offset value for RX AFE ATT_2 iDAC" newline hexmask.word.byte 0x0 8.--15. 1. "RESERVED_15_8,Reserved for Future use" newline hexmask.word.byte 0x0 0.--7. 1. "AFE_ATT_2_IDAC_OFST,Offset value for AFE ATT_2 iDAC when cc is 1 in ana typec projects" group.word 0xC1C4++0x1 line.word 0x0 "RAWLANE0_DIG_AON_RXTX_CC_OVRD_IN,Override incoming values for rxtx_cc" newline hexmask.word 0x0 2.--15. 1. "RESERVED_15_2,Reserved for Future use" newline bitfld.word 0x0 1. "RXTX_CC_OVRD_EN,Enable override value for rxtx_cc" "0,1" newline bitfld.word 0x0 0. "RXTX_CC_OVRD_VAL,Override value for rxtx_cc" "0,1" rgroup.word 0xC1C8++0x1 line.word 0x0 "RAWLANE0_DIG_AON_RXTX_CC_STATUS_IN,Incoming value of CC status from TCA" newline hexmask.word 0x0 1.--15. 1. "RESERVED_15_1,Reserved for Future use" newline bitfld.word 0x0 0. "RXTX_CC_IN_I,Value from TCA of cc" "0,1" rgroup.word 0xC1CC++0x1 line.word 0x0 "RAWLANE0_DIG_AON_RXTX_CC_STATUS_OUT,Current values for outgoing CC status to PMA" newline hexmask.word 0x0 1.--15. 1. "RESERVED_15_1,Reserved for Future use" newline bitfld.word 0x0 0. "RXTX_CC_OUT,Value to PMA of cc" "0,1" group.word 0xC200++0x1 line.word 0x0 "RAWLANE0_DIG_IRQ_CTL_RESET_RTN_REQ,Reset routine request" newline hexmask.word 0x0 1.--15. 1. "RESERVED_15_1,Reserved for Future use" newline bitfld.word 0x0 0. "RESET_RTN_REQ,Reset routine request" "0,1" rgroup.word 0xC204++0x1 line.word 0x0 "RAWLANE0_DIG_IRQ_CTL_RX_RESET_IRQ,Rx reset interrupt" newline hexmask.word 0x0 1.--15. 1. "RESERVED_15_1,Reserved for Future use" newline bitfld.word 0x0 0. "RX_RESET,Rx reset interrupt" "0,1" rgroup.word 0xC208++0x1 line.word 0x0 "RAWLANE0_DIG_IRQ_CTL_RX_REQ_IRQ,Rx request interrupt" newline hexmask.word 0x0 1.--15. 1. "RESERVED_15_1,Reserved for Future use" newline bitfld.word 0x0 0. "RX_REQ,Rx request interrupt" "0,1" rgroup.word 0xC20C++0x1 line.word 0x0 "RAWLANE0_DIG_IRQ_CTL_RX_RATE_IRQ,Rx rate change interrupt request" newline hexmask.word 0x0 1.--15. 1. "RESERVED_15_1,Reserved for Future use" newline bitfld.word 0x0 0. "RX_RATE_IRQ,Rx rate change interrupt request" "0,1" rgroup.word 0xC210++0x1 line.word 0x0 "RAWLANE0_DIG_IRQ_CTL_RX_PSTATE_IRQ,Rx pstate change interrupt request" newline hexmask.word 0x0 1.--15. 1. "RESERVED_15_1,Reserved for Future use" newline bitfld.word 0x0 0. "RX_PSTATE_IRQ,Rx pstate change interrupt request" "0,1" rgroup.word 0xC214++0x1 line.word 0x0 "RAWLANE0_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ,Rx adaptation request interrupt" newline hexmask.word 0x0 1.--15. 1. "RESERVED_15_1,Reserved for Future use" newline bitfld.word 0x0 0. "RX_ADAPT_REQ_IRQ,Rx adaptation request interrupt" "0,1" rgroup.word 0xC218++0x1 line.word 0x0 "RAWLANE0_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ,Rx adaptation disable interrupt" newline hexmask.word 0x0 1.--15. 1. "RESERVED_15_1,Reserved for Future use" newline bitfld.word 0x0 0. "RX_ADAPT_DIS_IRQ,Rx adaptation disable interrupt" "0,1" group.word 0xC21C++0x1 line.word 0x0 "RAWLANE0_DIG_IRQ_CTL_RX_RESET_IRQ_CLR,RX reset interrupt clear" newline hexmask.word 0x0 1.--15. 1. "RESERVED_15_1,Reserved for Future use" newline bitfld.word 0x0 0. "RX_RESET_IRQ_CLR,RX reset interrupt clear (self-clearing)" "0,1" group.word 0xC220++0x1 line.word 0x0 "RAWLANE0_DIG_IRQ_CTL_RX_REQ_IRQ_CLR,RX request interrupt clear" newline hexmask.word 0x0 1.--15. 1. "RESERVED_15_1,Reserved for Future use" newline bitfld.word 0x0 0. "RX_REQ_IRQ_CLR,RX request interrupt clear (self-clearing)" "0,1" group.word 0xC224++0x1 line.word 0x0 "RAWLANE0_DIG_IRQ_CTL_RX_RATE_IRQ_CLR,RX rate change interrupt clear" newline hexmask.word 0x0 1.--15. 1. "RESERVED_15_1,Reserved for Future use" newline bitfld.word 0x0 0. "RX_RATE_IRQ_CLR,RX rate change interrupt clear (self-clearing)" "0,1" group.word 0xC228++0x1 line.word 0x0 "RAWLANE0_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR,RX pstate change interrupt clear" newline hexmask.word 0x0 1.--15. 1. "RESERVED_15_1,Reserved for Future use" newline bitfld.word 0x0 0. "RX_PSTATE_IRQ_CLR,RX pstate change interrupt clear (self-clearing)" "0,1" group.word 0xC22C++0x1 line.word 0x0 "RAWLANE0_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR,RX adaptation request interrupt clear" newline hexmask.word 0x0 1.--15. 1. "RESERVED_15_1,Reserved for Future use" newline bitfld.word 0x0 0. "RX_ADAPT_REQ_IRQ_CLR,RX adaptation request interrupt clear (self-clearing)" "0,1" group.word 0xC230++0x1 line.word 0x0 "RAWLANE0_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR,RX adaptation disable interrupt clear" newline hexmask.word 0x0 1.--15. 1. "RESERVED_15_1,Reserved for Future use" newline bitfld.word 0x0 0. "RX_ADAPT_DIS_IRQ_CLR,RX adaptation disable interrupt clear (self-clearing)" "0,1" group.word 0xC234++0x1 line.word 0x0 "RAWLANE0_DIG_IRQ_CTL_IRQ_MASK,Interrupt Mask" newline hexmask.word 0x0 7.--15. 1. "RESERVED_15_7,Reserved for Future use" newline bitfld.word 0x0 6. "LANE_XCVR_MODE_IRQ_MSK,Mask for lane_xcvr_mode interrupt (0 = cannot interrupt)" "cannot interrupt),?" newline bitfld.word 0x0 5. "RX_RESET_IRQ_MSK,Mask for Rx reset interrupt (0 = cannot interrupt)" "cannot interrupt),?" newline bitfld.word 0x0 4. "RX_ADAPT_DIS_IRQ_MSK,Mask for Rx adaptation disable interrupt (0 = cannot interrupt)" "cannot interrupt),?" newline bitfld.word 0x0 3. "RX_ADAPT_REQ_IRQ_MSK,Mask for Rx adaptation request interrupt (0 = cannot interrupt)" "cannot interrupt),?" newline bitfld.word 0x0 2. "RX_PSTATE_IRQ_MSK,Mask for Rx pstate change interrupt (0 = cannot interrupt)" "cannot interrupt),?" newline bitfld.word 0x0 1. "RX_RATE_IRQ_MSK,Mask for Rx rate change interrupt (0 = cannot interrupt)" "cannot interrupt),?" newline bitfld.word 0x0 0. "RX_REQ_IRQ_MSK,Mask for Rx request interrupt (0 = cannot interrupt)" "cannot interrupt),?" rgroup.word 0xC238++0x1 line.word 0x0 "RAWLANE0_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ,Lane transceiver mode interrupt" newline hexmask.word 0x0 1.--15. 1. "RESERVED_15_1,Reserved for Future use" newline bitfld.word 0x0 0. "LANE_XCVR_MODE_IRQ,Lane transceiver mode interrupt" "0,1" group.word 0xC23C++0x1 line.word 0x0 "RAWLANE0_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR,Lane transceiver mode interrupt clear" newline hexmask.word 0x0 1.--15. 1. "RESERVED_15_1,Reserved for Future use" newline bitfld.word 0x0 0. "LANE_XCVR_MODE_IRQ_CLR,Lane transceiver mode interrupt clear (self-clearing)" "0,1" group.word 0xC280++0x1 line.word 0x0 "RAWLANE0_DIG_PMA_XF_LANE_OVRD_IN,Override values for incoming LANE controls" newline hexmask.word 0x0 3.--15. 1. "RESERVED_15_3,Reserved for Future use" newline bitfld.word 0x0 2. "LANE_OVRD_EN,Override enable for signals in this register" "0,1" newline bitfld.word 0x0 1. "LANE_MPLLB_EN_IN,Override value for lane_mpllb_en_in" "0,1" newline bitfld.word 0x0 0. "LANE_MPLLA_EN_IN,Override value for lane_mplla_en_in" "0,1" group.word 0xC284++0x1 line.word 0x0 "RAWLANE0_DIG_PMA_XF_LANE_OVRD_OUT,Override values for outgoing LANE controls" newline hexmask.word 0x0 3.--15. 1. "RESERVED_15_3,Reserved for Future use" newline bitfld.word 0x0 2. "LANE_OVRD_EN,Override enable for signals in this register" "0,1" newline bitfld.word 0x0 1. "LANE_MPLLB_EN_OUT,Override value for lane_mpllb_en_out" "0,1" newline bitfld.word 0x0 0. "LANE_MPLLA_EN_OUT,Override value for lane_mplla_en_out" "0,1" group.word 0xC288++0x1 line.word 0x0 "RAWLANE0_DIG_PMA_XF_SUP_OVRD_IN,Override values for incoming SUP controls from PMA" newline hexmask.word 0x0 3.--15. 1. "RESERVED_15_3,Reserved for Future use" newline bitfld.word 0x0 2. "SUP_STATE_OVRD_EN,Override enable for signals in this register" "0,1" newline bitfld.word 0x0 1. "MPLLB_STATE,Override value for mpllb_state" "0,1" newline bitfld.word 0x0 0. "MPLLA_STATE,Override value for mplla_state" "0,1" rgroup.word 0xC28C++0x1 line.word 0x0 "RAWLANE0_DIG_PMA_XF_SUP_PMA_IN,Current values for incoming MPLL status controls from PMA" newline hexmask.word 0x0 2.--15. 1. "RESERVED_15_2,Reserved for Future use" newline bitfld.word 0x0 1. "MPLLB_STATE,Value from PMA for mpllb_state" "0,1" newline bitfld.word 0x0 0. "MPLLA_STATE,Value from PMA for mplla_state" "0,1" group.word 0xC290++0x1 line.word 0x0 "RAWLANE0_DIG_PMA_XF_TX_OVRD_OUT,Override values for outgoing TX controls to PMA" newline hexmask.word 0x0 4.--15. 1. "RESERVED_15_4,Reserved for Future use" newline bitfld.word 0x0 3. "TX_RESET_OVRD_EN,Override enable for tx_reset" "0,1" newline bitfld.word 0x0 2. "TX_RESET_OVRD_VAL,Override value for tx_reset" "0,1" newline bitfld.word 0x0 1. "TX_REQ_OVRD_EN,Override enable for tx_req" "0,1" newline bitfld.word 0x0 0. "TX_REQ_OVRD_VAL,Override value for tx_req" "0,1" rgroup.word 0xC294++0x1 line.word 0x0 "RAWLANE0_DIG_PMA_XF_TX_PMA_IN,Current values for coming TX status controls from PMA" newline hexmask.word 0x0 1.--15. 1. "RESERVED_15_1,Reserved for Future use" newline bitfld.word 0x0 0. "ACK,Value from PMA for tx_ack" "0,1" group.word 0xC298++0x1 line.word 0x0 "RAWLANE0_DIG_PMA_XF_RX_OVRD_OUT,Override values for outgoing RX controls to PMA" newline hexmask.word 0x0 4.--15. 1. "RESERVED_15_4,Reserved for Future use" newline bitfld.word 0x0 3. "RX_RESET_OVRD_EN,Override enable for rx_reset" "0,1" newline bitfld.word 0x0 2. "RX_RESET_OVRD_VAL,Override value for rx_reset" "0,1" newline bitfld.word 0x0 1. "RX_REQ_OVRD_EN,Override enable for rx_req" "0,1" newline bitfld.word 0x0 0. "RX_REQ_OVRD_VAL,Override value for rx_req" "0,1" rgroup.word 0xC29C++0x1 line.word 0x0 "RAWLANE0_DIG_PMA_XF_RX_PMA_IN,Current values for coming RX status controls from PMA" newline hexmask.word 0x0 1.--15. 1. "RESERVED_15_1,Reserved for Future use" newline bitfld.word 0x0 0. "ACK,Value from PMA for rx_ack" "0,1" group.word 0xC2A0++0x1 line.word 0x0 "RAWLANE0_DIG_PMA_XF_LANE_RTUNE_CTL,Lane Rtune Controls" newline hexmask.word 0x0 1.--15. 1. "RESERVED_15_1,Reserved for Future use" newline bitfld.word 0x0 0. "LANE_RTUNE_REQ,Lane value for rtune_req" "0,1" rgroup.word 0xC2A4++0x1 line.word 0x0 "RAWLANE0_DIG_PMA_XF_SUP_PMA_IN_1,Current values for incoming RTUNE status controls from PMA" newline hexmask.word 0x0 1.--15. 1. "RESERVED_15_1,Reserved for Future use" newline bitfld.word 0x0 0. "RTUNE_ACK,Value from PMA for rtune_ack" "0,1" rgroup.word 0xC2A8++0x1 line.word 0x0 "RAWLANE0_DIG_PMA_XF_SUP_PMA_RX_VALID,Current value of RX valid from PMA" newline hexmask.word 0x0 1.--15. 1. "RESERVED_15_1,Reserved for Future use" newline bitfld.word 0x0 0. "RX_VALID,Value of RX_VALID" "0,1" group.word 0xC300++0x1 line.word 0x0 "RAWLANE0_DIG_TX_CTL_TX_FSM_CTL,TX FSM Control" newline hexmask.word.byte 0x0 10.--15. 1. "RESERVED_15_10,Reserved for Future use" newline bitfld.word 0x0 9. "TX_P0_ALLOW_RXDET,If asserted then rxdet request is allowed in P0" "0,1" newline bitfld.word 0x0 8. "TX_P0S_ALLOW_RXDET,If asserted then rxdet request is allowed in P0S" "0,1" newline bitfld.word 0x0 7. "TX_P1_ALLOW_RXDET,If asserted then rxdet request is allowed in P1" "0,1" newline bitfld.word 0x0 6. "TX_P2_ALLOW_RXDET,If asserted then rxdet request is allowed in P2" "0,1" newline hexmask.word.byte 0x0 0.--5. 1. "TX_WAIT_MPLL_OFF_TIME,Number of ref_range cycles to wait for MPLL to turn off (When entering P2)." group.word 0xC304++0x1 line.word 0x0 "RAWLANE0_DIG_TX_CTL_TX_CLK_CTL,Select clock to act as TX input clock" newline hexmask.word 0x0 5.--15. 1. "RESERVED_15_5,Reserved for Future use" newline hexmask.word.byte 0x0 1.--4. 1. "TX_CLK_SEL,Select clock source for tx_pma_clk 0 - tx_pcs_clk (input clock from pcs) 1 - mplla_word_clk 2 - mplla_dword_clk 3 - mplla_qword_clk 4 - mplla_oword_clk 5 - mplla_div_clk 6 - mpllb_word_clk 7 - mpllb_dword_clk 8 - mpllb_qword_clk 9 -.." newline bitfld.word 0x0 0. "TX_CLK_EN,Enable the tx_clk to pma tx lane TX_CLK_EN must be deasserted when switching TX_CLK_SEL" "0,1" group.word 0xC380++0x1 line.word 0x0 "RAWLANE0_DIG_RX_CTL_RX_FSM_CTL,RX FSM control register" newline hexmask.word 0x0 2.--15. 1. "RESERVED_15_2,Reserved for Future use" newline bitfld.word 0x0 1. "RATE_CHG_IN_P1,When asserted then a rate change in P0/P0s will be sequenced such that the RX is put in P1 the rate change is applied and then the RX is returned to P0/P0s." "0,1" newline bitfld.word 0x0 0. "EN_RX_CTL_FSM,Enable the RX control FSM in the Raw PCS If enabled then when FSM detects a rate change it moves the RX to P1 does the rate change then goes back to P0/P0s. If not enabled then FSM is by-passed." "0,1" group.word 0xC384++0x1 line.word 0x0 "RAWLANE0_DIG_RX_CTL_RX_LOS_MASK_CTL,RX LOS Mask Control" newline hexmask.word.byte 0x0 9.--15. 1. "RESERVED_15_9,Reserved for Future use" newline hexmask.word 0x0 0.--8. 1. "RX_LOS_MASK_CNT,Number of cycles (ref_range_clk) to mask out the rx_los output from the time the los is powered-on. Default set for minimum 10us." group.word 0xC388++0x1 line.word 0x0 "RAWLANE0_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL,RX Data Enable Override Control" newline hexmask.word 0x0 5.--15. 1. "INT_REF_TRCK_CNT,Number of ref_range cycles to wait for integral reference tracking to settle." newline hexmask.word.byte 0x0 0.--4. 1. "RX_DATA_EN_OVRD_CNT,Number of ref_range cycles to override rx_data_en to 1." rgroup.word 0xC38C++0x1 line.word 0x0 "RAWLANE0_DIG_RX_CTL_OFFCAN_CONT_STATUS,RX continuous offset cancellation status" newline hexmask.word 0x0 1.--15. 1. "RESERVED_15_1,Reserved for Future use" newline bitfld.word 0x0 0. "ENABLE,Enable status for rx continous offset cancellation" "0,1" rgroup.word 0xC390++0x1 line.word 0x0 "RAWLANE0_DIG_RX_CTL_ADAPT_CONT_STATUS,RX continuous adaptation status" newline hexmask.word 0x0 1.--15. 1. "RESERVED_15_1,Reserved for Future use" newline bitfld.word 0x0 0. "ENABLE,Enable status for rx continous adaptation" "0,1" group.word 0xC400++0x1 line.word 0x0 "RAWLANE1_DIG_PCS_XF_TX_OVRD_IN,Override values for incoming TX controls from PCS" newline rbitfld.word 0x0 13.--15. "RESERVED_15_13,Reserved for Future use" "0,1,2,3,4,5,6,7" newline bitfld.word 0x0 12. "OVRD_EN,Override enable for all input signals below" "0,1" newline bitfld.word 0x0 11. "MSTR_MPLLB_STATE,Override value for tx_master_mpllb_state" "0,1" newline bitfld.word 0x0 10. "MSTR_MPLLA_STATE,Override value for tx_master_mplla_state" "0,1" newline bitfld.word 0x0 9. "MPLL_EN,Override value for tx_mpll_en" "0,1" newline bitfld.word 0x0 8. "MPLLB_SEL,Override value for tx_mpllb_sel" "0,1" newline bitfld.word 0x0 5.--7. "RATE,Override value for tx_rate" "0,1,2,3,4,5,6,7" newline bitfld.word 0x0 3.--4. "WIDTH,Override value for tx_width" "0,1,2,3" newline bitfld.word 0x0 2. "LPD,Override value for tx_lpd" "0,1" newline bitfld.word 0x0 0.--1. "PSTATE,Override value for tx_pstate" "0,1,2,3" group.word 0xC404++0x1 line.word 0x0 "RAWLANE1_DIG_PCS_XF_TX_OVRD_IN_1,Override values for incoming TX controls from PCS. register #1" newline rbitfld.word 0x0 13.--15. "RESERVED_15_13,Reserved for Future use" "0,1,2,3,4,5,6,7" newline bitfld.word 0x0 12. "IBOOST_LVL_OVRD_EN,Override enable for tx_iboost_lvl[3:0]" "0,1" newline hexmask.word.byte 0x0 8.--11. 1. "IBOOST_LVL_OVRD_VAL,Override value for tx_iboost_lvl[3:0]" newline bitfld.word 0x0 7. "VBOOST_EN_OVRD_EN,Override enable for tx_vboost_en" "0,1" newline bitfld.word 0x0 6. "VBOOST_EN_OVRD_VAL,Override value for tx_vboost_en" "0,1" newline bitfld.word 0x0 5. "DETRX_REQ_OVRD_EN,Override enable for tx_detrx_req" "0,1" newline bitfld.word 0x0 4. "DETRX_REQ_OVRD_VAL,Override value for tx_detrx_req" "0,1" newline bitfld.word 0x0 3. "REQ_OVRD_EN,Override enable for tx_req" "0,1" newline bitfld.word 0x0 2. "REQ_OVRD_VAL,Override value for tx_req" "0,1" newline bitfld.word 0x0 1. "RESET_OVRD_EN,Override enable for tx_reset" "0,1" newline bitfld.word 0x0 0. "RESET_OVRD_VAL,Override value for tx_reset" "0,1" rgroup.word 0xC408++0x1 line.word 0x0 "RAWLANE1_DIG_PCS_XF_TX_PCS_IN,Current values for incoming TX controls from PCS" newline bitfld.word 0x0 15. "RESERVED_15_15,Reserved for Future use" "0,1" newline bitfld.word 0x0 14. "DETRX_REQ,Value from PCS for tx_detrx_req" "0,1" newline bitfld.word 0x0 13. "MSTR_MPLLB_STATE,Value from PCS for tx_master_mpllb_state" "0,1" newline bitfld.word 0x0 12. "MSTR_MPLLA_STATE,Value from PCS for tx_master_mplla_state" "0,1" newline bitfld.word 0x0 11. "MPLL_EN,Value from PCS for tx_mpll_en" "0,1" newline bitfld.word 0x0 10. "MPLLB_SEL,Value from PCS for tx_mpllb_sel" "0,1" newline bitfld.word 0x0 7.--9. "RATE,Value from PCS for tx_rate" "0,1,2,3,4,5,6,7" newline bitfld.word 0x0 5.--6. "WIDTH,Value from PCS for tx_width" "0,1,2,3" newline bitfld.word 0x0 4. "LPD,Value from PCS for tx_lpd" "0,1" newline bitfld.word 0x0 2.--3. "PSTATE,Value from PCS for tx_pstate" "0,1,2,3" newline bitfld.word 0x0 1. "REQ,Value from PCS for tx_req" "0,1" newline bitfld.word 0x0 0. "RESET,Value from PCS for tx_reset" "0,1" group.word 0xC40C++0x1 line.word 0x0 "RAWLANE1_DIG_PCS_XF_TX_OVRD_OUT,Override values for outgoing TX controls to PCS" newline hexmask.word 0x0 3.--15. 1. "RESERVED_15_3,Reserved for Future use" newline bitfld.word 0x0 2. "EN_CTL,Enable override values for all control outputs of this register" "0,1" newline bitfld.word 0x0 1. "DETRX_RESULT,Override value for tx_detrx_result" "0,1" newline bitfld.word 0x0 0. "ACK,Override value for tx_ack" "0,1" rgroup.word 0xC410++0x1 line.word 0x0 "RAWLANE1_DIG_PCS_XF_TX_PCS_OUT,Current values for outgoing TX status controls from Raw PCS" newline hexmask.word 0x0 1.--15. 1. "RESERVED_15_1,Reserved for Future use" newline bitfld.word 0x0 0. "ACK,Value from Raw PCS for tx_ack" "0,1" group.word 0xC414++0x1 line.word 0x0 "RAWLANE1_DIG_PCS_XF_RX_OVRD_IN,Override values for incoming RX controls from PCS" newline hexmask.word.byte 0x0 10.--15. 1. "RESERVED_15_10,Reserved for Future use" newline bitfld.word 0x0 9. "ADAPT_DFE_EN,Override value for rx_adapt_dfe_en" "0,1" newline bitfld.word 0x0 8. "ADAPT_AFE_EN,Override value for rx_adapt_afe_en" "0,1" newline bitfld.word 0x0 7. "OVRD_EN,Enable override values for all fields in this register" "0,1" newline bitfld.word 0x0 6. "LPD,Override value for rx_lpd" "0,1" newline bitfld.word 0x0 4.--5. "PSTATE,Override value for rx_pstate" "0,1,2,3" newline bitfld.word 0x0 2.--3. "WIDTH,Override value for rx_width" "0,1,2,3" newline bitfld.word 0x0 0.--1. "RATE,Override value for rx_rate" "0,1,2,3" group.word 0xC418++0x1 line.word 0x0 "RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_1,Override values for incoming RX controls from PCS. register #1" newline hexmask.word 0x0 4.--15. 1. "RESERVED_15_4,Reserved for Future use" newline bitfld.word 0x0 3. "REQ_OVRD_EN,Override enable for rx_req" "0,1" newline bitfld.word 0x0 2. "REQ_OVRD_VAL,Override value for rx_req" "0,1" newline bitfld.word 0x0 1. "RESET_OVRD_EN,Override enable for rx_reset" "0,1" newline bitfld.word 0x0 0. "RESET_OVRD_VAL,Override value for rx_reset" "0,1" group.word 0xC41C++0x1 line.word 0x0 "RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_2,Override values for incoming RX controls from PCS. register #2" newline bitfld.word 0x0 15. "VCO_LOWFREQ_VAL_OVRD_EN,Enable override for rx_cdr_vco_lowfreq" "0,1" newline bitfld.word 0x0 14. "VCO_LOWFREQ_VAL_OVRD,Override value for rx_cdr_vco_lowfreq" "0,1" newline bitfld.word 0x0 13. "VCO_LD_VAL_OVRD_EN,Enable override for rx_vco_ld_val" "0,1" newline hexmask.word 0x0 0.--12. 1. "VCO_LD_VAL_OVRD,Override value for rx_vco_ld_val" group.word 0xC420++0x1 line.word 0x0 "RAWLANE1_DIG_PCS_XF_RX_OVRD_IN_3,Override values for incoming RX controls from PCS. register #3" newline bitfld.word 0x0 15. "CONT_OVRD_EN,Enable override values for rx_adapt_cont and rx_offcan_cont" "0,1" newline bitfld.word 0x0 14. "OFFCAN_CONT,Override value for rx_offcan_cont" "0,1" newline bitfld.word 0x0 13. "ADAPT_CONT,Override value for rx_adapt_cont" "0,1" newline bitfld.word 0x0 12. "ADAPT_REQ_OVRD_EN,Enable override values for rx_adapt_req" "0,1" newline bitfld.word 0x0 11. "ADAPT_REQ,Override value for rx_adapt_req" "0,1" newline bitfld.word 0x0 10. "REF_LD_VAL_OVRD_EN,Enable override for rx_ref_ld_val" "0,1" newline hexmask.word.byte 0x0 4.--9. 1. "REF_LD_VAL_OVRD,Override value for rx_ref_ld_val" newline bitfld.word 0x0 3. "RX_LOS_THRSHLD_OVRD_EN,Enable override for rx_los_threshold" "0,1" newline bitfld.word 0x0 0.--2. "RX_LOS_THRSHLD_OVRD_VAL,Override value for rx_los_threshold" "0,1,2,3,4,5,6,7" rgroup.word 0xC424++0x1 line.word 0x0 "RAWLANE1_DIG_PCS_XF_RX_PCS_IN,Current values for incoming RX controls from PCS" newline bitfld.word 0x0 15. "RESERVED_15_15,Reserved for Future use" "0,1" newline bitfld.word 0x0 14. "RESET,Value from PCS for rx_reset" "0,1" newline bitfld.word 0x0 13. "OFFCAN_CONT,Value from PCS for rx_offcan_cont" "0,1" newline bitfld.word 0x0 12. "ADAPT_CONT,Value from PCS for rx_adapt_cont" "0,1" newline bitfld.word 0x0 11. "ADAPT_REQ,Value from PCS for rx_adapt_req" "0,1" newline bitfld.word 0x0 10. "ADAPT_DFE_EN,Value from PCS for rx_adapt_dfe_en" "0,1" newline bitfld.word 0x0 9. "ADAPT_AFE_EN,Value from PCS for rx_adapt_afe_en" "0,1" newline bitfld.word 0x0 8. "CDR_VCO_LOWFREQ,Value from PCS for rx_cdr_vco_lowfreq" "0,1" newline bitfld.word 0x0 7. "LPD,Value from PCS for rx_lpd" "0,1" newline bitfld.word 0x0 5.--6. "PSTATE,Value from PCS for rx_pstate" "0,1,2,3" newline bitfld.word 0x0 3.--4. "WIDTH,Value from PCS for rx_width" "0,1,2,3" newline bitfld.word 0x0 1.--2. "RATE,Value from PCS for rx_rate" "0,1,2,3" newline bitfld.word 0x0 0. "REQ,Value from PCS for rx_req" "0,1" rgroup.word 0xC428++0x1 line.word 0x0 "RAWLANE1_DIG_PCS_XF_RX_PCS_IN_1,Current values for incoming RX controls from PCS. register #1" newline hexmask.word 0x0 6.--15. 1. "RESERVED_15_6,Reserved for Future use" newline hexmask.word.byte 0x0 0.--5. 1. "REF_LD_VAL,Value from PCS for rx_ref_ld_val" rgroup.word 0xC42C++0x1 line.word 0x0 "RAWLANE1_DIG_PCS_XF_RX_PCS_IN_2,Current values for incoming RX controls from PCS. register #2" newline bitfld.word 0x0 13.--15. "RESERVED_15_13,Reserved for Future use" "0,1,2,3,4,5,6,7" newline hexmask.word 0x0 0.--12. 1. "VCO_LD_VAL,Value from PCS for rx_vco_ld_val" rgroup.word 0xC430++0x1 line.word 0x0 "RAWLANE1_DIG_PCS_XF_RX_PCS_IN_3,Current values for incoming RX controls from PCS. register #3" newline hexmask.word.byte 0x0 11.--15. 1. "EQ_CTLE_BOOST,Value from ASIC for rx_eq_ctle_boost" newline hexmask.word.byte 0x0 7.--10. 1. "EQ_VGA2_GAIN,Value from ASIC for rx_eq_vga2_gain" newline hexmask.word.byte 0x0 3.--6. 1. "EQ_VGA1_GAIN,Value from ASIC for rx_eq_vga1_gain" newline bitfld.word 0x0 0.--2. "EQ_ATT_LVL,Value from ASIC for rx_eq_att_lvl" "0,1,2,3,4,5,6,7" rgroup.word 0xC434++0x1 line.word 0x0 "RAWLANE1_DIG_PCS_XF_RX_PCS_IN_4,Current values for incoming RX controls from PCS. register #4" newline hexmask.word.byte 0x0 11.--15. 1. "RESERVED_15_11,Reserved for Future use" newline hexmask.word.byte 0x0 3.--10. 1. "EQ_DFE_TAP1,Value from ASIC for rx_eq_dfe_tap1" newline bitfld.word 0x0 0.--2. "EQ_CTLE_POLE,Value from ASIC for rx_eq_ctle_pole" "0,1,2,3,4,5,6,7" group.word 0xC438++0x1 line.word 0x0 "RAWLANE1_DIG_PCS_XF_RX_OVRD_OUT,Override values for outgoing RX controls to PCS" newline hexmask.word 0x0 2.--15. 1. "RESERVED_15_2,Reserved for Future use" newline bitfld.word 0x0 1. "EN_CTL,Enable override values for all control outputs of this register" "0,1" newline bitfld.word 0x0 0. "ACK,Override value for rx_ack" "0,1" rgroup.word 0xC43C++0x1 line.word 0x0 "RAWLANE1_DIG_PCS_XF_RX_PCS_OUT,Current values for outgoing RX status controls from Raw PCS" newline hexmask.word 0x0 1.--15. 1. "RESERVED_15_1,Reserved for Future use" newline bitfld.word 0x0 0. "ACK,Value from Raw PCS for rx_ack" "0,1" group.word 0xC440++0x1 line.word 0x0 "RAWLANE1_DIG_PCS_XF_RX_ADAPT_ACK,RX Adaptation Acknowledge" newline hexmask.word 0x0 1.--15. 1. "RESERVED_15_1,Reserved for Future use" newline bitfld.word 0x0 0. "RX_ADAPT_ACK,RX Adaptation Acknowledge" "0,1" group.word 0xC444++0x1 line.word 0x0 "RAWLANE1_DIG_PCS_XF_RX_ADAPT_FOM,RX Adaptation Figure of Merit" newline hexmask.word.byte 0x0 8.--15. 1. "RESERVED_15_8,Reserved for Future use" newline hexmask.word.byte 0x0 0.--7. 1. "RX_ADAPT_FOM,RX Adaptation Figure of Merit" group.word 0xC448++0x1 line.word 0x0 "RAWLANE1_DIG_PCS_XF_RX_TXPRE_DIR,RX calculated direction for TX-pre" newline hexmask.word 0x0 2.--15. 1. "RESERVED_15_2,Reserved for Future use" newline bitfld.word 0x0 0.--1. "RX_TXPRE_DIR,RX calculated direction for TX-pre 00 - No change 01 - Increment 10 - Decrement 11 - Reserved" "No change,Increment,?,?" group.word 0xC44C++0x1 line.word 0x0 "RAWLANE1_DIG_PCS_XF_RX_TXMAIN_DIR,RX calculated direction for TX-Main" newline hexmask.word 0x0 2.--15. 1. "RESERVED_15_2,Reserved for Future use" newline bitfld.word 0x0 0.--1. "RX_TXMAIN_DIR,RX calculated direction for TX-Main 00 - No change 01 - Increment 10 - Decrement 11 - Reserved" "No change,Increment,?,?" group.word 0xC450++0x1 line.word 0x0 "RAWLANE1_DIG_PCS_XF_RX_TXPOST_DIR,RX calculated direction for TX-Post" newline hexmask.word 0x0 2.--15. 1. "RESERVED_15_2,Reserved for Future use" newline bitfld.word 0x0 0.--1. "RX_TXPOST_DIR,RX calculated direction for TX-Post 00 - No change 01 - Increment 10 - Decrement 11 - Reserved" "No change,Increment,?,?" rgroup.word 0xC454++0x1 line.word 0x0 "RAWLANE1_DIG_PCS_XF_LANE_NUMBER,Current lane number" newline hexmask.word 0x0 4.--15. 1. "RESERVED_15_4,Reserved for Future use" newline hexmask.word.byte 0x0 0.--3. 1. "LANE_NUMBER,Current lane number" group.word 0xC458++0x1 line.word 0x0 "RAWLANE1_DIG_PCS_XF_LANE_XCVR_MODE_OVRD_IN,Override incoming values for lane_xcvr_mode" newline hexmask.word 0x0 3.--15. 1. "RESERVED_15_3,Reserved for Future use" newline bitfld.word 0x0 2. "LANE_XCVR_MODE_OVRD_EN,Enable override value for lane_xcvr_mode" "0,1" newline bitfld.word 0x0 0.--1. "LANE_XCVR_MODE_OVRD_VAL,Override value for lane_xcvr_mode" "0,1,2,3" rgroup.word 0xC45C++0x1 line.word 0x0 "RAWLANE1_DIG_PCS_XF_LANE_XCVR_MODE_IN,Lane transceiver mode status" newline hexmask.word 0x0 2.--15. 1. "RESERVED_15_2,Reserved for Future use" newline bitfld.word 0x0 0.--1. "LANE_XCVR_MODE,Lane transceiver mode Determines whether this lane is being used as Tx Rx or Tx/Rx 00 - Reserved 01 - Lane is used for Tx only 10 - Lane is used for Rx only 11 - Lane is used for Tx/Rx" "Reserved,Lane is used for Tx only,?,?" group.word 0xC460++0x1 line.word 0x0 "RAWLANE1_DIG_PCS_XF_ATE_OVRD_IN,ATE Override input to control top-level inputs" newline hexmask.word.byte 0x0 12.--15. 1. "RESERVED_15_12,Reserved for Future use" newline bitfld.word 0x0 11. "RX_ADAPT_DFE_EN_OVRD_EN,Enable override value for rx_adapt_dfe_en input" "0,1" newline bitfld.word 0x0 10. "RX_ADAPT_DFE_EN_OVRD_VAL,Override value for rx_adapt_dfe_en input" "0,1" newline bitfld.word 0x0 9. "RX_ADAPT_AFE_EN_OVRD_EN,Enable override value for rx_adapt_afe_en input" "0,1" newline bitfld.word 0x0 8. "RX_ADAPT_AFE_EN_OVRD_VAL,Override value for rx_adapt_afe_en input" "0,1" newline bitfld.word 0x0 7. "TX_REQ_ATE_OVRD_EN,Enable override value for tx_req input" "0,1" newline bitfld.word 0x0 6. "TX_REQ_ATE_OVRD_VAL,Override value for top-level tx_req input" "0,1" newline bitfld.word 0x0 5. "RX_REQ_ATE_OVRD_EN,Enable override value for rx_req input" "0,1" newline bitfld.word 0x0 4. "RX_REQ_ATE_OVRD_VAL,Override value for top-level rx_req input" "0,1" newline bitfld.word 0x0 3. "TX_RESET_ATE_OVRD_EN,Enable override value for tx_reset input" "0,1" newline bitfld.word 0x0 2. "TX_RESET_ATE_OVRD_VAL,Override value for top-level tx_reset input" "0,1" newline bitfld.word 0x0 1. "RX_RESET_ATE_OVRD_EN,Enable override value for rx_reset input" "0,1" newline bitfld.word 0x0 0. "RX_RESET_ATE_OVRD_VAL,Override value for top-level rx_reset input" "0,1" group.word 0xC464++0x1 line.word 0x0 "RAWLANE1_DIG_PCS_XF_RX_EQ_DELTA_IQ_OVRD_IN,Override incoming values for rx_eq_delta_iq" newline hexmask.word 0x0 5.--15. 1. "RESERVED_15_5,Reserved for Future use" newline bitfld.word 0x0 4. "RX_EQ_DELTA_IQ_OVRD_EN,Enable override value for rx_eq_delta_iq" "0,1" newline hexmask.word.byte 0x0 0.--3. 1. "RX_EQ_DELTA_IQ_OVRD_VAL,Override value for rx_eq_delta_iq" group.word 0xC468++0x1 line.word 0x0 "RAWLANE1_DIG_PCS_XF_TXRX_TERM_CTRL_OVRD_IN,Override incoming values for tx/rx_term_ctrl" newline hexmask.word.byte 0x0 8.--15. 1. "RESERVED_15_8,Reserved for Future use" newline bitfld.word 0x0 7. "TX_TERM_CTRL_OVRD_EN,Enable override value for tx_term_ctrl" "0,1" newline bitfld.word 0x0 4.--6. "TX_TERM_CTRL_OVRD_VAL,Override value for tx_term_ctrl" "0,1,2,3,4,5,6,7" newline bitfld.word 0x0 3. "RX_TERM_CTRL_OVRD_EN,Enable override value for rx_term_ctrl" "0,1" newline bitfld.word 0x0 0.--2. "RX_TERM_CTRL_OVRD_VAL,Override value for rx_term_ctrl" "0,1,2,3,4,5,6,7" rgroup.word 0xC46C++0x1 line.word 0x0 "RAWLANE1_DIG_PCS_XF_TXRX_TERM_CTRL_IN,tx/rx_term_ctrl status" newline hexmask.word 0x0 6.--15. 1. "RESERVED_15_6,Reserved for Future use" newline bitfld.word 0x0 3.--5. "TX_TERM_CTRL,tx_term_ctrl value" "0,1,2,3,4,5,6,7" newline bitfld.word 0x0 0.--2. "RX_TERM_CTRL,tx_term_ctrl value" "0,1,2,3,4,5,6,7" group.word 0xC470++0x1 line.word 0x0 "RAWLANE1_DIG_PCS_XF_RX_OVRD_OUT_1,Override values for outgoing RX controls to PCS. register #1" newline hexmask.word 0x0 1.--15. 1. "RESERVED_15_1,Reserved for Future use" newline bitfld.word 0x0 0. "RX_CLK_EN,Enable the outging rx_clk" "0,1" group.word 0xC474++0x1 line.word 0x0 "RAWLANE1_DIG_PCS_XF_RX_EQ_OVRD_IN_1,Override values for incoming RX EQ controls from PCS. register #1" newline hexmask.word.byte 0x0 8.--15. 1. "RESERVED_15_8,Reserved for Future use" newline bitfld.word 0x0 7. "RX_EQ_OVRD_EN,Enable override values for all RX EQ settings" "0,1" newline bitfld.word 0x0 4.--6. "RX_EQ_ATT_LVL_OVRD_VAL,Override value for rx_eq_att_lvl[2:0]" "0,1,2,3,4,5,6,7" newline hexmask.word.byte 0x0 0.--3. 1. "RX_EQ_AFE_GAIN_OVRD_VAL,Override value for rx_eq_afe_gain[3:0]" group.word 0xC478++0x1 line.word 0x0 "RAWLANE1_DIG_PCS_XF_RX_EQ_OVRD_IN_2,Override values for incoming RX EQ controls from PCS. register #2" newline rbitfld.word 0x0 13.--15. "RESERVED_15_13,Reserved for Future use" "0,1,2,3,4,5,6,7" newline hexmask.word.byte 0x0 8.--12. 1. "RX_EQ_CTLE_BOOST_OVRD_VAL,Override value for rx_eq_ctle_boost[4:0]" newline hexmask.word.byte 0x0 0.--7. 1. "RX_EQ_DFE_TAP1_OVRD_VAL,Override value for rx_eq_dfe_tap1[7:0]" group.word 0xC47C++0x1 line.word 0x0 "RAWLANE1_DIG_PCS_XF_RX_OVRD_OUT_2,Override value for RX VALID/DATA_EN/DATA_EN_ATE signal from PCS" newline hexmask.word.byte 0x0 11.--15. 1. "RESERVED_15_11,Reserved for Future use" newline bitfld.word 0x0 10. "RX_RATE_ATE_OVRD_EN,Override enable for rx_rate_ate" "0,1" newline bitfld.word 0x0 8.--9. "RX_RATE_ATE_OVRD_VAL,Override value for rx_rate_ate" "0,1,2,3" newline bitfld.word 0x0 7. "RX_CDR_TRACK_EN_ATE_OVRD_EN,Override enable for rx_cdr_track_en_ate" "0,1" newline bitfld.word 0x0 6. "RX_CDR_TRACK_EN_ATE_OVRD_VAL,Override value for rx_cdr_track_en_ate" "0,1" newline bitfld.word 0x0 5. "RX_DATA_EN_ATE_OVRD_EN,Override enable for rx_data_en_ate" "0,1" newline bitfld.word 0x0 4. "RX_DATA_EN_ATE_OVRD_VAL,Override value for rx_data_en_ate" "0,1" newline bitfld.word 0x0 3. "RX_DATA_EN_OVRD_EN,Override enable for rx_data_en" "0,1" newline bitfld.word 0x0 2. "RX_DATA_EN_OVRD_VAL,Override value for rx_data_en" "0,1" newline bitfld.word 0x0 1. "RX_VALID_OVRD_EN,Override enable for rx_valid" "0,1" newline bitfld.word 0x0 0. "RX_VALID_OVRD_VAL,Override value for rx_valid" "0,1" group.word 0xC480++0x1 line.word 0x0 "RAWLANE1_DIG_FSM_FSM_OVRD_CTL,FSM override control register" newline rbitfld.word 0x0 15. "RESERVED_15_15,Reserved for Future use" "0,1" newline bitfld.word 0x0 14. "FSM_OVRD_EN,Enable overriding the FSM execution of commands Must be asserted to use FSM_CMD_START and FSM_JMP_EN features" "0,1" newline bitfld.word 0x0 13. "FSM_CMD_START,Start executing the new command This is a self-clearing bit" "0,1" newline bitfld.word 0x0 12. "FSM_JMP_EN,Force the FSM to jump to FSM_JMP_ADDR in the program memory Is applied when FSM_CMD_START is pulsed." "0,1" newline hexmask.word 0x0 0.--11. 1. "FSM_JMP_ADDR,The jump address used when FSM_JUMP_EN=1 The address is encoded as follows: [11:8] mem_lane [7:5] bank [4:0] register" rgroup.word 0xC484++0x1 line.word 0x0 "RAWLANE1_DIG_FSM_MEM_ADDR_MON,Memory Address Monitor" newline hexmask.word 0x0 0.--15. 1. "MEM_ADDR,Current value of memory address used in Lane FSM" rgroup.word 0xC488++0x1 line.word 0x0 "RAWLANE1_DIG_FSM_STATUS_MON,FSM Status Monitor" newline hexmask.word.byte 0x0 11.--15. 1. "RESERVED_15_11,Reserved for Future use" newline bitfld.word 0x0 10. "RDMSK_DISABLED,Check if read mask is currently disabled (i.e. mask is all ones)" "0,1" newline bitfld.word 0x0 9. "WRMSK_DISABLED,Check if write mask is currently disabled (i.e. mask is all ones)" "0,1" newline bitfld.word 0x0 8. "WAIT_CNT_EQ0,Check if wait counter currently equals zero" "0,1" newline bitfld.word 0x0 7. "ALU_RES_EQ0,Check if ALU result register currently equals zero" "0,1" newline bitfld.word 0x0 6. "ALU_OVFLW,Current value of ALU overflow bit" "0,1" newline bitfld.word 0x0 5. "CMD_RDY,New command is ready for execution (applicable when FSM_OVRD_EN=1)" "0,1" newline hexmask.word.byte 0x0 0.--4. 1. "STATE,Current state of Lane FSM" rgroup.word 0xC48C++0x1 line.word 0x0 "RAWLANE1_DIG_FSM_FAST_RX_STARTUP_CAL,Status of Fast RX Start Up Calibration" newline hexmask.word 0x0 1.--15. 1. "RESERVED_15_1,Reserved for Future use" newline bitfld.word 0x0 0. "FAST_RX_STARTUP_CAL,Status of fast RX start-up calibration" "0,1" rgroup.word 0xC490++0x1 line.word 0x0 "RAWLANE1_DIG_FSM_FAST_RX_ADAPT,Status of Fast RX Adaptation" newline hexmask.word 0x0 1.--15. 1. "RESERVED_15_1,Reserved for Future use" newline bitfld.word 0x0 0. "FAST_RX_ADAPT,Status of fast RX adaptation" "0,1" rgroup.word 0xC494++0x1 line.word 0x0 "RAWLANE1_DIG_FSM_FAST_RX_AFE_CAL,Status of Fast RX AFE Calibration" newline hexmask.word 0x0 1.--15. 1. "RESERVED_15_1,Reserved for Future use" newline bitfld.word 0x0 0. "FAST_RX_AFE_CAL,Status of fast RX AFE DAC start-up calibration" "0,1" rgroup.word 0xC498++0x1 line.word 0x0 "RAWLANE1_DIG_FSM_FAST_RX_DFE_CAL,Status of Fast RX DFE Calibration" newline hexmask.word 0x0 1.--15. 1. "RESERVED_15_1,Reserved for Future use" newline bitfld.word 0x0 0. "FAST_RX_DFE_CAL,Status of fast RX DFE slicer start-up calibration" "0,1" rgroup.word 0xC49C++0x1 line.word 0x0 "RAWLANE1_DIG_FSM_FAST_RX_DFE_RE_ADAPT,Enables fast RX DFE re -adaptation" newline hexmask.word 0x0 1.--15. 1. "RESERVED_15_1,Reserved for Future use" newline bitfld.word 0x0 0. "FAST_RX_DFE_RE_ADAPT,Enables fast RX DFE re -adaptation" "0,1" rgroup.word 0xC4A0++0x1 line.word 0x0 "RAWLANE1_DIG_FSM_FAST_RX_REFLVL_CAL,Status of Fast RX Reference Level Calibration" newline hexmask.word 0x0 1.--15. 1. "RESERVED_15_1,Reserved for Future use" newline bitfld.word 0x0 0. "FAST_RX_REFLVL_CAL,Status of fast RX reference level (100mv 125mv 150mv) start-up calibration" "0,1" rgroup.word 0xC4A4++0x1 line.word 0x0 "RAWLANE1_DIG_FSM_FAST_RX_IQ_CAL,Status of Fast RX IQ Calibration" newline hexmask.word 0x0 1.--15. 1. "RESERVED_15_1,Reserved for Future use" newline bitfld.word 0x0 0. "FAST_RX_IQ_CAL,Status of fast RX IQ start-up calibration" "0,1" rgroup.word 0xC4A8++0x1 line.word 0x0 "RAWLANE1_DIG_FSM_FAST_RX_AFE_ADAPT,Status of Fast RX AFE Adaptation" newline hexmask.word 0x0 1.--15. 1. "RESERVED_15_1,Reserved for Future use" newline bitfld.word 0x0 0. "FAST_RX_AFE_ADAPT,Status of fast RX AFE DAC start-up adaptation" "0,1" rgroup.word 0xC4AC++0x1 line.word 0x0 "RAWLANE1_DIG_FSM_FAST_RX_DFE_ADAPT,Status of Fast RX DFE Adaptation" newline hexmask.word 0x0 1.--15. 1. "RESERVED_15_1,Reserved for Future use" newline bitfld.word 0x0 0. "FAST_RX_DFE_ADAPT,Status of fast RX DFE DAC start-up adaptation" "0,1" rgroup.word 0xC4B0++0x1 line.word 0x0 "RAWLANE1_DIG_FSM_FAST_SUP,Status of Fast Support block" newline hexmask.word 0x0 1.--15. 1. "RESERVED_15_1,Reserved for Future use" newline bitfld.word 0x0 0. "FAST_SUP,Status of fast Support block (MPLL and Rtune)" "0,1" rgroup.word 0xC4B4++0x1 line.word 0x0 "RAWLANE1_DIG_FSM_FAST_TX_CMN_MODE,Status of Fast TX Common-mode Charge-up" newline hexmask.word 0x0 1.--15. 1. "RESERVED_15_1,Reserved for Future use" newline bitfld.word 0x0 0. "FAST_TX_CMN_MODE,Status of fast TX Common-mode Charge-up" "0,1" rgroup.word 0xC4B8++0x1 line.word 0x0 "RAWLANE1_DIG_FSM_FAST_TX_RXDET,Status of Fast TX detect RX" newline hexmask.word 0x0 1.--15. 1. "RESERVED_15_1,Reserved for Future use" newline bitfld.word 0x0 0. "FAST_TX_RXDET,Status of fast TX detect RX" "0,1" rgroup.word 0xC4BC++0x1 line.word 0x0 "RAWLANE1_DIG_FSM_FAST_RX_PWRUP,Status of Fast RX Power-up" newline hexmask.word 0x0 1.--15. 1. "RESERVED_15_1,Reserved for Future use" newline bitfld.word 0x0 0. "FAST_RX_PWRUP,Status of fast RX Power-up (LOS VREG/AFE and DCC)" "0,1" rgroup.word 0xC4C0++0x1 line.word 0x0 "RAWLANE1_DIG_FSM_FAST_RX_VCO_WAIT,Status of Fast RX VCO Wait Times" newline hexmask.word 0x0 1.--15. 1. "RESERVED_15_1,Reserved for Future use" newline bitfld.word 0x0 0. "FAST_RX_VCO_WAIT,Status of fast RX VCO wait times" "0,1" rgroup.word 0xC4C4++0x1 line.word 0x0 "RAWLANE1_DIG_FSM_FAST_RX_VCO_CAL,Status of Fast RX VCO Calibration" newline hexmask.word 0x0 1.--15. 1. "RESERVED_15_1,Reserved for Future use" newline bitfld.word 0x0 0. "FAST_RX_VCO_CAL,Status of fast RX VCO Calibration" "0,1" rgroup.word 0xC4C8++0x1 line.word 0x0 "RAWLANE1_DIG_FSM_CMNCAL_MPLL_STATUS,Status of MPLL common calibration initiation" newline hexmask.word 0x0 2.--15. 1. "RESERVED_15_2,Reserved for Future use" newline bitfld.word 0x0 1. "CMNCAL_MPLL_DONE,Indicates whether MPLL common calibration has been completed by any lane or not." "0,1" newline bitfld.word 0x0 0. "CMNCAL_MPLL_INIT,Indicates whether MPLL common calibration has been started by any lane or not. ---------------------------------------------------------------------" "0,1" rgroup.word 0xC4CC++0x1 line.word 0x0 "RAWLANE1_DIG_FSM_FAST_RX_CONT_CAL_ADAPT,Status of Fast RX Continuous Calibration/Adaptation" newline hexmask.word 0x0 1.--15. 1. "RESERVED_15_1,Reserved for Future use" newline bitfld.word 0x0 0. "FAST_RX_CONT_CAL_ADAPT,Status of fast RX continuous calibration/adaptation" "0,1" rgroup.word 0xC4D0++0x1 line.word 0x0 "RAWLANE1_DIG_FSM_FAST_RX_CONT_ADAPT,Status of Fast RX Continuous Adaptation" newline hexmask.word 0x0 1.--15. 1. "RESERVED_15_1,Reserved for Future use" newline bitfld.word 0x0 0. "FAST_RX_CONT_ADAPT,Status of fast RX continuous adaptation" "0,1" rgroup.word 0xC4D4++0x1 line.word 0x0 "RAWLANE1_DIG_FSM_FAST_RX_CONT_DATA_CAL,Status of Fast RX Continuous Data Calibration" newline hexmask.word 0x0 1.--15. 1. "RESERVED_15_1,Reserved for Future use" newline bitfld.word 0x0 0. "FAST_RX_CONT_DATA_CAL,Status of fast RX continuous data calibration" "0,1" rgroup.word 0xC4D8++0x1 line.word 0x0 "RAWLANE1_DIG_FSM_FAST_RX_CONT_PHASE_CAL,Status of Fast RX Continuous Phase Calibration" newline hexmask.word 0x0 1.--15. 1. "RESERVED_15_1,Reserved for Future use" newline bitfld.word 0x0 0. "FAST_RX_CONT_PHASE_CAL,Status of fast RX continuous phase calibration" "0,1" rgroup.word 0xC4DC++0x1 line.word 0x0 "RAWLANE1_DIG_FSM_FAST_RX_CONT_AFE_CAL,Status of Fast RX Continuous AFE Calibration" newline hexmask.word 0x0 1.--15. 1. "RESERVED_15_1,Reserved for Future use" newline bitfld.word 0x0 0. "FAST_RX_CONT_AFE_CAL,Status of fast RX continuous AFE calibration" "0,1" rgroup.word 0xC4E0++0x1 line.word 0x0 "RAWLANE1_DIG_FSM_FAST_RX_IQ_ADAPT,Status of Fast RX IQ_ADAPT" newline hexmask.word 0x0 1.--15. 1. "RESERVED_15_1,Reserved for Future use" newline bitfld.word 0x0 0. "FAST_RX_IQ_ADAPT,Status of Fast RX IQ_ADAPT" "0,1" rgroup.word 0xC4E4++0x1 line.word 0x0 "RAWLANE1_DIG_FSM_RX_IQ_DELTA_ADD,Status of RX Delta addition" newline hexmask.word 0x0 1.--15. 1. "RESERVED_15_1,Reserved for Future use" newline bitfld.word 0x0 0. "RX_IQ_DELTA_ADD,Reserved" "0,1" rgroup.word 0xC4E8++0x1 line.word 0x0 "RAWLANE1_DIG_FSM_FAST_RX_ATT_ADAPT,Enables fast RX ATT adaptation" newline hexmask.word 0x0 1.--15. 1. "RESERVED_15_1,Reserved for Future use" newline bitfld.word 0x0 0. "FAST_RX_ATT_ADAPT,Enables fast RX ATT adaptation" "0,1" rgroup.word 0xC4EC++0x1 line.word 0x0 "RAWLANE1_DIG_FSM_FAST_RX_CTLE_ADAPT,Enables fast RX CTLE adaptation" newline hexmask.word 0x0 1.--15. 1. "RESERVED_15_1,Reserved for Future use" newline bitfld.word 0x0 0. "FAST_RX_CTLE_ADAPT,Enables fast RX CTLE adaptation" "0,1" group.word 0xC4F0++0x1 line.word 0x0 "RAWLANE1_DIG_FSM_CR_REG_OP_XTND_EN,CR interface timing extension enable" newline hexmask.word 0x0 1.--15. 1. "RESERVED_15_1,Reserved for Future use" newline bitfld.word 0x0 0. "CR_REG_OP_XTND_EN,CR interface timing extension enable 1'b0 - No Timing extension 1'b1 - Timing extension" "No Timing extension,Timing extension" group.word 0xC4F4++0x1 line.word 0x0 "RAWLANE1_DIG_FSM_TX_EQ_UPDATE_FLAG,TX Eq update flag" newline hexmask.word 0x0 1.--15. 1. "RESERVED_15_1,Reserved for Future use" newline bitfld.word 0x0 0. "TX_EQ_UPDATE_FLAG,Tx Eq update flag 1'b0 - Update tx eq post 1'b1 - Update tx eq pre" "Update tx eq post,Update tx eq pre" rgroup.word 0xC4F8++0x1 line.word 0x0 "RAWLANE1_DIG_FSM_CMNCAL_RCAL_STATUS,Status of RTUNE common calibration initiation" newline hexmask.word 0x0 2.--15. 1. "RESERVED_15_2,Reserved for Future use" newline bitfld.word 0x0 1. "CMNCAL_RCAL_DONE,Indicates whether RTUNE common calibration has been completed by any lane or not." "0,1" newline bitfld.word 0x0 0. "CMNCAL_RCAL_INIT,Indicates whether RTUNE common calibration has been started by any lane or not. ---------------------------------------------------------------------" "0,1" rgroup.word 0xC4FC++0x1 line.word 0x0 "RAWLANE1_DIG_FSM_RX_IQ_PHASE_OFFSET,Offset value for IQ Phase Calculation" newline hexmask.word 0x0 4.--15. 1. "RESERVED_15_4,Reserved for Future use" newline hexmask.word.byte 0x0 0.--3. 1. "RX_IQ_PHASE_OFFSET,Offset value for IQ Phase Calculation" group.word 0xC500++0x1 line.word 0x0 "RAWLANE1_DIG_AON_AFE_ATT_IDAC_OFST,Offset value for RX AFE ATT iDAC" newline hexmask.word.byte 0x0 8.--15. 1. "RESERVED_15_8,Reserved for Future use" newline hexmask.word.byte 0x0 0.--7. 1. "AFE_ATT_IDAC_OFST,Offset value for AFE ATT iDAC" group.word 0xC504++0x1 line.word 0x0 "RAWLANE1_DIG_AON_AFE_CTLE_IDAC_OFST,Offset value for RX AFE CTLE iDAC" newline hexmask.word.byte 0x0 8.--15. 1. "RESERVED_15_8,Reserved for Future use" newline hexmask.word.byte 0x0 0.--7. 1. "AFE_CTLE_IDAC_OFST,Offset value for AFE CTLE iDAC" group.word 0xC508++0x1 line.word 0x0 "RAWLANE1_DIG_AON_ADAPT_REF_LVL_DAC_CODE,Reference level for RX AFE Adaptation" newline hexmask.word.byte 0x0 8.--15. 1. "RESERVED_15_8,Reserved for Future use" newline hexmask.word.byte 0x0 0.--7. 1. "ADAPT_REF_LVL_DAC_CODE,Reference level for RX AFE Adaptation" group.word 0xC50C++0x1 line.word 0x0 "RAWLANE1_DIG_AON_RX_ADAPT_FOM,Adaptation Figure of Merit (FOM)" newline hexmask.word.byte 0x0 8.--15. 1. "RESERVED_15_8,Reserved for Future use" newline hexmask.word.byte 0x0 0.--7. 1. "RX_ADAPT_FOM,Adaptation Figure of Merit (FOM)" group.word 0xC510++0x1 line.word 0x0 "RAWLANE1_DIG_AON_AFE_CTLE_LBK_IDAC_OFST,Offset values for RX CTLE Loopback path iDAC" newline hexmask.word.byte 0x0 8.--15. 1. "RESERVED_15_8,Reserved for Future use" newline hexmask.word.byte 0x0 0.--7. 1. "AFE_CTLE_LBK_IDAC_OFST,Offset value for RX CTLE Loopback path iDAC" group.word 0xC514++0x1 line.word 0x0 "RAWLANE1_DIG_AON_DFE_PHASE_EVEN_VDAC_OFST,Offset values for RX DFE Phase Even vDAC" newline hexmask.word.byte 0x0 8.--15. 1. "RESERVED_15_8,Reserved for Future use" newline hexmask.word.byte 0x0 0.--7. 1. "DFE_PHASE_EVEN_VDAC_OFST,Offset value for DFE Phase Even vDAC" group.word 0xC518++0x1 line.word 0x0 "RAWLANE1_DIG_AON_DFE_PHASE_ODD_VDAC_OFST,Offset values for RX DFE Phase Odd vDAC" newline hexmask.word.byte 0x0 8.--15. 1. "RESERVED_15_8,Reserved for Future use" newline hexmask.word.byte 0x0 0.--7. 1. "DFE_PHASE_ODD_VDAC_OFST,Offset value for DFE Phase Odd vDAC" group.word 0xC51C++0x1 line.word 0x0 "RAWLANE1_DIG_AON_DFE_EVEN_REF_LVL,DFE Even reference level" newline hexmask.word.byte 0x0 8.--15. 1. "RESERVED_15_8,Reserved for Future use" newline hexmask.word.byte 0x0 0.--7. 1. "DFE_EVEN_REF_LVL,DFE Even reference level" group.word 0xC520++0x1 line.word 0x0 "RAWLANE1_DIG_AON_DFE_ODD_REF_LVL,DFE Odd reference level" newline hexmask.word.byte 0x0 8.--15. 1. "RESERVED_15_8,Reserved for Future use" newline hexmask.word.byte 0x0 0.--7. 1. "DFE_ODD_REF_LVL,DFE Odd reference level" group.word 0xC524++0x1 line.word 0x0 "RAWLANE1_DIG_AON_RX_PHSADJ_LIN,RX Phase Adjust Linear Value" newline hexmask.word 0x0 5.--15. 1. "RESERVED_15_5,Reserved for Future use" newline hexmask.word.byte 0x0 0.--4. 1. "RX_PHSADJ_LIN,Linear value for RX phase adjust" rgroup.word 0xC528++0x1 line.word 0x0 "RAWLANE1_DIG_AON_RX_PHSADJ_MAP,RX Phase Adjust Mapped Value" newline hexmask.word 0x0 5.--15. 1. "RESERVED_15_5,Reserved for Future use" newline hexmask.word.byte 0x0 0.--4. 1. "RX_PHSADJ_MAP,Mapped value for RX phase adjust" group.word 0xC52C++0x1 line.word 0x0 "RAWLANE1_DIG_AON_DFE_DATA_EVEN_HIGH_VDAC_OFST,Offset values for RX DFE Data Even High vDAC" newline hexmask.word.byte 0x0 8.--15. 1. "RESERVED_15_8,Reserved for Future use" newline hexmask.word.byte 0x0 0.--7. 1. "DFE_DATA_EVEN_HIGH_VDAC_OFST,Offset value for DFE Data Even High vDAC" group.word 0xC530++0x1 line.word 0x0 "RAWLANE1_DIG_AON_DFE_DATA_EVEN_LOW_VDAC_OFST,Offset values for RX DFE Data Even Low vDAC" newline hexmask.word 0x0 0.--15. 1. "DFE_DATA_EVEN_LOW_VDAC_OFST,Offset value for DFE Data Even Low vDAC" group.word 0xC534++0x1 line.word 0x0 "RAWLANE1_DIG_AON_DFE_DATA_ODD_HIGH_VDAC_OFST,Offset values for RX DFE Data Odd High vDAC" newline hexmask.word.byte 0x0 8.--15. 1. "RESERVED_15_8,Reserved for Future use" newline hexmask.word.byte 0x0 0.--7. 1. "DFE_DATA_ODD_HIGH_VDAC_OFST,Offset value for DFE Data Odd High vDAC" group.word 0xC538++0x1 line.word 0x0 "RAWLANE1_DIG_AON_DFE_DATA_ODD_LOW_VDAC_OFST,Offset values for RX DFE Data Odd Low vDAC" newline hexmask.word 0x0 0.--15. 1. "DFE_DATA_ODD_LOW_VDAC_OFST,Offset value for DFE Data Odd Low vDAC" group.word 0xC53C++0x1 line.word 0x0 "RAWLANE1_DIG_AON_DFE_BYPASS_EVEN_VDAC_OFST,Offset values for RX DFE By-Pass Even vDAC" newline hexmask.word.byte 0x0 8.--15. 1. "RESERVED_15_8,Reserved for Future use" newline hexmask.word.byte 0x0 0.--7. 1. "DFE_BYPASS_EVEN_VDAC_OFST,Offset value for DFE By-Pass Even vDAC" group.word 0xC540++0x1 line.word 0x0 "RAWLANE1_DIG_AON_DFE_BYPASS_ODD_VDAC_OFST,Offset values for RX DFE By-Pass Odd vDAC" newline hexmask.word.byte 0x0 8.--15. 1. "RESERVED_15_8,Reserved for Future use" newline hexmask.word.byte 0x0 0.--7. 1. "DFE_BYPASS_ODD_VDAC_OFST,Offset value for DFE By-Pass Odd vDAC" group.word 0xC544++0x1 line.word 0x0 "RAWLANE1_DIG_AON_DFE_ERROR_EVEN_VDAC_OFST,Offset values for RX DFE Error Even vDAC" newline hexmask.word.byte 0x0 8.--15. 1. "RESERVED_15_8,Reserved for Future use" newline hexmask.word.byte 0x0 0.--7. 1. "DFE_ERROR_EVEN_VDAC_OFST,Offset value for DFE Error Even vDAC" group.word 0xC548++0x1 line.word 0x0 "RAWLANE1_DIG_AON_DFE_ERROR_ODD_VDAC_OFST,Offset values for RX DFE Error Odd vDAC" newline hexmask.word.byte 0x0 8.--15. 1. "RESERVED_15_8,Reserved for Future use" newline hexmask.word.byte 0x0 0.--7. 1. "DFE_ERROR_ODD_VDAC_OFST,Offset value for DFE Error Odd vDAC" group.word 0xC54C++0x1 line.word 0x0 "RAWLANE1_DIG_AON_RX_IQ_PHASE_ADJUST,Value for RX IQ PHASE Adjust" newline hexmask.word 0x0 7.--15. 1. "RESERVED_15_7,Reserved for Future use" newline hexmask.word.byte 0x0 0.--6. 1. "RX_IQ_PHASE_ADJUST,Value for RX IQ PHASE Adjust" group.word 0xC550++0x1 line.word 0x0 "RAWLANE1_DIG_AON_MPLLA_COARSE_TUNE,MPLLA_COARSE_TUNE" newline hexmask.word.byte 0x0 8.--15. 1. "RESERVED_15_8,Reserved for Future use" newline hexmask.word.byte 0x0 0.--7. 1. "MPLLA_COARSE_TUNE,Stored coarse tune value for MPLLA" group.word 0xC554++0x1 line.word 0x0 "RAWLANE1_DIG_AON_MPLLB_COARSE_TUNE,MPLLB_COARSE_TUNE" newline hexmask.word.byte 0x0 8.--15. 1. "RESERVED_15_8,Reserved for Future use" newline hexmask.word.byte 0x0 0.--7. 1. "MPLLB_COARSE_TUNE,Stored coarse tune value for MPLLB" group.word 0xC558++0x1 line.word 0x0 "RAWLANE1_DIG_AON_INIT_PWRUP_DONE,Initial Power-Up Done Status" newline hexmask.word 0x0 1.--15. 1. "RESERVED_15_1,Reserved for Future use" newline bitfld.word 0x0 0. "INIT_PWRUP_DONE,Indicates whether initial power-up has completed or not." "0,1" group.word 0xC55C++0x1 line.word 0x0 "RAWLANE1_DIG_AON_RX_ADPT_ATT,RX Adapted value of ATT" newline hexmask.word.byte 0x0 8.--15. 1. "RESERVED_15_8,Reserved for Future use" newline hexmask.word.byte 0x0 0.--7. 1. "ATT_ADPT_VAL,Stored RX adapted ATT value" group.word 0xC560++0x1 line.word 0x0 "RAWLANE1_DIG_AON_RX_ADPT_VGA,RX Adapted value of VGA" newline hexmask.word.byte 0x0 10.--15. 1. "RESERVED_15_10,Reserved for Future use" newline hexmask.word 0x0 0.--9. 1. "VGA_ADPT_VAL,Stored RX adapted VGA value" group.word 0xC564++0x1 line.word 0x0 "RAWLANE1_DIG_AON_RX_ADPT_CTLE,RX Adapted value of CTLE" newline rbitfld.word 0x0 13.--15. "RESERVED_15_13,Reserved for Future use" "0,1,2,3,4,5,6,7" newline bitfld.word 0x0 10.--12. "CTLE_POLE_ADPT_VAL,Stored RX adapted CTLE pole value" "0,1,2,3,4,5,6,7" newline hexmask.word 0x0 0.--9. 1. "CTLE_BOOST_ADPT_VAL,Stored RX adapted CTLE boost value" group.word 0xC568++0x1 line.word 0x0 "RAWLANE1_DIG_AON_RX_ADPT_DFE_TAP1,RX Adapted value of DFE TAP1" newline rbitfld.word 0x0 13.--15. "RESERVED_15_13,Reserved for Future use" "0,1,2,3,4,5,6,7" newline hexmask.word 0x0 0.--12. 1. "DFE_TAP1_ADPT_VAL,Stored RX adapted DFE TAP1 value" group.word 0xC56C++0x1 line.word 0x0 "RAWLANE1_DIG_AON_RX_ADAPT_DONE,RX Adaptation Done Status" newline hexmask.word 0x0 1.--15. 1. "RESERVED_15_1,Reserved for Future use" newline bitfld.word 0x0 0. "RX_ADAPT_DONE,Indicates whether RX adaptation has completed or not." "0,1" group.word 0xC570++0x1 line.word 0x0 "RAWLANE1_DIG_AON_FAST_FLAGS,Fast flags for simulation only" newline rbitfld.word 0x0 15. "RESERVED_15_15,Reserved for Future use" "0,1" newline bitfld.word 0x0 14. "FAST_RX_VCO_CAL,Enable fast RX VCO Calibration" "0,1" newline bitfld.word 0x0 13. "FAST_RX_VCO_WAIT,Enable fast RX VCO wait times" "0,1" newline bitfld.word 0x0 12. "FAST_RX_PWRUP,Enable fast RX power-up (LOS VREG/AFE and DCC)" "0,1" newline bitfld.word 0x0 11. "FAST_TX_RXDET,Enable fast TX Detect RX" "0,1" newline bitfld.word 0x0 10. "FAST_TX_CMN_MODE,Enable fast TX Common Mode Charge-up" "0,1" newline bitfld.word 0x0 9. "FAST_SUP,Enable fast Support block (MPLL and Rtune)" "0,1" newline bitfld.word 0x0 8. "FAST_RX_DFE_ADAPT,Enables fast RX DFE DAC start-up adaptation" "0,1" newline bitfld.word 0x0 7. "FAST_RX_AFE_ADAPT,Enables fast RX AFE DAC start-up adaptation" "0,1" newline bitfld.word 0x0 6. "FAST_RX_IQ_CAL,Enables fast RX IQ start-up calibration" "0,1" newline bitfld.word 0x0 5. "FAST_RX_REFLVL_CAL,Enables fast RX reference level (100mv 125mv 150mv) start-up calibration" "0,1" newline bitfld.word 0x0 4. "FAST_RX_DFE_RE_ADAPT,Enables fast RX DFE re -adaptation" "0,1" newline bitfld.word 0x0 3. "FAST_RX_DFE_CAL,Enables fast RX DFE slicer start-up calibration" "0,1" newline bitfld.word 0x0 2. "FAST_RX_AFE_CAL,Enables fast RX AFE DAC start-up calibration" "0,1" newline bitfld.word 0x0 1. "FAST_RX_ADAPT,Enables fast RX adaptation" "0,1" newline bitfld.word 0x0 0. "FAST_RX_STARTUP_CAL,Enables fast RX start-up calibration" "0,1" group.word 0xC574++0x1 line.word 0x0 "RAWLANE1_DIG_AON_RX_ADPT_DFE_TAP2,RX Adapted value of DFE TAP2" newline hexmask.word.byte 0x0 12.--15. 1. "RESERVED_15_12,Reserved for Future use" newline hexmask.word 0x0 0.--11. 1. "DFE_TAP2_ADPT_VAL,Stored RX adapted DFE TAP2 value" group.word 0xC578++0x1 line.word 0x0 "RAWLANE1_DIG_AON_RX_PHSADJ_LIN_RIGHT,RX last stable iq phase of Right of the eye" newline hexmask.word.byte 0x0 8.--15. 1. "RESERVED,Reserved bits" newline hexmask.word.byte 0x0 0.--7. 1. "RX_PHSADJ_LIN_RIGHT,Stored RX iq phase right edge" group.word 0xC57C++0x1 line.word 0x0 "RAWLANE1_DIG_AON_RX_PHSADJ_LIN_LEFT,RX last stable iq phase of Left of the eye" newline hexmask.word.byte 0x0 8.--15. 1. "RESERVED,Reserved bits" newline hexmask.word.byte 0x0 0.--7. 1. "RX_PHSADJ_LIN_LEFT,Stored RX iq phase left edge" group.word 0xC580++0x1 line.word 0x0 "RAWLANE1_DIG_AON_RX_PHSADJ_LIN_ADAPT,RX Adapted value of PHASE IQ" newline hexmask.word.byte 0x0 8.--15. 1. "RESERVED,Reserved bits" newline hexmask.word.byte 0x0 0.--7. 1. "RX_PHSADJ_LIN_ADAPT,Stored RX adapted IQ value" group.word 0xC584++0x1 line.word 0x0 "RAWLANE1_DIG_AON_RX_SLICER_CTRL_EVEN,Sets values for RX SLICER CTRL EVEN signals going to ANA" newline hexmask.word 0x0 4.--15. 1. "RESERVED_15_4,Reserved for Future use" newline hexmask.word.byte 0x0 0.--3. 1. "RX_ANA_SLICER_CTRL_E,Value for rx_ana_slicer_ctrl_e[3:0]" group.word 0xC588++0x1 line.word 0x0 "RAWLANE1_DIG_AON_RX_SLICER_CTRL_ODD,Sets values for RX SLICER CTRL ODD signals going to ANA" newline hexmask.word 0x0 4.--15. 1. "RESERVED_15_4,Reserved for Future use" newline hexmask.word.byte 0x0 0.--3. 1. "RX_ANA_SLICER_CTRL_O,Value for rx_ana_slicer_ctrl_o[3:0]" group.word 0xC58C++0x1 line.word 0x0 "RAWLANE1_DIG_AON_LANE_CMNCAL_MPLL_STATUS,MPLL Common Calibration Status" newline hexmask.word 0x0 2.--15. 1. "RESERVED_15_2,Reserved for Future use" newline bitfld.word 0x0 1. "LANE_CMNCAL_MPLL_DONE,Indicates whether MPLL common calibration has been completed by this lane or not." "0,1" newline bitfld.word 0x0 0. "LANE_CMNCAL_MPLL_INIT,Indicates whether MPLL common calibration has been started by this lane or not." "0,1" repeat 8. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 )(list 0x0 0x4 0x8 0xC 0x10 0x14 0x18 0x1C ) group.word ($2+0xC590)++0x1 line.word 0x0 "RAWLANE1_DIG_AON_ADPT_CTL_$1,Adaptation Control register #0" newline hexmask.word 0x0 0.--15. 1. "VAL,Value of adaptation control" repeat.end group.word 0xC5B0++0x1 line.word 0x0 "RAWLANE1_DIG_AON_MPLL_DISABLE,LANE_MPLLA/B_DISABLE override" newline hexmask.word 0x0 2.--15. 1. "RESERVED_15_2,Reserved for Future use" newline bitfld.word 0x0 1. "LANE_MPLLB_DISABLE,Disable MPLLB" "0,1" newline bitfld.word 0x0 0. "LANE_MPLLA_DISABLE,Disable MPLLA" "0,1" group.word 0xC5B4++0x1 line.word 0x0 "RAWLANE1_DIG_AON_FAST_FLAGS_2,Fast flags for simulation only" newline hexmask.word.byte 0x0 12.--15. 1. "RSVD_FAST_FLAGS,Reserved fast flags" newline bitfld.word 0x0 11. "SKIP_IQ_STEP_SKIP,Skip the IQ step skip option" "0,1" newline bitfld.word 0x0 10. "SKIP_250US_WAIT,Skip bit for USB Gen1 250us wait FW WA" "0,1" newline bitfld.word 0x0 9. "WA_ATT_VCM_ISSUE_MODE,Workaround en or disable STAR 9001169835" "0,1" newline bitfld.word 0x0 8. "FAST_RX_CTLE_ADAPT,Enables fast RX CTLE adaptation" "0,1" newline bitfld.word 0x0 7. "FAST_RX_ATT_ADAPT,Enables fast RX ATT adaptation" "0,1" newline bitfld.word 0x0 6. "RX_IQ_DELTA_ADD,Enables RX IQ DELTA addition" "0,1" newline bitfld.word 0x0 5. "FAST_RX_IQ_ADAPT,Enables fast RX IQ ADAPT" "0,1" newline bitfld.word 0x0 4. "FAST_RX_CONT_AFE_CAL,Enables fast RX continuous AFE calibration" "0,1" newline bitfld.word 0x0 3. "FAST_RX_CONT_PHASE_CAL,Enables fast RX continuous phase calibration" "0,1" newline bitfld.word 0x0 2. "FAST_RX_CONT_DATA_CAL,Enables fast RX continuous data calibration" "0,1" newline bitfld.word 0x0 1. "FAST_RX_CONT_ADAPT,Enables fast RX continuous adaptation" "0,1" newline bitfld.word 0x0 0. "FAST_RX_CONT_CAL_ADAPT,Enables fast RX continuous calibration/adaptation" "0,1" group.word 0xC5B8++0x1 line.word 0x0 "RAWLANE1_DIG_AON_LANE_CMNCAL_RCAL_STATUS,RTUNE Common Calibration Status" newline hexmask.word 0x0 2.--15. 1. "RESERVED_15_2,Reserved for Future use" newline bitfld.word 0x0 1. "LANE_CMNCAL_RCAL_DONE,Indicates whether RTUNE common calibration has been completed by this lane or not." "0,1" newline bitfld.word 0x0 0. "LANE_CMNCAL_RCAL_INIT,Indicates whether RTUNE common calibration has been started by this lane or not." "0,1" group.word 0xC5BC++0x1 line.word 0x0 "RAWLANE1_DIG_AON_TXRX_OVRD_IN,Override values for incoming AON TX/RX controls from PCS" newline hexmask.word 0x0 4.--15. 1. "RESERVED_15_4,Reserved for Future use" newline bitfld.word 0x0 3. "TX_DISABLE_OVRD_EN,Override enable for tx_disable" "0,1" newline bitfld.word 0x0 2. "TX_DISABLE_OVRD_VAL,Override value for tx_disable" "0,1" newline bitfld.word 0x0 1. "RX_DISABLE_OVRD_EN,Override enable for rx_disable" "0,1" newline bitfld.word 0x0 0. "RX_DISABLE_OVRD_VAL,Override value for rx_disable" "0,1" group.word 0xC5C0++0x1 line.word 0x0 "RAWLANE1_DIG_AON_AFE_ATT_2_IDAC_OFST,Offset value for RX AFE ATT_2 iDAC" newline hexmask.word.byte 0x0 8.--15. 1. "RESERVED_15_8,Reserved for Future use" newline hexmask.word.byte 0x0 0.--7. 1. "AFE_ATT_2_IDAC_OFST,Offset value for AFE ATT_2 iDAC when cc is 1 in ana typec projects" group.word 0xC5C4++0x1 line.word 0x0 "RAWLANE1_DIG_AON_RXTX_CC_OVRD_IN,Override incoming values for rxtx_cc" newline hexmask.word 0x0 2.--15. 1. "RESERVED_15_2,Reserved for Future use" newline bitfld.word 0x0 1. "RXTX_CC_OVRD_EN,Enable override value for rxtx_cc" "0,1" newline bitfld.word 0x0 0. "RXTX_CC_OVRD_VAL,Override value for rxtx_cc" "0,1" rgroup.word 0xC5C8++0x1 line.word 0x0 "RAWLANE1_DIG_AON_RXTX_CC_STATUS_IN,Incoming value of CC status from TCA" newline hexmask.word 0x0 1.--15. 1. "RESERVED_15_1,Reserved for Future use" newline bitfld.word 0x0 0. "RXTX_CC_IN_I,Value from TCA of cc" "0,1" rgroup.word 0xC5CC++0x1 line.word 0x0 "RAWLANE1_DIG_AON_RXTX_CC_STATUS_OUT,Current values for outgoing CC status to PMA" newline hexmask.word 0x0 1.--15. 1. "RESERVED_15_1,Reserved for Future use" newline bitfld.word 0x0 0. "RXTX_CC_OUT,Value to PMA of cc" "0,1" group.word 0xC600++0x1 line.word 0x0 "RAWLANE1_DIG_IRQ_CTL_RESET_RTN_REQ,Reset routine request" newline hexmask.word 0x0 1.--15. 1. "RESERVED_15_1,Reserved for Future use" newline bitfld.word 0x0 0. "RESET_RTN_REQ,Reset routine request" "0,1" rgroup.word 0xC604++0x1 line.word 0x0 "RAWLANE1_DIG_IRQ_CTL_RX_RESET_IRQ,Rx reset interrupt" newline hexmask.word 0x0 1.--15. 1. "RESERVED_15_1,Reserved for Future use" newline bitfld.word 0x0 0. "RX_RESET,Rx reset interrupt" "0,1" rgroup.word 0xC608++0x1 line.word 0x0 "RAWLANE1_DIG_IRQ_CTL_RX_REQ_IRQ,Rx request interrupt" newline hexmask.word 0x0 1.--15. 1. "RESERVED_15_1,Reserved for Future use" newline bitfld.word 0x0 0. "RX_REQ,Rx request interrupt" "0,1" rgroup.word 0xC60C++0x1 line.word 0x0 "RAWLANE1_DIG_IRQ_CTL_RX_RATE_IRQ,Rx rate change interrupt request" newline hexmask.word 0x0 1.--15. 1. "RESERVED_15_1,Reserved for Future use" newline bitfld.word 0x0 0. "RX_RATE_IRQ,Rx rate change interrupt request" "0,1" rgroup.word 0xC610++0x1 line.word 0x0 "RAWLANE1_DIG_IRQ_CTL_RX_PSTATE_IRQ,Rx pstate change interrupt request" newline hexmask.word 0x0 1.--15. 1. "RESERVED_15_1,Reserved for Future use" newline bitfld.word 0x0 0. "RX_PSTATE_IRQ,Rx pstate change interrupt request" "0,1" rgroup.word 0xC614++0x1 line.word 0x0 "RAWLANE1_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ,Rx adaptation request interrupt" newline hexmask.word 0x0 1.--15. 1. "RESERVED_15_1,Reserved for Future use" newline bitfld.word 0x0 0. "RX_ADAPT_REQ_IRQ,Rx adaptation request interrupt" "0,1" rgroup.word 0xC618++0x1 line.word 0x0 "RAWLANE1_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ,Rx adaptation disable interrupt" newline hexmask.word 0x0 1.--15. 1. "RESERVED_15_1,Reserved for Future use" newline bitfld.word 0x0 0. "RX_ADAPT_DIS_IRQ,Rx adaptation disable interrupt" "0,1" group.word 0xC61C++0x1 line.word 0x0 "RAWLANE1_DIG_IRQ_CTL_RX_RESET_IRQ_CLR,RX reset interrupt clear" newline hexmask.word 0x0 1.--15. 1. "RESERVED_15_1,Reserved for Future use" newline bitfld.word 0x0 0. "RX_RESET_IRQ_CLR,RX reset interrupt clear (self-clearing)" "0,1" group.word 0xC620++0x1 line.word 0x0 "RAWLANE1_DIG_IRQ_CTL_RX_REQ_IRQ_CLR,RX request interrupt clear" newline hexmask.word 0x0 1.--15. 1. "RESERVED_15_1,Reserved for Future use" newline bitfld.word 0x0 0. "RX_REQ_IRQ_CLR,RX request interrupt clear (self-clearing)" "0,1" group.word 0xC624++0x1 line.word 0x0 "RAWLANE1_DIG_IRQ_CTL_RX_RATE_IRQ_CLR,RX rate change interrupt clear" newline hexmask.word 0x0 1.--15. 1. "RESERVED_15_1,Reserved for Future use" newline bitfld.word 0x0 0. "RX_RATE_IRQ_CLR,RX rate change interrupt clear (self-clearing)" "0,1" group.word 0xC628++0x1 line.word 0x0 "RAWLANE1_DIG_IRQ_CTL_RX_PSTATE_IRQ_CLR,RX pstate change interrupt clear" newline hexmask.word 0x0 1.--15. 1. "RESERVED_15_1,Reserved for Future use" newline bitfld.word 0x0 0. "RX_PSTATE_IRQ_CLR,RX pstate change interrupt clear (self-clearing)" "0,1" group.word 0xC62C++0x1 line.word 0x0 "RAWLANE1_DIG_IRQ_CTL_RX_ADAPT_REQ_IRQ_CLR,RX adaptation request interrupt clear" newline hexmask.word 0x0 1.--15. 1. "RESERVED_15_1,Reserved for Future use" newline bitfld.word 0x0 0. "RX_ADAPT_REQ_IRQ_CLR,RX adaptation request interrupt clear (self-clearing)" "0,1" group.word 0xC630++0x1 line.word 0x0 "RAWLANE1_DIG_IRQ_CTL_RX_ADAPT_DIS_IRQ_CLR,RX adaptation disable interrupt clear" newline hexmask.word 0x0 1.--15. 1. "RESERVED_15_1,Reserved for Future use" newline bitfld.word 0x0 0. "RX_ADAPT_DIS_IRQ_CLR,RX adaptation disable interrupt clear (self-clearing)" "0,1" group.word 0xC634++0x1 line.word 0x0 "RAWLANE1_DIG_IRQ_CTL_IRQ_MASK,Interrupt Mask" newline hexmask.word 0x0 7.--15. 1. "RESERVED_15_7,Reserved for Future use" newline bitfld.word 0x0 6. "LANE_XCVR_MODE_IRQ_MSK,Mask for lane_xcvr_mode interrupt (0 = cannot interrupt)" "cannot interrupt),?" newline bitfld.word 0x0 5. "RX_RESET_IRQ_MSK,Mask for Rx reset interrupt (0 = cannot interrupt)" "cannot interrupt),?" newline bitfld.word 0x0 4. "RX_ADAPT_DIS_IRQ_MSK,Mask for Rx adaptation disable interrupt (0 = cannot interrupt)" "cannot interrupt),?" newline bitfld.word 0x0 3. "RX_ADAPT_REQ_IRQ_MSK,Mask for Rx adaptation request interrupt (0 = cannot interrupt)" "cannot interrupt),?" newline bitfld.word 0x0 2. "RX_PSTATE_IRQ_MSK,Mask for Rx pstate change interrupt (0 = cannot interrupt)" "cannot interrupt),?" newline bitfld.word 0x0 1. "RX_RATE_IRQ_MSK,Mask for Rx rate change interrupt (0 = cannot interrupt)" "cannot interrupt),?" newline bitfld.word 0x0 0. "RX_REQ_IRQ_MSK,Mask for Rx request interrupt (0 = cannot interrupt)" "cannot interrupt),?" rgroup.word 0xC638++0x1 line.word 0x0 "RAWLANE1_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ,Lane transceiver mode interrupt" newline hexmask.word 0x0 1.--15. 1. "RESERVED_15_1,Reserved for Future use" newline bitfld.word 0x0 0. "LANE_XCVR_MODE_IRQ,Lane transceiver mode interrupt" "0,1" group.word 0xC63C++0x1 line.word 0x0 "RAWLANE1_DIG_IRQ_CTL_LANE_XCVR_MODE_IRQ_CLR,Lane transceiver mode interrupt clear" newline hexmask.word 0x0 1.--15. 1. "RESERVED_15_1,Reserved for Future use" newline bitfld.word 0x0 0. "LANE_XCVR_MODE_IRQ_CLR,Lane transceiver mode interrupt clear (self-clearing)" "0,1" group.word 0xC680++0x1 line.word 0x0 "RAWLANE1_DIG_PMA_XF_LANE_OVRD_IN,Override values for incoming LANE controls" newline hexmask.word 0x0 3.--15. 1. "RESERVED_15_3,Reserved for Future use" newline bitfld.word 0x0 2. "LANE_OVRD_EN,Override enable for signals in this register" "0,1" newline bitfld.word 0x0 1. "LANE_MPLLB_EN_IN,Override value for lane_mpllb_en_in" "0,1" newline bitfld.word 0x0 0. "LANE_MPLLA_EN_IN,Override value for lane_mplla_en_in" "0,1" group.word 0xC684++0x1 line.word 0x0 "RAWLANE1_DIG_PMA_XF_LANE_OVRD_OUT,Override values for outgoing LANE controls" newline hexmask.word 0x0 3.--15. 1. "RESERVED_15_3,Reserved for Future use" newline bitfld.word 0x0 2. "LANE_OVRD_EN,Override enable for signals in this register" "0,1" newline bitfld.word 0x0 1. "LANE_MPLLB_EN_OUT,Override value for lane_mpllb_en_out" "0,1" newline bitfld.word 0x0 0. "LANE_MPLLA_EN_OUT,Override value for lane_mplla_en_out" "0,1" group.word 0xC688++0x1 line.word 0x0 "RAWLANE1_DIG_PMA_XF_SUP_OVRD_IN,Override values for incoming SUP controls from PMA" newline hexmask.word 0x0 3.--15. 1. "RESERVED_15_3,Reserved for Future use" newline bitfld.word 0x0 2. "SUP_STATE_OVRD_EN,Override enable for signals in this register" "0,1" newline bitfld.word 0x0 1. "MPLLB_STATE,Override value for mpllb_state" "0,1" newline bitfld.word 0x0 0. "MPLLA_STATE,Override value for mplla_state" "0,1" rgroup.word 0xC68C++0x1 line.word 0x0 "RAWLANE1_DIG_PMA_XF_SUP_PMA_IN,Current values for incoming MPLL status controls from PMA" newline hexmask.word 0x0 2.--15. 1. "RESERVED_15_2,Reserved for Future use" newline bitfld.word 0x0 1. "MPLLB_STATE,Value from PMA for mpllb_state" "0,1" newline bitfld.word 0x0 0. "MPLLA_STATE,Value from PMA for mplla_state" "0,1" group.word 0xC690++0x1 line.word 0x0 "RAWLANE1_DIG_PMA_XF_TX_OVRD_OUT,Override values for outgoing TX controls to PMA" newline hexmask.word 0x0 4.--15. 1. "RESERVED_15_4,Reserved for Future use" newline bitfld.word 0x0 3. "TX_RESET_OVRD_EN,Override enable for tx_reset" "0,1" newline bitfld.word 0x0 2. "TX_RESET_OVRD_VAL,Override value for tx_reset" "0,1" newline bitfld.word 0x0 1. "TX_REQ_OVRD_EN,Override enable for tx_req" "0,1" newline bitfld.word 0x0 0. "TX_REQ_OVRD_VAL,Override value for tx_req" "0,1" rgroup.word 0xC694++0x1 line.word 0x0 "RAWLANE1_DIG_PMA_XF_TX_PMA_IN,Current values for coming TX status controls from PMA" newline hexmask.word 0x0 1.--15. 1. "RESERVED_15_1,Reserved for Future use" newline bitfld.word 0x0 0. "ACK,Value from PMA for tx_ack" "0,1" group.word 0xC698++0x1 line.word 0x0 "RAWLANE1_DIG_PMA_XF_RX_OVRD_OUT,Override values for outgoing RX controls to PMA" newline hexmask.word 0x0 4.--15. 1. "RESERVED_15_4,Reserved for Future use" newline bitfld.word 0x0 3. "RX_RESET_OVRD_EN,Override enable for rx_reset" "0,1" newline bitfld.word 0x0 2. "RX_RESET_OVRD_VAL,Override value for rx_reset" "0,1" newline bitfld.word 0x0 1. "RX_REQ_OVRD_EN,Override enable for rx_req" "0,1" newline bitfld.word 0x0 0. "RX_REQ_OVRD_VAL,Override value for rx_req" "0,1" rgroup.word 0xC69C++0x1 line.word 0x0 "RAWLANE1_DIG_PMA_XF_RX_PMA_IN,Current values for coming RX status controls from PMA" newline hexmask.word 0x0 1.--15. 1. "RESERVED_15_1,Reserved for Future use" newline bitfld.word 0x0 0. "ACK,Value from PMA for rx_ack" "0,1" group.word 0xC6A0++0x1 line.word 0x0 "RAWLANE1_DIG_PMA_XF_LANE_RTUNE_CTL,Lane Rtune Controls" newline hexmask.word 0x0 1.--15. 1. "RESERVED_15_1,Reserved for Future use" newline bitfld.word 0x0 0. "LANE_RTUNE_REQ,Lane value for rtune_req" "0,1" rgroup.word 0xC6A4++0x1 line.word 0x0 "RAWLANE1_DIG_PMA_XF_SUP_PMA_IN_1,Current values for incoming RTUNE status controls from PMA" newline hexmask.word 0x0 1.--15. 1. "RESERVED_15_1,Reserved for Future use" newline bitfld.word 0x0 0. "RTUNE_ACK,Value from PMA for rtune_ack" "0,1" rgroup.word 0xC6A8++0x1 line.word 0x0 "RAWLANE1_DIG_PMA_XF_SUP_PMA_RX_VALID,Current value of RX valid from PMA" newline hexmask.word 0x0 1.--15. 1. "RESERVED_15_1,Reserved for Future use" newline bitfld.word 0x0 0. "RX_VALID,Value of RX_VALID" "0,1" group.word 0xC700++0x1 line.word 0x0 "RAWLANE1_DIG_TX_CTL_TX_FSM_CTL,TX FSM Control" newline hexmask.word.byte 0x0 10.--15. 1. "RESERVED_15_10,Reserved for Future use" newline bitfld.word 0x0 9. "TX_P0_ALLOW_RXDET,If asserted then rxdet request is allowed in P0" "0,1" newline bitfld.word 0x0 8. "TX_P0S_ALLOW_RXDET,If asserted then rxdet request is allowed in P0S" "0,1" newline bitfld.word 0x0 7. "TX_P1_ALLOW_RXDET,If asserted then rxdet request is allowed in P1" "0,1" newline bitfld.word 0x0 6. "TX_P2_ALLOW_RXDET,If asserted then rxdet request is allowed in P2" "0,1" newline hexmask.word.byte 0x0 0.--5. 1. "TX_WAIT_MPLL_OFF_TIME,Number of ref_range cycles to wait for MPLL to turn off (When entering P2)." group.word 0xC704++0x1 line.word 0x0 "RAWLANE1_DIG_TX_CTL_TX_CLK_CTL,Select clock to act as TX input clock" newline hexmask.word 0x0 5.--15. 1. "RESERVED_15_5,Reserved for Future use" newline hexmask.word.byte 0x0 1.--4. 1. "TX_CLK_SEL,Select clock source for tx_pma_clk 0 - tx_pcs_clk (input clock from pcs) 1 - mplla_word_clk 2 - mplla_dword_clk 3 - mplla_qword_clk 4 - mplla_oword_clk 5 - mplla_div_clk 6 - mpllb_word_clk 7 - mpllb_dword_clk 8 - mpllb_qword_clk 9 -.." newline bitfld.word 0x0 0. "TX_CLK_EN,Enable the tx_clk to pma tx lane TX_CLK_EN must be deasserted when switching TX_CLK_SEL" "0,1" group.word 0xC780++0x1 line.word 0x0 "RAWLANE1_DIG_RX_CTL_RX_FSM_CTL,RX FSM control register" newline hexmask.word 0x0 2.--15. 1. "RESERVED_15_2,Reserved for Future use" newline bitfld.word 0x0 1. "RATE_CHG_IN_P1,When asserted then a rate change in P0/P0s will be sequenced such that the RX is put in P1 the rate change is applied and then the RX is returned to P0/P0s." "0,1" newline bitfld.word 0x0 0. "EN_RX_CTL_FSM,Enable the RX control FSM in the Raw PCS If enabled then when FSM detects a rate change it moves the RX to P1 does the rate change then goes back to P0/P0s. If not enabled then FSM is by-passed." "0,1" group.word 0xC784++0x1 line.word 0x0 "RAWLANE1_DIG_RX_CTL_RX_LOS_MASK_CTL,RX LOS Mask Control" newline hexmask.word.byte 0x0 9.--15. 1. "RESERVED_15_9,Reserved for Future use" newline hexmask.word 0x0 0.--8. 1. "RX_LOS_MASK_CNT,Number of cycles (ref_range_clk) to mask out the rx_los output from the time the los is powered-on. Default set for minimum 10us." group.word 0xC788++0x1 line.word 0x0 "RAWLANE1_DIG_RX_CTL_RX_DATA_EN_OVRD_CTL,RX Data Enable Override Control" newline hexmask.word 0x0 5.--15. 1. "INT_REF_TRCK_CNT,Number of ref_range cycles to wait for integral reference tracking to settle." newline hexmask.word.byte 0x0 0.--4. 1. "RX_DATA_EN_OVRD_CNT,Number of ref_range cycles to override rx_data_en to 1." rgroup.word 0xC78C++0x1 line.word 0x0 "RAWLANE1_DIG_RX_CTL_OFFCAN_CONT_STATUS,RX continuous offset cancellation status" newline hexmask.word 0x0 1.--15. 1. "RESERVED_15_1,Reserved for Future use" newline bitfld.word 0x0 0. "ENABLE,Enable status for rx continous offset cancellation" "0,1" rgroup.word 0xC790++0x1 line.word 0x0 "RAWLANE1_DIG_RX_CTL_ADAPT_CONT_STATUS,RX continuous adaptation status" newline hexmask.word 0x0 1.--15. 1. "RESERVED_15_1,Reserved for Future use" newline bitfld.word 0x0 0. "ENABLE,Enable status for rx continous adaptation" "0,1" tree.end tree "PCIE_PHY_NCR" base ad:0x31210000 group.long 0x0++0x3B line.long 0x0 "CTRL_0,CTRL_0" newline bitfld.long 0x0 24. "CR_CKEN,CR_CKEN This bit enable CR clock. 0x0 : CR clock disabled 0x1 : CR clock enabled Software need to enable this bit before any CR register access thourgh CR port." "CR clock disabled,CR clock enabled" newline bitfld.long 0x0 22.--23. "CR_PARA_SEL,Control Register (CR) parallel interface select Function: Controls selection between JTAG and CR interfaces: 0 : JTAG 1: Control Register (CR) This input can only be changed when the cr_para_clk and jtag_tck clock inputs are disabled." "JTAG,Control Register,?,?" newline bitfld.long 0x0 21. "PHY_SRAM_EXT_LD_DONE,SRAM external load done.Function: Signal asserted by user after any updates to the SRAM have been loaded." "0,1" newline bitfld.long 0x0 20. "PHY_SRAM_BYPASS,SRAM bypass Function: Control signal when asserted bypasses the SRAM interface. In this case the adaptation and calibration algorithms are executed from the hard wired values within the Raw PCS. If SRAM is not bypassed the internal.." "0,1" newline bitfld.long 0x0 19. "PG_MODE_EN,Power gating support enable. Function: Control input to enable the power gating support.When de-asserted. the control inputs related to power gating are ignored." "0,1" newline hexmask.long.word 0x0 3.--18. 1. "UPCS_PIPE_CONFIG,PCS PIPE configuration.When upcs_pipe_config[0] is set to 1 the PCS ignores lane-off via PIPE specification method (TxElecIdle = 1 and TxCompliance = 1) and responds to power-down/rate/width changes. Otherwise until the MAC deasserts.." newline bitfld.long 0x0 2. "PCS_EXT_PCLK_REQ,External PCLK request.When asserted the MPLL clock sources in the PHY are powered up and pcs_laneX_pclk outputs stay active regardless of the pcs_laneX_powerdown[3:0] inputs." "0,1" newline bitfld.long 0x0 1. "BIF_EN,BIF_EN 0x0 : Bifurcation disabled (Both Lane #0 and Lane #1 used for PCIEX2 core) 0x1 : Bifurcation enabled (Lane #0 used for PCIEX2 core and Lane #1 used for PCIEX1 core)" "Bifurcation disabled,Bifurcation enabled" newline bitfld.long 0x0 0. "PHY_RESET,PHY reset.Function: Asynchronously resets the core and all state machines.Asserting phy_reset resets all sequential elements in the design including control registers. As a result any register programming needs to be redone after phy_reset is.." "0,1" line.long 0x4 "CTRL_1,CTRL_1" newline bitfld.long 0x4 27. "PIPE_TX0_ONES_ZEROS,USB TX compliance pattern enable for lane 0" "0,1" newline bitfld.long 0x4 26. "PIPE_RX0_TERMINATION,RX termination enable for lane 0.When asserted the RX terminations are enabled." "0,1" newline bitfld.long 0x4 25. "PIPE_RX0_EQ_TRAINING,RX equalization training mode enable for lane 0" "0,1" newline bitfld.long 0x4 24. "PIPE_LANE0_CLKREQ_N,Clock request for lane 0" "0,1" newline bitfld.long 0x4 23. "PIPE_LANE0_TX2RX_LOOPBK,TX-to-RX loopback enable for lane 0.When asserted this input turns on the TX-to-RX serial loopback within the PHY.This signal is for debug purposes only." "0,1" newline hexmask.long.byte 0x4 19.--22. 1. "PIPE_LANE0_LINK_NUM,Reserved for future." newline bitfld.long 0x4 18. "PHY_TEST_TX_REF_CLK_EN,TX ref clock output enable.Function: Enables the reference clock inputs (ref_pad_clk_\{p m\} or ref_alt_clk_\{p m\}) to be directly output on txN_\{p m\}. For additional information see 'PHY Test Mode Selection' ." "0,1" newline bitfld.long 0x4 17. "PHY_TEST_STOP_CLK_EN,Stop-clock test mode enable.Function: Reserved" "0,1" newline bitfld.long 0x4 16. "PHY_MPLLB_SSC_EN,Spread spectrum enable.Function: Enables spread-spectrum clock (SSC) generation on the mpllb_div_clk output. If the reference clock already has spread spectrum applied mpllb_ssc_en must be de-asserted.These inputs can only be changed.." "0,1" newline bitfld.long 0x4 15. "PHY_MPLLB_FORCE_EN,MPLLB force enable.Function: When asserted the corresponding MPLL is forced to bepowered up irrespective of the txX_mpll_en input.This input is used for applications whehe a free-running MPLL clock output is required. There are no.." "0,1" newline bitfld.long 0x4 14. "PHY_MPLLA_SSC_EN,Spread spectrum enable.Function:Enables spread-spectrum clock (SSC) generation on the mplla_div_clk output. If the reference clock already has spread spectrum applied mplla_ssc_en must be de-asserted.These inputs can only be changed.." "0,1" newline bitfld.long 0x4 13. "PHY_MPLLA_FORCE_EN,MPLLA force enable.Function: When asserted the corresponding MPLL is forced to be powered up irrespective of the txX_mpll_en input.This input is used for applications where a free-running MPLL clock output is required. There are no.." "0,1" newline bitfld.long 0x4 12. "PHY_RX1_TERM_ACDC,Receiver termination control.Function: Reserved; tie off to 1'b1" "0,1" newline bitfld.long 0x4 11. "PHY_LANE1_RX2TX_PAR_LB_EN,Parallel (RX to TX) loopback enable.Function: When this signal is asserted recovered parallel data from the receiver is looped back to the transmit serializer." "0,1" newline bitfld.long 0x4 10. "PHY_RX0_TERM_ACDC,Receiver termination control.Function: Reserved; tie off to 1'b1" "0,1" newline bitfld.long 0x4 9. "PHY_LANE0_RX2TX_PAR_LB_EN,Parallel (RX to TX) loopback enable.Function: When this signal is asserted recovered parallel data from the receiver is looped back to the transmit serializer." "0,1" newline bitfld.long 0x4 8. "PHY_REF_ALT_CLK_SEL,PHY_REF_ALT_CLK_SEL 0x0 : PHY ref_alt_clk_p input from internal SoC PLL (100MHz). 0x1 : PHY ref_alt_clk_p input from Differential Buffer (100MHz)" "PHY ref_alt_clk_p input from internal SoC PLL,PHY ref_alt_clk_p input from Differential Buffer" newline bitfld.long 0x4 7. "PHY_LANE_POWER_PRESENT,VBUS power present.Signal from external VBUS detection circuit." "0,1" newline bitfld.long 0x4 6. "PHY_REF_REPEAT_CLK_EN,Repeat reference clock enable.Function: Enables the CMOS output clocks ref_repeat_clk_\{p m\}.This pair of clocks can be used as reference clocks for other on-chip PHYs." "0,1" newline bitfld.long 0x4 5. "PHY_REF_USE_PAD,Select reference clock connected to ref_pad_clk_p/ref_pad_clk_m.Function: Selects the external ref_pad_clk_p and ref_pad_clk_m inputs as the reference clock source when asserted. When deasserted ref_alt_clk_p and ref_alt_clk_m are the.." "0,1" newline bitfld.long 0x4 4. "PHY_TEST_POWERDOWN,All circuits power-down control.Function: Powers down all circuitry in the PHY for IDDQ testing Note:The PHY is not functional in this mode and must be reset after this signal is de-asserted." "0,1" newline bitfld.long 0x4 3. "PHY_TEST_BURNIN,All circuits activator." "0,1" newline bitfld.long 0x4 2. "PHY_RTUNE_REQ,Resistor tune request.Function: Assertion triggers a resistor tune request (if one is not already in progress)." "0,1" newline bitfld.long 0x4 0.--1. "CR_CKDIV,CR_CKDIV Clock divider for CR Bus clock. 0x0 : div 1 from APB bus clock 0x1 : div 2 from APB bus clock ...0x3: div4 from APB bus clock" "div 1 from APB bus clock,div 2 from APB bus clock,?,div4 from APB bus clock" line.long 0x8 "CTRL_2,CTRL_2" newline hexmask.long.byte 0x8 23.--27. 1. "PROTOCOL0_EXT_BS_RX_LEVEL,PROTOCOL0_EXT_BS_RX_LEVEL" newline bitfld.long 0x8 22. "PROTOCOL0_EXT_BS_TX_LOWSWING,PROTOCOL0_EXT_BS_TX_LOWSWING" "0,1" newline bitfld.long 0x8 21. "PROTOCOL0_EXT_BS_RX_BIGSWING,PROTOCOL0_EXT_BS_RX_BIGSWING" "0,1" newline bitfld.long 0x8 20. "PROTOCOL0_EXT_RX_LOS_LFPS_EN,PROTOCOL0_EXT_RX_LOS_LFPS_EN" "0,1" newline bitfld.long 0x8 17.--19. "PROTOCOL0_EXT_REF_RANGE,PROTOCOL0_EXT_REF_RANGE" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 16. "PROTOCOL0_EXT_REF_CLK_MPLLB_DIV2_EN,PROTOCOL0_EXT_REF_CLK_MPLLB_DIV2_EN" "0,1" newline bitfld.long 0x8 15. "PROTOCOL0_EXT_REF_CLK_MPLLA_DIV2_EN,PROTOCOL0_EXT_REF_CLK_MPLLA_DIV2_EN" "0,1" newline bitfld.long 0x8 14. "PROTOCOL0_EXT_REF_CLK_DIV2_EN,PROTOCOL0_EXT_REF_CLK_DIV2_EN" "0,1" newline bitfld.long 0x8 13. "PHY_EXT_CTRL_SEL,PHY_EXT_CTRL_SEL" "0,1" newline bitfld.long 0x8 11.--12. "PIPE_TX1_PATTERN,PIPE_TX1_PATTERN" "0,1,2,3" newline bitfld.long 0x8 10. "PIPE_TX1_ONES_ZEROS,PIPE_TX1_ONES_ZEROS" "0,1" newline bitfld.long 0x8 9. "PIPE_RX1_TERMINATION,PIPE_RX1_TERMINATION" "0,1" newline bitfld.long 0x8 8. "PIPE_RX1_EQ_TRAINING,PIPE_RX1_EQ_TRAINING" "0,1" newline bitfld.long 0x8 7. "PIPE_LANE1_TX2RX_LOOPBK,PIPE_LANE1_TX2RX_LOOPBK" "0,1" newline hexmask.long.byte 0x8 3.--6. 1. "PIPE_LANE1_LINK_NUM,PIPE_LANE1_LINK_NUM" newline bitfld.long 0x8 2. "PIPE_LANE1_CLKREQ_N,PIPE_LANE1_CLKREQ_N" "0,1" newline bitfld.long 0x8 0.--1. "PIPE_TX0_PATTERN,PIPE_TX0_PATTERN" "0,1,2,3" line.long 0xC "CTRL_3,CTRL_3" newline hexmask.long.byte 0xC 22.--29. 1. "PROTOCOL0_EXT_MPLLA_DIV_MULTIPLIER,PROTOCOL0_EXT_MPLLA_DIV_MULTIPLIER" newline hexmask.long.word 0xC 6.--21. 1. "PROTOCOL0_EXT_MPLLA_BANDWIDTH,PROTOCOL0_EXT_MPLLA_BANDWIDTH" newline bitfld.long 0xC 5. "PROTOCOL0_EXT_MPLLA_WORD_DIV2_EN,PROTOCOL0_EXT_MPLLA_WORD_DIV2_EN" "0,1" newline bitfld.long 0xC 4. "PROTOCOL0_EXT_MPLLA_SSC_FREQ_CNT_OVRD_EN,PROTOCOL0_EXT_MPLLA_SSC_FREQ_CNT_OVRD_EN" "0,1" newline bitfld.long 0xC 3. "PROTOCOL0_EXT_MPLLA_DIV_CLK_EN,PROTOCOL0_EXT_MPLLA_DIV_CLK_EN" "0,1" newline bitfld.long 0xC 2. "PROTOCOL0_EXT_MPLLA_DIV8_CLK_EN,PROTOCOL0_EXT_MPLLA_DIV8_CLK_EN" "0,1" newline bitfld.long 0xC 1. "PIPE_RX_RECAL_CONT_EN,PIPE_RX_RECAL_CONT_EN" "0,1" newline bitfld.long 0xC 0. "PROTOCOL0_EXT_MPLLA_DIV10_CLK_EN,PROTOCOL0_EXT_MPLLA_DIV10_CLK_EN" "0,1" line.long 0x10 "CTRL_4,CTRL_4" bitfld.long 0x10 30.--31. "CR_ADDR_BIT15_14,CR_ADDR_BIT15_14" "0,1,2,3" newline bitfld.long 0x10 29. "CR_ADDR_MODE,CR_ADDR_MODE" "0,1" newline bitfld.long 0x10 26.--28. "PROTOCOL0_EXT_MPLLA_SSC_CLK_SEL,PROTOCOL0_EXT_MPLLA_SSC_CLK_SEL" "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x10 18.--25. 1. "PROTOCOL0_EXT_MPLLA_MULTIPLIER,PROTOCOL0_EXT_MPLLA_MULTIPLIER" newline hexmask.long.word 0x10 7.--17. 1. "PROTOCOL0_EXT_MPLLA_FRACN_CTRL,PROTOCOL0_EXT_MPLLA_FRACN_CTRL" newline bitfld.long 0x10 6. "PROTOCOL0_EXT_MPLLB_DIV10_CLK_EN,PROTOCOL0_EXT_MPLLB_DIV10_CLK_EN" "0,1" newline bitfld.long 0x10 3.--5. "PROTOCOL0_EXT_MPLLA_TX_CLK_DIV,PROTOCOL0_EXT_MPLLA_TX_CLK_DIV" "0,1,2,3,4,5,6,7" newline bitfld.long 0x10 0.--2. "PROTOCOL0_EXT_MPLLA_SSC_RANGE,PROTOCOL0_EXT_MPLLA_SSC_RANGE" "0,1,2,3,4,5,6,7" line.long 0x14 "CTRL_5,CTRL_5" hexmask.long.byte 0x14 26.--31. 1. "PIPE_RX0_IDLE_LOS_CNT,PIPE_RX0_IDLE_LOS_CNT" newline bitfld.long 0x14 24. "PIPE_RX0_CMN_REFCLK_MODE,PIPE_RX0_CMN_REFCLK_MODE" "0,1" newline bitfld.long 0x14 23. "PROTOCOL0_EXT_MPLLB_WORD_DIV2_EN,PROTOCOL0_EXT_MPLLB_WORD_DIV2_EN" "0,1" newline hexmask.long.word 0x14 11.--22. 1. "PROTOCOL0_EXT_MPLLA_SSC_FREQ_CNT_INIT,PROTOCOL0_EXT_MPLLA_SSC_FREQ_CNT_INIT" newline bitfld.long 0x14 10. "PROTOCOL0_EXT_MPLLB_SSC_FREQ_CNT_OVRD_EN,PROTOCOL0_EXT_MPLLB_SSC_FREQ_CNT_OVRD_EN" "0,1" newline bitfld.long 0x14 9. "PROTOCOL0_EXT_MPLLB_DIV_CLK_EN,PROTOCOL0_EXT_MPLLB_DIV_CLK_EN" "0,1" newline bitfld.long 0x14 8. "PROTOCOL0_EXT_MPLLB_DIV8_CLK_EN,PROTOCOL0_EXT_MPLLB_DIV8_CLK_EN" "0,1" newline hexmask.long.byte 0x14 0.--7. 1. "PROTOCOL0_EXT_MPLLA_SSC_FREQ_CNT_PEAK,PROTOCOL0_EXT_MPLLA_SSC_FREQ_CNT_PEAK" line.long 0x18 "CTRL_6,CTRL_6" newline hexmask.long.byte 0x18 18.--25. 1. "PROTOCOL0_EXT_MPLLB_DIV_MULTIPLIER,PROTOCOL0_EXT_MPLLB_DIV_MULTIPLIER" newline bitfld.long 0x18 16.--17. "PROTOCOL0_EXT_RX_ADAPT_AFE_EN_G1,PROTOCOL0_EXT_RX_ADAPT_AFE_EN_G1" "0,1,2,3" newline hexmask.long.word 0x18 0.--15. 1. "PROTOCOL0_EXT_MPLLB_BANDWIDTH,PROTOCOL0_EXT_MPLLB_BANDWIDTH" line.long 0x1C "CTRL_7,CTRL_7" hexmask.long.byte 0x1C 26.--31. 1. "PIPE_RX1_IDLE_LOS_CNT,PIPE_RX1_IDLE_LOS_CNT" newline bitfld.long 0x1C 24. "PIPE_RX1_CMN_REFCLK_MODE,PIPE_RX1_CMN_REFCLK_MODE" "0,1" newline bitfld.long 0x1C 22.--23. "PROTOCOL0_EXT_RX_ADAPT_AFE_EN_G2,PROTOCOL0_EXT_RX_ADAPT_AFE_EN_G2" "0,1,2,3" newline bitfld.long 0x1C 19.--21. "PROTOCOL0_EXT_MPLLB_SSC_CLK_SEL,PROTOCOL0_EXT_MPLLB_SSC_CLK_SEL" "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x1C 11.--18. 1. "PROTOCOL0_EXT_MPLLB_MULTIPLIER,PROTOCOL0_EXT_MPLLB_MULTIPLIER" newline hexmask.long.word 0x1C 0.--10. 1. "PROTOCOL0_EXT_MPLLB_FRACN_CTRL,PROTOCOL0_EXT_MPLLB_FRACN_CTRL" line.long 0x20 "CTRL_8,CTRL_8" bitfld.long 0x20 30.--31. "PROTOCOL0_EXT_RX_ADAPT_DFE_EN_G1,PROTOCOL0_EXT_RX_ADAPT_DFE_EN_G1" "0,1,2,3" newline bitfld.long 0x20 26.--27. "PROTOCOL0_EXT_RX_ADAPT_AFE_EN_G3,PROTOCOL0_EXT_RX_ADAPT_AFE_EN_G3" "0,1,2,3" newline bitfld.long 0x20 23.--25. "PROTOCOL0_EXT_MPLLB_TX_CLK_DIV,PROTOCOL0_EXT_MPLLB_TX_CLK_DIV" "0,1,2,3,4,5,6,7" newline bitfld.long 0x20 20.--22. "PROTOCOL0_EXT_MPLLB_SSC_RANGE,PROTOCOL0_EXT_MPLLB_SSC_RANGE" "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x20 12.--19. 1. "PROTOCOL0_EXT_MPLLB_SSC_FREQ_CNT_PEAK,PROTOCOL0_EXT_MPLLB_SSC_FREQ_CNT_PEAK" newline hexmask.long.word 0x20 0.--11. 1. "PROTOCOL0_EXT_MPLLB_SSC_FREQ_CNT_INIT,PROTOCOL0_EXT_MPLLB_SSC_FREQ_CNT_INIT" line.long 0x24 "CTRL_9,CTRL_9" newline hexmask.long.byte 0x24 20.--27. 1. "PROTOCOL0_EXT_RX_EQ_AFE_GAIN_G3,PROTOCOL0_EXT_RX_EQ_AFE_GAIN_G3" newline hexmask.long.byte 0x24 12.--19. 1. "PROTOCOL0_EXT_RX_EQ_AFE_GAIN_G2,PROTOCOL0_EXT_RX_EQ_AFE_GAIN_G2" newline hexmask.long.byte 0x24 4.--11. 1. "PROTOCOL0_EXT_RX_EQ_AFE_GAIN_G1,PROTOCOL0_EXT_RX_EQ_AFE_GAIN_G1" newline bitfld.long 0x24 2.--3. "PROTOCOL0_EXT_RX_ADAPT_DFE_EN_G3,PROTOCOL0_EXT_RX_ADAPT_DFE_EN_G3" "0,1,2,3" newline bitfld.long 0x24 0.--1. "PROTOCOL0_EXT_RX_ADAPT_DFE_EN_G2,PROTOCOL0_EXT_RX_ADAPT_DFE_EN_G2" "0,1,2,3" line.long 0x28 "CTRL_10,CTRL_10" newline bitfld.long 0x28 22.--23. "PROTOCOL0_EXT_RX_CDR_VCO_LOWFREQ_G3,PROTOCOL0_EXT_RX_CDR_VCO_LOWFREQ_G3" "0,1,2,3" newline bitfld.long 0x28 20.--21. "PROTOCOL0_EXT_RX_CDR_VCO_LOWFREQ_G2,PROTOCOL0_EXT_RX_CDR_VCO_LOWFREQ_G2" "0,1,2,3" newline bitfld.long 0x28 18.--19. "PROTOCOL0_EXT_RX_CDR_VCO_LOWFREQ_G1,PROTOCOL0_EXT_RX_CDR_VCO_LOWFREQ_G1" "0,1,2,3" newline hexmask.long.byte 0x28 12.--17. 1. "PROTOCOL0_EXT_RX_EQ_ATT_LVL_G3,PROTOCOL0_EXT_RX_EQ_ATT_LVL_G3" newline hexmask.long.byte 0x28 6.--11. 1. "PROTOCOL0_EXT_RX_EQ_ATT_LVL_G2,PROTOCOL0_EXT_RX_EQ_ATT_LVL_G2" newline hexmask.long.byte 0x28 0.--5. 1. "PROTOCOL0_EXT_RX_EQ_ATT_LVL_G1,PROTOCOL0_EXT_RX_EQ_ATT_LVL_G1" line.long 0x2C "CTRL_11,CTRL_11" newline hexmask.long.word 0x2C 20.--29. 1. "PROTOCOL0_EXT_RX_EQ_CTLE_BOOST_G3,PROTOCOL0_EXT_RX_EQ_CTLE_BOOST_G3" newline hexmask.long.word 0x2C 10.--19. 1. "PROTOCOL0_EXT_RX_EQ_CTLE_BOOST_G2,PROTOCOL0_EXT_RX_EQ_CTLE_BOOST_G2" newline hexmask.long.word 0x2C 0.--9. 1. "PROTOCOL0_EXT_RX_EQ_CTLE_BOOST_G1,PROTOCOL0_EXT_RX_EQ_CTLE_BOOST_G1" line.long 0x30 "CTRL_12,CTRL_12" newline hexmask.long.byte 0x30 8.--15. 1. "PROTOCOL0_EXT_RX_EQ_DELTA_IQ_G2,PROTOCOL0_EXT_RX_EQ_DELTA_IQ_G2" newline hexmask.long.byte 0x30 0.--7. 1. "PROTOCOL0_EXT_RX_EQ_DELTA_IQ_G1,PROTOCOL0_EXT_RX_EQ_DELTA_IQ_G1" line.long 0x34 "CTRL_13,CTRL_13" newline hexmask.long.word 0x34 8.--23. 1. "PROTOCOL0_EXT_RX_EQ_DFE_TAP1_G1,PROTOCOL0_EXT_RX_EQ_DFE_TAP1_G1" newline hexmask.long.byte 0x34 0.--7. 1. "PROTOCOL0_EXT_RX_EQ_DELTA_IQ_G3,PROTOCOL0_EXT_RX_EQ_DELTA_IQ_G3" line.long 0x38 "CTRL_14,CTRL_14" hexmask.long.word 0x38 16.--31. 1. "PROTOCOL0_EXT_RX_EQ_DFE_TAP1_G3,PROTOCOL0_EXT_RX_EQ_DFE_TAP1_G3" newline hexmask.long.word 0x38 0.--15. 1. "PROTOCOL0_EXT_RX_EQ_DFE_TAP1_G2,PROTOCOL0_EXT_RX_EQ_DFE_TAP1_G2" repeat 6. (list 0xF 0x17 0x18 0x19 0x1A 0x1B )(list 0x0 0x20 0x24 0x28 0x2C 0x30 ) group.long ($2+0x3C)++0x3 line.long 0x0 "CTRL_$1,CTRL_15" hexmask.long 0x0 0.--31. 1. "RSVD0,RSVD0" repeat.end group.long 0x40++0x1B line.long 0x0 "CTRL_16,CTRL_16" newline hexmask.long.byte 0x0 18.--23. 1. "PROTOCOL0_EXT_RX_REF_LD_VAL_G3,PROTOCOL0_EXT_RX_REF_LD_VAL_G3" newline hexmask.long.byte 0x0 12.--17. 1. "PROTOCOL0_EXT_RX_REF_LD_VAL_G2,PROTOCOL0_EXT_RX_REF_LD_VAL_G2" newline hexmask.long.byte 0x0 6.--11. 1. "PROTOCOL0_EXT_RX_REF_LD_VAL_G1,PROTOCOL0_EXT_RX_REF_LD_VAL_G1" newline hexmask.long.byte 0x0 0.--5. 1. "PROTOCOL0_EXT_RX_LOS_THRESHOLD,PROTOCOL0_EXT_RX_LOS_THRESHOLD" line.long 0x4 "CTRL_17,CTRL_17" newline hexmask.long.word 0x4 16.--28. 1. "PROTOCOL0_EXT_RX_VCO_LD_VAL_G2,PROTOCOL0_EXT_RX_VCO_LD_VAL_G2" newline hexmask.long.word 0x4 3.--15. 1. "PROTOCOL0_EXT_RX_VCO_LD_VAL_G1,PROTOCOL0_EXT_RX_VCO_LD_VAL_G1" newline bitfld.long 0x4 0.--2. "PROTOCOL0_EXT_RX_TERM_CTRL,PROTOCOL0_EXT_RX_TERM_CTRL" "0,1,2,3,4,5,6,7" line.long 0x8 "CTRL_18,CTRL_18" newline hexmask.long.byte 0x8 13.--17. 1. "PROTOCOL0_EXT_RX_VREF_CTRL,PROTOCOL0_EXT_RX_VREF_CTRL" newline hexmask.long.word 0x8 0.--12. 1. "PROTOCOL0_EXT_RX_VCO_LD_VAL_G3,PROTOCOL0_EXT_RX_VCO_LD_VAL_G3" line.long 0xC "CTRL_19,CTRL_19" newline hexmask.long.word 0xC 16.--25. 1. "PROTOCOL0_EXT_TX_EQ_MAIN_G2,PROTOCOL0_EXT_TX_EQ_MAIN_G2" newline hexmask.long.word 0xC 6.--15. 1. "PROTOCOL0_EXT_TX_EQ_MAIN_G1,PROTOCOL0_EXT_TX_EQ_MAIN_G1" newline bitfld.long 0xC 4.--5. "PROTOCOL0_EXT_TX_EQ_OVRD_G3,PROTOCOL0_EXT_TX_EQ_OVRD_G3" "0,1,2,3" newline bitfld.long 0xC 2.--3. "PROTOCOL0_EXT_TX_EQ_OVRD_G2,PROTOCOL0_EXT_TX_EQ_OVRD_G2" "0,1,2,3" newline bitfld.long 0xC 0.--1. "PROTOCOL0_EXT_TX_EQ_OVRD_G1,PROTOCOL0_EXT_TX_EQ_OVRD_G1" "0,1,2,3" line.long 0x10 "CTRL_20,CTRL_20" newline hexmask.long.byte 0x10 18.--25. 1. "PROTOCOL0_EXT_TX_EQ_POST_G2,PROTOCOL0_EXT_TX_EQ_POST_G2" newline hexmask.long.byte 0x10 10.--17. 1. "PROTOCOL0_EXT_TX_EQ_POST_G1,PROTOCOL0_EXT_TX_EQ_POST_G1" newline hexmask.long.word 0x10 0.--9. 1. "PROTOCOL0_EXT_TX_EQ_MAIN_G3,PROTOCOL0_EXT_TX_EQ_MAIN_G3" line.long 0x14 "CTRL_21,CTRL_21" hexmask.long.byte 0x14 24.--31. 1. "PROTOCOL0_EXT_TX_EQ_PRE_G3,PROTOCOL0_EXT_TX_EQ_PRE_G3" newline hexmask.long.byte 0x14 16.--23. 1. "PROTOCOL0_EXT_TX_EQ_PRE_G2,PROTOCOL0_EXT_TX_EQ_PRE_G2" newline hexmask.long.byte 0x14 8.--15. 1. "PROTOCOL0_EXT_TX_EQ_PRE_G1,PROTOCOL0_EXT_TX_EQ_PRE_G1" newline hexmask.long.byte 0x14 0.--7. 1. "PROTOCOL0_EXT_TX_EQ_POST_G3,PROTOCOL0_EXT_TX_EQ_POST_G3" line.long 0x18 "CTRL_22,CTRL_22" hexmask.long.word 0x18 16.--31. 1. "DEBUG_CTL_79_64,DEBUG_CTL_79_64" newline bitfld.long 0x18 11.--13. "PROTOCOL0_EXT_TX_VBOOST_LVL,PROTOCOL0_EXT_TX_VBOOST_LVL" "0,1,2,3,4,5,6,7" newline bitfld.long 0x18 8.--10. "PROTOCOL0_EXT_TX_TERM_CTRL,PROTOCOL0_EXT_TX_TERM_CTRL" "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x18 0.--7. 1. "PROTOCOL0_EXT_TX_IBOOST_LVL,PROTOCOL0_EXT_TX_IBOOST_LVL" rgroup.long 0x80++0x7 line.long 0x0 "STS_0,STS_0" bitfld.long 0x0 31. "PIPE_RX1_ALIGN_DETECT,RX ALIGN symbol detected for lane 1;indicates receiver detection of an Align." "0,1" newline hexmask.long.word 0x0 22.--30. 1. "PIPE_RX1_EBUFF_LOCATION,Entries in elastic buffer for lane 1.Encodes the number of entries currently in the elastic buffer." newline bitfld.long 0x0 21. "PIPE_LANE1_POWER_PRESENT,Reserved." "0,1" newline bitfld.long 0x0 19.--20. "PIPE_LANE1_DATABUSWIDTH,Bus width configuration for lane 1.This field reports the width of the data bus configured for the PHY." "0,1,2,3" newline hexmask.long.word 0x0 10.--18. 1. "PIPE_RX0_EBUFF_LOCATION,Similar to PIPE_RX1_EBUFF_LOCATION." newline bitfld.long 0x0 9. "PIPE_RX0_ALIGN_DETECT,Similar to PIPE_RX1_ALIGN_DETECT." "0,1" newline bitfld.long 0x0 8. "PIPE_LANE1_CLKACK_N,Clock acknowledge for lane 1" "0,1" newline bitfld.long 0x0 7. "PIPE_LANE0_CLKACK_N,Similar to PIPE_LANE1_CLKACK_N" "0,1" newline bitfld.long 0x0 6. "PIPE_LANE0_POWER_PRESENT,Similar to PIPE_LANE1_POWER_PRESENT" "0,1" newline bitfld.long 0x0 4.--5. "PIPE_LANE0_DATABUSWIDTH,Similar to PIPE_LANE1_DATABUSWIDTH" "0,1,2,3" newline bitfld.long 0x0 3. "PHY_ANA_PWR_STABLE,Internal PMA switch stable.Function: Stable status signal from the PMA power switch." "0,1" newline bitfld.long 0x0 2. "PHY_RTUNE_ACK,Resistor tune acknowledge.Function: Indicates that a resistor tune has completed" "0,1" newline bitfld.long 0x0 1. "PHY_MPLLB_STATE,MPLLB state indicator.Function: Indicates the state of mpllb. This signal is asserted when MPLLB is powered up and phase-locked." "0,1" newline bitfld.long 0x0 0. "PHY_MPLLA_STATE,MPLLA state indicator.Function: Indicates the state of mplla. This signal is asserted when MPLLA is powered up and phase-locked." "0,1" line.long 0x4 "STS_1,STS_1" hexmask.long 0x4 4.--31. 1. "RSVD0,RSVD0" newline bitfld.long 0x4 3. "UPCS_PWR_EN,Power enable for PCS power switch(es).Enable signal for external switch(es) to supply power to the power-gated logic in the PCS" "0,1" newline bitfld.long 0x4 2. "PHY_PCS_PWR_EN,Power enable for Raw PCS power switches.Function: Enable signal for external switches to supply power to the power gated logic in Raw PCS." "0,1" newline bitfld.long 0x4 1. "PHY_PMA_PWR_EN,Power enable for PMA power switch Function: Enable signal for PMA power switch (external) to supply power to the PMA." "0,1" newline bitfld.long 0x4 0. "PHY_SRAM_INIT_DONE,SRAM Initialization done Function: Signal indicating that the SRAM has been initialized by the boot loader in the Raw PCS.This signal will not assert if sram_bypass is asserted." "0,1" repeat 6. (list 0x2 0x3 0x4 0x5 0x6 0x7 )(list 0x0 0x4 0x8 0xC 0x10 0x14 ) rgroup.long ($2+0x88)++0x3 line.long 0x0 "STS_$1,STS_2" hexmask.long 0x0 0.--31. 1. "RSVD0,RSVD0" repeat.end tree.end endif tree.end tree "PINCTRL (I/O Pins Controller)" sif (CORENAME()=="CORTEXR5F") tree "PINCTRL_AP" base ad:0xF8500000 group.long 0x0++0x1AF line.long 0x0 "IO_PAD_CONFIG_GPIO_C0,PAD GPIO_C0 config register" bitfld.long 0x0 16. "POE,GPIO_C0 PAD Parametric output enable" "0,1" bitfld.long 0x0 12. "IS,GPIO_C0 PAD Input select" "0,1" bitfld.long 0x0 8. "SR,GPIO_C0 PAD Slew rate" "0,1" newline bitfld.long 0x0 4.--5. "DS,GPIO_C0 PAD Driver select" "0,1,2,3" bitfld.long 0x0 1. "PS,GPIO_C0 PAD Pull select" "0,1" bitfld.long 0x0 0. "PE,GPIO_C0 PAD Pull enable" "0,1" line.long 0x4 "IO_PAD_CONFIG_GPIO_C1,PAD GPIO_C1 config register" bitfld.long 0x4 16. "POE,GPIO_C1 PAD Parametric output enable" "0,1" bitfld.long 0x4 12. "IS,GPIO_C1 PAD Input select" "0,1" bitfld.long 0x4 8. "SR,GPIO_C1 PAD Slew rate" "0,1" newline bitfld.long 0x4 4.--5. "DS,GPIO_C1 PAD Driver select" "0,1,2,3" bitfld.long 0x4 1. "PS,GPIO_C1 PAD Pull select" "0,1" bitfld.long 0x4 0. "PE,GPIO_C1 PAD Pull enable" "0,1" line.long 0x8 "IO_PAD_CONFIG_GPIO_C2,PAD GPIO_C2 config register" bitfld.long 0x8 16. "POE,GPIO_C2 PAD Parametric output enable" "0,1" bitfld.long 0x8 12. "IS,GPIO_C2 PAD Input select" "0,1" bitfld.long 0x8 8. "SR,GPIO_C2 PAD Slew rate" "0,1" newline bitfld.long 0x8 4.--5. "DS,GPIO_C2 PAD Driver select" "0,1,2,3" bitfld.long 0x8 1. "PS,GPIO_C2 PAD Pull select" "0,1" bitfld.long 0x8 0. "PE,GPIO_C2 PAD Pull enable" "0,1" line.long 0xC "IO_PAD_CONFIG_GPIO_C3,PAD GPIO_C3 config register" bitfld.long 0xC 16. "POE,GPIO_C3 PAD Parametric output enable" "0,1" bitfld.long 0xC 12. "IS,GPIO_C3 PAD Input select" "0,1" bitfld.long 0xC 8. "SR,GPIO_C3 PAD Slew rate" "0,1" newline bitfld.long 0xC 4.--5. "DS,GPIO_C3 PAD Driver select" "0,1,2,3" bitfld.long 0xC 1. "PS,GPIO_C3 PAD Pull select" "0,1" bitfld.long 0xC 0. "PE,GPIO_C3 PAD Pull enable" "0,1" line.long 0x10 "IO_PAD_CONFIG_GPIO_C4,PAD GPIO_C4 config register" bitfld.long 0x10 16. "POE,GPIO_C4 PAD Parametric output enable" "0,1" bitfld.long 0x10 12. "IS,GPIO_C4 PAD Input select" "0,1" bitfld.long 0x10 8. "SR,GPIO_C4 PAD Slew rate" "0,1" newline bitfld.long 0x10 4.--5. "DS,GPIO_C4 PAD Driver select" "0,1,2,3" bitfld.long 0x10 1. "PS,GPIO_C4 PAD Pull select" "0,1" bitfld.long 0x10 0. "PE,GPIO_C4 PAD Pull enable" "0,1" line.long 0x14 "IO_PAD_CONFIG_GPIO_C5,PAD GPIO_C5 config register" bitfld.long 0x14 16. "POE,GPIO_C5 PAD Parametric output enable" "0,1" bitfld.long 0x14 12. "IS,GPIO_C5 PAD Input select" "0,1" bitfld.long 0x14 8. "SR,GPIO_C5 PAD Slew rate" "0,1" newline bitfld.long 0x14 4.--5. "DS,GPIO_C5 PAD Driver select" "0,1,2,3" bitfld.long 0x14 1. "PS,GPIO_C5 PAD Pull select" "0,1" bitfld.long 0x14 0. "PE,GPIO_C5 PAD Pull enable" "0,1" line.long 0x18 "IO_PAD_CONFIG_GPIO_C6,PAD GPIO_C6 config register" bitfld.long 0x18 16. "POE,GPIO_C6 PAD Parametric output enable" "0,1" bitfld.long 0x18 12. "IS,GPIO_C6 PAD Input select" "0,1" bitfld.long 0x18 8. "SR,GPIO_C6 PAD Slew rate" "0,1" newline bitfld.long 0x18 4.--5. "DS,GPIO_C6 PAD Driver select" "0,1,2,3" bitfld.long 0x18 1. "PS,GPIO_C6 PAD Pull select" "0,1" bitfld.long 0x18 0. "PE,GPIO_C6 PAD Pull enable" "0,1" line.long 0x1C "IO_PAD_CONFIG_GPIO_C7,PAD GPIO_C7 config register" bitfld.long 0x1C 16. "POE,GPIO_C7 PAD Parametric output enable" "0,1" bitfld.long 0x1C 12. "IS,GPIO_C7 PAD Input select" "0,1" bitfld.long 0x1C 8. "SR,GPIO_C7 PAD Slew rate" "0,1" newline bitfld.long 0x1C 4.--5. "DS,GPIO_C7 PAD Driver select" "0,1,2,3" bitfld.long 0x1C 1. "PS,GPIO_C7 PAD Pull select" "0,1" bitfld.long 0x1C 0. "PE,GPIO_C7 PAD Pull enable" "0,1" line.long 0x20 "IO_PAD_CONFIG_GPIO_C8,PAD GPIO_C8 config register" bitfld.long 0x20 16. "POE,GPIO_C8 PAD Parametric output enable" "0,1" bitfld.long 0x20 12. "IS,GPIO_C8 PAD Input select" "0,1" bitfld.long 0x20 8. "SR,GPIO_C8 PAD Slew rate" "0,1" newline bitfld.long 0x20 4.--5. "DS,GPIO_C8 PAD Driver select" "0,1,2,3" bitfld.long 0x20 1. "PS,GPIO_C8 PAD Pull select" "0,1" bitfld.long 0x20 0. "PE,GPIO_C8 PAD Pull enable" "0,1" line.long 0x24 "IO_PAD_CONFIG_GPIO_C9,PAD GPIO_C9 config register" bitfld.long 0x24 16. "POE,GPIO_C9 PAD Parametric output enable" "0,1" bitfld.long 0x24 12. "IS,GPIO_C9 PAD Input select" "0,1" bitfld.long 0x24 8. "SR,GPIO_C9 PAD Slew rate" "0,1" newline bitfld.long 0x24 4.--5. "DS,GPIO_C9 PAD Driver select" "0,1,2,3" bitfld.long 0x24 1. "PS,GPIO_C9 PAD Pull select" "0,1" bitfld.long 0x24 0. "PE,GPIO_C9 PAD Pull enable" "0,1" line.long 0x28 "IO_PAD_CONFIG_GPIO_C10,PAD GPIO_C10 config register" bitfld.long 0x28 16. "POE,GPIO_C10 PAD Parametric output enable" "0,1" bitfld.long 0x28 12. "IS,GPIO_C10 PAD Input select" "0,1" bitfld.long 0x28 8. "SR,GPIO_C10 PAD Slew rate" "0,1" newline bitfld.long 0x28 4.--5. "DS,GPIO_C10 PAD Driver select" "0,1,2,3" bitfld.long 0x28 1. "PS,GPIO_C10 PAD Pull select" "0,1" bitfld.long 0x28 0. "PE,GPIO_C10 PAD Pull enable" "0,1" line.long 0x2C "IO_PAD_CONFIG_GPIO_C11,PAD GPIO_C11 config register" bitfld.long 0x2C 16. "POE,GPIO_C11 PAD Parametric output enable" "0,1" bitfld.long 0x2C 12. "IS,GPIO_C11 PAD Input select" "0,1" bitfld.long 0x2C 8. "SR,GPIO_C11 PAD Slew rate" "0,1" newline bitfld.long 0x2C 4.--5. "DS,GPIO_C11 PAD Driver select" "0,1,2,3" bitfld.long 0x2C 1. "PS,GPIO_C11 PAD Pull select" "0,1" bitfld.long 0x2C 0. "PE,GPIO_C11 PAD Pull enable" "0,1" line.long 0x30 "IO_PAD_CONFIG_GPIO_C12,PAD GPIO_C12 config register" bitfld.long 0x30 16. "POE,GPIO_C12 PAD Parametric output enable" "0,1" bitfld.long 0x30 12. "IS,GPIO_C12 PAD Input select" "0,1" bitfld.long 0x30 8. "SR,GPIO_C12 PAD Slew rate" "0,1" newline bitfld.long 0x30 4.--5. "DS,GPIO_C12 PAD Driver select" "0,1,2,3" bitfld.long 0x30 1. "PS,GPIO_C12 PAD Pull select" "0,1" bitfld.long 0x30 0. "PE,GPIO_C12 PAD Pull enable" "0,1" line.long 0x34 "IO_PAD_CONFIG_GPIO_C13,PAD GPIO_C13 config register" bitfld.long 0x34 16. "POE,GPIO_C13 PAD Parametric output enable" "0,1" bitfld.long 0x34 12. "IS,GPIO_C13 PAD Input select" "0,1" bitfld.long 0x34 8. "SR,GPIO_C13 PAD Slew rate" "0,1" newline bitfld.long 0x34 4.--5. "DS,GPIO_C13 PAD Driver select" "0,1,2,3" bitfld.long 0x34 1. "PS,GPIO_C13 PAD Pull select" "0,1" bitfld.long 0x34 0. "PE,GPIO_C13 PAD Pull enable" "0,1" line.long 0x38 "IO_PAD_CONFIG_GPIO_C14,PAD GPIO_C14 config register" bitfld.long 0x38 16. "POE,GPIO_C14 PAD Parametric output enable" "0,1" bitfld.long 0x38 12. "IS,GPIO_C14 PAD Input select" "0,1" bitfld.long 0x38 8. "SR,GPIO_C14 PAD Slew rate" "0,1" newline bitfld.long 0x38 4.--5. "DS,GPIO_C14 PAD Driver select" "0,1,2,3" bitfld.long 0x38 1. "PS,GPIO_C14 PAD Pull select" "0,1" bitfld.long 0x38 0. "PE,GPIO_C14 PAD Pull enable" "0,1" line.long 0x3C "IO_PAD_CONFIG_GPIO_C15,PAD GPIO_C15 config register" bitfld.long 0x3C 16. "POE,GPIO_C15 PAD Parametric output enable" "0,1" bitfld.long 0x3C 12. "IS,GPIO_C15 PAD Input select" "0,1" bitfld.long 0x3C 8. "SR,GPIO_C15 PAD Slew rate" "0,1" newline bitfld.long 0x3C 4.--5. "DS,GPIO_C15 PAD Driver select" "0,1,2,3" bitfld.long 0x3C 1. "PS,GPIO_C15 PAD Pull select" "0,1" bitfld.long 0x3C 0. "PE,GPIO_C15 PAD Pull enable" "0,1" line.long 0x40 "IO_PAD_CONFIG_GPIO_D0,PAD GPIO_D0 config register" bitfld.long 0x40 16. "POE,GPIO_D0 PAD Parametric output enable" "0,1" bitfld.long 0x40 12. "IS,GPIO_D0 PAD Input select" "0,1" bitfld.long 0x40 8. "SR,GPIO_D0 PAD Slew rate" "0,1" newline bitfld.long 0x40 4.--5. "DS,GPIO_D0 PAD Driver select" "0,1,2,3" bitfld.long 0x40 1. "PS,GPIO_D0 PAD Pull select" "0,1" bitfld.long 0x40 0. "PE,GPIO_D0 PAD Pull enable" "0,1" line.long 0x44 "IO_PAD_CONFIG_GPIO_D1,PAD GPIO_D1 config register" bitfld.long 0x44 16. "POE,GPIO_D1 PAD Parametric output enable" "0,1" bitfld.long 0x44 12. "IS,GPIO_D1 PAD Input select" "0,1" bitfld.long 0x44 8. "SR,GPIO_D1 PAD Slew rate" "0,1" newline bitfld.long 0x44 4.--5. "DS,GPIO_D1 PAD Driver select" "0,1,2,3" bitfld.long 0x44 1. "PS,GPIO_D1 PAD Pull select" "0,1" bitfld.long 0x44 0. "PE,GPIO_D1 PAD Pull enable" "0,1" line.long 0x48 "IO_PAD_CONFIG_GPIO_D2,PAD GPIO_D2 config register" bitfld.long 0x48 16. "POE,GPIO_D2 PAD Parametric output enable" "0,1" bitfld.long 0x48 12. "IS,GPIO_D2 PAD Input select" "0,1" bitfld.long 0x48 8. "SR,GPIO_D2 PAD Slew rate" "0,1" newline bitfld.long 0x48 4.--5. "DS,GPIO_D2 PAD Driver select" "0,1,2,3" bitfld.long 0x48 1. "PS,GPIO_D2 PAD Pull select" "0,1" bitfld.long 0x48 0. "PE,GPIO_D2 PAD Pull enable" "0,1" line.long 0x4C "IO_PAD_CONFIG_GPIO_D3,PAD GPIO_D3 config register" bitfld.long 0x4C 16. "POE,GPIO_D3 PAD Parametric output enable" "0,1" bitfld.long 0x4C 12. "IS,GPIO_D3 PAD Input select" "0,1" bitfld.long 0x4C 8. "SR,GPIO_D3 PAD Slew rate" "0,1" newline bitfld.long 0x4C 4.--5. "DS,GPIO_D3 PAD Driver select" "0,1,2,3" bitfld.long 0x4C 1. "PS,GPIO_D3 PAD Pull select" "0,1" bitfld.long 0x4C 0. "PE,GPIO_D3 PAD Pull enable" "0,1" line.long 0x50 "IO_PAD_CONFIG_GPIO_D4,PAD GPIO_D4 config register" bitfld.long 0x50 16. "POE,GPIO_D4 PAD Parametric output enable" "0,1" bitfld.long 0x50 12. "IS,GPIO_D4 PAD Input select" "0,1" bitfld.long 0x50 8. "SR,GPIO_D4 PAD Slew rate" "0,1" newline bitfld.long 0x50 4.--5. "DS,GPIO_D4 PAD Driver select" "0,1,2,3" bitfld.long 0x50 1. "PS,GPIO_D4 PAD Pull select" "0,1" bitfld.long 0x50 0. "PE,GPIO_D4 PAD Pull enable" "0,1" line.long 0x54 "IO_PAD_CONFIG_GPIO_D5,PAD GPIO_D5 config register" bitfld.long 0x54 16. "POE,GPIO_D5 PAD Parametric output enable" "0,1" bitfld.long 0x54 12. "IS,GPIO_D5 PAD Input select" "0,1" bitfld.long 0x54 8. "SR,GPIO_D5 PAD Slew rate" "0,1" newline bitfld.long 0x54 4.--5. "DS,GPIO_D5 PAD Driver select" "0,1,2,3" bitfld.long 0x54 1. "PS,GPIO_D5 PAD Pull select" "0,1" bitfld.long 0x54 0. "PE,GPIO_D5 PAD Pull enable" "0,1" line.long 0x58 "IO_PAD_CONFIG_GPIO_D6,PAD GPIO_D6 config register" bitfld.long 0x58 16. "POE,GPIO_D6 PAD Parametric output enable" "0,1" bitfld.long 0x58 12. "IS,GPIO_D6 PAD Input select" "0,1" bitfld.long 0x58 8. "SR,GPIO_D6 PAD Slew rate" "0,1" newline bitfld.long 0x58 4.--5. "DS,GPIO_D6 PAD Driver select" "0,1,2,3" bitfld.long 0x58 1. "PS,GPIO_D6 PAD Pull select" "0,1" bitfld.long 0x58 0. "PE,GPIO_D6 PAD Pull enable" "0,1" line.long 0x5C "IO_PAD_CONFIG_GPIO_D7,PAD GPIO_D7 config register" bitfld.long 0x5C 16. "POE,GPIO_D7 PAD Parametric output enable" "0,1" bitfld.long 0x5C 12. "IS,GPIO_D7 PAD Input select" "0,1" bitfld.long 0x5C 8. "SR,GPIO_D7 PAD Slew rate" "0,1" newline bitfld.long 0x5C 4.--5. "DS,GPIO_D7 PAD Driver select" "0,1,2,3" bitfld.long 0x5C 1. "PS,GPIO_D7 PAD Pull select" "0,1" bitfld.long 0x5C 0. "PE,GPIO_D7 PAD Pull enable" "0,1" line.long 0x60 "IO_PAD_CONFIG_GPIO_D8,PAD GPIO_D8 config register" bitfld.long 0x60 16. "POE,GPIO_D8 PAD Parametric output enable" "0,1" bitfld.long 0x60 12. "IS,GPIO_D8 PAD Input select" "0,1" bitfld.long 0x60 8. "SR,GPIO_D8 PAD Slew rate" "0,1" newline bitfld.long 0x60 4.--5. "DS,GPIO_D8 PAD Driver select" "0,1,2,3" bitfld.long 0x60 1. "PS,GPIO_D8 PAD Pull select" "0,1" bitfld.long 0x60 0. "PE,GPIO_D8 PAD Pull enable" "0,1" line.long 0x64 "IO_PAD_CONFIG_GPIO_D9,PAD GPIO_D9 config register" bitfld.long 0x64 16. "POE,GPIO_D9 PAD Parametric output enable" "0,1" bitfld.long 0x64 12. "IS,GPIO_D9 PAD Input select" "0,1" bitfld.long 0x64 8. "SR,GPIO_D9 PAD Slew rate" "0,1" newline bitfld.long 0x64 4.--5. "DS,GPIO_D9 PAD Driver select" "0,1,2,3" bitfld.long 0x64 1. "PS,GPIO_D9 PAD Pull select" "0,1" bitfld.long 0x64 0. "PE,GPIO_D9 PAD Pull enable" "0,1" line.long 0x68 "IO_PAD_CONFIG_GPIO_D10,PAD GPIO_D10 config register" bitfld.long 0x68 16. "POE,GPIO_D10 PAD Parametric output enable" "0,1" bitfld.long 0x68 12. "IS,GPIO_D10 PAD Input select" "0,1" bitfld.long 0x68 8. "SR,GPIO_D10 PAD Slew rate" "0,1" newline bitfld.long 0x68 4.--5. "DS,GPIO_D10 PAD Driver select" "0,1,2,3" bitfld.long 0x68 1. "PS,GPIO_D10 PAD Pull select" "0,1" bitfld.long 0x68 0. "PE,GPIO_D10 PAD Pull enable" "0,1" line.long 0x6C "IO_PAD_CONFIG_GPIO_D11,PAD GPIO_D11 config register" bitfld.long 0x6C 16. "POE,GPIO_D11 PAD Parametric output enable" "0,1" bitfld.long 0x6C 12. "IS,GPIO_D11 PAD Input select" "0,1" bitfld.long 0x6C 8. "SR,GPIO_D11 PAD Slew rate" "0,1" newline bitfld.long 0x6C 4.--5. "DS,GPIO_D11 PAD Driver select" "0,1,2,3" bitfld.long 0x6C 1. "PS,GPIO_D11 PAD Pull select" "0,1" bitfld.long 0x6C 0. "PE,GPIO_D11 PAD Pull enable" "0,1" line.long 0x70 "IO_PAD_CONFIG_GPIO_D12,PAD GPIO_D12 config register" bitfld.long 0x70 16. "POE,GPIO_D12 PAD Parametric output enable" "0,1" bitfld.long 0x70 12. "IS,GPIO_D12 PAD Input select" "0,1" bitfld.long 0x70 8. "SR,GPIO_D12 PAD Slew rate" "0,1" newline bitfld.long 0x70 4.--5. "DS,GPIO_D12 PAD Driver select" "0,1,2,3" bitfld.long 0x70 1. "PS,GPIO_D12 PAD Pull select" "0,1" bitfld.long 0x70 0. "PE,GPIO_D12 PAD Pull enable" "0,1" line.long 0x74 "IO_PAD_CONFIG_GPIO_D13,PAD GPIO_D13 config register" bitfld.long 0x74 16. "POE,GPIO_D13 PAD Parametric output enable" "0,1" bitfld.long 0x74 12. "IS,GPIO_D13 PAD Input select" "0,1" bitfld.long 0x74 8. "SR,GPIO_D13 PAD Slew rate" "0,1" newline bitfld.long 0x74 4.--5. "DS,GPIO_D13 PAD Driver select" "0,1,2,3" bitfld.long 0x74 1. "PS,GPIO_D13 PAD Pull select" "0,1" bitfld.long 0x74 0. "PE,GPIO_D13 PAD Pull enable" "0,1" line.long 0x78 "IO_PAD_CONFIG_GPIO_D14,PAD GPIO_D14 config register" bitfld.long 0x78 16. "POE,GPIO_D14 PAD Parametric output enable" "0,1" bitfld.long 0x78 12. "IS,GPIO_D14 PAD Input select" "0,1" bitfld.long 0x78 8. "SR,GPIO_D14 PAD Slew rate" "0,1" newline bitfld.long 0x78 4.--5. "DS,GPIO_D14 PAD Driver select" "0,1,2,3" bitfld.long 0x78 1. "PS,GPIO_D14 PAD Pull select" "0,1" bitfld.long 0x78 0. "PE,GPIO_D14 PAD Pull enable" "0,1" line.long 0x7C "IO_PAD_CONFIG_GPIO_D15,PAD GPIO_D15 config register" bitfld.long 0x7C 16. "POE,GPIO_D15 PAD Parametric output enable" "0,1" bitfld.long 0x7C 12. "IS,GPIO_D15 PAD Input select" "0,1" bitfld.long 0x7C 8. "SR,GPIO_D15 PAD Slew rate" "0,1" newline bitfld.long 0x7C 4.--5. "DS,GPIO_D15 PAD Driver select" "0,1,2,3" bitfld.long 0x7C 1. "PS,GPIO_D15 PAD Pull select" "0,1" bitfld.long 0x7C 0. "PE,GPIO_D15 PAD Pull enable" "0,1" line.long 0x80 "IO_PAD_CONFIG_OSPI2_SCLK,PAD OSPI2_SCLK config register" bitfld.long 0x80 16. "POE,OSPI2_SCLK PAD Parametric output enable" "0,1" bitfld.long 0x80 12. "IS,OSPI2_SCLK PAD Input select" "0,1" bitfld.long 0x80 8. "SR,OSPI2_SCLK PAD Slew rate" "0,1" newline bitfld.long 0x80 4.--5. "DS,OSPI2_SCLK PAD Driver select" "0,1,2,3" bitfld.long 0x80 1. "PS,OSPI2_SCLK PAD Pull select" "0,1" bitfld.long 0x80 0. "PE,OSPI2_SCLK PAD Pull enable" "0,1" line.long 0x84 "IO_PAD_CONFIG_OSPI2_SS0,PAD OSPI2_SS0 config register" bitfld.long 0x84 16. "POE,OSPI2_SS0 PAD Parametric output enable" "0,1" bitfld.long 0x84 12. "IS,OSPI2_SS0 PAD Input select" "0,1" bitfld.long 0x84 8. "SR,OSPI2_SS0 PAD Slew rate" "0,1" newline bitfld.long 0x84 4.--5. "DS,OSPI2_SS0 PAD Driver select" "0,1,2,3" bitfld.long 0x84 1. "PS,OSPI2_SS0 PAD Pull select" "0,1" bitfld.long 0x84 0. "PE,OSPI2_SS0 PAD Pull enable" "0,1" line.long 0x88 "IO_PAD_CONFIG_OSPI2_DATA0,PAD OSPI2_DATA0 config register" bitfld.long 0x88 16. "POE,OSPI2_DATA0 PAD Parametric output enable" "0,1" bitfld.long 0x88 12. "IS,OSPI2_DATA0 PAD Input select" "0,1" bitfld.long 0x88 8. "SR,OSPI2_DATA0 PAD Slew rate" "0,1" newline bitfld.long 0x88 4.--5. "DS,OSPI2_DATA0 PAD Driver select" "0,1,2,3" bitfld.long 0x88 1. "PS,OSPI2_DATA0 PAD Pull select" "0,1" bitfld.long 0x88 0. "PE,OSPI2_DATA0 PAD Pull enable" "0,1" line.long 0x8C "IO_PAD_CONFIG_OSPI2_DATA1,PAD OSPI2_DATA1 config register" bitfld.long 0x8C 16. "POE,OSPI2_DATA1 PAD Parametric output enable" "0,1" bitfld.long 0x8C 12. "IS,OSPI2_DATA1 PAD Input select" "0,1" bitfld.long 0x8C 8. "SR,OSPI2_DATA1 PAD Slew rate" "0,1" newline bitfld.long 0x8C 4.--5. "DS,OSPI2_DATA1 PAD Driver select" "0,1,2,3" bitfld.long 0x8C 1. "PS,OSPI2_DATA1 PAD Pull select" "0,1" bitfld.long 0x8C 0. "PE,OSPI2_DATA1 PAD Pull enable" "0,1" line.long 0x90 "IO_PAD_CONFIG_OSPI2_DATA2,PAD OSPI2_DATA2 config register" bitfld.long 0x90 16. "POE,OSPI2_DATA2 PAD Parametric output enable" "0,1" bitfld.long 0x90 12. "IS,OSPI2_DATA2 PAD Input select" "0,1" bitfld.long 0x90 8. "SR,OSPI2_DATA2 PAD Slew rate" "0,1" newline bitfld.long 0x90 4.--5. "DS,OSPI2_DATA2 PAD Driver select" "0,1,2,3" bitfld.long 0x90 1. "PS,OSPI2_DATA2 PAD Pull select" "0,1" bitfld.long 0x90 0. "PE,OSPI2_DATA2 PAD Pull enable" "0,1" line.long 0x94 "IO_PAD_CONFIG_OSPI2_DATA3,PAD OSPI2_DATA3 config register" bitfld.long 0x94 16. "POE,OSPI2_DATA3 PAD Parametric output enable" "0,1" bitfld.long 0x94 12. "IS,OSPI2_DATA3 PAD Input select" "0,1" bitfld.long 0x94 8. "SR,OSPI2_DATA3 PAD Slew rate" "0,1" newline bitfld.long 0x94 4.--5. "DS,OSPI2_DATA3 PAD Driver select" "0,1,2,3" bitfld.long 0x94 1. "PS,OSPI2_DATA3 PAD Pull select" "0,1" bitfld.long 0x94 0. "PE,OSPI2_DATA3 PAD Pull enable" "0,1" line.long 0x98 "IO_PAD_CONFIG_OSPI2_DATA4,PAD OSPI2_DATA4 config register" bitfld.long 0x98 16. "POE,OSPI2_DATA4 PAD Parametric output enable" "0,1" bitfld.long 0x98 12. "IS,OSPI2_DATA4 PAD Input select" "0,1" bitfld.long 0x98 8. "SR,OSPI2_DATA4 PAD Slew rate" "0,1" newline bitfld.long 0x98 4.--5. "DS,OSPI2_DATA4 PAD Driver select" "0,1,2,3" bitfld.long 0x98 1. "PS,OSPI2_DATA4 PAD Pull select" "0,1" bitfld.long 0x98 0. "PE,OSPI2_DATA4 PAD Pull enable" "0,1" line.long 0x9C "IO_PAD_CONFIG_OSPI2_DATA5,PAD OSPI2_DATA5 config register" bitfld.long 0x9C 16. "POE,OSPI2_DATA5 PAD Parametric output enable" "0,1" bitfld.long 0x9C 12. "IS,OSPI2_DATA5 PAD Input select" "0,1" bitfld.long 0x9C 8. "SR,OSPI2_DATA5 PAD Slew rate" "0,1" newline bitfld.long 0x9C 4.--5. "DS,OSPI2_DATA5 PAD Driver select" "0,1,2,3" bitfld.long 0x9C 1. "PS,OSPI2_DATA5 PAD Pull select" "0,1" bitfld.long 0x9C 0. "PE,OSPI2_DATA5 PAD Pull enable" "0,1" line.long 0xA0 "IO_PAD_CONFIG_OSPI2_DATA6,PAD OSPI2_DATA6 config register" bitfld.long 0xA0 16. "POE,OSPI2_DATA6 PAD Parametric output enable" "0,1" bitfld.long 0xA0 12. "IS,OSPI2_DATA6 PAD Input select" "0,1" bitfld.long 0xA0 8. "SR,OSPI2_DATA6 PAD Slew rate" "0,1" newline bitfld.long 0xA0 4.--5. "DS,OSPI2_DATA6 PAD Driver select" "0,1,2,3" bitfld.long 0xA0 1. "PS,OSPI2_DATA6 PAD Pull select" "0,1" bitfld.long 0xA0 0. "PE,OSPI2_DATA6 PAD Pull enable" "0,1" line.long 0xA4 "IO_PAD_CONFIG_OSPI2_DATA7,PAD OSPI2_DATA7 config register" bitfld.long 0xA4 16. "POE,OSPI2_DATA7 PAD Parametric output enable" "0,1" bitfld.long 0xA4 12. "IS,OSPI2_DATA7 PAD Input select" "0,1" bitfld.long 0xA4 8. "SR,OSPI2_DATA7 PAD Slew rate" "0,1" newline bitfld.long 0xA4 4.--5. "DS,OSPI2_DATA7 PAD Driver select" "0,1,2,3" bitfld.long 0xA4 1. "PS,OSPI2_DATA7 PAD Pull select" "0,1" bitfld.long 0xA4 0. "PE,OSPI2_DATA7 PAD Pull enable" "0,1" line.long 0xA8 "IO_PAD_CONFIG_OSPI2_DQS,PAD OSPI2_DQS config register" bitfld.long 0xA8 16. "POE,OSPI2_DQS PAD Parametric output enable" "0,1" bitfld.long 0xA8 12. "IS,OSPI2_DQS PAD Input select" "0,1" bitfld.long 0xA8 8. "SR,OSPI2_DQS PAD Slew rate" "0,1" newline bitfld.long 0xA8 4.--5. "DS,OSPI2_DQS PAD Driver select" "0,1,2,3" bitfld.long 0xA8 1. "PS,OSPI2_DQS PAD Pull select" "0,1" bitfld.long 0xA8 0. "PE,OSPI2_DQS PAD Pull enable" "0,1" line.long 0xAC "IO_PAD_CONFIG_OSPI2_SS1,PAD OSPI2_SS1 config register" bitfld.long 0xAC 16. "POE,OSPI2_SS1 PAD Parametric output enable" "0,1" bitfld.long 0xAC 12. "IS,OSPI2_SS1 PAD Input select" "0,1" bitfld.long 0xAC 8. "SR,OSPI2_SS1 PAD Slew rate" "0,1" newline bitfld.long 0xAC 4.--5. "DS,OSPI2_SS1 PAD Driver select" "0,1,2,3" bitfld.long 0xAC 1. "PS,OSPI2_SS1 PAD Pull select" "0,1" bitfld.long 0xAC 0. "PE,OSPI2_SS1 PAD Pull enable" "0,1" line.long 0xB0 "IO_PAD_CONFIG_RGMII2_TXC,PAD RGMII2_TXC config register" bitfld.long 0xB0 16. "POE,RGMII2_TXC PAD Parametric output enable" "0,1" bitfld.long 0xB0 12. "IS,RGMII2_TXC PAD Input select" "0,1" bitfld.long 0xB0 8. "SR,RGMII2_TXC PAD Slew rate" "0,1" newline bitfld.long 0xB0 4.--5. "DS,RGMII2_TXC PAD Driver select" "0,1,2,3" bitfld.long 0xB0 1. "PS,RGMII2_TXC PAD Pull select" "0,1" bitfld.long 0xB0 0. "PE,RGMII2_TXC PAD Pull enable" "0,1" line.long 0xB4 "IO_PAD_CONFIG_RGMII2_TXD0,PAD RGMII2_TXD0 config register" bitfld.long 0xB4 16. "POE,RGMII2_TXD0 PAD Parametric output enable" "0,1" bitfld.long 0xB4 12. "IS,RGMII2_TXD0 PAD Input select" "0,1" bitfld.long 0xB4 8. "SR,RGMII2_TXD0 PAD Slew rate" "0,1" newline bitfld.long 0xB4 4.--5. "DS,RGMII2_TXD0 PAD Driver select" "0,1,2,3" bitfld.long 0xB4 1. "PS,RGMII2_TXD0 PAD Pull select" "0,1" bitfld.long 0xB4 0. "PE,RGMII2_TXD0 PAD Pull enable" "0,1" line.long 0xB8 "IO_PAD_CONFIG_RGMII2_TXD1,PAD RGMII2_TXD1 config register" bitfld.long 0xB8 16. "POE,RGMII2_TXD1 PAD Parametric output enable" "0,1" bitfld.long 0xB8 12. "IS,RGMII2_TXD1 PAD Input select" "0,1" bitfld.long 0xB8 8. "SR,RGMII2_TXD1 PAD Slew rate" "0,1" newline bitfld.long 0xB8 4.--5. "DS,RGMII2_TXD1 PAD Driver select" "0,1,2,3" bitfld.long 0xB8 1. "PS,RGMII2_TXD1 PAD Pull select" "0,1" bitfld.long 0xB8 0. "PE,RGMII2_TXD1 PAD Pull enable" "0,1" line.long 0xBC "IO_PAD_CONFIG_RGMII2_TXD2,PAD RGMII2_TXD2 config register" bitfld.long 0xBC 16. "POE,RGMII2_TXD2 PAD Parametric output enable" "0,1" bitfld.long 0xBC 12. "IS,RGMII2_TXD2 PAD Input select" "0,1" bitfld.long 0xBC 8. "SR,RGMII2_TXD2 PAD Slew rate" "0,1" newline bitfld.long 0xBC 4.--5. "DS,RGMII2_TXD2 PAD Driver select" "0,1,2,3" bitfld.long 0xBC 1. "PS,RGMII2_TXD2 PAD Pull select" "0,1" bitfld.long 0xBC 0. "PE,RGMII2_TXD2 PAD Pull enable" "0,1" line.long 0xC0 "IO_PAD_CONFIG_RGMII2_TXD3,PAD RGMII2_TXD3 config register" bitfld.long 0xC0 16. "POE,RGMII2_TXD3 PAD Parametric output enable" "0,1" bitfld.long 0xC0 12. "IS,RGMII2_TXD3 PAD Input select" "0,1" bitfld.long 0xC0 8. "SR,RGMII2_TXD3 PAD Slew rate" "0,1" newline bitfld.long 0xC0 4.--5. "DS,RGMII2_TXD3 PAD Driver select" "0,1,2,3" bitfld.long 0xC0 1. "PS,RGMII2_TXD3 PAD Pull select" "0,1" bitfld.long 0xC0 0. "PE,RGMII2_TXD3 PAD Pull enable" "0,1" line.long 0xC4 "IO_PAD_CONFIG_RGMII2_TX_CTL,PAD RGMII2_TX_CTL config register" bitfld.long 0xC4 16. "POE,RGMII2_TX_CTL PAD Parametric output enable" "0,1" bitfld.long 0xC4 12. "IS,RGMII2_TX_CTL PAD Input select" "0,1" bitfld.long 0xC4 8. "SR,RGMII2_TX_CTL PAD Slew rate" "0,1" newline bitfld.long 0xC4 4.--5. "DS,RGMII2_TX_CTL PAD Driver select" "0,1,2,3" bitfld.long 0xC4 1. "PS,RGMII2_TX_CTL PAD Pull select" "0,1" bitfld.long 0xC4 0. "PE,RGMII2_TX_CTL PAD Pull enable" "0,1" line.long 0xC8 "IO_PAD_CONFIG_RGMII2_RXC,PAD RGMII2_RXC config register" bitfld.long 0xC8 16. "POE,RGMII2_RXC PAD Parametric output enable" "0,1" bitfld.long 0xC8 12. "IS,RGMII2_RXC PAD Input select" "0,1" bitfld.long 0xC8 8. "SR,RGMII2_RXC PAD Slew rate" "0,1" newline bitfld.long 0xC8 4.--5. "DS,RGMII2_RXC PAD Driver select" "0,1,2,3" bitfld.long 0xC8 1. "PS,RGMII2_RXC PAD Pull select" "0,1" bitfld.long 0xC8 0. "PE,RGMII2_RXC PAD Pull enable" "0,1" line.long 0xCC "IO_PAD_CONFIG_RGMII2_RXD0,PAD RGMII2_RXD0 config register" bitfld.long 0xCC 16. "POE,RGMII2_RXD0 PAD Parametric output enable" "0,1" bitfld.long 0xCC 12. "IS,RGMII2_RXD0 PAD Input select" "0,1" bitfld.long 0xCC 8. "SR,RGMII2_RXD0 PAD Slew rate" "0,1" newline bitfld.long 0xCC 4.--5. "DS,RGMII2_RXD0 PAD Driver select" "0,1,2,3" bitfld.long 0xCC 1. "PS,RGMII2_RXD0 PAD Pull select" "0,1" bitfld.long 0xCC 0. "PE,RGMII2_RXD0 PAD Pull enable" "0,1" line.long 0xD0 "IO_PAD_CONFIG_RGMII2_RXD1,PAD RGMII2_RXD1 config register" bitfld.long 0xD0 16. "POE,RGMII2_RXD1 PAD Parametric output enable" "0,1" bitfld.long 0xD0 12. "IS,RGMII2_RXD1 PAD Input select" "0,1" bitfld.long 0xD0 8. "SR,RGMII2_RXD1 PAD Slew rate" "0,1" newline bitfld.long 0xD0 4.--5. "DS,RGMII2_RXD1 PAD Driver select" "0,1,2,3" bitfld.long 0xD0 1. "PS,RGMII2_RXD1 PAD Pull select" "0,1" bitfld.long 0xD0 0. "PE,RGMII2_RXD1 PAD Pull enable" "0,1" line.long 0xD4 "IO_PAD_CONFIG_RGMII2_RXD2,PAD RGMII2_RXD2 config register" bitfld.long 0xD4 16. "POE,RGMII2_RXD2 PAD Parametric output enable" "0,1" bitfld.long 0xD4 12. "IS,RGMII2_RXD2 PAD Input select" "0,1" bitfld.long 0xD4 8. "SR,RGMII2_RXD2 PAD Slew rate" "0,1" newline bitfld.long 0xD4 4.--5. "DS,RGMII2_RXD2 PAD Driver select" "0,1,2,3" bitfld.long 0xD4 1. "PS,RGMII2_RXD2 PAD Pull select" "0,1" bitfld.long 0xD4 0. "PE,RGMII2_RXD2 PAD Pull enable" "0,1" line.long 0xD8 "IO_PAD_CONFIG_RGMII2_RXD3,PAD RGMII2_RXD3 config register" bitfld.long 0xD8 16. "POE,RGMII2_RXD3 PAD Parametric output enable" "0,1" bitfld.long 0xD8 12. "IS,RGMII2_RXD3 PAD Input select" "0,1" bitfld.long 0xD8 8. "SR,RGMII2_RXD3 PAD Slew rate" "0,1" newline bitfld.long 0xD8 4.--5. "DS,RGMII2_RXD3 PAD Driver select" "0,1,2,3" bitfld.long 0xD8 1. "PS,RGMII2_RXD3 PAD Pull select" "0,1" bitfld.long 0xD8 0. "PE,RGMII2_RXD3 PAD Pull enable" "0,1" line.long 0xDC "IO_PAD_CONFIG_RGMII2_RX_CTL,PAD RGMII2_RX_CTL config register" bitfld.long 0xDC 16. "POE,RGMII2_RX_CTL PAD Parametric output enable" "0,1" bitfld.long 0xDC 12. "IS,RGMII2_RX_CTL PAD Input select" "0,1" bitfld.long 0xDC 8. "SR,RGMII2_RX_CTL PAD Slew rate" "0,1" newline bitfld.long 0xDC 4.--5. "DS,RGMII2_RX_CTL PAD Driver select" "0,1,2,3" bitfld.long 0xDC 1. "PS,RGMII2_RX_CTL PAD Pull select" "0,1" bitfld.long 0xDC 0. "PE,RGMII2_RX_CTL PAD Pull enable" "0,1" line.long 0xE0 "IO_PAD_CONFIG_I2S_SC3_SCK,PAD I2S_SC3_SCK config register" bitfld.long 0xE0 16. "POE,I2S_SC3_SCK PAD Parametric output enable" "0,1" bitfld.long 0xE0 12. "IS,I2S_SC3_SCK PAD Input select" "0,1" bitfld.long 0xE0 8. "SR,I2S_SC3_SCK PAD Slew rate" "0,1" newline bitfld.long 0xE0 4.--5. "DS,I2S_SC3_SCK PAD Driver select" "0,1,2,3" bitfld.long 0xE0 1. "PS,I2S_SC3_SCK PAD Pull select" "0,1" bitfld.long 0xE0 0. "PE,I2S_SC3_SCK PAD Pull enable" "0,1" line.long 0xE4 "IO_PAD_CONFIG_I2S_SC3_WS,PAD I2S_SC3_WS config register" bitfld.long 0xE4 16. "POE,I2S_SC3_WS PAD Parametric output enable" "0,1" bitfld.long 0xE4 12. "IS,I2S_SC3_WS PAD Input select" "0,1" bitfld.long 0xE4 8. "SR,I2S_SC3_WS PAD Slew rate" "0,1" newline bitfld.long 0xE4 4.--5. "DS,I2S_SC3_WS PAD Driver select" "0,1,2,3" bitfld.long 0xE4 1. "PS,I2S_SC3_WS PAD Pull select" "0,1" bitfld.long 0xE4 0. "PE,I2S_SC3_WS PAD Pull enable" "0,1" line.long 0xE8 "IO_PAD_CONFIG_I2S_SC3_SD,PAD I2S_SC3_SD config register" bitfld.long 0xE8 16. "POE,I2S_SC3_SD PAD Parametric output enable" "0,1" bitfld.long 0xE8 12. "IS,I2S_SC3_SD PAD Input select" "0,1" bitfld.long 0xE8 8. "SR,I2S_SC3_SD PAD Slew rate" "0,1" newline bitfld.long 0xE8 4.--5. "DS,I2S_SC3_SD PAD Driver select" "0,1,2,3" bitfld.long 0xE8 1. "PS,I2S_SC3_SD PAD Pull select" "0,1" bitfld.long 0xE8 0. "PE,I2S_SC3_SD PAD Pull enable" "0,1" line.long 0xEC "IO_PAD_CONFIG_I2S_SC4_SCK,PAD I2S_SC4_SCK config register" bitfld.long 0xEC 16. "POE,I2S_SC4_SCK PAD Parametric output enable" "0,1" bitfld.long 0xEC 12. "IS,I2S_SC4_SCK PAD Input select" "0,1" bitfld.long 0xEC 8. "SR,I2S_SC4_SCK PAD Slew rate" "0,1" newline bitfld.long 0xEC 4.--5. "DS,I2S_SC4_SCK PAD Driver select" "0,1,2,3" bitfld.long 0xEC 1. "PS,I2S_SC4_SCK PAD Pull select" "0,1" bitfld.long 0xEC 0. "PE,I2S_SC4_SCK PAD Pull enable" "0,1" line.long 0xF0 "IO_PAD_CONFIG_I2S_SC4_WS,PAD I2S_SC4_WS config register" bitfld.long 0xF0 16. "POE,I2S_SC4_WS PAD Parametric output enable" "0,1" bitfld.long 0xF0 12. "IS,I2S_SC4_WS PAD Input select" "0,1" bitfld.long 0xF0 8. "SR,I2S_SC4_WS PAD Slew rate" "0,1" newline bitfld.long 0xF0 4.--5. "DS,I2S_SC4_WS PAD Driver select" "0,1,2,3" bitfld.long 0xF0 1. "PS,I2S_SC4_WS PAD Pull select" "0,1" bitfld.long 0xF0 0. "PE,I2S_SC4_WS PAD Pull enable" "0,1" line.long 0xF4 "IO_PAD_CONFIG_I2S_SC4_SD,PAD I2S_SC4_SD config register" bitfld.long 0xF4 16. "POE,I2S_SC4_SD PAD Parametric output enable" "0,1" bitfld.long 0xF4 12. "IS,I2S_SC4_SD PAD Input select" "0,1" bitfld.long 0xF4 8. "SR,I2S_SC4_SD PAD Slew rate" "0,1" newline bitfld.long 0xF4 4.--5. "DS,I2S_SC4_SD PAD Driver select" "0,1,2,3" bitfld.long 0xF4 1. "PS,I2S_SC4_SD PAD Pull select" "0,1" bitfld.long 0xF4 0. "PE,I2S_SC4_SD PAD Pull enable" "0,1" line.long 0xF8 "IO_PAD_CONFIG_I2S_SC5_SCK,PAD I2S_SC5_SCK config register" bitfld.long 0xF8 16. "POE,I2S_SC5_SCK PAD Parametric output enable" "0,1" bitfld.long 0xF8 12. "IS,I2S_SC5_SCK PAD Input select" "0,1" bitfld.long 0xF8 8. "SR,I2S_SC5_SCK PAD Slew rate" "0,1" newline bitfld.long 0xF8 4.--5. "DS,I2S_SC5_SCK PAD Driver select" "0,1,2,3" bitfld.long 0xF8 1. "PS,I2S_SC5_SCK PAD Pull select" "0,1" bitfld.long 0xF8 0. "PE,I2S_SC5_SCK PAD Pull enable" "0,1" line.long 0xFC "IO_PAD_CONFIG_I2S_SC5_WS,PAD I2S_SC5_WS config register" bitfld.long 0xFC 16. "POE,I2S_SC5_WS PAD Parametric output enable" "0,1" bitfld.long 0xFC 12. "IS,I2S_SC5_WS PAD Input select" "0,1" bitfld.long 0xFC 8. "SR,I2S_SC5_WS PAD Slew rate" "0,1" newline bitfld.long 0xFC 4.--5. "DS,I2S_SC5_WS PAD Driver select" "0,1,2,3" bitfld.long 0xFC 1. "PS,I2S_SC5_WS PAD Pull select" "0,1" bitfld.long 0xFC 0. "PE,I2S_SC5_WS PAD Pull enable" "0,1" line.long 0x100 "IO_PAD_CONFIG_I2S_SC5_SD,PAD I2S_SC5_SD config register" bitfld.long 0x100 16. "POE,I2S_SC5_SD PAD Parametric output enable" "0,1" bitfld.long 0x100 12. "IS,I2S_SC5_SD PAD Input select" "0,1" bitfld.long 0x100 8. "SR,I2S_SC5_SD PAD Slew rate" "0,1" newline bitfld.long 0x100 4.--5. "DS,I2S_SC5_SD PAD Driver select" "0,1,2,3" bitfld.long 0x100 1. "PS,I2S_SC5_SD PAD Pull select" "0,1" bitfld.long 0x100 0. "PE,I2S_SC5_SD PAD Pull enable" "0,1" line.long 0x104 "IO_PAD_CONFIG_I2S_SC6_SCK,PAD I2S_SC6_SCK config register" bitfld.long 0x104 16. "POE,I2S_SC6_SCK PAD Parametric output enable" "0,1" bitfld.long 0x104 12. "IS,I2S_SC6_SCK PAD Input select" "0,1" bitfld.long 0x104 8. "SR,I2S_SC6_SCK PAD Slew rate" "0,1" newline bitfld.long 0x104 4.--5. "DS,I2S_SC6_SCK PAD Driver select" "0,1,2,3" bitfld.long 0x104 1. "PS,I2S_SC6_SCK PAD Pull select" "0,1" bitfld.long 0x104 0. "PE,I2S_SC6_SCK PAD Pull enable" "0,1" line.long 0x108 "IO_PAD_CONFIG_I2S_SC6_WS,PAD I2S_SC6_WS config register" bitfld.long 0x108 16. "POE,I2S_SC6_WS PAD Parametric output enable" "0,1" bitfld.long 0x108 12. "IS,I2S_SC6_WS PAD Input select" "0,1" bitfld.long 0x108 8. "SR,I2S_SC6_WS PAD Slew rate" "0,1" newline bitfld.long 0x108 4.--5. "DS,I2S_SC6_WS PAD Driver select" "0,1,2,3" bitfld.long 0x108 1. "PS,I2S_SC6_WS PAD Pull select" "0,1" bitfld.long 0x108 0. "PE,I2S_SC6_WS PAD Pull enable" "0,1" line.long 0x10C "IO_PAD_CONFIG_I2S_SC6_SD,PAD I2S_SC6_SD config register" bitfld.long 0x10C 16. "POE,I2S_SC6_SD PAD Parametric output enable" "0,1" bitfld.long 0x10C 12. "IS,I2S_SC6_SD PAD Input select" "0,1" bitfld.long 0x10C 8. "SR,I2S_SC6_SD PAD Slew rate" "0,1" newline bitfld.long 0x10C 4.--5. "DS,I2S_SC6_SD PAD Driver select" "0,1,2,3" bitfld.long 0x10C 1. "PS,I2S_SC6_SD PAD Pull select" "0,1" bitfld.long 0x10C 0. "PE,I2S_SC6_SD PAD Pull enable" "0,1" line.long 0x110 "IO_PAD_CONFIG_I2S_SC7_SCK,PAD I2S_SC7_SCK config register" bitfld.long 0x110 16. "POE,I2S_SC7_SCK PAD Parametric output enable" "0,1" bitfld.long 0x110 12. "IS,I2S_SC7_SCK PAD Input select" "0,1" bitfld.long 0x110 8. "SR,I2S_SC7_SCK PAD Slew rate" "0,1" newline bitfld.long 0x110 4.--5. "DS,I2S_SC7_SCK PAD Driver select" "0,1,2,3" bitfld.long 0x110 1. "PS,I2S_SC7_SCK PAD Pull select" "0,1" bitfld.long 0x110 0. "PE,I2S_SC7_SCK PAD Pull enable" "0,1" line.long 0x114 "IO_PAD_CONFIG_I2S_SC7_WS,PAD I2S_SC7_WS config register" bitfld.long 0x114 16. "POE,I2S_SC7_WS PAD Parametric output enable" "0,1" bitfld.long 0x114 12. "IS,I2S_SC7_WS PAD Input select" "0,1" bitfld.long 0x114 8. "SR,I2S_SC7_WS PAD Slew rate" "0,1" newline bitfld.long 0x114 4.--5. "DS,I2S_SC7_WS PAD Driver select" "0,1,2,3" bitfld.long 0x114 1. "PS,I2S_SC7_WS PAD Pull select" "0,1" bitfld.long 0x114 0. "PE,I2S_SC7_WS PAD Pull enable" "0,1" line.long 0x118 "IO_PAD_CONFIG_I2S_SC7_SD,PAD I2S_SC7_SD config register" bitfld.long 0x118 16. "POE,I2S_SC7_SD PAD Parametric output enable" "0,1" bitfld.long 0x118 12. "IS,I2S_SC7_SD PAD Input select" "0,1" bitfld.long 0x118 8. "SR,I2S_SC7_SD PAD Slew rate" "0,1" newline bitfld.long 0x118 4.--5. "DS,I2S_SC7_SD PAD Driver select" "0,1,2,3" bitfld.long 0x118 1. "PS,I2S_SC7_SD PAD Pull select" "0,1" bitfld.long 0x118 0. "PE,I2S_SC7_SD PAD Pull enable" "0,1" line.long 0x11C "IO_PAD_CONFIG_I2S_SC8_SCK,PAD I2S_SC8_SCK config register" bitfld.long 0x11C 16. "POE,I2S_SC8_SCK PAD Parametric output enable" "0,1" bitfld.long 0x11C 12. "IS,I2S_SC8_SCK PAD Input select" "0,1" bitfld.long 0x11C 8. "SR,I2S_SC8_SCK PAD Slew rate" "0,1" newline bitfld.long 0x11C 4.--5. "DS,I2S_SC8_SCK PAD Driver select" "0,1,2,3" bitfld.long 0x11C 1. "PS,I2S_SC8_SCK PAD Pull select" "0,1" bitfld.long 0x11C 0. "PE,I2S_SC8_SCK PAD Pull enable" "0,1" line.long 0x120 "IO_PAD_CONFIG_I2S_SC8_WS,PAD I2S_SC8_WS config register" bitfld.long 0x120 16. "POE,I2S_SC8_WS PAD Parametric output enable" "0,1" bitfld.long 0x120 12. "IS,I2S_SC8_WS PAD Input select" "0,1" bitfld.long 0x120 8. "SR,I2S_SC8_WS PAD Slew rate" "0,1" newline bitfld.long 0x120 4.--5. "DS,I2S_SC8_WS PAD Driver select" "0,1,2,3" bitfld.long 0x120 1. "PS,I2S_SC8_WS PAD Pull select" "0,1" bitfld.long 0x120 0. "PE,I2S_SC8_WS PAD Pull enable" "0,1" line.long 0x124 "IO_PAD_CONFIG_I2S_SC8_SD,PAD I2S_SC8_SD config register" bitfld.long 0x124 16. "POE,I2S_SC8_SD PAD Parametric output enable" "0,1" bitfld.long 0x124 12. "IS,I2S_SC8_SD PAD Input select" "0,1" bitfld.long 0x124 8. "SR,I2S_SC8_SD PAD Slew rate" "0,1" newline bitfld.long 0x124 4.--5. "DS,I2S_SC8_SD PAD Driver select" "0,1,2,3" bitfld.long 0x124 1. "PS,I2S_SC8_SD PAD Pull select" "0,1" bitfld.long 0x124 0. "PE,I2S_SC8_SD PAD Pull enable" "0,1" line.long 0x128 "IO_PAD_CONFIG_I2S_MC_SCK,PAD I2S_MC_SCK config register" bitfld.long 0x128 16. "POE,I2S_MC_SCK PAD Parametric output enable" "0,1" bitfld.long 0x128 12. "IS,I2S_MC_SCK PAD Input select" "0,1" bitfld.long 0x128 8. "SR,I2S_MC_SCK PAD Slew rate" "0,1" newline bitfld.long 0x128 4.--5. "DS,I2S_MC_SCK PAD Driver select" "0,1,2,3" bitfld.long 0x128 1. "PS,I2S_MC_SCK PAD Pull select" "0,1" bitfld.long 0x128 0. "PE,I2S_MC_SCK PAD Pull enable" "0,1" line.long 0x12C "IO_PAD_CONFIG_I2S_MC_WS,PAD I2S_MC_WS config register" bitfld.long 0x12C 16. "POE,I2S_MC_WS PAD Parametric output enable" "0,1" bitfld.long 0x12C 12. "IS,I2S_MC_WS PAD Input select" "0,1" bitfld.long 0x12C 8. "SR,I2S_MC_WS PAD Slew rate" "0,1" newline bitfld.long 0x12C 4.--5. "DS,I2S_MC_WS PAD Driver select" "0,1,2,3" bitfld.long 0x12C 1. "PS,I2S_MC_WS PAD Pull select" "0,1" bitfld.long 0x12C 0. "PE,I2S_MC_WS PAD Pull enable" "0,1" line.long 0x130 "IO_PAD_CONFIG_I2S_MC_SD0,PAD I2S_MC_SD0 config register" bitfld.long 0x130 16. "POE,I2S_MC_SD0 PAD Parametric output enable" "0,1" bitfld.long 0x130 12. "IS,I2S_MC_SD0 PAD Input select" "0,1" bitfld.long 0x130 8. "SR,I2S_MC_SD0 PAD Slew rate" "0,1" newline bitfld.long 0x130 4.--5. "DS,I2S_MC_SD0 PAD Driver select" "0,1,2,3" bitfld.long 0x130 1. "PS,I2S_MC_SD0 PAD Pull select" "0,1" bitfld.long 0x130 0. "PE,I2S_MC_SD0 PAD Pull enable" "0,1" line.long 0x134 "IO_PAD_CONFIG_I2S_MC_SD1,PAD I2S_MC_SD1 config register" bitfld.long 0x134 16. "POE,I2S_MC_SD1 PAD Parametric output enable" "0,1" bitfld.long 0x134 12. "IS,I2S_MC_SD1 PAD Input select" "0,1" bitfld.long 0x134 8. "SR,I2S_MC_SD1 PAD Slew rate" "0,1" newline bitfld.long 0x134 4.--5. "DS,I2S_MC_SD1 PAD Driver select" "0,1,2,3" bitfld.long 0x134 1. "PS,I2S_MC_SD1 PAD Pull select" "0,1" bitfld.long 0x134 0. "PE,I2S_MC_SD1 PAD Pull enable" "0,1" line.long 0x138 "IO_PAD_CONFIG_I2S_MC_SD2,PAD I2S_MC_SD2 config register" bitfld.long 0x138 16. "POE,I2S_MC_SD2 PAD Parametric output enable" "0,1" bitfld.long 0x138 12. "IS,I2S_MC_SD2 PAD Input select" "0,1" bitfld.long 0x138 8. "SR,I2S_MC_SD2 PAD Slew rate" "0,1" newline bitfld.long 0x138 4.--5. "DS,I2S_MC_SD2 PAD Driver select" "0,1,2,3" bitfld.long 0x138 1. "PS,I2S_MC_SD2 PAD Pull select" "0,1" bitfld.long 0x138 0. "PE,I2S_MC_SD2 PAD Pull enable" "0,1" line.long 0x13C "IO_PAD_CONFIG_I2S_MC_SD3,PAD I2S_MC_SD3 config register" bitfld.long 0x13C 16. "POE,I2S_MC_SD3 PAD Parametric output enable" "0,1" bitfld.long 0x13C 12. "IS,I2S_MC_SD3 PAD Input select" "0,1" bitfld.long 0x13C 8. "SR,I2S_MC_SD3 PAD Slew rate" "0,1" newline bitfld.long 0x13C 4.--5. "DS,I2S_MC_SD3 PAD Driver select" "0,1,2,3" bitfld.long 0x13C 1. "PS,I2S_MC_SD3 PAD Pull select" "0,1" bitfld.long 0x13C 0. "PE,I2S_MC_SD3 PAD Pull enable" "0,1" line.long 0x140 "IO_PAD_CONFIG_I2S_MC_SD4,PAD I2S_MC_SD4 config register" bitfld.long 0x140 16. "POE,I2S_MC_SD4 PAD Parametric output enable" "0,1" bitfld.long 0x140 12. "IS,I2S_MC_SD4 PAD Input select" "0,1" bitfld.long 0x140 8. "SR,I2S_MC_SD4 PAD Slew rate" "0,1" newline bitfld.long 0x140 4.--5. "DS,I2S_MC_SD4 PAD Driver select" "0,1,2,3" bitfld.long 0x140 1. "PS,I2S_MC_SD4 PAD Pull select" "0,1" bitfld.long 0x140 0. "PE,I2S_MC_SD4 PAD Pull enable" "0,1" line.long 0x144 "IO_PAD_CONFIG_I2S_MC_SD5,PAD I2S_MC_SD5 config register" bitfld.long 0x144 16. "POE,I2S_MC_SD5 PAD Parametric output enable" "0,1" bitfld.long 0x144 12. "IS,I2S_MC_SD5 PAD Input select" "0,1" bitfld.long 0x144 8. "SR,I2S_MC_SD5 PAD Slew rate" "0,1" newline bitfld.long 0x144 4.--5. "DS,I2S_MC_SD5 PAD Driver select" "0,1,2,3" bitfld.long 0x144 1. "PS,I2S_MC_SD5 PAD Pull select" "0,1" bitfld.long 0x144 0. "PE,I2S_MC_SD5 PAD Pull enable" "0,1" line.long 0x148 "IO_PAD_CONFIG_I2S_MC_SD6,PAD I2S_MC_SD6 config register" bitfld.long 0x148 16. "POE,I2S_MC_SD6 PAD Parametric output enable" "0,1" bitfld.long 0x148 12. "IS,I2S_MC_SD6 PAD Input select" "0,1" bitfld.long 0x148 8. "SR,I2S_MC_SD6 PAD Slew rate" "0,1" newline bitfld.long 0x148 4.--5. "DS,I2S_MC_SD6 PAD Driver select" "0,1,2,3" bitfld.long 0x148 1. "PS,I2S_MC_SD6 PAD Pull select" "0,1" bitfld.long 0x148 0. "PE,I2S_MC_SD6 PAD Pull enable" "0,1" line.long 0x14C "IO_PAD_CONFIG_I2S_MC_SD7,PAD I2S_MC_SD7 config register" bitfld.long 0x14C 16. "POE,I2S_MC_SD7 PAD Parametric output enable" "0,1" bitfld.long 0x14C 12. "IS,I2S_MC_SD7 PAD Input select" "0,1" bitfld.long 0x14C 8. "SR,I2S_MC_SD7 PAD Slew rate" "0,1" newline bitfld.long 0x14C 4.--5. "DS,I2S_MC_SD7 PAD Driver select" "0,1,2,3" bitfld.long 0x14C 1. "PS,I2S_MC_SD7 PAD Pull select" "0,1" bitfld.long 0x14C 0. "PE,I2S_MC_SD7 PAD Pull enable" "0,1" line.long 0x150 "IO_PAD_CONFIG_EMMC1_CLK,PAD EMMC1_CLK config register" hexmask.long.byte 0x150 20.--23. 1. "SP,EMMC1_CLK PAD Drive Strength for P" hexmask.long.byte 0x150 16.--19. 1. "SN,EMMC1_CLK PAD Drive Strength for N" bitfld.long 0x150 12.--14. "RXSEL,EMMC1_CLK PAD Input Select" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x150 8.--11. 1. "TXPREP,EMMC1_CLK PAD Slew-Rate control for P" newline hexmask.long.byte 0x150 4.--7. 1. "TXPREN,EMMC1_CLK PAD Slew-Rate control for N" bitfld.long 0x150 0.--1. "PULL_EN,EMMC1_CLK PAD Pull Enable. 0: OFF; 1: PU; 2: PD; 3: RESERVED." "OFF;,PU;,PD;,RESERVED" line.long 0x154 "IO_PAD_CONFIG_EMMC1_CMD,PAD EMMC1_CMD config register" hexmask.long.byte 0x154 20.--23. 1. "SP,EMMC1_CMD PAD Drive Strength for P" hexmask.long.byte 0x154 16.--19. 1. "SN,EMMC1_CMD PAD Drive Strength for N" bitfld.long 0x154 12.--14. "RXSEL,EMMC1_CMD PAD Input Select" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x154 8.--11. 1. "TXPREP,EMMC1_CMD PAD Slew-Rate control for P" newline hexmask.long.byte 0x154 4.--7. 1. "TXPREN,EMMC1_CMD PAD Slew-Rate control for N" bitfld.long 0x154 0.--1. "PULL_EN,EMMC1_CMD PAD Pull Enable. 0: OFF; 1: PU; 2: PD; 3: RESERVED." "OFF;,PU;,PD;,RESERVED" line.long 0x158 "IO_PAD_CONFIG_EMMC1_DATA0,PAD EMMC1_DATA0 config register" hexmask.long.byte 0x158 20.--23. 1. "SP,EMMC1_DATA0 PAD Drive Strength for P" hexmask.long.byte 0x158 16.--19. 1. "SN,EMMC1_DATA0 PAD Drive Strength for N" bitfld.long 0x158 12.--14. "RXSEL,EMMC1_DATA0 PAD Input Select" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x158 8.--11. 1. "TXPREP,EMMC1_DATA0 PAD Slew-Rate control for P" newline hexmask.long.byte 0x158 4.--7. 1. "TXPREN,EMMC1_DATA0 PAD Slew-Rate control for N" bitfld.long 0x158 0.--1. "PULL_EN,EMMC1_DATA0 PAD Pull Enable. 0: OFF; 1: PU; 2: PD; 3: RESERVED." "OFF;,PU;,PD;,RESERVED" line.long 0x15C "IO_PAD_CONFIG_EMMC1_DATA1,PAD EMMC1_DATA1 config register" hexmask.long.byte 0x15C 20.--23. 1. "SP,EMMC1_DATA1 PAD Drive Strength for P" hexmask.long.byte 0x15C 16.--19. 1. "SN,EMMC1_DATA1 PAD Drive Strength for N" bitfld.long 0x15C 12.--14. "RXSEL,EMMC1_DATA1 PAD Input Select" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x15C 8.--11. 1. "TXPREP,EMMC1_DATA1 PAD Slew-Rate control for P" newline hexmask.long.byte 0x15C 4.--7. 1. "TXPREN,EMMC1_DATA1 PAD Slew-Rate control for N" bitfld.long 0x15C 0.--1. "PULL_EN,EMMC1_DATA1 PAD Pull Enable. 0: OFF; 1: PU; 2: PD; 3: RESERVED." "OFF;,PU;,PD;,RESERVED" line.long 0x160 "IO_PAD_CONFIG_EMMC1_DATA2,PAD EMMC1_DATA2 config register" hexmask.long.byte 0x160 20.--23. 1. "SP,EMMC1_DATA2 PAD Drive Strength for P" hexmask.long.byte 0x160 16.--19. 1. "SN,EMMC1_DATA2 PAD Drive Strength for N" bitfld.long 0x160 12.--14. "RXSEL,EMMC1_DATA2 PAD Input Select" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x160 8.--11. 1. "TXPREP,EMMC1_DATA2 PAD Slew-Rate control for P" newline hexmask.long.byte 0x160 4.--7. 1. "TXPREN,EMMC1_DATA2 PAD Slew-Rate control for N" bitfld.long 0x160 0.--1. "PULL_EN,EMMC1_DATA2 PAD Pull Enable. 0: OFF; 1: PU; 2: PD; 3: RESERVED." "OFF;,PU;,PD;,RESERVED" line.long 0x164 "IO_PAD_CONFIG_EMMC1_DATA3,PAD EMMC1_DATA3 config register" hexmask.long.byte 0x164 20.--23. 1. "SP,EMMC1_DATA3 PAD Drive Strength for P" hexmask.long.byte 0x164 16.--19. 1. "SN,EMMC1_DATA3 PAD Drive Strength for N" bitfld.long 0x164 12.--14. "RXSEL,EMMC1_DATA3 PAD Input Select" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x164 8.--11. 1. "TXPREP,EMMC1_DATA3 PAD Slew-Rate control for P" newline hexmask.long.byte 0x164 4.--7. 1. "TXPREN,EMMC1_DATA3 PAD Slew-Rate control for N" bitfld.long 0x164 0.--1. "PULL_EN,EMMC1_DATA3 PAD Pull Enable. 0: OFF; 1: PU; 2: PD; 3: RESERVED." "OFF;,PU;,PD;,RESERVED" line.long 0x168 "IO_PAD_CONFIG_EMMC1_DATA4,PAD EMMC1_DATA4 config register" hexmask.long.byte 0x168 20.--23. 1. "SP,EMMC1_DATA4 PAD Drive Strength for P" hexmask.long.byte 0x168 16.--19. 1. "SN,EMMC1_DATA4 PAD Drive Strength for N" bitfld.long 0x168 12.--14. "RXSEL,EMMC1_DATA4 PAD Input Select" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x168 8.--11. 1. "TXPREP,EMMC1_DATA4 PAD Slew-Rate control for P" newline hexmask.long.byte 0x168 4.--7. 1. "TXPREN,EMMC1_DATA4 PAD Slew-Rate control for N" bitfld.long 0x168 0.--1. "PULL_EN,EMMC1_DATA4 PAD Pull Enable. 0: OFF; 1: PU; 2: PD; 3: RESERVED." "OFF;,PU;,PD;,RESERVED" line.long 0x16C "IO_PAD_CONFIG_EMMC1_DATA5,PAD EMMC1_DATA5 config register" hexmask.long.byte 0x16C 20.--23. 1. "SP,EMMC1_DATA5 PAD Drive Strength for P" hexmask.long.byte 0x16C 16.--19. 1. "SN,EMMC1_DATA5 PAD Drive Strength for N" bitfld.long 0x16C 12.--14. "RXSEL,EMMC1_DATA5 PAD Input Select" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x16C 8.--11. 1. "TXPREP,EMMC1_DATA5 PAD Slew-Rate control for P" newline hexmask.long.byte 0x16C 4.--7. 1. "TXPREN,EMMC1_DATA5 PAD Slew-Rate control for N" bitfld.long 0x16C 0.--1. "PULL_EN,EMMC1_DATA5 PAD Pull Enable. 0: OFF; 1: PU; 2: PD; 3: RESERVED." "OFF;,PU;,PD;,RESERVED" line.long 0x170 "IO_PAD_CONFIG_EMMC1_DATA6,PAD EMMC1_DATA6 config register" hexmask.long.byte 0x170 20.--23. 1. "SP,EMMC1_DATA6 PAD Drive Strength for P" hexmask.long.byte 0x170 16.--19. 1. "SN,EMMC1_DATA6 PAD Drive Strength for N" bitfld.long 0x170 12.--14. "RXSEL,EMMC1_DATA6 PAD Input Select" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x170 8.--11. 1. "TXPREP,EMMC1_DATA6 PAD Slew-Rate control for P" newline hexmask.long.byte 0x170 4.--7. 1. "TXPREN,EMMC1_DATA6 PAD Slew-Rate control for N" bitfld.long 0x170 0.--1. "PULL_EN,EMMC1_DATA6 PAD Pull Enable. 0: OFF; 1: PU; 2: PD; 3: RESERVED." "OFF;,PU;,PD;,RESERVED" line.long 0x174 "IO_PAD_CONFIG_EMMC1_DATA7,PAD EMMC1_DATA7 config register" hexmask.long.byte 0x174 20.--23. 1. "SP,EMMC1_DATA7 PAD Drive Strength for P" hexmask.long.byte 0x174 16.--19. 1. "SN,EMMC1_DATA7 PAD Drive Strength for N" bitfld.long 0x174 12.--14. "RXSEL,EMMC1_DATA7 PAD Input Select" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x174 8.--11. 1. "TXPREP,EMMC1_DATA7 PAD Slew-Rate control for P" newline hexmask.long.byte 0x174 4.--7. 1. "TXPREN,EMMC1_DATA7 PAD Slew-Rate control for N" bitfld.long 0x174 0.--1. "PULL_EN,EMMC1_DATA7 PAD Pull Enable. 0: OFF; 1: PU; 2: PD; 3: RESERVED." "OFF;,PU;,PD;,RESERVED" line.long 0x178 "IO_PAD_CONFIG_EMMC1_STROBE,PAD EMMC1_STROBE config register" hexmask.long.byte 0x178 20.--23. 1. "SP,EMMC1_STROBE PAD Drive Strength for P" hexmask.long.byte 0x178 16.--19. 1. "SN,EMMC1_STROBE PAD Drive Strength for N" bitfld.long 0x178 12.--14. "RXSEL,EMMC1_STROBE PAD Input Select" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x178 8.--11. 1. "TXPREP,EMMC1_STROBE PAD Slew-Rate control for P" newline hexmask.long.byte 0x178 4.--7. 1. "TXPREN,EMMC1_STROBE PAD Slew-Rate control for N" bitfld.long 0x178 0.--1. "PULL_EN,EMMC1_STROBE PAD Pull Enable. 0: OFF; 1: PU; 2: PD; 3: RESERVED." "OFF;,PU;,PD;,RESERVED" line.long 0x17C "IO_PAD_CONFIG_EMMC1_RESET_N,PAD EMMC1_RESET_N config register" hexmask.long.byte 0x17C 20.--23. 1. "SP,EMMC1_RESET_N PAD Drive Strength for P" hexmask.long.byte 0x17C 16.--19. 1. "SN,EMMC1_RESET_N PAD Drive Strength for N" bitfld.long 0x17C 12.--14. "RXSEL,EMMC1_RESET_N PAD Input Select" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x17C 8.--11. 1. "TXPREP,EMMC1_RESET_N PAD Slew-Rate control for P" newline hexmask.long.byte 0x17C 4.--7. 1. "TXPREN,EMMC1_RESET_N PAD Slew-Rate control for N" bitfld.long 0x17C 0.--1. "PULL_EN,EMMC1_RESET_N PAD Pull Enable. 0: OFF; 1: PU; 2: PD; 3: RESERVED." "OFF;,PU;,PD;,RESERVED" line.long 0x180 "IO_PAD_CONFIG_EMMC2_CLK,PAD EMMC2_CLK config register" hexmask.long.byte 0x180 20.--23. 1. "SP,EMMC2_CLK PAD Drive Strength for P" hexmask.long.byte 0x180 16.--19. 1. "SN,EMMC2_CLK PAD Drive Strength for N" bitfld.long 0x180 12.--14. "RXSEL,EMMC2_CLK PAD Input Select" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x180 8.--11. 1. "TXPREP,EMMC2_CLK PAD Slew-Rate control for P" newline hexmask.long.byte 0x180 4.--7. 1. "TXPREN,EMMC2_CLK PAD Slew-Rate control for N" bitfld.long 0x180 0.--1. "PULL_EN,EMMC2_CLK PAD Pull Enable. 0: OFF; 1: PU; 2: PD; 3: RESERVED." "OFF;,PU;,PD;,RESERVED" line.long 0x184 "IO_PAD_CONFIG_EMMC2_CMD,PAD EMMC2_CMD config register" hexmask.long.byte 0x184 20.--23. 1. "SP,EMMC2_CMD PAD Drive Strength for P" hexmask.long.byte 0x184 16.--19. 1. "SN,EMMC2_CMD PAD Drive Strength for N" bitfld.long 0x184 12.--14. "RXSEL,EMMC2_CMD PAD Input Select" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x184 8.--11. 1. "TXPREP,EMMC2_CMD PAD Slew-Rate control for P" newline hexmask.long.byte 0x184 4.--7. 1. "TXPREN,EMMC2_CMD PAD Slew-Rate control for N" bitfld.long 0x184 0.--1. "PULL_EN,EMMC2_CMD PAD Pull Enable. 0: OFF; 1: PU; 2: PD; 3: RESERVED." "OFF;,PU;,PD;,RESERVED" line.long 0x188 "IO_PAD_CONFIG_EMMC2_DATA0,PAD EMMC2_DATA0 config register" hexmask.long.byte 0x188 20.--23. 1. "SP,EMMC2_DATA0 PAD Drive Strength for P" hexmask.long.byte 0x188 16.--19. 1. "SN,EMMC2_DATA0 PAD Drive Strength for N" bitfld.long 0x188 12.--14. "RXSEL,EMMC2_DATA0 PAD Input Select" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x188 8.--11. 1. "TXPREP,EMMC2_DATA0 PAD Slew-Rate control for P" newline hexmask.long.byte 0x188 4.--7. 1. "TXPREN,EMMC2_DATA0 PAD Slew-Rate control for N" bitfld.long 0x188 0.--1. "PULL_EN,EMMC2_DATA0 PAD Pull Enable. 0: OFF; 1: PU; 2: PD; 3: RESERVED." "OFF;,PU;,PD;,RESERVED" line.long 0x18C "IO_PAD_CONFIG_EMMC2_DATA1,PAD EMMC2_DATA1 config register" hexmask.long.byte 0x18C 20.--23. 1. "SP,EMMC2_DATA1 PAD Drive Strength for P" hexmask.long.byte 0x18C 16.--19. 1. "SN,EMMC2_DATA1 PAD Drive Strength for N" bitfld.long 0x18C 12.--14. "RXSEL,EMMC2_DATA1 PAD Input Select" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x18C 8.--11. 1. "TXPREP,EMMC2_DATA1 PAD Slew-Rate control for P" newline hexmask.long.byte 0x18C 4.--7. 1. "TXPREN,EMMC2_DATA1 PAD Slew-Rate control for N" bitfld.long 0x18C 0.--1. "PULL_EN,EMMC2_DATA1 PAD Pull Enable. 0: OFF; 1: PU; 2: PD; 3: RESERVED." "OFF;,PU;,PD;,RESERVED" line.long 0x190 "IO_PAD_CONFIG_EMMC2_DATA2,PAD EMMC2_DATA2 config register" hexmask.long.byte 0x190 20.--23. 1. "SP,EMMC2_DATA2 PAD Drive Strength for P" hexmask.long.byte 0x190 16.--19. 1. "SN,EMMC2_DATA2 PAD Drive Strength for N" bitfld.long 0x190 12.--14. "RXSEL,EMMC2_DATA2 PAD Input Select" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x190 8.--11. 1. "TXPREP,EMMC2_DATA2 PAD Slew-Rate control for P" newline hexmask.long.byte 0x190 4.--7. 1. "TXPREN,EMMC2_DATA2 PAD Slew-Rate control for N" bitfld.long 0x190 0.--1. "PULL_EN,EMMC2_DATA2 PAD Pull Enable. 0: OFF; 1: PU; 2: PD; 3: RESERVED." "OFF;,PU;,PD;,RESERVED" line.long 0x194 "IO_PAD_CONFIG_EMMC2_DATA3,PAD EMMC2_DATA3 config register" hexmask.long.byte 0x194 20.--23. 1. "SP,EMMC2_DATA3 PAD Drive Strength for P" hexmask.long.byte 0x194 16.--19. 1. "SN,EMMC2_DATA3 PAD Drive Strength for N" bitfld.long 0x194 12.--14. "RXSEL,EMMC2_DATA3 PAD Input Select" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x194 8.--11. 1. "TXPREP,EMMC2_DATA3 PAD Slew-Rate control for P" newline hexmask.long.byte 0x194 4.--7. 1. "TXPREN,EMMC2_DATA3 PAD Slew-Rate control for N" bitfld.long 0x194 0.--1. "PULL_EN,EMMC2_DATA3 PAD Pull Enable. 0: OFF; 1: PU; 2: PD; 3: RESERVED." "OFF;,PU;,PD;,RESERVED" line.long 0x198 "IO_PAD_CONFIG_EMMC2_DATA4,PAD EMMC2_DATA4 config register" hexmask.long.byte 0x198 20.--23. 1. "SP,EMMC2_DATA4 PAD Drive Strength for P" hexmask.long.byte 0x198 16.--19. 1. "SN,EMMC2_DATA4 PAD Drive Strength for N" bitfld.long 0x198 12.--14. "RXSEL,EMMC2_DATA4 PAD Input Select" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x198 8.--11. 1. "TXPREP,EMMC2_DATA4 PAD Slew-Rate control for P" newline hexmask.long.byte 0x198 4.--7. 1. "TXPREN,EMMC2_DATA4 PAD Slew-Rate control for N" bitfld.long 0x198 0.--1. "PULL_EN,EMMC2_DATA4 PAD Pull Enable. 0: OFF; 1: PU; 2: PD; 3: RESERVED." "OFF;,PU;,PD;,RESERVED" line.long 0x19C "IO_PAD_CONFIG_EMMC2_DATA5,PAD EMMC2_DATA5 config register" hexmask.long.byte 0x19C 20.--23. 1. "SP,EMMC2_DATA5 PAD Drive Strength for P" hexmask.long.byte 0x19C 16.--19. 1. "SN,EMMC2_DATA5 PAD Drive Strength for N" bitfld.long 0x19C 12.--14. "RXSEL,EMMC2_DATA5 PAD Input Select" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x19C 8.--11. 1. "TXPREP,EMMC2_DATA5 PAD Slew-Rate control for P" newline hexmask.long.byte 0x19C 4.--7. 1. "TXPREN,EMMC2_DATA5 PAD Slew-Rate control for N" bitfld.long 0x19C 0.--1. "PULL_EN,EMMC2_DATA5 PAD Pull Enable. 0: OFF; 1: PU; 2: PD; 3: RESERVED." "OFF;,PU;,PD;,RESERVED" line.long 0x1A0 "IO_PAD_CONFIG_EMMC2_DATA6,PAD EMMC2_DATA6 config register" hexmask.long.byte 0x1A0 20.--23. 1. "SP,EMMC2_DATA6 PAD Drive Strength for P" hexmask.long.byte 0x1A0 16.--19. 1. "SN,EMMC2_DATA6 PAD Drive Strength for N" bitfld.long 0x1A0 12.--14. "RXSEL,EMMC2_DATA6 PAD Input Select" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x1A0 8.--11. 1. "TXPREP,EMMC2_DATA6 PAD Slew-Rate control for P" newline hexmask.long.byte 0x1A0 4.--7. 1. "TXPREN,EMMC2_DATA6 PAD Slew-Rate control for N" bitfld.long 0x1A0 0.--1. "PULL_EN,EMMC2_DATA6 PAD Pull Enable. 0: OFF; 1: PU; 2: PD; 3: RESERVED." "OFF;,PU;,PD;,RESERVED" line.long 0x1A4 "IO_PAD_CONFIG_EMMC2_DATA7,PAD EMMC2_DATA7 config register" hexmask.long.byte 0x1A4 20.--23. 1. "SP,EMMC2_DATA7 PAD Drive Strength for P" hexmask.long.byte 0x1A4 16.--19. 1. "SN,EMMC2_DATA7 PAD Drive Strength for N" bitfld.long 0x1A4 12.--14. "RXSEL,EMMC2_DATA7 PAD Input Select" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x1A4 8.--11. 1. "TXPREP,EMMC2_DATA7 PAD Slew-Rate control for P" newline hexmask.long.byte 0x1A4 4.--7. 1. "TXPREN,EMMC2_DATA7 PAD Slew-Rate control for N" bitfld.long 0x1A4 0.--1. "PULL_EN,EMMC2_DATA7 PAD Pull Enable. 0: OFF; 1: PU; 2: PD; 3: RESERVED." "OFF;,PU;,PD;,RESERVED" line.long 0x1A8 "IO_PAD_CONFIG_EMMC2_STROBE,PAD EMMC2_STROBE config register" hexmask.long.byte 0x1A8 20.--23. 1. "SP,EMMC2_STROBE PAD Drive Strength for P" hexmask.long.byte 0x1A8 16.--19. 1. "SN,EMMC2_STROBE PAD Drive Strength for N" bitfld.long 0x1A8 12.--14. "RXSEL,EMMC2_STROBE PAD Input Select" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x1A8 8.--11. 1. "TXPREP,EMMC2_STROBE PAD Slew-Rate control for P" newline hexmask.long.byte 0x1A8 4.--7. 1. "TXPREN,EMMC2_STROBE PAD Slew-Rate control for N" bitfld.long 0x1A8 0.--1. "PULL_EN,EMMC2_STROBE PAD Pull Enable. 0: OFF; 1: PU; 2: PD; 3: RESERVED." "OFF;,PU;,PD;,RESERVED" line.long 0x1AC "IO_PAD_CONFIG_EMMC2_RESET_N,PAD EMMC2_RESET_N config register" hexmask.long.byte 0x1AC 20.--23. 1. "SP,EMMC2_RESET_N PAD Drive Strength for P" hexmask.long.byte 0x1AC 16.--19. 1. "SN,EMMC2_RESET_N PAD Drive Strength for N" bitfld.long 0x1AC 12.--14. "RXSEL,EMMC2_RESET_N PAD Input Select" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x1AC 8.--11. 1. "TXPREP,EMMC2_RESET_N PAD Slew-Rate control for P" newline hexmask.long.byte 0x1AC 4.--7. 1. "TXPREN,EMMC2_RESET_N PAD Slew-Rate control for N" bitfld.long 0x1AC 0.--1. "PULL_EN,EMMC2_RESET_N PAD Pull Enable. 0: OFF; 1: PU; 2: PD; 3: RESERVED." "OFF;,PU;,PD;,RESERVED" group.long 0x200++0x1AF line.long 0x0 "PIN_MUX_CONFIG_GPIO_C0,PAD GPIO_C0 pin-mux config register" bitfld.long 0x0 12. "FV,GPIO_C0 PAD Force Input Value when fin=0x2" "0,1" bitfld.long 0x0 8.--9. "FIN,GPIO_C0 PAD Force Input On/Off mode" "0,1,2,3" bitfld.long 0x0 4. "ODE,GPIO_C0 PAD Opn Drain Mode enable" "0,1" newline bitfld.long 0x0 0.--2. "MUX,GPIO_C0 PAD Pin-mux func select" "0,1,2,3,4,5,6,7" line.long 0x4 "PIN_MUX_CONFIG_GPIO_C1,PAD GPIO_C1 pin-mux config register" bitfld.long 0x4 12. "FV,GPIO_C1 PAD Force Input Value when fin=0x2" "0,1" bitfld.long 0x4 8.--9. "FIN,GPIO_C1 PAD Force Input On/Off mode" "0,1,2,3" bitfld.long 0x4 4. "ODE,GPIO_C1 PAD Opn Drain Mode enable" "0,1" newline bitfld.long 0x4 0.--2. "MUX,GPIO_C1 PAD Pin-mux func select" "0,1,2,3,4,5,6,7" line.long 0x8 "PIN_MUX_CONFIG_GPIO_C2,PAD GPIO_C2 pin-mux config register" bitfld.long 0x8 12. "FV,GPIO_C2 PAD Force Input Value when fin=0x2" "0,1" bitfld.long 0x8 8.--9. "FIN,GPIO_C2 PAD Force Input On/Off mode" "0,1,2,3" bitfld.long 0x8 4. "ODE,GPIO_C2 PAD Opn Drain Mode enable" "0,1" newline bitfld.long 0x8 0.--2. "MUX,GPIO_C2 PAD Pin-mux func select" "0,1,2,3,4,5,6,7" line.long 0xC "PIN_MUX_CONFIG_GPIO_C3,PAD GPIO_C3 pin-mux config register" bitfld.long 0xC 12. "FV,GPIO_C3 PAD Force Input Value when fin=0x2" "0,1" bitfld.long 0xC 8.--9. "FIN,GPIO_C3 PAD Force Input On/Off mode" "0,1,2,3" bitfld.long 0xC 4. "ODE,GPIO_C3 PAD Opn Drain Mode enable" "0,1" newline bitfld.long 0xC 0.--2. "MUX,GPIO_C3 PAD Pin-mux func select" "0,1,2,3,4,5,6,7" line.long 0x10 "PIN_MUX_CONFIG_GPIO_C4,PAD GPIO_C4 pin-mux config register" bitfld.long 0x10 12. "FV,GPIO_C4 PAD Force Input Value when fin=0x2" "0,1" bitfld.long 0x10 8.--9. "FIN,GPIO_C4 PAD Force Input On/Off mode" "0,1,2,3" bitfld.long 0x10 4. "ODE,GPIO_C4 PAD Opn Drain Mode enable" "0,1" newline bitfld.long 0x10 0.--2. "MUX,GPIO_C4 PAD Pin-mux func select" "0,1,2,3,4,5,6,7" line.long 0x14 "PIN_MUX_CONFIG_GPIO_C5,PAD GPIO_C5 pin-mux config register" bitfld.long 0x14 12. "FV,GPIO_C5 PAD Force Input Value when fin=0x2" "0,1" bitfld.long 0x14 8.--9. "FIN,GPIO_C5 PAD Force Input On/Off mode" "0,1,2,3" bitfld.long 0x14 4. "ODE,GPIO_C5 PAD Opn Drain Mode enable" "0,1" newline bitfld.long 0x14 0.--2. "MUX,GPIO_C5 PAD Pin-mux func select" "0,1,2,3,4,5,6,7" line.long 0x18 "PIN_MUX_CONFIG_GPIO_C6,PAD GPIO_C6 pin-mux config register" bitfld.long 0x18 12. "FV,GPIO_C6 PAD Force Input Value when fin=0x2" "0,1" bitfld.long 0x18 8.--9. "FIN,GPIO_C6 PAD Force Input On/Off mode" "0,1,2,3" bitfld.long 0x18 4. "ODE,GPIO_C6 PAD Opn Drain Mode enable" "0,1" newline bitfld.long 0x18 0.--2. "MUX,GPIO_C6 PAD Pin-mux func select" "0,1,2,3,4,5,6,7" line.long 0x1C "PIN_MUX_CONFIG_GPIO_C7,PAD GPIO_C7 pin-mux config register" bitfld.long 0x1C 12. "FV,GPIO_C7 PAD Force Input Value when fin=0x2" "0,1" bitfld.long 0x1C 8.--9. "FIN,GPIO_C7 PAD Force Input On/Off mode" "0,1,2,3" bitfld.long 0x1C 4. "ODE,GPIO_C7 PAD Opn Drain Mode enable" "0,1" newline bitfld.long 0x1C 0.--2. "MUX,GPIO_C7 PAD Pin-mux func select" "0,1,2,3,4,5,6,7" line.long 0x20 "PIN_MUX_CONFIG_GPIO_C8,PAD GPIO_C8 pin-mux config register" bitfld.long 0x20 12. "FV,GPIO_C8 PAD Force Input Value when fin=0x2" "0,1" bitfld.long 0x20 8.--9. "FIN,GPIO_C8 PAD Force Input On/Off mode" "0,1,2,3" bitfld.long 0x20 4. "ODE,GPIO_C8 PAD Opn Drain Mode enable" "0,1" newline bitfld.long 0x20 0.--2. "MUX,GPIO_C8 PAD Pin-mux func select" "0,1,2,3,4,5,6,7" line.long 0x24 "PIN_MUX_CONFIG_GPIO_C9,PAD GPIO_C9 pin-mux config register" bitfld.long 0x24 12. "FV,GPIO_C9 PAD Force Input Value when fin=0x2" "0,1" bitfld.long 0x24 8.--9. "FIN,GPIO_C9 PAD Force Input On/Off mode" "0,1,2,3" bitfld.long 0x24 4. "ODE,GPIO_C9 PAD Opn Drain Mode enable" "0,1" newline bitfld.long 0x24 0.--2. "MUX,GPIO_C9 PAD Pin-mux func select" "0,1,2,3,4,5,6,7" line.long 0x28 "PIN_MUX_CONFIG_GPIO_C10,PAD GPIO_C10 pin-mux config register" bitfld.long 0x28 12. "FV,GPIO_C10 PAD Force Input Value when fin=0x2" "0,1" bitfld.long 0x28 8.--9. "FIN,GPIO_C10 PAD Force Input On/Off mode" "0,1,2,3" bitfld.long 0x28 4. "ODE,GPIO_C10 PAD Opn Drain Mode enable" "0,1" newline bitfld.long 0x28 0.--2. "MUX,GPIO_C10 PAD Pin-mux func select" "0,1,2,3,4,5,6,7" line.long 0x2C "PIN_MUX_CONFIG_GPIO_C11,PAD GPIO_C11 pin-mux config register" bitfld.long 0x2C 12. "FV,GPIO_C11 PAD Force Input Value when fin=0x2" "0,1" bitfld.long 0x2C 8.--9. "FIN,GPIO_C11 PAD Force Input On/Off mode" "0,1,2,3" bitfld.long 0x2C 4. "ODE,GPIO_C11 PAD Opn Drain Mode enable" "0,1" newline bitfld.long 0x2C 0.--2. "MUX,GPIO_C11 PAD Pin-mux func select" "0,1,2,3,4,5,6,7" line.long 0x30 "PIN_MUX_CONFIG_GPIO_C12,PAD GPIO_C12 pin-mux config register" bitfld.long 0x30 12. "FV,GPIO_C12 PAD Force Input Value when fin=0x2" "0,1" bitfld.long 0x30 8.--9. "FIN,GPIO_C12 PAD Force Input On/Off mode" "0,1,2,3" bitfld.long 0x30 4. "ODE,GPIO_C12 PAD Opn Drain Mode enable" "0,1" newline bitfld.long 0x30 0.--2. "MUX,GPIO_C12 PAD Pin-mux func select" "0,1,2,3,4,5,6,7" line.long 0x34 "PIN_MUX_CONFIG_GPIO_C13,PAD GPIO_C13 pin-mux config register" bitfld.long 0x34 12. "FV,GPIO_C13 PAD Force Input Value when fin=0x2" "0,1" bitfld.long 0x34 8.--9. "FIN,GPIO_C13 PAD Force Input On/Off mode" "0,1,2,3" bitfld.long 0x34 4. "ODE,GPIO_C13 PAD Opn Drain Mode enable" "0,1" newline bitfld.long 0x34 0.--2. "MUX,GPIO_C13 PAD Pin-mux func select" "0,1,2,3,4,5,6,7" line.long 0x38 "PIN_MUX_CONFIG_GPIO_C14,PAD GPIO_C14 pin-mux config register" bitfld.long 0x38 12. "FV,GPIO_C14 PAD Force Input Value when fin=0x2" "0,1" bitfld.long 0x38 8.--9. "FIN,GPIO_C14 PAD Force Input On/Off mode" "0,1,2,3" bitfld.long 0x38 4. "ODE,GPIO_C14 PAD Opn Drain Mode enable" "0,1" newline bitfld.long 0x38 0.--2. "MUX,GPIO_C14 PAD Pin-mux func select" "0,1,2,3,4,5,6,7" line.long 0x3C "PIN_MUX_CONFIG_GPIO_C15,PAD GPIO_C15 pin-mux config register" bitfld.long 0x3C 12. "FV,GPIO_C15 PAD Force Input Value when fin=0x2" "0,1" bitfld.long 0x3C 8.--9. "FIN,GPIO_C15 PAD Force Input On/Off mode" "0,1,2,3" bitfld.long 0x3C 4. "ODE,GPIO_C15 PAD Opn Drain Mode enable" "0,1" newline bitfld.long 0x3C 0.--2. "MUX,GPIO_C15 PAD Pin-mux func select" "0,1,2,3,4,5,6,7" line.long 0x40 "PIN_MUX_CONFIG_GPIO_D0,PAD GPIO_D0 pin-mux config register" bitfld.long 0x40 12. "FV,GPIO_D0 PAD Force Input Value when fin=0x2" "0,1" bitfld.long 0x40 8.--9. "FIN,GPIO_D0 PAD Force Input On/Off mode" "0,1,2,3" bitfld.long 0x40 4. "ODE,GPIO_D0 PAD Opn Drain Mode enable" "0,1" newline bitfld.long 0x40 0.--2. "MUX,GPIO_D0 PAD Pin-mux func select" "0,1,2,3,4,5,6,7" line.long 0x44 "PIN_MUX_CONFIG_GPIO_D1,PAD GPIO_D1 pin-mux config register" bitfld.long 0x44 12. "FV,GPIO_D1 PAD Force Input Value when fin=0x2" "0,1" bitfld.long 0x44 8.--9. "FIN,GPIO_D1 PAD Force Input On/Off mode" "0,1,2,3" bitfld.long 0x44 4. "ODE,GPIO_D1 PAD Opn Drain Mode enable" "0,1" newline bitfld.long 0x44 0.--2. "MUX,GPIO_D1 PAD Pin-mux func select" "0,1,2,3,4,5,6,7" line.long 0x48 "PIN_MUX_CONFIG_GPIO_D2,PAD GPIO_D2 pin-mux config register" bitfld.long 0x48 12. "FV,GPIO_D2 PAD Force Input Value when fin=0x2" "0,1" bitfld.long 0x48 8.--9. "FIN,GPIO_D2 PAD Force Input On/Off mode" "0,1,2,3" bitfld.long 0x48 4. "ODE,GPIO_D2 PAD Opn Drain Mode enable" "0,1" newline bitfld.long 0x48 0.--2. "MUX,GPIO_D2 PAD Pin-mux func select" "0,1,2,3,4,5,6,7" line.long 0x4C "PIN_MUX_CONFIG_GPIO_D3,PAD GPIO_D3 pin-mux config register" bitfld.long 0x4C 12. "FV,GPIO_D3 PAD Force Input Value when fin=0x2" "0,1" bitfld.long 0x4C 8.--9. "FIN,GPIO_D3 PAD Force Input On/Off mode" "0,1,2,3" bitfld.long 0x4C 4. "ODE,GPIO_D3 PAD Opn Drain Mode enable" "0,1" newline bitfld.long 0x4C 0.--2. "MUX,GPIO_D3 PAD Pin-mux func select" "0,1,2,3,4,5,6,7" line.long 0x50 "PIN_MUX_CONFIG_GPIO_D4,PAD GPIO_D4 pin-mux config register" bitfld.long 0x50 12. "FV,GPIO_D4 PAD Force Input Value when fin=0x2" "0,1" bitfld.long 0x50 8.--9. "FIN,GPIO_D4 PAD Force Input On/Off mode" "0,1,2,3" bitfld.long 0x50 4. "ODE,GPIO_D4 PAD Opn Drain Mode enable" "0,1" newline bitfld.long 0x50 0.--2. "MUX,GPIO_D4 PAD Pin-mux func select" "0,1,2,3,4,5,6,7" line.long 0x54 "PIN_MUX_CONFIG_GPIO_D5,PAD GPIO_D5 pin-mux config register" bitfld.long 0x54 12. "FV,GPIO_D5 PAD Force Input Value when fin=0x2" "0,1" bitfld.long 0x54 8.--9. "FIN,GPIO_D5 PAD Force Input On/Off mode" "0,1,2,3" bitfld.long 0x54 4. "ODE,GPIO_D5 PAD Opn Drain Mode enable" "0,1" newline bitfld.long 0x54 0.--2. "MUX,GPIO_D5 PAD Pin-mux func select" "0,1,2,3,4,5,6,7" line.long 0x58 "PIN_MUX_CONFIG_GPIO_D6,PAD GPIO_D6 pin-mux config register" bitfld.long 0x58 12. "FV,GPIO_D6 PAD Force Input Value when fin=0x2" "0,1" bitfld.long 0x58 8.--9. "FIN,GPIO_D6 PAD Force Input On/Off mode" "0,1,2,3" bitfld.long 0x58 4. "ODE,GPIO_D6 PAD Opn Drain Mode enable" "0,1" newline bitfld.long 0x58 0.--2. "MUX,GPIO_D6 PAD Pin-mux func select" "0,1,2,3,4,5,6,7" line.long 0x5C "PIN_MUX_CONFIG_GPIO_D7,PAD GPIO_D7 pin-mux config register" bitfld.long 0x5C 12. "FV,GPIO_D7 PAD Force Input Value when fin=0x2" "0,1" bitfld.long 0x5C 8.--9. "FIN,GPIO_D7 PAD Force Input On/Off mode" "0,1,2,3" bitfld.long 0x5C 4. "ODE,GPIO_D7 PAD Opn Drain Mode enable" "0,1" newline bitfld.long 0x5C 0.--2. "MUX,GPIO_D7 PAD Pin-mux func select" "0,1,2,3,4,5,6,7" line.long 0x60 "PIN_MUX_CONFIG_GPIO_D8,PAD GPIO_D8 pin-mux config register" bitfld.long 0x60 12. "FV,GPIO_D8 PAD Force Input Value when fin=0x2" "0,1" bitfld.long 0x60 8.--9. "FIN,GPIO_D8 PAD Force Input On/Off mode" "0,1,2,3" bitfld.long 0x60 4. "ODE,GPIO_D8 PAD Opn Drain Mode enable" "0,1" newline bitfld.long 0x60 0.--2. "MUX,GPIO_D8 PAD Pin-mux func select" "0,1,2,3,4,5,6,7" line.long 0x64 "PIN_MUX_CONFIG_GPIO_D9,PAD GPIO_D9 pin-mux config register" bitfld.long 0x64 12. "FV,GPIO_D9 PAD Force Input Value when fin=0x2" "0,1" bitfld.long 0x64 8.--9. "FIN,GPIO_D9 PAD Force Input On/Off mode" "0,1,2,3" bitfld.long 0x64 4. "ODE,GPIO_D9 PAD Opn Drain Mode enable" "0,1" newline bitfld.long 0x64 0.--2. "MUX,GPIO_D9 PAD Pin-mux func select" "0,1,2,3,4,5,6,7" line.long 0x68 "PIN_MUX_CONFIG_GPIO_D10,PAD GPIO_D10 pin-mux config register" bitfld.long 0x68 12. "FV,GPIO_D10 PAD Force Input Value when fin=0x2" "0,1" bitfld.long 0x68 8.--9. "FIN,GPIO_D10 PAD Force Input On/Off mode" "0,1,2,3" bitfld.long 0x68 4. "ODE,GPIO_D10 PAD Opn Drain Mode enable" "0,1" newline bitfld.long 0x68 0.--2. "MUX,GPIO_D10 PAD Pin-mux func select" "0,1,2,3,4,5,6,7" line.long 0x6C "PIN_MUX_CONFIG_GPIO_D11,PAD GPIO_D11 pin-mux config register" bitfld.long 0x6C 12. "FV,GPIO_D11 PAD Force Input Value when fin=0x2" "0,1" bitfld.long 0x6C 8.--9. "FIN,GPIO_D11 PAD Force Input On/Off mode" "0,1,2,3" bitfld.long 0x6C 4. "ODE,GPIO_D11 PAD Opn Drain Mode enable" "0,1" newline bitfld.long 0x6C 0.--2. "MUX,GPIO_D11 PAD Pin-mux func select" "0,1,2,3,4,5,6,7" line.long 0x70 "PIN_MUX_CONFIG_GPIO_D12,PAD GPIO_D12 pin-mux config register" bitfld.long 0x70 12. "FV,GPIO_D12 PAD Force Input Value when fin=0x2" "0,1" bitfld.long 0x70 8.--9. "FIN,GPIO_D12 PAD Force Input On/Off mode" "0,1,2,3" bitfld.long 0x70 4. "ODE,GPIO_D12 PAD Opn Drain Mode enable" "0,1" newline bitfld.long 0x70 0.--2. "MUX,GPIO_D12 PAD Pin-mux func select" "0,1,2,3,4,5,6,7" line.long 0x74 "PIN_MUX_CONFIG_GPIO_D13,PAD GPIO_D13 pin-mux config register" bitfld.long 0x74 12. "FV,GPIO_D13 PAD Force Input Value when fin=0x2" "0,1" bitfld.long 0x74 8.--9. "FIN,GPIO_D13 PAD Force Input On/Off mode" "0,1,2,3" bitfld.long 0x74 4. "ODE,GPIO_D13 PAD Opn Drain Mode enable" "0,1" newline bitfld.long 0x74 0.--2. "MUX,GPIO_D13 PAD Pin-mux func select" "0,1,2,3,4,5,6,7" line.long 0x78 "PIN_MUX_CONFIG_GPIO_D14,PAD GPIO_D14 pin-mux config register" bitfld.long 0x78 12. "FV,GPIO_D14 PAD Force Input Value when fin=0x2" "0,1" bitfld.long 0x78 8.--9. "FIN,GPIO_D14 PAD Force Input On/Off mode" "0,1,2,3" bitfld.long 0x78 4. "ODE,GPIO_D14 PAD Opn Drain Mode enable" "0,1" newline bitfld.long 0x78 0.--2. "MUX,GPIO_D14 PAD Pin-mux func select" "0,1,2,3,4,5,6,7" line.long 0x7C "PIN_MUX_CONFIG_GPIO_D15,PAD GPIO_D15 pin-mux config register" bitfld.long 0x7C 12. "FV,GPIO_D15 PAD Force Input Value when fin=0x2" "0,1" bitfld.long 0x7C 8.--9. "FIN,GPIO_D15 PAD Force Input On/Off mode" "0,1,2,3" bitfld.long 0x7C 4. "ODE,GPIO_D15 PAD Opn Drain Mode enable" "0,1" newline bitfld.long 0x7C 0.--2. "MUX,GPIO_D15 PAD Pin-mux func select" "0,1,2,3,4,5,6,7" line.long 0x80 "PIN_MUX_CONFIG_OSPI2_SCLK,PAD OSPI2_SCLK pin-mux config register" bitfld.long 0x80 12. "FV,OSPI2_SCLK PAD Force Input Value when fin=0x2" "0,1" bitfld.long 0x80 8.--9. "FIN,OSPI2_SCLK PAD Force Input On/Off mode" "0,1,2,3" bitfld.long 0x80 4. "ODE,OSPI2_SCLK PAD Opn Drain Mode enable" "0,1" newline bitfld.long 0x80 0.--2. "MUX,OSPI2_SCLK PAD Pin-mux func select" "0,1,2,3,4,5,6,7" line.long 0x84 "PIN_MUX_CONFIG_OSPI2_SS0,PAD OSPI2_SS0 pin-mux config register" bitfld.long 0x84 12. "FV,OSPI2_SS0 PAD Force Input Value when fin=0x2" "0,1" bitfld.long 0x84 8.--9. "FIN,OSPI2_SS0 PAD Force Input On/Off mode" "0,1,2,3" bitfld.long 0x84 4. "ODE,OSPI2_SS0 PAD Opn Drain Mode enable" "0,1" newline bitfld.long 0x84 0.--2. "MUX,OSPI2_SS0 PAD Pin-mux func select" "0,1,2,3,4,5,6,7" line.long 0x88 "PIN_MUX_CONFIG_OSPI2_DATA0,PAD OSPI2_DATA0 pin-mux config register" bitfld.long 0x88 12. "FV,OSPI2_DATA0 PAD Force Input Value when fin=0x2" "0,1" bitfld.long 0x88 8.--9. "FIN,OSPI2_DATA0 PAD Force Input On/Off mode" "0,1,2,3" bitfld.long 0x88 4. "ODE,OSPI2_DATA0 PAD Opn Drain Mode enable" "0,1" newline bitfld.long 0x88 0.--2. "MUX,OSPI2_DATA0 PAD Pin-mux func select" "0,1,2,3,4,5,6,7" line.long 0x8C "PIN_MUX_CONFIG_OSPI2_DATA1,PAD OSPI2_DATA1 pin-mux config register" bitfld.long 0x8C 12. "FV,OSPI2_DATA1 PAD Force Input Value when fin=0x2" "0,1" bitfld.long 0x8C 8.--9. "FIN,OSPI2_DATA1 PAD Force Input On/Off mode" "0,1,2,3" bitfld.long 0x8C 4. "ODE,OSPI2_DATA1 PAD Opn Drain Mode enable" "0,1" newline bitfld.long 0x8C 0.--2. "MUX,OSPI2_DATA1 PAD Pin-mux func select" "0,1,2,3,4,5,6,7" line.long 0x90 "PIN_MUX_CONFIG_OSPI2_DATA2,PAD OSPI2_DATA2 pin-mux config register" bitfld.long 0x90 12. "FV,OSPI2_DATA2 PAD Force Input Value when fin=0x2" "0,1" bitfld.long 0x90 8.--9. "FIN,OSPI2_DATA2 PAD Force Input On/Off mode" "0,1,2,3" bitfld.long 0x90 4. "ODE,OSPI2_DATA2 PAD Opn Drain Mode enable" "0,1" newline bitfld.long 0x90 0.--2. "MUX,OSPI2_DATA2 PAD Pin-mux func select" "0,1,2,3,4,5,6,7" line.long 0x94 "PIN_MUX_CONFIG_OSPI2_DATA3,PAD OSPI2_DATA3 pin-mux config register" bitfld.long 0x94 12. "FV,OSPI2_DATA3 PAD Force Input Value when fin=0x2" "0,1" bitfld.long 0x94 8.--9. "FIN,OSPI2_DATA3 PAD Force Input On/Off mode" "0,1,2,3" bitfld.long 0x94 4. "ODE,OSPI2_DATA3 PAD Opn Drain Mode enable" "0,1" newline bitfld.long 0x94 0.--2. "MUX,OSPI2_DATA3 PAD Pin-mux func select" "0,1,2,3,4,5,6,7" line.long 0x98 "PIN_MUX_CONFIG_OSPI2_DATA4,PAD OSPI2_DATA4 pin-mux config register" bitfld.long 0x98 12. "FV,OSPI2_DATA4 PAD Force Input Value when fin=0x2" "0,1" bitfld.long 0x98 8.--9. "FIN,OSPI2_DATA4 PAD Force Input On/Off mode" "0,1,2,3" bitfld.long 0x98 4. "ODE,OSPI2_DATA4 PAD Opn Drain Mode enable" "0,1" newline bitfld.long 0x98 0.--2. "MUX,OSPI2_DATA4 PAD Pin-mux func select" "0,1,2,3,4,5,6,7" line.long 0x9C "PIN_MUX_CONFIG_OSPI2_DATA5,PAD OSPI2_DATA5 pin-mux config register" bitfld.long 0x9C 12. "FV,OSPI2_DATA5 PAD Force Input Value when fin=0x2" "0,1" bitfld.long 0x9C 8.--9. "FIN,OSPI2_DATA5 PAD Force Input On/Off mode" "0,1,2,3" bitfld.long 0x9C 4. "ODE,OSPI2_DATA5 PAD Opn Drain Mode enable" "0,1" newline bitfld.long 0x9C 0.--2. "MUX,OSPI2_DATA5 PAD Pin-mux func select" "0,1,2,3,4,5,6,7" line.long 0xA0 "PIN_MUX_CONFIG_OSPI2_DATA6,PAD OSPI2_DATA6 pin-mux config register" bitfld.long 0xA0 12. "FV,OSPI2_DATA6 PAD Force Input Value when fin=0x2" "0,1" bitfld.long 0xA0 8.--9. "FIN,OSPI2_DATA6 PAD Force Input On/Off mode" "0,1,2,3" bitfld.long 0xA0 4. "ODE,OSPI2_DATA6 PAD Opn Drain Mode enable" "0,1" newline bitfld.long 0xA0 0.--2. "MUX,OSPI2_DATA6 PAD Pin-mux func select" "0,1,2,3,4,5,6,7" line.long 0xA4 "PIN_MUX_CONFIG_OSPI2_DATA7,PAD OSPI2_DATA7 pin-mux config register" bitfld.long 0xA4 12. "FV,OSPI2_DATA7 PAD Force Input Value when fin=0x2" "0,1" bitfld.long 0xA4 8.--9. "FIN,OSPI2_DATA7 PAD Force Input On/Off mode" "0,1,2,3" bitfld.long 0xA4 4. "ODE,OSPI2_DATA7 PAD Opn Drain Mode enable" "0,1" newline bitfld.long 0xA4 0.--2. "MUX,OSPI2_DATA7 PAD Pin-mux func select" "0,1,2,3,4,5,6,7" line.long 0xA8 "PIN_MUX_CONFIG_OSPI2_DQS,PAD OSPI2_DQS pin-mux config register" bitfld.long 0xA8 12. "FV,OSPI2_DQS PAD Force Input Value when fin=0x2" "0,1" bitfld.long 0xA8 8.--9. "FIN,OSPI2_DQS PAD Force Input On/Off mode" "0,1,2,3" bitfld.long 0xA8 4. "ODE,OSPI2_DQS PAD Opn Drain Mode enable" "0,1" newline bitfld.long 0xA8 0.--2. "MUX,OSPI2_DQS PAD Pin-mux func select" "0,1,2,3,4,5,6,7" line.long 0xAC "PIN_MUX_CONFIG_OSPI2_SS1,PAD OSPI2_SS1 pin-mux config register" bitfld.long 0xAC 12. "FV,OSPI2_SS1 PAD Force Input Value when fin=0x2" "0,1" bitfld.long 0xAC 8.--9. "FIN,OSPI2_SS1 PAD Force Input On/Off mode" "0,1,2,3" bitfld.long 0xAC 4. "ODE,OSPI2_SS1 PAD Opn Drain Mode enable" "0,1" newline bitfld.long 0xAC 0.--2. "MUX,OSPI2_SS1 PAD Pin-mux func select" "0,1,2,3,4,5,6,7" line.long 0xB0 "PIN_MUX_CONFIG_RGMII2_TXC,PAD RGMII2_TXC pin-mux config register" bitfld.long 0xB0 12. "FV,RGMII2_TXC PAD Force Input Value when fin=0x2" "0,1" bitfld.long 0xB0 8.--9. "FIN,RGMII2_TXC PAD Force Input On/Off mode" "0,1,2,3" bitfld.long 0xB0 4. "ODE,RGMII2_TXC PAD Opn Drain Mode enable" "0,1" newline bitfld.long 0xB0 0.--2. "MUX,RGMII2_TXC PAD Pin-mux func select" "0,1,2,3,4,5,6,7" line.long 0xB4 "PIN_MUX_CONFIG_RGMII2_TXD0,PAD RGMII2_TXD0 pin-mux config register" bitfld.long 0xB4 12. "FV,RGMII2_TXD0 PAD Force Input Value when fin=0x2" "0,1" bitfld.long 0xB4 8.--9. "FIN,RGMII2_TXD0 PAD Force Input On/Off mode" "0,1,2,3" bitfld.long 0xB4 4. "ODE,RGMII2_TXD0 PAD Opn Drain Mode enable" "0,1" newline bitfld.long 0xB4 0.--2. "MUX,RGMII2_TXD0 PAD Pin-mux func select" "0,1,2,3,4,5,6,7" line.long 0xB8 "PIN_MUX_CONFIG_RGMII2_TXD1,PAD RGMII2_TXD1 pin-mux config register" bitfld.long 0xB8 12. "FV,RGMII2_TXD1 PAD Force Input Value when fin=0x2" "0,1" bitfld.long 0xB8 8.--9. "FIN,RGMII2_TXD1 PAD Force Input On/Off mode" "0,1,2,3" bitfld.long 0xB8 4. "ODE,RGMII2_TXD1 PAD Opn Drain Mode enable" "0,1" newline bitfld.long 0xB8 0.--2. "MUX,RGMII2_TXD1 PAD Pin-mux func select" "0,1,2,3,4,5,6,7" line.long 0xBC "PIN_MUX_CONFIG_RGMII2_TXD2,PAD RGMII2_TXD2 pin-mux config register" bitfld.long 0xBC 12. "FV,RGMII2_TXD2 PAD Force Input Value when fin=0x2" "0,1" bitfld.long 0xBC 8.--9. "FIN,RGMII2_TXD2 PAD Force Input On/Off mode" "0,1,2,3" bitfld.long 0xBC 4. "ODE,RGMII2_TXD2 PAD Opn Drain Mode enable" "0,1" newline bitfld.long 0xBC 0.--2. "MUX,RGMII2_TXD2 PAD Pin-mux func select" "0,1,2,3,4,5,6,7" line.long 0xC0 "PIN_MUX_CONFIG_RGMII2_TXD3,PAD RGMII2_TXD3 pin-mux config register" bitfld.long 0xC0 12. "FV,RGMII2_TXD3 PAD Force Input Value when fin=0x2" "0,1" bitfld.long 0xC0 8.--9. "FIN,RGMII2_TXD3 PAD Force Input On/Off mode" "0,1,2,3" bitfld.long 0xC0 4. "ODE,RGMII2_TXD3 PAD Opn Drain Mode enable" "0,1" newline bitfld.long 0xC0 0.--2. "MUX,RGMII2_TXD3 PAD Pin-mux func select" "0,1,2,3,4,5,6,7" line.long 0xC4 "PIN_MUX_CONFIG_RGMII2_TX_CTL,PAD RGMII2_TX_CTL pin-mux config register" bitfld.long 0xC4 12. "FV,RGMII2_TX_CTL PAD Force Input Value when fin=0x2" "0,1" bitfld.long 0xC4 8.--9. "FIN,RGMII2_TX_CTL PAD Force Input On/Off mode" "0,1,2,3" bitfld.long 0xC4 4. "ODE,RGMII2_TX_CTL PAD Opn Drain Mode enable" "0,1" newline bitfld.long 0xC4 0.--2. "MUX,RGMII2_TX_CTL PAD Pin-mux func select" "0,1,2,3,4,5,6,7" line.long 0xC8 "PIN_MUX_CONFIG_RGMII2_RXC,PAD RGMII2_RXC pin-mux config register" bitfld.long 0xC8 12. "FV,RGMII2_RXC PAD Force Input Value when fin=0x2" "0,1" bitfld.long 0xC8 8.--9. "FIN,RGMII2_RXC PAD Force Input On/Off mode" "0,1,2,3" bitfld.long 0xC8 4. "ODE,RGMII2_RXC PAD Opn Drain Mode enable" "0,1" newline bitfld.long 0xC8 0.--2. "MUX,RGMII2_RXC PAD Pin-mux func select" "0,1,2,3,4,5,6,7" line.long 0xCC "PIN_MUX_CONFIG_RGMII2_RXD0,PAD RGMII2_RXD0 pin-mux config register" bitfld.long 0xCC 12. "FV,RGMII2_RXD0 PAD Force Input Value when fin=0x2" "0,1" bitfld.long 0xCC 8.--9. "FIN,RGMII2_RXD0 PAD Force Input On/Off mode" "0,1,2,3" bitfld.long 0xCC 4. "ODE,RGMII2_RXD0 PAD Opn Drain Mode enable" "0,1" newline bitfld.long 0xCC 0.--2. "MUX,RGMII2_RXD0 PAD Pin-mux func select" "0,1,2,3,4,5,6,7" line.long 0xD0 "PIN_MUX_CONFIG_RGMII2_RXD1,PAD RGMII2_RXD1 pin-mux config register" bitfld.long 0xD0 12. "FV,RGMII2_RXD1 PAD Force Input Value when fin=0x2" "0,1" bitfld.long 0xD0 8.--9. "FIN,RGMII2_RXD1 PAD Force Input On/Off mode" "0,1,2,3" bitfld.long 0xD0 4. "ODE,RGMII2_RXD1 PAD Opn Drain Mode enable" "0,1" newline bitfld.long 0xD0 0.--2. "MUX,RGMII2_RXD1 PAD Pin-mux func select" "0,1,2,3,4,5,6,7" line.long 0xD4 "PIN_MUX_CONFIG_RGMII2_RXD2,PAD RGMII2_RXD2 pin-mux config register" bitfld.long 0xD4 12. "FV,RGMII2_RXD2 PAD Force Input Value when fin=0x2" "0,1" bitfld.long 0xD4 8.--9. "FIN,RGMII2_RXD2 PAD Force Input On/Off mode" "0,1,2,3" bitfld.long 0xD4 4. "ODE,RGMII2_RXD2 PAD Opn Drain Mode enable" "0,1" newline bitfld.long 0xD4 0.--2. "MUX,RGMII2_RXD2 PAD Pin-mux func select" "0,1,2,3,4,5,6,7" line.long 0xD8 "PIN_MUX_CONFIG_RGMII2_RXD3,PAD RGMII2_RXD3 pin-mux config register" bitfld.long 0xD8 12. "FV,RGMII2_RXD3 PAD Force Input Value when fin=0x2" "0,1" bitfld.long 0xD8 8.--9. "FIN,RGMII2_RXD3 PAD Force Input On/Off mode" "0,1,2,3" bitfld.long 0xD8 4. "ODE,RGMII2_RXD3 PAD Opn Drain Mode enable" "0,1" newline bitfld.long 0xD8 0.--2. "MUX,RGMII2_RXD3 PAD Pin-mux func select" "0,1,2,3,4,5,6,7" line.long 0xDC "PIN_MUX_CONFIG_RGMII2_RX_CTL,PAD RGMII2_RX_CTL pin-mux config register" bitfld.long 0xDC 12. "FV,RGMII2_RX_CTL PAD Force Input Value when fin=0x2" "0,1" bitfld.long 0xDC 8.--9. "FIN,RGMII2_RX_CTL PAD Force Input On/Off mode" "0,1,2,3" bitfld.long 0xDC 4. "ODE,RGMII2_RX_CTL PAD Opn Drain Mode enable" "0,1" newline bitfld.long 0xDC 0.--2. "MUX,RGMII2_RX_CTL PAD Pin-mux func select" "0,1,2,3,4,5,6,7" line.long 0xE0 "PIN_MUX_CONFIG_I2S_SC3_SCK,PAD I2S_SC3_SCK pin-mux config register" bitfld.long 0xE0 12. "FV,I2S_SC3_SCK PAD Force Input Value when fin=0x2" "0,1" bitfld.long 0xE0 8.--9. "FIN,I2S_SC3_SCK PAD Force Input On/Off mode" "0,1,2,3" bitfld.long 0xE0 4. "ODE,I2S_SC3_SCK PAD Opn Drain Mode enable" "0,1" newline bitfld.long 0xE0 0.--2. "MUX,I2S_SC3_SCK PAD Pin-mux func select" "0,1,2,3,4,5,6,7" line.long 0xE4 "PIN_MUX_CONFIG_I2S_SC3_WS,PAD I2S_SC3_WS pin-mux config register" bitfld.long 0xE4 12. "FV,I2S_SC3_WS PAD Force Input Value when fin=0x2" "0,1" bitfld.long 0xE4 8.--9. "FIN,I2S_SC3_WS PAD Force Input On/Off mode" "0,1,2,3" bitfld.long 0xE4 4. "ODE,I2S_SC3_WS PAD Opn Drain Mode enable" "0,1" newline bitfld.long 0xE4 0.--2. "MUX,I2S_SC3_WS PAD Pin-mux func select" "0,1,2,3,4,5,6,7" line.long 0xE8 "PIN_MUX_CONFIG_I2S_SC3_SD,PAD I2S_SC3_SD pin-mux config register" bitfld.long 0xE8 12. "FV,I2S_SC3_SD PAD Force Input Value when fin=0x2" "0,1" bitfld.long 0xE8 8.--9. "FIN,I2S_SC3_SD PAD Force Input On/Off mode" "0,1,2,3" bitfld.long 0xE8 4. "ODE,I2S_SC3_SD PAD Opn Drain Mode enable" "0,1" newline bitfld.long 0xE8 0.--2. "MUX,I2S_SC3_SD PAD Pin-mux func select" "0,1,2,3,4,5,6,7" line.long 0xEC "PIN_MUX_CONFIG_I2S_SC4_SCK,PAD I2S_SC4_SCK pin-mux config register" bitfld.long 0xEC 12. "FV,I2S_SC4_SCK PAD Force Input Value when fin=0x2" "0,1" bitfld.long 0xEC 8.--9. "FIN,I2S_SC4_SCK PAD Force Input On/Off mode" "0,1,2,3" bitfld.long 0xEC 4. "ODE,I2S_SC4_SCK PAD Opn Drain Mode enable" "0,1" newline bitfld.long 0xEC 0.--2. "MUX,I2S_SC4_SCK PAD Pin-mux func select" "0,1,2,3,4,5,6,7" line.long 0xF0 "PIN_MUX_CONFIG_I2S_SC4_WS,PAD I2S_SC4_WS pin-mux config register" bitfld.long 0xF0 12. "FV,I2S_SC4_WS PAD Force Input Value when fin=0x2" "0,1" bitfld.long 0xF0 8.--9. "FIN,I2S_SC4_WS PAD Force Input On/Off mode" "0,1,2,3" bitfld.long 0xF0 4. "ODE,I2S_SC4_WS PAD Opn Drain Mode enable" "0,1" newline bitfld.long 0xF0 0.--2. "MUX,I2S_SC4_WS PAD Pin-mux func select" "0,1,2,3,4,5,6,7" line.long 0xF4 "PIN_MUX_CONFIG_I2S_SC4_SD,PAD I2S_SC4_SD pin-mux config register" bitfld.long 0xF4 12. "FV,I2S_SC4_SD PAD Force Input Value when fin=0x2" "0,1" bitfld.long 0xF4 8.--9. "FIN,I2S_SC4_SD PAD Force Input On/Off mode" "0,1,2,3" bitfld.long 0xF4 4. "ODE,I2S_SC4_SD PAD Opn Drain Mode enable" "0,1" newline bitfld.long 0xF4 0.--2. "MUX,I2S_SC4_SD PAD Pin-mux func select" "0,1,2,3,4,5,6,7" line.long 0xF8 "PIN_MUX_CONFIG_I2S_SC5_SCK,PAD I2S_SC5_SCK pin-mux config register" bitfld.long 0xF8 12. "FV,I2S_SC5_SCK PAD Force Input Value when fin=0x2" "0,1" bitfld.long 0xF8 8.--9. "FIN,I2S_SC5_SCK PAD Force Input On/Off mode" "0,1,2,3" bitfld.long 0xF8 4. "ODE,I2S_SC5_SCK PAD Opn Drain Mode enable" "0,1" newline bitfld.long 0xF8 0.--2. "MUX,I2S_SC5_SCK PAD Pin-mux func select" "0,1,2,3,4,5,6,7" line.long 0xFC "PIN_MUX_CONFIG_I2S_SC5_WS,PAD I2S_SC5_WS pin-mux config register" bitfld.long 0xFC 12. "FV,I2S_SC5_WS PAD Force Input Value when fin=0x2" "0,1" bitfld.long 0xFC 8.--9. "FIN,I2S_SC5_WS PAD Force Input On/Off mode" "0,1,2,3" bitfld.long 0xFC 4. "ODE,I2S_SC5_WS PAD Opn Drain Mode enable" "0,1" newline bitfld.long 0xFC 0.--2. "MUX,I2S_SC5_WS PAD Pin-mux func select" "0,1,2,3,4,5,6,7" line.long 0x100 "PIN_MUX_CONFIG_I2S_SC5_SD,PAD I2S_SC5_SD pin-mux config register" bitfld.long 0x100 12. "FV,I2S_SC5_SD PAD Force Input Value when fin=0x2" "0,1" bitfld.long 0x100 8.--9. "FIN,I2S_SC5_SD PAD Force Input On/Off mode" "0,1,2,3" bitfld.long 0x100 4. "ODE,I2S_SC5_SD PAD Opn Drain Mode enable" "0,1" newline bitfld.long 0x100 0.--2. "MUX,I2S_SC5_SD PAD Pin-mux func select" "0,1,2,3,4,5,6,7" line.long 0x104 "PIN_MUX_CONFIG_I2S_SC6_SCK,PAD I2S_SC6_SCK pin-mux config register" bitfld.long 0x104 12. "FV,I2S_SC6_SCK PAD Force Input Value when fin=0x2" "0,1" bitfld.long 0x104 8.--9. "FIN,I2S_SC6_SCK PAD Force Input On/Off mode" "0,1,2,3" bitfld.long 0x104 4. "ODE,I2S_SC6_SCK PAD Opn Drain Mode enable" "0,1" newline bitfld.long 0x104 0.--2. "MUX,I2S_SC6_SCK PAD Pin-mux func select" "0,1,2,3,4,5,6,7" line.long 0x108 "PIN_MUX_CONFIG_I2S_SC6_WS,PAD I2S_SC6_WS pin-mux config register" bitfld.long 0x108 12. "FV,I2S_SC6_WS PAD Force Input Value when fin=0x2" "0,1" bitfld.long 0x108 8.--9. "FIN,I2S_SC6_WS PAD Force Input On/Off mode" "0,1,2,3" bitfld.long 0x108 4. "ODE,I2S_SC6_WS PAD Opn Drain Mode enable" "0,1" newline bitfld.long 0x108 0.--2. "MUX,I2S_SC6_WS PAD Pin-mux func select" "0,1,2,3,4,5,6,7" line.long 0x10C "PIN_MUX_CONFIG_I2S_SC6_SD,PAD I2S_SC6_SD pin-mux config register" bitfld.long 0x10C 12. "FV,I2S_SC6_SD PAD Force Input Value when fin=0x2" "0,1" bitfld.long 0x10C 8.--9. "FIN,I2S_SC6_SD PAD Force Input On/Off mode" "0,1,2,3" bitfld.long 0x10C 4. "ODE,I2S_SC6_SD PAD Opn Drain Mode enable" "0,1" newline bitfld.long 0x10C 0.--2. "MUX,I2S_SC6_SD PAD Pin-mux func select" "0,1,2,3,4,5,6,7" line.long 0x110 "PIN_MUX_CONFIG_I2S_SC7_SCK,PAD I2S_SC7_SCK pin-mux config register" bitfld.long 0x110 12. "FV,I2S_SC7_SCK PAD Force Input Value when fin=0x2" "0,1" bitfld.long 0x110 8.--9. "FIN,I2S_SC7_SCK PAD Force Input On/Off mode" "0,1,2,3" bitfld.long 0x110 4. "ODE,I2S_SC7_SCK PAD Opn Drain Mode enable" "0,1" newline bitfld.long 0x110 0.--2. "MUX,I2S_SC7_SCK PAD Pin-mux func select" "0,1,2,3,4,5,6,7" line.long 0x114 "PIN_MUX_CONFIG_I2S_SC7_WS,PAD I2S_SC7_WS pin-mux config register" bitfld.long 0x114 12. "FV,I2S_SC7_WS PAD Force Input Value when fin=0x2" "0,1" bitfld.long 0x114 8.--9. "FIN,I2S_SC7_WS PAD Force Input On/Off mode" "0,1,2,3" bitfld.long 0x114 4. "ODE,I2S_SC7_WS PAD Opn Drain Mode enable" "0,1" newline bitfld.long 0x114 0.--2. "MUX,I2S_SC7_WS PAD Pin-mux func select" "0,1,2,3,4,5,6,7" line.long 0x118 "PIN_MUX_CONFIG_I2S_SC7_SD,PAD I2S_SC7_SD pin-mux config register" bitfld.long 0x118 12. "FV,I2S_SC7_SD PAD Force Input Value when fin=0x2" "0,1" bitfld.long 0x118 8.--9. "FIN,I2S_SC7_SD PAD Force Input On/Off mode" "0,1,2,3" bitfld.long 0x118 4. "ODE,I2S_SC7_SD PAD Opn Drain Mode enable" "0,1" newline bitfld.long 0x118 0.--2. "MUX,I2S_SC7_SD PAD Pin-mux func select" "0,1,2,3,4,5,6,7" line.long 0x11C "PIN_MUX_CONFIG_I2S_SC8_SCK,PAD I2S_SC8_SCK pin-mux config register" bitfld.long 0x11C 12. "FV,I2S_SC8_SCK PAD Force Input Value when fin=0x2" "0,1" bitfld.long 0x11C 8.--9. "FIN,I2S_SC8_SCK PAD Force Input On/Off mode" "0,1,2,3" bitfld.long 0x11C 4. "ODE,I2S_SC8_SCK PAD Opn Drain Mode enable" "0,1" newline bitfld.long 0x11C 0.--2. "MUX,I2S_SC8_SCK PAD Pin-mux func select" "0,1,2,3,4,5,6,7" line.long 0x120 "PIN_MUX_CONFIG_I2S_SC8_WS,PAD I2S_SC8_WS pin-mux config register" bitfld.long 0x120 12. "FV,I2S_SC8_WS PAD Force Input Value when fin=0x2" "0,1" bitfld.long 0x120 8.--9. "FIN,I2S_SC8_WS PAD Force Input On/Off mode" "0,1,2,3" bitfld.long 0x120 4. "ODE,I2S_SC8_WS PAD Opn Drain Mode enable" "0,1" newline bitfld.long 0x120 0.--2. "MUX,I2S_SC8_WS PAD Pin-mux func select" "0,1,2,3,4,5,6,7" line.long 0x124 "PIN_MUX_CONFIG_I2S_SC8_SD,PAD I2S_SC8_SD pin-mux config register" bitfld.long 0x124 12. "FV,I2S_SC8_SD PAD Force Input Value when fin=0x2" "0,1" bitfld.long 0x124 8.--9. "FIN,I2S_SC8_SD PAD Force Input On/Off mode" "0,1,2,3" bitfld.long 0x124 4. "ODE,I2S_SC8_SD PAD Opn Drain Mode enable" "0,1" newline bitfld.long 0x124 0.--2. "MUX,I2S_SC8_SD PAD Pin-mux func select" "0,1,2,3,4,5,6,7" line.long 0x128 "PIN_MUX_CONFIG_I2S_MC_SCK,PAD I2S_MC_SCK pin-mux config register" bitfld.long 0x128 12. "FV,I2S_MC_SCK PAD Force Input Value when fin=0x2" "0,1" bitfld.long 0x128 8.--9. "FIN,I2S_MC_SCK PAD Force Input On/Off mode" "0,1,2,3" bitfld.long 0x128 4. "ODE,I2S_MC_SCK PAD Opn Drain Mode enable" "0,1" newline bitfld.long 0x128 0.--2. "MUX,I2S_MC_SCK PAD Pin-mux func select" "0,1,2,3,4,5,6,7" line.long 0x12C "PIN_MUX_CONFIG_I2S_MC_WS,PAD I2S_MC_WS pin-mux config register" bitfld.long 0x12C 12. "FV,I2S_MC_WS PAD Force Input Value when fin=0x2" "0,1" bitfld.long 0x12C 8.--9. "FIN,I2S_MC_WS PAD Force Input On/Off mode" "0,1,2,3" bitfld.long 0x12C 4. "ODE,I2S_MC_WS PAD Opn Drain Mode enable" "0,1" newline bitfld.long 0x12C 0.--2. "MUX,I2S_MC_WS PAD Pin-mux func select" "0,1,2,3,4,5,6,7" line.long 0x130 "PIN_MUX_CONFIG_I2S_MC_SD0,PAD I2S_MC_SD0 pin-mux config register" bitfld.long 0x130 12. "FV,I2S_MC_SD0 PAD Force Input Value when fin=0x2" "0,1" bitfld.long 0x130 8.--9. "FIN,I2S_MC_SD0 PAD Force Input On/Off mode" "0,1,2,3" bitfld.long 0x130 4. "ODE,I2S_MC_SD0 PAD Opn Drain Mode enable" "0,1" newline bitfld.long 0x130 0.--2. "MUX,I2S_MC_SD0 PAD Pin-mux func select" "0,1,2,3,4,5,6,7" line.long 0x134 "PIN_MUX_CONFIG_I2S_MC_SD1,PAD I2S_MC_SD1 pin-mux config register" bitfld.long 0x134 12. "FV,I2S_MC_SD1 PAD Force Input Value when fin=0x2" "0,1" bitfld.long 0x134 8.--9. "FIN,I2S_MC_SD1 PAD Force Input On/Off mode" "0,1,2,3" bitfld.long 0x134 4. "ODE,I2S_MC_SD1 PAD Opn Drain Mode enable" "0,1" newline bitfld.long 0x134 0.--2. "MUX,I2S_MC_SD1 PAD Pin-mux func select" "0,1,2,3,4,5,6,7" line.long 0x138 "PIN_MUX_CONFIG_I2S_MC_SD2,PAD I2S_MC_SD2 pin-mux config register" bitfld.long 0x138 12. "FV,I2S_MC_SD2 PAD Force Input Value when fin=0x2" "0,1" bitfld.long 0x138 8.--9. "FIN,I2S_MC_SD2 PAD Force Input On/Off mode" "0,1,2,3" bitfld.long 0x138 4. "ODE,I2S_MC_SD2 PAD Opn Drain Mode enable" "0,1" newline bitfld.long 0x138 0.--2. "MUX,I2S_MC_SD2 PAD Pin-mux func select" "0,1,2,3,4,5,6,7" line.long 0x13C "PIN_MUX_CONFIG_I2S_MC_SD3,PAD I2S_MC_SD3 pin-mux config register" bitfld.long 0x13C 12. "FV,I2S_MC_SD3 PAD Force Input Value when fin=0x2" "0,1" bitfld.long 0x13C 8.--9. "FIN,I2S_MC_SD3 PAD Force Input On/Off mode" "0,1,2,3" bitfld.long 0x13C 4. "ODE,I2S_MC_SD3 PAD Opn Drain Mode enable" "0,1" newline bitfld.long 0x13C 0.--2. "MUX,I2S_MC_SD3 PAD Pin-mux func select" "0,1,2,3,4,5,6,7" line.long 0x140 "PIN_MUX_CONFIG_I2S_MC_SD4,PAD I2S_MC_SD4 pin-mux config register" bitfld.long 0x140 12. "FV,I2S_MC_SD4 PAD Force Input Value when fin=0x2" "0,1" bitfld.long 0x140 8.--9. "FIN,I2S_MC_SD4 PAD Force Input On/Off mode" "0,1,2,3" bitfld.long 0x140 4. "ODE,I2S_MC_SD4 PAD Opn Drain Mode enable" "0,1" newline bitfld.long 0x140 0.--2. "MUX,I2S_MC_SD4 PAD Pin-mux func select" "0,1,2,3,4,5,6,7" line.long 0x144 "PIN_MUX_CONFIG_I2S_MC_SD5,PAD I2S_MC_SD5 pin-mux config register" bitfld.long 0x144 12. "FV,I2S_MC_SD5 PAD Force Input Value when fin=0x2" "0,1" bitfld.long 0x144 8.--9. "FIN,I2S_MC_SD5 PAD Force Input On/Off mode" "0,1,2,3" bitfld.long 0x144 4. "ODE,I2S_MC_SD5 PAD Opn Drain Mode enable" "0,1" newline bitfld.long 0x144 0.--2. "MUX,I2S_MC_SD5 PAD Pin-mux func select" "0,1,2,3,4,5,6,7" line.long 0x148 "PIN_MUX_CONFIG_I2S_MC_SD6,PAD I2S_MC_SD6 pin-mux config register" bitfld.long 0x148 12. "FV,I2S_MC_SD6 PAD Force Input Value when fin=0x2" "0,1" bitfld.long 0x148 8.--9. "FIN,I2S_MC_SD6 PAD Force Input On/Off mode" "0,1,2,3" bitfld.long 0x148 4. "ODE,I2S_MC_SD6 PAD Opn Drain Mode enable" "0,1" newline bitfld.long 0x148 0.--2. "MUX,I2S_MC_SD6 PAD Pin-mux func select" "0,1,2,3,4,5,6,7" line.long 0x14C "PIN_MUX_CONFIG_I2S_MC_SD7,PAD I2S_MC_SD7 pin-mux config register" bitfld.long 0x14C 12. "FV,I2S_MC_SD7 PAD Force Input Value when fin=0x2" "0,1" bitfld.long 0x14C 8.--9. "FIN,I2S_MC_SD7 PAD Force Input On/Off mode" "0,1,2,3" bitfld.long 0x14C 4. "ODE,I2S_MC_SD7 PAD Opn Drain Mode enable" "0,1" newline bitfld.long 0x14C 0.--2. "MUX,I2S_MC_SD7 PAD Pin-mux func select" "0,1,2,3,4,5,6,7" line.long 0x150 "PIN_MUX_CONFIG_EMMC1_CLK,PAD EMMC1_CLK pin-mux config register" bitfld.long 0x150 12. "FV,EMMC1_CLK PAD Force Input Value when fin=0x2" "0,1" bitfld.long 0x150 8.--9. "FIN,EMMC1_CLK PAD Force Input On/Off mode" "0,1,2,3" bitfld.long 0x150 4. "ODE,EMMC1_CLK PAD Opn Drain Mode enable" "0,1" newline bitfld.long 0x150 0.--2. "MUX,EMMC1_CLK PAD Pin-mux func select" "0,1,2,3,4,5,6,7" line.long 0x154 "PIN_MUX_CONFIG_EMMC1_CMD,PAD EMMC1_CMD pin-mux config register" bitfld.long 0x154 12. "FV,EMMC1_CMD PAD Force Input Value when fin=0x2" "0,1" bitfld.long 0x154 8.--9. "FIN,EMMC1_CMD PAD Force Input On/Off mode" "0,1,2,3" bitfld.long 0x154 4. "ODE,EMMC1_CMD PAD Opn Drain Mode enable" "0,1" newline bitfld.long 0x154 0.--2. "MUX,EMMC1_CMD PAD Pin-mux func select" "0,1,2,3,4,5,6,7" line.long 0x158 "PIN_MUX_CONFIG_EMMC1_DATA0,PAD EMMC1_DATA0 pin-mux config register" bitfld.long 0x158 12. "FV,EMMC1_DATA0 PAD Force Input Value when fin=0x2" "0,1" bitfld.long 0x158 8.--9. "FIN,EMMC1_DATA0 PAD Force Input On/Off mode" "0,1,2,3" bitfld.long 0x158 4. "ODE,EMMC1_DATA0 PAD Opn Drain Mode enable" "0,1" newline bitfld.long 0x158 0.--2. "MUX,EMMC1_DATA0 PAD Pin-mux func select" "0,1,2,3,4,5,6,7" line.long 0x15C "PIN_MUX_CONFIG_EMMC1_DATA1,PAD EMMC1_DATA1 pin-mux config register" bitfld.long 0x15C 12. "FV,EMMC1_DATA1 PAD Force Input Value when fin=0x2" "0,1" bitfld.long 0x15C 8.--9. "FIN,EMMC1_DATA1 PAD Force Input On/Off mode" "0,1,2,3" bitfld.long 0x15C 4. "ODE,EMMC1_DATA1 PAD Opn Drain Mode enable" "0,1" newline bitfld.long 0x15C 0.--2. "MUX,EMMC1_DATA1 PAD Pin-mux func select" "0,1,2,3,4,5,6,7" line.long 0x160 "PIN_MUX_CONFIG_EMMC1_DATA2,PAD EMMC1_DATA2 pin-mux config register" bitfld.long 0x160 12. "FV,EMMC1_DATA2 PAD Force Input Value when fin=0x2" "0,1" bitfld.long 0x160 8.--9. "FIN,EMMC1_DATA2 PAD Force Input On/Off mode" "0,1,2,3" bitfld.long 0x160 4. "ODE,EMMC1_DATA2 PAD Opn Drain Mode enable" "0,1" newline bitfld.long 0x160 0.--2. "MUX,EMMC1_DATA2 PAD Pin-mux func select" "0,1,2,3,4,5,6,7" line.long 0x164 "PIN_MUX_CONFIG_EMMC1_DATA3,PAD EMMC1_DATA3 pin-mux config register" bitfld.long 0x164 12. "FV,EMMC1_DATA3 PAD Force Input Value when fin=0x2" "0,1" bitfld.long 0x164 8.--9. "FIN,EMMC1_DATA3 PAD Force Input On/Off mode" "0,1,2,3" bitfld.long 0x164 4. "ODE,EMMC1_DATA3 PAD Opn Drain Mode enable" "0,1" newline bitfld.long 0x164 0.--2. "MUX,EMMC1_DATA3 PAD Pin-mux func select" "0,1,2,3,4,5,6,7" line.long 0x168 "PIN_MUX_CONFIG_EMMC1_DATA4,PAD EMMC1_DATA4 pin-mux config register" bitfld.long 0x168 12. "FV,EMMC1_DATA4 PAD Force Input Value when fin=0x2" "0,1" bitfld.long 0x168 8.--9. "FIN,EMMC1_DATA4 PAD Force Input On/Off mode" "0,1,2,3" bitfld.long 0x168 4. "ODE,EMMC1_DATA4 PAD Opn Drain Mode enable" "0,1" newline bitfld.long 0x168 0.--2. "MUX,EMMC1_DATA4 PAD Pin-mux func select" "0,1,2,3,4,5,6,7" line.long 0x16C "PIN_MUX_CONFIG_EMMC1_DATA5,PAD EMMC1_DATA5 pin-mux config register" bitfld.long 0x16C 12. "FV,EMMC1_DATA5 PAD Force Input Value when fin=0x2" "0,1" bitfld.long 0x16C 8.--9. "FIN,EMMC1_DATA5 PAD Force Input On/Off mode" "0,1,2,3" bitfld.long 0x16C 4. "ODE,EMMC1_DATA5 PAD Opn Drain Mode enable" "0,1" newline bitfld.long 0x16C 0.--2. "MUX,EMMC1_DATA5 PAD Pin-mux func select" "0,1,2,3,4,5,6,7" line.long 0x170 "PIN_MUX_CONFIG_EMMC1_DATA6,PAD EMMC1_DATA6 pin-mux config register" bitfld.long 0x170 12. "FV,EMMC1_DATA6 PAD Force Input Value when fin=0x2" "0,1" bitfld.long 0x170 8.--9. "FIN,EMMC1_DATA6 PAD Force Input On/Off mode" "0,1,2,3" bitfld.long 0x170 4. "ODE,EMMC1_DATA6 PAD Opn Drain Mode enable" "0,1" newline bitfld.long 0x170 0.--2. "MUX,EMMC1_DATA6 PAD Pin-mux func select" "0,1,2,3,4,5,6,7" line.long 0x174 "PIN_MUX_CONFIG_EMMC1_DATA7,PAD EMMC1_DATA7 pin-mux config register" bitfld.long 0x174 12. "FV,EMMC1_DATA7 PAD Force Input Value when fin=0x2" "0,1" bitfld.long 0x174 8.--9. "FIN,EMMC1_DATA7 PAD Force Input On/Off mode" "0,1,2,3" bitfld.long 0x174 4. "ODE,EMMC1_DATA7 PAD Opn Drain Mode enable" "0,1" newline bitfld.long 0x174 0.--2. "MUX,EMMC1_DATA7 PAD Pin-mux func select" "0,1,2,3,4,5,6,7" line.long 0x178 "PIN_MUX_CONFIG_EMMC1_STROBE,PAD EMMC1_STROBE pin-mux config register" bitfld.long 0x178 12. "FV,EMMC1_STROBE PAD Force Input Value when fin=0x2" "0,1" bitfld.long 0x178 8.--9. "FIN,EMMC1_STROBE PAD Force Input On/Off mode" "0,1,2,3" bitfld.long 0x178 4. "ODE,EMMC1_STROBE PAD Opn Drain Mode enable" "0,1" newline bitfld.long 0x178 0.--2. "MUX,EMMC1_STROBE PAD Pin-mux func select" "0,1,2,3,4,5,6,7" line.long 0x17C "PIN_MUX_CONFIG_EMMC1_RESET_N,PAD EMMC1_RESET_N pin-mux config register" bitfld.long 0x17C 12. "FV,EMMC1_RESET_N PAD Force Input Value when fin=0x2" "0,1" bitfld.long 0x17C 8.--9. "FIN,EMMC1_RESET_N PAD Force Input On/Off mode" "0,1,2,3" bitfld.long 0x17C 4. "ODE,EMMC1_RESET_N PAD Opn Drain Mode enable" "0,1" newline bitfld.long 0x17C 0.--2. "MUX,EMMC1_RESET_N PAD Pin-mux func select" "0,1,2,3,4,5,6,7" line.long 0x180 "PIN_MUX_CONFIG_EMMC2_CLK,PAD EMMC2_CLK pin-mux config register" bitfld.long 0x180 12. "FV,EMMC2_CLK PAD Force Input Value when fin=0x2" "0,1" bitfld.long 0x180 8.--9. "FIN,EMMC2_CLK PAD Force Input On/Off mode" "0,1,2,3" bitfld.long 0x180 4. "ODE,EMMC2_CLK PAD Opn Drain Mode enable" "0,1" newline bitfld.long 0x180 0.--2. "MUX,EMMC2_CLK PAD Pin-mux func select" "0,1,2,3,4,5,6,7" line.long 0x184 "PIN_MUX_CONFIG_EMMC2_CMD,PAD EMMC2_CMD pin-mux config register" bitfld.long 0x184 12. "FV,EMMC2_CMD PAD Force Input Value when fin=0x2" "0,1" bitfld.long 0x184 8.--9. "FIN,EMMC2_CMD PAD Force Input On/Off mode" "0,1,2,3" bitfld.long 0x184 4. "ODE,EMMC2_CMD PAD Opn Drain Mode enable" "0,1" newline bitfld.long 0x184 0.--2. "MUX,EMMC2_CMD PAD Pin-mux func select" "0,1,2,3,4,5,6,7" line.long 0x188 "PIN_MUX_CONFIG_EMMC2_DATA0,PAD EMMC2_DATA0 pin-mux config register" bitfld.long 0x188 12. "FV,EMMC2_DATA0 PAD Force Input Value when fin=0x2" "0,1" bitfld.long 0x188 8.--9. "FIN,EMMC2_DATA0 PAD Force Input On/Off mode" "0,1,2,3" bitfld.long 0x188 4. "ODE,EMMC2_DATA0 PAD Opn Drain Mode enable" "0,1" newline bitfld.long 0x188 0.--2. "MUX,EMMC2_DATA0 PAD Pin-mux func select" "0,1,2,3,4,5,6,7" line.long 0x18C "PIN_MUX_CONFIG_EMMC2_DATA1,PAD EMMC2_DATA1 pin-mux config register" bitfld.long 0x18C 12. "FV,EMMC2_DATA1 PAD Force Input Value when fin=0x2" "0,1" bitfld.long 0x18C 8.--9. "FIN,EMMC2_DATA1 PAD Force Input On/Off mode" "0,1,2,3" bitfld.long 0x18C 4. "ODE,EMMC2_DATA1 PAD Opn Drain Mode enable" "0,1" newline bitfld.long 0x18C 0.--2. "MUX,EMMC2_DATA1 PAD Pin-mux func select" "0,1,2,3,4,5,6,7" line.long 0x190 "PIN_MUX_CONFIG_EMMC2_DATA2,PAD EMMC2_DATA2 pin-mux config register" bitfld.long 0x190 12. "FV,EMMC2_DATA2 PAD Force Input Value when fin=0x2" "0,1" bitfld.long 0x190 8.--9. "FIN,EMMC2_DATA2 PAD Force Input On/Off mode" "0,1,2,3" bitfld.long 0x190 4. "ODE,EMMC2_DATA2 PAD Opn Drain Mode enable" "0,1" newline bitfld.long 0x190 0.--2. "MUX,EMMC2_DATA2 PAD Pin-mux func select" "0,1,2,3,4,5,6,7" line.long 0x194 "PIN_MUX_CONFIG_EMMC2_DATA3,PAD EMMC2_DATA3 pin-mux config register" bitfld.long 0x194 12. "FV,EMMC2_DATA3 PAD Force Input Value when fin=0x2" "0,1" bitfld.long 0x194 8.--9. "FIN,EMMC2_DATA3 PAD Force Input On/Off mode" "0,1,2,3" bitfld.long 0x194 4. "ODE,EMMC2_DATA3 PAD Opn Drain Mode enable" "0,1" newline bitfld.long 0x194 0.--2. "MUX,EMMC2_DATA3 PAD Pin-mux func select" "0,1,2,3,4,5,6,7" line.long 0x198 "PIN_MUX_CONFIG_EMMC2_DATA4,PAD EMMC2_DATA4 pin-mux config register" bitfld.long 0x198 12. "FV,EMMC2_DATA4 PAD Force Input Value when fin=0x2" "0,1" bitfld.long 0x198 8.--9. "FIN,EMMC2_DATA4 PAD Force Input On/Off mode" "0,1,2,3" bitfld.long 0x198 4. "ODE,EMMC2_DATA4 PAD Opn Drain Mode enable" "0,1" newline bitfld.long 0x198 0.--2. "MUX,EMMC2_DATA4 PAD Pin-mux func select" "0,1,2,3,4,5,6,7" line.long 0x19C "PIN_MUX_CONFIG_EMMC2_DATA5,PAD EMMC2_DATA5 pin-mux config register" bitfld.long 0x19C 12. "FV,EMMC2_DATA5 PAD Force Input Value when fin=0x2" "0,1" bitfld.long 0x19C 8.--9. "FIN,EMMC2_DATA5 PAD Force Input On/Off mode" "0,1,2,3" bitfld.long 0x19C 4. "ODE,EMMC2_DATA5 PAD Opn Drain Mode enable" "0,1" newline bitfld.long 0x19C 0.--2. "MUX,EMMC2_DATA5 PAD Pin-mux func select" "0,1,2,3,4,5,6,7" line.long 0x1A0 "PIN_MUX_CONFIG_EMMC2_DATA6,PAD EMMC2_DATA6 pin-mux config register" bitfld.long 0x1A0 12. "FV,EMMC2_DATA6 PAD Force Input Value when fin=0x2" "0,1" bitfld.long 0x1A0 8.--9. "FIN,EMMC2_DATA6 PAD Force Input On/Off mode" "0,1,2,3" bitfld.long 0x1A0 4. "ODE,EMMC2_DATA6 PAD Opn Drain Mode enable" "0,1" newline bitfld.long 0x1A0 0.--2. "MUX,EMMC2_DATA6 PAD Pin-mux func select" "0,1,2,3,4,5,6,7" line.long 0x1A4 "PIN_MUX_CONFIG_EMMC2_DATA7,PAD EMMC2_DATA7 pin-mux config register" bitfld.long 0x1A4 12. "FV,EMMC2_DATA7 PAD Force Input Value when fin=0x2" "0,1" bitfld.long 0x1A4 8.--9. "FIN,EMMC2_DATA7 PAD Force Input On/Off mode" "0,1,2,3" bitfld.long 0x1A4 4. "ODE,EMMC2_DATA7 PAD Opn Drain Mode enable" "0,1" newline bitfld.long 0x1A4 0.--2. "MUX,EMMC2_DATA7 PAD Pin-mux func select" "0,1,2,3,4,5,6,7" line.long 0x1A8 "PIN_MUX_CONFIG_EMMC2_STROBE,PAD EMMC2_STROBE pin-mux config register" bitfld.long 0x1A8 12. "FV,EMMC2_STROBE PAD Force Input Value when fin=0x2" "0,1" bitfld.long 0x1A8 8.--9. "FIN,EMMC2_STROBE PAD Force Input On/Off mode" "0,1,2,3" bitfld.long 0x1A8 4. "ODE,EMMC2_STROBE PAD Opn Drain Mode enable" "0,1" newline bitfld.long 0x1A8 0.--2. "MUX,EMMC2_STROBE PAD Pin-mux func select" "0,1,2,3,4,5,6,7" line.long 0x1AC "PIN_MUX_CONFIG_EMMC2_RESET_N,PAD EMMC2_RESET_N pin-mux config register" bitfld.long 0x1AC 12. "FV,EMMC2_RESET_N PAD Force Input Value when fin=0x2" "0,1" bitfld.long 0x1AC 8.--9. "FIN,EMMC2_RESET_N PAD Force Input On/Off mode" "0,1,2,3" bitfld.long 0x1AC 4. "ODE,EMMC2_RESET_N PAD Opn Drain Mode enable" "0,1" newline bitfld.long 0x1AC 0.--2. "MUX,EMMC2_RESET_N PAD Pin-mux func select" "0,1,2,3,4,5,6,7" group.long 0x400++0x19B line.long 0x0 "INPUT_SOURCE_SELECT_I2C5_SCL,I2C5_SCL input source select register" bitfld.long 0x0 0. "SRC_SEL,source select" "0,1" line.long 0x4 "INPUT_SOURCE_SELECT_SPI6_SCLK,SPI6_SCLK input source select register" bitfld.long 0x4 0. "SRC_SEL,source select" "0,1" line.long 0x8 "INPUT_SOURCE_SELECT_MSHC4_CARD_DET_N,MSHC4_CARD_DET_N input source select register" bitfld.long 0x8 0. "SRC_SEL,source select" "0,1" line.long 0xC "INPUT_SOURCE_SELECT_I2C5_SDA,I2C5_SDA input source select register" bitfld.long 0xC 0. "SRC_SEL,source select" "0,1" line.long 0x10 "INPUT_SOURCE_SELECT_SPI6_MISO,SPI6_MISO input source select register" bitfld.long 0x10 0. "SRC_SEL,source select" "0,1" line.long 0x14 "INPUT_SOURCE_SELECT_CANFD5_RX,CANFD5_RX input source select register" bitfld.long 0x14 0.--1. "SRC_SEL,source select" "0,1,2,3" line.long 0x18 "INPUT_SOURCE_SELECT_MSHC4_WP,MSHC4_WP input source select register" bitfld.long 0x18 0. "SRC_SEL,source select" "0,1" line.long 0x1C "INPUT_SOURCE_SELECT_USB_SS_USB1_OC,USB_SS_USB1_OC input source select register" bitfld.long 0x1C 0.--2. "SRC_SEL,source select" "0,1,2,3,4,5,6,7" line.long 0x20 "INPUT_SOURCE_SELECT_I2C6_SCL,I2C6_SCL input source select register" bitfld.long 0x20 0. "SRC_SEL,source select" "0,1" line.long 0x24 "INPUT_SOURCE_SELECT_SPI6_MOSI,SPI6_MOSI input source select register" bitfld.long 0x24 0. "SRC_SEL,source select" "0,1" line.long 0x28 "INPUT_SOURCE_SELECT_I2C6_SDA,I2C6_SDA input source select register" bitfld.long 0x28 0. "SRC_SEL,source select" "0,1" line.long 0x2C "INPUT_SOURCE_SELECT_SPI6_SS,SPI6_SS input source select register" bitfld.long 0x2C 0. "SRC_SEL,source select" "0,1" line.long 0x30 "INPUT_SOURCE_SELECT_CANFD6_RX,CANFD6_RX input source select register" bitfld.long 0x30 0.--1. "SRC_SEL,source select" "0,1,2,3" line.long 0x34 "INPUT_SOURCE_SELECT_USB_SS_USB2_OC,USB_SS_USB2_OC input source select register" bitfld.long 0x34 0.--2. "SRC_SEL,source select" "0,1,2,3,4,5,6,7" line.long 0x38 "INPUT_SOURCE_SELECT_I2C7_SCL,I2C7_SCL input source select register" bitfld.long 0x38 0.--1. "SRC_SEL,source select" "0,1,2,3" line.long 0x3C "INPUT_SOURCE_SELECT_MSHC3_CARD_DET_N,MSHC3_CARD_DET_N input source select register" bitfld.long 0x3C 0. "SRC_SEL,source select" "0,1" line.long 0x40 "INPUT_SOURCE_SELECT_PCIE_SS_PCIEX2_CLKREQ_N,PCIE_SS_PCIEX2_CLKREQ_N input source select register" bitfld.long 0x40 0.--1. "SRC_SEL,source select" "0,1,2,3" line.long 0x44 "INPUT_SOURCE_SELECT_I2C7_SDA,I2C7_SDA input source select register" bitfld.long 0x44 0.--1. "SRC_SEL,source select" "0,1,2,3" line.long 0x48 "INPUT_SOURCE_SELECT_MSHC3_WP,MSHC3_WP input source select register" bitfld.long 0x48 0. "SRC_SEL,source select" "0,1" line.long 0x4C "INPUT_SOURCE_SELECT_PCIE_SS_PCIEX1_CLKREQ_N,PCIE_SS_PCIEX1_CLKREQ_N input source select register" bitfld.long 0x4C 0.--1. "SRC_SEL,source select" "0,1,2,3" line.long 0x50 "INPUT_SOURCE_SELECT_I2C8_SCL,I2C8_SCL input source select register" bitfld.long 0x50 0.--1. "SRC_SEL,source select" "0,1,2,3" line.long 0x54 "INPUT_SOURCE_SELECT_ENET2_MDIO,ENET2_MDIO input source select register" bitfld.long 0x54 0.--2. "SRC_SEL,source select" "0,1,2,3,4,5,6,7" line.long 0x58 "INPUT_SOURCE_SELECT_MSHC3_VOLT_SW,MSHC3_VOLT_SW input source select register" bitfld.long 0x58 0. "SRC_SEL,source select" "0,1" line.long 0x5C "INPUT_SOURCE_SELECT_I2C8_SDA,I2C8_SDA input source select register" bitfld.long 0x5C 0.--1. "SRC_SEL,source select" "0,1,2,3" line.long 0x60 "INPUT_SOURCE_SELECT_SPI5_SCLK,SPI5_SCLK input source select register" bitfld.long 0x60 0.--1. "SRC_SEL,source select" "0,1,2,3" line.long 0x64 "INPUT_SOURCE_SELECT_SPI5_MISO,SPI5_MISO input source select register" bitfld.long 0x64 0.--1. "SRC_SEL,source select" "0,1,2,3" line.long 0x68 "INPUT_SOURCE_SELECT_UART11_RX,UART11_RX input source select register" bitfld.long 0x68 0.--1. "SRC_SEL,source select" "0,1,2,3" line.long 0x6C "INPUT_SOURCE_SELECT_SPI5_MOSI,SPI5_MOSI input source select register" bitfld.long 0x6C 0.--1. "SRC_SEL,source select" "0,1,2,3" line.long 0x70 "INPUT_SOURCE_SELECT_SPI5_SS,SPI5_SS input source select register" bitfld.long 0x70 0.--1. "SRC_SEL,source select" "0,1,2,3" line.long 0x74 "INPUT_SOURCE_SELECT_UART12_RX,UART12_RX input source select register" bitfld.long 0x74 0. "SRC_SEL,source select" "0,1" line.long 0x78 "INPUT_SOURCE_SELECT_I2C13_SCL,I2C13_SCL input source select register" bitfld.long 0x78 0.--1. "SRC_SEL,source select" "0,1,2,3" line.long 0x7C "INPUT_SOURCE_SELECT_PCIE_SS_PCIEX1_PERST_N,PCIE_SS_PCIEX1_PERST_N input source select register" bitfld.long 0x7C 0.--1. "SRC_SEL,source select" "0,1,2,3" line.long 0x80 "INPUT_SOURCE_SELECT_I2C13_SDA,I2C13_SDA input source select register" bitfld.long 0x80 0.--1. "SRC_SEL,source select" "0,1,2,3" line.long 0x84 "INPUT_SOURCE_SELECT_CANFD7_RX,CANFD7_RX input source select register" bitfld.long 0x84 0.--1. "SRC_SEL,source select" "0,1,2,3" line.long 0x88 "INPUT_SOURCE_SELECT_PCIE_SS_PCIEX1_WAKE_N,PCIE_SS_PCIEX1_WAKE_N input source select register" bitfld.long 0x88 0.--1. "SRC_SEL,source select" "0,1,2,3" line.long 0x8C "INPUT_SOURCE_SELECT_I2C14_SCL,I2C14_SCL input source select register" bitfld.long 0x8C 0.--1. "SRC_SEL,source select" "0,1,2,3" line.long 0x90 "INPUT_SOURCE_SELECT_PCIE_SS_PCIEX2_PERST_N,PCIE_SS_PCIEX2_PERST_N input source select register" bitfld.long 0x90 0.--1. "SRC_SEL,source select" "0,1,2,3" line.long 0x94 "INPUT_SOURCE_SELECT_I2C14_SDA,I2C14_SDA input source select register" bitfld.long 0x94 0.--1. "SRC_SEL,source select" "0,1,2,3" line.long 0x98 "INPUT_SOURCE_SELECT_CANFD8_RX,CANFD8_RX input source select register" bitfld.long 0x98 0.--1. "SRC_SEL,source select" "0,1,2,3" line.long 0x9C "INPUT_SOURCE_SELECT_PCIE_SS_PCIEX2_WAKE_N,PCIE_SS_PCIEX2_WAKE_N input source select register" bitfld.long 0x9C 0.--1. "SRC_SEL,source select" "0,1,2,3" line.long 0xA0 "INPUT_SOURCE_SELECT_SPI8_SCLK,SPI8_SCLK input source select register" bitfld.long 0xA0 0.--1. "SRC_SEL,source select" "0,1,2,3" line.long 0xA4 "INPUT_SOURCE_SELECT_SPI8_MISO,SPI8_MISO input source select register" bitfld.long 0xA4 0.--1. "SRC_SEL,source select" "0,1,2,3" line.long 0xA8 "INPUT_SOURCE_SELECT_SPI8_MOSI,SPI8_MOSI input source select register" bitfld.long 0xA8 0.--1. "SRC_SEL,source select" "0,1,2,3" line.long 0xAC "INPUT_SOURCE_SELECT_SPDIF3_IN,SPDIF3_IN input source select register" bitfld.long 0xAC 0. "SRC_SEL,source select" "0,1" line.long 0xB0 "INPUT_SOURCE_SELECT_SPI8_SS,SPI8_SS input source select register" bitfld.long 0xB0 0.--1. "SRC_SEL,source select" "0,1,2,3" line.long 0xB4 "INPUT_SOURCE_SELECT_UART13_RX,UART13_RX input source select register" bitfld.long 0xB4 0.--1. "SRC_SEL,source select" "0,1,2,3" line.long 0xB8 "INPUT_SOURCE_SELECT_UART14_CTS,UART14_CTS input source select register" bitfld.long 0xB8 0. "SRC_SEL,source select" "0,1" line.long 0xBC "INPUT_SOURCE_SELECT_I2C12_SCL,I2C12_SCL input source select register" bitfld.long 0xBC 0. "SRC_SEL,source select" "0,1" line.long 0xC0 "INPUT_SOURCE_SELECT_SPDIF4_IN,SPDIF4_IN input source select register" bitfld.long 0xC0 0. "SRC_SEL,source select" "0,1" line.long 0xC4 "INPUT_SOURCE_SELECT_UART14_RX,UART14_RX input source select register" bitfld.long 0xC4 0. "SRC_SEL,source select" "0,1" line.long 0xC8 "INPUT_SOURCE_SELECT_I2C12_SDA,I2C12_SDA input source select register" bitfld.long 0xC8 0. "SRC_SEL,source select" "0,1" line.long 0xCC "INPUT_SOURCE_SELECT_SPI7_SCLK,SPI7_SCLK input source select register" bitfld.long 0xCC 0. "SRC_SEL,source select" "0,1" line.long 0xD0 "INPUT_SOURCE_SELECT_SPI7_MISO,SPI7_MISO input source select register" bitfld.long 0xD0 0. "SRC_SEL,source select" "0,1" line.long 0xD4 "INPUT_SOURCE_SELECT_UART15_RX,UART15_RX input source select register" bitfld.long 0xD4 0.--1. "SRC_SEL,source select" "0,1,2,3" line.long 0xD8 "INPUT_SOURCE_SELECT_UART16_CTS,UART16_CTS input source select register" bitfld.long 0xD8 0.--1. "SRC_SEL,source select" "0,1,2,3" line.long 0xDC "INPUT_SOURCE_SELECT_SPI7_MOSI,SPI7_MOSI input source select register" bitfld.long 0xDC 0. "SRC_SEL,source select" "0,1" line.long 0xE0 "INPUT_SOURCE_SELECT_TIMER6_CH2,TIMER6_CH2 input source select register" bitfld.long 0xE0 0. "SRC_SEL,source select" "0,1" line.long 0xE4 "INPUT_SOURCE_SELECT_SPI7_SS,SPI7_SS input source select register" bitfld.long 0xE4 0. "SRC_SEL,source select" "0,1" line.long 0xE8 "INPUT_SOURCE_SELECT_UART16_RX,UART16_RX input source select register" bitfld.long 0xE8 0.--1. "SRC_SEL,source select" "0,1,2,3" line.long 0xEC "INPUT_SOURCE_SELECT_TIMER6_CH3,TIMER6_CH3 input source select register" bitfld.long 0xEC 0. "SRC_SEL,source select" "0,1" line.long 0xF0 "INPUT_SOURCE_SELECT_I2C15_SCL,I2C15_SCL input source select register" bitfld.long 0xF0 0.--1. "SRC_SEL,source select" "0,1,2,3" line.long 0xF4 "INPUT_SOURCE_SELECT_I2C15_SDA,I2C15_SDA input source select register" bitfld.long 0xF4 0.--1. "SRC_SEL,source select" "0,1,2,3" line.long 0xF8 "INPUT_SOURCE_SELECT_I2C16_SCL,I2C16_SCL input source select register" bitfld.long 0xF8 0.--1. "SRC_SEL,source select" "0,1,2,3" line.long 0xFC "INPUT_SOURCE_SELECT_I2C16_SDA,I2C16_SDA input source select register" bitfld.long 0xFC 0.--1. "SRC_SEL,source select" "0,1,2,3" line.long 0x100 "INPUT_SOURCE_SELECT_I2S_MC2_SCKO,I2S_MC2_SCKO input source select register" bitfld.long 0x100 0.--1. "SRC_SEL,source select" "0,1,2,3" line.long 0x104 "INPUT_SOURCE_SELECT_I2S_MC2_WSO,I2S_MC2_WSO input source select register" bitfld.long 0x104 0.--1. "SRC_SEL,source select" "0,1,2,3" line.long 0x108 "INPUT_SOURCE_SELECT_I2S_MC2_SDI0_SDO0,I2S_MC2_SDI0_SDO0 input source select register" bitfld.long 0x108 0.--1. "SRC_SEL,source select" "0,1,2,3" line.long 0x10C "INPUT_SOURCE_SELECT_I2S_MC2_SDI1_SDO1,I2S_MC2_SDI1_SDO1 input source select register" bitfld.long 0x10C 0.--1. "SRC_SEL,source select" "0,1,2,3" line.long 0x110 "INPUT_SOURCE_SELECT_I2S_MC2_SDI2_SDO2,I2S_MC2_SDI2_SDO2 input source select register" bitfld.long 0x110 0.--1. "SRC_SEL,source select" "0,1,2,3" line.long 0x114 "INPUT_SOURCE_SELECT_I2S_MC2_SDI3_SDO3,I2S_MC2_SDI3_SDO3 input source select register" bitfld.long 0x114 0.--1. "SRC_SEL,source select" "0,1,2,3" line.long 0x118 "INPUT_SOURCE_SELECT_I2S_MC2_SDI4_SDO4,I2S_MC2_SDI4_SDO4 input source select register" bitfld.long 0x118 0.--1. "SRC_SEL,source select" "0,1,2,3" line.long 0x11C "INPUT_SOURCE_SELECT_I2S_MC2_SDI5_SDO5,I2S_MC2_SDI5_SDO5 input source select register" bitfld.long 0x11C 0.--1. "SRC_SEL,source select" "0,1,2,3" line.long 0x120 "INPUT_SOURCE_SELECT_I2S_MC2_SDI6_SDO6,I2S_MC2_SDI6_SDO6 input source select register" bitfld.long 0x120 0.--1. "SRC_SEL,source select" "0,1,2,3" line.long 0x124 "INPUT_SOURCE_SELECT_I2S_MC2_SDI7_SDO7,I2S_MC2_SDI7_SDO7 input source select register" bitfld.long 0x124 0.--1. "SRC_SEL,source select" "0,1,2,3" line.long 0x128 "INPUT_SOURCE_SELECT_OSPI2_DQS,OSPI2_DQS input source select register" bitfld.long 0x128 0. "SRC_SEL,source select" "0,1" line.long 0x12C "INPUT_SOURCE_SELECT_I2S_MC2_WSI,I2S_MC2_WSI input source select register" bitfld.long 0x12C 0.--1. "SRC_SEL,source select" "0,1,2,3" line.long 0x130 "INPUT_SOURCE_SELECT_I2S_MC2_SCKI,I2S_MC2_SCKI input source select register" bitfld.long 0x130 0.--1. "SRC_SEL,source select" "0,1,2,3" line.long 0x134 "INPUT_SOURCE_SELECT_I2S_SC3_SCK,I2S_SC3_SCK input source select register" bitfld.long 0x134 0. "SRC_SEL,source select" "0,1" line.long 0x138 "INPUT_SOURCE_SELECT_I2S_SC3_WS,I2S_SC3_WS input source select register" bitfld.long 0x138 0. "SRC_SEL,source select" "0,1" line.long 0x13C "INPUT_SOURCE_SELECT_I2S_SC3_SDI_SDO,I2S_SC3_SDI_SDO input source select register" bitfld.long 0x13C 0.--1. "SRC_SEL,source select" "0,1,2,3" line.long 0x140 "INPUT_SOURCE_SELECT_I2S_SC4_SCK,I2S_SC4_SCK input source select register" bitfld.long 0x140 0. "SRC_SEL,source select" "0,1" line.long 0x144 "INPUT_SOURCE_SELECT_I2S_SC4_WS,I2S_SC4_WS input source select register" bitfld.long 0x144 0. "SRC_SEL,source select" "0,1" line.long 0x148 "INPUT_SOURCE_SELECT_I2S_SC4_SDI_SDO,I2S_SC4_SDI_SDO input source select register" bitfld.long 0x148 0.--1. "SRC_SEL,source select" "0,1,2,3" line.long 0x14C "INPUT_SOURCE_SELECT_I2S_SC6_SDI_SDO,I2S_SC6_SDI_SDO input source select register" bitfld.long 0x14C 0. "SRC_SEL,source select" "0,1" line.long 0x150 "INPUT_SOURCE_SELECT_I2S_SC5_SDI_SDO,I2S_SC5_SDI_SDO input source select register" bitfld.long 0x150 0. "SRC_SEL,source select" "0,1" line.long 0x154 "INPUT_SOURCE_SELECT_I2S_SC7_SCK,I2S_SC7_SCK input source select register" bitfld.long 0x154 0. "SRC_SEL,source select" "0,1" line.long 0x158 "INPUT_SOURCE_SELECT_I2S_MC1_SCKO,I2S_MC1_SCKO input source select register" bitfld.long 0x158 0.--1. "SRC_SEL,source select" "0,1,2,3" line.long 0x15C "INPUT_SOURCE_SELECT_I2S_SC7_WS,I2S_SC7_WS input source select register" bitfld.long 0x15C 0. "SRC_SEL,source select" "0,1" line.long 0x160 "INPUT_SOURCE_SELECT_I2S_MC1_WSO,I2S_MC1_WSO input source select register" bitfld.long 0x160 0.--1. "SRC_SEL,source select" "0,1,2,3" line.long 0x164 "INPUT_SOURCE_SELECT_I2S_SC8_SDI_SDO,I2S_SC8_SDI_SDO input source select register" bitfld.long 0x164 0.--2. "SRC_SEL,source select" "0,1,2,3,4,5,6,7" line.long 0x168 "INPUT_SOURCE_SELECT_I2S_MC1_SDI4_SDO4,I2S_MC1_SDI4_SDO4 input source select register" bitfld.long 0x168 0.--1. "SRC_SEL,source select" "0,1,2,3" line.long 0x16C "INPUT_SOURCE_SELECT_I2S_SC8_SCK,I2S_SC8_SCK input source select register" bitfld.long 0x16C 0.--1. "SRC_SEL,source select" "0,1,2,3" line.long 0x170 "INPUT_SOURCE_SELECT_I2S_MC1_SDI5_SDO5,I2S_MC1_SDI5_SDO5 input source select register" bitfld.long 0x170 0.--1. "SRC_SEL,source select" "0,1,2,3" line.long 0x174 "INPUT_SOURCE_SELECT_I2S_SC8_WS,I2S_SC8_WS input source select register" bitfld.long 0x174 0.--1. "SRC_SEL,source select" "0,1,2,3" line.long 0x178 "INPUT_SOURCE_SELECT_I2S_MC1_SDI6_SDO6,I2S_MC1_SDI6_SDO6 input source select register" bitfld.long 0x178 0.--1. "SRC_SEL,source select" "0,1,2,3" line.long 0x17C "INPUT_SOURCE_SELECT_I2S_SC7_SDI_SDO,I2S_SC7_SDI_SDO input source select register" bitfld.long 0x17C 0.--1. "SRC_SEL,source select" "0,1,2,3" line.long 0x180 "INPUT_SOURCE_SELECT_I2S_MC1_SDI7_SDO7,I2S_MC1_SDI7_SDO7 input source select register" bitfld.long 0x180 0.--1. "SRC_SEL,source select" "0,1,2,3" line.long 0x184 "INPUT_SOURCE_SELECT_I2S_MC1_SCKI,I2S_MC1_SCKI input source select register" bitfld.long 0x184 0.--1. "SRC_SEL,source select" "0,1,2,3" line.long 0x188 "INPUT_SOURCE_SELECT_I2S_MC1_WSI,I2S_MC1_WSI input source select register" bitfld.long 0x188 0.--1. "SRC_SEL,source select" "0,1,2,3" line.long 0x18C "INPUT_SOURCE_SELECT_I2S_MC1_SDI0_SDO0,I2S_MC1_SDI0_SDO0 input source select register" bitfld.long 0x18C 0. "SRC_SEL,source select" "0,1" line.long 0x190 "INPUT_SOURCE_SELECT_I2S_MC1_SDI1_SDO1,I2S_MC1_SDI1_SDO1 input source select register" bitfld.long 0x190 0. "SRC_SEL,source select" "0,1" line.long 0x194 "INPUT_SOURCE_SELECT_I2S_MC1_SDI2_SDO2,I2S_MC1_SDI2_SDO2 input source select register" bitfld.long 0x194 0. "SRC_SEL,source select" "0,1" line.long 0x198 "INPUT_SOURCE_SELECT_I2S_MC1_SDI3_SDO3,I2S_MC1_SDI3_SDO3 input source select register" bitfld.long 0x198 0. "SRC_SEL,source select" "0,1" tree.end tree "PINCTRL_RTC" base ad:0xF1860000 group.long 0x0++0x2F line.long 0x0 "IO_PAD_CONFIG_SYS_MODE0,PAD SYS_MODE0 config register" bitfld.long 0x0 16. "POE,SYS_MODE0 PAD Parametric output enable" "0,1" bitfld.long 0x0 12. "IS,SYS_MODE0 PAD Input select" "0,1" line.long 0x4 "IO_PAD_CONFIG_SYS_MODE1,PAD SYS_MODE1 config register" bitfld.long 0x4 16. "POE,SYS_MODE1 PAD Parametric output enable" "0,1" bitfld.long 0x4 12. "IS,SYS_MODE1 PAD Input select" "0,1" line.long 0x8 "IO_PAD_CONFIG_SYS_RESET_N,PAD SYS_RESET_N config register" bitfld.long 0x8 16. "POE,SYS_RESET_N PAD Parametric output enable" "0,1" bitfld.long 0x8 12. "IS,SYS_RESET_N PAD Input select" "0,1" line.long 0xC "IO_PAD_CONFIG_AP_RESET_N,PAD AP_RESET_N config register" bitfld.long 0xC 16. "POE,AP_RESET_N PAD Parametric output enable" "0,1" bitfld.long 0xC 12. "IS,AP_RESET_N PAD Input select" "0,1" line.long 0x10 "IO_PAD_CONFIG_RTC_RESET_N,PAD RTC_RESET_N config register" bitfld.long 0x10 16. "POE,RTC_RESET_N PAD Parametric output enable" "0,1" bitfld.long 0x10 12. "IS,RTC_RESET_N PAD Input select" "0,1" line.long 0x14 "IO_PAD_CONFIG_SYS_PWR_ON,PAD SYS_PWR_ON config register" bitfld.long 0x14 16. "POE,SYS_PWR_ON PAD Parametric output enable" "0,1" bitfld.long 0x14 12. "IS,SYS_PWR_ON PAD Input select" "0,1" bitfld.long 0x14 8. "SR,SYS_PWR_ON PAD Slew rate" "0,1" bitfld.long 0x14 4.--5. "DS,SYS_PWR_ON PAD Driver select" "0,1,2,3" newline bitfld.long 0x14 1. "PS,SYS_PWR_ON PAD Pull select" "0,1" bitfld.long 0x14 0. "PE,SYS_PWR_ON PAD Pull enable" "0,1" line.long 0x18 "IO_PAD_CONFIG_SYS_WAKEUP0,PAD SYS_WAKEUP0 config register" bitfld.long 0x18 16. "POE,SYS_WAKEUP0 PAD Parametric output enable" "0,1" bitfld.long 0x18 12. "IS,SYS_WAKEUP0 PAD Input select" "0,1" bitfld.long 0x18 8. "SR,SYS_WAKEUP0 PAD Slew rate" "0,1" bitfld.long 0x18 4.--5. "DS,SYS_WAKEUP0 PAD Driver select" "0,1,2,3" newline bitfld.long 0x18 1. "PS,SYS_WAKEUP0 PAD Pull select" "0,1" bitfld.long 0x18 0. "PE,SYS_WAKEUP0 PAD Pull enable" "0,1" line.long 0x1C "IO_PAD_CONFIG_SYS_WAKEUP1,PAD SYS_WAKEUP1 config register" bitfld.long 0x1C 16. "POE,SYS_WAKEUP1 PAD Parametric output enable" "0,1" bitfld.long 0x1C 12. "IS,SYS_WAKEUP1 PAD Input select" "0,1" bitfld.long 0x1C 8. "SR,SYS_WAKEUP1 PAD Slew rate" "0,1" bitfld.long 0x1C 4.--5. "DS,SYS_WAKEUP1 PAD Driver select" "0,1,2,3" newline bitfld.long 0x1C 1. "PS,SYS_WAKEUP1 PAD Pull select" "0,1" bitfld.long 0x1C 0. "PE,SYS_WAKEUP1 PAD Pull enable" "0,1" line.long 0x20 "IO_PAD_CONFIG_SYS_CTRL0,PAD SYS_CTRL0 config register" bitfld.long 0x20 16. "POE,SYS_CTRL0 PAD Parametric output enable" "0,1" bitfld.long 0x20 12. "IS,SYS_CTRL0 PAD Input select" "0,1" bitfld.long 0x20 8. "SR,SYS_CTRL0 PAD Slew rate" "0,1" bitfld.long 0x20 4.--5. "DS,SYS_CTRL0 PAD Driver select" "0,1,2,3" newline bitfld.long 0x20 1. "PS,SYS_CTRL0 PAD Pull select" "0,1" bitfld.long 0x20 0. "PE,SYS_CTRL0 PAD Pull enable" "0,1" line.long 0x24 "IO_PAD_CONFIG_SYS_CTRL1,PAD SYS_CTRL1 config register" bitfld.long 0x24 16. "POE,SYS_CTRL1 PAD Parametric output enable" "0,1" bitfld.long 0x24 12. "IS,SYS_CTRL1 PAD Input select" "0,1" bitfld.long 0x24 8. "SR,SYS_CTRL1 PAD Slew rate" "0,1" bitfld.long 0x24 4.--5. "DS,SYS_CTRL1 PAD Driver select" "0,1,2,3" newline bitfld.long 0x24 1. "PS,SYS_CTRL1 PAD Pull select" "0,1" bitfld.long 0x24 0. "PE,SYS_CTRL1 PAD Pull enable" "0,1" line.long 0x28 "IO_PAD_CONFIG_SYS_CTRL2,PAD SYS_CTRL2 config register" bitfld.long 0x28 16. "POE,SYS_CTRL2 PAD Parametric output enable" "0,1" bitfld.long 0x28 12. "IS,SYS_CTRL2 PAD Input select" "0,1" bitfld.long 0x28 8. "SR,SYS_CTRL2 PAD Slew rate" "0,1" bitfld.long 0x28 4.--5. "DS,SYS_CTRL2 PAD Driver select" "0,1,2,3" newline bitfld.long 0x28 1. "PS,SYS_CTRL2 PAD Pull select" "0,1" bitfld.long 0x28 0. "PE,SYS_CTRL2 PAD Pull enable" "0,1" line.long 0x2C "IO_PAD_CONFIG_SYS_CTRL3,PAD SYS_CTRL3 config register" bitfld.long 0x2C 16. "POE,SYS_CTRL3 PAD Parametric output enable" "0,1" bitfld.long 0x2C 12. "IS,SYS_CTRL3 PAD Input select" "0,1" bitfld.long 0x2C 8. "SR,SYS_CTRL3 PAD Slew rate" "0,1" bitfld.long 0x2C 4.--5. "DS,SYS_CTRL3 PAD Driver select" "0,1,2,3" newline bitfld.long 0x2C 1. "PS,SYS_CTRL3 PAD Pull select" "0,1" bitfld.long 0x2C 0. "PE,SYS_CTRL3 PAD Pull enable" "0,1" group.long 0x200++0x2B line.long 0x0 "PIN_MUX_CONFIG_SYS_MODE0,PAD SYS_MODE0 pin-mux config register" bitfld.long 0x0 12. "FV,SYS_MODE0 PAD Force Input Value when fin=0x2" "0,1" bitfld.long 0x0 8.--9. "FIN,SYS_MODE0 PAD Force Input On/Off mode" "0,1,2,3" bitfld.long 0x0 4. "ODE,SYS_MODE0 PAD Opn Drain Mode enable" "0,1" bitfld.long 0x0 0.--2. "MUX,SYS_MODE0 PAD Pin-mux func select" "0,1,2,3,4,5,6,7" line.long 0x4 "PIN_MUX_CONFIG_SYS_MODE1,PAD SYS_MODE1 pin-mux config register" bitfld.long 0x4 12. "FV,SYS_MODE1 PAD Force Input Value when fin=0x2" "0,1" bitfld.long 0x4 8.--9. "FIN,SYS_MODE1 PAD Force Input On/Off mode" "0,1,2,3" bitfld.long 0x4 4. "ODE,SYS_MODE1 PAD Opn Drain Mode enable" "0,1" bitfld.long 0x4 0.--2. "MUX,SYS_MODE1 PAD Pin-mux func select" "0,1,2,3,4,5,6,7" line.long 0x8 "PIN_MUX_CONFIG_SYS_RESET_N,PAD SYS_RESET_N pin-mux config register" bitfld.long 0x8 12. "FV,SYS_RESET_N PAD Force Input Value when fin=0x2" "0,1" bitfld.long 0x8 8.--9. "FIN,SYS_RESET_N PAD Force Input On/Off mode" "0,1,2,3" bitfld.long 0x8 4. "ODE,SYS_RESET_N PAD Opn Drain Mode enable" "0,1" bitfld.long 0x8 0.--2. "MUX,SYS_RESET_N PAD Pin-mux func select" "0,1,2,3,4,5,6,7" line.long 0xC "PIN_MUX_CONFIG_AP_RESET_N,PAD AP_RESET_N pin-mux config register" bitfld.long 0xC 12. "FV,AP_RESET_N PAD Force Input Value when fin=0x2" "0,1" bitfld.long 0xC 8.--9. "FIN,AP_RESET_N PAD Force Input On/Off mode" "0,1,2,3" bitfld.long 0xC 4. "ODE,AP_RESET_N PAD Opn Drain Mode enable" "0,1" bitfld.long 0xC 0.--2. "MUX,AP_RESET_N PAD Pin-mux func select" "0,1,2,3,4,5,6,7" line.long 0x10 "PIN_MUX_CONFIG_RTC_RESET_N,PAD RTC_RESET_N pin-mux config register" bitfld.long 0x10 12. "FV,RTC_RESET_N PAD Force Input Value when fin=0x2" "0,1" bitfld.long 0x10 8.--9. "FIN,RTC_RESET_N PAD Force Input On/Off mode" "0,1,2,3" bitfld.long 0x10 4. "ODE,RTC_RESET_N PAD Opn Drain Mode enable" "0,1" bitfld.long 0x10 0.--2. "MUX,RTC_RESET_N PAD Pin-mux func select" "0,1,2,3,4,5,6,7" line.long 0x14 "PIN_MUX_CONFIG_SYS_WAKEUP0,PAD SYS_WAKEUP0 pin-mux config register" bitfld.long 0x14 12. "FV,SYS_WAKEUP0 PAD Force Input Value when fin=0x2" "0,1" bitfld.long 0x14 8.--9. "FIN,SYS_WAKEUP0 PAD Force Input On/Off mode" "0,1,2,3" bitfld.long 0x14 4. "ODE,SYS_WAKEUP0 PAD Opn Drain Mode enable" "0,1" bitfld.long 0x14 0.--2. "MUX,SYS_WAKEUP0 PAD Pin-mux func select" "0,1,2,3,4,5,6,7" line.long 0x18 "PIN_MUX_CONFIG_SYS_WAKEUP1,PAD SYS_WAKEUP1 pin-mux config register" bitfld.long 0x18 12. "FV,SYS_WAKEUP1 PAD Force Input Value when fin=0x2" "0,1" bitfld.long 0x18 8.--9. "FIN,SYS_WAKEUP1 PAD Force Input On/Off mode" "0,1,2,3" bitfld.long 0x18 4. "ODE,SYS_WAKEUP1 PAD Opn Drain Mode enable" "0,1" bitfld.long 0x18 0.--2. "MUX,SYS_WAKEUP1 PAD Pin-mux func select" "0,1,2,3,4,5,6,7" line.long 0x1C "PIN_MUX_CONFIG_SYS_CTRL0,PAD SYS_CTRL0 pin-mux config register" bitfld.long 0x1C 12. "FV,SYS_CTRL0 PAD Force Input Value when fin=0x2" "0,1" bitfld.long 0x1C 8.--9. "FIN,SYS_CTRL0 PAD Force Input On/Off mode" "0,1,2,3" bitfld.long 0x1C 4. "ODE,SYS_CTRL0 PAD Opn Drain Mode enable" "0,1" bitfld.long 0x1C 0.--2. "MUX,SYS_CTRL0 PAD Pin-mux func select" "0,1,2,3,4,5,6,7" line.long 0x20 "PIN_MUX_CONFIG_SYS_CTRL1,PAD SYS_CTRL1 pin-mux config register" bitfld.long 0x20 12. "FV,SYS_CTRL1 PAD Force Input Value when fin=0x2" "0,1" bitfld.long 0x20 8.--9. "FIN,SYS_CTRL1 PAD Force Input On/Off mode" "0,1,2,3" bitfld.long 0x20 4. "ODE,SYS_CTRL1 PAD Opn Drain Mode enable" "0,1" bitfld.long 0x20 0.--2. "MUX,SYS_CTRL1 PAD Pin-mux func select" "0,1,2,3,4,5,6,7" line.long 0x24 "PIN_MUX_CONFIG_SYS_CTRL2,PAD SYS_CTRL2 pin-mux config register" bitfld.long 0x24 12. "FV,SYS_CTRL2 PAD Force Input Value when fin=0x2" "0,1" bitfld.long 0x24 8.--9. "FIN,SYS_CTRL2 PAD Force Input On/Off mode" "0,1,2,3" bitfld.long 0x24 4. "ODE,SYS_CTRL2 PAD Opn Drain Mode enable" "0,1" bitfld.long 0x24 0.--2. "MUX,SYS_CTRL2 PAD Pin-mux func select" "0,1,2,3,4,5,6,7" line.long 0x28 "PIN_MUX_CONFIG_SYS_CTRL3,PAD SYS_CTRL3 pin-mux config register" bitfld.long 0x28 12. "FV,SYS_CTRL3 PAD Force Input Value when fin=0x2" "0,1" bitfld.long 0x28 8.--9. "FIN,SYS_CTRL3 PAD Force Input On/Off mode" "0,1,2,3" bitfld.long 0x28 4. "ODE,SYS_CTRL3 PAD Opn Drain Mode enable" "0,1" bitfld.long 0x28 0.--2. "MUX,SYS_CTRL3 PAD Pin-mux func select" "0,1,2,3,4,5,6,7" tree.end tree "PINCTRL_SAFETY" base ad:0xFC500000 group.long 0x0++0xDB line.long 0x0 "IO_PAD_CONFIG_JTAG_TMS,PAD JTAG_TMS config register" bitfld.long 0x0 16. "POE,JTAG_TMS PAD Parametric output enable" "0,1" bitfld.long 0x0 12. "IS,JTAG_TMS PAD Input select" "0,1" bitfld.long 0x0 8. "SR,JTAG_TMS PAD Slew rate" "0,1" bitfld.long 0x0 4.--5. "DS,JTAG_TMS PAD Driver select" "0,1,2,3" newline bitfld.long 0x0 1. "PS,JTAG_TMS PAD Pull select" "0,1" bitfld.long 0x0 0. "PE,JTAG_TMS PAD Pull enable" "0,1" line.long 0x4 "IO_PAD_CONFIG_JTAG_TCK,PAD JTAG_TCK config register" bitfld.long 0x4 16. "POE,JTAG_TCK PAD Parametric output enable" "0,1" bitfld.long 0x4 12. "IS,JTAG_TCK PAD Input select" "0,1" bitfld.long 0x4 8. "SR,JTAG_TCK PAD Slew rate" "0,1" bitfld.long 0x4 4.--5. "DS,JTAG_TCK PAD Driver select" "0,1,2,3" newline bitfld.long 0x4 1. "PS,JTAG_TCK PAD Pull select" "0,1" bitfld.long 0x4 0. "PE,JTAG_TCK PAD Pull enable" "0,1" line.long 0x8 "IO_PAD_CONFIG_JTAG_TDI,PAD JTAG_TDI config register" bitfld.long 0x8 16. "POE,JTAG_TDI PAD Parametric output enable" "0,1" bitfld.long 0x8 12. "IS,JTAG_TDI PAD Input select" "0,1" bitfld.long 0x8 8. "SR,JTAG_TDI PAD Slew rate" "0,1" bitfld.long 0x8 4.--5. "DS,JTAG_TDI PAD Driver select" "0,1,2,3" newline bitfld.long 0x8 1. "PS,JTAG_TDI PAD Pull select" "0,1" bitfld.long 0x8 0. "PE,JTAG_TDI PAD Pull enable" "0,1" line.long 0xC "IO_PAD_CONFIG_JTAG_TDO,PAD JTAG_TDO config register" bitfld.long 0xC 16. "POE,JTAG_TDO PAD Parametric output enable" "0,1" bitfld.long 0xC 12. "IS,JTAG_TDO PAD Input select" "0,1" bitfld.long 0xC 8. "SR,JTAG_TDO PAD Slew rate" "0,1" bitfld.long 0xC 4.--5. "DS,JTAG_TDO PAD Driver select" "0,1,2,3" newline bitfld.long 0xC 1. "PS,JTAG_TDO PAD Pull select" "0,1" bitfld.long 0xC 0. "PE,JTAG_TDO PAD Pull enable" "0,1" line.long 0x10 "IO_PAD_CONFIG_JTAG_TRST_N,PAD JTAG_TRST_N config register" bitfld.long 0x10 16. "POE,JTAG_TRST_N PAD Parametric output enable" "0,1" bitfld.long 0x10 12. "IS,JTAG_TRST_N PAD Input select" "0,1" bitfld.long 0x10 8. "SR,JTAG_TRST_N PAD Slew rate" "0,1" bitfld.long 0x10 4.--5. "DS,JTAG_TRST_N PAD Driver select" "0,1,2,3" newline bitfld.long 0x10 1. "PS,JTAG_TRST_N PAD Pull select" "0,1" bitfld.long 0x10 0. "PE,JTAG_TRST_N PAD Pull enable" "0,1" line.long 0x14 "IO_PAD_CONFIG_OSPI1_SCLK,PAD OSPI1_SCLK config register" bitfld.long 0x14 16. "POE,OSPI1_SCLK PAD Parametric output enable" "0,1" bitfld.long 0x14 12. "IS,OSPI1_SCLK PAD Input select" "0,1" bitfld.long 0x14 8. "SR,OSPI1_SCLK PAD Slew rate" "0,1" bitfld.long 0x14 4.--5. "DS,OSPI1_SCLK PAD Driver select" "0,1,2,3" newline bitfld.long 0x14 1. "PS,OSPI1_SCLK PAD Pull select" "0,1" bitfld.long 0x14 0. "PE,OSPI1_SCLK PAD Pull enable" "0,1" line.long 0x18 "IO_PAD_CONFIG_OSPI1_SS0,PAD OSPI1_SS0 config register" bitfld.long 0x18 16. "POE,OSPI1_SS0 PAD Parametric output enable" "0,1" bitfld.long 0x18 12. "IS,OSPI1_SS0 PAD Input select" "0,1" bitfld.long 0x18 8. "SR,OSPI1_SS0 PAD Slew rate" "0,1" bitfld.long 0x18 4.--5. "DS,OSPI1_SS0 PAD Driver select" "0,1,2,3" newline bitfld.long 0x18 1. "PS,OSPI1_SS0 PAD Pull select" "0,1" bitfld.long 0x18 0. "PE,OSPI1_SS0 PAD Pull enable" "0,1" line.long 0x1C "IO_PAD_CONFIG_OSPI1_DATA0,PAD OSPI1_DATA0 config register" bitfld.long 0x1C 16. "POE,OSPI1_DATA0 PAD Parametric output enable" "0,1" bitfld.long 0x1C 12. "IS,OSPI1_DATA0 PAD Input select" "0,1" bitfld.long 0x1C 8. "SR,OSPI1_DATA0 PAD Slew rate" "0,1" bitfld.long 0x1C 4.--5. "DS,OSPI1_DATA0 PAD Driver select" "0,1,2,3" newline bitfld.long 0x1C 1. "PS,OSPI1_DATA0 PAD Pull select" "0,1" bitfld.long 0x1C 0. "PE,OSPI1_DATA0 PAD Pull enable" "0,1" line.long 0x20 "IO_PAD_CONFIG_OSPI1_DATA1,PAD OSPI1_DATA1 config register" bitfld.long 0x20 16. "POE,OSPI1_DATA1 PAD Parametric output enable" "0,1" bitfld.long 0x20 12. "IS,OSPI1_DATA1 PAD Input select" "0,1" bitfld.long 0x20 8. "SR,OSPI1_DATA1 PAD Slew rate" "0,1" bitfld.long 0x20 4.--5. "DS,OSPI1_DATA1 PAD Driver select" "0,1,2,3" newline bitfld.long 0x20 1. "PS,OSPI1_DATA1 PAD Pull select" "0,1" bitfld.long 0x20 0. "PE,OSPI1_DATA1 PAD Pull enable" "0,1" line.long 0x24 "IO_PAD_CONFIG_OSPI1_DATA2,PAD OSPI1_DATA2 config register" bitfld.long 0x24 16. "POE,OSPI1_DATA2 PAD Parametric output enable" "0,1" bitfld.long 0x24 12. "IS,OSPI1_DATA2 PAD Input select" "0,1" bitfld.long 0x24 8. "SR,OSPI1_DATA2 PAD Slew rate" "0,1" bitfld.long 0x24 4.--5. "DS,OSPI1_DATA2 PAD Driver select" "0,1,2,3" newline bitfld.long 0x24 1. "PS,OSPI1_DATA2 PAD Pull select" "0,1" bitfld.long 0x24 0. "PE,OSPI1_DATA2 PAD Pull enable" "0,1" line.long 0x28 "IO_PAD_CONFIG_OSPI1_DATA3,PAD OSPI1_DATA3 config register" bitfld.long 0x28 16. "POE,OSPI1_DATA3 PAD Parametric output enable" "0,1" bitfld.long 0x28 12. "IS,OSPI1_DATA3 PAD Input select" "0,1" bitfld.long 0x28 8. "SR,OSPI1_DATA3 PAD Slew rate" "0,1" bitfld.long 0x28 4.--5. "DS,OSPI1_DATA3 PAD Driver select" "0,1,2,3" newline bitfld.long 0x28 1. "PS,OSPI1_DATA3 PAD Pull select" "0,1" bitfld.long 0x28 0. "PE,OSPI1_DATA3 PAD Pull enable" "0,1" line.long 0x2C "IO_PAD_CONFIG_OSPI1_DATA4,PAD OSPI1_DATA4 config register" bitfld.long 0x2C 16. "POE,OSPI1_DATA4 PAD Parametric output enable" "0,1" bitfld.long 0x2C 12. "IS,OSPI1_DATA4 PAD Input select" "0,1" bitfld.long 0x2C 8. "SR,OSPI1_DATA4 PAD Slew rate" "0,1" bitfld.long 0x2C 4.--5. "DS,OSPI1_DATA4 PAD Driver select" "0,1,2,3" newline bitfld.long 0x2C 1. "PS,OSPI1_DATA4 PAD Pull select" "0,1" bitfld.long 0x2C 0. "PE,OSPI1_DATA4 PAD Pull enable" "0,1" line.long 0x30 "IO_PAD_CONFIG_OSPI1_DATA5,PAD OSPI1_DATA5 config register" bitfld.long 0x30 16. "POE,OSPI1_DATA5 PAD Parametric output enable" "0,1" bitfld.long 0x30 12. "IS,OSPI1_DATA5 PAD Input select" "0,1" bitfld.long 0x30 8. "SR,OSPI1_DATA5 PAD Slew rate" "0,1" bitfld.long 0x30 4.--5. "DS,OSPI1_DATA5 PAD Driver select" "0,1,2,3" newline bitfld.long 0x30 1. "PS,OSPI1_DATA5 PAD Pull select" "0,1" bitfld.long 0x30 0. "PE,OSPI1_DATA5 PAD Pull enable" "0,1" line.long 0x34 "IO_PAD_CONFIG_OSPI1_DATA6,PAD OSPI1_DATA6 config register" bitfld.long 0x34 16. "POE,OSPI1_DATA6 PAD Parametric output enable" "0,1" bitfld.long 0x34 12. "IS,OSPI1_DATA6 PAD Input select" "0,1" bitfld.long 0x34 8. "SR,OSPI1_DATA6 PAD Slew rate" "0,1" bitfld.long 0x34 4.--5. "DS,OSPI1_DATA6 PAD Driver select" "0,1,2,3" newline bitfld.long 0x34 1. "PS,OSPI1_DATA6 PAD Pull select" "0,1" bitfld.long 0x34 0. "PE,OSPI1_DATA6 PAD Pull enable" "0,1" line.long 0x38 "IO_PAD_CONFIG_OSPI1_DATA7,PAD OSPI1_DATA7 config register" bitfld.long 0x38 16. "POE,OSPI1_DATA7 PAD Parametric output enable" "0,1" bitfld.long 0x38 12. "IS,OSPI1_DATA7 PAD Input select" "0,1" bitfld.long 0x38 8. "SR,OSPI1_DATA7 PAD Slew rate" "0,1" bitfld.long 0x38 4.--5. "DS,OSPI1_DATA7 PAD Driver select" "0,1,2,3" newline bitfld.long 0x38 1. "PS,OSPI1_DATA7 PAD Pull select" "0,1" bitfld.long 0x38 0. "PE,OSPI1_DATA7 PAD Pull enable" "0,1" line.long 0x3C "IO_PAD_CONFIG_OSPI1_DQS,PAD OSPI1_DQS config register" bitfld.long 0x3C 16. "POE,OSPI1_DQS PAD Parametric output enable" "0,1" bitfld.long 0x3C 12. "IS,OSPI1_DQS PAD Input select" "0,1" bitfld.long 0x3C 8. "SR,OSPI1_DQS PAD Slew rate" "0,1" bitfld.long 0x3C 4.--5. "DS,OSPI1_DQS PAD Driver select" "0,1,2,3" newline bitfld.long 0x3C 1. "PS,OSPI1_DQS PAD Pull select" "0,1" bitfld.long 0x3C 0. "PE,OSPI1_DQS PAD Pull enable" "0,1" line.long 0x40 "IO_PAD_CONFIG_OSPI1_SS1,PAD OSPI1_SS1 config register" bitfld.long 0x40 16. "POE,OSPI1_SS1 PAD Parametric output enable" "0,1" bitfld.long 0x40 12. "IS,OSPI1_SS1 PAD Input select" "0,1" bitfld.long 0x40 8. "SR,OSPI1_SS1 PAD Slew rate" "0,1" bitfld.long 0x40 4.--5. "DS,OSPI1_SS1 PAD Driver select" "0,1,2,3" newline bitfld.long 0x40 1. "PS,OSPI1_SS1 PAD Pull select" "0,1" bitfld.long 0x40 0. "PE,OSPI1_SS1 PAD Pull enable" "0,1" line.long 0x44 "IO_PAD_CONFIG_RGMII1_TXC,PAD RGMII1_TXC config register" bitfld.long 0x44 16. "POE,RGMII1_TXC PAD Parametric output enable" "0,1" bitfld.long 0x44 12. "IS,RGMII1_TXC PAD Input select" "0,1" bitfld.long 0x44 8. "SR,RGMII1_TXC PAD Slew rate" "0,1" bitfld.long 0x44 4.--5. "DS,RGMII1_TXC PAD Driver select" "0,1,2,3" newline bitfld.long 0x44 1. "PS,RGMII1_TXC PAD Pull select" "0,1" bitfld.long 0x44 0. "PE,RGMII1_TXC PAD Pull enable" "0,1" line.long 0x48 "IO_PAD_CONFIG_RGMII1_TXD0,PAD RGMII1_TXD0 config register" bitfld.long 0x48 16. "POE,RGMII1_TXD0 PAD Parametric output enable" "0,1" bitfld.long 0x48 12. "IS,RGMII1_TXD0 PAD Input select" "0,1" bitfld.long 0x48 8. "SR,RGMII1_TXD0 PAD Slew rate" "0,1" bitfld.long 0x48 4.--5. "DS,RGMII1_TXD0 PAD Driver select" "0,1,2,3" newline bitfld.long 0x48 1. "PS,RGMII1_TXD0 PAD Pull select" "0,1" bitfld.long 0x48 0. "PE,RGMII1_TXD0 PAD Pull enable" "0,1" line.long 0x4C "IO_PAD_CONFIG_RGMII1_TXD1,PAD RGMII1_TXD1 config register" bitfld.long 0x4C 16. "POE,RGMII1_TXD1 PAD Parametric output enable" "0,1" bitfld.long 0x4C 12. "IS,RGMII1_TXD1 PAD Input select" "0,1" bitfld.long 0x4C 8. "SR,RGMII1_TXD1 PAD Slew rate" "0,1" bitfld.long 0x4C 4.--5. "DS,RGMII1_TXD1 PAD Driver select" "0,1,2,3" newline bitfld.long 0x4C 1. "PS,RGMII1_TXD1 PAD Pull select" "0,1" bitfld.long 0x4C 0. "PE,RGMII1_TXD1 PAD Pull enable" "0,1" line.long 0x50 "IO_PAD_CONFIG_RGMII1_TXD2,PAD RGMII1_TXD2 config register" bitfld.long 0x50 16. "POE,RGMII1_TXD2 PAD Parametric output enable" "0,1" bitfld.long 0x50 12. "IS,RGMII1_TXD2 PAD Input select" "0,1" bitfld.long 0x50 8. "SR,RGMII1_TXD2 PAD Slew rate" "0,1" bitfld.long 0x50 4.--5. "DS,RGMII1_TXD2 PAD Driver select" "0,1,2,3" newline bitfld.long 0x50 1. "PS,RGMII1_TXD2 PAD Pull select" "0,1" bitfld.long 0x50 0. "PE,RGMII1_TXD2 PAD Pull enable" "0,1" line.long 0x54 "IO_PAD_CONFIG_RGMII1_TXD3,PAD RGMII1_TXD3 config register" bitfld.long 0x54 16. "POE,RGMII1_TXD3 PAD Parametric output enable" "0,1" bitfld.long 0x54 12. "IS,RGMII1_TXD3 PAD Input select" "0,1" bitfld.long 0x54 8. "SR,RGMII1_TXD3 PAD Slew rate" "0,1" bitfld.long 0x54 4.--5. "DS,RGMII1_TXD3 PAD Driver select" "0,1,2,3" newline bitfld.long 0x54 1. "PS,RGMII1_TXD3 PAD Pull select" "0,1" bitfld.long 0x54 0. "PE,RGMII1_TXD3 PAD Pull enable" "0,1" line.long 0x58 "IO_PAD_CONFIG_RGMII1_TX_CTL,PAD RGMII1_TX_CTL config register" bitfld.long 0x58 16. "POE,RGMII1_TX_CTL PAD Parametric output enable" "0,1" bitfld.long 0x58 12. "IS,RGMII1_TX_CTL PAD Input select" "0,1" bitfld.long 0x58 8. "SR,RGMII1_TX_CTL PAD Slew rate" "0,1" bitfld.long 0x58 4.--5. "DS,RGMII1_TX_CTL PAD Driver select" "0,1,2,3" newline bitfld.long 0x58 1. "PS,RGMII1_TX_CTL PAD Pull select" "0,1" bitfld.long 0x58 0. "PE,RGMII1_TX_CTL PAD Pull enable" "0,1" line.long 0x5C "IO_PAD_CONFIG_RGMII1_RXC,PAD RGMII1_RXC config register" bitfld.long 0x5C 16. "POE,RGMII1_RXC PAD Parametric output enable" "0,1" bitfld.long 0x5C 12. "IS,RGMII1_RXC PAD Input select" "0,1" bitfld.long 0x5C 8. "SR,RGMII1_RXC PAD Slew rate" "0,1" bitfld.long 0x5C 4.--5. "DS,RGMII1_RXC PAD Driver select" "0,1,2,3" newline bitfld.long 0x5C 1. "PS,RGMII1_RXC PAD Pull select" "0,1" bitfld.long 0x5C 0. "PE,RGMII1_RXC PAD Pull enable" "0,1" line.long 0x60 "IO_PAD_CONFIG_RGMII1_RXD0,PAD RGMII1_RXD0 config register" bitfld.long 0x60 16. "POE,RGMII1_RXD0 PAD Parametric output enable" "0,1" bitfld.long 0x60 12. "IS,RGMII1_RXD0 PAD Input select" "0,1" bitfld.long 0x60 8. "SR,RGMII1_RXD0 PAD Slew rate" "0,1" bitfld.long 0x60 4.--5. "DS,RGMII1_RXD0 PAD Driver select" "0,1,2,3" newline bitfld.long 0x60 1. "PS,RGMII1_RXD0 PAD Pull select" "0,1" bitfld.long 0x60 0. "PE,RGMII1_RXD0 PAD Pull enable" "0,1" line.long 0x64 "IO_PAD_CONFIG_RGMII1_RXD1,PAD RGMII1_RXD1 config register" bitfld.long 0x64 16. "POE,RGMII1_RXD1 PAD Parametric output enable" "0,1" bitfld.long 0x64 12. "IS,RGMII1_RXD1 PAD Input select" "0,1" bitfld.long 0x64 8. "SR,RGMII1_RXD1 PAD Slew rate" "0,1" bitfld.long 0x64 4.--5. "DS,RGMII1_RXD1 PAD Driver select" "0,1,2,3" newline bitfld.long 0x64 1. "PS,RGMII1_RXD1 PAD Pull select" "0,1" bitfld.long 0x64 0. "PE,RGMII1_RXD1 PAD Pull enable" "0,1" line.long 0x68 "IO_PAD_CONFIG_RGMII1_RXD2,PAD RGMII1_RXD2 config register" bitfld.long 0x68 16. "POE,RGMII1_RXD2 PAD Parametric output enable" "0,1" bitfld.long 0x68 12. "IS,RGMII1_RXD2 PAD Input select" "0,1" bitfld.long 0x68 8. "SR,RGMII1_RXD2 PAD Slew rate" "0,1" bitfld.long 0x68 4.--5. "DS,RGMII1_RXD2 PAD Driver select" "0,1,2,3" newline bitfld.long 0x68 1. "PS,RGMII1_RXD2 PAD Pull select" "0,1" bitfld.long 0x68 0. "PE,RGMII1_RXD2 PAD Pull enable" "0,1" line.long 0x6C "IO_PAD_CONFIG_RGMII1_RXD3,PAD RGMII1_RXD3 config register" bitfld.long 0x6C 16. "POE,RGMII1_RXD3 PAD Parametric output enable" "0,1" bitfld.long 0x6C 12. "IS,RGMII1_RXD3 PAD Input select" "0,1" bitfld.long 0x6C 8. "SR,RGMII1_RXD3 PAD Slew rate" "0,1" bitfld.long 0x6C 4.--5. "DS,RGMII1_RXD3 PAD Driver select" "0,1,2,3" newline bitfld.long 0x6C 1. "PS,RGMII1_RXD3 PAD Pull select" "0,1" bitfld.long 0x6C 0. "PE,RGMII1_RXD3 PAD Pull enable" "0,1" line.long 0x70 "IO_PAD_CONFIG_RGMII1_RX_CTL,PAD RGMII1_RX_CTL config register" bitfld.long 0x70 16. "POE,RGMII1_RX_CTL PAD Parametric output enable" "0,1" bitfld.long 0x70 12. "IS,RGMII1_RX_CTL PAD Input select" "0,1" bitfld.long 0x70 8. "SR,RGMII1_RX_CTL PAD Slew rate" "0,1" bitfld.long 0x70 4.--5. "DS,RGMII1_RX_CTL PAD Driver select" "0,1,2,3" newline bitfld.long 0x70 1. "PS,RGMII1_RX_CTL PAD Pull select" "0,1" bitfld.long 0x70 0. "PE,RGMII1_RX_CTL PAD Pull enable" "0,1" line.long 0x74 "IO_PAD_CONFIG_GPIO_A0,PAD GPIO_A0 config register" bitfld.long 0x74 16. "POE,GPIO_A0 PAD Parametric output enable" "0,1" bitfld.long 0x74 12. "IS,GPIO_A0 PAD Input select" "0,1" bitfld.long 0x74 8. "SR,GPIO_A0 PAD Slew rate" "0,1" bitfld.long 0x74 4.--5. "DS,GPIO_A0 PAD Driver select" "0,1,2,3" newline bitfld.long 0x74 1. "PS,GPIO_A0 PAD Pull select" "0,1" bitfld.long 0x74 0. "PE,GPIO_A0 PAD Pull enable" "0,1" line.long 0x78 "IO_PAD_CONFIG_GPIO_A1,PAD GPIO_A1 config register" bitfld.long 0x78 16. "POE,GPIO_A1 PAD Parametric output enable" "0,1" bitfld.long 0x78 12. "IS,GPIO_A1 PAD Input select" "0,1" bitfld.long 0x78 8. "SR,GPIO_A1 PAD Slew rate" "0,1" bitfld.long 0x78 4.--5. "DS,GPIO_A1 PAD Driver select" "0,1,2,3" newline bitfld.long 0x78 1. "PS,GPIO_A1 PAD Pull select" "0,1" bitfld.long 0x78 0. "PE,GPIO_A1 PAD Pull enable" "0,1" line.long 0x7C "IO_PAD_CONFIG_GPIO_A2,PAD GPIO_A2 config register" bitfld.long 0x7C 16. "POE,GPIO_A2 PAD Parametric output enable" "0,1" bitfld.long 0x7C 12. "IS,GPIO_A2 PAD Input select" "0,1" bitfld.long 0x7C 8. "SR,GPIO_A2 PAD Slew rate" "0,1" bitfld.long 0x7C 4.--5. "DS,GPIO_A2 PAD Driver select" "0,1,2,3" newline bitfld.long 0x7C 1. "PS,GPIO_A2 PAD Pull select" "0,1" bitfld.long 0x7C 0. "PE,GPIO_A2 PAD Pull enable" "0,1" line.long 0x80 "IO_PAD_CONFIG_GPIO_A3,PAD GPIO_A3 config register" bitfld.long 0x80 16. "POE,GPIO_A3 PAD Parametric output enable" "0,1" bitfld.long 0x80 12. "IS,GPIO_A3 PAD Input select" "0,1" bitfld.long 0x80 8. "SR,GPIO_A3 PAD Slew rate" "0,1" bitfld.long 0x80 4.--5. "DS,GPIO_A3 PAD Driver select" "0,1,2,3" newline bitfld.long 0x80 1. "PS,GPIO_A3 PAD Pull select" "0,1" bitfld.long 0x80 0. "PE,GPIO_A3 PAD Pull enable" "0,1" line.long 0x84 "IO_PAD_CONFIG_GPIO_A4,PAD GPIO_A4 config register" bitfld.long 0x84 16. "POE,GPIO_A4 PAD Parametric output enable" "0,1" bitfld.long 0x84 12. "IS,GPIO_A4 PAD Input select" "0,1" bitfld.long 0x84 8. "SR,GPIO_A4 PAD Slew rate" "0,1" bitfld.long 0x84 4.--5. "DS,GPIO_A4 PAD Driver select" "0,1,2,3" newline bitfld.long 0x84 1. "PS,GPIO_A4 PAD Pull select" "0,1" bitfld.long 0x84 0. "PE,GPIO_A4 PAD Pull enable" "0,1" line.long 0x88 "IO_PAD_CONFIG_GPIO_A5,PAD GPIO_A5 config register" bitfld.long 0x88 16. "POE,GPIO_A5 PAD Parametric output enable" "0,1" bitfld.long 0x88 12. "IS,GPIO_A5 PAD Input select" "0,1" bitfld.long 0x88 8. "SR,GPIO_A5 PAD Slew rate" "0,1" bitfld.long 0x88 4.--5. "DS,GPIO_A5 PAD Driver select" "0,1,2,3" newline bitfld.long 0x88 1. "PS,GPIO_A5 PAD Pull select" "0,1" bitfld.long 0x88 0. "PE,GPIO_A5 PAD Pull enable" "0,1" line.long 0x8C "IO_PAD_CONFIG_GPIO_A6,PAD GPIO_A6 config register" bitfld.long 0x8C 16. "POE,GPIO_A6 PAD Parametric output enable" "0,1" bitfld.long 0x8C 12. "IS,GPIO_A6 PAD Input select" "0,1" bitfld.long 0x8C 8. "SR,GPIO_A6 PAD Slew rate" "0,1" bitfld.long 0x8C 4.--5. "DS,GPIO_A6 PAD Driver select" "0,1,2,3" newline bitfld.long 0x8C 1. "PS,GPIO_A6 PAD Pull select" "0,1" bitfld.long 0x8C 0. "PE,GPIO_A6 PAD Pull enable" "0,1" line.long 0x90 "IO_PAD_CONFIG_GPIO_A7,PAD GPIO_A7 config register" bitfld.long 0x90 16. "POE,GPIO_A7 PAD Parametric output enable" "0,1" bitfld.long 0x90 12. "IS,GPIO_A7 PAD Input select" "0,1" bitfld.long 0x90 8. "SR,GPIO_A7 PAD Slew rate" "0,1" bitfld.long 0x90 4.--5. "DS,GPIO_A7 PAD Driver select" "0,1,2,3" newline bitfld.long 0x90 1. "PS,GPIO_A7 PAD Pull select" "0,1" bitfld.long 0x90 0. "PE,GPIO_A7 PAD Pull enable" "0,1" line.long 0x94 "IO_PAD_CONFIG_GPIO_A8,PAD GPIO_A8 config register" bitfld.long 0x94 16. "POE,GPIO_A8 PAD Parametric output enable" "0,1" bitfld.long 0x94 12. "IS,GPIO_A8 PAD Input select" "0,1" bitfld.long 0x94 8. "SR,GPIO_A8 PAD Slew rate" "0,1" bitfld.long 0x94 4.--5. "DS,GPIO_A8 PAD Driver select" "0,1,2,3" newline bitfld.long 0x94 1. "PS,GPIO_A8 PAD Pull select" "0,1" bitfld.long 0x94 0. "PE,GPIO_A8 PAD Pull enable" "0,1" line.long 0x98 "IO_PAD_CONFIG_GPIO_A9,PAD GPIO_A9 config register" bitfld.long 0x98 16. "POE,GPIO_A9 PAD Parametric output enable" "0,1" bitfld.long 0x98 12. "IS,GPIO_A9 PAD Input select" "0,1" bitfld.long 0x98 8. "SR,GPIO_A9 PAD Slew rate" "0,1" bitfld.long 0x98 4.--5. "DS,GPIO_A9 PAD Driver select" "0,1,2,3" newline bitfld.long 0x98 1. "PS,GPIO_A9 PAD Pull select" "0,1" bitfld.long 0x98 0. "PE,GPIO_A9 PAD Pull enable" "0,1" line.long 0x9C "IO_PAD_CONFIG_GPIO_A10,PAD GPIO_A10 config register" bitfld.long 0x9C 16. "POE,GPIO_A10 PAD Parametric output enable" "0,1" bitfld.long 0x9C 12. "IS,GPIO_A10 PAD Input select" "0,1" bitfld.long 0x9C 8. "SR,GPIO_A10 PAD Slew rate" "0,1" bitfld.long 0x9C 4.--5. "DS,GPIO_A10 PAD Driver select" "0,1,2,3" newline bitfld.long 0x9C 1. "PS,GPIO_A10 PAD Pull select" "0,1" bitfld.long 0x9C 0. "PE,GPIO_A10 PAD Pull enable" "0,1" line.long 0xA0 "IO_PAD_CONFIG_GPIO_A11,PAD GPIO_A11 config register" bitfld.long 0xA0 16. "POE,GPIO_A11 PAD Parametric output enable" "0,1" bitfld.long 0xA0 12. "IS,GPIO_A11 PAD Input select" "0,1" bitfld.long 0xA0 8. "SR,GPIO_A11 PAD Slew rate" "0,1" bitfld.long 0xA0 4.--5. "DS,GPIO_A11 PAD Driver select" "0,1,2,3" newline bitfld.long 0xA0 1. "PS,GPIO_A11 PAD Pull select" "0,1" bitfld.long 0xA0 0. "PE,GPIO_A11 PAD Pull enable" "0,1" line.long 0xA4 "IO_PAD_CONFIG_GPIO_B0,PAD GPIO_B0 config register" bitfld.long 0xA4 16. "POE,GPIO_B0 PAD Parametric output enable" "0,1" bitfld.long 0xA4 12. "IS,GPIO_B0 PAD Input select" "0,1" bitfld.long 0xA4 8. "SR,GPIO_B0 PAD Slew rate" "0,1" bitfld.long 0xA4 4.--5. "DS,GPIO_B0 PAD Driver select" "0,1,2,3" newline bitfld.long 0xA4 1. "PS,GPIO_B0 PAD Pull select" "0,1" bitfld.long 0xA4 0. "PE,GPIO_B0 PAD Pull enable" "0,1" line.long 0xA8 "IO_PAD_CONFIG_GPIO_B1,PAD GPIO_B1 config register" bitfld.long 0xA8 16. "POE,GPIO_B1 PAD Parametric output enable" "0,1" bitfld.long 0xA8 12. "IS,GPIO_B1 PAD Input select" "0,1" bitfld.long 0xA8 8. "SR,GPIO_B1 PAD Slew rate" "0,1" bitfld.long 0xA8 4.--5. "DS,GPIO_B1 PAD Driver select" "0,1,2,3" newline bitfld.long 0xA8 1. "PS,GPIO_B1 PAD Pull select" "0,1" bitfld.long 0xA8 0. "PE,GPIO_B1 PAD Pull enable" "0,1" line.long 0xAC "IO_PAD_CONFIG_GPIO_B2,PAD GPIO_B2 config register" bitfld.long 0xAC 16. "POE,GPIO_B2 PAD Parametric output enable" "0,1" bitfld.long 0xAC 12. "IS,GPIO_B2 PAD Input select" "0,1" bitfld.long 0xAC 8. "SR,GPIO_B2 PAD Slew rate" "0,1" bitfld.long 0xAC 4.--5. "DS,GPIO_B2 PAD Driver select" "0,1,2,3" newline bitfld.long 0xAC 1. "PS,GPIO_B2 PAD Pull select" "0,1" bitfld.long 0xAC 0. "PE,GPIO_B2 PAD Pull enable" "0,1" line.long 0xB0 "IO_PAD_CONFIG_GPIO_B3,PAD GPIO_B3 config register" bitfld.long 0xB0 16. "POE,GPIO_B3 PAD Parametric output enable" "0,1" bitfld.long 0xB0 12. "IS,GPIO_B3 PAD Input select" "0,1" bitfld.long 0xB0 8. "SR,GPIO_B3 PAD Slew rate" "0,1" bitfld.long 0xB0 4.--5. "DS,GPIO_B3 PAD Driver select" "0,1,2,3" newline bitfld.long 0xB0 1. "PS,GPIO_B3 PAD Pull select" "0,1" bitfld.long 0xB0 0. "PE,GPIO_B3 PAD Pull enable" "0,1" line.long 0xB4 "IO_PAD_CONFIG_GPIO_B4,PAD GPIO_B4 config register" bitfld.long 0xB4 16. "POE,GPIO_B4 PAD Parametric output enable" "0,1" bitfld.long 0xB4 12. "IS,GPIO_B4 PAD Input select" "0,1" bitfld.long 0xB4 8. "SR,GPIO_B4 PAD Slew rate" "0,1" bitfld.long 0xB4 4.--5. "DS,GPIO_B4 PAD Driver select" "0,1,2,3" newline bitfld.long 0xB4 1. "PS,GPIO_B4 PAD Pull select" "0,1" bitfld.long 0xB4 0. "PE,GPIO_B4 PAD Pull enable" "0,1" line.long 0xB8 "IO_PAD_CONFIG_GPIO_B5,PAD GPIO_B5 config register" bitfld.long 0xB8 16. "POE,GPIO_B5 PAD Parametric output enable" "0,1" bitfld.long 0xB8 12. "IS,GPIO_B5 PAD Input select" "0,1" bitfld.long 0xB8 8. "SR,GPIO_B5 PAD Slew rate" "0,1" bitfld.long 0xB8 4.--5. "DS,GPIO_B5 PAD Driver select" "0,1,2,3" newline bitfld.long 0xB8 1. "PS,GPIO_B5 PAD Pull select" "0,1" bitfld.long 0xB8 0. "PE,GPIO_B5 PAD Pull enable" "0,1" line.long 0xBC "IO_PAD_CONFIG_GPIO_B6,PAD GPIO_B6 config register" bitfld.long 0xBC 16. "POE,GPIO_B6 PAD Parametric output enable" "0,1" bitfld.long 0xBC 12. "IS,GPIO_B6 PAD Input select" "0,1" bitfld.long 0xBC 8. "SR,GPIO_B6 PAD Slew rate" "0,1" bitfld.long 0xBC 4.--5. "DS,GPIO_B6 PAD Driver select" "0,1,2,3" newline bitfld.long 0xBC 1. "PS,GPIO_B6 PAD Pull select" "0,1" bitfld.long 0xBC 0. "PE,GPIO_B6 PAD Pull enable" "0,1" line.long 0xC0 "IO_PAD_CONFIG_GPIO_B7,PAD GPIO_B7 config register" bitfld.long 0xC0 16. "POE,GPIO_B7 PAD Parametric output enable" "0,1" bitfld.long 0xC0 12. "IS,GPIO_B7 PAD Input select" "0,1" bitfld.long 0xC0 8. "SR,GPIO_B7 PAD Slew rate" "0,1" bitfld.long 0xC0 4.--5. "DS,GPIO_B7 PAD Driver select" "0,1,2,3" newline bitfld.long 0xC0 1. "PS,GPIO_B7 PAD Pull select" "0,1" bitfld.long 0xC0 0. "PE,GPIO_B7 PAD Pull enable" "0,1" line.long 0xC4 "IO_PAD_CONFIG_GPIO_B8,PAD GPIO_B8 config register" bitfld.long 0xC4 16. "POE,GPIO_B8 PAD Parametric output enable" "0,1" bitfld.long 0xC4 12. "IS,GPIO_B8 PAD Input select" "0,1" bitfld.long 0xC4 8. "SR,GPIO_B8 PAD Slew rate" "0,1" bitfld.long 0xC4 4.--5. "DS,GPIO_B8 PAD Driver select" "0,1,2,3" newline bitfld.long 0xC4 1. "PS,GPIO_B8 PAD Pull select" "0,1" bitfld.long 0xC4 0. "PE,GPIO_B8 PAD Pull enable" "0,1" line.long 0xC8 "IO_PAD_CONFIG_GPIO_B9,PAD GPIO_B9 config register" bitfld.long 0xC8 16. "POE,GPIO_B9 PAD Parametric output enable" "0,1" bitfld.long 0xC8 12. "IS,GPIO_B9 PAD Input select" "0,1" bitfld.long 0xC8 8. "SR,GPIO_B9 PAD Slew rate" "0,1" bitfld.long 0xC8 4.--5. "DS,GPIO_B9 PAD Driver select" "0,1,2,3" newline bitfld.long 0xC8 1. "PS,GPIO_B9 PAD Pull select" "0,1" bitfld.long 0xC8 0. "PE,GPIO_B9 PAD Pull enable" "0,1" line.long 0xCC "IO_PAD_CONFIG_GPIO_B10,PAD GPIO_B10 config register" bitfld.long 0xCC 16. "POE,GPIO_B10 PAD Parametric output enable" "0,1" bitfld.long 0xCC 12. "IS,GPIO_B10 PAD Input select" "0,1" bitfld.long 0xCC 8. "SR,GPIO_B10 PAD Slew rate" "0,1" bitfld.long 0xCC 4.--5. "DS,GPIO_B10 PAD Driver select" "0,1,2,3" newline bitfld.long 0xCC 1. "PS,GPIO_B10 PAD Pull select" "0,1" bitfld.long 0xCC 0. "PE,GPIO_B10 PAD Pull enable" "0,1" line.long 0xD0 "IO_PAD_CONFIG_GPIO_B11,PAD GPIO_B11 config register" bitfld.long 0xD0 16. "POE,GPIO_B11 PAD Parametric output enable" "0,1" bitfld.long 0xD0 12. "IS,GPIO_B11 PAD Input select" "0,1" bitfld.long 0xD0 8. "SR,GPIO_B11 PAD Slew rate" "0,1" bitfld.long 0xD0 4.--5. "DS,GPIO_B11 PAD Driver select" "0,1,2,3" newline bitfld.long 0xD0 1. "PS,GPIO_B11 PAD Pull select" "0,1" bitfld.long 0xD0 0. "PE,GPIO_B11 PAD Pull enable" "0,1" line.long 0xD4 "IO_PAD_CONFIG_SEM_FAULT,PAD SEM_FAULT config register" bitfld.long 0xD4 16. "POE,SEM_FAULT PAD Parametric output enable" "0,1" bitfld.long 0xD4 12. "IS,SEM_FAULT PAD Input select" "0,1" bitfld.long 0xD4 8. "SR,SEM_FAULT PAD Slew rate" "0,1" bitfld.long 0xD4 4.--5. "DS,SEM_FAULT PAD Driver select" "0,1,2,3" newline bitfld.long 0xD4 1. "PS,SEM_FAULT PAD Pull select" "0,1" bitfld.long 0xD4 0. "PE,SEM_FAULT PAD Pull enable" "0,1" line.long 0xD8 "IO_PAD_CONFIG_GPIO_SAF,PAD GPIO_SAF config register" bitfld.long 0xD8 16. "POE,GPIO_SAF PAD Parametric output enable" "0,1" bitfld.long 0xD8 12. "IS,GPIO_SAF PAD Input select" "0,1" bitfld.long 0xD8 8. "SR,GPIO_SAF PAD Slew rate" "0,1" bitfld.long 0xD8 4.--5. "DS,GPIO_SAF PAD Driver select" "0,1,2,3" newline bitfld.long 0xD8 1. "PS,GPIO_SAF PAD Pull select" "0,1" bitfld.long 0xD8 0. "PE,GPIO_SAF PAD Pull enable" "0,1" group.long 0x200++0xBF line.long 0x0 "PIN_MUX_CONFIG_OSPI1_SCLK,PAD OSPI1_SCLK pin-mux config register" bitfld.long 0x0 12. "FV,OSPI1_SCLK PAD Force Input Value when fin=0x2" "0,1" bitfld.long 0x0 8.--9. "FIN,OSPI1_SCLK PAD Force Input On/Off mode" "0,1,2,3" bitfld.long 0x0 4. "ODE,OSPI1_SCLK PAD Opn Drain Mode enable" "0,1" bitfld.long 0x0 0.--2. "MUX,OSPI1_SCLK PAD Pin-mux func select" "0,1,2,3,4,5,6,7" line.long 0x4 "PIN_MUX_CONFIG_OSPI1_SS0,PAD OSPI1_SS0 pin-mux config register" bitfld.long 0x4 12. "FV,OSPI1_SS0 PAD Force Input Value when fin=0x2" "0,1" bitfld.long 0x4 8.--9. "FIN,OSPI1_SS0 PAD Force Input On/Off mode" "0,1,2,3" bitfld.long 0x4 4. "ODE,OSPI1_SS0 PAD Opn Drain Mode enable" "0,1" bitfld.long 0x4 0.--2. "MUX,OSPI1_SS0 PAD Pin-mux func select" "0,1,2,3,4,5,6,7" line.long 0x8 "PIN_MUX_CONFIG_OSPI1_DATA0,PAD OSPI1_DATA0 pin-mux config register" bitfld.long 0x8 12. "FV,OSPI1_DATA0 PAD Force Input Value when fin=0x2" "0,1" bitfld.long 0x8 8.--9. "FIN,OSPI1_DATA0 PAD Force Input On/Off mode" "0,1,2,3" bitfld.long 0x8 4. "ODE,OSPI1_DATA0 PAD Opn Drain Mode enable" "0,1" bitfld.long 0x8 0.--2. "MUX,OSPI1_DATA0 PAD Pin-mux func select" "0,1,2,3,4,5,6,7" line.long 0xC "PIN_MUX_CONFIG_OSPI1_DATA1,PAD OSPI1_DATA1 pin-mux config register" bitfld.long 0xC 12. "FV,OSPI1_DATA1 PAD Force Input Value when fin=0x2" "0,1" bitfld.long 0xC 8.--9. "FIN,OSPI1_DATA1 PAD Force Input On/Off mode" "0,1,2,3" bitfld.long 0xC 4. "ODE,OSPI1_DATA1 PAD Opn Drain Mode enable" "0,1" bitfld.long 0xC 0.--2. "MUX,OSPI1_DATA1 PAD Pin-mux func select" "0,1,2,3,4,5,6,7" line.long 0x10 "PIN_MUX_CONFIG_OSPI1_DATA2,PAD OSPI1_DATA2 pin-mux config register" bitfld.long 0x10 12. "FV,OSPI1_DATA2 PAD Force Input Value when fin=0x2" "0,1" bitfld.long 0x10 8.--9. "FIN,OSPI1_DATA2 PAD Force Input On/Off mode" "0,1,2,3" bitfld.long 0x10 4. "ODE,OSPI1_DATA2 PAD Opn Drain Mode enable" "0,1" bitfld.long 0x10 0.--2. "MUX,OSPI1_DATA2 PAD Pin-mux func select" "0,1,2,3,4,5,6,7" line.long 0x14 "PIN_MUX_CONFIG_OSPI1_DATA3,PAD OSPI1_DATA3 pin-mux config register" bitfld.long 0x14 12. "FV,OSPI1_DATA3 PAD Force Input Value when fin=0x2" "0,1" bitfld.long 0x14 8.--9. "FIN,OSPI1_DATA3 PAD Force Input On/Off mode" "0,1,2,3" bitfld.long 0x14 4. "ODE,OSPI1_DATA3 PAD Opn Drain Mode enable" "0,1" bitfld.long 0x14 0.--2. "MUX,OSPI1_DATA3 PAD Pin-mux func select" "0,1,2,3,4,5,6,7" line.long 0x18 "PIN_MUX_CONFIG_OSPI1_DATA4,PAD OSPI1_DATA4 pin-mux config register" bitfld.long 0x18 12. "FV,OSPI1_DATA4 PAD Force Input Value when fin=0x2" "0,1" bitfld.long 0x18 8.--9. "FIN,OSPI1_DATA4 PAD Force Input On/Off mode" "0,1,2,3" bitfld.long 0x18 4. "ODE,OSPI1_DATA4 PAD Opn Drain Mode enable" "0,1" bitfld.long 0x18 0.--2. "MUX,OSPI1_DATA4 PAD Pin-mux func select" "0,1,2,3,4,5,6,7" line.long 0x1C "PIN_MUX_CONFIG_OSPI1_DATA5,PAD OSPI1_DATA5 pin-mux config register" bitfld.long 0x1C 12. "FV,OSPI1_DATA5 PAD Force Input Value when fin=0x2" "0,1" bitfld.long 0x1C 8.--9. "FIN,OSPI1_DATA5 PAD Force Input On/Off mode" "0,1,2,3" bitfld.long 0x1C 4. "ODE,OSPI1_DATA5 PAD Opn Drain Mode enable" "0,1" bitfld.long 0x1C 0.--2. "MUX,OSPI1_DATA5 PAD Pin-mux func select" "0,1,2,3,4,5,6,7" line.long 0x20 "PIN_MUX_CONFIG_OSPI1_DATA6,PAD OSPI1_DATA6 pin-mux config register" bitfld.long 0x20 12. "FV,OSPI1_DATA6 PAD Force Input Value when fin=0x2" "0,1" bitfld.long 0x20 8.--9. "FIN,OSPI1_DATA6 PAD Force Input On/Off mode" "0,1,2,3" bitfld.long 0x20 4. "ODE,OSPI1_DATA6 PAD Opn Drain Mode enable" "0,1" bitfld.long 0x20 0.--2. "MUX,OSPI1_DATA6 PAD Pin-mux func select" "0,1,2,3,4,5,6,7" line.long 0x24 "PIN_MUX_CONFIG_OSPI1_DATA7,PAD OSPI1_DATA7 pin-mux config register" bitfld.long 0x24 12. "FV,OSPI1_DATA7 PAD Force Input Value when fin=0x2" "0,1" bitfld.long 0x24 8.--9. "FIN,OSPI1_DATA7 PAD Force Input On/Off mode" "0,1,2,3" bitfld.long 0x24 4. "ODE,OSPI1_DATA7 PAD Opn Drain Mode enable" "0,1" bitfld.long 0x24 0.--2. "MUX,OSPI1_DATA7 PAD Pin-mux func select" "0,1,2,3,4,5,6,7" line.long 0x28 "PIN_MUX_CONFIG_OSPI1_DQS,PAD OSPI1_DQS pin-mux config register" bitfld.long 0x28 12. "FV,OSPI1_DQS PAD Force Input Value when fin=0x2" "0,1" bitfld.long 0x28 8.--9. "FIN,OSPI1_DQS PAD Force Input On/Off mode" "0,1,2,3" bitfld.long 0x28 4. "ODE,OSPI1_DQS PAD Opn Drain Mode enable" "0,1" bitfld.long 0x28 0.--2. "MUX,OSPI1_DQS PAD Pin-mux func select" "0,1,2,3,4,5,6,7" line.long 0x2C "PIN_MUX_CONFIG_OSPI1_SS1,PAD OSPI1_SS1 pin-mux config register" bitfld.long 0x2C 12. "FV,OSPI1_SS1 PAD Force Input Value when fin=0x2" "0,1" bitfld.long 0x2C 8.--9. "FIN,OSPI1_SS1 PAD Force Input On/Off mode" "0,1,2,3" bitfld.long 0x2C 4. "ODE,OSPI1_SS1 PAD Opn Drain Mode enable" "0,1" bitfld.long 0x2C 0.--2. "MUX,OSPI1_SS1 PAD Pin-mux func select" "0,1,2,3,4,5,6,7" line.long 0x30 "PIN_MUX_CONFIG_RGMII1_TXC,PAD RGMII1_TXC pin-mux config register" bitfld.long 0x30 12. "FV,RGMII1_TXC PAD Force Input Value when fin=0x2" "0,1" bitfld.long 0x30 8.--9. "FIN,RGMII1_TXC PAD Force Input On/Off mode" "0,1,2,3" bitfld.long 0x30 4. "ODE,RGMII1_TXC PAD Opn Drain Mode enable" "0,1" bitfld.long 0x30 0.--2. "MUX,RGMII1_TXC PAD Pin-mux func select" "0,1,2,3,4,5,6,7" line.long 0x34 "PIN_MUX_CONFIG_RGMII1_TXD0,PAD RGMII1_TXD0 pin-mux config register" bitfld.long 0x34 12. "FV,RGMII1_TXD0 PAD Force Input Value when fin=0x2" "0,1" bitfld.long 0x34 8.--9. "FIN,RGMII1_TXD0 PAD Force Input On/Off mode" "0,1,2,3" bitfld.long 0x34 4. "ODE,RGMII1_TXD0 PAD Opn Drain Mode enable" "0,1" bitfld.long 0x34 0.--2. "MUX,RGMII1_TXD0 PAD Pin-mux func select" "0,1,2,3,4,5,6,7" line.long 0x38 "PIN_MUX_CONFIG_RGMII1_TXD1,PAD RGMII1_TXD1 pin-mux config register" bitfld.long 0x38 12. "FV,RGMII1_TXD1 PAD Force Input Value when fin=0x2" "0,1" bitfld.long 0x38 8.--9. "FIN,RGMII1_TXD1 PAD Force Input On/Off mode" "0,1,2,3" bitfld.long 0x38 4. "ODE,RGMII1_TXD1 PAD Opn Drain Mode enable" "0,1" bitfld.long 0x38 0.--2. "MUX,RGMII1_TXD1 PAD Pin-mux func select" "0,1,2,3,4,5,6,7" line.long 0x3C "PIN_MUX_CONFIG_RGMII1_TXD2,PAD RGMII1_TXD2 pin-mux config register" bitfld.long 0x3C 12. "FV,RGMII1_TXD2 PAD Force Input Value when fin=0x2" "0,1" bitfld.long 0x3C 8.--9. "FIN,RGMII1_TXD2 PAD Force Input On/Off mode" "0,1,2,3" bitfld.long 0x3C 4. "ODE,RGMII1_TXD2 PAD Opn Drain Mode enable" "0,1" bitfld.long 0x3C 0.--2. "MUX,RGMII1_TXD2 PAD Pin-mux func select" "0,1,2,3,4,5,6,7" line.long 0x40 "PIN_MUX_CONFIG_RGMII1_TXD3,PAD RGMII1_TXD3 pin-mux config register" bitfld.long 0x40 12. "FV,RGMII1_TXD3 PAD Force Input Value when fin=0x2" "0,1" bitfld.long 0x40 8.--9. "FIN,RGMII1_TXD3 PAD Force Input On/Off mode" "0,1,2,3" bitfld.long 0x40 4. "ODE,RGMII1_TXD3 PAD Opn Drain Mode enable" "0,1" bitfld.long 0x40 0.--2. "MUX,RGMII1_TXD3 PAD Pin-mux func select" "0,1,2,3,4,5,6,7" line.long 0x44 "PIN_MUX_CONFIG_RGMII1_TX_CTL,PAD RGMII1_TX_CTL pin-mux config register" bitfld.long 0x44 12. "FV,RGMII1_TX_CTL PAD Force Input Value when fin=0x2" "0,1" bitfld.long 0x44 8.--9. "FIN,RGMII1_TX_CTL PAD Force Input On/Off mode" "0,1,2,3" bitfld.long 0x44 4. "ODE,RGMII1_TX_CTL PAD Opn Drain Mode enable" "0,1" bitfld.long 0x44 0.--2. "MUX,RGMII1_TX_CTL PAD Pin-mux func select" "0,1,2,3,4,5,6,7" line.long 0x48 "PIN_MUX_CONFIG_RGMII1_RXC,PAD RGMII1_RXC pin-mux config register" bitfld.long 0x48 12. "FV,RGMII1_RXC PAD Force Input Value when fin=0x2" "0,1" bitfld.long 0x48 8.--9. "FIN,RGMII1_RXC PAD Force Input On/Off mode" "0,1,2,3" bitfld.long 0x48 4. "ODE,RGMII1_RXC PAD Opn Drain Mode enable" "0,1" bitfld.long 0x48 0.--2. "MUX,RGMII1_RXC PAD Pin-mux func select" "0,1,2,3,4,5,6,7" line.long 0x4C "PIN_MUX_CONFIG_RGMII1_RXD0,PAD RGMII1_RXD0 pin-mux config register" bitfld.long 0x4C 12. "FV,RGMII1_RXD0 PAD Force Input Value when fin=0x2" "0,1" bitfld.long 0x4C 8.--9. "FIN,RGMII1_RXD0 PAD Force Input On/Off mode" "0,1,2,3" bitfld.long 0x4C 4. "ODE,RGMII1_RXD0 PAD Opn Drain Mode enable" "0,1" bitfld.long 0x4C 0.--2. "MUX,RGMII1_RXD0 PAD Pin-mux func select" "0,1,2,3,4,5,6,7" line.long 0x50 "PIN_MUX_CONFIG_RGMII1_RXD1,PAD RGMII1_RXD1 pin-mux config register" bitfld.long 0x50 12. "FV,RGMII1_RXD1 PAD Force Input Value when fin=0x2" "0,1" bitfld.long 0x50 8.--9. "FIN,RGMII1_RXD1 PAD Force Input On/Off mode" "0,1,2,3" bitfld.long 0x50 4. "ODE,RGMII1_RXD1 PAD Opn Drain Mode enable" "0,1" bitfld.long 0x50 0.--2. "MUX,RGMII1_RXD1 PAD Pin-mux func select" "0,1,2,3,4,5,6,7" line.long 0x54 "PIN_MUX_CONFIG_RGMII1_RXD2,PAD RGMII1_RXD2 pin-mux config register" bitfld.long 0x54 12. "FV,RGMII1_RXD2 PAD Force Input Value when fin=0x2" "0,1" bitfld.long 0x54 8.--9. "FIN,RGMII1_RXD2 PAD Force Input On/Off mode" "0,1,2,3" bitfld.long 0x54 4. "ODE,RGMII1_RXD2 PAD Opn Drain Mode enable" "0,1" bitfld.long 0x54 0.--2. "MUX,RGMII1_RXD2 PAD Pin-mux func select" "0,1,2,3,4,5,6,7" line.long 0x58 "PIN_MUX_CONFIG_RGMII1_RXD3,PAD RGMII1_RXD3 pin-mux config register" bitfld.long 0x58 12. "FV,RGMII1_RXD3 PAD Force Input Value when fin=0x2" "0,1" bitfld.long 0x58 8.--9. "FIN,RGMII1_RXD3 PAD Force Input On/Off mode" "0,1,2,3" bitfld.long 0x58 4. "ODE,RGMII1_RXD3 PAD Opn Drain Mode enable" "0,1" bitfld.long 0x58 0.--2. "MUX,RGMII1_RXD3 PAD Pin-mux func select" "0,1,2,3,4,5,6,7" line.long 0x5C "PIN_MUX_CONFIG_RGMII1_RX_CTL,PAD RGMII1_RX_CTL pin-mux config register" bitfld.long 0x5C 12. "FV,RGMII1_RX_CTL PAD Force Input Value when fin=0x2" "0,1" bitfld.long 0x5C 8.--9. "FIN,RGMII1_RX_CTL PAD Force Input On/Off mode" "0,1,2,3" bitfld.long 0x5C 4. "ODE,RGMII1_RX_CTL PAD Opn Drain Mode enable" "0,1" bitfld.long 0x5C 0.--2. "MUX,RGMII1_RX_CTL PAD Pin-mux func select" "0,1,2,3,4,5,6,7" line.long 0x60 "PIN_MUX_CONFIG_GPIO_A0,PAD GPIO_A0 pin-mux config register" bitfld.long 0x60 12. "FV,GPIO_A0 PAD Force Input Value when fin=0x2" "0,1" bitfld.long 0x60 8.--9. "FIN,GPIO_A0 PAD Force Input On/Off mode" "0,1,2,3" bitfld.long 0x60 4. "ODE,GPIO_A0 PAD Opn Drain Mode enable" "0,1" bitfld.long 0x60 0.--2. "MUX,GPIO_A0 PAD Pin-mux func select" "0,1,2,3,4,5,6,7" line.long 0x64 "PIN_MUX_CONFIG_GPIO_A1,PAD GPIO_A1 pin-mux config register" bitfld.long 0x64 12. "FV,GPIO_A1 PAD Force Input Value when fin=0x2" "0,1" bitfld.long 0x64 8.--9. "FIN,GPIO_A1 PAD Force Input On/Off mode" "0,1,2,3" bitfld.long 0x64 4. "ODE,GPIO_A1 PAD Opn Drain Mode enable" "0,1" bitfld.long 0x64 0.--2. "MUX,GPIO_A1 PAD Pin-mux func select" "0,1,2,3,4,5,6,7" line.long 0x68 "PIN_MUX_CONFIG_GPIO_A2,PAD GPIO_A2 pin-mux config register" bitfld.long 0x68 12. "FV,GPIO_A2 PAD Force Input Value when fin=0x2" "0,1" bitfld.long 0x68 8.--9. "FIN,GPIO_A2 PAD Force Input On/Off mode" "0,1,2,3" bitfld.long 0x68 4. "ODE,GPIO_A2 PAD Opn Drain Mode enable" "0,1" bitfld.long 0x68 0.--2. "MUX,GPIO_A2 PAD Pin-mux func select" "0,1,2,3,4,5,6,7" line.long 0x6C "PIN_MUX_CONFIG_GPIO_A3,PAD GPIO_A3 pin-mux config register" bitfld.long 0x6C 12. "FV,GPIO_A3 PAD Force Input Value when fin=0x2" "0,1" bitfld.long 0x6C 8.--9. "FIN,GPIO_A3 PAD Force Input On/Off mode" "0,1,2,3" bitfld.long 0x6C 4. "ODE,GPIO_A3 PAD Opn Drain Mode enable" "0,1" bitfld.long 0x6C 0.--2. "MUX,GPIO_A3 PAD Pin-mux func select" "0,1,2,3,4,5,6,7" line.long 0x70 "PIN_MUX_CONFIG_GPIO_A4,PAD GPIO_A4 pin-mux config register" bitfld.long 0x70 12. "FV,GPIO_A4 PAD Force Input Value when fin=0x2" "0,1" bitfld.long 0x70 8.--9. "FIN,GPIO_A4 PAD Force Input On/Off mode" "0,1,2,3" bitfld.long 0x70 4. "ODE,GPIO_A4 PAD Opn Drain Mode enable" "0,1" bitfld.long 0x70 0.--2. "MUX,GPIO_A4 PAD Pin-mux func select" "0,1,2,3,4,5,6,7" line.long 0x74 "PIN_MUX_CONFIG_GPIO_A5,PAD GPIO_A5 pin-mux config register" bitfld.long 0x74 12. "FV,GPIO_A5 PAD Force Input Value when fin=0x2" "0,1" bitfld.long 0x74 8.--9. "FIN,GPIO_A5 PAD Force Input On/Off mode" "0,1,2,3" bitfld.long 0x74 4. "ODE,GPIO_A5 PAD Opn Drain Mode enable" "0,1" bitfld.long 0x74 0.--2. "MUX,GPIO_A5 PAD Pin-mux func select" "0,1,2,3,4,5,6,7" line.long 0x78 "PIN_MUX_CONFIG_GPIO_A6,PAD GPIO_A6 pin-mux config register" bitfld.long 0x78 12. "FV,GPIO_A6 PAD Force Input Value when fin=0x2" "0,1" bitfld.long 0x78 8.--9. "FIN,GPIO_A6 PAD Force Input On/Off mode" "0,1,2,3" bitfld.long 0x78 4. "ODE,GPIO_A6 PAD Opn Drain Mode enable" "0,1" bitfld.long 0x78 0.--2. "MUX,GPIO_A6 PAD Pin-mux func select" "0,1,2,3,4,5,6,7" line.long 0x7C "PIN_MUX_CONFIG_GPIO_A7,PAD GPIO_A7 pin-mux config register" bitfld.long 0x7C 12. "FV,GPIO_A7 PAD Force Input Value when fin=0x2" "0,1" bitfld.long 0x7C 8.--9. "FIN,GPIO_A7 PAD Force Input On/Off mode" "0,1,2,3" bitfld.long 0x7C 4. "ODE,GPIO_A7 PAD Opn Drain Mode enable" "0,1" bitfld.long 0x7C 0.--2. "MUX,GPIO_A7 PAD Pin-mux func select" "0,1,2,3,4,5,6,7" line.long 0x80 "PIN_MUX_CONFIG_GPIO_A8,PAD GPIO_A8 pin-mux config register" bitfld.long 0x80 12. "FV,GPIO_A8 PAD Force Input Value when fin=0x2" "0,1" bitfld.long 0x80 8.--9. "FIN,GPIO_A8 PAD Force Input On/Off mode" "0,1,2,3" bitfld.long 0x80 4. "ODE,GPIO_A8 PAD Opn Drain Mode enable" "0,1" bitfld.long 0x80 0.--2. "MUX,GPIO_A8 PAD Pin-mux func select" "0,1,2,3,4,5,6,7" line.long 0x84 "PIN_MUX_CONFIG_GPIO_A9,PAD GPIO_A9 pin-mux config register" bitfld.long 0x84 12. "FV,GPIO_A9 PAD Force Input Value when fin=0x2" "0,1" bitfld.long 0x84 8.--9. "FIN,GPIO_A9 PAD Force Input On/Off mode" "0,1,2,3" bitfld.long 0x84 4. "ODE,GPIO_A9 PAD Opn Drain Mode enable" "0,1" bitfld.long 0x84 0.--2. "MUX,GPIO_A9 PAD Pin-mux func select" "0,1,2,3,4,5,6,7" line.long 0x88 "PIN_MUX_CONFIG_GPIO_A10,PAD GPIO_A10 pin-mux config register" bitfld.long 0x88 12. "FV,GPIO_A10 PAD Force Input Value when fin=0x2" "0,1" bitfld.long 0x88 8.--9. "FIN,GPIO_A10 PAD Force Input On/Off mode" "0,1,2,3" bitfld.long 0x88 4. "ODE,GPIO_A10 PAD Opn Drain Mode enable" "0,1" bitfld.long 0x88 0.--2. "MUX,GPIO_A10 PAD Pin-mux func select" "0,1,2,3,4,5,6,7" line.long 0x8C "PIN_MUX_CONFIG_GPIO_A11,PAD GPIO_A11 pin-mux config register" bitfld.long 0x8C 12. "FV,GPIO_A11 PAD Force Input Value when fin=0x2" "0,1" bitfld.long 0x8C 8.--9. "FIN,GPIO_A11 PAD Force Input On/Off mode" "0,1,2,3" bitfld.long 0x8C 4. "ODE,GPIO_A11 PAD Opn Drain Mode enable" "0,1" bitfld.long 0x8C 0.--2. "MUX,GPIO_A11 PAD Pin-mux func select" "0,1,2,3,4,5,6,7" line.long 0x90 "PIN_MUX_CONFIG_GPIO_B0,PAD GPIO_B0 pin-mux config register" bitfld.long 0x90 12. "FV,GPIO_B0 PAD Force Input Value when fin=0x2" "0,1" bitfld.long 0x90 8.--9. "FIN,GPIO_B0 PAD Force Input On/Off mode" "0,1,2,3" bitfld.long 0x90 4. "ODE,GPIO_B0 PAD Opn Drain Mode enable" "0,1" bitfld.long 0x90 0.--2. "MUX,GPIO_B0 PAD Pin-mux func select" "0,1,2,3,4,5,6,7" line.long 0x94 "PIN_MUX_CONFIG_GPIO_B1,PAD GPIO_B1 pin-mux config register" bitfld.long 0x94 12. "FV,GPIO_B1 PAD Force Input Value when fin=0x2" "0,1" bitfld.long 0x94 8.--9. "FIN,GPIO_B1 PAD Force Input On/Off mode" "0,1,2,3" bitfld.long 0x94 4. "ODE,GPIO_B1 PAD Opn Drain Mode enable" "0,1" bitfld.long 0x94 0.--2. "MUX,GPIO_B1 PAD Pin-mux func select" "0,1,2,3,4,5,6,7" line.long 0x98 "PIN_MUX_CONFIG_GPIO_B2,PAD GPIO_B2 pin-mux config register" bitfld.long 0x98 12. "FV,GPIO_B2 PAD Force Input Value when fin=0x2" "0,1" bitfld.long 0x98 8.--9. "FIN,GPIO_B2 PAD Force Input On/Off mode" "0,1,2,3" bitfld.long 0x98 4. "ODE,GPIO_B2 PAD Opn Drain Mode enable" "0,1" bitfld.long 0x98 0.--2. "MUX,GPIO_B2 PAD Pin-mux func select" "0,1,2,3,4,5,6,7" line.long 0x9C "PIN_MUX_CONFIG_GPIO_B3,PAD GPIO_B3 pin-mux config register" bitfld.long 0x9C 12. "FV,GPIO_B3 PAD Force Input Value when fin=0x2" "0,1" bitfld.long 0x9C 8.--9. "FIN,GPIO_B3 PAD Force Input On/Off mode" "0,1,2,3" bitfld.long 0x9C 4. "ODE,GPIO_B3 PAD Opn Drain Mode enable" "0,1" bitfld.long 0x9C 0.--2. "MUX,GPIO_B3 PAD Pin-mux func select" "0,1,2,3,4,5,6,7" line.long 0xA0 "PIN_MUX_CONFIG_GPIO_B4,PAD GPIO_B4 pin-mux config register" bitfld.long 0xA0 12. "FV,GPIO_B4 PAD Force Input Value when fin=0x2" "0,1" bitfld.long 0xA0 8.--9. "FIN,GPIO_B4 PAD Force Input On/Off mode" "0,1,2,3" bitfld.long 0xA0 4. "ODE,GPIO_B4 PAD Opn Drain Mode enable" "0,1" bitfld.long 0xA0 0.--2. "MUX,GPIO_B4 PAD Pin-mux func select" "0,1,2,3,4,5,6,7" line.long 0xA4 "PIN_MUX_CONFIG_GPIO_B5,PAD GPIO_B5 pin-mux config register" bitfld.long 0xA4 12. "FV,GPIO_B5 PAD Force Input Value when fin=0x2" "0,1" bitfld.long 0xA4 8.--9. "FIN,GPIO_B5 PAD Force Input On/Off mode" "0,1,2,3" bitfld.long 0xA4 4. "ODE,GPIO_B5 PAD Opn Drain Mode enable" "0,1" bitfld.long 0xA4 0.--2. "MUX,GPIO_B5 PAD Pin-mux func select" "0,1,2,3,4,5,6,7" line.long 0xA8 "PIN_MUX_CONFIG_GPIO_B6,PAD GPIO_B6 pin-mux config register" bitfld.long 0xA8 12. "FV,GPIO_B6 PAD Force Input Value when fin=0x2" "0,1" bitfld.long 0xA8 8.--9. "FIN,GPIO_B6 PAD Force Input On/Off mode" "0,1,2,3" bitfld.long 0xA8 4. "ODE,GPIO_B6 PAD Opn Drain Mode enable" "0,1" bitfld.long 0xA8 0.--2. "MUX,GPIO_B6 PAD Pin-mux func select" "0,1,2,3,4,5,6,7" line.long 0xAC "PIN_MUX_CONFIG_GPIO_B7,PAD GPIO_B7 pin-mux config register" bitfld.long 0xAC 12. "FV,GPIO_B7 PAD Force Input Value when fin=0x2" "0,1" bitfld.long 0xAC 8.--9. "FIN,GPIO_B7 PAD Force Input On/Off mode" "0,1,2,3" bitfld.long 0xAC 4. "ODE,GPIO_B7 PAD Opn Drain Mode enable" "0,1" bitfld.long 0xAC 0.--2. "MUX,GPIO_B7 PAD Pin-mux func select" "0,1,2,3,4,5,6,7" line.long 0xB0 "PIN_MUX_CONFIG_GPIO_B8,PAD GPIO_B8 pin-mux config register" bitfld.long 0xB0 12. "FV,GPIO_B8 PAD Force Input Value when fin=0x2" "0,1" bitfld.long 0xB0 8.--9. "FIN,GPIO_B8 PAD Force Input On/Off mode" "0,1,2,3" bitfld.long 0xB0 4. "ODE,GPIO_B8 PAD Opn Drain Mode enable" "0,1" bitfld.long 0xB0 0.--2. "MUX,GPIO_B8 PAD Pin-mux func select" "0,1,2,3,4,5,6,7" line.long 0xB4 "PIN_MUX_CONFIG_GPIO_B9,PAD GPIO_B9 pin-mux config register" bitfld.long 0xB4 12. "FV,GPIO_B9 PAD Force Input Value when fin=0x2" "0,1" bitfld.long 0xB4 8.--9. "FIN,GPIO_B9 PAD Force Input On/Off mode" "0,1,2,3" bitfld.long 0xB4 4. "ODE,GPIO_B9 PAD Opn Drain Mode enable" "0,1" bitfld.long 0xB4 0.--2. "MUX,GPIO_B9 PAD Pin-mux func select" "0,1,2,3,4,5,6,7" line.long 0xB8 "PIN_MUX_CONFIG_GPIO_B10,PAD GPIO_B10 pin-mux config register" bitfld.long 0xB8 12. "FV,GPIO_B10 PAD Force Input Value when fin=0x2" "0,1" bitfld.long 0xB8 8.--9. "FIN,GPIO_B10 PAD Force Input On/Off mode" "0,1,2,3" bitfld.long 0xB8 4. "ODE,GPIO_B10 PAD Opn Drain Mode enable" "0,1" bitfld.long 0xB8 0.--2. "MUX,GPIO_B10 PAD Pin-mux func select" "0,1,2,3,4,5,6,7" line.long 0xBC "PIN_MUX_CONFIG_GPIO_B11,PAD GPIO_B11 pin-mux config register" bitfld.long 0xBC 12. "FV,GPIO_B11 PAD Force Input Value when fin=0x2" "0,1" bitfld.long 0xBC 8.--9. "FIN,GPIO_B11 PAD Force Input On/Off mode" "0,1,2,3" bitfld.long 0xBC 4. "ODE,GPIO_B11 PAD Opn Drain Mode enable" "0,1" bitfld.long 0xBC 0.--2. "MUX,GPIO_B11 PAD Pin-mux func select" "0,1,2,3,4,5,6,7" group.long 0x400++0xCF line.long 0x0 "INPUT_SOURCE_SELECT_CANFD1_RX,CANFD1_RX input source select register" bitfld.long 0x0 0.--1. "SRC_SEL,source select" "0,1,2,3" line.long 0x4 "INPUT_SOURCE_SELECT_CANFD2_RX,CANFD2_RX input source select register" bitfld.long 0x4 0.--1. "SRC_SEL,source select" "0,1,2,3" line.long 0x8 "INPUT_SOURCE_SELECT_SPI4_SCLK,SPI4_SCLK input source select register" bitfld.long 0x8 0. "SRC_SEL,source select" "0,1" line.long 0xC "INPUT_SOURCE_SELECT_SPI4_SS,SPI4_SS input source select register" bitfld.long 0xC 0. "SRC_SEL,source select" "0,1" line.long 0x10 "INPUT_SOURCE_SELECT_SPI4_MISO,SPI4_MISO input source select register" bitfld.long 0x10 0. "SRC_SEL,source select" "0,1" line.long 0x14 "INPUT_SOURCE_SELECT_SPI4_MOSI,SPI4_MOSI input source select register" bitfld.long 0x14 0. "SRC_SEL,source select" "0,1" line.long 0x18 "INPUT_SOURCE_SELECT_UART5_RX,UART5_RX input source select register" bitfld.long 0x18 0. "SRC_SEL,source select" "0,1" line.long 0x1C "INPUT_SOURCE_SELECT_ENET1_MDIO,ENET1_MDIO input source select register" bitfld.long 0x1C 0.--2. "SRC_SEL,source select" "0,1,2,3,4,5,6,7" line.long 0x20 "INPUT_SOURCE_SELECT_I2C2_SCL,I2C2_SCL input source select register" bitfld.long 0x20 0.--1. "SRC_SEL,source select" "0,1,2,3" line.long 0x24 "INPUT_SOURCE_SELECT_ENET1_AUS_IN_1,ENET1_AUS_IN_1 input source select register" bitfld.long 0x24 0. "SRC_SEL,source select" "0,1" line.long 0x28 "INPUT_SOURCE_SELECT_I2C2_SDA,I2C2_SDA input source select register" bitfld.long 0x28 0.--1. "SRC_SEL,source select" "0,1,2,3" line.long 0x2C "INPUT_SOURCE_SELECT_ENET1_AUS_IN_2,ENET1_AUS_IN_2 input source select register" bitfld.long 0x2C 0. "SRC_SEL,source select" "0,1" line.long 0x30 "INPUT_SOURCE_SELECT_SPI3_SCLK,SPI3_SCLK input source select register" bitfld.long 0x30 0. "SRC_SEL,source select" "0,1" line.long 0x34 "INPUT_SOURCE_SELECT_TIMER1_CH0,TIMER1_CH0 input source select register" bitfld.long 0x34 0. "SRC_SEL,source select" "0,1" line.long 0x38 "INPUT_SOURCE_SELECT_ENET1_CAP_COMP_0,ENET1_CAP_COMP_0 input source select register" bitfld.long 0x38 0. "SRC_SEL,source select" "0,1" line.long 0x3C "INPUT_SOURCE_SELECT_SPI3_MISO,SPI3_MISO input source select register" bitfld.long 0x3C 0. "SRC_SEL,source select" "0,1" line.long 0x40 "INPUT_SOURCE_SELECT_UART7_RX,UART7_RX input source select register" bitfld.long 0x40 0. "SRC_SEL,source select" "0,1" line.long 0x44 "INPUT_SOURCE_SELECT_CANFD3_RX,CANFD3_RX input source select register" bitfld.long 0x44 0. "SRC_SEL,source select" "0,1" line.long 0x48 "INPUT_SOURCE_SELECT_TIMER1_CH1,TIMER1_CH1 input source select register" bitfld.long 0x48 0. "SRC_SEL,source select" "0,1" line.long 0x4C "INPUT_SOURCE_SELECT_ENET1_CAP_COMP_1,ENET1_CAP_COMP_1 input source select register" bitfld.long 0x4C 0. "SRC_SEL,source select" "0,1" line.long 0x50 "INPUT_SOURCE_SELECT_SPI3_MOSI,SPI3_MOSI input source select register" bitfld.long 0x50 0. "SRC_SEL,source select" "0,1" line.long 0x54 "INPUT_SOURCE_SELECT_ENET1_CAP_COMP_2,ENET1_CAP_COMP_2 input source select register" bitfld.long 0x54 0. "SRC_SEL,source select" "0,1" line.long 0x58 "INPUT_SOURCE_SELECT_SPI3_SS,SPI3_SS input source select register" bitfld.long 0x58 0. "SRC_SEL,source select" "0,1" line.long 0x5C "INPUT_SOURCE_SELECT_CANFD4_RX,CANFD4_RX input source select register" bitfld.long 0x5C 0. "SRC_SEL,source select" "0,1" line.long 0x60 "INPUT_SOURCE_SELECT_ENET1_CAP_COMP_3,ENET1_CAP_COMP_3 input source select register" bitfld.long 0x60 0. "SRC_SEL,source select" "0,1" line.long 0x64 "INPUT_SOURCE_SELECT_I2C1_SCL,I2C1_SCL input source select register" bitfld.long 0x64 0.--1. "SRC_SEL,source select" "0,1,2,3" line.long 0x68 "INPUT_SOURCE_SELECT_ENET1_AUS_IN_0,ENET1_AUS_IN_0 input source select register" bitfld.long 0x68 0. "SRC_SEL,source select" "0,1" line.long 0x6C "INPUT_SOURCE_SELECT_I2C1_SDA,I2C1_SDA input source select register" bitfld.long 0x6C 0.--1. "SRC_SEL,source select" "0,1,2,3" line.long 0x70 "INPUT_SOURCE_SELECT_SPI1_SCLK,SPI1_SCLK input source select register" bitfld.long 0x70 0. "SRC_SEL,source select" "0,1" line.long 0x74 "INPUT_SOURCE_SELECT_I2S_SC1_SCK,I2S_SC1_SCK input source select register" bitfld.long 0x74 0. "SRC_SEL,source select" "0,1" line.long 0x78 "INPUT_SOURCE_SELECT_TIMER1_CH2,TIMER1_CH2 input source select register" bitfld.long 0x78 0. "SRC_SEL,source select" "0,1" line.long 0x7C "INPUT_SOURCE_SELECT_SPI1_MISO,SPI1_MISO input source select register" bitfld.long 0x7C 0. "SRC_SEL,source select" "0,1" line.long 0x80 "INPUT_SOURCE_SELECT_TIMER1_CH3,TIMER1_CH3 input source select register" bitfld.long 0x80 0. "SRC_SEL,source select" "0,1" line.long 0x84 "INPUT_SOURCE_SELECT_SPI1_MOSI,SPI1_MOSI input source select register" bitfld.long 0x84 0. "SRC_SEL,source select" "0,1" line.long 0x88 "INPUT_SOURCE_SELECT_I2S_SC1_SDI_SDO,I2S_SC1_SDI_SDO input source select register" bitfld.long 0x88 0.--1. "SRC_SEL,source select" "0,1,2,3" line.long 0x8C "INPUT_SOURCE_SELECT_SPI1_SS,SPI1_SS input source select register" bitfld.long 0x8C 0. "SRC_SEL,source select" "0,1" line.long 0x90 "INPUT_SOURCE_SELECT_I2S_SC1_WS,I2S_SC1_WS input source select register" bitfld.long 0x90 0. "SRC_SEL,source select" "0,1" line.long 0x94 "INPUT_SOURCE_SELECT_SPI2_SCLK,SPI2_SCLK input source select register" bitfld.long 0x94 0. "SRC_SEL,source select" "0,1" line.long 0x98 "INPUT_SOURCE_SELECT_I2S_SC2_SCK,I2S_SC2_SCK input source select register" bitfld.long 0x98 0. "SRC_SEL,source select" "0,1" line.long 0x9C "INPUT_SOURCE_SELECT_SPI2_MISO,SPI2_MISO input source select register" bitfld.long 0x9C 0. "SRC_SEL,source select" "0,1" line.long 0xA0 "INPUT_SOURCE_SELECT_SPI2_MOSI,SPI2_MOSI input source select register" bitfld.long 0xA0 0. "SRC_SEL,source select" "0,1" line.long 0xA4 "INPUT_SOURCE_SELECT_I2S_SC2_SDI_SDO,I2S_SC2_SDI_SDO input source select register" bitfld.long 0xA4 0.--1. "SRC_SEL,source select" "0,1,2,3" line.long 0xA8 "INPUT_SOURCE_SELECT_SPI2_SS,SPI2_SS input source select register" bitfld.long 0xA8 0. "SRC_SEL,source select" "0,1" line.long 0xAC "INPUT_SOURCE_SELECT_I2S_SC2_WS,I2S_SC2_WS input source select register" bitfld.long 0xAC 0. "SRC_SEL,source select" "0,1" line.long 0xB0 "INPUT_SOURCE_SELECT_I2C3_SCL,I2C3_SCL input source select register" bitfld.long 0xB0 0.--1. "SRC_SEL,source select" "0,1,2,3" line.long 0xB4 "INPUT_SOURCE_SELECT_I2C3_SDA,I2C3_SDA input source select register" bitfld.long 0xB4 0.--1. "SRC_SEL,source select" "0,1,2,3" line.long 0xB8 "INPUT_SOURCE_SELECT_TIMER2_CH0,TIMER2_CH0 input source select register" bitfld.long 0xB8 0. "SRC_SEL,source select" "0,1" line.long 0xBC "INPUT_SOURCE_SELECT_I2C4_SCL,I2C4_SCL input source select register" bitfld.long 0xBC 0.--1. "SRC_SEL,source select" "0,1,2,3" line.long 0xC0 "INPUT_SOURCE_SELECT_TIMER2_CH1,TIMER2_CH1 input source select register" bitfld.long 0xC0 0. "SRC_SEL,source select" "0,1" line.long 0xC4 "INPUT_SOURCE_SELECT_I2C4_SDA,I2C4_SDA input source select register" bitfld.long 0xC4 0.--1. "SRC_SEL,source select" "0,1,2,3" line.long 0xC8 "INPUT_SOURCE_SELECT_TIMER2_CH2,TIMER2_CH2 input source select register" bitfld.long 0xC8 0. "SRC_SEL,source select" "0,1" line.long 0xCC "INPUT_SOURCE_SELECT_TIMER2_CH3,TIMER2_CH3 input source select register" bitfld.long 0xCC 0. "SRC_SEL,source select" "0,1" tree.end elif (CORENAME()=="CORTEXA55") tree "PINCTRL_AP" base ad:0x38500000 group.long 0x0++0x1AF line.long 0x0 "IO_PAD_CONFIG_GPIO_C0,PAD GPIO_C0 config register" bitfld.long 0x0 16. "POE,GPIO_C0 PAD Parametric output enable" "0,1" bitfld.long 0x0 12. "IS,GPIO_C0 PAD Input select" "0,1" bitfld.long 0x0 8. "SR,GPIO_C0 PAD Slew rate" "0,1" newline bitfld.long 0x0 4.--5. "DS,GPIO_C0 PAD Driver select" "0,1,2,3" bitfld.long 0x0 1. "PS,GPIO_C0 PAD Pull select" "0,1" bitfld.long 0x0 0. "PE,GPIO_C0 PAD Pull enable" "0,1" line.long 0x4 "IO_PAD_CONFIG_GPIO_C1,PAD GPIO_C1 config register" bitfld.long 0x4 16. "POE,GPIO_C1 PAD Parametric output enable" "0,1" bitfld.long 0x4 12. "IS,GPIO_C1 PAD Input select" "0,1" bitfld.long 0x4 8. "SR,GPIO_C1 PAD Slew rate" "0,1" newline bitfld.long 0x4 4.--5. "DS,GPIO_C1 PAD Driver select" "0,1,2,3" bitfld.long 0x4 1. "PS,GPIO_C1 PAD Pull select" "0,1" bitfld.long 0x4 0. "PE,GPIO_C1 PAD Pull enable" "0,1" line.long 0x8 "IO_PAD_CONFIG_GPIO_C2,PAD GPIO_C2 config register" bitfld.long 0x8 16. "POE,GPIO_C2 PAD Parametric output enable" "0,1" bitfld.long 0x8 12. "IS,GPIO_C2 PAD Input select" "0,1" bitfld.long 0x8 8. "SR,GPIO_C2 PAD Slew rate" "0,1" newline bitfld.long 0x8 4.--5. "DS,GPIO_C2 PAD Driver select" "0,1,2,3" bitfld.long 0x8 1. "PS,GPIO_C2 PAD Pull select" "0,1" bitfld.long 0x8 0. "PE,GPIO_C2 PAD Pull enable" "0,1" line.long 0xC "IO_PAD_CONFIG_GPIO_C3,PAD GPIO_C3 config register" bitfld.long 0xC 16. "POE,GPIO_C3 PAD Parametric output enable" "0,1" bitfld.long 0xC 12. "IS,GPIO_C3 PAD Input select" "0,1" bitfld.long 0xC 8. "SR,GPIO_C3 PAD Slew rate" "0,1" newline bitfld.long 0xC 4.--5. "DS,GPIO_C3 PAD Driver select" "0,1,2,3" bitfld.long 0xC 1. "PS,GPIO_C3 PAD Pull select" "0,1" bitfld.long 0xC 0. "PE,GPIO_C3 PAD Pull enable" "0,1" line.long 0x10 "IO_PAD_CONFIG_GPIO_C4,PAD GPIO_C4 config register" bitfld.long 0x10 16. "POE,GPIO_C4 PAD Parametric output enable" "0,1" bitfld.long 0x10 12. "IS,GPIO_C4 PAD Input select" "0,1" bitfld.long 0x10 8. "SR,GPIO_C4 PAD Slew rate" "0,1" newline bitfld.long 0x10 4.--5. "DS,GPIO_C4 PAD Driver select" "0,1,2,3" bitfld.long 0x10 1. "PS,GPIO_C4 PAD Pull select" "0,1" bitfld.long 0x10 0. "PE,GPIO_C4 PAD Pull enable" "0,1" line.long 0x14 "IO_PAD_CONFIG_GPIO_C5,PAD GPIO_C5 config register" bitfld.long 0x14 16. "POE,GPIO_C5 PAD Parametric output enable" "0,1" bitfld.long 0x14 12. "IS,GPIO_C5 PAD Input select" "0,1" bitfld.long 0x14 8. "SR,GPIO_C5 PAD Slew rate" "0,1" newline bitfld.long 0x14 4.--5. "DS,GPIO_C5 PAD Driver select" "0,1,2,3" bitfld.long 0x14 1. "PS,GPIO_C5 PAD Pull select" "0,1" bitfld.long 0x14 0. "PE,GPIO_C5 PAD Pull enable" "0,1" line.long 0x18 "IO_PAD_CONFIG_GPIO_C6,PAD GPIO_C6 config register" bitfld.long 0x18 16. "POE,GPIO_C6 PAD Parametric output enable" "0,1" bitfld.long 0x18 12. "IS,GPIO_C6 PAD Input select" "0,1" bitfld.long 0x18 8. "SR,GPIO_C6 PAD Slew rate" "0,1" newline bitfld.long 0x18 4.--5. "DS,GPIO_C6 PAD Driver select" "0,1,2,3" bitfld.long 0x18 1. "PS,GPIO_C6 PAD Pull select" "0,1" bitfld.long 0x18 0. "PE,GPIO_C6 PAD Pull enable" "0,1" line.long 0x1C "IO_PAD_CONFIG_GPIO_C7,PAD GPIO_C7 config register" bitfld.long 0x1C 16. "POE,GPIO_C7 PAD Parametric output enable" "0,1" bitfld.long 0x1C 12. "IS,GPIO_C7 PAD Input select" "0,1" bitfld.long 0x1C 8. "SR,GPIO_C7 PAD Slew rate" "0,1" newline bitfld.long 0x1C 4.--5. "DS,GPIO_C7 PAD Driver select" "0,1,2,3" bitfld.long 0x1C 1. "PS,GPIO_C7 PAD Pull select" "0,1" bitfld.long 0x1C 0. "PE,GPIO_C7 PAD Pull enable" "0,1" line.long 0x20 "IO_PAD_CONFIG_GPIO_C8,PAD GPIO_C8 config register" bitfld.long 0x20 16. "POE,GPIO_C8 PAD Parametric output enable" "0,1" bitfld.long 0x20 12. "IS,GPIO_C8 PAD Input select" "0,1" bitfld.long 0x20 8. "SR,GPIO_C8 PAD Slew rate" "0,1" newline bitfld.long 0x20 4.--5. "DS,GPIO_C8 PAD Driver select" "0,1,2,3" bitfld.long 0x20 1. "PS,GPIO_C8 PAD Pull select" "0,1" bitfld.long 0x20 0. "PE,GPIO_C8 PAD Pull enable" "0,1" line.long 0x24 "IO_PAD_CONFIG_GPIO_C9,PAD GPIO_C9 config register" bitfld.long 0x24 16. "POE,GPIO_C9 PAD Parametric output enable" "0,1" bitfld.long 0x24 12. "IS,GPIO_C9 PAD Input select" "0,1" bitfld.long 0x24 8. "SR,GPIO_C9 PAD Slew rate" "0,1" newline bitfld.long 0x24 4.--5. "DS,GPIO_C9 PAD Driver select" "0,1,2,3" bitfld.long 0x24 1. "PS,GPIO_C9 PAD Pull select" "0,1" bitfld.long 0x24 0. "PE,GPIO_C9 PAD Pull enable" "0,1" line.long 0x28 "IO_PAD_CONFIG_GPIO_C10,PAD GPIO_C10 config register" bitfld.long 0x28 16. "POE,GPIO_C10 PAD Parametric output enable" "0,1" bitfld.long 0x28 12. "IS,GPIO_C10 PAD Input select" "0,1" bitfld.long 0x28 8. "SR,GPIO_C10 PAD Slew rate" "0,1" newline bitfld.long 0x28 4.--5. "DS,GPIO_C10 PAD Driver select" "0,1,2,3" bitfld.long 0x28 1. "PS,GPIO_C10 PAD Pull select" "0,1" bitfld.long 0x28 0. "PE,GPIO_C10 PAD Pull enable" "0,1" line.long 0x2C "IO_PAD_CONFIG_GPIO_C11,PAD GPIO_C11 config register" bitfld.long 0x2C 16. "POE,GPIO_C11 PAD Parametric output enable" "0,1" bitfld.long 0x2C 12. "IS,GPIO_C11 PAD Input select" "0,1" bitfld.long 0x2C 8. "SR,GPIO_C11 PAD Slew rate" "0,1" newline bitfld.long 0x2C 4.--5. "DS,GPIO_C11 PAD Driver select" "0,1,2,3" bitfld.long 0x2C 1. "PS,GPIO_C11 PAD Pull select" "0,1" bitfld.long 0x2C 0. "PE,GPIO_C11 PAD Pull enable" "0,1" line.long 0x30 "IO_PAD_CONFIG_GPIO_C12,PAD GPIO_C12 config register" bitfld.long 0x30 16. "POE,GPIO_C12 PAD Parametric output enable" "0,1" bitfld.long 0x30 12. "IS,GPIO_C12 PAD Input select" "0,1" bitfld.long 0x30 8. "SR,GPIO_C12 PAD Slew rate" "0,1" newline bitfld.long 0x30 4.--5. "DS,GPIO_C12 PAD Driver select" "0,1,2,3" bitfld.long 0x30 1. "PS,GPIO_C12 PAD Pull select" "0,1" bitfld.long 0x30 0. "PE,GPIO_C12 PAD Pull enable" "0,1" line.long 0x34 "IO_PAD_CONFIG_GPIO_C13,PAD GPIO_C13 config register" bitfld.long 0x34 16. "POE,GPIO_C13 PAD Parametric output enable" "0,1" bitfld.long 0x34 12. "IS,GPIO_C13 PAD Input select" "0,1" bitfld.long 0x34 8. "SR,GPIO_C13 PAD Slew rate" "0,1" newline bitfld.long 0x34 4.--5. "DS,GPIO_C13 PAD Driver select" "0,1,2,3" bitfld.long 0x34 1. "PS,GPIO_C13 PAD Pull select" "0,1" bitfld.long 0x34 0. "PE,GPIO_C13 PAD Pull enable" "0,1" line.long 0x38 "IO_PAD_CONFIG_GPIO_C14,PAD GPIO_C14 config register" bitfld.long 0x38 16. "POE,GPIO_C14 PAD Parametric output enable" "0,1" bitfld.long 0x38 12. "IS,GPIO_C14 PAD Input select" "0,1" bitfld.long 0x38 8. "SR,GPIO_C14 PAD Slew rate" "0,1" newline bitfld.long 0x38 4.--5. "DS,GPIO_C14 PAD Driver select" "0,1,2,3" bitfld.long 0x38 1. "PS,GPIO_C14 PAD Pull select" "0,1" bitfld.long 0x38 0. "PE,GPIO_C14 PAD Pull enable" "0,1" line.long 0x3C "IO_PAD_CONFIG_GPIO_C15,PAD GPIO_C15 config register" bitfld.long 0x3C 16. "POE,GPIO_C15 PAD Parametric output enable" "0,1" bitfld.long 0x3C 12. "IS,GPIO_C15 PAD Input select" "0,1" bitfld.long 0x3C 8. "SR,GPIO_C15 PAD Slew rate" "0,1" newline bitfld.long 0x3C 4.--5. "DS,GPIO_C15 PAD Driver select" "0,1,2,3" bitfld.long 0x3C 1. "PS,GPIO_C15 PAD Pull select" "0,1" bitfld.long 0x3C 0. "PE,GPIO_C15 PAD Pull enable" "0,1" line.long 0x40 "IO_PAD_CONFIG_GPIO_D0,PAD GPIO_D0 config register" bitfld.long 0x40 16. "POE,GPIO_D0 PAD Parametric output enable" "0,1" bitfld.long 0x40 12. "IS,GPIO_D0 PAD Input select" "0,1" bitfld.long 0x40 8. "SR,GPIO_D0 PAD Slew rate" "0,1" newline bitfld.long 0x40 4.--5. "DS,GPIO_D0 PAD Driver select" "0,1,2,3" bitfld.long 0x40 1. "PS,GPIO_D0 PAD Pull select" "0,1" bitfld.long 0x40 0. "PE,GPIO_D0 PAD Pull enable" "0,1" line.long 0x44 "IO_PAD_CONFIG_GPIO_D1,PAD GPIO_D1 config register" bitfld.long 0x44 16. "POE,GPIO_D1 PAD Parametric output enable" "0,1" bitfld.long 0x44 12. "IS,GPIO_D1 PAD Input select" "0,1" bitfld.long 0x44 8. "SR,GPIO_D1 PAD Slew rate" "0,1" newline bitfld.long 0x44 4.--5. "DS,GPIO_D1 PAD Driver select" "0,1,2,3" bitfld.long 0x44 1. "PS,GPIO_D1 PAD Pull select" "0,1" bitfld.long 0x44 0. "PE,GPIO_D1 PAD Pull enable" "0,1" line.long 0x48 "IO_PAD_CONFIG_GPIO_D2,PAD GPIO_D2 config register" bitfld.long 0x48 16. "POE,GPIO_D2 PAD Parametric output enable" "0,1" bitfld.long 0x48 12. "IS,GPIO_D2 PAD Input select" "0,1" bitfld.long 0x48 8. "SR,GPIO_D2 PAD Slew rate" "0,1" newline bitfld.long 0x48 4.--5. "DS,GPIO_D2 PAD Driver select" "0,1,2,3" bitfld.long 0x48 1. "PS,GPIO_D2 PAD Pull select" "0,1" bitfld.long 0x48 0. "PE,GPIO_D2 PAD Pull enable" "0,1" line.long 0x4C "IO_PAD_CONFIG_GPIO_D3,PAD GPIO_D3 config register" bitfld.long 0x4C 16. "POE,GPIO_D3 PAD Parametric output enable" "0,1" bitfld.long 0x4C 12. "IS,GPIO_D3 PAD Input select" "0,1" bitfld.long 0x4C 8. "SR,GPIO_D3 PAD Slew rate" "0,1" newline bitfld.long 0x4C 4.--5. "DS,GPIO_D3 PAD Driver select" "0,1,2,3" bitfld.long 0x4C 1. "PS,GPIO_D3 PAD Pull select" "0,1" bitfld.long 0x4C 0. "PE,GPIO_D3 PAD Pull enable" "0,1" line.long 0x50 "IO_PAD_CONFIG_GPIO_D4,PAD GPIO_D4 config register" bitfld.long 0x50 16. "POE,GPIO_D4 PAD Parametric output enable" "0,1" bitfld.long 0x50 12. "IS,GPIO_D4 PAD Input select" "0,1" bitfld.long 0x50 8. "SR,GPIO_D4 PAD Slew rate" "0,1" newline bitfld.long 0x50 4.--5. "DS,GPIO_D4 PAD Driver select" "0,1,2,3" bitfld.long 0x50 1. "PS,GPIO_D4 PAD Pull select" "0,1" bitfld.long 0x50 0. "PE,GPIO_D4 PAD Pull enable" "0,1" line.long 0x54 "IO_PAD_CONFIG_GPIO_D5,PAD GPIO_D5 config register" bitfld.long 0x54 16. "POE,GPIO_D5 PAD Parametric output enable" "0,1" bitfld.long 0x54 12. "IS,GPIO_D5 PAD Input select" "0,1" bitfld.long 0x54 8. "SR,GPIO_D5 PAD Slew rate" "0,1" newline bitfld.long 0x54 4.--5. "DS,GPIO_D5 PAD Driver select" "0,1,2,3" bitfld.long 0x54 1. "PS,GPIO_D5 PAD Pull select" "0,1" bitfld.long 0x54 0. "PE,GPIO_D5 PAD Pull enable" "0,1" line.long 0x58 "IO_PAD_CONFIG_GPIO_D6,PAD GPIO_D6 config register" bitfld.long 0x58 16. "POE,GPIO_D6 PAD Parametric output enable" "0,1" bitfld.long 0x58 12. "IS,GPIO_D6 PAD Input select" "0,1" bitfld.long 0x58 8. "SR,GPIO_D6 PAD Slew rate" "0,1" newline bitfld.long 0x58 4.--5. "DS,GPIO_D6 PAD Driver select" "0,1,2,3" bitfld.long 0x58 1. "PS,GPIO_D6 PAD Pull select" "0,1" bitfld.long 0x58 0. "PE,GPIO_D6 PAD Pull enable" "0,1" line.long 0x5C "IO_PAD_CONFIG_GPIO_D7,PAD GPIO_D7 config register" bitfld.long 0x5C 16. "POE,GPIO_D7 PAD Parametric output enable" "0,1" bitfld.long 0x5C 12. "IS,GPIO_D7 PAD Input select" "0,1" bitfld.long 0x5C 8. "SR,GPIO_D7 PAD Slew rate" "0,1" newline bitfld.long 0x5C 4.--5. "DS,GPIO_D7 PAD Driver select" "0,1,2,3" bitfld.long 0x5C 1. "PS,GPIO_D7 PAD Pull select" "0,1" bitfld.long 0x5C 0. "PE,GPIO_D7 PAD Pull enable" "0,1" line.long 0x60 "IO_PAD_CONFIG_GPIO_D8,PAD GPIO_D8 config register" bitfld.long 0x60 16. "POE,GPIO_D8 PAD Parametric output enable" "0,1" bitfld.long 0x60 12. "IS,GPIO_D8 PAD Input select" "0,1" bitfld.long 0x60 8. "SR,GPIO_D8 PAD Slew rate" "0,1" newline bitfld.long 0x60 4.--5. "DS,GPIO_D8 PAD Driver select" "0,1,2,3" bitfld.long 0x60 1. "PS,GPIO_D8 PAD Pull select" "0,1" bitfld.long 0x60 0. "PE,GPIO_D8 PAD Pull enable" "0,1" line.long 0x64 "IO_PAD_CONFIG_GPIO_D9,PAD GPIO_D9 config register" bitfld.long 0x64 16. "POE,GPIO_D9 PAD Parametric output enable" "0,1" bitfld.long 0x64 12. "IS,GPIO_D9 PAD Input select" "0,1" bitfld.long 0x64 8. "SR,GPIO_D9 PAD Slew rate" "0,1" newline bitfld.long 0x64 4.--5. "DS,GPIO_D9 PAD Driver select" "0,1,2,3" bitfld.long 0x64 1. "PS,GPIO_D9 PAD Pull select" "0,1" bitfld.long 0x64 0. "PE,GPIO_D9 PAD Pull enable" "0,1" line.long 0x68 "IO_PAD_CONFIG_GPIO_D10,PAD GPIO_D10 config register" bitfld.long 0x68 16. "POE,GPIO_D10 PAD Parametric output enable" "0,1" bitfld.long 0x68 12. "IS,GPIO_D10 PAD Input select" "0,1" bitfld.long 0x68 8. "SR,GPIO_D10 PAD Slew rate" "0,1" newline bitfld.long 0x68 4.--5. "DS,GPIO_D10 PAD Driver select" "0,1,2,3" bitfld.long 0x68 1. "PS,GPIO_D10 PAD Pull select" "0,1" bitfld.long 0x68 0. "PE,GPIO_D10 PAD Pull enable" "0,1" line.long 0x6C "IO_PAD_CONFIG_GPIO_D11,PAD GPIO_D11 config register" bitfld.long 0x6C 16. "POE,GPIO_D11 PAD Parametric output enable" "0,1" bitfld.long 0x6C 12. "IS,GPIO_D11 PAD Input select" "0,1" bitfld.long 0x6C 8. "SR,GPIO_D11 PAD Slew rate" "0,1" newline bitfld.long 0x6C 4.--5. "DS,GPIO_D11 PAD Driver select" "0,1,2,3" bitfld.long 0x6C 1. "PS,GPIO_D11 PAD Pull select" "0,1" bitfld.long 0x6C 0. "PE,GPIO_D11 PAD Pull enable" "0,1" line.long 0x70 "IO_PAD_CONFIG_GPIO_D12,PAD GPIO_D12 config register" bitfld.long 0x70 16. "POE,GPIO_D12 PAD Parametric output enable" "0,1" bitfld.long 0x70 12. "IS,GPIO_D12 PAD Input select" "0,1" bitfld.long 0x70 8. "SR,GPIO_D12 PAD Slew rate" "0,1" newline bitfld.long 0x70 4.--5. "DS,GPIO_D12 PAD Driver select" "0,1,2,3" bitfld.long 0x70 1. "PS,GPIO_D12 PAD Pull select" "0,1" bitfld.long 0x70 0. "PE,GPIO_D12 PAD Pull enable" "0,1" line.long 0x74 "IO_PAD_CONFIG_GPIO_D13,PAD GPIO_D13 config register" bitfld.long 0x74 16. "POE,GPIO_D13 PAD Parametric output enable" "0,1" bitfld.long 0x74 12. "IS,GPIO_D13 PAD Input select" "0,1" bitfld.long 0x74 8. "SR,GPIO_D13 PAD Slew rate" "0,1" newline bitfld.long 0x74 4.--5. "DS,GPIO_D13 PAD Driver select" "0,1,2,3" bitfld.long 0x74 1. "PS,GPIO_D13 PAD Pull select" "0,1" bitfld.long 0x74 0. "PE,GPIO_D13 PAD Pull enable" "0,1" line.long 0x78 "IO_PAD_CONFIG_GPIO_D14,PAD GPIO_D14 config register" bitfld.long 0x78 16. "POE,GPIO_D14 PAD Parametric output enable" "0,1" bitfld.long 0x78 12. "IS,GPIO_D14 PAD Input select" "0,1" bitfld.long 0x78 8. "SR,GPIO_D14 PAD Slew rate" "0,1" newline bitfld.long 0x78 4.--5. "DS,GPIO_D14 PAD Driver select" "0,1,2,3" bitfld.long 0x78 1. "PS,GPIO_D14 PAD Pull select" "0,1" bitfld.long 0x78 0. "PE,GPIO_D14 PAD Pull enable" "0,1" line.long 0x7C "IO_PAD_CONFIG_GPIO_D15,PAD GPIO_D15 config register" bitfld.long 0x7C 16. "POE,GPIO_D15 PAD Parametric output enable" "0,1" bitfld.long 0x7C 12. "IS,GPIO_D15 PAD Input select" "0,1" bitfld.long 0x7C 8. "SR,GPIO_D15 PAD Slew rate" "0,1" newline bitfld.long 0x7C 4.--5. "DS,GPIO_D15 PAD Driver select" "0,1,2,3" bitfld.long 0x7C 1. "PS,GPIO_D15 PAD Pull select" "0,1" bitfld.long 0x7C 0. "PE,GPIO_D15 PAD Pull enable" "0,1" line.long 0x80 "IO_PAD_CONFIG_OSPI2_SCLK,PAD OSPI2_SCLK config register" bitfld.long 0x80 16. "POE,OSPI2_SCLK PAD Parametric output enable" "0,1" bitfld.long 0x80 12. "IS,OSPI2_SCLK PAD Input select" "0,1" bitfld.long 0x80 8. "SR,OSPI2_SCLK PAD Slew rate" "0,1" newline bitfld.long 0x80 4.--5. "DS,OSPI2_SCLK PAD Driver select" "0,1,2,3" bitfld.long 0x80 1. "PS,OSPI2_SCLK PAD Pull select" "0,1" bitfld.long 0x80 0. "PE,OSPI2_SCLK PAD Pull enable" "0,1" line.long 0x84 "IO_PAD_CONFIG_OSPI2_SS0,PAD OSPI2_SS0 config register" bitfld.long 0x84 16. "POE,OSPI2_SS0 PAD Parametric output enable" "0,1" bitfld.long 0x84 12. "IS,OSPI2_SS0 PAD Input select" "0,1" bitfld.long 0x84 8. "SR,OSPI2_SS0 PAD Slew rate" "0,1" newline bitfld.long 0x84 4.--5. "DS,OSPI2_SS0 PAD Driver select" "0,1,2,3" bitfld.long 0x84 1. "PS,OSPI2_SS0 PAD Pull select" "0,1" bitfld.long 0x84 0. "PE,OSPI2_SS0 PAD Pull enable" "0,1" line.long 0x88 "IO_PAD_CONFIG_OSPI2_DATA0,PAD OSPI2_DATA0 config register" bitfld.long 0x88 16. "POE,OSPI2_DATA0 PAD Parametric output enable" "0,1" bitfld.long 0x88 12. "IS,OSPI2_DATA0 PAD Input select" "0,1" bitfld.long 0x88 8. "SR,OSPI2_DATA0 PAD Slew rate" "0,1" newline bitfld.long 0x88 4.--5. "DS,OSPI2_DATA0 PAD Driver select" "0,1,2,3" bitfld.long 0x88 1. "PS,OSPI2_DATA0 PAD Pull select" "0,1" bitfld.long 0x88 0. "PE,OSPI2_DATA0 PAD Pull enable" "0,1" line.long 0x8C "IO_PAD_CONFIG_OSPI2_DATA1,PAD OSPI2_DATA1 config register" bitfld.long 0x8C 16. "POE,OSPI2_DATA1 PAD Parametric output enable" "0,1" bitfld.long 0x8C 12. "IS,OSPI2_DATA1 PAD Input select" "0,1" bitfld.long 0x8C 8. "SR,OSPI2_DATA1 PAD Slew rate" "0,1" newline bitfld.long 0x8C 4.--5. "DS,OSPI2_DATA1 PAD Driver select" "0,1,2,3" bitfld.long 0x8C 1. "PS,OSPI2_DATA1 PAD Pull select" "0,1" bitfld.long 0x8C 0. "PE,OSPI2_DATA1 PAD Pull enable" "0,1" line.long 0x90 "IO_PAD_CONFIG_OSPI2_DATA2,PAD OSPI2_DATA2 config register" bitfld.long 0x90 16. "POE,OSPI2_DATA2 PAD Parametric output enable" "0,1" bitfld.long 0x90 12. "IS,OSPI2_DATA2 PAD Input select" "0,1" bitfld.long 0x90 8. "SR,OSPI2_DATA2 PAD Slew rate" "0,1" newline bitfld.long 0x90 4.--5. "DS,OSPI2_DATA2 PAD Driver select" "0,1,2,3" bitfld.long 0x90 1. "PS,OSPI2_DATA2 PAD Pull select" "0,1" bitfld.long 0x90 0. "PE,OSPI2_DATA2 PAD Pull enable" "0,1" line.long 0x94 "IO_PAD_CONFIG_OSPI2_DATA3,PAD OSPI2_DATA3 config register" bitfld.long 0x94 16. "POE,OSPI2_DATA3 PAD Parametric output enable" "0,1" bitfld.long 0x94 12. "IS,OSPI2_DATA3 PAD Input select" "0,1" bitfld.long 0x94 8. "SR,OSPI2_DATA3 PAD Slew rate" "0,1" newline bitfld.long 0x94 4.--5. "DS,OSPI2_DATA3 PAD Driver select" "0,1,2,3" bitfld.long 0x94 1. "PS,OSPI2_DATA3 PAD Pull select" "0,1" bitfld.long 0x94 0. "PE,OSPI2_DATA3 PAD Pull enable" "0,1" line.long 0x98 "IO_PAD_CONFIG_OSPI2_DATA4,PAD OSPI2_DATA4 config register" bitfld.long 0x98 16. "POE,OSPI2_DATA4 PAD Parametric output enable" "0,1" bitfld.long 0x98 12. "IS,OSPI2_DATA4 PAD Input select" "0,1" bitfld.long 0x98 8. "SR,OSPI2_DATA4 PAD Slew rate" "0,1" newline bitfld.long 0x98 4.--5. "DS,OSPI2_DATA4 PAD Driver select" "0,1,2,3" bitfld.long 0x98 1. "PS,OSPI2_DATA4 PAD Pull select" "0,1" bitfld.long 0x98 0. "PE,OSPI2_DATA4 PAD Pull enable" "0,1" line.long 0x9C "IO_PAD_CONFIG_OSPI2_DATA5,PAD OSPI2_DATA5 config register" bitfld.long 0x9C 16. "POE,OSPI2_DATA5 PAD Parametric output enable" "0,1" bitfld.long 0x9C 12. "IS,OSPI2_DATA5 PAD Input select" "0,1" bitfld.long 0x9C 8. "SR,OSPI2_DATA5 PAD Slew rate" "0,1" newline bitfld.long 0x9C 4.--5. "DS,OSPI2_DATA5 PAD Driver select" "0,1,2,3" bitfld.long 0x9C 1. "PS,OSPI2_DATA5 PAD Pull select" "0,1" bitfld.long 0x9C 0. "PE,OSPI2_DATA5 PAD Pull enable" "0,1" line.long 0xA0 "IO_PAD_CONFIG_OSPI2_DATA6,PAD OSPI2_DATA6 config register" bitfld.long 0xA0 16. "POE,OSPI2_DATA6 PAD Parametric output enable" "0,1" bitfld.long 0xA0 12. "IS,OSPI2_DATA6 PAD Input select" "0,1" bitfld.long 0xA0 8. "SR,OSPI2_DATA6 PAD Slew rate" "0,1" newline bitfld.long 0xA0 4.--5. "DS,OSPI2_DATA6 PAD Driver select" "0,1,2,3" bitfld.long 0xA0 1. "PS,OSPI2_DATA6 PAD Pull select" "0,1" bitfld.long 0xA0 0. "PE,OSPI2_DATA6 PAD Pull enable" "0,1" line.long 0xA4 "IO_PAD_CONFIG_OSPI2_DATA7,PAD OSPI2_DATA7 config register" bitfld.long 0xA4 16. "POE,OSPI2_DATA7 PAD Parametric output enable" "0,1" bitfld.long 0xA4 12. "IS,OSPI2_DATA7 PAD Input select" "0,1" bitfld.long 0xA4 8. "SR,OSPI2_DATA7 PAD Slew rate" "0,1" newline bitfld.long 0xA4 4.--5. "DS,OSPI2_DATA7 PAD Driver select" "0,1,2,3" bitfld.long 0xA4 1. "PS,OSPI2_DATA7 PAD Pull select" "0,1" bitfld.long 0xA4 0. "PE,OSPI2_DATA7 PAD Pull enable" "0,1" line.long 0xA8 "IO_PAD_CONFIG_OSPI2_DQS,PAD OSPI2_DQS config register" bitfld.long 0xA8 16. "POE,OSPI2_DQS PAD Parametric output enable" "0,1" bitfld.long 0xA8 12. "IS,OSPI2_DQS PAD Input select" "0,1" bitfld.long 0xA8 8. "SR,OSPI2_DQS PAD Slew rate" "0,1" newline bitfld.long 0xA8 4.--5. "DS,OSPI2_DQS PAD Driver select" "0,1,2,3" bitfld.long 0xA8 1. "PS,OSPI2_DQS PAD Pull select" "0,1" bitfld.long 0xA8 0. "PE,OSPI2_DQS PAD Pull enable" "0,1" line.long 0xAC "IO_PAD_CONFIG_OSPI2_SS1,PAD OSPI2_SS1 config register" bitfld.long 0xAC 16. "POE,OSPI2_SS1 PAD Parametric output enable" "0,1" bitfld.long 0xAC 12. "IS,OSPI2_SS1 PAD Input select" "0,1" bitfld.long 0xAC 8. "SR,OSPI2_SS1 PAD Slew rate" "0,1" newline bitfld.long 0xAC 4.--5. "DS,OSPI2_SS1 PAD Driver select" "0,1,2,3" bitfld.long 0xAC 1. "PS,OSPI2_SS1 PAD Pull select" "0,1" bitfld.long 0xAC 0. "PE,OSPI2_SS1 PAD Pull enable" "0,1" line.long 0xB0 "IO_PAD_CONFIG_RGMII2_TXC,PAD RGMII2_TXC config register" bitfld.long 0xB0 16. "POE,RGMII2_TXC PAD Parametric output enable" "0,1" bitfld.long 0xB0 12. "IS,RGMII2_TXC PAD Input select" "0,1" bitfld.long 0xB0 8. "SR,RGMII2_TXC PAD Slew rate" "0,1" newline bitfld.long 0xB0 4.--5. "DS,RGMII2_TXC PAD Driver select" "0,1,2,3" bitfld.long 0xB0 1. "PS,RGMII2_TXC PAD Pull select" "0,1" bitfld.long 0xB0 0. "PE,RGMII2_TXC PAD Pull enable" "0,1" line.long 0xB4 "IO_PAD_CONFIG_RGMII2_TXD0,PAD RGMII2_TXD0 config register" bitfld.long 0xB4 16. "POE,RGMII2_TXD0 PAD Parametric output enable" "0,1" bitfld.long 0xB4 12. "IS,RGMII2_TXD0 PAD Input select" "0,1" bitfld.long 0xB4 8. "SR,RGMII2_TXD0 PAD Slew rate" "0,1" newline bitfld.long 0xB4 4.--5. "DS,RGMII2_TXD0 PAD Driver select" "0,1,2,3" bitfld.long 0xB4 1. "PS,RGMII2_TXD0 PAD Pull select" "0,1" bitfld.long 0xB4 0. "PE,RGMII2_TXD0 PAD Pull enable" "0,1" line.long 0xB8 "IO_PAD_CONFIG_RGMII2_TXD1,PAD RGMII2_TXD1 config register" bitfld.long 0xB8 16. "POE,RGMII2_TXD1 PAD Parametric output enable" "0,1" bitfld.long 0xB8 12. "IS,RGMII2_TXD1 PAD Input select" "0,1" bitfld.long 0xB8 8. "SR,RGMII2_TXD1 PAD Slew rate" "0,1" newline bitfld.long 0xB8 4.--5. "DS,RGMII2_TXD1 PAD Driver select" "0,1,2,3" bitfld.long 0xB8 1. "PS,RGMII2_TXD1 PAD Pull select" "0,1" bitfld.long 0xB8 0. "PE,RGMII2_TXD1 PAD Pull enable" "0,1" line.long 0xBC "IO_PAD_CONFIG_RGMII2_TXD2,PAD RGMII2_TXD2 config register" bitfld.long 0xBC 16. "POE,RGMII2_TXD2 PAD Parametric output enable" "0,1" bitfld.long 0xBC 12. "IS,RGMII2_TXD2 PAD Input select" "0,1" bitfld.long 0xBC 8. "SR,RGMII2_TXD2 PAD Slew rate" "0,1" newline bitfld.long 0xBC 4.--5. "DS,RGMII2_TXD2 PAD Driver select" "0,1,2,3" bitfld.long 0xBC 1. "PS,RGMII2_TXD2 PAD Pull select" "0,1" bitfld.long 0xBC 0. "PE,RGMII2_TXD2 PAD Pull enable" "0,1" line.long 0xC0 "IO_PAD_CONFIG_RGMII2_TXD3,PAD RGMII2_TXD3 config register" bitfld.long 0xC0 16. "POE,RGMII2_TXD3 PAD Parametric output enable" "0,1" bitfld.long 0xC0 12. "IS,RGMII2_TXD3 PAD Input select" "0,1" bitfld.long 0xC0 8. "SR,RGMII2_TXD3 PAD Slew rate" "0,1" newline bitfld.long 0xC0 4.--5. "DS,RGMII2_TXD3 PAD Driver select" "0,1,2,3" bitfld.long 0xC0 1. "PS,RGMII2_TXD3 PAD Pull select" "0,1" bitfld.long 0xC0 0. "PE,RGMII2_TXD3 PAD Pull enable" "0,1" line.long 0xC4 "IO_PAD_CONFIG_RGMII2_TX_CTL,PAD RGMII2_TX_CTL config register" bitfld.long 0xC4 16. "POE,RGMII2_TX_CTL PAD Parametric output enable" "0,1" bitfld.long 0xC4 12. "IS,RGMII2_TX_CTL PAD Input select" "0,1" bitfld.long 0xC4 8. "SR,RGMII2_TX_CTL PAD Slew rate" "0,1" newline bitfld.long 0xC4 4.--5. "DS,RGMII2_TX_CTL PAD Driver select" "0,1,2,3" bitfld.long 0xC4 1. "PS,RGMII2_TX_CTL PAD Pull select" "0,1" bitfld.long 0xC4 0. "PE,RGMII2_TX_CTL PAD Pull enable" "0,1" line.long 0xC8 "IO_PAD_CONFIG_RGMII2_RXC,PAD RGMII2_RXC config register" bitfld.long 0xC8 16. "POE,RGMII2_RXC PAD Parametric output enable" "0,1" bitfld.long 0xC8 12. "IS,RGMII2_RXC PAD Input select" "0,1" bitfld.long 0xC8 8. "SR,RGMII2_RXC PAD Slew rate" "0,1" newline bitfld.long 0xC8 4.--5. "DS,RGMII2_RXC PAD Driver select" "0,1,2,3" bitfld.long 0xC8 1. "PS,RGMII2_RXC PAD Pull select" "0,1" bitfld.long 0xC8 0. "PE,RGMII2_RXC PAD Pull enable" "0,1" line.long 0xCC "IO_PAD_CONFIG_RGMII2_RXD0,PAD RGMII2_RXD0 config register" bitfld.long 0xCC 16. "POE,RGMII2_RXD0 PAD Parametric output enable" "0,1" bitfld.long 0xCC 12. "IS,RGMII2_RXD0 PAD Input select" "0,1" bitfld.long 0xCC 8. "SR,RGMII2_RXD0 PAD Slew rate" "0,1" newline bitfld.long 0xCC 4.--5. "DS,RGMII2_RXD0 PAD Driver select" "0,1,2,3" bitfld.long 0xCC 1. "PS,RGMII2_RXD0 PAD Pull select" "0,1" bitfld.long 0xCC 0. "PE,RGMII2_RXD0 PAD Pull enable" "0,1" line.long 0xD0 "IO_PAD_CONFIG_RGMII2_RXD1,PAD RGMII2_RXD1 config register" bitfld.long 0xD0 16. "POE,RGMII2_RXD1 PAD Parametric output enable" "0,1" bitfld.long 0xD0 12. "IS,RGMII2_RXD1 PAD Input select" "0,1" bitfld.long 0xD0 8. "SR,RGMII2_RXD1 PAD Slew rate" "0,1" newline bitfld.long 0xD0 4.--5. "DS,RGMII2_RXD1 PAD Driver select" "0,1,2,3" bitfld.long 0xD0 1. "PS,RGMII2_RXD1 PAD Pull select" "0,1" bitfld.long 0xD0 0. "PE,RGMII2_RXD1 PAD Pull enable" "0,1" line.long 0xD4 "IO_PAD_CONFIG_RGMII2_RXD2,PAD RGMII2_RXD2 config register" bitfld.long 0xD4 16. "POE,RGMII2_RXD2 PAD Parametric output enable" "0,1" bitfld.long 0xD4 12. "IS,RGMII2_RXD2 PAD Input select" "0,1" bitfld.long 0xD4 8. "SR,RGMII2_RXD2 PAD Slew rate" "0,1" newline bitfld.long 0xD4 4.--5. "DS,RGMII2_RXD2 PAD Driver select" "0,1,2,3" bitfld.long 0xD4 1. "PS,RGMII2_RXD2 PAD Pull select" "0,1" bitfld.long 0xD4 0. "PE,RGMII2_RXD2 PAD Pull enable" "0,1" line.long 0xD8 "IO_PAD_CONFIG_RGMII2_RXD3,PAD RGMII2_RXD3 config register" bitfld.long 0xD8 16. "POE,RGMII2_RXD3 PAD Parametric output enable" "0,1" bitfld.long 0xD8 12. "IS,RGMII2_RXD3 PAD Input select" "0,1" bitfld.long 0xD8 8. "SR,RGMII2_RXD3 PAD Slew rate" "0,1" newline bitfld.long 0xD8 4.--5. "DS,RGMII2_RXD3 PAD Driver select" "0,1,2,3" bitfld.long 0xD8 1. "PS,RGMII2_RXD3 PAD Pull select" "0,1" bitfld.long 0xD8 0. "PE,RGMII2_RXD3 PAD Pull enable" "0,1" line.long 0xDC "IO_PAD_CONFIG_RGMII2_RX_CTL,PAD RGMII2_RX_CTL config register" bitfld.long 0xDC 16. "POE,RGMII2_RX_CTL PAD Parametric output enable" "0,1" bitfld.long 0xDC 12. "IS,RGMII2_RX_CTL PAD Input select" "0,1" bitfld.long 0xDC 8. "SR,RGMII2_RX_CTL PAD Slew rate" "0,1" newline bitfld.long 0xDC 4.--5. "DS,RGMII2_RX_CTL PAD Driver select" "0,1,2,3" bitfld.long 0xDC 1. "PS,RGMII2_RX_CTL PAD Pull select" "0,1" bitfld.long 0xDC 0. "PE,RGMII2_RX_CTL PAD Pull enable" "0,1" line.long 0xE0 "IO_PAD_CONFIG_I2S_SC3_SCK,PAD I2S_SC3_SCK config register" bitfld.long 0xE0 16. "POE,I2S_SC3_SCK PAD Parametric output enable" "0,1" bitfld.long 0xE0 12. "IS,I2S_SC3_SCK PAD Input select" "0,1" bitfld.long 0xE0 8. "SR,I2S_SC3_SCK PAD Slew rate" "0,1" newline bitfld.long 0xE0 4.--5. "DS,I2S_SC3_SCK PAD Driver select" "0,1,2,3" bitfld.long 0xE0 1. "PS,I2S_SC3_SCK PAD Pull select" "0,1" bitfld.long 0xE0 0. "PE,I2S_SC3_SCK PAD Pull enable" "0,1" line.long 0xE4 "IO_PAD_CONFIG_I2S_SC3_WS,PAD I2S_SC3_WS config register" bitfld.long 0xE4 16. "POE,I2S_SC3_WS PAD Parametric output enable" "0,1" bitfld.long 0xE4 12. "IS,I2S_SC3_WS PAD Input select" "0,1" bitfld.long 0xE4 8. "SR,I2S_SC3_WS PAD Slew rate" "0,1" newline bitfld.long 0xE4 4.--5. "DS,I2S_SC3_WS PAD Driver select" "0,1,2,3" bitfld.long 0xE4 1. "PS,I2S_SC3_WS PAD Pull select" "0,1" bitfld.long 0xE4 0. "PE,I2S_SC3_WS PAD Pull enable" "0,1" line.long 0xE8 "IO_PAD_CONFIG_I2S_SC3_SD,PAD I2S_SC3_SD config register" bitfld.long 0xE8 16. "POE,I2S_SC3_SD PAD Parametric output enable" "0,1" bitfld.long 0xE8 12. "IS,I2S_SC3_SD PAD Input select" "0,1" bitfld.long 0xE8 8. "SR,I2S_SC3_SD PAD Slew rate" "0,1" newline bitfld.long 0xE8 4.--5. "DS,I2S_SC3_SD PAD Driver select" "0,1,2,3" bitfld.long 0xE8 1. "PS,I2S_SC3_SD PAD Pull select" "0,1" bitfld.long 0xE8 0. "PE,I2S_SC3_SD PAD Pull enable" "0,1" line.long 0xEC "IO_PAD_CONFIG_I2S_SC4_SCK,PAD I2S_SC4_SCK config register" bitfld.long 0xEC 16. "POE,I2S_SC4_SCK PAD Parametric output enable" "0,1" bitfld.long 0xEC 12. "IS,I2S_SC4_SCK PAD Input select" "0,1" bitfld.long 0xEC 8. "SR,I2S_SC4_SCK PAD Slew rate" "0,1" newline bitfld.long 0xEC 4.--5. "DS,I2S_SC4_SCK PAD Driver select" "0,1,2,3" bitfld.long 0xEC 1. "PS,I2S_SC4_SCK PAD Pull select" "0,1" bitfld.long 0xEC 0. "PE,I2S_SC4_SCK PAD Pull enable" "0,1" line.long 0xF0 "IO_PAD_CONFIG_I2S_SC4_WS,PAD I2S_SC4_WS config register" bitfld.long 0xF0 16. "POE,I2S_SC4_WS PAD Parametric output enable" "0,1" bitfld.long 0xF0 12. "IS,I2S_SC4_WS PAD Input select" "0,1" bitfld.long 0xF0 8. "SR,I2S_SC4_WS PAD Slew rate" "0,1" newline bitfld.long 0xF0 4.--5. "DS,I2S_SC4_WS PAD Driver select" "0,1,2,3" bitfld.long 0xF0 1. "PS,I2S_SC4_WS PAD Pull select" "0,1" bitfld.long 0xF0 0. "PE,I2S_SC4_WS PAD Pull enable" "0,1" line.long 0xF4 "IO_PAD_CONFIG_I2S_SC4_SD,PAD I2S_SC4_SD config register" bitfld.long 0xF4 16. "POE,I2S_SC4_SD PAD Parametric output enable" "0,1" bitfld.long 0xF4 12. "IS,I2S_SC4_SD PAD Input select" "0,1" bitfld.long 0xF4 8. "SR,I2S_SC4_SD PAD Slew rate" "0,1" newline bitfld.long 0xF4 4.--5. "DS,I2S_SC4_SD PAD Driver select" "0,1,2,3" bitfld.long 0xF4 1. "PS,I2S_SC4_SD PAD Pull select" "0,1" bitfld.long 0xF4 0. "PE,I2S_SC4_SD PAD Pull enable" "0,1" line.long 0xF8 "IO_PAD_CONFIG_I2S_SC5_SCK,PAD I2S_SC5_SCK config register" bitfld.long 0xF8 16. "POE,I2S_SC5_SCK PAD Parametric output enable" "0,1" bitfld.long 0xF8 12. "IS,I2S_SC5_SCK PAD Input select" "0,1" bitfld.long 0xF8 8. "SR,I2S_SC5_SCK PAD Slew rate" "0,1" newline bitfld.long 0xF8 4.--5. "DS,I2S_SC5_SCK PAD Driver select" "0,1,2,3" bitfld.long 0xF8 1. "PS,I2S_SC5_SCK PAD Pull select" "0,1" bitfld.long 0xF8 0. "PE,I2S_SC5_SCK PAD Pull enable" "0,1" line.long 0xFC "IO_PAD_CONFIG_I2S_SC5_WS,PAD I2S_SC5_WS config register" bitfld.long 0xFC 16. "POE,I2S_SC5_WS PAD Parametric output enable" "0,1" bitfld.long 0xFC 12. "IS,I2S_SC5_WS PAD Input select" "0,1" bitfld.long 0xFC 8. "SR,I2S_SC5_WS PAD Slew rate" "0,1" newline bitfld.long 0xFC 4.--5. "DS,I2S_SC5_WS PAD Driver select" "0,1,2,3" bitfld.long 0xFC 1. "PS,I2S_SC5_WS PAD Pull select" "0,1" bitfld.long 0xFC 0. "PE,I2S_SC5_WS PAD Pull enable" "0,1" line.long 0x100 "IO_PAD_CONFIG_I2S_SC5_SD,PAD I2S_SC5_SD config register" bitfld.long 0x100 16. "POE,I2S_SC5_SD PAD Parametric output enable" "0,1" bitfld.long 0x100 12. "IS,I2S_SC5_SD PAD Input select" "0,1" bitfld.long 0x100 8. "SR,I2S_SC5_SD PAD Slew rate" "0,1" newline bitfld.long 0x100 4.--5. "DS,I2S_SC5_SD PAD Driver select" "0,1,2,3" bitfld.long 0x100 1. "PS,I2S_SC5_SD PAD Pull select" "0,1" bitfld.long 0x100 0. "PE,I2S_SC5_SD PAD Pull enable" "0,1" line.long 0x104 "IO_PAD_CONFIG_I2S_SC6_SCK,PAD I2S_SC6_SCK config register" bitfld.long 0x104 16. "POE,I2S_SC6_SCK PAD Parametric output enable" "0,1" bitfld.long 0x104 12. "IS,I2S_SC6_SCK PAD Input select" "0,1" bitfld.long 0x104 8. "SR,I2S_SC6_SCK PAD Slew rate" "0,1" newline bitfld.long 0x104 4.--5. "DS,I2S_SC6_SCK PAD Driver select" "0,1,2,3" bitfld.long 0x104 1. "PS,I2S_SC6_SCK PAD Pull select" "0,1" bitfld.long 0x104 0. "PE,I2S_SC6_SCK PAD Pull enable" "0,1" line.long 0x108 "IO_PAD_CONFIG_I2S_SC6_WS,PAD I2S_SC6_WS config register" bitfld.long 0x108 16. "POE,I2S_SC6_WS PAD Parametric output enable" "0,1" bitfld.long 0x108 12. "IS,I2S_SC6_WS PAD Input select" "0,1" bitfld.long 0x108 8. "SR,I2S_SC6_WS PAD Slew rate" "0,1" newline bitfld.long 0x108 4.--5. "DS,I2S_SC6_WS PAD Driver select" "0,1,2,3" bitfld.long 0x108 1. "PS,I2S_SC6_WS PAD Pull select" "0,1" bitfld.long 0x108 0. "PE,I2S_SC6_WS PAD Pull enable" "0,1" line.long 0x10C "IO_PAD_CONFIG_I2S_SC6_SD,PAD I2S_SC6_SD config register" bitfld.long 0x10C 16. "POE,I2S_SC6_SD PAD Parametric output enable" "0,1" bitfld.long 0x10C 12. "IS,I2S_SC6_SD PAD Input select" "0,1" bitfld.long 0x10C 8. "SR,I2S_SC6_SD PAD Slew rate" "0,1" newline bitfld.long 0x10C 4.--5. "DS,I2S_SC6_SD PAD Driver select" "0,1,2,3" bitfld.long 0x10C 1. "PS,I2S_SC6_SD PAD Pull select" "0,1" bitfld.long 0x10C 0. "PE,I2S_SC6_SD PAD Pull enable" "0,1" line.long 0x110 "IO_PAD_CONFIG_I2S_SC7_SCK,PAD I2S_SC7_SCK config register" bitfld.long 0x110 16. "POE,I2S_SC7_SCK PAD Parametric output enable" "0,1" bitfld.long 0x110 12. "IS,I2S_SC7_SCK PAD Input select" "0,1" bitfld.long 0x110 8. "SR,I2S_SC7_SCK PAD Slew rate" "0,1" newline bitfld.long 0x110 4.--5. "DS,I2S_SC7_SCK PAD Driver select" "0,1,2,3" bitfld.long 0x110 1. "PS,I2S_SC7_SCK PAD Pull select" "0,1" bitfld.long 0x110 0. "PE,I2S_SC7_SCK PAD Pull enable" "0,1" line.long 0x114 "IO_PAD_CONFIG_I2S_SC7_WS,PAD I2S_SC7_WS config register" bitfld.long 0x114 16. "POE,I2S_SC7_WS PAD Parametric output enable" "0,1" bitfld.long 0x114 12. "IS,I2S_SC7_WS PAD Input select" "0,1" bitfld.long 0x114 8. "SR,I2S_SC7_WS PAD Slew rate" "0,1" newline bitfld.long 0x114 4.--5. "DS,I2S_SC7_WS PAD Driver select" "0,1,2,3" bitfld.long 0x114 1. "PS,I2S_SC7_WS PAD Pull select" "0,1" bitfld.long 0x114 0. "PE,I2S_SC7_WS PAD Pull enable" "0,1" line.long 0x118 "IO_PAD_CONFIG_I2S_SC7_SD,PAD I2S_SC7_SD config register" bitfld.long 0x118 16. "POE,I2S_SC7_SD PAD Parametric output enable" "0,1" bitfld.long 0x118 12. "IS,I2S_SC7_SD PAD Input select" "0,1" bitfld.long 0x118 8. "SR,I2S_SC7_SD PAD Slew rate" "0,1" newline bitfld.long 0x118 4.--5. "DS,I2S_SC7_SD PAD Driver select" "0,1,2,3" bitfld.long 0x118 1. "PS,I2S_SC7_SD PAD Pull select" "0,1" bitfld.long 0x118 0. "PE,I2S_SC7_SD PAD Pull enable" "0,1" line.long 0x11C "IO_PAD_CONFIG_I2S_SC8_SCK,PAD I2S_SC8_SCK config register" bitfld.long 0x11C 16. "POE,I2S_SC8_SCK PAD Parametric output enable" "0,1" bitfld.long 0x11C 12. "IS,I2S_SC8_SCK PAD Input select" "0,1" bitfld.long 0x11C 8. "SR,I2S_SC8_SCK PAD Slew rate" "0,1" newline bitfld.long 0x11C 4.--5. "DS,I2S_SC8_SCK PAD Driver select" "0,1,2,3" bitfld.long 0x11C 1. "PS,I2S_SC8_SCK PAD Pull select" "0,1" bitfld.long 0x11C 0. "PE,I2S_SC8_SCK PAD Pull enable" "0,1" line.long 0x120 "IO_PAD_CONFIG_I2S_SC8_WS,PAD I2S_SC8_WS config register" bitfld.long 0x120 16. "POE,I2S_SC8_WS PAD Parametric output enable" "0,1" bitfld.long 0x120 12. "IS,I2S_SC8_WS PAD Input select" "0,1" bitfld.long 0x120 8. "SR,I2S_SC8_WS PAD Slew rate" "0,1" newline bitfld.long 0x120 4.--5. "DS,I2S_SC8_WS PAD Driver select" "0,1,2,3" bitfld.long 0x120 1. "PS,I2S_SC8_WS PAD Pull select" "0,1" bitfld.long 0x120 0. "PE,I2S_SC8_WS PAD Pull enable" "0,1" line.long 0x124 "IO_PAD_CONFIG_I2S_SC8_SD,PAD I2S_SC8_SD config register" bitfld.long 0x124 16. "POE,I2S_SC8_SD PAD Parametric output enable" "0,1" bitfld.long 0x124 12. "IS,I2S_SC8_SD PAD Input select" "0,1" bitfld.long 0x124 8. "SR,I2S_SC8_SD PAD Slew rate" "0,1" newline bitfld.long 0x124 4.--5. "DS,I2S_SC8_SD PAD Driver select" "0,1,2,3" bitfld.long 0x124 1. "PS,I2S_SC8_SD PAD Pull select" "0,1" bitfld.long 0x124 0. "PE,I2S_SC8_SD PAD Pull enable" "0,1" line.long 0x128 "IO_PAD_CONFIG_I2S_MC_SCK,PAD I2S_MC_SCK config register" bitfld.long 0x128 16. "POE,I2S_MC_SCK PAD Parametric output enable" "0,1" bitfld.long 0x128 12. "IS,I2S_MC_SCK PAD Input select" "0,1" bitfld.long 0x128 8. "SR,I2S_MC_SCK PAD Slew rate" "0,1" newline bitfld.long 0x128 4.--5. "DS,I2S_MC_SCK PAD Driver select" "0,1,2,3" bitfld.long 0x128 1. "PS,I2S_MC_SCK PAD Pull select" "0,1" bitfld.long 0x128 0. "PE,I2S_MC_SCK PAD Pull enable" "0,1" line.long 0x12C "IO_PAD_CONFIG_I2S_MC_WS,PAD I2S_MC_WS config register" bitfld.long 0x12C 16. "POE,I2S_MC_WS PAD Parametric output enable" "0,1" bitfld.long 0x12C 12. "IS,I2S_MC_WS PAD Input select" "0,1" bitfld.long 0x12C 8. "SR,I2S_MC_WS PAD Slew rate" "0,1" newline bitfld.long 0x12C 4.--5. "DS,I2S_MC_WS PAD Driver select" "0,1,2,3" bitfld.long 0x12C 1. "PS,I2S_MC_WS PAD Pull select" "0,1" bitfld.long 0x12C 0. "PE,I2S_MC_WS PAD Pull enable" "0,1" line.long 0x130 "IO_PAD_CONFIG_I2S_MC_SD0,PAD I2S_MC_SD0 config register" bitfld.long 0x130 16. "POE,I2S_MC_SD0 PAD Parametric output enable" "0,1" bitfld.long 0x130 12. "IS,I2S_MC_SD0 PAD Input select" "0,1" bitfld.long 0x130 8. "SR,I2S_MC_SD0 PAD Slew rate" "0,1" newline bitfld.long 0x130 4.--5. "DS,I2S_MC_SD0 PAD Driver select" "0,1,2,3" bitfld.long 0x130 1. "PS,I2S_MC_SD0 PAD Pull select" "0,1" bitfld.long 0x130 0. "PE,I2S_MC_SD0 PAD Pull enable" "0,1" line.long 0x134 "IO_PAD_CONFIG_I2S_MC_SD1,PAD I2S_MC_SD1 config register" bitfld.long 0x134 16. "POE,I2S_MC_SD1 PAD Parametric output enable" "0,1" bitfld.long 0x134 12. "IS,I2S_MC_SD1 PAD Input select" "0,1" bitfld.long 0x134 8. "SR,I2S_MC_SD1 PAD Slew rate" "0,1" newline bitfld.long 0x134 4.--5. "DS,I2S_MC_SD1 PAD Driver select" "0,1,2,3" bitfld.long 0x134 1. "PS,I2S_MC_SD1 PAD Pull select" "0,1" bitfld.long 0x134 0. "PE,I2S_MC_SD1 PAD Pull enable" "0,1" line.long 0x138 "IO_PAD_CONFIG_I2S_MC_SD2,PAD I2S_MC_SD2 config register" bitfld.long 0x138 16. "POE,I2S_MC_SD2 PAD Parametric output enable" "0,1" bitfld.long 0x138 12. "IS,I2S_MC_SD2 PAD Input select" "0,1" bitfld.long 0x138 8. "SR,I2S_MC_SD2 PAD Slew rate" "0,1" newline bitfld.long 0x138 4.--5. "DS,I2S_MC_SD2 PAD Driver select" "0,1,2,3" bitfld.long 0x138 1. "PS,I2S_MC_SD2 PAD Pull select" "0,1" bitfld.long 0x138 0. "PE,I2S_MC_SD2 PAD Pull enable" "0,1" line.long 0x13C "IO_PAD_CONFIG_I2S_MC_SD3,PAD I2S_MC_SD3 config register" bitfld.long 0x13C 16. "POE,I2S_MC_SD3 PAD Parametric output enable" "0,1" bitfld.long 0x13C 12. "IS,I2S_MC_SD3 PAD Input select" "0,1" bitfld.long 0x13C 8. "SR,I2S_MC_SD3 PAD Slew rate" "0,1" newline bitfld.long 0x13C 4.--5. "DS,I2S_MC_SD3 PAD Driver select" "0,1,2,3" bitfld.long 0x13C 1. "PS,I2S_MC_SD3 PAD Pull select" "0,1" bitfld.long 0x13C 0. "PE,I2S_MC_SD3 PAD Pull enable" "0,1" line.long 0x140 "IO_PAD_CONFIG_I2S_MC_SD4,PAD I2S_MC_SD4 config register" bitfld.long 0x140 16. "POE,I2S_MC_SD4 PAD Parametric output enable" "0,1" bitfld.long 0x140 12. "IS,I2S_MC_SD4 PAD Input select" "0,1" bitfld.long 0x140 8. "SR,I2S_MC_SD4 PAD Slew rate" "0,1" newline bitfld.long 0x140 4.--5. "DS,I2S_MC_SD4 PAD Driver select" "0,1,2,3" bitfld.long 0x140 1. "PS,I2S_MC_SD4 PAD Pull select" "0,1" bitfld.long 0x140 0. "PE,I2S_MC_SD4 PAD Pull enable" "0,1" line.long 0x144 "IO_PAD_CONFIG_I2S_MC_SD5,PAD I2S_MC_SD5 config register" bitfld.long 0x144 16. "POE,I2S_MC_SD5 PAD Parametric output enable" "0,1" bitfld.long 0x144 12. "IS,I2S_MC_SD5 PAD Input select" "0,1" bitfld.long 0x144 8. "SR,I2S_MC_SD5 PAD Slew rate" "0,1" newline bitfld.long 0x144 4.--5. "DS,I2S_MC_SD5 PAD Driver select" "0,1,2,3" bitfld.long 0x144 1. "PS,I2S_MC_SD5 PAD Pull select" "0,1" bitfld.long 0x144 0. "PE,I2S_MC_SD5 PAD Pull enable" "0,1" line.long 0x148 "IO_PAD_CONFIG_I2S_MC_SD6,PAD I2S_MC_SD6 config register" bitfld.long 0x148 16. "POE,I2S_MC_SD6 PAD Parametric output enable" "0,1" bitfld.long 0x148 12. "IS,I2S_MC_SD6 PAD Input select" "0,1" bitfld.long 0x148 8. "SR,I2S_MC_SD6 PAD Slew rate" "0,1" newline bitfld.long 0x148 4.--5. "DS,I2S_MC_SD6 PAD Driver select" "0,1,2,3" bitfld.long 0x148 1. "PS,I2S_MC_SD6 PAD Pull select" "0,1" bitfld.long 0x148 0. "PE,I2S_MC_SD6 PAD Pull enable" "0,1" line.long 0x14C "IO_PAD_CONFIG_I2S_MC_SD7,PAD I2S_MC_SD7 config register" bitfld.long 0x14C 16. "POE,I2S_MC_SD7 PAD Parametric output enable" "0,1" bitfld.long 0x14C 12. "IS,I2S_MC_SD7 PAD Input select" "0,1" bitfld.long 0x14C 8. "SR,I2S_MC_SD7 PAD Slew rate" "0,1" newline bitfld.long 0x14C 4.--5. "DS,I2S_MC_SD7 PAD Driver select" "0,1,2,3" bitfld.long 0x14C 1. "PS,I2S_MC_SD7 PAD Pull select" "0,1" bitfld.long 0x14C 0. "PE,I2S_MC_SD7 PAD Pull enable" "0,1" line.long 0x150 "IO_PAD_CONFIG_EMMC1_CLK,PAD EMMC1_CLK config register" hexmask.long.byte 0x150 20.--23. 1. "SP,EMMC1_CLK PAD Drive Strength for P" hexmask.long.byte 0x150 16.--19. 1. "SN,EMMC1_CLK PAD Drive Strength for N" bitfld.long 0x150 12.--14. "RXSEL,EMMC1_CLK PAD Input Select" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x150 8.--11. 1. "TXPREP,EMMC1_CLK PAD Slew-Rate control for P" newline hexmask.long.byte 0x150 4.--7. 1. "TXPREN,EMMC1_CLK PAD Slew-Rate control for N" bitfld.long 0x150 0.--1. "PULL_EN,EMMC1_CLK PAD Pull Enable. 0: OFF; 1: PU; 2: PD; 3: RESERVED." "OFF;,PU;,PD;,RESERVED" line.long 0x154 "IO_PAD_CONFIG_EMMC1_CMD,PAD EMMC1_CMD config register" hexmask.long.byte 0x154 20.--23. 1. "SP,EMMC1_CMD PAD Drive Strength for P" hexmask.long.byte 0x154 16.--19. 1. "SN,EMMC1_CMD PAD Drive Strength for N" bitfld.long 0x154 12.--14. "RXSEL,EMMC1_CMD PAD Input Select" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x154 8.--11. 1. "TXPREP,EMMC1_CMD PAD Slew-Rate control for P" newline hexmask.long.byte 0x154 4.--7. 1. "TXPREN,EMMC1_CMD PAD Slew-Rate control for N" bitfld.long 0x154 0.--1. "PULL_EN,EMMC1_CMD PAD Pull Enable. 0: OFF; 1: PU; 2: PD; 3: RESERVED." "OFF;,PU;,PD;,RESERVED" line.long 0x158 "IO_PAD_CONFIG_EMMC1_DATA0,PAD EMMC1_DATA0 config register" hexmask.long.byte 0x158 20.--23. 1. "SP,EMMC1_DATA0 PAD Drive Strength for P" hexmask.long.byte 0x158 16.--19. 1. "SN,EMMC1_DATA0 PAD Drive Strength for N" bitfld.long 0x158 12.--14. "RXSEL,EMMC1_DATA0 PAD Input Select" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x158 8.--11. 1. "TXPREP,EMMC1_DATA0 PAD Slew-Rate control for P" newline hexmask.long.byte 0x158 4.--7. 1. "TXPREN,EMMC1_DATA0 PAD Slew-Rate control for N" bitfld.long 0x158 0.--1. "PULL_EN,EMMC1_DATA0 PAD Pull Enable. 0: OFF; 1: PU; 2: PD; 3: RESERVED." "OFF;,PU;,PD;,RESERVED" line.long 0x15C "IO_PAD_CONFIG_EMMC1_DATA1,PAD EMMC1_DATA1 config register" hexmask.long.byte 0x15C 20.--23. 1. "SP,EMMC1_DATA1 PAD Drive Strength for P" hexmask.long.byte 0x15C 16.--19. 1. "SN,EMMC1_DATA1 PAD Drive Strength for N" bitfld.long 0x15C 12.--14. "RXSEL,EMMC1_DATA1 PAD Input Select" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x15C 8.--11. 1. "TXPREP,EMMC1_DATA1 PAD Slew-Rate control for P" newline hexmask.long.byte 0x15C 4.--7. 1. "TXPREN,EMMC1_DATA1 PAD Slew-Rate control for N" bitfld.long 0x15C 0.--1. "PULL_EN,EMMC1_DATA1 PAD Pull Enable. 0: OFF; 1: PU; 2: PD; 3: RESERVED." "OFF;,PU;,PD;,RESERVED" line.long 0x160 "IO_PAD_CONFIG_EMMC1_DATA2,PAD EMMC1_DATA2 config register" hexmask.long.byte 0x160 20.--23. 1. "SP,EMMC1_DATA2 PAD Drive Strength for P" hexmask.long.byte 0x160 16.--19. 1. "SN,EMMC1_DATA2 PAD Drive Strength for N" bitfld.long 0x160 12.--14. "RXSEL,EMMC1_DATA2 PAD Input Select" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x160 8.--11. 1. "TXPREP,EMMC1_DATA2 PAD Slew-Rate control for P" newline hexmask.long.byte 0x160 4.--7. 1. "TXPREN,EMMC1_DATA2 PAD Slew-Rate control for N" bitfld.long 0x160 0.--1. "PULL_EN,EMMC1_DATA2 PAD Pull Enable. 0: OFF; 1: PU; 2: PD; 3: RESERVED." "OFF;,PU;,PD;,RESERVED" line.long 0x164 "IO_PAD_CONFIG_EMMC1_DATA3,PAD EMMC1_DATA3 config register" hexmask.long.byte 0x164 20.--23. 1. "SP,EMMC1_DATA3 PAD Drive Strength for P" hexmask.long.byte 0x164 16.--19. 1. "SN,EMMC1_DATA3 PAD Drive Strength for N" bitfld.long 0x164 12.--14. "RXSEL,EMMC1_DATA3 PAD Input Select" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x164 8.--11. 1. "TXPREP,EMMC1_DATA3 PAD Slew-Rate control for P" newline hexmask.long.byte 0x164 4.--7. 1. "TXPREN,EMMC1_DATA3 PAD Slew-Rate control for N" bitfld.long 0x164 0.--1. "PULL_EN,EMMC1_DATA3 PAD Pull Enable. 0: OFF; 1: PU; 2: PD; 3: RESERVED." "OFF;,PU;,PD;,RESERVED" line.long 0x168 "IO_PAD_CONFIG_EMMC1_DATA4,PAD EMMC1_DATA4 config register" hexmask.long.byte 0x168 20.--23. 1. "SP,EMMC1_DATA4 PAD Drive Strength for P" hexmask.long.byte 0x168 16.--19. 1. "SN,EMMC1_DATA4 PAD Drive Strength for N" bitfld.long 0x168 12.--14. "RXSEL,EMMC1_DATA4 PAD Input Select" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x168 8.--11. 1. "TXPREP,EMMC1_DATA4 PAD Slew-Rate control for P" newline hexmask.long.byte 0x168 4.--7. 1. "TXPREN,EMMC1_DATA4 PAD Slew-Rate control for N" bitfld.long 0x168 0.--1. "PULL_EN,EMMC1_DATA4 PAD Pull Enable. 0: OFF; 1: PU; 2: PD; 3: RESERVED." "OFF;,PU;,PD;,RESERVED" line.long 0x16C "IO_PAD_CONFIG_EMMC1_DATA5,PAD EMMC1_DATA5 config register" hexmask.long.byte 0x16C 20.--23. 1. "SP,EMMC1_DATA5 PAD Drive Strength for P" hexmask.long.byte 0x16C 16.--19. 1. "SN,EMMC1_DATA5 PAD Drive Strength for N" bitfld.long 0x16C 12.--14. "RXSEL,EMMC1_DATA5 PAD Input Select" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x16C 8.--11. 1. "TXPREP,EMMC1_DATA5 PAD Slew-Rate control for P" newline hexmask.long.byte 0x16C 4.--7. 1. "TXPREN,EMMC1_DATA5 PAD Slew-Rate control for N" bitfld.long 0x16C 0.--1. "PULL_EN,EMMC1_DATA5 PAD Pull Enable. 0: OFF; 1: PU; 2: PD; 3: RESERVED." "OFF;,PU;,PD;,RESERVED" line.long 0x170 "IO_PAD_CONFIG_EMMC1_DATA6,PAD EMMC1_DATA6 config register" hexmask.long.byte 0x170 20.--23. 1. "SP,EMMC1_DATA6 PAD Drive Strength for P" hexmask.long.byte 0x170 16.--19. 1. "SN,EMMC1_DATA6 PAD Drive Strength for N" bitfld.long 0x170 12.--14. "RXSEL,EMMC1_DATA6 PAD Input Select" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x170 8.--11. 1. "TXPREP,EMMC1_DATA6 PAD Slew-Rate control for P" newline hexmask.long.byte 0x170 4.--7. 1. "TXPREN,EMMC1_DATA6 PAD Slew-Rate control for N" bitfld.long 0x170 0.--1. "PULL_EN,EMMC1_DATA6 PAD Pull Enable. 0: OFF; 1: PU; 2: PD; 3: RESERVED." "OFF;,PU;,PD;,RESERVED" line.long 0x174 "IO_PAD_CONFIG_EMMC1_DATA7,PAD EMMC1_DATA7 config register" hexmask.long.byte 0x174 20.--23. 1. "SP,EMMC1_DATA7 PAD Drive Strength for P" hexmask.long.byte 0x174 16.--19. 1. "SN,EMMC1_DATA7 PAD Drive Strength for N" bitfld.long 0x174 12.--14. "RXSEL,EMMC1_DATA7 PAD Input Select" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x174 8.--11. 1. "TXPREP,EMMC1_DATA7 PAD Slew-Rate control for P" newline hexmask.long.byte 0x174 4.--7. 1. "TXPREN,EMMC1_DATA7 PAD Slew-Rate control for N" bitfld.long 0x174 0.--1. "PULL_EN,EMMC1_DATA7 PAD Pull Enable. 0: OFF; 1: PU; 2: PD; 3: RESERVED." "OFF;,PU;,PD;,RESERVED" line.long 0x178 "IO_PAD_CONFIG_EMMC1_STROBE,PAD EMMC1_STROBE config register" hexmask.long.byte 0x178 20.--23. 1. "SP,EMMC1_STROBE PAD Drive Strength for P" hexmask.long.byte 0x178 16.--19. 1. "SN,EMMC1_STROBE PAD Drive Strength for N" bitfld.long 0x178 12.--14. "RXSEL,EMMC1_STROBE PAD Input Select" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x178 8.--11. 1. "TXPREP,EMMC1_STROBE PAD Slew-Rate control for P" newline hexmask.long.byte 0x178 4.--7. 1. "TXPREN,EMMC1_STROBE PAD Slew-Rate control for N" bitfld.long 0x178 0.--1. "PULL_EN,EMMC1_STROBE PAD Pull Enable. 0: OFF; 1: PU; 2: PD; 3: RESERVED." "OFF;,PU;,PD;,RESERVED" line.long 0x17C "IO_PAD_CONFIG_EMMC1_RESET_N,PAD EMMC1_RESET_N config register" hexmask.long.byte 0x17C 20.--23. 1. "SP,EMMC1_RESET_N PAD Drive Strength for P" hexmask.long.byte 0x17C 16.--19. 1. "SN,EMMC1_RESET_N PAD Drive Strength for N" bitfld.long 0x17C 12.--14. "RXSEL,EMMC1_RESET_N PAD Input Select" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x17C 8.--11. 1. "TXPREP,EMMC1_RESET_N PAD Slew-Rate control for P" newline hexmask.long.byte 0x17C 4.--7. 1. "TXPREN,EMMC1_RESET_N PAD Slew-Rate control for N" bitfld.long 0x17C 0.--1. "PULL_EN,EMMC1_RESET_N PAD Pull Enable. 0: OFF; 1: PU; 2: PD; 3: RESERVED." "OFF;,PU;,PD;,RESERVED" line.long 0x180 "IO_PAD_CONFIG_EMMC2_CLK,PAD EMMC2_CLK config register" hexmask.long.byte 0x180 20.--23. 1. "SP,EMMC2_CLK PAD Drive Strength for P" hexmask.long.byte 0x180 16.--19. 1. "SN,EMMC2_CLK PAD Drive Strength for N" bitfld.long 0x180 12.--14. "RXSEL,EMMC2_CLK PAD Input Select" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x180 8.--11. 1. "TXPREP,EMMC2_CLK PAD Slew-Rate control for P" newline hexmask.long.byte 0x180 4.--7. 1. "TXPREN,EMMC2_CLK PAD Slew-Rate control for N" bitfld.long 0x180 0.--1. "PULL_EN,EMMC2_CLK PAD Pull Enable. 0: OFF; 1: PU; 2: PD; 3: RESERVED." "OFF;,PU;,PD;,RESERVED" line.long 0x184 "IO_PAD_CONFIG_EMMC2_CMD,PAD EMMC2_CMD config register" hexmask.long.byte 0x184 20.--23. 1. "SP,EMMC2_CMD PAD Drive Strength for P" hexmask.long.byte 0x184 16.--19. 1. "SN,EMMC2_CMD PAD Drive Strength for N" bitfld.long 0x184 12.--14. "RXSEL,EMMC2_CMD PAD Input Select" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x184 8.--11. 1. "TXPREP,EMMC2_CMD PAD Slew-Rate control for P" newline hexmask.long.byte 0x184 4.--7. 1. "TXPREN,EMMC2_CMD PAD Slew-Rate control for N" bitfld.long 0x184 0.--1. "PULL_EN,EMMC2_CMD PAD Pull Enable. 0: OFF; 1: PU; 2: PD; 3: RESERVED." "OFF;,PU;,PD;,RESERVED" line.long 0x188 "IO_PAD_CONFIG_EMMC2_DATA0,PAD EMMC2_DATA0 config register" hexmask.long.byte 0x188 20.--23. 1. "SP,EMMC2_DATA0 PAD Drive Strength for P" hexmask.long.byte 0x188 16.--19. 1. "SN,EMMC2_DATA0 PAD Drive Strength for N" bitfld.long 0x188 12.--14. "RXSEL,EMMC2_DATA0 PAD Input Select" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x188 8.--11. 1. "TXPREP,EMMC2_DATA0 PAD Slew-Rate control for P" newline hexmask.long.byte 0x188 4.--7. 1. "TXPREN,EMMC2_DATA0 PAD Slew-Rate control for N" bitfld.long 0x188 0.--1. "PULL_EN,EMMC2_DATA0 PAD Pull Enable. 0: OFF; 1: PU; 2: PD; 3: RESERVED." "OFF;,PU;,PD;,RESERVED" line.long 0x18C "IO_PAD_CONFIG_EMMC2_DATA1,PAD EMMC2_DATA1 config register" hexmask.long.byte 0x18C 20.--23. 1. "SP,EMMC2_DATA1 PAD Drive Strength for P" hexmask.long.byte 0x18C 16.--19. 1. "SN,EMMC2_DATA1 PAD Drive Strength for N" bitfld.long 0x18C 12.--14. "RXSEL,EMMC2_DATA1 PAD Input Select" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x18C 8.--11. 1. "TXPREP,EMMC2_DATA1 PAD Slew-Rate control for P" newline hexmask.long.byte 0x18C 4.--7. 1. "TXPREN,EMMC2_DATA1 PAD Slew-Rate control for N" bitfld.long 0x18C 0.--1. "PULL_EN,EMMC2_DATA1 PAD Pull Enable. 0: OFF; 1: PU; 2: PD; 3: RESERVED." "OFF;,PU;,PD;,RESERVED" line.long 0x190 "IO_PAD_CONFIG_EMMC2_DATA2,PAD EMMC2_DATA2 config register" hexmask.long.byte 0x190 20.--23. 1. "SP,EMMC2_DATA2 PAD Drive Strength for P" hexmask.long.byte 0x190 16.--19. 1. "SN,EMMC2_DATA2 PAD Drive Strength for N" bitfld.long 0x190 12.--14. "RXSEL,EMMC2_DATA2 PAD Input Select" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x190 8.--11. 1. "TXPREP,EMMC2_DATA2 PAD Slew-Rate control for P" newline hexmask.long.byte 0x190 4.--7. 1. "TXPREN,EMMC2_DATA2 PAD Slew-Rate control for N" bitfld.long 0x190 0.--1. "PULL_EN,EMMC2_DATA2 PAD Pull Enable. 0: OFF; 1: PU; 2: PD; 3: RESERVED." "OFF;,PU;,PD;,RESERVED" line.long 0x194 "IO_PAD_CONFIG_EMMC2_DATA3,PAD EMMC2_DATA3 config register" hexmask.long.byte 0x194 20.--23. 1. "SP,EMMC2_DATA3 PAD Drive Strength for P" hexmask.long.byte 0x194 16.--19. 1. "SN,EMMC2_DATA3 PAD Drive Strength for N" bitfld.long 0x194 12.--14. "RXSEL,EMMC2_DATA3 PAD Input Select" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x194 8.--11. 1. "TXPREP,EMMC2_DATA3 PAD Slew-Rate control for P" newline hexmask.long.byte 0x194 4.--7. 1. "TXPREN,EMMC2_DATA3 PAD Slew-Rate control for N" bitfld.long 0x194 0.--1. "PULL_EN,EMMC2_DATA3 PAD Pull Enable. 0: OFF; 1: PU; 2: PD; 3: RESERVED." "OFF;,PU;,PD;,RESERVED" line.long 0x198 "IO_PAD_CONFIG_EMMC2_DATA4,PAD EMMC2_DATA4 config register" hexmask.long.byte 0x198 20.--23. 1. "SP,EMMC2_DATA4 PAD Drive Strength for P" hexmask.long.byte 0x198 16.--19. 1. "SN,EMMC2_DATA4 PAD Drive Strength for N" bitfld.long 0x198 12.--14. "RXSEL,EMMC2_DATA4 PAD Input Select" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x198 8.--11. 1. "TXPREP,EMMC2_DATA4 PAD Slew-Rate control for P" newline hexmask.long.byte 0x198 4.--7. 1. "TXPREN,EMMC2_DATA4 PAD Slew-Rate control for N" bitfld.long 0x198 0.--1. "PULL_EN,EMMC2_DATA4 PAD Pull Enable. 0: OFF; 1: PU; 2: PD; 3: RESERVED." "OFF;,PU;,PD;,RESERVED" line.long 0x19C "IO_PAD_CONFIG_EMMC2_DATA5,PAD EMMC2_DATA5 config register" hexmask.long.byte 0x19C 20.--23. 1. "SP,EMMC2_DATA5 PAD Drive Strength for P" hexmask.long.byte 0x19C 16.--19. 1. "SN,EMMC2_DATA5 PAD Drive Strength for N" bitfld.long 0x19C 12.--14. "RXSEL,EMMC2_DATA5 PAD Input Select" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x19C 8.--11. 1. "TXPREP,EMMC2_DATA5 PAD Slew-Rate control for P" newline hexmask.long.byte 0x19C 4.--7. 1. "TXPREN,EMMC2_DATA5 PAD Slew-Rate control for N" bitfld.long 0x19C 0.--1. "PULL_EN,EMMC2_DATA5 PAD Pull Enable. 0: OFF; 1: PU; 2: PD; 3: RESERVED." "OFF;,PU;,PD;,RESERVED" line.long 0x1A0 "IO_PAD_CONFIG_EMMC2_DATA6,PAD EMMC2_DATA6 config register" hexmask.long.byte 0x1A0 20.--23. 1. "SP,EMMC2_DATA6 PAD Drive Strength for P" hexmask.long.byte 0x1A0 16.--19. 1. "SN,EMMC2_DATA6 PAD Drive Strength for N" bitfld.long 0x1A0 12.--14. "RXSEL,EMMC2_DATA6 PAD Input Select" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x1A0 8.--11. 1. "TXPREP,EMMC2_DATA6 PAD Slew-Rate control for P" newline hexmask.long.byte 0x1A0 4.--7. 1. "TXPREN,EMMC2_DATA6 PAD Slew-Rate control for N" bitfld.long 0x1A0 0.--1. "PULL_EN,EMMC2_DATA6 PAD Pull Enable. 0: OFF; 1: PU; 2: PD; 3: RESERVED." "OFF;,PU;,PD;,RESERVED" line.long 0x1A4 "IO_PAD_CONFIG_EMMC2_DATA7,PAD EMMC2_DATA7 config register" hexmask.long.byte 0x1A4 20.--23. 1. "SP,EMMC2_DATA7 PAD Drive Strength for P" hexmask.long.byte 0x1A4 16.--19. 1. "SN,EMMC2_DATA7 PAD Drive Strength for N" bitfld.long 0x1A4 12.--14. "RXSEL,EMMC2_DATA7 PAD Input Select" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x1A4 8.--11. 1. "TXPREP,EMMC2_DATA7 PAD Slew-Rate control for P" newline hexmask.long.byte 0x1A4 4.--7. 1. "TXPREN,EMMC2_DATA7 PAD Slew-Rate control for N" bitfld.long 0x1A4 0.--1. "PULL_EN,EMMC2_DATA7 PAD Pull Enable. 0: OFF; 1: PU; 2: PD; 3: RESERVED." "OFF;,PU;,PD;,RESERVED" line.long 0x1A8 "IO_PAD_CONFIG_EMMC2_STROBE,PAD EMMC2_STROBE config register" hexmask.long.byte 0x1A8 20.--23. 1. "SP,EMMC2_STROBE PAD Drive Strength for P" hexmask.long.byte 0x1A8 16.--19. 1. "SN,EMMC2_STROBE PAD Drive Strength for N" bitfld.long 0x1A8 12.--14. "RXSEL,EMMC2_STROBE PAD Input Select" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x1A8 8.--11. 1. "TXPREP,EMMC2_STROBE PAD Slew-Rate control for P" newline hexmask.long.byte 0x1A8 4.--7. 1. "TXPREN,EMMC2_STROBE PAD Slew-Rate control for N" bitfld.long 0x1A8 0.--1. "PULL_EN,EMMC2_STROBE PAD Pull Enable. 0: OFF; 1: PU; 2: PD; 3: RESERVED." "OFF;,PU;,PD;,RESERVED" line.long 0x1AC "IO_PAD_CONFIG_EMMC2_RESET_N,PAD EMMC2_RESET_N config register" hexmask.long.byte 0x1AC 20.--23. 1. "SP,EMMC2_RESET_N PAD Drive Strength for P" hexmask.long.byte 0x1AC 16.--19. 1. "SN,EMMC2_RESET_N PAD Drive Strength for N" bitfld.long 0x1AC 12.--14. "RXSEL,EMMC2_RESET_N PAD Input Select" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x1AC 8.--11. 1. "TXPREP,EMMC2_RESET_N PAD Slew-Rate control for P" newline hexmask.long.byte 0x1AC 4.--7. 1. "TXPREN,EMMC2_RESET_N PAD Slew-Rate control for N" bitfld.long 0x1AC 0.--1. "PULL_EN,EMMC2_RESET_N PAD Pull Enable. 0: OFF; 1: PU; 2: PD; 3: RESERVED." "OFF;,PU;,PD;,RESERVED" group.long 0x200++0x1AF line.long 0x0 "PIN_MUX_CONFIG_GPIO_C0,PAD GPIO_C0 pin-mux config register" bitfld.long 0x0 12. "FV,GPIO_C0 PAD Force Input Value when fin=0x2" "0,1" bitfld.long 0x0 8.--9. "FIN,GPIO_C0 PAD Force Input On/Off mode" "0,1,2,3" bitfld.long 0x0 4. "ODE,GPIO_C0 PAD Opn Drain Mode enable" "0,1" newline bitfld.long 0x0 0.--2. "MUX,GPIO_C0 PAD Pin-mux func select" "0,1,2,3,4,5,6,7" line.long 0x4 "PIN_MUX_CONFIG_GPIO_C1,PAD GPIO_C1 pin-mux config register" bitfld.long 0x4 12. "FV,GPIO_C1 PAD Force Input Value when fin=0x2" "0,1" bitfld.long 0x4 8.--9. "FIN,GPIO_C1 PAD Force Input On/Off mode" "0,1,2,3" bitfld.long 0x4 4. "ODE,GPIO_C1 PAD Opn Drain Mode enable" "0,1" newline bitfld.long 0x4 0.--2. "MUX,GPIO_C1 PAD Pin-mux func select" "0,1,2,3,4,5,6,7" line.long 0x8 "PIN_MUX_CONFIG_GPIO_C2,PAD GPIO_C2 pin-mux config register" bitfld.long 0x8 12. "FV,GPIO_C2 PAD Force Input Value when fin=0x2" "0,1" bitfld.long 0x8 8.--9. "FIN,GPIO_C2 PAD Force Input On/Off mode" "0,1,2,3" bitfld.long 0x8 4. "ODE,GPIO_C2 PAD Opn Drain Mode enable" "0,1" newline bitfld.long 0x8 0.--2. "MUX,GPIO_C2 PAD Pin-mux func select" "0,1,2,3,4,5,6,7" line.long 0xC "PIN_MUX_CONFIG_GPIO_C3,PAD GPIO_C3 pin-mux config register" bitfld.long 0xC 12. "FV,GPIO_C3 PAD Force Input Value when fin=0x2" "0,1" bitfld.long 0xC 8.--9. "FIN,GPIO_C3 PAD Force Input On/Off mode" "0,1,2,3" bitfld.long 0xC 4. "ODE,GPIO_C3 PAD Opn Drain Mode enable" "0,1" newline bitfld.long 0xC 0.--2. "MUX,GPIO_C3 PAD Pin-mux func select" "0,1,2,3,4,5,6,7" line.long 0x10 "PIN_MUX_CONFIG_GPIO_C4,PAD GPIO_C4 pin-mux config register" bitfld.long 0x10 12. "FV,GPIO_C4 PAD Force Input Value when fin=0x2" "0,1" bitfld.long 0x10 8.--9. "FIN,GPIO_C4 PAD Force Input On/Off mode" "0,1,2,3" bitfld.long 0x10 4. "ODE,GPIO_C4 PAD Opn Drain Mode enable" "0,1" newline bitfld.long 0x10 0.--2. "MUX,GPIO_C4 PAD Pin-mux func select" "0,1,2,3,4,5,6,7" line.long 0x14 "PIN_MUX_CONFIG_GPIO_C5,PAD GPIO_C5 pin-mux config register" bitfld.long 0x14 12. "FV,GPIO_C5 PAD Force Input Value when fin=0x2" "0,1" bitfld.long 0x14 8.--9. "FIN,GPIO_C5 PAD Force Input On/Off mode" "0,1,2,3" bitfld.long 0x14 4. "ODE,GPIO_C5 PAD Opn Drain Mode enable" "0,1" newline bitfld.long 0x14 0.--2. "MUX,GPIO_C5 PAD Pin-mux func select" "0,1,2,3,4,5,6,7" line.long 0x18 "PIN_MUX_CONFIG_GPIO_C6,PAD GPIO_C6 pin-mux config register" bitfld.long 0x18 12. "FV,GPIO_C6 PAD Force Input Value when fin=0x2" "0,1" bitfld.long 0x18 8.--9. "FIN,GPIO_C6 PAD Force Input On/Off mode" "0,1,2,3" bitfld.long 0x18 4. "ODE,GPIO_C6 PAD Opn Drain Mode enable" "0,1" newline bitfld.long 0x18 0.--2. "MUX,GPIO_C6 PAD Pin-mux func select" "0,1,2,3,4,5,6,7" line.long 0x1C "PIN_MUX_CONFIG_GPIO_C7,PAD GPIO_C7 pin-mux config register" bitfld.long 0x1C 12. "FV,GPIO_C7 PAD Force Input Value when fin=0x2" "0,1" bitfld.long 0x1C 8.--9. "FIN,GPIO_C7 PAD Force Input On/Off mode" "0,1,2,3" bitfld.long 0x1C 4. "ODE,GPIO_C7 PAD Opn Drain Mode enable" "0,1" newline bitfld.long 0x1C 0.--2. "MUX,GPIO_C7 PAD Pin-mux func select" "0,1,2,3,4,5,6,7" line.long 0x20 "PIN_MUX_CONFIG_GPIO_C8,PAD GPIO_C8 pin-mux config register" bitfld.long 0x20 12. "FV,GPIO_C8 PAD Force Input Value when fin=0x2" "0,1" bitfld.long 0x20 8.--9. "FIN,GPIO_C8 PAD Force Input On/Off mode" "0,1,2,3" bitfld.long 0x20 4. "ODE,GPIO_C8 PAD Opn Drain Mode enable" "0,1" newline bitfld.long 0x20 0.--2. "MUX,GPIO_C8 PAD Pin-mux func select" "0,1,2,3,4,5,6,7" line.long 0x24 "PIN_MUX_CONFIG_GPIO_C9,PAD GPIO_C9 pin-mux config register" bitfld.long 0x24 12. "FV,GPIO_C9 PAD Force Input Value when fin=0x2" "0,1" bitfld.long 0x24 8.--9. "FIN,GPIO_C9 PAD Force Input On/Off mode" "0,1,2,3" bitfld.long 0x24 4. "ODE,GPIO_C9 PAD Opn Drain Mode enable" "0,1" newline bitfld.long 0x24 0.--2. "MUX,GPIO_C9 PAD Pin-mux func select" "0,1,2,3,4,5,6,7" line.long 0x28 "PIN_MUX_CONFIG_GPIO_C10,PAD GPIO_C10 pin-mux config register" bitfld.long 0x28 12. "FV,GPIO_C10 PAD Force Input Value when fin=0x2" "0,1" bitfld.long 0x28 8.--9. "FIN,GPIO_C10 PAD Force Input On/Off mode" "0,1,2,3" bitfld.long 0x28 4. "ODE,GPIO_C10 PAD Opn Drain Mode enable" "0,1" newline bitfld.long 0x28 0.--2. "MUX,GPIO_C10 PAD Pin-mux func select" "0,1,2,3,4,5,6,7" line.long 0x2C "PIN_MUX_CONFIG_GPIO_C11,PAD GPIO_C11 pin-mux config register" bitfld.long 0x2C 12. "FV,GPIO_C11 PAD Force Input Value when fin=0x2" "0,1" bitfld.long 0x2C 8.--9. "FIN,GPIO_C11 PAD Force Input On/Off mode" "0,1,2,3" bitfld.long 0x2C 4. "ODE,GPIO_C11 PAD Opn Drain Mode enable" "0,1" newline bitfld.long 0x2C 0.--2. "MUX,GPIO_C11 PAD Pin-mux func select" "0,1,2,3,4,5,6,7" line.long 0x30 "PIN_MUX_CONFIG_GPIO_C12,PAD GPIO_C12 pin-mux config register" bitfld.long 0x30 12. "FV,GPIO_C12 PAD Force Input Value when fin=0x2" "0,1" bitfld.long 0x30 8.--9. "FIN,GPIO_C12 PAD Force Input On/Off mode" "0,1,2,3" bitfld.long 0x30 4. "ODE,GPIO_C12 PAD Opn Drain Mode enable" "0,1" newline bitfld.long 0x30 0.--2. "MUX,GPIO_C12 PAD Pin-mux func select" "0,1,2,3,4,5,6,7" line.long 0x34 "PIN_MUX_CONFIG_GPIO_C13,PAD GPIO_C13 pin-mux config register" bitfld.long 0x34 12. "FV,GPIO_C13 PAD Force Input Value when fin=0x2" "0,1" bitfld.long 0x34 8.--9. "FIN,GPIO_C13 PAD Force Input On/Off mode" "0,1,2,3" bitfld.long 0x34 4. "ODE,GPIO_C13 PAD Opn Drain Mode enable" "0,1" newline bitfld.long 0x34 0.--2. "MUX,GPIO_C13 PAD Pin-mux func select" "0,1,2,3,4,5,6,7" line.long 0x38 "PIN_MUX_CONFIG_GPIO_C14,PAD GPIO_C14 pin-mux config register" bitfld.long 0x38 12. "FV,GPIO_C14 PAD Force Input Value when fin=0x2" "0,1" bitfld.long 0x38 8.--9. "FIN,GPIO_C14 PAD Force Input On/Off mode" "0,1,2,3" bitfld.long 0x38 4. "ODE,GPIO_C14 PAD Opn Drain Mode enable" "0,1" newline bitfld.long 0x38 0.--2. "MUX,GPIO_C14 PAD Pin-mux func select" "0,1,2,3,4,5,6,7" line.long 0x3C "PIN_MUX_CONFIG_GPIO_C15,PAD GPIO_C15 pin-mux config register" bitfld.long 0x3C 12. "FV,GPIO_C15 PAD Force Input Value when fin=0x2" "0,1" bitfld.long 0x3C 8.--9. "FIN,GPIO_C15 PAD Force Input On/Off mode" "0,1,2,3" bitfld.long 0x3C 4. "ODE,GPIO_C15 PAD Opn Drain Mode enable" "0,1" newline bitfld.long 0x3C 0.--2. "MUX,GPIO_C15 PAD Pin-mux func select" "0,1,2,3,4,5,6,7" line.long 0x40 "PIN_MUX_CONFIG_GPIO_D0,PAD GPIO_D0 pin-mux config register" bitfld.long 0x40 12. "FV,GPIO_D0 PAD Force Input Value when fin=0x2" "0,1" bitfld.long 0x40 8.--9. "FIN,GPIO_D0 PAD Force Input On/Off mode" "0,1,2,3" bitfld.long 0x40 4. "ODE,GPIO_D0 PAD Opn Drain Mode enable" "0,1" newline bitfld.long 0x40 0.--2. "MUX,GPIO_D0 PAD Pin-mux func select" "0,1,2,3,4,5,6,7" line.long 0x44 "PIN_MUX_CONFIG_GPIO_D1,PAD GPIO_D1 pin-mux config register" bitfld.long 0x44 12. "FV,GPIO_D1 PAD Force Input Value when fin=0x2" "0,1" bitfld.long 0x44 8.--9. "FIN,GPIO_D1 PAD Force Input On/Off mode" "0,1,2,3" bitfld.long 0x44 4. "ODE,GPIO_D1 PAD Opn Drain Mode enable" "0,1" newline bitfld.long 0x44 0.--2. "MUX,GPIO_D1 PAD Pin-mux func select" "0,1,2,3,4,5,6,7" line.long 0x48 "PIN_MUX_CONFIG_GPIO_D2,PAD GPIO_D2 pin-mux config register" bitfld.long 0x48 12. "FV,GPIO_D2 PAD Force Input Value when fin=0x2" "0,1" bitfld.long 0x48 8.--9. "FIN,GPIO_D2 PAD Force Input On/Off mode" "0,1,2,3" bitfld.long 0x48 4. "ODE,GPIO_D2 PAD Opn Drain Mode enable" "0,1" newline bitfld.long 0x48 0.--2. "MUX,GPIO_D2 PAD Pin-mux func select" "0,1,2,3,4,5,6,7" line.long 0x4C "PIN_MUX_CONFIG_GPIO_D3,PAD GPIO_D3 pin-mux config register" bitfld.long 0x4C 12. "FV,GPIO_D3 PAD Force Input Value when fin=0x2" "0,1" bitfld.long 0x4C 8.--9. "FIN,GPIO_D3 PAD Force Input On/Off mode" "0,1,2,3" bitfld.long 0x4C 4. "ODE,GPIO_D3 PAD Opn Drain Mode enable" "0,1" newline bitfld.long 0x4C 0.--2. "MUX,GPIO_D3 PAD Pin-mux func select" "0,1,2,3,4,5,6,7" line.long 0x50 "PIN_MUX_CONFIG_GPIO_D4,PAD GPIO_D4 pin-mux config register" bitfld.long 0x50 12. "FV,GPIO_D4 PAD Force Input Value when fin=0x2" "0,1" bitfld.long 0x50 8.--9. "FIN,GPIO_D4 PAD Force Input On/Off mode" "0,1,2,3" bitfld.long 0x50 4. "ODE,GPIO_D4 PAD Opn Drain Mode enable" "0,1" newline bitfld.long 0x50 0.--2. "MUX,GPIO_D4 PAD Pin-mux func select" "0,1,2,3,4,5,6,7" line.long 0x54 "PIN_MUX_CONFIG_GPIO_D5,PAD GPIO_D5 pin-mux config register" bitfld.long 0x54 12. "FV,GPIO_D5 PAD Force Input Value when fin=0x2" "0,1" bitfld.long 0x54 8.--9. "FIN,GPIO_D5 PAD Force Input On/Off mode" "0,1,2,3" bitfld.long 0x54 4. "ODE,GPIO_D5 PAD Opn Drain Mode enable" "0,1" newline bitfld.long 0x54 0.--2. "MUX,GPIO_D5 PAD Pin-mux func select" "0,1,2,3,4,5,6,7" line.long 0x58 "PIN_MUX_CONFIG_GPIO_D6,PAD GPIO_D6 pin-mux config register" bitfld.long 0x58 12. "FV,GPIO_D6 PAD Force Input Value when fin=0x2" "0,1" bitfld.long 0x58 8.--9. "FIN,GPIO_D6 PAD Force Input On/Off mode" "0,1,2,3" bitfld.long 0x58 4. "ODE,GPIO_D6 PAD Opn Drain Mode enable" "0,1" newline bitfld.long 0x58 0.--2. "MUX,GPIO_D6 PAD Pin-mux func select" "0,1,2,3,4,5,6,7" line.long 0x5C "PIN_MUX_CONFIG_GPIO_D7,PAD GPIO_D7 pin-mux config register" bitfld.long 0x5C 12. "FV,GPIO_D7 PAD Force Input Value when fin=0x2" "0,1" bitfld.long 0x5C 8.--9. "FIN,GPIO_D7 PAD Force Input On/Off mode" "0,1,2,3" bitfld.long 0x5C 4. "ODE,GPIO_D7 PAD Opn Drain Mode enable" "0,1" newline bitfld.long 0x5C 0.--2. "MUX,GPIO_D7 PAD Pin-mux func select" "0,1,2,3,4,5,6,7" line.long 0x60 "PIN_MUX_CONFIG_GPIO_D8,PAD GPIO_D8 pin-mux config register" bitfld.long 0x60 12. "FV,GPIO_D8 PAD Force Input Value when fin=0x2" "0,1" bitfld.long 0x60 8.--9. "FIN,GPIO_D8 PAD Force Input On/Off mode" "0,1,2,3" bitfld.long 0x60 4. "ODE,GPIO_D8 PAD Opn Drain Mode enable" "0,1" newline bitfld.long 0x60 0.--2. "MUX,GPIO_D8 PAD Pin-mux func select" "0,1,2,3,4,5,6,7" line.long 0x64 "PIN_MUX_CONFIG_GPIO_D9,PAD GPIO_D9 pin-mux config register" bitfld.long 0x64 12. "FV,GPIO_D9 PAD Force Input Value when fin=0x2" "0,1" bitfld.long 0x64 8.--9. "FIN,GPIO_D9 PAD Force Input On/Off mode" "0,1,2,3" bitfld.long 0x64 4. "ODE,GPIO_D9 PAD Opn Drain Mode enable" "0,1" newline bitfld.long 0x64 0.--2. "MUX,GPIO_D9 PAD Pin-mux func select" "0,1,2,3,4,5,6,7" line.long 0x68 "PIN_MUX_CONFIG_GPIO_D10,PAD GPIO_D10 pin-mux config register" bitfld.long 0x68 12. "FV,GPIO_D10 PAD Force Input Value when fin=0x2" "0,1" bitfld.long 0x68 8.--9. "FIN,GPIO_D10 PAD Force Input On/Off mode" "0,1,2,3" bitfld.long 0x68 4. "ODE,GPIO_D10 PAD Opn Drain Mode enable" "0,1" newline bitfld.long 0x68 0.--2. "MUX,GPIO_D10 PAD Pin-mux func select" "0,1,2,3,4,5,6,7" line.long 0x6C "PIN_MUX_CONFIG_GPIO_D11,PAD GPIO_D11 pin-mux config register" bitfld.long 0x6C 12. "FV,GPIO_D11 PAD Force Input Value when fin=0x2" "0,1" bitfld.long 0x6C 8.--9. "FIN,GPIO_D11 PAD Force Input On/Off mode" "0,1,2,3" bitfld.long 0x6C 4. "ODE,GPIO_D11 PAD Opn Drain Mode enable" "0,1" newline bitfld.long 0x6C 0.--2. "MUX,GPIO_D11 PAD Pin-mux func select" "0,1,2,3,4,5,6,7" line.long 0x70 "PIN_MUX_CONFIG_GPIO_D12,PAD GPIO_D12 pin-mux config register" bitfld.long 0x70 12. "FV,GPIO_D12 PAD Force Input Value when fin=0x2" "0,1" bitfld.long 0x70 8.--9. "FIN,GPIO_D12 PAD Force Input On/Off mode" "0,1,2,3" bitfld.long 0x70 4. "ODE,GPIO_D12 PAD Opn Drain Mode enable" "0,1" newline bitfld.long 0x70 0.--2. "MUX,GPIO_D12 PAD Pin-mux func select" "0,1,2,3,4,5,6,7" line.long 0x74 "PIN_MUX_CONFIG_GPIO_D13,PAD GPIO_D13 pin-mux config register" bitfld.long 0x74 12. "FV,GPIO_D13 PAD Force Input Value when fin=0x2" "0,1" bitfld.long 0x74 8.--9. "FIN,GPIO_D13 PAD Force Input On/Off mode" "0,1,2,3" bitfld.long 0x74 4. "ODE,GPIO_D13 PAD Opn Drain Mode enable" "0,1" newline bitfld.long 0x74 0.--2. "MUX,GPIO_D13 PAD Pin-mux func select" "0,1,2,3,4,5,6,7" line.long 0x78 "PIN_MUX_CONFIG_GPIO_D14,PAD GPIO_D14 pin-mux config register" bitfld.long 0x78 12. "FV,GPIO_D14 PAD Force Input Value when fin=0x2" "0,1" bitfld.long 0x78 8.--9. "FIN,GPIO_D14 PAD Force Input On/Off mode" "0,1,2,3" bitfld.long 0x78 4. "ODE,GPIO_D14 PAD Opn Drain Mode enable" "0,1" newline bitfld.long 0x78 0.--2. "MUX,GPIO_D14 PAD Pin-mux func select" "0,1,2,3,4,5,6,7" line.long 0x7C "PIN_MUX_CONFIG_GPIO_D15,PAD GPIO_D15 pin-mux config register" bitfld.long 0x7C 12. "FV,GPIO_D15 PAD Force Input Value when fin=0x2" "0,1" bitfld.long 0x7C 8.--9. "FIN,GPIO_D15 PAD Force Input On/Off mode" "0,1,2,3" bitfld.long 0x7C 4. "ODE,GPIO_D15 PAD Opn Drain Mode enable" "0,1" newline bitfld.long 0x7C 0.--2. "MUX,GPIO_D15 PAD Pin-mux func select" "0,1,2,3,4,5,6,7" line.long 0x80 "PIN_MUX_CONFIG_OSPI2_SCLK,PAD OSPI2_SCLK pin-mux config register" bitfld.long 0x80 12. "FV,OSPI2_SCLK PAD Force Input Value when fin=0x2" "0,1" bitfld.long 0x80 8.--9. "FIN,OSPI2_SCLK PAD Force Input On/Off mode" "0,1,2,3" bitfld.long 0x80 4. "ODE,OSPI2_SCLK PAD Opn Drain Mode enable" "0,1" newline bitfld.long 0x80 0.--2. "MUX,OSPI2_SCLK PAD Pin-mux func select" "0,1,2,3,4,5,6,7" line.long 0x84 "PIN_MUX_CONFIG_OSPI2_SS0,PAD OSPI2_SS0 pin-mux config register" bitfld.long 0x84 12. "FV,OSPI2_SS0 PAD Force Input Value when fin=0x2" "0,1" bitfld.long 0x84 8.--9. "FIN,OSPI2_SS0 PAD Force Input On/Off mode" "0,1,2,3" bitfld.long 0x84 4. "ODE,OSPI2_SS0 PAD Opn Drain Mode enable" "0,1" newline bitfld.long 0x84 0.--2. "MUX,OSPI2_SS0 PAD Pin-mux func select" "0,1,2,3,4,5,6,7" line.long 0x88 "PIN_MUX_CONFIG_OSPI2_DATA0,PAD OSPI2_DATA0 pin-mux config register" bitfld.long 0x88 12. "FV,OSPI2_DATA0 PAD Force Input Value when fin=0x2" "0,1" bitfld.long 0x88 8.--9. "FIN,OSPI2_DATA0 PAD Force Input On/Off mode" "0,1,2,3" bitfld.long 0x88 4. "ODE,OSPI2_DATA0 PAD Opn Drain Mode enable" "0,1" newline bitfld.long 0x88 0.--2. "MUX,OSPI2_DATA0 PAD Pin-mux func select" "0,1,2,3,4,5,6,7" line.long 0x8C "PIN_MUX_CONFIG_OSPI2_DATA1,PAD OSPI2_DATA1 pin-mux config register" bitfld.long 0x8C 12. "FV,OSPI2_DATA1 PAD Force Input Value when fin=0x2" "0,1" bitfld.long 0x8C 8.--9. "FIN,OSPI2_DATA1 PAD Force Input On/Off mode" "0,1,2,3" bitfld.long 0x8C 4. "ODE,OSPI2_DATA1 PAD Opn Drain Mode enable" "0,1" newline bitfld.long 0x8C 0.--2. "MUX,OSPI2_DATA1 PAD Pin-mux func select" "0,1,2,3,4,5,6,7" line.long 0x90 "PIN_MUX_CONFIG_OSPI2_DATA2,PAD OSPI2_DATA2 pin-mux config register" bitfld.long 0x90 12. "FV,OSPI2_DATA2 PAD Force Input Value when fin=0x2" "0,1" bitfld.long 0x90 8.--9. "FIN,OSPI2_DATA2 PAD Force Input On/Off mode" "0,1,2,3" bitfld.long 0x90 4. "ODE,OSPI2_DATA2 PAD Opn Drain Mode enable" "0,1" newline bitfld.long 0x90 0.--2. "MUX,OSPI2_DATA2 PAD Pin-mux func select" "0,1,2,3,4,5,6,7" line.long 0x94 "PIN_MUX_CONFIG_OSPI2_DATA3,PAD OSPI2_DATA3 pin-mux config register" bitfld.long 0x94 12. "FV,OSPI2_DATA3 PAD Force Input Value when fin=0x2" "0,1" bitfld.long 0x94 8.--9. "FIN,OSPI2_DATA3 PAD Force Input On/Off mode" "0,1,2,3" bitfld.long 0x94 4. "ODE,OSPI2_DATA3 PAD Opn Drain Mode enable" "0,1" newline bitfld.long 0x94 0.--2. "MUX,OSPI2_DATA3 PAD Pin-mux func select" "0,1,2,3,4,5,6,7" line.long 0x98 "PIN_MUX_CONFIG_OSPI2_DATA4,PAD OSPI2_DATA4 pin-mux config register" bitfld.long 0x98 12. "FV,OSPI2_DATA4 PAD Force Input Value when fin=0x2" "0,1" bitfld.long 0x98 8.--9. "FIN,OSPI2_DATA4 PAD Force Input On/Off mode" "0,1,2,3" bitfld.long 0x98 4. "ODE,OSPI2_DATA4 PAD Opn Drain Mode enable" "0,1" newline bitfld.long 0x98 0.--2. "MUX,OSPI2_DATA4 PAD Pin-mux func select" "0,1,2,3,4,5,6,7" line.long 0x9C "PIN_MUX_CONFIG_OSPI2_DATA5,PAD OSPI2_DATA5 pin-mux config register" bitfld.long 0x9C 12. "FV,OSPI2_DATA5 PAD Force Input Value when fin=0x2" "0,1" bitfld.long 0x9C 8.--9. "FIN,OSPI2_DATA5 PAD Force Input On/Off mode" "0,1,2,3" bitfld.long 0x9C 4. "ODE,OSPI2_DATA5 PAD Opn Drain Mode enable" "0,1" newline bitfld.long 0x9C 0.--2. "MUX,OSPI2_DATA5 PAD Pin-mux func select" "0,1,2,3,4,5,6,7" line.long 0xA0 "PIN_MUX_CONFIG_OSPI2_DATA6,PAD OSPI2_DATA6 pin-mux config register" bitfld.long 0xA0 12. "FV,OSPI2_DATA6 PAD Force Input Value when fin=0x2" "0,1" bitfld.long 0xA0 8.--9. "FIN,OSPI2_DATA6 PAD Force Input On/Off mode" "0,1,2,3" bitfld.long 0xA0 4. "ODE,OSPI2_DATA6 PAD Opn Drain Mode enable" "0,1" newline bitfld.long 0xA0 0.--2. "MUX,OSPI2_DATA6 PAD Pin-mux func select" "0,1,2,3,4,5,6,7" line.long 0xA4 "PIN_MUX_CONFIG_OSPI2_DATA7,PAD OSPI2_DATA7 pin-mux config register" bitfld.long 0xA4 12. "FV,OSPI2_DATA7 PAD Force Input Value when fin=0x2" "0,1" bitfld.long 0xA4 8.--9. "FIN,OSPI2_DATA7 PAD Force Input On/Off mode" "0,1,2,3" bitfld.long 0xA4 4. "ODE,OSPI2_DATA7 PAD Opn Drain Mode enable" "0,1" newline bitfld.long 0xA4 0.--2. "MUX,OSPI2_DATA7 PAD Pin-mux func select" "0,1,2,3,4,5,6,7" line.long 0xA8 "PIN_MUX_CONFIG_OSPI2_DQS,PAD OSPI2_DQS pin-mux config register" bitfld.long 0xA8 12. "FV,OSPI2_DQS PAD Force Input Value when fin=0x2" "0,1" bitfld.long 0xA8 8.--9. "FIN,OSPI2_DQS PAD Force Input On/Off mode" "0,1,2,3" bitfld.long 0xA8 4. "ODE,OSPI2_DQS PAD Opn Drain Mode enable" "0,1" newline bitfld.long 0xA8 0.--2. "MUX,OSPI2_DQS PAD Pin-mux func select" "0,1,2,3,4,5,6,7" line.long 0xAC "PIN_MUX_CONFIG_OSPI2_SS1,PAD OSPI2_SS1 pin-mux config register" bitfld.long 0xAC 12. "FV,OSPI2_SS1 PAD Force Input Value when fin=0x2" "0,1" bitfld.long 0xAC 8.--9. "FIN,OSPI2_SS1 PAD Force Input On/Off mode" "0,1,2,3" bitfld.long 0xAC 4. "ODE,OSPI2_SS1 PAD Opn Drain Mode enable" "0,1" newline bitfld.long 0xAC 0.--2. "MUX,OSPI2_SS1 PAD Pin-mux func select" "0,1,2,3,4,5,6,7" line.long 0xB0 "PIN_MUX_CONFIG_RGMII2_TXC,PAD RGMII2_TXC pin-mux config register" bitfld.long 0xB0 12. "FV,RGMII2_TXC PAD Force Input Value when fin=0x2" "0,1" bitfld.long 0xB0 8.--9. "FIN,RGMII2_TXC PAD Force Input On/Off mode" "0,1,2,3" bitfld.long 0xB0 4. "ODE,RGMII2_TXC PAD Opn Drain Mode enable" "0,1" newline bitfld.long 0xB0 0.--2. "MUX,RGMII2_TXC PAD Pin-mux func select" "0,1,2,3,4,5,6,7" line.long 0xB4 "PIN_MUX_CONFIG_RGMII2_TXD0,PAD RGMII2_TXD0 pin-mux config register" bitfld.long 0xB4 12. "FV,RGMII2_TXD0 PAD Force Input Value when fin=0x2" "0,1" bitfld.long 0xB4 8.--9. "FIN,RGMII2_TXD0 PAD Force Input On/Off mode" "0,1,2,3" bitfld.long 0xB4 4. "ODE,RGMII2_TXD0 PAD Opn Drain Mode enable" "0,1" newline bitfld.long 0xB4 0.--2. "MUX,RGMII2_TXD0 PAD Pin-mux func select" "0,1,2,3,4,5,6,7" line.long 0xB8 "PIN_MUX_CONFIG_RGMII2_TXD1,PAD RGMII2_TXD1 pin-mux config register" bitfld.long 0xB8 12. "FV,RGMII2_TXD1 PAD Force Input Value when fin=0x2" "0,1" bitfld.long 0xB8 8.--9. "FIN,RGMII2_TXD1 PAD Force Input On/Off mode" "0,1,2,3" bitfld.long 0xB8 4. "ODE,RGMII2_TXD1 PAD Opn Drain Mode enable" "0,1" newline bitfld.long 0xB8 0.--2. "MUX,RGMII2_TXD1 PAD Pin-mux func select" "0,1,2,3,4,5,6,7" line.long 0xBC "PIN_MUX_CONFIG_RGMII2_TXD2,PAD RGMII2_TXD2 pin-mux config register" bitfld.long 0xBC 12. "FV,RGMII2_TXD2 PAD Force Input Value when fin=0x2" "0,1" bitfld.long 0xBC 8.--9. "FIN,RGMII2_TXD2 PAD Force Input On/Off mode" "0,1,2,3" bitfld.long 0xBC 4. "ODE,RGMII2_TXD2 PAD Opn Drain Mode enable" "0,1" newline bitfld.long 0xBC 0.--2. "MUX,RGMII2_TXD2 PAD Pin-mux func select" "0,1,2,3,4,5,6,7" line.long 0xC0 "PIN_MUX_CONFIG_RGMII2_TXD3,PAD RGMII2_TXD3 pin-mux config register" bitfld.long 0xC0 12. "FV,RGMII2_TXD3 PAD Force Input Value when fin=0x2" "0,1" bitfld.long 0xC0 8.--9. "FIN,RGMII2_TXD3 PAD Force Input On/Off mode" "0,1,2,3" bitfld.long 0xC0 4. "ODE,RGMII2_TXD3 PAD Opn Drain Mode enable" "0,1" newline bitfld.long 0xC0 0.--2. "MUX,RGMII2_TXD3 PAD Pin-mux func select" "0,1,2,3,4,5,6,7" line.long 0xC4 "PIN_MUX_CONFIG_RGMII2_TX_CTL,PAD RGMII2_TX_CTL pin-mux config register" bitfld.long 0xC4 12. "FV,RGMII2_TX_CTL PAD Force Input Value when fin=0x2" "0,1" bitfld.long 0xC4 8.--9. "FIN,RGMII2_TX_CTL PAD Force Input On/Off mode" "0,1,2,3" bitfld.long 0xC4 4. "ODE,RGMII2_TX_CTL PAD Opn Drain Mode enable" "0,1" newline bitfld.long 0xC4 0.--2. "MUX,RGMII2_TX_CTL PAD Pin-mux func select" "0,1,2,3,4,5,6,7" line.long 0xC8 "PIN_MUX_CONFIG_RGMII2_RXC,PAD RGMII2_RXC pin-mux config register" bitfld.long 0xC8 12. "FV,RGMII2_RXC PAD Force Input Value when fin=0x2" "0,1" bitfld.long 0xC8 8.--9. "FIN,RGMII2_RXC PAD Force Input On/Off mode" "0,1,2,3" bitfld.long 0xC8 4. "ODE,RGMII2_RXC PAD Opn Drain Mode enable" "0,1" newline bitfld.long 0xC8 0.--2. "MUX,RGMII2_RXC PAD Pin-mux func select" "0,1,2,3,4,5,6,7" line.long 0xCC "PIN_MUX_CONFIG_RGMII2_RXD0,PAD RGMII2_RXD0 pin-mux config register" bitfld.long 0xCC 12. "FV,RGMII2_RXD0 PAD Force Input Value when fin=0x2" "0,1" bitfld.long 0xCC 8.--9. "FIN,RGMII2_RXD0 PAD Force Input On/Off mode" "0,1,2,3" bitfld.long 0xCC 4. "ODE,RGMII2_RXD0 PAD Opn Drain Mode enable" "0,1" newline bitfld.long 0xCC 0.--2. "MUX,RGMII2_RXD0 PAD Pin-mux func select" "0,1,2,3,4,5,6,7" line.long 0xD0 "PIN_MUX_CONFIG_RGMII2_RXD1,PAD RGMII2_RXD1 pin-mux config register" bitfld.long 0xD0 12. "FV,RGMII2_RXD1 PAD Force Input Value when fin=0x2" "0,1" bitfld.long 0xD0 8.--9. "FIN,RGMII2_RXD1 PAD Force Input On/Off mode" "0,1,2,3" bitfld.long 0xD0 4. "ODE,RGMII2_RXD1 PAD Opn Drain Mode enable" "0,1" newline bitfld.long 0xD0 0.--2. "MUX,RGMII2_RXD1 PAD Pin-mux func select" "0,1,2,3,4,5,6,7" line.long 0xD4 "PIN_MUX_CONFIG_RGMII2_RXD2,PAD RGMII2_RXD2 pin-mux config register" bitfld.long 0xD4 12. "FV,RGMII2_RXD2 PAD Force Input Value when fin=0x2" "0,1" bitfld.long 0xD4 8.--9. "FIN,RGMII2_RXD2 PAD Force Input On/Off mode" "0,1,2,3" bitfld.long 0xD4 4. "ODE,RGMII2_RXD2 PAD Opn Drain Mode enable" "0,1" newline bitfld.long 0xD4 0.--2. "MUX,RGMII2_RXD2 PAD Pin-mux func select" "0,1,2,3,4,5,6,7" line.long 0xD8 "PIN_MUX_CONFIG_RGMII2_RXD3,PAD RGMII2_RXD3 pin-mux config register" bitfld.long 0xD8 12. "FV,RGMII2_RXD3 PAD Force Input Value when fin=0x2" "0,1" bitfld.long 0xD8 8.--9. "FIN,RGMII2_RXD3 PAD Force Input On/Off mode" "0,1,2,3" bitfld.long 0xD8 4. "ODE,RGMII2_RXD3 PAD Opn Drain Mode enable" "0,1" newline bitfld.long 0xD8 0.--2. "MUX,RGMII2_RXD3 PAD Pin-mux func select" "0,1,2,3,4,5,6,7" line.long 0xDC "PIN_MUX_CONFIG_RGMII2_RX_CTL,PAD RGMII2_RX_CTL pin-mux config register" bitfld.long 0xDC 12. "FV,RGMII2_RX_CTL PAD Force Input Value when fin=0x2" "0,1" bitfld.long 0xDC 8.--9. "FIN,RGMII2_RX_CTL PAD Force Input On/Off mode" "0,1,2,3" bitfld.long 0xDC 4. "ODE,RGMII2_RX_CTL PAD Opn Drain Mode enable" "0,1" newline bitfld.long 0xDC 0.--2. "MUX,RGMII2_RX_CTL PAD Pin-mux func select" "0,1,2,3,4,5,6,7" line.long 0xE0 "PIN_MUX_CONFIG_I2S_SC3_SCK,PAD I2S_SC3_SCK pin-mux config register" bitfld.long 0xE0 12. "FV,I2S_SC3_SCK PAD Force Input Value when fin=0x2" "0,1" bitfld.long 0xE0 8.--9. "FIN,I2S_SC3_SCK PAD Force Input On/Off mode" "0,1,2,3" bitfld.long 0xE0 4. "ODE,I2S_SC3_SCK PAD Opn Drain Mode enable" "0,1" newline bitfld.long 0xE0 0.--2. "MUX,I2S_SC3_SCK PAD Pin-mux func select" "0,1,2,3,4,5,6,7" line.long 0xE4 "PIN_MUX_CONFIG_I2S_SC3_WS,PAD I2S_SC3_WS pin-mux config register" bitfld.long 0xE4 12. "FV,I2S_SC3_WS PAD Force Input Value when fin=0x2" "0,1" bitfld.long 0xE4 8.--9. "FIN,I2S_SC3_WS PAD Force Input On/Off mode" "0,1,2,3" bitfld.long 0xE4 4. "ODE,I2S_SC3_WS PAD Opn Drain Mode enable" "0,1" newline bitfld.long 0xE4 0.--2. "MUX,I2S_SC3_WS PAD Pin-mux func select" "0,1,2,3,4,5,6,7" line.long 0xE8 "PIN_MUX_CONFIG_I2S_SC3_SD,PAD I2S_SC3_SD pin-mux config register" bitfld.long 0xE8 12. "FV,I2S_SC3_SD PAD Force Input Value when fin=0x2" "0,1" bitfld.long 0xE8 8.--9. "FIN,I2S_SC3_SD PAD Force Input On/Off mode" "0,1,2,3" bitfld.long 0xE8 4. "ODE,I2S_SC3_SD PAD Opn Drain Mode enable" "0,1" newline bitfld.long 0xE8 0.--2. "MUX,I2S_SC3_SD PAD Pin-mux func select" "0,1,2,3,4,5,6,7" line.long 0xEC "PIN_MUX_CONFIG_I2S_SC4_SCK,PAD I2S_SC4_SCK pin-mux config register" bitfld.long 0xEC 12. "FV,I2S_SC4_SCK PAD Force Input Value when fin=0x2" "0,1" bitfld.long 0xEC 8.--9. "FIN,I2S_SC4_SCK PAD Force Input On/Off mode" "0,1,2,3" bitfld.long 0xEC 4. "ODE,I2S_SC4_SCK PAD Opn Drain Mode enable" "0,1" newline bitfld.long 0xEC 0.--2. "MUX,I2S_SC4_SCK PAD Pin-mux func select" "0,1,2,3,4,5,6,7" line.long 0xF0 "PIN_MUX_CONFIG_I2S_SC4_WS,PAD I2S_SC4_WS pin-mux config register" bitfld.long 0xF0 12. "FV,I2S_SC4_WS PAD Force Input Value when fin=0x2" "0,1" bitfld.long 0xF0 8.--9. "FIN,I2S_SC4_WS PAD Force Input On/Off mode" "0,1,2,3" bitfld.long 0xF0 4. "ODE,I2S_SC4_WS PAD Opn Drain Mode enable" "0,1" newline bitfld.long 0xF0 0.--2. "MUX,I2S_SC4_WS PAD Pin-mux func select" "0,1,2,3,4,5,6,7" line.long 0xF4 "PIN_MUX_CONFIG_I2S_SC4_SD,PAD I2S_SC4_SD pin-mux config register" bitfld.long 0xF4 12. "FV,I2S_SC4_SD PAD Force Input Value when fin=0x2" "0,1" bitfld.long 0xF4 8.--9. "FIN,I2S_SC4_SD PAD Force Input On/Off mode" "0,1,2,3" bitfld.long 0xF4 4. "ODE,I2S_SC4_SD PAD Opn Drain Mode enable" "0,1" newline bitfld.long 0xF4 0.--2. "MUX,I2S_SC4_SD PAD Pin-mux func select" "0,1,2,3,4,5,6,7" line.long 0xF8 "PIN_MUX_CONFIG_I2S_SC5_SCK,PAD I2S_SC5_SCK pin-mux config register" bitfld.long 0xF8 12. "FV,I2S_SC5_SCK PAD Force Input Value when fin=0x2" "0,1" bitfld.long 0xF8 8.--9. "FIN,I2S_SC5_SCK PAD Force Input On/Off mode" "0,1,2,3" bitfld.long 0xF8 4. "ODE,I2S_SC5_SCK PAD Opn Drain Mode enable" "0,1" newline bitfld.long 0xF8 0.--2. "MUX,I2S_SC5_SCK PAD Pin-mux func select" "0,1,2,3,4,5,6,7" line.long 0xFC "PIN_MUX_CONFIG_I2S_SC5_WS,PAD I2S_SC5_WS pin-mux config register" bitfld.long 0xFC 12. "FV,I2S_SC5_WS PAD Force Input Value when fin=0x2" "0,1" bitfld.long 0xFC 8.--9. "FIN,I2S_SC5_WS PAD Force Input On/Off mode" "0,1,2,3" bitfld.long 0xFC 4. "ODE,I2S_SC5_WS PAD Opn Drain Mode enable" "0,1" newline bitfld.long 0xFC 0.--2. "MUX,I2S_SC5_WS PAD Pin-mux func select" "0,1,2,3,4,5,6,7" line.long 0x100 "PIN_MUX_CONFIG_I2S_SC5_SD,PAD I2S_SC5_SD pin-mux config register" bitfld.long 0x100 12. "FV,I2S_SC5_SD PAD Force Input Value when fin=0x2" "0,1" bitfld.long 0x100 8.--9. "FIN,I2S_SC5_SD PAD Force Input On/Off mode" "0,1,2,3" bitfld.long 0x100 4. "ODE,I2S_SC5_SD PAD Opn Drain Mode enable" "0,1" newline bitfld.long 0x100 0.--2. "MUX,I2S_SC5_SD PAD Pin-mux func select" "0,1,2,3,4,5,6,7" line.long 0x104 "PIN_MUX_CONFIG_I2S_SC6_SCK,PAD I2S_SC6_SCK pin-mux config register" bitfld.long 0x104 12. "FV,I2S_SC6_SCK PAD Force Input Value when fin=0x2" "0,1" bitfld.long 0x104 8.--9. "FIN,I2S_SC6_SCK PAD Force Input On/Off mode" "0,1,2,3" bitfld.long 0x104 4. "ODE,I2S_SC6_SCK PAD Opn Drain Mode enable" "0,1" newline bitfld.long 0x104 0.--2. "MUX,I2S_SC6_SCK PAD Pin-mux func select" "0,1,2,3,4,5,6,7" line.long 0x108 "PIN_MUX_CONFIG_I2S_SC6_WS,PAD I2S_SC6_WS pin-mux config register" bitfld.long 0x108 12. "FV,I2S_SC6_WS PAD Force Input Value when fin=0x2" "0,1" bitfld.long 0x108 8.--9. "FIN,I2S_SC6_WS PAD Force Input On/Off mode" "0,1,2,3" bitfld.long 0x108 4. "ODE,I2S_SC6_WS PAD Opn Drain Mode enable" "0,1" newline bitfld.long 0x108 0.--2. "MUX,I2S_SC6_WS PAD Pin-mux func select" "0,1,2,3,4,5,6,7" line.long 0x10C "PIN_MUX_CONFIG_I2S_SC6_SD,PAD I2S_SC6_SD pin-mux config register" bitfld.long 0x10C 12. "FV,I2S_SC6_SD PAD Force Input Value when fin=0x2" "0,1" bitfld.long 0x10C 8.--9. "FIN,I2S_SC6_SD PAD Force Input On/Off mode" "0,1,2,3" bitfld.long 0x10C 4. "ODE,I2S_SC6_SD PAD Opn Drain Mode enable" "0,1" newline bitfld.long 0x10C 0.--2. "MUX,I2S_SC6_SD PAD Pin-mux func select" "0,1,2,3,4,5,6,7" line.long 0x110 "PIN_MUX_CONFIG_I2S_SC7_SCK,PAD I2S_SC7_SCK pin-mux config register" bitfld.long 0x110 12. "FV,I2S_SC7_SCK PAD Force Input Value when fin=0x2" "0,1" bitfld.long 0x110 8.--9. "FIN,I2S_SC7_SCK PAD Force Input On/Off mode" "0,1,2,3" bitfld.long 0x110 4. "ODE,I2S_SC7_SCK PAD Opn Drain Mode enable" "0,1" newline bitfld.long 0x110 0.--2. "MUX,I2S_SC7_SCK PAD Pin-mux func select" "0,1,2,3,4,5,6,7" line.long 0x114 "PIN_MUX_CONFIG_I2S_SC7_WS,PAD I2S_SC7_WS pin-mux config register" bitfld.long 0x114 12. "FV,I2S_SC7_WS PAD Force Input Value when fin=0x2" "0,1" bitfld.long 0x114 8.--9. "FIN,I2S_SC7_WS PAD Force Input On/Off mode" "0,1,2,3" bitfld.long 0x114 4. "ODE,I2S_SC7_WS PAD Opn Drain Mode enable" "0,1" newline bitfld.long 0x114 0.--2. "MUX,I2S_SC7_WS PAD Pin-mux func select" "0,1,2,3,4,5,6,7" line.long 0x118 "PIN_MUX_CONFIG_I2S_SC7_SD,PAD I2S_SC7_SD pin-mux config register" bitfld.long 0x118 12. "FV,I2S_SC7_SD PAD Force Input Value when fin=0x2" "0,1" bitfld.long 0x118 8.--9. "FIN,I2S_SC7_SD PAD Force Input On/Off mode" "0,1,2,3" bitfld.long 0x118 4. "ODE,I2S_SC7_SD PAD Opn Drain Mode enable" "0,1" newline bitfld.long 0x118 0.--2. "MUX,I2S_SC7_SD PAD Pin-mux func select" "0,1,2,3,4,5,6,7" line.long 0x11C "PIN_MUX_CONFIG_I2S_SC8_SCK,PAD I2S_SC8_SCK pin-mux config register" bitfld.long 0x11C 12. "FV,I2S_SC8_SCK PAD Force Input Value when fin=0x2" "0,1" bitfld.long 0x11C 8.--9. "FIN,I2S_SC8_SCK PAD Force Input On/Off mode" "0,1,2,3" bitfld.long 0x11C 4. "ODE,I2S_SC8_SCK PAD Opn Drain Mode enable" "0,1" newline bitfld.long 0x11C 0.--2. "MUX,I2S_SC8_SCK PAD Pin-mux func select" "0,1,2,3,4,5,6,7" line.long 0x120 "PIN_MUX_CONFIG_I2S_SC8_WS,PAD I2S_SC8_WS pin-mux config register" bitfld.long 0x120 12. "FV,I2S_SC8_WS PAD Force Input Value when fin=0x2" "0,1" bitfld.long 0x120 8.--9. "FIN,I2S_SC8_WS PAD Force Input On/Off mode" "0,1,2,3" bitfld.long 0x120 4. "ODE,I2S_SC8_WS PAD Opn Drain Mode enable" "0,1" newline bitfld.long 0x120 0.--2. "MUX,I2S_SC8_WS PAD Pin-mux func select" "0,1,2,3,4,5,6,7" line.long 0x124 "PIN_MUX_CONFIG_I2S_SC8_SD,PAD I2S_SC8_SD pin-mux config register" bitfld.long 0x124 12. "FV,I2S_SC8_SD PAD Force Input Value when fin=0x2" "0,1" bitfld.long 0x124 8.--9. "FIN,I2S_SC8_SD PAD Force Input On/Off mode" "0,1,2,3" bitfld.long 0x124 4. "ODE,I2S_SC8_SD PAD Opn Drain Mode enable" "0,1" newline bitfld.long 0x124 0.--2. "MUX,I2S_SC8_SD PAD Pin-mux func select" "0,1,2,3,4,5,6,7" line.long 0x128 "PIN_MUX_CONFIG_I2S_MC_SCK,PAD I2S_MC_SCK pin-mux config register" bitfld.long 0x128 12. "FV,I2S_MC_SCK PAD Force Input Value when fin=0x2" "0,1" bitfld.long 0x128 8.--9. "FIN,I2S_MC_SCK PAD Force Input On/Off mode" "0,1,2,3" bitfld.long 0x128 4. "ODE,I2S_MC_SCK PAD Opn Drain Mode enable" "0,1" newline bitfld.long 0x128 0.--2. "MUX,I2S_MC_SCK PAD Pin-mux func select" "0,1,2,3,4,5,6,7" line.long 0x12C "PIN_MUX_CONFIG_I2S_MC_WS,PAD I2S_MC_WS pin-mux config register" bitfld.long 0x12C 12. "FV,I2S_MC_WS PAD Force Input Value when fin=0x2" "0,1" bitfld.long 0x12C 8.--9. "FIN,I2S_MC_WS PAD Force Input On/Off mode" "0,1,2,3" bitfld.long 0x12C 4. "ODE,I2S_MC_WS PAD Opn Drain Mode enable" "0,1" newline bitfld.long 0x12C 0.--2. "MUX,I2S_MC_WS PAD Pin-mux func select" "0,1,2,3,4,5,6,7" line.long 0x130 "PIN_MUX_CONFIG_I2S_MC_SD0,PAD I2S_MC_SD0 pin-mux config register" bitfld.long 0x130 12. "FV,I2S_MC_SD0 PAD Force Input Value when fin=0x2" "0,1" bitfld.long 0x130 8.--9. "FIN,I2S_MC_SD0 PAD Force Input On/Off mode" "0,1,2,3" bitfld.long 0x130 4. "ODE,I2S_MC_SD0 PAD Opn Drain Mode enable" "0,1" newline bitfld.long 0x130 0.--2. "MUX,I2S_MC_SD0 PAD Pin-mux func select" "0,1,2,3,4,5,6,7" line.long 0x134 "PIN_MUX_CONFIG_I2S_MC_SD1,PAD I2S_MC_SD1 pin-mux config register" bitfld.long 0x134 12. "FV,I2S_MC_SD1 PAD Force Input Value when fin=0x2" "0,1" bitfld.long 0x134 8.--9. "FIN,I2S_MC_SD1 PAD Force Input On/Off mode" "0,1,2,3" bitfld.long 0x134 4. "ODE,I2S_MC_SD1 PAD Opn Drain Mode enable" "0,1" newline bitfld.long 0x134 0.--2. "MUX,I2S_MC_SD1 PAD Pin-mux func select" "0,1,2,3,4,5,6,7" line.long 0x138 "PIN_MUX_CONFIG_I2S_MC_SD2,PAD I2S_MC_SD2 pin-mux config register" bitfld.long 0x138 12. "FV,I2S_MC_SD2 PAD Force Input Value when fin=0x2" "0,1" bitfld.long 0x138 8.--9. "FIN,I2S_MC_SD2 PAD Force Input On/Off mode" "0,1,2,3" bitfld.long 0x138 4. "ODE,I2S_MC_SD2 PAD Opn Drain Mode enable" "0,1" newline bitfld.long 0x138 0.--2. "MUX,I2S_MC_SD2 PAD Pin-mux func select" "0,1,2,3,4,5,6,7" line.long 0x13C "PIN_MUX_CONFIG_I2S_MC_SD3,PAD I2S_MC_SD3 pin-mux config register" bitfld.long 0x13C 12. "FV,I2S_MC_SD3 PAD Force Input Value when fin=0x2" "0,1" bitfld.long 0x13C 8.--9. "FIN,I2S_MC_SD3 PAD Force Input On/Off mode" "0,1,2,3" bitfld.long 0x13C 4. "ODE,I2S_MC_SD3 PAD Opn Drain Mode enable" "0,1" newline bitfld.long 0x13C 0.--2. "MUX,I2S_MC_SD3 PAD Pin-mux func select" "0,1,2,3,4,5,6,7" line.long 0x140 "PIN_MUX_CONFIG_I2S_MC_SD4,PAD I2S_MC_SD4 pin-mux config register" bitfld.long 0x140 12. "FV,I2S_MC_SD4 PAD Force Input Value when fin=0x2" "0,1" bitfld.long 0x140 8.--9. "FIN,I2S_MC_SD4 PAD Force Input On/Off mode" "0,1,2,3" bitfld.long 0x140 4. "ODE,I2S_MC_SD4 PAD Opn Drain Mode enable" "0,1" newline bitfld.long 0x140 0.--2. "MUX,I2S_MC_SD4 PAD Pin-mux func select" "0,1,2,3,4,5,6,7" line.long 0x144 "PIN_MUX_CONFIG_I2S_MC_SD5,PAD I2S_MC_SD5 pin-mux config register" bitfld.long 0x144 12. "FV,I2S_MC_SD5 PAD Force Input Value when fin=0x2" "0,1" bitfld.long 0x144 8.--9. "FIN,I2S_MC_SD5 PAD Force Input On/Off mode" "0,1,2,3" bitfld.long 0x144 4. "ODE,I2S_MC_SD5 PAD Opn Drain Mode enable" "0,1" newline bitfld.long 0x144 0.--2. "MUX,I2S_MC_SD5 PAD Pin-mux func select" "0,1,2,3,4,5,6,7" line.long 0x148 "PIN_MUX_CONFIG_I2S_MC_SD6,PAD I2S_MC_SD6 pin-mux config register" bitfld.long 0x148 12. "FV,I2S_MC_SD6 PAD Force Input Value when fin=0x2" "0,1" bitfld.long 0x148 8.--9. "FIN,I2S_MC_SD6 PAD Force Input On/Off mode" "0,1,2,3" bitfld.long 0x148 4. "ODE,I2S_MC_SD6 PAD Opn Drain Mode enable" "0,1" newline bitfld.long 0x148 0.--2. "MUX,I2S_MC_SD6 PAD Pin-mux func select" "0,1,2,3,4,5,6,7" line.long 0x14C "PIN_MUX_CONFIG_I2S_MC_SD7,PAD I2S_MC_SD7 pin-mux config register" bitfld.long 0x14C 12. "FV,I2S_MC_SD7 PAD Force Input Value when fin=0x2" "0,1" bitfld.long 0x14C 8.--9. "FIN,I2S_MC_SD7 PAD Force Input On/Off mode" "0,1,2,3" bitfld.long 0x14C 4. "ODE,I2S_MC_SD7 PAD Opn Drain Mode enable" "0,1" newline bitfld.long 0x14C 0.--2. "MUX,I2S_MC_SD7 PAD Pin-mux func select" "0,1,2,3,4,5,6,7" line.long 0x150 "PIN_MUX_CONFIG_EMMC1_CLK,PAD EMMC1_CLK pin-mux config register" bitfld.long 0x150 12. "FV,EMMC1_CLK PAD Force Input Value when fin=0x2" "0,1" bitfld.long 0x150 8.--9. "FIN,EMMC1_CLK PAD Force Input On/Off mode" "0,1,2,3" bitfld.long 0x150 4. "ODE,EMMC1_CLK PAD Opn Drain Mode enable" "0,1" newline bitfld.long 0x150 0.--2. "MUX,EMMC1_CLK PAD Pin-mux func select" "0,1,2,3,4,5,6,7" line.long 0x154 "PIN_MUX_CONFIG_EMMC1_CMD,PAD EMMC1_CMD pin-mux config register" bitfld.long 0x154 12. "FV,EMMC1_CMD PAD Force Input Value when fin=0x2" "0,1" bitfld.long 0x154 8.--9. "FIN,EMMC1_CMD PAD Force Input On/Off mode" "0,1,2,3" bitfld.long 0x154 4. "ODE,EMMC1_CMD PAD Opn Drain Mode enable" "0,1" newline bitfld.long 0x154 0.--2. "MUX,EMMC1_CMD PAD Pin-mux func select" "0,1,2,3,4,5,6,7" line.long 0x158 "PIN_MUX_CONFIG_EMMC1_DATA0,PAD EMMC1_DATA0 pin-mux config register" bitfld.long 0x158 12. "FV,EMMC1_DATA0 PAD Force Input Value when fin=0x2" "0,1" bitfld.long 0x158 8.--9. "FIN,EMMC1_DATA0 PAD Force Input On/Off mode" "0,1,2,3" bitfld.long 0x158 4. "ODE,EMMC1_DATA0 PAD Opn Drain Mode enable" "0,1" newline bitfld.long 0x158 0.--2. "MUX,EMMC1_DATA0 PAD Pin-mux func select" "0,1,2,3,4,5,6,7" line.long 0x15C "PIN_MUX_CONFIG_EMMC1_DATA1,PAD EMMC1_DATA1 pin-mux config register" bitfld.long 0x15C 12. "FV,EMMC1_DATA1 PAD Force Input Value when fin=0x2" "0,1" bitfld.long 0x15C 8.--9. "FIN,EMMC1_DATA1 PAD Force Input On/Off mode" "0,1,2,3" bitfld.long 0x15C 4. "ODE,EMMC1_DATA1 PAD Opn Drain Mode enable" "0,1" newline bitfld.long 0x15C 0.--2. "MUX,EMMC1_DATA1 PAD Pin-mux func select" "0,1,2,3,4,5,6,7" line.long 0x160 "PIN_MUX_CONFIG_EMMC1_DATA2,PAD EMMC1_DATA2 pin-mux config register" bitfld.long 0x160 12. "FV,EMMC1_DATA2 PAD Force Input Value when fin=0x2" "0,1" bitfld.long 0x160 8.--9. "FIN,EMMC1_DATA2 PAD Force Input On/Off mode" "0,1,2,3" bitfld.long 0x160 4. "ODE,EMMC1_DATA2 PAD Opn Drain Mode enable" "0,1" newline bitfld.long 0x160 0.--2. "MUX,EMMC1_DATA2 PAD Pin-mux func select" "0,1,2,3,4,5,6,7" line.long 0x164 "PIN_MUX_CONFIG_EMMC1_DATA3,PAD EMMC1_DATA3 pin-mux config register" bitfld.long 0x164 12. "FV,EMMC1_DATA3 PAD Force Input Value when fin=0x2" "0,1" bitfld.long 0x164 8.--9. "FIN,EMMC1_DATA3 PAD Force Input On/Off mode" "0,1,2,3" bitfld.long 0x164 4. "ODE,EMMC1_DATA3 PAD Opn Drain Mode enable" "0,1" newline bitfld.long 0x164 0.--2. "MUX,EMMC1_DATA3 PAD Pin-mux func select" "0,1,2,3,4,5,6,7" line.long 0x168 "PIN_MUX_CONFIG_EMMC1_DATA4,PAD EMMC1_DATA4 pin-mux config register" bitfld.long 0x168 12. "FV,EMMC1_DATA4 PAD Force Input Value when fin=0x2" "0,1" bitfld.long 0x168 8.--9. "FIN,EMMC1_DATA4 PAD Force Input On/Off mode" "0,1,2,3" bitfld.long 0x168 4. "ODE,EMMC1_DATA4 PAD Opn Drain Mode enable" "0,1" newline bitfld.long 0x168 0.--2. "MUX,EMMC1_DATA4 PAD Pin-mux func select" "0,1,2,3,4,5,6,7" line.long 0x16C "PIN_MUX_CONFIG_EMMC1_DATA5,PAD EMMC1_DATA5 pin-mux config register" bitfld.long 0x16C 12. "FV,EMMC1_DATA5 PAD Force Input Value when fin=0x2" "0,1" bitfld.long 0x16C 8.--9. "FIN,EMMC1_DATA5 PAD Force Input On/Off mode" "0,1,2,3" bitfld.long 0x16C 4. "ODE,EMMC1_DATA5 PAD Opn Drain Mode enable" "0,1" newline bitfld.long 0x16C 0.--2. "MUX,EMMC1_DATA5 PAD Pin-mux func select" "0,1,2,3,4,5,6,7" line.long 0x170 "PIN_MUX_CONFIG_EMMC1_DATA6,PAD EMMC1_DATA6 pin-mux config register" bitfld.long 0x170 12. "FV,EMMC1_DATA6 PAD Force Input Value when fin=0x2" "0,1" bitfld.long 0x170 8.--9. "FIN,EMMC1_DATA6 PAD Force Input On/Off mode" "0,1,2,3" bitfld.long 0x170 4. "ODE,EMMC1_DATA6 PAD Opn Drain Mode enable" "0,1" newline bitfld.long 0x170 0.--2. "MUX,EMMC1_DATA6 PAD Pin-mux func select" "0,1,2,3,4,5,6,7" line.long 0x174 "PIN_MUX_CONFIG_EMMC1_DATA7,PAD EMMC1_DATA7 pin-mux config register" bitfld.long 0x174 12. "FV,EMMC1_DATA7 PAD Force Input Value when fin=0x2" "0,1" bitfld.long 0x174 8.--9. "FIN,EMMC1_DATA7 PAD Force Input On/Off mode" "0,1,2,3" bitfld.long 0x174 4. "ODE,EMMC1_DATA7 PAD Opn Drain Mode enable" "0,1" newline bitfld.long 0x174 0.--2. "MUX,EMMC1_DATA7 PAD Pin-mux func select" "0,1,2,3,4,5,6,7" line.long 0x178 "PIN_MUX_CONFIG_EMMC1_STROBE,PAD EMMC1_STROBE pin-mux config register" bitfld.long 0x178 12. "FV,EMMC1_STROBE PAD Force Input Value when fin=0x2" "0,1" bitfld.long 0x178 8.--9. "FIN,EMMC1_STROBE PAD Force Input On/Off mode" "0,1,2,3" bitfld.long 0x178 4. "ODE,EMMC1_STROBE PAD Opn Drain Mode enable" "0,1" newline bitfld.long 0x178 0.--2. "MUX,EMMC1_STROBE PAD Pin-mux func select" "0,1,2,3,4,5,6,7" line.long 0x17C "PIN_MUX_CONFIG_EMMC1_RESET_N,PAD EMMC1_RESET_N pin-mux config register" bitfld.long 0x17C 12. "FV,EMMC1_RESET_N PAD Force Input Value when fin=0x2" "0,1" bitfld.long 0x17C 8.--9. "FIN,EMMC1_RESET_N PAD Force Input On/Off mode" "0,1,2,3" bitfld.long 0x17C 4. "ODE,EMMC1_RESET_N PAD Opn Drain Mode enable" "0,1" newline bitfld.long 0x17C 0.--2. "MUX,EMMC1_RESET_N PAD Pin-mux func select" "0,1,2,3,4,5,6,7" line.long 0x180 "PIN_MUX_CONFIG_EMMC2_CLK,PAD EMMC2_CLK pin-mux config register" bitfld.long 0x180 12. "FV,EMMC2_CLK PAD Force Input Value when fin=0x2" "0,1" bitfld.long 0x180 8.--9. "FIN,EMMC2_CLK PAD Force Input On/Off mode" "0,1,2,3" bitfld.long 0x180 4. "ODE,EMMC2_CLK PAD Opn Drain Mode enable" "0,1" newline bitfld.long 0x180 0.--2. "MUX,EMMC2_CLK PAD Pin-mux func select" "0,1,2,3,4,5,6,7" line.long 0x184 "PIN_MUX_CONFIG_EMMC2_CMD,PAD EMMC2_CMD pin-mux config register" bitfld.long 0x184 12. "FV,EMMC2_CMD PAD Force Input Value when fin=0x2" "0,1" bitfld.long 0x184 8.--9. "FIN,EMMC2_CMD PAD Force Input On/Off mode" "0,1,2,3" bitfld.long 0x184 4. "ODE,EMMC2_CMD PAD Opn Drain Mode enable" "0,1" newline bitfld.long 0x184 0.--2. "MUX,EMMC2_CMD PAD Pin-mux func select" "0,1,2,3,4,5,6,7" line.long 0x188 "PIN_MUX_CONFIG_EMMC2_DATA0,PAD EMMC2_DATA0 pin-mux config register" bitfld.long 0x188 12. "FV,EMMC2_DATA0 PAD Force Input Value when fin=0x2" "0,1" bitfld.long 0x188 8.--9. "FIN,EMMC2_DATA0 PAD Force Input On/Off mode" "0,1,2,3" bitfld.long 0x188 4. "ODE,EMMC2_DATA0 PAD Opn Drain Mode enable" "0,1" newline bitfld.long 0x188 0.--2. "MUX,EMMC2_DATA0 PAD Pin-mux func select" "0,1,2,3,4,5,6,7" line.long 0x18C "PIN_MUX_CONFIG_EMMC2_DATA1,PAD EMMC2_DATA1 pin-mux config register" bitfld.long 0x18C 12. "FV,EMMC2_DATA1 PAD Force Input Value when fin=0x2" "0,1" bitfld.long 0x18C 8.--9. "FIN,EMMC2_DATA1 PAD Force Input On/Off mode" "0,1,2,3" bitfld.long 0x18C 4. "ODE,EMMC2_DATA1 PAD Opn Drain Mode enable" "0,1" newline bitfld.long 0x18C 0.--2. "MUX,EMMC2_DATA1 PAD Pin-mux func select" "0,1,2,3,4,5,6,7" line.long 0x190 "PIN_MUX_CONFIG_EMMC2_DATA2,PAD EMMC2_DATA2 pin-mux config register" bitfld.long 0x190 12. "FV,EMMC2_DATA2 PAD Force Input Value when fin=0x2" "0,1" bitfld.long 0x190 8.--9. "FIN,EMMC2_DATA2 PAD Force Input On/Off mode" "0,1,2,3" bitfld.long 0x190 4. "ODE,EMMC2_DATA2 PAD Opn Drain Mode enable" "0,1" newline bitfld.long 0x190 0.--2. "MUX,EMMC2_DATA2 PAD Pin-mux func select" "0,1,2,3,4,5,6,7" line.long 0x194 "PIN_MUX_CONFIG_EMMC2_DATA3,PAD EMMC2_DATA3 pin-mux config register" bitfld.long 0x194 12. "FV,EMMC2_DATA3 PAD Force Input Value when fin=0x2" "0,1" bitfld.long 0x194 8.--9. "FIN,EMMC2_DATA3 PAD Force Input On/Off mode" "0,1,2,3" bitfld.long 0x194 4. "ODE,EMMC2_DATA3 PAD Opn Drain Mode enable" "0,1" newline bitfld.long 0x194 0.--2. "MUX,EMMC2_DATA3 PAD Pin-mux func select" "0,1,2,3,4,5,6,7" line.long 0x198 "PIN_MUX_CONFIG_EMMC2_DATA4,PAD EMMC2_DATA4 pin-mux config register" bitfld.long 0x198 12. "FV,EMMC2_DATA4 PAD Force Input Value when fin=0x2" "0,1" bitfld.long 0x198 8.--9. "FIN,EMMC2_DATA4 PAD Force Input On/Off mode" "0,1,2,3" bitfld.long 0x198 4. "ODE,EMMC2_DATA4 PAD Opn Drain Mode enable" "0,1" newline bitfld.long 0x198 0.--2. "MUX,EMMC2_DATA4 PAD Pin-mux func select" "0,1,2,3,4,5,6,7" line.long 0x19C "PIN_MUX_CONFIG_EMMC2_DATA5,PAD EMMC2_DATA5 pin-mux config register" bitfld.long 0x19C 12. "FV,EMMC2_DATA5 PAD Force Input Value when fin=0x2" "0,1" bitfld.long 0x19C 8.--9. "FIN,EMMC2_DATA5 PAD Force Input On/Off mode" "0,1,2,3" bitfld.long 0x19C 4. "ODE,EMMC2_DATA5 PAD Opn Drain Mode enable" "0,1" newline bitfld.long 0x19C 0.--2. "MUX,EMMC2_DATA5 PAD Pin-mux func select" "0,1,2,3,4,5,6,7" line.long 0x1A0 "PIN_MUX_CONFIG_EMMC2_DATA6,PAD EMMC2_DATA6 pin-mux config register" bitfld.long 0x1A0 12. "FV,EMMC2_DATA6 PAD Force Input Value when fin=0x2" "0,1" bitfld.long 0x1A0 8.--9. "FIN,EMMC2_DATA6 PAD Force Input On/Off mode" "0,1,2,3" bitfld.long 0x1A0 4. "ODE,EMMC2_DATA6 PAD Opn Drain Mode enable" "0,1" newline bitfld.long 0x1A0 0.--2. "MUX,EMMC2_DATA6 PAD Pin-mux func select" "0,1,2,3,4,5,6,7" line.long 0x1A4 "PIN_MUX_CONFIG_EMMC2_DATA7,PAD EMMC2_DATA7 pin-mux config register" bitfld.long 0x1A4 12. "FV,EMMC2_DATA7 PAD Force Input Value when fin=0x2" "0,1" bitfld.long 0x1A4 8.--9. "FIN,EMMC2_DATA7 PAD Force Input On/Off mode" "0,1,2,3" bitfld.long 0x1A4 4. "ODE,EMMC2_DATA7 PAD Opn Drain Mode enable" "0,1" newline bitfld.long 0x1A4 0.--2. "MUX,EMMC2_DATA7 PAD Pin-mux func select" "0,1,2,3,4,5,6,7" line.long 0x1A8 "PIN_MUX_CONFIG_EMMC2_STROBE,PAD EMMC2_STROBE pin-mux config register" bitfld.long 0x1A8 12. "FV,EMMC2_STROBE PAD Force Input Value when fin=0x2" "0,1" bitfld.long 0x1A8 8.--9. "FIN,EMMC2_STROBE PAD Force Input On/Off mode" "0,1,2,3" bitfld.long 0x1A8 4. "ODE,EMMC2_STROBE PAD Opn Drain Mode enable" "0,1" newline bitfld.long 0x1A8 0.--2. "MUX,EMMC2_STROBE PAD Pin-mux func select" "0,1,2,3,4,5,6,7" line.long 0x1AC "PIN_MUX_CONFIG_EMMC2_RESET_N,PAD EMMC2_RESET_N pin-mux config register" bitfld.long 0x1AC 12. "FV,EMMC2_RESET_N PAD Force Input Value when fin=0x2" "0,1" bitfld.long 0x1AC 8.--9. "FIN,EMMC2_RESET_N PAD Force Input On/Off mode" "0,1,2,3" bitfld.long 0x1AC 4. "ODE,EMMC2_RESET_N PAD Opn Drain Mode enable" "0,1" newline bitfld.long 0x1AC 0.--2. "MUX,EMMC2_RESET_N PAD Pin-mux func select" "0,1,2,3,4,5,6,7" group.long 0x400++0x19B line.long 0x0 "INPUT_SOURCE_SELECT_I2C5_SCL,I2C5_SCL input source select register" bitfld.long 0x0 0. "SRC_SEL,source select" "0,1" line.long 0x4 "INPUT_SOURCE_SELECT_SPI6_SCLK,SPI6_SCLK input source select register" bitfld.long 0x4 0. "SRC_SEL,source select" "0,1" line.long 0x8 "INPUT_SOURCE_SELECT_MSHC4_CARD_DET_N,MSHC4_CARD_DET_N input source select register" bitfld.long 0x8 0. "SRC_SEL,source select" "0,1" line.long 0xC "INPUT_SOURCE_SELECT_I2C5_SDA,I2C5_SDA input source select register" bitfld.long 0xC 0. "SRC_SEL,source select" "0,1" line.long 0x10 "INPUT_SOURCE_SELECT_SPI6_MISO,SPI6_MISO input source select register" bitfld.long 0x10 0. "SRC_SEL,source select" "0,1" line.long 0x14 "INPUT_SOURCE_SELECT_CANFD5_RX,CANFD5_RX input source select register" bitfld.long 0x14 0.--1. "SRC_SEL,source select" "0,1,2,3" line.long 0x18 "INPUT_SOURCE_SELECT_MSHC4_WP,MSHC4_WP input source select register" bitfld.long 0x18 0. "SRC_SEL,source select" "0,1" line.long 0x1C "INPUT_SOURCE_SELECT_USB_SS_USB1_OC,USB_SS_USB1_OC input source select register" bitfld.long 0x1C 0.--2. "SRC_SEL,source select" "0,1,2,3,4,5,6,7" line.long 0x20 "INPUT_SOURCE_SELECT_I2C6_SCL,I2C6_SCL input source select register" bitfld.long 0x20 0. "SRC_SEL,source select" "0,1" line.long 0x24 "INPUT_SOURCE_SELECT_SPI6_MOSI,SPI6_MOSI input source select register" bitfld.long 0x24 0. "SRC_SEL,source select" "0,1" line.long 0x28 "INPUT_SOURCE_SELECT_I2C6_SDA,I2C6_SDA input source select register" bitfld.long 0x28 0. "SRC_SEL,source select" "0,1" line.long 0x2C "INPUT_SOURCE_SELECT_SPI6_SS,SPI6_SS input source select register" bitfld.long 0x2C 0. "SRC_SEL,source select" "0,1" line.long 0x30 "INPUT_SOURCE_SELECT_CANFD6_RX,CANFD6_RX input source select register" bitfld.long 0x30 0.--1. "SRC_SEL,source select" "0,1,2,3" line.long 0x34 "INPUT_SOURCE_SELECT_USB_SS_USB2_OC,USB_SS_USB2_OC input source select register" bitfld.long 0x34 0.--2. "SRC_SEL,source select" "0,1,2,3,4,5,6,7" line.long 0x38 "INPUT_SOURCE_SELECT_I2C7_SCL,I2C7_SCL input source select register" bitfld.long 0x38 0.--1. "SRC_SEL,source select" "0,1,2,3" line.long 0x3C "INPUT_SOURCE_SELECT_MSHC3_CARD_DET_N,MSHC3_CARD_DET_N input source select register" bitfld.long 0x3C 0. "SRC_SEL,source select" "0,1" line.long 0x40 "INPUT_SOURCE_SELECT_PCIE_SS_PCIEX2_CLKREQ_N,PCIE_SS_PCIEX2_CLKREQ_N input source select register" bitfld.long 0x40 0.--1. "SRC_SEL,source select" "0,1,2,3" line.long 0x44 "INPUT_SOURCE_SELECT_I2C7_SDA,I2C7_SDA input source select register" bitfld.long 0x44 0.--1. "SRC_SEL,source select" "0,1,2,3" line.long 0x48 "INPUT_SOURCE_SELECT_MSHC3_WP,MSHC3_WP input source select register" bitfld.long 0x48 0. "SRC_SEL,source select" "0,1" line.long 0x4C "INPUT_SOURCE_SELECT_PCIE_SS_PCIEX1_CLKREQ_N,PCIE_SS_PCIEX1_CLKREQ_N input source select register" bitfld.long 0x4C 0.--1. "SRC_SEL,source select" "0,1,2,3" line.long 0x50 "INPUT_SOURCE_SELECT_I2C8_SCL,I2C8_SCL input source select register" bitfld.long 0x50 0.--1. "SRC_SEL,source select" "0,1,2,3" line.long 0x54 "INPUT_SOURCE_SELECT_ENET2_MDIO,ENET2_MDIO input source select register" bitfld.long 0x54 0.--2. "SRC_SEL,source select" "0,1,2,3,4,5,6,7" line.long 0x58 "INPUT_SOURCE_SELECT_MSHC3_VOLT_SW,MSHC3_VOLT_SW input source select register" bitfld.long 0x58 0. "SRC_SEL,source select" "0,1" line.long 0x5C "INPUT_SOURCE_SELECT_I2C8_SDA,I2C8_SDA input source select register" bitfld.long 0x5C 0.--1. "SRC_SEL,source select" "0,1,2,3" line.long 0x60 "INPUT_SOURCE_SELECT_SPI5_SCLK,SPI5_SCLK input source select register" bitfld.long 0x60 0.--1. "SRC_SEL,source select" "0,1,2,3" line.long 0x64 "INPUT_SOURCE_SELECT_SPI5_MISO,SPI5_MISO input source select register" bitfld.long 0x64 0.--1. "SRC_SEL,source select" "0,1,2,3" line.long 0x68 "INPUT_SOURCE_SELECT_UART11_RX,UART11_RX input source select register" bitfld.long 0x68 0.--1. "SRC_SEL,source select" "0,1,2,3" line.long 0x6C "INPUT_SOURCE_SELECT_SPI5_MOSI,SPI5_MOSI input source select register" bitfld.long 0x6C 0.--1. "SRC_SEL,source select" "0,1,2,3" line.long 0x70 "INPUT_SOURCE_SELECT_SPI5_SS,SPI5_SS input source select register" bitfld.long 0x70 0.--1. "SRC_SEL,source select" "0,1,2,3" line.long 0x74 "INPUT_SOURCE_SELECT_UART12_RX,UART12_RX input source select register" bitfld.long 0x74 0. "SRC_SEL,source select" "0,1" line.long 0x78 "INPUT_SOURCE_SELECT_I2C13_SCL,I2C13_SCL input source select register" bitfld.long 0x78 0.--1. "SRC_SEL,source select" "0,1,2,3" line.long 0x7C "INPUT_SOURCE_SELECT_PCIE_SS_PCIEX1_PERST_N,PCIE_SS_PCIEX1_PERST_N input source select register" bitfld.long 0x7C 0.--1. "SRC_SEL,source select" "0,1,2,3" line.long 0x80 "INPUT_SOURCE_SELECT_I2C13_SDA,I2C13_SDA input source select register" bitfld.long 0x80 0.--1. "SRC_SEL,source select" "0,1,2,3" line.long 0x84 "INPUT_SOURCE_SELECT_CANFD7_RX,CANFD7_RX input source select register" bitfld.long 0x84 0.--1. "SRC_SEL,source select" "0,1,2,3" line.long 0x88 "INPUT_SOURCE_SELECT_PCIE_SS_PCIEX1_WAKE_N,PCIE_SS_PCIEX1_WAKE_N input source select register" bitfld.long 0x88 0.--1. "SRC_SEL,source select" "0,1,2,3" line.long 0x8C "INPUT_SOURCE_SELECT_I2C14_SCL,I2C14_SCL input source select register" bitfld.long 0x8C 0.--1. "SRC_SEL,source select" "0,1,2,3" line.long 0x90 "INPUT_SOURCE_SELECT_PCIE_SS_PCIEX2_PERST_N,PCIE_SS_PCIEX2_PERST_N input source select register" bitfld.long 0x90 0.--1. "SRC_SEL,source select" "0,1,2,3" line.long 0x94 "INPUT_SOURCE_SELECT_I2C14_SDA,I2C14_SDA input source select register" bitfld.long 0x94 0.--1. "SRC_SEL,source select" "0,1,2,3" line.long 0x98 "INPUT_SOURCE_SELECT_CANFD8_RX,CANFD8_RX input source select register" bitfld.long 0x98 0.--1. "SRC_SEL,source select" "0,1,2,3" line.long 0x9C "INPUT_SOURCE_SELECT_PCIE_SS_PCIEX2_WAKE_N,PCIE_SS_PCIEX2_WAKE_N input source select register" bitfld.long 0x9C 0.--1. "SRC_SEL,source select" "0,1,2,3" line.long 0xA0 "INPUT_SOURCE_SELECT_SPI8_SCLK,SPI8_SCLK input source select register" bitfld.long 0xA0 0.--1. "SRC_SEL,source select" "0,1,2,3" line.long 0xA4 "INPUT_SOURCE_SELECT_SPI8_MISO,SPI8_MISO input source select register" bitfld.long 0xA4 0.--1. "SRC_SEL,source select" "0,1,2,3" line.long 0xA8 "INPUT_SOURCE_SELECT_SPI8_MOSI,SPI8_MOSI input source select register" bitfld.long 0xA8 0.--1. "SRC_SEL,source select" "0,1,2,3" line.long 0xAC "INPUT_SOURCE_SELECT_SPDIF3_IN,SPDIF3_IN input source select register" bitfld.long 0xAC 0. "SRC_SEL,source select" "0,1" line.long 0xB0 "INPUT_SOURCE_SELECT_SPI8_SS,SPI8_SS input source select register" bitfld.long 0xB0 0.--1. "SRC_SEL,source select" "0,1,2,3" line.long 0xB4 "INPUT_SOURCE_SELECT_UART13_RX,UART13_RX input source select register" bitfld.long 0xB4 0.--1. "SRC_SEL,source select" "0,1,2,3" line.long 0xB8 "INPUT_SOURCE_SELECT_UART14_CTS,UART14_CTS input source select register" bitfld.long 0xB8 0. "SRC_SEL,source select" "0,1" line.long 0xBC "INPUT_SOURCE_SELECT_I2C12_SCL,I2C12_SCL input source select register" bitfld.long 0xBC 0. "SRC_SEL,source select" "0,1" line.long 0xC0 "INPUT_SOURCE_SELECT_SPDIF4_IN,SPDIF4_IN input source select register" bitfld.long 0xC0 0. "SRC_SEL,source select" "0,1" line.long 0xC4 "INPUT_SOURCE_SELECT_UART14_RX,UART14_RX input source select register" bitfld.long 0xC4 0. "SRC_SEL,source select" "0,1" line.long 0xC8 "INPUT_SOURCE_SELECT_I2C12_SDA,I2C12_SDA input source select register" bitfld.long 0xC8 0. "SRC_SEL,source select" "0,1" line.long 0xCC "INPUT_SOURCE_SELECT_SPI7_SCLK,SPI7_SCLK input source select register" bitfld.long 0xCC 0. "SRC_SEL,source select" "0,1" line.long 0xD0 "INPUT_SOURCE_SELECT_SPI7_MISO,SPI7_MISO input source select register" bitfld.long 0xD0 0. "SRC_SEL,source select" "0,1" line.long 0xD4 "INPUT_SOURCE_SELECT_UART15_RX,UART15_RX input source select register" bitfld.long 0xD4 0.--1. "SRC_SEL,source select" "0,1,2,3" line.long 0xD8 "INPUT_SOURCE_SELECT_UART16_CTS,UART16_CTS input source select register" bitfld.long 0xD8 0.--1. "SRC_SEL,source select" "0,1,2,3" line.long 0xDC "INPUT_SOURCE_SELECT_SPI7_MOSI,SPI7_MOSI input source select register" bitfld.long 0xDC 0. "SRC_SEL,source select" "0,1" line.long 0xE0 "INPUT_SOURCE_SELECT_TIMER6_CH2,TIMER6_CH2 input source select register" bitfld.long 0xE0 0. "SRC_SEL,source select" "0,1" line.long 0xE4 "INPUT_SOURCE_SELECT_SPI7_SS,SPI7_SS input source select register" bitfld.long 0xE4 0. "SRC_SEL,source select" "0,1" line.long 0xE8 "INPUT_SOURCE_SELECT_UART16_RX,UART16_RX input source select register" bitfld.long 0xE8 0.--1. "SRC_SEL,source select" "0,1,2,3" line.long 0xEC "INPUT_SOURCE_SELECT_TIMER6_CH3,TIMER6_CH3 input source select register" bitfld.long 0xEC 0. "SRC_SEL,source select" "0,1" line.long 0xF0 "INPUT_SOURCE_SELECT_I2C15_SCL,I2C15_SCL input source select register" bitfld.long 0xF0 0.--1. "SRC_SEL,source select" "0,1,2,3" line.long 0xF4 "INPUT_SOURCE_SELECT_I2C15_SDA,I2C15_SDA input source select register" bitfld.long 0xF4 0.--1. "SRC_SEL,source select" "0,1,2,3" line.long 0xF8 "INPUT_SOURCE_SELECT_I2C16_SCL,I2C16_SCL input source select register" bitfld.long 0xF8 0.--1. "SRC_SEL,source select" "0,1,2,3" line.long 0xFC "INPUT_SOURCE_SELECT_I2C16_SDA,I2C16_SDA input source select register" bitfld.long 0xFC 0.--1. "SRC_SEL,source select" "0,1,2,3" line.long 0x100 "INPUT_SOURCE_SELECT_I2S_MC2_SCKO,I2S_MC2_SCKO input source select register" bitfld.long 0x100 0.--1. "SRC_SEL,source select" "0,1,2,3" line.long 0x104 "INPUT_SOURCE_SELECT_I2S_MC2_WSO,I2S_MC2_WSO input source select register" bitfld.long 0x104 0.--1. "SRC_SEL,source select" "0,1,2,3" line.long 0x108 "INPUT_SOURCE_SELECT_I2S_MC2_SDI0_SDO0,I2S_MC2_SDI0_SDO0 input source select register" bitfld.long 0x108 0.--1. "SRC_SEL,source select" "0,1,2,3" line.long 0x10C "INPUT_SOURCE_SELECT_I2S_MC2_SDI1_SDO1,I2S_MC2_SDI1_SDO1 input source select register" bitfld.long 0x10C 0.--1. "SRC_SEL,source select" "0,1,2,3" line.long 0x110 "INPUT_SOURCE_SELECT_I2S_MC2_SDI2_SDO2,I2S_MC2_SDI2_SDO2 input source select register" bitfld.long 0x110 0.--1. "SRC_SEL,source select" "0,1,2,3" line.long 0x114 "INPUT_SOURCE_SELECT_I2S_MC2_SDI3_SDO3,I2S_MC2_SDI3_SDO3 input source select register" bitfld.long 0x114 0.--1. "SRC_SEL,source select" "0,1,2,3" line.long 0x118 "INPUT_SOURCE_SELECT_I2S_MC2_SDI4_SDO4,I2S_MC2_SDI4_SDO4 input source select register" bitfld.long 0x118 0.--1. "SRC_SEL,source select" "0,1,2,3" line.long 0x11C "INPUT_SOURCE_SELECT_I2S_MC2_SDI5_SDO5,I2S_MC2_SDI5_SDO5 input source select register" bitfld.long 0x11C 0.--1. "SRC_SEL,source select" "0,1,2,3" line.long 0x120 "INPUT_SOURCE_SELECT_I2S_MC2_SDI6_SDO6,I2S_MC2_SDI6_SDO6 input source select register" bitfld.long 0x120 0.--1. "SRC_SEL,source select" "0,1,2,3" line.long 0x124 "INPUT_SOURCE_SELECT_I2S_MC2_SDI7_SDO7,I2S_MC2_SDI7_SDO7 input source select register" bitfld.long 0x124 0.--1. "SRC_SEL,source select" "0,1,2,3" line.long 0x128 "INPUT_SOURCE_SELECT_OSPI2_DQS,OSPI2_DQS input source select register" bitfld.long 0x128 0. "SRC_SEL,source select" "0,1" line.long 0x12C "INPUT_SOURCE_SELECT_I2S_MC2_WSI,I2S_MC2_WSI input source select register" bitfld.long 0x12C 0.--1. "SRC_SEL,source select" "0,1,2,3" line.long 0x130 "INPUT_SOURCE_SELECT_I2S_MC2_SCKI,I2S_MC2_SCKI input source select register" bitfld.long 0x130 0.--1. "SRC_SEL,source select" "0,1,2,3" line.long 0x134 "INPUT_SOURCE_SELECT_I2S_SC3_SCK,I2S_SC3_SCK input source select register" bitfld.long 0x134 0. "SRC_SEL,source select" "0,1" line.long 0x138 "INPUT_SOURCE_SELECT_I2S_SC3_WS,I2S_SC3_WS input source select register" bitfld.long 0x138 0. "SRC_SEL,source select" "0,1" line.long 0x13C "INPUT_SOURCE_SELECT_I2S_SC3_SDI_SDO,I2S_SC3_SDI_SDO input source select register" bitfld.long 0x13C 0.--1. "SRC_SEL,source select" "0,1,2,3" line.long 0x140 "INPUT_SOURCE_SELECT_I2S_SC4_SCK,I2S_SC4_SCK input source select register" bitfld.long 0x140 0. "SRC_SEL,source select" "0,1" line.long 0x144 "INPUT_SOURCE_SELECT_I2S_SC4_WS,I2S_SC4_WS input source select register" bitfld.long 0x144 0. "SRC_SEL,source select" "0,1" line.long 0x148 "INPUT_SOURCE_SELECT_I2S_SC4_SDI_SDO,I2S_SC4_SDI_SDO input source select register" bitfld.long 0x148 0.--1. "SRC_SEL,source select" "0,1,2,3" line.long 0x14C "INPUT_SOURCE_SELECT_I2S_SC6_SDI_SDO,I2S_SC6_SDI_SDO input source select register" bitfld.long 0x14C 0. "SRC_SEL,source select" "0,1" line.long 0x150 "INPUT_SOURCE_SELECT_I2S_SC5_SDI_SDO,I2S_SC5_SDI_SDO input source select register" bitfld.long 0x150 0. "SRC_SEL,source select" "0,1" line.long 0x154 "INPUT_SOURCE_SELECT_I2S_SC7_SCK,I2S_SC7_SCK input source select register" bitfld.long 0x154 0. "SRC_SEL,source select" "0,1" line.long 0x158 "INPUT_SOURCE_SELECT_I2S_MC1_SCKO,I2S_MC1_SCKO input source select register" bitfld.long 0x158 0.--1. "SRC_SEL,source select" "0,1,2,3" line.long 0x15C "INPUT_SOURCE_SELECT_I2S_SC7_WS,I2S_SC7_WS input source select register" bitfld.long 0x15C 0. "SRC_SEL,source select" "0,1" line.long 0x160 "INPUT_SOURCE_SELECT_I2S_MC1_WSO,I2S_MC1_WSO input source select register" bitfld.long 0x160 0.--1. "SRC_SEL,source select" "0,1,2,3" line.long 0x164 "INPUT_SOURCE_SELECT_I2S_SC8_SDI_SDO,I2S_SC8_SDI_SDO input source select register" bitfld.long 0x164 0.--2. "SRC_SEL,source select" "0,1,2,3,4,5,6,7" line.long 0x168 "INPUT_SOURCE_SELECT_I2S_MC1_SDI4_SDO4,I2S_MC1_SDI4_SDO4 input source select register" bitfld.long 0x168 0.--1. "SRC_SEL,source select" "0,1,2,3" line.long 0x16C "INPUT_SOURCE_SELECT_I2S_SC8_SCK,I2S_SC8_SCK input source select register" bitfld.long 0x16C 0.--1. "SRC_SEL,source select" "0,1,2,3" line.long 0x170 "INPUT_SOURCE_SELECT_I2S_MC1_SDI5_SDO5,I2S_MC1_SDI5_SDO5 input source select register" bitfld.long 0x170 0.--1. "SRC_SEL,source select" "0,1,2,3" line.long 0x174 "INPUT_SOURCE_SELECT_I2S_SC8_WS,I2S_SC8_WS input source select register" bitfld.long 0x174 0.--1. "SRC_SEL,source select" "0,1,2,3" line.long 0x178 "INPUT_SOURCE_SELECT_I2S_MC1_SDI6_SDO6,I2S_MC1_SDI6_SDO6 input source select register" bitfld.long 0x178 0.--1. "SRC_SEL,source select" "0,1,2,3" line.long 0x17C "INPUT_SOURCE_SELECT_I2S_SC7_SDI_SDO,I2S_SC7_SDI_SDO input source select register" bitfld.long 0x17C 0.--1. "SRC_SEL,source select" "0,1,2,3" line.long 0x180 "INPUT_SOURCE_SELECT_I2S_MC1_SDI7_SDO7,I2S_MC1_SDI7_SDO7 input source select register" bitfld.long 0x180 0.--1. "SRC_SEL,source select" "0,1,2,3" line.long 0x184 "INPUT_SOURCE_SELECT_I2S_MC1_SCKI,I2S_MC1_SCKI input source select register" bitfld.long 0x184 0.--1. "SRC_SEL,source select" "0,1,2,3" line.long 0x188 "INPUT_SOURCE_SELECT_I2S_MC1_WSI,I2S_MC1_WSI input source select register" bitfld.long 0x188 0.--1. "SRC_SEL,source select" "0,1,2,3" line.long 0x18C "INPUT_SOURCE_SELECT_I2S_MC1_SDI0_SDO0,I2S_MC1_SDI0_SDO0 input source select register" bitfld.long 0x18C 0. "SRC_SEL,source select" "0,1" line.long 0x190 "INPUT_SOURCE_SELECT_I2S_MC1_SDI1_SDO1,I2S_MC1_SDI1_SDO1 input source select register" bitfld.long 0x190 0. "SRC_SEL,source select" "0,1" line.long 0x194 "INPUT_SOURCE_SELECT_I2S_MC1_SDI2_SDO2,I2S_MC1_SDI2_SDO2 input source select register" bitfld.long 0x194 0. "SRC_SEL,source select" "0,1" line.long 0x198 "INPUT_SOURCE_SELECT_I2S_MC1_SDI3_SDO3,I2S_MC1_SDI3_SDO3 input source select register" bitfld.long 0x198 0. "SRC_SEL,source select" "0,1" tree.end tree "PINCTRL_RTC" base ad:0x31860000 group.long 0x0++0x2F line.long 0x0 "IO_PAD_CONFIG_SYS_MODE0,PAD SYS_MODE0 config register" bitfld.long 0x0 16. "POE,SYS_MODE0 PAD Parametric output enable" "0,1" bitfld.long 0x0 12. "IS,SYS_MODE0 PAD Input select" "0,1" line.long 0x4 "IO_PAD_CONFIG_SYS_MODE1,PAD SYS_MODE1 config register" bitfld.long 0x4 16. "POE,SYS_MODE1 PAD Parametric output enable" "0,1" bitfld.long 0x4 12. "IS,SYS_MODE1 PAD Input select" "0,1" line.long 0x8 "IO_PAD_CONFIG_SYS_RESET_N,PAD SYS_RESET_N config register" bitfld.long 0x8 16. "POE,SYS_RESET_N PAD Parametric output enable" "0,1" bitfld.long 0x8 12. "IS,SYS_RESET_N PAD Input select" "0,1" line.long 0xC "IO_PAD_CONFIG_AP_RESET_N,PAD AP_RESET_N config register" bitfld.long 0xC 16. "POE,AP_RESET_N PAD Parametric output enable" "0,1" bitfld.long 0xC 12. "IS,AP_RESET_N PAD Input select" "0,1" line.long 0x10 "IO_PAD_CONFIG_RTC_RESET_N,PAD RTC_RESET_N config register" bitfld.long 0x10 16. "POE,RTC_RESET_N PAD Parametric output enable" "0,1" bitfld.long 0x10 12. "IS,RTC_RESET_N PAD Input select" "0,1" line.long 0x14 "IO_PAD_CONFIG_SYS_PWR_ON,PAD SYS_PWR_ON config register" bitfld.long 0x14 16. "POE,SYS_PWR_ON PAD Parametric output enable" "0,1" bitfld.long 0x14 12. "IS,SYS_PWR_ON PAD Input select" "0,1" bitfld.long 0x14 8. "SR,SYS_PWR_ON PAD Slew rate" "0,1" bitfld.long 0x14 4.--5. "DS,SYS_PWR_ON PAD Driver select" "0,1,2,3" newline bitfld.long 0x14 1. "PS,SYS_PWR_ON PAD Pull select" "0,1" bitfld.long 0x14 0. "PE,SYS_PWR_ON PAD Pull enable" "0,1" line.long 0x18 "IO_PAD_CONFIG_SYS_WAKEUP0,PAD SYS_WAKEUP0 config register" bitfld.long 0x18 16. "POE,SYS_WAKEUP0 PAD Parametric output enable" "0,1" bitfld.long 0x18 12. "IS,SYS_WAKEUP0 PAD Input select" "0,1" bitfld.long 0x18 8. "SR,SYS_WAKEUP0 PAD Slew rate" "0,1" bitfld.long 0x18 4.--5. "DS,SYS_WAKEUP0 PAD Driver select" "0,1,2,3" newline bitfld.long 0x18 1. "PS,SYS_WAKEUP0 PAD Pull select" "0,1" bitfld.long 0x18 0. "PE,SYS_WAKEUP0 PAD Pull enable" "0,1" line.long 0x1C "IO_PAD_CONFIG_SYS_WAKEUP1,PAD SYS_WAKEUP1 config register" bitfld.long 0x1C 16. "POE,SYS_WAKEUP1 PAD Parametric output enable" "0,1" bitfld.long 0x1C 12. "IS,SYS_WAKEUP1 PAD Input select" "0,1" bitfld.long 0x1C 8. "SR,SYS_WAKEUP1 PAD Slew rate" "0,1" bitfld.long 0x1C 4.--5. "DS,SYS_WAKEUP1 PAD Driver select" "0,1,2,3" newline bitfld.long 0x1C 1. "PS,SYS_WAKEUP1 PAD Pull select" "0,1" bitfld.long 0x1C 0. "PE,SYS_WAKEUP1 PAD Pull enable" "0,1" line.long 0x20 "IO_PAD_CONFIG_SYS_CTRL0,PAD SYS_CTRL0 config register" bitfld.long 0x20 16. "POE,SYS_CTRL0 PAD Parametric output enable" "0,1" bitfld.long 0x20 12. "IS,SYS_CTRL0 PAD Input select" "0,1" bitfld.long 0x20 8. "SR,SYS_CTRL0 PAD Slew rate" "0,1" bitfld.long 0x20 4.--5. "DS,SYS_CTRL0 PAD Driver select" "0,1,2,3" newline bitfld.long 0x20 1. "PS,SYS_CTRL0 PAD Pull select" "0,1" bitfld.long 0x20 0. "PE,SYS_CTRL0 PAD Pull enable" "0,1" line.long 0x24 "IO_PAD_CONFIG_SYS_CTRL1,PAD SYS_CTRL1 config register" bitfld.long 0x24 16. "POE,SYS_CTRL1 PAD Parametric output enable" "0,1" bitfld.long 0x24 12. "IS,SYS_CTRL1 PAD Input select" "0,1" bitfld.long 0x24 8. "SR,SYS_CTRL1 PAD Slew rate" "0,1" bitfld.long 0x24 4.--5. "DS,SYS_CTRL1 PAD Driver select" "0,1,2,3" newline bitfld.long 0x24 1. "PS,SYS_CTRL1 PAD Pull select" "0,1" bitfld.long 0x24 0. "PE,SYS_CTRL1 PAD Pull enable" "0,1" line.long 0x28 "IO_PAD_CONFIG_SYS_CTRL2,PAD SYS_CTRL2 config register" bitfld.long 0x28 16. "POE,SYS_CTRL2 PAD Parametric output enable" "0,1" bitfld.long 0x28 12. "IS,SYS_CTRL2 PAD Input select" "0,1" bitfld.long 0x28 8. "SR,SYS_CTRL2 PAD Slew rate" "0,1" bitfld.long 0x28 4.--5. "DS,SYS_CTRL2 PAD Driver select" "0,1,2,3" newline bitfld.long 0x28 1. "PS,SYS_CTRL2 PAD Pull select" "0,1" bitfld.long 0x28 0. "PE,SYS_CTRL2 PAD Pull enable" "0,1" line.long 0x2C "IO_PAD_CONFIG_SYS_CTRL3,PAD SYS_CTRL3 config register" bitfld.long 0x2C 16. "POE,SYS_CTRL3 PAD Parametric output enable" "0,1" bitfld.long 0x2C 12. "IS,SYS_CTRL3 PAD Input select" "0,1" bitfld.long 0x2C 8. "SR,SYS_CTRL3 PAD Slew rate" "0,1" bitfld.long 0x2C 4.--5. "DS,SYS_CTRL3 PAD Driver select" "0,1,2,3" newline bitfld.long 0x2C 1. "PS,SYS_CTRL3 PAD Pull select" "0,1" bitfld.long 0x2C 0. "PE,SYS_CTRL3 PAD Pull enable" "0,1" group.long 0x200++0x2B line.long 0x0 "PIN_MUX_CONFIG_SYS_MODE0,PAD SYS_MODE0 pin-mux config register" bitfld.long 0x0 12. "FV,SYS_MODE0 PAD Force Input Value when fin=0x2" "0,1" bitfld.long 0x0 8.--9. "FIN,SYS_MODE0 PAD Force Input On/Off mode" "0,1,2,3" bitfld.long 0x0 4. "ODE,SYS_MODE0 PAD Opn Drain Mode enable" "0,1" bitfld.long 0x0 0.--2. "MUX,SYS_MODE0 PAD Pin-mux func select" "0,1,2,3,4,5,6,7" line.long 0x4 "PIN_MUX_CONFIG_SYS_MODE1,PAD SYS_MODE1 pin-mux config register" bitfld.long 0x4 12. "FV,SYS_MODE1 PAD Force Input Value when fin=0x2" "0,1" bitfld.long 0x4 8.--9. "FIN,SYS_MODE1 PAD Force Input On/Off mode" "0,1,2,3" bitfld.long 0x4 4. "ODE,SYS_MODE1 PAD Opn Drain Mode enable" "0,1" bitfld.long 0x4 0.--2. "MUX,SYS_MODE1 PAD Pin-mux func select" "0,1,2,3,4,5,6,7" line.long 0x8 "PIN_MUX_CONFIG_SYS_RESET_N,PAD SYS_RESET_N pin-mux config register" bitfld.long 0x8 12. "FV,SYS_RESET_N PAD Force Input Value when fin=0x2" "0,1" bitfld.long 0x8 8.--9. "FIN,SYS_RESET_N PAD Force Input On/Off mode" "0,1,2,3" bitfld.long 0x8 4. "ODE,SYS_RESET_N PAD Opn Drain Mode enable" "0,1" bitfld.long 0x8 0.--2. "MUX,SYS_RESET_N PAD Pin-mux func select" "0,1,2,3,4,5,6,7" line.long 0xC "PIN_MUX_CONFIG_AP_RESET_N,PAD AP_RESET_N pin-mux config register" bitfld.long 0xC 12. "FV,AP_RESET_N PAD Force Input Value when fin=0x2" "0,1" bitfld.long 0xC 8.--9. "FIN,AP_RESET_N PAD Force Input On/Off mode" "0,1,2,3" bitfld.long 0xC 4. "ODE,AP_RESET_N PAD Opn Drain Mode enable" "0,1" bitfld.long 0xC 0.--2. "MUX,AP_RESET_N PAD Pin-mux func select" "0,1,2,3,4,5,6,7" line.long 0x10 "PIN_MUX_CONFIG_RTC_RESET_N,PAD RTC_RESET_N pin-mux config register" bitfld.long 0x10 12. "FV,RTC_RESET_N PAD Force Input Value when fin=0x2" "0,1" bitfld.long 0x10 8.--9. "FIN,RTC_RESET_N PAD Force Input On/Off mode" "0,1,2,3" bitfld.long 0x10 4. "ODE,RTC_RESET_N PAD Opn Drain Mode enable" "0,1" bitfld.long 0x10 0.--2. "MUX,RTC_RESET_N PAD Pin-mux func select" "0,1,2,3,4,5,6,7" line.long 0x14 "PIN_MUX_CONFIG_SYS_WAKEUP0,PAD SYS_WAKEUP0 pin-mux config register" bitfld.long 0x14 12. "FV,SYS_WAKEUP0 PAD Force Input Value when fin=0x2" "0,1" bitfld.long 0x14 8.--9. "FIN,SYS_WAKEUP0 PAD Force Input On/Off mode" "0,1,2,3" bitfld.long 0x14 4. "ODE,SYS_WAKEUP0 PAD Opn Drain Mode enable" "0,1" bitfld.long 0x14 0.--2. "MUX,SYS_WAKEUP0 PAD Pin-mux func select" "0,1,2,3,4,5,6,7" line.long 0x18 "PIN_MUX_CONFIG_SYS_WAKEUP1,PAD SYS_WAKEUP1 pin-mux config register" bitfld.long 0x18 12. "FV,SYS_WAKEUP1 PAD Force Input Value when fin=0x2" "0,1" bitfld.long 0x18 8.--9. "FIN,SYS_WAKEUP1 PAD Force Input On/Off mode" "0,1,2,3" bitfld.long 0x18 4. "ODE,SYS_WAKEUP1 PAD Opn Drain Mode enable" "0,1" bitfld.long 0x18 0.--2. "MUX,SYS_WAKEUP1 PAD Pin-mux func select" "0,1,2,3,4,5,6,7" line.long 0x1C "PIN_MUX_CONFIG_SYS_CTRL0,PAD SYS_CTRL0 pin-mux config register" bitfld.long 0x1C 12. "FV,SYS_CTRL0 PAD Force Input Value when fin=0x2" "0,1" bitfld.long 0x1C 8.--9. "FIN,SYS_CTRL0 PAD Force Input On/Off mode" "0,1,2,3" bitfld.long 0x1C 4. "ODE,SYS_CTRL0 PAD Opn Drain Mode enable" "0,1" bitfld.long 0x1C 0.--2. "MUX,SYS_CTRL0 PAD Pin-mux func select" "0,1,2,3,4,5,6,7" line.long 0x20 "PIN_MUX_CONFIG_SYS_CTRL1,PAD SYS_CTRL1 pin-mux config register" bitfld.long 0x20 12. "FV,SYS_CTRL1 PAD Force Input Value when fin=0x2" "0,1" bitfld.long 0x20 8.--9. "FIN,SYS_CTRL1 PAD Force Input On/Off mode" "0,1,2,3" bitfld.long 0x20 4. "ODE,SYS_CTRL1 PAD Opn Drain Mode enable" "0,1" bitfld.long 0x20 0.--2. "MUX,SYS_CTRL1 PAD Pin-mux func select" "0,1,2,3,4,5,6,7" line.long 0x24 "PIN_MUX_CONFIG_SYS_CTRL2,PAD SYS_CTRL2 pin-mux config register" bitfld.long 0x24 12. "FV,SYS_CTRL2 PAD Force Input Value when fin=0x2" "0,1" bitfld.long 0x24 8.--9. "FIN,SYS_CTRL2 PAD Force Input On/Off mode" "0,1,2,3" bitfld.long 0x24 4. "ODE,SYS_CTRL2 PAD Opn Drain Mode enable" "0,1" bitfld.long 0x24 0.--2. "MUX,SYS_CTRL2 PAD Pin-mux func select" "0,1,2,3,4,5,6,7" line.long 0x28 "PIN_MUX_CONFIG_SYS_CTRL3,PAD SYS_CTRL3 pin-mux config register" bitfld.long 0x28 12. "FV,SYS_CTRL3 PAD Force Input Value when fin=0x2" "0,1" bitfld.long 0x28 8.--9. "FIN,SYS_CTRL3 PAD Force Input On/Off mode" "0,1,2,3" bitfld.long 0x28 4. "ODE,SYS_CTRL3 PAD Opn Drain Mode enable" "0,1" bitfld.long 0x28 0.--2. "MUX,SYS_CTRL3 PAD Pin-mux func select" "0,1,2,3,4,5,6,7" tree.end tree "PINCTRL_SAFETY" base ad:0x3C500000 group.long 0x0++0xDB line.long 0x0 "IO_PAD_CONFIG_JTAG_TMS,PAD JTAG_TMS config register" bitfld.long 0x0 16. "POE,JTAG_TMS PAD Parametric output enable" "0,1" bitfld.long 0x0 12. "IS,JTAG_TMS PAD Input select" "0,1" bitfld.long 0x0 8. "SR,JTAG_TMS PAD Slew rate" "0,1" bitfld.long 0x0 4.--5. "DS,JTAG_TMS PAD Driver select" "0,1,2,3" newline bitfld.long 0x0 1. "PS,JTAG_TMS PAD Pull select" "0,1" bitfld.long 0x0 0. "PE,JTAG_TMS PAD Pull enable" "0,1" line.long 0x4 "IO_PAD_CONFIG_JTAG_TCK,PAD JTAG_TCK config register" bitfld.long 0x4 16. "POE,JTAG_TCK PAD Parametric output enable" "0,1" bitfld.long 0x4 12. "IS,JTAG_TCK PAD Input select" "0,1" bitfld.long 0x4 8. "SR,JTAG_TCK PAD Slew rate" "0,1" bitfld.long 0x4 4.--5. "DS,JTAG_TCK PAD Driver select" "0,1,2,3" newline bitfld.long 0x4 1. "PS,JTAG_TCK PAD Pull select" "0,1" bitfld.long 0x4 0. "PE,JTAG_TCK PAD Pull enable" "0,1" line.long 0x8 "IO_PAD_CONFIG_JTAG_TDI,PAD JTAG_TDI config register" bitfld.long 0x8 16. "POE,JTAG_TDI PAD Parametric output enable" "0,1" bitfld.long 0x8 12. "IS,JTAG_TDI PAD Input select" "0,1" bitfld.long 0x8 8. "SR,JTAG_TDI PAD Slew rate" "0,1" bitfld.long 0x8 4.--5. "DS,JTAG_TDI PAD Driver select" "0,1,2,3" newline bitfld.long 0x8 1. "PS,JTAG_TDI PAD Pull select" "0,1" bitfld.long 0x8 0. "PE,JTAG_TDI PAD Pull enable" "0,1" line.long 0xC "IO_PAD_CONFIG_JTAG_TDO,PAD JTAG_TDO config register" bitfld.long 0xC 16. "POE,JTAG_TDO PAD Parametric output enable" "0,1" bitfld.long 0xC 12. "IS,JTAG_TDO PAD Input select" "0,1" bitfld.long 0xC 8. "SR,JTAG_TDO PAD Slew rate" "0,1" bitfld.long 0xC 4.--5. "DS,JTAG_TDO PAD Driver select" "0,1,2,3" newline bitfld.long 0xC 1. "PS,JTAG_TDO PAD Pull select" "0,1" bitfld.long 0xC 0. "PE,JTAG_TDO PAD Pull enable" "0,1" line.long 0x10 "IO_PAD_CONFIG_JTAG_TRST_N,PAD JTAG_TRST_N config register" bitfld.long 0x10 16. "POE,JTAG_TRST_N PAD Parametric output enable" "0,1" bitfld.long 0x10 12. "IS,JTAG_TRST_N PAD Input select" "0,1" bitfld.long 0x10 8. "SR,JTAG_TRST_N PAD Slew rate" "0,1" bitfld.long 0x10 4.--5. "DS,JTAG_TRST_N PAD Driver select" "0,1,2,3" newline bitfld.long 0x10 1. "PS,JTAG_TRST_N PAD Pull select" "0,1" bitfld.long 0x10 0. "PE,JTAG_TRST_N PAD Pull enable" "0,1" line.long 0x14 "IO_PAD_CONFIG_OSPI1_SCLK,PAD OSPI1_SCLK config register" bitfld.long 0x14 16. "POE,OSPI1_SCLK PAD Parametric output enable" "0,1" bitfld.long 0x14 12. "IS,OSPI1_SCLK PAD Input select" "0,1" bitfld.long 0x14 8. "SR,OSPI1_SCLK PAD Slew rate" "0,1" bitfld.long 0x14 4.--5. "DS,OSPI1_SCLK PAD Driver select" "0,1,2,3" newline bitfld.long 0x14 1. "PS,OSPI1_SCLK PAD Pull select" "0,1" bitfld.long 0x14 0. "PE,OSPI1_SCLK PAD Pull enable" "0,1" line.long 0x18 "IO_PAD_CONFIG_OSPI1_SS0,PAD OSPI1_SS0 config register" bitfld.long 0x18 16. "POE,OSPI1_SS0 PAD Parametric output enable" "0,1" bitfld.long 0x18 12. "IS,OSPI1_SS0 PAD Input select" "0,1" bitfld.long 0x18 8. "SR,OSPI1_SS0 PAD Slew rate" "0,1" bitfld.long 0x18 4.--5. "DS,OSPI1_SS0 PAD Driver select" "0,1,2,3" newline bitfld.long 0x18 1. "PS,OSPI1_SS0 PAD Pull select" "0,1" bitfld.long 0x18 0. "PE,OSPI1_SS0 PAD Pull enable" "0,1" line.long 0x1C "IO_PAD_CONFIG_OSPI1_DATA0,PAD OSPI1_DATA0 config register" bitfld.long 0x1C 16. "POE,OSPI1_DATA0 PAD Parametric output enable" "0,1" bitfld.long 0x1C 12. "IS,OSPI1_DATA0 PAD Input select" "0,1" bitfld.long 0x1C 8. "SR,OSPI1_DATA0 PAD Slew rate" "0,1" bitfld.long 0x1C 4.--5. "DS,OSPI1_DATA0 PAD Driver select" "0,1,2,3" newline bitfld.long 0x1C 1. "PS,OSPI1_DATA0 PAD Pull select" "0,1" bitfld.long 0x1C 0. "PE,OSPI1_DATA0 PAD Pull enable" "0,1" line.long 0x20 "IO_PAD_CONFIG_OSPI1_DATA1,PAD OSPI1_DATA1 config register" bitfld.long 0x20 16. "POE,OSPI1_DATA1 PAD Parametric output enable" "0,1" bitfld.long 0x20 12. "IS,OSPI1_DATA1 PAD Input select" "0,1" bitfld.long 0x20 8. "SR,OSPI1_DATA1 PAD Slew rate" "0,1" bitfld.long 0x20 4.--5. "DS,OSPI1_DATA1 PAD Driver select" "0,1,2,3" newline bitfld.long 0x20 1. "PS,OSPI1_DATA1 PAD Pull select" "0,1" bitfld.long 0x20 0. "PE,OSPI1_DATA1 PAD Pull enable" "0,1" line.long 0x24 "IO_PAD_CONFIG_OSPI1_DATA2,PAD OSPI1_DATA2 config register" bitfld.long 0x24 16. "POE,OSPI1_DATA2 PAD Parametric output enable" "0,1" bitfld.long 0x24 12. "IS,OSPI1_DATA2 PAD Input select" "0,1" bitfld.long 0x24 8. "SR,OSPI1_DATA2 PAD Slew rate" "0,1" bitfld.long 0x24 4.--5. "DS,OSPI1_DATA2 PAD Driver select" "0,1,2,3" newline bitfld.long 0x24 1. "PS,OSPI1_DATA2 PAD Pull select" "0,1" bitfld.long 0x24 0. "PE,OSPI1_DATA2 PAD Pull enable" "0,1" line.long 0x28 "IO_PAD_CONFIG_OSPI1_DATA3,PAD OSPI1_DATA3 config register" bitfld.long 0x28 16. "POE,OSPI1_DATA3 PAD Parametric output enable" "0,1" bitfld.long 0x28 12. "IS,OSPI1_DATA3 PAD Input select" "0,1" bitfld.long 0x28 8. "SR,OSPI1_DATA3 PAD Slew rate" "0,1" bitfld.long 0x28 4.--5. "DS,OSPI1_DATA3 PAD Driver select" "0,1,2,3" newline bitfld.long 0x28 1. "PS,OSPI1_DATA3 PAD Pull select" "0,1" bitfld.long 0x28 0. "PE,OSPI1_DATA3 PAD Pull enable" "0,1" line.long 0x2C "IO_PAD_CONFIG_OSPI1_DATA4,PAD OSPI1_DATA4 config register" bitfld.long 0x2C 16. "POE,OSPI1_DATA4 PAD Parametric output enable" "0,1" bitfld.long 0x2C 12. "IS,OSPI1_DATA4 PAD Input select" "0,1" bitfld.long 0x2C 8. "SR,OSPI1_DATA4 PAD Slew rate" "0,1" bitfld.long 0x2C 4.--5. "DS,OSPI1_DATA4 PAD Driver select" "0,1,2,3" newline bitfld.long 0x2C 1. "PS,OSPI1_DATA4 PAD Pull select" "0,1" bitfld.long 0x2C 0. "PE,OSPI1_DATA4 PAD Pull enable" "0,1" line.long 0x30 "IO_PAD_CONFIG_OSPI1_DATA5,PAD OSPI1_DATA5 config register" bitfld.long 0x30 16. "POE,OSPI1_DATA5 PAD Parametric output enable" "0,1" bitfld.long 0x30 12. "IS,OSPI1_DATA5 PAD Input select" "0,1" bitfld.long 0x30 8. "SR,OSPI1_DATA5 PAD Slew rate" "0,1" bitfld.long 0x30 4.--5. "DS,OSPI1_DATA5 PAD Driver select" "0,1,2,3" newline bitfld.long 0x30 1. "PS,OSPI1_DATA5 PAD Pull select" "0,1" bitfld.long 0x30 0. "PE,OSPI1_DATA5 PAD Pull enable" "0,1" line.long 0x34 "IO_PAD_CONFIG_OSPI1_DATA6,PAD OSPI1_DATA6 config register" bitfld.long 0x34 16. "POE,OSPI1_DATA6 PAD Parametric output enable" "0,1" bitfld.long 0x34 12. "IS,OSPI1_DATA6 PAD Input select" "0,1" bitfld.long 0x34 8. "SR,OSPI1_DATA6 PAD Slew rate" "0,1" bitfld.long 0x34 4.--5. "DS,OSPI1_DATA6 PAD Driver select" "0,1,2,3" newline bitfld.long 0x34 1. "PS,OSPI1_DATA6 PAD Pull select" "0,1" bitfld.long 0x34 0. "PE,OSPI1_DATA6 PAD Pull enable" "0,1" line.long 0x38 "IO_PAD_CONFIG_OSPI1_DATA7,PAD OSPI1_DATA7 config register" bitfld.long 0x38 16. "POE,OSPI1_DATA7 PAD Parametric output enable" "0,1" bitfld.long 0x38 12. "IS,OSPI1_DATA7 PAD Input select" "0,1" bitfld.long 0x38 8. "SR,OSPI1_DATA7 PAD Slew rate" "0,1" bitfld.long 0x38 4.--5. "DS,OSPI1_DATA7 PAD Driver select" "0,1,2,3" newline bitfld.long 0x38 1. "PS,OSPI1_DATA7 PAD Pull select" "0,1" bitfld.long 0x38 0. "PE,OSPI1_DATA7 PAD Pull enable" "0,1" line.long 0x3C "IO_PAD_CONFIG_OSPI1_DQS,PAD OSPI1_DQS config register" bitfld.long 0x3C 16. "POE,OSPI1_DQS PAD Parametric output enable" "0,1" bitfld.long 0x3C 12. "IS,OSPI1_DQS PAD Input select" "0,1" bitfld.long 0x3C 8. "SR,OSPI1_DQS PAD Slew rate" "0,1" bitfld.long 0x3C 4.--5. "DS,OSPI1_DQS PAD Driver select" "0,1,2,3" newline bitfld.long 0x3C 1. "PS,OSPI1_DQS PAD Pull select" "0,1" bitfld.long 0x3C 0. "PE,OSPI1_DQS PAD Pull enable" "0,1" line.long 0x40 "IO_PAD_CONFIG_OSPI1_SS1,PAD OSPI1_SS1 config register" bitfld.long 0x40 16. "POE,OSPI1_SS1 PAD Parametric output enable" "0,1" bitfld.long 0x40 12. "IS,OSPI1_SS1 PAD Input select" "0,1" bitfld.long 0x40 8. "SR,OSPI1_SS1 PAD Slew rate" "0,1" bitfld.long 0x40 4.--5. "DS,OSPI1_SS1 PAD Driver select" "0,1,2,3" newline bitfld.long 0x40 1. "PS,OSPI1_SS1 PAD Pull select" "0,1" bitfld.long 0x40 0. "PE,OSPI1_SS1 PAD Pull enable" "0,1" line.long 0x44 "IO_PAD_CONFIG_RGMII1_TXC,PAD RGMII1_TXC config register" bitfld.long 0x44 16. "POE,RGMII1_TXC PAD Parametric output enable" "0,1" bitfld.long 0x44 12. "IS,RGMII1_TXC PAD Input select" "0,1" bitfld.long 0x44 8. "SR,RGMII1_TXC PAD Slew rate" "0,1" bitfld.long 0x44 4.--5. "DS,RGMII1_TXC PAD Driver select" "0,1,2,3" newline bitfld.long 0x44 1. "PS,RGMII1_TXC PAD Pull select" "0,1" bitfld.long 0x44 0. "PE,RGMII1_TXC PAD Pull enable" "0,1" line.long 0x48 "IO_PAD_CONFIG_RGMII1_TXD0,PAD RGMII1_TXD0 config register" bitfld.long 0x48 16. "POE,RGMII1_TXD0 PAD Parametric output enable" "0,1" bitfld.long 0x48 12. "IS,RGMII1_TXD0 PAD Input select" "0,1" bitfld.long 0x48 8. "SR,RGMII1_TXD0 PAD Slew rate" "0,1" bitfld.long 0x48 4.--5. "DS,RGMII1_TXD0 PAD Driver select" "0,1,2,3" newline bitfld.long 0x48 1. "PS,RGMII1_TXD0 PAD Pull select" "0,1" bitfld.long 0x48 0. "PE,RGMII1_TXD0 PAD Pull enable" "0,1" line.long 0x4C "IO_PAD_CONFIG_RGMII1_TXD1,PAD RGMII1_TXD1 config register" bitfld.long 0x4C 16. "POE,RGMII1_TXD1 PAD Parametric output enable" "0,1" bitfld.long 0x4C 12. "IS,RGMII1_TXD1 PAD Input select" "0,1" bitfld.long 0x4C 8. "SR,RGMII1_TXD1 PAD Slew rate" "0,1" bitfld.long 0x4C 4.--5. "DS,RGMII1_TXD1 PAD Driver select" "0,1,2,3" newline bitfld.long 0x4C 1. "PS,RGMII1_TXD1 PAD Pull select" "0,1" bitfld.long 0x4C 0. "PE,RGMII1_TXD1 PAD Pull enable" "0,1" line.long 0x50 "IO_PAD_CONFIG_RGMII1_TXD2,PAD RGMII1_TXD2 config register" bitfld.long 0x50 16. "POE,RGMII1_TXD2 PAD Parametric output enable" "0,1" bitfld.long 0x50 12. "IS,RGMII1_TXD2 PAD Input select" "0,1" bitfld.long 0x50 8. "SR,RGMII1_TXD2 PAD Slew rate" "0,1" bitfld.long 0x50 4.--5. "DS,RGMII1_TXD2 PAD Driver select" "0,1,2,3" newline bitfld.long 0x50 1. "PS,RGMII1_TXD2 PAD Pull select" "0,1" bitfld.long 0x50 0. "PE,RGMII1_TXD2 PAD Pull enable" "0,1" line.long 0x54 "IO_PAD_CONFIG_RGMII1_TXD3,PAD RGMII1_TXD3 config register" bitfld.long 0x54 16. "POE,RGMII1_TXD3 PAD Parametric output enable" "0,1" bitfld.long 0x54 12. "IS,RGMII1_TXD3 PAD Input select" "0,1" bitfld.long 0x54 8. "SR,RGMII1_TXD3 PAD Slew rate" "0,1" bitfld.long 0x54 4.--5. "DS,RGMII1_TXD3 PAD Driver select" "0,1,2,3" newline bitfld.long 0x54 1. "PS,RGMII1_TXD3 PAD Pull select" "0,1" bitfld.long 0x54 0. "PE,RGMII1_TXD3 PAD Pull enable" "0,1" line.long 0x58 "IO_PAD_CONFIG_RGMII1_TX_CTL,PAD RGMII1_TX_CTL config register" bitfld.long 0x58 16. "POE,RGMII1_TX_CTL PAD Parametric output enable" "0,1" bitfld.long 0x58 12. "IS,RGMII1_TX_CTL PAD Input select" "0,1" bitfld.long 0x58 8. "SR,RGMII1_TX_CTL PAD Slew rate" "0,1" bitfld.long 0x58 4.--5. "DS,RGMII1_TX_CTL PAD Driver select" "0,1,2,3" newline bitfld.long 0x58 1. "PS,RGMII1_TX_CTL PAD Pull select" "0,1" bitfld.long 0x58 0. "PE,RGMII1_TX_CTL PAD Pull enable" "0,1" line.long 0x5C "IO_PAD_CONFIG_RGMII1_RXC,PAD RGMII1_RXC config register" bitfld.long 0x5C 16. "POE,RGMII1_RXC PAD Parametric output enable" "0,1" bitfld.long 0x5C 12. "IS,RGMII1_RXC PAD Input select" "0,1" bitfld.long 0x5C 8. "SR,RGMII1_RXC PAD Slew rate" "0,1" bitfld.long 0x5C 4.--5. "DS,RGMII1_RXC PAD Driver select" "0,1,2,3" newline bitfld.long 0x5C 1. "PS,RGMII1_RXC PAD Pull select" "0,1" bitfld.long 0x5C 0. "PE,RGMII1_RXC PAD Pull enable" "0,1" line.long 0x60 "IO_PAD_CONFIG_RGMII1_RXD0,PAD RGMII1_RXD0 config register" bitfld.long 0x60 16. "POE,RGMII1_RXD0 PAD Parametric output enable" "0,1" bitfld.long 0x60 12. "IS,RGMII1_RXD0 PAD Input select" "0,1" bitfld.long 0x60 8. "SR,RGMII1_RXD0 PAD Slew rate" "0,1" bitfld.long 0x60 4.--5. "DS,RGMII1_RXD0 PAD Driver select" "0,1,2,3" newline bitfld.long 0x60 1. "PS,RGMII1_RXD0 PAD Pull select" "0,1" bitfld.long 0x60 0. "PE,RGMII1_RXD0 PAD Pull enable" "0,1" line.long 0x64 "IO_PAD_CONFIG_RGMII1_RXD1,PAD RGMII1_RXD1 config register" bitfld.long 0x64 16. "POE,RGMII1_RXD1 PAD Parametric output enable" "0,1" bitfld.long 0x64 12. "IS,RGMII1_RXD1 PAD Input select" "0,1" bitfld.long 0x64 8. "SR,RGMII1_RXD1 PAD Slew rate" "0,1" bitfld.long 0x64 4.--5. "DS,RGMII1_RXD1 PAD Driver select" "0,1,2,3" newline bitfld.long 0x64 1. "PS,RGMII1_RXD1 PAD Pull select" "0,1" bitfld.long 0x64 0. "PE,RGMII1_RXD1 PAD Pull enable" "0,1" line.long 0x68 "IO_PAD_CONFIG_RGMII1_RXD2,PAD RGMII1_RXD2 config register" bitfld.long 0x68 16. "POE,RGMII1_RXD2 PAD Parametric output enable" "0,1" bitfld.long 0x68 12. "IS,RGMII1_RXD2 PAD Input select" "0,1" bitfld.long 0x68 8. "SR,RGMII1_RXD2 PAD Slew rate" "0,1" bitfld.long 0x68 4.--5. "DS,RGMII1_RXD2 PAD Driver select" "0,1,2,3" newline bitfld.long 0x68 1. "PS,RGMII1_RXD2 PAD Pull select" "0,1" bitfld.long 0x68 0. "PE,RGMII1_RXD2 PAD Pull enable" "0,1" line.long 0x6C "IO_PAD_CONFIG_RGMII1_RXD3,PAD RGMII1_RXD3 config register" bitfld.long 0x6C 16. "POE,RGMII1_RXD3 PAD Parametric output enable" "0,1" bitfld.long 0x6C 12. "IS,RGMII1_RXD3 PAD Input select" "0,1" bitfld.long 0x6C 8. "SR,RGMII1_RXD3 PAD Slew rate" "0,1" bitfld.long 0x6C 4.--5. "DS,RGMII1_RXD3 PAD Driver select" "0,1,2,3" newline bitfld.long 0x6C 1. "PS,RGMII1_RXD3 PAD Pull select" "0,1" bitfld.long 0x6C 0. "PE,RGMII1_RXD3 PAD Pull enable" "0,1" line.long 0x70 "IO_PAD_CONFIG_RGMII1_RX_CTL,PAD RGMII1_RX_CTL config register" bitfld.long 0x70 16. "POE,RGMII1_RX_CTL PAD Parametric output enable" "0,1" bitfld.long 0x70 12. "IS,RGMII1_RX_CTL PAD Input select" "0,1" bitfld.long 0x70 8. "SR,RGMII1_RX_CTL PAD Slew rate" "0,1" bitfld.long 0x70 4.--5. "DS,RGMII1_RX_CTL PAD Driver select" "0,1,2,3" newline bitfld.long 0x70 1. "PS,RGMII1_RX_CTL PAD Pull select" "0,1" bitfld.long 0x70 0. "PE,RGMII1_RX_CTL PAD Pull enable" "0,1" line.long 0x74 "IO_PAD_CONFIG_GPIO_A0,PAD GPIO_A0 config register" bitfld.long 0x74 16. "POE,GPIO_A0 PAD Parametric output enable" "0,1" bitfld.long 0x74 12. "IS,GPIO_A0 PAD Input select" "0,1" bitfld.long 0x74 8. "SR,GPIO_A0 PAD Slew rate" "0,1" bitfld.long 0x74 4.--5. "DS,GPIO_A0 PAD Driver select" "0,1,2,3" newline bitfld.long 0x74 1. "PS,GPIO_A0 PAD Pull select" "0,1" bitfld.long 0x74 0. "PE,GPIO_A0 PAD Pull enable" "0,1" line.long 0x78 "IO_PAD_CONFIG_GPIO_A1,PAD GPIO_A1 config register" bitfld.long 0x78 16. "POE,GPIO_A1 PAD Parametric output enable" "0,1" bitfld.long 0x78 12. "IS,GPIO_A1 PAD Input select" "0,1" bitfld.long 0x78 8. "SR,GPIO_A1 PAD Slew rate" "0,1" bitfld.long 0x78 4.--5. "DS,GPIO_A1 PAD Driver select" "0,1,2,3" newline bitfld.long 0x78 1. "PS,GPIO_A1 PAD Pull select" "0,1" bitfld.long 0x78 0. "PE,GPIO_A1 PAD Pull enable" "0,1" line.long 0x7C "IO_PAD_CONFIG_GPIO_A2,PAD GPIO_A2 config register" bitfld.long 0x7C 16. "POE,GPIO_A2 PAD Parametric output enable" "0,1" bitfld.long 0x7C 12. "IS,GPIO_A2 PAD Input select" "0,1" bitfld.long 0x7C 8. "SR,GPIO_A2 PAD Slew rate" "0,1" bitfld.long 0x7C 4.--5. "DS,GPIO_A2 PAD Driver select" "0,1,2,3" newline bitfld.long 0x7C 1. "PS,GPIO_A2 PAD Pull select" "0,1" bitfld.long 0x7C 0. "PE,GPIO_A2 PAD Pull enable" "0,1" line.long 0x80 "IO_PAD_CONFIG_GPIO_A3,PAD GPIO_A3 config register" bitfld.long 0x80 16. "POE,GPIO_A3 PAD Parametric output enable" "0,1" bitfld.long 0x80 12. "IS,GPIO_A3 PAD Input select" "0,1" bitfld.long 0x80 8. "SR,GPIO_A3 PAD Slew rate" "0,1" bitfld.long 0x80 4.--5. "DS,GPIO_A3 PAD Driver select" "0,1,2,3" newline bitfld.long 0x80 1. "PS,GPIO_A3 PAD Pull select" "0,1" bitfld.long 0x80 0. "PE,GPIO_A3 PAD Pull enable" "0,1" line.long 0x84 "IO_PAD_CONFIG_GPIO_A4,PAD GPIO_A4 config register" bitfld.long 0x84 16. "POE,GPIO_A4 PAD Parametric output enable" "0,1" bitfld.long 0x84 12. "IS,GPIO_A4 PAD Input select" "0,1" bitfld.long 0x84 8. "SR,GPIO_A4 PAD Slew rate" "0,1" bitfld.long 0x84 4.--5. "DS,GPIO_A4 PAD Driver select" "0,1,2,3" newline bitfld.long 0x84 1. "PS,GPIO_A4 PAD Pull select" "0,1" bitfld.long 0x84 0. "PE,GPIO_A4 PAD Pull enable" "0,1" line.long 0x88 "IO_PAD_CONFIG_GPIO_A5,PAD GPIO_A5 config register" bitfld.long 0x88 16. "POE,GPIO_A5 PAD Parametric output enable" "0,1" bitfld.long 0x88 12. "IS,GPIO_A5 PAD Input select" "0,1" bitfld.long 0x88 8. "SR,GPIO_A5 PAD Slew rate" "0,1" bitfld.long 0x88 4.--5. "DS,GPIO_A5 PAD Driver select" "0,1,2,3" newline bitfld.long 0x88 1. "PS,GPIO_A5 PAD Pull select" "0,1" bitfld.long 0x88 0. "PE,GPIO_A5 PAD Pull enable" "0,1" line.long 0x8C "IO_PAD_CONFIG_GPIO_A6,PAD GPIO_A6 config register" bitfld.long 0x8C 16. "POE,GPIO_A6 PAD Parametric output enable" "0,1" bitfld.long 0x8C 12. "IS,GPIO_A6 PAD Input select" "0,1" bitfld.long 0x8C 8. "SR,GPIO_A6 PAD Slew rate" "0,1" bitfld.long 0x8C 4.--5. "DS,GPIO_A6 PAD Driver select" "0,1,2,3" newline bitfld.long 0x8C 1. "PS,GPIO_A6 PAD Pull select" "0,1" bitfld.long 0x8C 0. "PE,GPIO_A6 PAD Pull enable" "0,1" line.long 0x90 "IO_PAD_CONFIG_GPIO_A7,PAD GPIO_A7 config register" bitfld.long 0x90 16. "POE,GPIO_A7 PAD Parametric output enable" "0,1" bitfld.long 0x90 12. "IS,GPIO_A7 PAD Input select" "0,1" bitfld.long 0x90 8. "SR,GPIO_A7 PAD Slew rate" "0,1" bitfld.long 0x90 4.--5. "DS,GPIO_A7 PAD Driver select" "0,1,2,3" newline bitfld.long 0x90 1. "PS,GPIO_A7 PAD Pull select" "0,1" bitfld.long 0x90 0. "PE,GPIO_A7 PAD Pull enable" "0,1" line.long 0x94 "IO_PAD_CONFIG_GPIO_A8,PAD GPIO_A8 config register" bitfld.long 0x94 16. "POE,GPIO_A8 PAD Parametric output enable" "0,1" bitfld.long 0x94 12. "IS,GPIO_A8 PAD Input select" "0,1" bitfld.long 0x94 8. "SR,GPIO_A8 PAD Slew rate" "0,1" bitfld.long 0x94 4.--5. "DS,GPIO_A8 PAD Driver select" "0,1,2,3" newline bitfld.long 0x94 1. "PS,GPIO_A8 PAD Pull select" "0,1" bitfld.long 0x94 0. "PE,GPIO_A8 PAD Pull enable" "0,1" line.long 0x98 "IO_PAD_CONFIG_GPIO_A9,PAD GPIO_A9 config register" bitfld.long 0x98 16. "POE,GPIO_A9 PAD Parametric output enable" "0,1" bitfld.long 0x98 12. "IS,GPIO_A9 PAD Input select" "0,1" bitfld.long 0x98 8. "SR,GPIO_A9 PAD Slew rate" "0,1" bitfld.long 0x98 4.--5. "DS,GPIO_A9 PAD Driver select" "0,1,2,3" newline bitfld.long 0x98 1. "PS,GPIO_A9 PAD Pull select" "0,1" bitfld.long 0x98 0. "PE,GPIO_A9 PAD Pull enable" "0,1" line.long 0x9C "IO_PAD_CONFIG_GPIO_A10,PAD GPIO_A10 config register" bitfld.long 0x9C 16. "POE,GPIO_A10 PAD Parametric output enable" "0,1" bitfld.long 0x9C 12. "IS,GPIO_A10 PAD Input select" "0,1" bitfld.long 0x9C 8. "SR,GPIO_A10 PAD Slew rate" "0,1" bitfld.long 0x9C 4.--5. "DS,GPIO_A10 PAD Driver select" "0,1,2,3" newline bitfld.long 0x9C 1. "PS,GPIO_A10 PAD Pull select" "0,1" bitfld.long 0x9C 0. "PE,GPIO_A10 PAD Pull enable" "0,1" line.long 0xA0 "IO_PAD_CONFIG_GPIO_A11,PAD GPIO_A11 config register" bitfld.long 0xA0 16. "POE,GPIO_A11 PAD Parametric output enable" "0,1" bitfld.long 0xA0 12. "IS,GPIO_A11 PAD Input select" "0,1" bitfld.long 0xA0 8. "SR,GPIO_A11 PAD Slew rate" "0,1" bitfld.long 0xA0 4.--5. "DS,GPIO_A11 PAD Driver select" "0,1,2,3" newline bitfld.long 0xA0 1. "PS,GPIO_A11 PAD Pull select" "0,1" bitfld.long 0xA0 0. "PE,GPIO_A11 PAD Pull enable" "0,1" line.long 0xA4 "IO_PAD_CONFIG_GPIO_B0,PAD GPIO_B0 config register" bitfld.long 0xA4 16. "POE,GPIO_B0 PAD Parametric output enable" "0,1" bitfld.long 0xA4 12. "IS,GPIO_B0 PAD Input select" "0,1" bitfld.long 0xA4 8. "SR,GPIO_B0 PAD Slew rate" "0,1" bitfld.long 0xA4 4.--5. "DS,GPIO_B0 PAD Driver select" "0,1,2,3" newline bitfld.long 0xA4 1. "PS,GPIO_B0 PAD Pull select" "0,1" bitfld.long 0xA4 0. "PE,GPIO_B0 PAD Pull enable" "0,1" line.long 0xA8 "IO_PAD_CONFIG_GPIO_B1,PAD GPIO_B1 config register" bitfld.long 0xA8 16. "POE,GPIO_B1 PAD Parametric output enable" "0,1" bitfld.long 0xA8 12. "IS,GPIO_B1 PAD Input select" "0,1" bitfld.long 0xA8 8. "SR,GPIO_B1 PAD Slew rate" "0,1" bitfld.long 0xA8 4.--5. "DS,GPIO_B1 PAD Driver select" "0,1,2,3" newline bitfld.long 0xA8 1. "PS,GPIO_B1 PAD Pull select" "0,1" bitfld.long 0xA8 0. "PE,GPIO_B1 PAD Pull enable" "0,1" line.long 0xAC "IO_PAD_CONFIG_GPIO_B2,PAD GPIO_B2 config register" bitfld.long 0xAC 16. "POE,GPIO_B2 PAD Parametric output enable" "0,1" bitfld.long 0xAC 12. "IS,GPIO_B2 PAD Input select" "0,1" bitfld.long 0xAC 8. "SR,GPIO_B2 PAD Slew rate" "0,1" bitfld.long 0xAC 4.--5. "DS,GPIO_B2 PAD Driver select" "0,1,2,3" newline bitfld.long 0xAC 1. "PS,GPIO_B2 PAD Pull select" "0,1" bitfld.long 0xAC 0. "PE,GPIO_B2 PAD Pull enable" "0,1" line.long 0xB0 "IO_PAD_CONFIG_GPIO_B3,PAD GPIO_B3 config register" bitfld.long 0xB0 16. "POE,GPIO_B3 PAD Parametric output enable" "0,1" bitfld.long 0xB0 12. "IS,GPIO_B3 PAD Input select" "0,1" bitfld.long 0xB0 8. "SR,GPIO_B3 PAD Slew rate" "0,1" bitfld.long 0xB0 4.--5. "DS,GPIO_B3 PAD Driver select" "0,1,2,3" newline bitfld.long 0xB0 1. "PS,GPIO_B3 PAD Pull select" "0,1" bitfld.long 0xB0 0. "PE,GPIO_B3 PAD Pull enable" "0,1" line.long 0xB4 "IO_PAD_CONFIG_GPIO_B4,PAD GPIO_B4 config register" bitfld.long 0xB4 16. "POE,GPIO_B4 PAD Parametric output enable" "0,1" bitfld.long 0xB4 12. "IS,GPIO_B4 PAD Input select" "0,1" bitfld.long 0xB4 8. "SR,GPIO_B4 PAD Slew rate" "0,1" bitfld.long 0xB4 4.--5. "DS,GPIO_B4 PAD Driver select" "0,1,2,3" newline bitfld.long 0xB4 1. "PS,GPIO_B4 PAD Pull select" "0,1" bitfld.long 0xB4 0. "PE,GPIO_B4 PAD Pull enable" "0,1" line.long 0xB8 "IO_PAD_CONFIG_GPIO_B5,PAD GPIO_B5 config register" bitfld.long 0xB8 16. "POE,GPIO_B5 PAD Parametric output enable" "0,1" bitfld.long 0xB8 12. "IS,GPIO_B5 PAD Input select" "0,1" bitfld.long 0xB8 8. "SR,GPIO_B5 PAD Slew rate" "0,1" bitfld.long 0xB8 4.--5. "DS,GPIO_B5 PAD Driver select" "0,1,2,3" newline bitfld.long 0xB8 1. "PS,GPIO_B5 PAD Pull select" "0,1" bitfld.long 0xB8 0. "PE,GPIO_B5 PAD Pull enable" "0,1" line.long 0xBC "IO_PAD_CONFIG_GPIO_B6,PAD GPIO_B6 config register" bitfld.long 0xBC 16. "POE,GPIO_B6 PAD Parametric output enable" "0,1" bitfld.long 0xBC 12. "IS,GPIO_B6 PAD Input select" "0,1" bitfld.long 0xBC 8. "SR,GPIO_B6 PAD Slew rate" "0,1" bitfld.long 0xBC 4.--5. "DS,GPIO_B6 PAD Driver select" "0,1,2,3" newline bitfld.long 0xBC 1. "PS,GPIO_B6 PAD Pull select" "0,1" bitfld.long 0xBC 0. "PE,GPIO_B6 PAD Pull enable" "0,1" line.long 0xC0 "IO_PAD_CONFIG_GPIO_B7,PAD GPIO_B7 config register" bitfld.long 0xC0 16. "POE,GPIO_B7 PAD Parametric output enable" "0,1" bitfld.long 0xC0 12. "IS,GPIO_B7 PAD Input select" "0,1" bitfld.long 0xC0 8. "SR,GPIO_B7 PAD Slew rate" "0,1" bitfld.long 0xC0 4.--5. "DS,GPIO_B7 PAD Driver select" "0,1,2,3" newline bitfld.long 0xC0 1. "PS,GPIO_B7 PAD Pull select" "0,1" bitfld.long 0xC0 0. "PE,GPIO_B7 PAD Pull enable" "0,1" line.long 0xC4 "IO_PAD_CONFIG_GPIO_B8,PAD GPIO_B8 config register" bitfld.long 0xC4 16. "POE,GPIO_B8 PAD Parametric output enable" "0,1" bitfld.long 0xC4 12. "IS,GPIO_B8 PAD Input select" "0,1" bitfld.long 0xC4 8. "SR,GPIO_B8 PAD Slew rate" "0,1" bitfld.long 0xC4 4.--5. "DS,GPIO_B8 PAD Driver select" "0,1,2,3" newline bitfld.long 0xC4 1. "PS,GPIO_B8 PAD Pull select" "0,1" bitfld.long 0xC4 0. "PE,GPIO_B8 PAD Pull enable" "0,1" line.long 0xC8 "IO_PAD_CONFIG_GPIO_B9,PAD GPIO_B9 config register" bitfld.long 0xC8 16. "POE,GPIO_B9 PAD Parametric output enable" "0,1" bitfld.long 0xC8 12. "IS,GPIO_B9 PAD Input select" "0,1" bitfld.long 0xC8 8. "SR,GPIO_B9 PAD Slew rate" "0,1" bitfld.long 0xC8 4.--5. "DS,GPIO_B9 PAD Driver select" "0,1,2,3" newline bitfld.long 0xC8 1. "PS,GPIO_B9 PAD Pull select" "0,1" bitfld.long 0xC8 0. "PE,GPIO_B9 PAD Pull enable" "0,1" line.long 0xCC "IO_PAD_CONFIG_GPIO_B10,PAD GPIO_B10 config register" bitfld.long 0xCC 16. "POE,GPIO_B10 PAD Parametric output enable" "0,1" bitfld.long 0xCC 12. "IS,GPIO_B10 PAD Input select" "0,1" bitfld.long 0xCC 8. "SR,GPIO_B10 PAD Slew rate" "0,1" bitfld.long 0xCC 4.--5. "DS,GPIO_B10 PAD Driver select" "0,1,2,3" newline bitfld.long 0xCC 1. "PS,GPIO_B10 PAD Pull select" "0,1" bitfld.long 0xCC 0. "PE,GPIO_B10 PAD Pull enable" "0,1" line.long 0xD0 "IO_PAD_CONFIG_GPIO_B11,PAD GPIO_B11 config register" bitfld.long 0xD0 16. "POE,GPIO_B11 PAD Parametric output enable" "0,1" bitfld.long 0xD0 12. "IS,GPIO_B11 PAD Input select" "0,1" bitfld.long 0xD0 8. "SR,GPIO_B11 PAD Slew rate" "0,1" bitfld.long 0xD0 4.--5. "DS,GPIO_B11 PAD Driver select" "0,1,2,3" newline bitfld.long 0xD0 1. "PS,GPIO_B11 PAD Pull select" "0,1" bitfld.long 0xD0 0. "PE,GPIO_B11 PAD Pull enable" "0,1" line.long 0xD4 "IO_PAD_CONFIG_SEM_FAULT,PAD SEM_FAULT config register" bitfld.long 0xD4 16. "POE,SEM_FAULT PAD Parametric output enable" "0,1" bitfld.long 0xD4 12. "IS,SEM_FAULT PAD Input select" "0,1" bitfld.long 0xD4 8. "SR,SEM_FAULT PAD Slew rate" "0,1" bitfld.long 0xD4 4.--5. "DS,SEM_FAULT PAD Driver select" "0,1,2,3" newline bitfld.long 0xD4 1. "PS,SEM_FAULT PAD Pull select" "0,1" bitfld.long 0xD4 0. "PE,SEM_FAULT PAD Pull enable" "0,1" line.long 0xD8 "IO_PAD_CONFIG_GPIO_SAF,PAD GPIO_SAF config register" bitfld.long 0xD8 16. "POE,GPIO_SAF PAD Parametric output enable" "0,1" bitfld.long 0xD8 12. "IS,GPIO_SAF PAD Input select" "0,1" bitfld.long 0xD8 8. "SR,GPIO_SAF PAD Slew rate" "0,1" bitfld.long 0xD8 4.--5. "DS,GPIO_SAF PAD Driver select" "0,1,2,3" newline bitfld.long 0xD8 1. "PS,GPIO_SAF PAD Pull select" "0,1" bitfld.long 0xD8 0. "PE,GPIO_SAF PAD Pull enable" "0,1" group.long 0x200++0xBF line.long 0x0 "PIN_MUX_CONFIG_OSPI1_SCLK,PAD OSPI1_SCLK pin-mux config register" bitfld.long 0x0 12. "FV,OSPI1_SCLK PAD Force Input Value when fin=0x2" "0,1" bitfld.long 0x0 8.--9. "FIN,OSPI1_SCLK PAD Force Input On/Off mode" "0,1,2,3" bitfld.long 0x0 4. "ODE,OSPI1_SCLK PAD Opn Drain Mode enable" "0,1" bitfld.long 0x0 0.--2. "MUX,OSPI1_SCLK PAD Pin-mux func select" "0,1,2,3,4,5,6,7" line.long 0x4 "PIN_MUX_CONFIG_OSPI1_SS0,PAD OSPI1_SS0 pin-mux config register" bitfld.long 0x4 12. "FV,OSPI1_SS0 PAD Force Input Value when fin=0x2" "0,1" bitfld.long 0x4 8.--9. "FIN,OSPI1_SS0 PAD Force Input On/Off mode" "0,1,2,3" bitfld.long 0x4 4. "ODE,OSPI1_SS0 PAD Opn Drain Mode enable" "0,1" bitfld.long 0x4 0.--2. "MUX,OSPI1_SS0 PAD Pin-mux func select" "0,1,2,3,4,5,6,7" line.long 0x8 "PIN_MUX_CONFIG_OSPI1_DATA0,PAD OSPI1_DATA0 pin-mux config register" bitfld.long 0x8 12. "FV,OSPI1_DATA0 PAD Force Input Value when fin=0x2" "0,1" bitfld.long 0x8 8.--9. "FIN,OSPI1_DATA0 PAD Force Input On/Off mode" "0,1,2,3" bitfld.long 0x8 4. "ODE,OSPI1_DATA0 PAD Opn Drain Mode enable" "0,1" bitfld.long 0x8 0.--2. "MUX,OSPI1_DATA0 PAD Pin-mux func select" "0,1,2,3,4,5,6,7" line.long 0xC "PIN_MUX_CONFIG_OSPI1_DATA1,PAD OSPI1_DATA1 pin-mux config register" bitfld.long 0xC 12. "FV,OSPI1_DATA1 PAD Force Input Value when fin=0x2" "0,1" bitfld.long 0xC 8.--9. "FIN,OSPI1_DATA1 PAD Force Input On/Off mode" "0,1,2,3" bitfld.long 0xC 4. "ODE,OSPI1_DATA1 PAD Opn Drain Mode enable" "0,1" bitfld.long 0xC 0.--2. "MUX,OSPI1_DATA1 PAD Pin-mux func select" "0,1,2,3,4,5,6,7" line.long 0x10 "PIN_MUX_CONFIG_OSPI1_DATA2,PAD OSPI1_DATA2 pin-mux config register" bitfld.long 0x10 12. "FV,OSPI1_DATA2 PAD Force Input Value when fin=0x2" "0,1" bitfld.long 0x10 8.--9. "FIN,OSPI1_DATA2 PAD Force Input On/Off mode" "0,1,2,3" bitfld.long 0x10 4. "ODE,OSPI1_DATA2 PAD Opn Drain Mode enable" "0,1" bitfld.long 0x10 0.--2. "MUX,OSPI1_DATA2 PAD Pin-mux func select" "0,1,2,3,4,5,6,7" line.long 0x14 "PIN_MUX_CONFIG_OSPI1_DATA3,PAD OSPI1_DATA3 pin-mux config register" bitfld.long 0x14 12. "FV,OSPI1_DATA3 PAD Force Input Value when fin=0x2" "0,1" bitfld.long 0x14 8.--9. "FIN,OSPI1_DATA3 PAD Force Input On/Off mode" "0,1,2,3" bitfld.long 0x14 4. "ODE,OSPI1_DATA3 PAD Opn Drain Mode enable" "0,1" bitfld.long 0x14 0.--2. "MUX,OSPI1_DATA3 PAD Pin-mux func select" "0,1,2,3,4,5,6,7" line.long 0x18 "PIN_MUX_CONFIG_OSPI1_DATA4,PAD OSPI1_DATA4 pin-mux config register" bitfld.long 0x18 12. "FV,OSPI1_DATA4 PAD Force Input Value when fin=0x2" "0,1" bitfld.long 0x18 8.--9. "FIN,OSPI1_DATA4 PAD Force Input On/Off mode" "0,1,2,3" bitfld.long 0x18 4. "ODE,OSPI1_DATA4 PAD Opn Drain Mode enable" "0,1" bitfld.long 0x18 0.--2. "MUX,OSPI1_DATA4 PAD Pin-mux func select" "0,1,2,3,4,5,6,7" line.long 0x1C "PIN_MUX_CONFIG_OSPI1_DATA5,PAD OSPI1_DATA5 pin-mux config register" bitfld.long 0x1C 12. "FV,OSPI1_DATA5 PAD Force Input Value when fin=0x2" "0,1" bitfld.long 0x1C 8.--9. "FIN,OSPI1_DATA5 PAD Force Input On/Off mode" "0,1,2,3" bitfld.long 0x1C 4. "ODE,OSPI1_DATA5 PAD Opn Drain Mode enable" "0,1" bitfld.long 0x1C 0.--2. "MUX,OSPI1_DATA5 PAD Pin-mux func select" "0,1,2,3,4,5,6,7" line.long 0x20 "PIN_MUX_CONFIG_OSPI1_DATA6,PAD OSPI1_DATA6 pin-mux config register" bitfld.long 0x20 12. "FV,OSPI1_DATA6 PAD Force Input Value when fin=0x2" "0,1" bitfld.long 0x20 8.--9. "FIN,OSPI1_DATA6 PAD Force Input On/Off mode" "0,1,2,3" bitfld.long 0x20 4. "ODE,OSPI1_DATA6 PAD Opn Drain Mode enable" "0,1" bitfld.long 0x20 0.--2. "MUX,OSPI1_DATA6 PAD Pin-mux func select" "0,1,2,3,4,5,6,7" line.long 0x24 "PIN_MUX_CONFIG_OSPI1_DATA7,PAD OSPI1_DATA7 pin-mux config register" bitfld.long 0x24 12. "FV,OSPI1_DATA7 PAD Force Input Value when fin=0x2" "0,1" bitfld.long 0x24 8.--9. "FIN,OSPI1_DATA7 PAD Force Input On/Off mode" "0,1,2,3" bitfld.long 0x24 4. "ODE,OSPI1_DATA7 PAD Opn Drain Mode enable" "0,1" bitfld.long 0x24 0.--2. "MUX,OSPI1_DATA7 PAD Pin-mux func select" "0,1,2,3,4,5,6,7" line.long 0x28 "PIN_MUX_CONFIG_OSPI1_DQS,PAD OSPI1_DQS pin-mux config register" bitfld.long 0x28 12. "FV,OSPI1_DQS PAD Force Input Value when fin=0x2" "0,1" bitfld.long 0x28 8.--9. "FIN,OSPI1_DQS PAD Force Input On/Off mode" "0,1,2,3" bitfld.long 0x28 4. "ODE,OSPI1_DQS PAD Opn Drain Mode enable" "0,1" bitfld.long 0x28 0.--2. "MUX,OSPI1_DQS PAD Pin-mux func select" "0,1,2,3,4,5,6,7" line.long 0x2C "PIN_MUX_CONFIG_OSPI1_SS1,PAD OSPI1_SS1 pin-mux config register" bitfld.long 0x2C 12. "FV,OSPI1_SS1 PAD Force Input Value when fin=0x2" "0,1" bitfld.long 0x2C 8.--9. "FIN,OSPI1_SS1 PAD Force Input On/Off mode" "0,1,2,3" bitfld.long 0x2C 4. "ODE,OSPI1_SS1 PAD Opn Drain Mode enable" "0,1" bitfld.long 0x2C 0.--2. "MUX,OSPI1_SS1 PAD Pin-mux func select" "0,1,2,3,4,5,6,7" line.long 0x30 "PIN_MUX_CONFIG_RGMII1_TXC,PAD RGMII1_TXC pin-mux config register" bitfld.long 0x30 12. "FV,RGMII1_TXC PAD Force Input Value when fin=0x2" "0,1" bitfld.long 0x30 8.--9. "FIN,RGMII1_TXC PAD Force Input On/Off mode" "0,1,2,3" bitfld.long 0x30 4. "ODE,RGMII1_TXC PAD Opn Drain Mode enable" "0,1" bitfld.long 0x30 0.--2. "MUX,RGMII1_TXC PAD Pin-mux func select" "0,1,2,3,4,5,6,7" line.long 0x34 "PIN_MUX_CONFIG_RGMII1_TXD0,PAD RGMII1_TXD0 pin-mux config register" bitfld.long 0x34 12. "FV,RGMII1_TXD0 PAD Force Input Value when fin=0x2" "0,1" bitfld.long 0x34 8.--9. "FIN,RGMII1_TXD0 PAD Force Input On/Off mode" "0,1,2,3" bitfld.long 0x34 4. "ODE,RGMII1_TXD0 PAD Opn Drain Mode enable" "0,1" bitfld.long 0x34 0.--2. "MUX,RGMII1_TXD0 PAD Pin-mux func select" "0,1,2,3,4,5,6,7" line.long 0x38 "PIN_MUX_CONFIG_RGMII1_TXD1,PAD RGMII1_TXD1 pin-mux config register" bitfld.long 0x38 12. "FV,RGMII1_TXD1 PAD Force Input Value when fin=0x2" "0,1" bitfld.long 0x38 8.--9. "FIN,RGMII1_TXD1 PAD Force Input On/Off mode" "0,1,2,3" bitfld.long 0x38 4. "ODE,RGMII1_TXD1 PAD Opn Drain Mode enable" "0,1" bitfld.long 0x38 0.--2. "MUX,RGMII1_TXD1 PAD Pin-mux func select" "0,1,2,3,4,5,6,7" line.long 0x3C "PIN_MUX_CONFIG_RGMII1_TXD2,PAD RGMII1_TXD2 pin-mux config register" bitfld.long 0x3C 12. "FV,RGMII1_TXD2 PAD Force Input Value when fin=0x2" "0,1" bitfld.long 0x3C 8.--9. "FIN,RGMII1_TXD2 PAD Force Input On/Off mode" "0,1,2,3" bitfld.long 0x3C 4. "ODE,RGMII1_TXD2 PAD Opn Drain Mode enable" "0,1" bitfld.long 0x3C 0.--2. "MUX,RGMII1_TXD2 PAD Pin-mux func select" "0,1,2,3,4,5,6,7" line.long 0x40 "PIN_MUX_CONFIG_RGMII1_TXD3,PAD RGMII1_TXD3 pin-mux config register" bitfld.long 0x40 12. "FV,RGMII1_TXD3 PAD Force Input Value when fin=0x2" "0,1" bitfld.long 0x40 8.--9. "FIN,RGMII1_TXD3 PAD Force Input On/Off mode" "0,1,2,3" bitfld.long 0x40 4. "ODE,RGMII1_TXD3 PAD Opn Drain Mode enable" "0,1" bitfld.long 0x40 0.--2. "MUX,RGMII1_TXD3 PAD Pin-mux func select" "0,1,2,3,4,5,6,7" line.long 0x44 "PIN_MUX_CONFIG_RGMII1_TX_CTL,PAD RGMII1_TX_CTL pin-mux config register" bitfld.long 0x44 12. "FV,RGMII1_TX_CTL PAD Force Input Value when fin=0x2" "0,1" bitfld.long 0x44 8.--9. "FIN,RGMII1_TX_CTL PAD Force Input On/Off mode" "0,1,2,3" bitfld.long 0x44 4. "ODE,RGMII1_TX_CTL PAD Opn Drain Mode enable" "0,1" bitfld.long 0x44 0.--2. "MUX,RGMII1_TX_CTL PAD Pin-mux func select" "0,1,2,3,4,5,6,7" line.long 0x48 "PIN_MUX_CONFIG_RGMII1_RXC,PAD RGMII1_RXC pin-mux config register" bitfld.long 0x48 12. "FV,RGMII1_RXC PAD Force Input Value when fin=0x2" "0,1" bitfld.long 0x48 8.--9. "FIN,RGMII1_RXC PAD Force Input On/Off mode" "0,1,2,3" bitfld.long 0x48 4. "ODE,RGMII1_RXC PAD Opn Drain Mode enable" "0,1" bitfld.long 0x48 0.--2. "MUX,RGMII1_RXC PAD Pin-mux func select" "0,1,2,3,4,5,6,7" line.long 0x4C "PIN_MUX_CONFIG_RGMII1_RXD0,PAD RGMII1_RXD0 pin-mux config register" bitfld.long 0x4C 12. "FV,RGMII1_RXD0 PAD Force Input Value when fin=0x2" "0,1" bitfld.long 0x4C 8.--9. "FIN,RGMII1_RXD0 PAD Force Input On/Off mode" "0,1,2,3" bitfld.long 0x4C 4. "ODE,RGMII1_RXD0 PAD Opn Drain Mode enable" "0,1" bitfld.long 0x4C 0.--2. "MUX,RGMII1_RXD0 PAD Pin-mux func select" "0,1,2,3,4,5,6,7" line.long 0x50 "PIN_MUX_CONFIG_RGMII1_RXD1,PAD RGMII1_RXD1 pin-mux config register" bitfld.long 0x50 12. "FV,RGMII1_RXD1 PAD Force Input Value when fin=0x2" "0,1" bitfld.long 0x50 8.--9. "FIN,RGMII1_RXD1 PAD Force Input On/Off mode" "0,1,2,3" bitfld.long 0x50 4. "ODE,RGMII1_RXD1 PAD Opn Drain Mode enable" "0,1" bitfld.long 0x50 0.--2. "MUX,RGMII1_RXD1 PAD Pin-mux func select" "0,1,2,3,4,5,6,7" line.long 0x54 "PIN_MUX_CONFIG_RGMII1_RXD2,PAD RGMII1_RXD2 pin-mux config register" bitfld.long 0x54 12. "FV,RGMII1_RXD2 PAD Force Input Value when fin=0x2" "0,1" bitfld.long 0x54 8.--9. "FIN,RGMII1_RXD2 PAD Force Input On/Off mode" "0,1,2,3" bitfld.long 0x54 4. "ODE,RGMII1_RXD2 PAD Opn Drain Mode enable" "0,1" bitfld.long 0x54 0.--2. "MUX,RGMII1_RXD2 PAD Pin-mux func select" "0,1,2,3,4,5,6,7" line.long 0x58 "PIN_MUX_CONFIG_RGMII1_RXD3,PAD RGMII1_RXD3 pin-mux config register" bitfld.long 0x58 12. "FV,RGMII1_RXD3 PAD Force Input Value when fin=0x2" "0,1" bitfld.long 0x58 8.--9. "FIN,RGMII1_RXD3 PAD Force Input On/Off mode" "0,1,2,3" bitfld.long 0x58 4. "ODE,RGMII1_RXD3 PAD Opn Drain Mode enable" "0,1" bitfld.long 0x58 0.--2. "MUX,RGMII1_RXD3 PAD Pin-mux func select" "0,1,2,3,4,5,6,7" line.long 0x5C "PIN_MUX_CONFIG_RGMII1_RX_CTL,PAD RGMII1_RX_CTL pin-mux config register" bitfld.long 0x5C 12. "FV,RGMII1_RX_CTL PAD Force Input Value when fin=0x2" "0,1" bitfld.long 0x5C 8.--9. "FIN,RGMII1_RX_CTL PAD Force Input On/Off mode" "0,1,2,3" bitfld.long 0x5C 4. "ODE,RGMII1_RX_CTL PAD Opn Drain Mode enable" "0,1" bitfld.long 0x5C 0.--2. "MUX,RGMII1_RX_CTL PAD Pin-mux func select" "0,1,2,3,4,5,6,7" line.long 0x60 "PIN_MUX_CONFIG_GPIO_A0,PAD GPIO_A0 pin-mux config register" bitfld.long 0x60 12. "FV,GPIO_A0 PAD Force Input Value when fin=0x2" "0,1" bitfld.long 0x60 8.--9. "FIN,GPIO_A0 PAD Force Input On/Off mode" "0,1,2,3" bitfld.long 0x60 4. "ODE,GPIO_A0 PAD Opn Drain Mode enable" "0,1" bitfld.long 0x60 0.--2. "MUX,GPIO_A0 PAD Pin-mux func select" "0,1,2,3,4,5,6,7" line.long 0x64 "PIN_MUX_CONFIG_GPIO_A1,PAD GPIO_A1 pin-mux config register" bitfld.long 0x64 12. "FV,GPIO_A1 PAD Force Input Value when fin=0x2" "0,1" bitfld.long 0x64 8.--9. "FIN,GPIO_A1 PAD Force Input On/Off mode" "0,1,2,3" bitfld.long 0x64 4. "ODE,GPIO_A1 PAD Opn Drain Mode enable" "0,1" bitfld.long 0x64 0.--2. "MUX,GPIO_A1 PAD Pin-mux func select" "0,1,2,3,4,5,6,7" line.long 0x68 "PIN_MUX_CONFIG_GPIO_A2,PAD GPIO_A2 pin-mux config register" bitfld.long 0x68 12. "FV,GPIO_A2 PAD Force Input Value when fin=0x2" "0,1" bitfld.long 0x68 8.--9. "FIN,GPIO_A2 PAD Force Input On/Off mode" "0,1,2,3" bitfld.long 0x68 4. "ODE,GPIO_A2 PAD Opn Drain Mode enable" "0,1" bitfld.long 0x68 0.--2. "MUX,GPIO_A2 PAD Pin-mux func select" "0,1,2,3,4,5,6,7" line.long 0x6C "PIN_MUX_CONFIG_GPIO_A3,PAD GPIO_A3 pin-mux config register" bitfld.long 0x6C 12. "FV,GPIO_A3 PAD Force Input Value when fin=0x2" "0,1" bitfld.long 0x6C 8.--9. "FIN,GPIO_A3 PAD Force Input On/Off mode" "0,1,2,3" bitfld.long 0x6C 4. "ODE,GPIO_A3 PAD Opn Drain Mode enable" "0,1" bitfld.long 0x6C 0.--2. "MUX,GPIO_A3 PAD Pin-mux func select" "0,1,2,3,4,5,6,7" line.long 0x70 "PIN_MUX_CONFIG_GPIO_A4,PAD GPIO_A4 pin-mux config register" bitfld.long 0x70 12. "FV,GPIO_A4 PAD Force Input Value when fin=0x2" "0,1" bitfld.long 0x70 8.--9. "FIN,GPIO_A4 PAD Force Input On/Off mode" "0,1,2,3" bitfld.long 0x70 4. "ODE,GPIO_A4 PAD Opn Drain Mode enable" "0,1" bitfld.long 0x70 0.--2. "MUX,GPIO_A4 PAD Pin-mux func select" "0,1,2,3,4,5,6,7" line.long 0x74 "PIN_MUX_CONFIG_GPIO_A5,PAD GPIO_A5 pin-mux config register" bitfld.long 0x74 12. "FV,GPIO_A5 PAD Force Input Value when fin=0x2" "0,1" bitfld.long 0x74 8.--9. "FIN,GPIO_A5 PAD Force Input On/Off mode" "0,1,2,3" bitfld.long 0x74 4. "ODE,GPIO_A5 PAD Opn Drain Mode enable" "0,1" bitfld.long 0x74 0.--2. "MUX,GPIO_A5 PAD Pin-mux func select" "0,1,2,3,4,5,6,7" line.long 0x78 "PIN_MUX_CONFIG_GPIO_A6,PAD GPIO_A6 pin-mux config register" bitfld.long 0x78 12. "FV,GPIO_A6 PAD Force Input Value when fin=0x2" "0,1" bitfld.long 0x78 8.--9. "FIN,GPIO_A6 PAD Force Input On/Off mode" "0,1,2,3" bitfld.long 0x78 4. "ODE,GPIO_A6 PAD Opn Drain Mode enable" "0,1" bitfld.long 0x78 0.--2. "MUX,GPIO_A6 PAD Pin-mux func select" "0,1,2,3,4,5,6,7" line.long 0x7C "PIN_MUX_CONFIG_GPIO_A7,PAD GPIO_A7 pin-mux config register" bitfld.long 0x7C 12. "FV,GPIO_A7 PAD Force Input Value when fin=0x2" "0,1" bitfld.long 0x7C 8.--9. "FIN,GPIO_A7 PAD Force Input On/Off mode" "0,1,2,3" bitfld.long 0x7C 4. "ODE,GPIO_A7 PAD Opn Drain Mode enable" "0,1" bitfld.long 0x7C 0.--2. "MUX,GPIO_A7 PAD Pin-mux func select" "0,1,2,3,4,5,6,7" line.long 0x80 "PIN_MUX_CONFIG_GPIO_A8,PAD GPIO_A8 pin-mux config register" bitfld.long 0x80 12. "FV,GPIO_A8 PAD Force Input Value when fin=0x2" "0,1" bitfld.long 0x80 8.--9. "FIN,GPIO_A8 PAD Force Input On/Off mode" "0,1,2,3" bitfld.long 0x80 4. "ODE,GPIO_A8 PAD Opn Drain Mode enable" "0,1" bitfld.long 0x80 0.--2. "MUX,GPIO_A8 PAD Pin-mux func select" "0,1,2,3,4,5,6,7" line.long 0x84 "PIN_MUX_CONFIG_GPIO_A9,PAD GPIO_A9 pin-mux config register" bitfld.long 0x84 12. "FV,GPIO_A9 PAD Force Input Value when fin=0x2" "0,1" bitfld.long 0x84 8.--9. "FIN,GPIO_A9 PAD Force Input On/Off mode" "0,1,2,3" bitfld.long 0x84 4. "ODE,GPIO_A9 PAD Opn Drain Mode enable" "0,1" bitfld.long 0x84 0.--2. "MUX,GPIO_A9 PAD Pin-mux func select" "0,1,2,3,4,5,6,7" line.long 0x88 "PIN_MUX_CONFIG_GPIO_A10,PAD GPIO_A10 pin-mux config register" bitfld.long 0x88 12. "FV,GPIO_A10 PAD Force Input Value when fin=0x2" "0,1" bitfld.long 0x88 8.--9. "FIN,GPIO_A10 PAD Force Input On/Off mode" "0,1,2,3" bitfld.long 0x88 4. "ODE,GPIO_A10 PAD Opn Drain Mode enable" "0,1" bitfld.long 0x88 0.--2. "MUX,GPIO_A10 PAD Pin-mux func select" "0,1,2,3,4,5,6,7" line.long 0x8C "PIN_MUX_CONFIG_GPIO_A11,PAD GPIO_A11 pin-mux config register" bitfld.long 0x8C 12. "FV,GPIO_A11 PAD Force Input Value when fin=0x2" "0,1" bitfld.long 0x8C 8.--9. "FIN,GPIO_A11 PAD Force Input On/Off mode" "0,1,2,3" bitfld.long 0x8C 4. "ODE,GPIO_A11 PAD Opn Drain Mode enable" "0,1" bitfld.long 0x8C 0.--2. "MUX,GPIO_A11 PAD Pin-mux func select" "0,1,2,3,4,5,6,7" line.long 0x90 "PIN_MUX_CONFIG_GPIO_B0,PAD GPIO_B0 pin-mux config register" bitfld.long 0x90 12. "FV,GPIO_B0 PAD Force Input Value when fin=0x2" "0,1" bitfld.long 0x90 8.--9. "FIN,GPIO_B0 PAD Force Input On/Off mode" "0,1,2,3" bitfld.long 0x90 4. "ODE,GPIO_B0 PAD Opn Drain Mode enable" "0,1" bitfld.long 0x90 0.--2. "MUX,GPIO_B0 PAD Pin-mux func select" "0,1,2,3,4,5,6,7" line.long 0x94 "PIN_MUX_CONFIG_GPIO_B1,PAD GPIO_B1 pin-mux config register" bitfld.long 0x94 12. "FV,GPIO_B1 PAD Force Input Value when fin=0x2" "0,1" bitfld.long 0x94 8.--9. "FIN,GPIO_B1 PAD Force Input On/Off mode" "0,1,2,3" bitfld.long 0x94 4. "ODE,GPIO_B1 PAD Opn Drain Mode enable" "0,1" bitfld.long 0x94 0.--2. "MUX,GPIO_B1 PAD Pin-mux func select" "0,1,2,3,4,5,6,7" line.long 0x98 "PIN_MUX_CONFIG_GPIO_B2,PAD GPIO_B2 pin-mux config register" bitfld.long 0x98 12. "FV,GPIO_B2 PAD Force Input Value when fin=0x2" "0,1" bitfld.long 0x98 8.--9. "FIN,GPIO_B2 PAD Force Input On/Off mode" "0,1,2,3" bitfld.long 0x98 4. "ODE,GPIO_B2 PAD Opn Drain Mode enable" "0,1" bitfld.long 0x98 0.--2. "MUX,GPIO_B2 PAD Pin-mux func select" "0,1,2,3,4,5,6,7" line.long 0x9C "PIN_MUX_CONFIG_GPIO_B3,PAD GPIO_B3 pin-mux config register" bitfld.long 0x9C 12. "FV,GPIO_B3 PAD Force Input Value when fin=0x2" "0,1" bitfld.long 0x9C 8.--9. "FIN,GPIO_B3 PAD Force Input On/Off mode" "0,1,2,3" bitfld.long 0x9C 4. "ODE,GPIO_B3 PAD Opn Drain Mode enable" "0,1" bitfld.long 0x9C 0.--2. "MUX,GPIO_B3 PAD Pin-mux func select" "0,1,2,3,4,5,6,7" line.long 0xA0 "PIN_MUX_CONFIG_GPIO_B4,PAD GPIO_B4 pin-mux config register" bitfld.long 0xA0 12. "FV,GPIO_B4 PAD Force Input Value when fin=0x2" "0,1" bitfld.long 0xA0 8.--9. "FIN,GPIO_B4 PAD Force Input On/Off mode" "0,1,2,3" bitfld.long 0xA0 4. "ODE,GPIO_B4 PAD Opn Drain Mode enable" "0,1" bitfld.long 0xA0 0.--2. "MUX,GPIO_B4 PAD Pin-mux func select" "0,1,2,3,4,5,6,7" line.long 0xA4 "PIN_MUX_CONFIG_GPIO_B5,PAD GPIO_B5 pin-mux config register" bitfld.long 0xA4 12. "FV,GPIO_B5 PAD Force Input Value when fin=0x2" "0,1" bitfld.long 0xA4 8.--9. "FIN,GPIO_B5 PAD Force Input On/Off mode" "0,1,2,3" bitfld.long 0xA4 4. "ODE,GPIO_B5 PAD Opn Drain Mode enable" "0,1" bitfld.long 0xA4 0.--2. "MUX,GPIO_B5 PAD Pin-mux func select" "0,1,2,3,4,5,6,7" line.long 0xA8 "PIN_MUX_CONFIG_GPIO_B6,PAD GPIO_B6 pin-mux config register" bitfld.long 0xA8 12. "FV,GPIO_B6 PAD Force Input Value when fin=0x2" "0,1" bitfld.long 0xA8 8.--9. "FIN,GPIO_B6 PAD Force Input On/Off mode" "0,1,2,3" bitfld.long 0xA8 4. "ODE,GPIO_B6 PAD Opn Drain Mode enable" "0,1" bitfld.long 0xA8 0.--2. "MUX,GPIO_B6 PAD Pin-mux func select" "0,1,2,3,4,5,6,7" line.long 0xAC "PIN_MUX_CONFIG_GPIO_B7,PAD GPIO_B7 pin-mux config register" bitfld.long 0xAC 12. "FV,GPIO_B7 PAD Force Input Value when fin=0x2" "0,1" bitfld.long 0xAC 8.--9. "FIN,GPIO_B7 PAD Force Input On/Off mode" "0,1,2,3" bitfld.long 0xAC 4. "ODE,GPIO_B7 PAD Opn Drain Mode enable" "0,1" bitfld.long 0xAC 0.--2. "MUX,GPIO_B7 PAD Pin-mux func select" "0,1,2,3,4,5,6,7" line.long 0xB0 "PIN_MUX_CONFIG_GPIO_B8,PAD GPIO_B8 pin-mux config register" bitfld.long 0xB0 12. "FV,GPIO_B8 PAD Force Input Value when fin=0x2" "0,1" bitfld.long 0xB0 8.--9. "FIN,GPIO_B8 PAD Force Input On/Off mode" "0,1,2,3" bitfld.long 0xB0 4. "ODE,GPIO_B8 PAD Opn Drain Mode enable" "0,1" bitfld.long 0xB0 0.--2. "MUX,GPIO_B8 PAD Pin-mux func select" "0,1,2,3,4,5,6,7" line.long 0xB4 "PIN_MUX_CONFIG_GPIO_B9,PAD GPIO_B9 pin-mux config register" bitfld.long 0xB4 12. "FV,GPIO_B9 PAD Force Input Value when fin=0x2" "0,1" bitfld.long 0xB4 8.--9. "FIN,GPIO_B9 PAD Force Input On/Off mode" "0,1,2,3" bitfld.long 0xB4 4. "ODE,GPIO_B9 PAD Opn Drain Mode enable" "0,1" bitfld.long 0xB4 0.--2. "MUX,GPIO_B9 PAD Pin-mux func select" "0,1,2,3,4,5,6,7" line.long 0xB8 "PIN_MUX_CONFIG_GPIO_B10,PAD GPIO_B10 pin-mux config register" bitfld.long 0xB8 12. "FV,GPIO_B10 PAD Force Input Value when fin=0x2" "0,1" bitfld.long 0xB8 8.--9. "FIN,GPIO_B10 PAD Force Input On/Off mode" "0,1,2,3" bitfld.long 0xB8 4. "ODE,GPIO_B10 PAD Opn Drain Mode enable" "0,1" bitfld.long 0xB8 0.--2. "MUX,GPIO_B10 PAD Pin-mux func select" "0,1,2,3,4,5,6,7" line.long 0xBC "PIN_MUX_CONFIG_GPIO_B11,PAD GPIO_B11 pin-mux config register" bitfld.long 0xBC 12. "FV,GPIO_B11 PAD Force Input Value when fin=0x2" "0,1" bitfld.long 0xBC 8.--9. "FIN,GPIO_B11 PAD Force Input On/Off mode" "0,1,2,3" bitfld.long 0xBC 4. "ODE,GPIO_B11 PAD Opn Drain Mode enable" "0,1" bitfld.long 0xBC 0.--2. "MUX,GPIO_B11 PAD Pin-mux func select" "0,1,2,3,4,5,6,7" group.long 0x400++0xCF line.long 0x0 "INPUT_SOURCE_SELECT_CANFD1_RX,CANFD1_RX input source select register" bitfld.long 0x0 0.--1. "SRC_SEL,source select" "0,1,2,3" line.long 0x4 "INPUT_SOURCE_SELECT_CANFD2_RX,CANFD2_RX input source select register" bitfld.long 0x4 0.--1. "SRC_SEL,source select" "0,1,2,3" line.long 0x8 "INPUT_SOURCE_SELECT_SPI4_SCLK,SPI4_SCLK input source select register" bitfld.long 0x8 0. "SRC_SEL,source select" "0,1" line.long 0xC "INPUT_SOURCE_SELECT_SPI4_SS,SPI4_SS input source select register" bitfld.long 0xC 0. "SRC_SEL,source select" "0,1" line.long 0x10 "INPUT_SOURCE_SELECT_SPI4_MISO,SPI4_MISO input source select register" bitfld.long 0x10 0. "SRC_SEL,source select" "0,1" line.long 0x14 "INPUT_SOURCE_SELECT_SPI4_MOSI,SPI4_MOSI input source select register" bitfld.long 0x14 0. "SRC_SEL,source select" "0,1" line.long 0x18 "INPUT_SOURCE_SELECT_UART5_RX,UART5_RX input source select register" bitfld.long 0x18 0. "SRC_SEL,source select" "0,1" line.long 0x1C "INPUT_SOURCE_SELECT_ENET1_MDIO,ENET1_MDIO input source select register" bitfld.long 0x1C 0.--2. "SRC_SEL,source select" "0,1,2,3,4,5,6,7" line.long 0x20 "INPUT_SOURCE_SELECT_I2C2_SCL,I2C2_SCL input source select register" bitfld.long 0x20 0.--1. "SRC_SEL,source select" "0,1,2,3" line.long 0x24 "INPUT_SOURCE_SELECT_ENET1_AUS_IN_1,ENET1_AUS_IN_1 input source select register" bitfld.long 0x24 0. "SRC_SEL,source select" "0,1" line.long 0x28 "INPUT_SOURCE_SELECT_I2C2_SDA,I2C2_SDA input source select register" bitfld.long 0x28 0.--1. "SRC_SEL,source select" "0,1,2,3" line.long 0x2C "INPUT_SOURCE_SELECT_ENET1_AUS_IN_2,ENET1_AUS_IN_2 input source select register" bitfld.long 0x2C 0. "SRC_SEL,source select" "0,1" line.long 0x30 "INPUT_SOURCE_SELECT_SPI3_SCLK,SPI3_SCLK input source select register" bitfld.long 0x30 0. "SRC_SEL,source select" "0,1" line.long 0x34 "INPUT_SOURCE_SELECT_TIMER1_CH0,TIMER1_CH0 input source select register" bitfld.long 0x34 0. "SRC_SEL,source select" "0,1" line.long 0x38 "INPUT_SOURCE_SELECT_ENET1_CAP_COMP_0,ENET1_CAP_COMP_0 input source select register" bitfld.long 0x38 0. "SRC_SEL,source select" "0,1" line.long 0x3C "INPUT_SOURCE_SELECT_SPI3_MISO,SPI3_MISO input source select register" bitfld.long 0x3C 0. "SRC_SEL,source select" "0,1" line.long 0x40 "INPUT_SOURCE_SELECT_UART7_RX,UART7_RX input source select register" bitfld.long 0x40 0. "SRC_SEL,source select" "0,1" line.long 0x44 "INPUT_SOURCE_SELECT_CANFD3_RX,CANFD3_RX input source select register" bitfld.long 0x44 0. "SRC_SEL,source select" "0,1" line.long 0x48 "INPUT_SOURCE_SELECT_TIMER1_CH1,TIMER1_CH1 input source select register" bitfld.long 0x48 0. "SRC_SEL,source select" "0,1" line.long 0x4C "INPUT_SOURCE_SELECT_ENET1_CAP_COMP_1,ENET1_CAP_COMP_1 input source select register" bitfld.long 0x4C 0. "SRC_SEL,source select" "0,1" line.long 0x50 "INPUT_SOURCE_SELECT_SPI3_MOSI,SPI3_MOSI input source select register" bitfld.long 0x50 0. "SRC_SEL,source select" "0,1" line.long 0x54 "INPUT_SOURCE_SELECT_ENET1_CAP_COMP_2,ENET1_CAP_COMP_2 input source select register" bitfld.long 0x54 0. "SRC_SEL,source select" "0,1" line.long 0x58 "INPUT_SOURCE_SELECT_SPI3_SS,SPI3_SS input source select register" bitfld.long 0x58 0. "SRC_SEL,source select" "0,1" line.long 0x5C "INPUT_SOURCE_SELECT_CANFD4_RX,CANFD4_RX input source select register" bitfld.long 0x5C 0. "SRC_SEL,source select" "0,1" line.long 0x60 "INPUT_SOURCE_SELECT_ENET1_CAP_COMP_3,ENET1_CAP_COMP_3 input source select register" bitfld.long 0x60 0. "SRC_SEL,source select" "0,1" line.long 0x64 "INPUT_SOURCE_SELECT_I2C1_SCL,I2C1_SCL input source select register" bitfld.long 0x64 0.--1. "SRC_SEL,source select" "0,1,2,3" line.long 0x68 "INPUT_SOURCE_SELECT_ENET1_AUS_IN_0,ENET1_AUS_IN_0 input source select register" bitfld.long 0x68 0. "SRC_SEL,source select" "0,1" line.long 0x6C "INPUT_SOURCE_SELECT_I2C1_SDA,I2C1_SDA input source select register" bitfld.long 0x6C 0.--1. "SRC_SEL,source select" "0,1,2,3" line.long 0x70 "INPUT_SOURCE_SELECT_SPI1_SCLK,SPI1_SCLK input source select register" bitfld.long 0x70 0. "SRC_SEL,source select" "0,1" line.long 0x74 "INPUT_SOURCE_SELECT_I2S_SC1_SCK,I2S_SC1_SCK input source select register" bitfld.long 0x74 0. "SRC_SEL,source select" "0,1" line.long 0x78 "INPUT_SOURCE_SELECT_TIMER1_CH2,TIMER1_CH2 input source select register" bitfld.long 0x78 0. "SRC_SEL,source select" "0,1" line.long 0x7C "INPUT_SOURCE_SELECT_SPI1_MISO,SPI1_MISO input source select register" bitfld.long 0x7C 0. "SRC_SEL,source select" "0,1" line.long 0x80 "INPUT_SOURCE_SELECT_TIMER1_CH3,TIMER1_CH3 input source select register" bitfld.long 0x80 0. "SRC_SEL,source select" "0,1" line.long 0x84 "INPUT_SOURCE_SELECT_SPI1_MOSI,SPI1_MOSI input source select register" bitfld.long 0x84 0. "SRC_SEL,source select" "0,1" line.long 0x88 "INPUT_SOURCE_SELECT_I2S_SC1_SDI_SDO,I2S_SC1_SDI_SDO input source select register" bitfld.long 0x88 0.--1. "SRC_SEL,source select" "0,1,2,3" line.long 0x8C "INPUT_SOURCE_SELECT_SPI1_SS,SPI1_SS input source select register" bitfld.long 0x8C 0. "SRC_SEL,source select" "0,1" line.long 0x90 "INPUT_SOURCE_SELECT_I2S_SC1_WS,I2S_SC1_WS input source select register" bitfld.long 0x90 0. "SRC_SEL,source select" "0,1" line.long 0x94 "INPUT_SOURCE_SELECT_SPI2_SCLK,SPI2_SCLK input source select register" bitfld.long 0x94 0. "SRC_SEL,source select" "0,1" line.long 0x98 "INPUT_SOURCE_SELECT_I2S_SC2_SCK,I2S_SC2_SCK input source select register" bitfld.long 0x98 0. "SRC_SEL,source select" "0,1" line.long 0x9C "INPUT_SOURCE_SELECT_SPI2_MISO,SPI2_MISO input source select register" bitfld.long 0x9C 0. "SRC_SEL,source select" "0,1" line.long 0xA0 "INPUT_SOURCE_SELECT_SPI2_MOSI,SPI2_MOSI input source select register" bitfld.long 0xA0 0. "SRC_SEL,source select" "0,1" line.long 0xA4 "INPUT_SOURCE_SELECT_I2S_SC2_SDI_SDO,I2S_SC2_SDI_SDO input source select register" bitfld.long 0xA4 0.--1. "SRC_SEL,source select" "0,1,2,3" line.long 0xA8 "INPUT_SOURCE_SELECT_SPI2_SS,SPI2_SS input source select register" bitfld.long 0xA8 0. "SRC_SEL,source select" "0,1" line.long 0xAC "INPUT_SOURCE_SELECT_I2S_SC2_WS,I2S_SC2_WS input source select register" bitfld.long 0xAC 0. "SRC_SEL,source select" "0,1" line.long 0xB0 "INPUT_SOURCE_SELECT_I2C3_SCL,I2C3_SCL input source select register" bitfld.long 0xB0 0.--1. "SRC_SEL,source select" "0,1,2,3" line.long 0xB4 "INPUT_SOURCE_SELECT_I2C3_SDA,I2C3_SDA input source select register" bitfld.long 0xB4 0.--1. "SRC_SEL,source select" "0,1,2,3" line.long 0xB8 "INPUT_SOURCE_SELECT_TIMER2_CH0,TIMER2_CH0 input source select register" bitfld.long 0xB8 0. "SRC_SEL,source select" "0,1" line.long 0xBC "INPUT_SOURCE_SELECT_I2C4_SCL,I2C4_SCL input source select register" bitfld.long 0xBC 0.--1. "SRC_SEL,source select" "0,1,2,3" line.long 0xC0 "INPUT_SOURCE_SELECT_TIMER2_CH1,TIMER2_CH1 input source select register" bitfld.long 0xC0 0. "SRC_SEL,source select" "0,1" line.long 0xC4 "INPUT_SOURCE_SELECT_I2C4_SDA,I2C4_SDA input source select register" bitfld.long 0xC4 0.--1. "SRC_SEL,source select" "0,1,2,3" line.long 0xC8 "INPUT_SOURCE_SELECT_TIMER2_CH2,TIMER2_CH2 input source select register" bitfld.long 0xC8 0. "SRC_SEL,source select" "0,1" line.long 0xCC "INPUT_SOURCE_SELECT_TIMER2_CH3,TIMER2_CH3 input source select register" bitfld.long 0xCC 0. "SRC_SEL,source select" "0,1" tree.end endif tree.end tree "PLL (Phase Locked Loop)" sif (CORENAME()=="CORTEXR5F") repeat 7. (increment 1. 1.) (list ad:0xF0250000 ad:0xF0260000 ad:0xF0800000 ad:0xF0810000 ad:0xF0820000 ad:0xF0830000 ad:0xF0840000) tree "PLL$1" base $2 group.long 0x0++0x1B line.long 0x0 "PLL_CTRL,pll global control register" rbitfld.long 0x0 31. "LOCK,Lock signal Indicates no cycle slips between the feedback clock and FPFD for 128 consecutive cycles." "0,1" newline bitfld.long 0x0 21. "PLL_DIVD_CG_EN,divider d cg enable" "0,1" bitfld.long 0x0 20. "PLL_DIVC_CG_EN,divider c cg enable" "0,1" newline bitfld.long 0x0 19. "PLL_DIVB_CG_EN,divider b cg enable" "0,1" bitfld.long 0x0 18. "PLL_DIVA_CG_EN,divider a cg enable" "0,1" newline bitfld.long 0x0 17. "BYPASS,PLL bypass. 1: pll bypass FREF is bypassed to FOUTDIV 0: bypass inactive" "bypass inactive,pll bypass" bitfld.long 0x0 16. "PLLPOSTCG_EN,PLL post divider clock gating enable. 1: postdiv clock gating enable 0: post divider clock gating disable." "post divider clock gating disable,postdiv clock gating enable" newline bitfld.long 0x0 4. "FOUTPOSTDIVEN,Post divide power down. 1: FOUTPOSTDIV 4-phase and synchronous clocks are enabled. 0: FOUTPOSTDIV 4-phase and synchronous clocks are powered down (outputs held at 1'b0)" "FOUTPOSTDIV,FOUTPOSTDIV" newline bitfld.long 0x0 3. "FOUT4PHASEEN,Enable of 4 phase clock generator4 phase output is also powered down if FOUTPOSTDIVEN=1'b0. 1: 4-phase and synchronous clocks are enabled. 0: 4-phase and synchronous clocks are powered down (outputs held at 1'b0)." "0,1" bitfld.long 0x0 2. "DACEN,Enable fractional noise canceling DAC in FRAC mode (this has no function in integer mode). 1: Fractional noise canceling DAC is active (default mode). 0: Fractional noise canceling DAC is not active (test mode only)." "Fractional noise canceling DAC is not active,Fractional noise canceling DAC is active" newline bitfld.long 0x0 1. "INT_MODE,int mode or fractional mode 1: integer mode 0: fractional mode" "fractional mode,integer mode" bitfld.long 0x0 0. "PLLEN,PLL enable. 1: pll enable 0: pll disable pll under low power mode." "pll disable,pll enable" line.long 0x4 "PLL_DIV,used to set the pll divide number" bitfld.long 0x4 9.--11. "POSTDIV2,PLL post divide 2 setting (1 to 7) POSTDIV2=0 is unused. Total post divide is POSTDIV1*POSTDIV2 POSTDIV1>= POSTDIV2" "?,POSTDIV2,?,?,?,?,?,?" newline bitfld.long 0x4 6.--8. "POSTDIV1,PLL post divide 1 setting (1 to 7) POSTDIV1=0 is unused. Total post divide is POSTDIV1*POSTDIV2 POSTDIV1>= POSTDIV2" "?,POSTDIV2,?,?,?,?,?,?" hexmask.long.byte 0x4 0.--5. 1. "REFDIV,Reference divide value (1 to 63)" line.long 0x8 "PLL_FBDIV,used to set the FBDIV value" hexmask.long.word 0x8 0.--11. 1. "FBDIV,PLL Feedback divide value (16 to 640 in integer mode 20 to 320 in fractional mode)" line.long 0xC "PLL_FRAC,used to set the FRAC value" hexmask.long.tbyte 0xC 0.--23. 1. "FRAC,Fractional portion of feedback divide value" line.long 0x10 "PLL_DESKEW,used to set pll DESKEW function. normally. the default setting is ok" hexmask.long.word 0x10 6.--17. 1. "DSKEWCALIN,DSKEWCALBYP==1'b0: Initial condition for deskew cali-bration logic. DSKEWCALBYP==1'b1: Override value for deskew cali-bration. It is a signed integer with positive values delaying thereset of the faster path and negative values delaying the.." newline bitfld.long 0x10 3.--5. "DSKEWCALCNT,Programmable counter for deskew calibration loopSelects the number of PFD edges to wait after each deskewcalibration step. Count is defined as 2DS KEWCALCNT+4(e.g. ifDSKEWCALCNT=3'd6 the loop will wait 1024 PFD periodsbef ore trying a new.." "0,1,2,3,4,5,6,7" bitfld.long 0x10 2. "DSKEWCALBYP,Deskew calibration bypass. 1'b0 - use the skew calibration output (whenDSKEW-CALEN=1) to set the phase correction. 1'b1 - use the DSKEWCALIN[11:0] value (whenDSKEW-CALEN=1) to set the phase correction" "use the skew calibration output,use the DSKEWCALIN[11:0] value" newline bitfld.long 0x10 1. "DSKEWFASTCAL,Deskew fast calibration enableSet this to 1 for initial calibration if an initial value is not al-ready knownShould be set to 0 for normal operation" "0,1" bitfld.long 0x10 0. "DSKEWCALEN,Deskew calibration enable to actively adjust for input skew. 1'b0 - skew calibration is disabled. Static phase oset is deter-mined by analog matching only. 1'b1 - skew calibration is enabled. Static phase oset is ad-justed by sensing phase at.." "skew calibration is disabled,skew calibration is enabled" line.long 0x14 "PLL_DESKEW_STA,pll deskew output register" hexmask.long.word 0x14 5.--16. 1. "DSKEWCALOUT,This is the output of either the skew calibration block (if DSKEWCALBYP=0) or a bueredversion of DSKEWCALIN[11:0] (if DSKEWCALBYP=1). It can be used to read out the phase calibration state to use as an override value so that skew calibration.." newline hexmask.long.byte 0x14 1.--4. 1. "DSKEWCALLOCKCNT,Reserved for future use" rbitfld.long 0x14 0. "DSKEWCALLOCK,Asserted when phase lock is achieved when DSKEWCALEN is set to 1'b1." "0,1" line.long 0x18 "PLL_SSMOD,pll spread spectrum setting" hexmask.long.byte 0x18 9.--14. 1. "DIVVAL,Input divider to set modulation frequency. Divide value is DIVVAL+1 For SELEXTWAVE=1'b0: Modulation Freq=Fclksscg/((DIVVAL+1)* 128) For SELEXTWAVE=1'b1: Modulation Freq=Fclksscg/((DIVVAL+1)*EXTMAXADDR)" newline hexmask.long.byte 0x18 4.--8. 1. "SPREAD,Spread Depth Control in 0.1% steps 5'b00001 ->0.1% 5'b00010 ->0.2% ... 5'b10000 ->1.6% ... 5'b11111 ->3.1%" bitfld.long 0x18 3. "DOWNSPREAD,Downspread control 0: Center-Spread 1: Downspread" "Center-Spread,Downspread" newline bitfld.long 0x18 2. "RESETPTR,Active High reset for wave table pointer Internally synchronized to CLKSSCG 0: If modulation is active(RESET=1'b0 DIS-ABLESSCG=1'b0) INTMOD and FRACMOD are updating based on internal wave table. 1: Modulation is stopped and wave table position.." "If modulation is active,Modulation is stopped and wave table position is.." bitfld.long 0x18 1. "DISABLE_SSCG,Active-High Modulator Bypass Control 0: Use Modulator Output. De-Assertion of DISABLE SSCG is synchronous with CLKSSCG 1: Bypass modulator (INTMOD=INTIN FRACMOD=FRACIN). Assertion of DISABLE SSCG is asynchronous" "Use Modulator Output,Bypass modulator" newline bitfld.long 0x18 0. "MOD_RESET,Active High Modulator Reset 1'b0 ->Modulator is operating 1'b1 ->Reset Modulator.INTMOD=12'd20 FRACMOD=24'd00" "0,1" repeat 2. (list 0x1 0x2 )(list 0x0 0x4 ) group.long ($2+0x20)++0x3 line.long 0x0 "PLL_OUT_DIV_$1,pll outside divider register" rbitfld.long 0x0 31. "DIV_BUSY_B,divider b busy indicator 1: busy 0: not busy" "not busy,busy" newline hexmask.long.byte 0x0 16.--19. 1. "DIV_NUM_B,divider b divider number" rbitfld.long 0x0 15. "DIV_BUSY_A,divider a busy indicator 1: busy 0: not busy" "not busy,busy" newline hexmask.long.byte 0x0 0.--3. 1. "DIV_NUM_A,divider a divider number" repeat.end tree.end repeat.end repeat 4. (increment 1. 1.) (list ad:0xF0C00000 ad:0xF0C10000 ad:0xF0C20000 ad:0xF0C30000) tree "PLL_LVDS$1" base $2 group.long 0x0++0x1B line.long 0x0 "PLL_CTRL,pll global control register" rbitfld.long 0x0 31. "LOCK,Lock signal Indicates no cycle slips between the feedback clock and FPFD for 128 consecutive cycles." "0,1" newline bitfld.long 0x0 21. "PLL_DIVD_CG_EN,divider d cg enable" "0,1" bitfld.long 0x0 20. "PLL_DIVC_CG_EN,divider c cg enable" "0,1" newline bitfld.long 0x0 19. "PLL_DIVB_CG_EN,divider b cg enable" "0,1" bitfld.long 0x0 18. "PLL_DIVA_CG_EN,divider a cg enable" "0,1" newline bitfld.long 0x0 17. "BYPASS,PLL bypass. 1: pll bypass FREF is bypassed to FOUTDIV 0: bypass inactive" "bypass inactive,pll bypass" bitfld.long 0x0 16. "PLLPOSTCG_EN,PLL post divider clock gating enable. 1: postdiv clock gating enable 0: post divider clock gating disable." "post divider clock gating disable,postdiv clock gating enable" newline bitfld.long 0x0 4. "FOUTPOSTDIVEN,Post divide power down. 1: FOUTPOSTDIV 4-phase and synchronous clocks are enabled. 0: FOUTPOSTDIV 4-phase and synchronous clocks are powered down (outputs held at 1'b0)" "FOUTPOSTDIV,FOUTPOSTDIV" newline bitfld.long 0x0 3. "FOUT4PHASEEN,Enable of 4 phase clock generator4 phase output is also powered down if FOUTPOSTDIVEN=1'b0. 1: 4-phase and synchronous clocks are enabled. 0: 4-phase and synchronous clocks are powered down (outputs held at 1'b0)." "0,1" bitfld.long 0x0 2. "DACEN,Enable fractional noise canceling DAC in FRAC mode (this has no function in integer mode). 1: Fractional noise canceling DAC is active (default mode). 0: Fractional noise canceling DAC is not active (test mode only)." "Fractional noise canceling DAC is not active,Fractional noise canceling DAC is active" newline bitfld.long 0x0 1. "INT_MODE,int mode or fractional mode 1: integer mode 0: fractional mode" "fractional mode,integer mode" bitfld.long 0x0 0. "PLLEN,PLL enable. 1: pll enable 0: pll disable pll under low power mode." "pll disable,pll enable" line.long 0x4 "PLL_DIV,used to set the pll divide number" bitfld.long 0x4 9.--11. "POSTDIV2,PLL post divide 2 setting (1 to 7) POSTDIV2=0 is unused. Total post divide is POSTDIV1*POSTDIV2 POSTDIV1>= POSTDIV2" "?,POSTDIV2,?,?,?,?,?,?" newline bitfld.long 0x4 6.--8. "POSTDIV1,PLL post divide 1 setting (1 to 7) POSTDIV1=0 is unused. Total post divide is POSTDIV1*POSTDIV2 POSTDIV1>= POSTDIV2" "?,POSTDIV2,?,?,?,?,?,?" hexmask.long.byte 0x4 0.--5. 1. "REFDIV,Reference divide value (1 to 63)" line.long 0x8 "PLL_FBDIV,used to set the FBDIV value" hexmask.long.word 0x8 0.--11. 1. "FBDIV,PLL Feedback divide value (16 to 640 in integer mode 20 to 320 in fractional mode)" line.long 0xC "PLL_FRAC,used to set the FRAC value" hexmask.long.tbyte 0xC 0.--23. 1. "FRAC,Fractional portion of feedback divide value" line.long 0x10 "PLL_DESKEW,used to set pll DESKEW function. normally. the default setting is ok" hexmask.long.word 0x10 6.--17. 1. "DSKEWCALIN,DSKEWCALBYP==1'b0: Initial condition for deskew cali-bration logic. DSKEWCALBYP==1'b1: Override value for deskew cali-bration. It is a signed integer with positive values delaying thereset of the faster path and negative values delaying the.." newline bitfld.long 0x10 3.--5. "DSKEWCALCNT,Programmable counter for deskew calibration loopSelects the number of PFD edges to wait after each deskewcalibration step. Count is defined as 2DS KEWCALCNT+4(e.g. ifDSKEWCALCNT=3'd6 the loop will wait 1024 PFD periodsbef ore trying a new.." "0,1,2,3,4,5,6,7" bitfld.long 0x10 2. "DSKEWCALBYP,Deskew calibration bypass. 1'b0 - use the skew calibration output (whenDSKEW-CALEN=1) to set the phase correction. 1'b1 - use the DSKEWCALIN[11:0] value (whenDSKEW-CALEN=1) to set the phase correction" "use the skew calibration output,use the DSKEWCALIN[11:0] value" newline bitfld.long 0x10 1. "DSKEWFASTCAL,Deskew fast calibration enableSet this to 1 for initial calibration if an initial value is not al-ready knownShould be set to 0 for normal operation" "0,1" bitfld.long 0x10 0. "DSKEWCALEN,Deskew calibration enable to actively adjust for input skew. 1'b0 - skew calibration is disabled. Static phase oset is deter-mined by analog matching only. 1'b1 - skew calibration is enabled. Static phase oset is ad-justed by sensing phase at.." "skew calibration is disabled,skew calibration is enabled" line.long 0x14 "PLL_DESKEW_STA,pll deskew output register" hexmask.long.word 0x14 5.--16. 1. "DSKEWCALOUT,This is the output of either the skew calibration block (if DSKEWCALBYP=0) or a bueredversion of DSKEWCALIN[11:0] (if DSKEWCALBYP=1). It can be used to read out the phase calibration state to use as an override value so that skew calibration.." newline hexmask.long.byte 0x14 1.--4. 1. "DSKEWCALLOCKCNT,Reserved for future use" rbitfld.long 0x14 0. "DSKEWCALLOCK,Asserted when phase lock is achieved when DSKEWCALEN is set to 1'b1." "0,1" line.long 0x18 "PLL_SSMOD,pll spread spectrum setting" hexmask.long.byte 0x18 9.--14. 1. "DIVVAL,Input divider to set modulation frequency. Divide value is DIVVAL+1 For SELEXTWAVE=1'b0: Modulation Freq=Fclksscg/((DIVVAL+1)* 128) For SELEXTWAVE=1'b1: Modulation Freq=Fclksscg/((DIVVAL+1)*EXTMAXADDR)" newline hexmask.long.byte 0x18 4.--8. 1. "SPREAD,Spread Depth Control in 0.1% steps 5'b00001 ->0.1% 5'b00010 ->0.2% ... 5'b10000 ->1.6% ... 5'b11111 ->3.1%" bitfld.long 0x18 3. "DOWNSPREAD,Downspread control 0: Center-Spread 1: Downspread" "Center-Spread,Downspread" newline bitfld.long 0x18 2. "RESETPTR,Active High reset for wave table pointer Internally synchronized to CLKSSCG 0: If modulation is active(RESET=1'b0 DIS-ABLESSCG=1'b0) INTMOD and FRACMOD are updating based on internal wave table. 1: Modulation is stopped and wave table position.." "If modulation is active,Modulation is stopped and wave table position is.." bitfld.long 0x18 1. "DISABLE_SSCG,Active-High Modulator Bypass Control 0: Use Modulator Output. De-Assertion of DISABLE SSCG is synchronous with CLKSSCG 1: Bypass modulator (INTMOD=INTIN FRACMOD=FRACIN). Assertion of DISABLE SSCG is asynchronous" "Use Modulator Output,Bypass modulator" newline bitfld.long 0x18 0. "MOD_RESET,Active High Modulator Reset 1'b0 ->Modulator is operating 1'b1 ->Reset Modulator.INTMOD=12'd20 FRACMOD=24'd00" "0,1" repeat 2. (list 0x1 0x2 )(list 0x0 0x4 ) group.long ($2+0x20)++0x3 line.long 0x0 "PLL_OUT_DIV_$1,pll outside divider register" rbitfld.long 0x0 31. "DIV_BUSY_B,divider b busy indicator 1: busy 0: not busy" "not busy,busy" newline hexmask.long.byte 0x0 16.--19. 1. "DIV_NUM_B,divider b divider number" rbitfld.long 0x0 15. "DIV_BUSY_A,divider a busy indicator 1: busy 0: not busy" "not busy,busy" newline hexmask.long.byte 0x0 0.--3. 1. "DIV_NUM_A,divider a divider number" repeat.end tree.end repeat.end tree "PLL_DISP" base ad:0xF0D30000 group.long 0x0++0x1B line.long 0x0 "PLL_CTRL,pll global control register" rbitfld.long 0x0 31. "LOCK,Lock signal Indicates no cycle slips between the feedback clock and FPFD for 128 consecutive cycles." "0,1" newline bitfld.long 0x0 21. "PLL_DIVD_CG_EN,divider d cg enable" "0,1" bitfld.long 0x0 20. "PLL_DIVC_CG_EN,divider c cg enable" "0,1" newline bitfld.long 0x0 19. "PLL_DIVB_CG_EN,divider b cg enable" "0,1" bitfld.long 0x0 18. "PLL_DIVA_CG_EN,divider a cg enable" "0,1" newline bitfld.long 0x0 17. "BYPASS,PLL bypass. 1: pll bypass FREF is bypassed to FOUTDIV 0: bypass inactive" "bypass inactive,pll bypass" bitfld.long 0x0 16. "PLLPOSTCG_EN,PLL post divider clock gating enable. 1: postdiv clock gating enable 0: post divider clock gating disable." "post divider clock gating disable,postdiv clock gating enable" newline bitfld.long 0x0 4. "FOUTPOSTDIVEN,Post divide power down. 1: FOUTPOSTDIV 4-phase and synchronous clocks are enabled. 0: FOUTPOSTDIV 4-phase and synchronous clocks are powered down (outputs held at 1'b0)" "FOUTPOSTDIV,FOUTPOSTDIV" newline bitfld.long 0x0 3. "FOUT4PHASEEN,Enable of 4 phase clock generator4 phase output is also powered down if FOUTPOSTDIVEN=1'b0. 1: 4-phase and synchronous clocks are enabled. 0: 4-phase and synchronous clocks are powered down (outputs held at 1'b0)." "0,1" bitfld.long 0x0 2. "DACEN,Enable fractional noise canceling DAC in FRAC mode (this has no function in integer mode). 1: Fractional noise canceling DAC is active (default mode). 0: Fractional noise canceling DAC is not active (test mode only)." "Fractional noise canceling DAC is not active,Fractional noise canceling DAC is active" newline bitfld.long 0x0 1. "INT_MODE,int mode or fractional mode 1: integer mode 0: fractional mode" "fractional mode,integer mode" bitfld.long 0x0 0. "PLLEN,PLL enable. 1: pll enable 0: pll disable pll under low power mode." "pll disable,pll enable" line.long 0x4 "PLL_DIV,used to set the pll divide number" bitfld.long 0x4 9.--11. "POSTDIV2,PLL post divide 2 setting (1 to 7) POSTDIV2=0 is unused. Total post divide is POSTDIV1*POSTDIV2 POSTDIV1>= POSTDIV2" "?,POSTDIV2,?,?,?,?,?,?" newline bitfld.long 0x4 6.--8. "POSTDIV1,PLL post divide 1 setting (1 to 7) POSTDIV1=0 is unused. Total post divide is POSTDIV1*POSTDIV2 POSTDIV1>= POSTDIV2" "?,POSTDIV2,?,?,?,?,?,?" hexmask.long.byte 0x4 0.--5. 1. "REFDIV,Reference divide value (1 to 63)" line.long 0x8 "PLL_FBDIV,used to set the FBDIV value" hexmask.long.word 0x8 0.--11. 1. "FBDIV,PLL Feedback divide value (16 to 640 in integer mode 20 to 320 in fractional mode)" line.long 0xC "PLL_FRAC,used to set the FRAC value" hexmask.long.tbyte 0xC 0.--23. 1. "FRAC,Fractional portion of feedback divide value" line.long 0x10 "PLL_DESKEW,used to set pll DESKEW function. normally. the default setting is ok" hexmask.long.word 0x10 6.--17. 1. "DSKEWCALIN,DSKEWCALBYP==1'b0: Initial condition for deskew cali-bration logic. DSKEWCALBYP==1'b1: Override value for deskew cali-bration. It is a signed integer with positive values delaying thereset of the faster path and negative values delaying the.." newline bitfld.long 0x10 3.--5. "DSKEWCALCNT,Programmable counter for deskew calibration loopSelects the number of PFD edges to wait after each deskewcalibration step. Count is defined as 2DS KEWCALCNT+4(e.g. ifDSKEWCALCNT=3'd6 the loop will wait 1024 PFD periodsbef ore trying a new.." "0,1,2,3,4,5,6,7" bitfld.long 0x10 2. "DSKEWCALBYP,Deskew calibration bypass. 1'b0 - use the skew calibration output (whenDSKEW-CALEN=1) to set the phase correction. 1'b1 - use the DSKEWCALIN[11:0] value (whenDSKEW-CALEN=1) to set the phase correction" "use the skew calibration output,use the DSKEWCALIN[11:0] value" newline bitfld.long 0x10 1. "DSKEWFASTCAL,Deskew fast calibration enableSet this to 1 for initial calibration if an initial value is not al-ready knownShould be set to 0 for normal operation" "0,1" bitfld.long 0x10 0. "DSKEWCALEN,Deskew calibration enable to actively adjust for input skew. 1'b0 - skew calibration is disabled. Static phase oset is deter-mined by analog matching only. 1'b1 - skew calibration is enabled. Static phase oset is ad-justed by sensing phase at.." "skew calibration is disabled,skew calibration is enabled" line.long 0x14 "PLL_DESKEW_STA,pll deskew output register" hexmask.long.word 0x14 5.--16. 1. "DSKEWCALOUT,This is the output of either the skew calibration block (if DSKEWCALBYP=0) or a bueredversion of DSKEWCALIN[11:0] (if DSKEWCALBYP=1). It can be used to read out the phase calibration state to use as an override value so that skew calibration.." newline hexmask.long.byte 0x14 1.--4. 1. "DSKEWCALLOCKCNT,Reserved for future use" rbitfld.long 0x14 0. "DSKEWCALLOCK,Asserted when phase lock is achieved when DSKEWCALEN is set to 1'b1." "0,1" line.long 0x18 "PLL_SSMOD,pll spread spectrum setting" hexmask.long.byte 0x18 9.--14. 1. "DIVVAL,Input divider to set modulation frequency. Divide value is DIVVAL+1 For SELEXTWAVE=1'b0: Modulation Freq=Fclksscg/((DIVVAL+1)* 128) For SELEXTWAVE=1'b1: Modulation Freq=Fclksscg/((DIVVAL+1)*EXTMAXADDR)" newline hexmask.long.byte 0x18 4.--8. 1. "SPREAD,Spread Depth Control in 0.1% steps 5'b00001 ->0.1% 5'b00010 ->0.2% ... 5'b10000 ->1.6% ... 5'b11111 ->3.1%" bitfld.long 0x18 3. "DOWNSPREAD,Downspread control 0: Center-Spread 1: Downspread" "Center-Spread,Downspread" newline bitfld.long 0x18 2. "RESETPTR,Active High reset for wave table pointer Internally synchronized to CLKSSCG 0: If modulation is active(RESET=1'b0 DIS-ABLESSCG=1'b0) INTMOD and FRACMOD are updating based on internal wave table. 1: Modulation is stopped and wave table position.." "If modulation is active,Modulation is stopped and wave table position is.." bitfld.long 0x18 1. "DISABLE_SSCG,Active-High Modulator Bypass Control 0: Use Modulator Output. De-Assertion of DISABLE SSCG is synchronous with CLKSSCG 1: Bypass modulator (INTMOD=INTIN FRACMOD=FRACIN). Assertion of DISABLE SSCG is asynchronous" "Use Modulator Output,Bypass modulator" newline bitfld.long 0x18 0. "MOD_RESET,Active High Modulator Reset 1'b0 ->Modulator is operating 1'b1 ->Reset Modulator.INTMOD=12'd20 FRACMOD=24'd00" "0,1" repeat 2. (list 0x1 0x2 )(list 0x0 0x4 ) group.long ($2+0x20)++0x3 line.long 0x0 "PLL_OUT_DIV_$1,pll outside divider register" rbitfld.long 0x0 31. "DIV_BUSY_B,divider b busy indicator 1: busy 0: not busy" "not busy,busy" newline hexmask.long.byte 0x0 16.--19. 1. "DIV_NUM_B,divider b divider number" rbitfld.long 0x0 15. "DIV_BUSY_A,divider a busy indicator 1: busy 0: not busy" "not busy,busy" newline hexmask.long.byte 0x0 0.--3. 1. "DIV_NUM_A,divider a divider number" repeat.end tree.end tree "PLL_HIS" base ad:0xF12A0000 group.long 0x0++0x1B line.long 0x0 "PLL_CTRL,pll global control register" rbitfld.long 0x0 31. "LOCK,Lock signal Indicates no cycle slips between the feedback clock and FPFD for 128 consecutive cycles." "0,1" newline bitfld.long 0x0 21. "PLL_DIVD_CG_EN,divider d cg enable" "0,1" bitfld.long 0x0 20. "PLL_DIVC_CG_EN,divider c cg enable" "0,1" newline bitfld.long 0x0 19. "PLL_DIVB_CG_EN,divider b cg enable" "0,1" bitfld.long 0x0 18. "PLL_DIVA_CG_EN,divider a cg enable" "0,1" newline bitfld.long 0x0 17. "BYPASS,PLL bypass. 1: pll bypass FREF is bypassed to FOUTDIV 0: bypass inactive" "bypass inactive,pll bypass" bitfld.long 0x0 16. "PLLPOSTCG_EN,PLL post divider clock gating enable. 1: postdiv clock gating enable 0: post divider clock gating disable." "post divider clock gating disable,postdiv clock gating enable" newline bitfld.long 0x0 4. "FOUTPOSTDIVEN,Post divide power down. 1: FOUTPOSTDIV 4-phase and synchronous clocks are enabled. 0: FOUTPOSTDIV 4-phase and synchronous clocks are powered down (outputs held at 1'b0)" "FOUTPOSTDIV,FOUTPOSTDIV" newline bitfld.long 0x0 3. "FOUT4PHASEEN,Enable of 4 phase clock generator4 phase output is also powered down if FOUTPOSTDIVEN=1'b0. 1: 4-phase and synchronous clocks are enabled. 0: 4-phase and synchronous clocks are powered down (outputs held at 1'b0)." "0,1" bitfld.long 0x0 2. "DACEN,Enable fractional noise canceling DAC in FRAC mode (this has no function in integer mode). 1: Fractional noise canceling DAC is active (default mode). 0: Fractional noise canceling DAC is not active (test mode only)." "Fractional noise canceling DAC is not active,Fractional noise canceling DAC is active" newline bitfld.long 0x0 1. "INT_MODE,int mode or fractional mode 1: integer mode 0: fractional mode" "fractional mode,integer mode" bitfld.long 0x0 0. "PLLEN,PLL enable. 1: pll enable 0: pll disable pll under low power mode." "pll disable,pll enable" line.long 0x4 "PLL_DIV,used to set the pll divide number" bitfld.long 0x4 9.--11. "POSTDIV2,PLL post divide 2 setting (1 to 7) POSTDIV2=0 is unused. Total post divide is POSTDIV1*POSTDIV2 POSTDIV1>= POSTDIV2" "?,POSTDIV2,?,?,?,?,?,?" newline bitfld.long 0x4 6.--8. "POSTDIV1,PLL post divide 1 setting (1 to 7) POSTDIV1=0 is unused. Total post divide is POSTDIV1*POSTDIV2 POSTDIV1>= POSTDIV2" "?,POSTDIV2,?,?,?,?,?,?" hexmask.long.byte 0x4 0.--5. 1. "REFDIV,Reference divide value (1 to 63)" line.long 0x8 "PLL_FBDIV,used to set the FBDIV value" hexmask.long.word 0x8 0.--11. 1. "FBDIV,PLL Feedback divide value (16 to 640 in integer mode 20 to 320 in fractional mode)" line.long 0xC "PLL_FRAC,used to set the FRAC value" hexmask.long.tbyte 0xC 0.--23. 1. "FRAC,Fractional portion of feedback divide value" line.long 0x10 "PLL_DESKEW,used to set pll DESKEW function. normally. the default setting is ok" hexmask.long.word 0x10 6.--17. 1. "DSKEWCALIN,DSKEWCALBYP==1'b0: Initial condition for deskew cali-bration logic. DSKEWCALBYP==1'b1: Override value for deskew cali-bration. It is a signed integer with positive values delaying thereset of the faster path and negative values delaying the.." newline bitfld.long 0x10 3.--5. "DSKEWCALCNT,Programmable counter for deskew calibration loopSelects the number of PFD edges to wait after each deskewcalibration step. Count is defined as 2DS KEWCALCNT+4(e.g. ifDSKEWCALCNT=3'd6 the loop will wait 1024 PFD periodsbef ore trying a new.." "0,1,2,3,4,5,6,7" bitfld.long 0x10 2. "DSKEWCALBYP,Deskew calibration bypass. 1'b0 - use the skew calibration output (whenDSKEW-CALEN=1) to set the phase correction. 1'b1 - use the DSKEWCALIN[11:0] value (whenDSKEW-CALEN=1) to set the phase correction" "use the skew calibration output,use the DSKEWCALIN[11:0] value" newline bitfld.long 0x10 1. "DSKEWFASTCAL,Deskew fast calibration enableSet this to 1 for initial calibration if an initial value is not al-ready knownShould be set to 0 for normal operation" "0,1" bitfld.long 0x10 0. "DSKEWCALEN,Deskew calibration enable to actively adjust for input skew. 1'b0 - skew calibration is disabled. Static phase oset is deter-mined by analog matching only. 1'b1 - skew calibration is enabled. Static phase oset is ad-justed by sensing phase at.." "skew calibration is disabled,skew calibration is enabled" line.long 0x14 "PLL_DESKEW_STA,pll deskew output register" hexmask.long.word 0x14 5.--16. 1. "DSKEWCALOUT,This is the output of either the skew calibration block (if DSKEWCALBYP=0) or a bueredversion of DSKEWCALIN[11:0] (if DSKEWCALBYP=1). It can be used to read out the phase calibration state to use as an override value so that skew calibration.." newline hexmask.long.byte 0x14 1.--4. 1. "DSKEWCALLOCKCNT,Reserved for future use" rbitfld.long 0x14 0. "DSKEWCALLOCK,Asserted when phase lock is achieved when DSKEWCALEN is set to 1'b1." "0,1" line.long 0x18 "PLL_SSMOD,pll spread spectrum setting" hexmask.long.byte 0x18 9.--14. 1. "DIVVAL,Input divider to set modulation frequency. Divide value is DIVVAL+1 For SELEXTWAVE=1'b0: Modulation Freq=Fclksscg/((DIVVAL+1)* 128) For SELEXTWAVE=1'b1: Modulation Freq=Fclksscg/((DIVVAL+1)*EXTMAXADDR)" newline hexmask.long.byte 0x18 4.--8. 1. "SPREAD,Spread Depth Control in 0.1% steps 5'b00001 ->0.1% 5'b00010 ->0.2% ... 5'b10000 ->1.6% ... 5'b11111 ->3.1%" bitfld.long 0x18 3. "DOWNSPREAD,Downspread control 0: Center-Spread 1: Downspread" "Center-Spread,Downspread" newline bitfld.long 0x18 2. "RESETPTR,Active High reset for wave table pointer Internally synchronized to CLKSSCG 0: If modulation is active(RESET=1'b0 DIS-ABLESSCG=1'b0) INTMOD and FRACMOD are updating based on internal wave table. 1: Modulation is stopped and wave table position.." "If modulation is active,Modulation is stopped and wave table position is.." bitfld.long 0x18 1. "DISABLE_SSCG,Active-High Modulator Bypass Control 0: Use Modulator Output. De-Assertion of DISABLE SSCG is synchronous with CLKSSCG 1: Bypass modulator (INTMOD=INTIN FRACMOD=FRACIN). Assertion of DISABLE SSCG is asynchronous" "Use Modulator Output,Bypass modulator" newline bitfld.long 0x18 0. "MOD_RESET,Active High Modulator Reset 1'b0 ->Modulator is operating 1'b1 ->Reset Modulator.INTMOD=12'd20 FRACMOD=24'd00" "0,1" repeat 2. (list 0x1 0x2 )(list 0x0 0x4 ) group.long ($2+0x20)++0x3 line.long 0x0 "PLL_OUT_DIV_$1,pll outside divider register" rbitfld.long 0x0 31. "DIV_BUSY_B,divider b busy indicator 1: busy 0: not busy" "not busy,busy" newline hexmask.long.byte 0x0 16.--19. 1. "DIV_NUM_B,divider b divider number" rbitfld.long 0x0 15. "DIV_BUSY_A,divider a busy indicator 1: busy 0: not busy" "not busy,busy" newline hexmask.long.byte 0x0 0.--3. 1. "DIV_NUM_A,divider a divider number" repeat.end tree.end tree "PLL_VPU" base ad:0xF1450000 group.long 0x0++0x1B line.long 0x0 "PLL_CTRL,pll global control register" rbitfld.long 0x0 31. "LOCK,Lock signal Indicates no cycle slips between the feedback clock and FPFD for 128 consecutive cycles." "0,1" newline bitfld.long 0x0 21. "PLL_DIVD_CG_EN,divider d cg enable" "0,1" bitfld.long 0x0 20. "PLL_DIVC_CG_EN,divider c cg enable" "0,1" newline bitfld.long 0x0 19. "PLL_DIVB_CG_EN,divider b cg enable" "0,1" bitfld.long 0x0 18. "PLL_DIVA_CG_EN,divider a cg enable" "0,1" newline bitfld.long 0x0 17. "BYPASS,PLL bypass. 1: pll bypass FREF is bypassed to FOUTDIV 0: bypass inactive" "bypass inactive,pll bypass" bitfld.long 0x0 16. "PLLPOSTCG_EN,PLL post divider clock gating enable. 1: postdiv clock gating enable 0: post divider clock gating disable." "post divider clock gating disable,postdiv clock gating enable" newline bitfld.long 0x0 4. "FOUTPOSTDIVEN,Post divide power down. 1: FOUTPOSTDIV 4-phase and synchronous clocks are enabled. 0: FOUTPOSTDIV 4-phase and synchronous clocks are powered down (outputs held at 1'b0)" "FOUTPOSTDIV,FOUTPOSTDIV" newline bitfld.long 0x0 3. "FOUT4PHASEEN,Enable of 4 phase clock generator4 phase output is also powered down if FOUTPOSTDIVEN=1'b0. 1: 4-phase and synchronous clocks are enabled. 0: 4-phase and synchronous clocks are powered down (outputs held at 1'b0)." "0,1" bitfld.long 0x0 2. "DACEN,Enable fractional noise canceling DAC in FRAC mode (this has no function in integer mode). 1: Fractional noise canceling DAC is active (default mode). 0: Fractional noise canceling DAC is not active (test mode only)." "Fractional noise canceling DAC is not active,Fractional noise canceling DAC is active" newline bitfld.long 0x0 1. "INT_MODE,int mode or fractional mode 1: integer mode 0: fractional mode" "fractional mode,integer mode" bitfld.long 0x0 0. "PLLEN,PLL enable. 1: pll enable 0: pll disable pll under low power mode." "pll disable,pll enable" line.long 0x4 "PLL_DIV,used to set the pll divide number" bitfld.long 0x4 9.--11. "POSTDIV2,PLL post divide 2 setting (1 to 7) POSTDIV2=0 is unused. Total post divide is POSTDIV1*POSTDIV2 POSTDIV1>= POSTDIV2" "?,POSTDIV2,?,?,?,?,?,?" newline bitfld.long 0x4 6.--8. "POSTDIV1,PLL post divide 1 setting (1 to 7) POSTDIV1=0 is unused. Total post divide is POSTDIV1*POSTDIV2 POSTDIV1>= POSTDIV2" "?,POSTDIV2,?,?,?,?,?,?" hexmask.long.byte 0x4 0.--5. 1. "REFDIV,Reference divide value (1 to 63)" line.long 0x8 "PLL_FBDIV,used to set the FBDIV value" hexmask.long.word 0x8 0.--11. 1. "FBDIV,PLL Feedback divide value (16 to 640 in integer mode 20 to 320 in fractional mode)" line.long 0xC "PLL_FRAC,used to set the FRAC value" hexmask.long.tbyte 0xC 0.--23. 1. "FRAC,Fractional portion of feedback divide value" line.long 0x10 "PLL_DESKEW,used to set pll DESKEW function. normally. the default setting is ok" hexmask.long.word 0x10 6.--17. 1. "DSKEWCALIN,DSKEWCALBYP==1'b0: Initial condition for deskew cali-bration logic. DSKEWCALBYP==1'b1: Override value for deskew cali-bration. It is a signed integer with positive values delaying thereset of the faster path and negative values delaying the.." newline bitfld.long 0x10 3.--5. "DSKEWCALCNT,Programmable counter for deskew calibration loopSelects the number of PFD edges to wait after each deskewcalibration step. Count is defined as 2DS KEWCALCNT+4(e.g. ifDSKEWCALCNT=3'd6 the loop will wait 1024 PFD periodsbef ore trying a new.." "0,1,2,3,4,5,6,7" bitfld.long 0x10 2. "DSKEWCALBYP,Deskew calibration bypass. 1'b0 - use the skew calibration output (whenDSKEW-CALEN=1) to set the phase correction. 1'b1 - use the DSKEWCALIN[11:0] value (whenDSKEW-CALEN=1) to set the phase correction" "use the skew calibration output,use the DSKEWCALIN[11:0] value" newline bitfld.long 0x10 1. "DSKEWFASTCAL,Deskew fast calibration enableSet this to 1 for initial calibration if an initial value is not al-ready knownShould be set to 0 for normal operation" "0,1" bitfld.long 0x10 0. "DSKEWCALEN,Deskew calibration enable to actively adjust for input skew. 1'b0 - skew calibration is disabled. Static phase oset is deter-mined by analog matching only. 1'b1 - skew calibration is enabled. Static phase oset is ad-justed by sensing phase at.." "skew calibration is disabled,skew calibration is enabled" line.long 0x14 "PLL_DESKEW_STA,pll deskew output register" hexmask.long.word 0x14 5.--16. 1. "DSKEWCALOUT,This is the output of either the skew calibration block (if DSKEWCALBYP=0) or a bueredversion of DSKEWCALIN[11:0] (if DSKEWCALBYP=1). It can be used to read out the phase calibration state to use as an override value so that skew calibration.." newline hexmask.long.byte 0x14 1.--4. 1. "DSKEWCALLOCKCNT,Reserved for future use" rbitfld.long 0x14 0. "DSKEWCALLOCK,Asserted when phase lock is achieved when DSKEWCALEN is set to 1'b1." "0,1" line.long 0x18 "PLL_SSMOD,pll spread spectrum setting" hexmask.long.byte 0x18 9.--14. 1. "DIVVAL,Input divider to set modulation frequency. Divide value is DIVVAL+1 For SELEXTWAVE=1'b0: Modulation Freq=Fclksscg/((DIVVAL+1)* 128) For SELEXTWAVE=1'b1: Modulation Freq=Fclksscg/((DIVVAL+1)*EXTMAXADDR)" newline hexmask.long.byte 0x18 4.--8. 1. "SPREAD,Spread Depth Control in 0.1% steps 5'b00001 ->0.1% 5'b00010 ->0.2% ... 5'b10000 ->1.6% ... 5'b11111 ->3.1%" bitfld.long 0x18 3. "DOWNSPREAD,Downspread control 0: Center-Spread 1: Downspread" "Center-Spread,Downspread" newline bitfld.long 0x18 2. "RESETPTR,Active High reset for wave table pointer Internally synchronized to CLKSSCG 0: If modulation is active(RESET=1'b0 DIS-ABLESSCG=1'b0) INTMOD and FRACMOD are updating based on internal wave table. 1: Modulation is stopped and wave table position.." "If modulation is active,Modulation is stopped and wave table position is.." bitfld.long 0x18 1. "DISABLE_SSCG,Active-High Modulator Bypass Control 0: Use Modulator Output. De-Assertion of DISABLE SSCG is synchronous with CLKSSCG 1: Bypass modulator (INTMOD=INTIN FRACMOD=FRACIN). Assertion of DISABLE SSCG is asynchronous" "Use Modulator Output,Bypass modulator" newline bitfld.long 0x18 0. "MOD_RESET,Active High Modulator Reset 1'b0 ->Modulator is operating 1'b1 ->Reset Modulator.INTMOD=12'd20 FRACMOD=24'd00" "0,1" repeat 2. (list 0x1 0x2 )(list 0x0 0x4 ) group.long ($2+0x20)++0x3 line.long 0x0 "PLL_OUT_DIV_$1,pll outside divider register" rbitfld.long 0x0 31. "DIV_BUSY_B,divider b busy indicator 1: busy 0: not busy" "not busy,busy" newline hexmask.long.byte 0x0 16.--19. 1. "DIV_NUM_B,divider b divider number" rbitfld.long 0x0 15. "DIV_BUSY_A,divider a busy indicator 1: busy 0: not busy" "not busy,busy" newline hexmask.long.byte 0x0 0.--3. 1. "DIV_NUM_A,divider a divider number" repeat.end tree.end tree "PLL_GPU1" base ad:0xF1480000 group.long 0x0++0x1B line.long 0x0 "PLL_CTRL,pll global control register" rbitfld.long 0x0 31. "LOCK,Lock signal Indicates no cycle slips between the feedback clock and FPFD for 128 consecutive cycles." "0,1" newline bitfld.long 0x0 21. "PLL_DIVD_CG_EN,divider d cg enable" "0,1" bitfld.long 0x0 20. "PLL_DIVC_CG_EN,divider c cg enable" "0,1" newline bitfld.long 0x0 19. "PLL_DIVB_CG_EN,divider b cg enable" "0,1" bitfld.long 0x0 18. "PLL_DIVA_CG_EN,divider a cg enable" "0,1" newline bitfld.long 0x0 17. "BYPASS,PLL bypass. 1: pll bypass FREF is bypassed to FOUTDIV 0: bypass inactive" "bypass inactive,pll bypass" bitfld.long 0x0 16. "PLLPOSTCG_EN,PLL post divider clock gating enable. 1: postdiv clock gating enable 0: post divider clock gating disable." "post divider clock gating disable,postdiv clock gating enable" newline bitfld.long 0x0 4. "FOUTPOSTDIVEN,Post divide power down. 1: FOUTPOSTDIV 4-phase and synchronous clocks are enabled. 0: FOUTPOSTDIV 4-phase and synchronous clocks are powered down (outputs held at 1'b0)" "FOUTPOSTDIV,FOUTPOSTDIV" newline bitfld.long 0x0 3. "FOUT4PHASEEN,Enable of 4 phase clock generator4 phase output is also powered down if FOUTPOSTDIVEN=1'b0. 1: 4-phase and synchronous clocks are enabled. 0: 4-phase and synchronous clocks are powered down (outputs held at 1'b0)." "0,1" bitfld.long 0x0 2. "DACEN,Enable fractional noise canceling DAC in FRAC mode (this has no function in integer mode). 1: Fractional noise canceling DAC is active (default mode). 0: Fractional noise canceling DAC is not active (test mode only)." "Fractional noise canceling DAC is not active,Fractional noise canceling DAC is active" newline bitfld.long 0x0 1. "INT_MODE,int mode or fractional mode 1: integer mode 0: fractional mode" "fractional mode,integer mode" bitfld.long 0x0 0. "PLLEN,PLL enable. 1: pll enable 0: pll disable pll under low power mode." "pll disable,pll enable" line.long 0x4 "PLL_DIV,used to set the pll divide number" bitfld.long 0x4 9.--11. "POSTDIV2,PLL post divide 2 setting (1 to 7) POSTDIV2=0 is unused. Total post divide is POSTDIV1*POSTDIV2 POSTDIV1>= POSTDIV2" "?,POSTDIV2,?,?,?,?,?,?" newline bitfld.long 0x4 6.--8. "POSTDIV1,PLL post divide 1 setting (1 to 7) POSTDIV1=0 is unused. Total post divide is POSTDIV1*POSTDIV2 POSTDIV1>= POSTDIV2" "?,POSTDIV2,?,?,?,?,?,?" hexmask.long.byte 0x4 0.--5. 1. "REFDIV,Reference divide value (1 to 63)" line.long 0x8 "PLL_FBDIV,used to set the FBDIV value" hexmask.long.word 0x8 0.--11. 1. "FBDIV,PLL Feedback divide value (16 to 640 in integer mode 20 to 320 in fractional mode)" line.long 0xC "PLL_FRAC,used to set the FRAC value" hexmask.long.tbyte 0xC 0.--23. 1. "FRAC,Fractional portion of feedback divide value" line.long 0x10 "PLL_DESKEW,used to set pll DESKEW function. normally. the default setting is ok" hexmask.long.word 0x10 6.--17. 1. "DSKEWCALIN,DSKEWCALBYP==1'b0: Initial condition for deskew cali-bration logic. DSKEWCALBYP==1'b1: Override value for deskew cali-bration. It is a signed integer with positive values delaying thereset of the faster path and negative values delaying the.." newline bitfld.long 0x10 3.--5. "DSKEWCALCNT,Programmable counter for deskew calibration loopSelects the number of PFD edges to wait after each deskewcalibration step. Count is defined as 2DS KEWCALCNT+4(e.g. ifDSKEWCALCNT=3'd6 the loop will wait 1024 PFD periodsbef ore trying a new.." "0,1,2,3,4,5,6,7" bitfld.long 0x10 2. "DSKEWCALBYP,Deskew calibration bypass. 1'b0 - use the skew calibration output (whenDSKEW-CALEN=1) to set the phase correction. 1'b1 - use the DSKEWCALIN[11:0] value (whenDSKEW-CALEN=1) to set the phase correction" "use the skew calibration output,use the DSKEWCALIN[11:0] value" newline bitfld.long 0x10 1. "DSKEWFASTCAL,Deskew fast calibration enableSet this to 1 for initial calibration if an initial value is not al-ready knownShould be set to 0 for normal operation" "0,1" bitfld.long 0x10 0. "DSKEWCALEN,Deskew calibration enable to actively adjust for input skew. 1'b0 - skew calibration is disabled. Static phase oset is deter-mined by analog matching only. 1'b1 - skew calibration is enabled. Static phase oset is ad-justed by sensing phase at.." "skew calibration is disabled,skew calibration is enabled" line.long 0x14 "PLL_DESKEW_STA,pll deskew output register" hexmask.long.word 0x14 5.--16. 1. "DSKEWCALOUT,This is the output of either the skew calibration block (if DSKEWCALBYP=0) or a bueredversion of DSKEWCALIN[11:0] (if DSKEWCALBYP=1). It can be used to read out the phase calibration state to use as an override value so that skew calibration.." newline hexmask.long.byte 0x14 1.--4. 1. "DSKEWCALLOCKCNT,Reserved for future use" rbitfld.long 0x14 0. "DSKEWCALLOCK,Asserted when phase lock is achieved when DSKEWCALEN is set to 1'b1." "0,1" line.long 0x18 "PLL_SSMOD,pll spread spectrum setting" hexmask.long.byte 0x18 9.--14. 1. "DIVVAL,Input divider to set modulation frequency. Divide value is DIVVAL+1 For SELEXTWAVE=1'b0: Modulation Freq=Fclksscg/((DIVVAL+1)* 128) For SELEXTWAVE=1'b1: Modulation Freq=Fclksscg/((DIVVAL+1)*EXTMAXADDR)" newline hexmask.long.byte 0x18 4.--8. 1. "SPREAD,Spread Depth Control in 0.1% steps 5'b00001 ->0.1% 5'b00010 ->0.2% ... 5'b10000 ->1.6% ... 5'b11111 ->3.1%" bitfld.long 0x18 3. "DOWNSPREAD,Downspread control 0: Center-Spread 1: Downspread" "Center-Spread,Downspread" newline bitfld.long 0x18 2. "RESETPTR,Active High reset for wave table pointer Internally synchronized to CLKSSCG 0: If modulation is active(RESET=1'b0 DIS-ABLESSCG=1'b0) INTMOD and FRACMOD are updating based on internal wave table. 1: Modulation is stopped and wave table position.." "If modulation is active,Modulation is stopped and wave table position is.." bitfld.long 0x18 1. "DISABLE_SSCG,Active-High Modulator Bypass Control 0: Use Modulator Output. De-Assertion of DISABLE SSCG is synchronous with CLKSSCG 1: Bypass modulator (INTMOD=INTIN FRACMOD=FRACIN). Assertion of DISABLE SSCG is asynchronous" "Use Modulator Output,Bypass modulator" newline bitfld.long 0x18 0. "MOD_RESET,Active High Modulator Reset 1'b0 ->Modulator is operating 1'b1 ->Reset Modulator.INTMOD=12'd20 FRACMOD=24'd00" "0,1" repeat 2. (list 0x1 0x2 )(list 0x0 0x4 ) group.long ($2+0x20)++0x3 line.long 0x0 "PLL_OUT_DIV_$1,pll outside divider register" rbitfld.long 0x0 31. "DIV_BUSY_B,divider b busy indicator 1: busy 0: not busy" "not busy,busy" newline hexmask.long.byte 0x0 16.--19. 1. "DIV_NUM_B,divider b divider number" rbitfld.long 0x0 15. "DIV_BUSY_A,divider a busy indicator 1: busy 0: not busy" "not busy,busy" newline hexmask.long.byte 0x0 0.--3. 1. "DIV_NUM_A,divider a divider number" repeat.end tree.end tree "PLL_GPU2" base ad:0xF1490000 group.long 0x0++0x1B line.long 0x0 "PLL_CTRL,pll global control register" rbitfld.long 0x0 31. "LOCK,Lock signal Indicates no cycle slips between the feedback clock and FPFD for 128 consecutive cycles." "0,1" newline bitfld.long 0x0 21. "PLL_DIVD_CG_EN,divider d cg enable" "0,1" bitfld.long 0x0 20. "PLL_DIVC_CG_EN,divider c cg enable" "0,1" newline bitfld.long 0x0 19. "PLL_DIVB_CG_EN,divider b cg enable" "0,1" bitfld.long 0x0 18. "PLL_DIVA_CG_EN,divider a cg enable" "0,1" newline bitfld.long 0x0 17. "BYPASS,PLL bypass. 1: pll bypass FREF is bypassed to FOUTDIV 0: bypass inactive" "bypass inactive,pll bypass" bitfld.long 0x0 16. "PLLPOSTCG_EN,PLL post divider clock gating enable. 1: postdiv clock gating enable 0: post divider clock gating disable." "post divider clock gating disable,postdiv clock gating enable" newline bitfld.long 0x0 4. "FOUTPOSTDIVEN,Post divide power down. 1: FOUTPOSTDIV 4-phase and synchronous clocks are enabled. 0: FOUTPOSTDIV 4-phase and synchronous clocks are powered down (outputs held at 1'b0)" "FOUTPOSTDIV,FOUTPOSTDIV" newline bitfld.long 0x0 3. "FOUT4PHASEEN,Enable of 4 phase clock generator4 phase output is also powered down if FOUTPOSTDIVEN=1'b0. 1: 4-phase and synchronous clocks are enabled. 0: 4-phase and synchronous clocks are powered down (outputs held at 1'b0)." "0,1" bitfld.long 0x0 2. "DACEN,Enable fractional noise canceling DAC in FRAC mode (this has no function in integer mode). 1: Fractional noise canceling DAC is active (default mode). 0: Fractional noise canceling DAC is not active (test mode only)." "Fractional noise canceling DAC is not active,Fractional noise canceling DAC is active" newline bitfld.long 0x0 1. "INT_MODE,int mode or fractional mode 1: integer mode 0: fractional mode" "fractional mode,integer mode" bitfld.long 0x0 0. "PLLEN,PLL enable. 1: pll enable 0: pll disable pll under low power mode." "pll disable,pll enable" line.long 0x4 "PLL_DIV,used to set the pll divide number" bitfld.long 0x4 9.--11. "POSTDIV2,PLL post divide 2 setting (1 to 7) POSTDIV2=0 is unused. Total post divide is POSTDIV1*POSTDIV2 POSTDIV1>= POSTDIV2" "?,POSTDIV2,?,?,?,?,?,?" newline bitfld.long 0x4 6.--8. "POSTDIV1,PLL post divide 1 setting (1 to 7) POSTDIV1=0 is unused. Total post divide is POSTDIV1*POSTDIV2 POSTDIV1>= POSTDIV2" "?,POSTDIV2,?,?,?,?,?,?" hexmask.long.byte 0x4 0.--5. 1. "REFDIV,Reference divide value (1 to 63)" line.long 0x8 "PLL_FBDIV,used to set the FBDIV value" hexmask.long.word 0x8 0.--11. 1. "FBDIV,PLL Feedback divide value (16 to 640 in integer mode 20 to 320 in fractional mode)" line.long 0xC "PLL_FRAC,used to set the FRAC value" hexmask.long.tbyte 0xC 0.--23. 1. "FRAC,Fractional portion of feedback divide value" line.long 0x10 "PLL_DESKEW,used to set pll DESKEW function. normally. the default setting is ok" hexmask.long.word 0x10 6.--17. 1. "DSKEWCALIN,DSKEWCALBYP==1'b0: Initial condition for deskew cali-bration logic. DSKEWCALBYP==1'b1: Override value for deskew cali-bration. It is a signed integer with positive values delaying thereset of the faster path and negative values delaying the.." newline bitfld.long 0x10 3.--5. "DSKEWCALCNT,Programmable counter for deskew calibration loopSelects the number of PFD edges to wait after each deskewcalibration step. Count is defined as 2DS KEWCALCNT+4(e.g. ifDSKEWCALCNT=3'd6 the loop will wait 1024 PFD periodsbef ore trying a new.." "0,1,2,3,4,5,6,7" bitfld.long 0x10 2. "DSKEWCALBYP,Deskew calibration bypass. 1'b0 - use the skew calibration output (whenDSKEW-CALEN=1) to set the phase correction. 1'b1 - use the DSKEWCALIN[11:0] value (whenDSKEW-CALEN=1) to set the phase correction" "use the skew calibration output,use the DSKEWCALIN[11:0] value" newline bitfld.long 0x10 1. "DSKEWFASTCAL,Deskew fast calibration enableSet this to 1 for initial calibration if an initial value is not al-ready knownShould be set to 0 for normal operation" "0,1" bitfld.long 0x10 0. "DSKEWCALEN,Deskew calibration enable to actively adjust for input skew. 1'b0 - skew calibration is disabled. Static phase oset is deter-mined by analog matching only. 1'b1 - skew calibration is enabled. Static phase oset is ad-justed by sensing phase at.." "skew calibration is disabled,skew calibration is enabled" line.long 0x14 "PLL_DESKEW_STA,pll deskew output register" hexmask.long.word 0x14 5.--16. 1. "DSKEWCALOUT,This is the output of either the skew calibration block (if DSKEWCALBYP=0) or a bueredversion of DSKEWCALIN[11:0] (if DSKEWCALBYP=1). It can be used to read out the phase calibration state to use as an override value so that skew calibration.." newline hexmask.long.byte 0x14 1.--4. 1. "DSKEWCALLOCKCNT,Reserved for future use" rbitfld.long 0x14 0. "DSKEWCALLOCK,Asserted when phase lock is achieved when DSKEWCALEN is set to 1'b1." "0,1" line.long 0x18 "PLL_SSMOD,pll spread spectrum setting" hexmask.long.byte 0x18 9.--14. 1. "DIVVAL,Input divider to set modulation frequency. Divide value is DIVVAL+1 For SELEXTWAVE=1'b0: Modulation Freq=Fclksscg/((DIVVAL+1)* 128) For SELEXTWAVE=1'b1: Modulation Freq=Fclksscg/((DIVVAL+1)*EXTMAXADDR)" newline hexmask.long.byte 0x18 4.--8. 1. "SPREAD,Spread Depth Control in 0.1% steps 5'b00001 ->0.1% 5'b00010 ->0.2% ... 5'b10000 ->1.6% ... 5'b11111 ->3.1%" bitfld.long 0x18 3. "DOWNSPREAD,Downspread control 0: Center-Spread 1: Downspread" "Center-Spread,Downspread" newline bitfld.long 0x18 2. "RESETPTR,Active High reset for wave table pointer Internally synchronized to CLKSSCG 0: If modulation is active(RESET=1'b0 DIS-ABLESSCG=1'b0) INTMOD and FRACMOD are updating based on internal wave table. 1: Modulation is stopped and wave table position.." "If modulation is active,Modulation is stopped and wave table position is.." bitfld.long 0x18 1. "DISABLE_SSCG,Active-High Modulator Bypass Control 0: Use Modulator Output. De-Assertion of DISABLE SSCG is synchronous with CLKSSCG 1: Bypass modulator (INTMOD=INTIN FRACMOD=FRACIN). Assertion of DISABLE SSCG is asynchronous" "Use Modulator Output,Bypass modulator" newline bitfld.long 0x18 0. "MOD_RESET,Active High Modulator Reset 1'b0 ->Modulator is operating 1'b1 ->Reset Modulator.INTMOD=12'd20 FRACMOD=24'd00" "0,1" repeat 2. (list 0x1 0x2 )(list 0x0 0x4 ) group.long ($2+0x20)++0x3 line.long 0x0 "PLL_OUT_DIV_$1,pll outside divider register" rbitfld.long 0x0 31. "DIV_BUSY_B,divider b busy indicator 1: busy 0: not busy" "not busy,busy" newline hexmask.long.byte 0x0 16.--19. 1. "DIV_NUM_B,divider b divider number" rbitfld.long 0x0 15. "DIV_BUSY_A,divider a busy indicator 1: busy 0: not busy" "not busy,busy" newline hexmask.long.byte 0x0 0.--3. 1. "DIV_NUM_A,divider a divider number" repeat.end tree.end tree "PLL_CPU_CORE" base ad:0xF14A0000 group.long 0x0++0x1B line.long 0x0 "PLL_CTRL,pll global control register" rbitfld.long 0x0 31. "LOCK,Lock signal Indicates no cycle slips between the feedback clock and FPFD for 128 consecutive cycles." "0,1" newline bitfld.long 0x0 21. "PLL_DIVD_CG_EN,divider d cg enable" "0,1" bitfld.long 0x0 20. "PLL_DIVC_CG_EN,divider c cg enable" "0,1" newline bitfld.long 0x0 19. "PLL_DIVB_CG_EN,divider b cg enable" "0,1" bitfld.long 0x0 18. "PLL_DIVA_CG_EN,divider a cg enable" "0,1" newline bitfld.long 0x0 17. "BYPASS,PLL bypass. 1: pll bypass FREF is bypassed to FOUTDIV 0: bypass inactive" "bypass inactive,pll bypass" bitfld.long 0x0 16. "PLLPOSTCG_EN,PLL post divider clock gating enable. 1: postdiv clock gating enable 0: post divider clock gating disable." "post divider clock gating disable,postdiv clock gating enable" newline bitfld.long 0x0 4. "FOUTPOSTDIVEN,Post divide power down. 1: FOUTPOSTDIV 4-phase and synchronous clocks are enabled. 0: FOUTPOSTDIV 4-phase and synchronous clocks are powered down (outputs held at 1'b0)" "FOUTPOSTDIV,FOUTPOSTDIV" newline bitfld.long 0x0 3. "FOUT4PHASEEN,Enable of 4 phase clock generator4 phase output is also powered down if FOUTPOSTDIVEN=1'b0. 1: 4-phase and synchronous clocks are enabled. 0: 4-phase and synchronous clocks are powered down (outputs held at 1'b0)." "0,1" bitfld.long 0x0 2. "DACEN,Enable fractional noise canceling DAC in FRAC mode (this has no function in integer mode). 1: Fractional noise canceling DAC is active (default mode). 0: Fractional noise canceling DAC is not active (test mode only)." "Fractional noise canceling DAC is not active,Fractional noise canceling DAC is active" newline bitfld.long 0x0 1. "INT_MODE,int mode or fractional mode 1: integer mode 0: fractional mode" "fractional mode,integer mode" bitfld.long 0x0 0. "PLLEN,PLL enable. 1: pll enable 0: pll disable pll under low power mode." "pll disable,pll enable" line.long 0x4 "PLL_DIV,used to set the pll divide number" bitfld.long 0x4 9.--11. "POSTDIV2,PLL post divide 2 setting (1 to 7) POSTDIV2=0 is unused. Total post divide is POSTDIV1*POSTDIV2 POSTDIV1>= POSTDIV2" "?,POSTDIV2,?,?,?,?,?,?" newline bitfld.long 0x4 6.--8. "POSTDIV1,PLL post divide 1 setting (1 to 7) POSTDIV1=0 is unused. Total post divide is POSTDIV1*POSTDIV2 POSTDIV1>= POSTDIV2" "?,POSTDIV2,?,?,?,?,?,?" hexmask.long.byte 0x4 0.--5. 1. "REFDIV,Reference divide value (1 to 63)" line.long 0x8 "PLL_FBDIV,used to set the FBDIV value" hexmask.long.word 0x8 0.--11. 1. "FBDIV,PLL Feedback divide value (16 to 640 in integer mode 20 to 320 in fractional mode)" line.long 0xC "PLL_FRAC,used to set the FRAC value" hexmask.long.tbyte 0xC 0.--23. 1. "FRAC,Fractional portion of feedback divide value" line.long 0x10 "PLL_DESKEW,used to set pll DESKEW function. normally. the default setting is ok" hexmask.long.word 0x10 6.--17. 1. "DSKEWCALIN,DSKEWCALBYP==1'b0: Initial condition for deskew cali-bration logic. DSKEWCALBYP==1'b1: Override value for deskew cali-bration. It is a signed integer with positive values delaying thereset of the faster path and negative values delaying the.." newline bitfld.long 0x10 3.--5. "DSKEWCALCNT,Programmable counter for deskew calibration loopSelects the number of PFD edges to wait after each deskewcalibration step. Count is defined as 2DS KEWCALCNT+4(e.g. ifDSKEWCALCNT=3'd6 the loop will wait 1024 PFD periodsbef ore trying a new.." "0,1,2,3,4,5,6,7" bitfld.long 0x10 2. "DSKEWCALBYP,Deskew calibration bypass. 1'b0 - use the skew calibration output (whenDSKEW-CALEN=1) to set the phase correction. 1'b1 - use the DSKEWCALIN[11:0] value (whenDSKEW-CALEN=1) to set the phase correction" "use the skew calibration output,use the DSKEWCALIN[11:0] value" newline bitfld.long 0x10 1. "DSKEWFASTCAL,Deskew fast calibration enableSet this to 1 for initial calibration if an initial value is not al-ready knownShould be set to 0 for normal operation" "0,1" bitfld.long 0x10 0. "DSKEWCALEN,Deskew calibration enable to actively adjust for input skew. 1'b0 - skew calibration is disabled. Static phase oset is deter-mined by analog matching only. 1'b1 - skew calibration is enabled. Static phase oset is ad-justed by sensing phase at.." "skew calibration is disabled,skew calibration is enabled" line.long 0x14 "PLL_DESKEW_STA,pll deskew output register" hexmask.long.word 0x14 5.--16. 1. "DSKEWCALOUT,This is the output of either the skew calibration block (if DSKEWCALBYP=0) or a bueredversion of DSKEWCALIN[11:0] (if DSKEWCALBYP=1). It can be used to read out the phase calibration state to use as an override value so that skew calibration.." newline hexmask.long.byte 0x14 1.--4. 1. "DSKEWCALLOCKCNT,Reserved for future use" rbitfld.long 0x14 0. "DSKEWCALLOCK,Asserted when phase lock is achieved when DSKEWCALEN is set to 1'b1." "0,1" line.long 0x18 "PLL_SSMOD,pll spread spectrum setting" hexmask.long.byte 0x18 9.--14. 1. "DIVVAL,Input divider to set modulation frequency. Divide value is DIVVAL+1 For SELEXTWAVE=1'b0: Modulation Freq=Fclksscg/((DIVVAL+1)* 128) For SELEXTWAVE=1'b1: Modulation Freq=Fclksscg/((DIVVAL+1)*EXTMAXADDR)" newline hexmask.long.byte 0x18 4.--8. 1. "SPREAD,Spread Depth Control in 0.1% steps 5'b00001 ->0.1% 5'b00010 ->0.2% ... 5'b10000 ->1.6% ... 5'b11111 ->3.1%" bitfld.long 0x18 3. "DOWNSPREAD,Downspread control 0: Center-Spread 1: Downspread" "Center-Spread,Downspread" newline bitfld.long 0x18 2. "RESETPTR,Active High reset for wave table pointer Internally synchronized to CLKSSCG 0: If modulation is active(RESET=1'b0 DIS-ABLESSCG=1'b0) INTMOD and FRACMOD are updating based on internal wave table. 1: Modulation is stopped and wave table position.." "If modulation is active,Modulation is stopped and wave table position is.." bitfld.long 0x18 1. "DISABLE_SSCG,Active-High Modulator Bypass Control 0: Use Modulator Output. De-Assertion of DISABLE SSCG is synchronous with CLKSSCG 1: Bypass modulator (INTMOD=INTIN FRACMOD=FRACIN). Assertion of DISABLE SSCG is asynchronous" "Use Modulator Output,Bypass modulator" newline bitfld.long 0x18 0. "MOD_RESET,Active High Modulator Reset 1'b0 ->Modulator is operating 1'b1 ->Reset Modulator.INTMOD=12'd20 FRACMOD=24'd00" "0,1" repeat 2. (list 0x1 0x2 )(list 0x0 0x4 ) group.long ($2+0x20)++0x3 line.long 0x0 "PLL_OUT_DIV_$1,pll outside divider register" rbitfld.long 0x0 31. "DIV_BUSY_B,divider b busy indicator 1: busy 0: not busy" "not busy,busy" newline hexmask.long.byte 0x0 16.--19. 1. "DIV_NUM_B,divider b divider number" rbitfld.long 0x0 15. "DIV_BUSY_A,divider a busy indicator 1: busy 0: not busy" "not busy,busy" newline hexmask.long.byte 0x0 0.--3. 1. "DIV_NUM_A,divider a divider number" repeat.end tree.end tree "PLL_CPU" base ad:0xF14B0000 group.long 0x0++0x1B line.long 0x0 "PLL_CTRL,pll global control register" rbitfld.long 0x0 31. "LOCK,Lock signal Indicates no cycle slips between the feedback clock and FPFD for 128 consecutive cycles." "0,1" newline bitfld.long 0x0 21. "PLL_DIVD_CG_EN,divider d cg enable" "0,1" bitfld.long 0x0 20. "PLL_DIVC_CG_EN,divider c cg enable" "0,1" newline bitfld.long 0x0 19. "PLL_DIVB_CG_EN,divider b cg enable" "0,1" bitfld.long 0x0 18. "PLL_DIVA_CG_EN,divider a cg enable" "0,1" newline bitfld.long 0x0 17. "BYPASS,PLL bypass. 1: pll bypass FREF is bypassed to FOUTDIV 0: bypass inactive" "bypass inactive,pll bypass" bitfld.long 0x0 16. "PLLPOSTCG_EN,PLL post divider clock gating enable. 1: postdiv clock gating enable 0: post divider clock gating disable." "post divider clock gating disable,postdiv clock gating enable" newline bitfld.long 0x0 4. "FOUTPOSTDIVEN,Post divide power down. 1: FOUTPOSTDIV 4-phase and synchronous clocks are enabled. 0: FOUTPOSTDIV 4-phase and synchronous clocks are powered down (outputs held at 1'b0)" "FOUTPOSTDIV,FOUTPOSTDIV" newline bitfld.long 0x0 3. "FOUT4PHASEEN,Enable of 4 phase clock generator4 phase output is also powered down if FOUTPOSTDIVEN=1'b0. 1: 4-phase and synchronous clocks are enabled. 0: 4-phase and synchronous clocks are powered down (outputs held at 1'b0)." "0,1" bitfld.long 0x0 2. "DACEN,Enable fractional noise canceling DAC in FRAC mode (this has no function in integer mode). 1: Fractional noise canceling DAC is active (default mode). 0: Fractional noise canceling DAC is not active (test mode only)." "Fractional noise canceling DAC is not active,Fractional noise canceling DAC is active" newline bitfld.long 0x0 1. "INT_MODE,int mode or fractional mode 1: integer mode 0: fractional mode" "fractional mode,integer mode" bitfld.long 0x0 0. "PLLEN,PLL enable. 1: pll enable 0: pll disable pll under low power mode." "pll disable,pll enable" line.long 0x4 "PLL_DIV,used to set the pll divide number" bitfld.long 0x4 9.--11. "POSTDIV2,PLL post divide 2 setting (1 to 7) POSTDIV2=0 is unused. Total post divide is POSTDIV1*POSTDIV2 POSTDIV1>= POSTDIV2" "?,POSTDIV2,?,?,?,?,?,?" newline bitfld.long 0x4 6.--8. "POSTDIV1,PLL post divide 1 setting (1 to 7) POSTDIV1=0 is unused. Total post divide is POSTDIV1*POSTDIV2 POSTDIV1>= POSTDIV2" "?,POSTDIV2,?,?,?,?,?,?" hexmask.long.byte 0x4 0.--5. 1. "REFDIV,Reference divide value (1 to 63)" line.long 0x8 "PLL_FBDIV,used to set the FBDIV value" hexmask.long.word 0x8 0.--11. 1. "FBDIV,PLL Feedback divide value (16 to 640 in integer mode 20 to 320 in fractional mode)" line.long 0xC "PLL_FRAC,used to set the FRAC value" hexmask.long.tbyte 0xC 0.--23. 1. "FRAC,Fractional portion of feedback divide value" line.long 0x10 "PLL_DESKEW,used to set pll DESKEW function. normally. the default setting is ok" hexmask.long.word 0x10 6.--17. 1. "DSKEWCALIN,DSKEWCALBYP==1'b0: Initial condition for deskew cali-bration logic. DSKEWCALBYP==1'b1: Override value for deskew cali-bration. It is a signed integer with positive values delaying thereset of the faster path and negative values delaying the.." newline bitfld.long 0x10 3.--5. "DSKEWCALCNT,Programmable counter for deskew calibration loopSelects the number of PFD edges to wait after each deskewcalibration step. Count is defined as 2DS KEWCALCNT+4(e.g. ifDSKEWCALCNT=3'd6 the loop will wait 1024 PFD periodsbef ore trying a new.." "0,1,2,3,4,5,6,7" bitfld.long 0x10 2. "DSKEWCALBYP,Deskew calibration bypass. 1'b0 - use the skew calibration output (whenDSKEW-CALEN=1) to set the phase correction. 1'b1 - use the DSKEWCALIN[11:0] value (whenDSKEW-CALEN=1) to set the phase correction" "use the skew calibration output,use the DSKEWCALIN[11:0] value" newline bitfld.long 0x10 1. "DSKEWFASTCAL,Deskew fast calibration enableSet this to 1 for initial calibration if an initial value is not al-ready knownShould be set to 0 for normal operation" "0,1" bitfld.long 0x10 0. "DSKEWCALEN,Deskew calibration enable to actively adjust for input skew. 1'b0 - skew calibration is disabled. Static phase oset is deter-mined by analog matching only. 1'b1 - skew calibration is enabled. Static phase oset is ad-justed by sensing phase at.." "skew calibration is disabled,skew calibration is enabled" line.long 0x14 "PLL_DESKEW_STA,pll deskew output register" hexmask.long.word 0x14 5.--16. 1. "DSKEWCALOUT,This is the output of either the skew calibration block (if DSKEWCALBYP=0) or a bueredversion of DSKEWCALIN[11:0] (if DSKEWCALBYP=1). It can be used to read out the phase calibration state to use as an override value so that skew calibration.." newline hexmask.long.byte 0x14 1.--4. 1. "DSKEWCALLOCKCNT,Reserved for future use" rbitfld.long 0x14 0. "DSKEWCALLOCK,Asserted when phase lock is achieved when DSKEWCALEN is set to 1'b1." "0,1" line.long 0x18 "PLL_SSMOD,pll spread spectrum setting" hexmask.long.byte 0x18 9.--14. 1. "DIVVAL,Input divider to set modulation frequency. Divide value is DIVVAL+1 For SELEXTWAVE=1'b0: Modulation Freq=Fclksscg/((DIVVAL+1)* 128) For SELEXTWAVE=1'b1: Modulation Freq=Fclksscg/((DIVVAL+1)*EXTMAXADDR)" newline hexmask.long.byte 0x18 4.--8. 1. "SPREAD,Spread Depth Control in 0.1% steps 5'b00001 ->0.1% 5'b00010 ->0.2% ... 5'b10000 ->1.6% ... 5'b11111 ->3.1%" bitfld.long 0x18 3. "DOWNSPREAD,Downspread control 0: Center-Spread 1: Downspread" "Center-Spread,Downspread" newline bitfld.long 0x18 2. "RESETPTR,Active High reset for wave table pointer Internally synchronized to CLKSSCG 0: If modulation is active(RESET=1'b0 DIS-ABLESSCG=1'b0) INTMOD and FRACMOD are updating based on internal wave table. 1: Modulation is stopped and wave table position.." "If modulation is active,Modulation is stopped and wave table position is.." bitfld.long 0x18 1. "DISABLE_SSCG,Active-High Modulator Bypass Control 0: Use Modulator Output. De-Assertion of DISABLE SSCG is synchronous with CLKSSCG 1: Bypass modulator (INTMOD=INTIN FRACMOD=FRACIN). Assertion of DISABLE SSCG is asynchronous" "Use Modulator Output,Bypass modulator" newline bitfld.long 0x18 0. "MOD_RESET,Active High Modulator Reset 1'b0 ->Modulator is operating 1'b1 ->Reset Modulator.INTMOD=12'd20 FRACMOD=24'd00" "0,1" repeat 2. (list 0x1 0x2 )(list 0x0 0x4 ) group.long ($2+0x20)++0x3 line.long 0x0 "PLL_OUT_DIV_$1,pll outside divider register" rbitfld.long 0x0 31. "DIV_BUSY_B,divider b busy indicator 1: busy 0: not busy" "not busy,busy" newline hexmask.long.byte 0x0 16.--19. 1. "DIV_NUM_B,divider b divider number" rbitfld.long 0x0 15. "DIV_BUSY_A,divider a busy indicator 1: busy 0: not busy" "not busy,busy" newline hexmask.long.byte 0x0 0.--3. 1. "DIV_NUM_A,divider a divider number" repeat.end tree.end tree "PLL_CPU_DSU" base ad:0xF14D0000 group.long 0x0++0x1B line.long 0x0 "PLL_CTRL,pll global control register" rbitfld.long 0x0 31. "LOCK,Lock signal Indicates no cycle slips between the feedback clock and FPFD for 128 consecutive cycles." "0,1" newline bitfld.long 0x0 21. "PLL_DIVD_CG_EN,divider d cg enable" "0,1" bitfld.long 0x0 20. "PLL_DIVC_CG_EN,divider c cg enable" "0,1" newline bitfld.long 0x0 19. "PLL_DIVB_CG_EN,divider b cg enable" "0,1" bitfld.long 0x0 18. "PLL_DIVA_CG_EN,divider a cg enable" "0,1" newline bitfld.long 0x0 17. "BYPASS,PLL bypass. 1: pll bypass FREF is bypassed to FOUTDIV 0: bypass inactive" "bypass inactive,pll bypass" bitfld.long 0x0 16. "PLLPOSTCG_EN,PLL post divider clock gating enable. 1: postdiv clock gating enable 0: post divider clock gating disable." "post divider clock gating disable,postdiv clock gating enable" newline bitfld.long 0x0 4. "FOUTPOSTDIVEN,Post divide power down. 1: FOUTPOSTDIV 4-phase and synchronous clocks are enabled. 0: FOUTPOSTDIV 4-phase and synchronous clocks are powered down (outputs held at 1'b0)" "FOUTPOSTDIV,FOUTPOSTDIV" newline bitfld.long 0x0 3. "FOUT4PHASEEN,Enable of 4 phase clock generator4 phase output is also powered down if FOUTPOSTDIVEN=1'b0. 1: 4-phase and synchronous clocks are enabled. 0: 4-phase and synchronous clocks are powered down (outputs held at 1'b0)." "0,1" bitfld.long 0x0 2. "DACEN,Enable fractional noise canceling DAC in FRAC mode (this has no function in integer mode). 1: Fractional noise canceling DAC is active (default mode). 0: Fractional noise canceling DAC is not active (test mode only)." "Fractional noise canceling DAC is not active,Fractional noise canceling DAC is active" newline bitfld.long 0x0 1. "INT_MODE,int mode or fractional mode 1: integer mode 0: fractional mode" "fractional mode,integer mode" bitfld.long 0x0 0. "PLLEN,PLL enable. 1: pll enable 0: pll disable pll under low power mode." "pll disable,pll enable" line.long 0x4 "PLL_DIV,used to set the pll divide number" bitfld.long 0x4 9.--11. "POSTDIV2,PLL post divide 2 setting (1 to 7) POSTDIV2=0 is unused. Total post divide is POSTDIV1*POSTDIV2 POSTDIV1>= POSTDIV2" "?,POSTDIV2,?,?,?,?,?,?" newline bitfld.long 0x4 6.--8. "POSTDIV1,PLL post divide 1 setting (1 to 7) POSTDIV1=0 is unused. Total post divide is POSTDIV1*POSTDIV2 POSTDIV1>= POSTDIV2" "?,POSTDIV2,?,?,?,?,?,?" hexmask.long.byte 0x4 0.--5. 1. "REFDIV,Reference divide value (1 to 63)" line.long 0x8 "PLL_FBDIV,used to set the FBDIV value" hexmask.long.word 0x8 0.--11. 1. "FBDIV,PLL Feedback divide value (16 to 640 in integer mode 20 to 320 in fractional mode)" line.long 0xC "PLL_FRAC,used to set the FRAC value" hexmask.long.tbyte 0xC 0.--23. 1. "FRAC,Fractional portion of feedback divide value" line.long 0x10 "PLL_DESKEW,used to set pll DESKEW function. normally. the default setting is ok" hexmask.long.word 0x10 6.--17. 1. "DSKEWCALIN,DSKEWCALBYP==1'b0: Initial condition for deskew cali-bration logic. DSKEWCALBYP==1'b1: Override value for deskew cali-bration. It is a signed integer with positive values delaying thereset of the faster path and negative values delaying the.." newline bitfld.long 0x10 3.--5. "DSKEWCALCNT,Programmable counter for deskew calibration loopSelects the number of PFD edges to wait after each deskewcalibration step. Count is defined as 2DS KEWCALCNT+4(e.g. ifDSKEWCALCNT=3'd6 the loop will wait 1024 PFD periodsbef ore trying a new.." "0,1,2,3,4,5,6,7" bitfld.long 0x10 2. "DSKEWCALBYP,Deskew calibration bypass. 1'b0 - use the skew calibration output (whenDSKEW-CALEN=1) to set the phase correction. 1'b1 - use the DSKEWCALIN[11:0] value (whenDSKEW-CALEN=1) to set the phase correction" "use the skew calibration output,use the DSKEWCALIN[11:0] value" newline bitfld.long 0x10 1. "DSKEWFASTCAL,Deskew fast calibration enableSet this to 1 for initial calibration if an initial value is not al-ready knownShould be set to 0 for normal operation" "0,1" bitfld.long 0x10 0. "DSKEWCALEN,Deskew calibration enable to actively adjust for input skew. 1'b0 - skew calibration is disabled. Static phase oset is deter-mined by analog matching only. 1'b1 - skew calibration is enabled. Static phase oset is ad-justed by sensing phase at.." "skew calibration is disabled,skew calibration is enabled" line.long 0x14 "PLL_DESKEW_STA,pll deskew output register" hexmask.long.word 0x14 5.--16. 1. "DSKEWCALOUT,This is the output of either the skew calibration block (if DSKEWCALBYP=0) or a bueredversion of DSKEWCALIN[11:0] (if DSKEWCALBYP=1). It can be used to read out the phase calibration state to use as an override value so that skew calibration.." newline hexmask.long.byte 0x14 1.--4. 1. "DSKEWCALLOCKCNT,Reserved for future use" rbitfld.long 0x14 0. "DSKEWCALLOCK,Asserted when phase lock is achieved when DSKEWCALEN is set to 1'b1." "0,1" line.long 0x18 "PLL_SSMOD,pll spread spectrum setting" hexmask.long.byte 0x18 9.--14. 1. "DIVVAL,Input divider to set modulation frequency. Divide value is DIVVAL+1 For SELEXTWAVE=1'b0: Modulation Freq=Fclksscg/((DIVVAL+1)* 128) For SELEXTWAVE=1'b1: Modulation Freq=Fclksscg/((DIVVAL+1)*EXTMAXADDR)" newline hexmask.long.byte 0x18 4.--8. 1. "SPREAD,Spread Depth Control in 0.1% steps 5'b00001 ->0.1% 5'b00010 ->0.2% ... 5'b10000 ->1.6% ... 5'b11111 ->3.1%" bitfld.long 0x18 3. "DOWNSPREAD,Downspread control 0: Center-Spread 1: Downspread" "Center-Spread,Downspread" newline bitfld.long 0x18 2. "RESETPTR,Active High reset for wave table pointer Internally synchronized to CLKSSCG 0: If modulation is active(RESET=1'b0 DIS-ABLESSCG=1'b0) INTMOD and FRACMOD are updating based on internal wave table. 1: Modulation is stopped and wave table position.." "If modulation is active,Modulation is stopped and wave table position is.." bitfld.long 0x18 1. "DISABLE_SSCG,Active-High Modulator Bypass Control 0: Use Modulator Output. De-Assertion of DISABLE SSCG is synchronous with CLKSSCG 1: Bypass modulator (INTMOD=INTIN FRACMOD=FRACIN). Assertion of DISABLE SSCG is asynchronous" "Use Modulator Output,Bypass modulator" newline bitfld.long 0x18 0. "MOD_RESET,Active High Modulator Reset 1'b0 ->Modulator is operating 1'b1 ->Reset Modulator.INTMOD=12'd20 FRACMOD=24'd00" "0,1" repeat 2. (list 0x1 0x2 )(list 0x0 0x4 ) group.long ($2+0x20)++0x3 line.long 0x0 "PLL_OUT_DIV_$1,pll outside divider register" rbitfld.long 0x0 31. "DIV_BUSY_B,divider b busy indicator 1: busy 0: not busy" "not busy,busy" newline hexmask.long.byte 0x0 16.--19. 1. "DIV_NUM_B,divider b divider number" rbitfld.long 0x0 15. "DIV_BUSY_A,divider a busy indicator 1: busy 0: not busy" "not busy,busy" newline hexmask.long.byte 0x0 0.--3. 1. "DIV_NUM_A,divider a divider number" repeat.end tree.end tree "PLL_HPI" base ad:0xF1500000 group.long 0x0++0x1B line.long 0x0 "PLL_CTRL,pll global control register" rbitfld.long 0x0 31. "LOCK,Lock signal Indicates no cycle slips between the feedback clock and FPFD for 128 consecutive cycles." "0,1" newline bitfld.long 0x0 21. "PLL_DIVD_CG_EN,divider d cg enable" "0,1" bitfld.long 0x0 20. "PLL_DIVC_CG_EN,divider c cg enable" "0,1" newline bitfld.long 0x0 19. "PLL_DIVB_CG_EN,divider b cg enable" "0,1" bitfld.long 0x0 18. "PLL_DIVA_CG_EN,divider a cg enable" "0,1" newline bitfld.long 0x0 17. "BYPASS,PLL bypass. 1: pll bypass FREF is bypassed to FOUTDIV 0: bypass inactive" "bypass inactive,pll bypass" bitfld.long 0x0 16. "PLLPOSTCG_EN,PLL post divider clock gating enable. 1: postdiv clock gating enable 0: post divider clock gating disable." "post divider clock gating disable,postdiv clock gating enable" newline bitfld.long 0x0 4. "FOUTPOSTDIVEN,Post divide power down. 1: FOUTPOSTDIV 4-phase and synchronous clocks are enabled. 0: FOUTPOSTDIV 4-phase and synchronous clocks are powered down (outputs held at 1'b0)" "FOUTPOSTDIV,FOUTPOSTDIV" newline bitfld.long 0x0 3. "FOUT4PHASEEN,Enable of 4 phase clock generator4 phase output is also powered down if FOUTPOSTDIVEN=1'b0. 1: 4-phase and synchronous clocks are enabled. 0: 4-phase and synchronous clocks are powered down (outputs held at 1'b0)." "0,1" bitfld.long 0x0 2. "DACEN,Enable fractional noise canceling DAC in FRAC mode (this has no function in integer mode). 1: Fractional noise canceling DAC is active (default mode). 0: Fractional noise canceling DAC is not active (test mode only)." "Fractional noise canceling DAC is not active,Fractional noise canceling DAC is active" newline bitfld.long 0x0 1. "INT_MODE,int mode or fractional mode 1: integer mode 0: fractional mode" "fractional mode,integer mode" bitfld.long 0x0 0. "PLLEN,PLL enable. 1: pll enable 0: pll disable pll under low power mode." "pll disable,pll enable" line.long 0x4 "PLL_DIV,used to set the pll divide number" bitfld.long 0x4 9.--11. "POSTDIV2,PLL post divide 2 setting (1 to 7) POSTDIV2=0 is unused. Total post divide is POSTDIV1*POSTDIV2 POSTDIV1>= POSTDIV2" "?,POSTDIV2,?,?,?,?,?,?" newline bitfld.long 0x4 6.--8. "POSTDIV1,PLL post divide 1 setting (1 to 7) POSTDIV1=0 is unused. Total post divide is POSTDIV1*POSTDIV2 POSTDIV1>= POSTDIV2" "?,POSTDIV2,?,?,?,?,?,?" hexmask.long.byte 0x4 0.--5. 1. "REFDIV,Reference divide value (1 to 63)" line.long 0x8 "PLL_FBDIV,used to set the FBDIV value" hexmask.long.word 0x8 0.--11. 1. "FBDIV,PLL Feedback divide value (16 to 640 in integer mode 20 to 320 in fractional mode)" line.long 0xC "PLL_FRAC,used to set the FRAC value" hexmask.long.tbyte 0xC 0.--23. 1. "FRAC,Fractional portion of feedback divide value" line.long 0x10 "PLL_DESKEW,used to set pll DESKEW function. normally. the default setting is ok" hexmask.long.word 0x10 6.--17. 1. "DSKEWCALIN,DSKEWCALBYP==1'b0: Initial condition for deskew cali-bration logic. DSKEWCALBYP==1'b1: Override value for deskew cali-bration. It is a signed integer with positive values delaying thereset of the faster path and negative values delaying the.." newline bitfld.long 0x10 3.--5. "DSKEWCALCNT,Programmable counter for deskew calibration loopSelects the number of PFD edges to wait after each deskewcalibration step. Count is defined as 2DS KEWCALCNT+4(e.g. ifDSKEWCALCNT=3'd6 the loop will wait 1024 PFD periodsbef ore trying a new.." "0,1,2,3,4,5,6,7" bitfld.long 0x10 2. "DSKEWCALBYP,Deskew calibration bypass. 1'b0 - use the skew calibration output (whenDSKEW-CALEN=1) to set the phase correction. 1'b1 - use the DSKEWCALIN[11:0] value (whenDSKEW-CALEN=1) to set the phase correction" "use the skew calibration output,use the DSKEWCALIN[11:0] value" newline bitfld.long 0x10 1. "DSKEWFASTCAL,Deskew fast calibration enableSet this to 1 for initial calibration if an initial value is not al-ready knownShould be set to 0 for normal operation" "0,1" bitfld.long 0x10 0. "DSKEWCALEN,Deskew calibration enable to actively adjust for input skew. 1'b0 - skew calibration is disabled. Static phase oset is deter-mined by analog matching only. 1'b1 - skew calibration is enabled. Static phase oset is ad-justed by sensing phase at.." "skew calibration is disabled,skew calibration is enabled" line.long 0x14 "PLL_DESKEW_STA,pll deskew output register" hexmask.long.word 0x14 5.--16. 1. "DSKEWCALOUT,This is the output of either the skew calibration block (if DSKEWCALBYP=0) or a bueredversion of DSKEWCALIN[11:0] (if DSKEWCALBYP=1). It can be used to read out the phase calibration state to use as an override value so that skew calibration.." newline hexmask.long.byte 0x14 1.--4. 1. "DSKEWCALLOCKCNT,Reserved for future use" rbitfld.long 0x14 0. "DSKEWCALLOCK,Asserted when phase lock is achieved when DSKEWCALEN is set to 1'b1." "0,1" line.long 0x18 "PLL_SSMOD,pll spread spectrum setting" hexmask.long.byte 0x18 9.--14. 1. "DIVVAL,Input divider to set modulation frequency. Divide value is DIVVAL+1 For SELEXTWAVE=1'b0: Modulation Freq=Fclksscg/((DIVVAL+1)* 128) For SELEXTWAVE=1'b1: Modulation Freq=Fclksscg/((DIVVAL+1)*EXTMAXADDR)" newline hexmask.long.byte 0x18 4.--8. 1. "SPREAD,Spread Depth Control in 0.1% steps 5'b00001 ->0.1% 5'b00010 ->0.2% ... 5'b10000 ->1.6% ... 5'b11111 ->3.1%" bitfld.long 0x18 3. "DOWNSPREAD,Downspread control 0: Center-Spread 1: Downspread" "Center-Spread,Downspread" newline bitfld.long 0x18 2. "RESETPTR,Active High reset for wave table pointer Internally synchronized to CLKSSCG 0: If modulation is active(RESET=1'b0 DIS-ABLESSCG=1'b0) INTMOD and FRACMOD are updating based on internal wave table. 1: Modulation is stopped and wave table position.." "If modulation is active,Modulation is stopped and wave table position is.." bitfld.long 0x18 1. "DISABLE_SSCG,Active-High Modulator Bypass Control 0: Use Modulator Output. De-Assertion of DISABLE SSCG is synchronous with CLKSSCG 1: Bypass modulator (INTMOD=INTIN FRACMOD=FRACIN). Assertion of DISABLE SSCG is asynchronous" "Use Modulator Output,Bypass modulator" newline bitfld.long 0x18 0. "MOD_RESET,Active High Modulator Reset 1'b0 ->Modulator is operating 1'b1 ->Reset Modulator.INTMOD=12'd20 FRACMOD=24'd00" "0,1" repeat 2. (list 0x1 0x2 )(list 0x0 0x4 ) group.long ($2+0x20)++0x3 line.long 0x0 "PLL_OUT_DIV_$1,pll outside divider register" rbitfld.long 0x0 31. "DIV_BUSY_B,divider b busy indicator 1: busy 0: not busy" "not busy,busy" newline hexmask.long.byte 0x0 16.--19. 1. "DIV_NUM_B,divider b divider number" rbitfld.long 0x0 15. "DIV_BUSY_A,divider a busy indicator 1: busy 0: not busy" "not busy,busy" newline hexmask.long.byte 0x0 0.--3. 1. "DIV_NUM_A,divider a divider number" repeat.end tree.end tree "PLL_DDR" base ad:0xF3010000 group.long 0x0++0x1B line.long 0x0 "PLL_CTRL,pll global control register" rbitfld.long 0x0 31. "LOCK,Lock signal Indicates no cycle slips between the feedback clock and FPFD for 128 consecutive cycles." "0,1" newline bitfld.long 0x0 21. "PLL_DIVD_CG_EN,divider d cg enable" "0,1" bitfld.long 0x0 20. "PLL_DIVC_CG_EN,divider c cg enable" "0,1" newline bitfld.long 0x0 19. "PLL_DIVB_CG_EN,divider b cg enable" "0,1" bitfld.long 0x0 18. "PLL_DIVA_CG_EN,divider a cg enable" "0,1" newline bitfld.long 0x0 17. "BYPASS,PLL bypass. 1: pll bypass FREF is bypassed to FOUTDIV 0: bypass inactive" "bypass inactive,pll bypass" bitfld.long 0x0 16. "PLLPOSTCG_EN,PLL post divider clock gating enable. 1: postdiv clock gating enable 0: post divider clock gating disable." "post divider clock gating disable,postdiv clock gating enable" newline bitfld.long 0x0 4. "FOUTPOSTDIVEN,Post divide power down. 1: FOUTPOSTDIV 4-phase and synchronous clocks are enabled. 0: FOUTPOSTDIV 4-phase and synchronous clocks are powered down (outputs held at 1'b0)" "FOUTPOSTDIV,FOUTPOSTDIV" newline bitfld.long 0x0 3. "FOUT4PHASEEN,Enable of 4 phase clock generator4 phase output is also powered down if FOUTPOSTDIVEN=1'b0. 1: 4-phase and synchronous clocks are enabled. 0: 4-phase and synchronous clocks are powered down (outputs held at 1'b0)." "0,1" bitfld.long 0x0 2. "DACEN,Enable fractional noise canceling DAC in FRAC mode (this has no function in integer mode). 1: Fractional noise canceling DAC is active (default mode). 0: Fractional noise canceling DAC is not active (test mode only)." "Fractional noise canceling DAC is not active,Fractional noise canceling DAC is active" newline bitfld.long 0x0 1. "INT_MODE,int mode or fractional mode 1: integer mode 0: fractional mode" "fractional mode,integer mode" bitfld.long 0x0 0. "PLLEN,PLL enable. 1: pll enable 0: pll disable pll under low power mode." "pll disable,pll enable" line.long 0x4 "PLL_DIV,used to set the pll divide number" bitfld.long 0x4 9.--11. "POSTDIV2,PLL post divide 2 setting (1 to 7) POSTDIV2=0 is unused. Total post divide is POSTDIV1*POSTDIV2 POSTDIV1>= POSTDIV2" "?,POSTDIV2,?,?,?,?,?,?" newline bitfld.long 0x4 6.--8. "POSTDIV1,PLL post divide 1 setting (1 to 7) POSTDIV1=0 is unused. Total post divide is POSTDIV1*POSTDIV2 POSTDIV1>= POSTDIV2" "?,POSTDIV2,?,?,?,?,?,?" hexmask.long.byte 0x4 0.--5. 1. "REFDIV,Reference divide value (1 to 63)" line.long 0x8 "PLL_FBDIV,used to set the FBDIV value" hexmask.long.word 0x8 0.--11. 1. "FBDIV,PLL Feedback divide value (16 to 640 in integer mode 20 to 320 in fractional mode)" line.long 0xC "PLL_FRAC,used to set the FRAC value" hexmask.long.tbyte 0xC 0.--23. 1. "FRAC,Fractional portion of feedback divide value" line.long 0x10 "PLL_DESKEW,used to set pll DESKEW function. normally. the default setting is ok" hexmask.long.word 0x10 6.--17. 1. "DSKEWCALIN,DSKEWCALBYP==1'b0: Initial condition for deskew cali-bration logic. DSKEWCALBYP==1'b1: Override value for deskew cali-bration. It is a signed integer with positive values delaying thereset of the faster path and negative values delaying the.." newline bitfld.long 0x10 3.--5. "DSKEWCALCNT,Programmable counter for deskew calibration loopSelects the number of PFD edges to wait after each deskewcalibration step. Count is defined as 2DS KEWCALCNT+4(e.g. ifDSKEWCALCNT=3'd6 the loop will wait 1024 PFD periodsbef ore trying a new.." "0,1,2,3,4,5,6,7" bitfld.long 0x10 2. "DSKEWCALBYP,Deskew calibration bypass. 1'b0 - use the skew calibration output (whenDSKEW-CALEN=1) to set the phase correction. 1'b1 - use the DSKEWCALIN[11:0] value (whenDSKEW-CALEN=1) to set the phase correction" "use the skew calibration output,use the DSKEWCALIN[11:0] value" newline bitfld.long 0x10 1. "DSKEWFASTCAL,Deskew fast calibration enableSet this to 1 for initial calibration if an initial value is not al-ready knownShould be set to 0 for normal operation" "0,1" bitfld.long 0x10 0. "DSKEWCALEN,Deskew calibration enable to actively adjust for input skew. 1'b0 - skew calibration is disabled. Static phase oset is deter-mined by analog matching only. 1'b1 - skew calibration is enabled. Static phase oset is ad-justed by sensing phase at.." "skew calibration is disabled,skew calibration is enabled" line.long 0x14 "PLL_DESKEW_STA,pll deskew output register" hexmask.long.word 0x14 5.--16. 1. "DSKEWCALOUT,This is the output of either the skew calibration block (if DSKEWCALBYP=0) or a bueredversion of DSKEWCALIN[11:0] (if DSKEWCALBYP=1). It can be used to read out the phase calibration state to use as an override value so that skew calibration.." newline hexmask.long.byte 0x14 1.--4. 1. "DSKEWCALLOCKCNT,Reserved for future use" rbitfld.long 0x14 0. "DSKEWCALLOCK,Asserted when phase lock is achieved when DSKEWCALEN is set to 1'b1." "0,1" line.long 0x18 "PLL_SSMOD,pll spread spectrum setting" hexmask.long.byte 0x18 9.--14. 1. "DIVVAL,Input divider to set modulation frequency. Divide value is DIVVAL+1 For SELEXTWAVE=1'b0: Modulation Freq=Fclksscg/((DIVVAL+1)* 128) For SELEXTWAVE=1'b1: Modulation Freq=Fclksscg/((DIVVAL+1)*EXTMAXADDR)" newline hexmask.long.byte 0x18 4.--8. 1. "SPREAD,Spread Depth Control in 0.1% steps 5'b00001 ->0.1% 5'b00010 ->0.2% ... 5'b10000 ->1.6% ... 5'b11111 ->3.1%" bitfld.long 0x18 3. "DOWNSPREAD,Downspread control 0: Center-Spread 1: Downspread" "Center-Spread,Downspread" newline bitfld.long 0x18 2. "RESETPTR,Active High reset for wave table pointer Internally synchronized to CLKSSCG 0: If modulation is active(RESET=1'b0 DIS-ABLESSCG=1'b0) INTMOD and FRACMOD are updating based on internal wave table. 1: Modulation is stopped and wave table position.." "If modulation is active,Modulation is stopped and wave table position is.." bitfld.long 0x18 1. "DISABLE_SSCG,Active-High Modulator Bypass Control 0: Use Modulator Output. De-Assertion of DISABLE SSCG is synchronous with CLKSSCG 1: Bypass modulator (INTMOD=INTIN FRACMOD=FRACIN). Assertion of DISABLE SSCG is asynchronous" "Use Modulator Output,Bypass modulator" newline bitfld.long 0x18 0. "MOD_RESET,Active High Modulator Reset 1'b0 ->Modulator is operating 1'b1 ->Reset Modulator.INTMOD=12'd20 FRACMOD=24'd00" "0,1" repeat 2. (list 0x1 0x2 )(list 0x0 0x4 ) group.long ($2+0x20)++0x3 line.long 0x0 "PLL_OUT_DIV_$1,pll outside divider register" rbitfld.long 0x0 31. "DIV_BUSY_B,divider b busy indicator 1: busy 0: not busy" "not busy,busy" newline hexmask.long.byte 0x0 16.--19. 1. "DIV_NUM_B,divider b divider number" rbitfld.long 0x0 15. "DIV_BUSY_A,divider a busy indicator 1: busy 0: not busy" "not busy,busy" newline hexmask.long.byte 0x0 0.--3. 1. "DIV_NUM_A,divider a divider number" repeat.end tree.end tree "PLL_VSN" base ad:0xF5000000 group.long 0x0++0x1B line.long 0x0 "PLL_CTRL,pll global control register" rbitfld.long 0x0 31. "LOCK,Lock signal Indicates no cycle slips between the feedback clock and FPFD for 128 consecutive cycles." "0,1" newline bitfld.long 0x0 21. "PLL_DIVD_CG_EN,divider d cg enable" "0,1" bitfld.long 0x0 20. "PLL_DIVC_CG_EN,divider c cg enable" "0,1" newline bitfld.long 0x0 19. "PLL_DIVB_CG_EN,divider b cg enable" "0,1" bitfld.long 0x0 18. "PLL_DIVA_CG_EN,divider a cg enable" "0,1" newline bitfld.long 0x0 17. "BYPASS,PLL bypass. 1: pll bypass FREF is bypassed to FOUTDIV 0: bypass inactive" "bypass inactive,pll bypass" bitfld.long 0x0 16. "PLLPOSTCG_EN,PLL post divider clock gating enable. 1: postdiv clock gating enable 0: post divider clock gating disable." "post divider clock gating disable,postdiv clock gating enable" newline bitfld.long 0x0 4. "FOUTPOSTDIVEN,Post divide power down. 1: FOUTPOSTDIV 4-phase and synchronous clocks are enabled. 0: FOUTPOSTDIV 4-phase and synchronous clocks are powered down (outputs held at 1'b0)" "FOUTPOSTDIV,FOUTPOSTDIV" newline bitfld.long 0x0 3. "FOUT4PHASEEN,Enable of 4 phase clock generator4 phase output is also powered down if FOUTPOSTDIVEN=1'b0. 1: 4-phase and synchronous clocks are enabled. 0: 4-phase and synchronous clocks are powered down (outputs held at 1'b0)." "0,1" bitfld.long 0x0 2. "DACEN,Enable fractional noise canceling DAC in FRAC mode (this has no function in integer mode). 1: Fractional noise canceling DAC is active (default mode). 0: Fractional noise canceling DAC is not active (test mode only)." "Fractional noise canceling DAC is not active,Fractional noise canceling DAC is active" newline bitfld.long 0x0 1. "INT_MODE,int mode or fractional mode 1: integer mode 0: fractional mode" "fractional mode,integer mode" bitfld.long 0x0 0. "PLLEN,PLL enable. 1: pll enable 0: pll disable pll under low power mode." "pll disable,pll enable" line.long 0x4 "PLL_DIV,used to set the pll divide number" bitfld.long 0x4 9.--11. "POSTDIV2,PLL post divide 2 setting (1 to 7) POSTDIV2=0 is unused. Total post divide is POSTDIV1*POSTDIV2 POSTDIV1>= POSTDIV2" "?,POSTDIV2,?,?,?,?,?,?" newline bitfld.long 0x4 6.--8. "POSTDIV1,PLL post divide 1 setting (1 to 7) POSTDIV1=0 is unused. Total post divide is POSTDIV1*POSTDIV2 POSTDIV1>= POSTDIV2" "?,POSTDIV2,?,?,?,?,?,?" hexmask.long.byte 0x4 0.--5. 1. "REFDIV,Reference divide value (1 to 63)" line.long 0x8 "PLL_FBDIV,used to set the FBDIV value" hexmask.long.word 0x8 0.--11. 1. "FBDIV,PLL Feedback divide value (16 to 640 in integer mode 20 to 320 in fractional mode)" line.long 0xC "PLL_FRAC,used to set the FRAC value" hexmask.long.tbyte 0xC 0.--23. 1. "FRAC,Fractional portion of feedback divide value" line.long 0x10 "PLL_DESKEW,used to set pll DESKEW function. normally. the default setting is ok" hexmask.long.word 0x10 6.--17. 1. "DSKEWCALIN,DSKEWCALBYP==1'b0: Initial condition for deskew cali-bration logic. DSKEWCALBYP==1'b1: Override value for deskew cali-bration. It is a signed integer with positive values delaying thereset of the faster path and negative values delaying the.." newline bitfld.long 0x10 3.--5. "DSKEWCALCNT,Programmable counter for deskew calibration loopSelects the number of PFD edges to wait after each deskewcalibration step. Count is defined as 2DS KEWCALCNT+4(e.g. ifDSKEWCALCNT=3'd6 the loop will wait 1024 PFD periodsbef ore trying a new.." "0,1,2,3,4,5,6,7" bitfld.long 0x10 2. "DSKEWCALBYP,Deskew calibration bypass. 1'b0 - use the skew calibration output (whenDSKEW-CALEN=1) to set the phase correction. 1'b1 - use the DSKEWCALIN[11:0] value (whenDSKEW-CALEN=1) to set the phase correction" "use the skew calibration output,use the DSKEWCALIN[11:0] value" newline bitfld.long 0x10 1. "DSKEWFASTCAL,Deskew fast calibration enableSet this to 1 for initial calibration if an initial value is not al-ready knownShould be set to 0 for normal operation" "0,1" bitfld.long 0x10 0. "DSKEWCALEN,Deskew calibration enable to actively adjust for input skew. 1'b0 - skew calibration is disabled. Static phase oset is deter-mined by analog matching only. 1'b1 - skew calibration is enabled. Static phase oset is ad-justed by sensing phase at.." "skew calibration is disabled,skew calibration is enabled" line.long 0x14 "PLL_DESKEW_STA,pll deskew output register" hexmask.long.word 0x14 5.--16. 1. "DSKEWCALOUT,This is the output of either the skew calibration block (if DSKEWCALBYP=0) or a bueredversion of DSKEWCALIN[11:0] (if DSKEWCALBYP=1). It can be used to read out the phase calibration state to use as an override value so that skew calibration.." newline hexmask.long.byte 0x14 1.--4. 1. "DSKEWCALLOCKCNT,Reserved for future use" rbitfld.long 0x14 0. "DSKEWCALLOCK,Asserted when phase lock is achieved when DSKEWCALEN is set to 1'b1." "0,1" line.long 0x18 "PLL_SSMOD,pll spread spectrum setting" hexmask.long.byte 0x18 9.--14. 1. "DIVVAL,Input divider to set modulation frequency. Divide value is DIVVAL+1 For SELEXTWAVE=1'b0: Modulation Freq=Fclksscg/((DIVVAL+1)* 128) For SELEXTWAVE=1'b1: Modulation Freq=Fclksscg/((DIVVAL+1)*EXTMAXADDR)" newline hexmask.long.byte 0x18 4.--8. 1. "SPREAD,Spread Depth Control in 0.1% steps 5'b00001 ->0.1% 5'b00010 ->0.2% ... 5'b10000 ->1.6% ... 5'b11111 ->3.1%" bitfld.long 0x18 3. "DOWNSPREAD,Downspread control 0: Center-Spread 1: Downspread" "Center-Spread,Downspread" newline bitfld.long 0x18 2. "RESETPTR,Active High reset for wave table pointer Internally synchronized to CLKSSCG 0: If modulation is active(RESET=1'b0 DIS-ABLESSCG=1'b0) INTMOD and FRACMOD are updating based on internal wave table. 1: Modulation is stopped and wave table position.." "If modulation is active,Modulation is stopped and wave table position is.." bitfld.long 0x18 1. "DISABLE_SSCG,Active-High Modulator Bypass Control 0: Use Modulator Output. De-Assertion of DISABLE SSCG is synchronous with CLKSSCG 1: Bypass modulator (INTMOD=INTIN FRACMOD=FRACIN). Assertion of DISABLE SSCG is asynchronous" "Use Modulator Output,Bypass modulator" newline bitfld.long 0x18 0. "MOD_RESET,Active High Modulator Reset 1'b0 ->Modulator is operating 1'b1 ->Reset Modulator.INTMOD=12'd20 FRACMOD=24'd00" "0,1" repeat 2. (list 0x1 0x2 )(list 0x0 0x4 ) group.long ($2+0x20)++0x3 line.long 0x0 "PLL_OUT_DIV_$1,pll outside divider register" rbitfld.long 0x0 31. "DIV_BUSY_B,divider b busy indicator 1: busy 0: not busy" "not busy,busy" newline hexmask.long.byte 0x0 16.--19. 1. "DIV_NUM_B,divider b divider number" rbitfld.long 0x0 15. "DIV_BUSY_A,divider a busy indicator 1: busy 0: not busy" "not busy,busy" newline hexmask.long.byte 0x0 0.--3. 1. "DIV_NUM_A,divider a divider number" repeat.end tree.end elif (CORENAME()=="CORTEXA55") repeat 7. (increment 1. 1.) (list ad:0x30250000 ad:0x30260000 ad:0x30800000 ad:0x30810000 ad:0x30820000 ad:0x30830000 ad:0x30840000) tree "PLL$1" base $2 group.long 0x0++0x1B line.long 0x0 "PLL_CTRL,pll global control register" rbitfld.long 0x0 31. "LOCK,Lock signal Indicates no cycle slips between the feedback clock and FPFD for 128 consecutive cycles." "0,1" newline bitfld.long 0x0 21. "PLL_DIVD_CG_EN,divider d cg enable" "0,1" bitfld.long 0x0 20. "PLL_DIVC_CG_EN,divider c cg enable" "0,1" newline bitfld.long 0x0 19. "PLL_DIVB_CG_EN,divider b cg enable" "0,1" bitfld.long 0x0 18. "PLL_DIVA_CG_EN,divider a cg enable" "0,1" newline bitfld.long 0x0 17. "BYPASS,PLL bypass. 1: pll bypass FREF is bypassed to FOUTDIV 0: bypass inactive" "bypass inactive,pll bypass" bitfld.long 0x0 16. "PLLPOSTCG_EN,PLL post divider clock gating enable. 1: postdiv clock gating enable 0: post divider clock gating disable." "post divider clock gating disable,postdiv clock gating enable" newline bitfld.long 0x0 4. "FOUTPOSTDIVEN,Post divide power down. 1: FOUTPOSTDIV 4-phase and synchronous clocks are enabled. 0: FOUTPOSTDIV 4-phase and synchronous clocks are powered down (outputs held at 1'b0)" "FOUTPOSTDIV,FOUTPOSTDIV" newline bitfld.long 0x0 3. "FOUT4PHASEEN,Enable of 4 phase clock generator4 phase output is also powered down if FOUTPOSTDIVEN=1'b0. 1: 4-phase and synchronous clocks are enabled. 0: 4-phase and synchronous clocks are powered down (outputs held at 1'b0)." "0,1" bitfld.long 0x0 2. "DACEN,Enable fractional noise canceling DAC in FRAC mode (this has no function in integer mode). 1: Fractional noise canceling DAC is active (default mode). 0: Fractional noise canceling DAC is not active (test mode only)." "Fractional noise canceling DAC is not active,Fractional noise canceling DAC is active" newline bitfld.long 0x0 1. "INT_MODE,int mode or fractional mode 1: integer mode 0: fractional mode" "fractional mode,integer mode" bitfld.long 0x0 0. "PLLEN,PLL enable. 1: pll enable 0: pll disable pll under low power mode." "pll disable,pll enable" line.long 0x4 "PLL_DIV,used to set the pll divide number" bitfld.long 0x4 9.--11. "POSTDIV2,PLL post divide 2 setting (1 to 7) POSTDIV2=0 is unused. Total post divide is POSTDIV1*POSTDIV2 POSTDIV1>= POSTDIV2" "?,POSTDIV2,?,?,?,?,?,?" newline bitfld.long 0x4 6.--8. "POSTDIV1,PLL post divide 1 setting (1 to 7) POSTDIV1=0 is unused. Total post divide is POSTDIV1*POSTDIV2 POSTDIV1>= POSTDIV2" "?,POSTDIV2,?,?,?,?,?,?" hexmask.long.byte 0x4 0.--5. 1. "REFDIV,Reference divide value (1 to 63)" line.long 0x8 "PLL_FBDIV,used to set the FBDIV value" hexmask.long.word 0x8 0.--11. 1. "FBDIV,PLL Feedback divide value (16 to 640 in integer mode 20 to 320 in fractional mode)" line.long 0xC "PLL_FRAC,used to set the FRAC value" hexmask.long.tbyte 0xC 0.--23. 1. "FRAC,Fractional portion of feedback divide value" line.long 0x10 "PLL_DESKEW,used to set pll DESKEW function. normally. the default setting is ok" hexmask.long.word 0x10 6.--17. 1. "DSKEWCALIN,DSKEWCALBYP==1'b0: Initial condition for deskew cali-bration logic. DSKEWCALBYP==1'b1: Override value for deskew cali-bration. It is a signed integer with positive values delaying thereset of the faster path and negative values delaying the.." newline bitfld.long 0x10 3.--5. "DSKEWCALCNT,Programmable counter for deskew calibration loopSelects the number of PFD edges to wait after each deskewcalibration step. Count is defined as 2DS KEWCALCNT+4(e.g. ifDSKEWCALCNT=3'd6 the loop will wait 1024 PFD periodsbef ore trying a new.." "0,1,2,3,4,5,6,7" bitfld.long 0x10 2. "DSKEWCALBYP,Deskew calibration bypass. 1'b0 - use the skew calibration output (whenDSKEW-CALEN=1) to set the phase correction. 1'b1 - use the DSKEWCALIN[11:0] value (whenDSKEW-CALEN=1) to set the phase correction" "use the skew calibration output,use the DSKEWCALIN[11:0] value" newline bitfld.long 0x10 1. "DSKEWFASTCAL,Deskew fast calibration enableSet this to 1 for initial calibration if an initial value is not al-ready knownShould be set to 0 for normal operation" "0,1" bitfld.long 0x10 0. "DSKEWCALEN,Deskew calibration enable to actively adjust for input skew. 1'b0 - skew calibration is disabled. Static phase oset is deter-mined by analog matching only. 1'b1 - skew calibration is enabled. Static phase oset is ad-justed by sensing phase at.." "skew calibration is disabled,skew calibration is enabled" line.long 0x14 "PLL_DESKEW_STA,pll deskew output register" hexmask.long.word 0x14 5.--16. 1. "DSKEWCALOUT,This is the output of either the skew calibration block (if DSKEWCALBYP=0) or a bueredversion of DSKEWCALIN[11:0] (if DSKEWCALBYP=1). It can be used to read out the phase calibration state to use as an override value so that skew calibration.." newline hexmask.long.byte 0x14 1.--4. 1. "DSKEWCALLOCKCNT,Reserved for future use" rbitfld.long 0x14 0. "DSKEWCALLOCK,Asserted when phase lock is achieved when DSKEWCALEN is set to 1'b1." "0,1" line.long 0x18 "PLL_SSMOD,pll spread spectrum setting" hexmask.long.byte 0x18 9.--14. 1. "DIVVAL,Input divider to set modulation frequency. Divide value is DIVVAL+1 For SELEXTWAVE=1'b0: Modulation Freq=Fclksscg/((DIVVAL+1)* 128) For SELEXTWAVE=1'b1: Modulation Freq=Fclksscg/((DIVVAL+1)*EXTMAXADDR)" newline hexmask.long.byte 0x18 4.--8. 1. "SPREAD,Spread Depth Control in 0.1% steps 5'b00001 ->0.1% 5'b00010 ->0.2% ... 5'b10000 ->1.6% ... 5'b11111 ->3.1%" bitfld.long 0x18 3. "DOWNSPREAD,Downspread control 0: Center-Spread 1: Downspread" "Center-Spread,Downspread" newline bitfld.long 0x18 2. "RESETPTR,Active High reset for wave table pointer Internally synchronized to CLKSSCG 0: If modulation is active(RESET=1'b0 DIS-ABLESSCG=1'b0) INTMOD and FRACMOD are updating based on internal wave table. 1: Modulation is stopped and wave table position.." "If modulation is active,Modulation is stopped and wave table position is.." bitfld.long 0x18 1. "DISABLE_SSCG,Active-High Modulator Bypass Control 0: Use Modulator Output. De-Assertion of DISABLE SSCG is synchronous with CLKSSCG 1: Bypass modulator (INTMOD=INTIN FRACMOD=FRACIN). Assertion of DISABLE SSCG is asynchronous" "Use Modulator Output,Bypass modulator" newline bitfld.long 0x18 0. "MOD_RESET,Active High Modulator Reset 1'b0 ->Modulator is operating 1'b1 ->Reset Modulator.INTMOD=12'd20 FRACMOD=24'd00" "0,1" repeat 2. (list 0x1 0x2 )(list 0x0 0x4 ) group.long ($2+0x20)++0x3 line.long 0x0 "PLL_OUT_DIV_$1,pll outside divider register" rbitfld.long 0x0 31. "DIV_BUSY_B,divider b busy indicator 1: busy 0: not busy" "not busy,busy" newline hexmask.long.byte 0x0 16.--19. 1. "DIV_NUM_B,divider b divider number" rbitfld.long 0x0 15. "DIV_BUSY_A,divider a busy indicator 1: busy 0: not busy" "not busy,busy" newline hexmask.long.byte 0x0 0.--3. 1. "DIV_NUM_A,divider a divider number" repeat.end tree.end repeat.end repeat 4. (increment 1. 1.) (list ad:0x30C00000 ad:0x30C10000 ad:0x30C20000 ad:0x30C30000) tree "PLL_LVDS$1" base $2 group.long 0x0++0x1B line.long 0x0 "PLL_CTRL,pll global control register" rbitfld.long 0x0 31. "LOCK,Lock signal Indicates no cycle slips between the feedback clock and FPFD for 128 consecutive cycles." "0,1" newline bitfld.long 0x0 21. "PLL_DIVD_CG_EN,divider d cg enable" "0,1" bitfld.long 0x0 20. "PLL_DIVC_CG_EN,divider c cg enable" "0,1" newline bitfld.long 0x0 19. "PLL_DIVB_CG_EN,divider b cg enable" "0,1" bitfld.long 0x0 18. "PLL_DIVA_CG_EN,divider a cg enable" "0,1" newline bitfld.long 0x0 17. "BYPASS,PLL bypass. 1: pll bypass FREF is bypassed to FOUTDIV 0: bypass inactive" "bypass inactive,pll bypass" bitfld.long 0x0 16. "PLLPOSTCG_EN,PLL post divider clock gating enable. 1: postdiv clock gating enable 0: post divider clock gating disable." "post divider clock gating disable,postdiv clock gating enable" newline bitfld.long 0x0 4. "FOUTPOSTDIVEN,Post divide power down. 1: FOUTPOSTDIV 4-phase and synchronous clocks are enabled. 0: FOUTPOSTDIV 4-phase and synchronous clocks are powered down (outputs held at 1'b0)" "FOUTPOSTDIV,FOUTPOSTDIV" newline bitfld.long 0x0 3. "FOUT4PHASEEN,Enable of 4 phase clock generator4 phase output is also powered down if FOUTPOSTDIVEN=1'b0. 1: 4-phase and synchronous clocks are enabled. 0: 4-phase and synchronous clocks are powered down (outputs held at 1'b0)." "0,1" bitfld.long 0x0 2. "DACEN,Enable fractional noise canceling DAC in FRAC mode (this has no function in integer mode). 1: Fractional noise canceling DAC is active (default mode). 0: Fractional noise canceling DAC is not active (test mode only)." "Fractional noise canceling DAC is not active,Fractional noise canceling DAC is active" newline bitfld.long 0x0 1. "INT_MODE,int mode or fractional mode 1: integer mode 0: fractional mode" "fractional mode,integer mode" bitfld.long 0x0 0. "PLLEN,PLL enable. 1: pll enable 0: pll disable pll under low power mode." "pll disable,pll enable" line.long 0x4 "PLL_DIV,used to set the pll divide number" bitfld.long 0x4 9.--11. "POSTDIV2,PLL post divide 2 setting (1 to 7) POSTDIV2=0 is unused. Total post divide is POSTDIV1*POSTDIV2 POSTDIV1>= POSTDIV2" "?,POSTDIV2,?,?,?,?,?,?" newline bitfld.long 0x4 6.--8. "POSTDIV1,PLL post divide 1 setting (1 to 7) POSTDIV1=0 is unused. Total post divide is POSTDIV1*POSTDIV2 POSTDIV1>= POSTDIV2" "?,POSTDIV2,?,?,?,?,?,?" hexmask.long.byte 0x4 0.--5. 1. "REFDIV,Reference divide value (1 to 63)" line.long 0x8 "PLL_FBDIV,used to set the FBDIV value" hexmask.long.word 0x8 0.--11. 1. "FBDIV,PLL Feedback divide value (16 to 640 in integer mode 20 to 320 in fractional mode)" line.long 0xC "PLL_FRAC,used to set the FRAC value" hexmask.long.tbyte 0xC 0.--23. 1. "FRAC,Fractional portion of feedback divide value" line.long 0x10 "PLL_DESKEW,used to set pll DESKEW function. normally. the default setting is ok" hexmask.long.word 0x10 6.--17. 1. "DSKEWCALIN,DSKEWCALBYP==1'b0: Initial condition for deskew cali-bration logic. DSKEWCALBYP==1'b1: Override value for deskew cali-bration. It is a signed integer with positive values delaying thereset of the faster path and negative values delaying the.." newline bitfld.long 0x10 3.--5. "DSKEWCALCNT,Programmable counter for deskew calibration loopSelects the number of PFD edges to wait after each deskewcalibration step. Count is defined as 2DS KEWCALCNT+4(e.g. ifDSKEWCALCNT=3'd6 the loop will wait 1024 PFD periodsbef ore trying a new.." "0,1,2,3,4,5,6,7" bitfld.long 0x10 2. "DSKEWCALBYP,Deskew calibration bypass. 1'b0 - use the skew calibration output (whenDSKEW-CALEN=1) to set the phase correction. 1'b1 - use the DSKEWCALIN[11:0] value (whenDSKEW-CALEN=1) to set the phase correction" "use the skew calibration output,use the DSKEWCALIN[11:0] value" newline bitfld.long 0x10 1. "DSKEWFASTCAL,Deskew fast calibration enableSet this to 1 for initial calibration if an initial value is not al-ready knownShould be set to 0 for normal operation" "0,1" bitfld.long 0x10 0. "DSKEWCALEN,Deskew calibration enable to actively adjust for input skew. 1'b0 - skew calibration is disabled. Static phase oset is deter-mined by analog matching only. 1'b1 - skew calibration is enabled. Static phase oset is ad-justed by sensing phase at.." "skew calibration is disabled,skew calibration is enabled" line.long 0x14 "PLL_DESKEW_STA,pll deskew output register" hexmask.long.word 0x14 5.--16. 1. "DSKEWCALOUT,This is the output of either the skew calibration block (if DSKEWCALBYP=0) or a bueredversion of DSKEWCALIN[11:0] (if DSKEWCALBYP=1). It can be used to read out the phase calibration state to use as an override value so that skew calibration.." newline hexmask.long.byte 0x14 1.--4. 1. "DSKEWCALLOCKCNT,Reserved for future use" rbitfld.long 0x14 0. "DSKEWCALLOCK,Asserted when phase lock is achieved when DSKEWCALEN is set to 1'b1." "0,1" line.long 0x18 "PLL_SSMOD,pll spread spectrum setting" hexmask.long.byte 0x18 9.--14. 1. "DIVVAL,Input divider to set modulation frequency. Divide value is DIVVAL+1 For SELEXTWAVE=1'b0: Modulation Freq=Fclksscg/((DIVVAL+1)* 128) For SELEXTWAVE=1'b1: Modulation Freq=Fclksscg/((DIVVAL+1)*EXTMAXADDR)" newline hexmask.long.byte 0x18 4.--8. 1. "SPREAD,Spread Depth Control in 0.1% steps 5'b00001 ->0.1% 5'b00010 ->0.2% ... 5'b10000 ->1.6% ... 5'b11111 ->3.1%" bitfld.long 0x18 3. "DOWNSPREAD,Downspread control 0: Center-Spread 1: Downspread" "Center-Spread,Downspread" newline bitfld.long 0x18 2. "RESETPTR,Active High reset for wave table pointer Internally synchronized to CLKSSCG 0: If modulation is active(RESET=1'b0 DIS-ABLESSCG=1'b0) INTMOD and FRACMOD are updating based on internal wave table. 1: Modulation is stopped and wave table position.." "If modulation is active,Modulation is stopped and wave table position is.." bitfld.long 0x18 1. "DISABLE_SSCG,Active-High Modulator Bypass Control 0: Use Modulator Output. De-Assertion of DISABLE SSCG is synchronous with CLKSSCG 1: Bypass modulator (INTMOD=INTIN FRACMOD=FRACIN). Assertion of DISABLE SSCG is asynchronous" "Use Modulator Output,Bypass modulator" newline bitfld.long 0x18 0. "MOD_RESET,Active High Modulator Reset 1'b0 ->Modulator is operating 1'b1 ->Reset Modulator.INTMOD=12'd20 FRACMOD=24'd00" "0,1" repeat 2. (list 0x1 0x2 )(list 0x0 0x4 ) group.long ($2+0x20)++0x3 line.long 0x0 "PLL_OUT_DIV_$1,pll outside divider register" rbitfld.long 0x0 31. "DIV_BUSY_B,divider b busy indicator 1: busy 0: not busy" "not busy,busy" newline hexmask.long.byte 0x0 16.--19. 1. "DIV_NUM_B,divider b divider number" rbitfld.long 0x0 15. "DIV_BUSY_A,divider a busy indicator 1: busy 0: not busy" "not busy,busy" newline hexmask.long.byte 0x0 0.--3. 1. "DIV_NUM_A,divider a divider number" repeat.end tree.end repeat.end tree "PLL_DISP" base ad:0x30D30000 group.long 0x0++0x1B line.long 0x0 "PLL_CTRL,pll global control register" rbitfld.long 0x0 31. "LOCK,Lock signal Indicates no cycle slips between the feedback clock and FPFD for 128 consecutive cycles." "0,1" newline bitfld.long 0x0 21. "PLL_DIVD_CG_EN,divider d cg enable" "0,1" bitfld.long 0x0 20. "PLL_DIVC_CG_EN,divider c cg enable" "0,1" newline bitfld.long 0x0 19. "PLL_DIVB_CG_EN,divider b cg enable" "0,1" bitfld.long 0x0 18. "PLL_DIVA_CG_EN,divider a cg enable" "0,1" newline bitfld.long 0x0 17. "BYPASS,PLL bypass. 1: pll bypass FREF is bypassed to FOUTDIV 0: bypass inactive" "bypass inactive,pll bypass" bitfld.long 0x0 16. "PLLPOSTCG_EN,PLL post divider clock gating enable. 1: postdiv clock gating enable 0: post divider clock gating disable." "post divider clock gating disable,postdiv clock gating enable" newline bitfld.long 0x0 4. "FOUTPOSTDIVEN,Post divide power down. 1: FOUTPOSTDIV 4-phase and synchronous clocks are enabled. 0: FOUTPOSTDIV 4-phase and synchronous clocks are powered down (outputs held at 1'b0)" "FOUTPOSTDIV,FOUTPOSTDIV" newline bitfld.long 0x0 3. "FOUT4PHASEEN,Enable of 4 phase clock generator4 phase output is also powered down if FOUTPOSTDIVEN=1'b0. 1: 4-phase and synchronous clocks are enabled. 0: 4-phase and synchronous clocks are powered down (outputs held at 1'b0)." "0,1" bitfld.long 0x0 2. "DACEN,Enable fractional noise canceling DAC in FRAC mode (this has no function in integer mode). 1: Fractional noise canceling DAC is active (default mode). 0: Fractional noise canceling DAC is not active (test mode only)." "Fractional noise canceling DAC is not active,Fractional noise canceling DAC is active" newline bitfld.long 0x0 1. "INT_MODE,int mode or fractional mode 1: integer mode 0: fractional mode" "fractional mode,integer mode" bitfld.long 0x0 0. "PLLEN,PLL enable. 1: pll enable 0: pll disable pll under low power mode." "pll disable,pll enable" line.long 0x4 "PLL_DIV,used to set the pll divide number" bitfld.long 0x4 9.--11. "POSTDIV2,PLL post divide 2 setting (1 to 7) POSTDIV2=0 is unused. Total post divide is POSTDIV1*POSTDIV2 POSTDIV1>= POSTDIV2" "?,POSTDIV2,?,?,?,?,?,?" newline bitfld.long 0x4 6.--8. "POSTDIV1,PLL post divide 1 setting (1 to 7) POSTDIV1=0 is unused. Total post divide is POSTDIV1*POSTDIV2 POSTDIV1>= POSTDIV2" "?,POSTDIV2,?,?,?,?,?,?" hexmask.long.byte 0x4 0.--5. 1. "REFDIV,Reference divide value (1 to 63)" line.long 0x8 "PLL_FBDIV,used to set the FBDIV value" hexmask.long.word 0x8 0.--11. 1. "FBDIV,PLL Feedback divide value (16 to 640 in integer mode 20 to 320 in fractional mode)" line.long 0xC "PLL_FRAC,used to set the FRAC value" hexmask.long.tbyte 0xC 0.--23. 1. "FRAC,Fractional portion of feedback divide value" line.long 0x10 "PLL_DESKEW,used to set pll DESKEW function. normally. the default setting is ok" hexmask.long.word 0x10 6.--17. 1. "DSKEWCALIN,DSKEWCALBYP==1'b0: Initial condition for deskew cali-bration logic. DSKEWCALBYP==1'b1: Override value for deskew cali-bration. It is a signed integer with positive values delaying thereset of the faster path and negative values delaying the.." newline bitfld.long 0x10 3.--5. "DSKEWCALCNT,Programmable counter for deskew calibration loopSelects the number of PFD edges to wait after each deskewcalibration step. Count is defined as 2DS KEWCALCNT+4(e.g. ifDSKEWCALCNT=3'd6 the loop will wait 1024 PFD periodsbef ore trying a new.." "0,1,2,3,4,5,6,7" bitfld.long 0x10 2. "DSKEWCALBYP,Deskew calibration bypass. 1'b0 - use the skew calibration output (whenDSKEW-CALEN=1) to set the phase correction. 1'b1 - use the DSKEWCALIN[11:0] value (whenDSKEW-CALEN=1) to set the phase correction" "use the skew calibration output,use the DSKEWCALIN[11:0] value" newline bitfld.long 0x10 1. "DSKEWFASTCAL,Deskew fast calibration enableSet this to 1 for initial calibration if an initial value is not al-ready knownShould be set to 0 for normal operation" "0,1" bitfld.long 0x10 0. "DSKEWCALEN,Deskew calibration enable to actively adjust for input skew. 1'b0 - skew calibration is disabled. Static phase oset is deter-mined by analog matching only. 1'b1 - skew calibration is enabled. Static phase oset is ad-justed by sensing phase at.." "skew calibration is disabled,skew calibration is enabled" line.long 0x14 "PLL_DESKEW_STA,pll deskew output register" hexmask.long.word 0x14 5.--16. 1. "DSKEWCALOUT,This is the output of either the skew calibration block (if DSKEWCALBYP=0) or a bueredversion of DSKEWCALIN[11:0] (if DSKEWCALBYP=1). It can be used to read out the phase calibration state to use as an override value so that skew calibration.." newline hexmask.long.byte 0x14 1.--4. 1. "DSKEWCALLOCKCNT,Reserved for future use" rbitfld.long 0x14 0. "DSKEWCALLOCK,Asserted when phase lock is achieved when DSKEWCALEN is set to 1'b1." "0,1" line.long 0x18 "PLL_SSMOD,pll spread spectrum setting" hexmask.long.byte 0x18 9.--14. 1. "DIVVAL,Input divider to set modulation frequency. Divide value is DIVVAL+1 For SELEXTWAVE=1'b0: Modulation Freq=Fclksscg/((DIVVAL+1)* 128) For SELEXTWAVE=1'b1: Modulation Freq=Fclksscg/((DIVVAL+1)*EXTMAXADDR)" newline hexmask.long.byte 0x18 4.--8. 1. "SPREAD,Spread Depth Control in 0.1% steps 5'b00001 ->0.1% 5'b00010 ->0.2% ... 5'b10000 ->1.6% ... 5'b11111 ->3.1%" bitfld.long 0x18 3. "DOWNSPREAD,Downspread control 0: Center-Spread 1: Downspread" "Center-Spread,Downspread" newline bitfld.long 0x18 2. "RESETPTR,Active High reset for wave table pointer Internally synchronized to CLKSSCG 0: If modulation is active(RESET=1'b0 DIS-ABLESSCG=1'b0) INTMOD and FRACMOD are updating based on internal wave table. 1: Modulation is stopped and wave table position.." "If modulation is active,Modulation is stopped and wave table position is.." bitfld.long 0x18 1. "DISABLE_SSCG,Active-High Modulator Bypass Control 0: Use Modulator Output. De-Assertion of DISABLE SSCG is synchronous with CLKSSCG 1: Bypass modulator (INTMOD=INTIN FRACMOD=FRACIN). Assertion of DISABLE SSCG is asynchronous" "Use Modulator Output,Bypass modulator" newline bitfld.long 0x18 0. "MOD_RESET,Active High Modulator Reset 1'b0 ->Modulator is operating 1'b1 ->Reset Modulator.INTMOD=12'd20 FRACMOD=24'd00" "0,1" repeat 2. (list 0x1 0x2 )(list 0x0 0x4 ) group.long ($2+0x20)++0x3 line.long 0x0 "PLL_OUT_DIV_$1,pll outside divider register" rbitfld.long 0x0 31. "DIV_BUSY_B,divider b busy indicator 1: busy 0: not busy" "not busy,busy" newline hexmask.long.byte 0x0 16.--19. 1. "DIV_NUM_B,divider b divider number" rbitfld.long 0x0 15. "DIV_BUSY_A,divider a busy indicator 1: busy 0: not busy" "not busy,busy" newline hexmask.long.byte 0x0 0.--3. 1. "DIV_NUM_A,divider a divider number" repeat.end tree.end tree "PLL_HIS" base ad:0x312A0000 group.long 0x0++0x1B line.long 0x0 "PLL_CTRL,pll global control register" rbitfld.long 0x0 31. "LOCK,Lock signal Indicates no cycle slips between the feedback clock and FPFD for 128 consecutive cycles." "0,1" newline bitfld.long 0x0 21. "PLL_DIVD_CG_EN,divider d cg enable" "0,1" bitfld.long 0x0 20. "PLL_DIVC_CG_EN,divider c cg enable" "0,1" newline bitfld.long 0x0 19. "PLL_DIVB_CG_EN,divider b cg enable" "0,1" bitfld.long 0x0 18. "PLL_DIVA_CG_EN,divider a cg enable" "0,1" newline bitfld.long 0x0 17. "BYPASS,PLL bypass. 1: pll bypass FREF is bypassed to FOUTDIV 0: bypass inactive" "bypass inactive,pll bypass" bitfld.long 0x0 16. "PLLPOSTCG_EN,PLL post divider clock gating enable. 1: postdiv clock gating enable 0: post divider clock gating disable." "post divider clock gating disable,postdiv clock gating enable" newline bitfld.long 0x0 4. "FOUTPOSTDIVEN,Post divide power down. 1: FOUTPOSTDIV 4-phase and synchronous clocks are enabled. 0: FOUTPOSTDIV 4-phase and synchronous clocks are powered down (outputs held at 1'b0)" "FOUTPOSTDIV,FOUTPOSTDIV" newline bitfld.long 0x0 3. "FOUT4PHASEEN,Enable of 4 phase clock generator4 phase output is also powered down if FOUTPOSTDIVEN=1'b0. 1: 4-phase and synchronous clocks are enabled. 0: 4-phase and synchronous clocks are powered down (outputs held at 1'b0)." "0,1" bitfld.long 0x0 2. "DACEN,Enable fractional noise canceling DAC in FRAC mode (this has no function in integer mode). 1: Fractional noise canceling DAC is active (default mode). 0: Fractional noise canceling DAC is not active (test mode only)." "Fractional noise canceling DAC is not active,Fractional noise canceling DAC is active" newline bitfld.long 0x0 1. "INT_MODE,int mode or fractional mode 1: integer mode 0: fractional mode" "fractional mode,integer mode" bitfld.long 0x0 0. "PLLEN,PLL enable. 1: pll enable 0: pll disable pll under low power mode." "pll disable,pll enable" line.long 0x4 "PLL_DIV,used to set the pll divide number" bitfld.long 0x4 9.--11. "POSTDIV2,PLL post divide 2 setting (1 to 7) POSTDIV2=0 is unused. Total post divide is POSTDIV1*POSTDIV2 POSTDIV1>= POSTDIV2" "?,POSTDIV2,?,?,?,?,?,?" newline bitfld.long 0x4 6.--8. "POSTDIV1,PLL post divide 1 setting (1 to 7) POSTDIV1=0 is unused. Total post divide is POSTDIV1*POSTDIV2 POSTDIV1>= POSTDIV2" "?,POSTDIV2,?,?,?,?,?,?" hexmask.long.byte 0x4 0.--5. 1. "REFDIV,Reference divide value (1 to 63)" line.long 0x8 "PLL_FBDIV,used to set the FBDIV value" hexmask.long.word 0x8 0.--11. 1. "FBDIV,PLL Feedback divide value (16 to 640 in integer mode 20 to 320 in fractional mode)" line.long 0xC "PLL_FRAC,used to set the FRAC value" hexmask.long.tbyte 0xC 0.--23. 1. "FRAC,Fractional portion of feedback divide value" line.long 0x10 "PLL_DESKEW,used to set pll DESKEW function. normally. the default setting is ok" hexmask.long.word 0x10 6.--17. 1. "DSKEWCALIN,DSKEWCALBYP==1'b0: Initial condition for deskew cali-bration logic. DSKEWCALBYP==1'b1: Override value for deskew cali-bration. It is a signed integer with positive values delaying thereset of the faster path and negative values delaying the.." newline bitfld.long 0x10 3.--5. "DSKEWCALCNT,Programmable counter for deskew calibration loopSelects the number of PFD edges to wait after each deskewcalibration step. Count is defined as 2DS KEWCALCNT+4(e.g. ifDSKEWCALCNT=3'd6 the loop will wait 1024 PFD periodsbef ore trying a new.." "0,1,2,3,4,5,6,7" bitfld.long 0x10 2. "DSKEWCALBYP,Deskew calibration bypass. 1'b0 - use the skew calibration output (whenDSKEW-CALEN=1) to set the phase correction. 1'b1 - use the DSKEWCALIN[11:0] value (whenDSKEW-CALEN=1) to set the phase correction" "use the skew calibration output,use the DSKEWCALIN[11:0] value" newline bitfld.long 0x10 1. "DSKEWFASTCAL,Deskew fast calibration enableSet this to 1 for initial calibration if an initial value is not al-ready knownShould be set to 0 for normal operation" "0,1" bitfld.long 0x10 0. "DSKEWCALEN,Deskew calibration enable to actively adjust for input skew. 1'b0 - skew calibration is disabled. Static phase oset is deter-mined by analog matching only. 1'b1 - skew calibration is enabled. Static phase oset is ad-justed by sensing phase at.." "skew calibration is disabled,skew calibration is enabled" line.long 0x14 "PLL_DESKEW_STA,pll deskew output register" hexmask.long.word 0x14 5.--16. 1. "DSKEWCALOUT,This is the output of either the skew calibration block (if DSKEWCALBYP=0) or a bueredversion of DSKEWCALIN[11:0] (if DSKEWCALBYP=1). It can be used to read out the phase calibration state to use as an override value so that skew calibration.." newline hexmask.long.byte 0x14 1.--4. 1. "DSKEWCALLOCKCNT,Reserved for future use" rbitfld.long 0x14 0. "DSKEWCALLOCK,Asserted when phase lock is achieved when DSKEWCALEN is set to 1'b1." "0,1" line.long 0x18 "PLL_SSMOD,pll spread spectrum setting" hexmask.long.byte 0x18 9.--14. 1. "DIVVAL,Input divider to set modulation frequency. Divide value is DIVVAL+1 For SELEXTWAVE=1'b0: Modulation Freq=Fclksscg/((DIVVAL+1)* 128) For SELEXTWAVE=1'b1: Modulation Freq=Fclksscg/((DIVVAL+1)*EXTMAXADDR)" newline hexmask.long.byte 0x18 4.--8. 1. "SPREAD,Spread Depth Control in 0.1% steps 5'b00001 ->0.1% 5'b00010 ->0.2% ... 5'b10000 ->1.6% ... 5'b11111 ->3.1%" bitfld.long 0x18 3. "DOWNSPREAD,Downspread control 0: Center-Spread 1: Downspread" "Center-Spread,Downspread" newline bitfld.long 0x18 2. "RESETPTR,Active High reset for wave table pointer Internally synchronized to CLKSSCG 0: If modulation is active(RESET=1'b0 DIS-ABLESSCG=1'b0) INTMOD and FRACMOD are updating based on internal wave table. 1: Modulation is stopped and wave table position.." "If modulation is active,Modulation is stopped and wave table position is.." bitfld.long 0x18 1. "DISABLE_SSCG,Active-High Modulator Bypass Control 0: Use Modulator Output. De-Assertion of DISABLE SSCG is synchronous with CLKSSCG 1: Bypass modulator (INTMOD=INTIN FRACMOD=FRACIN). Assertion of DISABLE SSCG is asynchronous" "Use Modulator Output,Bypass modulator" newline bitfld.long 0x18 0. "MOD_RESET,Active High Modulator Reset 1'b0 ->Modulator is operating 1'b1 ->Reset Modulator.INTMOD=12'd20 FRACMOD=24'd00" "0,1" repeat 2. (list 0x1 0x2 )(list 0x0 0x4 ) group.long ($2+0x20)++0x3 line.long 0x0 "PLL_OUT_DIV_$1,pll outside divider register" rbitfld.long 0x0 31. "DIV_BUSY_B,divider b busy indicator 1: busy 0: not busy" "not busy,busy" newline hexmask.long.byte 0x0 16.--19. 1. "DIV_NUM_B,divider b divider number" rbitfld.long 0x0 15. "DIV_BUSY_A,divider a busy indicator 1: busy 0: not busy" "not busy,busy" newline hexmask.long.byte 0x0 0.--3. 1. "DIV_NUM_A,divider a divider number" repeat.end tree.end tree "PLL_VPU" base ad:0x31450000 group.long 0x0++0x1B line.long 0x0 "PLL_CTRL,pll global control register" rbitfld.long 0x0 31. "LOCK,Lock signal Indicates no cycle slips between the feedback clock and FPFD for 128 consecutive cycles." "0,1" newline bitfld.long 0x0 21. "PLL_DIVD_CG_EN,divider d cg enable" "0,1" bitfld.long 0x0 20. "PLL_DIVC_CG_EN,divider c cg enable" "0,1" newline bitfld.long 0x0 19. "PLL_DIVB_CG_EN,divider b cg enable" "0,1" bitfld.long 0x0 18. "PLL_DIVA_CG_EN,divider a cg enable" "0,1" newline bitfld.long 0x0 17. "BYPASS,PLL bypass. 1: pll bypass FREF is bypassed to FOUTDIV 0: bypass inactive" "bypass inactive,pll bypass" bitfld.long 0x0 16. "PLLPOSTCG_EN,PLL post divider clock gating enable. 1: postdiv clock gating enable 0: post divider clock gating disable." "post divider clock gating disable,postdiv clock gating enable" newline bitfld.long 0x0 4. "FOUTPOSTDIVEN,Post divide power down. 1: FOUTPOSTDIV 4-phase and synchronous clocks are enabled. 0: FOUTPOSTDIV 4-phase and synchronous clocks are powered down (outputs held at 1'b0)" "FOUTPOSTDIV,FOUTPOSTDIV" newline bitfld.long 0x0 3. "FOUT4PHASEEN,Enable of 4 phase clock generator4 phase output is also powered down if FOUTPOSTDIVEN=1'b0. 1: 4-phase and synchronous clocks are enabled. 0: 4-phase and synchronous clocks are powered down (outputs held at 1'b0)." "0,1" bitfld.long 0x0 2. "DACEN,Enable fractional noise canceling DAC in FRAC mode (this has no function in integer mode). 1: Fractional noise canceling DAC is active (default mode). 0: Fractional noise canceling DAC is not active (test mode only)." "Fractional noise canceling DAC is not active,Fractional noise canceling DAC is active" newline bitfld.long 0x0 1. "INT_MODE,int mode or fractional mode 1: integer mode 0: fractional mode" "fractional mode,integer mode" bitfld.long 0x0 0. "PLLEN,PLL enable. 1: pll enable 0: pll disable pll under low power mode." "pll disable,pll enable" line.long 0x4 "PLL_DIV,used to set the pll divide number" bitfld.long 0x4 9.--11. "POSTDIV2,PLL post divide 2 setting (1 to 7) POSTDIV2=0 is unused. Total post divide is POSTDIV1*POSTDIV2 POSTDIV1>= POSTDIV2" "?,POSTDIV2,?,?,?,?,?,?" newline bitfld.long 0x4 6.--8. "POSTDIV1,PLL post divide 1 setting (1 to 7) POSTDIV1=0 is unused. Total post divide is POSTDIV1*POSTDIV2 POSTDIV1>= POSTDIV2" "?,POSTDIV2,?,?,?,?,?,?" hexmask.long.byte 0x4 0.--5. 1. "REFDIV,Reference divide value (1 to 63)" line.long 0x8 "PLL_FBDIV,used to set the FBDIV value" hexmask.long.word 0x8 0.--11. 1. "FBDIV,PLL Feedback divide value (16 to 640 in integer mode 20 to 320 in fractional mode)" line.long 0xC "PLL_FRAC,used to set the FRAC value" hexmask.long.tbyte 0xC 0.--23. 1. "FRAC,Fractional portion of feedback divide value" line.long 0x10 "PLL_DESKEW,used to set pll DESKEW function. normally. the default setting is ok" hexmask.long.word 0x10 6.--17. 1. "DSKEWCALIN,DSKEWCALBYP==1'b0: Initial condition for deskew cali-bration logic. DSKEWCALBYP==1'b1: Override value for deskew cali-bration. It is a signed integer with positive values delaying thereset of the faster path and negative values delaying the.." newline bitfld.long 0x10 3.--5. "DSKEWCALCNT,Programmable counter for deskew calibration loopSelects the number of PFD edges to wait after each deskewcalibration step. Count is defined as 2DS KEWCALCNT+4(e.g. ifDSKEWCALCNT=3'd6 the loop will wait 1024 PFD periodsbef ore trying a new.." "0,1,2,3,4,5,6,7" bitfld.long 0x10 2. "DSKEWCALBYP,Deskew calibration bypass. 1'b0 - use the skew calibration output (whenDSKEW-CALEN=1) to set the phase correction. 1'b1 - use the DSKEWCALIN[11:0] value (whenDSKEW-CALEN=1) to set the phase correction" "use the skew calibration output,use the DSKEWCALIN[11:0] value" newline bitfld.long 0x10 1. "DSKEWFASTCAL,Deskew fast calibration enableSet this to 1 for initial calibration if an initial value is not al-ready knownShould be set to 0 for normal operation" "0,1" bitfld.long 0x10 0. "DSKEWCALEN,Deskew calibration enable to actively adjust for input skew. 1'b0 - skew calibration is disabled. Static phase oset is deter-mined by analog matching only. 1'b1 - skew calibration is enabled. Static phase oset is ad-justed by sensing phase at.." "skew calibration is disabled,skew calibration is enabled" line.long 0x14 "PLL_DESKEW_STA,pll deskew output register" hexmask.long.word 0x14 5.--16. 1. "DSKEWCALOUT,This is the output of either the skew calibration block (if DSKEWCALBYP=0) or a bueredversion of DSKEWCALIN[11:0] (if DSKEWCALBYP=1). It can be used to read out the phase calibration state to use as an override value so that skew calibration.." newline hexmask.long.byte 0x14 1.--4. 1. "DSKEWCALLOCKCNT,Reserved for future use" rbitfld.long 0x14 0. "DSKEWCALLOCK,Asserted when phase lock is achieved when DSKEWCALEN is set to 1'b1." "0,1" line.long 0x18 "PLL_SSMOD,pll spread spectrum setting" hexmask.long.byte 0x18 9.--14. 1. "DIVVAL,Input divider to set modulation frequency. Divide value is DIVVAL+1 For SELEXTWAVE=1'b0: Modulation Freq=Fclksscg/((DIVVAL+1)* 128) For SELEXTWAVE=1'b1: Modulation Freq=Fclksscg/((DIVVAL+1)*EXTMAXADDR)" newline hexmask.long.byte 0x18 4.--8. 1. "SPREAD,Spread Depth Control in 0.1% steps 5'b00001 ->0.1% 5'b00010 ->0.2% ... 5'b10000 ->1.6% ... 5'b11111 ->3.1%" bitfld.long 0x18 3. "DOWNSPREAD,Downspread control 0: Center-Spread 1: Downspread" "Center-Spread,Downspread" newline bitfld.long 0x18 2. "RESETPTR,Active High reset for wave table pointer Internally synchronized to CLKSSCG 0: If modulation is active(RESET=1'b0 DIS-ABLESSCG=1'b0) INTMOD and FRACMOD are updating based on internal wave table. 1: Modulation is stopped and wave table position.." "If modulation is active,Modulation is stopped and wave table position is.." bitfld.long 0x18 1. "DISABLE_SSCG,Active-High Modulator Bypass Control 0: Use Modulator Output. De-Assertion of DISABLE SSCG is synchronous with CLKSSCG 1: Bypass modulator (INTMOD=INTIN FRACMOD=FRACIN). Assertion of DISABLE SSCG is asynchronous" "Use Modulator Output,Bypass modulator" newline bitfld.long 0x18 0. "MOD_RESET,Active High Modulator Reset 1'b0 ->Modulator is operating 1'b1 ->Reset Modulator.INTMOD=12'd20 FRACMOD=24'd00" "0,1" repeat 2. (list 0x1 0x2 )(list 0x0 0x4 ) group.long ($2+0x20)++0x3 line.long 0x0 "PLL_OUT_DIV_$1,pll outside divider register" rbitfld.long 0x0 31. "DIV_BUSY_B,divider b busy indicator 1: busy 0: not busy" "not busy,busy" newline hexmask.long.byte 0x0 16.--19. 1. "DIV_NUM_B,divider b divider number" rbitfld.long 0x0 15. "DIV_BUSY_A,divider a busy indicator 1: busy 0: not busy" "not busy,busy" newline hexmask.long.byte 0x0 0.--3. 1. "DIV_NUM_A,divider a divider number" repeat.end tree.end tree "PLL_GPU1" base ad:0x31480000 group.long 0x0++0x1B line.long 0x0 "PLL_CTRL,pll global control register" rbitfld.long 0x0 31. "LOCK,Lock signal Indicates no cycle slips between the feedback clock and FPFD for 128 consecutive cycles." "0,1" newline bitfld.long 0x0 21. "PLL_DIVD_CG_EN,divider d cg enable" "0,1" bitfld.long 0x0 20. "PLL_DIVC_CG_EN,divider c cg enable" "0,1" newline bitfld.long 0x0 19. "PLL_DIVB_CG_EN,divider b cg enable" "0,1" bitfld.long 0x0 18. "PLL_DIVA_CG_EN,divider a cg enable" "0,1" newline bitfld.long 0x0 17. "BYPASS,PLL bypass. 1: pll bypass FREF is bypassed to FOUTDIV 0: bypass inactive" "bypass inactive,pll bypass" bitfld.long 0x0 16. "PLLPOSTCG_EN,PLL post divider clock gating enable. 1: postdiv clock gating enable 0: post divider clock gating disable." "post divider clock gating disable,postdiv clock gating enable" newline bitfld.long 0x0 4. "FOUTPOSTDIVEN,Post divide power down. 1: FOUTPOSTDIV 4-phase and synchronous clocks are enabled. 0: FOUTPOSTDIV 4-phase and synchronous clocks are powered down (outputs held at 1'b0)" "FOUTPOSTDIV,FOUTPOSTDIV" newline bitfld.long 0x0 3. "FOUT4PHASEEN,Enable of 4 phase clock generator4 phase output is also powered down if FOUTPOSTDIVEN=1'b0. 1: 4-phase and synchronous clocks are enabled. 0: 4-phase and synchronous clocks are powered down (outputs held at 1'b0)." "0,1" bitfld.long 0x0 2. "DACEN,Enable fractional noise canceling DAC in FRAC mode (this has no function in integer mode). 1: Fractional noise canceling DAC is active (default mode). 0: Fractional noise canceling DAC is not active (test mode only)." "Fractional noise canceling DAC is not active,Fractional noise canceling DAC is active" newline bitfld.long 0x0 1. "INT_MODE,int mode or fractional mode 1: integer mode 0: fractional mode" "fractional mode,integer mode" bitfld.long 0x0 0. "PLLEN,PLL enable. 1: pll enable 0: pll disable pll under low power mode." "pll disable,pll enable" line.long 0x4 "PLL_DIV,used to set the pll divide number" bitfld.long 0x4 9.--11. "POSTDIV2,PLL post divide 2 setting (1 to 7) POSTDIV2=0 is unused. Total post divide is POSTDIV1*POSTDIV2 POSTDIV1>= POSTDIV2" "?,POSTDIV2,?,?,?,?,?,?" newline bitfld.long 0x4 6.--8. "POSTDIV1,PLL post divide 1 setting (1 to 7) POSTDIV1=0 is unused. Total post divide is POSTDIV1*POSTDIV2 POSTDIV1>= POSTDIV2" "?,POSTDIV2,?,?,?,?,?,?" hexmask.long.byte 0x4 0.--5. 1. "REFDIV,Reference divide value (1 to 63)" line.long 0x8 "PLL_FBDIV,used to set the FBDIV value" hexmask.long.word 0x8 0.--11. 1. "FBDIV,PLL Feedback divide value (16 to 640 in integer mode 20 to 320 in fractional mode)" line.long 0xC "PLL_FRAC,used to set the FRAC value" hexmask.long.tbyte 0xC 0.--23. 1. "FRAC,Fractional portion of feedback divide value" line.long 0x10 "PLL_DESKEW,used to set pll DESKEW function. normally. the default setting is ok" hexmask.long.word 0x10 6.--17. 1. "DSKEWCALIN,DSKEWCALBYP==1'b0: Initial condition for deskew cali-bration logic. DSKEWCALBYP==1'b1: Override value for deskew cali-bration. It is a signed integer with positive values delaying thereset of the faster path and negative values delaying the.." newline bitfld.long 0x10 3.--5. "DSKEWCALCNT,Programmable counter for deskew calibration loopSelects the number of PFD edges to wait after each deskewcalibration step. Count is defined as 2DS KEWCALCNT+4(e.g. ifDSKEWCALCNT=3'd6 the loop will wait 1024 PFD periodsbef ore trying a new.." "0,1,2,3,4,5,6,7" bitfld.long 0x10 2. "DSKEWCALBYP,Deskew calibration bypass. 1'b0 - use the skew calibration output (whenDSKEW-CALEN=1) to set the phase correction. 1'b1 - use the DSKEWCALIN[11:0] value (whenDSKEW-CALEN=1) to set the phase correction" "use the skew calibration output,use the DSKEWCALIN[11:0] value" newline bitfld.long 0x10 1. "DSKEWFASTCAL,Deskew fast calibration enableSet this to 1 for initial calibration if an initial value is not al-ready knownShould be set to 0 for normal operation" "0,1" bitfld.long 0x10 0. "DSKEWCALEN,Deskew calibration enable to actively adjust for input skew. 1'b0 - skew calibration is disabled. Static phase oset is deter-mined by analog matching only. 1'b1 - skew calibration is enabled. Static phase oset is ad-justed by sensing phase at.." "skew calibration is disabled,skew calibration is enabled" line.long 0x14 "PLL_DESKEW_STA,pll deskew output register" hexmask.long.word 0x14 5.--16. 1. "DSKEWCALOUT,This is the output of either the skew calibration block (if DSKEWCALBYP=0) or a bueredversion of DSKEWCALIN[11:0] (if DSKEWCALBYP=1). It can be used to read out the phase calibration state to use as an override value so that skew calibration.." newline hexmask.long.byte 0x14 1.--4. 1. "DSKEWCALLOCKCNT,Reserved for future use" rbitfld.long 0x14 0. "DSKEWCALLOCK,Asserted when phase lock is achieved when DSKEWCALEN is set to 1'b1." "0,1" line.long 0x18 "PLL_SSMOD,pll spread spectrum setting" hexmask.long.byte 0x18 9.--14. 1. "DIVVAL,Input divider to set modulation frequency. Divide value is DIVVAL+1 For SELEXTWAVE=1'b0: Modulation Freq=Fclksscg/((DIVVAL+1)* 128) For SELEXTWAVE=1'b1: Modulation Freq=Fclksscg/((DIVVAL+1)*EXTMAXADDR)" newline hexmask.long.byte 0x18 4.--8. 1. "SPREAD,Spread Depth Control in 0.1% steps 5'b00001 ->0.1% 5'b00010 ->0.2% ... 5'b10000 ->1.6% ... 5'b11111 ->3.1%" bitfld.long 0x18 3. "DOWNSPREAD,Downspread control 0: Center-Spread 1: Downspread" "Center-Spread,Downspread" newline bitfld.long 0x18 2. "RESETPTR,Active High reset for wave table pointer Internally synchronized to CLKSSCG 0: If modulation is active(RESET=1'b0 DIS-ABLESSCG=1'b0) INTMOD and FRACMOD are updating based on internal wave table. 1: Modulation is stopped and wave table position.." "If modulation is active,Modulation is stopped and wave table position is.." bitfld.long 0x18 1. "DISABLE_SSCG,Active-High Modulator Bypass Control 0: Use Modulator Output. De-Assertion of DISABLE SSCG is synchronous with CLKSSCG 1: Bypass modulator (INTMOD=INTIN FRACMOD=FRACIN). Assertion of DISABLE SSCG is asynchronous" "Use Modulator Output,Bypass modulator" newline bitfld.long 0x18 0. "MOD_RESET,Active High Modulator Reset 1'b0 ->Modulator is operating 1'b1 ->Reset Modulator.INTMOD=12'd20 FRACMOD=24'd00" "0,1" repeat 2. (list 0x1 0x2 )(list 0x0 0x4 ) group.long ($2+0x20)++0x3 line.long 0x0 "PLL_OUT_DIV_$1,pll outside divider register" rbitfld.long 0x0 31. "DIV_BUSY_B,divider b busy indicator 1: busy 0: not busy" "not busy,busy" newline hexmask.long.byte 0x0 16.--19. 1. "DIV_NUM_B,divider b divider number" rbitfld.long 0x0 15. "DIV_BUSY_A,divider a busy indicator 1: busy 0: not busy" "not busy,busy" newline hexmask.long.byte 0x0 0.--3. 1. "DIV_NUM_A,divider a divider number" repeat.end tree.end tree "PLL_GPU2" base ad:0x31490000 group.long 0x0++0x1B line.long 0x0 "PLL_CTRL,pll global control register" rbitfld.long 0x0 31. "LOCK,Lock signal Indicates no cycle slips between the feedback clock and FPFD for 128 consecutive cycles." "0,1" newline bitfld.long 0x0 21. "PLL_DIVD_CG_EN,divider d cg enable" "0,1" bitfld.long 0x0 20. "PLL_DIVC_CG_EN,divider c cg enable" "0,1" newline bitfld.long 0x0 19. "PLL_DIVB_CG_EN,divider b cg enable" "0,1" bitfld.long 0x0 18. "PLL_DIVA_CG_EN,divider a cg enable" "0,1" newline bitfld.long 0x0 17. "BYPASS,PLL bypass. 1: pll bypass FREF is bypassed to FOUTDIV 0: bypass inactive" "bypass inactive,pll bypass" bitfld.long 0x0 16. "PLLPOSTCG_EN,PLL post divider clock gating enable. 1: postdiv clock gating enable 0: post divider clock gating disable." "post divider clock gating disable,postdiv clock gating enable" newline bitfld.long 0x0 4. "FOUTPOSTDIVEN,Post divide power down. 1: FOUTPOSTDIV 4-phase and synchronous clocks are enabled. 0: FOUTPOSTDIV 4-phase and synchronous clocks are powered down (outputs held at 1'b0)" "FOUTPOSTDIV,FOUTPOSTDIV" newline bitfld.long 0x0 3. "FOUT4PHASEEN,Enable of 4 phase clock generator4 phase output is also powered down if FOUTPOSTDIVEN=1'b0. 1: 4-phase and synchronous clocks are enabled. 0: 4-phase and synchronous clocks are powered down (outputs held at 1'b0)." "0,1" bitfld.long 0x0 2. "DACEN,Enable fractional noise canceling DAC in FRAC mode (this has no function in integer mode). 1: Fractional noise canceling DAC is active (default mode). 0: Fractional noise canceling DAC is not active (test mode only)." "Fractional noise canceling DAC is not active,Fractional noise canceling DAC is active" newline bitfld.long 0x0 1. "INT_MODE,int mode or fractional mode 1: integer mode 0: fractional mode" "fractional mode,integer mode" bitfld.long 0x0 0. "PLLEN,PLL enable. 1: pll enable 0: pll disable pll under low power mode." "pll disable,pll enable" line.long 0x4 "PLL_DIV,used to set the pll divide number" bitfld.long 0x4 9.--11. "POSTDIV2,PLL post divide 2 setting (1 to 7) POSTDIV2=0 is unused. Total post divide is POSTDIV1*POSTDIV2 POSTDIV1>= POSTDIV2" "?,POSTDIV2,?,?,?,?,?,?" newline bitfld.long 0x4 6.--8. "POSTDIV1,PLL post divide 1 setting (1 to 7) POSTDIV1=0 is unused. Total post divide is POSTDIV1*POSTDIV2 POSTDIV1>= POSTDIV2" "?,POSTDIV2,?,?,?,?,?,?" hexmask.long.byte 0x4 0.--5. 1. "REFDIV,Reference divide value (1 to 63)" line.long 0x8 "PLL_FBDIV,used to set the FBDIV value" hexmask.long.word 0x8 0.--11. 1. "FBDIV,PLL Feedback divide value (16 to 640 in integer mode 20 to 320 in fractional mode)" line.long 0xC "PLL_FRAC,used to set the FRAC value" hexmask.long.tbyte 0xC 0.--23. 1. "FRAC,Fractional portion of feedback divide value" line.long 0x10 "PLL_DESKEW,used to set pll DESKEW function. normally. the default setting is ok" hexmask.long.word 0x10 6.--17. 1. "DSKEWCALIN,DSKEWCALBYP==1'b0: Initial condition for deskew cali-bration logic. DSKEWCALBYP==1'b1: Override value for deskew cali-bration. It is a signed integer with positive values delaying thereset of the faster path and negative values delaying the.." newline bitfld.long 0x10 3.--5. "DSKEWCALCNT,Programmable counter for deskew calibration loopSelects the number of PFD edges to wait after each deskewcalibration step. Count is defined as 2DS KEWCALCNT+4(e.g. ifDSKEWCALCNT=3'd6 the loop will wait 1024 PFD periodsbef ore trying a new.." "0,1,2,3,4,5,6,7" bitfld.long 0x10 2. "DSKEWCALBYP,Deskew calibration bypass. 1'b0 - use the skew calibration output (whenDSKEW-CALEN=1) to set the phase correction. 1'b1 - use the DSKEWCALIN[11:0] value (whenDSKEW-CALEN=1) to set the phase correction" "use the skew calibration output,use the DSKEWCALIN[11:0] value" newline bitfld.long 0x10 1. "DSKEWFASTCAL,Deskew fast calibration enableSet this to 1 for initial calibration if an initial value is not al-ready knownShould be set to 0 for normal operation" "0,1" bitfld.long 0x10 0. "DSKEWCALEN,Deskew calibration enable to actively adjust for input skew. 1'b0 - skew calibration is disabled. Static phase oset is deter-mined by analog matching only. 1'b1 - skew calibration is enabled. Static phase oset is ad-justed by sensing phase at.." "skew calibration is disabled,skew calibration is enabled" line.long 0x14 "PLL_DESKEW_STA,pll deskew output register" hexmask.long.word 0x14 5.--16. 1. "DSKEWCALOUT,This is the output of either the skew calibration block (if DSKEWCALBYP=0) or a bueredversion of DSKEWCALIN[11:0] (if DSKEWCALBYP=1). It can be used to read out the phase calibration state to use as an override value so that skew calibration.." newline hexmask.long.byte 0x14 1.--4. 1. "DSKEWCALLOCKCNT,Reserved for future use" rbitfld.long 0x14 0. "DSKEWCALLOCK,Asserted when phase lock is achieved when DSKEWCALEN is set to 1'b1." "0,1" line.long 0x18 "PLL_SSMOD,pll spread spectrum setting" hexmask.long.byte 0x18 9.--14. 1. "DIVVAL,Input divider to set modulation frequency. Divide value is DIVVAL+1 For SELEXTWAVE=1'b0: Modulation Freq=Fclksscg/((DIVVAL+1)* 128) For SELEXTWAVE=1'b1: Modulation Freq=Fclksscg/((DIVVAL+1)*EXTMAXADDR)" newline hexmask.long.byte 0x18 4.--8. 1. "SPREAD,Spread Depth Control in 0.1% steps 5'b00001 ->0.1% 5'b00010 ->0.2% ... 5'b10000 ->1.6% ... 5'b11111 ->3.1%" bitfld.long 0x18 3. "DOWNSPREAD,Downspread control 0: Center-Spread 1: Downspread" "Center-Spread,Downspread" newline bitfld.long 0x18 2. "RESETPTR,Active High reset for wave table pointer Internally synchronized to CLKSSCG 0: If modulation is active(RESET=1'b0 DIS-ABLESSCG=1'b0) INTMOD and FRACMOD are updating based on internal wave table. 1: Modulation is stopped and wave table position.." "If modulation is active,Modulation is stopped and wave table position is.." bitfld.long 0x18 1. "DISABLE_SSCG,Active-High Modulator Bypass Control 0: Use Modulator Output. De-Assertion of DISABLE SSCG is synchronous with CLKSSCG 1: Bypass modulator (INTMOD=INTIN FRACMOD=FRACIN). Assertion of DISABLE SSCG is asynchronous" "Use Modulator Output,Bypass modulator" newline bitfld.long 0x18 0. "MOD_RESET,Active High Modulator Reset 1'b0 ->Modulator is operating 1'b1 ->Reset Modulator.INTMOD=12'd20 FRACMOD=24'd00" "0,1" repeat 2. (list 0x1 0x2 )(list 0x0 0x4 ) group.long ($2+0x20)++0x3 line.long 0x0 "PLL_OUT_DIV_$1,pll outside divider register" rbitfld.long 0x0 31. "DIV_BUSY_B,divider b busy indicator 1: busy 0: not busy" "not busy,busy" newline hexmask.long.byte 0x0 16.--19. 1. "DIV_NUM_B,divider b divider number" rbitfld.long 0x0 15. "DIV_BUSY_A,divider a busy indicator 1: busy 0: not busy" "not busy,busy" newline hexmask.long.byte 0x0 0.--3. 1. "DIV_NUM_A,divider a divider number" repeat.end tree.end tree "PLL_CPU_CORE" base ad:0x314A0000 group.long 0x0++0x1B line.long 0x0 "PLL_CTRL,pll global control register" rbitfld.long 0x0 31. "LOCK,Lock signal Indicates no cycle slips between the feedback clock and FPFD for 128 consecutive cycles." "0,1" newline bitfld.long 0x0 21. "PLL_DIVD_CG_EN,divider d cg enable" "0,1" bitfld.long 0x0 20. "PLL_DIVC_CG_EN,divider c cg enable" "0,1" newline bitfld.long 0x0 19. "PLL_DIVB_CG_EN,divider b cg enable" "0,1" bitfld.long 0x0 18. "PLL_DIVA_CG_EN,divider a cg enable" "0,1" newline bitfld.long 0x0 17. "BYPASS,PLL bypass. 1: pll bypass FREF is bypassed to FOUTDIV 0: bypass inactive" "bypass inactive,pll bypass" bitfld.long 0x0 16. "PLLPOSTCG_EN,PLL post divider clock gating enable. 1: postdiv clock gating enable 0: post divider clock gating disable." "post divider clock gating disable,postdiv clock gating enable" newline bitfld.long 0x0 4. "FOUTPOSTDIVEN,Post divide power down. 1: FOUTPOSTDIV 4-phase and synchronous clocks are enabled. 0: FOUTPOSTDIV 4-phase and synchronous clocks are powered down (outputs held at 1'b0)" "FOUTPOSTDIV,FOUTPOSTDIV" newline bitfld.long 0x0 3. "FOUT4PHASEEN,Enable of 4 phase clock generator4 phase output is also powered down if FOUTPOSTDIVEN=1'b0. 1: 4-phase and synchronous clocks are enabled. 0: 4-phase and synchronous clocks are powered down (outputs held at 1'b0)." "0,1" bitfld.long 0x0 2. "DACEN,Enable fractional noise canceling DAC in FRAC mode (this has no function in integer mode). 1: Fractional noise canceling DAC is active (default mode). 0: Fractional noise canceling DAC is not active (test mode only)." "Fractional noise canceling DAC is not active,Fractional noise canceling DAC is active" newline bitfld.long 0x0 1. "INT_MODE,int mode or fractional mode 1: integer mode 0: fractional mode" "fractional mode,integer mode" bitfld.long 0x0 0. "PLLEN,PLL enable. 1: pll enable 0: pll disable pll under low power mode." "pll disable,pll enable" line.long 0x4 "PLL_DIV,used to set the pll divide number" bitfld.long 0x4 9.--11. "POSTDIV2,PLL post divide 2 setting (1 to 7) POSTDIV2=0 is unused. Total post divide is POSTDIV1*POSTDIV2 POSTDIV1>= POSTDIV2" "?,POSTDIV2,?,?,?,?,?,?" newline bitfld.long 0x4 6.--8. "POSTDIV1,PLL post divide 1 setting (1 to 7) POSTDIV1=0 is unused. Total post divide is POSTDIV1*POSTDIV2 POSTDIV1>= POSTDIV2" "?,POSTDIV2,?,?,?,?,?,?" hexmask.long.byte 0x4 0.--5. 1. "REFDIV,Reference divide value (1 to 63)" line.long 0x8 "PLL_FBDIV,used to set the FBDIV value" hexmask.long.word 0x8 0.--11. 1. "FBDIV,PLL Feedback divide value (16 to 640 in integer mode 20 to 320 in fractional mode)" line.long 0xC "PLL_FRAC,used to set the FRAC value" hexmask.long.tbyte 0xC 0.--23. 1. "FRAC,Fractional portion of feedback divide value" line.long 0x10 "PLL_DESKEW,used to set pll DESKEW function. normally. the default setting is ok" hexmask.long.word 0x10 6.--17. 1. "DSKEWCALIN,DSKEWCALBYP==1'b0: Initial condition for deskew cali-bration logic. DSKEWCALBYP==1'b1: Override value for deskew cali-bration. It is a signed integer with positive values delaying thereset of the faster path and negative values delaying the.." newline bitfld.long 0x10 3.--5. "DSKEWCALCNT,Programmable counter for deskew calibration loopSelects the number of PFD edges to wait after each deskewcalibration step. Count is defined as 2DS KEWCALCNT+4(e.g. ifDSKEWCALCNT=3'd6 the loop will wait 1024 PFD periodsbef ore trying a new.." "0,1,2,3,4,5,6,7" bitfld.long 0x10 2. "DSKEWCALBYP,Deskew calibration bypass. 1'b0 - use the skew calibration output (whenDSKEW-CALEN=1) to set the phase correction. 1'b1 - use the DSKEWCALIN[11:0] value (whenDSKEW-CALEN=1) to set the phase correction" "use the skew calibration output,use the DSKEWCALIN[11:0] value" newline bitfld.long 0x10 1. "DSKEWFASTCAL,Deskew fast calibration enableSet this to 1 for initial calibration if an initial value is not al-ready knownShould be set to 0 for normal operation" "0,1" bitfld.long 0x10 0. "DSKEWCALEN,Deskew calibration enable to actively adjust for input skew. 1'b0 - skew calibration is disabled. Static phase oset is deter-mined by analog matching only. 1'b1 - skew calibration is enabled. Static phase oset is ad-justed by sensing phase at.." "skew calibration is disabled,skew calibration is enabled" line.long 0x14 "PLL_DESKEW_STA,pll deskew output register" hexmask.long.word 0x14 5.--16. 1. "DSKEWCALOUT,This is the output of either the skew calibration block (if DSKEWCALBYP=0) or a bueredversion of DSKEWCALIN[11:0] (if DSKEWCALBYP=1). It can be used to read out the phase calibration state to use as an override value so that skew calibration.." newline hexmask.long.byte 0x14 1.--4. 1. "DSKEWCALLOCKCNT,Reserved for future use" rbitfld.long 0x14 0. "DSKEWCALLOCK,Asserted when phase lock is achieved when DSKEWCALEN is set to 1'b1." "0,1" line.long 0x18 "PLL_SSMOD,pll spread spectrum setting" hexmask.long.byte 0x18 9.--14. 1. "DIVVAL,Input divider to set modulation frequency. Divide value is DIVVAL+1 For SELEXTWAVE=1'b0: Modulation Freq=Fclksscg/((DIVVAL+1)* 128) For SELEXTWAVE=1'b1: Modulation Freq=Fclksscg/((DIVVAL+1)*EXTMAXADDR)" newline hexmask.long.byte 0x18 4.--8. 1. "SPREAD,Spread Depth Control in 0.1% steps 5'b00001 ->0.1% 5'b00010 ->0.2% ... 5'b10000 ->1.6% ... 5'b11111 ->3.1%" bitfld.long 0x18 3. "DOWNSPREAD,Downspread control 0: Center-Spread 1: Downspread" "Center-Spread,Downspread" newline bitfld.long 0x18 2. "RESETPTR,Active High reset for wave table pointer Internally synchronized to CLKSSCG 0: If modulation is active(RESET=1'b0 DIS-ABLESSCG=1'b0) INTMOD and FRACMOD are updating based on internal wave table. 1: Modulation is stopped and wave table position.." "If modulation is active,Modulation is stopped and wave table position is.." bitfld.long 0x18 1. "DISABLE_SSCG,Active-High Modulator Bypass Control 0: Use Modulator Output. De-Assertion of DISABLE SSCG is synchronous with CLKSSCG 1: Bypass modulator (INTMOD=INTIN FRACMOD=FRACIN). Assertion of DISABLE SSCG is asynchronous" "Use Modulator Output,Bypass modulator" newline bitfld.long 0x18 0. "MOD_RESET,Active High Modulator Reset 1'b0 ->Modulator is operating 1'b1 ->Reset Modulator.INTMOD=12'd20 FRACMOD=24'd00" "0,1" repeat 2. (list 0x1 0x2 )(list 0x0 0x4 ) group.long ($2+0x20)++0x3 line.long 0x0 "PLL_OUT_DIV_$1,pll outside divider register" rbitfld.long 0x0 31. "DIV_BUSY_B,divider b busy indicator 1: busy 0: not busy" "not busy,busy" newline hexmask.long.byte 0x0 16.--19. 1. "DIV_NUM_B,divider b divider number" rbitfld.long 0x0 15. "DIV_BUSY_A,divider a busy indicator 1: busy 0: not busy" "not busy,busy" newline hexmask.long.byte 0x0 0.--3. 1. "DIV_NUM_A,divider a divider number" repeat.end tree.end tree "PLL_CPU" base ad:0x314B0000 group.long 0x0++0x1B line.long 0x0 "PLL_CTRL,pll global control register" rbitfld.long 0x0 31. "LOCK,Lock signal Indicates no cycle slips between the feedback clock and FPFD for 128 consecutive cycles." "0,1" newline bitfld.long 0x0 21. "PLL_DIVD_CG_EN,divider d cg enable" "0,1" bitfld.long 0x0 20. "PLL_DIVC_CG_EN,divider c cg enable" "0,1" newline bitfld.long 0x0 19. "PLL_DIVB_CG_EN,divider b cg enable" "0,1" bitfld.long 0x0 18. "PLL_DIVA_CG_EN,divider a cg enable" "0,1" newline bitfld.long 0x0 17. "BYPASS,PLL bypass. 1: pll bypass FREF is bypassed to FOUTDIV 0: bypass inactive" "bypass inactive,pll bypass" bitfld.long 0x0 16. "PLLPOSTCG_EN,PLL post divider clock gating enable. 1: postdiv clock gating enable 0: post divider clock gating disable." "post divider clock gating disable,postdiv clock gating enable" newline bitfld.long 0x0 4. "FOUTPOSTDIVEN,Post divide power down. 1: FOUTPOSTDIV 4-phase and synchronous clocks are enabled. 0: FOUTPOSTDIV 4-phase and synchronous clocks are powered down (outputs held at 1'b0)" "FOUTPOSTDIV,FOUTPOSTDIV" newline bitfld.long 0x0 3. "FOUT4PHASEEN,Enable of 4 phase clock generator4 phase output is also powered down if FOUTPOSTDIVEN=1'b0. 1: 4-phase and synchronous clocks are enabled. 0: 4-phase and synchronous clocks are powered down (outputs held at 1'b0)." "0,1" bitfld.long 0x0 2. "DACEN,Enable fractional noise canceling DAC in FRAC mode (this has no function in integer mode). 1: Fractional noise canceling DAC is active (default mode). 0: Fractional noise canceling DAC is not active (test mode only)." "Fractional noise canceling DAC is not active,Fractional noise canceling DAC is active" newline bitfld.long 0x0 1. "INT_MODE,int mode or fractional mode 1: integer mode 0: fractional mode" "fractional mode,integer mode" bitfld.long 0x0 0. "PLLEN,PLL enable. 1: pll enable 0: pll disable pll under low power mode." "pll disable,pll enable" line.long 0x4 "PLL_DIV,used to set the pll divide number" bitfld.long 0x4 9.--11. "POSTDIV2,PLL post divide 2 setting (1 to 7) POSTDIV2=0 is unused. Total post divide is POSTDIV1*POSTDIV2 POSTDIV1>= POSTDIV2" "?,POSTDIV2,?,?,?,?,?,?" newline bitfld.long 0x4 6.--8. "POSTDIV1,PLL post divide 1 setting (1 to 7) POSTDIV1=0 is unused. Total post divide is POSTDIV1*POSTDIV2 POSTDIV1>= POSTDIV2" "?,POSTDIV2,?,?,?,?,?,?" hexmask.long.byte 0x4 0.--5. 1. "REFDIV,Reference divide value (1 to 63)" line.long 0x8 "PLL_FBDIV,used to set the FBDIV value" hexmask.long.word 0x8 0.--11. 1. "FBDIV,PLL Feedback divide value (16 to 640 in integer mode 20 to 320 in fractional mode)" line.long 0xC "PLL_FRAC,used to set the FRAC value" hexmask.long.tbyte 0xC 0.--23. 1. "FRAC,Fractional portion of feedback divide value" line.long 0x10 "PLL_DESKEW,used to set pll DESKEW function. normally. the default setting is ok" hexmask.long.word 0x10 6.--17. 1. "DSKEWCALIN,DSKEWCALBYP==1'b0: Initial condition for deskew cali-bration logic. DSKEWCALBYP==1'b1: Override value for deskew cali-bration. It is a signed integer with positive values delaying thereset of the faster path and negative values delaying the.." newline bitfld.long 0x10 3.--5. "DSKEWCALCNT,Programmable counter for deskew calibration loopSelects the number of PFD edges to wait after each deskewcalibration step. Count is defined as 2DS KEWCALCNT+4(e.g. ifDSKEWCALCNT=3'd6 the loop will wait 1024 PFD periodsbef ore trying a new.." "0,1,2,3,4,5,6,7" bitfld.long 0x10 2. "DSKEWCALBYP,Deskew calibration bypass. 1'b0 - use the skew calibration output (whenDSKEW-CALEN=1) to set the phase correction. 1'b1 - use the DSKEWCALIN[11:0] value (whenDSKEW-CALEN=1) to set the phase correction" "use the skew calibration output,use the DSKEWCALIN[11:0] value" newline bitfld.long 0x10 1. "DSKEWFASTCAL,Deskew fast calibration enableSet this to 1 for initial calibration if an initial value is not al-ready knownShould be set to 0 for normal operation" "0,1" bitfld.long 0x10 0. "DSKEWCALEN,Deskew calibration enable to actively adjust for input skew. 1'b0 - skew calibration is disabled. Static phase oset is deter-mined by analog matching only. 1'b1 - skew calibration is enabled. Static phase oset is ad-justed by sensing phase at.." "skew calibration is disabled,skew calibration is enabled" line.long 0x14 "PLL_DESKEW_STA,pll deskew output register" hexmask.long.word 0x14 5.--16. 1. "DSKEWCALOUT,This is the output of either the skew calibration block (if DSKEWCALBYP=0) or a bueredversion of DSKEWCALIN[11:0] (if DSKEWCALBYP=1). It can be used to read out the phase calibration state to use as an override value so that skew calibration.." newline hexmask.long.byte 0x14 1.--4. 1. "DSKEWCALLOCKCNT,Reserved for future use" rbitfld.long 0x14 0. "DSKEWCALLOCK,Asserted when phase lock is achieved when DSKEWCALEN is set to 1'b1." "0,1" line.long 0x18 "PLL_SSMOD,pll spread spectrum setting" hexmask.long.byte 0x18 9.--14. 1. "DIVVAL,Input divider to set modulation frequency. Divide value is DIVVAL+1 For SELEXTWAVE=1'b0: Modulation Freq=Fclksscg/((DIVVAL+1)* 128) For SELEXTWAVE=1'b1: Modulation Freq=Fclksscg/((DIVVAL+1)*EXTMAXADDR)" newline hexmask.long.byte 0x18 4.--8. 1. "SPREAD,Spread Depth Control in 0.1% steps 5'b00001 ->0.1% 5'b00010 ->0.2% ... 5'b10000 ->1.6% ... 5'b11111 ->3.1%" bitfld.long 0x18 3. "DOWNSPREAD,Downspread control 0: Center-Spread 1: Downspread" "Center-Spread,Downspread" newline bitfld.long 0x18 2. "RESETPTR,Active High reset for wave table pointer Internally synchronized to CLKSSCG 0: If modulation is active(RESET=1'b0 DIS-ABLESSCG=1'b0) INTMOD and FRACMOD are updating based on internal wave table. 1: Modulation is stopped and wave table position.." "If modulation is active,Modulation is stopped and wave table position is.." bitfld.long 0x18 1. "DISABLE_SSCG,Active-High Modulator Bypass Control 0: Use Modulator Output. De-Assertion of DISABLE SSCG is synchronous with CLKSSCG 1: Bypass modulator (INTMOD=INTIN FRACMOD=FRACIN). Assertion of DISABLE SSCG is asynchronous" "Use Modulator Output,Bypass modulator" newline bitfld.long 0x18 0. "MOD_RESET,Active High Modulator Reset 1'b0 ->Modulator is operating 1'b1 ->Reset Modulator.INTMOD=12'd20 FRACMOD=24'd00" "0,1" repeat 2. (list 0x1 0x2 )(list 0x0 0x4 ) group.long ($2+0x20)++0x3 line.long 0x0 "PLL_OUT_DIV_$1,pll outside divider register" rbitfld.long 0x0 31. "DIV_BUSY_B,divider b busy indicator 1: busy 0: not busy" "not busy,busy" newline hexmask.long.byte 0x0 16.--19. 1. "DIV_NUM_B,divider b divider number" rbitfld.long 0x0 15. "DIV_BUSY_A,divider a busy indicator 1: busy 0: not busy" "not busy,busy" newline hexmask.long.byte 0x0 0.--3. 1. "DIV_NUM_A,divider a divider number" repeat.end tree.end tree "PLL_CPU_DSU" base ad:0x314D0000 group.long 0x0++0x1B line.long 0x0 "PLL_CTRL,pll global control register" rbitfld.long 0x0 31. "LOCK,Lock signal Indicates no cycle slips between the feedback clock and FPFD for 128 consecutive cycles." "0,1" newline bitfld.long 0x0 21. "PLL_DIVD_CG_EN,divider d cg enable" "0,1" bitfld.long 0x0 20. "PLL_DIVC_CG_EN,divider c cg enable" "0,1" newline bitfld.long 0x0 19. "PLL_DIVB_CG_EN,divider b cg enable" "0,1" bitfld.long 0x0 18. "PLL_DIVA_CG_EN,divider a cg enable" "0,1" newline bitfld.long 0x0 17. "BYPASS,PLL bypass. 1: pll bypass FREF is bypassed to FOUTDIV 0: bypass inactive" "bypass inactive,pll bypass" bitfld.long 0x0 16. "PLLPOSTCG_EN,PLL post divider clock gating enable. 1: postdiv clock gating enable 0: post divider clock gating disable." "post divider clock gating disable,postdiv clock gating enable" newline bitfld.long 0x0 4. "FOUTPOSTDIVEN,Post divide power down. 1: FOUTPOSTDIV 4-phase and synchronous clocks are enabled. 0: FOUTPOSTDIV 4-phase and synchronous clocks are powered down (outputs held at 1'b0)" "FOUTPOSTDIV,FOUTPOSTDIV" newline bitfld.long 0x0 3. "FOUT4PHASEEN,Enable of 4 phase clock generator4 phase output is also powered down if FOUTPOSTDIVEN=1'b0. 1: 4-phase and synchronous clocks are enabled. 0: 4-phase and synchronous clocks are powered down (outputs held at 1'b0)." "0,1" bitfld.long 0x0 2. "DACEN,Enable fractional noise canceling DAC in FRAC mode (this has no function in integer mode). 1: Fractional noise canceling DAC is active (default mode). 0: Fractional noise canceling DAC is not active (test mode only)." "Fractional noise canceling DAC is not active,Fractional noise canceling DAC is active" newline bitfld.long 0x0 1. "INT_MODE,int mode or fractional mode 1: integer mode 0: fractional mode" "fractional mode,integer mode" bitfld.long 0x0 0. "PLLEN,PLL enable. 1: pll enable 0: pll disable pll under low power mode." "pll disable,pll enable" line.long 0x4 "PLL_DIV,used to set the pll divide number" bitfld.long 0x4 9.--11. "POSTDIV2,PLL post divide 2 setting (1 to 7) POSTDIV2=0 is unused. Total post divide is POSTDIV1*POSTDIV2 POSTDIV1>= POSTDIV2" "?,POSTDIV2,?,?,?,?,?,?" newline bitfld.long 0x4 6.--8. "POSTDIV1,PLL post divide 1 setting (1 to 7) POSTDIV1=0 is unused. Total post divide is POSTDIV1*POSTDIV2 POSTDIV1>= POSTDIV2" "?,POSTDIV2,?,?,?,?,?,?" hexmask.long.byte 0x4 0.--5. 1. "REFDIV,Reference divide value (1 to 63)" line.long 0x8 "PLL_FBDIV,used to set the FBDIV value" hexmask.long.word 0x8 0.--11. 1. "FBDIV,PLL Feedback divide value (16 to 640 in integer mode 20 to 320 in fractional mode)" line.long 0xC "PLL_FRAC,used to set the FRAC value" hexmask.long.tbyte 0xC 0.--23. 1. "FRAC,Fractional portion of feedback divide value" line.long 0x10 "PLL_DESKEW,used to set pll DESKEW function. normally. the default setting is ok" hexmask.long.word 0x10 6.--17. 1. "DSKEWCALIN,DSKEWCALBYP==1'b0: Initial condition for deskew cali-bration logic. DSKEWCALBYP==1'b1: Override value for deskew cali-bration. It is a signed integer with positive values delaying thereset of the faster path and negative values delaying the.." newline bitfld.long 0x10 3.--5. "DSKEWCALCNT,Programmable counter for deskew calibration loopSelects the number of PFD edges to wait after each deskewcalibration step. Count is defined as 2DS KEWCALCNT+4(e.g. ifDSKEWCALCNT=3'd6 the loop will wait 1024 PFD periodsbef ore trying a new.." "0,1,2,3,4,5,6,7" bitfld.long 0x10 2. "DSKEWCALBYP,Deskew calibration bypass. 1'b0 - use the skew calibration output (whenDSKEW-CALEN=1) to set the phase correction. 1'b1 - use the DSKEWCALIN[11:0] value (whenDSKEW-CALEN=1) to set the phase correction" "use the skew calibration output,use the DSKEWCALIN[11:0] value" newline bitfld.long 0x10 1. "DSKEWFASTCAL,Deskew fast calibration enableSet this to 1 for initial calibration if an initial value is not al-ready knownShould be set to 0 for normal operation" "0,1" bitfld.long 0x10 0. "DSKEWCALEN,Deskew calibration enable to actively adjust for input skew. 1'b0 - skew calibration is disabled. Static phase oset is deter-mined by analog matching only. 1'b1 - skew calibration is enabled. Static phase oset is ad-justed by sensing phase at.." "skew calibration is disabled,skew calibration is enabled" line.long 0x14 "PLL_DESKEW_STA,pll deskew output register" hexmask.long.word 0x14 5.--16. 1. "DSKEWCALOUT,This is the output of either the skew calibration block (if DSKEWCALBYP=0) or a bueredversion of DSKEWCALIN[11:0] (if DSKEWCALBYP=1). It can be used to read out the phase calibration state to use as an override value so that skew calibration.." newline hexmask.long.byte 0x14 1.--4. 1. "DSKEWCALLOCKCNT,Reserved for future use" rbitfld.long 0x14 0. "DSKEWCALLOCK,Asserted when phase lock is achieved when DSKEWCALEN is set to 1'b1." "0,1" line.long 0x18 "PLL_SSMOD,pll spread spectrum setting" hexmask.long.byte 0x18 9.--14. 1. "DIVVAL,Input divider to set modulation frequency. Divide value is DIVVAL+1 For SELEXTWAVE=1'b0: Modulation Freq=Fclksscg/((DIVVAL+1)* 128) For SELEXTWAVE=1'b1: Modulation Freq=Fclksscg/((DIVVAL+1)*EXTMAXADDR)" newline hexmask.long.byte 0x18 4.--8. 1. "SPREAD,Spread Depth Control in 0.1% steps 5'b00001 ->0.1% 5'b00010 ->0.2% ... 5'b10000 ->1.6% ... 5'b11111 ->3.1%" bitfld.long 0x18 3. "DOWNSPREAD,Downspread control 0: Center-Spread 1: Downspread" "Center-Spread,Downspread" newline bitfld.long 0x18 2. "RESETPTR,Active High reset for wave table pointer Internally synchronized to CLKSSCG 0: If modulation is active(RESET=1'b0 DIS-ABLESSCG=1'b0) INTMOD and FRACMOD are updating based on internal wave table. 1: Modulation is stopped and wave table position.." "If modulation is active,Modulation is stopped and wave table position is.." bitfld.long 0x18 1. "DISABLE_SSCG,Active-High Modulator Bypass Control 0: Use Modulator Output. De-Assertion of DISABLE SSCG is synchronous with CLKSSCG 1: Bypass modulator (INTMOD=INTIN FRACMOD=FRACIN). Assertion of DISABLE SSCG is asynchronous" "Use Modulator Output,Bypass modulator" newline bitfld.long 0x18 0. "MOD_RESET,Active High Modulator Reset 1'b0 ->Modulator is operating 1'b1 ->Reset Modulator.INTMOD=12'd20 FRACMOD=24'd00" "0,1" repeat 2. (list 0x1 0x2 )(list 0x0 0x4 ) group.long ($2+0x20)++0x3 line.long 0x0 "PLL_OUT_DIV_$1,pll outside divider register" rbitfld.long 0x0 31. "DIV_BUSY_B,divider b busy indicator 1: busy 0: not busy" "not busy,busy" newline hexmask.long.byte 0x0 16.--19. 1. "DIV_NUM_B,divider b divider number" rbitfld.long 0x0 15. "DIV_BUSY_A,divider a busy indicator 1: busy 0: not busy" "not busy,busy" newline hexmask.long.byte 0x0 0.--3. 1. "DIV_NUM_A,divider a divider number" repeat.end tree.end tree "PLL_HPI" base ad:0x31500000 group.long 0x0++0x1B line.long 0x0 "PLL_CTRL,pll global control register" rbitfld.long 0x0 31. "LOCK,Lock signal Indicates no cycle slips between the feedback clock and FPFD for 128 consecutive cycles." "0,1" newline bitfld.long 0x0 21. "PLL_DIVD_CG_EN,divider d cg enable" "0,1" bitfld.long 0x0 20. "PLL_DIVC_CG_EN,divider c cg enable" "0,1" newline bitfld.long 0x0 19. "PLL_DIVB_CG_EN,divider b cg enable" "0,1" bitfld.long 0x0 18. "PLL_DIVA_CG_EN,divider a cg enable" "0,1" newline bitfld.long 0x0 17. "BYPASS,PLL bypass. 1: pll bypass FREF is bypassed to FOUTDIV 0: bypass inactive" "bypass inactive,pll bypass" bitfld.long 0x0 16. "PLLPOSTCG_EN,PLL post divider clock gating enable. 1: postdiv clock gating enable 0: post divider clock gating disable." "post divider clock gating disable,postdiv clock gating enable" newline bitfld.long 0x0 4. "FOUTPOSTDIVEN,Post divide power down. 1: FOUTPOSTDIV 4-phase and synchronous clocks are enabled. 0: FOUTPOSTDIV 4-phase and synchronous clocks are powered down (outputs held at 1'b0)" "FOUTPOSTDIV,FOUTPOSTDIV" newline bitfld.long 0x0 3. "FOUT4PHASEEN,Enable of 4 phase clock generator4 phase output is also powered down if FOUTPOSTDIVEN=1'b0. 1: 4-phase and synchronous clocks are enabled. 0: 4-phase and synchronous clocks are powered down (outputs held at 1'b0)." "0,1" bitfld.long 0x0 2. "DACEN,Enable fractional noise canceling DAC in FRAC mode (this has no function in integer mode). 1: Fractional noise canceling DAC is active (default mode). 0: Fractional noise canceling DAC is not active (test mode only)." "Fractional noise canceling DAC is not active,Fractional noise canceling DAC is active" newline bitfld.long 0x0 1. "INT_MODE,int mode or fractional mode 1: integer mode 0: fractional mode" "fractional mode,integer mode" bitfld.long 0x0 0. "PLLEN,PLL enable. 1: pll enable 0: pll disable pll under low power mode." "pll disable,pll enable" line.long 0x4 "PLL_DIV,used to set the pll divide number" bitfld.long 0x4 9.--11. "POSTDIV2,PLL post divide 2 setting (1 to 7) POSTDIV2=0 is unused. Total post divide is POSTDIV1*POSTDIV2 POSTDIV1>= POSTDIV2" "?,POSTDIV2,?,?,?,?,?,?" newline bitfld.long 0x4 6.--8. "POSTDIV1,PLL post divide 1 setting (1 to 7) POSTDIV1=0 is unused. Total post divide is POSTDIV1*POSTDIV2 POSTDIV1>= POSTDIV2" "?,POSTDIV2,?,?,?,?,?,?" hexmask.long.byte 0x4 0.--5. 1. "REFDIV,Reference divide value (1 to 63)" line.long 0x8 "PLL_FBDIV,used to set the FBDIV value" hexmask.long.word 0x8 0.--11. 1. "FBDIV,PLL Feedback divide value (16 to 640 in integer mode 20 to 320 in fractional mode)" line.long 0xC "PLL_FRAC,used to set the FRAC value" hexmask.long.tbyte 0xC 0.--23. 1. "FRAC,Fractional portion of feedback divide value" line.long 0x10 "PLL_DESKEW,used to set pll DESKEW function. normally. the default setting is ok" hexmask.long.word 0x10 6.--17. 1. "DSKEWCALIN,DSKEWCALBYP==1'b0: Initial condition for deskew cali-bration logic. DSKEWCALBYP==1'b1: Override value for deskew cali-bration. It is a signed integer with positive values delaying thereset of the faster path and negative values delaying the.." newline bitfld.long 0x10 3.--5. "DSKEWCALCNT,Programmable counter for deskew calibration loopSelects the number of PFD edges to wait after each deskewcalibration step. Count is defined as 2DS KEWCALCNT+4(e.g. ifDSKEWCALCNT=3'd6 the loop will wait 1024 PFD periodsbef ore trying a new.." "0,1,2,3,4,5,6,7" bitfld.long 0x10 2. "DSKEWCALBYP,Deskew calibration bypass. 1'b0 - use the skew calibration output (whenDSKEW-CALEN=1) to set the phase correction. 1'b1 - use the DSKEWCALIN[11:0] value (whenDSKEW-CALEN=1) to set the phase correction" "use the skew calibration output,use the DSKEWCALIN[11:0] value" newline bitfld.long 0x10 1. "DSKEWFASTCAL,Deskew fast calibration enableSet this to 1 for initial calibration if an initial value is not al-ready knownShould be set to 0 for normal operation" "0,1" bitfld.long 0x10 0. "DSKEWCALEN,Deskew calibration enable to actively adjust for input skew. 1'b0 - skew calibration is disabled. Static phase oset is deter-mined by analog matching only. 1'b1 - skew calibration is enabled. Static phase oset is ad-justed by sensing phase at.." "skew calibration is disabled,skew calibration is enabled" line.long 0x14 "PLL_DESKEW_STA,pll deskew output register" hexmask.long.word 0x14 5.--16. 1. "DSKEWCALOUT,This is the output of either the skew calibration block (if DSKEWCALBYP=0) or a bueredversion of DSKEWCALIN[11:0] (if DSKEWCALBYP=1). It can be used to read out the phase calibration state to use as an override value so that skew calibration.." newline hexmask.long.byte 0x14 1.--4. 1. "DSKEWCALLOCKCNT,Reserved for future use" rbitfld.long 0x14 0. "DSKEWCALLOCK,Asserted when phase lock is achieved when DSKEWCALEN is set to 1'b1." "0,1" line.long 0x18 "PLL_SSMOD,pll spread spectrum setting" hexmask.long.byte 0x18 9.--14. 1. "DIVVAL,Input divider to set modulation frequency. Divide value is DIVVAL+1 For SELEXTWAVE=1'b0: Modulation Freq=Fclksscg/((DIVVAL+1)* 128) For SELEXTWAVE=1'b1: Modulation Freq=Fclksscg/((DIVVAL+1)*EXTMAXADDR)" newline hexmask.long.byte 0x18 4.--8. 1. "SPREAD,Spread Depth Control in 0.1% steps 5'b00001 ->0.1% 5'b00010 ->0.2% ... 5'b10000 ->1.6% ... 5'b11111 ->3.1%" bitfld.long 0x18 3. "DOWNSPREAD,Downspread control 0: Center-Spread 1: Downspread" "Center-Spread,Downspread" newline bitfld.long 0x18 2. "RESETPTR,Active High reset for wave table pointer Internally synchronized to CLKSSCG 0: If modulation is active(RESET=1'b0 DIS-ABLESSCG=1'b0) INTMOD and FRACMOD are updating based on internal wave table. 1: Modulation is stopped and wave table position.." "If modulation is active,Modulation is stopped and wave table position is.." bitfld.long 0x18 1. "DISABLE_SSCG,Active-High Modulator Bypass Control 0: Use Modulator Output. De-Assertion of DISABLE SSCG is synchronous with CLKSSCG 1: Bypass modulator (INTMOD=INTIN FRACMOD=FRACIN). Assertion of DISABLE SSCG is asynchronous" "Use Modulator Output,Bypass modulator" newline bitfld.long 0x18 0. "MOD_RESET,Active High Modulator Reset 1'b0 ->Modulator is operating 1'b1 ->Reset Modulator.INTMOD=12'd20 FRACMOD=24'd00" "0,1" repeat 2. (list 0x1 0x2 )(list 0x0 0x4 ) group.long ($2+0x20)++0x3 line.long 0x0 "PLL_OUT_DIV_$1,pll outside divider register" rbitfld.long 0x0 31. "DIV_BUSY_B,divider b busy indicator 1: busy 0: not busy" "not busy,busy" newline hexmask.long.byte 0x0 16.--19. 1. "DIV_NUM_B,divider b divider number" rbitfld.long 0x0 15. "DIV_BUSY_A,divider a busy indicator 1: busy 0: not busy" "not busy,busy" newline hexmask.long.byte 0x0 0.--3. 1. "DIV_NUM_A,divider a divider number" repeat.end tree.end tree "PLL_DDR" base ad:0x33010000 group.long 0x0++0x1B line.long 0x0 "PLL_CTRL,pll global control register" rbitfld.long 0x0 31. "LOCK,Lock signal Indicates no cycle slips between the feedback clock and FPFD for 128 consecutive cycles." "0,1" newline bitfld.long 0x0 21. "PLL_DIVD_CG_EN,divider d cg enable" "0,1" bitfld.long 0x0 20. "PLL_DIVC_CG_EN,divider c cg enable" "0,1" newline bitfld.long 0x0 19. "PLL_DIVB_CG_EN,divider b cg enable" "0,1" bitfld.long 0x0 18. "PLL_DIVA_CG_EN,divider a cg enable" "0,1" newline bitfld.long 0x0 17. "BYPASS,PLL bypass. 1: pll bypass FREF is bypassed to FOUTDIV 0: bypass inactive" "bypass inactive,pll bypass" bitfld.long 0x0 16. "PLLPOSTCG_EN,PLL post divider clock gating enable. 1: postdiv clock gating enable 0: post divider clock gating disable." "post divider clock gating disable,postdiv clock gating enable" newline bitfld.long 0x0 4. "FOUTPOSTDIVEN,Post divide power down. 1: FOUTPOSTDIV 4-phase and synchronous clocks are enabled. 0: FOUTPOSTDIV 4-phase and synchronous clocks are powered down (outputs held at 1'b0)" "FOUTPOSTDIV,FOUTPOSTDIV" newline bitfld.long 0x0 3. "FOUT4PHASEEN,Enable of 4 phase clock generator4 phase output is also powered down if FOUTPOSTDIVEN=1'b0. 1: 4-phase and synchronous clocks are enabled. 0: 4-phase and synchronous clocks are powered down (outputs held at 1'b0)." "0,1" bitfld.long 0x0 2. "DACEN,Enable fractional noise canceling DAC in FRAC mode (this has no function in integer mode). 1: Fractional noise canceling DAC is active (default mode). 0: Fractional noise canceling DAC is not active (test mode only)." "Fractional noise canceling DAC is not active,Fractional noise canceling DAC is active" newline bitfld.long 0x0 1. "INT_MODE,int mode or fractional mode 1: integer mode 0: fractional mode" "fractional mode,integer mode" bitfld.long 0x0 0. "PLLEN,PLL enable. 1: pll enable 0: pll disable pll under low power mode." "pll disable,pll enable" line.long 0x4 "PLL_DIV,used to set the pll divide number" bitfld.long 0x4 9.--11. "POSTDIV2,PLL post divide 2 setting (1 to 7) POSTDIV2=0 is unused. Total post divide is POSTDIV1*POSTDIV2 POSTDIV1>= POSTDIV2" "?,POSTDIV2,?,?,?,?,?,?" newline bitfld.long 0x4 6.--8. "POSTDIV1,PLL post divide 1 setting (1 to 7) POSTDIV1=0 is unused. Total post divide is POSTDIV1*POSTDIV2 POSTDIV1>= POSTDIV2" "?,POSTDIV2,?,?,?,?,?,?" hexmask.long.byte 0x4 0.--5. 1. "REFDIV,Reference divide value (1 to 63)" line.long 0x8 "PLL_FBDIV,used to set the FBDIV value" hexmask.long.word 0x8 0.--11. 1. "FBDIV,PLL Feedback divide value (16 to 640 in integer mode 20 to 320 in fractional mode)" line.long 0xC "PLL_FRAC,used to set the FRAC value" hexmask.long.tbyte 0xC 0.--23. 1. "FRAC,Fractional portion of feedback divide value" line.long 0x10 "PLL_DESKEW,used to set pll DESKEW function. normally. the default setting is ok" hexmask.long.word 0x10 6.--17. 1. "DSKEWCALIN,DSKEWCALBYP==1'b0: Initial condition for deskew cali-bration logic. DSKEWCALBYP==1'b1: Override value for deskew cali-bration. It is a signed integer with positive values delaying thereset of the faster path and negative values delaying the.." newline bitfld.long 0x10 3.--5. "DSKEWCALCNT,Programmable counter for deskew calibration loopSelects the number of PFD edges to wait after each deskewcalibration step. Count is defined as 2DS KEWCALCNT+4(e.g. ifDSKEWCALCNT=3'd6 the loop will wait 1024 PFD periodsbef ore trying a new.." "0,1,2,3,4,5,6,7" bitfld.long 0x10 2. "DSKEWCALBYP,Deskew calibration bypass. 1'b0 - use the skew calibration output (whenDSKEW-CALEN=1) to set the phase correction. 1'b1 - use the DSKEWCALIN[11:0] value (whenDSKEW-CALEN=1) to set the phase correction" "use the skew calibration output,use the DSKEWCALIN[11:0] value" newline bitfld.long 0x10 1. "DSKEWFASTCAL,Deskew fast calibration enableSet this to 1 for initial calibration if an initial value is not al-ready knownShould be set to 0 for normal operation" "0,1" bitfld.long 0x10 0. "DSKEWCALEN,Deskew calibration enable to actively adjust for input skew. 1'b0 - skew calibration is disabled. Static phase oset is deter-mined by analog matching only. 1'b1 - skew calibration is enabled. Static phase oset is ad-justed by sensing phase at.." "skew calibration is disabled,skew calibration is enabled" line.long 0x14 "PLL_DESKEW_STA,pll deskew output register" hexmask.long.word 0x14 5.--16. 1. "DSKEWCALOUT,This is the output of either the skew calibration block (if DSKEWCALBYP=0) or a bueredversion of DSKEWCALIN[11:0] (if DSKEWCALBYP=1). It can be used to read out the phase calibration state to use as an override value so that skew calibration.." newline hexmask.long.byte 0x14 1.--4. 1. "DSKEWCALLOCKCNT,Reserved for future use" rbitfld.long 0x14 0. "DSKEWCALLOCK,Asserted when phase lock is achieved when DSKEWCALEN is set to 1'b1." "0,1" line.long 0x18 "PLL_SSMOD,pll spread spectrum setting" hexmask.long.byte 0x18 9.--14. 1. "DIVVAL,Input divider to set modulation frequency. Divide value is DIVVAL+1 For SELEXTWAVE=1'b0: Modulation Freq=Fclksscg/((DIVVAL+1)* 128) For SELEXTWAVE=1'b1: Modulation Freq=Fclksscg/((DIVVAL+1)*EXTMAXADDR)" newline hexmask.long.byte 0x18 4.--8. 1. "SPREAD,Spread Depth Control in 0.1% steps 5'b00001 ->0.1% 5'b00010 ->0.2% ... 5'b10000 ->1.6% ... 5'b11111 ->3.1%" bitfld.long 0x18 3. "DOWNSPREAD,Downspread control 0: Center-Spread 1: Downspread" "Center-Spread,Downspread" newline bitfld.long 0x18 2. "RESETPTR,Active High reset for wave table pointer Internally synchronized to CLKSSCG 0: If modulation is active(RESET=1'b0 DIS-ABLESSCG=1'b0) INTMOD and FRACMOD are updating based on internal wave table. 1: Modulation is stopped and wave table position.." "If modulation is active,Modulation is stopped and wave table position is.." bitfld.long 0x18 1. "DISABLE_SSCG,Active-High Modulator Bypass Control 0: Use Modulator Output. De-Assertion of DISABLE SSCG is synchronous with CLKSSCG 1: Bypass modulator (INTMOD=INTIN FRACMOD=FRACIN). Assertion of DISABLE SSCG is asynchronous" "Use Modulator Output,Bypass modulator" newline bitfld.long 0x18 0. "MOD_RESET,Active High Modulator Reset 1'b0 ->Modulator is operating 1'b1 ->Reset Modulator.INTMOD=12'd20 FRACMOD=24'd00" "0,1" repeat 2. (list 0x1 0x2 )(list 0x0 0x4 ) group.long ($2+0x20)++0x3 line.long 0x0 "PLL_OUT_DIV_$1,pll outside divider register" rbitfld.long 0x0 31. "DIV_BUSY_B,divider b busy indicator 1: busy 0: not busy" "not busy,busy" newline hexmask.long.byte 0x0 16.--19. 1. "DIV_NUM_B,divider b divider number" rbitfld.long 0x0 15. "DIV_BUSY_A,divider a busy indicator 1: busy 0: not busy" "not busy,busy" newline hexmask.long.byte 0x0 0.--3. 1. "DIV_NUM_A,divider a divider number" repeat.end tree.end tree "PLL_VSN" base ad:0x35000000 group.long 0x0++0x1B line.long 0x0 "PLL_CTRL,pll global control register" rbitfld.long 0x0 31. "LOCK,Lock signal Indicates no cycle slips between the feedback clock and FPFD for 128 consecutive cycles." "0,1" newline bitfld.long 0x0 21. "PLL_DIVD_CG_EN,divider d cg enable" "0,1" bitfld.long 0x0 20. "PLL_DIVC_CG_EN,divider c cg enable" "0,1" newline bitfld.long 0x0 19. "PLL_DIVB_CG_EN,divider b cg enable" "0,1" bitfld.long 0x0 18. "PLL_DIVA_CG_EN,divider a cg enable" "0,1" newline bitfld.long 0x0 17. "BYPASS,PLL bypass. 1: pll bypass FREF is bypassed to FOUTDIV 0: bypass inactive" "bypass inactive,pll bypass" bitfld.long 0x0 16. "PLLPOSTCG_EN,PLL post divider clock gating enable. 1: postdiv clock gating enable 0: post divider clock gating disable." "post divider clock gating disable,postdiv clock gating enable" newline bitfld.long 0x0 4. "FOUTPOSTDIVEN,Post divide power down. 1: FOUTPOSTDIV 4-phase and synchronous clocks are enabled. 0: FOUTPOSTDIV 4-phase and synchronous clocks are powered down (outputs held at 1'b0)" "FOUTPOSTDIV,FOUTPOSTDIV" newline bitfld.long 0x0 3. "FOUT4PHASEEN,Enable of 4 phase clock generator4 phase output is also powered down if FOUTPOSTDIVEN=1'b0. 1: 4-phase and synchronous clocks are enabled. 0: 4-phase and synchronous clocks are powered down (outputs held at 1'b0)." "0,1" bitfld.long 0x0 2. "DACEN,Enable fractional noise canceling DAC in FRAC mode (this has no function in integer mode). 1: Fractional noise canceling DAC is active (default mode). 0: Fractional noise canceling DAC is not active (test mode only)." "Fractional noise canceling DAC is not active,Fractional noise canceling DAC is active" newline bitfld.long 0x0 1. "INT_MODE,int mode or fractional mode 1: integer mode 0: fractional mode" "fractional mode,integer mode" bitfld.long 0x0 0. "PLLEN,PLL enable. 1: pll enable 0: pll disable pll under low power mode." "pll disable,pll enable" line.long 0x4 "PLL_DIV,used to set the pll divide number" bitfld.long 0x4 9.--11. "POSTDIV2,PLL post divide 2 setting (1 to 7) POSTDIV2=0 is unused. Total post divide is POSTDIV1*POSTDIV2 POSTDIV1>= POSTDIV2" "?,POSTDIV2,?,?,?,?,?,?" newline bitfld.long 0x4 6.--8. "POSTDIV1,PLL post divide 1 setting (1 to 7) POSTDIV1=0 is unused. Total post divide is POSTDIV1*POSTDIV2 POSTDIV1>= POSTDIV2" "?,POSTDIV2,?,?,?,?,?,?" hexmask.long.byte 0x4 0.--5. 1. "REFDIV,Reference divide value (1 to 63)" line.long 0x8 "PLL_FBDIV,used to set the FBDIV value" hexmask.long.word 0x8 0.--11. 1. "FBDIV,PLL Feedback divide value (16 to 640 in integer mode 20 to 320 in fractional mode)" line.long 0xC "PLL_FRAC,used to set the FRAC value" hexmask.long.tbyte 0xC 0.--23. 1. "FRAC,Fractional portion of feedback divide value" line.long 0x10 "PLL_DESKEW,used to set pll DESKEW function. normally. the default setting is ok" hexmask.long.word 0x10 6.--17. 1. "DSKEWCALIN,DSKEWCALBYP==1'b0: Initial condition for deskew cali-bration logic. DSKEWCALBYP==1'b1: Override value for deskew cali-bration. It is a signed integer with positive values delaying thereset of the faster path and negative values delaying the.." newline bitfld.long 0x10 3.--5. "DSKEWCALCNT,Programmable counter for deskew calibration loopSelects the number of PFD edges to wait after each deskewcalibration step. Count is defined as 2DS KEWCALCNT+4(e.g. ifDSKEWCALCNT=3'd6 the loop will wait 1024 PFD periodsbef ore trying a new.." "0,1,2,3,4,5,6,7" bitfld.long 0x10 2. "DSKEWCALBYP,Deskew calibration bypass. 1'b0 - use the skew calibration output (whenDSKEW-CALEN=1) to set the phase correction. 1'b1 - use the DSKEWCALIN[11:0] value (whenDSKEW-CALEN=1) to set the phase correction" "use the skew calibration output,use the DSKEWCALIN[11:0] value" newline bitfld.long 0x10 1. "DSKEWFASTCAL,Deskew fast calibration enableSet this to 1 for initial calibration if an initial value is not al-ready knownShould be set to 0 for normal operation" "0,1" bitfld.long 0x10 0. "DSKEWCALEN,Deskew calibration enable to actively adjust for input skew. 1'b0 - skew calibration is disabled. Static phase oset is deter-mined by analog matching only. 1'b1 - skew calibration is enabled. Static phase oset is ad-justed by sensing phase at.." "skew calibration is disabled,skew calibration is enabled" line.long 0x14 "PLL_DESKEW_STA,pll deskew output register" hexmask.long.word 0x14 5.--16. 1. "DSKEWCALOUT,This is the output of either the skew calibration block (if DSKEWCALBYP=0) or a bueredversion of DSKEWCALIN[11:0] (if DSKEWCALBYP=1). It can be used to read out the phase calibration state to use as an override value so that skew calibration.." newline hexmask.long.byte 0x14 1.--4. 1. "DSKEWCALLOCKCNT,Reserved for future use" rbitfld.long 0x14 0. "DSKEWCALLOCK,Asserted when phase lock is achieved when DSKEWCALEN is set to 1'b1." "0,1" line.long 0x18 "PLL_SSMOD,pll spread spectrum setting" hexmask.long.byte 0x18 9.--14. 1. "DIVVAL,Input divider to set modulation frequency. Divide value is DIVVAL+1 For SELEXTWAVE=1'b0: Modulation Freq=Fclksscg/((DIVVAL+1)* 128) For SELEXTWAVE=1'b1: Modulation Freq=Fclksscg/((DIVVAL+1)*EXTMAXADDR)" newline hexmask.long.byte 0x18 4.--8. 1. "SPREAD,Spread Depth Control in 0.1% steps 5'b00001 ->0.1% 5'b00010 ->0.2% ... 5'b10000 ->1.6% ... 5'b11111 ->3.1%" bitfld.long 0x18 3. "DOWNSPREAD,Downspread control 0: Center-Spread 1: Downspread" "Center-Spread,Downspread" newline bitfld.long 0x18 2. "RESETPTR,Active High reset for wave table pointer Internally synchronized to CLKSSCG 0: If modulation is active(RESET=1'b0 DIS-ABLESSCG=1'b0) INTMOD and FRACMOD are updating based on internal wave table. 1: Modulation is stopped and wave table position.." "If modulation is active,Modulation is stopped and wave table position is.." bitfld.long 0x18 1. "DISABLE_SSCG,Active-High Modulator Bypass Control 0: Use Modulator Output. De-Assertion of DISABLE SSCG is synchronous with CLKSSCG 1: Bypass modulator (INTMOD=INTIN FRACMOD=FRACIN). Assertion of DISABLE SSCG is asynchronous" "Use Modulator Output,Bypass modulator" newline bitfld.long 0x18 0. "MOD_RESET,Active High Modulator Reset 1'b0 ->Modulator is operating 1'b1 ->Reset Modulator.INTMOD=12'd20 FRACMOD=24'd00" "0,1" repeat 2. (list 0x1 0x2 )(list 0x0 0x4 ) group.long ($2+0x20)++0x3 line.long 0x0 "PLL_OUT_DIV_$1,pll outside divider register" rbitfld.long 0x0 31. "DIV_BUSY_B,divider b busy indicator 1: busy 0: not busy" "not busy,busy" newline hexmask.long.byte 0x0 16.--19. 1. "DIV_NUM_B,divider b divider number" rbitfld.long 0x0 15. "DIV_BUSY_A,divider a busy indicator 1: busy 0: not busy" "not busy,busy" newline hexmask.long.byte 0x0 0.--3. 1. "DIV_NUM_A,divider a divider number" repeat.end tree.end endif tree.end tree "PMU (Power Management Unit)" sif (CORENAME()=="CORTEXR5F") base ad:0xF1850000 group.long 0x0++0x23 line.long 0x0 "EXT_CTRL,control register bits for external wakeup and external reset" rbitfld.long 0x0 31. "EXT_WAKEUP_B_1_STATUS,External wakeup 1 status This field indicates the logic level status on external wakeup pin 1 (SYS_WAKEUP1)." "0,1" newline rbitfld.long 0x0 30. "EXT_WAKEUP_B_0_STATUS,External wakeup 0 status This field indicates the logic level status on external wakeup pin 0 (SYS_WAKEUP0)." "0,1" newline rbitfld.long 0x0 29. "EXT_RESET_B_1_STATUS,External reset 1 status This field indicates the logic level status on external reset 1 (EXT_RESET_REQ1)." "0,1" newline rbitfld.long 0x0 28. "EXT_RESET_B_0_STATUS,External reset 0 status This field indicates the logic level status on external reset 0 (EXT_RESET_REQ0)." "0,1" newline hexmask.long.byte 0x0 24.--27. 1. "EXT_WAKEUP_B_1_DEBOUNCE_TIME,External wakeup 1 debounce time control Similar as external wakeup 0." newline bitfld.long 0x0 23. "EXT_WAKEUP_B_1_DEBOUNCE_EN,External wakeup 1 debounce enable Similar as external wakeup 0." "0,1" newline bitfld.long 0x0 22. "EXT_WAKEUP_B_1_POL,External wakeup 1 polarity Similar as external wakeup 0." "0,1" newline bitfld.long 0x0 21. "EXT_WAKEUP_B_1_EN,External wakeup 1 enable Similar as external wakeup 0." "0,1" newline hexmask.long.byte 0x0 17.--20. 1. "EXT_WAKEUP_B_0_DEBOUNCE_TIME,External wakeup 0 debounce time control Similar as external reset 0." newline bitfld.long 0x0 16. "EXT_WAKEUP_B_0_DEBOUNCE_EN,External wakeup 0 debounce enable Similar as external reset 0." "0,1" newline bitfld.long 0x0 15. "EXT_WAKEUP_B_0_POL,External wakeup 0 polarity 0x0 - Low active 0x1 - High active" "Low active,High active" newline bitfld.long 0x0 14. "EXT_WAKEUP_B_0_EN,External wakeup 0 enable 0x0 - External wakeup 0 disabled 0x1 - External wakeup 0 enabled." "External wakeup 0 disabled,External wakeup 0 enabled" newline hexmask.long.byte 0x0 10.--13. 1. "EXT_RESET_B_1_DEBOUNCE_TIME,External reset 1 debounce time control Similar as external reset 0." newline bitfld.long 0x0 9. "EXT_RESET_B_1_DEBOUNCE_EN,External reset 1 debounce enable Similar as external reset 0." "0,1" newline bitfld.long 0x0 8. "EXT_RESET_B_1_POL,External reset 1 polarity Similar as external reset 0." "0,1" newline bitfld.long 0x0 7. "EXT_RESET_B_1_EN,External reset 1 enable Similar as external reset 0." "0,1" newline hexmask.long.byte 0x0 3.--6. 1. "EXT_RESET_B_0_DEBOUNCE_TIME,External reset 0 debounce time control The debounce time will be: 0x0 - (2-1) cycle of rtc clock (32KHz) 0x1 - (3-1) cycle of rtc clock (32KHz) 0x2 - (4-1) cycle of rtc clock (32KHz) 0x3 - (8-1) cycle of rtc clock (32KHz) 0x4.." newline bitfld.long 0x0 2. "EXT_RESET_B_0_DEBOUNCE_EN,External reset 0 debounce enable 0x0 - External reset will take affect immediately when there is any active edge change. 0x1 - External reset will take affect only if the active period lasts longer than the configured debounce.." "External reset will take affect immediately when..,External reset will take affect only if the.." newline bitfld.long 0x0 1. "EXT_RESET_B_0_POL,External reset 0 polarity 0x0 - Low active 0x1 - High active" "Low active,High active" newline bitfld.long 0x0 0. "EXT_RESET_B_0_EN,External reset 0 enable 0x0 - External reset 0 disabled 0x1 - External reset 0 enabled. Note: Software should wait at least 40ms (more than one cycle in 32KHz) between EXT_RESET_B_0_POL setting and EXT_RESET_B_0_EN setting." "External reset 0 disabled,External reset 0 enabled" line.long 0x4 "RTC_CTRL,RTC wakeup control" newline bitfld.long 0x4 1. "RTC_WAKEUP_B_1_EN,RTC wakeup 1 enable 0x0 - RTC wakeup 1 disabled 0x1 - RTC wakeup 1 enabled." "RTC wakeup 1 disabled,RTC wakeup 1 enabled" newline bitfld.long 0x4 0. "RTC_WAKEUP_B_0_EN,RTC wakeup 0 enable 0x0 - RTC wakeup 0 disabled 0x1 - RTC wakeup 0 enabled." "RTC wakeup 0 disabled,RTC wakeup 0 enabled" line.long 0x8 "GF_CTRL,Glitch filter configuration" newline bitfld.long 0x8 11.--13. "GF_CTL,Glitch filter control bit this field apply to all PMU glitch filter circuit. PMU will ignore all high and low pulse which is shorter then glitch filter time if related glitch filter enabled. The glitch filter time is as following (in cycle of RTC.." "0,1,2,3,4,5,6,7" newline hexmask.long.word 0x8 0.--10. 1. "GF_EN,Glitch filter enable bits bit 0 : Glitch filter enable bit for external reset 0 bit 1 : Glitch filter enable bit for external reset 1 bit 2 : Glitch filter enable bit for external wakeup request 0 bit 3 : Glitch filter enable bit for external.." line.long 0xC "RST_CTRL,Reset Configuration" newline hexmask.long.byte 0xC 24.--28. 1. "PMU_STATE,PMU_STATE This field indicates the real PMU state. 0x01 - PMU_INIT 0x02 - PMU_PWRUP 0x04 - PMU_ON 0x08 - PMU_PWRDWN 0x10 - PMU_OFF" newline bitfld.long 0xC 11.--13. "PORPDCTL,Analog POR cell PD control When PMU power down the on-chip POR cell the output rtc_power_stable from POR cell may get LOW but it doesn't mean RTC domain power supply is deasserted. PMU should ignore this POR cell output for a certain time to.." "0,1,2,3,4,5,6,7" newline bitfld.long 0xC 10. "POR_AUTO_PD,POR auto PD 0x1 - PMU will automatically put the on-chip POR cell into low power mode (power down) when PMU enters PMU_OFF state. This can help save more power consumption. 0x0 - PMU will keep the on-chip POR cell in normal operation when PMU.." "PMU will keep the on-chip POR cell in normal..,PMU will automatically put the on-chip POR cell.." newline bitfld.long 0xC 9. "POR_FORCE_PD,POR force PD Software can force POR cell into low power mode (power down) by setting this field bit 0x01 and bring iit back to normal operation by clearing this field bit. It is recommended to change this field only in PMU_ON state." "0,1" newline bitfld.long 0xC 8. "AP_ISO_CTL,ap_iso_b control 0x0 - ap_iso_b will be not asserted when ap_power_stable turn low 0x1 - ap_iso_b will be asserted when ap_power_stable turn low This field is for internal use only." "ap_iso_b will be not asserted when..,ap_iso_b will be asserted when ap_power_stable.." newline bitfld.long 0xC 7. "AP_POR_CTL,ap_por_b control 0x0 - ap_por_b will be not asserted when ap_power_stable turn low 0x1 - ap_por_b will be asserted when ap_power_stable turn low This field is for internal use only." "ap_por_b will be not asserted when..,ap_por_b will be asserted when ap_power_stable.." newline bitfld.long 0xC 6. "SAFETY_ISO_CTL,safety_iso_b control 0x0 - safety_iso_b will be not asserted when safety_power_stable turn low 0x1 - safety_iso_b will be asserted when safety_power_stable turn low This field is for internal use only." "safety_iso_b will be not asserted when..,safety_iso_b will be asserted when.." newline bitfld.long 0xC 5. "SAFETY_POR_CTL,safety_por_b control 0x0 - safety_por_b will be not asserted when safety_power_stable turn low 0x1 - safety_por_b will be asserted when safety_power_stable turn low This field is for internal use only." "safety_por_b will be not asserted when..,safety_por_b will be asserted when.." newline bitfld.long 0xC 4. "IGNORE_AP_RESET,Ignore SoC AP_RESET_N pin input This field controls whether the ap_por_b and ap_iso_b signal is hold asserted (LOW) while SoC AP_RESET_N pin input is active (LOW). 0x0 - ap_por_b/ap_iso_b is kept asserted (LOW) while AP_RESET_N pin input.." "ap_por_b/ap_iso_b is kept asserted,AP_RESET_N input is ignored" newline bitfld.long 0xC 3. "HOLD_AP_ISO,Force AP domain isolation control (ap_iso_b) active (LOW). This is useful when AP domain power supplies are managed by safety Domain CPU cores. It can set this register bit to hold AP isolation active until all related AP domain power supply.." "0,1" newline bitfld.long 0xC 2. "WAIT_AP_POWER_STABLE,Wait on ap_power_stable output from on-chip POR cell This field controls whether AP domain is kept in reset when ap_power_stable from on-chip POR cell is inactive (LOW). 0x0 - The output ap_power_stable from on-chip POR cell is.." "The output ap_power_stable from on-chip POR cell..,AP domain is kept in reset state" newline bitfld.long 0xC 1. "WAIT_SAFETY_POWER_STABLE,Controls if the safety_por_b signal is de-asserted only after safety_power_stable signal is asserted 0x0 - ignore power stable signal from POR cell 0x1 - wait for power stable signal from POR cell Wait on safety_power_stable.." "The output safety_power_stable from on-chip POR..,Safety domain is kept in reset state" newline bitfld.long 0xC 0. "WAIT_RTC_POWER_STABLE,Wait on rtc_power_stable output from on-chip POR cell This field controls whether RTC domain (except PMU) is kept in reset (rtc_por_b is active/LOW) when rtc_power_stable from on-chip POR cell is inactive (LOW). 0x0 - The output.." "The output rtc_power_stable from on-chip POR..,RTC domain is kept in reset state" line.long 0x10 "PWR_CTRL_0,power up/down configuration" newline bitfld.long 0x10 8. "PWR_DOWN,Force PMU power down Software can force PMU to enter PMU_OFF state by setting this field bit from 0x0 to 0x1." "0,1" newline hexmask.long.byte 0x10 4.--7. 1. "PWR_DOWN_DELAY,PMU power down delay This field configures the power down delay for PMU. 0x0 - 0us 0x1 - 30us 0x2 - 60us 0x3 - 120us 0x4 - 0.25us 0x5 - 0.5ms 0x6 - 0.75ms 0x7 - 1ms 0x8 - 2ms 0x9 - 3ms 0xA - 4ms 0xB - 5ms 0xC - 6ms 0xD - 7ms 0xE - 8ms 0xF.." newline hexmask.long.byte 0x10 0.--3. 1. "PWR_UP_DELAY,PMU power up delay This field configures the power up delay for PMU. 0x0 - 0us 0x1 - 30us 0x2 - 60us 0x3 - 120us 0x4 - 0.25us 0x5 - 0.5ms 0x6 - 0.75ms 0x7 - 1ms 0x8 - 2ms 0x9 - 3ms 0xA - 4ms 0xB - 5ms 0xC - 6ms 0xD - 7ms 0xE - 8ms 0xF - 16ms" line.long 0x14 "PWR_CTRL_1,PWRCTRL0/PWRCTRL1 pin configuration" rbitfld.long 0x14 31. "INLVL1,PWRCTRL1 input status This field indicates the pin input status of PWRCTRL1. It has no meaning when this pin is configured in output mode (IOMODE1=0x0)." "0,1" newline rbitfld.long 0x14 30. "INLVL0,PWRCTRL0 input status This field indicates the pin input status of PWRCTRL0. It has no meaning when this pin is configured in output mode (IOMODE0=0x0)." "0,1" newline bitfld.long 0x14 21. "OUTLVL1,PWRCTRL1 output level control This field control the output level for PWRCTRL1 pin. 0x0 - Low 0x1 - High This field setting is ignored when this pin is configured in input mode (IOMODE1=0x1) or output level mode is 0x0 (CTLMODE1=0x0)." "Low,High" newline bitfld.long 0x14 20. "CTLMODE1,PWRCTRL1 output level mode This field control the output level logic for PWRCTRL1 pin. 0x0 - PMU automatically determines the pin output level according to PMU state. PWRCTRL1 get asserted (HIGH) when PMU enters PMU_PWRUP state with power up.." "PMU automatically determines the pin output..,The pin output level is controlled by software.." newline bitfld.long 0x14 19. "IOMODE1,PWRCTRL1 IO mode This field controls the IO mode of PWRCTRL1 pin. 0x0 - Output mode 0x1 - Input mode" "Output mode,Input mode" newline hexmask.long.byte 0x14 15.--18. 1. "PWRDOWNDELAY1,PWRCTRL1 power down delay configuration 0x0 - 0us 0x1 - 30us 0x2 - 60us 0x3 - 120us 0x4 - 0.25us 0x5 - 0.5ms 0x6 - 0.75ms 0x7 - 1ms 0x8 - 2ms 0x9 - 3ms 0xA - 4ms 0xB - 5ms 0xC - 6ms 0xD - 7ms 0xE - 8ms 0xF - 16ms" newline hexmask.long.byte 0x14 11.--14. 1. "PWRUPDELAY1,PWRCTRL1 power up delay configuration 0x0 - 0us 0x1 - 30us 0x2 - 60us 0x3 - 120us 0x4 - 0.25us 0x5 - 0.5ms 0x6 - 0.75ms 0x7 - 1ms 0x8 - 2ms 0x9 - 3ms 0xA - 4ms 0xB - 5ms 0xC - 6ms 0xD - 7ms 0xE - 8ms 0xF - 16ms" newline bitfld.long 0x14 10. "OUTLVL0,PWRCTRL0 output level control This field control the output level for PWRCTRL0 pin. 0x0 - Low 0x1 - High This field setting is ignored when this pin is configured in input mode (IOMODE0=0x1) or output level mode is 0x0 (CTLMODE0=0x0)." "Low,High" newline bitfld.long 0x14 9. "CTLMODE0,PWRCTRL0 output level mode This field control the output level logic for PWRCTRL0 pin. 0x0 - PMU automatically determines the pin output level according to PMU state. PWRCTRL0 get asserted (HIGH) when PMU enters PMU_PWRUP state with power up.." "PMU automatically determines the pin output..,The pin output level is controlled by software.." newline bitfld.long 0x14 8. "IOMODE0,PWRCTRL0 IO mode This field controls the IO mode of PWRCTRL0 pin. 0x0 - Output mode 0x1 - Input mode" "Output mode,Input mode" newline hexmask.long.byte 0x14 4.--7. 1. "PWRDOWNDELAY0,PWRCTRL0 power down delay configuration 0x0 - 0us 0x1 - 30us 0x2 - 60us 0x3 - 120us 0x4 - 0.25us 0x5 - 0.5ms 0x6 - 0.75ms 0x7 - 1ms 0x8 - 2ms 0x9 - 3ms 0xA - 4ms 0xB - 5ms 0xC - 6ms 0xD - 7ms 0xE - 8ms 0xF - 16ms" newline hexmask.long.byte 0x14 0.--3. 1. "PWRUPDELAY0,PWRCTRL0 power up delay configuration 0x0 - 0us 0x1 - 30us 0x2 - 60us 0x3 - 120us 0x4 - 0.25us 0x5 - 0.5ms 0x6 - 0.75ms 0x7 - 1ms 0x8 - 2ms 0x9 - 3ms 0xA - 4ms 0xB - 5ms 0xC - 6ms 0xD - 7ms 0xE - 8ms 0xF - 16ms" line.long 0x18 "PWR_CTRL_2,PWRCTRL2/PWRCTRL3 pin configuration" rbitfld.long 0x18 31. "INLVL3,PWRCTRL3 input status This field indicates the pin input status of PWRCTRL3. It has no meaning when this pin is configured in output mode (IOMODE3=0x0)." "0,1" newline rbitfld.long 0x18 30. "INLVL2,PWRCTRL2 input status This field indicates the pin input status of PWRCTRL2. It has no meaning when this pin is configured in output mode (IOMODE2=0x0)." "0,1" newline bitfld.long 0x18 21. "OUTLVL3,PWRCTRL3 output level control This field control the output level for PWRCTRL3 pin. 0x0 - Low 0x1 - High This field setting is ignored when this pin is configured in input mode (IOMODE3=0x1) or output level mode is 0x0 (CTLMODE3=0x0)." "Low,High" newline bitfld.long 0x18 20. "CTLMODE3,PWRCTRL3 output level mode This field control the output level logic for PWRCTRL3 pin. 0x0 - PMU automatically determines the pin output level according to PMU state. PWRCTRL3 get asserted (HIGH) when PMU enters PMU_PWRUP state with power up.." "PMU automatically determines the pin output..,The pin output level is controlled by software.." newline bitfld.long 0x18 19. "IOMODE3,PWRCTRL3 IO mode This field controls the IO mode of PWRCTRL3 pin. 0x0 - Output mode 0x1 - Input mode" "Output mode,Input mode" newline hexmask.long.byte 0x18 15.--18. 1. "PWRDOWNDELAY3,PWRCTRL3 power down delay configuration 0x0 - 0us 0x1 - 30us 0x2 - 60us 0x3 - 120us 0x4 - 0.25us 0x5 - 0.5ms 0x6 - 0.75ms 0x7 - 1ms 0x8 - 2ms 0x9 - 3ms 0xA - 4ms 0xB - 5ms 0xC - 6ms 0xD - 7ms 0xE - 8ms 0xF - 16ms" newline hexmask.long.byte 0x18 11.--14. 1. "PWRUPDELAY3,PWRCTRL3 power up delay configuration 0x0 - 0us 0x1 - 30us 0x2 - 60us 0x3 - 120us 0x4 - 0.25us 0x5 - 0.5ms 0x6 - 0.75ms 0x7 - 1ms 0x8 - 2ms 0x9 - 3ms 0xA - 4ms 0xB - 5ms 0xC - 6ms 0xD - 7ms 0xE - 8ms 0xF - 16ms" newline bitfld.long 0x18 10. "OUTLVL2,PWRCTRL2 output level control This field control the output level for PWRCTRL2 pin. 0x0 - Low 0x1 - High This field setting is ignored when this pin is configured in input mode (IOMODE2=0x1) or output level mode is 0x0 (CTLMODE2=0x0)." "Low,High" newline bitfld.long 0x18 9. "CTLMODE2,PWRCTRL2 output level mode This field control the output level logic for PWRCTRL2 pin. 0x0 - PMU automatically determines the pin output level according to PMU state. PWRCTRL2 get asserted (HIGH) when PMU enters PMU_PWRUP state with power up.." "PMU automatically determines the pin output..,The pin output level is controlled by software.." newline bitfld.long 0x18 8. "IOMODE2,PWRCTRL2 IO mode This field controls the IO mode of PWRCTRL2 pin. 0x0 - Output mode 0x1 - Input mode" "Output mode,Input mode" newline hexmask.long.byte 0x18 4.--7. 1. "PWRDOWNDELAY2,PWRCTRL2 power down delay configuration 0x0 - 0us 0x1 - 30us 0x2 - 60us 0x3 - 120us 0x4 - 0.25us 0x5 - 0.5ms 0x6 - 0.75ms 0x7 - 1ms 0x8 - 2ms 0x9 - 3ms 0xA - 4ms 0xB - 5ms 0xC - 6ms 0xD - 7ms 0xE - 8ms 0xF - 16ms" newline hexmask.long.byte 0x18 0.--3. 1. "PWRUPDELAY2,PWRCTRL2 power up delay configuration 0x0 - 0us 0x1 - 30us 0x2 - 60us 0x3 - 120us 0x4 - 0.25us 0x5 - 0.5ms 0x6 - 0.75ms 0x7 - 1ms 0x8 - 2ms 0x9 - 3ms 0xA - 4ms 0xB - 5ms 0xC - 6ms 0xD - 7ms 0xE - 8ms 0xF - 16ms" line.long 0x1C "PWR_CTRL_3,control register bits for internal power down request (from on-chip temperature sensor)" newline rbitfld.long 0x1C 9. "INT_PWRDWN_B_1_STATUS,Internal power down request 1 status This field indicates the real status of internal power down request 1." "0,1" newline rbitfld.long 0x1C 8. "INT_PWRDWN_B_0_STATUS,Internal power down request 0 status This field indicates the real status of internal power down request 0." "0,1" newline bitfld.long 0x1C 3. "INT_PWRDWN_B_1_POL,Internal power down request 1 polarity 0x0 - Low active 0x1 - High active" "Low active,High active" newline bitfld.long 0x1C 2. "INT_PWRDWN_B_1_EN,Internal power down request 1 enable 0x0 - Internal power down disabled 0x1 - Internal power down enabled" "Internal power down disabled,Internal power down enabled" newline bitfld.long 0x1C 1. "INT_PWRDWN_B_0_POL,Internal power down request 0 polarity 0x0 - Low active 0x1 - High active" "Low active,High active" newline bitfld.long 0x1C 0. "INT_PWRDWN_B_0_EN,Internal power down request 0 enable 0x0 - Internal power down disabled 0x1 - Internal power down enabled" "Internal power down disabled,Internal power down enabled" line.long 0x20 "STICKY_STS_0,Sticky status 0 This register records whether any external reset. external wakeup. rtc wakeup and internal power down requesst happened. This register gets reset only when RTC Domain power supply removed or SYS_RESET_N get asserted." hexmask.long.tbyte 0x20 8.--31. 1. "RSVD0,RSVD0" newline bitfld.long 0x20 7. "RTC_WAKEUP_1,RTC_WAKEUP_1 This field recorded whether RTC WAKEUP 1 happened. It get set (to 0x1) whenever RTC WAKEUP happened. It get reset (to 0x0) when RTC domain power supply removed or SYS_RESET_N asserted (LOW active). It can also be cleared by.." "0,1" newline bitfld.long 0x20 6. "RTC_WAKEUP_0,RTC_WAKEUP_0 This field recorded whether RTC WAKEUP 0 happened. It get set (to 0x1) whenever RTC WAKEUP 0 happened. It get reset (to 0x0) when RTC domain power supply removed or SYS_RESET_N asserted (LOW active). It can also be cleared by.." "0,1" newline bitfld.long 0x20 5. "EXT_WAKEUP_1,EXT_WAKEUP_1 This field recorded whether External WAKEUP 1 happened. It get set (to 0x1) whenever external WAKEUP 1 happened. It get reset (to 0x0) when RTC domain power supply removed or SYS_RESET_N asserted (LOW active). It can also be.." "0,1" newline bitfld.long 0x20 4. "EXT_WAKEUP_0,EXT_WAKEUP_0 This field recorded whether External WAKEUP 0 happened. It get set (to 0x1) whenever external WAKEUP 0 happened. It get reset (to 0x0) when RTC domain power supply removed or SYS_RESET_N asserted (LOW active). It can also be.." "0,1" newline bitfld.long 0x20 3. "EXT_RESET_1,EXT_RESET_1 This field recorded whether External reset 1 happened. It get set (to 0x1) whenever external reset 1 happened. It get reset (to 0x0) when RTC domain power supply removed or SYS_RESET_N asserted (LOW active). It can also be cleared.." "0,1" newline bitfld.long 0x20 2. "EXT_RESET_0,EXT_RESET_0 This field recorded whether External reset 0 happened. It get set (to 0x1) whenever external reset 0 happened. It get reset (to 0x0) when RTC domain power supply removed or SYS_RESET_N asserted (LOW active). It can also be cleared.." "0,1" newline bitfld.long 0x20 1. "INT_PWRDWN_1,INT_PWRDWN_1 This field recorded whether internal power down request 1 happened. It get set (to 0x1) whenever internal power down request 1 happened. It get reset (to 0x0) when RTC domain power supply removed or SYS_RESET_N asserted (LOW.." "0,1" newline bitfld.long 0x20 0. "INT_PWRDWN_0,INT_PWRDWN_0 This field recorded whether internal power down request 0 happened. It get set (to 0x1) whenever internal power down request 0 happened. It get reset (to 0x0) when RTC domain power supply removed or SYS_RESET_N asserted (LOW.." "0,1" repeat 3. (list 0x0 0x1 0x2 )(list 0x0 0x4 0x8 ) group.long ($2+0x24)++0x3 line.long 0x0 "RSVD_$1,RSVD_0" hexmask.long 0x0 0.--31. 1. "RSVD,RSVD" repeat.end repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) rgroup.long ($2+0x30)++0x3 line.long 0x0 "STS_$1,Debounce timer counter for EXT_RESET_0 This register is for internal use only." newline hexmask.long.word 0x0 17.--25. 1. "CNT3,CNT3: counter 3 count for 10ms with 32K clock. This counter is started only when debounce_time_ctrl[3] is one and overflow when count to 10ms." newline hexmask.long.word 0x0 8.--16. 1. "CNT2,CNT2: counter 2 count with 10ms. This counter is started only when debounce_time_ctrl[3] is one." newline hexmask.long.byte 0x0 0.--7. 1. "CNT1,CNT1: counter 1 count with 32K clock from 0 to 127. This counter is started only when debounce_time_ctrl[3] is zero." repeat.end repeat 2. (list 0x2 0x3 )(list 0x0 0x4 ) rgroup.long ($2+0x38)++0x3 line.long 0x0 "STS_$1,Debounce timer counter for EXT_WAKEUP_0 This register is for internal use only." newline hexmask.long.word 0x0 17.--25. 1. "CNT3,CNT3: counter 3 count for 10ms with 32K clock. This counter is started only when debounce_time_ctrl[3] is one and overflow when count to 10ms." newline hexmask.long.word 0x0 8.--16. 1. "CNT2,CNT2: counter 2 count with 1ms. This counter is started only when debounce_time_ctrl[3] is one." newline hexmask.long.byte 0x0 0.--7. 1. "CNT1,CNT1: counter 1 count with 32K clock from 0 to 127. This counter is started only when debounce_time_ctrl[3] is zero." repeat.end elif (CORENAME()=="CORTEXA55") base ad:0x31850000 group.long 0x0++0x23 line.long 0x0 "EXT_CTRL,control register bits for external wakeup and external reset" rbitfld.long 0x0 31. "EXT_WAKEUP_B_1_STATUS,External wakeup 1 status This field indicates the logic level status on external wakeup pin 1 (SYS_WAKEUP1)." "0,1" newline rbitfld.long 0x0 30. "EXT_WAKEUP_B_0_STATUS,External wakeup 0 status This field indicates the logic level status on external wakeup pin 0 (SYS_WAKEUP0)." "0,1" newline rbitfld.long 0x0 29. "EXT_RESET_B_1_STATUS,External reset 1 status This field indicates the logic level status on external reset 1 (EXT_RESET_REQ1)." "0,1" newline rbitfld.long 0x0 28. "EXT_RESET_B_0_STATUS,External reset 0 status This field indicates the logic level status on external reset 0 (EXT_RESET_REQ0)." "0,1" newline hexmask.long.byte 0x0 24.--27. 1. "EXT_WAKEUP_B_1_DEBOUNCE_TIME,External wakeup 1 debounce time control Similar as external wakeup 0." newline bitfld.long 0x0 23. "EXT_WAKEUP_B_1_DEBOUNCE_EN,External wakeup 1 debounce enable Similar as external wakeup 0." "0,1" newline bitfld.long 0x0 22. "EXT_WAKEUP_B_1_POL,External wakeup 1 polarity Similar as external wakeup 0." "0,1" newline bitfld.long 0x0 21. "EXT_WAKEUP_B_1_EN,External wakeup 1 enable Similar as external wakeup 0." "0,1" newline hexmask.long.byte 0x0 17.--20. 1. "EXT_WAKEUP_B_0_DEBOUNCE_TIME,External wakeup 0 debounce time control Similar as external reset 0." newline bitfld.long 0x0 16. "EXT_WAKEUP_B_0_DEBOUNCE_EN,External wakeup 0 debounce enable Similar as external reset 0." "0,1" newline bitfld.long 0x0 15. "EXT_WAKEUP_B_0_POL,External wakeup 0 polarity 0x0 - Low active 0x1 - High active" "Low active,High active" newline bitfld.long 0x0 14. "EXT_WAKEUP_B_0_EN,External wakeup 0 enable 0x0 - External wakeup 0 disabled 0x1 - External wakeup 0 enabled." "External wakeup 0 disabled,External wakeup 0 enabled" newline hexmask.long.byte 0x0 10.--13. 1. "EXT_RESET_B_1_DEBOUNCE_TIME,External reset 1 debounce time control Similar as external reset 0." newline bitfld.long 0x0 9. "EXT_RESET_B_1_DEBOUNCE_EN,External reset 1 debounce enable Similar as external reset 0." "0,1" newline bitfld.long 0x0 8. "EXT_RESET_B_1_POL,External reset 1 polarity Similar as external reset 0." "0,1" newline bitfld.long 0x0 7. "EXT_RESET_B_1_EN,External reset 1 enable Similar as external reset 0." "0,1" newline hexmask.long.byte 0x0 3.--6. 1. "EXT_RESET_B_0_DEBOUNCE_TIME,External reset 0 debounce time control The debounce time will be: 0x0 - (2-1) cycle of rtc clock (32KHz) 0x1 - (3-1) cycle of rtc clock (32KHz) 0x2 - (4-1) cycle of rtc clock (32KHz) 0x3 - (8-1) cycle of rtc clock (32KHz) 0x4.." newline bitfld.long 0x0 2. "EXT_RESET_B_0_DEBOUNCE_EN,External reset 0 debounce enable 0x0 - External reset will take affect immediately when there is any active edge change. 0x1 - External reset will take affect only if the active period lasts longer than the configured debounce.." "External reset will take affect immediately when..,External reset will take affect only if the.." newline bitfld.long 0x0 1. "EXT_RESET_B_0_POL,External reset 0 polarity 0x0 - Low active 0x1 - High active" "Low active,High active" newline bitfld.long 0x0 0. "EXT_RESET_B_0_EN,External reset 0 enable 0x0 - External reset 0 disabled 0x1 - External reset 0 enabled. Note: Software should wait at least 40ms (more than one cycle in 32KHz) between EXT_RESET_B_0_POL setting and EXT_RESET_B_0_EN setting." "External reset 0 disabled,External reset 0 enabled" line.long 0x4 "RTC_CTRL,RTC wakeup control" newline bitfld.long 0x4 1. "RTC_WAKEUP_B_1_EN,RTC wakeup 1 enable 0x0 - RTC wakeup 1 disabled 0x1 - RTC wakeup 1 enabled." "RTC wakeup 1 disabled,RTC wakeup 1 enabled" newline bitfld.long 0x4 0. "RTC_WAKEUP_B_0_EN,RTC wakeup 0 enable 0x0 - RTC wakeup 0 disabled 0x1 - RTC wakeup 0 enabled." "RTC wakeup 0 disabled,RTC wakeup 0 enabled" line.long 0x8 "GF_CTRL,Glitch filter configuration" newline bitfld.long 0x8 11.--13. "GF_CTL,Glitch filter control bit this field apply to all PMU glitch filter circuit. PMU will ignore all high and low pulse which is shorter then glitch filter time if related glitch filter enabled. The glitch filter time is as following (in cycle of RTC.." "0,1,2,3,4,5,6,7" newline hexmask.long.word 0x8 0.--10. 1. "GF_EN,Glitch filter enable bits bit 0 : Glitch filter enable bit for external reset 0 bit 1 : Glitch filter enable bit for external reset 1 bit 2 : Glitch filter enable bit for external wakeup request 0 bit 3 : Glitch filter enable bit for external.." line.long 0xC "RST_CTRL,Reset Configuration" newline hexmask.long.byte 0xC 24.--28. 1. "PMU_STATE,PMU_STATE This field indicates the real PMU state. 0x01 - PMU_INIT 0x02 - PMU_PWRUP 0x04 - PMU_ON 0x08 - PMU_PWRDWN 0x10 - PMU_OFF" newline bitfld.long 0xC 11.--13. "PORPDCTL,Analog POR cell PD control When PMU power down the on-chip POR cell the output rtc_power_stable from POR cell may get LOW but it doesn't mean RTC domain power supply is deasserted. PMU should ignore this POR cell output for a certain time to.." "0,1,2,3,4,5,6,7" newline bitfld.long 0xC 10. "POR_AUTO_PD,POR auto PD 0x1 - PMU will automatically put the on-chip POR cell into low power mode (power down) when PMU enters PMU_OFF state. This can help save more power consumption. 0x0 - PMU will keep the on-chip POR cell in normal operation when PMU.." "PMU will keep the on-chip POR cell in normal..,PMU will automatically put the on-chip POR cell.." newline bitfld.long 0xC 9. "POR_FORCE_PD,POR force PD Software can force POR cell into low power mode (power down) by setting this field bit 0x01 and bring iit back to normal operation by clearing this field bit. It is recommended to change this field only in PMU_ON state." "0,1" newline bitfld.long 0xC 8. "AP_ISO_CTL,ap_iso_b control 0x0 - ap_iso_b will be not asserted when ap_power_stable turn low 0x1 - ap_iso_b will be asserted when ap_power_stable turn low This field is for internal use only." "ap_iso_b will be not asserted when..,ap_iso_b will be asserted when ap_power_stable.." newline bitfld.long 0xC 7. "AP_POR_CTL,ap_por_b control 0x0 - ap_por_b will be not asserted when ap_power_stable turn low 0x1 - ap_por_b will be asserted when ap_power_stable turn low This field is for internal use only." "ap_por_b will be not asserted when..,ap_por_b will be asserted when ap_power_stable.." newline bitfld.long 0xC 6. "SAFETY_ISO_CTL,safety_iso_b control 0x0 - safety_iso_b will be not asserted when safety_power_stable turn low 0x1 - safety_iso_b will be asserted when safety_power_stable turn low This field is for internal use only." "safety_iso_b will be not asserted when..,safety_iso_b will be asserted when.." newline bitfld.long 0xC 5. "SAFETY_POR_CTL,safety_por_b control 0x0 - safety_por_b will be not asserted when safety_power_stable turn low 0x1 - safety_por_b will be asserted when safety_power_stable turn low This field is for internal use only." "safety_por_b will be not asserted when..,safety_por_b will be asserted when.." newline bitfld.long 0xC 4. "IGNORE_AP_RESET,Ignore SoC AP_RESET_N pin input This field controls whether the ap_por_b and ap_iso_b signal is hold asserted (LOW) while SoC AP_RESET_N pin input is active (LOW). 0x0 - ap_por_b/ap_iso_b is kept asserted (LOW) while AP_RESET_N pin input.." "ap_por_b/ap_iso_b is kept asserted,AP_RESET_N input is ignored" newline bitfld.long 0xC 3. "HOLD_AP_ISO,Force AP domain isolation control (ap_iso_b) active (LOW). This is useful when AP domain power supplies are managed by safety Domain CPU cores. It can set this register bit to hold AP isolation active until all related AP domain power supply.." "0,1" newline bitfld.long 0xC 2. "WAIT_AP_POWER_STABLE,Wait on ap_power_stable output from on-chip POR cell This field controls whether AP domain is kept in reset when ap_power_stable from on-chip POR cell is inactive (LOW). 0x0 - The output ap_power_stable from on-chip POR cell is.." "The output ap_power_stable from on-chip POR cell..,AP domain is kept in reset state" newline bitfld.long 0xC 1. "WAIT_SAFETY_POWER_STABLE,Controls if the safety_por_b signal is de-asserted only after safety_power_stable signal is asserted 0x0 - ignore power stable signal from POR cell 0x1 - wait for power stable signal from POR cell Wait on safety_power_stable.." "The output safety_power_stable from on-chip POR..,Safety domain is kept in reset state" newline bitfld.long 0xC 0. "WAIT_RTC_POWER_STABLE,Wait on rtc_power_stable output from on-chip POR cell This field controls whether RTC domain (except PMU) is kept in reset (rtc_por_b is active/LOW) when rtc_power_stable from on-chip POR cell is inactive (LOW). 0x0 - The output.." "The output rtc_power_stable from on-chip POR..,RTC domain is kept in reset state" line.long 0x10 "PWR_CTRL_0,power up/down configuration" newline bitfld.long 0x10 8. "PWR_DOWN,Force PMU power down Software can force PMU to enter PMU_OFF state by setting this field bit from 0x0 to 0x1." "0,1" newline hexmask.long.byte 0x10 4.--7. 1. "PWR_DOWN_DELAY,PMU power down delay This field configures the power down delay for PMU. 0x0 - 0us 0x1 - 30us 0x2 - 60us 0x3 - 120us 0x4 - 0.25us 0x5 - 0.5ms 0x6 - 0.75ms 0x7 - 1ms 0x8 - 2ms 0x9 - 3ms 0xA - 4ms 0xB - 5ms 0xC - 6ms 0xD - 7ms 0xE - 8ms 0xF.." newline hexmask.long.byte 0x10 0.--3. 1. "PWR_UP_DELAY,PMU power up delay This field configures the power up delay for PMU. 0x0 - 0us 0x1 - 30us 0x2 - 60us 0x3 - 120us 0x4 - 0.25us 0x5 - 0.5ms 0x6 - 0.75ms 0x7 - 1ms 0x8 - 2ms 0x9 - 3ms 0xA - 4ms 0xB - 5ms 0xC - 6ms 0xD - 7ms 0xE - 8ms 0xF - 16ms" line.long 0x14 "PWR_CTRL_1,PWRCTRL0/PWRCTRL1 pin configuration" rbitfld.long 0x14 31. "INLVL1,PWRCTRL1 input status This field indicates the pin input status of PWRCTRL1. It has no meaning when this pin is configured in output mode (IOMODE1=0x0)." "0,1" newline rbitfld.long 0x14 30. "INLVL0,PWRCTRL0 input status This field indicates the pin input status of PWRCTRL0. It has no meaning when this pin is configured in output mode (IOMODE0=0x0)." "0,1" newline bitfld.long 0x14 21. "OUTLVL1,PWRCTRL1 output level control This field control the output level for PWRCTRL1 pin. 0x0 - Low 0x1 - High This field setting is ignored when this pin is configured in input mode (IOMODE1=0x1) or output level mode is 0x0 (CTLMODE1=0x0)." "Low,High" newline bitfld.long 0x14 20. "CTLMODE1,PWRCTRL1 output level mode This field control the output level logic for PWRCTRL1 pin. 0x0 - PMU automatically determines the pin output level according to PMU state. PWRCTRL1 get asserted (HIGH) when PMU enters PMU_PWRUP state with power up.." "PMU automatically determines the pin output..,The pin output level is controlled by software.." newline bitfld.long 0x14 19. "IOMODE1,PWRCTRL1 IO mode This field controls the IO mode of PWRCTRL1 pin. 0x0 - Output mode 0x1 - Input mode" "Output mode,Input mode" newline hexmask.long.byte 0x14 15.--18. 1. "PWRDOWNDELAY1,PWRCTRL1 power down delay configuration 0x0 - 0us 0x1 - 30us 0x2 - 60us 0x3 - 120us 0x4 - 0.25us 0x5 - 0.5ms 0x6 - 0.75ms 0x7 - 1ms 0x8 - 2ms 0x9 - 3ms 0xA - 4ms 0xB - 5ms 0xC - 6ms 0xD - 7ms 0xE - 8ms 0xF - 16ms" newline hexmask.long.byte 0x14 11.--14. 1. "PWRUPDELAY1,PWRCTRL1 power up delay configuration 0x0 - 0us 0x1 - 30us 0x2 - 60us 0x3 - 120us 0x4 - 0.25us 0x5 - 0.5ms 0x6 - 0.75ms 0x7 - 1ms 0x8 - 2ms 0x9 - 3ms 0xA - 4ms 0xB - 5ms 0xC - 6ms 0xD - 7ms 0xE - 8ms 0xF - 16ms" newline bitfld.long 0x14 10. "OUTLVL0,PWRCTRL0 output level control This field control the output level for PWRCTRL0 pin. 0x0 - Low 0x1 - High This field setting is ignored when this pin is configured in input mode (IOMODE0=0x1) or output level mode is 0x0 (CTLMODE0=0x0)." "Low,High" newline bitfld.long 0x14 9. "CTLMODE0,PWRCTRL0 output level mode This field control the output level logic for PWRCTRL0 pin. 0x0 - PMU automatically determines the pin output level according to PMU state. PWRCTRL0 get asserted (HIGH) when PMU enters PMU_PWRUP state with power up.." "PMU automatically determines the pin output..,The pin output level is controlled by software.." newline bitfld.long 0x14 8. "IOMODE0,PWRCTRL0 IO mode This field controls the IO mode of PWRCTRL0 pin. 0x0 - Output mode 0x1 - Input mode" "Output mode,Input mode" newline hexmask.long.byte 0x14 4.--7. 1. "PWRDOWNDELAY0,PWRCTRL0 power down delay configuration 0x0 - 0us 0x1 - 30us 0x2 - 60us 0x3 - 120us 0x4 - 0.25us 0x5 - 0.5ms 0x6 - 0.75ms 0x7 - 1ms 0x8 - 2ms 0x9 - 3ms 0xA - 4ms 0xB - 5ms 0xC - 6ms 0xD - 7ms 0xE - 8ms 0xF - 16ms" newline hexmask.long.byte 0x14 0.--3. 1. "PWRUPDELAY0,PWRCTRL0 power up delay configuration 0x0 - 0us 0x1 - 30us 0x2 - 60us 0x3 - 120us 0x4 - 0.25us 0x5 - 0.5ms 0x6 - 0.75ms 0x7 - 1ms 0x8 - 2ms 0x9 - 3ms 0xA - 4ms 0xB - 5ms 0xC - 6ms 0xD - 7ms 0xE - 8ms 0xF - 16ms" line.long 0x18 "PWR_CTRL_2,PWRCTRL2/PWRCTRL3 pin configuration" rbitfld.long 0x18 31. "INLVL3,PWRCTRL3 input status This field indicates the pin input status of PWRCTRL3. It has no meaning when this pin is configured in output mode (IOMODE3=0x0)." "0,1" newline rbitfld.long 0x18 30. "INLVL2,PWRCTRL2 input status This field indicates the pin input status of PWRCTRL2. It has no meaning when this pin is configured in output mode (IOMODE2=0x0)." "0,1" newline bitfld.long 0x18 21. "OUTLVL3,PWRCTRL3 output level control This field control the output level for PWRCTRL3 pin. 0x0 - Low 0x1 - High This field setting is ignored when this pin is configured in input mode (IOMODE3=0x1) or output level mode is 0x0 (CTLMODE3=0x0)." "Low,High" newline bitfld.long 0x18 20. "CTLMODE3,PWRCTRL3 output level mode This field control the output level logic for PWRCTRL3 pin. 0x0 - PMU automatically determines the pin output level according to PMU state. PWRCTRL3 get asserted (HIGH) when PMU enters PMU_PWRUP state with power up.." "PMU automatically determines the pin output..,The pin output level is controlled by software.." newline bitfld.long 0x18 19. "IOMODE3,PWRCTRL3 IO mode This field controls the IO mode of PWRCTRL3 pin. 0x0 - Output mode 0x1 - Input mode" "Output mode,Input mode" newline hexmask.long.byte 0x18 15.--18. 1. "PWRDOWNDELAY3,PWRCTRL3 power down delay configuration 0x0 - 0us 0x1 - 30us 0x2 - 60us 0x3 - 120us 0x4 - 0.25us 0x5 - 0.5ms 0x6 - 0.75ms 0x7 - 1ms 0x8 - 2ms 0x9 - 3ms 0xA - 4ms 0xB - 5ms 0xC - 6ms 0xD - 7ms 0xE - 8ms 0xF - 16ms" newline hexmask.long.byte 0x18 11.--14. 1. "PWRUPDELAY3,PWRCTRL3 power up delay configuration 0x0 - 0us 0x1 - 30us 0x2 - 60us 0x3 - 120us 0x4 - 0.25us 0x5 - 0.5ms 0x6 - 0.75ms 0x7 - 1ms 0x8 - 2ms 0x9 - 3ms 0xA - 4ms 0xB - 5ms 0xC - 6ms 0xD - 7ms 0xE - 8ms 0xF - 16ms" newline bitfld.long 0x18 10. "OUTLVL2,PWRCTRL2 output level control This field control the output level for PWRCTRL2 pin. 0x0 - Low 0x1 - High This field setting is ignored when this pin is configured in input mode (IOMODE2=0x1) or output level mode is 0x0 (CTLMODE2=0x0)." "Low,High" newline bitfld.long 0x18 9. "CTLMODE2,PWRCTRL2 output level mode This field control the output level logic for PWRCTRL2 pin. 0x0 - PMU automatically determines the pin output level according to PMU state. PWRCTRL2 get asserted (HIGH) when PMU enters PMU_PWRUP state with power up.." "PMU automatically determines the pin output..,The pin output level is controlled by software.." newline bitfld.long 0x18 8. "IOMODE2,PWRCTRL2 IO mode This field controls the IO mode of PWRCTRL2 pin. 0x0 - Output mode 0x1 - Input mode" "Output mode,Input mode" newline hexmask.long.byte 0x18 4.--7. 1. "PWRDOWNDELAY2,PWRCTRL2 power down delay configuration 0x0 - 0us 0x1 - 30us 0x2 - 60us 0x3 - 120us 0x4 - 0.25us 0x5 - 0.5ms 0x6 - 0.75ms 0x7 - 1ms 0x8 - 2ms 0x9 - 3ms 0xA - 4ms 0xB - 5ms 0xC - 6ms 0xD - 7ms 0xE - 8ms 0xF - 16ms" newline hexmask.long.byte 0x18 0.--3. 1. "PWRUPDELAY2,PWRCTRL2 power up delay configuration 0x0 - 0us 0x1 - 30us 0x2 - 60us 0x3 - 120us 0x4 - 0.25us 0x5 - 0.5ms 0x6 - 0.75ms 0x7 - 1ms 0x8 - 2ms 0x9 - 3ms 0xA - 4ms 0xB - 5ms 0xC - 6ms 0xD - 7ms 0xE - 8ms 0xF - 16ms" line.long 0x1C "PWR_CTRL_3,control register bits for internal power down request (from on-chip temperature sensor)" newline rbitfld.long 0x1C 9. "INT_PWRDWN_B_1_STATUS,Internal power down request 1 status This field indicates the real status of internal power down request 1." "0,1" newline rbitfld.long 0x1C 8. "INT_PWRDWN_B_0_STATUS,Internal power down request 0 status This field indicates the real status of internal power down request 0." "0,1" newline bitfld.long 0x1C 3. "INT_PWRDWN_B_1_POL,Internal power down request 1 polarity 0x0 - Low active 0x1 - High active" "Low active,High active" newline bitfld.long 0x1C 2. "INT_PWRDWN_B_1_EN,Internal power down request 1 enable 0x0 - Internal power down disabled 0x1 - Internal power down enabled" "Internal power down disabled,Internal power down enabled" newline bitfld.long 0x1C 1. "INT_PWRDWN_B_0_POL,Internal power down request 0 polarity 0x0 - Low active 0x1 - High active" "Low active,High active" newline bitfld.long 0x1C 0. "INT_PWRDWN_B_0_EN,Internal power down request 0 enable 0x0 - Internal power down disabled 0x1 - Internal power down enabled" "Internal power down disabled,Internal power down enabled" line.long 0x20 "STICKY_STS_0,Sticky status 0 This register records whether any external reset. external wakeup. rtc wakeup and internal power down requesst happened. This register gets reset only when RTC Domain power supply removed or SYS_RESET_N get asserted." hexmask.long.tbyte 0x20 8.--31. 1. "RSVD0,RSVD0" newline bitfld.long 0x20 7. "RTC_WAKEUP_1,RTC_WAKEUP_1 This field recorded whether RTC WAKEUP 1 happened. It get set (to 0x1) whenever RTC WAKEUP happened. It get reset (to 0x0) when RTC domain power supply removed or SYS_RESET_N asserted (LOW active). It can also be cleared by.." "0,1" newline bitfld.long 0x20 6. "RTC_WAKEUP_0,RTC_WAKEUP_0 This field recorded whether RTC WAKEUP 0 happened. It get set (to 0x1) whenever RTC WAKEUP 0 happened. It get reset (to 0x0) when RTC domain power supply removed or SYS_RESET_N asserted (LOW active). It can also be cleared by.." "0,1" newline bitfld.long 0x20 5. "EXT_WAKEUP_1,EXT_WAKEUP_1 This field recorded whether External WAKEUP 1 happened. It get set (to 0x1) whenever external WAKEUP 1 happened. It get reset (to 0x0) when RTC domain power supply removed or SYS_RESET_N asserted (LOW active). It can also be.." "0,1" newline bitfld.long 0x20 4. "EXT_WAKEUP_0,EXT_WAKEUP_0 This field recorded whether External WAKEUP 0 happened. It get set (to 0x1) whenever external WAKEUP 0 happened. It get reset (to 0x0) when RTC domain power supply removed or SYS_RESET_N asserted (LOW active). It can also be.." "0,1" newline bitfld.long 0x20 3. "EXT_RESET_1,EXT_RESET_1 This field recorded whether External reset 1 happened. It get set (to 0x1) whenever external reset 1 happened. It get reset (to 0x0) when RTC domain power supply removed or SYS_RESET_N asserted (LOW active). It can also be cleared.." "0,1" newline bitfld.long 0x20 2. "EXT_RESET_0,EXT_RESET_0 This field recorded whether External reset 0 happened. It get set (to 0x1) whenever external reset 0 happened. It get reset (to 0x0) when RTC domain power supply removed or SYS_RESET_N asserted (LOW active). It can also be cleared.." "0,1" newline bitfld.long 0x20 1. "INT_PWRDWN_1,INT_PWRDWN_1 This field recorded whether internal power down request 1 happened. It get set (to 0x1) whenever internal power down request 1 happened. It get reset (to 0x0) when RTC domain power supply removed or SYS_RESET_N asserted (LOW.." "0,1" newline bitfld.long 0x20 0. "INT_PWRDWN_0,INT_PWRDWN_0 This field recorded whether internal power down request 0 happened. It get set (to 0x1) whenever internal power down request 0 happened. It get reset (to 0x0) when RTC domain power supply removed or SYS_RESET_N asserted (LOW.." "0,1" repeat 3. (list 0x0 0x1 0x2 )(list 0x0 0x4 0x8 ) group.long ($2+0x24)++0x3 line.long 0x0 "RSVD_$1,RSVD_0" hexmask.long 0x0 0.--31. 1. "RSVD,RSVD" repeat.end repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) rgroup.long ($2+0x30)++0x3 line.long 0x0 "STS_$1,Debounce timer counter for EXT_RESET_0 This register is for internal use only." newline hexmask.long.word 0x0 17.--25. 1. "CNT3,CNT3: counter 3 count for 10ms with 32K clock. This counter is started only when debounce_time_ctrl[3] is one and overflow when count to 10ms." newline hexmask.long.word 0x0 8.--16. 1. "CNT2,CNT2: counter 2 count with 10ms. This counter is started only when debounce_time_ctrl[3] is one." newline hexmask.long.byte 0x0 0.--7. 1. "CNT1,CNT1: counter 1 count with 32K clock from 0 to 127. This counter is started only when debounce_time_ctrl[3] is zero." repeat.end repeat 2. (list 0x2 0x3 )(list 0x0 0x4 ) rgroup.long ($2+0x38)++0x3 line.long 0x0 "STS_$1,Debounce timer counter for EXT_WAKEUP_0 This register is for internal use only." newline hexmask.long.word 0x0 17.--25. 1. "CNT3,CNT3: counter 3 count for 10ms with 32K clock. This counter is started only when debounce_time_ctrl[3] is one and overflow when count to 10ms." newline hexmask.long.word 0x0 8.--16. 1. "CNT2,CNT2: counter 2 count with 1ms. This counter is started only when debounce_time_ctrl[3] is one." newline hexmask.long.byte 0x0 0.--7. 1. "CNT1,CNT1: counter 1 count with 32K clock from 0 to 127. This counter is started only when debounce_time_ctrl[3] is zero." repeat.end endif tree.end tree "PVT_SENS (PVT Sensor)" sif (CORENAME()=="CORTEXR5F") tree "PVT_SNS_SAFETY" base ad:0xF02C0000 group.long 0x0++0x3 line.long 0x0 "PVT_CTRL,PVT CONTROL REGISTER" bitfld.long 0x0 19. "RF_MODE_EN_1,pvt alarm rising/falling mode enable for ctrl_1 0: disable 1: enable" "disable,enable" bitfld.long 0x0 18. "HL_MODE_EN_1,pvt alarm high/low mode enable for ctrl_1 0: disable 1: enable" "disable,enable" bitfld.long 0x0 17. "RF_MODE_EN_0,pvt alarm rising/falling mode enable for ctrl_0 0: disable 1: enable" "disable,enable" bitfld.long 0x0 16. "HL_MODE_EN_0,pvt alarm high/low mode enable for ctrl_0 0: disable 1: enable" "disable,enable" newline hexmask.long.byte 0x0 10.--15. 1. "TRIMO,Trim offset bits Optional programmable inputs which may be used to improve the absolute accuracy of the temperature sensor. The optimal values may be ascertained during test or at any other time.TRIMO bits are sampled when ENA goes from 0 to.." hexmask.long.byte 0x0 5.--9. 1. "TRIMG,trim gain bits Optional programmable inputs which may be used to improve the absolute accuracy of the temperature sensor. The optimalvalues may be ascertained during test or at any other time.TRIMGbits are only to be changed while ENA=0.Default.." bitfld.long 0x0 4. "SENS_EN,software control sensor enable 0: disable 1: enable" "disable,enable" bitfld.long 0x0 2.--3. "PMODE,process detect mode" "0,1,2,3" bitfld.long 0x0 1. "VMODE,voltage detect mode" "0,1" newline bitfld.long 0x0 0. "MODE,control mode: 1: from register 0: from fuse" "from fuse,from register" rgroup.long 0x4++0x3 line.long 0x0 "PVT_DOUT,PVT DATA OUT REGISTER" hexmask.long.word 0x0 1.--10. 1. "DOUT,pvt dout value" bitfld.long 0x0 0. "VALID,pvt dout valid indicate 0: invalid 1: valid because pvt enable is triggerd one by one the design use the posedge of enable so the valid is not active all the time. debug only. no need for software" "invalid,valid" group.long 0x8++0xF line.long 0x0 "PVT_HYST_H,PVT ALARM HYST HIGH MODE SETTING" hexmask.long.word 0x0 10.--19. 1. "THRESH_L,alarm low setting" hexmask.long.word 0x0 0.--9. 1. "THRESH_H,alarm high setting" line.long 0x4 "PVT_HYST_L,PVT ALARM HYST LOW MODE SETTING" hexmask.long.word 0x4 10.--19. 1. "THRESH_L,alarm low setting" hexmask.long.word 0x4 0.--9. 1. "THRESH_H,alarm high setting" line.long 0x8 "PVT_HYST_R,PVT ALARM HYST MODE SETTING" hexmask.long.word 0x8 10.--19. 1. "HYST,hyst setting" hexmask.long.word 0x8 0.--9. 1. "ALARM,alarm setting" line.long 0xC "PVT_HYST_F,PVT ALARM HYST MODE SETTING" hexmask.long.word 0xC 10.--19. 1. "HYST,hyst setting" hexmask.long.word 0xC 0.--9. 1. "ALARM,alarm setting" rgroup.long 0x18++0x3 line.long 0x0 "PVT_HYST_TIMER,PVT HYST TIMER" hexmask.long.word 0x0 16.--31. 1. "F_TIMER,hyst falling time record" hexmask.long.word 0x0 0.--15. 1. "R_TIMER,hyst rising time record" group.long 0x1C++0x3 line.long 0x0 "PVT_INT_EN,PVT INTERRUPT ENABLE" bitfld.long 0x0 3. "HYST_F,hyst falling mode output beyond alarm interrupt enable" "0,1" bitfld.long 0x0 2. "HYST_R,hyst rising mode output beyond alarm interrupt enable" "0,1" bitfld.long 0x0 1. "HYST_LOW,hyst h/l mode output beyond alarm low interrupt enable" "0,1" bitfld.long 0x0 0. "HYST_HIGH,hyst h/l mode output beyond alarm high interrupt enable" "0,1" rgroup.long 0x20++0x3 line.long 0x0 "PVT_INT_STATUS,PVT INTERRUPT STATUS" bitfld.long 0x0 3. "HYST_F,hyst falling mode output beyond alarm interrupt status" "0,1" bitfld.long 0x0 2. "HYST_R,hyst rising mode output beyond alarm interrupt status" "0,1" bitfld.long 0x0 1. "HYST_LOW,hyst h/l mode output beyond alarm low interrupt status" "0,1" bitfld.long 0x0 0. "HYST_HIGH,hyst h/l mode output beyond alarm high interrupt status" "0,1" group.long 0x24++0x13 line.long 0x0 "PVT_INT_CLR,PVT INTERRUPT CLEAR" bitfld.long 0x0 3. "HYST_F,hyst falling mode output beyond alarm interrupt clear. this is auto clear register." "0,1" bitfld.long 0x0 2. "HYST_R,hyst rising mode output beyond alarm interrupt clear. this is auto clear register." "0,1" bitfld.long 0x0 1. "HYST_LOW,hyst h/l mode output beyond alarm low interrupt clear. this is auto clear register." "0,1" bitfld.long 0x0 0. "HYST_HIGH,hyst h/l mode output beyond alarm high interrupt clear. this is auto clear register." "0,1" line.long 0x4 "PVT_HYST_H_1,PVT ALARM HYST HIGH MODE SETTING" hexmask.long.word 0x4 10.--19. 1. "THRESH_L,alarm low setting" hexmask.long.word 0x4 0.--9. 1. "THRESH_H,alarm high setting" line.long 0x8 "PVT_HYST_L_1,PVT ALARM HYST LOW MODE SETTING" hexmask.long.word 0x8 10.--19. 1. "THRESH_L,alarm low setting" hexmask.long.word 0x8 0.--9. 1. "THRESH_H,alarm high setting" line.long 0xC "PVT_HYST_R_1,PVT ALARM HYST MODE SETTING" hexmask.long.word 0xC 10.--19. 1. "HYST,hyst setting" hexmask.long.word 0xC 0.--9. 1. "ALARM,alarm setting" line.long 0x10 "PVT_HYST_F_1,PVT ALARM HYST MODE SETTING" hexmask.long.word 0x10 10.--19. 1. "HYST,hyst setting" hexmask.long.word 0x10 0.--9. 1. "ALARM,alarm setting" rgroup.long 0x38++0x3 line.long 0x0 "PVT_HYST_TIMER_1,PVT HYST TIMER" hexmask.long.word 0x0 16.--31. 1. "F_TIMER,hyst falling time record" hexmask.long.word 0x0 0.--15. 1. "R_TIMER,hyst rising time record" group.long 0x3C++0x3 line.long 0x0 "PVT_INT_EN_1,PVT INTERRUPT ENABLE" bitfld.long 0x0 3. "HYST_F,hyst falling mode output beyond alarm interrupt enable" "0,1" bitfld.long 0x0 2. "HYST_R,hyst rising mode output beyond alarm interrupt enable" "0,1" bitfld.long 0x0 1. "HYST_LOW,hyst h/l mode output beyond alarm low interrupt enable" "0,1" bitfld.long 0x0 0. "HYST_HIGH,hyst h/l mode output beyond alarm high interrupt enable" "0,1" rgroup.long 0x40++0x3 line.long 0x0 "PVT_INT_STATUS_1,PVT INTERRUPT STATUS" bitfld.long 0x0 3. "HYST_F,hyst falling mode output beyond alarm interrupt status" "0,1" bitfld.long 0x0 2. "HYST_R,hyst rising mode output beyond alarm interrupt status" "0,1" bitfld.long 0x0 1. "HYST_LOW,hyst h/l mode output beyond alarm low interrupt status" "0,1" bitfld.long 0x0 0. "HYST_HIGH,hyst h/l mode output beyond alarm high interrupt status" "0,1" group.long 0x44++0x3 line.long 0x0 "PVT_INT_CLR_1,PVT INTERRUPT CLEAR" bitfld.long 0x0 3. "HYST_F,hyst falling mode output beyond alarm interrupt clear. this is auto clear register." "0,1" bitfld.long 0x0 2. "HYST_R,hyst rising mode output beyond alarm interrupt clear. this is auto clear register." "0,1" bitfld.long 0x0 1. "HYST_LOW,hyst h/l mode output beyond alarm low interrupt clear. this is auto clear register." "0,1" bitfld.long 0x0 0. "HYST_HIGH,hyst h/l mode output beyond alarm high interrupt clear. this is auto clear register." "0,1" tree.end tree "PVT_SNS_AP" base ad:0xF0880000 group.long 0x0++0x3 line.long 0x0 "PVT_CTRL,PVT CONTROL REGISTER" bitfld.long 0x0 19. "RF_MODE_EN_1,pvt alarm rising/falling mode enable for ctrl_1 0: disable 1: enable" "disable,enable" bitfld.long 0x0 18. "HL_MODE_EN_1,pvt alarm high/low mode enable for ctrl_1 0: disable 1: enable" "disable,enable" bitfld.long 0x0 17. "RF_MODE_EN_0,pvt alarm rising/falling mode enable for ctrl_0 0: disable 1: enable" "disable,enable" bitfld.long 0x0 16. "HL_MODE_EN_0,pvt alarm high/low mode enable for ctrl_0 0: disable 1: enable" "disable,enable" newline hexmask.long.byte 0x0 10.--15. 1. "TRIMO,Trim offset bits Optional programmable inputs which may be used to improve the absolute accuracy of the temperature sensor. The optimal values may be ascertained during test or at any other time.TRIMO bits are sampled when ENA goes from 0 to.." hexmask.long.byte 0x0 5.--9. 1. "TRIMG,trim gain bits Optional programmable inputs which may be used to improve the absolute accuracy of the temperature sensor. The optimalvalues may be ascertained during test or at any other time.TRIMGbits are only to be changed while ENA=0.Default.." bitfld.long 0x0 4. "SENS_EN,software control sensor enable 0: disable 1: enable" "disable,enable" bitfld.long 0x0 2.--3. "PMODE,process detect mode" "0,1,2,3" bitfld.long 0x0 1. "VMODE,voltage detect mode" "0,1" newline bitfld.long 0x0 0. "MODE,control mode: 1: from register 0: from fuse" "from fuse,from register" rgroup.long 0x4++0x3 line.long 0x0 "PVT_DOUT,PVT DATA OUT REGISTER" hexmask.long.word 0x0 1.--10. 1. "DOUT,pvt dout value" bitfld.long 0x0 0. "VALID,pvt dout valid indicate 0: invalid 1: valid because pvt enable is triggerd one by one the design use the posedge of enable so the valid is not active all the time. debug only. no need for software" "invalid,valid" group.long 0x8++0xF line.long 0x0 "PVT_HYST_H,PVT ALARM HYST HIGH MODE SETTING" hexmask.long.word 0x0 10.--19. 1. "THRESH_L,alarm low setting" hexmask.long.word 0x0 0.--9. 1. "THRESH_H,alarm high setting" line.long 0x4 "PVT_HYST_L,PVT ALARM HYST LOW MODE SETTING" hexmask.long.word 0x4 10.--19. 1. "THRESH_L,alarm low setting" hexmask.long.word 0x4 0.--9. 1. "THRESH_H,alarm high setting" line.long 0x8 "PVT_HYST_R,PVT ALARM HYST MODE SETTING" hexmask.long.word 0x8 10.--19. 1. "HYST,hyst setting" hexmask.long.word 0x8 0.--9. 1. "ALARM,alarm setting" line.long 0xC "PVT_HYST_F,PVT ALARM HYST MODE SETTING" hexmask.long.word 0xC 10.--19. 1. "HYST,hyst setting" hexmask.long.word 0xC 0.--9. 1. "ALARM,alarm setting" rgroup.long 0x18++0x3 line.long 0x0 "PVT_HYST_TIMER,PVT HYST TIMER" hexmask.long.word 0x0 16.--31. 1. "F_TIMER,hyst falling time record" hexmask.long.word 0x0 0.--15. 1. "R_TIMER,hyst rising time record" group.long 0x1C++0x3 line.long 0x0 "PVT_INT_EN,PVT INTERRUPT ENABLE" bitfld.long 0x0 3. "HYST_F,hyst falling mode output beyond alarm interrupt enable" "0,1" bitfld.long 0x0 2. "HYST_R,hyst rising mode output beyond alarm interrupt enable" "0,1" bitfld.long 0x0 1. "HYST_LOW,hyst h/l mode output beyond alarm low interrupt enable" "0,1" bitfld.long 0x0 0. "HYST_HIGH,hyst h/l mode output beyond alarm high interrupt enable" "0,1" rgroup.long 0x20++0x3 line.long 0x0 "PVT_INT_STATUS,PVT INTERRUPT STATUS" bitfld.long 0x0 3. "HYST_F,hyst falling mode output beyond alarm interrupt status" "0,1" bitfld.long 0x0 2. "HYST_R,hyst rising mode output beyond alarm interrupt status" "0,1" bitfld.long 0x0 1. "HYST_LOW,hyst h/l mode output beyond alarm low interrupt status" "0,1" bitfld.long 0x0 0. "HYST_HIGH,hyst h/l mode output beyond alarm high interrupt status" "0,1" group.long 0x24++0x13 line.long 0x0 "PVT_INT_CLR,PVT INTERRUPT CLEAR" bitfld.long 0x0 3. "HYST_F,hyst falling mode output beyond alarm interrupt clear. this is auto clear register." "0,1" bitfld.long 0x0 2. "HYST_R,hyst rising mode output beyond alarm interrupt clear. this is auto clear register." "0,1" bitfld.long 0x0 1. "HYST_LOW,hyst h/l mode output beyond alarm low interrupt clear. this is auto clear register." "0,1" bitfld.long 0x0 0. "HYST_HIGH,hyst h/l mode output beyond alarm high interrupt clear. this is auto clear register." "0,1" line.long 0x4 "PVT_HYST_H_1,PVT ALARM HYST HIGH MODE SETTING" hexmask.long.word 0x4 10.--19. 1. "THRESH_L,alarm low setting" hexmask.long.word 0x4 0.--9. 1. "THRESH_H,alarm high setting" line.long 0x8 "PVT_HYST_L_1,PVT ALARM HYST LOW MODE SETTING" hexmask.long.word 0x8 10.--19. 1. "THRESH_L,alarm low setting" hexmask.long.word 0x8 0.--9. 1. "THRESH_H,alarm high setting" line.long 0xC "PVT_HYST_R_1,PVT ALARM HYST MODE SETTING" hexmask.long.word 0xC 10.--19. 1. "HYST,hyst setting" hexmask.long.word 0xC 0.--9. 1. "ALARM,alarm setting" line.long 0x10 "PVT_HYST_F_1,PVT ALARM HYST MODE SETTING" hexmask.long.word 0x10 10.--19. 1. "HYST,hyst setting" hexmask.long.word 0x10 0.--9. 1. "ALARM,alarm setting" rgroup.long 0x38++0x3 line.long 0x0 "PVT_HYST_TIMER_1,PVT HYST TIMER" hexmask.long.word 0x0 16.--31. 1. "F_TIMER,hyst falling time record" hexmask.long.word 0x0 0.--15. 1. "R_TIMER,hyst rising time record" group.long 0x3C++0x3 line.long 0x0 "PVT_INT_EN_1,PVT INTERRUPT ENABLE" bitfld.long 0x0 3. "HYST_F,hyst falling mode output beyond alarm interrupt enable" "0,1" bitfld.long 0x0 2. "HYST_R,hyst rising mode output beyond alarm interrupt enable" "0,1" bitfld.long 0x0 1. "HYST_LOW,hyst h/l mode output beyond alarm low interrupt enable" "0,1" bitfld.long 0x0 0. "HYST_HIGH,hyst h/l mode output beyond alarm high interrupt enable" "0,1" rgroup.long 0x40++0x3 line.long 0x0 "PVT_INT_STATUS_1,PVT INTERRUPT STATUS" bitfld.long 0x0 3. "HYST_F,hyst falling mode output beyond alarm interrupt status" "0,1" bitfld.long 0x0 2. "HYST_R,hyst rising mode output beyond alarm interrupt status" "0,1" bitfld.long 0x0 1. "HYST_LOW,hyst h/l mode output beyond alarm low interrupt status" "0,1" bitfld.long 0x0 0. "HYST_HIGH,hyst h/l mode output beyond alarm high interrupt status" "0,1" group.long 0x44++0x3 line.long 0x0 "PVT_INT_CLR_1,PVT INTERRUPT CLEAR" bitfld.long 0x0 3. "HYST_F,hyst falling mode output beyond alarm interrupt clear. this is auto clear register." "0,1" bitfld.long 0x0 2. "HYST_R,hyst rising mode output beyond alarm interrupt clear. this is auto clear register." "0,1" bitfld.long 0x0 1. "HYST_LOW,hyst h/l mode output beyond alarm low interrupt clear. this is auto clear register." "0,1" bitfld.long 0x0 0. "HYST_HIGH,hyst h/l mode output beyond alarm high interrupt clear. this is auto clear register." "0,1" tree.end elif (CORENAME()=="CORTEXA55") tree "PVT_SNS_SAFETY" base ad:0x302C0000 group.long 0x0++0x3 line.long 0x0 "PVT_CTRL,PVT CONTROL REGISTER" bitfld.long 0x0 19. "RF_MODE_EN_1,pvt alarm rising/falling mode enable for ctrl_1 0: disable 1: enable" "disable,enable" bitfld.long 0x0 18. "HL_MODE_EN_1,pvt alarm high/low mode enable for ctrl_1 0: disable 1: enable" "disable,enable" bitfld.long 0x0 17. "RF_MODE_EN_0,pvt alarm rising/falling mode enable for ctrl_0 0: disable 1: enable" "disable,enable" bitfld.long 0x0 16. "HL_MODE_EN_0,pvt alarm high/low mode enable for ctrl_0 0: disable 1: enable" "disable,enable" newline hexmask.long.byte 0x0 10.--15. 1. "TRIMO,Trim offset bits Optional programmable inputs which may be used to improve the absolute accuracy of the temperature sensor. The optimal values may be ascertained during test or at any other time.TRIMO bits are sampled when ENA goes from 0 to.." hexmask.long.byte 0x0 5.--9. 1. "TRIMG,trim gain bits Optional programmable inputs which may be used to improve the absolute accuracy of the temperature sensor. The optimalvalues may be ascertained during test or at any other time.TRIMGbits are only to be changed while ENA=0.Default.." bitfld.long 0x0 4. "SENS_EN,software control sensor enable 0: disable 1: enable" "disable,enable" bitfld.long 0x0 2.--3. "PMODE,process detect mode" "0,1,2,3" bitfld.long 0x0 1. "VMODE,voltage detect mode" "0,1" newline bitfld.long 0x0 0. "MODE,control mode: 1: from register 0: from fuse" "from fuse,from register" rgroup.long 0x4++0x3 line.long 0x0 "PVT_DOUT,PVT DATA OUT REGISTER" hexmask.long.word 0x0 1.--10. 1. "DOUT,pvt dout value" bitfld.long 0x0 0. "VALID,pvt dout valid indicate 0: invalid 1: valid because pvt enable is triggerd one by one the design use the posedge of enable so the valid is not active all the time. debug only. no need for software" "invalid,valid" group.long 0x8++0xF line.long 0x0 "PVT_HYST_H,PVT ALARM HYST HIGH MODE SETTING" hexmask.long.word 0x0 10.--19. 1. "THRESH_L,alarm low setting" hexmask.long.word 0x0 0.--9. 1. "THRESH_H,alarm high setting" line.long 0x4 "PVT_HYST_L,PVT ALARM HYST LOW MODE SETTING" hexmask.long.word 0x4 10.--19. 1. "THRESH_L,alarm low setting" hexmask.long.word 0x4 0.--9. 1. "THRESH_H,alarm high setting" line.long 0x8 "PVT_HYST_R,PVT ALARM HYST MODE SETTING" hexmask.long.word 0x8 10.--19. 1. "HYST,hyst setting" hexmask.long.word 0x8 0.--9. 1. "ALARM,alarm setting" line.long 0xC "PVT_HYST_F,PVT ALARM HYST MODE SETTING" hexmask.long.word 0xC 10.--19. 1. "HYST,hyst setting" hexmask.long.word 0xC 0.--9. 1. "ALARM,alarm setting" rgroup.long 0x18++0x3 line.long 0x0 "PVT_HYST_TIMER,PVT HYST TIMER" hexmask.long.word 0x0 16.--31. 1. "F_TIMER,hyst falling time record" hexmask.long.word 0x0 0.--15. 1. "R_TIMER,hyst rising time record" group.long 0x1C++0x3 line.long 0x0 "PVT_INT_EN,PVT INTERRUPT ENABLE" bitfld.long 0x0 3. "HYST_F,hyst falling mode output beyond alarm interrupt enable" "0,1" bitfld.long 0x0 2. "HYST_R,hyst rising mode output beyond alarm interrupt enable" "0,1" bitfld.long 0x0 1. "HYST_LOW,hyst h/l mode output beyond alarm low interrupt enable" "0,1" bitfld.long 0x0 0. "HYST_HIGH,hyst h/l mode output beyond alarm high interrupt enable" "0,1" rgroup.long 0x20++0x3 line.long 0x0 "PVT_INT_STATUS,PVT INTERRUPT STATUS" bitfld.long 0x0 3. "HYST_F,hyst falling mode output beyond alarm interrupt status" "0,1" bitfld.long 0x0 2. "HYST_R,hyst rising mode output beyond alarm interrupt status" "0,1" bitfld.long 0x0 1. "HYST_LOW,hyst h/l mode output beyond alarm low interrupt status" "0,1" bitfld.long 0x0 0. "HYST_HIGH,hyst h/l mode output beyond alarm high interrupt status" "0,1" group.long 0x24++0x13 line.long 0x0 "PVT_INT_CLR,PVT INTERRUPT CLEAR" bitfld.long 0x0 3. "HYST_F,hyst falling mode output beyond alarm interrupt clear. this is auto clear register." "0,1" bitfld.long 0x0 2. "HYST_R,hyst rising mode output beyond alarm interrupt clear. this is auto clear register." "0,1" bitfld.long 0x0 1. "HYST_LOW,hyst h/l mode output beyond alarm low interrupt clear. this is auto clear register." "0,1" bitfld.long 0x0 0. "HYST_HIGH,hyst h/l mode output beyond alarm high interrupt clear. this is auto clear register." "0,1" line.long 0x4 "PVT_HYST_H_1,PVT ALARM HYST HIGH MODE SETTING" hexmask.long.word 0x4 10.--19. 1. "THRESH_L,alarm low setting" hexmask.long.word 0x4 0.--9. 1. "THRESH_H,alarm high setting" line.long 0x8 "PVT_HYST_L_1,PVT ALARM HYST LOW MODE SETTING" hexmask.long.word 0x8 10.--19. 1. "THRESH_L,alarm low setting" hexmask.long.word 0x8 0.--9. 1. "THRESH_H,alarm high setting" line.long 0xC "PVT_HYST_R_1,PVT ALARM HYST MODE SETTING" hexmask.long.word 0xC 10.--19. 1. "HYST,hyst setting" hexmask.long.word 0xC 0.--9. 1. "ALARM,alarm setting" line.long 0x10 "PVT_HYST_F_1,PVT ALARM HYST MODE SETTING" hexmask.long.word 0x10 10.--19. 1. "HYST,hyst setting" hexmask.long.word 0x10 0.--9. 1. "ALARM,alarm setting" rgroup.long 0x38++0x3 line.long 0x0 "PVT_HYST_TIMER_1,PVT HYST TIMER" hexmask.long.word 0x0 16.--31. 1. "F_TIMER,hyst falling time record" hexmask.long.word 0x0 0.--15. 1. "R_TIMER,hyst rising time record" group.long 0x3C++0x3 line.long 0x0 "PVT_INT_EN_1,PVT INTERRUPT ENABLE" bitfld.long 0x0 3. "HYST_F,hyst falling mode output beyond alarm interrupt enable" "0,1" bitfld.long 0x0 2. "HYST_R,hyst rising mode output beyond alarm interrupt enable" "0,1" bitfld.long 0x0 1. "HYST_LOW,hyst h/l mode output beyond alarm low interrupt enable" "0,1" bitfld.long 0x0 0. "HYST_HIGH,hyst h/l mode output beyond alarm high interrupt enable" "0,1" rgroup.long 0x40++0x3 line.long 0x0 "PVT_INT_STATUS_1,PVT INTERRUPT STATUS" bitfld.long 0x0 3. "HYST_F,hyst falling mode output beyond alarm interrupt status" "0,1" bitfld.long 0x0 2. "HYST_R,hyst rising mode output beyond alarm interrupt status" "0,1" bitfld.long 0x0 1. "HYST_LOW,hyst h/l mode output beyond alarm low interrupt status" "0,1" bitfld.long 0x0 0. "HYST_HIGH,hyst h/l mode output beyond alarm high interrupt status" "0,1" group.long 0x44++0x3 line.long 0x0 "PVT_INT_CLR_1,PVT INTERRUPT CLEAR" bitfld.long 0x0 3. "HYST_F,hyst falling mode output beyond alarm interrupt clear. this is auto clear register." "0,1" bitfld.long 0x0 2. "HYST_R,hyst rising mode output beyond alarm interrupt clear. this is auto clear register." "0,1" bitfld.long 0x0 1. "HYST_LOW,hyst h/l mode output beyond alarm low interrupt clear. this is auto clear register." "0,1" bitfld.long 0x0 0. "HYST_HIGH,hyst h/l mode output beyond alarm high interrupt clear. this is auto clear register." "0,1" tree.end tree "PVT_SNS_AP" base ad:0x30880000 group.long 0x0++0x3 line.long 0x0 "PVT_CTRL,PVT CONTROL REGISTER" bitfld.long 0x0 19. "RF_MODE_EN_1,pvt alarm rising/falling mode enable for ctrl_1 0: disable 1: enable" "disable,enable" bitfld.long 0x0 18. "HL_MODE_EN_1,pvt alarm high/low mode enable for ctrl_1 0: disable 1: enable" "disable,enable" bitfld.long 0x0 17. "RF_MODE_EN_0,pvt alarm rising/falling mode enable for ctrl_0 0: disable 1: enable" "disable,enable" bitfld.long 0x0 16. "HL_MODE_EN_0,pvt alarm high/low mode enable for ctrl_0 0: disable 1: enable" "disable,enable" newline hexmask.long.byte 0x0 10.--15. 1. "TRIMO,Trim offset bits Optional programmable inputs which may be used to improve the absolute accuracy of the temperature sensor. The optimal values may be ascertained during test or at any other time.TRIMO bits are sampled when ENA goes from 0 to.." hexmask.long.byte 0x0 5.--9. 1. "TRIMG,trim gain bits Optional programmable inputs which may be used to improve the absolute accuracy of the temperature sensor. The optimalvalues may be ascertained during test or at any other time.TRIMGbits are only to be changed while ENA=0.Default.." bitfld.long 0x0 4. "SENS_EN,software control sensor enable 0: disable 1: enable" "disable,enable" bitfld.long 0x0 2.--3. "PMODE,process detect mode" "0,1,2,3" bitfld.long 0x0 1. "VMODE,voltage detect mode" "0,1" newline bitfld.long 0x0 0. "MODE,control mode: 1: from register 0: from fuse" "from fuse,from register" rgroup.long 0x4++0x3 line.long 0x0 "PVT_DOUT,PVT DATA OUT REGISTER" hexmask.long.word 0x0 1.--10. 1. "DOUT,pvt dout value" bitfld.long 0x0 0. "VALID,pvt dout valid indicate 0: invalid 1: valid because pvt enable is triggerd one by one the design use the posedge of enable so the valid is not active all the time. debug only. no need for software" "invalid,valid" group.long 0x8++0xF line.long 0x0 "PVT_HYST_H,PVT ALARM HYST HIGH MODE SETTING" hexmask.long.word 0x0 10.--19. 1. "THRESH_L,alarm low setting" hexmask.long.word 0x0 0.--9. 1. "THRESH_H,alarm high setting" line.long 0x4 "PVT_HYST_L,PVT ALARM HYST LOW MODE SETTING" hexmask.long.word 0x4 10.--19. 1. "THRESH_L,alarm low setting" hexmask.long.word 0x4 0.--9. 1. "THRESH_H,alarm high setting" line.long 0x8 "PVT_HYST_R,PVT ALARM HYST MODE SETTING" hexmask.long.word 0x8 10.--19. 1. "HYST,hyst setting" hexmask.long.word 0x8 0.--9. 1. "ALARM,alarm setting" line.long 0xC "PVT_HYST_F,PVT ALARM HYST MODE SETTING" hexmask.long.word 0xC 10.--19. 1. "HYST,hyst setting" hexmask.long.word 0xC 0.--9. 1. "ALARM,alarm setting" rgroup.long 0x18++0x3 line.long 0x0 "PVT_HYST_TIMER,PVT HYST TIMER" hexmask.long.word 0x0 16.--31. 1. "F_TIMER,hyst falling time record" hexmask.long.word 0x0 0.--15. 1. "R_TIMER,hyst rising time record" group.long 0x1C++0x3 line.long 0x0 "PVT_INT_EN,PVT INTERRUPT ENABLE" bitfld.long 0x0 3. "HYST_F,hyst falling mode output beyond alarm interrupt enable" "0,1" bitfld.long 0x0 2. "HYST_R,hyst rising mode output beyond alarm interrupt enable" "0,1" bitfld.long 0x0 1. "HYST_LOW,hyst h/l mode output beyond alarm low interrupt enable" "0,1" bitfld.long 0x0 0. "HYST_HIGH,hyst h/l mode output beyond alarm high interrupt enable" "0,1" rgroup.long 0x20++0x3 line.long 0x0 "PVT_INT_STATUS,PVT INTERRUPT STATUS" bitfld.long 0x0 3. "HYST_F,hyst falling mode output beyond alarm interrupt status" "0,1" bitfld.long 0x0 2. "HYST_R,hyst rising mode output beyond alarm interrupt status" "0,1" bitfld.long 0x0 1. "HYST_LOW,hyst h/l mode output beyond alarm low interrupt status" "0,1" bitfld.long 0x0 0. "HYST_HIGH,hyst h/l mode output beyond alarm high interrupt status" "0,1" group.long 0x24++0x13 line.long 0x0 "PVT_INT_CLR,PVT INTERRUPT CLEAR" bitfld.long 0x0 3. "HYST_F,hyst falling mode output beyond alarm interrupt clear. this is auto clear register." "0,1" bitfld.long 0x0 2. "HYST_R,hyst rising mode output beyond alarm interrupt clear. this is auto clear register." "0,1" bitfld.long 0x0 1. "HYST_LOW,hyst h/l mode output beyond alarm low interrupt clear. this is auto clear register." "0,1" bitfld.long 0x0 0. "HYST_HIGH,hyst h/l mode output beyond alarm high interrupt clear. this is auto clear register." "0,1" line.long 0x4 "PVT_HYST_H_1,PVT ALARM HYST HIGH MODE SETTING" hexmask.long.word 0x4 10.--19. 1. "THRESH_L,alarm low setting" hexmask.long.word 0x4 0.--9. 1. "THRESH_H,alarm high setting" line.long 0x8 "PVT_HYST_L_1,PVT ALARM HYST LOW MODE SETTING" hexmask.long.word 0x8 10.--19. 1. "THRESH_L,alarm low setting" hexmask.long.word 0x8 0.--9. 1. "THRESH_H,alarm high setting" line.long 0xC "PVT_HYST_R_1,PVT ALARM HYST MODE SETTING" hexmask.long.word 0xC 10.--19. 1. "HYST,hyst setting" hexmask.long.word 0xC 0.--9. 1. "ALARM,alarm setting" line.long 0x10 "PVT_HYST_F_1,PVT ALARM HYST MODE SETTING" hexmask.long.word 0x10 10.--19. 1. "HYST,hyst setting" hexmask.long.word 0x10 0.--9. 1. "ALARM,alarm setting" rgroup.long 0x38++0x3 line.long 0x0 "PVT_HYST_TIMER_1,PVT HYST TIMER" hexmask.long.word 0x0 16.--31. 1. "F_TIMER,hyst falling time record" hexmask.long.word 0x0 0.--15. 1. "R_TIMER,hyst rising time record" group.long 0x3C++0x3 line.long 0x0 "PVT_INT_EN_1,PVT INTERRUPT ENABLE" bitfld.long 0x0 3. "HYST_F,hyst falling mode output beyond alarm interrupt enable" "0,1" bitfld.long 0x0 2. "HYST_R,hyst rising mode output beyond alarm interrupt enable" "0,1" bitfld.long 0x0 1. "HYST_LOW,hyst h/l mode output beyond alarm low interrupt enable" "0,1" bitfld.long 0x0 0. "HYST_HIGH,hyst h/l mode output beyond alarm high interrupt enable" "0,1" rgroup.long 0x40++0x3 line.long 0x0 "PVT_INT_STATUS_1,PVT INTERRUPT STATUS" bitfld.long 0x0 3. "HYST_F,hyst falling mode output beyond alarm interrupt status" "0,1" bitfld.long 0x0 2. "HYST_R,hyst rising mode output beyond alarm interrupt status" "0,1" bitfld.long 0x0 1. "HYST_LOW,hyst h/l mode output beyond alarm low interrupt status" "0,1" bitfld.long 0x0 0. "HYST_HIGH,hyst h/l mode output beyond alarm high interrupt status" "0,1" group.long 0x44++0x3 line.long 0x0 "PVT_INT_CLR_1,PVT INTERRUPT CLEAR" bitfld.long 0x0 3. "HYST_F,hyst falling mode output beyond alarm interrupt clear. this is auto clear register." "0,1" bitfld.long 0x0 2. "HYST_R,hyst rising mode output beyond alarm interrupt clear. this is auto clear register." "0,1" bitfld.long 0x0 1. "HYST_LOW,hyst h/l mode output beyond alarm low interrupt clear. this is auto clear register." "0,1" bitfld.long 0x0 0. "HYST_HIGH,hyst h/l mode output beyond alarm high interrupt clear. this is auto clear register." "0,1" tree.end endif tree.end tree "PWM (Pulse Width Modulation)" sif (CORENAME()=="CORTEXR5F") repeat 8. (increment 1. 1.) (list ad:0xF01A0000 ad:0xF01B0000 ad:0xF0910000 ad:0xF0920000 ad:0xF0930000 ad:0xF0940000 ad:0xF0950000 ad:0xF0960000) tree "PWM$1" base $2 group.long 0x0++0x17 line.long 0x0 "INT_STA,This register provides interrupt status." bitfld.long 0x0 2. "FIFO_UNDERRUN,When set indicates FIFO is underrrun in dma mode" "0,1" newline bitfld.long 0x0 1. "CNT_G0_OVF,When set indicates CNT_G0 overflow" "0,1" bitfld.long 0x0 0. "CMP_EVENT,When set indicates compare event happen" "0,1" line.long 0x4 "INT_STA_EN,This register provides enable bits for interrupt status." bitfld.long 0x4 2. "FIFO_UNDERRUN,FIFO underrun interrput status enable" "0,1" newline bitfld.long 0x4 1. "CNT_G0_OVF,CNT_G0 overflow interrupt status enable" "0,1" bitfld.long 0x4 0. "CMP_EVENT,Compare event interrupt status enable" "0,1" line.long 0x8 "INT_SIG_EN,This register provides enable bits for interrupt signal" bitfld.long 0x8 2. "FIFO_UNDERRUN,FIFO underrun interrupt signal enable" "0,1" newline bitfld.long 0x8 1. "CNT_G0_OVF,CNT_G0 overflow interrupt signal enable" "0,1" bitfld.long 0x8 0. "CMP_EVENT,Compare event interrupt signal enable" "0,1" line.long 0xC "CNT_G0_CONFIG,This register provides clock configuration for CNT_G0" hexmask.long.word 0xC 16.--31. 1. "DIV_NUM,Divider number for CNT_G0" newline bitfld.long 0xC 4. "INT_CLR,Internal timer clear." "0,1" bitfld.long 0xC 3. "EXT_CLR_EN,External clear enable" "0,1" newline bitfld.long 0xC 2. "FRC_RLD,Force reload for cnt_g0." "0,1" bitfld.long 0xC 0.--1. "SRC_CLK_SEL,Select source clock. 00: High frequency clock(hf_clk) up to 400mhz. 01: Alternative High Frequency clock(ahf_clk) up to 400mhz. 10: tie 0 11: External clock. Pls note when change src_clk_sel need make sure source and destination clock are.." "High frequency,Alternative High Frequency clock,?,?" line.long 0x10 "CLK_CONFIG,clk0 and clk1 frequency setting" hexmask.long.word 0x10 16.--31. 1. "CLK1_DIV,Divider number for CLK1" hexmask.long.word 0x10 0.--15. 1. "CLK0_DIV,Divider number for CLK0" line.long 0x14 "CNT_G0_OVF,This register is used to update overflow value for CNT_G0." hexmask.long 0x14 0.--31. 1. "VALUE,When CNT_G0 reach VALUE it will be reset to 0. After write new value new VALUE value will not be effective until one overrflow happens or FRC_RLD in CNT_G0_CONFIG register is set." rgroup.long 0x18++0x3 line.long 0x0 "CNT_G0,CNT_G0 timer counter" hexmask.long 0x0 0.--31. 1. "TIMER,CTN_G0 timer counter value" group.long 0x1C++0x2B line.long 0x0 "CMP_VAL_UPT,Indicate CPU has updated compare value. Hardware will auto update all the compare value to shadow register. Use for no-DMA mode." bitfld.long 0x0 0. "UPT,Indicate CPU has updated compare value." "0,1" line.long 0x4 "CMP0_A_VAL,This reigister provides compare 0 value for compare channel A in no-DMA mode." hexmask.long 0x4 0.--31. 1. "DATA,Compare value" line.long 0x8 "CMP1_A_VAL,This reigister provides compare 1 value for compare channel A in no-DMA mode." hexmask.long 0x8 0.--31. 1. "DATA,Compare value" line.long 0xC "CMP0_B_VAL,This reigister provides compare 0 value for compare channel B in no-DMA mode" hexmask.long 0xC 0.--31. 1. "DATA,Compare value" line.long 0x10 "CMP1_B_VAL,This reigister provides compare 1 value for compare channel B in no-DMA mode." hexmask.long 0x10 0.--31. 1. "DATA,Compare value" line.long 0x14 "CMP0_C_VAL,This reigister provides compare 0 value for compare channel C in no-DMA mode." hexmask.long 0x14 0.--31. 1. "DATA,Compare value" line.long 0x18 "CMP1_C_VAL,This reigister provides compare 1 value for compare channel C in no-DMA mode." hexmask.long 0x18 0.--31. 1. "DATA,Compare value" line.long 0x1C "CMP0_D_VAL,This reigister provides compare 0 value for compare channel D in no-DMA mode." hexmask.long 0x1C 0.--31. 1. "DATA,Compare value" line.long 0x20 "CMP1_D_VAL,This reigister provides compare 1 value for compare channel D in no-DMA mode." hexmask.long 0x20 0.--31. 1. "DATA,Compare value" line.long 0x24 "CMP_CONFIG,This register provides data configuration for compare function." hexmask.long.byte 0x24 16.--23. 1. "RPT_NUM,Repeat each group of data by a pre-programmed times." newline hexmask.long.byte 0x24 8.--13. 1. "FIFO_WML,Water mark level for FIFO. When FIFO is used for compare function dma request will be asserted if left space in FIFO is greater than or equal to FIFO_WML." newline bitfld.long 0x24 5. "DMA_EN,Dma enable" "0,1" newline bitfld.long 0x24 4. "DUAL_CMP_MODE,Compare twice for one PWM output." "0,1" bitfld.long 0x24 2.--3. "GRP_NUM,00: Only compare channel A work 01: Compare A and compare B are working together. 10/11:compare A compare B compae C and compare D work together." "Only compare channel A work,Compare A and compare B are working together,?,?" newline bitfld.long 0x24 0.--1. "DATA_FORMAT,Data bits width 00: 32 bit 01: 16 bit 10/11: 8 bit" "0,1,2,3" line.long 0x28 "FIFO_ENTRY,This register provides FIFO entry for comare function." hexmask.long 0x28 0.--31. 1. "DATA,data" rgroup.long 0x48++0x3 line.long 0x0 "FIFO_STAT,FIFO status" hexmask.long.byte 0x0 2.--8. 1. "ENTRIES,Indicates data numbers of FIFO." newline bitfld.long 0x0 1. "EMPTY,Indicates FIFO is empty" "0,1" bitfld.long 0x0 0. "FULL,Indicates FIFO D is full." "0,1" group.long 0x4C++0x2B line.long 0x0 "CMP_CTRL,This register provides compare function control" bitfld.long 0x0 31. "SW_RST,Software reset whole IP." "0,1" newline bitfld.long 0x0 1. "SINGLE_MODE,1: only generate one time compare event. Then auto clear EN bit. 0. Continously compare until SW clear EN bit." "?,only generate one time compare event" bitfld.long 0x0 0. "EN,Enable compare function.In single mode this bit will be auto cleared after compare event happens.In consecutive compare mode compare will keep working until SW clear this bit." "0,1" line.long 0x4 "CMP_A_CONFIG0,Compare A configuration register0 This register provides configuration for compare channel A." hexmask.long.byte 0x4 24.--31. 1. "CMP1_PULSE_WID,Width when output second positive or negative pulse in dual compare mode." hexmask.long.byte 0x4 16.--23. 1. "CMP0_PULSE_WID,Width when output positive or negative pulse" newline bitfld.long 0x4 3.--5. "CMP1_OUT_MODE,Second compare output mode in dual compare mode 000: Positive pulse. 001: Negative pulse 010: Signal toggle. 011: Level high. 100: Level low. Other value: keep" "Positive pulse,Negative pulse,?,?,?,?,?,?" newline bitfld.long 0x4 0.--2. "CMP0_OUT_MODE,Compare output mode. 000: Positive pulse. 001: Negative pulse 010: Signal toggle. 011: Level high. 100: Level low. Other value: keep" "Positive pulse,Negative pulse,?,?,?,?,?,?" line.long 0x8 "CMP_A_CONFIG1,Compare A configuration register1. This register provides configuration or compare channel A." hexmask.long.byte 0x8 16.--23. 1. "OVF_PULSE_WID,Width when output positive or negative pulse for overflow event." newline bitfld.long 0x8 5. "FRC_LOW,Force compare out to low." "0,1" newline bitfld.long 0x8 4. "FRC_HIGH,Force compare out to high." "0,1" newline bitfld.long 0x8 0.--2. "OVF_OUT_MODE,Output mode for overflow event. 000: Positive pulse. 001: Negative pulse 010: Signal toggle. 011: Level high. 100: Level low. Other value: keep" "Positive pulse,Negative pulse,?,?,?,?,?,?" line.long 0xC "CMP_B_CONFIG0,Compare B configuration register0 This register provides configuration for compare channel B." hexmask.long.byte 0xC 24.--31. 1. "CMP1_PULSE_WID,Width when output second positive or negative pulse in dual compare mode." hexmask.long.byte 0xC 16.--23. 1. "CMP0_PULSE_WID,Width when output positive or negative pulse" newline bitfld.long 0xC 3.--5. "CMP1_OUT_MODE,Second compare output mode in dual compare mode 000: Positive pulse. 001: Negative pulse 010: Signal toggle. 011: Level high. 100: Level low. Other value: keep" "Positive pulse,Negative pulse,?,?,?,?,?,?" newline bitfld.long 0xC 0.--2. "CMP0_OUT_MODE,Compare output mode. 000: Positive pulse. 001: Negative pulse 010: Signal toggle. 011: Level high. 100: Level low. Other value: keep" "Positive pulse,Negative pulse,?,?,?,?,?,?" line.long 0x10 "CMP_B_CONFIG1,Compare B configuration register1. This register provides configuration or compare channel B." hexmask.long.byte 0x10 16.--23. 1. "OVF_PULSE_WID,Width when output positive or negative pulse for overflow event." newline bitfld.long 0x10 5. "FRC_LOW,Force compare out to low." "0,1" newline bitfld.long 0x10 4. "FRC_HIGH,Force compare out to high." "0,1" newline bitfld.long 0x10 0.--2. "OVF_OUT_MODE,Output mode for overflow event. 000: Positive pulse. 001: Negative pulse 010: Signal toggle. 011: Level high. 100: Level low. Other value: keep" "Positive pulse,Negative pulse,?,?,?,?,?,?" line.long 0x14 "CMP_C_CONFIG0,Compare C configuration register0. This register provides configuration or compare channel C." hexmask.long.byte 0x14 24.--31. 1. "CMP1_PULSE_WID,Width when output second positive or negative pulse in dual compare mode." hexmask.long.byte 0x14 16.--23. 1. "CMP0_PULSE_WID,Width when output positive or negative pulse" newline bitfld.long 0x14 3.--5. "CMP1_OUT_MODE,Second compare output mode in dual compare mode 000: Positive pulse. 001: Negative pulse 010: Signal toggle. 011: Level high. 100: Level low. Other value: keep" "Positive pulse,Negative pulse,?,?,?,?,?,?" newline bitfld.long 0x14 0.--2. "CMP0_OUT_MODE,Compare output mode. 000: Positive pulse. 001: Negative pulse 010: Signal toggle. 011: Level high. 100: Level low. Other value: keep" "Positive pulse,Negative pulse,?,?,?,?,?,?" line.long 0x18 "CMP_C_CONFIG1,Compare C configuration register1. This register provides configuration or compare channel C." hexmask.long.byte 0x18 16.--23. 1. "OVF_PULSE_WID,Width when output positive or negative pulse for overflow event." newline bitfld.long 0x18 5. "FRC_LOW,Force compare out to low." "0,1" newline bitfld.long 0x18 4. "FRC_HIGH,Force compare out to high." "0,1" newline bitfld.long 0x18 0.--2. "OVF_OUT_MODE,Output mode for overflow event. 000: Positive pulse. 001: Negative pulse 010: Signal toggle. 011: Level high. 100: Level low. Other value: keep" "Positive pulse,Negative pulse,?,?,?,?,?,?" line.long 0x1C "CMP_D_CONFIG0,Compare D configuration register0. This register provides configuration or compare channel D." hexmask.long.byte 0x1C 24.--31. 1. "CMP1_PULSE_WID,Width when output second positive or negative pulse in dual compare mode." hexmask.long.byte 0x1C 16.--23. 1. "CMP0_PULSE_WID,Width when output positive or negative pulse" newline bitfld.long 0x1C 3.--5. "CMP1_OUT_MODE,Second compare output mode in dual compare mode 000: Positive pulse. 001: Negative pulse 010: Signal toggle. 011: Level high. 100: Level low. Other value: keep" "Positive pulse,Negative pulse,?,?,?,?,?,?" newline bitfld.long 0x1C 0.--2. "CMP0_OUT_MODE,Compare output mode. 000: Positive pulse. 001: Negative pulse 010: Signal toggle. 011: Level high. 100: Level low. Other value: keep" "Positive pulse,Negative pulse,?,?,?,?,?,?" line.long 0x20 "CMP_D_CONFIG1,Compare D configuration register1. This register provides configuration or compare channel D." hexmask.long.byte 0x20 16.--23. 1. "OVF_PULSE_WID,Width when output positive or negative pulse for overflow event." newline bitfld.long 0x20 5. "FRC_LOW,Force compare out to low." "0,1" newline bitfld.long 0x20 4. "FRC_HIGH,Force compare out to high." "0,1" newline bitfld.long 0x20 0.--2. "OVF_OUT_MODE,Output mode for overflow event. 000: Positive pulse. 001: Negative pulse 010: Signal toggle. 011: Level high. 100: Level low. Other value: keep" "Positive pulse,Negative pulse,?,?,?,?,?,?" line.long 0x24 "DITHER_CTRL,Dither control register. This register provides dither function setting" hexmask.long.word 0x24 16.--31. 1. "INIT_OFFSET,Init offset for carry bit generation of quantization error" newline hexmask.long.byte 0x24 8.--11. 1. "CLIP_RSLT,Dither clipped LSB data bit width. 0~15 means 1~16 bit" hexmask.long.byte 0x24 4.--7. 1. "DROP,Directly dropped LSB data bit width. 0 means no drop." newline bitfld.long 0x24 2.--3. "IN_RSLT,Dither input data width. 00: 8 bit 01: 16 bit 10: 24 bit 11: 32 bit" "0,1,2,3" bitfld.long 0x24 1. "INIT_OFFSET_EN,When Quantizaion error reach INIT_OFFSET generate carry bit for clipped data." "0,1" newline bitfld.long 0x24 0. "DITHER_EN,Enable dither function." "0,1" line.long 0x28 "MFC_CTRL,It is used for modulation frequency and preserving PWM accracy." hexmask.long.byte 0x28 0.--3. 1. "MFC_UP,Increasing modulation frequency up to 2^N times where N ranged in between [0 10]. 0 means MFC disable." group.long 0x80++0x13 line.long 0x0 "SSE_CTRL,This register controls signal synthsis engine function." hexmask.long.byte 0x0 22.--27. 1. "SSE_SEL_D,Select 4 signals from CMP_A CMP_B CMP_C PWM_DIV_CLK CLK0 and CLK1 for compare channle D signal systhesis" newline hexmask.long.byte 0x0 16.--21. 1. "SSE_SEL_C,Select 4 signals from CMP_A CMP_B CMP_D PWM_DIV_CLK CLK0 and CLK1 for compare channle C signal systhesis" hexmask.long.byte 0x0 10.--15. 1. "SSE_SEL_B,Select 4 signals from CMP_A CMP_C CMP_D PWM_DIV_CLK CLK0 and CLK1 for compare channle B signal systhesis" newline hexmask.long.byte 0x0 4.--9. 1. "SSE_SEL_A,Select 4 signals from CMP_B CMP_C CMP_D PWM_DIV_CLK CLK0 and CLK1 for compare channle A signal systhesis." bitfld.long 0x0 3. "SSE_EN_D,Synthesis CMP_D and other 4 signals into one signal for compare channel D" "0,1" newline bitfld.long 0x0 2. "SSE_EN_C,Synthesis CMP_C and other 4 signals into one signal for compare channel C" "0,1" bitfld.long 0x0 1. "SSE_EN_B,Synthesis CMP_B and other 4 signals into one signal for compare channel B" "0,1" newline bitfld.long 0x0 0. "SSE_EN_A,Synthesis CMP_A and other 4 signals into one signal for compare channel A" "0,1" line.long 0x4 "SSE_A,Signal synthesis for COMPARE A output" hexmask.long 0x4 0.--31. 1. "SSE,Signal synthesis to drive one logic output from 5 logical inputs." line.long 0x8 "SSE_B,Signal synthesis for COMPARE B output" hexmask.long 0x8 0.--31. 1. "SSE,Signal synthesis to drive one logic output from 5 logical inputs." line.long 0xC "SSE_C,Signal synthesis for COMPARE C output" hexmask.long 0xC 0.--31. 1. "SSE,Signal synthesis to drive one logic output from 5 logical inputs." line.long 0x10 "SSE_D,Signal synthesis for COMPARE D output" hexmask.long 0x10 0.--31. 1. "SSE,Signal synthesis to drive one logic output from 5 logical inputs." tree.end repeat.end elif (CORENAME()=="CORTEXA55") repeat 8. (increment 1. 1.) (list ad:0x301A0000 ad:0x301B0000 ad:0x30910000 ad:0x30920000 ad:0x30930000 ad:0x30940000 ad:0x30950000 ad:0x30960000) tree "PWM$1" base $2 group.long 0x0++0x17 line.long 0x0 "INT_STA,This register provides interrupt status." bitfld.long 0x0 2. "FIFO_UNDERRUN,When set indicates FIFO is underrrun in dma mode" "0,1" newline bitfld.long 0x0 1. "CNT_G0_OVF,When set indicates CNT_G0 overflow" "0,1" bitfld.long 0x0 0. "CMP_EVENT,When set indicates compare event happen" "0,1" line.long 0x4 "INT_STA_EN,This register provides enable bits for interrupt status." bitfld.long 0x4 2. "FIFO_UNDERRUN,FIFO underrun interrput status enable" "0,1" newline bitfld.long 0x4 1. "CNT_G0_OVF,CNT_G0 overflow interrupt status enable" "0,1" bitfld.long 0x4 0. "CMP_EVENT,Compare event interrupt status enable" "0,1" line.long 0x8 "INT_SIG_EN,This register provides enable bits for interrupt signal" bitfld.long 0x8 2. "FIFO_UNDERRUN,FIFO underrun interrupt signal enable" "0,1" newline bitfld.long 0x8 1. "CNT_G0_OVF,CNT_G0 overflow interrupt signal enable" "0,1" bitfld.long 0x8 0. "CMP_EVENT,Compare event interrupt signal enable" "0,1" line.long 0xC "CNT_G0_CONFIG,This register provides clock configuration for CNT_G0" hexmask.long.word 0xC 16.--31. 1. "DIV_NUM,Divider number for CNT_G0" newline bitfld.long 0xC 4. "INT_CLR,Internal timer clear." "0,1" bitfld.long 0xC 3. "EXT_CLR_EN,External clear enable" "0,1" newline bitfld.long 0xC 2. "FRC_RLD,Force reload for cnt_g0." "0,1" bitfld.long 0xC 0.--1. "SRC_CLK_SEL,Select source clock. 00: High frequency clock(hf_clk) up to 400mhz. 01: Alternative High Frequency clock(ahf_clk) up to 400mhz. 10: tie 0 11: External clock. Pls note when change src_clk_sel need make sure source and destination clock are.." "High frequency,Alternative High Frequency clock,?,?" line.long 0x10 "CLK_CONFIG,clk0 and clk1 frequency setting" hexmask.long.word 0x10 16.--31. 1. "CLK1_DIV,Divider number for CLK1" hexmask.long.word 0x10 0.--15. 1. "CLK0_DIV,Divider number for CLK0" line.long 0x14 "CNT_G0_OVF,This register is used to update overflow value for CNT_G0." hexmask.long 0x14 0.--31. 1. "VALUE,When CNT_G0 reach VALUE it will be reset to 0. After write new value new VALUE value will not be effective until one overrflow happens or FRC_RLD in CNT_G0_CONFIG register is set." rgroup.long 0x18++0x3 line.long 0x0 "CNT_G0,CNT_G0 timer counter" hexmask.long 0x0 0.--31. 1. "TIMER,CTN_G0 timer counter value" group.long 0x1C++0x2B line.long 0x0 "CMP_VAL_UPT,Indicate CPU has updated compare value. Hardware will auto update all the compare value to shadow register. Use for no-DMA mode." bitfld.long 0x0 0. "UPT,Indicate CPU has updated compare value." "0,1" line.long 0x4 "CMP0_A_VAL,This reigister provides compare 0 value for compare channel A in no-DMA mode." hexmask.long 0x4 0.--31. 1. "DATA,Compare value" line.long 0x8 "CMP1_A_VAL,This reigister provides compare 1 value for compare channel A in no-DMA mode." hexmask.long 0x8 0.--31. 1. "DATA,Compare value" line.long 0xC "CMP0_B_VAL,This reigister provides compare 0 value for compare channel B in no-DMA mode" hexmask.long 0xC 0.--31. 1. "DATA,Compare value" line.long 0x10 "CMP1_B_VAL,This reigister provides compare 1 value for compare channel B in no-DMA mode." hexmask.long 0x10 0.--31. 1. "DATA,Compare value" line.long 0x14 "CMP0_C_VAL,This reigister provides compare 0 value for compare channel C in no-DMA mode." hexmask.long 0x14 0.--31. 1. "DATA,Compare value" line.long 0x18 "CMP1_C_VAL,This reigister provides compare 1 value for compare channel C in no-DMA mode." hexmask.long 0x18 0.--31. 1. "DATA,Compare value" line.long 0x1C "CMP0_D_VAL,This reigister provides compare 0 value for compare channel D in no-DMA mode." hexmask.long 0x1C 0.--31. 1. "DATA,Compare value" line.long 0x20 "CMP1_D_VAL,This reigister provides compare 1 value for compare channel D in no-DMA mode." hexmask.long 0x20 0.--31. 1. "DATA,Compare value" line.long 0x24 "CMP_CONFIG,This register provides data configuration for compare function." hexmask.long.byte 0x24 16.--23. 1. "RPT_NUM,Repeat each group of data by a pre-programmed times." newline hexmask.long.byte 0x24 8.--13. 1. "FIFO_WML,Water mark level for FIFO. When FIFO is used for compare function dma request will be asserted if left space in FIFO is greater than or equal to FIFO_WML." newline bitfld.long 0x24 5. "DMA_EN,Dma enable" "0,1" newline bitfld.long 0x24 4. "DUAL_CMP_MODE,Compare twice for one PWM output." "0,1" bitfld.long 0x24 2.--3. "GRP_NUM,00: Only compare channel A work 01: Compare A and compare B are working together. 10/11:compare A compare B compae C and compare D work together." "Only compare channel A work,Compare A and compare B are working together,?,?" newline bitfld.long 0x24 0.--1. "DATA_FORMAT,Data bits width 00: 32 bit 01: 16 bit 10/11: 8 bit" "0,1,2,3" line.long 0x28 "FIFO_ENTRY,This register provides FIFO entry for comare function." hexmask.long 0x28 0.--31. 1. "DATA,data" rgroup.long 0x48++0x3 line.long 0x0 "FIFO_STAT,FIFO status" hexmask.long.byte 0x0 2.--8. 1. "ENTRIES,Indicates data numbers of FIFO." newline bitfld.long 0x0 1. "EMPTY,Indicates FIFO is empty" "0,1" bitfld.long 0x0 0. "FULL,Indicates FIFO D is full." "0,1" group.long 0x4C++0x2B line.long 0x0 "CMP_CTRL,This register provides compare function control" bitfld.long 0x0 31. "SW_RST,Software reset whole IP." "0,1" newline bitfld.long 0x0 1. "SINGLE_MODE,1: only generate one time compare event. Then auto clear EN bit. 0. Continously compare until SW clear EN bit." "?,only generate one time compare event" bitfld.long 0x0 0. "EN,Enable compare function.In single mode this bit will be auto cleared after compare event happens.In consecutive compare mode compare will keep working until SW clear this bit." "0,1" line.long 0x4 "CMP_A_CONFIG0,Compare A configuration register0 This register provides configuration for compare channel A." hexmask.long.byte 0x4 24.--31. 1. "CMP1_PULSE_WID,Width when output second positive or negative pulse in dual compare mode." hexmask.long.byte 0x4 16.--23. 1. "CMP0_PULSE_WID,Width when output positive or negative pulse" newline bitfld.long 0x4 3.--5. "CMP1_OUT_MODE,Second compare output mode in dual compare mode 000: Positive pulse. 001: Negative pulse 010: Signal toggle. 011: Level high. 100: Level low. Other value: keep" "Positive pulse,Negative pulse,?,?,?,?,?,?" newline bitfld.long 0x4 0.--2. "CMP0_OUT_MODE,Compare output mode. 000: Positive pulse. 001: Negative pulse 010: Signal toggle. 011: Level high. 100: Level low. Other value: keep" "Positive pulse,Negative pulse,?,?,?,?,?,?" line.long 0x8 "CMP_A_CONFIG1,Compare A configuration register1. This register provides configuration or compare channel A." hexmask.long.byte 0x8 16.--23. 1. "OVF_PULSE_WID,Width when output positive or negative pulse for overflow event." newline bitfld.long 0x8 5. "FRC_LOW,Force compare out to low." "0,1" newline bitfld.long 0x8 4. "FRC_HIGH,Force compare out to high." "0,1" newline bitfld.long 0x8 0.--2. "OVF_OUT_MODE,Output mode for overflow event. 000: Positive pulse. 001: Negative pulse 010: Signal toggle. 011: Level high. 100: Level low. Other value: keep" "Positive pulse,Negative pulse,?,?,?,?,?,?" line.long 0xC "CMP_B_CONFIG0,Compare B configuration register0 This register provides configuration for compare channel B." hexmask.long.byte 0xC 24.--31. 1. "CMP1_PULSE_WID,Width when output second positive or negative pulse in dual compare mode." hexmask.long.byte 0xC 16.--23. 1. "CMP0_PULSE_WID,Width when output positive or negative pulse" newline bitfld.long 0xC 3.--5. "CMP1_OUT_MODE,Second compare output mode in dual compare mode 000: Positive pulse. 001: Negative pulse 010: Signal toggle. 011: Level high. 100: Level low. Other value: keep" "Positive pulse,Negative pulse,?,?,?,?,?,?" newline bitfld.long 0xC 0.--2. "CMP0_OUT_MODE,Compare output mode. 000: Positive pulse. 001: Negative pulse 010: Signal toggle. 011: Level high. 100: Level low. Other value: keep" "Positive pulse,Negative pulse,?,?,?,?,?,?" line.long 0x10 "CMP_B_CONFIG1,Compare B configuration register1. This register provides configuration or compare channel B." hexmask.long.byte 0x10 16.--23. 1. "OVF_PULSE_WID,Width when output positive or negative pulse for overflow event." newline bitfld.long 0x10 5. "FRC_LOW,Force compare out to low." "0,1" newline bitfld.long 0x10 4. "FRC_HIGH,Force compare out to high." "0,1" newline bitfld.long 0x10 0.--2. "OVF_OUT_MODE,Output mode for overflow event. 000: Positive pulse. 001: Negative pulse 010: Signal toggle. 011: Level high. 100: Level low. Other value: keep" "Positive pulse,Negative pulse,?,?,?,?,?,?" line.long 0x14 "CMP_C_CONFIG0,Compare C configuration register0. This register provides configuration or compare channel C." hexmask.long.byte 0x14 24.--31. 1. "CMP1_PULSE_WID,Width when output second positive or negative pulse in dual compare mode." hexmask.long.byte 0x14 16.--23. 1. "CMP0_PULSE_WID,Width when output positive or negative pulse" newline bitfld.long 0x14 3.--5. "CMP1_OUT_MODE,Second compare output mode in dual compare mode 000: Positive pulse. 001: Negative pulse 010: Signal toggle. 011: Level high. 100: Level low. Other value: keep" "Positive pulse,Negative pulse,?,?,?,?,?,?" newline bitfld.long 0x14 0.--2. "CMP0_OUT_MODE,Compare output mode. 000: Positive pulse. 001: Negative pulse 010: Signal toggle. 011: Level high. 100: Level low. Other value: keep" "Positive pulse,Negative pulse,?,?,?,?,?,?" line.long 0x18 "CMP_C_CONFIG1,Compare C configuration register1. This register provides configuration or compare channel C." hexmask.long.byte 0x18 16.--23. 1. "OVF_PULSE_WID,Width when output positive or negative pulse for overflow event." newline bitfld.long 0x18 5. "FRC_LOW,Force compare out to low." "0,1" newline bitfld.long 0x18 4. "FRC_HIGH,Force compare out to high." "0,1" newline bitfld.long 0x18 0.--2. "OVF_OUT_MODE,Output mode for overflow event. 000: Positive pulse. 001: Negative pulse 010: Signal toggle. 011: Level high. 100: Level low. Other value: keep" "Positive pulse,Negative pulse,?,?,?,?,?,?" line.long 0x1C "CMP_D_CONFIG0,Compare D configuration register0. This register provides configuration or compare channel D." hexmask.long.byte 0x1C 24.--31. 1. "CMP1_PULSE_WID,Width when output second positive or negative pulse in dual compare mode." hexmask.long.byte 0x1C 16.--23. 1. "CMP0_PULSE_WID,Width when output positive or negative pulse" newline bitfld.long 0x1C 3.--5. "CMP1_OUT_MODE,Second compare output mode in dual compare mode 000: Positive pulse. 001: Negative pulse 010: Signal toggle. 011: Level high. 100: Level low. Other value: keep" "Positive pulse,Negative pulse,?,?,?,?,?,?" newline bitfld.long 0x1C 0.--2. "CMP0_OUT_MODE,Compare output mode. 000: Positive pulse. 001: Negative pulse 010: Signal toggle. 011: Level high. 100: Level low. Other value: keep" "Positive pulse,Negative pulse,?,?,?,?,?,?" line.long 0x20 "CMP_D_CONFIG1,Compare D configuration register1. This register provides configuration or compare channel D." hexmask.long.byte 0x20 16.--23. 1. "OVF_PULSE_WID,Width when output positive or negative pulse for overflow event." newline bitfld.long 0x20 5. "FRC_LOW,Force compare out to low." "0,1" newline bitfld.long 0x20 4. "FRC_HIGH,Force compare out to high." "0,1" newline bitfld.long 0x20 0.--2. "OVF_OUT_MODE,Output mode for overflow event. 000: Positive pulse. 001: Negative pulse 010: Signal toggle. 011: Level high. 100: Level low. Other value: keep" "Positive pulse,Negative pulse,?,?,?,?,?,?" line.long 0x24 "DITHER_CTRL,Dither control register. This register provides dither function setting" hexmask.long.word 0x24 16.--31. 1. "INIT_OFFSET,Init offset for carry bit generation of quantization error" newline hexmask.long.byte 0x24 8.--11. 1. "CLIP_RSLT,Dither clipped LSB data bit width. 0~15 means 1~16 bit" hexmask.long.byte 0x24 4.--7. 1. "DROP,Directly dropped LSB data bit width. 0 means no drop." newline bitfld.long 0x24 2.--3. "IN_RSLT,Dither input data width. 00: 8 bit 01: 16 bit 10: 24 bit 11: 32 bit" "0,1,2,3" bitfld.long 0x24 1. "INIT_OFFSET_EN,When Quantizaion error reach INIT_OFFSET generate carry bit for clipped data." "0,1" newline bitfld.long 0x24 0. "DITHER_EN,Enable dither function." "0,1" line.long 0x28 "MFC_CTRL,It is used for modulation frequency and preserving PWM accracy." hexmask.long.byte 0x28 0.--3. 1. "MFC_UP,Increasing modulation frequency up to 2^N times where N ranged in between [0 10]. 0 means MFC disable." group.long 0x80++0x13 line.long 0x0 "SSE_CTRL,This register controls signal synthsis engine function." hexmask.long.byte 0x0 22.--27. 1. "SSE_SEL_D,Select 4 signals from CMP_A CMP_B CMP_C PWM_DIV_CLK CLK0 and CLK1 for compare channle D signal systhesis" newline hexmask.long.byte 0x0 16.--21. 1. "SSE_SEL_C,Select 4 signals from CMP_A CMP_B CMP_D PWM_DIV_CLK CLK0 and CLK1 for compare channle C signal systhesis" hexmask.long.byte 0x0 10.--15. 1. "SSE_SEL_B,Select 4 signals from CMP_A CMP_C CMP_D PWM_DIV_CLK CLK0 and CLK1 for compare channle B signal systhesis" newline hexmask.long.byte 0x0 4.--9. 1. "SSE_SEL_A,Select 4 signals from CMP_B CMP_C CMP_D PWM_DIV_CLK CLK0 and CLK1 for compare channle A signal systhesis." bitfld.long 0x0 3. "SSE_EN_D,Synthesis CMP_D and other 4 signals into one signal for compare channel D" "0,1" newline bitfld.long 0x0 2. "SSE_EN_C,Synthesis CMP_C and other 4 signals into one signal for compare channel C" "0,1" bitfld.long 0x0 1. "SSE_EN_B,Synthesis CMP_B and other 4 signals into one signal for compare channel B" "0,1" newline bitfld.long 0x0 0. "SSE_EN_A,Synthesis CMP_A and other 4 signals into one signal for compare channel A" "0,1" line.long 0x4 "SSE_A,Signal synthesis for COMPARE A output" hexmask.long 0x4 0.--31. 1. "SSE,Signal synthesis to drive one logic output from 5 logical inputs." line.long 0x8 "SSE_B,Signal synthesis for COMPARE B output" hexmask.long 0x8 0.--31. 1. "SSE,Signal synthesis to drive one logic output from 5 logical inputs." line.long 0xC "SSE_C,Signal synthesis for COMPARE C output" hexmask.long 0xC 0.--31. 1. "SSE,Signal synthesis to drive one logic output from 5 logical inputs." line.long 0x10 "SSE_D,Signal synthesis for COMPARE D output" hexmask.long 0x10 0.--31. 1. "SSE,Signal synthesis to drive one logic output from 5 logical inputs." tree.end repeat.end endif tree.end tree "ROMC (ROM Controller)" sif (CORENAME()=="CORTEXR5F") tree "ROMC_SAFETY" base ad:0xF0200000 group.long 0x0++0x23 line.long 0x0 "MEM_ERR_INT_STATUS,Memory ECC error Interrupt status" bitfld.long 0x0 2. "RDATA_FATAL,It can report ECC correction logic error and protect rdata internal path." "0,1" bitfld.long 0x0 1. "MUL_ERR,Indicate double bit errors are detected." "0,1" bitfld.long 0x0 0. "SIG_ERR,Indicate single bit error is detected." "0,1" line.long 0x4 "MEM_ERR_INT_STA_EN,Memory ECC error Interrupt status enable" bitfld.long 0x4 2. "RDATA_FATAL_EN,Rdata fatal interrupt status enable" "0,1" bitfld.long 0x4 1. "MUL_ERR_EN,Multiple bit error interrupt status enable." "0,1" bitfld.long 0x4 0. "SIG_ERR_EN,Single bit error interrupt status enable." "0,1" line.long 0x8 "MEM_ERR_INT_SIG_EN,Memory ECC Interrupt signal enable" bitfld.long 0x8 2. "RDATA_FATAL_EN,Rdata fatal interrupt signal enable." "0,1" bitfld.long 0x8 1. "MUL_ERR_EN,Multiple bits errors interrupt signal enable." "0,1" bitfld.long 0x8 0. "SIG_ERR_EN,Single bit error interrupt signal enable." "0,1" line.long 0xC "UNCERR_INT_STA,AXI bus uncorrectable error interrupt status" bitfld.long 0xC 20. "RREADY,Uncorrectable error for RREADY" "0,1" bitfld.long 0xC 5. "ARVALID,Uncorrectable error for ARVALID" "0,1" newline bitfld.long 0xC 3. "ARCTL1,Uncorrectable error for ARCTL1(ARLOCK ARBURST ARSIZE ARLEN)" "0,1" bitfld.long 0xC 1. "ARADDR,Uncorrectable error for ARADDR" "0,1" bitfld.long 0xC 0. "ARID,Uncorrectable error for ARID" "0,1" line.long 0x10 "UNCERR_INT_STA_EN,AXI bus uncorrectable error interrupt status enable" bitfld.long 0x10 20. "RREADY,Statusl enable for RREADY" "0,1" bitfld.long 0x10 5. "ARVALID,Status enable for ARVALID" "0,1" newline bitfld.long 0x10 3. "ARCTL1,Status enable for ARCTL1(ARLOCK ARBURST ARSIZE ARLEN)" "0,1" bitfld.long 0x10 1. "ARADDR,Status enable for ARADDR" "0,1" bitfld.long 0x10 0. "ARID,Status enable for ARID" "0,1" line.long 0x14 "UNCERR_INT_SIG_EN,AXI bus uncorrectable error interrupt signal enable" bitfld.long 0x14 20. "RREADY,Signal enable for RREADY" "0,1" bitfld.long 0x14 5. "ARVALID,Signal enable for ARVALID" "0,1" newline bitfld.long 0x14 3. "ARCTL1,Signal enable for ARCTL1(ARLOCK ARBURST ARSIZE ARLEN)" "0,1" bitfld.long 0x14 1. "ARADDR,Signal enable for ARADDR" "0,1" bitfld.long 0x14 0. "ARID,Signal enable for ARID" "0,1" line.long 0x18 "CORERR_INT_STA,AXI bus correctable error interrupt status" bitfld.long 0x18 0. "ARADDR,Correctable error for ARADDR" "0,1" line.long 0x1C "CORERR_INT_STA_EN,AXI bus correctable error interrupt status enable" bitfld.long 0x1C 0. "ARADDR,Status enable for ARADDR" "0,1" line.long 0x20 "CORERR_INT_SIG_EN,AXI bus correctable error interrupt signal enable" bitfld.long 0x20 0. "ARADDR,Signal enable for ARADDR" "0,1" group.long 0x30++0x7 line.long 0x0 "FWEN,Firewall enable" bitfld.long 0x0 31. "LOCK,Lock FWEM register bit and itself" "0,1" bitfld.long 0x0 0. "FWEN,Firewall enable. Enable master ID check for all the apb access." "0,1" line.long 0x4 "STICKY_REG,Sticky register" bitfld.long 0x4 31. "LOCK_15,Lock lower register bit and itself" "0,1" bitfld.long 0x4 30. "LOCK_14,Lock lower register bit and itself" "0,1" bitfld.long 0x4 29. "LOCK_13,Lock lower register bit and itself" "0,1" bitfld.long 0x4 28. "LOCK_12,Lock lower register bit and itself" "0,1" bitfld.long 0x4 27. "LOCK_11,Lock lower register bit and itself" "0,1" newline bitfld.long 0x4 26. "LOCK_10,Lock lower register bit and itself" "0,1" bitfld.long 0x4 25. "LOCK_9,Lock lower register bit and itself" "0,1" bitfld.long 0x4 24. "LOCK_8,Lock lower register bit and itself" "0,1" bitfld.long 0x4 23. "LOCK_7,Lock lower register bit and itself" "0,1" bitfld.long 0x4 22. "LOCK_6,Lock lower register bit and itself" "0,1" newline bitfld.long 0x4 21. "LOCK_5,Lock lower register bit and itself" "0,1" bitfld.long 0x4 20. "LOCK_4,Lock lower register bit and itself" "0,1" bitfld.long 0x4 19. "LOCK_3,Lock lower register bit and itself" "0,1" bitfld.long 0x4 18. "LOCK_2,Lock lower register bit and itself" "0,1" bitfld.long 0x4 17. "LOCK_1,Lock lower register bit and itself" "0,1" newline bitfld.long 0x4 16. "LOCK_0,Lock lower register bit and itself" "0,1" bitfld.long 0x4 15. "REG_15,Register" "0,1" bitfld.long 0x4 14. "REG_14,Register" "0,1" bitfld.long 0x4 13. "REG_13,Register" "0,1" bitfld.long 0x4 12. "REG_12,Register" "0,1" newline bitfld.long 0x4 11. "REG_11,Register" "0,1" bitfld.long 0x4 10. "REG_10,Register" "0,1" bitfld.long 0x4 9. "REG_9,Register" "0,1" bitfld.long 0x4 8. "REG_8,Register" "0,1" bitfld.long 0x4 7. "REG_7,Register" "0,1" newline bitfld.long 0x4 6. "REG_6,Register" "0,1" bitfld.long 0x4 5. "REG_5,Register" "0,1" bitfld.long 0x4 4. "REG_4,Register" "0,1" bitfld.long 0x4 3. "REG_3,Register" "0,1" bitfld.long 0x4 2. "REG_2,Register" "0,1" newline bitfld.long 0x4 1. "REG_1,Register" "0,1" bitfld.long 0x4 0. "REG_0,Register" "0,1" rgroup.long 0x40++0x27 line.long 0x0 "SIG_ERR_ADDR,Store access address for first single bit error." hexmask.long 0x0 0.--31. 1. "ADDR,Error addr" line.long 0x4 "SIG_ERR_DATA_31_0,Store Error data for first single bit error" hexmask.long 0x4 0.--31. 1. "DATA,Error data" line.long 0x8 "SIG_ERR_DATA_63_32,Store Error data for first single bit error" hexmask.long 0x8 0.--31. 1. "DATA,Error data" line.long 0xC "SIG_ERR_DATA_95_64,Store Error data for first single bit error" hexmask.long 0xC 0.--31. 1. "DATA,Error data" line.long 0x10 "SIG_ERR_DATA_127_96,Store Error data for first single bit error" hexmask.long 0x10 0.--31. 1. "DATA,Error data" line.long 0x14 "MUL_ERR_ADDR,Store access address for multiple bits error." hexmask.long 0x14 0.--31. 1. "ADDR,Error address" line.long 0x18 "MUL_ERR_DATA_31_0,Store Error data for first multiple bits error" hexmask.long 0x18 0.--31. 1. "DATA,Error data" line.long 0x1C "MUL_ERR_DATA_63_32,Store Error data for first multiple bits error" hexmask.long 0x1C 0.--31. 1. "DATA,Error data" line.long 0x20 "MUL_ERR_DATA_95_64,Store Error data for first multiple bits error" hexmask.long 0x20 0.--31. 1. "DATA,Error data" line.long 0x24 "MUL_ERR_DATA_127_96,Store Error data for first multiple bits error" hexmask.long 0x24 0.--31. 1. "DATA,Error data" group.long 0x80++0x3 line.long 0x0 "ROM_DIS,ROM code disable" bitfld.long 0x0 0. "DIS,When this bit is set ROM code read and ROM fix register access are disable. Once this bit is set it is always set unless POR reset." "0,1" group.long 0x100++0x13 line.long 0x0 "RDATA_31_0_INJ,Error injection on rdata" hexmask.long 0x0 0.--31. 1. "RDATA_INJ,Error injection on rdata" line.long 0x4 "RDATA_63_32_INJ,Error injection on rdata" hexmask.long 0x4 0.--31. 1. "RDATA_INJ,Error injection on rdata" line.long 0x8 "RDATA_95_64_INJ,Error injection on rdata" hexmask.long 0x8 0.--31. 1. "RDATA_INJ,Error injection on rdata" line.long 0xC "RDATA_127_96_INJ,Error injection on rdata" hexmask.long 0xC 0.--31. 1. "RDATA_INJ,Error injection on rdata" line.long 0x10 "ECC_INJ,Error injection on read ecc code" hexmask.long.byte 0x10 8.--15. 1. "ECC_INJ1,Error injection on 8 ecc code for high 64 bits wdata" hexmask.long.byte 0x10 0.--7. 1. "ECC_INJ0,Error injection on 8 ecc code for low 64 bits wdata" group.long 0x120++0x13 line.long 0x0 "RD_DATA_31_0_INJ,Error injection on rdata after ECC correction" hexmask.long 0x0 0.--31. 1. "RDATA_INJ,Error injection on rdata" line.long 0x4 "RD_DATA_63_32_INJ,Error injection on rdata after ECC correction" hexmask.long 0x4 0.--31. 1. "RDATA_INJ,Error injection on rdata" line.long 0x8 "RD_DATA_95_64_INJ,Error injection on rdata after ECC correction" hexmask.long 0x8 0.--31. 1. "RDATA_INJ,Error injection on rdata" line.long 0xC "RD_DATA_127_96_INJ,Error injection on rdata after ECC correction" hexmask.long 0xC 0.--31. 1. "RDATA_INJ,Error injection on rdata" line.long 0x10 "RD_ECC_INJ,Error injection on read ecc code after ECC correction" hexmask.long.byte 0x10 8.--15. 1. "ECC_INJ1,Error injection on 8 ecc code for high 64 bits wdata" hexmask.long.byte 0x10 0.--7. 1. "ECC_INJ0,Error injection on 8 ecc code for low 64 bits wdata" rgroup.long 0x200++0x3 line.long 0x0 "ROM_FIX_NUM,Indicate ROM fix numbers and RTL version" hexmask.long.byte 0x0 24.--31. 1. "MAJOR_VERSION,ROM FIX major version" hexmask.long.byte 0x0 16.--23. 1. "MINOR_VERSION,ROM fix minor version" hexmask.long.byte 0x0 0.--7. 1. "FIX_NUM,Indicate ROM fix numbers" group.long 0x204++0x7 line.long 0x0 "ROM_FIX_CTRL,ROM fix feature enable and ROM fix registers lock" bitfld.long 0x0 1. "LOCK,When this bit is set all the ROM fix registers can not be written." "0,1" bitfld.long 0x0 0. "GLB_EN,enable ROM replace fix feature" "0,1" line.long 0x4 "ROM_FIX_EN,Indicate which ROM fix is enable" hexmask.long 0x4 0.--31. 1. "FIX_EN,Indicate which ROM replace fix is enable. Effective bits depend on ROM_FIX_NUM." group.long 0x210++0x7F line.long 0x0 "ROM_FIX_ADDR,Indicate ROM FIX address and jump instruction type." bitfld.long 0x0 28.--29. "JUMP_TYPE,Jump type. 0 - Jump fix thumb code; 1 - Jump fix ARM code; 2 - Jump fix AARCH64 code" "0,1,2,3" hexmask.long 0x0 0.--27. 1. "FIX_ADDR,Indicate ROM replace FIX address. Effective address depends on ROM size." line.long 0x4 "JUMP_ADDR,Indicate jump address." hexmask.long.tbyte 0x4 0.--23. 1. "ADDR,Indicate jump address." line.long 0x8 "ROM_FIX_ADDR,Indicate ROM FIX address and jump instruction type." bitfld.long 0x8 28.--29. "JUMP_TYPE,Jump type. 0 - Jump fix thumb code; 1 - Jump fix ARM code; 2 - Jump fix AARCH64 code" "0,1,2,3" hexmask.long 0x8 0.--27. 1. "FIX_ADDR,Indicate ROM replace FIX address. Effective address depends on ROM size." line.long 0xC "JUMP_ADDR,Indicate jump address." hexmask.long.tbyte 0xC 0.--23. 1. "ADDR,Indicate jump address." line.long 0x10 "ROM_FIX_ADDR,Indicate ROM FIX address and jump instruction type." bitfld.long 0x10 28.--29. "JUMP_TYPE,Jump type. 0 - Jump fix thumb code; 1 - Jump fix ARM code; 2 - Jump fix AARCH64 code" "0,1,2,3" hexmask.long 0x10 0.--27. 1. "FIX_ADDR,Indicate ROM replace FIX address. Effective address depends on ROM size." line.long 0x14 "JUMP_ADDR,Indicate jump address." hexmask.long.tbyte 0x14 0.--23. 1. "ADDR,Indicate jump address." line.long 0x18 "ROM_FIX_ADDR,Indicate ROM FIX address and jump instruction type." bitfld.long 0x18 28.--29. "JUMP_TYPE,Jump type. 0 - Jump fix thumb code; 1 - Jump fix ARM code; 2 - Jump fix AARCH64 code" "0,1,2,3" hexmask.long 0x18 0.--27. 1. "FIX_ADDR,Indicate ROM replace FIX address. Effective address depends on ROM size." line.long 0x1C "JUMP_ADDR,Indicate jump address." hexmask.long.tbyte 0x1C 0.--23. 1. "ADDR,Indicate jump address." line.long 0x20 "ROM_FIX_ADDR,Indicate ROM FIX address and jump instruction type." bitfld.long 0x20 28.--29. "JUMP_TYPE,Jump type. 0 - Jump fix thumb code; 1 - Jump fix ARM code; 2 - Jump fix AARCH64 code" "0,1,2,3" hexmask.long 0x20 0.--27. 1. "FIX_ADDR,Indicate ROM replace FIX address. Effective address depends on ROM size." line.long 0x24 "JUMP_ADDR,Indicate jump address." hexmask.long.tbyte 0x24 0.--23. 1. "ADDR,Indicate jump address." line.long 0x28 "ROM_FIX_ADDR,Indicate ROM FIX address and jump instruction type." bitfld.long 0x28 28.--29. "JUMP_TYPE,Jump type. 0 - Jump fix thumb code; 1 - Jump fix ARM code; 2 - Jump fix AARCH64 code" "0,1,2,3" hexmask.long 0x28 0.--27. 1. "FIX_ADDR,Indicate ROM replace FIX address. Effective address depends on ROM size." line.long 0x2C "JUMP_ADDR,Indicate jump address." hexmask.long.tbyte 0x2C 0.--23. 1. "ADDR,Indicate jump address." line.long 0x30 "ROM_FIX_ADDR,Indicate ROM FIX address and jump instruction type." bitfld.long 0x30 28.--29. "JUMP_TYPE,Jump type. 0 - Jump fix thumb code; 1 - Jump fix ARM code; 2 - Jump fix AARCH64 code" "0,1,2,3" hexmask.long 0x30 0.--27. 1. "FIX_ADDR,Indicate ROM replace FIX address. Effective address depends on ROM size." line.long 0x34 "JUMP_ADDR,Indicate jump address." hexmask.long.tbyte 0x34 0.--23. 1. "ADDR,Indicate jump address." line.long 0x38 "ROM_FIX_ADDR,Indicate ROM FIX address and jump instruction type." bitfld.long 0x38 28.--29. "JUMP_TYPE,Jump type. 0 - Jump fix thumb code; 1 - Jump fix ARM code; 2 - Jump fix AARCH64 code" "0,1,2,3" hexmask.long 0x38 0.--27. 1. "FIX_ADDR,Indicate ROM replace FIX address. Effective address depends on ROM size." line.long 0x3C "JUMP_ADDR,Indicate jump address." hexmask.long.tbyte 0x3C 0.--23. 1. "ADDR,Indicate jump address." line.long 0x40 "ROM_FIX_ADDR,Indicate ROM FIX address and jump instruction type." bitfld.long 0x40 28.--29. "JUMP_TYPE,Jump type. 0 - Jump fix thumb code; 1 - Jump fix ARM code; 2 - Jump fix AARCH64 code" "0,1,2,3" hexmask.long 0x40 0.--27. 1. "FIX_ADDR,Indicate ROM replace FIX address. Effective address depends on ROM size." line.long 0x44 "JUMP_ADDR,Indicate jump address." hexmask.long.tbyte 0x44 0.--23. 1. "ADDR,Indicate jump address." line.long 0x48 "ROM_FIX_ADDR,Indicate ROM FIX address and jump instruction type." bitfld.long 0x48 28.--29. "JUMP_TYPE,Jump type. 0 - Jump fix thumb code; 1 - Jump fix ARM code; 2 - Jump fix AARCH64 code" "0,1,2,3" hexmask.long 0x48 0.--27. 1. "FIX_ADDR,Indicate ROM replace FIX address. Effective address depends on ROM size." line.long 0x4C "JUMP_ADDR,Indicate jump address." hexmask.long.tbyte 0x4C 0.--23. 1. "ADDR,Indicate jump address." line.long 0x50 "ROM_FIX_ADDR,Indicate ROM FIX address and jump instruction type." bitfld.long 0x50 28.--29. "JUMP_TYPE,Jump type. 0 - Jump fix thumb code; 1 - Jump fix ARM code; 2 - Jump fix AARCH64 code" "0,1,2,3" hexmask.long 0x50 0.--27. 1. "FIX_ADDR,Indicate ROM replace FIX address. Effective address depends on ROM size." line.long 0x54 "JUMP_ADDR,Indicate jump address." hexmask.long.tbyte 0x54 0.--23. 1. "ADDR,Indicate jump address." line.long 0x58 "ROM_FIX_ADDR,Indicate ROM FIX address and jump instruction type." bitfld.long 0x58 28.--29. "JUMP_TYPE,Jump type. 0 - Jump fix thumb code; 1 - Jump fix ARM code; 2 - Jump fix AARCH64 code" "0,1,2,3" hexmask.long 0x58 0.--27. 1. "FIX_ADDR,Indicate ROM replace FIX address. Effective address depends on ROM size." line.long 0x5C "JUMP_ADDR,Indicate jump address." hexmask.long.tbyte 0x5C 0.--23. 1. "ADDR,Indicate jump address." line.long 0x60 "ROM_FIX_ADDR,Indicate ROM FIX address and jump instruction type." bitfld.long 0x60 28.--29. "JUMP_TYPE,Jump type. 0 - Jump fix thumb code; 1 - Jump fix ARM code; 2 - Jump fix AARCH64 code" "0,1,2,3" hexmask.long 0x60 0.--27. 1. "FIX_ADDR,Indicate ROM replace FIX address. Effective address depends on ROM size." line.long 0x64 "JUMP_ADDR,Indicate jump address." hexmask.long.tbyte 0x64 0.--23. 1. "ADDR,Indicate jump address." line.long 0x68 "ROM_FIX_ADDR,Indicate ROM FIX address and jump instruction type." bitfld.long 0x68 28.--29. "JUMP_TYPE,Jump type. 0 - Jump fix thumb code; 1 - Jump fix ARM code; 2 - Jump fix AARCH64 code" "0,1,2,3" hexmask.long 0x68 0.--27. 1. "FIX_ADDR,Indicate ROM replace FIX address. Effective address depends on ROM size." line.long 0x6C "JUMP_ADDR,Indicate jump address." hexmask.long.tbyte 0x6C 0.--23. 1. "ADDR,Indicate jump address." line.long 0x70 "ROM_FIX_ADDR,Indicate ROM FIX address and jump instruction type." bitfld.long 0x70 28.--29. "JUMP_TYPE,Jump type. 0 - Jump fix thumb code; 1 - Jump fix ARM code; 2 - Jump fix AARCH64 code" "0,1,2,3" hexmask.long 0x70 0.--27. 1. "FIX_ADDR,Indicate ROM replace FIX address. Effective address depends on ROM size." line.long 0x74 "JUMP_ADDR,Indicate jump address." hexmask.long.tbyte 0x74 0.--23. 1. "ADDR,Indicate jump address." line.long 0x78 "ROM_FIX_ADDR,Indicate ROM FIX address and jump instruction type." bitfld.long 0x78 28.--29. "JUMP_TYPE,Jump type. 0 - Jump fix thumb code; 1 - Jump fix ARM code; 2 - Jump fix AARCH64 code" "0,1,2,3" hexmask.long 0x78 0.--27. 1. "FIX_ADDR,Indicate ROM replace FIX address. Effective address depends on ROM size." line.long 0x7C "JUMP_ADDR,Indicate jump address." hexmask.long.tbyte 0x7C 0.--23. 1. "ADDR,Indicate jump address." group.long 0x400++0xFF line.long 0x0 "ROM_INJ,ROM injection code" hexmask.long 0x0 0.--31. 1. "CODE,ROM injection code" line.long 0x4 "ROM_INJ,ROM injection code" hexmask.long 0x4 0.--31. 1. "CODE,ROM injection code" line.long 0x8 "ROM_INJ,ROM injection code" hexmask.long 0x8 0.--31. 1. "CODE,ROM injection code" line.long 0xC "ROM_INJ,ROM injection code" hexmask.long 0xC 0.--31. 1. "CODE,ROM injection code" line.long 0x10 "ROM_INJ,ROM injection code" hexmask.long 0x10 0.--31. 1. "CODE,ROM injection code" line.long 0x14 "ROM_INJ,ROM injection code" hexmask.long 0x14 0.--31. 1. "CODE,ROM injection code" line.long 0x18 "ROM_INJ,ROM injection code" hexmask.long 0x18 0.--31. 1. "CODE,ROM injection code" line.long 0x1C "ROM_INJ,ROM injection code" hexmask.long 0x1C 0.--31. 1. "CODE,ROM injection code" line.long 0x20 "ROM_INJ,ROM injection code" hexmask.long 0x20 0.--31. 1. "CODE,ROM injection code" line.long 0x24 "ROM_INJ,ROM injection code" hexmask.long 0x24 0.--31. 1. "CODE,ROM injection code" line.long 0x28 "ROM_INJ,ROM injection code" hexmask.long 0x28 0.--31. 1. "CODE,ROM injection code" line.long 0x2C "ROM_INJ,ROM injection code" hexmask.long 0x2C 0.--31. 1. "CODE,ROM injection code" line.long 0x30 "ROM_INJ,ROM injection code" hexmask.long 0x30 0.--31. 1. "CODE,ROM injection code" line.long 0x34 "ROM_INJ,ROM injection code" hexmask.long 0x34 0.--31. 1. "CODE,ROM injection code" line.long 0x38 "ROM_INJ,ROM injection code" hexmask.long 0x38 0.--31. 1. "CODE,ROM injection code" line.long 0x3C "ROM_INJ,ROM injection code" hexmask.long 0x3C 0.--31. 1. "CODE,ROM injection code" line.long 0x40 "ROM_INJ,ROM injection code" hexmask.long 0x40 0.--31. 1. "CODE,ROM injection code" line.long 0x44 "ROM_INJ,ROM injection code" hexmask.long 0x44 0.--31. 1. "CODE,ROM injection code" line.long 0x48 "ROM_INJ,ROM injection code" hexmask.long 0x48 0.--31. 1. "CODE,ROM injection code" line.long 0x4C "ROM_INJ,ROM injection code" hexmask.long 0x4C 0.--31. 1. "CODE,ROM injection code" line.long 0x50 "ROM_INJ,ROM injection code" hexmask.long 0x50 0.--31. 1. "CODE,ROM injection code" line.long 0x54 "ROM_INJ,ROM injection code" hexmask.long 0x54 0.--31. 1. "CODE,ROM injection code" line.long 0x58 "ROM_INJ,ROM injection code" hexmask.long 0x58 0.--31. 1. "CODE,ROM injection code" line.long 0x5C "ROM_INJ,ROM injection code" hexmask.long 0x5C 0.--31. 1. "CODE,ROM injection code" line.long 0x60 "ROM_INJ,ROM injection code" hexmask.long 0x60 0.--31. 1. "CODE,ROM injection code" line.long 0x64 "ROM_INJ,ROM injection code" hexmask.long 0x64 0.--31. 1. "CODE,ROM injection code" line.long 0x68 "ROM_INJ,ROM injection code" hexmask.long 0x68 0.--31. 1. "CODE,ROM injection code" line.long 0x6C "ROM_INJ,ROM injection code" hexmask.long 0x6C 0.--31. 1. "CODE,ROM injection code" line.long 0x70 "ROM_INJ,ROM injection code" hexmask.long 0x70 0.--31. 1. "CODE,ROM injection code" line.long 0x74 "ROM_INJ,ROM injection code" hexmask.long 0x74 0.--31. 1. "CODE,ROM injection code" line.long 0x78 "ROM_INJ,ROM injection code" hexmask.long 0x78 0.--31. 1. "CODE,ROM injection code" line.long 0x7C "ROM_INJ,ROM injection code" hexmask.long 0x7C 0.--31. 1. "CODE,ROM injection code" line.long 0x80 "ROM_INJ,ROM injection code" hexmask.long 0x80 0.--31. 1. "CODE,ROM injection code" line.long 0x84 "ROM_INJ,ROM injection code" hexmask.long 0x84 0.--31. 1. "CODE,ROM injection code" line.long 0x88 "ROM_INJ,ROM injection code" hexmask.long 0x88 0.--31. 1. "CODE,ROM injection code" line.long 0x8C "ROM_INJ,ROM injection code" hexmask.long 0x8C 0.--31. 1. "CODE,ROM injection code" line.long 0x90 "ROM_INJ,ROM injection code" hexmask.long 0x90 0.--31. 1. "CODE,ROM injection code" line.long 0x94 "ROM_INJ,ROM injection code" hexmask.long 0x94 0.--31. 1. "CODE,ROM injection code" line.long 0x98 "ROM_INJ,ROM injection code" hexmask.long 0x98 0.--31. 1. "CODE,ROM injection code" line.long 0x9C "ROM_INJ,ROM injection code" hexmask.long 0x9C 0.--31. 1. "CODE,ROM injection code" line.long 0xA0 "ROM_INJ,ROM injection code" hexmask.long 0xA0 0.--31. 1. "CODE,ROM injection code" line.long 0xA4 "ROM_INJ,ROM injection code" hexmask.long 0xA4 0.--31. 1. "CODE,ROM injection code" line.long 0xA8 "ROM_INJ,ROM injection code" hexmask.long 0xA8 0.--31. 1. "CODE,ROM injection code" line.long 0xAC "ROM_INJ,ROM injection code" hexmask.long 0xAC 0.--31. 1. "CODE,ROM injection code" line.long 0xB0 "ROM_INJ,ROM injection code" hexmask.long 0xB0 0.--31. 1. "CODE,ROM injection code" line.long 0xB4 "ROM_INJ,ROM injection code" hexmask.long 0xB4 0.--31. 1. "CODE,ROM injection code" line.long 0xB8 "ROM_INJ,ROM injection code" hexmask.long 0xB8 0.--31. 1. "CODE,ROM injection code" line.long 0xBC "ROM_INJ,ROM injection code" hexmask.long 0xBC 0.--31. 1. "CODE,ROM injection code" line.long 0xC0 "ROM_INJ,ROM injection code" hexmask.long 0xC0 0.--31. 1. "CODE,ROM injection code" line.long 0xC4 "ROM_INJ,ROM injection code" hexmask.long 0xC4 0.--31. 1. "CODE,ROM injection code" line.long 0xC8 "ROM_INJ,ROM injection code" hexmask.long 0xC8 0.--31. 1. "CODE,ROM injection code" line.long 0xCC "ROM_INJ,ROM injection code" hexmask.long 0xCC 0.--31. 1. "CODE,ROM injection code" line.long 0xD0 "ROM_INJ,ROM injection code" hexmask.long 0xD0 0.--31. 1. "CODE,ROM injection code" line.long 0xD4 "ROM_INJ,ROM injection code" hexmask.long 0xD4 0.--31. 1. "CODE,ROM injection code" line.long 0xD8 "ROM_INJ,ROM injection code" hexmask.long 0xD8 0.--31. 1. "CODE,ROM injection code" line.long 0xDC "ROM_INJ,ROM injection code" hexmask.long 0xDC 0.--31. 1. "CODE,ROM injection code" line.long 0xE0 "ROM_INJ,ROM injection code" hexmask.long 0xE0 0.--31. 1. "CODE,ROM injection code" line.long 0xE4 "ROM_INJ,ROM injection code" hexmask.long 0xE4 0.--31. 1. "CODE,ROM injection code" line.long 0xE8 "ROM_INJ,ROM injection code" hexmask.long 0xE8 0.--31. 1. "CODE,ROM injection code" line.long 0xEC "ROM_INJ,ROM injection code" hexmask.long 0xEC 0.--31. 1. "CODE,ROM injection code" line.long 0xF0 "ROM_INJ,ROM injection code" hexmask.long 0xF0 0.--31. 1. "CODE,ROM injection code" line.long 0xF4 "ROM_INJ,ROM injection code" hexmask.long 0xF4 0.--31. 1. "CODE,ROM injection code" line.long 0xF8 "ROM_INJ,ROM injection code" hexmask.long 0xF8 0.--31. 1. "CODE,ROM injection code" line.long 0xFC "ROM_INJ,ROM injection code" hexmask.long 0xFC 0.--31. 1. "CODE,ROM injection code" tree.end tree "ROMC_AP" base ad:0xF06F0000 group.long 0x0++0x23 line.long 0x0 "MEM_ERR_INT_STATUS,Memory ECC error Interrupt status" bitfld.long 0x0 2. "RDATA_FATAL,It can report ECC correction logic error and protect rdata internal path." "0,1" bitfld.long 0x0 1. "MUL_ERR,Indicate double bit errors are detected." "0,1" bitfld.long 0x0 0. "SIG_ERR,Indicate single bit error is detected." "0,1" line.long 0x4 "MEM_ERR_INT_STA_EN,Memory ECC error Interrupt status enable" bitfld.long 0x4 2. "RDATA_FATAL_EN,Rdata fatal interrupt status enable" "0,1" bitfld.long 0x4 1. "MUL_ERR_EN,Multiple bit error interrupt status enable." "0,1" bitfld.long 0x4 0. "SIG_ERR_EN,Single bit error interrupt status enable." "0,1" line.long 0x8 "MEM_ERR_INT_SIG_EN,Memory ECC Interrupt signal enable" bitfld.long 0x8 2. "RDATA_FATAL_EN,Rdata fatal interrupt signal enable." "0,1" bitfld.long 0x8 1. "MUL_ERR_EN,Multiple bits errors interrupt signal enable." "0,1" bitfld.long 0x8 0. "SIG_ERR_EN,Single bit error interrupt signal enable." "0,1" line.long 0xC "UNCERR_INT_STA,AXI bus uncorrectable error interrupt status" bitfld.long 0xC 20. "RREADY,Uncorrectable error for RREADY" "0,1" bitfld.long 0xC 5. "ARVALID,Uncorrectable error for ARVALID" "0,1" newline bitfld.long 0xC 3. "ARCTL1,Uncorrectable error for ARCTL1(ARLOCK ARBURST ARSIZE ARLEN)" "0,1" bitfld.long 0xC 1. "ARADDR,Uncorrectable error for ARADDR" "0,1" bitfld.long 0xC 0. "ARID,Uncorrectable error for ARID" "0,1" line.long 0x10 "UNCERR_INT_STA_EN,AXI bus uncorrectable error interrupt status enable" bitfld.long 0x10 20. "RREADY,Statusl enable for RREADY" "0,1" bitfld.long 0x10 5. "ARVALID,Status enable for ARVALID" "0,1" newline bitfld.long 0x10 3. "ARCTL1,Status enable for ARCTL1(ARLOCK ARBURST ARSIZE ARLEN)" "0,1" bitfld.long 0x10 1. "ARADDR,Status enable for ARADDR" "0,1" bitfld.long 0x10 0. "ARID,Status enable for ARID" "0,1" line.long 0x14 "UNCERR_INT_SIG_EN,AXI bus uncorrectable error interrupt signal enable" bitfld.long 0x14 20. "RREADY,Signal enable for RREADY" "0,1" bitfld.long 0x14 5. "ARVALID,Signal enable for ARVALID" "0,1" newline bitfld.long 0x14 3. "ARCTL1,Signal enable for ARCTL1(ARLOCK ARBURST ARSIZE ARLEN)" "0,1" bitfld.long 0x14 1. "ARADDR,Signal enable for ARADDR" "0,1" bitfld.long 0x14 0. "ARID,Signal enable for ARID" "0,1" line.long 0x18 "CORERR_INT_STA,AXI bus correctable error interrupt status" bitfld.long 0x18 0. "ARADDR,Correctable error for ARADDR" "0,1" line.long 0x1C "CORERR_INT_STA_EN,AXI bus correctable error interrupt status enable" bitfld.long 0x1C 0. "ARADDR,Status enable for ARADDR" "0,1" line.long 0x20 "CORERR_INT_SIG_EN,AXI bus correctable error interrupt signal enable" bitfld.long 0x20 0. "ARADDR,Signal enable for ARADDR" "0,1" group.long 0x30++0x7 line.long 0x0 "FWEN,Firewall enable" bitfld.long 0x0 31. "LOCK,Lock FWEM register bit and itself" "0,1" bitfld.long 0x0 0. "FWEN,Firewall enable. Enable master ID check for all the apb access." "0,1" line.long 0x4 "STICKY_REG,Sticky register" bitfld.long 0x4 31. "LOCK_15,Lock lower register bit and itself" "0,1" bitfld.long 0x4 30. "LOCK_14,Lock lower register bit and itself" "0,1" bitfld.long 0x4 29. "LOCK_13,Lock lower register bit and itself" "0,1" bitfld.long 0x4 28. "LOCK_12,Lock lower register bit and itself" "0,1" bitfld.long 0x4 27. "LOCK_11,Lock lower register bit and itself" "0,1" newline bitfld.long 0x4 26. "LOCK_10,Lock lower register bit and itself" "0,1" bitfld.long 0x4 25. "LOCK_9,Lock lower register bit and itself" "0,1" bitfld.long 0x4 24. "LOCK_8,Lock lower register bit and itself" "0,1" bitfld.long 0x4 23. "LOCK_7,Lock lower register bit and itself" "0,1" bitfld.long 0x4 22. "LOCK_6,Lock lower register bit and itself" "0,1" newline bitfld.long 0x4 21. "LOCK_5,Lock lower register bit and itself" "0,1" bitfld.long 0x4 20. "LOCK_4,Lock lower register bit and itself" "0,1" bitfld.long 0x4 19. "LOCK_3,Lock lower register bit and itself" "0,1" bitfld.long 0x4 18. "LOCK_2,Lock lower register bit and itself" "0,1" bitfld.long 0x4 17. "LOCK_1,Lock lower register bit and itself" "0,1" newline bitfld.long 0x4 16. "LOCK_0,Lock lower register bit and itself" "0,1" bitfld.long 0x4 15. "REG_15,Register" "0,1" bitfld.long 0x4 14. "REG_14,Register" "0,1" bitfld.long 0x4 13. "REG_13,Register" "0,1" bitfld.long 0x4 12. "REG_12,Register" "0,1" newline bitfld.long 0x4 11. "REG_11,Register" "0,1" bitfld.long 0x4 10. "REG_10,Register" "0,1" bitfld.long 0x4 9. "REG_9,Register" "0,1" bitfld.long 0x4 8. "REG_8,Register" "0,1" bitfld.long 0x4 7. "REG_7,Register" "0,1" newline bitfld.long 0x4 6. "REG_6,Register" "0,1" bitfld.long 0x4 5. "REG_5,Register" "0,1" bitfld.long 0x4 4. "REG_4,Register" "0,1" bitfld.long 0x4 3. "REG_3,Register" "0,1" bitfld.long 0x4 2. "REG_2,Register" "0,1" newline bitfld.long 0x4 1. "REG_1,Register" "0,1" bitfld.long 0x4 0. "REG_0,Register" "0,1" rgroup.long 0x40++0x27 line.long 0x0 "SIG_ERR_ADDR,Store access address for first single bit error." hexmask.long 0x0 0.--31. 1. "ADDR,Error addr" line.long 0x4 "SIG_ERR_DATA_31_0,Store Error data for first single bit error" hexmask.long 0x4 0.--31. 1. "DATA,Error data" line.long 0x8 "SIG_ERR_DATA_63_32,Store Error data for first single bit error" hexmask.long 0x8 0.--31. 1. "DATA,Error data" line.long 0xC "SIG_ERR_DATA_95_64,Store Error data for first single bit error" hexmask.long 0xC 0.--31. 1. "DATA,Error data" line.long 0x10 "SIG_ERR_DATA_127_96,Store Error data for first single bit error" hexmask.long 0x10 0.--31. 1. "DATA,Error data" line.long 0x14 "MUL_ERR_ADDR,Store access address for multiple bits error." hexmask.long 0x14 0.--31. 1. "ADDR,Error address" line.long 0x18 "MUL_ERR_DATA_31_0,Store Error data for first multiple bits error" hexmask.long 0x18 0.--31. 1. "DATA,Error data" line.long 0x1C "MUL_ERR_DATA_63_32,Store Error data for first multiple bits error" hexmask.long 0x1C 0.--31. 1. "DATA,Error data" line.long 0x20 "MUL_ERR_DATA_95_64,Store Error data for first multiple bits error" hexmask.long 0x20 0.--31. 1. "DATA,Error data" line.long 0x24 "MUL_ERR_DATA_127_96,Store Error data for first multiple bits error" hexmask.long 0x24 0.--31. 1. "DATA,Error data" group.long 0x80++0x3 line.long 0x0 "ROM_DIS,ROM code disable" bitfld.long 0x0 0. "DIS,When this bit is set ROM code read and ROM fix register access are disable. Once this bit is set it is always set unless POR reset." "0,1" group.long 0x100++0x13 line.long 0x0 "RDATA_31_0_INJ,Error injection on rdata" hexmask.long 0x0 0.--31. 1. "RDATA_INJ,Error injection on rdata" line.long 0x4 "RDATA_63_32_INJ,Error injection on rdata" hexmask.long 0x4 0.--31. 1. "RDATA_INJ,Error injection on rdata" line.long 0x8 "RDATA_95_64_INJ,Error injection on rdata" hexmask.long 0x8 0.--31. 1. "RDATA_INJ,Error injection on rdata" line.long 0xC "RDATA_127_96_INJ,Error injection on rdata" hexmask.long 0xC 0.--31. 1. "RDATA_INJ,Error injection on rdata" line.long 0x10 "ECC_INJ,Error injection on read ecc code" hexmask.long.byte 0x10 8.--15. 1. "ECC_INJ1,Error injection on 8 ecc code for high 64 bits wdata" hexmask.long.byte 0x10 0.--7. 1. "ECC_INJ0,Error injection on 8 ecc code for low 64 bits wdata" group.long 0x120++0x13 line.long 0x0 "RD_DATA_31_0_INJ,Error injection on rdata after ECC correction" hexmask.long 0x0 0.--31. 1. "RDATA_INJ,Error injection on rdata" line.long 0x4 "RD_DATA_63_32_INJ,Error injection on rdata after ECC correction" hexmask.long 0x4 0.--31. 1. "RDATA_INJ,Error injection on rdata" line.long 0x8 "RD_DATA_95_64_INJ,Error injection on rdata after ECC correction" hexmask.long 0x8 0.--31. 1. "RDATA_INJ,Error injection on rdata" line.long 0xC "RD_DATA_127_96_INJ,Error injection on rdata after ECC correction" hexmask.long 0xC 0.--31. 1. "RDATA_INJ,Error injection on rdata" line.long 0x10 "RD_ECC_INJ,Error injection on read ecc code after ECC correction" hexmask.long.byte 0x10 8.--15. 1. "ECC_INJ1,Error injection on 8 ecc code for high 64 bits wdata" hexmask.long.byte 0x10 0.--7. 1. "ECC_INJ0,Error injection on 8 ecc code for low 64 bits wdata" rgroup.long 0x200++0x3 line.long 0x0 "ROM_FIX_NUM,Indicate ROM fix numbers and RTL version" hexmask.long.byte 0x0 24.--31. 1. "MAJOR_VERSION,ROM FIX major version" hexmask.long.byte 0x0 16.--23. 1. "MINOR_VERSION,ROM fix minor version" hexmask.long.byte 0x0 0.--7. 1. "FIX_NUM,Indicate ROM fix numbers" group.long 0x204++0x7 line.long 0x0 "ROM_FIX_CTRL,ROM fix feature enable and ROM fix registers lock" bitfld.long 0x0 1. "LOCK,When this bit is set all the ROM fix registers can not be written." "0,1" bitfld.long 0x0 0. "GLB_EN,enable ROM replace fix feature" "0,1" line.long 0x4 "ROM_FIX_EN,Indicate which ROM fix is enable" hexmask.long 0x4 0.--31. 1. "FIX_EN,Indicate which ROM replace fix is enable. Effective bits depend on ROM_FIX_NUM." group.long 0x210++0x7F line.long 0x0 "ROM_FIX_ADDR,Indicate ROM FIX address and jump instruction type." bitfld.long 0x0 28.--29. "JUMP_TYPE,Jump type. 0 - Jump fix thumb code; 1 - Jump fix ARM code; 2 - Jump fix AARCH64 code" "0,1,2,3" hexmask.long 0x0 0.--27. 1. "FIX_ADDR,Indicate ROM replace FIX address. Effective address depends on ROM size." line.long 0x4 "JUMP_ADDR,Indicate jump address." hexmask.long.tbyte 0x4 0.--23. 1. "ADDR,Indicate jump address." line.long 0x8 "ROM_FIX_ADDR,Indicate ROM FIX address and jump instruction type." bitfld.long 0x8 28.--29. "JUMP_TYPE,Jump type. 0 - Jump fix thumb code; 1 - Jump fix ARM code; 2 - Jump fix AARCH64 code" "0,1,2,3" hexmask.long 0x8 0.--27. 1. "FIX_ADDR,Indicate ROM replace FIX address. Effective address depends on ROM size." line.long 0xC "JUMP_ADDR,Indicate jump address." hexmask.long.tbyte 0xC 0.--23. 1. "ADDR,Indicate jump address." line.long 0x10 "ROM_FIX_ADDR,Indicate ROM FIX address and jump instruction type." bitfld.long 0x10 28.--29. "JUMP_TYPE,Jump type. 0 - Jump fix thumb code; 1 - Jump fix ARM code; 2 - Jump fix AARCH64 code" "0,1,2,3" hexmask.long 0x10 0.--27. 1. "FIX_ADDR,Indicate ROM replace FIX address. Effective address depends on ROM size." line.long 0x14 "JUMP_ADDR,Indicate jump address." hexmask.long.tbyte 0x14 0.--23. 1. "ADDR,Indicate jump address." line.long 0x18 "ROM_FIX_ADDR,Indicate ROM FIX address and jump instruction type." bitfld.long 0x18 28.--29. "JUMP_TYPE,Jump type. 0 - Jump fix thumb code; 1 - Jump fix ARM code; 2 - Jump fix AARCH64 code" "0,1,2,3" hexmask.long 0x18 0.--27. 1. "FIX_ADDR,Indicate ROM replace FIX address. Effective address depends on ROM size." line.long 0x1C "JUMP_ADDR,Indicate jump address." hexmask.long.tbyte 0x1C 0.--23. 1. "ADDR,Indicate jump address." line.long 0x20 "ROM_FIX_ADDR,Indicate ROM FIX address and jump instruction type." bitfld.long 0x20 28.--29. "JUMP_TYPE,Jump type. 0 - Jump fix thumb code; 1 - Jump fix ARM code; 2 - Jump fix AARCH64 code" "0,1,2,3" hexmask.long 0x20 0.--27. 1. "FIX_ADDR,Indicate ROM replace FIX address. Effective address depends on ROM size." line.long 0x24 "JUMP_ADDR,Indicate jump address." hexmask.long.tbyte 0x24 0.--23. 1. "ADDR,Indicate jump address." line.long 0x28 "ROM_FIX_ADDR,Indicate ROM FIX address and jump instruction type." bitfld.long 0x28 28.--29. "JUMP_TYPE,Jump type. 0 - Jump fix thumb code; 1 - Jump fix ARM code; 2 - Jump fix AARCH64 code" "0,1,2,3" hexmask.long 0x28 0.--27. 1. "FIX_ADDR,Indicate ROM replace FIX address. Effective address depends on ROM size." line.long 0x2C "JUMP_ADDR,Indicate jump address." hexmask.long.tbyte 0x2C 0.--23. 1. "ADDR,Indicate jump address." line.long 0x30 "ROM_FIX_ADDR,Indicate ROM FIX address and jump instruction type." bitfld.long 0x30 28.--29. "JUMP_TYPE,Jump type. 0 - Jump fix thumb code; 1 - Jump fix ARM code; 2 - Jump fix AARCH64 code" "0,1,2,3" hexmask.long 0x30 0.--27. 1. "FIX_ADDR,Indicate ROM replace FIX address. Effective address depends on ROM size." line.long 0x34 "JUMP_ADDR,Indicate jump address." hexmask.long.tbyte 0x34 0.--23. 1. "ADDR,Indicate jump address." line.long 0x38 "ROM_FIX_ADDR,Indicate ROM FIX address and jump instruction type." bitfld.long 0x38 28.--29. "JUMP_TYPE,Jump type. 0 - Jump fix thumb code; 1 - Jump fix ARM code; 2 - Jump fix AARCH64 code" "0,1,2,3" hexmask.long 0x38 0.--27. 1. "FIX_ADDR,Indicate ROM replace FIX address. Effective address depends on ROM size." line.long 0x3C "JUMP_ADDR,Indicate jump address." hexmask.long.tbyte 0x3C 0.--23. 1. "ADDR,Indicate jump address." line.long 0x40 "ROM_FIX_ADDR,Indicate ROM FIX address and jump instruction type." bitfld.long 0x40 28.--29. "JUMP_TYPE,Jump type. 0 - Jump fix thumb code; 1 - Jump fix ARM code; 2 - Jump fix AARCH64 code" "0,1,2,3" hexmask.long 0x40 0.--27. 1. "FIX_ADDR,Indicate ROM replace FIX address. Effective address depends on ROM size." line.long 0x44 "JUMP_ADDR,Indicate jump address." hexmask.long.tbyte 0x44 0.--23. 1. "ADDR,Indicate jump address." line.long 0x48 "ROM_FIX_ADDR,Indicate ROM FIX address and jump instruction type." bitfld.long 0x48 28.--29. "JUMP_TYPE,Jump type. 0 - Jump fix thumb code; 1 - Jump fix ARM code; 2 - Jump fix AARCH64 code" "0,1,2,3" hexmask.long 0x48 0.--27. 1. "FIX_ADDR,Indicate ROM replace FIX address. Effective address depends on ROM size." line.long 0x4C "JUMP_ADDR,Indicate jump address." hexmask.long.tbyte 0x4C 0.--23. 1. "ADDR,Indicate jump address." line.long 0x50 "ROM_FIX_ADDR,Indicate ROM FIX address and jump instruction type." bitfld.long 0x50 28.--29. "JUMP_TYPE,Jump type. 0 - Jump fix thumb code; 1 - Jump fix ARM code; 2 - Jump fix AARCH64 code" "0,1,2,3" hexmask.long 0x50 0.--27. 1. "FIX_ADDR,Indicate ROM replace FIX address. Effective address depends on ROM size." line.long 0x54 "JUMP_ADDR,Indicate jump address." hexmask.long.tbyte 0x54 0.--23. 1. "ADDR,Indicate jump address." line.long 0x58 "ROM_FIX_ADDR,Indicate ROM FIX address and jump instruction type." bitfld.long 0x58 28.--29. "JUMP_TYPE,Jump type. 0 - Jump fix thumb code; 1 - Jump fix ARM code; 2 - Jump fix AARCH64 code" "0,1,2,3" hexmask.long 0x58 0.--27. 1. "FIX_ADDR,Indicate ROM replace FIX address. Effective address depends on ROM size." line.long 0x5C "JUMP_ADDR,Indicate jump address." hexmask.long.tbyte 0x5C 0.--23. 1. "ADDR,Indicate jump address." line.long 0x60 "ROM_FIX_ADDR,Indicate ROM FIX address and jump instruction type." bitfld.long 0x60 28.--29. "JUMP_TYPE,Jump type. 0 - Jump fix thumb code; 1 - Jump fix ARM code; 2 - Jump fix AARCH64 code" "0,1,2,3" hexmask.long 0x60 0.--27. 1. "FIX_ADDR,Indicate ROM replace FIX address. Effective address depends on ROM size." line.long 0x64 "JUMP_ADDR,Indicate jump address." hexmask.long.tbyte 0x64 0.--23. 1. "ADDR,Indicate jump address." line.long 0x68 "ROM_FIX_ADDR,Indicate ROM FIX address and jump instruction type." bitfld.long 0x68 28.--29. "JUMP_TYPE,Jump type. 0 - Jump fix thumb code; 1 - Jump fix ARM code; 2 - Jump fix AARCH64 code" "0,1,2,3" hexmask.long 0x68 0.--27. 1. "FIX_ADDR,Indicate ROM replace FIX address. Effective address depends on ROM size." line.long 0x6C "JUMP_ADDR,Indicate jump address." hexmask.long.tbyte 0x6C 0.--23. 1. "ADDR,Indicate jump address." line.long 0x70 "ROM_FIX_ADDR,Indicate ROM FIX address and jump instruction type." bitfld.long 0x70 28.--29. "JUMP_TYPE,Jump type. 0 - Jump fix thumb code; 1 - Jump fix ARM code; 2 - Jump fix AARCH64 code" "0,1,2,3" hexmask.long 0x70 0.--27. 1. "FIX_ADDR,Indicate ROM replace FIX address. Effective address depends on ROM size." line.long 0x74 "JUMP_ADDR,Indicate jump address." hexmask.long.tbyte 0x74 0.--23. 1. "ADDR,Indicate jump address." line.long 0x78 "ROM_FIX_ADDR,Indicate ROM FIX address and jump instruction type." bitfld.long 0x78 28.--29. "JUMP_TYPE,Jump type. 0 - Jump fix thumb code; 1 - Jump fix ARM code; 2 - Jump fix AARCH64 code" "0,1,2,3" hexmask.long 0x78 0.--27. 1. "FIX_ADDR,Indicate ROM replace FIX address. Effective address depends on ROM size." line.long 0x7C "JUMP_ADDR,Indicate jump address." hexmask.long.tbyte 0x7C 0.--23. 1. "ADDR,Indicate jump address." group.long 0x400++0xFF line.long 0x0 "ROM_INJ,ROM injection code" hexmask.long 0x0 0.--31. 1. "CODE,ROM injection code" line.long 0x4 "ROM_INJ,ROM injection code" hexmask.long 0x4 0.--31. 1. "CODE,ROM injection code" line.long 0x8 "ROM_INJ,ROM injection code" hexmask.long 0x8 0.--31. 1. "CODE,ROM injection code" line.long 0xC "ROM_INJ,ROM injection code" hexmask.long 0xC 0.--31. 1. "CODE,ROM injection code" line.long 0x10 "ROM_INJ,ROM injection code" hexmask.long 0x10 0.--31. 1. "CODE,ROM injection code" line.long 0x14 "ROM_INJ,ROM injection code" hexmask.long 0x14 0.--31. 1. "CODE,ROM injection code" line.long 0x18 "ROM_INJ,ROM injection code" hexmask.long 0x18 0.--31. 1. "CODE,ROM injection code" line.long 0x1C "ROM_INJ,ROM injection code" hexmask.long 0x1C 0.--31. 1. "CODE,ROM injection code" line.long 0x20 "ROM_INJ,ROM injection code" hexmask.long 0x20 0.--31. 1. "CODE,ROM injection code" line.long 0x24 "ROM_INJ,ROM injection code" hexmask.long 0x24 0.--31. 1. "CODE,ROM injection code" line.long 0x28 "ROM_INJ,ROM injection code" hexmask.long 0x28 0.--31. 1. "CODE,ROM injection code" line.long 0x2C "ROM_INJ,ROM injection code" hexmask.long 0x2C 0.--31. 1. "CODE,ROM injection code" line.long 0x30 "ROM_INJ,ROM injection code" hexmask.long 0x30 0.--31. 1. "CODE,ROM injection code" line.long 0x34 "ROM_INJ,ROM injection code" hexmask.long 0x34 0.--31. 1. "CODE,ROM injection code" line.long 0x38 "ROM_INJ,ROM injection code" hexmask.long 0x38 0.--31. 1. "CODE,ROM injection code" line.long 0x3C "ROM_INJ,ROM injection code" hexmask.long 0x3C 0.--31. 1. "CODE,ROM injection code" line.long 0x40 "ROM_INJ,ROM injection code" hexmask.long 0x40 0.--31. 1. "CODE,ROM injection code" line.long 0x44 "ROM_INJ,ROM injection code" hexmask.long 0x44 0.--31. 1. "CODE,ROM injection code" line.long 0x48 "ROM_INJ,ROM injection code" hexmask.long 0x48 0.--31. 1. "CODE,ROM injection code" line.long 0x4C "ROM_INJ,ROM injection code" hexmask.long 0x4C 0.--31. 1. "CODE,ROM injection code" line.long 0x50 "ROM_INJ,ROM injection code" hexmask.long 0x50 0.--31. 1. "CODE,ROM injection code" line.long 0x54 "ROM_INJ,ROM injection code" hexmask.long 0x54 0.--31. 1. "CODE,ROM injection code" line.long 0x58 "ROM_INJ,ROM injection code" hexmask.long 0x58 0.--31. 1. "CODE,ROM injection code" line.long 0x5C "ROM_INJ,ROM injection code" hexmask.long 0x5C 0.--31. 1. "CODE,ROM injection code" line.long 0x60 "ROM_INJ,ROM injection code" hexmask.long 0x60 0.--31. 1. "CODE,ROM injection code" line.long 0x64 "ROM_INJ,ROM injection code" hexmask.long 0x64 0.--31. 1. "CODE,ROM injection code" line.long 0x68 "ROM_INJ,ROM injection code" hexmask.long 0x68 0.--31. 1. "CODE,ROM injection code" line.long 0x6C "ROM_INJ,ROM injection code" hexmask.long 0x6C 0.--31. 1. "CODE,ROM injection code" line.long 0x70 "ROM_INJ,ROM injection code" hexmask.long 0x70 0.--31. 1. "CODE,ROM injection code" line.long 0x74 "ROM_INJ,ROM injection code" hexmask.long 0x74 0.--31. 1. "CODE,ROM injection code" line.long 0x78 "ROM_INJ,ROM injection code" hexmask.long 0x78 0.--31. 1. "CODE,ROM injection code" line.long 0x7C "ROM_INJ,ROM injection code" hexmask.long 0x7C 0.--31. 1. "CODE,ROM injection code" line.long 0x80 "ROM_INJ,ROM injection code" hexmask.long 0x80 0.--31. 1. "CODE,ROM injection code" line.long 0x84 "ROM_INJ,ROM injection code" hexmask.long 0x84 0.--31. 1. "CODE,ROM injection code" line.long 0x88 "ROM_INJ,ROM injection code" hexmask.long 0x88 0.--31. 1. "CODE,ROM injection code" line.long 0x8C "ROM_INJ,ROM injection code" hexmask.long 0x8C 0.--31. 1. "CODE,ROM injection code" line.long 0x90 "ROM_INJ,ROM injection code" hexmask.long 0x90 0.--31. 1. "CODE,ROM injection code" line.long 0x94 "ROM_INJ,ROM injection code" hexmask.long 0x94 0.--31. 1. "CODE,ROM injection code" line.long 0x98 "ROM_INJ,ROM injection code" hexmask.long 0x98 0.--31. 1. "CODE,ROM injection code" line.long 0x9C "ROM_INJ,ROM injection code" hexmask.long 0x9C 0.--31. 1. "CODE,ROM injection code" line.long 0xA0 "ROM_INJ,ROM injection code" hexmask.long 0xA0 0.--31. 1. "CODE,ROM injection code" line.long 0xA4 "ROM_INJ,ROM injection code" hexmask.long 0xA4 0.--31. 1. "CODE,ROM injection code" line.long 0xA8 "ROM_INJ,ROM injection code" hexmask.long 0xA8 0.--31. 1. "CODE,ROM injection code" line.long 0xAC "ROM_INJ,ROM injection code" hexmask.long 0xAC 0.--31. 1. "CODE,ROM injection code" line.long 0xB0 "ROM_INJ,ROM injection code" hexmask.long 0xB0 0.--31. 1. "CODE,ROM injection code" line.long 0xB4 "ROM_INJ,ROM injection code" hexmask.long 0xB4 0.--31. 1. "CODE,ROM injection code" line.long 0xB8 "ROM_INJ,ROM injection code" hexmask.long 0xB8 0.--31. 1. "CODE,ROM injection code" line.long 0xBC "ROM_INJ,ROM injection code" hexmask.long 0xBC 0.--31. 1. "CODE,ROM injection code" line.long 0xC0 "ROM_INJ,ROM injection code" hexmask.long 0xC0 0.--31. 1. "CODE,ROM injection code" line.long 0xC4 "ROM_INJ,ROM injection code" hexmask.long 0xC4 0.--31. 1. "CODE,ROM injection code" line.long 0xC8 "ROM_INJ,ROM injection code" hexmask.long 0xC8 0.--31. 1. "CODE,ROM injection code" line.long 0xCC "ROM_INJ,ROM injection code" hexmask.long 0xCC 0.--31. 1. "CODE,ROM injection code" line.long 0xD0 "ROM_INJ,ROM injection code" hexmask.long 0xD0 0.--31. 1. "CODE,ROM injection code" line.long 0xD4 "ROM_INJ,ROM injection code" hexmask.long 0xD4 0.--31. 1. "CODE,ROM injection code" line.long 0xD8 "ROM_INJ,ROM injection code" hexmask.long 0xD8 0.--31. 1. "CODE,ROM injection code" line.long 0xDC "ROM_INJ,ROM injection code" hexmask.long 0xDC 0.--31. 1. "CODE,ROM injection code" line.long 0xE0 "ROM_INJ,ROM injection code" hexmask.long 0xE0 0.--31. 1. "CODE,ROM injection code" line.long 0xE4 "ROM_INJ,ROM injection code" hexmask.long 0xE4 0.--31. 1. "CODE,ROM injection code" line.long 0xE8 "ROM_INJ,ROM injection code" hexmask.long 0xE8 0.--31. 1. "CODE,ROM injection code" line.long 0xEC "ROM_INJ,ROM injection code" hexmask.long 0xEC 0.--31. 1. "CODE,ROM injection code" line.long 0xF0 "ROM_INJ,ROM injection code" hexmask.long 0xF0 0.--31. 1. "CODE,ROM injection code" line.long 0xF4 "ROM_INJ,ROM injection code" hexmask.long 0xF4 0.--31. 1. "CODE,ROM injection code" line.long 0xF8 "ROM_INJ,ROM injection code" hexmask.long 0xF8 0.--31. 1. "CODE,ROM injection code" line.long 0xFC "ROM_INJ,ROM injection code" hexmask.long 0xFC 0.--31. 1. "CODE,ROM injection code" tree.end elif (CORENAME()=="CORTEXA55") tree "ROMC_SAFETY" base ad:0x30200000 group.long 0x0++0x23 line.long 0x0 "MEM_ERR_INT_STATUS,Memory ECC error Interrupt status" bitfld.long 0x0 2. "RDATA_FATAL,It can report ECC correction logic error and protect rdata internal path." "0,1" bitfld.long 0x0 1. "MUL_ERR,Indicate double bit errors are detected." "0,1" bitfld.long 0x0 0. "SIG_ERR,Indicate single bit error is detected." "0,1" line.long 0x4 "MEM_ERR_INT_STA_EN,Memory ECC error Interrupt status enable" bitfld.long 0x4 2. "RDATA_FATAL_EN,Rdata fatal interrupt status enable" "0,1" bitfld.long 0x4 1. "MUL_ERR_EN,Multiple bit error interrupt status enable." "0,1" bitfld.long 0x4 0. "SIG_ERR_EN,Single bit error interrupt status enable." "0,1" line.long 0x8 "MEM_ERR_INT_SIG_EN,Memory ECC Interrupt signal enable" bitfld.long 0x8 2. "RDATA_FATAL_EN,Rdata fatal interrupt signal enable." "0,1" bitfld.long 0x8 1. "MUL_ERR_EN,Multiple bits errors interrupt signal enable." "0,1" bitfld.long 0x8 0. "SIG_ERR_EN,Single bit error interrupt signal enable." "0,1" line.long 0xC "UNCERR_INT_STA,AXI bus uncorrectable error interrupt status" bitfld.long 0xC 20. "RREADY,Uncorrectable error for RREADY" "0,1" bitfld.long 0xC 5. "ARVALID,Uncorrectable error for ARVALID" "0,1" newline bitfld.long 0xC 3. "ARCTL1,Uncorrectable error for ARCTL1(ARLOCK ARBURST ARSIZE ARLEN)" "0,1" bitfld.long 0xC 1. "ARADDR,Uncorrectable error for ARADDR" "0,1" bitfld.long 0xC 0. "ARID,Uncorrectable error for ARID" "0,1" line.long 0x10 "UNCERR_INT_STA_EN,AXI bus uncorrectable error interrupt status enable" bitfld.long 0x10 20. "RREADY,Statusl enable for RREADY" "0,1" bitfld.long 0x10 5. "ARVALID,Status enable for ARVALID" "0,1" newline bitfld.long 0x10 3. "ARCTL1,Status enable for ARCTL1(ARLOCK ARBURST ARSIZE ARLEN)" "0,1" bitfld.long 0x10 1. "ARADDR,Status enable for ARADDR" "0,1" bitfld.long 0x10 0. "ARID,Status enable for ARID" "0,1" line.long 0x14 "UNCERR_INT_SIG_EN,AXI bus uncorrectable error interrupt signal enable" bitfld.long 0x14 20. "RREADY,Signal enable for RREADY" "0,1" bitfld.long 0x14 5. "ARVALID,Signal enable for ARVALID" "0,1" newline bitfld.long 0x14 3. "ARCTL1,Signal enable for ARCTL1(ARLOCK ARBURST ARSIZE ARLEN)" "0,1" bitfld.long 0x14 1. "ARADDR,Signal enable for ARADDR" "0,1" bitfld.long 0x14 0. "ARID,Signal enable for ARID" "0,1" line.long 0x18 "CORERR_INT_STA,AXI bus correctable error interrupt status" bitfld.long 0x18 0. "ARADDR,Correctable error for ARADDR" "0,1" line.long 0x1C "CORERR_INT_STA_EN,AXI bus correctable error interrupt status enable" bitfld.long 0x1C 0. "ARADDR,Status enable for ARADDR" "0,1" line.long 0x20 "CORERR_INT_SIG_EN,AXI bus correctable error interrupt signal enable" bitfld.long 0x20 0. "ARADDR,Signal enable for ARADDR" "0,1" group.long 0x30++0x7 line.long 0x0 "FWEN,Firewall enable" bitfld.long 0x0 31. "LOCK,Lock FWEM register bit and itself" "0,1" bitfld.long 0x0 0. "FWEN,Firewall enable. Enable master ID check for all the apb access." "0,1" line.long 0x4 "STICKY_REG,Sticky register" bitfld.long 0x4 31. "LOCK_15,Lock lower register bit and itself" "0,1" bitfld.long 0x4 30. "LOCK_14,Lock lower register bit and itself" "0,1" bitfld.long 0x4 29. "LOCK_13,Lock lower register bit and itself" "0,1" bitfld.long 0x4 28. "LOCK_12,Lock lower register bit and itself" "0,1" bitfld.long 0x4 27. "LOCK_11,Lock lower register bit and itself" "0,1" newline bitfld.long 0x4 26. "LOCK_10,Lock lower register bit and itself" "0,1" bitfld.long 0x4 25. "LOCK_9,Lock lower register bit and itself" "0,1" bitfld.long 0x4 24. "LOCK_8,Lock lower register bit and itself" "0,1" bitfld.long 0x4 23. "LOCK_7,Lock lower register bit and itself" "0,1" bitfld.long 0x4 22. "LOCK_6,Lock lower register bit and itself" "0,1" newline bitfld.long 0x4 21. "LOCK_5,Lock lower register bit and itself" "0,1" bitfld.long 0x4 20. "LOCK_4,Lock lower register bit and itself" "0,1" bitfld.long 0x4 19. "LOCK_3,Lock lower register bit and itself" "0,1" bitfld.long 0x4 18. "LOCK_2,Lock lower register bit and itself" "0,1" bitfld.long 0x4 17. "LOCK_1,Lock lower register bit and itself" "0,1" newline bitfld.long 0x4 16. "LOCK_0,Lock lower register bit and itself" "0,1" bitfld.long 0x4 15. "REG_15,Register" "0,1" bitfld.long 0x4 14. "REG_14,Register" "0,1" bitfld.long 0x4 13. "REG_13,Register" "0,1" bitfld.long 0x4 12. "REG_12,Register" "0,1" newline bitfld.long 0x4 11. "REG_11,Register" "0,1" bitfld.long 0x4 10. "REG_10,Register" "0,1" bitfld.long 0x4 9. "REG_9,Register" "0,1" bitfld.long 0x4 8. "REG_8,Register" "0,1" bitfld.long 0x4 7. "REG_7,Register" "0,1" newline bitfld.long 0x4 6. "REG_6,Register" "0,1" bitfld.long 0x4 5. "REG_5,Register" "0,1" bitfld.long 0x4 4. "REG_4,Register" "0,1" bitfld.long 0x4 3. "REG_3,Register" "0,1" bitfld.long 0x4 2. "REG_2,Register" "0,1" newline bitfld.long 0x4 1. "REG_1,Register" "0,1" bitfld.long 0x4 0. "REG_0,Register" "0,1" rgroup.long 0x40++0x27 line.long 0x0 "SIG_ERR_ADDR,Store access address for first single bit error." hexmask.long 0x0 0.--31. 1. "ADDR,Error addr" line.long 0x4 "SIG_ERR_DATA_31_0,Store Error data for first single bit error" hexmask.long 0x4 0.--31. 1. "DATA,Error data" line.long 0x8 "SIG_ERR_DATA_63_32,Store Error data for first single bit error" hexmask.long 0x8 0.--31. 1. "DATA,Error data" line.long 0xC "SIG_ERR_DATA_95_64,Store Error data for first single bit error" hexmask.long 0xC 0.--31. 1. "DATA,Error data" line.long 0x10 "SIG_ERR_DATA_127_96,Store Error data for first single bit error" hexmask.long 0x10 0.--31. 1. "DATA,Error data" line.long 0x14 "MUL_ERR_ADDR,Store access address for multiple bits error." hexmask.long 0x14 0.--31. 1. "ADDR,Error address" line.long 0x18 "MUL_ERR_DATA_31_0,Store Error data for first multiple bits error" hexmask.long 0x18 0.--31. 1. "DATA,Error data" line.long 0x1C "MUL_ERR_DATA_63_32,Store Error data for first multiple bits error" hexmask.long 0x1C 0.--31. 1. "DATA,Error data" line.long 0x20 "MUL_ERR_DATA_95_64,Store Error data for first multiple bits error" hexmask.long 0x20 0.--31. 1. "DATA,Error data" line.long 0x24 "MUL_ERR_DATA_127_96,Store Error data for first multiple bits error" hexmask.long 0x24 0.--31. 1. "DATA,Error data" group.long 0x80++0x3 line.long 0x0 "ROM_DIS,ROM code disable" bitfld.long 0x0 0. "DIS,When this bit is set ROM code read and ROM fix register access are disable. Once this bit is set it is always set unless POR reset." "0,1" group.long 0x100++0x13 line.long 0x0 "RDATA_31_0_INJ,Error injection on rdata" hexmask.long 0x0 0.--31. 1. "RDATA_INJ,Error injection on rdata" line.long 0x4 "RDATA_63_32_INJ,Error injection on rdata" hexmask.long 0x4 0.--31. 1. "RDATA_INJ,Error injection on rdata" line.long 0x8 "RDATA_95_64_INJ,Error injection on rdata" hexmask.long 0x8 0.--31. 1. "RDATA_INJ,Error injection on rdata" line.long 0xC "RDATA_127_96_INJ,Error injection on rdata" hexmask.long 0xC 0.--31. 1. "RDATA_INJ,Error injection on rdata" line.long 0x10 "ECC_INJ,Error injection on read ecc code" hexmask.long.byte 0x10 8.--15. 1. "ECC_INJ1,Error injection on 8 ecc code for high 64 bits wdata" hexmask.long.byte 0x10 0.--7. 1. "ECC_INJ0,Error injection on 8 ecc code for low 64 bits wdata" group.long 0x120++0x13 line.long 0x0 "RD_DATA_31_0_INJ,Error injection on rdata after ECC correction" hexmask.long 0x0 0.--31. 1. "RDATA_INJ,Error injection on rdata" line.long 0x4 "RD_DATA_63_32_INJ,Error injection on rdata after ECC correction" hexmask.long 0x4 0.--31. 1. "RDATA_INJ,Error injection on rdata" line.long 0x8 "RD_DATA_95_64_INJ,Error injection on rdata after ECC correction" hexmask.long 0x8 0.--31. 1. "RDATA_INJ,Error injection on rdata" line.long 0xC "RD_DATA_127_96_INJ,Error injection on rdata after ECC correction" hexmask.long 0xC 0.--31. 1. "RDATA_INJ,Error injection on rdata" line.long 0x10 "RD_ECC_INJ,Error injection on read ecc code after ECC correction" hexmask.long.byte 0x10 8.--15. 1. "ECC_INJ1,Error injection on 8 ecc code for high 64 bits wdata" hexmask.long.byte 0x10 0.--7. 1. "ECC_INJ0,Error injection on 8 ecc code for low 64 bits wdata" rgroup.long 0x200++0x3 line.long 0x0 "ROM_FIX_NUM,Indicate ROM fix numbers and RTL version" hexmask.long.byte 0x0 24.--31. 1. "MAJOR_VERSION,ROM FIX major version" hexmask.long.byte 0x0 16.--23. 1. "MINOR_VERSION,ROM fix minor version" hexmask.long.byte 0x0 0.--7. 1. "FIX_NUM,Indicate ROM fix numbers" group.long 0x204++0x7 line.long 0x0 "ROM_FIX_CTRL,ROM fix feature enable and ROM fix registers lock" bitfld.long 0x0 1. "LOCK,When this bit is set all the ROM fix registers can not be written." "0,1" bitfld.long 0x0 0. "GLB_EN,enable ROM replace fix feature" "0,1" line.long 0x4 "ROM_FIX_EN,Indicate which ROM fix is enable" hexmask.long 0x4 0.--31. 1. "FIX_EN,Indicate which ROM replace fix is enable. Effective bits depend on ROM_FIX_NUM." group.long 0x210++0x7F line.long 0x0 "ROM_FIX_ADDR,Indicate ROM FIX address and jump instruction type." bitfld.long 0x0 28.--29. "JUMP_TYPE,Jump type. 0 - Jump fix thumb code; 1 - Jump fix ARM code; 2 - Jump fix AARCH64 code" "0,1,2,3" hexmask.long 0x0 0.--27. 1. "FIX_ADDR,Indicate ROM replace FIX address. Effective address depends on ROM size." line.long 0x4 "JUMP_ADDR,Indicate jump address." hexmask.long.tbyte 0x4 0.--23. 1. "ADDR,Indicate jump address." line.long 0x8 "ROM_FIX_ADDR,Indicate ROM FIX address and jump instruction type." bitfld.long 0x8 28.--29. "JUMP_TYPE,Jump type. 0 - Jump fix thumb code; 1 - Jump fix ARM code; 2 - Jump fix AARCH64 code" "0,1,2,3" hexmask.long 0x8 0.--27. 1. "FIX_ADDR,Indicate ROM replace FIX address. Effective address depends on ROM size." line.long 0xC "JUMP_ADDR,Indicate jump address." hexmask.long.tbyte 0xC 0.--23. 1. "ADDR,Indicate jump address." line.long 0x10 "ROM_FIX_ADDR,Indicate ROM FIX address and jump instruction type." bitfld.long 0x10 28.--29. "JUMP_TYPE,Jump type. 0 - Jump fix thumb code; 1 - Jump fix ARM code; 2 - Jump fix AARCH64 code" "0,1,2,3" hexmask.long 0x10 0.--27. 1. "FIX_ADDR,Indicate ROM replace FIX address. Effective address depends on ROM size." line.long 0x14 "JUMP_ADDR,Indicate jump address." hexmask.long.tbyte 0x14 0.--23. 1. "ADDR,Indicate jump address." line.long 0x18 "ROM_FIX_ADDR,Indicate ROM FIX address and jump instruction type." bitfld.long 0x18 28.--29. "JUMP_TYPE,Jump type. 0 - Jump fix thumb code; 1 - Jump fix ARM code; 2 - Jump fix AARCH64 code" "0,1,2,3" hexmask.long 0x18 0.--27. 1. "FIX_ADDR,Indicate ROM replace FIX address. Effective address depends on ROM size." line.long 0x1C "JUMP_ADDR,Indicate jump address." hexmask.long.tbyte 0x1C 0.--23. 1. "ADDR,Indicate jump address." line.long 0x20 "ROM_FIX_ADDR,Indicate ROM FIX address and jump instruction type." bitfld.long 0x20 28.--29. "JUMP_TYPE,Jump type. 0 - Jump fix thumb code; 1 - Jump fix ARM code; 2 - Jump fix AARCH64 code" "0,1,2,3" hexmask.long 0x20 0.--27. 1. "FIX_ADDR,Indicate ROM replace FIX address. Effective address depends on ROM size." line.long 0x24 "JUMP_ADDR,Indicate jump address." hexmask.long.tbyte 0x24 0.--23. 1. "ADDR,Indicate jump address." line.long 0x28 "ROM_FIX_ADDR,Indicate ROM FIX address and jump instruction type." bitfld.long 0x28 28.--29. "JUMP_TYPE,Jump type. 0 - Jump fix thumb code; 1 - Jump fix ARM code; 2 - Jump fix AARCH64 code" "0,1,2,3" hexmask.long 0x28 0.--27. 1. "FIX_ADDR,Indicate ROM replace FIX address. Effective address depends on ROM size." line.long 0x2C "JUMP_ADDR,Indicate jump address." hexmask.long.tbyte 0x2C 0.--23. 1. "ADDR,Indicate jump address." line.long 0x30 "ROM_FIX_ADDR,Indicate ROM FIX address and jump instruction type." bitfld.long 0x30 28.--29. "JUMP_TYPE,Jump type. 0 - Jump fix thumb code; 1 - Jump fix ARM code; 2 - Jump fix AARCH64 code" "0,1,2,3" hexmask.long 0x30 0.--27. 1. "FIX_ADDR,Indicate ROM replace FIX address. Effective address depends on ROM size." line.long 0x34 "JUMP_ADDR,Indicate jump address." hexmask.long.tbyte 0x34 0.--23. 1. "ADDR,Indicate jump address." line.long 0x38 "ROM_FIX_ADDR,Indicate ROM FIX address and jump instruction type." bitfld.long 0x38 28.--29. "JUMP_TYPE,Jump type. 0 - Jump fix thumb code; 1 - Jump fix ARM code; 2 - Jump fix AARCH64 code" "0,1,2,3" hexmask.long 0x38 0.--27. 1. "FIX_ADDR,Indicate ROM replace FIX address. Effective address depends on ROM size." line.long 0x3C "JUMP_ADDR,Indicate jump address." hexmask.long.tbyte 0x3C 0.--23. 1. "ADDR,Indicate jump address." line.long 0x40 "ROM_FIX_ADDR,Indicate ROM FIX address and jump instruction type." bitfld.long 0x40 28.--29. "JUMP_TYPE,Jump type. 0 - Jump fix thumb code; 1 - Jump fix ARM code; 2 - Jump fix AARCH64 code" "0,1,2,3" hexmask.long 0x40 0.--27. 1. "FIX_ADDR,Indicate ROM replace FIX address. Effective address depends on ROM size." line.long 0x44 "JUMP_ADDR,Indicate jump address." hexmask.long.tbyte 0x44 0.--23. 1. "ADDR,Indicate jump address." line.long 0x48 "ROM_FIX_ADDR,Indicate ROM FIX address and jump instruction type." bitfld.long 0x48 28.--29. "JUMP_TYPE,Jump type. 0 - Jump fix thumb code; 1 - Jump fix ARM code; 2 - Jump fix AARCH64 code" "0,1,2,3" hexmask.long 0x48 0.--27. 1. "FIX_ADDR,Indicate ROM replace FIX address. Effective address depends on ROM size." line.long 0x4C "JUMP_ADDR,Indicate jump address." hexmask.long.tbyte 0x4C 0.--23. 1. "ADDR,Indicate jump address." line.long 0x50 "ROM_FIX_ADDR,Indicate ROM FIX address and jump instruction type." bitfld.long 0x50 28.--29. "JUMP_TYPE,Jump type. 0 - Jump fix thumb code; 1 - Jump fix ARM code; 2 - Jump fix AARCH64 code" "0,1,2,3" hexmask.long 0x50 0.--27. 1. "FIX_ADDR,Indicate ROM replace FIX address. Effective address depends on ROM size." line.long 0x54 "JUMP_ADDR,Indicate jump address." hexmask.long.tbyte 0x54 0.--23. 1. "ADDR,Indicate jump address." line.long 0x58 "ROM_FIX_ADDR,Indicate ROM FIX address and jump instruction type." bitfld.long 0x58 28.--29. "JUMP_TYPE,Jump type. 0 - Jump fix thumb code; 1 - Jump fix ARM code; 2 - Jump fix AARCH64 code" "0,1,2,3" hexmask.long 0x58 0.--27. 1. "FIX_ADDR,Indicate ROM replace FIX address. Effective address depends on ROM size." line.long 0x5C "JUMP_ADDR,Indicate jump address." hexmask.long.tbyte 0x5C 0.--23. 1. "ADDR,Indicate jump address." line.long 0x60 "ROM_FIX_ADDR,Indicate ROM FIX address and jump instruction type." bitfld.long 0x60 28.--29. "JUMP_TYPE,Jump type. 0 - Jump fix thumb code; 1 - Jump fix ARM code; 2 - Jump fix AARCH64 code" "0,1,2,3" hexmask.long 0x60 0.--27. 1. "FIX_ADDR,Indicate ROM replace FIX address. Effective address depends on ROM size." line.long 0x64 "JUMP_ADDR,Indicate jump address." hexmask.long.tbyte 0x64 0.--23. 1. "ADDR,Indicate jump address." line.long 0x68 "ROM_FIX_ADDR,Indicate ROM FIX address and jump instruction type." bitfld.long 0x68 28.--29. "JUMP_TYPE,Jump type. 0 - Jump fix thumb code; 1 - Jump fix ARM code; 2 - Jump fix AARCH64 code" "0,1,2,3" hexmask.long 0x68 0.--27. 1. "FIX_ADDR,Indicate ROM replace FIX address. Effective address depends on ROM size." line.long 0x6C "JUMP_ADDR,Indicate jump address." hexmask.long.tbyte 0x6C 0.--23. 1. "ADDR,Indicate jump address." line.long 0x70 "ROM_FIX_ADDR,Indicate ROM FIX address and jump instruction type." bitfld.long 0x70 28.--29. "JUMP_TYPE,Jump type. 0 - Jump fix thumb code; 1 - Jump fix ARM code; 2 - Jump fix AARCH64 code" "0,1,2,3" hexmask.long 0x70 0.--27. 1. "FIX_ADDR,Indicate ROM replace FIX address. Effective address depends on ROM size." line.long 0x74 "JUMP_ADDR,Indicate jump address." hexmask.long.tbyte 0x74 0.--23. 1. "ADDR,Indicate jump address." line.long 0x78 "ROM_FIX_ADDR,Indicate ROM FIX address and jump instruction type." bitfld.long 0x78 28.--29. "JUMP_TYPE,Jump type. 0 - Jump fix thumb code; 1 - Jump fix ARM code; 2 - Jump fix AARCH64 code" "0,1,2,3" hexmask.long 0x78 0.--27. 1. "FIX_ADDR,Indicate ROM replace FIX address. Effective address depends on ROM size." line.long 0x7C "JUMP_ADDR,Indicate jump address." hexmask.long.tbyte 0x7C 0.--23. 1. "ADDR,Indicate jump address." group.long 0x400++0xFF line.long 0x0 "ROM_INJ,ROM injection code" hexmask.long 0x0 0.--31. 1. "CODE,ROM injection code" line.long 0x4 "ROM_INJ,ROM injection code" hexmask.long 0x4 0.--31. 1. "CODE,ROM injection code" line.long 0x8 "ROM_INJ,ROM injection code" hexmask.long 0x8 0.--31. 1. "CODE,ROM injection code" line.long 0xC "ROM_INJ,ROM injection code" hexmask.long 0xC 0.--31. 1. "CODE,ROM injection code" line.long 0x10 "ROM_INJ,ROM injection code" hexmask.long 0x10 0.--31. 1. "CODE,ROM injection code" line.long 0x14 "ROM_INJ,ROM injection code" hexmask.long 0x14 0.--31. 1. "CODE,ROM injection code" line.long 0x18 "ROM_INJ,ROM injection code" hexmask.long 0x18 0.--31. 1. "CODE,ROM injection code" line.long 0x1C "ROM_INJ,ROM injection code" hexmask.long 0x1C 0.--31. 1. "CODE,ROM injection code" line.long 0x20 "ROM_INJ,ROM injection code" hexmask.long 0x20 0.--31. 1. "CODE,ROM injection code" line.long 0x24 "ROM_INJ,ROM injection code" hexmask.long 0x24 0.--31. 1. "CODE,ROM injection code" line.long 0x28 "ROM_INJ,ROM injection code" hexmask.long 0x28 0.--31. 1. "CODE,ROM injection code" line.long 0x2C "ROM_INJ,ROM injection code" hexmask.long 0x2C 0.--31. 1. "CODE,ROM injection code" line.long 0x30 "ROM_INJ,ROM injection code" hexmask.long 0x30 0.--31. 1. "CODE,ROM injection code" line.long 0x34 "ROM_INJ,ROM injection code" hexmask.long 0x34 0.--31. 1. "CODE,ROM injection code" line.long 0x38 "ROM_INJ,ROM injection code" hexmask.long 0x38 0.--31. 1. "CODE,ROM injection code" line.long 0x3C "ROM_INJ,ROM injection code" hexmask.long 0x3C 0.--31. 1. "CODE,ROM injection code" line.long 0x40 "ROM_INJ,ROM injection code" hexmask.long 0x40 0.--31. 1. "CODE,ROM injection code" line.long 0x44 "ROM_INJ,ROM injection code" hexmask.long 0x44 0.--31. 1. "CODE,ROM injection code" line.long 0x48 "ROM_INJ,ROM injection code" hexmask.long 0x48 0.--31. 1. "CODE,ROM injection code" line.long 0x4C "ROM_INJ,ROM injection code" hexmask.long 0x4C 0.--31. 1. "CODE,ROM injection code" line.long 0x50 "ROM_INJ,ROM injection code" hexmask.long 0x50 0.--31. 1. "CODE,ROM injection code" line.long 0x54 "ROM_INJ,ROM injection code" hexmask.long 0x54 0.--31. 1. "CODE,ROM injection code" line.long 0x58 "ROM_INJ,ROM injection code" hexmask.long 0x58 0.--31. 1. "CODE,ROM injection code" line.long 0x5C "ROM_INJ,ROM injection code" hexmask.long 0x5C 0.--31. 1. "CODE,ROM injection code" line.long 0x60 "ROM_INJ,ROM injection code" hexmask.long 0x60 0.--31. 1. "CODE,ROM injection code" line.long 0x64 "ROM_INJ,ROM injection code" hexmask.long 0x64 0.--31. 1. "CODE,ROM injection code" line.long 0x68 "ROM_INJ,ROM injection code" hexmask.long 0x68 0.--31. 1. "CODE,ROM injection code" line.long 0x6C "ROM_INJ,ROM injection code" hexmask.long 0x6C 0.--31. 1. "CODE,ROM injection code" line.long 0x70 "ROM_INJ,ROM injection code" hexmask.long 0x70 0.--31. 1. "CODE,ROM injection code" line.long 0x74 "ROM_INJ,ROM injection code" hexmask.long 0x74 0.--31. 1. "CODE,ROM injection code" line.long 0x78 "ROM_INJ,ROM injection code" hexmask.long 0x78 0.--31. 1. "CODE,ROM injection code" line.long 0x7C "ROM_INJ,ROM injection code" hexmask.long 0x7C 0.--31. 1. "CODE,ROM injection code" line.long 0x80 "ROM_INJ,ROM injection code" hexmask.long 0x80 0.--31. 1. "CODE,ROM injection code" line.long 0x84 "ROM_INJ,ROM injection code" hexmask.long 0x84 0.--31. 1. "CODE,ROM injection code" line.long 0x88 "ROM_INJ,ROM injection code" hexmask.long 0x88 0.--31. 1. "CODE,ROM injection code" line.long 0x8C "ROM_INJ,ROM injection code" hexmask.long 0x8C 0.--31. 1. "CODE,ROM injection code" line.long 0x90 "ROM_INJ,ROM injection code" hexmask.long 0x90 0.--31. 1. "CODE,ROM injection code" line.long 0x94 "ROM_INJ,ROM injection code" hexmask.long 0x94 0.--31. 1. "CODE,ROM injection code" line.long 0x98 "ROM_INJ,ROM injection code" hexmask.long 0x98 0.--31. 1. "CODE,ROM injection code" line.long 0x9C "ROM_INJ,ROM injection code" hexmask.long 0x9C 0.--31. 1. "CODE,ROM injection code" line.long 0xA0 "ROM_INJ,ROM injection code" hexmask.long 0xA0 0.--31. 1. "CODE,ROM injection code" line.long 0xA4 "ROM_INJ,ROM injection code" hexmask.long 0xA4 0.--31. 1. "CODE,ROM injection code" line.long 0xA8 "ROM_INJ,ROM injection code" hexmask.long 0xA8 0.--31. 1. "CODE,ROM injection code" line.long 0xAC "ROM_INJ,ROM injection code" hexmask.long 0xAC 0.--31. 1. "CODE,ROM injection code" line.long 0xB0 "ROM_INJ,ROM injection code" hexmask.long 0xB0 0.--31. 1. "CODE,ROM injection code" line.long 0xB4 "ROM_INJ,ROM injection code" hexmask.long 0xB4 0.--31. 1. "CODE,ROM injection code" line.long 0xB8 "ROM_INJ,ROM injection code" hexmask.long 0xB8 0.--31. 1. "CODE,ROM injection code" line.long 0xBC "ROM_INJ,ROM injection code" hexmask.long 0xBC 0.--31. 1. "CODE,ROM injection code" line.long 0xC0 "ROM_INJ,ROM injection code" hexmask.long 0xC0 0.--31. 1. "CODE,ROM injection code" line.long 0xC4 "ROM_INJ,ROM injection code" hexmask.long 0xC4 0.--31. 1. "CODE,ROM injection code" line.long 0xC8 "ROM_INJ,ROM injection code" hexmask.long 0xC8 0.--31. 1. "CODE,ROM injection code" line.long 0xCC "ROM_INJ,ROM injection code" hexmask.long 0xCC 0.--31. 1. "CODE,ROM injection code" line.long 0xD0 "ROM_INJ,ROM injection code" hexmask.long 0xD0 0.--31. 1. "CODE,ROM injection code" line.long 0xD4 "ROM_INJ,ROM injection code" hexmask.long 0xD4 0.--31. 1. "CODE,ROM injection code" line.long 0xD8 "ROM_INJ,ROM injection code" hexmask.long 0xD8 0.--31. 1. "CODE,ROM injection code" line.long 0xDC "ROM_INJ,ROM injection code" hexmask.long 0xDC 0.--31. 1. "CODE,ROM injection code" line.long 0xE0 "ROM_INJ,ROM injection code" hexmask.long 0xE0 0.--31. 1. "CODE,ROM injection code" line.long 0xE4 "ROM_INJ,ROM injection code" hexmask.long 0xE4 0.--31. 1. "CODE,ROM injection code" line.long 0xE8 "ROM_INJ,ROM injection code" hexmask.long 0xE8 0.--31. 1. "CODE,ROM injection code" line.long 0xEC "ROM_INJ,ROM injection code" hexmask.long 0xEC 0.--31. 1. "CODE,ROM injection code" line.long 0xF0 "ROM_INJ,ROM injection code" hexmask.long 0xF0 0.--31. 1. "CODE,ROM injection code" line.long 0xF4 "ROM_INJ,ROM injection code" hexmask.long 0xF4 0.--31. 1. "CODE,ROM injection code" line.long 0xF8 "ROM_INJ,ROM injection code" hexmask.long 0xF8 0.--31. 1. "CODE,ROM injection code" line.long 0xFC "ROM_INJ,ROM injection code" hexmask.long 0xFC 0.--31. 1. "CODE,ROM injection code" tree.end tree "ROMC_AP" base ad:0x306F0000 group.long 0x0++0x23 line.long 0x0 "MEM_ERR_INT_STATUS,Memory ECC error Interrupt status" bitfld.long 0x0 2. "RDATA_FATAL,It can report ECC correction logic error and protect rdata internal path." "0,1" bitfld.long 0x0 1. "MUL_ERR,Indicate double bit errors are detected." "0,1" bitfld.long 0x0 0. "SIG_ERR,Indicate single bit error is detected." "0,1" line.long 0x4 "MEM_ERR_INT_STA_EN,Memory ECC error Interrupt status enable" bitfld.long 0x4 2. "RDATA_FATAL_EN,Rdata fatal interrupt status enable" "0,1" bitfld.long 0x4 1. "MUL_ERR_EN,Multiple bit error interrupt status enable." "0,1" bitfld.long 0x4 0. "SIG_ERR_EN,Single bit error interrupt status enable." "0,1" line.long 0x8 "MEM_ERR_INT_SIG_EN,Memory ECC Interrupt signal enable" bitfld.long 0x8 2. "RDATA_FATAL_EN,Rdata fatal interrupt signal enable." "0,1" bitfld.long 0x8 1. "MUL_ERR_EN,Multiple bits errors interrupt signal enable." "0,1" bitfld.long 0x8 0. "SIG_ERR_EN,Single bit error interrupt signal enable." "0,1" line.long 0xC "UNCERR_INT_STA,AXI bus uncorrectable error interrupt status" bitfld.long 0xC 20. "RREADY,Uncorrectable error for RREADY" "0,1" bitfld.long 0xC 5. "ARVALID,Uncorrectable error for ARVALID" "0,1" newline bitfld.long 0xC 3. "ARCTL1,Uncorrectable error for ARCTL1(ARLOCK ARBURST ARSIZE ARLEN)" "0,1" bitfld.long 0xC 1. "ARADDR,Uncorrectable error for ARADDR" "0,1" bitfld.long 0xC 0. "ARID,Uncorrectable error for ARID" "0,1" line.long 0x10 "UNCERR_INT_STA_EN,AXI bus uncorrectable error interrupt status enable" bitfld.long 0x10 20. "RREADY,Statusl enable for RREADY" "0,1" bitfld.long 0x10 5. "ARVALID,Status enable for ARVALID" "0,1" newline bitfld.long 0x10 3. "ARCTL1,Status enable for ARCTL1(ARLOCK ARBURST ARSIZE ARLEN)" "0,1" bitfld.long 0x10 1. "ARADDR,Status enable for ARADDR" "0,1" bitfld.long 0x10 0. "ARID,Status enable for ARID" "0,1" line.long 0x14 "UNCERR_INT_SIG_EN,AXI bus uncorrectable error interrupt signal enable" bitfld.long 0x14 20. "RREADY,Signal enable for RREADY" "0,1" bitfld.long 0x14 5. "ARVALID,Signal enable for ARVALID" "0,1" newline bitfld.long 0x14 3. "ARCTL1,Signal enable for ARCTL1(ARLOCK ARBURST ARSIZE ARLEN)" "0,1" bitfld.long 0x14 1. "ARADDR,Signal enable for ARADDR" "0,1" bitfld.long 0x14 0. "ARID,Signal enable for ARID" "0,1" line.long 0x18 "CORERR_INT_STA,AXI bus correctable error interrupt status" bitfld.long 0x18 0. "ARADDR,Correctable error for ARADDR" "0,1" line.long 0x1C "CORERR_INT_STA_EN,AXI bus correctable error interrupt status enable" bitfld.long 0x1C 0. "ARADDR,Status enable for ARADDR" "0,1" line.long 0x20 "CORERR_INT_SIG_EN,AXI bus correctable error interrupt signal enable" bitfld.long 0x20 0. "ARADDR,Signal enable for ARADDR" "0,1" group.long 0x30++0x7 line.long 0x0 "FWEN,Firewall enable" bitfld.long 0x0 31. "LOCK,Lock FWEM register bit and itself" "0,1" bitfld.long 0x0 0. "FWEN,Firewall enable. Enable master ID check for all the apb access." "0,1" line.long 0x4 "STICKY_REG,Sticky register" bitfld.long 0x4 31. "LOCK_15,Lock lower register bit and itself" "0,1" bitfld.long 0x4 30. "LOCK_14,Lock lower register bit and itself" "0,1" bitfld.long 0x4 29. "LOCK_13,Lock lower register bit and itself" "0,1" bitfld.long 0x4 28. "LOCK_12,Lock lower register bit and itself" "0,1" bitfld.long 0x4 27. "LOCK_11,Lock lower register bit and itself" "0,1" newline bitfld.long 0x4 26. "LOCK_10,Lock lower register bit and itself" "0,1" bitfld.long 0x4 25. "LOCK_9,Lock lower register bit and itself" "0,1" bitfld.long 0x4 24. "LOCK_8,Lock lower register bit and itself" "0,1" bitfld.long 0x4 23. "LOCK_7,Lock lower register bit and itself" "0,1" bitfld.long 0x4 22. "LOCK_6,Lock lower register bit and itself" "0,1" newline bitfld.long 0x4 21. "LOCK_5,Lock lower register bit and itself" "0,1" bitfld.long 0x4 20. "LOCK_4,Lock lower register bit and itself" "0,1" bitfld.long 0x4 19. "LOCK_3,Lock lower register bit and itself" "0,1" bitfld.long 0x4 18. "LOCK_2,Lock lower register bit and itself" "0,1" bitfld.long 0x4 17. "LOCK_1,Lock lower register bit and itself" "0,1" newline bitfld.long 0x4 16. "LOCK_0,Lock lower register bit and itself" "0,1" bitfld.long 0x4 15. "REG_15,Register" "0,1" bitfld.long 0x4 14. "REG_14,Register" "0,1" bitfld.long 0x4 13. "REG_13,Register" "0,1" bitfld.long 0x4 12. "REG_12,Register" "0,1" newline bitfld.long 0x4 11. "REG_11,Register" "0,1" bitfld.long 0x4 10. "REG_10,Register" "0,1" bitfld.long 0x4 9. "REG_9,Register" "0,1" bitfld.long 0x4 8. "REG_8,Register" "0,1" bitfld.long 0x4 7. "REG_7,Register" "0,1" newline bitfld.long 0x4 6. "REG_6,Register" "0,1" bitfld.long 0x4 5. "REG_5,Register" "0,1" bitfld.long 0x4 4. "REG_4,Register" "0,1" bitfld.long 0x4 3. "REG_3,Register" "0,1" bitfld.long 0x4 2. "REG_2,Register" "0,1" newline bitfld.long 0x4 1. "REG_1,Register" "0,1" bitfld.long 0x4 0. "REG_0,Register" "0,1" rgroup.long 0x40++0x27 line.long 0x0 "SIG_ERR_ADDR,Store access address for first single bit error." hexmask.long 0x0 0.--31. 1. "ADDR,Error addr" line.long 0x4 "SIG_ERR_DATA_31_0,Store Error data for first single bit error" hexmask.long 0x4 0.--31. 1. "DATA,Error data" line.long 0x8 "SIG_ERR_DATA_63_32,Store Error data for first single bit error" hexmask.long 0x8 0.--31. 1. "DATA,Error data" line.long 0xC "SIG_ERR_DATA_95_64,Store Error data for first single bit error" hexmask.long 0xC 0.--31. 1. "DATA,Error data" line.long 0x10 "SIG_ERR_DATA_127_96,Store Error data for first single bit error" hexmask.long 0x10 0.--31. 1. "DATA,Error data" line.long 0x14 "MUL_ERR_ADDR,Store access address for multiple bits error." hexmask.long 0x14 0.--31. 1. "ADDR,Error address" line.long 0x18 "MUL_ERR_DATA_31_0,Store Error data for first multiple bits error" hexmask.long 0x18 0.--31. 1. "DATA,Error data" line.long 0x1C "MUL_ERR_DATA_63_32,Store Error data for first multiple bits error" hexmask.long 0x1C 0.--31. 1. "DATA,Error data" line.long 0x20 "MUL_ERR_DATA_95_64,Store Error data for first multiple bits error" hexmask.long 0x20 0.--31. 1. "DATA,Error data" line.long 0x24 "MUL_ERR_DATA_127_96,Store Error data for first multiple bits error" hexmask.long 0x24 0.--31. 1. "DATA,Error data" group.long 0x80++0x3 line.long 0x0 "ROM_DIS,ROM code disable" bitfld.long 0x0 0. "DIS,When this bit is set ROM code read and ROM fix register access are disable. Once this bit is set it is always set unless POR reset." "0,1" group.long 0x100++0x13 line.long 0x0 "RDATA_31_0_INJ,Error injection on rdata" hexmask.long 0x0 0.--31. 1. "RDATA_INJ,Error injection on rdata" line.long 0x4 "RDATA_63_32_INJ,Error injection on rdata" hexmask.long 0x4 0.--31. 1. "RDATA_INJ,Error injection on rdata" line.long 0x8 "RDATA_95_64_INJ,Error injection on rdata" hexmask.long 0x8 0.--31. 1. "RDATA_INJ,Error injection on rdata" line.long 0xC "RDATA_127_96_INJ,Error injection on rdata" hexmask.long 0xC 0.--31. 1. "RDATA_INJ,Error injection on rdata" line.long 0x10 "ECC_INJ,Error injection on read ecc code" hexmask.long.byte 0x10 8.--15. 1. "ECC_INJ1,Error injection on 8 ecc code for high 64 bits wdata" hexmask.long.byte 0x10 0.--7. 1. "ECC_INJ0,Error injection on 8 ecc code for low 64 bits wdata" group.long 0x120++0x13 line.long 0x0 "RD_DATA_31_0_INJ,Error injection on rdata after ECC correction" hexmask.long 0x0 0.--31. 1. "RDATA_INJ,Error injection on rdata" line.long 0x4 "RD_DATA_63_32_INJ,Error injection on rdata after ECC correction" hexmask.long 0x4 0.--31. 1. "RDATA_INJ,Error injection on rdata" line.long 0x8 "RD_DATA_95_64_INJ,Error injection on rdata after ECC correction" hexmask.long 0x8 0.--31. 1. "RDATA_INJ,Error injection on rdata" line.long 0xC "RD_DATA_127_96_INJ,Error injection on rdata after ECC correction" hexmask.long 0xC 0.--31. 1. "RDATA_INJ,Error injection on rdata" line.long 0x10 "RD_ECC_INJ,Error injection on read ecc code after ECC correction" hexmask.long.byte 0x10 8.--15. 1. "ECC_INJ1,Error injection on 8 ecc code for high 64 bits wdata" hexmask.long.byte 0x10 0.--7. 1. "ECC_INJ0,Error injection on 8 ecc code for low 64 bits wdata" rgroup.long 0x200++0x3 line.long 0x0 "ROM_FIX_NUM,Indicate ROM fix numbers and RTL version" hexmask.long.byte 0x0 24.--31. 1. "MAJOR_VERSION,ROM FIX major version" hexmask.long.byte 0x0 16.--23. 1. "MINOR_VERSION,ROM fix minor version" hexmask.long.byte 0x0 0.--7. 1. "FIX_NUM,Indicate ROM fix numbers" group.long 0x204++0x7 line.long 0x0 "ROM_FIX_CTRL,ROM fix feature enable and ROM fix registers lock" bitfld.long 0x0 1. "LOCK,When this bit is set all the ROM fix registers can not be written." "0,1" bitfld.long 0x0 0. "GLB_EN,enable ROM replace fix feature" "0,1" line.long 0x4 "ROM_FIX_EN,Indicate which ROM fix is enable" hexmask.long 0x4 0.--31. 1. "FIX_EN,Indicate which ROM replace fix is enable. Effective bits depend on ROM_FIX_NUM." group.long 0x210++0x7F line.long 0x0 "ROM_FIX_ADDR,Indicate ROM FIX address and jump instruction type." bitfld.long 0x0 28.--29. "JUMP_TYPE,Jump type. 0 - Jump fix thumb code; 1 - Jump fix ARM code; 2 - Jump fix AARCH64 code" "0,1,2,3" hexmask.long 0x0 0.--27. 1. "FIX_ADDR,Indicate ROM replace FIX address. Effective address depends on ROM size." line.long 0x4 "JUMP_ADDR,Indicate jump address." hexmask.long.tbyte 0x4 0.--23. 1. "ADDR,Indicate jump address." line.long 0x8 "ROM_FIX_ADDR,Indicate ROM FIX address and jump instruction type." bitfld.long 0x8 28.--29. "JUMP_TYPE,Jump type. 0 - Jump fix thumb code; 1 - Jump fix ARM code; 2 - Jump fix AARCH64 code" "0,1,2,3" hexmask.long 0x8 0.--27. 1. "FIX_ADDR,Indicate ROM replace FIX address. Effective address depends on ROM size." line.long 0xC "JUMP_ADDR,Indicate jump address." hexmask.long.tbyte 0xC 0.--23. 1. "ADDR,Indicate jump address." line.long 0x10 "ROM_FIX_ADDR,Indicate ROM FIX address and jump instruction type." bitfld.long 0x10 28.--29. "JUMP_TYPE,Jump type. 0 - Jump fix thumb code; 1 - Jump fix ARM code; 2 - Jump fix AARCH64 code" "0,1,2,3" hexmask.long 0x10 0.--27. 1. "FIX_ADDR,Indicate ROM replace FIX address. Effective address depends on ROM size." line.long 0x14 "JUMP_ADDR,Indicate jump address." hexmask.long.tbyte 0x14 0.--23. 1. "ADDR,Indicate jump address." line.long 0x18 "ROM_FIX_ADDR,Indicate ROM FIX address and jump instruction type." bitfld.long 0x18 28.--29. "JUMP_TYPE,Jump type. 0 - Jump fix thumb code; 1 - Jump fix ARM code; 2 - Jump fix AARCH64 code" "0,1,2,3" hexmask.long 0x18 0.--27. 1. "FIX_ADDR,Indicate ROM replace FIX address. Effective address depends on ROM size." line.long 0x1C "JUMP_ADDR,Indicate jump address." hexmask.long.tbyte 0x1C 0.--23. 1. "ADDR,Indicate jump address." line.long 0x20 "ROM_FIX_ADDR,Indicate ROM FIX address and jump instruction type." bitfld.long 0x20 28.--29. "JUMP_TYPE,Jump type. 0 - Jump fix thumb code; 1 - Jump fix ARM code; 2 - Jump fix AARCH64 code" "0,1,2,3" hexmask.long 0x20 0.--27. 1. "FIX_ADDR,Indicate ROM replace FIX address. Effective address depends on ROM size." line.long 0x24 "JUMP_ADDR,Indicate jump address." hexmask.long.tbyte 0x24 0.--23. 1. "ADDR,Indicate jump address." line.long 0x28 "ROM_FIX_ADDR,Indicate ROM FIX address and jump instruction type." bitfld.long 0x28 28.--29. "JUMP_TYPE,Jump type. 0 - Jump fix thumb code; 1 - Jump fix ARM code; 2 - Jump fix AARCH64 code" "0,1,2,3" hexmask.long 0x28 0.--27. 1. "FIX_ADDR,Indicate ROM replace FIX address. Effective address depends on ROM size." line.long 0x2C "JUMP_ADDR,Indicate jump address." hexmask.long.tbyte 0x2C 0.--23. 1. "ADDR,Indicate jump address." line.long 0x30 "ROM_FIX_ADDR,Indicate ROM FIX address and jump instruction type." bitfld.long 0x30 28.--29. "JUMP_TYPE,Jump type. 0 - Jump fix thumb code; 1 - Jump fix ARM code; 2 - Jump fix AARCH64 code" "0,1,2,3" hexmask.long 0x30 0.--27. 1. "FIX_ADDR,Indicate ROM replace FIX address. Effective address depends on ROM size." line.long 0x34 "JUMP_ADDR,Indicate jump address." hexmask.long.tbyte 0x34 0.--23. 1. "ADDR,Indicate jump address." line.long 0x38 "ROM_FIX_ADDR,Indicate ROM FIX address and jump instruction type." bitfld.long 0x38 28.--29. "JUMP_TYPE,Jump type. 0 - Jump fix thumb code; 1 - Jump fix ARM code; 2 - Jump fix AARCH64 code" "0,1,2,3" hexmask.long 0x38 0.--27. 1. "FIX_ADDR,Indicate ROM replace FIX address. Effective address depends on ROM size." line.long 0x3C "JUMP_ADDR,Indicate jump address." hexmask.long.tbyte 0x3C 0.--23. 1. "ADDR,Indicate jump address." line.long 0x40 "ROM_FIX_ADDR,Indicate ROM FIX address and jump instruction type." bitfld.long 0x40 28.--29. "JUMP_TYPE,Jump type. 0 - Jump fix thumb code; 1 - Jump fix ARM code; 2 - Jump fix AARCH64 code" "0,1,2,3" hexmask.long 0x40 0.--27. 1. "FIX_ADDR,Indicate ROM replace FIX address. Effective address depends on ROM size." line.long 0x44 "JUMP_ADDR,Indicate jump address." hexmask.long.tbyte 0x44 0.--23. 1. "ADDR,Indicate jump address." line.long 0x48 "ROM_FIX_ADDR,Indicate ROM FIX address and jump instruction type." bitfld.long 0x48 28.--29. "JUMP_TYPE,Jump type. 0 - Jump fix thumb code; 1 - Jump fix ARM code; 2 - Jump fix AARCH64 code" "0,1,2,3" hexmask.long 0x48 0.--27. 1. "FIX_ADDR,Indicate ROM replace FIX address. Effective address depends on ROM size." line.long 0x4C "JUMP_ADDR,Indicate jump address." hexmask.long.tbyte 0x4C 0.--23. 1. "ADDR,Indicate jump address." line.long 0x50 "ROM_FIX_ADDR,Indicate ROM FIX address and jump instruction type." bitfld.long 0x50 28.--29. "JUMP_TYPE,Jump type. 0 - Jump fix thumb code; 1 - Jump fix ARM code; 2 - Jump fix AARCH64 code" "0,1,2,3" hexmask.long 0x50 0.--27. 1. "FIX_ADDR,Indicate ROM replace FIX address. Effective address depends on ROM size." line.long 0x54 "JUMP_ADDR,Indicate jump address." hexmask.long.tbyte 0x54 0.--23. 1. "ADDR,Indicate jump address." line.long 0x58 "ROM_FIX_ADDR,Indicate ROM FIX address and jump instruction type." bitfld.long 0x58 28.--29. "JUMP_TYPE,Jump type. 0 - Jump fix thumb code; 1 - Jump fix ARM code; 2 - Jump fix AARCH64 code" "0,1,2,3" hexmask.long 0x58 0.--27. 1. "FIX_ADDR,Indicate ROM replace FIX address. Effective address depends on ROM size." line.long 0x5C "JUMP_ADDR,Indicate jump address." hexmask.long.tbyte 0x5C 0.--23. 1. "ADDR,Indicate jump address." line.long 0x60 "ROM_FIX_ADDR,Indicate ROM FIX address and jump instruction type." bitfld.long 0x60 28.--29. "JUMP_TYPE,Jump type. 0 - Jump fix thumb code; 1 - Jump fix ARM code; 2 - Jump fix AARCH64 code" "0,1,2,3" hexmask.long 0x60 0.--27. 1. "FIX_ADDR,Indicate ROM replace FIX address. Effective address depends on ROM size." line.long 0x64 "JUMP_ADDR,Indicate jump address." hexmask.long.tbyte 0x64 0.--23. 1. "ADDR,Indicate jump address." line.long 0x68 "ROM_FIX_ADDR,Indicate ROM FIX address and jump instruction type." bitfld.long 0x68 28.--29. "JUMP_TYPE,Jump type. 0 - Jump fix thumb code; 1 - Jump fix ARM code; 2 - Jump fix AARCH64 code" "0,1,2,3" hexmask.long 0x68 0.--27. 1. "FIX_ADDR,Indicate ROM replace FIX address. Effective address depends on ROM size." line.long 0x6C "JUMP_ADDR,Indicate jump address." hexmask.long.tbyte 0x6C 0.--23. 1. "ADDR,Indicate jump address." line.long 0x70 "ROM_FIX_ADDR,Indicate ROM FIX address and jump instruction type." bitfld.long 0x70 28.--29. "JUMP_TYPE,Jump type. 0 - Jump fix thumb code; 1 - Jump fix ARM code; 2 - Jump fix AARCH64 code" "0,1,2,3" hexmask.long 0x70 0.--27. 1. "FIX_ADDR,Indicate ROM replace FIX address. Effective address depends on ROM size." line.long 0x74 "JUMP_ADDR,Indicate jump address." hexmask.long.tbyte 0x74 0.--23. 1. "ADDR,Indicate jump address." line.long 0x78 "ROM_FIX_ADDR,Indicate ROM FIX address and jump instruction type." bitfld.long 0x78 28.--29. "JUMP_TYPE,Jump type. 0 - Jump fix thumb code; 1 - Jump fix ARM code; 2 - Jump fix AARCH64 code" "0,1,2,3" hexmask.long 0x78 0.--27. 1. "FIX_ADDR,Indicate ROM replace FIX address. Effective address depends on ROM size." line.long 0x7C "JUMP_ADDR,Indicate jump address." hexmask.long.tbyte 0x7C 0.--23. 1. "ADDR,Indicate jump address." group.long 0x400++0xFF line.long 0x0 "ROM_INJ,ROM injection code" hexmask.long 0x0 0.--31. 1. "CODE,ROM injection code" line.long 0x4 "ROM_INJ,ROM injection code" hexmask.long 0x4 0.--31. 1. "CODE,ROM injection code" line.long 0x8 "ROM_INJ,ROM injection code" hexmask.long 0x8 0.--31. 1. "CODE,ROM injection code" line.long 0xC "ROM_INJ,ROM injection code" hexmask.long 0xC 0.--31. 1. "CODE,ROM injection code" line.long 0x10 "ROM_INJ,ROM injection code" hexmask.long 0x10 0.--31. 1. "CODE,ROM injection code" line.long 0x14 "ROM_INJ,ROM injection code" hexmask.long 0x14 0.--31. 1. "CODE,ROM injection code" line.long 0x18 "ROM_INJ,ROM injection code" hexmask.long 0x18 0.--31. 1. "CODE,ROM injection code" line.long 0x1C "ROM_INJ,ROM injection code" hexmask.long 0x1C 0.--31. 1. "CODE,ROM injection code" line.long 0x20 "ROM_INJ,ROM injection code" hexmask.long 0x20 0.--31. 1. "CODE,ROM injection code" line.long 0x24 "ROM_INJ,ROM injection code" hexmask.long 0x24 0.--31. 1. "CODE,ROM injection code" line.long 0x28 "ROM_INJ,ROM injection code" hexmask.long 0x28 0.--31. 1. "CODE,ROM injection code" line.long 0x2C "ROM_INJ,ROM injection code" hexmask.long 0x2C 0.--31. 1. "CODE,ROM injection code" line.long 0x30 "ROM_INJ,ROM injection code" hexmask.long 0x30 0.--31. 1. "CODE,ROM injection code" line.long 0x34 "ROM_INJ,ROM injection code" hexmask.long 0x34 0.--31. 1. "CODE,ROM injection code" line.long 0x38 "ROM_INJ,ROM injection code" hexmask.long 0x38 0.--31. 1. "CODE,ROM injection code" line.long 0x3C "ROM_INJ,ROM injection code" hexmask.long 0x3C 0.--31. 1. "CODE,ROM injection code" line.long 0x40 "ROM_INJ,ROM injection code" hexmask.long 0x40 0.--31. 1. "CODE,ROM injection code" line.long 0x44 "ROM_INJ,ROM injection code" hexmask.long 0x44 0.--31. 1. "CODE,ROM injection code" line.long 0x48 "ROM_INJ,ROM injection code" hexmask.long 0x48 0.--31. 1. "CODE,ROM injection code" line.long 0x4C "ROM_INJ,ROM injection code" hexmask.long 0x4C 0.--31. 1. "CODE,ROM injection code" line.long 0x50 "ROM_INJ,ROM injection code" hexmask.long 0x50 0.--31. 1. "CODE,ROM injection code" line.long 0x54 "ROM_INJ,ROM injection code" hexmask.long 0x54 0.--31. 1. "CODE,ROM injection code" line.long 0x58 "ROM_INJ,ROM injection code" hexmask.long 0x58 0.--31. 1. "CODE,ROM injection code" line.long 0x5C "ROM_INJ,ROM injection code" hexmask.long 0x5C 0.--31. 1. "CODE,ROM injection code" line.long 0x60 "ROM_INJ,ROM injection code" hexmask.long 0x60 0.--31. 1. "CODE,ROM injection code" line.long 0x64 "ROM_INJ,ROM injection code" hexmask.long 0x64 0.--31. 1. "CODE,ROM injection code" line.long 0x68 "ROM_INJ,ROM injection code" hexmask.long 0x68 0.--31. 1. "CODE,ROM injection code" line.long 0x6C "ROM_INJ,ROM injection code" hexmask.long 0x6C 0.--31. 1. "CODE,ROM injection code" line.long 0x70 "ROM_INJ,ROM injection code" hexmask.long 0x70 0.--31. 1. "CODE,ROM injection code" line.long 0x74 "ROM_INJ,ROM injection code" hexmask.long 0x74 0.--31. 1. "CODE,ROM injection code" line.long 0x78 "ROM_INJ,ROM injection code" hexmask.long 0x78 0.--31. 1. "CODE,ROM injection code" line.long 0x7C "ROM_INJ,ROM injection code" hexmask.long 0x7C 0.--31. 1. "CODE,ROM injection code" line.long 0x80 "ROM_INJ,ROM injection code" hexmask.long 0x80 0.--31. 1. "CODE,ROM injection code" line.long 0x84 "ROM_INJ,ROM injection code" hexmask.long 0x84 0.--31. 1. "CODE,ROM injection code" line.long 0x88 "ROM_INJ,ROM injection code" hexmask.long 0x88 0.--31. 1. "CODE,ROM injection code" line.long 0x8C "ROM_INJ,ROM injection code" hexmask.long 0x8C 0.--31. 1. "CODE,ROM injection code" line.long 0x90 "ROM_INJ,ROM injection code" hexmask.long 0x90 0.--31. 1. "CODE,ROM injection code" line.long 0x94 "ROM_INJ,ROM injection code" hexmask.long 0x94 0.--31. 1. "CODE,ROM injection code" line.long 0x98 "ROM_INJ,ROM injection code" hexmask.long 0x98 0.--31. 1. "CODE,ROM injection code" line.long 0x9C "ROM_INJ,ROM injection code" hexmask.long 0x9C 0.--31. 1. "CODE,ROM injection code" line.long 0xA0 "ROM_INJ,ROM injection code" hexmask.long 0xA0 0.--31. 1. "CODE,ROM injection code" line.long 0xA4 "ROM_INJ,ROM injection code" hexmask.long 0xA4 0.--31. 1. "CODE,ROM injection code" line.long 0xA8 "ROM_INJ,ROM injection code" hexmask.long 0xA8 0.--31. 1. "CODE,ROM injection code" line.long 0xAC "ROM_INJ,ROM injection code" hexmask.long 0xAC 0.--31. 1. "CODE,ROM injection code" line.long 0xB0 "ROM_INJ,ROM injection code" hexmask.long 0xB0 0.--31. 1. "CODE,ROM injection code" line.long 0xB4 "ROM_INJ,ROM injection code" hexmask.long 0xB4 0.--31. 1. "CODE,ROM injection code" line.long 0xB8 "ROM_INJ,ROM injection code" hexmask.long 0xB8 0.--31. 1. "CODE,ROM injection code" line.long 0xBC "ROM_INJ,ROM injection code" hexmask.long 0xBC 0.--31. 1. "CODE,ROM injection code" line.long 0xC0 "ROM_INJ,ROM injection code" hexmask.long 0xC0 0.--31. 1. "CODE,ROM injection code" line.long 0xC4 "ROM_INJ,ROM injection code" hexmask.long 0xC4 0.--31. 1. "CODE,ROM injection code" line.long 0xC8 "ROM_INJ,ROM injection code" hexmask.long 0xC8 0.--31. 1. "CODE,ROM injection code" line.long 0xCC "ROM_INJ,ROM injection code" hexmask.long 0xCC 0.--31. 1. "CODE,ROM injection code" line.long 0xD0 "ROM_INJ,ROM injection code" hexmask.long 0xD0 0.--31. 1. "CODE,ROM injection code" line.long 0xD4 "ROM_INJ,ROM injection code" hexmask.long 0xD4 0.--31. 1. "CODE,ROM injection code" line.long 0xD8 "ROM_INJ,ROM injection code" hexmask.long 0xD8 0.--31. 1. "CODE,ROM injection code" line.long 0xDC "ROM_INJ,ROM injection code" hexmask.long 0xDC 0.--31. 1. "CODE,ROM injection code" line.long 0xE0 "ROM_INJ,ROM injection code" hexmask.long 0xE0 0.--31. 1. "CODE,ROM injection code" line.long 0xE4 "ROM_INJ,ROM injection code" hexmask.long 0xE4 0.--31. 1. "CODE,ROM injection code" line.long 0xE8 "ROM_INJ,ROM injection code" hexmask.long 0xE8 0.--31. 1. "CODE,ROM injection code" line.long 0xEC "ROM_INJ,ROM injection code" hexmask.long 0xEC 0.--31. 1. "CODE,ROM injection code" line.long 0xF0 "ROM_INJ,ROM injection code" hexmask.long 0xF0 0.--31. 1. "CODE,ROM injection code" line.long 0xF4 "ROM_INJ,ROM injection code" hexmask.long 0xF4 0.--31. 1. "CODE,ROM injection code" line.long 0xF8 "ROM_INJ,ROM injection code" hexmask.long 0xF8 0.--31. 1. "CODE,ROM injection code" line.long 0xFC "ROM_INJ,ROM injection code" hexmask.long 0xFC 0.--31. 1. "CODE,ROM injection code" tree.end endif tree.end tree "RPC (Register Access Permission Controller)" sif (CORENAME()=="CORTEXR5F") tree "RPC_XPU_CLKGEN" base ad:0xF6800000 repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x4 0x8 0xC 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C ) group.long ($2)++0x3 line.long 0x0 "REGG0_DOM_$1,Assign domain for CKGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1A 0x1B 0x1C 0x1D 0x1E 0x1F )(list 0x40 0x44 0x48 0x4C 0x50 0x54 0x58 0x5C 0x60 0x64 0x68 0x6C 0x70 0x74 0x78 0x7C ) group.long ($2)++0x3 line.long 0x0 "REGG0_DOM_$1,Assign domain for CKGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x20 0x21 0x22 0x23 0x24 0x25 0x26 0x27 0x28 0x29 0x2A 0x2B 0x2C 0x2D 0x2E 0x2F )(list 0x80 0x84 0x88 0x8C 0x90 0x94 0x98 0x9C 0xA0 0xA4 0xA8 0xAC 0xB0 0xB4 0xB8 0xBC ) group.long ($2)++0x3 line.long 0x0 "REGG0_DOM_$1,Assign domain for CKGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x30 0x31 0x32 0x33 0x34 0x35 0x36 0x37 0x38 0x39 0x3A 0x3B 0x3C 0x3D 0x3E 0x3F )(list 0xC0 0xC4 0xC8 0xCC 0xD0 0xD4 0xD8 0xDC 0xE0 0xE4 0xE8 0xEC 0xF0 0xF4 0xF8 0xFC ) group.long ($2)++0x3 line.long 0x0 "REGG0_DOM_$1,Assign domain for CKGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x40 0x41 0x42 0x43 0x44 0x45 0x46 0x47 0x48 0x49 0x4A 0x4B 0x4C 0x4D 0x4E 0x4F )(list 0x100 0x104 0x108 0x10C 0x110 0x114 0x118 0x11C 0x120 0x124 0x128 0x12C 0x130 0x134 0x138 0x13C ) group.long ($2)++0x3 line.long 0x0 "REGG0_DOM_$1,Assign domain for CKGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x50 0x51 0x52 0x53 0x54 0x55 0x56 0x57 0x58 0x59 0x5A 0x5B 0x5C 0x5D 0x5E 0x5F )(list 0x140 0x144 0x148 0x14C 0x150 0x154 0x158 0x15C 0x160 0x164 0x168 0x16C 0x170 0x174 0x178 0x17C ) group.long ($2)++0x3 line.long 0x0 "REGG0_DOM_$1,Assign domain for CKGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x60 0x61 0x62 0x63 0x64 0x65 0x66 0x67 0x68 0x69 0x6A 0x6B 0x6C 0x6D 0x6E 0x6F )(list 0x180 0x184 0x188 0x18C 0x190 0x194 0x198 0x19C 0x1A0 0x1A4 0x1A8 0x1AC 0x1B0 0x1B4 0x1B8 0x1BC ) group.long ($2)++0x3 line.long 0x0 "REGG0_DOM_$1,Assign domain for CKGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x70 0x71 0x72 0x73 0x74 0x75 0x76 0x77 0x78 0x79 0x7A 0x7B 0x7C 0x7D 0x7E 0x7F )(list 0x1C0 0x1C4 0x1C8 0x1CC 0x1D0 0x1D4 0x1D8 0x1DC 0x1E0 0x1E4 0x1E8 0x1EC 0x1F0 0x1F4 0x1F8 0x1FC ) group.long ($2)++0x3 line.long 0x0 "REGG0_DOM_$1,Assign domain for CKGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x80 0x81 0x82 0x83 0x84 0x85 0x86 0x87 0x88 0x89 0x8A 0x8B 0x8C 0x8D 0x8E 0x8F )(list 0x200 0x204 0x208 0x20C 0x210 0x214 0x218 0x21C 0x220 0x224 0x228 0x22C 0x230 0x234 0x238 0x23C ) group.long ($2)++0x3 line.long 0x0 "REGG0_DOM_$1,Assign domain for CKGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x90 0x91 0x92 0x93 0x94 0x95 0x96 0x97 0x98 0x99 0x9A 0x9B 0x9C 0x9D 0x9E 0x9F )(list 0x240 0x244 0x248 0x24C 0x250 0x254 0x258 0x25C 0x260 0x264 0x268 0x26C 0x270 0x274 0x278 0x27C ) group.long ($2)++0x3 line.long 0x0 "REGG0_DOM_$1,Assign domain for CKGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xA0 0xA1 0xA2 0xA3 0xA4 0xA5 0xA6 0xA7 0xA8 0xA9 0xAA 0xAB 0xAC 0xAD 0xAE 0xAF )(list 0x280 0x284 0x288 0x28C 0x290 0x294 0x298 0x29C 0x2A0 0x2A4 0x2A8 0x2AC 0x2B0 0x2B4 0x2B8 0x2BC ) group.long ($2)++0x3 line.long 0x0 "REGG0_DOM_$1,Assign domain for CKGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xB0 0xB1 0xB2 0xB3 0xB4 0xB5 0xB6 0xB7 0xB8 0xB9 0xBA 0xBB 0xBC 0xBD 0xBE 0xBF )(list 0x2C0 0x2C4 0x2C8 0x2CC 0x2D0 0x2D4 0x2D8 0x2DC 0x2E0 0x2E4 0x2E8 0x2EC 0x2F0 0x2F4 0x2F8 0x2FC ) group.long ($2)++0x3 line.long 0x0 "REGG0_DOM_$1,Assign domain for CKGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xC0 0xC1 0xC2 0xC3 0xC4 0xC5 0xC6 0xC7 0xC8 0xC9 0xCA 0xCB 0xCC 0xCD 0xCE 0xCF )(list 0x300 0x304 0x308 0x30C 0x310 0x314 0x318 0x31C 0x320 0x324 0x328 0x32C 0x330 0x334 0x338 0x33C ) group.long ($2)++0x3 line.long 0x0 "REGG0_DOM_$1,Assign domain for CKGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xD0 0xD1 0xD2 0xD3 0xD4 0xD5 0xD6 0xD7 0xD8 0xD9 0xDA 0xDB 0xDC 0xDD 0xDE 0xDF )(list 0x340 0x344 0x348 0x34C 0x350 0x354 0x358 0x35C 0x360 0x364 0x368 0x36C 0x370 0x374 0x378 0x37C ) group.long ($2)++0x3 line.long 0x0 "REGG0_DOM_$1,Assign domain for CKGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xE0 0xE1 0xE2 0xE3 0xE4 0xE5 0xE6 0xE7 0xE8 0xE9 0xEA 0xEB 0xEC 0xED 0xEE 0xEF )(list 0x380 0x384 0x388 0x38C 0x390 0x394 0x398 0x39C 0x3A0 0x3A4 0x3A8 0x3AC 0x3B0 0x3B4 0x3B8 0x3BC ) group.long ($2)++0x3 line.long 0x0 "REGG0_DOM_$1,Assign domain for CKGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xF0 0xF1 0xF2 0xF3 0xF4 0xF5 0xF6 0xF7 0xF8 0xF9 0xFA 0xFB 0xFC 0xFD 0xFE 0xFF )(list 0x3C0 0x3C4 0x3C8 0x3CC 0x3D0 0x3D4 0x3D8 0x3DC 0x3E0 0x3E4 0x3E8 0x3EC 0x3F0 0x3F4 0x3F8 0x3FC ) group.long ($2)++0x3 line.long 0x0 "REGG0_DOM_$1,Assign domain for CKGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x4 0x8 0xC 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C ) group.long ($2+0x400)++0x3 line.long 0x0 "REGG1_DOM_$1,Assign domain for CKGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1A 0x1B 0x1C 0x1D 0x1E 0x1F )(list 0x40 0x44 0x48 0x4C 0x50 0x54 0x58 0x5C 0x60 0x64 0x68 0x6C 0x70 0x74 0x78 0x7C ) group.long ($2+0x400)++0x3 line.long 0x0 "REGG1_DOM_$1,Assign domain for CKGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x20 0x21 0x22 0x23 0x24 0x25 0x26 0x27 0x28 0x29 0x2A 0x2B 0x2C 0x2D 0x2E 0x2F )(list 0x80 0x84 0x88 0x8C 0x90 0x94 0x98 0x9C 0xA0 0xA4 0xA8 0xAC 0xB0 0xB4 0xB8 0xBC ) group.long ($2+0x400)++0x3 line.long 0x0 "REGG1_DOM_$1,Assign domain for CKGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x30 0x31 0x32 0x33 0x34 0x35 0x36 0x37 0x38 0x39 0x3A 0x3B 0x3C 0x3D 0x3E 0x3F )(list 0xC0 0xC4 0xC8 0xCC 0xD0 0xD4 0xD8 0xDC 0xE0 0xE4 0xE8 0xEC 0xF0 0xF4 0xF8 0xFC ) group.long ($2+0x400)++0x3 line.long 0x0 "REGG1_DOM_$1,Assign domain for CKGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x40 0x41 0x42 0x43 0x44 0x45 0x46 0x47 0x48 0x49 0x4A 0x4B 0x4C 0x4D 0x4E 0x4F )(list 0x100 0x104 0x108 0x10C 0x110 0x114 0x118 0x11C 0x120 0x124 0x128 0x12C 0x130 0x134 0x138 0x13C ) group.long ($2+0x400)++0x3 line.long 0x0 "REGG1_DOM_$1,Assign domain for CKGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x50 0x51 0x52 0x53 0x54 0x55 0x56 0x57 0x58 0x59 0x5A 0x5B 0x5C 0x5D 0x5E 0x5F )(list 0x140 0x144 0x148 0x14C 0x150 0x154 0x158 0x15C 0x160 0x164 0x168 0x16C 0x170 0x174 0x178 0x17C ) group.long ($2+0x400)++0x3 line.long 0x0 "REGG1_DOM_$1,Assign domain for CKGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x60 0x61 0x62 0x63 0x64 0x65 0x66 0x67 0x68 0x69 0x6A 0x6B 0x6C 0x6D 0x6E 0x6F )(list 0x180 0x184 0x188 0x18C 0x190 0x194 0x198 0x19C 0x1A0 0x1A4 0x1A8 0x1AC 0x1B0 0x1B4 0x1B8 0x1BC ) group.long ($2+0x400)++0x3 line.long 0x0 "REGG1_DOM_$1,Assign domain for CKGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x70 0x71 0x72 0x73 0x74 0x75 0x76 0x77 0x78 0x79 0x7A 0x7B 0x7C 0x7D 0x7E 0x7F )(list 0x1C0 0x1C4 0x1C8 0x1CC 0x1D0 0x1D4 0x1D8 0x1DC 0x1E0 0x1E4 0x1E8 0x1EC 0x1F0 0x1F4 0x1F8 0x1FC ) group.long ($2+0x400)++0x3 line.long 0x0 "REGG1_DOM_$1,Assign domain for CKGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x80 0x81 0x82 0x83 0x84 0x85 0x86 0x87 0x88 0x89 0x8A 0x8B 0x8C 0x8D 0x8E 0x8F )(list 0x200 0x204 0x208 0x20C 0x210 0x214 0x218 0x21C 0x220 0x224 0x228 0x22C 0x230 0x234 0x238 0x23C ) group.long ($2+0x400)++0x3 line.long 0x0 "REGG1_DOM_$1,Assign domain for CKGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x90 0x91 0x92 0x93 0x94 0x95 0x96 0x97 0x98 0x99 0x9A 0x9B 0x9C 0x9D 0x9E 0x9F )(list 0x240 0x244 0x248 0x24C 0x250 0x254 0x258 0x25C 0x260 0x264 0x268 0x26C 0x270 0x274 0x278 0x27C ) group.long ($2+0x400)++0x3 line.long 0x0 "REGG1_DOM_$1,Assign domain for CKGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xA0 0xA1 0xA2 0xA3 0xA4 0xA5 0xA6 0xA7 0xA8 0xA9 0xAA 0xAB 0xAC 0xAD 0xAE 0xAF )(list 0x280 0x284 0x288 0x28C 0x290 0x294 0x298 0x29C 0x2A0 0x2A4 0x2A8 0x2AC 0x2B0 0x2B4 0x2B8 0x2BC ) group.long ($2+0x400)++0x3 line.long 0x0 "REGG1_DOM_$1,Assign domain for CKGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xB0 0xB1 0xB2 0xB3 0xB4 0xB5 0xB6 0xB7 0xB8 0xB9 0xBA 0xBB 0xBC 0xBD 0xBE 0xBF )(list 0x2C0 0x2C4 0x2C8 0x2CC 0x2D0 0x2D4 0x2D8 0x2DC 0x2E0 0x2E4 0x2E8 0x2EC 0x2F0 0x2F4 0x2F8 0x2FC ) group.long ($2+0x400)++0x3 line.long 0x0 "REGG1_DOM_$1,Assign domain for CKGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xC0 0xC1 0xC2 0xC3 0xC4 0xC5 0xC6 0xC7 0xC8 0xC9 0xCA 0xCB 0xCC 0xCD 0xCE 0xCF )(list 0x300 0x304 0x308 0x30C 0x310 0x314 0x318 0x31C 0x320 0x324 0x328 0x32C 0x330 0x334 0x338 0x33C ) group.long ($2+0x400)++0x3 line.long 0x0 "REGG1_DOM_$1,Assign domain for CKGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xD0 0xD1 0xD2 0xD3 0xD4 0xD5 0xD6 0xD7 0xD8 0xD9 0xDA 0xDB 0xDC 0xDD 0xDE 0xDF )(list 0x340 0x344 0x348 0x34C 0x350 0x354 0x358 0x35C 0x360 0x364 0x368 0x36C 0x370 0x374 0x378 0x37C ) group.long ($2+0x400)++0x3 line.long 0x0 "REGG1_DOM_$1,Assign domain for CKGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xE0 0xE1 0xE2 0xE3 0xE4 0xE5 0xE6 0xE7 0xE8 0xE9 0xEA 0xEB 0xEC 0xED 0xEE 0xEF )(list 0x380 0x384 0x388 0x38C 0x390 0x394 0x398 0x39C 0x3A0 0x3A4 0x3A8 0x3AC 0x3B0 0x3B4 0x3B8 0x3BC ) group.long ($2+0x400)++0x3 line.long 0x0 "REGG1_DOM_$1,Assign domain for CKGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xF0 0xF1 0xF2 0xF3 0xF4 0xF5 0xF6 0xF7 0xF8 0xF9 0xFA 0xFB 0xFC 0xFD 0xFE 0xFF )(list 0x3C0 0x3C4 0x3C8 0x3CC 0x3D0 0x3D4 0x3D8 0x3DC 0x3E0 0x3E4 0x3E8 0x3EC 0x3F0 0x3F4 0x3F8 0x3FC ) group.long ($2+0x400)++0x3 line.long 0x0 "REGG1_DOM_$1,Assign domain for CKGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x4 0x8 0xC 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C ) group.long ($2+0x800)++0x3 line.long 0x0 "REGG2_DOM_$1,Assign domain for SCR registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1A 0x1B 0x1C 0x1D 0x1E 0x1F )(list 0x40 0x44 0x48 0x4C 0x50 0x54 0x58 0x5C 0x60 0x64 0x68 0x6C 0x70 0x74 0x78 0x7C ) group.long ($2+0x800)++0x3 line.long 0x0 "REGG2_DOM_$1,Assign domain for SCR registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x20 0x21 0x22 0x23 0x24 0x25 0x26 0x27 0x28 0x29 0x2A 0x2B 0x2C 0x2D 0x2E 0x2F )(list 0x80 0x84 0x88 0x8C 0x90 0x94 0x98 0x9C 0xA0 0xA4 0xA8 0xAC 0xB0 0xB4 0xB8 0xBC ) group.long ($2+0x800)++0x3 line.long 0x0 "REGG2_DOM_$1,Assign domain for SCR registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x30 0x31 0x32 0x33 0x34 0x35 0x36 0x37 0x38 0x39 0x3A 0x3B 0x3C 0x3D 0x3E 0x3F )(list 0xC0 0xC4 0xC8 0xCC 0xD0 0xD4 0xD8 0xDC 0xE0 0xE4 0xE8 0xEC 0xF0 0xF4 0xF8 0xFC ) group.long ($2+0x800)++0x3 line.long 0x0 "REGG2_DOM_$1,Assign domain for SCR registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x40 0x41 0x42 0x43 0x44 0x45 0x46 0x47 0x48 0x49 0x4A 0x4B 0x4C 0x4D 0x4E 0x4F )(list 0x100 0x104 0x108 0x10C 0x110 0x114 0x118 0x11C 0x120 0x124 0x128 0x12C 0x130 0x134 0x138 0x13C ) group.long ($2+0x800)++0x3 line.long 0x0 "REGG2_DOM_$1,Assign domain for SCR registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x50 0x51 0x52 0x53 0x54 0x55 0x56 0x57 0x58 0x59 0x5A 0x5B 0x5C 0x5D 0x5E 0x5F )(list 0x140 0x144 0x148 0x14C 0x150 0x154 0x158 0x15C 0x160 0x164 0x168 0x16C 0x170 0x174 0x178 0x17C ) group.long ($2+0x800)++0x3 line.long 0x0 "REGG2_DOM_$1,Assign domain for SCR registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x60 0x61 0x62 0x63 0x64 0x65 0x66 0x67 0x68 0x69 0x6A 0x6B 0x6C 0x6D 0x6E 0x6F )(list 0x180 0x184 0x188 0x18C 0x190 0x194 0x198 0x19C 0x1A0 0x1A4 0x1A8 0x1AC 0x1B0 0x1B4 0x1B8 0x1BC ) group.long ($2+0x800)++0x3 line.long 0x0 "REGG2_DOM_$1,Assign domain for SCR registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x70 0x71 0x72 0x73 0x74 0x75 0x76 0x77 0x78 0x79 0x7A 0x7B 0x7C 0x7D 0x7E 0x7F )(list 0x1C0 0x1C4 0x1C8 0x1CC 0x1D0 0x1D4 0x1D8 0x1DC 0x1E0 0x1E4 0x1E8 0x1EC 0x1F0 0x1F4 0x1F8 0x1FC ) group.long ($2+0x800)++0x3 line.long 0x0 "REGG2_DOM_$1,Assign domain for SCR registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x80 0x81 0x82 0x83 0x84 0x85 0x86 0x87 0x88 0x89 0x8A 0x8B 0x8C 0x8D 0x8E 0x8F )(list 0x200 0x204 0x208 0x20C 0x210 0x214 0x218 0x21C 0x220 0x224 0x228 0x22C 0x230 0x234 0x238 0x23C ) group.long ($2+0x800)++0x3 line.long 0x0 "REGG2_DOM_$1,Assign domain for SCR registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x90 0x91 0x92 0x93 0x94 0x95 0x96 0x97 0x98 0x99 0x9A 0x9B 0x9C 0x9D 0x9E 0x9F )(list 0x240 0x244 0x248 0x24C 0x250 0x254 0x258 0x25C 0x260 0x264 0x268 0x26C 0x270 0x274 0x278 0x27C ) group.long ($2+0x800)++0x3 line.long 0x0 "REGG2_DOM_$1,Assign domain for SCR registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xA0 0xA1 0xA2 0xA3 0xA4 0xA5 0xA6 0xA7 0xA8 0xA9 0xAA 0xAB 0xAC 0xAD 0xAE 0xAF )(list 0x280 0x284 0x288 0x28C 0x290 0x294 0x298 0x29C 0x2A0 0x2A4 0x2A8 0x2AC 0x2B0 0x2B4 0x2B8 0x2BC ) group.long ($2+0x800)++0x3 line.long 0x0 "REGG2_DOM_$1,Assign domain for SCR registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xB0 0xB1 0xB2 0xB3 0xB4 0xB5 0xB6 0xB7 0xB8 0xB9 0xBA 0xBB 0xBC 0xBD 0xBE 0xBF )(list 0x2C0 0x2C4 0x2C8 0x2CC 0x2D0 0x2D4 0x2D8 0x2DC 0x2E0 0x2E4 0x2E8 0x2EC 0x2F0 0x2F4 0x2F8 0x2FC ) group.long ($2+0x800)++0x3 line.long 0x0 "REGG2_DOM_$1,Assign domain for SCR registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xC0 0xC1 0xC2 0xC3 0xC4 0xC5 0xC6 0xC7 0xC8 0xC9 0xCA 0xCB 0xCC 0xCD 0xCE 0xCF )(list 0x300 0x304 0x308 0x30C 0x310 0x314 0x318 0x31C 0x320 0x324 0x328 0x32C 0x330 0x334 0x338 0x33C ) group.long ($2+0x800)++0x3 line.long 0x0 "REGG2_DOM_$1,Assign domain for SCR registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xD0 0xD1 0xD2 0xD3 0xD4 0xD5 0xD6 0xD7 0xD8 0xD9 0xDA 0xDB 0xDC 0xDD 0xDE 0xDF )(list 0x340 0x344 0x348 0x34C 0x350 0x354 0x358 0x35C 0x360 0x364 0x368 0x36C 0x370 0x374 0x378 0x37C ) group.long ($2+0x800)++0x3 line.long 0x0 "REGG2_DOM_$1,Assign domain for SCR registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xE0 0xE1 0xE2 0xE3 0xE4 0xE5 0xE6 0xE7 0xE8 0xE9 0xEA 0xEB 0xEC 0xED 0xEE 0xEF )(list 0x380 0x384 0x388 0x38C 0x390 0x394 0x398 0x39C 0x3A0 0x3A4 0x3A8 0x3AC 0x3B0 0x3B4 0x3B8 0x3BC ) group.long ($2+0x800)++0x3 line.long 0x0 "REGG2_DOM_$1,Assign domain for SCR registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xF0 0xF1 0xF2 0xF3 0xF4 0xF5 0xF6 0xF7 0xF8 0xF9 0xFA 0xFB 0xFC 0xFD 0xFE 0xFF )(list 0x3C0 0x3C4 0x3C8 0x3CC 0x3D0 0x3D4 0x3D8 0x3DC 0x3E0 0x3E4 0x3E8 0x3EC 0x3F0 0x3F4 0x3F8 0x3FC ) group.long ($2+0x800)++0x3 line.long 0x0 "REGG2_DOM_$1,Assign domain for SCR registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x4 0x8 0xC 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C ) group.long ($2+0xC00)++0x3 line.long 0x0 "REGG3_DOM_$1,Assign domain for SCR registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1A 0x1B 0x1C 0x1D 0x1E 0x1F )(list 0x40 0x44 0x48 0x4C 0x50 0x54 0x58 0x5C 0x60 0x64 0x68 0x6C 0x70 0x74 0x78 0x7C ) group.long ($2+0xC00)++0x3 line.long 0x0 "REGG3_DOM_$1,Assign domain for SCR registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x20 0x21 0x22 0x23 0x24 0x25 0x26 0x27 0x28 0x29 0x2A 0x2B 0x2C 0x2D 0x2E 0x2F )(list 0x80 0x84 0x88 0x8C 0x90 0x94 0x98 0x9C 0xA0 0xA4 0xA8 0xAC 0xB0 0xB4 0xB8 0xBC ) group.long ($2+0xC00)++0x3 line.long 0x0 "REGG3_DOM_$1,Assign domain for SCR registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x30 0x31 0x32 0x33 0x34 0x35 0x36 0x37 0x38 0x39 0x3A 0x3B 0x3C 0x3D 0x3E 0x3F )(list 0xC0 0xC4 0xC8 0xCC 0xD0 0xD4 0xD8 0xDC 0xE0 0xE4 0xE8 0xEC 0xF0 0xF4 0xF8 0xFC ) group.long ($2+0xC00)++0x3 line.long 0x0 "REGG3_DOM_$1,Assign domain for SCR registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x40 0x41 0x42 0x43 0x44 0x45 0x46 0x47 0x48 0x49 0x4A 0x4B 0x4C 0x4D 0x4E 0x4F )(list 0x100 0x104 0x108 0x10C 0x110 0x114 0x118 0x11C 0x120 0x124 0x128 0x12C 0x130 0x134 0x138 0x13C ) group.long ($2+0xC00)++0x3 line.long 0x0 "REGG3_DOM_$1,Assign domain for SCR registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x50 0x51 0x52 0x53 0x54 0x55 0x56 0x57 0x58 0x59 0x5A 0x5B 0x5C 0x5D 0x5E 0x5F )(list 0x140 0x144 0x148 0x14C 0x150 0x154 0x158 0x15C 0x160 0x164 0x168 0x16C 0x170 0x174 0x178 0x17C ) group.long ($2+0xC00)++0x3 line.long 0x0 "REGG3_DOM_$1,Assign domain for SCR registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x60 0x61 0x62 0x63 0x64 0x65 0x66 0x67 0x68 0x69 0x6A 0x6B 0x6C 0x6D 0x6E 0x6F )(list 0x180 0x184 0x188 0x18C 0x190 0x194 0x198 0x19C 0x1A0 0x1A4 0x1A8 0x1AC 0x1B0 0x1B4 0x1B8 0x1BC ) group.long ($2+0xC00)++0x3 line.long 0x0 "REGG3_DOM_$1,Assign domain for SCR registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x70 0x71 0x72 0x73 0x74 0x75 0x76 0x77 0x78 0x79 0x7A 0x7B 0x7C 0x7D 0x7E 0x7F )(list 0x1C0 0x1C4 0x1C8 0x1CC 0x1D0 0x1D4 0x1D8 0x1DC 0x1E0 0x1E4 0x1E8 0x1EC 0x1F0 0x1F4 0x1F8 0x1FC ) group.long ($2+0xC00)++0x3 line.long 0x0 "REGG3_DOM_$1,Assign domain for SCR registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x80 0x81 0x82 0x83 0x84 0x85 0x86 0x87 0x88 0x89 0x8A 0x8B 0x8C 0x8D 0x8E 0x8F )(list 0x200 0x204 0x208 0x20C 0x210 0x214 0x218 0x21C 0x220 0x224 0x228 0x22C 0x230 0x234 0x238 0x23C ) group.long ($2+0xC00)++0x3 line.long 0x0 "REGG3_DOM_$1,Assign domain for SCR registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x90 0x91 0x92 0x93 0x94 0x95 0x96 0x97 0x98 0x99 0x9A 0x9B 0x9C 0x9D 0x9E 0x9F )(list 0x240 0x244 0x248 0x24C 0x250 0x254 0x258 0x25C 0x260 0x264 0x268 0x26C 0x270 0x274 0x278 0x27C ) group.long ($2+0xC00)++0x3 line.long 0x0 "REGG3_DOM_$1,Assign domain for SCR registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xA0 0xA1 0xA2 0xA3 0xA4 0xA5 0xA6 0xA7 0xA8 0xA9 0xAA 0xAB 0xAC 0xAD 0xAE 0xAF )(list 0x280 0x284 0x288 0x28C 0x290 0x294 0x298 0x29C 0x2A0 0x2A4 0x2A8 0x2AC 0x2B0 0x2B4 0x2B8 0x2BC ) group.long ($2+0xC00)++0x3 line.long 0x0 "REGG3_DOM_$1,Assign domain for SCR registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xB0 0xB1 0xB2 0xB3 0xB4 0xB5 0xB6 0xB7 0xB8 0xB9 0xBA 0xBB 0xBC 0xBD 0xBE 0xBF )(list 0x2C0 0x2C4 0x2C8 0x2CC 0x2D0 0x2D4 0x2D8 0x2DC 0x2E0 0x2E4 0x2E8 0x2EC 0x2F0 0x2F4 0x2F8 0x2FC ) group.long ($2+0xC00)++0x3 line.long 0x0 "REGG3_DOM_$1,Assign domain for SCR registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xC0 0xC1 0xC2 0xC3 0xC4 0xC5 0xC6 0xC7 0xC8 0xC9 0xCA 0xCB 0xCC 0xCD 0xCE 0xCF )(list 0x300 0x304 0x308 0x30C 0x310 0x314 0x318 0x31C 0x320 0x324 0x328 0x32C 0x330 0x334 0x338 0x33C ) group.long ($2+0xC00)++0x3 line.long 0x0 "REGG3_DOM_$1,Assign domain for SCR registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xD0 0xD1 0xD2 0xD3 0xD4 0xD5 0xD6 0xD7 0xD8 0xD9 0xDA 0xDB 0xDC 0xDD 0xDE 0xDF )(list 0x340 0x344 0x348 0x34C 0x350 0x354 0x358 0x35C 0x360 0x364 0x368 0x36C 0x370 0x374 0x378 0x37C ) group.long ($2+0xC00)++0x3 line.long 0x0 "REGG3_DOM_$1,Assign domain for SCR registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xE0 0xE1 0xE2 0xE3 0xE4 0xE5 0xE6 0xE7 0xE8 0xE9 0xEA 0xEB 0xEC 0xED 0xEE 0xEF )(list 0x380 0x384 0x388 0x38C 0x390 0x394 0x398 0x39C 0x3A0 0x3A4 0x3A8 0x3AC 0x3B0 0x3B4 0x3B8 0x3BC ) group.long ($2+0xC00)++0x3 line.long 0x0 "REGG3_DOM_$1,Assign domain for SCR registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xF0 0xF1 0xF2 0xF3 0xF4 0xF5 0xF6 0xF7 0xF8 0xF9 0xFA 0xFB 0xFC 0xFD 0xFE 0xFF )(list 0x3C0 0x3C4 0x3C8 0x3CC 0x3D0 0x3D4 0x3D8 0x3DC 0x3E0 0x3E4 0x3E8 0x3EC 0x3F0 0x3F4 0x3F8 0x3FC ) group.long ($2+0xC00)++0x3 line.long 0x0 "REGG3_DOM_$1,Assign domain for SCR registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x4 0x8 0xC 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C ) group.long ($2+0x1000)++0x3 line.long 0x0 "REGG4_DOM_$1,Assign domain for RSTGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1A 0x1B 0x1C 0x1D 0x1E 0x1F )(list 0x40 0x44 0x48 0x4C 0x50 0x54 0x58 0x5C 0x60 0x64 0x68 0x6C 0x70 0x74 0x78 0x7C ) group.long ($2+0x1000)++0x3 line.long 0x0 "REGG4_DOM_$1,Assign domain for RSTGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x20 0x21 0x22 0x23 0x24 0x25 0x26 0x27 0x28 0x29 0x2A 0x2B 0x2C 0x2D 0x2E 0x2F )(list 0x80 0x84 0x88 0x8C 0x90 0x94 0x98 0x9C 0xA0 0xA4 0xA8 0xAC 0xB0 0xB4 0xB8 0xBC ) group.long ($2+0x1000)++0x3 line.long 0x0 "REGG4_DOM_$1,Assign domain for RSTGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x30 0x31 0x32 0x33 0x34 0x35 0x36 0x37 0x38 0x39 0x3A 0x3B 0x3C 0x3D 0x3E 0x3F )(list 0xC0 0xC4 0xC8 0xCC 0xD0 0xD4 0xD8 0xDC 0xE0 0xE4 0xE8 0xEC 0xF0 0xF4 0xF8 0xFC ) group.long ($2+0x1000)++0x3 line.long 0x0 "REGG4_DOM_$1,Assign domain for RSTGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x40 0x41 0x42 0x43 0x44 0x45 0x46 0x47 0x48 0x49 0x4A 0x4B 0x4C 0x4D 0x4E 0x4F )(list 0x100 0x104 0x108 0x10C 0x110 0x114 0x118 0x11C 0x120 0x124 0x128 0x12C 0x130 0x134 0x138 0x13C ) group.long ($2+0x1000)++0x3 line.long 0x0 "REGG4_DOM_$1,Assign domain for RSTGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x50 0x51 0x52 0x53 0x54 0x55 0x56 0x57 0x58 0x59 0x5A 0x5B 0x5C 0x5D 0x5E 0x5F )(list 0x140 0x144 0x148 0x14C 0x150 0x154 0x158 0x15C 0x160 0x164 0x168 0x16C 0x170 0x174 0x178 0x17C ) group.long ($2+0x1000)++0x3 line.long 0x0 "REGG4_DOM_$1,Assign domain for RSTGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x60 0x61 0x62 0x63 0x64 0x65 0x66 0x67 0x68 0x69 0x6A 0x6B 0x6C 0x6D 0x6E 0x6F )(list 0x180 0x184 0x188 0x18C 0x190 0x194 0x198 0x19C 0x1A0 0x1A4 0x1A8 0x1AC 0x1B0 0x1B4 0x1B8 0x1BC ) group.long ($2+0x1000)++0x3 line.long 0x0 "REGG4_DOM_$1,Assign domain for RSTGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x70 0x71 0x72 0x73 0x74 0x75 0x76 0x77 0x78 0x79 0x7A 0x7B 0x7C 0x7D 0x7E 0x7F )(list 0x1C0 0x1C4 0x1C8 0x1CC 0x1D0 0x1D4 0x1D8 0x1DC 0x1E0 0x1E4 0x1E8 0x1EC 0x1F0 0x1F4 0x1F8 0x1FC ) group.long ($2+0x1000)++0x3 line.long 0x0 "REGG4_DOM_$1,Assign domain for RSTGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x80 0x81 0x82 0x83 0x84 0x85 0x86 0x87 0x88 0x89 0x8A 0x8B 0x8C 0x8D 0x8E 0x8F )(list 0x200 0x204 0x208 0x20C 0x210 0x214 0x218 0x21C 0x220 0x224 0x228 0x22C 0x230 0x234 0x238 0x23C ) group.long ($2+0x1000)++0x3 line.long 0x0 "REGG4_DOM_$1,Assign domain for RSTGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x90 0x91 0x92 0x93 0x94 0x95 0x96 0x97 0x98 0x99 0x9A 0x9B 0x9C 0x9D 0x9E 0x9F )(list 0x240 0x244 0x248 0x24C 0x250 0x254 0x258 0x25C 0x260 0x264 0x268 0x26C 0x270 0x274 0x278 0x27C ) group.long ($2+0x1000)++0x3 line.long 0x0 "REGG4_DOM_$1,Assign domain for RSTGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xA0 0xA1 0xA2 0xA3 0xA4 0xA5 0xA6 0xA7 0xA8 0xA9 0xAA 0xAB 0xAC 0xAD 0xAE 0xAF )(list 0x280 0x284 0x288 0x28C 0x290 0x294 0x298 0x29C 0x2A0 0x2A4 0x2A8 0x2AC 0x2B0 0x2B4 0x2B8 0x2BC ) group.long ($2+0x1000)++0x3 line.long 0x0 "REGG4_DOM_$1,Assign domain for RSTGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xB0 0xB1 0xB2 0xB3 0xB4 0xB5 0xB6 0xB7 0xB8 0xB9 0xBA 0xBB 0xBC 0xBD 0xBE 0xBF )(list 0x2C0 0x2C4 0x2C8 0x2CC 0x2D0 0x2D4 0x2D8 0x2DC 0x2E0 0x2E4 0x2E8 0x2EC 0x2F0 0x2F4 0x2F8 0x2FC ) group.long ($2+0x1000)++0x3 line.long 0x0 "REGG4_DOM_$1,Assign domain for RSTGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xC0 0xC1 0xC2 0xC3 0xC4 0xC5 0xC6 0xC7 0xC8 0xC9 0xCA 0xCB 0xCC 0xCD 0xCE 0xCF )(list 0x300 0x304 0x308 0x30C 0x310 0x314 0x318 0x31C 0x320 0x324 0x328 0x32C 0x330 0x334 0x338 0x33C ) group.long ($2+0x1000)++0x3 line.long 0x0 "REGG4_DOM_$1,Assign domain for RSTGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xD0 0xD1 0xD2 0xD3 0xD4 0xD5 0xD6 0xD7 0xD8 0xD9 0xDA 0xDB 0xDC 0xDD 0xDE 0xDF )(list 0x340 0x344 0x348 0x34C 0x350 0x354 0x358 0x35C 0x360 0x364 0x368 0x36C 0x370 0x374 0x378 0x37C ) group.long ($2+0x1000)++0x3 line.long 0x0 "REGG4_DOM_$1,Assign domain for RSTGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xE0 0xE1 0xE2 0xE3 0xE4 0xE5 0xE6 0xE7 0xE8 0xE9 0xEA 0xEB 0xEC 0xED 0xEE 0xEF )(list 0x380 0x384 0x388 0x38C 0x390 0x394 0x398 0x39C 0x3A0 0x3A4 0x3A8 0x3AC 0x3B0 0x3B4 0x3B8 0x3BC ) group.long ($2+0x1000)++0x3 line.long 0x0 "REGG4_DOM_$1,Assign domain for RSTGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xF0 0xF1 0xF2 0xF3 0xF4 0xF5 0xF6 0xF7 0xF8 0xF9 0xFA 0xFB 0xFC 0xFD 0xFE 0xFF )(list 0x3C0 0x3C4 0x3C8 0x3CC 0x3D0 0x3D4 0x3D8 0x3DC 0x3E0 0x3E4 0x3E8 0x3EC 0x3F0 0x3F4 0x3F8 0x3FC ) group.long ($2+0x1000)++0x3 line.long 0x0 "REGG4_DOM_$1,Assign domain for RSTGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x4 0x8 0xC 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C ) group.long ($2+0x1400)++0x3 line.long 0x0 "REGG5_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1A 0x1B 0x1C 0x1D 0x1E 0x1F )(list 0x40 0x44 0x48 0x4C 0x50 0x54 0x58 0x5C 0x60 0x64 0x68 0x6C 0x70 0x74 0x78 0x7C ) group.long ($2+0x1400)++0x3 line.long 0x0 "REGG5_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x20 0x21 0x22 0x23 0x24 0x25 0x26 0x27 0x28 0x29 0x2A 0x2B 0x2C 0x2D 0x2E 0x2F )(list 0x80 0x84 0x88 0x8C 0x90 0x94 0x98 0x9C 0xA0 0xA4 0xA8 0xAC 0xB0 0xB4 0xB8 0xBC ) group.long ($2+0x1400)++0x3 line.long 0x0 "REGG5_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x30 0x31 0x32 0x33 0x34 0x35 0x36 0x37 0x38 0x39 0x3A 0x3B 0x3C 0x3D 0x3E 0x3F )(list 0xC0 0xC4 0xC8 0xCC 0xD0 0xD4 0xD8 0xDC 0xE0 0xE4 0xE8 0xEC 0xF0 0xF4 0xF8 0xFC ) group.long ($2+0x1400)++0x3 line.long 0x0 "REGG5_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x40 0x41 0x42 0x43 0x44 0x45 0x46 0x47 0x48 0x49 0x4A 0x4B 0x4C 0x4D 0x4E 0x4F )(list 0x100 0x104 0x108 0x10C 0x110 0x114 0x118 0x11C 0x120 0x124 0x128 0x12C 0x130 0x134 0x138 0x13C ) group.long ($2+0x1400)++0x3 line.long 0x0 "REGG5_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x50 0x51 0x52 0x53 0x54 0x55 0x56 0x57 0x58 0x59 0x5A 0x5B 0x5C 0x5D 0x5E 0x5F )(list 0x140 0x144 0x148 0x14C 0x150 0x154 0x158 0x15C 0x160 0x164 0x168 0x16C 0x170 0x174 0x178 0x17C ) group.long ($2+0x1400)++0x3 line.long 0x0 "REGG5_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x60 0x61 0x62 0x63 0x64 0x65 0x66 0x67 0x68 0x69 0x6A 0x6B 0x6C 0x6D 0x6E 0x6F )(list 0x180 0x184 0x188 0x18C 0x190 0x194 0x198 0x19C 0x1A0 0x1A4 0x1A8 0x1AC 0x1B0 0x1B4 0x1B8 0x1BC ) group.long ($2+0x1400)++0x3 line.long 0x0 "REGG5_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x70 0x71 0x72 0x73 0x74 0x75 0x76 0x77 0x78 0x79 0x7A 0x7B 0x7C 0x7D 0x7E 0x7F )(list 0x1C0 0x1C4 0x1C8 0x1CC 0x1D0 0x1D4 0x1D8 0x1DC 0x1E0 0x1E4 0x1E8 0x1EC 0x1F0 0x1F4 0x1F8 0x1FC ) group.long ($2+0x1400)++0x3 line.long 0x0 "REGG5_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x80 0x81 0x82 0x83 0x84 0x85 0x86 0x87 0x88 0x89 0x8A 0x8B 0x8C 0x8D 0x8E 0x8F )(list 0x200 0x204 0x208 0x20C 0x210 0x214 0x218 0x21C 0x220 0x224 0x228 0x22C 0x230 0x234 0x238 0x23C ) group.long ($2+0x1400)++0x3 line.long 0x0 "REGG5_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x90 0x91 0x92 0x93 0x94 0x95 0x96 0x97 0x98 0x99 0x9A 0x9B 0x9C 0x9D 0x9E 0x9F )(list 0x240 0x244 0x248 0x24C 0x250 0x254 0x258 0x25C 0x260 0x264 0x268 0x26C 0x270 0x274 0x278 0x27C ) group.long ($2+0x1400)++0x3 line.long 0x0 "REGG5_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xA0 0xA1 0xA2 0xA3 0xA4 0xA5 0xA6 0xA7 0xA8 0xA9 0xAA 0xAB 0xAC 0xAD 0xAE 0xAF )(list 0x280 0x284 0x288 0x28C 0x290 0x294 0x298 0x29C 0x2A0 0x2A4 0x2A8 0x2AC 0x2B0 0x2B4 0x2B8 0x2BC ) group.long ($2+0x1400)++0x3 line.long 0x0 "REGG5_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xB0 0xB1 0xB2 0xB3 0xB4 0xB5 0xB6 0xB7 0xB8 0xB9 0xBA 0xBB 0xBC 0xBD 0xBE 0xBF )(list 0x2C0 0x2C4 0x2C8 0x2CC 0x2D0 0x2D4 0x2D8 0x2DC 0x2E0 0x2E4 0x2E8 0x2EC 0x2F0 0x2F4 0x2F8 0x2FC ) group.long ($2+0x1400)++0x3 line.long 0x0 "REGG5_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xC0 0xC1 0xC2 0xC3 0xC4 0xC5 0xC6 0xC7 0xC8 0xC9 0xCA 0xCB 0xCC 0xCD 0xCE 0xCF )(list 0x300 0x304 0x308 0x30C 0x310 0x314 0x318 0x31C 0x320 0x324 0x328 0x32C 0x330 0x334 0x338 0x33C ) group.long ($2+0x1400)++0x3 line.long 0x0 "REGG5_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xD0 0xD1 0xD2 0xD3 0xD4 0xD5 0xD6 0xD7 0xD8 0xD9 0xDA 0xDB 0xDC 0xDD 0xDE 0xDF )(list 0x340 0x344 0x348 0x34C 0x350 0x354 0x358 0x35C 0x360 0x364 0x368 0x36C 0x370 0x374 0x378 0x37C ) group.long ($2+0x1400)++0x3 line.long 0x0 "REGG5_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xE0 0xE1 0xE2 0xE3 0xE4 0xE5 0xE6 0xE7 0xE8 0xE9 0xEA 0xEB 0xEC 0xED 0xEE 0xEF )(list 0x380 0x384 0x388 0x38C 0x390 0x394 0x398 0x39C 0x3A0 0x3A4 0x3A8 0x3AC 0x3B0 0x3B4 0x3B8 0x3BC ) group.long ($2+0x1400)++0x3 line.long 0x0 "REGG5_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xF0 0xF1 0xF2 0xF3 0xF4 0xF5 0xF6 0xF7 0xF8 0xF9 0xFA 0xFB 0xFC 0xFD 0xFE 0xFF )(list 0x3C0 0x3C4 0x3C8 0x3CC 0x3D0 0x3D4 0x3D8 0x3DC 0x3E0 0x3E4 0x3E8 0x3EC 0x3F0 0x3F4 0x3F8 0x3FC ) group.long ($2+0x1400)++0x3 line.long 0x0 "REGG5_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x4 0x8 0xC 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C ) group.long ($2+0x1800)++0x3 line.long 0x0 "REGG6_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1A 0x1B 0x1C 0x1D 0x1E 0x1F )(list 0x40 0x44 0x48 0x4C 0x50 0x54 0x58 0x5C 0x60 0x64 0x68 0x6C 0x70 0x74 0x78 0x7C ) group.long ($2+0x1800)++0x3 line.long 0x0 "REGG6_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x20 0x21 0x22 0x23 0x24 0x25 0x26 0x27 0x28 0x29 0x2A 0x2B 0x2C 0x2D 0x2E 0x2F )(list 0x80 0x84 0x88 0x8C 0x90 0x94 0x98 0x9C 0xA0 0xA4 0xA8 0xAC 0xB0 0xB4 0xB8 0xBC ) group.long ($2+0x1800)++0x3 line.long 0x0 "REGG6_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x30 0x31 0x32 0x33 0x34 0x35 0x36 0x37 0x38 0x39 0x3A 0x3B 0x3C 0x3D 0x3E 0x3F )(list 0xC0 0xC4 0xC8 0xCC 0xD0 0xD4 0xD8 0xDC 0xE0 0xE4 0xE8 0xEC 0xF0 0xF4 0xF8 0xFC ) group.long ($2+0x1800)++0x3 line.long 0x0 "REGG6_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x40 0x41 0x42 0x43 0x44 0x45 0x46 0x47 0x48 0x49 0x4A 0x4B 0x4C 0x4D 0x4E 0x4F )(list 0x100 0x104 0x108 0x10C 0x110 0x114 0x118 0x11C 0x120 0x124 0x128 0x12C 0x130 0x134 0x138 0x13C ) group.long ($2+0x1800)++0x3 line.long 0x0 "REGG6_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x50 0x51 0x52 0x53 0x54 0x55 0x56 0x57 0x58 0x59 0x5A 0x5B 0x5C 0x5D 0x5E 0x5F )(list 0x140 0x144 0x148 0x14C 0x150 0x154 0x158 0x15C 0x160 0x164 0x168 0x16C 0x170 0x174 0x178 0x17C ) group.long ($2+0x1800)++0x3 line.long 0x0 "REGG6_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x60 0x61 0x62 0x63 0x64 0x65 0x66 0x67 0x68 0x69 0x6A 0x6B 0x6C 0x6D 0x6E 0x6F )(list 0x180 0x184 0x188 0x18C 0x190 0x194 0x198 0x19C 0x1A0 0x1A4 0x1A8 0x1AC 0x1B0 0x1B4 0x1B8 0x1BC ) group.long ($2+0x1800)++0x3 line.long 0x0 "REGG6_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x70 0x71 0x72 0x73 0x74 0x75 0x76 0x77 0x78 0x79 0x7A 0x7B 0x7C 0x7D 0x7E 0x7F )(list 0x1C0 0x1C4 0x1C8 0x1CC 0x1D0 0x1D4 0x1D8 0x1DC 0x1E0 0x1E4 0x1E8 0x1EC 0x1F0 0x1F4 0x1F8 0x1FC ) group.long ($2+0x1800)++0x3 line.long 0x0 "REGG6_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x80 0x81 0x82 0x83 0x84 0x85 0x86 0x87 0x88 0x89 0x8A 0x8B 0x8C 0x8D 0x8E 0x8F )(list 0x200 0x204 0x208 0x20C 0x210 0x214 0x218 0x21C 0x220 0x224 0x228 0x22C 0x230 0x234 0x238 0x23C ) group.long ($2+0x1800)++0x3 line.long 0x0 "REGG6_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x90 0x91 0x92 0x93 0x94 0x95 0x96 0x97 0x98 0x99 0x9A 0x9B 0x9C 0x9D 0x9E 0x9F )(list 0x240 0x244 0x248 0x24C 0x250 0x254 0x258 0x25C 0x260 0x264 0x268 0x26C 0x270 0x274 0x278 0x27C ) group.long ($2+0x1800)++0x3 line.long 0x0 "REGG6_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xA0 0xA1 0xA2 0xA3 0xA4 0xA5 0xA6 0xA7 0xA8 0xA9 0xAA 0xAB 0xAC 0xAD 0xAE 0xAF )(list 0x280 0x284 0x288 0x28C 0x290 0x294 0x298 0x29C 0x2A0 0x2A4 0x2A8 0x2AC 0x2B0 0x2B4 0x2B8 0x2BC ) group.long ($2+0x1800)++0x3 line.long 0x0 "REGG6_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xB0 0xB1 0xB2 0xB3 0xB4 0xB5 0xB6 0xB7 0xB8 0xB9 0xBA 0xBB 0xBC 0xBD 0xBE 0xBF )(list 0x2C0 0x2C4 0x2C8 0x2CC 0x2D0 0x2D4 0x2D8 0x2DC 0x2E0 0x2E4 0x2E8 0x2EC 0x2F0 0x2F4 0x2F8 0x2FC ) group.long ($2+0x1800)++0x3 line.long 0x0 "REGG6_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xC0 0xC1 0xC2 0xC3 0xC4 0xC5 0xC6 0xC7 0xC8 0xC9 0xCA 0xCB 0xCC 0xCD 0xCE 0xCF )(list 0x300 0x304 0x308 0x30C 0x310 0x314 0x318 0x31C 0x320 0x324 0x328 0x32C 0x330 0x334 0x338 0x33C ) group.long ($2+0x1800)++0x3 line.long 0x0 "REGG6_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xD0 0xD1 0xD2 0xD3 0xD4 0xD5 0xD6 0xD7 0xD8 0xD9 0xDA 0xDB 0xDC 0xDD 0xDE 0xDF )(list 0x340 0x344 0x348 0x34C 0x350 0x354 0x358 0x35C 0x360 0x364 0x368 0x36C 0x370 0x374 0x378 0x37C ) group.long ($2+0x1800)++0x3 line.long 0x0 "REGG6_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xE0 0xE1 0xE2 0xE3 0xE4 0xE5 0xE6 0xE7 0xE8 0xE9 0xEA 0xEB 0xEC 0xED 0xEE 0xEF )(list 0x380 0x384 0x388 0x38C 0x390 0x394 0x398 0x39C 0x3A0 0x3A4 0x3A8 0x3AC 0x3B0 0x3B4 0x3B8 0x3BC ) group.long ($2+0x1800)++0x3 line.long 0x0 "REGG6_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xF0 0xF1 0xF2 0xF3 0xF4 0xF5 0xF6 0xF7 0xF8 0xF9 0xFA 0xFB 0xFC 0xFD 0xFE 0xFF )(list 0x3C0 0x3C4 0x3C8 0x3CC 0x3D0 0x3D4 0x3D8 0x3DC 0x3E0 0x3E4 0x3E8 0x3EC 0x3F0 0x3F4 0x3F8 0x3FC ) group.long ($2+0x1800)++0x3 line.long 0x0 "REGG6_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x4 0x8 0xC 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C ) group.long ($2+0x1C00)++0x3 line.long 0x0 "REGG7_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1A 0x1B 0x1C 0x1D 0x1E 0x1F )(list 0x40 0x44 0x48 0x4C 0x50 0x54 0x58 0x5C 0x60 0x64 0x68 0x6C 0x70 0x74 0x78 0x7C ) group.long ($2+0x1C00)++0x3 line.long 0x0 "REGG7_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x20 0x21 0x22 0x23 0x24 0x25 0x26 0x27 0x28 0x29 0x2A 0x2B 0x2C 0x2D 0x2E 0x2F )(list 0x80 0x84 0x88 0x8C 0x90 0x94 0x98 0x9C 0xA0 0xA4 0xA8 0xAC 0xB0 0xB4 0xB8 0xBC ) group.long ($2+0x1C00)++0x3 line.long 0x0 "REGG7_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x30 0x31 0x32 0x33 0x34 0x35 0x36 0x37 0x38 0x39 0x3A 0x3B 0x3C 0x3D 0x3E 0x3F )(list 0xC0 0xC4 0xC8 0xCC 0xD0 0xD4 0xD8 0xDC 0xE0 0xE4 0xE8 0xEC 0xF0 0xF4 0xF8 0xFC ) group.long ($2+0x1C00)++0x3 line.long 0x0 "REGG7_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x40 0x41 0x42 0x43 0x44 0x45 0x46 0x47 0x48 0x49 0x4A 0x4B 0x4C 0x4D 0x4E 0x4F )(list 0x100 0x104 0x108 0x10C 0x110 0x114 0x118 0x11C 0x120 0x124 0x128 0x12C 0x130 0x134 0x138 0x13C ) group.long ($2+0x1C00)++0x3 line.long 0x0 "REGG7_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x50 0x51 0x52 0x53 0x54 0x55 0x56 0x57 0x58 0x59 0x5A 0x5B 0x5C 0x5D 0x5E 0x5F )(list 0x140 0x144 0x148 0x14C 0x150 0x154 0x158 0x15C 0x160 0x164 0x168 0x16C 0x170 0x174 0x178 0x17C ) group.long ($2+0x1C00)++0x3 line.long 0x0 "REGG7_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x60 0x61 0x62 0x63 0x64 0x65 0x66 0x67 0x68 0x69 0x6A 0x6B 0x6C 0x6D 0x6E 0x6F )(list 0x180 0x184 0x188 0x18C 0x190 0x194 0x198 0x19C 0x1A0 0x1A4 0x1A8 0x1AC 0x1B0 0x1B4 0x1B8 0x1BC ) group.long ($2+0x1C00)++0x3 line.long 0x0 "REGG7_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x70 0x71 0x72 0x73 0x74 0x75 0x76 0x77 0x78 0x79 0x7A 0x7B 0x7C 0x7D 0x7E 0x7F )(list 0x1C0 0x1C4 0x1C8 0x1CC 0x1D0 0x1D4 0x1D8 0x1DC 0x1E0 0x1E4 0x1E8 0x1EC 0x1F0 0x1F4 0x1F8 0x1FC ) group.long ($2+0x1C00)++0x3 line.long 0x0 "REGG7_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x80 0x81 0x82 0x83 0x84 0x85 0x86 0x87 0x88 0x89 0x8A 0x8B 0x8C 0x8D 0x8E 0x8F )(list 0x200 0x204 0x208 0x20C 0x210 0x214 0x218 0x21C 0x220 0x224 0x228 0x22C 0x230 0x234 0x238 0x23C ) group.long ($2+0x1C00)++0x3 line.long 0x0 "REGG7_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x90 0x91 0x92 0x93 0x94 0x95 0x96 0x97 0x98 0x99 0x9A 0x9B 0x9C 0x9D 0x9E 0x9F )(list 0x240 0x244 0x248 0x24C 0x250 0x254 0x258 0x25C 0x260 0x264 0x268 0x26C 0x270 0x274 0x278 0x27C ) group.long ($2+0x1C00)++0x3 line.long 0x0 "REGG7_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xA0 0xA1 0xA2 0xA3 0xA4 0xA5 0xA6 0xA7 0xA8 0xA9 0xAA 0xAB 0xAC 0xAD 0xAE 0xAF )(list 0x280 0x284 0x288 0x28C 0x290 0x294 0x298 0x29C 0x2A0 0x2A4 0x2A8 0x2AC 0x2B0 0x2B4 0x2B8 0x2BC ) group.long ($2+0x1C00)++0x3 line.long 0x0 "REGG7_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xB0 0xB1 0xB2 0xB3 0xB4 0xB5 0xB6 0xB7 0xB8 0xB9 0xBA 0xBB 0xBC 0xBD 0xBE 0xBF )(list 0x2C0 0x2C4 0x2C8 0x2CC 0x2D0 0x2D4 0x2D8 0x2DC 0x2E0 0x2E4 0x2E8 0x2EC 0x2F0 0x2F4 0x2F8 0x2FC ) group.long ($2+0x1C00)++0x3 line.long 0x0 "REGG7_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xC0 0xC1 0xC2 0xC3 0xC4 0xC5 0xC6 0xC7 0xC8 0xC9 0xCA 0xCB 0xCC 0xCD 0xCE 0xCF )(list 0x300 0x304 0x308 0x30C 0x310 0x314 0x318 0x31C 0x320 0x324 0x328 0x32C 0x330 0x334 0x338 0x33C ) group.long ($2+0x1C00)++0x3 line.long 0x0 "REGG7_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xD0 0xD1 0xD2 0xD3 0xD4 0xD5 0xD6 0xD7 0xD8 0xD9 0xDA 0xDB 0xDC 0xDD 0xDE 0xDF )(list 0x340 0x344 0x348 0x34C 0x350 0x354 0x358 0x35C 0x360 0x364 0x368 0x36C 0x370 0x374 0x378 0x37C ) group.long ($2+0x1C00)++0x3 line.long 0x0 "REGG7_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xE0 0xE1 0xE2 0xE3 0xE4 0xE5 0xE6 0xE7 0xE8 0xE9 0xEA 0xEB 0xEC 0xED 0xEE 0xEF )(list 0x380 0x384 0x388 0x38C 0x390 0x394 0x398 0x39C 0x3A0 0x3A4 0x3A8 0x3AC 0x3B0 0x3B4 0x3B8 0x3BC ) group.long ($2+0x1C00)++0x3 line.long 0x0 "REGG7_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xF0 0xF1 0xF2 0xF3 0xF4 0xF5 0xF6 0xF7 0xF8 0xF9 0xFA 0xFB 0xFC 0xFD 0xFE 0xFF )(list 0x3C0 0x3C4 0x3C8 0x3CC 0x3D0 0x3D4 0x3D8 0x3DC 0x3E0 0x3E4 0x3E8 0x3EC 0x3F0 0x3F4 0x3F8 0x3FC ) group.long ($2+0x1C00)++0x3 line.long 0x0 "REGG7_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end group.long 0x2000++0x17 line.long 0x0 "GLB_CTL,This register provides global enable settings for permission control." bitfld.long 0x0 5. "DOM_CFG_LOCK,Lock write for DOM_CFG_MODE bit." "0,1" bitfld.long 0x0 4. "DOM_CFG_MODE,When enabled all the source setting can be configured by master from domain 0 if it is not locked. When disabled only resource manager can configure the permission of the resource." "0,1" bitfld.long 0x0 3. "PERCK_DIS_LOCK,Lock write for PERCK_DIS" "0,1" bitfld.long 0x0 2. "PERCK_DIS,All the permission check disable." "0,1" newline bitfld.long 0x0 1. "DOM_PRO_LOCK,Lock write for DOM_PRO_EN bit." "0,1" bitfld.long 0x0 0. "DOM_PRO_EN,When disabled no domain access permission check" "0,1" line.long 0x4 "RES_MGR,Resource manager register. This regster is used to assign resource manager for global resource access control" bitfld.long 0x4 17. "MID_LOCK,Lock write for MID_EN and MID_LOW and MID_HIG registers." "0,1" bitfld.long 0x4 16. "MID_EN,Master ID check enable" "0,1" bitfld.long 0x4 15. "PRI_PER_LOCK,Lock write for PRI_PER and PRI_PER_EN" "0,1" bitfld.long 0x4 13.--14. "PRI_PER,Resource manager privileged access permission. bit0 for privileged access bit1 for user access" "0,1,2,3" newline bitfld.long 0x4 12. "PRI_PER_EN,Resource manager privileged access permission enable." "0,1" bitfld.long 0x4 11. "SEC_PER_LOCK,Lock for SEC_PER and SEC_PER_LOCK" "0,1" bitfld.long 0x4 9.--10. "SEC_PER,Resource manager secure access permission. bit 0 for secure access bit 1 for non-secure access" "0,1,2,3" bitfld.long 0x4 8. "SEC_PER_EN,Resource manager secure permission enable" "0,1" bitfld.long 0x4 7. "DID_LOCK,Lock write for DID_EN and DID" "0,1" newline hexmask.long.byte 0x4 3.--6. 1. "DID,Resource manager domain ID" bitfld.long 0x4 2. "DID_EN,Resource manager Domain ID enable" "0,1" bitfld.long 0x4 1. "RES_MGR_EN_LOCK,Lock for RES_MGR_EN" "0,1" bitfld.long 0x4 0. "RES_MGR_EN,Resource manager enable. When the bit is disable there is no resource manager." "0,1" line.long 0x8 "RES_MGR_MA0,This register is used to assign master 0~31 as resource manager." hexmask.long 0x8 0.--31. 1. "MID,Assign master 0~31 for resource manager" line.long 0xC "RES_MGR_MA1,This register is used to assign master 32~63 as resource manager." hexmask.long 0xC 0.--31. 1. "MID,Indicate if master 32~63 is resource manager." line.long 0x10 "RES_MGR_MA2,This register is used to assign master 64~95 as resource manager." hexmask.long 0x10 0.--31. 1. "MID,Indicate if master 64~95 is resource manager." line.long 0x14 "RES_MGR_MA3,This register is used to assign master 96~127 as resource manager." hexmask.long 0x14 0.--31. 1. "MID,Indicate if master 96~127 is resource manager." repeat 8. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 )(list 0x0 0x14 0x28 0x3C 0x50 0x64 0x78 0x8C ) group.long ($2+0x2100)++0x3 line.long 0x0 "GRP_MGR_$1,Group Manager Register. This register is used to assign group manager for each domain" bitfld.long 0x0 17. "MID_LOCK,Lock write for MID_EN and MID_LOW and MID_HIG registers." "0,1" bitfld.long 0x0 16. "MID_EN,Master ID check enable" "0,1" bitfld.long 0x0 15. "PRI_PER_LOCK,Lock write for PRI_PER and PRI_PER_EN" "0,1" bitfld.long 0x0 13.--14. "PRI_PER,Group manager privileged access permission. bit0 for privileged access bit1 for user access" "0,1,2,3" newline bitfld.long 0x0 12. "PRI_PER_EN,Group manager privileged access permission enable." "0,1" bitfld.long 0x0 11. "SEC_PER_LOCK,Lock for SEC_PER and SEC_PER_LOCK" "0,1" bitfld.long 0x0 9.--10. "SEC_PER,Group manager secure access permission. bit 0 for secure access bit 1 for non-secure access" "0,1,2,3" bitfld.long 0x0 8. "SEC_PER_EN,Group manager secure permission enable" "0,1" bitfld.long 0x0 7. "DID_LOCK,Lock write for DID_EN and DID" "0,1" newline hexmask.long.byte 0x0 3.--6. 1. "DID,Group manager domain ID" bitfld.long 0x0 2. "DID_EN,Group manager Domain ID enable" "0,1" bitfld.long 0x0 1. "GRP_MGR_EN_LOCK,Lock write for GPR_MGR_EN" "0,1" bitfld.long 0x0 0. "GRP_MGR_EN,Group manager enable. When the bit is disable there is no resource manager." "0,1" repeat.end repeat 8. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 )(list 0x0 0x14 0x28 0x3C 0x50 0x64 0x78 0x8C ) group.long ($2+0x2104)++0x3 line.long 0x0 "GRP_MGR_MA0_$1,Assign master 0~31 for group manager 0" hexmask.long 0x0 0.--31. 1. "MID,Assign master 0~31 for resource manager" repeat.end repeat 8. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 )(list 0x0 0x14 0x28 0x3C 0x50 0x64 0x78 0x8C ) group.long ($2+0x2108)++0x3 line.long 0x0 "GRP_MGR_MA1_$1,Assign master 32~63 for group manager 0" hexmask.long 0x0 0.--31. 1. "MID,Indicate if master 32~63 is resource manager." repeat.end repeat 8. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 )(list 0x0 0x14 0x28 0x3C 0x50 0x64 0x78 0x8C ) group.long ($2+0x210C)++0x3 line.long 0x0 "GRP_MGR_MA2_$1,Assign master 64~95 for group manager 0" hexmask.long 0x0 0.--31. 1. "MID,Indicate if master 64~95 is resource manager." repeat.end repeat 8. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 )(list 0x0 0x14 0x28 0x3C 0x50 0x64 0x78 0x8C ) group.long ($2+0x2110)++0x3 line.long 0x0 "GRP_MGR_MA3_$1,Assign master 96~127 for group manager 0" hexmask.long 0x0 0.--31. 1. "MID,Indicate if master 96~127 is resource manager." repeat.end group.long 0x2200++0x3 line.long 0x0 "DOM_GID_0,Indicate which group domain 0 belong to" bitfld.long 0x0 3. "LOCK,Lock write for GID" "0,1" bitfld.long 0x0 0.--2. "GID,Group ID" "0,1,2,3,4,5,6,7" repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x18 0x30 0x48 0x60 0x78 0x90 0xA8 0xC0 0xD8 0xF0 0x108 0x120 0x138 0x150 0x168 ) group.long ($2+0x2204)++0x3 line.long 0x0 "DOM_OWN_$1,Assign owner for function domain 0." bitfld.long 0x0 17. "MID_LOCK,Lock write for MID_EN and MID_LOW and MID_HIG registers." "0,1" bitfld.long 0x0 16. "MID_EN,Master ID check enable" "0,1" bitfld.long 0x0 15. "PRI_PER_LOCK,Lock write for PRI_PER and PRI_PER_EN" "0,1" bitfld.long 0x0 13.--14. "PRI_PER,Group manager privileged access permission. bit0 for privileged access bit1 for user access" "0,1,2,3" newline bitfld.long 0x0 12. "PRI_PER_EN,Group manager privileged access permission enable." "0,1" bitfld.long 0x0 11. "SEC_PER_LOCK,Lock for SEC_PER and SEC_PER_LOCK" "0,1" bitfld.long 0x0 9.--10. "SEC_PER,Domain owner secure access permission. bit 0 for secure access bit 1 for non-secure access" "0,1,2,3" bitfld.long 0x0 8. "SEC_PER_EN,Domain owner secure permission enable" "0,1" newline bitfld.long 0x0 1. "DOM_OWN_EN_LOCK,Lock for DOM_OWN_EN" "0,1" bitfld.long 0x0 0. "DOM_OWN_EN,Domain owner enable. When the bit is disable there is no domain owner." "0,1" repeat.end repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x18 0x30 0x48 0x60 0x78 0x90 0xA8 0xC0 0xD8 0xF0 0x108 0x120 0x138 0x150 0x168 ) group.long ($2+0x2208)++0x3 line.long 0x0 "DOM_OWN_MA0_$1,Assign master 0~31 for domain owner 0" hexmask.long 0x0 0.--31. 1. "MID,Assign master 0~31 for resource manager" repeat.end repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x18 0x30 0x48 0x60 0x78 0x90 0xA8 0xC0 0xD8 0xF0 0x108 0x120 0x138 0x150 0x168 ) group.long ($2+0x220C)++0x3 line.long 0x0 "DOM_OWN_MA1_$1,Assign master 32~63 for domain owner 0" hexmask.long 0x0 0.--31. 1. "MID,Indicate if master 32~63 is resource manager." repeat.end repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x18 0x30 0x48 0x60 0x78 0x90 0xA8 0xC0 0xD8 0xF0 0x108 0x120 0x138 0x150 0x168 ) group.long ($2+0x2210)++0x3 line.long 0x0 "DOM_OWN_MA2_$1,Assign master 64~95 for domain owner 0" hexmask.long 0x0 0.--31. 1. "MID,Indicate if master 64~95 is resource manager." repeat.end repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x18 0x30 0x48 0x60 0x78 0x90 0xA8 0xC0 0xD8 0xF0 0x108 0x120 0x138 0x150 0x168 ) group.long ($2+0x2214)++0x3 line.long 0x0 "DOM_OWN_MA3_$1,Assign master 96~127 for domain owner 0" hexmask.long 0x0 0.--31. 1. "MID,Indicate if master 96~127 is resource manager." repeat.end group.long 0x2218++0x3 line.long 0x0 "DOM_GID_1,Indicate which group domain 1 belong to" bitfld.long 0x0 3. "LOCK,Lock write for GID" "0,1" bitfld.long 0x0 0.--2. "GID,Group ID" "0,1,2,3,4,5,6,7" group.long 0x2230++0x3 line.long 0x0 "DOM_GID_2,Indicate which group domain 2 belong to" bitfld.long 0x0 3. "LOCK,Lock write for GID" "0,1" bitfld.long 0x0 0.--2. "GID,Group ID" "0,1,2,3,4,5,6,7" group.long 0x2248++0x3 line.long 0x0 "DOM_GID_3,Indicate which group domain 3 belong to" bitfld.long 0x0 3. "LOCK,Lock write for GID" "0,1" bitfld.long 0x0 0.--2. "GID,Group ID" "0,1,2,3,4,5,6,7" group.long 0x2260++0x3 line.long 0x0 "DOM_GID_4,Indicate which group domain 4 belong to" bitfld.long 0x0 3. "LOCK,Lock write for GID" "0,1" bitfld.long 0x0 0.--2. "GID,Group ID" "0,1,2,3,4,5,6,7" group.long 0x2278++0x3 line.long 0x0 "DOM_GID_5,Indicate which group domain 5 belong to" bitfld.long 0x0 3. "LOCK,Lock write for GID" "0,1" bitfld.long 0x0 0.--2. "GID,Group ID" "0,1,2,3,4,5,6,7" group.long 0x2290++0x3 line.long 0x0 "DOM_GID_6,Indicate which group domain 6 belong to" bitfld.long 0x0 3. "LOCK,Lock write for GID" "0,1" bitfld.long 0x0 0.--2. "GID,Group ID" "0,1,2,3,4,5,6,7" group.long 0x22A8++0x3 line.long 0x0 "DOM_GID_7,Indicate which group domain 7 belong to" bitfld.long 0x0 3. "LOCK,Lock write for GID" "0,1" bitfld.long 0x0 0.--2. "GID,Group ID" "0,1,2,3,4,5,6,7" group.long 0x22C0++0x3 line.long 0x0 "DOM_GID_8,Indicate which group domain 8 belong to" bitfld.long 0x0 3. "LOCK,Lock write for GID" "0,1" bitfld.long 0x0 0.--2. "GID,Group ID" "0,1,2,3,4,5,6,7" group.long 0x22D8++0x3 line.long 0x0 "DOM_GID_9,Indicate which group domain 9 belong to" bitfld.long 0x0 3. "LOCK,Lock write for GID" "0,1" bitfld.long 0x0 0.--2. "GID,Group ID" "0,1,2,3,4,5,6,7" group.long 0x22F0++0x3 line.long 0x0 "DOM_GID_10,Indicate which group domain 10 belong to" bitfld.long 0x0 3. "LOCK,Lock write for GID" "0,1" bitfld.long 0x0 0.--2. "GID,Group ID" "0,1,2,3,4,5,6,7" group.long 0x2308++0x3 line.long 0x0 "DOM_GID_11,Indicate which group domain 11 belong to" bitfld.long 0x0 3. "LOCK,Lock write for GID" "0,1" bitfld.long 0x0 0.--2. "GID,Group ID" "0,1,2,3,4,5,6,7" group.long 0x2320++0x3 line.long 0x0 "DOM_GID_12,Indicate which group domain 12 belong to" bitfld.long 0x0 3. "LOCK,Lock write for GID" "0,1" bitfld.long 0x0 0.--2. "GID,Group ID" "0,1,2,3,4,5,6,7" group.long 0x2338++0x3 line.long 0x0 "DOM_GID_13,Indicate which group domain 13 belong to" bitfld.long 0x0 3. "LOCK,Lock write for GID" "0,1" bitfld.long 0x0 0.--2. "GID,Group ID" "0,1,2,3,4,5,6,7" group.long 0x2350++0x3 line.long 0x0 "DOM_GID_14,Indicate which group domain 14 belong to" bitfld.long 0x0 3. "LOCK,Lock write for GID" "0,1" bitfld.long 0x0 0.--2. "GID,Group ID" "0,1,2,3,4,5,6,7" group.long 0x2368++0x3 line.long 0x0 "DOM_GID_15,Indicate which group domain 15 belong to" bitfld.long 0x0 3. "LOCK,Lock write for GID" "0,1" bitfld.long 0x0 0.--2. "GID,Group ID" "0,1,2,3,4,5,6,7" repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x34 0x68 0x9C 0xD0 0x104 0x138 0x16C 0x1A0 0x1D4 0x208 0x23C 0x270 0x2A4 0x2D8 0x30C ) group.long ($2+0x2400)++0x3 line.long 0x0 "DOM_PER0_$1,Domain Permission Control. It can be only configured by resource manager and domain owner." bitfld.long 0x0 31. "DOM7_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 29.--30. "DOM7_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 28. "DOM7_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 27. "DOM6_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 25.--26. "DOM6_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" newline bitfld.long 0x0 24. "DOM6_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 23. "DOM5_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 21.--22. "DOM5_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 20. "DOM5_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 19. "DOM4_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" newline bitfld.long 0x0 17.--18. "DOM4_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM4_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 15. "DOM3_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 13.--14. "DOM3_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 12. "DOM3_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" newline bitfld.long 0x0 11. "DOM2_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 9.--10. "DOM2_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM2_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 7. "DOM1_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 5.--6. "DOM1_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" newline bitfld.long 0x0 4. "DOM1_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 3. "DOM0_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 1.--2. "DOM0_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM0_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" repeat.end repeat 16. (list 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1A 0x1B 0x1C 0x1D 0x1E 0x1F )(list 0x340 0x374 0x3A8 0x3DC 0x410 0x444 0x478 0x4AC 0x4E0 0x514 0x548 0x57C 0x5B0 0x5E4 0x618 0x64C ) group.long ($2+0x2400)++0x3 line.long 0x0 "DOM_PER0_$1,Domain Permission Control. It can be only configured by resource manager and domain owner." bitfld.long 0x0 31. "DOM7_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 29.--30. "DOM7_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 28. "DOM7_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 27. "DOM6_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 25.--26. "DOM6_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" newline bitfld.long 0x0 24. "DOM6_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 23. "DOM5_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 21.--22. "DOM5_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 20. "DOM5_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 19. "DOM4_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" newline bitfld.long 0x0 17.--18. "DOM4_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM4_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 15. "DOM3_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 13.--14. "DOM3_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 12. "DOM3_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" newline bitfld.long 0x0 11. "DOM2_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 9.--10. "DOM2_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM2_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 7. "DOM1_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 5.--6. "DOM1_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" newline bitfld.long 0x0 4. "DOM1_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 3. "DOM0_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 1.--2. "DOM0_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM0_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" repeat.end repeat 16. (list 0x20 0x21 0x22 0x23 0x24 0x25 0x26 0x27 0x28 0x29 0x2A 0x2B 0x2C 0x2D 0x2E 0x2F )(list 0x680 0x6B4 0x6E8 0x71C 0x750 0x784 0x7B8 0x7EC 0x820 0x854 0x888 0x8BC 0x8F0 0x924 0x958 0x98C ) group.long ($2+0x2400)++0x3 line.long 0x0 "DOM_PER0_$1,Domain Permission Control. It can be only configured by resource manager and domain owner." bitfld.long 0x0 31. "DOM7_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 29.--30. "DOM7_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 28. "DOM7_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 27. "DOM6_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 25.--26. "DOM6_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" newline bitfld.long 0x0 24. "DOM6_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 23. "DOM5_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 21.--22. "DOM5_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 20. "DOM5_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 19. "DOM4_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" newline bitfld.long 0x0 17.--18. "DOM4_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM4_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 15. "DOM3_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 13.--14. "DOM3_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 12. "DOM3_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" newline bitfld.long 0x0 11. "DOM2_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 9.--10. "DOM2_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM2_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 7. "DOM1_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 5.--6. "DOM1_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" newline bitfld.long 0x0 4. "DOM1_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 3. "DOM0_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 1.--2. "DOM0_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM0_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" repeat.end repeat 16. (list 0x30 0x31 0x32 0x33 0x34 0x35 0x36 0x37 0x38 0x39 0x3A 0x3B 0x3C 0x3D 0x3E 0x3F )(list 0x9C0 0x9F4 0xA28 0xA5C 0xA90 0xAC4 0xAF8 0xB2C 0xB60 0xB94 0xBC8 0xBFC 0xC30 0xC64 0xC98 0xCCC ) group.long ($2+0x2400)++0x3 line.long 0x0 "DOM_PER0_$1,Domain Permission Control. It can be only configured by resource manager and domain owner." bitfld.long 0x0 31. "DOM7_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 29.--30. "DOM7_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 28. "DOM7_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 27. "DOM6_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 25.--26. "DOM6_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" newline bitfld.long 0x0 24. "DOM6_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 23. "DOM5_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 21.--22. "DOM5_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 20. "DOM5_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 19. "DOM4_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" newline bitfld.long 0x0 17.--18. "DOM4_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM4_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 15. "DOM3_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 13.--14. "DOM3_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 12. "DOM3_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" newline bitfld.long 0x0 11. "DOM2_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 9.--10. "DOM2_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM2_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 7. "DOM1_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 5.--6. "DOM1_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" newline bitfld.long 0x0 4. "DOM1_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 3. "DOM0_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 1.--2. "DOM0_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM0_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" repeat.end repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x34 0x68 0x9C 0xD0 0x104 0x138 0x16C 0x1A0 0x1D4 0x208 0x23C 0x270 0x2A4 0x2D8 0x30C ) group.long ($2+0x2404)++0x3 line.long 0x0 "DOM_PER1_$1,Domain Permission Control. It can be only configured by resource manager and domain owner." bitfld.long 0x0 31. "DOM15_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 29.--30. "DOM15_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 28. "DOM15_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 27. "DOM14_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 25.--26. "DOM14_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" newline bitfld.long 0x0 24. "DOM14_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 23. "DOM13_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 21.--22. "DOM13_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 20. "DOM13_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 19. "DOM12_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" newline bitfld.long 0x0 17.--18. "DOM12_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM12_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 15. "DOM11_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 13.--14. "DOM11_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 12. "DOM11_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" newline bitfld.long 0x0 11. "DOM10_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 9.--10. "DOM10_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM10_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 7. "DOM9_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 5.--6. "DOM9_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" newline bitfld.long 0x0 4. "DOM9_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 3. "DOM8_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 1.--2. "DOM8_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM8_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" repeat.end repeat 16. (list 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1A 0x1B 0x1C 0x1D 0x1E 0x1F )(list 0x340 0x374 0x3A8 0x3DC 0x410 0x444 0x478 0x4AC 0x4E0 0x514 0x548 0x57C 0x5B0 0x5E4 0x618 0x64C ) group.long ($2+0x2404)++0x3 line.long 0x0 "DOM_PER1_$1,Domain Permission Control. It can be only configured by resource manager and domain owner." bitfld.long 0x0 31. "DOM15_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 29.--30. "DOM15_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 28. "DOM15_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 27. "DOM14_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 25.--26. "DOM14_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" newline bitfld.long 0x0 24. "DOM14_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 23. "DOM13_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 21.--22. "DOM13_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 20. "DOM13_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 19. "DOM12_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" newline bitfld.long 0x0 17.--18. "DOM12_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM12_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 15. "DOM11_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 13.--14. "DOM11_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 12. "DOM11_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" newline bitfld.long 0x0 11. "DOM10_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 9.--10. "DOM10_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM10_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 7. "DOM9_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 5.--6. "DOM9_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" newline bitfld.long 0x0 4. "DOM9_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 3. "DOM8_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 1.--2. "DOM8_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM8_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" repeat.end repeat 16. (list 0x20 0x21 0x22 0x23 0x24 0x25 0x26 0x27 0x28 0x29 0x2A 0x2B 0x2C 0x2D 0x2E 0x2F )(list 0x680 0x6B4 0x6E8 0x71C 0x750 0x784 0x7B8 0x7EC 0x820 0x854 0x888 0x8BC 0x8F0 0x924 0x958 0x98C ) group.long ($2+0x2404)++0x3 line.long 0x0 "DOM_PER1_$1,Domain Permission Control. It can be only configured by resource manager and domain owner." bitfld.long 0x0 31. "DOM15_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 29.--30. "DOM15_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 28. "DOM15_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 27. "DOM14_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 25.--26. "DOM14_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" newline bitfld.long 0x0 24. "DOM14_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 23. "DOM13_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 21.--22. "DOM13_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 20. "DOM13_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 19. "DOM12_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" newline bitfld.long 0x0 17.--18. "DOM12_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM12_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 15. "DOM11_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 13.--14. "DOM11_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 12. "DOM11_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" newline bitfld.long 0x0 11. "DOM10_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 9.--10. "DOM10_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM10_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 7. "DOM9_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 5.--6. "DOM9_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" newline bitfld.long 0x0 4. "DOM9_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 3. "DOM8_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 1.--2. "DOM8_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM8_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" repeat.end repeat 16. (list 0x30 0x31 0x32 0x33 0x34 0x35 0x36 0x37 0x38 0x39 0x3A 0x3B 0x3C 0x3D 0x3E 0x3F )(list 0x9C0 0x9F4 0xA28 0xA5C 0xA90 0xAC4 0xAF8 0xB2C 0xB60 0xB94 0xBC8 0xBFC 0xC30 0xC64 0xC98 0xCCC ) group.long ($2+0x2404)++0x3 line.long 0x0 "DOM_PER1_$1,Domain Permission Control. It can be only configured by resource manager and domain owner." bitfld.long 0x0 31. "DOM15_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 29.--30. "DOM15_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 28. "DOM15_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 27. "DOM14_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 25.--26. "DOM14_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" newline bitfld.long 0x0 24. "DOM14_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 23. "DOM13_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 21.--22. "DOM13_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 20. "DOM13_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 19. "DOM12_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" newline bitfld.long 0x0 17.--18. "DOM12_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM12_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 15. "DOM11_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 13.--14. "DOM11_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 12. "DOM11_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" newline bitfld.long 0x0 11. "DOM10_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 9.--10. "DOM10_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM10_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 7. "DOM9_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 5.--6. "DOM9_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" newline bitfld.long 0x0 4. "DOM9_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 3. "DOM8_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 1.--2. "DOM8_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM8_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" repeat.end repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x34 0x68 0x9C 0xD0 0x104 0x138 0x16C 0x1A0 0x1D4 0x208 0x23C 0x270 0x2A4 0x2D8 0x30C ) group.long ($2+0x2408)++0x3 line.long 0x0 "SEC_PER0_$1,This register is only used for resource manager to control secure access permission." bitfld.long 0x0 31. "DOM3_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM3_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM3_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM3_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM2_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM2_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM2_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM2_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM1_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM1_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM1_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM1_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM0_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM0_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM0_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM0_SEC_EN,Domain secure permission control enable" "0,1" repeat.end repeat 16. (list 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1A 0x1B 0x1C 0x1D 0x1E 0x1F )(list 0x340 0x374 0x3A8 0x3DC 0x410 0x444 0x478 0x4AC 0x4E0 0x514 0x548 0x57C 0x5B0 0x5E4 0x618 0x64C ) group.long ($2+0x2408)++0x3 line.long 0x0 "SEC_PER0_$1,This register is only used for resource manager to control secure access permission." bitfld.long 0x0 31. "DOM3_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM3_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM3_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM3_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM2_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM2_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM2_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM2_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM1_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM1_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM1_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM1_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM0_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM0_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM0_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM0_SEC_EN,Domain secure permission control enable" "0,1" repeat.end repeat 16. (list 0x20 0x21 0x22 0x23 0x24 0x25 0x26 0x27 0x28 0x29 0x2A 0x2B 0x2C 0x2D 0x2E 0x2F )(list 0x680 0x6B4 0x6E8 0x71C 0x750 0x784 0x7B8 0x7EC 0x820 0x854 0x888 0x8BC 0x8F0 0x924 0x958 0x98C ) group.long ($2+0x2408)++0x3 line.long 0x0 "SEC_PER0_$1,This register is only used for resource manager to control secure access permission." bitfld.long 0x0 31. "DOM3_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM3_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM3_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM3_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM2_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM2_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM2_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM2_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM1_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM1_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM1_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM1_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM0_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM0_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM0_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM0_SEC_EN,Domain secure permission control enable" "0,1" repeat.end repeat 16. (list 0x30 0x31 0x32 0x33 0x34 0x35 0x36 0x37 0x38 0x39 0x3A 0x3B 0x3C 0x3D 0x3E 0x3F )(list 0x9C0 0x9F4 0xA28 0xA5C 0xA90 0xAC4 0xAF8 0xB2C 0xB60 0xB94 0xBC8 0xBFC 0xC30 0xC64 0xC98 0xCCC ) group.long ($2+0x2408)++0x3 line.long 0x0 "SEC_PER0_$1,This register is only used for resource manager to control secure access permission." bitfld.long 0x0 31. "DOM3_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM3_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM3_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM3_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM2_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM2_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM2_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM2_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM1_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM1_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM1_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM1_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM0_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM0_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM0_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM0_SEC_EN,Domain secure permission control enable" "0,1" repeat.end repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x34 0x68 0x9C 0xD0 0x104 0x138 0x16C 0x1A0 0x1D4 0x208 0x23C 0x270 0x2A4 0x2D8 0x30C ) group.long ($2+0x240C)++0x3 line.long 0x0 "SEC_PER1_$1,This register is only used for resource manager to control secure access permission." bitfld.long 0x0 31. "DOM7_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM7_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM7_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM7_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM6_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM6_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM6_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM6_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM5_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM5_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM5_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM5_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM4_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM4_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM4_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM4_SEC_EN,Domain secure permission control enable" "0,1" repeat.end repeat 16. (list 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1A 0x1B 0x1C 0x1D 0x1E 0x1F )(list 0x340 0x374 0x3A8 0x3DC 0x410 0x444 0x478 0x4AC 0x4E0 0x514 0x548 0x57C 0x5B0 0x5E4 0x618 0x64C ) group.long ($2+0x240C)++0x3 line.long 0x0 "SEC_PER1_$1,This register is only used for resource manager to control secure access permission." bitfld.long 0x0 31. "DOM7_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM7_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM7_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM7_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM6_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM6_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM6_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM6_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM5_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM5_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM5_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM5_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM4_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM4_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM4_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM4_SEC_EN,Domain secure permission control enable" "0,1" repeat.end repeat 16. (list 0x20 0x21 0x22 0x23 0x24 0x25 0x26 0x27 0x28 0x29 0x2A 0x2B 0x2C 0x2D 0x2E 0x2F )(list 0x680 0x6B4 0x6E8 0x71C 0x750 0x784 0x7B8 0x7EC 0x820 0x854 0x888 0x8BC 0x8F0 0x924 0x958 0x98C ) group.long ($2+0x240C)++0x3 line.long 0x0 "SEC_PER1_$1,This register is only used for resource manager to control secure access permission." bitfld.long 0x0 31. "DOM7_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM7_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM7_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM7_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM6_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM6_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM6_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM6_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM5_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM5_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM5_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM5_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM4_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM4_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM4_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM4_SEC_EN,Domain secure permission control enable" "0,1" repeat.end repeat 16. (list 0x30 0x31 0x32 0x33 0x34 0x35 0x36 0x37 0x38 0x39 0x3A 0x3B 0x3C 0x3D 0x3E 0x3F )(list 0x9C0 0x9F4 0xA28 0xA5C 0xA90 0xAC4 0xAF8 0xB2C 0xB60 0xB94 0xBC8 0xBFC 0xC30 0xC64 0xC98 0xCCC ) group.long ($2+0x240C)++0x3 line.long 0x0 "SEC_PER1_$1,This register is only used for resource manager to control secure access permission." bitfld.long 0x0 31. "DOM7_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM7_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM7_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM7_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM6_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM6_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM6_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM6_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM5_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM5_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM5_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM5_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM4_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM4_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM4_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM4_SEC_EN,Domain secure permission control enable" "0,1" repeat.end repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x34 0x68 0x9C 0xD0 0x104 0x138 0x16C 0x1A0 0x1D4 0x208 0x23C 0x270 0x2A4 0x2D8 0x30C ) group.long ($2+0x2410)++0x3 line.long 0x0 "SEC_PER2_$1,This register is only used for resource manager to control secure access permission." bitfld.long 0x0 31. "DOM11_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM11_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM11_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM11_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM10_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM10_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM10_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM10_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM9_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM9_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM9_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM9_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM8_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM8_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM8_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM8_SEC_EN,Domain secure permission control enable" "0,1" repeat.end repeat 16. (list 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1A 0x1B 0x1C 0x1D 0x1E 0x1F )(list 0x340 0x374 0x3A8 0x3DC 0x410 0x444 0x478 0x4AC 0x4E0 0x514 0x548 0x57C 0x5B0 0x5E4 0x618 0x64C ) group.long ($2+0x2410)++0x3 line.long 0x0 "SEC_PER2_$1,This register is only used for resource manager to control secure access permission." bitfld.long 0x0 31. "DOM11_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM11_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM11_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM11_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM10_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM10_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM10_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM10_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM9_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM9_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM9_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM9_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM8_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM8_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM8_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM8_SEC_EN,Domain secure permission control enable" "0,1" repeat.end repeat 16. (list 0x20 0x21 0x22 0x23 0x24 0x25 0x26 0x27 0x28 0x29 0x2A 0x2B 0x2C 0x2D 0x2E 0x2F )(list 0x680 0x6B4 0x6E8 0x71C 0x750 0x784 0x7B8 0x7EC 0x820 0x854 0x888 0x8BC 0x8F0 0x924 0x958 0x98C ) group.long ($2+0x2410)++0x3 line.long 0x0 "SEC_PER2_$1,This register is only used for resource manager to control secure access permission." bitfld.long 0x0 31. "DOM11_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM11_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM11_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM11_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM10_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM10_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM10_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM10_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM9_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM9_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM9_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM9_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM8_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM8_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM8_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM8_SEC_EN,Domain secure permission control enable" "0,1" repeat.end repeat 16. (list 0x30 0x31 0x32 0x33 0x34 0x35 0x36 0x37 0x38 0x39 0x3A 0x3B 0x3C 0x3D 0x3E 0x3F )(list 0x9C0 0x9F4 0xA28 0xA5C 0xA90 0xAC4 0xAF8 0xB2C 0xB60 0xB94 0xBC8 0xBFC 0xC30 0xC64 0xC98 0xCCC ) group.long ($2+0x2410)++0x3 line.long 0x0 "SEC_PER2_$1,This register is only used for resource manager to control secure access permission." bitfld.long 0x0 31. "DOM11_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM11_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM11_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM11_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM10_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM10_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM10_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM10_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM9_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM9_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM9_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM9_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM8_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM8_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM8_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM8_SEC_EN,Domain secure permission control enable" "0,1" repeat.end repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x34 0x68 0x9C 0xD0 0x104 0x138 0x16C 0x1A0 0x1D4 0x208 0x23C 0x270 0x2A4 0x2D8 0x30C ) group.long ($2+0x2414)++0x3 line.long 0x0 "SEC_PER3_$1,This register is only used for resource manager to control secure access permission." bitfld.long 0x0 31. "DOM15_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM15_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM15_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM15_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM14_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM14_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM14_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM14_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM13_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM13_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM13_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM13_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM12_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM12_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM12_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM12_SEC_EN,Domain secure permission control enable" "0,1" repeat.end repeat 16. (list 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1A 0x1B 0x1C 0x1D 0x1E 0x1F )(list 0x340 0x374 0x3A8 0x3DC 0x410 0x444 0x478 0x4AC 0x4E0 0x514 0x548 0x57C 0x5B0 0x5E4 0x618 0x64C ) group.long ($2+0x2414)++0x3 line.long 0x0 "SEC_PER3_$1,This register is only used for resource manager to control secure access permission." bitfld.long 0x0 31. "DOM15_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM15_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM15_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM15_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM14_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM14_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM14_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM14_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM13_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM13_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM13_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM13_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM12_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM12_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM12_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM12_SEC_EN,Domain secure permission control enable" "0,1" repeat.end repeat 16. (list 0x20 0x21 0x22 0x23 0x24 0x25 0x26 0x27 0x28 0x29 0x2A 0x2B 0x2C 0x2D 0x2E 0x2F )(list 0x680 0x6B4 0x6E8 0x71C 0x750 0x784 0x7B8 0x7EC 0x820 0x854 0x888 0x8BC 0x8F0 0x924 0x958 0x98C ) group.long ($2+0x2414)++0x3 line.long 0x0 "SEC_PER3_$1,This register is only used for resource manager to control secure access permission." bitfld.long 0x0 31. "DOM15_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM15_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM15_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM15_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM14_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM14_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM14_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM14_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM13_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM13_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM13_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM13_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM12_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM12_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM12_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM12_SEC_EN,Domain secure permission control enable" "0,1" repeat.end repeat 16. (list 0x30 0x31 0x32 0x33 0x34 0x35 0x36 0x37 0x38 0x39 0x3A 0x3B 0x3C 0x3D 0x3E 0x3F )(list 0x9C0 0x9F4 0xA28 0xA5C 0xA90 0xAC4 0xAF8 0xB2C 0xB60 0xB94 0xBC8 0xBFC 0xC30 0xC64 0xC98 0xCCC ) group.long ($2+0x2414)++0x3 line.long 0x0 "SEC_PER3_$1,This register is only used for resource manager to control secure access permission." bitfld.long 0x0 31. "DOM15_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM15_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM15_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM15_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM14_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM14_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM14_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM14_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM13_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM13_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM13_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM13_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM12_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM12_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM12_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM12_SEC_EN,Domain secure permission control enable" "0,1" repeat.end repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x34 0x68 0x9C 0xD0 0x104 0x138 0x16C 0x1A0 0x1D4 0x208 0x23C 0x270 0x2A4 0x2D8 0x30C ) group.long ($2+0x2418)++0x3 line.long 0x0 "PRI_PER0_$1,This register is only used for resource manager to control privileged access permission." bitfld.long 0x0 31. "DOM3_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM3_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM3_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM3_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM2_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM2_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM2_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM2_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM1_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM1_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM1_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM1_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM0_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM0_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM0_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM0_PRI_EN,Domain privileged permission control enable" "0,1" repeat.end repeat 16. (list 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1A 0x1B 0x1C 0x1D 0x1E 0x1F )(list 0x340 0x374 0x3A8 0x3DC 0x410 0x444 0x478 0x4AC 0x4E0 0x514 0x548 0x57C 0x5B0 0x5E4 0x618 0x64C ) group.long ($2+0x2418)++0x3 line.long 0x0 "PRI_PER0_$1,This register is only used for resource manager to control privileged access permission." bitfld.long 0x0 31. "DOM3_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM3_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM3_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM3_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM2_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM2_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM2_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM2_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM1_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM1_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM1_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM1_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM0_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM0_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM0_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM0_PRI_EN,Domain privileged permission control enable" "0,1" repeat.end repeat 16. (list 0x20 0x21 0x22 0x23 0x24 0x25 0x26 0x27 0x28 0x29 0x2A 0x2B 0x2C 0x2D 0x2E 0x2F )(list 0x680 0x6B4 0x6E8 0x71C 0x750 0x784 0x7B8 0x7EC 0x820 0x854 0x888 0x8BC 0x8F0 0x924 0x958 0x98C ) group.long ($2+0x2418)++0x3 line.long 0x0 "PRI_PER0_$1,This register is only used for resource manager to control privileged access permission." bitfld.long 0x0 31. "DOM3_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM3_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM3_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM3_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM2_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM2_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM2_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM2_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM1_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM1_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM1_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM1_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM0_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM0_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM0_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM0_PRI_EN,Domain privileged permission control enable" "0,1" repeat.end repeat 16. (list 0x30 0x31 0x32 0x33 0x34 0x35 0x36 0x37 0x38 0x39 0x3A 0x3B 0x3C 0x3D 0x3E 0x3F )(list 0x9C0 0x9F4 0xA28 0xA5C 0xA90 0xAC4 0xAF8 0xB2C 0xB60 0xB94 0xBC8 0xBFC 0xC30 0xC64 0xC98 0xCCC ) group.long ($2+0x2418)++0x3 line.long 0x0 "PRI_PER0_$1,This register is only used for resource manager to control privileged access permission." bitfld.long 0x0 31. "DOM3_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM3_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM3_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM3_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM2_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM2_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM2_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM2_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM1_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM1_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM1_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM1_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM0_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM0_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM0_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM0_PRI_EN,Domain privileged permission control enable" "0,1" repeat.end repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x34 0x68 0x9C 0xD0 0x104 0x138 0x16C 0x1A0 0x1D4 0x208 0x23C 0x270 0x2A4 0x2D8 0x30C ) group.long ($2+0x241C)++0x3 line.long 0x0 "PRI_PER1_$1,This register is only used for resource manager to control privileged access permission." bitfld.long 0x0 31. "DOM7_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM7_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM7_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM7_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM6_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM6_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM6_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM6_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM5_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM5_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM5_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM5_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM4_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM4_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM4_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM4_PRI_EN,Domain privileged permission control enable" "0,1" repeat.end repeat 16. (list 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1A 0x1B 0x1C 0x1D 0x1E 0x1F )(list 0x340 0x374 0x3A8 0x3DC 0x410 0x444 0x478 0x4AC 0x4E0 0x514 0x548 0x57C 0x5B0 0x5E4 0x618 0x64C ) group.long ($2+0x241C)++0x3 line.long 0x0 "PRI_PER1_$1,This register is only used for resource manager to control privileged access permission." bitfld.long 0x0 31. "DOM7_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM7_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM7_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM7_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM6_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM6_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM6_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM6_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM5_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM5_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM5_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM5_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM4_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM4_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM4_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM4_PRI_EN,Domain privileged permission control enable" "0,1" repeat.end repeat 16. (list 0x20 0x21 0x22 0x23 0x24 0x25 0x26 0x27 0x28 0x29 0x2A 0x2B 0x2C 0x2D 0x2E 0x2F )(list 0x680 0x6B4 0x6E8 0x71C 0x750 0x784 0x7B8 0x7EC 0x820 0x854 0x888 0x8BC 0x8F0 0x924 0x958 0x98C ) group.long ($2+0x241C)++0x3 line.long 0x0 "PRI_PER1_$1,This register is only used for resource manager to control privileged access permission." bitfld.long 0x0 31. "DOM7_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM7_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM7_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM7_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM6_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM6_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM6_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM6_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM5_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM5_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM5_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM5_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM4_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM4_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM4_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM4_PRI_EN,Domain privileged permission control enable" "0,1" repeat.end repeat 16. (list 0x30 0x31 0x32 0x33 0x34 0x35 0x36 0x37 0x38 0x39 0x3A 0x3B 0x3C 0x3D 0x3E 0x3F )(list 0x9C0 0x9F4 0xA28 0xA5C 0xA90 0xAC4 0xAF8 0xB2C 0xB60 0xB94 0xBC8 0xBFC 0xC30 0xC64 0xC98 0xCCC ) group.long ($2+0x241C)++0x3 line.long 0x0 "PRI_PER1_$1,This register is only used for resource manager to control privileged access permission." bitfld.long 0x0 31. "DOM7_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM7_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM7_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM7_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM6_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM6_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM6_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM6_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM5_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM5_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM5_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM5_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM4_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM4_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM4_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM4_PRI_EN,Domain privileged permission control enable" "0,1" repeat.end repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x34 0x68 0x9C 0xD0 0x104 0x138 0x16C 0x1A0 0x1D4 0x208 0x23C 0x270 0x2A4 0x2D8 0x30C ) group.long ($2+0x2420)++0x3 line.long 0x0 "PRI_PER2_$1,This register is only used for resource manager to control privileged access permission." bitfld.long 0x0 31. "DOM11_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM11_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM11_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM11_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM10_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM10_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM10_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM10_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM9_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM9_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM9_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM9_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM8_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM8_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM8_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM8_PRI_EN,Domain privileged permission control enable" "0,1" repeat.end repeat 16. (list 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1A 0x1B 0x1C 0x1D 0x1E 0x1F )(list 0x340 0x374 0x3A8 0x3DC 0x410 0x444 0x478 0x4AC 0x4E0 0x514 0x548 0x57C 0x5B0 0x5E4 0x618 0x64C ) group.long ($2+0x2420)++0x3 line.long 0x0 "PRI_PER2_$1,This register is only used for resource manager to control privileged access permission." bitfld.long 0x0 31. "DOM11_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM11_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM11_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM11_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM10_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM10_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM10_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM10_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM9_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM9_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM9_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM9_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM8_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM8_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM8_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM8_PRI_EN,Domain privileged permission control enable" "0,1" repeat.end repeat 16. (list 0x20 0x21 0x22 0x23 0x24 0x25 0x26 0x27 0x28 0x29 0x2A 0x2B 0x2C 0x2D 0x2E 0x2F )(list 0x680 0x6B4 0x6E8 0x71C 0x750 0x784 0x7B8 0x7EC 0x820 0x854 0x888 0x8BC 0x8F0 0x924 0x958 0x98C ) group.long ($2+0x2420)++0x3 line.long 0x0 "PRI_PER2_$1,This register is only used for resource manager to control privileged access permission." bitfld.long 0x0 31. "DOM11_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM11_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM11_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM11_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM10_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM10_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM10_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM10_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM9_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM9_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM9_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM9_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM8_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM8_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM8_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM8_PRI_EN,Domain privileged permission control enable" "0,1" repeat.end repeat 16. (list 0x30 0x31 0x32 0x33 0x34 0x35 0x36 0x37 0x38 0x39 0x3A 0x3B 0x3C 0x3D 0x3E 0x3F )(list 0x9C0 0x9F4 0xA28 0xA5C 0xA90 0xAC4 0xAF8 0xB2C 0xB60 0xB94 0xBC8 0xBFC 0xC30 0xC64 0xC98 0xCCC ) group.long ($2+0x2420)++0x3 line.long 0x0 "PRI_PER2_$1,This register is only used for resource manager to control privileged access permission." bitfld.long 0x0 31. "DOM11_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM11_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM11_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM11_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM10_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM10_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM10_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM10_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM9_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM9_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM9_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM9_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM8_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM8_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM8_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM8_PRI_EN,Domain privileged permission control enable" "0,1" repeat.end repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x34 0x68 0x9C 0xD0 0x104 0x138 0x16C 0x1A0 0x1D4 0x208 0x23C 0x270 0x2A4 0x2D8 0x30C ) group.long ($2+0x2424)++0x3 line.long 0x0 "PRI_PER3_$1,This register is only used for resource manager to control privileged access permission." bitfld.long 0x0 31. "DOM15_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM15_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM15_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM15_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM14_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM14_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM14_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM14_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM13_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM13_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM13_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM13_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM12_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM12_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM12_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM12_PRI_EN,Domain privileged permission control enable" "0,1" repeat.end repeat 16. (list 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1A 0x1B 0x1C 0x1D 0x1E 0x1F )(list 0x340 0x374 0x3A8 0x3DC 0x410 0x444 0x478 0x4AC 0x4E0 0x514 0x548 0x57C 0x5B0 0x5E4 0x618 0x64C ) group.long ($2+0x2424)++0x3 line.long 0x0 "PRI_PER3_$1,This register is only used for resource manager to control privileged access permission." bitfld.long 0x0 31. "DOM15_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM15_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM15_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM15_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM14_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM14_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM14_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM14_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM13_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM13_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM13_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM13_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM12_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM12_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM12_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM12_PRI_EN,Domain privileged permission control enable" "0,1" repeat.end repeat 16. (list 0x20 0x21 0x22 0x23 0x24 0x25 0x26 0x27 0x28 0x29 0x2A 0x2B 0x2C 0x2D 0x2E 0x2F )(list 0x680 0x6B4 0x6E8 0x71C 0x750 0x784 0x7B8 0x7EC 0x820 0x854 0x888 0x8BC 0x8F0 0x924 0x958 0x98C ) group.long ($2+0x2424)++0x3 line.long 0x0 "PRI_PER3_$1,This register is only used for resource manager to control privileged access permission." bitfld.long 0x0 31. "DOM15_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM15_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM15_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM15_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM14_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM14_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM14_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM14_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM13_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM13_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM13_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM13_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM12_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM12_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM12_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM12_PRI_EN,Domain privileged permission control enable" "0,1" repeat.end repeat 16. (list 0x30 0x31 0x32 0x33 0x34 0x35 0x36 0x37 0x38 0x39 0x3A 0x3B 0x3C 0x3D 0x3E 0x3F )(list 0x9C0 0x9F4 0xA28 0xA5C 0xA90 0xAC4 0xAF8 0xB2C 0xB60 0xB94 0xBC8 0xBFC 0xC30 0xC64 0xC98 0xCCC ) group.long ($2+0x2424)++0x3 line.long 0x0 "PRI_PER3_$1,This register is only used for resource manager to control privileged access permission." bitfld.long 0x0 31. "DOM15_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM15_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM15_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM15_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM14_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM14_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM14_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM14_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM13_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM13_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM13_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM13_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM12_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM12_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM12_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM12_PRI_EN,Domain privileged permission control enable" "0,1" repeat.end repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x34 0x68 0x9C 0xD0 0x104 0x138 0x16C 0x1A0 0x1D4 0x208 0x23C 0x270 0x2A4 0x2D8 0x30C ) group.long ($2+0x2428)++0x3 line.long 0x0 "DOM_SEC_PER_$1,This register is only used for domain master to control secure access permission. When the domain master write this register. it only changes the secure permission for itself. When the domain master read this register. it gets permission.." bitfld.long 0x0 7. "DOM_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" newline bitfld.long 0x0 0. "DOM_SEC_EN,Domain secure permission control enable" "0,1" repeat.end repeat 16. (list 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1A 0x1B 0x1C 0x1D 0x1E 0x1F )(list 0x340 0x374 0x3A8 0x3DC 0x410 0x444 0x478 0x4AC 0x4E0 0x514 0x548 0x57C 0x5B0 0x5E4 0x618 0x64C ) group.long ($2+0x2428)++0x3 line.long 0x0 "DOM_SEC_PER_$1,This register is only used for domain master to control secure access permission. When the domain master write this register. it only changes the secure permission for itself. When the domain master read this register. it gets permission.." bitfld.long 0x0 7. "DOM_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" newline bitfld.long 0x0 0. "DOM_SEC_EN,Domain secure permission control enable" "0,1" repeat.end repeat 16. (list 0x20 0x21 0x22 0x23 0x24 0x25 0x26 0x27 0x28 0x29 0x2A 0x2B 0x2C 0x2D 0x2E 0x2F )(list 0x680 0x6B4 0x6E8 0x71C 0x750 0x784 0x7B8 0x7EC 0x820 0x854 0x888 0x8BC 0x8F0 0x924 0x958 0x98C ) group.long ($2+0x2428)++0x3 line.long 0x0 "DOM_SEC_PER_$1,This register is only used for domain master to control secure access permission. When the domain master write this register. it only changes the secure permission for itself. When the domain master read this register. it gets permission.." bitfld.long 0x0 7. "DOM_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" newline bitfld.long 0x0 0. "DOM_SEC_EN,Domain secure permission control enable" "0,1" repeat.end repeat 16. (list 0x30 0x31 0x32 0x33 0x34 0x35 0x36 0x37 0x38 0x39 0x3A 0x3B 0x3C 0x3D 0x3E 0x3F )(list 0x9C0 0x9F4 0xA28 0xA5C 0xA90 0xAC4 0xAF8 0xB2C 0xB60 0xB94 0xBC8 0xBFC 0xC30 0xC64 0xC98 0xCCC ) group.long ($2+0x2428)++0x3 line.long 0x0 "DOM_SEC_PER_$1,This register is only used for domain master to control secure access permission. When the domain master write this register. it only changes the secure permission for itself. When the domain master read this register. it gets permission.." bitfld.long 0x0 7. "DOM_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" newline bitfld.long 0x0 0. "DOM_SEC_EN,Domain secure permission control enable" "0,1" repeat.end repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x34 0x68 0x9C 0xD0 0x104 0x138 0x16C 0x1A0 0x1D4 0x208 0x23C 0x270 0x2A4 0x2D8 0x30C ) group.long ($2+0x242C)++0x3 line.long 0x0 "DOM_PRI_PER_$1,This register is only used for domain master to control secure access permission. When the domain master write this register. it only changes the secure permission for itself. When the domain master read this register. it gets permission.." bitfld.long 0x0 7. "DOM_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" newline bitfld.long 0x0 0. "DOM_PRI_EN,Domain privileged permission control enable" "0,1" repeat.end repeat 16. (list 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1A 0x1B 0x1C 0x1D 0x1E 0x1F )(list 0x340 0x374 0x3A8 0x3DC 0x410 0x444 0x478 0x4AC 0x4E0 0x514 0x548 0x57C 0x5B0 0x5E4 0x618 0x64C ) group.long ($2+0x242C)++0x3 line.long 0x0 "DOM_PRI_PER_$1,This register is only used for domain master to control secure access permission. When the domain master write this register. it only changes the secure permission for itself. When the domain master read this register. it gets permission.." bitfld.long 0x0 7. "DOM_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" newline bitfld.long 0x0 0. "DOM_PRI_EN,Domain privileged permission control enable" "0,1" repeat.end repeat 16. (list 0x20 0x21 0x22 0x23 0x24 0x25 0x26 0x27 0x28 0x29 0x2A 0x2B 0x2C 0x2D 0x2E 0x2F )(list 0x680 0x6B4 0x6E8 0x71C 0x750 0x784 0x7B8 0x7EC 0x820 0x854 0x888 0x8BC 0x8F0 0x924 0x958 0x98C ) group.long ($2+0x242C)++0x3 line.long 0x0 "DOM_PRI_PER_$1,This register is only used for domain master to control secure access permission. When the domain master write this register. it only changes the secure permission for itself. When the domain master read this register. it gets permission.." bitfld.long 0x0 7. "DOM_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" newline bitfld.long 0x0 0. "DOM_PRI_EN,Domain privileged permission control enable" "0,1" repeat.end repeat 16. (list 0x30 0x31 0x32 0x33 0x34 0x35 0x36 0x37 0x38 0x39 0x3A 0x3B 0x3C 0x3D 0x3E 0x3F )(list 0x9C0 0x9F4 0xA28 0xA5C 0xA90 0xAC4 0xAF8 0xB2C 0xB60 0xB94 0xBC8 0xBFC 0xC30 0xC64 0xC98 0xCCC ) group.long ($2+0x242C)++0x3 line.long 0x0 "DOM_PRI_PER_$1,This register is only used for domain master to control secure access permission. When the domain master write this register. it only changes the secure permission for itself. When the domain master read this register. it gets permission.." bitfld.long 0x0 7. "DOM_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" newline bitfld.long 0x0 0. "DOM_PRI_EN,Domain privileged permission control enable" "0,1" repeat.end repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x34 0x68 0x9C 0xD0 0x104 0x138 0x16C 0x1A0 0x1D4 0x208 0x23C 0x270 0x2A4 0x2D8 0x30C ) group.long ($2+0x2430)++0x3 line.long 0x0 "DOM_ASSIGN_$1,Use to assign domain for accessing DOM_SEC_PER and DOM_PRI_PER register. Only resource manager. group manager and domain owner can access this register. For write. group manager must write its owen domain ID. otherwise write accessing will.." hexmask.long.byte 0x0 0.--3. 1. "DID,accessing DOM_SEC_PER and DOM_PRI_PER register" repeat.end repeat 16. (list 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1A 0x1B 0x1C 0x1D 0x1E 0x1F )(list 0x340 0x374 0x3A8 0x3DC 0x410 0x444 0x478 0x4AC 0x4E0 0x514 0x548 0x57C 0x5B0 0x5E4 0x618 0x64C ) group.long ($2+0x2430)++0x3 line.long 0x0 "DOM_ASSIGN_$1,Use to assign domain for accessing DOM_SEC_PER and DOM_PRI_PER register. Only resource manager. group manager and domain owner can access this register. For write. group manager must write its owen domain ID. otherwise write accessing will.." hexmask.long.byte 0x0 0.--3. 1. "DID,accessing DOM_SEC_PER and DOM_PRI_PER register" repeat.end repeat 16. (list 0x20 0x21 0x22 0x23 0x24 0x25 0x26 0x27 0x28 0x29 0x2A 0x2B 0x2C 0x2D 0x2E 0x2F )(list 0x680 0x6B4 0x6E8 0x71C 0x750 0x784 0x7B8 0x7EC 0x820 0x854 0x888 0x8BC 0x8F0 0x924 0x958 0x98C ) group.long ($2+0x2430)++0x3 line.long 0x0 "DOM_ASSIGN_$1,Use to assign domain for accessing DOM_SEC_PER and DOM_PRI_PER register. Only resource manager. group manager and domain owner can access this register. For write. group manager must write its owen domain ID. otherwise write accessing will.." hexmask.long.byte 0x0 0.--3. 1. "DID,accessing DOM_SEC_PER and DOM_PRI_PER register" repeat.end repeat 16. (list 0x30 0x31 0x32 0x33 0x34 0x35 0x36 0x37 0x38 0x39 0x3A 0x3B 0x3C 0x3D 0x3E 0x3F )(list 0x9C0 0x9F4 0xA28 0xA5C 0xA90 0xAC4 0xAF8 0xB2C 0xB60 0xB94 0xBC8 0xBFC 0xC30 0xC64 0xC98 0xCCC ) group.long ($2+0x2430)++0x3 line.long 0x0 "DOM_ASSIGN_$1,Use to assign domain for accessing DOM_SEC_PER and DOM_PRI_PER register. Only resource manager. group manager and domain owner can access this register. For write. group manager must write its owen domain ID. otherwise write accessing will.." hexmask.long.byte 0x0 0.--3. 1. "DID,accessing DOM_SEC_PER and DOM_PRI_PER register" repeat.end repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x38 0x70 0xA8 0xE0 0x118 0x150 0x188 0x1C0 0x1F8 0x230 0x268 0x2A0 0x2D8 0x310 0x348 ) group.long ($2+0x3100)++0x3 line.long 0x0 "RGN_DOM_$1,Assign domain for peripheral. It can be only configured by resource and group manager" bitfld.long 0x0 31. "LOCK,When this bit is set lock write for all the bits in the register." "0,1" bitfld.long 0x0 4. "SET,Set together with DID would change permission of this resource to following setting: 1) Domain access control enabled. 2) Read/Write allowed for the domain owner. 3) Read/Write not allowed for all the other domains. If this bit is not set only DID.." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Assign domain for peripheral" repeat.end repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x38 0x70 0xA8 0xE0 0x118 0x150 0x188 0x1C0 0x1F8 0x230 0x268 0x2A0 0x2D8 0x310 0x348 ) group.long ($2+0x3104)++0x3 line.long 0x0 "RGN_DOM_PER0_$1,Domain Permission Control. It can be only configured by resource manager and domain owner." bitfld.long 0x0 31. "DOM7_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 29.--30. "DOM7_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 28. "DOM7_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 27. "DOM6_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 25.--26. "DOM6_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" newline bitfld.long 0x0 24. "DOM6_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 23. "DOM5_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 21.--22. "DOM5_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 20. "DOM5_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 19. "DOM4_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" newline bitfld.long 0x0 17.--18. "DOM4_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM4_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 15. "DOM3_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 13.--14. "DOM3_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 12. "DOM3_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" newline bitfld.long 0x0 11. "DOM2_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 9.--10. "DOM2_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM2_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 7. "DOM1_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 5.--6. "DOM1_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" newline bitfld.long 0x0 4. "DOM1_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 3. "DOM0_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 1.--2. "DOM0_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM0_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" repeat.end repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x38 0x70 0xA8 0xE0 0x118 0x150 0x188 0x1C0 0x1F8 0x230 0x268 0x2A0 0x2D8 0x310 0x348 ) group.long ($2+0x3108)++0x3 line.long 0x0 "RGN_DOM_PER1_$1,Domain Permission Control. It can be only configured by resource manager and domain owner." bitfld.long 0x0 31. "DOM15_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 29.--30. "DOM15_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 28. "DOM15_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 27. "DOM14_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 25.--26. "DOM14_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" newline bitfld.long 0x0 24. "DOM14_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 23. "DOM13_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 21.--22. "DOM13_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 20. "DOM13_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 19. "DOM12_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" newline bitfld.long 0x0 17.--18. "DOM12_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM12_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 15. "DOM11_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 13.--14. "DOM11_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 12. "DOM11_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" newline bitfld.long 0x0 11. "DOM10_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 9.--10. "DOM10_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM10_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 7. "DOM9_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 5.--6. "DOM9_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" newline bitfld.long 0x0 4. "DOM9_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 3. "DOM8_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 1.--2. "DOM8_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM8_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" repeat.end repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x38 0x70 0xA8 0xE0 0x118 0x150 0x188 0x1C0 0x1F8 0x230 0x268 0x2A0 0x2D8 0x310 0x348 ) group.long ($2+0x310C)++0x3 line.long 0x0 "RGN_SEC_PER0_$1,This register is only used for resource manager to control secure access permission." bitfld.long 0x0 31. "DOM3_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM3_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM3_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM3_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM2_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM2_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM2_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM2_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM1_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM1_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM1_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM1_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM0_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM0_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM0_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM0_SEC_EN,Domain secure permission control enable" "0,1" repeat.end repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x38 0x70 0xA8 0xE0 0x118 0x150 0x188 0x1C0 0x1F8 0x230 0x268 0x2A0 0x2D8 0x310 0x348 ) group.long ($2+0x3110)++0x3 line.long 0x0 "RGN_SEC_PER1_$1,This register is only used for resource manager to control secure access permission." bitfld.long 0x0 31. "DOM7_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM7_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM7_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM7_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM6_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM6_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM6_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM6_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM5_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM5_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM5_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM5_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM4_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM4_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM4_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM4_SEC_EN,Domain secure permission control enable" "0,1" repeat.end repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x38 0x70 0xA8 0xE0 0x118 0x150 0x188 0x1C0 0x1F8 0x230 0x268 0x2A0 0x2D8 0x310 0x348 ) group.long ($2+0x3114)++0x3 line.long 0x0 "RGN_SEC_PER2_$1,This register is only used for resource manager to control secure access permission." bitfld.long 0x0 31. "DOM11_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM11_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM11_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM11_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM10_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM10_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM10_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM10_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM9_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM9_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM9_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM9_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM8_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM8_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM8_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM8_SEC_EN,Domain secure permission control enable" "0,1" repeat.end repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x38 0x70 0xA8 0xE0 0x118 0x150 0x188 0x1C0 0x1F8 0x230 0x268 0x2A0 0x2D8 0x310 0x348 ) group.long ($2+0x3118)++0x3 line.long 0x0 "RGN_SEC_PER3_$1,This register is only used for resource manager to control secure access permission." bitfld.long 0x0 31. "DOM15_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM15_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM15_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM15_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM14_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM14_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM14_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM14_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM13_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM13_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM13_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM13_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM12_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM12_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM12_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM12_SEC_EN,Domain secure permission control enable" "0,1" repeat.end repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x38 0x70 0xA8 0xE0 0x118 0x150 0x188 0x1C0 0x1F8 0x230 0x268 0x2A0 0x2D8 0x310 0x348 ) group.long ($2+0x311C)++0x3 line.long 0x0 "RGN_PRI_PER0_$1,This register is only used for resource manager to control privileged access permission." bitfld.long 0x0 31. "DOM3_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM3_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM3_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM3_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM2_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM2_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM2_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM2_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM1_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM1_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM1_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM1_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM0_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM0_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM0_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM0_PRI_EN,Domain privileged permission control enable" "0,1" repeat.end repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x38 0x70 0xA8 0xE0 0x118 0x150 0x188 0x1C0 0x1F8 0x230 0x268 0x2A0 0x2D8 0x310 0x348 ) group.long ($2+0x3120)++0x3 line.long 0x0 "RGN_PRI_PER1_$1,This register is only used for resource manager to control privileged access permission." bitfld.long 0x0 31. "DOM7_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM7_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM7_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM7_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM6_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM6_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM6_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM6_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM5_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM5_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM5_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM5_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM4_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM4_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM4_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM4_PRI_EN,Domain privileged permission control enable" "0,1" repeat.end repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x38 0x70 0xA8 0xE0 0x118 0x150 0x188 0x1C0 0x1F8 0x230 0x268 0x2A0 0x2D8 0x310 0x348 ) group.long ($2+0x3124)++0x3 line.long 0x0 "RGN_PRI_PER2_$1,This register is only used for resource manager to control privileged access permission." bitfld.long 0x0 31. "DOM11_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM11_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM11_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM11_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM10_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM10_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM10_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM10_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM9_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM9_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM9_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM9_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM8_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM8_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM8_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM8_PRI_EN,Domain privileged permission control enable" "0,1" repeat.end repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x38 0x70 0xA8 0xE0 0x118 0x150 0x188 0x1C0 0x1F8 0x230 0x268 0x2A0 0x2D8 0x310 0x348 ) group.long ($2+0x3128)++0x3 line.long 0x0 "RGN_PRI_PER3_$1,This register is only used for resource manager to control privileged access permission." bitfld.long 0x0 31. "DOM15_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM15_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM15_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM15_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM14_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM14_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM14_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM14_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM13_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM13_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM13_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM13_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM12_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM12_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM12_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM12_PRI_EN,Domain privileged permission control enable" "0,1" repeat.end repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x38 0x70 0xA8 0xE0 0x118 0x150 0x188 0x1C0 0x1F8 0x230 0x268 0x2A0 0x2D8 0x310 0x348 ) group.long ($2+0x312C)++0x3 line.long 0x0 "RGN_DOM_SEC_PER_$1,This register is only used for domain master to control secure access permission. When the domain master write this register. it only changes the secure permission for itself. When the domain master read this register. it gets.." bitfld.long 0x0 7. "DOM_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" newline bitfld.long 0x0 0. "DOM_SEC_EN,Domain secure permission control enable" "0,1" repeat.end repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x38 0x70 0xA8 0xE0 0x118 0x150 0x188 0x1C0 0x1F8 0x230 0x268 0x2A0 0x2D8 0x310 0x348 ) group.long ($2+0x3130)++0x3 line.long 0x0 "RGN_DOM_PRI_PER_$1,This register is only used for domain master to control secure access permission. When the domain master write this register. it only changes the secure permission for itself. When the domain master read this register. it gets.." bitfld.long 0x0 7. "DOM_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" newline bitfld.long 0x0 0. "DOM_PRI_EN,Domain privileged permission control enable" "0,1" repeat.end repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x38 0x70 0xA8 0xE0 0x118 0x150 0x188 0x1C0 0x1F8 0x230 0x268 0x2A0 0x2D8 0x310 0x348 ) group.long ($2+0x3134)++0x3 line.long 0x0 "RGN_DOM_ASSIGN_$1,Use to assign domain for accessing DOM_SEC_PER and DOM_PRI_PER register. Only resource manager. group manager and domain owner can access this register. For write. group manager must write its owen domain ID. otherwise write accessing.." hexmask.long.byte 0x0 0.--3. 1. "DID,accessing DOM_SEC_PER and DOM_PRI_PER register" repeat.end tree.end tree "RPC_DISP_CLKGEN" base ad:0xF6A00000 repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x4 0x8 0xC 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C ) group.long ($2)++0x3 line.long 0x0 "REGG0_DOM_$1,Assign domain for CKGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1A 0x1B 0x1C 0x1D 0x1E 0x1F )(list 0x40 0x44 0x48 0x4C 0x50 0x54 0x58 0x5C 0x60 0x64 0x68 0x6C 0x70 0x74 0x78 0x7C ) group.long ($2)++0x3 line.long 0x0 "REGG0_DOM_$1,Assign domain for CKGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x20 0x21 0x22 0x23 0x24 0x25 0x26 0x27 0x28 0x29 0x2A 0x2B 0x2C 0x2D 0x2E 0x2F )(list 0x80 0x84 0x88 0x8C 0x90 0x94 0x98 0x9C 0xA0 0xA4 0xA8 0xAC 0xB0 0xB4 0xB8 0xBC ) group.long ($2)++0x3 line.long 0x0 "REGG0_DOM_$1,Assign domain for CKGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x30 0x31 0x32 0x33 0x34 0x35 0x36 0x37 0x38 0x39 0x3A 0x3B 0x3C 0x3D 0x3E 0x3F )(list 0xC0 0xC4 0xC8 0xCC 0xD0 0xD4 0xD8 0xDC 0xE0 0xE4 0xE8 0xEC 0xF0 0xF4 0xF8 0xFC ) group.long ($2)++0x3 line.long 0x0 "REGG0_DOM_$1,Assign domain for CKGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x40 0x41 0x42 0x43 0x44 0x45 0x46 0x47 0x48 0x49 0x4A 0x4B 0x4C 0x4D 0x4E 0x4F )(list 0x100 0x104 0x108 0x10C 0x110 0x114 0x118 0x11C 0x120 0x124 0x128 0x12C 0x130 0x134 0x138 0x13C ) group.long ($2)++0x3 line.long 0x0 "REGG0_DOM_$1,Assign domain for CKGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x50 0x51 0x52 0x53 0x54 0x55 0x56 0x57 0x58 0x59 0x5A 0x5B 0x5C 0x5D 0x5E 0x5F )(list 0x140 0x144 0x148 0x14C 0x150 0x154 0x158 0x15C 0x160 0x164 0x168 0x16C 0x170 0x174 0x178 0x17C ) group.long ($2)++0x3 line.long 0x0 "REGG0_DOM_$1,Assign domain for CKGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x60 0x61 0x62 0x63 0x64 0x65 0x66 0x67 0x68 0x69 0x6A 0x6B 0x6C 0x6D 0x6E 0x6F )(list 0x180 0x184 0x188 0x18C 0x190 0x194 0x198 0x19C 0x1A0 0x1A4 0x1A8 0x1AC 0x1B0 0x1B4 0x1B8 0x1BC ) group.long ($2)++0x3 line.long 0x0 "REGG0_DOM_$1,Assign domain for CKGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x70 0x71 0x72 0x73 0x74 0x75 0x76 0x77 0x78 0x79 0x7A 0x7B 0x7C 0x7D 0x7E 0x7F )(list 0x1C0 0x1C4 0x1C8 0x1CC 0x1D0 0x1D4 0x1D8 0x1DC 0x1E0 0x1E4 0x1E8 0x1EC 0x1F0 0x1F4 0x1F8 0x1FC ) group.long ($2)++0x3 line.long 0x0 "REGG0_DOM_$1,Assign domain for CKGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x80 0x81 0x82 0x83 0x84 0x85 0x86 0x87 0x88 0x89 0x8A 0x8B 0x8C 0x8D 0x8E 0x8F )(list 0x200 0x204 0x208 0x20C 0x210 0x214 0x218 0x21C 0x220 0x224 0x228 0x22C 0x230 0x234 0x238 0x23C ) group.long ($2)++0x3 line.long 0x0 "REGG0_DOM_$1,Assign domain for CKGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x90 0x91 0x92 0x93 0x94 0x95 0x96 0x97 0x98 0x99 0x9A 0x9B 0x9C 0x9D 0x9E 0x9F )(list 0x240 0x244 0x248 0x24C 0x250 0x254 0x258 0x25C 0x260 0x264 0x268 0x26C 0x270 0x274 0x278 0x27C ) group.long ($2)++0x3 line.long 0x0 "REGG0_DOM_$1,Assign domain for CKGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xA0 0xA1 0xA2 0xA3 0xA4 0xA5 0xA6 0xA7 0xA8 0xA9 0xAA 0xAB 0xAC 0xAD 0xAE 0xAF )(list 0x280 0x284 0x288 0x28C 0x290 0x294 0x298 0x29C 0x2A0 0x2A4 0x2A8 0x2AC 0x2B0 0x2B4 0x2B8 0x2BC ) group.long ($2)++0x3 line.long 0x0 "REGG0_DOM_$1,Assign domain for CKGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xB0 0xB1 0xB2 0xB3 0xB4 0xB5 0xB6 0xB7 0xB8 0xB9 0xBA 0xBB 0xBC 0xBD 0xBE 0xBF )(list 0x2C0 0x2C4 0x2C8 0x2CC 0x2D0 0x2D4 0x2D8 0x2DC 0x2E0 0x2E4 0x2E8 0x2EC 0x2F0 0x2F4 0x2F8 0x2FC ) group.long ($2)++0x3 line.long 0x0 "REGG0_DOM_$1,Assign domain for CKGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xC0 0xC1 0xC2 0xC3 0xC4 0xC5 0xC6 0xC7 0xC8 0xC9 0xCA 0xCB 0xCC 0xCD 0xCE 0xCF )(list 0x300 0x304 0x308 0x30C 0x310 0x314 0x318 0x31C 0x320 0x324 0x328 0x32C 0x330 0x334 0x338 0x33C ) group.long ($2)++0x3 line.long 0x0 "REGG0_DOM_$1,Assign domain for CKGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xD0 0xD1 0xD2 0xD3 0xD4 0xD5 0xD6 0xD7 0xD8 0xD9 0xDA 0xDB 0xDC 0xDD 0xDE 0xDF )(list 0x340 0x344 0x348 0x34C 0x350 0x354 0x358 0x35C 0x360 0x364 0x368 0x36C 0x370 0x374 0x378 0x37C ) group.long ($2)++0x3 line.long 0x0 "REGG0_DOM_$1,Assign domain for CKGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xE0 0xE1 0xE2 0xE3 0xE4 0xE5 0xE6 0xE7 0xE8 0xE9 0xEA 0xEB 0xEC 0xED 0xEE 0xEF )(list 0x380 0x384 0x388 0x38C 0x390 0x394 0x398 0x39C 0x3A0 0x3A4 0x3A8 0x3AC 0x3B0 0x3B4 0x3B8 0x3BC ) group.long ($2)++0x3 line.long 0x0 "REGG0_DOM_$1,Assign domain for CKGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xF0 0xF1 0xF2 0xF3 0xF4 0xF5 0xF6 0xF7 0xF8 0xF9 0xFA 0xFB 0xFC 0xFD 0xFE 0xFF )(list 0x3C0 0x3C4 0x3C8 0x3CC 0x3D0 0x3D4 0x3D8 0x3DC 0x3E0 0x3E4 0x3E8 0x3EC 0x3F0 0x3F4 0x3F8 0x3FC ) group.long ($2)++0x3 line.long 0x0 "REGG0_DOM_$1,Assign domain for CKGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x4 0x8 0xC 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C ) group.long ($2+0x400)++0x3 line.long 0x0 "REGG1_DOM_$1,Assign domain for CKGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1A 0x1B 0x1C 0x1D 0x1E 0x1F )(list 0x40 0x44 0x48 0x4C 0x50 0x54 0x58 0x5C 0x60 0x64 0x68 0x6C 0x70 0x74 0x78 0x7C ) group.long ($2+0x400)++0x3 line.long 0x0 "REGG1_DOM_$1,Assign domain for CKGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x20 0x21 0x22 0x23 0x24 0x25 0x26 0x27 0x28 0x29 0x2A 0x2B 0x2C 0x2D 0x2E 0x2F )(list 0x80 0x84 0x88 0x8C 0x90 0x94 0x98 0x9C 0xA0 0xA4 0xA8 0xAC 0xB0 0xB4 0xB8 0xBC ) group.long ($2+0x400)++0x3 line.long 0x0 "REGG1_DOM_$1,Assign domain for CKGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x30 0x31 0x32 0x33 0x34 0x35 0x36 0x37 0x38 0x39 0x3A 0x3B 0x3C 0x3D 0x3E 0x3F )(list 0xC0 0xC4 0xC8 0xCC 0xD0 0xD4 0xD8 0xDC 0xE0 0xE4 0xE8 0xEC 0xF0 0xF4 0xF8 0xFC ) group.long ($2+0x400)++0x3 line.long 0x0 "REGG1_DOM_$1,Assign domain for CKGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x40 0x41 0x42 0x43 0x44 0x45 0x46 0x47 0x48 0x49 0x4A 0x4B 0x4C 0x4D 0x4E 0x4F )(list 0x100 0x104 0x108 0x10C 0x110 0x114 0x118 0x11C 0x120 0x124 0x128 0x12C 0x130 0x134 0x138 0x13C ) group.long ($2+0x400)++0x3 line.long 0x0 "REGG1_DOM_$1,Assign domain for CKGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x50 0x51 0x52 0x53 0x54 0x55 0x56 0x57 0x58 0x59 0x5A 0x5B 0x5C 0x5D 0x5E 0x5F )(list 0x140 0x144 0x148 0x14C 0x150 0x154 0x158 0x15C 0x160 0x164 0x168 0x16C 0x170 0x174 0x178 0x17C ) group.long ($2+0x400)++0x3 line.long 0x0 "REGG1_DOM_$1,Assign domain for CKGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x60 0x61 0x62 0x63 0x64 0x65 0x66 0x67 0x68 0x69 0x6A 0x6B 0x6C 0x6D 0x6E 0x6F )(list 0x180 0x184 0x188 0x18C 0x190 0x194 0x198 0x19C 0x1A0 0x1A4 0x1A8 0x1AC 0x1B0 0x1B4 0x1B8 0x1BC ) group.long ($2+0x400)++0x3 line.long 0x0 "REGG1_DOM_$1,Assign domain for CKGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x70 0x71 0x72 0x73 0x74 0x75 0x76 0x77 0x78 0x79 0x7A 0x7B 0x7C 0x7D 0x7E 0x7F )(list 0x1C0 0x1C4 0x1C8 0x1CC 0x1D0 0x1D4 0x1D8 0x1DC 0x1E0 0x1E4 0x1E8 0x1EC 0x1F0 0x1F4 0x1F8 0x1FC ) group.long ($2+0x400)++0x3 line.long 0x0 "REGG1_DOM_$1,Assign domain for CKGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x80 0x81 0x82 0x83 0x84 0x85 0x86 0x87 0x88 0x89 0x8A 0x8B 0x8C 0x8D 0x8E 0x8F )(list 0x200 0x204 0x208 0x20C 0x210 0x214 0x218 0x21C 0x220 0x224 0x228 0x22C 0x230 0x234 0x238 0x23C ) group.long ($2+0x400)++0x3 line.long 0x0 "REGG1_DOM_$1,Assign domain for CKGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x90 0x91 0x92 0x93 0x94 0x95 0x96 0x97 0x98 0x99 0x9A 0x9B 0x9C 0x9D 0x9E 0x9F )(list 0x240 0x244 0x248 0x24C 0x250 0x254 0x258 0x25C 0x260 0x264 0x268 0x26C 0x270 0x274 0x278 0x27C ) group.long ($2+0x400)++0x3 line.long 0x0 "REGG1_DOM_$1,Assign domain for CKGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xA0 0xA1 0xA2 0xA3 0xA4 0xA5 0xA6 0xA7 0xA8 0xA9 0xAA 0xAB 0xAC 0xAD 0xAE 0xAF )(list 0x280 0x284 0x288 0x28C 0x290 0x294 0x298 0x29C 0x2A0 0x2A4 0x2A8 0x2AC 0x2B0 0x2B4 0x2B8 0x2BC ) group.long ($2+0x400)++0x3 line.long 0x0 "REGG1_DOM_$1,Assign domain for CKGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xB0 0xB1 0xB2 0xB3 0xB4 0xB5 0xB6 0xB7 0xB8 0xB9 0xBA 0xBB 0xBC 0xBD 0xBE 0xBF )(list 0x2C0 0x2C4 0x2C8 0x2CC 0x2D0 0x2D4 0x2D8 0x2DC 0x2E0 0x2E4 0x2E8 0x2EC 0x2F0 0x2F4 0x2F8 0x2FC ) group.long ($2+0x400)++0x3 line.long 0x0 "REGG1_DOM_$1,Assign domain for CKGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xC0 0xC1 0xC2 0xC3 0xC4 0xC5 0xC6 0xC7 0xC8 0xC9 0xCA 0xCB 0xCC 0xCD 0xCE 0xCF )(list 0x300 0x304 0x308 0x30C 0x310 0x314 0x318 0x31C 0x320 0x324 0x328 0x32C 0x330 0x334 0x338 0x33C ) group.long ($2+0x400)++0x3 line.long 0x0 "REGG1_DOM_$1,Assign domain for CKGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xD0 0xD1 0xD2 0xD3 0xD4 0xD5 0xD6 0xD7 0xD8 0xD9 0xDA 0xDB 0xDC 0xDD 0xDE 0xDF )(list 0x340 0x344 0x348 0x34C 0x350 0x354 0x358 0x35C 0x360 0x364 0x368 0x36C 0x370 0x374 0x378 0x37C ) group.long ($2+0x400)++0x3 line.long 0x0 "REGG1_DOM_$1,Assign domain for CKGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xE0 0xE1 0xE2 0xE3 0xE4 0xE5 0xE6 0xE7 0xE8 0xE9 0xEA 0xEB 0xEC 0xED 0xEE 0xEF )(list 0x380 0x384 0x388 0x38C 0x390 0x394 0x398 0x39C 0x3A0 0x3A4 0x3A8 0x3AC 0x3B0 0x3B4 0x3B8 0x3BC ) group.long ($2+0x400)++0x3 line.long 0x0 "REGG1_DOM_$1,Assign domain for CKGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xF0 0xF1 0xF2 0xF3 0xF4 0xF5 0xF6 0xF7 0xF8 0xF9 0xFA 0xFB 0xFC 0xFD 0xFE 0xFF )(list 0x3C0 0x3C4 0x3C8 0x3CC 0x3D0 0x3D4 0x3D8 0x3DC 0x3E0 0x3E4 0x3E8 0x3EC 0x3F0 0x3F4 0x3F8 0x3FC ) group.long ($2+0x400)++0x3 line.long 0x0 "REGG1_DOM_$1,Assign domain for CKGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x4 0x8 0xC 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C ) group.long ($2+0x800)++0x3 line.long 0x0 "REGG2_DOM_$1,Assign domain for SCR registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1A 0x1B 0x1C 0x1D 0x1E 0x1F )(list 0x40 0x44 0x48 0x4C 0x50 0x54 0x58 0x5C 0x60 0x64 0x68 0x6C 0x70 0x74 0x78 0x7C ) group.long ($2+0x800)++0x3 line.long 0x0 "REGG2_DOM_$1,Assign domain for SCR registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x20 0x21 0x22 0x23 0x24 0x25 0x26 0x27 0x28 0x29 0x2A 0x2B 0x2C 0x2D 0x2E 0x2F )(list 0x80 0x84 0x88 0x8C 0x90 0x94 0x98 0x9C 0xA0 0xA4 0xA8 0xAC 0xB0 0xB4 0xB8 0xBC ) group.long ($2+0x800)++0x3 line.long 0x0 "REGG2_DOM_$1,Assign domain for SCR registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x30 0x31 0x32 0x33 0x34 0x35 0x36 0x37 0x38 0x39 0x3A 0x3B 0x3C 0x3D 0x3E 0x3F )(list 0xC0 0xC4 0xC8 0xCC 0xD0 0xD4 0xD8 0xDC 0xE0 0xE4 0xE8 0xEC 0xF0 0xF4 0xF8 0xFC ) group.long ($2+0x800)++0x3 line.long 0x0 "REGG2_DOM_$1,Assign domain for SCR registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x40 0x41 0x42 0x43 0x44 0x45 0x46 0x47 0x48 0x49 0x4A 0x4B 0x4C 0x4D 0x4E 0x4F )(list 0x100 0x104 0x108 0x10C 0x110 0x114 0x118 0x11C 0x120 0x124 0x128 0x12C 0x130 0x134 0x138 0x13C ) group.long ($2+0x800)++0x3 line.long 0x0 "REGG2_DOM_$1,Assign domain for SCR registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x50 0x51 0x52 0x53 0x54 0x55 0x56 0x57 0x58 0x59 0x5A 0x5B 0x5C 0x5D 0x5E 0x5F )(list 0x140 0x144 0x148 0x14C 0x150 0x154 0x158 0x15C 0x160 0x164 0x168 0x16C 0x170 0x174 0x178 0x17C ) group.long ($2+0x800)++0x3 line.long 0x0 "REGG2_DOM_$1,Assign domain for SCR registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x60 0x61 0x62 0x63 0x64 0x65 0x66 0x67 0x68 0x69 0x6A 0x6B 0x6C 0x6D 0x6E 0x6F )(list 0x180 0x184 0x188 0x18C 0x190 0x194 0x198 0x19C 0x1A0 0x1A4 0x1A8 0x1AC 0x1B0 0x1B4 0x1B8 0x1BC ) group.long ($2+0x800)++0x3 line.long 0x0 "REGG2_DOM_$1,Assign domain for SCR registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x70 0x71 0x72 0x73 0x74 0x75 0x76 0x77 0x78 0x79 0x7A 0x7B 0x7C 0x7D 0x7E 0x7F )(list 0x1C0 0x1C4 0x1C8 0x1CC 0x1D0 0x1D4 0x1D8 0x1DC 0x1E0 0x1E4 0x1E8 0x1EC 0x1F0 0x1F4 0x1F8 0x1FC ) group.long ($2+0x800)++0x3 line.long 0x0 "REGG2_DOM_$1,Assign domain for SCR registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x80 0x81 0x82 0x83 0x84 0x85 0x86 0x87 0x88 0x89 0x8A 0x8B 0x8C 0x8D 0x8E 0x8F )(list 0x200 0x204 0x208 0x20C 0x210 0x214 0x218 0x21C 0x220 0x224 0x228 0x22C 0x230 0x234 0x238 0x23C ) group.long ($2+0x800)++0x3 line.long 0x0 "REGG2_DOM_$1,Assign domain for SCR registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x90 0x91 0x92 0x93 0x94 0x95 0x96 0x97 0x98 0x99 0x9A 0x9B 0x9C 0x9D 0x9E 0x9F )(list 0x240 0x244 0x248 0x24C 0x250 0x254 0x258 0x25C 0x260 0x264 0x268 0x26C 0x270 0x274 0x278 0x27C ) group.long ($2+0x800)++0x3 line.long 0x0 "REGG2_DOM_$1,Assign domain for SCR registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xA0 0xA1 0xA2 0xA3 0xA4 0xA5 0xA6 0xA7 0xA8 0xA9 0xAA 0xAB 0xAC 0xAD 0xAE 0xAF )(list 0x280 0x284 0x288 0x28C 0x290 0x294 0x298 0x29C 0x2A0 0x2A4 0x2A8 0x2AC 0x2B0 0x2B4 0x2B8 0x2BC ) group.long ($2+0x800)++0x3 line.long 0x0 "REGG2_DOM_$1,Assign domain for SCR registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xB0 0xB1 0xB2 0xB3 0xB4 0xB5 0xB6 0xB7 0xB8 0xB9 0xBA 0xBB 0xBC 0xBD 0xBE 0xBF )(list 0x2C0 0x2C4 0x2C8 0x2CC 0x2D0 0x2D4 0x2D8 0x2DC 0x2E0 0x2E4 0x2E8 0x2EC 0x2F0 0x2F4 0x2F8 0x2FC ) group.long ($2+0x800)++0x3 line.long 0x0 "REGG2_DOM_$1,Assign domain for SCR registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xC0 0xC1 0xC2 0xC3 0xC4 0xC5 0xC6 0xC7 0xC8 0xC9 0xCA 0xCB 0xCC 0xCD 0xCE 0xCF )(list 0x300 0x304 0x308 0x30C 0x310 0x314 0x318 0x31C 0x320 0x324 0x328 0x32C 0x330 0x334 0x338 0x33C ) group.long ($2+0x800)++0x3 line.long 0x0 "REGG2_DOM_$1,Assign domain for SCR registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xD0 0xD1 0xD2 0xD3 0xD4 0xD5 0xD6 0xD7 0xD8 0xD9 0xDA 0xDB 0xDC 0xDD 0xDE 0xDF )(list 0x340 0x344 0x348 0x34C 0x350 0x354 0x358 0x35C 0x360 0x364 0x368 0x36C 0x370 0x374 0x378 0x37C ) group.long ($2+0x800)++0x3 line.long 0x0 "REGG2_DOM_$1,Assign domain for SCR registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xE0 0xE1 0xE2 0xE3 0xE4 0xE5 0xE6 0xE7 0xE8 0xE9 0xEA 0xEB 0xEC 0xED 0xEE 0xEF )(list 0x380 0x384 0x388 0x38C 0x390 0x394 0x398 0x39C 0x3A0 0x3A4 0x3A8 0x3AC 0x3B0 0x3B4 0x3B8 0x3BC ) group.long ($2+0x800)++0x3 line.long 0x0 "REGG2_DOM_$1,Assign domain for SCR registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xF0 0xF1 0xF2 0xF3 0xF4 0xF5 0xF6 0xF7 0xF8 0xF9 0xFA 0xFB 0xFC 0xFD 0xFE 0xFF )(list 0x3C0 0x3C4 0x3C8 0x3CC 0x3D0 0x3D4 0x3D8 0x3DC 0x3E0 0x3E4 0x3E8 0x3EC 0x3F0 0x3F4 0x3F8 0x3FC ) group.long ($2+0x800)++0x3 line.long 0x0 "REGG2_DOM_$1,Assign domain for SCR registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x4 0x8 0xC 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C ) group.long ($2+0xC00)++0x3 line.long 0x0 "REGG3_DOM_$1,Assign domain for SCR registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1A 0x1B 0x1C 0x1D 0x1E 0x1F )(list 0x40 0x44 0x48 0x4C 0x50 0x54 0x58 0x5C 0x60 0x64 0x68 0x6C 0x70 0x74 0x78 0x7C ) group.long ($2+0xC00)++0x3 line.long 0x0 "REGG3_DOM_$1,Assign domain for SCR registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x20 0x21 0x22 0x23 0x24 0x25 0x26 0x27 0x28 0x29 0x2A 0x2B 0x2C 0x2D 0x2E 0x2F )(list 0x80 0x84 0x88 0x8C 0x90 0x94 0x98 0x9C 0xA0 0xA4 0xA8 0xAC 0xB0 0xB4 0xB8 0xBC ) group.long ($2+0xC00)++0x3 line.long 0x0 "REGG3_DOM_$1,Assign domain for SCR registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x30 0x31 0x32 0x33 0x34 0x35 0x36 0x37 0x38 0x39 0x3A 0x3B 0x3C 0x3D 0x3E 0x3F )(list 0xC0 0xC4 0xC8 0xCC 0xD0 0xD4 0xD8 0xDC 0xE0 0xE4 0xE8 0xEC 0xF0 0xF4 0xF8 0xFC ) group.long ($2+0xC00)++0x3 line.long 0x0 "REGG3_DOM_$1,Assign domain for SCR registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x40 0x41 0x42 0x43 0x44 0x45 0x46 0x47 0x48 0x49 0x4A 0x4B 0x4C 0x4D 0x4E 0x4F )(list 0x100 0x104 0x108 0x10C 0x110 0x114 0x118 0x11C 0x120 0x124 0x128 0x12C 0x130 0x134 0x138 0x13C ) group.long ($2+0xC00)++0x3 line.long 0x0 "REGG3_DOM_$1,Assign domain for SCR registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x50 0x51 0x52 0x53 0x54 0x55 0x56 0x57 0x58 0x59 0x5A 0x5B 0x5C 0x5D 0x5E 0x5F )(list 0x140 0x144 0x148 0x14C 0x150 0x154 0x158 0x15C 0x160 0x164 0x168 0x16C 0x170 0x174 0x178 0x17C ) group.long ($2+0xC00)++0x3 line.long 0x0 "REGG3_DOM_$1,Assign domain for SCR registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x60 0x61 0x62 0x63 0x64 0x65 0x66 0x67 0x68 0x69 0x6A 0x6B 0x6C 0x6D 0x6E 0x6F )(list 0x180 0x184 0x188 0x18C 0x190 0x194 0x198 0x19C 0x1A0 0x1A4 0x1A8 0x1AC 0x1B0 0x1B4 0x1B8 0x1BC ) group.long ($2+0xC00)++0x3 line.long 0x0 "REGG3_DOM_$1,Assign domain for SCR registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x70 0x71 0x72 0x73 0x74 0x75 0x76 0x77 0x78 0x79 0x7A 0x7B 0x7C 0x7D 0x7E 0x7F )(list 0x1C0 0x1C4 0x1C8 0x1CC 0x1D0 0x1D4 0x1D8 0x1DC 0x1E0 0x1E4 0x1E8 0x1EC 0x1F0 0x1F4 0x1F8 0x1FC ) group.long ($2+0xC00)++0x3 line.long 0x0 "REGG3_DOM_$1,Assign domain for SCR registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x80 0x81 0x82 0x83 0x84 0x85 0x86 0x87 0x88 0x89 0x8A 0x8B 0x8C 0x8D 0x8E 0x8F )(list 0x200 0x204 0x208 0x20C 0x210 0x214 0x218 0x21C 0x220 0x224 0x228 0x22C 0x230 0x234 0x238 0x23C ) group.long ($2+0xC00)++0x3 line.long 0x0 "REGG3_DOM_$1,Assign domain for SCR registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x90 0x91 0x92 0x93 0x94 0x95 0x96 0x97 0x98 0x99 0x9A 0x9B 0x9C 0x9D 0x9E 0x9F )(list 0x240 0x244 0x248 0x24C 0x250 0x254 0x258 0x25C 0x260 0x264 0x268 0x26C 0x270 0x274 0x278 0x27C ) group.long ($2+0xC00)++0x3 line.long 0x0 "REGG3_DOM_$1,Assign domain for SCR registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xA0 0xA1 0xA2 0xA3 0xA4 0xA5 0xA6 0xA7 0xA8 0xA9 0xAA 0xAB 0xAC 0xAD 0xAE 0xAF )(list 0x280 0x284 0x288 0x28C 0x290 0x294 0x298 0x29C 0x2A0 0x2A4 0x2A8 0x2AC 0x2B0 0x2B4 0x2B8 0x2BC ) group.long ($2+0xC00)++0x3 line.long 0x0 "REGG3_DOM_$1,Assign domain for SCR registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xB0 0xB1 0xB2 0xB3 0xB4 0xB5 0xB6 0xB7 0xB8 0xB9 0xBA 0xBB 0xBC 0xBD 0xBE 0xBF )(list 0x2C0 0x2C4 0x2C8 0x2CC 0x2D0 0x2D4 0x2D8 0x2DC 0x2E0 0x2E4 0x2E8 0x2EC 0x2F0 0x2F4 0x2F8 0x2FC ) group.long ($2+0xC00)++0x3 line.long 0x0 "REGG3_DOM_$1,Assign domain for SCR registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xC0 0xC1 0xC2 0xC3 0xC4 0xC5 0xC6 0xC7 0xC8 0xC9 0xCA 0xCB 0xCC 0xCD 0xCE 0xCF )(list 0x300 0x304 0x308 0x30C 0x310 0x314 0x318 0x31C 0x320 0x324 0x328 0x32C 0x330 0x334 0x338 0x33C ) group.long ($2+0xC00)++0x3 line.long 0x0 "REGG3_DOM_$1,Assign domain for SCR registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xD0 0xD1 0xD2 0xD3 0xD4 0xD5 0xD6 0xD7 0xD8 0xD9 0xDA 0xDB 0xDC 0xDD 0xDE 0xDF )(list 0x340 0x344 0x348 0x34C 0x350 0x354 0x358 0x35C 0x360 0x364 0x368 0x36C 0x370 0x374 0x378 0x37C ) group.long ($2+0xC00)++0x3 line.long 0x0 "REGG3_DOM_$1,Assign domain for SCR registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xE0 0xE1 0xE2 0xE3 0xE4 0xE5 0xE6 0xE7 0xE8 0xE9 0xEA 0xEB 0xEC 0xED 0xEE 0xEF )(list 0x380 0x384 0x388 0x38C 0x390 0x394 0x398 0x39C 0x3A0 0x3A4 0x3A8 0x3AC 0x3B0 0x3B4 0x3B8 0x3BC ) group.long ($2+0xC00)++0x3 line.long 0x0 "REGG3_DOM_$1,Assign domain for SCR registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xF0 0xF1 0xF2 0xF3 0xF4 0xF5 0xF6 0xF7 0xF8 0xF9 0xFA 0xFB 0xFC 0xFD 0xFE 0xFF )(list 0x3C0 0x3C4 0x3C8 0x3CC 0x3D0 0x3D4 0x3D8 0x3DC 0x3E0 0x3E4 0x3E8 0x3EC 0x3F0 0x3F4 0x3F8 0x3FC ) group.long ($2+0xC00)++0x3 line.long 0x0 "REGG3_DOM_$1,Assign domain for SCR registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x4 0x8 0xC 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C ) group.long ($2+0x1000)++0x3 line.long 0x0 "REGG4_DOM_$1,Assign domain for RSTGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1A 0x1B 0x1C 0x1D 0x1E 0x1F )(list 0x40 0x44 0x48 0x4C 0x50 0x54 0x58 0x5C 0x60 0x64 0x68 0x6C 0x70 0x74 0x78 0x7C ) group.long ($2+0x1000)++0x3 line.long 0x0 "REGG4_DOM_$1,Assign domain for RSTGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x20 0x21 0x22 0x23 0x24 0x25 0x26 0x27 0x28 0x29 0x2A 0x2B 0x2C 0x2D 0x2E 0x2F )(list 0x80 0x84 0x88 0x8C 0x90 0x94 0x98 0x9C 0xA0 0xA4 0xA8 0xAC 0xB0 0xB4 0xB8 0xBC ) group.long ($2+0x1000)++0x3 line.long 0x0 "REGG4_DOM_$1,Assign domain for RSTGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x30 0x31 0x32 0x33 0x34 0x35 0x36 0x37 0x38 0x39 0x3A 0x3B 0x3C 0x3D 0x3E 0x3F )(list 0xC0 0xC4 0xC8 0xCC 0xD0 0xD4 0xD8 0xDC 0xE0 0xE4 0xE8 0xEC 0xF0 0xF4 0xF8 0xFC ) group.long ($2+0x1000)++0x3 line.long 0x0 "REGG4_DOM_$1,Assign domain for RSTGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x40 0x41 0x42 0x43 0x44 0x45 0x46 0x47 0x48 0x49 0x4A 0x4B 0x4C 0x4D 0x4E 0x4F )(list 0x100 0x104 0x108 0x10C 0x110 0x114 0x118 0x11C 0x120 0x124 0x128 0x12C 0x130 0x134 0x138 0x13C ) group.long ($2+0x1000)++0x3 line.long 0x0 "REGG4_DOM_$1,Assign domain for RSTGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x50 0x51 0x52 0x53 0x54 0x55 0x56 0x57 0x58 0x59 0x5A 0x5B 0x5C 0x5D 0x5E 0x5F )(list 0x140 0x144 0x148 0x14C 0x150 0x154 0x158 0x15C 0x160 0x164 0x168 0x16C 0x170 0x174 0x178 0x17C ) group.long ($2+0x1000)++0x3 line.long 0x0 "REGG4_DOM_$1,Assign domain for RSTGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x60 0x61 0x62 0x63 0x64 0x65 0x66 0x67 0x68 0x69 0x6A 0x6B 0x6C 0x6D 0x6E 0x6F )(list 0x180 0x184 0x188 0x18C 0x190 0x194 0x198 0x19C 0x1A0 0x1A4 0x1A8 0x1AC 0x1B0 0x1B4 0x1B8 0x1BC ) group.long ($2+0x1000)++0x3 line.long 0x0 "REGG4_DOM_$1,Assign domain for RSTGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x70 0x71 0x72 0x73 0x74 0x75 0x76 0x77 0x78 0x79 0x7A 0x7B 0x7C 0x7D 0x7E 0x7F )(list 0x1C0 0x1C4 0x1C8 0x1CC 0x1D0 0x1D4 0x1D8 0x1DC 0x1E0 0x1E4 0x1E8 0x1EC 0x1F0 0x1F4 0x1F8 0x1FC ) group.long ($2+0x1000)++0x3 line.long 0x0 "REGG4_DOM_$1,Assign domain for RSTGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x80 0x81 0x82 0x83 0x84 0x85 0x86 0x87 0x88 0x89 0x8A 0x8B 0x8C 0x8D 0x8E 0x8F )(list 0x200 0x204 0x208 0x20C 0x210 0x214 0x218 0x21C 0x220 0x224 0x228 0x22C 0x230 0x234 0x238 0x23C ) group.long ($2+0x1000)++0x3 line.long 0x0 "REGG4_DOM_$1,Assign domain for RSTGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x90 0x91 0x92 0x93 0x94 0x95 0x96 0x97 0x98 0x99 0x9A 0x9B 0x9C 0x9D 0x9E 0x9F )(list 0x240 0x244 0x248 0x24C 0x250 0x254 0x258 0x25C 0x260 0x264 0x268 0x26C 0x270 0x274 0x278 0x27C ) group.long ($2+0x1000)++0x3 line.long 0x0 "REGG4_DOM_$1,Assign domain for RSTGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xA0 0xA1 0xA2 0xA3 0xA4 0xA5 0xA6 0xA7 0xA8 0xA9 0xAA 0xAB 0xAC 0xAD 0xAE 0xAF )(list 0x280 0x284 0x288 0x28C 0x290 0x294 0x298 0x29C 0x2A0 0x2A4 0x2A8 0x2AC 0x2B0 0x2B4 0x2B8 0x2BC ) group.long ($2+0x1000)++0x3 line.long 0x0 "REGG4_DOM_$1,Assign domain for RSTGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xB0 0xB1 0xB2 0xB3 0xB4 0xB5 0xB6 0xB7 0xB8 0xB9 0xBA 0xBB 0xBC 0xBD 0xBE 0xBF )(list 0x2C0 0x2C4 0x2C8 0x2CC 0x2D0 0x2D4 0x2D8 0x2DC 0x2E0 0x2E4 0x2E8 0x2EC 0x2F0 0x2F4 0x2F8 0x2FC ) group.long ($2+0x1000)++0x3 line.long 0x0 "REGG4_DOM_$1,Assign domain for RSTGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xC0 0xC1 0xC2 0xC3 0xC4 0xC5 0xC6 0xC7 0xC8 0xC9 0xCA 0xCB 0xCC 0xCD 0xCE 0xCF )(list 0x300 0x304 0x308 0x30C 0x310 0x314 0x318 0x31C 0x320 0x324 0x328 0x32C 0x330 0x334 0x338 0x33C ) group.long ($2+0x1000)++0x3 line.long 0x0 "REGG4_DOM_$1,Assign domain for RSTGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xD0 0xD1 0xD2 0xD3 0xD4 0xD5 0xD6 0xD7 0xD8 0xD9 0xDA 0xDB 0xDC 0xDD 0xDE 0xDF )(list 0x340 0x344 0x348 0x34C 0x350 0x354 0x358 0x35C 0x360 0x364 0x368 0x36C 0x370 0x374 0x378 0x37C ) group.long ($2+0x1000)++0x3 line.long 0x0 "REGG4_DOM_$1,Assign domain for RSTGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xE0 0xE1 0xE2 0xE3 0xE4 0xE5 0xE6 0xE7 0xE8 0xE9 0xEA 0xEB 0xEC 0xED 0xEE 0xEF )(list 0x380 0x384 0x388 0x38C 0x390 0x394 0x398 0x39C 0x3A0 0x3A4 0x3A8 0x3AC 0x3B0 0x3B4 0x3B8 0x3BC ) group.long ($2+0x1000)++0x3 line.long 0x0 "REGG4_DOM_$1,Assign domain for RSTGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xF0 0xF1 0xF2 0xF3 0xF4 0xF5 0xF6 0xF7 0xF8 0xF9 0xFA 0xFB 0xFC 0xFD 0xFE 0xFF )(list 0x3C0 0x3C4 0x3C8 0x3CC 0x3D0 0x3D4 0x3D8 0x3DC 0x3E0 0x3E4 0x3E8 0x3EC 0x3F0 0x3F4 0x3F8 0x3FC ) group.long ($2+0x1000)++0x3 line.long 0x0 "REGG4_DOM_$1,Assign domain for RSTGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x4 0x8 0xC 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C ) group.long ($2+0x1400)++0x3 line.long 0x0 "REGG5_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1A 0x1B 0x1C 0x1D 0x1E 0x1F )(list 0x40 0x44 0x48 0x4C 0x50 0x54 0x58 0x5C 0x60 0x64 0x68 0x6C 0x70 0x74 0x78 0x7C ) group.long ($2+0x1400)++0x3 line.long 0x0 "REGG5_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x20 0x21 0x22 0x23 0x24 0x25 0x26 0x27 0x28 0x29 0x2A 0x2B 0x2C 0x2D 0x2E 0x2F )(list 0x80 0x84 0x88 0x8C 0x90 0x94 0x98 0x9C 0xA0 0xA4 0xA8 0xAC 0xB0 0xB4 0xB8 0xBC ) group.long ($2+0x1400)++0x3 line.long 0x0 "REGG5_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x30 0x31 0x32 0x33 0x34 0x35 0x36 0x37 0x38 0x39 0x3A 0x3B 0x3C 0x3D 0x3E 0x3F )(list 0xC0 0xC4 0xC8 0xCC 0xD0 0xD4 0xD8 0xDC 0xE0 0xE4 0xE8 0xEC 0xF0 0xF4 0xF8 0xFC ) group.long ($2+0x1400)++0x3 line.long 0x0 "REGG5_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x40 0x41 0x42 0x43 0x44 0x45 0x46 0x47 0x48 0x49 0x4A 0x4B 0x4C 0x4D 0x4E 0x4F )(list 0x100 0x104 0x108 0x10C 0x110 0x114 0x118 0x11C 0x120 0x124 0x128 0x12C 0x130 0x134 0x138 0x13C ) group.long ($2+0x1400)++0x3 line.long 0x0 "REGG5_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x50 0x51 0x52 0x53 0x54 0x55 0x56 0x57 0x58 0x59 0x5A 0x5B 0x5C 0x5D 0x5E 0x5F )(list 0x140 0x144 0x148 0x14C 0x150 0x154 0x158 0x15C 0x160 0x164 0x168 0x16C 0x170 0x174 0x178 0x17C ) group.long ($2+0x1400)++0x3 line.long 0x0 "REGG5_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x60 0x61 0x62 0x63 0x64 0x65 0x66 0x67 0x68 0x69 0x6A 0x6B 0x6C 0x6D 0x6E 0x6F )(list 0x180 0x184 0x188 0x18C 0x190 0x194 0x198 0x19C 0x1A0 0x1A4 0x1A8 0x1AC 0x1B0 0x1B4 0x1B8 0x1BC ) group.long ($2+0x1400)++0x3 line.long 0x0 "REGG5_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x70 0x71 0x72 0x73 0x74 0x75 0x76 0x77 0x78 0x79 0x7A 0x7B 0x7C 0x7D 0x7E 0x7F )(list 0x1C0 0x1C4 0x1C8 0x1CC 0x1D0 0x1D4 0x1D8 0x1DC 0x1E0 0x1E4 0x1E8 0x1EC 0x1F0 0x1F4 0x1F8 0x1FC ) group.long ($2+0x1400)++0x3 line.long 0x0 "REGG5_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x80 0x81 0x82 0x83 0x84 0x85 0x86 0x87 0x88 0x89 0x8A 0x8B 0x8C 0x8D 0x8E 0x8F )(list 0x200 0x204 0x208 0x20C 0x210 0x214 0x218 0x21C 0x220 0x224 0x228 0x22C 0x230 0x234 0x238 0x23C ) group.long ($2+0x1400)++0x3 line.long 0x0 "REGG5_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x90 0x91 0x92 0x93 0x94 0x95 0x96 0x97 0x98 0x99 0x9A 0x9B 0x9C 0x9D 0x9E 0x9F )(list 0x240 0x244 0x248 0x24C 0x250 0x254 0x258 0x25C 0x260 0x264 0x268 0x26C 0x270 0x274 0x278 0x27C ) group.long ($2+0x1400)++0x3 line.long 0x0 "REGG5_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xA0 0xA1 0xA2 0xA3 0xA4 0xA5 0xA6 0xA7 0xA8 0xA9 0xAA 0xAB 0xAC 0xAD 0xAE 0xAF )(list 0x280 0x284 0x288 0x28C 0x290 0x294 0x298 0x29C 0x2A0 0x2A4 0x2A8 0x2AC 0x2B0 0x2B4 0x2B8 0x2BC ) group.long ($2+0x1400)++0x3 line.long 0x0 "REGG5_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xB0 0xB1 0xB2 0xB3 0xB4 0xB5 0xB6 0xB7 0xB8 0xB9 0xBA 0xBB 0xBC 0xBD 0xBE 0xBF )(list 0x2C0 0x2C4 0x2C8 0x2CC 0x2D0 0x2D4 0x2D8 0x2DC 0x2E0 0x2E4 0x2E8 0x2EC 0x2F0 0x2F4 0x2F8 0x2FC ) group.long ($2+0x1400)++0x3 line.long 0x0 "REGG5_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xC0 0xC1 0xC2 0xC3 0xC4 0xC5 0xC6 0xC7 0xC8 0xC9 0xCA 0xCB 0xCC 0xCD 0xCE 0xCF )(list 0x300 0x304 0x308 0x30C 0x310 0x314 0x318 0x31C 0x320 0x324 0x328 0x32C 0x330 0x334 0x338 0x33C ) group.long ($2+0x1400)++0x3 line.long 0x0 "REGG5_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xD0 0xD1 0xD2 0xD3 0xD4 0xD5 0xD6 0xD7 0xD8 0xD9 0xDA 0xDB 0xDC 0xDD 0xDE 0xDF )(list 0x340 0x344 0x348 0x34C 0x350 0x354 0x358 0x35C 0x360 0x364 0x368 0x36C 0x370 0x374 0x378 0x37C ) group.long ($2+0x1400)++0x3 line.long 0x0 "REGG5_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xE0 0xE1 0xE2 0xE3 0xE4 0xE5 0xE6 0xE7 0xE8 0xE9 0xEA 0xEB 0xEC 0xED 0xEE 0xEF )(list 0x380 0x384 0x388 0x38C 0x390 0x394 0x398 0x39C 0x3A0 0x3A4 0x3A8 0x3AC 0x3B0 0x3B4 0x3B8 0x3BC ) group.long ($2+0x1400)++0x3 line.long 0x0 "REGG5_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xF0 0xF1 0xF2 0xF3 0xF4 0xF5 0xF6 0xF7 0xF8 0xF9 0xFA 0xFB 0xFC 0xFD 0xFE 0xFF )(list 0x3C0 0x3C4 0x3C8 0x3CC 0x3D0 0x3D4 0x3D8 0x3DC 0x3E0 0x3E4 0x3E8 0x3EC 0x3F0 0x3F4 0x3F8 0x3FC ) group.long ($2+0x1400)++0x3 line.long 0x0 "REGG5_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x4 0x8 0xC 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C ) group.long ($2+0x1800)++0x3 line.long 0x0 "REGG6_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1A 0x1B 0x1C 0x1D 0x1E 0x1F )(list 0x40 0x44 0x48 0x4C 0x50 0x54 0x58 0x5C 0x60 0x64 0x68 0x6C 0x70 0x74 0x78 0x7C ) group.long ($2+0x1800)++0x3 line.long 0x0 "REGG6_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x20 0x21 0x22 0x23 0x24 0x25 0x26 0x27 0x28 0x29 0x2A 0x2B 0x2C 0x2D 0x2E 0x2F )(list 0x80 0x84 0x88 0x8C 0x90 0x94 0x98 0x9C 0xA0 0xA4 0xA8 0xAC 0xB0 0xB4 0xB8 0xBC ) group.long ($2+0x1800)++0x3 line.long 0x0 "REGG6_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x30 0x31 0x32 0x33 0x34 0x35 0x36 0x37 0x38 0x39 0x3A 0x3B 0x3C 0x3D 0x3E 0x3F )(list 0xC0 0xC4 0xC8 0xCC 0xD0 0xD4 0xD8 0xDC 0xE0 0xE4 0xE8 0xEC 0xF0 0xF4 0xF8 0xFC ) group.long ($2+0x1800)++0x3 line.long 0x0 "REGG6_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x40 0x41 0x42 0x43 0x44 0x45 0x46 0x47 0x48 0x49 0x4A 0x4B 0x4C 0x4D 0x4E 0x4F )(list 0x100 0x104 0x108 0x10C 0x110 0x114 0x118 0x11C 0x120 0x124 0x128 0x12C 0x130 0x134 0x138 0x13C ) group.long ($2+0x1800)++0x3 line.long 0x0 "REGG6_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x50 0x51 0x52 0x53 0x54 0x55 0x56 0x57 0x58 0x59 0x5A 0x5B 0x5C 0x5D 0x5E 0x5F )(list 0x140 0x144 0x148 0x14C 0x150 0x154 0x158 0x15C 0x160 0x164 0x168 0x16C 0x170 0x174 0x178 0x17C ) group.long ($2+0x1800)++0x3 line.long 0x0 "REGG6_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x60 0x61 0x62 0x63 0x64 0x65 0x66 0x67 0x68 0x69 0x6A 0x6B 0x6C 0x6D 0x6E 0x6F )(list 0x180 0x184 0x188 0x18C 0x190 0x194 0x198 0x19C 0x1A0 0x1A4 0x1A8 0x1AC 0x1B0 0x1B4 0x1B8 0x1BC ) group.long ($2+0x1800)++0x3 line.long 0x0 "REGG6_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x70 0x71 0x72 0x73 0x74 0x75 0x76 0x77 0x78 0x79 0x7A 0x7B 0x7C 0x7D 0x7E 0x7F )(list 0x1C0 0x1C4 0x1C8 0x1CC 0x1D0 0x1D4 0x1D8 0x1DC 0x1E0 0x1E4 0x1E8 0x1EC 0x1F0 0x1F4 0x1F8 0x1FC ) group.long ($2+0x1800)++0x3 line.long 0x0 "REGG6_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x80 0x81 0x82 0x83 0x84 0x85 0x86 0x87 0x88 0x89 0x8A 0x8B 0x8C 0x8D 0x8E 0x8F )(list 0x200 0x204 0x208 0x20C 0x210 0x214 0x218 0x21C 0x220 0x224 0x228 0x22C 0x230 0x234 0x238 0x23C ) group.long ($2+0x1800)++0x3 line.long 0x0 "REGG6_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x90 0x91 0x92 0x93 0x94 0x95 0x96 0x97 0x98 0x99 0x9A 0x9B 0x9C 0x9D 0x9E 0x9F )(list 0x240 0x244 0x248 0x24C 0x250 0x254 0x258 0x25C 0x260 0x264 0x268 0x26C 0x270 0x274 0x278 0x27C ) group.long ($2+0x1800)++0x3 line.long 0x0 "REGG6_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xA0 0xA1 0xA2 0xA3 0xA4 0xA5 0xA6 0xA7 0xA8 0xA9 0xAA 0xAB 0xAC 0xAD 0xAE 0xAF )(list 0x280 0x284 0x288 0x28C 0x290 0x294 0x298 0x29C 0x2A0 0x2A4 0x2A8 0x2AC 0x2B0 0x2B4 0x2B8 0x2BC ) group.long ($2+0x1800)++0x3 line.long 0x0 "REGG6_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xB0 0xB1 0xB2 0xB3 0xB4 0xB5 0xB6 0xB7 0xB8 0xB9 0xBA 0xBB 0xBC 0xBD 0xBE 0xBF )(list 0x2C0 0x2C4 0x2C8 0x2CC 0x2D0 0x2D4 0x2D8 0x2DC 0x2E0 0x2E4 0x2E8 0x2EC 0x2F0 0x2F4 0x2F8 0x2FC ) group.long ($2+0x1800)++0x3 line.long 0x0 "REGG6_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xC0 0xC1 0xC2 0xC3 0xC4 0xC5 0xC6 0xC7 0xC8 0xC9 0xCA 0xCB 0xCC 0xCD 0xCE 0xCF )(list 0x300 0x304 0x308 0x30C 0x310 0x314 0x318 0x31C 0x320 0x324 0x328 0x32C 0x330 0x334 0x338 0x33C ) group.long ($2+0x1800)++0x3 line.long 0x0 "REGG6_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xD0 0xD1 0xD2 0xD3 0xD4 0xD5 0xD6 0xD7 0xD8 0xD9 0xDA 0xDB 0xDC 0xDD 0xDE 0xDF )(list 0x340 0x344 0x348 0x34C 0x350 0x354 0x358 0x35C 0x360 0x364 0x368 0x36C 0x370 0x374 0x378 0x37C ) group.long ($2+0x1800)++0x3 line.long 0x0 "REGG6_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xE0 0xE1 0xE2 0xE3 0xE4 0xE5 0xE6 0xE7 0xE8 0xE9 0xEA 0xEB 0xEC 0xED 0xEE 0xEF )(list 0x380 0x384 0x388 0x38C 0x390 0x394 0x398 0x39C 0x3A0 0x3A4 0x3A8 0x3AC 0x3B0 0x3B4 0x3B8 0x3BC ) group.long ($2+0x1800)++0x3 line.long 0x0 "REGG6_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xF0 0xF1 0xF2 0xF3 0xF4 0xF5 0xF6 0xF7 0xF8 0xF9 0xFA 0xFB 0xFC 0xFD 0xFE 0xFF )(list 0x3C0 0x3C4 0x3C8 0x3CC 0x3D0 0x3D4 0x3D8 0x3DC 0x3E0 0x3E4 0x3E8 0x3EC 0x3F0 0x3F4 0x3F8 0x3FC ) group.long ($2+0x1800)++0x3 line.long 0x0 "REGG6_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x4 0x8 0xC 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C ) group.long ($2+0x1C00)++0x3 line.long 0x0 "REGG7_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1A 0x1B 0x1C 0x1D 0x1E 0x1F )(list 0x40 0x44 0x48 0x4C 0x50 0x54 0x58 0x5C 0x60 0x64 0x68 0x6C 0x70 0x74 0x78 0x7C ) group.long ($2+0x1C00)++0x3 line.long 0x0 "REGG7_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x20 0x21 0x22 0x23 0x24 0x25 0x26 0x27 0x28 0x29 0x2A 0x2B 0x2C 0x2D 0x2E 0x2F )(list 0x80 0x84 0x88 0x8C 0x90 0x94 0x98 0x9C 0xA0 0xA4 0xA8 0xAC 0xB0 0xB4 0xB8 0xBC ) group.long ($2+0x1C00)++0x3 line.long 0x0 "REGG7_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x30 0x31 0x32 0x33 0x34 0x35 0x36 0x37 0x38 0x39 0x3A 0x3B 0x3C 0x3D 0x3E 0x3F )(list 0xC0 0xC4 0xC8 0xCC 0xD0 0xD4 0xD8 0xDC 0xE0 0xE4 0xE8 0xEC 0xF0 0xF4 0xF8 0xFC ) group.long ($2+0x1C00)++0x3 line.long 0x0 "REGG7_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x40 0x41 0x42 0x43 0x44 0x45 0x46 0x47 0x48 0x49 0x4A 0x4B 0x4C 0x4D 0x4E 0x4F )(list 0x100 0x104 0x108 0x10C 0x110 0x114 0x118 0x11C 0x120 0x124 0x128 0x12C 0x130 0x134 0x138 0x13C ) group.long ($2+0x1C00)++0x3 line.long 0x0 "REGG7_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x50 0x51 0x52 0x53 0x54 0x55 0x56 0x57 0x58 0x59 0x5A 0x5B 0x5C 0x5D 0x5E 0x5F )(list 0x140 0x144 0x148 0x14C 0x150 0x154 0x158 0x15C 0x160 0x164 0x168 0x16C 0x170 0x174 0x178 0x17C ) group.long ($2+0x1C00)++0x3 line.long 0x0 "REGG7_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x60 0x61 0x62 0x63 0x64 0x65 0x66 0x67 0x68 0x69 0x6A 0x6B 0x6C 0x6D 0x6E 0x6F )(list 0x180 0x184 0x188 0x18C 0x190 0x194 0x198 0x19C 0x1A0 0x1A4 0x1A8 0x1AC 0x1B0 0x1B4 0x1B8 0x1BC ) group.long ($2+0x1C00)++0x3 line.long 0x0 "REGG7_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x70 0x71 0x72 0x73 0x74 0x75 0x76 0x77 0x78 0x79 0x7A 0x7B 0x7C 0x7D 0x7E 0x7F )(list 0x1C0 0x1C4 0x1C8 0x1CC 0x1D0 0x1D4 0x1D8 0x1DC 0x1E0 0x1E4 0x1E8 0x1EC 0x1F0 0x1F4 0x1F8 0x1FC ) group.long ($2+0x1C00)++0x3 line.long 0x0 "REGG7_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x80 0x81 0x82 0x83 0x84 0x85 0x86 0x87 0x88 0x89 0x8A 0x8B 0x8C 0x8D 0x8E 0x8F )(list 0x200 0x204 0x208 0x20C 0x210 0x214 0x218 0x21C 0x220 0x224 0x228 0x22C 0x230 0x234 0x238 0x23C ) group.long ($2+0x1C00)++0x3 line.long 0x0 "REGG7_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x90 0x91 0x92 0x93 0x94 0x95 0x96 0x97 0x98 0x99 0x9A 0x9B 0x9C 0x9D 0x9E 0x9F )(list 0x240 0x244 0x248 0x24C 0x250 0x254 0x258 0x25C 0x260 0x264 0x268 0x26C 0x270 0x274 0x278 0x27C ) group.long ($2+0x1C00)++0x3 line.long 0x0 "REGG7_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xA0 0xA1 0xA2 0xA3 0xA4 0xA5 0xA6 0xA7 0xA8 0xA9 0xAA 0xAB 0xAC 0xAD 0xAE 0xAF )(list 0x280 0x284 0x288 0x28C 0x290 0x294 0x298 0x29C 0x2A0 0x2A4 0x2A8 0x2AC 0x2B0 0x2B4 0x2B8 0x2BC ) group.long ($2+0x1C00)++0x3 line.long 0x0 "REGG7_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xB0 0xB1 0xB2 0xB3 0xB4 0xB5 0xB6 0xB7 0xB8 0xB9 0xBA 0xBB 0xBC 0xBD 0xBE 0xBF )(list 0x2C0 0x2C4 0x2C8 0x2CC 0x2D0 0x2D4 0x2D8 0x2DC 0x2E0 0x2E4 0x2E8 0x2EC 0x2F0 0x2F4 0x2F8 0x2FC ) group.long ($2+0x1C00)++0x3 line.long 0x0 "REGG7_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xC0 0xC1 0xC2 0xC3 0xC4 0xC5 0xC6 0xC7 0xC8 0xC9 0xCA 0xCB 0xCC 0xCD 0xCE 0xCF )(list 0x300 0x304 0x308 0x30C 0x310 0x314 0x318 0x31C 0x320 0x324 0x328 0x32C 0x330 0x334 0x338 0x33C ) group.long ($2+0x1C00)++0x3 line.long 0x0 "REGG7_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xD0 0xD1 0xD2 0xD3 0xD4 0xD5 0xD6 0xD7 0xD8 0xD9 0xDA 0xDB 0xDC 0xDD 0xDE 0xDF )(list 0x340 0x344 0x348 0x34C 0x350 0x354 0x358 0x35C 0x360 0x364 0x368 0x36C 0x370 0x374 0x378 0x37C ) group.long ($2+0x1C00)++0x3 line.long 0x0 "REGG7_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xE0 0xE1 0xE2 0xE3 0xE4 0xE5 0xE6 0xE7 0xE8 0xE9 0xEA 0xEB 0xEC 0xED 0xEE 0xEF )(list 0x380 0x384 0x388 0x38C 0x390 0x394 0x398 0x39C 0x3A0 0x3A4 0x3A8 0x3AC 0x3B0 0x3B4 0x3B8 0x3BC ) group.long ($2+0x1C00)++0x3 line.long 0x0 "REGG7_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xF0 0xF1 0xF2 0xF3 0xF4 0xF5 0xF6 0xF7 0xF8 0xF9 0xFA 0xFB 0xFC 0xFD 0xFE 0xFF )(list 0x3C0 0x3C4 0x3C8 0x3CC 0x3D0 0x3D4 0x3D8 0x3DC 0x3E0 0x3E4 0x3E8 0x3EC 0x3F0 0x3F4 0x3F8 0x3FC ) group.long ($2+0x1C00)++0x3 line.long 0x0 "REGG7_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end group.long 0x2000++0x17 line.long 0x0 "GLB_CTL,This register provides global enable settings for permission control." bitfld.long 0x0 5. "DOM_CFG_LOCK,Lock write for DOM_CFG_MODE bit." "0,1" bitfld.long 0x0 4. "DOM_CFG_MODE,When enabled all the source setting can be configured by master from domain 0 if it is not locked. When disabled only resource manager can configure the permission of the resource." "0,1" bitfld.long 0x0 3. "PERCK_DIS_LOCK,Lock write for PERCK_DIS" "0,1" bitfld.long 0x0 2. "PERCK_DIS,All the permission check disable." "0,1" newline bitfld.long 0x0 1. "DOM_PRO_LOCK,Lock write for DOM_PRO_EN bit." "0,1" bitfld.long 0x0 0. "DOM_PRO_EN,When disabled no domain access permission check" "0,1" line.long 0x4 "RES_MGR,Resource manager register. This regster is used to assign resource manager for global resource access control" bitfld.long 0x4 17. "MID_LOCK,Lock write for MID_EN and MID_LOW and MID_HIG registers." "0,1" bitfld.long 0x4 16. "MID_EN,Master ID check enable" "0,1" bitfld.long 0x4 15. "PRI_PER_LOCK,Lock write for PRI_PER and PRI_PER_EN" "0,1" bitfld.long 0x4 13.--14. "PRI_PER,Resource manager privileged access permission. bit0 for privileged access bit1 for user access" "0,1,2,3" newline bitfld.long 0x4 12. "PRI_PER_EN,Resource manager privileged access permission enable." "0,1" bitfld.long 0x4 11. "SEC_PER_LOCK,Lock for SEC_PER and SEC_PER_LOCK" "0,1" bitfld.long 0x4 9.--10. "SEC_PER,Resource manager secure access permission. bit 0 for secure access bit 1 for non-secure access" "0,1,2,3" bitfld.long 0x4 8. "SEC_PER_EN,Resource manager secure permission enable" "0,1" bitfld.long 0x4 7. "DID_LOCK,Lock write for DID_EN and DID" "0,1" newline hexmask.long.byte 0x4 3.--6. 1. "DID,Resource manager domain ID" bitfld.long 0x4 2. "DID_EN,Resource manager Domain ID enable" "0,1" bitfld.long 0x4 1. "RES_MGR_EN_LOCK,Lock for RES_MGR_EN" "0,1" bitfld.long 0x4 0. "RES_MGR_EN,Resource manager enable. When the bit is disable there is no resource manager." "0,1" line.long 0x8 "RES_MGR_MA0,This register is used to assign master 0~31 as resource manager." hexmask.long 0x8 0.--31. 1. "MID,Assign master 0~31 for resource manager" line.long 0xC "RES_MGR_MA1,This register is used to assign master 32~63 as resource manager." hexmask.long 0xC 0.--31. 1. "MID,Indicate if master 32~63 is resource manager." line.long 0x10 "RES_MGR_MA2,This register is used to assign master 64~95 as resource manager." hexmask.long 0x10 0.--31. 1. "MID,Indicate if master 64~95 is resource manager." line.long 0x14 "RES_MGR_MA3,This register is used to assign master 96~127 as resource manager." hexmask.long 0x14 0.--31. 1. "MID,Indicate if master 96~127 is resource manager." repeat 8. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 )(list 0x0 0x14 0x28 0x3C 0x50 0x64 0x78 0x8C ) group.long ($2+0x2100)++0x3 line.long 0x0 "GRP_MGR_$1,Group Manager Register. This register is used to assign group manager for each domain" bitfld.long 0x0 17. "MID_LOCK,Lock write for MID_EN and MID_LOW and MID_HIG registers." "0,1" bitfld.long 0x0 16. "MID_EN,Master ID check enable" "0,1" bitfld.long 0x0 15. "PRI_PER_LOCK,Lock write for PRI_PER and PRI_PER_EN" "0,1" bitfld.long 0x0 13.--14. "PRI_PER,Group manager privileged access permission. bit0 for privileged access bit1 for user access" "0,1,2,3" newline bitfld.long 0x0 12. "PRI_PER_EN,Group manager privileged access permission enable." "0,1" bitfld.long 0x0 11. "SEC_PER_LOCK,Lock for SEC_PER and SEC_PER_LOCK" "0,1" bitfld.long 0x0 9.--10. "SEC_PER,Group manager secure access permission. bit 0 for secure access bit 1 for non-secure access" "0,1,2,3" bitfld.long 0x0 8. "SEC_PER_EN,Group manager secure permission enable" "0,1" bitfld.long 0x0 7. "DID_LOCK,Lock write for DID_EN and DID" "0,1" newline hexmask.long.byte 0x0 3.--6. 1. "DID,Group manager domain ID" bitfld.long 0x0 2. "DID_EN,Group manager Domain ID enable" "0,1" bitfld.long 0x0 1. "GRP_MGR_EN_LOCK,Lock write for GPR_MGR_EN" "0,1" bitfld.long 0x0 0. "GRP_MGR_EN,Group manager enable. When the bit is disable there is no resource manager." "0,1" repeat.end repeat 8. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 )(list 0x0 0x14 0x28 0x3C 0x50 0x64 0x78 0x8C ) group.long ($2+0x2104)++0x3 line.long 0x0 "GRP_MGR_MA0_$1,Assign master 0~31 for group manager 0" hexmask.long 0x0 0.--31. 1. "MID,Assign master 0~31 for resource manager" repeat.end repeat 8. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 )(list 0x0 0x14 0x28 0x3C 0x50 0x64 0x78 0x8C ) group.long ($2+0x2108)++0x3 line.long 0x0 "GRP_MGR_MA1_$1,Assign master 32~63 for group manager 0" hexmask.long 0x0 0.--31. 1. "MID,Indicate if master 32~63 is resource manager." repeat.end repeat 8. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 )(list 0x0 0x14 0x28 0x3C 0x50 0x64 0x78 0x8C ) group.long ($2+0x210C)++0x3 line.long 0x0 "GRP_MGR_MA2_$1,Assign master 64~95 for group manager 0" hexmask.long 0x0 0.--31. 1. "MID,Indicate if master 64~95 is resource manager." repeat.end repeat 8. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 )(list 0x0 0x14 0x28 0x3C 0x50 0x64 0x78 0x8C ) group.long ($2+0x2110)++0x3 line.long 0x0 "GRP_MGR_MA3_$1,Assign master 96~127 for group manager 0" hexmask.long 0x0 0.--31. 1. "MID,Indicate if master 96~127 is resource manager." repeat.end group.long 0x2200++0x3 line.long 0x0 "DOM_GID_0,Indicate which group domain 0 belong to" bitfld.long 0x0 3. "LOCK,Lock write for GID" "0,1" bitfld.long 0x0 0.--2. "GID,Group ID" "0,1,2,3,4,5,6,7" repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x18 0x30 0x48 0x60 0x78 0x90 0xA8 0xC0 0xD8 0xF0 0x108 0x120 0x138 0x150 0x168 ) group.long ($2+0x2204)++0x3 line.long 0x0 "DOM_OWN_$1,Assign owner for function domain 0." bitfld.long 0x0 17. "MID_LOCK,Lock write for MID_EN and MID_LOW and MID_HIG registers." "0,1" bitfld.long 0x0 16. "MID_EN,Master ID check enable" "0,1" bitfld.long 0x0 15. "PRI_PER_LOCK,Lock write for PRI_PER and PRI_PER_EN" "0,1" bitfld.long 0x0 13.--14. "PRI_PER,Group manager privileged access permission. bit0 for privileged access bit1 for user access" "0,1,2,3" newline bitfld.long 0x0 12. "PRI_PER_EN,Group manager privileged access permission enable." "0,1" bitfld.long 0x0 11. "SEC_PER_LOCK,Lock for SEC_PER and SEC_PER_LOCK" "0,1" bitfld.long 0x0 9.--10. "SEC_PER,Domain owner secure access permission. bit 0 for secure access bit 1 for non-secure access" "0,1,2,3" bitfld.long 0x0 8. "SEC_PER_EN,Domain owner secure permission enable" "0,1" newline bitfld.long 0x0 1. "DOM_OWN_EN_LOCK,Lock for DOM_OWN_EN" "0,1" bitfld.long 0x0 0. "DOM_OWN_EN,Domain owner enable. When the bit is disable there is no domain owner." "0,1" repeat.end repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x18 0x30 0x48 0x60 0x78 0x90 0xA8 0xC0 0xD8 0xF0 0x108 0x120 0x138 0x150 0x168 ) group.long ($2+0x2208)++0x3 line.long 0x0 "DOM_OWN_MA0_$1,Assign master 0~31 for domain owner 0" hexmask.long 0x0 0.--31. 1. "MID,Assign master 0~31 for resource manager" repeat.end repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x18 0x30 0x48 0x60 0x78 0x90 0xA8 0xC0 0xD8 0xF0 0x108 0x120 0x138 0x150 0x168 ) group.long ($2+0x220C)++0x3 line.long 0x0 "DOM_OWN_MA1_$1,Assign master 32~63 for domain owner 0" hexmask.long 0x0 0.--31. 1. "MID,Indicate if master 32~63 is resource manager." repeat.end repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x18 0x30 0x48 0x60 0x78 0x90 0xA8 0xC0 0xD8 0xF0 0x108 0x120 0x138 0x150 0x168 ) group.long ($2+0x2210)++0x3 line.long 0x0 "DOM_OWN_MA2_$1,Assign master 64~95 for domain owner 0" hexmask.long 0x0 0.--31. 1. "MID,Indicate if master 64~95 is resource manager." repeat.end repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x18 0x30 0x48 0x60 0x78 0x90 0xA8 0xC0 0xD8 0xF0 0x108 0x120 0x138 0x150 0x168 ) group.long ($2+0x2214)++0x3 line.long 0x0 "DOM_OWN_MA3_$1,Assign master 96~127 for domain owner 0" hexmask.long 0x0 0.--31. 1. "MID,Indicate if master 96~127 is resource manager." repeat.end group.long 0x2218++0x3 line.long 0x0 "DOM_GID_1,Indicate which group domain 1 belong to" bitfld.long 0x0 3. "LOCK,Lock write for GID" "0,1" bitfld.long 0x0 0.--2. "GID,Group ID" "0,1,2,3,4,5,6,7" group.long 0x2230++0x3 line.long 0x0 "DOM_GID_2,Indicate which group domain 2 belong to" bitfld.long 0x0 3. "LOCK,Lock write for GID" "0,1" bitfld.long 0x0 0.--2. "GID,Group ID" "0,1,2,3,4,5,6,7" group.long 0x2248++0x3 line.long 0x0 "DOM_GID_3,Indicate which group domain 3 belong to" bitfld.long 0x0 3. "LOCK,Lock write for GID" "0,1" bitfld.long 0x0 0.--2. "GID,Group ID" "0,1,2,3,4,5,6,7" group.long 0x2260++0x3 line.long 0x0 "DOM_GID_4,Indicate which group domain 4 belong to" bitfld.long 0x0 3. "LOCK,Lock write for GID" "0,1" bitfld.long 0x0 0.--2. "GID,Group ID" "0,1,2,3,4,5,6,7" group.long 0x2278++0x3 line.long 0x0 "DOM_GID_5,Indicate which group domain 5 belong to" bitfld.long 0x0 3. "LOCK,Lock write for GID" "0,1" bitfld.long 0x0 0.--2. "GID,Group ID" "0,1,2,3,4,5,6,7" group.long 0x2290++0x3 line.long 0x0 "DOM_GID_6,Indicate which group domain 6 belong to" bitfld.long 0x0 3. "LOCK,Lock write for GID" "0,1" bitfld.long 0x0 0.--2. "GID,Group ID" "0,1,2,3,4,5,6,7" group.long 0x22A8++0x3 line.long 0x0 "DOM_GID_7,Indicate which group domain 7 belong to" bitfld.long 0x0 3. "LOCK,Lock write for GID" "0,1" bitfld.long 0x0 0.--2. "GID,Group ID" "0,1,2,3,4,5,6,7" group.long 0x22C0++0x3 line.long 0x0 "DOM_GID_8,Indicate which group domain 8 belong to" bitfld.long 0x0 3. "LOCK,Lock write for GID" "0,1" bitfld.long 0x0 0.--2. "GID,Group ID" "0,1,2,3,4,5,6,7" group.long 0x22D8++0x3 line.long 0x0 "DOM_GID_9,Indicate which group domain 9 belong to" bitfld.long 0x0 3. "LOCK,Lock write for GID" "0,1" bitfld.long 0x0 0.--2. "GID,Group ID" "0,1,2,3,4,5,6,7" group.long 0x22F0++0x3 line.long 0x0 "DOM_GID_10,Indicate which group domain 10 belong to" bitfld.long 0x0 3. "LOCK,Lock write for GID" "0,1" bitfld.long 0x0 0.--2. "GID,Group ID" "0,1,2,3,4,5,6,7" group.long 0x2308++0x3 line.long 0x0 "DOM_GID_11,Indicate which group domain 11 belong to" bitfld.long 0x0 3. "LOCK,Lock write for GID" "0,1" bitfld.long 0x0 0.--2. "GID,Group ID" "0,1,2,3,4,5,6,7" group.long 0x2320++0x3 line.long 0x0 "DOM_GID_12,Indicate which group domain 12 belong to" bitfld.long 0x0 3. "LOCK,Lock write for GID" "0,1" bitfld.long 0x0 0.--2. "GID,Group ID" "0,1,2,3,4,5,6,7" group.long 0x2338++0x3 line.long 0x0 "DOM_GID_13,Indicate which group domain 13 belong to" bitfld.long 0x0 3. "LOCK,Lock write for GID" "0,1" bitfld.long 0x0 0.--2. "GID,Group ID" "0,1,2,3,4,5,6,7" group.long 0x2350++0x3 line.long 0x0 "DOM_GID_14,Indicate which group domain 14 belong to" bitfld.long 0x0 3. "LOCK,Lock write for GID" "0,1" bitfld.long 0x0 0.--2. "GID,Group ID" "0,1,2,3,4,5,6,7" group.long 0x2368++0x3 line.long 0x0 "DOM_GID_15,Indicate which group domain 15 belong to" bitfld.long 0x0 3. "LOCK,Lock write for GID" "0,1" bitfld.long 0x0 0.--2. "GID,Group ID" "0,1,2,3,4,5,6,7" repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x34 0x68 0x9C 0xD0 0x104 0x138 0x16C 0x1A0 0x1D4 0x208 0x23C 0x270 0x2A4 0x2D8 0x30C ) group.long ($2+0x2400)++0x3 line.long 0x0 "DOM_PER0_$1,Domain Permission Control. It can be only configured by resource manager and domain owner." bitfld.long 0x0 31. "DOM7_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 29.--30. "DOM7_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 28. "DOM7_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 27. "DOM6_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 25.--26. "DOM6_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" newline bitfld.long 0x0 24. "DOM6_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 23. "DOM5_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 21.--22. "DOM5_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 20. "DOM5_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 19. "DOM4_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" newline bitfld.long 0x0 17.--18. "DOM4_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM4_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 15. "DOM3_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 13.--14. "DOM3_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 12. "DOM3_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" newline bitfld.long 0x0 11. "DOM2_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 9.--10. "DOM2_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM2_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 7. "DOM1_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 5.--6. "DOM1_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" newline bitfld.long 0x0 4. "DOM1_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 3. "DOM0_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 1.--2. "DOM0_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM0_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" repeat.end repeat 16. (list 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1A 0x1B 0x1C 0x1D 0x1E 0x1F )(list 0x340 0x374 0x3A8 0x3DC 0x410 0x444 0x478 0x4AC 0x4E0 0x514 0x548 0x57C 0x5B0 0x5E4 0x618 0x64C ) group.long ($2+0x2400)++0x3 line.long 0x0 "DOM_PER0_$1,Domain Permission Control. It can be only configured by resource manager and domain owner." bitfld.long 0x0 31. "DOM7_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 29.--30. "DOM7_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 28. "DOM7_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 27. "DOM6_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 25.--26. "DOM6_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" newline bitfld.long 0x0 24. "DOM6_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 23. "DOM5_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 21.--22. "DOM5_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 20. "DOM5_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 19. "DOM4_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" newline bitfld.long 0x0 17.--18. "DOM4_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM4_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 15. "DOM3_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 13.--14. "DOM3_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 12. "DOM3_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" newline bitfld.long 0x0 11. "DOM2_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 9.--10. "DOM2_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM2_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 7. "DOM1_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 5.--6. "DOM1_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" newline bitfld.long 0x0 4. "DOM1_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 3. "DOM0_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 1.--2. "DOM0_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM0_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" repeat.end repeat 16. (list 0x20 0x21 0x22 0x23 0x24 0x25 0x26 0x27 0x28 0x29 0x2A 0x2B 0x2C 0x2D 0x2E 0x2F )(list 0x680 0x6B4 0x6E8 0x71C 0x750 0x784 0x7B8 0x7EC 0x820 0x854 0x888 0x8BC 0x8F0 0x924 0x958 0x98C ) group.long ($2+0x2400)++0x3 line.long 0x0 "DOM_PER0_$1,Domain Permission Control. It can be only configured by resource manager and domain owner." bitfld.long 0x0 31. "DOM7_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 29.--30. "DOM7_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 28. "DOM7_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 27. "DOM6_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 25.--26. "DOM6_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" newline bitfld.long 0x0 24. "DOM6_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 23. "DOM5_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 21.--22. "DOM5_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 20. "DOM5_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 19. "DOM4_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" newline bitfld.long 0x0 17.--18. "DOM4_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM4_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 15. "DOM3_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 13.--14. "DOM3_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 12. "DOM3_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" newline bitfld.long 0x0 11. "DOM2_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 9.--10. "DOM2_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM2_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 7. "DOM1_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 5.--6. "DOM1_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" newline bitfld.long 0x0 4. "DOM1_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 3. "DOM0_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 1.--2. "DOM0_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM0_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" repeat.end repeat 16. (list 0x30 0x31 0x32 0x33 0x34 0x35 0x36 0x37 0x38 0x39 0x3A 0x3B 0x3C 0x3D 0x3E 0x3F )(list 0x9C0 0x9F4 0xA28 0xA5C 0xA90 0xAC4 0xAF8 0xB2C 0xB60 0xB94 0xBC8 0xBFC 0xC30 0xC64 0xC98 0xCCC ) group.long ($2+0x2400)++0x3 line.long 0x0 "DOM_PER0_$1,Domain Permission Control. It can be only configured by resource manager and domain owner." bitfld.long 0x0 31. "DOM7_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 29.--30. "DOM7_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 28. "DOM7_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 27. "DOM6_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 25.--26. "DOM6_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" newline bitfld.long 0x0 24. "DOM6_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 23. "DOM5_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 21.--22. "DOM5_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 20. "DOM5_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 19. "DOM4_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" newline bitfld.long 0x0 17.--18. "DOM4_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM4_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 15. "DOM3_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 13.--14. "DOM3_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 12. "DOM3_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" newline bitfld.long 0x0 11. "DOM2_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 9.--10. "DOM2_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM2_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 7. "DOM1_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 5.--6. "DOM1_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" newline bitfld.long 0x0 4. "DOM1_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 3. "DOM0_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 1.--2. "DOM0_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM0_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" repeat.end repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x34 0x68 0x9C 0xD0 0x104 0x138 0x16C 0x1A0 0x1D4 0x208 0x23C 0x270 0x2A4 0x2D8 0x30C ) group.long ($2+0x2404)++0x3 line.long 0x0 "DOM_PER1_$1,Domain Permission Control. It can be only configured by resource manager and domain owner." bitfld.long 0x0 31. "DOM15_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 29.--30. "DOM15_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 28. "DOM15_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 27. "DOM14_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 25.--26. "DOM14_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" newline bitfld.long 0x0 24. "DOM14_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 23. "DOM13_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 21.--22. "DOM13_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 20. "DOM13_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 19. "DOM12_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" newline bitfld.long 0x0 17.--18. "DOM12_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM12_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 15. "DOM11_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 13.--14. "DOM11_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 12. "DOM11_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" newline bitfld.long 0x0 11. "DOM10_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 9.--10. "DOM10_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM10_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 7. "DOM9_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 5.--6. "DOM9_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" newline bitfld.long 0x0 4. "DOM9_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 3. "DOM8_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 1.--2. "DOM8_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM8_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" repeat.end repeat 16. (list 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1A 0x1B 0x1C 0x1D 0x1E 0x1F )(list 0x340 0x374 0x3A8 0x3DC 0x410 0x444 0x478 0x4AC 0x4E0 0x514 0x548 0x57C 0x5B0 0x5E4 0x618 0x64C ) group.long ($2+0x2404)++0x3 line.long 0x0 "DOM_PER1_$1,Domain Permission Control. It can be only configured by resource manager and domain owner." bitfld.long 0x0 31. "DOM15_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 29.--30. "DOM15_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 28. "DOM15_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 27. "DOM14_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 25.--26. "DOM14_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" newline bitfld.long 0x0 24. "DOM14_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 23. "DOM13_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 21.--22. "DOM13_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 20. "DOM13_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 19. "DOM12_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" newline bitfld.long 0x0 17.--18. "DOM12_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM12_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 15. "DOM11_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 13.--14. "DOM11_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 12. "DOM11_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" newline bitfld.long 0x0 11. "DOM10_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 9.--10. "DOM10_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM10_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 7. "DOM9_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 5.--6. "DOM9_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" newline bitfld.long 0x0 4. "DOM9_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 3. "DOM8_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 1.--2. "DOM8_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM8_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" repeat.end repeat 16. (list 0x20 0x21 0x22 0x23 0x24 0x25 0x26 0x27 0x28 0x29 0x2A 0x2B 0x2C 0x2D 0x2E 0x2F )(list 0x680 0x6B4 0x6E8 0x71C 0x750 0x784 0x7B8 0x7EC 0x820 0x854 0x888 0x8BC 0x8F0 0x924 0x958 0x98C ) group.long ($2+0x2404)++0x3 line.long 0x0 "DOM_PER1_$1,Domain Permission Control. It can be only configured by resource manager and domain owner." bitfld.long 0x0 31. "DOM15_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 29.--30. "DOM15_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 28. "DOM15_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 27. "DOM14_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 25.--26. "DOM14_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" newline bitfld.long 0x0 24. "DOM14_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 23. "DOM13_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 21.--22. "DOM13_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 20. "DOM13_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 19. "DOM12_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" newline bitfld.long 0x0 17.--18. "DOM12_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM12_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 15. "DOM11_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 13.--14. "DOM11_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 12. "DOM11_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" newline bitfld.long 0x0 11. "DOM10_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 9.--10. "DOM10_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM10_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 7. "DOM9_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 5.--6. "DOM9_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" newline bitfld.long 0x0 4. "DOM9_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 3. "DOM8_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 1.--2. "DOM8_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM8_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" repeat.end repeat 16. (list 0x30 0x31 0x32 0x33 0x34 0x35 0x36 0x37 0x38 0x39 0x3A 0x3B 0x3C 0x3D 0x3E 0x3F )(list 0x9C0 0x9F4 0xA28 0xA5C 0xA90 0xAC4 0xAF8 0xB2C 0xB60 0xB94 0xBC8 0xBFC 0xC30 0xC64 0xC98 0xCCC ) group.long ($2+0x2404)++0x3 line.long 0x0 "DOM_PER1_$1,Domain Permission Control. It can be only configured by resource manager and domain owner." bitfld.long 0x0 31. "DOM15_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 29.--30. "DOM15_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 28. "DOM15_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 27. "DOM14_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 25.--26. "DOM14_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" newline bitfld.long 0x0 24. "DOM14_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 23. "DOM13_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 21.--22. "DOM13_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 20. "DOM13_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 19. "DOM12_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" newline bitfld.long 0x0 17.--18. "DOM12_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM12_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 15. "DOM11_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 13.--14. "DOM11_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 12. "DOM11_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" newline bitfld.long 0x0 11. "DOM10_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 9.--10. "DOM10_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM10_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 7. "DOM9_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 5.--6. "DOM9_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" newline bitfld.long 0x0 4. "DOM9_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 3. "DOM8_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 1.--2. "DOM8_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM8_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" repeat.end repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x34 0x68 0x9C 0xD0 0x104 0x138 0x16C 0x1A0 0x1D4 0x208 0x23C 0x270 0x2A4 0x2D8 0x30C ) group.long ($2+0x2408)++0x3 line.long 0x0 "SEC_PER0_$1,This register is only used for resource manager to control secure access permission." bitfld.long 0x0 31. "DOM3_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM3_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM3_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM3_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM2_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM2_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM2_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM2_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM1_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM1_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM1_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM1_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM0_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM0_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM0_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM0_SEC_EN,Domain secure permission control enable" "0,1" repeat.end repeat 16. (list 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1A 0x1B 0x1C 0x1D 0x1E 0x1F )(list 0x340 0x374 0x3A8 0x3DC 0x410 0x444 0x478 0x4AC 0x4E0 0x514 0x548 0x57C 0x5B0 0x5E4 0x618 0x64C ) group.long ($2+0x2408)++0x3 line.long 0x0 "SEC_PER0_$1,This register is only used for resource manager to control secure access permission." bitfld.long 0x0 31. "DOM3_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM3_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM3_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM3_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM2_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM2_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM2_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM2_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM1_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM1_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM1_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM1_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM0_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM0_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM0_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM0_SEC_EN,Domain secure permission control enable" "0,1" repeat.end repeat 16. (list 0x20 0x21 0x22 0x23 0x24 0x25 0x26 0x27 0x28 0x29 0x2A 0x2B 0x2C 0x2D 0x2E 0x2F )(list 0x680 0x6B4 0x6E8 0x71C 0x750 0x784 0x7B8 0x7EC 0x820 0x854 0x888 0x8BC 0x8F0 0x924 0x958 0x98C ) group.long ($2+0x2408)++0x3 line.long 0x0 "SEC_PER0_$1,This register is only used for resource manager to control secure access permission." bitfld.long 0x0 31. "DOM3_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM3_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM3_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM3_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM2_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM2_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM2_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM2_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM1_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM1_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM1_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM1_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM0_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM0_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM0_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM0_SEC_EN,Domain secure permission control enable" "0,1" repeat.end repeat 16. (list 0x30 0x31 0x32 0x33 0x34 0x35 0x36 0x37 0x38 0x39 0x3A 0x3B 0x3C 0x3D 0x3E 0x3F )(list 0x9C0 0x9F4 0xA28 0xA5C 0xA90 0xAC4 0xAF8 0xB2C 0xB60 0xB94 0xBC8 0xBFC 0xC30 0xC64 0xC98 0xCCC ) group.long ($2+0x2408)++0x3 line.long 0x0 "SEC_PER0_$1,This register is only used for resource manager to control secure access permission." bitfld.long 0x0 31. "DOM3_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM3_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM3_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM3_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM2_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM2_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM2_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM2_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM1_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM1_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM1_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM1_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM0_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM0_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM0_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM0_SEC_EN,Domain secure permission control enable" "0,1" repeat.end repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x34 0x68 0x9C 0xD0 0x104 0x138 0x16C 0x1A0 0x1D4 0x208 0x23C 0x270 0x2A4 0x2D8 0x30C ) group.long ($2+0x240C)++0x3 line.long 0x0 "SEC_PER1_$1,This register is only used for resource manager to control secure access permission." bitfld.long 0x0 31. "DOM7_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM7_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM7_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM7_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM6_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM6_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM6_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM6_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM5_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM5_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM5_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM5_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM4_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM4_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM4_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM4_SEC_EN,Domain secure permission control enable" "0,1" repeat.end repeat 16. (list 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1A 0x1B 0x1C 0x1D 0x1E 0x1F )(list 0x340 0x374 0x3A8 0x3DC 0x410 0x444 0x478 0x4AC 0x4E0 0x514 0x548 0x57C 0x5B0 0x5E4 0x618 0x64C ) group.long ($2+0x240C)++0x3 line.long 0x0 "SEC_PER1_$1,This register is only used for resource manager to control secure access permission." bitfld.long 0x0 31. "DOM7_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM7_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM7_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM7_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM6_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM6_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM6_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM6_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM5_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM5_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM5_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM5_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM4_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM4_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM4_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM4_SEC_EN,Domain secure permission control enable" "0,1" repeat.end repeat 16. (list 0x20 0x21 0x22 0x23 0x24 0x25 0x26 0x27 0x28 0x29 0x2A 0x2B 0x2C 0x2D 0x2E 0x2F )(list 0x680 0x6B4 0x6E8 0x71C 0x750 0x784 0x7B8 0x7EC 0x820 0x854 0x888 0x8BC 0x8F0 0x924 0x958 0x98C ) group.long ($2+0x240C)++0x3 line.long 0x0 "SEC_PER1_$1,This register is only used for resource manager to control secure access permission." bitfld.long 0x0 31. "DOM7_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM7_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM7_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM7_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM6_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM6_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM6_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM6_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM5_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM5_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM5_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM5_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM4_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM4_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM4_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM4_SEC_EN,Domain secure permission control enable" "0,1" repeat.end repeat 16. (list 0x30 0x31 0x32 0x33 0x34 0x35 0x36 0x37 0x38 0x39 0x3A 0x3B 0x3C 0x3D 0x3E 0x3F )(list 0x9C0 0x9F4 0xA28 0xA5C 0xA90 0xAC4 0xAF8 0xB2C 0xB60 0xB94 0xBC8 0xBFC 0xC30 0xC64 0xC98 0xCCC ) group.long ($2+0x240C)++0x3 line.long 0x0 "SEC_PER1_$1,This register is only used for resource manager to control secure access permission." bitfld.long 0x0 31. "DOM7_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM7_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM7_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM7_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM6_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM6_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM6_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM6_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM5_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM5_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM5_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM5_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM4_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM4_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM4_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM4_SEC_EN,Domain secure permission control enable" "0,1" repeat.end repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x34 0x68 0x9C 0xD0 0x104 0x138 0x16C 0x1A0 0x1D4 0x208 0x23C 0x270 0x2A4 0x2D8 0x30C ) group.long ($2+0x2410)++0x3 line.long 0x0 "SEC_PER2_$1,This register is only used for resource manager to control secure access permission." bitfld.long 0x0 31. "DOM11_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM11_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM11_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM11_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM10_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM10_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM10_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM10_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM9_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM9_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM9_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM9_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM8_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM8_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM8_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM8_SEC_EN,Domain secure permission control enable" "0,1" repeat.end repeat 16. (list 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1A 0x1B 0x1C 0x1D 0x1E 0x1F )(list 0x340 0x374 0x3A8 0x3DC 0x410 0x444 0x478 0x4AC 0x4E0 0x514 0x548 0x57C 0x5B0 0x5E4 0x618 0x64C ) group.long ($2+0x2410)++0x3 line.long 0x0 "SEC_PER2_$1,This register is only used for resource manager to control secure access permission." bitfld.long 0x0 31. "DOM11_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM11_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM11_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM11_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM10_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM10_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM10_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM10_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM9_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM9_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM9_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM9_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM8_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM8_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM8_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM8_SEC_EN,Domain secure permission control enable" "0,1" repeat.end repeat 16. (list 0x20 0x21 0x22 0x23 0x24 0x25 0x26 0x27 0x28 0x29 0x2A 0x2B 0x2C 0x2D 0x2E 0x2F )(list 0x680 0x6B4 0x6E8 0x71C 0x750 0x784 0x7B8 0x7EC 0x820 0x854 0x888 0x8BC 0x8F0 0x924 0x958 0x98C ) group.long ($2+0x2410)++0x3 line.long 0x0 "SEC_PER2_$1,This register is only used for resource manager to control secure access permission." bitfld.long 0x0 31. "DOM11_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM11_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM11_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM11_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM10_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM10_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM10_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM10_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM9_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM9_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM9_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM9_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM8_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM8_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM8_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM8_SEC_EN,Domain secure permission control enable" "0,1" repeat.end repeat 16. (list 0x30 0x31 0x32 0x33 0x34 0x35 0x36 0x37 0x38 0x39 0x3A 0x3B 0x3C 0x3D 0x3E 0x3F )(list 0x9C0 0x9F4 0xA28 0xA5C 0xA90 0xAC4 0xAF8 0xB2C 0xB60 0xB94 0xBC8 0xBFC 0xC30 0xC64 0xC98 0xCCC ) group.long ($2+0x2410)++0x3 line.long 0x0 "SEC_PER2_$1,This register is only used for resource manager to control secure access permission." bitfld.long 0x0 31. "DOM11_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM11_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM11_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM11_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM10_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM10_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM10_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM10_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM9_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM9_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM9_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM9_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM8_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM8_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM8_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM8_SEC_EN,Domain secure permission control enable" "0,1" repeat.end repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x34 0x68 0x9C 0xD0 0x104 0x138 0x16C 0x1A0 0x1D4 0x208 0x23C 0x270 0x2A4 0x2D8 0x30C ) group.long ($2+0x2414)++0x3 line.long 0x0 "SEC_PER3_$1,This register is only used for resource manager to control secure access permission." bitfld.long 0x0 31. "DOM15_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM15_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM15_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM15_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM14_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM14_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM14_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM14_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM13_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM13_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM13_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM13_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM12_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM12_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM12_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM12_SEC_EN,Domain secure permission control enable" "0,1" repeat.end repeat 16. (list 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1A 0x1B 0x1C 0x1D 0x1E 0x1F )(list 0x340 0x374 0x3A8 0x3DC 0x410 0x444 0x478 0x4AC 0x4E0 0x514 0x548 0x57C 0x5B0 0x5E4 0x618 0x64C ) group.long ($2+0x2414)++0x3 line.long 0x0 "SEC_PER3_$1,This register is only used for resource manager to control secure access permission." bitfld.long 0x0 31. "DOM15_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM15_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM15_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM15_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM14_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM14_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM14_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM14_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM13_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM13_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM13_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM13_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM12_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM12_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM12_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM12_SEC_EN,Domain secure permission control enable" "0,1" repeat.end repeat 16. (list 0x20 0x21 0x22 0x23 0x24 0x25 0x26 0x27 0x28 0x29 0x2A 0x2B 0x2C 0x2D 0x2E 0x2F )(list 0x680 0x6B4 0x6E8 0x71C 0x750 0x784 0x7B8 0x7EC 0x820 0x854 0x888 0x8BC 0x8F0 0x924 0x958 0x98C ) group.long ($2+0x2414)++0x3 line.long 0x0 "SEC_PER3_$1,This register is only used for resource manager to control secure access permission." bitfld.long 0x0 31. "DOM15_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM15_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM15_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM15_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM14_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM14_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM14_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM14_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM13_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM13_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM13_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM13_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM12_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM12_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM12_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM12_SEC_EN,Domain secure permission control enable" "0,1" repeat.end repeat 16. (list 0x30 0x31 0x32 0x33 0x34 0x35 0x36 0x37 0x38 0x39 0x3A 0x3B 0x3C 0x3D 0x3E 0x3F )(list 0x9C0 0x9F4 0xA28 0xA5C 0xA90 0xAC4 0xAF8 0xB2C 0xB60 0xB94 0xBC8 0xBFC 0xC30 0xC64 0xC98 0xCCC ) group.long ($2+0x2414)++0x3 line.long 0x0 "SEC_PER3_$1,This register is only used for resource manager to control secure access permission." bitfld.long 0x0 31. "DOM15_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM15_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM15_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM15_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM14_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM14_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM14_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM14_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM13_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM13_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM13_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM13_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM12_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM12_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM12_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM12_SEC_EN,Domain secure permission control enable" "0,1" repeat.end repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x34 0x68 0x9C 0xD0 0x104 0x138 0x16C 0x1A0 0x1D4 0x208 0x23C 0x270 0x2A4 0x2D8 0x30C ) group.long ($2+0x2418)++0x3 line.long 0x0 "PRI_PER0_$1,This register is only used for resource manager to control privileged access permission." bitfld.long 0x0 31. "DOM3_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM3_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM3_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM3_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM2_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM2_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM2_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM2_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM1_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM1_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM1_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM1_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM0_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM0_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM0_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM0_PRI_EN,Domain privileged permission control enable" "0,1" repeat.end repeat 16. (list 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1A 0x1B 0x1C 0x1D 0x1E 0x1F )(list 0x340 0x374 0x3A8 0x3DC 0x410 0x444 0x478 0x4AC 0x4E0 0x514 0x548 0x57C 0x5B0 0x5E4 0x618 0x64C ) group.long ($2+0x2418)++0x3 line.long 0x0 "PRI_PER0_$1,This register is only used for resource manager to control privileged access permission." bitfld.long 0x0 31. "DOM3_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM3_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM3_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM3_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM2_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM2_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM2_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM2_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM1_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM1_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM1_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM1_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM0_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM0_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM0_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM0_PRI_EN,Domain privileged permission control enable" "0,1" repeat.end repeat 16. (list 0x20 0x21 0x22 0x23 0x24 0x25 0x26 0x27 0x28 0x29 0x2A 0x2B 0x2C 0x2D 0x2E 0x2F )(list 0x680 0x6B4 0x6E8 0x71C 0x750 0x784 0x7B8 0x7EC 0x820 0x854 0x888 0x8BC 0x8F0 0x924 0x958 0x98C ) group.long ($2+0x2418)++0x3 line.long 0x0 "PRI_PER0_$1,This register is only used for resource manager to control privileged access permission." bitfld.long 0x0 31. "DOM3_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM3_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM3_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM3_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM2_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM2_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM2_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM2_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM1_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM1_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM1_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM1_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM0_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM0_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM0_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM0_PRI_EN,Domain privileged permission control enable" "0,1" repeat.end repeat 16. (list 0x30 0x31 0x32 0x33 0x34 0x35 0x36 0x37 0x38 0x39 0x3A 0x3B 0x3C 0x3D 0x3E 0x3F )(list 0x9C0 0x9F4 0xA28 0xA5C 0xA90 0xAC4 0xAF8 0xB2C 0xB60 0xB94 0xBC8 0xBFC 0xC30 0xC64 0xC98 0xCCC ) group.long ($2+0x2418)++0x3 line.long 0x0 "PRI_PER0_$1,This register is only used for resource manager to control privileged access permission." bitfld.long 0x0 31. "DOM3_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM3_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM3_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM3_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM2_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM2_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM2_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM2_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM1_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM1_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM1_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM1_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM0_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM0_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM0_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM0_PRI_EN,Domain privileged permission control enable" "0,1" repeat.end repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x34 0x68 0x9C 0xD0 0x104 0x138 0x16C 0x1A0 0x1D4 0x208 0x23C 0x270 0x2A4 0x2D8 0x30C ) group.long ($2+0x241C)++0x3 line.long 0x0 "PRI_PER1_$1,This register is only used for resource manager to control privileged access permission." bitfld.long 0x0 31. "DOM7_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM7_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM7_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM7_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM6_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM6_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM6_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM6_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM5_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM5_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM5_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM5_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM4_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM4_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM4_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM4_PRI_EN,Domain privileged permission control enable" "0,1" repeat.end repeat 16. (list 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1A 0x1B 0x1C 0x1D 0x1E 0x1F )(list 0x340 0x374 0x3A8 0x3DC 0x410 0x444 0x478 0x4AC 0x4E0 0x514 0x548 0x57C 0x5B0 0x5E4 0x618 0x64C ) group.long ($2+0x241C)++0x3 line.long 0x0 "PRI_PER1_$1,This register is only used for resource manager to control privileged access permission." bitfld.long 0x0 31. "DOM7_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM7_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM7_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM7_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM6_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM6_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM6_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM6_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM5_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM5_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM5_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM5_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM4_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM4_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM4_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM4_PRI_EN,Domain privileged permission control enable" "0,1" repeat.end repeat 16. (list 0x20 0x21 0x22 0x23 0x24 0x25 0x26 0x27 0x28 0x29 0x2A 0x2B 0x2C 0x2D 0x2E 0x2F )(list 0x680 0x6B4 0x6E8 0x71C 0x750 0x784 0x7B8 0x7EC 0x820 0x854 0x888 0x8BC 0x8F0 0x924 0x958 0x98C ) group.long ($2+0x241C)++0x3 line.long 0x0 "PRI_PER1_$1,This register is only used for resource manager to control privileged access permission." bitfld.long 0x0 31. "DOM7_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM7_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM7_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM7_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM6_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM6_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM6_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM6_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM5_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM5_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM5_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM5_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM4_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM4_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM4_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM4_PRI_EN,Domain privileged permission control enable" "0,1" repeat.end repeat 16. (list 0x30 0x31 0x32 0x33 0x34 0x35 0x36 0x37 0x38 0x39 0x3A 0x3B 0x3C 0x3D 0x3E 0x3F )(list 0x9C0 0x9F4 0xA28 0xA5C 0xA90 0xAC4 0xAF8 0xB2C 0xB60 0xB94 0xBC8 0xBFC 0xC30 0xC64 0xC98 0xCCC ) group.long ($2+0x241C)++0x3 line.long 0x0 "PRI_PER1_$1,This register is only used for resource manager to control privileged access permission." bitfld.long 0x0 31. "DOM7_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM7_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM7_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM7_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM6_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM6_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM6_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM6_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM5_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM5_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM5_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM5_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM4_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM4_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM4_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM4_PRI_EN,Domain privileged permission control enable" "0,1" repeat.end repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x34 0x68 0x9C 0xD0 0x104 0x138 0x16C 0x1A0 0x1D4 0x208 0x23C 0x270 0x2A4 0x2D8 0x30C ) group.long ($2+0x2420)++0x3 line.long 0x0 "PRI_PER2_$1,This register is only used for resource manager to control privileged access permission." bitfld.long 0x0 31. "DOM11_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM11_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM11_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM11_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM10_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM10_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM10_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM10_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM9_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM9_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM9_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM9_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM8_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM8_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM8_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM8_PRI_EN,Domain privileged permission control enable" "0,1" repeat.end repeat 16. (list 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1A 0x1B 0x1C 0x1D 0x1E 0x1F )(list 0x340 0x374 0x3A8 0x3DC 0x410 0x444 0x478 0x4AC 0x4E0 0x514 0x548 0x57C 0x5B0 0x5E4 0x618 0x64C ) group.long ($2+0x2420)++0x3 line.long 0x0 "PRI_PER2_$1,This register is only used for resource manager to control privileged access permission." bitfld.long 0x0 31. "DOM11_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM11_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM11_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM11_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM10_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM10_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM10_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM10_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM9_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM9_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM9_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM9_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM8_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM8_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM8_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM8_PRI_EN,Domain privileged permission control enable" "0,1" repeat.end repeat 16. (list 0x20 0x21 0x22 0x23 0x24 0x25 0x26 0x27 0x28 0x29 0x2A 0x2B 0x2C 0x2D 0x2E 0x2F )(list 0x680 0x6B4 0x6E8 0x71C 0x750 0x784 0x7B8 0x7EC 0x820 0x854 0x888 0x8BC 0x8F0 0x924 0x958 0x98C ) group.long ($2+0x2420)++0x3 line.long 0x0 "PRI_PER2_$1,This register is only used for resource manager to control privileged access permission." bitfld.long 0x0 31. "DOM11_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM11_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM11_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM11_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM10_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM10_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM10_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM10_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM9_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM9_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM9_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM9_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM8_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM8_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM8_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM8_PRI_EN,Domain privileged permission control enable" "0,1" repeat.end repeat 16. (list 0x30 0x31 0x32 0x33 0x34 0x35 0x36 0x37 0x38 0x39 0x3A 0x3B 0x3C 0x3D 0x3E 0x3F )(list 0x9C0 0x9F4 0xA28 0xA5C 0xA90 0xAC4 0xAF8 0xB2C 0xB60 0xB94 0xBC8 0xBFC 0xC30 0xC64 0xC98 0xCCC ) group.long ($2+0x2420)++0x3 line.long 0x0 "PRI_PER2_$1,This register is only used for resource manager to control privileged access permission." bitfld.long 0x0 31. "DOM11_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM11_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM11_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM11_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM10_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM10_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM10_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM10_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM9_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM9_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM9_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM9_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM8_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM8_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM8_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM8_PRI_EN,Domain privileged permission control enable" "0,1" repeat.end repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x34 0x68 0x9C 0xD0 0x104 0x138 0x16C 0x1A0 0x1D4 0x208 0x23C 0x270 0x2A4 0x2D8 0x30C ) group.long ($2+0x2424)++0x3 line.long 0x0 "PRI_PER3_$1,This register is only used for resource manager to control privileged access permission." bitfld.long 0x0 31. "DOM15_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM15_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM15_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM15_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM14_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM14_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM14_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM14_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM13_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM13_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM13_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM13_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM12_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM12_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM12_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM12_PRI_EN,Domain privileged permission control enable" "0,1" repeat.end repeat 16. (list 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1A 0x1B 0x1C 0x1D 0x1E 0x1F )(list 0x340 0x374 0x3A8 0x3DC 0x410 0x444 0x478 0x4AC 0x4E0 0x514 0x548 0x57C 0x5B0 0x5E4 0x618 0x64C ) group.long ($2+0x2424)++0x3 line.long 0x0 "PRI_PER3_$1,This register is only used for resource manager to control privileged access permission." bitfld.long 0x0 31. "DOM15_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM15_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM15_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM15_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM14_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM14_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM14_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM14_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM13_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM13_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM13_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM13_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM12_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM12_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM12_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM12_PRI_EN,Domain privileged permission control enable" "0,1" repeat.end repeat 16. (list 0x20 0x21 0x22 0x23 0x24 0x25 0x26 0x27 0x28 0x29 0x2A 0x2B 0x2C 0x2D 0x2E 0x2F )(list 0x680 0x6B4 0x6E8 0x71C 0x750 0x784 0x7B8 0x7EC 0x820 0x854 0x888 0x8BC 0x8F0 0x924 0x958 0x98C ) group.long ($2+0x2424)++0x3 line.long 0x0 "PRI_PER3_$1,This register is only used for resource manager to control privileged access permission." bitfld.long 0x0 31. "DOM15_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM15_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM15_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM15_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM14_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM14_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM14_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM14_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM13_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM13_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM13_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM13_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM12_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM12_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM12_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM12_PRI_EN,Domain privileged permission control enable" "0,1" repeat.end repeat 16. (list 0x30 0x31 0x32 0x33 0x34 0x35 0x36 0x37 0x38 0x39 0x3A 0x3B 0x3C 0x3D 0x3E 0x3F )(list 0x9C0 0x9F4 0xA28 0xA5C 0xA90 0xAC4 0xAF8 0xB2C 0xB60 0xB94 0xBC8 0xBFC 0xC30 0xC64 0xC98 0xCCC ) group.long ($2+0x2424)++0x3 line.long 0x0 "PRI_PER3_$1,This register is only used for resource manager to control privileged access permission." bitfld.long 0x0 31. "DOM15_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM15_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM15_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM15_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM14_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM14_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM14_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM14_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM13_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM13_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM13_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM13_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM12_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM12_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM12_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM12_PRI_EN,Domain privileged permission control enable" "0,1" repeat.end repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x34 0x68 0x9C 0xD0 0x104 0x138 0x16C 0x1A0 0x1D4 0x208 0x23C 0x270 0x2A4 0x2D8 0x30C ) group.long ($2+0x2428)++0x3 line.long 0x0 "DOM_SEC_PER_$1,This register is only used for domain master to control secure access permission. When the domain master write this register. it only changes the secure permission for itself. When the domain master read this register. it gets permission.." bitfld.long 0x0 7. "DOM_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" newline bitfld.long 0x0 0. "DOM_SEC_EN,Domain secure permission control enable" "0,1" repeat.end repeat 16. (list 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1A 0x1B 0x1C 0x1D 0x1E 0x1F )(list 0x340 0x374 0x3A8 0x3DC 0x410 0x444 0x478 0x4AC 0x4E0 0x514 0x548 0x57C 0x5B0 0x5E4 0x618 0x64C ) group.long ($2+0x2428)++0x3 line.long 0x0 "DOM_SEC_PER_$1,This register is only used for domain master to control secure access permission. When the domain master write this register. it only changes the secure permission for itself. When the domain master read this register. it gets permission.." bitfld.long 0x0 7. "DOM_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" newline bitfld.long 0x0 0. "DOM_SEC_EN,Domain secure permission control enable" "0,1" repeat.end repeat 16. (list 0x20 0x21 0x22 0x23 0x24 0x25 0x26 0x27 0x28 0x29 0x2A 0x2B 0x2C 0x2D 0x2E 0x2F )(list 0x680 0x6B4 0x6E8 0x71C 0x750 0x784 0x7B8 0x7EC 0x820 0x854 0x888 0x8BC 0x8F0 0x924 0x958 0x98C ) group.long ($2+0x2428)++0x3 line.long 0x0 "DOM_SEC_PER_$1,This register is only used for domain master to control secure access permission. When the domain master write this register. it only changes the secure permission for itself. When the domain master read this register. it gets permission.." bitfld.long 0x0 7. "DOM_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" newline bitfld.long 0x0 0. "DOM_SEC_EN,Domain secure permission control enable" "0,1" repeat.end repeat 16. (list 0x30 0x31 0x32 0x33 0x34 0x35 0x36 0x37 0x38 0x39 0x3A 0x3B 0x3C 0x3D 0x3E 0x3F )(list 0x9C0 0x9F4 0xA28 0xA5C 0xA90 0xAC4 0xAF8 0xB2C 0xB60 0xB94 0xBC8 0xBFC 0xC30 0xC64 0xC98 0xCCC ) group.long ($2+0x2428)++0x3 line.long 0x0 "DOM_SEC_PER_$1,This register is only used for domain master to control secure access permission. When the domain master write this register. it only changes the secure permission for itself. When the domain master read this register. it gets permission.." bitfld.long 0x0 7. "DOM_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" newline bitfld.long 0x0 0. "DOM_SEC_EN,Domain secure permission control enable" "0,1" repeat.end repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x34 0x68 0x9C 0xD0 0x104 0x138 0x16C 0x1A0 0x1D4 0x208 0x23C 0x270 0x2A4 0x2D8 0x30C ) group.long ($2+0x242C)++0x3 line.long 0x0 "DOM_PRI_PER_$1,This register is only used for domain master to control secure access permission. When the domain master write this register. it only changes the secure permission for itself. When the domain master read this register. it gets permission.." bitfld.long 0x0 7. "DOM_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" newline bitfld.long 0x0 0. "DOM_PRI_EN,Domain privileged permission control enable" "0,1" repeat.end repeat 16. (list 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1A 0x1B 0x1C 0x1D 0x1E 0x1F )(list 0x340 0x374 0x3A8 0x3DC 0x410 0x444 0x478 0x4AC 0x4E0 0x514 0x548 0x57C 0x5B0 0x5E4 0x618 0x64C ) group.long ($2+0x242C)++0x3 line.long 0x0 "DOM_PRI_PER_$1,This register is only used for domain master to control secure access permission. When the domain master write this register. it only changes the secure permission for itself. When the domain master read this register. it gets permission.." bitfld.long 0x0 7. "DOM_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" newline bitfld.long 0x0 0. "DOM_PRI_EN,Domain privileged permission control enable" "0,1" repeat.end repeat 16. (list 0x20 0x21 0x22 0x23 0x24 0x25 0x26 0x27 0x28 0x29 0x2A 0x2B 0x2C 0x2D 0x2E 0x2F )(list 0x680 0x6B4 0x6E8 0x71C 0x750 0x784 0x7B8 0x7EC 0x820 0x854 0x888 0x8BC 0x8F0 0x924 0x958 0x98C ) group.long ($2+0x242C)++0x3 line.long 0x0 "DOM_PRI_PER_$1,This register is only used for domain master to control secure access permission. When the domain master write this register. it only changes the secure permission for itself. When the domain master read this register. it gets permission.." bitfld.long 0x0 7. "DOM_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" newline bitfld.long 0x0 0. "DOM_PRI_EN,Domain privileged permission control enable" "0,1" repeat.end repeat 16. (list 0x30 0x31 0x32 0x33 0x34 0x35 0x36 0x37 0x38 0x39 0x3A 0x3B 0x3C 0x3D 0x3E 0x3F )(list 0x9C0 0x9F4 0xA28 0xA5C 0xA90 0xAC4 0xAF8 0xB2C 0xB60 0xB94 0xBC8 0xBFC 0xC30 0xC64 0xC98 0xCCC ) group.long ($2+0x242C)++0x3 line.long 0x0 "DOM_PRI_PER_$1,This register is only used for domain master to control secure access permission. When the domain master write this register. it only changes the secure permission for itself. When the domain master read this register. it gets permission.." bitfld.long 0x0 7. "DOM_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" newline bitfld.long 0x0 0. "DOM_PRI_EN,Domain privileged permission control enable" "0,1" repeat.end repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x34 0x68 0x9C 0xD0 0x104 0x138 0x16C 0x1A0 0x1D4 0x208 0x23C 0x270 0x2A4 0x2D8 0x30C ) group.long ($2+0x2430)++0x3 line.long 0x0 "DOM_ASSIGN_$1,Use to assign domain for accessing DOM_SEC_PER and DOM_PRI_PER register. Only resource manager. group manager and domain owner can access this register. For write. group manager must write its owen domain ID. otherwise write accessing will.." hexmask.long.byte 0x0 0.--3. 1. "DID,accessing DOM_SEC_PER and DOM_PRI_PER register" repeat.end repeat 16. (list 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1A 0x1B 0x1C 0x1D 0x1E 0x1F )(list 0x340 0x374 0x3A8 0x3DC 0x410 0x444 0x478 0x4AC 0x4E0 0x514 0x548 0x57C 0x5B0 0x5E4 0x618 0x64C ) group.long ($2+0x2430)++0x3 line.long 0x0 "DOM_ASSIGN_$1,Use to assign domain for accessing DOM_SEC_PER and DOM_PRI_PER register. Only resource manager. group manager and domain owner can access this register. For write. group manager must write its owen domain ID. otherwise write accessing will.." hexmask.long.byte 0x0 0.--3. 1. "DID,accessing DOM_SEC_PER and DOM_PRI_PER register" repeat.end repeat 16. (list 0x20 0x21 0x22 0x23 0x24 0x25 0x26 0x27 0x28 0x29 0x2A 0x2B 0x2C 0x2D 0x2E 0x2F )(list 0x680 0x6B4 0x6E8 0x71C 0x750 0x784 0x7B8 0x7EC 0x820 0x854 0x888 0x8BC 0x8F0 0x924 0x958 0x98C ) group.long ($2+0x2430)++0x3 line.long 0x0 "DOM_ASSIGN_$1,Use to assign domain for accessing DOM_SEC_PER and DOM_PRI_PER register. Only resource manager. group manager and domain owner can access this register. For write. group manager must write its owen domain ID. otherwise write accessing will.." hexmask.long.byte 0x0 0.--3. 1. "DID,accessing DOM_SEC_PER and DOM_PRI_PER register" repeat.end repeat 16. (list 0x30 0x31 0x32 0x33 0x34 0x35 0x36 0x37 0x38 0x39 0x3A 0x3B 0x3C 0x3D 0x3E 0x3F )(list 0x9C0 0x9F4 0xA28 0xA5C 0xA90 0xAC4 0xAF8 0xB2C 0xB60 0xB94 0xBC8 0xBFC 0xC30 0xC64 0xC98 0xCCC ) group.long ($2+0x2430)++0x3 line.long 0x0 "DOM_ASSIGN_$1,Use to assign domain for accessing DOM_SEC_PER and DOM_PRI_PER register. Only resource manager. group manager and domain owner can access this register. For write. group manager must write its owen domain ID. otherwise write accessing will.." hexmask.long.byte 0x0 0.--3. 1. "DID,accessing DOM_SEC_PER and DOM_PRI_PER register" repeat.end repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x38 0x70 0xA8 0xE0 0x118 0x150 0x188 0x1C0 0x1F8 0x230 0x268 0x2A0 0x2D8 0x310 0x348 ) group.long ($2+0x3100)++0x3 line.long 0x0 "RGN_DOM_$1,Assign domain for peripheral. It can be only configured by resource and group manager" bitfld.long 0x0 31. "LOCK,When this bit is set lock write for all the bits in the register." "0,1" bitfld.long 0x0 4. "SET,Set together with DID would change permission of this resource to following setting: 1) Domain access control enabled. 2) Read/Write allowed for the domain owner. 3) Read/Write not allowed for all the other domains. If this bit is not set only DID.." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Assign domain for peripheral" repeat.end repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x38 0x70 0xA8 0xE0 0x118 0x150 0x188 0x1C0 0x1F8 0x230 0x268 0x2A0 0x2D8 0x310 0x348 ) group.long ($2+0x3104)++0x3 line.long 0x0 "RGN_DOM_PER0_$1,Domain Permission Control. It can be only configured by resource manager and domain owner." bitfld.long 0x0 31. "DOM7_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 29.--30. "DOM7_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 28. "DOM7_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 27. "DOM6_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 25.--26. "DOM6_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" newline bitfld.long 0x0 24. "DOM6_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 23. "DOM5_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 21.--22. "DOM5_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 20. "DOM5_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 19. "DOM4_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" newline bitfld.long 0x0 17.--18. "DOM4_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM4_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 15. "DOM3_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 13.--14. "DOM3_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 12. "DOM3_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" newline bitfld.long 0x0 11. "DOM2_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 9.--10. "DOM2_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM2_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 7. "DOM1_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 5.--6. "DOM1_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" newline bitfld.long 0x0 4. "DOM1_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 3. "DOM0_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 1.--2. "DOM0_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM0_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" repeat.end repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x38 0x70 0xA8 0xE0 0x118 0x150 0x188 0x1C0 0x1F8 0x230 0x268 0x2A0 0x2D8 0x310 0x348 ) group.long ($2+0x3108)++0x3 line.long 0x0 "RGN_DOM_PER1_$1,Domain Permission Control. It can be only configured by resource manager and domain owner." bitfld.long 0x0 31. "DOM15_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 29.--30. "DOM15_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 28. "DOM15_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 27. "DOM14_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 25.--26. "DOM14_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" newline bitfld.long 0x0 24. "DOM14_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 23. "DOM13_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 21.--22. "DOM13_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 20. "DOM13_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 19. "DOM12_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" newline bitfld.long 0x0 17.--18. "DOM12_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM12_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 15. "DOM11_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 13.--14. "DOM11_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 12. "DOM11_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" newline bitfld.long 0x0 11. "DOM10_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 9.--10. "DOM10_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM10_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 7. "DOM9_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 5.--6. "DOM9_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" newline bitfld.long 0x0 4. "DOM9_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 3. "DOM8_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 1.--2. "DOM8_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM8_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" repeat.end repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x38 0x70 0xA8 0xE0 0x118 0x150 0x188 0x1C0 0x1F8 0x230 0x268 0x2A0 0x2D8 0x310 0x348 ) group.long ($2+0x310C)++0x3 line.long 0x0 "RGN_SEC_PER0_$1,This register is only used for resource manager to control secure access permission." bitfld.long 0x0 31. "DOM3_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM3_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM3_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM3_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM2_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM2_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM2_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM2_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM1_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM1_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM1_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM1_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM0_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM0_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM0_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM0_SEC_EN,Domain secure permission control enable" "0,1" repeat.end repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x38 0x70 0xA8 0xE0 0x118 0x150 0x188 0x1C0 0x1F8 0x230 0x268 0x2A0 0x2D8 0x310 0x348 ) group.long ($2+0x3110)++0x3 line.long 0x0 "RGN_SEC_PER1_$1,This register is only used for resource manager to control secure access permission." bitfld.long 0x0 31. "DOM7_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM7_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM7_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM7_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM6_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM6_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM6_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM6_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM5_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM5_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM5_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM5_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM4_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM4_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM4_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM4_SEC_EN,Domain secure permission control enable" "0,1" repeat.end repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x38 0x70 0xA8 0xE0 0x118 0x150 0x188 0x1C0 0x1F8 0x230 0x268 0x2A0 0x2D8 0x310 0x348 ) group.long ($2+0x3114)++0x3 line.long 0x0 "RGN_SEC_PER2_$1,This register is only used for resource manager to control secure access permission." bitfld.long 0x0 31. "DOM11_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM11_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM11_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM11_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM10_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM10_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM10_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM10_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM9_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM9_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM9_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM9_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM8_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM8_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM8_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM8_SEC_EN,Domain secure permission control enable" "0,1" repeat.end repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x38 0x70 0xA8 0xE0 0x118 0x150 0x188 0x1C0 0x1F8 0x230 0x268 0x2A0 0x2D8 0x310 0x348 ) group.long ($2+0x3118)++0x3 line.long 0x0 "RGN_SEC_PER3_$1,This register is only used for resource manager to control secure access permission." bitfld.long 0x0 31. "DOM15_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM15_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM15_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM15_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM14_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM14_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM14_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM14_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM13_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM13_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM13_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM13_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM12_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM12_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM12_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM12_SEC_EN,Domain secure permission control enable" "0,1" repeat.end repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x38 0x70 0xA8 0xE0 0x118 0x150 0x188 0x1C0 0x1F8 0x230 0x268 0x2A0 0x2D8 0x310 0x348 ) group.long ($2+0x311C)++0x3 line.long 0x0 "RGN_PRI_PER0_$1,This register is only used for resource manager to control privileged access permission." bitfld.long 0x0 31. "DOM3_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM3_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM3_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM3_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM2_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM2_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM2_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM2_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM1_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM1_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM1_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM1_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM0_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM0_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM0_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM0_PRI_EN,Domain privileged permission control enable" "0,1" repeat.end repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x38 0x70 0xA8 0xE0 0x118 0x150 0x188 0x1C0 0x1F8 0x230 0x268 0x2A0 0x2D8 0x310 0x348 ) group.long ($2+0x3120)++0x3 line.long 0x0 "RGN_PRI_PER1_$1,This register is only used for resource manager to control privileged access permission." bitfld.long 0x0 31. "DOM7_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM7_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM7_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM7_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM6_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM6_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM6_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM6_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM5_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM5_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM5_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM5_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM4_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM4_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM4_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM4_PRI_EN,Domain privileged permission control enable" "0,1" repeat.end repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x38 0x70 0xA8 0xE0 0x118 0x150 0x188 0x1C0 0x1F8 0x230 0x268 0x2A0 0x2D8 0x310 0x348 ) group.long ($2+0x3124)++0x3 line.long 0x0 "RGN_PRI_PER2_$1,This register is only used for resource manager to control privileged access permission." bitfld.long 0x0 31. "DOM11_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM11_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM11_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM11_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM10_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM10_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM10_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM10_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM9_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM9_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM9_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM9_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM8_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM8_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM8_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM8_PRI_EN,Domain privileged permission control enable" "0,1" repeat.end repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x38 0x70 0xA8 0xE0 0x118 0x150 0x188 0x1C0 0x1F8 0x230 0x268 0x2A0 0x2D8 0x310 0x348 ) group.long ($2+0x3128)++0x3 line.long 0x0 "RGN_PRI_PER3_$1,This register is only used for resource manager to control privileged access permission." bitfld.long 0x0 31. "DOM15_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM15_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM15_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM15_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM14_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM14_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM14_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM14_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM13_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM13_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM13_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM13_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM12_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM12_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM12_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM12_PRI_EN,Domain privileged permission control enable" "0,1" repeat.end repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x38 0x70 0xA8 0xE0 0x118 0x150 0x188 0x1C0 0x1F8 0x230 0x268 0x2A0 0x2D8 0x310 0x348 ) group.long ($2+0x312C)++0x3 line.long 0x0 "RGN_DOM_SEC_PER_$1,This register is only used for domain master to control secure access permission. When the domain master write this register. it only changes the secure permission for itself. When the domain master read this register. it gets.." bitfld.long 0x0 7. "DOM_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" newline bitfld.long 0x0 0. "DOM_SEC_EN,Domain secure permission control enable" "0,1" repeat.end repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x38 0x70 0xA8 0xE0 0x118 0x150 0x188 0x1C0 0x1F8 0x230 0x268 0x2A0 0x2D8 0x310 0x348 ) group.long ($2+0x3130)++0x3 line.long 0x0 "RGN_DOM_PRI_PER_$1,This register is only used for domain master to control secure access permission. When the domain master write this register. it only changes the secure permission for itself. When the domain master read this register. it gets.." bitfld.long 0x0 7. "DOM_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" newline bitfld.long 0x0 0. "DOM_PRI_EN,Domain privileged permission control enable" "0,1" repeat.end repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x38 0x70 0xA8 0xE0 0x118 0x150 0x188 0x1C0 0x1F8 0x230 0x268 0x2A0 0x2D8 0x310 0x348 ) group.long ($2+0x3134)++0x3 line.long 0x0 "RGN_DOM_ASSIGN_$1,Use to assign domain for accessing DOM_SEC_PER and DOM_PRI_PER register. Only resource manager. group manager and domain owner can access this register. For write. group manager must write its owen domain ID. otherwise write accessing.." hexmask.long.byte 0x0 0.--3. 1. "DID,accessing DOM_SEC_PER and DOM_PRI_PER register" repeat.end tree.end tree "RPC_XPU_DISP_GLOBAL" base ad:0xF6FFE000 repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x4 0x8 0xC 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C ) group.long ($2)++0x3 line.long 0x0 "REGG0_DOM_$1,Assign domain for CKGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1A 0x1B 0x1C 0x1D 0x1E 0x1F )(list 0x40 0x44 0x48 0x4C 0x50 0x54 0x58 0x5C 0x60 0x64 0x68 0x6C 0x70 0x74 0x78 0x7C ) group.long ($2)++0x3 line.long 0x0 "REGG0_DOM_$1,Assign domain for CKGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x20 0x21 0x22 0x23 0x24 0x25 0x26 0x27 0x28 0x29 0x2A 0x2B 0x2C 0x2D 0x2E 0x2F )(list 0x80 0x84 0x88 0x8C 0x90 0x94 0x98 0x9C 0xA0 0xA4 0xA8 0xAC 0xB0 0xB4 0xB8 0xBC ) group.long ($2)++0x3 line.long 0x0 "REGG0_DOM_$1,Assign domain for CKGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x30 0x31 0x32 0x33 0x34 0x35 0x36 0x37 0x38 0x39 0x3A 0x3B 0x3C 0x3D 0x3E 0x3F )(list 0xC0 0xC4 0xC8 0xCC 0xD0 0xD4 0xD8 0xDC 0xE0 0xE4 0xE8 0xEC 0xF0 0xF4 0xF8 0xFC ) group.long ($2)++0x3 line.long 0x0 "REGG0_DOM_$1,Assign domain for CKGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x40 0x41 0x42 0x43 0x44 0x45 0x46 0x47 0x48 0x49 0x4A 0x4B 0x4C 0x4D 0x4E 0x4F )(list 0x100 0x104 0x108 0x10C 0x110 0x114 0x118 0x11C 0x120 0x124 0x128 0x12C 0x130 0x134 0x138 0x13C ) group.long ($2)++0x3 line.long 0x0 "REGG0_DOM_$1,Assign domain for CKGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x50 0x51 0x52 0x53 0x54 0x55 0x56 0x57 0x58 0x59 0x5A 0x5B 0x5C 0x5D 0x5E 0x5F )(list 0x140 0x144 0x148 0x14C 0x150 0x154 0x158 0x15C 0x160 0x164 0x168 0x16C 0x170 0x174 0x178 0x17C ) group.long ($2)++0x3 line.long 0x0 "REGG0_DOM_$1,Assign domain for CKGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x60 0x61 0x62 0x63 0x64 0x65 0x66 0x67 0x68 0x69 0x6A 0x6B 0x6C 0x6D 0x6E 0x6F )(list 0x180 0x184 0x188 0x18C 0x190 0x194 0x198 0x19C 0x1A0 0x1A4 0x1A8 0x1AC 0x1B0 0x1B4 0x1B8 0x1BC ) group.long ($2)++0x3 line.long 0x0 "REGG0_DOM_$1,Assign domain for CKGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x70 0x71 0x72 0x73 0x74 0x75 0x76 0x77 0x78 0x79 0x7A 0x7B 0x7C 0x7D 0x7E 0x7F )(list 0x1C0 0x1C4 0x1C8 0x1CC 0x1D0 0x1D4 0x1D8 0x1DC 0x1E0 0x1E4 0x1E8 0x1EC 0x1F0 0x1F4 0x1F8 0x1FC ) group.long ($2)++0x3 line.long 0x0 "REGG0_DOM_$1,Assign domain for CKGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x80 0x81 0x82 0x83 0x84 0x85 0x86 0x87 0x88 0x89 0x8A 0x8B 0x8C 0x8D 0x8E 0x8F )(list 0x200 0x204 0x208 0x20C 0x210 0x214 0x218 0x21C 0x220 0x224 0x228 0x22C 0x230 0x234 0x238 0x23C ) group.long ($2)++0x3 line.long 0x0 "REGG0_DOM_$1,Assign domain for CKGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x90 0x91 0x92 0x93 0x94 0x95 0x96 0x97 0x98 0x99 0x9A 0x9B 0x9C 0x9D 0x9E 0x9F )(list 0x240 0x244 0x248 0x24C 0x250 0x254 0x258 0x25C 0x260 0x264 0x268 0x26C 0x270 0x274 0x278 0x27C ) group.long ($2)++0x3 line.long 0x0 "REGG0_DOM_$1,Assign domain for CKGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xA0 0xA1 0xA2 0xA3 0xA4 0xA5 0xA6 0xA7 0xA8 0xA9 0xAA 0xAB 0xAC 0xAD 0xAE 0xAF )(list 0x280 0x284 0x288 0x28C 0x290 0x294 0x298 0x29C 0x2A0 0x2A4 0x2A8 0x2AC 0x2B0 0x2B4 0x2B8 0x2BC ) group.long ($2)++0x3 line.long 0x0 "REGG0_DOM_$1,Assign domain for CKGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xB0 0xB1 0xB2 0xB3 0xB4 0xB5 0xB6 0xB7 0xB8 0xB9 0xBA 0xBB 0xBC 0xBD 0xBE 0xBF )(list 0x2C0 0x2C4 0x2C8 0x2CC 0x2D0 0x2D4 0x2D8 0x2DC 0x2E0 0x2E4 0x2E8 0x2EC 0x2F0 0x2F4 0x2F8 0x2FC ) group.long ($2)++0x3 line.long 0x0 "REGG0_DOM_$1,Assign domain for CKGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xC0 0xC1 0xC2 0xC3 0xC4 0xC5 0xC6 0xC7 0xC8 0xC9 0xCA 0xCB 0xCC 0xCD 0xCE 0xCF )(list 0x300 0x304 0x308 0x30C 0x310 0x314 0x318 0x31C 0x320 0x324 0x328 0x32C 0x330 0x334 0x338 0x33C ) group.long ($2)++0x3 line.long 0x0 "REGG0_DOM_$1,Assign domain for CKGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xD0 0xD1 0xD2 0xD3 0xD4 0xD5 0xD6 0xD7 0xD8 0xD9 0xDA 0xDB 0xDC 0xDD 0xDE 0xDF )(list 0x340 0x344 0x348 0x34C 0x350 0x354 0x358 0x35C 0x360 0x364 0x368 0x36C 0x370 0x374 0x378 0x37C ) group.long ($2)++0x3 line.long 0x0 "REGG0_DOM_$1,Assign domain for CKGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xE0 0xE1 0xE2 0xE3 0xE4 0xE5 0xE6 0xE7 0xE8 0xE9 0xEA 0xEB 0xEC 0xED 0xEE 0xEF )(list 0x380 0x384 0x388 0x38C 0x390 0x394 0x398 0x39C 0x3A0 0x3A4 0x3A8 0x3AC 0x3B0 0x3B4 0x3B8 0x3BC ) group.long ($2)++0x3 line.long 0x0 "REGG0_DOM_$1,Assign domain for CKGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xF0 0xF1 0xF2 0xF3 0xF4 0xF5 0xF6 0xF7 0xF8 0xF9 0xFA 0xFB 0xFC 0xFD 0xFE 0xFF )(list 0x3C0 0x3C4 0x3C8 0x3CC 0x3D0 0x3D4 0x3D8 0x3DC 0x3E0 0x3E4 0x3E8 0x3EC 0x3F0 0x3F4 0x3F8 0x3FC ) group.long ($2)++0x3 line.long 0x0 "REGG0_DOM_$1,Assign domain for CKGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x4 0x8 0xC 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C ) group.long ($2+0x400)++0x3 line.long 0x0 "REGG1_DOM_$1,Assign domain for CKGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1A 0x1B 0x1C 0x1D 0x1E 0x1F )(list 0x40 0x44 0x48 0x4C 0x50 0x54 0x58 0x5C 0x60 0x64 0x68 0x6C 0x70 0x74 0x78 0x7C ) group.long ($2+0x400)++0x3 line.long 0x0 "REGG1_DOM_$1,Assign domain for CKGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x20 0x21 0x22 0x23 0x24 0x25 0x26 0x27 0x28 0x29 0x2A 0x2B 0x2C 0x2D 0x2E 0x2F )(list 0x80 0x84 0x88 0x8C 0x90 0x94 0x98 0x9C 0xA0 0xA4 0xA8 0xAC 0xB0 0xB4 0xB8 0xBC ) group.long ($2+0x400)++0x3 line.long 0x0 "REGG1_DOM_$1,Assign domain for CKGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x30 0x31 0x32 0x33 0x34 0x35 0x36 0x37 0x38 0x39 0x3A 0x3B 0x3C 0x3D 0x3E 0x3F )(list 0xC0 0xC4 0xC8 0xCC 0xD0 0xD4 0xD8 0xDC 0xE0 0xE4 0xE8 0xEC 0xF0 0xF4 0xF8 0xFC ) group.long ($2+0x400)++0x3 line.long 0x0 "REGG1_DOM_$1,Assign domain for CKGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x40 0x41 0x42 0x43 0x44 0x45 0x46 0x47 0x48 0x49 0x4A 0x4B 0x4C 0x4D 0x4E 0x4F )(list 0x100 0x104 0x108 0x10C 0x110 0x114 0x118 0x11C 0x120 0x124 0x128 0x12C 0x130 0x134 0x138 0x13C ) group.long ($2+0x400)++0x3 line.long 0x0 "REGG1_DOM_$1,Assign domain for CKGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x50 0x51 0x52 0x53 0x54 0x55 0x56 0x57 0x58 0x59 0x5A 0x5B 0x5C 0x5D 0x5E 0x5F )(list 0x140 0x144 0x148 0x14C 0x150 0x154 0x158 0x15C 0x160 0x164 0x168 0x16C 0x170 0x174 0x178 0x17C ) group.long ($2+0x400)++0x3 line.long 0x0 "REGG1_DOM_$1,Assign domain for CKGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x60 0x61 0x62 0x63 0x64 0x65 0x66 0x67 0x68 0x69 0x6A 0x6B 0x6C 0x6D 0x6E 0x6F )(list 0x180 0x184 0x188 0x18C 0x190 0x194 0x198 0x19C 0x1A0 0x1A4 0x1A8 0x1AC 0x1B0 0x1B4 0x1B8 0x1BC ) group.long ($2+0x400)++0x3 line.long 0x0 "REGG1_DOM_$1,Assign domain for CKGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x70 0x71 0x72 0x73 0x74 0x75 0x76 0x77 0x78 0x79 0x7A 0x7B 0x7C 0x7D 0x7E 0x7F )(list 0x1C0 0x1C4 0x1C8 0x1CC 0x1D0 0x1D4 0x1D8 0x1DC 0x1E0 0x1E4 0x1E8 0x1EC 0x1F0 0x1F4 0x1F8 0x1FC ) group.long ($2+0x400)++0x3 line.long 0x0 "REGG1_DOM_$1,Assign domain for CKGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x80 0x81 0x82 0x83 0x84 0x85 0x86 0x87 0x88 0x89 0x8A 0x8B 0x8C 0x8D 0x8E 0x8F )(list 0x200 0x204 0x208 0x20C 0x210 0x214 0x218 0x21C 0x220 0x224 0x228 0x22C 0x230 0x234 0x238 0x23C ) group.long ($2+0x400)++0x3 line.long 0x0 "REGG1_DOM_$1,Assign domain for CKGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x90 0x91 0x92 0x93 0x94 0x95 0x96 0x97 0x98 0x99 0x9A 0x9B 0x9C 0x9D 0x9E 0x9F )(list 0x240 0x244 0x248 0x24C 0x250 0x254 0x258 0x25C 0x260 0x264 0x268 0x26C 0x270 0x274 0x278 0x27C ) group.long ($2+0x400)++0x3 line.long 0x0 "REGG1_DOM_$1,Assign domain for CKGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xA0 0xA1 0xA2 0xA3 0xA4 0xA5 0xA6 0xA7 0xA8 0xA9 0xAA 0xAB 0xAC 0xAD 0xAE 0xAF )(list 0x280 0x284 0x288 0x28C 0x290 0x294 0x298 0x29C 0x2A0 0x2A4 0x2A8 0x2AC 0x2B0 0x2B4 0x2B8 0x2BC ) group.long ($2+0x400)++0x3 line.long 0x0 "REGG1_DOM_$1,Assign domain for CKGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xB0 0xB1 0xB2 0xB3 0xB4 0xB5 0xB6 0xB7 0xB8 0xB9 0xBA 0xBB 0xBC 0xBD 0xBE 0xBF )(list 0x2C0 0x2C4 0x2C8 0x2CC 0x2D0 0x2D4 0x2D8 0x2DC 0x2E0 0x2E4 0x2E8 0x2EC 0x2F0 0x2F4 0x2F8 0x2FC ) group.long ($2+0x400)++0x3 line.long 0x0 "REGG1_DOM_$1,Assign domain for CKGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xC0 0xC1 0xC2 0xC3 0xC4 0xC5 0xC6 0xC7 0xC8 0xC9 0xCA 0xCB 0xCC 0xCD 0xCE 0xCF )(list 0x300 0x304 0x308 0x30C 0x310 0x314 0x318 0x31C 0x320 0x324 0x328 0x32C 0x330 0x334 0x338 0x33C ) group.long ($2+0x400)++0x3 line.long 0x0 "REGG1_DOM_$1,Assign domain for CKGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xD0 0xD1 0xD2 0xD3 0xD4 0xD5 0xD6 0xD7 0xD8 0xD9 0xDA 0xDB 0xDC 0xDD 0xDE 0xDF )(list 0x340 0x344 0x348 0x34C 0x350 0x354 0x358 0x35C 0x360 0x364 0x368 0x36C 0x370 0x374 0x378 0x37C ) group.long ($2+0x400)++0x3 line.long 0x0 "REGG1_DOM_$1,Assign domain for CKGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xE0 0xE1 0xE2 0xE3 0xE4 0xE5 0xE6 0xE7 0xE8 0xE9 0xEA 0xEB 0xEC 0xED 0xEE 0xEF )(list 0x380 0x384 0x388 0x38C 0x390 0x394 0x398 0x39C 0x3A0 0x3A4 0x3A8 0x3AC 0x3B0 0x3B4 0x3B8 0x3BC ) group.long ($2+0x400)++0x3 line.long 0x0 "REGG1_DOM_$1,Assign domain for CKGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xF0 0xF1 0xF2 0xF3 0xF4 0xF5 0xF6 0xF7 0xF8 0xF9 0xFA 0xFB 0xFC 0xFD 0xFE 0xFF )(list 0x3C0 0x3C4 0x3C8 0x3CC 0x3D0 0x3D4 0x3D8 0x3DC 0x3E0 0x3E4 0x3E8 0x3EC 0x3F0 0x3F4 0x3F8 0x3FC ) group.long ($2+0x400)++0x3 line.long 0x0 "REGG1_DOM_$1,Assign domain for CKGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x4 0x8 0xC 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C ) group.long ($2+0x800)++0x3 line.long 0x0 "REGG2_DOM_$1,Assign domain for SCR registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1A 0x1B 0x1C 0x1D 0x1E 0x1F )(list 0x40 0x44 0x48 0x4C 0x50 0x54 0x58 0x5C 0x60 0x64 0x68 0x6C 0x70 0x74 0x78 0x7C ) group.long ($2+0x800)++0x3 line.long 0x0 "REGG2_DOM_$1,Assign domain for SCR registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x20 0x21 0x22 0x23 0x24 0x25 0x26 0x27 0x28 0x29 0x2A 0x2B 0x2C 0x2D 0x2E 0x2F )(list 0x80 0x84 0x88 0x8C 0x90 0x94 0x98 0x9C 0xA0 0xA4 0xA8 0xAC 0xB0 0xB4 0xB8 0xBC ) group.long ($2+0x800)++0x3 line.long 0x0 "REGG2_DOM_$1,Assign domain for SCR registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x30 0x31 0x32 0x33 0x34 0x35 0x36 0x37 0x38 0x39 0x3A 0x3B 0x3C 0x3D 0x3E 0x3F )(list 0xC0 0xC4 0xC8 0xCC 0xD0 0xD4 0xD8 0xDC 0xE0 0xE4 0xE8 0xEC 0xF0 0xF4 0xF8 0xFC ) group.long ($2+0x800)++0x3 line.long 0x0 "REGG2_DOM_$1,Assign domain for SCR registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x40 0x41 0x42 0x43 0x44 0x45 0x46 0x47 0x48 0x49 0x4A 0x4B 0x4C 0x4D 0x4E 0x4F )(list 0x100 0x104 0x108 0x10C 0x110 0x114 0x118 0x11C 0x120 0x124 0x128 0x12C 0x130 0x134 0x138 0x13C ) group.long ($2+0x800)++0x3 line.long 0x0 "REGG2_DOM_$1,Assign domain for SCR registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x50 0x51 0x52 0x53 0x54 0x55 0x56 0x57 0x58 0x59 0x5A 0x5B 0x5C 0x5D 0x5E 0x5F )(list 0x140 0x144 0x148 0x14C 0x150 0x154 0x158 0x15C 0x160 0x164 0x168 0x16C 0x170 0x174 0x178 0x17C ) group.long ($2+0x800)++0x3 line.long 0x0 "REGG2_DOM_$1,Assign domain for SCR registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x60 0x61 0x62 0x63 0x64 0x65 0x66 0x67 0x68 0x69 0x6A 0x6B 0x6C 0x6D 0x6E 0x6F )(list 0x180 0x184 0x188 0x18C 0x190 0x194 0x198 0x19C 0x1A0 0x1A4 0x1A8 0x1AC 0x1B0 0x1B4 0x1B8 0x1BC ) group.long ($2+0x800)++0x3 line.long 0x0 "REGG2_DOM_$1,Assign domain for SCR registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x70 0x71 0x72 0x73 0x74 0x75 0x76 0x77 0x78 0x79 0x7A 0x7B 0x7C 0x7D 0x7E 0x7F )(list 0x1C0 0x1C4 0x1C8 0x1CC 0x1D0 0x1D4 0x1D8 0x1DC 0x1E0 0x1E4 0x1E8 0x1EC 0x1F0 0x1F4 0x1F8 0x1FC ) group.long ($2+0x800)++0x3 line.long 0x0 "REGG2_DOM_$1,Assign domain for SCR registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x80 0x81 0x82 0x83 0x84 0x85 0x86 0x87 0x88 0x89 0x8A 0x8B 0x8C 0x8D 0x8E 0x8F )(list 0x200 0x204 0x208 0x20C 0x210 0x214 0x218 0x21C 0x220 0x224 0x228 0x22C 0x230 0x234 0x238 0x23C ) group.long ($2+0x800)++0x3 line.long 0x0 "REGG2_DOM_$1,Assign domain for SCR registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x90 0x91 0x92 0x93 0x94 0x95 0x96 0x97 0x98 0x99 0x9A 0x9B 0x9C 0x9D 0x9E 0x9F )(list 0x240 0x244 0x248 0x24C 0x250 0x254 0x258 0x25C 0x260 0x264 0x268 0x26C 0x270 0x274 0x278 0x27C ) group.long ($2+0x800)++0x3 line.long 0x0 "REGG2_DOM_$1,Assign domain for SCR registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xA0 0xA1 0xA2 0xA3 0xA4 0xA5 0xA6 0xA7 0xA8 0xA9 0xAA 0xAB 0xAC 0xAD 0xAE 0xAF )(list 0x280 0x284 0x288 0x28C 0x290 0x294 0x298 0x29C 0x2A0 0x2A4 0x2A8 0x2AC 0x2B0 0x2B4 0x2B8 0x2BC ) group.long ($2+0x800)++0x3 line.long 0x0 "REGG2_DOM_$1,Assign domain for SCR registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xB0 0xB1 0xB2 0xB3 0xB4 0xB5 0xB6 0xB7 0xB8 0xB9 0xBA 0xBB 0xBC 0xBD 0xBE 0xBF )(list 0x2C0 0x2C4 0x2C8 0x2CC 0x2D0 0x2D4 0x2D8 0x2DC 0x2E0 0x2E4 0x2E8 0x2EC 0x2F0 0x2F4 0x2F8 0x2FC ) group.long ($2+0x800)++0x3 line.long 0x0 "REGG2_DOM_$1,Assign domain for SCR registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xC0 0xC1 0xC2 0xC3 0xC4 0xC5 0xC6 0xC7 0xC8 0xC9 0xCA 0xCB 0xCC 0xCD 0xCE 0xCF )(list 0x300 0x304 0x308 0x30C 0x310 0x314 0x318 0x31C 0x320 0x324 0x328 0x32C 0x330 0x334 0x338 0x33C ) group.long ($2+0x800)++0x3 line.long 0x0 "REGG2_DOM_$1,Assign domain for SCR registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xD0 0xD1 0xD2 0xD3 0xD4 0xD5 0xD6 0xD7 0xD8 0xD9 0xDA 0xDB 0xDC 0xDD 0xDE 0xDF )(list 0x340 0x344 0x348 0x34C 0x350 0x354 0x358 0x35C 0x360 0x364 0x368 0x36C 0x370 0x374 0x378 0x37C ) group.long ($2+0x800)++0x3 line.long 0x0 "REGG2_DOM_$1,Assign domain for SCR registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xE0 0xE1 0xE2 0xE3 0xE4 0xE5 0xE6 0xE7 0xE8 0xE9 0xEA 0xEB 0xEC 0xED 0xEE 0xEF )(list 0x380 0x384 0x388 0x38C 0x390 0x394 0x398 0x39C 0x3A0 0x3A4 0x3A8 0x3AC 0x3B0 0x3B4 0x3B8 0x3BC ) group.long ($2+0x800)++0x3 line.long 0x0 "REGG2_DOM_$1,Assign domain for SCR registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xF0 0xF1 0xF2 0xF3 0xF4 0xF5 0xF6 0xF7 0xF8 0xF9 0xFA 0xFB 0xFC 0xFD 0xFE 0xFF )(list 0x3C0 0x3C4 0x3C8 0x3CC 0x3D0 0x3D4 0x3D8 0x3DC 0x3E0 0x3E4 0x3E8 0x3EC 0x3F0 0x3F4 0x3F8 0x3FC ) group.long ($2+0x800)++0x3 line.long 0x0 "REGG2_DOM_$1,Assign domain for SCR registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x4 0x8 0xC 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C ) group.long ($2+0xC00)++0x3 line.long 0x0 "REGG3_DOM_$1,Assign domain for SCR registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1A 0x1B 0x1C 0x1D 0x1E 0x1F )(list 0x40 0x44 0x48 0x4C 0x50 0x54 0x58 0x5C 0x60 0x64 0x68 0x6C 0x70 0x74 0x78 0x7C ) group.long ($2+0xC00)++0x3 line.long 0x0 "REGG3_DOM_$1,Assign domain for SCR registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x20 0x21 0x22 0x23 0x24 0x25 0x26 0x27 0x28 0x29 0x2A 0x2B 0x2C 0x2D 0x2E 0x2F )(list 0x80 0x84 0x88 0x8C 0x90 0x94 0x98 0x9C 0xA0 0xA4 0xA8 0xAC 0xB0 0xB4 0xB8 0xBC ) group.long ($2+0xC00)++0x3 line.long 0x0 "REGG3_DOM_$1,Assign domain for SCR registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x30 0x31 0x32 0x33 0x34 0x35 0x36 0x37 0x38 0x39 0x3A 0x3B 0x3C 0x3D 0x3E 0x3F )(list 0xC0 0xC4 0xC8 0xCC 0xD0 0xD4 0xD8 0xDC 0xE0 0xE4 0xE8 0xEC 0xF0 0xF4 0xF8 0xFC ) group.long ($2+0xC00)++0x3 line.long 0x0 "REGG3_DOM_$1,Assign domain for SCR registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x40 0x41 0x42 0x43 0x44 0x45 0x46 0x47 0x48 0x49 0x4A 0x4B 0x4C 0x4D 0x4E 0x4F )(list 0x100 0x104 0x108 0x10C 0x110 0x114 0x118 0x11C 0x120 0x124 0x128 0x12C 0x130 0x134 0x138 0x13C ) group.long ($2+0xC00)++0x3 line.long 0x0 "REGG3_DOM_$1,Assign domain for SCR registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x50 0x51 0x52 0x53 0x54 0x55 0x56 0x57 0x58 0x59 0x5A 0x5B 0x5C 0x5D 0x5E 0x5F )(list 0x140 0x144 0x148 0x14C 0x150 0x154 0x158 0x15C 0x160 0x164 0x168 0x16C 0x170 0x174 0x178 0x17C ) group.long ($2+0xC00)++0x3 line.long 0x0 "REGG3_DOM_$1,Assign domain for SCR registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x60 0x61 0x62 0x63 0x64 0x65 0x66 0x67 0x68 0x69 0x6A 0x6B 0x6C 0x6D 0x6E 0x6F )(list 0x180 0x184 0x188 0x18C 0x190 0x194 0x198 0x19C 0x1A0 0x1A4 0x1A8 0x1AC 0x1B0 0x1B4 0x1B8 0x1BC ) group.long ($2+0xC00)++0x3 line.long 0x0 "REGG3_DOM_$1,Assign domain for SCR registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x70 0x71 0x72 0x73 0x74 0x75 0x76 0x77 0x78 0x79 0x7A 0x7B 0x7C 0x7D 0x7E 0x7F )(list 0x1C0 0x1C4 0x1C8 0x1CC 0x1D0 0x1D4 0x1D8 0x1DC 0x1E0 0x1E4 0x1E8 0x1EC 0x1F0 0x1F4 0x1F8 0x1FC ) group.long ($2+0xC00)++0x3 line.long 0x0 "REGG3_DOM_$1,Assign domain for SCR registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x80 0x81 0x82 0x83 0x84 0x85 0x86 0x87 0x88 0x89 0x8A 0x8B 0x8C 0x8D 0x8E 0x8F )(list 0x200 0x204 0x208 0x20C 0x210 0x214 0x218 0x21C 0x220 0x224 0x228 0x22C 0x230 0x234 0x238 0x23C ) group.long ($2+0xC00)++0x3 line.long 0x0 "REGG3_DOM_$1,Assign domain for SCR registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x90 0x91 0x92 0x93 0x94 0x95 0x96 0x97 0x98 0x99 0x9A 0x9B 0x9C 0x9D 0x9E 0x9F )(list 0x240 0x244 0x248 0x24C 0x250 0x254 0x258 0x25C 0x260 0x264 0x268 0x26C 0x270 0x274 0x278 0x27C ) group.long ($2+0xC00)++0x3 line.long 0x0 "REGG3_DOM_$1,Assign domain for SCR registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xA0 0xA1 0xA2 0xA3 0xA4 0xA5 0xA6 0xA7 0xA8 0xA9 0xAA 0xAB 0xAC 0xAD 0xAE 0xAF )(list 0x280 0x284 0x288 0x28C 0x290 0x294 0x298 0x29C 0x2A0 0x2A4 0x2A8 0x2AC 0x2B0 0x2B4 0x2B8 0x2BC ) group.long ($2+0xC00)++0x3 line.long 0x0 "REGG3_DOM_$1,Assign domain for SCR registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xB0 0xB1 0xB2 0xB3 0xB4 0xB5 0xB6 0xB7 0xB8 0xB9 0xBA 0xBB 0xBC 0xBD 0xBE 0xBF )(list 0x2C0 0x2C4 0x2C8 0x2CC 0x2D0 0x2D4 0x2D8 0x2DC 0x2E0 0x2E4 0x2E8 0x2EC 0x2F0 0x2F4 0x2F8 0x2FC ) group.long ($2+0xC00)++0x3 line.long 0x0 "REGG3_DOM_$1,Assign domain for SCR registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xC0 0xC1 0xC2 0xC3 0xC4 0xC5 0xC6 0xC7 0xC8 0xC9 0xCA 0xCB 0xCC 0xCD 0xCE 0xCF )(list 0x300 0x304 0x308 0x30C 0x310 0x314 0x318 0x31C 0x320 0x324 0x328 0x32C 0x330 0x334 0x338 0x33C ) group.long ($2+0xC00)++0x3 line.long 0x0 "REGG3_DOM_$1,Assign domain for SCR registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xD0 0xD1 0xD2 0xD3 0xD4 0xD5 0xD6 0xD7 0xD8 0xD9 0xDA 0xDB 0xDC 0xDD 0xDE 0xDF )(list 0x340 0x344 0x348 0x34C 0x350 0x354 0x358 0x35C 0x360 0x364 0x368 0x36C 0x370 0x374 0x378 0x37C ) group.long ($2+0xC00)++0x3 line.long 0x0 "REGG3_DOM_$1,Assign domain for SCR registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xE0 0xE1 0xE2 0xE3 0xE4 0xE5 0xE6 0xE7 0xE8 0xE9 0xEA 0xEB 0xEC 0xED 0xEE 0xEF )(list 0x380 0x384 0x388 0x38C 0x390 0x394 0x398 0x39C 0x3A0 0x3A4 0x3A8 0x3AC 0x3B0 0x3B4 0x3B8 0x3BC ) group.long ($2+0xC00)++0x3 line.long 0x0 "REGG3_DOM_$1,Assign domain for SCR registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xF0 0xF1 0xF2 0xF3 0xF4 0xF5 0xF6 0xF7 0xF8 0xF9 0xFA 0xFB 0xFC 0xFD 0xFE 0xFF )(list 0x3C0 0x3C4 0x3C8 0x3CC 0x3D0 0x3D4 0x3D8 0x3DC 0x3E0 0x3E4 0x3E8 0x3EC 0x3F0 0x3F4 0x3F8 0x3FC ) group.long ($2+0xC00)++0x3 line.long 0x0 "REGG3_DOM_$1,Assign domain for SCR registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x4 0x8 0xC 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C ) group.long ($2+0x1000)++0x3 line.long 0x0 "REGG4_DOM_$1,Assign domain for RSTGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1A 0x1B 0x1C 0x1D 0x1E 0x1F )(list 0x40 0x44 0x48 0x4C 0x50 0x54 0x58 0x5C 0x60 0x64 0x68 0x6C 0x70 0x74 0x78 0x7C ) group.long ($2+0x1000)++0x3 line.long 0x0 "REGG4_DOM_$1,Assign domain for RSTGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x20 0x21 0x22 0x23 0x24 0x25 0x26 0x27 0x28 0x29 0x2A 0x2B 0x2C 0x2D 0x2E 0x2F )(list 0x80 0x84 0x88 0x8C 0x90 0x94 0x98 0x9C 0xA0 0xA4 0xA8 0xAC 0xB0 0xB4 0xB8 0xBC ) group.long ($2+0x1000)++0x3 line.long 0x0 "REGG4_DOM_$1,Assign domain for RSTGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x30 0x31 0x32 0x33 0x34 0x35 0x36 0x37 0x38 0x39 0x3A 0x3B 0x3C 0x3D 0x3E 0x3F )(list 0xC0 0xC4 0xC8 0xCC 0xD0 0xD4 0xD8 0xDC 0xE0 0xE4 0xE8 0xEC 0xF0 0xF4 0xF8 0xFC ) group.long ($2+0x1000)++0x3 line.long 0x0 "REGG4_DOM_$1,Assign domain for RSTGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x40 0x41 0x42 0x43 0x44 0x45 0x46 0x47 0x48 0x49 0x4A 0x4B 0x4C 0x4D 0x4E 0x4F )(list 0x100 0x104 0x108 0x10C 0x110 0x114 0x118 0x11C 0x120 0x124 0x128 0x12C 0x130 0x134 0x138 0x13C ) group.long ($2+0x1000)++0x3 line.long 0x0 "REGG4_DOM_$1,Assign domain for RSTGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x50 0x51 0x52 0x53 0x54 0x55 0x56 0x57 0x58 0x59 0x5A 0x5B 0x5C 0x5D 0x5E 0x5F )(list 0x140 0x144 0x148 0x14C 0x150 0x154 0x158 0x15C 0x160 0x164 0x168 0x16C 0x170 0x174 0x178 0x17C ) group.long ($2+0x1000)++0x3 line.long 0x0 "REGG4_DOM_$1,Assign domain for RSTGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x60 0x61 0x62 0x63 0x64 0x65 0x66 0x67 0x68 0x69 0x6A 0x6B 0x6C 0x6D 0x6E 0x6F )(list 0x180 0x184 0x188 0x18C 0x190 0x194 0x198 0x19C 0x1A0 0x1A4 0x1A8 0x1AC 0x1B0 0x1B4 0x1B8 0x1BC ) group.long ($2+0x1000)++0x3 line.long 0x0 "REGG4_DOM_$1,Assign domain for RSTGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x70 0x71 0x72 0x73 0x74 0x75 0x76 0x77 0x78 0x79 0x7A 0x7B 0x7C 0x7D 0x7E 0x7F )(list 0x1C0 0x1C4 0x1C8 0x1CC 0x1D0 0x1D4 0x1D8 0x1DC 0x1E0 0x1E4 0x1E8 0x1EC 0x1F0 0x1F4 0x1F8 0x1FC ) group.long ($2+0x1000)++0x3 line.long 0x0 "REGG4_DOM_$1,Assign domain for RSTGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x80 0x81 0x82 0x83 0x84 0x85 0x86 0x87 0x88 0x89 0x8A 0x8B 0x8C 0x8D 0x8E 0x8F )(list 0x200 0x204 0x208 0x20C 0x210 0x214 0x218 0x21C 0x220 0x224 0x228 0x22C 0x230 0x234 0x238 0x23C ) group.long ($2+0x1000)++0x3 line.long 0x0 "REGG4_DOM_$1,Assign domain for RSTGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x90 0x91 0x92 0x93 0x94 0x95 0x96 0x97 0x98 0x99 0x9A 0x9B 0x9C 0x9D 0x9E 0x9F )(list 0x240 0x244 0x248 0x24C 0x250 0x254 0x258 0x25C 0x260 0x264 0x268 0x26C 0x270 0x274 0x278 0x27C ) group.long ($2+0x1000)++0x3 line.long 0x0 "REGG4_DOM_$1,Assign domain for RSTGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xA0 0xA1 0xA2 0xA3 0xA4 0xA5 0xA6 0xA7 0xA8 0xA9 0xAA 0xAB 0xAC 0xAD 0xAE 0xAF )(list 0x280 0x284 0x288 0x28C 0x290 0x294 0x298 0x29C 0x2A0 0x2A4 0x2A8 0x2AC 0x2B0 0x2B4 0x2B8 0x2BC ) group.long ($2+0x1000)++0x3 line.long 0x0 "REGG4_DOM_$1,Assign domain for RSTGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xB0 0xB1 0xB2 0xB3 0xB4 0xB5 0xB6 0xB7 0xB8 0xB9 0xBA 0xBB 0xBC 0xBD 0xBE 0xBF )(list 0x2C0 0x2C4 0x2C8 0x2CC 0x2D0 0x2D4 0x2D8 0x2DC 0x2E0 0x2E4 0x2E8 0x2EC 0x2F0 0x2F4 0x2F8 0x2FC ) group.long ($2+0x1000)++0x3 line.long 0x0 "REGG4_DOM_$1,Assign domain for RSTGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xC0 0xC1 0xC2 0xC3 0xC4 0xC5 0xC6 0xC7 0xC8 0xC9 0xCA 0xCB 0xCC 0xCD 0xCE 0xCF )(list 0x300 0x304 0x308 0x30C 0x310 0x314 0x318 0x31C 0x320 0x324 0x328 0x32C 0x330 0x334 0x338 0x33C ) group.long ($2+0x1000)++0x3 line.long 0x0 "REGG4_DOM_$1,Assign domain for RSTGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xD0 0xD1 0xD2 0xD3 0xD4 0xD5 0xD6 0xD7 0xD8 0xD9 0xDA 0xDB 0xDC 0xDD 0xDE 0xDF )(list 0x340 0x344 0x348 0x34C 0x350 0x354 0x358 0x35C 0x360 0x364 0x368 0x36C 0x370 0x374 0x378 0x37C ) group.long ($2+0x1000)++0x3 line.long 0x0 "REGG4_DOM_$1,Assign domain for RSTGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xE0 0xE1 0xE2 0xE3 0xE4 0xE5 0xE6 0xE7 0xE8 0xE9 0xEA 0xEB 0xEC 0xED 0xEE 0xEF )(list 0x380 0x384 0x388 0x38C 0x390 0x394 0x398 0x39C 0x3A0 0x3A4 0x3A8 0x3AC 0x3B0 0x3B4 0x3B8 0x3BC ) group.long ($2+0x1000)++0x3 line.long 0x0 "REGG4_DOM_$1,Assign domain for RSTGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xF0 0xF1 0xF2 0xF3 0xF4 0xF5 0xF6 0xF7 0xF8 0xF9 0xFA 0xFB 0xFC 0xFD 0xFE 0xFF )(list 0x3C0 0x3C4 0x3C8 0x3CC 0x3D0 0x3D4 0x3D8 0x3DC 0x3E0 0x3E4 0x3E8 0x3EC 0x3F0 0x3F4 0x3F8 0x3FC ) group.long ($2+0x1000)++0x3 line.long 0x0 "REGG4_DOM_$1,Assign domain for RSTGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x4 0x8 0xC 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C ) group.long ($2+0x1400)++0x3 line.long 0x0 "REGG5_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1A 0x1B 0x1C 0x1D 0x1E 0x1F )(list 0x40 0x44 0x48 0x4C 0x50 0x54 0x58 0x5C 0x60 0x64 0x68 0x6C 0x70 0x74 0x78 0x7C ) group.long ($2+0x1400)++0x3 line.long 0x0 "REGG5_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x20 0x21 0x22 0x23 0x24 0x25 0x26 0x27 0x28 0x29 0x2A 0x2B 0x2C 0x2D 0x2E 0x2F )(list 0x80 0x84 0x88 0x8C 0x90 0x94 0x98 0x9C 0xA0 0xA4 0xA8 0xAC 0xB0 0xB4 0xB8 0xBC ) group.long ($2+0x1400)++0x3 line.long 0x0 "REGG5_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x30 0x31 0x32 0x33 0x34 0x35 0x36 0x37 0x38 0x39 0x3A 0x3B 0x3C 0x3D 0x3E 0x3F )(list 0xC0 0xC4 0xC8 0xCC 0xD0 0xD4 0xD8 0xDC 0xE0 0xE4 0xE8 0xEC 0xF0 0xF4 0xF8 0xFC ) group.long ($2+0x1400)++0x3 line.long 0x0 "REGG5_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x40 0x41 0x42 0x43 0x44 0x45 0x46 0x47 0x48 0x49 0x4A 0x4B 0x4C 0x4D 0x4E 0x4F )(list 0x100 0x104 0x108 0x10C 0x110 0x114 0x118 0x11C 0x120 0x124 0x128 0x12C 0x130 0x134 0x138 0x13C ) group.long ($2+0x1400)++0x3 line.long 0x0 "REGG5_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x50 0x51 0x52 0x53 0x54 0x55 0x56 0x57 0x58 0x59 0x5A 0x5B 0x5C 0x5D 0x5E 0x5F )(list 0x140 0x144 0x148 0x14C 0x150 0x154 0x158 0x15C 0x160 0x164 0x168 0x16C 0x170 0x174 0x178 0x17C ) group.long ($2+0x1400)++0x3 line.long 0x0 "REGG5_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x60 0x61 0x62 0x63 0x64 0x65 0x66 0x67 0x68 0x69 0x6A 0x6B 0x6C 0x6D 0x6E 0x6F )(list 0x180 0x184 0x188 0x18C 0x190 0x194 0x198 0x19C 0x1A0 0x1A4 0x1A8 0x1AC 0x1B0 0x1B4 0x1B8 0x1BC ) group.long ($2+0x1400)++0x3 line.long 0x0 "REGG5_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x70 0x71 0x72 0x73 0x74 0x75 0x76 0x77 0x78 0x79 0x7A 0x7B 0x7C 0x7D 0x7E 0x7F )(list 0x1C0 0x1C4 0x1C8 0x1CC 0x1D0 0x1D4 0x1D8 0x1DC 0x1E0 0x1E4 0x1E8 0x1EC 0x1F0 0x1F4 0x1F8 0x1FC ) group.long ($2+0x1400)++0x3 line.long 0x0 "REGG5_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x80 0x81 0x82 0x83 0x84 0x85 0x86 0x87 0x88 0x89 0x8A 0x8B 0x8C 0x8D 0x8E 0x8F )(list 0x200 0x204 0x208 0x20C 0x210 0x214 0x218 0x21C 0x220 0x224 0x228 0x22C 0x230 0x234 0x238 0x23C ) group.long ($2+0x1400)++0x3 line.long 0x0 "REGG5_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x90 0x91 0x92 0x93 0x94 0x95 0x96 0x97 0x98 0x99 0x9A 0x9B 0x9C 0x9D 0x9E 0x9F )(list 0x240 0x244 0x248 0x24C 0x250 0x254 0x258 0x25C 0x260 0x264 0x268 0x26C 0x270 0x274 0x278 0x27C ) group.long ($2+0x1400)++0x3 line.long 0x0 "REGG5_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xA0 0xA1 0xA2 0xA3 0xA4 0xA5 0xA6 0xA7 0xA8 0xA9 0xAA 0xAB 0xAC 0xAD 0xAE 0xAF )(list 0x280 0x284 0x288 0x28C 0x290 0x294 0x298 0x29C 0x2A0 0x2A4 0x2A8 0x2AC 0x2B0 0x2B4 0x2B8 0x2BC ) group.long ($2+0x1400)++0x3 line.long 0x0 "REGG5_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xB0 0xB1 0xB2 0xB3 0xB4 0xB5 0xB6 0xB7 0xB8 0xB9 0xBA 0xBB 0xBC 0xBD 0xBE 0xBF )(list 0x2C0 0x2C4 0x2C8 0x2CC 0x2D0 0x2D4 0x2D8 0x2DC 0x2E0 0x2E4 0x2E8 0x2EC 0x2F0 0x2F4 0x2F8 0x2FC ) group.long ($2+0x1400)++0x3 line.long 0x0 "REGG5_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xC0 0xC1 0xC2 0xC3 0xC4 0xC5 0xC6 0xC7 0xC8 0xC9 0xCA 0xCB 0xCC 0xCD 0xCE 0xCF )(list 0x300 0x304 0x308 0x30C 0x310 0x314 0x318 0x31C 0x320 0x324 0x328 0x32C 0x330 0x334 0x338 0x33C ) group.long ($2+0x1400)++0x3 line.long 0x0 "REGG5_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xD0 0xD1 0xD2 0xD3 0xD4 0xD5 0xD6 0xD7 0xD8 0xD9 0xDA 0xDB 0xDC 0xDD 0xDE 0xDF )(list 0x340 0x344 0x348 0x34C 0x350 0x354 0x358 0x35C 0x360 0x364 0x368 0x36C 0x370 0x374 0x378 0x37C ) group.long ($2+0x1400)++0x3 line.long 0x0 "REGG5_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xE0 0xE1 0xE2 0xE3 0xE4 0xE5 0xE6 0xE7 0xE8 0xE9 0xEA 0xEB 0xEC 0xED 0xEE 0xEF )(list 0x380 0x384 0x388 0x38C 0x390 0x394 0x398 0x39C 0x3A0 0x3A4 0x3A8 0x3AC 0x3B0 0x3B4 0x3B8 0x3BC ) group.long ($2+0x1400)++0x3 line.long 0x0 "REGG5_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xF0 0xF1 0xF2 0xF3 0xF4 0xF5 0xF6 0xF7 0xF8 0xF9 0xFA 0xFB 0xFC 0xFD 0xFE 0xFF )(list 0x3C0 0x3C4 0x3C8 0x3CC 0x3D0 0x3D4 0x3D8 0x3DC 0x3E0 0x3E4 0x3E8 0x3EC 0x3F0 0x3F4 0x3F8 0x3FC ) group.long ($2+0x1400)++0x3 line.long 0x0 "REGG5_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x4 0x8 0xC 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C ) group.long ($2+0x1800)++0x3 line.long 0x0 "REGG6_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1A 0x1B 0x1C 0x1D 0x1E 0x1F )(list 0x40 0x44 0x48 0x4C 0x50 0x54 0x58 0x5C 0x60 0x64 0x68 0x6C 0x70 0x74 0x78 0x7C ) group.long ($2+0x1800)++0x3 line.long 0x0 "REGG6_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x20 0x21 0x22 0x23 0x24 0x25 0x26 0x27 0x28 0x29 0x2A 0x2B 0x2C 0x2D 0x2E 0x2F )(list 0x80 0x84 0x88 0x8C 0x90 0x94 0x98 0x9C 0xA0 0xA4 0xA8 0xAC 0xB0 0xB4 0xB8 0xBC ) group.long ($2+0x1800)++0x3 line.long 0x0 "REGG6_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x30 0x31 0x32 0x33 0x34 0x35 0x36 0x37 0x38 0x39 0x3A 0x3B 0x3C 0x3D 0x3E 0x3F )(list 0xC0 0xC4 0xC8 0xCC 0xD0 0xD4 0xD8 0xDC 0xE0 0xE4 0xE8 0xEC 0xF0 0xF4 0xF8 0xFC ) group.long ($2+0x1800)++0x3 line.long 0x0 "REGG6_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x40 0x41 0x42 0x43 0x44 0x45 0x46 0x47 0x48 0x49 0x4A 0x4B 0x4C 0x4D 0x4E 0x4F )(list 0x100 0x104 0x108 0x10C 0x110 0x114 0x118 0x11C 0x120 0x124 0x128 0x12C 0x130 0x134 0x138 0x13C ) group.long ($2+0x1800)++0x3 line.long 0x0 "REGG6_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x50 0x51 0x52 0x53 0x54 0x55 0x56 0x57 0x58 0x59 0x5A 0x5B 0x5C 0x5D 0x5E 0x5F )(list 0x140 0x144 0x148 0x14C 0x150 0x154 0x158 0x15C 0x160 0x164 0x168 0x16C 0x170 0x174 0x178 0x17C ) group.long ($2+0x1800)++0x3 line.long 0x0 "REGG6_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x60 0x61 0x62 0x63 0x64 0x65 0x66 0x67 0x68 0x69 0x6A 0x6B 0x6C 0x6D 0x6E 0x6F )(list 0x180 0x184 0x188 0x18C 0x190 0x194 0x198 0x19C 0x1A0 0x1A4 0x1A8 0x1AC 0x1B0 0x1B4 0x1B8 0x1BC ) group.long ($2+0x1800)++0x3 line.long 0x0 "REGG6_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x70 0x71 0x72 0x73 0x74 0x75 0x76 0x77 0x78 0x79 0x7A 0x7B 0x7C 0x7D 0x7E 0x7F )(list 0x1C0 0x1C4 0x1C8 0x1CC 0x1D0 0x1D4 0x1D8 0x1DC 0x1E0 0x1E4 0x1E8 0x1EC 0x1F0 0x1F4 0x1F8 0x1FC ) group.long ($2+0x1800)++0x3 line.long 0x0 "REGG6_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x80 0x81 0x82 0x83 0x84 0x85 0x86 0x87 0x88 0x89 0x8A 0x8B 0x8C 0x8D 0x8E 0x8F )(list 0x200 0x204 0x208 0x20C 0x210 0x214 0x218 0x21C 0x220 0x224 0x228 0x22C 0x230 0x234 0x238 0x23C ) group.long ($2+0x1800)++0x3 line.long 0x0 "REGG6_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x90 0x91 0x92 0x93 0x94 0x95 0x96 0x97 0x98 0x99 0x9A 0x9B 0x9C 0x9D 0x9E 0x9F )(list 0x240 0x244 0x248 0x24C 0x250 0x254 0x258 0x25C 0x260 0x264 0x268 0x26C 0x270 0x274 0x278 0x27C ) group.long ($2+0x1800)++0x3 line.long 0x0 "REGG6_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xA0 0xA1 0xA2 0xA3 0xA4 0xA5 0xA6 0xA7 0xA8 0xA9 0xAA 0xAB 0xAC 0xAD 0xAE 0xAF )(list 0x280 0x284 0x288 0x28C 0x290 0x294 0x298 0x29C 0x2A0 0x2A4 0x2A8 0x2AC 0x2B0 0x2B4 0x2B8 0x2BC ) group.long ($2+0x1800)++0x3 line.long 0x0 "REGG6_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xB0 0xB1 0xB2 0xB3 0xB4 0xB5 0xB6 0xB7 0xB8 0xB9 0xBA 0xBB 0xBC 0xBD 0xBE 0xBF )(list 0x2C0 0x2C4 0x2C8 0x2CC 0x2D0 0x2D4 0x2D8 0x2DC 0x2E0 0x2E4 0x2E8 0x2EC 0x2F0 0x2F4 0x2F8 0x2FC ) group.long ($2+0x1800)++0x3 line.long 0x0 "REGG6_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xC0 0xC1 0xC2 0xC3 0xC4 0xC5 0xC6 0xC7 0xC8 0xC9 0xCA 0xCB 0xCC 0xCD 0xCE 0xCF )(list 0x300 0x304 0x308 0x30C 0x310 0x314 0x318 0x31C 0x320 0x324 0x328 0x32C 0x330 0x334 0x338 0x33C ) group.long ($2+0x1800)++0x3 line.long 0x0 "REGG6_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xD0 0xD1 0xD2 0xD3 0xD4 0xD5 0xD6 0xD7 0xD8 0xD9 0xDA 0xDB 0xDC 0xDD 0xDE 0xDF )(list 0x340 0x344 0x348 0x34C 0x350 0x354 0x358 0x35C 0x360 0x364 0x368 0x36C 0x370 0x374 0x378 0x37C ) group.long ($2+0x1800)++0x3 line.long 0x0 "REGG6_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xE0 0xE1 0xE2 0xE3 0xE4 0xE5 0xE6 0xE7 0xE8 0xE9 0xEA 0xEB 0xEC 0xED 0xEE 0xEF )(list 0x380 0x384 0x388 0x38C 0x390 0x394 0x398 0x39C 0x3A0 0x3A4 0x3A8 0x3AC 0x3B0 0x3B4 0x3B8 0x3BC ) group.long ($2+0x1800)++0x3 line.long 0x0 "REGG6_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xF0 0xF1 0xF2 0xF3 0xF4 0xF5 0xF6 0xF7 0xF8 0xF9 0xFA 0xFB 0xFC 0xFD 0xFE 0xFF )(list 0x3C0 0x3C4 0x3C8 0x3CC 0x3D0 0x3D4 0x3D8 0x3DC 0x3E0 0x3E4 0x3E8 0x3EC 0x3F0 0x3F4 0x3F8 0x3FC ) group.long ($2+0x1800)++0x3 line.long 0x0 "REGG6_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x4 0x8 0xC 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C ) group.long ($2+0x1C00)++0x3 line.long 0x0 "REGG7_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1A 0x1B 0x1C 0x1D 0x1E 0x1F )(list 0x40 0x44 0x48 0x4C 0x50 0x54 0x58 0x5C 0x60 0x64 0x68 0x6C 0x70 0x74 0x78 0x7C ) group.long ($2+0x1C00)++0x3 line.long 0x0 "REGG7_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x20 0x21 0x22 0x23 0x24 0x25 0x26 0x27 0x28 0x29 0x2A 0x2B 0x2C 0x2D 0x2E 0x2F )(list 0x80 0x84 0x88 0x8C 0x90 0x94 0x98 0x9C 0xA0 0xA4 0xA8 0xAC 0xB0 0xB4 0xB8 0xBC ) group.long ($2+0x1C00)++0x3 line.long 0x0 "REGG7_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x30 0x31 0x32 0x33 0x34 0x35 0x36 0x37 0x38 0x39 0x3A 0x3B 0x3C 0x3D 0x3E 0x3F )(list 0xC0 0xC4 0xC8 0xCC 0xD0 0xD4 0xD8 0xDC 0xE0 0xE4 0xE8 0xEC 0xF0 0xF4 0xF8 0xFC ) group.long ($2+0x1C00)++0x3 line.long 0x0 "REGG7_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x40 0x41 0x42 0x43 0x44 0x45 0x46 0x47 0x48 0x49 0x4A 0x4B 0x4C 0x4D 0x4E 0x4F )(list 0x100 0x104 0x108 0x10C 0x110 0x114 0x118 0x11C 0x120 0x124 0x128 0x12C 0x130 0x134 0x138 0x13C ) group.long ($2+0x1C00)++0x3 line.long 0x0 "REGG7_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x50 0x51 0x52 0x53 0x54 0x55 0x56 0x57 0x58 0x59 0x5A 0x5B 0x5C 0x5D 0x5E 0x5F )(list 0x140 0x144 0x148 0x14C 0x150 0x154 0x158 0x15C 0x160 0x164 0x168 0x16C 0x170 0x174 0x178 0x17C ) group.long ($2+0x1C00)++0x3 line.long 0x0 "REGG7_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x60 0x61 0x62 0x63 0x64 0x65 0x66 0x67 0x68 0x69 0x6A 0x6B 0x6C 0x6D 0x6E 0x6F )(list 0x180 0x184 0x188 0x18C 0x190 0x194 0x198 0x19C 0x1A0 0x1A4 0x1A8 0x1AC 0x1B0 0x1B4 0x1B8 0x1BC ) group.long ($2+0x1C00)++0x3 line.long 0x0 "REGG7_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x70 0x71 0x72 0x73 0x74 0x75 0x76 0x77 0x78 0x79 0x7A 0x7B 0x7C 0x7D 0x7E 0x7F )(list 0x1C0 0x1C4 0x1C8 0x1CC 0x1D0 0x1D4 0x1D8 0x1DC 0x1E0 0x1E4 0x1E8 0x1EC 0x1F0 0x1F4 0x1F8 0x1FC ) group.long ($2+0x1C00)++0x3 line.long 0x0 "REGG7_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x80 0x81 0x82 0x83 0x84 0x85 0x86 0x87 0x88 0x89 0x8A 0x8B 0x8C 0x8D 0x8E 0x8F )(list 0x200 0x204 0x208 0x20C 0x210 0x214 0x218 0x21C 0x220 0x224 0x228 0x22C 0x230 0x234 0x238 0x23C ) group.long ($2+0x1C00)++0x3 line.long 0x0 "REGG7_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x90 0x91 0x92 0x93 0x94 0x95 0x96 0x97 0x98 0x99 0x9A 0x9B 0x9C 0x9D 0x9E 0x9F )(list 0x240 0x244 0x248 0x24C 0x250 0x254 0x258 0x25C 0x260 0x264 0x268 0x26C 0x270 0x274 0x278 0x27C ) group.long ($2+0x1C00)++0x3 line.long 0x0 "REGG7_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xA0 0xA1 0xA2 0xA3 0xA4 0xA5 0xA6 0xA7 0xA8 0xA9 0xAA 0xAB 0xAC 0xAD 0xAE 0xAF )(list 0x280 0x284 0x288 0x28C 0x290 0x294 0x298 0x29C 0x2A0 0x2A4 0x2A8 0x2AC 0x2B0 0x2B4 0x2B8 0x2BC ) group.long ($2+0x1C00)++0x3 line.long 0x0 "REGG7_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xB0 0xB1 0xB2 0xB3 0xB4 0xB5 0xB6 0xB7 0xB8 0xB9 0xBA 0xBB 0xBC 0xBD 0xBE 0xBF )(list 0x2C0 0x2C4 0x2C8 0x2CC 0x2D0 0x2D4 0x2D8 0x2DC 0x2E0 0x2E4 0x2E8 0x2EC 0x2F0 0x2F4 0x2F8 0x2FC ) group.long ($2+0x1C00)++0x3 line.long 0x0 "REGG7_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xC0 0xC1 0xC2 0xC3 0xC4 0xC5 0xC6 0xC7 0xC8 0xC9 0xCA 0xCB 0xCC 0xCD 0xCE 0xCF )(list 0x300 0x304 0x308 0x30C 0x310 0x314 0x318 0x31C 0x320 0x324 0x328 0x32C 0x330 0x334 0x338 0x33C ) group.long ($2+0x1C00)++0x3 line.long 0x0 "REGG7_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xD0 0xD1 0xD2 0xD3 0xD4 0xD5 0xD6 0xD7 0xD8 0xD9 0xDA 0xDB 0xDC 0xDD 0xDE 0xDF )(list 0x340 0x344 0x348 0x34C 0x350 0x354 0x358 0x35C 0x360 0x364 0x368 0x36C 0x370 0x374 0x378 0x37C ) group.long ($2+0x1C00)++0x3 line.long 0x0 "REGG7_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xE0 0xE1 0xE2 0xE3 0xE4 0xE5 0xE6 0xE7 0xE8 0xE9 0xEA 0xEB 0xEC 0xED 0xEE 0xEF )(list 0x380 0x384 0x388 0x38C 0x390 0x394 0x398 0x39C 0x3A0 0x3A4 0x3A8 0x3AC 0x3B0 0x3B4 0x3B8 0x3BC ) group.long ($2+0x1C00)++0x3 line.long 0x0 "REGG7_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xF0 0xF1 0xF2 0xF3 0xF4 0xF5 0xF6 0xF7 0xF8 0xF9 0xFA 0xFB 0xFC 0xFD 0xFE 0xFF )(list 0x3C0 0x3C4 0x3C8 0x3CC 0x3D0 0x3D4 0x3D8 0x3DC 0x3E0 0x3E4 0x3E8 0x3EC 0x3F0 0x3F4 0x3F8 0x3FC ) group.long ($2+0x1C00)++0x3 line.long 0x0 "REGG7_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end group.long 0x2000++0x17 line.long 0x0 "GLB_CTL,This register provides global enable settings for permission control." bitfld.long 0x0 5. "DOM_CFG_LOCK,Lock write for DOM_CFG_MODE bit." "0,1" bitfld.long 0x0 4. "DOM_CFG_MODE,When enabled all the source setting can be configured by master from domain 0 if it is not locked. When disabled only resource manager can configure the permission of the resource." "0,1" bitfld.long 0x0 3. "PERCK_DIS_LOCK,Lock write for PERCK_DIS" "0,1" bitfld.long 0x0 2. "PERCK_DIS,All the permission check disable." "0,1" newline bitfld.long 0x0 1. "DOM_PRO_LOCK,Lock write for DOM_PRO_EN bit." "0,1" bitfld.long 0x0 0. "DOM_PRO_EN,When disabled no domain access permission check" "0,1" line.long 0x4 "RES_MGR,Resource manager register. This regster is used to assign resource manager for global resource access control" bitfld.long 0x4 17. "MID_LOCK,Lock write for MID_EN and MID_LOW and MID_HIG registers." "0,1" bitfld.long 0x4 16. "MID_EN,Master ID check enable" "0,1" bitfld.long 0x4 15. "PRI_PER_LOCK,Lock write for PRI_PER and PRI_PER_EN" "0,1" bitfld.long 0x4 13.--14. "PRI_PER,Resource manager privileged access permission. bit0 for privileged access bit1 for user access" "0,1,2,3" newline bitfld.long 0x4 12. "PRI_PER_EN,Resource manager privileged access permission enable." "0,1" bitfld.long 0x4 11. "SEC_PER_LOCK,Lock for SEC_PER and SEC_PER_LOCK" "0,1" bitfld.long 0x4 9.--10. "SEC_PER,Resource manager secure access permission. bit 0 for secure access bit 1 for non-secure access" "0,1,2,3" bitfld.long 0x4 8. "SEC_PER_EN,Resource manager secure permission enable" "0,1" bitfld.long 0x4 7. "DID_LOCK,Lock write for DID_EN and DID" "0,1" newline hexmask.long.byte 0x4 3.--6. 1. "DID,Resource manager domain ID" bitfld.long 0x4 2. "DID_EN,Resource manager Domain ID enable" "0,1" bitfld.long 0x4 1. "RES_MGR_EN_LOCK,Lock for RES_MGR_EN" "0,1" bitfld.long 0x4 0. "RES_MGR_EN,Resource manager enable. When the bit is disable there is no resource manager." "0,1" line.long 0x8 "RES_MGR_MA0,This register is used to assign master 0~31 as resource manager." hexmask.long 0x8 0.--31. 1. "MID,Assign master 0~31 for resource manager" line.long 0xC "RES_MGR_MA1,This register is used to assign master 32~63 as resource manager." hexmask.long 0xC 0.--31. 1. "MID,Indicate if master 32~63 is resource manager." line.long 0x10 "RES_MGR_MA2,This register is used to assign master 64~95 as resource manager." hexmask.long 0x10 0.--31. 1. "MID,Indicate if master 64~95 is resource manager." line.long 0x14 "RES_MGR_MA3,This register is used to assign master 96~127 as resource manager." hexmask.long 0x14 0.--31. 1. "MID,Indicate if master 96~127 is resource manager." repeat 8. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 )(list 0x0 0x14 0x28 0x3C 0x50 0x64 0x78 0x8C ) group.long ($2+0x2100)++0x3 line.long 0x0 "GRP_MGR_$1,Group Manager Register. This register is used to assign group manager for each domain" bitfld.long 0x0 17. "MID_LOCK,Lock write for MID_EN and MID_LOW and MID_HIG registers." "0,1" bitfld.long 0x0 16. "MID_EN,Master ID check enable" "0,1" bitfld.long 0x0 15. "PRI_PER_LOCK,Lock write for PRI_PER and PRI_PER_EN" "0,1" bitfld.long 0x0 13.--14. "PRI_PER,Group manager privileged access permission. bit0 for privileged access bit1 for user access" "0,1,2,3" newline bitfld.long 0x0 12. "PRI_PER_EN,Group manager privileged access permission enable." "0,1" bitfld.long 0x0 11. "SEC_PER_LOCK,Lock for SEC_PER and SEC_PER_LOCK" "0,1" bitfld.long 0x0 9.--10. "SEC_PER,Group manager secure access permission. bit 0 for secure access bit 1 for non-secure access" "0,1,2,3" bitfld.long 0x0 8. "SEC_PER_EN,Group manager secure permission enable" "0,1" bitfld.long 0x0 7. "DID_LOCK,Lock write for DID_EN and DID" "0,1" newline hexmask.long.byte 0x0 3.--6. 1. "DID,Group manager domain ID" bitfld.long 0x0 2. "DID_EN,Group manager Domain ID enable" "0,1" bitfld.long 0x0 1. "GRP_MGR_EN_LOCK,Lock write for GPR_MGR_EN" "0,1" bitfld.long 0x0 0. "GRP_MGR_EN,Group manager enable. When the bit is disable there is no resource manager." "0,1" repeat.end repeat 8. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 )(list 0x0 0x14 0x28 0x3C 0x50 0x64 0x78 0x8C ) group.long ($2+0x2104)++0x3 line.long 0x0 "GRP_MGR_MA0_$1,Assign master 0~31 for group manager 0" hexmask.long 0x0 0.--31. 1. "MID,Assign master 0~31 for resource manager" repeat.end repeat 8. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 )(list 0x0 0x14 0x28 0x3C 0x50 0x64 0x78 0x8C ) group.long ($2+0x2108)++0x3 line.long 0x0 "GRP_MGR_MA1_$1,Assign master 32~63 for group manager 0" hexmask.long 0x0 0.--31. 1. "MID,Indicate if master 32~63 is resource manager." repeat.end repeat 8. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 )(list 0x0 0x14 0x28 0x3C 0x50 0x64 0x78 0x8C ) group.long ($2+0x210C)++0x3 line.long 0x0 "GRP_MGR_MA2_$1,Assign master 64~95 for group manager 0" hexmask.long 0x0 0.--31. 1. "MID,Indicate if master 64~95 is resource manager." repeat.end repeat 8. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 )(list 0x0 0x14 0x28 0x3C 0x50 0x64 0x78 0x8C ) group.long ($2+0x2110)++0x3 line.long 0x0 "GRP_MGR_MA3_$1,Assign master 96~127 for group manager 0" hexmask.long 0x0 0.--31. 1. "MID,Indicate if master 96~127 is resource manager." repeat.end group.long 0x2200++0x3 line.long 0x0 "DOM_GID_0,Indicate which group domain 0 belong to" bitfld.long 0x0 3. "LOCK,Lock write for GID" "0,1" bitfld.long 0x0 0.--2. "GID,Group ID" "0,1,2,3,4,5,6,7" repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x18 0x30 0x48 0x60 0x78 0x90 0xA8 0xC0 0xD8 0xF0 0x108 0x120 0x138 0x150 0x168 ) group.long ($2+0x2204)++0x3 line.long 0x0 "DOM_OWN_$1,Assign owner for function domain 0." bitfld.long 0x0 17. "MID_LOCK,Lock write for MID_EN and MID_LOW and MID_HIG registers." "0,1" bitfld.long 0x0 16. "MID_EN,Master ID check enable" "0,1" bitfld.long 0x0 15. "PRI_PER_LOCK,Lock write for PRI_PER and PRI_PER_EN" "0,1" bitfld.long 0x0 13.--14. "PRI_PER,Group manager privileged access permission. bit0 for privileged access bit1 for user access" "0,1,2,3" newline bitfld.long 0x0 12. "PRI_PER_EN,Group manager privileged access permission enable." "0,1" bitfld.long 0x0 11. "SEC_PER_LOCK,Lock for SEC_PER and SEC_PER_LOCK" "0,1" bitfld.long 0x0 9.--10. "SEC_PER,Domain owner secure access permission. bit 0 for secure access bit 1 for non-secure access" "0,1,2,3" bitfld.long 0x0 8. "SEC_PER_EN,Domain owner secure permission enable" "0,1" newline bitfld.long 0x0 1. "DOM_OWN_EN_LOCK,Lock for DOM_OWN_EN" "0,1" bitfld.long 0x0 0. "DOM_OWN_EN,Domain owner enable. When the bit is disable there is no domain owner." "0,1" repeat.end repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x18 0x30 0x48 0x60 0x78 0x90 0xA8 0xC0 0xD8 0xF0 0x108 0x120 0x138 0x150 0x168 ) group.long ($2+0x2208)++0x3 line.long 0x0 "DOM_OWN_MA0_$1,Assign master 0~31 for domain owner 0" hexmask.long 0x0 0.--31. 1. "MID,Assign master 0~31 for resource manager" repeat.end repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x18 0x30 0x48 0x60 0x78 0x90 0xA8 0xC0 0xD8 0xF0 0x108 0x120 0x138 0x150 0x168 ) group.long ($2+0x220C)++0x3 line.long 0x0 "DOM_OWN_MA1_$1,Assign master 32~63 for domain owner 0" hexmask.long 0x0 0.--31. 1. "MID,Indicate if master 32~63 is resource manager." repeat.end repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x18 0x30 0x48 0x60 0x78 0x90 0xA8 0xC0 0xD8 0xF0 0x108 0x120 0x138 0x150 0x168 ) group.long ($2+0x2210)++0x3 line.long 0x0 "DOM_OWN_MA2_$1,Assign master 64~95 for domain owner 0" hexmask.long 0x0 0.--31. 1. "MID,Indicate if master 64~95 is resource manager." repeat.end repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x18 0x30 0x48 0x60 0x78 0x90 0xA8 0xC0 0xD8 0xF0 0x108 0x120 0x138 0x150 0x168 ) group.long ($2+0x2214)++0x3 line.long 0x0 "DOM_OWN_MA3_$1,Assign master 96~127 for domain owner 0" hexmask.long 0x0 0.--31. 1. "MID,Indicate if master 96~127 is resource manager." repeat.end group.long 0x2218++0x3 line.long 0x0 "DOM_GID_1,Indicate which group domain 1 belong to" bitfld.long 0x0 3. "LOCK,Lock write for GID" "0,1" bitfld.long 0x0 0.--2. "GID,Group ID" "0,1,2,3,4,5,6,7" group.long 0x2230++0x3 line.long 0x0 "DOM_GID_2,Indicate which group domain 2 belong to" bitfld.long 0x0 3. "LOCK,Lock write for GID" "0,1" bitfld.long 0x0 0.--2. "GID,Group ID" "0,1,2,3,4,5,6,7" group.long 0x2248++0x3 line.long 0x0 "DOM_GID_3,Indicate which group domain 3 belong to" bitfld.long 0x0 3. "LOCK,Lock write for GID" "0,1" bitfld.long 0x0 0.--2. "GID,Group ID" "0,1,2,3,4,5,6,7" group.long 0x2260++0x3 line.long 0x0 "DOM_GID_4,Indicate which group domain 4 belong to" bitfld.long 0x0 3. "LOCK,Lock write for GID" "0,1" bitfld.long 0x0 0.--2. "GID,Group ID" "0,1,2,3,4,5,6,7" group.long 0x2278++0x3 line.long 0x0 "DOM_GID_5,Indicate which group domain 5 belong to" bitfld.long 0x0 3. "LOCK,Lock write for GID" "0,1" bitfld.long 0x0 0.--2. "GID,Group ID" "0,1,2,3,4,5,6,7" group.long 0x2290++0x3 line.long 0x0 "DOM_GID_6,Indicate which group domain 6 belong to" bitfld.long 0x0 3. "LOCK,Lock write for GID" "0,1" bitfld.long 0x0 0.--2. "GID,Group ID" "0,1,2,3,4,5,6,7" group.long 0x22A8++0x3 line.long 0x0 "DOM_GID_7,Indicate which group domain 7 belong to" bitfld.long 0x0 3. "LOCK,Lock write for GID" "0,1" bitfld.long 0x0 0.--2. "GID,Group ID" "0,1,2,3,4,5,6,7" group.long 0x22C0++0x3 line.long 0x0 "DOM_GID_8,Indicate which group domain 8 belong to" bitfld.long 0x0 3. "LOCK,Lock write for GID" "0,1" bitfld.long 0x0 0.--2. "GID,Group ID" "0,1,2,3,4,5,6,7" group.long 0x22D8++0x3 line.long 0x0 "DOM_GID_9,Indicate which group domain 9 belong to" bitfld.long 0x0 3. "LOCK,Lock write for GID" "0,1" bitfld.long 0x0 0.--2. "GID,Group ID" "0,1,2,3,4,5,6,7" group.long 0x22F0++0x3 line.long 0x0 "DOM_GID_10,Indicate which group domain 10 belong to" bitfld.long 0x0 3. "LOCK,Lock write for GID" "0,1" bitfld.long 0x0 0.--2. "GID,Group ID" "0,1,2,3,4,5,6,7" group.long 0x2308++0x3 line.long 0x0 "DOM_GID_11,Indicate which group domain 11 belong to" bitfld.long 0x0 3. "LOCK,Lock write for GID" "0,1" bitfld.long 0x0 0.--2. "GID,Group ID" "0,1,2,3,4,5,6,7" group.long 0x2320++0x3 line.long 0x0 "DOM_GID_12,Indicate which group domain 12 belong to" bitfld.long 0x0 3. "LOCK,Lock write for GID" "0,1" bitfld.long 0x0 0.--2. "GID,Group ID" "0,1,2,3,4,5,6,7" group.long 0x2338++0x3 line.long 0x0 "DOM_GID_13,Indicate which group domain 13 belong to" bitfld.long 0x0 3. "LOCK,Lock write for GID" "0,1" bitfld.long 0x0 0.--2. "GID,Group ID" "0,1,2,3,4,5,6,7" group.long 0x2350++0x3 line.long 0x0 "DOM_GID_14,Indicate which group domain 14 belong to" bitfld.long 0x0 3. "LOCK,Lock write for GID" "0,1" bitfld.long 0x0 0.--2. "GID,Group ID" "0,1,2,3,4,5,6,7" group.long 0x2368++0x3 line.long 0x0 "DOM_GID_15,Indicate which group domain 15 belong to" bitfld.long 0x0 3. "LOCK,Lock write for GID" "0,1" bitfld.long 0x0 0.--2. "GID,Group ID" "0,1,2,3,4,5,6,7" repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x34 0x68 0x9C 0xD0 0x104 0x138 0x16C 0x1A0 0x1D4 0x208 0x23C 0x270 0x2A4 0x2D8 0x30C ) group.long ($2+0x2400)++0x3 line.long 0x0 "DOM_PER0_$1,Domain Permission Control. It can be only configured by resource manager and domain owner." bitfld.long 0x0 31. "DOM7_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 29.--30. "DOM7_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 28. "DOM7_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 27. "DOM6_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 25.--26. "DOM6_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" newline bitfld.long 0x0 24. "DOM6_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 23. "DOM5_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 21.--22. "DOM5_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 20. "DOM5_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 19. "DOM4_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" newline bitfld.long 0x0 17.--18. "DOM4_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM4_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 15. "DOM3_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 13.--14. "DOM3_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 12. "DOM3_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" newline bitfld.long 0x0 11. "DOM2_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 9.--10. "DOM2_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM2_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 7. "DOM1_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 5.--6. "DOM1_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" newline bitfld.long 0x0 4. "DOM1_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 3. "DOM0_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 1.--2. "DOM0_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM0_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" repeat.end repeat 16. (list 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1A 0x1B 0x1C 0x1D 0x1E 0x1F )(list 0x340 0x374 0x3A8 0x3DC 0x410 0x444 0x478 0x4AC 0x4E0 0x514 0x548 0x57C 0x5B0 0x5E4 0x618 0x64C ) group.long ($2+0x2400)++0x3 line.long 0x0 "DOM_PER0_$1,Domain Permission Control. It can be only configured by resource manager and domain owner." bitfld.long 0x0 31. "DOM7_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 29.--30. "DOM7_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 28. "DOM7_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 27. "DOM6_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 25.--26. "DOM6_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" newline bitfld.long 0x0 24. "DOM6_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 23. "DOM5_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 21.--22. "DOM5_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 20. "DOM5_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 19. "DOM4_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" newline bitfld.long 0x0 17.--18. "DOM4_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM4_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 15. "DOM3_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 13.--14. "DOM3_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 12. "DOM3_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" newline bitfld.long 0x0 11. "DOM2_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 9.--10. "DOM2_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM2_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 7. "DOM1_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 5.--6. "DOM1_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" newline bitfld.long 0x0 4. "DOM1_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 3. "DOM0_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 1.--2. "DOM0_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM0_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" repeat.end repeat 16. (list 0x20 0x21 0x22 0x23 0x24 0x25 0x26 0x27 0x28 0x29 0x2A 0x2B 0x2C 0x2D 0x2E 0x2F )(list 0x680 0x6B4 0x6E8 0x71C 0x750 0x784 0x7B8 0x7EC 0x820 0x854 0x888 0x8BC 0x8F0 0x924 0x958 0x98C ) group.long ($2+0x2400)++0x3 line.long 0x0 "DOM_PER0_$1,Domain Permission Control. It can be only configured by resource manager and domain owner." bitfld.long 0x0 31. "DOM7_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 29.--30. "DOM7_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 28. "DOM7_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 27. "DOM6_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 25.--26. "DOM6_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" newline bitfld.long 0x0 24. "DOM6_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 23. "DOM5_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 21.--22. "DOM5_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 20. "DOM5_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 19. "DOM4_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" newline bitfld.long 0x0 17.--18. "DOM4_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM4_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 15. "DOM3_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 13.--14. "DOM3_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 12. "DOM3_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" newline bitfld.long 0x0 11. "DOM2_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 9.--10. "DOM2_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM2_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 7. "DOM1_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 5.--6. "DOM1_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" newline bitfld.long 0x0 4. "DOM1_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 3. "DOM0_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 1.--2. "DOM0_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM0_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" repeat.end repeat 16. (list 0x30 0x31 0x32 0x33 0x34 0x35 0x36 0x37 0x38 0x39 0x3A 0x3B 0x3C 0x3D 0x3E 0x3F )(list 0x9C0 0x9F4 0xA28 0xA5C 0xA90 0xAC4 0xAF8 0xB2C 0xB60 0xB94 0xBC8 0xBFC 0xC30 0xC64 0xC98 0xCCC ) group.long ($2+0x2400)++0x3 line.long 0x0 "DOM_PER0_$1,Domain Permission Control. It can be only configured by resource manager and domain owner." bitfld.long 0x0 31. "DOM7_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 29.--30. "DOM7_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 28. "DOM7_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 27. "DOM6_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 25.--26. "DOM6_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" newline bitfld.long 0x0 24. "DOM6_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 23. "DOM5_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 21.--22. "DOM5_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 20. "DOM5_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 19. "DOM4_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" newline bitfld.long 0x0 17.--18. "DOM4_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM4_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 15. "DOM3_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 13.--14. "DOM3_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 12. "DOM3_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" newline bitfld.long 0x0 11. "DOM2_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 9.--10. "DOM2_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM2_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 7. "DOM1_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 5.--6. "DOM1_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" newline bitfld.long 0x0 4. "DOM1_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 3. "DOM0_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 1.--2. "DOM0_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM0_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" repeat.end repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x34 0x68 0x9C 0xD0 0x104 0x138 0x16C 0x1A0 0x1D4 0x208 0x23C 0x270 0x2A4 0x2D8 0x30C ) group.long ($2+0x2404)++0x3 line.long 0x0 "DOM_PER1_$1,Domain Permission Control. It can be only configured by resource manager and domain owner." bitfld.long 0x0 31. "DOM15_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 29.--30. "DOM15_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 28. "DOM15_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 27. "DOM14_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 25.--26. "DOM14_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" newline bitfld.long 0x0 24. "DOM14_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 23. "DOM13_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 21.--22. "DOM13_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 20. "DOM13_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 19. "DOM12_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" newline bitfld.long 0x0 17.--18. "DOM12_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM12_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 15. "DOM11_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 13.--14. "DOM11_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 12. "DOM11_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" newline bitfld.long 0x0 11. "DOM10_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 9.--10. "DOM10_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM10_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 7. "DOM9_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 5.--6. "DOM9_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" newline bitfld.long 0x0 4. "DOM9_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 3. "DOM8_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 1.--2. "DOM8_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM8_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" repeat.end repeat 16. (list 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1A 0x1B 0x1C 0x1D 0x1E 0x1F )(list 0x340 0x374 0x3A8 0x3DC 0x410 0x444 0x478 0x4AC 0x4E0 0x514 0x548 0x57C 0x5B0 0x5E4 0x618 0x64C ) group.long ($2+0x2404)++0x3 line.long 0x0 "DOM_PER1_$1,Domain Permission Control. It can be only configured by resource manager and domain owner." bitfld.long 0x0 31. "DOM15_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 29.--30. "DOM15_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 28. "DOM15_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 27. "DOM14_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 25.--26. "DOM14_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" newline bitfld.long 0x0 24. "DOM14_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 23. "DOM13_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 21.--22. "DOM13_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 20. "DOM13_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 19. "DOM12_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" newline bitfld.long 0x0 17.--18. "DOM12_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM12_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 15. "DOM11_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 13.--14. "DOM11_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 12. "DOM11_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" newline bitfld.long 0x0 11. "DOM10_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 9.--10. "DOM10_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM10_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 7. "DOM9_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 5.--6. "DOM9_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" newline bitfld.long 0x0 4. "DOM9_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 3. "DOM8_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 1.--2. "DOM8_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM8_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" repeat.end repeat 16. (list 0x20 0x21 0x22 0x23 0x24 0x25 0x26 0x27 0x28 0x29 0x2A 0x2B 0x2C 0x2D 0x2E 0x2F )(list 0x680 0x6B4 0x6E8 0x71C 0x750 0x784 0x7B8 0x7EC 0x820 0x854 0x888 0x8BC 0x8F0 0x924 0x958 0x98C ) group.long ($2+0x2404)++0x3 line.long 0x0 "DOM_PER1_$1,Domain Permission Control. It can be only configured by resource manager and domain owner." bitfld.long 0x0 31. "DOM15_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 29.--30. "DOM15_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 28. "DOM15_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 27. "DOM14_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 25.--26. "DOM14_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" newline bitfld.long 0x0 24. "DOM14_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 23. "DOM13_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 21.--22. "DOM13_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 20. "DOM13_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 19. "DOM12_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" newline bitfld.long 0x0 17.--18. "DOM12_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM12_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 15. "DOM11_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 13.--14. "DOM11_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 12. "DOM11_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" newline bitfld.long 0x0 11. "DOM10_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 9.--10. "DOM10_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM10_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 7. "DOM9_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 5.--6. "DOM9_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" newline bitfld.long 0x0 4. "DOM9_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 3. "DOM8_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 1.--2. "DOM8_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM8_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" repeat.end repeat 16. (list 0x30 0x31 0x32 0x33 0x34 0x35 0x36 0x37 0x38 0x39 0x3A 0x3B 0x3C 0x3D 0x3E 0x3F )(list 0x9C0 0x9F4 0xA28 0xA5C 0xA90 0xAC4 0xAF8 0xB2C 0xB60 0xB94 0xBC8 0xBFC 0xC30 0xC64 0xC98 0xCCC ) group.long ($2+0x2404)++0x3 line.long 0x0 "DOM_PER1_$1,Domain Permission Control. It can be only configured by resource manager and domain owner." bitfld.long 0x0 31. "DOM15_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 29.--30. "DOM15_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 28. "DOM15_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 27. "DOM14_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 25.--26. "DOM14_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" newline bitfld.long 0x0 24. "DOM14_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 23. "DOM13_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 21.--22. "DOM13_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 20. "DOM13_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 19. "DOM12_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" newline bitfld.long 0x0 17.--18. "DOM12_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM12_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 15. "DOM11_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 13.--14. "DOM11_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 12. "DOM11_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" newline bitfld.long 0x0 11. "DOM10_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 9.--10. "DOM10_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM10_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 7. "DOM9_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 5.--6. "DOM9_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" newline bitfld.long 0x0 4. "DOM9_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 3. "DOM8_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 1.--2. "DOM8_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM8_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" repeat.end repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x34 0x68 0x9C 0xD0 0x104 0x138 0x16C 0x1A0 0x1D4 0x208 0x23C 0x270 0x2A4 0x2D8 0x30C ) group.long ($2+0x2408)++0x3 line.long 0x0 "SEC_PER0_$1,This register is only used for resource manager to control secure access permission." bitfld.long 0x0 31. "DOM3_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM3_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM3_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM3_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM2_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM2_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM2_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM2_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM1_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM1_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM1_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM1_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM0_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM0_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM0_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM0_SEC_EN,Domain secure permission control enable" "0,1" repeat.end repeat 16. (list 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1A 0x1B 0x1C 0x1D 0x1E 0x1F )(list 0x340 0x374 0x3A8 0x3DC 0x410 0x444 0x478 0x4AC 0x4E0 0x514 0x548 0x57C 0x5B0 0x5E4 0x618 0x64C ) group.long ($2+0x2408)++0x3 line.long 0x0 "SEC_PER0_$1,This register is only used for resource manager to control secure access permission." bitfld.long 0x0 31. "DOM3_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM3_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM3_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM3_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM2_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM2_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM2_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM2_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM1_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM1_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM1_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM1_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM0_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM0_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM0_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM0_SEC_EN,Domain secure permission control enable" "0,1" repeat.end repeat 16. (list 0x20 0x21 0x22 0x23 0x24 0x25 0x26 0x27 0x28 0x29 0x2A 0x2B 0x2C 0x2D 0x2E 0x2F )(list 0x680 0x6B4 0x6E8 0x71C 0x750 0x784 0x7B8 0x7EC 0x820 0x854 0x888 0x8BC 0x8F0 0x924 0x958 0x98C ) group.long ($2+0x2408)++0x3 line.long 0x0 "SEC_PER0_$1,This register is only used for resource manager to control secure access permission." bitfld.long 0x0 31. "DOM3_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM3_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM3_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM3_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM2_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM2_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM2_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM2_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM1_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM1_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM1_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM1_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM0_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM0_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM0_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM0_SEC_EN,Domain secure permission control enable" "0,1" repeat.end repeat 16. (list 0x30 0x31 0x32 0x33 0x34 0x35 0x36 0x37 0x38 0x39 0x3A 0x3B 0x3C 0x3D 0x3E 0x3F )(list 0x9C0 0x9F4 0xA28 0xA5C 0xA90 0xAC4 0xAF8 0xB2C 0xB60 0xB94 0xBC8 0xBFC 0xC30 0xC64 0xC98 0xCCC ) group.long ($2+0x2408)++0x3 line.long 0x0 "SEC_PER0_$1,This register is only used for resource manager to control secure access permission." bitfld.long 0x0 31. "DOM3_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM3_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM3_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM3_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM2_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM2_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM2_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM2_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM1_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM1_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM1_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM1_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM0_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM0_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM0_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM0_SEC_EN,Domain secure permission control enable" "0,1" repeat.end repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x34 0x68 0x9C 0xD0 0x104 0x138 0x16C 0x1A0 0x1D4 0x208 0x23C 0x270 0x2A4 0x2D8 0x30C ) group.long ($2+0x240C)++0x3 line.long 0x0 "SEC_PER1_$1,This register is only used for resource manager to control secure access permission." bitfld.long 0x0 31. "DOM7_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM7_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM7_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM7_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM6_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM6_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM6_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM6_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM5_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM5_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM5_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM5_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM4_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM4_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM4_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM4_SEC_EN,Domain secure permission control enable" "0,1" repeat.end repeat 16. (list 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1A 0x1B 0x1C 0x1D 0x1E 0x1F )(list 0x340 0x374 0x3A8 0x3DC 0x410 0x444 0x478 0x4AC 0x4E0 0x514 0x548 0x57C 0x5B0 0x5E4 0x618 0x64C ) group.long ($2+0x240C)++0x3 line.long 0x0 "SEC_PER1_$1,This register is only used for resource manager to control secure access permission." bitfld.long 0x0 31. "DOM7_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM7_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM7_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM7_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM6_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM6_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM6_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM6_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM5_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM5_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM5_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM5_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM4_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM4_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM4_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM4_SEC_EN,Domain secure permission control enable" "0,1" repeat.end repeat 16. (list 0x20 0x21 0x22 0x23 0x24 0x25 0x26 0x27 0x28 0x29 0x2A 0x2B 0x2C 0x2D 0x2E 0x2F )(list 0x680 0x6B4 0x6E8 0x71C 0x750 0x784 0x7B8 0x7EC 0x820 0x854 0x888 0x8BC 0x8F0 0x924 0x958 0x98C ) group.long ($2+0x240C)++0x3 line.long 0x0 "SEC_PER1_$1,This register is only used for resource manager to control secure access permission." bitfld.long 0x0 31. "DOM7_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM7_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM7_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM7_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM6_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM6_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM6_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM6_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM5_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM5_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM5_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM5_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM4_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM4_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM4_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM4_SEC_EN,Domain secure permission control enable" "0,1" repeat.end repeat 16. (list 0x30 0x31 0x32 0x33 0x34 0x35 0x36 0x37 0x38 0x39 0x3A 0x3B 0x3C 0x3D 0x3E 0x3F )(list 0x9C0 0x9F4 0xA28 0xA5C 0xA90 0xAC4 0xAF8 0xB2C 0xB60 0xB94 0xBC8 0xBFC 0xC30 0xC64 0xC98 0xCCC ) group.long ($2+0x240C)++0x3 line.long 0x0 "SEC_PER1_$1,This register is only used for resource manager to control secure access permission." bitfld.long 0x0 31. "DOM7_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM7_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM7_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM7_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM6_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM6_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM6_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM6_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM5_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM5_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM5_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM5_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM4_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM4_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM4_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM4_SEC_EN,Domain secure permission control enable" "0,1" repeat.end repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x34 0x68 0x9C 0xD0 0x104 0x138 0x16C 0x1A0 0x1D4 0x208 0x23C 0x270 0x2A4 0x2D8 0x30C ) group.long ($2+0x2410)++0x3 line.long 0x0 "SEC_PER2_$1,This register is only used for resource manager to control secure access permission." bitfld.long 0x0 31. "DOM11_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM11_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM11_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM11_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM10_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM10_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM10_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM10_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM9_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM9_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM9_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM9_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM8_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM8_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM8_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM8_SEC_EN,Domain secure permission control enable" "0,1" repeat.end repeat 16. (list 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1A 0x1B 0x1C 0x1D 0x1E 0x1F )(list 0x340 0x374 0x3A8 0x3DC 0x410 0x444 0x478 0x4AC 0x4E0 0x514 0x548 0x57C 0x5B0 0x5E4 0x618 0x64C ) group.long ($2+0x2410)++0x3 line.long 0x0 "SEC_PER2_$1,This register is only used for resource manager to control secure access permission." bitfld.long 0x0 31. "DOM11_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM11_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM11_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM11_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM10_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM10_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM10_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM10_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM9_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM9_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM9_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM9_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM8_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM8_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM8_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM8_SEC_EN,Domain secure permission control enable" "0,1" repeat.end repeat 16. (list 0x20 0x21 0x22 0x23 0x24 0x25 0x26 0x27 0x28 0x29 0x2A 0x2B 0x2C 0x2D 0x2E 0x2F )(list 0x680 0x6B4 0x6E8 0x71C 0x750 0x784 0x7B8 0x7EC 0x820 0x854 0x888 0x8BC 0x8F0 0x924 0x958 0x98C ) group.long ($2+0x2410)++0x3 line.long 0x0 "SEC_PER2_$1,This register is only used for resource manager to control secure access permission." bitfld.long 0x0 31. "DOM11_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM11_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM11_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM11_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM10_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM10_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM10_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM10_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM9_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM9_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM9_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM9_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM8_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM8_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM8_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM8_SEC_EN,Domain secure permission control enable" "0,1" repeat.end repeat 16. (list 0x30 0x31 0x32 0x33 0x34 0x35 0x36 0x37 0x38 0x39 0x3A 0x3B 0x3C 0x3D 0x3E 0x3F )(list 0x9C0 0x9F4 0xA28 0xA5C 0xA90 0xAC4 0xAF8 0xB2C 0xB60 0xB94 0xBC8 0xBFC 0xC30 0xC64 0xC98 0xCCC ) group.long ($2+0x2410)++0x3 line.long 0x0 "SEC_PER2_$1,This register is only used for resource manager to control secure access permission." bitfld.long 0x0 31. "DOM11_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM11_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM11_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM11_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM10_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM10_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM10_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM10_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM9_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM9_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM9_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM9_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM8_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM8_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM8_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM8_SEC_EN,Domain secure permission control enable" "0,1" repeat.end repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x34 0x68 0x9C 0xD0 0x104 0x138 0x16C 0x1A0 0x1D4 0x208 0x23C 0x270 0x2A4 0x2D8 0x30C ) group.long ($2+0x2414)++0x3 line.long 0x0 "SEC_PER3_$1,This register is only used for resource manager to control secure access permission." bitfld.long 0x0 31. "DOM15_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM15_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM15_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM15_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM14_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM14_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM14_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM14_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM13_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM13_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM13_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM13_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM12_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM12_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM12_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM12_SEC_EN,Domain secure permission control enable" "0,1" repeat.end repeat 16. (list 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1A 0x1B 0x1C 0x1D 0x1E 0x1F )(list 0x340 0x374 0x3A8 0x3DC 0x410 0x444 0x478 0x4AC 0x4E0 0x514 0x548 0x57C 0x5B0 0x5E4 0x618 0x64C ) group.long ($2+0x2414)++0x3 line.long 0x0 "SEC_PER3_$1,This register is only used for resource manager to control secure access permission." bitfld.long 0x0 31. "DOM15_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM15_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM15_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM15_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM14_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM14_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM14_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM14_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM13_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM13_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM13_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM13_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM12_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM12_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM12_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM12_SEC_EN,Domain secure permission control enable" "0,1" repeat.end repeat 16. (list 0x20 0x21 0x22 0x23 0x24 0x25 0x26 0x27 0x28 0x29 0x2A 0x2B 0x2C 0x2D 0x2E 0x2F )(list 0x680 0x6B4 0x6E8 0x71C 0x750 0x784 0x7B8 0x7EC 0x820 0x854 0x888 0x8BC 0x8F0 0x924 0x958 0x98C ) group.long ($2+0x2414)++0x3 line.long 0x0 "SEC_PER3_$1,This register is only used for resource manager to control secure access permission." bitfld.long 0x0 31. "DOM15_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM15_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM15_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM15_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM14_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM14_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM14_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM14_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM13_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM13_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM13_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM13_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM12_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM12_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM12_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM12_SEC_EN,Domain secure permission control enable" "0,1" repeat.end repeat 16. (list 0x30 0x31 0x32 0x33 0x34 0x35 0x36 0x37 0x38 0x39 0x3A 0x3B 0x3C 0x3D 0x3E 0x3F )(list 0x9C0 0x9F4 0xA28 0xA5C 0xA90 0xAC4 0xAF8 0xB2C 0xB60 0xB94 0xBC8 0xBFC 0xC30 0xC64 0xC98 0xCCC ) group.long ($2+0x2414)++0x3 line.long 0x0 "SEC_PER3_$1,This register is only used for resource manager to control secure access permission." bitfld.long 0x0 31. "DOM15_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM15_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM15_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM15_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM14_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM14_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM14_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM14_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM13_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM13_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM13_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM13_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM12_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM12_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM12_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM12_SEC_EN,Domain secure permission control enable" "0,1" repeat.end repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x34 0x68 0x9C 0xD0 0x104 0x138 0x16C 0x1A0 0x1D4 0x208 0x23C 0x270 0x2A4 0x2D8 0x30C ) group.long ($2+0x2418)++0x3 line.long 0x0 "PRI_PER0_$1,This register is only used for resource manager to control privileged access permission." bitfld.long 0x0 31. "DOM3_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM3_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM3_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM3_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM2_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM2_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM2_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM2_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM1_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM1_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM1_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM1_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM0_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM0_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM0_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM0_PRI_EN,Domain privileged permission control enable" "0,1" repeat.end repeat 16. (list 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1A 0x1B 0x1C 0x1D 0x1E 0x1F )(list 0x340 0x374 0x3A8 0x3DC 0x410 0x444 0x478 0x4AC 0x4E0 0x514 0x548 0x57C 0x5B0 0x5E4 0x618 0x64C ) group.long ($2+0x2418)++0x3 line.long 0x0 "PRI_PER0_$1,This register is only used for resource manager to control privileged access permission." bitfld.long 0x0 31. "DOM3_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM3_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM3_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM3_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM2_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM2_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM2_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM2_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM1_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM1_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM1_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM1_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM0_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM0_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM0_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM0_PRI_EN,Domain privileged permission control enable" "0,1" repeat.end repeat 16. (list 0x20 0x21 0x22 0x23 0x24 0x25 0x26 0x27 0x28 0x29 0x2A 0x2B 0x2C 0x2D 0x2E 0x2F )(list 0x680 0x6B4 0x6E8 0x71C 0x750 0x784 0x7B8 0x7EC 0x820 0x854 0x888 0x8BC 0x8F0 0x924 0x958 0x98C ) group.long ($2+0x2418)++0x3 line.long 0x0 "PRI_PER0_$1,This register is only used for resource manager to control privileged access permission." bitfld.long 0x0 31. "DOM3_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM3_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM3_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM3_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM2_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM2_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM2_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM2_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM1_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM1_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM1_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM1_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM0_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM0_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM0_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM0_PRI_EN,Domain privileged permission control enable" "0,1" repeat.end repeat 16. (list 0x30 0x31 0x32 0x33 0x34 0x35 0x36 0x37 0x38 0x39 0x3A 0x3B 0x3C 0x3D 0x3E 0x3F )(list 0x9C0 0x9F4 0xA28 0xA5C 0xA90 0xAC4 0xAF8 0xB2C 0xB60 0xB94 0xBC8 0xBFC 0xC30 0xC64 0xC98 0xCCC ) group.long ($2+0x2418)++0x3 line.long 0x0 "PRI_PER0_$1,This register is only used for resource manager to control privileged access permission." bitfld.long 0x0 31. "DOM3_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM3_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM3_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM3_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM2_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM2_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM2_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM2_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM1_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM1_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM1_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM1_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM0_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM0_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM0_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM0_PRI_EN,Domain privileged permission control enable" "0,1" repeat.end repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x34 0x68 0x9C 0xD0 0x104 0x138 0x16C 0x1A0 0x1D4 0x208 0x23C 0x270 0x2A4 0x2D8 0x30C ) group.long ($2+0x241C)++0x3 line.long 0x0 "PRI_PER1_$1,This register is only used for resource manager to control privileged access permission." bitfld.long 0x0 31. "DOM7_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM7_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM7_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM7_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM6_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM6_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM6_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM6_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM5_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM5_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM5_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM5_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM4_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM4_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM4_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM4_PRI_EN,Domain privileged permission control enable" "0,1" repeat.end repeat 16. (list 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1A 0x1B 0x1C 0x1D 0x1E 0x1F )(list 0x340 0x374 0x3A8 0x3DC 0x410 0x444 0x478 0x4AC 0x4E0 0x514 0x548 0x57C 0x5B0 0x5E4 0x618 0x64C ) group.long ($2+0x241C)++0x3 line.long 0x0 "PRI_PER1_$1,This register is only used for resource manager to control privileged access permission." bitfld.long 0x0 31. "DOM7_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM7_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM7_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM7_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM6_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM6_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM6_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM6_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM5_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM5_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM5_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM5_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM4_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM4_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM4_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM4_PRI_EN,Domain privileged permission control enable" "0,1" repeat.end repeat 16. (list 0x20 0x21 0x22 0x23 0x24 0x25 0x26 0x27 0x28 0x29 0x2A 0x2B 0x2C 0x2D 0x2E 0x2F )(list 0x680 0x6B4 0x6E8 0x71C 0x750 0x784 0x7B8 0x7EC 0x820 0x854 0x888 0x8BC 0x8F0 0x924 0x958 0x98C ) group.long ($2+0x241C)++0x3 line.long 0x0 "PRI_PER1_$1,This register is only used for resource manager to control privileged access permission." bitfld.long 0x0 31. "DOM7_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM7_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM7_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM7_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM6_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM6_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM6_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM6_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM5_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM5_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM5_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM5_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM4_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM4_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM4_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM4_PRI_EN,Domain privileged permission control enable" "0,1" repeat.end repeat 16. (list 0x30 0x31 0x32 0x33 0x34 0x35 0x36 0x37 0x38 0x39 0x3A 0x3B 0x3C 0x3D 0x3E 0x3F )(list 0x9C0 0x9F4 0xA28 0xA5C 0xA90 0xAC4 0xAF8 0xB2C 0xB60 0xB94 0xBC8 0xBFC 0xC30 0xC64 0xC98 0xCCC ) group.long ($2+0x241C)++0x3 line.long 0x0 "PRI_PER1_$1,This register is only used for resource manager to control privileged access permission." bitfld.long 0x0 31. "DOM7_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM7_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM7_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM7_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM6_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM6_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM6_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM6_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM5_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM5_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM5_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM5_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM4_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM4_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM4_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM4_PRI_EN,Domain privileged permission control enable" "0,1" repeat.end repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x34 0x68 0x9C 0xD0 0x104 0x138 0x16C 0x1A0 0x1D4 0x208 0x23C 0x270 0x2A4 0x2D8 0x30C ) group.long ($2+0x2420)++0x3 line.long 0x0 "PRI_PER2_$1,This register is only used for resource manager to control privileged access permission." bitfld.long 0x0 31. "DOM11_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM11_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM11_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM11_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM10_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM10_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM10_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM10_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM9_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM9_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM9_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM9_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM8_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM8_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM8_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM8_PRI_EN,Domain privileged permission control enable" "0,1" repeat.end repeat 16. (list 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1A 0x1B 0x1C 0x1D 0x1E 0x1F )(list 0x340 0x374 0x3A8 0x3DC 0x410 0x444 0x478 0x4AC 0x4E0 0x514 0x548 0x57C 0x5B0 0x5E4 0x618 0x64C ) group.long ($2+0x2420)++0x3 line.long 0x0 "PRI_PER2_$1,This register is only used for resource manager to control privileged access permission." bitfld.long 0x0 31. "DOM11_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM11_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM11_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM11_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM10_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM10_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM10_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM10_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM9_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM9_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM9_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM9_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM8_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM8_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM8_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM8_PRI_EN,Domain privileged permission control enable" "0,1" repeat.end repeat 16. (list 0x20 0x21 0x22 0x23 0x24 0x25 0x26 0x27 0x28 0x29 0x2A 0x2B 0x2C 0x2D 0x2E 0x2F )(list 0x680 0x6B4 0x6E8 0x71C 0x750 0x784 0x7B8 0x7EC 0x820 0x854 0x888 0x8BC 0x8F0 0x924 0x958 0x98C ) group.long ($2+0x2420)++0x3 line.long 0x0 "PRI_PER2_$1,This register is only used for resource manager to control privileged access permission." bitfld.long 0x0 31. "DOM11_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM11_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM11_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM11_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM10_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM10_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM10_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM10_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM9_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM9_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM9_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM9_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM8_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM8_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM8_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM8_PRI_EN,Domain privileged permission control enable" "0,1" repeat.end repeat 16. (list 0x30 0x31 0x32 0x33 0x34 0x35 0x36 0x37 0x38 0x39 0x3A 0x3B 0x3C 0x3D 0x3E 0x3F )(list 0x9C0 0x9F4 0xA28 0xA5C 0xA90 0xAC4 0xAF8 0xB2C 0xB60 0xB94 0xBC8 0xBFC 0xC30 0xC64 0xC98 0xCCC ) group.long ($2+0x2420)++0x3 line.long 0x0 "PRI_PER2_$1,This register is only used for resource manager to control privileged access permission." bitfld.long 0x0 31. "DOM11_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM11_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM11_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM11_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM10_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM10_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM10_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM10_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM9_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM9_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM9_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM9_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM8_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM8_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM8_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM8_PRI_EN,Domain privileged permission control enable" "0,1" repeat.end repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x34 0x68 0x9C 0xD0 0x104 0x138 0x16C 0x1A0 0x1D4 0x208 0x23C 0x270 0x2A4 0x2D8 0x30C ) group.long ($2+0x2424)++0x3 line.long 0x0 "PRI_PER3_$1,This register is only used for resource manager to control privileged access permission." bitfld.long 0x0 31. "DOM15_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM15_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM15_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM15_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM14_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM14_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM14_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM14_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM13_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM13_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM13_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM13_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM12_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM12_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM12_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM12_PRI_EN,Domain privileged permission control enable" "0,1" repeat.end repeat 16. (list 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1A 0x1B 0x1C 0x1D 0x1E 0x1F )(list 0x340 0x374 0x3A8 0x3DC 0x410 0x444 0x478 0x4AC 0x4E0 0x514 0x548 0x57C 0x5B0 0x5E4 0x618 0x64C ) group.long ($2+0x2424)++0x3 line.long 0x0 "PRI_PER3_$1,This register is only used for resource manager to control privileged access permission." bitfld.long 0x0 31. "DOM15_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM15_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM15_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM15_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM14_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM14_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM14_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM14_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM13_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM13_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM13_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM13_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM12_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM12_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM12_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM12_PRI_EN,Domain privileged permission control enable" "0,1" repeat.end repeat 16. (list 0x20 0x21 0x22 0x23 0x24 0x25 0x26 0x27 0x28 0x29 0x2A 0x2B 0x2C 0x2D 0x2E 0x2F )(list 0x680 0x6B4 0x6E8 0x71C 0x750 0x784 0x7B8 0x7EC 0x820 0x854 0x888 0x8BC 0x8F0 0x924 0x958 0x98C ) group.long ($2+0x2424)++0x3 line.long 0x0 "PRI_PER3_$1,This register is only used for resource manager to control privileged access permission." bitfld.long 0x0 31. "DOM15_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM15_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM15_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM15_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM14_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM14_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM14_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM14_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM13_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM13_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM13_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM13_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM12_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM12_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM12_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM12_PRI_EN,Domain privileged permission control enable" "0,1" repeat.end repeat 16. (list 0x30 0x31 0x32 0x33 0x34 0x35 0x36 0x37 0x38 0x39 0x3A 0x3B 0x3C 0x3D 0x3E 0x3F )(list 0x9C0 0x9F4 0xA28 0xA5C 0xA90 0xAC4 0xAF8 0xB2C 0xB60 0xB94 0xBC8 0xBFC 0xC30 0xC64 0xC98 0xCCC ) group.long ($2+0x2424)++0x3 line.long 0x0 "PRI_PER3_$1,This register is only used for resource manager to control privileged access permission." bitfld.long 0x0 31. "DOM15_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM15_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM15_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM15_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM14_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM14_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM14_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM14_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM13_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM13_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM13_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM13_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM12_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM12_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM12_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM12_PRI_EN,Domain privileged permission control enable" "0,1" repeat.end repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x34 0x68 0x9C 0xD0 0x104 0x138 0x16C 0x1A0 0x1D4 0x208 0x23C 0x270 0x2A4 0x2D8 0x30C ) group.long ($2+0x2428)++0x3 line.long 0x0 "DOM_SEC_PER_$1,This register is only used for domain master to control secure access permission. When the domain master write this register. it only changes the secure permission for itself. When the domain master read this register. it gets permission.." bitfld.long 0x0 7. "DOM_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" newline bitfld.long 0x0 0. "DOM_SEC_EN,Domain secure permission control enable" "0,1" repeat.end repeat 16. (list 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1A 0x1B 0x1C 0x1D 0x1E 0x1F )(list 0x340 0x374 0x3A8 0x3DC 0x410 0x444 0x478 0x4AC 0x4E0 0x514 0x548 0x57C 0x5B0 0x5E4 0x618 0x64C ) group.long ($2+0x2428)++0x3 line.long 0x0 "DOM_SEC_PER_$1,This register is only used for domain master to control secure access permission. When the domain master write this register. it only changes the secure permission for itself. When the domain master read this register. it gets permission.." bitfld.long 0x0 7. "DOM_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" newline bitfld.long 0x0 0. "DOM_SEC_EN,Domain secure permission control enable" "0,1" repeat.end repeat 16. (list 0x20 0x21 0x22 0x23 0x24 0x25 0x26 0x27 0x28 0x29 0x2A 0x2B 0x2C 0x2D 0x2E 0x2F )(list 0x680 0x6B4 0x6E8 0x71C 0x750 0x784 0x7B8 0x7EC 0x820 0x854 0x888 0x8BC 0x8F0 0x924 0x958 0x98C ) group.long ($2+0x2428)++0x3 line.long 0x0 "DOM_SEC_PER_$1,This register is only used for domain master to control secure access permission. When the domain master write this register. it only changes the secure permission for itself. When the domain master read this register. it gets permission.." bitfld.long 0x0 7. "DOM_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" newline bitfld.long 0x0 0. "DOM_SEC_EN,Domain secure permission control enable" "0,1" repeat.end repeat 16. (list 0x30 0x31 0x32 0x33 0x34 0x35 0x36 0x37 0x38 0x39 0x3A 0x3B 0x3C 0x3D 0x3E 0x3F )(list 0x9C0 0x9F4 0xA28 0xA5C 0xA90 0xAC4 0xAF8 0xB2C 0xB60 0xB94 0xBC8 0xBFC 0xC30 0xC64 0xC98 0xCCC ) group.long ($2+0x2428)++0x3 line.long 0x0 "DOM_SEC_PER_$1,This register is only used for domain master to control secure access permission. When the domain master write this register. it only changes the secure permission for itself. When the domain master read this register. it gets permission.." bitfld.long 0x0 7. "DOM_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" newline bitfld.long 0x0 0. "DOM_SEC_EN,Domain secure permission control enable" "0,1" repeat.end repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x34 0x68 0x9C 0xD0 0x104 0x138 0x16C 0x1A0 0x1D4 0x208 0x23C 0x270 0x2A4 0x2D8 0x30C ) group.long ($2+0x242C)++0x3 line.long 0x0 "DOM_PRI_PER_$1,This register is only used for domain master to control secure access permission. When the domain master write this register. it only changes the secure permission for itself. When the domain master read this register. it gets permission.." bitfld.long 0x0 7. "DOM_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" newline bitfld.long 0x0 0. "DOM_PRI_EN,Domain privileged permission control enable" "0,1" repeat.end repeat 16. (list 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1A 0x1B 0x1C 0x1D 0x1E 0x1F )(list 0x340 0x374 0x3A8 0x3DC 0x410 0x444 0x478 0x4AC 0x4E0 0x514 0x548 0x57C 0x5B0 0x5E4 0x618 0x64C ) group.long ($2+0x242C)++0x3 line.long 0x0 "DOM_PRI_PER_$1,This register is only used for domain master to control secure access permission. When the domain master write this register. it only changes the secure permission for itself. When the domain master read this register. it gets permission.." bitfld.long 0x0 7. "DOM_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" newline bitfld.long 0x0 0. "DOM_PRI_EN,Domain privileged permission control enable" "0,1" repeat.end repeat 16. (list 0x20 0x21 0x22 0x23 0x24 0x25 0x26 0x27 0x28 0x29 0x2A 0x2B 0x2C 0x2D 0x2E 0x2F )(list 0x680 0x6B4 0x6E8 0x71C 0x750 0x784 0x7B8 0x7EC 0x820 0x854 0x888 0x8BC 0x8F0 0x924 0x958 0x98C ) group.long ($2+0x242C)++0x3 line.long 0x0 "DOM_PRI_PER_$1,This register is only used for domain master to control secure access permission. When the domain master write this register. it only changes the secure permission for itself. When the domain master read this register. it gets permission.." bitfld.long 0x0 7. "DOM_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" newline bitfld.long 0x0 0. "DOM_PRI_EN,Domain privileged permission control enable" "0,1" repeat.end repeat 16. (list 0x30 0x31 0x32 0x33 0x34 0x35 0x36 0x37 0x38 0x39 0x3A 0x3B 0x3C 0x3D 0x3E 0x3F )(list 0x9C0 0x9F4 0xA28 0xA5C 0xA90 0xAC4 0xAF8 0xB2C 0xB60 0xB94 0xBC8 0xBFC 0xC30 0xC64 0xC98 0xCCC ) group.long ($2+0x242C)++0x3 line.long 0x0 "DOM_PRI_PER_$1,This register is only used for domain master to control secure access permission. When the domain master write this register. it only changes the secure permission for itself. When the domain master read this register. it gets permission.." bitfld.long 0x0 7. "DOM_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" newline bitfld.long 0x0 0. "DOM_PRI_EN,Domain privileged permission control enable" "0,1" repeat.end repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x34 0x68 0x9C 0xD0 0x104 0x138 0x16C 0x1A0 0x1D4 0x208 0x23C 0x270 0x2A4 0x2D8 0x30C ) group.long ($2+0x2430)++0x3 line.long 0x0 "DOM_ASSIGN_$1,Use to assign domain for accessing DOM_SEC_PER and DOM_PRI_PER register. Only resource manager. group manager and domain owner can access this register. For write. group manager must write its owen domain ID. otherwise write accessing will.." hexmask.long.byte 0x0 0.--3. 1. "DID,accessing DOM_SEC_PER and DOM_PRI_PER register" repeat.end repeat 16. (list 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1A 0x1B 0x1C 0x1D 0x1E 0x1F )(list 0x340 0x374 0x3A8 0x3DC 0x410 0x444 0x478 0x4AC 0x4E0 0x514 0x548 0x57C 0x5B0 0x5E4 0x618 0x64C ) group.long ($2+0x2430)++0x3 line.long 0x0 "DOM_ASSIGN_$1,Use to assign domain for accessing DOM_SEC_PER and DOM_PRI_PER register. Only resource manager. group manager and domain owner can access this register. For write. group manager must write its owen domain ID. otherwise write accessing will.." hexmask.long.byte 0x0 0.--3. 1. "DID,accessing DOM_SEC_PER and DOM_PRI_PER register" repeat.end repeat 16. (list 0x20 0x21 0x22 0x23 0x24 0x25 0x26 0x27 0x28 0x29 0x2A 0x2B 0x2C 0x2D 0x2E 0x2F )(list 0x680 0x6B4 0x6E8 0x71C 0x750 0x784 0x7B8 0x7EC 0x820 0x854 0x888 0x8BC 0x8F0 0x924 0x958 0x98C ) group.long ($2+0x2430)++0x3 line.long 0x0 "DOM_ASSIGN_$1,Use to assign domain for accessing DOM_SEC_PER and DOM_PRI_PER register. Only resource manager. group manager and domain owner can access this register. For write. group manager must write its owen domain ID. otherwise write accessing will.." hexmask.long.byte 0x0 0.--3. 1. "DID,accessing DOM_SEC_PER and DOM_PRI_PER register" repeat.end repeat 16. (list 0x30 0x31 0x32 0x33 0x34 0x35 0x36 0x37 0x38 0x39 0x3A 0x3B 0x3C 0x3D 0x3E 0x3F )(list 0x9C0 0x9F4 0xA28 0xA5C 0xA90 0xAC4 0xAF8 0xB2C 0xB60 0xB94 0xBC8 0xBFC 0xC30 0xC64 0xC98 0xCCC ) group.long ($2+0x2430)++0x3 line.long 0x0 "DOM_ASSIGN_$1,Use to assign domain for accessing DOM_SEC_PER and DOM_PRI_PER register. Only resource manager. group manager and domain owner can access this register. For write. group manager must write its owen domain ID. otherwise write accessing will.." hexmask.long.byte 0x0 0.--3. 1. "DID,accessing DOM_SEC_PER and DOM_PRI_PER register" repeat.end repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x38 0x70 0xA8 0xE0 0x118 0x150 0x188 0x1C0 0x1F8 0x230 0x268 0x2A0 0x2D8 0x310 0x348 ) group.long ($2+0x3100)++0x3 line.long 0x0 "RGN_DOM_$1,Assign domain for peripheral. It can be only configured by resource and group manager" bitfld.long 0x0 31. "LOCK,When this bit is set lock write for all the bits in the register." "0,1" bitfld.long 0x0 4. "SET,Set together with DID would change permission of this resource to following setting: 1) Domain access control enabled. 2) Read/Write allowed for the domain owner. 3) Read/Write not allowed for all the other domains. If this bit is not set only DID.." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Assign domain for peripheral" repeat.end repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x38 0x70 0xA8 0xE0 0x118 0x150 0x188 0x1C0 0x1F8 0x230 0x268 0x2A0 0x2D8 0x310 0x348 ) group.long ($2+0x3104)++0x3 line.long 0x0 "RGN_DOM_PER0_$1,Domain Permission Control. It can be only configured by resource manager and domain owner." bitfld.long 0x0 31. "DOM7_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 29.--30. "DOM7_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 28. "DOM7_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 27. "DOM6_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 25.--26. "DOM6_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" newline bitfld.long 0x0 24. "DOM6_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 23. "DOM5_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 21.--22. "DOM5_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 20. "DOM5_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 19. "DOM4_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" newline bitfld.long 0x0 17.--18. "DOM4_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM4_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 15. "DOM3_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 13.--14. "DOM3_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 12. "DOM3_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" newline bitfld.long 0x0 11. "DOM2_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 9.--10. "DOM2_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM2_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 7. "DOM1_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 5.--6. "DOM1_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" newline bitfld.long 0x0 4. "DOM1_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 3. "DOM0_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 1.--2. "DOM0_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM0_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" repeat.end repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x38 0x70 0xA8 0xE0 0x118 0x150 0x188 0x1C0 0x1F8 0x230 0x268 0x2A0 0x2D8 0x310 0x348 ) group.long ($2+0x3108)++0x3 line.long 0x0 "RGN_DOM_PER1_$1,Domain Permission Control. It can be only configured by resource manager and domain owner." bitfld.long 0x0 31. "DOM15_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 29.--30. "DOM15_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 28. "DOM15_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 27. "DOM14_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 25.--26. "DOM14_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" newline bitfld.long 0x0 24. "DOM14_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 23. "DOM13_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 21.--22. "DOM13_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 20. "DOM13_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 19. "DOM12_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" newline bitfld.long 0x0 17.--18. "DOM12_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM12_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 15. "DOM11_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 13.--14. "DOM11_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 12. "DOM11_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" newline bitfld.long 0x0 11. "DOM10_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 9.--10. "DOM10_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM10_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 7. "DOM9_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 5.--6. "DOM9_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" newline bitfld.long 0x0 4. "DOM9_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 3. "DOM8_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 1.--2. "DOM8_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM8_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" repeat.end repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x38 0x70 0xA8 0xE0 0x118 0x150 0x188 0x1C0 0x1F8 0x230 0x268 0x2A0 0x2D8 0x310 0x348 ) group.long ($2+0x310C)++0x3 line.long 0x0 "RGN_SEC_PER0_$1,This register is only used for resource manager to control secure access permission." bitfld.long 0x0 31. "DOM3_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM3_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM3_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM3_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM2_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM2_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM2_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM2_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM1_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM1_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM1_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM1_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM0_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM0_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM0_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM0_SEC_EN,Domain secure permission control enable" "0,1" repeat.end repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x38 0x70 0xA8 0xE0 0x118 0x150 0x188 0x1C0 0x1F8 0x230 0x268 0x2A0 0x2D8 0x310 0x348 ) group.long ($2+0x3110)++0x3 line.long 0x0 "RGN_SEC_PER1_$1,This register is only used for resource manager to control secure access permission." bitfld.long 0x0 31. "DOM7_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM7_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM7_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM7_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM6_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM6_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM6_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM6_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM5_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM5_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM5_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM5_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM4_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM4_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM4_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM4_SEC_EN,Domain secure permission control enable" "0,1" repeat.end repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x38 0x70 0xA8 0xE0 0x118 0x150 0x188 0x1C0 0x1F8 0x230 0x268 0x2A0 0x2D8 0x310 0x348 ) group.long ($2+0x3114)++0x3 line.long 0x0 "RGN_SEC_PER2_$1,This register is only used for resource manager to control secure access permission." bitfld.long 0x0 31. "DOM11_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM11_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM11_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM11_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM10_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM10_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM10_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM10_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM9_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM9_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM9_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM9_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM8_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM8_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM8_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM8_SEC_EN,Domain secure permission control enable" "0,1" repeat.end repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x38 0x70 0xA8 0xE0 0x118 0x150 0x188 0x1C0 0x1F8 0x230 0x268 0x2A0 0x2D8 0x310 0x348 ) group.long ($2+0x3118)++0x3 line.long 0x0 "RGN_SEC_PER3_$1,This register is only used for resource manager to control secure access permission." bitfld.long 0x0 31. "DOM15_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM15_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM15_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM15_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM14_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM14_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM14_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM14_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM13_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM13_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM13_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM13_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM12_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM12_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM12_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM12_SEC_EN,Domain secure permission control enable" "0,1" repeat.end repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x38 0x70 0xA8 0xE0 0x118 0x150 0x188 0x1C0 0x1F8 0x230 0x268 0x2A0 0x2D8 0x310 0x348 ) group.long ($2+0x311C)++0x3 line.long 0x0 "RGN_PRI_PER0_$1,This register is only used for resource manager to control privileged access permission." bitfld.long 0x0 31. "DOM3_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM3_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM3_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM3_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM2_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM2_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM2_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM2_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM1_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM1_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM1_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM1_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM0_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM0_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM0_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM0_PRI_EN,Domain privileged permission control enable" "0,1" repeat.end repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x38 0x70 0xA8 0xE0 0x118 0x150 0x188 0x1C0 0x1F8 0x230 0x268 0x2A0 0x2D8 0x310 0x348 ) group.long ($2+0x3120)++0x3 line.long 0x0 "RGN_PRI_PER1_$1,This register is only used for resource manager to control privileged access permission." bitfld.long 0x0 31. "DOM7_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM7_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM7_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM7_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM6_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM6_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM6_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM6_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM5_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM5_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM5_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM5_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM4_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM4_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM4_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM4_PRI_EN,Domain privileged permission control enable" "0,1" repeat.end repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x38 0x70 0xA8 0xE0 0x118 0x150 0x188 0x1C0 0x1F8 0x230 0x268 0x2A0 0x2D8 0x310 0x348 ) group.long ($2+0x3124)++0x3 line.long 0x0 "RGN_PRI_PER2_$1,This register is only used for resource manager to control privileged access permission." bitfld.long 0x0 31. "DOM11_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM11_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM11_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM11_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM10_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM10_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM10_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM10_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM9_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM9_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM9_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM9_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM8_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM8_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM8_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM8_PRI_EN,Domain privileged permission control enable" "0,1" repeat.end repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x38 0x70 0xA8 0xE0 0x118 0x150 0x188 0x1C0 0x1F8 0x230 0x268 0x2A0 0x2D8 0x310 0x348 ) group.long ($2+0x3128)++0x3 line.long 0x0 "RGN_PRI_PER3_$1,This register is only used for resource manager to control privileged access permission." bitfld.long 0x0 31. "DOM15_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM15_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM15_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM15_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM14_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM14_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM14_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM14_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM13_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM13_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM13_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM13_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM12_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM12_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM12_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM12_PRI_EN,Domain privileged permission control enable" "0,1" repeat.end repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x38 0x70 0xA8 0xE0 0x118 0x150 0x188 0x1C0 0x1F8 0x230 0x268 0x2A0 0x2D8 0x310 0x348 ) group.long ($2+0x312C)++0x3 line.long 0x0 "RGN_DOM_SEC_PER_$1,This register is only used for domain master to control secure access permission. When the domain master write this register. it only changes the secure permission for itself. When the domain master read this register. it gets.." bitfld.long 0x0 7. "DOM_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" newline bitfld.long 0x0 0. "DOM_SEC_EN,Domain secure permission control enable" "0,1" repeat.end repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x38 0x70 0xA8 0xE0 0x118 0x150 0x188 0x1C0 0x1F8 0x230 0x268 0x2A0 0x2D8 0x310 0x348 ) group.long ($2+0x3130)++0x3 line.long 0x0 "RGN_DOM_PRI_PER_$1,This register is only used for domain master to control secure access permission. When the domain master write this register. it only changes the secure permission for itself. When the domain master read this register. it gets.." bitfld.long 0x0 7. "DOM_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" newline bitfld.long 0x0 0. "DOM_PRI_EN,Domain privileged permission control enable" "0,1" repeat.end repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x38 0x70 0xA8 0xE0 0x118 0x150 0x188 0x1C0 0x1F8 0x230 0x268 0x2A0 0x2D8 0x310 0x348 ) group.long ($2+0x3134)++0x3 line.long 0x0 "RGN_DOM_ASSIGN_$1,Use to assign domain for accessing DOM_SEC_PER and DOM_PRI_PER register. Only resource manager. group manager and domain owner can access this register. For write. group manager must write its owen domain ID. otherwise write accessing.." hexmask.long.byte 0x0 0.--3. 1. "DID,accessing DOM_SEC_PER and DOM_PRI_PER register" repeat.end tree.end tree "RPC_AP_CLKGEN" base ad:0xF8800000 repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x4 0x8 0xC 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C ) group.long ($2)++0x3 line.long 0x0 "REGG0_DOM_$1,Assign domain for CKGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1A 0x1B 0x1C 0x1D 0x1E 0x1F )(list 0x40 0x44 0x48 0x4C 0x50 0x54 0x58 0x5C 0x60 0x64 0x68 0x6C 0x70 0x74 0x78 0x7C ) group.long ($2)++0x3 line.long 0x0 "REGG0_DOM_$1,Assign domain for CKGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x20 0x21 0x22 0x23 0x24 0x25 0x26 0x27 0x28 0x29 0x2A 0x2B 0x2C 0x2D 0x2E 0x2F )(list 0x80 0x84 0x88 0x8C 0x90 0x94 0x98 0x9C 0xA0 0xA4 0xA8 0xAC 0xB0 0xB4 0xB8 0xBC ) group.long ($2)++0x3 line.long 0x0 "REGG0_DOM_$1,Assign domain for CKGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x30 0x31 0x32 0x33 0x34 0x35 0x36 0x37 0x38 0x39 0x3A 0x3B 0x3C 0x3D 0x3E 0x3F )(list 0xC0 0xC4 0xC8 0xCC 0xD0 0xD4 0xD8 0xDC 0xE0 0xE4 0xE8 0xEC 0xF0 0xF4 0xF8 0xFC ) group.long ($2)++0x3 line.long 0x0 "REGG0_DOM_$1,Assign domain for CKGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x40 0x41 0x42 0x43 0x44 0x45 0x46 0x47 0x48 0x49 0x4A 0x4B 0x4C 0x4D 0x4E 0x4F )(list 0x100 0x104 0x108 0x10C 0x110 0x114 0x118 0x11C 0x120 0x124 0x128 0x12C 0x130 0x134 0x138 0x13C ) group.long ($2)++0x3 line.long 0x0 "REGG0_DOM_$1,Assign domain for CKGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x50 0x51 0x52 0x53 0x54 0x55 0x56 0x57 0x58 0x59 0x5A 0x5B 0x5C 0x5D 0x5E 0x5F )(list 0x140 0x144 0x148 0x14C 0x150 0x154 0x158 0x15C 0x160 0x164 0x168 0x16C 0x170 0x174 0x178 0x17C ) group.long ($2)++0x3 line.long 0x0 "REGG0_DOM_$1,Assign domain for CKGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x60 0x61 0x62 0x63 0x64 0x65 0x66 0x67 0x68 0x69 0x6A 0x6B 0x6C 0x6D 0x6E 0x6F )(list 0x180 0x184 0x188 0x18C 0x190 0x194 0x198 0x19C 0x1A0 0x1A4 0x1A8 0x1AC 0x1B0 0x1B4 0x1B8 0x1BC ) group.long ($2)++0x3 line.long 0x0 "REGG0_DOM_$1,Assign domain for CKGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x70 0x71 0x72 0x73 0x74 0x75 0x76 0x77 0x78 0x79 0x7A 0x7B 0x7C 0x7D 0x7E 0x7F )(list 0x1C0 0x1C4 0x1C8 0x1CC 0x1D0 0x1D4 0x1D8 0x1DC 0x1E0 0x1E4 0x1E8 0x1EC 0x1F0 0x1F4 0x1F8 0x1FC ) group.long ($2)++0x3 line.long 0x0 "REGG0_DOM_$1,Assign domain for CKGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x80 0x81 0x82 0x83 0x84 0x85 0x86 0x87 0x88 0x89 0x8A 0x8B 0x8C 0x8D 0x8E 0x8F )(list 0x200 0x204 0x208 0x20C 0x210 0x214 0x218 0x21C 0x220 0x224 0x228 0x22C 0x230 0x234 0x238 0x23C ) group.long ($2)++0x3 line.long 0x0 "REGG0_DOM_$1,Assign domain for CKGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x90 0x91 0x92 0x93 0x94 0x95 0x96 0x97 0x98 0x99 0x9A 0x9B 0x9C 0x9D 0x9E 0x9F )(list 0x240 0x244 0x248 0x24C 0x250 0x254 0x258 0x25C 0x260 0x264 0x268 0x26C 0x270 0x274 0x278 0x27C ) group.long ($2)++0x3 line.long 0x0 "REGG0_DOM_$1,Assign domain for CKGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xA0 0xA1 0xA2 0xA3 0xA4 0xA5 0xA6 0xA7 0xA8 0xA9 0xAA 0xAB 0xAC 0xAD 0xAE 0xAF )(list 0x280 0x284 0x288 0x28C 0x290 0x294 0x298 0x29C 0x2A0 0x2A4 0x2A8 0x2AC 0x2B0 0x2B4 0x2B8 0x2BC ) group.long ($2)++0x3 line.long 0x0 "REGG0_DOM_$1,Assign domain for CKGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xB0 0xB1 0xB2 0xB3 0xB4 0xB5 0xB6 0xB7 0xB8 0xB9 0xBA 0xBB 0xBC 0xBD 0xBE 0xBF )(list 0x2C0 0x2C4 0x2C8 0x2CC 0x2D0 0x2D4 0x2D8 0x2DC 0x2E0 0x2E4 0x2E8 0x2EC 0x2F0 0x2F4 0x2F8 0x2FC ) group.long ($2)++0x3 line.long 0x0 "REGG0_DOM_$1,Assign domain for CKGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xC0 0xC1 0xC2 0xC3 0xC4 0xC5 0xC6 0xC7 0xC8 0xC9 0xCA 0xCB 0xCC 0xCD 0xCE 0xCF )(list 0x300 0x304 0x308 0x30C 0x310 0x314 0x318 0x31C 0x320 0x324 0x328 0x32C 0x330 0x334 0x338 0x33C ) group.long ($2)++0x3 line.long 0x0 "REGG0_DOM_$1,Assign domain for CKGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xD0 0xD1 0xD2 0xD3 0xD4 0xD5 0xD6 0xD7 0xD8 0xD9 0xDA 0xDB 0xDC 0xDD 0xDE 0xDF )(list 0x340 0x344 0x348 0x34C 0x350 0x354 0x358 0x35C 0x360 0x364 0x368 0x36C 0x370 0x374 0x378 0x37C ) group.long ($2)++0x3 line.long 0x0 "REGG0_DOM_$1,Assign domain for CKGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xE0 0xE1 0xE2 0xE3 0xE4 0xE5 0xE6 0xE7 0xE8 0xE9 0xEA 0xEB 0xEC 0xED 0xEE 0xEF )(list 0x380 0x384 0x388 0x38C 0x390 0x394 0x398 0x39C 0x3A0 0x3A4 0x3A8 0x3AC 0x3B0 0x3B4 0x3B8 0x3BC ) group.long ($2)++0x3 line.long 0x0 "REGG0_DOM_$1,Assign domain for CKGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xF0 0xF1 0xF2 0xF3 0xF4 0xF5 0xF6 0xF7 0xF8 0xF9 0xFA 0xFB 0xFC 0xFD 0xFE 0xFF )(list 0x3C0 0x3C4 0x3C8 0x3CC 0x3D0 0x3D4 0x3D8 0x3DC 0x3E0 0x3E4 0x3E8 0x3EC 0x3F0 0x3F4 0x3F8 0x3FC ) group.long ($2)++0x3 line.long 0x0 "REGG0_DOM_$1,Assign domain for CKGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x4 0x8 0xC 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C ) group.long ($2+0x400)++0x3 line.long 0x0 "REGG1_DOM_$1,Assign domain for CKGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1A 0x1B 0x1C 0x1D 0x1E 0x1F )(list 0x40 0x44 0x48 0x4C 0x50 0x54 0x58 0x5C 0x60 0x64 0x68 0x6C 0x70 0x74 0x78 0x7C ) group.long ($2+0x400)++0x3 line.long 0x0 "REGG1_DOM_$1,Assign domain for CKGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x20 0x21 0x22 0x23 0x24 0x25 0x26 0x27 0x28 0x29 0x2A 0x2B 0x2C 0x2D 0x2E 0x2F )(list 0x80 0x84 0x88 0x8C 0x90 0x94 0x98 0x9C 0xA0 0xA4 0xA8 0xAC 0xB0 0xB4 0xB8 0xBC ) group.long ($2+0x400)++0x3 line.long 0x0 "REGG1_DOM_$1,Assign domain for CKGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x30 0x31 0x32 0x33 0x34 0x35 0x36 0x37 0x38 0x39 0x3A 0x3B 0x3C 0x3D 0x3E 0x3F )(list 0xC0 0xC4 0xC8 0xCC 0xD0 0xD4 0xD8 0xDC 0xE0 0xE4 0xE8 0xEC 0xF0 0xF4 0xF8 0xFC ) group.long ($2+0x400)++0x3 line.long 0x0 "REGG1_DOM_$1,Assign domain for CKGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x40 0x41 0x42 0x43 0x44 0x45 0x46 0x47 0x48 0x49 0x4A 0x4B 0x4C 0x4D 0x4E 0x4F )(list 0x100 0x104 0x108 0x10C 0x110 0x114 0x118 0x11C 0x120 0x124 0x128 0x12C 0x130 0x134 0x138 0x13C ) group.long ($2+0x400)++0x3 line.long 0x0 "REGG1_DOM_$1,Assign domain for CKGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x50 0x51 0x52 0x53 0x54 0x55 0x56 0x57 0x58 0x59 0x5A 0x5B 0x5C 0x5D 0x5E 0x5F )(list 0x140 0x144 0x148 0x14C 0x150 0x154 0x158 0x15C 0x160 0x164 0x168 0x16C 0x170 0x174 0x178 0x17C ) group.long ($2+0x400)++0x3 line.long 0x0 "REGG1_DOM_$1,Assign domain for CKGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x60 0x61 0x62 0x63 0x64 0x65 0x66 0x67 0x68 0x69 0x6A 0x6B 0x6C 0x6D 0x6E 0x6F )(list 0x180 0x184 0x188 0x18C 0x190 0x194 0x198 0x19C 0x1A0 0x1A4 0x1A8 0x1AC 0x1B0 0x1B4 0x1B8 0x1BC ) group.long ($2+0x400)++0x3 line.long 0x0 "REGG1_DOM_$1,Assign domain for CKGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x70 0x71 0x72 0x73 0x74 0x75 0x76 0x77 0x78 0x79 0x7A 0x7B 0x7C 0x7D 0x7E 0x7F )(list 0x1C0 0x1C4 0x1C8 0x1CC 0x1D0 0x1D4 0x1D8 0x1DC 0x1E0 0x1E4 0x1E8 0x1EC 0x1F0 0x1F4 0x1F8 0x1FC ) group.long ($2+0x400)++0x3 line.long 0x0 "REGG1_DOM_$1,Assign domain for CKGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x80 0x81 0x82 0x83 0x84 0x85 0x86 0x87 0x88 0x89 0x8A 0x8B 0x8C 0x8D 0x8E 0x8F )(list 0x200 0x204 0x208 0x20C 0x210 0x214 0x218 0x21C 0x220 0x224 0x228 0x22C 0x230 0x234 0x238 0x23C ) group.long ($2+0x400)++0x3 line.long 0x0 "REGG1_DOM_$1,Assign domain for CKGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x90 0x91 0x92 0x93 0x94 0x95 0x96 0x97 0x98 0x99 0x9A 0x9B 0x9C 0x9D 0x9E 0x9F )(list 0x240 0x244 0x248 0x24C 0x250 0x254 0x258 0x25C 0x260 0x264 0x268 0x26C 0x270 0x274 0x278 0x27C ) group.long ($2+0x400)++0x3 line.long 0x0 "REGG1_DOM_$1,Assign domain for CKGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xA0 0xA1 0xA2 0xA3 0xA4 0xA5 0xA6 0xA7 0xA8 0xA9 0xAA 0xAB 0xAC 0xAD 0xAE 0xAF )(list 0x280 0x284 0x288 0x28C 0x290 0x294 0x298 0x29C 0x2A0 0x2A4 0x2A8 0x2AC 0x2B0 0x2B4 0x2B8 0x2BC ) group.long ($2+0x400)++0x3 line.long 0x0 "REGG1_DOM_$1,Assign domain for CKGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xB0 0xB1 0xB2 0xB3 0xB4 0xB5 0xB6 0xB7 0xB8 0xB9 0xBA 0xBB 0xBC 0xBD 0xBE 0xBF )(list 0x2C0 0x2C4 0x2C8 0x2CC 0x2D0 0x2D4 0x2D8 0x2DC 0x2E0 0x2E4 0x2E8 0x2EC 0x2F0 0x2F4 0x2F8 0x2FC ) group.long ($2+0x400)++0x3 line.long 0x0 "REGG1_DOM_$1,Assign domain for CKGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xC0 0xC1 0xC2 0xC3 0xC4 0xC5 0xC6 0xC7 0xC8 0xC9 0xCA 0xCB 0xCC 0xCD 0xCE 0xCF )(list 0x300 0x304 0x308 0x30C 0x310 0x314 0x318 0x31C 0x320 0x324 0x328 0x32C 0x330 0x334 0x338 0x33C ) group.long ($2+0x400)++0x3 line.long 0x0 "REGG1_DOM_$1,Assign domain for CKGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xD0 0xD1 0xD2 0xD3 0xD4 0xD5 0xD6 0xD7 0xD8 0xD9 0xDA 0xDB 0xDC 0xDD 0xDE 0xDF )(list 0x340 0x344 0x348 0x34C 0x350 0x354 0x358 0x35C 0x360 0x364 0x368 0x36C 0x370 0x374 0x378 0x37C ) group.long ($2+0x400)++0x3 line.long 0x0 "REGG1_DOM_$1,Assign domain for CKGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xE0 0xE1 0xE2 0xE3 0xE4 0xE5 0xE6 0xE7 0xE8 0xE9 0xEA 0xEB 0xEC 0xED 0xEE 0xEF )(list 0x380 0x384 0x388 0x38C 0x390 0x394 0x398 0x39C 0x3A0 0x3A4 0x3A8 0x3AC 0x3B0 0x3B4 0x3B8 0x3BC ) group.long ($2+0x400)++0x3 line.long 0x0 "REGG1_DOM_$1,Assign domain for CKGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xF0 0xF1 0xF2 0xF3 0xF4 0xF5 0xF6 0xF7 0xF8 0xF9 0xFA 0xFB 0xFC 0xFD 0xFE 0xFF )(list 0x3C0 0x3C4 0x3C8 0x3CC 0x3D0 0x3D4 0x3D8 0x3DC 0x3E0 0x3E4 0x3E8 0x3EC 0x3F0 0x3F4 0x3F8 0x3FC ) group.long ($2+0x400)++0x3 line.long 0x0 "REGG1_DOM_$1,Assign domain for CKGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x4 0x8 0xC 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C ) group.long ($2+0x800)++0x3 line.long 0x0 "REGG2_DOM_$1,Assign domain for SCR registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1A 0x1B 0x1C 0x1D 0x1E 0x1F )(list 0x40 0x44 0x48 0x4C 0x50 0x54 0x58 0x5C 0x60 0x64 0x68 0x6C 0x70 0x74 0x78 0x7C ) group.long ($2+0x800)++0x3 line.long 0x0 "REGG2_DOM_$1,Assign domain for SCR registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x20 0x21 0x22 0x23 0x24 0x25 0x26 0x27 0x28 0x29 0x2A 0x2B 0x2C 0x2D 0x2E 0x2F )(list 0x80 0x84 0x88 0x8C 0x90 0x94 0x98 0x9C 0xA0 0xA4 0xA8 0xAC 0xB0 0xB4 0xB8 0xBC ) group.long ($2+0x800)++0x3 line.long 0x0 "REGG2_DOM_$1,Assign domain for SCR registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x30 0x31 0x32 0x33 0x34 0x35 0x36 0x37 0x38 0x39 0x3A 0x3B 0x3C 0x3D 0x3E 0x3F )(list 0xC0 0xC4 0xC8 0xCC 0xD0 0xD4 0xD8 0xDC 0xE0 0xE4 0xE8 0xEC 0xF0 0xF4 0xF8 0xFC ) group.long ($2+0x800)++0x3 line.long 0x0 "REGG2_DOM_$1,Assign domain for SCR registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x40 0x41 0x42 0x43 0x44 0x45 0x46 0x47 0x48 0x49 0x4A 0x4B 0x4C 0x4D 0x4E 0x4F )(list 0x100 0x104 0x108 0x10C 0x110 0x114 0x118 0x11C 0x120 0x124 0x128 0x12C 0x130 0x134 0x138 0x13C ) group.long ($2+0x800)++0x3 line.long 0x0 "REGG2_DOM_$1,Assign domain for SCR registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x50 0x51 0x52 0x53 0x54 0x55 0x56 0x57 0x58 0x59 0x5A 0x5B 0x5C 0x5D 0x5E 0x5F )(list 0x140 0x144 0x148 0x14C 0x150 0x154 0x158 0x15C 0x160 0x164 0x168 0x16C 0x170 0x174 0x178 0x17C ) group.long ($2+0x800)++0x3 line.long 0x0 "REGG2_DOM_$1,Assign domain for SCR registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x60 0x61 0x62 0x63 0x64 0x65 0x66 0x67 0x68 0x69 0x6A 0x6B 0x6C 0x6D 0x6E 0x6F )(list 0x180 0x184 0x188 0x18C 0x190 0x194 0x198 0x19C 0x1A0 0x1A4 0x1A8 0x1AC 0x1B0 0x1B4 0x1B8 0x1BC ) group.long ($2+0x800)++0x3 line.long 0x0 "REGG2_DOM_$1,Assign domain for SCR registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x70 0x71 0x72 0x73 0x74 0x75 0x76 0x77 0x78 0x79 0x7A 0x7B 0x7C 0x7D 0x7E 0x7F )(list 0x1C0 0x1C4 0x1C8 0x1CC 0x1D0 0x1D4 0x1D8 0x1DC 0x1E0 0x1E4 0x1E8 0x1EC 0x1F0 0x1F4 0x1F8 0x1FC ) group.long ($2+0x800)++0x3 line.long 0x0 "REGG2_DOM_$1,Assign domain for SCR registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x80 0x81 0x82 0x83 0x84 0x85 0x86 0x87 0x88 0x89 0x8A 0x8B 0x8C 0x8D 0x8E 0x8F )(list 0x200 0x204 0x208 0x20C 0x210 0x214 0x218 0x21C 0x220 0x224 0x228 0x22C 0x230 0x234 0x238 0x23C ) group.long ($2+0x800)++0x3 line.long 0x0 "REGG2_DOM_$1,Assign domain for SCR registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x90 0x91 0x92 0x93 0x94 0x95 0x96 0x97 0x98 0x99 0x9A 0x9B 0x9C 0x9D 0x9E 0x9F )(list 0x240 0x244 0x248 0x24C 0x250 0x254 0x258 0x25C 0x260 0x264 0x268 0x26C 0x270 0x274 0x278 0x27C ) group.long ($2+0x800)++0x3 line.long 0x0 "REGG2_DOM_$1,Assign domain for SCR registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xA0 0xA1 0xA2 0xA3 0xA4 0xA5 0xA6 0xA7 0xA8 0xA9 0xAA 0xAB 0xAC 0xAD 0xAE 0xAF )(list 0x280 0x284 0x288 0x28C 0x290 0x294 0x298 0x29C 0x2A0 0x2A4 0x2A8 0x2AC 0x2B0 0x2B4 0x2B8 0x2BC ) group.long ($2+0x800)++0x3 line.long 0x0 "REGG2_DOM_$1,Assign domain for SCR registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xB0 0xB1 0xB2 0xB3 0xB4 0xB5 0xB6 0xB7 0xB8 0xB9 0xBA 0xBB 0xBC 0xBD 0xBE 0xBF )(list 0x2C0 0x2C4 0x2C8 0x2CC 0x2D0 0x2D4 0x2D8 0x2DC 0x2E0 0x2E4 0x2E8 0x2EC 0x2F0 0x2F4 0x2F8 0x2FC ) group.long ($2+0x800)++0x3 line.long 0x0 "REGG2_DOM_$1,Assign domain for SCR registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xC0 0xC1 0xC2 0xC3 0xC4 0xC5 0xC6 0xC7 0xC8 0xC9 0xCA 0xCB 0xCC 0xCD 0xCE 0xCF )(list 0x300 0x304 0x308 0x30C 0x310 0x314 0x318 0x31C 0x320 0x324 0x328 0x32C 0x330 0x334 0x338 0x33C ) group.long ($2+0x800)++0x3 line.long 0x0 "REGG2_DOM_$1,Assign domain for SCR registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xD0 0xD1 0xD2 0xD3 0xD4 0xD5 0xD6 0xD7 0xD8 0xD9 0xDA 0xDB 0xDC 0xDD 0xDE 0xDF )(list 0x340 0x344 0x348 0x34C 0x350 0x354 0x358 0x35C 0x360 0x364 0x368 0x36C 0x370 0x374 0x378 0x37C ) group.long ($2+0x800)++0x3 line.long 0x0 "REGG2_DOM_$1,Assign domain for SCR registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xE0 0xE1 0xE2 0xE3 0xE4 0xE5 0xE6 0xE7 0xE8 0xE9 0xEA 0xEB 0xEC 0xED 0xEE 0xEF )(list 0x380 0x384 0x388 0x38C 0x390 0x394 0x398 0x39C 0x3A0 0x3A4 0x3A8 0x3AC 0x3B0 0x3B4 0x3B8 0x3BC ) group.long ($2+0x800)++0x3 line.long 0x0 "REGG2_DOM_$1,Assign domain for SCR registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xF0 0xF1 0xF2 0xF3 0xF4 0xF5 0xF6 0xF7 0xF8 0xF9 0xFA 0xFB 0xFC 0xFD 0xFE 0xFF )(list 0x3C0 0x3C4 0x3C8 0x3CC 0x3D0 0x3D4 0x3D8 0x3DC 0x3E0 0x3E4 0x3E8 0x3EC 0x3F0 0x3F4 0x3F8 0x3FC ) group.long ($2+0x800)++0x3 line.long 0x0 "REGG2_DOM_$1,Assign domain for SCR registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x4 0x8 0xC 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C ) group.long ($2+0xC00)++0x3 line.long 0x0 "REGG3_DOM_$1,Assign domain for SCR registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1A 0x1B 0x1C 0x1D 0x1E 0x1F )(list 0x40 0x44 0x48 0x4C 0x50 0x54 0x58 0x5C 0x60 0x64 0x68 0x6C 0x70 0x74 0x78 0x7C ) group.long ($2+0xC00)++0x3 line.long 0x0 "REGG3_DOM_$1,Assign domain for SCR registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x20 0x21 0x22 0x23 0x24 0x25 0x26 0x27 0x28 0x29 0x2A 0x2B 0x2C 0x2D 0x2E 0x2F )(list 0x80 0x84 0x88 0x8C 0x90 0x94 0x98 0x9C 0xA0 0xA4 0xA8 0xAC 0xB0 0xB4 0xB8 0xBC ) group.long ($2+0xC00)++0x3 line.long 0x0 "REGG3_DOM_$1,Assign domain for SCR registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x30 0x31 0x32 0x33 0x34 0x35 0x36 0x37 0x38 0x39 0x3A 0x3B 0x3C 0x3D 0x3E 0x3F )(list 0xC0 0xC4 0xC8 0xCC 0xD0 0xD4 0xD8 0xDC 0xE0 0xE4 0xE8 0xEC 0xF0 0xF4 0xF8 0xFC ) group.long ($2+0xC00)++0x3 line.long 0x0 "REGG3_DOM_$1,Assign domain for SCR registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x40 0x41 0x42 0x43 0x44 0x45 0x46 0x47 0x48 0x49 0x4A 0x4B 0x4C 0x4D 0x4E 0x4F )(list 0x100 0x104 0x108 0x10C 0x110 0x114 0x118 0x11C 0x120 0x124 0x128 0x12C 0x130 0x134 0x138 0x13C ) group.long ($2+0xC00)++0x3 line.long 0x0 "REGG3_DOM_$1,Assign domain for SCR registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x50 0x51 0x52 0x53 0x54 0x55 0x56 0x57 0x58 0x59 0x5A 0x5B 0x5C 0x5D 0x5E 0x5F )(list 0x140 0x144 0x148 0x14C 0x150 0x154 0x158 0x15C 0x160 0x164 0x168 0x16C 0x170 0x174 0x178 0x17C ) group.long ($2+0xC00)++0x3 line.long 0x0 "REGG3_DOM_$1,Assign domain for SCR registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x60 0x61 0x62 0x63 0x64 0x65 0x66 0x67 0x68 0x69 0x6A 0x6B 0x6C 0x6D 0x6E 0x6F )(list 0x180 0x184 0x188 0x18C 0x190 0x194 0x198 0x19C 0x1A0 0x1A4 0x1A8 0x1AC 0x1B0 0x1B4 0x1B8 0x1BC ) group.long ($2+0xC00)++0x3 line.long 0x0 "REGG3_DOM_$1,Assign domain for SCR registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x70 0x71 0x72 0x73 0x74 0x75 0x76 0x77 0x78 0x79 0x7A 0x7B 0x7C 0x7D 0x7E 0x7F )(list 0x1C0 0x1C4 0x1C8 0x1CC 0x1D0 0x1D4 0x1D8 0x1DC 0x1E0 0x1E4 0x1E8 0x1EC 0x1F0 0x1F4 0x1F8 0x1FC ) group.long ($2+0xC00)++0x3 line.long 0x0 "REGG3_DOM_$1,Assign domain for SCR registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x80 0x81 0x82 0x83 0x84 0x85 0x86 0x87 0x88 0x89 0x8A 0x8B 0x8C 0x8D 0x8E 0x8F )(list 0x200 0x204 0x208 0x20C 0x210 0x214 0x218 0x21C 0x220 0x224 0x228 0x22C 0x230 0x234 0x238 0x23C ) group.long ($2+0xC00)++0x3 line.long 0x0 "REGG3_DOM_$1,Assign domain for SCR registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x90 0x91 0x92 0x93 0x94 0x95 0x96 0x97 0x98 0x99 0x9A 0x9B 0x9C 0x9D 0x9E 0x9F )(list 0x240 0x244 0x248 0x24C 0x250 0x254 0x258 0x25C 0x260 0x264 0x268 0x26C 0x270 0x274 0x278 0x27C ) group.long ($2+0xC00)++0x3 line.long 0x0 "REGG3_DOM_$1,Assign domain for SCR registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xA0 0xA1 0xA2 0xA3 0xA4 0xA5 0xA6 0xA7 0xA8 0xA9 0xAA 0xAB 0xAC 0xAD 0xAE 0xAF )(list 0x280 0x284 0x288 0x28C 0x290 0x294 0x298 0x29C 0x2A0 0x2A4 0x2A8 0x2AC 0x2B0 0x2B4 0x2B8 0x2BC ) group.long ($2+0xC00)++0x3 line.long 0x0 "REGG3_DOM_$1,Assign domain for SCR registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xB0 0xB1 0xB2 0xB3 0xB4 0xB5 0xB6 0xB7 0xB8 0xB9 0xBA 0xBB 0xBC 0xBD 0xBE 0xBF )(list 0x2C0 0x2C4 0x2C8 0x2CC 0x2D0 0x2D4 0x2D8 0x2DC 0x2E0 0x2E4 0x2E8 0x2EC 0x2F0 0x2F4 0x2F8 0x2FC ) group.long ($2+0xC00)++0x3 line.long 0x0 "REGG3_DOM_$1,Assign domain for SCR registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xC0 0xC1 0xC2 0xC3 0xC4 0xC5 0xC6 0xC7 0xC8 0xC9 0xCA 0xCB 0xCC 0xCD 0xCE 0xCF )(list 0x300 0x304 0x308 0x30C 0x310 0x314 0x318 0x31C 0x320 0x324 0x328 0x32C 0x330 0x334 0x338 0x33C ) group.long ($2+0xC00)++0x3 line.long 0x0 "REGG3_DOM_$1,Assign domain for SCR registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xD0 0xD1 0xD2 0xD3 0xD4 0xD5 0xD6 0xD7 0xD8 0xD9 0xDA 0xDB 0xDC 0xDD 0xDE 0xDF )(list 0x340 0x344 0x348 0x34C 0x350 0x354 0x358 0x35C 0x360 0x364 0x368 0x36C 0x370 0x374 0x378 0x37C ) group.long ($2+0xC00)++0x3 line.long 0x0 "REGG3_DOM_$1,Assign domain for SCR registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xE0 0xE1 0xE2 0xE3 0xE4 0xE5 0xE6 0xE7 0xE8 0xE9 0xEA 0xEB 0xEC 0xED 0xEE 0xEF )(list 0x380 0x384 0x388 0x38C 0x390 0x394 0x398 0x39C 0x3A0 0x3A4 0x3A8 0x3AC 0x3B0 0x3B4 0x3B8 0x3BC ) group.long ($2+0xC00)++0x3 line.long 0x0 "REGG3_DOM_$1,Assign domain for SCR registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xF0 0xF1 0xF2 0xF3 0xF4 0xF5 0xF6 0xF7 0xF8 0xF9 0xFA 0xFB 0xFC 0xFD 0xFE 0xFF )(list 0x3C0 0x3C4 0x3C8 0x3CC 0x3D0 0x3D4 0x3D8 0x3DC 0x3E0 0x3E4 0x3E8 0x3EC 0x3F0 0x3F4 0x3F8 0x3FC ) group.long ($2+0xC00)++0x3 line.long 0x0 "REGG3_DOM_$1,Assign domain for SCR registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x4 0x8 0xC 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C ) group.long ($2+0x1000)++0x3 line.long 0x0 "REGG4_DOM_$1,Assign domain for RSTGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1A 0x1B 0x1C 0x1D 0x1E 0x1F )(list 0x40 0x44 0x48 0x4C 0x50 0x54 0x58 0x5C 0x60 0x64 0x68 0x6C 0x70 0x74 0x78 0x7C ) group.long ($2+0x1000)++0x3 line.long 0x0 "REGG4_DOM_$1,Assign domain for RSTGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x20 0x21 0x22 0x23 0x24 0x25 0x26 0x27 0x28 0x29 0x2A 0x2B 0x2C 0x2D 0x2E 0x2F )(list 0x80 0x84 0x88 0x8C 0x90 0x94 0x98 0x9C 0xA0 0xA4 0xA8 0xAC 0xB0 0xB4 0xB8 0xBC ) group.long ($2+0x1000)++0x3 line.long 0x0 "REGG4_DOM_$1,Assign domain for RSTGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x30 0x31 0x32 0x33 0x34 0x35 0x36 0x37 0x38 0x39 0x3A 0x3B 0x3C 0x3D 0x3E 0x3F )(list 0xC0 0xC4 0xC8 0xCC 0xD0 0xD4 0xD8 0xDC 0xE0 0xE4 0xE8 0xEC 0xF0 0xF4 0xF8 0xFC ) group.long ($2+0x1000)++0x3 line.long 0x0 "REGG4_DOM_$1,Assign domain for RSTGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x40 0x41 0x42 0x43 0x44 0x45 0x46 0x47 0x48 0x49 0x4A 0x4B 0x4C 0x4D 0x4E 0x4F )(list 0x100 0x104 0x108 0x10C 0x110 0x114 0x118 0x11C 0x120 0x124 0x128 0x12C 0x130 0x134 0x138 0x13C ) group.long ($2+0x1000)++0x3 line.long 0x0 "REGG4_DOM_$1,Assign domain for RSTGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x50 0x51 0x52 0x53 0x54 0x55 0x56 0x57 0x58 0x59 0x5A 0x5B 0x5C 0x5D 0x5E 0x5F )(list 0x140 0x144 0x148 0x14C 0x150 0x154 0x158 0x15C 0x160 0x164 0x168 0x16C 0x170 0x174 0x178 0x17C ) group.long ($2+0x1000)++0x3 line.long 0x0 "REGG4_DOM_$1,Assign domain for RSTGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x60 0x61 0x62 0x63 0x64 0x65 0x66 0x67 0x68 0x69 0x6A 0x6B 0x6C 0x6D 0x6E 0x6F )(list 0x180 0x184 0x188 0x18C 0x190 0x194 0x198 0x19C 0x1A0 0x1A4 0x1A8 0x1AC 0x1B0 0x1B4 0x1B8 0x1BC ) group.long ($2+0x1000)++0x3 line.long 0x0 "REGG4_DOM_$1,Assign domain for RSTGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x70 0x71 0x72 0x73 0x74 0x75 0x76 0x77 0x78 0x79 0x7A 0x7B 0x7C 0x7D 0x7E 0x7F )(list 0x1C0 0x1C4 0x1C8 0x1CC 0x1D0 0x1D4 0x1D8 0x1DC 0x1E0 0x1E4 0x1E8 0x1EC 0x1F0 0x1F4 0x1F8 0x1FC ) group.long ($2+0x1000)++0x3 line.long 0x0 "REGG4_DOM_$1,Assign domain for RSTGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x80 0x81 0x82 0x83 0x84 0x85 0x86 0x87 0x88 0x89 0x8A 0x8B 0x8C 0x8D 0x8E 0x8F )(list 0x200 0x204 0x208 0x20C 0x210 0x214 0x218 0x21C 0x220 0x224 0x228 0x22C 0x230 0x234 0x238 0x23C ) group.long ($2+0x1000)++0x3 line.long 0x0 "REGG4_DOM_$1,Assign domain for RSTGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x90 0x91 0x92 0x93 0x94 0x95 0x96 0x97 0x98 0x99 0x9A 0x9B 0x9C 0x9D 0x9E 0x9F )(list 0x240 0x244 0x248 0x24C 0x250 0x254 0x258 0x25C 0x260 0x264 0x268 0x26C 0x270 0x274 0x278 0x27C ) group.long ($2+0x1000)++0x3 line.long 0x0 "REGG4_DOM_$1,Assign domain for RSTGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xA0 0xA1 0xA2 0xA3 0xA4 0xA5 0xA6 0xA7 0xA8 0xA9 0xAA 0xAB 0xAC 0xAD 0xAE 0xAF )(list 0x280 0x284 0x288 0x28C 0x290 0x294 0x298 0x29C 0x2A0 0x2A4 0x2A8 0x2AC 0x2B0 0x2B4 0x2B8 0x2BC ) group.long ($2+0x1000)++0x3 line.long 0x0 "REGG4_DOM_$1,Assign domain for RSTGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xB0 0xB1 0xB2 0xB3 0xB4 0xB5 0xB6 0xB7 0xB8 0xB9 0xBA 0xBB 0xBC 0xBD 0xBE 0xBF )(list 0x2C0 0x2C4 0x2C8 0x2CC 0x2D0 0x2D4 0x2D8 0x2DC 0x2E0 0x2E4 0x2E8 0x2EC 0x2F0 0x2F4 0x2F8 0x2FC ) group.long ($2+0x1000)++0x3 line.long 0x0 "REGG4_DOM_$1,Assign domain for RSTGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xC0 0xC1 0xC2 0xC3 0xC4 0xC5 0xC6 0xC7 0xC8 0xC9 0xCA 0xCB 0xCC 0xCD 0xCE 0xCF )(list 0x300 0x304 0x308 0x30C 0x310 0x314 0x318 0x31C 0x320 0x324 0x328 0x32C 0x330 0x334 0x338 0x33C ) group.long ($2+0x1000)++0x3 line.long 0x0 "REGG4_DOM_$1,Assign domain for RSTGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xD0 0xD1 0xD2 0xD3 0xD4 0xD5 0xD6 0xD7 0xD8 0xD9 0xDA 0xDB 0xDC 0xDD 0xDE 0xDF )(list 0x340 0x344 0x348 0x34C 0x350 0x354 0x358 0x35C 0x360 0x364 0x368 0x36C 0x370 0x374 0x378 0x37C ) group.long ($2+0x1000)++0x3 line.long 0x0 "REGG4_DOM_$1,Assign domain for RSTGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xE0 0xE1 0xE2 0xE3 0xE4 0xE5 0xE6 0xE7 0xE8 0xE9 0xEA 0xEB 0xEC 0xED 0xEE 0xEF )(list 0x380 0x384 0x388 0x38C 0x390 0x394 0x398 0x39C 0x3A0 0x3A4 0x3A8 0x3AC 0x3B0 0x3B4 0x3B8 0x3BC ) group.long ($2+0x1000)++0x3 line.long 0x0 "REGG4_DOM_$1,Assign domain for RSTGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xF0 0xF1 0xF2 0xF3 0xF4 0xF5 0xF6 0xF7 0xF8 0xF9 0xFA 0xFB 0xFC 0xFD 0xFE 0xFF )(list 0x3C0 0x3C4 0x3C8 0x3CC 0x3D0 0x3D4 0x3D8 0x3DC 0x3E0 0x3E4 0x3E8 0x3EC 0x3F0 0x3F4 0x3F8 0x3FC ) group.long ($2+0x1000)++0x3 line.long 0x0 "REGG4_DOM_$1,Assign domain for RSTGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x4 0x8 0xC 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C ) group.long ($2+0x1400)++0x3 line.long 0x0 "REGG5_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1A 0x1B 0x1C 0x1D 0x1E 0x1F )(list 0x40 0x44 0x48 0x4C 0x50 0x54 0x58 0x5C 0x60 0x64 0x68 0x6C 0x70 0x74 0x78 0x7C ) group.long ($2+0x1400)++0x3 line.long 0x0 "REGG5_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x20 0x21 0x22 0x23 0x24 0x25 0x26 0x27 0x28 0x29 0x2A 0x2B 0x2C 0x2D 0x2E 0x2F )(list 0x80 0x84 0x88 0x8C 0x90 0x94 0x98 0x9C 0xA0 0xA4 0xA8 0xAC 0xB0 0xB4 0xB8 0xBC ) group.long ($2+0x1400)++0x3 line.long 0x0 "REGG5_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x30 0x31 0x32 0x33 0x34 0x35 0x36 0x37 0x38 0x39 0x3A 0x3B 0x3C 0x3D 0x3E 0x3F )(list 0xC0 0xC4 0xC8 0xCC 0xD0 0xD4 0xD8 0xDC 0xE0 0xE4 0xE8 0xEC 0xF0 0xF4 0xF8 0xFC ) group.long ($2+0x1400)++0x3 line.long 0x0 "REGG5_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x40 0x41 0x42 0x43 0x44 0x45 0x46 0x47 0x48 0x49 0x4A 0x4B 0x4C 0x4D 0x4E 0x4F )(list 0x100 0x104 0x108 0x10C 0x110 0x114 0x118 0x11C 0x120 0x124 0x128 0x12C 0x130 0x134 0x138 0x13C ) group.long ($2+0x1400)++0x3 line.long 0x0 "REGG5_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x50 0x51 0x52 0x53 0x54 0x55 0x56 0x57 0x58 0x59 0x5A 0x5B 0x5C 0x5D 0x5E 0x5F )(list 0x140 0x144 0x148 0x14C 0x150 0x154 0x158 0x15C 0x160 0x164 0x168 0x16C 0x170 0x174 0x178 0x17C ) group.long ($2+0x1400)++0x3 line.long 0x0 "REGG5_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x60 0x61 0x62 0x63 0x64 0x65 0x66 0x67 0x68 0x69 0x6A 0x6B 0x6C 0x6D 0x6E 0x6F )(list 0x180 0x184 0x188 0x18C 0x190 0x194 0x198 0x19C 0x1A0 0x1A4 0x1A8 0x1AC 0x1B0 0x1B4 0x1B8 0x1BC ) group.long ($2+0x1400)++0x3 line.long 0x0 "REGG5_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x70 0x71 0x72 0x73 0x74 0x75 0x76 0x77 0x78 0x79 0x7A 0x7B 0x7C 0x7D 0x7E 0x7F )(list 0x1C0 0x1C4 0x1C8 0x1CC 0x1D0 0x1D4 0x1D8 0x1DC 0x1E0 0x1E4 0x1E8 0x1EC 0x1F0 0x1F4 0x1F8 0x1FC ) group.long ($2+0x1400)++0x3 line.long 0x0 "REGG5_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x80 0x81 0x82 0x83 0x84 0x85 0x86 0x87 0x88 0x89 0x8A 0x8B 0x8C 0x8D 0x8E 0x8F )(list 0x200 0x204 0x208 0x20C 0x210 0x214 0x218 0x21C 0x220 0x224 0x228 0x22C 0x230 0x234 0x238 0x23C ) group.long ($2+0x1400)++0x3 line.long 0x0 "REGG5_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x90 0x91 0x92 0x93 0x94 0x95 0x96 0x97 0x98 0x99 0x9A 0x9B 0x9C 0x9D 0x9E 0x9F )(list 0x240 0x244 0x248 0x24C 0x250 0x254 0x258 0x25C 0x260 0x264 0x268 0x26C 0x270 0x274 0x278 0x27C ) group.long ($2+0x1400)++0x3 line.long 0x0 "REGG5_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xA0 0xA1 0xA2 0xA3 0xA4 0xA5 0xA6 0xA7 0xA8 0xA9 0xAA 0xAB 0xAC 0xAD 0xAE 0xAF )(list 0x280 0x284 0x288 0x28C 0x290 0x294 0x298 0x29C 0x2A0 0x2A4 0x2A8 0x2AC 0x2B0 0x2B4 0x2B8 0x2BC ) group.long ($2+0x1400)++0x3 line.long 0x0 "REGG5_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xB0 0xB1 0xB2 0xB3 0xB4 0xB5 0xB6 0xB7 0xB8 0xB9 0xBA 0xBB 0xBC 0xBD 0xBE 0xBF )(list 0x2C0 0x2C4 0x2C8 0x2CC 0x2D0 0x2D4 0x2D8 0x2DC 0x2E0 0x2E4 0x2E8 0x2EC 0x2F0 0x2F4 0x2F8 0x2FC ) group.long ($2+0x1400)++0x3 line.long 0x0 "REGG5_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xC0 0xC1 0xC2 0xC3 0xC4 0xC5 0xC6 0xC7 0xC8 0xC9 0xCA 0xCB 0xCC 0xCD 0xCE 0xCF )(list 0x300 0x304 0x308 0x30C 0x310 0x314 0x318 0x31C 0x320 0x324 0x328 0x32C 0x330 0x334 0x338 0x33C ) group.long ($2+0x1400)++0x3 line.long 0x0 "REGG5_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xD0 0xD1 0xD2 0xD3 0xD4 0xD5 0xD6 0xD7 0xD8 0xD9 0xDA 0xDB 0xDC 0xDD 0xDE 0xDF )(list 0x340 0x344 0x348 0x34C 0x350 0x354 0x358 0x35C 0x360 0x364 0x368 0x36C 0x370 0x374 0x378 0x37C ) group.long ($2+0x1400)++0x3 line.long 0x0 "REGG5_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xE0 0xE1 0xE2 0xE3 0xE4 0xE5 0xE6 0xE7 0xE8 0xE9 0xEA 0xEB 0xEC 0xED 0xEE 0xEF )(list 0x380 0x384 0x388 0x38C 0x390 0x394 0x398 0x39C 0x3A0 0x3A4 0x3A8 0x3AC 0x3B0 0x3B4 0x3B8 0x3BC ) group.long ($2+0x1400)++0x3 line.long 0x0 "REGG5_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xF0 0xF1 0xF2 0xF3 0xF4 0xF5 0xF6 0xF7 0xF8 0xF9 0xFA 0xFB 0xFC 0xFD 0xFE 0xFF )(list 0x3C0 0x3C4 0x3C8 0x3CC 0x3D0 0x3D4 0x3D8 0x3DC 0x3E0 0x3E4 0x3E8 0x3EC 0x3F0 0x3F4 0x3F8 0x3FC ) group.long ($2+0x1400)++0x3 line.long 0x0 "REGG5_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x4 0x8 0xC 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C ) group.long ($2+0x1800)++0x3 line.long 0x0 "REGG6_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1A 0x1B 0x1C 0x1D 0x1E 0x1F )(list 0x40 0x44 0x48 0x4C 0x50 0x54 0x58 0x5C 0x60 0x64 0x68 0x6C 0x70 0x74 0x78 0x7C ) group.long ($2+0x1800)++0x3 line.long 0x0 "REGG6_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x20 0x21 0x22 0x23 0x24 0x25 0x26 0x27 0x28 0x29 0x2A 0x2B 0x2C 0x2D 0x2E 0x2F )(list 0x80 0x84 0x88 0x8C 0x90 0x94 0x98 0x9C 0xA0 0xA4 0xA8 0xAC 0xB0 0xB4 0xB8 0xBC ) group.long ($2+0x1800)++0x3 line.long 0x0 "REGG6_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x30 0x31 0x32 0x33 0x34 0x35 0x36 0x37 0x38 0x39 0x3A 0x3B 0x3C 0x3D 0x3E 0x3F )(list 0xC0 0xC4 0xC8 0xCC 0xD0 0xD4 0xD8 0xDC 0xE0 0xE4 0xE8 0xEC 0xF0 0xF4 0xF8 0xFC ) group.long ($2+0x1800)++0x3 line.long 0x0 "REGG6_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x40 0x41 0x42 0x43 0x44 0x45 0x46 0x47 0x48 0x49 0x4A 0x4B 0x4C 0x4D 0x4E 0x4F )(list 0x100 0x104 0x108 0x10C 0x110 0x114 0x118 0x11C 0x120 0x124 0x128 0x12C 0x130 0x134 0x138 0x13C ) group.long ($2+0x1800)++0x3 line.long 0x0 "REGG6_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x50 0x51 0x52 0x53 0x54 0x55 0x56 0x57 0x58 0x59 0x5A 0x5B 0x5C 0x5D 0x5E 0x5F )(list 0x140 0x144 0x148 0x14C 0x150 0x154 0x158 0x15C 0x160 0x164 0x168 0x16C 0x170 0x174 0x178 0x17C ) group.long ($2+0x1800)++0x3 line.long 0x0 "REGG6_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x60 0x61 0x62 0x63 0x64 0x65 0x66 0x67 0x68 0x69 0x6A 0x6B 0x6C 0x6D 0x6E 0x6F )(list 0x180 0x184 0x188 0x18C 0x190 0x194 0x198 0x19C 0x1A0 0x1A4 0x1A8 0x1AC 0x1B0 0x1B4 0x1B8 0x1BC ) group.long ($2+0x1800)++0x3 line.long 0x0 "REGG6_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x70 0x71 0x72 0x73 0x74 0x75 0x76 0x77 0x78 0x79 0x7A 0x7B 0x7C 0x7D 0x7E 0x7F )(list 0x1C0 0x1C4 0x1C8 0x1CC 0x1D0 0x1D4 0x1D8 0x1DC 0x1E0 0x1E4 0x1E8 0x1EC 0x1F0 0x1F4 0x1F8 0x1FC ) group.long ($2+0x1800)++0x3 line.long 0x0 "REGG6_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x80 0x81 0x82 0x83 0x84 0x85 0x86 0x87 0x88 0x89 0x8A 0x8B 0x8C 0x8D 0x8E 0x8F )(list 0x200 0x204 0x208 0x20C 0x210 0x214 0x218 0x21C 0x220 0x224 0x228 0x22C 0x230 0x234 0x238 0x23C ) group.long ($2+0x1800)++0x3 line.long 0x0 "REGG6_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x90 0x91 0x92 0x93 0x94 0x95 0x96 0x97 0x98 0x99 0x9A 0x9B 0x9C 0x9D 0x9E 0x9F )(list 0x240 0x244 0x248 0x24C 0x250 0x254 0x258 0x25C 0x260 0x264 0x268 0x26C 0x270 0x274 0x278 0x27C ) group.long ($2+0x1800)++0x3 line.long 0x0 "REGG6_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xA0 0xA1 0xA2 0xA3 0xA4 0xA5 0xA6 0xA7 0xA8 0xA9 0xAA 0xAB 0xAC 0xAD 0xAE 0xAF )(list 0x280 0x284 0x288 0x28C 0x290 0x294 0x298 0x29C 0x2A0 0x2A4 0x2A8 0x2AC 0x2B0 0x2B4 0x2B8 0x2BC ) group.long ($2+0x1800)++0x3 line.long 0x0 "REGG6_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xB0 0xB1 0xB2 0xB3 0xB4 0xB5 0xB6 0xB7 0xB8 0xB9 0xBA 0xBB 0xBC 0xBD 0xBE 0xBF )(list 0x2C0 0x2C4 0x2C8 0x2CC 0x2D0 0x2D4 0x2D8 0x2DC 0x2E0 0x2E4 0x2E8 0x2EC 0x2F0 0x2F4 0x2F8 0x2FC ) group.long ($2+0x1800)++0x3 line.long 0x0 "REGG6_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xC0 0xC1 0xC2 0xC3 0xC4 0xC5 0xC6 0xC7 0xC8 0xC9 0xCA 0xCB 0xCC 0xCD 0xCE 0xCF )(list 0x300 0x304 0x308 0x30C 0x310 0x314 0x318 0x31C 0x320 0x324 0x328 0x32C 0x330 0x334 0x338 0x33C ) group.long ($2+0x1800)++0x3 line.long 0x0 "REGG6_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xD0 0xD1 0xD2 0xD3 0xD4 0xD5 0xD6 0xD7 0xD8 0xD9 0xDA 0xDB 0xDC 0xDD 0xDE 0xDF )(list 0x340 0x344 0x348 0x34C 0x350 0x354 0x358 0x35C 0x360 0x364 0x368 0x36C 0x370 0x374 0x378 0x37C ) group.long ($2+0x1800)++0x3 line.long 0x0 "REGG6_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xE0 0xE1 0xE2 0xE3 0xE4 0xE5 0xE6 0xE7 0xE8 0xE9 0xEA 0xEB 0xEC 0xED 0xEE 0xEF )(list 0x380 0x384 0x388 0x38C 0x390 0x394 0x398 0x39C 0x3A0 0x3A4 0x3A8 0x3AC 0x3B0 0x3B4 0x3B8 0x3BC ) group.long ($2+0x1800)++0x3 line.long 0x0 "REGG6_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xF0 0xF1 0xF2 0xF3 0xF4 0xF5 0xF6 0xF7 0xF8 0xF9 0xFA 0xFB 0xFC 0xFD 0xFE 0xFF )(list 0x3C0 0x3C4 0x3C8 0x3CC 0x3D0 0x3D4 0x3D8 0x3DC 0x3E0 0x3E4 0x3E8 0x3EC 0x3F0 0x3F4 0x3F8 0x3FC ) group.long ($2+0x1800)++0x3 line.long 0x0 "REGG6_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x4 0x8 0xC 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C ) group.long ($2+0x1C00)++0x3 line.long 0x0 "REGG7_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1A 0x1B 0x1C 0x1D 0x1E 0x1F )(list 0x40 0x44 0x48 0x4C 0x50 0x54 0x58 0x5C 0x60 0x64 0x68 0x6C 0x70 0x74 0x78 0x7C ) group.long ($2+0x1C00)++0x3 line.long 0x0 "REGG7_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x20 0x21 0x22 0x23 0x24 0x25 0x26 0x27 0x28 0x29 0x2A 0x2B 0x2C 0x2D 0x2E 0x2F )(list 0x80 0x84 0x88 0x8C 0x90 0x94 0x98 0x9C 0xA0 0xA4 0xA8 0xAC 0xB0 0xB4 0xB8 0xBC ) group.long ($2+0x1C00)++0x3 line.long 0x0 "REGG7_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x30 0x31 0x32 0x33 0x34 0x35 0x36 0x37 0x38 0x39 0x3A 0x3B 0x3C 0x3D 0x3E 0x3F )(list 0xC0 0xC4 0xC8 0xCC 0xD0 0xD4 0xD8 0xDC 0xE0 0xE4 0xE8 0xEC 0xF0 0xF4 0xF8 0xFC ) group.long ($2+0x1C00)++0x3 line.long 0x0 "REGG7_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x40 0x41 0x42 0x43 0x44 0x45 0x46 0x47 0x48 0x49 0x4A 0x4B 0x4C 0x4D 0x4E 0x4F )(list 0x100 0x104 0x108 0x10C 0x110 0x114 0x118 0x11C 0x120 0x124 0x128 0x12C 0x130 0x134 0x138 0x13C ) group.long ($2+0x1C00)++0x3 line.long 0x0 "REGG7_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x50 0x51 0x52 0x53 0x54 0x55 0x56 0x57 0x58 0x59 0x5A 0x5B 0x5C 0x5D 0x5E 0x5F )(list 0x140 0x144 0x148 0x14C 0x150 0x154 0x158 0x15C 0x160 0x164 0x168 0x16C 0x170 0x174 0x178 0x17C ) group.long ($2+0x1C00)++0x3 line.long 0x0 "REGG7_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x60 0x61 0x62 0x63 0x64 0x65 0x66 0x67 0x68 0x69 0x6A 0x6B 0x6C 0x6D 0x6E 0x6F )(list 0x180 0x184 0x188 0x18C 0x190 0x194 0x198 0x19C 0x1A0 0x1A4 0x1A8 0x1AC 0x1B0 0x1B4 0x1B8 0x1BC ) group.long ($2+0x1C00)++0x3 line.long 0x0 "REGG7_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x70 0x71 0x72 0x73 0x74 0x75 0x76 0x77 0x78 0x79 0x7A 0x7B 0x7C 0x7D 0x7E 0x7F )(list 0x1C0 0x1C4 0x1C8 0x1CC 0x1D0 0x1D4 0x1D8 0x1DC 0x1E0 0x1E4 0x1E8 0x1EC 0x1F0 0x1F4 0x1F8 0x1FC ) group.long ($2+0x1C00)++0x3 line.long 0x0 "REGG7_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x80 0x81 0x82 0x83 0x84 0x85 0x86 0x87 0x88 0x89 0x8A 0x8B 0x8C 0x8D 0x8E 0x8F )(list 0x200 0x204 0x208 0x20C 0x210 0x214 0x218 0x21C 0x220 0x224 0x228 0x22C 0x230 0x234 0x238 0x23C ) group.long ($2+0x1C00)++0x3 line.long 0x0 "REGG7_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x90 0x91 0x92 0x93 0x94 0x95 0x96 0x97 0x98 0x99 0x9A 0x9B 0x9C 0x9D 0x9E 0x9F )(list 0x240 0x244 0x248 0x24C 0x250 0x254 0x258 0x25C 0x260 0x264 0x268 0x26C 0x270 0x274 0x278 0x27C ) group.long ($2+0x1C00)++0x3 line.long 0x0 "REGG7_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xA0 0xA1 0xA2 0xA3 0xA4 0xA5 0xA6 0xA7 0xA8 0xA9 0xAA 0xAB 0xAC 0xAD 0xAE 0xAF )(list 0x280 0x284 0x288 0x28C 0x290 0x294 0x298 0x29C 0x2A0 0x2A4 0x2A8 0x2AC 0x2B0 0x2B4 0x2B8 0x2BC ) group.long ($2+0x1C00)++0x3 line.long 0x0 "REGG7_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xB0 0xB1 0xB2 0xB3 0xB4 0xB5 0xB6 0xB7 0xB8 0xB9 0xBA 0xBB 0xBC 0xBD 0xBE 0xBF )(list 0x2C0 0x2C4 0x2C8 0x2CC 0x2D0 0x2D4 0x2D8 0x2DC 0x2E0 0x2E4 0x2E8 0x2EC 0x2F0 0x2F4 0x2F8 0x2FC ) group.long ($2+0x1C00)++0x3 line.long 0x0 "REGG7_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xC0 0xC1 0xC2 0xC3 0xC4 0xC5 0xC6 0xC7 0xC8 0xC9 0xCA 0xCB 0xCC 0xCD 0xCE 0xCF )(list 0x300 0x304 0x308 0x30C 0x310 0x314 0x318 0x31C 0x320 0x324 0x328 0x32C 0x330 0x334 0x338 0x33C ) group.long ($2+0x1C00)++0x3 line.long 0x0 "REGG7_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xD0 0xD1 0xD2 0xD3 0xD4 0xD5 0xD6 0xD7 0xD8 0xD9 0xDA 0xDB 0xDC 0xDD 0xDE 0xDF )(list 0x340 0x344 0x348 0x34C 0x350 0x354 0x358 0x35C 0x360 0x364 0x368 0x36C 0x370 0x374 0x378 0x37C ) group.long ($2+0x1C00)++0x3 line.long 0x0 "REGG7_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xE0 0xE1 0xE2 0xE3 0xE4 0xE5 0xE6 0xE7 0xE8 0xE9 0xEA 0xEB 0xEC 0xED 0xEE 0xEF )(list 0x380 0x384 0x388 0x38C 0x390 0x394 0x398 0x39C 0x3A0 0x3A4 0x3A8 0x3AC 0x3B0 0x3B4 0x3B8 0x3BC ) group.long ($2+0x1C00)++0x3 line.long 0x0 "REGG7_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xF0 0xF1 0xF2 0xF3 0xF4 0xF5 0xF6 0xF7 0xF8 0xF9 0xFA 0xFB 0xFC 0xFD 0xFE 0xFF )(list 0x3C0 0x3C4 0x3C8 0x3CC 0x3D0 0x3D4 0x3D8 0x3DC 0x3E0 0x3E4 0x3E8 0x3EC 0x3F0 0x3F4 0x3F8 0x3FC ) group.long ($2+0x1C00)++0x3 line.long 0x0 "REGG7_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end group.long 0x2000++0x17 line.long 0x0 "GLB_CTL,This register provides global enable settings for permission control." bitfld.long 0x0 5. "DOM_CFG_LOCK,Lock write for DOM_CFG_MODE bit." "0,1" bitfld.long 0x0 4. "DOM_CFG_MODE,When enabled all the source setting can be configured by master from domain 0 if it is not locked. When disabled only resource manager can configure the permission of the resource." "0,1" bitfld.long 0x0 3. "PERCK_DIS_LOCK,Lock write for PERCK_DIS" "0,1" bitfld.long 0x0 2. "PERCK_DIS,All the permission check disable." "0,1" newline bitfld.long 0x0 1. "DOM_PRO_LOCK,Lock write for DOM_PRO_EN bit." "0,1" bitfld.long 0x0 0. "DOM_PRO_EN,When disabled no domain access permission check" "0,1" line.long 0x4 "RES_MGR,Resource manager register. This regster is used to assign resource manager for global resource access control" bitfld.long 0x4 17. "MID_LOCK,Lock write for MID_EN and MID_LOW and MID_HIG registers." "0,1" bitfld.long 0x4 16. "MID_EN,Master ID check enable" "0,1" bitfld.long 0x4 15. "PRI_PER_LOCK,Lock write for PRI_PER and PRI_PER_EN" "0,1" bitfld.long 0x4 13.--14. "PRI_PER,Resource manager privileged access permission. bit0 for privileged access bit1 for user access" "0,1,2,3" newline bitfld.long 0x4 12. "PRI_PER_EN,Resource manager privileged access permission enable." "0,1" bitfld.long 0x4 11. "SEC_PER_LOCK,Lock for SEC_PER and SEC_PER_LOCK" "0,1" bitfld.long 0x4 9.--10. "SEC_PER,Resource manager secure access permission. bit 0 for secure access bit 1 for non-secure access" "0,1,2,3" bitfld.long 0x4 8. "SEC_PER_EN,Resource manager secure permission enable" "0,1" bitfld.long 0x4 7. "DID_LOCK,Lock write for DID_EN and DID" "0,1" newline hexmask.long.byte 0x4 3.--6. 1. "DID,Resource manager domain ID" bitfld.long 0x4 2. "DID_EN,Resource manager Domain ID enable" "0,1" bitfld.long 0x4 1. "RES_MGR_EN_LOCK,Lock for RES_MGR_EN" "0,1" bitfld.long 0x4 0. "RES_MGR_EN,Resource manager enable. When the bit is disable there is no resource manager." "0,1" line.long 0x8 "RES_MGR_MA0,This register is used to assign master 0~31 as resource manager." hexmask.long 0x8 0.--31. 1. "MID,Assign master 0~31 for resource manager" line.long 0xC "RES_MGR_MA1,This register is used to assign master 32~63 as resource manager." hexmask.long 0xC 0.--31. 1. "MID,Indicate if master 32~63 is resource manager." line.long 0x10 "RES_MGR_MA2,This register is used to assign master 64~95 as resource manager." hexmask.long 0x10 0.--31. 1. "MID,Indicate if master 64~95 is resource manager." line.long 0x14 "RES_MGR_MA3,This register is used to assign master 96~127 as resource manager." hexmask.long 0x14 0.--31. 1. "MID,Indicate if master 96~127 is resource manager." repeat 8. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 )(list 0x0 0x14 0x28 0x3C 0x50 0x64 0x78 0x8C ) group.long ($2+0x2100)++0x3 line.long 0x0 "GRP_MGR_$1,Group Manager Register. This register is used to assign group manager for each domain" bitfld.long 0x0 17. "MID_LOCK,Lock write for MID_EN and MID_LOW and MID_HIG registers." "0,1" bitfld.long 0x0 16. "MID_EN,Master ID check enable" "0,1" bitfld.long 0x0 15. "PRI_PER_LOCK,Lock write for PRI_PER and PRI_PER_EN" "0,1" bitfld.long 0x0 13.--14. "PRI_PER,Group manager privileged access permission. bit0 for privileged access bit1 for user access" "0,1,2,3" newline bitfld.long 0x0 12. "PRI_PER_EN,Group manager privileged access permission enable." "0,1" bitfld.long 0x0 11. "SEC_PER_LOCK,Lock for SEC_PER and SEC_PER_LOCK" "0,1" bitfld.long 0x0 9.--10. "SEC_PER,Group manager secure access permission. bit 0 for secure access bit 1 for non-secure access" "0,1,2,3" bitfld.long 0x0 8. "SEC_PER_EN,Group manager secure permission enable" "0,1" bitfld.long 0x0 7. "DID_LOCK,Lock write for DID_EN and DID" "0,1" newline hexmask.long.byte 0x0 3.--6. 1. "DID,Group manager domain ID" bitfld.long 0x0 2. "DID_EN,Group manager Domain ID enable" "0,1" bitfld.long 0x0 1. "GRP_MGR_EN_LOCK,Lock write for GPR_MGR_EN" "0,1" bitfld.long 0x0 0. "GRP_MGR_EN,Group manager enable. When the bit is disable there is no resource manager." "0,1" repeat.end repeat 8. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 )(list 0x0 0x14 0x28 0x3C 0x50 0x64 0x78 0x8C ) group.long ($2+0x2104)++0x3 line.long 0x0 "GRP_MGR_MA0_$1,Assign master 0~31 for group manager 0" hexmask.long 0x0 0.--31. 1. "MID,Assign master 0~31 for resource manager" repeat.end repeat 8. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 )(list 0x0 0x14 0x28 0x3C 0x50 0x64 0x78 0x8C ) group.long ($2+0x2108)++0x3 line.long 0x0 "GRP_MGR_MA1_$1,Assign master 32~63 for group manager 0" hexmask.long 0x0 0.--31. 1. "MID,Indicate if master 32~63 is resource manager." repeat.end repeat 8. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 )(list 0x0 0x14 0x28 0x3C 0x50 0x64 0x78 0x8C ) group.long ($2+0x210C)++0x3 line.long 0x0 "GRP_MGR_MA2_$1,Assign master 64~95 for group manager 0" hexmask.long 0x0 0.--31. 1. "MID,Indicate if master 64~95 is resource manager." repeat.end repeat 8. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 )(list 0x0 0x14 0x28 0x3C 0x50 0x64 0x78 0x8C ) group.long ($2+0x2110)++0x3 line.long 0x0 "GRP_MGR_MA3_$1,Assign master 96~127 for group manager 0" hexmask.long 0x0 0.--31. 1. "MID,Indicate if master 96~127 is resource manager." repeat.end group.long 0x2200++0x3 line.long 0x0 "DOM_GID_0,Indicate which group domain 0 belong to" bitfld.long 0x0 3. "LOCK,Lock write for GID" "0,1" bitfld.long 0x0 0.--2. "GID,Group ID" "0,1,2,3,4,5,6,7" repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x18 0x30 0x48 0x60 0x78 0x90 0xA8 0xC0 0xD8 0xF0 0x108 0x120 0x138 0x150 0x168 ) group.long ($2+0x2204)++0x3 line.long 0x0 "DOM_OWN_$1,Assign owner for function domain 0." bitfld.long 0x0 17. "MID_LOCK,Lock write for MID_EN and MID_LOW and MID_HIG registers." "0,1" bitfld.long 0x0 16. "MID_EN,Master ID check enable" "0,1" bitfld.long 0x0 15. "PRI_PER_LOCK,Lock write for PRI_PER and PRI_PER_EN" "0,1" bitfld.long 0x0 13.--14. "PRI_PER,Group manager privileged access permission. bit0 for privileged access bit1 for user access" "0,1,2,3" newline bitfld.long 0x0 12. "PRI_PER_EN,Group manager privileged access permission enable." "0,1" bitfld.long 0x0 11. "SEC_PER_LOCK,Lock for SEC_PER and SEC_PER_LOCK" "0,1" bitfld.long 0x0 9.--10. "SEC_PER,Domain owner secure access permission. bit 0 for secure access bit 1 for non-secure access" "0,1,2,3" bitfld.long 0x0 8. "SEC_PER_EN,Domain owner secure permission enable" "0,1" newline bitfld.long 0x0 1. "DOM_OWN_EN_LOCK,Lock for DOM_OWN_EN" "0,1" bitfld.long 0x0 0. "DOM_OWN_EN,Domain owner enable. When the bit is disable there is no domain owner." "0,1" repeat.end repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x18 0x30 0x48 0x60 0x78 0x90 0xA8 0xC0 0xD8 0xF0 0x108 0x120 0x138 0x150 0x168 ) group.long ($2+0x2208)++0x3 line.long 0x0 "DOM_OWN_MA0_$1,Assign master 0~31 for domain owner 0" hexmask.long 0x0 0.--31. 1. "MID,Assign master 0~31 for resource manager" repeat.end repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x18 0x30 0x48 0x60 0x78 0x90 0xA8 0xC0 0xD8 0xF0 0x108 0x120 0x138 0x150 0x168 ) group.long ($2+0x220C)++0x3 line.long 0x0 "DOM_OWN_MA1_$1,Assign master 32~63 for domain owner 0" hexmask.long 0x0 0.--31. 1. "MID,Indicate if master 32~63 is resource manager." repeat.end repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x18 0x30 0x48 0x60 0x78 0x90 0xA8 0xC0 0xD8 0xF0 0x108 0x120 0x138 0x150 0x168 ) group.long ($2+0x2210)++0x3 line.long 0x0 "DOM_OWN_MA2_$1,Assign master 64~95 for domain owner 0" hexmask.long 0x0 0.--31. 1. "MID,Indicate if master 64~95 is resource manager." repeat.end repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x18 0x30 0x48 0x60 0x78 0x90 0xA8 0xC0 0xD8 0xF0 0x108 0x120 0x138 0x150 0x168 ) group.long ($2+0x2214)++0x3 line.long 0x0 "DOM_OWN_MA3_$1,Assign master 96~127 for domain owner 0" hexmask.long 0x0 0.--31. 1. "MID,Indicate if master 96~127 is resource manager." repeat.end group.long 0x2218++0x3 line.long 0x0 "DOM_GID_1,Indicate which group domain 1 belong to" bitfld.long 0x0 3. "LOCK,Lock write for GID" "0,1" bitfld.long 0x0 0.--2. "GID,Group ID" "0,1,2,3,4,5,6,7" group.long 0x2230++0x3 line.long 0x0 "DOM_GID_2,Indicate which group domain 2 belong to" bitfld.long 0x0 3. "LOCK,Lock write for GID" "0,1" bitfld.long 0x0 0.--2. "GID,Group ID" "0,1,2,3,4,5,6,7" group.long 0x2248++0x3 line.long 0x0 "DOM_GID_3,Indicate which group domain 3 belong to" bitfld.long 0x0 3. "LOCK,Lock write for GID" "0,1" bitfld.long 0x0 0.--2. "GID,Group ID" "0,1,2,3,4,5,6,7" group.long 0x2260++0x3 line.long 0x0 "DOM_GID_4,Indicate which group domain 4 belong to" bitfld.long 0x0 3. "LOCK,Lock write for GID" "0,1" bitfld.long 0x0 0.--2. "GID,Group ID" "0,1,2,3,4,5,6,7" group.long 0x2278++0x3 line.long 0x0 "DOM_GID_5,Indicate which group domain 5 belong to" bitfld.long 0x0 3. "LOCK,Lock write for GID" "0,1" bitfld.long 0x0 0.--2. "GID,Group ID" "0,1,2,3,4,5,6,7" group.long 0x2290++0x3 line.long 0x0 "DOM_GID_6,Indicate which group domain 6 belong to" bitfld.long 0x0 3. "LOCK,Lock write for GID" "0,1" bitfld.long 0x0 0.--2. "GID,Group ID" "0,1,2,3,4,5,6,7" group.long 0x22A8++0x3 line.long 0x0 "DOM_GID_7,Indicate which group domain 7 belong to" bitfld.long 0x0 3. "LOCK,Lock write for GID" "0,1" bitfld.long 0x0 0.--2. "GID,Group ID" "0,1,2,3,4,5,6,7" group.long 0x22C0++0x3 line.long 0x0 "DOM_GID_8,Indicate which group domain 8 belong to" bitfld.long 0x0 3. "LOCK,Lock write for GID" "0,1" bitfld.long 0x0 0.--2. "GID,Group ID" "0,1,2,3,4,5,6,7" group.long 0x22D8++0x3 line.long 0x0 "DOM_GID_9,Indicate which group domain 9 belong to" bitfld.long 0x0 3. "LOCK,Lock write for GID" "0,1" bitfld.long 0x0 0.--2. "GID,Group ID" "0,1,2,3,4,5,6,7" group.long 0x22F0++0x3 line.long 0x0 "DOM_GID_10,Indicate which group domain 10 belong to" bitfld.long 0x0 3. "LOCK,Lock write for GID" "0,1" bitfld.long 0x0 0.--2. "GID,Group ID" "0,1,2,3,4,5,6,7" group.long 0x2308++0x3 line.long 0x0 "DOM_GID_11,Indicate which group domain 11 belong to" bitfld.long 0x0 3. "LOCK,Lock write for GID" "0,1" bitfld.long 0x0 0.--2. "GID,Group ID" "0,1,2,3,4,5,6,7" group.long 0x2320++0x3 line.long 0x0 "DOM_GID_12,Indicate which group domain 12 belong to" bitfld.long 0x0 3. "LOCK,Lock write for GID" "0,1" bitfld.long 0x0 0.--2. "GID,Group ID" "0,1,2,3,4,5,6,7" group.long 0x2338++0x3 line.long 0x0 "DOM_GID_13,Indicate which group domain 13 belong to" bitfld.long 0x0 3. "LOCK,Lock write for GID" "0,1" bitfld.long 0x0 0.--2. "GID,Group ID" "0,1,2,3,4,5,6,7" group.long 0x2350++0x3 line.long 0x0 "DOM_GID_14,Indicate which group domain 14 belong to" bitfld.long 0x0 3. "LOCK,Lock write for GID" "0,1" bitfld.long 0x0 0.--2. "GID,Group ID" "0,1,2,3,4,5,6,7" group.long 0x2368++0x3 line.long 0x0 "DOM_GID_15,Indicate which group domain 15 belong to" bitfld.long 0x0 3. "LOCK,Lock write for GID" "0,1" bitfld.long 0x0 0.--2. "GID,Group ID" "0,1,2,3,4,5,6,7" repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x34 0x68 0x9C 0xD0 0x104 0x138 0x16C 0x1A0 0x1D4 0x208 0x23C 0x270 0x2A4 0x2D8 0x30C ) group.long ($2+0x2400)++0x3 line.long 0x0 "DOM_PER0_$1,Domain Permission Control. It can be only configured by resource manager and domain owner." bitfld.long 0x0 31. "DOM7_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 29.--30. "DOM7_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 28. "DOM7_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 27. "DOM6_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 25.--26. "DOM6_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" newline bitfld.long 0x0 24. "DOM6_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 23. "DOM5_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 21.--22. "DOM5_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 20. "DOM5_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 19. "DOM4_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" newline bitfld.long 0x0 17.--18. "DOM4_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM4_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 15. "DOM3_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 13.--14. "DOM3_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 12. "DOM3_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" newline bitfld.long 0x0 11. "DOM2_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 9.--10. "DOM2_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM2_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 7. "DOM1_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 5.--6. "DOM1_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" newline bitfld.long 0x0 4. "DOM1_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 3. "DOM0_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 1.--2. "DOM0_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM0_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" repeat.end repeat 16. (list 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1A 0x1B 0x1C 0x1D 0x1E 0x1F )(list 0x340 0x374 0x3A8 0x3DC 0x410 0x444 0x478 0x4AC 0x4E0 0x514 0x548 0x57C 0x5B0 0x5E4 0x618 0x64C ) group.long ($2+0x2400)++0x3 line.long 0x0 "DOM_PER0_$1,Domain Permission Control. It can be only configured by resource manager and domain owner." bitfld.long 0x0 31. "DOM7_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 29.--30. "DOM7_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 28. "DOM7_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 27. "DOM6_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 25.--26. "DOM6_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" newline bitfld.long 0x0 24. "DOM6_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 23. "DOM5_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 21.--22. "DOM5_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 20. "DOM5_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 19. "DOM4_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" newline bitfld.long 0x0 17.--18. "DOM4_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM4_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 15. "DOM3_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 13.--14. "DOM3_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 12. "DOM3_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" newline bitfld.long 0x0 11. "DOM2_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 9.--10. "DOM2_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM2_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 7. "DOM1_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 5.--6. "DOM1_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" newline bitfld.long 0x0 4. "DOM1_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 3. "DOM0_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 1.--2. "DOM0_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM0_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" repeat.end repeat 16. (list 0x20 0x21 0x22 0x23 0x24 0x25 0x26 0x27 0x28 0x29 0x2A 0x2B 0x2C 0x2D 0x2E 0x2F )(list 0x680 0x6B4 0x6E8 0x71C 0x750 0x784 0x7B8 0x7EC 0x820 0x854 0x888 0x8BC 0x8F0 0x924 0x958 0x98C ) group.long ($2+0x2400)++0x3 line.long 0x0 "DOM_PER0_$1,Domain Permission Control. It can be only configured by resource manager and domain owner." bitfld.long 0x0 31. "DOM7_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 29.--30. "DOM7_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 28. "DOM7_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 27. "DOM6_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 25.--26. "DOM6_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" newline bitfld.long 0x0 24. "DOM6_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 23. "DOM5_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 21.--22. "DOM5_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 20. "DOM5_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 19. "DOM4_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" newline bitfld.long 0x0 17.--18. "DOM4_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM4_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 15. "DOM3_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 13.--14. "DOM3_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 12. "DOM3_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" newline bitfld.long 0x0 11. "DOM2_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 9.--10. "DOM2_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM2_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 7. "DOM1_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 5.--6. "DOM1_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" newline bitfld.long 0x0 4. "DOM1_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 3. "DOM0_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 1.--2. "DOM0_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM0_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" repeat.end repeat 16. (list 0x30 0x31 0x32 0x33 0x34 0x35 0x36 0x37 0x38 0x39 0x3A 0x3B 0x3C 0x3D 0x3E 0x3F )(list 0x9C0 0x9F4 0xA28 0xA5C 0xA90 0xAC4 0xAF8 0xB2C 0xB60 0xB94 0xBC8 0xBFC 0xC30 0xC64 0xC98 0xCCC ) group.long ($2+0x2400)++0x3 line.long 0x0 "DOM_PER0_$1,Domain Permission Control. It can be only configured by resource manager and domain owner." bitfld.long 0x0 31. "DOM7_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 29.--30. "DOM7_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 28. "DOM7_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 27. "DOM6_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 25.--26. "DOM6_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" newline bitfld.long 0x0 24. "DOM6_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 23. "DOM5_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 21.--22. "DOM5_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 20. "DOM5_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 19. "DOM4_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" newline bitfld.long 0x0 17.--18. "DOM4_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM4_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 15. "DOM3_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 13.--14. "DOM3_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 12. "DOM3_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" newline bitfld.long 0x0 11. "DOM2_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 9.--10. "DOM2_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM2_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 7. "DOM1_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 5.--6. "DOM1_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" newline bitfld.long 0x0 4. "DOM1_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 3. "DOM0_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 1.--2. "DOM0_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM0_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" repeat.end repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x34 0x68 0x9C 0xD0 0x104 0x138 0x16C 0x1A0 0x1D4 0x208 0x23C 0x270 0x2A4 0x2D8 0x30C ) group.long ($2+0x2404)++0x3 line.long 0x0 "DOM_PER1_$1,Domain Permission Control. It can be only configured by resource manager and domain owner." bitfld.long 0x0 31. "DOM15_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 29.--30. "DOM15_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 28. "DOM15_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 27. "DOM14_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 25.--26. "DOM14_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" newline bitfld.long 0x0 24. "DOM14_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 23. "DOM13_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 21.--22. "DOM13_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 20. "DOM13_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 19. "DOM12_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" newline bitfld.long 0x0 17.--18. "DOM12_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM12_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 15. "DOM11_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 13.--14. "DOM11_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 12. "DOM11_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" newline bitfld.long 0x0 11. "DOM10_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 9.--10. "DOM10_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM10_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 7. "DOM9_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 5.--6. "DOM9_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" newline bitfld.long 0x0 4. "DOM9_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 3. "DOM8_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 1.--2. "DOM8_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM8_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" repeat.end repeat 16. (list 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1A 0x1B 0x1C 0x1D 0x1E 0x1F )(list 0x340 0x374 0x3A8 0x3DC 0x410 0x444 0x478 0x4AC 0x4E0 0x514 0x548 0x57C 0x5B0 0x5E4 0x618 0x64C ) group.long ($2+0x2404)++0x3 line.long 0x0 "DOM_PER1_$1,Domain Permission Control. It can be only configured by resource manager and domain owner." bitfld.long 0x0 31. "DOM15_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 29.--30. "DOM15_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 28. "DOM15_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 27. "DOM14_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 25.--26. "DOM14_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" newline bitfld.long 0x0 24. "DOM14_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 23. "DOM13_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 21.--22. "DOM13_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 20. "DOM13_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 19. "DOM12_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" newline bitfld.long 0x0 17.--18. "DOM12_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM12_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 15. "DOM11_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 13.--14. "DOM11_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 12. "DOM11_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" newline bitfld.long 0x0 11. "DOM10_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 9.--10. "DOM10_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM10_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 7. "DOM9_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 5.--6. "DOM9_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" newline bitfld.long 0x0 4. "DOM9_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 3. "DOM8_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 1.--2. "DOM8_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM8_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" repeat.end repeat 16. (list 0x20 0x21 0x22 0x23 0x24 0x25 0x26 0x27 0x28 0x29 0x2A 0x2B 0x2C 0x2D 0x2E 0x2F )(list 0x680 0x6B4 0x6E8 0x71C 0x750 0x784 0x7B8 0x7EC 0x820 0x854 0x888 0x8BC 0x8F0 0x924 0x958 0x98C ) group.long ($2+0x2404)++0x3 line.long 0x0 "DOM_PER1_$1,Domain Permission Control. It can be only configured by resource manager and domain owner." bitfld.long 0x0 31. "DOM15_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 29.--30. "DOM15_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 28. "DOM15_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 27. "DOM14_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 25.--26. "DOM14_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" newline bitfld.long 0x0 24. "DOM14_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 23. "DOM13_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 21.--22. "DOM13_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 20. "DOM13_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 19. "DOM12_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" newline bitfld.long 0x0 17.--18. "DOM12_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM12_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 15. "DOM11_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 13.--14. "DOM11_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 12. "DOM11_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" newline bitfld.long 0x0 11. "DOM10_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 9.--10. "DOM10_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM10_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 7. "DOM9_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 5.--6. "DOM9_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" newline bitfld.long 0x0 4. "DOM9_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 3. "DOM8_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 1.--2. "DOM8_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM8_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" repeat.end repeat 16. (list 0x30 0x31 0x32 0x33 0x34 0x35 0x36 0x37 0x38 0x39 0x3A 0x3B 0x3C 0x3D 0x3E 0x3F )(list 0x9C0 0x9F4 0xA28 0xA5C 0xA90 0xAC4 0xAF8 0xB2C 0xB60 0xB94 0xBC8 0xBFC 0xC30 0xC64 0xC98 0xCCC ) group.long ($2+0x2404)++0x3 line.long 0x0 "DOM_PER1_$1,Domain Permission Control. It can be only configured by resource manager and domain owner." bitfld.long 0x0 31. "DOM15_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 29.--30. "DOM15_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 28. "DOM15_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 27. "DOM14_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 25.--26. "DOM14_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" newline bitfld.long 0x0 24. "DOM14_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 23. "DOM13_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 21.--22. "DOM13_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 20. "DOM13_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 19. "DOM12_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" newline bitfld.long 0x0 17.--18. "DOM12_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM12_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 15. "DOM11_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 13.--14. "DOM11_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 12. "DOM11_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" newline bitfld.long 0x0 11. "DOM10_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 9.--10. "DOM10_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM10_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 7. "DOM9_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 5.--6. "DOM9_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" newline bitfld.long 0x0 4. "DOM9_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 3. "DOM8_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 1.--2. "DOM8_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM8_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" repeat.end repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x34 0x68 0x9C 0xD0 0x104 0x138 0x16C 0x1A0 0x1D4 0x208 0x23C 0x270 0x2A4 0x2D8 0x30C ) group.long ($2+0x2408)++0x3 line.long 0x0 "SEC_PER0_$1,This register is only used for resource manager to control secure access permission." bitfld.long 0x0 31. "DOM3_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM3_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM3_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM3_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM2_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM2_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM2_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM2_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM1_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM1_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM1_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM1_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM0_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM0_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM0_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM0_SEC_EN,Domain secure permission control enable" "0,1" repeat.end repeat 16. (list 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1A 0x1B 0x1C 0x1D 0x1E 0x1F )(list 0x340 0x374 0x3A8 0x3DC 0x410 0x444 0x478 0x4AC 0x4E0 0x514 0x548 0x57C 0x5B0 0x5E4 0x618 0x64C ) group.long ($2+0x2408)++0x3 line.long 0x0 "SEC_PER0_$1,This register is only used for resource manager to control secure access permission." bitfld.long 0x0 31. "DOM3_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM3_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM3_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM3_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM2_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM2_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM2_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM2_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM1_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM1_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM1_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM1_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM0_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM0_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM0_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM0_SEC_EN,Domain secure permission control enable" "0,1" repeat.end repeat 16. (list 0x20 0x21 0x22 0x23 0x24 0x25 0x26 0x27 0x28 0x29 0x2A 0x2B 0x2C 0x2D 0x2E 0x2F )(list 0x680 0x6B4 0x6E8 0x71C 0x750 0x784 0x7B8 0x7EC 0x820 0x854 0x888 0x8BC 0x8F0 0x924 0x958 0x98C ) group.long ($2+0x2408)++0x3 line.long 0x0 "SEC_PER0_$1,This register is only used for resource manager to control secure access permission." bitfld.long 0x0 31. "DOM3_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM3_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM3_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM3_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM2_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM2_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM2_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM2_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM1_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM1_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM1_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM1_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM0_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM0_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM0_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM0_SEC_EN,Domain secure permission control enable" "0,1" repeat.end repeat 16. (list 0x30 0x31 0x32 0x33 0x34 0x35 0x36 0x37 0x38 0x39 0x3A 0x3B 0x3C 0x3D 0x3E 0x3F )(list 0x9C0 0x9F4 0xA28 0xA5C 0xA90 0xAC4 0xAF8 0xB2C 0xB60 0xB94 0xBC8 0xBFC 0xC30 0xC64 0xC98 0xCCC ) group.long ($2+0x2408)++0x3 line.long 0x0 "SEC_PER0_$1,This register is only used for resource manager to control secure access permission." bitfld.long 0x0 31. "DOM3_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM3_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM3_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM3_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM2_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM2_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM2_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM2_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM1_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM1_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM1_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM1_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM0_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM0_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM0_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM0_SEC_EN,Domain secure permission control enable" "0,1" repeat.end repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x34 0x68 0x9C 0xD0 0x104 0x138 0x16C 0x1A0 0x1D4 0x208 0x23C 0x270 0x2A4 0x2D8 0x30C ) group.long ($2+0x240C)++0x3 line.long 0x0 "SEC_PER1_$1,This register is only used for resource manager to control secure access permission." bitfld.long 0x0 31. "DOM7_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM7_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM7_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM7_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM6_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM6_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM6_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM6_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM5_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM5_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM5_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM5_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM4_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM4_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM4_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM4_SEC_EN,Domain secure permission control enable" "0,1" repeat.end repeat 16. (list 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1A 0x1B 0x1C 0x1D 0x1E 0x1F )(list 0x340 0x374 0x3A8 0x3DC 0x410 0x444 0x478 0x4AC 0x4E0 0x514 0x548 0x57C 0x5B0 0x5E4 0x618 0x64C ) group.long ($2+0x240C)++0x3 line.long 0x0 "SEC_PER1_$1,This register is only used for resource manager to control secure access permission." bitfld.long 0x0 31. "DOM7_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM7_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM7_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM7_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM6_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM6_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM6_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM6_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM5_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM5_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM5_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM5_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM4_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM4_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM4_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM4_SEC_EN,Domain secure permission control enable" "0,1" repeat.end repeat 16. (list 0x20 0x21 0x22 0x23 0x24 0x25 0x26 0x27 0x28 0x29 0x2A 0x2B 0x2C 0x2D 0x2E 0x2F )(list 0x680 0x6B4 0x6E8 0x71C 0x750 0x784 0x7B8 0x7EC 0x820 0x854 0x888 0x8BC 0x8F0 0x924 0x958 0x98C ) group.long ($2+0x240C)++0x3 line.long 0x0 "SEC_PER1_$1,This register is only used for resource manager to control secure access permission." bitfld.long 0x0 31. "DOM7_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM7_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM7_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM7_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM6_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM6_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM6_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM6_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM5_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM5_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM5_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM5_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM4_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM4_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM4_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM4_SEC_EN,Domain secure permission control enable" "0,1" repeat.end repeat 16. (list 0x30 0x31 0x32 0x33 0x34 0x35 0x36 0x37 0x38 0x39 0x3A 0x3B 0x3C 0x3D 0x3E 0x3F )(list 0x9C0 0x9F4 0xA28 0xA5C 0xA90 0xAC4 0xAF8 0xB2C 0xB60 0xB94 0xBC8 0xBFC 0xC30 0xC64 0xC98 0xCCC ) group.long ($2+0x240C)++0x3 line.long 0x0 "SEC_PER1_$1,This register is only used for resource manager to control secure access permission." bitfld.long 0x0 31. "DOM7_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM7_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM7_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM7_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM6_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM6_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM6_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM6_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM5_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM5_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM5_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM5_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM4_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM4_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM4_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM4_SEC_EN,Domain secure permission control enable" "0,1" repeat.end repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x34 0x68 0x9C 0xD0 0x104 0x138 0x16C 0x1A0 0x1D4 0x208 0x23C 0x270 0x2A4 0x2D8 0x30C ) group.long ($2+0x2410)++0x3 line.long 0x0 "SEC_PER2_$1,This register is only used for resource manager to control secure access permission." bitfld.long 0x0 31. "DOM11_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM11_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM11_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM11_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM10_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM10_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM10_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM10_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM9_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM9_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM9_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM9_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM8_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM8_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM8_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM8_SEC_EN,Domain secure permission control enable" "0,1" repeat.end repeat 16. (list 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1A 0x1B 0x1C 0x1D 0x1E 0x1F )(list 0x340 0x374 0x3A8 0x3DC 0x410 0x444 0x478 0x4AC 0x4E0 0x514 0x548 0x57C 0x5B0 0x5E4 0x618 0x64C ) group.long ($2+0x2410)++0x3 line.long 0x0 "SEC_PER2_$1,This register is only used for resource manager to control secure access permission." bitfld.long 0x0 31. "DOM11_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM11_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM11_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM11_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM10_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM10_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM10_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM10_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM9_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM9_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM9_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM9_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM8_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM8_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM8_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM8_SEC_EN,Domain secure permission control enable" "0,1" repeat.end repeat 16. (list 0x20 0x21 0x22 0x23 0x24 0x25 0x26 0x27 0x28 0x29 0x2A 0x2B 0x2C 0x2D 0x2E 0x2F )(list 0x680 0x6B4 0x6E8 0x71C 0x750 0x784 0x7B8 0x7EC 0x820 0x854 0x888 0x8BC 0x8F0 0x924 0x958 0x98C ) group.long ($2+0x2410)++0x3 line.long 0x0 "SEC_PER2_$1,This register is only used for resource manager to control secure access permission." bitfld.long 0x0 31. "DOM11_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM11_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM11_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM11_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM10_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM10_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM10_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM10_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM9_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM9_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM9_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM9_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM8_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM8_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM8_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM8_SEC_EN,Domain secure permission control enable" "0,1" repeat.end repeat 16. (list 0x30 0x31 0x32 0x33 0x34 0x35 0x36 0x37 0x38 0x39 0x3A 0x3B 0x3C 0x3D 0x3E 0x3F )(list 0x9C0 0x9F4 0xA28 0xA5C 0xA90 0xAC4 0xAF8 0xB2C 0xB60 0xB94 0xBC8 0xBFC 0xC30 0xC64 0xC98 0xCCC ) group.long ($2+0x2410)++0x3 line.long 0x0 "SEC_PER2_$1,This register is only used for resource manager to control secure access permission." bitfld.long 0x0 31. "DOM11_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM11_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM11_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM11_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM10_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM10_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM10_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM10_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM9_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM9_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM9_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM9_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM8_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM8_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM8_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM8_SEC_EN,Domain secure permission control enable" "0,1" repeat.end repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x34 0x68 0x9C 0xD0 0x104 0x138 0x16C 0x1A0 0x1D4 0x208 0x23C 0x270 0x2A4 0x2D8 0x30C ) group.long ($2+0x2414)++0x3 line.long 0x0 "SEC_PER3_$1,This register is only used for resource manager to control secure access permission." bitfld.long 0x0 31. "DOM15_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM15_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM15_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM15_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM14_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM14_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM14_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM14_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM13_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM13_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM13_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM13_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM12_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM12_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM12_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM12_SEC_EN,Domain secure permission control enable" "0,1" repeat.end repeat 16. (list 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1A 0x1B 0x1C 0x1D 0x1E 0x1F )(list 0x340 0x374 0x3A8 0x3DC 0x410 0x444 0x478 0x4AC 0x4E0 0x514 0x548 0x57C 0x5B0 0x5E4 0x618 0x64C ) group.long ($2+0x2414)++0x3 line.long 0x0 "SEC_PER3_$1,This register is only used for resource manager to control secure access permission." bitfld.long 0x0 31. "DOM15_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM15_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM15_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM15_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM14_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM14_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM14_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM14_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM13_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM13_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM13_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM13_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM12_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM12_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM12_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM12_SEC_EN,Domain secure permission control enable" "0,1" repeat.end repeat 16. (list 0x20 0x21 0x22 0x23 0x24 0x25 0x26 0x27 0x28 0x29 0x2A 0x2B 0x2C 0x2D 0x2E 0x2F )(list 0x680 0x6B4 0x6E8 0x71C 0x750 0x784 0x7B8 0x7EC 0x820 0x854 0x888 0x8BC 0x8F0 0x924 0x958 0x98C ) group.long ($2+0x2414)++0x3 line.long 0x0 "SEC_PER3_$1,This register is only used for resource manager to control secure access permission." bitfld.long 0x0 31. "DOM15_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM15_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM15_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM15_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM14_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM14_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM14_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM14_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM13_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM13_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM13_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM13_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM12_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM12_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM12_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM12_SEC_EN,Domain secure permission control enable" "0,1" repeat.end repeat 16. (list 0x30 0x31 0x32 0x33 0x34 0x35 0x36 0x37 0x38 0x39 0x3A 0x3B 0x3C 0x3D 0x3E 0x3F )(list 0x9C0 0x9F4 0xA28 0xA5C 0xA90 0xAC4 0xAF8 0xB2C 0xB60 0xB94 0xBC8 0xBFC 0xC30 0xC64 0xC98 0xCCC ) group.long ($2+0x2414)++0x3 line.long 0x0 "SEC_PER3_$1,This register is only used for resource manager to control secure access permission." bitfld.long 0x0 31. "DOM15_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM15_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM15_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM15_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM14_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM14_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM14_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM14_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM13_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM13_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM13_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM13_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM12_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM12_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM12_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM12_SEC_EN,Domain secure permission control enable" "0,1" repeat.end repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x34 0x68 0x9C 0xD0 0x104 0x138 0x16C 0x1A0 0x1D4 0x208 0x23C 0x270 0x2A4 0x2D8 0x30C ) group.long ($2+0x2418)++0x3 line.long 0x0 "PRI_PER0_$1,This register is only used for resource manager to control privileged access permission." bitfld.long 0x0 31. "DOM3_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM3_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM3_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM3_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM2_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM2_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM2_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM2_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM1_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM1_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM1_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM1_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM0_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM0_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM0_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM0_PRI_EN,Domain privileged permission control enable" "0,1" repeat.end repeat 16. (list 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1A 0x1B 0x1C 0x1D 0x1E 0x1F )(list 0x340 0x374 0x3A8 0x3DC 0x410 0x444 0x478 0x4AC 0x4E0 0x514 0x548 0x57C 0x5B0 0x5E4 0x618 0x64C ) group.long ($2+0x2418)++0x3 line.long 0x0 "PRI_PER0_$1,This register is only used for resource manager to control privileged access permission." bitfld.long 0x0 31. "DOM3_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM3_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM3_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM3_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM2_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM2_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM2_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM2_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM1_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM1_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM1_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM1_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM0_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM0_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM0_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM0_PRI_EN,Domain privileged permission control enable" "0,1" repeat.end repeat 16. (list 0x20 0x21 0x22 0x23 0x24 0x25 0x26 0x27 0x28 0x29 0x2A 0x2B 0x2C 0x2D 0x2E 0x2F )(list 0x680 0x6B4 0x6E8 0x71C 0x750 0x784 0x7B8 0x7EC 0x820 0x854 0x888 0x8BC 0x8F0 0x924 0x958 0x98C ) group.long ($2+0x2418)++0x3 line.long 0x0 "PRI_PER0_$1,This register is only used for resource manager to control privileged access permission." bitfld.long 0x0 31. "DOM3_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM3_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM3_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM3_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM2_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM2_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM2_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM2_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM1_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM1_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM1_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM1_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM0_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM0_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM0_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM0_PRI_EN,Domain privileged permission control enable" "0,1" repeat.end repeat 16. (list 0x30 0x31 0x32 0x33 0x34 0x35 0x36 0x37 0x38 0x39 0x3A 0x3B 0x3C 0x3D 0x3E 0x3F )(list 0x9C0 0x9F4 0xA28 0xA5C 0xA90 0xAC4 0xAF8 0xB2C 0xB60 0xB94 0xBC8 0xBFC 0xC30 0xC64 0xC98 0xCCC ) group.long ($2+0x2418)++0x3 line.long 0x0 "PRI_PER0_$1,This register is only used for resource manager to control privileged access permission." bitfld.long 0x0 31. "DOM3_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM3_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM3_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM3_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM2_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM2_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM2_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM2_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM1_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM1_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM1_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM1_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM0_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM0_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM0_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM0_PRI_EN,Domain privileged permission control enable" "0,1" repeat.end repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x34 0x68 0x9C 0xD0 0x104 0x138 0x16C 0x1A0 0x1D4 0x208 0x23C 0x270 0x2A4 0x2D8 0x30C ) group.long ($2+0x241C)++0x3 line.long 0x0 "PRI_PER1_$1,This register is only used for resource manager to control privileged access permission." bitfld.long 0x0 31. "DOM7_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM7_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM7_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM7_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM6_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM6_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM6_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM6_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM5_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM5_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM5_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM5_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM4_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM4_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM4_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM4_PRI_EN,Domain privileged permission control enable" "0,1" repeat.end repeat 16. (list 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1A 0x1B 0x1C 0x1D 0x1E 0x1F )(list 0x340 0x374 0x3A8 0x3DC 0x410 0x444 0x478 0x4AC 0x4E0 0x514 0x548 0x57C 0x5B0 0x5E4 0x618 0x64C ) group.long ($2+0x241C)++0x3 line.long 0x0 "PRI_PER1_$1,This register is only used for resource manager to control privileged access permission." bitfld.long 0x0 31. "DOM7_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM7_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM7_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM7_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM6_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM6_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM6_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM6_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM5_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM5_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM5_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM5_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM4_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM4_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM4_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM4_PRI_EN,Domain privileged permission control enable" "0,1" repeat.end repeat 16. (list 0x20 0x21 0x22 0x23 0x24 0x25 0x26 0x27 0x28 0x29 0x2A 0x2B 0x2C 0x2D 0x2E 0x2F )(list 0x680 0x6B4 0x6E8 0x71C 0x750 0x784 0x7B8 0x7EC 0x820 0x854 0x888 0x8BC 0x8F0 0x924 0x958 0x98C ) group.long ($2+0x241C)++0x3 line.long 0x0 "PRI_PER1_$1,This register is only used for resource manager to control privileged access permission." bitfld.long 0x0 31. "DOM7_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM7_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM7_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM7_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM6_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM6_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM6_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM6_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM5_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM5_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM5_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM5_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM4_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM4_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM4_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM4_PRI_EN,Domain privileged permission control enable" "0,1" repeat.end repeat 16. (list 0x30 0x31 0x32 0x33 0x34 0x35 0x36 0x37 0x38 0x39 0x3A 0x3B 0x3C 0x3D 0x3E 0x3F )(list 0x9C0 0x9F4 0xA28 0xA5C 0xA90 0xAC4 0xAF8 0xB2C 0xB60 0xB94 0xBC8 0xBFC 0xC30 0xC64 0xC98 0xCCC ) group.long ($2+0x241C)++0x3 line.long 0x0 "PRI_PER1_$1,This register is only used for resource manager to control privileged access permission." bitfld.long 0x0 31. "DOM7_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM7_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM7_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM7_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM6_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM6_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM6_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM6_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM5_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM5_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM5_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM5_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM4_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM4_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM4_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM4_PRI_EN,Domain privileged permission control enable" "0,1" repeat.end repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x34 0x68 0x9C 0xD0 0x104 0x138 0x16C 0x1A0 0x1D4 0x208 0x23C 0x270 0x2A4 0x2D8 0x30C ) group.long ($2+0x2420)++0x3 line.long 0x0 "PRI_PER2_$1,This register is only used for resource manager to control privileged access permission." bitfld.long 0x0 31. "DOM11_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM11_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM11_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM11_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM10_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM10_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM10_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM10_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM9_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM9_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM9_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM9_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM8_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM8_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM8_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM8_PRI_EN,Domain privileged permission control enable" "0,1" repeat.end repeat 16. (list 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1A 0x1B 0x1C 0x1D 0x1E 0x1F )(list 0x340 0x374 0x3A8 0x3DC 0x410 0x444 0x478 0x4AC 0x4E0 0x514 0x548 0x57C 0x5B0 0x5E4 0x618 0x64C ) group.long ($2+0x2420)++0x3 line.long 0x0 "PRI_PER2_$1,This register is only used for resource manager to control privileged access permission." bitfld.long 0x0 31. "DOM11_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM11_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM11_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM11_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM10_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM10_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM10_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM10_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM9_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM9_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM9_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM9_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM8_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM8_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM8_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM8_PRI_EN,Domain privileged permission control enable" "0,1" repeat.end repeat 16. (list 0x20 0x21 0x22 0x23 0x24 0x25 0x26 0x27 0x28 0x29 0x2A 0x2B 0x2C 0x2D 0x2E 0x2F )(list 0x680 0x6B4 0x6E8 0x71C 0x750 0x784 0x7B8 0x7EC 0x820 0x854 0x888 0x8BC 0x8F0 0x924 0x958 0x98C ) group.long ($2+0x2420)++0x3 line.long 0x0 "PRI_PER2_$1,This register is only used for resource manager to control privileged access permission." bitfld.long 0x0 31. "DOM11_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM11_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM11_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM11_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM10_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM10_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM10_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM10_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM9_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM9_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM9_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM9_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM8_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM8_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM8_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM8_PRI_EN,Domain privileged permission control enable" "0,1" repeat.end repeat 16. (list 0x30 0x31 0x32 0x33 0x34 0x35 0x36 0x37 0x38 0x39 0x3A 0x3B 0x3C 0x3D 0x3E 0x3F )(list 0x9C0 0x9F4 0xA28 0xA5C 0xA90 0xAC4 0xAF8 0xB2C 0xB60 0xB94 0xBC8 0xBFC 0xC30 0xC64 0xC98 0xCCC ) group.long ($2+0x2420)++0x3 line.long 0x0 "PRI_PER2_$1,This register is only used for resource manager to control privileged access permission." bitfld.long 0x0 31. "DOM11_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM11_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM11_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM11_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM10_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM10_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM10_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM10_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM9_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM9_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM9_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM9_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM8_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM8_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM8_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM8_PRI_EN,Domain privileged permission control enable" "0,1" repeat.end repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x34 0x68 0x9C 0xD0 0x104 0x138 0x16C 0x1A0 0x1D4 0x208 0x23C 0x270 0x2A4 0x2D8 0x30C ) group.long ($2+0x2424)++0x3 line.long 0x0 "PRI_PER3_$1,This register is only used for resource manager to control privileged access permission." bitfld.long 0x0 31. "DOM15_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM15_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM15_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM15_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM14_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM14_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM14_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM14_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM13_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM13_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM13_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM13_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM12_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM12_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM12_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM12_PRI_EN,Domain privileged permission control enable" "0,1" repeat.end repeat 16. (list 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1A 0x1B 0x1C 0x1D 0x1E 0x1F )(list 0x340 0x374 0x3A8 0x3DC 0x410 0x444 0x478 0x4AC 0x4E0 0x514 0x548 0x57C 0x5B0 0x5E4 0x618 0x64C ) group.long ($2+0x2424)++0x3 line.long 0x0 "PRI_PER3_$1,This register is only used for resource manager to control privileged access permission." bitfld.long 0x0 31. "DOM15_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM15_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM15_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM15_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM14_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM14_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM14_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM14_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM13_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM13_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM13_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM13_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM12_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM12_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM12_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM12_PRI_EN,Domain privileged permission control enable" "0,1" repeat.end repeat 16. (list 0x20 0x21 0x22 0x23 0x24 0x25 0x26 0x27 0x28 0x29 0x2A 0x2B 0x2C 0x2D 0x2E 0x2F )(list 0x680 0x6B4 0x6E8 0x71C 0x750 0x784 0x7B8 0x7EC 0x820 0x854 0x888 0x8BC 0x8F0 0x924 0x958 0x98C ) group.long ($2+0x2424)++0x3 line.long 0x0 "PRI_PER3_$1,This register is only used for resource manager to control privileged access permission." bitfld.long 0x0 31. "DOM15_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM15_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM15_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM15_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM14_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM14_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM14_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM14_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM13_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM13_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM13_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM13_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM12_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM12_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM12_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM12_PRI_EN,Domain privileged permission control enable" "0,1" repeat.end repeat 16. (list 0x30 0x31 0x32 0x33 0x34 0x35 0x36 0x37 0x38 0x39 0x3A 0x3B 0x3C 0x3D 0x3E 0x3F )(list 0x9C0 0x9F4 0xA28 0xA5C 0xA90 0xAC4 0xAF8 0xB2C 0xB60 0xB94 0xBC8 0xBFC 0xC30 0xC64 0xC98 0xCCC ) group.long ($2+0x2424)++0x3 line.long 0x0 "PRI_PER3_$1,This register is only used for resource manager to control privileged access permission." bitfld.long 0x0 31. "DOM15_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM15_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM15_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM15_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM14_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM14_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM14_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM14_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM13_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM13_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM13_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM13_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM12_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM12_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM12_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM12_PRI_EN,Domain privileged permission control enable" "0,1" repeat.end repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x34 0x68 0x9C 0xD0 0x104 0x138 0x16C 0x1A0 0x1D4 0x208 0x23C 0x270 0x2A4 0x2D8 0x30C ) group.long ($2+0x2428)++0x3 line.long 0x0 "DOM_SEC_PER_$1,This register is only used for domain master to control secure access permission. When the domain master write this register. it only changes the secure permission for itself. When the domain master read this register. it gets permission.." bitfld.long 0x0 7. "DOM_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" newline bitfld.long 0x0 0. "DOM_SEC_EN,Domain secure permission control enable" "0,1" repeat.end repeat 16. (list 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1A 0x1B 0x1C 0x1D 0x1E 0x1F )(list 0x340 0x374 0x3A8 0x3DC 0x410 0x444 0x478 0x4AC 0x4E0 0x514 0x548 0x57C 0x5B0 0x5E4 0x618 0x64C ) group.long ($2+0x2428)++0x3 line.long 0x0 "DOM_SEC_PER_$1,This register is only used for domain master to control secure access permission. When the domain master write this register. it only changes the secure permission for itself. When the domain master read this register. it gets permission.." bitfld.long 0x0 7. "DOM_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" newline bitfld.long 0x0 0. "DOM_SEC_EN,Domain secure permission control enable" "0,1" repeat.end repeat 16. (list 0x20 0x21 0x22 0x23 0x24 0x25 0x26 0x27 0x28 0x29 0x2A 0x2B 0x2C 0x2D 0x2E 0x2F )(list 0x680 0x6B4 0x6E8 0x71C 0x750 0x784 0x7B8 0x7EC 0x820 0x854 0x888 0x8BC 0x8F0 0x924 0x958 0x98C ) group.long ($2+0x2428)++0x3 line.long 0x0 "DOM_SEC_PER_$1,This register is only used for domain master to control secure access permission. When the domain master write this register. it only changes the secure permission for itself. When the domain master read this register. it gets permission.." bitfld.long 0x0 7. "DOM_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" newline bitfld.long 0x0 0. "DOM_SEC_EN,Domain secure permission control enable" "0,1" repeat.end repeat 16. (list 0x30 0x31 0x32 0x33 0x34 0x35 0x36 0x37 0x38 0x39 0x3A 0x3B 0x3C 0x3D 0x3E 0x3F )(list 0x9C0 0x9F4 0xA28 0xA5C 0xA90 0xAC4 0xAF8 0xB2C 0xB60 0xB94 0xBC8 0xBFC 0xC30 0xC64 0xC98 0xCCC ) group.long ($2+0x2428)++0x3 line.long 0x0 "DOM_SEC_PER_$1,This register is only used for domain master to control secure access permission. When the domain master write this register. it only changes the secure permission for itself. When the domain master read this register. it gets permission.." bitfld.long 0x0 7. "DOM_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" newline bitfld.long 0x0 0. "DOM_SEC_EN,Domain secure permission control enable" "0,1" repeat.end repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x34 0x68 0x9C 0xD0 0x104 0x138 0x16C 0x1A0 0x1D4 0x208 0x23C 0x270 0x2A4 0x2D8 0x30C ) group.long ($2+0x242C)++0x3 line.long 0x0 "DOM_PRI_PER_$1,This register is only used for domain master to control secure access permission. When the domain master write this register. it only changes the secure permission for itself. When the domain master read this register. it gets permission.." bitfld.long 0x0 7. "DOM_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" newline bitfld.long 0x0 0. "DOM_PRI_EN,Domain privileged permission control enable" "0,1" repeat.end repeat 16. (list 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1A 0x1B 0x1C 0x1D 0x1E 0x1F )(list 0x340 0x374 0x3A8 0x3DC 0x410 0x444 0x478 0x4AC 0x4E0 0x514 0x548 0x57C 0x5B0 0x5E4 0x618 0x64C ) group.long ($2+0x242C)++0x3 line.long 0x0 "DOM_PRI_PER_$1,This register is only used for domain master to control secure access permission. When the domain master write this register. it only changes the secure permission for itself. When the domain master read this register. it gets permission.." bitfld.long 0x0 7. "DOM_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" newline bitfld.long 0x0 0. "DOM_PRI_EN,Domain privileged permission control enable" "0,1" repeat.end repeat 16. (list 0x20 0x21 0x22 0x23 0x24 0x25 0x26 0x27 0x28 0x29 0x2A 0x2B 0x2C 0x2D 0x2E 0x2F )(list 0x680 0x6B4 0x6E8 0x71C 0x750 0x784 0x7B8 0x7EC 0x820 0x854 0x888 0x8BC 0x8F0 0x924 0x958 0x98C ) group.long ($2+0x242C)++0x3 line.long 0x0 "DOM_PRI_PER_$1,This register is only used for domain master to control secure access permission. When the domain master write this register. it only changes the secure permission for itself. When the domain master read this register. it gets permission.." bitfld.long 0x0 7. "DOM_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" newline bitfld.long 0x0 0. "DOM_PRI_EN,Domain privileged permission control enable" "0,1" repeat.end repeat 16. (list 0x30 0x31 0x32 0x33 0x34 0x35 0x36 0x37 0x38 0x39 0x3A 0x3B 0x3C 0x3D 0x3E 0x3F )(list 0x9C0 0x9F4 0xA28 0xA5C 0xA90 0xAC4 0xAF8 0xB2C 0xB60 0xB94 0xBC8 0xBFC 0xC30 0xC64 0xC98 0xCCC ) group.long ($2+0x242C)++0x3 line.long 0x0 "DOM_PRI_PER_$1,This register is only used for domain master to control secure access permission. When the domain master write this register. it only changes the secure permission for itself. When the domain master read this register. it gets permission.." bitfld.long 0x0 7. "DOM_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" newline bitfld.long 0x0 0. "DOM_PRI_EN,Domain privileged permission control enable" "0,1" repeat.end repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x34 0x68 0x9C 0xD0 0x104 0x138 0x16C 0x1A0 0x1D4 0x208 0x23C 0x270 0x2A4 0x2D8 0x30C ) group.long ($2+0x2430)++0x3 line.long 0x0 "DOM_ASSIGN_$1,Use to assign domain for accessing DOM_SEC_PER and DOM_PRI_PER register. Only resource manager. group manager and domain owner can access this register. For write. group manager must write its owen domain ID. otherwise write accessing will.." hexmask.long.byte 0x0 0.--3. 1. "DID,accessing DOM_SEC_PER and DOM_PRI_PER register" repeat.end repeat 16. (list 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1A 0x1B 0x1C 0x1D 0x1E 0x1F )(list 0x340 0x374 0x3A8 0x3DC 0x410 0x444 0x478 0x4AC 0x4E0 0x514 0x548 0x57C 0x5B0 0x5E4 0x618 0x64C ) group.long ($2+0x2430)++0x3 line.long 0x0 "DOM_ASSIGN_$1,Use to assign domain for accessing DOM_SEC_PER and DOM_PRI_PER register. Only resource manager. group manager and domain owner can access this register. For write. group manager must write its owen domain ID. otherwise write accessing will.." hexmask.long.byte 0x0 0.--3. 1. "DID,accessing DOM_SEC_PER and DOM_PRI_PER register" repeat.end repeat 16. (list 0x20 0x21 0x22 0x23 0x24 0x25 0x26 0x27 0x28 0x29 0x2A 0x2B 0x2C 0x2D 0x2E 0x2F )(list 0x680 0x6B4 0x6E8 0x71C 0x750 0x784 0x7B8 0x7EC 0x820 0x854 0x888 0x8BC 0x8F0 0x924 0x958 0x98C ) group.long ($2+0x2430)++0x3 line.long 0x0 "DOM_ASSIGN_$1,Use to assign domain for accessing DOM_SEC_PER and DOM_PRI_PER register. Only resource manager. group manager and domain owner can access this register. For write. group manager must write its owen domain ID. otherwise write accessing will.." hexmask.long.byte 0x0 0.--3. 1. "DID,accessing DOM_SEC_PER and DOM_PRI_PER register" repeat.end repeat 16. (list 0x30 0x31 0x32 0x33 0x34 0x35 0x36 0x37 0x38 0x39 0x3A 0x3B 0x3C 0x3D 0x3E 0x3F )(list 0x9C0 0x9F4 0xA28 0xA5C 0xA90 0xAC4 0xAF8 0xB2C 0xB60 0xB94 0xBC8 0xBFC 0xC30 0xC64 0xC98 0xCCC ) group.long ($2+0x2430)++0x3 line.long 0x0 "DOM_ASSIGN_$1,Use to assign domain for accessing DOM_SEC_PER and DOM_PRI_PER register. Only resource manager. group manager and domain owner can access this register. For write. group manager must write its owen domain ID. otherwise write accessing will.." hexmask.long.byte 0x0 0.--3. 1. "DID,accessing DOM_SEC_PER and DOM_PRI_PER register" repeat.end repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x38 0x70 0xA8 0xE0 0x118 0x150 0x188 0x1C0 0x1F8 0x230 0x268 0x2A0 0x2D8 0x310 0x348 ) group.long ($2+0x3100)++0x3 line.long 0x0 "RGN_DOM_$1,Assign domain for peripheral. It can be only configured by resource and group manager" bitfld.long 0x0 31. "LOCK,When this bit is set lock write for all the bits in the register." "0,1" bitfld.long 0x0 4. "SET,Set together with DID would change permission of this resource to following setting: 1) Domain access control enabled. 2) Read/Write allowed for the domain owner. 3) Read/Write not allowed for all the other domains. If this bit is not set only DID.." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Assign domain for peripheral" repeat.end repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x38 0x70 0xA8 0xE0 0x118 0x150 0x188 0x1C0 0x1F8 0x230 0x268 0x2A0 0x2D8 0x310 0x348 ) group.long ($2+0x3104)++0x3 line.long 0x0 "RGN_DOM_PER0_$1,Domain Permission Control. It can be only configured by resource manager and domain owner." bitfld.long 0x0 31. "DOM7_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 29.--30. "DOM7_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 28. "DOM7_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 27. "DOM6_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 25.--26. "DOM6_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" newline bitfld.long 0x0 24. "DOM6_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 23. "DOM5_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 21.--22. "DOM5_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 20. "DOM5_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 19. "DOM4_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" newline bitfld.long 0x0 17.--18. "DOM4_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM4_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 15. "DOM3_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 13.--14. "DOM3_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 12. "DOM3_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" newline bitfld.long 0x0 11. "DOM2_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 9.--10. "DOM2_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM2_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 7. "DOM1_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 5.--6. "DOM1_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" newline bitfld.long 0x0 4. "DOM1_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 3. "DOM0_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 1.--2. "DOM0_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM0_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" repeat.end repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x38 0x70 0xA8 0xE0 0x118 0x150 0x188 0x1C0 0x1F8 0x230 0x268 0x2A0 0x2D8 0x310 0x348 ) group.long ($2+0x3108)++0x3 line.long 0x0 "RGN_DOM_PER1_$1,Domain Permission Control. It can be only configured by resource manager and domain owner." bitfld.long 0x0 31. "DOM15_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 29.--30. "DOM15_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 28. "DOM15_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 27. "DOM14_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 25.--26. "DOM14_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" newline bitfld.long 0x0 24. "DOM14_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 23. "DOM13_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 21.--22. "DOM13_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 20. "DOM13_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 19. "DOM12_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" newline bitfld.long 0x0 17.--18. "DOM12_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM12_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 15. "DOM11_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 13.--14. "DOM11_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 12. "DOM11_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" newline bitfld.long 0x0 11. "DOM10_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 9.--10. "DOM10_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM10_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 7. "DOM9_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 5.--6. "DOM9_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" newline bitfld.long 0x0 4. "DOM9_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 3. "DOM8_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 1.--2. "DOM8_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM8_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" repeat.end repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x38 0x70 0xA8 0xE0 0x118 0x150 0x188 0x1C0 0x1F8 0x230 0x268 0x2A0 0x2D8 0x310 0x348 ) group.long ($2+0x310C)++0x3 line.long 0x0 "RGN_SEC_PER0_$1,This register is only used for resource manager to control secure access permission." bitfld.long 0x0 31. "DOM3_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM3_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM3_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM3_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM2_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM2_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM2_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM2_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM1_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM1_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM1_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM1_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM0_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM0_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM0_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM0_SEC_EN,Domain secure permission control enable" "0,1" repeat.end repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x38 0x70 0xA8 0xE0 0x118 0x150 0x188 0x1C0 0x1F8 0x230 0x268 0x2A0 0x2D8 0x310 0x348 ) group.long ($2+0x3110)++0x3 line.long 0x0 "RGN_SEC_PER1_$1,This register is only used for resource manager to control secure access permission." bitfld.long 0x0 31. "DOM7_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM7_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM7_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM7_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM6_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM6_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM6_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM6_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM5_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM5_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM5_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM5_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM4_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM4_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM4_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM4_SEC_EN,Domain secure permission control enable" "0,1" repeat.end repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x38 0x70 0xA8 0xE0 0x118 0x150 0x188 0x1C0 0x1F8 0x230 0x268 0x2A0 0x2D8 0x310 0x348 ) group.long ($2+0x3114)++0x3 line.long 0x0 "RGN_SEC_PER2_$1,This register is only used for resource manager to control secure access permission." bitfld.long 0x0 31. "DOM11_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM11_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM11_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM11_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM10_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM10_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM10_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM10_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM9_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM9_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM9_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM9_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM8_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM8_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM8_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM8_SEC_EN,Domain secure permission control enable" "0,1" repeat.end repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x38 0x70 0xA8 0xE0 0x118 0x150 0x188 0x1C0 0x1F8 0x230 0x268 0x2A0 0x2D8 0x310 0x348 ) group.long ($2+0x3118)++0x3 line.long 0x0 "RGN_SEC_PER3_$1,This register is only used for resource manager to control secure access permission." bitfld.long 0x0 31. "DOM15_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM15_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM15_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM15_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM14_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM14_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM14_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM14_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM13_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM13_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM13_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM13_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM12_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM12_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM12_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM12_SEC_EN,Domain secure permission control enable" "0,1" repeat.end repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x38 0x70 0xA8 0xE0 0x118 0x150 0x188 0x1C0 0x1F8 0x230 0x268 0x2A0 0x2D8 0x310 0x348 ) group.long ($2+0x311C)++0x3 line.long 0x0 "RGN_PRI_PER0_$1,This register is only used for resource manager to control privileged access permission." bitfld.long 0x0 31. "DOM3_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM3_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM3_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM3_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM2_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM2_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM2_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM2_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM1_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM1_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM1_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM1_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM0_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM0_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM0_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM0_PRI_EN,Domain privileged permission control enable" "0,1" repeat.end repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x38 0x70 0xA8 0xE0 0x118 0x150 0x188 0x1C0 0x1F8 0x230 0x268 0x2A0 0x2D8 0x310 0x348 ) group.long ($2+0x3120)++0x3 line.long 0x0 "RGN_PRI_PER1_$1,This register is only used for resource manager to control privileged access permission." bitfld.long 0x0 31. "DOM7_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM7_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM7_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM7_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM6_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM6_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM6_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM6_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM5_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM5_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM5_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM5_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM4_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM4_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM4_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM4_PRI_EN,Domain privileged permission control enable" "0,1" repeat.end repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x38 0x70 0xA8 0xE0 0x118 0x150 0x188 0x1C0 0x1F8 0x230 0x268 0x2A0 0x2D8 0x310 0x348 ) group.long ($2+0x3124)++0x3 line.long 0x0 "RGN_PRI_PER2_$1,This register is only used for resource manager to control privileged access permission." bitfld.long 0x0 31. "DOM11_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM11_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM11_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM11_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM10_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM10_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM10_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM10_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM9_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM9_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM9_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM9_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM8_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM8_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM8_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM8_PRI_EN,Domain privileged permission control enable" "0,1" repeat.end repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x38 0x70 0xA8 0xE0 0x118 0x150 0x188 0x1C0 0x1F8 0x230 0x268 0x2A0 0x2D8 0x310 0x348 ) group.long ($2+0x3128)++0x3 line.long 0x0 "RGN_PRI_PER3_$1,This register is only used for resource manager to control privileged access permission." bitfld.long 0x0 31. "DOM15_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM15_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM15_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM15_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM14_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM14_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM14_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM14_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM13_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM13_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM13_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM13_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM12_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM12_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM12_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM12_PRI_EN,Domain privileged permission control enable" "0,1" repeat.end repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x38 0x70 0xA8 0xE0 0x118 0x150 0x188 0x1C0 0x1F8 0x230 0x268 0x2A0 0x2D8 0x310 0x348 ) group.long ($2+0x312C)++0x3 line.long 0x0 "RGN_DOM_SEC_PER_$1,This register is only used for domain master to control secure access permission. When the domain master write this register. it only changes the secure permission for itself. When the domain master read this register. it gets.." bitfld.long 0x0 7. "DOM_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" newline bitfld.long 0x0 0. "DOM_SEC_EN,Domain secure permission control enable" "0,1" repeat.end repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x38 0x70 0xA8 0xE0 0x118 0x150 0x188 0x1C0 0x1F8 0x230 0x268 0x2A0 0x2D8 0x310 0x348 ) group.long ($2+0x3130)++0x3 line.long 0x0 "RGN_DOM_PRI_PER_$1,This register is only used for domain master to control secure access permission. When the domain master write this register. it only changes the secure permission for itself. When the domain master read this register. it gets.." bitfld.long 0x0 7. "DOM_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" newline bitfld.long 0x0 0. "DOM_PRI_EN,Domain privileged permission control enable" "0,1" repeat.end repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x38 0x70 0xA8 0xE0 0x118 0x150 0x188 0x1C0 0x1F8 0x230 0x268 0x2A0 0x2D8 0x310 0x348 ) group.long ($2+0x3134)++0x3 line.long 0x0 "RGN_DOM_ASSIGN_$1,Use to assign domain for accessing DOM_SEC_PER and DOM_PRI_PER register. Only resource manager. group manager and domain owner can access this register. For write. group manager must write its owen domain ID. otherwise write accessing.." hexmask.long.byte 0x0 0.--3. 1. "DID,accessing DOM_SEC_PER and DOM_PRI_PER register" repeat.end tree.end tree "RPC_AP_RSTGEN" base ad:0xF8C00000 repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x4 0x8 0xC 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C ) group.long ($2)++0x3 line.long 0x0 "REGG0_DOM_$1,Assign domain for CKGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1A 0x1B 0x1C 0x1D 0x1E 0x1F )(list 0x40 0x44 0x48 0x4C 0x50 0x54 0x58 0x5C 0x60 0x64 0x68 0x6C 0x70 0x74 0x78 0x7C ) group.long ($2)++0x3 line.long 0x0 "REGG0_DOM_$1,Assign domain for CKGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x20 0x21 0x22 0x23 0x24 0x25 0x26 0x27 0x28 0x29 0x2A 0x2B 0x2C 0x2D 0x2E 0x2F )(list 0x80 0x84 0x88 0x8C 0x90 0x94 0x98 0x9C 0xA0 0xA4 0xA8 0xAC 0xB0 0xB4 0xB8 0xBC ) group.long ($2)++0x3 line.long 0x0 "REGG0_DOM_$1,Assign domain for CKGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x30 0x31 0x32 0x33 0x34 0x35 0x36 0x37 0x38 0x39 0x3A 0x3B 0x3C 0x3D 0x3E 0x3F )(list 0xC0 0xC4 0xC8 0xCC 0xD0 0xD4 0xD8 0xDC 0xE0 0xE4 0xE8 0xEC 0xF0 0xF4 0xF8 0xFC ) group.long ($2)++0x3 line.long 0x0 "REGG0_DOM_$1,Assign domain for CKGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x40 0x41 0x42 0x43 0x44 0x45 0x46 0x47 0x48 0x49 0x4A 0x4B 0x4C 0x4D 0x4E 0x4F )(list 0x100 0x104 0x108 0x10C 0x110 0x114 0x118 0x11C 0x120 0x124 0x128 0x12C 0x130 0x134 0x138 0x13C ) group.long ($2)++0x3 line.long 0x0 "REGG0_DOM_$1,Assign domain for CKGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x50 0x51 0x52 0x53 0x54 0x55 0x56 0x57 0x58 0x59 0x5A 0x5B 0x5C 0x5D 0x5E 0x5F )(list 0x140 0x144 0x148 0x14C 0x150 0x154 0x158 0x15C 0x160 0x164 0x168 0x16C 0x170 0x174 0x178 0x17C ) group.long ($2)++0x3 line.long 0x0 "REGG0_DOM_$1,Assign domain for CKGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x60 0x61 0x62 0x63 0x64 0x65 0x66 0x67 0x68 0x69 0x6A 0x6B 0x6C 0x6D 0x6E 0x6F )(list 0x180 0x184 0x188 0x18C 0x190 0x194 0x198 0x19C 0x1A0 0x1A4 0x1A8 0x1AC 0x1B0 0x1B4 0x1B8 0x1BC ) group.long ($2)++0x3 line.long 0x0 "REGG0_DOM_$1,Assign domain for CKGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x70 0x71 0x72 0x73 0x74 0x75 0x76 0x77 0x78 0x79 0x7A 0x7B 0x7C 0x7D 0x7E 0x7F )(list 0x1C0 0x1C4 0x1C8 0x1CC 0x1D0 0x1D4 0x1D8 0x1DC 0x1E0 0x1E4 0x1E8 0x1EC 0x1F0 0x1F4 0x1F8 0x1FC ) group.long ($2)++0x3 line.long 0x0 "REGG0_DOM_$1,Assign domain for CKGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x80 0x81 0x82 0x83 0x84 0x85 0x86 0x87 0x88 0x89 0x8A 0x8B 0x8C 0x8D 0x8E 0x8F )(list 0x200 0x204 0x208 0x20C 0x210 0x214 0x218 0x21C 0x220 0x224 0x228 0x22C 0x230 0x234 0x238 0x23C ) group.long ($2)++0x3 line.long 0x0 "REGG0_DOM_$1,Assign domain for CKGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x90 0x91 0x92 0x93 0x94 0x95 0x96 0x97 0x98 0x99 0x9A 0x9B 0x9C 0x9D 0x9E 0x9F )(list 0x240 0x244 0x248 0x24C 0x250 0x254 0x258 0x25C 0x260 0x264 0x268 0x26C 0x270 0x274 0x278 0x27C ) group.long ($2)++0x3 line.long 0x0 "REGG0_DOM_$1,Assign domain for CKGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xA0 0xA1 0xA2 0xA3 0xA4 0xA5 0xA6 0xA7 0xA8 0xA9 0xAA 0xAB 0xAC 0xAD 0xAE 0xAF )(list 0x280 0x284 0x288 0x28C 0x290 0x294 0x298 0x29C 0x2A0 0x2A4 0x2A8 0x2AC 0x2B0 0x2B4 0x2B8 0x2BC ) group.long ($2)++0x3 line.long 0x0 "REGG0_DOM_$1,Assign domain for CKGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xB0 0xB1 0xB2 0xB3 0xB4 0xB5 0xB6 0xB7 0xB8 0xB9 0xBA 0xBB 0xBC 0xBD 0xBE 0xBF )(list 0x2C0 0x2C4 0x2C8 0x2CC 0x2D0 0x2D4 0x2D8 0x2DC 0x2E0 0x2E4 0x2E8 0x2EC 0x2F0 0x2F4 0x2F8 0x2FC ) group.long ($2)++0x3 line.long 0x0 "REGG0_DOM_$1,Assign domain for CKGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xC0 0xC1 0xC2 0xC3 0xC4 0xC5 0xC6 0xC7 0xC8 0xC9 0xCA 0xCB 0xCC 0xCD 0xCE 0xCF )(list 0x300 0x304 0x308 0x30C 0x310 0x314 0x318 0x31C 0x320 0x324 0x328 0x32C 0x330 0x334 0x338 0x33C ) group.long ($2)++0x3 line.long 0x0 "REGG0_DOM_$1,Assign domain for CKGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xD0 0xD1 0xD2 0xD3 0xD4 0xD5 0xD6 0xD7 0xD8 0xD9 0xDA 0xDB 0xDC 0xDD 0xDE 0xDF )(list 0x340 0x344 0x348 0x34C 0x350 0x354 0x358 0x35C 0x360 0x364 0x368 0x36C 0x370 0x374 0x378 0x37C ) group.long ($2)++0x3 line.long 0x0 "REGG0_DOM_$1,Assign domain for CKGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xE0 0xE1 0xE2 0xE3 0xE4 0xE5 0xE6 0xE7 0xE8 0xE9 0xEA 0xEB 0xEC 0xED 0xEE 0xEF )(list 0x380 0x384 0x388 0x38C 0x390 0x394 0x398 0x39C 0x3A0 0x3A4 0x3A8 0x3AC 0x3B0 0x3B4 0x3B8 0x3BC ) group.long ($2)++0x3 line.long 0x0 "REGG0_DOM_$1,Assign domain for CKGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xF0 0xF1 0xF2 0xF3 0xF4 0xF5 0xF6 0xF7 0xF8 0xF9 0xFA 0xFB 0xFC 0xFD 0xFE 0xFF )(list 0x3C0 0x3C4 0x3C8 0x3CC 0x3D0 0x3D4 0x3D8 0x3DC 0x3E0 0x3E4 0x3E8 0x3EC 0x3F0 0x3F4 0x3F8 0x3FC ) group.long ($2)++0x3 line.long 0x0 "REGG0_DOM_$1,Assign domain for CKGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x4 0x8 0xC 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C ) group.long ($2+0x400)++0x3 line.long 0x0 "REGG1_DOM_$1,Assign domain for CKGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1A 0x1B 0x1C 0x1D 0x1E 0x1F )(list 0x40 0x44 0x48 0x4C 0x50 0x54 0x58 0x5C 0x60 0x64 0x68 0x6C 0x70 0x74 0x78 0x7C ) group.long ($2+0x400)++0x3 line.long 0x0 "REGG1_DOM_$1,Assign domain for CKGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x20 0x21 0x22 0x23 0x24 0x25 0x26 0x27 0x28 0x29 0x2A 0x2B 0x2C 0x2D 0x2E 0x2F )(list 0x80 0x84 0x88 0x8C 0x90 0x94 0x98 0x9C 0xA0 0xA4 0xA8 0xAC 0xB0 0xB4 0xB8 0xBC ) group.long ($2+0x400)++0x3 line.long 0x0 "REGG1_DOM_$1,Assign domain for CKGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x30 0x31 0x32 0x33 0x34 0x35 0x36 0x37 0x38 0x39 0x3A 0x3B 0x3C 0x3D 0x3E 0x3F )(list 0xC0 0xC4 0xC8 0xCC 0xD0 0xD4 0xD8 0xDC 0xE0 0xE4 0xE8 0xEC 0xF0 0xF4 0xF8 0xFC ) group.long ($2+0x400)++0x3 line.long 0x0 "REGG1_DOM_$1,Assign domain for CKGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x40 0x41 0x42 0x43 0x44 0x45 0x46 0x47 0x48 0x49 0x4A 0x4B 0x4C 0x4D 0x4E 0x4F )(list 0x100 0x104 0x108 0x10C 0x110 0x114 0x118 0x11C 0x120 0x124 0x128 0x12C 0x130 0x134 0x138 0x13C ) group.long ($2+0x400)++0x3 line.long 0x0 "REGG1_DOM_$1,Assign domain for CKGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x50 0x51 0x52 0x53 0x54 0x55 0x56 0x57 0x58 0x59 0x5A 0x5B 0x5C 0x5D 0x5E 0x5F )(list 0x140 0x144 0x148 0x14C 0x150 0x154 0x158 0x15C 0x160 0x164 0x168 0x16C 0x170 0x174 0x178 0x17C ) group.long ($2+0x400)++0x3 line.long 0x0 "REGG1_DOM_$1,Assign domain for CKGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x60 0x61 0x62 0x63 0x64 0x65 0x66 0x67 0x68 0x69 0x6A 0x6B 0x6C 0x6D 0x6E 0x6F )(list 0x180 0x184 0x188 0x18C 0x190 0x194 0x198 0x19C 0x1A0 0x1A4 0x1A8 0x1AC 0x1B0 0x1B4 0x1B8 0x1BC ) group.long ($2+0x400)++0x3 line.long 0x0 "REGG1_DOM_$1,Assign domain for CKGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x70 0x71 0x72 0x73 0x74 0x75 0x76 0x77 0x78 0x79 0x7A 0x7B 0x7C 0x7D 0x7E 0x7F )(list 0x1C0 0x1C4 0x1C8 0x1CC 0x1D0 0x1D4 0x1D8 0x1DC 0x1E0 0x1E4 0x1E8 0x1EC 0x1F0 0x1F4 0x1F8 0x1FC ) group.long ($2+0x400)++0x3 line.long 0x0 "REGG1_DOM_$1,Assign domain for CKGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x80 0x81 0x82 0x83 0x84 0x85 0x86 0x87 0x88 0x89 0x8A 0x8B 0x8C 0x8D 0x8E 0x8F )(list 0x200 0x204 0x208 0x20C 0x210 0x214 0x218 0x21C 0x220 0x224 0x228 0x22C 0x230 0x234 0x238 0x23C ) group.long ($2+0x400)++0x3 line.long 0x0 "REGG1_DOM_$1,Assign domain for CKGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x90 0x91 0x92 0x93 0x94 0x95 0x96 0x97 0x98 0x99 0x9A 0x9B 0x9C 0x9D 0x9E 0x9F )(list 0x240 0x244 0x248 0x24C 0x250 0x254 0x258 0x25C 0x260 0x264 0x268 0x26C 0x270 0x274 0x278 0x27C ) group.long ($2+0x400)++0x3 line.long 0x0 "REGG1_DOM_$1,Assign domain for CKGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xA0 0xA1 0xA2 0xA3 0xA4 0xA5 0xA6 0xA7 0xA8 0xA9 0xAA 0xAB 0xAC 0xAD 0xAE 0xAF )(list 0x280 0x284 0x288 0x28C 0x290 0x294 0x298 0x29C 0x2A0 0x2A4 0x2A8 0x2AC 0x2B0 0x2B4 0x2B8 0x2BC ) group.long ($2+0x400)++0x3 line.long 0x0 "REGG1_DOM_$1,Assign domain for CKGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xB0 0xB1 0xB2 0xB3 0xB4 0xB5 0xB6 0xB7 0xB8 0xB9 0xBA 0xBB 0xBC 0xBD 0xBE 0xBF )(list 0x2C0 0x2C4 0x2C8 0x2CC 0x2D0 0x2D4 0x2D8 0x2DC 0x2E0 0x2E4 0x2E8 0x2EC 0x2F0 0x2F4 0x2F8 0x2FC ) group.long ($2+0x400)++0x3 line.long 0x0 "REGG1_DOM_$1,Assign domain for CKGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xC0 0xC1 0xC2 0xC3 0xC4 0xC5 0xC6 0xC7 0xC8 0xC9 0xCA 0xCB 0xCC 0xCD 0xCE 0xCF )(list 0x300 0x304 0x308 0x30C 0x310 0x314 0x318 0x31C 0x320 0x324 0x328 0x32C 0x330 0x334 0x338 0x33C ) group.long ($2+0x400)++0x3 line.long 0x0 "REGG1_DOM_$1,Assign domain for CKGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xD0 0xD1 0xD2 0xD3 0xD4 0xD5 0xD6 0xD7 0xD8 0xD9 0xDA 0xDB 0xDC 0xDD 0xDE 0xDF )(list 0x340 0x344 0x348 0x34C 0x350 0x354 0x358 0x35C 0x360 0x364 0x368 0x36C 0x370 0x374 0x378 0x37C ) group.long ($2+0x400)++0x3 line.long 0x0 "REGG1_DOM_$1,Assign domain for CKGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xE0 0xE1 0xE2 0xE3 0xE4 0xE5 0xE6 0xE7 0xE8 0xE9 0xEA 0xEB 0xEC 0xED 0xEE 0xEF )(list 0x380 0x384 0x388 0x38C 0x390 0x394 0x398 0x39C 0x3A0 0x3A4 0x3A8 0x3AC 0x3B0 0x3B4 0x3B8 0x3BC ) group.long ($2+0x400)++0x3 line.long 0x0 "REGG1_DOM_$1,Assign domain for CKGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xF0 0xF1 0xF2 0xF3 0xF4 0xF5 0xF6 0xF7 0xF8 0xF9 0xFA 0xFB 0xFC 0xFD 0xFE 0xFF )(list 0x3C0 0x3C4 0x3C8 0x3CC 0x3D0 0x3D4 0x3D8 0x3DC 0x3E0 0x3E4 0x3E8 0x3EC 0x3F0 0x3F4 0x3F8 0x3FC ) group.long ($2+0x400)++0x3 line.long 0x0 "REGG1_DOM_$1,Assign domain for CKGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x4 0x8 0xC 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C ) group.long ($2+0x800)++0x3 line.long 0x0 "REGG2_DOM_$1,Assign domain for SCR registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1A 0x1B 0x1C 0x1D 0x1E 0x1F )(list 0x40 0x44 0x48 0x4C 0x50 0x54 0x58 0x5C 0x60 0x64 0x68 0x6C 0x70 0x74 0x78 0x7C ) group.long ($2+0x800)++0x3 line.long 0x0 "REGG2_DOM_$1,Assign domain for SCR registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x20 0x21 0x22 0x23 0x24 0x25 0x26 0x27 0x28 0x29 0x2A 0x2B 0x2C 0x2D 0x2E 0x2F )(list 0x80 0x84 0x88 0x8C 0x90 0x94 0x98 0x9C 0xA0 0xA4 0xA8 0xAC 0xB0 0xB4 0xB8 0xBC ) group.long ($2+0x800)++0x3 line.long 0x0 "REGG2_DOM_$1,Assign domain for SCR registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x30 0x31 0x32 0x33 0x34 0x35 0x36 0x37 0x38 0x39 0x3A 0x3B 0x3C 0x3D 0x3E 0x3F )(list 0xC0 0xC4 0xC8 0xCC 0xD0 0xD4 0xD8 0xDC 0xE0 0xE4 0xE8 0xEC 0xF0 0xF4 0xF8 0xFC ) group.long ($2+0x800)++0x3 line.long 0x0 "REGG2_DOM_$1,Assign domain for SCR registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x40 0x41 0x42 0x43 0x44 0x45 0x46 0x47 0x48 0x49 0x4A 0x4B 0x4C 0x4D 0x4E 0x4F )(list 0x100 0x104 0x108 0x10C 0x110 0x114 0x118 0x11C 0x120 0x124 0x128 0x12C 0x130 0x134 0x138 0x13C ) group.long ($2+0x800)++0x3 line.long 0x0 "REGG2_DOM_$1,Assign domain for SCR registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x50 0x51 0x52 0x53 0x54 0x55 0x56 0x57 0x58 0x59 0x5A 0x5B 0x5C 0x5D 0x5E 0x5F )(list 0x140 0x144 0x148 0x14C 0x150 0x154 0x158 0x15C 0x160 0x164 0x168 0x16C 0x170 0x174 0x178 0x17C ) group.long ($2+0x800)++0x3 line.long 0x0 "REGG2_DOM_$1,Assign domain for SCR registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x60 0x61 0x62 0x63 0x64 0x65 0x66 0x67 0x68 0x69 0x6A 0x6B 0x6C 0x6D 0x6E 0x6F )(list 0x180 0x184 0x188 0x18C 0x190 0x194 0x198 0x19C 0x1A0 0x1A4 0x1A8 0x1AC 0x1B0 0x1B4 0x1B8 0x1BC ) group.long ($2+0x800)++0x3 line.long 0x0 "REGG2_DOM_$1,Assign domain for SCR registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x70 0x71 0x72 0x73 0x74 0x75 0x76 0x77 0x78 0x79 0x7A 0x7B 0x7C 0x7D 0x7E 0x7F )(list 0x1C0 0x1C4 0x1C8 0x1CC 0x1D0 0x1D4 0x1D8 0x1DC 0x1E0 0x1E4 0x1E8 0x1EC 0x1F0 0x1F4 0x1F8 0x1FC ) group.long ($2+0x800)++0x3 line.long 0x0 "REGG2_DOM_$1,Assign domain for SCR registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x80 0x81 0x82 0x83 0x84 0x85 0x86 0x87 0x88 0x89 0x8A 0x8B 0x8C 0x8D 0x8E 0x8F )(list 0x200 0x204 0x208 0x20C 0x210 0x214 0x218 0x21C 0x220 0x224 0x228 0x22C 0x230 0x234 0x238 0x23C ) group.long ($2+0x800)++0x3 line.long 0x0 "REGG2_DOM_$1,Assign domain for SCR registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x90 0x91 0x92 0x93 0x94 0x95 0x96 0x97 0x98 0x99 0x9A 0x9B 0x9C 0x9D 0x9E 0x9F )(list 0x240 0x244 0x248 0x24C 0x250 0x254 0x258 0x25C 0x260 0x264 0x268 0x26C 0x270 0x274 0x278 0x27C ) group.long ($2+0x800)++0x3 line.long 0x0 "REGG2_DOM_$1,Assign domain for SCR registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xA0 0xA1 0xA2 0xA3 0xA4 0xA5 0xA6 0xA7 0xA8 0xA9 0xAA 0xAB 0xAC 0xAD 0xAE 0xAF )(list 0x280 0x284 0x288 0x28C 0x290 0x294 0x298 0x29C 0x2A0 0x2A4 0x2A8 0x2AC 0x2B0 0x2B4 0x2B8 0x2BC ) group.long ($2+0x800)++0x3 line.long 0x0 "REGG2_DOM_$1,Assign domain for SCR registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xB0 0xB1 0xB2 0xB3 0xB4 0xB5 0xB6 0xB7 0xB8 0xB9 0xBA 0xBB 0xBC 0xBD 0xBE 0xBF )(list 0x2C0 0x2C4 0x2C8 0x2CC 0x2D0 0x2D4 0x2D8 0x2DC 0x2E0 0x2E4 0x2E8 0x2EC 0x2F0 0x2F4 0x2F8 0x2FC ) group.long ($2+0x800)++0x3 line.long 0x0 "REGG2_DOM_$1,Assign domain for SCR registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xC0 0xC1 0xC2 0xC3 0xC4 0xC5 0xC6 0xC7 0xC8 0xC9 0xCA 0xCB 0xCC 0xCD 0xCE 0xCF )(list 0x300 0x304 0x308 0x30C 0x310 0x314 0x318 0x31C 0x320 0x324 0x328 0x32C 0x330 0x334 0x338 0x33C ) group.long ($2+0x800)++0x3 line.long 0x0 "REGG2_DOM_$1,Assign domain for SCR registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xD0 0xD1 0xD2 0xD3 0xD4 0xD5 0xD6 0xD7 0xD8 0xD9 0xDA 0xDB 0xDC 0xDD 0xDE 0xDF )(list 0x340 0x344 0x348 0x34C 0x350 0x354 0x358 0x35C 0x360 0x364 0x368 0x36C 0x370 0x374 0x378 0x37C ) group.long ($2+0x800)++0x3 line.long 0x0 "REGG2_DOM_$1,Assign domain for SCR registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xE0 0xE1 0xE2 0xE3 0xE4 0xE5 0xE6 0xE7 0xE8 0xE9 0xEA 0xEB 0xEC 0xED 0xEE 0xEF )(list 0x380 0x384 0x388 0x38C 0x390 0x394 0x398 0x39C 0x3A0 0x3A4 0x3A8 0x3AC 0x3B0 0x3B4 0x3B8 0x3BC ) group.long ($2+0x800)++0x3 line.long 0x0 "REGG2_DOM_$1,Assign domain for SCR registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xF0 0xF1 0xF2 0xF3 0xF4 0xF5 0xF6 0xF7 0xF8 0xF9 0xFA 0xFB 0xFC 0xFD 0xFE 0xFF )(list 0x3C0 0x3C4 0x3C8 0x3CC 0x3D0 0x3D4 0x3D8 0x3DC 0x3E0 0x3E4 0x3E8 0x3EC 0x3F0 0x3F4 0x3F8 0x3FC ) group.long ($2+0x800)++0x3 line.long 0x0 "REGG2_DOM_$1,Assign domain for SCR registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x4 0x8 0xC 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C ) group.long ($2+0xC00)++0x3 line.long 0x0 "REGG3_DOM_$1,Assign domain for SCR registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1A 0x1B 0x1C 0x1D 0x1E 0x1F )(list 0x40 0x44 0x48 0x4C 0x50 0x54 0x58 0x5C 0x60 0x64 0x68 0x6C 0x70 0x74 0x78 0x7C ) group.long ($2+0xC00)++0x3 line.long 0x0 "REGG3_DOM_$1,Assign domain for SCR registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x20 0x21 0x22 0x23 0x24 0x25 0x26 0x27 0x28 0x29 0x2A 0x2B 0x2C 0x2D 0x2E 0x2F )(list 0x80 0x84 0x88 0x8C 0x90 0x94 0x98 0x9C 0xA0 0xA4 0xA8 0xAC 0xB0 0xB4 0xB8 0xBC ) group.long ($2+0xC00)++0x3 line.long 0x0 "REGG3_DOM_$1,Assign domain for SCR registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x30 0x31 0x32 0x33 0x34 0x35 0x36 0x37 0x38 0x39 0x3A 0x3B 0x3C 0x3D 0x3E 0x3F )(list 0xC0 0xC4 0xC8 0xCC 0xD0 0xD4 0xD8 0xDC 0xE0 0xE4 0xE8 0xEC 0xF0 0xF4 0xF8 0xFC ) group.long ($2+0xC00)++0x3 line.long 0x0 "REGG3_DOM_$1,Assign domain for SCR registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x40 0x41 0x42 0x43 0x44 0x45 0x46 0x47 0x48 0x49 0x4A 0x4B 0x4C 0x4D 0x4E 0x4F )(list 0x100 0x104 0x108 0x10C 0x110 0x114 0x118 0x11C 0x120 0x124 0x128 0x12C 0x130 0x134 0x138 0x13C ) group.long ($2+0xC00)++0x3 line.long 0x0 "REGG3_DOM_$1,Assign domain for SCR registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x50 0x51 0x52 0x53 0x54 0x55 0x56 0x57 0x58 0x59 0x5A 0x5B 0x5C 0x5D 0x5E 0x5F )(list 0x140 0x144 0x148 0x14C 0x150 0x154 0x158 0x15C 0x160 0x164 0x168 0x16C 0x170 0x174 0x178 0x17C ) group.long ($2+0xC00)++0x3 line.long 0x0 "REGG3_DOM_$1,Assign domain for SCR registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x60 0x61 0x62 0x63 0x64 0x65 0x66 0x67 0x68 0x69 0x6A 0x6B 0x6C 0x6D 0x6E 0x6F )(list 0x180 0x184 0x188 0x18C 0x190 0x194 0x198 0x19C 0x1A0 0x1A4 0x1A8 0x1AC 0x1B0 0x1B4 0x1B8 0x1BC ) group.long ($2+0xC00)++0x3 line.long 0x0 "REGG3_DOM_$1,Assign domain for SCR registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x70 0x71 0x72 0x73 0x74 0x75 0x76 0x77 0x78 0x79 0x7A 0x7B 0x7C 0x7D 0x7E 0x7F )(list 0x1C0 0x1C4 0x1C8 0x1CC 0x1D0 0x1D4 0x1D8 0x1DC 0x1E0 0x1E4 0x1E8 0x1EC 0x1F0 0x1F4 0x1F8 0x1FC ) group.long ($2+0xC00)++0x3 line.long 0x0 "REGG3_DOM_$1,Assign domain for SCR registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x80 0x81 0x82 0x83 0x84 0x85 0x86 0x87 0x88 0x89 0x8A 0x8B 0x8C 0x8D 0x8E 0x8F )(list 0x200 0x204 0x208 0x20C 0x210 0x214 0x218 0x21C 0x220 0x224 0x228 0x22C 0x230 0x234 0x238 0x23C ) group.long ($2+0xC00)++0x3 line.long 0x0 "REGG3_DOM_$1,Assign domain for SCR registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x90 0x91 0x92 0x93 0x94 0x95 0x96 0x97 0x98 0x99 0x9A 0x9B 0x9C 0x9D 0x9E 0x9F )(list 0x240 0x244 0x248 0x24C 0x250 0x254 0x258 0x25C 0x260 0x264 0x268 0x26C 0x270 0x274 0x278 0x27C ) group.long ($2+0xC00)++0x3 line.long 0x0 "REGG3_DOM_$1,Assign domain for SCR registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xA0 0xA1 0xA2 0xA3 0xA4 0xA5 0xA6 0xA7 0xA8 0xA9 0xAA 0xAB 0xAC 0xAD 0xAE 0xAF )(list 0x280 0x284 0x288 0x28C 0x290 0x294 0x298 0x29C 0x2A0 0x2A4 0x2A8 0x2AC 0x2B0 0x2B4 0x2B8 0x2BC ) group.long ($2+0xC00)++0x3 line.long 0x0 "REGG3_DOM_$1,Assign domain for SCR registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xB0 0xB1 0xB2 0xB3 0xB4 0xB5 0xB6 0xB7 0xB8 0xB9 0xBA 0xBB 0xBC 0xBD 0xBE 0xBF )(list 0x2C0 0x2C4 0x2C8 0x2CC 0x2D0 0x2D4 0x2D8 0x2DC 0x2E0 0x2E4 0x2E8 0x2EC 0x2F0 0x2F4 0x2F8 0x2FC ) group.long ($2+0xC00)++0x3 line.long 0x0 "REGG3_DOM_$1,Assign domain for SCR registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xC0 0xC1 0xC2 0xC3 0xC4 0xC5 0xC6 0xC7 0xC8 0xC9 0xCA 0xCB 0xCC 0xCD 0xCE 0xCF )(list 0x300 0x304 0x308 0x30C 0x310 0x314 0x318 0x31C 0x320 0x324 0x328 0x32C 0x330 0x334 0x338 0x33C ) group.long ($2+0xC00)++0x3 line.long 0x0 "REGG3_DOM_$1,Assign domain for SCR registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xD0 0xD1 0xD2 0xD3 0xD4 0xD5 0xD6 0xD7 0xD8 0xD9 0xDA 0xDB 0xDC 0xDD 0xDE 0xDF )(list 0x340 0x344 0x348 0x34C 0x350 0x354 0x358 0x35C 0x360 0x364 0x368 0x36C 0x370 0x374 0x378 0x37C ) group.long ($2+0xC00)++0x3 line.long 0x0 "REGG3_DOM_$1,Assign domain for SCR registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xE0 0xE1 0xE2 0xE3 0xE4 0xE5 0xE6 0xE7 0xE8 0xE9 0xEA 0xEB 0xEC 0xED 0xEE 0xEF )(list 0x380 0x384 0x388 0x38C 0x390 0x394 0x398 0x39C 0x3A0 0x3A4 0x3A8 0x3AC 0x3B0 0x3B4 0x3B8 0x3BC ) group.long ($2+0xC00)++0x3 line.long 0x0 "REGG3_DOM_$1,Assign domain for SCR registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xF0 0xF1 0xF2 0xF3 0xF4 0xF5 0xF6 0xF7 0xF8 0xF9 0xFA 0xFB 0xFC 0xFD 0xFE 0xFF )(list 0x3C0 0x3C4 0x3C8 0x3CC 0x3D0 0x3D4 0x3D8 0x3DC 0x3E0 0x3E4 0x3E8 0x3EC 0x3F0 0x3F4 0x3F8 0x3FC ) group.long ($2+0xC00)++0x3 line.long 0x0 "REGG3_DOM_$1,Assign domain for SCR registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x4 0x8 0xC 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C ) group.long ($2+0x1000)++0x3 line.long 0x0 "REGG4_DOM_$1,Assign domain for RSTGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1A 0x1B 0x1C 0x1D 0x1E 0x1F )(list 0x40 0x44 0x48 0x4C 0x50 0x54 0x58 0x5C 0x60 0x64 0x68 0x6C 0x70 0x74 0x78 0x7C ) group.long ($2+0x1000)++0x3 line.long 0x0 "REGG4_DOM_$1,Assign domain for RSTGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x20 0x21 0x22 0x23 0x24 0x25 0x26 0x27 0x28 0x29 0x2A 0x2B 0x2C 0x2D 0x2E 0x2F )(list 0x80 0x84 0x88 0x8C 0x90 0x94 0x98 0x9C 0xA0 0xA4 0xA8 0xAC 0xB0 0xB4 0xB8 0xBC ) group.long ($2+0x1000)++0x3 line.long 0x0 "REGG4_DOM_$1,Assign domain for RSTGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x30 0x31 0x32 0x33 0x34 0x35 0x36 0x37 0x38 0x39 0x3A 0x3B 0x3C 0x3D 0x3E 0x3F )(list 0xC0 0xC4 0xC8 0xCC 0xD0 0xD4 0xD8 0xDC 0xE0 0xE4 0xE8 0xEC 0xF0 0xF4 0xF8 0xFC ) group.long ($2+0x1000)++0x3 line.long 0x0 "REGG4_DOM_$1,Assign domain for RSTGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x40 0x41 0x42 0x43 0x44 0x45 0x46 0x47 0x48 0x49 0x4A 0x4B 0x4C 0x4D 0x4E 0x4F )(list 0x100 0x104 0x108 0x10C 0x110 0x114 0x118 0x11C 0x120 0x124 0x128 0x12C 0x130 0x134 0x138 0x13C ) group.long ($2+0x1000)++0x3 line.long 0x0 "REGG4_DOM_$1,Assign domain for RSTGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x50 0x51 0x52 0x53 0x54 0x55 0x56 0x57 0x58 0x59 0x5A 0x5B 0x5C 0x5D 0x5E 0x5F )(list 0x140 0x144 0x148 0x14C 0x150 0x154 0x158 0x15C 0x160 0x164 0x168 0x16C 0x170 0x174 0x178 0x17C ) group.long ($2+0x1000)++0x3 line.long 0x0 "REGG4_DOM_$1,Assign domain for RSTGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x60 0x61 0x62 0x63 0x64 0x65 0x66 0x67 0x68 0x69 0x6A 0x6B 0x6C 0x6D 0x6E 0x6F )(list 0x180 0x184 0x188 0x18C 0x190 0x194 0x198 0x19C 0x1A0 0x1A4 0x1A8 0x1AC 0x1B0 0x1B4 0x1B8 0x1BC ) group.long ($2+0x1000)++0x3 line.long 0x0 "REGG4_DOM_$1,Assign domain for RSTGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x70 0x71 0x72 0x73 0x74 0x75 0x76 0x77 0x78 0x79 0x7A 0x7B 0x7C 0x7D 0x7E 0x7F )(list 0x1C0 0x1C4 0x1C8 0x1CC 0x1D0 0x1D4 0x1D8 0x1DC 0x1E0 0x1E4 0x1E8 0x1EC 0x1F0 0x1F4 0x1F8 0x1FC ) group.long ($2+0x1000)++0x3 line.long 0x0 "REGG4_DOM_$1,Assign domain for RSTGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x80 0x81 0x82 0x83 0x84 0x85 0x86 0x87 0x88 0x89 0x8A 0x8B 0x8C 0x8D 0x8E 0x8F )(list 0x200 0x204 0x208 0x20C 0x210 0x214 0x218 0x21C 0x220 0x224 0x228 0x22C 0x230 0x234 0x238 0x23C ) group.long ($2+0x1000)++0x3 line.long 0x0 "REGG4_DOM_$1,Assign domain for RSTGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x90 0x91 0x92 0x93 0x94 0x95 0x96 0x97 0x98 0x99 0x9A 0x9B 0x9C 0x9D 0x9E 0x9F )(list 0x240 0x244 0x248 0x24C 0x250 0x254 0x258 0x25C 0x260 0x264 0x268 0x26C 0x270 0x274 0x278 0x27C ) group.long ($2+0x1000)++0x3 line.long 0x0 "REGG4_DOM_$1,Assign domain for RSTGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xA0 0xA1 0xA2 0xA3 0xA4 0xA5 0xA6 0xA7 0xA8 0xA9 0xAA 0xAB 0xAC 0xAD 0xAE 0xAF )(list 0x280 0x284 0x288 0x28C 0x290 0x294 0x298 0x29C 0x2A0 0x2A4 0x2A8 0x2AC 0x2B0 0x2B4 0x2B8 0x2BC ) group.long ($2+0x1000)++0x3 line.long 0x0 "REGG4_DOM_$1,Assign domain for RSTGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xB0 0xB1 0xB2 0xB3 0xB4 0xB5 0xB6 0xB7 0xB8 0xB9 0xBA 0xBB 0xBC 0xBD 0xBE 0xBF )(list 0x2C0 0x2C4 0x2C8 0x2CC 0x2D0 0x2D4 0x2D8 0x2DC 0x2E0 0x2E4 0x2E8 0x2EC 0x2F0 0x2F4 0x2F8 0x2FC ) group.long ($2+0x1000)++0x3 line.long 0x0 "REGG4_DOM_$1,Assign domain for RSTGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xC0 0xC1 0xC2 0xC3 0xC4 0xC5 0xC6 0xC7 0xC8 0xC9 0xCA 0xCB 0xCC 0xCD 0xCE 0xCF )(list 0x300 0x304 0x308 0x30C 0x310 0x314 0x318 0x31C 0x320 0x324 0x328 0x32C 0x330 0x334 0x338 0x33C ) group.long ($2+0x1000)++0x3 line.long 0x0 "REGG4_DOM_$1,Assign domain for RSTGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xD0 0xD1 0xD2 0xD3 0xD4 0xD5 0xD6 0xD7 0xD8 0xD9 0xDA 0xDB 0xDC 0xDD 0xDE 0xDF )(list 0x340 0x344 0x348 0x34C 0x350 0x354 0x358 0x35C 0x360 0x364 0x368 0x36C 0x370 0x374 0x378 0x37C ) group.long ($2+0x1000)++0x3 line.long 0x0 "REGG4_DOM_$1,Assign domain for RSTGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xE0 0xE1 0xE2 0xE3 0xE4 0xE5 0xE6 0xE7 0xE8 0xE9 0xEA 0xEB 0xEC 0xED 0xEE 0xEF )(list 0x380 0x384 0x388 0x38C 0x390 0x394 0x398 0x39C 0x3A0 0x3A4 0x3A8 0x3AC 0x3B0 0x3B4 0x3B8 0x3BC ) group.long ($2+0x1000)++0x3 line.long 0x0 "REGG4_DOM_$1,Assign domain for RSTGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xF0 0xF1 0xF2 0xF3 0xF4 0xF5 0xF6 0xF7 0xF8 0xF9 0xFA 0xFB 0xFC 0xFD 0xFE 0xFF )(list 0x3C0 0x3C4 0x3C8 0x3CC 0x3D0 0x3D4 0x3D8 0x3DC 0x3E0 0x3E4 0x3E8 0x3EC 0x3F0 0x3F4 0x3F8 0x3FC ) group.long ($2+0x1000)++0x3 line.long 0x0 "REGG4_DOM_$1,Assign domain for RSTGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x4 0x8 0xC 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C ) group.long ($2+0x1400)++0x3 line.long 0x0 "REGG5_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1A 0x1B 0x1C 0x1D 0x1E 0x1F )(list 0x40 0x44 0x48 0x4C 0x50 0x54 0x58 0x5C 0x60 0x64 0x68 0x6C 0x70 0x74 0x78 0x7C ) group.long ($2+0x1400)++0x3 line.long 0x0 "REGG5_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x20 0x21 0x22 0x23 0x24 0x25 0x26 0x27 0x28 0x29 0x2A 0x2B 0x2C 0x2D 0x2E 0x2F )(list 0x80 0x84 0x88 0x8C 0x90 0x94 0x98 0x9C 0xA0 0xA4 0xA8 0xAC 0xB0 0xB4 0xB8 0xBC ) group.long ($2+0x1400)++0x3 line.long 0x0 "REGG5_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x30 0x31 0x32 0x33 0x34 0x35 0x36 0x37 0x38 0x39 0x3A 0x3B 0x3C 0x3D 0x3E 0x3F )(list 0xC0 0xC4 0xC8 0xCC 0xD0 0xD4 0xD8 0xDC 0xE0 0xE4 0xE8 0xEC 0xF0 0xF4 0xF8 0xFC ) group.long ($2+0x1400)++0x3 line.long 0x0 "REGG5_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x40 0x41 0x42 0x43 0x44 0x45 0x46 0x47 0x48 0x49 0x4A 0x4B 0x4C 0x4D 0x4E 0x4F )(list 0x100 0x104 0x108 0x10C 0x110 0x114 0x118 0x11C 0x120 0x124 0x128 0x12C 0x130 0x134 0x138 0x13C ) group.long ($2+0x1400)++0x3 line.long 0x0 "REGG5_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x50 0x51 0x52 0x53 0x54 0x55 0x56 0x57 0x58 0x59 0x5A 0x5B 0x5C 0x5D 0x5E 0x5F )(list 0x140 0x144 0x148 0x14C 0x150 0x154 0x158 0x15C 0x160 0x164 0x168 0x16C 0x170 0x174 0x178 0x17C ) group.long ($2+0x1400)++0x3 line.long 0x0 "REGG5_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x60 0x61 0x62 0x63 0x64 0x65 0x66 0x67 0x68 0x69 0x6A 0x6B 0x6C 0x6D 0x6E 0x6F )(list 0x180 0x184 0x188 0x18C 0x190 0x194 0x198 0x19C 0x1A0 0x1A4 0x1A8 0x1AC 0x1B0 0x1B4 0x1B8 0x1BC ) group.long ($2+0x1400)++0x3 line.long 0x0 "REGG5_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x70 0x71 0x72 0x73 0x74 0x75 0x76 0x77 0x78 0x79 0x7A 0x7B 0x7C 0x7D 0x7E 0x7F )(list 0x1C0 0x1C4 0x1C8 0x1CC 0x1D0 0x1D4 0x1D8 0x1DC 0x1E0 0x1E4 0x1E8 0x1EC 0x1F0 0x1F4 0x1F8 0x1FC ) group.long ($2+0x1400)++0x3 line.long 0x0 "REGG5_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x80 0x81 0x82 0x83 0x84 0x85 0x86 0x87 0x88 0x89 0x8A 0x8B 0x8C 0x8D 0x8E 0x8F )(list 0x200 0x204 0x208 0x20C 0x210 0x214 0x218 0x21C 0x220 0x224 0x228 0x22C 0x230 0x234 0x238 0x23C ) group.long ($2+0x1400)++0x3 line.long 0x0 "REGG5_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x90 0x91 0x92 0x93 0x94 0x95 0x96 0x97 0x98 0x99 0x9A 0x9B 0x9C 0x9D 0x9E 0x9F )(list 0x240 0x244 0x248 0x24C 0x250 0x254 0x258 0x25C 0x260 0x264 0x268 0x26C 0x270 0x274 0x278 0x27C ) group.long ($2+0x1400)++0x3 line.long 0x0 "REGG5_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xA0 0xA1 0xA2 0xA3 0xA4 0xA5 0xA6 0xA7 0xA8 0xA9 0xAA 0xAB 0xAC 0xAD 0xAE 0xAF )(list 0x280 0x284 0x288 0x28C 0x290 0x294 0x298 0x29C 0x2A0 0x2A4 0x2A8 0x2AC 0x2B0 0x2B4 0x2B8 0x2BC ) group.long ($2+0x1400)++0x3 line.long 0x0 "REGG5_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xB0 0xB1 0xB2 0xB3 0xB4 0xB5 0xB6 0xB7 0xB8 0xB9 0xBA 0xBB 0xBC 0xBD 0xBE 0xBF )(list 0x2C0 0x2C4 0x2C8 0x2CC 0x2D0 0x2D4 0x2D8 0x2DC 0x2E0 0x2E4 0x2E8 0x2EC 0x2F0 0x2F4 0x2F8 0x2FC ) group.long ($2+0x1400)++0x3 line.long 0x0 "REGG5_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xC0 0xC1 0xC2 0xC3 0xC4 0xC5 0xC6 0xC7 0xC8 0xC9 0xCA 0xCB 0xCC 0xCD 0xCE 0xCF )(list 0x300 0x304 0x308 0x30C 0x310 0x314 0x318 0x31C 0x320 0x324 0x328 0x32C 0x330 0x334 0x338 0x33C ) group.long ($2+0x1400)++0x3 line.long 0x0 "REGG5_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xD0 0xD1 0xD2 0xD3 0xD4 0xD5 0xD6 0xD7 0xD8 0xD9 0xDA 0xDB 0xDC 0xDD 0xDE 0xDF )(list 0x340 0x344 0x348 0x34C 0x350 0x354 0x358 0x35C 0x360 0x364 0x368 0x36C 0x370 0x374 0x378 0x37C ) group.long ($2+0x1400)++0x3 line.long 0x0 "REGG5_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xE0 0xE1 0xE2 0xE3 0xE4 0xE5 0xE6 0xE7 0xE8 0xE9 0xEA 0xEB 0xEC 0xED 0xEE 0xEF )(list 0x380 0x384 0x388 0x38C 0x390 0x394 0x398 0x39C 0x3A0 0x3A4 0x3A8 0x3AC 0x3B0 0x3B4 0x3B8 0x3BC ) group.long ($2+0x1400)++0x3 line.long 0x0 "REGG5_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xF0 0xF1 0xF2 0xF3 0xF4 0xF5 0xF6 0xF7 0xF8 0xF9 0xFA 0xFB 0xFC 0xFD 0xFE 0xFF )(list 0x3C0 0x3C4 0x3C8 0x3CC 0x3D0 0x3D4 0x3D8 0x3DC 0x3E0 0x3E4 0x3E8 0x3EC 0x3F0 0x3F4 0x3F8 0x3FC ) group.long ($2+0x1400)++0x3 line.long 0x0 "REGG5_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x4 0x8 0xC 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C ) group.long ($2+0x1800)++0x3 line.long 0x0 "REGG6_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1A 0x1B 0x1C 0x1D 0x1E 0x1F )(list 0x40 0x44 0x48 0x4C 0x50 0x54 0x58 0x5C 0x60 0x64 0x68 0x6C 0x70 0x74 0x78 0x7C ) group.long ($2+0x1800)++0x3 line.long 0x0 "REGG6_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x20 0x21 0x22 0x23 0x24 0x25 0x26 0x27 0x28 0x29 0x2A 0x2B 0x2C 0x2D 0x2E 0x2F )(list 0x80 0x84 0x88 0x8C 0x90 0x94 0x98 0x9C 0xA0 0xA4 0xA8 0xAC 0xB0 0xB4 0xB8 0xBC ) group.long ($2+0x1800)++0x3 line.long 0x0 "REGG6_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x30 0x31 0x32 0x33 0x34 0x35 0x36 0x37 0x38 0x39 0x3A 0x3B 0x3C 0x3D 0x3E 0x3F )(list 0xC0 0xC4 0xC8 0xCC 0xD0 0xD4 0xD8 0xDC 0xE0 0xE4 0xE8 0xEC 0xF0 0xF4 0xF8 0xFC ) group.long ($2+0x1800)++0x3 line.long 0x0 "REGG6_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x40 0x41 0x42 0x43 0x44 0x45 0x46 0x47 0x48 0x49 0x4A 0x4B 0x4C 0x4D 0x4E 0x4F )(list 0x100 0x104 0x108 0x10C 0x110 0x114 0x118 0x11C 0x120 0x124 0x128 0x12C 0x130 0x134 0x138 0x13C ) group.long ($2+0x1800)++0x3 line.long 0x0 "REGG6_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x50 0x51 0x52 0x53 0x54 0x55 0x56 0x57 0x58 0x59 0x5A 0x5B 0x5C 0x5D 0x5E 0x5F )(list 0x140 0x144 0x148 0x14C 0x150 0x154 0x158 0x15C 0x160 0x164 0x168 0x16C 0x170 0x174 0x178 0x17C ) group.long ($2+0x1800)++0x3 line.long 0x0 "REGG6_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x60 0x61 0x62 0x63 0x64 0x65 0x66 0x67 0x68 0x69 0x6A 0x6B 0x6C 0x6D 0x6E 0x6F )(list 0x180 0x184 0x188 0x18C 0x190 0x194 0x198 0x19C 0x1A0 0x1A4 0x1A8 0x1AC 0x1B0 0x1B4 0x1B8 0x1BC ) group.long ($2+0x1800)++0x3 line.long 0x0 "REGG6_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x70 0x71 0x72 0x73 0x74 0x75 0x76 0x77 0x78 0x79 0x7A 0x7B 0x7C 0x7D 0x7E 0x7F )(list 0x1C0 0x1C4 0x1C8 0x1CC 0x1D0 0x1D4 0x1D8 0x1DC 0x1E0 0x1E4 0x1E8 0x1EC 0x1F0 0x1F4 0x1F8 0x1FC ) group.long ($2+0x1800)++0x3 line.long 0x0 "REGG6_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x80 0x81 0x82 0x83 0x84 0x85 0x86 0x87 0x88 0x89 0x8A 0x8B 0x8C 0x8D 0x8E 0x8F )(list 0x200 0x204 0x208 0x20C 0x210 0x214 0x218 0x21C 0x220 0x224 0x228 0x22C 0x230 0x234 0x238 0x23C ) group.long ($2+0x1800)++0x3 line.long 0x0 "REGG6_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x90 0x91 0x92 0x93 0x94 0x95 0x96 0x97 0x98 0x99 0x9A 0x9B 0x9C 0x9D 0x9E 0x9F )(list 0x240 0x244 0x248 0x24C 0x250 0x254 0x258 0x25C 0x260 0x264 0x268 0x26C 0x270 0x274 0x278 0x27C ) group.long ($2+0x1800)++0x3 line.long 0x0 "REGG6_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xA0 0xA1 0xA2 0xA3 0xA4 0xA5 0xA6 0xA7 0xA8 0xA9 0xAA 0xAB 0xAC 0xAD 0xAE 0xAF )(list 0x280 0x284 0x288 0x28C 0x290 0x294 0x298 0x29C 0x2A0 0x2A4 0x2A8 0x2AC 0x2B0 0x2B4 0x2B8 0x2BC ) group.long ($2+0x1800)++0x3 line.long 0x0 "REGG6_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xB0 0xB1 0xB2 0xB3 0xB4 0xB5 0xB6 0xB7 0xB8 0xB9 0xBA 0xBB 0xBC 0xBD 0xBE 0xBF )(list 0x2C0 0x2C4 0x2C8 0x2CC 0x2D0 0x2D4 0x2D8 0x2DC 0x2E0 0x2E4 0x2E8 0x2EC 0x2F0 0x2F4 0x2F8 0x2FC ) group.long ($2+0x1800)++0x3 line.long 0x0 "REGG6_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xC0 0xC1 0xC2 0xC3 0xC4 0xC5 0xC6 0xC7 0xC8 0xC9 0xCA 0xCB 0xCC 0xCD 0xCE 0xCF )(list 0x300 0x304 0x308 0x30C 0x310 0x314 0x318 0x31C 0x320 0x324 0x328 0x32C 0x330 0x334 0x338 0x33C ) group.long ($2+0x1800)++0x3 line.long 0x0 "REGG6_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xD0 0xD1 0xD2 0xD3 0xD4 0xD5 0xD6 0xD7 0xD8 0xD9 0xDA 0xDB 0xDC 0xDD 0xDE 0xDF )(list 0x340 0x344 0x348 0x34C 0x350 0x354 0x358 0x35C 0x360 0x364 0x368 0x36C 0x370 0x374 0x378 0x37C ) group.long ($2+0x1800)++0x3 line.long 0x0 "REGG6_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xE0 0xE1 0xE2 0xE3 0xE4 0xE5 0xE6 0xE7 0xE8 0xE9 0xEA 0xEB 0xEC 0xED 0xEE 0xEF )(list 0x380 0x384 0x388 0x38C 0x390 0x394 0x398 0x39C 0x3A0 0x3A4 0x3A8 0x3AC 0x3B0 0x3B4 0x3B8 0x3BC ) group.long ($2+0x1800)++0x3 line.long 0x0 "REGG6_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xF0 0xF1 0xF2 0xF3 0xF4 0xF5 0xF6 0xF7 0xF8 0xF9 0xFA 0xFB 0xFC 0xFD 0xFE 0xFF )(list 0x3C0 0x3C4 0x3C8 0x3CC 0x3D0 0x3D4 0x3D8 0x3DC 0x3E0 0x3E4 0x3E8 0x3EC 0x3F0 0x3F4 0x3F8 0x3FC ) group.long ($2+0x1800)++0x3 line.long 0x0 "REGG6_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x4 0x8 0xC 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C ) group.long ($2+0x1C00)++0x3 line.long 0x0 "REGG7_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1A 0x1B 0x1C 0x1D 0x1E 0x1F )(list 0x40 0x44 0x48 0x4C 0x50 0x54 0x58 0x5C 0x60 0x64 0x68 0x6C 0x70 0x74 0x78 0x7C ) group.long ($2+0x1C00)++0x3 line.long 0x0 "REGG7_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x20 0x21 0x22 0x23 0x24 0x25 0x26 0x27 0x28 0x29 0x2A 0x2B 0x2C 0x2D 0x2E 0x2F )(list 0x80 0x84 0x88 0x8C 0x90 0x94 0x98 0x9C 0xA0 0xA4 0xA8 0xAC 0xB0 0xB4 0xB8 0xBC ) group.long ($2+0x1C00)++0x3 line.long 0x0 "REGG7_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x30 0x31 0x32 0x33 0x34 0x35 0x36 0x37 0x38 0x39 0x3A 0x3B 0x3C 0x3D 0x3E 0x3F )(list 0xC0 0xC4 0xC8 0xCC 0xD0 0xD4 0xD8 0xDC 0xE0 0xE4 0xE8 0xEC 0xF0 0xF4 0xF8 0xFC ) group.long ($2+0x1C00)++0x3 line.long 0x0 "REGG7_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x40 0x41 0x42 0x43 0x44 0x45 0x46 0x47 0x48 0x49 0x4A 0x4B 0x4C 0x4D 0x4E 0x4F )(list 0x100 0x104 0x108 0x10C 0x110 0x114 0x118 0x11C 0x120 0x124 0x128 0x12C 0x130 0x134 0x138 0x13C ) group.long ($2+0x1C00)++0x3 line.long 0x0 "REGG7_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x50 0x51 0x52 0x53 0x54 0x55 0x56 0x57 0x58 0x59 0x5A 0x5B 0x5C 0x5D 0x5E 0x5F )(list 0x140 0x144 0x148 0x14C 0x150 0x154 0x158 0x15C 0x160 0x164 0x168 0x16C 0x170 0x174 0x178 0x17C ) group.long ($2+0x1C00)++0x3 line.long 0x0 "REGG7_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x60 0x61 0x62 0x63 0x64 0x65 0x66 0x67 0x68 0x69 0x6A 0x6B 0x6C 0x6D 0x6E 0x6F )(list 0x180 0x184 0x188 0x18C 0x190 0x194 0x198 0x19C 0x1A0 0x1A4 0x1A8 0x1AC 0x1B0 0x1B4 0x1B8 0x1BC ) group.long ($2+0x1C00)++0x3 line.long 0x0 "REGG7_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x70 0x71 0x72 0x73 0x74 0x75 0x76 0x77 0x78 0x79 0x7A 0x7B 0x7C 0x7D 0x7E 0x7F )(list 0x1C0 0x1C4 0x1C8 0x1CC 0x1D0 0x1D4 0x1D8 0x1DC 0x1E0 0x1E4 0x1E8 0x1EC 0x1F0 0x1F4 0x1F8 0x1FC ) group.long ($2+0x1C00)++0x3 line.long 0x0 "REGG7_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x80 0x81 0x82 0x83 0x84 0x85 0x86 0x87 0x88 0x89 0x8A 0x8B 0x8C 0x8D 0x8E 0x8F )(list 0x200 0x204 0x208 0x20C 0x210 0x214 0x218 0x21C 0x220 0x224 0x228 0x22C 0x230 0x234 0x238 0x23C ) group.long ($2+0x1C00)++0x3 line.long 0x0 "REGG7_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x90 0x91 0x92 0x93 0x94 0x95 0x96 0x97 0x98 0x99 0x9A 0x9B 0x9C 0x9D 0x9E 0x9F )(list 0x240 0x244 0x248 0x24C 0x250 0x254 0x258 0x25C 0x260 0x264 0x268 0x26C 0x270 0x274 0x278 0x27C ) group.long ($2+0x1C00)++0x3 line.long 0x0 "REGG7_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xA0 0xA1 0xA2 0xA3 0xA4 0xA5 0xA6 0xA7 0xA8 0xA9 0xAA 0xAB 0xAC 0xAD 0xAE 0xAF )(list 0x280 0x284 0x288 0x28C 0x290 0x294 0x298 0x29C 0x2A0 0x2A4 0x2A8 0x2AC 0x2B0 0x2B4 0x2B8 0x2BC ) group.long ($2+0x1C00)++0x3 line.long 0x0 "REGG7_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xB0 0xB1 0xB2 0xB3 0xB4 0xB5 0xB6 0xB7 0xB8 0xB9 0xBA 0xBB 0xBC 0xBD 0xBE 0xBF )(list 0x2C0 0x2C4 0x2C8 0x2CC 0x2D0 0x2D4 0x2D8 0x2DC 0x2E0 0x2E4 0x2E8 0x2EC 0x2F0 0x2F4 0x2F8 0x2FC ) group.long ($2+0x1C00)++0x3 line.long 0x0 "REGG7_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xC0 0xC1 0xC2 0xC3 0xC4 0xC5 0xC6 0xC7 0xC8 0xC9 0xCA 0xCB 0xCC 0xCD 0xCE 0xCF )(list 0x300 0x304 0x308 0x30C 0x310 0x314 0x318 0x31C 0x320 0x324 0x328 0x32C 0x330 0x334 0x338 0x33C ) group.long ($2+0x1C00)++0x3 line.long 0x0 "REGG7_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xD0 0xD1 0xD2 0xD3 0xD4 0xD5 0xD6 0xD7 0xD8 0xD9 0xDA 0xDB 0xDC 0xDD 0xDE 0xDF )(list 0x340 0x344 0x348 0x34C 0x350 0x354 0x358 0x35C 0x360 0x364 0x368 0x36C 0x370 0x374 0x378 0x37C ) group.long ($2+0x1C00)++0x3 line.long 0x0 "REGG7_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xE0 0xE1 0xE2 0xE3 0xE4 0xE5 0xE6 0xE7 0xE8 0xE9 0xEA 0xEB 0xEC 0xED 0xEE 0xEF )(list 0x380 0x384 0x388 0x38C 0x390 0x394 0x398 0x39C 0x3A0 0x3A4 0x3A8 0x3AC 0x3B0 0x3B4 0x3B8 0x3BC ) group.long ($2+0x1C00)++0x3 line.long 0x0 "REGG7_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xF0 0xF1 0xF2 0xF3 0xF4 0xF5 0xF6 0xF7 0xF8 0xF9 0xFA 0xFB 0xFC 0xFD 0xFE 0xFF )(list 0x3C0 0x3C4 0x3C8 0x3CC 0x3D0 0x3D4 0x3D8 0x3DC 0x3E0 0x3E4 0x3E8 0x3EC 0x3F0 0x3F4 0x3F8 0x3FC ) group.long ($2+0x1C00)++0x3 line.long 0x0 "REGG7_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end group.long 0x2000++0x17 line.long 0x0 "GLB_CTL,This register provides global enable settings for permission control." bitfld.long 0x0 5. "DOM_CFG_LOCK,Lock write for DOM_CFG_MODE bit." "0,1" bitfld.long 0x0 4. "DOM_CFG_MODE,When enabled all the source setting can be configured by master from domain 0 if it is not locked. When disabled only resource manager can configure the permission of the resource." "0,1" bitfld.long 0x0 3. "PERCK_DIS_LOCK,Lock write for PERCK_DIS" "0,1" bitfld.long 0x0 2. "PERCK_DIS,All the permission check disable." "0,1" newline bitfld.long 0x0 1. "DOM_PRO_LOCK,Lock write for DOM_PRO_EN bit." "0,1" bitfld.long 0x0 0. "DOM_PRO_EN,When disabled no domain access permission check" "0,1" line.long 0x4 "RES_MGR,Resource manager register. This regster is used to assign resource manager for global resource access control" bitfld.long 0x4 17. "MID_LOCK,Lock write for MID_EN and MID_LOW and MID_HIG registers." "0,1" bitfld.long 0x4 16. "MID_EN,Master ID check enable" "0,1" bitfld.long 0x4 15. "PRI_PER_LOCK,Lock write for PRI_PER and PRI_PER_EN" "0,1" bitfld.long 0x4 13.--14. "PRI_PER,Resource manager privileged access permission. bit0 for privileged access bit1 for user access" "0,1,2,3" newline bitfld.long 0x4 12. "PRI_PER_EN,Resource manager privileged access permission enable." "0,1" bitfld.long 0x4 11. "SEC_PER_LOCK,Lock for SEC_PER and SEC_PER_LOCK" "0,1" bitfld.long 0x4 9.--10. "SEC_PER,Resource manager secure access permission. bit 0 for secure access bit 1 for non-secure access" "0,1,2,3" bitfld.long 0x4 8. "SEC_PER_EN,Resource manager secure permission enable" "0,1" bitfld.long 0x4 7. "DID_LOCK,Lock write for DID_EN and DID" "0,1" newline hexmask.long.byte 0x4 3.--6. 1. "DID,Resource manager domain ID" bitfld.long 0x4 2. "DID_EN,Resource manager Domain ID enable" "0,1" bitfld.long 0x4 1. "RES_MGR_EN_LOCK,Lock for RES_MGR_EN" "0,1" bitfld.long 0x4 0. "RES_MGR_EN,Resource manager enable. When the bit is disable there is no resource manager." "0,1" line.long 0x8 "RES_MGR_MA0,This register is used to assign master 0~31 as resource manager." hexmask.long 0x8 0.--31. 1. "MID,Assign master 0~31 for resource manager" line.long 0xC "RES_MGR_MA1,This register is used to assign master 32~63 as resource manager." hexmask.long 0xC 0.--31. 1. "MID,Indicate if master 32~63 is resource manager." line.long 0x10 "RES_MGR_MA2,This register is used to assign master 64~95 as resource manager." hexmask.long 0x10 0.--31. 1. "MID,Indicate if master 64~95 is resource manager." line.long 0x14 "RES_MGR_MA3,This register is used to assign master 96~127 as resource manager." hexmask.long 0x14 0.--31. 1. "MID,Indicate if master 96~127 is resource manager." repeat 8. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 )(list 0x0 0x14 0x28 0x3C 0x50 0x64 0x78 0x8C ) group.long ($2+0x2100)++0x3 line.long 0x0 "GRP_MGR_$1,Group Manager Register. This register is used to assign group manager for each domain" bitfld.long 0x0 17. "MID_LOCK,Lock write for MID_EN and MID_LOW and MID_HIG registers." "0,1" bitfld.long 0x0 16. "MID_EN,Master ID check enable" "0,1" bitfld.long 0x0 15. "PRI_PER_LOCK,Lock write for PRI_PER and PRI_PER_EN" "0,1" bitfld.long 0x0 13.--14. "PRI_PER,Group manager privileged access permission. bit0 for privileged access bit1 for user access" "0,1,2,3" newline bitfld.long 0x0 12. "PRI_PER_EN,Group manager privileged access permission enable." "0,1" bitfld.long 0x0 11. "SEC_PER_LOCK,Lock for SEC_PER and SEC_PER_LOCK" "0,1" bitfld.long 0x0 9.--10. "SEC_PER,Group manager secure access permission. bit 0 for secure access bit 1 for non-secure access" "0,1,2,3" bitfld.long 0x0 8. "SEC_PER_EN,Group manager secure permission enable" "0,1" bitfld.long 0x0 7. "DID_LOCK,Lock write for DID_EN and DID" "0,1" newline hexmask.long.byte 0x0 3.--6. 1. "DID,Group manager domain ID" bitfld.long 0x0 2. "DID_EN,Group manager Domain ID enable" "0,1" bitfld.long 0x0 1. "GRP_MGR_EN_LOCK,Lock write for GPR_MGR_EN" "0,1" bitfld.long 0x0 0. "GRP_MGR_EN,Group manager enable. When the bit is disable there is no resource manager." "0,1" repeat.end repeat 8. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 )(list 0x0 0x14 0x28 0x3C 0x50 0x64 0x78 0x8C ) group.long ($2+0x2104)++0x3 line.long 0x0 "GRP_MGR_MA0_$1,Assign master 0~31 for group manager 0" hexmask.long 0x0 0.--31. 1. "MID,Assign master 0~31 for resource manager" repeat.end repeat 8. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 )(list 0x0 0x14 0x28 0x3C 0x50 0x64 0x78 0x8C ) group.long ($2+0x2108)++0x3 line.long 0x0 "GRP_MGR_MA1_$1,Assign master 32~63 for group manager 0" hexmask.long 0x0 0.--31. 1. "MID,Indicate if master 32~63 is resource manager." repeat.end repeat 8. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 )(list 0x0 0x14 0x28 0x3C 0x50 0x64 0x78 0x8C ) group.long ($2+0x210C)++0x3 line.long 0x0 "GRP_MGR_MA2_$1,Assign master 64~95 for group manager 0" hexmask.long 0x0 0.--31. 1. "MID,Indicate if master 64~95 is resource manager." repeat.end repeat 8. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 )(list 0x0 0x14 0x28 0x3C 0x50 0x64 0x78 0x8C ) group.long ($2+0x2110)++0x3 line.long 0x0 "GRP_MGR_MA3_$1,Assign master 96~127 for group manager 0" hexmask.long 0x0 0.--31. 1. "MID,Indicate if master 96~127 is resource manager." repeat.end group.long 0x2200++0x3 line.long 0x0 "DOM_GID_0,Indicate which group domain 0 belong to" bitfld.long 0x0 3. "LOCK,Lock write for GID" "0,1" bitfld.long 0x0 0.--2. "GID,Group ID" "0,1,2,3,4,5,6,7" repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x18 0x30 0x48 0x60 0x78 0x90 0xA8 0xC0 0xD8 0xF0 0x108 0x120 0x138 0x150 0x168 ) group.long ($2+0x2204)++0x3 line.long 0x0 "DOM_OWN_$1,Assign owner for function domain 0." bitfld.long 0x0 17. "MID_LOCK,Lock write for MID_EN and MID_LOW and MID_HIG registers." "0,1" bitfld.long 0x0 16. "MID_EN,Master ID check enable" "0,1" bitfld.long 0x0 15. "PRI_PER_LOCK,Lock write for PRI_PER and PRI_PER_EN" "0,1" bitfld.long 0x0 13.--14. "PRI_PER,Group manager privileged access permission. bit0 for privileged access bit1 for user access" "0,1,2,3" newline bitfld.long 0x0 12. "PRI_PER_EN,Group manager privileged access permission enable." "0,1" bitfld.long 0x0 11. "SEC_PER_LOCK,Lock for SEC_PER and SEC_PER_LOCK" "0,1" bitfld.long 0x0 9.--10. "SEC_PER,Domain owner secure access permission. bit 0 for secure access bit 1 for non-secure access" "0,1,2,3" bitfld.long 0x0 8. "SEC_PER_EN,Domain owner secure permission enable" "0,1" newline bitfld.long 0x0 1. "DOM_OWN_EN_LOCK,Lock for DOM_OWN_EN" "0,1" bitfld.long 0x0 0. "DOM_OWN_EN,Domain owner enable. When the bit is disable there is no domain owner." "0,1" repeat.end repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x18 0x30 0x48 0x60 0x78 0x90 0xA8 0xC0 0xD8 0xF0 0x108 0x120 0x138 0x150 0x168 ) group.long ($2+0x2208)++0x3 line.long 0x0 "DOM_OWN_MA0_$1,Assign master 0~31 for domain owner 0" hexmask.long 0x0 0.--31. 1. "MID,Assign master 0~31 for resource manager" repeat.end repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x18 0x30 0x48 0x60 0x78 0x90 0xA8 0xC0 0xD8 0xF0 0x108 0x120 0x138 0x150 0x168 ) group.long ($2+0x220C)++0x3 line.long 0x0 "DOM_OWN_MA1_$1,Assign master 32~63 for domain owner 0" hexmask.long 0x0 0.--31. 1. "MID,Indicate if master 32~63 is resource manager." repeat.end repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x18 0x30 0x48 0x60 0x78 0x90 0xA8 0xC0 0xD8 0xF0 0x108 0x120 0x138 0x150 0x168 ) group.long ($2+0x2210)++0x3 line.long 0x0 "DOM_OWN_MA2_$1,Assign master 64~95 for domain owner 0" hexmask.long 0x0 0.--31. 1. "MID,Indicate if master 64~95 is resource manager." repeat.end repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x18 0x30 0x48 0x60 0x78 0x90 0xA8 0xC0 0xD8 0xF0 0x108 0x120 0x138 0x150 0x168 ) group.long ($2+0x2214)++0x3 line.long 0x0 "DOM_OWN_MA3_$1,Assign master 96~127 for domain owner 0" hexmask.long 0x0 0.--31. 1. "MID,Indicate if master 96~127 is resource manager." repeat.end group.long 0x2218++0x3 line.long 0x0 "DOM_GID_1,Indicate which group domain 1 belong to" bitfld.long 0x0 3. "LOCK,Lock write for GID" "0,1" bitfld.long 0x0 0.--2. "GID,Group ID" "0,1,2,3,4,5,6,7" group.long 0x2230++0x3 line.long 0x0 "DOM_GID_2,Indicate which group domain 2 belong to" bitfld.long 0x0 3. "LOCK,Lock write for GID" "0,1" bitfld.long 0x0 0.--2. "GID,Group ID" "0,1,2,3,4,5,6,7" group.long 0x2248++0x3 line.long 0x0 "DOM_GID_3,Indicate which group domain 3 belong to" bitfld.long 0x0 3. "LOCK,Lock write for GID" "0,1" bitfld.long 0x0 0.--2. "GID,Group ID" "0,1,2,3,4,5,6,7" group.long 0x2260++0x3 line.long 0x0 "DOM_GID_4,Indicate which group domain 4 belong to" bitfld.long 0x0 3. "LOCK,Lock write for GID" "0,1" bitfld.long 0x0 0.--2. "GID,Group ID" "0,1,2,3,4,5,6,7" group.long 0x2278++0x3 line.long 0x0 "DOM_GID_5,Indicate which group domain 5 belong to" bitfld.long 0x0 3. "LOCK,Lock write for GID" "0,1" bitfld.long 0x0 0.--2. "GID,Group ID" "0,1,2,3,4,5,6,7" group.long 0x2290++0x3 line.long 0x0 "DOM_GID_6,Indicate which group domain 6 belong to" bitfld.long 0x0 3. "LOCK,Lock write for GID" "0,1" bitfld.long 0x0 0.--2. "GID,Group ID" "0,1,2,3,4,5,6,7" group.long 0x22A8++0x3 line.long 0x0 "DOM_GID_7,Indicate which group domain 7 belong to" bitfld.long 0x0 3. "LOCK,Lock write for GID" "0,1" bitfld.long 0x0 0.--2. "GID,Group ID" "0,1,2,3,4,5,6,7" group.long 0x22C0++0x3 line.long 0x0 "DOM_GID_8,Indicate which group domain 8 belong to" bitfld.long 0x0 3. "LOCK,Lock write for GID" "0,1" bitfld.long 0x0 0.--2. "GID,Group ID" "0,1,2,3,4,5,6,7" group.long 0x22D8++0x3 line.long 0x0 "DOM_GID_9,Indicate which group domain 9 belong to" bitfld.long 0x0 3. "LOCK,Lock write for GID" "0,1" bitfld.long 0x0 0.--2. "GID,Group ID" "0,1,2,3,4,5,6,7" group.long 0x22F0++0x3 line.long 0x0 "DOM_GID_10,Indicate which group domain 10 belong to" bitfld.long 0x0 3. "LOCK,Lock write for GID" "0,1" bitfld.long 0x0 0.--2. "GID,Group ID" "0,1,2,3,4,5,6,7" group.long 0x2308++0x3 line.long 0x0 "DOM_GID_11,Indicate which group domain 11 belong to" bitfld.long 0x0 3. "LOCK,Lock write for GID" "0,1" bitfld.long 0x0 0.--2. "GID,Group ID" "0,1,2,3,4,5,6,7" group.long 0x2320++0x3 line.long 0x0 "DOM_GID_12,Indicate which group domain 12 belong to" bitfld.long 0x0 3. "LOCK,Lock write for GID" "0,1" bitfld.long 0x0 0.--2. "GID,Group ID" "0,1,2,3,4,5,6,7" group.long 0x2338++0x3 line.long 0x0 "DOM_GID_13,Indicate which group domain 13 belong to" bitfld.long 0x0 3. "LOCK,Lock write for GID" "0,1" bitfld.long 0x0 0.--2. "GID,Group ID" "0,1,2,3,4,5,6,7" group.long 0x2350++0x3 line.long 0x0 "DOM_GID_14,Indicate which group domain 14 belong to" bitfld.long 0x0 3. "LOCK,Lock write for GID" "0,1" bitfld.long 0x0 0.--2. "GID,Group ID" "0,1,2,3,4,5,6,7" group.long 0x2368++0x3 line.long 0x0 "DOM_GID_15,Indicate which group domain 15 belong to" bitfld.long 0x0 3. "LOCK,Lock write for GID" "0,1" bitfld.long 0x0 0.--2. "GID,Group ID" "0,1,2,3,4,5,6,7" repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x34 0x68 0x9C 0xD0 0x104 0x138 0x16C 0x1A0 0x1D4 0x208 0x23C 0x270 0x2A4 0x2D8 0x30C ) group.long ($2+0x2400)++0x3 line.long 0x0 "DOM_PER0_$1,Domain Permission Control. It can be only configured by resource manager and domain owner." bitfld.long 0x0 31. "DOM7_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 29.--30. "DOM7_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 28. "DOM7_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 27. "DOM6_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 25.--26. "DOM6_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" newline bitfld.long 0x0 24. "DOM6_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 23. "DOM5_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 21.--22. "DOM5_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 20. "DOM5_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 19. "DOM4_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" newline bitfld.long 0x0 17.--18. "DOM4_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM4_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 15. "DOM3_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 13.--14. "DOM3_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 12. "DOM3_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" newline bitfld.long 0x0 11. "DOM2_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 9.--10. "DOM2_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM2_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 7. "DOM1_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 5.--6. "DOM1_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" newline bitfld.long 0x0 4. "DOM1_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 3. "DOM0_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 1.--2. "DOM0_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM0_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" repeat.end repeat 16. (list 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1A 0x1B 0x1C 0x1D 0x1E 0x1F )(list 0x340 0x374 0x3A8 0x3DC 0x410 0x444 0x478 0x4AC 0x4E0 0x514 0x548 0x57C 0x5B0 0x5E4 0x618 0x64C ) group.long ($2+0x2400)++0x3 line.long 0x0 "DOM_PER0_$1,Domain Permission Control. It can be only configured by resource manager and domain owner." bitfld.long 0x0 31. "DOM7_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 29.--30. "DOM7_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 28. "DOM7_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 27. "DOM6_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 25.--26. "DOM6_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" newline bitfld.long 0x0 24. "DOM6_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 23. "DOM5_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 21.--22. "DOM5_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 20. "DOM5_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 19. "DOM4_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" newline bitfld.long 0x0 17.--18. "DOM4_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM4_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 15. "DOM3_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 13.--14. "DOM3_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 12. "DOM3_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" newline bitfld.long 0x0 11. "DOM2_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 9.--10. "DOM2_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM2_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 7. "DOM1_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 5.--6. "DOM1_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" newline bitfld.long 0x0 4. "DOM1_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 3. "DOM0_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 1.--2. "DOM0_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM0_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" repeat.end repeat 16. (list 0x20 0x21 0x22 0x23 0x24 0x25 0x26 0x27 0x28 0x29 0x2A 0x2B 0x2C 0x2D 0x2E 0x2F )(list 0x680 0x6B4 0x6E8 0x71C 0x750 0x784 0x7B8 0x7EC 0x820 0x854 0x888 0x8BC 0x8F0 0x924 0x958 0x98C ) group.long ($2+0x2400)++0x3 line.long 0x0 "DOM_PER0_$1,Domain Permission Control. It can be only configured by resource manager and domain owner." bitfld.long 0x0 31. "DOM7_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 29.--30. "DOM7_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 28. "DOM7_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 27. "DOM6_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 25.--26. "DOM6_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" newline bitfld.long 0x0 24. "DOM6_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 23. "DOM5_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 21.--22. "DOM5_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 20. "DOM5_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 19. "DOM4_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" newline bitfld.long 0x0 17.--18. "DOM4_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM4_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 15. "DOM3_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 13.--14. "DOM3_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 12. "DOM3_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" newline bitfld.long 0x0 11. "DOM2_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 9.--10. "DOM2_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM2_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 7. "DOM1_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 5.--6. "DOM1_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" newline bitfld.long 0x0 4. "DOM1_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 3. "DOM0_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 1.--2. "DOM0_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM0_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" repeat.end repeat 16. (list 0x30 0x31 0x32 0x33 0x34 0x35 0x36 0x37 0x38 0x39 0x3A 0x3B 0x3C 0x3D 0x3E 0x3F )(list 0x9C0 0x9F4 0xA28 0xA5C 0xA90 0xAC4 0xAF8 0xB2C 0xB60 0xB94 0xBC8 0xBFC 0xC30 0xC64 0xC98 0xCCC ) group.long ($2+0x2400)++0x3 line.long 0x0 "DOM_PER0_$1,Domain Permission Control. It can be only configured by resource manager and domain owner." bitfld.long 0x0 31. "DOM7_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 29.--30. "DOM7_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 28. "DOM7_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 27. "DOM6_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 25.--26. "DOM6_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" newline bitfld.long 0x0 24. "DOM6_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 23. "DOM5_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 21.--22. "DOM5_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 20. "DOM5_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 19. "DOM4_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" newline bitfld.long 0x0 17.--18. "DOM4_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM4_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 15. "DOM3_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 13.--14. "DOM3_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 12. "DOM3_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" newline bitfld.long 0x0 11. "DOM2_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 9.--10. "DOM2_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM2_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 7. "DOM1_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 5.--6. "DOM1_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" newline bitfld.long 0x0 4. "DOM1_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 3. "DOM0_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 1.--2. "DOM0_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM0_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" repeat.end repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x34 0x68 0x9C 0xD0 0x104 0x138 0x16C 0x1A0 0x1D4 0x208 0x23C 0x270 0x2A4 0x2D8 0x30C ) group.long ($2+0x2404)++0x3 line.long 0x0 "DOM_PER1_$1,Domain Permission Control. It can be only configured by resource manager and domain owner." bitfld.long 0x0 31. "DOM15_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 29.--30. "DOM15_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 28. "DOM15_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 27. "DOM14_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 25.--26. "DOM14_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" newline bitfld.long 0x0 24. "DOM14_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 23. "DOM13_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 21.--22. "DOM13_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 20. "DOM13_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 19. "DOM12_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" newline bitfld.long 0x0 17.--18. "DOM12_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM12_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 15. "DOM11_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 13.--14. "DOM11_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 12. "DOM11_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" newline bitfld.long 0x0 11. "DOM10_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 9.--10. "DOM10_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM10_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 7. "DOM9_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 5.--6. "DOM9_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" newline bitfld.long 0x0 4. "DOM9_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 3. "DOM8_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 1.--2. "DOM8_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM8_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" repeat.end repeat 16. (list 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1A 0x1B 0x1C 0x1D 0x1E 0x1F )(list 0x340 0x374 0x3A8 0x3DC 0x410 0x444 0x478 0x4AC 0x4E0 0x514 0x548 0x57C 0x5B0 0x5E4 0x618 0x64C ) group.long ($2+0x2404)++0x3 line.long 0x0 "DOM_PER1_$1,Domain Permission Control. It can be only configured by resource manager and domain owner." bitfld.long 0x0 31. "DOM15_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 29.--30. "DOM15_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 28. "DOM15_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 27. "DOM14_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 25.--26. "DOM14_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" newline bitfld.long 0x0 24. "DOM14_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 23. "DOM13_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 21.--22. "DOM13_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 20. "DOM13_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 19. "DOM12_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" newline bitfld.long 0x0 17.--18. "DOM12_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM12_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 15. "DOM11_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 13.--14. "DOM11_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 12. "DOM11_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" newline bitfld.long 0x0 11. "DOM10_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 9.--10. "DOM10_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM10_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 7. "DOM9_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 5.--6. "DOM9_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" newline bitfld.long 0x0 4. "DOM9_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 3. "DOM8_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 1.--2. "DOM8_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM8_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" repeat.end repeat 16. (list 0x20 0x21 0x22 0x23 0x24 0x25 0x26 0x27 0x28 0x29 0x2A 0x2B 0x2C 0x2D 0x2E 0x2F )(list 0x680 0x6B4 0x6E8 0x71C 0x750 0x784 0x7B8 0x7EC 0x820 0x854 0x888 0x8BC 0x8F0 0x924 0x958 0x98C ) group.long ($2+0x2404)++0x3 line.long 0x0 "DOM_PER1_$1,Domain Permission Control. It can be only configured by resource manager and domain owner." bitfld.long 0x0 31. "DOM15_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 29.--30. "DOM15_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 28. "DOM15_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 27. "DOM14_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 25.--26. "DOM14_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" newline bitfld.long 0x0 24. "DOM14_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 23. "DOM13_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 21.--22. "DOM13_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 20. "DOM13_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 19. "DOM12_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" newline bitfld.long 0x0 17.--18. "DOM12_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM12_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 15. "DOM11_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 13.--14. "DOM11_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 12. "DOM11_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" newline bitfld.long 0x0 11. "DOM10_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 9.--10. "DOM10_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM10_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 7. "DOM9_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 5.--6. "DOM9_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" newline bitfld.long 0x0 4. "DOM9_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 3. "DOM8_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 1.--2. "DOM8_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM8_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" repeat.end repeat 16. (list 0x30 0x31 0x32 0x33 0x34 0x35 0x36 0x37 0x38 0x39 0x3A 0x3B 0x3C 0x3D 0x3E 0x3F )(list 0x9C0 0x9F4 0xA28 0xA5C 0xA90 0xAC4 0xAF8 0xB2C 0xB60 0xB94 0xBC8 0xBFC 0xC30 0xC64 0xC98 0xCCC ) group.long ($2+0x2404)++0x3 line.long 0x0 "DOM_PER1_$1,Domain Permission Control. It can be only configured by resource manager and domain owner." bitfld.long 0x0 31. "DOM15_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 29.--30. "DOM15_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 28. "DOM15_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 27. "DOM14_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 25.--26. "DOM14_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" newline bitfld.long 0x0 24. "DOM14_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 23. "DOM13_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 21.--22. "DOM13_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 20. "DOM13_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 19. "DOM12_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" newline bitfld.long 0x0 17.--18. "DOM12_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM12_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 15. "DOM11_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 13.--14. "DOM11_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 12. "DOM11_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" newline bitfld.long 0x0 11. "DOM10_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 9.--10. "DOM10_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM10_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 7. "DOM9_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 5.--6. "DOM9_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" newline bitfld.long 0x0 4. "DOM9_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 3. "DOM8_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 1.--2. "DOM8_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM8_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" repeat.end repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x34 0x68 0x9C 0xD0 0x104 0x138 0x16C 0x1A0 0x1D4 0x208 0x23C 0x270 0x2A4 0x2D8 0x30C ) group.long ($2+0x2408)++0x3 line.long 0x0 "SEC_PER0_$1,This register is only used for resource manager to control secure access permission." bitfld.long 0x0 31. "DOM3_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM3_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM3_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM3_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM2_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM2_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM2_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM2_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM1_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM1_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM1_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM1_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM0_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM0_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM0_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM0_SEC_EN,Domain secure permission control enable" "0,1" repeat.end repeat 16. (list 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1A 0x1B 0x1C 0x1D 0x1E 0x1F )(list 0x340 0x374 0x3A8 0x3DC 0x410 0x444 0x478 0x4AC 0x4E0 0x514 0x548 0x57C 0x5B0 0x5E4 0x618 0x64C ) group.long ($2+0x2408)++0x3 line.long 0x0 "SEC_PER0_$1,This register is only used for resource manager to control secure access permission." bitfld.long 0x0 31. "DOM3_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM3_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM3_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM3_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM2_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM2_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM2_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM2_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM1_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM1_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM1_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM1_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM0_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM0_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM0_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM0_SEC_EN,Domain secure permission control enable" "0,1" repeat.end repeat 16. (list 0x20 0x21 0x22 0x23 0x24 0x25 0x26 0x27 0x28 0x29 0x2A 0x2B 0x2C 0x2D 0x2E 0x2F )(list 0x680 0x6B4 0x6E8 0x71C 0x750 0x784 0x7B8 0x7EC 0x820 0x854 0x888 0x8BC 0x8F0 0x924 0x958 0x98C ) group.long ($2+0x2408)++0x3 line.long 0x0 "SEC_PER0_$1,This register is only used for resource manager to control secure access permission." bitfld.long 0x0 31. "DOM3_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM3_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM3_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM3_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM2_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM2_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM2_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM2_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM1_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM1_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM1_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM1_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM0_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM0_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM0_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM0_SEC_EN,Domain secure permission control enable" "0,1" repeat.end repeat 16. (list 0x30 0x31 0x32 0x33 0x34 0x35 0x36 0x37 0x38 0x39 0x3A 0x3B 0x3C 0x3D 0x3E 0x3F )(list 0x9C0 0x9F4 0xA28 0xA5C 0xA90 0xAC4 0xAF8 0xB2C 0xB60 0xB94 0xBC8 0xBFC 0xC30 0xC64 0xC98 0xCCC ) group.long ($2+0x2408)++0x3 line.long 0x0 "SEC_PER0_$1,This register is only used for resource manager to control secure access permission." bitfld.long 0x0 31. "DOM3_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM3_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM3_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM3_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM2_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM2_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM2_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM2_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM1_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM1_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM1_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM1_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM0_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM0_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM0_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM0_SEC_EN,Domain secure permission control enable" "0,1" repeat.end repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x34 0x68 0x9C 0xD0 0x104 0x138 0x16C 0x1A0 0x1D4 0x208 0x23C 0x270 0x2A4 0x2D8 0x30C ) group.long ($2+0x240C)++0x3 line.long 0x0 "SEC_PER1_$1,This register is only used for resource manager to control secure access permission." bitfld.long 0x0 31. "DOM7_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM7_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM7_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM7_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM6_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM6_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM6_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM6_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM5_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM5_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM5_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM5_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM4_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM4_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM4_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM4_SEC_EN,Domain secure permission control enable" "0,1" repeat.end repeat 16. (list 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1A 0x1B 0x1C 0x1D 0x1E 0x1F )(list 0x340 0x374 0x3A8 0x3DC 0x410 0x444 0x478 0x4AC 0x4E0 0x514 0x548 0x57C 0x5B0 0x5E4 0x618 0x64C ) group.long ($2+0x240C)++0x3 line.long 0x0 "SEC_PER1_$1,This register is only used for resource manager to control secure access permission." bitfld.long 0x0 31. "DOM7_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM7_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM7_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM7_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM6_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM6_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM6_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM6_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM5_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM5_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM5_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM5_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM4_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM4_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM4_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM4_SEC_EN,Domain secure permission control enable" "0,1" repeat.end repeat 16. (list 0x20 0x21 0x22 0x23 0x24 0x25 0x26 0x27 0x28 0x29 0x2A 0x2B 0x2C 0x2D 0x2E 0x2F )(list 0x680 0x6B4 0x6E8 0x71C 0x750 0x784 0x7B8 0x7EC 0x820 0x854 0x888 0x8BC 0x8F0 0x924 0x958 0x98C ) group.long ($2+0x240C)++0x3 line.long 0x0 "SEC_PER1_$1,This register is only used for resource manager to control secure access permission." bitfld.long 0x0 31. "DOM7_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM7_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM7_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM7_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM6_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM6_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM6_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM6_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM5_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM5_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM5_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM5_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM4_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM4_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM4_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM4_SEC_EN,Domain secure permission control enable" "0,1" repeat.end repeat 16. (list 0x30 0x31 0x32 0x33 0x34 0x35 0x36 0x37 0x38 0x39 0x3A 0x3B 0x3C 0x3D 0x3E 0x3F )(list 0x9C0 0x9F4 0xA28 0xA5C 0xA90 0xAC4 0xAF8 0xB2C 0xB60 0xB94 0xBC8 0xBFC 0xC30 0xC64 0xC98 0xCCC ) group.long ($2+0x240C)++0x3 line.long 0x0 "SEC_PER1_$1,This register is only used for resource manager to control secure access permission." bitfld.long 0x0 31. "DOM7_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM7_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM7_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM7_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM6_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM6_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM6_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM6_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM5_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM5_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM5_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM5_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM4_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM4_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM4_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM4_SEC_EN,Domain secure permission control enable" "0,1" repeat.end repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x34 0x68 0x9C 0xD0 0x104 0x138 0x16C 0x1A0 0x1D4 0x208 0x23C 0x270 0x2A4 0x2D8 0x30C ) group.long ($2+0x2410)++0x3 line.long 0x0 "SEC_PER2_$1,This register is only used for resource manager to control secure access permission." bitfld.long 0x0 31. "DOM11_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM11_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM11_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM11_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM10_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM10_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM10_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM10_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM9_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM9_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM9_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM9_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM8_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM8_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM8_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM8_SEC_EN,Domain secure permission control enable" "0,1" repeat.end repeat 16. (list 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1A 0x1B 0x1C 0x1D 0x1E 0x1F )(list 0x340 0x374 0x3A8 0x3DC 0x410 0x444 0x478 0x4AC 0x4E0 0x514 0x548 0x57C 0x5B0 0x5E4 0x618 0x64C ) group.long ($2+0x2410)++0x3 line.long 0x0 "SEC_PER2_$1,This register is only used for resource manager to control secure access permission." bitfld.long 0x0 31. "DOM11_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM11_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM11_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM11_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM10_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM10_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM10_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM10_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM9_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM9_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM9_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM9_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM8_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM8_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM8_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM8_SEC_EN,Domain secure permission control enable" "0,1" repeat.end repeat 16. (list 0x20 0x21 0x22 0x23 0x24 0x25 0x26 0x27 0x28 0x29 0x2A 0x2B 0x2C 0x2D 0x2E 0x2F )(list 0x680 0x6B4 0x6E8 0x71C 0x750 0x784 0x7B8 0x7EC 0x820 0x854 0x888 0x8BC 0x8F0 0x924 0x958 0x98C ) group.long ($2+0x2410)++0x3 line.long 0x0 "SEC_PER2_$1,This register is only used for resource manager to control secure access permission." bitfld.long 0x0 31. "DOM11_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM11_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM11_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM11_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM10_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM10_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM10_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM10_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM9_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM9_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM9_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM9_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM8_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM8_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM8_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM8_SEC_EN,Domain secure permission control enable" "0,1" repeat.end repeat 16. (list 0x30 0x31 0x32 0x33 0x34 0x35 0x36 0x37 0x38 0x39 0x3A 0x3B 0x3C 0x3D 0x3E 0x3F )(list 0x9C0 0x9F4 0xA28 0xA5C 0xA90 0xAC4 0xAF8 0xB2C 0xB60 0xB94 0xBC8 0xBFC 0xC30 0xC64 0xC98 0xCCC ) group.long ($2+0x2410)++0x3 line.long 0x0 "SEC_PER2_$1,This register is only used for resource manager to control secure access permission." bitfld.long 0x0 31. "DOM11_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM11_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM11_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM11_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM10_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM10_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM10_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM10_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM9_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM9_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM9_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM9_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM8_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM8_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM8_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM8_SEC_EN,Domain secure permission control enable" "0,1" repeat.end repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x34 0x68 0x9C 0xD0 0x104 0x138 0x16C 0x1A0 0x1D4 0x208 0x23C 0x270 0x2A4 0x2D8 0x30C ) group.long ($2+0x2414)++0x3 line.long 0x0 "SEC_PER3_$1,This register is only used for resource manager to control secure access permission." bitfld.long 0x0 31. "DOM15_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM15_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM15_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM15_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM14_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM14_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM14_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM14_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM13_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM13_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM13_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM13_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM12_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM12_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM12_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM12_SEC_EN,Domain secure permission control enable" "0,1" repeat.end repeat 16. (list 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1A 0x1B 0x1C 0x1D 0x1E 0x1F )(list 0x340 0x374 0x3A8 0x3DC 0x410 0x444 0x478 0x4AC 0x4E0 0x514 0x548 0x57C 0x5B0 0x5E4 0x618 0x64C ) group.long ($2+0x2414)++0x3 line.long 0x0 "SEC_PER3_$1,This register is only used for resource manager to control secure access permission." bitfld.long 0x0 31. "DOM15_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM15_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM15_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM15_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM14_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM14_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM14_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM14_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM13_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM13_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM13_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM13_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM12_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM12_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM12_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM12_SEC_EN,Domain secure permission control enable" "0,1" repeat.end repeat 16. (list 0x20 0x21 0x22 0x23 0x24 0x25 0x26 0x27 0x28 0x29 0x2A 0x2B 0x2C 0x2D 0x2E 0x2F )(list 0x680 0x6B4 0x6E8 0x71C 0x750 0x784 0x7B8 0x7EC 0x820 0x854 0x888 0x8BC 0x8F0 0x924 0x958 0x98C ) group.long ($2+0x2414)++0x3 line.long 0x0 "SEC_PER3_$1,This register is only used for resource manager to control secure access permission." bitfld.long 0x0 31. "DOM15_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM15_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM15_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM15_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM14_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM14_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM14_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM14_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM13_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM13_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM13_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM13_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM12_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM12_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM12_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM12_SEC_EN,Domain secure permission control enable" "0,1" repeat.end repeat 16. (list 0x30 0x31 0x32 0x33 0x34 0x35 0x36 0x37 0x38 0x39 0x3A 0x3B 0x3C 0x3D 0x3E 0x3F )(list 0x9C0 0x9F4 0xA28 0xA5C 0xA90 0xAC4 0xAF8 0xB2C 0xB60 0xB94 0xBC8 0xBFC 0xC30 0xC64 0xC98 0xCCC ) group.long ($2+0x2414)++0x3 line.long 0x0 "SEC_PER3_$1,This register is only used for resource manager to control secure access permission." bitfld.long 0x0 31. "DOM15_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM15_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM15_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM15_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM14_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM14_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM14_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM14_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM13_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM13_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM13_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM13_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM12_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM12_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM12_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM12_SEC_EN,Domain secure permission control enable" "0,1" repeat.end repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x34 0x68 0x9C 0xD0 0x104 0x138 0x16C 0x1A0 0x1D4 0x208 0x23C 0x270 0x2A4 0x2D8 0x30C ) group.long ($2+0x2418)++0x3 line.long 0x0 "PRI_PER0_$1,This register is only used for resource manager to control privileged access permission." bitfld.long 0x0 31. "DOM3_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM3_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM3_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM3_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM2_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM2_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM2_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM2_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM1_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM1_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM1_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM1_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM0_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM0_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM0_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM0_PRI_EN,Domain privileged permission control enable" "0,1" repeat.end repeat 16. (list 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1A 0x1B 0x1C 0x1D 0x1E 0x1F )(list 0x340 0x374 0x3A8 0x3DC 0x410 0x444 0x478 0x4AC 0x4E0 0x514 0x548 0x57C 0x5B0 0x5E4 0x618 0x64C ) group.long ($2+0x2418)++0x3 line.long 0x0 "PRI_PER0_$1,This register is only used for resource manager to control privileged access permission." bitfld.long 0x0 31. "DOM3_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM3_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM3_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM3_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM2_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM2_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM2_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM2_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM1_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM1_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM1_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM1_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM0_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM0_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM0_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM0_PRI_EN,Domain privileged permission control enable" "0,1" repeat.end repeat 16. (list 0x20 0x21 0x22 0x23 0x24 0x25 0x26 0x27 0x28 0x29 0x2A 0x2B 0x2C 0x2D 0x2E 0x2F )(list 0x680 0x6B4 0x6E8 0x71C 0x750 0x784 0x7B8 0x7EC 0x820 0x854 0x888 0x8BC 0x8F0 0x924 0x958 0x98C ) group.long ($2+0x2418)++0x3 line.long 0x0 "PRI_PER0_$1,This register is only used for resource manager to control privileged access permission." bitfld.long 0x0 31. "DOM3_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM3_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM3_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM3_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM2_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM2_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM2_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM2_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM1_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM1_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM1_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM1_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM0_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM0_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM0_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM0_PRI_EN,Domain privileged permission control enable" "0,1" repeat.end repeat 16. (list 0x30 0x31 0x32 0x33 0x34 0x35 0x36 0x37 0x38 0x39 0x3A 0x3B 0x3C 0x3D 0x3E 0x3F )(list 0x9C0 0x9F4 0xA28 0xA5C 0xA90 0xAC4 0xAF8 0xB2C 0xB60 0xB94 0xBC8 0xBFC 0xC30 0xC64 0xC98 0xCCC ) group.long ($2+0x2418)++0x3 line.long 0x0 "PRI_PER0_$1,This register is only used for resource manager to control privileged access permission." bitfld.long 0x0 31. "DOM3_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM3_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM3_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM3_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM2_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM2_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM2_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM2_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM1_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM1_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM1_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM1_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM0_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM0_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM0_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM0_PRI_EN,Domain privileged permission control enable" "0,1" repeat.end repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x34 0x68 0x9C 0xD0 0x104 0x138 0x16C 0x1A0 0x1D4 0x208 0x23C 0x270 0x2A4 0x2D8 0x30C ) group.long ($2+0x241C)++0x3 line.long 0x0 "PRI_PER1_$1,This register is only used for resource manager to control privileged access permission." bitfld.long 0x0 31. "DOM7_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM7_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM7_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM7_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM6_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM6_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM6_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM6_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM5_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM5_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM5_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM5_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM4_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM4_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM4_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM4_PRI_EN,Domain privileged permission control enable" "0,1" repeat.end repeat 16. (list 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1A 0x1B 0x1C 0x1D 0x1E 0x1F )(list 0x340 0x374 0x3A8 0x3DC 0x410 0x444 0x478 0x4AC 0x4E0 0x514 0x548 0x57C 0x5B0 0x5E4 0x618 0x64C ) group.long ($2+0x241C)++0x3 line.long 0x0 "PRI_PER1_$1,This register is only used for resource manager to control privileged access permission." bitfld.long 0x0 31. "DOM7_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM7_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM7_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM7_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM6_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM6_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM6_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM6_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM5_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM5_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM5_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM5_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM4_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM4_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM4_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM4_PRI_EN,Domain privileged permission control enable" "0,1" repeat.end repeat 16. (list 0x20 0x21 0x22 0x23 0x24 0x25 0x26 0x27 0x28 0x29 0x2A 0x2B 0x2C 0x2D 0x2E 0x2F )(list 0x680 0x6B4 0x6E8 0x71C 0x750 0x784 0x7B8 0x7EC 0x820 0x854 0x888 0x8BC 0x8F0 0x924 0x958 0x98C ) group.long ($2+0x241C)++0x3 line.long 0x0 "PRI_PER1_$1,This register is only used for resource manager to control privileged access permission." bitfld.long 0x0 31. "DOM7_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM7_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM7_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM7_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM6_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM6_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM6_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM6_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM5_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM5_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM5_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM5_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM4_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM4_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM4_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM4_PRI_EN,Domain privileged permission control enable" "0,1" repeat.end repeat 16. (list 0x30 0x31 0x32 0x33 0x34 0x35 0x36 0x37 0x38 0x39 0x3A 0x3B 0x3C 0x3D 0x3E 0x3F )(list 0x9C0 0x9F4 0xA28 0xA5C 0xA90 0xAC4 0xAF8 0xB2C 0xB60 0xB94 0xBC8 0xBFC 0xC30 0xC64 0xC98 0xCCC ) group.long ($2+0x241C)++0x3 line.long 0x0 "PRI_PER1_$1,This register is only used for resource manager to control privileged access permission." bitfld.long 0x0 31. "DOM7_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM7_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM7_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM7_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM6_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM6_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM6_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM6_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM5_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM5_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM5_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM5_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM4_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM4_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM4_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM4_PRI_EN,Domain privileged permission control enable" "0,1" repeat.end repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x34 0x68 0x9C 0xD0 0x104 0x138 0x16C 0x1A0 0x1D4 0x208 0x23C 0x270 0x2A4 0x2D8 0x30C ) group.long ($2+0x2420)++0x3 line.long 0x0 "PRI_PER2_$1,This register is only used for resource manager to control privileged access permission." bitfld.long 0x0 31. "DOM11_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM11_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM11_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM11_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM10_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM10_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM10_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM10_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM9_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM9_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM9_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM9_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM8_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM8_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM8_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM8_PRI_EN,Domain privileged permission control enable" "0,1" repeat.end repeat 16. (list 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1A 0x1B 0x1C 0x1D 0x1E 0x1F )(list 0x340 0x374 0x3A8 0x3DC 0x410 0x444 0x478 0x4AC 0x4E0 0x514 0x548 0x57C 0x5B0 0x5E4 0x618 0x64C ) group.long ($2+0x2420)++0x3 line.long 0x0 "PRI_PER2_$1,This register is only used for resource manager to control privileged access permission." bitfld.long 0x0 31. "DOM11_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM11_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM11_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM11_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM10_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM10_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM10_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM10_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM9_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM9_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM9_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM9_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM8_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM8_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM8_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM8_PRI_EN,Domain privileged permission control enable" "0,1" repeat.end repeat 16. (list 0x20 0x21 0x22 0x23 0x24 0x25 0x26 0x27 0x28 0x29 0x2A 0x2B 0x2C 0x2D 0x2E 0x2F )(list 0x680 0x6B4 0x6E8 0x71C 0x750 0x784 0x7B8 0x7EC 0x820 0x854 0x888 0x8BC 0x8F0 0x924 0x958 0x98C ) group.long ($2+0x2420)++0x3 line.long 0x0 "PRI_PER2_$1,This register is only used for resource manager to control privileged access permission." bitfld.long 0x0 31. "DOM11_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM11_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM11_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM11_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM10_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM10_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM10_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM10_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM9_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM9_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM9_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM9_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM8_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM8_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM8_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM8_PRI_EN,Domain privileged permission control enable" "0,1" repeat.end repeat 16. (list 0x30 0x31 0x32 0x33 0x34 0x35 0x36 0x37 0x38 0x39 0x3A 0x3B 0x3C 0x3D 0x3E 0x3F )(list 0x9C0 0x9F4 0xA28 0xA5C 0xA90 0xAC4 0xAF8 0xB2C 0xB60 0xB94 0xBC8 0xBFC 0xC30 0xC64 0xC98 0xCCC ) group.long ($2+0x2420)++0x3 line.long 0x0 "PRI_PER2_$1,This register is only used for resource manager to control privileged access permission." bitfld.long 0x0 31. "DOM11_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM11_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM11_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM11_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM10_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM10_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM10_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM10_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM9_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM9_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM9_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM9_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM8_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM8_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM8_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM8_PRI_EN,Domain privileged permission control enable" "0,1" repeat.end repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x34 0x68 0x9C 0xD0 0x104 0x138 0x16C 0x1A0 0x1D4 0x208 0x23C 0x270 0x2A4 0x2D8 0x30C ) group.long ($2+0x2424)++0x3 line.long 0x0 "PRI_PER3_$1,This register is only used for resource manager to control privileged access permission." bitfld.long 0x0 31. "DOM15_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM15_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM15_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM15_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM14_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM14_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM14_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM14_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM13_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM13_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM13_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM13_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM12_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM12_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM12_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM12_PRI_EN,Domain privileged permission control enable" "0,1" repeat.end repeat 16. (list 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1A 0x1B 0x1C 0x1D 0x1E 0x1F )(list 0x340 0x374 0x3A8 0x3DC 0x410 0x444 0x478 0x4AC 0x4E0 0x514 0x548 0x57C 0x5B0 0x5E4 0x618 0x64C ) group.long ($2+0x2424)++0x3 line.long 0x0 "PRI_PER3_$1,This register is only used for resource manager to control privileged access permission." bitfld.long 0x0 31. "DOM15_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM15_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM15_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM15_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM14_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM14_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM14_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM14_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM13_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM13_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM13_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM13_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM12_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM12_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM12_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM12_PRI_EN,Domain privileged permission control enable" "0,1" repeat.end repeat 16. (list 0x20 0x21 0x22 0x23 0x24 0x25 0x26 0x27 0x28 0x29 0x2A 0x2B 0x2C 0x2D 0x2E 0x2F )(list 0x680 0x6B4 0x6E8 0x71C 0x750 0x784 0x7B8 0x7EC 0x820 0x854 0x888 0x8BC 0x8F0 0x924 0x958 0x98C ) group.long ($2+0x2424)++0x3 line.long 0x0 "PRI_PER3_$1,This register is only used for resource manager to control privileged access permission." bitfld.long 0x0 31. "DOM15_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM15_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM15_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM15_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM14_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM14_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM14_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM14_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM13_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM13_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM13_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM13_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM12_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM12_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM12_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM12_PRI_EN,Domain privileged permission control enable" "0,1" repeat.end repeat 16. (list 0x30 0x31 0x32 0x33 0x34 0x35 0x36 0x37 0x38 0x39 0x3A 0x3B 0x3C 0x3D 0x3E 0x3F )(list 0x9C0 0x9F4 0xA28 0xA5C 0xA90 0xAC4 0xAF8 0xB2C 0xB60 0xB94 0xBC8 0xBFC 0xC30 0xC64 0xC98 0xCCC ) group.long ($2+0x2424)++0x3 line.long 0x0 "PRI_PER3_$1,This register is only used for resource manager to control privileged access permission." bitfld.long 0x0 31. "DOM15_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM15_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM15_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM15_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM14_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM14_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM14_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM14_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM13_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM13_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM13_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM13_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM12_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM12_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM12_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM12_PRI_EN,Domain privileged permission control enable" "0,1" repeat.end repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x34 0x68 0x9C 0xD0 0x104 0x138 0x16C 0x1A0 0x1D4 0x208 0x23C 0x270 0x2A4 0x2D8 0x30C ) group.long ($2+0x2428)++0x3 line.long 0x0 "DOM_SEC_PER_$1,This register is only used for domain master to control secure access permission. When the domain master write this register. it only changes the secure permission for itself. When the domain master read this register. it gets permission.." bitfld.long 0x0 7. "DOM_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" newline bitfld.long 0x0 0. "DOM_SEC_EN,Domain secure permission control enable" "0,1" repeat.end repeat 16. (list 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1A 0x1B 0x1C 0x1D 0x1E 0x1F )(list 0x340 0x374 0x3A8 0x3DC 0x410 0x444 0x478 0x4AC 0x4E0 0x514 0x548 0x57C 0x5B0 0x5E4 0x618 0x64C ) group.long ($2+0x2428)++0x3 line.long 0x0 "DOM_SEC_PER_$1,This register is only used for domain master to control secure access permission. When the domain master write this register. it only changes the secure permission for itself. When the domain master read this register. it gets permission.." bitfld.long 0x0 7. "DOM_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" newline bitfld.long 0x0 0. "DOM_SEC_EN,Domain secure permission control enable" "0,1" repeat.end repeat 16. (list 0x20 0x21 0x22 0x23 0x24 0x25 0x26 0x27 0x28 0x29 0x2A 0x2B 0x2C 0x2D 0x2E 0x2F )(list 0x680 0x6B4 0x6E8 0x71C 0x750 0x784 0x7B8 0x7EC 0x820 0x854 0x888 0x8BC 0x8F0 0x924 0x958 0x98C ) group.long ($2+0x2428)++0x3 line.long 0x0 "DOM_SEC_PER_$1,This register is only used for domain master to control secure access permission. When the domain master write this register. it only changes the secure permission for itself. When the domain master read this register. it gets permission.." bitfld.long 0x0 7. "DOM_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" newline bitfld.long 0x0 0. "DOM_SEC_EN,Domain secure permission control enable" "0,1" repeat.end repeat 16. (list 0x30 0x31 0x32 0x33 0x34 0x35 0x36 0x37 0x38 0x39 0x3A 0x3B 0x3C 0x3D 0x3E 0x3F )(list 0x9C0 0x9F4 0xA28 0xA5C 0xA90 0xAC4 0xAF8 0xB2C 0xB60 0xB94 0xBC8 0xBFC 0xC30 0xC64 0xC98 0xCCC ) group.long ($2+0x2428)++0x3 line.long 0x0 "DOM_SEC_PER_$1,This register is only used for domain master to control secure access permission. When the domain master write this register. it only changes the secure permission for itself. When the domain master read this register. it gets permission.." bitfld.long 0x0 7. "DOM_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" newline bitfld.long 0x0 0. "DOM_SEC_EN,Domain secure permission control enable" "0,1" repeat.end repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x34 0x68 0x9C 0xD0 0x104 0x138 0x16C 0x1A0 0x1D4 0x208 0x23C 0x270 0x2A4 0x2D8 0x30C ) group.long ($2+0x242C)++0x3 line.long 0x0 "DOM_PRI_PER_$1,This register is only used for domain master to control secure access permission. When the domain master write this register. it only changes the secure permission for itself. When the domain master read this register. it gets permission.." bitfld.long 0x0 7. "DOM_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" newline bitfld.long 0x0 0. "DOM_PRI_EN,Domain privileged permission control enable" "0,1" repeat.end repeat 16. (list 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1A 0x1B 0x1C 0x1D 0x1E 0x1F )(list 0x340 0x374 0x3A8 0x3DC 0x410 0x444 0x478 0x4AC 0x4E0 0x514 0x548 0x57C 0x5B0 0x5E4 0x618 0x64C ) group.long ($2+0x242C)++0x3 line.long 0x0 "DOM_PRI_PER_$1,This register is only used for domain master to control secure access permission. When the domain master write this register. it only changes the secure permission for itself. When the domain master read this register. it gets permission.." bitfld.long 0x0 7. "DOM_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" newline bitfld.long 0x0 0. "DOM_PRI_EN,Domain privileged permission control enable" "0,1" repeat.end repeat 16. (list 0x20 0x21 0x22 0x23 0x24 0x25 0x26 0x27 0x28 0x29 0x2A 0x2B 0x2C 0x2D 0x2E 0x2F )(list 0x680 0x6B4 0x6E8 0x71C 0x750 0x784 0x7B8 0x7EC 0x820 0x854 0x888 0x8BC 0x8F0 0x924 0x958 0x98C ) group.long ($2+0x242C)++0x3 line.long 0x0 "DOM_PRI_PER_$1,This register is only used for domain master to control secure access permission. When the domain master write this register. it only changes the secure permission for itself. When the domain master read this register. it gets permission.." bitfld.long 0x0 7. "DOM_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" newline bitfld.long 0x0 0. "DOM_PRI_EN,Domain privileged permission control enable" "0,1" repeat.end repeat 16. (list 0x30 0x31 0x32 0x33 0x34 0x35 0x36 0x37 0x38 0x39 0x3A 0x3B 0x3C 0x3D 0x3E 0x3F )(list 0x9C0 0x9F4 0xA28 0xA5C 0xA90 0xAC4 0xAF8 0xB2C 0xB60 0xB94 0xBC8 0xBFC 0xC30 0xC64 0xC98 0xCCC ) group.long ($2+0x242C)++0x3 line.long 0x0 "DOM_PRI_PER_$1,This register is only used for domain master to control secure access permission. When the domain master write this register. it only changes the secure permission for itself. When the domain master read this register. it gets permission.." bitfld.long 0x0 7. "DOM_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" newline bitfld.long 0x0 0. "DOM_PRI_EN,Domain privileged permission control enable" "0,1" repeat.end repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x34 0x68 0x9C 0xD0 0x104 0x138 0x16C 0x1A0 0x1D4 0x208 0x23C 0x270 0x2A4 0x2D8 0x30C ) group.long ($2+0x2430)++0x3 line.long 0x0 "DOM_ASSIGN_$1,Use to assign domain for accessing DOM_SEC_PER and DOM_PRI_PER register. Only resource manager. group manager and domain owner can access this register. For write. group manager must write its owen domain ID. otherwise write accessing will.." hexmask.long.byte 0x0 0.--3. 1. "DID,accessing DOM_SEC_PER and DOM_PRI_PER register" repeat.end repeat 16. (list 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1A 0x1B 0x1C 0x1D 0x1E 0x1F )(list 0x340 0x374 0x3A8 0x3DC 0x410 0x444 0x478 0x4AC 0x4E0 0x514 0x548 0x57C 0x5B0 0x5E4 0x618 0x64C ) group.long ($2+0x2430)++0x3 line.long 0x0 "DOM_ASSIGN_$1,Use to assign domain for accessing DOM_SEC_PER and DOM_PRI_PER register. Only resource manager. group manager and domain owner can access this register. For write. group manager must write its owen domain ID. otherwise write accessing will.." hexmask.long.byte 0x0 0.--3. 1. "DID,accessing DOM_SEC_PER and DOM_PRI_PER register" repeat.end repeat 16. (list 0x20 0x21 0x22 0x23 0x24 0x25 0x26 0x27 0x28 0x29 0x2A 0x2B 0x2C 0x2D 0x2E 0x2F )(list 0x680 0x6B4 0x6E8 0x71C 0x750 0x784 0x7B8 0x7EC 0x820 0x854 0x888 0x8BC 0x8F0 0x924 0x958 0x98C ) group.long ($2+0x2430)++0x3 line.long 0x0 "DOM_ASSIGN_$1,Use to assign domain for accessing DOM_SEC_PER and DOM_PRI_PER register. Only resource manager. group manager and domain owner can access this register. For write. group manager must write its owen domain ID. otherwise write accessing will.." hexmask.long.byte 0x0 0.--3. 1. "DID,accessing DOM_SEC_PER and DOM_PRI_PER register" repeat.end repeat 16. (list 0x30 0x31 0x32 0x33 0x34 0x35 0x36 0x37 0x38 0x39 0x3A 0x3B 0x3C 0x3D 0x3E 0x3F )(list 0x9C0 0x9F4 0xA28 0xA5C 0xA90 0xAC4 0xAF8 0xB2C 0xB60 0xB94 0xBC8 0xBFC 0xC30 0xC64 0xC98 0xCCC ) group.long ($2+0x2430)++0x3 line.long 0x0 "DOM_ASSIGN_$1,Use to assign domain for accessing DOM_SEC_PER and DOM_PRI_PER register. Only resource manager. group manager and domain owner can access this register. For write. group manager must write its owen domain ID. otherwise write accessing will.." hexmask.long.byte 0x0 0.--3. 1. "DID,accessing DOM_SEC_PER and DOM_PRI_PER register" repeat.end repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x38 0x70 0xA8 0xE0 0x118 0x150 0x188 0x1C0 0x1F8 0x230 0x268 0x2A0 0x2D8 0x310 0x348 ) group.long ($2+0x3100)++0x3 line.long 0x0 "RGN_DOM_$1,Assign domain for peripheral. It can be only configured by resource and group manager" bitfld.long 0x0 31. "LOCK,When this bit is set lock write for all the bits in the register." "0,1" bitfld.long 0x0 4. "SET,Set together with DID would change permission of this resource to following setting: 1) Domain access control enabled. 2) Read/Write allowed for the domain owner. 3) Read/Write not allowed for all the other domains. If this bit is not set only DID.." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Assign domain for peripheral" repeat.end repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x38 0x70 0xA8 0xE0 0x118 0x150 0x188 0x1C0 0x1F8 0x230 0x268 0x2A0 0x2D8 0x310 0x348 ) group.long ($2+0x3104)++0x3 line.long 0x0 "RGN_DOM_PER0_$1,Domain Permission Control. It can be only configured by resource manager and domain owner." bitfld.long 0x0 31. "DOM7_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 29.--30. "DOM7_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 28. "DOM7_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 27. "DOM6_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 25.--26. "DOM6_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" newline bitfld.long 0x0 24. "DOM6_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 23. "DOM5_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 21.--22. "DOM5_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 20. "DOM5_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 19. "DOM4_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" newline bitfld.long 0x0 17.--18. "DOM4_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM4_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 15. "DOM3_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 13.--14. "DOM3_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 12. "DOM3_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" newline bitfld.long 0x0 11. "DOM2_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 9.--10. "DOM2_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM2_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 7. "DOM1_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 5.--6. "DOM1_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" newline bitfld.long 0x0 4. "DOM1_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 3. "DOM0_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 1.--2. "DOM0_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM0_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" repeat.end repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x38 0x70 0xA8 0xE0 0x118 0x150 0x188 0x1C0 0x1F8 0x230 0x268 0x2A0 0x2D8 0x310 0x348 ) group.long ($2+0x3108)++0x3 line.long 0x0 "RGN_DOM_PER1_$1,Domain Permission Control. It can be only configured by resource manager and domain owner." bitfld.long 0x0 31. "DOM15_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 29.--30. "DOM15_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 28. "DOM15_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 27. "DOM14_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 25.--26. "DOM14_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" newline bitfld.long 0x0 24. "DOM14_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 23. "DOM13_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 21.--22. "DOM13_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 20. "DOM13_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 19. "DOM12_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" newline bitfld.long 0x0 17.--18. "DOM12_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM12_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 15. "DOM11_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 13.--14. "DOM11_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 12. "DOM11_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" newline bitfld.long 0x0 11. "DOM10_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 9.--10. "DOM10_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM10_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 7. "DOM9_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 5.--6. "DOM9_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" newline bitfld.long 0x0 4. "DOM9_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 3. "DOM8_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 1.--2. "DOM8_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM8_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" repeat.end repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x38 0x70 0xA8 0xE0 0x118 0x150 0x188 0x1C0 0x1F8 0x230 0x268 0x2A0 0x2D8 0x310 0x348 ) group.long ($2+0x310C)++0x3 line.long 0x0 "RGN_SEC_PER0_$1,This register is only used for resource manager to control secure access permission." bitfld.long 0x0 31. "DOM3_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM3_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM3_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM3_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM2_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM2_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM2_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM2_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM1_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM1_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM1_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM1_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM0_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM0_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM0_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM0_SEC_EN,Domain secure permission control enable" "0,1" repeat.end repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x38 0x70 0xA8 0xE0 0x118 0x150 0x188 0x1C0 0x1F8 0x230 0x268 0x2A0 0x2D8 0x310 0x348 ) group.long ($2+0x3110)++0x3 line.long 0x0 "RGN_SEC_PER1_$1,This register is only used for resource manager to control secure access permission." bitfld.long 0x0 31. "DOM7_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM7_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM7_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM7_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM6_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM6_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM6_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM6_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM5_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM5_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM5_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM5_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM4_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM4_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM4_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM4_SEC_EN,Domain secure permission control enable" "0,1" repeat.end repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x38 0x70 0xA8 0xE0 0x118 0x150 0x188 0x1C0 0x1F8 0x230 0x268 0x2A0 0x2D8 0x310 0x348 ) group.long ($2+0x3114)++0x3 line.long 0x0 "RGN_SEC_PER2_$1,This register is only used for resource manager to control secure access permission." bitfld.long 0x0 31. "DOM11_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM11_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM11_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM11_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM10_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM10_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM10_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM10_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM9_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM9_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM9_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM9_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM8_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM8_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM8_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM8_SEC_EN,Domain secure permission control enable" "0,1" repeat.end repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x38 0x70 0xA8 0xE0 0x118 0x150 0x188 0x1C0 0x1F8 0x230 0x268 0x2A0 0x2D8 0x310 0x348 ) group.long ($2+0x3118)++0x3 line.long 0x0 "RGN_SEC_PER3_$1,This register is only used for resource manager to control secure access permission." bitfld.long 0x0 31. "DOM15_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM15_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM15_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM15_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM14_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM14_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM14_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM14_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM13_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM13_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM13_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM13_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM12_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM12_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM12_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM12_SEC_EN,Domain secure permission control enable" "0,1" repeat.end repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x38 0x70 0xA8 0xE0 0x118 0x150 0x188 0x1C0 0x1F8 0x230 0x268 0x2A0 0x2D8 0x310 0x348 ) group.long ($2+0x311C)++0x3 line.long 0x0 "RGN_PRI_PER0_$1,This register is only used for resource manager to control privileged access permission." bitfld.long 0x0 31. "DOM3_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM3_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM3_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM3_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM2_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM2_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM2_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM2_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM1_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM1_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM1_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM1_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM0_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM0_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM0_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM0_PRI_EN,Domain privileged permission control enable" "0,1" repeat.end repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x38 0x70 0xA8 0xE0 0x118 0x150 0x188 0x1C0 0x1F8 0x230 0x268 0x2A0 0x2D8 0x310 0x348 ) group.long ($2+0x3120)++0x3 line.long 0x0 "RGN_PRI_PER1_$1,This register is only used for resource manager to control privileged access permission." bitfld.long 0x0 31. "DOM7_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM7_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM7_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM7_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM6_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM6_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM6_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM6_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM5_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM5_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM5_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM5_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM4_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM4_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM4_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM4_PRI_EN,Domain privileged permission control enable" "0,1" repeat.end repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x38 0x70 0xA8 0xE0 0x118 0x150 0x188 0x1C0 0x1F8 0x230 0x268 0x2A0 0x2D8 0x310 0x348 ) group.long ($2+0x3124)++0x3 line.long 0x0 "RGN_PRI_PER2_$1,This register is only used for resource manager to control privileged access permission." bitfld.long 0x0 31. "DOM11_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM11_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM11_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM11_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM10_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM10_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM10_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM10_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM9_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM9_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM9_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM9_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM8_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM8_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM8_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM8_PRI_EN,Domain privileged permission control enable" "0,1" repeat.end repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x38 0x70 0xA8 0xE0 0x118 0x150 0x188 0x1C0 0x1F8 0x230 0x268 0x2A0 0x2D8 0x310 0x348 ) group.long ($2+0x3128)++0x3 line.long 0x0 "RGN_PRI_PER3_$1,This register is only used for resource manager to control privileged access permission." bitfld.long 0x0 31. "DOM15_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM15_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM15_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM15_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM14_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM14_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM14_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM14_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM13_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM13_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM13_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM13_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM12_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM12_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM12_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM12_PRI_EN,Domain privileged permission control enable" "0,1" repeat.end repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x38 0x70 0xA8 0xE0 0x118 0x150 0x188 0x1C0 0x1F8 0x230 0x268 0x2A0 0x2D8 0x310 0x348 ) group.long ($2+0x312C)++0x3 line.long 0x0 "RGN_DOM_SEC_PER_$1,This register is only used for domain master to control secure access permission. When the domain master write this register. it only changes the secure permission for itself. When the domain master read this register. it gets.." bitfld.long 0x0 7. "DOM_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" newline bitfld.long 0x0 0. "DOM_SEC_EN,Domain secure permission control enable" "0,1" repeat.end repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x38 0x70 0xA8 0xE0 0x118 0x150 0x188 0x1C0 0x1F8 0x230 0x268 0x2A0 0x2D8 0x310 0x348 ) group.long ($2+0x3130)++0x3 line.long 0x0 "RGN_DOM_PRI_PER_$1,This register is only used for domain master to control secure access permission. When the domain master write this register. it only changes the secure permission for itself. When the domain master read this register. it gets.." bitfld.long 0x0 7. "DOM_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" newline bitfld.long 0x0 0. "DOM_PRI_EN,Domain privileged permission control enable" "0,1" repeat.end repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x38 0x70 0xA8 0xE0 0x118 0x150 0x188 0x1C0 0x1F8 0x230 0x268 0x2A0 0x2D8 0x310 0x348 ) group.long ($2+0x3134)++0x3 line.long 0x0 "RGN_DOM_ASSIGN_$1,Use to assign domain for accessing DOM_SEC_PER and DOM_PRI_PER register. Only resource manager. group manager and domain owner can access this register. For write. group manager must write its owen domain ID. otherwise write accessing.." hexmask.long.byte 0x0 0.--3. 1. "DID,accessing DOM_SEC_PER and DOM_PRI_PER register" repeat.end tree.end tree "RPC_AP_PINCTRL" base ad:0xF8D00000 repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x4 0x8 0xC 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C ) group.long ($2)++0x3 line.long 0x0 "REGG0_DOM_$1,Assign domain for CKGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1A 0x1B 0x1C 0x1D 0x1E 0x1F )(list 0x40 0x44 0x48 0x4C 0x50 0x54 0x58 0x5C 0x60 0x64 0x68 0x6C 0x70 0x74 0x78 0x7C ) group.long ($2)++0x3 line.long 0x0 "REGG0_DOM_$1,Assign domain for CKGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x20 0x21 0x22 0x23 0x24 0x25 0x26 0x27 0x28 0x29 0x2A 0x2B 0x2C 0x2D 0x2E 0x2F )(list 0x80 0x84 0x88 0x8C 0x90 0x94 0x98 0x9C 0xA0 0xA4 0xA8 0xAC 0xB0 0xB4 0xB8 0xBC ) group.long ($2)++0x3 line.long 0x0 "REGG0_DOM_$1,Assign domain for CKGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x30 0x31 0x32 0x33 0x34 0x35 0x36 0x37 0x38 0x39 0x3A 0x3B 0x3C 0x3D 0x3E 0x3F )(list 0xC0 0xC4 0xC8 0xCC 0xD0 0xD4 0xD8 0xDC 0xE0 0xE4 0xE8 0xEC 0xF0 0xF4 0xF8 0xFC ) group.long ($2)++0x3 line.long 0x0 "REGG0_DOM_$1,Assign domain for CKGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x40 0x41 0x42 0x43 0x44 0x45 0x46 0x47 0x48 0x49 0x4A 0x4B 0x4C 0x4D 0x4E 0x4F )(list 0x100 0x104 0x108 0x10C 0x110 0x114 0x118 0x11C 0x120 0x124 0x128 0x12C 0x130 0x134 0x138 0x13C ) group.long ($2)++0x3 line.long 0x0 "REGG0_DOM_$1,Assign domain for CKGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x50 0x51 0x52 0x53 0x54 0x55 0x56 0x57 0x58 0x59 0x5A 0x5B 0x5C 0x5D 0x5E 0x5F )(list 0x140 0x144 0x148 0x14C 0x150 0x154 0x158 0x15C 0x160 0x164 0x168 0x16C 0x170 0x174 0x178 0x17C ) group.long ($2)++0x3 line.long 0x0 "REGG0_DOM_$1,Assign domain for CKGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x60 0x61 0x62 0x63 0x64 0x65 0x66 0x67 0x68 0x69 0x6A 0x6B 0x6C 0x6D 0x6E 0x6F )(list 0x180 0x184 0x188 0x18C 0x190 0x194 0x198 0x19C 0x1A0 0x1A4 0x1A8 0x1AC 0x1B0 0x1B4 0x1B8 0x1BC ) group.long ($2)++0x3 line.long 0x0 "REGG0_DOM_$1,Assign domain for CKGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x70 0x71 0x72 0x73 0x74 0x75 0x76 0x77 0x78 0x79 0x7A 0x7B 0x7C 0x7D 0x7E 0x7F )(list 0x1C0 0x1C4 0x1C8 0x1CC 0x1D0 0x1D4 0x1D8 0x1DC 0x1E0 0x1E4 0x1E8 0x1EC 0x1F0 0x1F4 0x1F8 0x1FC ) group.long ($2)++0x3 line.long 0x0 "REGG0_DOM_$1,Assign domain for CKGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x80 0x81 0x82 0x83 0x84 0x85 0x86 0x87 0x88 0x89 0x8A 0x8B 0x8C 0x8D 0x8E 0x8F )(list 0x200 0x204 0x208 0x20C 0x210 0x214 0x218 0x21C 0x220 0x224 0x228 0x22C 0x230 0x234 0x238 0x23C ) group.long ($2)++0x3 line.long 0x0 "REGG0_DOM_$1,Assign domain for CKGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x90 0x91 0x92 0x93 0x94 0x95 0x96 0x97 0x98 0x99 0x9A 0x9B 0x9C 0x9D 0x9E 0x9F )(list 0x240 0x244 0x248 0x24C 0x250 0x254 0x258 0x25C 0x260 0x264 0x268 0x26C 0x270 0x274 0x278 0x27C ) group.long ($2)++0x3 line.long 0x0 "REGG0_DOM_$1,Assign domain for CKGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xA0 0xA1 0xA2 0xA3 0xA4 0xA5 0xA6 0xA7 0xA8 0xA9 0xAA 0xAB 0xAC 0xAD 0xAE 0xAF )(list 0x280 0x284 0x288 0x28C 0x290 0x294 0x298 0x29C 0x2A0 0x2A4 0x2A8 0x2AC 0x2B0 0x2B4 0x2B8 0x2BC ) group.long ($2)++0x3 line.long 0x0 "REGG0_DOM_$1,Assign domain for CKGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xB0 0xB1 0xB2 0xB3 0xB4 0xB5 0xB6 0xB7 0xB8 0xB9 0xBA 0xBB 0xBC 0xBD 0xBE 0xBF )(list 0x2C0 0x2C4 0x2C8 0x2CC 0x2D0 0x2D4 0x2D8 0x2DC 0x2E0 0x2E4 0x2E8 0x2EC 0x2F0 0x2F4 0x2F8 0x2FC ) group.long ($2)++0x3 line.long 0x0 "REGG0_DOM_$1,Assign domain for CKGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xC0 0xC1 0xC2 0xC3 0xC4 0xC5 0xC6 0xC7 0xC8 0xC9 0xCA 0xCB 0xCC 0xCD 0xCE 0xCF )(list 0x300 0x304 0x308 0x30C 0x310 0x314 0x318 0x31C 0x320 0x324 0x328 0x32C 0x330 0x334 0x338 0x33C ) group.long ($2)++0x3 line.long 0x0 "REGG0_DOM_$1,Assign domain for CKGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xD0 0xD1 0xD2 0xD3 0xD4 0xD5 0xD6 0xD7 0xD8 0xD9 0xDA 0xDB 0xDC 0xDD 0xDE 0xDF )(list 0x340 0x344 0x348 0x34C 0x350 0x354 0x358 0x35C 0x360 0x364 0x368 0x36C 0x370 0x374 0x378 0x37C ) group.long ($2)++0x3 line.long 0x0 "REGG0_DOM_$1,Assign domain for CKGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xE0 0xE1 0xE2 0xE3 0xE4 0xE5 0xE6 0xE7 0xE8 0xE9 0xEA 0xEB 0xEC 0xED 0xEE 0xEF )(list 0x380 0x384 0x388 0x38C 0x390 0x394 0x398 0x39C 0x3A0 0x3A4 0x3A8 0x3AC 0x3B0 0x3B4 0x3B8 0x3BC ) group.long ($2)++0x3 line.long 0x0 "REGG0_DOM_$1,Assign domain for CKGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xF0 0xF1 0xF2 0xF3 0xF4 0xF5 0xF6 0xF7 0xF8 0xF9 0xFA 0xFB 0xFC 0xFD 0xFE 0xFF )(list 0x3C0 0x3C4 0x3C8 0x3CC 0x3D0 0x3D4 0x3D8 0x3DC 0x3E0 0x3E4 0x3E8 0x3EC 0x3F0 0x3F4 0x3F8 0x3FC ) group.long ($2)++0x3 line.long 0x0 "REGG0_DOM_$1,Assign domain for CKGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x4 0x8 0xC 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C ) group.long ($2+0x400)++0x3 line.long 0x0 "REGG1_DOM_$1,Assign domain for CKGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1A 0x1B 0x1C 0x1D 0x1E 0x1F )(list 0x40 0x44 0x48 0x4C 0x50 0x54 0x58 0x5C 0x60 0x64 0x68 0x6C 0x70 0x74 0x78 0x7C ) group.long ($2+0x400)++0x3 line.long 0x0 "REGG1_DOM_$1,Assign domain for CKGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x20 0x21 0x22 0x23 0x24 0x25 0x26 0x27 0x28 0x29 0x2A 0x2B 0x2C 0x2D 0x2E 0x2F )(list 0x80 0x84 0x88 0x8C 0x90 0x94 0x98 0x9C 0xA0 0xA4 0xA8 0xAC 0xB0 0xB4 0xB8 0xBC ) group.long ($2+0x400)++0x3 line.long 0x0 "REGG1_DOM_$1,Assign domain for CKGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x30 0x31 0x32 0x33 0x34 0x35 0x36 0x37 0x38 0x39 0x3A 0x3B 0x3C 0x3D 0x3E 0x3F )(list 0xC0 0xC4 0xC8 0xCC 0xD0 0xD4 0xD8 0xDC 0xE0 0xE4 0xE8 0xEC 0xF0 0xF4 0xF8 0xFC ) group.long ($2+0x400)++0x3 line.long 0x0 "REGG1_DOM_$1,Assign domain for CKGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x40 0x41 0x42 0x43 0x44 0x45 0x46 0x47 0x48 0x49 0x4A 0x4B 0x4C 0x4D 0x4E 0x4F )(list 0x100 0x104 0x108 0x10C 0x110 0x114 0x118 0x11C 0x120 0x124 0x128 0x12C 0x130 0x134 0x138 0x13C ) group.long ($2+0x400)++0x3 line.long 0x0 "REGG1_DOM_$1,Assign domain for CKGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x50 0x51 0x52 0x53 0x54 0x55 0x56 0x57 0x58 0x59 0x5A 0x5B 0x5C 0x5D 0x5E 0x5F )(list 0x140 0x144 0x148 0x14C 0x150 0x154 0x158 0x15C 0x160 0x164 0x168 0x16C 0x170 0x174 0x178 0x17C ) group.long ($2+0x400)++0x3 line.long 0x0 "REGG1_DOM_$1,Assign domain for CKGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x60 0x61 0x62 0x63 0x64 0x65 0x66 0x67 0x68 0x69 0x6A 0x6B 0x6C 0x6D 0x6E 0x6F )(list 0x180 0x184 0x188 0x18C 0x190 0x194 0x198 0x19C 0x1A0 0x1A4 0x1A8 0x1AC 0x1B0 0x1B4 0x1B8 0x1BC ) group.long ($2+0x400)++0x3 line.long 0x0 "REGG1_DOM_$1,Assign domain for CKGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x70 0x71 0x72 0x73 0x74 0x75 0x76 0x77 0x78 0x79 0x7A 0x7B 0x7C 0x7D 0x7E 0x7F )(list 0x1C0 0x1C4 0x1C8 0x1CC 0x1D0 0x1D4 0x1D8 0x1DC 0x1E0 0x1E4 0x1E8 0x1EC 0x1F0 0x1F4 0x1F8 0x1FC ) group.long ($2+0x400)++0x3 line.long 0x0 "REGG1_DOM_$1,Assign domain for CKGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x80 0x81 0x82 0x83 0x84 0x85 0x86 0x87 0x88 0x89 0x8A 0x8B 0x8C 0x8D 0x8E 0x8F )(list 0x200 0x204 0x208 0x20C 0x210 0x214 0x218 0x21C 0x220 0x224 0x228 0x22C 0x230 0x234 0x238 0x23C ) group.long ($2+0x400)++0x3 line.long 0x0 "REGG1_DOM_$1,Assign domain for CKGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x90 0x91 0x92 0x93 0x94 0x95 0x96 0x97 0x98 0x99 0x9A 0x9B 0x9C 0x9D 0x9E 0x9F )(list 0x240 0x244 0x248 0x24C 0x250 0x254 0x258 0x25C 0x260 0x264 0x268 0x26C 0x270 0x274 0x278 0x27C ) group.long ($2+0x400)++0x3 line.long 0x0 "REGG1_DOM_$1,Assign domain for CKGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xA0 0xA1 0xA2 0xA3 0xA4 0xA5 0xA6 0xA7 0xA8 0xA9 0xAA 0xAB 0xAC 0xAD 0xAE 0xAF )(list 0x280 0x284 0x288 0x28C 0x290 0x294 0x298 0x29C 0x2A0 0x2A4 0x2A8 0x2AC 0x2B0 0x2B4 0x2B8 0x2BC ) group.long ($2+0x400)++0x3 line.long 0x0 "REGG1_DOM_$1,Assign domain for CKGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xB0 0xB1 0xB2 0xB3 0xB4 0xB5 0xB6 0xB7 0xB8 0xB9 0xBA 0xBB 0xBC 0xBD 0xBE 0xBF )(list 0x2C0 0x2C4 0x2C8 0x2CC 0x2D0 0x2D4 0x2D8 0x2DC 0x2E0 0x2E4 0x2E8 0x2EC 0x2F0 0x2F4 0x2F8 0x2FC ) group.long ($2+0x400)++0x3 line.long 0x0 "REGG1_DOM_$1,Assign domain for CKGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xC0 0xC1 0xC2 0xC3 0xC4 0xC5 0xC6 0xC7 0xC8 0xC9 0xCA 0xCB 0xCC 0xCD 0xCE 0xCF )(list 0x300 0x304 0x308 0x30C 0x310 0x314 0x318 0x31C 0x320 0x324 0x328 0x32C 0x330 0x334 0x338 0x33C ) group.long ($2+0x400)++0x3 line.long 0x0 "REGG1_DOM_$1,Assign domain for CKGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xD0 0xD1 0xD2 0xD3 0xD4 0xD5 0xD6 0xD7 0xD8 0xD9 0xDA 0xDB 0xDC 0xDD 0xDE 0xDF )(list 0x340 0x344 0x348 0x34C 0x350 0x354 0x358 0x35C 0x360 0x364 0x368 0x36C 0x370 0x374 0x378 0x37C ) group.long ($2+0x400)++0x3 line.long 0x0 "REGG1_DOM_$1,Assign domain for CKGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xE0 0xE1 0xE2 0xE3 0xE4 0xE5 0xE6 0xE7 0xE8 0xE9 0xEA 0xEB 0xEC 0xED 0xEE 0xEF )(list 0x380 0x384 0x388 0x38C 0x390 0x394 0x398 0x39C 0x3A0 0x3A4 0x3A8 0x3AC 0x3B0 0x3B4 0x3B8 0x3BC ) group.long ($2+0x400)++0x3 line.long 0x0 "REGG1_DOM_$1,Assign domain for CKGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xF0 0xF1 0xF2 0xF3 0xF4 0xF5 0xF6 0xF7 0xF8 0xF9 0xFA 0xFB 0xFC 0xFD 0xFE 0xFF )(list 0x3C0 0x3C4 0x3C8 0x3CC 0x3D0 0x3D4 0x3D8 0x3DC 0x3E0 0x3E4 0x3E8 0x3EC 0x3F0 0x3F4 0x3F8 0x3FC ) group.long ($2+0x400)++0x3 line.long 0x0 "REGG1_DOM_$1,Assign domain for CKGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x4 0x8 0xC 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C ) group.long ($2+0x800)++0x3 line.long 0x0 "REGG2_DOM_$1,Assign domain for SCR registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1A 0x1B 0x1C 0x1D 0x1E 0x1F )(list 0x40 0x44 0x48 0x4C 0x50 0x54 0x58 0x5C 0x60 0x64 0x68 0x6C 0x70 0x74 0x78 0x7C ) group.long ($2+0x800)++0x3 line.long 0x0 "REGG2_DOM_$1,Assign domain for SCR registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x20 0x21 0x22 0x23 0x24 0x25 0x26 0x27 0x28 0x29 0x2A 0x2B 0x2C 0x2D 0x2E 0x2F )(list 0x80 0x84 0x88 0x8C 0x90 0x94 0x98 0x9C 0xA0 0xA4 0xA8 0xAC 0xB0 0xB4 0xB8 0xBC ) group.long ($2+0x800)++0x3 line.long 0x0 "REGG2_DOM_$1,Assign domain for SCR registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x30 0x31 0x32 0x33 0x34 0x35 0x36 0x37 0x38 0x39 0x3A 0x3B 0x3C 0x3D 0x3E 0x3F )(list 0xC0 0xC4 0xC8 0xCC 0xD0 0xD4 0xD8 0xDC 0xE0 0xE4 0xE8 0xEC 0xF0 0xF4 0xF8 0xFC ) group.long ($2+0x800)++0x3 line.long 0x0 "REGG2_DOM_$1,Assign domain for SCR registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x40 0x41 0x42 0x43 0x44 0x45 0x46 0x47 0x48 0x49 0x4A 0x4B 0x4C 0x4D 0x4E 0x4F )(list 0x100 0x104 0x108 0x10C 0x110 0x114 0x118 0x11C 0x120 0x124 0x128 0x12C 0x130 0x134 0x138 0x13C ) group.long ($2+0x800)++0x3 line.long 0x0 "REGG2_DOM_$1,Assign domain for SCR registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x50 0x51 0x52 0x53 0x54 0x55 0x56 0x57 0x58 0x59 0x5A 0x5B 0x5C 0x5D 0x5E 0x5F )(list 0x140 0x144 0x148 0x14C 0x150 0x154 0x158 0x15C 0x160 0x164 0x168 0x16C 0x170 0x174 0x178 0x17C ) group.long ($2+0x800)++0x3 line.long 0x0 "REGG2_DOM_$1,Assign domain for SCR registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x60 0x61 0x62 0x63 0x64 0x65 0x66 0x67 0x68 0x69 0x6A 0x6B 0x6C 0x6D 0x6E 0x6F )(list 0x180 0x184 0x188 0x18C 0x190 0x194 0x198 0x19C 0x1A0 0x1A4 0x1A8 0x1AC 0x1B0 0x1B4 0x1B8 0x1BC ) group.long ($2+0x800)++0x3 line.long 0x0 "REGG2_DOM_$1,Assign domain for SCR registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x70 0x71 0x72 0x73 0x74 0x75 0x76 0x77 0x78 0x79 0x7A 0x7B 0x7C 0x7D 0x7E 0x7F )(list 0x1C0 0x1C4 0x1C8 0x1CC 0x1D0 0x1D4 0x1D8 0x1DC 0x1E0 0x1E4 0x1E8 0x1EC 0x1F0 0x1F4 0x1F8 0x1FC ) group.long ($2+0x800)++0x3 line.long 0x0 "REGG2_DOM_$1,Assign domain for SCR registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x80 0x81 0x82 0x83 0x84 0x85 0x86 0x87 0x88 0x89 0x8A 0x8B 0x8C 0x8D 0x8E 0x8F )(list 0x200 0x204 0x208 0x20C 0x210 0x214 0x218 0x21C 0x220 0x224 0x228 0x22C 0x230 0x234 0x238 0x23C ) group.long ($2+0x800)++0x3 line.long 0x0 "REGG2_DOM_$1,Assign domain for SCR registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x90 0x91 0x92 0x93 0x94 0x95 0x96 0x97 0x98 0x99 0x9A 0x9B 0x9C 0x9D 0x9E 0x9F )(list 0x240 0x244 0x248 0x24C 0x250 0x254 0x258 0x25C 0x260 0x264 0x268 0x26C 0x270 0x274 0x278 0x27C ) group.long ($2+0x800)++0x3 line.long 0x0 "REGG2_DOM_$1,Assign domain for SCR registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xA0 0xA1 0xA2 0xA3 0xA4 0xA5 0xA6 0xA7 0xA8 0xA9 0xAA 0xAB 0xAC 0xAD 0xAE 0xAF )(list 0x280 0x284 0x288 0x28C 0x290 0x294 0x298 0x29C 0x2A0 0x2A4 0x2A8 0x2AC 0x2B0 0x2B4 0x2B8 0x2BC ) group.long ($2+0x800)++0x3 line.long 0x0 "REGG2_DOM_$1,Assign domain for SCR registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xB0 0xB1 0xB2 0xB3 0xB4 0xB5 0xB6 0xB7 0xB8 0xB9 0xBA 0xBB 0xBC 0xBD 0xBE 0xBF )(list 0x2C0 0x2C4 0x2C8 0x2CC 0x2D0 0x2D4 0x2D8 0x2DC 0x2E0 0x2E4 0x2E8 0x2EC 0x2F0 0x2F4 0x2F8 0x2FC ) group.long ($2+0x800)++0x3 line.long 0x0 "REGG2_DOM_$1,Assign domain for SCR registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xC0 0xC1 0xC2 0xC3 0xC4 0xC5 0xC6 0xC7 0xC8 0xC9 0xCA 0xCB 0xCC 0xCD 0xCE 0xCF )(list 0x300 0x304 0x308 0x30C 0x310 0x314 0x318 0x31C 0x320 0x324 0x328 0x32C 0x330 0x334 0x338 0x33C ) group.long ($2+0x800)++0x3 line.long 0x0 "REGG2_DOM_$1,Assign domain for SCR registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xD0 0xD1 0xD2 0xD3 0xD4 0xD5 0xD6 0xD7 0xD8 0xD9 0xDA 0xDB 0xDC 0xDD 0xDE 0xDF )(list 0x340 0x344 0x348 0x34C 0x350 0x354 0x358 0x35C 0x360 0x364 0x368 0x36C 0x370 0x374 0x378 0x37C ) group.long ($2+0x800)++0x3 line.long 0x0 "REGG2_DOM_$1,Assign domain for SCR registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xE0 0xE1 0xE2 0xE3 0xE4 0xE5 0xE6 0xE7 0xE8 0xE9 0xEA 0xEB 0xEC 0xED 0xEE 0xEF )(list 0x380 0x384 0x388 0x38C 0x390 0x394 0x398 0x39C 0x3A0 0x3A4 0x3A8 0x3AC 0x3B0 0x3B4 0x3B8 0x3BC ) group.long ($2+0x800)++0x3 line.long 0x0 "REGG2_DOM_$1,Assign domain for SCR registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xF0 0xF1 0xF2 0xF3 0xF4 0xF5 0xF6 0xF7 0xF8 0xF9 0xFA 0xFB 0xFC 0xFD 0xFE 0xFF )(list 0x3C0 0x3C4 0x3C8 0x3CC 0x3D0 0x3D4 0x3D8 0x3DC 0x3E0 0x3E4 0x3E8 0x3EC 0x3F0 0x3F4 0x3F8 0x3FC ) group.long ($2+0x800)++0x3 line.long 0x0 "REGG2_DOM_$1,Assign domain for SCR registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x4 0x8 0xC 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C ) group.long ($2+0xC00)++0x3 line.long 0x0 "REGG3_DOM_$1,Assign domain for SCR registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1A 0x1B 0x1C 0x1D 0x1E 0x1F )(list 0x40 0x44 0x48 0x4C 0x50 0x54 0x58 0x5C 0x60 0x64 0x68 0x6C 0x70 0x74 0x78 0x7C ) group.long ($2+0xC00)++0x3 line.long 0x0 "REGG3_DOM_$1,Assign domain for SCR registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x20 0x21 0x22 0x23 0x24 0x25 0x26 0x27 0x28 0x29 0x2A 0x2B 0x2C 0x2D 0x2E 0x2F )(list 0x80 0x84 0x88 0x8C 0x90 0x94 0x98 0x9C 0xA0 0xA4 0xA8 0xAC 0xB0 0xB4 0xB8 0xBC ) group.long ($2+0xC00)++0x3 line.long 0x0 "REGG3_DOM_$1,Assign domain for SCR registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x30 0x31 0x32 0x33 0x34 0x35 0x36 0x37 0x38 0x39 0x3A 0x3B 0x3C 0x3D 0x3E 0x3F )(list 0xC0 0xC4 0xC8 0xCC 0xD0 0xD4 0xD8 0xDC 0xE0 0xE4 0xE8 0xEC 0xF0 0xF4 0xF8 0xFC ) group.long ($2+0xC00)++0x3 line.long 0x0 "REGG3_DOM_$1,Assign domain for SCR registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x40 0x41 0x42 0x43 0x44 0x45 0x46 0x47 0x48 0x49 0x4A 0x4B 0x4C 0x4D 0x4E 0x4F )(list 0x100 0x104 0x108 0x10C 0x110 0x114 0x118 0x11C 0x120 0x124 0x128 0x12C 0x130 0x134 0x138 0x13C ) group.long ($2+0xC00)++0x3 line.long 0x0 "REGG3_DOM_$1,Assign domain for SCR registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x50 0x51 0x52 0x53 0x54 0x55 0x56 0x57 0x58 0x59 0x5A 0x5B 0x5C 0x5D 0x5E 0x5F )(list 0x140 0x144 0x148 0x14C 0x150 0x154 0x158 0x15C 0x160 0x164 0x168 0x16C 0x170 0x174 0x178 0x17C ) group.long ($2+0xC00)++0x3 line.long 0x0 "REGG3_DOM_$1,Assign domain for SCR registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x60 0x61 0x62 0x63 0x64 0x65 0x66 0x67 0x68 0x69 0x6A 0x6B 0x6C 0x6D 0x6E 0x6F )(list 0x180 0x184 0x188 0x18C 0x190 0x194 0x198 0x19C 0x1A0 0x1A4 0x1A8 0x1AC 0x1B0 0x1B4 0x1B8 0x1BC ) group.long ($2+0xC00)++0x3 line.long 0x0 "REGG3_DOM_$1,Assign domain for SCR registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x70 0x71 0x72 0x73 0x74 0x75 0x76 0x77 0x78 0x79 0x7A 0x7B 0x7C 0x7D 0x7E 0x7F )(list 0x1C0 0x1C4 0x1C8 0x1CC 0x1D0 0x1D4 0x1D8 0x1DC 0x1E0 0x1E4 0x1E8 0x1EC 0x1F0 0x1F4 0x1F8 0x1FC ) group.long ($2+0xC00)++0x3 line.long 0x0 "REGG3_DOM_$1,Assign domain for SCR registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x80 0x81 0x82 0x83 0x84 0x85 0x86 0x87 0x88 0x89 0x8A 0x8B 0x8C 0x8D 0x8E 0x8F )(list 0x200 0x204 0x208 0x20C 0x210 0x214 0x218 0x21C 0x220 0x224 0x228 0x22C 0x230 0x234 0x238 0x23C ) group.long ($2+0xC00)++0x3 line.long 0x0 "REGG3_DOM_$1,Assign domain for SCR registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x90 0x91 0x92 0x93 0x94 0x95 0x96 0x97 0x98 0x99 0x9A 0x9B 0x9C 0x9D 0x9E 0x9F )(list 0x240 0x244 0x248 0x24C 0x250 0x254 0x258 0x25C 0x260 0x264 0x268 0x26C 0x270 0x274 0x278 0x27C ) group.long ($2+0xC00)++0x3 line.long 0x0 "REGG3_DOM_$1,Assign domain for SCR registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xA0 0xA1 0xA2 0xA3 0xA4 0xA5 0xA6 0xA7 0xA8 0xA9 0xAA 0xAB 0xAC 0xAD 0xAE 0xAF )(list 0x280 0x284 0x288 0x28C 0x290 0x294 0x298 0x29C 0x2A0 0x2A4 0x2A8 0x2AC 0x2B0 0x2B4 0x2B8 0x2BC ) group.long ($2+0xC00)++0x3 line.long 0x0 "REGG3_DOM_$1,Assign domain for SCR registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xB0 0xB1 0xB2 0xB3 0xB4 0xB5 0xB6 0xB7 0xB8 0xB9 0xBA 0xBB 0xBC 0xBD 0xBE 0xBF )(list 0x2C0 0x2C4 0x2C8 0x2CC 0x2D0 0x2D4 0x2D8 0x2DC 0x2E0 0x2E4 0x2E8 0x2EC 0x2F0 0x2F4 0x2F8 0x2FC ) group.long ($2+0xC00)++0x3 line.long 0x0 "REGG3_DOM_$1,Assign domain for SCR registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xC0 0xC1 0xC2 0xC3 0xC4 0xC5 0xC6 0xC7 0xC8 0xC9 0xCA 0xCB 0xCC 0xCD 0xCE 0xCF )(list 0x300 0x304 0x308 0x30C 0x310 0x314 0x318 0x31C 0x320 0x324 0x328 0x32C 0x330 0x334 0x338 0x33C ) group.long ($2+0xC00)++0x3 line.long 0x0 "REGG3_DOM_$1,Assign domain for SCR registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xD0 0xD1 0xD2 0xD3 0xD4 0xD5 0xD6 0xD7 0xD8 0xD9 0xDA 0xDB 0xDC 0xDD 0xDE 0xDF )(list 0x340 0x344 0x348 0x34C 0x350 0x354 0x358 0x35C 0x360 0x364 0x368 0x36C 0x370 0x374 0x378 0x37C ) group.long ($2+0xC00)++0x3 line.long 0x0 "REGG3_DOM_$1,Assign domain for SCR registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xE0 0xE1 0xE2 0xE3 0xE4 0xE5 0xE6 0xE7 0xE8 0xE9 0xEA 0xEB 0xEC 0xED 0xEE 0xEF )(list 0x380 0x384 0x388 0x38C 0x390 0x394 0x398 0x39C 0x3A0 0x3A4 0x3A8 0x3AC 0x3B0 0x3B4 0x3B8 0x3BC ) group.long ($2+0xC00)++0x3 line.long 0x0 "REGG3_DOM_$1,Assign domain for SCR registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xF0 0xF1 0xF2 0xF3 0xF4 0xF5 0xF6 0xF7 0xF8 0xF9 0xFA 0xFB 0xFC 0xFD 0xFE 0xFF )(list 0x3C0 0x3C4 0x3C8 0x3CC 0x3D0 0x3D4 0x3D8 0x3DC 0x3E0 0x3E4 0x3E8 0x3EC 0x3F0 0x3F4 0x3F8 0x3FC ) group.long ($2+0xC00)++0x3 line.long 0x0 "REGG3_DOM_$1,Assign domain for SCR registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x4 0x8 0xC 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C ) group.long ($2+0x1000)++0x3 line.long 0x0 "REGG4_DOM_$1,Assign domain for RSTGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1A 0x1B 0x1C 0x1D 0x1E 0x1F )(list 0x40 0x44 0x48 0x4C 0x50 0x54 0x58 0x5C 0x60 0x64 0x68 0x6C 0x70 0x74 0x78 0x7C ) group.long ($2+0x1000)++0x3 line.long 0x0 "REGG4_DOM_$1,Assign domain for RSTGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x20 0x21 0x22 0x23 0x24 0x25 0x26 0x27 0x28 0x29 0x2A 0x2B 0x2C 0x2D 0x2E 0x2F )(list 0x80 0x84 0x88 0x8C 0x90 0x94 0x98 0x9C 0xA0 0xA4 0xA8 0xAC 0xB0 0xB4 0xB8 0xBC ) group.long ($2+0x1000)++0x3 line.long 0x0 "REGG4_DOM_$1,Assign domain for RSTGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x30 0x31 0x32 0x33 0x34 0x35 0x36 0x37 0x38 0x39 0x3A 0x3B 0x3C 0x3D 0x3E 0x3F )(list 0xC0 0xC4 0xC8 0xCC 0xD0 0xD4 0xD8 0xDC 0xE0 0xE4 0xE8 0xEC 0xF0 0xF4 0xF8 0xFC ) group.long ($2+0x1000)++0x3 line.long 0x0 "REGG4_DOM_$1,Assign domain for RSTGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x40 0x41 0x42 0x43 0x44 0x45 0x46 0x47 0x48 0x49 0x4A 0x4B 0x4C 0x4D 0x4E 0x4F )(list 0x100 0x104 0x108 0x10C 0x110 0x114 0x118 0x11C 0x120 0x124 0x128 0x12C 0x130 0x134 0x138 0x13C ) group.long ($2+0x1000)++0x3 line.long 0x0 "REGG4_DOM_$1,Assign domain for RSTGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x50 0x51 0x52 0x53 0x54 0x55 0x56 0x57 0x58 0x59 0x5A 0x5B 0x5C 0x5D 0x5E 0x5F )(list 0x140 0x144 0x148 0x14C 0x150 0x154 0x158 0x15C 0x160 0x164 0x168 0x16C 0x170 0x174 0x178 0x17C ) group.long ($2+0x1000)++0x3 line.long 0x0 "REGG4_DOM_$1,Assign domain for RSTGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x60 0x61 0x62 0x63 0x64 0x65 0x66 0x67 0x68 0x69 0x6A 0x6B 0x6C 0x6D 0x6E 0x6F )(list 0x180 0x184 0x188 0x18C 0x190 0x194 0x198 0x19C 0x1A0 0x1A4 0x1A8 0x1AC 0x1B0 0x1B4 0x1B8 0x1BC ) group.long ($2+0x1000)++0x3 line.long 0x0 "REGG4_DOM_$1,Assign domain for RSTGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x70 0x71 0x72 0x73 0x74 0x75 0x76 0x77 0x78 0x79 0x7A 0x7B 0x7C 0x7D 0x7E 0x7F )(list 0x1C0 0x1C4 0x1C8 0x1CC 0x1D0 0x1D4 0x1D8 0x1DC 0x1E0 0x1E4 0x1E8 0x1EC 0x1F0 0x1F4 0x1F8 0x1FC ) group.long ($2+0x1000)++0x3 line.long 0x0 "REGG4_DOM_$1,Assign domain for RSTGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x80 0x81 0x82 0x83 0x84 0x85 0x86 0x87 0x88 0x89 0x8A 0x8B 0x8C 0x8D 0x8E 0x8F )(list 0x200 0x204 0x208 0x20C 0x210 0x214 0x218 0x21C 0x220 0x224 0x228 0x22C 0x230 0x234 0x238 0x23C ) group.long ($2+0x1000)++0x3 line.long 0x0 "REGG4_DOM_$1,Assign domain for RSTGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x90 0x91 0x92 0x93 0x94 0x95 0x96 0x97 0x98 0x99 0x9A 0x9B 0x9C 0x9D 0x9E 0x9F )(list 0x240 0x244 0x248 0x24C 0x250 0x254 0x258 0x25C 0x260 0x264 0x268 0x26C 0x270 0x274 0x278 0x27C ) group.long ($2+0x1000)++0x3 line.long 0x0 "REGG4_DOM_$1,Assign domain for RSTGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xA0 0xA1 0xA2 0xA3 0xA4 0xA5 0xA6 0xA7 0xA8 0xA9 0xAA 0xAB 0xAC 0xAD 0xAE 0xAF )(list 0x280 0x284 0x288 0x28C 0x290 0x294 0x298 0x29C 0x2A0 0x2A4 0x2A8 0x2AC 0x2B0 0x2B4 0x2B8 0x2BC ) group.long ($2+0x1000)++0x3 line.long 0x0 "REGG4_DOM_$1,Assign domain for RSTGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xB0 0xB1 0xB2 0xB3 0xB4 0xB5 0xB6 0xB7 0xB8 0xB9 0xBA 0xBB 0xBC 0xBD 0xBE 0xBF )(list 0x2C0 0x2C4 0x2C8 0x2CC 0x2D0 0x2D4 0x2D8 0x2DC 0x2E0 0x2E4 0x2E8 0x2EC 0x2F0 0x2F4 0x2F8 0x2FC ) group.long ($2+0x1000)++0x3 line.long 0x0 "REGG4_DOM_$1,Assign domain for RSTGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xC0 0xC1 0xC2 0xC3 0xC4 0xC5 0xC6 0xC7 0xC8 0xC9 0xCA 0xCB 0xCC 0xCD 0xCE 0xCF )(list 0x300 0x304 0x308 0x30C 0x310 0x314 0x318 0x31C 0x320 0x324 0x328 0x32C 0x330 0x334 0x338 0x33C ) group.long ($2+0x1000)++0x3 line.long 0x0 "REGG4_DOM_$1,Assign domain for RSTGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xD0 0xD1 0xD2 0xD3 0xD4 0xD5 0xD6 0xD7 0xD8 0xD9 0xDA 0xDB 0xDC 0xDD 0xDE 0xDF )(list 0x340 0x344 0x348 0x34C 0x350 0x354 0x358 0x35C 0x360 0x364 0x368 0x36C 0x370 0x374 0x378 0x37C ) group.long ($2+0x1000)++0x3 line.long 0x0 "REGG4_DOM_$1,Assign domain for RSTGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xE0 0xE1 0xE2 0xE3 0xE4 0xE5 0xE6 0xE7 0xE8 0xE9 0xEA 0xEB 0xEC 0xED 0xEE 0xEF )(list 0x380 0x384 0x388 0x38C 0x390 0x394 0x398 0x39C 0x3A0 0x3A4 0x3A8 0x3AC 0x3B0 0x3B4 0x3B8 0x3BC ) group.long ($2+0x1000)++0x3 line.long 0x0 "REGG4_DOM_$1,Assign domain for RSTGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xF0 0xF1 0xF2 0xF3 0xF4 0xF5 0xF6 0xF7 0xF8 0xF9 0xFA 0xFB 0xFC 0xFD 0xFE 0xFF )(list 0x3C0 0x3C4 0x3C8 0x3CC 0x3D0 0x3D4 0x3D8 0x3DC 0x3E0 0x3E4 0x3E8 0x3EC 0x3F0 0x3F4 0x3F8 0x3FC ) group.long ($2+0x1000)++0x3 line.long 0x0 "REGG4_DOM_$1,Assign domain for RSTGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x4 0x8 0xC 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C ) group.long ($2+0x1400)++0x3 line.long 0x0 "REGG5_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1A 0x1B 0x1C 0x1D 0x1E 0x1F )(list 0x40 0x44 0x48 0x4C 0x50 0x54 0x58 0x5C 0x60 0x64 0x68 0x6C 0x70 0x74 0x78 0x7C ) group.long ($2+0x1400)++0x3 line.long 0x0 "REGG5_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x20 0x21 0x22 0x23 0x24 0x25 0x26 0x27 0x28 0x29 0x2A 0x2B 0x2C 0x2D 0x2E 0x2F )(list 0x80 0x84 0x88 0x8C 0x90 0x94 0x98 0x9C 0xA0 0xA4 0xA8 0xAC 0xB0 0xB4 0xB8 0xBC ) group.long ($2+0x1400)++0x3 line.long 0x0 "REGG5_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x30 0x31 0x32 0x33 0x34 0x35 0x36 0x37 0x38 0x39 0x3A 0x3B 0x3C 0x3D 0x3E 0x3F )(list 0xC0 0xC4 0xC8 0xCC 0xD0 0xD4 0xD8 0xDC 0xE0 0xE4 0xE8 0xEC 0xF0 0xF4 0xF8 0xFC ) group.long ($2+0x1400)++0x3 line.long 0x0 "REGG5_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x40 0x41 0x42 0x43 0x44 0x45 0x46 0x47 0x48 0x49 0x4A 0x4B 0x4C 0x4D 0x4E 0x4F )(list 0x100 0x104 0x108 0x10C 0x110 0x114 0x118 0x11C 0x120 0x124 0x128 0x12C 0x130 0x134 0x138 0x13C ) group.long ($2+0x1400)++0x3 line.long 0x0 "REGG5_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x50 0x51 0x52 0x53 0x54 0x55 0x56 0x57 0x58 0x59 0x5A 0x5B 0x5C 0x5D 0x5E 0x5F )(list 0x140 0x144 0x148 0x14C 0x150 0x154 0x158 0x15C 0x160 0x164 0x168 0x16C 0x170 0x174 0x178 0x17C ) group.long ($2+0x1400)++0x3 line.long 0x0 "REGG5_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x60 0x61 0x62 0x63 0x64 0x65 0x66 0x67 0x68 0x69 0x6A 0x6B 0x6C 0x6D 0x6E 0x6F )(list 0x180 0x184 0x188 0x18C 0x190 0x194 0x198 0x19C 0x1A0 0x1A4 0x1A8 0x1AC 0x1B0 0x1B4 0x1B8 0x1BC ) group.long ($2+0x1400)++0x3 line.long 0x0 "REGG5_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x70 0x71 0x72 0x73 0x74 0x75 0x76 0x77 0x78 0x79 0x7A 0x7B 0x7C 0x7D 0x7E 0x7F )(list 0x1C0 0x1C4 0x1C8 0x1CC 0x1D0 0x1D4 0x1D8 0x1DC 0x1E0 0x1E4 0x1E8 0x1EC 0x1F0 0x1F4 0x1F8 0x1FC ) group.long ($2+0x1400)++0x3 line.long 0x0 "REGG5_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x80 0x81 0x82 0x83 0x84 0x85 0x86 0x87 0x88 0x89 0x8A 0x8B 0x8C 0x8D 0x8E 0x8F )(list 0x200 0x204 0x208 0x20C 0x210 0x214 0x218 0x21C 0x220 0x224 0x228 0x22C 0x230 0x234 0x238 0x23C ) group.long ($2+0x1400)++0x3 line.long 0x0 "REGG5_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x90 0x91 0x92 0x93 0x94 0x95 0x96 0x97 0x98 0x99 0x9A 0x9B 0x9C 0x9D 0x9E 0x9F )(list 0x240 0x244 0x248 0x24C 0x250 0x254 0x258 0x25C 0x260 0x264 0x268 0x26C 0x270 0x274 0x278 0x27C ) group.long ($2+0x1400)++0x3 line.long 0x0 "REGG5_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xA0 0xA1 0xA2 0xA3 0xA4 0xA5 0xA6 0xA7 0xA8 0xA9 0xAA 0xAB 0xAC 0xAD 0xAE 0xAF )(list 0x280 0x284 0x288 0x28C 0x290 0x294 0x298 0x29C 0x2A0 0x2A4 0x2A8 0x2AC 0x2B0 0x2B4 0x2B8 0x2BC ) group.long ($2+0x1400)++0x3 line.long 0x0 "REGG5_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xB0 0xB1 0xB2 0xB3 0xB4 0xB5 0xB6 0xB7 0xB8 0xB9 0xBA 0xBB 0xBC 0xBD 0xBE 0xBF )(list 0x2C0 0x2C4 0x2C8 0x2CC 0x2D0 0x2D4 0x2D8 0x2DC 0x2E0 0x2E4 0x2E8 0x2EC 0x2F0 0x2F4 0x2F8 0x2FC ) group.long ($2+0x1400)++0x3 line.long 0x0 "REGG5_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xC0 0xC1 0xC2 0xC3 0xC4 0xC5 0xC6 0xC7 0xC8 0xC9 0xCA 0xCB 0xCC 0xCD 0xCE 0xCF )(list 0x300 0x304 0x308 0x30C 0x310 0x314 0x318 0x31C 0x320 0x324 0x328 0x32C 0x330 0x334 0x338 0x33C ) group.long ($2+0x1400)++0x3 line.long 0x0 "REGG5_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xD0 0xD1 0xD2 0xD3 0xD4 0xD5 0xD6 0xD7 0xD8 0xD9 0xDA 0xDB 0xDC 0xDD 0xDE 0xDF )(list 0x340 0x344 0x348 0x34C 0x350 0x354 0x358 0x35C 0x360 0x364 0x368 0x36C 0x370 0x374 0x378 0x37C ) group.long ($2+0x1400)++0x3 line.long 0x0 "REGG5_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xE0 0xE1 0xE2 0xE3 0xE4 0xE5 0xE6 0xE7 0xE8 0xE9 0xEA 0xEB 0xEC 0xED 0xEE 0xEF )(list 0x380 0x384 0x388 0x38C 0x390 0x394 0x398 0x39C 0x3A0 0x3A4 0x3A8 0x3AC 0x3B0 0x3B4 0x3B8 0x3BC ) group.long ($2+0x1400)++0x3 line.long 0x0 "REGG5_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xF0 0xF1 0xF2 0xF3 0xF4 0xF5 0xF6 0xF7 0xF8 0xF9 0xFA 0xFB 0xFC 0xFD 0xFE 0xFF )(list 0x3C0 0x3C4 0x3C8 0x3CC 0x3D0 0x3D4 0x3D8 0x3DC 0x3E0 0x3E4 0x3E8 0x3EC 0x3F0 0x3F4 0x3F8 0x3FC ) group.long ($2+0x1400)++0x3 line.long 0x0 "REGG5_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x4 0x8 0xC 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C ) group.long ($2+0x1800)++0x3 line.long 0x0 "REGG6_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1A 0x1B 0x1C 0x1D 0x1E 0x1F )(list 0x40 0x44 0x48 0x4C 0x50 0x54 0x58 0x5C 0x60 0x64 0x68 0x6C 0x70 0x74 0x78 0x7C ) group.long ($2+0x1800)++0x3 line.long 0x0 "REGG6_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x20 0x21 0x22 0x23 0x24 0x25 0x26 0x27 0x28 0x29 0x2A 0x2B 0x2C 0x2D 0x2E 0x2F )(list 0x80 0x84 0x88 0x8C 0x90 0x94 0x98 0x9C 0xA0 0xA4 0xA8 0xAC 0xB0 0xB4 0xB8 0xBC ) group.long ($2+0x1800)++0x3 line.long 0x0 "REGG6_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x30 0x31 0x32 0x33 0x34 0x35 0x36 0x37 0x38 0x39 0x3A 0x3B 0x3C 0x3D 0x3E 0x3F )(list 0xC0 0xC4 0xC8 0xCC 0xD0 0xD4 0xD8 0xDC 0xE0 0xE4 0xE8 0xEC 0xF0 0xF4 0xF8 0xFC ) group.long ($2+0x1800)++0x3 line.long 0x0 "REGG6_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x40 0x41 0x42 0x43 0x44 0x45 0x46 0x47 0x48 0x49 0x4A 0x4B 0x4C 0x4D 0x4E 0x4F )(list 0x100 0x104 0x108 0x10C 0x110 0x114 0x118 0x11C 0x120 0x124 0x128 0x12C 0x130 0x134 0x138 0x13C ) group.long ($2+0x1800)++0x3 line.long 0x0 "REGG6_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x50 0x51 0x52 0x53 0x54 0x55 0x56 0x57 0x58 0x59 0x5A 0x5B 0x5C 0x5D 0x5E 0x5F )(list 0x140 0x144 0x148 0x14C 0x150 0x154 0x158 0x15C 0x160 0x164 0x168 0x16C 0x170 0x174 0x178 0x17C ) group.long ($2+0x1800)++0x3 line.long 0x0 "REGG6_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x60 0x61 0x62 0x63 0x64 0x65 0x66 0x67 0x68 0x69 0x6A 0x6B 0x6C 0x6D 0x6E 0x6F )(list 0x180 0x184 0x188 0x18C 0x190 0x194 0x198 0x19C 0x1A0 0x1A4 0x1A8 0x1AC 0x1B0 0x1B4 0x1B8 0x1BC ) group.long ($2+0x1800)++0x3 line.long 0x0 "REGG6_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x70 0x71 0x72 0x73 0x74 0x75 0x76 0x77 0x78 0x79 0x7A 0x7B 0x7C 0x7D 0x7E 0x7F )(list 0x1C0 0x1C4 0x1C8 0x1CC 0x1D0 0x1D4 0x1D8 0x1DC 0x1E0 0x1E4 0x1E8 0x1EC 0x1F0 0x1F4 0x1F8 0x1FC ) group.long ($2+0x1800)++0x3 line.long 0x0 "REGG6_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x80 0x81 0x82 0x83 0x84 0x85 0x86 0x87 0x88 0x89 0x8A 0x8B 0x8C 0x8D 0x8E 0x8F )(list 0x200 0x204 0x208 0x20C 0x210 0x214 0x218 0x21C 0x220 0x224 0x228 0x22C 0x230 0x234 0x238 0x23C ) group.long ($2+0x1800)++0x3 line.long 0x0 "REGG6_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x90 0x91 0x92 0x93 0x94 0x95 0x96 0x97 0x98 0x99 0x9A 0x9B 0x9C 0x9D 0x9E 0x9F )(list 0x240 0x244 0x248 0x24C 0x250 0x254 0x258 0x25C 0x260 0x264 0x268 0x26C 0x270 0x274 0x278 0x27C ) group.long ($2+0x1800)++0x3 line.long 0x0 "REGG6_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xA0 0xA1 0xA2 0xA3 0xA4 0xA5 0xA6 0xA7 0xA8 0xA9 0xAA 0xAB 0xAC 0xAD 0xAE 0xAF )(list 0x280 0x284 0x288 0x28C 0x290 0x294 0x298 0x29C 0x2A0 0x2A4 0x2A8 0x2AC 0x2B0 0x2B4 0x2B8 0x2BC ) group.long ($2+0x1800)++0x3 line.long 0x0 "REGG6_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xB0 0xB1 0xB2 0xB3 0xB4 0xB5 0xB6 0xB7 0xB8 0xB9 0xBA 0xBB 0xBC 0xBD 0xBE 0xBF )(list 0x2C0 0x2C4 0x2C8 0x2CC 0x2D0 0x2D4 0x2D8 0x2DC 0x2E0 0x2E4 0x2E8 0x2EC 0x2F0 0x2F4 0x2F8 0x2FC ) group.long ($2+0x1800)++0x3 line.long 0x0 "REGG6_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xC0 0xC1 0xC2 0xC3 0xC4 0xC5 0xC6 0xC7 0xC8 0xC9 0xCA 0xCB 0xCC 0xCD 0xCE 0xCF )(list 0x300 0x304 0x308 0x30C 0x310 0x314 0x318 0x31C 0x320 0x324 0x328 0x32C 0x330 0x334 0x338 0x33C ) group.long ($2+0x1800)++0x3 line.long 0x0 "REGG6_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xD0 0xD1 0xD2 0xD3 0xD4 0xD5 0xD6 0xD7 0xD8 0xD9 0xDA 0xDB 0xDC 0xDD 0xDE 0xDF )(list 0x340 0x344 0x348 0x34C 0x350 0x354 0x358 0x35C 0x360 0x364 0x368 0x36C 0x370 0x374 0x378 0x37C ) group.long ($2+0x1800)++0x3 line.long 0x0 "REGG6_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xE0 0xE1 0xE2 0xE3 0xE4 0xE5 0xE6 0xE7 0xE8 0xE9 0xEA 0xEB 0xEC 0xED 0xEE 0xEF )(list 0x380 0x384 0x388 0x38C 0x390 0x394 0x398 0x39C 0x3A0 0x3A4 0x3A8 0x3AC 0x3B0 0x3B4 0x3B8 0x3BC ) group.long ($2+0x1800)++0x3 line.long 0x0 "REGG6_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xF0 0xF1 0xF2 0xF3 0xF4 0xF5 0xF6 0xF7 0xF8 0xF9 0xFA 0xFB 0xFC 0xFD 0xFE 0xFF )(list 0x3C0 0x3C4 0x3C8 0x3CC 0x3D0 0x3D4 0x3D8 0x3DC 0x3E0 0x3E4 0x3E8 0x3EC 0x3F0 0x3F4 0x3F8 0x3FC ) group.long ($2+0x1800)++0x3 line.long 0x0 "REGG6_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x4 0x8 0xC 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C ) group.long ($2+0x1C00)++0x3 line.long 0x0 "REGG7_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1A 0x1B 0x1C 0x1D 0x1E 0x1F )(list 0x40 0x44 0x48 0x4C 0x50 0x54 0x58 0x5C 0x60 0x64 0x68 0x6C 0x70 0x74 0x78 0x7C ) group.long ($2+0x1C00)++0x3 line.long 0x0 "REGG7_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x20 0x21 0x22 0x23 0x24 0x25 0x26 0x27 0x28 0x29 0x2A 0x2B 0x2C 0x2D 0x2E 0x2F )(list 0x80 0x84 0x88 0x8C 0x90 0x94 0x98 0x9C 0xA0 0xA4 0xA8 0xAC 0xB0 0xB4 0xB8 0xBC ) group.long ($2+0x1C00)++0x3 line.long 0x0 "REGG7_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x30 0x31 0x32 0x33 0x34 0x35 0x36 0x37 0x38 0x39 0x3A 0x3B 0x3C 0x3D 0x3E 0x3F )(list 0xC0 0xC4 0xC8 0xCC 0xD0 0xD4 0xD8 0xDC 0xE0 0xE4 0xE8 0xEC 0xF0 0xF4 0xF8 0xFC ) group.long ($2+0x1C00)++0x3 line.long 0x0 "REGG7_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x40 0x41 0x42 0x43 0x44 0x45 0x46 0x47 0x48 0x49 0x4A 0x4B 0x4C 0x4D 0x4E 0x4F )(list 0x100 0x104 0x108 0x10C 0x110 0x114 0x118 0x11C 0x120 0x124 0x128 0x12C 0x130 0x134 0x138 0x13C ) group.long ($2+0x1C00)++0x3 line.long 0x0 "REGG7_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x50 0x51 0x52 0x53 0x54 0x55 0x56 0x57 0x58 0x59 0x5A 0x5B 0x5C 0x5D 0x5E 0x5F )(list 0x140 0x144 0x148 0x14C 0x150 0x154 0x158 0x15C 0x160 0x164 0x168 0x16C 0x170 0x174 0x178 0x17C ) group.long ($2+0x1C00)++0x3 line.long 0x0 "REGG7_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x60 0x61 0x62 0x63 0x64 0x65 0x66 0x67 0x68 0x69 0x6A 0x6B 0x6C 0x6D 0x6E 0x6F )(list 0x180 0x184 0x188 0x18C 0x190 0x194 0x198 0x19C 0x1A0 0x1A4 0x1A8 0x1AC 0x1B0 0x1B4 0x1B8 0x1BC ) group.long ($2+0x1C00)++0x3 line.long 0x0 "REGG7_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x70 0x71 0x72 0x73 0x74 0x75 0x76 0x77 0x78 0x79 0x7A 0x7B 0x7C 0x7D 0x7E 0x7F )(list 0x1C0 0x1C4 0x1C8 0x1CC 0x1D0 0x1D4 0x1D8 0x1DC 0x1E0 0x1E4 0x1E8 0x1EC 0x1F0 0x1F4 0x1F8 0x1FC ) group.long ($2+0x1C00)++0x3 line.long 0x0 "REGG7_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x80 0x81 0x82 0x83 0x84 0x85 0x86 0x87 0x88 0x89 0x8A 0x8B 0x8C 0x8D 0x8E 0x8F )(list 0x200 0x204 0x208 0x20C 0x210 0x214 0x218 0x21C 0x220 0x224 0x228 0x22C 0x230 0x234 0x238 0x23C ) group.long ($2+0x1C00)++0x3 line.long 0x0 "REGG7_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x90 0x91 0x92 0x93 0x94 0x95 0x96 0x97 0x98 0x99 0x9A 0x9B 0x9C 0x9D 0x9E 0x9F )(list 0x240 0x244 0x248 0x24C 0x250 0x254 0x258 0x25C 0x260 0x264 0x268 0x26C 0x270 0x274 0x278 0x27C ) group.long ($2+0x1C00)++0x3 line.long 0x0 "REGG7_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xA0 0xA1 0xA2 0xA3 0xA4 0xA5 0xA6 0xA7 0xA8 0xA9 0xAA 0xAB 0xAC 0xAD 0xAE 0xAF )(list 0x280 0x284 0x288 0x28C 0x290 0x294 0x298 0x29C 0x2A0 0x2A4 0x2A8 0x2AC 0x2B0 0x2B4 0x2B8 0x2BC ) group.long ($2+0x1C00)++0x3 line.long 0x0 "REGG7_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xB0 0xB1 0xB2 0xB3 0xB4 0xB5 0xB6 0xB7 0xB8 0xB9 0xBA 0xBB 0xBC 0xBD 0xBE 0xBF )(list 0x2C0 0x2C4 0x2C8 0x2CC 0x2D0 0x2D4 0x2D8 0x2DC 0x2E0 0x2E4 0x2E8 0x2EC 0x2F0 0x2F4 0x2F8 0x2FC ) group.long ($2+0x1C00)++0x3 line.long 0x0 "REGG7_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xC0 0xC1 0xC2 0xC3 0xC4 0xC5 0xC6 0xC7 0xC8 0xC9 0xCA 0xCB 0xCC 0xCD 0xCE 0xCF )(list 0x300 0x304 0x308 0x30C 0x310 0x314 0x318 0x31C 0x320 0x324 0x328 0x32C 0x330 0x334 0x338 0x33C ) group.long ($2+0x1C00)++0x3 line.long 0x0 "REGG7_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xD0 0xD1 0xD2 0xD3 0xD4 0xD5 0xD6 0xD7 0xD8 0xD9 0xDA 0xDB 0xDC 0xDD 0xDE 0xDF )(list 0x340 0x344 0x348 0x34C 0x350 0x354 0x358 0x35C 0x360 0x364 0x368 0x36C 0x370 0x374 0x378 0x37C ) group.long ($2+0x1C00)++0x3 line.long 0x0 "REGG7_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xE0 0xE1 0xE2 0xE3 0xE4 0xE5 0xE6 0xE7 0xE8 0xE9 0xEA 0xEB 0xEC 0xED 0xEE 0xEF )(list 0x380 0x384 0x388 0x38C 0x390 0x394 0x398 0x39C 0x3A0 0x3A4 0x3A8 0x3AC 0x3B0 0x3B4 0x3B8 0x3BC ) group.long ($2+0x1C00)++0x3 line.long 0x0 "REGG7_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xF0 0xF1 0xF2 0xF3 0xF4 0xF5 0xF6 0xF7 0xF8 0xF9 0xFA 0xFB 0xFC 0xFD 0xFE 0xFF )(list 0x3C0 0x3C4 0x3C8 0x3CC 0x3D0 0x3D4 0x3D8 0x3DC 0x3E0 0x3E4 0x3E8 0x3EC 0x3F0 0x3F4 0x3F8 0x3FC ) group.long ($2+0x1C00)++0x3 line.long 0x0 "REGG7_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end group.long 0x2000++0x17 line.long 0x0 "GLB_CTL,This register provides global enable settings for permission control." bitfld.long 0x0 5. "DOM_CFG_LOCK,Lock write for DOM_CFG_MODE bit." "0,1" bitfld.long 0x0 4. "DOM_CFG_MODE,When enabled all the source setting can be configured by master from domain 0 if it is not locked. When disabled only resource manager can configure the permission of the resource." "0,1" bitfld.long 0x0 3. "PERCK_DIS_LOCK,Lock write for PERCK_DIS" "0,1" bitfld.long 0x0 2. "PERCK_DIS,All the permission check disable." "0,1" newline bitfld.long 0x0 1. "DOM_PRO_LOCK,Lock write for DOM_PRO_EN bit." "0,1" bitfld.long 0x0 0. "DOM_PRO_EN,When disabled no domain access permission check" "0,1" line.long 0x4 "RES_MGR,Resource manager register. This regster is used to assign resource manager for global resource access control" bitfld.long 0x4 17. "MID_LOCK,Lock write for MID_EN and MID_LOW and MID_HIG registers." "0,1" bitfld.long 0x4 16. "MID_EN,Master ID check enable" "0,1" bitfld.long 0x4 15. "PRI_PER_LOCK,Lock write for PRI_PER and PRI_PER_EN" "0,1" bitfld.long 0x4 13.--14. "PRI_PER,Resource manager privileged access permission. bit0 for privileged access bit1 for user access" "0,1,2,3" newline bitfld.long 0x4 12. "PRI_PER_EN,Resource manager privileged access permission enable." "0,1" bitfld.long 0x4 11. "SEC_PER_LOCK,Lock for SEC_PER and SEC_PER_LOCK" "0,1" bitfld.long 0x4 9.--10. "SEC_PER,Resource manager secure access permission. bit 0 for secure access bit 1 for non-secure access" "0,1,2,3" bitfld.long 0x4 8. "SEC_PER_EN,Resource manager secure permission enable" "0,1" bitfld.long 0x4 7. "DID_LOCK,Lock write for DID_EN and DID" "0,1" newline hexmask.long.byte 0x4 3.--6. 1. "DID,Resource manager domain ID" bitfld.long 0x4 2. "DID_EN,Resource manager Domain ID enable" "0,1" bitfld.long 0x4 1. "RES_MGR_EN_LOCK,Lock for RES_MGR_EN" "0,1" bitfld.long 0x4 0. "RES_MGR_EN,Resource manager enable. When the bit is disable there is no resource manager." "0,1" line.long 0x8 "RES_MGR_MA0,This register is used to assign master 0~31 as resource manager." hexmask.long 0x8 0.--31. 1. "MID,Assign master 0~31 for resource manager" line.long 0xC "RES_MGR_MA1,This register is used to assign master 32~63 as resource manager." hexmask.long 0xC 0.--31. 1. "MID,Indicate if master 32~63 is resource manager." line.long 0x10 "RES_MGR_MA2,This register is used to assign master 64~95 as resource manager." hexmask.long 0x10 0.--31. 1. "MID,Indicate if master 64~95 is resource manager." line.long 0x14 "RES_MGR_MA3,This register is used to assign master 96~127 as resource manager." hexmask.long 0x14 0.--31. 1. "MID,Indicate if master 96~127 is resource manager." repeat 8. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 )(list 0x0 0x14 0x28 0x3C 0x50 0x64 0x78 0x8C ) group.long ($2+0x2100)++0x3 line.long 0x0 "GRP_MGR_$1,Group Manager Register. This register is used to assign group manager for each domain" bitfld.long 0x0 17. "MID_LOCK,Lock write for MID_EN and MID_LOW and MID_HIG registers." "0,1" bitfld.long 0x0 16. "MID_EN,Master ID check enable" "0,1" bitfld.long 0x0 15. "PRI_PER_LOCK,Lock write for PRI_PER and PRI_PER_EN" "0,1" bitfld.long 0x0 13.--14. "PRI_PER,Group manager privileged access permission. bit0 for privileged access bit1 for user access" "0,1,2,3" newline bitfld.long 0x0 12. "PRI_PER_EN,Group manager privileged access permission enable." "0,1" bitfld.long 0x0 11. "SEC_PER_LOCK,Lock for SEC_PER and SEC_PER_LOCK" "0,1" bitfld.long 0x0 9.--10. "SEC_PER,Group manager secure access permission. bit 0 for secure access bit 1 for non-secure access" "0,1,2,3" bitfld.long 0x0 8. "SEC_PER_EN,Group manager secure permission enable" "0,1" bitfld.long 0x0 7. "DID_LOCK,Lock write for DID_EN and DID" "0,1" newline hexmask.long.byte 0x0 3.--6. 1. "DID,Group manager domain ID" bitfld.long 0x0 2. "DID_EN,Group manager Domain ID enable" "0,1" bitfld.long 0x0 1. "GRP_MGR_EN_LOCK,Lock write for GPR_MGR_EN" "0,1" bitfld.long 0x0 0. "GRP_MGR_EN,Group manager enable. When the bit is disable there is no resource manager." "0,1" repeat.end repeat 8. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 )(list 0x0 0x14 0x28 0x3C 0x50 0x64 0x78 0x8C ) group.long ($2+0x2104)++0x3 line.long 0x0 "GRP_MGR_MA0_$1,Assign master 0~31 for group manager 0" hexmask.long 0x0 0.--31. 1. "MID,Assign master 0~31 for resource manager" repeat.end repeat 8. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 )(list 0x0 0x14 0x28 0x3C 0x50 0x64 0x78 0x8C ) group.long ($2+0x2108)++0x3 line.long 0x0 "GRP_MGR_MA1_$1,Assign master 32~63 for group manager 0" hexmask.long 0x0 0.--31. 1. "MID,Indicate if master 32~63 is resource manager." repeat.end repeat 8. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 )(list 0x0 0x14 0x28 0x3C 0x50 0x64 0x78 0x8C ) group.long ($2+0x210C)++0x3 line.long 0x0 "GRP_MGR_MA2_$1,Assign master 64~95 for group manager 0" hexmask.long 0x0 0.--31. 1. "MID,Indicate if master 64~95 is resource manager." repeat.end repeat 8. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 )(list 0x0 0x14 0x28 0x3C 0x50 0x64 0x78 0x8C ) group.long ($2+0x2110)++0x3 line.long 0x0 "GRP_MGR_MA3_$1,Assign master 96~127 for group manager 0" hexmask.long 0x0 0.--31. 1. "MID,Indicate if master 96~127 is resource manager." repeat.end group.long 0x2200++0x3 line.long 0x0 "DOM_GID_0,Indicate which group domain 0 belong to" bitfld.long 0x0 3. "LOCK,Lock write for GID" "0,1" bitfld.long 0x0 0.--2. "GID,Group ID" "0,1,2,3,4,5,6,7" repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x18 0x30 0x48 0x60 0x78 0x90 0xA8 0xC0 0xD8 0xF0 0x108 0x120 0x138 0x150 0x168 ) group.long ($2+0x2204)++0x3 line.long 0x0 "DOM_OWN_$1,Assign owner for function domain 0." bitfld.long 0x0 17. "MID_LOCK,Lock write for MID_EN and MID_LOW and MID_HIG registers." "0,1" bitfld.long 0x0 16. "MID_EN,Master ID check enable" "0,1" bitfld.long 0x0 15. "PRI_PER_LOCK,Lock write for PRI_PER and PRI_PER_EN" "0,1" bitfld.long 0x0 13.--14. "PRI_PER,Group manager privileged access permission. bit0 for privileged access bit1 for user access" "0,1,2,3" newline bitfld.long 0x0 12. "PRI_PER_EN,Group manager privileged access permission enable." "0,1" bitfld.long 0x0 11. "SEC_PER_LOCK,Lock for SEC_PER and SEC_PER_LOCK" "0,1" bitfld.long 0x0 9.--10. "SEC_PER,Domain owner secure access permission. bit 0 for secure access bit 1 for non-secure access" "0,1,2,3" bitfld.long 0x0 8. "SEC_PER_EN,Domain owner secure permission enable" "0,1" newline bitfld.long 0x0 1. "DOM_OWN_EN_LOCK,Lock for DOM_OWN_EN" "0,1" bitfld.long 0x0 0. "DOM_OWN_EN,Domain owner enable. When the bit is disable there is no domain owner." "0,1" repeat.end repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x18 0x30 0x48 0x60 0x78 0x90 0xA8 0xC0 0xD8 0xF0 0x108 0x120 0x138 0x150 0x168 ) group.long ($2+0x2208)++0x3 line.long 0x0 "DOM_OWN_MA0_$1,Assign master 0~31 for domain owner 0" hexmask.long 0x0 0.--31. 1. "MID,Assign master 0~31 for resource manager" repeat.end repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x18 0x30 0x48 0x60 0x78 0x90 0xA8 0xC0 0xD8 0xF0 0x108 0x120 0x138 0x150 0x168 ) group.long ($2+0x220C)++0x3 line.long 0x0 "DOM_OWN_MA1_$1,Assign master 32~63 for domain owner 0" hexmask.long 0x0 0.--31. 1. "MID,Indicate if master 32~63 is resource manager." repeat.end repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x18 0x30 0x48 0x60 0x78 0x90 0xA8 0xC0 0xD8 0xF0 0x108 0x120 0x138 0x150 0x168 ) group.long ($2+0x2210)++0x3 line.long 0x0 "DOM_OWN_MA2_$1,Assign master 64~95 for domain owner 0" hexmask.long 0x0 0.--31. 1. "MID,Indicate if master 64~95 is resource manager." repeat.end repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x18 0x30 0x48 0x60 0x78 0x90 0xA8 0xC0 0xD8 0xF0 0x108 0x120 0x138 0x150 0x168 ) group.long ($2+0x2214)++0x3 line.long 0x0 "DOM_OWN_MA3_$1,Assign master 96~127 for domain owner 0" hexmask.long 0x0 0.--31. 1. "MID,Indicate if master 96~127 is resource manager." repeat.end group.long 0x2218++0x3 line.long 0x0 "DOM_GID_1,Indicate which group domain 1 belong to" bitfld.long 0x0 3. "LOCK,Lock write for GID" "0,1" bitfld.long 0x0 0.--2. "GID,Group ID" "0,1,2,3,4,5,6,7" group.long 0x2230++0x3 line.long 0x0 "DOM_GID_2,Indicate which group domain 2 belong to" bitfld.long 0x0 3. "LOCK,Lock write for GID" "0,1" bitfld.long 0x0 0.--2. "GID,Group ID" "0,1,2,3,4,5,6,7" group.long 0x2248++0x3 line.long 0x0 "DOM_GID_3,Indicate which group domain 3 belong to" bitfld.long 0x0 3. "LOCK,Lock write for GID" "0,1" bitfld.long 0x0 0.--2. "GID,Group ID" "0,1,2,3,4,5,6,7" group.long 0x2260++0x3 line.long 0x0 "DOM_GID_4,Indicate which group domain 4 belong to" bitfld.long 0x0 3. "LOCK,Lock write for GID" "0,1" bitfld.long 0x0 0.--2. "GID,Group ID" "0,1,2,3,4,5,6,7" group.long 0x2278++0x3 line.long 0x0 "DOM_GID_5,Indicate which group domain 5 belong to" bitfld.long 0x0 3. "LOCK,Lock write for GID" "0,1" bitfld.long 0x0 0.--2. "GID,Group ID" "0,1,2,3,4,5,6,7" group.long 0x2290++0x3 line.long 0x0 "DOM_GID_6,Indicate which group domain 6 belong to" bitfld.long 0x0 3. "LOCK,Lock write for GID" "0,1" bitfld.long 0x0 0.--2. "GID,Group ID" "0,1,2,3,4,5,6,7" group.long 0x22A8++0x3 line.long 0x0 "DOM_GID_7,Indicate which group domain 7 belong to" bitfld.long 0x0 3. "LOCK,Lock write for GID" "0,1" bitfld.long 0x0 0.--2. "GID,Group ID" "0,1,2,3,4,5,6,7" group.long 0x22C0++0x3 line.long 0x0 "DOM_GID_8,Indicate which group domain 8 belong to" bitfld.long 0x0 3. "LOCK,Lock write for GID" "0,1" bitfld.long 0x0 0.--2. "GID,Group ID" "0,1,2,3,4,5,6,7" group.long 0x22D8++0x3 line.long 0x0 "DOM_GID_9,Indicate which group domain 9 belong to" bitfld.long 0x0 3. "LOCK,Lock write for GID" "0,1" bitfld.long 0x0 0.--2. "GID,Group ID" "0,1,2,3,4,5,6,7" group.long 0x22F0++0x3 line.long 0x0 "DOM_GID_10,Indicate which group domain 10 belong to" bitfld.long 0x0 3. "LOCK,Lock write for GID" "0,1" bitfld.long 0x0 0.--2. "GID,Group ID" "0,1,2,3,4,5,6,7" group.long 0x2308++0x3 line.long 0x0 "DOM_GID_11,Indicate which group domain 11 belong to" bitfld.long 0x0 3. "LOCK,Lock write for GID" "0,1" bitfld.long 0x0 0.--2. "GID,Group ID" "0,1,2,3,4,5,6,7" group.long 0x2320++0x3 line.long 0x0 "DOM_GID_12,Indicate which group domain 12 belong to" bitfld.long 0x0 3. "LOCK,Lock write for GID" "0,1" bitfld.long 0x0 0.--2. "GID,Group ID" "0,1,2,3,4,5,6,7" group.long 0x2338++0x3 line.long 0x0 "DOM_GID_13,Indicate which group domain 13 belong to" bitfld.long 0x0 3. "LOCK,Lock write for GID" "0,1" bitfld.long 0x0 0.--2. "GID,Group ID" "0,1,2,3,4,5,6,7" group.long 0x2350++0x3 line.long 0x0 "DOM_GID_14,Indicate which group domain 14 belong to" bitfld.long 0x0 3. "LOCK,Lock write for GID" "0,1" bitfld.long 0x0 0.--2. "GID,Group ID" "0,1,2,3,4,5,6,7" group.long 0x2368++0x3 line.long 0x0 "DOM_GID_15,Indicate which group domain 15 belong to" bitfld.long 0x0 3. "LOCK,Lock write for GID" "0,1" bitfld.long 0x0 0.--2. "GID,Group ID" "0,1,2,3,4,5,6,7" repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x34 0x68 0x9C 0xD0 0x104 0x138 0x16C 0x1A0 0x1D4 0x208 0x23C 0x270 0x2A4 0x2D8 0x30C ) group.long ($2+0x2400)++0x3 line.long 0x0 "DOM_PER0_$1,Domain Permission Control. It can be only configured by resource manager and domain owner." bitfld.long 0x0 31. "DOM7_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 29.--30. "DOM7_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 28. "DOM7_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 27. "DOM6_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 25.--26. "DOM6_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" newline bitfld.long 0x0 24. "DOM6_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 23. "DOM5_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 21.--22. "DOM5_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 20. "DOM5_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 19. "DOM4_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" newline bitfld.long 0x0 17.--18. "DOM4_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM4_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 15. "DOM3_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 13.--14. "DOM3_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 12. "DOM3_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" newline bitfld.long 0x0 11. "DOM2_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 9.--10. "DOM2_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM2_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 7. "DOM1_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 5.--6. "DOM1_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" newline bitfld.long 0x0 4. "DOM1_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 3. "DOM0_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 1.--2. "DOM0_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM0_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" repeat.end repeat 16. (list 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1A 0x1B 0x1C 0x1D 0x1E 0x1F )(list 0x340 0x374 0x3A8 0x3DC 0x410 0x444 0x478 0x4AC 0x4E0 0x514 0x548 0x57C 0x5B0 0x5E4 0x618 0x64C ) group.long ($2+0x2400)++0x3 line.long 0x0 "DOM_PER0_$1,Domain Permission Control. It can be only configured by resource manager and domain owner." bitfld.long 0x0 31. "DOM7_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 29.--30. "DOM7_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 28. "DOM7_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 27. "DOM6_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 25.--26. "DOM6_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" newline bitfld.long 0x0 24. "DOM6_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 23. "DOM5_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 21.--22. "DOM5_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 20. "DOM5_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 19. "DOM4_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" newline bitfld.long 0x0 17.--18. "DOM4_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM4_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 15. "DOM3_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 13.--14. "DOM3_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 12. "DOM3_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" newline bitfld.long 0x0 11. "DOM2_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 9.--10. "DOM2_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM2_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 7. "DOM1_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 5.--6. "DOM1_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" newline bitfld.long 0x0 4. "DOM1_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 3. "DOM0_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 1.--2. "DOM0_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM0_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" repeat.end repeat 16. (list 0x20 0x21 0x22 0x23 0x24 0x25 0x26 0x27 0x28 0x29 0x2A 0x2B 0x2C 0x2D 0x2E 0x2F )(list 0x680 0x6B4 0x6E8 0x71C 0x750 0x784 0x7B8 0x7EC 0x820 0x854 0x888 0x8BC 0x8F0 0x924 0x958 0x98C ) group.long ($2+0x2400)++0x3 line.long 0x0 "DOM_PER0_$1,Domain Permission Control. It can be only configured by resource manager and domain owner." bitfld.long 0x0 31. "DOM7_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 29.--30. "DOM7_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 28. "DOM7_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 27. "DOM6_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 25.--26. "DOM6_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" newline bitfld.long 0x0 24. "DOM6_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 23. "DOM5_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 21.--22. "DOM5_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 20. "DOM5_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 19. "DOM4_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" newline bitfld.long 0x0 17.--18. "DOM4_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM4_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 15. "DOM3_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 13.--14. "DOM3_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 12. "DOM3_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" newline bitfld.long 0x0 11. "DOM2_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 9.--10. "DOM2_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM2_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 7. "DOM1_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 5.--6. "DOM1_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" newline bitfld.long 0x0 4. "DOM1_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 3. "DOM0_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 1.--2. "DOM0_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM0_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" repeat.end repeat 16. (list 0x30 0x31 0x32 0x33 0x34 0x35 0x36 0x37 0x38 0x39 0x3A 0x3B 0x3C 0x3D 0x3E 0x3F )(list 0x9C0 0x9F4 0xA28 0xA5C 0xA90 0xAC4 0xAF8 0xB2C 0xB60 0xB94 0xBC8 0xBFC 0xC30 0xC64 0xC98 0xCCC ) group.long ($2+0x2400)++0x3 line.long 0x0 "DOM_PER0_$1,Domain Permission Control. It can be only configured by resource manager and domain owner." bitfld.long 0x0 31. "DOM7_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 29.--30. "DOM7_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 28. "DOM7_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 27. "DOM6_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 25.--26. "DOM6_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" newline bitfld.long 0x0 24. "DOM6_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 23. "DOM5_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 21.--22. "DOM5_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 20. "DOM5_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 19. "DOM4_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" newline bitfld.long 0x0 17.--18. "DOM4_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM4_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 15. "DOM3_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 13.--14. "DOM3_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 12. "DOM3_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" newline bitfld.long 0x0 11. "DOM2_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 9.--10. "DOM2_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM2_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 7. "DOM1_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 5.--6. "DOM1_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" newline bitfld.long 0x0 4. "DOM1_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 3. "DOM0_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 1.--2. "DOM0_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM0_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" repeat.end repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x34 0x68 0x9C 0xD0 0x104 0x138 0x16C 0x1A0 0x1D4 0x208 0x23C 0x270 0x2A4 0x2D8 0x30C ) group.long ($2+0x2404)++0x3 line.long 0x0 "DOM_PER1_$1,Domain Permission Control. It can be only configured by resource manager and domain owner." bitfld.long 0x0 31. "DOM15_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 29.--30. "DOM15_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 28. "DOM15_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 27. "DOM14_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 25.--26. "DOM14_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" newline bitfld.long 0x0 24. "DOM14_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 23. "DOM13_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 21.--22. "DOM13_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 20. "DOM13_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 19. "DOM12_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" newline bitfld.long 0x0 17.--18. "DOM12_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM12_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 15. "DOM11_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 13.--14. "DOM11_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 12. "DOM11_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" newline bitfld.long 0x0 11. "DOM10_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 9.--10. "DOM10_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM10_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 7. "DOM9_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 5.--6. "DOM9_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" newline bitfld.long 0x0 4. "DOM9_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 3. "DOM8_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 1.--2. "DOM8_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM8_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" repeat.end repeat 16. (list 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1A 0x1B 0x1C 0x1D 0x1E 0x1F )(list 0x340 0x374 0x3A8 0x3DC 0x410 0x444 0x478 0x4AC 0x4E0 0x514 0x548 0x57C 0x5B0 0x5E4 0x618 0x64C ) group.long ($2+0x2404)++0x3 line.long 0x0 "DOM_PER1_$1,Domain Permission Control. It can be only configured by resource manager and domain owner." bitfld.long 0x0 31. "DOM15_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 29.--30. "DOM15_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 28. "DOM15_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 27. "DOM14_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 25.--26. "DOM14_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" newline bitfld.long 0x0 24. "DOM14_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 23. "DOM13_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 21.--22. "DOM13_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 20. "DOM13_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 19. "DOM12_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" newline bitfld.long 0x0 17.--18. "DOM12_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM12_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 15. "DOM11_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 13.--14. "DOM11_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 12. "DOM11_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" newline bitfld.long 0x0 11. "DOM10_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 9.--10. "DOM10_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM10_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 7. "DOM9_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 5.--6. "DOM9_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" newline bitfld.long 0x0 4. "DOM9_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 3. "DOM8_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 1.--2. "DOM8_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM8_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" repeat.end repeat 16. (list 0x20 0x21 0x22 0x23 0x24 0x25 0x26 0x27 0x28 0x29 0x2A 0x2B 0x2C 0x2D 0x2E 0x2F )(list 0x680 0x6B4 0x6E8 0x71C 0x750 0x784 0x7B8 0x7EC 0x820 0x854 0x888 0x8BC 0x8F0 0x924 0x958 0x98C ) group.long ($2+0x2404)++0x3 line.long 0x0 "DOM_PER1_$1,Domain Permission Control. It can be only configured by resource manager and domain owner." bitfld.long 0x0 31. "DOM15_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 29.--30. "DOM15_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 28. "DOM15_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 27. "DOM14_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 25.--26. "DOM14_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" newline bitfld.long 0x0 24. "DOM14_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 23. "DOM13_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 21.--22. "DOM13_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 20. "DOM13_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 19. "DOM12_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" newline bitfld.long 0x0 17.--18. "DOM12_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM12_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 15. "DOM11_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 13.--14. "DOM11_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 12. "DOM11_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" newline bitfld.long 0x0 11. "DOM10_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 9.--10. "DOM10_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM10_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 7. "DOM9_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 5.--6. "DOM9_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" newline bitfld.long 0x0 4. "DOM9_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 3. "DOM8_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 1.--2. "DOM8_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM8_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" repeat.end repeat 16. (list 0x30 0x31 0x32 0x33 0x34 0x35 0x36 0x37 0x38 0x39 0x3A 0x3B 0x3C 0x3D 0x3E 0x3F )(list 0x9C0 0x9F4 0xA28 0xA5C 0xA90 0xAC4 0xAF8 0xB2C 0xB60 0xB94 0xBC8 0xBFC 0xC30 0xC64 0xC98 0xCCC ) group.long ($2+0x2404)++0x3 line.long 0x0 "DOM_PER1_$1,Domain Permission Control. It can be only configured by resource manager and domain owner." bitfld.long 0x0 31. "DOM15_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 29.--30. "DOM15_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 28. "DOM15_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 27. "DOM14_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 25.--26. "DOM14_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" newline bitfld.long 0x0 24. "DOM14_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 23. "DOM13_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 21.--22. "DOM13_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 20. "DOM13_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 19. "DOM12_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" newline bitfld.long 0x0 17.--18. "DOM12_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM12_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 15. "DOM11_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 13.--14. "DOM11_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 12. "DOM11_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" newline bitfld.long 0x0 11. "DOM10_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 9.--10. "DOM10_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM10_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 7. "DOM9_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 5.--6. "DOM9_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" newline bitfld.long 0x0 4. "DOM9_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 3. "DOM8_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 1.--2. "DOM8_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM8_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" repeat.end repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x34 0x68 0x9C 0xD0 0x104 0x138 0x16C 0x1A0 0x1D4 0x208 0x23C 0x270 0x2A4 0x2D8 0x30C ) group.long ($2+0x2408)++0x3 line.long 0x0 "SEC_PER0_$1,This register is only used for resource manager to control secure access permission." bitfld.long 0x0 31. "DOM3_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM3_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM3_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM3_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM2_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM2_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM2_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM2_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM1_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM1_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM1_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM1_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM0_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM0_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM0_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM0_SEC_EN,Domain secure permission control enable" "0,1" repeat.end repeat 16. (list 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1A 0x1B 0x1C 0x1D 0x1E 0x1F )(list 0x340 0x374 0x3A8 0x3DC 0x410 0x444 0x478 0x4AC 0x4E0 0x514 0x548 0x57C 0x5B0 0x5E4 0x618 0x64C ) group.long ($2+0x2408)++0x3 line.long 0x0 "SEC_PER0_$1,This register is only used for resource manager to control secure access permission." bitfld.long 0x0 31. "DOM3_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM3_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM3_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM3_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM2_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM2_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM2_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM2_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM1_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM1_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM1_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM1_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM0_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM0_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM0_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM0_SEC_EN,Domain secure permission control enable" "0,1" repeat.end repeat 16. (list 0x20 0x21 0x22 0x23 0x24 0x25 0x26 0x27 0x28 0x29 0x2A 0x2B 0x2C 0x2D 0x2E 0x2F )(list 0x680 0x6B4 0x6E8 0x71C 0x750 0x784 0x7B8 0x7EC 0x820 0x854 0x888 0x8BC 0x8F0 0x924 0x958 0x98C ) group.long ($2+0x2408)++0x3 line.long 0x0 "SEC_PER0_$1,This register is only used for resource manager to control secure access permission." bitfld.long 0x0 31. "DOM3_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM3_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM3_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM3_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM2_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM2_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM2_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM2_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM1_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM1_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM1_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM1_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM0_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM0_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM0_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM0_SEC_EN,Domain secure permission control enable" "0,1" repeat.end repeat 16. (list 0x30 0x31 0x32 0x33 0x34 0x35 0x36 0x37 0x38 0x39 0x3A 0x3B 0x3C 0x3D 0x3E 0x3F )(list 0x9C0 0x9F4 0xA28 0xA5C 0xA90 0xAC4 0xAF8 0xB2C 0xB60 0xB94 0xBC8 0xBFC 0xC30 0xC64 0xC98 0xCCC ) group.long ($2+0x2408)++0x3 line.long 0x0 "SEC_PER0_$1,This register is only used for resource manager to control secure access permission." bitfld.long 0x0 31. "DOM3_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM3_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM3_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM3_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM2_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM2_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM2_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM2_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM1_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM1_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM1_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM1_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM0_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM0_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM0_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM0_SEC_EN,Domain secure permission control enable" "0,1" repeat.end repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x34 0x68 0x9C 0xD0 0x104 0x138 0x16C 0x1A0 0x1D4 0x208 0x23C 0x270 0x2A4 0x2D8 0x30C ) group.long ($2+0x240C)++0x3 line.long 0x0 "SEC_PER1_$1,This register is only used for resource manager to control secure access permission." bitfld.long 0x0 31. "DOM7_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM7_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM7_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM7_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM6_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM6_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM6_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM6_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM5_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM5_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM5_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM5_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM4_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM4_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM4_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM4_SEC_EN,Domain secure permission control enable" "0,1" repeat.end repeat 16. (list 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1A 0x1B 0x1C 0x1D 0x1E 0x1F )(list 0x340 0x374 0x3A8 0x3DC 0x410 0x444 0x478 0x4AC 0x4E0 0x514 0x548 0x57C 0x5B0 0x5E4 0x618 0x64C ) group.long ($2+0x240C)++0x3 line.long 0x0 "SEC_PER1_$1,This register is only used for resource manager to control secure access permission." bitfld.long 0x0 31. "DOM7_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM7_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM7_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM7_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM6_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM6_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM6_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM6_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM5_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM5_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM5_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM5_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM4_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM4_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM4_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM4_SEC_EN,Domain secure permission control enable" "0,1" repeat.end repeat 16. (list 0x20 0x21 0x22 0x23 0x24 0x25 0x26 0x27 0x28 0x29 0x2A 0x2B 0x2C 0x2D 0x2E 0x2F )(list 0x680 0x6B4 0x6E8 0x71C 0x750 0x784 0x7B8 0x7EC 0x820 0x854 0x888 0x8BC 0x8F0 0x924 0x958 0x98C ) group.long ($2+0x240C)++0x3 line.long 0x0 "SEC_PER1_$1,This register is only used for resource manager to control secure access permission." bitfld.long 0x0 31. "DOM7_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM7_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM7_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM7_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM6_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM6_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM6_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM6_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM5_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM5_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM5_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM5_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM4_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM4_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM4_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM4_SEC_EN,Domain secure permission control enable" "0,1" repeat.end repeat 16. (list 0x30 0x31 0x32 0x33 0x34 0x35 0x36 0x37 0x38 0x39 0x3A 0x3B 0x3C 0x3D 0x3E 0x3F )(list 0x9C0 0x9F4 0xA28 0xA5C 0xA90 0xAC4 0xAF8 0xB2C 0xB60 0xB94 0xBC8 0xBFC 0xC30 0xC64 0xC98 0xCCC ) group.long ($2+0x240C)++0x3 line.long 0x0 "SEC_PER1_$1,This register is only used for resource manager to control secure access permission." bitfld.long 0x0 31. "DOM7_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM7_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM7_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM7_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM6_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM6_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM6_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM6_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM5_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM5_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM5_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM5_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM4_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM4_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM4_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM4_SEC_EN,Domain secure permission control enable" "0,1" repeat.end repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x34 0x68 0x9C 0xD0 0x104 0x138 0x16C 0x1A0 0x1D4 0x208 0x23C 0x270 0x2A4 0x2D8 0x30C ) group.long ($2+0x2410)++0x3 line.long 0x0 "SEC_PER2_$1,This register is only used for resource manager to control secure access permission." bitfld.long 0x0 31. "DOM11_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM11_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM11_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM11_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM10_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM10_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM10_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM10_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM9_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM9_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM9_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM9_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM8_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM8_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM8_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM8_SEC_EN,Domain secure permission control enable" "0,1" repeat.end repeat 16. (list 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1A 0x1B 0x1C 0x1D 0x1E 0x1F )(list 0x340 0x374 0x3A8 0x3DC 0x410 0x444 0x478 0x4AC 0x4E0 0x514 0x548 0x57C 0x5B0 0x5E4 0x618 0x64C ) group.long ($2+0x2410)++0x3 line.long 0x0 "SEC_PER2_$1,This register is only used for resource manager to control secure access permission." bitfld.long 0x0 31. "DOM11_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM11_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM11_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM11_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM10_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM10_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM10_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM10_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM9_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM9_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM9_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM9_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM8_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM8_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM8_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM8_SEC_EN,Domain secure permission control enable" "0,1" repeat.end repeat 16. (list 0x20 0x21 0x22 0x23 0x24 0x25 0x26 0x27 0x28 0x29 0x2A 0x2B 0x2C 0x2D 0x2E 0x2F )(list 0x680 0x6B4 0x6E8 0x71C 0x750 0x784 0x7B8 0x7EC 0x820 0x854 0x888 0x8BC 0x8F0 0x924 0x958 0x98C ) group.long ($2+0x2410)++0x3 line.long 0x0 "SEC_PER2_$1,This register is only used for resource manager to control secure access permission." bitfld.long 0x0 31. "DOM11_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM11_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM11_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM11_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM10_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM10_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM10_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM10_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM9_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM9_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM9_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM9_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM8_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM8_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM8_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM8_SEC_EN,Domain secure permission control enable" "0,1" repeat.end repeat 16. (list 0x30 0x31 0x32 0x33 0x34 0x35 0x36 0x37 0x38 0x39 0x3A 0x3B 0x3C 0x3D 0x3E 0x3F )(list 0x9C0 0x9F4 0xA28 0xA5C 0xA90 0xAC4 0xAF8 0xB2C 0xB60 0xB94 0xBC8 0xBFC 0xC30 0xC64 0xC98 0xCCC ) group.long ($2+0x2410)++0x3 line.long 0x0 "SEC_PER2_$1,This register is only used for resource manager to control secure access permission." bitfld.long 0x0 31. "DOM11_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM11_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM11_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM11_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM10_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM10_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM10_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM10_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM9_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM9_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM9_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM9_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM8_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM8_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM8_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM8_SEC_EN,Domain secure permission control enable" "0,1" repeat.end repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x34 0x68 0x9C 0xD0 0x104 0x138 0x16C 0x1A0 0x1D4 0x208 0x23C 0x270 0x2A4 0x2D8 0x30C ) group.long ($2+0x2414)++0x3 line.long 0x0 "SEC_PER3_$1,This register is only used for resource manager to control secure access permission." bitfld.long 0x0 31. "DOM15_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM15_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM15_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM15_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM14_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM14_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM14_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM14_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM13_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM13_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM13_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM13_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM12_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM12_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM12_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM12_SEC_EN,Domain secure permission control enable" "0,1" repeat.end repeat 16. (list 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1A 0x1B 0x1C 0x1D 0x1E 0x1F )(list 0x340 0x374 0x3A8 0x3DC 0x410 0x444 0x478 0x4AC 0x4E0 0x514 0x548 0x57C 0x5B0 0x5E4 0x618 0x64C ) group.long ($2+0x2414)++0x3 line.long 0x0 "SEC_PER3_$1,This register is only used for resource manager to control secure access permission." bitfld.long 0x0 31. "DOM15_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM15_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM15_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM15_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM14_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM14_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM14_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM14_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM13_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM13_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM13_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM13_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM12_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM12_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM12_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM12_SEC_EN,Domain secure permission control enable" "0,1" repeat.end repeat 16. (list 0x20 0x21 0x22 0x23 0x24 0x25 0x26 0x27 0x28 0x29 0x2A 0x2B 0x2C 0x2D 0x2E 0x2F )(list 0x680 0x6B4 0x6E8 0x71C 0x750 0x784 0x7B8 0x7EC 0x820 0x854 0x888 0x8BC 0x8F0 0x924 0x958 0x98C ) group.long ($2+0x2414)++0x3 line.long 0x0 "SEC_PER3_$1,This register is only used for resource manager to control secure access permission." bitfld.long 0x0 31. "DOM15_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM15_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM15_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM15_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM14_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM14_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM14_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM14_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM13_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM13_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM13_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM13_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM12_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM12_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM12_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM12_SEC_EN,Domain secure permission control enable" "0,1" repeat.end repeat 16. (list 0x30 0x31 0x32 0x33 0x34 0x35 0x36 0x37 0x38 0x39 0x3A 0x3B 0x3C 0x3D 0x3E 0x3F )(list 0x9C0 0x9F4 0xA28 0xA5C 0xA90 0xAC4 0xAF8 0xB2C 0xB60 0xB94 0xBC8 0xBFC 0xC30 0xC64 0xC98 0xCCC ) group.long ($2+0x2414)++0x3 line.long 0x0 "SEC_PER3_$1,This register is only used for resource manager to control secure access permission." bitfld.long 0x0 31. "DOM15_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM15_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM15_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM15_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM14_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM14_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM14_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM14_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM13_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM13_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM13_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM13_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM12_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM12_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM12_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM12_SEC_EN,Domain secure permission control enable" "0,1" repeat.end repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x34 0x68 0x9C 0xD0 0x104 0x138 0x16C 0x1A0 0x1D4 0x208 0x23C 0x270 0x2A4 0x2D8 0x30C ) group.long ($2+0x2418)++0x3 line.long 0x0 "PRI_PER0_$1,This register is only used for resource manager to control privileged access permission." bitfld.long 0x0 31. "DOM3_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM3_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM3_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM3_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM2_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM2_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM2_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM2_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM1_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM1_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM1_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM1_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM0_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM0_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM0_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM0_PRI_EN,Domain privileged permission control enable" "0,1" repeat.end repeat 16. (list 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1A 0x1B 0x1C 0x1D 0x1E 0x1F )(list 0x340 0x374 0x3A8 0x3DC 0x410 0x444 0x478 0x4AC 0x4E0 0x514 0x548 0x57C 0x5B0 0x5E4 0x618 0x64C ) group.long ($2+0x2418)++0x3 line.long 0x0 "PRI_PER0_$1,This register is only used for resource manager to control privileged access permission." bitfld.long 0x0 31. "DOM3_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM3_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM3_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM3_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM2_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM2_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM2_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM2_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM1_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM1_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM1_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM1_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM0_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM0_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM0_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM0_PRI_EN,Domain privileged permission control enable" "0,1" repeat.end repeat 16. (list 0x20 0x21 0x22 0x23 0x24 0x25 0x26 0x27 0x28 0x29 0x2A 0x2B 0x2C 0x2D 0x2E 0x2F )(list 0x680 0x6B4 0x6E8 0x71C 0x750 0x784 0x7B8 0x7EC 0x820 0x854 0x888 0x8BC 0x8F0 0x924 0x958 0x98C ) group.long ($2+0x2418)++0x3 line.long 0x0 "PRI_PER0_$1,This register is only used for resource manager to control privileged access permission." bitfld.long 0x0 31. "DOM3_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM3_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM3_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM3_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM2_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM2_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM2_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM2_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM1_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM1_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM1_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM1_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM0_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM0_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM0_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM0_PRI_EN,Domain privileged permission control enable" "0,1" repeat.end repeat 16. (list 0x30 0x31 0x32 0x33 0x34 0x35 0x36 0x37 0x38 0x39 0x3A 0x3B 0x3C 0x3D 0x3E 0x3F )(list 0x9C0 0x9F4 0xA28 0xA5C 0xA90 0xAC4 0xAF8 0xB2C 0xB60 0xB94 0xBC8 0xBFC 0xC30 0xC64 0xC98 0xCCC ) group.long ($2+0x2418)++0x3 line.long 0x0 "PRI_PER0_$1,This register is only used for resource manager to control privileged access permission." bitfld.long 0x0 31. "DOM3_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM3_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM3_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM3_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM2_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM2_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM2_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM2_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM1_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM1_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM1_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM1_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM0_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM0_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM0_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM0_PRI_EN,Domain privileged permission control enable" "0,1" repeat.end repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x34 0x68 0x9C 0xD0 0x104 0x138 0x16C 0x1A0 0x1D4 0x208 0x23C 0x270 0x2A4 0x2D8 0x30C ) group.long ($2+0x241C)++0x3 line.long 0x0 "PRI_PER1_$1,This register is only used for resource manager to control privileged access permission." bitfld.long 0x0 31. "DOM7_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM7_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM7_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM7_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM6_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM6_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM6_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM6_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM5_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM5_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM5_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM5_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM4_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM4_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM4_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM4_PRI_EN,Domain privileged permission control enable" "0,1" repeat.end repeat 16. (list 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1A 0x1B 0x1C 0x1D 0x1E 0x1F )(list 0x340 0x374 0x3A8 0x3DC 0x410 0x444 0x478 0x4AC 0x4E0 0x514 0x548 0x57C 0x5B0 0x5E4 0x618 0x64C ) group.long ($2+0x241C)++0x3 line.long 0x0 "PRI_PER1_$1,This register is only used for resource manager to control privileged access permission." bitfld.long 0x0 31. "DOM7_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM7_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM7_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM7_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM6_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM6_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM6_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM6_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM5_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM5_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM5_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM5_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM4_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM4_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM4_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM4_PRI_EN,Domain privileged permission control enable" "0,1" repeat.end repeat 16. (list 0x20 0x21 0x22 0x23 0x24 0x25 0x26 0x27 0x28 0x29 0x2A 0x2B 0x2C 0x2D 0x2E 0x2F )(list 0x680 0x6B4 0x6E8 0x71C 0x750 0x784 0x7B8 0x7EC 0x820 0x854 0x888 0x8BC 0x8F0 0x924 0x958 0x98C ) group.long ($2+0x241C)++0x3 line.long 0x0 "PRI_PER1_$1,This register is only used for resource manager to control privileged access permission." bitfld.long 0x0 31. "DOM7_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM7_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM7_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM7_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM6_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM6_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM6_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM6_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM5_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM5_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM5_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM5_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM4_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM4_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM4_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM4_PRI_EN,Domain privileged permission control enable" "0,1" repeat.end repeat 16. (list 0x30 0x31 0x32 0x33 0x34 0x35 0x36 0x37 0x38 0x39 0x3A 0x3B 0x3C 0x3D 0x3E 0x3F )(list 0x9C0 0x9F4 0xA28 0xA5C 0xA90 0xAC4 0xAF8 0xB2C 0xB60 0xB94 0xBC8 0xBFC 0xC30 0xC64 0xC98 0xCCC ) group.long ($2+0x241C)++0x3 line.long 0x0 "PRI_PER1_$1,This register is only used for resource manager to control privileged access permission." bitfld.long 0x0 31. "DOM7_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM7_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM7_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM7_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM6_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM6_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM6_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM6_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM5_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM5_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM5_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM5_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM4_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM4_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM4_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM4_PRI_EN,Domain privileged permission control enable" "0,1" repeat.end repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x34 0x68 0x9C 0xD0 0x104 0x138 0x16C 0x1A0 0x1D4 0x208 0x23C 0x270 0x2A4 0x2D8 0x30C ) group.long ($2+0x2420)++0x3 line.long 0x0 "PRI_PER2_$1,This register is only used for resource manager to control privileged access permission." bitfld.long 0x0 31. "DOM11_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM11_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM11_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM11_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM10_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM10_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM10_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM10_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM9_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM9_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM9_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM9_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM8_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM8_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM8_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM8_PRI_EN,Domain privileged permission control enable" "0,1" repeat.end repeat 16. (list 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1A 0x1B 0x1C 0x1D 0x1E 0x1F )(list 0x340 0x374 0x3A8 0x3DC 0x410 0x444 0x478 0x4AC 0x4E0 0x514 0x548 0x57C 0x5B0 0x5E4 0x618 0x64C ) group.long ($2+0x2420)++0x3 line.long 0x0 "PRI_PER2_$1,This register is only used for resource manager to control privileged access permission." bitfld.long 0x0 31. "DOM11_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM11_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM11_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM11_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM10_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM10_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM10_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM10_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM9_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM9_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM9_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM9_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM8_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM8_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM8_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM8_PRI_EN,Domain privileged permission control enable" "0,1" repeat.end repeat 16. (list 0x20 0x21 0x22 0x23 0x24 0x25 0x26 0x27 0x28 0x29 0x2A 0x2B 0x2C 0x2D 0x2E 0x2F )(list 0x680 0x6B4 0x6E8 0x71C 0x750 0x784 0x7B8 0x7EC 0x820 0x854 0x888 0x8BC 0x8F0 0x924 0x958 0x98C ) group.long ($2+0x2420)++0x3 line.long 0x0 "PRI_PER2_$1,This register is only used for resource manager to control privileged access permission." bitfld.long 0x0 31. "DOM11_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM11_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM11_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM11_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM10_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM10_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM10_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM10_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM9_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM9_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM9_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM9_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM8_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM8_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM8_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM8_PRI_EN,Domain privileged permission control enable" "0,1" repeat.end repeat 16. (list 0x30 0x31 0x32 0x33 0x34 0x35 0x36 0x37 0x38 0x39 0x3A 0x3B 0x3C 0x3D 0x3E 0x3F )(list 0x9C0 0x9F4 0xA28 0xA5C 0xA90 0xAC4 0xAF8 0xB2C 0xB60 0xB94 0xBC8 0xBFC 0xC30 0xC64 0xC98 0xCCC ) group.long ($2+0x2420)++0x3 line.long 0x0 "PRI_PER2_$1,This register is only used for resource manager to control privileged access permission." bitfld.long 0x0 31. "DOM11_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM11_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM11_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM11_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM10_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM10_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM10_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM10_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM9_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM9_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM9_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM9_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM8_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM8_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM8_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM8_PRI_EN,Domain privileged permission control enable" "0,1" repeat.end repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x34 0x68 0x9C 0xD0 0x104 0x138 0x16C 0x1A0 0x1D4 0x208 0x23C 0x270 0x2A4 0x2D8 0x30C ) group.long ($2+0x2424)++0x3 line.long 0x0 "PRI_PER3_$1,This register is only used for resource manager to control privileged access permission." bitfld.long 0x0 31. "DOM15_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM15_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM15_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM15_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM14_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM14_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM14_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM14_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM13_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM13_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM13_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM13_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM12_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM12_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM12_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM12_PRI_EN,Domain privileged permission control enable" "0,1" repeat.end repeat 16. (list 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1A 0x1B 0x1C 0x1D 0x1E 0x1F )(list 0x340 0x374 0x3A8 0x3DC 0x410 0x444 0x478 0x4AC 0x4E0 0x514 0x548 0x57C 0x5B0 0x5E4 0x618 0x64C ) group.long ($2+0x2424)++0x3 line.long 0x0 "PRI_PER3_$1,This register is only used for resource manager to control privileged access permission." bitfld.long 0x0 31. "DOM15_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM15_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM15_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM15_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM14_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM14_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM14_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM14_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM13_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM13_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM13_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM13_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM12_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM12_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM12_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM12_PRI_EN,Domain privileged permission control enable" "0,1" repeat.end repeat 16. (list 0x20 0x21 0x22 0x23 0x24 0x25 0x26 0x27 0x28 0x29 0x2A 0x2B 0x2C 0x2D 0x2E 0x2F )(list 0x680 0x6B4 0x6E8 0x71C 0x750 0x784 0x7B8 0x7EC 0x820 0x854 0x888 0x8BC 0x8F0 0x924 0x958 0x98C ) group.long ($2+0x2424)++0x3 line.long 0x0 "PRI_PER3_$1,This register is only used for resource manager to control privileged access permission." bitfld.long 0x0 31. "DOM15_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM15_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM15_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM15_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM14_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM14_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM14_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM14_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM13_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM13_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM13_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM13_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM12_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM12_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM12_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM12_PRI_EN,Domain privileged permission control enable" "0,1" repeat.end repeat 16. (list 0x30 0x31 0x32 0x33 0x34 0x35 0x36 0x37 0x38 0x39 0x3A 0x3B 0x3C 0x3D 0x3E 0x3F )(list 0x9C0 0x9F4 0xA28 0xA5C 0xA90 0xAC4 0xAF8 0xB2C 0xB60 0xB94 0xBC8 0xBFC 0xC30 0xC64 0xC98 0xCCC ) group.long ($2+0x2424)++0x3 line.long 0x0 "PRI_PER3_$1,This register is only used for resource manager to control privileged access permission." bitfld.long 0x0 31. "DOM15_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM15_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM15_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM15_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM14_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM14_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM14_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM14_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM13_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM13_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM13_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM13_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM12_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM12_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM12_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM12_PRI_EN,Domain privileged permission control enable" "0,1" repeat.end repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x34 0x68 0x9C 0xD0 0x104 0x138 0x16C 0x1A0 0x1D4 0x208 0x23C 0x270 0x2A4 0x2D8 0x30C ) group.long ($2+0x2428)++0x3 line.long 0x0 "DOM_SEC_PER_$1,This register is only used for domain master to control secure access permission. When the domain master write this register. it only changes the secure permission for itself. When the domain master read this register. it gets permission.." bitfld.long 0x0 7. "DOM_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" newline bitfld.long 0x0 0. "DOM_SEC_EN,Domain secure permission control enable" "0,1" repeat.end repeat 16. (list 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1A 0x1B 0x1C 0x1D 0x1E 0x1F )(list 0x340 0x374 0x3A8 0x3DC 0x410 0x444 0x478 0x4AC 0x4E0 0x514 0x548 0x57C 0x5B0 0x5E4 0x618 0x64C ) group.long ($2+0x2428)++0x3 line.long 0x0 "DOM_SEC_PER_$1,This register is only used for domain master to control secure access permission. When the domain master write this register. it only changes the secure permission for itself. When the domain master read this register. it gets permission.." bitfld.long 0x0 7. "DOM_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" newline bitfld.long 0x0 0. "DOM_SEC_EN,Domain secure permission control enable" "0,1" repeat.end repeat 16. (list 0x20 0x21 0x22 0x23 0x24 0x25 0x26 0x27 0x28 0x29 0x2A 0x2B 0x2C 0x2D 0x2E 0x2F )(list 0x680 0x6B4 0x6E8 0x71C 0x750 0x784 0x7B8 0x7EC 0x820 0x854 0x888 0x8BC 0x8F0 0x924 0x958 0x98C ) group.long ($2+0x2428)++0x3 line.long 0x0 "DOM_SEC_PER_$1,This register is only used for domain master to control secure access permission. When the domain master write this register. it only changes the secure permission for itself. When the domain master read this register. it gets permission.." bitfld.long 0x0 7. "DOM_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" newline bitfld.long 0x0 0. "DOM_SEC_EN,Domain secure permission control enable" "0,1" repeat.end repeat 16. (list 0x30 0x31 0x32 0x33 0x34 0x35 0x36 0x37 0x38 0x39 0x3A 0x3B 0x3C 0x3D 0x3E 0x3F )(list 0x9C0 0x9F4 0xA28 0xA5C 0xA90 0xAC4 0xAF8 0xB2C 0xB60 0xB94 0xBC8 0xBFC 0xC30 0xC64 0xC98 0xCCC ) group.long ($2+0x2428)++0x3 line.long 0x0 "DOM_SEC_PER_$1,This register is only used for domain master to control secure access permission. When the domain master write this register. it only changes the secure permission for itself. When the domain master read this register. it gets permission.." bitfld.long 0x0 7. "DOM_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" newline bitfld.long 0x0 0. "DOM_SEC_EN,Domain secure permission control enable" "0,1" repeat.end repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x34 0x68 0x9C 0xD0 0x104 0x138 0x16C 0x1A0 0x1D4 0x208 0x23C 0x270 0x2A4 0x2D8 0x30C ) group.long ($2+0x242C)++0x3 line.long 0x0 "DOM_PRI_PER_$1,This register is only used for domain master to control secure access permission. When the domain master write this register. it only changes the secure permission for itself. When the domain master read this register. it gets permission.." bitfld.long 0x0 7. "DOM_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" newline bitfld.long 0x0 0. "DOM_PRI_EN,Domain privileged permission control enable" "0,1" repeat.end repeat 16. (list 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1A 0x1B 0x1C 0x1D 0x1E 0x1F )(list 0x340 0x374 0x3A8 0x3DC 0x410 0x444 0x478 0x4AC 0x4E0 0x514 0x548 0x57C 0x5B0 0x5E4 0x618 0x64C ) group.long ($2+0x242C)++0x3 line.long 0x0 "DOM_PRI_PER_$1,This register is only used for domain master to control secure access permission. When the domain master write this register. it only changes the secure permission for itself. When the domain master read this register. it gets permission.." bitfld.long 0x0 7. "DOM_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" newline bitfld.long 0x0 0. "DOM_PRI_EN,Domain privileged permission control enable" "0,1" repeat.end repeat 16. (list 0x20 0x21 0x22 0x23 0x24 0x25 0x26 0x27 0x28 0x29 0x2A 0x2B 0x2C 0x2D 0x2E 0x2F )(list 0x680 0x6B4 0x6E8 0x71C 0x750 0x784 0x7B8 0x7EC 0x820 0x854 0x888 0x8BC 0x8F0 0x924 0x958 0x98C ) group.long ($2+0x242C)++0x3 line.long 0x0 "DOM_PRI_PER_$1,This register is only used for domain master to control secure access permission. When the domain master write this register. it only changes the secure permission for itself. When the domain master read this register. it gets permission.." bitfld.long 0x0 7. "DOM_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" newline bitfld.long 0x0 0. "DOM_PRI_EN,Domain privileged permission control enable" "0,1" repeat.end repeat 16. (list 0x30 0x31 0x32 0x33 0x34 0x35 0x36 0x37 0x38 0x39 0x3A 0x3B 0x3C 0x3D 0x3E 0x3F )(list 0x9C0 0x9F4 0xA28 0xA5C 0xA90 0xAC4 0xAF8 0xB2C 0xB60 0xB94 0xBC8 0xBFC 0xC30 0xC64 0xC98 0xCCC ) group.long ($2+0x242C)++0x3 line.long 0x0 "DOM_PRI_PER_$1,This register is only used for domain master to control secure access permission. When the domain master write this register. it only changes the secure permission for itself. When the domain master read this register. it gets permission.." bitfld.long 0x0 7. "DOM_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" newline bitfld.long 0x0 0. "DOM_PRI_EN,Domain privileged permission control enable" "0,1" repeat.end repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x34 0x68 0x9C 0xD0 0x104 0x138 0x16C 0x1A0 0x1D4 0x208 0x23C 0x270 0x2A4 0x2D8 0x30C ) group.long ($2+0x2430)++0x3 line.long 0x0 "DOM_ASSIGN_$1,Use to assign domain for accessing DOM_SEC_PER and DOM_PRI_PER register. Only resource manager. group manager and domain owner can access this register. For write. group manager must write its owen domain ID. otherwise write accessing will.." hexmask.long.byte 0x0 0.--3. 1. "DID,accessing DOM_SEC_PER and DOM_PRI_PER register" repeat.end repeat 16. (list 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1A 0x1B 0x1C 0x1D 0x1E 0x1F )(list 0x340 0x374 0x3A8 0x3DC 0x410 0x444 0x478 0x4AC 0x4E0 0x514 0x548 0x57C 0x5B0 0x5E4 0x618 0x64C ) group.long ($2+0x2430)++0x3 line.long 0x0 "DOM_ASSIGN_$1,Use to assign domain for accessing DOM_SEC_PER and DOM_PRI_PER register. Only resource manager. group manager and domain owner can access this register. For write. group manager must write its owen domain ID. otherwise write accessing will.." hexmask.long.byte 0x0 0.--3. 1. "DID,accessing DOM_SEC_PER and DOM_PRI_PER register" repeat.end repeat 16. (list 0x20 0x21 0x22 0x23 0x24 0x25 0x26 0x27 0x28 0x29 0x2A 0x2B 0x2C 0x2D 0x2E 0x2F )(list 0x680 0x6B4 0x6E8 0x71C 0x750 0x784 0x7B8 0x7EC 0x820 0x854 0x888 0x8BC 0x8F0 0x924 0x958 0x98C ) group.long ($2+0x2430)++0x3 line.long 0x0 "DOM_ASSIGN_$1,Use to assign domain for accessing DOM_SEC_PER and DOM_PRI_PER register. Only resource manager. group manager and domain owner can access this register. For write. group manager must write its owen domain ID. otherwise write accessing will.." hexmask.long.byte 0x0 0.--3. 1. "DID,accessing DOM_SEC_PER and DOM_PRI_PER register" repeat.end repeat 16. (list 0x30 0x31 0x32 0x33 0x34 0x35 0x36 0x37 0x38 0x39 0x3A 0x3B 0x3C 0x3D 0x3E 0x3F )(list 0x9C0 0x9F4 0xA28 0xA5C 0xA90 0xAC4 0xAF8 0xB2C 0xB60 0xB94 0xBC8 0xBFC 0xC30 0xC64 0xC98 0xCCC ) group.long ($2+0x2430)++0x3 line.long 0x0 "DOM_ASSIGN_$1,Use to assign domain for accessing DOM_SEC_PER and DOM_PRI_PER register. Only resource manager. group manager and domain owner can access this register. For write. group manager must write its owen domain ID. otherwise write accessing will.." hexmask.long.byte 0x0 0.--3. 1. "DID,accessing DOM_SEC_PER and DOM_PRI_PER register" repeat.end repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x38 0x70 0xA8 0xE0 0x118 0x150 0x188 0x1C0 0x1F8 0x230 0x268 0x2A0 0x2D8 0x310 0x348 ) group.long ($2+0x3100)++0x3 line.long 0x0 "RGN_DOM_$1,Assign domain for peripheral. It can be only configured by resource and group manager" bitfld.long 0x0 31. "LOCK,When this bit is set lock write for all the bits in the register." "0,1" bitfld.long 0x0 4. "SET,Set together with DID would change permission of this resource to following setting: 1) Domain access control enabled. 2) Read/Write allowed for the domain owner. 3) Read/Write not allowed for all the other domains. If this bit is not set only DID.." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Assign domain for peripheral" repeat.end repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x38 0x70 0xA8 0xE0 0x118 0x150 0x188 0x1C0 0x1F8 0x230 0x268 0x2A0 0x2D8 0x310 0x348 ) group.long ($2+0x3104)++0x3 line.long 0x0 "RGN_DOM_PER0_$1,Domain Permission Control. It can be only configured by resource manager and domain owner." bitfld.long 0x0 31. "DOM7_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 29.--30. "DOM7_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 28. "DOM7_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 27. "DOM6_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 25.--26. "DOM6_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" newline bitfld.long 0x0 24. "DOM6_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 23. "DOM5_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 21.--22. "DOM5_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 20. "DOM5_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 19. "DOM4_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" newline bitfld.long 0x0 17.--18. "DOM4_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM4_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 15. "DOM3_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 13.--14. "DOM3_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 12. "DOM3_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" newline bitfld.long 0x0 11. "DOM2_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 9.--10. "DOM2_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM2_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 7. "DOM1_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 5.--6. "DOM1_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" newline bitfld.long 0x0 4. "DOM1_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 3. "DOM0_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 1.--2. "DOM0_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM0_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" repeat.end repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x38 0x70 0xA8 0xE0 0x118 0x150 0x188 0x1C0 0x1F8 0x230 0x268 0x2A0 0x2D8 0x310 0x348 ) group.long ($2+0x3108)++0x3 line.long 0x0 "RGN_DOM_PER1_$1,Domain Permission Control. It can be only configured by resource manager and domain owner." bitfld.long 0x0 31. "DOM15_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 29.--30. "DOM15_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 28. "DOM15_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 27. "DOM14_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 25.--26. "DOM14_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" newline bitfld.long 0x0 24. "DOM14_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 23. "DOM13_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 21.--22. "DOM13_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 20. "DOM13_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 19. "DOM12_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" newline bitfld.long 0x0 17.--18. "DOM12_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM12_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 15. "DOM11_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 13.--14. "DOM11_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 12. "DOM11_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" newline bitfld.long 0x0 11. "DOM10_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 9.--10. "DOM10_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM10_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 7. "DOM9_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 5.--6. "DOM9_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" newline bitfld.long 0x0 4. "DOM9_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 3. "DOM8_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 1.--2. "DOM8_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM8_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" repeat.end repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x38 0x70 0xA8 0xE0 0x118 0x150 0x188 0x1C0 0x1F8 0x230 0x268 0x2A0 0x2D8 0x310 0x348 ) group.long ($2+0x310C)++0x3 line.long 0x0 "RGN_SEC_PER0_$1,This register is only used for resource manager to control secure access permission." bitfld.long 0x0 31. "DOM3_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM3_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM3_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM3_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM2_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM2_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM2_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM2_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM1_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM1_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM1_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM1_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM0_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM0_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM0_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM0_SEC_EN,Domain secure permission control enable" "0,1" repeat.end repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x38 0x70 0xA8 0xE0 0x118 0x150 0x188 0x1C0 0x1F8 0x230 0x268 0x2A0 0x2D8 0x310 0x348 ) group.long ($2+0x3110)++0x3 line.long 0x0 "RGN_SEC_PER1_$1,This register is only used for resource manager to control secure access permission." bitfld.long 0x0 31. "DOM7_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM7_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM7_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM7_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM6_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM6_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM6_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM6_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM5_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM5_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM5_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM5_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM4_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM4_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM4_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM4_SEC_EN,Domain secure permission control enable" "0,1" repeat.end repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x38 0x70 0xA8 0xE0 0x118 0x150 0x188 0x1C0 0x1F8 0x230 0x268 0x2A0 0x2D8 0x310 0x348 ) group.long ($2+0x3114)++0x3 line.long 0x0 "RGN_SEC_PER2_$1,This register is only used for resource manager to control secure access permission." bitfld.long 0x0 31. "DOM11_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM11_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM11_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM11_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM10_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM10_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM10_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM10_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM9_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM9_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM9_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM9_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM8_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM8_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM8_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM8_SEC_EN,Domain secure permission control enable" "0,1" repeat.end repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x38 0x70 0xA8 0xE0 0x118 0x150 0x188 0x1C0 0x1F8 0x230 0x268 0x2A0 0x2D8 0x310 0x348 ) group.long ($2+0x3118)++0x3 line.long 0x0 "RGN_SEC_PER3_$1,This register is only used for resource manager to control secure access permission." bitfld.long 0x0 31. "DOM15_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM15_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM15_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM15_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM14_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM14_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM14_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM14_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM13_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM13_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM13_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM13_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM12_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM12_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM12_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM12_SEC_EN,Domain secure permission control enable" "0,1" repeat.end repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x38 0x70 0xA8 0xE0 0x118 0x150 0x188 0x1C0 0x1F8 0x230 0x268 0x2A0 0x2D8 0x310 0x348 ) group.long ($2+0x311C)++0x3 line.long 0x0 "RGN_PRI_PER0_$1,This register is only used for resource manager to control privileged access permission." bitfld.long 0x0 31. "DOM3_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM3_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM3_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM3_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM2_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM2_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM2_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM2_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM1_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM1_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM1_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM1_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM0_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM0_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM0_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM0_PRI_EN,Domain privileged permission control enable" "0,1" repeat.end repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x38 0x70 0xA8 0xE0 0x118 0x150 0x188 0x1C0 0x1F8 0x230 0x268 0x2A0 0x2D8 0x310 0x348 ) group.long ($2+0x3120)++0x3 line.long 0x0 "RGN_PRI_PER1_$1,This register is only used for resource manager to control privileged access permission." bitfld.long 0x0 31. "DOM7_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM7_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM7_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM7_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM6_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM6_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM6_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM6_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM5_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM5_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM5_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM5_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM4_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM4_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM4_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM4_PRI_EN,Domain privileged permission control enable" "0,1" repeat.end repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x38 0x70 0xA8 0xE0 0x118 0x150 0x188 0x1C0 0x1F8 0x230 0x268 0x2A0 0x2D8 0x310 0x348 ) group.long ($2+0x3124)++0x3 line.long 0x0 "RGN_PRI_PER2_$1,This register is only used for resource manager to control privileged access permission." bitfld.long 0x0 31. "DOM11_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM11_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM11_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM11_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM10_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM10_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM10_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM10_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM9_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM9_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM9_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM9_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM8_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM8_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM8_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM8_PRI_EN,Domain privileged permission control enable" "0,1" repeat.end repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x38 0x70 0xA8 0xE0 0x118 0x150 0x188 0x1C0 0x1F8 0x230 0x268 0x2A0 0x2D8 0x310 0x348 ) group.long ($2+0x3128)++0x3 line.long 0x0 "RGN_PRI_PER3_$1,This register is only used for resource manager to control privileged access permission." bitfld.long 0x0 31. "DOM15_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM15_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM15_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM15_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM14_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM14_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM14_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM14_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM13_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM13_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM13_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM13_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM12_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM12_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM12_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM12_PRI_EN,Domain privileged permission control enable" "0,1" repeat.end repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x38 0x70 0xA8 0xE0 0x118 0x150 0x188 0x1C0 0x1F8 0x230 0x268 0x2A0 0x2D8 0x310 0x348 ) group.long ($2+0x312C)++0x3 line.long 0x0 "RGN_DOM_SEC_PER_$1,This register is only used for domain master to control secure access permission. When the domain master write this register. it only changes the secure permission for itself. When the domain master read this register. it gets.." bitfld.long 0x0 7. "DOM_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" newline bitfld.long 0x0 0. "DOM_SEC_EN,Domain secure permission control enable" "0,1" repeat.end repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x38 0x70 0xA8 0xE0 0x118 0x150 0x188 0x1C0 0x1F8 0x230 0x268 0x2A0 0x2D8 0x310 0x348 ) group.long ($2+0x3130)++0x3 line.long 0x0 "RGN_DOM_PRI_PER_$1,This register is only used for domain master to control secure access permission. When the domain master write this register. it only changes the secure permission for itself. When the domain master read this register. it gets.." bitfld.long 0x0 7. "DOM_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" newline bitfld.long 0x0 0. "DOM_PRI_EN,Domain privileged permission control enable" "0,1" repeat.end repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x38 0x70 0xA8 0xE0 0x118 0x150 0x188 0x1C0 0x1F8 0x230 0x268 0x2A0 0x2D8 0x310 0x348 ) group.long ($2+0x3134)++0x3 line.long 0x0 "RGN_DOM_ASSIGN_$1,Use to assign domain for accessing DOM_SEC_PER and DOM_PRI_PER register. Only resource manager. group manager and domain owner can access this register. For write. group manager must write its owen domain ID. otherwise write accessing.." hexmask.long.byte 0x0 0.--3. 1. "DID,accessing DOM_SEC_PER and DOM_PRI_PER register" repeat.end tree.end tree "RPC_AP_GLOBAL" base ad:0xF8FFE000 repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x4 0x8 0xC 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C ) group.long ($2)++0x3 line.long 0x0 "REGG0_DOM_$1,Assign domain for CKGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1A 0x1B 0x1C 0x1D 0x1E 0x1F )(list 0x40 0x44 0x48 0x4C 0x50 0x54 0x58 0x5C 0x60 0x64 0x68 0x6C 0x70 0x74 0x78 0x7C ) group.long ($2)++0x3 line.long 0x0 "REGG0_DOM_$1,Assign domain for CKGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x20 0x21 0x22 0x23 0x24 0x25 0x26 0x27 0x28 0x29 0x2A 0x2B 0x2C 0x2D 0x2E 0x2F )(list 0x80 0x84 0x88 0x8C 0x90 0x94 0x98 0x9C 0xA0 0xA4 0xA8 0xAC 0xB0 0xB4 0xB8 0xBC ) group.long ($2)++0x3 line.long 0x0 "REGG0_DOM_$1,Assign domain for CKGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x30 0x31 0x32 0x33 0x34 0x35 0x36 0x37 0x38 0x39 0x3A 0x3B 0x3C 0x3D 0x3E 0x3F )(list 0xC0 0xC4 0xC8 0xCC 0xD0 0xD4 0xD8 0xDC 0xE0 0xE4 0xE8 0xEC 0xF0 0xF4 0xF8 0xFC ) group.long ($2)++0x3 line.long 0x0 "REGG0_DOM_$1,Assign domain for CKGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x40 0x41 0x42 0x43 0x44 0x45 0x46 0x47 0x48 0x49 0x4A 0x4B 0x4C 0x4D 0x4E 0x4F )(list 0x100 0x104 0x108 0x10C 0x110 0x114 0x118 0x11C 0x120 0x124 0x128 0x12C 0x130 0x134 0x138 0x13C ) group.long ($2)++0x3 line.long 0x0 "REGG0_DOM_$1,Assign domain for CKGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x50 0x51 0x52 0x53 0x54 0x55 0x56 0x57 0x58 0x59 0x5A 0x5B 0x5C 0x5D 0x5E 0x5F )(list 0x140 0x144 0x148 0x14C 0x150 0x154 0x158 0x15C 0x160 0x164 0x168 0x16C 0x170 0x174 0x178 0x17C ) group.long ($2)++0x3 line.long 0x0 "REGG0_DOM_$1,Assign domain for CKGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x60 0x61 0x62 0x63 0x64 0x65 0x66 0x67 0x68 0x69 0x6A 0x6B 0x6C 0x6D 0x6E 0x6F )(list 0x180 0x184 0x188 0x18C 0x190 0x194 0x198 0x19C 0x1A0 0x1A4 0x1A8 0x1AC 0x1B0 0x1B4 0x1B8 0x1BC ) group.long ($2)++0x3 line.long 0x0 "REGG0_DOM_$1,Assign domain for CKGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x70 0x71 0x72 0x73 0x74 0x75 0x76 0x77 0x78 0x79 0x7A 0x7B 0x7C 0x7D 0x7E 0x7F )(list 0x1C0 0x1C4 0x1C8 0x1CC 0x1D0 0x1D4 0x1D8 0x1DC 0x1E0 0x1E4 0x1E8 0x1EC 0x1F0 0x1F4 0x1F8 0x1FC ) group.long ($2)++0x3 line.long 0x0 "REGG0_DOM_$1,Assign domain for CKGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x80 0x81 0x82 0x83 0x84 0x85 0x86 0x87 0x88 0x89 0x8A 0x8B 0x8C 0x8D 0x8E 0x8F )(list 0x200 0x204 0x208 0x20C 0x210 0x214 0x218 0x21C 0x220 0x224 0x228 0x22C 0x230 0x234 0x238 0x23C ) group.long ($2)++0x3 line.long 0x0 "REGG0_DOM_$1,Assign domain for CKGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x90 0x91 0x92 0x93 0x94 0x95 0x96 0x97 0x98 0x99 0x9A 0x9B 0x9C 0x9D 0x9E 0x9F )(list 0x240 0x244 0x248 0x24C 0x250 0x254 0x258 0x25C 0x260 0x264 0x268 0x26C 0x270 0x274 0x278 0x27C ) group.long ($2)++0x3 line.long 0x0 "REGG0_DOM_$1,Assign domain for CKGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xA0 0xA1 0xA2 0xA3 0xA4 0xA5 0xA6 0xA7 0xA8 0xA9 0xAA 0xAB 0xAC 0xAD 0xAE 0xAF )(list 0x280 0x284 0x288 0x28C 0x290 0x294 0x298 0x29C 0x2A0 0x2A4 0x2A8 0x2AC 0x2B0 0x2B4 0x2B8 0x2BC ) group.long ($2)++0x3 line.long 0x0 "REGG0_DOM_$1,Assign domain for CKGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xB0 0xB1 0xB2 0xB3 0xB4 0xB5 0xB6 0xB7 0xB8 0xB9 0xBA 0xBB 0xBC 0xBD 0xBE 0xBF )(list 0x2C0 0x2C4 0x2C8 0x2CC 0x2D0 0x2D4 0x2D8 0x2DC 0x2E0 0x2E4 0x2E8 0x2EC 0x2F0 0x2F4 0x2F8 0x2FC ) group.long ($2)++0x3 line.long 0x0 "REGG0_DOM_$1,Assign domain for CKGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xC0 0xC1 0xC2 0xC3 0xC4 0xC5 0xC6 0xC7 0xC8 0xC9 0xCA 0xCB 0xCC 0xCD 0xCE 0xCF )(list 0x300 0x304 0x308 0x30C 0x310 0x314 0x318 0x31C 0x320 0x324 0x328 0x32C 0x330 0x334 0x338 0x33C ) group.long ($2)++0x3 line.long 0x0 "REGG0_DOM_$1,Assign domain for CKGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xD0 0xD1 0xD2 0xD3 0xD4 0xD5 0xD6 0xD7 0xD8 0xD9 0xDA 0xDB 0xDC 0xDD 0xDE 0xDF )(list 0x340 0x344 0x348 0x34C 0x350 0x354 0x358 0x35C 0x360 0x364 0x368 0x36C 0x370 0x374 0x378 0x37C ) group.long ($2)++0x3 line.long 0x0 "REGG0_DOM_$1,Assign domain for CKGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xE0 0xE1 0xE2 0xE3 0xE4 0xE5 0xE6 0xE7 0xE8 0xE9 0xEA 0xEB 0xEC 0xED 0xEE 0xEF )(list 0x380 0x384 0x388 0x38C 0x390 0x394 0x398 0x39C 0x3A0 0x3A4 0x3A8 0x3AC 0x3B0 0x3B4 0x3B8 0x3BC ) group.long ($2)++0x3 line.long 0x0 "REGG0_DOM_$1,Assign domain for CKGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xF0 0xF1 0xF2 0xF3 0xF4 0xF5 0xF6 0xF7 0xF8 0xF9 0xFA 0xFB 0xFC 0xFD 0xFE 0xFF )(list 0x3C0 0x3C4 0x3C8 0x3CC 0x3D0 0x3D4 0x3D8 0x3DC 0x3E0 0x3E4 0x3E8 0x3EC 0x3F0 0x3F4 0x3F8 0x3FC ) group.long ($2)++0x3 line.long 0x0 "REGG0_DOM_$1,Assign domain for CKGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x4 0x8 0xC 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C ) group.long ($2+0x400)++0x3 line.long 0x0 "REGG1_DOM_$1,Assign domain for CKGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1A 0x1B 0x1C 0x1D 0x1E 0x1F )(list 0x40 0x44 0x48 0x4C 0x50 0x54 0x58 0x5C 0x60 0x64 0x68 0x6C 0x70 0x74 0x78 0x7C ) group.long ($2+0x400)++0x3 line.long 0x0 "REGG1_DOM_$1,Assign domain for CKGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x20 0x21 0x22 0x23 0x24 0x25 0x26 0x27 0x28 0x29 0x2A 0x2B 0x2C 0x2D 0x2E 0x2F )(list 0x80 0x84 0x88 0x8C 0x90 0x94 0x98 0x9C 0xA0 0xA4 0xA8 0xAC 0xB0 0xB4 0xB8 0xBC ) group.long ($2+0x400)++0x3 line.long 0x0 "REGG1_DOM_$1,Assign domain for CKGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x30 0x31 0x32 0x33 0x34 0x35 0x36 0x37 0x38 0x39 0x3A 0x3B 0x3C 0x3D 0x3E 0x3F )(list 0xC0 0xC4 0xC8 0xCC 0xD0 0xD4 0xD8 0xDC 0xE0 0xE4 0xE8 0xEC 0xF0 0xF4 0xF8 0xFC ) group.long ($2+0x400)++0x3 line.long 0x0 "REGG1_DOM_$1,Assign domain for CKGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x40 0x41 0x42 0x43 0x44 0x45 0x46 0x47 0x48 0x49 0x4A 0x4B 0x4C 0x4D 0x4E 0x4F )(list 0x100 0x104 0x108 0x10C 0x110 0x114 0x118 0x11C 0x120 0x124 0x128 0x12C 0x130 0x134 0x138 0x13C ) group.long ($2+0x400)++0x3 line.long 0x0 "REGG1_DOM_$1,Assign domain for CKGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x50 0x51 0x52 0x53 0x54 0x55 0x56 0x57 0x58 0x59 0x5A 0x5B 0x5C 0x5D 0x5E 0x5F )(list 0x140 0x144 0x148 0x14C 0x150 0x154 0x158 0x15C 0x160 0x164 0x168 0x16C 0x170 0x174 0x178 0x17C ) group.long ($2+0x400)++0x3 line.long 0x0 "REGG1_DOM_$1,Assign domain for CKGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x60 0x61 0x62 0x63 0x64 0x65 0x66 0x67 0x68 0x69 0x6A 0x6B 0x6C 0x6D 0x6E 0x6F )(list 0x180 0x184 0x188 0x18C 0x190 0x194 0x198 0x19C 0x1A0 0x1A4 0x1A8 0x1AC 0x1B0 0x1B4 0x1B8 0x1BC ) group.long ($2+0x400)++0x3 line.long 0x0 "REGG1_DOM_$1,Assign domain for CKGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x70 0x71 0x72 0x73 0x74 0x75 0x76 0x77 0x78 0x79 0x7A 0x7B 0x7C 0x7D 0x7E 0x7F )(list 0x1C0 0x1C4 0x1C8 0x1CC 0x1D0 0x1D4 0x1D8 0x1DC 0x1E0 0x1E4 0x1E8 0x1EC 0x1F0 0x1F4 0x1F8 0x1FC ) group.long ($2+0x400)++0x3 line.long 0x0 "REGG1_DOM_$1,Assign domain for CKGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x80 0x81 0x82 0x83 0x84 0x85 0x86 0x87 0x88 0x89 0x8A 0x8B 0x8C 0x8D 0x8E 0x8F )(list 0x200 0x204 0x208 0x20C 0x210 0x214 0x218 0x21C 0x220 0x224 0x228 0x22C 0x230 0x234 0x238 0x23C ) group.long ($2+0x400)++0x3 line.long 0x0 "REGG1_DOM_$1,Assign domain for CKGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x90 0x91 0x92 0x93 0x94 0x95 0x96 0x97 0x98 0x99 0x9A 0x9B 0x9C 0x9D 0x9E 0x9F )(list 0x240 0x244 0x248 0x24C 0x250 0x254 0x258 0x25C 0x260 0x264 0x268 0x26C 0x270 0x274 0x278 0x27C ) group.long ($2+0x400)++0x3 line.long 0x0 "REGG1_DOM_$1,Assign domain for CKGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xA0 0xA1 0xA2 0xA3 0xA4 0xA5 0xA6 0xA7 0xA8 0xA9 0xAA 0xAB 0xAC 0xAD 0xAE 0xAF )(list 0x280 0x284 0x288 0x28C 0x290 0x294 0x298 0x29C 0x2A0 0x2A4 0x2A8 0x2AC 0x2B0 0x2B4 0x2B8 0x2BC ) group.long ($2+0x400)++0x3 line.long 0x0 "REGG1_DOM_$1,Assign domain for CKGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xB0 0xB1 0xB2 0xB3 0xB4 0xB5 0xB6 0xB7 0xB8 0xB9 0xBA 0xBB 0xBC 0xBD 0xBE 0xBF )(list 0x2C0 0x2C4 0x2C8 0x2CC 0x2D0 0x2D4 0x2D8 0x2DC 0x2E0 0x2E4 0x2E8 0x2EC 0x2F0 0x2F4 0x2F8 0x2FC ) group.long ($2+0x400)++0x3 line.long 0x0 "REGG1_DOM_$1,Assign domain for CKGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xC0 0xC1 0xC2 0xC3 0xC4 0xC5 0xC6 0xC7 0xC8 0xC9 0xCA 0xCB 0xCC 0xCD 0xCE 0xCF )(list 0x300 0x304 0x308 0x30C 0x310 0x314 0x318 0x31C 0x320 0x324 0x328 0x32C 0x330 0x334 0x338 0x33C ) group.long ($2+0x400)++0x3 line.long 0x0 "REGG1_DOM_$1,Assign domain for CKGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xD0 0xD1 0xD2 0xD3 0xD4 0xD5 0xD6 0xD7 0xD8 0xD9 0xDA 0xDB 0xDC 0xDD 0xDE 0xDF )(list 0x340 0x344 0x348 0x34C 0x350 0x354 0x358 0x35C 0x360 0x364 0x368 0x36C 0x370 0x374 0x378 0x37C ) group.long ($2+0x400)++0x3 line.long 0x0 "REGG1_DOM_$1,Assign domain for CKGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xE0 0xE1 0xE2 0xE3 0xE4 0xE5 0xE6 0xE7 0xE8 0xE9 0xEA 0xEB 0xEC 0xED 0xEE 0xEF )(list 0x380 0x384 0x388 0x38C 0x390 0x394 0x398 0x39C 0x3A0 0x3A4 0x3A8 0x3AC 0x3B0 0x3B4 0x3B8 0x3BC ) group.long ($2+0x400)++0x3 line.long 0x0 "REGG1_DOM_$1,Assign domain for CKGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xF0 0xF1 0xF2 0xF3 0xF4 0xF5 0xF6 0xF7 0xF8 0xF9 0xFA 0xFB 0xFC 0xFD 0xFE 0xFF )(list 0x3C0 0x3C4 0x3C8 0x3CC 0x3D0 0x3D4 0x3D8 0x3DC 0x3E0 0x3E4 0x3E8 0x3EC 0x3F0 0x3F4 0x3F8 0x3FC ) group.long ($2+0x400)++0x3 line.long 0x0 "REGG1_DOM_$1,Assign domain for CKGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x4 0x8 0xC 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C ) group.long ($2+0x800)++0x3 line.long 0x0 "REGG2_DOM_$1,Assign domain for SCR registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1A 0x1B 0x1C 0x1D 0x1E 0x1F )(list 0x40 0x44 0x48 0x4C 0x50 0x54 0x58 0x5C 0x60 0x64 0x68 0x6C 0x70 0x74 0x78 0x7C ) group.long ($2+0x800)++0x3 line.long 0x0 "REGG2_DOM_$1,Assign domain for SCR registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x20 0x21 0x22 0x23 0x24 0x25 0x26 0x27 0x28 0x29 0x2A 0x2B 0x2C 0x2D 0x2E 0x2F )(list 0x80 0x84 0x88 0x8C 0x90 0x94 0x98 0x9C 0xA0 0xA4 0xA8 0xAC 0xB0 0xB4 0xB8 0xBC ) group.long ($2+0x800)++0x3 line.long 0x0 "REGG2_DOM_$1,Assign domain for SCR registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x30 0x31 0x32 0x33 0x34 0x35 0x36 0x37 0x38 0x39 0x3A 0x3B 0x3C 0x3D 0x3E 0x3F )(list 0xC0 0xC4 0xC8 0xCC 0xD0 0xD4 0xD8 0xDC 0xE0 0xE4 0xE8 0xEC 0xF0 0xF4 0xF8 0xFC ) group.long ($2+0x800)++0x3 line.long 0x0 "REGG2_DOM_$1,Assign domain for SCR registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x40 0x41 0x42 0x43 0x44 0x45 0x46 0x47 0x48 0x49 0x4A 0x4B 0x4C 0x4D 0x4E 0x4F )(list 0x100 0x104 0x108 0x10C 0x110 0x114 0x118 0x11C 0x120 0x124 0x128 0x12C 0x130 0x134 0x138 0x13C ) group.long ($2+0x800)++0x3 line.long 0x0 "REGG2_DOM_$1,Assign domain for SCR registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x50 0x51 0x52 0x53 0x54 0x55 0x56 0x57 0x58 0x59 0x5A 0x5B 0x5C 0x5D 0x5E 0x5F )(list 0x140 0x144 0x148 0x14C 0x150 0x154 0x158 0x15C 0x160 0x164 0x168 0x16C 0x170 0x174 0x178 0x17C ) group.long ($2+0x800)++0x3 line.long 0x0 "REGG2_DOM_$1,Assign domain for SCR registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x60 0x61 0x62 0x63 0x64 0x65 0x66 0x67 0x68 0x69 0x6A 0x6B 0x6C 0x6D 0x6E 0x6F )(list 0x180 0x184 0x188 0x18C 0x190 0x194 0x198 0x19C 0x1A0 0x1A4 0x1A8 0x1AC 0x1B0 0x1B4 0x1B8 0x1BC ) group.long ($2+0x800)++0x3 line.long 0x0 "REGG2_DOM_$1,Assign domain for SCR registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x70 0x71 0x72 0x73 0x74 0x75 0x76 0x77 0x78 0x79 0x7A 0x7B 0x7C 0x7D 0x7E 0x7F )(list 0x1C0 0x1C4 0x1C8 0x1CC 0x1D0 0x1D4 0x1D8 0x1DC 0x1E0 0x1E4 0x1E8 0x1EC 0x1F0 0x1F4 0x1F8 0x1FC ) group.long ($2+0x800)++0x3 line.long 0x0 "REGG2_DOM_$1,Assign domain for SCR registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x80 0x81 0x82 0x83 0x84 0x85 0x86 0x87 0x88 0x89 0x8A 0x8B 0x8C 0x8D 0x8E 0x8F )(list 0x200 0x204 0x208 0x20C 0x210 0x214 0x218 0x21C 0x220 0x224 0x228 0x22C 0x230 0x234 0x238 0x23C ) group.long ($2+0x800)++0x3 line.long 0x0 "REGG2_DOM_$1,Assign domain for SCR registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x90 0x91 0x92 0x93 0x94 0x95 0x96 0x97 0x98 0x99 0x9A 0x9B 0x9C 0x9D 0x9E 0x9F )(list 0x240 0x244 0x248 0x24C 0x250 0x254 0x258 0x25C 0x260 0x264 0x268 0x26C 0x270 0x274 0x278 0x27C ) group.long ($2+0x800)++0x3 line.long 0x0 "REGG2_DOM_$1,Assign domain for SCR registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xA0 0xA1 0xA2 0xA3 0xA4 0xA5 0xA6 0xA7 0xA8 0xA9 0xAA 0xAB 0xAC 0xAD 0xAE 0xAF )(list 0x280 0x284 0x288 0x28C 0x290 0x294 0x298 0x29C 0x2A0 0x2A4 0x2A8 0x2AC 0x2B0 0x2B4 0x2B8 0x2BC ) group.long ($2+0x800)++0x3 line.long 0x0 "REGG2_DOM_$1,Assign domain for SCR registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xB0 0xB1 0xB2 0xB3 0xB4 0xB5 0xB6 0xB7 0xB8 0xB9 0xBA 0xBB 0xBC 0xBD 0xBE 0xBF )(list 0x2C0 0x2C4 0x2C8 0x2CC 0x2D0 0x2D4 0x2D8 0x2DC 0x2E0 0x2E4 0x2E8 0x2EC 0x2F0 0x2F4 0x2F8 0x2FC ) group.long ($2+0x800)++0x3 line.long 0x0 "REGG2_DOM_$1,Assign domain for SCR registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xC0 0xC1 0xC2 0xC3 0xC4 0xC5 0xC6 0xC7 0xC8 0xC9 0xCA 0xCB 0xCC 0xCD 0xCE 0xCF )(list 0x300 0x304 0x308 0x30C 0x310 0x314 0x318 0x31C 0x320 0x324 0x328 0x32C 0x330 0x334 0x338 0x33C ) group.long ($2+0x800)++0x3 line.long 0x0 "REGG2_DOM_$1,Assign domain for SCR registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xD0 0xD1 0xD2 0xD3 0xD4 0xD5 0xD6 0xD7 0xD8 0xD9 0xDA 0xDB 0xDC 0xDD 0xDE 0xDF )(list 0x340 0x344 0x348 0x34C 0x350 0x354 0x358 0x35C 0x360 0x364 0x368 0x36C 0x370 0x374 0x378 0x37C ) group.long ($2+0x800)++0x3 line.long 0x0 "REGG2_DOM_$1,Assign domain for SCR registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xE0 0xE1 0xE2 0xE3 0xE4 0xE5 0xE6 0xE7 0xE8 0xE9 0xEA 0xEB 0xEC 0xED 0xEE 0xEF )(list 0x380 0x384 0x388 0x38C 0x390 0x394 0x398 0x39C 0x3A0 0x3A4 0x3A8 0x3AC 0x3B0 0x3B4 0x3B8 0x3BC ) group.long ($2+0x800)++0x3 line.long 0x0 "REGG2_DOM_$1,Assign domain for SCR registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xF0 0xF1 0xF2 0xF3 0xF4 0xF5 0xF6 0xF7 0xF8 0xF9 0xFA 0xFB 0xFC 0xFD 0xFE 0xFF )(list 0x3C0 0x3C4 0x3C8 0x3CC 0x3D0 0x3D4 0x3D8 0x3DC 0x3E0 0x3E4 0x3E8 0x3EC 0x3F0 0x3F4 0x3F8 0x3FC ) group.long ($2+0x800)++0x3 line.long 0x0 "REGG2_DOM_$1,Assign domain for SCR registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x4 0x8 0xC 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C ) group.long ($2+0xC00)++0x3 line.long 0x0 "REGG3_DOM_$1,Assign domain for SCR registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1A 0x1B 0x1C 0x1D 0x1E 0x1F )(list 0x40 0x44 0x48 0x4C 0x50 0x54 0x58 0x5C 0x60 0x64 0x68 0x6C 0x70 0x74 0x78 0x7C ) group.long ($2+0xC00)++0x3 line.long 0x0 "REGG3_DOM_$1,Assign domain for SCR registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x20 0x21 0x22 0x23 0x24 0x25 0x26 0x27 0x28 0x29 0x2A 0x2B 0x2C 0x2D 0x2E 0x2F )(list 0x80 0x84 0x88 0x8C 0x90 0x94 0x98 0x9C 0xA0 0xA4 0xA8 0xAC 0xB0 0xB4 0xB8 0xBC ) group.long ($2+0xC00)++0x3 line.long 0x0 "REGG3_DOM_$1,Assign domain for SCR registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x30 0x31 0x32 0x33 0x34 0x35 0x36 0x37 0x38 0x39 0x3A 0x3B 0x3C 0x3D 0x3E 0x3F )(list 0xC0 0xC4 0xC8 0xCC 0xD0 0xD4 0xD8 0xDC 0xE0 0xE4 0xE8 0xEC 0xF0 0xF4 0xF8 0xFC ) group.long ($2+0xC00)++0x3 line.long 0x0 "REGG3_DOM_$1,Assign domain for SCR registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x40 0x41 0x42 0x43 0x44 0x45 0x46 0x47 0x48 0x49 0x4A 0x4B 0x4C 0x4D 0x4E 0x4F )(list 0x100 0x104 0x108 0x10C 0x110 0x114 0x118 0x11C 0x120 0x124 0x128 0x12C 0x130 0x134 0x138 0x13C ) group.long ($2+0xC00)++0x3 line.long 0x0 "REGG3_DOM_$1,Assign domain for SCR registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x50 0x51 0x52 0x53 0x54 0x55 0x56 0x57 0x58 0x59 0x5A 0x5B 0x5C 0x5D 0x5E 0x5F )(list 0x140 0x144 0x148 0x14C 0x150 0x154 0x158 0x15C 0x160 0x164 0x168 0x16C 0x170 0x174 0x178 0x17C ) group.long ($2+0xC00)++0x3 line.long 0x0 "REGG3_DOM_$1,Assign domain for SCR registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x60 0x61 0x62 0x63 0x64 0x65 0x66 0x67 0x68 0x69 0x6A 0x6B 0x6C 0x6D 0x6E 0x6F )(list 0x180 0x184 0x188 0x18C 0x190 0x194 0x198 0x19C 0x1A0 0x1A4 0x1A8 0x1AC 0x1B0 0x1B4 0x1B8 0x1BC ) group.long ($2+0xC00)++0x3 line.long 0x0 "REGG3_DOM_$1,Assign domain for SCR registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x70 0x71 0x72 0x73 0x74 0x75 0x76 0x77 0x78 0x79 0x7A 0x7B 0x7C 0x7D 0x7E 0x7F )(list 0x1C0 0x1C4 0x1C8 0x1CC 0x1D0 0x1D4 0x1D8 0x1DC 0x1E0 0x1E4 0x1E8 0x1EC 0x1F0 0x1F4 0x1F8 0x1FC ) group.long ($2+0xC00)++0x3 line.long 0x0 "REGG3_DOM_$1,Assign domain for SCR registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x80 0x81 0x82 0x83 0x84 0x85 0x86 0x87 0x88 0x89 0x8A 0x8B 0x8C 0x8D 0x8E 0x8F )(list 0x200 0x204 0x208 0x20C 0x210 0x214 0x218 0x21C 0x220 0x224 0x228 0x22C 0x230 0x234 0x238 0x23C ) group.long ($2+0xC00)++0x3 line.long 0x0 "REGG3_DOM_$1,Assign domain for SCR registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x90 0x91 0x92 0x93 0x94 0x95 0x96 0x97 0x98 0x99 0x9A 0x9B 0x9C 0x9D 0x9E 0x9F )(list 0x240 0x244 0x248 0x24C 0x250 0x254 0x258 0x25C 0x260 0x264 0x268 0x26C 0x270 0x274 0x278 0x27C ) group.long ($2+0xC00)++0x3 line.long 0x0 "REGG3_DOM_$1,Assign domain for SCR registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xA0 0xA1 0xA2 0xA3 0xA4 0xA5 0xA6 0xA7 0xA8 0xA9 0xAA 0xAB 0xAC 0xAD 0xAE 0xAF )(list 0x280 0x284 0x288 0x28C 0x290 0x294 0x298 0x29C 0x2A0 0x2A4 0x2A8 0x2AC 0x2B0 0x2B4 0x2B8 0x2BC ) group.long ($2+0xC00)++0x3 line.long 0x0 "REGG3_DOM_$1,Assign domain for SCR registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xB0 0xB1 0xB2 0xB3 0xB4 0xB5 0xB6 0xB7 0xB8 0xB9 0xBA 0xBB 0xBC 0xBD 0xBE 0xBF )(list 0x2C0 0x2C4 0x2C8 0x2CC 0x2D0 0x2D4 0x2D8 0x2DC 0x2E0 0x2E4 0x2E8 0x2EC 0x2F0 0x2F4 0x2F8 0x2FC ) group.long ($2+0xC00)++0x3 line.long 0x0 "REGG3_DOM_$1,Assign domain for SCR registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xC0 0xC1 0xC2 0xC3 0xC4 0xC5 0xC6 0xC7 0xC8 0xC9 0xCA 0xCB 0xCC 0xCD 0xCE 0xCF )(list 0x300 0x304 0x308 0x30C 0x310 0x314 0x318 0x31C 0x320 0x324 0x328 0x32C 0x330 0x334 0x338 0x33C ) group.long ($2+0xC00)++0x3 line.long 0x0 "REGG3_DOM_$1,Assign domain for SCR registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xD0 0xD1 0xD2 0xD3 0xD4 0xD5 0xD6 0xD7 0xD8 0xD9 0xDA 0xDB 0xDC 0xDD 0xDE 0xDF )(list 0x340 0x344 0x348 0x34C 0x350 0x354 0x358 0x35C 0x360 0x364 0x368 0x36C 0x370 0x374 0x378 0x37C ) group.long ($2+0xC00)++0x3 line.long 0x0 "REGG3_DOM_$1,Assign domain for SCR registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xE0 0xE1 0xE2 0xE3 0xE4 0xE5 0xE6 0xE7 0xE8 0xE9 0xEA 0xEB 0xEC 0xED 0xEE 0xEF )(list 0x380 0x384 0x388 0x38C 0x390 0x394 0x398 0x39C 0x3A0 0x3A4 0x3A8 0x3AC 0x3B0 0x3B4 0x3B8 0x3BC ) group.long ($2+0xC00)++0x3 line.long 0x0 "REGG3_DOM_$1,Assign domain for SCR registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xF0 0xF1 0xF2 0xF3 0xF4 0xF5 0xF6 0xF7 0xF8 0xF9 0xFA 0xFB 0xFC 0xFD 0xFE 0xFF )(list 0x3C0 0x3C4 0x3C8 0x3CC 0x3D0 0x3D4 0x3D8 0x3DC 0x3E0 0x3E4 0x3E8 0x3EC 0x3F0 0x3F4 0x3F8 0x3FC ) group.long ($2+0xC00)++0x3 line.long 0x0 "REGG3_DOM_$1,Assign domain for SCR registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x4 0x8 0xC 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C ) group.long ($2+0x1000)++0x3 line.long 0x0 "REGG4_DOM_$1,Assign domain for RSTGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1A 0x1B 0x1C 0x1D 0x1E 0x1F )(list 0x40 0x44 0x48 0x4C 0x50 0x54 0x58 0x5C 0x60 0x64 0x68 0x6C 0x70 0x74 0x78 0x7C ) group.long ($2+0x1000)++0x3 line.long 0x0 "REGG4_DOM_$1,Assign domain for RSTGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x20 0x21 0x22 0x23 0x24 0x25 0x26 0x27 0x28 0x29 0x2A 0x2B 0x2C 0x2D 0x2E 0x2F )(list 0x80 0x84 0x88 0x8C 0x90 0x94 0x98 0x9C 0xA0 0xA4 0xA8 0xAC 0xB0 0xB4 0xB8 0xBC ) group.long ($2+0x1000)++0x3 line.long 0x0 "REGG4_DOM_$1,Assign domain for RSTGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x30 0x31 0x32 0x33 0x34 0x35 0x36 0x37 0x38 0x39 0x3A 0x3B 0x3C 0x3D 0x3E 0x3F )(list 0xC0 0xC4 0xC8 0xCC 0xD0 0xD4 0xD8 0xDC 0xE0 0xE4 0xE8 0xEC 0xF0 0xF4 0xF8 0xFC ) group.long ($2+0x1000)++0x3 line.long 0x0 "REGG4_DOM_$1,Assign domain for RSTGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x40 0x41 0x42 0x43 0x44 0x45 0x46 0x47 0x48 0x49 0x4A 0x4B 0x4C 0x4D 0x4E 0x4F )(list 0x100 0x104 0x108 0x10C 0x110 0x114 0x118 0x11C 0x120 0x124 0x128 0x12C 0x130 0x134 0x138 0x13C ) group.long ($2+0x1000)++0x3 line.long 0x0 "REGG4_DOM_$1,Assign domain for RSTGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x50 0x51 0x52 0x53 0x54 0x55 0x56 0x57 0x58 0x59 0x5A 0x5B 0x5C 0x5D 0x5E 0x5F )(list 0x140 0x144 0x148 0x14C 0x150 0x154 0x158 0x15C 0x160 0x164 0x168 0x16C 0x170 0x174 0x178 0x17C ) group.long ($2+0x1000)++0x3 line.long 0x0 "REGG4_DOM_$1,Assign domain for RSTGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x60 0x61 0x62 0x63 0x64 0x65 0x66 0x67 0x68 0x69 0x6A 0x6B 0x6C 0x6D 0x6E 0x6F )(list 0x180 0x184 0x188 0x18C 0x190 0x194 0x198 0x19C 0x1A0 0x1A4 0x1A8 0x1AC 0x1B0 0x1B4 0x1B8 0x1BC ) group.long ($2+0x1000)++0x3 line.long 0x0 "REGG4_DOM_$1,Assign domain for RSTGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x70 0x71 0x72 0x73 0x74 0x75 0x76 0x77 0x78 0x79 0x7A 0x7B 0x7C 0x7D 0x7E 0x7F )(list 0x1C0 0x1C4 0x1C8 0x1CC 0x1D0 0x1D4 0x1D8 0x1DC 0x1E0 0x1E4 0x1E8 0x1EC 0x1F0 0x1F4 0x1F8 0x1FC ) group.long ($2+0x1000)++0x3 line.long 0x0 "REGG4_DOM_$1,Assign domain for RSTGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x80 0x81 0x82 0x83 0x84 0x85 0x86 0x87 0x88 0x89 0x8A 0x8B 0x8C 0x8D 0x8E 0x8F )(list 0x200 0x204 0x208 0x20C 0x210 0x214 0x218 0x21C 0x220 0x224 0x228 0x22C 0x230 0x234 0x238 0x23C ) group.long ($2+0x1000)++0x3 line.long 0x0 "REGG4_DOM_$1,Assign domain for RSTGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x90 0x91 0x92 0x93 0x94 0x95 0x96 0x97 0x98 0x99 0x9A 0x9B 0x9C 0x9D 0x9E 0x9F )(list 0x240 0x244 0x248 0x24C 0x250 0x254 0x258 0x25C 0x260 0x264 0x268 0x26C 0x270 0x274 0x278 0x27C ) group.long ($2+0x1000)++0x3 line.long 0x0 "REGG4_DOM_$1,Assign domain for RSTGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xA0 0xA1 0xA2 0xA3 0xA4 0xA5 0xA6 0xA7 0xA8 0xA9 0xAA 0xAB 0xAC 0xAD 0xAE 0xAF )(list 0x280 0x284 0x288 0x28C 0x290 0x294 0x298 0x29C 0x2A0 0x2A4 0x2A8 0x2AC 0x2B0 0x2B4 0x2B8 0x2BC ) group.long ($2+0x1000)++0x3 line.long 0x0 "REGG4_DOM_$1,Assign domain for RSTGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xB0 0xB1 0xB2 0xB3 0xB4 0xB5 0xB6 0xB7 0xB8 0xB9 0xBA 0xBB 0xBC 0xBD 0xBE 0xBF )(list 0x2C0 0x2C4 0x2C8 0x2CC 0x2D0 0x2D4 0x2D8 0x2DC 0x2E0 0x2E4 0x2E8 0x2EC 0x2F0 0x2F4 0x2F8 0x2FC ) group.long ($2+0x1000)++0x3 line.long 0x0 "REGG4_DOM_$1,Assign domain for RSTGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xC0 0xC1 0xC2 0xC3 0xC4 0xC5 0xC6 0xC7 0xC8 0xC9 0xCA 0xCB 0xCC 0xCD 0xCE 0xCF )(list 0x300 0x304 0x308 0x30C 0x310 0x314 0x318 0x31C 0x320 0x324 0x328 0x32C 0x330 0x334 0x338 0x33C ) group.long ($2+0x1000)++0x3 line.long 0x0 "REGG4_DOM_$1,Assign domain for RSTGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xD0 0xD1 0xD2 0xD3 0xD4 0xD5 0xD6 0xD7 0xD8 0xD9 0xDA 0xDB 0xDC 0xDD 0xDE 0xDF )(list 0x340 0x344 0x348 0x34C 0x350 0x354 0x358 0x35C 0x360 0x364 0x368 0x36C 0x370 0x374 0x378 0x37C ) group.long ($2+0x1000)++0x3 line.long 0x0 "REGG4_DOM_$1,Assign domain for RSTGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xE0 0xE1 0xE2 0xE3 0xE4 0xE5 0xE6 0xE7 0xE8 0xE9 0xEA 0xEB 0xEC 0xED 0xEE 0xEF )(list 0x380 0x384 0x388 0x38C 0x390 0x394 0x398 0x39C 0x3A0 0x3A4 0x3A8 0x3AC 0x3B0 0x3B4 0x3B8 0x3BC ) group.long ($2+0x1000)++0x3 line.long 0x0 "REGG4_DOM_$1,Assign domain for RSTGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xF0 0xF1 0xF2 0xF3 0xF4 0xF5 0xF6 0xF7 0xF8 0xF9 0xFA 0xFB 0xFC 0xFD 0xFE 0xFF )(list 0x3C0 0x3C4 0x3C8 0x3CC 0x3D0 0x3D4 0x3D8 0x3DC 0x3E0 0x3E4 0x3E8 0x3EC 0x3F0 0x3F4 0x3F8 0x3FC ) group.long ($2+0x1000)++0x3 line.long 0x0 "REGG4_DOM_$1,Assign domain for RSTGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x4 0x8 0xC 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C ) group.long ($2+0x1400)++0x3 line.long 0x0 "REGG5_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1A 0x1B 0x1C 0x1D 0x1E 0x1F )(list 0x40 0x44 0x48 0x4C 0x50 0x54 0x58 0x5C 0x60 0x64 0x68 0x6C 0x70 0x74 0x78 0x7C ) group.long ($2+0x1400)++0x3 line.long 0x0 "REGG5_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x20 0x21 0x22 0x23 0x24 0x25 0x26 0x27 0x28 0x29 0x2A 0x2B 0x2C 0x2D 0x2E 0x2F )(list 0x80 0x84 0x88 0x8C 0x90 0x94 0x98 0x9C 0xA0 0xA4 0xA8 0xAC 0xB0 0xB4 0xB8 0xBC ) group.long ($2+0x1400)++0x3 line.long 0x0 "REGG5_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x30 0x31 0x32 0x33 0x34 0x35 0x36 0x37 0x38 0x39 0x3A 0x3B 0x3C 0x3D 0x3E 0x3F )(list 0xC0 0xC4 0xC8 0xCC 0xD0 0xD4 0xD8 0xDC 0xE0 0xE4 0xE8 0xEC 0xF0 0xF4 0xF8 0xFC ) group.long ($2+0x1400)++0x3 line.long 0x0 "REGG5_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x40 0x41 0x42 0x43 0x44 0x45 0x46 0x47 0x48 0x49 0x4A 0x4B 0x4C 0x4D 0x4E 0x4F )(list 0x100 0x104 0x108 0x10C 0x110 0x114 0x118 0x11C 0x120 0x124 0x128 0x12C 0x130 0x134 0x138 0x13C ) group.long ($2+0x1400)++0x3 line.long 0x0 "REGG5_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x50 0x51 0x52 0x53 0x54 0x55 0x56 0x57 0x58 0x59 0x5A 0x5B 0x5C 0x5D 0x5E 0x5F )(list 0x140 0x144 0x148 0x14C 0x150 0x154 0x158 0x15C 0x160 0x164 0x168 0x16C 0x170 0x174 0x178 0x17C ) group.long ($2+0x1400)++0x3 line.long 0x0 "REGG5_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x60 0x61 0x62 0x63 0x64 0x65 0x66 0x67 0x68 0x69 0x6A 0x6B 0x6C 0x6D 0x6E 0x6F )(list 0x180 0x184 0x188 0x18C 0x190 0x194 0x198 0x19C 0x1A0 0x1A4 0x1A8 0x1AC 0x1B0 0x1B4 0x1B8 0x1BC ) group.long ($2+0x1400)++0x3 line.long 0x0 "REGG5_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x70 0x71 0x72 0x73 0x74 0x75 0x76 0x77 0x78 0x79 0x7A 0x7B 0x7C 0x7D 0x7E 0x7F )(list 0x1C0 0x1C4 0x1C8 0x1CC 0x1D0 0x1D4 0x1D8 0x1DC 0x1E0 0x1E4 0x1E8 0x1EC 0x1F0 0x1F4 0x1F8 0x1FC ) group.long ($2+0x1400)++0x3 line.long 0x0 "REGG5_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x80 0x81 0x82 0x83 0x84 0x85 0x86 0x87 0x88 0x89 0x8A 0x8B 0x8C 0x8D 0x8E 0x8F )(list 0x200 0x204 0x208 0x20C 0x210 0x214 0x218 0x21C 0x220 0x224 0x228 0x22C 0x230 0x234 0x238 0x23C ) group.long ($2+0x1400)++0x3 line.long 0x0 "REGG5_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x90 0x91 0x92 0x93 0x94 0x95 0x96 0x97 0x98 0x99 0x9A 0x9B 0x9C 0x9D 0x9E 0x9F )(list 0x240 0x244 0x248 0x24C 0x250 0x254 0x258 0x25C 0x260 0x264 0x268 0x26C 0x270 0x274 0x278 0x27C ) group.long ($2+0x1400)++0x3 line.long 0x0 "REGG5_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xA0 0xA1 0xA2 0xA3 0xA4 0xA5 0xA6 0xA7 0xA8 0xA9 0xAA 0xAB 0xAC 0xAD 0xAE 0xAF )(list 0x280 0x284 0x288 0x28C 0x290 0x294 0x298 0x29C 0x2A0 0x2A4 0x2A8 0x2AC 0x2B0 0x2B4 0x2B8 0x2BC ) group.long ($2+0x1400)++0x3 line.long 0x0 "REGG5_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xB0 0xB1 0xB2 0xB3 0xB4 0xB5 0xB6 0xB7 0xB8 0xB9 0xBA 0xBB 0xBC 0xBD 0xBE 0xBF )(list 0x2C0 0x2C4 0x2C8 0x2CC 0x2D0 0x2D4 0x2D8 0x2DC 0x2E0 0x2E4 0x2E8 0x2EC 0x2F0 0x2F4 0x2F8 0x2FC ) group.long ($2+0x1400)++0x3 line.long 0x0 "REGG5_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xC0 0xC1 0xC2 0xC3 0xC4 0xC5 0xC6 0xC7 0xC8 0xC9 0xCA 0xCB 0xCC 0xCD 0xCE 0xCF )(list 0x300 0x304 0x308 0x30C 0x310 0x314 0x318 0x31C 0x320 0x324 0x328 0x32C 0x330 0x334 0x338 0x33C ) group.long ($2+0x1400)++0x3 line.long 0x0 "REGG5_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xD0 0xD1 0xD2 0xD3 0xD4 0xD5 0xD6 0xD7 0xD8 0xD9 0xDA 0xDB 0xDC 0xDD 0xDE 0xDF )(list 0x340 0x344 0x348 0x34C 0x350 0x354 0x358 0x35C 0x360 0x364 0x368 0x36C 0x370 0x374 0x378 0x37C ) group.long ($2+0x1400)++0x3 line.long 0x0 "REGG5_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xE0 0xE1 0xE2 0xE3 0xE4 0xE5 0xE6 0xE7 0xE8 0xE9 0xEA 0xEB 0xEC 0xED 0xEE 0xEF )(list 0x380 0x384 0x388 0x38C 0x390 0x394 0x398 0x39C 0x3A0 0x3A4 0x3A8 0x3AC 0x3B0 0x3B4 0x3B8 0x3BC ) group.long ($2+0x1400)++0x3 line.long 0x0 "REGG5_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xF0 0xF1 0xF2 0xF3 0xF4 0xF5 0xF6 0xF7 0xF8 0xF9 0xFA 0xFB 0xFC 0xFD 0xFE 0xFF )(list 0x3C0 0x3C4 0x3C8 0x3CC 0x3D0 0x3D4 0x3D8 0x3DC 0x3E0 0x3E4 0x3E8 0x3EC 0x3F0 0x3F4 0x3F8 0x3FC ) group.long ($2+0x1400)++0x3 line.long 0x0 "REGG5_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x4 0x8 0xC 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C ) group.long ($2+0x1800)++0x3 line.long 0x0 "REGG6_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1A 0x1B 0x1C 0x1D 0x1E 0x1F )(list 0x40 0x44 0x48 0x4C 0x50 0x54 0x58 0x5C 0x60 0x64 0x68 0x6C 0x70 0x74 0x78 0x7C ) group.long ($2+0x1800)++0x3 line.long 0x0 "REGG6_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x20 0x21 0x22 0x23 0x24 0x25 0x26 0x27 0x28 0x29 0x2A 0x2B 0x2C 0x2D 0x2E 0x2F )(list 0x80 0x84 0x88 0x8C 0x90 0x94 0x98 0x9C 0xA0 0xA4 0xA8 0xAC 0xB0 0xB4 0xB8 0xBC ) group.long ($2+0x1800)++0x3 line.long 0x0 "REGG6_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x30 0x31 0x32 0x33 0x34 0x35 0x36 0x37 0x38 0x39 0x3A 0x3B 0x3C 0x3D 0x3E 0x3F )(list 0xC0 0xC4 0xC8 0xCC 0xD0 0xD4 0xD8 0xDC 0xE0 0xE4 0xE8 0xEC 0xF0 0xF4 0xF8 0xFC ) group.long ($2+0x1800)++0x3 line.long 0x0 "REGG6_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x40 0x41 0x42 0x43 0x44 0x45 0x46 0x47 0x48 0x49 0x4A 0x4B 0x4C 0x4D 0x4E 0x4F )(list 0x100 0x104 0x108 0x10C 0x110 0x114 0x118 0x11C 0x120 0x124 0x128 0x12C 0x130 0x134 0x138 0x13C ) group.long ($2+0x1800)++0x3 line.long 0x0 "REGG6_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x50 0x51 0x52 0x53 0x54 0x55 0x56 0x57 0x58 0x59 0x5A 0x5B 0x5C 0x5D 0x5E 0x5F )(list 0x140 0x144 0x148 0x14C 0x150 0x154 0x158 0x15C 0x160 0x164 0x168 0x16C 0x170 0x174 0x178 0x17C ) group.long ($2+0x1800)++0x3 line.long 0x0 "REGG6_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x60 0x61 0x62 0x63 0x64 0x65 0x66 0x67 0x68 0x69 0x6A 0x6B 0x6C 0x6D 0x6E 0x6F )(list 0x180 0x184 0x188 0x18C 0x190 0x194 0x198 0x19C 0x1A0 0x1A4 0x1A8 0x1AC 0x1B0 0x1B4 0x1B8 0x1BC ) group.long ($2+0x1800)++0x3 line.long 0x0 "REGG6_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x70 0x71 0x72 0x73 0x74 0x75 0x76 0x77 0x78 0x79 0x7A 0x7B 0x7C 0x7D 0x7E 0x7F )(list 0x1C0 0x1C4 0x1C8 0x1CC 0x1D0 0x1D4 0x1D8 0x1DC 0x1E0 0x1E4 0x1E8 0x1EC 0x1F0 0x1F4 0x1F8 0x1FC ) group.long ($2+0x1800)++0x3 line.long 0x0 "REGG6_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x80 0x81 0x82 0x83 0x84 0x85 0x86 0x87 0x88 0x89 0x8A 0x8B 0x8C 0x8D 0x8E 0x8F )(list 0x200 0x204 0x208 0x20C 0x210 0x214 0x218 0x21C 0x220 0x224 0x228 0x22C 0x230 0x234 0x238 0x23C ) group.long ($2+0x1800)++0x3 line.long 0x0 "REGG6_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x90 0x91 0x92 0x93 0x94 0x95 0x96 0x97 0x98 0x99 0x9A 0x9B 0x9C 0x9D 0x9E 0x9F )(list 0x240 0x244 0x248 0x24C 0x250 0x254 0x258 0x25C 0x260 0x264 0x268 0x26C 0x270 0x274 0x278 0x27C ) group.long ($2+0x1800)++0x3 line.long 0x0 "REGG6_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xA0 0xA1 0xA2 0xA3 0xA4 0xA5 0xA6 0xA7 0xA8 0xA9 0xAA 0xAB 0xAC 0xAD 0xAE 0xAF )(list 0x280 0x284 0x288 0x28C 0x290 0x294 0x298 0x29C 0x2A0 0x2A4 0x2A8 0x2AC 0x2B0 0x2B4 0x2B8 0x2BC ) group.long ($2+0x1800)++0x3 line.long 0x0 "REGG6_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xB0 0xB1 0xB2 0xB3 0xB4 0xB5 0xB6 0xB7 0xB8 0xB9 0xBA 0xBB 0xBC 0xBD 0xBE 0xBF )(list 0x2C0 0x2C4 0x2C8 0x2CC 0x2D0 0x2D4 0x2D8 0x2DC 0x2E0 0x2E4 0x2E8 0x2EC 0x2F0 0x2F4 0x2F8 0x2FC ) group.long ($2+0x1800)++0x3 line.long 0x0 "REGG6_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xC0 0xC1 0xC2 0xC3 0xC4 0xC5 0xC6 0xC7 0xC8 0xC9 0xCA 0xCB 0xCC 0xCD 0xCE 0xCF )(list 0x300 0x304 0x308 0x30C 0x310 0x314 0x318 0x31C 0x320 0x324 0x328 0x32C 0x330 0x334 0x338 0x33C ) group.long ($2+0x1800)++0x3 line.long 0x0 "REGG6_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xD0 0xD1 0xD2 0xD3 0xD4 0xD5 0xD6 0xD7 0xD8 0xD9 0xDA 0xDB 0xDC 0xDD 0xDE 0xDF )(list 0x340 0x344 0x348 0x34C 0x350 0x354 0x358 0x35C 0x360 0x364 0x368 0x36C 0x370 0x374 0x378 0x37C ) group.long ($2+0x1800)++0x3 line.long 0x0 "REGG6_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xE0 0xE1 0xE2 0xE3 0xE4 0xE5 0xE6 0xE7 0xE8 0xE9 0xEA 0xEB 0xEC 0xED 0xEE 0xEF )(list 0x380 0x384 0x388 0x38C 0x390 0x394 0x398 0x39C 0x3A0 0x3A4 0x3A8 0x3AC 0x3B0 0x3B4 0x3B8 0x3BC ) group.long ($2+0x1800)++0x3 line.long 0x0 "REGG6_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xF0 0xF1 0xF2 0xF3 0xF4 0xF5 0xF6 0xF7 0xF8 0xF9 0xFA 0xFB 0xFC 0xFD 0xFE 0xFF )(list 0x3C0 0x3C4 0x3C8 0x3CC 0x3D0 0x3D4 0x3D8 0x3DC 0x3E0 0x3E4 0x3E8 0x3EC 0x3F0 0x3F4 0x3F8 0x3FC ) group.long ($2+0x1800)++0x3 line.long 0x0 "REGG6_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x4 0x8 0xC 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C ) group.long ($2+0x1C00)++0x3 line.long 0x0 "REGG7_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1A 0x1B 0x1C 0x1D 0x1E 0x1F )(list 0x40 0x44 0x48 0x4C 0x50 0x54 0x58 0x5C 0x60 0x64 0x68 0x6C 0x70 0x74 0x78 0x7C ) group.long ($2+0x1C00)++0x3 line.long 0x0 "REGG7_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x20 0x21 0x22 0x23 0x24 0x25 0x26 0x27 0x28 0x29 0x2A 0x2B 0x2C 0x2D 0x2E 0x2F )(list 0x80 0x84 0x88 0x8C 0x90 0x94 0x98 0x9C 0xA0 0xA4 0xA8 0xAC 0xB0 0xB4 0xB8 0xBC ) group.long ($2+0x1C00)++0x3 line.long 0x0 "REGG7_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x30 0x31 0x32 0x33 0x34 0x35 0x36 0x37 0x38 0x39 0x3A 0x3B 0x3C 0x3D 0x3E 0x3F )(list 0xC0 0xC4 0xC8 0xCC 0xD0 0xD4 0xD8 0xDC 0xE0 0xE4 0xE8 0xEC 0xF0 0xF4 0xF8 0xFC ) group.long ($2+0x1C00)++0x3 line.long 0x0 "REGG7_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x40 0x41 0x42 0x43 0x44 0x45 0x46 0x47 0x48 0x49 0x4A 0x4B 0x4C 0x4D 0x4E 0x4F )(list 0x100 0x104 0x108 0x10C 0x110 0x114 0x118 0x11C 0x120 0x124 0x128 0x12C 0x130 0x134 0x138 0x13C ) group.long ($2+0x1C00)++0x3 line.long 0x0 "REGG7_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x50 0x51 0x52 0x53 0x54 0x55 0x56 0x57 0x58 0x59 0x5A 0x5B 0x5C 0x5D 0x5E 0x5F )(list 0x140 0x144 0x148 0x14C 0x150 0x154 0x158 0x15C 0x160 0x164 0x168 0x16C 0x170 0x174 0x178 0x17C ) group.long ($2+0x1C00)++0x3 line.long 0x0 "REGG7_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x60 0x61 0x62 0x63 0x64 0x65 0x66 0x67 0x68 0x69 0x6A 0x6B 0x6C 0x6D 0x6E 0x6F )(list 0x180 0x184 0x188 0x18C 0x190 0x194 0x198 0x19C 0x1A0 0x1A4 0x1A8 0x1AC 0x1B0 0x1B4 0x1B8 0x1BC ) group.long ($2+0x1C00)++0x3 line.long 0x0 "REGG7_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x70 0x71 0x72 0x73 0x74 0x75 0x76 0x77 0x78 0x79 0x7A 0x7B 0x7C 0x7D 0x7E 0x7F )(list 0x1C0 0x1C4 0x1C8 0x1CC 0x1D0 0x1D4 0x1D8 0x1DC 0x1E0 0x1E4 0x1E8 0x1EC 0x1F0 0x1F4 0x1F8 0x1FC ) group.long ($2+0x1C00)++0x3 line.long 0x0 "REGG7_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x80 0x81 0x82 0x83 0x84 0x85 0x86 0x87 0x88 0x89 0x8A 0x8B 0x8C 0x8D 0x8E 0x8F )(list 0x200 0x204 0x208 0x20C 0x210 0x214 0x218 0x21C 0x220 0x224 0x228 0x22C 0x230 0x234 0x238 0x23C ) group.long ($2+0x1C00)++0x3 line.long 0x0 "REGG7_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x90 0x91 0x92 0x93 0x94 0x95 0x96 0x97 0x98 0x99 0x9A 0x9B 0x9C 0x9D 0x9E 0x9F )(list 0x240 0x244 0x248 0x24C 0x250 0x254 0x258 0x25C 0x260 0x264 0x268 0x26C 0x270 0x274 0x278 0x27C ) group.long ($2+0x1C00)++0x3 line.long 0x0 "REGG7_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xA0 0xA1 0xA2 0xA3 0xA4 0xA5 0xA6 0xA7 0xA8 0xA9 0xAA 0xAB 0xAC 0xAD 0xAE 0xAF )(list 0x280 0x284 0x288 0x28C 0x290 0x294 0x298 0x29C 0x2A0 0x2A4 0x2A8 0x2AC 0x2B0 0x2B4 0x2B8 0x2BC ) group.long ($2+0x1C00)++0x3 line.long 0x0 "REGG7_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xB0 0xB1 0xB2 0xB3 0xB4 0xB5 0xB6 0xB7 0xB8 0xB9 0xBA 0xBB 0xBC 0xBD 0xBE 0xBF )(list 0x2C0 0x2C4 0x2C8 0x2CC 0x2D0 0x2D4 0x2D8 0x2DC 0x2E0 0x2E4 0x2E8 0x2EC 0x2F0 0x2F4 0x2F8 0x2FC ) group.long ($2+0x1C00)++0x3 line.long 0x0 "REGG7_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xC0 0xC1 0xC2 0xC3 0xC4 0xC5 0xC6 0xC7 0xC8 0xC9 0xCA 0xCB 0xCC 0xCD 0xCE 0xCF )(list 0x300 0x304 0x308 0x30C 0x310 0x314 0x318 0x31C 0x320 0x324 0x328 0x32C 0x330 0x334 0x338 0x33C ) group.long ($2+0x1C00)++0x3 line.long 0x0 "REGG7_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xD0 0xD1 0xD2 0xD3 0xD4 0xD5 0xD6 0xD7 0xD8 0xD9 0xDA 0xDB 0xDC 0xDD 0xDE 0xDF )(list 0x340 0x344 0x348 0x34C 0x350 0x354 0x358 0x35C 0x360 0x364 0x368 0x36C 0x370 0x374 0x378 0x37C ) group.long ($2+0x1C00)++0x3 line.long 0x0 "REGG7_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xE0 0xE1 0xE2 0xE3 0xE4 0xE5 0xE6 0xE7 0xE8 0xE9 0xEA 0xEB 0xEC 0xED 0xEE 0xEF )(list 0x380 0x384 0x388 0x38C 0x390 0x394 0x398 0x39C 0x3A0 0x3A4 0x3A8 0x3AC 0x3B0 0x3B4 0x3B8 0x3BC ) group.long ($2+0x1C00)++0x3 line.long 0x0 "REGG7_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xF0 0xF1 0xF2 0xF3 0xF4 0xF5 0xF6 0xF7 0xF8 0xF9 0xFA 0xFB 0xFC 0xFD 0xFE 0xFF )(list 0x3C0 0x3C4 0x3C8 0x3CC 0x3D0 0x3D4 0x3D8 0x3DC 0x3E0 0x3E4 0x3E8 0x3EC 0x3F0 0x3F4 0x3F8 0x3FC ) group.long ($2+0x1C00)++0x3 line.long 0x0 "REGG7_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end group.long 0x2000++0x17 line.long 0x0 "GLB_CTL,This register provides global enable settings for permission control." bitfld.long 0x0 5. "DOM_CFG_LOCK,Lock write for DOM_CFG_MODE bit." "0,1" bitfld.long 0x0 4. "DOM_CFG_MODE,When enabled all the source setting can be configured by master from domain 0 if it is not locked. When disabled only resource manager can configure the permission of the resource." "0,1" bitfld.long 0x0 3. "PERCK_DIS_LOCK,Lock write for PERCK_DIS" "0,1" bitfld.long 0x0 2. "PERCK_DIS,All the permission check disable." "0,1" newline bitfld.long 0x0 1. "DOM_PRO_LOCK,Lock write for DOM_PRO_EN bit." "0,1" bitfld.long 0x0 0. "DOM_PRO_EN,When disabled no domain access permission check" "0,1" line.long 0x4 "RES_MGR,Resource manager register. This regster is used to assign resource manager for global resource access control" bitfld.long 0x4 17. "MID_LOCK,Lock write for MID_EN and MID_LOW and MID_HIG registers." "0,1" bitfld.long 0x4 16. "MID_EN,Master ID check enable" "0,1" bitfld.long 0x4 15. "PRI_PER_LOCK,Lock write for PRI_PER and PRI_PER_EN" "0,1" bitfld.long 0x4 13.--14. "PRI_PER,Resource manager privileged access permission. bit0 for privileged access bit1 for user access" "0,1,2,3" newline bitfld.long 0x4 12. "PRI_PER_EN,Resource manager privileged access permission enable." "0,1" bitfld.long 0x4 11. "SEC_PER_LOCK,Lock for SEC_PER and SEC_PER_LOCK" "0,1" bitfld.long 0x4 9.--10. "SEC_PER,Resource manager secure access permission. bit 0 for secure access bit 1 for non-secure access" "0,1,2,3" bitfld.long 0x4 8. "SEC_PER_EN,Resource manager secure permission enable" "0,1" bitfld.long 0x4 7. "DID_LOCK,Lock write for DID_EN and DID" "0,1" newline hexmask.long.byte 0x4 3.--6. 1. "DID,Resource manager domain ID" bitfld.long 0x4 2. "DID_EN,Resource manager Domain ID enable" "0,1" bitfld.long 0x4 1. "RES_MGR_EN_LOCK,Lock for RES_MGR_EN" "0,1" bitfld.long 0x4 0. "RES_MGR_EN,Resource manager enable. When the bit is disable there is no resource manager." "0,1" line.long 0x8 "RES_MGR_MA0,This register is used to assign master 0~31 as resource manager." hexmask.long 0x8 0.--31. 1. "MID,Assign master 0~31 for resource manager" line.long 0xC "RES_MGR_MA1,This register is used to assign master 32~63 as resource manager." hexmask.long 0xC 0.--31. 1. "MID,Indicate if master 32~63 is resource manager." line.long 0x10 "RES_MGR_MA2,This register is used to assign master 64~95 as resource manager." hexmask.long 0x10 0.--31. 1. "MID,Indicate if master 64~95 is resource manager." line.long 0x14 "RES_MGR_MA3,This register is used to assign master 96~127 as resource manager." hexmask.long 0x14 0.--31. 1. "MID,Indicate if master 96~127 is resource manager." repeat 8. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 )(list 0x0 0x14 0x28 0x3C 0x50 0x64 0x78 0x8C ) group.long ($2+0x2100)++0x3 line.long 0x0 "GRP_MGR_$1,Group Manager Register. This register is used to assign group manager for each domain" bitfld.long 0x0 17. "MID_LOCK,Lock write for MID_EN and MID_LOW and MID_HIG registers." "0,1" bitfld.long 0x0 16. "MID_EN,Master ID check enable" "0,1" bitfld.long 0x0 15. "PRI_PER_LOCK,Lock write for PRI_PER and PRI_PER_EN" "0,1" bitfld.long 0x0 13.--14. "PRI_PER,Group manager privileged access permission. bit0 for privileged access bit1 for user access" "0,1,2,3" newline bitfld.long 0x0 12. "PRI_PER_EN,Group manager privileged access permission enable." "0,1" bitfld.long 0x0 11. "SEC_PER_LOCK,Lock for SEC_PER and SEC_PER_LOCK" "0,1" bitfld.long 0x0 9.--10. "SEC_PER,Group manager secure access permission. bit 0 for secure access bit 1 for non-secure access" "0,1,2,3" bitfld.long 0x0 8. "SEC_PER_EN,Group manager secure permission enable" "0,1" bitfld.long 0x0 7. "DID_LOCK,Lock write for DID_EN and DID" "0,1" newline hexmask.long.byte 0x0 3.--6. 1. "DID,Group manager domain ID" bitfld.long 0x0 2. "DID_EN,Group manager Domain ID enable" "0,1" bitfld.long 0x0 1. "GRP_MGR_EN_LOCK,Lock write for GPR_MGR_EN" "0,1" bitfld.long 0x0 0. "GRP_MGR_EN,Group manager enable. When the bit is disable there is no resource manager." "0,1" repeat.end repeat 8. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 )(list 0x0 0x14 0x28 0x3C 0x50 0x64 0x78 0x8C ) group.long ($2+0x2104)++0x3 line.long 0x0 "GRP_MGR_MA0_$1,Assign master 0~31 for group manager 0" hexmask.long 0x0 0.--31. 1. "MID,Assign master 0~31 for resource manager" repeat.end repeat 8. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 )(list 0x0 0x14 0x28 0x3C 0x50 0x64 0x78 0x8C ) group.long ($2+0x2108)++0x3 line.long 0x0 "GRP_MGR_MA1_$1,Assign master 32~63 for group manager 0" hexmask.long 0x0 0.--31. 1. "MID,Indicate if master 32~63 is resource manager." repeat.end repeat 8. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 )(list 0x0 0x14 0x28 0x3C 0x50 0x64 0x78 0x8C ) group.long ($2+0x210C)++0x3 line.long 0x0 "GRP_MGR_MA2_$1,Assign master 64~95 for group manager 0" hexmask.long 0x0 0.--31. 1. "MID,Indicate if master 64~95 is resource manager." repeat.end repeat 8. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 )(list 0x0 0x14 0x28 0x3C 0x50 0x64 0x78 0x8C ) group.long ($2+0x2110)++0x3 line.long 0x0 "GRP_MGR_MA3_$1,Assign master 96~127 for group manager 0" hexmask.long 0x0 0.--31. 1. "MID,Indicate if master 96~127 is resource manager." repeat.end group.long 0x2200++0x3 line.long 0x0 "DOM_GID_0,Indicate which group domain 0 belong to" bitfld.long 0x0 3. "LOCK,Lock write for GID" "0,1" bitfld.long 0x0 0.--2. "GID,Group ID" "0,1,2,3,4,5,6,7" repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x18 0x30 0x48 0x60 0x78 0x90 0xA8 0xC0 0xD8 0xF0 0x108 0x120 0x138 0x150 0x168 ) group.long ($2+0x2204)++0x3 line.long 0x0 "DOM_OWN_$1,Assign owner for function domain 0." bitfld.long 0x0 17. "MID_LOCK,Lock write for MID_EN and MID_LOW and MID_HIG registers." "0,1" bitfld.long 0x0 16. "MID_EN,Master ID check enable" "0,1" bitfld.long 0x0 15. "PRI_PER_LOCK,Lock write for PRI_PER and PRI_PER_EN" "0,1" bitfld.long 0x0 13.--14. "PRI_PER,Group manager privileged access permission. bit0 for privileged access bit1 for user access" "0,1,2,3" newline bitfld.long 0x0 12. "PRI_PER_EN,Group manager privileged access permission enable." "0,1" bitfld.long 0x0 11. "SEC_PER_LOCK,Lock for SEC_PER and SEC_PER_LOCK" "0,1" bitfld.long 0x0 9.--10. "SEC_PER,Domain owner secure access permission. bit 0 for secure access bit 1 for non-secure access" "0,1,2,3" bitfld.long 0x0 8. "SEC_PER_EN,Domain owner secure permission enable" "0,1" newline bitfld.long 0x0 1. "DOM_OWN_EN_LOCK,Lock for DOM_OWN_EN" "0,1" bitfld.long 0x0 0. "DOM_OWN_EN,Domain owner enable. When the bit is disable there is no domain owner." "0,1" repeat.end repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x18 0x30 0x48 0x60 0x78 0x90 0xA8 0xC0 0xD8 0xF0 0x108 0x120 0x138 0x150 0x168 ) group.long ($2+0x2208)++0x3 line.long 0x0 "DOM_OWN_MA0_$1,Assign master 0~31 for domain owner 0" hexmask.long 0x0 0.--31. 1. "MID,Assign master 0~31 for resource manager" repeat.end repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x18 0x30 0x48 0x60 0x78 0x90 0xA8 0xC0 0xD8 0xF0 0x108 0x120 0x138 0x150 0x168 ) group.long ($2+0x220C)++0x3 line.long 0x0 "DOM_OWN_MA1_$1,Assign master 32~63 for domain owner 0" hexmask.long 0x0 0.--31. 1. "MID,Indicate if master 32~63 is resource manager." repeat.end repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x18 0x30 0x48 0x60 0x78 0x90 0xA8 0xC0 0xD8 0xF0 0x108 0x120 0x138 0x150 0x168 ) group.long ($2+0x2210)++0x3 line.long 0x0 "DOM_OWN_MA2_$1,Assign master 64~95 for domain owner 0" hexmask.long 0x0 0.--31. 1. "MID,Indicate if master 64~95 is resource manager." repeat.end repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x18 0x30 0x48 0x60 0x78 0x90 0xA8 0xC0 0xD8 0xF0 0x108 0x120 0x138 0x150 0x168 ) group.long ($2+0x2214)++0x3 line.long 0x0 "DOM_OWN_MA3_$1,Assign master 96~127 for domain owner 0" hexmask.long 0x0 0.--31. 1. "MID,Indicate if master 96~127 is resource manager." repeat.end group.long 0x2218++0x3 line.long 0x0 "DOM_GID_1,Indicate which group domain 1 belong to" bitfld.long 0x0 3. "LOCK,Lock write for GID" "0,1" bitfld.long 0x0 0.--2. "GID,Group ID" "0,1,2,3,4,5,6,7" group.long 0x2230++0x3 line.long 0x0 "DOM_GID_2,Indicate which group domain 2 belong to" bitfld.long 0x0 3. "LOCK,Lock write for GID" "0,1" bitfld.long 0x0 0.--2. "GID,Group ID" "0,1,2,3,4,5,6,7" group.long 0x2248++0x3 line.long 0x0 "DOM_GID_3,Indicate which group domain 3 belong to" bitfld.long 0x0 3. "LOCK,Lock write for GID" "0,1" bitfld.long 0x0 0.--2. "GID,Group ID" "0,1,2,3,4,5,6,7" group.long 0x2260++0x3 line.long 0x0 "DOM_GID_4,Indicate which group domain 4 belong to" bitfld.long 0x0 3. "LOCK,Lock write for GID" "0,1" bitfld.long 0x0 0.--2. "GID,Group ID" "0,1,2,3,4,5,6,7" group.long 0x2278++0x3 line.long 0x0 "DOM_GID_5,Indicate which group domain 5 belong to" bitfld.long 0x0 3. "LOCK,Lock write for GID" "0,1" bitfld.long 0x0 0.--2. "GID,Group ID" "0,1,2,3,4,5,6,7" group.long 0x2290++0x3 line.long 0x0 "DOM_GID_6,Indicate which group domain 6 belong to" bitfld.long 0x0 3. "LOCK,Lock write for GID" "0,1" bitfld.long 0x0 0.--2. "GID,Group ID" "0,1,2,3,4,5,6,7" group.long 0x22A8++0x3 line.long 0x0 "DOM_GID_7,Indicate which group domain 7 belong to" bitfld.long 0x0 3. "LOCK,Lock write for GID" "0,1" bitfld.long 0x0 0.--2. "GID,Group ID" "0,1,2,3,4,5,6,7" group.long 0x22C0++0x3 line.long 0x0 "DOM_GID_8,Indicate which group domain 8 belong to" bitfld.long 0x0 3. "LOCK,Lock write for GID" "0,1" bitfld.long 0x0 0.--2. "GID,Group ID" "0,1,2,3,4,5,6,7" group.long 0x22D8++0x3 line.long 0x0 "DOM_GID_9,Indicate which group domain 9 belong to" bitfld.long 0x0 3. "LOCK,Lock write for GID" "0,1" bitfld.long 0x0 0.--2. "GID,Group ID" "0,1,2,3,4,5,6,7" group.long 0x22F0++0x3 line.long 0x0 "DOM_GID_10,Indicate which group domain 10 belong to" bitfld.long 0x0 3. "LOCK,Lock write for GID" "0,1" bitfld.long 0x0 0.--2. "GID,Group ID" "0,1,2,3,4,5,6,7" group.long 0x2308++0x3 line.long 0x0 "DOM_GID_11,Indicate which group domain 11 belong to" bitfld.long 0x0 3. "LOCK,Lock write for GID" "0,1" bitfld.long 0x0 0.--2. "GID,Group ID" "0,1,2,3,4,5,6,7" group.long 0x2320++0x3 line.long 0x0 "DOM_GID_12,Indicate which group domain 12 belong to" bitfld.long 0x0 3. "LOCK,Lock write for GID" "0,1" bitfld.long 0x0 0.--2. "GID,Group ID" "0,1,2,3,4,5,6,7" group.long 0x2338++0x3 line.long 0x0 "DOM_GID_13,Indicate which group domain 13 belong to" bitfld.long 0x0 3. "LOCK,Lock write for GID" "0,1" bitfld.long 0x0 0.--2. "GID,Group ID" "0,1,2,3,4,5,6,7" group.long 0x2350++0x3 line.long 0x0 "DOM_GID_14,Indicate which group domain 14 belong to" bitfld.long 0x0 3. "LOCK,Lock write for GID" "0,1" bitfld.long 0x0 0.--2. "GID,Group ID" "0,1,2,3,4,5,6,7" group.long 0x2368++0x3 line.long 0x0 "DOM_GID_15,Indicate which group domain 15 belong to" bitfld.long 0x0 3. "LOCK,Lock write for GID" "0,1" bitfld.long 0x0 0.--2. "GID,Group ID" "0,1,2,3,4,5,6,7" repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x34 0x68 0x9C 0xD0 0x104 0x138 0x16C 0x1A0 0x1D4 0x208 0x23C 0x270 0x2A4 0x2D8 0x30C ) group.long ($2+0x2400)++0x3 line.long 0x0 "DOM_PER0_$1,Domain Permission Control. It can be only configured by resource manager and domain owner." bitfld.long 0x0 31. "DOM7_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 29.--30. "DOM7_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 28. "DOM7_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 27. "DOM6_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 25.--26. "DOM6_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" newline bitfld.long 0x0 24. "DOM6_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 23. "DOM5_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 21.--22. "DOM5_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 20. "DOM5_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 19. "DOM4_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" newline bitfld.long 0x0 17.--18. "DOM4_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM4_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 15. "DOM3_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 13.--14. "DOM3_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 12. "DOM3_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" newline bitfld.long 0x0 11. "DOM2_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 9.--10. "DOM2_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM2_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 7. "DOM1_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 5.--6. "DOM1_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" newline bitfld.long 0x0 4. "DOM1_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 3. "DOM0_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 1.--2. "DOM0_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM0_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" repeat.end repeat 16. (list 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1A 0x1B 0x1C 0x1D 0x1E 0x1F )(list 0x340 0x374 0x3A8 0x3DC 0x410 0x444 0x478 0x4AC 0x4E0 0x514 0x548 0x57C 0x5B0 0x5E4 0x618 0x64C ) group.long ($2+0x2400)++0x3 line.long 0x0 "DOM_PER0_$1,Domain Permission Control. It can be only configured by resource manager and domain owner." bitfld.long 0x0 31. "DOM7_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 29.--30. "DOM7_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 28. "DOM7_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 27. "DOM6_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 25.--26. "DOM6_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" newline bitfld.long 0x0 24. "DOM6_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 23. "DOM5_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 21.--22. "DOM5_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 20. "DOM5_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 19. "DOM4_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" newline bitfld.long 0x0 17.--18. "DOM4_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM4_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 15. "DOM3_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 13.--14. "DOM3_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 12. "DOM3_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" newline bitfld.long 0x0 11. "DOM2_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 9.--10. "DOM2_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM2_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 7. "DOM1_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 5.--6. "DOM1_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" newline bitfld.long 0x0 4. "DOM1_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 3. "DOM0_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 1.--2. "DOM0_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM0_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" repeat.end repeat 16. (list 0x20 0x21 0x22 0x23 0x24 0x25 0x26 0x27 0x28 0x29 0x2A 0x2B 0x2C 0x2D 0x2E 0x2F )(list 0x680 0x6B4 0x6E8 0x71C 0x750 0x784 0x7B8 0x7EC 0x820 0x854 0x888 0x8BC 0x8F0 0x924 0x958 0x98C ) group.long ($2+0x2400)++0x3 line.long 0x0 "DOM_PER0_$1,Domain Permission Control. It can be only configured by resource manager and domain owner." bitfld.long 0x0 31. "DOM7_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 29.--30. "DOM7_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 28. "DOM7_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 27. "DOM6_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 25.--26. "DOM6_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" newline bitfld.long 0x0 24. "DOM6_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 23. "DOM5_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 21.--22. "DOM5_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 20. "DOM5_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 19. "DOM4_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" newline bitfld.long 0x0 17.--18. "DOM4_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM4_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 15. "DOM3_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 13.--14. "DOM3_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 12. "DOM3_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" newline bitfld.long 0x0 11. "DOM2_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 9.--10. "DOM2_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM2_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 7. "DOM1_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 5.--6. "DOM1_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" newline bitfld.long 0x0 4. "DOM1_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 3. "DOM0_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 1.--2. "DOM0_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM0_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" repeat.end repeat 16. (list 0x30 0x31 0x32 0x33 0x34 0x35 0x36 0x37 0x38 0x39 0x3A 0x3B 0x3C 0x3D 0x3E 0x3F )(list 0x9C0 0x9F4 0xA28 0xA5C 0xA90 0xAC4 0xAF8 0xB2C 0xB60 0xB94 0xBC8 0xBFC 0xC30 0xC64 0xC98 0xCCC ) group.long ($2+0x2400)++0x3 line.long 0x0 "DOM_PER0_$1,Domain Permission Control. It can be only configured by resource manager and domain owner." bitfld.long 0x0 31. "DOM7_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 29.--30. "DOM7_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 28. "DOM7_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 27. "DOM6_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 25.--26. "DOM6_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" newline bitfld.long 0x0 24. "DOM6_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 23. "DOM5_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 21.--22. "DOM5_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 20. "DOM5_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 19. "DOM4_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" newline bitfld.long 0x0 17.--18. "DOM4_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM4_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 15. "DOM3_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 13.--14. "DOM3_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 12. "DOM3_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" newline bitfld.long 0x0 11. "DOM2_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 9.--10. "DOM2_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM2_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 7. "DOM1_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 5.--6. "DOM1_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" newline bitfld.long 0x0 4. "DOM1_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 3. "DOM0_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 1.--2. "DOM0_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM0_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" repeat.end repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x34 0x68 0x9C 0xD0 0x104 0x138 0x16C 0x1A0 0x1D4 0x208 0x23C 0x270 0x2A4 0x2D8 0x30C ) group.long ($2+0x2404)++0x3 line.long 0x0 "DOM_PER1_$1,Domain Permission Control. It can be only configured by resource manager and domain owner." bitfld.long 0x0 31. "DOM15_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 29.--30. "DOM15_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 28. "DOM15_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 27. "DOM14_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 25.--26. "DOM14_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" newline bitfld.long 0x0 24. "DOM14_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 23. "DOM13_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 21.--22. "DOM13_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 20. "DOM13_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 19. "DOM12_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" newline bitfld.long 0x0 17.--18. "DOM12_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM12_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 15. "DOM11_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 13.--14. "DOM11_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 12. "DOM11_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" newline bitfld.long 0x0 11. "DOM10_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 9.--10. "DOM10_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM10_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 7. "DOM9_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 5.--6. "DOM9_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" newline bitfld.long 0x0 4. "DOM9_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 3. "DOM8_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 1.--2. "DOM8_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM8_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" repeat.end repeat 16. (list 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1A 0x1B 0x1C 0x1D 0x1E 0x1F )(list 0x340 0x374 0x3A8 0x3DC 0x410 0x444 0x478 0x4AC 0x4E0 0x514 0x548 0x57C 0x5B0 0x5E4 0x618 0x64C ) group.long ($2+0x2404)++0x3 line.long 0x0 "DOM_PER1_$1,Domain Permission Control. It can be only configured by resource manager and domain owner." bitfld.long 0x0 31. "DOM15_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 29.--30. "DOM15_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 28. "DOM15_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 27. "DOM14_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 25.--26. "DOM14_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" newline bitfld.long 0x0 24. "DOM14_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 23. "DOM13_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 21.--22. "DOM13_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 20. "DOM13_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 19. "DOM12_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" newline bitfld.long 0x0 17.--18. "DOM12_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM12_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 15. "DOM11_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 13.--14. "DOM11_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 12. "DOM11_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" newline bitfld.long 0x0 11. "DOM10_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 9.--10. "DOM10_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM10_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 7. "DOM9_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 5.--6. "DOM9_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" newline bitfld.long 0x0 4. "DOM9_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 3. "DOM8_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 1.--2. "DOM8_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM8_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" repeat.end repeat 16. (list 0x20 0x21 0x22 0x23 0x24 0x25 0x26 0x27 0x28 0x29 0x2A 0x2B 0x2C 0x2D 0x2E 0x2F )(list 0x680 0x6B4 0x6E8 0x71C 0x750 0x784 0x7B8 0x7EC 0x820 0x854 0x888 0x8BC 0x8F0 0x924 0x958 0x98C ) group.long ($2+0x2404)++0x3 line.long 0x0 "DOM_PER1_$1,Domain Permission Control. It can be only configured by resource manager and domain owner." bitfld.long 0x0 31. "DOM15_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 29.--30. "DOM15_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 28. "DOM15_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 27. "DOM14_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 25.--26. "DOM14_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" newline bitfld.long 0x0 24. "DOM14_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 23. "DOM13_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 21.--22. "DOM13_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 20. "DOM13_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 19. "DOM12_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" newline bitfld.long 0x0 17.--18. "DOM12_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM12_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 15. "DOM11_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 13.--14. "DOM11_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 12. "DOM11_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" newline bitfld.long 0x0 11. "DOM10_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 9.--10. "DOM10_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM10_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 7. "DOM9_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 5.--6. "DOM9_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" newline bitfld.long 0x0 4. "DOM9_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 3. "DOM8_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 1.--2. "DOM8_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM8_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" repeat.end repeat 16. (list 0x30 0x31 0x32 0x33 0x34 0x35 0x36 0x37 0x38 0x39 0x3A 0x3B 0x3C 0x3D 0x3E 0x3F )(list 0x9C0 0x9F4 0xA28 0xA5C 0xA90 0xAC4 0xAF8 0xB2C 0xB60 0xB94 0xBC8 0xBFC 0xC30 0xC64 0xC98 0xCCC ) group.long ($2+0x2404)++0x3 line.long 0x0 "DOM_PER1_$1,Domain Permission Control. It can be only configured by resource manager and domain owner." bitfld.long 0x0 31. "DOM15_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 29.--30. "DOM15_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 28. "DOM15_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 27. "DOM14_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 25.--26. "DOM14_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" newline bitfld.long 0x0 24. "DOM14_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 23. "DOM13_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 21.--22. "DOM13_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 20. "DOM13_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 19. "DOM12_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" newline bitfld.long 0x0 17.--18. "DOM12_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM12_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 15. "DOM11_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 13.--14. "DOM11_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 12. "DOM11_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" newline bitfld.long 0x0 11. "DOM10_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 9.--10. "DOM10_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM10_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 7. "DOM9_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 5.--6. "DOM9_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" newline bitfld.long 0x0 4. "DOM9_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 3. "DOM8_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 1.--2. "DOM8_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM8_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" repeat.end repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x34 0x68 0x9C 0xD0 0x104 0x138 0x16C 0x1A0 0x1D4 0x208 0x23C 0x270 0x2A4 0x2D8 0x30C ) group.long ($2+0x2408)++0x3 line.long 0x0 "SEC_PER0_$1,This register is only used for resource manager to control secure access permission." bitfld.long 0x0 31. "DOM3_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM3_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM3_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM3_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM2_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM2_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM2_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM2_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM1_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM1_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM1_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM1_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM0_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM0_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM0_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM0_SEC_EN,Domain secure permission control enable" "0,1" repeat.end repeat 16. (list 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1A 0x1B 0x1C 0x1D 0x1E 0x1F )(list 0x340 0x374 0x3A8 0x3DC 0x410 0x444 0x478 0x4AC 0x4E0 0x514 0x548 0x57C 0x5B0 0x5E4 0x618 0x64C ) group.long ($2+0x2408)++0x3 line.long 0x0 "SEC_PER0_$1,This register is only used for resource manager to control secure access permission." bitfld.long 0x0 31. "DOM3_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM3_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM3_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM3_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM2_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM2_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM2_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM2_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM1_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM1_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM1_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM1_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM0_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM0_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM0_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM0_SEC_EN,Domain secure permission control enable" "0,1" repeat.end repeat 16. (list 0x20 0x21 0x22 0x23 0x24 0x25 0x26 0x27 0x28 0x29 0x2A 0x2B 0x2C 0x2D 0x2E 0x2F )(list 0x680 0x6B4 0x6E8 0x71C 0x750 0x784 0x7B8 0x7EC 0x820 0x854 0x888 0x8BC 0x8F0 0x924 0x958 0x98C ) group.long ($2+0x2408)++0x3 line.long 0x0 "SEC_PER0_$1,This register is only used for resource manager to control secure access permission." bitfld.long 0x0 31. "DOM3_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM3_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM3_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM3_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM2_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM2_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM2_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM2_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM1_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM1_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM1_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM1_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM0_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM0_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM0_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM0_SEC_EN,Domain secure permission control enable" "0,1" repeat.end repeat 16. (list 0x30 0x31 0x32 0x33 0x34 0x35 0x36 0x37 0x38 0x39 0x3A 0x3B 0x3C 0x3D 0x3E 0x3F )(list 0x9C0 0x9F4 0xA28 0xA5C 0xA90 0xAC4 0xAF8 0xB2C 0xB60 0xB94 0xBC8 0xBFC 0xC30 0xC64 0xC98 0xCCC ) group.long ($2+0x2408)++0x3 line.long 0x0 "SEC_PER0_$1,This register is only used for resource manager to control secure access permission." bitfld.long 0x0 31. "DOM3_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM3_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM3_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM3_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM2_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM2_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM2_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM2_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM1_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM1_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM1_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM1_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM0_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM0_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM0_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM0_SEC_EN,Domain secure permission control enable" "0,1" repeat.end repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x34 0x68 0x9C 0xD0 0x104 0x138 0x16C 0x1A0 0x1D4 0x208 0x23C 0x270 0x2A4 0x2D8 0x30C ) group.long ($2+0x240C)++0x3 line.long 0x0 "SEC_PER1_$1,This register is only used for resource manager to control secure access permission." bitfld.long 0x0 31. "DOM7_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM7_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM7_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM7_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM6_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM6_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM6_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM6_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM5_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM5_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM5_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM5_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM4_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM4_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM4_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM4_SEC_EN,Domain secure permission control enable" "0,1" repeat.end repeat 16. (list 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1A 0x1B 0x1C 0x1D 0x1E 0x1F )(list 0x340 0x374 0x3A8 0x3DC 0x410 0x444 0x478 0x4AC 0x4E0 0x514 0x548 0x57C 0x5B0 0x5E4 0x618 0x64C ) group.long ($2+0x240C)++0x3 line.long 0x0 "SEC_PER1_$1,This register is only used for resource manager to control secure access permission." bitfld.long 0x0 31. "DOM7_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM7_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM7_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM7_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM6_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM6_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM6_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM6_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM5_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM5_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM5_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM5_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM4_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM4_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM4_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM4_SEC_EN,Domain secure permission control enable" "0,1" repeat.end repeat 16. (list 0x20 0x21 0x22 0x23 0x24 0x25 0x26 0x27 0x28 0x29 0x2A 0x2B 0x2C 0x2D 0x2E 0x2F )(list 0x680 0x6B4 0x6E8 0x71C 0x750 0x784 0x7B8 0x7EC 0x820 0x854 0x888 0x8BC 0x8F0 0x924 0x958 0x98C ) group.long ($2+0x240C)++0x3 line.long 0x0 "SEC_PER1_$1,This register is only used for resource manager to control secure access permission." bitfld.long 0x0 31. "DOM7_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM7_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM7_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM7_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM6_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM6_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM6_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM6_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM5_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM5_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM5_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM5_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM4_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM4_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM4_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM4_SEC_EN,Domain secure permission control enable" "0,1" repeat.end repeat 16. (list 0x30 0x31 0x32 0x33 0x34 0x35 0x36 0x37 0x38 0x39 0x3A 0x3B 0x3C 0x3D 0x3E 0x3F )(list 0x9C0 0x9F4 0xA28 0xA5C 0xA90 0xAC4 0xAF8 0xB2C 0xB60 0xB94 0xBC8 0xBFC 0xC30 0xC64 0xC98 0xCCC ) group.long ($2+0x240C)++0x3 line.long 0x0 "SEC_PER1_$1,This register is only used for resource manager to control secure access permission." bitfld.long 0x0 31. "DOM7_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM7_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM7_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM7_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM6_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM6_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM6_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM6_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM5_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM5_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM5_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM5_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM4_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM4_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM4_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM4_SEC_EN,Domain secure permission control enable" "0,1" repeat.end repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x34 0x68 0x9C 0xD0 0x104 0x138 0x16C 0x1A0 0x1D4 0x208 0x23C 0x270 0x2A4 0x2D8 0x30C ) group.long ($2+0x2410)++0x3 line.long 0x0 "SEC_PER2_$1,This register is only used for resource manager to control secure access permission." bitfld.long 0x0 31. "DOM11_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM11_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM11_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM11_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM10_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM10_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM10_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM10_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM9_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM9_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM9_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM9_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM8_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM8_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM8_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM8_SEC_EN,Domain secure permission control enable" "0,1" repeat.end repeat 16. (list 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1A 0x1B 0x1C 0x1D 0x1E 0x1F )(list 0x340 0x374 0x3A8 0x3DC 0x410 0x444 0x478 0x4AC 0x4E0 0x514 0x548 0x57C 0x5B0 0x5E4 0x618 0x64C ) group.long ($2+0x2410)++0x3 line.long 0x0 "SEC_PER2_$1,This register is only used for resource manager to control secure access permission." bitfld.long 0x0 31. "DOM11_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM11_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM11_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM11_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM10_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM10_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM10_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM10_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM9_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM9_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM9_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM9_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM8_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM8_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM8_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM8_SEC_EN,Domain secure permission control enable" "0,1" repeat.end repeat 16. (list 0x20 0x21 0x22 0x23 0x24 0x25 0x26 0x27 0x28 0x29 0x2A 0x2B 0x2C 0x2D 0x2E 0x2F )(list 0x680 0x6B4 0x6E8 0x71C 0x750 0x784 0x7B8 0x7EC 0x820 0x854 0x888 0x8BC 0x8F0 0x924 0x958 0x98C ) group.long ($2+0x2410)++0x3 line.long 0x0 "SEC_PER2_$1,This register is only used for resource manager to control secure access permission." bitfld.long 0x0 31. "DOM11_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM11_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM11_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM11_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM10_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM10_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM10_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM10_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM9_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM9_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM9_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM9_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM8_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM8_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM8_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM8_SEC_EN,Domain secure permission control enable" "0,1" repeat.end repeat 16. (list 0x30 0x31 0x32 0x33 0x34 0x35 0x36 0x37 0x38 0x39 0x3A 0x3B 0x3C 0x3D 0x3E 0x3F )(list 0x9C0 0x9F4 0xA28 0xA5C 0xA90 0xAC4 0xAF8 0xB2C 0xB60 0xB94 0xBC8 0xBFC 0xC30 0xC64 0xC98 0xCCC ) group.long ($2+0x2410)++0x3 line.long 0x0 "SEC_PER2_$1,This register is only used for resource manager to control secure access permission." bitfld.long 0x0 31. "DOM11_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM11_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM11_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM11_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM10_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM10_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM10_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM10_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM9_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM9_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM9_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM9_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM8_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM8_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM8_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM8_SEC_EN,Domain secure permission control enable" "0,1" repeat.end repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x34 0x68 0x9C 0xD0 0x104 0x138 0x16C 0x1A0 0x1D4 0x208 0x23C 0x270 0x2A4 0x2D8 0x30C ) group.long ($2+0x2414)++0x3 line.long 0x0 "SEC_PER3_$1,This register is only used for resource manager to control secure access permission." bitfld.long 0x0 31. "DOM15_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM15_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM15_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM15_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM14_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM14_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM14_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM14_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM13_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM13_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM13_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM13_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM12_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM12_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM12_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM12_SEC_EN,Domain secure permission control enable" "0,1" repeat.end repeat 16. (list 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1A 0x1B 0x1C 0x1D 0x1E 0x1F )(list 0x340 0x374 0x3A8 0x3DC 0x410 0x444 0x478 0x4AC 0x4E0 0x514 0x548 0x57C 0x5B0 0x5E4 0x618 0x64C ) group.long ($2+0x2414)++0x3 line.long 0x0 "SEC_PER3_$1,This register is only used for resource manager to control secure access permission." bitfld.long 0x0 31. "DOM15_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM15_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM15_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM15_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM14_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM14_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM14_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM14_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM13_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM13_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM13_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM13_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM12_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM12_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM12_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM12_SEC_EN,Domain secure permission control enable" "0,1" repeat.end repeat 16. (list 0x20 0x21 0x22 0x23 0x24 0x25 0x26 0x27 0x28 0x29 0x2A 0x2B 0x2C 0x2D 0x2E 0x2F )(list 0x680 0x6B4 0x6E8 0x71C 0x750 0x784 0x7B8 0x7EC 0x820 0x854 0x888 0x8BC 0x8F0 0x924 0x958 0x98C ) group.long ($2+0x2414)++0x3 line.long 0x0 "SEC_PER3_$1,This register is only used for resource manager to control secure access permission." bitfld.long 0x0 31. "DOM15_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM15_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM15_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM15_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM14_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM14_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM14_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM14_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM13_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM13_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM13_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM13_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM12_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM12_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM12_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM12_SEC_EN,Domain secure permission control enable" "0,1" repeat.end repeat 16. (list 0x30 0x31 0x32 0x33 0x34 0x35 0x36 0x37 0x38 0x39 0x3A 0x3B 0x3C 0x3D 0x3E 0x3F )(list 0x9C0 0x9F4 0xA28 0xA5C 0xA90 0xAC4 0xAF8 0xB2C 0xB60 0xB94 0xBC8 0xBFC 0xC30 0xC64 0xC98 0xCCC ) group.long ($2+0x2414)++0x3 line.long 0x0 "SEC_PER3_$1,This register is only used for resource manager to control secure access permission." bitfld.long 0x0 31. "DOM15_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM15_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM15_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM15_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM14_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM14_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM14_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM14_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM13_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM13_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM13_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM13_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM12_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM12_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM12_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM12_SEC_EN,Domain secure permission control enable" "0,1" repeat.end repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x34 0x68 0x9C 0xD0 0x104 0x138 0x16C 0x1A0 0x1D4 0x208 0x23C 0x270 0x2A4 0x2D8 0x30C ) group.long ($2+0x2418)++0x3 line.long 0x0 "PRI_PER0_$1,This register is only used for resource manager to control privileged access permission." bitfld.long 0x0 31. "DOM3_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM3_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM3_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM3_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM2_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM2_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM2_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM2_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM1_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM1_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM1_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM1_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM0_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM0_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM0_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM0_PRI_EN,Domain privileged permission control enable" "0,1" repeat.end repeat 16. (list 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1A 0x1B 0x1C 0x1D 0x1E 0x1F )(list 0x340 0x374 0x3A8 0x3DC 0x410 0x444 0x478 0x4AC 0x4E0 0x514 0x548 0x57C 0x5B0 0x5E4 0x618 0x64C ) group.long ($2+0x2418)++0x3 line.long 0x0 "PRI_PER0_$1,This register is only used for resource manager to control privileged access permission." bitfld.long 0x0 31. "DOM3_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM3_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM3_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM3_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM2_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM2_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM2_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM2_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM1_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM1_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM1_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM1_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM0_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM0_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM0_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM0_PRI_EN,Domain privileged permission control enable" "0,1" repeat.end repeat 16. (list 0x20 0x21 0x22 0x23 0x24 0x25 0x26 0x27 0x28 0x29 0x2A 0x2B 0x2C 0x2D 0x2E 0x2F )(list 0x680 0x6B4 0x6E8 0x71C 0x750 0x784 0x7B8 0x7EC 0x820 0x854 0x888 0x8BC 0x8F0 0x924 0x958 0x98C ) group.long ($2+0x2418)++0x3 line.long 0x0 "PRI_PER0_$1,This register is only used for resource manager to control privileged access permission." bitfld.long 0x0 31. "DOM3_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM3_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM3_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM3_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM2_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM2_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM2_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM2_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM1_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM1_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM1_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM1_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM0_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM0_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM0_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM0_PRI_EN,Domain privileged permission control enable" "0,1" repeat.end repeat 16. (list 0x30 0x31 0x32 0x33 0x34 0x35 0x36 0x37 0x38 0x39 0x3A 0x3B 0x3C 0x3D 0x3E 0x3F )(list 0x9C0 0x9F4 0xA28 0xA5C 0xA90 0xAC4 0xAF8 0xB2C 0xB60 0xB94 0xBC8 0xBFC 0xC30 0xC64 0xC98 0xCCC ) group.long ($2+0x2418)++0x3 line.long 0x0 "PRI_PER0_$1,This register is only used for resource manager to control privileged access permission." bitfld.long 0x0 31. "DOM3_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM3_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM3_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM3_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM2_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM2_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM2_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM2_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM1_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM1_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM1_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM1_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM0_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM0_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM0_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM0_PRI_EN,Domain privileged permission control enable" "0,1" repeat.end repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x34 0x68 0x9C 0xD0 0x104 0x138 0x16C 0x1A0 0x1D4 0x208 0x23C 0x270 0x2A4 0x2D8 0x30C ) group.long ($2+0x241C)++0x3 line.long 0x0 "PRI_PER1_$1,This register is only used for resource manager to control privileged access permission." bitfld.long 0x0 31. "DOM7_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM7_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM7_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM7_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM6_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM6_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM6_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM6_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM5_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM5_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM5_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM5_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM4_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM4_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM4_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM4_PRI_EN,Domain privileged permission control enable" "0,1" repeat.end repeat 16. (list 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1A 0x1B 0x1C 0x1D 0x1E 0x1F )(list 0x340 0x374 0x3A8 0x3DC 0x410 0x444 0x478 0x4AC 0x4E0 0x514 0x548 0x57C 0x5B0 0x5E4 0x618 0x64C ) group.long ($2+0x241C)++0x3 line.long 0x0 "PRI_PER1_$1,This register is only used for resource manager to control privileged access permission." bitfld.long 0x0 31. "DOM7_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM7_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM7_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM7_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM6_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM6_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM6_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM6_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM5_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM5_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM5_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM5_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM4_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM4_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM4_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM4_PRI_EN,Domain privileged permission control enable" "0,1" repeat.end repeat 16. (list 0x20 0x21 0x22 0x23 0x24 0x25 0x26 0x27 0x28 0x29 0x2A 0x2B 0x2C 0x2D 0x2E 0x2F )(list 0x680 0x6B4 0x6E8 0x71C 0x750 0x784 0x7B8 0x7EC 0x820 0x854 0x888 0x8BC 0x8F0 0x924 0x958 0x98C ) group.long ($2+0x241C)++0x3 line.long 0x0 "PRI_PER1_$1,This register is only used for resource manager to control privileged access permission." bitfld.long 0x0 31. "DOM7_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM7_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM7_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM7_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM6_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM6_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM6_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM6_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM5_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM5_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM5_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM5_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM4_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM4_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM4_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM4_PRI_EN,Domain privileged permission control enable" "0,1" repeat.end repeat 16. (list 0x30 0x31 0x32 0x33 0x34 0x35 0x36 0x37 0x38 0x39 0x3A 0x3B 0x3C 0x3D 0x3E 0x3F )(list 0x9C0 0x9F4 0xA28 0xA5C 0xA90 0xAC4 0xAF8 0xB2C 0xB60 0xB94 0xBC8 0xBFC 0xC30 0xC64 0xC98 0xCCC ) group.long ($2+0x241C)++0x3 line.long 0x0 "PRI_PER1_$1,This register is only used for resource manager to control privileged access permission." bitfld.long 0x0 31. "DOM7_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM7_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM7_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM7_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM6_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM6_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM6_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM6_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM5_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM5_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM5_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM5_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM4_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM4_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM4_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM4_PRI_EN,Domain privileged permission control enable" "0,1" repeat.end repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x34 0x68 0x9C 0xD0 0x104 0x138 0x16C 0x1A0 0x1D4 0x208 0x23C 0x270 0x2A4 0x2D8 0x30C ) group.long ($2+0x2420)++0x3 line.long 0x0 "PRI_PER2_$1,This register is only used for resource manager to control privileged access permission." bitfld.long 0x0 31. "DOM11_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM11_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM11_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM11_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM10_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM10_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM10_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM10_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM9_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM9_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM9_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM9_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM8_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM8_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM8_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM8_PRI_EN,Domain privileged permission control enable" "0,1" repeat.end repeat 16. (list 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1A 0x1B 0x1C 0x1D 0x1E 0x1F )(list 0x340 0x374 0x3A8 0x3DC 0x410 0x444 0x478 0x4AC 0x4E0 0x514 0x548 0x57C 0x5B0 0x5E4 0x618 0x64C ) group.long ($2+0x2420)++0x3 line.long 0x0 "PRI_PER2_$1,This register is only used for resource manager to control privileged access permission." bitfld.long 0x0 31. "DOM11_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM11_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM11_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM11_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM10_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM10_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM10_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM10_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM9_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM9_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM9_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM9_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM8_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM8_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM8_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM8_PRI_EN,Domain privileged permission control enable" "0,1" repeat.end repeat 16. (list 0x20 0x21 0x22 0x23 0x24 0x25 0x26 0x27 0x28 0x29 0x2A 0x2B 0x2C 0x2D 0x2E 0x2F )(list 0x680 0x6B4 0x6E8 0x71C 0x750 0x784 0x7B8 0x7EC 0x820 0x854 0x888 0x8BC 0x8F0 0x924 0x958 0x98C ) group.long ($2+0x2420)++0x3 line.long 0x0 "PRI_PER2_$1,This register is only used for resource manager to control privileged access permission." bitfld.long 0x0 31. "DOM11_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM11_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM11_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM11_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM10_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM10_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM10_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM10_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM9_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM9_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM9_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM9_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM8_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM8_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM8_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM8_PRI_EN,Domain privileged permission control enable" "0,1" repeat.end repeat 16. (list 0x30 0x31 0x32 0x33 0x34 0x35 0x36 0x37 0x38 0x39 0x3A 0x3B 0x3C 0x3D 0x3E 0x3F )(list 0x9C0 0x9F4 0xA28 0xA5C 0xA90 0xAC4 0xAF8 0xB2C 0xB60 0xB94 0xBC8 0xBFC 0xC30 0xC64 0xC98 0xCCC ) group.long ($2+0x2420)++0x3 line.long 0x0 "PRI_PER2_$1,This register is only used for resource manager to control privileged access permission." bitfld.long 0x0 31. "DOM11_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM11_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM11_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM11_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM10_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM10_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM10_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM10_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM9_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM9_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM9_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM9_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM8_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM8_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM8_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM8_PRI_EN,Domain privileged permission control enable" "0,1" repeat.end repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x34 0x68 0x9C 0xD0 0x104 0x138 0x16C 0x1A0 0x1D4 0x208 0x23C 0x270 0x2A4 0x2D8 0x30C ) group.long ($2+0x2424)++0x3 line.long 0x0 "PRI_PER3_$1,This register is only used for resource manager to control privileged access permission." bitfld.long 0x0 31. "DOM15_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM15_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM15_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM15_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM14_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM14_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM14_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM14_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM13_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM13_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM13_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM13_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM12_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM12_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM12_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM12_PRI_EN,Domain privileged permission control enable" "0,1" repeat.end repeat 16. (list 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1A 0x1B 0x1C 0x1D 0x1E 0x1F )(list 0x340 0x374 0x3A8 0x3DC 0x410 0x444 0x478 0x4AC 0x4E0 0x514 0x548 0x57C 0x5B0 0x5E4 0x618 0x64C ) group.long ($2+0x2424)++0x3 line.long 0x0 "PRI_PER3_$1,This register is only used for resource manager to control privileged access permission." bitfld.long 0x0 31. "DOM15_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM15_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM15_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM15_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM14_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM14_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM14_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM14_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM13_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM13_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM13_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM13_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM12_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM12_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM12_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM12_PRI_EN,Domain privileged permission control enable" "0,1" repeat.end repeat 16. (list 0x20 0x21 0x22 0x23 0x24 0x25 0x26 0x27 0x28 0x29 0x2A 0x2B 0x2C 0x2D 0x2E 0x2F )(list 0x680 0x6B4 0x6E8 0x71C 0x750 0x784 0x7B8 0x7EC 0x820 0x854 0x888 0x8BC 0x8F0 0x924 0x958 0x98C ) group.long ($2+0x2424)++0x3 line.long 0x0 "PRI_PER3_$1,This register is only used for resource manager to control privileged access permission." bitfld.long 0x0 31. "DOM15_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM15_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM15_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM15_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM14_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM14_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM14_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM14_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM13_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM13_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM13_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM13_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM12_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM12_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM12_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM12_PRI_EN,Domain privileged permission control enable" "0,1" repeat.end repeat 16. (list 0x30 0x31 0x32 0x33 0x34 0x35 0x36 0x37 0x38 0x39 0x3A 0x3B 0x3C 0x3D 0x3E 0x3F )(list 0x9C0 0x9F4 0xA28 0xA5C 0xA90 0xAC4 0xAF8 0xB2C 0xB60 0xB94 0xBC8 0xBFC 0xC30 0xC64 0xC98 0xCCC ) group.long ($2+0x2424)++0x3 line.long 0x0 "PRI_PER3_$1,This register is only used for resource manager to control privileged access permission." bitfld.long 0x0 31. "DOM15_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM15_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM15_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM15_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM14_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM14_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM14_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM14_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM13_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM13_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM13_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM13_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM12_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM12_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM12_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM12_PRI_EN,Domain privileged permission control enable" "0,1" repeat.end repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x34 0x68 0x9C 0xD0 0x104 0x138 0x16C 0x1A0 0x1D4 0x208 0x23C 0x270 0x2A4 0x2D8 0x30C ) group.long ($2+0x2428)++0x3 line.long 0x0 "DOM_SEC_PER_$1,This register is only used for domain master to control secure access permission. When the domain master write this register. it only changes the secure permission for itself. When the domain master read this register. it gets permission.." bitfld.long 0x0 7. "DOM_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" newline bitfld.long 0x0 0. "DOM_SEC_EN,Domain secure permission control enable" "0,1" repeat.end repeat 16. (list 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1A 0x1B 0x1C 0x1D 0x1E 0x1F )(list 0x340 0x374 0x3A8 0x3DC 0x410 0x444 0x478 0x4AC 0x4E0 0x514 0x548 0x57C 0x5B0 0x5E4 0x618 0x64C ) group.long ($2+0x2428)++0x3 line.long 0x0 "DOM_SEC_PER_$1,This register is only used for domain master to control secure access permission. When the domain master write this register. it only changes the secure permission for itself. When the domain master read this register. it gets permission.." bitfld.long 0x0 7. "DOM_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" newline bitfld.long 0x0 0. "DOM_SEC_EN,Domain secure permission control enable" "0,1" repeat.end repeat 16. (list 0x20 0x21 0x22 0x23 0x24 0x25 0x26 0x27 0x28 0x29 0x2A 0x2B 0x2C 0x2D 0x2E 0x2F )(list 0x680 0x6B4 0x6E8 0x71C 0x750 0x784 0x7B8 0x7EC 0x820 0x854 0x888 0x8BC 0x8F0 0x924 0x958 0x98C ) group.long ($2+0x2428)++0x3 line.long 0x0 "DOM_SEC_PER_$1,This register is only used for domain master to control secure access permission. When the domain master write this register. it only changes the secure permission for itself. When the domain master read this register. it gets permission.." bitfld.long 0x0 7. "DOM_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" newline bitfld.long 0x0 0. "DOM_SEC_EN,Domain secure permission control enable" "0,1" repeat.end repeat 16. (list 0x30 0x31 0x32 0x33 0x34 0x35 0x36 0x37 0x38 0x39 0x3A 0x3B 0x3C 0x3D 0x3E 0x3F )(list 0x9C0 0x9F4 0xA28 0xA5C 0xA90 0xAC4 0xAF8 0xB2C 0xB60 0xB94 0xBC8 0xBFC 0xC30 0xC64 0xC98 0xCCC ) group.long ($2+0x2428)++0x3 line.long 0x0 "DOM_SEC_PER_$1,This register is only used for domain master to control secure access permission. When the domain master write this register. it only changes the secure permission for itself. When the domain master read this register. it gets permission.." bitfld.long 0x0 7. "DOM_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" newline bitfld.long 0x0 0. "DOM_SEC_EN,Domain secure permission control enable" "0,1" repeat.end repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x34 0x68 0x9C 0xD0 0x104 0x138 0x16C 0x1A0 0x1D4 0x208 0x23C 0x270 0x2A4 0x2D8 0x30C ) group.long ($2+0x242C)++0x3 line.long 0x0 "DOM_PRI_PER_$1,This register is only used for domain master to control secure access permission. When the domain master write this register. it only changes the secure permission for itself. When the domain master read this register. it gets permission.." bitfld.long 0x0 7. "DOM_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" newline bitfld.long 0x0 0. "DOM_PRI_EN,Domain privileged permission control enable" "0,1" repeat.end repeat 16. (list 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1A 0x1B 0x1C 0x1D 0x1E 0x1F )(list 0x340 0x374 0x3A8 0x3DC 0x410 0x444 0x478 0x4AC 0x4E0 0x514 0x548 0x57C 0x5B0 0x5E4 0x618 0x64C ) group.long ($2+0x242C)++0x3 line.long 0x0 "DOM_PRI_PER_$1,This register is only used for domain master to control secure access permission. When the domain master write this register. it only changes the secure permission for itself. When the domain master read this register. it gets permission.." bitfld.long 0x0 7. "DOM_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" newline bitfld.long 0x0 0. "DOM_PRI_EN,Domain privileged permission control enable" "0,1" repeat.end repeat 16. (list 0x20 0x21 0x22 0x23 0x24 0x25 0x26 0x27 0x28 0x29 0x2A 0x2B 0x2C 0x2D 0x2E 0x2F )(list 0x680 0x6B4 0x6E8 0x71C 0x750 0x784 0x7B8 0x7EC 0x820 0x854 0x888 0x8BC 0x8F0 0x924 0x958 0x98C ) group.long ($2+0x242C)++0x3 line.long 0x0 "DOM_PRI_PER_$1,This register is only used for domain master to control secure access permission. When the domain master write this register. it only changes the secure permission for itself. When the domain master read this register. it gets permission.." bitfld.long 0x0 7. "DOM_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" newline bitfld.long 0x0 0. "DOM_PRI_EN,Domain privileged permission control enable" "0,1" repeat.end repeat 16. (list 0x30 0x31 0x32 0x33 0x34 0x35 0x36 0x37 0x38 0x39 0x3A 0x3B 0x3C 0x3D 0x3E 0x3F )(list 0x9C0 0x9F4 0xA28 0xA5C 0xA90 0xAC4 0xAF8 0xB2C 0xB60 0xB94 0xBC8 0xBFC 0xC30 0xC64 0xC98 0xCCC ) group.long ($2+0x242C)++0x3 line.long 0x0 "DOM_PRI_PER_$1,This register is only used for domain master to control secure access permission. When the domain master write this register. it only changes the secure permission for itself. When the domain master read this register. it gets permission.." bitfld.long 0x0 7. "DOM_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" newline bitfld.long 0x0 0. "DOM_PRI_EN,Domain privileged permission control enable" "0,1" repeat.end repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x34 0x68 0x9C 0xD0 0x104 0x138 0x16C 0x1A0 0x1D4 0x208 0x23C 0x270 0x2A4 0x2D8 0x30C ) group.long ($2+0x2430)++0x3 line.long 0x0 "DOM_ASSIGN_$1,Use to assign domain for accessing DOM_SEC_PER and DOM_PRI_PER register. Only resource manager. group manager and domain owner can access this register. For write. group manager must write its owen domain ID. otherwise write accessing will.." hexmask.long.byte 0x0 0.--3. 1. "DID,accessing DOM_SEC_PER and DOM_PRI_PER register" repeat.end repeat 16. (list 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1A 0x1B 0x1C 0x1D 0x1E 0x1F )(list 0x340 0x374 0x3A8 0x3DC 0x410 0x444 0x478 0x4AC 0x4E0 0x514 0x548 0x57C 0x5B0 0x5E4 0x618 0x64C ) group.long ($2+0x2430)++0x3 line.long 0x0 "DOM_ASSIGN_$1,Use to assign domain for accessing DOM_SEC_PER and DOM_PRI_PER register. Only resource manager. group manager and domain owner can access this register. For write. group manager must write its owen domain ID. otherwise write accessing will.." hexmask.long.byte 0x0 0.--3. 1. "DID,accessing DOM_SEC_PER and DOM_PRI_PER register" repeat.end repeat 16. (list 0x20 0x21 0x22 0x23 0x24 0x25 0x26 0x27 0x28 0x29 0x2A 0x2B 0x2C 0x2D 0x2E 0x2F )(list 0x680 0x6B4 0x6E8 0x71C 0x750 0x784 0x7B8 0x7EC 0x820 0x854 0x888 0x8BC 0x8F0 0x924 0x958 0x98C ) group.long ($2+0x2430)++0x3 line.long 0x0 "DOM_ASSIGN_$1,Use to assign domain for accessing DOM_SEC_PER and DOM_PRI_PER register. Only resource manager. group manager and domain owner can access this register. For write. group manager must write its owen domain ID. otherwise write accessing will.." hexmask.long.byte 0x0 0.--3. 1. "DID,accessing DOM_SEC_PER and DOM_PRI_PER register" repeat.end repeat 16. (list 0x30 0x31 0x32 0x33 0x34 0x35 0x36 0x37 0x38 0x39 0x3A 0x3B 0x3C 0x3D 0x3E 0x3F )(list 0x9C0 0x9F4 0xA28 0xA5C 0xA90 0xAC4 0xAF8 0xB2C 0xB60 0xB94 0xBC8 0xBFC 0xC30 0xC64 0xC98 0xCCC ) group.long ($2+0x2430)++0x3 line.long 0x0 "DOM_ASSIGN_$1,Use to assign domain for accessing DOM_SEC_PER and DOM_PRI_PER register. Only resource manager. group manager and domain owner can access this register. For write. group manager must write its owen domain ID. otherwise write accessing will.." hexmask.long.byte 0x0 0.--3. 1. "DID,accessing DOM_SEC_PER and DOM_PRI_PER register" repeat.end repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x38 0x70 0xA8 0xE0 0x118 0x150 0x188 0x1C0 0x1F8 0x230 0x268 0x2A0 0x2D8 0x310 0x348 ) group.long ($2+0x3100)++0x3 line.long 0x0 "RGN_DOM_$1,Assign domain for peripheral. It can be only configured by resource and group manager" bitfld.long 0x0 31. "LOCK,When this bit is set lock write for all the bits in the register." "0,1" bitfld.long 0x0 4. "SET,Set together with DID would change permission of this resource to following setting: 1) Domain access control enabled. 2) Read/Write allowed for the domain owner. 3) Read/Write not allowed for all the other domains. If this bit is not set only DID.." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Assign domain for peripheral" repeat.end repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x38 0x70 0xA8 0xE0 0x118 0x150 0x188 0x1C0 0x1F8 0x230 0x268 0x2A0 0x2D8 0x310 0x348 ) group.long ($2+0x3104)++0x3 line.long 0x0 "RGN_DOM_PER0_$1,Domain Permission Control. It can be only configured by resource manager and domain owner." bitfld.long 0x0 31. "DOM7_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 29.--30. "DOM7_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 28. "DOM7_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 27. "DOM6_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 25.--26. "DOM6_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" newline bitfld.long 0x0 24. "DOM6_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 23. "DOM5_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 21.--22. "DOM5_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 20. "DOM5_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 19. "DOM4_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" newline bitfld.long 0x0 17.--18. "DOM4_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM4_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 15. "DOM3_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 13.--14. "DOM3_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 12. "DOM3_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" newline bitfld.long 0x0 11. "DOM2_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 9.--10. "DOM2_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM2_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 7. "DOM1_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 5.--6. "DOM1_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" newline bitfld.long 0x0 4. "DOM1_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 3. "DOM0_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 1.--2. "DOM0_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM0_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" repeat.end repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x38 0x70 0xA8 0xE0 0x118 0x150 0x188 0x1C0 0x1F8 0x230 0x268 0x2A0 0x2D8 0x310 0x348 ) group.long ($2+0x3108)++0x3 line.long 0x0 "RGN_DOM_PER1_$1,Domain Permission Control. It can be only configured by resource manager and domain owner." bitfld.long 0x0 31. "DOM15_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 29.--30. "DOM15_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 28. "DOM15_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 27. "DOM14_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 25.--26. "DOM14_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" newline bitfld.long 0x0 24. "DOM14_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 23. "DOM13_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 21.--22. "DOM13_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 20. "DOM13_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 19. "DOM12_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" newline bitfld.long 0x0 17.--18. "DOM12_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM12_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 15. "DOM11_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 13.--14. "DOM11_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 12. "DOM11_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" newline bitfld.long 0x0 11. "DOM10_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 9.--10. "DOM10_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM10_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 7. "DOM9_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 5.--6. "DOM9_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" newline bitfld.long 0x0 4. "DOM9_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 3. "DOM8_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 1.--2. "DOM8_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM8_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" repeat.end repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x38 0x70 0xA8 0xE0 0x118 0x150 0x188 0x1C0 0x1F8 0x230 0x268 0x2A0 0x2D8 0x310 0x348 ) group.long ($2+0x310C)++0x3 line.long 0x0 "RGN_SEC_PER0_$1,This register is only used for resource manager to control secure access permission." bitfld.long 0x0 31. "DOM3_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM3_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM3_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM3_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM2_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM2_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM2_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM2_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM1_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM1_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM1_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM1_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM0_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM0_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM0_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM0_SEC_EN,Domain secure permission control enable" "0,1" repeat.end repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x38 0x70 0xA8 0xE0 0x118 0x150 0x188 0x1C0 0x1F8 0x230 0x268 0x2A0 0x2D8 0x310 0x348 ) group.long ($2+0x3110)++0x3 line.long 0x0 "RGN_SEC_PER1_$1,This register is only used for resource manager to control secure access permission." bitfld.long 0x0 31. "DOM7_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM7_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM7_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM7_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM6_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM6_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM6_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM6_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM5_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM5_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM5_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM5_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM4_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM4_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM4_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM4_SEC_EN,Domain secure permission control enable" "0,1" repeat.end repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x38 0x70 0xA8 0xE0 0x118 0x150 0x188 0x1C0 0x1F8 0x230 0x268 0x2A0 0x2D8 0x310 0x348 ) group.long ($2+0x3114)++0x3 line.long 0x0 "RGN_SEC_PER2_$1,This register is only used for resource manager to control secure access permission." bitfld.long 0x0 31. "DOM11_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM11_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM11_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM11_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM10_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM10_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM10_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM10_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM9_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM9_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM9_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM9_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM8_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM8_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM8_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM8_SEC_EN,Domain secure permission control enable" "0,1" repeat.end repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x38 0x70 0xA8 0xE0 0x118 0x150 0x188 0x1C0 0x1F8 0x230 0x268 0x2A0 0x2D8 0x310 0x348 ) group.long ($2+0x3118)++0x3 line.long 0x0 "RGN_SEC_PER3_$1,This register is only used for resource manager to control secure access permission." bitfld.long 0x0 31. "DOM15_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM15_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM15_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM15_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM14_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM14_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM14_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM14_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM13_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM13_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM13_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM13_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM12_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM12_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM12_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM12_SEC_EN,Domain secure permission control enable" "0,1" repeat.end repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x38 0x70 0xA8 0xE0 0x118 0x150 0x188 0x1C0 0x1F8 0x230 0x268 0x2A0 0x2D8 0x310 0x348 ) group.long ($2+0x311C)++0x3 line.long 0x0 "RGN_PRI_PER0_$1,This register is only used for resource manager to control privileged access permission." bitfld.long 0x0 31. "DOM3_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM3_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM3_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM3_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM2_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM2_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM2_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM2_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM1_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM1_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM1_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM1_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM0_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM0_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM0_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM0_PRI_EN,Domain privileged permission control enable" "0,1" repeat.end repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x38 0x70 0xA8 0xE0 0x118 0x150 0x188 0x1C0 0x1F8 0x230 0x268 0x2A0 0x2D8 0x310 0x348 ) group.long ($2+0x3120)++0x3 line.long 0x0 "RGN_PRI_PER1_$1,This register is only used for resource manager to control privileged access permission." bitfld.long 0x0 31. "DOM7_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM7_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM7_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM7_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM6_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM6_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM6_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM6_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM5_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM5_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM5_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM5_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM4_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM4_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM4_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM4_PRI_EN,Domain privileged permission control enable" "0,1" repeat.end repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x38 0x70 0xA8 0xE0 0x118 0x150 0x188 0x1C0 0x1F8 0x230 0x268 0x2A0 0x2D8 0x310 0x348 ) group.long ($2+0x3124)++0x3 line.long 0x0 "RGN_PRI_PER2_$1,This register is only used for resource manager to control privileged access permission." bitfld.long 0x0 31. "DOM11_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM11_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM11_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM11_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM10_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM10_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM10_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM10_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM9_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM9_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM9_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM9_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM8_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM8_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM8_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM8_PRI_EN,Domain privileged permission control enable" "0,1" repeat.end repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x38 0x70 0xA8 0xE0 0x118 0x150 0x188 0x1C0 0x1F8 0x230 0x268 0x2A0 0x2D8 0x310 0x348 ) group.long ($2+0x3128)++0x3 line.long 0x0 "RGN_PRI_PER3_$1,This register is only used for resource manager to control privileged access permission." bitfld.long 0x0 31. "DOM15_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM15_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM15_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM15_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM14_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM14_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM14_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM14_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM13_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM13_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM13_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM13_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM12_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM12_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM12_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM12_PRI_EN,Domain privileged permission control enable" "0,1" repeat.end repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x38 0x70 0xA8 0xE0 0x118 0x150 0x188 0x1C0 0x1F8 0x230 0x268 0x2A0 0x2D8 0x310 0x348 ) group.long ($2+0x312C)++0x3 line.long 0x0 "RGN_DOM_SEC_PER_$1,This register is only used for domain master to control secure access permission. When the domain master write this register. it only changes the secure permission for itself. When the domain master read this register. it gets.." bitfld.long 0x0 7. "DOM_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" newline bitfld.long 0x0 0. "DOM_SEC_EN,Domain secure permission control enable" "0,1" repeat.end repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x38 0x70 0xA8 0xE0 0x118 0x150 0x188 0x1C0 0x1F8 0x230 0x268 0x2A0 0x2D8 0x310 0x348 ) group.long ($2+0x3130)++0x3 line.long 0x0 "RGN_DOM_PRI_PER_$1,This register is only used for domain master to control secure access permission. When the domain master write this register. it only changes the secure permission for itself. When the domain master read this register. it gets.." bitfld.long 0x0 7. "DOM_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" newline bitfld.long 0x0 0. "DOM_PRI_EN,Domain privileged permission control enable" "0,1" repeat.end repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x38 0x70 0xA8 0xE0 0x118 0x150 0x188 0x1C0 0x1F8 0x230 0x268 0x2A0 0x2D8 0x310 0x348 ) group.long ($2+0x3134)++0x3 line.long 0x0 "RGN_DOM_ASSIGN_$1,Use to assign domain for accessing DOM_SEC_PER and DOM_PRI_PER register. Only resource manager. group manager and domain owner can access this register. For write. group manager must write its owen domain ID. otherwise write accessing.." hexmask.long.byte 0x0 0.--3. 1. "DID,accessing DOM_SEC_PER and DOM_PRI_PER register" repeat.end tree.end tree "RPC_SAFETY_CLKGEN" base ad:0xFC800000 repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x4 0x8 0xC 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C ) group.long ($2)++0x3 line.long 0x0 "REGG0_DOM_$1,Assign domain for CKGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1A 0x1B 0x1C 0x1D 0x1E 0x1F )(list 0x40 0x44 0x48 0x4C 0x50 0x54 0x58 0x5C 0x60 0x64 0x68 0x6C 0x70 0x74 0x78 0x7C ) group.long ($2)++0x3 line.long 0x0 "REGG0_DOM_$1,Assign domain for CKGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x20 0x21 0x22 0x23 0x24 0x25 0x26 0x27 0x28 0x29 0x2A 0x2B 0x2C 0x2D 0x2E 0x2F )(list 0x80 0x84 0x88 0x8C 0x90 0x94 0x98 0x9C 0xA0 0xA4 0xA8 0xAC 0xB0 0xB4 0xB8 0xBC ) group.long ($2)++0x3 line.long 0x0 "REGG0_DOM_$1,Assign domain for CKGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x30 0x31 0x32 0x33 0x34 0x35 0x36 0x37 0x38 0x39 0x3A 0x3B 0x3C 0x3D 0x3E 0x3F )(list 0xC0 0xC4 0xC8 0xCC 0xD0 0xD4 0xD8 0xDC 0xE0 0xE4 0xE8 0xEC 0xF0 0xF4 0xF8 0xFC ) group.long ($2)++0x3 line.long 0x0 "REGG0_DOM_$1,Assign domain for CKGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x40 0x41 0x42 0x43 0x44 0x45 0x46 0x47 0x48 0x49 0x4A 0x4B 0x4C 0x4D 0x4E 0x4F )(list 0x100 0x104 0x108 0x10C 0x110 0x114 0x118 0x11C 0x120 0x124 0x128 0x12C 0x130 0x134 0x138 0x13C ) group.long ($2)++0x3 line.long 0x0 "REGG0_DOM_$1,Assign domain for CKGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x50 0x51 0x52 0x53 0x54 0x55 0x56 0x57 0x58 0x59 0x5A 0x5B 0x5C 0x5D 0x5E 0x5F )(list 0x140 0x144 0x148 0x14C 0x150 0x154 0x158 0x15C 0x160 0x164 0x168 0x16C 0x170 0x174 0x178 0x17C ) group.long ($2)++0x3 line.long 0x0 "REGG0_DOM_$1,Assign domain for CKGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x60 0x61 0x62 0x63 0x64 0x65 0x66 0x67 0x68 0x69 0x6A 0x6B 0x6C 0x6D 0x6E 0x6F )(list 0x180 0x184 0x188 0x18C 0x190 0x194 0x198 0x19C 0x1A0 0x1A4 0x1A8 0x1AC 0x1B0 0x1B4 0x1B8 0x1BC ) group.long ($2)++0x3 line.long 0x0 "REGG0_DOM_$1,Assign domain for CKGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x70 0x71 0x72 0x73 0x74 0x75 0x76 0x77 0x78 0x79 0x7A 0x7B 0x7C 0x7D 0x7E 0x7F )(list 0x1C0 0x1C4 0x1C8 0x1CC 0x1D0 0x1D4 0x1D8 0x1DC 0x1E0 0x1E4 0x1E8 0x1EC 0x1F0 0x1F4 0x1F8 0x1FC ) group.long ($2)++0x3 line.long 0x0 "REGG0_DOM_$1,Assign domain for CKGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x80 0x81 0x82 0x83 0x84 0x85 0x86 0x87 0x88 0x89 0x8A 0x8B 0x8C 0x8D 0x8E 0x8F )(list 0x200 0x204 0x208 0x20C 0x210 0x214 0x218 0x21C 0x220 0x224 0x228 0x22C 0x230 0x234 0x238 0x23C ) group.long ($2)++0x3 line.long 0x0 "REGG0_DOM_$1,Assign domain for CKGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x90 0x91 0x92 0x93 0x94 0x95 0x96 0x97 0x98 0x99 0x9A 0x9B 0x9C 0x9D 0x9E 0x9F )(list 0x240 0x244 0x248 0x24C 0x250 0x254 0x258 0x25C 0x260 0x264 0x268 0x26C 0x270 0x274 0x278 0x27C ) group.long ($2)++0x3 line.long 0x0 "REGG0_DOM_$1,Assign domain for CKGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xA0 0xA1 0xA2 0xA3 0xA4 0xA5 0xA6 0xA7 0xA8 0xA9 0xAA 0xAB 0xAC 0xAD 0xAE 0xAF )(list 0x280 0x284 0x288 0x28C 0x290 0x294 0x298 0x29C 0x2A0 0x2A4 0x2A8 0x2AC 0x2B0 0x2B4 0x2B8 0x2BC ) group.long ($2)++0x3 line.long 0x0 "REGG0_DOM_$1,Assign domain for CKGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xB0 0xB1 0xB2 0xB3 0xB4 0xB5 0xB6 0xB7 0xB8 0xB9 0xBA 0xBB 0xBC 0xBD 0xBE 0xBF )(list 0x2C0 0x2C4 0x2C8 0x2CC 0x2D0 0x2D4 0x2D8 0x2DC 0x2E0 0x2E4 0x2E8 0x2EC 0x2F0 0x2F4 0x2F8 0x2FC ) group.long ($2)++0x3 line.long 0x0 "REGG0_DOM_$1,Assign domain for CKGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xC0 0xC1 0xC2 0xC3 0xC4 0xC5 0xC6 0xC7 0xC8 0xC9 0xCA 0xCB 0xCC 0xCD 0xCE 0xCF )(list 0x300 0x304 0x308 0x30C 0x310 0x314 0x318 0x31C 0x320 0x324 0x328 0x32C 0x330 0x334 0x338 0x33C ) group.long ($2)++0x3 line.long 0x0 "REGG0_DOM_$1,Assign domain for CKGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xD0 0xD1 0xD2 0xD3 0xD4 0xD5 0xD6 0xD7 0xD8 0xD9 0xDA 0xDB 0xDC 0xDD 0xDE 0xDF )(list 0x340 0x344 0x348 0x34C 0x350 0x354 0x358 0x35C 0x360 0x364 0x368 0x36C 0x370 0x374 0x378 0x37C ) group.long ($2)++0x3 line.long 0x0 "REGG0_DOM_$1,Assign domain for CKGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xE0 0xE1 0xE2 0xE3 0xE4 0xE5 0xE6 0xE7 0xE8 0xE9 0xEA 0xEB 0xEC 0xED 0xEE 0xEF )(list 0x380 0x384 0x388 0x38C 0x390 0x394 0x398 0x39C 0x3A0 0x3A4 0x3A8 0x3AC 0x3B0 0x3B4 0x3B8 0x3BC ) group.long ($2)++0x3 line.long 0x0 "REGG0_DOM_$1,Assign domain for CKGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xF0 0xF1 0xF2 0xF3 0xF4 0xF5 0xF6 0xF7 0xF8 0xF9 0xFA 0xFB 0xFC 0xFD 0xFE 0xFF )(list 0x3C0 0x3C4 0x3C8 0x3CC 0x3D0 0x3D4 0x3D8 0x3DC 0x3E0 0x3E4 0x3E8 0x3EC 0x3F0 0x3F4 0x3F8 0x3FC ) group.long ($2)++0x3 line.long 0x0 "REGG0_DOM_$1,Assign domain for CKGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x4 0x8 0xC 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C ) group.long ($2+0x400)++0x3 line.long 0x0 "REGG1_DOM_$1,Assign domain for CKGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1A 0x1B 0x1C 0x1D 0x1E 0x1F )(list 0x40 0x44 0x48 0x4C 0x50 0x54 0x58 0x5C 0x60 0x64 0x68 0x6C 0x70 0x74 0x78 0x7C ) group.long ($2+0x400)++0x3 line.long 0x0 "REGG1_DOM_$1,Assign domain for CKGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x20 0x21 0x22 0x23 0x24 0x25 0x26 0x27 0x28 0x29 0x2A 0x2B 0x2C 0x2D 0x2E 0x2F )(list 0x80 0x84 0x88 0x8C 0x90 0x94 0x98 0x9C 0xA0 0xA4 0xA8 0xAC 0xB0 0xB4 0xB8 0xBC ) group.long ($2+0x400)++0x3 line.long 0x0 "REGG1_DOM_$1,Assign domain for CKGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x30 0x31 0x32 0x33 0x34 0x35 0x36 0x37 0x38 0x39 0x3A 0x3B 0x3C 0x3D 0x3E 0x3F )(list 0xC0 0xC4 0xC8 0xCC 0xD0 0xD4 0xD8 0xDC 0xE0 0xE4 0xE8 0xEC 0xF0 0xF4 0xF8 0xFC ) group.long ($2+0x400)++0x3 line.long 0x0 "REGG1_DOM_$1,Assign domain for CKGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x40 0x41 0x42 0x43 0x44 0x45 0x46 0x47 0x48 0x49 0x4A 0x4B 0x4C 0x4D 0x4E 0x4F )(list 0x100 0x104 0x108 0x10C 0x110 0x114 0x118 0x11C 0x120 0x124 0x128 0x12C 0x130 0x134 0x138 0x13C ) group.long ($2+0x400)++0x3 line.long 0x0 "REGG1_DOM_$1,Assign domain for CKGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x50 0x51 0x52 0x53 0x54 0x55 0x56 0x57 0x58 0x59 0x5A 0x5B 0x5C 0x5D 0x5E 0x5F )(list 0x140 0x144 0x148 0x14C 0x150 0x154 0x158 0x15C 0x160 0x164 0x168 0x16C 0x170 0x174 0x178 0x17C ) group.long ($2+0x400)++0x3 line.long 0x0 "REGG1_DOM_$1,Assign domain for CKGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x60 0x61 0x62 0x63 0x64 0x65 0x66 0x67 0x68 0x69 0x6A 0x6B 0x6C 0x6D 0x6E 0x6F )(list 0x180 0x184 0x188 0x18C 0x190 0x194 0x198 0x19C 0x1A0 0x1A4 0x1A8 0x1AC 0x1B0 0x1B4 0x1B8 0x1BC ) group.long ($2+0x400)++0x3 line.long 0x0 "REGG1_DOM_$1,Assign domain for CKGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x70 0x71 0x72 0x73 0x74 0x75 0x76 0x77 0x78 0x79 0x7A 0x7B 0x7C 0x7D 0x7E 0x7F )(list 0x1C0 0x1C4 0x1C8 0x1CC 0x1D0 0x1D4 0x1D8 0x1DC 0x1E0 0x1E4 0x1E8 0x1EC 0x1F0 0x1F4 0x1F8 0x1FC ) group.long ($2+0x400)++0x3 line.long 0x0 "REGG1_DOM_$1,Assign domain for CKGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x80 0x81 0x82 0x83 0x84 0x85 0x86 0x87 0x88 0x89 0x8A 0x8B 0x8C 0x8D 0x8E 0x8F )(list 0x200 0x204 0x208 0x20C 0x210 0x214 0x218 0x21C 0x220 0x224 0x228 0x22C 0x230 0x234 0x238 0x23C ) group.long ($2+0x400)++0x3 line.long 0x0 "REGG1_DOM_$1,Assign domain for CKGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x90 0x91 0x92 0x93 0x94 0x95 0x96 0x97 0x98 0x99 0x9A 0x9B 0x9C 0x9D 0x9E 0x9F )(list 0x240 0x244 0x248 0x24C 0x250 0x254 0x258 0x25C 0x260 0x264 0x268 0x26C 0x270 0x274 0x278 0x27C ) group.long ($2+0x400)++0x3 line.long 0x0 "REGG1_DOM_$1,Assign domain for CKGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xA0 0xA1 0xA2 0xA3 0xA4 0xA5 0xA6 0xA7 0xA8 0xA9 0xAA 0xAB 0xAC 0xAD 0xAE 0xAF )(list 0x280 0x284 0x288 0x28C 0x290 0x294 0x298 0x29C 0x2A0 0x2A4 0x2A8 0x2AC 0x2B0 0x2B4 0x2B8 0x2BC ) group.long ($2+0x400)++0x3 line.long 0x0 "REGG1_DOM_$1,Assign domain for CKGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xB0 0xB1 0xB2 0xB3 0xB4 0xB5 0xB6 0xB7 0xB8 0xB9 0xBA 0xBB 0xBC 0xBD 0xBE 0xBF )(list 0x2C0 0x2C4 0x2C8 0x2CC 0x2D0 0x2D4 0x2D8 0x2DC 0x2E0 0x2E4 0x2E8 0x2EC 0x2F0 0x2F4 0x2F8 0x2FC ) group.long ($2+0x400)++0x3 line.long 0x0 "REGG1_DOM_$1,Assign domain for CKGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xC0 0xC1 0xC2 0xC3 0xC4 0xC5 0xC6 0xC7 0xC8 0xC9 0xCA 0xCB 0xCC 0xCD 0xCE 0xCF )(list 0x300 0x304 0x308 0x30C 0x310 0x314 0x318 0x31C 0x320 0x324 0x328 0x32C 0x330 0x334 0x338 0x33C ) group.long ($2+0x400)++0x3 line.long 0x0 "REGG1_DOM_$1,Assign domain for CKGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xD0 0xD1 0xD2 0xD3 0xD4 0xD5 0xD6 0xD7 0xD8 0xD9 0xDA 0xDB 0xDC 0xDD 0xDE 0xDF )(list 0x340 0x344 0x348 0x34C 0x350 0x354 0x358 0x35C 0x360 0x364 0x368 0x36C 0x370 0x374 0x378 0x37C ) group.long ($2+0x400)++0x3 line.long 0x0 "REGG1_DOM_$1,Assign domain for CKGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xE0 0xE1 0xE2 0xE3 0xE4 0xE5 0xE6 0xE7 0xE8 0xE9 0xEA 0xEB 0xEC 0xED 0xEE 0xEF )(list 0x380 0x384 0x388 0x38C 0x390 0x394 0x398 0x39C 0x3A0 0x3A4 0x3A8 0x3AC 0x3B0 0x3B4 0x3B8 0x3BC ) group.long ($2+0x400)++0x3 line.long 0x0 "REGG1_DOM_$1,Assign domain for CKGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xF0 0xF1 0xF2 0xF3 0xF4 0xF5 0xF6 0xF7 0xF8 0xF9 0xFA 0xFB 0xFC 0xFD 0xFE 0xFF )(list 0x3C0 0x3C4 0x3C8 0x3CC 0x3D0 0x3D4 0x3D8 0x3DC 0x3E0 0x3E4 0x3E8 0x3EC 0x3F0 0x3F4 0x3F8 0x3FC ) group.long ($2+0x400)++0x3 line.long 0x0 "REGG1_DOM_$1,Assign domain for CKGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x4 0x8 0xC 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C ) group.long ($2+0x800)++0x3 line.long 0x0 "REGG2_DOM_$1,Assign domain for SCR registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1A 0x1B 0x1C 0x1D 0x1E 0x1F )(list 0x40 0x44 0x48 0x4C 0x50 0x54 0x58 0x5C 0x60 0x64 0x68 0x6C 0x70 0x74 0x78 0x7C ) group.long ($2+0x800)++0x3 line.long 0x0 "REGG2_DOM_$1,Assign domain for SCR registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x20 0x21 0x22 0x23 0x24 0x25 0x26 0x27 0x28 0x29 0x2A 0x2B 0x2C 0x2D 0x2E 0x2F )(list 0x80 0x84 0x88 0x8C 0x90 0x94 0x98 0x9C 0xA0 0xA4 0xA8 0xAC 0xB0 0xB4 0xB8 0xBC ) group.long ($2+0x800)++0x3 line.long 0x0 "REGG2_DOM_$1,Assign domain for SCR registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x30 0x31 0x32 0x33 0x34 0x35 0x36 0x37 0x38 0x39 0x3A 0x3B 0x3C 0x3D 0x3E 0x3F )(list 0xC0 0xC4 0xC8 0xCC 0xD0 0xD4 0xD8 0xDC 0xE0 0xE4 0xE8 0xEC 0xF0 0xF4 0xF8 0xFC ) group.long ($2+0x800)++0x3 line.long 0x0 "REGG2_DOM_$1,Assign domain for SCR registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x40 0x41 0x42 0x43 0x44 0x45 0x46 0x47 0x48 0x49 0x4A 0x4B 0x4C 0x4D 0x4E 0x4F )(list 0x100 0x104 0x108 0x10C 0x110 0x114 0x118 0x11C 0x120 0x124 0x128 0x12C 0x130 0x134 0x138 0x13C ) group.long ($2+0x800)++0x3 line.long 0x0 "REGG2_DOM_$1,Assign domain for SCR registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x50 0x51 0x52 0x53 0x54 0x55 0x56 0x57 0x58 0x59 0x5A 0x5B 0x5C 0x5D 0x5E 0x5F )(list 0x140 0x144 0x148 0x14C 0x150 0x154 0x158 0x15C 0x160 0x164 0x168 0x16C 0x170 0x174 0x178 0x17C ) group.long ($2+0x800)++0x3 line.long 0x0 "REGG2_DOM_$1,Assign domain for SCR registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x60 0x61 0x62 0x63 0x64 0x65 0x66 0x67 0x68 0x69 0x6A 0x6B 0x6C 0x6D 0x6E 0x6F )(list 0x180 0x184 0x188 0x18C 0x190 0x194 0x198 0x19C 0x1A0 0x1A4 0x1A8 0x1AC 0x1B0 0x1B4 0x1B8 0x1BC ) group.long ($2+0x800)++0x3 line.long 0x0 "REGG2_DOM_$1,Assign domain for SCR registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x70 0x71 0x72 0x73 0x74 0x75 0x76 0x77 0x78 0x79 0x7A 0x7B 0x7C 0x7D 0x7E 0x7F )(list 0x1C0 0x1C4 0x1C8 0x1CC 0x1D0 0x1D4 0x1D8 0x1DC 0x1E0 0x1E4 0x1E8 0x1EC 0x1F0 0x1F4 0x1F8 0x1FC ) group.long ($2+0x800)++0x3 line.long 0x0 "REGG2_DOM_$1,Assign domain for SCR registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x80 0x81 0x82 0x83 0x84 0x85 0x86 0x87 0x88 0x89 0x8A 0x8B 0x8C 0x8D 0x8E 0x8F )(list 0x200 0x204 0x208 0x20C 0x210 0x214 0x218 0x21C 0x220 0x224 0x228 0x22C 0x230 0x234 0x238 0x23C ) group.long ($2+0x800)++0x3 line.long 0x0 "REGG2_DOM_$1,Assign domain for SCR registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x90 0x91 0x92 0x93 0x94 0x95 0x96 0x97 0x98 0x99 0x9A 0x9B 0x9C 0x9D 0x9E 0x9F )(list 0x240 0x244 0x248 0x24C 0x250 0x254 0x258 0x25C 0x260 0x264 0x268 0x26C 0x270 0x274 0x278 0x27C ) group.long ($2+0x800)++0x3 line.long 0x0 "REGG2_DOM_$1,Assign domain for SCR registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xA0 0xA1 0xA2 0xA3 0xA4 0xA5 0xA6 0xA7 0xA8 0xA9 0xAA 0xAB 0xAC 0xAD 0xAE 0xAF )(list 0x280 0x284 0x288 0x28C 0x290 0x294 0x298 0x29C 0x2A0 0x2A4 0x2A8 0x2AC 0x2B0 0x2B4 0x2B8 0x2BC ) group.long ($2+0x800)++0x3 line.long 0x0 "REGG2_DOM_$1,Assign domain for SCR registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xB0 0xB1 0xB2 0xB3 0xB4 0xB5 0xB6 0xB7 0xB8 0xB9 0xBA 0xBB 0xBC 0xBD 0xBE 0xBF )(list 0x2C0 0x2C4 0x2C8 0x2CC 0x2D0 0x2D4 0x2D8 0x2DC 0x2E0 0x2E4 0x2E8 0x2EC 0x2F0 0x2F4 0x2F8 0x2FC ) group.long ($2+0x800)++0x3 line.long 0x0 "REGG2_DOM_$1,Assign domain for SCR registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xC0 0xC1 0xC2 0xC3 0xC4 0xC5 0xC6 0xC7 0xC8 0xC9 0xCA 0xCB 0xCC 0xCD 0xCE 0xCF )(list 0x300 0x304 0x308 0x30C 0x310 0x314 0x318 0x31C 0x320 0x324 0x328 0x32C 0x330 0x334 0x338 0x33C ) group.long ($2+0x800)++0x3 line.long 0x0 "REGG2_DOM_$1,Assign domain for SCR registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xD0 0xD1 0xD2 0xD3 0xD4 0xD5 0xD6 0xD7 0xD8 0xD9 0xDA 0xDB 0xDC 0xDD 0xDE 0xDF )(list 0x340 0x344 0x348 0x34C 0x350 0x354 0x358 0x35C 0x360 0x364 0x368 0x36C 0x370 0x374 0x378 0x37C ) group.long ($2+0x800)++0x3 line.long 0x0 "REGG2_DOM_$1,Assign domain for SCR registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xE0 0xE1 0xE2 0xE3 0xE4 0xE5 0xE6 0xE7 0xE8 0xE9 0xEA 0xEB 0xEC 0xED 0xEE 0xEF )(list 0x380 0x384 0x388 0x38C 0x390 0x394 0x398 0x39C 0x3A0 0x3A4 0x3A8 0x3AC 0x3B0 0x3B4 0x3B8 0x3BC ) group.long ($2+0x800)++0x3 line.long 0x0 "REGG2_DOM_$1,Assign domain for SCR registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xF0 0xF1 0xF2 0xF3 0xF4 0xF5 0xF6 0xF7 0xF8 0xF9 0xFA 0xFB 0xFC 0xFD 0xFE 0xFF )(list 0x3C0 0x3C4 0x3C8 0x3CC 0x3D0 0x3D4 0x3D8 0x3DC 0x3E0 0x3E4 0x3E8 0x3EC 0x3F0 0x3F4 0x3F8 0x3FC ) group.long ($2+0x800)++0x3 line.long 0x0 "REGG2_DOM_$1,Assign domain for SCR registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x4 0x8 0xC 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C ) group.long ($2+0xC00)++0x3 line.long 0x0 "REGG3_DOM_$1,Assign domain for SCR registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1A 0x1B 0x1C 0x1D 0x1E 0x1F )(list 0x40 0x44 0x48 0x4C 0x50 0x54 0x58 0x5C 0x60 0x64 0x68 0x6C 0x70 0x74 0x78 0x7C ) group.long ($2+0xC00)++0x3 line.long 0x0 "REGG3_DOM_$1,Assign domain for SCR registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x20 0x21 0x22 0x23 0x24 0x25 0x26 0x27 0x28 0x29 0x2A 0x2B 0x2C 0x2D 0x2E 0x2F )(list 0x80 0x84 0x88 0x8C 0x90 0x94 0x98 0x9C 0xA0 0xA4 0xA8 0xAC 0xB0 0xB4 0xB8 0xBC ) group.long ($2+0xC00)++0x3 line.long 0x0 "REGG3_DOM_$1,Assign domain for SCR registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x30 0x31 0x32 0x33 0x34 0x35 0x36 0x37 0x38 0x39 0x3A 0x3B 0x3C 0x3D 0x3E 0x3F )(list 0xC0 0xC4 0xC8 0xCC 0xD0 0xD4 0xD8 0xDC 0xE0 0xE4 0xE8 0xEC 0xF0 0xF4 0xF8 0xFC ) group.long ($2+0xC00)++0x3 line.long 0x0 "REGG3_DOM_$1,Assign domain for SCR registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x40 0x41 0x42 0x43 0x44 0x45 0x46 0x47 0x48 0x49 0x4A 0x4B 0x4C 0x4D 0x4E 0x4F )(list 0x100 0x104 0x108 0x10C 0x110 0x114 0x118 0x11C 0x120 0x124 0x128 0x12C 0x130 0x134 0x138 0x13C ) group.long ($2+0xC00)++0x3 line.long 0x0 "REGG3_DOM_$1,Assign domain for SCR registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x50 0x51 0x52 0x53 0x54 0x55 0x56 0x57 0x58 0x59 0x5A 0x5B 0x5C 0x5D 0x5E 0x5F )(list 0x140 0x144 0x148 0x14C 0x150 0x154 0x158 0x15C 0x160 0x164 0x168 0x16C 0x170 0x174 0x178 0x17C ) group.long ($2+0xC00)++0x3 line.long 0x0 "REGG3_DOM_$1,Assign domain for SCR registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x60 0x61 0x62 0x63 0x64 0x65 0x66 0x67 0x68 0x69 0x6A 0x6B 0x6C 0x6D 0x6E 0x6F )(list 0x180 0x184 0x188 0x18C 0x190 0x194 0x198 0x19C 0x1A0 0x1A4 0x1A8 0x1AC 0x1B0 0x1B4 0x1B8 0x1BC ) group.long ($2+0xC00)++0x3 line.long 0x0 "REGG3_DOM_$1,Assign domain for SCR registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x70 0x71 0x72 0x73 0x74 0x75 0x76 0x77 0x78 0x79 0x7A 0x7B 0x7C 0x7D 0x7E 0x7F )(list 0x1C0 0x1C4 0x1C8 0x1CC 0x1D0 0x1D4 0x1D8 0x1DC 0x1E0 0x1E4 0x1E8 0x1EC 0x1F0 0x1F4 0x1F8 0x1FC ) group.long ($2+0xC00)++0x3 line.long 0x0 "REGG3_DOM_$1,Assign domain for SCR registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x80 0x81 0x82 0x83 0x84 0x85 0x86 0x87 0x88 0x89 0x8A 0x8B 0x8C 0x8D 0x8E 0x8F )(list 0x200 0x204 0x208 0x20C 0x210 0x214 0x218 0x21C 0x220 0x224 0x228 0x22C 0x230 0x234 0x238 0x23C ) group.long ($2+0xC00)++0x3 line.long 0x0 "REGG3_DOM_$1,Assign domain for SCR registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x90 0x91 0x92 0x93 0x94 0x95 0x96 0x97 0x98 0x99 0x9A 0x9B 0x9C 0x9D 0x9E 0x9F )(list 0x240 0x244 0x248 0x24C 0x250 0x254 0x258 0x25C 0x260 0x264 0x268 0x26C 0x270 0x274 0x278 0x27C ) group.long ($2+0xC00)++0x3 line.long 0x0 "REGG3_DOM_$1,Assign domain for SCR registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xA0 0xA1 0xA2 0xA3 0xA4 0xA5 0xA6 0xA7 0xA8 0xA9 0xAA 0xAB 0xAC 0xAD 0xAE 0xAF )(list 0x280 0x284 0x288 0x28C 0x290 0x294 0x298 0x29C 0x2A0 0x2A4 0x2A8 0x2AC 0x2B0 0x2B4 0x2B8 0x2BC ) group.long ($2+0xC00)++0x3 line.long 0x0 "REGG3_DOM_$1,Assign domain for SCR registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xB0 0xB1 0xB2 0xB3 0xB4 0xB5 0xB6 0xB7 0xB8 0xB9 0xBA 0xBB 0xBC 0xBD 0xBE 0xBF )(list 0x2C0 0x2C4 0x2C8 0x2CC 0x2D0 0x2D4 0x2D8 0x2DC 0x2E0 0x2E4 0x2E8 0x2EC 0x2F0 0x2F4 0x2F8 0x2FC ) group.long ($2+0xC00)++0x3 line.long 0x0 "REGG3_DOM_$1,Assign domain for SCR registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xC0 0xC1 0xC2 0xC3 0xC4 0xC5 0xC6 0xC7 0xC8 0xC9 0xCA 0xCB 0xCC 0xCD 0xCE 0xCF )(list 0x300 0x304 0x308 0x30C 0x310 0x314 0x318 0x31C 0x320 0x324 0x328 0x32C 0x330 0x334 0x338 0x33C ) group.long ($2+0xC00)++0x3 line.long 0x0 "REGG3_DOM_$1,Assign domain for SCR registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xD0 0xD1 0xD2 0xD3 0xD4 0xD5 0xD6 0xD7 0xD8 0xD9 0xDA 0xDB 0xDC 0xDD 0xDE 0xDF )(list 0x340 0x344 0x348 0x34C 0x350 0x354 0x358 0x35C 0x360 0x364 0x368 0x36C 0x370 0x374 0x378 0x37C ) group.long ($2+0xC00)++0x3 line.long 0x0 "REGG3_DOM_$1,Assign domain for SCR registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xE0 0xE1 0xE2 0xE3 0xE4 0xE5 0xE6 0xE7 0xE8 0xE9 0xEA 0xEB 0xEC 0xED 0xEE 0xEF )(list 0x380 0x384 0x388 0x38C 0x390 0x394 0x398 0x39C 0x3A0 0x3A4 0x3A8 0x3AC 0x3B0 0x3B4 0x3B8 0x3BC ) group.long ($2+0xC00)++0x3 line.long 0x0 "REGG3_DOM_$1,Assign domain for SCR registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xF0 0xF1 0xF2 0xF3 0xF4 0xF5 0xF6 0xF7 0xF8 0xF9 0xFA 0xFB 0xFC 0xFD 0xFE 0xFF )(list 0x3C0 0x3C4 0x3C8 0x3CC 0x3D0 0x3D4 0x3D8 0x3DC 0x3E0 0x3E4 0x3E8 0x3EC 0x3F0 0x3F4 0x3F8 0x3FC ) group.long ($2+0xC00)++0x3 line.long 0x0 "REGG3_DOM_$1,Assign domain for SCR registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x4 0x8 0xC 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C ) group.long ($2+0x1000)++0x3 line.long 0x0 "REGG4_DOM_$1,Assign domain for RSTGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1A 0x1B 0x1C 0x1D 0x1E 0x1F )(list 0x40 0x44 0x48 0x4C 0x50 0x54 0x58 0x5C 0x60 0x64 0x68 0x6C 0x70 0x74 0x78 0x7C ) group.long ($2+0x1000)++0x3 line.long 0x0 "REGG4_DOM_$1,Assign domain for RSTGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x20 0x21 0x22 0x23 0x24 0x25 0x26 0x27 0x28 0x29 0x2A 0x2B 0x2C 0x2D 0x2E 0x2F )(list 0x80 0x84 0x88 0x8C 0x90 0x94 0x98 0x9C 0xA0 0xA4 0xA8 0xAC 0xB0 0xB4 0xB8 0xBC ) group.long ($2+0x1000)++0x3 line.long 0x0 "REGG4_DOM_$1,Assign domain for RSTGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x30 0x31 0x32 0x33 0x34 0x35 0x36 0x37 0x38 0x39 0x3A 0x3B 0x3C 0x3D 0x3E 0x3F )(list 0xC0 0xC4 0xC8 0xCC 0xD0 0xD4 0xD8 0xDC 0xE0 0xE4 0xE8 0xEC 0xF0 0xF4 0xF8 0xFC ) group.long ($2+0x1000)++0x3 line.long 0x0 "REGG4_DOM_$1,Assign domain for RSTGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x40 0x41 0x42 0x43 0x44 0x45 0x46 0x47 0x48 0x49 0x4A 0x4B 0x4C 0x4D 0x4E 0x4F )(list 0x100 0x104 0x108 0x10C 0x110 0x114 0x118 0x11C 0x120 0x124 0x128 0x12C 0x130 0x134 0x138 0x13C ) group.long ($2+0x1000)++0x3 line.long 0x0 "REGG4_DOM_$1,Assign domain for RSTGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x50 0x51 0x52 0x53 0x54 0x55 0x56 0x57 0x58 0x59 0x5A 0x5B 0x5C 0x5D 0x5E 0x5F )(list 0x140 0x144 0x148 0x14C 0x150 0x154 0x158 0x15C 0x160 0x164 0x168 0x16C 0x170 0x174 0x178 0x17C ) group.long ($2+0x1000)++0x3 line.long 0x0 "REGG4_DOM_$1,Assign domain for RSTGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x60 0x61 0x62 0x63 0x64 0x65 0x66 0x67 0x68 0x69 0x6A 0x6B 0x6C 0x6D 0x6E 0x6F )(list 0x180 0x184 0x188 0x18C 0x190 0x194 0x198 0x19C 0x1A0 0x1A4 0x1A8 0x1AC 0x1B0 0x1B4 0x1B8 0x1BC ) group.long ($2+0x1000)++0x3 line.long 0x0 "REGG4_DOM_$1,Assign domain for RSTGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x70 0x71 0x72 0x73 0x74 0x75 0x76 0x77 0x78 0x79 0x7A 0x7B 0x7C 0x7D 0x7E 0x7F )(list 0x1C0 0x1C4 0x1C8 0x1CC 0x1D0 0x1D4 0x1D8 0x1DC 0x1E0 0x1E4 0x1E8 0x1EC 0x1F0 0x1F4 0x1F8 0x1FC ) group.long ($2+0x1000)++0x3 line.long 0x0 "REGG4_DOM_$1,Assign domain for RSTGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x80 0x81 0x82 0x83 0x84 0x85 0x86 0x87 0x88 0x89 0x8A 0x8B 0x8C 0x8D 0x8E 0x8F )(list 0x200 0x204 0x208 0x20C 0x210 0x214 0x218 0x21C 0x220 0x224 0x228 0x22C 0x230 0x234 0x238 0x23C ) group.long ($2+0x1000)++0x3 line.long 0x0 "REGG4_DOM_$1,Assign domain for RSTGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x90 0x91 0x92 0x93 0x94 0x95 0x96 0x97 0x98 0x99 0x9A 0x9B 0x9C 0x9D 0x9E 0x9F )(list 0x240 0x244 0x248 0x24C 0x250 0x254 0x258 0x25C 0x260 0x264 0x268 0x26C 0x270 0x274 0x278 0x27C ) group.long ($2+0x1000)++0x3 line.long 0x0 "REGG4_DOM_$1,Assign domain for RSTGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xA0 0xA1 0xA2 0xA3 0xA4 0xA5 0xA6 0xA7 0xA8 0xA9 0xAA 0xAB 0xAC 0xAD 0xAE 0xAF )(list 0x280 0x284 0x288 0x28C 0x290 0x294 0x298 0x29C 0x2A0 0x2A4 0x2A8 0x2AC 0x2B0 0x2B4 0x2B8 0x2BC ) group.long ($2+0x1000)++0x3 line.long 0x0 "REGG4_DOM_$1,Assign domain for RSTGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xB0 0xB1 0xB2 0xB3 0xB4 0xB5 0xB6 0xB7 0xB8 0xB9 0xBA 0xBB 0xBC 0xBD 0xBE 0xBF )(list 0x2C0 0x2C4 0x2C8 0x2CC 0x2D0 0x2D4 0x2D8 0x2DC 0x2E0 0x2E4 0x2E8 0x2EC 0x2F0 0x2F4 0x2F8 0x2FC ) group.long ($2+0x1000)++0x3 line.long 0x0 "REGG4_DOM_$1,Assign domain for RSTGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xC0 0xC1 0xC2 0xC3 0xC4 0xC5 0xC6 0xC7 0xC8 0xC9 0xCA 0xCB 0xCC 0xCD 0xCE 0xCF )(list 0x300 0x304 0x308 0x30C 0x310 0x314 0x318 0x31C 0x320 0x324 0x328 0x32C 0x330 0x334 0x338 0x33C ) group.long ($2+0x1000)++0x3 line.long 0x0 "REGG4_DOM_$1,Assign domain for RSTGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xD0 0xD1 0xD2 0xD3 0xD4 0xD5 0xD6 0xD7 0xD8 0xD9 0xDA 0xDB 0xDC 0xDD 0xDE 0xDF )(list 0x340 0x344 0x348 0x34C 0x350 0x354 0x358 0x35C 0x360 0x364 0x368 0x36C 0x370 0x374 0x378 0x37C ) group.long ($2+0x1000)++0x3 line.long 0x0 "REGG4_DOM_$1,Assign domain for RSTGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xE0 0xE1 0xE2 0xE3 0xE4 0xE5 0xE6 0xE7 0xE8 0xE9 0xEA 0xEB 0xEC 0xED 0xEE 0xEF )(list 0x380 0x384 0x388 0x38C 0x390 0x394 0x398 0x39C 0x3A0 0x3A4 0x3A8 0x3AC 0x3B0 0x3B4 0x3B8 0x3BC ) group.long ($2+0x1000)++0x3 line.long 0x0 "REGG4_DOM_$1,Assign domain for RSTGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xF0 0xF1 0xF2 0xF3 0xF4 0xF5 0xF6 0xF7 0xF8 0xF9 0xFA 0xFB 0xFC 0xFD 0xFE 0xFF )(list 0x3C0 0x3C4 0x3C8 0x3CC 0x3D0 0x3D4 0x3D8 0x3DC 0x3E0 0x3E4 0x3E8 0x3EC 0x3F0 0x3F4 0x3F8 0x3FC ) group.long ($2+0x1000)++0x3 line.long 0x0 "REGG4_DOM_$1,Assign domain for RSTGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x4 0x8 0xC 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C ) group.long ($2+0x1400)++0x3 line.long 0x0 "REGG5_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1A 0x1B 0x1C 0x1D 0x1E 0x1F )(list 0x40 0x44 0x48 0x4C 0x50 0x54 0x58 0x5C 0x60 0x64 0x68 0x6C 0x70 0x74 0x78 0x7C ) group.long ($2+0x1400)++0x3 line.long 0x0 "REGG5_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x20 0x21 0x22 0x23 0x24 0x25 0x26 0x27 0x28 0x29 0x2A 0x2B 0x2C 0x2D 0x2E 0x2F )(list 0x80 0x84 0x88 0x8C 0x90 0x94 0x98 0x9C 0xA0 0xA4 0xA8 0xAC 0xB0 0xB4 0xB8 0xBC ) group.long ($2+0x1400)++0x3 line.long 0x0 "REGG5_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x30 0x31 0x32 0x33 0x34 0x35 0x36 0x37 0x38 0x39 0x3A 0x3B 0x3C 0x3D 0x3E 0x3F )(list 0xC0 0xC4 0xC8 0xCC 0xD0 0xD4 0xD8 0xDC 0xE0 0xE4 0xE8 0xEC 0xF0 0xF4 0xF8 0xFC ) group.long ($2+0x1400)++0x3 line.long 0x0 "REGG5_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x40 0x41 0x42 0x43 0x44 0x45 0x46 0x47 0x48 0x49 0x4A 0x4B 0x4C 0x4D 0x4E 0x4F )(list 0x100 0x104 0x108 0x10C 0x110 0x114 0x118 0x11C 0x120 0x124 0x128 0x12C 0x130 0x134 0x138 0x13C ) group.long ($2+0x1400)++0x3 line.long 0x0 "REGG5_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x50 0x51 0x52 0x53 0x54 0x55 0x56 0x57 0x58 0x59 0x5A 0x5B 0x5C 0x5D 0x5E 0x5F )(list 0x140 0x144 0x148 0x14C 0x150 0x154 0x158 0x15C 0x160 0x164 0x168 0x16C 0x170 0x174 0x178 0x17C ) group.long ($2+0x1400)++0x3 line.long 0x0 "REGG5_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x60 0x61 0x62 0x63 0x64 0x65 0x66 0x67 0x68 0x69 0x6A 0x6B 0x6C 0x6D 0x6E 0x6F )(list 0x180 0x184 0x188 0x18C 0x190 0x194 0x198 0x19C 0x1A0 0x1A4 0x1A8 0x1AC 0x1B0 0x1B4 0x1B8 0x1BC ) group.long ($2+0x1400)++0x3 line.long 0x0 "REGG5_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x70 0x71 0x72 0x73 0x74 0x75 0x76 0x77 0x78 0x79 0x7A 0x7B 0x7C 0x7D 0x7E 0x7F )(list 0x1C0 0x1C4 0x1C8 0x1CC 0x1D0 0x1D4 0x1D8 0x1DC 0x1E0 0x1E4 0x1E8 0x1EC 0x1F0 0x1F4 0x1F8 0x1FC ) group.long ($2+0x1400)++0x3 line.long 0x0 "REGG5_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x80 0x81 0x82 0x83 0x84 0x85 0x86 0x87 0x88 0x89 0x8A 0x8B 0x8C 0x8D 0x8E 0x8F )(list 0x200 0x204 0x208 0x20C 0x210 0x214 0x218 0x21C 0x220 0x224 0x228 0x22C 0x230 0x234 0x238 0x23C ) group.long ($2+0x1400)++0x3 line.long 0x0 "REGG5_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x90 0x91 0x92 0x93 0x94 0x95 0x96 0x97 0x98 0x99 0x9A 0x9B 0x9C 0x9D 0x9E 0x9F )(list 0x240 0x244 0x248 0x24C 0x250 0x254 0x258 0x25C 0x260 0x264 0x268 0x26C 0x270 0x274 0x278 0x27C ) group.long ($2+0x1400)++0x3 line.long 0x0 "REGG5_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xA0 0xA1 0xA2 0xA3 0xA4 0xA5 0xA6 0xA7 0xA8 0xA9 0xAA 0xAB 0xAC 0xAD 0xAE 0xAF )(list 0x280 0x284 0x288 0x28C 0x290 0x294 0x298 0x29C 0x2A0 0x2A4 0x2A8 0x2AC 0x2B0 0x2B4 0x2B8 0x2BC ) group.long ($2+0x1400)++0x3 line.long 0x0 "REGG5_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xB0 0xB1 0xB2 0xB3 0xB4 0xB5 0xB6 0xB7 0xB8 0xB9 0xBA 0xBB 0xBC 0xBD 0xBE 0xBF )(list 0x2C0 0x2C4 0x2C8 0x2CC 0x2D0 0x2D4 0x2D8 0x2DC 0x2E0 0x2E4 0x2E8 0x2EC 0x2F0 0x2F4 0x2F8 0x2FC ) group.long ($2+0x1400)++0x3 line.long 0x0 "REGG5_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xC0 0xC1 0xC2 0xC3 0xC4 0xC5 0xC6 0xC7 0xC8 0xC9 0xCA 0xCB 0xCC 0xCD 0xCE 0xCF )(list 0x300 0x304 0x308 0x30C 0x310 0x314 0x318 0x31C 0x320 0x324 0x328 0x32C 0x330 0x334 0x338 0x33C ) group.long ($2+0x1400)++0x3 line.long 0x0 "REGG5_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xD0 0xD1 0xD2 0xD3 0xD4 0xD5 0xD6 0xD7 0xD8 0xD9 0xDA 0xDB 0xDC 0xDD 0xDE 0xDF )(list 0x340 0x344 0x348 0x34C 0x350 0x354 0x358 0x35C 0x360 0x364 0x368 0x36C 0x370 0x374 0x378 0x37C ) group.long ($2+0x1400)++0x3 line.long 0x0 "REGG5_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xE0 0xE1 0xE2 0xE3 0xE4 0xE5 0xE6 0xE7 0xE8 0xE9 0xEA 0xEB 0xEC 0xED 0xEE 0xEF )(list 0x380 0x384 0x388 0x38C 0x390 0x394 0x398 0x39C 0x3A0 0x3A4 0x3A8 0x3AC 0x3B0 0x3B4 0x3B8 0x3BC ) group.long ($2+0x1400)++0x3 line.long 0x0 "REGG5_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xF0 0xF1 0xF2 0xF3 0xF4 0xF5 0xF6 0xF7 0xF8 0xF9 0xFA 0xFB 0xFC 0xFD 0xFE 0xFF )(list 0x3C0 0x3C4 0x3C8 0x3CC 0x3D0 0x3D4 0x3D8 0x3DC 0x3E0 0x3E4 0x3E8 0x3EC 0x3F0 0x3F4 0x3F8 0x3FC ) group.long ($2+0x1400)++0x3 line.long 0x0 "REGG5_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x4 0x8 0xC 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C ) group.long ($2+0x1800)++0x3 line.long 0x0 "REGG6_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1A 0x1B 0x1C 0x1D 0x1E 0x1F )(list 0x40 0x44 0x48 0x4C 0x50 0x54 0x58 0x5C 0x60 0x64 0x68 0x6C 0x70 0x74 0x78 0x7C ) group.long ($2+0x1800)++0x3 line.long 0x0 "REGG6_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x20 0x21 0x22 0x23 0x24 0x25 0x26 0x27 0x28 0x29 0x2A 0x2B 0x2C 0x2D 0x2E 0x2F )(list 0x80 0x84 0x88 0x8C 0x90 0x94 0x98 0x9C 0xA0 0xA4 0xA8 0xAC 0xB0 0xB4 0xB8 0xBC ) group.long ($2+0x1800)++0x3 line.long 0x0 "REGG6_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x30 0x31 0x32 0x33 0x34 0x35 0x36 0x37 0x38 0x39 0x3A 0x3B 0x3C 0x3D 0x3E 0x3F )(list 0xC0 0xC4 0xC8 0xCC 0xD0 0xD4 0xD8 0xDC 0xE0 0xE4 0xE8 0xEC 0xF0 0xF4 0xF8 0xFC ) group.long ($2+0x1800)++0x3 line.long 0x0 "REGG6_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x40 0x41 0x42 0x43 0x44 0x45 0x46 0x47 0x48 0x49 0x4A 0x4B 0x4C 0x4D 0x4E 0x4F )(list 0x100 0x104 0x108 0x10C 0x110 0x114 0x118 0x11C 0x120 0x124 0x128 0x12C 0x130 0x134 0x138 0x13C ) group.long ($2+0x1800)++0x3 line.long 0x0 "REGG6_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x50 0x51 0x52 0x53 0x54 0x55 0x56 0x57 0x58 0x59 0x5A 0x5B 0x5C 0x5D 0x5E 0x5F )(list 0x140 0x144 0x148 0x14C 0x150 0x154 0x158 0x15C 0x160 0x164 0x168 0x16C 0x170 0x174 0x178 0x17C ) group.long ($2+0x1800)++0x3 line.long 0x0 "REGG6_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x60 0x61 0x62 0x63 0x64 0x65 0x66 0x67 0x68 0x69 0x6A 0x6B 0x6C 0x6D 0x6E 0x6F )(list 0x180 0x184 0x188 0x18C 0x190 0x194 0x198 0x19C 0x1A0 0x1A4 0x1A8 0x1AC 0x1B0 0x1B4 0x1B8 0x1BC ) group.long ($2+0x1800)++0x3 line.long 0x0 "REGG6_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x70 0x71 0x72 0x73 0x74 0x75 0x76 0x77 0x78 0x79 0x7A 0x7B 0x7C 0x7D 0x7E 0x7F )(list 0x1C0 0x1C4 0x1C8 0x1CC 0x1D0 0x1D4 0x1D8 0x1DC 0x1E0 0x1E4 0x1E8 0x1EC 0x1F0 0x1F4 0x1F8 0x1FC ) group.long ($2+0x1800)++0x3 line.long 0x0 "REGG6_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x80 0x81 0x82 0x83 0x84 0x85 0x86 0x87 0x88 0x89 0x8A 0x8B 0x8C 0x8D 0x8E 0x8F )(list 0x200 0x204 0x208 0x20C 0x210 0x214 0x218 0x21C 0x220 0x224 0x228 0x22C 0x230 0x234 0x238 0x23C ) group.long ($2+0x1800)++0x3 line.long 0x0 "REGG6_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x90 0x91 0x92 0x93 0x94 0x95 0x96 0x97 0x98 0x99 0x9A 0x9B 0x9C 0x9D 0x9E 0x9F )(list 0x240 0x244 0x248 0x24C 0x250 0x254 0x258 0x25C 0x260 0x264 0x268 0x26C 0x270 0x274 0x278 0x27C ) group.long ($2+0x1800)++0x3 line.long 0x0 "REGG6_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xA0 0xA1 0xA2 0xA3 0xA4 0xA5 0xA6 0xA7 0xA8 0xA9 0xAA 0xAB 0xAC 0xAD 0xAE 0xAF )(list 0x280 0x284 0x288 0x28C 0x290 0x294 0x298 0x29C 0x2A0 0x2A4 0x2A8 0x2AC 0x2B0 0x2B4 0x2B8 0x2BC ) group.long ($2+0x1800)++0x3 line.long 0x0 "REGG6_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xB0 0xB1 0xB2 0xB3 0xB4 0xB5 0xB6 0xB7 0xB8 0xB9 0xBA 0xBB 0xBC 0xBD 0xBE 0xBF )(list 0x2C0 0x2C4 0x2C8 0x2CC 0x2D0 0x2D4 0x2D8 0x2DC 0x2E0 0x2E4 0x2E8 0x2EC 0x2F0 0x2F4 0x2F8 0x2FC ) group.long ($2+0x1800)++0x3 line.long 0x0 "REGG6_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xC0 0xC1 0xC2 0xC3 0xC4 0xC5 0xC6 0xC7 0xC8 0xC9 0xCA 0xCB 0xCC 0xCD 0xCE 0xCF )(list 0x300 0x304 0x308 0x30C 0x310 0x314 0x318 0x31C 0x320 0x324 0x328 0x32C 0x330 0x334 0x338 0x33C ) group.long ($2+0x1800)++0x3 line.long 0x0 "REGG6_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xD0 0xD1 0xD2 0xD3 0xD4 0xD5 0xD6 0xD7 0xD8 0xD9 0xDA 0xDB 0xDC 0xDD 0xDE 0xDF )(list 0x340 0x344 0x348 0x34C 0x350 0x354 0x358 0x35C 0x360 0x364 0x368 0x36C 0x370 0x374 0x378 0x37C ) group.long ($2+0x1800)++0x3 line.long 0x0 "REGG6_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xE0 0xE1 0xE2 0xE3 0xE4 0xE5 0xE6 0xE7 0xE8 0xE9 0xEA 0xEB 0xEC 0xED 0xEE 0xEF )(list 0x380 0x384 0x388 0x38C 0x390 0x394 0x398 0x39C 0x3A0 0x3A4 0x3A8 0x3AC 0x3B0 0x3B4 0x3B8 0x3BC ) group.long ($2+0x1800)++0x3 line.long 0x0 "REGG6_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xF0 0xF1 0xF2 0xF3 0xF4 0xF5 0xF6 0xF7 0xF8 0xF9 0xFA 0xFB 0xFC 0xFD 0xFE 0xFF )(list 0x3C0 0x3C4 0x3C8 0x3CC 0x3D0 0x3D4 0x3D8 0x3DC 0x3E0 0x3E4 0x3E8 0x3EC 0x3F0 0x3F4 0x3F8 0x3FC ) group.long ($2+0x1800)++0x3 line.long 0x0 "REGG6_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x4 0x8 0xC 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C ) group.long ($2+0x1C00)++0x3 line.long 0x0 "REGG7_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1A 0x1B 0x1C 0x1D 0x1E 0x1F )(list 0x40 0x44 0x48 0x4C 0x50 0x54 0x58 0x5C 0x60 0x64 0x68 0x6C 0x70 0x74 0x78 0x7C ) group.long ($2+0x1C00)++0x3 line.long 0x0 "REGG7_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x20 0x21 0x22 0x23 0x24 0x25 0x26 0x27 0x28 0x29 0x2A 0x2B 0x2C 0x2D 0x2E 0x2F )(list 0x80 0x84 0x88 0x8C 0x90 0x94 0x98 0x9C 0xA0 0xA4 0xA8 0xAC 0xB0 0xB4 0xB8 0xBC ) group.long ($2+0x1C00)++0x3 line.long 0x0 "REGG7_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x30 0x31 0x32 0x33 0x34 0x35 0x36 0x37 0x38 0x39 0x3A 0x3B 0x3C 0x3D 0x3E 0x3F )(list 0xC0 0xC4 0xC8 0xCC 0xD0 0xD4 0xD8 0xDC 0xE0 0xE4 0xE8 0xEC 0xF0 0xF4 0xF8 0xFC ) group.long ($2+0x1C00)++0x3 line.long 0x0 "REGG7_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x40 0x41 0x42 0x43 0x44 0x45 0x46 0x47 0x48 0x49 0x4A 0x4B 0x4C 0x4D 0x4E 0x4F )(list 0x100 0x104 0x108 0x10C 0x110 0x114 0x118 0x11C 0x120 0x124 0x128 0x12C 0x130 0x134 0x138 0x13C ) group.long ($2+0x1C00)++0x3 line.long 0x0 "REGG7_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x50 0x51 0x52 0x53 0x54 0x55 0x56 0x57 0x58 0x59 0x5A 0x5B 0x5C 0x5D 0x5E 0x5F )(list 0x140 0x144 0x148 0x14C 0x150 0x154 0x158 0x15C 0x160 0x164 0x168 0x16C 0x170 0x174 0x178 0x17C ) group.long ($2+0x1C00)++0x3 line.long 0x0 "REGG7_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x60 0x61 0x62 0x63 0x64 0x65 0x66 0x67 0x68 0x69 0x6A 0x6B 0x6C 0x6D 0x6E 0x6F )(list 0x180 0x184 0x188 0x18C 0x190 0x194 0x198 0x19C 0x1A0 0x1A4 0x1A8 0x1AC 0x1B0 0x1B4 0x1B8 0x1BC ) group.long ($2+0x1C00)++0x3 line.long 0x0 "REGG7_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x70 0x71 0x72 0x73 0x74 0x75 0x76 0x77 0x78 0x79 0x7A 0x7B 0x7C 0x7D 0x7E 0x7F )(list 0x1C0 0x1C4 0x1C8 0x1CC 0x1D0 0x1D4 0x1D8 0x1DC 0x1E0 0x1E4 0x1E8 0x1EC 0x1F0 0x1F4 0x1F8 0x1FC ) group.long ($2+0x1C00)++0x3 line.long 0x0 "REGG7_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x80 0x81 0x82 0x83 0x84 0x85 0x86 0x87 0x88 0x89 0x8A 0x8B 0x8C 0x8D 0x8E 0x8F )(list 0x200 0x204 0x208 0x20C 0x210 0x214 0x218 0x21C 0x220 0x224 0x228 0x22C 0x230 0x234 0x238 0x23C ) group.long ($2+0x1C00)++0x3 line.long 0x0 "REGG7_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x90 0x91 0x92 0x93 0x94 0x95 0x96 0x97 0x98 0x99 0x9A 0x9B 0x9C 0x9D 0x9E 0x9F )(list 0x240 0x244 0x248 0x24C 0x250 0x254 0x258 0x25C 0x260 0x264 0x268 0x26C 0x270 0x274 0x278 0x27C ) group.long ($2+0x1C00)++0x3 line.long 0x0 "REGG7_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xA0 0xA1 0xA2 0xA3 0xA4 0xA5 0xA6 0xA7 0xA8 0xA9 0xAA 0xAB 0xAC 0xAD 0xAE 0xAF )(list 0x280 0x284 0x288 0x28C 0x290 0x294 0x298 0x29C 0x2A0 0x2A4 0x2A8 0x2AC 0x2B0 0x2B4 0x2B8 0x2BC ) group.long ($2+0x1C00)++0x3 line.long 0x0 "REGG7_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xB0 0xB1 0xB2 0xB3 0xB4 0xB5 0xB6 0xB7 0xB8 0xB9 0xBA 0xBB 0xBC 0xBD 0xBE 0xBF )(list 0x2C0 0x2C4 0x2C8 0x2CC 0x2D0 0x2D4 0x2D8 0x2DC 0x2E0 0x2E4 0x2E8 0x2EC 0x2F0 0x2F4 0x2F8 0x2FC ) group.long ($2+0x1C00)++0x3 line.long 0x0 "REGG7_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xC0 0xC1 0xC2 0xC3 0xC4 0xC5 0xC6 0xC7 0xC8 0xC9 0xCA 0xCB 0xCC 0xCD 0xCE 0xCF )(list 0x300 0x304 0x308 0x30C 0x310 0x314 0x318 0x31C 0x320 0x324 0x328 0x32C 0x330 0x334 0x338 0x33C ) group.long ($2+0x1C00)++0x3 line.long 0x0 "REGG7_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xD0 0xD1 0xD2 0xD3 0xD4 0xD5 0xD6 0xD7 0xD8 0xD9 0xDA 0xDB 0xDC 0xDD 0xDE 0xDF )(list 0x340 0x344 0x348 0x34C 0x350 0x354 0x358 0x35C 0x360 0x364 0x368 0x36C 0x370 0x374 0x378 0x37C ) group.long ($2+0x1C00)++0x3 line.long 0x0 "REGG7_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xE0 0xE1 0xE2 0xE3 0xE4 0xE5 0xE6 0xE7 0xE8 0xE9 0xEA 0xEB 0xEC 0xED 0xEE 0xEF )(list 0x380 0x384 0x388 0x38C 0x390 0x394 0x398 0x39C 0x3A0 0x3A4 0x3A8 0x3AC 0x3B0 0x3B4 0x3B8 0x3BC ) group.long ($2+0x1C00)++0x3 line.long 0x0 "REGG7_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xF0 0xF1 0xF2 0xF3 0xF4 0xF5 0xF6 0xF7 0xF8 0xF9 0xFA 0xFB 0xFC 0xFD 0xFE 0xFF )(list 0x3C0 0x3C4 0x3C8 0x3CC 0x3D0 0x3D4 0x3D8 0x3DC 0x3E0 0x3E4 0x3E8 0x3EC 0x3F0 0x3F4 0x3F8 0x3FC ) group.long ($2+0x1C00)++0x3 line.long 0x0 "REGG7_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end group.long 0x2000++0x17 line.long 0x0 "GLB_CTL,This register provides global enable settings for permission control." bitfld.long 0x0 5. "DOM_CFG_LOCK,Lock write for DOM_CFG_MODE bit." "0,1" bitfld.long 0x0 4. "DOM_CFG_MODE,When enabled all the source setting can be configured by master from domain 0 if it is not locked. When disabled only resource manager can configure the permission of the resource." "0,1" bitfld.long 0x0 3. "PERCK_DIS_LOCK,Lock write for PERCK_DIS" "0,1" bitfld.long 0x0 2. "PERCK_DIS,All the permission check disable." "0,1" newline bitfld.long 0x0 1. "DOM_PRO_LOCK,Lock write for DOM_PRO_EN bit." "0,1" bitfld.long 0x0 0. "DOM_PRO_EN,When disabled no domain access permission check" "0,1" line.long 0x4 "RES_MGR,Resource manager register. This regster is used to assign resource manager for global resource access control" bitfld.long 0x4 17. "MID_LOCK,Lock write for MID_EN and MID_LOW and MID_HIG registers." "0,1" bitfld.long 0x4 16. "MID_EN,Master ID check enable" "0,1" bitfld.long 0x4 15. "PRI_PER_LOCK,Lock write for PRI_PER and PRI_PER_EN" "0,1" bitfld.long 0x4 13.--14. "PRI_PER,Resource manager privileged access permission. bit0 for privileged access bit1 for user access" "0,1,2,3" newline bitfld.long 0x4 12. "PRI_PER_EN,Resource manager privileged access permission enable." "0,1" bitfld.long 0x4 11. "SEC_PER_LOCK,Lock for SEC_PER and SEC_PER_LOCK" "0,1" bitfld.long 0x4 9.--10. "SEC_PER,Resource manager secure access permission. bit 0 for secure access bit 1 for non-secure access" "0,1,2,3" bitfld.long 0x4 8. "SEC_PER_EN,Resource manager secure permission enable" "0,1" bitfld.long 0x4 7. "DID_LOCK,Lock write for DID_EN and DID" "0,1" newline hexmask.long.byte 0x4 3.--6. 1. "DID,Resource manager domain ID" bitfld.long 0x4 2. "DID_EN,Resource manager Domain ID enable" "0,1" bitfld.long 0x4 1. "RES_MGR_EN_LOCK,Lock for RES_MGR_EN" "0,1" bitfld.long 0x4 0. "RES_MGR_EN,Resource manager enable. When the bit is disable there is no resource manager." "0,1" line.long 0x8 "RES_MGR_MA0,This register is used to assign master 0~31 as resource manager." hexmask.long 0x8 0.--31. 1. "MID,Assign master 0~31 for resource manager" line.long 0xC "RES_MGR_MA1,This register is used to assign master 32~63 as resource manager." hexmask.long 0xC 0.--31. 1. "MID,Indicate if master 32~63 is resource manager." line.long 0x10 "RES_MGR_MA2,This register is used to assign master 64~95 as resource manager." hexmask.long 0x10 0.--31. 1. "MID,Indicate if master 64~95 is resource manager." line.long 0x14 "RES_MGR_MA3,This register is used to assign master 96~127 as resource manager." hexmask.long 0x14 0.--31. 1. "MID,Indicate if master 96~127 is resource manager." repeat 8. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 )(list 0x0 0x14 0x28 0x3C 0x50 0x64 0x78 0x8C ) group.long ($2+0x2100)++0x3 line.long 0x0 "GRP_MGR_$1,Group Manager Register. This register is used to assign group manager for each domain" bitfld.long 0x0 17. "MID_LOCK,Lock write for MID_EN and MID_LOW and MID_HIG registers." "0,1" bitfld.long 0x0 16. "MID_EN,Master ID check enable" "0,1" bitfld.long 0x0 15. "PRI_PER_LOCK,Lock write for PRI_PER and PRI_PER_EN" "0,1" bitfld.long 0x0 13.--14. "PRI_PER,Group manager privileged access permission. bit0 for privileged access bit1 for user access" "0,1,2,3" newline bitfld.long 0x0 12. "PRI_PER_EN,Group manager privileged access permission enable." "0,1" bitfld.long 0x0 11. "SEC_PER_LOCK,Lock for SEC_PER and SEC_PER_LOCK" "0,1" bitfld.long 0x0 9.--10. "SEC_PER,Group manager secure access permission. bit 0 for secure access bit 1 for non-secure access" "0,1,2,3" bitfld.long 0x0 8. "SEC_PER_EN,Group manager secure permission enable" "0,1" bitfld.long 0x0 7. "DID_LOCK,Lock write for DID_EN and DID" "0,1" newline hexmask.long.byte 0x0 3.--6. 1. "DID,Group manager domain ID" bitfld.long 0x0 2. "DID_EN,Group manager Domain ID enable" "0,1" bitfld.long 0x0 1. "GRP_MGR_EN_LOCK,Lock write for GPR_MGR_EN" "0,1" bitfld.long 0x0 0. "GRP_MGR_EN,Group manager enable. When the bit is disable there is no resource manager." "0,1" repeat.end repeat 8. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 )(list 0x0 0x14 0x28 0x3C 0x50 0x64 0x78 0x8C ) group.long ($2+0x2104)++0x3 line.long 0x0 "GRP_MGR_MA0_$1,Assign master 0~31 for group manager 0" hexmask.long 0x0 0.--31. 1. "MID,Assign master 0~31 for resource manager" repeat.end repeat 8. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 )(list 0x0 0x14 0x28 0x3C 0x50 0x64 0x78 0x8C ) group.long ($2+0x2108)++0x3 line.long 0x0 "GRP_MGR_MA1_$1,Assign master 32~63 for group manager 0" hexmask.long 0x0 0.--31. 1. "MID,Indicate if master 32~63 is resource manager." repeat.end repeat 8. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 )(list 0x0 0x14 0x28 0x3C 0x50 0x64 0x78 0x8C ) group.long ($2+0x210C)++0x3 line.long 0x0 "GRP_MGR_MA2_$1,Assign master 64~95 for group manager 0" hexmask.long 0x0 0.--31. 1. "MID,Indicate if master 64~95 is resource manager." repeat.end repeat 8. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 )(list 0x0 0x14 0x28 0x3C 0x50 0x64 0x78 0x8C ) group.long ($2+0x2110)++0x3 line.long 0x0 "GRP_MGR_MA3_$1,Assign master 96~127 for group manager 0" hexmask.long 0x0 0.--31. 1. "MID,Indicate if master 96~127 is resource manager." repeat.end group.long 0x2200++0x3 line.long 0x0 "DOM_GID_0,Indicate which group domain 0 belong to" bitfld.long 0x0 3. "LOCK,Lock write for GID" "0,1" bitfld.long 0x0 0.--2. "GID,Group ID" "0,1,2,3,4,5,6,7" repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x18 0x30 0x48 0x60 0x78 0x90 0xA8 0xC0 0xD8 0xF0 0x108 0x120 0x138 0x150 0x168 ) group.long ($2+0x2204)++0x3 line.long 0x0 "DOM_OWN_$1,Assign owner for function domain 0." bitfld.long 0x0 17. "MID_LOCK,Lock write for MID_EN and MID_LOW and MID_HIG registers." "0,1" bitfld.long 0x0 16. "MID_EN,Master ID check enable" "0,1" bitfld.long 0x0 15. "PRI_PER_LOCK,Lock write for PRI_PER and PRI_PER_EN" "0,1" bitfld.long 0x0 13.--14. "PRI_PER,Group manager privileged access permission. bit0 for privileged access bit1 for user access" "0,1,2,3" newline bitfld.long 0x0 12. "PRI_PER_EN,Group manager privileged access permission enable." "0,1" bitfld.long 0x0 11. "SEC_PER_LOCK,Lock for SEC_PER and SEC_PER_LOCK" "0,1" bitfld.long 0x0 9.--10. "SEC_PER,Domain owner secure access permission. bit 0 for secure access bit 1 for non-secure access" "0,1,2,3" bitfld.long 0x0 8. "SEC_PER_EN,Domain owner secure permission enable" "0,1" newline bitfld.long 0x0 1. "DOM_OWN_EN_LOCK,Lock for DOM_OWN_EN" "0,1" bitfld.long 0x0 0. "DOM_OWN_EN,Domain owner enable. When the bit is disable there is no domain owner." "0,1" repeat.end repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x18 0x30 0x48 0x60 0x78 0x90 0xA8 0xC0 0xD8 0xF0 0x108 0x120 0x138 0x150 0x168 ) group.long ($2+0x2208)++0x3 line.long 0x0 "DOM_OWN_MA0_$1,Assign master 0~31 for domain owner 0" hexmask.long 0x0 0.--31. 1. "MID,Assign master 0~31 for resource manager" repeat.end repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x18 0x30 0x48 0x60 0x78 0x90 0xA8 0xC0 0xD8 0xF0 0x108 0x120 0x138 0x150 0x168 ) group.long ($2+0x220C)++0x3 line.long 0x0 "DOM_OWN_MA1_$1,Assign master 32~63 for domain owner 0" hexmask.long 0x0 0.--31. 1. "MID,Indicate if master 32~63 is resource manager." repeat.end repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x18 0x30 0x48 0x60 0x78 0x90 0xA8 0xC0 0xD8 0xF0 0x108 0x120 0x138 0x150 0x168 ) group.long ($2+0x2210)++0x3 line.long 0x0 "DOM_OWN_MA2_$1,Assign master 64~95 for domain owner 0" hexmask.long 0x0 0.--31. 1. "MID,Indicate if master 64~95 is resource manager." repeat.end repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x18 0x30 0x48 0x60 0x78 0x90 0xA8 0xC0 0xD8 0xF0 0x108 0x120 0x138 0x150 0x168 ) group.long ($2+0x2214)++0x3 line.long 0x0 "DOM_OWN_MA3_$1,Assign master 96~127 for domain owner 0" hexmask.long 0x0 0.--31. 1. "MID,Indicate if master 96~127 is resource manager." repeat.end group.long 0x2218++0x3 line.long 0x0 "DOM_GID_1,Indicate which group domain 1 belong to" bitfld.long 0x0 3. "LOCK,Lock write for GID" "0,1" bitfld.long 0x0 0.--2. "GID,Group ID" "0,1,2,3,4,5,6,7" group.long 0x2230++0x3 line.long 0x0 "DOM_GID_2,Indicate which group domain 2 belong to" bitfld.long 0x0 3. "LOCK,Lock write for GID" "0,1" bitfld.long 0x0 0.--2. "GID,Group ID" "0,1,2,3,4,5,6,7" group.long 0x2248++0x3 line.long 0x0 "DOM_GID_3,Indicate which group domain 3 belong to" bitfld.long 0x0 3. "LOCK,Lock write for GID" "0,1" bitfld.long 0x0 0.--2. "GID,Group ID" "0,1,2,3,4,5,6,7" group.long 0x2260++0x3 line.long 0x0 "DOM_GID_4,Indicate which group domain 4 belong to" bitfld.long 0x0 3. "LOCK,Lock write for GID" "0,1" bitfld.long 0x0 0.--2. "GID,Group ID" "0,1,2,3,4,5,6,7" group.long 0x2278++0x3 line.long 0x0 "DOM_GID_5,Indicate which group domain 5 belong to" bitfld.long 0x0 3. "LOCK,Lock write for GID" "0,1" bitfld.long 0x0 0.--2. "GID,Group ID" "0,1,2,3,4,5,6,7" group.long 0x2290++0x3 line.long 0x0 "DOM_GID_6,Indicate which group domain 6 belong to" bitfld.long 0x0 3. "LOCK,Lock write for GID" "0,1" bitfld.long 0x0 0.--2. "GID,Group ID" "0,1,2,3,4,5,6,7" group.long 0x22A8++0x3 line.long 0x0 "DOM_GID_7,Indicate which group domain 7 belong to" bitfld.long 0x0 3. "LOCK,Lock write for GID" "0,1" bitfld.long 0x0 0.--2. "GID,Group ID" "0,1,2,3,4,5,6,7" group.long 0x22C0++0x3 line.long 0x0 "DOM_GID_8,Indicate which group domain 8 belong to" bitfld.long 0x0 3. "LOCK,Lock write for GID" "0,1" bitfld.long 0x0 0.--2. "GID,Group ID" "0,1,2,3,4,5,6,7" group.long 0x22D8++0x3 line.long 0x0 "DOM_GID_9,Indicate which group domain 9 belong to" bitfld.long 0x0 3. "LOCK,Lock write for GID" "0,1" bitfld.long 0x0 0.--2. "GID,Group ID" "0,1,2,3,4,5,6,7" group.long 0x22F0++0x3 line.long 0x0 "DOM_GID_10,Indicate which group domain 10 belong to" bitfld.long 0x0 3. "LOCK,Lock write for GID" "0,1" bitfld.long 0x0 0.--2. "GID,Group ID" "0,1,2,3,4,5,6,7" group.long 0x2308++0x3 line.long 0x0 "DOM_GID_11,Indicate which group domain 11 belong to" bitfld.long 0x0 3. "LOCK,Lock write for GID" "0,1" bitfld.long 0x0 0.--2. "GID,Group ID" "0,1,2,3,4,5,6,7" group.long 0x2320++0x3 line.long 0x0 "DOM_GID_12,Indicate which group domain 12 belong to" bitfld.long 0x0 3. "LOCK,Lock write for GID" "0,1" bitfld.long 0x0 0.--2. "GID,Group ID" "0,1,2,3,4,5,6,7" group.long 0x2338++0x3 line.long 0x0 "DOM_GID_13,Indicate which group domain 13 belong to" bitfld.long 0x0 3. "LOCK,Lock write for GID" "0,1" bitfld.long 0x0 0.--2. "GID,Group ID" "0,1,2,3,4,5,6,7" group.long 0x2350++0x3 line.long 0x0 "DOM_GID_14,Indicate which group domain 14 belong to" bitfld.long 0x0 3. "LOCK,Lock write for GID" "0,1" bitfld.long 0x0 0.--2. "GID,Group ID" "0,1,2,3,4,5,6,7" group.long 0x2368++0x3 line.long 0x0 "DOM_GID_15,Indicate which group domain 15 belong to" bitfld.long 0x0 3. "LOCK,Lock write for GID" "0,1" bitfld.long 0x0 0.--2. "GID,Group ID" "0,1,2,3,4,5,6,7" repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x34 0x68 0x9C 0xD0 0x104 0x138 0x16C 0x1A0 0x1D4 0x208 0x23C 0x270 0x2A4 0x2D8 0x30C ) group.long ($2+0x2400)++0x3 line.long 0x0 "DOM_PER0_$1,Domain Permission Control. It can be only configured by resource manager and domain owner." bitfld.long 0x0 31. "DOM7_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 29.--30. "DOM7_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 28. "DOM7_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 27. "DOM6_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 25.--26. "DOM6_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" newline bitfld.long 0x0 24. "DOM6_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 23. "DOM5_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 21.--22. "DOM5_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 20. "DOM5_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 19. "DOM4_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" newline bitfld.long 0x0 17.--18. "DOM4_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM4_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 15. "DOM3_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 13.--14. "DOM3_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 12. "DOM3_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" newline bitfld.long 0x0 11. "DOM2_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 9.--10. "DOM2_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM2_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 7. "DOM1_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 5.--6. "DOM1_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" newline bitfld.long 0x0 4. "DOM1_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 3. "DOM0_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 1.--2. "DOM0_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM0_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" repeat.end repeat 16. (list 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1A 0x1B 0x1C 0x1D 0x1E 0x1F )(list 0x340 0x374 0x3A8 0x3DC 0x410 0x444 0x478 0x4AC 0x4E0 0x514 0x548 0x57C 0x5B0 0x5E4 0x618 0x64C ) group.long ($2+0x2400)++0x3 line.long 0x0 "DOM_PER0_$1,Domain Permission Control. It can be only configured by resource manager and domain owner." bitfld.long 0x0 31. "DOM7_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 29.--30. "DOM7_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 28. "DOM7_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 27. "DOM6_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 25.--26. "DOM6_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" newline bitfld.long 0x0 24. "DOM6_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 23. "DOM5_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 21.--22. "DOM5_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 20. "DOM5_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 19. "DOM4_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" newline bitfld.long 0x0 17.--18. "DOM4_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM4_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 15. "DOM3_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 13.--14. "DOM3_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 12. "DOM3_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" newline bitfld.long 0x0 11. "DOM2_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 9.--10. "DOM2_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM2_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 7. "DOM1_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 5.--6. "DOM1_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" newline bitfld.long 0x0 4. "DOM1_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 3. "DOM0_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 1.--2. "DOM0_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM0_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" repeat.end repeat 16. (list 0x20 0x21 0x22 0x23 0x24 0x25 0x26 0x27 0x28 0x29 0x2A 0x2B 0x2C 0x2D 0x2E 0x2F )(list 0x680 0x6B4 0x6E8 0x71C 0x750 0x784 0x7B8 0x7EC 0x820 0x854 0x888 0x8BC 0x8F0 0x924 0x958 0x98C ) group.long ($2+0x2400)++0x3 line.long 0x0 "DOM_PER0_$1,Domain Permission Control. It can be only configured by resource manager and domain owner." bitfld.long 0x0 31. "DOM7_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 29.--30. "DOM7_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 28. "DOM7_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 27. "DOM6_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 25.--26. "DOM6_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" newline bitfld.long 0x0 24. "DOM6_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 23. "DOM5_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 21.--22. "DOM5_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 20. "DOM5_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 19. "DOM4_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" newline bitfld.long 0x0 17.--18. "DOM4_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM4_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 15. "DOM3_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 13.--14. "DOM3_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 12. "DOM3_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" newline bitfld.long 0x0 11. "DOM2_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 9.--10. "DOM2_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM2_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 7. "DOM1_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 5.--6. "DOM1_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" newline bitfld.long 0x0 4. "DOM1_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 3. "DOM0_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 1.--2. "DOM0_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM0_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" repeat.end repeat 16. (list 0x30 0x31 0x32 0x33 0x34 0x35 0x36 0x37 0x38 0x39 0x3A 0x3B 0x3C 0x3D 0x3E 0x3F )(list 0x9C0 0x9F4 0xA28 0xA5C 0xA90 0xAC4 0xAF8 0xB2C 0xB60 0xB94 0xBC8 0xBFC 0xC30 0xC64 0xC98 0xCCC ) group.long ($2+0x2400)++0x3 line.long 0x0 "DOM_PER0_$1,Domain Permission Control. It can be only configured by resource manager and domain owner." bitfld.long 0x0 31. "DOM7_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 29.--30. "DOM7_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 28. "DOM7_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 27. "DOM6_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 25.--26. "DOM6_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" newline bitfld.long 0x0 24. "DOM6_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 23. "DOM5_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 21.--22. "DOM5_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 20. "DOM5_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 19. "DOM4_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" newline bitfld.long 0x0 17.--18. "DOM4_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM4_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 15. "DOM3_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 13.--14. "DOM3_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 12. "DOM3_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" newline bitfld.long 0x0 11. "DOM2_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 9.--10. "DOM2_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM2_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 7. "DOM1_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 5.--6. "DOM1_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" newline bitfld.long 0x0 4. "DOM1_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 3. "DOM0_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 1.--2. "DOM0_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM0_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" repeat.end repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x34 0x68 0x9C 0xD0 0x104 0x138 0x16C 0x1A0 0x1D4 0x208 0x23C 0x270 0x2A4 0x2D8 0x30C ) group.long ($2+0x2404)++0x3 line.long 0x0 "DOM_PER1_$1,Domain Permission Control. It can be only configured by resource manager and domain owner." bitfld.long 0x0 31. "DOM15_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 29.--30. "DOM15_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 28. "DOM15_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 27. "DOM14_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 25.--26. "DOM14_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" newline bitfld.long 0x0 24. "DOM14_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 23. "DOM13_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 21.--22. "DOM13_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 20. "DOM13_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 19. "DOM12_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" newline bitfld.long 0x0 17.--18. "DOM12_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM12_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 15. "DOM11_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 13.--14. "DOM11_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 12. "DOM11_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" newline bitfld.long 0x0 11. "DOM10_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 9.--10. "DOM10_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM10_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 7. "DOM9_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 5.--6. "DOM9_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" newline bitfld.long 0x0 4. "DOM9_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 3. "DOM8_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 1.--2. "DOM8_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM8_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" repeat.end repeat 16. (list 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1A 0x1B 0x1C 0x1D 0x1E 0x1F )(list 0x340 0x374 0x3A8 0x3DC 0x410 0x444 0x478 0x4AC 0x4E0 0x514 0x548 0x57C 0x5B0 0x5E4 0x618 0x64C ) group.long ($2+0x2404)++0x3 line.long 0x0 "DOM_PER1_$1,Domain Permission Control. It can be only configured by resource manager and domain owner." bitfld.long 0x0 31. "DOM15_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 29.--30. "DOM15_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 28. "DOM15_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 27. "DOM14_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 25.--26. "DOM14_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" newline bitfld.long 0x0 24. "DOM14_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 23. "DOM13_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 21.--22. "DOM13_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 20. "DOM13_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 19. "DOM12_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" newline bitfld.long 0x0 17.--18. "DOM12_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM12_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 15. "DOM11_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 13.--14. "DOM11_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 12. "DOM11_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" newline bitfld.long 0x0 11. "DOM10_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 9.--10. "DOM10_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM10_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 7. "DOM9_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 5.--6. "DOM9_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" newline bitfld.long 0x0 4. "DOM9_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 3. "DOM8_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 1.--2. "DOM8_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM8_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" repeat.end repeat 16. (list 0x20 0x21 0x22 0x23 0x24 0x25 0x26 0x27 0x28 0x29 0x2A 0x2B 0x2C 0x2D 0x2E 0x2F )(list 0x680 0x6B4 0x6E8 0x71C 0x750 0x784 0x7B8 0x7EC 0x820 0x854 0x888 0x8BC 0x8F0 0x924 0x958 0x98C ) group.long ($2+0x2404)++0x3 line.long 0x0 "DOM_PER1_$1,Domain Permission Control. It can be only configured by resource manager and domain owner." bitfld.long 0x0 31. "DOM15_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 29.--30. "DOM15_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 28. "DOM15_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 27. "DOM14_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 25.--26. "DOM14_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" newline bitfld.long 0x0 24. "DOM14_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 23. "DOM13_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 21.--22. "DOM13_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 20. "DOM13_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 19. "DOM12_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" newline bitfld.long 0x0 17.--18. "DOM12_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM12_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 15. "DOM11_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 13.--14. "DOM11_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 12. "DOM11_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" newline bitfld.long 0x0 11. "DOM10_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 9.--10. "DOM10_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM10_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 7. "DOM9_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 5.--6. "DOM9_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" newline bitfld.long 0x0 4. "DOM9_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 3. "DOM8_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 1.--2. "DOM8_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM8_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" repeat.end repeat 16. (list 0x30 0x31 0x32 0x33 0x34 0x35 0x36 0x37 0x38 0x39 0x3A 0x3B 0x3C 0x3D 0x3E 0x3F )(list 0x9C0 0x9F4 0xA28 0xA5C 0xA90 0xAC4 0xAF8 0xB2C 0xB60 0xB94 0xBC8 0xBFC 0xC30 0xC64 0xC98 0xCCC ) group.long ($2+0x2404)++0x3 line.long 0x0 "DOM_PER1_$1,Domain Permission Control. It can be only configured by resource manager and domain owner." bitfld.long 0x0 31. "DOM15_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 29.--30. "DOM15_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 28. "DOM15_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 27. "DOM14_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 25.--26. "DOM14_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" newline bitfld.long 0x0 24. "DOM14_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 23. "DOM13_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 21.--22. "DOM13_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 20. "DOM13_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 19. "DOM12_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" newline bitfld.long 0x0 17.--18. "DOM12_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM12_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 15. "DOM11_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 13.--14. "DOM11_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 12. "DOM11_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" newline bitfld.long 0x0 11. "DOM10_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 9.--10. "DOM10_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM10_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 7. "DOM9_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 5.--6. "DOM9_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" newline bitfld.long 0x0 4. "DOM9_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 3. "DOM8_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 1.--2. "DOM8_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM8_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" repeat.end repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x34 0x68 0x9C 0xD0 0x104 0x138 0x16C 0x1A0 0x1D4 0x208 0x23C 0x270 0x2A4 0x2D8 0x30C ) group.long ($2+0x2408)++0x3 line.long 0x0 "SEC_PER0_$1,This register is only used for resource manager to control secure access permission." bitfld.long 0x0 31. "DOM3_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM3_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM3_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM3_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM2_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM2_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM2_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM2_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM1_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM1_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM1_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM1_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM0_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM0_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM0_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM0_SEC_EN,Domain secure permission control enable" "0,1" repeat.end repeat 16. (list 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1A 0x1B 0x1C 0x1D 0x1E 0x1F )(list 0x340 0x374 0x3A8 0x3DC 0x410 0x444 0x478 0x4AC 0x4E0 0x514 0x548 0x57C 0x5B0 0x5E4 0x618 0x64C ) group.long ($2+0x2408)++0x3 line.long 0x0 "SEC_PER0_$1,This register is only used for resource manager to control secure access permission." bitfld.long 0x0 31. "DOM3_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM3_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM3_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM3_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM2_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM2_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM2_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM2_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM1_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM1_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM1_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM1_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM0_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM0_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM0_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM0_SEC_EN,Domain secure permission control enable" "0,1" repeat.end repeat 16. (list 0x20 0x21 0x22 0x23 0x24 0x25 0x26 0x27 0x28 0x29 0x2A 0x2B 0x2C 0x2D 0x2E 0x2F )(list 0x680 0x6B4 0x6E8 0x71C 0x750 0x784 0x7B8 0x7EC 0x820 0x854 0x888 0x8BC 0x8F0 0x924 0x958 0x98C ) group.long ($2+0x2408)++0x3 line.long 0x0 "SEC_PER0_$1,This register is only used for resource manager to control secure access permission." bitfld.long 0x0 31. "DOM3_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM3_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM3_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM3_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM2_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM2_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM2_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM2_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM1_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM1_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM1_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM1_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM0_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM0_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM0_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM0_SEC_EN,Domain secure permission control enable" "0,1" repeat.end repeat 16. (list 0x30 0x31 0x32 0x33 0x34 0x35 0x36 0x37 0x38 0x39 0x3A 0x3B 0x3C 0x3D 0x3E 0x3F )(list 0x9C0 0x9F4 0xA28 0xA5C 0xA90 0xAC4 0xAF8 0xB2C 0xB60 0xB94 0xBC8 0xBFC 0xC30 0xC64 0xC98 0xCCC ) group.long ($2+0x2408)++0x3 line.long 0x0 "SEC_PER0_$1,This register is only used for resource manager to control secure access permission." bitfld.long 0x0 31. "DOM3_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM3_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM3_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM3_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM2_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM2_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM2_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM2_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM1_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM1_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM1_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM1_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM0_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM0_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM0_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM0_SEC_EN,Domain secure permission control enable" "0,1" repeat.end repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x34 0x68 0x9C 0xD0 0x104 0x138 0x16C 0x1A0 0x1D4 0x208 0x23C 0x270 0x2A4 0x2D8 0x30C ) group.long ($2+0x240C)++0x3 line.long 0x0 "SEC_PER1_$1,This register is only used for resource manager to control secure access permission." bitfld.long 0x0 31. "DOM7_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM7_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM7_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM7_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM6_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM6_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM6_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM6_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM5_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM5_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM5_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM5_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM4_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM4_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM4_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM4_SEC_EN,Domain secure permission control enable" "0,1" repeat.end repeat 16. (list 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1A 0x1B 0x1C 0x1D 0x1E 0x1F )(list 0x340 0x374 0x3A8 0x3DC 0x410 0x444 0x478 0x4AC 0x4E0 0x514 0x548 0x57C 0x5B0 0x5E4 0x618 0x64C ) group.long ($2+0x240C)++0x3 line.long 0x0 "SEC_PER1_$1,This register is only used for resource manager to control secure access permission." bitfld.long 0x0 31. "DOM7_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM7_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM7_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM7_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM6_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM6_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM6_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM6_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM5_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM5_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM5_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM5_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM4_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM4_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM4_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM4_SEC_EN,Domain secure permission control enable" "0,1" repeat.end repeat 16. (list 0x20 0x21 0x22 0x23 0x24 0x25 0x26 0x27 0x28 0x29 0x2A 0x2B 0x2C 0x2D 0x2E 0x2F )(list 0x680 0x6B4 0x6E8 0x71C 0x750 0x784 0x7B8 0x7EC 0x820 0x854 0x888 0x8BC 0x8F0 0x924 0x958 0x98C ) group.long ($2+0x240C)++0x3 line.long 0x0 "SEC_PER1_$1,This register is only used for resource manager to control secure access permission." bitfld.long 0x0 31. "DOM7_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM7_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM7_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM7_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM6_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM6_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM6_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM6_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM5_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM5_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM5_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM5_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM4_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM4_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM4_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM4_SEC_EN,Domain secure permission control enable" "0,1" repeat.end repeat 16. (list 0x30 0x31 0x32 0x33 0x34 0x35 0x36 0x37 0x38 0x39 0x3A 0x3B 0x3C 0x3D 0x3E 0x3F )(list 0x9C0 0x9F4 0xA28 0xA5C 0xA90 0xAC4 0xAF8 0xB2C 0xB60 0xB94 0xBC8 0xBFC 0xC30 0xC64 0xC98 0xCCC ) group.long ($2+0x240C)++0x3 line.long 0x0 "SEC_PER1_$1,This register is only used for resource manager to control secure access permission." bitfld.long 0x0 31. "DOM7_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM7_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM7_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM7_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM6_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM6_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM6_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM6_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM5_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM5_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM5_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM5_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM4_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM4_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM4_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM4_SEC_EN,Domain secure permission control enable" "0,1" repeat.end repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x34 0x68 0x9C 0xD0 0x104 0x138 0x16C 0x1A0 0x1D4 0x208 0x23C 0x270 0x2A4 0x2D8 0x30C ) group.long ($2+0x2410)++0x3 line.long 0x0 "SEC_PER2_$1,This register is only used for resource manager to control secure access permission." bitfld.long 0x0 31. "DOM11_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM11_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM11_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM11_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM10_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM10_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM10_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM10_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM9_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM9_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM9_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM9_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM8_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM8_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM8_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM8_SEC_EN,Domain secure permission control enable" "0,1" repeat.end repeat 16. (list 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1A 0x1B 0x1C 0x1D 0x1E 0x1F )(list 0x340 0x374 0x3A8 0x3DC 0x410 0x444 0x478 0x4AC 0x4E0 0x514 0x548 0x57C 0x5B0 0x5E4 0x618 0x64C ) group.long ($2+0x2410)++0x3 line.long 0x0 "SEC_PER2_$1,This register is only used for resource manager to control secure access permission." bitfld.long 0x0 31. "DOM11_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM11_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM11_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM11_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM10_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM10_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM10_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM10_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM9_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM9_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM9_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM9_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM8_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM8_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM8_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM8_SEC_EN,Domain secure permission control enable" "0,1" repeat.end repeat 16. (list 0x20 0x21 0x22 0x23 0x24 0x25 0x26 0x27 0x28 0x29 0x2A 0x2B 0x2C 0x2D 0x2E 0x2F )(list 0x680 0x6B4 0x6E8 0x71C 0x750 0x784 0x7B8 0x7EC 0x820 0x854 0x888 0x8BC 0x8F0 0x924 0x958 0x98C ) group.long ($2+0x2410)++0x3 line.long 0x0 "SEC_PER2_$1,This register is only used for resource manager to control secure access permission." bitfld.long 0x0 31. "DOM11_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM11_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM11_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM11_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM10_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM10_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM10_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM10_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM9_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM9_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM9_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM9_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM8_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM8_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM8_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM8_SEC_EN,Domain secure permission control enable" "0,1" repeat.end repeat 16. (list 0x30 0x31 0x32 0x33 0x34 0x35 0x36 0x37 0x38 0x39 0x3A 0x3B 0x3C 0x3D 0x3E 0x3F )(list 0x9C0 0x9F4 0xA28 0xA5C 0xA90 0xAC4 0xAF8 0xB2C 0xB60 0xB94 0xBC8 0xBFC 0xC30 0xC64 0xC98 0xCCC ) group.long ($2+0x2410)++0x3 line.long 0x0 "SEC_PER2_$1,This register is only used for resource manager to control secure access permission." bitfld.long 0x0 31. "DOM11_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM11_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM11_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM11_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM10_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM10_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM10_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM10_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM9_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM9_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM9_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM9_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM8_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM8_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM8_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM8_SEC_EN,Domain secure permission control enable" "0,1" repeat.end repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x34 0x68 0x9C 0xD0 0x104 0x138 0x16C 0x1A0 0x1D4 0x208 0x23C 0x270 0x2A4 0x2D8 0x30C ) group.long ($2+0x2414)++0x3 line.long 0x0 "SEC_PER3_$1,This register is only used for resource manager to control secure access permission." bitfld.long 0x0 31. "DOM15_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM15_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM15_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM15_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM14_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM14_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM14_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM14_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM13_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM13_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM13_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM13_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM12_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM12_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM12_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM12_SEC_EN,Domain secure permission control enable" "0,1" repeat.end repeat 16. (list 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1A 0x1B 0x1C 0x1D 0x1E 0x1F )(list 0x340 0x374 0x3A8 0x3DC 0x410 0x444 0x478 0x4AC 0x4E0 0x514 0x548 0x57C 0x5B0 0x5E4 0x618 0x64C ) group.long ($2+0x2414)++0x3 line.long 0x0 "SEC_PER3_$1,This register is only used for resource manager to control secure access permission." bitfld.long 0x0 31. "DOM15_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM15_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM15_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM15_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM14_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM14_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM14_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM14_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM13_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM13_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM13_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM13_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM12_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM12_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM12_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM12_SEC_EN,Domain secure permission control enable" "0,1" repeat.end repeat 16. (list 0x20 0x21 0x22 0x23 0x24 0x25 0x26 0x27 0x28 0x29 0x2A 0x2B 0x2C 0x2D 0x2E 0x2F )(list 0x680 0x6B4 0x6E8 0x71C 0x750 0x784 0x7B8 0x7EC 0x820 0x854 0x888 0x8BC 0x8F0 0x924 0x958 0x98C ) group.long ($2+0x2414)++0x3 line.long 0x0 "SEC_PER3_$1,This register is only used for resource manager to control secure access permission." bitfld.long 0x0 31. "DOM15_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM15_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM15_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM15_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM14_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM14_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM14_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM14_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM13_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM13_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM13_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM13_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM12_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM12_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM12_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM12_SEC_EN,Domain secure permission control enable" "0,1" repeat.end repeat 16. (list 0x30 0x31 0x32 0x33 0x34 0x35 0x36 0x37 0x38 0x39 0x3A 0x3B 0x3C 0x3D 0x3E 0x3F )(list 0x9C0 0x9F4 0xA28 0xA5C 0xA90 0xAC4 0xAF8 0xB2C 0xB60 0xB94 0xBC8 0xBFC 0xC30 0xC64 0xC98 0xCCC ) group.long ($2+0x2414)++0x3 line.long 0x0 "SEC_PER3_$1,This register is only used for resource manager to control secure access permission." bitfld.long 0x0 31. "DOM15_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM15_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM15_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM15_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM14_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM14_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM14_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM14_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM13_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM13_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM13_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM13_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM12_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM12_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM12_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM12_SEC_EN,Domain secure permission control enable" "0,1" repeat.end repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x34 0x68 0x9C 0xD0 0x104 0x138 0x16C 0x1A0 0x1D4 0x208 0x23C 0x270 0x2A4 0x2D8 0x30C ) group.long ($2+0x2418)++0x3 line.long 0x0 "PRI_PER0_$1,This register is only used for resource manager to control privileged access permission." bitfld.long 0x0 31. "DOM3_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM3_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM3_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM3_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM2_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM2_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM2_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM2_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM1_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM1_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM1_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM1_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM0_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM0_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM0_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM0_PRI_EN,Domain privileged permission control enable" "0,1" repeat.end repeat 16. (list 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1A 0x1B 0x1C 0x1D 0x1E 0x1F )(list 0x340 0x374 0x3A8 0x3DC 0x410 0x444 0x478 0x4AC 0x4E0 0x514 0x548 0x57C 0x5B0 0x5E4 0x618 0x64C ) group.long ($2+0x2418)++0x3 line.long 0x0 "PRI_PER0_$1,This register is only used for resource manager to control privileged access permission." bitfld.long 0x0 31. "DOM3_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM3_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM3_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM3_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM2_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM2_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM2_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM2_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM1_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM1_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM1_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM1_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM0_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM0_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM0_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM0_PRI_EN,Domain privileged permission control enable" "0,1" repeat.end repeat 16. (list 0x20 0x21 0x22 0x23 0x24 0x25 0x26 0x27 0x28 0x29 0x2A 0x2B 0x2C 0x2D 0x2E 0x2F )(list 0x680 0x6B4 0x6E8 0x71C 0x750 0x784 0x7B8 0x7EC 0x820 0x854 0x888 0x8BC 0x8F0 0x924 0x958 0x98C ) group.long ($2+0x2418)++0x3 line.long 0x0 "PRI_PER0_$1,This register is only used for resource manager to control privileged access permission." bitfld.long 0x0 31. "DOM3_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM3_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM3_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM3_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM2_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM2_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM2_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM2_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM1_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM1_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM1_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM1_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM0_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM0_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM0_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM0_PRI_EN,Domain privileged permission control enable" "0,1" repeat.end repeat 16. (list 0x30 0x31 0x32 0x33 0x34 0x35 0x36 0x37 0x38 0x39 0x3A 0x3B 0x3C 0x3D 0x3E 0x3F )(list 0x9C0 0x9F4 0xA28 0xA5C 0xA90 0xAC4 0xAF8 0xB2C 0xB60 0xB94 0xBC8 0xBFC 0xC30 0xC64 0xC98 0xCCC ) group.long ($2+0x2418)++0x3 line.long 0x0 "PRI_PER0_$1,This register is only used for resource manager to control privileged access permission." bitfld.long 0x0 31. "DOM3_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM3_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM3_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM3_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM2_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM2_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM2_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM2_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM1_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM1_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM1_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM1_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM0_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM0_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM0_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM0_PRI_EN,Domain privileged permission control enable" "0,1" repeat.end repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x34 0x68 0x9C 0xD0 0x104 0x138 0x16C 0x1A0 0x1D4 0x208 0x23C 0x270 0x2A4 0x2D8 0x30C ) group.long ($2+0x241C)++0x3 line.long 0x0 "PRI_PER1_$1,This register is only used for resource manager to control privileged access permission." bitfld.long 0x0 31. "DOM7_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM7_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM7_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM7_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM6_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM6_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM6_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM6_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM5_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM5_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM5_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM5_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM4_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM4_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM4_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM4_PRI_EN,Domain privileged permission control enable" "0,1" repeat.end repeat 16. (list 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1A 0x1B 0x1C 0x1D 0x1E 0x1F )(list 0x340 0x374 0x3A8 0x3DC 0x410 0x444 0x478 0x4AC 0x4E0 0x514 0x548 0x57C 0x5B0 0x5E4 0x618 0x64C ) group.long ($2+0x241C)++0x3 line.long 0x0 "PRI_PER1_$1,This register is only used for resource manager to control privileged access permission." bitfld.long 0x0 31. "DOM7_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM7_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM7_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM7_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM6_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM6_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM6_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM6_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM5_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM5_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM5_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM5_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM4_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM4_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM4_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM4_PRI_EN,Domain privileged permission control enable" "0,1" repeat.end repeat 16. (list 0x20 0x21 0x22 0x23 0x24 0x25 0x26 0x27 0x28 0x29 0x2A 0x2B 0x2C 0x2D 0x2E 0x2F )(list 0x680 0x6B4 0x6E8 0x71C 0x750 0x784 0x7B8 0x7EC 0x820 0x854 0x888 0x8BC 0x8F0 0x924 0x958 0x98C ) group.long ($2+0x241C)++0x3 line.long 0x0 "PRI_PER1_$1,This register is only used for resource manager to control privileged access permission." bitfld.long 0x0 31. "DOM7_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM7_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM7_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM7_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM6_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM6_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM6_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM6_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM5_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM5_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM5_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM5_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM4_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM4_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM4_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM4_PRI_EN,Domain privileged permission control enable" "0,1" repeat.end repeat 16. (list 0x30 0x31 0x32 0x33 0x34 0x35 0x36 0x37 0x38 0x39 0x3A 0x3B 0x3C 0x3D 0x3E 0x3F )(list 0x9C0 0x9F4 0xA28 0xA5C 0xA90 0xAC4 0xAF8 0xB2C 0xB60 0xB94 0xBC8 0xBFC 0xC30 0xC64 0xC98 0xCCC ) group.long ($2+0x241C)++0x3 line.long 0x0 "PRI_PER1_$1,This register is only used for resource manager to control privileged access permission." bitfld.long 0x0 31. "DOM7_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM7_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM7_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM7_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM6_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM6_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM6_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM6_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM5_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM5_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM5_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM5_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM4_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM4_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM4_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM4_PRI_EN,Domain privileged permission control enable" "0,1" repeat.end repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x34 0x68 0x9C 0xD0 0x104 0x138 0x16C 0x1A0 0x1D4 0x208 0x23C 0x270 0x2A4 0x2D8 0x30C ) group.long ($2+0x2420)++0x3 line.long 0x0 "PRI_PER2_$1,This register is only used for resource manager to control privileged access permission." bitfld.long 0x0 31. "DOM11_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM11_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM11_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM11_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM10_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM10_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM10_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM10_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM9_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM9_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM9_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM9_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM8_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM8_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM8_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM8_PRI_EN,Domain privileged permission control enable" "0,1" repeat.end repeat 16. (list 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1A 0x1B 0x1C 0x1D 0x1E 0x1F )(list 0x340 0x374 0x3A8 0x3DC 0x410 0x444 0x478 0x4AC 0x4E0 0x514 0x548 0x57C 0x5B0 0x5E4 0x618 0x64C ) group.long ($2+0x2420)++0x3 line.long 0x0 "PRI_PER2_$1,This register is only used for resource manager to control privileged access permission." bitfld.long 0x0 31. "DOM11_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM11_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM11_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM11_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM10_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM10_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM10_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM10_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM9_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM9_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM9_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM9_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM8_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM8_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM8_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM8_PRI_EN,Domain privileged permission control enable" "0,1" repeat.end repeat 16. (list 0x20 0x21 0x22 0x23 0x24 0x25 0x26 0x27 0x28 0x29 0x2A 0x2B 0x2C 0x2D 0x2E 0x2F )(list 0x680 0x6B4 0x6E8 0x71C 0x750 0x784 0x7B8 0x7EC 0x820 0x854 0x888 0x8BC 0x8F0 0x924 0x958 0x98C ) group.long ($2+0x2420)++0x3 line.long 0x0 "PRI_PER2_$1,This register is only used for resource manager to control privileged access permission." bitfld.long 0x0 31. "DOM11_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM11_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM11_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM11_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM10_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM10_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM10_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM10_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM9_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM9_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM9_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM9_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM8_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM8_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM8_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM8_PRI_EN,Domain privileged permission control enable" "0,1" repeat.end repeat 16. (list 0x30 0x31 0x32 0x33 0x34 0x35 0x36 0x37 0x38 0x39 0x3A 0x3B 0x3C 0x3D 0x3E 0x3F )(list 0x9C0 0x9F4 0xA28 0xA5C 0xA90 0xAC4 0xAF8 0xB2C 0xB60 0xB94 0xBC8 0xBFC 0xC30 0xC64 0xC98 0xCCC ) group.long ($2+0x2420)++0x3 line.long 0x0 "PRI_PER2_$1,This register is only used for resource manager to control privileged access permission." bitfld.long 0x0 31. "DOM11_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM11_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM11_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM11_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM10_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM10_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM10_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM10_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM9_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM9_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM9_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM9_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM8_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM8_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM8_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM8_PRI_EN,Domain privileged permission control enable" "0,1" repeat.end repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x34 0x68 0x9C 0xD0 0x104 0x138 0x16C 0x1A0 0x1D4 0x208 0x23C 0x270 0x2A4 0x2D8 0x30C ) group.long ($2+0x2424)++0x3 line.long 0x0 "PRI_PER3_$1,This register is only used for resource manager to control privileged access permission." bitfld.long 0x0 31. "DOM15_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM15_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM15_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM15_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM14_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM14_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM14_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM14_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM13_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM13_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM13_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM13_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM12_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM12_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM12_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM12_PRI_EN,Domain privileged permission control enable" "0,1" repeat.end repeat 16. (list 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1A 0x1B 0x1C 0x1D 0x1E 0x1F )(list 0x340 0x374 0x3A8 0x3DC 0x410 0x444 0x478 0x4AC 0x4E0 0x514 0x548 0x57C 0x5B0 0x5E4 0x618 0x64C ) group.long ($2+0x2424)++0x3 line.long 0x0 "PRI_PER3_$1,This register is only used for resource manager to control privileged access permission." bitfld.long 0x0 31. "DOM15_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM15_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM15_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM15_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM14_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM14_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM14_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM14_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM13_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM13_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM13_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM13_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM12_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM12_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM12_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM12_PRI_EN,Domain privileged permission control enable" "0,1" repeat.end repeat 16. (list 0x20 0x21 0x22 0x23 0x24 0x25 0x26 0x27 0x28 0x29 0x2A 0x2B 0x2C 0x2D 0x2E 0x2F )(list 0x680 0x6B4 0x6E8 0x71C 0x750 0x784 0x7B8 0x7EC 0x820 0x854 0x888 0x8BC 0x8F0 0x924 0x958 0x98C ) group.long ($2+0x2424)++0x3 line.long 0x0 "PRI_PER3_$1,This register is only used for resource manager to control privileged access permission." bitfld.long 0x0 31. "DOM15_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM15_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM15_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM15_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM14_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM14_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM14_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM14_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM13_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM13_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM13_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM13_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM12_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM12_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM12_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM12_PRI_EN,Domain privileged permission control enable" "0,1" repeat.end repeat 16. (list 0x30 0x31 0x32 0x33 0x34 0x35 0x36 0x37 0x38 0x39 0x3A 0x3B 0x3C 0x3D 0x3E 0x3F )(list 0x9C0 0x9F4 0xA28 0xA5C 0xA90 0xAC4 0xAF8 0xB2C 0xB60 0xB94 0xBC8 0xBFC 0xC30 0xC64 0xC98 0xCCC ) group.long ($2+0x2424)++0x3 line.long 0x0 "PRI_PER3_$1,This register is only used for resource manager to control privileged access permission." bitfld.long 0x0 31. "DOM15_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM15_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM15_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM15_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM14_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM14_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM14_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM14_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM13_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM13_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM13_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM13_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM12_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM12_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM12_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM12_PRI_EN,Domain privileged permission control enable" "0,1" repeat.end repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x34 0x68 0x9C 0xD0 0x104 0x138 0x16C 0x1A0 0x1D4 0x208 0x23C 0x270 0x2A4 0x2D8 0x30C ) group.long ($2+0x2428)++0x3 line.long 0x0 "DOM_SEC_PER_$1,This register is only used for domain master to control secure access permission. When the domain master write this register. it only changes the secure permission for itself. When the domain master read this register. it gets permission.." bitfld.long 0x0 7. "DOM_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" newline bitfld.long 0x0 0. "DOM_SEC_EN,Domain secure permission control enable" "0,1" repeat.end repeat 16. (list 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1A 0x1B 0x1C 0x1D 0x1E 0x1F )(list 0x340 0x374 0x3A8 0x3DC 0x410 0x444 0x478 0x4AC 0x4E0 0x514 0x548 0x57C 0x5B0 0x5E4 0x618 0x64C ) group.long ($2+0x2428)++0x3 line.long 0x0 "DOM_SEC_PER_$1,This register is only used for domain master to control secure access permission. When the domain master write this register. it only changes the secure permission for itself. When the domain master read this register. it gets permission.." bitfld.long 0x0 7. "DOM_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" newline bitfld.long 0x0 0. "DOM_SEC_EN,Domain secure permission control enable" "0,1" repeat.end repeat 16. (list 0x20 0x21 0x22 0x23 0x24 0x25 0x26 0x27 0x28 0x29 0x2A 0x2B 0x2C 0x2D 0x2E 0x2F )(list 0x680 0x6B4 0x6E8 0x71C 0x750 0x784 0x7B8 0x7EC 0x820 0x854 0x888 0x8BC 0x8F0 0x924 0x958 0x98C ) group.long ($2+0x2428)++0x3 line.long 0x0 "DOM_SEC_PER_$1,This register is only used for domain master to control secure access permission. When the domain master write this register. it only changes the secure permission for itself. When the domain master read this register. it gets permission.." bitfld.long 0x0 7. "DOM_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" newline bitfld.long 0x0 0. "DOM_SEC_EN,Domain secure permission control enable" "0,1" repeat.end repeat 16. (list 0x30 0x31 0x32 0x33 0x34 0x35 0x36 0x37 0x38 0x39 0x3A 0x3B 0x3C 0x3D 0x3E 0x3F )(list 0x9C0 0x9F4 0xA28 0xA5C 0xA90 0xAC4 0xAF8 0xB2C 0xB60 0xB94 0xBC8 0xBFC 0xC30 0xC64 0xC98 0xCCC ) group.long ($2+0x2428)++0x3 line.long 0x0 "DOM_SEC_PER_$1,This register is only used for domain master to control secure access permission. When the domain master write this register. it only changes the secure permission for itself. When the domain master read this register. it gets permission.." bitfld.long 0x0 7. "DOM_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" newline bitfld.long 0x0 0. "DOM_SEC_EN,Domain secure permission control enable" "0,1" repeat.end repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x34 0x68 0x9C 0xD0 0x104 0x138 0x16C 0x1A0 0x1D4 0x208 0x23C 0x270 0x2A4 0x2D8 0x30C ) group.long ($2+0x242C)++0x3 line.long 0x0 "DOM_PRI_PER_$1,This register is only used for domain master to control secure access permission. When the domain master write this register. it only changes the secure permission for itself. When the domain master read this register. it gets permission.." bitfld.long 0x0 7. "DOM_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" newline bitfld.long 0x0 0. "DOM_PRI_EN,Domain privileged permission control enable" "0,1" repeat.end repeat 16. (list 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1A 0x1B 0x1C 0x1D 0x1E 0x1F )(list 0x340 0x374 0x3A8 0x3DC 0x410 0x444 0x478 0x4AC 0x4E0 0x514 0x548 0x57C 0x5B0 0x5E4 0x618 0x64C ) group.long ($2+0x242C)++0x3 line.long 0x0 "DOM_PRI_PER_$1,This register is only used for domain master to control secure access permission. When the domain master write this register. it only changes the secure permission for itself. When the domain master read this register. it gets permission.." bitfld.long 0x0 7. "DOM_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" newline bitfld.long 0x0 0. "DOM_PRI_EN,Domain privileged permission control enable" "0,1" repeat.end repeat 16. (list 0x20 0x21 0x22 0x23 0x24 0x25 0x26 0x27 0x28 0x29 0x2A 0x2B 0x2C 0x2D 0x2E 0x2F )(list 0x680 0x6B4 0x6E8 0x71C 0x750 0x784 0x7B8 0x7EC 0x820 0x854 0x888 0x8BC 0x8F0 0x924 0x958 0x98C ) group.long ($2+0x242C)++0x3 line.long 0x0 "DOM_PRI_PER_$1,This register is only used for domain master to control secure access permission. When the domain master write this register. it only changes the secure permission for itself. When the domain master read this register. it gets permission.." bitfld.long 0x0 7. "DOM_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" newline bitfld.long 0x0 0. "DOM_PRI_EN,Domain privileged permission control enable" "0,1" repeat.end repeat 16. (list 0x30 0x31 0x32 0x33 0x34 0x35 0x36 0x37 0x38 0x39 0x3A 0x3B 0x3C 0x3D 0x3E 0x3F )(list 0x9C0 0x9F4 0xA28 0xA5C 0xA90 0xAC4 0xAF8 0xB2C 0xB60 0xB94 0xBC8 0xBFC 0xC30 0xC64 0xC98 0xCCC ) group.long ($2+0x242C)++0x3 line.long 0x0 "DOM_PRI_PER_$1,This register is only used for domain master to control secure access permission. When the domain master write this register. it only changes the secure permission for itself. When the domain master read this register. it gets permission.." bitfld.long 0x0 7. "DOM_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" newline bitfld.long 0x0 0. "DOM_PRI_EN,Domain privileged permission control enable" "0,1" repeat.end repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x34 0x68 0x9C 0xD0 0x104 0x138 0x16C 0x1A0 0x1D4 0x208 0x23C 0x270 0x2A4 0x2D8 0x30C ) group.long ($2+0x2430)++0x3 line.long 0x0 "DOM_ASSIGN_$1,Use to assign domain for accessing DOM_SEC_PER and DOM_PRI_PER register. Only resource manager. group manager and domain owner can access this register. For write. group manager must write its owen domain ID. otherwise write accessing will.." hexmask.long.byte 0x0 0.--3. 1. "DID,accessing DOM_SEC_PER and DOM_PRI_PER register" repeat.end repeat 16. (list 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1A 0x1B 0x1C 0x1D 0x1E 0x1F )(list 0x340 0x374 0x3A8 0x3DC 0x410 0x444 0x478 0x4AC 0x4E0 0x514 0x548 0x57C 0x5B0 0x5E4 0x618 0x64C ) group.long ($2+0x2430)++0x3 line.long 0x0 "DOM_ASSIGN_$1,Use to assign domain for accessing DOM_SEC_PER and DOM_PRI_PER register. Only resource manager. group manager and domain owner can access this register. For write. group manager must write its owen domain ID. otherwise write accessing will.." hexmask.long.byte 0x0 0.--3. 1. "DID,accessing DOM_SEC_PER and DOM_PRI_PER register" repeat.end repeat 16. (list 0x20 0x21 0x22 0x23 0x24 0x25 0x26 0x27 0x28 0x29 0x2A 0x2B 0x2C 0x2D 0x2E 0x2F )(list 0x680 0x6B4 0x6E8 0x71C 0x750 0x784 0x7B8 0x7EC 0x820 0x854 0x888 0x8BC 0x8F0 0x924 0x958 0x98C ) group.long ($2+0x2430)++0x3 line.long 0x0 "DOM_ASSIGN_$1,Use to assign domain for accessing DOM_SEC_PER and DOM_PRI_PER register. Only resource manager. group manager and domain owner can access this register. For write. group manager must write its owen domain ID. otherwise write accessing will.." hexmask.long.byte 0x0 0.--3. 1. "DID,accessing DOM_SEC_PER and DOM_PRI_PER register" repeat.end repeat 16. (list 0x30 0x31 0x32 0x33 0x34 0x35 0x36 0x37 0x38 0x39 0x3A 0x3B 0x3C 0x3D 0x3E 0x3F )(list 0x9C0 0x9F4 0xA28 0xA5C 0xA90 0xAC4 0xAF8 0xB2C 0xB60 0xB94 0xBC8 0xBFC 0xC30 0xC64 0xC98 0xCCC ) group.long ($2+0x2430)++0x3 line.long 0x0 "DOM_ASSIGN_$1,Use to assign domain for accessing DOM_SEC_PER and DOM_PRI_PER register. Only resource manager. group manager and domain owner can access this register. For write. group manager must write its owen domain ID. otherwise write accessing will.." hexmask.long.byte 0x0 0.--3. 1. "DID,accessing DOM_SEC_PER and DOM_PRI_PER register" repeat.end repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x38 0x70 0xA8 0xE0 0x118 0x150 0x188 0x1C0 0x1F8 0x230 0x268 0x2A0 0x2D8 0x310 0x348 ) group.long ($2+0x3100)++0x3 line.long 0x0 "RGN_DOM_$1,Assign domain for peripheral. It can be only configured by resource and group manager" bitfld.long 0x0 31. "LOCK,When this bit is set lock write for all the bits in the register." "0,1" bitfld.long 0x0 4. "SET,Set together with DID would change permission of this resource to following setting: 1) Domain access control enabled. 2) Read/Write allowed for the domain owner. 3) Read/Write not allowed for all the other domains. If this bit is not set only DID.." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Assign domain for peripheral" repeat.end repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x38 0x70 0xA8 0xE0 0x118 0x150 0x188 0x1C0 0x1F8 0x230 0x268 0x2A0 0x2D8 0x310 0x348 ) group.long ($2+0x3104)++0x3 line.long 0x0 "RGN_DOM_PER0_$1,Domain Permission Control. It can be only configured by resource manager and domain owner." bitfld.long 0x0 31. "DOM7_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 29.--30. "DOM7_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 28. "DOM7_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 27. "DOM6_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 25.--26. "DOM6_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" newline bitfld.long 0x0 24. "DOM6_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 23. "DOM5_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 21.--22. "DOM5_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 20. "DOM5_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 19. "DOM4_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" newline bitfld.long 0x0 17.--18. "DOM4_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM4_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 15. "DOM3_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 13.--14. "DOM3_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 12. "DOM3_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" newline bitfld.long 0x0 11. "DOM2_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 9.--10. "DOM2_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM2_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 7. "DOM1_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 5.--6. "DOM1_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" newline bitfld.long 0x0 4. "DOM1_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 3. "DOM0_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 1.--2. "DOM0_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM0_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" repeat.end repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x38 0x70 0xA8 0xE0 0x118 0x150 0x188 0x1C0 0x1F8 0x230 0x268 0x2A0 0x2D8 0x310 0x348 ) group.long ($2+0x3108)++0x3 line.long 0x0 "RGN_DOM_PER1_$1,Domain Permission Control. It can be only configured by resource manager and domain owner." bitfld.long 0x0 31. "DOM15_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 29.--30. "DOM15_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 28. "DOM15_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 27. "DOM14_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 25.--26. "DOM14_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" newline bitfld.long 0x0 24. "DOM14_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 23. "DOM13_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 21.--22. "DOM13_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 20. "DOM13_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 19. "DOM12_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" newline bitfld.long 0x0 17.--18. "DOM12_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM12_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 15. "DOM11_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 13.--14. "DOM11_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 12. "DOM11_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" newline bitfld.long 0x0 11. "DOM10_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 9.--10. "DOM10_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM10_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 7. "DOM9_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 5.--6. "DOM9_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" newline bitfld.long 0x0 4. "DOM9_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 3. "DOM8_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 1.--2. "DOM8_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM8_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" repeat.end repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x38 0x70 0xA8 0xE0 0x118 0x150 0x188 0x1C0 0x1F8 0x230 0x268 0x2A0 0x2D8 0x310 0x348 ) group.long ($2+0x310C)++0x3 line.long 0x0 "RGN_SEC_PER0_$1,This register is only used for resource manager to control secure access permission." bitfld.long 0x0 31. "DOM3_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM3_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM3_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM3_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM2_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM2_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM2_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM2_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM1_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM1_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM1_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM1_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM0_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM0_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM0_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM0_SEC_EN,Domain secure permission control enable" "0,1" repeat.end repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x38 0x70 0xA8 0xE0 0x118 0x150 0x188 0x1C0 0x1F8 0x230 0x268 0x2A0 0x2D8 0x310 0x348 ) group.long ($2+0x3110)++0x3 line.long 0x0 "RGN_SEC_PER1_$1,This register is only used for resource manager to control secure access permission." bitfld.long 0x0 31. "DOM7_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM7_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM7_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM7_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM6_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM6_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM6_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM6_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM5_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM5_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM5_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM5_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM4_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM4_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM4_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM4_SEC_EN,Domain secure permission control enable" "0,1" repeat.end repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x38 0x70 0xA8 0xE0 0x118 0x150 0x188 0x1C0 0x1F8 0x230 0x268 0x2A0 0x2D8 0x310 0x348 ) group.long ($2+0x3114)++0x3 line.long 0x0 "RGN_SEC_PER2_$1,This register is only used for resource manager to control secure access permission." bitfld.long 0x0 31. "DOM11_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM11_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM11_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM11_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM10_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM10_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM10_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM10_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM9_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM9_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM9_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM9_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM8_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM8_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM8_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM8_SEC_EN,Domain secure permission control enable" "0,1" repeat.end repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x38 0x70 0xA8 0xE0 0x118 0x150 0x188 0x1C0 0x1F8 0x230 0x268 0x2A0 0x2D8 0x310 0x348 ) group.long ($2+0x3118)++0x3 line.long 0x0 "RGN_SEC_PER3_$1,This register is only used for resource manager to control secure access permission." bitfld.long 0x0 31. "DOM15_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM15_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM15_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM15_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM14_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM14_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM14_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM14_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM13_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM13_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM13_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM13_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM12_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM12_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM12_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM12_SEC_EN,Domain secure permission control enable" "0,1" repeat.end repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x38 0x70 0xA8 0xE0 0x118 0x150 0x188 0x1C0 0x1F8 0x230 0x268 0x2A0 0x2D8 0x310 0x348 ) group.long ($2+0x311C)++0x3 line.long 0x0 "RGN_PRI_PER0_$1,This register is only used for resource manager to control privileged access permission." bitfld.long 0x0 31. "DOM3_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM3_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM3_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM3_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM2_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM2_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM2_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM2_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM1_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM1_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM1_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM1_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM0_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM0_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM0_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM0_PRI_EN,Domain privileged permission control enable" "0,1" repeat.end repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x38 0x70 0xA8 0xE0 0x118 0x150 0x188 0x1C0 0x1F8 0x230 0x268 0x2A0 0x2D8 0x310 0x348 ) group.long ($2+0x3120)++0x3 line.long 0x0 "RGN_PRI_PER1_$1,This register is only used for resource manager to control privileged access permission." bitfld.long 0x0 31. "DOM7_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM7_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM7_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM7_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM6_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM6_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM6_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM6_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM5_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM5_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM5_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM5_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM4_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM4_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM4_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM4_PRI_EN,Domain privileged permission control enable" "0,1" repeat.end repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x38 0x70 0xA8 0xE0 0x118 0x150 0x188 0x1C0 0x1F8 0x230 0x268 0x2A0 0x2D8 0x310 0x348 ) group.long ($2+0x3124)++0x3 line.long 0x0 "RGN_PRI_PER2_$1,This register is only used for resource manager to control privileged access permission." bitfld.long 0x0 31. "DOM11_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM11_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM11_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM11_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM10_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM10_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM10_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM10_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM9_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM9_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM9_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM9_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM8_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM8_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM8_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM8_PRI_EN,Domain privileged permission control enable" "0,1" repeat.end repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x38 0x70 0xA8 0xE0 0x118 0x150 0x188 0x1C0 0x1F8 0x230 0x268 0x2A0 0x2D8 0x310 0x348 ) group.long ($2+0x3128)++0x3 line.long 0x0 "RGN_PRI_PER3_$1,This register is only used for resource manager to control privileged access permission." bitfld.long 0x0 31. "DOM15_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM15_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM15_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM15_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM14_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM14_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM14_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM14_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM13_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM13_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM13_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM13_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM12_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM12_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM12_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM12_PRI_EN,Domain privileged permission control enable" "0,1" repeat.end repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x38 0x70 0xA8 0xE0 0x118 0x150 0x188 0x1C0 0x1F8 0x230 0x268 0x2A0 0x2D8 0x310 0x348 ) group.long ($2+0x312C)++0x3 line.long 0x0 "RGN_DOM_SEC_PER_$1,This register is only used for domain master to control secure access permission. When the domain master write this register. it only changes the secure permission for itself. When the domain master read this register. it gets.." bitfld.long 0x0 7. "DOM_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" newline bitfld.long 0x0 0. "DOM_SEC_EN,Domain secure permission control enable" "0,1" repeat.end repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x38 0x70 0xA8 0xE0 0x118 0x150 0x188 0x1C0 0x1F8 0x230 0x268 0x2A0 0x2D8 0x310 0x348 ) group.long ($2+0x3130)++0x3 line.long 0x0 "RGN_DOM_PRI_PER_$1,This register is only used for domain master to control secure access permission. When the domain master write this register. it only changes the secure permission for itself. When the domain master read this register. it gets.." bitfld.long 0x0 7. "DOM_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" newline bitfld.long 0x0 0. "DOM_PRI_EN,Domain privileged permission control enable" "0,1" repeat.end repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x38 0x70 0xA8 0xE0 0x118 0x150 0x188 0x1C0 0x1F8 0x230 0x268 0x2A0 0x2D8 0x310 0x348 ) group.long ($2+0x3134)++0x3 line.long 0x0 "RGN_DOM_ASSIGN_$1,Use to assign domain for accessing DOM_SEC_PER and DOM_PRI_PER register. Only resource manager. group manager and domain owner can access this register. For write. group manager must write its owen domain ID. otherwise write accessing.." hexmask.long.byte 0x0 0.--3. 1. "DID,accessing DOM_SEC_PER and DOM_PRI_PER register" repeat.end tree.end tree "RPC_SAFETY_SCR" base ad:0xFCA00000 repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x4 0x8 0xC 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C ) group.long ($2)++0x3 line.long 0x0 "REGG0_DOM_$1,Assign domain for CKGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1A 0x1B 0x1C 0x1D 0x1E 0x1F )(list 0x40 0x44 0x48 0x4C 0x50 0x54 0x58 0x5C 0x60 0x64 0x68 0x6C 0x70 0x74 0x78 0x7C ) group.long ($2)++0x3 line.long 0x0 "REGG0_DOM_$1,Assign domain for CKGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x20 0x21 0x22 0x23 0x24 0x25 0x26 0x27 0x28 0x29 0x2A 0x2B 0x2C 0x2D 0x2E 0x2F )(list 0x80 0x84 0x88 0x8C 0x90 0x94 0x98 0x9C 0xA0 0xA4 0xA8 0xAC 0xB0 0xB4 0xB8 0xBC ) group.long ($2)++0x3 line.long 0x0 "REGG0_DOM_$1,Assign domain for CKGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x30 0x31 0x32 0x33 0x34 0x35 0x36 0x37 0x38 0x39 0x3A 0x3B 0x3C 0x3D 0x3E 0x3F )(list 0xC0 0xC4 0xC8 0xCC 0xD0 0xD4 0xD8 0xDC 0xE0 0xE4 0xE8 0xEC 0xF0 0xF4 0xF8 0xFC ) group.long ($2)++0x3 line.long 0x0 "REGG0_DOM_$1,Assign domain for CKGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x40 0x41 0x42 0x43 0x44 0x45 0x46 0x47 0x48 0x49 0x4A 0x4B 0x4C 0x4D 0x4E 0x4F )(list 0x100 0x104 0x108 0x10C 0x110 0x114 0x118 0x11C 0x120 0x124 0x128 0x12C 0x130 0x134 0x138 0x13C ) group.long ($2)++0x3 line.long 0x0 "REGG0_DOM_$1,Assign domain for CKGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x50 0x51 0x52 0x53 0x54 0x55 0x56 0x57 0x58 0x59 0x5A 0x5B 0x5C 0x5D 0x5E 0x5F )(list 0x140 0x144 0x148 0x14C 0x150 0x154 0x158 0x15C 0x160 0x164 0x168 0x16C 0x170 0x174 0x178 0x17C ) group.long ($2)++0x3 line.long 0x0 "REGG0_DOM_$1,Assign domain for CKGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x60 0x61 0x62 0x63 0x64 0x65 0x66 0x67 0x68 0x69 0x6A 0x6B 0x6C 0x6D 0x6E 0x6F )(list 0x180 0x184 0x188 0x18C 0x190 0x194 0x198 0x19C 0x1A0 0x1A4 0x1A8 0x1AC 0x1B0 0x1B4 0x1B8 0x1BC ) group.long ($2)++0x3 line.long 0x0 "REGG0_DOM_$1,Assign domain for CKGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x70 0x71 0x72 0x73 0x74 0x75 0x76 0x77 0x78 0x79 0x7A 0x7B 0x7C 0x7D 0x7E 0x7F )(list 0x1C0 0x1C4 0x1C8 0x1CC 0x1D0 0x1D4 0x1D8 0x1DC 0x1E0 0x1E4 0x1E8 0x1EC 0x1F0 0x1F4 0x1F8 0x1FC ) group.long ($2)++0x3 line.long 0x0 "REGG0_DOM_$1,Assign domain for CKGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x80 0x81 0x82 0x83 0x84 0x85 0x86 0x87 0x88 0x89 0x8A 0x8B 0x8C 0x8D 0x8E 0x8F )(list 0x200 0x204 0x208 0x20C 0x210 0x214 0x218 0x21C 0x220 0x224 0x228 0x22C 0x230 0x234 0x238 0x23C ) group.long ($2)++0x3 line.long 0x0 "REGG0_DOM_$1,Assign domain for CKGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x90 0x91 0x92 0x93 0x94 0x95 0x96 0x97 0x98 0x99 0x9A 0x9B 0x9C 0x9D 0x9E 0x9F )(list 0x240 0x244 0x248 0x24C 0x250 0x254 0x258 0x25C 0x260 0x264 0x268 0x26C 0x270 0x274 0x278 0x27C ) group.long ($2)++0x3 line.long 0x0 "REGG0_DOM_$1,Assign domain for CKGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xA0 0xA1 0xA2 0xA3 0xA4 0xA5 0xA6 0xA7 0xA8 0xA9 0xAA 0xAB 0xAC 0xAD 0xAE 0xAF )(list 0x280 0x284 0x288 0x28C 0x290 0x294 0x298 0x29C 0x2A0 0x2A4 0x2A8 0x2AC 0x2B0 0x2B4 0x2B8 0x2BC ) group.long ($2)++0x3 line.long 0x0 "REGG0_DOM_$1,Assign domain for CKGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xB0 0xB1 0xB2 0xB3 0xB4 0xB5 0xB6 0xB7 0xB8 0xB9 0xBA 0xBB 0xBC 0xBD 0xBE 0xBF )(list 0x2C0 0x2C4 0x2C8 0x2CC 0x2D0 0x2D4 0x2D8 0x2DC 0x2E0 0x2E4 0x2E8 0x2EC 0x2F0 0x2F4 0x2F8 0x2FC ) group.long ($2)++0x3 line.long 0x0 "REGG0_DOM_$1,Assign domain for CKGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xC0 0xC1 0xC2 0xC3 0xC4 0xC5 0xC6 0xC7 0xC8 0xC9 0xCA 0xCB 0xCC 0xCD 0xCE 0xCF )(list 0x300 0x304 0x308 0x30C 0x310 0x314 0x318 0x31C 0x320 0x324 0x328 0x32C 0x330 0x334 0x338 0x33C ) group.long ($2)++0x3 line.long 0x0 "REGG0_DOM_$1,Assign domain for CKGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xD0 0xD1 0xD2 0xD3 0xD4 0xD5 0xD6 0xD7 0xD8 0xD9 0xDA 0xDB 0xDC 0xDD 0xDE 0xDF )(list 0x340 0x344 0x348 0x34C 0x350 0x354 0x358 0x35C 0x360 0x364 0x368 0x36C 0x370 0x374 0x378 0x37C ) group.long ($2)++0x3 line.long 0x0 "REGG0_DOM_$1,Assign domain for CKGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xE0 0xE1 0xE2 0xE3 0xE4 0xE5 0xE6 0xE7 0xE8 0xE9 0xEA 0xEB 0xEC 0xED 0xEE 0xEF )(list 0x380 0x384 0x388 0x38C 0x390 0x394 0x398 0x39C 0x3A0 0x3A4 0x3A8 0x3AC 0x3B0 0x3B4 0x3B8 0x3BC ) group.long ($2)++0x3 line.long 0x0 "REGG0_DOM_$1,Assign domain for CKGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xF0 0xF1 0xF2 0xF3 0xF4 0xF5 0xF6 0xF7 0xF8 0xF9 0xFA 0xFB 0xFC 0xFD 0xFE 0xFF )(list 0x3C0 0x3C4 0x3C8 0x3CC 0x3D0 0x3D4 0x3D8 0x3DC 0x3E0 0x3E4 0x3E8 0x3EC 0x3F0 0x3F4 0x3F8 0x3FC ) group.long ($2)++0x3 line.long 0x0 "REGG0_DOM_$1,Assign domain for CKGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x4 0x8 0xC 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C ) group.long ($2+0x400)++0x3 line.long 0x0 "REGG1_DOM_$1,Assign domain for CKGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1A 0x1B 0x1C 0x1D 0x1E 0x1F )(list 0x40 0x44 0x48 0x4C 0x50 0x54 0x58 0x5C 0x60 0x64 0x68 0x6C 0x70 0x74 0x78 0x7C ) group.long ($2+0x400)++0x3 line.long 0x0 "REGG1_DOM_$1,Assign domain for CKGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x20 0x21 0x22 0x23 0x24 0x25 0x26 0x27 0x28 0x29 0x2A 0x2B 0x2C 0x2D 0x2E 0x2F )(list 0x80 0x84 0x88 0x8C 0x90 0x94 0x98 0x9C 0xA0 0xA4 0xA8 0xAC 0xB0 0xB4 0xB8 0xBC ) group.long ($2+0x400)++0x3 line.long 0x0 "REGG1_DOM_$1,Assign domain for CKGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x30 0x31 0x32 0x33 0x34 0x35 0x36 0x37 0x38 0x39 0x3A 0x3B 0x3C 0x3D 0x3E 0x3F )(list 0xC0 0xC4 0xC8 0xCC 0xD0 0xD4 0xD8 0xDC 0xE0 0xE4 0xE8 0xEC 0xF0 0xF4 0xF8 0xFC ) group.long ($2+0x400)++0x3 line.long 0x0 "REGG1_DOM_$1,Assign domain for CKGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x40 0x41 0x42 0x43 0x44 0x45 0x46 0x47 0x48 0x49 0x4A 0x4B 0x4C 0x4D 0x4E 0x4F )(list 0x100 0x104 0x108 0x10C 0x110 0x114 0x118 0x11C 0x120 0x124 0x128 0x12C 0x130 0x134 0x138 0x13C ) group.long ($2+0x400)++0x3 line.long 0x0 "REGG1_DOM_$1,Assign domain for CKGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x50 0x51 0x52 0x53 0x54 0x55 0x56 0x57 0x58 0x59 0x5A 0x5B 0x5C 0x5D 0x5E 0x5F )(list 0x140 0x144 0x148 0x14C 0x150 0x154 0x158 0x15C 0x160 0x164 0x168 0x16C 0x170 0x174 0x178 0x17C ) group.long ($2+0x400)++0x3 line.long 0x0 "REGG1_DOM_$1,Assign domain for CKGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x60 0x61 0x62 0x63 0x64 0x65 0x66 0x67 0x68 0x69 0x6A 0x6B 0x6C 0x6D 0x6E 0x6F )(list 0x180 0x184 0x188 0x18C 0x190 0x194 0x198 0x19C 0x1A0 0x1A4 0x1A8 0x1AC 0x1B0 0x1B4 0x1B8 0x1BC ) group.long ($2+0x400)++0x3 line.long 0x0 "REGG1_DOM_$1,Assign domain for CKGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x70 0x71 0x72 0x73 0x74 0x75 0x76 0x77 0x78 0x79 0x7A 0x7B 0x7C 0x7D 0x7E 0x7F )(list 0x1C0 0x1C4 0x1C8 0x1CC 0x1D0 0x1D4 0x1D8 0x1DC 0x1E0 0x1E4 0x1E8 0x1EC 0x1F0 0x1F4 0x1F8 0x1FC ) group.long ($2+0x400)++0x3 line.long 0x0 "REGG1_DOM_$1,Assign domain for CKGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x80 0x81 0x82 0x83 0x84 0x85 0x86 0x87 0x88 0x89 0x8A 0x8B 0x8C 0x8D 0x8E 0x8F )(list 0x200 0x204 0x208 0x20C 0x210 0x214 0x218 0x21C 0x220 0x224 0x228 0x22C 0x230 0x234 0x238 0x23C ) group.long ($2+0x400)++0x3 line.long 0x0 "REGG1_DOM_$1,Assign domain for CKGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x90 0x91 0x92 0x93 0x94 0x95 0x96 0x97 0x98 0x99 0x9A 0x9B 0x9C 0x9D 0x9E 0x9F )(list 0x240 0x244 0x248 0x24C 0x250 0x254 0x258 0x25C 0x260 0x264 0x268 0x26C 0x270 0x274 0x278 0x27C ) group.long ($2+0x400)++0x3 line.long 0x0 "REGG1_DOM_$1,Assign domain for CKGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xA0 0xA1 0xA2 0xA3 0xA4 0xA5 0xA6 0xA7 0xA8 0xA9 0xAA 0xAB 0xAC 0xAD 0xAE 0xAF )(list 0x280 0x284 0x288 0x28C 0x290 0x294 0x298 0x29C 0x2A0 0x2A4 0x2A8 0x2AC 0x2B0 0x2B4 0x2B8 0x2BC ) group.long ($2+0x400)++0x3 line.long 0x0 "REGG1_DOM_$1,Assign domain for CKGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xB0 0xB1 0xB2 0xB3 0xB4 0xB5 0xB6 0xB7 0xB8 0xB9 0xBA 0xBB 0xBC 0xBD 0xBE 0xBF )(list 0x2C0 0x2C4 0x2C8 0x2CC 0x2D0 0x2D4 0x2D8 0x2DC 0x2E0 0x2E4 0x2E8 0x2EC 0x2F0 0x2F4 0x2F8 0x2FC ) group.long ($2+0x400)++0x3 line.long 0x0 "REGG1_DOM_$1,Assign domain for CKGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xC0 0xC1 0xC2 0xC3 0xC4 0xC5 0xC6 0xC7 0xC8 0xC9 0xCA 0xCB 0xCC 0xCD 0xCE 0xCF )(list 0x300 0x304 0x308 0x30C 0x310 0x314 0x318 0x31C 0x320 0x324 0x328 0x32C 0x330 0x334 0x338 0x33C ) group.long ($2+0x400)++0x3 line.long 0x0 "REGG1_DOM_$1,Assign domain for CKGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xD0 0xD1 0xD2 0xD3 0xD4 0xD5 0xD6 0xD7 0xD8 0xD9 0xDA 0xDB 0xDC 0xDD 0xDE 0xDF )(list 0x340 0x344 0x348 0x34C 0x350 0x354 0x358 0x35C 0x360 0x364 0x368 0x36C 0x370 0x374 0x378 0x37C ) group.long ($2+0x400)++0x3 line.long 0x0 "REGG1_DOM_$1,Assign domain for CKGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xE0 0xE1 0xE2 0xE3 0xE4 0xE5 0xE6 0xE7 0xE8 0xE9 0xEA 0xEB 0xEC 0xED 0xEE 0xEF )(list 0x380 0x384 0x388 0x38C 0x390 0x394 0x398 0x39C 0x3A0 0x3A4 0x3A8 0x3AC 0x3B0 0x3B4 0x3B8 0x3BC ) group.long ($2+0x400)++0x3 line.long 0x0 "REGG1_DOM_$1,Assign domain for CKGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xF0 0xF1 0xF2 0xF3 0xF4 0xF5 0xF6 0xF7 0xF8 0xF9 0xFA 0xFB 0xFC 0xFD 0xFE 0xFF )(list 0x3C0 0x3C4 0x3C8 0x3CC 0x3D0 0x3D4 0x3D8 0x3DC 0x3E0 0x3E4 0x3E8 0x3EC 0x3F0 0x3F4 0x3F8 0x3FC ) group.long ($2+0x400)++0x3 line.long 0x0 "REGG1_DOM_$1,Assign domain for CKGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x4 0x8 0xC 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C ) group.long ($2+0x800)++0x3 line.long 0x0 "REGG2_DOM_$1,Assign domain for SCR registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1A 0x1B 0x1C 0x1D 0x1E 0x1F )(list 0x40 0x44 0x48 0x4C 0x50 0x54 0x58 0x5C 0x60 0x64 0x68 0x6C 0x70 0x74 0x78 0x7C ) group.long ($2+0x800)++0x3 line.long 0x0 "REGG2_DOM_$1,Assign domain for SCR registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x20 0x21 0x22 0x23 0x24 0x25 0x26 0x27 0x28 0x29 0x2A 0x2B 0x2C 0x2D 0x2E 0x2F )(list 0x80 0x84 0x88 0x8C 0x90 0x94 0x98 0x9C 0xA0 0xA4 0xA8 0xAC 0xB0 0xB4 0xB8 0xBC ) group.long ($2+0x800)++0x3 line.long 0x0 "REGG2_DOM_$1,Assign domain for SCR registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x30 0x31 0x32 0x33 0x34 0x35 0x36 0x37 0x38 0x39 0x3A 0x3B 0x3C 0x3D 0x3E 0x3F )(list 0xC0 0xC4 0xC8 0xCC 0xD0 0xD4 0xD8 0xDC 0xE0 0xE4 0xE8 0xEC 0xF0 0xF4 0xF8 0xFC ) group.long ($2+0x800)++0x3 line.long 0x0 "REGG2_DOM_$1,Assign domain for SCR registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x40 0x41 0x42 0x43 0x44 0x45 0x46 0x47 0x48 0x49 0x4A 0x4B 0x4C 0x4D 0x4E 0x4F )(list 0x100 0x104 0x108 0x10C 0x110 0x114 0x118 0x11C 0x120 0x124 0x128 0x12C 0x130 0x134 0x138 0x13C ) group.long ($2+0x800)++0x3 line.long 0x0 "REGG2_DOM_$1,Assign domain for SCR registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x50 0x51 0x52 0x53 0x54 0x55 0x56 0x57 0x58 0x59 0x5A 0x5B 0x5C 0x5D 0x5E 0x5F )(list 0x140 0x144 0x148 0x14C 0x150 0x154 0x158 0x15C 0x160 0x164 0x168 0x16C 0x170 0x174 0x178 0x17C ) group.long ($2+0x800)++0x3 line.long 0x0 "REGG2_DOM_$1,Assign domain for SCR registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x60 0x61 0x62 0x63 0x64 0x65 0x66 0x67 0x68 0x69 0x6A 0x6B 0x6C 0x6D 0x6E 0x6F )(list 0x180 0x184 0x188 0x18C 0x190 0x194 0x198 0x19C 0x1A0 0x1A4 0x1A8 0x1AC 0x1B0 0x1B4 0x1B8 0x1BC ) group.long ($2+0x800)++0x3 line.long 0x0 "REGG2_DOM_$1,Assign domain for SCR registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x70 0x71 0x72 0x73 0x74 0x75 0x76 0x77 0x78 0x79 0x7A 0x7B 0x7C 0x7D 0x7E 0x7F )(list 0x1C0 0x1C4 0x1C8 0x1CC 0x1D0 0x1D4 0x1D8 0x1DC 0x1E0 0x1E4 0x1E8 0x1EC 0x1F0 0x1F4 0x1F8 0x1FC ) group.long ($2+0x800)++0x3 line.long 0x0 "REGG2_DOM_$1,Assign domain for SCR registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x80 0x81 0x82 0x83 0x84 0x85 0x86 0x87 0x88 0x89 0x8A 0x8B 0x8C 0x8D 0x8E 0x8F )(list 0x200 0x204 0x208 0x20C 0x210 0x214 0x218 0x21C 0x220 0x224 0x228 0x22C 0x230 0x234 0x238 0x23C ) group.long ($2+0x800)++0x3 line.long 0x0 "REGG2_DOM_$1,Assign domain for SCR registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x90 0x91 0x92 0x93 0x94 0x95 0x96 0x97 0x98 0x99 0x9A 0x9B 0x9C 0x9D 0x9E 0x9F )(list 0x240 0x244 0x248 0x24C 0x250 0x254 0x258 0x25C 0x260 0x264 0x268 0x26C 0x270 0x274 0x278 0x27C ) group.long ($2+0x800)++0x3 line.long 0x0 "REGG2_DOM_$1,Assign domain for SCR registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xA0 0xA1 0xA2 0xA3 0xA4 0xA5 0xA6 0xA7 0xA8 0xA9 0xAA 0xAB 0xAC 0xAD 0xAE 0xAF )(list 0x280 0x284 0x288 0x28C 0x290 0x294 0x298 0x29C 0x2A0 0x2A4 0x2A8 0x2AC 0x2B0 0x2B4 0x2B8 0x2BC ) group.long ($2+0x800)++0x3 line.long 0x0 "REGG2_DOM_$1,Assign domain for SCR registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xB0 0xB1 0xB2 0xB3 0xB4 0xB5 0xB6 0xB7 0xB8 0xB9 0xBA 0xBB 0xBC 0xBD 0xBE 0xBF )(list 0x2C0 0x2C4 0x2C8 0x2CC 0x2D0 0x2D4 0x2D8 0x2DC 0x2E0 0x2E4 0x2E8 0x2EC 0x2F0 0x2F4 0x2F8 0x2FC ) group.long ($2+0x800)++0x3 line.long 0x0 "REGG2_DOM_$1,Assign domain for SCR registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xC0 0xC1 0xC2 0xC3 0xC4 0xC5 0xC6 0xC7 0xC8 0xC9 0xCA 0xCB 0xCC 0xCD 0xCE 0xCF )(list 0x300 0x304 0x308 0x30C 0x310 0x314 0x318 0x31C 0x320 0x324 0x328 0x32C 0x330 0x334 0x338 0x33C ) group.long ($2+0x800)++0x3 line.long 0x0 "REGG2_DOM_$1,Assign domain for SCR registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xD0 0xD1 0xD2 0xD3 0xD4 0xD5 0xD6 0xD7 0xD8 0xD9 0xDA 0xDB 0xDC 0xDD 0xDE 0xDF )(list 0x340 0x344 0x348 0x34C 0x350 0x354 0x358 0x35C 0x360 0x364 0x368 0x36C 0x370 0x374 0x378 0x37C ) group.long ($2+0x800)++0x3 line.long 0x0 "REGG2_DOM_$1,Assign domain for SCR registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xE0 0xE1 0xE2 0xE3 0xE4 0xE5 0xE6 0xE7 0xE8 0xE9 0xEA 0xEB 0xEC 0xED 0xEE 0xEF )(list 0x380 0x384 0x388 0x38C 0x390 0x394 0x398 0x39C 0x3A0 0x3A4 0x3A8 0x3AC 0x3B0 0x3B4 0x3B8 0x3BC ) group.long ($2+0x800)++0x3 line.long 0x0 "REGG2_DOM_$1,Assign domain for SCR registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xF0 0xF1 0xF2 0xF3 0xF4 0xF5 0xF6 0xF7 0xF8 0xF9 0xFA 0xFB 0xFC 0xFD 0xFE 0xFF )(list 0x3C0 0x3C4 0x3C8 0x3CC 0x3D0 0x3D4 0x3D8 0x3DC 0x3E0 0x3E4 0x3E8 0x3EC 0x3F0 0x3F4 0x3F8 0x3FC ) group.long ($2+0x800)++0x3 line.long 0x0 "REGG2_DOM_$1,Assign domain for SCR registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x4 0x8 0xC 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C ) group.long ($2+0xC00)++0x3 line.long 0x0 "REGG3_DOM_$1,Assign domain for SCR registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1A 0x1B 0x1C 0x1D 0x1E 0x1F )(list 0x40 0x44 0x48 0x4C 0x50 0x54 0x58 0x5C 0x60 0x64 0x68 0x6C 0x70 0x74 0x78 0x7C ) group.long ($2+0xC00)++0x3 line.long 0x0 "REGG3_DOM_$1,Assign domain for SCR registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x20 0x21 0x22 0x23 0x24 0x25 0x26 0x27 0x28 0x29 0x2A 0x2B 0x2C 0x2D 0x2E 0x2F )(list 0x80 0x84 0x88 0x8C 0x90 0x94 0x98 0x9C 0xA0 0xA4 0xA8 0xAC 0xB0 0xB4 0xB8 0xBC ) group.long ($2+0xC00)++0x3 line.long 0x0 "REGG3_DOM_$1,Assign domain for SCR registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x30 0x31 0x32 0x33 0x34 0x35 0x36 0x37 0x38 0x39 0x3A 0x3B 0x3C 0x3D 0x3E 0x3F )(list 0xC0 0xC4 0xC8 0xCC 0xD0 0xD4 0xD8 0xDC 0xE0 0xE4 0xE8 0xEC 0xF0 0xF4 0xF8 0xFC ) group.long ($2+0xC00)++0x3 line.long 0x0 "REGG3_DOM_$1,Assign domain for SCR registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x40 0x41 0x42 0x43 0x44 0x45 0x46 0x47 0x48 0x49 0x4A 0x4B 0x4C 0x4D 0x4E 0x4F )(list 0x100 0x104 0x108 0x10C 0x110 0x114 0x118 0x11C 0x120 0x124 0x128 0x12C 0x130 0x134 0x138 0x13C ) group.long ($2+0xC00)++0x3 line.long 0x0 "REGG3_DOM_$1,Assign domain for SCR registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x50 0x51 0x52 0x53 0x54 0x55 0x56 0x57 0x58 0x59 0x5A 0x5B 0x5C 0x5D 0x5E 0x5F )(list 0x140 0x144 0x148 0x14C 0x150 0x154 0x158 0x15C 0x160 0x164 0x168 0x16C 0x170 0x174 0x178 0x17C ) group.long ($2+0xC00)++0x3 line.long 0x0 "REGG3_DOM_$1,Assign domain for SCR registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x60 0x61 0x62 0x63 0x64 0x65 0x66 0x67 0x68 0x69 0x6A 0x6B 0x6C 0x6D 0x6E 0x6F )(list 0x180 0x184 0x188 0x18C 0x190 0x194 0x198 0x19C 0x1A0 0x1A4 0x1A8 0x1AC 0x1B0 0x1B4 0x1B8 0x1BC ) group.long ($2+0xC00)++0x3 line.long 0x0 "REGG3_DOM_$1,Assign domain for SCR registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x70 0x71 0x72 0x73 0x74 0x75 0x76 0x77 0x78 0x79 0x7A 0x7B 0x7C 0x7D 0x7E 0x7F )(list 0x1C0 0x1C4 0x1C8 0x1CC 0x1D0 0x1D4 0x1D8 0x1DC 0x1E0 0x1E4 0x1E8 0x1EC 0x1F0 0x1F4 0x1F8 0x1FC ) group.long ($2+0xC00)++0x3 line.long 0x0 "REGG3_DOM_$1,Assign domain for SCR registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x80 0x81 0x82 0x83 0x84 0x85 0x86 0x87 0x88 0x89 0x8A 0x8B 0x8C 0x8D 0x8E 0x8F )(list 0x200 0x204 0x208 0x20C 0x210 0x214 0x218 0x21C 0x220 0x224 0x228 0x22C 0x230 0x234 0x238 0x23C ) group.long ($2+0xC00)++0x3 line.long 0x0 "REGG3_DOM_$1,Assign domain for SCR registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x90 0x91 0x92 0x93 0x94 0x95 0x96 0x97 0x98 0x99 0x9A 0x9B 0x9C 0x9D 0x9E 0x9F )(list 0x240 0x244 0x248 0x24C 0x250 0x254 0x258 0x25C 0x260 0x264 0x268 0x26C 0x270 0x274 0x278 0x27C ) group.long ($2+0xC00)++0x3 line.long 0x0 "REGG3_DOM_$1,Assign domain for SCR registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xA0 0xA1 0xA2 0xA3 0xA4 0xA5 0xA6 0xA7 0xA8 0xA9 0xAA 0xAB 0xAC 0xAD 0xAE 0xAF )(list 0x280 0x284 0x288 0x28C 0x290 0x294 0x298 0x29C 0x2A0 0x2A4 0x2A8 0x2AC 0x2B0 0x2B4 0x2B8 0x2BC ) group.long ($2+0xC00)++0x3 line.long 0x0 "REGG3_DOM_$1,Assign domain for SCR registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xB0 0xB1 0xB2 0xB3 0xB4 0xB5 0xB6 0xB7 0xB8 0xB9 0xBA 0xBB 0xBC 0xBD 0xBE 0xBF )(list 0x2C0 0x2C4 0x2C8 0x2CC 0x2D0 0x2D4 0x2D8 0x2DC 0x2E0 0x2E4 0x2E8 0x2EC 0x2F0 0x2F4 0x2F8 0x2FC ) group.long ($2+0xC00)++0x3 line.long 0x0 "REGG3_DOM_$1,Assign domain for SCR registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xC0 0xC1 0xC2 0xC3 0xC4 0xC5 0xC6 0xC7 0xC8 0xC9 0xCA 0xCB 0xCC 0xCD 0xCE 0xCF )(list 0x300 0x304 0x308 0x30C 0x310 0x314 0x318 0x31C 0x320 0x324 0x328 0x32C 0x330 0x334 0x338 0x33C ) group.long ($2+0xC00)++0x3 line.long 0x0 "REGG3_DOM_$1,Assign domain for SCR registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xD0 0xD1 0xD2 0xD3 0xD4 0xD5 0xD6 0xD7 0xD8 0xD9 0xDA 0xDB 0xDC 0xDD 0xDE 0xDF )(list 0x340 0x344 0x348 0x34C 0x350 0x354 0x358 0x35C 0x360 0x364 0x368 0x36C 0x370 0x374 0x378 0x37C ) group.long ($2+0xC00)++0x3 line.long 0x0 "REGG3_DOM_$1,Assign domain for SCR registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xE0 0xE1 0xE2 0xE3 0xE4 0xE5 0xE6 0xE7 0xE8 0xE9 0xEA 0xEB 0xEC 0xED 0xEE 0xEF )(list 0x380 0x384 0x388 0x38C 0x390 0x394 0x398 0x39C 0x3A0 0x3A4 0x3A8 0x3AC 0x3B0 0x3B4 0x3B8 0x3BC ) group.long ($2+0xC00)++0x3 line.long 0x0 "REGG3_DOM_$1,Assign domain for SCR registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xF0 0xF1 0xF2 0xF3 0xF4 0xF5 0xF6 0xF7 0xF8 0xF9 0xFA 0xFB 0xFC 0xFD 0xFE 0xFF )(list 0x3C0 0x3C4 0x3C8 0x3CC 0x3D0 0x3D4 0x3D8 0x3DC 0x3E0 0x3E4 0x3E8 0x3EC 0x3F0 0x3F4 0x3F8 0x3FC ) group.long ($2+0xC00)++0x3 line.long 0x0 "REGG3_DOM_$1,Assign domain for SCR registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x4 0x8 0xC 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C ) group.long ($2+0x1000)++0x3 line.long 0x0 "REGG4_DOM_$1,Assign domain for RSTGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1A 0x1B 0x1C 0x1D 0x1E 0x1F )(list 0x40 0x44 0x48 0x4C 0x50 0x54 0x58 0x5C 0x60 0x64 0x68 0x6C 0x70 0x74 0x78 0x7C ) group.long ($2+0x1000)++0x3 line.long 0x0 "REGG4_DOM_$1,Assign domain for RSTGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x20 0x21 0x22 0x23 0x24 0x25 0x26 0x27 0x28 0x29 0x2A 0x2B 0x2C 0x2D 0x2E 0x2F )(list 0x80 0x84 0x88 0x8C 0x90 0x94 0x98 0x9C 0xA0 0xA4 0xA8 0xAC 0xB0 0xB4 0xB8 0xBC ) group.long ($2+0x1000)++0x3 line.long 0x0 "REGG4_DOM_$1,Assign domain for RSTGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x30 0x31 0x32 0x33 0x34 0x35 0x36 0x37 0x38 0x39 0x3A 0x3B 0x3C 0x3D 0x3E 0x3F )(list 0xC0 0xC4 0xC8 0xCC 0xD0 0xD4 0xD8 0xDC 0xE0 0xE4 0xE8 0xEC 0xF0 0xF4 0xF8 0xFC ) group.long ($2+0x1000)++0x3 line.long 0x0 "REGG4_DOM_$1,Assign domain for RSTGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x40 0x41 0x42 0x43 0x44 0x45 0x46 0x47 0x48 0x49 0x4A 0x4B 0x4C 0x4D 0x4E 0x4F )(list 0x100 0x104 0x108 0x10C 0x110 0x114 0x118 0x11C 0x120 0x124 0x128 0x12C 0x130 0x134 0x138 0x13C ) group.long ($2+0x1000)++0x3 line.long 0x0 "REGG4_DOM_$1,Assign domain for RSTGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x50 0x51 0x52 0x53 0x54 0x55 0x56 0x57 0x58 0x59 0x5A 0x5B 0x5C 0x5D 0x5E 0x5F )(list 0x140 0x144 0x148 0x14C 0x150 0x154 0x158 0x15C 0x160 0x164 0x168 0x16C 0x170 0x174 0x178 0x17C ) group.long ($2+0x1000)++0x3 line.long 0x0 "REGG4_DOM_$1,Assign domain for RSTGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x60 0x61 0x62 0x63 0x64 0x65 0x66 0x67 0x68 0x69 0x6A 0x6B 0x6C 0x6D 0x6E 0x6F )(list 0x180 0x184 0x188 0x18C 0x190 0x194 0x198 0x19C 0x1A0 0x1A4 0x1A8 0x1AC 0x1B0 0x1B4 0x1B8 0x1BC ) group.long ($2+0x1000)++0x3 line.long 0x0 "REGG4_DOM_$1,Assign domain for RSTGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x70 0x71 0x72 0x73 0x74 0x75 0x76 0x77 0x78 0x79 0x7A 0x7B 0x7C 0x7D 0x7E 0x7F )(list 0x1C0 0x1C4 0x1C8 0x1CC 0x1D0 0x1D4 0x1D8 0x1DC 0x1E0 0x1E4 0x1E8 0x1EC 0x1F0 0x1F4 0x1F8 0x1FC ) group.long ($2+0x1000)++0x3 line.long 0x0 "REGG4_DOM_$1,Assign domain for RSTGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x80 0x81 0x82 0x83 0x84 0x85 0x86 0x87 0x88 0x89 0x8A 0x8B 0x8C 0x8D 0x8E 0x8F )(list 0x200 0x204 0x208 0x20C 0x210 0x214 0x218 0x21C 0x220 0x224 0x228 0x22C 0x230 0x234 0x238 0x23C ) group.long ($2+0x1000)++0x3 line.long 0x0 "REGG4_DOM_$1,Assign domain for RSTGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x90 0x91 0x92 0x93 0x94 0x95 0x96 0x97 0x98 0x99 0x9A 0x9B 0x9C 0x9D 0x9E 0x9F )(list 0x240 0x244 0x248 0x24C 0x250 0x254 0x258 0x25C 0x260 0x264 0x268 0x26C 0x270 0x274 0x278 0x27C ) group.long ($2+0x1000)++0x3 line.long 0x0 "REGG4_DOM_$1,Assign domain for RSTGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xA0 0xA1 0xA2 0xA3 0xA4 0xA5 0xA6 0xA7 0xA8 0xA9 0xAA 0xAB 0xAC 0xAD 0xAE 0xAF )(list 0x280 0x284 0x288 0x28C 0x290 0x294 0x298 0x29C 0x2A0 0x2A4 0x2A8 0x2AC 0x2B0 0x2B4 0x2B8 0x2BC ) group.long ($2+0x1000)++0x3 line.long 0x0 "REGG4_DOM_$1,Assign domain for RSTGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xB0 0xB1 0xB2 0xB3 0xB4 0xB5 0xB6 0xB7 0xB8 0xB9 0xBA 0xBB 0xBC 0xBD 0xBE 0xBF )(list 0x2C0 0x2C4 0x2C8 0x2CC 0x2D0 0x2D4 0x2D8 0x2DC 0x2E0 0x2E4 0x2E8 0x2EC 0x2F0 0x2F4 0x2F8 0x2FC ) group.long ($2+0x1000)++0x3 line.long 0x0 "REGG4_DOM_$1,Assign domain for RSTGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xC0 0xC1 0xC2 0xC3 0xC4 0xC5 0xC6 0xC7 0xC8 0xC9 0xCA 0xCB 0xCC 0xCD 0xCE 0xCF )(list 0x300 0x304 0x308 0x30C 0x310 0x314 0x318 0x31C 0x320 0x324 0x328 0x32C 0x330 0x334 0x338 0x33C ) group.long ($2+0x1000)++0x3 line.long 0x0 "REGG4_DOM_$1,Assign domain for RSTGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xD0 0xD1 0xD2 0xD3 0xD4 0xD5 0xD6 0xD7 0xD8 0xD9 0xDA 0xDB 0xDC 0xDD 0xDE 0xDF )(list 0x340 0x344 0x348 0x34C 0x350 0x354 0x358 0x35C 0x360 0x364 0x368 0x36C 0x370 0x374 0x378 0x37C ) group.long ($2+0x1000)++0x3 line.long 0x0 "REGG4_DOM_$1,Assign domain for RSTGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xE0 0xE1 0xE2 0xE3 0xE4 0xE5 0xE6 0xE7 0xE8 0xE9 0xEA 0xEB 0xEC 0xED 0xEE 0xEF )(list 0x380 0x384 0x388 0x38C 0x390 0x394 0x398 0x39C 0x3A0 0x3A4 0x3A8 0x3AC 0x3B0 0x3B4 0x3B8 0x3BC ) group.long ($2+0x1000)++0x3 line.long 0x0 "REGG4_DOM_$1,Assign domain for RSTGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xF0 0xF1 0xF2 0xF3 0xF4 0xF5 0xF6 0xF7 0xF8 0xF9 0xFA 0xFB 0xFC 0xFD 0xFE 0xFF )(list 0x3C0 0x3C4 0x3C8 0x3CC 0x3D0 0x3D4 0x3D8 0x3DC 0x3E0 0x3E4 0x3E8 0x3EC 0x3F0 0x3F4 0x3F8 0x3FC ) group.long ($2+0x1000)++0x3 line.long 0x0 "REGG4_DOM_$1,Assign domain for RSTGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x4 0x8 0xC 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C ) group.long ($2+0x1400)++0x3 line.long 0x0 "REGG5_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1A 0x1B 0x1C 0x1D 0x1E 0x1F )(list 0x40 0x44 0x48 0x4C 0x50 0x54 0x58 0x5C 0x60 0x64 0x68 0x6C 0x70 0x74 0x78 0x7C ) group.long ($2+0x1400)++0x3 line.long 0x0 "REGG5_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x20 0x21 0x22 0x23 0x24 0x25 0x26 0x27 0x28 0x29 0x2A 0x2B 0x2C 0x2D 0x2E 0x2F )(list 0x80 0x84 0x88 0x8C 0x90 0x94 0x98 0x9C 0xA0 0xA4 0xA8 0xAC 0xB0 0xB4 0xB8 0xBC ) group.long ($2+0x1400)++0x3 line.long 0x0 "REGG5_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x30 0x31 0x32 0x33 0x34 0x35 0x36 0x37 0x38 0x39 0x3A 0x3B 0x3C 0x3D 0x3E 0x3F )(list 0xC0 0xC4 0xC8 0xCC 0xD0 0xD4 0xD8 0xDC 0xE0 0xE4 0xE8 0xEC 0xF0 0xF4 0xF8 0xFC ) group.long ($2+0x1400)++0x3 line.long 0x0 "REGG5_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x40 0x41 0x42 0x43 0x44 0x45 0x46 0x47 0x48 0x49 0x4A 0x4B 0x4C 0x4D 0x4E 0x4F )(list 0x100 0x104 0x108 0x10C 0x110 0x114 0x118 0x11C 0x120 0x124 0x128 0x12C 0x130 0x134 0x138 0x13C ) group.long ($2+0x1400)++0x3 line.long 0x0 "REGG5_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x50 0x51 0x52 0x53 0x54 0x55 0x56 0x57 0x58 0x59 0x5A 0x5B 0x5C 0x5D 0x5E 0x5F )(list 0x140 0x144 0x148 0x14C 0x150 0x154 0x158 0x15C 0x160 0x164 0x168 0x16C 0x170 0x174 0x178 0x17C ) group.long ($2+0x1400)++0x3 line.long 0x0 "REGG5_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x60 0x61 0x62 0x63 0x64 0x65 0x66 0x67 0x68 0x69 0x6A 0x6B 0x6C 0x6D 0x6E 0x6F )(list 0x180 0x184 0x188 0x18C 0x190 0x194 0x198 0x19C 0x1A0 0x1A4 0x1A8 0x1AC 0x1B0 0x1B4 0x1B8 0x1BC ) group.long ($2+0x1400)++0x3 line.long 0x0 "REGG5_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x70 0x71 0x72 0x73 0x74 0x75 0x76 0x77 0x78 0x79 0x7A 0x7B 0x7C 0x7D 0x7E 0x7F )(list 0x1C0 0x1C4 0x1C8 0x1CC 0x1D0 0x1D4 0x1D8 0x1DC 0x1E0 0x1E4 0x1E8 0x1EC 0x1F0 0x1F4 0x1F8 0x1FC ) group.long ($2+0x1400)++0x3 line.long 0x0 "REGG5_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x80 0x81 0x82 0x83 0x84 0x85 0x86 0x87 0x88 0x89 0x8A 0x8B 0x8C 0x8D 0x8E 0x8F )(list 0x200 0x204 0x208 0x20C 0x210 0x214 0x218 0x21C 0x220 0x224 0x228 0x22C 0x230 0x234 0x238 0x23C ) group.long ($2+0x1400)++0x3 line.long 0x0 "REGG5_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x90 0x91 0x92 0x93 0x94 0x95 0x96 0x97 0x98 0x99 0x9A 0x9B 0x9C 0x9D 0x9E 0x9F )(list 0x240 0x244 0x248 0x24C 0x250 0x254 0x258 0x25C 0x260 0x264 0x268 0x26C 0x270 0x274 0x278 0x27C ) group.long ($2+0x1400)++0x3 line.long 0x0 "REGG5_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xA0 0xA1 0xA2 0xA3 0xA4 0xA5 0xA6 0xA7 0xA8 0xA9 0xAA 0xAB 0xAC 0xAD 0xAE 0xAF )(list 0x280 0x284 0x288 0x28C 0x290 0x294 0x298 0x29C 0x2A0 0x2A4 0x2A8 0x2AC 0x2B0 0x2B4 0x2B8 0x2BC ) group.long ($2+0x1400)++0x3 line.long 0x0 "REGG5_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xB0 0xB1 0xB2 0xB3 0xB4 0xB5 0xB6 0xB7 0xB8 0xB9 0xBA 0xBB 0xBC 0xBD 0xBE 0xBF )(list 0x2C0 0x2C4 0x2C8 0x2CC 0x2D0 0x2D4 0x2D8 0x2DC 0x2E0 0x2E4 0x2E8 0x2EC 0x2F0 0x2F4 0x2F8 0x2FC ) group.long ($2+0x1400)++0x3 line.long 0x0 "REGG5_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xC0 0xC1 0xC2 0xC3 0xC4 0xC5 0xC6 0xC7 0xC8 0xC9 0xCA 0xCB 0xCC 0xCD 0xCE 0xCF )(list 0x300 0x304 0x308 0x30C 0x310 0x314 0x318 0x31C 0x320 0x324 0x328 0x32C 0x330 0x334 0x338 0x33C ) group.long ($2+0x1400)++0x3 line.long 0x0 "REGG5_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xD0 0xD1 0xD2 0xD3 0xD4 0xD5 0xD6 0xD7 0xD8 0xD9 0xDA 0xDB 0xDC 0xDD 0xDE 0xDF )(list 0x340 0x344 0x348 0x34C 0x350 0x354 0x358 0x35C 0x360 0x364 0x368 0x36C 0x370 0x374 0x378 0x37C ) group.long ($2+0x1400)++0x3 line.long 0x0 "REGG5_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xE0 0xE1 0xE2 0xE3 0xE4 0xE5 0xE6 0xE7 0xE8 0xE9 0xEA 0xEB 0xEC 0xED 0xEE 0xEF )(list 0x380 0x384 0x388 0x38C 0x390 0x394 0x398 0x39C 0x3A0 0x3A4 0x3A8 0x3AC 0x3B0 0x3B4 0x3B8 0x3BC ) group.long ($2+0x1400)++0x3 line.long 0x0 "REGG5_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xF0 0xF1 0xF2 0xF3 0xF4 0xF5 0xF6 0xF7 0xF8 0xF9 0xFA 0xFB 0xFC 0xFD 0xFE 0xFF )(list 0x3C0 0x3C4 0x3C8 0x3CC 0x3D0 0x3D4 0x3D8 0x3DC 0x3E0 0x3E4 0x3E8 0x3EC 0x3F0 0x3F4 0x3F8 0x3FC ) group.long ($2+0x1400)++0x3 line.long 0x0 "REGG5_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x4 0x8 0xC 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C ) group.long ($2+0x1800)++0x3 line.long 0x0 "REGG6_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1A 0x1B 0x1C 0x1D 0x1E 0x1F )(list 0x40 0x44 0x48 0x4C 0x50 0x54 0x58 0x5C 0x60 0x64 0x68 0x6C 0x70 0x74 0x78 0x7C ) group.long ($2+0x1800)++0x3 line.long 0x0 "REGG6_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x20 0x21 0x22 0x23 0x24 0x25 0x26 0x27 0x28 0x29 0x2A 0x2B 0x2C 0x2D 0x2E 0x2F )(list 0x80 0x84 0x88 0x8C 0x90 0x94 0x98 0x9C 0xA0 0xA4 0xA8 0xAC 0xB0 0xB4 0xB8 0xBC ) group.long ($2+0x1800)++0x3 line.long 0x0 "REGG6_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x30 0x31 0x32 0x33 0x34 0x35 0x36 0x37 0x38 0x39 0x3A 0x3B 0x3C 0x3D 0x3E 0x3F )(list 0xC0 0xC4 0xC8 0xCC 0xD0 0xD4 0xD8 0xDC 0xE0 0xE4 0xE8 0xEC 0xF0 0xF4 0xF8 0xFC ) group.long ($2+0x1800)++0x3 line.long 0x0 "REGG6_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x40 0x41 0x42 0x43 0x44 0x45 0x46 0x47 0x48 0x49 0x4A 0x4B 0x4C 0x4D 0x4E 0x4F )(list 0x100 0x104 0x108 0x10C 0x110 0x114 0x118 0x11C 0x120 0x124 0x128 0x12C 0x130 0x134 0x138 0x13C ) group.long ($2+0x1800)++0x3 line.long 0x0 "REGG6_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x50 0x51 0x52 0x53 0x54 0x55 0x56 0x57 0x58 0x59 0x5A 0x5B 0x5C 0x5D 0x5E 0x5F )(list 0x140 0x144 0x148 0x14C 0x150 0x154 0x158 0x15C 0x160 0x164 0x168 0x16C 0x170 0x174 0x178 0x17C ) group.long ($2+0x1800)++0x3 line.long 0x0 "REGG6_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x60 0x61 0x62 0x63 0x64 0x65 0x66 0x67 0x68 0x69 0x6A 0x6B 0x6C 0x6D 0x6E 0x6F )(list 0x180 0x184 0x188 0x18C 0x190 0x194 0x198 0x19C 0x1A0 0x1A4 0x1A8 0x1AC 0x1B0 0x1B4 0x1B8 0x1BC ) group.long ($2+0x1800)++0x3 line.long 0x0 "REGG6_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x70 0x71 0x72 0x73 0x74 0x75 0x76 0x77 0x78 0x79 0x7A 0x7B 0x7C 0x7D 0x7E 0x7F )(list 0x1C0 0x1C4 0x1C8 0x1CC 0x1D0 0x1D4 0x1D8 0x1DC 0x1E0 0x1E4 0x1E8 0x1EC 0x1F0 0x1F4 0x1F8 0x1FC ) group.long ($2+0x1800)++0x3 line.long 0x0 "REGG6_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x80 0x81 0x82 0x83 0x84 0x85 0x86 0x87 0x88 0x89 0x8A 0x8B 0x8C 0x8D 0x8E 0x8F )(list 0x200 0x204 0x208 0x20C 0x210 0x214 0x218 0x21C 0x220 0x224 0x228 0x22C 0x230 0x234 0x238 0x23C ) group.long ($2+0x1800)++0x3 line.long 0x0 "REGG6_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x90 0x91 0x92 0x93 0x94 0x95 0x96 0x97 0x98 0x99 0x9A 0x9B 0x9C 0x9D 0x9E 0x9F )(list 0x240 0x244 0x248 0x24C 0x250 0x254 0x258 0x25C 0x260 0x264 0x268 0x26C 0x270 0x274 0x278 0x27C ) group.long ($2+0x1800)++0x3 line.long 0x0 "REGG6_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xA0 0xA1 0xA2 0xA3 0xA4 0xA5 0xA6 0xA7 0xA8 0xA9 0xAA 0xAB 0xAC 0xAD 0xAE 0xAF )(list 0x280 0x284 0x288 0x28C 0x290 0x294 0x298 0x29C 0x2A0 0x2A4 0x2A8 0x2AC 0x2B0 0x2B4 0x2B8 0x2BC ) group.long ($2+0x1800)++0x3 line.long 0x0 "REGG6_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xB0 0xB1 0xB2 0xB3 0xB4 0xB5 0xB6 0xB7 0xB8 0xB9 0xBA 0xBB 0xBC 0xBD 0xBE 0xBF )(list 0x2C0 0x2C4 0x2C8 0x2CC 0x2D0 0x2D4 0x2D8 0x2DC 0x2E0 0x2E4 0x2E8 0x2EC 0x2F0 0x2F4 0x2F8 0x2FC ) group.long ($2+0x1800)++0x3 line.long 0x0 "REGG6_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xC0 0xC1 0xC2 0xC3 0xC4 0xC5 0xC6 0xC7 0xC8 0xC9 0xCA 0xCB 0xCC 0xCD 0xCE 0xCF )(list 0x300 0x304 0x308 0x30C 0x310 0x314 0x318 0x31C 0x320 0x324 0x328 0x32C 0x330 0x334 0x338 0x33C ) group.long ($2+0x1800)++0x3 line.long 0x0 "REGG6_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xD0 0xD1 0xD2 0xD3 0xD4 0xD5 0xD6 0xD7 0xD8 0xD9 0xDA 0xDB 0xDC 0xDD 0xDE 0xDF )(list 0x340 0x344 0x348 0x34C 0x350 0x354 0x358 0x35C 0x360 0x364 0x368 0x36C 0x370 0x374 0x378 0x37C ) group.long ($2+0x1800)++0x3 line.long 0x0 "REGG6_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xE0 0xE1 0xE2 0xE3 0xE4 0xE5 0xE6 0xE7 0xE8 0xE9 0xEA 0xEB 0xEC 0xED 0xEE 0xEF )(list 0x380 0x384 0x388 0x38C 0x390 0x394 0x398 0x39C 0x3A0 0x3A4 0x3A8 0x3AC 0x3B0 0x3B4 0x3B8 0x3BC ) group.long ($2+0x1800)++0x3 line.long 0x0 "REGG6_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xF0 0xF1 0xF2 0xF3 0xF4 0xF5 0xF6 0xF7 0xF8 0xF9 0xFA 0xFB 0xFC 0xFD 0xFE 0xFF )(list 0x3C0 0x3C4 0x3C8 0x3CC 0x3D0 0x3D4 0x3D8 0x3DC 0x3E0 0x3E4 0x3E8 0x3EC 0x3F0 0x3F4 0x3F8 0x3FC ) group.long ($2+0x1800)++0x3 line.long 0x0 "REGG6_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x4 0x8 0xC 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C ) group.long ($2+0x1C00)++0x3 line.long 0x0 "REGG7_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1A 0x1B 0x1C 0x1D 0x1E 0x1F )(list 0x40 0x44 0x48 0x4C 0x50 0x54 0x58 0x5C 0x60 0x64 0x68 0x6C 0x70 0x74 0x78 0x7C ) group.long ($2+0x1C00)++0x3 line.long 0x0 "REGG7_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x20 0x21 0x22 0x23 0x24 0x25 0x26 0x27 0x28 0x29 0x2A 0x2B 0x2C 0x2D 0x2E 0x2F )(list 0x80 0x84 0x88 0x8C 0x90 0x94 0x98 0x9C 0xA0 0xA4 0xA8 0xAC 0xB0 0xB4 0xB8 0xBC ) group.long ($2+0x1C00)++0x3 line.long 0x0 "REGG7_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x30 0x31 0x32 0x33 0x34 0x35 0x36 0x37 0x38 0x39 0x3A 0x3B 0x3C 0x3D 0x3E 0x3F )(list 0xC0 0xC4 0xC8 0xCC 0xD0 0xD4 0xD8 0xDC 0xE0 0xE4 0xE8 0xEC 0xF0 0xF4 0xF8 0xFC ) group.long ($2+0x1C00)++0x3 line.long 0x0 "REGG7_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x40 0x41 0x42 0x43 0x44 0x45 0x46 0x47 0x48 0x49 0x4A 0x4B 0x4C 0x4D 0x4E 0x4F )(list 0x100 0x104 0x108 0x10C 0x110 0x114 0x118 0x11C 0x120 0x124 0x128 0x12C 0x130 0x134 0x138 0x13C ) group.long ($2+0x1C00)++0x3 line.long 0x0 "REGG7_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x50 0x51 0x52 0x53 0x54 0x55 0x56 0x57 0x58 0x59 0x5A 0x5B 0x5C 0x5D 0x5E 0x5F )(list 0x140 0x144 0x148 0x14C 0x150 0x154 0x158 0x15C 0x160 0x164 0x168 0x16C 0x170 0x174 0x178 0x17C ) group.long ($2+0x1C00)++0x3 line.long 0x0 "REGG7_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x60 0x61 0x62 0x63 0x64 0x65 0x66 0x67 0x68 0x69 0x6A 0x6B 0x6C 0x6D 0x6E 0x6F )(list 0x180 0x184 0x188 0x18C 0x190 0x194 0x198 0x19C 0x1A0 0x1A4 0x1A8 0x1AC 0x1B0 0x1B4 0x1B8 0x1BC ) group.long ($2+0x1C00)++0x3 line.long 0x0 "REGG7_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x70 0x71 0x72 0x73 0x74 0x75 0x76 0x77 0x78 0x79 0x7A 0x7B 0x7C 0x7D 0x7E 0x7F )(list 0x1C0 0x1C4 0x1C8 0x1CC 0x1D0 0x1D4 0x1D8 0x1DC 0x1E0 0x1E4 0x1E8 0x1EC 0x1F0 0x1F4 0x1F8 0x1FC ) group.long ($2+0x1C00)++0x3 line.long 0x0 "REGG7_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x80 0x81 0x82 0x83 0x84 0x85 0x86 0x87 0x88 0x89 0x8A 0x8B 0x8C 0x8D 0x8E 0x8F )(list 0x200 0x204 0x208 0x20C 0x210 0x214 0x218 0x21C 0x220 0x224 0x228 0x22C 0x230 0x234 0x238 0x23C ) group.long ($2+0x1C00)++0x3 line.long 0x0 "REGG7_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x90 0x91 0x92 0x93 0x94 0x95 0x96 0x97 0x98 0x99 0x9A 0x9B 0x9C 0x9D 0x9E 0x9F )(list 0x240 0x244 0x248 0x24C 0x250 0x254 0x258 0x25C 0x260 0x264 0x268 0x26C 0x270 0x274 0x278 0x27C ) group.long ($2+0x1C00)++0x3 line.long 0x0 "REGG7_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xA0 0xA1 0xA2 0xA3 0xA4 0xA5 0xA6 0xA7 0xA8 0xA9 0xAA 0xAB 0xAC 0xAD 0xAE 0xAF )(list 0x280 0x284 0x288 0x28C 0x290 0x294 0x298 0x29C 0x2A0 0x2A4 0x2A8 0x2AC 0x2B0 0x2B4 0x2B8 0x2BC ) group.long ($2+0x1C00)++0x3 line.long 0x0 "REGG7_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xB0 0xB1 0xB2 0xB3 0xB4 0xB5 0xB6 0xB7 0xB8 0xB9 0xBA 0xBB 0xBC 0xBD 0xBE 0xBF )(list 0x2C0 0x2C4 0x2C8 0x2CC 0x2D0 0x2D4 0x2D8 0x2DC 0x2E0 0x2E4 0x2E8 0x2EC 0x2F0 0x2F4 0x2F8 0x2FC ) group.long ($2+0x1C00)++0x3 line.long 0x0 "REGG7_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xC0 0xC1 0xC2 0xC3 0xC4 0xC5 0xC6 0xC7 0xC8 0xC9 0xCA 0xCB 0xCC 0xCD 0xCE 0xCF )(list 0x300 0x304 0x308 0x30C 0x310 0x314 0x318 0x31C 0x320 0x324 0x328 0x32C 0x330 0x334 0x338 0x33C ) group.long ($2+0x1C00)++0x3 line.long 0x0 "REGG7_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xD0 0xD1 0xD2 0xD3 0xD4 0xD5 0xD6 0xD7 0xD8 0xD9 0xDA 0xDB 0xDC 0xDD 0xDE 0xDF )(list 0x340 0x344 0x348 0x34C 0x350 0x354 0x358 0x35C 0x360 0x364 0x368 0x36C 0x370 0x374 0x378 0x37C ) group.long ($2+0x1C00)++0x3 line.long 0x0 "REGG7_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xE0 0xE1 0xE2 0xE3 0xE4 0xE5 0xE6 0xE7 0xE8 0xE9 0xEA 0xEB 0xEC 0xED 0xEE 0xEF )(list 0x380 0x384 0x388 0x38C 0x390 0x394 0x398 0x39C 0x3A0 0x3A4 0x3A8 0x3AC 0x3B0 0x3B4 0x3B8 0x3BC ) group.long ($2+0x1C00)++0x3 line.long 0x0 "REGG7_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xF0 0xF1 0xF2 0xF3 0xF4 0xF5 0xF6 0xF7 0xF8 0xF9 0xFA 0xFB 0xFC 0xFD 0xFE 0xFF )(list 0x3C0 0x3C4 0x3C8 0x3CC 0x3D0 0x3D4 0x3D8 0x3DC 0x3E0 0x3E4 0x3E8 0x3EC 0x3F0 0x3F4 0x3F8 0x3FC ) group.long ($2+0x1C00)++0x3 line.long 0x0 "REGG7_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end group.long 0x2000++0x17 line.long 0x0 "GLB_CTL,This register provides global enable settings for permission control." bitfld.long 0x0 5. "DOM_CFG_LOCK,Lock write for DOM_CFG_MODE bit." "0,1" bitfld.long 0x0 4. "DOM_CFG_MODE,When enabled all the source setting can be configured by master from domain 0 if it is not locked. When disabled only resource manager can configure the permission of the resource." "0,1" bitfld.long 0x0 3. "PERCK_DIS_LOCK,Lock write for PERCK_DIS" "0,1" bitfld.long 0x0 2. "PERCK_DIS,All the permission check disable." "0,1" newline bitfld.long 0x0 1. "DOM_PRO_LOCK,Lock write for DOM_PRO_EN bit." "0,1" bitfld.long 0x0 0. "DOM_PRO_EN,When disabled no domain access permission check" "0,1" line.long 0x4 "RES_MGR,Resource manager register. This regster is used to assign resource manager for global resource access control" bitfld.long 0x4 17. "MID_LOCK,Lock write for MID_EN and MID_LOW and MID_HIG registers." "0,1" bitfld.long 0x4 16. "MID_EN,Master ID check enable" "0,1" bitfld.long 0x4 15. "PRI_PER_LOCK,Lock write for PRI_PER and PRI_PER_EN" "0,1" bitfld.long 0x4 13.--14. "PRI_PER,Resource manager privileged access permission. bit0 for privileged access bit1 for user access" "0,1,2,3" newline bitfld.long 0x4 12. "PRI_PER_EN,Resource manager privileged access permission enable." "0,1" bitfld.long 0x4 11. "SEC_PER_LOCK,Lock for SEC_PER and SEC_PER_LOCK" "0,1" bitfld.long 0x4 9.--10. "SEC_PER,Resource manager secure access permission. bit 0 for secure access bit 1 for non-secure access" "0,1,2,3" bitfld.long 0x4 8. "SEC_PER_EN,Resource manager secure permission enable" "0,1" bitfld.long 0x4 7. "DID_LOCK,Lock write for DID_EN and DID" "0,1" newline hexmask.long.byte 0x4 3.--6. 1. "DID,Resource manager domain ID" bitfld.long 0x4 2. "DID_EN,Resource manager Domain ID enable" "0,1" bitfld.long 0x4 1. "RES_MGR_EN_LOCK,Lock for RES_MGR_EN" "0,1" bitfld.long 0x4 0. "RES_MGR_EN,Resource manager enable. When the bit is disable there is no resource manager." "0,1" line.long 0x8 "RES_MGR_MA0,This register is used to assign master 0~31 as resource manager." hexmask.long 0x8 0.--31. 1. "MID,Assign master 0~31 for resource manager" line.long 0xC "RES_MGR_MA1,This register is used to assign master 32~63 as resource manager." hexmask.long 0xC 0.--31. 1. "MID,Indicate if master 32~63 is resource manager." line.long 0x10 "RES_MGR_MA2,This register is used to assign master 64~95 as resource manager." hexmask.long 0x10 0.--31. 1. "MID,Indicate if master 64~95 is resource manager." line.long 0x14 "RES_MGR_MA3,This register is used to assign master 96~127 as resource manager." hexmask.long 0x14 0.--31. 1. "MID,Indicate if master 96~127 is resource manager." repeat 8. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 )(list 0x0 0x14 0x28 0x3C 0x50 0x64 0x78 0x8C ) group.long ($2+0x2100)++0x3 line.long 0x0 "GRP_MGR_$1,Group Manager Register. This register is used to assign group manager for each domain" bitfld.long 0x0 17. "MID_LOCK,Lock write for MID_EN and MID_LOW and MID_HIG registers." "0,1" bitfld.long 0x0 16. "MID_EN,Master ID check enable" "0,1" bitfld.long 0x0 15. "PRI_PER_LOCK,Lock write for PRI_PER and PRI_PER_EN" "0,1" bitfld.long 0x0 13.--14. "PRI_PER,Group manager privileged access permission. bit0 for privileged access bit1 for user access" "0,1,2,3" newline bitfld.long 0x0 12. "PRI_PER_EN,Group manager privileged access permission enable." "0,1" bitfld.long 0x0 11. "SEC_PER_LOCK,Lock for SEC_PER and SEC_PER_LOCK" "0,1" bitfld.long 0x0 9.--10. "SEC_PER,Group manager secure access permission. bit 0 for secure access bit 1 for non-secure access" "0,1,2,3" bitfld.long 0x0 8. "SEC_PER_EN,Group manager secure permission enable" "0,1" bitfld.long 0x0 7. "DID_LOCK,Lock write for DID_EN and DID" "0,1" newline hexmask.long.byte 0x0 3.--6. 1. "DID,Group manager domain ID" bitfld.long 0x0 2. "DID_EN,Group manager Domain ID enable" "0,1" bitfld.long 0x0 1. "GRP_MGR_EN_LOCK,Lock write for GPR_MGR_EN" "0,1" bitfld.long 0x0 0. "GRP_MGR_EN,Group manager enable. When the bit is disable there is no resource manager." "0,1" repeat.end repeat 8. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 )(list 0x0 0x14 0x28 0x3C 0x50 0x64 0x78 0x8C ) group.long ($2+0x2104)++0x3 line.long 0x0 "GRP_MGR_MA0_$1,Assign master 0~31 for group manager 0" hexmask.long 0x0 0.--31. 1. "MID,Assign master 0~31 for resource manager" repeat.end repeat 8. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 )(list 0x0 0x14 0x28 0x3C 0x50 0x64 0x78 0x8C ) group.long ($2+0x2108)++0x3 line.long 0x0 "GRP_MGR_MA1_$1,Assign master 32~63 for group manager 0" hexmask.long 0x0 0.--31. 1. "MID,Indicate if master 32~63 is resource manager." repeat.end repeat 8. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 )(list 0x0 0x14 0x28 0x3C 0x50 0x64 0x78 0x8C ) group.long ($2+0x210C)++0x3 line.long 0x0 "GRP_MGR_MA2_$1,Assign master 64~95 for group manager 0" hexmask.long 0x0 0.--31. 1. "MID,Indicate if master 64~95 is resource manager." repeat.end repeat 8. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 )(list 0x0 0x14 0x28 0x3C 0x50 0x64 0x78 0x8C ) group.long ($2+0x2110)++0x3 line.long 0x0 "GRP_MGR_MA3_$1,Assign master 96~127 for group manager 0" hexmask.long 0x0 0.--31. 1. "MID,Indicate if master 96~127 is resource manager." repeat.end group.long 0x2200++0x3 line.long 0x0 "DOM_GID_0,Indicate which group domain 0 belong to" bitfld.long 0x0 3. "LOCK,Lock write for GID" "0,1" bitfld.long 0x0 0.--2. "GID,Group ID" "0,1,2,3,4,5,6,7" repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x18 0x30 0x48 0x60 0x78 0x90 0xA8 0xC0 0xD8 0xF0 0x108 0x120 0x138 0x150 0x168 ) group.long ($2+0x2204)++0x3 line.long 0x0 "DOM_OWN_$1,Assign owner for function domain 0." bitfld.long 0x0 17. "MID_LOCK,Lock write for MID_EN and MID_LOW and MID_HIG registers." "0,1" bitfld.long 0x0 16. "MID_EN,Master ID check enable" "0,1" bitfld.long 0x0 15. "PRI_PER_LOCK,Lock write for PRI_PER and PRI_PER_EN" "0,1" bitfld.long 0x0 13.--14. "PRI_PER,Group manager privileged access permission. bit0 for privileged access bit1 for user access" "0,1,2,3" newline bitfld.long 0x0 12. "PRI_PER_EN,Group manager privileged access permission enable." "0,1" bitfld.long 0x0 11. "SEC_PER_LOCK,Lock for SEC_PER and SEC_PER_LOCK" "0,1" bitfld.long 0x0 9.--10. "SEC_PER,Domain owner secure access permission. bit 0 for secure access bit 1 for non-secure access" "0,1,2,3" bitfld.long 0x0 8. "SEC_PER_EN,Domain owner secure permission enable" "0,1" newline bitfld.long 0x0 1. "DOM_OWN_EN_LOCK,Lock for DOM_OWN_EN" "0,1" bitfld.long 0x0 0. "DOM_OWN_EN,Domain owner enable. When the bit is disable there is no domain owner." "0,1" repeat.end repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x18 0x30 0x48 0x60 0x78 0x90 0xA8 0xC0 0xD8 0xF0 0x108 0x120 0x138 0x150 0x168 ) group.long ($2+0x2208)++0x3 line.long 0x0 "DOM_OWN_MA0_$1,Assign master 0~31 for domain owner 0" hexmask.long 0x0 0.--31. 1. "MID,Assign master 0~31 for resource manager" repeat.end repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x18 0x30 0x48 0x60 0x78 0x90 0xA8 0xC0 0xD8 0xF0 0x108 0x120 0x138 0x150 0x168 ) group.long ($2+0x220C)++0x3 line.long 0x0 "DOM_OWN_MA1_$1,Assign master 32~63 for domain owner 0" hexmask.long 0x0 0.--31. 1. "MID,Indicate if master 32~63 is resource manager." repeat.end repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x18 0x30 0x48 0x60 0x78 0x90 0xA8 0xC0 0xD8 0xF0 0x108 0x120 0x138 0x150 0x168 ) group.long ($2+0x2210)++0x3 line.long 0x0 "DOM_OWN_MA2_$1,Assign master 64~95 for domain owner 0" hexmask.long 0x0 0.--31. 1. "MID,Indicate if master 64~95 is resource manager." repeat.end repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x18 0x30 0x48 0x60 0x78 0x90 0xA8 0xC0 0xD8 0xF0 0x108 0x120 0x138 0x150 0x168 ) group.long ($2+0x2214)++0x3 line.long 0x0 "DOM_OWN_MA3_$1,Assign master 96~127 for domain owner 0" hexmask.long 0x0 0.--31. 1. "MID,Indicate if master 96~127 is resource manager." repeat.end group.long 0x2218++0x3 line.long 0x0 "DOM_GID_1,Indicate which group domain 1 belong to" bitfld.long 0x0 3. "LOCK,Lock write for GID" "0,1" bitfld.long 0x0 0.--2. "GID,Group ID" "0,1,2,3,4,5,6,7" group.long 0x2230++0x3 line.long 0x0 "DOM_GID_2,Indicate which group domain 2 belong to" bitfld.long 0x0 3. "LOCK,Lock write for GID" "0,1" bitfld.long 0x0 0.--2. "GID,Group ID" "0,1,2,3,4,5,6,7" group.long 0x2248++0x3 line.long 0x0 "DOM_GID_3,Indicate which group domain 3 belong to" bitfld.long 0x0 3. "LOCK,Lock write for GID" "0,1" bitfld.long 0x0 0.--2. "GID,Group ID" "0,1,2,3,4,5,6,7" group.long 0x2260++0x3 line.long 0x0 "DOM_GID_4,Indicate which group domain 4 belong to" bitfld.long 0x0 3. "LOCK,Lock write for GID" "0,1" bitfld.long 0x0 0.--2. "GID,Group ID" "0,1,2,3,4,5,6,7" group.long 0x2278++0x3 line.long 0x0 "DOM_GID_5,Indicate which group domain 5 belong to" bitfld.long 0x0 3. "LOCK,Lock write for GID" "0,1" bitfld.long 0x0 0.--2. "GID,Group ID" "0,1,2,3,4,5,6,7" group.long 0x2290++0x3 line.long 0x0 "DOM_GID_6,Indicate which group domain 6 belong to" bitfld.long 0x0 3. "LOCK,Lock write for GID" "0,1" bitfld.long 0x0 0.--2. "GID,Group ID" "0,1,2,3,4,5,6,7" group.long 0x22A8++0x3 line.long 0x0 "DOM_GID_7,Indicate which group domain 7 belong to" bitfld.long 0x0 3. "LOCK,Lock write for GID" "0,1" bitfld.long 0x0 0.--2. "GID,Group ID" "0,1,2,3,4,5,6,7" group.long 0x22C0++0x3 line.long 0x0 "DOM_GID_8,Indicate which group domain 8 belong to" bitfld.long 0x0 3. "LOCK,Lock write for GID" "0,1" bitfld.long 0x0 0.--2. "GID,Group ID" "0,1,2,3,4,5,6,7" group.long 0x22D8++0x3 line.long 0x0 "DOM_GID_9,Indicate which group domain 9 belong to" bitfld.long 0x0 3. "LOCK,Lock write for GID" "0,1" bitfld.long 0x0 0.--2. "GID,Group ID" "0,1,2,3,4,5,6,7" group.long 0x22F0++0x3 line.long 0x0 "DOM_GID_10,Indicate which group domain 10 belong to" bitfld.long 0x0 3. "LOCK,Lock write for GID" "0,1" bitfld.long 0x0 0.--2. "GID,Group ID" "0,1,2,3,4,5,6,7" group.long 0x2308++0x3 line.long 0x0 "DOM_GID_11,Indicate which group domain 11 belong to" bitfld.long 0x0 3. "LOCK,Lock write for GID" "0,1" bitfld.long 0x0 0.--2. "GID,Group ID" "0,1,2,3,4,5,6,7" group.long 0x2320++0x3 line.long 0x0 "DOM_GID_12,Indicate which group domain 12 belong to" bitfld.long 0x0 3. "LOCK,Lock write for GID" "0,1" bitfld.long 0x0 0.--2. "GID,Group ID" "0,1,2,3,4,5,6,7" group.long 0x2338++0x3 line.long 0x0 "DOM_GID_13,Indicate which group domain 13 belong to" bitfld.long 0x0 3. "LOCK,Lock write for GID" "0,1" bitfld.long 0x0 0.--2. "GID,Group ID" "0,1,2,3,4,5,6,7" group.long 0x2350++0x3 line.long 0x0 "DOM_GID_14,Indicate which group domain 14 belong to" bitfld.long 0x0 3. "LOCK,Lock write for GID" "0,1" bitfld.long 0x0 0.--2. "GID,Group ID" "0,1,2,3,4,5,6,7" group.long 0x2368++0x3 line.long 0x0 "DOM_GID_15,Indicate which group domain 15 belong to" bitfld.long 0x0 3. "LOCK,Lock write for GID" "0,1" bitfld.long 0x0 0.--2. "GID,Group ID" "0,1,2,3,4,5,6,7" repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x34 0x68 0x9C 0xD0 0x104 0x138 0x16C 0x1A0 0x1D4 0x208 0x23C 0x270 0x2A4 0x2D8 0x30C ) group.long ($2+0x2400)++0x3 line.long 0x0 "DOM_PER0_$1,Domain Permission Control. It can be only configured by resource manager and domain owner." bitfld.long 0x0 31. "DOM7_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 29.--30. "DOM7_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 28. "DOM7_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 27. "DOM6_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 25.--26. "DOM6_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" newline bitfld.long 0x0 24. "DOM6_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 23. "DOM5_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 21.--22. "DOM5_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 20. "DOM5_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 19. "DOM4_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" newline bitfld.long 0x0 17.--18. "DOM4_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM4_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 15. "DOM3_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 13.--14. "DOM3_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 12. "DOM3_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" newline bitfld.long 0x0 11. "DOM2_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 9.--10. "DOM2_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM2_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 7. "DOM1_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 5.--6. "DOM1_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" newline bitfld.long 0x0 4. "DOM1_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 3. "DOM0_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 1.--2. "DOM0_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM0_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" repeat.end repeat 16. (list 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1A 0x1B 0x1C 0x1D 0x1E 0x1F )(list 0x340 0x374 0x3A8 0x3DC 0x410 0x444 0x478 0x4AC 0x4E0 0x514 0x548 0x57C 0x5B0 0x5E4 0x618 0x64C ) group.long ($2+0x2400)++0x3 line.long 0x0 "DOM_PER0_$1,Domain Permission Control. It can be only configured by resource manager and domain owner." bitfld.long 0x0 31. "DOM7_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 29.--30. "DOM7_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 28. "DOM7_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 27. "DOM6_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 25.--26. "DOM6_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" newline bitfld.long 0x0 24. "DOM6_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 23. "DOM5_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 21.--22. "DOM5_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 20. "DOM5_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 19. "DOM4_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" newline bitfld.long 0x0 17.--18. "DOM4_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM4_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 15. "DOM3_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 13.--14. "DOM3_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 12. "DOM3_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" newline bitfld.long 0x0 11. "DOM2_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 9.--10. "DOM2_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM2_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 7. "DOM1_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 5.--6. "DOM1_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" newline bitfld.long 0x0 4. "DOM1_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 3. "DOM0_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 1.--2. "DOM0_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM0_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" repeat.end repeat 16. (list 0x20 0x21 0x22 0x23 0x24 0x25 0x26 0x27 0x28 0x29 0x2A 0x2B 0x2C 0x2D 0x2E 0x2F )(list 0x680 0x6B4 0x6E8 0x71C 0x750 0x784 0x7B8 0x7EC 0x820 0x854 0x888 0x8BC 0x8F0 0x924 0x958 0x98C ) group.long ($2+0x2400)++0x3 line.long 0x0 "DOM_PER0_$1,Domain Permission Control. It can be only configured by resource manager and domain owner." bitfld.long 0x0 31. "DOM7_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 29.--30. "DOM7_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 28. "DOM7_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 27. "DOM6_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 25.--26. "DOM6_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" newline bitfld.long 0x0 24. "DOM6_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 23. "DOM5_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 21.--22. "DOM5_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 20. "DOM5_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 19. "DOM4_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" newline bitfld.long 0x0 17.--18. "DOM4_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM4_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 15. "DOM3_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 13.--14. "DOM3_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 12. "DOM3_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" newline bitfld.long 0x0 11. "DOM2_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 9.--10. "DOM2_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM2_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 7. "DOM1_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 5.--6. "DOM1_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" newline bitfld.long 0x0 4. "DOM1_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 3. "DOM0_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 1.--2. "DOM0_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM0_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" repeat.end repeat 16. (list 0x30 0x31 0x32 0x33 0x34 0x35 0x36 0x37 0x38 0x39 0x3A 0x3B 0x3C 0x3D 0x3E 0x3F )(list 0x9C0 0x9F4 0xA28 0xA5C 0xA90 0xAC4 0xAF8 0xB2C 0xB60 0xB94 0xBC8 0xBFC 0xC30 0xC64 0xC98 0xCCC ) group.long ($2+0x2400)++0x3 line.long 0x0 "DOM_PER0_$1,Domain Permission Control. It can be only configured by resource manager and domain owner." bitfld.long 0x0 31. "DOM7_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 29.--30. "DOM7_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 28. "DOM7_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 27. "DOM6_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 25.--26. "DOM6_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" newline bitfld.long 0x0 24. "DOM6_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 23. "DOM5_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 21.--22. "DOM5_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 20. "DOM5_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 19. "DOM4_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" newline bitfld.long 0x0 17.--18. "DOM4_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM4_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 15. "DOM3_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 13.--14. "DOM3_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 12. "DOM3_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" newline bitfld.long 0x0 11. "DOM2_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 9.--10. "DOM2_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM2_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 7. "DOM1_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 5.--6. "DOM1_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" newline bitfld.long 0x0 4. "DOM1_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 3. "DOM0_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 1.--2. "DOM0_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM0_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" repeat.end repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x34 0x68 0x9C 0xD0 0x104 0x138 0x16C 0x1A0 0x1D4 0x208 0x23C 0x270 0x2A4 0x2D8 0x30C ) group.long ($2+0x2404)++0x3 line.long 0x0 "DOM_PER1_$1,Domain Permission Control. It can be only configured by resource manager and domain owner." bitfld.long 0x0 31. "DOM15_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 29.--30. "DOM15_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 28. "DOM15_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 27. "DOM14_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 25.--26. "DOM14_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" newline bitfld.long 0x0 24. "DOM14_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 23. "DOM13_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 21.--22. "DOM13_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 20. "DOM13_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 19. "DOM12_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" newline bitfld.long 0x0 17.--18. "DOM12_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM12_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 15. "DOM11_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 13.--14. "DOM11_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 12. "DOM11_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" newline bitfld.long 0x0 11. "DOM10_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 9.--10. "DOM10_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM10_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 7. "DOM9_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 5.--6. "DOM9_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" newline bitfld.long 0x0 4. "DOM9_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 3. "DOM8_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 1.--2. "DOM8_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM8_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" repeat.end repeat 16. (list 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1A 0x1B 0x1C 0x1D 0x1E 0x1F )(list 0x340 0x374 0x3A8 0x3DC 0x410 0x444 0x478 0x4AC 0x4E0 0x514 0x548 0x57C 0x5B0 0x5E4 0x618 0x64C ) group.long ($2+0x2404)++0x3 line.long 0x0 "DOM_PER1_$1,Domain Permission Control. It can be only configured by resource manager and domain owner." bitfld.long 0x0 31. "DOM15_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 29.--30. "DOM15_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 28. "DOM15_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 27. "DOM14_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 25.--26. "DOM14_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" newline bitfld.long 0x0 24. "DOM14_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 23. "DOM13_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 21.--22. "DOM13_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 20. "DOM13_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 19. "DOM12_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" newline bitfld.long 0x0 17.--18. "DOM12_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM12_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 15. "DOM11_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 13.--14. "DOM11_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 12. "DOM11_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" newline bitfld.long 0x0 11. "DOM10_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 9.--10. "DOM10_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM10_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 7. "DOM9_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 5.--6. "DOM9_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" newline bitfld.long 0x0 4. "DOM9_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 3. "DOM8_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 1.--2. "DOM8_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM8_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" repeat.end repeat 16. (list 0x20 0x21 0x22 0x23 0x24 0x25 0x26 0x27 0x28 0x29 0x2A 0x2B 0x2C 0x2D 0x2E 0x2F )(list 0x680 0x6B4 0x6E8 0x71C 0x750 0x784 0x7B8 0x7EC 0x820 0x854 0x888 0x8BC 0x8F0 0x924 0x958 0x98C ) group.long ($2+0x2404)++0x3 line.long 0x0 "DOM_PER1_$1,Domain Permission Control. It can be only configured by resource manager and domain owner." bitfld.long 0x0 31. "DOM15_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 29.--30. "DOM15_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 28. "DOM15_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 27. "DOM14_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 25.--26. "DOM14_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" newline bitfld.long 0x0 24. "DOM14_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 23. "DOM13_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 21.--22. "DOM13_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 20. "DOM13_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 19. "DOM12_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" newline bitfld.long 0x0 17.--18. "DOM12_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM12_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 15. "DOM11_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 13.--14. "DOM11_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 12. "DOM11_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" newline bitfld.long 0x0 11. "DOM10_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 9.--10. "DOM10_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM10_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 7. "DOM9_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 5.--6. "DOM9_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" newline bitfld.long 0x0 4. "DOM9_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 3. "DOM8_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 1.--2. "DOM8_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM8_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" repeat.end repeat 16. (list 0x30 0x31 0x32 0x33 0x34 0x35 0x36 0x37 0x38 0x39 0x3A 0x3B 0x3C 0x3D 0x3E 0x3F )(list 0x9C0 0x9F4 0xA28 0xA5C 0xA90 0xAC4 0xAF8 0xB2C 0xB60 0xB94 0xBC8 0xBFC 0xC30 0xC64 0xC98 0xCCC ) group.long ($2+0x2404)++0x3 line.long 0x0 "DOM_PER1_$1,Domain Permission Control. It can be only configured by resource manager and domain owner." bitfld.long 0x0 31. "DOM15_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 29.--30. "DOM15_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 28. "DOM15_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 27. "DOM14_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 25.--26. "DOM14_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" newline bitfld.long 0x0 24. "DOM14_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 23. "DOM13_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 21.--22. "DOM13_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 20. "DOM13_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 19. "DOM12_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" newline bitfld.long 0x0 17.--18. "DOM12_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM12_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 15. "DOM11_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 13.--14. "DOM11_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 12. "DOM11_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" newline bitfld.long 0x0 11. "DOM10_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 9.--10. "DOM10_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM10_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 7. "DOM9_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 5.--6. "DOM9_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" newline bitfld.long 0x0 4. "DOM9_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 3. "DOM8_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 1.--2. "DOM8_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM8_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" repeat.end repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x34 0x68 0x9C 0xD0 0x104 0x138 0x16C 0x1A0 0x1D4 0x208 0x23C 0x270 0x2A4 0x2D8 0x30C ) group.long ($2+0x2408)++0x3 line.long 0x0 "SEC_PER0_$1,This register is only used for resource manager to control secure access permission." bitfld.long 0x0 31. "DOM3_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM3_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM3_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM3_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM2_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM2_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM2_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM2_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM1_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM1_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM1_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM1_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM0_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM0_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM0_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM0_SEC_EN,Domain secure permission control enable" "0,1" repeat.end repeat 16. (list 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1A 0x1B 0x1C 0x1D 0x1E 0x1F )(list 0x340 0x374 0x3A8 0x3DC 0x410 0x444 0x478 0x4AC 0x4E0 0x514 0x548 0x57C 0x5B0 0x5E4 0x618 0x64C ) group.long ($2+0x2408)++0x3 line.long 0x0 "SEC_PER0_$1,This register is only used for resource manager to control secure access permission." bitfld.long 0x0 31. "DOM3_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM3_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM3_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM3_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM2_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM2_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM2_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM2_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM1_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM1_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM1_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM1_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM0_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM0_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM0_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM0_SEC_EN,Domain secure permission control enable" "0,1" repeat.end repeat 16. (list 0x20 0x21 0x22 0x23 0x24 0x25 0x26 0x27 0x28 0x29 0x2A 0x2B 0x2C 0x2D 0x2E 0x2F )(list 0x680 0x6B4 0x6E8 0x71C 0x750 0x784 0x7B8 0x7EC 0x820 0x854 0x888 0x8BC 0x8F0 0x924 0x958 0x98C ) group.long ($2+0x2408)++0x3 line.long 0x0 "SEC_PER0_$1,This register is only used for resource manager to control secure access permission." bitfld.long 0x0 31. "DOM3_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM3_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM3_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM3_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM2_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM2_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM2_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM2_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM1_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM1_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM1_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM1_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM0_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM0_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM0_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM0_SEC_EN,Domain secure permission control enable" "0,1" repeat.end repeat 16. (list 0x30 0x31 0x32 0x33 0x34 0x35 0x36 0x37 0x38 0x39 0x3A 0x3B 0x3C 0x3D 0x3E 0x3F )(list 0x9C0 0x9F4 0xA28 0xA5C 0xA90 0xAC4 0xAF8 0xB2C 0xB60 0xB94 0xBC8 0xBFC 0xC30 0xC64 0xC98 0xCCC ) group.long ($2+0x2408)++0x3 line.long 0x0 "SEC_PER0_$1,This register is only used for resource manager to control secure access permission." bitfld.long 0x0 31. "DOM3_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM3_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM3_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM3_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM2_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM2_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM2_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM2_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM1_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM1_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM1_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM1_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM0_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM0_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM0_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM0_SEC_EN,Domain secure permission control enable" "0,1" repeat.end repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x34 0x68 0x9C 0xD0 0x104 0x138 0x16C 0x1A0 0x1D4 0x208 0x23C 0x270 0x2A4 0x2D8 0x30C ) group.long ($2+0x240C)++0x3 line.long 0x0 "SEC_PER1_$1,This register is only used for resource manager to control secure access permission." bitfld.long 0x0 31. "DOM7_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM7_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM7_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM7_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM6_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM6_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM6_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM6_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM5_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM5_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM5_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM5_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM4_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM4_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM4_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM4_SEC_EN,Domain secure permission control enable" "0,1" repeat.end repeat 16. (list 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1A 0x1B 0x1C 0x1D 0x1E 0x1F )(list 0x340 0x374 0x3A8 0x3DC 0x410 0x444 0x478 0x4AC 0x4E0 0x514 0x548 0x57C 0x5B0 0x5E4 0x618 0x64C ) group.long ($2+0x240C)++0x3 line.long 0x0 "SEC_PER1_$1,This register is only used for resource manager to control secure access permission." bitfld.long 0x0 31. "DOM7_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM7_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM7_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM7_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM6_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM6_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM6_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM6_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM5_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM5_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM5_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM5_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM4_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM4_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM4_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM4_SEC_EN,Domain secure permission control enable" "0,1" repeat.end repeat 16. (list 0x20 0x21 0x22 0x23 0x24 0x25 0x26 0x27 0x28 0x29 0x2A 0x2B 0x2C 0x2D 0x2E 0x2F )(list 0x680 0x6B4 0x6E8 0x71C 0x750 0x784 0x7B8 0x7EC 0x820 0x854 0x888 0x8BC 0x8F0 0x924 0x958 0x98C ) group.long ($2+0x240C)++0x3 line.long 0x0 "SEC_PER1_$1,This register is only used for resource manager to control secure access permission." bitfld.long 0x0 31. "DOM7_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM7_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM7_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM7_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM6_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM6_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM6_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM6_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM5_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM5_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM5_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM5_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM4_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM4_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM4_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM4_SEC_EN,Domain secure permission control enable" "0,1" repeat.end repeat 16. (list 0x30 0x31 0x32 0x33 0x34 0x35 0x36 0x37 0x38 0x39 0x3A 0x3B 0x3C 0x3D 0x3E 0x3F )(list 0x9C0 0x9F4 0xA28 0xA5C 0xA90 0xAC4 0xAF8 0xB2C 0xB60 0xB94 0xBC8 0xBFC 0xC30 0xC64 0xC98 0xCCC ) group.long ($2+0x240C)++0x3 line.long 0x0 "SEC_PER1_$1,This register is only used for resource manager to control secure access permission." bitfld.long 0x0 31. "DOM7_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM7_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM7_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM7_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM6_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM6_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM6_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM6_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM5_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM5_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM5_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM5_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM4_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM4_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM4_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM4_SEC_EN,Domain secure permission control enable" "0,1" repeat.end repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x34 0x68 0x9C 0xD0 0x104 0x138 0x16C 0x1A0 0x1D4 0x208 0x23C 0x270 0x2A4 0x2D8 0x30C ) group.long ($2+0x2410)++0x3 line.long 0x0 "SEC_PER2_$1,This register is only used for resource manager to control secure access permission." bitfld.long 0x0 31. "DOM11_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM11_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM11_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM11_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM10_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM10_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM10_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM10_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM9_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM9_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM9_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM9_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM8_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM8_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM8_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM8_SEC_EN,Domain secure permission control enable" "0,1" repeat.end repeat 16. (list 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1A 0x1B 0x1C 0x1D 0x1E 0x1F )(list 0x340 0x374 0x3A8 0x3DC 0x410 0x444 0x478 0x4AC 0x4E0 0x514 0x548 0x57C 0x5B0 0x5E4 0x618 0x64C ) group.long ($2+0x2410)++0x3 line.long 0x0 "SEC_PER2_$1,This register is only used for resource manager to control secure access permission." bitfld.long 0x0 31. "DOM11_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM11_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM11_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM11_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM10_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM10_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM10_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM10_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM9_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM9_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM9_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM9_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM8_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM8_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM8_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM8_SEC_EN,Domain secure permission control enable" "0,1" repeat.end repeat 16. (list 0x20 0x21 0x22 0x23 0x24 0x25 0x26 0x27 0x28 0x29 0x2A 0x2B 0x2C 0x2D 0x2E 0x2F )(list 0x680 0x6B4 0x6E8 0x71C 0x750 0x784 0x7B8 0x7EC 0x820 0x854 0x888 0x8BC 0x8F0 0x924 0x958 0x98C ) group.long ($2+0x2410)++0x3 line.long 0x0 "SEC_PER2_$1,This register is only used for resource manager to control secure access permission." bitfld.long 0x0 31. "DOM11_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM11_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM11_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM11_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM10_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM10_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM10_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM10_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM9_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM9_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM9_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM9_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM8_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM8_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM8_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM8_SEC_EN,Domain secure permission control enable" "0,1" repeat.end repeat 16. (list 0x30 0x31 0x32 0x33 0x34 0x35 0x36 0x37 0x38 0x39 0x3A 0x3B 0x3C 0x3D 0x3E 0x3F )(list 0x9C0 0x9F4 0xA28 0xA5C 0xA90 0xAC4 0xAF8 0xB2C 0xB60 0xB94 0xBC8 0xBFC 0xC30 0xC64 0xC98 0xCCC ) group.long ($2+0x2410)++0x3 line.long 0x0 "SEC_PER2_$1,This register is only used for resource manager to control secure access permission." bitfld.long 0x0 31. "DOM11_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM11_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM11_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM11_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM10_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM10_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM10_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM10_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM9_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM9_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM9_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM9_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM8_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM8_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM8_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM8_SEC_EN,Domain secure permission control enable" "0,1" repeat.end repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x34 0x68 0x9C 0xD0 0x104 0x138 0x16C 0x1A0 0x1D4 0x208 0x23C 0x270 0x2A4 0x2D8 0x30C ) group.long ($2+0x2414)++0x3 line.long 0x0 "SEC_PER3_$1,This register is only used for resource manager to control secure access permission." bitfld.long 0x0 31. "DOM15_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM15_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM15_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM15_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM14_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM14_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM14_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM14_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM13_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM13_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM13_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM13_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM12_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM12_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM12_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM12_SEC_EN,Domain secure permission control enable" "0,1" repeat.end repeat 16. (list 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1A 0x1B 0x1C 0x1D 0x1E 0x1F )(list 0x340 0x374 0x3A8 0x3DC 0x410 0x444 0x478 0x4AC 0x4E0 0x514 0x548 0x57C 0x5B0 0x5E4 0x618 0x64C ) group.long ($2+0x2414)++0x3 line.long 0x0 "SEC_PER3_$1,This register is only used for resource manager to control secure access permission." bitfld.long 0x0 31. "DOM15_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM15_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM15_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM15_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM14_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM14_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM14_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM14_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM13_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM13_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM13_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM13_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM12_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM12_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM12_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM12_SEC_EN,Domain secure permission control enable" "0,1" repeat.end repeat 16. (list 0x20 0x21 0x22 0x23 0x24 0x25 0x26 0x27 0x28 0x29 0x2A 0x2B 0x2C 0x2D 0x2E 0x2F )(list 0x680 0x6B4 0x6E8 0x71C 0x750 0x784 0x7B8 0x7EC 0x820 0x854 0x888 0x8BC 0x8F0 0x924 0x958 0x98C ) group.long ($2+0x2414)++0x3 line.long 0x0 "SEC_PER3_$1,This register is only used for resource manager to control secure access permission." bitfld.long 0x0 31. "DOM15_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM15_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM15_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM15_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM14_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM14_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM14_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM14_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM13_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM13_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM13_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM13_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM12_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM12_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM12_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM12_SEC_EN,Domain secure permission control enable" "0,1" repeat.end repeat 16. (list 0x30 0x31 0x32 0x33 0x34 0x35 0x36 0x37 0x38 0x39 0x3A 0x3B 0x3C 0x3D 0x3E 0x3F )(list 0x9C0 0x9F4 0xA28 0xA5C 0xA90 0xAC4 0xAF8 0xB2C 0xB60 0xB94 0xBC8 0xBFC 0xC30 0xC64 0xC98 0xCCC ) group.long ($2+0x2414)++0x3 line.long 0x0 "SEC_PER3_$1,This register is only used for resource manager to control secure access permission." bitfld.long 0x0 31. "DOM15_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM15_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM15_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM15_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM14_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM14_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM14_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM14_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM13_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM13_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM13_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM13_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM12_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM12_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM12_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM12_SEC_EN,Domain secure permission control enable" "0,1" repeat.end repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x34 0x68 0x9C 0xD0 0x104 0x138 0x16C 0x1A0 0x1D4 0x208 0x23C 0x270 0x2A4 0x2D8 0x30C ) group.long ($2+0x2418)++0x3 line.long 0x0 "PRI_PER0_$1,This register is only used for resource manager to control privileged access permission." bitfld.long 0x0 31. "DOM3_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM3_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM3_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM3_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM2_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM2_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM2_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM2_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM1_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM1_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM1_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM1_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM0_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM0_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM0_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM0_PRI_EN,Domain privileged permission control enable" "0,1" repeat.end repeat 16. (list 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1A 0x1B 0x1C 0x1D 0x1E 0x1F )(list 0x340 0x374 0x3A8 0x3DC 0x410 0x444 0x478 0x4AC 0x4E0 0x514 0x548 0x57C 0x5B0 0x5E4 0x618 0x64C ) group.long ($2+0x2418)++0x3 line.long 0x0 "PRI_PER0_$1,This register is only used for resource manager to control privileged access permission." bitfld.long 0x0 31. "DOM3_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM3_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM3_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM3_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM2_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM2_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM2_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM2_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM1_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM1_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM1_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM1_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM0_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM0_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM0_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM0_PRI_EN,Domain privileged permission control enable" "0,1" repeat.end repeat 16. (list 0x20 0x21 0x22 0x23 0x24 0x25 0x26 0x27 0x28 0x29 0x2A 0x2B 0x2C 0x2D 0x2E 0x2F )(list 0x680 0x6B4 0x6E8 0x71C 0x750 0x784 0x7B8 0x7EC 0x820 0x854 0x888 0x8BC 0x8F0 0x924 0x958 0x98C ) group.long ($2+0x2418)++0x3 line.long 0x0 "PRI_PER0_$1,This register is only used for resource manager to control privileged access permission." bitfld.long 0x0 31. "DOM3_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM3_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM3_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM3_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM2_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM2_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM2_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM2_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM1_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM1_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM1_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM1_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM0_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM0_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM0_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM0_PRI_EN,Domain privileged permission control enable" "0,1" repeat.end repeat 16. (list 0x30 0x31 0x32 0x33 0x34 0x35 0x36 0x37 0x38 0x39 0x3A 0x3B 0x3C 0x3D 0x3E 0x3F )(list 0x9C0 0x9F4 0xA28 0xA5C 0xA90 0xAC4 0xAF8 0xB2C 0xB60 0xB94 0xBC8 0xBFC 0xC30 0xC64 0xC98 0xCCC ) group.long ($2+0x2418)++0x3 line.long 0x0 "PRI_PER0_$1,This register is only used for resource manager to control privileged access permission." bitfld.long 0x0 31. "DOM3_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM3_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM3_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM3_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM2_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM2_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM2_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM2_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM1_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM1_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM1_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM1_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM0_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM0_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM0_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM0_PRI_EN,Domain privileged permission control enable" "0,1" repeat.end repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x34 0x68 0x9C 0xD0 0x104 0x138 0x16C 0x1A0 0x1D4 0x208 0x23C 0x270 0x2A4 0x2D8 0x30C ) group.long ($2+0x241C)++0x3 line.long 0x0 "PRI_PER1_$1,This register is only used for resource manager to control privileged access permission." bitfld.long 0x0 31. "DOM7_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM7_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM7_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM7_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM6_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM6_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM6_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM6_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM5_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM5_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM5_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM5_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM4_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM4_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM4_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM4_PRI_EN,Domain privileged permission control enable" "0,1" repeat.end repeat 16. (list 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1A 0x1B 0x1C 0x1D 0x1E 0x1F )(list 0x340 0x374 0x3A8 0x3DC 0x410 0x444 0x478 0x4AC 0x4E0 0x514 0x548 0x57C 0x5B0 0x5E4 0x618 0x64C ) group.long ($2+0x241C)++0x3 line.long 0x0 "PRI_PER1_$1,This register is only used for resource manager to control privileged access permission." bitfld.long 0x0 31. "DOM7_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM7_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM7_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM7_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM6_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM6_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM6_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM6_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM5_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM5_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM5_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM5_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM4_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM4_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM4_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM4_PRI_EN,Domain privileged permission control enable" "0,1" repeat.end repeat 16. (list 0x20 0x21 0x22 0x23 0x24 0x25 0x26 0x27 0x28 0x29 0x2A 0x2B 0x2C 0x2D 0x2E 0x2F )(list 0x680 0x6B4 0x6E8 0x71C 0x750 0x784 0x7B8 0x7EC 0x820 0x854 0x888 0x8BC 0x8F0 0x924 0x958 0x98C ) group.long ($2+0x241C)++0x3 line.long 0x0 "PRI_PER1_$1,This register is only used for resource manager to control privileged access permission." bitfld.long 0x0 31. "DOM7_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM7_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM7_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM7_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM6_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM6_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM6_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM6_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM5_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM5_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM5_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM5_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM4_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM4_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM4_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM4_PRI_EN,Domain privileged permission control enable" "0,1" repeat.end repeat 16. (list 0x30 0x31 0x32 0x33 0x34 0x35 0x36 0x37 0x38 0x39 0x3A 0x3B 0x3C 0x3D 0x3E 0x3F )(list 0x9C0 0x9F4 0xA28 0xA5C 0xA90 0xAC4 0xAF8 0xB2C 0xB60 0xB94 0xBC8 0xBFC 0xC30 0xC64 0xC98 0xCCC ) group.long ($2+0x241C)++0x3 line.long 0x0 "PRI_PER1_$1,This register is only used for resource manager to control privileged access permission." bitfld.long 0x0 31. "DOM7_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM7_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM7_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM7_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM6_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM6_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM6_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM6_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM5_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM5_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM5_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM5_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM4_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM4_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM4_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM4_PRI_EN,Domain privileged permission control enable" "0,1" repeat.end repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x34 0x68 0x9C 0xD0 0x104 0x138 0x16C 0x1A0 0x1D4 0x208 0x23C 0x270 0x2A4 0x2D8 0x30C ) group.long ($2+0x2420)++0x3 line.long 0x0 "PRI_PER2_$1,This register is only used for resource manager to control privileged access permission." bitfld.long 0x0 31. "DOM11_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM11_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM11_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM11_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM10_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM10_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM10_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM10_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM9_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM9_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM9_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM9_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM8_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM8_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM8_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM8_PRI_EN,Domain privileged permission control enable" "0,1" repeat.end repeat 16. (list 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1A 0x1B 0x1C 0x1D 0x1E 0x1F )(list 0x340 0x374 0x3A8 0x3DC 0x410 0x444 0x478 0x4AC 0x4E0 0x514 0x548 0x57C 0x5B0 0x5E4 0x618 0x64C ) group.long ($2+0x2420)++0x3 line.long 0x0 "PRI_PER2_$1,This register is only used for resource manager to control privileged access permission." bitfld.long 0x0 31. "DOM11_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM11_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM11_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM11_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM10_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM10_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM10_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM10_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM9_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM9_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM9_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM9_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM8_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM8_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM8_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM8_PRI_EN,Domain privileged permission control enable" "0,1" repeat.end repeat 16. (list 0x20 0x21 0x22 0x23 0x24 0x25 0x26 0x27 0x28 0x29 0x2A 0x2B 0x2C 0x2D 0x2E 0x2F )(list 0x680 0x6B4 0x6E8 0x71C 0x750 0x784 0x7B8 0x7EC 0x820 0x854 0x888 0x8BC 0x8F0 0x924 0x958 0x98C ) group.long ($2+0x2420)++0x3 line.long 0x0 "PRI_PER2_$1,This register is only used for resource manager to control privileged access permission." bitfld.long 0x0 31. "DOM11_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM11_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM11_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM11_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM10_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM10_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM10_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM10_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM9_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM9_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM9_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM9_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM8_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM8_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM8_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM8_PRI_EN,Domain privileged permission control enable" "0,1" repeat.end repeat 16. (list 0x30 0x31 0x32 0x33 0x34 0x35 0x36 0x37 0x38 0x39 0x3A 0x3B 0x3C 0x3D 0x3E 0x3F )(list 0x9C0 0x9F4 0xA28 0xA5C 0xA90 0xAC4 0xAF8 0xB2C 0xB60 0xB94 0xBC8 0xBFC 0xC30 0xC64 0xC98 0xCCC ) group.long ($2+0x2420)++0x3 line.long 0x0 "PRI_PER2_$1,This register is only used for resource manager to control privileged access permission." bitfld.long 0x0 31. "DOM11_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM11_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM11_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM11_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM10_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM10_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM10_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM10_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM9_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM9_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM9_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM9_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM8_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM8_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM8_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM8_PRI_EN,Domain privileged permission control enable" "0,1" repeat.end repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x34 0x68 0x9C 0xD0 0x104 0x138 0x16C 0x1A0 0x1D4 0x208 0x23C 0x270 0x2A4 0x2D8 0x30C ) group.long ($2+0x2424)++0x3 line.long 0x0 "PRI_PER3_$1,This register is only used for resource manager to control privileged access permission." bitfld.long 0x0 31. "DOM15_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM15_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM15_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM15_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM14_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM14_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM14_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM14_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM13_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM13_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM13_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM13_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM12_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM12_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM12_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM12_PRI_EN,Domain privileged permission control enable" "0,1" repeat.end repeat 16. (list 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1A 0x1B 0x1C 0x1D 0x1E 0x1F )(list 0x340 0x374 0x3A8 0x3DC 0x410 0x444 0x478 0x4AC 0x4E0 0x514 0x548 0x57C 0x5B0 0x5E4 0x618 0x64C ) group.long ($2+0x2424)++0x3 line.long 0x0 "PRI_PER3_$1,This register is only used for resource manager to control privileged access permission." bitfld.long 0x0 31. "DOM15_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM15_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM15_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM15_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM14_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM14_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM14_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM14_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM13_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM13_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM13_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM13_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM12_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM12_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM12_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM12_PRI_EN,Domain privileged permission control enable" "0,1" repeat.end repeat 16. (list 0x20 0x21 0x22 0x23 0x24 0x25 0x26 0x27 0x28 0x29 0x2A 0x2B 0x2C 0x2D 0x2E 0x2F )(list 0x680 0x6B4 0x6E8 0x71C 0x750 0x784 0x7B8 0x7EC 0x820 0x854 0x888 0x8BC 0x8F0 0x924 0x958 0x98C ) group.long ($2+0x2424)++0x3 line.long 0x0 "PRI_PER3_$1,This register is only used for resource manager to control privileged access permission." bitfld.long 0x0 31. "DOM15_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM15_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM15_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM15_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM14_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM14_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM14_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM14_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM13_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM13_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM13_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM13_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM12_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM12_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM12_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM12_PRI_EN,Domain privileged permission control enable" "0,1" repeat.end repeat 16. (list 0x30 0x31 0x32 0x33 0x34 0x35 0x36 0x37 0x38 0x39 0x3A 0x3B 0x3C 0x3D 0x3E 0x3F )(list 0x9C0 0x9F4 0xA28 0xA5C 0xA90 0xAC4 0xAF8 0xB2C 0xB60 0xB94 0xBC8 0xBFC 0xC30 0xC64 0xC98 0xCCC ) group.long ($2+0x2424)++0x3 line.long 0x0 "PRI_PER3_$1,This register is only used for resource manager to control privileged access permission." bitfld.long 0x0 31. "DOM15_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM15_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM15_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM15_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM14_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM14_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM14_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM14_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM13_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM13_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM13_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM13_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM12_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM12_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM12_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM12_PRI_EN,Domain privileged permission control enable" "0,1" repeat.end repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x34 0x68 0x9C 0xD0 0x104 0x138 0x16C 0x1A0 0x1D4 0x208 0x23C 0x270 0x2A4 0x2D8 0x30C ) group.long ($2+0x2428)++0x3 line.long 0x0 "DOM_SEC_PER_$1,This register is only used for domain master to control secure access permission. When the domain master write this register. it only changes the secure permission for itself. When the domain master read this register. it gets permission.." bitfld.long 0x0 7. "DOM_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" newline bitfld.long 0x0 0. "DOM_SEC_EN,Domain secure permission control enable" "0,1" repeat.end repeat 16. (list 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1A 0x1B 0x1C 0x1D 0x1E 0x1F )(list 0x340 0x374 0x3A8 0x3DC 0x410 0x444 0x478 0x4AC 0x4E0 0x514 0x548 0x57C 0x5B0 0x5E4 0x618 0x64C ) group.long ($2+0x2428)++0x3 line.long 0x0 "DOM_SEC_PER_$1,This register is only used for domain master to control secure access permission. When the domain master write this register. it only changes the secure permission for itself. When the domain master read this register. it gets permission.." bitfld.long 0x0 7. "DOM_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" newline bitfld.long 0x0 0. "DOM_SEC_EN,Domain secure permission control enable" "0,1" repeat.end repeat 16. (list 0x20 0x21 0x22 0x23 0x24 0x25 0x26 0x27 0x28 0x29 0x2A 0x2B 0x2C 0x2D 0x2E 0x2F )(list 0x680 0x6B4 0x6E8 0x71C 0x750 0x784 0x7B8 0x7EC 0x820 0x854 0x888 0x8BC 0x8F0 0x924 0x958 0x98C ) group.long ($2+0x2428)++0x3 line.long 0x0 "DOM_SEC_PER_$1,This register is only used for domain master to control secure access permission. When the domain master write this register. it only changes the secure permission for itself. When the domain master read this register. it gets permission.." bitfld.long 0x0 7. "DOM_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" newline bitfld.long 0x0 0. "DOM_SEC_EN,Domain secure permission control enable" "0,1" repeat.end repeat 16. (list 0x30 0x31 0x32 0x33 0x34 0x35 0x36 0x37 0x38 0x39 0x3A 0x3B 0x3C 0x3D 0x3E 0x3F )(list 0x9C0 0x9F4 0xA28 0xA5C 0xA90 0xAC4 0xAF8 0xB2C 0xB60 0xB94 0xBC8 0xBFC 0xC30 0xC64 0xC98 0xCCC ) group.long ($2+0x2428)++0x3 line.long 0x0 "DOM_SEC_PER_$1,This register is only used for domain master to control secure access permission. When the domain master write this register. it only changes the secure permission for itself. When the domain master read this register. it gets permission.." bitfld.long 0x0 7. "DOM_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" newline bitfld.long 0x0 0. "DOM_SEC_EN,Domain secure permission control enable" "0,1" repeat.end repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x34 0x68 0x9C 0xD0 0x104 0x138 0x16C 0x1A0 0x1D4 0x208 0x23C 0x270 0x2A4 0x2D8 0x30C ) group.long ($2+0x242C)++0x3 line.long 0x0 "DOM_PRI_PER_$1,This register is only used for domain master to control secure access permission. When the domain master write this register. it only changes the secure permission for itself. When the domain master read this register. it gets permission.." bitfld.long 0x0 7. "DOM_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" newline bitfld.long 0x0 0. "DOM_PRI_EN,Domain privileged permission control enable" "0,1" repeat.end repeat 16. (list 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1A 0x1B 0x1C 0x1D 0x1E 0x1F )(list 0x340 0x374 0x3A8 0x3DC 0x410 0x444 0x478 0x4AC 0x4E0 0x514 0x548 0x57C 0x5B0 0x5E4 0x618 0x64C ) group.long ($2+0x242C)++0x3 line.long 0x0 "DOM_PRI_PER_$1,This register is only used for domain master to control secure access permission. When the domain master write this register. it only changes the secure permission for itself. When the domain master read this register. it gets permission.." bitfld.long 0x0 7. "DOM_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" newline bitfld.long 0x0 0. "DOM_PRI_EN,Domain privileged permission control enable" "0,1" repeat.end repeat 16. (list 0x20 0x21 0x22 0x23 0x24 0x25 0x26 0x27 0x28 0x29 0x2A 0x2B 0x2C 0x2D 0x2E 0x2F )(list 0x680 0x6B4 0x6E8 0x71C 0x750 0x784 0x7B8 0x7EC 0x820 0x854 0x888 0x8BC 0x8F0 0x924 0x958 0x98C ) group.long ($2+0x242C)++0x3 line.long 0x0 "DOM_PRI_PER_$1,This register is only used for domain master to control secure access permission. When the domain master write this register. it only changes the secure permission for itself. When the domain master read this register. it gets permission.." bitfld.long 0x0 7. "DOM_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" newline bitfld.long 0x0 0. "DOM_PRI_EN,Domain privileged permission control enable" "0,1" repeat.end repeat 16. (list 0x30 0x31 0x32 0x33 0x34 0x35 0x36 0x37 0x38 0x39 0x3A 0x3B 0x3C 0x3D 0x3E 0x3F )(list 0x9C0 0x9F4 0xA28 0xA5C 0xA90 0xAC4 0xAF8 0xB2C 0xB60 0xB94 0xBC8 0xBFC 0xC30 0xC64 0xC98 0xCCC ) group.long ($2+0x242C)++0x3 line.long 0x0 "DOM_PRI_PER_$1,This register is only used for domain master to control secure access permission. When the domain master write this register. it only changes the secure permission for itself. When the domain master read this register. it gets permission.." bitfld.long 0x0 7. "DOM_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" newline bitfld.long 0x0 0. "DOM_PRI_EN,Domain privileged permission control enable" "0,1" repeat.end repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x34 0x68 0x9C 0xD0 0x104 0x138 0x16C 0x1A0 0x1D4 0x208 0x23C 0x270 0x2A4 0x2D8 0x30C ) group.long ($2+0x2430)++0x3 line.long 0x0 "DOM_ASSIGN_$1,Use to assign domain for accessing DOM_SEC_PER and DOM_PRI_PER register. Only resource manager. group manager and domain owner can access this register. For write. group manager must write its owen domain ID. otherwise write accessing will.." hexmask.long.byte 0x0 0.--3. 1. "DID,accessing DOM_SEC_PER and DOM_PRI_PER register" repeat.end repeat 16. (list 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1A 0x1B 0x1C 0x1D 0x1E 0x1F )(list 0x340 0x374 0x3A8 0x3DC 0x410 0x444 0x478 0x4AC 0x4E0 0x514 0x548 0x57C 0x5B0 0x5E4 0x618 0x64C ) group.long ($2+0x2430)++0x3 line.long 0x0 "DOM_ASSIGN_$1,Use to assign domain for accessing DOM_SEC_PER and DOM_PRI_PER register. Only resource manager. group manager and domain owner can access this register. For write. group manager must write its owen domain ID. otherwise write accessing will.." hexmask.long.byte 0x0 0.--3. 1. "DID,accessing DOM_SEC_PER and DOM_PRI_PER register" repeat.end repeat 16. (list 0x20 0x21 0x22 0x23 0x24 0x25 0x26 0x27 0x28 0x29 0x2A 0x2B 0x2C 0x2D 0x2E 0x2F )(list 0x680 0x6B4 0x6E8 0x71C 0x750 0x784 0x7B8 0x7EC 0x820 0x854 0x888 0x8BC 0x8F0 0x924 0x958 0x98C ) group.long ($2+0x2430)++0x3 line.long 0x0 "DOM_ASSIGN_$1,Use to assign domain for accessing DOM_SEC_PER and DOM_PRI_PER register. Only resource manager. group manager and domain owner can access this register. For write. group manager must write its owen domain ID. otherwise write accessing will.." hexmask.long.byte 0x0 0.--3. 1. "DID,accessing DOM_SEC_PER and DOM_PRI_PER register" repeat.end repeat 16. (list 0x30 0x31 0x32 0x33 0x34 0x35 0x36 0x37 0x38 0x39 0x3A 0x3B 0x3C 0x3D 0x3E 0x3F )(list 0x9C0 0x9F4 0xA28 0xA5C 0xA90 0xAC4 0xAF8 0xB2C 0xB60 0xB94 0xBC8 0xBFC 0xC30 0xC64 0xC98 0xCCC ) group.long ($2+0x2430)++0x3 line.long 0x0 "DOM_ASSIGN_$1,Use to assign domain for accessing DOM_SEC_PER and DOM_PRI_PER register. Only resource manager. group manager and domain owner can access this register. For write. group manager must write its owen domain ID. otherwise write accessing will.." hexmask.long.byte 0x0 0.--3. 1. "DID,accessing DOM_SEC_PER and DOM_PRI_PER register" repeat.end repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x38 0x70 0xA8 0xE0 0x118 0x150 0x188 0x1C0 0x1F8 0x230 0x268 0x2A0 0x2D8 0x310 0x348 ) group.long ($2+0x3100)++0x3 line.long 0x0 "RGN_DOM_$1,Assign domain for peripheral. It can be only configured by resource and group manager" bitfld.long 0x0 31. "LOCK,When this bit is set lock write for all the bits in the register." "0,1" bitfld.long 0x0 4. "SET,Set together with DID would change permission of this resource to following setting: 1) Domain access control enabled. 2) Read/Write allowed for the domain owner. 3) Read/Write not allowed for all the other domains. If this bit is not set only DID.." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Assign domain for peripheral" repeat.end repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x38 0x70 0xA8 0xE0 0x118 0x150 0x188 0x1C0 0x1F8 0x230 0x268 0x2A0 0x2D8 0x310 0x348 ) group.long ($2+0x3104)++0x3 line.long 0x0 "RGN_DOM_PER0_$1,Domain Permission Control. It can be only configured by resource manager and domain owner." bitfld.long 0x0 31. "DOM7_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 29.--30. "DOM7_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 28. "DOM7_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 27. "DOM6_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 25.--26. "DOM6_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" newline bitfld.long 0x0 24. "DOM6_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 23. "DOM5_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 21.--22. "DOM5_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 20. "DOM5_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 19. "DOM4_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" newline bitfld.long 0x0 17.--18. "DOM4_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM4_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 15. "DOM3_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 13.--14. "DOM3_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 12. "DOM3_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" newline bitfld.long 0x0 11. "DOM2_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 9.--10. "DOM2_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM2_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 7. "DOM1_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 5.--6. "DOM1_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" newline bitfld.long 0x0 4. "DOM1_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 3. "DOM0_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 1.--2. "DOM0_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM0_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" repeat.end repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x38 0x70 0xA8 0xE0 0x118 0x150 0x188 0x1C0 0x1F8 0x230 0x268 0x2A0 0x2D8 0x310 0x348 ) group.long ($2+0x3108)++0x3 line.long 0x0 "RGN_DOM_PER1_$1,Domain Permission Control. It can be only configured by resource manager and domain owner." bitfld.long 0x0 31. "DOM15_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 29.--30. "DOM15_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 28. "DOM15_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 27. "DOM14_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 25.--26. "DOM14_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" newline bitfld.long 0x0 24. "DOM14_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 23. "DOM13_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 21.--22. "DOM13_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 20. "DOM13_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 19. "DOM12_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" newline bitfld.long 0x0 17.--18. "DOM12_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM12_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 15. "DOM11_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 13.--14. "DOM11_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 12. "DOM11_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" newline bitfld.long 0x0 11. "DOM10_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 9.--10. "DOM10_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM10_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 7. "DOM9_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 5.--6. "DOM9_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" newline bitfld.long 0x0 4. "DOM9_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 3. "DOM8_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 1.--2. "DOM8_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM8_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" repeat.end repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x38 0x70 0xA8 0xE0 0x118 0x150 0x188 0x1C0 0x1F8 0x230 0x268 0x2A0 0x2D8 0x310 0x348 ) group.long ($2+0x310C)++0x3 line.long 0x0 "RGN_SEC_PER0_$1,This register is only used for resource manager to control secure access permission." bitfld.long 0x0 31. "DOM3_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM3_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM3_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM3_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM2_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM2_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM2_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM2_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM1_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM1_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM1_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM1_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM0_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM0_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM0_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM0_SEC_EN,Domain secure permission control enable" "0,1" repeat.end repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x38 0x70 0xA8 0xE0 0x118 0x150 0x188 0x1C0 0x1F8 0x230 0x268 0x2A0 0x2D8 0x310 0x348 ) group.long ($2+0x3110)++0x3 line.long 0x0 "RGN_SEC_PER1_$1,This register is only used for resource manager to control secure access permission." bitfld.long 0x0 31. "DOM7_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM7_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM7_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM7_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM6_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM6_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM6_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM6_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM5_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM5_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM5_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM5_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM4_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM4_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM4_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM4_SEC_EN,Domain secure permission control enable" "0,1" repeat.end repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x38 0x70 0xA8 0xE0 0x118 0x150 0x188 0x1C0 0x1F8 0x230 0x268 0x2A0 0x2D8 0x310 0x348 ) group.long ($2+0x3114)++0x3 line.long 0x0 "RGN_SEC_PER2_$1,This register is only used for resource manager to control secure access permission." bitfld.long 0x0 31. "DOM11_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM11_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM11_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM11_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM10_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM10_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM10_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM10_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM9_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM9_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM9_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM9_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM8_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM8_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM8_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM8_SEC_EN,Domain secure permission control enable" "0,1" repeat.end repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x38 0x70 0xA8 0xE0 0x118 0x150 0x188 0x1C0 0x1F8 0x230 0x268 0x2A0 0x2D8 0x310 0x348 ) group.long ($2+0x3118)++0x3 line.long 0x0 "RGN_SEC_PER3_$1,This register is only used for resource manager to control secure access permission." bitfld.long 0x0 31. "DOM15_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM15_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM15_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM15_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM14_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM14_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM14_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM14_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM13_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM13_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM13_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM13_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM12_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM12_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM12_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM12_SEC_EN,Domain secure permission control enable" "0,1" repeat.end repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x38 0x70 0xA8 0xE0 0x118 0x150 0x188 0x1C0 0x1F8 0x230 0x268 0x2A0 0x2D8 0x310 0x348 ) group.long ($2+0x311C)++0x3 line.long 0x0 "RGN_PRI_PER0_$1,This register is only used for resource manager to control privileged access permission." bitfld.long 0x0 31. "DOM3_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM3_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM3_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM3_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM2_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM2_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM2_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM2_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM1_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM1_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM1_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM1_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM0_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM0_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM0_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM0_PRI_EN,Domain privileged permission control enable" "0,1" repeat.end repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x38 0x70 0xA8 0xE0 0x118 0x150 0x188 0x1C0 0x1F8 0x230 0x268 0x2A0 0x2D8 0x310 0x348 ) group.long ($2+0x3120)++0x3 line.long 0x0 "RGN_PRI_PER1_$1,This register is only used for resource manager to control privileged access permission." bitfld.long 0x0 31. "DOM7_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM7_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM7_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM7_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM6_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM6_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM6_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM6_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM5_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM5_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM5_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM5_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM4_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM4_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM4_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM4_PRI_EN,Domain privileged permission control enable" "0,1" repeat.end repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x38 0x70 0xA8 0xE0 0x118 0x150 0x188 0x1C0 0x1F8 0x230 0x268 0x2A0 0x2D8 0x310 0x348 ) group.long ($2+0x3124)++0x3 line.long 0x0 "RGN_PRI_PER2_$1,This register is only used for resource manager to control privileged access permission." bitfld.long 0x0 31. "DOM11_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM11_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM11_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM11_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM10_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM10_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM10_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM10_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM9_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM9_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM9_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM9_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM8_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM8_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM8_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM8_PRI_EN,Domain privileged permission control enable" "0,1" repeat.end repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x38 0x70 0xA8 0xE0 0x118 0x150 0x188 0x1C0 0x1F8 0x230 0x268 0x2A0 0x2D8 0x310 0x348 ) group.long ($2+0x3128)++0x3 line.long 0x0 "RGN_PRI_PER3_$1,This register is only used for resource manager to control privileged access permission." bitfld.long 0x0 31. "DOM15_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM15_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM15_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM15_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM14_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM14_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM14_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM14_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM13_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM13_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM13_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM13_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM12_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM12_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM12_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM12_PRI_EN,Domain privileged permission control enable" "0,1" repeat.end repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x38 0x70 0xA8 0xE0 0x118 0x150 0x188 0x1C0 0x1F8 0x230 0x268 0x2A0 0x2D8 0x310 0x348 ) group.long ($2+0x312C)++0x3 line.long 0x0 "RGN_DOM_SEC_PER_$1,This register is only used for domain master to control secure access permission. When the domain master write this register. it only changes the secure permission for itself. When the domain master read this register. it gets.." bitfld.long 0x0 7. "DOM_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" newline bitfld.long 0x0 0. "DOM_SEC_EN,Domain secure permission control enable" "0,1" repeat.end repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x38 0x70 0xA8 0xE0 0x118 0x150 0x188 0x1C0 0x1F8 0x230 0x268 0x2A0 0x2D8 0x310 0x348 ) group.long ($2+0x3130)++0x3 line.long 0x0 "RGN_DOM_PRI_PER_$1,This register is only used for domain master to control secure access permission. When the domain master write this register. it only changes the secure permission for itself. When the domain master read this register. it gets.." bitfld.long 0x0 7. "DOM_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" newline bitfld.long 0x0 0. "DOM_PRI_EN,Domain privileged permission control enable" "0,1" repeat.end repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x38 0x70 0xA8 0xE0 0x118 0x150 0x188 0x1C0 0x1F8 0x230 0x268 0x2A0 0x2D8 0x310 0x348 ) group.long ($2+0x3134)++0x3 line.long 0x0 "RGN_DOM_ASSIGN_$1,Use to assign domain for accessing DOM_SEC_PER and DOM_PRI_PER register. Only resource manager. group manager and domain owner can access this register. For write. group manager must write its owen domain ID. otherwise write accessing.." hexmask.long.byte 0x0 0.--3. 1. "DID,accessing DOM_SEC_PER and DOM_PRI_PER register" repeat.end tree.end tree "RPC_SAFETY_RSTGEN" base ad:0xFCC00000 repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x4 0x8 0xC 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C ) group.long ($2)++0x3 line.long 0x0 "REGG0_DOM_$1,Assign domain for CKGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1A 0x1B 0x1C 0x1D 0x1E 0x1F )(list 0x40 0x44 0x48 0x4C 0x50 0x54 0x58 0x5C 0x60 0x64 0x68 0x6C 0x70 0x74 0x78 0x7C ) group.long ($2)++0x3 line.long 0x0 "REGG0_DOM_$1,Assign domain for CKGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x20 0x21 0x22 0x23 0x24 0x25 0x26 0x27 0x28 0x29 0x2A 0x2B 0x2C 0x2D 0x2E 0x2F )(list 0x80 0x84 0x88 0x8C 0x90 0x94 0x98 0x9C 0xA0 0xA4 0xA8 0xAC 0xB0 0xB4 0xB8 0xBC ) group.long ($2)++0x3 line.long 0x0 "REGG0_DOM_$1,Assign domain for CKGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x30 0x31 0x32 0x33 0x34 0x35 0x36 0x37 0x38 0x39 0x3A 0x3B 0x3C 0x3D 0x3E 0x3F )(list 0xC0 0xC4 0xC8 0xCC 0xD0 0xD4 0xD8 0xDC 0xE0 0xE4 0xE8 0xEC 0xF0 0xF4 0xF8 0xFC ) group.long ($2)++0x3 line.long 0x0 "REGG0_DOM_$1,Assign domain for CKGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x40 0x41 0x42 0x43 0x44 0x45 0x46 0x47 0x48 0x49 0x4A 0x4B 0x4C 0x4D 0x4E 0x4F )(list 0x100 0x104 0x108 0x10C 0x110 0x114 0x118 0x11C 0x120 0x124 0x128 0x12C 0x130 0x134 0x138 0x13C ) group.long ($2)++0x3 line.long 0x0 "REGG0_DOM_$1,Assign domain for CKGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x50 0x51 0x52 0x53 0x54 0x55 0x56 0x57 0x58 0x59 0x5A 0x5B 0x5C 0x5D 0x5E 0x5F )(list 0x140 0x144 0x148 0x14C 0x150 0x154 0x158 0x15C 0x160 0x164 0x168 0x16C 0x170 0x174 0x178 0x17C ) group.long ($2)++0x3 line.long 0x0 "REGG0_DOM_$1,Assign domain for CKGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x60 0x61 0x62 0x63 0x64 0x65 0x66 0x67 0x68 0x69 0x6A 0x6B 0x6C 0x6D 0x6E 0x6F )(list 0x180 0x184 0x188 0x18C 0x190 0x194 0x198 0x19C 0x1A0 0x1A4 0x1A8 0x1AC 0x1B0 0x1B4 0x1B8 0x1BC ) group.long ($2)++0x3 line.long 0x0 "REGG0_DOM_$1,Assign domain for CKGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x70 0x71 0x72 0x73 0x74 0x75 0x76 0x77 0x78 0x79 0x7A 0x7B 0x7C 0x7D 0x7E 0x7F )(list 0x1C0 0x1C4 0x1C8 0x1CC 0x1D0 0x1D4 0x1D8 0x1DC 0x1E0 0x1E4 0x1E8 0x1EC 0x1F0 0x1F4 0x1F8 0x1FC ) group.long ($2)++0x3 line.long 0x0 "REGG0_DOM_$1,Assign domain for CKGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x80 0x81 0x82 0x83 0x84 0x85 0x86 0x87 0x88 0x89 0x8A 0x8B 0x8C 0x8D 0x8E 0x8F )(list 0x200 0x204 0x208 0x20C 0x210 0x214 0x218 0x21C 0x220 0x224 0x228 0x22C 0x230 0x234 0x238 0x23C ) group.long ($2)++0x3 line.long 0x0 "REGG0_DOM_$1,Assign domain for CKGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x90 0x91 0x92 0x93 0x94 0x95 0x96 0x97 0x98 0x99 0x9A 0x9B 0x9C 0x9D 0x9E 0x9F )(list 0x240 0x244 0x248 0x24C 0x250 0x254 0x258 0x25C 0x260 0x264 0x268 0x26C 0x270 0x274 0x278 0x27C ) group.long ($2)++0x3 line.long 0x0 "REGG0_DOM_$1,Assign domain for CKGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xA0 0xA1 0xA2 0xA3 0xA4 0xA5 0xA6 0xA7 0xA8 0xA9 0xAA 0xAB 0xAC 0xAD 0xAE 0xAF )(list 0x280 0x284 0x288 0x28C 0x290 0x294 0x298 0x29C 0x2A0 0x2A4 0x2A8 0x2AC 0x2B0 0x2B4 0x2B8 0x2BC ) group.long ($2)++0x3 line.long 0x0 "REGG0_DOM_$1,Assign domain for CKGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xB0 0xB1 0xB2 0xB3 0xB4 0xB5 0xB6 0xB7 0xB8 0xB9 0xBA 0xBB 0xBC 0xBD 0xBE 0xBF )(list 0x2C0 0x2C4 0x2C8 0x2CC 0x2D0 0x2D4 0x2D8 0x2DC 0x2E0 0x2E4 0x2E8 0x2EC 0x2F0 0x2F4 0x2F8 0x2FC ) group.long ($2)++0x3 line.long 0x0 "REGG0_DOM_$1,Assign domain for CKGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xC0 0xC1 0xC2 0xC3 0xC4 0xC5 0xC6 0xC7 0xC8 0xC9 0xCA 0xCB 0xCC 0xCD 0xCE 0xCF )(list 0x300 0x304 0x308 0x30C 0x310 0x314 0x318 0x31C 0x320 0x324 0x328 0x32C 0x330 0x334 0x338 0x33C ) group.long ($2)++0x3 line.long 0x0 "REGG0_DOM_$1,Assign domain for CKGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xD0 0xD1 0xD2 0xD3 0xD4 0xD5 0xD6 0xD7 0xD8 0xD9 0xDA 0xDB 0xDC 0xDD 0xDE 0xDF )(list 0x340 0x344 0x348 0x34C 0x350 0x354 0x358 0x35C 0x360 0x364 0x368 0x36C 0x370 0x374 0x378 0x37C ) group.long ($2)++0x3 line.long 0x0 "REGG0_DOM_$1,Assign domain for CKGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xE0 0xE1 0xE2 0xE3 0xE4 0xE5 0xE6 0xE7 0xE8 0xE9 0xEA 0xEB 0xEC 0xED 0xEE 0xEF )(list 0x380 0x384 0x388 0x38C 0x390 0x394 0x398 0x39C 0x3A0 0x3A4 0x3A8 0x3AC 0x3B0 0x3B4 0x3B8 0x3BC ) group.long ($2)++0x3 line.long 0x0 "REGG0_DOM_$1,Assign domain for CKGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xF0 0xF1 0xF2 0xF3 0xF4 0xF5 0xF6 0xF7 0xF8 0xF9 0xFA 0xFB 0xFC 0xFD 0xFE 0xFF )(list 0x3C0 0x3C4 0x3C8 0x3CC 0x3D0 0x3D4 0x3D8 0x3DC 0x3E0 0x3E4 0x3E8 0x3EC 0x3F0 0x3F4 0x3F8 0x3FC ) group.long ($2)++0x3 line.long 0x0 "REGG0_DOM_$1,Assign domain for CKGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x4 0x8 0xC 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C ) group.long ($2+0x400)++0x3 line.long 0x0 "REGG1_DOM_$1,Assign domain for CKGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1A 0x1B 0x1C 0x1D 0x1E 0x1F )(list 0x40 0x44 0x48 0x4C 0x50 0x54 0x58 0x5C 0x60 0x64 0x68 0x6C 0x70 0x74 0x78 0x7C ) group.long ($2+0x400)++0x3 line.long 0x0 "REGG1_DOM_$1,Assign domain for CKGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x20 0x21 0x22 0x23 0x24 0x25 0x26 0x27 0x28 0x29 0x2A 0x2B 0x2C 0x2D 0x2E 0x2F )(list 0x80 0x84 0x88 0x8C 0x90 0x94 0x98 0x9C 0xA0 0xA4 0xA8 0xAC 0xB0 0xB4 0xB8 0xBC ) group.long ($2+0x400)++0x3 line.long 0x0 "REGG1_DOM_$1,Assign domain for CKGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x30 0x31 0x32 0x33 0x34 0x35 0x36 0x37 0x38 0x39 0x3A 0x3B 0x3C 0x3D 0x3E 0x3F )(list 0xC0 0xC4 0xC8 0xCC 0xD0 0xD4 0xD8 0xDC 0xE0 0xE4 0xE8 0xEC 0xF0 0xF4 0xF8 0xFC ) group.long ($2+0x400)++0x3 line.long 0x0 "REGG1_DOM_$1,Assign domain for CKGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x40 0x41 0x42 0x43 0x44 0x45 0x46 0x47 0x48 0x49 0x4A 0x4B 0x4C 0x4D 0x4E 0x4F )(list 0x100 0x104 0x108 0x10C 0x110 0x114 0x118 0x11C 0x120 0x124 0x128 0x12C 0x130 0x134 0x138 0x13C ) group.long ($2+0x400)++0x3 line.long 0x0 "REGG1_DOM_$1,Assign domain for CKGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x50 0x51 0x52 0x53 0x54 0x55 0x56 0x57 0x58 0x59 0x5A 0x5B 0x5C 0x5D 0x5E 0x5F )(list 0x140 0x144 0x148 0x14C 0x150 0x154 0x158 0x15C 0x160 0x164 0x168 0x16C 0x170 0x174 0x178 0x17C ) group.long ($2+0x400)++0x3 line.long 0x0 "REGG1_DOM_$1,Assign domain for CKGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x60 0x61 0x62 0x63 0x64 0x65 0x66 0x67 0x68 0x69 0x6A 0x6B 0x6C 0x6D 0x6E 0x6F )(list 0x180 0x184 0x188 0x18C 0x190 0x194 0x198 0x19C 0x1A0 0x1A4 0x1A8 0x1AC 0x1B0 0x1B4 0x1B8 0x1BC ) group.long ($2+0x400)++0x3 line.long 0x0 "REGG1_DOM_$1,Assign domain for CKGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x70 0x71 0x72 0x73 0x74 0x75 0x76 0x77 0x78 0x79 0x7A 0x7B 0x7C 0x7D 0x7E 0x7F )(list 0x1C0 0x1C4 0x1C8 0x1CC 0x1D0 0x1D4 0x1D8 0x1DC 0x1E0 0x1E4 0x1E8 0x1EC 0x1F0 0x1F4 0x1F8 0x1FC ) group.long ($2+0x400)++0x3 line.long 0x0 "REGG1_DOM_$1,Assign domain for CKGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x80 0x81 0x82 0x83 0x84 0x85 0x86 0x87 0x88 0x89 0x8A 0x8B 0x8C 0x8D 0x8E 0x8F )(list 0x200 0x204 0x208 0x20C 0x210 0x214 0x218 0x21C 0x220 0x224 0x228 0x22C 0x230 0x234 0x238 0x23C ) group.long ($2+0x400)++0x3 line.long 0x0 "REGG1_DOM_$1,Assign domain for CKGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x90 0x91 0x92 0x93 0x94 0x95 0x96 0x97 0x98 0x99 0x9A 0x9B 0x9C 0x9D 0x9E 0x9F )(list 0x240 0x244 0x248 0x24C 0x250 0x254 0x258 0x25C 0x260 0x264 0x268 0x26C 0x270 0x274 0x278 0x27C ) group.long ($2+0x400)++0x3 line.long 0x0 "REGG1_DOM_$1,Assign domain for CKGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xA0 0xA1 0xA2 0xA3 0xA4 0xA5 0xA6 0xA7 0xA8 0xA9 0xAA 0xAB 0xAC 0xAD 0xAE 0xAF )(list 0x280 0x284 0x288 0x28C 0x290 0x294 0x298 0x29C 0x2A0 0x2A4 0x2A8 0x2AC 0x2B0 0x2B4 0x2B8 0x2BC ) group.long ($2+0x400)++0x3 line.long 0x0 "REGG1_DOM_$1,Assign domain for CKGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xB0 0xB1 0xB2 0xB3 0xB4 0xB5 0xB6 0xB7 0xB8 0xB9 0xBA 0xBB 0xBC 0xBD 0xBE 0xBF )(list 0x2C0 0x2C4 0x2C8 0x2CC 0x2D0 0x2D4 0x2D8 0x2DC 0x2E0 0x2E4 0x2E8 0x2EC 0x2F0 0x2F4 0x2F8 0x2FC ) group.long ($2+0x400)++0x3 line.long 0x0 "REGG1_DOM_$1,Assign domain for CKGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xC0 0xC1 0xC2 0xC3 0xC4 0xC5 0xC6 0xC7 0xC8 0xC9 0xCA 0xCB 0xCC 0xCD 0xCE 0xCF )(list 0x300 0x304 0x308 0x30C 0x310 0x314 0x318 0x31C 0x320 0x324 0x328 0x32C 0x330 0x334 0x338 0x33C ) group.long ($2+0x400)++0x3 line.long 0x0 "REGG1_DOM_$1,Assign domain for CKGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xD0 0xD1 0xD2 0xD3 0xD4 0xD5 0xD6 0xD7 0xD8 0xD9 0xDA 0xDB 0xDC 0xDD 0xDE 0xDF )(list 0x340 0x344 0x348 0x34C 0x350 0x354 0x358 0x35C 0x360 0x364 0x368 0x36C 0x370 0x374 0x378 0x37C ) group.long ($2+0x400)++0x3 line.long 0x0 "REGG1_DOM_$1,Assign domain for CKGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xE0 0xE1 0xE2 0xE3 0xE4 0xE5 0xE6 0xE7 0xE8 0xE9 0xEA 0xEB 0xEC 0xED 0xEE 0xEF )(list 0x380 0x384 0x388 0x38C 0x390 0x394 0x398 0x39C 0x3A0 0x3A4 0x3A8 0x3AC 0x3B0 0x3B4 0x3B8 0x3BC ) group.long ($2+0x400)++0x3 line.long 0x0 "REGG1_DOM_$1,Assign domain for CKGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xF0 0xF1 0xF2 0xF3 0xF4 0xF5 0xF6 0xF7 0xF8 0xF9 0xFA 0xFB 0xFC 0xFD 0xFE 0xFF )(list 0x3C0 0x3C4 0x3C8 0x3CC 0x3D0 0x3D4 0x3D8 0x3DC 0x3E0 0x3E4 0x3E8 0x3EC 0x3F0 0x3F4 0x3F8 0x3FC ) group.long ($2+0x400)++0x3 line.long 0x0 "REGG1_DOM_$1,Assign domain for CKGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x4 0x8 0xC 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C ) group.long ($2+0x800)++0x3 line.long 0x0 "REGG2_DOM_$1,Assign domain for SCR registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1A 0x1B 0x1C 0x1D 0x1E 0x1F )(list 0x40 0x44 0x48 0x4C 0x50 0x54 0x58 0x5C 0x60 0x64 0x68 0x6C 0x70 0x74 0x78 0x7C ) group.long ($2+0x800)++0x3 line.long 0x0 "REGG2_DOM_$1,Assign domain for SCR registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x20 0x21 0x22 0x23 0x24 0x25 0x26 0x27 0x28 0x29 0x2A 0x2B 0x2C 0x2D 0x2E 0x2F )(list 0x80 0x84 0x88 0x8C 0x90 0x94 0x98 0x9C 0xA0 0xA4 0xA8 0xAC 0xB0 0xB4 0xB8 0xBC ) group.long ($2+0x800)++0x3 line.long 0x0 "REGG2_DOM_$1,Assign domain for SCR registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x30 0x31 0x32 0x33 0x34 0x35 0x36 0x37 0x38 0x39 0x3A 0x3B 0x3C 0x3D 0x3E 0x3F )(list 0xC0 0xC4 0xC8 0xCC 0xD0 0xD4 0xD8 0xDC 0xE0 0xE4 0xE8 0xEC 0xF0 0xF4 0xF8 0xFC ) group.long ($2+0x800)++0x3 line.long 0x0 "REGG2_DOM_$1,Assign domain for SCR registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x40 0x41 0x42 0x43 0x44 0x45 0x46 0x47 0x48 0x49 0x4A 0x4B 0x4C 0x4D 0x4E 0x4F )(list 0x100 0x104 0x108 0x10C 0x110 0x114 0x118 0x11C 0x120 0x124 0x128 0x12C 0x130 0x134 0x138 0x13C ) group.long ($2+0x800)++0x3 line.long 0x0 "REGG2_DOM_$1,Assign domain for SCR registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x50 0x51 0x52 0x53 0x54 0x55 0x56 0x57 0x58 0x59 0x5A 0x5B 0x5C 0x5D 0x5E 0x5F )(list 0x140 0x144 0x148 0x14C 0x150 0x154 0x158 0x15C 0x160 0x164 0x168 0x16C 0x170 0x174 0x178 0x17C ) group.long ($2+0x800)++0x3 line.long 0x0 "REGG2_DOM_$1,Assign domain for SCR registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x60 0x61 0x62 0x63 0x64 0x65 0x66 0x67 0x68 0x69 0x6A 0x6B 0x6C 0x6D 0x6E 0x6F )(list 0x180 0x184 0x188 0x18C 0x190 0x194 0x198 0x19C 0x1A0 0x1A4 0x1A8 0x1AC 0x1B0 0x1B4 0x1B8 0x1BC ) group.long ($2+0x800)++0x3 line.long 0x0 "REGG2_DOM_$1,Assign domain for SCR registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x70 0x71 0x72 0x73 0x74 0x75 0x76 0x77 0x78 0x79 0x7A 0x7B 0x7C 0x7D 0x7E 0x7F )(list 0x1C0 0x1C4 0x1C8 0x1CC 0x1D0 0x1D4 0x1D8 0x1DC 0x1E0 0x1E4 0x1E8 0x1EC 0x1F0 0x1F4 0x1F8 0x1FC ) group.long ($2+0x800)++0x3 line.long 0x0 "REGG2_DOM_$1,Assign domain for SCR registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x80 0x81 0x82 0x83 0x84 0x85 0x86 0x87 0x88 0x89 0x8A 0x8B 0x8C 0x8D 0x8E 0x8F )(list 0x200 0x204 0x208 0x20C 0x210 0x214 0x218 0x21C 0x220 0x224 0x228 0x22C 0x230 0x234 0x238 0x23C ) group.long ($2+0x800)++0x3 line.long 0x0 "REGG2_DOM_$1,Assign domain for SCR registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x90 0x91 0x92 0x93 0x94 0x95 0x96 0x97 0x98 0x99 0x9A 0x9B 0x9C 0x9D 0x9E 0x9F )(list 0x240 0x244 0x248 0x24C 0x250 0x254 0x258 0x25C 0x260 0x264 0x268 0x26C 0x270 0x274 0x278 0x27C ) group.long ($2+0x800)++0x3 line.long 0x0 "REGG2_DOM_$1,Assign domain for SCR registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xA0 0xA1 0xA2 0xA3 0xA4 0xA5 0xA6 0xA7 0xA8 0xA9 0xAA 0xAB 0xAC 0xAD 0xAE 0xAF )(list 0x280 0x284 0x288 0x28C 0x290 0x294 0x298 0x29C 0x2A0 0x2A4 0x2A8 0x2AC 0x2B0 0x2B4 0x2B8 0x2BC ) group.long ($2+0x800)++0x3 line.long 0x0 "REGG2_DOM_$1,Assign domain for SCR registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xB0 0xB1 0xB2 0xB3 0xB4 0xB5 0xB6 0xB7 0xB8 0xB9 0xBA 0xBB 0xBC 0xBD 0xBE 0xBF )(list 0x2C0 0x2C4 0x2C8 0x2CC 0x2D0 0x2D4 0x2D8 0x2DC 0x2E0 0x2E4 0x2E8 0x2EC 0x2F0 0x2F4 0x2F8 0x2FC ) group.long ($2+0x800)++0x3 line.long 0x0 "REGG2_DOM_$1,Assign domain for SCR registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xC0 0xC1 0xC2 0xC3 0xC4 0xC5 0xC6 0xC7 0xC8 0xC9 0xCA 0xCB 0xCC 0xCD 0xCE 0xCF )(list 0x300 0x304 0x308 0x30C 0x310 0x314 0x318 0x31C 0x320 0x324 0x328 0x32C 0x330 0x334 0x338 0x33C ) group.long ($2+0x800)++0x3 line.long 0x0 "REGG2_DOM_$1,Assign domain for SCR registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xD0 0xD1 0xD2 0xD3 0xD4 0xD5 0xD6 0xD7 0xD8 0xD9 0xDA 0xDB 0xDC 0xDD 0xDE 0xDF )(list 0x340 0x344 0x348 0x34C 0x350 0x354 0x358 0x35C 0x360 0x364 0x368 0x36C 0x370 0x374 0x378 0x37C ) group.long ($2+0x800)++0x3 line.long 0x0 "REGG2_DOM_$1,Assign domain for SCR registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xE0 0xE1 0xE2 0xE3 0xE4 0xE5 0xE6 0xE7 0xE8 0xE9 0xEA 0xEB 0xEC 0xED 0xEE 0xEF )(list 0x380 0x384 0x388 0x38C 0x390 0x394 0x398 0x39C 0x3A0 0x3A4 0x3A8 0x3AC 0x3B0 0x3B4 0x3B8 0x3BC ) group.long ($2+0x800)++0x3 line.long 0x0 "REGG2_DOM_$1,Assign domain for SCR registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xF0 0xF1 0xF2 0xF3 0xF4 0xF5 0xF6 0xF7 0xF8 0xF9 0xFA 0xFB 0xFC 0xFD 0xFE 0xFF )(list 0x3C0 0x3C4 0x3C8 0x3CC 0x3D0 0x3D4 0x3D8 0x3DC 0x3E0 0x3E4 0x3E8 0x3EC 0x3F0 0x3F4 0x3F8 0x3FC ) group.long ($2+0x800)++0x3 line.long 0x0 "REGG2_DOM_$1,Assign domain for SCR registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x4 0x8 0xC 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C ) group.long ($2+0xC00)++0x3 line.long 0x0 "REGG3_DOM_$1,Assign domain for SCR registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1A 0x1B 0x1C 0x1D 0x1E 0x1F )(list 0x40 0x44 0x48 0x4C 0x50 0x54 0x58 0x5C 0x60 0x64 0x68 0x6C 0x70 0x74 0x78 0x7C ) group.long ($2+0xC00)++0x3 line.long 0x0 "REGG3_DOM_$1,Assign domain for SCR registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x20 0x21 0x22 0x23 0x24 0x25 0x26 0x27 0x28 0x29 0x2A 0x2B 0x2C 0x2D 0x2E 0x2F )(list 0x80 0x84 0x88 0x8C 0x90 0x94 0x98 0x9C 0xA0 0xA4 0xA8 0xAC 0xB0 0xB4 0xB8 0xBC ) group.long ($2+0xC00)++0x3 line.long 0x0 "REGG3_DOM_$1,Assign domain for SCR registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x30 0x31 0x32 0x33 0x34 0x35 0x36 0x37 0x38 0x39 0x3A 0x3B 0x3C 0x3D 0x3E 0x3F )(list 0xC0 0xC4 0xC8 0xCC 0xD0 0xD4 0xD8 0xDC 0xE0 0xE4 0xE8 0xEC 0xF0 0xF4 0xF8 0xFC ) group.long ($2+0xC00)++0x3 line.long 0x0 "REGG3_DOM_$1,Assign domain for SCR registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x40 0x41 0x42 0x43 0x44 0x45 0x46 0x47 0x48 0x49 0x4A 0x4B 0x4C 0x4D 0x4E 0x4F )(list 0x100 0x104 0x108 0x10C 0x110 0x114 0x118 0x11C 0x120 0x124 0x128 0x12C 0x130 0x134 0x138 0x13C ) group.long ($2+0xC00)++0x3 line.long 0x0 "REGG3_DOM_$1,Assign domain for SCR registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x50 0x51 0x52 0x53 0x54 0x55 0x56 0x57 0x58 0x59 0x5A 0x5B 0x5C 0x5D 0x5E 0x5F )(list 0x140 0x144 0x148 0x14C 0x150 0x154 0x158 0x15C 0x160 0x164 0x168 0x16C 0x170 0x174 0x178 0x17C ) group.long ($2+0xC00)++0x3 line.long 0x0 "REGG3_DOM_$1,Assign domain for SCR registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x60 0x61 0x62 0x63 0x64 0x65 0x66 0x67 0x68 0x69 0x6A 0x6B 0x6C 0x6D 0x6E 0x6F )(list 0x180 0x184 0x188 0x18C 0x190 0x194 0x198 0x19C 0x1A0 0x1A4 0x1A8 0x1AC 0x1B0 0x1B4 0x1B8 0x1BC ) group.long ($2+0xC00)++0x3 line.long 0x0 "REGG3_DOM_$1,Assign domain for SCR registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x70 0x71 0x72 0x73 0x74 0x75 0x76 0x77 0x78 0x79 0x7A 0x7B 0x7C 0x7D 0x7E 0x7F )(list 0x1C0 0x1C4 0x1C8 0x1CC 0x1D0 0x1D4 0x1D8 0x1DC 0x1E0 0x1E4 0x1E8 0x1EC 0x1F0 0x1F4 0x1F8 0x1FC ) group.long ($2+0xC00)++0x3 line.long 0x0 "REGG3_DOM_$1,Assign domain for SCR registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x80 0x81 0x82 0x83 0x84 0x85 0x86 0x87 0x88 0x89 0x8A 0x8B 0x8C 0x8D 0x8E 0x8F )(list 0x200 0x204 0x208 0x20C 0x210 0x214 0x218 0x21C 0x220 0x224 0x228 0x22C 0x230 0x234 0x238 0x23C ) group.long ($2+0xC00)++0x3 line.long 0x0 "REGG3_DOM_$1,Assign domain for SCR registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x90 0x91 0x92 0x93 0x94 0x95 0x96 0x97 0x98 0x99 0x9A 0x9B 0x9C 0x9D 0x9E 0x9F )(list 0x240 0x244 0x248 0x24C 0x250 0x254 0x258 0x25C 0x260 0x264 0x268 0x26C 0x270 0x274 0x278 0x27C ) group.long ($2+0xC00)++0x3 line.long 0x0 "REGG3_DOM_$1,Assign domain for SCR registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xA0 0xA1 0xA2 0xA3 0xA4 0xA5 0xA6 0xA7 0xA8 0xA9 0xAA 0xAB 0xAC 0xAD 0xAE 0xAF )(list 0x280 0x284 0x288 0x28C 0x290 0x294 0x298 0x29C 0x2A0 0x2A4 0x2A8 0x2AC 0x2B0 0x2B4 0x2B8 0x2BC ) group.long ($2+0xC00)++0x3 line.long 0x0 "REGG3_DOM_$1,Assign domain for SCR registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xB0 0xB1 0xB2 0xB3 0xB4 0xB5 0xB6 0xB7 0xB8 0xB9 0xBA 0xBB 0xBC 0xBD 0xBE 0xBF )(list 0x2C0 0x2C4 0x2C8 0x2CC 0x2D0 0x2D4 0x2D8 0x2DC 0x2E0 0x2E4 0x2E8 0x2EC 0x2F0 0x2F4 0x2F8 0x2FC ) group.long ($2+0xC00)++0x3 line.long 0x0 "REGG3_DOM_$1,Assign domain for SCR registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xC0 0xC1 0xC2 0xC3 0xC4 0xC5 0xC6 0xC7 0xC8 0xC9 0xCA 0xCB 0xCC 0xCD 0xCE 0xCF )(list 0x300 0x304 0x308 0x30C 0x310 0x314 0x318 0x31C 0x320 0x324 0x328 0x32C 0x330 0x334 0x338 0x33C ) group.long ($2+0xC00)++0x3 line.long 0x0 "REGG3_DOM_$1,Assign domain for SCR registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xD0 0xD1 0xD2 0xD3 0xD4 0xD5 0xD6 0xD7 0xD8 0xD9 0xDA 0xDB 0xDC 0xDD 0xDE 0xDF )(list 0x340 0x344 0x348 0x34C 0x350 0x354 0x358 0x35C 0x360 0x364 0x368 0x36C 0x370 0x374 0x378 0x37C ) group.long ($2+0xC00)++0x3 line.long 0x0 "REGG3_DOM_$1,Assign domain for SCR registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xE0 0xE1 0xE2 0xE3 0xE4 0xE5 0xE6 0xE7 0xE8 0xE9 0xEA 0xEB 0xEC 0xED 0xEE 0xEF )(list 0x380 0x384 0x388 0x38C 0x390 0x394 0x398 0x39C 0x3A0 0x3A4 0x3A8 0x3AC 0x3B0 0x3B4 0x3B8 0x3BC ) group.long ($2+0xC00)++0x3 line.long 0x0 "REGG3_DOM_$1,Assign domain for SCR registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xF0 0xF1 0xF2 0xF3 0xF4 0xF5 0xF6 0xF7 0xF8 0xF9 0xFA 0xFB 0xFC 0xFD 0xFE 0xFF )(list 0x3C0 0x3C4 0x3C8 0x3CC 0x3D0 0x3D4 0x3D8 0x3DC 0x3E0 0x3E4 0x3E8 0x3EC 0x3F0 0x3F4 0x3F8 0x3FC ) group.long ($2+0xC00)++0x3 line.long 0x0 "REGG3_DOM_$1,Assign domain for SCR registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x4 0x8 0xC 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C ) group.long ($2+0x1000)++0x3 line.long 0x0 "REGG4_DOM_$1,Assign domain for RSTGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1A 0x1B 0x1C 0x1D 0x1E 0x1F )(list 0x40 0x44 0x48 0x4C 0x50 0x54 0x58 0x5C 0x60 0x64 0x68 0x6C 0x70 0x74 0x78 0x7C ) group.long ($2+0x1000)++0x3 line.long 0x0 "REGG4_DOM_$1,Assign domain for RSTGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x20 0x21 0x22 0x23 0x24 0x25 0x26 0x27 0x28 0x29 0x2A 0x2B 0x2C 0x2D 0x2E 0x2F )(list 0x80 0x84 0x88 0x8C 0x90 0x94 0x98 0x9C 0xA0 0xA4 0xA8 0xAC 0xB0 0xB4 0xB8 0xBC ) group.long ($2+0x1000)++0x3 line.long 0x0 "REGG4_DOM_$1,Assign domain for RSTGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x30 0x31 0x32 0x33 0x34 0x35 0x36 0x37 0x38 0x39 0x3A 0x3B 0x3C 0x3D 0x3E 0x3F )(list 0xC0 0xC4 0xC8 0xCC 0xD0 0xD4 0xD8 0xDC 0xE0 0xE4 0xE8 0xEC 0xF0 0xF4 0xF8 0xFC ) group.long ($2+0x1000)++0x3 line.long 0x0 "REGG4_DOM_$1,Assign domain for RSTGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x40 0x41 0x42 0x43 0x44 0x45 0x46 0x47 0x48 0x49 0x4A 0x4B 0x4C 0x4D 0x4E 0x4F )(list 0x100 0x104 0x108 0x10C 0x110 0x114 0x118 0x11C 0x120 0x124 0x128 0x12C 0x130 0x134 0x138 0x13C ) group.long ($2+0x1000)++0x3 line.long 0x0 "REGG4_DOM_$1,Assign domain for RSTGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x50 0x51 0x52 0x53 0x54 0x55 0x56 0x57 0x58 0x59 0x5A 0x5B 0x5C 0x5D 0x5E 0x5F )(list 0x140 0x144 0x148 0x14C 0x150 0x154 0x158 0x15C 0x160 0x164 0x168 0x16C 0x170 0x174 0x178 0x17C ) group.long ($2+0x1000)++0x3 line.long 0x0 "REGG4_DOM_$1,Assign domain for RSTGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x60 0x61 0x62 0x63 0x64 0x65 0x66 0x67 0x68 0x69 0x6A 0x6B 0x6C 0x6D 0x6E 0x6F )(list 0x180 0x184 0x188 0x18C 0x190 0x194 0x198 0x19C 0x1A0 0x1A4 0x1A8 0x1AC 0x1B0 0x1B4 0x1B8 0x1BC ) group.long ($2+0x1000)++0x3 line.long 0x0 "REGG4_DOM_$1,Assign domain for RSTGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x70 0x71 0x72 0x73 0x74 0x75 0x76 0x77 0x78 0x79 0x7A 0x7B 0x7C 0x7D 0x7E 0x7F )(list 0x1C0 0x1C4 0x1C8 0x1CC 0x1D0 0x1D4 0x1D8 0x1DC 0x1E0 0x1E4 0x1E8 0x1EC 0x1F0 0x1F4 0x1F8 0x1FC ) group.long ($2+0x1000)++0x3 line.long 0x0 "REGG4_DOM_$1,Assign domain for RSTGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x80 0x81 0x82 0x83 0x84 0x85 0x86 0x87 0x88 0x89 0x8A 0x8B 0x8C 0x8D 0x8E 0x8F )(list 0x200 0x204 0x208 0x20C 0x210 0x214 0x218 0x21C 0x220 0x224 0x228 0x22C 0x230 0x234 0x238 0x23C ) group.long ($2+0x1000)++0x3 line.long 0x0 "REGG4_DOM_$1,Assign domain for RSTGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x90 0x91 0x92 0x93 0x94 0x95 0x96 0x97 0x98 0x99 0x9A 0x9B 0x9C 0x9D 0x9E 0x9F )(list 0x240 0x244 0x248 0x24C 0x250 0x254 0x258 0x25C 0x260 0x264 0x268 0x26C 0x270 0x274 0x278 0x27C ) group.long ($2+0x1000)++0x3 line.long 0x0 "REGG4_DOM_$1,Assign domain for RSTGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xA0 0xA1 0xA2 0xA3 0xA4 0xA5 0xA6 0xA7 0xA8 0xA9 0xAA 0xAB 0xAC 0xAD 0xAE 0xAF )(list 0x280 0x284 0x288 0x28C 0x290 0x294 0x298 0x29C 0x2A0 0x2A4 0x2A8 0x2AC 0x2B0 0x2B4 0x2B8 0x2BC ) group.long ($2+0x1000)++0x3 line.long 0x0 "REGG4_DOM_$1,Assign domain for RSTGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xB0 0xB1 0xB2 0xB3 0xB4 0xB5 0xB6 0xB7 0xB8 0xB9 0xBA 0xBB 0xBC 0xBD 0xBE 0xBF )(list 0x2C0 0x2C4 0x2C8 0x2CC 0x2D0 0x2D4 0x2D8 0x2DC 0x2E0 0x2E4 0x2E8 0x2EC 0x2F0 0x2F4 0x2F8 0x2FC ) group.long ($2+0x1000)++0x3 line.long 0x0 "REGG4_DOM_$1,Assign domain for RSTGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xC0 0xC1 0xC2 0xC3 0xC4 0xC5 0xC6 0xC7 0xC8 0xC9 0xCA 0xCB 0xCC 0xCD 0xCE 0xCF )(list 0x300 0x304 0x308 0x30C 0x310 0x314 0x318 0x31C 0x320 0x324 0x328 0x32C 0x330 0x334 0x338 0x33C ) group.long ($2+0x1000)++0x3 line.long 0x0 "REGG4_DOM_$1,Assign domain for RSTGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xD0 0xD1 0xD2 0xD3 0xD4 0xD5 0xD6 0xD7 0xD8 0xD9 0xDA 0xDB 0xDC 0xDD 0xDE 0xDF )(list 0x340 0x344 0x348 0x34C 0x350 0x354 0x358 0x35C 0x360 0x364 0x368 0x36C 0x370 0x374 0x378 0x37C ) group.long ($2+0x1000)++0x3 line.long 0x0 "REGG4_DOM_$1,Assign domain for RSTGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xE0 0xE1 0xE2 0xE3 0xE4 0xE5 0xE6 0xE7 0xE8 0xE9 0xEA 0xEB 0xEC 0xED 0xEE 0xEF )(list 0x380 0x384 0x388 0x38C 0x390 0x394 0x398 0x39C 0x3A0 0x3A4 0x3A8 0x3AC 0x3B0 0x3B4 0x3B8 0x3BC ) group.long ($2+0x1000)++0x3 line.long 0x0 "REGG4_DOM_$1,Assign domain for RSTGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xF0 0xF1 0xF2 0xF3 0xF4 0xF5 0xF6 0xF7 0xF8 0xF9 0xFA 0xFB 0xFC 0xFD 0xFE 0xFF )(list 0x3C0 0x3C4 0x3C8 0x3CC 0x3D0 0x3D4 0x3D8 0x3DC 0x3E0 0x3E4 0x3E8 0x3EC 0x3F0 0x3F4 0x3F8 0x3FC ) group.long ($2+0x1000)++0x3 line.long 0x0 "REGG4_DOM_$1,Assign domain for RSTGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x4 0x8 0xC 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C ) group.long ($2+0x1400)++0x3 line.long 0x0 "REGG5_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1A 0x1B 0x1C 0x1D 0x1E 0x1F )(list 0x40 0x44 0x48 0x4C 0x50 0x54 0x58 0x5C 0x60 0x64 0x68 0x6C 0x70 0x74 0x78 0x7C ) group.long ($2+0x1400)++0x3 line.long 0x0 "REGG5_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x20 0x21 0x22 0x23 0x24 0x25 0x26 0x27 0x28 0x29 0x2A 0x2B 0x2C 0x2D 0x2E 0x2F )(list 0x80 0x84 0x88 0x8C 0x90 0x94 0x98 0x9C 0xA0 0xA4 0xA8 0xAC 0xB0 0xB4 0xB8 0xBC ) group.long ($2+0x1400)++0x3 line.long 0x0 "REGG5_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x30 0x31 0x32 0x33 0x34 0x35 0x36 0x37 0x38 0x39 0x3A 0x3B 0x3C 0x3D 0x3E 0x3F )(list 0xC0 0xC4 0xC8 0xCC 0xD0 0xD4 0xD8 0xDC 0xE0 0xE4 0xE8 0xEC 0xF0 0xF4 0xF8 0xFC ) group.long ($2+0x1400)++0x3 line.long 0x0 "REGG5_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x40 0x41 0x42 0x43 0x44 0x45 0x46 0x47 0x48 0x49 0x4A 0x4B 0x4C 0x4D 0x4E 0x4F )(list 0x100 0x104 0x108 0x10C 0x110 0x114 0x118 0x11C 0x120 0x124 0x128 0x12C 0x130 0x134 0x138 0x13C ) group.long ($2+0x1400)++0x3 line.long 0x0 "REGG5_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x50 0x51 0x52 0x53 0x54 0x55 0x56 0x57 0x58 0x59 0x5A 0x5B 0x5C 0x5D 0x5E 0x5F )(list 0x140 0x144 0x148 0x14C 0x150 0x154 0x158 0x15C 0x160 0x164 0x168 0x16C 0x170 0x174 0x178 0x17C ) group.long ($2+0x1400)++0x3 line.long 0x0 "REGG5_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x60 0x61 0x62 0x63 0x64 0x65 0x66 0x67 0x68 0x69 0x6A 0x6B 0x6C 0x6D 0x6E 0x6F )(list 0x180 0x184 0x188 0x18C 0x190 0x194 0x198 0x19C 0x1A0 0x1A4 0x1A8 0x1AC 0x1B0 0x1B4 0x1B8 0x1BC ) group.long ($2+0x1400)++0x3 line.long 0x0 "REGG5_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x70 0x71 0x72 0x73 0x74 0x75 0x76 0x77 0x78 0x79 0x7A 0x7B 0x7C 0x7D 0x7E 0x7F )(list 0x1C0 0x1C4 0x1C8 0x1CC 0x1D0 0x1D4 0x1D8 0x1DC 0x1E0 0x1E4 0x1E8 0x1EC 0x1F0 0x1F4 0x1F8 0x1FC ) group.long ($2+0x1400)++0x3 line.long 0x0 "REGG5_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x80 0x81 0x82 0x83 0x84 0x85 0x86 0x87 0x88 0x89 0x8A 0x8B 0x8C 0x8D 0x8E 0x8F )(list 0x200 0x204 0x208 0x20C 0x210 0x214 0x218 0x21C 0x220 0x224 0x228 0x22C 0x230 0x234 0x238 0x23C ) group.long ($2+0x1400)++0x3 line.long 0x0 "REGG5_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x90 0x91 0x92 0x93 0x94 0x95 0x96 0x97 0x98 0x99 0x9A 0x9B 0x9C 0x9D 0x9E 0x9F )(list 0x240 0x244 0x248 0x24C 0x250 0x254 0x258 0x25C 0x260 0x264 0x268 0x26C 0x270 0x274 0x278 0x27C ) group.long ($2+0x1400)++0x3 line.long 0x0 "REGG5_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xA0 0xA1 0xA2 0xA3 0xA4 0xA5 0xA6 0xA7 0xA8 0xA9 0xAA 0xAB 0xAC 0xAD 0xAE 0xAF )(list 0x280 0x284 0x288 0x28C 0x290 0x294 0x298 0x29C 0x2A0 0x2A4 0x2A8 0x2AC 0x2B0 0x2B4 0x2B8 0x2BC ) group.long ($2+0x1400)++0x3 line.long 0x0 "REGG5_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xB0 0xB1 0xB2 0xB3 0xB4 0xB5 0xB6 0xB7 0xB8 0xB9 0xBA 0xBB 0xBC 0xBD 0xBE 0xBF )(list 0x2C0 0x2C4 0x2C8 0x2CC 0x2D0 0x2D4 0x2D8 0x2DC 0x2E0 0x2E4 0x2E8 0x2EC 0x2F0 0x2F4 0x2F8 0x2FC ) group.long ($2+0x1400)++0x3 line.long 0x0 "REGG5_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xC0 0xC1 0xC2 0xC3 0xC4 0xC5 0xC6 0xC7 0xC8 0xC9 0xCA 0xCB 0xCC 0xCD 0xCE 0xCF )(list 0x300 0x304 0x308 0x30C 0x310 0x314 0x318 0x31C 0x320 0x324 0x328 0x32C 0x330 0x334 0x338 0x33C ) group.long ($2+0x1400)++0x3 line.long 0x0 "REGG5_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xD0 0xD1 0xD2 0xD3 0xD4 0xD5 0xD6 0xD7 0xD8 0xD9 0xDA 0xDB 0xDC 0xDD 0xDE 0xDF )(list 0x340 0x344 0x348 0x34C 0x350 0x354 0x358 0x35C 0x360 0x364 0x368 0x36C 0x370 0x374 0x378 0x37C ) group.long ($2+0x1400)++0x3 line.long 0x0 "REGG5_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xE0 0xE1 0xE2 0xE3 0xE4 0xE5 0xE6 0xE7 0xE8 0xE9 0xEA 0xEB 0xEC 0xED 0xEE 0xEF )(list 0x380 0x384 0x388 0x38C 0x390 0x394 0x398 0x39C 0x3A0 0x3A4 0x3A8 0x3AC 0x3B0 0x3B4 0x3B8 0x3BC ) group.long ($2+0x1400)++0x3 line.long 0x0 "REGG5_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xF0 0xF1 0xF2 0xF3 0xF4 0xF5 0xF6 0xF7 0xF8 0xF9 0xFA 0xFB 0xFC 0xFD 0xFE 0xFF )(list 0x3C0 0x3C4 0x3C8 0x3CC 0x3D0 0x3D4 0x3D8 0x3DC 0x3E0 0x3E4 0x3E8 0x3EC 0x3F0 0x3F4 0x3F8 0x3FC ) group.long ($2+0x1400)++0x3 line.long 0x0 "REGG5_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x4 0x8 0xC 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C ) group.long ($2+0x1800)++0x3 line.long 0x0 "REGG6_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1A 0x1B 0x1C 0x1D 0x1E 0x1F )(list 0x40 0x44 0x48 0x4C 0x50 0x54 0x58 0x5C 0x60 0x64 0x68 0x6C 0x70 0x74 0x78 0x7C ) group.long ($2+0x1800)++0x3 line.long 0x0 "REGG6_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x20 0x21 0x22 0x23 0x24 0x25 0x26 0x27 0x28 0x29 0x2A 0x2B 0x2C 0x2D 0x2E 0x2F )(list 0x80 0x84 0x88 0x8C 0x90 0x94 0x98 0x9C 0xA0 0xA4 0xA8 0xAC 0xB0 0xB4 0xB8 0xBC ) group.long ($2+0x1800)++0x3 line.long 0x0 "REGG6_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x30 0x31 0x32 0x33 0x34 0x35 0x36 0x37 0x38 0x39 0x3A 0x3B 0x3C 0x3D 0x3E 0x3F )(list 0xC0 0xC4 0xC8 0xCC 0xD0 0xD4 0xD8 0xDC 0xE0 0xE4 0xE8 0xEC 0xF0 0xF4 0xF8 0xFC ) group.long ($2+0x1800)++0x3 line.long 0x0 "REGG6_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x40 0x41 0x42 0x43 0x44 0x45 0x46 0x47 0x48 0x49 0x4A 0x4B 0x4C 0x4D 0x4E 0x4F )(list 0x100 0x104 0x108 0x10C 0x110 0x114 0x118 0x11C 0x120 0x124 0x128 0x12C 0x130 0x134 0x138 0x13C ) group.long ($2+0x1800)++0x3 line.long 0x0 "REGG6_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x50 0x51 0x52 0x53 0x54 0x55 0x56 0x57 0x58 0x59 0x5A 0x5B 0x5C 0x5D 0x5E 0x5F )(list 0x140 0x144 0x148 0x14C 0x150 0x154 0x158 0x15C 0x160 0x164 0x168 0x16C 0x170 0x174 0x178 0x17C ) group.long ($2+0x1800)++0x3 line.long 0x0 "REGG6_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x60 0x61 0x62 0x63 0x64 0x65 0x66 0x67 0x68 0x69 0x6A 0x6B 0x6C 0x6D 0x6E 0x6F )(list 0x180 0x184 0x188 0x18C 0x190 0x194 0x198 0x19C 0x1A0 0x1A4 0x1A8 0x1AC 0x1B0 0x1B4 0x1B8 0x1BC ) group.long ($2+0x1800)++0x3 line.long 0x0 "REGG6_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x70 0x71 0x72 0x73 0x74 0x75 0x76 0x77 0x78 0x79 0x7A 0x7B 0x7C 0x7D 0x7E 0x7F )(list 0x1C0 0x1C4 0x1C8 0x1CC 0x1D0 0x1D4 0x1D8 0x1DC 0x1E0 0x1E4 0x1E8 0x1EC 0x1F0 0x1F4 0x1F8 0x1FC ) group.long ($2+0x1800)++0x3 line.long 0x0 "REGG6_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x80 0x81 0x82 0x83 0x84 0x85 0x86 0x87 0x88 0x89 0x8A 0x8B 0x8C 0x8D 0x8E 0x8F )(list 0x200 0x204 0x208 0x20C 0x210 0x214 0x218 0x21C 0x220 0x224 0x228 0x22C 0x230 0x234 0x238 0x23C ) group.long ($2+0x1800)++0x3 line.long 0x0 "REGG6_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x90 0x91 0x92 0x93 0x94 0x95 0x96 0x97 0x98 0x99 0x9A 0x9B 0x9C 0x9D 0x9E 0x9F )(list 0x240 0x244 0x248 0x24C 0x250 0x254 0x258 0x25C 0x260 0x264 0x268 0x26C 0x270 0x274 0x278 0x27C ) group.long ($2+0x1800)++0x3 line.long 0x0 "REGG6_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xA0 0xA1 0xA2 0xA3 0xA4 0xA5 0xA6 0xA7 0xA8 0xA9 0xAA 0xAB 0xAC 0xAD 0xAE 0xAF )(list 0x280 0x284 0x288 0x28C 0x290 0x294 0x298 0x29C 0x2A0 0x2A4 0x2A8 0x2AC 0x2B0 0x2B4 0x2B8 0x2BC ) group.long ($2+0x1800)++0x3 line.long 0x0 "REGG6_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xB0 0xB1 0xB2 0xB3 0xB4 0xB5 0xB6 0xB7 0xB8 0xB9 0xBA 0xBB 0xBC 0xBD 0xBE 0xBF )(list 0x2C0 0x2C4 0x2C8 0x2CC 0x2D0 0x2D4 0x2D8 0x2DC 0x2E0 0x2E4 0x2E8 0x2EC 0x2F0 0x2F4 0x2F8 0x2FC ) group.long ($2+0x1800)++0x3 line.long 0x0 "REGG6_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xC0 0xC1 0xC2 0xC3 0xC4 0xC5 0xC6 0xC7 0xC8 0xC9 0xCA 0xCB 0xCC 0xCD 0xCE 0xCF )(list 0x300 0x304 0x308 0x30C 0x310 0x314 0x318 0x31C 0x320 0x324 0x328 0x32C 0x330 0x334 0x338 0x33C ) group.long ($2+0x1800)++0x3 line.long 0x0 "REGG6_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xD0 0xD1 0xD2 0xD3 0xD4 0xD5 0xD6 0xD7 0xD8 0xD9 0xDA 0xDB 0xDC 0xDD 0xDE 0xDF )(list 0x340 0x344 0x348 0x34C 0x350 0x354 0x358 0x35C 0x360 0x364 0x368 0x36C 0x370 0x374 0x378 0x37C ) group.long ($2+0x1800)++0x3 line.long 0x0 "REGG6_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xE0 0xE1 0xE2 0xE3 0xE4 0xE5 0xE6 0xE7 0xE8 0xE9 0xEA 0xEB 0xEC 0xED 0xEE 0xEF )(list 0x380 0x384 0x388 0x38C 0x390 0x394 0x398 0x39C 0x3A0 0x3A4 0x3A8 0x3AC 0x3B0 0x3B4 0x3B8 0x3BC ) group.long ($2+0x1800)++0x3 line.long 0x0 "REGG6_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xF0 0xF1 0xF2 0xF3 0xF4 0xF5 0xF6 0xF7 0xF8 0xF9 0xFA 0xFB 0xFC 0xFD 0xFE 0xFF )(list 0x3C0 0x3C4 0x3C8 0x3CC 0x3D0 0x3D4 0x3D8 0x3DC 0x3E0 0x3E4 0x3E8 0x3EC 0x3F0 0x3F4 0x3F8 0x3FC ) group.long ($2+0x1800)++0x3 line.long 0x0 "REGG6_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x4 0x8 0xC 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C ) group.long ($2+0x1C00)++0x3 line.long 0x0 "REGG7_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1A 0x1B 0x1C 0x1D 0x1E 0x1F )(list 0x40 0x44 0x48 0x4C 0x50 0x54 0x58 0x5C 0x60 0x64 0x68 0x6C 0x70 0x74 0x78 0x7C ) group.long ($2+0x1C00)++0x3 line.long 0x0 "REGG7_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x20 0x21 0x22 0x23 0x24 0x25 0x26 0x27 0x28 0x29 0x2A 0x2B 0x2C 0x2D 0x2E 0x2F )(list 0x80 0x84 0x88 0x8C 0x90 0x94 0x98 0x9C 0xA0 0xA4 0xA8 0xAC 0xB0 0xB4 0xB8 0xBC ) group.long ($2+0x1C00)++0x3 line.long 0x0 "REGG7_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x30 0x31 0x32 0x33 0x34 0x35 0x36 0x37 0x38 0x39 0x3A 0x3B 0x3C 0x3D 0x3E 0x3F )(list 0xC0 0xC4 0xC8 0xCC 0xD0 0xD4 0xD8 0xDC 0xE0 0xE4 0xE8 0xEC 0xF0 0xF4 0xF8 0xFC ) group.long ($2+0x1C00)++0x3 line.long 0x0 "REGG7_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x40 0x41 0x42 0x43 0x44 0x45 0x46 0x47 0x48 0x49 0x4A 0x4B 0x4C 0x4D 0x4E 0x4F )(list 0x100 0x104 0x108 0x10C 0x110 0x114 0x118 0x11C 0x120 0x124 0x128 0x12C 0x130 0x134 0x138 0x13C ) group.long ($2+0x1C00)++0x3 line.long 0x0 "REGG7_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x50 0x51 0x52 0x53 0x54 0x55 0x56 0x57 0x58 0x59 0x5A 0x5B 0x5C 0x5D 0x5E 0x5F )(list 0x140 0x144 0x148 0x14C 0x150 0x154 0x158 0x15C 0x160 0x164 0x168 0x16C 0x170 0x174 0x178 0x17C ) group.long ($2+0x1C00)++0x3 line.long 0x0 "REGG7_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x60 0x61 0x62 0x63 0x64 0x65 0x66 0x67 0x68 0x69 0x6A 0x6B 0x6C 0x6D 0x6E 0x6F )(list 0x180 0x184 0x188 0x18C 0x190 0x194 0x198 0x19C 0x1A0 0x1A4 0x1A8 0x1AC 0x1B0 0x1B4 0x1B8 0x1BC ) group.long ($2+0x1C00)++0x3 line.long 0x0 "REGG7_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x70 0x71 0x72 0x73 0x74 0x75 0x76 0x77 0x78 0x79 0x7A 0x7B 0x7C 0x7D 0x7E 0x7F )(list 0x1C0 0x1C4 0x1C8 0x1CC 0x1D0 0x1D4 0x1D8 0x1DC 0x1E0 0x1E4 0x1E8 0x1EC 0x1F0 0x1F4 0x1F8 0x1FC ) group.long ($2+0x1C00)++0x3 line.long 0x0 "REGG7_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x80 0x81 0x82 0x83 0x84 0x85 0x86 0x87 0x88 0x89 0x8A 0x8B 0x8C 0x8D 0x8E 0x8F )(list 0x200 0x204 0x208 0x20C 0x210 0x214 0x218 0x21C 0x220 0x224 0x228 0x22C 0x230 0x234 0x238 0x23C ) group.long ($2+0x1C00)++0x3 line.long 0x0 "REGG7_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x90 0x91 0x92 0x93 0x94 0x95 0x96 0x97 0x98 0x99 0x9A 0x9B 0x9C 0x9D 0x9E 0x9F )(list 0x240 0x244 0x248 0x24C 0x250 0x254 0x258 0x25C 0x260 0x264 0x268 0x26C 0x270 0x274 0x278 0x27C ) group.long ($2+0x1C00)++0x3 line.long 0x0 "REGG7_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xA0 0xA1 0xA2 0xA3 0xA4 0xA5 0xA6 0xA7 0xA8 0xA9 0xAA 0xAB 0xAC 0xAD 0xAE 0xAF )(list 0x280 0x284 0x288 0x28C 0x290 0x294 0x298 0x29C 0x2A0 0x2A4 0x2A8 0x2AC 0x2B0 0x2B4 0x2B8 0x2BC ) group.long ($2+0x1C00)++0x3 line.long 0x0 "REGG7_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xB0 0xB1 0xB2 0xB3 0xB4 0xB5 0xB6 0xB7 0xB8 0xB9 0xBA 0xBB 0xBC 0xBD 0xBE 0xBF )(list 0x2C0 0x2C4 0x2C8 0x2CC 0x2D0 0x2D4 0x2D8 0x2DC 0x2E0 0x2E4 0x2E8 0x2EC 0x2F0 0x2F4 0x2F8 0x2FC ) group.long ($2+0x1C00)++0x3 line.long 0x0 "REGG7_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xC0 0xC1 0xC2 0xC3 0xC4 0xC5 0xC6 0xC7 0xC8 0xC9 0xCA 0xCB 0xCC 0xCD 0xCE 0xCF )(list 0x300 0x304 0x308 0x30C 0x310 0x314 0x318 0x31C 0x320 0x324 0x328 0x32C 0x330 0x334 0x338 0x33C ) group.long ($2+0x1C00)++0x3 line.long 0x0 "REGG7_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xD0 0xD1 0xD2 0xD3 0xD4 0xD5 0xD6 0xD7 0xD8 0xD9 0xDA 0xDB 0xDC 0xDD 0xDE 0xDF )(list 0x340 0x344 0x348 0x34C 0x350 0x354 0x358 0x35C 0x360 0x364 0x368 0x36C 0x370 0x374 0x378 0x37C ) group.long ($2+0x1C00)++0x3 line.long 0x0 "REGG7_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xE0 0xE1 0xE2 0xE3 0xE4 0xE5 0xE6 0xE7 0xE8 0xE9 0xEA 0xEB 0xEC 0xED 0xEE 0xEF )(list 0x380 0x384 0x388 0x38C 0x390 0x394 0x398 0x39C 0x3A0 0x3A4 0x3A8 0x3AC 0x3B0 0x3B4 0x3B8 0x3BC ) group.long ($2+0x1C00)++0x3 line.long 0x0 "REGG7_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xF0 0xF1 0xF2 0xF3 0xF4 0xF5 0xF6 0xF7 0xF8 0xF9 0xFA 0xFB 0xFC 0xFD 0xFE 0xFF )(list 0x3C0 0x3C4 0x3C8 0x3CC 0x3D0 0x3D4 0x3D8 0x3DC 0x3E0 0x3E4 0x3E8 0x3EC 0x3F0 0x3F4 0x3F8 0x3FC ) group.long ($2+0x1C00)++0x3 line.long 0x0 "REGG7_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end group.long 0x2000++0x17 line.long 0x0 "GLB_CTL,This register provides global enable settings for permission control." bitfld.long 0x0 5. "DOM_CFG_LOCK,Lock write for DOM_CFG_MODE bit." "0,1" bitfld.long 0x0 4. "DOM_CFG_MODE,When enabled all the source setting can be configured by master from domain 0 if it is not locked. When disabled only resource manager can configure the permission of the resource." "0,1" bitfld.long 0x0 3. "PERCK_DIS_LOCK,Lock write for PERCK_DIS" "0,1" bitfld.long 0x0 2. "PERCK_DIS,All the permission check disable." "0,1" newline bitfld.long 0x0 1. "DOM_PRO_LOCK,Lock write for DOM_PRO_EN bit." "0,1" bitfld.long 0x0 0. "DOM_PRO_EN,When disabled no domain access permission check" "0,1" line.long 0x4 "RES_MGR,Resource manager register. This regster is used to assign resource manager for global resource access control" bitfld.long 0x4 17. "MID_LOCK,Lock write for MID_EN and MID_LOW and MID_HIG registers." "0,1" bitfld.long 0x4 16. "MID_EN,Master ID check enable" "0,1" bitfld.long 0x4 15. "PRI_PER_LOCK,Lock write for PRI_PER and PRI_PER_EN" "0,1" bitfld.long 0x4 13.--14. "PRI_PER,Resource manager privileged access permission. bit0 for privileged access bit1 for user access" "0,1,2,3" newline bitfld.long 0x4 12. "PRI_PER_EN,Resource manager privileged access permission enable." "0,1" bitfld.long 0x4 11. "SEC_PER_LOCK,Lock for SEC_PER and SEC_PER_LOCK" "0,1" bitfld.long 0x4 9.--10. "SEC_PER,Resource manager secure access permission. bit 0 for secure access bit 1 for non-secure access" "0,1,2,3" bitfld.long 0x4 8. "SEC_PER_EN,Resource manager secure permission enable" "0,1" bitfld.long 0x4 7. "DID_LOCK,Lock write for DID_EN and DID" "0,1" newline hexmask.long.byte 0x4 3.--6. 1. "DID,Resource manager domain ID" bitfld.long 0x4 2. "DID_EN,Resource manager Domain ID enable" "0,1" bitfld.long 0x4 1. "RES_MGR_EN_LOCK,Lock for RES_MGR_EN" "0,1" bitfld.long 0x4 0. "RES_MGR_EN,Resource manager enable. When the bit is disable there is no resource manager." "0,1" line.long 0x8 "RES_MGR_MA0,This register is used to assign master 0~31 as resource manager." hexmask.long 0x8 0.--31. 1. "MID,Assign master 0~31 for resource manager" line.long 0xC "RES_MGR_MA1,This register is used to assign master 32~63 as resource manager." hexmask.long 0xC 0.--31. 1. "MID,Indicate if master 32~63 is resource manager." line.long 0x10 "RES_MGR_MA2,This register is used to assign master 64~95 as resource manager." hexmask.long 0x10 0.--31. 1. "MID,Indicate if master 64~95 is resource manager." line.long 0x14 "RES_MGR_MA3,This register is used to assign master 96~127 as resource manager." hexmask.long 0x14 0.--31. 1. "MID,Indicate if master 96~127 is resource manager." repeat 8. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 )(list 0x0 0x14 0x28 0x3C 0x50 0x64 0x78 0x8C ) group.long ($2+0x2100)++0x3 line.long 0x0 "GRP_MGR_$1,Group Manager Register. This register is used to assign group manager for each domain" bitfld.long 0x0 17. "MID_LOCK,Lock write for MID_EN and MID_LOW and MID_HIG registers." "0,1" bitfld.long 0x0 16. "MID_EN,Master ID check enable" "0,1" bitfld.long 0x0 15. "PRI_PER_LOCK,Lock write for PRI_PER and PRI_PER_EN" "0,1" bitfld.long 0x0 13.--14. "PRI_PER,Group manager privileged access permission. bit0 for privileged access bit1 for user access" "0,1,2,3" newline bitfld.long 0x0 12. "PRI_PER_EN,Group manager privileged access permission enable." "0,1" bitfld.long 0x0 11. "SEC_PER_LOCK,Lock for SEC_PER and SEC_PER_LOCK" "0,1" bitfld.long 0x0 9.--10. "SEC_PER,Group manager secure access permission. bit 0 for secure access bit 1 for non-secure access" "0,1,2,3" bitfld.long 0x0 8. "SEC_PER_EN,Group manager secure permission enable" "0,1" bitfld.long 0x0 7. "DID_LOCK,Lock write for DID_EN and DID" "0,1" newline hexmask.long.byte 0x0 3.--6. 1. "DID,Group manager domain ID" bitfld.long 0x0 2. "DID_EN,Group manager Domain ID enable" "0,1" bitfld.long 0x0 1. "GRP_MGR_EN_LOCK,Lock write for GPR_MGR_EN" "0,1" bitfld.long 0x0 0. "GRP_MGR_EN,Group manager enable. When the bit is disable there is no resource manager." "0,1" repeat.end repeat 8. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 )(list 0x0 0x14 0x28 0x3C 0x50 0x64 0x78 0x8C ) group.long ($2+0x2104)++0x3 line.long 0x0 "GRP_MGR_MA0_$1,Assign master 0~31 for group manager 0" hexmask.long 0x0 0.--31. 1. "MID,Assign master 0~31 for resource manager" repeat.end repeat 8. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 )(list 0x0 0x14 0x28 0x3C 0x50 0x64 0x78 0x8C ) group.long ($2+0x2108)++0x3 line.long 0x0 "GRP_MGR_MA1_$1,Assign master 32~63 for group manager 0" hexmask.long 0x0 0.--31. 1. "MID,Indicate if master 32~63 is resource manager." repeat.end repeat 8. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 )(list 0x0 0x14 0x28 0x3C 0x50 0x64 0x78 0x8C ) group.long ($2+0x210C)++0x3 line.long 0x0 "GRP_MGR_MA2_$1,Assign master 64~95 for group manager 0" hexmask.long 0x0 0.--31. 1. "MID,Indicate if master 64~95 is resource manager." repeat.end repeat 8. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 )(list 0x0 0x14 0x28 0x3C 0x50 0x64 0x78 0x8C ) group.long ($2+0x2110)++0x3 line.long 0x0 "GRP_MGR_MA3_$1,Assign master 96~127 for group manager 0" hexmask.long 0x0 0.--31. 1. "MID,Indicate if master 96~127 is resource manager." repeat.end group.long 0x2200++0x3 line.long 0x0 "DOM_GID_0,Indicate which group domain 0 belong to" bitfld.long 0x0 3. "LOCK,Lock write for GID" "0,1" bitfld.long 0x0 0.--2. "GID,Group ID" "0,1,2,3,4,5,6,7" repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x18 0x30 0x48 0x60 0x78 0x90 0xA8 0xC0 0xD8 0xF0 0x108 0x120 0x138 0x150 0x168 ) group.long ($2+0x2204)++0x3 line.long 0x0 "DOM_OWN_$1,Assign owner for function domain 0." bitfld.long 0x0 17. "MID_LOCK,Lock write for MID_EN and MID_LOW and MID_HIG registers." "0,1" bitfld.long 0x0 16. "MID_EN,Master ID check enable" "0,1" bitfld.long 0x0 15. "PRI_PER_LOCK,Lock write for PRI_PER and PRI_PER_EN" "0,1" bitfld.long 0x0 13.--14. "PRI_PER,Group manager privileged access permission. bit0 for privileged access bit1 for user access" "0,1,2,3" newline bitfld.long 0x0 12. "PRI_PER_EN,Group manager privileged access permission enable." "0,1" bitfld.long 0x0 11. "SEC_PER_LOCK,Lock for SEC_PER and SEC_PER_LOCK" "0,1" bitfld.long 0x0 9.--10. "SEC_PER,Domain owner secure access permission. bit 0 for secure access bit 1 for non-secure access" "0,1,2,3" bitfld.long 0x0 8. "SEC_PER_EN,Domain owner secure permission enable" "0,1" newline bitfld.long 0x0 1. "DOM_OWN_EN_LOCK,Lock for DOM_OWN_EN" "0,1" bitfld.long 0x0 0. "DOM_OWN_EN,Domain owner enable. When the bit is disable there is no domain owner." "0,1" repeat.end repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x18 0x30 0x48 0x60 0x78 0x90 0xA8 0xC0 0xD8 0xF0 0x108 0x120 0x138 0x150 0x168 ) group.long ($2+0x2208)++0x3 line.long 0x0 "DOM_OWN_MA0_$1,Assign master 0~31 for domain owner 0" hexmask.long 0x0 0.--31. 1. "MID,Assign master 0~31 for resource manager" repeat.end repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x18 0x30 0x48 0x60 0x78 0x90 0xA8 0xC0 0xD8 0xF0 0x108 0x120 0x138 0x150 0x168 ) group.long ($2+0x220C)++0x3 line.long 0x0 "DOM_OWN_MA1_$1,Assign master 32~63 for domain owner 0" hexmask.long 0x0 0.--31. 1. "MID,Indicate if master 32~63 is resource manager." repeat.end repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x18 0x30 0x48 0x60 0x78 0x90 0xA8 0xC0 0xD8 0xF0 0x108 0x120 0x138 0x150 0x168 ) group.long ($2+0x2210)++0x3 line.long 0x0 "DOM_OWN_MA2_$1,Assign master 64~95 for domain owner 0" hexmask.long 0x0 0.--31. 1. "MID,Indicate if master 64~95 is resource manager." repeat.end repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x18 0x30 0x48 0x60 0x78 0x90 0xA8 0xC0 0xD8 0xF0 0x108 0x120 0x138 0x150 0x168 ) group.long ($2+0x2214)++0x3 line.long 0x0 "DOM_OWN_MA3_$1,Assign master 96~127 for domain owner 0" hexmask.long 0x0 0.--31. 1. "MID,Indicate if master 96~127 is resource manager." repeat.end group.long 0x2218++0x3 line.long 0x0 "DOM_GID_1,Indicate which group domain 1 belong to" bitfld.long 0x0 3. "LOCK,Lock write for GID" "0,1" bitfld.long 0x0 0.--2. "GID,Group ID" "0,1,2,3,4,5,6,7" group.long 0x2230++0x3 line.long 0x0 "DOM_GID_2,Indicate which group domain 2 belong to" bitfld.long 0x0 3. "LOCK,Lock write for GID" "0,1" bitfld.long 0x0 0.--2. "GID,Group ID" "0,1,2,3,4,5,6,7" group.long 0x2248++0x3 line.long 0x0 "DOM_GID_3,Indicate which group domain 3 belong to" bitfld.long 0x0 3. "LOCK,Lock write for GID" "0,1" bitfld.long 0x0 0.--2. "GID,Group ID" "0,1,2,3,4,5,6,7" group.long 0x2260++0x3 line.long 0x0 "DOM_GID_4,Indicate which group domain 4 belong to" bitfld.long 0x0 3. "LOCK,Lock write for GID" "0,1" bitfld.long 0x0 0.--2. "GID,Group ID" "0,1,2,3,4,5,6,7" group.long 0x2278++0x3 line.long 0x0 "DOM_GID_5,Indicate which group domain 5 belong to" bitfld.long 0x0 3. "LOCK,Lock write for GID" "0,1" bitfld.long 0x0 0.--2. "GID,Group ID" "0,1,2,3,4,5,6,7" group.long 0x2290++0x3 line.long 0x0 "DOM_GID_6,Indicate which group domain 6 belong to" bitfld.long 0x0 3. "LOCK,Lock write for GID" "0,1" bitfld.long 0x0 0.--2. "GID,Group ID" "0,1,2,3,4,5,6,7" group.long 0x22A8++0x3 line.long 0x0 "DOM_GID_7,Indicate which group domain 7 belong to" bitfld.long 0x0 3. "LOCK,Lock write for GID" "0,1" bitfld.long 0x0 0.--2. "GID,Group ID" "0,1,2,3,4,5,6,7" group.long 0x22C0++0x3 line.long 0x0 "DOM_GID_8,Indicate which group domain 8 belong to" bitfld.long 0x0 3. "LOCK,Lock write for GID" "0,1" bitfld.long 0x0 0.--2. "GID,Group ID" "0,1,2,3,4,5,6,7" group.long 0x22D8++0x3 line.long 0x0 "DOM_GID_9,Indicate which group domain 9 belong to" bitfld.long 0x0 3. "LOCK,Lock write for GID" "0,1" bitfld.long 0x0 0.--2. "GID,Group ID" "0,1,2,3,4,5,6,7" group.long 0x22F0++0x3 line.long 0x0 "DOM_GID_10,Indicate which group domain 10 belong to" bitfld.long 0x0 3. "LOCK,Lock write for GID" "0,1" bitfld.long 0x0 0.--2. "GID,Group ID" "0,1,2,3,4,5,6,7" group.long 0x2308++0x3 line.long 0x0 "DOM_GID_11,Indicate which group domain 11 belong to" bitfld.long 0x0 3. "LOCK,Lock write for GID" "0,1" bitfld.long 0x0 0.--2. "GID,Group ID" "0,1,2,3,4,5,6,7" group.long 0x2320++0x3 line.long 0x0 "DOM_GID_12,Indicate which group domain 12 belong to" bitfld.long 0x0 3. "LOCK,Lock write for GID" "0,1" bitfld.long 0x0 0.--2. "GID,Group ID" "0,1,2,3,4,5,6,7" group.long 0x2338++0x3 line.long 0x0 "DOM_GID_13,Indicate which group domain 13 belong to" bitfld.long 0x0 3. "LOCK,Lock write for GID" "0,1" bitfld.long 0x0 0.--2. "GID,Group ID" "0,1,2,3,4,5,6,7" group.long 0x2350++0x3 line.long 0x0 "DOM_GID_14,Indicate which group domain 14 belong to" bitfld.long 0x0 3. "LOCK,Lock write for GID" "0,1" bitfld.long 0x0 0.--2. "GID,Group ID" "0,1,2,3,4,5,6,7" group.long 0x2368++0x3 line.long 0x0 "DOM_GID_15,Indicate which group domain 15 belong to" bitfld.long 0x0 3. "LOCK,Lock write for GID" "0,1" bitfld.long 0x0 0.--2. "GID,Group ID" "0,1,2,3,4,5,6,7" repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x34 0x68 0x9C 0xD0 0x104 0x138 0x16C 0x1A0 0x1D4 0x208 0x23C 0x270 0x2A4 0x2D8 0x30C ) group.long ($2+0x2400)++0x3 line.long 0x0 "DOM_PER0_$1,Domain Permission Control. It can be only configured by resource manager and domain owner." bitfld.long 0x0 31. "DOM7_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 29.--30. "DOM7_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 28. "DOM7_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 27. "DOM6_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 25.--26. "DOM6_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" newline bitfld.long 0x0 24. "DOM6_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 23. "DOM5_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 21.--22. "DOM5_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 20. "DOM5_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 19. "DOM4_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" newline bitfld.long 0x0 17.--18. "DOM4_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM4_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 15. "DOM3_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 13.--14. "DOM3_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 12. "DOM3_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" newline bitfld.long 0x0 11. "DOM2_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 9.--10. "DOM2_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM2_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 7. "DOM1_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 5.--6. "DOM1_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" newline bitfld.long 0x0 4. "DOM1_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 3. "DOM0_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 1.--2. "DOM0_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM0_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" repeat.end repeat 16. (list 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1A 0x1B 0x1C 0x1D 0x1E 0x1F )(list 0x340 0x374 0x3A8 0x3DC 0x410 0x444 0x478 0x4AC 0x4E0 0x514 0x548 0x57C 0x5B0 0x5E4 0x618 0x64C ) group.long ($2+0x2400)++0x3 line.long 0x0 "DOM_PER0_$1,Domain Permission Control. It can be only configured by resource manager and domain owner." bitfld.long 0x0 31. "DOM7_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 29.--30. "DOM7_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 28. "DOM7_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 27. "DOM6_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 25.--26. "DOM6_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" newline bitfld.long 0x0 24. "DOM6_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 23. "DOM5_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 21.--22. "DOM5_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 20. "DOM5_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 19. "DOM4_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" newline bitfld.long 0x0 17.--18. "DOM4_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM4_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 15. "DOM3_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 13.--14. "DOM3_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 12. "DOM3_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" newline bitfld.long 0x0 11. "DOM2_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 9.--10. "DOM2_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM2_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 7. "DOM1_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 5.--6. "DOM1_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" newline bitfld.long 0x0 4. "DOM1_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 3. "DOM0_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 1.--2. "DOM0_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM0_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" repeat.end repeat 16. (list 0x20 0x21 0x22 0x23 0x24 0x25 0x26 0x27 0x28 0x29 0x2A 0x2B 0x2C 0x2D 0x2E 0x2F )(list 0x680 0x6B4 0x6E8 0x71C 0x750 0x784 0x7B8 0x7EC 0x820 0x854 0x888 0x8BC 0x8F0 0x924 0x958 0x98C ) group.long ($2+0x2400)++0x3 line.long 0x0 "DOM_PER0_$1,Domain Permission Control. It can be only configured by resource manager and domain owner." bitfld.long 0x0 31. "DOM7_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 29.--30. "DOM7_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 28. "DOM7_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 27. "DOM6_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 25.--26. "DOM6_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" newline bitfld.long 0x0 24. "DOM6_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 23. "DOM5_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 21.--22. "DOM5_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 20. "DOM5_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 19. "DOM4_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" newline bitfld.long 0x0 17.--18. "DOM4_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM4_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 15. "DOM3_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 13.--14. "DOM3_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 12. "DOM3_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" newline bitfld.long 0x0 11. "DOM2_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 9.--10. "DOM2_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM2_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 7. "DOM1_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 5.--6. "DOM1_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" newline bitfld.long 0x0 4. "DOM1_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 3. "DOM0_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 1.--2. "DOM0_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM0_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" repeat.end repeat 16. (list 0x30 0x31 0x32 0x33 0x34 0x35 0x36 0x37 0x38 0x39 0x3A 0x3B 0x3C 0x3D 0x3E 0x3F )(list 0x9C0 0x9F4 0xA28 0xA5C 0xA90 0xAC4 0xAF8 0xB2C 0xB60 0xB94 0xBC8 0xBFC 0xC30 0xC64 0xC98 0xCCC ) group.long ($2+0x2400)++0x3 line.long 0x0 "DOM_PER0_$1,Domain Permission Control. It can be only configured by resource manager and domain owner." bitfld.long 0x0 31. "DOM7_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 29.--30. "DOM7_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 28. "DOM7_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 27. "DOM6_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 25.--26. "DOM6_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" newline bitfld.long 0x0 24. "DOM6_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 23. "DOM5_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 21.--22. "DOM5_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 20. "DOM5_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 19. "DOM4_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" newline bitfld.long 0x0 17.--18. "DOM4_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM4_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 15. "DOM3_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 13.--14. "DOM3_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 12. "DOM3_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" newline bitfld.long 0x0 11. "DOM2_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 9.--10. "DOM2_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM2_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 7. "DOM1_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 5.--6. "DOM1_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" newline bitfld.long 0x0 4. "DOM1_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 3. "DOM0_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 1.--2. "DOM0_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM0_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" repeat.end repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x34 0x68 0x9C 0xD0 0x104 0x138 0x16C 0x1A0 0x1D4 0x208 0x23C 0x270 0x2A4 0x2D8 0x30C ) group.long ($2+0x2404)++0x3 line.long 0x0 "DOM_PER1_$1,Domain Permission Control. It can be only configured by resource manager and domain owner." bitfld.long 0x0 31. "DOM15_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 29.--30. "DOM15_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 28. "DOM15_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 27. "DOM14_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 25.--26. "DOM14_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" newline bitfld.long 0x0 24. "DOM14_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 23. "DOM13_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 21.--22. "DOM13_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 20. "DOM13_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 19. "DOM12_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" newline bitfld.long 0x0 17.--18. "DOM12_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM12_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 15. "DOM11_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 13.--14. "DOM11_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 12. "DOM11_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" newline bitfld.long 0x0 11. "DOM10_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 9.--10. "DOM10_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM10_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 7. "DOM9_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 5.--6. "DOM9_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" newline bitfld.long 0x0 4. "DOM9_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 3. "DOM8_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 1.--2. "DOM8_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM8_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" repeat.end repeat 16. (list 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1A 0x1B 0x1C 0x1D 0x1E 0x1F )(list 0x340 0x374 0x3A8 0x3DC 0x410 0x444 0x478 0x4AC 0x4E0 0x514 0x548 0x57C 0x5B0 0x5E4 0x618 0x64C ) group.long ($2+0x2404)++0x3 line.long 0x0 "DOM_PER1_$1,Domain Permission Control. It can be only configured by resource manager and domain owner." bitfld.long 0x0 31. "DOM15_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 29.--30. "DOM15_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 28. "DOM15_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 27. "DOM14_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 25.--26. "DOM14_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" newline bitfld.long 0x0 24. "DOM14_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 23. "DOM13_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 21.--22. "DOM13_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 20. "DOM13_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 19. "DOM12_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" newline bitfld.long 0x0 17.--18. "DOM12_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM12_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 15. "DOM11_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 13.--14. "DOM11_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 12. "DOM11_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" newline bitfld.long 0x0 11. "DOM10_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 9.--10. "DOM10_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM10_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 7. "DOM9_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 5.--6. "DOM9_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" newline bitfld.long 0x0 4. "DOM9_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 3. "DOM8_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 1.--2. "DOM8_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM8_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" repeat.end repeat 16. (list 0x20 0x21 0x22 0x23 0x24 0x25 0x26 0x27 0x28 0x29 0x2A 0x2B 0x2C 0x2D 0x2E 0x2F )(list 0x680 0x6B4 0x6E8 0x71C 0x750 0x784 0x7B8 0x7EC 0x820 0x854 0x888 0x8BC 0x8F0 0x924 0x958 0x98C ) group.long ($2+0x2404)++0x3 line.long 0x0 "DOM_PER1_$1,Domain Permission Control. It can be only configured by resource manager and domain owner." bitfld.long 0x0 31. "DOM15_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 29.--30. "DOM15_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 28. "DOM15_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 27. "DOM14_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 25.--26. "DOM14_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" newline bitfld.long 0x0 24. "DOM14_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 23. "DOM13_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 21.--22. "DOM13_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 20. "DOM13_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 19. "DOM12_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" newline bitfld.long 0x0 17.--18. "DOM12_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM12_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 15. "DOM11_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 13.--14. "DOM11_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 12. "DOM11_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" newline bitfld.long 0x0 11. "DOM10_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 9.--10. "DOM10_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM10_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 7. "DOM9_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 5.--6. "DOM9_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" newline bitfld.long 0x0 4. "DOM9_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 3. "DOM8_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 1.--2. "DOM8_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM8_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" repeat.end repeat 16. (list 0x30 0x31 0x32 0x33 0x34 0x35 0x36 0x37 0x38 0x39 0x3A 0x3B 0x3C 0x3D 0x3E 0x3F )(list 0x9C0 0x9F4 0xA28 0xA5C 0xA90 0xAC4 0xAF8 0xB2C 0xB60 0xB94 0xBC8 0xBFC 0xC30 0xC64 0xC98 0xCCC ) group.long ($2+0x2404)++0x3 line.long 0x0 "DOM_PER1_$1,Domain Permission Control. It can be only configured by resource manager and domain owner." bitfld.long 0x0 31. "DOM15_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 29.--30. "DOM15_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 28. "DOM15_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 27. "DOM14_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 25.--26. "DOM14_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" newline bitfld.long 0x0 24. "DOM14_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 23. "DOM13_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 21.--22. "DOM13_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 20. "DOM13_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 19. "DOM12_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" newline bitfld.long 0x0 17.--18. "DOM12_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM12_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 15. "DOM11_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 13.--14. "DOM11_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 12. "DOM11_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" newline bitfld.long 0x0 11. "DOM10_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 9.--10. "DOM10_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM10_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 7. "DOM9_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 5.--6. "DOM9_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" newline bitfld.long 0x0 4. "DOM9_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 3. "DOM8_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 1.--2. "DOM8_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM8_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" repeat.end repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x34 0x68 0x9C 0xD0 0x104 0x138 0x16C 0x1A0 0x1D4 0x208 0x23C 0x270 0x2A4 0x2D8 0x30C ) group.long ($2+0x2408)++0x3 line.long 0x0 "SEC_PER0_$1,This register is only used for resource manager to control secure access permission." bitfld.long 0x0 31. "DOM3_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM3_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM3_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM3_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM2_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM2_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM2_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM2_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM1_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM1_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM1_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM1_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM0_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM0_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM0_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM0_SEC_EN,Domain secure permission control enable" "0,1" repeat.end repeat 16. (list 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1A 0x1B 0x1C 0x1D 0x1E 0x1F )(list 0x340 0x374 0x3A8 0x3DC 0x410 0x444 0x478 0x4AC 0x4E0 0x514 0x548 0x57C 0x5B0 0x5E4 0x618 0x64C ) group.long ($2+0x2408)++0x3 line.long 0x0 "SEC_PER0_$1,This register is only used for resource manager to control secure access permission." bitfld.long 0x0 31. "DOM3_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM3_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM3_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM3_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM2_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM2_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM2_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM2_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM1_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM1_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM1_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM1_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM0_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM0_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM0_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM0_SEC_EN,Domain secure permission control enable" "0,1" repeat.end repeat 16. (list 0x20 0x21 0x22 0x23 0x24 0x25 0x26 0x27 0x28 0x29 0x2A 0x2B 0x2C 0x2D 0x2E 0x2F )(list 0x680 0x6B4 0x6E8 0x71C 0x750 0x784 0x7B8 0x7EC 0x820 0x854 0x888 0x8BC 0x8F0 0x924 0x958 0x98C ) group.long ($2+0x2408)++0x3 line.long 0x0 "SEC_PER0_$1,This register is only used for resource manager to control secure access permission." bitfld.long 0x0 31. "DOM3_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM3_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM3_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM3_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM2_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM2_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM2_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM2_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM1_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM1_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM1_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM1_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM0_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM0_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM0_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM0_SEC_EN,Domain secure permission control enable" "0,1" repeat.end repeat 16. (list 0x30 0x31 0x32 0x33 0x34 0x35 0x36 0x37 0x38 0x39 0x3A 0x3B 0x3C 0x3D 0x3E 0x3F )(list 0x9C0 0x9F4 0xA28 0xA5C 0xA90 0xAC4 0xAF8 0xB2C 0xB60 0xB94 0xBC8 0xBFC 0xC30 0xC64 0xC98 0xCCC ) group.long ($2+0x2408)++0x3 line.long 0x0 "SEC_PER0_$1,This register is only used for resource manager to control secure access permission." bitfld.long 0x0 31. "DOM3_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM3_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM3_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM3_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM2_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM2_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM2_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM2_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM1_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM1_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM1_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM1_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM0_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM0_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM0_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM0_SEC_EN,Domain secure permission control enable" "0,1" repeat.end repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x34 0x68 0x9C 0xD0 0x104 0x138 0x16C 0x1A0 0x1D4 0x208 0x23C 0x270 0x2A4 0x2D8 0x30C ) group.long ($2+0x240C)++0x3 line.long 0x0 "SEC_PER1_$1,This register is only used for resource manager to control secure access permission." bitfld.long 0x0 31. "DOM7_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM7_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM7_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM7_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM6_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM6_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM6_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM6_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM5_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM5_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM5_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM5_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM4_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM4_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM4_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM4_SEC_EN,Domain secure permission control enable" "0,1" repeat.end repeat 16. (list 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1A 0x1B 0x1C 0x1D 0x1E 0x1F )(list 0x340 0x374 0x3A8 0x3DC 0x410 0x444 0x478 0x4AC 0x4E0 0x514 0x548 0x57C 0x5B0 0x5E4 0x618 0x64C ) group.long ($2+0x240C)++0x3 line.long 0x0 "SEC_PER1_$1,This register is only used for resource manager to control secure access permission." bitfld.long 0x0 31. "DOM7_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM7_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM7_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM7_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM6_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM6_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM6_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM6_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM5_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM5_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM5_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM5_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM4_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM4_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM4_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM4_SEC_EN,Domain secure permission control enable" "0,1" repeat.end repeat 16. (list 0x20 0x21 0x22 0x23 0x24 0x25 0x26 0x27 0x28 0x29 0x2A 0x2B 0x2C 0x2D 0x2E 0x2F )(list 0x680 0x6B4 0x6E8 0x71C 0x750 0x784 0x7B8 0x7EC 0x820 0x854 0x888 0x8BC 0x8F0 0x924 0x958 0x98C ) group.long ($2+0x240C)++0x3 line.long 0x0 "SEC_PER1_$1,This register is only used for resource manager to control secure access permission." bitfld.long 0x0 31. "DOM7_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM7_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM7_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM7_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM6_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM6_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM6_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM6_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM5_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM5_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM5_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM5_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM4_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM4_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM4_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM4_SEC_EN,Domain secure permission control enable" "0,1" repeat.end repeat 16. (list 0x30 0x31 0x32 0x33 0x34 0x35 0x36 0x37 0x38 0x39 0x3A 0x3B 0x3C 0x3D 0x3E 0x3F )(list 0x9C0 0x9F4 0xA28 0xA5C 0xA90 0xAC4 0xAF8 0xB2C 0xB60 0xB94 0xBC8 0xBFC 0xC30 0xC64 0xC98 0xCCC ) group.long ($2+0x240C)++0x3 line.long 0x0 "SEC_PER1_$1,This register is only used for resource manager to control secure access permission." bitfld.long 0x0 31. "DOM7_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM7_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM7_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM7_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM6_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM6_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM6_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM6_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM5_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM5_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM5_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM5_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM4_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM4_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM4_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM4_SEC_EN,Domain secure permission control enable" "0,1" repeat.end repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x34 0x68 0x9C 0xD0 0x104 0x138 0x16C 0x1A0 0x1D4 0x208 0x23C 0x270 0x2A4 0x2D8 0x30C ) group.long ($2+0x2410)++0x3 line.long 0x0 "SEC_PER2_$1,This register is only used for resource manager to control secure access permission." bitfld.long 0x0 31. "DOM11_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM11_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM11_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM11_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM10_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM10_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM10_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM10_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM9_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM9_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM9_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM9_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM8_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM8_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM8_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM8_SEC_EN,Domain secure permission control enable" "0,1" repeat.end repeat 16. (list 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1A 0x1B 0x1C 0x1D 0x1E 0x1F )(list 0x340 0x374 0x3A8 0x3DC 0x410 0x444 0x478 0x4AC 0x4E0 0x514 0x548 0x57C 0x5B0 0x5E4 0x618 0x64C ) group.long ($2+0x2410)++0x3 line.long 0x0 "SEC_PER2_$1,This register is only used for resource manager to control secure access permission." bitfld.long 0x0 31. "DOM11_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM11_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM11_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM11_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM10_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM10_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM10_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM10_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM9_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM9_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM9_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM9_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM8_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM8_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM8_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM8_SEC_EN,Domain secure permission control enable" "0,1" repeat.end repeat 16. (list 0x20 0x21 0x22 0x23 0x24 0x25 0x26 0x27 0x28 0x29 0x2A 0x2B 0x2C 0x2D 0x2E 0x2F )(list 0x680 0x6B4 0x6E8 0x71C 0x750 0x784 0x7B8 0x7EC 0x820 0x854 0x888 0x8BC 0x8F0 0x924 0x958 0x98C ) group.long ($2+0x2410)++0x3 line.long 0x0 "SEC_PER2_$1,This register is only used for resource manager to control secure access permission." bitfld.long 0x0 31. "DOM11_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM11_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM11_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM11_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM10_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM10_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM10_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM10_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM9_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM9_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM9_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM9_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM8_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM8_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM8_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM8_SEC_EN,Domain secure permission control enable" "0,1" repeat.end repeat 16. (list 0x30 0x31 0x32 0x33 0x34 0x35 0x36 0x37 0x38 0x39 0x3A 0x3B 0x3C 0x3D 0x3E 0x3F )(list 0x9C0 0x9F4 0xA28 0xA5C 0xA90 0xAC4 0xAF8 0xB2C 0xB60 0xB94 0xBC8 0xBFC 0xC30 0xC64 0xC98 0xCCC ) group.long ($2+0x2410)++0x3 line.long 0x0 "SEC_PER2_$1,This register is only used for resource manager to control secure access permission." bitfld.long 0x0 31. "DOM11_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM11_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM11_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM11_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM10_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM10_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM10_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM10_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM9_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM9_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM9_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM9_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM8_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM8_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM8_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM8_SEC_EN,Domain secure permission control enable" "0,1" repeat.end repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x34 0x68 0x9C 0xD0 0x104 0x138 0x16C 0x1A0 0x1D4 0x208 0x23C 0x270 0x2A4 0x2D8 0x30C ) group.long ($2+0x2414)++0x3 line.long 0x0 "SEC_PER3_$1,This register is only used for resource manager to control secure access permission." bitfld.long 0x0 31. "DOM15_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM15_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM15_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM15_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM14_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM14_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM14_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM14_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM13_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM13_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM13_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM13_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM12_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM12_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM12_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM12_SEC_EN,Domain secure permission control enable" "0,1" repeat.end repeat 16. (list 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1A 0x1B 0x1C 0x1D 0x1E 0x1F )(list 0x340 0x374 0x3A8 0x3DC 0x410 0x444 0x478 0x4AC 0x4E0 0x514 0x548 0x57C 0x5B0 0x5E4 0x618 0x64C ) group.long ($2+0x2414)++0x3 line.long 0x0 "SEC_PER3_$1,This register is only used for resource manager to control secure access permission." bitfld.long 0x0 31. "DOM15_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM15_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM15_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM15_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM14_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM14_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM14_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM14_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM13_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM13_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM13_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM13_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM12_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM12_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM12_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM12_SEC_EN,Domain secure permission control enable" "0,1" repeat.end repeat 16. (list 0x20 0x21 0x22 0x23 0x24 0x25 0x26 0x27 0x28 0x29 0x2A 0x2B 0x2C 0x2D 0x2E 0x2F )(list 0x680 0x6B4 0x6E8 0x71C 0x750 0x784 0x7B8 0x7EC 0x820 0x854 0x888 0x8BC 0x8F0 0x924 0x958 0x98C ) group.long ($2+0x2414)++0x3 line.long 0x0 "SEC_PER3_$1,This register is only used for resource manager to control secure access permission." bitfld.long 0x0 31. "DOM15_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM15_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM15_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM15_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM14_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM14_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM14_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM14_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM13_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM13_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM13_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM13_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM12_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM12_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM12_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM12_SEC_EN,Domain secure permission control enable" "0,1" repeat.end repeat 16. (list 0x30 0x31 0x32 0x33 0x34 0x35 0x36 0x37 0x38 0x39 0x3A 0x3B 0x3C 0x3D 0x3E 0x3F )(list 0x9C0 0x9F4 0xA28 0xA5C 0xA90 0xAC4 0xAF8 0xB2C 0xB60 0xB94 0xBC8 0xBFC 0xC30 0xC64 0xC98 0xCCC ) group.long ($2+0x2414)++0x3 line.long 0x0 "SEC_PER3_$1,This register is only used for resource manager to control secure access permission." bitfld.long 0x0 31. "DOM15_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM15_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM15_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM15_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM14_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM14_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM14_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM14_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM13_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM13_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM13_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM13_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM12_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM12_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM12_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM12_SEC_EN,Domain secure permission control enable" "0,1" repeat.end repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x34 0x68 0x9C 0xD0 0x104 0x138 0x16C 0x1A0 0x1D4 0x208 0x23C 0x270 0x2A4 0x2D8 0x30C ) group.long ($2+0x2418)++0x3 line.long 0x0 "PRI_PER0_$1,This register is only used for resource manager to control privileged access permission." bitfld.long 0x0 31. "DOM3_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM3_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM3_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM3_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM2_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM2_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM2_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM2_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM1_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM1_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM1_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM1_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM0_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM0_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM0_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM0_PRI_EN,Domain privileged permission control enable" "0,1" repeat.end repeat 16. (list 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1A 0x1B 0x1C 0x1D 0x1E 0x1F )(list 0x340 0x374 0x3A8 0x3DC 0x410 0x444 0x478 0x4AC 0x4E0 0x514 0x548 0x57C 0x5B0 0x5E4 0x618 0x64C ) group.long ($2+0x2418)++0x3 line.long 0x0 "PRI_PER0_$1,This register is only used for resource manager to control privileged access permission." bitfld.long 0x0 31. "DOM3_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM3_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM3_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM3_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM2_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM2_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM2_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM2_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM1_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM1_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM1_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM1_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM0_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM0_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM0_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM0_PRI_EN,Domain privileged permission control enable" "0,1" repeat.end repeat 16. (list 0x20 0x21 0x22 0x23 0x24 0x25 0x26 0x27 0x28 0x29 0x2A 0x2B 0x2C 0x2D 0x2E 0x2F )(list 0x680 0x6B4 0x6E8 0x71C 0x750 0x784 0x7B8 0x7EC 0x820 0x854 0x888 0x8BC 0x8F0 0x924 0x958 0x98C ) group.long ($2+0x2418)++0x3 line.long 0x0 "PRI_PER0_$1,This register is only used for resource manager to control privileged access permission." bitfld.long 0x0 31. "DOM3_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM3_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM3_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM3_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM2_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM2_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM2_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM2_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM1_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM1_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM1_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM1_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM0_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM0_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM0_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM0_PRI_EN,Domain privileged permission control enable" "0,1" repeat.end repeat 16. (list 0x30 0x31 0x32 0x33 0x34 0x35 0x36 0x37 0x38 0x39 0x3A 0x3B 0x3C 0x3D 0x3E 0x3F )(list 0x9C0 0x9F4 0xA28 0xA5C 0xA90 0xAC4 0xAF8 0xB2C 0xB60 0xB94 0xBC8 0xBFC 0xC30 0xC64 0xC98 0xCCC ) group.long ($2+0x2418)++0x3 line.long 0x0 "PRI_PER0_$1,This register is only used for resource manager to control privileged access permission." bitfld.long 0x0 31. "DOM3_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM3_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM3_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM3_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM2_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM2_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM2_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM2_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM1_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM1_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM1_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM1_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM0_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM0_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM0_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM0_PRI_EN,Domain privileged permission control enable" "0,1" repeat.end repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x34 0x68 0x9C 0xD0 0x104 0x138 0x16C 0x1A0 0x1D4 0x208 0x23C 0x270 0x2A4 0x2D8 0x30C ) group.long ($2+0x241C)++0x3 line.long 0x0 "PRI_PER1_$1,This register is only used for resource manager to control privileged access permission." bitfld.long 0x0 31. "DOM7_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM7_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM7_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM7_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM6_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM6_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM6_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM6_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM5_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM5_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM5_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM5_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM4_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM4_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM4_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM4_PRI_EN,Domain privileged permission control enable" "0,1" repeat.end repeat 16. (list 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1A 0x1B 0x1C 0x1D 0x1E 0x1F )(list 0x340 0x374 0x3A8 0x3DC 0x410 0x444 0x478 0x4AC 0x4E0 0x514 0x548 0x57C 0x5B0 0x5E4 0x618 0x64C ) group.long ($2+0x241C)++0x3 line.long 0x0 "PRI_PER1_$1,This register is only used for resource manager to control privileged access permission." bitfld.long 0x0 31. "DOM7_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM7_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM7_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM7_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM6_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM6_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM6_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM6_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM5_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM5_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM5_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM5_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM4_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM4_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM4_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM4_PRI_EN,Domain privileged permission control enable" "0,1" repeat.end repeat 16. (list 0x20 0x21 0x22 0x23 0x24 0x25 0x26 0x27 0x28 0x29 0x2A 0x2B 0x2C 0x2D 0x2E 0x2F )(list 0x680 0x6B4 0x6E8 0x71C 0x750 0x784 0x7B8 0x7EC 0x820 0x854 0x888 0x8BC 0x8F0 0x924 0x958 0x98C ) group.long ($2+0x241C)++0x3 line.long 0x0 "PRI_PER1_$1,This register is only used for resource manager to control privileged access permission." bitfld.long 0x0 31. "DOM7_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM7_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM7_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM7_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM6_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM6_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM6_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM6_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM5_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM5_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM5_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM5_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM4_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM4_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM4_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM4_PRI_EN,Domain privileged permission control enable" "0,1" repeat.end repeat 16. (list 0x30 0x31 0x32 0x33 0x34 0x35 0x36 0x37 0x38 0x39 0x3A 0x3B 0x3C 0x3D 0x3E 0x3F )(list 0x9C0 0x9F4 0xA28 0xA5C 0xA90 0xAC4 0xAF8 0xB2C 0xB60 0xB94 0xBC8 0xBFC 0xC30 0xC64 0xC98 0xCCC ) group.long ($2+0x241C)++0x3 line.long 0x0 "PRI_PER1_$1,This register is only used for resource manager to control privileged access permission." bitfld.long 0x0 31. "DOM7_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM7_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM7_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM7_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM6_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM6_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM6_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM6_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM5_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM5_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM5_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM5_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM4_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM4_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM4_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM4_PRI_EN,Domain privileged permission control enable" "0,1" repeat.end repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x34 0x68 0x9C 0xD0 0x104 0x138 0x16C 0x1A0 0x1D4 0x208 0x23C 0x270 0x2A4 0x2D8 0x30C ) group.long ($2+0x2420)++0x3 line.long 0x0 "PRI_PER2_$1,This register is only used for resource manager to control privileged access permission." bitfld.long 0x0 31. "DOM11_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM11_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM11_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM11_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM10_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM10_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM10_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM10_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM9_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM9_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM9_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM9_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM8_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM8_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM8_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM8_PRI_EN,Domain privileged permission control enable" "0,1" repeat.end repeat 16. (list 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1A 0x1B 0x1C 0x1D 0x1E 0x1F )(list 0x340 0x374 0x3A8 0x3DC 0x410 0x444 0x478 0x4AC 0x4E0 0x514 0x548 0x57C 0x5B0 0x5E4 0x618 0x64C ) group.long ($2+0x2420)++0x3 line.long 0x0 "PRI_PER2_$1,This register is only used for resource manager to control privileged access permission." bitfld.long 0x0 31. "DOM11_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM11_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM11_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM11_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM10_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM10_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM10_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM10_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM9_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM9_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM9_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM9_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM8_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM8_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM8_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM8_PRI_EN,Domain privileged permission control enable" "0,1" repeat.end repeat 16. (list 0x20 0x21 0x22 0x23 0x24 0x25 0x26 0x27 0x28 0x29 0x2A 0x2B 0x2C 0x2D 0x2E 0x2F )(list 0x680 0x6B4 0x6E8 0x71C 0x750 0x784 0x7B8 0x7EC 0x820 0x854 0x888 0x8BC 0x8F0 0x924 0x958 0x98C ) group.long ($2+0x2420)++0x3 line.long 0x0 "PRI_PER2_$1,This register is only used for resource manager to control privileged access permission." bitfld.long 0x0 31. "DOM11_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM11_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM11_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM11_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM10_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM10_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM10_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM10_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM9_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM9_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM9_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM9_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM8_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM8_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM8_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM8_PRI_EN,Domain privileged permission control enable" "0,1" repeat.end repeat 16. (list 0x30 0x31 0x32 0x33 0x34 0x35 0x36 0x37 0x38 0x39 0x3A 0x3B 0x3C 0x3D 0x3E 0x3F )(list 0x9C0 0x9F4 0xA28 0xA5C 0xA90 0xAC4 0xAF8 0xB2C 0xB60 0xB94 0xBC8 0xBFC 0xC30 0xC64 0xC98 0xCCC ) group.long ($2+0x2420)++0x3 line.long 0x0 "PRI_PER2_$1,This register is only used for resource manager to control privileged access permission." bitfld.long 0x0 31. "DOM11_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM11_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM11_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM11_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM10_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM10_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM10_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM10_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM9_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM9_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM9_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM9_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM8_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM8_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM8_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM8_PRI_EN,Domain privileged permission control enable" "0,1" repeat.end repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x34 0x68 0x9C 0xD0 0x104 0x138 0x16C 0x1A0 0x1D4 0x208 0x23C 0x270 0x2A4 0x2D8 0x30C ) group.long ($2+0x2424)++0x3 line.long 0x0 "PRI_PER3_$1,This register is only used for resource manager to control privileged access permission." bitfld.long 0x0 31. "DOM15_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM15_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM15_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM15_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM14_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM14_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM14_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM14_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM13_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM13_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM13_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM13_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM12_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM12_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM12_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM12_PRI_EN,Domain privileged permission control enable" "0,1" repeat.end repeat 16. (list 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1A 0x1B 0x1C 0x1D 0x1E 0x1F )(list 0x340 0x374 0x3A8 0x3DC 0x410 0x444 0x478 0x4AC 0x4E0 0x514 0x548 0x57C 0x5B0 0x5E4 0x618 0x64C ) group.long ($2+0x2424)++0x3 line.long 0x0 "PRI_PER3_$1,This register is only used for resource manager to control privileged access permission." bitfld.long 0x0 31. "DOM15_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM15_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM15_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM15_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM14_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM14_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM14_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM14_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM13_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM13_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM13_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM13_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM12_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM12_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM12_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM12_PRI_EN,Domain privileged permission control enable" "0,1" repeat.end repeat 16. (list 0x20 0x21 0x22 0x23 0x24 0x25 0x26 0x27 0x28 0x29 0x2A 0x2B 0x2C 0x2D 0x2E 0x2F )(list 0x680 0x6B4 0x6E8 0x71C 0x750 0x784 0x7B8 0x7EC 0x820 0x854 0x888 0x8BC 0x8F0 0x924 0x958 0x98C ) group.long ($2+0x2424)++0x3 line.long 0x0 "PRI_PER3_$1,This register is only used for resource manager to control privileged access permission." bitfld.long 0x0 31. "DOM15_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM15_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM15_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM15_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM14_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM14_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM14_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM14_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM13_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM13_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM13_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM13_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM12_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM12_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM12_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM12_PRI_EN,Domain privileged permission control enable" "0,1" repeat.end repeat 16. (list 0x30 0x31 0x32 0x33 0x34 0x35 0x36 0x37 0x38 0x39 0x3A 0x3B 0x3C 0x3D 0x3E 0x3F )(list 0x9C0 0x9F4 0xA28 0xA5C 0xA90 0xAC4 0xAF8 0xB2C 0xB60 0xB94 0xBC8 0xBFC 0xC30 0xC64 0xC98 0xCCC ) group.long ($2+0x2424)++0x3 line.long 0x0 "PRI_PER3_$1,This register is only used for resource manager to control privileged access permission." bitfld.long 0x0 31. "DOM15_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM15_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM15_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM15_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM14_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM14_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM14_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM14_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM13_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM13_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM13_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM13_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM12_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM12_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM12_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM12_PRI_EN,Domain privileged permission control enable" "0,1" repeat.end repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x34 0x68 0x9C 0xD0 0x104 0x138 0x16C 0x1A0 0x1D4 0x208 0x23C 0x270 0x2A4 0x2D8 0x30C ) group.long ($2+0x2428)++0x3 line.long 0x0 "DOM_SEC_PER_$1,This register is only used for domain master to control secure access permission. When the domain master write this register. it only changes the secure permission for itself. When the domain master read this register. it gets permission.." bitfld.long 0x0 7. "DOM_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" newline bitfld.long 0x0 0. "DOM_SEC_EN,Domain secure permission control enable" "0,1" repeat.end repeat 16. (list 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1A 0x1B 0x1C 0x1D 0x1E 0x1F )(list 0x340 0x374 0x3A8 0x3DC 0x410 0x444 0x478 0x4AC 0x4E0 0x514 0x548 0x57C 0x5B0 0x5E4 0x618 0x64C ) group.long ($2+0x2428)++0x3 line.long 0x0 "DOM_SEC_PER_$1,This register is only used for domain master to control secure access permission. When the domain master write this register. it only changes the secure permission for itself. When the domain master read this register. it gets permission.." bitfld.long 0x0 7. "DOM_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" newline bitfld.long 0x0 0. "DOM_SEC_EN,Domain secure permission control enable" "0,1" repeat.end repeat 16. (list 0x20 0x21 0x22 0x23 0x24 0x25 0x26 0x27 0x28 0x29 0x2A 0x2B 0x2C 0x2D 0x2E 0x2F )(list 0x680 0x6B4 0x6E8 0x71C 0x750 0x784 0x7B8 0x7EC 0x820 0x854 0x888 0x8BC 0x8F0 0x924 0x958 0x98C ) group.long ($2+0x2428)++0x3 line.long 0x0 "DOM_SEC_PER_$1,This register is only used for domain master to control secure access permission. When the domain master write this register. it only changes the secure permission for itself. When the domain master read this register. it gets permission.." bitfld.long 0x0 7. "DOM_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" newline bitfld.long 0x0 0. "DOM_SEC_EN,Domain secure permission control enable" "0,1" repeat.end repeat 16. (list 0x30 0x31 0x32 0x33 0x34 0x35 0x36 0x37 0x38 0x39 0x3A 0x3B 0x3C 0x3D 0x3E 0x3F )(list 0x9C0 0x9F4 0xA28 0xA5C 0xA90 0xAC4 0xAF8 0xB2C 0xB60 0xB94 0xBC8 0xBFC 0xC30 0xC64 0xC98 0xCCC ) group.long ($2+0x2428)++0x3 line.long 0x0 "DOM_SEC_PER_$1,This register is only used for domain master to control secure access permission. When the domain master write this register. it only changes the secure permission for itself. When the domain master read this register. it gets permission.." bitfld.long 0x0 7. "DOM_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" newline bitfld.long 0x0 0. "DOM_SEC_EN,Domain secure permission control enable" "0,1" repeat.end repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x34 0x68 0x9C 0xD0 0x104 0x138 0x16C 0x1A0 0x1D4 0x208 0x23C 0x270 0x2A4 0x2D8 0x30C ) group.long ($2+0x242C)++0x3 line.long 0x0 "DOM_PRI_PER_$1,This register is only used for domain master to control secure access permission. When the domain master write this register. it only changes the secure permission for itself. When the domain master read this register. it gets permission.." bitfld.long 0x0 7. "DOM_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" newline bitfld.long 0x0 0. "DOM_PRI_EN,Domain privileged permission control enable" "0,1" repeat.end repeat 16. (list 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1A 0x1B 0x1C 0x1D 0x1E 0x1F )(list 0x340 0x374 0x3A8 0x3DC 0x410 0x444 0x478 0x4AC 0x4E0 0x514 0x548 0x57C 0x5B0 0x5E4 0x618 0x64C ) group.long ($2+0x242C)++0x3 line.long 0x0 "DOM_PRI_PER_$1,This register is only used for domain master to control secure access permission. When the domain master write this register. it only changes the secure permission for itself. When the domain master read this register. it gets permission.." bitfld.long 0x0 7. "DOM_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" newline bitfld.long 0x0 0. "DOM_PRI_EN,Domain privileged permission control enable" "0,1" repeat.end repeat 16. (list 0x20 0x21 0x22 0x23 0x24 0x25 0x26 0x27 0x28 0x29 0x2A 0x2B 0x2C 0x2D 0x2E 0x2F )(list 0x680 0x6B4 0x6E8 0x71C 0x750 0x784 0x7B8 0x7EC 0x820 0x854 0x888 0x8BC 0x8F0 0x924 0x958 0x98C ) group.long ($2+0x242C)++0x3 line.long 0x0 "DOM_PRI_PER_$1,This register is only used for domain master to control secure access permission. When the domain master write this register. it only changes the secure permission for itself. When the domain master read this register. it gets permission.." bitfld.long 0x0 7. "DOM_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" newline bitfld.long 0x0 0. "DOM_PRI_EN,Domain privileged permission control enable" "0,1" repeat.end repeat 16. (list 0x30 0x31 0x32 0x33 0x34 0x35 0x36 0x37 0x38 0x39 0x3A 0x3B 0x3C 0x3D 0x3E 0x3F )(list 0x9C0 0x9F4 0xA28 0xA5C 0xA90 0xAC4 0xAF8 0xB2C 0xB60 0xB94 0xBC8 0xBFC 0xC30 0xC64 0xC98 0xCCC ) group.long ($2+0x242C)++0x3 line.long 0x0 "DOM_PRI_PER_$1,This register is only used for domain master to control secure access permission. When the domain master write this register. it only changes the secure permission for itself. When the domain master read this register. it gets permission.." bitfld.long 0x0 7. "DOM_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" newline bitfld.long 0x0 0. "DOM_PRI_EN,Domain privileged permission control enable" "0,1" repeat.end repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x34 0x68 0x9C 0xD0 0x104 0x138 0x16C 0x1A0 0x1D4 0x208 0x23C 0x270 0x2A4 0x2D8 0x30C ) group.long ($2+0x2430)++0x3 line.long 0x0 "DOM_ASSIGN_$1,Use to assign domain for accessing DOM_SEC_PER and DOM_PRI_PER register. Only resource manager. group manager and domain owner can access this register. For write. group manager must write its owen domain ID. otherwise write accessing will.." hexmask.long.byte 0x0 0.--3. 1. "DID,accessing DOM_SEC_PER and DOM_PRI_PER register" repeat.end repeat 16. (list 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1A 0x1B 0x1C 0x1D 0x1E 0x1F )(list 0x340 0x374 0x3A8 0x3DC 0x410 0x444 0x478 0x4AC 0x4E0 0x514 0x548 0x57C 0x5B0 0x5E4 0x618 0x64C ) group.long ($2+0x2430)++0x3 line.long 0x0 "DOM_ASSIGN_$1,Use to assign domain for accessing DOM_SEC_PER and DOM_PRI_PER register. Only resource manager. group manager and domain owner can access this register. For write. group manager must write its owen domain ID. otherwise write accessing will.." hexmask.long.byte 0x0 0.--3. 1. "DID,accessing DOM_SEC_PER and DOM_PRI_PER register" repeat.end repeat 16. (list 0x20 0x21 0x22 0x23 0x24 0x25 0x26 0x27 0x28 0x29 0x2A 0x2B 0x2C 0x2D 0x2E 0x2F )(list 0x680 0x6B4 0x6E8 0x71C 0x750 0x784 0x7B8 0x7EC 0x820 0x854 0x888 0x8BC 0x8F0 0x924 0x958 0x98C ) group.long ($2+0x2430)++0x3 line.long 0x0 "DOM_ASSIGN_$1,Use to assign domain for accessing DOM_SEC_PER and DOM_PRI_PER register. Only resource manager. group manager and domain owner can access this register. For write. group manager must write its owen domain ID. otherwise write accessing will.." hexmask.long.byte 0x0 0.--3. 1. "DID,accessing DOM_SEC_PER and DOM_PRI_PER register" repeat.end repeat 16. (list 0x30 0x31 0x32 0x33 0x34 0x35 0x36 0x37 0x38 0x39 0x3A 0x3B 0x3C 0x3D 0x3E 0x3F )(list 0x9C0 0x9F4 0xA28 0xA5C 0xA90 0xAC4 0xAF8 0xB2C 0xB60 0xB94 0xBC8 0xBFC 0xC30 0xC64 0xC98 0xCCC ) group.long ($2+0x2430)++0x3 line.long 0x0 "DOM_ASSIGN_$1,Use to assign domain for accessing DOM_SEC_PER and DOM_PRI_PER register. Only resource manager. group manager and domain owner can access this register. For write. group manager must write its owen domain ID. otherwise write accessing will.." hexmask.long.byte 0x0 0.--3. 1. "DID,accessing DOM_SEC_PER and DOM_PRI_PER register" repeat.end repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x38 0x70 0xA8 0xE0 0x118 0x150 0x188 0x1C0 0x1F8 0x230 0x268 0x2A0 0x2D8 0x310 0x348 ) group.long ($2+0x3100)++0x3 line.long 0x0 "RGN_DOM_$1,Assign domain for peripheral. It can be only configured by resource and group manager" bitfld.long 0x0 31. "LOCK,When this bit is set lock write for all the bits in the register." "0,1" bitfld.long 0x0 4. "SET,Set together with DID would change permission of this resource to following setting: 1) Domain access control enabled. 2) Read/Write allowed for the domain owner. 3) Read/Write not allowed for all the other domains. If this bit is not set only DID.." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Assign domain for peripheral" repeat.end repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x38 0x70 0xA8 0xE0 0x118 0x150 0x188 0x1C0 0x1F8 0x230 0x268 0x2A0 0x2D8 0x310 0x348 ) group.long ($2+0x3104)++0x3 line.long 0x0 "RGN_DOM_PER0_$1,Domain Permission Control. It can be only configured by resource manager and domain owner." bitfld.long 0x0 31. "DOM7_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 29.--30. "DOM7_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 28. "DOM7_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 27. "DOM6_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 25.--26. "DOM6_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" newline bitfld.long 0x0 24. "DOM6_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 23. "DOM5_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 21.--22. "DOM5_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 20. "DOM5_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 19. "DOM4_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" newline bitfld.long 0x0 17.--18. "DOM4_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM4_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 15. "DOM3_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 13.--14. "DOM3_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 12. "DOM3_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" newline bitfld.long 0x0 11. "DOM2_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 9.--10. "DOM2_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM2_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 7. "DOM1_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 5.--6. "DOM1_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" newline bitfld.long 0x0 4. "DOM1_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 3. "DOM0_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 1.--2. "DOM0_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM0_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" repeat.end repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x38 0x70 0xA8 0xE0 0x118 0x150 0x188 0x1C0 0x1F8 0x230 0x268 0x2A0 0x2D8 0x310 0x348 ) group.long ($2+0x3108)++0x3 line.long 0x0 "RGN_DOM_PER1_$1,Domain Permission Control. It can be only configured by resource manager and domain owner." bitfld.long 0x0 31. "DOM15_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 29.--30. "DOM15_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 28. "DOM15_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 27. "DOM14_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 25.--26. "DOM14_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" newline bitfld.long 0x0 24. "DOM14_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 23. "DOM13_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 21.--22. "DOM13_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 20. "DOM13_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 19. "DOM12_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" newline bitfld.long 0x0 17.--18. "DOM12_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM12_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 15. "DOM11_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 13.--14. "DOM11_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 12. "DOM11_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" newline bitfld.long 0x0 11. "DOM10_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 9.--10. "DOM10_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM10_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 7. "DOM9_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 5.--6. "DOM9_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" newline bitfld.long 0x0 4. "DOM9_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 3. "DOM8_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 1.--2. "DOM8_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM8_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" repeat.end repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x38 0x70 0xA8 0xE0 0x118 0x150 0x188 0x1C0 0x1F8 0x230 0x268 0x2A0 0x2D8 0x310 0x348 ) group.long ($2+0x310C)++0x3 line.long 0x0 "RGN_SEC_PER0_$1,This register is only used for resource manager to control secure access permission." bitfld.long 0x0 31. "DOM3_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM3_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM3_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM3_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM2_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM2_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM2_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM2_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM1_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM1_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM1_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM1_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM0_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM0_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM0_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM0_SEC_EN,Domain secure permission control enable" "0,1" repeat.end repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x38 0x70 0xA8 0xE0 0x118 0x150 0x188 0x1C0 0x1F8 0x230 0x268 0x2A0 0x2D8 0x310 0x348 ) group.long ($2+0x3110)++0x3 line.long 0x0 "RGN_SEC_PER1_$1,This register is only used for resource manager to control secure access permission." bitfld.long 0x0 31. "DOM7_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM7_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM7_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM7_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM6_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM6_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM6_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM6_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM5_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM5_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM5_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM5_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM4_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM4_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM4_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM4_SEC_EN,Domain secure permission control enable" "0,1" repeat.end repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x38 0x70 0xA8 0xE0 0x118 0x150 0x188 0x1C0 0x1F8 0x230 0x268 0x2A0 0x2D8 0x310 0x348 ) group.long ($2+0x3114)++0x3 line.long 0x0 "RGN_SEC_PER2_$1,This register is only used for resource manager to control secure access permission." bitfld.long 0x0 31. "DOM11_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM11_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM11_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM11_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM10_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM10_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM10_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM10_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM9_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM9_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM9_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM9_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM8_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM8_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM8_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM8_SEC_EN,Domain secure permission control enable" "0,1" repeat.end repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x38 0x70 0xA8 0xE0 0x118 0x150 0x188 0x1C0 0x1F8 0x230 0x268 0x2A0 0x2D8 0x310 0x348 ) group.long ($2+0x3118)++0x3 line.long 0x0 "RGN_SEC_PER3_$1,This register is only used for resource manager to control secure access permission." bitfld.long 0x0 31. "DOM15_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM15_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM15_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM15_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM14_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM14_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM14_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM14_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM13_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM13_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM13_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM13_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM12_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM12_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM12_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM12_SEC_EN,Domain secure permission control enable" "0,1" repeat.end repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x38 0x70 0xA8 0xE0 0x118 0x150 0x188 0x1C0 0x1F8 0x230 0x268 0x2A0 0x2D8 0x310 0x348 ) group.long ($2+0x311C)++0x3 line.long 0x0 "RGN_PRI_PER0_$1,This register is only used for resource manager to control privileged access permission." bitfld.long 0x0 31. "DOM3_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM3_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM3_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM3_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM2_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM2_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM2_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM2_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM1_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM1_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM1_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM1_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM0_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM0_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM0_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM0_PRI_EN,Domain privileged permission control enable" "0,1" repeat.end repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x38 0x70 0xA8 0xE0 0x118 0x150 0x188 0x1C0 0x1F8 0x230 0x268 0x2A0 0x2D8 0x310 0x348 ) group.long ($2+0x3120)++0x3 line.long 0x0 "RGN_PRI_PER1_$1,This register is only used for resource manager to control privileged access permission." bitfld.long 0x0 31. "DOM7_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM7_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM7_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM7_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM6_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM6_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM6_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM6_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM5_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM5_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM5_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM5_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM4_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM4_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM4_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM4_PRI_EN,Domain privileged permission control enable" "0,1" repeat.end repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x38 0x70 0xA8 0xE0 0x118 0x150 0x188 0x1C0 0x1F8 0x230 0x268 0x2A0 0x2D8 0x310 0x348 ) group.long ($2+0x3124)++0x3 line.long 0x0 "RGN_PRI_PER2_$1,This register is only used for resource manager to control privileged access permission." bitfld.long 0x0 31. "DOM11_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM11_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM11_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM11_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM10_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM10_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM10_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM10_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM9_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM9_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM9_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM9_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM8_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM8_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM8_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM8_PRI_EN,Domain privileged permission control enable" "0,1" repeat.end repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x38 0x70 0xA8 0xE0 0x118 0x150 0x188 0x1C0 0x1F8 0x230 0x268 0x2A0 0x2D8 0x310 0x348 ) group.long ($2+0x3128)++0x3 line.long 0x0 "RGN_PRI_PER3_$1,This register is only used for resource manager to control privileged access permission." bitfld.long 0x0 31. "DOM15_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM15_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM15_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM15_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM14_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM14_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM14_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM14_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM13_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM13_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM13_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM13_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM12_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM12_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM12_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM12_PRI_EN,Domain privileged permission control enable" "0,1" repeat.end repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x38 0x70 0xA8 0xE0 0x118 0x150 0x188 0x1C0 0x1F8 0x230 0x268 0x2A0 0x2D8 0x310 0x348 ) group.long ($2+0x312C)++0x3 line.long 0x0 "RGN_DOM_SEC_PER_$1,This register is only used for domain master to control secure access permission. When the domain master write this register. it only changes the secure permission for itself. When the domain master read this register. it gets.." bitfld.long 0x0 7. "DOM_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" newline bitfld.long 0x0 0. "DOM_SEC_EN,Domain secure permission control enable" "0,1" repeat.end repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x38 0x70 0xA8 0xE0 0x118 0x150 0x188 0x1C0 0x1F8 0x230 0x268 0x2A0 0x2D8 0x310 0x348 ) group.long ($2+0x3130)++0x3 line.long 0x0 "RGN_DOM_PRI_PER_$1,This register is only used for domain master to control secure access permission. When the domain master write this register. it only changes the secure permission for itself. When the domain master read this register. it gets.." bitfld.long 0x0 7. "DOM_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" newline bitfld.long 0x0 0. "DOM_PRI_EN,Domain privileged permission control enable" "0,1" repeat.end repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x38 0x70 0xA8 0xE0 0x118 0x150 0x188 0x1C0 0x1F8 0x230 0x268 0x2A0 0x2D8 0x310 0x348 ) group.long ($2+0x3134)++0x3 line.long 0x0 "RGN_DOM_ASSIGN_$1,Use to assign domain for accessing DOM_SEC_PER and DOM_PRI_PER register. Only resource manager. group manager and domain owner can access this register. For write. group manager must write its owen domain ID. otherwise write accessing.." hexmask.long.byte 0x0 0.--3. 1. "DID,accessing DOM_SEC_PER and DOM_PRI_PER register" repeat.end tree.end tree "RPC_SAFETY_PINCTRL" base ad:0xFCD00000 repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x4 0x8 0xC 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C ) group.long ($2)++0x3 line.long 0x0 "REGG0_DOM_$1,Assign domain for CKGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1A 0x1B 0x1C 0x1D 0x1E 0x1F )(list 0x40 0x44 0x48 0x4C 0x50 0x54 0x58 0x5C 0x60 0x64 0x68 0x6C 0x70 0x74 0x78 0x7C ) group.long ($2)++0x3 line.long 0x0 "REGG0_DOM_$1,Assign domain for CKGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x20 0x21 0x22 0x23 0x24 0x25 0x26 0x27 0x28 0x29 0x2A 0x2B 0x2C 0x2D 0x2E 0x2F )(list 0x80 0x84 0x88 0x8C 0x90 0x94 0x98 0x9C 0xA0 0xA4 0xA8 0xAC 0xB0 0xB4 0xB8 0xBC ) group.long ($2)++0x3 line.long 0x0 "REGG0_DOM_$1,Assign domain for CKGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x30 0x31 0x32 0x33 0x34 0x35 0x36 0x37 0x38 0x39 0x3A 0x3B 0x3C 0x3D 0x3E 0x3F )(list 0xC0 0xC4 0xC8 0xCC 0xD0 0xD4 0xD8 0xDC 0xE0 0xE4 0xE8 0xEC 0xF0 0xF4 0xF8 0xFC ) group.long ($2)++0x3 line.long 0x0 "REGG0_DOM_$1,Assign domain for CKGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x40 0x41 0x42 0x43 0x44 0x45 0x46 0x47 0x48 0x49 0x4A 0x4B 0x4C 0x4D 0x4E 0x4F )(list 0x100 0x104 0x108 0x10C 0x110 0x114 0x118 0x11C 0x120 0x124 0x128 0x12C 0x130 0x134 0x138 0x13C ) group.long ($2)++0x3 line.long 0x0 "REGG0_DOM_$1,Assign domain for CKGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x50 0x51 0x52 0x53 0x54 0x55 0x56 0x57 0x58 0x59 0x5A 0x5B 0x5C 0x5D 0x5E 0x5F )(list 0x140 0x144 0x148 0x14C 0x150 0x154 0x158 0x15C 0x160 0x164 0x168 0x16C 0x170 0x174 0x178 0x17C ) group.long ($2)++0x3 line.long 0x0 "REGG0_DOM_$1,Assign domain for CKGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x60 0x61 0x62 0x63 0x64 0x65 0x66 0x67 0x68 0x69 0x6A 0x6B 0x6C 0x6D 0x6E 0x6F )(list 0x180 0x184 0x188 0x18C 0x190 0x194 0x198 0x19C 0x1A0 0x1A4 0x1A8 0x1AC 0x1B0 0x1B4 0x1B8 0x1BC ) group.long ($2)++0x3 line.long 0x0 "REGG0_DOM_$1,Assign domain for CKGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x70 0x71 0x72 0x73 0x74 0x75 0x76 0x77 0x78 0x79 0x7A 0x7B 0x7C 0x7D 0x7E 0x7F )(list 0x1C0 0x1C4 0x1C8 0x1CC 0x1D0 0x1D4 0x1D8 0x1DC 0x1E0 0x1E4 0x1E8 0x1EC 0x1F0 0x1F4 0x1F8 0x1FC ) group.long ($2)++0x3 line.long 0x0 "REGG0_DOM_$1,Assign domain for CKGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x80 0x81 0x82 0x83 0x84 0x85 0x86 0x87 0x88 0x89 0x8A 0x8B 0x8C 0x8D 0x8E 0x8F )(list 0x200 0x204 0x208 0x20C 0x210 0x214 0x218 0x21C 0x220 0x224 0x228 0x22C 0x230 0x234 0x238 0x23C ) group.long ($2)++0x3 line.long 0x0 "REGG0_DOM_$1,Assign domain for CKGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x90 0x91 0x92 0x93 0x94 0x95 0x96 0x97 0x98 0x99 0x9A 0x9B 0x9C 0x9D 0x9E 0x9F )(list 0x240 0x244 0x248 0x24C 0x250 0x254 0x258 0x25C 0x260 0x264 0x268 0x26C 0x270 0x274 0x278 0x27C ) group.long ($2)++0x3 line.long 0x0 "REGG0_DOM_$1,Assign domain for CKGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xA0 0xA1 0xA2 0xA3 0xA4 0xA5 0xA6 0xA7 0xA8 0xA9 0xAA 0xAB 0xAC 0xAD 0xAE 0xAF )(list 0x280 0x284 0x288 0x28C 0x290 0x294 0x298 0x29C 0x2A0 0x2A4 0x2A8 0x2AC 0x2B0 0x2B4 0x2B8 0x2BC ) group.long ($2)++0x3 line.long 0x0 "REGG0_DOM_$1,Assign domain for CKGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xB0 0xB1 0xB2 0xB3 0xB4 0xB5 0xB6 0xB7 0xB8 0xB9 0xBA 0xBB 0xBC 0xBD 0xBE 0xBF )(list 0x2C0 0x2C4 0x2C8 0x2CC 0x2D0 0x2D4 0x2D8 0x2DC 0x2E0 0x2E4 0x2E8 0x2EC 0x2F0 0x2F4 0x2F8 0x2FC ) group.long ($2)++0x3 line.long 0x0 "REGG0_DOM_$1,Assign domain for CKGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xC0 0xC1 0xC2 0xC3 0xC4 0xC5 0xC6 0xC7 0xC8 0xC9 0xCA 0xCB 0xCC 0xCD 0xCE 0xCF )(list 0x300 0x304 0x308 0x30C 0x310 0x314 0x318 0x31C 0x320 0x324 0x328 0x32C 0x330 0x334 0x338 0x33C ) group.long ($2)++0x3 line.long 0x0 "REGG0_DOM_$1,Assign domain for CKGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xD0 0xD1 0xD2 0xD3 0xD4 0xD5 0xD6 0xD7 0xD8 0xD9 0xDA 0xDB 0xDC 0xDD 0xDE 0xDF )(list 0x340 0x344 0x348 0x34C 0x350 0x354 0x358 0x35C 0x360 0x364 0x368 0x36C 0x370 0x374 0x378 0x37C ) group.long ($2)++0x3 line.long 0x0 "REGG0_DOM_$1,Assign domain for CKGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xE0 0xE1 0xE2 0xE3 0xE4 0xE5 0xE6 0xE7 0xE8 0xE9 0xEA 0xEB 0xEC 0xED 0xEE 0xEF )(list 0x380 0x384 0x388 0x38C 0x390 0x394 0x398 0x39C 0x3A0 0x3A4 0x3A8 0x3AC 0x3B0 0x3B4 0x3B8 0x3BC ) group.long ($2)++0x3 line.long 0x0 "REGG0_DOM_$1,Assign domain for CKGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xF0 0xF1 0xF2 0xF3 0xF4 0xF5 0xF6 0xF7 0xF8 0xF9 0xFA 0xFB 0xFC 0xFD 0xFE 0xFF )(list 0x3C0 0x3C4 0x3C8 0x3CC 0x3D0 0x3D4 0x3D8 0x3DC 0x3E0 0x3E4 0x3E8 0x3EC 0x3F0 0x3F4 0x3F8 0x3FC ) group.long ($2)++0x3 line.long 0x0 "REGG0_DOM_$1,Assign domain for CKGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x4 0x8 0xC 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C ) group.long ($2+0x400)++0x3 line.long 0x0 "REGG1_DOM_$1,Assign domain for CKGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1A 0x1B 0x1C 0x1D 0x1E 0x1F )(list 0x40 0x44 0x48 0x4C 0x50 0x54 0x58 0x5C 0x60 0x64 0x68 0x6C 0x70 0x74 0x78 0x7C ) group.long ($2+0x400)++0x3 line.long 0x0 "REGG1_DOM_$1,Assign domain for CKGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x20 0x21 0x22 0x23 0x24 0x25 0x26 0x27 0x28 0x29 0x2A 0x2B 0x2C 0x2D 0x2E 0x2F )(list 0x80 0x84 0x88 0x8C 0x90 0x94 0x98 0x9C 0xA0 0xA4 0xA8 0xAC 0xB0 0xB4 0xB8 0xBC ) group.long ($2+0x400)++0x3 line.long 0x0 "REGG1_DOM_$1,Assign domain for CKGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x30 0x31 0x32 0x33 0x34 0x35 0x36 0x37 0x38 0x39 0x3A 0x3B 0x3C 0x3D 0x3E 0x3F )(list 0xC0 0xC4 0xC8 0xCC 0xD0 0xD4 0xD8 0xDC 0xE0 0xE4 0xE8 0xEC 0xF0 0xF4 0xF8 0xFC ) group.long ($2+0x400)++0x3 line.long 0x0 "REGG1_DOM_$1,Assign domain for CKGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x40 0x41 0x42 0x43 0x44 0x45 0x46 0x47 0x48 0x49 0x4A 0x4B 0x4C 0x4D 0x4E 0x4F )(list 0x100 0x104 0x108 0x10C 0x110 0x114 0x118 0x11C 0x120 0x124 0x128 0x12C 0x130 0x134 0x138 0x13C ) group.long ($2+0x400)++0x3 line.long 0x0 "REGG1_DOM_$1,Assign domain for CKGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x50 0x51 0x52 0x53 0x54 0x55 0x56 0x57 0x58 0x59 0x5A 0x5B 0x5C 0x5D 0x5E 0x5F )(list 0x140 0x144 0x148 0x14C 0x150 0x154 0x158 0x15C 0x160 0x164 0x168 0x16C 0x170 0x174 0x178 0x17C ) group.long ($2+0x400)++0x3 line.long 0x0 "REGG1_DOM_$1,Assign domain for CKGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x60 0x61 0x62 0x63 0x64 0x65 0x66 0x67 0x68 0x69 0x6A 0x6B 0x6C 0x6D 0x6E 0x6F )(list 0x180 0x184 0x188 0x18C 0x190 0x194 0x198 0x19C 0x1A0 0x1A4 0x1A8 0x1AC 0x1B0 0x1B4 0x1B8 0x1BC ) group.long ($2+0x400)++0x3 line.long 0x0 "REGG1_DOM_$1,Assign domain for CKGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x70 0x71 0x72 0x73 0x74 0x75 0x76 0x77 0x78 0x79 0x7A 0x7B 0x7C 0x7D 0x7E 0x7F )(list 0x1C0 0x1C4 0x1C8 0x1CC 0x1D0 0x1D4 0x1D8 0x1DC 0x1E0 0x1E4 0x1E8 0x1EC 0x1F0 0x1F4 0x1F8 0x1FC ) group.long ($2+0x400)++0x3 line.long 0x0 "REGG1_DOM_$1,Assign domain for CKGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x80 0x81 0x82 0x83 0x84 0x85 0x86 0x87 0x88 0x89 0x8A 0x8B 0x8C 0x8D 0x8E 0x8F )(list 0x200 0x204 0x208 0x20C 0x210 0x214 0x218 0x21C 0x220 0x224 0x228 0x22C 0x230 0x234 0x238 0x23C ) group.long ($2+0x400)++0x3 line.long 0x0 "REGG1_DOM_$1,Assign domain for CKGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x90 0x91 0x92 0x93 0x94 0x95 0x96 0x97 0x98 0x99 0x9A 0x9B 0x9C 0x9D 0x9E 0x9F )(list 0x240 0x244 0x248 0x24C 0x250 0x254 0x258 0x25C 0x260 0x264 0x268 0x26C 0x270 0x274 0x278 0x27C ) group.long ($2+0x400)++0x3 line.long 0x0 "REGG1_DOM_$1,Assign domain for CKGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xA0 0xA1 0xA2 0xA3 0xA4 0xA5 0xA6 0xA7 0xA8 0xA9 0xAA 0xAB 0xAC 0xAD 0xAE 0xAF )(list 0x280 0x284 0x288 0x28C 0x290 0x294 0x298 0x29C 0x2A0 0x2A4 0x2A8 0x2AC 0x2B0 0x2B4 0x2B8 0x2BC ) group.long ($2+0x400)++0x3 line.long 0x0 "REGG1_DOM_$1,Assign domain for CKGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xB0 0xB1 0xB2 0xB3 0xB4 0xB5 0xB6 0xB7 0xB8 0xB9 0xBA 0xBB 0xBC 0xBD 0xBE 0xBF )(list 0x2C0 0x2C4 0x2C8 0x2CC 0x2D0 0x2D4 0x2D8 0x2DC 0x2E0 0x2E4 0x2E8 0x2EC 0x2F0 0x2F4 0x2F8 0x2FC ) group.long ($2+0x400)++0x3 line.long 0x0 "REGG1_DOM_$1,Assign domain for CKGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xC0 0xC1 0xC2 0xC3 0xC4 0xC5 0xC6 0xC7 0xC8 0xC9 0xCA 0xCB 0xCC 0xCD 0xCE 0xCF )(list 0x300 0x304 0x308 0x30C 0x310 0x314 0x318 0x31C 0x320 0x324 0x328 0x32C 0x330 0x334 0x338 0x33C ) group.long ($2+0x400)++0x3 line.long 0x0 "REGG1_DOM_$1,Assign domain for CKGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xD0 0xD1 0xD2 0xD3 0xD4 0xD5 0xD6 0xD7 0xD8 0xD9 0xDA 0xDB 0xDC 0xDD 0xDE 0xDF )(list 0x340 0x344 0x348 0x34C 0x350 0x354 0x358 0x35C 0x360 0x364 0x368 0x36C 0x370 0x374 0x378 0x37C ) group.long ($2+0x400)++0x3 line.long 0x0 "REGG1_DOM_$1,Assign domain for CKGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xE0 0xE1 0xE2 0xE3 0xE4 0xE5 0xE6 0xE7 0xE8 0xE9 0xEA 0xEB 0xEC 0xED 0xEE 0xEF )(list 0x380 0x384 0x388 0x38C 0x390 0x394 0x398 0x39C 0x3A0 0x3A4 0x3A8 0x3AC 0x3B0 0x3B4 0x3B8 0x3BC ) group.long ($2+0x400)++0x3 line.long 0x0 "REGG1_DOM_$1,Assign domain for CKGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xF0 0xF1 0xF2 0xF3 0xF4 0xF5 0xF6 0xF7 0xF8 0xF9 0xFA 0xFB 0xFC 0xFD 0xFE 0xFF )(list 0x3C0 0x3C4 0x3C8 0x3CC 0x3D0 0x3D4 0x3D8 0x3DC 0x3E0 0x3E4 0x3E8 0x3EC 0x3F0 0x3F4 0x3F8 0x3FC ) group.long ($2+0x400)++0x3 line.long 0x0 "REGG1_DOM_$1,Assign domain for CKGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x4 0x8 0xC 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C ) group.long ($2+0x800)++0x3 line.long 0x0 "REGG2_DOM_$1,Assign domain for SCR registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1A 0x1B 0x1C 0x1D 0x1E 0x1F )(list 0x40 0x44 0x48 0x4C 0x50 0x54 0x58 0x5C 0x60 0x64 0x68 0x6C 0x70 0x74 0x78 0x7C ) group.long ($2+0x800)++0x3 line.long 0x0 "REGG2_DOM_$1,Assign domain for SCR registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x20 0x21 0x22 0x23 0x24 0x25 0x26 0x27 0x28 0x29 0x2A 0x2B 0x2C 0x2D 0x2E 0x2F )(list 0x80 0x84 0x88 0x8C 0x90 0x94 0x98 0x9C 0xA0 0xA4 0xA8 0xAC 0xB0 0xB4 0xB8 0xBC ) group.long ($2+0x800)++0x3 line.long 0x0 "REGG2_DOM_$1,Assign domain for SCR registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x30 0x31 0x32 0x33 0x34 0x35 0x36 0x37 0x38 0x39 0x3A 0x3B 0x3C 0x3D 0x3E 0x3F )(list 0xC0 0xC4 0xC8 0xCC 0xD0 0xD4 0xD8 0xDC 0xE0 0xE4 0xE8 0xEC 0xF0 0xF4 0xF8 0xFC ) group.long ($2+0x800)++0x3 line.long 0x0 "REGG2_DOM_$1,Assign domain for SCR registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x40 0x41 0x42 0x43 0x44 0x45 0x46 0x47 0x48 0x49 0x4A 0x4B 0x4C 0x4D 0x4E 0x4F )(list 0x100 0x104 0x108 0x10C 0x110 0x114 0x118 0x11C 0x120 0x124 0x128 0x12C 0x130 0x134 0x138 0x13C ) group.long ($2+0x800)++0x3 line.long 0x0 "REGG2_DOM_$1,Assign domain for SCR registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x50 0x51 0x52 0x53 0x54 0x55 0x56 0x57 0x58 0x59 0x5A 0x5B 0x5C 0x5D 0x5E 0x5F )(list 0x140 0x144 0x148 0x14C 0x150 0x154 0x158 0x15C 0x160 0x164 0x168 0x16C 0x170 0x174 0x178 0x17C ) group.long ($2+0x800)++0x3 line.long 0x0 "REGG2_DOM_$1,Assign domain for SCR registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x60 0x61 0x62 0x63 0x64 0x65 0x66 0x67 0x68 0x69 0x6A 0x6B 0x6C 0x6D 0x6E 0x6F )(list 0x180 0x184 0x188 0x18C 0x190 0x194 0x198 0x19C 0x1A0 0x1A4 0x1A8 0x1AC 0x1B0 0x1B4 0x1B8 0x1BC ) group.long ($2+0x800)++0x3 line.long 0x0 "REGG2_DOM_$1,Assign domain for SCR registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x70 0x71 0x72 0x73 0x74 0x75 0x76 0x77 0x78 0x79 0x7A 0x7B 0x7C 0x7D 0x7E 0x7F )(list 0x1C0 0x1C4 0x1C8 0x1CC 0x1D0 0x1D4 0x1D8 0x1DC 0x1E0 0x1E4 0x1E8 0x1EC 0x1F0 0x1F4 0x1F8 0x1FC ) group.long ($2+0x800)++0x3 line.long 0x0 "REGG2_DOM_$1,Assign domain for SCR registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x80 0x81 0x82 0x83 0x84 0x85 0x86 0x87 0x88 0x89 0x8A 0x8B 0x8C 0x8D 0x8E 0x8F )(list 0x200 0x204 0x208 0x20C 0x210 0x214 0x218 0x21C 0x220 0x224 0x228 0x22C 0x230 0x234 0x238 0x23C ) group.long ($2+0x800)++0x3 line.long 0x0 "REGG2_DOM_$1,Assign domain for SCR registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x90 0x91 0x92 0x93 0x94 0x95 0x96 0x97 0x98 0x99 0x9A 0x9B 0x9C 0x9D 0x9E 0x9F )(list 0x240 0x244 0x248 0x24C 0x250 0x254 0x258 0x25C 0x260 0x264 0x268 0x26C 0x270 0x274 0x278 0x27C ) group.long ($2+0x800)++0x3 line.long 0x0 "REGG2_DOM_$1,Assign domain for SCR registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xA0 0xA1 0xA2 0xA3 0xA4 0xA5 0xA6 0xA7 0xA8 0xA9 0xAA 0xAB 0xAC 0xAD 0xAE 0xAF )(list 0x280 0x284 0x288 0x28C 0x290 0x294 0x298 0x29C 0x2A0 0x2A4 0x2A8 0x2AC 0x2B0 0x2B4 0x2B8 0x2BC ) group.long ($2+0x800)++0x3 line.long 0x0 "REGG2_DOM_$1,Assign domain for SCR registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xB0 0xB1 0xB2 0xB3 0xB4 0xB5 0xB6 0xB7 0xB8 0xB9 0xBA 0xBB 0xBC 0xBD 0xBE 0xBF )(list 0x2C0 0x2C4 0x2C8 0x2CC 0x2D0 0x2D4 0x2D8 0x2DC 0x2E0 0x2E4 0x2E8 0x2EC 0x2F0 0x2F4 0x2F8 0x2FC ) group.long ($2+0x800)++0x3 line.long 0x0 "REGG2_DOM_$1,Assign domain for SCR registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xC0 0xC1 0xC2 0xC3 0xC4 0xC5 0xC6 0xC7 0xC8 0xC9 0xCA 0xCB 0xCC 0xCD 0xCE 0xCF )(list 0x300 0x304 0x308 0x30C 0x310 0x314 0x318 0x31C 0x320 0x324 0x328 0x32C 0x330 0x334 0x338 0x33C ) group.long ($2+0x800)++0x3 line.long 0x0 "REGG2_DOM_$1,Assign domain for SCR registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xD0 0xD1 0xD2 0xD3 0xD4 0xD5 0xD6 0xD7 0xD8 0xD9 0xDA 0xDB 0xDC 0xDD 0xDE 0xDF )(list 0x340 0x344 0x348 0x34C 0x350 0x354 0x358 0x35C 0x360 0x364 0x368 0x36C 0x370 0x374 0x378 0x37C ) group.long ($2+0x800)++0x3 line.long 0x0 "REGG2_DOM_$1,Assign domain for SCR registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xE0 0xE1 0xE2 0xE3 0xE4 0xE5 0xE6 0xE7 0xE8 0xE9 0xEA 0xEB 0xEC 0xED 0xEE 0xEF )(list 0x380 0x384 0x388 0x38C 0x390 0x394 0x398 0x39C 0x3A0 0x3A4 0x3A8 0x3AC 0x3B0 0x3B4 0x3B8 0x3BC ) group.long ($2+0x800)++0x3 line.long 0x0 "REGG2_DOM_$1,Assign domain for SCR registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xF0 0xF1 0xF2 0xF3 0xF4 0xF5 0xF6 0xF7 0xF8 0xF9 0xFA 0xFB 0xFC 0xFD 0xFE 0xFF )(list 0x3C0 0x3C4 0x3C8 0x3CC 0x3D0 0x3D4 0x3D8 0x3DC 0x3E0 0x3E4 0x3E8 0x3EC 0x3F0 0x3F4 0x3F8 0x3FC ) group.long ($2+0x800)++0x3 line.long 0x0 "REGG2_DOM_$1,Assign domain for SCR registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x4 0x8 0xC 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C ) group.long ($2+0xC00)++0x3 line.long 0x0 "REGG3_DOM_$1,Assign domain for SCR registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1A 0x1B 0x1C 0x1D 0x1E 0x1F )(list 0x40 0x44 0x48 0x4C 0x50 0x54 0x58 0x5C 0x60 0x64 0x68 0x6C 0x70 0x74 0x78 0x7C ) group.long ($2+0xC00)++0x3 line.long 0x0 "REGG3_DOM_$1,Assign domain for SCR registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x20 0x21 0x22 0x23 0x24 0x25 0x26 0x27 0x28 0x29 0x2A 0x2B 0x2C 0x2D 0x2E 0x2F )(list 0x80 0x84 0x88 0x8C 0x90 0x94 0x98 0x9C 0xA0 0xA4 0xA8 0xAC 0xB0 0xB4 0xB8 0xBC ) group.long ($2+0xC00)++0x3 line.long 0x0 "REGG3_DOM_$1,Assign domain for SCR registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x30 0x31 0x32 0x33 0x34 0x35 0x36 0x37 0x38 0x39 0x3A 0x3B 0x3C 0x3D 0x3E 0x3F )(list 0xC0 0xC4 0xC8 0xCC 0xD0 0xD4 0xD8 0xDC 0xE0 0xE4 0xE8 0xEC 0xF0 0xF4 0xF8 0xFC ) group.long ($2+0xC00)++0x3 line.long 0x0 "REGG3_DOM_$1,Assign domain for SCR registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x40 0x41 0x42 0x43 0x44 0x45 0x46 0x47 0x48 0x49 0x4A 0x4B 0x4C 0x4D 0x4E 0x4F )(list 0x100 0x104 0x108 0x10C 0x110 0x114 0x118 0x11C 0x120 0x124 0x128 0x12C 0x130 0x134 0x138 0x13C ) group.long ($2+0xC00)++0x3 line.long 0x0 "REGG3_DOM_$1,Assign domain for SCR registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x50 0x51 0x52 0x53 0x54 0x55 0x56 0x57 0x58 0x59 0x5A 0x5B 0x5C 0x5D 0x5E 0x5F )(list 0x140 0x144 0x148 0x14C 0x150 0x154 0x158 0x15C 0x160 0x164 0x168 0x16C 0x170 0x174 0x178 0x17C ) group.long ($2+0xC00)++0x3 line.long 0x0 "REGG3_DOM_$1,Assign domain for SCR registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x60 0x61 0x62 0x63 0x64 0x65 0x66 0x67 0x68 0x69 0x6A 0x6B 0x6C 0x6D 0x6E 0x6F )(list 0x180 0x184 0x188 0x18C 0x190 0x194 0x198 0x19C 0x1A0 0x1A4 0x1A8 0x1AC 0x1B0 0x1B4 0x1B8 0x1BC ) group.long ($2+0xC00)++0x3 line.long 0x0 "REGG3_DOM_$1,Assign domain for SCR registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x70 0x71 0x72 0x73 0x74 0x75 0x76 0x77 0x78 0x79 0x7A 0x7B 0x7C 0x7D 0x7E 0x7F )(list 0x1C0 0x1C4 0x1C8 0x1CC 0x1D0 0x1D4 0x1D8 0x1DC 0x1E0 0x1E4 0x1E8 0x1EC 0x1F0 0x1F4 0x1F8 0x1FC ) group.long ($2+0xC00)++0x3 line.long 0x0 "REGG3_DOM_$1,Assign domain for SCR registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x80 0x81 0x82 0x83 0x84 0x85 0x86 0x87 0x88 0x89 0x8A 0x8B 0x8C 0x8D 0x8E 0x8F )(list 0x200 0x204 0x208 0x20C 0x210 0x214 0x218 0x21C 0x220 0x224 0x228 0x22C 0x230 0x234 0x238 0x23C ) group.long ($2+0xC00)++0x3 line.long 0x0 "REGG3_DOM_$1,Assign domain for SCR registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x90 0x91 0x92 0x93 0x94 0x95 0x96 0x97 0x98 0x99 0x9A 0x9B 0x9C 0x9D 0x9E 0x9F )(list 0x240 0x244 0x248 0x24C 0x250 0x254 0x258 0x25C 0x260 0x264 0x268 0x26C 0x270 0x274 0x278 0x27C ) group.long ($2+0xC00)++0x3 line.long 0x0 "REGG3_DOM_$1,Assign domain for SCR registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xA0 0xA1 0xA2 0xA3 0xA4 0xA5 0xA6 0xA7 0xA8 0xA9 0xAA 0xAB 0xAC 0xAD 0xAE 0xAF )(list 0x280 0x284 0x288 0x28C 0x290 0x294 0x298 0x29C 0x2A0 0x2A4 0x2A8 0x2AC 0x2B0 0x2B4 0x2B8 0x2BC ) group.long ($2+0xC00)++0x3 line.long 0x0 "REGG3_DOM_$1,Assign domain for SCR registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xB0 0xB1 0xB2 0xB3 0xB4 0xB5 0xB6 0xB7 0xB8 0xB9 0xBA 0xBB 0xBC 0xBD 0xBE 0xBF )(list 0x2C0 0x2C4 0x2C8 0x2CC 0x2D0 0x2D4 0x2D8 0x2DC 0x2E0 0x2E4 0x2E8 0x2EC 0x2F0 0x2F4 0x2F8 0x2FC ) group.long ($2+0xC00)++0x3 line.long 0x0 "REGG3_DOM_$1,Assign domain for SCR registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xC0 0xC1 0xC2 0xC3 0xC4 0xC5 0xC6 0xC7 0xC8 0xC9 0xCA 0xCB 0xCC 0xCD 0xCE 0xCF )(list 0x300 0x304 0x308 0x30C 0x310 0x314 0x318 0x31C 0x320 0x324 0x328 0x32C 0x330 0x334 0x338 0x33C ) group.long ($2+0xC00)++0x3 line.long 0x0 "REGG3_DOM_$1,Assign domain for SCR registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xD0 0xD1 0xD2 0xD3 0xD4 0xD5 0xD6 0xD7 0xD8 0xD9 0xDA 0xDB 0xDC 0xDD 0xDE 0xDF )(list 0x340 0x344 0x348 0x34C 0x350 0x354 0x358 0x35C 0x360 0x364 0x368 0x36C 0x370 0x374 0x378 0x37C ) group.long ($2+0xC00)++0x3 line.long 0x0 "REGG3_DOM_$1,Assign domain for SCR registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xE0 0xE1 0xE2 0xE3 0xE4 0xE5 0xE6 0xE7 0xE8 0xE9 0xEA 0xEB 0xEC 0xED 0xEE 0xEF )(list 0x380 0x384 0x388 0x38C 0x390 0x394 0x398 0x39C 0x3A0 0x3A4 0x3A8 0x3AC 0x3B0 0x3B4 0x3B8 0x3BC ) group.long ($2+0xC00)++0x3 line.long 0x0 "REGG3_DOM_$1,Assign domain for SCR registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xF0 0xF1 0xF2 0xF3 0xF4 0xF5 0xF6 0xF7 0xF8 0xF9 0xFA 0xFB 0xFC 0xFD 0xFE 0xFF )(list 0x3C0 0x3C4 0x3C8 0x3CC 0x3D0 0x3D4 0x3D8 0x3DC 0x3E0 0x3E4 0x3E8 0x3EC 0x3F0 0x3F4 0x3F8 0x3FC ) group.long ($2+0xC00)++0x3 line.long 0x0 "REGG3_DOM_$1,Assign domain for SCR registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x4 0x8 0xC 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C ) group.long ($2+0x1000)++0x3 line.long 0x0 "REGG4_DOM_$1,Assign domain for RSTGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1A 0x1B 0x1C 0x1D 0x1E 0x1F )(list 0x40 0x44 0x48 0x4C 0x50 0x54 0x58 0x5C 0x60 0x64 0x68 0x6C 0x70 0x74 0x78 0x7C ) group.long ($2+0x1000)++0x3 line.long 0x0 "REGG4_DOM_$1,Assign domain for RSTGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x20 0x21 0x22 0x23 0x24 0x25 0x26 0x27 0x28 0x29 0x2A 0x2B 0x2C 0x2D 0x2E 0x2F )(list 0x80 0x84 0x88 0x8C 0x90 0x94 0x98 0x9C 0xA0 0xA4 0xA8 0xAC 0xB0 0xB4 0xB8 0xBC ) group.long ($2+0x1000)++0x3 line.long 0x0 "REGG4_DOM_$1,Assign domain for RSTGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x30 0x31 0x32 0x33 0x34 0x35 0x36 0x37 0x38 0x39 0x3A 0x3B 0x3C 0x3D 0x3E 0x3F )(list 0xC0 0xC4 0xC8 0xCC 0xD0 0xD4 0xD8 0xDC 0xE0 0xE4 0xE8 0xEC 0xF0 0xF4 0xF8 0xFC ) group.long ($2+0x1000)++0x3 line.long 0x0 "REGG4_DOM_$1,Assign domain for RSTGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x40 0x41 0x42 0x43 0x44 0x45 0x46 0x47 0x48 0x49 0x4A 0x4B 0x4C 0x4D 0x4E 0x4F )(list 0x100 0x104 0x108 0x10C 0x110 0x114 0x118 0x11C 0x120 0x124 0x128 0x12C 0x130 0x134 0x138 0x13C ) group.long ($2+0x1000)++0x3 line.long 0x0 "REGG4_DOM_$1,Assign domain for RSTGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x50 0x51 0x52 0x53 0x54 0x55 0x56 0x57 0x58 0x59 0x5A 0x5B 0x5C 0x5D 0x5E 0x5F )(list 0x140 0x144 0x148 0x14C 0x150 0x154 0x158 0x15C 0x160 0x164 0x168 0x16C 0x170 0x174 0x178 0x17C ) group.long ($2+0x1000)++0x3 line.long 0x0 "REGG4_DOM_$1,Assign domain for RSTGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x60 0x61 0x62 0x63 0x64 0x65 0x66 0x67 0x68 0x69 0x6A 0x6B 0x6C 0x6D 0x6E 0x6F )(list 0x180 0x184 0x188 0x18C 0x190 0x194 0x198 0x19C 0x1A0 0x1A4 0x1A8 0x1AC 0x1B0 0x1B4 0x1B8 0x1BC ) group.long ($2+0x1000)++0x3 line.long 0x0 "REGG4_DOM_$1,Assign domain for RSTGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x70 0x71 0x72 0x73 0x74 0x75 0x76 0x77 0x78 0x79 0x7A 0x7B 0x7C 0x7D 0x7E 0x7F )(list 0x1C0 0x1C4 0x1C8 0x1CC 0x1D0 0x1D4 0x1D8 0x1DC 0x1E0 0x1E4 0x1E8 0x1EC 0x1F0 0x1F4 0x1F8 0x1FC ) group.long ($2+0x1000)++0x3 line.long 0x0 "REGG4_DOM_$1,Assign domain for RSTGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x80 0x81 0x82 0x83 0x84 0x85 0x86 0x87 0x88 0x89 0x8A 0x8B 0x8C 0x8D 0x8E 0x8F )(list 0x200 0x204 0x208 0x20C 0x210 0x214 0x218 0x21C 0x220 0x224 0x228 0x22C 0x230 0x234 0x238 0x23C ) group.long ($2+0x1000)++0x3 line.long 0x0 "REGG4_DOM_$1,Assign domain for RSTGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x90 0x91 0x92 0x93 0x94 0x95 0x96 0x97 0x98 0x99 0x9A 0x9B 0x9C 0x9D 0x9E 0x9F )(list 0x240 0x244 0x248 0x24C 0x250 0x254 0x258 0x25C 0x260 0x264 0x268 0x26C 0x270 0x274 0x278 0x27C ) group.long ($2+0x1000)++0x3 line.long 0x0 "REGG4_DOM_$1,Assign domain for RSTGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xA0 0xA1 0xA2 0xA3 0xA4 0xA5 0xA6 0xA7 0xA8 0xA9 0xAA 0xAB 0xAC 0xAD 0xAE 0xAF )(list 0x280 0x284 0x288 0x28C 0x290 0x294 0x298 0x29C 0x2A0 0x2A4 0x2A8 0x2AC 0x2B0 0x2B4 0x2B8 0x2BC ) group.long ($2+0x1000)++0x3 line.long 0x0 "REGG4_DOM_$1,Assign domain for RSTGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xB0 0xB1 0xB2 0xB3 0xB4 0xB5 0xB6 0xB7 0xB8 0xB9 0xBA 0xBB 0xBC 0xBD 0xBE 0xBF )(list 0x2C0 0x2C4 0x2C8 0x2CC 0x2D0 0x2D4 0x2D8 0x2DC 0x2E0 0x2E4 0x2E8 0x2EC 0x2F0 0x2F4 0x2F8 0x2FC ) group.long ($2+0x1000)++0x3 line.long 0x0 "REGG4_DOM_$1,Assign domain for RSTGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xC0 0xC1 0xC2 0xC3 0xC4 0xC5 0xC6 0xC7 0xC8 0xC9 0xCA 0xCB 0xCC 0xCD 0xCE 0xCF )(list 0x300 0x304 0x308 0x30C 0x310 0x314 0x318 0x31C 0x320 0x324 0x328 0x32C 0x330 0x334 0x338 0x33C ) group.long ($2+0x1000)++0x3 line.long 0x0 "REGG4_DOM_$1,Assign domain for RSTGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xD0 0xD1 0xD2 0xD3 0xD4 0xD5 0xD6 0xD7 0xD8 0xD9 0xDA 0xDB 0xDC 0xDD 0xDE 0xDF )(list 0x340 0x344 0x348 0x34C 0x350 0x354 0x358 0x35C 0x360 0x364 0x368 0x36C 0x370 0x374 0x378 0x37C ) group.long ($2+0x1000)++0x3 line.long 0x0 "REGG4_DOM_$1,Assign domain for RSTGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xE0 0xE1 0xE2 0xE3 0xE4 0xE5 0xE6 0xE7 0xE8 0xE9 0xEA 0xEB 0xEC 0xED 0xEE 0xEF )(list 0x380 0x384 0x388 0x38C 0x390 0x394 0x398 0x39C 0x3A0 0x3A4 0x3A8 0x3AC 0x3B0 0x3B4 0x3B8 0x3BC ) group.long ($2+0x1000)++0x3 line.long 0x0 "REGG4_DOM_$1,Assign domain for RSTGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xF0 0xF1 0xF2 0xF3 0xF4 0xF5 0xF6 0xF7 0xF8 0xF9 0xFA 0xFB 0xFC 0xFD 0xFE 0xFF )(list 0x3C0 0x3C4 0x3C8 0x3CC 0x3D0 0x3D4 0x3D8 0x3DC 0x3E0 0x3E4 0x3E8 0x3EC 0x3F0 0x3F4 0x3F8 0x3FC ) group.long ($2+0x1000)++0x3 line.long 0x0 "REGG4_DOM_$1,Assign domain for RSTGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x4 0x8 0xC 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C ) group.long ($2+0x1400)++0x3 line.long 0x0 "REGG5_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1A 0x1B 0x1C 0x1D 0x1E 0x1F )(list 0x40 0x44 0x48 0x4C 0x50 0x54 0x58 0x5C 0x60 0x64 0x68 0x6C 0x70 0x74 0x78 0x7C ) group.long ($2+0x1400)++0x3 line.long 0x0 "REGG5_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x20 0x21 0x22 0x23 0x24 0x25 0x26 0x27 0x28 0x29 0x2A 0x2B 0x2C 0x2D 0x2E 0x2F )(list 0x80 0x84 0x88 0x8C 0x90 0x94 0x98 0x9C 0xA0 0xA4 0xA8 0xAC 0xB0 0xB4 0xB8 0xBC ) group.long ($2+0x1400)++0x3 line.long 0x0 "REGG5_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x30 0x31 0x32 0x33 0x34 0x35 0x36 0x37 0x38 0x39 0x3A 0x3B 0x3C 0x3D 0x3E 0x3F )(list 0xC0 0xC4 0xC8 0xCC 0xD0 0xD4 0xD8 0xDC 0xE0 0xE4 0xE8 0xEC 0xF0 0xF4 0xF8 0xFC ) group.long ($2+0x1400)++0x3 line.long 0x0 "REGG5_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x40 0x41 0x42 0x43 0x44 0x45 0x46 0x47 0x48 0x49 0x4A 0x4B 0x4C 0x4D 0x4E 0x4F )(list 0x100 0x104 0x108 0x10C 0x110 0x114 0x118 0x11C 0x120 0x124 0x128 0x12C 0x130 0x134 0x138 0x13C ) group.long ($2+0x1400)++0x3 line.long 0x0 "REGG5_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x50 0x51 0x52 0x53 0x54 0x55 0x56 0x57 0x58 0x59 0x5A 0x5B 0x5C 0x5D 0x5E 0x5F )(list 0x140 0x144 0x148 0x14C 0x150 0x154 0x158 0x15C 0x160 0x164 0x168 0x16C 0x170 0x174 0x178 0x17C ) group.long ($2+0x1400)++0x3 line.long 0x0 "REGG5_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x60 0x61 0x62 0x63 0x64 0x65 0x66 0x67 0x68 0x69 0x6A 0x6B 0x6C 0x6D 0x6E 0x6F )(list 0x180 0x184 0x188 0x18C 0x190 0x194 0x198 0x19C 0x1A0 0x1A4 0x1A8 0x1AC 0x1B0 0x1B4 0x1B8 0x1BC ) group.long ($2+0x1400)++0x3 line.long 0x0 "REGG5_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x70 0x71 0x72 0x73 0x74 0x75 0x76 0x77 0x78 0x79 0x7A 0x7B 0x7C 0x7D 0x7E 0x7F )(list 0x1C0 0x1C4 0x1C8 0x1CC 0x1D0 0x1D4 0x1D8 0x1DC 0x1E0 0x1E4 0x1E8 0x1EC 0x1F0 0x1F4 0x1F8 0x1FC ) group.long ($2+0x1400)++0x3 line.long 0x0 "REGG5_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x80 0x81 0x82 0x83 0x84 0x85 0x86 0x87 0x88 0x89 0x8A 0x8B 0x8C 0x8D 0x8E 0x8F )(list 0x200 0x204 0x208 0x20C 0x210 0x214 0x218 0x21C 0x220 0x224 0x228 0x22C 0x230 0x234 0x238 0x23C ) group.long ($2+0x1400)++0x3 line.long 0x0 "REGG5_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x90 0x91 0x92 0x93 0x94 0x95 0x96 0x97 0x98 0x99 0x9A 0x9B 0x9C 0x9D 0x9E 0x9F )(list 0x240 0x244 0x248 0x24C 0x250 0x254 0x258 0x25C 0x260 0x264 0x268 0x26C 0x270 0x274 0x278 0x27C ) group.long ($2+0x1400)++0x3 line.long 0x0 "REGG5_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xA0 0xA1 0xA2 0xA3 0xA4 0xA5 0xA6 0xA7 0xA8 0xA9 0xAA 0xAB 0xAC 0xAD 0xAE 0xAF )(list 0x280 0x284 0x288 0x28C 0x290 0x294 0x298 0x29C 0x2A0 0x2A4 0x2A8 0x2AC 0x2B0 0x2B4 0x2B8 0x2BC ) group.long ($2+0x1400)++0x3 line.long 0x0 "REGG5_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xB0 0xB1 0xB2 0xB3 0xB4 0xB5 0xB6 0xB7 0xB8 0xB9 0xBA 0xBB 0xBC 0xBD 0xBE 0xBF )(list 0x2C0 0x2C4 0x2C8 0x2CC 0x2D0 0x2D4 0x2D8 0x2DC 0x2E0 0x2E4 0x2E8 0x2EC 0x2F0 0x2F4 0x2F8 0x2FC ) group.long ($2+0x1400)++0x3 line.long 0x0 "REGG5_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xC0 0xC1 0xC2 0xC3 0xC4 0xC5 0xC6 0xC7 0xC8 0xC9 0xCA 0xCB 0xCC 0xCD 0xCE 0xCF )(list 0x300 0x304 0x308 0x30C 0x310 0x314 0x318 0x31C 0x320 0x324 0x328 0x32C 0x330 0x334 0x338 0x33C ) group.long ($2+0x1400)++0x3 line.long 0x0 "REGG5_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xD0 0xD1 0xD2 0xD3 0xD4 0xD5 0xD6 0xD7 0xD8 0xD9 0xDA 0xDB 0xDC 0xDD 0xDE 0xDF )(list 0x340 0x344 0x348 0x34C 0x350 0x354 0x358 0x35C 0x360 0x364 0x368 0x36C 0x370 0x374 0x378 0x37C ) group.long ($2+0x1400)++0x3 line.long 0x0 "REGG5_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xE0 0xE1 0xE2 0xE3 0xE4 0xE5 0xE6 0xE7 0xE8 0xE9 0xEA 0xEB 0xEC 0xED 0xEE 0xEF )(list 0x380 0x384 0x388 0x38C 0x390 0x394 0x398 0x39C 0x3A0 0x3A4 0x3A8 0x3AC 0x3B0 0x3B4 0x3B8 0x3BC ) group.long ($2+0x1400)++0x3 line.long 0x0 "REGG5_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xF0 0xF1 0xF2 0xF3 0xF4 0xF5 0xF6 0xF7 0xF8 0xF9 0xFA 0xFB 0xFC 0xFD 0xFE 0xFF )(list 0x3C0 0x3C4 0x3C8 0x3CC 0x3D0 0x3D4 0x3D8 0x3DC 0x3E0 0x3E4 0x3E8 0x3EC 0x3F0 0x3F4 0x3F8 0x3FC ) group.long ($2+0x1400)++0x3 line.long 0x0 "REGG5_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x4 0x8 0xC 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C ) group.long ($2+0x1800)++0x3 line.long 0x0 "REGG6_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1A 0x1B 0x1C 0x1D 0x1E 0x1F )(list 0x40 0x44 0x48 0x4C 0x50 0x54 0x58 0x5C 0x60 0x64 0x68 0x6C 0x70 0x74 0x78 0x7C ) group.long ($2+0x1800)++0x3 line.long 0x0 "REGG6_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x20 0x21 0x22 0x23 0x24 0x25 0x26 0x27 0x28 0x29 0x2A 0x2B 0x2C 0x2D 0x2E 0x2F )(list 0x80 0x84 0x88 0x8C 0x90 0x94 0x98 0x9C 0xA0 0xA4 0xA8 0xAC 0xB0 0xB4 0xB8 0xBC ) group.long ($2+0x1800)++0x3 line.long 0x0 "REGG6_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x30 0x31 0x32 0x33 0x34 0x35 0x36 0x37 0x38 0x39 0x3A 0x3B 0x3C 0x3D 0x3E 0x3F )(list 0xC0 0xC4 0xC8 0xCC 0xD0 0xD4 0xD8 0xDC 0xE0 0xE4 0xE8 0xEC 0xF0 0xF4 0xF8 0xFC ) group.long ($2+0x1800)++0x3 line.long 0x0 "REGG6_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x40 0x41 0x42 0x43 0x44 0x45 0x46 0x47 0x48 0x49 0x4A 0x4B 0x4C 0x4D 0x4E 0x4F )(list 0x100 0x104 0x108 0x10C 0x110 0x114 0x118 0x11C 0x120 0x124 0x128 0x12C 0x130 0x134 0x138 0x13C ) group.long ($2+0x1800)++0x3 line.long 0x0 "REGG6_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x50 0x51 0x52 0x53 0x54 0x55 0x56 0x57 0x58 0x59 0x5A 0x5B 0x5C 0x5D 0x5E 0x5F )(list 0x140 0x144 0x148 0x14C 0x150 0x154 0x158 0x15C 0x160 0x164 0x168 0x16C 0x170 0x174 0x178 0x17C ) group.long ($2+0x1800)++0x3 line.long 0x0 "REGG6_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x60 0x61 0x62 0x63 0x64 0x65 0x66 0x67 0x68 0x69 0x6A 0x6B 0x6C 0x6D 0x6E 0x6F )(list 0x180 0x184 0x188 0x18C 0x190 0x194 0x198 0x19C 0x1A0 0x1A4 0x1A8 0x1AC 0x1B0 0x1B4 0x1B8 0x1BC ) group.long ($2+0x1800)++0x3 line.long 0x0 "REGG6_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x70 0x71 0x72 0x73 0x74 0x75 0x76 0x77 0x78 0x79 0x7A 0x7B 0x7C 0x7D 0x7E 0x7F )(list 0x1C0 0x1C4 0x1C8 0x1CC 0x1D0 0x1D4 0x1D8 0x1DC 0x1E0 0x1E4 0x1E8 0x1EC 0x1F0 0x1F4 0x1F8 0x1FC ) group.long ($2+0x1800)++0x3 line.long 0x0 "REGG6_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x80 0x81 0x82 0x83 0x84 0x85 0x86 0x87 0x88 0x89 0x8A 0x8B 0x8C 0x8D 0x8E 0x8F )(list 0x200 0x204 0x208 0x20C 0x210 0x214 0x218 0x21C 0x220 0x224 0x228 0x22C 0x230 0x234 0x238 0x23C ) group.long ($2+0x1800)++0x3 line.long 0x0 "REGG6_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x90 0x91 0x92 0x93 0x94 0x95 0x96 0x97 0x98 0x99 0x9A 0x9B 0x9C 0x9D 0x9E 0x9F )(list 0x240 0x244 0x248 0x24C 0x250 0x254 0x258 0x25C 0x260 0x264 0x268 0x26C 0x270 0x274 0x278 0x27C ) group.long ($2+0x1800)++0x3 line.long 0x0 "REGG6_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xA0 0xA1 0xA2 0xA3 0xA4 0xA5 0xA6 0xA7 0xA8 0xA9 0xAA 0xAB 0xAC 0xAD 0xAE 0xAF )(list 0x280 0x284 0x288 0x28C 0x290 0x294 0x298 0x29C 0x2A0 0x2A4 0x2A8 0x2AC 0x2B0 0x2B4 0x2B8 0x2BC ) group.long ($2+0x1800)++0x3 line.long 0x0 "REGG6_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xB0 0xB1 0xB2 0xB3 0xB4 0xB5 0xB6 0xB7 0xB8 0xB9 0xBA 0xBB 0xBC 0xBD 0xBE 0xBF )(list 0x2C0 0x2C4 0x2C8 0x2CC 0x2D0 0x2D4 0x2D8 0x2DC 0x2E0 0x2E4 0x2E8 0x2EC 0x2F0 0x2F4 0x2F8 0x2FC ) group.long ($2+0x1800)++0x3 line.long 0x0 "REGG6_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xC0 0xC1 0xC2 0xC3 0xC4 0xC5 0xC6 0xC7 0xC8 0xC9 0xCA 0xCB 0xCC 0xCD 0xCE 0xCF )(list 0x300 0x304 0x308 0x30C 0x310 0x314 0x318 0x31C 0x320 0x324 0x328 0x32C 0x330 0x334 0x338 0x33C ) group.long ($2+0x1800)++0x3 line.long 0x0 "REGG6_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xD0 0xD1 0xD2 0xD3 0xD4 0xD5 0xD6 0xD7 0xD8 0xD9 0xDA 0xDB 0xDC 0xDD 0xDE 0xDF )(list 0x340 0x344 0x348 0x34C 0x350 0x354 0x358 0x35C 0x360 0x364 0x368 0x36C 0x370 0x374 0x378 0x37C ) group.long ($2+0x1800)++0x3 line.long 0x0 "REGG6_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xE0 0xE1 0xE2 0xE3 0xE4 0xE5 0xE6 0xE7 0xE8 0xE9 0xEA 0xEB 0xEC 0xED 0xEE 0xEF )(list 0x380 0x384 0x388 0x38C 0x390 0x394 0x398 0x39C 0x3A0 0x3A4 0x3A8 0x3AC 0x3B0 0x3B4 0x3B8 0x3BC ) group.long ($2+0x1800)++0x3 line.long 0x0 "REGG6_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xF0 0xF1 0xF2 0xF3 0xF4 0xF5 0xF6 0xF7 0xF8 0xF9 0xFA 0xFB 0xFC 0xFD 0xFE 0xFF )(list 0x3C0 0x3C4 0x3C8 0x3CC 0x3D0 0x3D4 0x3D8 0x3DC 0x3E0 0x3E4 0x3E8 0x3EC 0x3F0 0x3F4 0x3F8 0x3FC ) group.long ($2+0x1800)++0x3 line.long 0x0 "REGG6_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x4 0x8 0xC 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C ) group.long ($2+0x1C00)++0x3 line.long 0x0 "REGG7_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1A 0x1B 0x1C 0x1D 0x1E 0x1F )(list 0x40 0x44 0x48 0x4C 0x50 0x54 0x58 0x5C 0x60 0x64 0x68 0x6C 0x70 0x74 0x78 0x7C ) group.long ($2+0x1C00)++0x3 line.long 0x0 "REGG7_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x20 0x21 0x22 0x23 0x24 0x25 0x26 0x27 0x28 0x29 0x2A 0x2B 0x2C 0x2D 0x2E 0x2F )(list 0x80 0x84 0x88 0x8C 0x90 0x94 0x98 0x9C 0xA0 0xA4 0xA8 0xAC 0xB0 0xB4 0xB8 0xBC ) group.long ($2+0x1C00)++0x3 line.long 0x0 "REGG7_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x30 0x31 0x32 0x33 0x34 0x35 0x36 0x37 0x38 0x39 0x3A 0x3B 0x3C 0x3D 0x3E 0x3F )(list 0xC0 0xC4 0xC8 0xCC 0xD0 0xD4 0xD8 0xDC 0xE0 0xE4 0xE8 0xEC 0xF0 0xF4 0xF8 0xFC ) group.long ($2+0x1C00)++0x3 line.long 0x0 "REGG7_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x40 0x41 0x42 0x43 0x44 0x45 0x46 0x47 0x48 0x49 0x4A 0x4B 0x4C 0x4D 0x4E 0x4F )(list 0x100 0x104 0x108 0x10C 0x110 0x114 0x118 0x11C 0x120 0x124 0x128 0x12C 0x130 0x134 0x138 0x13C ) group.long ($2+0x1C00)++0x3 line.long 0x0 "REGG7_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x50 0x51 0x52 0x53 0x54 0x55 0x56 0x57 0x58 0x59 0x5A 0x5B 0x5C 0x5D 0x5E 0x5F )(list 0x140 0x144 0x148 0x14C 0x150 0x154 0x158 0x15C 0x160 0x164 0x168 0x16C 0x170 0x174 0x178 0x17C ) group.long ($2+0x1C00)++0x3 line.long 0x0 "REGG7_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x60 0x61 0x62 0x63 0x64 0x65 0x66 0x67 0x68 0x69 0x6A 0x6B 0x6C 0x6D 0x6E 0x6F )(list 0x180 0x184 0x188 0x18C 0x190 0x194 0x198 0x19C 0x1A0 0x1A4 0x1A8 0x1AC 0x1B0 0x1B4 0x1B8 0x1BC ) group.long ($2+0x1C00)++0x3 line.long 0x0 "REGG7_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x70 0x71 0x72 0x73 0x74 0x75 0x76 0x77 0x78 0x79 0x7A 0x7B 0x7C 0x7D 0x7E 0x7F )(list 0x1C0 0x1C4 0x1C8 0x1CC 0x1D0 0x1D4 0x1D8 0x1DC 0x1E0 0x1E4 0x1E8 0x1EC 0x1F0 0x1F4 0x1F8 0x1FC ) group.long ($2+0x1C00)++0x3 line.long 0x0 "REGG7_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x80 0x81 0x82 0x83 0x84 0x85 0x86 0x87 0x88 0x89 0x8A 0x8B 0x8C 0x8D 0x8E 0x8F )(list 0x200 0x204 0x208 0x20C 0x210 0x214 0x218 0x21C 0x220 0x224 0x228 0x22C 0x230 0x234 0x238 0x23C ) group.long ($2+0x1C00)++0x3 line.long 0x0 "REGG7_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x90 0x91 0x92 0x93 0x94 0x95 0x96 0x97 0x98 0x99 0x9A 0x9B 0x9C 0x9D 0x9E 0x9F )(list 0x240 0x244 0x248 0x24C 0x250 0x254 0x258 0x25C 0x260 0x264 0x268 0x26C 0x270 0x274 0x278 0x27C ) group.long ($2+0x1C00)++0x3 line.long 0x0 "REGG7_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xA0 0xA1 0xA2 0xA3 0xA4 0xA5 0xA6 0xA7 0xA8 0xA9 0xAA 0xAB 0xAC 0xAD 0xAE 0xAF )(list 0x280 0x284 0x288 0x28C 0x290 0x294 0x298 0x29C 0x2A0 0x2A4 0x2A8 0x2AC 0x2B0 0x2B4 0x2B8 0x2BC ) group.long ($2+0x1C00)++0x3 line.long 0x0 "REGG7_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xB0 0xB1 0xB2 0xB3 0xB4 0xB5 0xB6 0xB7 0xB8 0xB9 0xBA 0xBB 0xBC 0xBD 0xBE 0xBF )(list 0x2C0 0x2C4 0x2C8 0x2CC 0x2D0 0x2D4 0x2D8 0x2DC 0x2E0 0x2E4 0x2E8 0x2EC 0x2F0 0x2F4 0x2F8 0x2FC ) group.long ($2+0x1C00)++0x3 line.long 0x0 "REGG7_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xC0 0xC1 0xC2 0xC3 0xC4 0xC5 0xC6 0xC7 0xC8 0xC9 0xCA 0xCB 0xCC 0xCD 0xCE 0xCF )(list 0x300 0x304 0x308 0x30C 0x310 0x314 0x318 0x31C 0x320 0x324 0x328 0x32C 0x330 0x334 0x338 0x33C ) group.long ($2+0x1C00)++0x3 line.long 0x0 "REGG7_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xD0 0xD1 0xD2 0xD3 0xD4 0xD5 0xD6 0xD7 0xD8 0xD9 0xDA 0xDB 0xDC 0xDD 0xDE 0xDF )(list 0x340 0x344 0x348 0x34C 0x350 0x354 0x358 0x35C 0x360 0x364 0x368 0x36C 0x370 0x374 0x378 0x37C ) group.long ($2+0x1C00)++0x3 line.long 0x0 "REGG7_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xE0 0xE1 0xE2 0xE3 0xE4 0xE5 0xE6 0xE7 0xE8 0xE9 0xEA 0xEB 0xEC 0xED 0xEE 0xEF )(list 0x380 0x384 0x388 0x38C 0x390 0x394 0x398 0x39C 0x3A0 0x3A4 0x3A8 0x3AC 0x3B0 0x3B4 0x3B8 0x3BC ) group.long ($2+0x1C00)++0x3 line.long 0x0 "REGG7_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xF0 0xF1 0xF2 0xF3 0xF4 0xF5 0xF6 0xF7 0xF8 0xF9 0xFA 0xFB 0xFC 0xFD 0xFE 0xFF )(list 0x3C0 0x3C4 0x3C8 0x3CC 0x3D0 0x3D4 0x3D8 0x3DC 0x3E0 0x3E4 0x3E8 0x3EC 0x3F0 0x3F4 0x3F8 0x3FC ) group.long ($2+0x1C00)++0x3 line.long 0x0 "REGG7_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end group.long 0x2000++0x17 line.long 0x0 "GLB_CTL,This register provides global enable settings for permission control." bitfld.long 0x0 5. "DOM_CFG_LOCK,Lock write for DOM_CFG_MODE bit." "0,1" bitfld.long 0x0 4. "DOM_CFG_MODE,When enabled all the source setting can be configured by master from domain 0 if it is not locked. When disabled only resource manager can configure the permission of the resource." "0,1" bitfld.long 0x0 3. "PERCK_DIS_LOCK,Lock write for PERCK_DIS" "0,1" bitfld.long 0x0 2. "PERCK_DIS,All the permission check disable." "0,1" newline bitfld.long 0x0 1. "DOM_PRO_LOCK,Lock write for DOM_PRO_EN bit." "0,1" bitfld.long 0x0 0. "DOM_PRO_EN,When disabled no domain access permission check" "0,1" line.long 0x4 "RES_MGR,Resource manager register. This regster is used to assign resource manager for global resource access control" bitfld.long 0x4 17. "MID_LOCK,Lock write for MID_EN and MID_LOW and MID_HIG registers." "0,1" bitfld.long 0x4 16. "MID_EN,Master ID check enable" "0,1" bitfld.long 0x4 15. "PRI_PER_LOCK,Lock write for PRI_PER and PRI_PER_EN" "0,1" bitfld.long 0x4 13.--14. "PRI_PER,Resource manager privileged access permission. bit0 for privileged access bit1 for user access" "0,1,2,3" newline bitfld.long 0x4 12. "PRI_PER_EN,Resource manager privileged access permission enable." "0,1" bitfld.long 0x4 11. "SEC_PER_LOCK,Lock for SEC_PER and SEC_PER_LOCK" "0,1" bitfld.long 0x4 9.--10. "SEC_PER,Resource manager secure access permission. bit 0 for secure access bit 1 for non-secure access" "0,1,2,3" bitfld.long 0x4 8. "SEC_PER_EN,Resource manager secure permission enable" "0,1" bitfld.long 0x4 7. "DID_LOCK,Lock write for DID_EN and DID" "0,1" newline hexmask.long.byte 0x4 3.--6. 1. "DID,Resource manager domain ID" bitfld.long 0x4 2. "DID_EN,Resource manager Domain ID enable" "0,1" bitfld.long 0x4 1. "RES_MGR_EN_LOCK,Lock for RES_MGR_EN" "0,1" bitfld.long 0x4 0. "RES_MGR_EN,Resource manager enable. When the bit is disable there is no resource manager." "0,1" line.long 0x8 "RES_MGR_MA0,This register is used to assign master 0~31 as resource manager." hexmask.long 0x8 0.--31. 1. "MID,Assign master 0~31 for resource manager" line.long 0xC "RES_MGR_MA1,This register is used to assign master 32~63 as resource manager." hexmask.long 0xC 0.--31. 1. "MID,Indicate if master 32~63 is resource manager." line.long 0x10 "RES_MGR_MA2,This register is used to assign master 64~95 as resource manager." hexmask.long 0x10 0.--31. 1. "MID,Indicate if master 64~95 is resource manager." line.long 0x14 "RES_MGR_MA3,This register is used to assign master 96~127 as resource manager." hexmask.long 0x14 0.--31. 1. "MID,Indicate if master 96~127 is resource manager." repeat 8. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 )(list 0x0 0x14 0x28 0x3C 0x50 0x64 0x78 0x8C ) group.long ($2+0x2100)++0x3 line.long 0x0 "GRP_MGR_$1,Group Manager Register. This register is used to assign group manager for each domain" bitfld.long 0x0 17. "MID_LOCK,Lock write for MID_EN and MID_LOW and MID_HIG registers." "0,1" bitfld.long 0x0 16. "MID_EN,Master ID check enable" "0,1" bitfld.long 0x0 15. "PRI_PER_LOCK,Lock write for PRI_PER and PRI_PER_EN" "0,1" bitfld.long 0x0 13.--14. "PRI_PER,Group manager privileged access permission. bit0 for privileged access bit1 for user access" "0,1,2,3" newline bitfld.long 0x0 12. "PRI_PER_EN,Group manager privileged access permission enable." "0,1" bitfld.long 0x0 11. "SEC_PER_LOCK,Lock for SEC_PER and SEC_PER_LOCK" "0,1" bitfld.long 0x0 9.--10. "SEC_PER,Group manager secure access permission. bit 0 for secure access bit 1 for non-secure access" "0,1,2,3" bitfld.long 0x0 8. "SEC_PER_EN,Group manager secure permission enable" "0,1" bitfld.long 0x0 7. "DID_LOCK,Lock write for DID_EN and DID" "0,1" newline hexmask.long.byte 0x0 3.--6. 1. "DID,Group manager domain ID" bitfld.long 0x0 2. "DID_EN,Group manager Domain ID enable" "0,1" bitfld.long 0x0 1. "GRP_MGR_EN_LOCK,Lock write for GPR_MGR_EN" "0,1" bitfld.long 0x0 0. "GRP_MGR_EN,Group manager enable. When the bit is disable there is no resource manager." "0,1" repeat.end repeat 8. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 )(list 0x0 0x14 0x28 0x3C 0x50 0x64 0x78 0x8C ) group.long ($2+0x2104)++0x3 line.long 0x0 "GRP_MGR_MA0_$1,Assign master 0~31 for group manager 0" hexmask.long 0x0 0.--31. 1. "MID,Assign master 0~31 for resource manager" repeat.end repeat 8. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 )(list 0x0 0x14 0x28 0x3C 0x50 0x64 0x78 0x8C ) group.long ($2+0x2108)++0x3 line.long 0x0 "GRP_MGR_MA1_$1,Assign master 32~63 for group manager 0" hexmask.long 0x0 0.--31. 1. "MID,Indicate if master 32~63 is resource manager." repeat.end repeat 8. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 )(list 0x0 0x14 0x28 0x3C 0x50 0x64 0x78 0x8C ) group.long ($2+0x210C)++0x3 line.long 0x0 "GRP_MGR_MA2_$1,Assign master 64~95 for group manager 0" hexmask.long 0x0 0.--31. 1. "MID,Indicate if master 64~95 is resource manager." repeat.end repeat 8. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 )(list 0x0 0x14 0x28 0x3C 0x50 0x64 0x78 0x8C ) group.long ($2+0x2110)++0x3 line.long 0x0 "GRP_MGR_MA3_$1,Assign master 96~127 for group manager 0" hexmask.long 0x0 0.--31. 1. "MID,Indicate if master 96~127 is resource manager." repeat.end group.long 0x2200++0x3 line.long 0x0 "DOM_GID_0,Indicate which group domain 0 belong to" bitfld.long 0x0 3. "LOCK,Lock write for GID" "0,1" bitfld.long 0x0 0.--2. "GID,Group ID" "0,1,2,3,4,5,6,7" repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x18 0x30 0x48 0x60 0x78 0x90 0xA8 0xC0 0xD8 0xF0 0x108 0x120 0x138 0x150 0x168 ) group.long ($2+0x2204)++0x3 line.long 0x0 "DOM_OWN_$1,Assign owner for function domain 0." bitfld.long 0x0 17. "MID_LOCK,Lock write for MID_EN and MID_LOW and MID_HIG registers." "0,1" bitfld.long 0x0 16. "MID_EN,Master ID check enable" "0,1" bitfld.long 0x0 15. "PRI_PER_LOCK,Lock write for PRI_PER and PRI_PER_EN" "0,1" bitfld.long 0x0 13.--14. "PRI_PER,Group manager privileged access permission. bit0 for privileged access bit1 for user access" "0,1,2,3" newline bitfld.long 0x0 12. "PRI_PER_EN,Group manager privileged access permission enable." "0,1" bitfld.long 0x0 11. "SEC_PER_LOCK,Lock for SEC_PER and SEC_PER_LOCK" "0,1" bitfld.long 0x0 9.--10. "SEC_PER,Domain owner secure access permission. bit 0 for secure access bit 1 for non-secure access" "0,1,2,3" bitfld.long 0x0 8. "SEC_PER_EN,Domain owner secure permission enable" "0,1" newline bitfld.long 0x0 1. "DOM_OWN_EN_LOCK,Lock for DOM_OWN_EN" "0,1" bitfld.long 0x0 0. "DOM_OWN_EN,Domain owner enable. When the bit is disable there is no domain owner." "0,1" repeat.end repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x18 0x30 0x48 0x60 0x78 0x90 0xA8 0xC0 0xD8 0xF0 0x108 0x120 0x138 0x150 0x168 ) group.long ($2+0x2208)++0x3 line.long 0x0 "DOM_OWN_MA0_$1,Assign master 0~31 for domain owner 0" hexmask.long 0x0 0.--31. 1. "MID,Assign master 0~31 for resource manager" repeat.end repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x18 0x30 0x48 0x60 0x78 0x90 0xA8 0xC0 0xD8 0xF0 0x108 0x120 0x138 0x150 0x168 ) group.long ($2+0x220C)++0x3 line.long 0x0 "DOM_OWN_MA1_$1,Assign master 32~63 for domain owner 0" hexmask.long 0x0 0.--31. 1. "MID,Indicate if master 32~63 is resource manager." repeat.end repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x18 0x30 0x48 0x60 0x78 0x90 0xA8 0xC0 0xD8 0xF0 0x108 0x120 0x138 0x150 0x168 ) group.long ($2+0x2210)++0x3 line.long 0x0 "DOM_OWN_MA2_$1,Assign master 64~95 for domain owner 0" hexmask.long 0x0 0.--31. 1. "MID,Indicate if master 64~95 is resource manager." repeat.end repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x18 0x30 0x48 0x60 0x78 0x90 0xA8 0xC0 0xD8 0xF0 0x108 0x120 0x138 0x150 0x168 ) group.long ($2+0x2214)++0x3 line.long 0x0 "DOM_OWN_MA3_$1,Assign master 96~127 for domain owner 0" hexmask.long 0x0 0.--31. 1. "MID,Indicate if master 96~127 is resource manager." repeat.end group.long 0x2218++0x3 line.long 0x0 "DOM_GID_1,Indicate which group domain 1 belong to" bitfld.long 0x0 3. "LOCK,Lock write for GID" "0,1" bitfld.long 0x0 0.--2. "GID,Group ID" "0,1,2,3,4,5,6,7" group.long 0x2230++0x3 line.long 0x0 "DOM_GID_2,Indicate which group domain 2 belong to" bitfld.long 0x0 3. "LOCK,Lock write for GID" "0,1" bitfld.long 0x0 0.--2. "GID,Group ID" "0,1,2,3,4,5,6,7" group.long 0x2248++0x3 line.long 0x0 "DOM_GID_3,Indicate which group domain 3 belong to" bitfld.long 0x0 3. "LOCK,Lock write for GID" "0,1" bitfld.long 0x0 0.--2. "GID,Group ID" "0,1,2,3,4,5,6,7" group.long 0x2260++0x3 line.long 0x0 "DOM_GID_4,Indicate which group domain 4 belong to" bitfld.long 0x0 3. "LOCK,Lock write for GID" "0,1" bitfld.long 0x0 0.--2. "GID,Group ID" "0,1,2,3,4,5,6,7" group.long 0x2278++0x3 line.long 0x0 "DOM_GID_5,Indicate which group domain 5 belong to" bitfld.long 0x0 3. "LOCK,Lock write for GID" "0,1" bitfld.long 0x0 0.--2. "GID,Group ID" "0,1,2,3,4,5,6,7" group.long 0x2290++0x3 line.long 0x0 "DOM_GID_6,Indicate which group domain 6 belong to" bitfld.long 0x0 3. "LOCK,Lock write for GID" "0,1" bitfld.long 0x0 0.--2. "GID,Group ID" "0,1,2,3,4,5,6,7" group.long 0x22A8++0x3 line.long 0x0 "DOM_GID_7,Indicate which group domain 7 belong to" bitfld.long 0x0 3. "LOCK,Lock write for GID" "0,1" bitfld.long 0x0 0.--2. "GID,Group ID" "0,1,2,3,4,5,6,7" group.long 0x22C0++0x3 line.long 0x0 "DOM_GID_8,Indicate which group domain 8 belong to" bitfld.long 0x0 3. "LOCK,Lock write for GID" "0,1" bitfld.long 0x0 0.--2. "GID,Group ID" "0,1,2,3,4,5,6,7" group.long 0x22D8++0x3 line.long 0x0 "DOM_GID_9,Indicate which group domain 9 belong to" bitfld.long 0x0 3. "LOCK,Lock write for GID" "0,1" bitfld.long 0x0 0.--2. "GID,Group ID" "0,1,2,3,4,5,6,7" group.long 0x22F0++0x3 line.long 0x0 "DOM_GID_10,Indicate which group domain 10 belong to" bitfld.long 0x0 3. "LOCK,Lock write for GID" "0,1" bitfld.long 0x0 0.--2. "GID,Group ID" "0,1,2,3,4,5,6,7" group.long 0x2308++0x3 line.long 0x0 "DOM_GID_11,Indicate which group domain 11 belong to" bitfld.long 0x0 3. "LOCK,Lock write for GID" "0,1" bitfld.long 0x0 0.--2. "GID,Group ID" "0,1,2,3,4,5,6,7" group.long 0x2320++0x3 line.long 0x0 "DOM_GID_12,Indicate which group domain 12 belong to" bitfld.long 0x0 3. "LOCK,Lock write for GID" "0,1" bitfld.long 0x0 0.--2. "GID,Group ID" "0,1,2,3,4,5,6,7" group.long 0x2338++0x3 line.long 0x0 "DOM_GID_13,Indicate which group domain 13 belong to" bitfld.long 0x0 3. "LOCK,Lock write for GID" "0,1" bitfld.long 0x0 0.--2. "GID,Group ID" "0,1,2,3,4,5,6,7" group.long 0x2350++0x3 line.long 0x0 "DOM_GID_14,Indicate which group domain 14 belong to" bitfld.long 0x0 3. "LOCK,Lock write for GID" "0,1" bitfld.long 0x0 0.--2. "GID,Group ID" "0,1,2,3,4,5,6,7" group.long 0x2368++0x3 line.long 0x0 "DOM_GID_15,Indicate which group domain 15 belong to" bitfld.long 0x0 3. "LOCK,Lock write for GID" "0,1" bitfld.long 0x0 0.--2. "GID,Group ID" "0,1,2,3,4,5,6,7" repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x34 0x68 0x9C 0xD0 0x104 0x138 0x16C 0x1A0 0x1D4 0x208 0x23C 0x270 0x2A4 0x2D8 0x30C ) group.long ($2+0x2400)++0x3 line.long 0x0 "DOM_PER0_$1,Domain Permission Control. It can be only configured by resource manager and domain owner." bitfld.long 0x0 31. "DOM7_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 29.--30. "DOM7_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 28. "DOM7_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 27. "DOM6_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 25.--26. "DOM6_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" newline bitfld.long 0x0 24. "DOM6_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 23. "DOM5_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 21.--22. "DOM5_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 20. "DOM5_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 19. "DOM4_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" newline bitfld.long 0x0 17.--18. "DOM4_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM4_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 15. "DOM3_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 13.--14. "DOM3_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 12. "DOM3_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" newline bitfld.long 0x0 11. "DOM2_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 9.--10. "DOM2_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM2_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 7. "DOM1_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 5.--6. "DOM1_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" newline bitfld.long 0x0 4. "DOM1_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 3. "DOM0_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 1.--2. "DOM0_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM0_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" repeat.end repeat 16. (list 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1A 0x1B 0x1C 0x1D 0x1E 0x1F )(list 0x340 0x374 0x3A8 0x3DC 0x410 0x444 0x478 0x4AC 0x4E0 0x514 0x548 0x57C 0x5B0 0x5E4 0x618 0x64C ) group.long ($2+0x2400)++0x3 line.long 0x0 "DOM_PER0_$1,Domain Permission Control. It can be only configured by resource manager and domain owner." bitfld.long 0x0 31. "DOM7_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 29.--30. "DOM7_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 28. "DOM7_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 27. "DOM6_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 25.--26. "DOM6_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" newline bitfld.long 0x0 24. "DOM6_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 23. "DOM5_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 21.--22. "DOM5_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 20. "DOM5_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 19. "DOM4_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" newline bitfld.long 0x0 17.--18. "DOM4_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM4_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 15. "DOM3_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 13.--14. "DOM3_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 12. "DOM3_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" newline bitfld.long 0x0 11. "DOM2_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 9.--10. "DOM2_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM2_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 7. "DOM1_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 5.--6. "DOM1_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" newline bitfld.long 0x0 4. "DOM1_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 3. "DOM0_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 1.--2. "DOM0_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM0_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" repeat.end repeat 16. (list 0x20 0x21 0x22 0x23 0x24 0x25 0x26 0x27 0x28 0x29 0x2A 0x2B 0x2C 0x2D 0x2E 0x2F )(list 0x680 0x6B4 0x6E8 0x71C 0x750 0x784 0x7B8 0x7EC 0x820 0x854 0x888 0x8BC 0x8F0 0x924 0x958 0x98C ) group.long ($2+0x2400)++0x3 line.long 0x0 "DOM_PER0_$1,Domain Permission Control. It can be only configured by resource manager and domain owner." bitfld.long 0x0 31. "DOM7_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 29.--30. "DOM7_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 28. "DOM7_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 27. "DOM6_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 25.--26. "DOM6_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" newline bitfld.long 0x0 24. "DOM6_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 23. "DOM5_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 21.--22. "DOM5_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 20. "DOM5_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 19. "DOM4_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" newline bitfld.long 0x0 17.--18. "DOM4_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM4_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 15. "DOM3_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 13.--14. "DOM3_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 12. "DOM3_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" newline bitfld.long 0x0 11. "DOM2_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 9.--10. "DOM2_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM2_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 7. "DOM1_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 5.--6. "DOM1_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" newline bitfld.long 0x0 4. "DOM1_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 3. "DOM0_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 1.--2. "DOM0_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM0_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" repeat.end repeat 16. (list 0x30 0x31 0x32 0x33 0x34 0x35 0x36 0x37 0x38 0x39 0x3A 0x3B 0x3C 0x3D 0x3E 0x3F )(list 0x9C0 0x9F4 0xA28 0xA5C 0xA90 0xAC4 0xAF8 0xB2C 0xB60 0xB94 0xBC8 0xBFC 0xC30 0xC64 0xC98 0xCCC ) group.long ($2+0x2400)++0x3 line.long 0x0 "DOM_PER0_$1,Domain Permission Control. It can be only configured by resource manager and domain owner." bitfld.long 0x0 31. "DOM7_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 29.--30. "DOM7_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 28. "DOM7_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 27. "DOM6_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 25.--26. "DOM6_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" newline bitfld.long 0x0 24. "DOM6_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 23. "DOM5_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 21.--22. "DOM5_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 20. "DOM5_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 19. "DOM4_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" newline bitfld.long 0x0 17.--18. "DOM4_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM4_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 15. "DOM3_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 13.--14. "DOM3_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 12. "DOM3_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" newline bitfld.long 0x0 11. "DOM2_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 9.--10. "DOM2_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM2_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 7. "DOM1_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 5.--6. "DOM1_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" newline bitfld.long 0x0 4. "DOM1_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 3. "DOM0_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 1.--2. "DOM0_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM0_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" repeat.end repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x34 0x68 0x9C 0xD0 0x104 0x138 0x16C 0x1A0 0x1D4 0x208 0x23C 0x270 0x2A4 0x2D8 0x30C ) group.long ($2+0x2404)++0x3 line.long 0x0 "DOM_PER1_$1,Domain Permission Control. It can be only configured by resource manager and domain owner." bitfld.long 0x0 31. "DOM15_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 29.--30. "DOM15_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 28. "DOM15_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 27. "DOM14_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 25.--26. "DOM14_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" newline bitfld.long 0x0 24. "DOM14_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 23. "DOM13_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 21.--22. "DOM13_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 20. "DOM13_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 19. "DOM12_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" newline bitfld.long 0x0 17.--18. "DOM12_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM12_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 15. "DOM11_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 13.--14. "DOM11_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 12. "DOM11_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" newline bitfld.long 0x0 11. "DOM10_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 9.--10. "DOM10_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM10_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 7. "DOM9_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 5.--6. "DOM9_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" newline bitfld.long 0x0 4. "DOM9_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 3. "DOM8_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 1.--2. "DOM8_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM8_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" repeat.end repeat 16. (list 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1A 0x1B 0x1C 0x1D 0x1E 0x1F )(list 0x340 0x374 0x3A8 0x3DC 0x410 0x444 0x478 0x4AC 0x4E0 0x514 0x548 0x57C 0x5B0 0x5E4 0x618 0x64C ) group.long ($2+0x2404)++0x3 line.long 0x0 "DOM_PER1_$1,Domain Permission Control. It can be only configured by resource manager and domain owner." bitfld.long 0x0 31. "DOM15_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 29.--30. "DOM15_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 28. "DOM15_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 27. "DOM14_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 25.--26. "DOM14_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" newline bitfld.long 0x0 24. "DOM14_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 23. "DOM13_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 21.--22. "DOM13_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 20. "DOM13_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 19. "DOM12_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" newline bitfld.long 0x0 17.--18. "DOM12_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM12_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 15. "DOM11_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 13.--14. "DOM11_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 12. "DOM11_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" newline bitfld.long 0x0 11. "DOM10_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 9.--10. "DOM10_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM10_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 7. "DOM9_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 5.--6. "DOM9_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" newline bitfld.long 0x0 4. "DOM9_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 3. "DOM8_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 1.--2. "DOM8_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM8_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" repeat.end repeat 16. (list 0x20 0x21 0x22 0x23 0x24 0x25 0x26 0x27 0x28 0x29 0x2A 0x2B 0x2C 0x2D 0x2E 0x2F )(list 0x680 0x6B4 0x6E8 0x71C 0x750 0x784 0x7B8 0x7EC 0x820 0x854 0x888 0x8BC 0x8F0 0x924 0x958 0x98C ) group.long ($2+0x2404)++0x3 line.long 0x0 "DOM_PER1_$1,Domain Permission Control. It can be only configured by resource manager and domain owner." bitfld.long 0x0 31. "DOM15_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 29.--30. "DOM15_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 28. "DOM15_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 27. "DOM14_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 25.--26. "DOM14_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" newline bitfld.long 0x0 24. "DOM14_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 23. "DOM13_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 21.--22. "DOM13_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 20. "DOM13_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 19. "DOM12_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" newline bitfld.long 0x0 17.--18. "DOM12_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM12_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 15. "DOM11_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 13.--14. "DOM11_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 12. "DOM11_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" newline bitfld.long 0x0 11. "DOM10_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 9.--10. "DOM10_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM10_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 7. "DOM9_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 5.--6. "DOM9_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" newline bitfld.long 0x0 4. "DOM9_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 3. "DOM8_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 1.--2. "DOM8_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM8_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" repeat.end repeat 16. (list 0x30 0x31 0x32 0x33 0x34 0x35 0x36 0x37 0x38 0x39 0x3A 0x3B 0x3C 0x3D 0x3E 0x3F )(list 0x9C0 0x9F4 0xA28 0xA5C 0xA90 0xAC4 0xAF8 0xB2C 0xB60 0xB94 0xBC8 0xBFC 0xC30 0xC64 0xC98 0xCCC ) group.long ($2+0x2404)++0x3 line.long 0x0 "DOM_PER1_$1,Domain Permission Control. It can be only configured by resource manager and domain owner." bitfld.long 0x0 31. "DOM15_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 29.--30. "DOM15_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 28. "DOM15_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 27. "DOM14_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 25.--26. "DOM14_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" newline bitfld.long 0x0 24. "DOM14_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 23. "DOM13_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 21.--22. "DOM13_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 20. "DOM13_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 19. "DOM12_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" newline bitfld.long 0x0 17.--18. "DOM12_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM12_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 15. "DOM11_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 13.--14. "DOM11_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 12. "DOM11_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" newline bitfld.long 0x0 11. "DOM10_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 9.--10. "DOM10_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM10_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 7. "DOM9_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 5.--6. "DOM9_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" newline bitfld.long 0x0 4. "DOM9_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 3. "DOM8_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 1.--2. "DOM8_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM8_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" repeat.end repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x34 0x68 0x9C 0xD0 0x104 0x138 0x16C 0x1A0 0x1D4 0x208 0x23C 0x270 0x2A4 0x2D8 0x30C ) group.long ($2+0x2408)++0x3 line.long 0x0 "SEC_PER0_$1,This register is only used for resource manager to control secure access permission." bitfld.long 0x0 31. "DOM3_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM3_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM3_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM3_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM2_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM2_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM2_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM2_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM1_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM1_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM1_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM1_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM0_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM0_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM0_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM0_SEC_EN,Domain secure permission control enable" "0,1" repeat.end repeat 16. (list 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1A 0x1B 0x1C 0x1D 0x1E 0x1F )(list 0x340 0x374 0x3A8 0x3DC 0x410 0x444 0x478 0x4AC 0x4E0 0x514 0x548 0x57C 0x5B0 0x5E4 0x618 0x64C ) group.long ($2+0x2408)++0x3 line.long 0x0 "SEC_PER0_$1,This register is only used for resource manager to control secure access permission." bitfld.long 0x0 31. "DOM3_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM3_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM3_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM3_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM2_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM2_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM2_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM2_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM1_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM1_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM1_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM1_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM0_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM0_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM0_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM0_SEC_EN,Domain secure permission control enable" "0,1" repeat.end repeat 16. (list 0x20 0x21 0x22 0x23 0x24 0x25 0x26 0x27 0x28 0x29 0x2A 0x2B 0x2C 0x2D 0x2E 0x2F )(list 0x680 0x6B4 0x6E8 0x71C 0x750 0x784 0x7B8 0x7EC 0x820 0x854 0x888 0x8BC 0x8F0 0x924 0x958 0x98C ) group.long ($2+0x2408)++0x3 line.long 0x0 "SEC_PER0_$1,This register is only used for resource manager to control secure access permission." bitfld.long 0x0 31. "DOM3_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM3_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM3_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM3_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM2_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM2_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM2_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM2_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM1_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM1_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM1_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM1_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM0_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM0_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM0_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM0_SEC_EN,Domain secure permission control enable" "0,1" repeat.end repeat 16. (list 0x30 0x31 0x32 0x33 0x34 0x35 0x36 0x37 0x38 0x39 0x3A 0x3B 0x3C 0x3D 0x3E 0x3F )(list 0x9C0 0x9F4 0xA28 0xA5C 0xA90 0xAC4 0xAF8 0xB2C 0xB60 0xB94 0xBC8 0xBFC 0xC30 0xC64 0xC98 0xCCC ) group.long ($2+0x2408)++0x3 line.long 0x0 "SEC_PER0_$1,This register is only used for resource manager to control secure access permission." bitfld.long 0x0 31. "DOM3_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM3_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM3_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM3_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM2_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM2_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM2_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM2_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM1_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM1_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM1_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM1_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM0_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM0_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM0_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM0_SEC_EN,Domain secure permission control enable" "0,1" repeat.end repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x34 0x68 0x9C 0xD0 0x104 0x138 0x16C 0x1A0 0x1D4 0x208 0x23C 0x270 0x2A4 0x2D8 0x30C ) group.long ($2+0x240C)++0x3 line.long 0x0 "SEC_PER1_$1,This register is only used for resource manager to control secure access permission." bitfld.long 0x0 31. "DOM7_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM7_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM7_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM7_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM6_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM6_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM6_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM6_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM5_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM5_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM5_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM5_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM4_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM4_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM4_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM4_SEC_EN,Domain secure permission control enable" "0,1" repeat.end repeat 16. (list 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1A 0x1B 0x1C 0x1D 0x1E 0x1F )(list 0x340 0x374 0x3A8 0x3DC 0x410 0x444 0x478 0x4AC 0x4E0 0x514 0x548 0x57C 0x5B0 0x5E4 0x618 0x64C ) group.long ($2+0x240C)++0x3 line.long 0x0 "SEC_PER1_$1,This register is only used for resource manager to control secure access permission." bitfld.long 0x0 31. "DOM7_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM7_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM7_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM7_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM6_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM6_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM6_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM6_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM5_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM5_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM5_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM5_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM4_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM4_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM4_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM4_SEC_EN,Domain secure permission control enable" "0,1" repeat.end repeat 16. (list 0x20 0x21 0x22 0x23 0x24 0x25 0x26 0x27 0x28 0x29 0x2A 0x2B 0x2C 0x2D 0x2E 0x2F )(list 0x680 0x6B4 0x6E8 0x71C 0x750 0x784 0x7B8 0x7EC 0x820 0x854 0x888 0x8BC 0x8F0 0x924 0x958 0x98C ) group.long ($2+0x240C)++0x3 line.long 0x0 "SEC_PER1_$1,This register is only used for resource manager to control secure access permission." bitfld.long 0x0 31. "DOM7_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM7_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM7_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM7_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM6_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM6_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM6_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM6_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM5_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM5_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM5_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM5_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM4_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM4_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM4_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM4_SEC_EN,Domain secure permission control enable" "0,1" repeat.end repeat 16. (list 0x30 0x31 0x32 0x33 0x34 0x35 0x36 0x37 0x38 0x39 0x3A 0x3B 0x3C 0x3D 0x3E 0x3F )(list 0x9C0 0x9F4 0xA28 0xA5C 0xA90 0xAC4 0xAF8 0xB2C 0xB60 0xB94 0xBC8 0xBFC 0xC30 0xC64 0xC98 0xCCC ) group.long ($2+0x240C)++0x3 line.long 0x0 "SEC_PER1_$1,This register is only used for resource manager to control secure access permission." bitfld.long 0x0 31. "DOM7_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM7_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM7_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM7_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM6_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM6_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM6_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM6_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM5_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM5_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM5_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM5_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM4_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM4_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM4_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM4_SEC_EN,Domain secure permission control enable" "0,1" repeat.end repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x34 0x68 0x9C 0xD0 0x104 0x138 0x16C 0x1A0 0x1D4 0x208 0x23C 0x270 0x2A4 0x2D8 0x30C ) group.long ($2+0x2410)++0x3 line.long 0x0 "SEC_PER2_$1,This register is only used for resource manager to control secure access permission." bitfld.long 0x0 31. "DOM11_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM11_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM11_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM11_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM10_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM10_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM10_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM10_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM9_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM9_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM9_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM9_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM8_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM8_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM8_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM8_SEC_EN,Domain secure permission control enable" "0,1" repeat.end repeat 16. (list 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1A 0x1B 0x1C 0x1D 0x1E 0x1F )(list 0x340 0x374 0x3A8 0x3DC 0x410 0x444 0x478 0x4AC 0x4E0 0x514 0x548 0x57C 0x5B0 0x5E4 0x618 0x64C ) group.long ($2+0x2410)++0x3 line.long 0x0 "SEC_PER2_$1,This register is only used for resource manager to control secure access permission." bitfld.long 0x0 31. "DOM11_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM11_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM11_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM11_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM10_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM10_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM10_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM10_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM9_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM9_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM9_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM9_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM8_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM8_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM8_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM8_SEC_EN,Domain secure permission control enable" "0,1" repeat.end repeat 16. (list 0x20 0x21 0x22 0x23 0x24 0x25 0x26 0x27 0x28 0x29 0x2A 0x2B 0x2C 0x2D 0x2E 0x2F )(list 0x680 0x6B4 0x6E8 0x71C 0x750 0x784 0x7B8 0x7EC 0x820 0x854 0x888 0x8BC 0x8F0 0x924 0x958 0x98C ) group.long ($2+0x2410)++0x3 line.long 0x0 "SEC_PER2_$1,This register is only used for resource manager to control secure access permission." bitfld.long 0x0 31. "DOM11_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM11_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM11_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM11_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM10_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM10_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM10_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM10_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM9_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM9_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM9_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM9_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM8_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM8_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM8_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM8_SEC_EN,Domain secure permission control enable" "0,1" repeat.end repeat 16. (list 0x30 0x31 0x32 0x33 0x34 0x35 0x36 0x37 0x38 0x39 0x3A 0x3B 0x3C 0x3D 0x3E 0x3F )(list 0x9C0 0x9F4 0xA28 0xA5C 0xA90 0xAC4 0xAF8 0xB2C 0xB60 0xB94 0xBC8 0xBFC 0xC30 0xC64 0xC98 0xCCC ) group.long ($2+0x2410)++0x3 line.long 0x0 "SEC_PER2_$1,This register is only used for resource manager to control secure access permission." bitfld.long 0x0 31. "DOM11_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM11_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM11_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM11_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM10_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM10_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM10_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM10_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM9_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM9_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM9_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM9_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM8_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM8_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM8_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM8_SEC_EN,Domain secure permission control enable" "0,1" repeat.end repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x34 0x68 0x9C 0xD0 0x104 0x138 0x16C 0x1A0 0x1D4 0x208 0x23C 0x270 0x2A4 0x2D8 0x30C ) group.long ($2+0x2414)++0x3 line.long 0x0 "SEC_PER3_$1,This register is only used for resource manager to control secure access permission." bitfld.long 0x0 31. "DOM15_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM15_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM15_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM15_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM14_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM14_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM14_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM14_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM13_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM13_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM13_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM13_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM12_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM12_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM12_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM12_SEC_EN,Domain secure permission control enable" "0,1" repeat.end repeat 16. (list 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1A 0x1B 0x1C 0x1D 0x1E 0x1F )(list 0x340 0x374 0x3A8 0x3DC 0x410 0x444 0x478 0x4AC 0x4E0 0x514 0x548 0x57C 0x5B0 0x5E4 0x618 0x64C ) group.long ($2+0x2414)++0x3 line.long 0x0 "SEC_PER3_$1,This register is only used for resource manager to control secure access permission." bitfld.long 0x0 31. "DOM15_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM15_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM15_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM15_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM14_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM14_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM14_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM14_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM13_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM13_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM13_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM13_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM12_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM12_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM12_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM12_SEC_EN,Domain secure permission control enable" "0,1" repeat.end repeat 16. (list 0x20 0x21 0x22 0x23 0x24 0x25 0x26 0x27 0x28 0x29 0x2A 0x2B 0x2C 0x2D 0x2E 0x2F )(list 0x680 0x6B4 0x6E8 0x71C 0x750 0x784 0x7B8 0x7EC 0x820 0x854 0x888 0x8BC 0x8F0 0x924 0x958 0x98C ) group.long ($2+0x2414)++0x3 line.long 0x0 "SEC_PER3_$1,This register is only used for resource manager to control secure access permission." bitfld.long 0x0 31. "DOM15_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM15_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM15_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM15_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM14_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM14_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM14_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM14_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM13_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM13_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM13_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM13_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM12_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM12_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM12_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM12_SEC_EN,Domain secure permission control enable" "0,1" repeat.end repeat 16. (list 0x30 0x31 0x32 0x33 0x34 0x35 0x36 0x37 0x38 0x39 0x3A 0x3B 0x3C 0x3D 0x3E 0x3F )(list 0x9C0 0x9F4 0xA28 0xA5C 0xA90 0xAC4 0xAF8 0xB2C 0xB60 0xB94 0xBC8 0xBFC 0xC30 0xC64 0xC98 0xCCC ) group.long ($2+0x2414)++0x3 line.long 0x0 "SEC_PER3_$1,This register is only used for resource manager to control secure access permission." bitfld.long 0x0 31. "DOM15_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM15_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM15_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM15_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM14_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM14_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM14_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM14_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM13_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM13_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM13_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM13_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM12_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM12_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM12_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM12_SEC_EN,Domain secure permission control enable" "0,1" repeat.end repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x34 0x68 0x9C 0xD0 0x104 0x138 0x16C 0x1A0 0x1D4 0x208 0x23C 0x270 0x2A4 0x2D8 0x30C ) group.long ($2+0x2418)++0x3 line.long 0x0 "PRI_PER0_$1,This register is only used for resource manager to control privileged access permission." bitfld.long 0x0 31. "DOM3_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM3_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM3_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM3_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM2_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM2_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM2_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM2_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM1_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM1_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM1_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM1_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM0_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM0_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM0_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM0_PRI_EN,Domain privileged permission control enable" "0,1" repeat.end repeat 16. (list 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1A 0x1B 0x1C 0x1D 0x1E 0x1F )(list 0x340 0x374 0x3A8 0x3DC 0x410 0x444 0x478 0x4AC 0x4E0 0x514 0x548 0x57C 0x5B0 0x5E4 0x618 0x64C ) group.long ($2+0x2418)++0x3 line.long 0x0 "PRI_PER0_$1,This register is only used for resource manager to control privileged access permission." bitfld.long 0x0 31. "DOM3_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM3_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM3_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM3_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM2_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM2_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM2_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM2_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM1_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM1_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM1_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM1_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM0_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM0_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM0_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM0_PRI_EN,Domain privileged permission control enable" "0,1" repeat.end repeat 16. (list 0x20 0x21 0x22 0x23 0x24 0x25 0x26 0x27 0x28 0x29 0x2A 0x2B 0x2C 0x2D 0x2E 0x2F )(list 0x680 0x6B4 0x6E8 0x71C 0x750 0x784 0x7B8 0x7EC 0x820 0x854 0x888 0x8BC 0x8F0 0x924 0x958 0x98C ) group.long ($2+0x2418)++0x3 line.long 0x0 "PRI_PER0_$1,This register is only used for resource manager to control privileged access permission." bitfld.long 0x0 31. "DOM3_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM3_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM3_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM3_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM2_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM2_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM2_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM2_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM1_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM1_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM1_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM1_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM0_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM0_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM0_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM0_PRI_EN,Domain privileged permission control enable" "0,1" repeat.end repeat 16. (list 0x30 0x31 0x32 0x33 0x34 0x35 0x36 0x37 0x38 0x39 0x3A 0x3B 0x3C 0x3D 0x3E 0x3F )(list 0x9C0 0x9F4 0xA28 0xA5C 0xA90 0xAC4 0xAF8 0xB2C 0xB60 0xB94 0xBC8 0xBFC 0xC30 0xC64 0xC98 0xCCC ) group.long ($2+0x2418)++0x3 line.long 0x0 "PRI_PER0_$1,This register is only used for resource manager to control privileged access permission." bitfld.long 0x0 31. "DOM3_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM3_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM3_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM3_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM2_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM2_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM2_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM2_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM1_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM1_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM1_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM1_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM0_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM0_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM0_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM0_PRI_EN,Domain privileged permission control enable" "0,1" repeat.end repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x34 0x68 0x9C 0xD0 0x104 0x138 0x16C 0x1A0 0x1D4 0x208 0x23C 0x270 0x2A4 0x2D8 0x30C ) group.long ($2+0x241C)++0x3 line.long 0x0 "PRI_PER1_$1,This register is only used for resource manager to control privileged access permission." bitfld.long 0x0 31. "DOM7_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM7_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM7_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM7_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM6_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM6_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM6_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM6_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM5_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM5_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM5_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM5_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM4_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM4_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM4_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM4_PRI_EN,Domain privileged permission control enable" "0,1" repeat.end repeat 16. (list 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1A 0x1B 0x1C 0x1D 0x1E 0x1F )(list 0x340 0x374 0x3A8 0x3DC 0x410 0x444 0x478 0x4AC 0x4E0 0x514 0x548 0x57C 0x5B0 0x5E4 0x618 0x64C ) group.long ($2+0x241C)++0x3 line.long 0x0 "PRI_PER1_$1,This register is only used for resource manager to control privileged access permission." bitfld.long 0x0 31. "DOM7_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM7_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM7_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM7_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM6_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM6_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM6_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM6_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM5_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM5_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM5_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM5_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM4_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM4_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM4_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM4_PRI_EN,Domain privileged permission control enable" "0,1" repeat.end repeat 16. (list 0x20 0x21 0x22 0x23 0x24 0x25 0x26 0x27 0x28 0x29 0x2A 0x2B 0x2C 0x2D 0x2E 0x2F )(list 0x680 0x6B4 0x6E8 0x71C 0x750 0x784 0x7B8 0x7EC 0x820 0x854 0x888 0x8BC 0x8F0 0x924 0x958 0x98C ) group.long ($2+0x241C)++0x3 line.long 0x0 "PRI_PER1_$1,This register is only used for resource manager to control privileged access permission." bitfld.long 0x0 31. "DOM7_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM7_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM7_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM7_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM6_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM6_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM6_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM6_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM5_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM5_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM5_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM5_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM4_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM4_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM4_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM4_PRI_EN,Domain privileged permission control enable" "0,1" repeat.end repeat 16. (list 0x30 0x31 0x32 0x33 0x34 0x35 0x36 0x37 0x38 0x39 0x3A 0x3B 0x3C 0x3D 0x3E 0x3F )(list 0x9C0 0x9F4 0xA28 0xA5C 0xA90 0xAC4 0xAF8 0xB2C 0xB60 0xB94 0xBC8 0xBFC 0xC30 0xC64 0xC98 0xCCC ) group.long ($2+0x241C)++0x3 line.long 0x0 "PRI_PER1_$1,This register is only used for resource manager to control privileged access permission." bitfld.long 0x0 31. "DOM7_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM7_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM7_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM7_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM6_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM6_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM6_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM6_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM5_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM5_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM5_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM5_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM4_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM4_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM4_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM4_PRI_EN,Domain privileged permission control enable" "0,1" repeat.end repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x34 0x68 0x9C 0xD0 0x104 0x138 0x16C 0x1A0 0x1D4 0x208 0x23C 0x270 0x2A4 0x2D8 0x30C ) group.long ($2+0x2420)++0x3 line.long 0x0 "PRI_PER2_$1,This register is only used for resource manager to control privileged access permission." bitfld.long 0x0 31. "DOM11_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM11_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM11_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM11_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM10_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM10_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM10_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM10_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM9_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM9_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM9_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM9_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM8_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM8_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM8_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM8_PRI_EN,Domain privileged permission control enable" "0,1" repeat.end repeat 16. (list 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1A 0x1B 0x1C 0x1D 0x1E 0x1F )(list 0x340 0x374 0x3A8 0x3DC 0x410 0x444 0x478 0x4AC 0x4E0 0x514 0x548 0x57C 0x5B0 0x5E4 0x618 0x64C ) group.long ($2+0x2420)++0x3 line.long 0x0 "PRI_PER2_$1,This register is only used for resource manager to control privileged access permission." bitfld.long 0x0 31. "DOM11_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM11_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM11_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM11_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM10_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM10_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM10_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM10_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM9_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM9_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM9_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM9_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM8_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM8_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM8_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM8_PRI_EN,Domain privileged permission control enable" "0,1" repeat.end repeat 16. (list 0x20 0x21 0x22 0x23 0x24 0x25 0x26 0x27 0x28 0x29 0x2A 0x2B 0x2C 0x2D 0x2E 0x2F )(list 0x680 0x6B4 0x6E8 0x71C 0x750 0x784 0x7B8 0x7EC 0x820 0x854 0x888 0x8BC 0x8F0 0x924 0x958 0x98C ) group.long ($2+0x2420)++0x3 line.long 0x0 "PRI_PER2_$1,This register is only used for resource manager to control privileged access permission." bitfld.long 0x0 31. "DOM11_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM11_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM11_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM11_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM10_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM10_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM10_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM10_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM9_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM9_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM9_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM9_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM8_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM8_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM8_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM8_PRI_EN,Domain privileged permission control enable" "0,1" repeat.end repeat 16. (list 0x30 0x31 0x32 0x33 0x34 0x35 0x36 0x37 0x38 0x39 0x3A 0x3B 0x3C 0x3D 0x3E 0x3F )(list 0x9C0 0x9F4 0xA28 0xA5C 0xA90 0xAC4 0xAF8 0xB2C 0xB60 0xB94 0xBC8 0xBFC 0xC30 0xC64 0xC98 0xCCC ) group.long ($2+0x2420)++0x3 line.long 0x0 "PRI_PER2_$1,This register is only used for resource manager to control privileged access permission." bitfld.long 0x0 31. "DOM11_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM11_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM11_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM11_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM10_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM10_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM10_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM10_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM9_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM9_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM9_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM9_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM8_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM8_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM8_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM8_PRI_EN,Domain privileged permission control enable" "0,1" repeat.end repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x34 0x68 0x9C 0xD0 0x104 0x138 0x16C 0x1A0 0x1D4 0x208 0x23C 0x270 0x2A4 0x2D8 0x30C ) group.long ($2+0x2424)++0x3 line.long 0x0 "PRI_PER3_$1,This register is only used for resource manager to control privileged access permission." bitfld.long 0x0 31. "DOM15_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM15_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM15_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM15_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM14_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM14_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM14_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM14_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM13_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM13_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM13_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM13_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM12_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM12_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM12_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM12_PRI_EN,Domain privileged permission control enable" "0,1" repeat.end repeat 16. (list 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1A 0x1B 0x1C 0x1D 0x1E 0x1F )(list 0x340 0x374 0x3A8 0x3DC 0x410 0x444 0x478 0x4AC 0x4E0 0x514 0x548 0x57C 0x5B0 0x5E4 0x618 0x64C ) group.long ($2+0x2424)++0x3 line.long 0x0 "PRI_PER3_$1,This register is only used for resource manager to control privileged access permission." bitfld.long 0x0 31. "DOM15_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM15_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM15_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM15_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM14_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM14_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM14_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM14_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM13_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM13_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM13_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM13_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM12_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM12_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM12_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM12_PRI_EN,Domain privileged permission control enable" "0,1" repeat.end repeat 16. (list 0x20 0x21 0x22 0x23 0x24 0x25 0x26 0x27 0x28 0x29 0x2A 0x2B 0x2C 0x2D 0x2E 0x2F )(list 0x680 0x6B4 0x6E8 0x71C 0x750 0x784 0x7B8 0x7EC 0x820 0x854 0x888 0x8BC 0x8F0 0x924 0x958 0x98C ) group.long ($2+0x2424)++0x3 line.long 0x0 "PRI_PER3_$1,This register is only used for resource manager to control privileged access permission." bitfld.long 0x0 31. "DOM15_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM15_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM15_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM15_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM14_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM14_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM14_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM14_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM13_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM13_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM13_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM13_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM12_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM12_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM12_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM12_PRI_EN,Domain privileged permission control enable" "0,1" repeat.end repeat 16. (list 0x30 0x31 0x32 0x33 0x34 0x35 0x36 0x37 0x38 0x39 0x3A 0x3B 0x3C 0x3D 0x3E 0x3F )(list 0x9C0 0x9F4 0xA28 0xA5C 0xA90 0xAC4 0xAF8 0xB2C 0xB60 0xB94 0xBC8 0xBFC 0xC30 0xC64 0xC98 0xCCC ) group.long ($2+0x2424)++0x3 line.long 0x0 "PRI_PER3_$1,This register is only used for resource manager to control privileged access permission." bitfld.long 0x0 31. "DOM15_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM15_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM15_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM15_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM14_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM14_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM14_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM14_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM13_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM13_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM13_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM13_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM12_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM12_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM12_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM12_PRI_EN,Domain privileged permission control enable" "0,1" repeat.end repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x34 0x68 0x9C 0xD0 0x104 0x138 0x16C 0x1A0 0x1D4 0x208 0x23C 0x270 0x2A4 0x2D8 0x30C ) group.long ($2+0x2428)++0x3 line.long 0x0 "DOM_SEC_PER_$1,This register is only used for domain master to control secure access permission. When the domain master write this register. it only changes the secure permission for itself. When the domain master read this register. it gets permission.." bitfld.long 0x0 7. "DOM_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" newline bitfld.long 0x0 0. "DOM_SEC_EN,Domain secure permission control enable" "0,1" repeat.end repeat 16. (list 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1A 0x1B 0x1C 0x1D 0x1E 0x1F )(list 0x340 0x374 0x3A8 0x3DC 0x410 0x444 0x478 0x4AC 0x4E0 0x514 0x548 0x57C 0x5B0 0x5E4 0x618 0x64C ) group.long ($2+0x2428)++0x3 line.long 0x0 "DOM_SEC_PER_$1,This register is only used for domain master to control secure access permission. When the domain master write this register. it only changes the secure permission for itself. When the domain master read this register. it gets permission.." bitfld.long 0x0 7. "DOM_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" newline bitfld.long 0x0 0. "DOM_SEC_EN,Domain secure permission control enable" "0,1" repeat.end repeat 16. (list 0x20 0x21 0x22 0x23 0x24 0x25 0x26 0x27 0x28 0x29 0x2A 0x2B 0x2C 0x2D 0x2E 0x2F )(list 0x680 0x6B4 0x6E8 0x71C 0x750 0x784 0x7B8 0x7EC 0x820 0x854 0x888 0x8BC 0x8F0 0x924 0x958 0x98C ) group.long ($2+0x2428)++0x3 line.long 0x0 "DOM_SEC_PER_$1,This register is only used for domain master to control secure access permission. When the domain master write this register. it only changes the secure permission for itself. When the domain master read this register. it gets permission.." bitfld.long 0x0 7. "DOM_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" newline bitfld.long 0x0 0. "DOM_SEC_EN,Domain secure permission control enable" "0,1" repeat.end repeat 16. (list 0x30 0x31 0x32 0x33 0x34 0x35 0x36 0x37 0x38 0x39 0x3A 0x3B 0x3C 0x3D 0x3E 0x3F )(list 0x9C0 0x9F4 0xA28 0xA5C 0xA90 0xAC4 0xAF8 0xB2C 0xB60 0xB94 0xBC8 0xBFC 0xC30 0xC64 0xC98 0xCCC ) group.long ($2+0x2428)++0x3 line.long 0x0 "DOM_SEC_PER_$1,This register is only used for domain master to control secure access permission. When the domain master write this register. it only changes the secure permission for itself. When the domain master read this register. it gets permission.." bitfld.long 0x0 7. "DOM_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" newline bitfld.long 0x0 0. "DOM_SEC_EN,Domain secure permission control enable" "0,1" repeat.end repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x34 0x68 0x9C 0xD0 0x104 0x138 0x16C 0x1A0 0x1D4 0x208 0x23C 0x270 0x2A4 0x2D8 0x30C ) group.long ($2+0x242C)++0x3 line.long 0x0 "DOM_PRI_PER_$1,This register is only used for domain master to control secure access permission. When the domain master write this register. it only changes the secure permission for itself. When the domain master read this register. it gets permission.." bitfld.long 0x0 7. "DOM_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" newline bitfld.long 0x0 0. "DOM_PRI_EN,Domain privileged permission control enable" "0,1" repeat.end repeat 16. (list 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1A 0x1B 0x1C 0x1D 0x1E 0x1F )(list 0x340 0x374 0x3A8 0x3DC 0x410 0x444 0x478 0x4AC 0x4E0 0x514 0x548 0x57C 0x5B0 0x5E4 0x618 0x64C ) group.long ($2+0x242C)++0x3 line.long 0x0 "DOM_PRI_PER_$1,This register is only used for domain master to control secure access permission. When the domain master write this register. it only changes the secure permission for itself. When the domain master read this register. it gets permission.." bitfld.long 0x0 7. "DOM_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" newline bitfld.long 0x0 0. "DOM_PRI_EN,Domain privileged permission control enable" "0,1" repeat.end repeat 16. (list 0x20 0x21 0x22 0x23 0x24 0x25 0x26 0x27 0x28 0x29 0x2A 0x2B 0x2C 0x2D 0x2E 0x2F )(list 0x680 0x6B4 0x6E8 0x71C 0x750 0x784 0x7B8 0x7EC 0x820 0x854 0x888 0x8BC 0x8F0 0x924 0x958 0x98C ) group.long ($2+0x242C)++0x3 line.long 0x0 "DOM_PRI_PER_$1,This register is only used for domain master to control secure access permission. When the domain master write this register. it only changes the secure permission for itself. When the domain master read this register. it gets permission.." bitfld.long 0x0 7. "DOM_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" newline bitfld.long 0x0 0. "DOM_PRI_EN,Domain privileged permission control enable" "0,1" repeat.end repeat 16. (list 0x30 0x31 0x32 0x33 0x34 0x35 0x36 0x37 0x38 0x39 0x3A 0x3B 0x3C 0x3D 0x3E 0x3F )(list 0x9C0 0x9F4 0xA28 0xA5C 0xA90 0xAC4 0xAF8 0xB2C 0xB60 0xB94 0xBC8 0xBFC 0xC30 0xC64 0xC98 0xCCC ) group.long ($2+0x242C)++0x3 line.long 0x0 "DOM_PRI_PER_$1,This register is only used for domain master to control secure access permission. When the domain master write this register. it only changes the secure permission for itself. When the domain master read this register. it gets permission.." bitfld.long 0x0 7. "DOM_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" newline bitfld.long 0x0 0. "DOM_PRI_EN,Domain privileged permission control enable" "0,1" repeat.end repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x34 0x68 0x9C 0xD0 0x104 0x138 0x16C 0x1A0 0x1D4 0x208 0x23C 0x270 0x2A4 0x2D8 0x30C ) group.long ($2+0x2430)++0x3 line.long 0x0 "DOM_ASSIGN_$1,Use to assign domain for accessing DOM_SEC_PER and DOM_PRI_PER register. Only resource manager. group manager and domain owner can access this register. For write. group manager must write its owen domain ID. otherwise write accessing will.." hexmask.long.byte 0x0 0.--3. 1. "DID,accessing DOM_SEC_PER and DOM_PRI_PER register" repeat.end repeat 16. (list 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1A 0x1B 0x1C 0x1D 0x1E 0x1F )(list 0x340 0x374 0x3A8 0x3DC 0x410 0x444 0x478 0x4AC 0x4E0 0x514 0x548 0x57C 0x5B0 0x5E4 0x618 0x64C ) group.long ($2+0x2430)++0x3 line.long 0x0 "DOM_ASSIGN_$1,Use to assign domain for accessing DOM_SEC_PER and DOM_PRI_PER register. Only resource manager. group manager and domain owner can access this register. For write. group manager must write its owen domain ID. otherwise write accessing will.." hexmask.long.byte 0x0 0.--3. 1. "DID,accessing DOM_SEC_PER and DOM_PRI_PER register" repeat.end repeat 16. (list 0x20 0x21 0x22 0x23 0x24 0x25 0x26 0x27 0x28 0x29 0x2A 0x2B 0x2C 0x2D 0x2E 0x2F )(list 0x680 0x6B4 0x6E8 0x71C 0x750 0x784 0x7B8 0x7EC 0x820 0x854 0x888 0x8BC 0x8F0 0x924 0x958 0x98C ) group.long ($2+0x2430)++0x3 line.long 0x0 "DOM_ASSIGN_$1,Use to assign domain for accessing DOM_SEC_PER and DOM_PRI_PER register. Only resource manager. group manager and domain owner can access this register. For write. group manager must write its owen domain ID. otherwise write accessing will.." hexmask.long.byte 0x0 0.--3. 1. "DID,accessing DOM_SEC_PER and DOM_PRI_PER register" repeat.end repeat 16. (list 0x30 0x31 0x32 0x33 0x34 0x35 0x36 0x37 0x38 0x39 0x3A 0x3B 0x3C 0x3D 0x3E 0x3F )(list 0x9C0 0x9F4 0xA28 0xA5C 0xA90 0xAC4 0xAF8 0xB2C 0xB60 0xB94 0xBC8 0xBFC 0xC30 0xC64 0xC98 0xCCC ) group.long ($2+0x2430)++0x3 line.long 0x0 "DOM_ASSIGN_$1,Use to assign domain for accessing DOM_SEC_PER and DOM_PRI_PER register. Only resource manager. group manager and domain owner can access this register. For write. group manager must write its owen domain ID. otherwise write accessing will.." hexmask.long.byte 0x0 0.--3. 1. "DID,accessing DOM_SEC_PER and DOM_PRI_PER register" repeat.end repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x38 0x70 0xA8 0xE0 0x118 0x150 0x188 0x1C0 0x1F8 0x230 0x268 0x2A0 0x2D8 0x310 0x348 ) group.long ($2+0x3100)++0x3 line.long 0x0 "RGN_DOM_$1,Assign domain for peripheral. It can be only configured by resource and group manager" bitfld.long 0x0 31. "LOCK,When this bit is set lock write for all the bits in the register." "0,1" bitfld.long 0x0 4. "SET,Set together with DID would change permission of this resource to following setting: 1) Domain access control enabled. 2) Read/Write allowed for the domain owner. 3) Read/Write not allowed for all the other domains. If this bit is not set only DID.." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Assign domain for peripheral" repeat.end repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x38 0x70 0xA8 0xE0 0x118 0x150 0x188 0x1C0 0x1F8 0x230 0x268 0x2A0 0x2D8 0x310 0x348 ) group.long ($2+0x3104)++0x3 line.long 0x0 "RGN_DOM_PER0_$1,Domain Permission Control. It can be only configured by resource manager and domain owner." bitfld.long 0x0 31. "DOM7_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 29.--30. "DOM7_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 28. "DOM7_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 27. "DOM6_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 25.--26. "DOM6_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" newline bitfld.long 0x0 24. "DOM6_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 23. "DOM5_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 21.--22. "DOM5_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 20. "DOM5_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 19. "DOM4_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" newline bitfld.long 0x0 17.--18. "DOM4_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM4_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 15. "DOM3_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 13.--14. "DOM3_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 12. "DOM3_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" newline bitfld.long 0x0 11. "DOM2_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 9.--10. "DOM2_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM2_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 7. "DOM1_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 5.--6. "DOM1_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" newline bitfld.long 0x0 4. "DOM1_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 3. "DOM0_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 1.--2. "DOM0_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM0_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" repeat.end repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x38 0x70 0xA8 0xE0 0x118 0x150 0x188 0x1C0 0x1F8 0x230 0x268 0x2A0 0x2D8 0x310 0x348 ) group.long ($2+0x3108)++0x3 line.long 0x0 "RGN_DOM_PER1_$1,Domain Permission Control. It can be only configured by resource manager and domain owner." bitfld.long 0x0 31. "DOM15_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 29.--30. "DOM15_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 28. "DOM15_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 27. "DOM14_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 25.--26. "DOM14_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" newline bitfld.long 0x0 24. "DOM14_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 23. "DOM13_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 21.--22. "DOM13_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 20. "DOM13_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 19. "DOM12_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" newline bitfld.long 0x0 17.--18. "DOM12_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM12_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 15. "DOM11_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 13.--14. "DOM11_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 12. "DOM11_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" newline bitfld.long 0x0 11. "DOM10_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 9.--10. "DOM10_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM10_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 7. "DOM9_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 5.--6. "DOM9_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" newline bitfld.long 0x0 4. "DOM9_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 3. "DOM8_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 1.--2. "DOM8_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM8_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" repeat.end repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x38 0x70 0xA8 0xE0 0x118 0x150 0x188 0x1C0 0x1F8 0x230 0x268 0x2A0 0x2D8 0x310 0x348 ) group.long ($2+0x310C)++0x3 line.long 0x0 "RGN_SEC_PER0_$1,This register is only used for resource manager to control secure access permission." bitfld.long 0x0 31. "DOM3_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM3_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM3_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM3_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM2_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM2_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM2_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM2_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM1_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM1_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM1_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM1_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM0_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM0_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM0_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM0_SEC_EN,Domain secure permission control enable" "0,1" repeat.end repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x38 0x70 0xA8 0xE0 0x118 0x150 0x188 0x1C0 0x1F8 0x230 0x268 0x2A0 0x2D8 0x310 0x348 ) group.long ($2+0x3110)++0x3 line.long 0x0 "RGN_SEC_PER1_$1,This register is only used for resource manager to control secure access permission." bitfld.long 0x0 31. "DOM7_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM7_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM7_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM7_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM6_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM6_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM6_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM6_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM5_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM5_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM5_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM5_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM4_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM4_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM4_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM4_SEC_EN,Domain secure permission control enable" "0,1" repeat.end repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x38 0x70 0xA8 0xE0 0x118 0x150 0x188 0x1C0 0x1F8 0x230 0x268 0x2A0 0x2D8 0x310 0x348 ) group.long ($2+0x3114)++0x3 line.long 0x0 "RGN_SEC_PER2_$1,This register is only used for resource manager to control secure access permission." bitfld.long 0x0 31. "DOM11_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM11_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM11_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM11_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM10_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM10_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM10_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM10_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM9_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM9_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM9_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM9_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM8_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM8_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM8_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM8_SEC_EN,Domain secure permission control enable" "0,1" repeat.end repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x38 0x70 0xA8 0xE0 0x118 0x150 0x188 0x1C0 0x1F8 0x230 0x268 0x2A0 0x2D8 0x310 0x348 ) group.long ($2+0x3118)++0x3 line.long 0x0 "RGN_SEC_PER3_$1,This register is only used for resource manager to control secure access permission." bitfld.long 0x0 31. "DOM15_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM15_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM15_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM15_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM14_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM14_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM14_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM14_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM13_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM13_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM13_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM13_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM12_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM12_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM12_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM12_SEC_EN,Domain secure permission control enable" "0,1" repeat.end repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x38 0x70 0xA8 0xE0 0x118 0x150 0x188 0x1C0 0x1F8 0x230 0x268 0x2A0 0x2D8 0x310 0x348 ) group.long ($2+0x311C)++0x3 line.long 0x0 "RGN_PRI_PER0_$1,This register is only used for resource manager to control privileged access permission." bitfld.long 0x0 31. "DOM3_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM3_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM3_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM3_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM2_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM2_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM2_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM2_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM1_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM1_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM1_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM1_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM0_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM0_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM0_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM0_PRI_EN,Domain privileged permission control enable" "0,1" repeat.end repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x38 0x70 0xA8 0xE0 0x118 0x150 0x188 0x1C0 0x1F8 0x230 0x268 0x2A0 0x2D8 0x310 0x348 ) group.long ($2+0x3120)++0x3 line.long 0x0 "RGN_PRI_PER1_$1,This register is only used for resource manager to control privileged access permission." bitfld.long 0x0 31. "DOM7_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM7_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM7_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM7_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM6_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM6_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM6_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM6_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM5_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM5_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM5_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM5_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM4_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM4_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM4_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM4_PRI_EN,Domain privileged permission control enable" "0,1" repeat.end repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x38 0x70 0xA8 0xE0 0x118 0x150 0x188 0x1C0 0x1F8 0x230 0x268 0x2A0 0x2D8 0x310 0x348 ) group.long ($2+0x3124)++0x3 line.long 0x0 "RGN_PRI_PER2_$1,This register is only used for resource manager to control privileged access permission." bitfld.long 0x0 31. "DOM11_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM11_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM11_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM11_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM10_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM10_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM10_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM10_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM9_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM9_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM9_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM9_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM8_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM8_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM8_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM8_PRI_EN,Domain privileged permission control enable" "0,1" repeat.end repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x38 0x70 0xA8 0xE0 0x118 0x150 0x188 0x1C0 0x1F8 0x230 0x268 0x2A0 0x2D8 0x310 0x348 ) group.long ($2+0x3128)++0x3 line.long 0x0 "RGN_PRI_PER3_$1,This register is only used for resource manager to control privileged access permission." bitfld.long 0x0 31. "DOM15_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM15_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM15_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM15_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM14_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM14_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM14_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM14_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM13_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM13_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM13_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM13_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM12_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM12_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM12_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM12_PRI_EN,Domain privileged permission control enable" "0,1" repeat.end repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x38 0x70 0xA8 0xE0 0x118 0x150 0x188 0x1C0 0x1F8 0x230 0x268 0x2A0 0x2D8 0x310 0x348 ) group.long ($2+0x312C)++0x3 line.long 0x0 "RGN_DOM_SEC_PER_$1,This register is only used for domain master to control secure access permission. When the domain master write this register. it only changes the secure permission for itself. When the domain master read this register. it gets.." bitfld.long 0x0 7. "DOM_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" newline bitfld.long 0x0 0. "DOM_SEC_EN,Domain secure permission control enable" "0,1" repeat.end repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x38 0x70 0xA8 0xE0 0x118 0x150 0x188 0x1C0 0x1F8 0x230 0x268 0x2A0 0x2D8 0x310 0x348 ) group.long ($2+0x3130)++0x3 line.long 0x0 "RGN_DOM_PRI_PER_$1,This register is only used for domain master to control secure access permission. When the domain master write this register. it only changes the secure permission for itself. When the domain master read this register. it gets.." bitfld.long 0x0 7. "DOM_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" newline bitfld.long 0x0 0. "DOM_PRI_EN,Domain privileged permission control enable" "0,1" repeat.end repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x38 0x70 0xA8 0xE0 0x118 0x150 0x188 0x1C0 0x1F8 0x230 0x268 0x2A0 0x2D8 0x310 0x348 ) group.long ($2+0x3134)++0x3 line.long 0x0 "RGN_DOM_ASSIGN_$1,Use to assign domain for accessing DOM_SEC_PER and DOM_PRI_PER register. Only resource manager. group manager and domain owner can access this register. For write. group manager must write its owen domain ID. otherwise write accessing.." hexmask.long.byte 0x0 0.--3. 1. "DID,accessing DOM_SEC_PER and DOM_PRI_PER register" repeat.end tree.end tree "RPC_SAFETY_GLOBAL" base ad:0xFCFFE000 repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x4 0x8 0xC 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C ) group.long ($2)++0x3 line.long 0x0 "REGG0_DOM_$1,Assign domain for CKGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1A 0x1B 0x1C 0x1D 0x1E 0x1F )(list 0x40 0x44 0x48 0x4C 0x50 0x54 0x58 0x5C 0x60 0x64 0x68 0x6C 0x70 0x74 0x78 0x7C ) group.long ($2)++0x3 line.long 0x0 "REGG0_DOM_$1,Assign domain for CKGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x20 0x21 0x22 0x23 0x24 0x25 0x26 0x27 0x28 0x29 0x2A 0x2B 0x2C 0x2D 0x2E 0x2F )(list 0x80 0x84 0x88 0x8C 0x90 0x94 0x98 0x9C 0xA0 0xA4 0xA8 0xAC 0xB0 0xB4 0xB8 0xBC ) group.long ($2)++0x3 line.long 0x0 "REGG0_DOM_$1,Assign domain for CKGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x30 0x31 0x32 0x33 0x34 0x35 0x36 0x37 0x38 0x39 0x3A 0x3B 0x3C 0x3D 0x3E 0x3F )(list 0xC0 0xC4 0xC8 0xCC 0xD0 0xD4 0xD8 0xDC 0xE0 0xE4 0xE8 0xEC 0xF0 0xF4 0xF8 0xFC ) group.long ($2)++0x3 line.long 0x0 "REGG0_DOM_$1,Assign domain for CKGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x40 0x41 0x42 0x43 0x44 0x45 0x46 0x47 0x48 0x49 0x4A 0x4B 0x4C 0x4D 0x4E 0x4F )(list 0x100 0x104 0x108 0x10C 0x110 0x114 0x118 0x11C 0x120 0x124 0x128 0x12C 0x130 0x134 0x138 0x13C ) group.long ($2)++0x3 line.long 0x0 "REGG0_DOM_$1,Assign domain for CKGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x50 0x51 0x52 0x53 0x54 0x55 0x56 0x57 0x58 0x59 0x5A 0x5B 0x5C 0x5D 0x5E 0x5F )(list 0x140 0x144 0x148 0x14C 0x150 0x154 0x158 0x15C 0x160 0x164 0x168 0x16C 0x170 0x174 0x178 0x17C ) group.long ($2)++0x3 line.long 0x0 "REGG0_DOM_$1,Assign domain for CKGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x60 0x61 0x62 0x63 0x64 0x65 0x66 0x67 0x68 0x69 0x6A 0x6B 0x6C 0x6D 0x6E 0x6F )(list 0x180 0x184 0x188 0x18C 0x190 0x194 0x198 0x19C 0x1A0 0x1A4 0x1A8 0x1AC 0x1B0 0x1B4 0x1B8 0x1BC ) group.long ($2)++0x3 line.long 0x0 "REGG0_DOM_$1,Assign domain for CKGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x70 0x71 0x72 0x73 0x74 0x75 0x76 0x77 0x78 0x79 0x7A 0x7B 0x7C 0x7D 0x7E 0x7F )(list 0x1C0 0x1C4 0x1C8 0x1CC 0x1D0 0x1D4 0x1D8 0x1DC 0x1E0 0x1E4 0x1E8 0x1EC 0x1F0 0x1F4 0x1F8 0x1FC ) group.long ($2)++0x3 line.long 0x0 "REGG0_DOM_$1,Assign domain for CKGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x80 0x81 0x82 0x83 0x84 0x85 0x86 0x87 0x88 0x89 0x8A 0x8B 0x8C 0x8D 0x8E 0x8F )(list 0x200 0x204 0x208 0x20C 0x210 0x214 0x218 0x21C 0x220 0x224 0x228 0x22C 0x230 0x234 0x238 0x23C ) group.long ($2)++0x3 line.long 0x0 "REGG0_DOM_$1,Assign domain for CKGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x90 0x91 0x92 0x93 0x94 0x95 0x96 0x97 0x98 0x99 0x9A 0x9B 0x9C 0x9D 0x9E 0x9F )(list 0x240 0x244 0x248 0x24C 0x250 0x254 0x258 0x25C 0x260 0x264 0x268 0x26C 0x270 0x274 0x278 0x27C ) group.long ($2)++0x3 line.long 0x0 "REGG0_DOM_$1,Assign domain for CKGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xA0 0xA1 0xA2 0xA3 0xA4 0xA5 0xA6 0xA7 0xA8 0xA9 0xAA 0xAB 0xAC 0xAD 0xAE 0xAF )(list 0x280 0x284 0x288 0x28C 0x290 0x294 0x298 0x29C 0x2A0 0x2A4 0x2A8 0x2AC 0x2B0 0x2B4 0x2B8 0x2BC ) group.long ($2)++0x3 line.long 0x0 "REGG0_DOM_$1,Assign domain for CKGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xB0 0xB1 0xB2 0xB3 0xB4 0xB5 0xB6 0xB7 0xB8 0xB9 0xBA 0xBB 0xBC 0xBD 0xBE 0xBF )(list 0x2C0 0x2C4 0x2C8 0x2CC 0x2D0 0x2D4 0x2D8 0x2DC 0x2E0 0x2E4 0x2E8 0x2EC 0x2F0 0x2F4 0x2F8 0x2FC ) group.long ($2)++0x3 line.long 0x0 "REGG0_DOM_$1,Assign domain for CKGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xC0 0xC1 0xC2 0xC3 0xC4 0xC5 0xC6 0xC7 0xC8 0xC9 0xCA 0xCB 0xCC 0xCD 0xCE 0xCF )(list 0x300 0x304 0x308 0x30C 0x310 0x314 0x318 0x31C 0x320 0x324 0x328 0x32C 0x330 0x334 0x338 0x33C ) group.long ($2)++0x3 line.long 0x0 "REGG0_DOM_$1,Assign domain for CKGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xD0 0xD1 0xD2 0xD3 0xD4 0xD5 0xD6 0xD7 0xD8 0xD9 0xDA 0xDB 0xDC 0xDD 0xDE 0xDF )(list 0x340 0x344 0x348 0x34C 0x350 0x354 0x358 0x35C 0x360 0x364 0x368 0x36C 0x370 0x374 0x378 0x37C ) group.long ($2)++0x3 line.long 0x0 "REGG0_DOM_$1,Assign domain for CKGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xE0 0xE1 0xE2 0xE3 0xE4 0xE5 0xE6 0xE7 0xE8 0xE9 0xEA 0xEB 0xEC 0xED 0xEE 0xEF )(list 0x380 0x384 0x388 0x38C 0x390 0x394 0x398 0x39C 0x3A0 0x3A4 0x3A8 0x3AC 0x3B0 0x3B4 0x3B8 0x3BC ) group.long ($2)++0x3 line.long 0x0 "REGG0_DOM_$1,Assign domain for CKGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xF0 0xF1 0xF2 0xF3 0xF4 0xF5 0xF6 0xF7 0xF8 0xF9 0xFA 0xFB 0xFC 0xFD 0xFE 0xFF )(list 0x3C0 0x3C4 0x3C8 0x3CC 0x3D0 0x3D4 0x3D8 0x3DC 0x3E0 0x3E4 0x3E8 0x3EC 0x3F0 0x3F4 0x3F8 0x3FC ) group.long ($2)++0x3 line.long 0x0 "REGG0_DOM_$1,Assign domain for CKGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x4 0x8 0xC 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C ) group.long ($2+0x400)++0x3 line.long 0x0 "REGG1_DOM_$1,Assign domain for CKGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1A 0x1B 0x1C 0x1D 0x1E 0x1F )(list 0x40 0x44 0x48 0x4C 0x50 0x54 0x58 0x5C 0x60 0x64 0x68 0x6C 0x70 0x74 0x78 0x7C ) group.long ($2+0x400)++0x3 line.long 0x0 "REGG1_DOM_$1,Assign domain for CKGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x20 0x21 0x22 0x23 0x24 0x25 0x26 0x27 0x28 0x29 0x2A 0x2B 0x2C 0x2D 0x2E 0x2F )(list 0x80 0x84 0x88 0x8C 0x90 0x94 0x98 0x9C 0xA0 0xA4 0xA8 0xAC 0xB0 0xB4 0xB8 0xBC ) group.long ($2+0x400)++0x3 line.long 0x0 "REGG1_DOM_$1,Assign domain for CKGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x30 0x31 0x32 0x33 0x34 0x35 0x36 0x37 0x38 0x39 0x3A 0x3B 0x3C 0x3D 0x3E 0x3F )(list 0xC0 0xC4 0xC8 0xCC 0xD0 0xD4 0xD8 0xDC 0xE0 0xE4 0xE8 0xEC 0xF0 0xF4 0xF8 0xFC ) group.long ($2+0x400)++0x3 line.long 0x0 "REGG1_DOM_$1,Assign domain for CKGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x40 0x41 0x42 0x43 0x44 0x45 0x46 0x47 0x48 0x49 0x4A 0x4B 0x4C 0x4D 0x4E 0x4F )(list 0x100 0x104 0x108 0x10C 0x110 0x114 0x118 0x11C 0x120 0x124 0x128 0x12C 0x130 0x134 0x138 0x13C ) group.long ($2+0x400)++0x3 line.long 0x0 "REGG1_DOM_$1,Assign domain for CKGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x50 0x51 0x52 0x53 0x54 0x55 0x56 0x57 0x58 0x59 0x5A 0x5B 0x5C 0x5D 0x5E 0x5F )(list 0x140 0x144 0x148 0x14C 0x150 0x154 0x158 0x15C 0x160 0x164 0x168 0x16C 0x170 0x174 0x178 0x17C ) group.long ($2+0x400)++0x3 line.long 0x0 "REGG1_DOM_$1,Assign domain for CKGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x60 0x61 0x62 0x63 0x64 0x65 0x66 0x67 0x68 0x69 0x6A 0x6B 0x6C 0x6D 0x6E 0x6F )(list 0x180 0x184 0x188 0x18C 0x190 0x194 0x198 0x19C 0x1A0 0x1A4 0x1A8 0x1AC 0x1B0 0x1B4 0x1B8 0x1BC ) group.long ($2+0x400)++0x3 line.long 0x0 "REGG1_DOM_$1,Assign domain for CKGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x70 0x71 0x72 0x73 0x74 0x75 0x76 0x77 0x78 0x79 0x7A 0x7B 0x7C 0x7D 0x7E 0x7F )(list 0x1C0 0x1C4 0x1C8 0x1CC 0x1D0 0x1D4 0x1D8 0x1DC 0x1E0 0x1E4 0x1E8 0x1EC 0x1F0 0x1F4 0x1F8 0x1FC ) group.long ($2+0x400)++0x3 line.long 0x0 "REGG1_DOM_$1,Assign domain for CKGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x80 0x81 0x82 0x83 0x84 0x85 0x86 0x87 0x88 0x89 0x8A 0x8B 0x8C 0x8D 0x8E 0x8F )(list 0x200 0x204 0x208 0x20C 0x210 0x214 0x218 0x21C 0x220 0x224 0x228 0x22C 0x230 0x234 0x238 0x23C ) group.long ($2+0x400)++0x3 line.long 0x0 "REGG1_DOM_$1,Assign domain for CKGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x90 0x91 0x92 0x93 0x94 0x95 0x96 0x97 0x98 0x99 0x9A 0x9B 0x9C 0x9D 0x9E 0x9F )(list 0x240 0x244 0x248 0x24C 0x250 0x254 0x258 0x25C 0x260 0x264 0x268 0x26C 0x270 0x274 0x278 0x27C ) group.long ($2+0x400)++0x3 line.long 0x0 "REGG1_DOM_$1,Assign domain for CKGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xA0 0xA1 0xA2 0xA3 0xA4 0xA5 0xA6 0xA7 0xA8 0xA9 0xAA 0xAB 0xAC 0xAD 0xAE 0xAF )(list 0x280 0x284 0x288 0x28C 0x290 0x294 0x298 0x29C 0x2A0 0x2A4 0x2A8 0x2AC 0x2B0 0x2B4 0x2B8 0x2BC ) group.long ($2+0x400)++0x3 line.long 0x0 "REGG1_DOM_$1,Assign domain for CKGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xB0 0xB1 0xB2 0xB3 0xB4 0xB5 0xB6 0xB7 0xB8 0xB9 0xBA 0xBB 0xBC 0xBD 0xBE 0xBF )(list 0x2C0 0x2C4 0x2C8 0x2CC 0x2D0 0x2D4 0x2D8 0x2DC 0x2E0 0x2E4 0x2E8 0x2EC 0x2F0 0x2F4 0x2F8 0x2FC ) group.long ($2+0x400)++0x3 line.long 0x0 "REGG1_DOM_$1,Assign domain for CKGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xC0 0xC1 0xC2 0xC3 0xC4 0xC5 0xC6 0xC7 0xC8 0xC9 0xCA 0xCB 0xCC 0xCD 0xCE 0xCF )(list 0x300 0x304 0x308 0x30C 0x310 0x314 0x318 0x31C 0x320 0x324 0x328 0x32C 0x330 0x334 0x338 0x33C ) group.long ($2+0x400)++0x3 line.long 0x0 "REGG1_DOM_$1,Assign domain for CKGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xD0 0xD1 0xD2 0xD3 0xD4 0xD5 0xD6 0xD7 0xD8 0xD9 0xDA 0xDB 0xDC 0xDD 0xDE 0xDF )(list 0x340 0x344 0x348 0x34C 0x350 0x354 0x358 0x35C 0x360 0x364 0x368 0x36C 0x370 0x374 0x378 0x37C ) group.long ($2+0x400)++0x3 line.long 0x0 "REGG1_DOM_$1,Assign domain for CKGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xE0 0xE1 0xE2 0xE3 0xE4 0xE5 0xE6 0xE7 0xE8 0xE9 0xEA 0xEB 0xEC 0xED 0xEE 0xEF )(list 0x380 0x384 0x388 0x38C 0x390 0x394 0x398 0x39C 0x3A0 0x3A4 0x3A8 0x3AC 0x3B0 0x3B4 0x3B8 0x3BC ) group.long ($2+0x400)++0x3 line.long 0x0 "REGG1_DOM_$1,Assign domain for CKGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xF0 0xF1 0xF2 0xF3 0xF4 0xF5 0xF6 0xF7 0xF8 0xF9 0xFA 0xFB 0xFC 0xFD 0xFE 0xFF )(list 0x3C0 0x3C4 0x3C8 0x3CC 0x3D0 0x3D4 0x3D8 0x3DC 0x3E0 0x3E4 0x3E8 0x3EC 0x3F0 0x3F4 0x3F8 0x3FC ) group.long ($2+0x400)++0x3 line.long 0x0 "REGG1_DOM_$1,Assign domain for CKGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x4 0x8 0xC 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C ) group.long ($2+0x800)++0x3 line.long 0x0 "REGG2_DOM_$1,Assign domain for SCR registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1A 0x1B 0x1C 0x1D 0x1E 0x1F )(list 0x40 0x44 0x48 0x4C 0x50 0x54 0x58 0x5C 0x60 0x64 0x68 0x6C 0x70 0x74 0x78 0x7C ) group.long ($2+0x800)++0x3 line.long 0x0 "REGG2_DOM_$1,Assign domain for SCR registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x20 0x21 0x22 0x23 0x24 0x25 0x26 0x27 0x28 0x29 0x2A 0x2B 0x2C 0x2D 0x2E 0x2F )(list 0x80 0x84 0x88 0x8C 0x90 0x94 0x98 0x9C 0xA0 0xA4 0xA8 0xAC 0xB0 0xB4 0xB8 0xBC ) group.long ($2+0x800)++0x3 line.long 0x0 "REGG2_DOM_$1,Assign domain for SCR registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x30 0x31 0x32 0x33 0x34 0x35 0x36 0x37 0x38 0x39 0x3A 0x3B 0x3C 0x3D 0x3E 0x3F )(list 0xC0 0xC4 0xC8 0xCC 0xD0 0xD4 0xD8 0xDC 0xE0 0xE4 0xE8 0xEC 0xF0 0xF4 0xF8 0xFC ) group.long ($2+0x800)++0x3 line.long 0x0 "REGG2_DOM_$1,Assign domain for SCR registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x40 0x41 0x42 0x43 0x44 0x45 0x46 0x47 0x48 0x49 0x4A 0x4B 0x4C 0x4D 0x4E 0x4F )(list 0x100 0x104 0x108 0x10C 0x110 0x114 0x118 0x11C 0x120 0x124 0x128 0x12C 0x130 0x134 0x138 0x13C ) group.long ($2+0x800)++0x3 line.long 0x0 "REGG2_DOM_$1,Assign domain for SCR registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x50 0x51 0x52 0x53 0x54 0x55 0x56 0x57 0x58 0x59 0x5A 0x5B 0x5C 0x5D 0x5E 0x5F )(list 0x140 0x144 0x148 0x14C 0x150 0x154 0x158 0x15C 0x160 0x164 0x168 0x16C 0x170 0x174 0x178 0x17C ) group.long ($2+0x800)++0x3 line.long 0x0 "REGG2_DOM_$1,Assign domain for SCR registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x60 0x61 0x62 0x63 0x64 0x65 0x66 0x67 0x68 0x69 0x6A 0x6B 0x6C 0x6D 0x6E 0x6F )(list 0x180 0x184 0x188 0x18C 0x190 0x194 0x198 0x19C 0x1A0 0x1A4 0x1A8 0x1AC 0x1B0 0x1B4 0x1B8 0x1BC ) group.long ($2+0x800)++0x3 line.long 0x0 "REGG2_DOM_$1,Assign domain for SCR registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x70 0x71 0x72 0x73 0x74 0x75 0x76 0x77 0x78 0x79 0x7A 0x7B 0x7C 0x7D 0x7E 0x7F )(list 0x1C0 0x1C4 0x1C8 0x1CC 0x1D0 0x1D4 0x1D8 0x1DC 0x1E0 0x1E4 0x1E8 0x1EC 0x1F0 0x1F4 0x1F8 0x1FC ) group.long ($2+0x800)++0x3 line.long 0x0 "REGG2_DOM_$1,Assign domain for SCR registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x80 0x81 0x82 0x83 0x84 0x85 0x86 0x87 0x88 0x89 0x8A 0x8B 0x8C 0x8D 0x8E 0x8F )(list 0x200 0x204 0x208 0x20C 0x210 0x214 0x218 0x21C 0x220 0x224 0x228 0x22C 0x230 0x234 0x238 0x23C ) group.long ($2+0x800)++0x3 line.long 0x0 "REGG2_DOM_$1,Assign domain for SCR registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x90 0x91 0x92 0x93 0x94 0x95 0x96 0x97 0x98 0x99 0x9A 0x9B 0x9C 0x9D 0x9E 0x9F )(list 0x240 0x244 0x248 0x24C 0x250 0x254 0x258 0x25C 0x260 0x264 0x268 0x26C 0x270 0x274 0x278 0x27C ) group.long ($2+0x800)++0x3 line.long 0x0 "REGG2_DOM_$1,Assign domain for SCR registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xA0 0xA1 0xA2 0xA3 0xA4 0xA5 0xA6 0xA7 0xA8 0xA9 0xAA 0xAB 0xAC 0xAD 0xAE 0xAF )(list 0x280 0x284 0x288 0x28C 0x290 0x294 0x298 0x29C 0x2A0 0x2A4 0x2A8 0x2AC 0x2B0 0x2B4 0x2B8 0x2BC ) group.long ($2+0x800)++0x3 line.long 0x0 "REGG2_DOM_$1,Assign domain for SCR registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xB0 0xB1 0xB2 0xB3 0xB4 0xB5 0xB6 0xB7 0xB8 0xB9 0xBA 0xBB 0xBC 0xBD 0xBE 0xBF )(list 0x2C0 0x2C4 0x2C8 0x2CC 0x2D0 0x2D4 0x2D8 0x2DC 0x2E0 0x2E4 0x2E8 0x2EC 0x2F0 0x2F4 0x2F8 0x2FC ) group.long ($2+0x800)++0x3 line.long 0x0 "REGG2_DOM_$1,Assign domain for SCR registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xC0 0xC1 0xC2 0xC3 0xC4 0xC5 0xC6 0xC7 0xC8 0xC9 0xCA 0xCB 0xCC 0xCD 0xCE 0xCF )(list 0x300 0x304 0x308 0x30C 0x310 0x314 0x318 0x31C 0x320 0x324 0x328 0x32C 0x330 0x334 0x338 0x33C ) group.long ($2+0x800)++0x3 line.long 0x0 "REGG2_DOM_$1,Assign domain for SCR registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xD0 0xD1 0xD2 0xD3 0xD4 0xD5 0xD6 0xD7 0xD8 0xD9 0xDA 0xDB 0xDC 0xDD 0xDE 0xDF )(list 0x340 0x344 0x348 0x34C 0x350 0x354 0x358 0x35C 0x360 0x364 0x368 0x36C 0x370 0x374 0x378 0x37C ) group.long ($2+0x800)++0x3 line.long 0x0 "REGG2_DOM_$1,Assign domain for SCR registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xE0 0xE1 0xE2 0xE3 0xE4 0xE5 0xE6 0xE7 0xE8 0xE9 0xEA 0xEB 0xEC 0xED 0xEE 0xEF )(list 0x380 0x384 0x388 0x38C 0x390 0x394 0x398 0x39C 0x3A0 0x3A4 0x3A8 0x3AC 0x3B0 0x3B4 0x3B8 0x3BC ) group.long ($2+0x800)++0x3 line.long 0x0 "REGG2_DOM_$1,Assign domain for SCR registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xF0 0xF1 0xF2 0xF3 0xF4 0xF5 0xF6 0xF7 0xF8 0xF9 0xFA 0xFB 0xFC 0xFD 0xFE 0xFF )(list 0x3C0 0x3C4 0x3C8 0x3CC 0x3D0 0x3D4 0x3D8 0x3DC 0x3E0 0x3E4 0x3E8 0x3EC 0x3F0 0x3F4 0x3F8 0x3FC ) group.long ($2+0x800)++0x3 line.long 0x0 "REGG2_DOM_$1,Assign domain for SCR registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x4 0x8 0xC 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C ) group.long ($2+0xC00)++0x3 line.long 0x0 "REGG3_DOM_$1,Assign domain for SCR registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1A 0x1B 0x1C 0x1D 0x1E 0x1F )(list 0x40 0x44 0x48 0x4C 0x50 0x54 0x58 0x5C 0x60 0x64 0x68 0x6C 0x70 0x74 0x78 0x7C ) group.long ($2+0xC00)++0x3 line.long 0x0 "REGG3_DOM_$1,Assign domain for SCR registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x20 0x21 0x22 0x23 0x24 0x25 0x26 0x27 0x28 0x29 0x2A 0x2B 0x2C 0x2D 0x2E 0x2F )(list 0x80 0x84 0x88 0x8C 0x90 0x94 0x98 0x9C 0xA0 0xA4 0xA8 0xAC 0xB0 0xB4 0xB8 0xBC ) group.long ($2+0xC00)++0x3 line.long 0x0 "REGG3_DOM_$1,Assign domain for SCR registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x30 0x31 0x32 0x33 0x34 0x35 0x36 0x37 0x38 0x39 0x3A 0x3B 0x3C 0x3D 0x3E 0x3F )(list 0xC0 0xC4 0xC8 0xCC 0xD0 0xD4 0xD8 0xDC 0xE0 0xE4 0xE8 0xEC 0xF0 0xF4 0xF8 0xFC ) group.long ($2+0xC00)++0x3 line.long 0x0 "REGG3_DOM_$1,Assign domain for SCR registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x40 0x41 0x42 0x43 0x44 0x45 0x46 0x47 0x48 0x49 0x4A 0x4B 0x4C 0x4D 0x4E 0x4F )(list 0x100 0x104 0x108 0x10C 0x110 0x114 0x118 0x11C 0x120 0x124 0x128 0x12C 0x130 0x134 0x138 0x13C ) group.long ($2+0xC00)++0x3 line.long 0x0 "REGG3_DOM_$1,Assign domain for SCR registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x50 0x51 0x52 0x53 0x54 0x55 0x56 0x57 0x58 0x59 0x5A 0x5B 0x5C 0x5D 0x5E 0x5F )(list 0x140 0x144 0x148 0x14C 0x150 0x154 0x158 0x15C 0x160 0x164 0x168 0x16C 0x170 0x174 0x178 0x17C ) group.long ($2+0xC00)++0x3 line.long 0x0 "REGG3_DOM_$1,Assign domain for SCR registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x60 0x61 0x62 0x63 0x64 0x65 0x66 0x67 0x68 0x69 0x6A 0x6B 0x6C 0x6D 0x6E 0x6F )(list 0x180 0x184 0x188 0x18C 0x190 0x194 0x198 0x19C 0x1A0 0x1A4 0x1A8 0x1AC 0x1B0 0x1B4 0x1B8 0x1BC ) group.long ($2+0xC00)++0x3 line.long 0x0 "REGG3_DOM_$1,Assign domain for SCR registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x70 0x71 0x72 0x73 0x74 0x75 0x76 0x77 0x78 0x79 0x7A 0x7B 0x7C 0x7D 0x7E 0x7F )(list 0x1C0 0x1C4 0x1C8 0x1CC 0x1D0 0x1D4 0x1D8 0x1DC 0x1E0 0x1E4 0x1E8 0x1EC 0x1F0 0x1F4 0x1F8 0x1FC ) group.long ($2+0xC00)++0x3 line.long 0x0 "REGG3_DOM_$1,Assign domain for SCR registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x80 0x81 0x82 0x83 0x84 0x85 0x86 0x87 0x88 0x89 0x8A 0x8B 0x8C 0x8D 0x8E 0x8F )(list 0x200 0x204 0x208 0x20C 0x210 0x214 0x218 0x21C 0x220 0x224 0x228 0x22C 0x230 0x234 0x238 0x23C ) group.long ($2+0xC00)++0x3 line.long 0x0 "REGG3_DOM_$1,Assign domain for SCR registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x90 0x91 0x92 0x93 0x94 0x95 0x96 0x97 0x98 0x99 0x9A 0x9B 0x9C 0x9D 0x9E 0x9F )(list 0x240 0x244 0x248 0x24C 0x250 0x254 0x258 0x25C 0x260 0x264 0x268 0x26C 0x270 0x274 0x278 0x27C ) group.long ($2+0xC00)++0x3 line.long 0x0 "REGG3_DOM_$1,Assign domain for SCR registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xA0 0xA1 0xA2 0xA3 0xA4 0xA5 0xA6 0xA7 0xA8 0xA9 0xAA 0xAB 0xAC 0xAD 0xAE 0xAF )(list 0x280 0x284 0x288 0x28C 0x290 0x294 0x298 0x29C 0x2A0 0x2A4 0x2A8 0x2AC 0x2B0 0x2B4 0x2B8 0x2BC ) group.long ($2+0xC00)++0x3 line.long 0x0 "REGG3_DOM_$1,Assign domain for SCR registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xB0 0xB1 0xB2 0xB3 0xB4 0xB5 0xB6 0xB7 0xB8 0xB9 0xBA 0xBB 0xBC 0xBD 0xBE 0xBF )(list 0x2C0 0x2C4 0x2C8 0x2CC 0x2D0 0x2D4 0x2D8 0x2DC 0x2E0 0x2E4 0x2E8 0x2EC 0x2F0 0x2F4 0x2F8 0x2FC ) group.long ($2+0xC00)++0x3 line.long 0x0 "REGG3_DOM_$1,Assign domain for SCR registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xC0 0xC1 0xC2 0xC3 0xC4 0xC5 0xC6 0xC7 0xC8 0xC9 0xCA 0xCB 0xCC 0xCD 0xCE 0xCF )(list 0x300 0x304 0x308 0x30C 0x310 0x314 0x318 0x31C 0x320 0x324 0x328 0x32C 0x330 0x334 0x338 0x33C ) group.long ($2+0xC00)++0x3 line.long 0x0 "REGG3_DOM_$1,Assign domain for SCR registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xD0 0xD1 0xD2 0xD3 0xD4 0xD5 0xD6 0xD7 0xD8 0xD9 0xDA 0xDB 0xDC 0xDD 0xDE 0xDF )(list 0x340 0x344 0x348 0x34C 0x350 0x354 0x358 0x35C 0x360 0x364 0x368 0x36C 0x370 0x374 0x378 0x37C ) group.long ($2+0xC00)++0x3 line.long 0x0 "REGG3_DOM_$1,Assign domain for SCR registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xE0 0xE1 0xE2 0xE3 0xE4 0xE5 0xE6 0xE7 0xE8 0xE9 0xEA 0xEB 0xEC 0xED 0xEE 0xEF )(list 0x380 0x384 0x388 0x38C 0x390 0x394 0x398 0x39C 0x3A0 0x3A4 0x3A8 0x3AC 0x3B0 0x3B4 0x3B8 0x3BC ) group.long ($2+0xC00)++0x3 line.long 0x0 "REGG3_DOM_$1,Assign domain for SCR registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xF0 0xF1 0xF2 0xF3 0xF4 0xF5 0xF6 0xF7 0xF8 0xF9 0xFA 0xFB 0xFC 0xFD 0xFE 0xFF )(list 0x3C0 0x3C4 0x3C8 0x3CC 0x3D0 0x3D4 0x3D8 0x3DC 0x3E0 0x3E4 0x3E8 0x3EC 0x3F0 0x3F4 0x3F8 0x3FC ) group.long ($2+0xC00)++0x3 line.long 0x0 "REGG3_DOM_$1,Assign domain for SCR registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x4 0x8 0xC 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C ) group.long ($2+0x1000)++0x3 line.long 0x0 "REGG4_DOM_$1,Assign domain for RSTGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1A 0x1B 0x1C 0x1D 0x1E 0x1F )(list 0x40 0x44 0x48 0x4C 0x50 0x54 0x58 0x5C 0x60 0x64 0x68 0x6C 0x70 0x74 0x78 0x7C ) group.long ($2+0x1000)++0x3 line.long 0x0 "REGG4_DOM_$1,Assign domain for RSTGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x20 0x21 0x22 0x23 0x24 0x25 0x26 0x27 0x28 0x29 0x2A 0x2B 0x2C 0x2D 0x2E 0x2F )(list 0x80 0x84 0x88 0x8C 0x90 0x94 0x98 0x9C 0xA0 0xA4 0xA8 0xAC 0xB0 0xB4 0xB8 0xBC ) group.long ($2+0x1000)++0x3 line.long 0x0 "REGG4_DOM_$1,Assign domain for RSTGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x30 0x31 0x32 0x33 0x34 0x35 0x36 0x37 0x38 0x39 0x3A 0x3B 0x3C 0x3D 0x3E 0x3F )(list 0xC0 0xC4 0xC8 0xCC 0xD0 0xD4 0xD8 0xDC 0xE0 0xE4 0xE8 0xEC 0xF0 0xF4 0xF8 0xFC ) group.long ($2+0x1000)++0x3 line.long 0x0 "REGG4_DOM_$1,Assign domain for RSTGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x40 0x41 0x42 0x43 0x44 0x45 0x46 0x47 0x48 0x49 0x4A 0x4B 0x4C 0x4D 0x4E 0x4F )(list 0x100 0x104 0x108 0x10C 0x110 0x114 0x118 0x11C 0x120 0x124 0x128 0x12C 0x130 0x134 0x138 0x13C ) group.long ($2+0x1000)++0x3 line.long 0x0 "REGG4_DOM_$1,Assign domain for RSTGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x50 0x51 0x52 0x53 0x54 0x55 0x56 0x57 0x58 0x59 0x5A 0x5B 0x5C 0x5D 0x5E 0x5F )(list 0x140 0x144 0x148 0x14C 0x150 0x154 0x158 0x15C 0x160 0x164 0x168 0x16C 0x170 0x174 0x178 0x17C ) group.long ($2+0x1000)++0x3 line.long 0x0 "REGG4_DOM_$1,Assign domain for RSTGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x60 0x61 0x62 0x63 0x64 0x65 0x66 0x67 0x68 0x69 0x6A 0x6B 0x6C 0x6D 0x6E 0x6F )(list 0x180 0x184 0x188 0x18C 0x190 0x194 0x198 0x19C 0x1A0 0x1A4 0x1A8 0x1AC 0x1B0 0x1B4 0x1B8 0x1BC ) group.long ($2+0x1000)++0x3 line.long 0x0 "REGG4_DOM_$1,Assign domain for RSTGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x70 0x71 0x72 0x73 0x74 0x75 0x76 0x77 0x78 0x79 0x7A 0x7B 0x7C 0x7D 0x7E 0x7F )(list 0x1C0 0x1C4 0x1C8 0x1CC 0x1D0 0x1D4 0x1D8 0x1DC 0x1E0 0x1E4 0x1E8 0x1EC 0x1F0 0x1F4 0x1F8 0x1FC ) group.long ($2+0x1000)++0x3 line.long 0x0 "REGG4_DOM_$1,Assign domain for RSTGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x80 0x81 0x82 0x83 0x84 0x85 0x86 0x87 0x88 0x89 0x8A 0x8B 0x8C 0x8D 0x8E 0x8F )(list 0x200 0x204 0x208 0x20C 0x210 0x214 0x218 0x21C 0x220 0x224 0x228 0x22C 0x230 0x234 0x238 0x23C ) group.long ($2+0x1000)++0x3 line.long 0x0 "REGG4_DOM_$1,Assign domain for RSTGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x90 0x91 0x92 0x93 0x94 0x95 0x96 0x97 0x98 0x99 0x9A 0x9B 0x9C 0x9D 0x9E 0x9F )(list 0x240 0x244 0x248 0x24C 0x250 0x254 0x258 0x25C 0x260 0x264 0x268 0x26C 0x270 0x274 0x278 0x27C ) group.long ($2+0x1000)++0x3 line.long 0x0 "REGG4_DOM_$1,Assign domain for RSTGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xA0 0xA1 0xA2 0xA3 0xA4 0xA5 0xA6 0xA7 0xA8 0xA9 0xAA 0xAB 0xAC 0xAD 0xAE 0xAF )(list 0x280 0x284 0x288 0x28C 0x290 0x294 0x298 0x29C 0x2A0 0x2A4 0x2A8 0x2AC 0x2B0 0x2B4 0x2B8 0x2BC ) group.long ($2+0x1000)++0x3 line.long 0x0 "REGG4_DOM_$1,Assign domain for RSTGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xB0 0xB1 0xB2 0xB3 0xB4 0xB5 0xB6 0xB7 0xB8 0xB9 0xBA 0xBB 0xBC 0xBD 0xBE 0xBF )(list 0x2C0 0x2C4 0x2C8 0x2CC 0x2D0 0x2D4 0x2D8 0x2DC 0x2E0 0x2E4 0x2E8 0x2EC 0x2F0 0x2F4 0x2F8 0x2FC ) group.long ($2+0x1000)++0x3 line.long 0x0 "REGG4_DOM_$1,Assign domain for RSTGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xC0 0xC1 0xC2 0xC3 0xC4 0xC5 0xC6 0xC7 0xC8 0xC9 0xCA 0xCB 0xCC 0xCD 0xCE 0xCF )(list 0x300 0x304 0x308 0x30C 0x310 0x314 0x318 0x31C 0x320 0x324 0x328 0x32C 0x330 0x334 0x338 0x33C ) group.long ($2+0x1000)++0x3 line.long 0x0 "REGG4_DOM_$1,Assign domain for RSTGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xD0 0xD1 0xD2 0xD3 0xD4 0xD5 0xD6 0xD7 0xD8 0xD9 0xDA 0xDB 0xDC 0xDD 0xDE 0xDF )(list 0x340 0x344 0x348 0x34C 0x350 0x354 0x358 0x35C 0x360 0x364 0x368 0x36C 0x370 0x374 0x378 0x37C ) group.long ($2+0x1000)++0x3 line.long 0x0 "REGG4_DOM_$1,Assign domain for RSTGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xE0 0xE1 0xE2 0xE3 0xE4 0xE5 0xE6 0xE7 0xE8 0xE9 0xEA 0xEB 0xEC 0xED 0xEE 0xEF )(list 0x380 0x384 0x388 0x38C 0x390 0x394 0x398 0x39C 0x3A0 0x3A4 0x3A8 0x3AC 0x3B0 0x3B4 0x3B8 0x3BC ) group.long ($2+0x1000)++0x3 line.long 0x0 "REGG4_DOM_$1,Assign domain for RSTGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xF0 0xF1 0xF2 0xF3 0xF4 0xF5 0xF6 0xF7 0xF8 0xF9 0xFA 0xFB 0xFC 0xFD 0xFE 0xFF )(list 0x3C0 0x3C4 0x3C8 0x3CC 0x3D0 0x3D4 0x3D8 0x3DC 0x3E0 0x3E4 0x3E8 0x3EC 0x3F0 0x3F4 0x3F8 0x3FC ) group.long ($2+0x1000)++0x3 line.long 0x0 "REGG4_DOM_$1,Assign domain for RSTGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x4 0x8 0xC 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C ) group.long ($2+0x1400)++0x3 line.long 0x0 "REGG5_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1A 0x1B 0x1C 0x1D 0x1E 0x1F )(list 0x40 0x44 0x48 0x4C 0x50 0x54 0x58 0x5C 0x60 0x64 0x68 0x6C 0x70 0x74 0x78 0x7C ) group.long ($2+0x1400)++0x3 line.long 0x0 "REGG5_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x20 0x21 0x22 0x23 0x24 0x25 0x26 0x27 0x28 0x29 0x2A 0x2B 0x2C 0x2D 0x2E 0x2F )(list 0x80 0x84 0x88 0x8C 0x90 0x94 0x98 0x9C 0xA0 0xA4 0xA8 0xAC 0xB0 0xB4 0xB8 0xBC ) group.long ($2+0x1400)++0x3 line.long 0x0 "REGG5_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x30 0x31 0x32 0x33 0x34 0x35 0x36 0x37 0x38 0x39 0x3A 0x3B 0x3C 0x3D 0x3E 0x3F )(list 0xC0 0xC4 0xC8 0xCC 0xD0 0xD4 0xD8 0xDC 0xE0 0xE4 0xE8 0xEC 0xF0 0xF4 0xF8 0xFC ) group.long ($2+0x1400)++0x3 line.long 0x0 "REGG5_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x40 0x41 0x42 0x43 0x44 0x45 0x46 0x47 0x48 0x49 0x4A 0x4B 0x4C 0x4D 0x4E 0x4F )(list 0x100 0x104 0x108 0x10C 0x110 0x114 0x118 0x11C 0x120 0x124 0x128 0x12C 0x130 0x134 0x138 0x13C ) group.long ($2+0x1400)++0x3 line.long 0x0 "REGG5_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x50 0x51 0x52 0x53 0x54 0x55 0x56 0x57 0x58 0x59 0x5A 0x5B 0x5C 0x5D 0x5E 0x5F )(list 0x140 0x144 0x148 0x14C 0x150 0x154 0x158 0x15C 0x160 0x164 0x168 0x16C 0x170 0x174 0x178 0x17C ) group.long ($2+0x1400)++0x3 line.long 0x0 "REGG5_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x60 0x61 0x62 0x63 0x64 0x65 0x66 0x67 0x68 0x69 0x6A 0x6B 0x6C 0x6D 0x6E 0x6F )(list 0x180 0x184 0x188 0x18C 0x190 0x194 0x198 0x19C 0x1A0 0x1A4 0x1A8 0x1AC 0x1B0 0x1B4 0x1B8 0x1BC ) group.long ($2+0x1400)++0x3 line.long 0x0 "REGG5_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x70 0x71 0x72 0x73 0x74 0x75 0x76 0x77 0x78 0x79 0x7A 0x7B 0x7C 0x7D 0x7E 0x7F )(list 0x1C0 0x1C4 0x1C8 0x1CC 0x1D0 0x1D4 0x1D8 0x1DC 0x1E0 0x1E4 0x1E8 0x1EC 0x1F0 0x1F4 0x1F8 0x1FC ) group.long ($2+0x1400)++0x3 line.long 0x0 "REGG5_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x80 0x81 0x82 0x83 0x84 0x85 0x86 0x87 0x88 0x89 0x8A 0x8B 0x8C 0x8D 0x8E 0x8F )(list 0x200 0x204 0x208 0x20C 0x210 0x214 0x218 0x21C 0x220 0x224 0x228 0x22C 0x230 0x234 0x238 0x23C ) group.long ($2+0x1400)++0x3 line.long 0x0 "REGG5_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x90 0x91 0x92 0x93 0x94 0x95 0x96 0x97 0x98 0x99 0x9A 0x9B 0x9C 0x9D 0x9E 0x9F )(list 0x240 0x244 0x248 0x24C 0x250 0x254 0x258 0x25C 0x260 0x264 0x268 0x26C 0x270 0x274 0x278 0x27C ) group.long ($2+0x1400)++0x3 line.long 0x0 "REGG5_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xA0 0xA1 0xA2 0xA3 0xA4 0xA5 0xA6 0xA7 0xA8 0xA9 0xAA 0xAB 0xAC 0xAD 0xAE 0xAF )(list 0x280 0x284 0x288 0x28C 0x290 0x294 0x298 0x29C 0x2A0 0x2A4 0x2A8 0x2AC 0x2B0 0x2B4 0x2B8 0x2BC ) group.long ($2+0x1400)++0x3 line.long 0x0 "REGG5_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xB0 0xB1 0xB2 0xB3 0xB4 0xB5 0xB6 0xB7 0xB8 0xB9 0xBA 0xBB 0xBC 0xBD 0xBE 0xBF )(list 0x2C0 0x2C4 0x2C8 0x2CC 0x2D0 0x2D4 0x2D8 0x2DC 0x2E0 0x2E4 0x2E8 0x2EC 0x2F0 0x2F4 0x2F8 0x2FC ) group.long ($2+0x1400)++0x3 line.long 0x0 "REGG5_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xC0 0xC1 0xC2 0xC3 0xC4 0xC5 0xC6 0xC7 0xC8 0xC9 0xCA 0xCB 0xCC 0xCD 0xCE 0xCF )(list 0x300 0x304 0x308 0x30C 0x310 0x314 0x318 0x31C 0x320 0x324 0x328 0x32C 0x330 0x334 0x338 0x33C ) group.long ($2+0x1400)++0x3 line.long 0x0 "REGG5_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xD0 0xD1 0xD2 0xD3 0xD4 0xD5 0xD6 0xD7 0xD8 0xD9 0xDA 0xDB 0xDC 0xDD 0xDE 0xDF )(list 0x340 0x344 0x348 0x34C 0x350 0x354 0x358 0x35C 0x360 0x364 0x368 0x36C 0x370 0x374 0x378 0x37C ) group.long ($2+0x1400)++0x3 line.long 0x0 "REGG5_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xE0 0xE1 0xE2 0xE3 0xE4 0xE5 0xE6 0xE7 0xE8 0xE9 0xEA 0xEB 0xEC 0xED 0xEE 0xEF )(list 0x380 0x384 0x388 0x38C 0x390 0x394 0x398 0x39C 0x3A0 0x3A4 0x3A8 0x3AC 0x3B0 0x3B4 0x3B8 0x3BC ) group.long ($2+0x1400)++0x3 line.long 0x0 "REGG5_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xF0 0xF1 0xF2 0xF3 0xF4 0xF5 0xF6 0xF7 0xF8 0xF9 0xFA 0xFB 0xFC 0xFD 0xFE 0xFF )(list 0x3C0 0x3C4 0x3C8 0x3CC 0x3D0 0x3D4 0x3D8 0x3DC 0x3E0 0x3E4 0x3E8 0x3EC 0x3F0 0x3F4 0x3F8 0x3FC ) group.long ($2+0x1400)++0x3 line.long 0x0 "REGG5_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x4 0x8 0xC 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C ) group.long ($2+0x1800)++0x3 line.long 0x0 "REGG6_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1A 0x1B 0x1C 0x1D 0x1E 0x1F )(list 0x40 0x44 0x48 0x4C 0x50 0x54 0x58 0x5C 0x60 0x64 0x68 0x6C 0x70 0x74 0x78 0x7C ) group.long ($2+0x1800)++0x3 line.long 0x0 "REGG6_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x20 0x21 0x22 0x23 0x24 0x25 0x26 0x27 0x28 0x29 0x2A 0x2B 0x2C 0x2D 0x2E 0x2F )(list 0x80 0x84 0x88 0x8C 0x90 0x94 0x98 0x9C 0xA0 0xA4 0xA8 0xAC 0xB0 0xB4 0xB8 0xBC ) group.long ($2+0x1800)++0x3 line.long 0x0 "REGG6_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x30 0x31 0x32 0x33 0x34 0x35 0x36 0x37 0x38 0x39 0x3A 0x3B 0x3C 0x3D 0x3E 0x3F )(list 0xC0 0xC4 0xC8 0xCC 0xD0 0xD4 0xD8 0xDC 0xE0 0xE4 0xE8 0xEC 0xF0 0xF4 0xF8 0xFC ) group.long ($2+0x1800)++0x3 line.long 0x0 "REGG6_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x40 0x41 0x42 0x43 0x44 0x45 0x46 0x47 0x48 0x49 0x4A 0x4B 0x4C 0x4D 0x4E 0x4F )(list 0x100 0x104 0x108 0x10C 0x110 0x114 0x118 0x11C 0x120 0x124 0x128 0x12C 0x130 0x134 0x138 0x13C ) group.long ($2+0x1800)++0x3 line.long 0x0 "REGG6_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x50 0x51 0x52 0x53 0x54 0x55 0x56 0x57 0x58 0x59 0x5A 0x5B 0x5C 0x5D 0x5E 0x5F )(list 0x140 0x144 0x148 0x14C 0x150 0x154 0x158 0x15C 0x160 0x164 0x168 0x16C 0x170 0x174 0x178 0x17C ) group.long ($2+0x1800)++0x3 line.long 0x0 "REGG6_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x60 0x61 0x62 0x63 0x64 0x65 0x66 0x67 0x68 0x69 0x6A 0x6B 0x6C 0x6D 0x6E 0x6F )(list 0x180 0x184 0x188 0x18C 0x190 0x194 0x198 0x19C 0x1A0 0x1A4 0x1A8 0x1AC 0x1B0 0x1B4 0x1B8 0x1BC ) group.long ($2+0x1800)++0x3 line.long 0x0 "REGG6_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x70 0x71 0x72 0x73 0x74 0x75 0x76 0x77 0x78 0x79 0x7A 0x7B 0x7C 0x7D 0x7E 0x7F )(list 0x1C0 0x1C4 0x1C8 0x1CC 0x1D0 0x1D4 0x1D8 0x1DC 0x1E0 0x1E4 0x1E8 0x1EC 0x1F0 0x1F4 0x1F8 0x1FC ) group.long ($2+0x1800)++0x3 line.long 0x0 "REGG6_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x80 0x81 0x82 0x83 0x84 0x85 0x86 0x87 0x88 0x89 0x8A 0x8B 0x8C 0x8D 0x8E 0x8F )(list 0x200 0x204 0x208 0x20C 0x210 0x214 0x218 0x21C 0x220 0x224 0x228 0x22C 0x230 0x234 0x238 0x23C ) group.long ($2+0x1800)++0x3 line.long 0x0 "REGG6_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x90 0x91 0x92 0x93 0x94 0x95 0x96 0x97 0x98 0x99 0x9A 0x9B 0x9C 0x9D 0x9E 0x9F )(list 0x240 0x244 0x248 0x24C 0x250 0x254 0x258 0x25C 0x260 0x264 0x268 0x26C 0x270 0x274 0x278 0x27C ) group.long ($2+0x1800)++0x3 line.long 0x0 "REGG6_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xA0 0xA1 0xA2 0xA3 0xA4 0xA5 0xA6 0xA7 0xA8 0xA9 0xAA 0xAB 0xAC 0xAD 0xAE 0xAF )(list 0x280 0x284 0x288 0x28C 0x290 0x294 0x298 0x29C 0x2A0 0x2A4 0x2A8 0x2AC 0x2B0 0x2B4 0x2B8 0x2BC ) group.long ($2+0x1800)++0x3 line.long 0x0 "REGG6_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xB0 0xB1 0xB2 0xB3 0xB4 0xB5 0xB6 0xB7 0xB8 0xB9 0xBA 0xBB 0xBC 0xBD 0xBE 0xBF )(list 0x2C0 0x2C4 0x2C8 0x2CC 0x2D0 0x2D4 0x2D8 0x2DC 0x2E0 0x2E4 0x2E8 0x2EC 0x2F0 0x2F4 0x2F8 0x2FC ) group.long ($2+0x1800)++0x3 line.long 0x0 "REGG6_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xC0 0xC1 0xC2 0xC3 0xC4 0xC5 0xC6 0xC7 0xC8 0xC9 0xCA 0xCB 0xCC 0xCD 0xCE 0xCF )(list 0x300 0x304 0x308 0x30C 0x310 0x314 0x318 0x31C 0x320 0x324 0x328 0x32C 0x330 0x334 0x338 0x33C ) group.long ($2+0x1800)++0x3 line.long 0x0 "REGG6_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xD0 0xD1 0xD2 0xD3 0xD4 0xD5 0xD6 0xD7 0xD8 0xD9 0xDA 0xDB 0xDC 0xDD 0xDE 0xDF )(list 0x340 0x344 0x348 0x34C 0x350 0x354 0x358 0x35C 0x360 0x364 0x368 0x36C 0x370 0x374 0x378 0x37C ) group.long ($2+0x1800)++0x3 line.long 0x0 "REGG6_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xE0 0xE1 0xE2 0xE3 0xE4 0xE5 0xE6 0xE7 0xE8 0xE9 0xEA 0xEB 0xEC 0xED 0xEE 0xEF )(list 0x380 0x384 0x388 0x38C 0x390 0x394 0x398 0x39C 0x3A0 0x3A4 0x3A8 0x3AC 0x3B0 0x3B4 0x3B8 0x3BC ) group.long ($2+0x1800)++0x3 line.long 0x0 "REGG6_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xF0 0xF1 0xF2 0xF3 0xF4 0xF5 0xF6 0xF7 0xF8 0xF9 0xFA 0xFB 0xFC 0xFD 0xFE 0xFF )(list 0x3C0 0x3C4 0x3C8 0x3CC 0x3D0 0x3D4 0x3D8 0x3DC 0x3E0 0x3E4 0x3E8 0x3EC 0x3F0 0x3F4 0x3F8 0x3FC ) group.long ($2+0x1800)++0x3 line.long 0x0 "REGG6_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x4 0x8 0xC 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C ) group.long ($2+0x1C00)++0x3 line.long 0x0 "REGG7_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1A 0x1B 0x1C 0x1D 0x1E 0x1F )(list 0x40 0x44 0x48 0x4C 0x50 0x54 0x58 0x5C 0x60 0x64 0x68 0x6C 0x70 0x74 0x78 0x7C ) group.long ($2+0x1C00)++0x3 line.long 0x0 "REGG7_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x20 0x21 0x22 0x23 0x24 0x25 0x26 0x27 0x28 0x29 0x2A 0x2B 0x2C 0x2D 0x2E 0x2F )(list 0x80 0x84 0x88 0x8C 0x90 0x94 0x98 0x9C 0xA0 0xA4 0xA8 0xAC 0xB0 0xB4 0xB8 0xBC ) group.long ($2+0x1C00)++0x3 line.long 0x0 "REGG7_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x30 0x31 0x32 0x33 0x34 0x35 0x36 0x37 0x38 0x39 0x3A 0x3B 0x3C 0x3D 0x3E 0x3F )(list 0xC0 0xC4 0xC8 0xCC 0xD0 0xD4 0xD8 0xDC 0xE0 0xE4 0xE8 0xEC 0xF0 0xF4 0xF8 0xFC ) group.long ($2+0x1C00)++0x3 line.long 0x0 "REGG7_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x40 0x41 0x42 0x43 0x44 0x45 0x46 0x47 0x48 0x49 0x4A 0x4B 0x4C 0x4D 0x4E 0x4F )(list 0x100 0x104 0x108 0x10C 0x110 0x114 0x118 0x11C 0x120 0x124 0x128 0x12C 0x130 0x134 0x138 0x13C ) group.long ($2+0x1C00)++0x3 line.long 0x0 "REGG7_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x50 0x51 0x52 0x53 0x54 0x55 0x56 0x57 0x58 0x59 0x5A 0x5B 0x5C 0x5D 0x5E 0x5F )(list 0x140 0x144 0x148 0x14C 0x150 0x154 0x158 0x15C 0x160 0x164 0x168 0x16C 0x170 0x174 0x178 0x17C ) group.long ($2+0x1C00)++0x3 line.long 0x0 "REGG7_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x60 0x61 0x62 0x63 0x64 0x65 0x66 0x67 0x68 0x69 0x6A 0x6B 0x6C 0x6D 0x6E 0x6F )(list 0x180 0x184 0x188 0x18C 0x190 0x194 0x198 0x19C 0x1A0 0x1A4 0x1A8 0x1AC 0x1B0 0x1B4 0x1B8 0x1BC ) group.long ($2+0x1C00)++0x3 line.long 0x0 "REGG7_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x70 0x71 0x72 0x73 0x74 0x75 0x76 0x77 0x78 0x79 0x7A 0x7B 0x7C 0x7D 0x7E 0x7F )(list 0x1C0 0x1C4 0x1C8 0x1CC 0x1D0 0x1D4 0x1D8 0x1DC 0x1E0 0x1E4 0x1E8 0x1EC 0x1F0 0x1F4 0x1F8 0x1FC ) group.long ($2+0x1C00)++0x3 line.long 0x0 "REGG7_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x80 0x81 0x82 0x83 0x84 0x85 0x86 0x87 0x88 0x89 0x8A 0x8B 0x8C 0x8D 0x8E 0x8F )(list 0x200 0x204 0x208 0x20C 0x210 0x214 0x218 0x21C 0x220 0x224 0x228 0x22C 0x230 0x234 0x238 0x23C ) group.long ($2+0x1C00)++0x3 line.long 0x0 "REGG7_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x90 0x91 0x92 0x93 0x94 0x95 0x96 0x97 0x98 0x99 0x9A 0x9B 0x9C 0x9D 0x9E 0x9F )(list 0x240 0x244 0x248 0x24C 0x250 0x254 0x258 0x25C 0x260 0x264 0x268 0x26C 0x270 0x274 0x278 0x27C ) group.long ($2+0x1C00)++0x3 line.long 0x0 "REGG7_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xA0 0xA1 0xA2 0xA3 0xA4 0xA5 0xA6 0xA7 0xA8 0xA9 0xAA 0xAB 0xAC 0xAD 0xAE 0xAF )(list 0x280 0x284 0x288 0x28C 0x290 0x294 0x298 0x29C 0x2A0 0x2A4 0x2A8 0x2AC 0x2B0 0x2B4 0x2B8 0x2BC ) group.long ($2+0x1C00)++0x3 line.long 0x0 "REGG7_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xB0 0xB1 0xB2 0xB3 0xB4 0xB5 0xB6 0xB7 0xB8 0xB9 0xBA 0xBB 0xBC 0xBD 0xBE 0xBF )(list 0x2C0 0x2C4 0x2C8 0x2CC 0x2D0 0x2D4 0x2D8 0x2DC 0x2E0 0x2E4 0x2E8 0x2EC 0x2F0 0x2F4 0x2F8 0x2FC ) group.long ($2+0x1C00)++0x3 line.long 0x0 "REGG7_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xC0 0xC1 0xC2 0xC3 0xC4 0xC5 0xC6 0xC7 0xC8 0xC9 0xCA 0xCB 0xCC 0xCD 0xCE 0xCF )(list 0x300 0x304 0x308 0x30C 0x310 0x314 0x318 0x31C 0x320 0x324 0x328 0x32C 0x330 0x334 0x338 0x33C ) group.long ($2+0x1C00)++0x3 line.long 0x0 "REGG7_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xD0 0xD1 0xD2 0xD3 0xD4 0xD5 0xD6 0xD7 0xD8 0xD9 0xDA 0xDB 0xDC 0xDD 0xDE 0xDF )(list 0x340 0x344 0x348 0x34C 0x350 0x354 0x358 0x35C 0x360 0x364 0x368 0x36C 0x370 0x374 0x378 0x37C ) group.long ($2+0x1C00)++0x3 line.long 0x0 "REGG7_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xE0 0xE1 0xE2 0xE3 0xE4 0xE5 0xE6 0xE7 0xE8 0xE9 0xEA 0xEB 0xEC 0xED 0xEE 0xEF )(list 0x380 0x384 0x388 0x38C 0x390 0x394 0x398 0x39C 0x3A0 0x3A4 0x3A8 0x3AC 0x3B0 0x3B4 0x3B8 0x3BC ) group.long ($2+0x1C00)++0x3 line.long 0x0 "REGG7_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xF0 0xF1 0xF2 0xF3 0xF4 0xF5 0xF6 0xF7 0xF8 0xF9 0xFA 0xFB 0xFC 0xFD 0xFE 0xFF )(list 0x3C0 0x3C4 0x3C8 0x3CC 0x3D0 0x3D4 0x3D8 0x3DC 0x3E0 0x3E4 0x3E8 0x3EC 0x3F0 0x3F4 0x3F8 0x3FC ) group.long ($2+0x1C00)++0x3 line.long 0x0 "REGG7_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end group.long 0x2000++0x17 line.long 0x0 "GLB_CTL,This register provides global enable settings for permission control." bitfld.long 0x0 5. "DOM_CFG_LOCK,Lock write for DOM_CFG_MODE bit." "0,1" bitfld.long 0x0 4. "DOM_CFG_MODE,When enabled all the source setting can be configured by master from domain 0 if it is not locked. When disabled only resource manager can configure the permission of the resource." "0,1" bitfld.long 0x0 3. "PERCK_DIS_LOCK,Lock write for PERCK_DIS" "0,1" bitfld.long 0x0 2. "PERCK_DIS,All the permission check disable." "0,1" newline bitfld.long 0x0 1. "DOM_PRO_LOCK,Lock write for DOM_PRO_EN bit." "0,1" bitfld.long 0x0 0. "DOM_PRO_EN,When disabled no domain access permission check" "0,1" line.long 0x4 "RES_MGR,Resource manager register. This regster is used to assign resource manager for global resource access control" bitfld.long 0x4 17. "MID_LOCK,Lock write for MID_EN and MID_LOW and MID_HIG registers." "0,1" bitfld.long 0x4 16. "MID_EN,Master ID check enable" "0,1" bitfld.long 0x4 15. "PRI_PER_LOCK,Lock write for PRI_PER and PRI_PER_EN" "0,1" bitfld.long 0x4 13.--14. "PRI_PER,Resource manager privileged access permission. bit0 for privileged access bit1 for user access" "0,1,2,3" newline bitfld.long 0x4 12. "PRI_PER_EN,Resource manager privileged access permission enable." "0,1" bitfld.long 0x4 11. "SEC_PER_LOCK,Lock for SEC_PER and SEC_PER_LOCK" "0,1" bitfld.long 0x4 9.--10. "SEC_PER,Resource manager secure access permission. bit 0 for secure access bit 1 for non-secure access" "0,1,2,3" bitfld.long 0x4 8. "SEC_PER_EN,Resource manager secure permission enable" "0,1" bitfld.long 0x4 7. "DID_LOCK,Lock write for DID_EN and DID" "0,1" newline hexmask.long.byte 0x4 3.--6. 1. "DID,Resource manager domain ID" bitfld.long 0x4 2. "DID_EN,Resource manager Domain ID enable" "0,1" bitfld.long 0x4 1. "RES_MGR_EN_LOCK,Lock for RES_MGR_EN" "0,1" bitfld.long 0x4 0. "RES_MGR_EN,Resource manager enable. When the bit is disable there is no resource manager." "0,1" line.long 0x8 "RES_MGR_MA0,This register is used to assign master 0~31 as resource manager." hexmask.long 0x8 0.--31. 1. "MID,Assign master 0~31 for resource manager" line.long 0xC "RES_MGR_MA1,This register is used to assign master 32~63 as resource manager." hexmask.long 0xC 0.--31. 1. "MID,Indicate if master 32~63 is resource manager." line.long 0x10 "RES_MGR_MA2,This register is used to assign master 64~95 as resource manager." hexmask.long 0x10 0.--31. 1. "MID,Indicate if master 64~95 is resource manager." line.long 0x14 "RES_MGR_MA3,This register is used to assign master 96~127 as resource manager." hexmask.long 0x14 0.--31. 1. "MID,Indicate if master 96~127 is resource manager." repeat 8. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 )(list 0x0 0x14 0x28 0x3C 0x50 0x64 0x78 0x8C ) group.long ($2+0x2100)++0x3 line.long 0x0 "GRP_MGR_$1,Group Manager Register. This register is used to assign group manager for each domain" bitfld.long 0x0 17. "MID_LOCK,Lock write for MID_EN and MID_LOW and MID_HIG registers." "0,1" bitfld.long 0x0 16. "MID_EN,Master ID check enable" "0,1" bitfld.long 0x0 15. "PRI_PER_LOCK,Lock write for PRI_PER and PRI_PER_EN" "0,1" bitfld.long 0x0 13.--14. "PRI_PER,Group manager privileged access permission. bit0 for privileged access bit1 for user access" "0,1,2,3" newline bitfld.long 0x0 12. "PRI_PER_EN,Group manager privileged access permission enable." "0,1" bitfld.long 0x0 11. "SEC_PER_LOCK,Lock for SEC_PER and SEC_PER_LOCK" "0,1" bitfld.long 0x0 9.--10. "SEC_PER,Group manager secure access permission. bit 0 for secure access bit 1 for non-secure access" "0,1,2,3" bitfld.long 0x0 8. "SEC_PER_EN,Group manager secure permission enable" "0,1" bitfld.long 0x0 7. "DID_LOCK,Lock write for DID_EN and DID" "0,1" newline hexmask.long.byte 0x0 3.--6. 1. "DID,Group manager domain ID" bitfld.long 0x0 2. "DID_EN,Group manager Domain ID enable" "0,1" bitfld.long 0x0 1. "GRP_MGR_EN_LOCK,Lock write for GPR_MGR_EN" "0,1" bitfld.long 0x0 0. "GRP_MGR_EN,Group manager enable. When the bit is disable there is no resource manager." "0,1" repeat.end repeat 8. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 )(list 0x0 0x14 0x28 0x3C 0x50 0x64 0x78 0x8C ) group.long ($2+0x2104)++0x3 line.long 0x0 "GRP_MGR_MA0_$1,Assign master 0~31 for group manager 0" hexmask.long 0x0 0.--31. 1. "MID,Assign master 0~31 for resource manager" repeat.end repeat 8. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 )(list 0x0 0x14 0x28 0x3C 0x50 0x64 0x78 0x8C ) group.long ($2+0x2108)++0x3 line.long 0x0 "GRP_MGR_MA1_$1,Assign master 32~63 for group manager 0" hexmask.long 0x0 0.--31. 1. "MID,Indicate if master 32~63 is resource manager." repeat.end repeat 8. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 )(list 0x0 0x14 0x28 0x3C 0x50 0x64 0x78 0x8C ) group.long ($2+0x210C)++0x3 line.long 0x0 "GRP_MGR_MA2_$1,Assign master 64~95 for group manager 0" hexmask.long 0x0 0.--31. 1. "MID,Indicate if master 64~95 is resource manager." repeat.end repeat 8. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 )(list 0x0 0x14 0x28 0x3C 0x50 0x64 0x78 0x8C ) group.long ($2+0x2110)++0x3 line.long 0x0 "GRP_MGR_MA3_$1,Assign master 96~127 for group manager 0" hexmask.long 0x0 0.--31. 1. "MID,Indicate if master 96~127 is resource manager." repeat.end group.long 0x2200++0x3 line.long 0x0 "DOM_GID_0,Indicate which group domain 0 belong to" bitfld.long 0x0 3. "LOCK,Lock write for GID" "0,1" bitfld.long 0x0 0.--2. "GID,Group ID" "0,1,2,3,4,5,6,7" repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x18 0x30 0x48 0x60 0x78 0x90 0xA8 0xC0 0xD8 0xF0 0x108 0x120 0x138 0x150 0x168 ) group.long ($2+0x2204)++0x3 line.long 0x0 "DOM_OWN_$1,Assign owner for function domain 0." bitfld.long 0x0 17. "MID_LOCK,Lock write for MID_EN and MID_LOW and MID_HIG registers." "0,1" bitfld.long 0x0 16. "MID_EN,Master ID check enable" "0,1" bitfld.long 0x0 15. "PRI_PER_LOCK,Lock write for PRI_PER and PRI_PER_EN" "0,1" bitfld.long 0x0 13.--14. "PRI_PER,Group manager privileged access permission. bit0 for privileged access bit1 for user access" "0,1,2,3" newline bitfld.long 0x0 12. "PRI_PER_EN,Group manager privileged access permission enable." "0,1" bitfld.long 0x0 11. "SEC_PER_LOCK,Lock for SEC_PER and SEC_PER_LOCK" "0,1" bitfld.long 0x0 9.--10. "SEC_PER,Domain owner secure access permission. bit 0 for secure access bit 1 for non-secure access" "0,1,2,3" bitfld.long 0x0 8. "SEC_PER_EN,Domain owner secure permission enable" "0,1" newline bitfld.long 0x0 1. "DOM_OWN_EN_LOCK,Lock for DOM_OWN_EN" "0,1" bitfld.long 0x0 0. "DOM_OWN_EN,Domain owner enable. When the bit is disable there is no domain owner." "0,1" repeat.end repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x18 0x30 0x48 0x60 0x78 0x90 0xA8 0xC0 0xD8 0xF0 0x108 0x120 0x138 0x150 0x168 ) group.long ($2+0x2208)++0x3 line.long 0x0 "DOM_OWN_MA0_$1,Assign master 0~31 for domain owner 0" hexmask.long 0x0 0.--31. 1. "MID,Assign master 0~31 for resource manager" repeat.end repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x18 0x30 0x48 0x60 0x78 0x90 0xA8 0xC0 0xD8 0xF0 0x108 0x120 0x138 0x150 0x168 ) group.long ($2+0x220C)++0x3 line.long 0x0 "DOM_OWN_MA1_$1,Assign master 32~63 for domain owner 0" hexmask.long 0x0 0.--31. 1. "MID,Indicate if master 32~63 is resource manager." repeat.end repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x18 0x30 0x48 0x60 0x78 0x90 0xA8 0xC0 0xD8 0xF0 0x108 0x120 0x138 0x150 0x168 ) group.long ($2+0x2210)++0x3 line.long 0x0 "DOM_OWN_MA2_$1,Assign master 64~95 for domain owner 0" hexmask.long 0x0 0.--31. 1. "MID,Indicate if master 64~95 is resource manager." repeat.end repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x18 0x30 0x48 0x60 0x78 0x90 0xA8 0xC0 0xD8 0xF0 0x108 0x120 0x138 0x150 0x168 ) group.long ($2+0x2214)++0x3 line.long 0x0 "DOM_OWN_MA3_$1,Assign master 96~127 for domain owner 0" hexmask.long 0x0 0.--31. 1. "MID,Indicate if master 96~127 is resource manager." repeat.end group.long 0x2218++0x3 line.long 0x0 "DOM_GID_1,Indicate which group domain 1 belong to" bitfld.long 0x0 3. "LOCK,Lock write for GID" "0,1" bitfld.long 0x0 0.--2. "GID,Group ID" "0,1,2,3,4,5,6,7" group.long 0x2230++0x3 line.long 0x0 "DOM_GID_2,Indicate which group domain 2 belong to" bitfld.long 0x0 3. "LOCK,Lock write for GID" "0,1" bitfld.long 0x0 0.--2. "GID,Group ID" "0,1,2,3,4,5,6,7" group.long 0x2248++0x3 line.long 0x0 "DOM_GID_3,Indicate which group domain 3 belong to" bitfld.long 0x0 3. "LOCK,Lock write for GID" "0,1" bitfld.long 0x0 0.--2. "GID,Group ID" "0,1,2,3,4,5,6,7" group.long 0x2260++0x3 line.long 0x0 "DOM_GID_4,Indicate which group domain 4 belong to" bitfld.long 0x0 3. "LOCK,Lock write for GID" "0,1" bitfld.long 0x0 0.--2. "GID,Group ID" "0,1,2,3,4,5,6,7" group.long 0x2278++0x3 line.long 0x0 "DOM_GID_5,Indicate which group domain 5 belong to" bitfld.long 0x0 3. "LOCK,Lock write for GID" "0,1" bitfld.long 0x0 0.--2. "GID,Group ID" "0,1,2,3,4,5,6,7" group.long 0x2290++0x3 line.long 0x0 "DOM_GID_6,Indicate which group domain 6 belong to" bitfld.long 0x0 3. "LOCK,Lock write for GID" "0,1" bitfld.long 0x0 0.--2. "GID,Group ID" "0,1,2,3,4,5,6,7" group.long 0x22A8++0x3 line.long 0x0 "DOM_GID_7,Indicate which group domain 7 belong to" bitfld.long 0x0 3. "LOCK,Lock write for GID" "0,1" bitfld.long 0x0 0.--2. "GID,Group ID" "0,1,2,3,4,5,6,7" group.long 0x22C0++0x3 line.long 0x0 "DOM_GID_8,Indicate which group domain 8 belong to" bitfld.long 0x0 3. "LOCK,Lock write for GID" "0,1" bitfld.long 0x0 0.--2. "GID,Group ID" "0,1,2,3,4,5,6,7" group.long 0x22D8++0x3 line.long 0x0 "DOM_GID_9,Indicate which group domain 9 belong to" bitfld.long 0x0 3. "LOCK,Lock write for GID" "0,1" bitfld.long 0x0 0.--2. "GID,Group ID" "0,1,2,3,4,5,6,7" group.long 0x22F0++0x3 line.long 0x0 "DOM_GID_10,Indicate which group domain 10 belong to" bitfld.long 0x0 3. "LOCK,Lock write for GID" "0,1" bitfld.long 0x0 0.--2. "GID,Group ID" "0,1,2,3,4,5,6,7" group.long 0x2308++0x3 line.long 0x0 "DOM_GID_11,Indicate which group domain 11 belong to" bitfld.long 0x0 3. "LOCK,Lock write for GID" "0,1" bitfld.long 0x0 0.--2. "GID,Group ID" "0,1,2,3,4,5,6,7" group.long 0x2320++0x3 line.long 0x0 "DOM_GID_12,Indicate which group domain 12 belong to" bitfld.long 0x0 3. "LOCK,Lock write for GID" "0,1" bitfld.long 0x0 0.--2. "GID,Group ID" "0,1,2,3,4,5,6,7" group.long 0x2338++0x3 line.long 0x0 "DOM_GID_13,Indicate which group domain 13 belong to" bitfld.long 0x0 3. "LOCK,Lock write for GID" "0,1" bitfld.long 0x0 0.--2. "GID,Group ID" "0,1,2,3,4,5,6,7" group.long 0x2350++0x3 line.long 0x0 "DOM_GID_14,Indicate which group domain 14 belong to" bitfld.long 0x0 3. "LOCK,Lock write for GID" "0,1" bitfld.long 0x0 0.--2. "GID,Group ID" "0,1,2,3,4,5,6,7" group.long 0x2368++0x3 line.long 0x0 "DOM_GID_15,Indicate which group domain 15 belong to" bitfld.long 0x0 3. "LOCK,Lock write for GID" "0,1" bitfld.long 0x0 0.--2. "GID,Group ID" "0,1,2,3,4,5,6,7" repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x34 0x68 0x9C 0xD0 0x104 0x138 0x16C 0x1A0 0x1D4 0x208 0x23C 0x270 0x2A4 0x2D8 0x30C ) group.long ($2+0x2400)++0x3 line.long 0x0 "DOM_PER0_$1,Domain Permission Control. It can be only configured by resource manager and domain owner." bitfld.long 0x0 31. "DOM7_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 29.--30. "DOM7_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 28. "DOM7_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 27. "DOM6_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 25.--26. "DOM6_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" newline bitfld.long 0x0 24. "DOM6_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 23. "DOM5_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 21.--22. "DOM5_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 20. "DOM5_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 19. "DOM4_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" newline bitfld.long 0x0 17.--18. "DOM4_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM4_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 15. "DOM3_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 13.--14. "DOM3_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 12. "DOM3_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" newline bitfld.long 0x0 11. "DOM2_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 9.--10. "DOM2_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM2_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 7. "DOM1_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 5.--6. "DOM1_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" newline bitfld.long 0x0 4. "DOM1_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 3. "DOM0_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 1.--2. "DOM0_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM0_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" repeat.end repeat 16. (list 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1A 0x1B 0x1C 0x1D 0x1E 0x1F )(list 0x340 0x374 0x3A8 0x3DC 0x410 0x444 0x478 0x4AC 0x4E0 0x514 0x548 0x57C 0x5B0 0x5E4 0x618 0x64C ) group.long ($2+0x2400)++0x3 line.long 0x0 "DOM_PER0_$1,Domain Permission Control. It can be only configured by resource manager and domain owner." bitfld.long 0x0 31. "DOM7_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 29.--30. "DOM7_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 28. "DOM7_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 27. "DOM6_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 25.--26. "DOM6_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" newline bitfld.long 0x0 24. "DOM6_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 23. "DOM5_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 21.--22. "DOM5_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 20. "DOM5_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 19. "DOM4_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" newline bitfld.long 0x0 17.--18. "DOM4_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM4_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 15. "DOM3_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 13.--14. "DOM3_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 12. "DOM3_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" newline bitfld.long 0x0 11. "DOM2_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 9.--10. "DOM2_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM2_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 7. "DOM1_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 5.--6. "DOM1_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" newline bitfld.long 0x0 4. "DOM1_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 3. "DOM0_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 1.--2. "DOM0_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM0_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" repeat.end repeat 16. (list 0x20 0x21 0x22 0x23 0x24 0x25 0x26 0x27 0x28 0x29 0x2A 0x2B 0x2C 0x2D 0x2E 0x2F )(list 0x680 0x6B4 0x6E8 0x71C 0x750 0x784 0x7B8 0x7EC 0x820 0x854 0x888 0x8BC 0x8F0 0x924 0x958 0x98C ) group.long ($2+0x2400)++0x3 line.long 0x0 "DOM_PER0_$1,Domain Permission Control. It can be only configured by resource manager and domain owner." bitfld.long 0x0 31. "DOM7_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 29.--30. "DOM7_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 28. "DOM7_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 27. "DOM6_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 25.--26. "DOM6_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" newline bitfld.long 0x0 24. "DOM6_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 23. "DOM5_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 21.--22. "DOM5_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 20. "DOM5_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 19. "DOM4_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" newline bitfld.long 0x0 17.--18. "DOM4_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM4_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 15. "DOM3_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 13.--14. "DOM3_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 12. "DOM3_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" newline bitfld.long 0x0 11. "DOM2_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 9.--10. "DOM2_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM2_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 7. "DOM1_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 5.--6. "DOM1_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" newline bitfld.long 0x0 4. "DOM1_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 3. "DOM0_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 1.--2. "DOM0_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM0_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" repeat.end repeat 16. (list 0x30 0x31 0x32 0x33 0x34 0x35 0x36 0x37 0x38 0x39 0x3A 0x3B 0x3C 0x3D 0x3E 0x3F )(list 0x9C0 0x9F4 0xA28 0xA5C 0xA90 0xAC4 0xAF8 0xB2C 0xB60 0xB94 0xBC8 0xBFC 0xC30 0xC64 0xC98 0xCCC ) group.long ($2+0x2400)++0x3 line.long 0x0 "DOM_PER0_$1,Domain Permission Control. It can be only configured by resource manager and domain owner." bitfld.long 0x0 31. "DOM7_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 29.--30. "DOM7_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 28. "DOM7_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 27. "DOM6_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 25.--26. "DOM6_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" newline bitfld.long 0x0 24. "DOM6_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 23. "DOM5_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 21.--22. "DOM5_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 20. "DOM5_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 19. "DOM4_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" newline bitfld.long 0x0 17.--18. "DOM4_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM4_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 15. "DOM3_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 13.--14. "DOM3_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 12. "DOM3_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" newline bitfld.long 0x0 11. "DOM2_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 9.--10. "DOM2_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM2_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 7. "DOM1_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 5.--6. "DOM1_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" newline bitfld.long 0x0 4. "DOM1_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 3. "DOM0_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 1.--2. "DOM0_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM0_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" repeat.end repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x34 0x68 0x9C 0xD0 0x104 0x138 0x16C 0x1A0 0x1D4 0x208 0x23C 0x270 0x2A4 0x2D8 0x30C ) group.long ($2+0x2404)++0x3 line.long 0x0 "DOM_PER1_$1,Domain Permission Control. It can be only configured by resource manager and domain owner." bitfld.long 0x0 31. "DOM15_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 29.--30. "DOM15_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 28. "DOM15_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 27. "DOM14_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 25.--26. "DOM14_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" newline bitfld.long 0x0 24. "DOM14_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 23. "DOM13_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 21.--22. "DOM13_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 20. "DOM13_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 19. "DOM12_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" newline bitfld.long 0x0 17.--18. "DOM12_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM12_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 15. "DOM11_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 13.--14. "DOM11_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 12. "DOM11_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" newline bitfld.long 0x0 11. "DOM10_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 9.--10. "DOM10_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM10_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 7. "DOM9_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 5.--6. "DOM9_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" newline bitfld.long 0x0 4. "DOM9_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 3. "DOM8_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 1.--2. "DOM8_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM8_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" repeat.end repeat 16. (list 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1A 0x1B 0x1C 0x1D 0x1E 0x1F )(list 0x340 0x374 0x3A8 0x3DC 0x410 0x444 0x478 0x4AC 0x4E0 0x514 0x548 0x57C 0x5B0 0x5E4 0x618 0x64C ) group.long ($2+0x2404)++0x3 line.long 0x0 "DOM_PER1_$1,Domain Permission Control. It can be only configured by resource manager and domain owner." bitfld.long 0x0 31. "DOM15_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 29.--30. "DOM15_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 28. "DOM15_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 27. "DOM14_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 25.--26. "DOM14_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" newline bitfld.long 0x0 24. "DOM14_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 23. "DOM13_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 21.--22. "DOM13_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 20. "DOM13_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 19. "DOM12_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" newline bitfld.long 0x0 17.--18. "DOM12_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM12_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 15. "DOM11_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 13.--14. "DOM11_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 12. "DOM11_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" newline bitfld.long 0x0 11. "DOM10_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 9.--10. "DOM10_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM10_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 7. "DOM9_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 5.--6. "DOM9_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" newline bitfld.long 0x0 4. "DOM9_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 3. "DOM8_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 1.--2. "DOM8_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM8_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" repeat.end repeat 16. (list 0x20 0x21 0x22 0x23 0x24 0x25 0x26 0x27 0x28 0x29 0x2A 0x2B 0x2C 0x2D 0x2E 0x2F )(list 0x680 0x6B4 0x6E8 0x71C 0x750 0x784 0x7B8 0x7EC 0x820 0x854 0x888 0x8BC 0x8F0 0x924 0x958 0x98C ) group.long ($2+0x2404)++0x3 line.long 0x0 "DOM_PER1_$1,Domain Permission Control. It can be only configured by resource manager and domain owner." bitfld.long 0x0 31. "DOM15_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 29.--30. "DOM15_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 28. "DOM15_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 27. "DOM14_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 25.--26. "DOM14_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" newline bitfld.long 0x0 24. "DOM14_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 23. "DOM13_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 21.--22. "DOM13_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 20. "DOM13_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 19. "DOM12_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" newline bitfld.long 0x0 17.--18. "DOM12_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM12_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 15. "DOM11_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 13.--14. "DOM11_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 12. "DOM11_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" newline bitfld.long 0x0 11. "DOM10_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 9.--10. "DOM10_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM10_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 7. "DOM9_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 5.--6. "DOM9_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" newline bitfld.long 0x0 4. "DOM9_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 3. "DOM8_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 1.--2. "DOM8_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM8_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" repeat.end repeat 16. (list 0x30 0x31 0x32 0x33 0x34 0x35 0x36 0x37 0x38 0x39 0x3A 0x3B 0x3C 0x3D 0x3E 0x3F )(list 0x9C0 0x9F4 0xA28 0xA5C 0xA90 0xAC4 0xAF8 0xB2C 0xB60 0xB94 0xBC8 0xBFC 0xC30 0xC64 0xC98 0xCCC ) group.long ($2+0x2404)++0x3 line.long 0x0 "DOM_PER1_$1,Domain Permission Control. It can be only configured by resource manager and domain owner." bitfld.long 0x0 31. "DOM15_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 29.--30. "DOM15_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 28. "DOM15_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 27. "DOM14_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 25.--26. "DOM14_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" newline bitfld.long 0x0 24. "DOM14_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 23. "DOM13_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 21.--22. "DOM13_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 20. "DOM13_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 19. "DOM12_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" newline bitfld.long 0x0 17.--18. "DOM12_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM12_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 15. "DOM11_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 13.--14. "DOM11_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 12. "DOM11_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" newline bitfld.long 0x0 11. "DOM10_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 9.--10. "DOM10_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM10_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 7. "DOM9_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 5.--6. "DOM9_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" newline bitfld.long 0x0 4. "DOM9_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 3. "DOM8_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 1.--2. "DOM8_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM8_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" repeat.end repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x34 0x68 0x9C 0xD0 0x104 0x138 0x16C 0x1A0 0x1D4 0x208 0x23C 0x270 0x2A4 0x2D8 0x30C ) group.long ($2+0x2408)++0x3 line.long 0x0 "SEC_PER0_$1,This register is only used for resource manager to control secure access permission." bitfld.long 0x0 31. "DOM3_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM3_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM3_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM3_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM2_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM2_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM2_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM2_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM1_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM1_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM1_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM1_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM0_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM0_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM0_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM0_SEC_EN,Domain secure permission control enable" "0,1" repeat.end repeat 16. (list 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1A 0x1B 0x1C 0x1D 0x1E 0x1F )(list 0x340 0x374 0x3A8 0x3DC 0x410 0x444 0x478 0x4AC 0x4E0 0x514 0x548 0x57C 0x5B0 0x5E4 0x618 0x64C ) group.long ($2+0x2408)++0x3 line.long 0x0 "SEC_PER0_$1,This register is only used for resource manager to control secure access permission." bitfld.long 0x0 31. "DOM3_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM3_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM3_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM3_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM2_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM2_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM2_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM2_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM1_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM1_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM1_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM1_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM0_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM0_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM0_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM0_SEC_EN,Domain secure permission control enable" "0,1" repeat.end repeat 16. (list 0x20 0x21 0x22 0x23 0x24 0x25 0x26 0x27 0x28 0x29 0x2A 0x2B 0x2C 0x2D 0x2E 0x2F )(list 0x680 0x6B4 0x6E8 0x71C 0x750 0x784 0x7B8 0x7EC 0x820 0x854 0x888 0x8BC 0x8F0 0x924 0x958 0x98C ) group.long ($2+0x2408)++0x3 line.long 0x0 "SEC_PER0_$1,This register is only used for resource manager to control secure access permission." bitfld.long 0x0 31. "DOM3_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM3_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM3_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM3_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM2_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM2_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM2_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM2_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM1_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM1_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM1_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM1_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM0_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM0_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM0_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM0_SEC_EN,Domain secure permission control enable" "0,1" repeat.end repeat 16. (list 0x30 0x31 0x32 0x33 0x34 0x35 0x36 0x37 0x38 0x39 0x3A 0x3B 0x3C 0x3D 0x3E 0x3F )(list 0x9C0 0x9F4 0xA28 0xA5C 0xA90 0xAC4 0xAF8 0xB2C 0xB60 0xB94 0xBC8 0xBFC 0xC30 0xC64 0xC98 0xCCC ) group.long ($2+0x2408)++0x3 line.long 0x0 "SEC_PER0_$1,This register is only used for resource manager to control secure access permission." bitfld.long 0x0 31. "DOM3_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM3_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM3_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM3_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM2_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM2_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM2_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM2_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM1_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM1_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM1_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM1_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM0_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM0_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM0_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM0_SEC_EN,Domain secure permission control enable" "0,1" repeat.end repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x34 0x68 0x9C 0xD0 0x104 0x138 0x16C 0x1A0 0x1D4 0x208 0x23C 0x270 0x2A4 0x2D8 0x30C ) group.long ($2+0x240C)++0x3 line.long 0x0 "SEC_PER1_$1,This register is only used for resource manager to control secure access permission." bitfld.long 0x0 31. "DOM7_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM7_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM7_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM7_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM6_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM6_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM6_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM6_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM5_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM5_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM5_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM5_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM4_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM4_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM4_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM4_SEC_EN,Domain secure permission control enable" "0,1" repeat.end repeat 16. (list 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1A 0x1B 0x1C 0x1D 0x1E 0x1F )(list 0x340 0x374 0x3A8 0x3DC 0x410 0x444 0x478 0x4AC 0x4E0 0x514 0x548 0x57C 0x5B0 0x5E4 0x618 0x64C ) group.long ($2+0x240C)++0x3 line.long 0x0 "SEC_PER1_$1,This register is only used for resource manager to control secure access permission." bitfld.long 0x0 31. "DOM7_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM7_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM7_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM7_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM6_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM6_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM6_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM6_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM5_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM5_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM5_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM5_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM4_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM4_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM4_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM4_SEC_EN,Domain secure permission control enable" "0,1" repeat.end repeat 16. (list 0x20 0x21 0x22 0x23 0x24 0x25 0x26 0x27 0x28 0x29 0x2A 0x2B 0x2C 0x2D 0x2E 0x2F )(list 0x680 0x6B4 0x6E8 0x71C 0x750 0x784 0x7B8 0x7EC 0x820 0x854 0x888 0x8BC 0x8F0 0x924 0x958 0x98C ) group.long ($2+0x240C)++0x3 line.long 0x0 "SEC_PER1_$1,This register is only used for resource manager to control secure access permission." bitfld.long 0x0 31. "DOM7_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM7_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM7_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM7_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM6_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM6_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM6_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM6_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM5_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM5_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM5_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM5_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM4_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM4_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM4_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM4_SEC_EN,Domain secure permission control enable" "0,1" repeat.end repeat 16. (list 0x30 0x31 0x32 0x33 0x34 0x35 0x36 0x37 0x38 0x39 0x3A 0x3B 0x3C 0x3D 0x3E 0x3F )(list 0x9C0 0x9F4 0xA28 0xA5C 0xA90 0xAC4 0xAF8 0xB2C 0xB60 0xB94 0xBC8 0xBFC 0xC30 0xC64 0xC98 0xCCC ) group.long ($2+0x240C)++0x3 line.long 0x0 "SEC_PER1_$1,This register is only used for resource manager to control secure access permission." bitfld.long 0x0 31. "DOM7_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM7_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM7_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM7_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM6_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM6_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM6_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM6_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM5_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM5_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM5_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM5_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM4_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM4_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM4_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM4_SEC_EN,Domain secure permission control enable" "0,1" repeat.end repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x34 0x68 0x9C 0xD0 0x104 0x138 0x16C 0x1A0 0x1D4 0x208 0x23C 0x270 0x2A4 0x2D8 0x30C ) group.long ($2+0x2410)++0x3 line.long 0x0 "SEC_PER2_$1,This register is only used for resource manager to control secure access permission." bitfld.long 0x0 31. "DOM11_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM11_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM11_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM11_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM10_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM10_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM10_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM10_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM9_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM9_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM9_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM9_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM8_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM8_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM8_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM8_SEC_EN,Domain secure permission control enable" "0,1" repeat.end repeat 16. (list 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1A 0x1B 0x1C 0x1D 0x1E 0x1F )(list 0x340 0x374 0x3A8 0x3DC 0x410 0x444 0x478 0x4AC 0x4E0 0x514 0x548 0x57C 0x5B0 0x5E4 0x618 0x64C ) group.long ($2+0x2410)++0x3 line.long 0x0 "SEC_PER2_$1,This register is only used for resource manager to control secure access permission." bitfld.long 0x0 31. "DOM11_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM11_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM11_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM11_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM10_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM10_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM10_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM10_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM9_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM9_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM9_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM9_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM8_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM8_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM8_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM8_SEC_EN,Domain secure permission control enable" "0,1" repeat.end repeat 16. (list 0x20 0x21 0x22 0x23 0x24 0x25 0x26 0x27 0x28 0x29 0x2A 0x2B 0x2C 0x2D 0x2E 0x2F )(list 0x680 0x6B4 0x6E8 0x71C 0x750 0x784 0x7B8 0x7EC 0x820 0x854 0x888 0x8BC 0x8F0 0x924 0x958 0x98C ) group.long ($2+0x2410)++0x3 line.long 0x0 "SEC_PER2_$1,This register is only used for resource manager to control secure access permission." bitfld.long 0x0 31. "DOM11_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM11_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM11_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM11_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM10_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM10_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM10_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM10_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM9_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM9_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM9_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM9_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM8_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM8_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM8_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM8_SEC_EN,Domain secure permission control enable" "0,1" repeat.end repeat 16. (list 0x30 0x31 0x32 0x33 0x34 0x35 0x36 0x37 0x38 0x39 0x3A 0x3B 0x3C 0x3D 0x3E 0x3F )(list 0x9C0 0x9F4 0xA28 0xA5C 0xA90 0xAC4 0xAF8 0xB2C 0xB60 0xB94 0xBC8 0xBFC 0xC30 0xC64 0xC98 0xCCC ) group.long ($2+0x2410)++0x3 line.long 0x0 "SEC_PER2_$1,This register is only used for resource manager to control secure access permission." bitfld.long 0x0 31. "DOM11_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM11_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM11_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM11_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM10_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM10_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM10_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM10_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM9_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM9_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM9_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM9_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM8_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM8_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM8_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM8_SEC_EN,Domain secure permission control enable" "0,1" repeat.end repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x34 0x68 0x9C 0xD0 0x104 0x138 0x16C 0x1A0 0x1D4 0x208 0x23C 0x270 0x2A4 0x2D8 0x30C ) group.long ($2+0x2414)++0x3 line.long 0x0 "SEC_PER3_$1,This register is only used for resource manager to control secure access permission." bitfld.long 0x0 31. "DOM15_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM15_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM15_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM15_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM14_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM14_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM14_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM14_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM13_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM13_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM13_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM13_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM12_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM12_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM12_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM12_SEC_EN,Domain secure permission control enable" "0,1" repeat.end repeat 16. (list 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1A 0x1B 0x1C 0x1D 0x1E 0x1F )(list 0x340 0x374 0x3A8 0x3DC 0x410 0x444 0x478 0x4AC 0x4E0 0x514 0x548 0x57C 0x5B0 0x5E4 0x618 0x64C ) group.long ($2+0x2414)++0x3 line.long 0x0 "SEC_PER3_$1,This register is only used for resource manager to control secure access permission." bitfld.long 0x0 31. "DOM15_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM15_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM15_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM15_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM14_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM14_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM14_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM14_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM13_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM13_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM13_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM13_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM12_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM12_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM12_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM12_SEC_EN,Domain secure permission control enable" "0,1" repeat.end repeat 16. (list 0x20 0x21 0x22 0x23 0x24 0x25 0x26 0x27 0x28 0x29 0x2A 0x2B 0x2C 0x2D 0x2E 0x2F )(list 0x680 0x6B4 0x6E8 0x71C 0x750 0x784 0x7B8 0x7EC 0x820 0x854 0x888 0x8BC 0x8F0 0x924 0x958 0x98C ) group.long ($2+0x2414)++0x3 line.long 0x0 "SEC_PER3_$1,This register is only used for resource manager to control secure access permission." bitfld.long 0x0 31. "DOM15_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM15_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM15_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM15_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM14_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM14_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM14_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM14_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM13_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM13_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM13_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM13_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM12_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM12_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM12_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM12_SEC_EN,Domain secure permission control enable" "0,1" repeat.end repeat 16. (list 0x30 0x31 0x32 0x33 0x34 0x35 0x36 0x37 0x38 0x39 0x3A 0x3B 0x3C 0x3D 0x3E 0x3F )(list 0x9C0 0x9F4 0xA28 0xA5C 0xA90 0xAC4 0xAF8 0xB2C 0xB60 0xB94 0xBC8 0xBFC 0xC30 0xC64 0xC98 0xCCC ) group.long ($2+0x2414)++0x3 line.long 0x0 "SEC_PER3_$1,This register is only used for resource manager to control secure access permission." bitfld.long 0x0 31. "DOM15_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM15_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM15_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM15_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM14_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM14_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM14_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM14_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM13_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM13_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM13_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM13_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM12_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM12_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM12_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM12_SEC_EN,Domain secure permission control enable" "0,1" repeat.end repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x34 0x68 0x9C 0xD0 0x104 0x138 0x16C 0x1A0 0x1D4 0x208 0x23C 0x270 0x2A4 0x2D8 0x30C ) group.long ($2+0x2418)++0x3 line.long 0x0 "PRI_PER0_$1,This register is only used for resource manager to control privileged access permission." bitfld.long 0x0 31. "DOM3_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM3_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM3_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM3_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM2_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM2_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM2_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM2_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM1_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM1_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM1_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM1_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM0_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM0_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM0_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM0_PRI_EN,Domain privileged permission control enable" "0,1" repeat.end repeat 16. (list 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1A 0x1B 0x1C 0x1D 0x1E 0x1F )(list 0x340 0x374 0x3A8 0x3DC 0x410 0x444 0x478 0x4AC 0x4E0 0x514 0x548 0x57C 0x5B0 0x5E4 0x618 0x64C ) group.long ($2+0x2418)++0x3 line.long 0x0 "PRI_PER0_$1,This register is only used for resource manager to control privileged access permission." bitfld.long 0x0 31. "DOM3_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM3_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM3_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM3_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM2_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM2_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM2_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM2_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM1_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM1_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM1_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM1_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM0_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM0_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM0_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM0_PRI_EN,Domain privileged permission control enable" "0,1" repeat.end repeat 16. (list 0x20 0x21 0x22 0x23 0x24 0x25 0x26 0x27 0x28 0x29 0x2A 0x2B 0x2C 0x2D 0x2E 0x2F )(list 0x680 0x6B4 0x6E8 0x71C 0x750 0x784 0x7B8 0x7EC 0x820 0x854 0x888 0x8BC 0x8F0 0x924 0x958 0x98C ) group.long ($2+0x2418)++0x3 line.long 0x0 "PRI_PER0_$1,This register is only used for resource manager to control privileged access permission." bitfld.long 0x0 31. "DOM3_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM3_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM3_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM3_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM2_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM2_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM2_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM2_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM1_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM1_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM1_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM1_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM0_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM0_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM0_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM0_PRI_EN,Domain privileged permission control enable" "0,1" repeat.end repeat 16. (list 0x30 0x31 0x32 0x33 0x34 0x35 0x36 0x37 0x38 0x39 0x3A 0x3B 0x3C 0x3D 0x3E 0x3F )(list 0x9C0 0x9F4 0xA28 0xA5C 0xA90 0xAC4 0xAF8 0xB2C 0xB60 0xB94 0xBC8 0xBFC 0xC30 0xC64 0xC98 0xCCC ) group.long ($2+0x2418)++0x3 line.long 0x0 "PRI_PER0_$1,This register is only used for resource manager to control privileged access permission." bitfld.long 0x0 31. "DOM3_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM3_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM3_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM3_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM2_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM2_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM2_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM2_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM1_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM1_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM1_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM1_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM0_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM0_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM0_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM0_PRI_EN,Domain privileged permission control enable" "0,1" repeat.end repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x34 0x68 0x9C 0xD0 0x104 0x138 0x16C 0x1A0 0x1D4 0x208 0x23C 0x270 0x2A4 0x2D8 0x30C ) group.long ($2+0x241C)++0x3 line.long 0x0 "PRI_PER1_$1,This register is only used for resource manager to control privileged access permission." bitfld.long 0x0 31. "DOM7_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM7_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM7_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM7_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM6_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM6_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM6_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM6_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM5_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM5_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM5_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM5_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM4_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM4_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM4_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM4_PRI_EN,Domain privileged permission control enable" "0,1" repeat.end repeat 16. (list 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1A 0x1B 0x1C 0x1D 0x1E 0x1F )(list 0x340 0x374 0x3A8 0x3DC 0x410 0x444 0x478 0x4AC 0x4E0 0x514 0x548 0x57C 0x5B0 0x5E4 0x618 0x64C ) group.long ($2+0x241C)++0x3 line.long 0x0 "PRI_PER1_$1,This register is only used for resource manager to control privileged access permission." bitfld.long 0x0 31. "DOM7_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM7_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM7_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM7_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM6_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM6_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM6_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM6_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM5_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM5_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM5_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM5_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM4_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM4_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM4_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM4_PRI_EN,Domain privileged permission control enable" "0,1" repeat.end repeat 16. (list 0x20 0x21 0x22 0x23 0x24 0x25 0x26 0x27 0x28 0x29 0x2A 0x2B 0x2C 0x2D 0x2E 0x2F )(list 0x680 0x6B4 0x6E8 0x71C 0x750 0x784 0x7B8 0x7EC 0x820 0x854 0x888 0x8BC 0x8F0 0x924 0x958 0x98C ) group.long ($2+0x241C)++0x3 line.long 0x0 "PRI_PER1_$1,This register is only used for resource manager to control privileged access permission." bitfld.long 0x0 31. "DOM7_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM7_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM7_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM7_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM6_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM6_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM6_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM6_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM5_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM5_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM5_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM5_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM4_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM4_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM4_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM4_PRI_EN,Domain privileged permission control enable" "0,1" repeat.end repeat 16. (list 0x30 0x31 0x32 0x33 0x34 0x35 0x36 0x37 0x38 0x39 0x3A 0x3B 0x3C 0x3D 0x3E 0x3F )(list 0x9C0 0x9F4 0xA28 0xA5C 0xA90 0xAC4 0xAF8 0xB2C 0xB60 0xB94 0xBC8 0xBFC 0xC30 0xC64 0xC98 0xCCC ) group.long ($2+0x241C)++0x3 line.long 0x0 "PRI_PER1_$1,This register is only used for resource manager to control privileged access permission." bitfld.long 0x0 31. "DOM7_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM7_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM7_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM7_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM6_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM6_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM6_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM6_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM5_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM5_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM5_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM5_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM4_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM4_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM4_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM4_PRI_EN,Domain privileged permission control enable" "0,1" repeat.end repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x34 0x68 0x9C 0xD0 0x104 0x138 0x16C 0x1A0 0x1D4 0x208 0x23C 0x270 0x2A4 0x2D8 0x30C ) group.long ($2+0x2420)++0x3 line.long 0x0 "PRI_PER2_$1,This register is only used for resource manager to control privileged access permission." bitfld.long 0x0 31. "DOM11_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM11_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM11_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM11_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM10_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM10_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM10_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM10_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM9_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM9_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM9_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM9_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM8_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM8_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM8_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM8_PRI_EN,Domain privileged permission control enable" "0,1" repeat.end repeat 16. (list 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1A 0x1B 0x1C 0x1D 0x1E 0x1F )(list 0x340 0x374 0x3A8 0x3DC 0x410 0x444 0x478 0x4AC 0x4E0 0x514 0x548 0x57C 0x5B0 0x5E4 0x618 0x64C ) group.long ($2+0x2420)++0x3 line.long 0x0 "PRI_PER2_$1,This register is only used for resource manager to control privileged access permission." bitfld.long 0x0 31. "DOM11_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM11_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM11_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM11_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM10_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM10_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM10_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM10_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM9_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM9_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM9_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM9_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM8_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM8_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM8_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM8_PRI_EN,Domain privileged permission control enable" "0,1" repeat.end repeat 16. (list 0x20 0x21 0x22 0x23 0x24 0x25 0x26 0x27 0x28 0x29 0x2A 0x2B 0x2C 0x2D 0x2E 0x2F )(list 0x680 0x6B4 0x6E8 0x71C 0x750 0x784 0x7B8 0x7EC 0x820 0x854 0x888 0x8BC 0x8F0 0x924 0x958 0x98C ) group.long ($2+0x2420)++0x3 line.long 0x0 "PRI_PER2_$1,This register is only used for resource manager to control privileged access permission." bitfld.long 0x0 31. "DOM11_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM11_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM11_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM11_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM10_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM10_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM10_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM10_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM9_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM9_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM9_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM9_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM8_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM8_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM8_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM8_PRI_EN,Domain privileged permission control enable" "0,1" repeat.end repeat 16. (list 0x30 0x31 0x32 0x33 0x34 0x35 0x36 0x37 0x38 0x39 0x3A 0x3B 0x3C 0x3D 0x3E 0x3F )(list 0x9C0 0x9F4 0xA28 0xA5C 0xA90 0xAC4 0xAF8 0xB2C 0xB60 0xB94 0xBC8 0xBFC 0xC30 0xC64 0xC98 0xCCC ) group.long ($2+0x2420)++0x3 line.long 0x0 "PRI_PER2_$1,This register is only used for resource manager to control privileged access permission." bitfld.long 0x0 31. "DOM11_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM11_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM11_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM11_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM10_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM10_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM10_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM10_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM9_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM9_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM9_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM9_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM8_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM8_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM8_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM8_PRI_EN,Domain privileged permission control enable" "0,1" repeat.end repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x34 0x68 0x9C 0xD0 0x104 0x138 0x16C 0x1A0 0x1D4 0x208 0x23C 0x270 0x2A4 0x2D8 0x30C ) group.long ($2+0x2424)++0x3 line.long 0x0 "PRI_PER3_$1,This register is only used for resource manager to control privileged access permission." bitfld.long 0x0 31. "DOM15_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM15_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM15_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM15_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM14_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM14_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM14_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM14_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM13_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM13_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM13_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM13_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM12_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM12_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM12_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM12_PRI_EN,Domain privileged permission control enable" "0,1" repeat.end repeat 16. (list 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1A 0x1B 0x1C 0x1D 0x1E 0x1F )(list 0x340 0x374 0x3A8 0x3DC 0x410 0x444 0x478 0x4AC 0x4E0 0x514 0x548 0x57C 0x5B0 0x5E4 0x618 0x64C ) group.long ($2+0x2424)++0x3 line.long 0x0 "PRI_PER3_$1,This register is only used for resource manager to control privileged access permission." bitfld.long 0x0 31. "DOM15_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM15_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM15_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM15_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM14_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM14_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM14_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM14_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM13_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM13_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM13_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM13_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM12_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM12_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM12_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM12_PRI_EN,Domain privileged permission control enable" "0,1" repeat.end repeat 16. (list 0x20 0x21 0x22 0x23 0x24 0x25 0x26 0x27 0x28 0x29 0x2A 0x2B 0x2C 0x2D 0x2E 0x2F )(list 0x680 0x6B4 0x6E8 0x71C 0x750 0x784 0x7B8 0x7EC 0x820 0x854 0x888 0x8BC 0x8F0 0x924 0x958 0x98C ) group.long ($2+0x2424)++0x3 line.long 0x0 "PRI_PER3_$1,This register is only used for resource manager to control privileged access permission." bitfld.long 0x0 31. "DOM15_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM15_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM15_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM15_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM14_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM14_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM14_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM14_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM13_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM13_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM13_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM13_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM12_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM12_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM12_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM12_PRI_EN,Domain privileged permission control enable" "0,1" repeat.end repeat 16. (list 0x30 0x31 0x32 0x33 0x34 0x35 0x36 0x37 0x38 0x39 0x3A 0x3B 0x3C 0x3D 0x3E 0x3F )(list 0x9C0 0x9F4 0xA28 0xA5C 0xA90 0xAC4 0xAF8 0xB2C 0xB60 0xB94 0xBC8 0xBFC 0xC30 0xC64 0xC98 0xCCC ) group.long ($2+0x2424)++0x3 line.long 0x0 "PRI_PER3_$1,This register is only used for resource manager to control privileged access permission." bitfld.long 0x0 31. "DOM15_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM15_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM15_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM15_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM14_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM14_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM14_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM14_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM13_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM13_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM13_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM13_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM12_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM12_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM12_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM12_PRI_EN,Domain privileged permission control enable" "0,1" repeat.end repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x34 0x68 0x9C 0xD0 0x104 0x138 0x16C 0x1A0 0x1D4 0x208 0x23C 0x270 0x2A4 0x2D8 0x30C ) group.long ($2+0x2428)++0x3 line.long 0x0 "DOM_SEC_PER_$1,This register is only used for domain master to control secure access permission. When the domain master write this register. it only changes the secure permission for itself. When the domain master read this register. it gets permission.." bitfld.long 0x0 7. "DOM_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" newline bitfld.long 0x0 0. "DOM_SEC_EN,Domain secure permission control enable" "0,1" repeat.end repeat 16. (list 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1A 0x1B 0x1C 0x1D 0x1E 0x1F )(list 0x340 0x374 0x3A8 0x3DC 0x410 0x444 0x478 0x4AC 0x4E0 0x514 0x548 0x57C 0x5B0 0x5E4 0x618 0x64C ) group.long ($2+0x2428)++0x3 line.long 0x0 "DOM_SEC_PER_$1,This register is only used for domain master to control secure access permission. When the domain master write this register. it only changes the secure permission for itself. When the domain master read this register. it gets permission.." bitfld.long 0x0 7. "DOM_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" newline bitfld.long 0x0 0. "DOM_SEC_EN,Domain secure permission control enable" "0,1" repeat.end repeat 16. (list 0x20 0x21 0x22 0x23 0x24 0x25 0x26 0x27 0x28 0x29 0x2A 0x2B 0x2C 0x2D 0x2E 0x2F )(list 0x680 0x6B4 0x6E8 0x71C 0x750 0x784 0x7B8 0x7EC 0x820 0x854 0x888 0x8BC 0x8F0 0x924 0x958 0x98C ) group.long ($2+0x2428)++0x3 line.long 0x0 "DOM_SEC_PER_$1,This register is only used for domain master to control secure access permission. When the domain master write this register. it only changes the secure permission for itself. When the domain master read this register. it gets permission.." bitfld.long 0x0 7. "DOM_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" newline bitfld.long 0x0 0. "DOM_SEC_EN,Domain secure permission control enable" "0,1" repeat.end repeat 16. (list 0x30 0x31 0x32 0x33 0x34 0x35 0x36 0x37 0x38 0x39 0x3A 0x3B 0x3C 0x3D 0x3E 0x3F )(list 0x9C0 0x9F4 0xA28 0xA5C 0xA90 0xAC4 0xAF8 0xB2C 0xB60 0xB94 0xBC8 0xBFC 0xC30 0xC64 0xC98 0xCCC ) group.long ($2+0x2428)++0x3 line.long 0x0 "DOM_SEC_PER_$1,This register is only used for domain master to control secure access permission. When the domain master write this register. it only changes the secure permission for itself. When the domain master read this register. it gets permission.." bitfld.long 0x0 7. "DOM_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" newline bitfld.long 0x0 0. "DOM_SEC_EN,Domain secure permission control enable" "0,1" repeat.end repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x34 0x68 0x9C 0xD0 0x104 0x138 0x16C 0x1A0 0x1D4 0x208 0x23C 0x270 0x2A4 0x2D8 0x30C ) group.long ($2+0x242C)++0x3 line.long 0x0 "DOM_PRI_PER_$1,This register is only used for domain master to control secure access permission. When the domain master write this register. it only changes the secure permission for itself. When the domain master read this register. it gets permission.." bitfld.long 0x0 7. "DOM_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" newline bitfld.long 0x0 0. "DOM_PRI_EN,Domain privileged permission control enable" "0,1" repeat.end repeat 16. (list 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1A 0x1B 0x1C 0x1D 0x1E 0x1F )(list 0x340 0x374 0x3A8 0x3DC 0x410 0x444 0x478 0x4AC 0x4E0 0x514 0x548 0x57C 0x5B0 0x5E4 0x618 0x64C ) group.long ($2+0x242C)++0x3 line.long 0x0 "DOM_PRI_PER_$1,This register is only used for domain master to control secure access permission. When the domain master write this register. it only changes the secure permission for itself. When the domain master read this register. it gets permission.." bitfld.long 0x0 7. "DOM_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" newline bitfld.long 0x0 0. "DOM_PRI_EN,Domain privileged permission control enable" "0,1" repeat.end repeat 16. (list 0x20 0x21 0x22 0x23 0x24 0x25 0x26 0x27 0x28 0x29 0x2A 0x2B 0x2C 0x2D 0x2E 0x2F )(list 0x680 0x6B4 0x6E8 0x71C 0x750 0x784 0x7B8 0x7EC 0x820 0x854 0x888 0x8BC 0x8F0 0x924 0x958 0x98C ) group.long ($2+0x242C)++0x3 line.long 0x0 "DOM_PRI_PER_$1,This register is only used for domain master to control secure access permission. When the domain master write this register. it only changes the secure permission for itself. When the domain master read this register. it gets permission.." bitfld.long 0x0 7. "DOM_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" newline bitfld.long 0x0 0. "DOM_PRI_EN,Domain privileged permission control enable" "0,1" repeat.end repeat 16. (list 0x30 0x31 0x32 0x33 0x34 0x35 0x36 0x37 0x38 0x39 0x3A 0x3B 0x3C 0x3D 0x3E 0x3F )(list 0x9C0 0x9F4 0xA28 0xA5C 0xA90 0xAC4 0xAF8 0xB2C 0xB60 0xB94 0xBC8 0xBFC 0xC30 0xC64 0xC98 0xCCC ) group.long ($2+0x242C)++0x3 line.long 0x0 "DOM_PRI_PER_$1,This register is only used for domain master to control secure access permission. When the domain master write this register. it only changes the secure permission for itself. When the domain master read this register. it gets permission.." bitfld.long 0x0 7. "DOM_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" newline bitfld.long 0x0 0. "DOM_PRI_EN,Domain privileged permission control enable" "0,1" repeat.end repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x34 0x68 0x9C 0xD0 0x104 0x138 0x16C 0x1A0 0x1D4 0x208 0x23C 0x270 0x2A4 0x2D8 0x30C ) group.long ($2+0x2430)++0x3 line.long 0x0 "DOM_ASSIGN_$1,Use to assign domain for accessing DOM_SEC_PER and DOM_PRI_PER register. Only resource manager. group manager and domain owner can access this register. For write. group manager must write its owen domain ID. otherwise write accessing will.." hexmask.long.byte 0x0 0.--3. 1. "DID,accessing DOM_SEC_PER and DOM_PRI_PER register" repeat.end repeat 16. (list 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1A 0x1B 0x1C 0x1D 0x1E 0x1F )(list 0x340 0x374 0x3A8 0x3DC 0x410 0x444 0x478 0x4AC 0x4E0 0x514 0x548 0x57C 0x5B0 0x5E4 0x618 0x64C ) group.long ($2+0x2430)++0x3 line.long 0x0 "DOM_ASSIGN_$1,Use to assign domain for accessing DOM_SEC_PER and DOM_PRI_PER register. Only resource manager. group manager and domain owner can access this register. For write. group manager must write its owen domain ID. otherwise write accessing will.." hexmask.long.byte 0x0 0.--3. 1. "DID,accessing DOM_SEC_PER and DOM_PRI_PER register" repeat.end repeat 16. (list 0x20 0x21 0x22 0x23 0x24 0x25 0x26 0x27 0x28 0x29 0x2A 0x2B 0x2C 0x2D 0x2E 0x2F )(list 0x680 0x6B4 0x6E8 0x71C 0x750 0x784 0x7B8 0x7EC 0x820 0x854 0x888 0x8BC 0x8F0 0x924 0x958 0x98C ) group.long ($2+0x2430)++0x3 line.long 0x0 "DOM_ASSIGN_$1,Use to assign domain for accessing DOM_SEC_PER and DOM_PRI_PER register. Only resource manager. group manager and domain owner can access this register. For write. group manager must write its owen domain ID. otherwise write accessing will.." hexmask.long.byte 0x0 0.--3. 1. "DID,accessing DOM_SEC_PER and DOM_PRI_PER register" repeat.end repeat 16. (list 0x30 0x31 0x32 0x33 0x34 0x35 0x36 0x37 0x38 0x39 0x3A 0x3B 0x3C 0x3D 0x3E 0x3F )(list 0x9C0 0x9F4 0xA28 0xA5C 0xA90 0xAC4 0xAF8 0xB2C 0xB60 0xB94 0xBC8 0xBFC 0xC30 0xC64 0xC98 0xCCC ) group.long ($2+0x2430)++0x3 line.long 0x0 "DOM_ASSIGN_$1,Use to assign domain for accessing DOM_SEC_PER and DOM_PRI_PER register. Only resource manager. group manager and domain owner can access this register. For write. group manager must write its owen domain ID. otherwise write accessing will.." hexmask.long.byte 0x0 0.--3. 1. "DID,accessing DOM_SEC_PER and DOM_PRI_PER register" repeat.end repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x38 0x70 0xA8 0xE0 0x118 0x150 0x188 0x1C0 0x1F8 0x230 0x268 0x2A0 0x2D8 0x310 0x348 ) group.long ($2+0x3100)++0x3 line.long 0x0 "RGN_DOM_$1,Assign domain for peripheral. It can be only configured by resource and group manager" bitfld.long 0x0 31. "LOCK,When this bit is set lock write for all the bits in the register." "0,1" bitfld.long 0x0 4. "SET,Set together with DID would change permission of this resource to following setting: 1) Domain access control enabled. 2) Read/Write allowed for the domain owner. 3) Read/Write not allowed for all the other domains. If this bit is not set only DID.." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Assign domain for peripheral" repeat.end repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x38 0x70 0xA8 0xE0 0x118 0x150 0x188 0x1C0 0x1F8 0x230 0x268 0x2A0 0x2D8 0x310 0x348 ) group.long ($2+0x3104)++0x3 line.long 0x0 "RGN_DOM_PER0_$1,Domain Permission Control. It can be only configured by resource manager and domain owner." bitfld.long 0x0 31. "DOM7_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 29.--30. "DOM7_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 28. "DOM7_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 27. "DOM6_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 25.--26. "DOM6_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" newline bitfld.long 0x0 24. "DOM6_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 23. "DOM5_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 21.--22. "DOM5_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 20. "DOM5_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 19. "DOM4_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" newline bitfld.long 0x0 17.--18. "DOM4_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM4_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 15. "DOM3_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 13.--14. "DOM3_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 12. "DOM3_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" newline bitfld.long 0x0 11. "DOM2_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 9.--10. "DOM2_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM2_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 7. "DOM1_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 5.--6. "DOM1_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" newline bitfld.long 0x0 4. "DOM1_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 3. "DOM0_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 1.--2. "DOM0_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM0_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" repeat.end repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x38 0x70 0xA8 0xE0 0x118 0x150 0x188 0x1C0 0x1F8 0x230 0x268 0x2A0 0x2D8 0x310 0x348 ) group.long ($2+0x3108)++0x3 line.long 0x0 "RGN_DOM_PER1_$1,Domain Permission Control. It can be only configured by resource manager and domain owner." bitfld.long 0x0 31. "DOM15_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 29.--30. "DOM15_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 28. "DOM15_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 27. "DOM14_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 25.--26. "DOM14_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" newline bitfld.long 0x0 24. "DOM14_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 23. "DOM13_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 21.--22. "DOM13_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 20. "DOM13_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 19. "DOM12_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" newline bitfld.long 0x0 17.--18. "DOM12_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM12_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 15. "DOM11_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 13.--14. "DOM11_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 12. "DOM11_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" newline bitfld.long 0x0 11. "DOM10_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 9.--10. "DOM10_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM10_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 7. "DOM9_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 5.--6. "DOM9_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" newline bitfld.long 0x0 4. "DOM9_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 3. "DOM8_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 1.--2. "DOM8_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM8_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" repeat.end repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x38 0x70 0xA8 0xE0 0x118 0x150 0x188 0x1C0 0x1F8 0x230 0x268 0x2A0 0x2D8 0x310 0x348 ) group.long ($2+0x310C)++0x3 line.long 0x0 "RGN_SEC_PER0_$1,This register is only used for resource manager to control secure access permission." bitfld.long 0x0 31. "DOM3_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM3_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM3_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM3_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM2_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM2_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM2_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM2_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM1_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM1_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM1_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM1_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM0_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM0_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM0_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM0_SEC_EN,Domain secure permission control enable" "0,1" repeat.end repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x38 0x70 0xA8 0xE0 0x118 0x150 0x188 0x1C0 0x1F8 0x230 0x268 0x2A0 0x2D8 0x310 0x348 ) group.long ($2+0x3110)++0x3 line.long 0x0 "RGN_SEC_PER1_$1,This register is only used for resource manager to control secure access permission." bitfld.long 0x0 31. "DOM7_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM7_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM7_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM7_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM6_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM6_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM6_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM6_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM5_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM5_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM5_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM5_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM4_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM4_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM4_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM4_SEC_EN,Domain secure permission control enable" "0,1" repeat.end repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x38 0x70 0xA8 0xE0 0x118 0x150 0x188 0x1C0 0x1F8 0x230 0x268 0x2A0 0x2D8 0x310 0x348 ) group.long ($2+0x3114)++0x3 line.long 0x0 "RGN_SEC_PER2_$1,This register is only used for resource manager to control secure access permission." bitfld.long 0x0 31. "DOM11_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM11_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM11_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM11_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM10_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM10_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM10_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM10_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM9_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM9_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM9_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM9_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM8_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM8_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM8_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM8_SEC_EN,Domain secure permission control enable" "0,1" repeat.end repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x38 0x70 0xA8 0xE0 0x118 0x150 0x188 0x1C0 0x1F8 0x230 0x268 0x2A0 0x2D8 0x310 0x348 ) group.long ($2+0x3118)++0x3 line.long 0x0 "RGN_SEC_PER3_$1,This register is only used for resource manager to control secure access permission." bitfld.long 0x0 31. "DOM15_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM15_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM15_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM15_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM14_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM14_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM14_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM14_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM13_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM13_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM13_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM13_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM12_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM12_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM12_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM12_SEC_EN,Domain secure permission control enable" "0,1" repeat.end repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x38 0x70 0xA8 0xE0 0x118 0x150 0x188 0x1C0 0x1F8 0x230 0x268 0x2A0 0x2D8 0x310 0x348 ) group.long ($2+0x311C)++0x3 line.long 0x0 "RGN_PRI_PER0_$1,This register is only used for resource manager to control privileged access permission." bitfld.long 0x0 31. "DOM3_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM3_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM3_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM3_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM2_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM2_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM2_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM2_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM1_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM1_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM1_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM1_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM0_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM0_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM0_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM0_PRI_EN,Domain privileged permission control enable" "0,1" repeat.end repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x38 0x70 0xA8 0xE0 0x118 0x150 0x188 0x1C0 0x1F8 0x230 0x268 0x2A0 0x2D8 0x310 0x348 ) group.long ($2+0x3120)++0x3 line.long 0x0 "RGN_PRI_PER1_$1,This register is only used for resource manager to control privileged access permission." bitfld.long 0x0 31. "DOM7_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM7_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM7_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM7_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM6_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM6_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM6_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM6_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM5_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM5_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM5_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM5_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM4_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM4_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM4_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM4_PRI_EN,Domain privileged permission control enable" "0,1" repeat.end repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x38 0x70 0xA8 0xE0 0x118 0x150 0x188 0x1C0 0x1F8 0x230 0x268 0x2A0 0x2D8 0x310 0x348 ) group.long ($2+0x3124)++0x3 line.long 0x0 "RGN_PRI_PER2_$1,This register is only used for resource manager to control privileged access permission." bitfld.long 0x0 31. "DOM11_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM11_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM11_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM11_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM10_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM10_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM10_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM10_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM9_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM9_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM9_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM9_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM8_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM8_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM8_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM8_PRI_EN,Domain privileged permission control enable" "0,1" repeat.end repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x38 0x70 0xA8 0xE0 0x118 0x150 0x188 0x1C0 0x1F8 0x230 0x268 0x2A0 0x2D8 0x310 0x348 ) group.long ($2+0x3128)++0x3 line.long 0x0 "RGN_PRI_PER3_$1,This register is only used for resource manager to control privileged access permission." bitfld.long 0x0 31. "DOM15_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM15_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM15_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM15_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM14_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM14_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM14_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM14_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM13_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM13_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM13_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM13_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM12_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM12_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM12_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM12_PRI_EN,Domain privileged permission control enable" "0,1" repeat.end repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x38 0x70 0xA8 0xE0 0x118 0x150 0x188 0x1C0 0x1F8 0x230 0x268 0x2A0 0x2D8 0x310 0x348 ) group.long ($2+0x312C)++0x3 line.long 0x0 "RGN_DOM_SEC_PER_$1,This register is only used for domain master to control secure access permission. When the domain master write this register. it only changes the secure permission for itself. When the domain master read this register. it gets.." bitfld.long 0x0 7. "DOM_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" newline bitfld.long 0x0 0. "DOM_SEC_EN,Domain secure permission control enable" "0,1" repeat.end repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x38 0x70 0xA8 0xE0 0x118 0x150 0x188 0x1C0 0x1F8 0x230 0x268 0x2A0 0x2D8 0x310 0x348 ) group.long ($2+0x3130)++0x3 line.long 0x0 "RGN_DOM_PRI_PER_$1,This register is only used for domain master to control secure access permission. When the domain master write this register. it only changes the secure permission for itself. When the domain master read this register. it gets.." bitfld.long 0x0 7. "DOM_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" newline bitfld.long 0x0 0. "DOM_PRI_EN,Domain privileged permission control enable" "0,1" repeat.end repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x38 0x70 0xA8 0xE0 0x118 0x150 0x188 0x1C0 0x1F8 0x230 0x268 0x2A0 0x2D8 0x310 0x348 ) group.long ($2+0x3134)++0x3 line.long 0x0 "RGN_DOM_ASSIGN_$1,Use to assign domain for accessing DOM_SEC_PER and DOM_PRI_PER register. Only resource manager. group manager and domain owner can access this register. For write. group manager must write its owen domain ID. otherwise write accessing.." hexmask.long.byte 0x0 0.--3. 1. "DID,accessing DOM_SEC_PER and DOM_PRI_PER register" repeat.end tree.end elif (CORENAME()=="CORTEXA55") tree "RPC_XPU_CLKGEN" base ad:0x36800000 repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x4 0x8 0xC 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C ) group.long ($2)++0x3 line.long 0x0 "REGG0_DOM_$1,Assign domain for CKGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1A 0x1B 0x1C 0x1D 0x1E 0x1F )(list 0x40 0x44 0x48 0x4C 0x50 0x54 0x58 0x5C 0x60 0x64 0x68 0x6C 0x70 0x74 0x78 0x7C ) group.long ($2)++0x3 line.long 0x0 "REGG0_DOM_$1,Assign domain for CKGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x20 0x21 0x22 0x23 0x24 0x25 0x26 0x27 0x28 0x29 0x2A 0x2B 0x2C 0x2D 0x2E 0x2F )(list 0x80 0x84 0x88 0x8C 0x90 0x94 0x98 0x9C 0xA0 0xA4 0xA8 0xAC 0xB0 0xB4 0xB8 0xBC ) group.long ($2)++0x3 line.long 0x0 "REGG0_DOM_$1,Assign domain for CKGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x30 0x31 0x32 0x33 0x34 0x35 0x36 0x37 0x38 0x39 0x3A 0x3B 0x3C 0x3D 0x3E 0x3F )(list 0xC0 0xC4 0xC8 0xCC 0xD0 0xD4 0xD8 0xDC 0xE0 0xE4 0xE8 0xEC 0xF0 0xF4 0xF8 0xFC ) group.long ($2)++0x3 line.long 0x0 "REGG0_DOM_$1,Assign domain for CKGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x40 0x41 0x42 0x43 0x44 0x45 0x46 0x47 0x48 0x49 0x4A 0x4B 0x4C 0x4D 0x4E 0x4F )(list 0x100 0x104 0x108 0x10C 0x110 0x114 0x118 0x11C 0x120 0x124 0x128 0x12C 0x130 0x134 0x138 0x13C ) group.long ($2)++0x3 line.long 0x0 "REGG0_DOM_$1,Assign domain for CKGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x50 0x51 0x52 0x53 0x54 0x55 0x56 0x57 0x58 0x59 0x5A 0x5B 0x5C 0x5D 0x5E 0x5F )(list 0x140 0x144 0x148 0x14C 0x150 0x154 0x158 0x15C 0x160 0x164 0x168 0x16C 0x170 0x174 0x178 0x17C ) group.long ($2)++0x3 line.long 0x0 "REGG0_DOM_$1,Assign domain for CKGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x60 0x61 0x62 0x63 0x64 0x65 0x66 0x67 0x68 0x69 0x6A 0x6B 0x6C 0x6D 0x6E 0x6F )(list 0x180 0x184 0x188 0x18C 0x190 0x194 0x198 0x19C 0x1A0 0x1A4 0x1A8 0x1AC 0x1B0 0x1B4 0x1B8 0x1BC ) group.long ($2)++0x3 line.long 0x0 "REGG0_DOM_$1,Assign domain for CKGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x70 0x71 0x72 0x73 0x74 0x75 0x76 0x77 0x78 0x79 0x7A 0x7B 0x7C 0x7D 0x7E 0x7F )(list 0x1C0 0x1C4 0x1C8 0x1CC 0x1D0 0x1D4 0x1D8 0x1DC 0x1E0 0x1E4 0x1E8 0x1EC 0x1F0 0x1F4 0x1F8 0x1FC ) group.long ($2)++0x3 line.long 0x0 "REGG0_DOM_$1,Assign domain for CKGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x80 0x81 0x82 0x83 0x84 0x85 0x86 0x87 0x88 0x89 0x8A 0x8B 0x8C 0x8D 0x8E 0x8F )(list 0x200 0x204 0x208 0x20C 0x210 0x214 0x218 0x21C 0x220 0x224 0x228 0x22C 0x230 0x234 0x238 0x23C ) group.long ($2)++0x3 line.long 0x0 "REGG0_DOM_$1,Assign domain for CKGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x90 0x91 0x92 0x93 0x94 0x95 0x96 0x97 0x98 0x99 0x9A 0x9B 0x9C 0x9D 0x9E 0x9F )(list 0x240 0x244 0x248 0x24C 0x250 0x254 0x258 0x25C 0x260 0x264 0x268 0x26C 0x270 0x274 0x278 0x27C ) group.long ($2)++0x3 line.long 0x0 "REGG0_DOM_$1,Assign domain for CKGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xA0 0xA1 0xA2 0xA3 0xA4 0xA5 0xA6 0xA7 0xA8 0xA9 0xAA 0xAB 0xAC 0xAD 0xAE 0xAF )(list 0x280 0x284 0x288 0x28C 0x290 0x294 0x298 0x29C 0x2A0 0x2A4 0x2A8 0x2AC 0x2B0 0x2B4 0x2B8 0x2BC ) group.long ($2)++0x3 line.long 0x0 "REGG0_DOM_$1,Assign domain for CKGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xB0 0xB1 0xB2 0xB3 0xB4 0xB5 0xB6 0xB7 0xB8 0xB9 0xBA 0xBB 0xBC 0xBD 0xBE 0xBF )(list 0x2C0 0x2C4 0x2C8 0x2CC 0x2D0 0x2D4 0x2D8 0x2DC 0x2E0 0x2E4 0x2E8 0x2EC 0x2F0 0x2F4 0x2F8 0x2FC ) group.long ($2)++0x3 line.long 0x0 "REGG0_DOM_$1,Assign domain for CKGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xC0 0xC1 0xC2 0xC3 0xC4 0xC5 0xC6 0xC7 0xC8 0xC9 0xCA 0xCB 0xCC 0xCD 0xCE 0xCF )(list 0x300 0x304 0x308 0x30C 0x310 0x314 0x318 0x31C 0x320 0x324 0x328 0x32C 0x330 0x334 0x338 0x33C ) group.long ($2)++0x3 line.long 0x0 "REGG0_DOM_$1,Assign domain for CKGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xD0 0xD1 0xD2 0xD3 0xD4 0xD5 0xD6 0xD7 0xD8 0xD9 0xDA 0xDB 0xDC 0xDD 0xDE 0xDF )(list 0x340 0x344 0x348 0x34C 0x350 0x354 0x358 0x35C 0x360 0x364 0x368 0x36C 0x370 0x374 0x378 0x37C ) group.long ($2)++0x3 line.long 0x0 "REGG0_DOM_$1,Assign domain for CKGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xE0 0xE1 0xE2 0xE3 0xE4 0xE5 0xE6 0xE7 0xE8 0xE9 0xEA 0xEB 0xEC 0xED 0xEE 0xEF )(list 0x380 0x384 0x388 0x38C 0x390 0x394 0x398 0x39C 0x3A0 0x3A4 0x3A8 0x3AC 0x3B0 0x3B4 0x3B8 0x3BC ) group.long ($2)++0x3 line.long 0x0 "REGG0_DOM_$1,Assign domain for CKGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xF0 0xF1 0xF2 0xF3 0xF4 0xF5 0xF6 0xF7 0xF8 0xF9 0xFA 0xFB 0xFC 0xFD 0xFE 0xFF )(list 0x3C0 0x3C4 0x3C8 0x3CC 0x3D0 0x3D4 0x3D8 0x3DC 0x3E0 0x3E4 0x3E8 0x3EC 0x3F0 0x3F4 0x3F8 0x3FC ) group.long ($2)++0x3 line.long 0x0 "REGG0_DOM_$1,Assign domain for CKGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x4 0x8 0xC 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C ) group.long ($2+0x400)++0x3 line.long 0x0 "REGG1_DOM_$1,Assign domain for CKGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1A 0x1B 0x1C 0x1D 0x1E 0x1F )(list 0x40 0x44 0x48 0x4C 0x50 0x54 0x58 0x5C 0x60 0x64 0x68 0x6C 0x70 0x74 0x78 0x7C ) group.long ($2+0x400)++0x3 line.long 0x0 "REGG1_DOM_$1,Assign domain for CKGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x20 0x21 0x22 0x23 0x24 0x25 0x26 0x27 0x28 0x29 0x2A 0x2B 0x2C 0x2D 0x2E 0x2F )(list 0x80 0x84 0x88 0x8C 0x90 0x94 0x98 0x9C 0xA0 0xA4 0xA8 0xAC 0xB0 0xB4 0xB8 0xBC ) group.long ($2+0x400)++0x3 line.long 0x0 "REGG1_DOM_$1,Assign domain for CKGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x30 0x31 0x32 0x33 0x34 0x35 0x36 0x37 0x38 0x39 0x3A 0x3B 0x3C 0x3D 0x3E 0x3F )(list 0xC0 0xC4 0xC8 0xCC 0xD0 0xD4 0xD8 0xDC 0xE0 0xE4 0xE8 0xEC 0xF0 0xF4 0xF8 0xFC ) group.long ($2+0x400)++0x3 line.long 0x0 "REGG1_DOM_$1,Assign domain for CKGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x40 0x41 0x42 0x43 0x44 0x45 0x46 0x47 0x48 0x49 0x4A 0x4B 0x4C 0x4D 0x4E 0x4F )(list 0x100 0x104 0x108 0x10C 0x110 0x114 0x118 0x11C 0x120 0x124 0x128 0x12C 0x130 0x134 0x138 0x13C ) group.long ($2+0x400)++0x3 line.long 0x0 "REGG1_DOM_$1,Assign domain for CKGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x50 0x51 0x52 0x53 0x54 0x55 0x56 0x57 0x58 0x59 0x5A 0x5B 0x5C 0x5D 0x5E 0x5F )(list 0x140 0x144 0x148 0x14C 0x150 0x154 0x158 0x15C 0x160 0x164 0x168 0x16C 0x170 0x174 0x178 0x17C ) group.long ($2+0x400)++0x3 line.long 0x0 "REGG1_DOM_$1,Assign domain for CKGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x60 0x61 0x62 0x63 0x64 0x65 0x66 0x67 0x68 0x69 0x6A 0x6B 0x6C 0x6D 0x6E 0x6F )(list 0x180 0x184 0x188 0x18C 0x190 0x194 0x198 0x19C 0x1A0 0x1A4 0x1A8 0x1AC 0x1B0 0x1B4 0x1B8 0x1BC ) group.long ($2+0x400)++0x3 line.long 0x0 "REGG1_DOM_$1,Assign domain for CKGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x70 0x71 0x72 0x73 0x74 0x75 0x76 0x77 0x78 0x79 0x7A 0x7B 0x7C 0x7D 0x7E 0x7F )(list 0x1C0 0x1C4 0x1C8 0x1CC 0x1D0 0x1D4 0x1D8 0x1DC 0x1E0 0x1E4 0x1E8 0x1EC 0x1F0 0x1F4 0x1F8 0x1FC ) group.long ($2+0x400)++0x3 line.long 0x0 "REGG1_DOM_$1,Assign domain for CKGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x80 0x81 0x82 0x83 0x84 0x85 0x86 0x87 0x88 0x89 0x8A 0x8B 0x8C 0x8D 0x8E 0x8F )(list 0x200 0x204 0x208 0x20C 0x210 0x214 0x218 0x21C 0x220 0x224 0x228 0x22C 0x230 0x234 0x238 0x23C ) group.long ($2+0x400)++0x3 line.long 0x0 "REGG1_DOM_$1,Assign domain for CKGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x90 0x91 0x92 0x93 0x94 0x95 0x96 0x97 0x98 0x99 0x9A 0x9B 0x9C 0x9D 0x9E 0x9F )(list 0x240 0x244 0x248 0x24C 0x250 0x254 0x258 0x25C 0x260 0x264 0x268 0x26C 0x270 0x274 0x278 0x27C ) group.long ($2+0x400)++0x3 line.long 0x0 "REGG1_DOM_$1,Assign domain for CKGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xA0 0xA1 0xA2 0xA3 0xA4 0xA5 0xA6 0xA7 0xA8 0xA9 0xAA 0xAB 0xAC 0xAD 0xAE 0xAF )(list 0x280 0x284 0x288 0x28C 0x290 0x294 0x298 0x29C 0x2A0 0x2A4 0x2A8 0x2AC 0x2B0 0x2B4 0x2B8 0x2BC ) group.long ($2+0x400)++0x3 line.long 0x0 "REGG1_DOM_$1,Assign domain for CKGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xB0 0xB1 0xB2 0xB3 0xB4 0xB5 0xB6 0xB7 0xB8 0xB9 0xBA 0xBB 0xBC 0xBD 0xBE 0xBF )(list 0x2C0 0x2C4 0x2C8 0x2CC 0x2D0 0x2D4 0x2D8 0x2DC 0x2E0 0x2E4 0x2E8 0x2EC 0x2F0 0x2F4 0x2F8 0x2FC ) group.long ($2+0x400)++0x3 line.long 0x0 "REGG1_DOM_$1,Assign domain for CKGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xC0 0xC1 0xC2 0xC3 0xC4 0xC5 0xC6 0xC7 0xC8 0xC9 0xCA 0xCB 0xCC 0xCD 0xCE 0xCF )(list 0x300 0x304 0x308 0x30C 0x310 0x314 0x318 0x31C 0x320 0x324 0x328 0x32C 0x330 0x334 0x338 0x33C ) group.long ($2+0x400)++0x3 line.long 0x0 "REGG1_DOM_$1,Assign domain for CKGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xD0 0xD1 0xD2 0xD3 0xD4 0xD5 0xD6 0xD7 0xD8 0xD9 0xDA 0xDB 0xDC 0xDD 0xDE 0xDF )(list 0x340 0x344 0x348 0x34C 0x350 0x354 0x358 0x35C 0x360 0x364 0x368 0x36C 0x370 0x374 0x378 0x37C ) group.long ($2+0x400)++0x3 line.long 0x0 "REGG1_DOM_$1,Assign domain for CKGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xE0 0xE1 0xE2 0xE3 0xE4 0xE5 0xE6 0xE7 0xE8 0xE9 0xEA 0xEB 0xEC 0xED 0xEE 0xEF )(list 0x380 0x384 0x388 0x38C 0x390 0x394 0x398 0x39C 0x3A0 0x3A4 0x3A8 0x3AC 0x3B0 0x3B4 0x3B8 0x3BC ) group.long ($2+0x400)++0x3 line.long 0x0 "REGG1_DOM_$1,Assign domain for CKGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xF0 0xF1 0xF2 0xF3 0xF4 0xF5 0xF6 0xF7 0xF8 0xF9 0xFA 0xFB 0xFC 0xFD 0xFE 0xFF )(list 0x3C0 0x3C4 0x3C8 0x3CC 0x3D0 0x3D4 0x3D8 0x3DC 0x3E0 0x3E4 0x3E8 0x3EC 0x3F0 0x3F4 0x3F8 0x3FC ) group.long ($2+0x400)++0x3 line.long 0x0 "REGG1_DOM_$1,Assign domain for CKGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x4 0x8 0xC 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C ) group.long ($2+0x800)++0x3 line.long 0x0 "REGG2_DOM_$1,Assign domain for SCR registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1A 0x1B 0x1C 0x1D 0x1E 0x1F )(list 0x40 0x44 0x48 0x4C 0x50 0x54 0x58 0x5C 0x60 0x64 0x68 0x6C 0x70 0x74 0x78 0x7C ) group.long ($2+0x800)++0x3 line.long 0x0 "REGG2_DOM_$1,Assign domain for SCR registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x20 0x21 0x22 0x23 0x24 0x25 0x26 0x27 0x28 0x29 0x2A 0x2B 0x2C 0x2D 0x2E 0x2F )(list 0x80 0x84 0x88 0x8C 0x90 0x94 0x98 0x9C 0xA0 0xA4 0xA8 0xAC 0xB0 0xB4 0xB8 0xBC ) group.long ($2+0x800)++0x3 line.long 0x0 "REGG2_DOM_$1,Assign domain for SCR registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x30 0x31 0x32 0x33 0x34 0x35 0x36 0x37 0x38 0x39 0x3A 0x3B 0x3C 0x3D 0x3E 0x3F )(list 0xC0 0xC4 0xC8 0xCC 0xD0 0xD4 0xD8 0xDC 0xE0 0xE4 0xE8 0xEC 0xF0 0xF4 0xF8 0xFC ) group.long ($2+0x800)++0x3 line.long 0x0 "REGG2_DOM_$1,Assign domain for SCR registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x40 0x41 0x42 0x43 0x44 0x45 0x46 0x47 0x48 0x49 0x4A 0x4B 0x4C 0x4D 0x4E 0x4F )(list 0x100 0x104 0x108 0x10C 0x110 0x114 0x118 0x11C 0x120 0x124 0x128 0x12C 0x130 0x134 0x138 0x13C ) group.long ($2+0x800)++0x3 line.long 0x0 "REGG2_DOM_$1,Assign domain for SCR registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x50 0x51 0x52 0x53 0x54 0x55 0x56 0x57 0x58 0x59 0x5A 0x5B 0x5C 0x5D 0x5E 0x5F )(list 0x140 0x144 0x148 0x14C 0x150 0x154 0x158 0x15C 0x160 0x164 0x168 0x16C 0x170 0x174 0x178 0x17C ) group.long ($2+0x800)++0x3 line.long 0x0 "REGG2_DOM_$1,Assign domain for SCR registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x60 0x61 0x62 0x63 0x64 0x65 0x66 0x67 0x68 0x69 0x6A 0x6B 0x6C 0x6D 0x6E 0x6F )(list 0x180 0x184 0x188 0x18C 0x190 0x194 0x198 0x19C 0x1A0 0x1A4 0x1A8 0x1AC 0x1B0 0x1B4 0x1B8 0x1BC ) group.long ($2+0x800)++0x3 line.long 0x0 "REGG2_DOM_$1,Assign domain for SCR registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x70 0x71 0x72 0x73 0x74 0x75 0x76 0x77 0x78 0x79 0x7A 0x7B 0x7C 0x7D 0x7E 0x7F )(list 0x1C0 0x1C4 0x1C8 0x1CC 0x1D0 0x1D4 0x1D8 0x1DC 0x1E0 0x1E4 0x1E8 0x1EC 0x1F0 0x1F4 0x1F8 0x1FC ) group.long ($2+0x800)++0x3 line.long 0x0 "REGG2_DOM_$1,Assign domain for SCR registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x80 0x81 0x82 0x83 0x84 0x85 0x86 0x87 0x88 0x89 0x8A 0x8B 0x8C 0x8D 0x8E 0x8F )(list 0x200 0x204 0x208 0x20C 0x210 0x214 0x218 0x21C 0x220 0x224 0x228 0x22C 0x230 0x234 0x238 0x23C ) group.long ($2+0x800)++0x3 line.long 0x0 "REGG2_DOM_$1,Assign domain for SCR registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x90 0x91 0x92 0x93 0x94 0x95 0x96 0x97 0x98 0x99 0x9A 0x9B 0x9C 0x9D 0x9E 0x9F )(list 0x240 0x244 0x248 0x24C 0x250 0x254 0x258 0x25C 0x260 0x264 0x268 0x26C 0x270 0x274 0x278 0x27C ) group.long ($2+0x800)++0x3 line.long 0x0 "REGG2_DOM_$1,Assign domain for SCR registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xA0 0xA1 0xA2 0xA3 0xA4 0xA5 0xA6 0xA7 0xA8 0xA9 0xAA 0xAB 0xAC 0xAD 0xAE 0xAF )(list 0x280 0x284 0x288 0x28C 0x290 0x294 0x298 0x29C 0x2A0 0x2A4 0x2A8 0x2AC 0x2B0 0x2B4 0x2B8 0x2BC ) group.long ($2+0x800)++0x3 line.long 0x0 "REGG2_DOM_$1,Assign domain for SCR registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xB0 0xB1 0xB2 0xB3 0xB4 0xB5 0xB6 0xB7 0xB8 0xB9 0xBA 0xBB 0xBC 0xBD 0xBE 0xBF )(list 0x2C0 0x2C4 0x2C8 0x2CC 0x2D0 0x2D4 0x2D8 0x2DC 0x2E0 0x2E4 0x2E8 0x2EC 0x2F0 0x2F4 0x2F8 0x2FC ) group.long ($2+0x800)++0x3 line.long 0x0 "REGG2_DOM_$1,Assign domain for SCR registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xC0 0xC1 0xC2 0xC3 0xC4 0xC5 0xC6 0xC7 0xC8 0xC9 0xCA 0xCB 0xCC 0xCD 0xCE 0xCF )(list 0x300 0x304 0x308 0x30C 0x310 0x314 0x318 0x31C 0x320 0x324 0x328 0x32C 0x330 0x334 0x338 0x33C ) group.long ($2+0x800)++0x3 line.long 0x0 "REGG2_DOM_$1,Assign domain for SCR registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xD0 0xD1 0xD2 0xD3 0xD4 0xD5 0xD6 0xD7 0xD8 0xD9 0xDA 0xDB 0xDC 0xDD 0xDE 0xDF )(list 0x340 0x344 0x348 0x34C 0x350 0x354 0x358 0x35C 0x360 0x364 0x368 0x36C 0x370 0x374 0x378 0x37C ) group.long ($2+0x800)++0x3 line.long 0x0 "REGG2_DOM_$1,Assign domain for SCR registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xE0 0xE1 0xE2 0xE3 0xE4 0xE5 0xE6 0xE7 0xE8 0xE9 0xEA 0xEB 0xEC 0xED 0xEE 0xEF )(list 0x380 0x384 0x388 0x38C 0x390 0x394 0x398 0x39C 0x3A0 0x3A4 0x3A8 0x3AC 0x3B0 0x3B4 0x3B8 0x3BC ) group.long ($2+0x800)++0x3 line.long 0x0 "REGG2_DOM_$1,Assign domain for SCR registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xF0 0xF1 0xF2 0xF3 0xF4 0xF5 0xF6 0xF7 0xF8 0xF9 0xFA 0xFB 0xFC 0xFD 0xFE 0xFF )(list 0x3C0 0x3C4 0x3C8 0x3CC 0x3D0 0x3D4 0x3D8 0x3DC 0x3E0 0x3E4 0x3E8 0x3EC 0x3F0 0x3F4 0x3F8 0x3FC ) group.long ($2+0x800)++0x3 line.long 0x0 "REGG2_DOM_$1,Assign domain for SCR registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x4 0x8 0xC 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C ) group.long ($2+0xC00)++0x3 line.long 0x0 "REGG3_DOM_$1,Assign domain for SCR registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1A 0x1B 0x1C 0x1D 0x1E 0x1F )(list 0x40 0x44 0x48 0x4C 0x50 0x54 0x58 0x5C 0x60 0x64 0x68 0x6C 0x70 0x74 0x78 0x7C ) group.long ($2+0xC00)++0x3 line.long 0x0 "REGG3_DOM_$1,Assign domain for SCR registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x20 0x21 0x22 0x23 0x24 0x25 0x26 0x27 0x28 0x29 0x2A 0x2B 0x2C 0x2D 0x2E 0x2F )(list 0x80 0x84 0x88 0x8C 0x90 0x94 0x98 0x9C 0xA0 0xA4 0xA8 0xAC 0xB0 0xB4 0xB8 0xBC ) group.long ($2+0xC00)++0x3 line.long 0x0 "REGG3_DOM_$1,Assign domain for SCR registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x30 0x31 0x32 0x33 0x34 0x35 0x36 0x37 0x38 0x39 0x3A 0x3B 0x3C 0x3D 0x3E 0x3F )(list 0xC0 0xC4 0xC8 0xCC 0xD0 0xD4 0xD8 0xDC 0xE0 0xE4 0xE8 0xEC 0xF0 0xF4 0xF8 0xFC ) group.long ($2+0xC00)++0x3 line.long 0x0 "REGG3_DOM_$1,Assign domain for SCR registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x40 0x41 0x42 0x43 0x44 0x45 0x46 0x47 0x48 0x49 0x4A 0x4B 0x4C 0x4D 0x4E 0x4F )(list 0x100 0x104 0x108 0x10C 0x110 0x114 0x118 0x11C 0x120 0x124 0x128 0x12C 0x130 0x134 0x138 0x13C ) group.long ($2+0xC00)++0x3 line.long 0x0 "REGG3_DOM_$1,Assign domain for SCR registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x50 0x51 0x52 0x53 0x54 0x55 0x56 0x57 0x58 0x59 0x5A 0x5B 0x5C 0x5D 0x5E 0x5F )(list 0x140 0x144 0x148 0x14C 0x150 0x154 0x158 0x15C 0x160 0x164 0x168 0x16C 0x170 0x174 0x178 0x17C ) group.long ($2+0xC00)++0x3 line.long 0x0 "REGG3_DOM_$1,Assign domain for SCR registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x60 0x61 0x62 0x63 0x64 0x65 0x66 0x67 0x68 0x69 0x6A 0x6B 0x6C 0x6D 0x6E 0x6F )(list 0x180 0x184 0x188 0x18C 0x190 0x194 0x198 0x19C 0x1A0 0x1A4 0x1A8 0x1AC 0x1B0 0x1B4 0x1B8 0x1BC ) group.long ($2+0xC00)++0x3 line.long 0x0 "REGG3_DOM_$1,Assign domain for SCR registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x70 0x71 0x72 0x73 0x74 0x75 0x76 0x77 0x78 0x79 0x7A 0x7B 0x7C 0x7D 0x7E 0x7F )(list 0x1C0 0x1C4 0x1C8 0x1CC 0x1D0 0x1D4 0x1D8 0x1DC 0x1E0 0x1E4 0x1E8 0x1EC 0x1F0 0x1F4 0x1F8 0x1FC ) group.long ($2+0xC00)++0x3 line.long 0x0 "REGG3_DOM_$1,Assign domain for SCR registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x80 0x81 0x82 0x83 0x84 0x85 0x86 0x87 0x88 0x89 0x8A 0x8B 0x8C 0x8D 0x8E 0x8F )(list 0x200 0x204 0x208 0x20C 0x210 0x214 0x218 0x21C 0x220 0x224 0x228 0x22C 0x230 0x234 0x238 0x23C ) group.long ($2+0xC00)++0x3 line.long 0x0 "REGG3_DOM_$1,Assign domain for SCR registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x90 0x91 0x92 0x93 0x94 0x95 0x96 0x97 0x98 0x99 0x9A 0x9B 0x9C 0x9D 0x9E 0x9F )(list 0x240 0x244 0x248 0x24C 0x250 0x254 0x258 0x25C 0x260 0x264 0x268 0x26C 0x270 0x274 0x278 0x27C ) group.long ($2+0xC00)++0x3 line.long 0x0 "REGG3_DOM_$1,Assign domain for SCR registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xA0 0xA1 0xA2 0xA3 0xA4 0xA5 0xA6 0xA7 0xA8 0xA9 0xAA 0xAB 0xAC 0xAD 0xAE 0xAF )(list 0x280 0x284 0x288 0x28C 0x290 0x294 0x298 0x29C 0x2A0 0x2A4 0x2A8 0x2AC 0x2B0 0x2B4 0x2B8 0x2BC ) group.long ($2+0xC00)++0x3 line.long 0x0 "REGG3_DOM_$1,Assign domain for SCR registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xB0 0xB1 0xB2 0xB3 0xB4 0xB5 0xB6 0xB7 0xB8 0xB9 0xBA 0xBB 0xBC 0xBD 0xBE 0xBF )(list 0x2C0 0x2C4 0x2C8 0x2CC 0x2D0 0x2D4 0x2D8 0x2DC 0x2E0 0x2E4 0x2E8 0x2EC 0x2F0 0x2F4 0x2F8 0x2FC ) group.long ($2+0xC00)++0x3 line.long 0x0 "REGG3_DOM_$1,Assign domain for SCR registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xC0 0xC1 0xC2 0xC3 0xC4 0xC5 0xC6 0xC7 0xC8 0xC9 0xCA 0xCB 0xCC 0xCD 0xCE 0xCF )(list 0x300 0x304 0x308 0x30C 0x310 0x314 0x318 0x31C 0x320 0x324 0x328 0x32C 0x330 0x334 0x338 0x33C ) group.long ($2+0xC00)++0x3 line.long 0x0 "REGG3_DOM_$1,Assign domain for SCR registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xD0 0xD1 0xD2 0xD3 0xD4 0xD5 0xD6 0xD7 0xD8 0xD9 0xDA 0xDB 0xDC 0xDD 0xDE 0xDF )(list 0x340 0x344 0x348 0x34C 0x350 0x354 0x358 0x35C 0x360 0x364 0x368 0x36C 0x370 0x374 0x378 0x37C ) group.long ($2+0xC00)++0x3 line.long 0x0 "REGG3_DOM_$1,Assign domain for SCR registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xE0 0xE1 0xE2 0xE3 0xE4 0xE5 0xE6 0xE7 0xE8 0xE9 0xEA 0xEB 0xEC 0xED 0xEE 0xEF )(list 0x380 0x384 0x388 0x38C 0x390 0x394 0x398 0x39C 0x3A0 0x3A4 0x3A8 0x3AC 0x3B0 0x3B4 0x3B8 0x3BC ) group.long ($2+0xC00)++0x3 line.long 0x0 "REGG3_DOM_$1,Assign domain for SCR registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xF0 0xF1 0xF2 0xF3 0xF4 0xF5 0xF6 0xF7 0xF8 0xF9 0xFA 0xFB 0xFC 0xFD 0xFE 0xFF )(list 0x3C0 0x3C4 0x3C8 0x3CC 0x3D0 0x3D4 0x3D8 0x3DC 0x3E0 0x3E4 0x3E8 0x3EC 0x3F0 0x3F4 0x3F8 0x3FC ) group.long ($2+0xC00)++0x3 line.long 0x0 "REGG3_DOM_$1,Assign domain for SCR registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x4 0x8 0xC 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C ) group.long ($2+0x1000)++0x3 line.long 0x0 "REGG4_DOM_$1,Assign domain for RSTGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1A 0x1B 0x1C 0x1D 0x1E 0x1F )(list 0x40 0x44 0x48 0x4C 0x50 0x54 0x58 0x5C 0x60 0x64 0x68 0x6C 0x70 0x74 0x78 0x7C ) group.long ($2+0x1000)++0x3 line.long 0x0 "REGG4_DOM_$1,Assign domain for RSTGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x20 0x21 0x22 0x23 0x24 0x25 0x26 0x27 0x28 0x29 0x2A 0x2B 0x2C 0x2D 0x2E 0x2F )(list 0x80 0x84 0x88 0x8C 0x90 0x94 0x98 0x9C 0xA0 0xA4 0xA8 0xAC 0xB0 0xB4 0xB8 0xBC ) group.long ($2+0x1000)++0x3 line.long 0x0 "REGG4_DOM_$1,Assign domain for RSTGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x30 0x31 0x32 0x33 0x34 0x35 0x36 0x37 0x38 0x39 0x3A 0x3B 0x3C 0x3D 0x3E 0x3F )(list 0xC0 0xC4 0xC8 0xCC 0xD0 0xD4 0xD8 0xDC 0xE0 0xE4 0xE8 0xEC 0xF0 0xF4 0xF8 0xFC ) group.long ($2+0x1000)++0x3 line.long 0x0 "REGG4_DOM_$1,Assign domain for RSTGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x40 0x41 0x42 0x43 0x44 0x45 0x46 0x47 0x48 0x49 0x4A 0x4B 0x4C 0x4D 0x4E 0x4F )(list 0x100 0x104 0x108 0x10C 0x110 0x114 0x118 0x11C 0x120 0x124 0x128 0x12C 0x130 0x134 0x138 0x13C ) group.long ($2+0x1000)++0x3 line.long 0x0 "REGG4_DOM_$1,Assign domain for RSTGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x50 0x51 0x52 0x53 0x54 0x55 0x56 0x57 0x58 0x59 0x5A 0x5B 0x5C 0x5D 0x5E 0x5F )(list 0x140 0x144 0x148 0x14C 0x150 0x154 0x158 0x15C 0x160 0x164 0x168 0x16C 0x170 0x174 0x178 0x17C ) group.long ($2+0x1000)++0x3 line.long 0x0 "REGG4_DOM_$1,Assign domain for RSTGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x60 0x61 0x62 0x63 0x64 0x65 0x66 0x67 0x68 0x69 0x6A 0x6B 0x6C 0x6D 0x6E 0x6F )(list 0x180 0x184 0x188 0x18C 0x190 0x194 0x198 0x19C 0x1A0 0x1A4 0x1A8 0x1AC 0x1B0 0x1B4 0x1B8 0x1BC ) group.long ($2+0x1000)++0x3 line.long 0x0 "REGG4_DOM_$1,Assign domain for RSTGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x70 0x71 0x72 0x73 0x74 0x75 0x76 0x77 0x78 0x79 0x7A 0x7B 0x7C 0x7D 0x7E 0x7F )(list 0x1C0 0x1C4 0x1C8 0x1CC 0x1D0 0x1D4 0x1D8 0x1DC 0x1E0 0x1E4 0x1E8 0x1EC 0x1F0 0x1F4 0x1F8 0x1FC ) group.long ($2+0x1000)++0x3 line.long 0x0 "REGG4_DOM_$1,Assign domain for RSTGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x80 0x81 0x82 0x83 0x84 0x85 0x86 0x87 0x88 0x89 0x8A 0x8B 0x8C 0x8D 0x8E 0x8F )(list 0x200 0x204 0x208 0x20C 0x210 0x214 0x218 0x21C 0x220 0x224 0x228 0x22C 0x230 0x234 0x238 0x23C ) group.long ($2+0x1000)++0x3 line.long 0x0 "REGG4_DOM_$1,Assign domain for RSTGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x90 0x91 0x92 0x93 0x94 0x95 0x96 0x97 0x98 0x99 0x9A 0x9B 0x9C 0x9D 0x9E 0x9F )(list 0x240 0x244 0x248 0x24C 0x250 0x254 0x258 0x25C 0x260 0x264 0x268 0x26C 0x270 0x274 0x278 0x27C ) group.long ($2+0x1000)++0x3 line.long 0x0 "REGG4_DOM_$1,Assign domain for RSTGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xA0 0xA1 0xA2 0xA3 0xA4 0xA5 0xA6 0xA7 0xA8 0xA9 0xAA 0xAB 0xAC 0xAD 0xAE 0xAF )(list 0x280 0x284 0x288 0x28C 0x290 0x294 0x298 0x29C 0x2A0 0x2A4 0x2A8 0x2AC 0x2B0 0x2B4 0x2B8 0x2BC ) group.long ($2+0x1000)++0x3 line.long 0x0 "REGG4_DOM_$1,Assign domain for RSTGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xB0 0xB1 0xB2 0xB3 0xB4 0xB5 0xB6 0xB7 0xB8 0xB9 0xBA 0xBB 0xBC 0xBD 0xBE 0xBF )(list 0x2C0 0x2C4 0x2C8 0x2CC 0x2D0 0x2D4 0x2D8 0x2DC 0x2E0 0x2E4 0x2E8 0x2EC 0x2F0 0x2F4 0x2F8 0x2FC ) group.long ($2+0x1000)++0x3 line.long 0x0 "REGG4_DOM_$1,Assign domain for RSTGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xC0 0xC1 0xC2 0xC3 0xC4 0xC5 0xC6 0xC7 0xC8 0xC9 0xCA 0xCB 0xCC 0xCD 0xCE 0xCF )(list 0x300 0x304 0x308 0x30C 0x310 0x314 0x318 0x31C 0x320 0x324 0x328 0x32C 0x330 0x334 0x338 0x33C ) group.long ($2+0x1000)++0x3 line.long 0x0 "REGG4_DOM_$1,Assign domain for RSTGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xD0 0xD1 0xD2 0xD3 0xD4 0xD5 0xD6 0xD7 0xD8 0xD9 0xDA 0xDB 0xDC 0xDD 0xDE 0xDF )(list 0x340 0x344 0x348 0x34C 0x350 0x354 0x358 0x35C 0x360 0x364 0x368 0x36C 0x370 0x374 0x378 0x37C ) group.long ($2+0x1000)++0x3 line.long 0x0 "REGG4_DOM_$1,Assign domain for RSTGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xE0 0xE1 0xE2 0xE3 0xE4 0xE5 0xE6 0xE7 0xE8 0xE9 0xEA 0xEB 0xEC 0xED 0xEE 0xEF )(list 0x380 0x384 0x388 0x38C 0x390 0x394 0x398 0x39C 0x3A0 0x3A4 0x3A8 0x3AC 0x3B0 0x3B4 0x3B8 0x3BC ) group.long ($2+0x1000)++0x3 line.long 0x0 "REGG4_DOM_$1,Assign domain for RSTGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xF0 0xF1 0xF2 0xF3 0xF4 0xF5 0xF6 0xF7 0xF8 0xF9 0xFA 0xFB 0xFC 0xFD 0xFE 0xFF )(list 0x3C0 0x3C4 0x3C8 0x3CC 0x3D0 0x3D4 0x3D8 0x3DC 0x3E0 0x3E4 0x3E8 0x3EC 0x3F0 0x3F4 0x3F8 0x3FC ) group.long ($2+0x1000)++0x3 line.long 0x0 "REGG4_DOM_$1,Assign domain for RSTGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x4 0x8 0xC 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C ) group.long ($2+0x1400)++0x3 line.long 0x0 "REGG5_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1A 0x1B 0x1C 0x1D 0x1E 0x1F )(list 0x40 0x44 0x48 0x4C 0x50 0x54 0x58 0x5C 0x60 0x64 0x68 0x6C 0x70 0x74 0x78 0x7C ) group.long ($2+0x1400)++0x3 line.long 0x0 "REGG5_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x20 0x21 0x22 0x23 0x24 0x25 0x26 0x27 0x28 0x29 0x2A 0x2B 0x2C 0x2D 0x2E 0x2F )(list 0x80 0x84 0x88 0x8C 0x90 0x94 0x98 0x9C 0xA0 0xA4 0xA8 0xAC 0xB0 0xB4 0xB8 0xBC ) group.long ($2+0x1400)++0x3 line.long 0x0 "REGG5_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x30 0x31 0x32 0x33 0x34 0x35 0x36 0x37 0x38 0x39 0x3A 0x3B 0x3C 0x3D 0x3E 0x3F )(list 0xC0 0xC4 0xC8 0xCC 0xD0 0xD4 0xD8 0xDC 0xE0 0xE4 0xE8 0xEC 0xF0 0xF4 0xF8 0xFC ) group.long ($2+0x1400)++0x3 line.long 0x0 "REGG5_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x40 0x41 0x42 0x43 0x44 0x45 0x46 0x47 0x48 0x49 0x4A 0x4B 0x4C 0x4D 0x4E 0x4F )(list 0x100 0x104 0x108 0x10C 0x110 0x114 0x118 0x11C 0x120 0x124 0x128 0x12C 0x130 0x134 0x138 0x13C ) group.long ($2+0x1400)++0x3 line.long 0x0 "REGG5_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x50 0x51 0x52 0x53 0x54 0x55 0x56 0x57 0x58 0x59 0x5A 0x5B 0x5C 0x5D 0x5E 0x5F )(list 0x140 0x144 0x148 0x14C 0x150 0x154 0x158 0x15C 0x160 0x164 0x168 0x16C 0x170 0x174 0x178 0x17C ) group.long ($2+0x1400)++0x3 line.long 0x0 "REGG5_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x60 0x61 0x62 0x63 0x64 0x65 0x66 0x67 0x68 0x69 0x6A 0x6B 0x6C 0x6D 0x6E 0x6F )(list 0x180 0x184 0x188 0x18C 0x190 0x194 0x198 0x19C 0x1A0 0x1A4 0x1A8 0x1AC 0x1B0 0x1B4 0x1B8 0x1BC ) group.long ($2+0x1400)++0x3 line.long 0x0 "REGG5_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x70 0x71 0x72 0x73 0x74 0x75 0x76 0x77 0x78 0x79 0x7A 0x7B 0x7C 0x7D 0x7E 0x7F )(list 0x1C0 0x1C4 0x1C8 0x1CC 0x1D0 0x1D4 0x1D8 0x1DC 0x1E0 0x1E4 0x1E8 0x1EC 0x1F0 0x1F4 0x1F8 0x1FC ) group.long ($2+0x1400)++0x3 line.long 0x0 "REGG5_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x80 0x81 0x82 0x83 0x84 0x85 0x86 0x87 0x88 0x89 0x8A 0x8B 0x8C 0x8D 0x8E 0x8F )(list 0x200 0x204 0x208 0x20C 0x210 0x214 0x218 0x21C 0x220 0x224 0x228 0x22C 0x230 0x234 0x238 0x23C ) group.long ($2+0x1400)++0x3 line.long 0x0 "REGG5_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x90 0x91 0x92 0x93 0x94 0x95 0x96 0x97 0x98 0x99 0x9A 0x9B 0x9C 0x9D 0x9E 0x9F )(list 0x240 0x244 0x248 0x24C 0x250 0x254 0x258 0x25C 0x260 0x264 0x268 0x26C 0x270 0x274 0x278 0x27C ) group.long ($2+0x1400)++0x3 line.long 0x0 "REGG5_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xA0 0xA1 0xA2 0xA3 0xA4 0xA5 0xA6 0xA7 0xA8 0xA9 0xAA 0xAB 0xAC 0xAD 0xAE 0xAF )(list 0x280 0x284 0x288 0x28C 0x290 0x294 0x298 0x29C 0x2A0 0x2A4 0x2A8 0x2AC 0x2B0 0x2B4 0x2B8 0x2BC ) group.long ($2+0x1400)++0x3 line.long 0x0 "REGG5_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xB0 0xB1 0xB2 0xB3 0xB4 0xB5 0xB6 0xB7 0xB8 0xB9 0xBA 0xBB 0xBC 0xBD 0xBE 0xBF )(list 0x2C0 0x2C4 0x2C8 0x2CC 0x2D0 0x2D4 0x2D8 0x2DC 0x2E0 0x2E4 0x2E8 0x2EC 0x2F0 0x2F4 0x2F8 0x2FC ) group.long ($2+0x1400)++0x3 line.long 0x0 "REGG5_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xC0 0xC1 0xC2 0xC3 0xC4 0xC5 0xC6 0xC7 0xC8 0xC9 0xCA 0xCB 0xCC 0xCD 0xCE 0xCF )(list 0x300 0x304 0x308 0x30C 0x310 0x314 0x318 0x31C 0x320 0x324 0x328 0x32C 0x330 0x334 0x338 0x33C ) group.long ($2+0x1400)++0x3 line.long 0x0 "REGG5_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xD0 0xD1 0xD2 0xD3 0xD4 0xD5 0xD6 0xD7 0xD8 0xD9 0xDA 0xDB 0xDC 0xDD 0xDE 0xDF )(list 0x340 0x344 0x348 0x34C 0x350 0x354 0x358 0x35C 0x360 0x364 0x368 0x36C 0x370 0x374 0x378 0x37C ) group.long ($2+0x1400)++0x3 line.long 0x0 "REGG5_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xE0 0xE1 0xE2 0xE3 0xE4 0xE5 0xE6 0xE7 0xE8 0xE9 0xEA 0xEB 0xEC 0xED 0xEE 0xEF )(list 0x380 0x384 0x388 0x38C 0x390 0x394 0x398 0x39C 0x3A0 0x3A4 0x3A8 0x3AC 0x3B0 0x3B4 0x3B8 0x3BC ) group.long ($2+0x1400)++0x3 line.long 0x0 "REGG5_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xF0 0xF1 0xF2 0xF3 0xF4 0xF5 0xF6 0xF7 0xF8 0xF9 0xFA 0xFB 0xFC 0xFD 0xFE 0xFF )(list 0x3C0 0x3C4 0x3C8 0x3CC 0x3D0 0x3D4 0x3D8 0x3DC 0x3E0 0x3E4 0x3E8 0x3EC 0x3F0 0x3F4 0x3F8 0x3FC ) group.long ($2+0x1400)++0x3 line.long 0x0 "REGG5_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x4 0x8 0xC 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C ) group.long ($2+0x1800)++0x3 line.long 0x0 "REGG6_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1A 0x1B 0x1C 0x1D 0x1E 0x1F )(list 0x40 0x44 0x48 0x4C 0x50 0x54 0x58 0x5C 0x60 0x64 0x68 0x6C 0x70 0x74 0x78 0x7C ) group.long ($2+0x1800)++0x3 line.long 0x0 "REGG6_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x20 0x21 0x22 0x23 0x24 0x25 0x26 0x27 0x28 0x29 0x2A 0x2B 0x2C 0x2D 0x2E 0x2F )(list 0x80 0x84 0x88 0x8C 0x90 0x94 0x98 0x9C 0xA0 0xA4 0xA8 0xAC 0xB0 0xB4 0xB8 0xBC ) group.long ($2+0x1800)++0x3 line.long 0x0 "REGG6_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x30 0x31 0x32 0x33 0x34 0x35 0x36 0x37 0x38 0x39 0x3A 0x3B 0x3C 0x3D 0x3E 0x3F )(list 0xC0 0xC4 0xC8 0xCC 0xD0 0xD4 0xD8 0xDC 0xE0 0xE4 0xE8 0xEC 0xF0 0xF4 0xF8 0xFC ) group.long ($2+0x1800)++0x3 line.long 0x0 "REGG6_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x40 0x41 0x42 0x43 0x44 0x45 0x46 0x47 0x48 0x49 0x4A 0x4B 0x4C 0x4D 0x4E 0x4F )(list 0x100 0x104 0x108 0x10C 0x110 0x114 0x118 0x11C 0x120 0x124 0x128 0x12C 0x130 0x134 0x138 0x13C ) group.long ($2+0x1800)++0x3 line.long 0x0 "REGG6_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x50 0x51 0x52 0x53 0x54 0x55 0x56 0x57 0x58 0x59 0x5A 0x5B 0x5C 0x5D 0x5E 0x5F )(list 0x140 0x144 0x148 0x14C 0x150 0x154 0x158 0x15C 0x160 0x164 0x168 0x16C 0x170 0x174 0x178 0x17C ) group.long ($2+0x1800)++0x3 line.long 0x0 "REGG6_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x60 0x61 0x62 0x63 0x64 0x65 0x66 0x67 0x68 0x69 0x6A 0x6B 0x6C 0x6D 0x6E 0x6F )(list 0x180 0x184 0x188 0x18C 0x190 0x194 0x198 0x19C 0x1A0 0x1A4 0x1A8 0x1AC 0x1B0 0x1B4 0x1B8 0x1BC ) group.long ($2+0x1800)++0x3 line.long 0x0 "REGG6_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x70 0x71 0x72 0x73 0x74 0x75 0x76 0x77 0x78 0x79 0x7A 0x7B 0x7C 0x7D 0x7E 0x7F )(list 0x1C0 0x1C4 0x1C8 0x1CC 0x1D0 0x1D4 0x1D8 0x1DC 0x1E0 0x1E4 0x1E8 0x1EC 0x1F0 0x1F4 0x1F8 0x1FC ) group.long ($2+0x1800)++0x3 line.long 0x0 "REGG6_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x80 0x81 0x82 0x83 0x84 0x85 0x86 0x87 0x88 0x89 0x8A 0x8B 0x8C 0x8D 0x8E 0x8F )(list 0x200 0x204 0x208 0x20C 0x210 0x214 0x218 0x21C 0x220 0x224 0x228 0x22C 0x230 0x234 0x238 0x23C ) group.long ($2+0x1800)++0x3 line.long 0x0 "REGG6_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x90 0x91 0x92 0x93 0x94 0x95 0x96 0x97 0x98 0x99 0x9A 0x9B 0x9C 0x9D 0x9E 0x9F )(list 0x240 0x244 0x248 0x24C 0x250 0x254 0x258 0x25C 0x260 0x264 0x268 0x26C 0x270 0x274 0x278 0x27C ) group.long ($2+0x1800)++0x3 line.long 0x0 "REGG6_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xA0 0xA1 0xA2 0xA3 0xA4 0xA5 0xA6 0xA7 0xA8 0xA9 0xAA 0xAB 0xAC 0xAD 0xAE 0xAF )(list 0x280 0x284 0x288 0x28C 0x290 0x294 0x298 0x29C 0x2A0 0x2A4 0x2A8 0x2AC 0x2B0 0x2B4 0x2B8 0x2BC ) group.long ($2+0x1800)++0x3 line.long 0x0 "REGG6_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xB0 0xB1 0xB2 0xB3 0xB4 0xB5 0xB6 0xB7 0xB8 0xB9 0xBA 0xBB 0xBC 0xBD 0xBE 0xBF )(list 0x2C0 0x2C4 0x2C8 0x2CC 0x2D0 0x2D4 0x2D8 0x2DC 0x2E0 0x2E4 0x2E8 0x2EC 0x2F0 0x2F4 0x2F8 0x2FC ) group.long ($2+0x1800)++0x3 line.long 0x0 "REGG6_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xC0 0xC1 0xC2 0xC3 0xC4 0xC5 0xC6 0xC7 0xC8 0xC9 0xCA 0xCB 0xCC 0xCD 0xCE 0xCF )(list 0x300 0x304 0x308 0x30C 0x310 0x314 0x318 0x31C 0x320 0x324 0x328 0x32C 0x330 0x334 0x338 0x33C ) group.long ($2+0x1800)++0x3 line.long 0x0 "REGG6_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xD0 0xD1 0xD2 0xD3 0xD4 0xD5 0xD6 0xD7 0xD8 0xD9 0xDA 0xDB 0xDC 0xDD 0xDE 0xDF )(list 0x340 0x344 0x348 0x34C 0x350 0x354 0x358 0x35C 0x360 0x364 0x368 0x36C 0x370 0x374 0x378 0x37C ) group.long ($2+0x1800)++0x3 line.long 0x0 "REGG6_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xE0 0xE1 0xE2 0xE3 0xE4 0xE5 0xE6 0xE7 0xE8 0xE9 0xEA 0xEB 0xEC 0xED 0xEE 0xEF )(list 0x380 0x384 0x388 0x38C 0x390 0x394 0x398 0x39C 0x3A0 0x3A4 0x3A8 0x3AC 0x3B0 0x3B4 0x3B8 0x3BC ) group.long ($2+0x1800)++0x3 line.long 0x0 "REGG6_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xF0 0xF1 0xF2 0xF3 0xF4 0xF5 0xF6 0xF7 0xF8 0xF9 0xFA 0xFB 0xFC 0xFD 0xFE 0xFF )(list 0x3C0 0x3C4 0x3C8 0x3CC 0x3D0 0x3D4 0x3D8 0x3DC 0x3E0 0x3E4 0x3E8 0x3EC 0x3F0 0x3F4 0x3F8 0x3FC ) group.long ($2+0x1800)++0x3 line.long 0x0 "REGG6_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x4 0x8 0xC 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C ) group.long ($2+0x1C00)++0x3 line.long 0x0 "REGG7_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1A 0x1B 0x1C 0x1D 0x1E 0x1F )(list 0x40 0x44 0x48 0x4C 0x50 0x54 0x58 0x5C 0x60 0x64 0x68 0x6C 0x70 0x74 0x78 0x7C ) group.long ($2+0x1C00)++0x3 line.long 0x0 "REGG7_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x20 0x21 0x22 0x23 0x24 0x25 0x26 0x27 0x28 0x29 0x2A 0x2B 0x2C 0x2D 0x2E 0x2F )(list 0x80 0x84 0x88 0x8C 0x90 0x94 0x98 0x9C 0xA0 0xA4 0xA8 0xAC 0xB0 0xB4 0xB8 0xBC ) group.long ($2+0x1C00)++0x3 line.long 0x0 "REGG7_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x30 0x31 0x32 0x33 0x34 0x35 0x36 0x37 0x38 0x39 0x3A 0x3B 0x3C 0x3D 0x3E 0x3F )(list 0xC0 0xC4 0xC8 0xCC 0xD0 0xD4 0xD8 0xDC 0xE0 0xE4 0xE8 0xEC 0xF0 0xF4 0xF8 0xFC ) group.long ($2+0x1C00)++0x3 line.long 0x0 "REGG7_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x40 0x41 0x42 0x43 0x44 0x45 0x46 0x47 0x48 0x49 0x4A 0x4B 0x4C 0x4D 0x4E 0x4F )(list 0x100 0x104 0x108 0x10C 0x110 0x114 0x118 0x11C 0x120 0x124 0x128 0x12C 0x130 0x134 0x138 0x13C ) group.long ($2+0x1C00)++0x3 line.long 0x0 "REGG7_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x50 0x51 0x52 0x53 0x54 0x55 0x56 0x57 0x58 0x59 0x5A 0x5B 0x5C 0x5D 0x5E 0x5F )(list 0x140 0x144 0x148 0x14C 0x150 0x154 0x158 0x15C 0x160 0x164 0x168 0x16C 0x170 0x174 0x178 0x17C ) group.long ($2+0x1C00)++0x3 line.long 0x0 "REGG7_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x60 0x61 0x62 0x63 0x64 0x65 0x66 0x67 0x68 0x69 0x6A 0x6B 0x6C 0x6D 0x6E 0x6F )(list 0x180 0x184 0x188 0x18C 0x190 0x194 0x198 0x19C 0x1A0 0x1A4 0x1A8 0x1AC 0x1B0 0x1B4 0x1B8 0x1BC ) group.long ($2+0x1C00)++0x3 line.long 0x0 "REGG7_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x70 0x71 0x72 0x73 0x74 0x75 0x76 0x77 0x78 0x79 0x7A 0x7B 0x7C 0x7D 0x7E 0x7F )(list 0x1C0 0x1C4 0x1C8 0x1CC 0x1D0 0x1D4 0x1D8 0x1DC 0x1E0 0x1E4 0x1E8 0x1EC 0x1F0 0x1F4 0x1F8 0x1FC ) group.long ($2+0x1C00)++0x3 line.long 0x0 "REGG7_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x80 0x81 0x82 0x83 0x84 0x85 0x86 0x87 0x88 0x89 0x8A 0x8B 0x8C 0x8D 0x8E 0x8F )(list 0x200 0x204 0x208 0x20C 0x210 0x214 0x218 0x21C 0x220 0x224 0x228 0x22C 0x230 0x234 0x238 0x23C ) group.long ($2+0x1C00)++0x3 line.long 0x0 "REGG7_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x90 0x91 0x92 0x93 0x94 0x95 0x96 0x97 0x98 0x99 0x9A 0x9B 0x9C 0x9D 0x9E 0x9F )(list 0x240 0x244 0x248 0x24C 0x250 0x254 0x258 0x25C 0x260 0x264 0x268 0x26C 0x270 0x274 0x278 0x27C ) group.long ($2+0x1C00)++0x3 line.long 0x0 "REGG7_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xA0 0xA1 0xA2 0xA3 0xA4 0xA5 0xA6 0xA7 0xA8 0xA9 0xAA 0xAB 0xAC 0xAD 0xAE 0xAF )(list 0x280 0x284 0x288 0x28C 0x290 0x294 0x298 0x29C 0x2A0 0x2A4 0x2A8 0x2AC 0x2B0 0x2B4 0x2B8 0x2BC ) group.long ($2+0x1C00)++0x3 line.long 0x0 "REGG7_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xB0 0xB1 0xB2 0xB3 0xB4 0xB5 0xB6 0xB7 0xB8 0xB9 0xBA 0xBB 0xBC 0xBD 0xBE 0xBF )(list 0x2C0 0x2C4 0x2C8 0x2CC 0x2D0 0x2D4 0x2D8 0x2DC 0x2E0 0x2E4 0x2E8 0x2EC 0x2F0 0x2F4 0x2F8 0x2FC ) group.long ($2+0x1C00)++0x3 line.long 0x0 "REGG7_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xC0 0xC1 0xC2 0xC3 0xC4 0xC5 0xC6 0xC7 0xC8 0xC9 0xCA 0xCB 0xCC 0xCD 0xCE 0xCF )(list 0x300 0x304 0x308 0x30C 0x310 0x314 0x318 0x31C 0x320 0x324 0x328 0x32C 0x330 0x334 0x338 0x33C ) group.long ($2+0x1C00)++0x3 line.long 0x0 "REGG7_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xD0 0xD1 0xD2 0xD3 0xD4 0xD5 0xD6 0xD7 0xD8 0xD9 0xDA 0xDB 0xDC 0xDD 0xDE 0xDF )(list 0x340 0x344 0x348 0x34C 0x350 0x354 0x358 0x35C 0x360 0x364 0x368 0x36C 0x370 0x374 0x378 0x37C ) group.long ($2+0x1C00)++0x3 line.long 0x0 "REGG7_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xE0 0xE1 0xE2 0xE3 0xE4 0xE5 0xE6 0xE7 0xE8 0xE9 0xEA 0xEB 0xEC 0xED 0xEE 0xEF )(list 0x380 0x384 0x388 0x38C 0x390 0x394 0x398 0x39C 0x3A0 0x3A4 0x3A8 0x3AC 0x3B0 0x3B4 0x3B8 0x3BC ) group.long ($2+0x1C00)++0x3 line.long 0x0 "REGG7_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xF0 0xF1 0xF2 0xF3 0xF4 0xF5 0xF6 0xF7 0xF8 0xF9 0xFA 0xFB 0xFC 0xFD 0xFE 0xFF )(list 0x3C0 0x3C4 0x3C8 0x3CC 0x3D0 0x3D4 0x3D8 0x3DC 0x3E0 0x3E4 0x3E8 0x3EC 0x3F0 0x3F4 0x3F8 0x3FC ) group.long ($2+0x1C00)++0x3 line.long 0x0 "REGG7_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end group.long 0x2000++0x17 line.long 0x0 "GLB_CTL,This register provides global enable settings for permission control." bitfld.long 0x0 5. "DOM_CFG_LOCK,Lock write for DOM_CFG_MODE bit." "0,1" bitfld.long 0x0 4. "DOM_CFG_MODE,When enabled all the source setting can be configured by master from domain 0 if it is not locked. When disabled only resource manager can configure the permission of the resource." "0,1" bitfld.long 0x0 3. "PERCK_DIS_LOCK,Lock write for PERCK_DIS" "0,1" bitfld.long 0x0 2. "PERCK_DIS,All the permission check disable." "0,1" newline bitfld.long 0x0 1. "DOM_PRO_LOCK,Lock write for DOM_PRO_EN bit." "0,1" bitfld.long 0x0 0. "DOM_PRO_EN,When disabled no domain access permission check" "0,1" line.long 0x4 "RES_MGR,Resource manager register. This regster is used to assign resource manager for global resource access control" bitfld.long 0x4 17. "MID_LOCK,Lock write for MID_EN and MID_LOW and MID_HIG registers." "0,1" bitfld.long 0x4 16. "MID_EN,Master ID check enable" "0,1" bitfld.long 0x4 15. "PRI_PER_LOCK,Lock write for PRI_PER and PRI_PER_EN" "0,1" bitfld.long 0x4 13.--14. "PRI_PER,Resource manager privileged access permission. bit0 for privileged access bit1 for user access" "0,1,2,3" newline bitfld.long 0x4 12. "PRI_PER_EN,Resource manager privileged access permission enable." "0,1" bitfld.long 0x4 11. "SEC_PER_LOCK,Lock for SEC_PER and SEC_PER_LOCK" "0,1" bitfld.long 0x4 9.--10. "SEC_PER,Resource manager secure access permission. bit 0 for secure access bit 1 for non-secure access" "0,1,2,3" bitfld.long 0x4 8. "SEC_PER_EN,Resource manager secure permission enable" "0,1" bitfld.long 0x4 7. "DID_LOCK,Lock write for DID_EN and DID" "0,1" newline hexmask.long.byte 0x4 3.--6. 1. "DID,Resource manager domain ID" bitfld.long 0x4 2. "DID_EN,Resource manager Domain ID enable" "0,1" bitfld.long 0x4 1. "RES_MGR_EN_LOCK,Lock for RES_MGR_EN" "0,1" bitfld.long 0x4 0. "RES_MGR_EN,Resource manager enable. When the bit is disable there is no resource manager." "0,1" line.long 0x8 "RES_MGR_MA0,This register is used to assign master 0~31 as resource manager." hexmask.long 0x8 0.--31. 1. "MID,Assign master 0~31 for resource manager" line.long 0xC "RES_MGR_MA1,This register is used to assign master 32~63 as resource manager." hexmask.long 0xC 0.--31. 1. "MID,Indicate if master 32~63 is resource manager." line.long 0x10 "RES_MGR_MA2,This register is used to assign master 64~95 as resource manager." hexmask.long 0x10 0.--31. 1. "MID,Indicate if master 64~95 is resource manager." line.long 0x14 "RES_MGR_MA3,This register is used to assign master 96~127 as resource manager." hexmask.long 0x14 0.--31. 1. "MID,Indicate if master 96~127 is resource manager." repeat 8. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 )(list 0x0 0x14 0x28 0x3C 0x50 0x64 0x78 0x8C ) group.long ($2+0x2100)++0x3 line.long 0x0 "GRP_MGR_$1,Group Manager Register. This register is used to assign group manager for each domain" bitfld.long 0x0 17. "MID_LOCK,Lock write for MID_EN and MID_LOW and MID_HIG registers." "0,1" bitfld.long 0x0 16. "MID_EN,Master ID check enable" "0,1" bitfld.long 0x0 15. "PRI_PER_LOCK,Lock write for PRI_PER and PRI_PER_EN" "0,1" bitfld.long 0x0 13.--14. "PRI_PER,Group manager privileged access permission. bit0 for privileged access bit1 for user access" "0,1,2,3" newline bitfld.long 0x0 12. "PRI_PER_EN,Group manager privileged access permission enable." "0,1" bitfld.long 0x0 11. "SEC_PER_LOCK,Lock for SEC_PER and SEC_PER_LOCK" "0,1" bitfld.long 0x0 9.--10. "SEC_PER,Group manager secure access permission. bit 0 for secure access bit 1 for non-secure access" "0,1,2,3" bitfld.long 0x0 8. "SEC_PER_EN,Group manager secure permission enable" "0,1" bitfld.long 0x0 7. "DID_LOCK,Lock write for DID_EN and DID" "0,1" newline hexmask.long.byte 0x0 3.--6. 1. "DID,Group manager domain ID" bitfld.long 0x0 2. "DID_EN,Group manager Domain ID enable" "0,1" bitfld.long 0x0 1. "GRP_MGR_EN_LOCK,Lock write for GPR_MGR_EN" "0,1" bitfld.long 0x0 0. "GRP_MGR_EN,Group manager enable. When the bit is disable there is no resource manager." "0,1" repeat.end repeat 8. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 )(list 0x0 0x14 0x28 0x3C 0x50 0x64 0x78 0x8C ) group.long ($2+0x2104)++0x3 line.long 0x0 "GRP_MGR_MA0_$1,Assign master 0~31 for group manager 0" hexmask.long 0x0 0.--31. 1. "MID,Assign master 0~31 for resource manager" repeat.end repeat 8. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 )(list 0x0 0x14 0x28 0x3C 0x50 0x64 0x78 0x8C ) group.long ($2+0x2108)++0x3 line.long 0x0 "GRP_MGR_MA1_$1,Assign master 32~63 for group manager 0" hexmask.long 0x0 0.--31. 1. "MID,Indicate if master 32~63 is resource manager." repeat.end repeat 8. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 )(list 0x0 0x14 0x28 0x3C 0x50 0x64 0x78 0x8C ) group.long ($2+0x210C)++0x3 line.long 0x0 "GRP_MGR_MA2_$1,Assign master 64~95 for group manager 0" hexmask.long 0x0 0.--31. 1. "MID,Indicate if master 64~95 is resource manager." repeat.end repeat 8. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 )(list 0x0 0x14 0x28 0x3C 0x50 0x64 0x78 0x8C ) group.long ($2+0x2110)++0x3 line.long 0x0 "GRP_MGR_MA3_$1,Assign master 96~127 for group manager 0" hexmask.long 0x0 0.--31. 1. "MID,Indicate if master 96~127 is resource manager." repeat.end group.long 0x2200++0x3 line.long 0x0 "DOM_GID_0,Indicate which group domain 0 belong to" bitfld.long 0x0 3. "LOCK,Lock write for GID" "0,1" bitfld.long 0x0 0.--2. "GID,Group ID" "0,1,2,3,4,5,6,7" repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x18 0x30 0x48 0x60 0x78 0x90 0xA8 0xC0 0xD8 0xF0 0x108 0x120 0x138 0x150 0x168 ) group.long ($2+0x2204)++0x3 line.long 0x0 "DOM_OWN_$1,Assign owner for function domain 0." bitfld.long 0x0 17. "MID_LOCK,Lock write for MID_EN and MID_LOW and MID_HIG registers." "0,1" bitfld.long 0x0 16. "MID_EN,Master ID check enable" "0,1" bitfld.long 0x0 15. "PRI_PER_LOCK,Lock write for PRI_PER and PRI_PER_EN" "0,1" bitfld.long 0x0 13.--14. "PRI_PER,Group manager privileged access permission. bit0 for privileged access bit1 for user access" "0,1,2,3" newline bitfld.long 0x0 12. "PRI_PER_EN,Group manager privileged access permission enable." "0,1" bitfld.long 0x0 11. "SEC_PER_LOCK,Lock for SEC_PER and SEC_PER_LOCK" "0,1" bitfld.long 0x0 9.--10. "SEC_PER,Domain owner secure access permission. bit 0 for secure access bit 1 for non-secure access" "0,1,2,3" bitfld.long 0x0 8. "SEC_PER_EN,Domain owner secure permission enable" "0,1" newline bitfld.long 0x0 1. "DOM_OWN_EN_LOCK,Lock for DOM_OWN_EN" "0,1" bitfld.long 0x0 0. "DOM_OWN_EN,Domain owner enable. When the bit is disable there is no domain owner." "0,1" repeat.end repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x18 0x30 0x48 0x60 0x78 0x90 0xA8 0xC0 0xD8 0xF0 0x108 0x120 0x138 0x150 0x168 ) group.long ($2+0x2208)++0x3 line.long 0x0 "DOM_OWN_MA0_$1,Assign master 0~31 for domain owner 0" hexmask.long 0x0 0.--31. 1. "MID,Assign master 0~31 for resource manager" repeat.end repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x18 0x30 0x48 0x60 0x78 0x90 0xA8 0xC0 0xD8 0xF0 0x108 0x120 0x138 0x150 0x168 ) group.long ($2+0x220C)++0x3 line.long 0x0 "DOM_OWN_MA1_$1,Assign master 32~63 for domain owner 0" hexmask.long 0x0 0.--31. 1. "MID,Indicate if master 32~63 is resource manager." repeat.end repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x18 0x30 0x48 0x60 0x78 0x90 0xA8 0xC0 0xD8 0xF0 0x108 0x120 0x138 0x150 0x168 ) group.long ($2+0x2210)++0x3 line.long 0x0 "DOM_OWN_MA2_$1,Assign master 64~95 for domain owner 0" hexmask.long 0x0 0.--31. 1. "MID,Indicate if master 64~95 is resource manager." repeat.end repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x18 0x30 0x48 0x60 0x78 0x90 0xA8 0xC0 0xD8 0xF0 0x108 0x120 0x138 0x150 0x168 ) group.long ($2+0x2214)++0x3 line.long 0x0 "DOM_OWN_MA3_$1,Assign master 96~127 for domain owner 0" hexmask.long 0x0 0.--31. 1. "MID,Indicate if master 96~127 is resource manager." repeat.end group.long 0x2218++0x3 line.long 0x0 "DOM_GID_1,Indicate which group domain 1 belong to" bitfld.long 0x0 3. "LOCK,Lock write for GID" "0,1" bitfld.long 0x0 0.--2. "GID,Group ID" "0,1,2,3,4,5,6,7" group.long 0x2230++0x3 line.long 0x0 "DOM_GID_2,Indicate which group domain 2 belong to" bitfld.long 0x0 3. "LOCK,Lock write for GID" "0,1" bitfld.long 0x0 0.--2. "GID,Group ID" "0,1,2,3,4,5,6,7" group.long 0x2248++0x3 line.long 0x0 "DOM_GID_3,Indicate which group domain 3 belong to" bitfld.long 0x0 3. "LOCK,Lock write for GID" "0,1" bitfld.long 0x0 0.--2. "GID,Group ID" "0,1,2,3,4,5,6,7" group.long 0x2260++0x3 line.long 0x0 "DOM_GID_4,Indicate which group domain 4 belong to" bitfld.long 0x0 3. "LOCK,Lock write for GID" "0,1" bitfld.long 0x0 0.--2. "GID,Group ID" "0,1,2,3,4,5,6,7" group.long 0x2278++0x3 line.long 0x0 "DOM_GID_5,Indicate which group domain 5 belong to" bitfld.long 0x0 3. "LOCK,Lock write for GID" "0,1" bitfld.long 0x0 0.--2. "GID,Group ID" "0,1,2,3,4,5,6,7" group.long 0x2290++0x3 line.long 0x0 "DOM_GID_6,Indicate which group domain 6 belong to" bitfld.long 0x0 3. "LOCK,Lock write for GID" "0,1" bitfld.long 0x0 0.--2. "GID,Group ID" "0,1,2,3,4,5,6,7" group.long 0x22A8++0x3 line.long 0x0 "DOM_GID_7,Indicate which group domain 7 belong to" bitfld.long 0x0 3. "LOCK,Lock write for GID" "0,1" bitfld.long 0x0 0.--2. "GID,Group ID" "0,1,2,3,4,5,6,7" group.long 0x22C0++0x3 line.long 0x0 "DOM_GID_8,Indicate which group domain 8 belong to" bitfld.long 0x0 3. "LOCK,Lock write for GID" "0,1" bitfld.long 0x0 0.--2. "GID,Group ID" "0,1,2,3,4,5,6,7" group.long 0x22D8++0x3 line.long 0x0 "DOM_GID_9,Indicate which group domain 9 belong to" bitfld.long 0x0 3. "LOCK,Lock write for GID" "0,1" bitfld.long 0x0 0.--2. "GID,Group ID" "0,1,2,3,4,5,6,7" group.long 0x22F0++0x3 line.long 0x0 "DOM_GID_10,Indicate which group domain 10 belong to" bitfld.long 0x0 3. "LOCK,Lock write for GID" "0,1" bitfld.long 0x0 0.--2. "GID,Group ID" "0,1,2,3,4,5,6,7" group.long 0x2308++0x3 line.long 0x0 "DOM_GID_11,Indicate which group domain 11 belong to" bitfld.long 0x0 3. "LOCK,Lock write for GID" "0,1" bitfld.long 0x0 0.--2. "GID,Group ID" "0,1,2,3,4,5,6,7" group.long 0x2320++0x3 line.long 0x0 "DOM_GID_12,Indicate which group domain 12 belong to" bitfld.long 0x0 3. "LOCK,Lock write for GID" "0,1" bitfld.long 0x0 0.--2. "GID,Group ID" "0,1,2,3,4,5,6,7" group.long 0x2338++0x3 line.long 0x0 "DOM_GID_13,Indicate which group domain 13 belong to" bitfld.long 0x0 3. "LOCK,Lock write for GID" "0,1" bitfld.long 0x0 0.--2. "GID,Group ID" "0,1,2,3,4,5,6,7" group.long 0x2350++0x3 line.long 0x0 "DOM_GID_14,Indicate which group domain 14 belong to" bitfld.long 0x0 3. "LOCK,Lock write for GID" "0,1" bitfld.long 0x0 0.--2. "GID,Group ID" "0,1,2,3,4,5,6,7" group.long 0x2368++0x3 line.long 0x0 "DOM_GID_15,Indicate which group domain 15 belong to" bitfld.long 0x0 3. "LOCK,Lock write for GID" "0,1" bitfld.long 0x0 0.--2. "GID,Group ID" "0,1,2,3,4,5,6,7" repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x34 0x68 0x9C 0xD0 0x104 0x138 0x16C 0x1A0 0x1D4 0x208 0x23C 0x270 0x2A4 0x2D8 0x30C ) group.long ($2+0x2400)++0x3 line.long 0x0 "DOM_PER0_$1,Domain Permission Control. It can be only configured by resource manager and domain owner." bitfld.long 0x0 31. "DOM7_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 29.--30. "DOM7_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 28. "DOM7_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 27. "DOM6_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 25.--26. "DOM6_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" newline bitfld.long 0x0 24. "DOM6_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 23. "DOM5_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 21.--22. "DOM5_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 20. "DOM5_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 19. "DOM4_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" newline bitfld.long 0x0 17.--18. "DOM4_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM4_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 15. "DOM3_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 13.--14. "DOM3_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 12. "DOM3_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" newline bitfld.long 0x0 11. "DOM2_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 9.--10. "DOM2_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM2_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 7. "DOM1_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 5.--6. "DOM1_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" newline bitfld.long 0x0 4. "DOM1_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 3. "DOM0_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 1.--2. "DOM0_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM0_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" repeat.end repeat 16. (list 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1A 0x1B 0x1C 0x1D 0x1E 0x1F )(list 0x340 0x374 0x3A8 0x3DC 0x410 0x444 0x478 0x4AC 0x4E0 0x514 0x548 0x57C 0x5B0 0x5E4 0x618 0x64C ) group.long ($2+0x2400)++0x3 line.long 0x0 "DOM_PER0_$1,Domain Permission Control. It can be only configured by resource manager and domain owner." bitfld.long 0x0 31. "DOM7_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 29.--30. "DOM7_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 28. "DOM7_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 27. "DOM6_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 25.--26. "DOM6_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" newline bitfld.long 0x0 24. "DOM6_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 23. "DOM5_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 21.--22. "DOM5_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 20. "DOM5_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 19. "DOM4_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" newline bitfld.long 0x0 17.--18. "DOM4_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM4_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 15. "DOM3_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 13.--14. "DOM3_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 12. "DOM3_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" newline bitfld.long 0x0 11. "DOM2_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 9.--10. "DOM2_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM2_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 7. "DOM1_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 5.--6. "DOM1_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" newline bitfld.long 0x0 4. "DOM1_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 3. "DOM0_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 1.--2. "DOM0_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM0_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" repeat.end repeat 16. (list 0x20 0x21 0x22 0x23 0x24 0x25 0x26 0x27 0x28 0x29 0x2A 0x2B 0x2C 0x2D 0x2E 0x2F )(list 0x680 0x6B4 0x6E8 0x71C 0x750 0x784 0x7B8 0x7EC 0x820 0x854 0x888 0x8BC 0x8F0 0x924 0x958 0x98C ) group.long ($2+0x2400)++0x3 line.long 0x0 "DOM_PER0_$1,Domain Permission Control. It can be only configured by resource manager and domain owner." bitfld.long 0x0 31. "DOM7_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 29.--30. "DOM7_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 28. "DOM7_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 27. "DOM6_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 25.--26. "DOM6_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" newline bitfld.long 0x0 24. "DOM6_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 23. "DOM5_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 21.--22. "DOM5_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 20. "DOM5_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 19. "DOM4_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" newline bitfld.long 0x0 17.--18. "DOM4_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM4_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 15. "DOM3_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 13.--14. "DOM3_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 12. "DOM3_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" newline bitfld.long 0x0 11. "DOM2_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 9.--10. "DOM2_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM2_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 7. "DOM1_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 5.--6. "DOM1_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" newline bitfld.long 0x0 4. "DOM1_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 3. "DOM0_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 1.--2. "DOM0_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM0_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" repeat.end repeat 16. (list 0x30 0x31 0x32 0x33 0x34 0x35 0x36 0x37 0x38 0x39 0x3A 0x3B 0x3C 0x3D 0x3E 0x3F )(list 0x9C0 0x9F4 0xA28 0xA5C 0xA90 0xAC4 0xAF8 0xB2C 0xB60 0xB94 0xBC8 0xBFC 0xC30 0xC64 0xC98 0xCCC ) group.long ($2+0x2400)++0x3 line.long 0x0 "DOM_PER0_$1,Domain Permission Control. It can be only configured by resource manager and domain owner." bitfld.long 0x0 31. "DOM7_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 29.--30. "DOM7_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 28. "DOM7_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 27. "DOM6_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 25.--26. "DOM6_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" newline bitfld.long 0x0 24. "DOM6_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 23. "DOM5_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 21.--22. "DOM5_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 20. "DOM5_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 19. "DOM4_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" newline bitfld.long 0x0 17.--18. "DOM4_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM4_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 15. "DOM3_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 13.--14. "DOM3_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 12. "DOM3_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" newline bitfld.long 0x0 11. "DOM2_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 9.--10. "DOM2_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM2_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 7. "DOM1_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 5.--6. "DOM1_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" newline bitfld.long 0x0 4. "DOM1_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 3. "DOM0_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 1.--2. "DOM0_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM0_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" repeat.end repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x34 0x68 0x9C 0xD0 0x104 0x138 0x16C 0x1A0 0x1D4 0x208 0x23C 0x270 0x2A4 0x2D8 0x30C ) group.long ($2+0x2404)++0x3 line.long 0x0 "DOM_PER1_$1,Domain Permission Control. It can be only configured by resource manager and domain owner." bitfld.long 0x0 31. "DOM15_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 29.--30. "DOM15_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 28. "DOM15_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 27. "DOM14_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 25.--26. "DOM14_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" newline bitfld.long 0x0 24. "DOM14_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 23. "DOM13_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 21.--22. "DOM13_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 20. "DOM13_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 19. "DOM12_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" newline bitfld.long 0x0 17.--18. "DOM12_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM12_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 15. "DOM11_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 13.--14. "DOM11_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 12. "DOM11_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" newline bitfld.long 0x0 11. "DOM10_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 9.--10. "DOM10_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM10_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 7. "DOM9_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 5.--6. "DOM9_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" newline bitfld.long 0x0 4. "DOM9_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 3. "DOM8_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 1.--2. "DOM8_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM8_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" repeat.end repeat 16. (list 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1A 0x1B 0x1C 0x1D 0x1E 0x1F )(list 0x340 0x374 0x3A8 0x3DC 0x410 0x444 0x478 0x4AC 0x4E0 0x514 0x548 0x57C 0x5B0 0x5E4 0x618 0x64C ) group.long ($2+0x2404)++0x3 line.long 0x0 "DOM_PER1_$1,Domain Permission Control. It can be only configured by resource manager and domain owner." bitfld.long 0x0 31. "DOM15_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 29.--30. "DOM15_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 28. "DOM15_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 27. "DOM14_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 25.--26. "DOM14_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" newline bitfld.long 0x0 24. "DOM14_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 23. "DOM13_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 21.--22. "DOM13_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 20. "DOM13_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 19. "DOM12_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" newline bitfld.long 0x0 17.--18. "DOM12_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM12_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 15. "DOM11_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 13.--14. "DOM11_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 12. "DOM11_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" newline bitfld.long 0x0 11. "DOM10_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 9.--10. "DOM10_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM10_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 7. "DOM9_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 5.--6. "DOM9_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" newline bitfld.long 0x0 4. "DOM9_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 3. "DOM8_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 1.--2. "DOM8_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM8_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" repeat.end repeat 16. (list 0x20 0x21 0x22 0x23 0x24 0x25 0x26 0x27 0x28 0x29 0x2A 0x2B 0x2C 0x2D 0x2E 0x2F )(list 0x680 0x6B4 0x6E8 0x71C 0x750 0x784 0x7B8 0x7EC 0x820 0x854 0x888 0x8BC 0x8F0 0x924 0x958 0x98C ) group.long ($2+0x2404)++0x3 line.long 0x0 "DOM_PER1_$1,Domain Permission Control. It can be only configured by resource manager and domain owner." bitfld.long 0x0 31. "DOM15_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 29.--30. "DOM15_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 28. "DOM15_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 27. "DOM14_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 25.--26. "DOM14_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" newline bitfld.long 0x0 24. "DOM14_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 23. "DOM13_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 21.--22. "DOM13_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 20. "DOM13_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 19. "DOM12_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" newline bitfld.long 0x0 17.--18. "DOM12_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM12_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 15. "DOM11_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 13.--14. "DOM11_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 12. "DOM11_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" newline bitfld.long 0x0 11. "DOM10_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 9.--10. "DOM10_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM10_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 7. "DOM9_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 5.--6. "DOM9_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" newline bitfld.long 0x0 4. "DOM9_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 3. "DOM8_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 1.--2. "DOM8_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM8_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" repeat.end repeat 16. (list 0x30 0x31 0x32 0x33 0x34 0x35 0x36 0x37 0x38 0x39 0x3A 0x3B 0x3C 0x3D 0x3E 0x3F )(list 0x9C0 0x9F4 0xA28 0xA5C 0xA90 0xAC4 0xAF8 0xB2C 0xB60 0xB94 0xBC8 0xBFC 0xC30 0xC64 0xC98 0xCCC ) group.long ($2+0x2404)++0x3 line.long 0x0 "DOM_PER1_$1,Domain Permission Control. It can be only configured by resource manager and domain owner." bitfld.long 0x0 31. "DOM15_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 29.--30. "DOM15_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 28. "DOM15_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 27. "DOM14_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 25.--26. "DOM14_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" newline bitfld.long 0x0 24. "DOM14_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 23. "DOM13_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 21.--22. "DOM13_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 20. "DOM13_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 19. "DOM12_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" newline bitfld.long 0x0 17.--18. "DOM12_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM12_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 15. "DOM11_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 13.--14. "DOM11_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 12. "DOM11_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" newline bitfld.long 0x0 11. "DOM10_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 9.--10. "DOM10_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM10_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 7. "DOM9_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 5.--6. "DOM9_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" newline bitfld.long 0x0 4. "DOM9_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 3. "DOM8_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 1.--2. "DOM8_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM8_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" repeat.end repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x34 0x68 0x9C 0xD0 0x104 0x138 0x16C 0x1A0 0x1D4 0x208 0x23C 0x270 0x2A4 0x2D8 0x30C ) group.long ($2+0x2408)++0x3 line.long 0x0 "SEC_PER0_$1,This register is only used for resource manager to control secure access permission." bitfld.long 0x0 31. "DOM3_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM3_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM3_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM3_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM2_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM2_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM2_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM2_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM1_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM1_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM1_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM1_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM0_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM0_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM0_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM0_SEC_EN,Domain secure permission control enable" "0,1" repeat.end repeat 16. (list 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1A 0x1B 0x1C 0x1D 0x1E 0x1F )(list 0x340 0x374 0x3A8 0x3DC 0x410 0x444 0x478 0x4AC 0x4E0 0x514 0x548 0x57C 0x5B0 0x5E4 0x618 0x64C ) group.long ($2+0x2408)++0x3 line.long 0x0 "SEC_PER0_$1,This register is only used for resource manager to control secure access permission." bitfld.long 0x0 31. "DOM3_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM3_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM3_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM3_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM2_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM2_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM2_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM2_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM1_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM1_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM1_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM1_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM0_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM0_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM0_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM0_SEC_EN,Domain secure permission control enable" "0,1" repeat.end repeat 16. (list 0x20 0x21 0x22 0x23 0x24 0x25 0x26 0x27 0x28 0x29 0x2A 0x2B 0x2C 0x2D 0x2E 0x2F )(list 0x680 0x6B4 0x6E8 0x71C 0x750 0x784 0x7B8 0x7EC 0x820 0x854 0x888 0x8BC 0x8F0 0x924 0x958 0x98C ) group.long ($2+0x2408)++0x3 line.long 0x0 "SEC_PER0_$1,This register is only used for resource manager to control secure access permission." bitfld.long 0x0 31. "DOM3_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM3_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM3_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM3_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM2_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM2_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM2_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM2_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM1_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM1_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM1_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM1_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM0_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM0_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM0_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM0_SEC_EN,Domain secure permission control enable" "0,1" repeat.end repeat 16. (list 0x30 0x31 0x32 0x33 0x34 0x35 0x36 0x37 0x38 0x39 0x3A 0x3B 0x3C 0x3D 0x3E 0x3F )(list 0x9C0 0x9F4 0xA28 0xA5C 0xA90 0xAC4 0xAF8 0xB2C 0xB60 0xB94 0xBC8 0xBFC 0xC30 0xC64 0xC98 0xCCC ) group.long ($2+0x2408)++0x3 line.long 0x0 "SEC_PER0_$1,This register is only used for resource manager to control secure access permission." bitfld.long 0x0 31. "DOM3_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM3_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM3_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM3_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM2_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM2_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM2_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM2_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM1_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM1_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM1_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM1_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM0_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM0_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM0_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM0_SEC_EN,Domain secure permission control enable" "0,1" repeat.end repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x34 0x68 0x9C 0xD0 0x104 0x138 0x16C 0x1A0 0x1D4 0x208 0x23C 0x270 0x2A4 0x2D8 0x30C ) group.long ($2+0x240C)++0x3 line.long 0x0 "SEC_PER1_$1,This register is only used for resource manager to control secure access permission." bitfld.long 0x0 31. "DOM7_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM7_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM7_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM7_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM6_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM6_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM6_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM6_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM5_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM5_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM5_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM5_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM4_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM4_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM4_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM4_SEC_EN,Domain secure permission control enable" "0,1" repeat.end repeat 16. (list 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1A 0x1B 0x1C 0x1D 0x1E 0x1F )(list 0x340 0x374 0x3A8 0x3DC 0x410 0x444 0x478 0x4AC 0x4E0 0x514 0x548 0x57C 0x5B0 0x5E4 0x618 0x64C ) group.long ($2+0x240C)++0x3 line.long 0x0 "SEC_PER1_$1,This register is only used for resource manager to control secure access permission." bitfld.long 0x0 31. "DOM7_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM7_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM7_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM7_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM6_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM6_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM6_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM6_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM5_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM5_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM5_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM5_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM4_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM4_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM4_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM4_SEC_EN,Domain secure permission control enable" "0,1" repeat.end repeat 16. (list 0x20 0x21 0x22 0x23 0x24 0x25 0x26 0x27 0x28 0x29 0x2A 0x2B 0x2C 0x2D 0x2E 0x2F )(list 0x680 0x6B4 0x6E8 0x71C 0x750 0x784 0x7B8 0x7EC 0x820 0x854 0x888 0x8BC 0x8F0 0x924 0x958 0x98C ) group.long ($2+0x240C)++0x3 line.long 0x0 "SEC_PER1_$1,This register is only used for resource manager to control secure access permission." bitfld.long 0x0 31. "DOM7_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM7_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM7_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM7_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM6_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM6_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM6_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM6_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM5_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM5_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM5_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM5_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM4_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM4_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM4_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM4_SEC_EN,Domain secure permission control enable" "0,1" repeat.end repeat 16. (list 0x30 0x31 0x32 0x33 0x34 0x35 0x36 0x37 0x38 0x39 0x3A 0x3B 0x3C 0x3D 0x3E 0x3F )(list 0x9C0 0x9F4 0xA28 0xA5C 0xA90 0xAC4 0xAF8 0xB2C 0xB60 0xB94 0xBC8 0xBFC 0xC30 0xC64 0xC98 0xCCC ) group.long ($2+0x240C)++0x3 line.long 0x0 "SEC_PER1_$1,This register is only used for resource manager to control secure access permission." bitfld.long 0x0 31. "DOM7_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM7_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM7_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM7_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM6_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM6_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM6_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM6_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM5_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM5_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM5_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM5_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM4_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM4_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM4_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM4_SEC_EN,Domain secure permission control enable" "0,1" repeat.end repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x34 0x68 0x9C 0xD0 0x104 0x138 0x16C 0x1A0 0x1D4 0x208 0x23C 0x270 0x2A4 0x2D8 0x30C ) group.long ($2+0x2410)++0x3 line.long 0x0 "SEC_PER2_$1,This register is only used for resource manager to control secure access permission." bitfld.long 0x0 31. "DOM11_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM11_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM11_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM11_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM10_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM10_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM10_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM10_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM9_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM9_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM9_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM9_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM8_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM8_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM8_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM8_SEC_EN,Domain secure permission control enable" "0,1" repeat.end repeat 16. (list 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1A 0x1B 0x1C 0x1D 0x1E 0x1F )(list 0x340 0x374 0x3A8 0x3DC 0x410 0x444 0x478 0x4AC 0x4E0 0x514 0x548 0x57C 0x5B0 0x5E4 0x618 0x64C ) group.long ($2+0x2410)++0x3 line.long 0x0 "SEC_PER2_$1,This register is only used for resource manager to control secure access permission." bitfld.long 0x0 31. "DOM11_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM11_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM11_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM11_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM10_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM10_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM10_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM10_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM9_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM9_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM9_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM9_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM8_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM8_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM8_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM8_SEC_EN,Domain secure permission control enable" "0,1" repeat.end repeat 16. (list 0x20 0x21 0x22 0x23 0x24 0x25 0x26 0x27 0x28 0x29 0x2A 0x2B 0x2C 0x2D 0x2E 0x2F )(list 0x680 0x6B4 0x6E8 0x71C 0x750 0x784 0x7B8 0x7EC 0x820 0x854 0x888 0x8BC 0x8F0 0x924 0x958 0x98C ) group.long ($2+0x2410)++0x3 line.long 0x0 "SEC_PER2_$1,This register is only used for resource manager to control secure access permission." bitfld.long 0x0 31. "DOM11_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM11_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM11_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM11_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM10_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM10_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM10_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM10_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM9_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM9_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM9_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM9_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM8_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM8_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM8_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM8_SEC_EN,Domain secure permission control enable" "0,1" repeat.end repeat 16. (list 0x30 0x31 0x32 0x33 0x34 0x35 0x36 0x37 0x38 0x39 0x3A 0x3B 0x3C 0x3D 0x3E 0x3F )(list 0x9C0 0x9F4 0xA28 0xA5C 0xA90 0xAC4 0xAF8 0xB2C 0xB60 0xB94 0xBC8 0xBFC 0xC30 0xC64 0xC98 0xCCC ) group.long ($2+0x2410)++0x3 line.long 0x0 "SEC_PER2_$1,This register is only used for resource manager to control secure access permission." bitfld.long 0x0 31. "DOM11_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM11_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM11_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM11_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM10_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM10_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM10_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM10_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM9_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM9_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM9_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM9_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM8_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM8_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM8_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM8_SEC_EN,Domain secure permission control enable" "0,1" repeat.end repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x34 0x68 0x9C 0xD0 0x104 0x138 0x16C 0x1A0 0x1D4 0x208 0x23C 0x270 0x2A4 0x2D8 0x30C ) group.long ($2+0x2414)++0x3 line.long 0x0 "SEC_PER3_$1,This register is only used for resource manager to control secure access permission." bitfld.long 0x0 31. "DOM15_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM15_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM15_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM15_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM14_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM14_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM14_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM14_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM13_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM13_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM13_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM13_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM12_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM12_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM12_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM12_SEC_EN,Domain secure permission control enable" "0,1" repeat.end repeat 16. (list 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1A 0x1B 0x1C 0x1D 0x1E 0x1F )(list 0x340 0x374 0x3A8 0x3DC 0x410 0x444 0x478 0x4AC 0x4E0 0x514 0x548 0x57C 0x5B0 0x5E4 0x618 0x64C ) group.long ($2+0x2414)++0x3 line.long 0x0 "SEC_PER3_$1,This register is only used for resource manager to control secure access permission." bitfld.long 0x0 31. "DOM15_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM15_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM15_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM15_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM14_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM14_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM14_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM14_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM13_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM13_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM13_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM13_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM12_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM12_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM12_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM12_SEC_EN,Domain secure permission control enable" "0,1" repeat.end repeat 16. (list 0x20 0x21 0x22 0x23 0x24 0x25 0x26 0x27 0x28 0x29 0x2A 0x2B 0x2C 0x2D 0x2E 0x2F )(list 0x680 0x6B4 0x6E8 0x71C 0x750 0x784 0x7B8 0x7EC 0x820 0x854 0x888 0x8BC 0x8F0 0x924 0x958 0x98C ) group.long ($2+0x2414)++0x3 line.long 0x0 "SEC_PER3_$1,This register is only used for resource manager to control secure access permission." bitfld.long 0x0 31. "DOM15_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM15_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM15_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM15_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM14_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM14_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM14_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM14_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM13_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM13_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM13_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM13_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM12_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM12_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM12_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM12_SEC_EN,Domain secure permission control enable" "0,1" repeat.end repeat 16. (list 0x30 0x31 0x32 0x33 0x34 0x35 0x36 0x37 0x38 0x39 0x3A 0x3B 0x3C 0x3D 0x3E 0x3F )(list 0x9C0 0x9F4 0xA28 0xA5C 0xA90 0xAC4 0xAF8 0xB2C 0xB60 0xB94 0xBC8 0xBFC 0xC30 0xC64 0xC98 0xCCC ) group.long ($2+0x2414)++0x3 line.long 0x0 "SEC_PER3_$1,This register is only used for resource manager to control secure access permission." bitfld.long 0x0 31. "DOM15_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM15_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM15_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM15_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM14_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM14_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM14_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM14_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM13_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM13_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM13_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM13_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM12_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM12_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM12_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM12_SEC_EN,Domain secure permission control enable" "0,1" repeat.end repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x34 0x68 0x9C 0xD0 0x104 0x138 0x16C 0x1A0 0x1D4 0x208 0x23C 0x270 0x2A4 0x2D8 0x30C ) group.long ($2+0x2418)++0x3 line.long 0x0 "PRI_PER0_$1,This register is only used for resource manager to control privileged access permission." bitfld.long 0x0 31. "DOM3_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM3_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM3_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM3_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM2_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM2_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM2_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM2_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM1_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM1_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM1_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM1_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM0_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM0_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM0_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM0_PRI_EN,Domain privileged permission control enable" "0,1" repeat.end repeat 16. (list 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1A 0x1B 0x1C 0x1D 0x1E 0x1F )(list 0x340 0x374 0x3A8 0x3DC 0x410 0x444 0x478 0x4AC 0x4E0 0x514 0x548 0x57C 0x5B0 0x5E4 0x618 0x64C ) group.long ($2+0x2418)++0x3 line.long 0x0 "PRI_PER0_$1,This register is only used for resource manager to control privileged access permission." bitfld.long 0x0 31. "DOM3_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM3_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM3_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM3_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM2_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM2_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM2_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM2_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM1_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM1_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM1_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM1_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM0_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM0_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM0_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM0_PRI_EN,Domain privileged permission control enable" "0,1" repeat.end repeat 16. (list 0x20 0x21 0x22 0x23 0x24 0x25 0x26 0x27 0x28 0x29 0x2A 0x2B 0x2C 0x2D 0x2E 0x2F )(list 0x680 0x6B4 0x6E8 0x71C 0x750 0x784 0x7B8 0x7EC 0x820 0x854 0x888 0x8BC 0x8F0 0x924 0x958 0x98C ) group.long ($2+0x2418)++0x3 line.long 0x0 "PRI_PER0_$1,This register is only used for resource manager to control privileged access permission." bitfld.long 0x0 31. "DOM3_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM3_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM3_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM3_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM2_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM2_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM2_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM2_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM1_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM1_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM1_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM1_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM0_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM0_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM0_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM0_PRI_EN,Domain privileged permission control enable" "0,1" repeat.end repeat 16. (list 0x30 0x31 0x32 0x33 0x34 0x35 0x36 0x37 0x38 0x39 0x3A 0x3B 0x3C 0x3D 0x3E 0x3F )(list 0x9C0 0x9F4 0xA28 0xA5C 0xA90 0xAC4 0xAF8 0xB2C 0xB60 0xB94 0xBC8 0xBFC 0xC30 0xC64 0xC98 0xCCC ) group.long ($2+0x2418)++0x3 line.long 0x0 "PRI_PER0_$1,This register is only used for resource manager to control privileged access permission." bitfld.long 0x0 31. "DOM3_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM3_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM3_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM3_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM2_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM2_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM2_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM2_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM1_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM1_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM1_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM1_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM0_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM0_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM0_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM0_PRI_EN,Domain privileged permission control enable" "0,1" repeat.end repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x34 0x68 0x9C 0xD0 0x104 0x138 0x16C 0x1A0 0x1D4 0x208 0x23C 0x270 0x2A4 0x2D8 0x30C ) group.long ($2+0x241C)++0x3 line.long 0x0 "PRI_PER1_$1,This register is only used for resource manager to control privileged access permission." bitfld.long 0x0 31. "DOM7_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM7_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM7_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM7_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM6_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM6_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM6_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM6_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM5_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM5_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM5_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM5_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM4_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM4_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM4_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM4_PRI_EN,Domain privileged permission control enable" "0,1" repeat.end repeat 16. (list 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1A 0x1B 0x1C 0x1D 0x1E 0x1F )(list 0x340 0x374 0x3A8 0x3DC 0x410 0x444 0x478 0x4AC 0x4E0 0x514 0x548 0x57C 0x5B0 0x5E4 0x618 0x64C ) group.long ($2+0x241C)++0x3 line.long 0x0 "PRI_PER1_$1,This register is only used for resource manager to control privileged access permission." bitfld.long 0x0 31. "DOM7_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM7_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM7_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM7_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM6_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM6_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM6_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM6_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM5_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM5_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM5_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM5_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM4_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM4_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM4_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM4_PRI_EN,Domain privileged permission control enable" "0,1" repeat.end repeat 16. (list 0x20 0x21 0x22 0x23 0x24 0x25 0x26 0x27 0x28 0x29 0x2A 0x2B 0x2C 0x2D 0x2E 0x2F )(list 0x680 0x6B4 0x6E8 0x71C 0x750 0x784 0x7B8 0x7EC 0x820 0x854 0x888 0x8BC 0x8F0 0x924 0x958 0x98C ) group.long ($2+0x241C)++0x3 line.long 0x0 "PRI_PER1_$1,This register is only used for resource manager to control privileged access permission." bitfld.long 0x0 31. "DOM7_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM7_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM7_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM7_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM6_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM6_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM6_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM6_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM5_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM5_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM5_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM5_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM4_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM4_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM4_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM4_PRI_EN,Domain privileged permission control enable" "0,1" repeat.end repeat 16. (list 0x30 0x31 0x32 0x33 0x34 0x35 0x36 0x37 0x38 0x39 0x3A 0x3B 0x3C 0x3D 0x3E 0x3F )(list 0x9C0 0x9F4 0xA28 0xA5C 0xA90 0xAC4 0xAF8 0xB2C 0xB60 0xB94 0xBC8 0xBFC 0xC30 0xC64 0xC98 0xCCC ) group.long ($2+0x241C)++0x3 line.long 0x0 "PRI_PER1_$1,This register is only used for resource manager to control privileged access permission." bitfld.long 0x0 31. "DOM7_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM7_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM7_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM7_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM6_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM6_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM6_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM6_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM5_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM5_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM5_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM5_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM4_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM4_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM4_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM4_PRI_EN,Domain privileged permission control enable" "0,1" repeat.end repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x34 0x68 0x9C 0xD0 0x104 0x138 0x16C 0x1A0 0x1D4 0x208 0x23C 0x270 0x2A4 0x2D8 0x30C ) group.long ($2+0x2420)++0x3 line.long 0x0 "PRI_PER2_$1,This register is only used for resource manager to control privileged access permission." bitfld.long 0x0 31. "DOM11_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM11_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM11_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM11_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM10_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM10_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM10_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM10_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM9_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM9_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM9_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM9_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM8_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM8_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM8_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM8_PRI_EN,Domain privileged permission control enable" "0,1" repeat.end repeat 16. (list 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1A 0x1B 0x1C 0x1D 0x1E 0x1F )(list 0x340 0x374 0x3A8 0x3DC 0x410 0x444 0x478 0x4AC 0x4E0 0x514 0x548 0x57C 0x5B0 0x5E4 0x618 0x64C ) group.long ($2+0x2420)++0x3 line.long 0x0 "PRI_PER2_$1,This register is only used for resource manager to control privileged access permission." bitfld.long 0x0 31. "DOM11_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM11_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM11_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM11_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM10_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM10_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM10_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM10_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM9_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM9_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM9_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM9_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM8_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM8_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM8_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM8_PRI_EN,Domain privileged permission control enable" "0,1" repeat.end repeat 16. (list 0x20 0x21 0x22 0x23 0x24 0x25 0x26 0x27 0x28 0x29 0x2A 0x2B 0x2C 0x2D 0x2E 0x2F )(list 0x680 0x6B4 0x6E8 0x71C 0x750 0x784 0x7B8 0x7EC 0x820 0x854 0x888 0x8BC 0x8F0 0x924 0x958 0x98C ) group.long ($2+0x2420)++0x3 line.long 0x0 "PRI_PER2_$1,This register is only used for resource manager to control privileged access permission." bitfld.long 0x0 31. "DOM11_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM11_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM11_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM11_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM10_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM10_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM10_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM10_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM9_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM9_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM9_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM9_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM8_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM8_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM8_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM8_PRI_EN,Domain privileged permission control enable" "0,1" repeat.end repeat 16. (list 0x30 0x31 0x32 0x33 0x34 0x35 0x36 0x37 0x38 0x39 0x3A 0x3B 0x3C 0x3D 0x3E 0x3F )(list 0x9C0 0x9F4 0xA28 0xA5C 0xA90 0xAC4 0xAF8 0xB2C 0xB60 0xB94 0xBC8 0xBFC 0xC30 0xC64 0xC98 0xCCC ) group.long ($2+0x2420)++0x3 line.long 0x0 "PRI_PER2_$1,This register is only used for resource manager to control privileged access permission." bitfld.long 0x0 31. "DOM11_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM11_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM11_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM11_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM10_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM10_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM10_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM10_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM9_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM9_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM9_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM9_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM8_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM8_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM8_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM8_PRI_EN,Domain privileged permission control enable" "0,1" repeat.end repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x34 0x68 0x9C 0xD0 0x104 0x138 0x16C 0x1A0 0x1D4 0x208 0x23C 0x270 0x2A4 0x2D8 0x30C ) group.long ($2+0x2424)++0x3 line.long 0x0 "PRI_PER3_$1,This register is only used for resource manager to control privileged access permission." bitfld.long 0x0 31. "DOM15_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM15_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM15_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM15_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM14_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM14_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM14_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM14_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM13_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM13_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM13_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM13_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM12_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM12_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM12_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM12_PRI_EN,Domain privileged permission control enable" "0,1" repeat.end repeat 16. (list 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1A 0x1B 0x1C 0x1D 0x1E 0x1F )(list 0x340 0x374 0x3A8 0x3DC 0x410 0x444 0x478 0x4AC 0x4E0 0x514 0x548 0x57C 0x5B0 0x5E4 0x618 0x64C ) group.long ($2+0x2424)++0x3 line.long 0x0 "PRI_PER3_$1,This register is only used for resource manager to control privileged access permission." bitfld.long 0x0 31. "DOM15_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM15_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM15_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM15_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM14_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM14_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM14_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM14_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM13_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM13_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM13_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM13_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM12_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM12_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM12_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM12_PRI_EN,Domain privileged permission control enable" "0,1" repeat.end repeat 16. (list 0x20 0x21 0x22 0x23 0x24 0x25 0x26 0x27 0x28 0x29 0x2A 0x2B 0x2C 0x2D 0x2E 0x2F )(list 0x680 0x6B4 0x6E8 0x71C 0x750 0x784 0x7B8 0x7EC 0x820 0x854 0x888 0x8BC 0x8F0 0x924 0x958 0x98C ) group.long ($2+0x2424)++0x3 line.long 0x0 "PRI_PER3_$1,This register is only used for resource manager to control privileged access permission." bitfld.long 0x0 31. "DOM15_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM15_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM15_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM15_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM14_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM14_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM14_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM14_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM13_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM13_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM13_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM13_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM12_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM12_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM12_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM12_PRI_EN,Domain privileged permission control enable" "0,1" repeat.end repeat 16. (list 0x30 0x31 0x32 0x33 0x34 0x35 0x36 0x37 0x38 0x39 0x3A 0x3B 0x3C 0x3D 0x3E 0x3F )(list 0x9C0 0x9F4 0xA28 0xA5C 0xA90 0xAC4 0xAF8 0xB2C 0xB60 0xB94 0xBC8 0xBFC 0xC30 0xC64 0xC98 0xCCC ) group.long ($2+0x2424)++0x3 line.long 0x0 "PRI_PER3_$1,This register is only used for resource manager to control privileged access permission." bitfld.long 0x0 31. "DOM15_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM15_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM15_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM15_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM14_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM14_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM14_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM14_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM13_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM13_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM13_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM13_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM12_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM12_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM12_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM12_PRI_EN,Domain privileged permission control enable" "0,1" repeat.end repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x34 0x68 0x9C 0xD0 0x104 0x138 0x16C 0x1A0 0x1D4 0x208 0x23C 0x270 0x2A4 0x2D8 0x30C ) group.long ($2+0x2428)++0x3 line.long 0x0 "DOM_SEC_PER_$1,This register is only used for domain master to control secure access permission. When the domain master write this register. it only changes the secure permission for itself. When the domain master read this register. it gets permission.." bitfld.long 0x0 7. "DOM_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" newline bitfld.long 0x0 0. "DOM_SEC_EN,Domain secure permission control enable" "0,1" repeat.end repeat 16. (list 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1A 0x1B 0x1C 0x1D 0x1E 0x1F )(list 0x340 0x374 0x3A8 0x3DC 0x410 0x444 0x478 0x4AC 0x4E0 0x514 0x548 0x57C 0x5B0 0x5E4 0x618 0x64C ) group.long ($2+0x2428)++0x3 line.long 0x0 "DOM_SEC_PER_$1,This register is only used for domain master to control secure access permission. When the domain master write this register. it only changes the secure permission for itself. When the domain master read this register. it gets permission.." bitfld.long 0x0 7. "DOM_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" newline bitfld.long 0x0 0. "DOM_SEC_EN,Domain secure permission control enable" "0,1" repeat.end repeat 16. (list 0x20 0x21 0x22 0x23 0x24 0x25 0x26 0x27 0x28 0x29 0x2A 0x2B 0x2C 0x2D 0x2E 0x2F )(list 0x680 0x6B4 0x6E8 0x71C 0x750 0x784 0x7B8 0x7EC 0x820 0x854 0x888 0x8BC 0x8F0 0x924 0x958 0x98C ) group.long ($2+0x2428)++0x3 line.long 0x0 "DOM_SEC_PER_$1,This register is only used for domain master to control secure access permission. When the domain master write this register. it only changes the secure permission for itself. When the domain master read this register. it gets permission.." bitfld.long 0x0 7. "DOM_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" newline bitfld.long 0x0 0. "DOM_SEC_EN,Domain secure permission control enable" "0,1" repeat.end repeat 16. (list 0x30 0x31 0x32 0x33 0x34 0x35 0x36 0x37 0x38 0x39 0x3A 0x3B 0x3C 0x3D 0x3E 0x3F )(list 0x9C0 0x9F4 0xA28 0xA5C 0xA90 0xAC4 0xAF8 0xB2C 0xB60 0xB94 0xBC8 0xBFC 0xC30 0xC64 0xC98 0xCCC ) group.long ($2+0x2428)++0x3 line.long 0x0 "DOM_SEC_PER_$1,This register is only used for domain master to control secure access permission. When the domain master write this register. it only changes the secure permission for itself. When the domain master read this register. it gets permission.." bitfld.long 0x0 7. "DOM_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" newline bitfld.long 0x0 0. "DOM_SEC_EN,Domain secure permission control enable" "0,1" repeat.end repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x34 0x68 0x9C 0xD0 0x104 0x138 0x16C 0x1A0 0x1D4 0x208 0x23C 0x270 0x2A4 0x2D8 0x30C ) group.long ($2+0x242C)++0x3 line.long 0x0 "DOM_PRI_PER_$1,This register is only used for domain master to control secure access permission. When the domain master write this register. it only changes the secure permission for itself. When the domain master read this register. it gets permission.." bitfld.long 0x0 7. "DOM_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" newline bitfld.long 0x0 0. "DOM_PRI_EN,Domain privileged permission control enable" "0,1" repeat.end repeat 16. (list 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1A 0x1B 0x1C 0x1D 0x1E 0x1F )(list 0x340 0x374 0x3A8 0x3DC 0x410 0x444 0x478 0x4AC 0x4E0 0x514 0x548 0x57C 0x5B0 0x5E4 0x618 0x64C ) group.long ($2+0x242C)++0x3 line.long 0x0 "DOM_PRI_PER_$1,This register is only used for domain master to control secure access permission. When the domain master write this register. it only changes the secure permission for itself. When the domain master read this register. it gets permission.." bitfld.long 0x0 7. "DOM_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" newline bitfld.long 0x0 0. "DOM_PRI_EN,Domain privileged permission control enable" "0,1" repeat.end repeat 16. (list 0x20 0x21 0x22 0x23 0x24 0x25 0x26 0x27 0x28 0x29 0x2A 0x2B 0x2C 0x2D 0x2E 0x2F )(list 0x680 0x6B4 0x6E8 0x71C 0x750 0x784 0x7B8 0x7EC 0x820 0x854 0x888 0x8BC 0x8F0 0x924 0x958 0x98C ) group.long ($2+0x242C)++0x3 line.long 0x0 "DOM_PRI_PER_$1,This register is only used for domain master to control secure access permission. When the domain master write this register. it only changes the secure permission for itself. When the domain master read this register. it gets permission.." bitfld.long 0x0 7. "DOM_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" newline bitfld.long 0x0 0. "DOM_PRI_EN,Domain privileged permission control enable" "0,1" repeat.end repeat 16. (list 0x30 0x31 0x32 0x33 0x34 0x35 0x36 0x37 0x38 0x39 0x3A 0x3B 0x3C 0x3D 0x3E 0x3F )(list 0x9C0 0x9F4 0xA28 0xA5C 0xA90 0xAC4 0xAF8 0xB2C 0xB60 0xB94 0xBC8 0xBFC 0xC30 0xC64 0xC98 0xCCC ) group.long ($2+0x242C)++0x3 line.long 0x0 "DOM_PRI_PER_$1,This register is only used for domain master to control secure access permission. When the domain master write this register. it only changes the secure permission for itself. When the domain master read this register. it gets permission.." bitfld.long 0x0 7. "DOM_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" newline bitfld.long 0x0 0. "DOM_PRI_EN,Domain privileged permission control enable" "0,1" repeat.end repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x34 0x68 0x9C 0xD0 0x104 0x138 0x16C 0x1A0 0x1D4 0x208 0x23C 0x270 0x2A4 0x2D8 0x30C ) group.long ($2+0x2430)++0x3 line.long 0x0 "DOM_ASSIGN_$1,Use to assign domain for accessing DOM_SEC_PER and DOM_PRI_PER register. Only resource manager. group manager and domain owner can access this register. For write. group manager must write its owen domain ID. otherwise write accessing will.." hexmask.long.byte 0x0 0.--3. 1. "DID,accessing DOM_SEC_PER and DOM_PRI_PER register" repeat.end repeat 16. (list 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1A 0x1B 0x1C 0x1D 0x1E 0x1F )(list 0x340 0x374 0x3A8 0x3DC 0x410 0x444 0x478 0x4AC 0x4E0 0x514 0x548 0x57C 0x5B0 0x5E4 0x618 0x64C ) group.long ($2+0x2430)++0x3 line.long 0x0 "DOM_ASSIGN_$1,Use to assign domain for accessing DOM_SEC_PER and DOM_PRI_PER register. Only resource manager. group manager and domain owner can access this register. For write. group manager must write its owen domain ID. otherwise write accessing will.." hexmask.long.byte 0x0 0.--3. 1. "DID,accessing DOM_SEC_PER and DOM_PRI_PER register" repeat.end repeat 16. (list 0x20 0x21 0x22 0x23 0x24 0x25 0x26 0x27 0x28 0x29 0x2A 0x2B 0x2C 0x2D 0x2E 0x2F )(list 0x680 0x6B4 0x6E8 0x71C 0x750 0x784 0x7B8 0x7EC 0x820 0x854 0x888 0x8BC 0x8F0 0x924 0x958 0x98C ) group.long ($2+0x2430)++0x3 line.long 0x0 "DOM_ASSIGN_$1,Use to assign domain for accessing DOM_SEC_PER and DOM_PRI_PER register. Only resource manager. group manager and domain owner can access this register. For write. group manager must write its owen domain ID. otherwise write accessing will.." hexmask.long.byte 0x0 0.--3. 1. "DID,accessing DOM_SEC_PER and DOM_PRI_PER register" repeat.end repeat 16. (list 0x30 0x31 0x32 0x33 0x34 0x35 0x36 0x37 0x38 0x39 0x3A 0x3B 0x3C 0x3D 0x3E 0x3F )(list 0x9C0 0x9F4 0xA28 0xA5C 0xA90 0xAC4 0xAF8 0xB2C 0xB60 0xB94 0xBC8 0xBFC 0xC30 0xC64 0xC98 0xCCC ) group.long ($2+0x2430)++0x3 line.long 0x0 "DOM_ASSIGN_$1,Use to assign domain for accessing DOM_SEC_PER and DOM_PRI_PER register. Only resource manager. group manager and domain owner can access this register. For write. group manager must write its owen domain ID. otherwise write accessing will.." hexmask.long.byte 0x0 0.--3. 1. "DID,accessing DOM_SEC_PER and DOM_PRI_PER register" repeat.end repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x38 0x70 0xA8 0xE0 0x118 0x150 0x188 0x1C0 0x1F8 0x230 0x268 0x2A0 0x2D8 0x310 0x348 ) group.long ($2+0x3100)++0x3 line.long 0x0 "RGN_DOM_$1,Assign domain for peripheral. It can be only configured by resource and group manager" bitfld.long 0x0 31. "LOCK,When this bit is set lock write for all the bits in the register." "0,1" bitfld.long 0x0 4. "SET,Set together with DID would change permission of this resource to following setting: 1) Domain access control enabled. 2) Read/Write allowed for the domain owner. 3) Read/Write not allowed for all the other domains. If this bit is not set only DID.." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Assign domain for peripheral" repeat.end repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x38 0x70 0xA8 0xE0 0x118 0x150 0x188 0x1C0 0x1F8 0x230 0x268 0x2A0 0x2D8 0x310 0x348 ) group.long ($2+0x3104)++0x3 line.long 0x0 "RGN_DOM_PER0_$1,Domain Permission Control. It can be only configured by resource manager and domain owner." bitfld.long 0x0 31. "DOM7_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 29.--30. "DOM7_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 28. "DOM7_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 27. "DOM6_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 25.--26. "DOM6_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" newline bitfld.long 0x0 24. "DOM6_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 23. "DOM5_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 21.--22. "DOM5_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 20. "DOM5_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 19. "DOM4_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" newline bitfld.long 0x0 17.--18. "DOM4_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM4_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 15. "DOM3_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 13.--14. "DOM3_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 12. "DOM3_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" newline bitfld.long 0x0 11. "DOM2_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 9.--10. "DOM2_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM2_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 7. "DOM1_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 5.--6. "DOM1_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" newline bitfld.long 0x0 4. "DOM1_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 3. "DOM0_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 1.--2. "DOM0_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM0_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" repeat.end repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x38 0x70 0xA8 0xE0 0x118 0x150 0x188 0x1C0 0x1F8 0x230 0x268 0x2A0 0x2D8 0x310 0x348 ) group.long ($2+0x3108)++0x3 line.long 0x0 "RGN_DOM_PER1_$1,Domain Permission Control. It can be only configured by resource manager and domain owner." bitfld.long 0x0 31. "DOM15_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 29.--30. "DOM15_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 28. "DOM15_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 27. "DOM14_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 25.--26. "DOM14_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" newline bitfld.long 0x0 24. "DOM14_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 23. "DOM13_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 21.--22. "DOM13_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 20. "DOM13_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 19. "DOM12_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" newline bitfld.long 0x0 17.--18. "DOM12_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM12_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 15. "DOM11_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 13.--14. "DOM11_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 12. "DOM11_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" newline bitfld.long 0x0 11. "DOM10_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 9.--10. "DOM10_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM10_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 7. "DOM9_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 5.--6. "DOM9_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" newline bitfld.long 0x0 4. "DOM9_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 3. "DOM8_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 1.--2. "DOM8_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM8_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" repeat.end repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x38 0x70 0xA8 0xE0 0x118 0x150 0x188 0x1C0 0x1F8 0x230 0x268 0x2A0 0x2D8 0x310 0x348 ) group.long ($2+0x310C)++0x3 line.long 0x0 "RGN_SEC_PER0_$1,This register is only used for resource manager to control secure access permission." bitfld.long 0x0 31. "DOM3_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM3_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM3_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM3_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM2_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM2_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM2_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM2_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM1_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM1_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM1_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM1_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM0_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM0_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM0_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM0_SEC_EN,Domain secure permission control enable" "0,1" repeat.end repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x38 0x70 0xA8 0xE0 0x118 0x150 0x188 0x1C0 0x1F8 0x230 0x268 0x2A0 0x2D8 0x310 0x348 ) group.long ($2+0x3110)++0x3 line.long 0x0 "RGN_SEC_PER1_$1,This register is only used for resource manager to control secure access permission." bitfld.long 0x0 31. "DOM7_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM7_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM7_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM7_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM6_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM6_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM6_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM6_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM5_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM5_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM5_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM5_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM4_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM4_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM4_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM4_SEC_EN,Domain secure permission control enable" "0,1" repeat.end repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x38 0x70 0xA8 0xE0 0x118 0x150 0x188 0x1C0 0x1F8 0x230 0x268 0x2A0 0x2D8 0x310 0x348 ) group.long ($2+0x3114)++0x3 line.long 0x0 "RGN_SEC_PER2_$1,This register is only used for resource manager to control secure access permission." bitfld.long 0x0 31. "DOM11_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM11_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM11_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM11_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM10_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM10_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM10_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM10_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM9_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM9_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM9_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM9_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM8_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM8_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM8_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM8_SEC_EN,Domain secure permission control enable" "0,1" repeat.end repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x38 0x70 0xA8 0xE0 0x118 0x150 0x188 0x1C0 0x1F8 0x230 0x268 0x2A0 0x2D8 0x310 0x348 ) group.long ($2+0x3118)++0x3 line.long 0x0 "RGN_SEC_PER3_$1,This register is only used for resource manager to control secure access permission." bitfld.long 0x0 31. "DOM15_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM15_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM15_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM15_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM14_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM14_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM14_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM14_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM13_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM13_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM13_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM13_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM12_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM12_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM12_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM12_SEC_EN,Domain secure permission control enable" "0,1" repeat.end repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x38 0x70 0xA8 0xE0 0x118 0x150 0x188 0x1C0 0x1F8 0x230 0x268 0x2A0 0x2D8 0x310 0x348 ) group.long ($2+0x311C)++0x3 line.long 0x0 "RGN_PRI_PER0_$1,This register is only used for resource manager to control privileged access permission." bitfld.long 0x0 31. "DOM3_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM3_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM3_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM3_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM2_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM2_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM2_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM2_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM1_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM1_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM1_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM1_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM0_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM0_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM0_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM0_PRI_EN,Domain privileged permission control enable" "0,1" repeat.end repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x38 0x70 0xA8 0xE0 0x118 0x150 0x188 0x1C0 0x1F8 0x230 0x268 0x2A0 0x2D8 0x310 0x348 ) group.long ($2+0x3120)++0x3 line.long 0x0 "RGN_PRI_PER1_$1,This register is only used for resource manager to control privileged access permission." bitfld.long 0x0 31. "DOM7_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM7_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM7_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM7_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM6_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM6_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM6_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM6_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM5_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM5_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM5_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM5_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM4_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM4_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM4_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM4_PRI_EN,Domain privileged permission control enable" "0,1" repeat.end repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x38 0x70 0xA8 0xE0 0x118 0x150 0x188 0x1C0 0x1F8 0x230 0x268 0x2A0 0x2D8 0x310 0x348 ) group.long ($2+0x3124)++0x3 line.long 0x0 "RGN_PRI_PER2_$1,This register is only used for resource manager to control privileged access permission." bitfld.long 0x0 31. "DOM11_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM11_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM11_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM11_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM10_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM10_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM10_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM10_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM9_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM9_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM9_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM9_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM8_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM8_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM8_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM8_PRI_EN,Domain privileged permission control enable" "0,1" repeat.end repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x38 0x70 0xA8 0xE0 0x118 0x150 0x188 0x1C0 0x1F8 0x230 0x268 0x2A0 0x2D8 0x310 0x348 ) group.long ($2+0x3128)++0x3 line.long 0x0 "RGN_PRI_PER3_$1,This register is only used for resource manager to control privileged access permission." bitfld.long 0x0 31. "DOM15_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM15_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM15_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM15_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM14_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM14_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM14_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM14_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM13_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM13_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM13_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM13_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM12_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM12_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM12_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM12_PRI_EN,Domain privileged permission control enable" "0,1" repeat.end repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x38 0x70 0xA8 0xE0 0x118 0x150 0x188 0x1C0 0x1F8 0x230 0x268 0x2A0 0x2D8 0x310 0x348 ) group.long ($2+0x312C)++0x3 line.long 0x0 "RGN_DOM_SEC_PER_$1,This register is only used for domain master to control secure access permission. When the domain master write this register. it only changes the secure permission for itself. When the domain master read this register. it gets.." bitfld.long 0x0 7. "DOM_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" newline bitfld.long 0x0 0. "DOM_SEC_EN,Domain secure permission control enable" "0,1" repeat.end repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x38 0x70 0xA8 0xE0 0x118 0x150 0x188 0x1C0 0x1F8 0x230 0x268 0x2A0 0x2D8 0x310 0x348 ) group.long ($2+0x3130)++0x3 line.long 0x0 "RGN_DOM_PRI_PER_$1,This register is only used for domain master to control secure access permission. When the domain master write this register. it only changes the secure permission for itself. When the domain master read this register. it gets.." bitfld.long 0x0 7. "DOM_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" newline bitfld.long 0x0 0. "DOM_PRI_EN,Domain privileged permission control enable" "0,1" repeat.end repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x38 0x70 0xA8 0xE0 0x118 0x150 0x188 0x1C0 0x1F8 0x230 0x268 0x2A0 0x2D8 0x310 0x348 ) group.long ($2+0x3134)++0x3 line.long 0x0 "RGN_DOM_ASSIGN_$1,Use to assign domain for accessing DOM_SEC_PER and DOM_PRI_PER register. Only resource manager. group manager and domain owner can access this register. For write. group manager must write its owen domain ID. otherwise write accessing.." hexmask.long.byte 0x0 0.--3. 1. "DID,accessing DOM_SEC_PER and DOM_PRI_PER register" repeat.end tree.end tree "RPC_DISP_CLKGEN" base ad:0x36A00000 repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x4 0x8 0xC 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C ) group.long ($2)++0x3 line.long 0x0 "REGG0_DOM_$1,Assign domain for CKGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1A 0x1B 0x1C 0x1D 0x1E 0x1F )(list 0x40 0x44 0x48 0x4C 0x50 0x54 0x58 0x5C 0x60 0x64 0x68 0x6C 0x70 0x74 0x78 0x7C ) group.long ($2)++0x3 line.long 0x0 "REGG0_DOM_$1,Assign domain for CKGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x20 0x21 0x22 0x23 0x24 0x25 0x26 0x27 0x28 0x29 0x2A 0x2B 0x2C 0x2D 0x2E 0x2F )(list 0x80 0x84 0x88 0x8C 0x90 0x94 0x98 0x9C 0xA0 0xA4 0xA8 0xAC 0xB0 0xB4 0xB8 0xBC ) group.long ($2)++0x3 line.long 0x0 "REGG0_DOM_$1,Assign domain for CKGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x30 0x31 0x32 0x33 0x34 0x35 0x36 0x37 0x38 0x39 0x3A 0x3B 0x3C 0x3D 0x3E 0x3F )(list 0xC0 0xC4 0xC8 0xCC 0xD0 0xD4 0xD8 0xDC 0xE0 0xE4 0xE8 0xEC 0xF0 0xF4 0xF8 0xFC ) group.long ($2)++0x3 line.long 0x0 "REGG0_DOM_$1,Assign domain for CKGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x40 0x41 0x42 0x43 0x44 0x45 0x46 0x47 0x48 0x49 0x4A 0x4B 0x4C 0x4D 0x4E 0x4F )(list 0x100 0x104 0x108 0x10C 0x110 0x114 0x118 0x11C 0x120 0x124 0x128 0x12C 0x130 0x134 0x138 0x13C ) group.long ($2)++0x3 line.long 0x0 "REGG0_DOM_$1,Assign domain for CKGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x50 0x51 0x52 0x53 0x54 0x55 0x56 0x57 0x58 0x59 0x5A 0x5B 0x5C 0x5D 0x5E 0x5F )(list 0x140 0x144 0x148 0x14C 0x150 0x154 0x158 0x15C 0x160 0x164 0x168 0x16C 0x170 0x174 0x178 0x17C ) group.long ($2)++0x3 line.long 0x0 "REGG0_DOM_$1,Assign domain for CKGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x60 0x61 0x62 0x63 0x64 0x65 0x66 0x67 0x68 0x69 0x6A 0x6B 0x6C 0x6D 0x6E 0x6F )(list 0x180 0x184 0x188 0x18C 0x190 0x194 0x198 0x19C 0x1A0 0x1A4 0x1A8 0x1AC 0x1B0 0x1B4 0x1B8 0x1BC ) group.long ($2)++0x3 line.long 0x0 "REGG0_DOM_$1,Assign domain for CKGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x70 0x71 0x72 0x73 0x74 0x75 0x76 0x77 0x78 0x79 0x7A 0x7B 0x7C 0x7D 0x7E 0x7F )(list 0x1C0 0x1C4 0x1C8 0x1CC 0x1D0 0x1D4 0x1D8 0x1DC 0x1E0 0x1E4 0x1E8 0x1EC 0x1F0 0x1F4 0x1F8 0x1FC ) group.long ($2)++0x3 line.long 0x0 "REGG0_DOM_$1,Assign domain for CKGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x80 0x81 0x82 0x83 0x84 0x85 0x86 0x87 0x88 0x89 0x8A 0x8B 0x8C 0x8D 0x8E 0x8F )(list 0x200 0x204 0x208 0x20C 0x210 0x214 0x218 0x21C 0x220 0x224 0x228 0x22C 0x230 0x234 0x238 0x23C ) group.long ($2)++0x3 line.long 0x0 "REGG0_DOM_$1,Assign domain for CKGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x90 0x91 0x92 0x93 0x94 0x95 0x96 0x97 0x98 0x99 0x9A 0x9B 0x9C 0x9D 0x9E 0x9F )(list 0x240 0x244 0x248 0x24C 0x250 0x254 0x258 0x25C 0x260 0x264 0x268 0x26C 0x270 0x274 0x278 0x27C ) group.long ($2)++0x3 line.long 0x0 "REGG0_DOM_$1,Assign domain for CKGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xA0 0xA1 0xA2 0xA3 0xA4 0xA5 0xA6 0xA7 0xA8 0xA9 0xAA 0xAB 0xAC 0xAD 0xAE 0xAF )(list 0x280 0x284 0x288 0x28C 0x290 0x294 0x298 0x29C 0x2A0 0x2A4 0x2A8 0x2AC 0x2B0 0x2B4 0x2B8 0x2BC ) group.long ($2)++0x3 line.long 0x0 "REGG0_DOM_$1,Assign domain for CKGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xB0 0xB1 0xB2 0xB3 0xB4 0xB5 0xB6 0xB7 0xB8 0xB9 0xBA 0xBB 0xBC 0xBD 0xBE 0xBF )(list 0x2C0 0x2C4 0x2C8 0x2CC 0x2D0 0x2D4 0x2D8 0x2DC 0x2E0 0x2E4 0x2E8 0x2EC 0x2F0 0x2F4 0x2F8 0x2FC ) group.long ($2)++0x3 line.long 0x0 "REGG0_DOM_$1,Assign domain for CKGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xC0 0xC1 0xC2 0xC3 0xC4 0xC5 0xC6 0xC7 0xC8 0xC9 0xCA 0xCB 0xCC 0xCD 0xCE 0xCF )(list 0x300 0x304 0x308 0x30C 0x310 0x314 0x318 0x31C 0x320 0x324 0x328 0x32C 0x330 0x334 0x338 0x33C ) group.long ($2)++0x3 line.long 0x0 "REGG0_DOM_$1,Assign domain for CKGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xD0 0xD1 0xD2 0xD3 0xD4 0xD5 0xD6 0xD7 0xD8 0xD9 0xDA 0xDB 0xDC 0xDD 0xDE 0xDF )(list 0x340 0x344 0x348 0x34C 0x350 0x354 0x358 0x35C 0x360 0x364 0x368 0x36C 0x370 0x374 0x378 0x37C ) group.long ($2)++0x3 line.long 0x0 "REGG0_DOM_$1,Assign domain for CKGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xE0 0xE1 0xE2 0xE3 0xE4 0xE5 0xE6 0xE7 0xE8 0xE9 0xEA 0xEB 0xEC 0xED 0xEE 0xEF )(list 0x380 0x384 0x388 0x38C 0x390 0x394 0x398 0x39C 0x3A0 0x3A4 0x3A8 0x3AC 0x3B0 0x3B4 0x3B8 0x3BC ) group.long ($2)++0x3 line.long 0x0 "REGG0_DOM_$1,Assign domain for CKGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xF0 0xF1 0xF2 0xF3 0xF4 0xF5 0xF6 0xF7 0xF8 0xF9 0xFA 0xFB 0xFC 0xFD 0xFE 0xFF )(list 0x3C0 0x3C4 0x3C8 0x3CC 0x3D0 0x3D4 0x3D8 0x3DC 0x3E0 0x3E4 0x3E8 0x3EC 0x3F0 0x3F4 0x3F8 0x3FC ) group.long ($2)++0x3 line.long 0x0 "REGG0_DOM_$1,Assign domain for CKGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x4 0x8 0xC 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C ) group.long ($2+0x400)++0x3 line.long 0x0 "REGG1_DOM_$1,Assign domain for CKGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1A 0x1B 0x1C 0x1D 0x1E 0x1F )(list 0x40 0x44 0x48 0x4C 0x50 0x54 0x58 0x5C 0x60 0x64 0x68 0x6C 0x70 0x74 0x78 0x7C ) group.long ($2+0x400)++0x3 line.long 0x0 "REGG1_DOM_$1,Assign domain for CKGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x20 0x21 0x22 0x23 0x24 0x25 0x26 0x27 0x28 0x29 0x2A 0x2B 0x2C 0x2D 0x2E 0x2F )(list 0x80 0x84 0x88 0x8C 0x90 0x94 0x98 0x9C 0xA0 0xA4 0xA8 0xAC 0xB0 0xB4 0xB8 0xBC ) group.long ($2+0x400)++0x3 line.long 0x0 "REGG1_DOM_$1,Assign domain for CKGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x30 0x31 0x32 0x33 0x34 0x35 0x36 0x37 0x38 0x39 0x3A 0x3B 0x3C 0x3D 0x3E 0x3F )(list 0xC0 0xC4 0xC8 0xCC 0xD0 0xD4 0xD8 0xDC 0xE0 0xE4 0xE8 0xEC 0xF0 0xF4 0xF8 0xFC ) group.long ($2+0x400)++0x3 line.long 0x0 "REGG1_DOM_$1,Assign domain for CKGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x40 0x41 0x42 0x43 0x44 0x45 0x46 0x47 0x48 0x49 0x4A 0x4B 0x4C 0x4D 0x4E 0x4F )(list 0x100 0x104 0x108 0x10C 0x110 0x114 0x118 0x11C 0x120 0x124 0x128 0x12C 0x130 0x134 0x138 0x13C ) group.long ($2+0x400)++0x3 line.long 0x0 "REGG1_DOM_$1,Assign domain for CKGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x50 0x51 0x52 0x53 0x54 0x55 0x56 0x57 0x58 0x59 0x5A 0x5B 0x5C 0x5D 0x5E 0x5F )(list 0x140 0x144 0x148 0x14C 0x150 0x154 0x158 0x15C 0x160 0x164 0x168 0x16C 0x170 0x174 0x178 0x17C ) group.long ($2+0x400)++0x3 line.long 0x0 "REGG1_DOM_$1,Assign domain for CKGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x60 0x61 0x62 0x63 0x64 0x65 0x66 0x67 0x68 0x69 0x6A 0x6B 0x6C 0x6D 0x6E 0x6F )(list 0x180 0x184 0x188 0x18C 0x190 0x194 0x198 0x19C 0x1A0 0x1A4 0x1A8 0x1AC 0x1B0 0x1B4 0x1B8 0x1BC ) group.long ($2+0x400)++0x3 line.long 0x0 "REGG1_DOM_$1,Assign domain for CKGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x70 0x71 0x72 0x73 0x74 0x75 0x76 0x77 0x78 0x79 0x7A 0x7B 0x7C 0x7D 0x7E 0x7F )(list 0x1C0 0x1C4 0x1C8 0x1CC 0x1D0 0x1D4 0x1D8 0x1DC 0x1E0 0x1E4 0x1E8 0x1EC 0x1F0 0x1F4 0x1F8 0x1FC ) group.long ($2+0x400)++0x3 line.long 0x0 "REGG1_DOM_$1,Assign domain for CKGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x80 0x81 0x82 0x83 0x84 0x85 0x86 0x87 0x88 0x89 0x8A 0x8B 0x8C 0x8D 0x8E 0x8F )(list 0x200 0x204 0x208 0x20C 0x210 0x214 0x218 0x21C 0x220 0x224 0x228 0x22C 0x230 0x234 0x238 0x23C ) group.long ($2+0x400)++0x3 line.long 0x0 "REGG1_DOM_$1,Assign domain for CKGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x90 0x91 0x92 0x93 0x94 0x95 0x96 0x97 0x98 0x99 0x9A 0x9B 0x9C 0x9D 0x9E 0x9F )(list 0x240 0x244 0x248 0x24C 0x250 0x254 0x258 0x25C 0x260 0x264 0x268 0x26C 0x270 0x274 0x278 0x27C ) group.long ($2+0x400)++0x3 line.long 0x0 "REGG1_DOM_$1,Assign domain for CKGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xA0 0xA1 0xA2 0xA3 0xA4 0xA5 0xA6 0xA7 0xA8 0xA9 0xAA 0xAB 0xAC 0xAD 0xAE 0xAF )(list 0x280 0x284 0x288 0x28C 0x290 0x294 0x298 0x29C 0x2A0 0x2A4 0x2A8 0x2AC 0x2B0 0x2B4 0x2B8 0x2BC ) group.long ($2+0x400)++0x3 line.long 0x0 "REGG1_DOM_$1,Assign domain for CKGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xB0 0xB1 0xB2 0xB3 0xB4 0xB5 0xB6 0xB7 0xB8 0xB9 0xBA 0xBB 0xBC 0xBD 0xBE 0xBF )(list 0x2C0 0x2C4 0x2C8 0x2CC 0x2D0 0x2D4 0x2D8 0x2DC 0x2E0 0x2E4 0x2E8 0x2EC 0x2F0 0x2F4 0x2F8 0x2FC ) group.long ($2+0x400)++0x3 line.long 0x0 "REGG1_DOM_$1,Assign domain for CKGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xC0 0xC1 0xC2 0xC3 0xC4 0xC5 0xC6 0xC7 0xC8 0xC9 0xCA 0xCB 0xCC 0xCD 0xCE 0xCF )(list 0x300 0x304 0x308 0x30C 0x310 0x314 0x318 0x31C 0x320 0x324 0x328 0x32C 0x330 0x334 0x338 0x33C ) group.long ($2+0x400)++0x3 line.long 0x0 "REGG1_DOM_$1,Assign domain for CKGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xD0 0xD1 0xD2 0xD3 0xD4 0xD5 0xD6 0xD7 0xD8 0xD9 0xDA 0xDB 0xDC 0xDD 0xDE 0xDF )(list 0x340 0x344 0x348 0x34C 0x350 0x354 0x358 0x35C 0x360 0x364 0x368 0x36C 0x370 0x374 0x378 0x37C ) group.long ($2+0x400)++0x3 line.long 0x0 "REGG1_DOM_$1,Assign domain for CKGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xE0 0xE1 0xE2 0xE3 0xE4 0xE5 0xE6 0xE7 0xE8 0xE9 0xEA 0xEB 0xEC 0xED 0xEE 0xEF )(list 0x380 0x384 0x388 0x38C 0x390 0x394 0x398 0x39C 0x3A0 0x3A4 0x3A8 0x3AC 0x3B0 0x3B4 0x3B8 0x3BC ) group.long ($2+0x400)++0x3 line.long 0x0 "REGG1_DOM_$1,Assign domain for CKGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xF0 0xF1 0xF2 0xF3 0xF4 0xF5 0xF6 0xF7 0xF8 0xF9 0xFA 0xFB 0xFC 0xFD 0xFE 0xFF )(list 0x3C0 0x3C4 0x3C8 0x3CC 0x3D0 0x3D4 0x3D8 0x3DC 0x3E0 0x3E4 0x3E8 0x3EC 0x3F0 0x3F4 0x3F8 0x3FC ) group.long ($2+0x400)++0x3 line.long 0x0 "REGG1_DOM_$1,Assign domain for CKGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x4 0x8 0xC 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C ) group.long ($2+0x800)++0x3 line.long 0x0 "REGG2_DOM_$1,Assign domain for SCR registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1A 0x1B 0x1C 0x1D 0x1E 0x1F )(list 0x40 0x44 0x48 0x4C 0x50 0x54 0x58 0x5C 0x60 0x64 0x68 0x6C 0x70 0x74 0x78 0x7C ) group.long ($2+0x800)++0x3 line.long 0x0 "REGG2_DOM_$1,Assign domain for SCR registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x20 0x21 0x22 0x23 0x24 0x25 0x26 0x27 0x28 0x29 0x2A 0x2B 0x2C 0x2D 0x2E 0x2F )(list 0x80 0x84 0x88 0x8C 0x90 0x94 0x98 0x9C 0xA0 0xA4 0xA8 0xAC 0xB0 0xB4 0xB8 0xBC ) group.long ($2+0x800)++0x3 line.long 0x0 "REGG2_DOM_$1,Assign domain for SCR registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x30 0x31 0x32 0x33 0x34 0x35 0x36 0x37 0x38 0x39 0x3A 0x3B 0x3C 0x3D 0x3E 0x3F )(list 0xC0 0xC4 0xC8 0xCC 0xD0 0xD4 0xD8 0xDC 0xE0 0xE4 0xE8 0xEC 0xF0 0xF4 0xF8 0xFC ) group.long ($2+0x800)++0x3 line.long 0x0 "REGG2_DOM_$1,Assign domain for SCR registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x40 0x41 0x42 0x43 0x44 0x45 0x46 0x47 0x48 0x49 0x4A 0x4B 0x4C 0x4D 0x4E 0x4F )(list 0x100 0x104 0x108 0x10C 0x110 0x114 0x118 0x11C 0x120 0x124 0x128 0x12C 0x130 0x134 0x138 0x13C ) group.long ($2+0x800)++0x3 line.long 0x0 "REGG2_DOM_$1,Assign domain for SCR registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x50 0x51 0x52 0x53 0x54 0x55 0x56 0x57 0x58 0x59 0x5A 0x5B 0x5C 0x5D 0x5E 0x5F )(list 0x140 0x144 0x148 0x14C 0x150 0x154 0x158 0x15C 0x160 0x164 0x168 0x16C 0x170 0x174 0x178 0x17C ) group.long ($2+0x800)++0x3 line.long 0x0 "REGG2_DOM_$1,Assign domain for SCR registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x60 0x61 0x62 0x63 0x64 0x65 0x66 0x67 0x68 0x69 0x6A 0x6B 0x6C 0x6D 0x6E 0x6F )(list 0x180 0x184 0x188 0x18C 0x190 0x194 0x198 0x19C 0x1A0 0x1A4 0x1A8 0x1AC 0x1B0 0x1B4 0x1B8 0x1BC ) group.long ($2+0x800)++0x3 line.long 0x0 "REGG2_DOM_$1,Assign domain for SCR registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x70 0x71 0x72 0x73 0x74 0x75 0x76 0x77 0x78 0x79 0x7A 0x7B 0x7C 0x7D 0x7E 0x7F )(list 0x1C0 0x1C4 0x1C8 0x1CC 0x1D0 0x1D4 0x1D8 0x1DC 0x1E0 0x1E4 0x1E8 0x1EC 0x1F0 0x1F4 0x1F8 0x1FC ) group.long ($2+0x800)++0x3 line.long 0x0 "REGG2_DOM_$1,Assign domain for SCR registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x80 0x81 0x82 0x83 0x84 0x85 0x86 0x87 0x88 0x89 0x8A 0x8B 0x8C 0x8D 0x8E 0x8F )(list 0x200 0x204 0x208 0x20C 0x210 0x214 0x218 0x21C 0x220 0x224 0x228 0x22C 0x230 0x234 0x238 0x23C ) group.long ($2+0x800)++0x3 line.long 0x0 "REGG2_DOM_$1,Assign domain for SCR registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x90 0x91 0x92 0x93 0x94 0x95 0x96 0x97 0x98 0x99 0x9A 0x9B 0x9C 0x9D 0x9E 0x9F )(list 0x240 0x244 0x248 0x24C 0x250 0x254 0x258 0x25C 0x260 0x264 0x268 0x26C 0x270 0x274 0x278 0x27C ) group.long ($2+0x800)++0x3 line.long 0x0 "REGG2_DOM_$1,Assign domain for SCR registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xA0 0xA1 0xA2 0xA3 0xA4 0xA5 0xA6 0xA7 0xA8 0xA9 0xAA 0xAB 0xAC 0xAD 0xAE 0xAF )(list 0x280 0x284 0x288 0x28C 0x290 0x294 0x298 0x29C 0x2A0 0x2A4 0x2A8 0x2AC 0x2B0 0x2B4 0x2B8 0x2BC ) group.long ($2+0x800)++0x3 line.long 0x0 "REGG2_DOM_$1,Assign domain for SCR registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xB0 0xB1 0xB2 0xB3 0xB4 0xB5 0xB6 0xB7 0xB8 0xB9 0xBA 0xBB 0xBC 0xBD 0xBE 0xBF )(list 0x2C0 0x2C4 0x2C8 0x2CC 0x2D0 0x2D4 0x2D8 0x2DC 0x2E0 0x2E4 0x2E8 0x2EC 0x2F0 0x2F4 0x2F8 0x2FC ) group.long ($2+0x800)++0x3 line.long 0x0 "REGG2_DOM_$1,Assign domain for SCR registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xC0 0xC1 0xC2 0xC3 0xC4 0xC5 0xC6 0xC7 0xC8 0xC9 0xCA 0xCB 0xCC 0xCD 0xCE 0xCF )(list 0x300 0x304 0x308 0x30C 0x310 0x314 0x318 0x31C 0x320 0x324 0x328 0x32C 0x330 0x334 0x338 0x33C ) group.long ($2+0x800)++0x3 line.long 0x0 "REGG2_DOM_$1,Assign domain for SCR registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xD0 0xD1 0xD2 0xD3 0xD4 0xD5 0xD6 0xD7 0xD8 0xD9 0xDA 0xDB 0xDC 0xDD 0xDE 0xDF )(list 0x340 0x344 0x348 0x34C 0x350 0x354 0x358 0x35C 0x360 0x364 0x368 0x36C 0x370 0x374 0x378 0x37C ) group.long ($2+0x800)++0x3 line.long 0x0 "REGG2_DOM_$1,Assign domain for SCR registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xE0 0xE1 0xE2 0xE3 0xE4 0xE5 0xE6 0xE7 0xE8 0xE9 0xEA 0xEB 0xEC 0xED 0xEE 0xEF )(list 0x380 0x384 0x388 0x38C 0x390 0x394 0x398 0x39C 0x3A0 0x3A4 0x3A8 0x3AC 0x3B0 0x3B4 0x3B8 0x3BC ) group.long ($2+0x800)++0x3 line.long 0x0 "REGG2_DOM_$1,Assign domain for SCR registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xF0 0xF1 0xF2 0xF3 0xF4 0xF5 0xF6 0xF7 0xF8 0xF9 0xFA 0xFB 0xFC 0xFD 0xFE 0xFF )(list 0x3C0 0x3C4 0x3C8 0x3CC 0x3D0 0x3D4 0x3D8 0x3DC 0x3E0 0x3E4 0x3E8 0x3EC 0x3F0 0x3F4 0x3F8 0x3FC ) group.long ($2+0x800)++0x3 line.long 0x0 "REGG2_DOM_$1,Assign domain for SCR registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x4 0x8 0xC 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C ) group.long ($2+0xC00)++0x3 line.long 0x0 "REGG3_DOM_$1,Assign domain for SCR registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1A 0x1B 0x1C 0x1D 0x1E 0x1F )(list 0x40 0x44 0x48 0x4C 0x50 0x54 0x58 0x5C 0x60 0x64 0x68 0x6C 0x70 0x74 0x78 0x7C ) group.long ($2+0xC00)++0x3 line.long 0x0 "REGG3_DOM_$1,Assign domain for SCR registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x20 0x21 0x22 0x23 0x24 0x25 0x26 0x27 0x28 0x29 0x2A 0x2B 0x2C 0x2D 0x2E 0x2F )(list 0x80 0x84 0x88 0x8C 0x90 0x94 0x98 0x9C 0xA0 0xA4 0xA8 0xAC 0xB0 0xB4 0xB8 0xBC ) group.long ($2+0xC00)++0x3 line.long 0x0 "REGG3_DOM_$1,Assign domain for SCR registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x30 0x31 0x32 0x33 0x34 0x35 0x36 0x37 0x38 0x39 0x3A 0x3B 0x3C 0x3D 0x3E 0x3F )(list 0xC0 0xC4 0xC8 0xCC 0xD0 0xD4 0xD8 0xDC 0xE0 0xE4 0xE8 0xEC 0xF0 0xF4 0xF8 0xFC ) group.long ($2+0xC00)++0x3 line.long 0x0 "REGG3_DOM_$1,Assign domain for SCR registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x40 0x41 0x42 0x43 0x44 0x45 0x46 0x47 0x48 0x49 0x4A 0x4B 0x4C 0x4D 0x4E 0x4F )(list 0x100 0x104 0x108 0x10C 0x110 0x114 0x118 0x11C 0x120 0x124 0x128 0x12C 0x130 0x134 0x138 0x13C ) group.long ($2+0xC00)++0x3 line.long 0x0 "REGG3_DOM_$1,Assign domain for SCR registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x50 0x51 0x52 0x53 0x54 0x55 0x56 0x57 0x58 0x59 0x5A 0x5B 0x5C 0x5D 0x5E 0x5F )(list 0x140 0x144 0x148 0x14C 0x150 0x154 0x158 0x15C 0x160 0x164 0x168 0x16C 0x170 0x174 0x178 0x17C ) group.long ($2+0xC00)++0x3 line.long 0x0 "REGG3_DOM_$1,Assign domain for SCR registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x60 0x61 0x62 0x63 0x64 0x65 0x66 0x67 0x68 0x69 0x6A 0x6B 0x6C 0x6D 0x6E 0x6F )(list 0x180 0x184 0x188 0x18C 0x190 0x194 0x198 0x19C 0x1A0 0x1A4 0x1A8 0x1AC 0x1B0 0x1B4 0x1B8 0x1BC ) group.long ($2+0xC00)++0x3 line.long 0x0 "REGG3_DOM_$1,Assign domain for SCR registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x70 0x71 0x72 0x73 0x74 0x75 0x76 0x77 0x78 0x79 0x7A 0x7B 0x7C 0x7D 0x7E 0x7F )(list 0x1C0 0x1C4 0x1C8 0x1CC 0x1D0 0x1D4 0x1D8 0x1DC 0x1E0 0x1E4 0x1E8 0x1EC 0x1F0 0x1F4 0x1F8 0x1FC ) group.long ($2+0xC00)++0x3 line.long 0x0 "REGG3_DOM_$1,Assign domain for SCR registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x80 0x81 0x82 0x83 0x84 0x85 0x86 0x87 0x88 0x89 0x8A 0x8B 0x8C 0x8D 0x8E 0x8F )(list 0x200 0x204 0x208 0x20C 0x210 0x214 0x218 0x21C 0x220 0x224 0x228 0x22C 0x230 0x234 0x238 0x23C ) group.long ($2+0xC00)++0x3 line.long 0x0 "REGG3_DOM_$1,Assign domain for SCR registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x90 0x91 0x92 0x93 0x94 0x95 0x96 0x97 0x98 0x99 0x9A 0x9B 0x9C 0x9D 0x9E 0x9F )(list 0x240 0x244 0x248 0x24C 0x250 0x254 0x258 0x25C 0x260 0x264 0x268 0x26C 0x270 0x274 0x278 0x27C ) group.long ($2+0xC00)++0x3 line.long 0x0 "REGG3_DOM_$1,Assign domain for SCR registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xA0 0xA1 0xA2 0xA3 0xA4 0xA5 0xA6 0xA7 0xA8 0xA9 0xAA 0xAB 0xAC 0xAD 0xAE 0xAF )(list 0x280 0x284 0x288 0x28C 0x290 0x294 0x298 0x29C 0x2A0 0x2A4 0x2A8 0x2AC 0x2B0 0x2B4 0x2B8 0x2BC ) group.long ($2+0xC00)++0x3 line.long 0x0 "REGG3_DOM_$1,Assign domain for SCR registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xB0 0xB1 0xB2 0xB3 0xB4 0xB5 0xB6 0xB7 0xB8 0xB9 0xBA 0xBB 0xBC 0xBD 0xBE 0xBF )(list 0x2C0 0x2C4 0x2C8 0x2CC 0x2D0 0x2D4 0x2D8 0x2DC 0x2E0 0x2E4 0x2E8 0x2EC 0x2F0 0x2F4 0x2F8 0x2FC ) group.long ($2+0xC00)++0x3 line.long 0x0 "REGG3_DOM_$1,Assign domain for SCR registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xC0 0xC1 0xC2 0xC3 0xC4 0xC5 0xC6 0xC7 0xC8 0xC9 0xCA 0xCB 0xCC 0xCD 0xCE 0xCF )(list 0x300 0x304 0x308 0x30C 0x310 0x314 0x318 0x31C 0x320 0x324 0x328 0x32C 0x330 0x334 0x338 0x33C ) group.long ($2+0xC00)++0x3 line.long 0x0 "REGG3_DOM_$1,Assign domain for SCR registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xD0 0xD1 0xD2 0xD3 0xD4 0xD5 0xD6 0xD7 0xD8 0xD9 0xDA 0xDB 0xDC 0xDD 0xDE 0xDF )(list 0x340 0x344 0x348 0x34C 0x350 0x354 0x358 0x35C 0x360 0x364 0x368 0x36C 0x370 0x374 0x378 0x37C ) group.long ($2+0xC00)++0x3 line.long 0x0 "REGG3_DOM_$1,Assign domain for SCR registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xE0 0xE1 0xE2 0xE3 0xE4 0xE5 0xE6 0xE7 0xE8 0xE9 0xEA 0xEB 0xEC 0xED 0xEE 0xEF )(list 0x380 0x384 0x388 0x38C 0x390 0x394 0x398 0x39C 0x3A0 0x3A4 0x3A8 0x3AC 0x3B0 0x3B4 0x3B8 0x3BC ) group.long ($2+0xC00)++0x3 line.long 0x0 "REGG3_DOM_$1,Assign domain for SCR registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xF0 0xF1 0xF2 0xF3 0xF4 0xF5 0xF6 0xF7 0xF8 0xF9 0xFA 0xFB 0xFC 0xFD 0xFE 0xFF )(list 0x3C0 0x3C4 0x3C8 0x3CC 0x3D0 0x3D4 0x3D8 0x3DC 0x3E0 0x3E4 0x3E8 0x3EC 0x3F0 0x3F4 0x3F8 0x3FC ) group.long ($2+0xC00)++0x3 line.long 0x0 "REGG3_DOM_$1,Assign domain for SCR registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x4 0x8 0xC 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C ) group.long ($2+0x1000)++0x3 line.long 0x0 "REGG4_DOM_$1,Assign domain for RSTGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1A 0x1B 0x1C 0x1D 0x1E 0x1F )(list 0x40 0x44 0x48 0x4C 0x50 0x54 0x58 0x5C 0x60 0x64 0x68 0x6C 0x70 0x74 0x78 0x7C ) group.long ($2+0x1000)++0x3 line.long 0x0 "REGG4_DOM_$1,Assign domain for RSTGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x20 0x21 0x22 0x23 0x24 0x25 0x26 0x27 0x28 0x29 0x2A 0x2B 0x2C 0x2D 0x2E 0x2F )(list 0x80 0x84 0x88 0x8C 0x90 0x94 0x98 0x9C 0xA0 0xA4 0xA8 0xAC 0xB0 0xB4 0xB8 0xBC ) group.long ($2+0x1000)++0x3 line.long 0x0 "REGG4_DOM_$1,Assign domain for RSTGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x30 0x31 0x32 0x33 0x34 0x35 0x36 0x37 0x38 0x39 0x3A 0x3B 0x3C 0x3D 0x3E 0x3F )(list 0xC0 0xC4 0xC8 0xCC 0xD0 0xD4 0xD8 0xDC 0xE0 0xE4 0xE8 0xEC 0xF0 0xF4 0xF8 0xFC ) group.long ($2+0x1000)++0x3 line.long 0x0 "REGG4_DOM_$1,Assign domain for RSTGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x40 0x41 0x42 0x43 0x44 0x45 0x46 0x47 0x48 0x49 0x4A 0x4B 0x4C 0x4D 0x4E 0x4F )(list 0x100 0x104 0x108 0x10C 0x110 0x114 0x118 0x11C 0x120 0x124 0x128 0x12C 0x130 0x134 0x138 0x13C ) group.long ($2+0x1000)++0x3 line.long 0x0 "REGG4_DOM_$1,Assign domain for RSTGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x50 0x51 0x52 0x53 0x54 0x55 0x56 0x57 0x58 0x59 0x5A 0x5B 0x5C 0x5D 0x5E 0x5F )(list 0x140 0x144 0x148 0x14C 0x150 0x154 0x158 0x15C 0x160 0x164 0x168 0x16C 0x170 0x174 0x178 0x17C ) group.long ($2+0x1000)++0x3 line.long 0x0 "REGG4_DOM_$1,Assign domain for RSTGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x60 0x61 0x62 0x63 0x64 0x65 0x66 0x67 0x68 0x69 0x6A 0x6B 0x6C 0x6D 0x6E 0x6F )(list 0x180 0x184 0x188 0x18C 0x190 0x194 0x198 0x19C 0x1A0 0x1A4 0x1A8 0x1AC 0x1B0 0x1B4 0x1B8 0x1BC ) group.long ($2+0x1000)++0x3 line.long 0x0 "REGG4_DOM_$1,Assign domain for RSTGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x70 0x71 0x72 0x73 0x74 0x75 0x76 0x77 0x78 0x79 0x7A 0x7B 0x7C 0x7D 0x7E 0x7F )(list 0x1C0 0x1C4 0x1C8 0x1CC 0x1D0 0x1D4 0x1D8 0x1DC 0x1E0 0x1E4 0x1E8 0x1EC 0x1F0 0x1F4 0x1F8 0x1FC ) group.long ($2+0x1000)++0x3 line.long 0x0 "REGG4_DOM_$1,Assign domain for RSTGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x80 0x81 0x82 0x83 0x84 0x85 0x86 0x87 0x88 0x89 0x8A 0x8B 0x8C 0x8D 0x8E 0x8F )(list 0x200 0x204 0x208 0x20C 0x210 0x214 0x218 0x21C 0x220 0x224 0x228 0x22C 0x230 0x234 0x238 0x23C ) group.long ($2+0x1000)++0x3 line.long 0x0 "REGG4_DOM_$1,Assign domain for RSTGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x90 0x91 0x92 0x93 0x94 0x95 0x96 0x97 0x98 0x99 0x9A 0x9B 0x9C 0x9D 0x9E 0x9F )(list 0x240 0x244 0x248 0x24C 0x250 0x254 0x258 0x25C 0x260 0x264 0x268 0x26C 0x270 0x274 0x278 0x27C ) group.long ($2+0x1000)++0x3 line.long 0x0 "REGG4_DOM_$1,Assign domain for RSTGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xA0 0xA1 0xA2 0xA3 0xA4 0xA5 0xA6 0xA7 0xA8 0xA9 0xAA 0xAB 0xAC 0xAD 0xAE 0xAF )(list 0x280 0x284 0x288 0x28C 0x290 0x294 0x298 0x29C 0x2A0 0x2A4 0x2A8 0x2AC 0x2B0 0x2B4 0x2B8 0x2BC ) group.long ($2+0x1000)++0x3 line.long 0x0 "REGG4_DOM_$1,Assign domain for RSTGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xB0 0xB1 0xB2 0xB3 0xB4 0xB5 0xB6 0xB7 0xB8 0xB9 0xBA 0xBB 0xBC 0xBD 0xBE 0xBF )(list 0x2C0 0x2C4 0x2C8 0x2CC 0x2D0 0x2D4 0x2D8 0x2DC 0x2E0 0x2E4 0x2E8 0x2EC 0x2F0 0x2F4 0x2F8 0x2FC ) group.long ($2+0x1000)++0x3 line.long 0x0 "REGG4_DOM_$1,Assign domain for RSTGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xC0 0xC1 0xC2 0xC3 0xC4 0xC5 0xC6 0xC7 0xC8 0xC9 0xCA 0xCB 0xCC 0xCD 0xCE 0xCF )(list 0x300 0x304 0x308 0x30C 0x310 0x314 0x318 0x31C 0x320 0x324 0x328 0x32C 0x330 0x334 0x338 0x33C ) group.long ($2+0x1000)++0x3 line.long 0x0 "REGG4_DOM_$1,Assign domain for RSTGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xD0 0xD1 0xD2 0xD3 0xD4 0xD5 0xD6 0xD7 0xD8 0xD9 0xDA 0xDB 0xDC 0xDD 0xDE 0xDF )(list 0x340 0x344 0x348 0x34C 0x350 0x354 0x358 0x35C 0x360 0x364 0x368 0x36C 0x370 0x374 0x378 0x37C ) group.long ($2+0x1000)++0x3 line.long 0x0 "REGG4_DOM_$1,Assign domain for RSTGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xE0 0xE1 0xE2 0xE3 0xE4 0xE5 0xE6 0xE7 0xE8 0xE9 0xEA 0xEB 0xEC 0xED 0xEE 0xEF )(list 0x380 0x384 0x388 0x38C 0x390 0x394 0x398 0x39C 0x3A0 0x3A4 0x3A8 0x3AC 0x3B0 0x3B4 0x3B8 0x3BC ) group.long ($2+0x1000)++0x3 line.long 0x0 "REGG4_DOM_$1,Assign domain for RSTGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xF0 0xF1 0xF2 0xF3 0xF4 0xF5 0xF6 0xF7 0xF8 0xF9 0xFA 0xFB 0xFC 0xFD 0xFE 0xFF )(list 0x3C0 0x3C4 0x3C8 0x3CC 0x3D0 0x3D4 0x3D8 0x3DC 0x3E0 0x3E4 0x3E8 0x3EC 0x3F0 0x3F4 0x3F8 0x3FC ) group.long ($2+0x1000)++0x3 line.long 0x0 "REGG4_DOM_$1,Assign domain for RSTGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x4 0x8 0xC 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C ) group.long ($2+0x1400)++0x3 line.long 0x0 "REGG5_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1A 0x1B 0x1C 0x1D 0x1E 0x1F )(list 0x40 0x44 0x48 0x4C 0x50 0x54 0x58 0x5C 0x60 0x64 0x68 0x6C 0x70 0x74 0x78 0x7C ) group.long ($2+0x1400)++0x3 line.long 0x0 "REGG5_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x20 0x21 0x22 0x23 0x24 0x25 0x26 0x27 0x28 0x29 0x2A 0x2B 0x2C 0x2D 0x2E 0x2F )(list 0x80 0x84 0x88 0x8C 0x90 0x94 0x98 0x9C 0xA0 0xA4 0xA8 0xAC 0xB0 0xB4 0xB8 0xBC ) group.long ($2+0x1400)++0x3 line.long 0x0 "REGG5_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x30 0x31 0x32 0x33 0x34 0x35 0x36 0x37 0x38 0x39 0x3A 0x3B 0x3C 0x3D 0x3E 0x3F )(list 0xC0 0xC4 0xC8 0xCC 0xD0 0xD4 0xD8 0xDC 0xE0 0xE4 0xE8 0xEC 0xF0 0xF4 0xF8 0xFC ) group.long ($2+0x1400)++0x3 line.long 0x0 "REGG5_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x40 0x41 0x42 0x43 0x44 0x45 0x46 0x47 0x48 0x49 0x4A 0x4B 0x4C 0x4D 0x4E 0x4F )(list 0x100 0x104 0x108 0x10C 0x110 0x114 0x118 0x11C 0x120 0x124 0x128 0x12C 0x130 0x134 0x138 0x13C ) group.long ($2+0x1400)++0x3 line.long 0x0 "REGG5_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x50 0x51 0x52 0x53 0x54 0x55 0x56 0x57 0x58 0x59 0x5A 0x5B 0x5C 0x5D 0x5E 0x5F )(list 0x140 0x144 0x148 0x14C 0x150 0x154 0x158 0x15C 0x160 0x164 0x168 0x16C 0x170 0x174 0x178 0x17C ) group.long ($2+0x1400)++0x3 line.long 0x0 "REGG5_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x60 0x61 0x62 0x63 0x64 0x65 0x66 0x67 0x68 0x69 0x6A 0x6B 0x6C 0x6D 0x6E 0x6F )(list 0x180 0x184 0x188 0x18C 0x190 0x194 0x198 0x19C 0x1A0 0x1A4 0x1A8 0x1AC 0x1B0 0x1B4 0x1B8 0x1BC ) group.long ($2+0x1400)++0x3 line.long 0x0 "REGG5_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x70 0x71 0x72 0x73 0x74 0x75 0x76 0x77 0x78 0x79 0x7A 0x7B 0x7C 0x7D 0x7E 0x7F )(list 0x1C0 0x1C4 0x1C8 0x1CC 0x1D0 0x1D4 0x1D8 0x1DC 0x1E0 0x1E4 0x1E8 0x1EC 0x1F0 0x1F4 0x1F8 0x1FC ) group.long ($2+0x1400)++0x3 line.long 0x0 "REGG5_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x80 0x81 0x82 0x83 0x84 0x85 0x86 0x87 0x88 0x89 0x8A 0x8B 0x8C 0x8D 0x8E 0x8F )(list 0x200 0x204 0x208 0x20C 0x210 0x214 0x218 0x21C 0x220 0x224 0x228 0x22C 0x230 0x234 0x238 0x23C ) group.long ($2+0x1400)++0x3 line.long 0x0 "REGG5_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x90 0x91 0x92 0x93 0x94 0x95 0x96 0x97 0x98 0x99 0x9A 0x9B 0x9C 0x9D 0x9E 0x9F )(list 0x240 0x244 0x248 0x24C 0x250 0x254 0x258 0x25C 0x260 0x264 0x268 0x26C 0x270 0x274 0x278 0x27C ) group.long ($2+0x1400)++0x3 line.long 0x0 "REGG5_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xA0 0xA1 0xA2 0xA3 0xA4 0xA5 0xA6 0xA7 0xA8 0xA9 0xAA 0xAB 0xAC 0xAD 0xAE 0xAF )(list 0x280 0x284 0x288 0x28C 0x290 0x294 0x298 0x29C 0x2A0 0x2A4 0x2A8 0x2AC 0x2B0 0x2B4 0x2B8 0x2BC ) group.long ($2+0x1400)++0x3 line.long 0x0 "REGG5_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xB0 0xB1 0xB2 0xB3 0xB4 0xB5 0xB6 0xB7 0xB8 0xB9 0xBA 0xBB 0xBC 0xBD 0xBE 0xBF )(list 0x2C0 0x2C4 0x2C8 0x2CC 0x2D0 0x2D4 0x2D8 0x2DC 0x2E0 0x2E4 0x2E8 0x2EC 0x2F0 0x2F4 0x2F8 0x2FC ) group.long ($2+0x1400)++0x3 line.long 0x0 "REGG5_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xC0 0xC1 0xC2 0xC3 0xC4 0xC5 0xC6 0xC7 0xC8 0xC9 0xCA 0xCB 0xCC 0xCD 0xCE 0xCF )(list 0x300 0x304 0x308 0x30C 0x310 0x314 0x318 0x31C 0x320 0x324 0x328 0x32C 0x330 0x334 0x338 0x33C ) group.long ($2+0x1400)++0x3 line.long 0x0 "REGG5_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xD0 0xD1 0xD2 0xD3 0xD4 0xD5 0xD6 0xD7 0xD8 0xD9 0xDA 0xDB 0xDC 0xDD 0xDE 0xDF )(list 0x340 0x344 0x348 0x34C 0x350 0x354 0x358 0x35C 0x360 0x364 0x368 0x36C 0x370 0x374 0x378 0x37C ) group.long ($2+0x1400)++0x3 line.long 0x0 "REGG5_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xE0 0xE1 0xE2 0xE3 0xE4 0xE5 0xE6 0xE7 0xE8 0xE9 0xEA 0xEB 0xEC 0xED 0xEE 0xEF )(list 0x380 0x384 0x388 0x38C 0x390 0x394 0x398 0x39C 0x3A0 0x3A4 0x3A8 0x3AC 0x3B0 0x3B4 0x3B8 0x3BC ) group.long ($2+0x1400)++0x3 line.long 0x0 "REGG5_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xF0 0xF1 0xF2 0xF3 0xF4 0xF5 0xF6 0xF7 0xF8 0xF9 0xFA 0xFB 0xFC 0xFD 0xFE 0xFF )(list 0x3C0 0x3C4 0x3C8 0x3CC 0x3D0 0x3D4 0x3D8 0x3DC 0x3E0 0x3E4 0x3E8 0x3EC 0x3F0 0x3F4 0x3F8 0x3FC ) group.long ($2+0x1400)++0x3 line.long 0x0 "REGG5_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x4 0x8 0xC 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C ) group.long ($2+0x1800)++0x3 line.long 0x0 "REGG6_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1A 0x1B 0x1C 0x1D 0x1E 0x1F )(list 0x40 0x44 0x48 0x4C 0x50 0x54 0x58 0x5C 0x60 0x64 0x68 0x6C 0x70 0x74 0x78 0x7C ) group.long ($2+0x1800)++0x3 line.long 0x0 "REGG6_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x20 0x21 0x22 0x23 0x24 0x25 0x26 0x27 0x28 0x29 0x2A 0x2B 0x2C 0x2D 0x2E 0x2F )(list 0x80 0x84 0x88 0x8C 0x90 0x94 0x98 0x9C 0xA0 0xA4 0xA8 0xAC 0xB0 0xB4 0xB8 0xBC ) group.long ($2+0x1800)++0x3 line.long 0x0 "REGG6_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x30 0x31 0x32 0x33 0x34 0x35 0x36 0x37 0x38 0x39 0x3A 0x3B 0x3C 0x3D 0x3E 0x3F )(list 0xC0 0xC4 0xC8 0xCC 0xD0 0xD4 0xD8 0xDC 0xE0 0xE4 0xE8 0xEC 0xF0 0xF4 0xF8 0xFC ) group.long ($2+0x1800)++0x3 line.long 0x0 "REGG6_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x40 0x41 0x42 0x43 0x44 0x45 0x46 0x47 0x48 0x49 0x4A 0x4B 0x4C 0x4D 0x4E 0x4F )(list 0x100 0x104 0x108 0x10C 0x110 0x114 0x118 0x11C 0x120 0x124 0x128 0x12C 0x130 0x134 0x138 0x13C ) group.long ($2+0x1800)++0x3 line.long 0x0 "REGG6_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x50 0x51 0x52 0x53 0x54 0x55 0x56 0x57 0x58 0x59 0x5A 0x5B 0x5C 0x5D 0x5E 0x5F )(list 0x140 0x144 0x148 0x14C 0x150 0x154 0x158 0x15C 0x160 0x164 0x168 0x16C 0x170 0x174 0x178 0x17C ) group.long ($2+0x1800)++0x3 line.long 0x0 "REGG6_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x60 0x61 0x62 0x63 0x64 0x65 0x66 0x67 0x68 0x69 0x6A 0x6B 0x6C 0x6D 0x6E 0x6F )(list 0x180 0x184 0x188 0x18C 0x190 0x194 0x198 0x19C 0x1A0 0x1A4 0x1A8 0x1AC 0x1B0 0x1B4 0x1B8 0x1BC ) group.long ($2+0x1800)++0x3 line.long 0x0 "REGG6_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x70 0x71 0x72 0x73 0x74 0x75 0x76 0x77 0x78 0x79 0x7A 0x7B 0x7C 0x7D 0x7E 0x7F )(list 0x1C0 0x1C4 0x1C8 0x1CC 0x1D0 0x1D4 0x1D8 0x1DC 0x1E0 0x1E4 0x1E8 0x1EC 0x1F0 0x1F4 0x1F8 0x1FC ) group.long ($2+0x1800)++0x3 line.long 0x0 "REGG6_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x80 0x81 0x82 0x83 0x84 0x85 0x86 0x87 0x88 0x89 0x8A 0x8B 0x8C 0x8D 0x8E 0x8F )(list 0x200 0x204 0x208 0x20C 0x210 0x214 0x218 0x21C 0x220 0x224 0x228 0x22C 0x230 0x234 0x238 0x23C ) group.long ($2+0x1800)++0x3 line.long 0x0 "REGG6_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x90 0x91 0x92 0x93 0x94 0x95 0x96 0x97 0x98 0x99 0x9A 0x9B 0x9C 0x9D 0x9E 0x9F )(list 0x240 0x244 0x248 0x24C 0x250 0x254 0x258 0x25C 0x260 0x264 0x268 0x26C 0x270 0x274 0x278 0x27C ) group.long ($2+0x1800)++0x3 line.long 0x0 "REGG6_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xA0 0xA1 0xA2 0xA3 0xA4 0xA5 0xA6 0xA7 0xA8 0xA9 0xAA 0xAB 0xAC 0xAD 0xAE 0xAF )(list 0x280 0x284 0x288 0x28C 0x290 0x294 0x298 0x29C 0x2A0 0x2A4 0x2A8 0x2AC 0x2B0 0x2B4 0x2B8 0x2BC ) group.long ($2+0x1800)++0x3 line.long 0x0 "REGG6_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xB0 0xB1 0xB2 0xB3 0xB4 0xB5 0xB6 0xB7 0xB8 0xB9 0xBA 0xBB 0xBC 0xBD 0xBE 0xBF )(list 0x2C0 0x2C4 0x2C8 0x2CC 0x2D0 0x2D4 0x2D8 0x2DC 0x2E0 0x2E4 0x2E8 0x2EC 0x2F0 0x2F4 0x2F8 0x2FC ) group.long ($2+0x1800)++0x3 line.long 0x0 "REGG6_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xC0 0xC1 0xC2 0xC3 0xC4 0xC5 0xC6 0xC7 0xC8 0xC9 0xCA 0xCB 0xCC 0xCD 0xCE 0xCF )(list 0x300 0x304 0x308 0x30C 0x310 0x314 0x318 0x31C 0x320 0x324 0x328 0x32C 0x330 0x334 0x338 0x33C ) group.long ($2+0x1800)++0x3 line.long 0x0 "REGG6_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xD0 0xD1 0xD2 0xD3 0xD4 0xD5 0xD6 0xD7 0xD8 0xD9 0xDA 0xDB 0xDC 0xDD 0xDE 0xDF )(list 0x340 0x344 0x348 0x34C 0x350 0x354 0x358 0x35C 0x360 0x364 0x368 0x36C 0x370 0x374 0x378 0x37C ) group.long ($2+0x1800)++0x3 line.long 0x0 "REGG6_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xE0 0xE1 0xE2 0xE3 0xE4 0xE5 0xE6 0xE7 0xE8 0xE9 0xEA 0xEB 0xEC 0xED 0xEE 0xEF )(list 0x380 0x384 0x388 0x38C 0x390 0x394 0x398 0x39C 0x3A0 0x3A4 0x3A8 0x3AC 0x3B0 0x3B4 0x3B8 0x3BC ) group.long ($2+0x1800)++0x3 line.long 0x0 "REGG6_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xF0 0xF1 0xF2 0xF3 0xF4 0xF5 0xF6 0xF7 0xF8 0xF9 0xFA 0xFB 0xFC 0xFD 0xFE 0xFF )(list 0x3C0 0x3C4 0x3C8 0x3CC 0x3D0 0x3D4 0x3D8 0x3DC 0x3E0 0x3E4 0x3E8 0x3EC 0x3F0 0x3F4 0x3F8 0x3FC ) group.long ($2+0x1800)++0x3 line.long 0x0 "REGG6_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x4 0x8 0xC 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C ) group.long ($2+0x1C00)++0x3 line.long 0x0 "REGG7_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1A 0x1B 0x1C 0x1D 0x1E 0x1F )(list 0x40 0x44 0x48 0x4C 0x50 0x54 0x58 0x5C 0x60 0x64 0x68 0x6C 0x70 0x74 0x78 0x7C ) group.long ($2+0x1C00)++0x3 line.long 0x0 "REGG7_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x20 0x21 0x22 0x23 0x24 0x25 0x26 0x27 0x28 0x29 0x2A 0x2B 0x2C 0x2D 0x2E 0x2F )(list 0x80 0x84 0x88 0x8C 0x90 0x94 0x98 0x9C 0xA0 0xA4 0xA8 0xAC 0xB0 0xB4 0xB8 0xBC ) group.long ($2+0x1C00)++0x3 line.long 0x0 "REGG7_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x30 0x31 0x32 0x33 0x34 0x35 0x36 0x37 0x38 0x39 0x3A 0x3B 0x3C 0x3D 0x3E 0x3F )(list 0xC0 0xC4 0xC8 0xCC 0xD0 0xD4 0xD8 0xDC 0xE0 0xE4 0xE8 0xEC 0xF0 0xF4 0xF8 0xFC ) group.long ($2+0x1C00)++0x3 line.long 0x0 "REGG7_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x40 0x41 0x42 0x43 0x44 0x45 0x46 0x47 0x48 0x49 0x4A 0x4B 0x4C 0x4D 0x4E 0x4F )(list 0x100 0x104 0x108 0x10C 0x110 0x114 0x118 0x11C 0x120 0x124 0x128 0x12C 0x130 0x134 0x138 0x13C ) group.long ($2+0x1C00)++0x3 line.long 0x0 "REGG7_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x50 0x51 0x52 0x53 0x54 0x55 0x56 0x57 0x58 0x59 0x5A 0x5B 0x5C 0x5D 0x5E 0x5F )(list 0x140 0x144 0x148 0x14C 0x150 0x154 0x158 0x15C 0x160 0x164 0x168 0x16C 0x170 0x174 0x178 0x17C ) group.long ($2+0x1C00)++0x3 line.long 0x0 "REGG7_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x60 0x61 0x62 0x63 0x64 0x65 0x66 0x67 0x68 0x69 0x6A 0x6B 0x6C 0x6D 0x6E 0x6F )(list 0x180 0x184 0x188 0x18C 0x190 0x194 0x198 0x19C 0x1A0 0x1A4 0x1A8 0x1AC 0x1B0 0x1B4 0x1B8 0x1BC ) group.long ($2+0x1C00)++0x3 line.long 0x0 "REGG7_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x70 0x71 0x72 0x73 0x74 0x75 0x76 0x77 0x78 0x79 0x7A 0x7B 0x7C 0x7D 0x7E 0x7F )(list 0x1C0 0x1C4 0x1C8 0x1CC 0x1D0 0x1D4 0x1D8 0x1DC 0x1E0 0x1E4 0x1E8 0x1EC 0x1F0 0x1F4 0x1F8 0x1FC ) group.long ($2+0x1C00)++0x3 line.long 0x0 "REGG7_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x80 0x81 0x82 0x83 0x84 0x85 0x86 0x87 0x88 0x89 0x8A 0x8B 0x8C 0x8D 0x8E 0x8F )(list 0x200 0x204 0x208 0x20C 0x210 0x214 0x218 0x21C 0x220 0x224 0x228 0x22C 0x230 0x234 0x238 0x23C ) group.long ($2+0x1C00)++0x3 line.long 0x0 "REGG7_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x90 0x91 0x92 0x93 0x94 0x95 0x96 0x97 0x98 0x99 0x9A 0x9B 0x9C 0x9D 0x9E 0x9F )(list 0x240 0x244 0x248 0x24C 0x250 0x254 0x258 0x25C 0x260 0x264 0x268 0x26C 0x270 0x274 0x278 0x27C ) group.long ($2+0x1C00)++0x3 line.long 0x0 "REGG7_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xA0 0xA1 0xA2 0xA3 0xA4 0xA5 0xA6 0xA7 0xA8 0xA9 0xAA 0xAB 0xAC 0xAD 0xAE 0xAF )(list 0x280 0x284 0x288 0x28C 0x290 0x294 0x298 0x29C 0x2A0 0x2A4 0x2A8 0x2AC 0x2B0 0x2B4 0x2B8 0x2BC ) group.long ($2+0x1C00)++0x3 line.long 0x0 "REGG7_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xB0 0xB1 0xB2 0xB3 0xB4 0xB5 0xB6 0xB7 0xB8 0xB9 0xBA 0xBB 0xBC 0xBD 0xBE 0xBF )(list 0x2C0 0x2C4 0x2C8 0x2CC 0x2D0 0x2D4 0x2D8 0x2DC 0x2E0 0x2E4 0x2E8 0x2EC 0x2F0 0x2F4 0x2F8 0x2FC ) group.long ($2+0x1C00)++0x3 line.long 0x0 "REGG7_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xC0 0xC1 0xC2 0xC3 0xC4 0xC5 0xC6 0xC7 0xC8 0xC9 0xCA 0xCB 0xCC 0xCD 0xCE 0xCF )(list 0x300 0x304 0x308 0x30C 0x310 0x314 0x318 0x31C 0x320 0x324 0x328 0x32C 0x330 0x334 0x338 0x33C ) group.long ($2+0x1C00)++0x3 line.long 0x0 "REGG7_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xD0 0xD1 0xD2 0xD3 0xD4 0xD5 0xD6 0xD7 0xD8 0xD9 0xDA 0xDB 0xDC 0xDD 0xDE 0xDF )(list 0x340 0x344 0x348 0x34C 0x350 0x354 0x358 0x35C 0x360 0x364 0x368 0x36C 0x370 0x374 0x378 0x37C ) group.long ($2+0x1C00)++0x3 line.long 0x0 "REGG7_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xE0 0xE1 0xE2 0xE3 0xE4 0xE5 0xE6 0xE7 0xE8 0xE9 0xEA 0xEB 0xEC 0xED 0xEE 0xEF )(list 0x380 0x384 0x388 0x38C 0x390 0x394 0x398 0x39C 0x3A0 0x3A4 0x3A8 0x3AC 0x3B0 0x3B4 0x3B8 0x3BC ) group.long ($2+0x1C00)++0x3 line.long 0x0 "REGG7_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xF0 0xF1 0xF2 0xF3 0xF4 0xF5 0xF6 0xF7 0xF8 0xF9 0xFA 0xFB 0xFC 0xFD 0xFE 0xFF )(list 0x3C0 0x3C4 0x3C8 0x3CC 0x3D0 0x3D4 0x3D8 0x3DC 0x3E0 0x3E4 0x3E8 0x3EC 0x3F0 0x3F4 0x3F8 0x3FC ) group.long ($2+0x1C00)++0x3 line.long 0x0 "REGG7_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end group.long 0x2000++0x17 line.long 0x0 "GLB_CTL,This register provides global enable settings for permission control." bitfld.long 0x0 5. "DOM_CFG_LOCK,Lock write for DOM_CFG_MODE bit." "0,1" bitfld.long 0x0 4. "DOM_CFG_MODE,When enabled all the source setting can be configured by master from domain 0 if it is not locked. When disabled only resource manager can configure the permission of the resource." "0,1" bitfld.long 0x0 3. "PERCK_DIS_LOCK,Lock write for PERCK_DIS" "0,1" bitfld.long 0x0 2. "PERCK_DIS,All the permission check disable." "0,1" newline bitfld.long 0x0 1. "DOM_PRO_LOCK,Lock write for DOM_PRO_EN bit." "0,1" bitfld.long 0x0 0. "DOM_PRO_EN,When disabled no domain access permission check" "0,1" line.long 0x4 "RES_MGR,Resource manager register. This regster is used to assign resource manager for global resource access control" bitfld.long 0x4 17. "MID_LOCK,Lock write for MID_EN and MID_LOW and MID_HIG registers." "0,1" bitfld.long 0x4 16. "MID_EN,Master ID check enable" "0,1" bitfld.long 0x4 15. "PRI_PER_LOCK,Lock write for PRI_PER and PRI_PER_EN" "0,1" bitfld.long 0x4 13.--14. "PRI_PER,Resource manager privileged access permission. bit0 for privileged access bit1 for user access" "0,1,2,3" newline bitfld.long 0x4 12. "PRI_PER_EN,Resource manager privileged access permission enable." "0,1" bitfld.long 0x4 11. "SEC_PER_LOCK,Lock for SEC_PER and SEC_PER_LOCK" "0,1" bitfld.long 0x4 9.--10. "SEC_PER,Resource manager secure access permission. bit 0 for secure access bit 1 for non-secure access" "0,1,2,3" bitfld.long 0x4 8. "SEC_PER_EN,Resource manager secure permission enable" "0,1" bitfld.long 0x4 7. "DID_LOCK,Lock write for DID_EN and DID" "0,1" newline hexmask.long.byte 0x4 3.--6. 1. "DID,Resource manager domain ID" bitfld.long 0x4 2. "DID_EN,Resource manager Domain ID enable" "0,1" bitfld.long 0x4 1. "RES_MGR_EN_LOCK,Lock for RES_MGR_EN" "0,1" bitfld.long 0x4 0. "RES_MGR_EN,Resource manager enable. When the bit is disable there is no resource manager." "0,1" line.long 0x8 "RES_MGR_MA0,This register is used to assign master 0~31 as resource manager." hexmask.long 0x8 0.--31. 1. "MID,Assign master 0~31 for resource manager" line.long 0xC "RES_MGR_MA1,This register is used to assign master 32~63 as resource manager." hexmask.long 0xC 0.--31. 1. "MID,Indicate if master 32~63 is resource manager." line.long 0x10 "RES_MGR_MA2,This register is used to assign master 64~95 as resource manager." hexmask.long 0x10 0.--31. 1. "MID,Indicate if master 64~95 is resource manager." line.long 0x14 "RES_MGR_MA3,This register is used to assign master 96~127 as resource manager." hexmask.long 0x14 0.--31. 1. "MID,Indicate if master 96~127 is resource manager." repeat 8. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 )(list 0x0 0x14 0x28 0x3C 0x50 0x64 0x78 0x8C ) group.long ($2+0x2100)++0x3 line.long 0x0 "GRP_MGR_$1,Group Manager Register. This register is used to assign group manager for each domain" bitfld.long 0x0 17. "MID_LOCK,Lock write for MID_EN and MID_LOW and MID_HIG registers." "0,1" bitfld.long 0x0 16. "MID_EN,Master ID check enable" "0,1" bitfld.long 0x0 15. "PRI_PER_LOCK,Lock write for PRI_PER and PRI_PER_EN" "0,1" bitfld.long 0x0 13.--14. "PRI_PER,Group manager privileged access permission. bit0 for privileged access bit1 for user access" "0,1,2,3" newline bitfld.long 0x0 12. "PRI_PER_EN,Group manager privileged access permission enable." "0,1" bitfld.long 0x0 11. "SEC_PER_LOCK,Lock for SEC_PER and SEC_PER_LOCK" "0,1" bitfld.long 0x0 9.--10. "SEC_PER,Group manager secure access permission. bit 0 for secure access bit 1 for non-secure access" "0,1,2,3" bitfld.long 0x0 8. "SEC_PER_EN,Group manager secure permission enable" "0,1" bitfld.long 0x0 7. "DID_LOCK,Lock write for DID_EN and DID" "0,1" newline hexmask.long.byte 0x0 3.--6. 1. "DID,Group manager domain ID" bitfld.long 0x0 2. "DID_EN,Group manager Domain ID enable" "0,1" bitfld.long 0x0 1. "GRP_MGR_EN_LOCK,Lock write for GPR_MGR_EN" "0,1" bitfld.long 0x0 0. "GRP_MGR_EN,Group manager enable. When the bit is disable there is no resource manager." "0,1" repeat.end repeat 8. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 )(list 0x0 0x14 0x28 0x3C 0x50 0x64 0x78 0x8C ) group.long ($2+0x2104)++0x3 line.long 0x0 "GRP_MGR_MA0_$1,Assign master 0~31 for group manager 0" hexmask.long 0x0 0.--31. 1. "MID,Assign master 0~31 for resource manager" repeat.end repeat 8. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 )(list 0x0 0x14 0x28 0x3C 0x50 0x64 0x78 0x8C ) group.long ($2+0x2108)++0x3 line.long 0x0 "GRP_MGR_MA1_$1,Assign master 32~63 for group manager 0" hexmask.long 0x0 0.--31. 1. "MID,Indicate if master 32~63 is resource manager." repeat.end repeat 8. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 )(list 0x0 0x14 0x28 0x3C 0x50 0x64 0x78 0x8C ) group.long ($2+0x210C)++0x3 line.long 0x0 "GRP_MGR_MA2_$1,Assign master 64~95 for group manager 0" hexmask.long 0x0 0.--31. 1. "MID,Indicate if master 64~95 is resource manager." repeat.end repeat 8. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 )(list 0x0 0x14 0x28 0x3C 0x50 0x64 0x78 0x8C ) group.long ($2+0x2110)++0x3 line.long 0x0 "GRP_MGR_MA3_$1,Assign master 96~127 for group manager 0" hexmask.long 0x0 0.--31. 1. "MID,Indicate if master 96~127 is resource manager." repeat.end group.long 0x2200++0x3 line.long 0x0 "DOM_GID_0,Indicate which group domain 0 belong to" bitfld.long 0x0 3. "LOCK,Lock write for GID" "0,1" bitfld.long 0x0 0.--2. "GID,Group ID" "0,1,2,3,4,5,6,7" repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x18 0x30 0x48 0x60 0x78 0x90 0xA8 0xC0 0xD8 0xF0 0x108 0x120 0x138 0x150 0x168 ) group.long ($2+0x2204)++0x3 line.long 0x0 "DOM_OWN_$1,Assign owner for function domain 0." bitfld.long 0x0 17. "MID_LOCK,Lock write for MID_EN and MID_LOW and MID_HIG registers." "0,1" bitfld.long 0x0 16. "MID_EN,Master ID check enable" "0,1" bitfld.long 0x0 15. "PRI_PER_LOCK,Lock write for PRI_PER and PRI_PER_EN" "0,1" bitfld.long 0x0 13.--14. "PRI_PER,Group manager privileged access permission. bit0 for privileged access bit1 for user access" "0,1,2,3" newline bitfld.long 0x0 12. "PRI_PER_EN,Group manager privileged access permission enable." "0,1" bitfld.long 0x0 11. "SEC_PER_LOCK,Lock for SEC_PER and SEC_PER_LOCK" "0,1" bitfld.long 0x0 9.--10. "SEC_PER,Domain owner secure access permission. bit 0 for secure access bit 1 for non-secure access" "0,1,2,3" bitfld.long 0x0 8. "SEC_PER_EN,Domain owner secure permission enable" "0,1" newline bitfld.long 0x0 1. "DOM_OWN_EN_LOCK,Lock for DOM_OWN_EN" "0,1" bitfld.long 0x0 0. "DOM_OWN_EN,Domain owner enable. When the bit is disable there is no domain owner." "0,1" repeat.end repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x18 0x30 0x48 0x60 0x78 0x90 0xA8 0xC0 0xD8 0xF0 0x108 0x120 0x138 0x150 0x168 ) group.long ($2+0x2208)++0x3 line.long 0x0 "DOM_OWN_MA0_$1,Assign master 0~31 for domain owner 0" hexmask.long 0x0 0.--31. 1. "MID,Assign master 0~31 for resource manager" repeat.end repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x18 0x30 0x48 0x60 0x78 0x90 0xA8 0xC0 0xD8 0xF0 0x108 0x120 0x138 0x150 0x168 ) group.long ($2+0x220C)++0x3 line.long 0x0 "DOM_OWN_MA1_$1,Assign master 32~63 for domain owner 0" hexmask.long 0x0 0.--31. 1. "MID,Indicate if master 32~63 is resource manager." repeat.end repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x18 0x30 0x48 0x60 0x78 0x90 0xA8 0xC0 0xD8 0xF0 0x108 0x120 0x138 0x150 0x168 ) group.long ($2+0x2210)++0x3 line.long 0x0 "DOM_OWN_MA2_$1,Assign master 64~95 for domain owner 0" hexmask.long 0x0 0.--31. 1. "MID,Indicate if master 64~95 is resource manager." repeat.end repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x18 0x30 0x48 0x60 0x78 0x90 0xA8 0xC0 0xD8 0xF0 0x108 0x120 0x138 0x150 0x168 ) group.long ($2+0x2214)++0x3 line.long 0x0 "DOM_OWN_MA3_$1,Assign master 96~127 for domain owner 0" hexmask.long 0x0 0.--31. 1. "MID,Indicate if master 96~127 is resource manager." repeat.end group.long 0x2218++0x3 line.long 0x0 "DOM_GID_1,Indicate which group domain 1 belong to" bitfld.long 0x0 3. "LOCK,Lock write for GID" "0,1" bitfld.long 0x0 0.--2. "GID,Group ID" "0,1,2,3,4,5,6,7" group.long 0x2230++0x3 line.long 0x0 "DOM_GID_2,Indicate which group domain 2 belong to" bitfld.long 0x0 3. "LOCK,Lock write for GID" "0,1" bitfld.long 0x0 0.--2. "GID,Group ID" "0,1,2,3,4,5,6,7" group.long 0x2248++0x3 line.long 0x0 "DOM_GID_3,Indicate which group domain 3 belong to" bitfld.long 0x0 3. "LOCK,Lock write for GID" "0,1" bitfld.long 0x0 0.--2. "GID,Group ID" "0,1,2,3,4,5,6,7" group.long 0x2260++0x3 line.long 0x0 "DOM_GID_4,Indicate which group domain 4 belong to" bitfld.long 0x0 3. "LOCK,Lock write for GID" "0,1" bitfld.long 0x0 0.--2. "GID,Group ID" "0,1,2,3,4,5,6,7" group.long 0x2278++0x3 line.long 0x0 "DOM_GID_5,Indicate which group domain 5 belong to" bitfld.long 0x0 3. "LOCK,Lock write for GID" "0,1" bitfld.long 0x0 0.--2. "GID,Group ID" "0,1,2,3,4,5,6,7" group.long 0x2290++0x3 line.long 0x0 "DOM_GID_6,Indicate which group domain 6 belong to" bitfld.long 0x0 3. "LOCK,Lock write for GID" "0,1" bitfld.long 0x0 0.--2. "GID,Group ID" "0,1,2,3,4,5,6,7" group.long 0x22A8++0x3 line.long 0x0 "DOM_GID_7,Indicate which group domain 7 belong to" bitfld.long 0x0 3. "LOCK,Lock write for GID" "0,1" bitfld.long 0x0 0.--2. "GID,Group ID" "0,1,2,3,4,5,6,7" group.long 0x22C0++0x3 line.long 0x0 "DOM_GID_8,Indicate which group domain 8 belong to" bitfld.long 0x0 3. "LOCK,Lock write for GID" "0,1" bitfld.long 0x0 0.--2. "GID,Group ID" "0,1,2,3,4,5,6,7" group.long 0x22D8++0x3 line.long 0x0 "DOM_GID_9,Indicate which group domain 9 belong to" bitfld.long 0x0 3. "LOCK,Lock write for GID" "0,1" bitfld.long 0x0 0.--2. "GID,Group ID" "0,1,2,3,4,5,6,7" group.long 0x22F0++0x3 line.long 0x0 "DOM_GID_10,Indicate which group domain 10 belong to" bitfld.long 0x0 3. "LOCK,Lock write for GID" "0,1" bitfld.long 0x0 0.--2. "GID,Group ID" "0,1,2,3,4,5,6,7" group.long 0x2308++0x3 line.long 0x0 "DOM_GID_11,Indicate which group domain 11 belong to" bitfld.long 0x0 3. "LOCK,Lock write for GID" "0,1" bitfld.long 0x0 0.--2. "GID,Group ID" "0,1,2,3,4,5,6,7" group.long 0x2320++0x3 line.long 0x0 "DOM_GID_12,Indicate which group domain 12 belong to" bitfld.long 0x0 3. "LOCK,Lock write for GID" "0,1" bitfld.long 0x0 0.--2. "GID,Group ID" "0,1,2,3,4,5,6,7" group.long 0x2338++0x3 line.long 0x0 "DOM_GID_13,Indicate which group domain 13 belong to" bitfld.long 0x0 3. "LOCK,Lock write for GID" "0,1" bitfld.long 0x0 0.--2. "GID,Group ID" "0,1,2,3,4,5,6,7" group.long 0x2350++0x3 line.long 0x0 "DOM_GID_14,Indicate which group domain 14 belong to" bitfld.long 0x0 3. "LOCK,Lock write for GID" "0,1" bitfld.long 0x0 0.--2. "GID,Group ID" "0,1,2,3,4,5,6,7" group.long 0x2368++0x3 line.long 0x0 "DOM_GID_15,Indicate which group domain 15 belong to" bitfld.long 0x0 3. "LOCK,Lock write for GID" "0,1" bitfld.long 0x0 0.--2. "GID,Group ID" "0,1,2,3,4,5,6,7" repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x34 0x68 0x9C 0xD0 0x104 0x138 0x16C 0x1A0 0x1D4 0x208 0x23C 0x270 0x2A4 0x2D8 0x30C ) group.long ($2+0x2400)++0x3 line.long 0x0 "DOM_PER0_$1,Domain Permission Control. It can be only configured by resource manager and domain owner." bitfld.long 0x0 31. "DOM7_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 29.--30. "DOM7_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 28. "DOM7_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 27. "DOM6_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 25.--26. "DOM6_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" newline bitfld.long 0x0 24. "DOM6_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 23. "DOM5_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 21.--22. "DOM5_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 20. "DOM5_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 19. "DOM4_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" newline bitfld.long 0x0 17.--18. "DOM4_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM4_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 15. "DOM3_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 13.--14. "DOM3_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 12. "DOM3_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" newline bitfld.long 0x0 11. "DOM2_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 9.--10. "DOM2_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM2_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 7. "DOM1_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 5.--6. "DOM1_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" newline bitfld.long 0x0 4. "DOM1_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 3. "DOM0_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 1.--2. "DOM0_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM0_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" repeat.end repeat 16. (list 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1A 0x1B 0x1C 0x1D 0x1E 0x1F )(list 0x340 0x374 0x3A8 0x3DC 0x410 0x444 0x478 0x4AC 0x4E0 0x514 0x548 0x57C 0x5B0 0x5E4 0x618 0x64C ) group.long ($2+0x2400)++0x3 line.long 0x0 "DOM_PER0_$1,Domain Permission Control. It can be only configured by resource manager and domain owner." bitfld.long 0x0 31. "DOM7_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 29.--30. "DOM7_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 28. "DOM7_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 27. "DOM6_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 25.--26. "DOM6_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" newline bitfld.long 0x0 24. "DOM6_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 23. "DOM5_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 21.--22. "DOM5_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 20. "DOM5_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 19. "DOM4_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" newline bitfld.long 0x0 17.--18. "DOM4_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM4_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 15. "DOM3_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 13.--14. "DOM3_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 12. "DOM3_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" newline bitfld.long 0x0 11. "DOM2_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 9.--10. "DOM2_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM2_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 7. "DOM1_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 5.--6. "DOM1_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" newline bitfld.long 0x0 4. "DOM1_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 3. "DOM0_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 1.--2. "DOM0_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM0_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" repeat.end repeat 16. (list 0x20 0x21 0x22 0x23 0x24 0x25 0x26 0x27 0x28 0x29 0x2A 0x2B 0x2C 0x2D 0x2E 0x2F )(list 0x680 0x6B4 0x6E8 0x71C 0x750 0x784 0x7B8 0x7EC 0x820 0x854 0x888 0x8BC 0x8F0 0x924 0x958 0x98C ) group.long ($2+0x2400)++0x3 line.long 0x0 "DOM_PER0_$1,Domain Permission Control. It can be only configured by resource manager and domain owner." bitfld.long 0x0 31. "DOM7_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 29.--30. "DOM7_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 28. "DOM7_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 27. "DOM6_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 25.--26. "DOM6_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" newline bitfld.long 0x0 24. "DOM6_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 23. "DOM5_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 21.--22. "DOM5_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 20. "DOM5_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 19. "DOM4_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" newline bitfld.long 0x0 17.--18. "DOM4_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM4_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 15. "DOM3_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 13.--14. "DOM3_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 12. "DOM3_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" newline bitfld.long 0x0 11. "DOM2_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 9.--10. "DOM2_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM2_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 7. "DOM1_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 5.--6. "DOM1_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" newline bitfld.long 0x0 4. "DOM1_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 3. "DOM0_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 1.--2. "DOM0_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM0_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" repeat.end repeat 16. (list 0x30 0x31 0x32 0x33 0x34 0x35 0x36 0x37 0x38 0x39 0x3A 0x3B 0x3C 0x3D 0x3E 0x3F )(list 0x9C0 0x9F4 0xA28 0xA5C 0xA90 0xAC4 0xAF8 0xB2C 0xB60 0xB94 0xBC8 0xBFC 0xC30 0xC64 0xC98 0xCCC ) group.long ($2+0x2400)++0x3 line.long 0x0 "DOM_PER0_$1,Domain Permission Control. It can be only configured by resource manager and domain owner." bitfld.long 0x0 31. "DOM7_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 29.--30. "DOM7_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 28. "DOM7_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 27. "DOM6_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 25.--26. "DOM6_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" newline bitfld.long 0x0 24. "DOM6_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 23. "DOM5_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 21.--22. "DOM5_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 20. "DOM5_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 19. "DOM4_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" newline bitfld.long 0x0 17.--18. "DOM4_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM4_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 15. "DOM3_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 13.--14. "DOM3_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 12. "DOM3_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" newline bitfld.long 0x0 11. "DOM2_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 9.--10. "DOM2_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM2_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 7. "DOM1_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 5.--6. "DOM1_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" newline bitfld.long 0x0 4. "DOM1_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 3. "DOM0_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 1.--2. "DOM0_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM0_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" repeat.end repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x34 0x68 0x9C 0xD0 0x104 0x138 0x16C 0x1A0 0x1D4 0x208 0x23C 0x270 0x2A4 0x2D8 0x30C ) group.long ($2+0x2404)++0x3 line.long 0x0 "DOM_PER1_$1,Domain Permission Control. It can be only configured by resource manager and domain owner." bitfld.long 0x0 31. "DOM15_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 29.--30. "DOM15_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 28. "DOM15_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 27. "DOM14_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 25.--26. "DOM14_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" newline bitfld.long 0x0 24. "DOM14_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 23. "DOM13_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 21.--22. "DOM13_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 20. "DOM13_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 19. "DOM12_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" newline bitfld.long 0x0 17.--18. "DOM12_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM12_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 15. "DOM11_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 13.--14. "DOM11_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 12. "DOM11_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" newline bitfld.long 0x0 11. "DOM10_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 9.--10. "DOM10_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM10_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 7. "DOM9_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 5.--6. "DOM9_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" newline bitfld.long 0x0 4. "DOM9_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 3. "DOM8_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 1.--2. "DOM8_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM8_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" repeat.end repeat 16. (list 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1A 0x1B 0x1C 0x1D 0x1E 0x1F )(list 0x340 0x374 0x3A8 0x3DC 0x410 0x444 0x478 0x4AC 0x4E0 0x514 0x548 0x57C 0x5B0 0x5E4 0x618 0x64C ) group.long ($2+0x2404)++0x3 line.long 0x0 "DOM_PER1_$1,Domain Permission Control. It can be only configured by resource manager and domain owner." bitfld.long 0x0 31. "DOM15_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 29.--30. "DOM15_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 28. "DOM15_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 27. "DOM14_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 25.--26. "DOM14_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" newline bitfld.long 0x0 24. "DOM14_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 23. "DOM13_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 21.--22. "DOM13_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 20. "DOM13_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 19. "DOM12_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" newline bitfld.long 0x0 17.--18. "DOM12_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM12_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 15. "DOM11_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 13.--14. "DOM11_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 12. "DOM11_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" newline bitfld.long 0x0 11. "DOM10_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 9.--10. "DOM10_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM10_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 7. "DOM9_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 5.--6. "DOM9_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" newline bitfld.long 0x0 4. "DOM9_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 3. "DOM8_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 1.--2. "DOM8_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM8_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" repeat.end repeat 16. (list 0x20 0x21 0x22 0x23 0x24 0x25 0x26 0x27 0x28 0x29 0x2A 0x2B 0x2C 0x2D 0x2E 0x2F )(list 0x680 0x6B4 0x6E8 0x71C 0x750 0x784 0x7B8 0x7EC 0x820 0x854 0x888 0x8BC 0x8F0 0x924 0x958 0x98C ) group.long ($2+0x2404)++0x3 line.long 0x0 "DOM_PER1_$1,Domain Permission Control. It can be only configured by resource manager and domain owner." bitfld.long 0x0 31. "DOM15_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 29.--30. "DOM15_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 28. "DOM15_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 27. "DOM14_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 25.--26. "DOM14_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" newline bitfld.long 0x0 24. "DOM14_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 23. "DOM13_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 21.--22. "DOM13_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 20. "DOM13_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 19. "DOM12_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" newline bitfld.long 0x0 17.--18. "DOM12_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM12_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 15. "DOM11_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 13.--14. "DOM11_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 12. "DOM11_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" newline bitfld.long 0x0 11. "DOM10_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 9.--10. "DOM10_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM10_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 7. "DOM9_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 5.--6. "DOM9_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" newline bitfld.long 0x0 4. "DOM9_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 3. "DOM8_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 1.--2. "DOM8_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM8_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" repeat.end repeat 16. (list 0x30 0x31 0x32 0x33 0x34 0x35 0x36 0x37 0x38 0x39 0x3A 0x3B 0x3C 0x3D 0x3E 0x3F )(list 0x9C0 0x9F4 0xA28 0xA5C 0xA90 0xAC4 0xAF8 0xB2C 0xB60 0xB94 0xBC8 0xBFC 0xC30 0xC64 0xC98 0xCCC ) group.long ($2+0x2404)++0x3 line.long 0x0 "DOM_PER1_$1,Domain Permission Control. It can be only configured by resource manager and domain owner." bitfld.long 0x0 31. "DOM15_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 29.--30. "DOM15_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 28. "DOM15_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 27. "DOM14_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 25.--26. "DOM14_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" newline bitfld.long 0x0 24. "DOM14_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 23. "DOM13_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 21.--22. "DOM13_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 20. "DOM13_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 19. "DOM12_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" newline bitfld.long 0x0 17.--18. "DOM12_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM12_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 15. "DOM11_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 13.--14. "DOM11_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 12. "DOM11_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" newline bitfld.long 0x0 11. "DOM10_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 9.--10. "DOM10_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM10_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 7. "DOM9_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 5.--6. "DOM9_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" newline bitfld.long 0x0 4. "DOM9_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 3. "DOM8_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 1.--2. "DOM8_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM8_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" repeat.end repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x34 0x68 0x9C 0xD0 0x104 0x138 0x16C 0x1A0 0x1D4 0x208 0x23C 0x270 0x2A4 0x2D8 0x30C ) group.long ($2+0x2408)++0x3 line.long 0x0 "SEC_PER0_$1,This register is only used for resource manager to control secure access permission." bitfld.long 0x0 31. "DOM3_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM3_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM3_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM3_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM2_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM2_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM2_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM2_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM1_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM1_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM1_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM1_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM0_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM0_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM0_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM0_SEC_EN,Domain secure permission control enable" "0,1" repeat.end repeat 16. (list 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1A 0x1B 0x1C 0x1D 0x1E 0x1F )(list 0x340 0x374 0x3A8 0x3DC 0x410 0x444 0x478 0x4AC 0x4E0 0x514 0x548 0x57C 0x5B0 0x5E4 0x618 0x64C ) group.long ($2+0x2408)++0x3 line.long 0x0 "SEC_PER0_$1,This register is only used for resource manager to control secure access permission." bitfld.long 0x0 31. "DOM3_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM3_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM3_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM3_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM2_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM2_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM2_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM2_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM1_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM1_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM1_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM1_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM0_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM0_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM0_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM0_SEC_EN,Domain secure permission control enable" "0,1" repeat.end repeat 16. (list 0x20 0x21 0x22 0x23 0x24 0x25 0x26 0x27 0x28 0x29 0x2A 0x2B 0x2C 0x2D 0x2E 0x2F )(list 0x680 0x6B4 0x6E8 0x71C 0x750 0x784 0x7B8 0x7EC 0x820 0x854 0x888 0x8BC 0x8F0 0x924 0x958 0x98C ) group.long ($2+0x2408)++0x3 line.long 0x0 "SEC_PER0_$1,This register is only used for resource manager to control secure access permission." bitfld.long 0x0 31. "DOM3_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM3_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM3_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM3_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM2_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM2_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM2_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM2_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM1_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM1_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM1_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM1_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM0_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM0_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM0_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM0_SEC_EN,Domain secure permission control enable" "0,1" repeat.end repeat 16. (list 0x30 0x31 0x32 0x33 0x34 0x35 0x36 0x37 0x38 0x39 0x3A 0x3B 0x3C 0x3D 0x3E 0x3F )(list 0x9C0 0x9F4 0xA28 0xA5C 0xA90 0xAC4 0xAF8 0xB2C 0xB60 0xB94 0xBC8 0xBFC 0xC30 0xC64 0xC98 0xCCC ) group.long ($2+0x2408)++0x3 line.long 0x0 "SEC_PER0_$1,This register is only used for resource manager to control secure access permission." bitfld.long 0x0 31. "DOM3_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM3_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM3_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM3_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM2_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM2_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM2_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM2_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM1_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM1_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM1_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM1_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM0_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM0_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM0_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM0_SEC_EN,Domain secure permission control enable" "0,1" repeat.end repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x34 0x68 0x9C 0xD0 0x104 0x138 0x16C 0x1A0 0x1D4 0x208 0x23C 0x270 0x2A4 0x2D8 0x30C ) group.long ($2+0x240C)++0x3 line.long 0x0 "SEC_PER1_$1,This register is only used for resource manager to control secure access permission." bitfld.long 0x0 31. "DOM7_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM7_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM7_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM7_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM6_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM6_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM6_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM6_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM5_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM5_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM5_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM5_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM4_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM4_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM4_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM4_SEC_EN,Domain secure permission control enable" "0,1" repeat.end repeat 16. (list 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1A 0x1B 0x1C 0x1D 0x1E 0x1F )(list 0x340 0x374 0x3A8 0x3DC 0x410 0x444 0x478 0x4AC 0x4E0 0x514 0x548 0x57C 0x5B0 0x5E4 0x618 0x64C ) group.long ($2+0x240C)++0x3 line.long 0x0 "SEC_PER1_$1,This register is only used for resource manager to control secure access permission." bitfld.long 0x0 31. "DOM7_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM7_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM7_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM7_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM6_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM6_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM6_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM6_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM5_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM5_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM5_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM5_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM4_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM4_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM4_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM4_SEC_EN,Domain secure permission control enable" "0,1" repeat.end repeat 16. (list 0x20 0x21 0x22 0x23 0x24 0x25 0x26 0x27 0x28 0x29 0x2A 0x2B 0x2C 0x2D 0x2E 0x2F )(list 0x680 0x6B4 0x6E8 0x71C 0x750 0x784 0x7B8 0x7EC 0x820 0x854 0x888 0x8BC 0x8F0 0x924 0x958 0x98C ) group.long ($2+0x240C)++0x3 line.long 0x0 "SEC_PER1_$1,This register is only used for resource manager to control secure access permission." bitfld.long 0x0 31. "DOM7_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM7_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM7_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM7_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM6_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM6_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM6_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM6_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM5_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM5_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM5_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM5_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM4_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM4_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM4_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM4_SEC_EN,Domain secure permission control enable" "0,1" repeat.end repeat 16. (list 0x30 0x31 0x32 0x33 0x34 0x35 0x36 0x37 0x38 0x39 0x3A 0x3B 0x3C 0x3D 0x3E 0x3F )(list 0x9C0 0x9F4 0xA28 0xA5C 0xA90 0xAC4 0xAF8 0xB2C 0xB60 0xB94 0xBC8 0xBFC 0xC30 0xC64 0xC98 0xCCC ) group.long ($2+0x240C)++0x3 line.long 0x0 "SEC_PER1_$1,This register is only used for resource manager to control secure access permission." bitfld.long 0x0 31. "DOM7_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM7_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM7_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM7_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM6_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM6_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM6_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM6_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM5_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM5_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM5_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM5_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM4_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM4_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM4_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM4_SEC_EN,Domain secure permission control enable" "0,1" repeat.end repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x34 0x68 0x9C 0xD0 0x104 0x138 0x16C 0x1A0 0x1D4 0x208 0x23C 0x270 0x2A4 0x2D8 0x30C ) group.long ($2+0x2410)++0x3 line.long 0x0 "SEC_PER2_$1,This register is only used for resource manager to control secure access permission." bitfld.long 0x0 31. "DOM11_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM11_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM11_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM11_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM10_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM10_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM10_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM10_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM9_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM9_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM9_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM9_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM8_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM8_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM8_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM8_SEC_EN,Domain secure permission control enable" "0,1" repeat.end repeat 16. (list 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1A 0x1B 0x1C 0x1D 0x1E 0x1F )(list 0x340 0x374 0x3A8 0x3DC 0x410 0x444 0x478 0x4AC 0x4E0 0x514 0x548 0x57C 0x5B0 0x5E4 0x618 0x64C ) group.long ($2+0x2410)++0x3 line.long 0x0 "SEC_PER2_$1,This register is only used for resource manager to control secure access permission." bitfld.long 0x0 31. "DOM11_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM11_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM11_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM11_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM10_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM10_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM10_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM10_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM9_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM9_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM9_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM9_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM8_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM8_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM8_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM8_SEC_EN,Domain secure permission control enable" "0,1" repeat.end repeat 16. (list 0x20 0x21 0x22 0x23 0x24 0x25 0x26 0x27 0x28 0x29 0x2A 0x2B 0x2C 0x2D 0x2E 0x2F )(list 0x680 0x6B4 0x6E8 0x71C 0x750 0x784 0x7B8 0x7EC 0x820 0x854 0x888 0x8BC 0x8F0 0x924 0x958 0x98C ) group.long ($2+0x2410)++0x3 line.long 0x0 "SEC_PER2_$1,This register is only used for resource manager to control secure access permission." bitfld.long 0x0 31. "DOM11_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM11_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM11_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM11_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM10_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM10_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM10_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM10_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM9_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM9_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM9_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM9_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM8_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM8_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM8_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM8_SEC_EN,Domain secure permission control enable" "0,1" repeat.end repeat 16. (list 0x30 0x31 0x32 0x33 0x34 0x35 0x36 0x37 0x38 0x39 0x3A 0x3B 0x3C 0x3D 0x3E 0x3F )(list 0x9C0 0x9F4 0xA28 0xA5C 0xA90 0xAC4 0xAF8 0xB2C 0xB60 0xB94 0xBC8 0xBFC 0xC30 0xC64 0xC98 0xCCC ) group.long ($2+0x2410)++0x3 line.long 0x0 "SEC_PER2_$1,This register is only used for resource manager to control secure access permission." bitfld.long 0x0 31. "DOM11_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM11_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM11_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM11_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM10_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM10_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM10_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM10_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM9_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM9_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM9_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM9_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM8_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM8_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM8_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM8_SEC_EN,Domain secure permission control enable" "0,1" repeat.end repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x34 0x68 0x9C 0xD0 0x104 0x138 0x16C 0x1A0 0x1D4 0x208 0x23C 0x270 0x2A4 0x2D8 0x30C ) group.long ($2+0x2414)++0x3 line.long 0x0 "SEC_PER3_$1,This register is only used for resource manager to control secure access permission." bitfld.long 0x0 31. "DOM15_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM15_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM15_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM15_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM14_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM14_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM14_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM14_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM13_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM13_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM13_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM13_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM12_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM12_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM12_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM12_SEC_EN,Domain secure permission control enable" "0,1" repeat.end repeat 16. (list 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1A 0x1B 0x1C 0x1D 0x1E 0x1F )(list 0x340 0x374 0x3A8 0x3DC 0x410 0x444 0x478 0x4AC 0x4E0 0x514 0x548 0x57C 0x5B0 0x5E4 0x618 0x64C ) group.long ($2+0x2414)++0x3 line.long 0x0 "SEC_PER3_$1,This register is only used for resource manager to control secure access permission." bitfld.long 0x0 31. "DOM15_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM15_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM15_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM15_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM14_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM14_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM14_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM14_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM13_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM13_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM13_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM13_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM12_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM12_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM12_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM12_SEC_EN,Domain secure permission control enable" "0,1" repeat.end repeat 16. (list 0x20 0x21 0x22 0x23 0x24 0x25 0x26 0x27 0x28 0x29 0x2A 0x2B 0x2C 0x2D 0x2E 0x2F )(list 0x680 0x6B4 0x6E8 0x71C 0x750 0x784 0x7B8 0x7EC 0x820 0x854 0x888 0x8BC 0x8F0 0x924 0x958 0x98C ) group.long ($2+0x2414)++0x3 line.long 0x0 "SEC_PER3_$1,This register is only used for resource manager to control secure access permission." bitfld.long 0x0 31. "DOM15_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM15_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM15_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM15_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM14_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM14_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM14_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM14_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM13_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM13_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM13_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM13_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM12_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM12_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM12_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM12_SEC_EN,Domain secure permission control enable" "0,1" repeat.end repeat 16. (list 0x30 0x31 0x32 0x33 0x34 0x35 0x36 0x37 0x38 0x39 0x3A 0x3B 0x3C 0x3D 0x3E 0x3F )(list 0x9C0 0x9F4 0xA28 0xA5C 0xA90 0xAC4 0xAF8 0xB2C 0xB60 0xB94 0xBC8 0xBFC 0xC30 0xC64 0xC98 0xCCC ) group.long ($2+0x2414)++0x3 line.long 0x0 "SEC_PER3_$1,This register is only used for resource manager to control secure access permission." bitfld.long 0x0 31. "DOM15_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM15_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM15_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM15_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM14_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM14_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM14_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM14_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM13_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM13_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM13_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM13_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM12_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM12_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM12_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM12_SEC_EN,Domain secure permission control enable" "0,1" repeat.end repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x34 0x68 0x9C 0xD0 0x104 0x138 0x16C 0x1A0 0x1D4 0x208 0x23C 0x270 0x2A4 0x2D8 0x30C ) group.long ($2+0x2418)++0x3 line.long 0x0 "PRI_PER0_$1,This register is only used for resource manager to control privileged access permission." bitfld.long 0x0 31. "DOM3_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM3_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM3_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM3_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM2_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM2_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM2_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM2_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM1_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM1_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM1_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM1_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM0_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM0_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM0_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM0_PRI_EN,Domain privileged permission control enable" "0,1" repeat.end repeat 16. (list 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1A 0x1B 0x1C 0x1D 0x1E 0x1F )(list 0x340 0x374 0x3A8 0x3DC 0x410 0x444 0x478 0x4AC 0x4E0 0x514 0x548 0x57C 0x5B0 0x5E4 0x618 0x64C ) group.long ($2+0x2418)++0x3 line.long 0x0 "PRI_PER0_$1,This register is only used for resource manager to control privileged access permission." bitfld.long 0x0 31. "DOM3_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM3_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM3_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM3_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM2_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM2_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM2_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM2_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM1_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM1_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM1_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM1_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM0_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM0_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM0_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM0_PRI_EN,Domain privileged permission control enable" "0,1" repeat.end repeat 16. (list 0x20 0x21 0x22 0x23 0x24 0x25 0x26 0x27 0x28 0x29 0x2A 0x2B 0x2C 0x2D 0x2E 0x2F )(list 0x680 0x6B4 0x6E8 0x71C 0x750 0x784 0x7B8 0x7EC 0x820 0x854 0x888 0x8BC 0x8F0 0x924 0x958 0x98C ) group.long ($2+0x2418)++0x3 line.long 0x0 "PRI_PER0_$1,This register is only used for resource manager to control privileged access permission." bitfld.long 0x0 31. "DOM3_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM3_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM3_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM3_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM2_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM2_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM2_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM2_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM1_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM1_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM1_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM1_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM0_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM0_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM0_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM0_PRI_EN,Domain privileged permission control enable" "0,1" repeat.end repeat 16. (list 0x30 0x31 0x32 0x33 0x34 0x35 0x36 0x37 0x38 0x39 0x3A 0x3B 0x3C 0x3D 0x3E 0x3F )(list 0x9C0 0x9F4 0xA28 0xA5C 0xA90 0xAC4 0xAF8 0xB2C 0xB60 0xB94 0xBC8 0xBFC 0xC30 0xC64 0xC98 0xCCC ) group.long ($2+0x2418)++0x3 line.long 0x0 "PRI_PER0_$1,This register is only used for resource manager to control privileged access permission." bitfld.long 0x0 31. "DOM3_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM3_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM3_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM3_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM2_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM2_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM2_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM2_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM1_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM1_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM1_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM1_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM0_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM0_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM0_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM0_PRI_EN,Domain privileged permission control enable" "0,1" repeat.end repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x34 0x68 0x9C 0xD0 0x104 0x138 0x16C 0x1A0 0x1D4 0x208 0x23C 0x270 0x2A4 0x2D8 0x30C ) group.long ($2+0x241C)++0x3 line.long 0x0 "PRI_PER1_$1,This register is only used for resource manager to control privileged access permission." bitfld.long 0x0 31. "DOM7_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM7_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM7_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM7_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM6_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM6_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM6_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM6_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM5_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM5_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM5_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM5_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM4_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM4_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM4_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM4_PRI_EN,Domain privileged permission control enable" "0,1" repeat.end repeat 16. (list 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1A 0x1B 0x1C 0x1D 0x1E 0x1F )(list 0x340 0x374 0x3A8 0x3DC 0x410 0x444 0x478 0x4AC 0x4E0 0x514 0x548 0x57C 0x5B0 0x5E4 0x618 0x64C ) group.long ($2+0x241C)++0x3 line.long 0x0 "PRI_PER1_$1,This register is only used for resource manager to control privileged access permission." bitfld.long 0x0 31. "DOM7_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM7_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM7_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM7_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM6_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM6_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM6_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM6_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM5_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM5_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM5_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM5_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM4_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM4_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM4_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM4_PRI_EN,Domain privileged permission control enable" "0,1" repeat.end repeat 16. (list 0x20 0x21 0x22 0x23 0x24 0x25 0x26 0x27 0x28 0x29 0x2A 0x2B 0x2C 0x2D 0x2E 0x2F )(list 0x680 0x6B4 0x6E8 0x71C 0x750 0x784 0x7B8 0x7EC 0x820 0x854 0x888 0x8BC 0x8F0 0x924 0x958 0x98C ) group.long ($2+0x241C)++0x3 line.long 0x0 "PRI_PER1_$1,This register is only used for resource manager to control privileged access permission." bitfld.long 0x0 31. "DOM7_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM7_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM7_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM7_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM6_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM6_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM6_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM6_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM5_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM5_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM5_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM5_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM4_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM4_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM4_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM4_PRI_EN,Domain privileged permission control enable" "0,1" repeat.end repeat 16. (list 0x30 0x31 0x32 0x33 0x34 0x35 0x36 0x37 0x38 0x39 0x3A 0x3B 0x3C 0x3D 0x3E 0x3F )(list 0x9C0 0x9F4 0xA28 0xA5C 0xA90 0xAC4 0xAF8 0xB2C 0xB60 0xB94 0xBC8 0xBFC 0xC30 0xC64 0xC98 0xCCC ) group.long ($2+0x241C)++0x3 line.long 0x0 "PRI_PER1_$1,This register is only used for resource manager to control privileged access permission." bitfld.long 0x0 31. "DOM7_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM7_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM7_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM7_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM6_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM6_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM6_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM6_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM5_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM5_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM5_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM5_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM4_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM4_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM4_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM4_PRI_EN,Domain privileged permission control enable" "0,1" repeat.end repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x34 0x68 0x9C 0xD0 0x104 0x138 0x16C 0x1A0 0x1D4 0x208 0x23C 0x270 0x2A4 0x2D8 0x30C ) group.long ($2+0x2420)++0x3 line.long 0x0 "PRI_PER2_$1,This register is only used for resource manager to control privileged access permission." bitfld.long 0x0 31. "DOM11_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM11_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM11_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM11_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM10_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM10_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM10_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM10_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM9_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM9_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM9_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM9_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM8_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM8_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM8_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM8_PRI_EN,Domain privileged permission control enable" "0,1" repeat.end repeat 16. (list 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1A 0x1B 0x1C 0x1D 0x1E 0x1F )(list 0x340 0x374 0x3A8 0x3DC 0x410 0x444 0x478 0x4AC 0x4E0 0x514 0x548 0x57C 0x5B0 0x5E4 0x618 0x64C ) group.long ($2+0x2420)++0x3 line.long 0x0 "PRI_PER2_$1,This register is only used for resource manager to control privileged access permission." bitfld.long 0x0 31. "DOM11_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM11_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM11_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM11_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM10_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM10_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM10_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM10_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM9_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM9_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM9_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM9_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM8_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM8_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM8_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM8_PRI_EN,Domain privileged permission control enable" "0,1" repeat.end repeat 16. (list 0x20 0x21 0x22 0x23 0x24 0x25 0x26 0x27 0x28 0x29 0x2A 0x2B 0x2C 0x2D 0x2E 0x2F )(list 0x680 0x6B4 0x6E8 0x71C 0x750 0x784 0x7B8 0x7EC 0x820 0x854 0x888 0x8BC 0x8F0 0x924 0x958 0x98C ) group.long ($2+0x2420)++0x3 line.long 0x0 "PRI_PER2_$1,This register is only used for resource manager to control privileged access permission." bitfld.long 0x0 31. "DOM11_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM11_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM11_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM11_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM10_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM10_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM10_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM10_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM9_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM9_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM9_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM9_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM8_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM8_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM8_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM8_PRI_EN,Domain privileged permission control enable" "0,1" repeat.end repeat 16. (list 0x30 0x31 0x32 0x33 0x34 0x35 0x36 0x37 0x38 0x39 0x3A 0x3B 0x3C 0x3D 0x3E 0x3F )(list 0x9C0 0x9F4 0xA28 0xA5C 0xA90 0xAC4 0xAF8 0xB2C 0xB60 0xB94 0xBC8 0xBFC 0xC30 0xC64 0xC98 0xCCC ) group.long ($2+0x2420)++0x3 line.long 0x0 "PRI_PER2_$1,This register is only used for resource manager to control privileged access permission." bitfld.long 0x0 31. "DOM11_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM11_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM11_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM11_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM10_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM10_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM10_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM10_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM9_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM9_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM9_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM9_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM8_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM8_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM8_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM8_PRI_EN,Domain privileged permission control enable" "0,1" repeat.end repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x34 0x68 0x9C 0xD0 0x104 0x138 0x16C 0x1A0 0x1D4 0x208 0x23C 0x270 0x2A4 0x2D8 0x30C ) group.long ($2+0x2424)++0x3 line.long 0x0 "PRI_PER3_$1,This register is only used for resource manager to control privileged access permission." bitfld.long 0x0 31. "DOM15_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM15_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM15_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM15_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM14_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM14_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM14_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM14_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM13_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM13_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM13_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM13_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM12_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM12_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM12_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM12_PRI_EN,Domain privileged permission control enable" "0,1" repeat.end repeat 16. (list 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1A 0x1B 0x1C 0x1D 0x1E 0x1F )(list 0x340 0x374 0x3A8 0x3DC 0x410 0x444 0x478 0x4AC 0x4E0 0x514 0x548 0x57C 0x5B0 0x5E4 0x618 0x64C ) group.long ($2+0x2424)++0x3 line.long 0x0 "PRI_PER3_$1,This register is only used for resource manager to control privileged access permission." bitfld.long 0x0 31. "DOM15_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM15_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM15_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM15_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM14_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM14_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM14_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM14_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM13_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM13_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM13_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM13_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM12_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM12_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM12_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM12_PRI_EN,Domain privileged permission control enable" "0,1" repeat.end repeat 16. (list 0x20 0x21 0x22 0x23 0x24 0x25 0x26 0x27 0x28 0x29 0x2A 0x2B 0x2C 0x2D 0x2E 0x2F )(list 0x680 0x6B4 0x6E8 0x71C 0x750 0x784 0x7B8 0x7EC 0x820 0x854 0x888 0x8BC 0x8F0 0x924 0x958 0x98C ) group.long ($2+0x2424)++0x3 line.long 0x0 "PRI_PER3_$1,This register is only used for resource manager to control privileged access permission." bitfld.long 0x0 31. "DOM15_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM15_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM15_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM15_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM14_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM14_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM14_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM14_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM13_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM13_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM13_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM13_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM12_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM12_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM12_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM12_PRI_EN,Domain privileged permission control enable" "0,1" repeat.end repeat 16. (list 0x30 0x31 0x32 0x33 0x34 0x35 0x36 0x37 0x38 0x39 0x3A 0x3B 0x3C 0x3D 0x3E 0x3F )(list 0x9C0 0x9F4 0xA28 0xA5C 0xA90 0xAC4 0xAF8 0xB2C 0xB60 0xB94 0xBC8 0xBFC 0xC30 0xC64 0xC98 0xCCC ) group.long ($2+0x2424)++0x3 line.long 0x0 "PRI_PER3_$1,This register is only used for resource manager to control privileged access permission." bitfld.long 0x0 31. "DOM15_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM15_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM15_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM15_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM14_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM14_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM14_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM14_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM13_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM13_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM13_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM13_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM12_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM12_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM12_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM12_PRI_EN,Domain privileged permission control enable" "0,1" repeat.end repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x34 0x68 0x9C 0xD0 0x104 0x138 0x16C 0x1A0 0x1D4 0x208 0x23C 0x270 0x2A4 0x2D8 0x30C ) group.long ($2+0x2428)++0x3 line.long 0x0 "DOM_SEC_PER_$1,This register is only used for domain master to control secure access permission. When the domain master write this register. it only changes the secure permission for itself. When the domain master read this register. it gets permission.." bitfld.long 0x0 7. "DOM_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" newline bitfld.long 0x0 0. "DOM_SEC_EN,Domain secure permission control enable" "0,1" repeat.end repeat 16. (list 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1A 0x1B 0x1C 0x1D 0x1E 0x1F )(list 0x340 0x374 0x3A8 0x3DC 0x410 0x444 0x478 0x4AC 0x4E0 0x514 0x548 0x57C 0x5B0 0x5E4 0x618 0x64C ) group.long ($2+0x2428)++0x3 line.long 0x0 "DOM_SEC_PER_$1,This register is only used for domain master to control secure access permission. When the domain master write this register. it only changes the secure permission for itself. When the domain master read this register. it gets permission.." bitfld.long 0x0 7. "DOM_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" newline bitfld.long 0x0 0. "DOM_SEC_EN,Domain secure permission control enable" "0,1" repeat.end repeat 16. (list 0x20 0x21 0x22 0x23 0x24 0x25 0x26 0x27 0x28 0x29 0x2A 0x2B 0x2C 0x2D 0x2E 0x2F )(list 0x680 0x6B4 0x6E8 0x71C 0x750 0x784 0x7B8 0x7EC 0x820 0x854 0x888 0x8BC 0x8F0 0x924 0x958 0x98C ) group.long ($2+0x2428)++0x3 line.long 0x0 "DOM_SEC_PER_$1,This register is only used for domain master to control secure access permission. When the domain master write this register. it only changes the secure permission for itself. When the domain master read this register. it gets permission.." bitfld.long 0x0 7. "DOM_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" newline bitfld.long 0x0 0. "DOM_SEC_EN,Domain secure permission control enable" "0,1" repeat.end repeat 16. (list 0x30 0x31 0x32 0x33 0x34 0x35 0x36 0x37 0x38 0x39 0x3A 0x3B 0x3C 0x3D 0x3E 0x3F )(list 0x9C0 0x9F4 0xA28 0xA5C 0xA90 0xAC4 0xAF8 0xB2C 0xB60 0xB94 0xBC8 0xBFC 0xC30 0xC64 0xC98 0xCCC ) group.long ($2+0x2428)++0x3 line.long 0x0 "DOM_SEC_PER_$1,This register is only used for domain master to control secure access permission. When the domain master write this register. it only changes the secure permission for itself. When the domain master read this register. it gets permission.." bitfld.long 0x0 7. "DOM_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" newline bitfld.long 0x0 0. "DOM_SEC_EN,Domain secure permission control enable" "0,1" repeat.end repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x34 0x68 0x9C 0xD0 0x104 0x138 0x16C 0x1A0 0x1D4 0x208 0x23C 0x270 0x2A4 0x2D8 0x30C ) group.long ($2+0x242C)++0x3 line.long 0x0 "DOM_PRI_PER_$1,This register is only used for domain master to control secure access permission. When the domain master write this register. it only changes the secure permission for itself. When the domain master read this register. it gets permission.." bitfld.long 0x0 7. "DOM_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" newline bitfld.long 0x0 0. "DOM_PRI_EN,Domain privileged permission control enable" "0,1" repeat.end repeat 16. (list 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1A 0x1B 0x1C 0x1D 0x1E 0x1F )(list 0x340 0x374 0x3A8 0x3DC 0x410 0x444 0x478 0x4AC 0x4E0 0x514 0x548 0x57C 0x5B0 0x5E4 0x618 0x64C ) group.long ($2+0x242C)++0x3 line.long 0x0 "DOM_PRI_PER_$1,This register is only used for domain master to control secure access permission. When the domain master write this register. it only changes the secure permission for itself. When the domain master read this register. it gets permission.." bitfld.long 0x0 7. "DOM_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" newline bitfld.long 0x0 0. "DOM_PRI_EN,Domain privileged permission control enable" "0,1" repeat.end repeat 16. (list 0x20 0x21 0x22 0x23 0x24 0x25 0x26 0x27 0x28 0x29 0x2A 0x2B 0x2C 0x2D 0x2E 0x2F )(list 0x680 0x6B4 0x6E8 0x71C 0x750 0x784 0x7B8 0x7EC 0x820 0x854 0x888 0x8BC 0x8F0 0x924 0x958 0x98C ) group.long ($2+0x242C)++0x3 line.long 0x0 "DOM_PRI_PER_$1,This register is only used for domain master to control secure access permission. When the domain master write this register. it only changes the secure permission for itself. When the domain master read this register. it gets permission.." bitfld.long 0x0 7. "DOM_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" newline bitfld.long 0x0 0. "DOM_PRI_EN,Domain privileged permission control enable" "0,1" repeat.end repeat 16. (list 0x30 0x31 0x32 0x33 0x34 0x35 0x36 0x37 0x38 0x39 0x3A 0x3B 0x3C 0x3D 0x3E 0x3F )(list 0x9C0 0x9F4 0xA28 0xA5C 0xA90 0xAC4 0xAF8 0xB2C 0xB60 0xB94 0xBC8 0xBFC 0xC30 0xC64 0xC98 0xCCC ) group.long ($2+0x242C)++0x3 line.long 0x0 "DOM_PRI_PER_$1,This register is only used for domain master to control secure access permission. When the domain master write this register. it only changes the secure permission for itself. When the domain master read this register. it gets permission.." bitfld.long 0x0 7. "DOM_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" newline bitfld.long 0x0 0. "DOM_PRI_EN,Domain privileged permission control enable" "0,1" repeat.end repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x34 0x68 0x9C 0xD0 0x104 0x138 0x16C 0x1A0 0x1D4 0x208 0x23C 0x270 0x2A4 0x2D8 0x30C ) group.long ($2+0x2430)++0x3 line.long 0x0 "DOM_ASSIGN_$1,Use to assign domain for accessing DOM_SEC_PER and DOM_PRI_PER register. Only resource manager. group manager and domain owner can access this register. For write. group manager must write its owen domain ID. otherwise write accessing will.." hexmask.long.byte 0x0 0.--3. 1. "DID,accessing DOM_SEC_PER and DOM_PRI_PER register" repeat.end repeat 16. (list 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1A 0x1B 0x1C 0x1D 0x1E 0x1F )(list 0x340 0x374 0x3A8 0x3DC 0x410 0x444 0x478 0x4AC 0x4E0 0x514 0x548 0x57C 0x5B0 0x5E4 0x618 0x64C ) group.long ($2+0x2430)++0x3 line.long 0x0 "DOM_ASSIGN_$1,Use to assign domain for accessing DOM_SEC_PER and DOM_PRI_PER register. Only resource manager. group manager and domain owner can access this register. For write. group manager must write its owen domain ID. otherwise write accessing will.." hexmask.long.byte 0x0 0.--3. 1. "DID,accessing DOM_SEC_PER and DOM_PRI_PER register" repeat.end repeat 16. (list 0x20 0x21 0x22 0x23 0x24 0x25 0x26 0x27 0x28 0x29 0x2A 0x2B 0x2C 0x2D 0x2E 0x2F )(list 0x680 0x6B4 0x6E8 0x71C 0x750 0x784 0x7B8 0x7EC 0x820 0x854 0x888 0x8BC 0x8F0 0x924 0x958 0x98C ) group.long ($2+0x2430)++0x3 line.long 0x0 "DOM_ASSIGN_$1,Use to assign domain for accessing DOM_SEC_PER and DOM_PRI_PER register. Only resource manager. group manager and domain owner can access this register. For write. group manager must write its owen domain ID. otherwise write accessing will.." hexmask.long.byte 0x0 0.--3. 1. "DID,accessing DOM_SEC_PER and DOM_PRI_PER register" repeat.end repeat 16. (list 0x30 0x31 0x32 0x33 0x34 0x35 0x36 0x37 0x38 0x39 0x3A 0x3B 0x3C 0x3D 0x3E 0x3F )(list 0x9C0 0x9F4 0xA28 0xA5C 0xA90 0xAC4 0xAF8 0xB2C 0xB60 0xB94 0xBC8 0xBFC 0xC30 0xC64 0xC98 0xCCC ) group.long ($2+0x2430)++0x3 line.long 0x0 "DOM_ASSIGN_$1,Use to assign domain for accessing DOM_SEC_PER and DOM_PRI_PER register. Only resource manager. group manager and domain owner can access this register. For write. group manager must write its owen domain ID. otherwise write accessing will.." hexmask.long.byte 0x0 0.--3. 1. "DID,accessing DOM_SEC_PER and DOM_PRI_PER register" repeat.end repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x38 0x70 0xA8 0xE0 0x118 0x150 0x188 0x1C0 0x1F8 0x230 0x268 0x2A0 0x2D8 0x310 0x348 ) group.long ($2+0x3100)++0x3 line.long 0x0 "RGN_DOM_$1,Assign domain for peripheral. It can be only configured by resource and group manager" bitfld.long 0x0 31. "LOCK,When this bit is set lock write for all the bits in the register." "0,1" bitfld.long 0x0 4. "SET,Set together with DID would change permission of this resource to following setting: 1) Domain access control enabled. 2) Read/Write allowed for the domain owner. 3) Read/Write not allowed for all the other domains. If this bit is not set only DID.." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Assign domain for peripheral" repeat.end repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x38 0x70 0xA8 0xE0 0x118 0x150 0x188 0x1C0 0x1F8 0x230 0x268 0x2A0 0x2D8 0x310 0x348 ) group.long ($2+0x3104)++0x3 line.long 0x0 "RGN_DOM_PER0_$1,Domain Permission Control. It can be only configured by resource manager and domain owner." bitfld.long 0x0 31. "DOM7_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 29.--30. "DOM7_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 28. "DOM7_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 27. "DOM6_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 25.--26. "DOM6_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" newline bitfld.long 0x0 24. "DOM6_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 23. "DOM5_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 21.--22. "DOM5_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 20. "DOM5_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 19. "DOM4_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" newline bitfld.long 0x0 17.--18. "DOM4_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM4_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 15. "DOM3_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 13.--14. "DOM3_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 12. "DOM3_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" newline bitfld.long 0x0 11. "DOM2_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 9.--10. "DOM2_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM2_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 7. "DOM1_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 5.--6. "DOM1_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" newline bitfld.long 0x0 4. "DOM1_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 3. "DOM0_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 1.--2. "DOM0_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM0_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" repeat.end repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x38 0x70 0xA8 0xE0 0x118 0x150 0x188 0x1C0 0x1F8 0x230 0x268 0x2A0 0x2D8 0x310 0x348 ) group.long ($2+0x3108)++0x3 line.long 0x0 "RGN_DOM_PER1_$1,Domain Permission Control. It can be only configured by resource manager and domain owner." bitfld.long 0x0 31. "DOM15_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 29.--30. "DOM15_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 28. "DOM15_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 27. "DOM14_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 25.--26. "DOM14_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" newline bitfld.long 0x0 24. "DOM14_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 23. "DOM13_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 21.--22. "DOM13_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 20. "DOM13_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 19. "DOM12_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" newline bitfld.long 0x0 17.--18. "DOM12_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM12_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 15. "DOM11_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 13.--14. "DOM11_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 12. "DOM11_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" newline bitfld.long 0x0 11. "DOM10_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 9.--10. "DOM10_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM10_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 7. "DOM9_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 5.--6. "DOM9_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" newline bitfld.long 0x0 4. "DOM9_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 3. "DOM8_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 1.--2. "DOM8_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM8_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" repeat.end repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x38 0x70 0xA8 0xE0 0x118 0x150 0x188 0x1C0 0x1F8 0x230 0x268 0x2A0 0x2D8 0x310 0x348 ) group.long ($2+0x310C)++0x3 line.long 0x0 "RGN_SEC_PER0_$1,This register is only used for resource manager to control secure access permission." bitfld.long 0x0 31. "DOM3_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM3_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM3_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM3_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM2_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM2_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM2_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM2_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM1_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM1_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM1_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM1_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM0_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM0_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM0_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM0_SEC_EN,Domain secure permission control enable" "0,1" repeat.end repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x38 0x70 0xA8 0xE0 0x118 0x150 0x188 0x1C0 0x1F8 0x230 0x268 0x2A0 0x2D8 0x310 0x348 ) group.long ($2+0x3110)++0x3 line.long 0x0 "RGN_SEC_PER1_$1,This register is only used for resource manager to control secure access permission." bitfld.long 0x0 31. "DOM7_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM7_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM7_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM7_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM6_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM6_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM6_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM6_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM5_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM5_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM5_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM5_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM4_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM4_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM4_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM4_SEC_EN,Domain secure permission control enable" "0,1" repeat.end repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x38 0x70 0xA8 0xE0 0x118 0x150 0x188 0x1C0 0x1F8 0x230 0x268 0x2A0 0x2D8 0x310 0x348 ) group.long ($2+0x3114)++0x3 line.long 0x0 "RGN_SEC_PER2_$1,This register is only used for resource manager to control secure access permission." bitfld.long 0x0 31. "DOM11_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM11_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM11_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM11_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM10_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM10_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM10_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM10_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM9_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM9_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM9_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM9_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM8_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM8_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM8_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM8_SEC_EN,Domain secure permission control enable" "0,1" repeat.end repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x38 0x70 0xA8 0xE0 0x118 0x150 0x188 0x1C0 0x1F8 0x230 0x268 0x2A0 0x2D8 0x310 0x348 ) group.long ($2+0x3118)++0x3 line.long 0x0 "RGN_SEC_PER3_$1,This register is only used for resource manager to control secure access permission." bitfld.long 0x0 31. "DOM15_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM15_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM15_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM15_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM14_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM14_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM14_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM14_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM13_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM13_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM13_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM13_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM12_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM12_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM12_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM12_SEC_EN,Domain secure permission control enable" "0,1" repeat.end repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x38 0x70 0xA8 0xE0 0x118 0x150 0x188 0x1C0 0x1F8 0x230 0x268 0x2A0 0x2D8 0x310 0x348 ) group.long ($2+0x311C)++0x3 line.long 0x0 "RGN_PRI_PER0_$1,This register is only used for resource manager to control privileged access permission." bitfld.long 0x0 31. "DOM3_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM3_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM3_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM3_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM2_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM2_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM2_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM2_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM1_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM1_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM1_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM1_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM0_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM0_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM0_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM0_PRI_EN,Domain privileged permission control enable" "0,1" repeat.end repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x38 0x70 0xA8 0xE0 0x118 0x150 0x188 0x1C0 0x1F8 0x230 0x268 0x2A0 0x2D8 0x310 0x348 ) group.long ($2+0x3120)++0x3 line.long 0x0 "RGN_PRI_PER1_$1,This register is only used for resource manager to control privileged access permission." bitfld.long 0x0 31. "DOM7_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM7_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM7_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM7_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM6_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM6_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM6_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM6_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM5_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM5_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM5_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM5_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM4_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM4_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM4_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM4_PRI_EN,Domain privileged permission control enable" "0,1" repeat.end repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x38 0x70 0xA8 0xE0 0x118 0x150 0x188 0x1C0 0x1F8 0x230 0x268 0x2A0 0x2D8 0x310 0x348 ) group.long ($2+0x3124)++0x3 line.long 0x0 "RGN_PRI_PER2_$1,This register is only used for resource manager to control privileged access permission." bitfld.long 0x0 31. "DOM11_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM11_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM11_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM11_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM10_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM10_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM10_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM10_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM9_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM9_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM9_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM9_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM8_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM8_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM8_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM8_PRI_EN,Domain privileged permission control enable" "0,1" repeat.end repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x38 0x70 0xA8 0xE0 0x118 0x150 0x188 0x1C0 0x1F8 0x230 0x268 0x2A0 0x2D8 0x310 0x348 ) group.long ($2+0x3128)++0x3 line.long 0x0 "RGN_PRI_PER3_$1,This register is only used for resource manager to control privileged access permission." bitfld.long 0x0 31. "DOM15_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM15_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM15_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM15_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM14_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM14_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM14_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM14_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM13_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM13_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM13_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM13_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM12_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM12_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM12_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM12_PRI_EN,Domain privileged permission control enable" "0,1" repeat.end repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x38 0x70 0xA8 0xE0 0x118 0x150 0x188 0x1C0 0x1F8 0x230 0x268 0x2A0 0x2D8 0x310 0x348 ) group.long ($2+0x312C)++0x3 line.long 0x0 "RGN_DOM_SEC_PER_$1,This register is only used for domain master to control secure access permission. When the domain master write this register. it only changes the secure permission for itself. When the domain master read this register. it gets.." bitfld.long 0x0 7. "DOM_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" newline bitfld.long 0x0 0. "DOM_SEC_EN,Domain secure permission control enable" "0,1" repeat.end repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x38 0x70 0xA8 0xE0 0x118 0x150 0x188 0x1C0 0x1F8 0x230 0x268 0x2A0 0x2D8 0x310 0x348 ) group.long ($2+0x3130)++0x3 line.long 0x0 "RGN_DOM_PRI_PER_$1,This register is only used for domain master to control secure access permission. When the domain master write this register. it only changes the secure permission for itself. When the domain master read this register. it gets.." bitfld.long 0x0 7. "DOM_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" newline bitfld.long 0x0 0. "DOM_PRI_EN,Domain privileged permission control enable" "0,1" repeat.end repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x38 0x70 0xA8 0xE0 0x118 0x150 0x188 0x1C0 0x1F8 0x230 0x268 0x2A0 0x2D8 0x310 0x348 ) group.long ($2+0x3134)++0x3 line.long 0x0 "RGN_DOM_ASSIGN_$1,Use to assign domain for accessing DOM_SEC_PER and DOM_PRI_PER register. Only resource manager. group manager and domain owner can access this register. For write. group manager must write its owen domain ID. otherwise write accessing.." hexmask.long.byte 0x0 0.--3. 1. "DID,accessing DOM_SEC_PER and DOM_PRI_PER register" repeat.end tree.end tree "RPC_XPU_DISP_GLOBAL" base ad:0x36FFE000 repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x4 0x8 0xC 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C ) group.long ($2)++0x3 line.long 0x0 "REGG0_DOM_$1,Assign domain for CKGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1A 0x1B 0x1C 0x1D 0x1E 0x1F )(list 0x40 0x44 0x48 0x4C 0x50 0x54 0x58 0x5C 0x60 0x64 0x68 0x6C 0x70 0x74 0x78 0x7C ) group.long ($2)++0x3 line.long 0x0 "REGG0_DOM_$1,Assign domain for CKGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x20 0x21 0x22 0x23 0x24 0x25 0x26 0x27 0x28 0x29 0x2A 0x2B 0x2C 0x2D 0x2E 0x2F )(list 0x80 0x84 0x88 0x8C 0x90 0x94 0x98 0x9C 0xA0 0xA4 0xA8 0xAC 0xB0 0xB4 0xB8 0xBC ) group.long ($2)++0x3 line.long 0x0 "REGG0_DOM_$1,Assign domain for CKGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x30 0x31 0x32 0x33 0x34 0x35 0x36 0x37 0x38 0x39 0x3A 0x3B 0x3C 0x3D 0x3E 0x3F )(list 0xC0 0xC4 0xC8 0xCC 0xD0 0xD4 0xD8 0xDC 0xE0 0xE4 0xE8 0xEC 0xF0 0xF4 0xF8 0xFC ) group.long ($2)++0x3 line.long 0x0 "REGG0_DOM_$1,Assign domain for CKGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x40 0x41 0x42 0x43 0x44 0x45 0x46 0x47 0x48 0x49 0x4A 0x4B 0x4C 0x4D 0x4E 0x4F )(list 0x100 0x104 0x108 0x10C 0x110 0x114 0x118 0x11C 0x120 0x124 0x128 0x12C 0x130 0x134 0x138 0x13C ) group.long ($2)++0x3 line.long 0x0 "REGG0_DOM_$1,Assign domain for CKGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x50 0x51 0x52 0x53 0x54 0x55 0x56 0x57 0x58 0x59 0x5A 0x5B 0x5C 0x5D 0x5E 0x5F )(list 0x140 0x144 0x148 0x14C 0x150 0x154 0x158 0x15C 0x160 0x164 0x168 0x16C 0x170 0x174 0x178 0x17C ) group.long ($2)++0x3 line.long 0x0 "REGG0_DOM_$1,Assign domain for CKGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x60 0x61 0x62 0x63 0x64 0x65 0x66 0x67 0x68 0x69 0x6A 0x6B 0x6C 0x6D 0x6E 0x6F )(list 0x180 0x184 0x188 0x18C 0x190 0x194 0x198 0x19C 0x1A0 0x1A4 0x1A8 0x1AC 0x1B0 0x1B4 0x1B8 0x1BC ) group.long ($2)++0x3 line.long 0x0 "REGG0_DOM_$1,Assign domain for CKGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x70 0x71 0x72 0x73 0x74 0x75 0x76 0x77 0x78 0x79 0x7A 0x7B 0x7C 0x7D 0x7E 0x7F )(list 0x1C0 0x1C4 0x1C8 0x1CC 0x1D0 0x1D4 0x1D8 0x1DC 0x1E0 0x1E4 0x1E8 0x1EC 0x1F0 0x1F4 0x1F8 0x1FC ) group.long ($2)++0x3 line.long 0x0 "REGG0_DOM_$1,Assign domain for CKGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x80 0x81 0x82 0x83 0x84 0x85 0x86 0x87 0x88 0x89 0x8A 0x8B 0x8C 0x8D 0x8E 0x8F )(list 0x200 0x204 0x208 0x20C 0x210 0x214 0x218 0x21C 0x220 0x224 0x228 0x22C 0x230 0x234 0x238 0x23C ) group.long ($2)++0x3 line.long 0x0 "REGG0_DOM_$1,Assign domain for CKGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x90 0x91 0x92 0x93 0x94 0x95 0x96 0x97 0x98 0x99 0x9A 0x9B 0x9C 0x9D 0x9E 0x9F )(list 0x240 0x244 0x248 0x24C 0x250 0x254 0x258 0x25C 0x260 0x264 0x268 0x26C 0x270 0x274 0x278 0x27C ) group.long ($2)++0x3 line.long 0x0 "REGG0_DOM_$1,Assign domain for CKGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xA0 0xA1 0xA2 0xA3 0xA4 0xA5 0xA6 0xA7 0xA8 0xA9 0xAA 0xAB 0xAC 0xAD 0xAE 0xAF )(list 0x280 0x284 0x288 0x28C 0x290 0x294 0x298 0x29C 0x2A0 0x2A4 0x2A8 0x2AC 0x2B0 0x2B4 0x2B8 0x2BC ) group.long ($2)++0x3 line.long 0x0 "REGG0_DOM_$1,Assign domain for CKGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xB0 0xB1 0xB2 0xB3 0xB4 0xB5 0xB6 0xB7 0xB8 0xB9 0xBA 0xBB 0xBC 0xBD 0xBE 0xBF )(list 0x2C0 0x2C4 0x2C8 0x2CC 0x2D0 0x2D4 0x2D8 0x2DC 0x2E0 0x2E4 0x2E8 0x2EC 0x2F0 0x2F4 0x2F8 0x2FC ) group.long ($2)++0x3 line.long 0x0 "REGG0_DOM_$1,Assign domain for CKGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xC0 0xC1 0xC2 0xC3 0xC4 0xC5 0xC6 0xC7 0xC8 0xC9 0xCA 0xCB 0xCC 0xCD 0xCE 0xCF )(list 0x300 0x304 0x308 0x30C 0x310 0x314 0x318 0x31C 0x320 0x324 0x328 0x32C 0x330 0x334 0x338 0x33C ) group.long ($2)++0x3 line.long 0x0 "REGG0_DOM_$1,Assign domain for CKGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xD0 0xD1 0xD2 0xD3 0xD4 0xD5 0xD6 0xD7 0xD8 0xD9 0xDA 0xDB 0xDC 0xDD 0xDE 0xDF )(list 0x340 0x344 0x348 0x34C 0x350 0x354 0x358 0x35C 0x360 0x364 0x368 0x36C 0x370 0x374 0x378 0x37C ) group.long ($2)++0x3 line.long 0x0 "REGG0_DOM_$1,Assign domain for CKGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xE0 0xE1 0xE2 0xE3 0xE4 0xE5 0xE6 0xE7 0xE8 0xE9 0xEA 0xEB 0xEC 0xED 0xEE 0xEF )(list 0x380 0x384 0x388 0x38C 0x390 0x394 0x398 0x39C 0x3A0 0x3A4 0x3A8 0x3AC 0x3B0 0x3B4 0x3B8 0x3BC ) group.long ($2)++0x3 line.long 0x0 "REGG0_DOM_$1,Assign domain for CKGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xF0 0xF1 0xF2 0xF3 0xF4 0xF5 0xF6 0xF7 0xF8 0xF9 0xFA 0xFB 0xFC 0xFD 0xFE 0xFF )(list 0x3C0 0x3C4 0x3C8 0x3CC 0x3D0 0x3D4 0x3D8 0x3DC 0x3E0 0x3E4 0x3E8 0x3EC 0x3F0 0x3F4 0x3F8 0x3FC ) group.long ($2)++0x3 line.long 0x0 "REGG0_DOM_$1,Assign domain for CKGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x4 0x8 0xC 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C ) group.long ($2+0x400)++0x3 line.long 0x0 "REGG1_DOM_$1,Assign domain for CKGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1A 0x1B 0x1C 0x1D 0x1E 0x1F )(list 0x40 0x44 0x48 0x4C 0x50 0x54 0x58 0x5C 0x60 0x64 0x68 0x6C 0x70 0x74 0x78 0x7C ) group.long ($2+0x400)++0x3 line.long 0x0 "REGG1_DOM_$1,Assign domain for CKGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x20 0x21 0x22 0x23 0x24 0x25 0x26 0x27 0x28 0x29 0x2A 0x2B 0x2C 0x2D 0x2E 0x2F )(list 0x80 0x84 0x88 0x8C 0x90 0x94 0x98 0x9C 0xA0 0xA4 0xA8 0xAC 0xB0 0xB4 0xB8 0xBC ) group.long ($2+0x400)++0x3 line.long 0x0 "REGG1_DOM_$1,Assign domain for CKGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x30 0x31 0x32 0x33 0x34 0x35 0x36 0x37 0x38 0x39 0x3A 0x3B 0x3C 0x3D 0x3E 0x3F )(list 0xC0 0xC4 0xC8 0xCC 0xD0 0xD4 0xD8 0xDC 0xE0 0xE4 0xE8 0xEC 0xF0 0xF4 0xF8 0xFC ) group.long ($2+0x400)++0x3 line.long 0x0 "REGG1_DOM_$1,Assign domain for CKGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x40 0x41 0x42 0x43 0x44 0x45 0x46 0x47 0x48 0x49 0x4A 0x4B 0x4C 0x4D 0x4E 0x4F )(list 0x100 0x104 0x108 0x10C 0x110 0x114 0x118 0x11C 0x120 0x124 0x128 0x12C 0x130 0x134 0x138 0x13C ) group.long ($2+0x400)++0x3 line.long 0x0 "REGG1_DOM_$1,Assign domain for CKGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x50 0x51 0x52 0x53 0x54 0x55 0x56 0x57 0x58 0x59 0x5A 0x5B 0x5C 0x5D 0x5E 0x5F )(list 0x140 0x144 0x148 0x14C 0x150 0x154 0x158 0x15C 0x160 0x164 0x168 0x16C 0x170 0x174 0x178 0x17C ) group.long ($2+0x400)++0x3 line.long 0x0 "REGG1_DOM_$1,Assign domain for CKGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x60 0x61 0x62 0x63 0x64 0x65 0x66 0x67 0x68 0x69 0x6A 0x6B 0x6C 0x6D 0x6E 0x6F )(list 0x180 0x184 0x188 0x18C 0x190 0x194 0x198 0x19C 0x1A0 0x1A4 0x1A8 0x1AC 0x1B0 0x1B4 0x1B8 0x1BC ) group.long ($2+0x400)++0x3 line.long 0x0 "REGG1_DOM_$1,Assign domain for CKGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x70 0x71 0x72 0x73 0x74 0x75 0x76 0x77 0x78 0x79 0x7A 0x7B 0x7C 0x7D 0x7E 0x7F )(list 0x1C0 0x1C4 0x1C8 0x1CC 0x1D0 0x1D4 0x1D8 0x1DC 0x1E0 0x1E4 0x1E8 0x1EC 0x1F0 0x1F4 0x1F8 0x1FC ) group.long ($2+0x400)++0x3 line.long 0x0 "REGG1_DOM_$1,Assign domain for CKGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x80 0x81 0x82 0x83 0x84 0x85 0x86 0x87 0x88 0x89 0x8A 0x8B 0x8C 0x8D 0x8E 0x8F )(list 0x200 0x204 0x208 0x20C 0x210 0x214 0x218 0x21C 0x220 0x224 0x228 0x22C 0x230 0x234 0x238 0x23C ) group.long ($2+0x400)++0x3 line.long 0x0 "REGG1_DOM_$1,Assign domain for CKGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x90 0x91 0x92 0x93 0x94 0x95 0x96 0x97 0x98 0x99 0x9A 0x9B 0x9C 0x9D 0x9E 0x9F )(list 0x240 0x244 0x248 0x24C 0x250 0x254 0x258 0x25C 0x260 0x264 0x268 0x26C 0x270 0x274 0x278 0x27C ) group.long ($2+0x400)++0x3 line.long 0x0 "REGG1_DOM_$1,Assign domain for CKGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xA0 0xA1 0xA2 0xA3 0xA4 0xA5 0xA6 0xA7 0xA8 0xA9 0xAA 0xAB 0xAC 0xAD 0xAE 0xAF )(list 0x280 0x284 0x288 0x28C 0x290 0x294 0x298 0x29C 0x2A0 0x2A4 0x2A8 0x2AC 0x2B0 0x2B4 0x2B8 0x2BC ) group.long ($2+0x400)++0x3 line.long 0x0 "REGG1_DOM_$1,Assign domain for CKGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xB0 0xB1 0xB2 0xB3 0xB4 0xB5 0xB6 0xB7 0xB8 0xB9 0xBA 0xBB 0xBC 0xBD 0xBE 0xBF )(list 0x2C0 0x2C4 0x2C8 0x2CC 0x2D0 0x2D4 0x2D8 0x2DC 0x2E0 0x2E4 0x2E8 0x2EC 0x2F0 0x2F4 0x2F8 0x2FC ) group.long ($2+0x400)++0x3 line.long 0x0 "REGG1_DOM_$1,Assign domain for CKGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xC0 0xC1 0xC2 0xC3 0xC4 0xC5 0xC6 0xC7 0xC8 0xC9 0xCA 0xCB 0xCC 0xCD 0xCE 0xCF )(list 0x300 0x304 0x308 0x30C 0x310 0x314 0x318 0x31C 0x320 0x324 0x328 0x32C 0x330 0x334 0x338 0x33C ) group.long ($2+0x400)++0x3 line.long 0x0 "REGG1_DOM_$1,Assign domain for CKGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xD0 0xD1 0xD2 0xD3 0xD4 0xD5 0xD6 0xD7 0xD8 0xD9 0xDA 0xDB 0xDC 0xDD 0xDE 0xDF )(list 0x340 0x344 0x348 0x34C 0x350 0x354 0x358 0x35C 0x360 0x364 0x368 0x36C 0x370 0x374 0x378 0x37C ) group.long ($2+0x400)++0x3 line.long 0x0 "REGG1_DOM_$1,Assign domain for CKGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xE0 0xE1 0xE2 0xE3 0xE4 0xE5 0xE6 0xE7 0xE8 0xE9 0xEA 0xEB 0xEC 0xED 0xEE 0xEF )(list 0x380 0x384 0x388 0x38C 0x390 0x394 0x398 0x39C 0x3A0 0x3A4 0x3A8 0x3AC 0x3B0 0x3B4 0x3B8 0x3BC ) group.long ($2+0x400)++0x3 line.long 0x0 "REGG1_DOM_$1,Assign domain for CKGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xF0 0xF1 0xF2 0xF3 0xF4 0xF5 0xF6 0xF7 0xF8 0xF9 0xFA 0xFB 0xFC 0xFD 0xFE 0xFF )(list 0x3C0 0x3C4 0x3C8 0x3CC 0x3D0 0x3D4 0x3D8 0x3DC 0x3E0 0x3E4 0x3E8 0x3EC 0x3F0 0x3F4 0x3F8 0x3FC ) group.long ($2+0x400)++0x3 line.long 0x0 "REGG1_DOM_$1,Assign domain for CKGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x4 0x8 0xC 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C ) group.long ($2+0x800)++0x3 line.long 0x0 "REGG2_DOM_$1,Assign domain for SCR registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1A 0x1B 0x1C 0x1D 0x1E 0x1F )(list 0x40 0x44 0x48 0x4C 0x50 0x54 0x58 0x5C 0x60 0x64 0x68 0x6C 0x70 0x74 0x78 0x7C ) group.long ($2+0x800)++0x3 line.long 0x0 "REGG2_DOM_$1,Assign domain for SCR registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x20 0x21 0x22 0x23 0x24 0x25 0x26 0x27 0x28 0x29 0x2A 0x2B 0x2C 0x2D 0x2E 0x2F )(list 0x80 0x84 0x88 0x8C 0x90 0x94 0x98 0x9C 0xA0 0xA4 0xA8 0xAC 0xB0 0xB4 0xB8 0xBC ) group.long ($2+0x800)++0x3 line.long 0x0 "REGG2_DOM_$1,Assign domain for SCR registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x30 0x31 0x32 0x33 0x34 0x35 0x36 0x37 0x38 0x39 0x3A 0x3B 0x3C 0x3D 0x3E 0x3F )(list 0xC0 0xC4 0xC8 0xCC 0xD0 0xD4 0xD8 0xDC 0xE0 0xE4 0xE8 0xEC 0xF0 0xF4 0xF8 0xFC ) group.long ($2+0x800)++0x3 line.long 0x0 "REGG2_DOM_$1,Assign domain for SCR registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x40 0x41 0x42 0x43 0x44 0x45 0x46 0x47 0x48 0x49 0x4A 0x4B 0x4C 0x4D 0x4E 0x4F )(list 0x100 0x104 0x108 0x10C 0x110 0x114 0x118 0x11C 0x120 0x124 0x128 0x12C 0x130 0x134 0x138 0x13C ) group.long ($2+0x800)++0x3 line.long 0x0 "REGG2_DOM_$1,Assign domain for SCR registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x50 0x51 0x52 0x53 0x54 0x55 0x56 0x57 0x58 0x59 0x5A 0x5B 0x5C 0x5D 0x5E 0x5F )(list 0x140 0x144 0x148 0x14C 0x150 0x154 0x158 0x15C 0x160 0x164 0x168 0x16C 0x170 0x174 0x178 0x17C ) group.long ($2+0x800)++0x3 line.long 0x0 "REGG2_DOM_$1,Assign domain for SCR registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x60 0x61 0x62 0x63 0x64 0x65 0x66 0x67 0x68 0x69 0x6A 0x6B 0x6C 0x6D 0x6E 0x6F )(list 0x180 0x184 0x188 0x18C 0x190 0x194 0x198 0x19C 0x1A0 0x1A4 0x1A8 0x1AC 0x1B0 0x1B4 0x1B8 0x1BC ) group.long ($2+0x800)++0x3 line.long 0x0 "REGG2_DOM_$1,Assign domain for SCR registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x70 0x71 0x72 0x73 0x74 0x75 0x76 0x77 0x78 0x79 0x7A 0x7B 0x7C 0x7D 0x7E 0x7F )(list 0x1C0 0x1C4 0x1C8 0x1CC 0x1D0 0x1D4 0x1D8 0x1DC 0x1E0 0x1E4 0x1E8 0x1EC 0x1F0 0x1F4 0x1F8 0x1FC ) group.long ($2+0x800)++0x3 line.long 0x0 "REGG2_DOM_$1,Assign domain for SCR registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x80 0x81 0x82 0x83 0x84 0x85 0x86 0x87 0x88 0x89 0x8A 0x8B 0x8C 0x8D 0x8E 0x8F )(list 0x200 0x204 0x208 0x20C 0x210 0x214 0x218 0x21C 0x220 0x224 0x228 0x22C 0x230 0x234 0x238 0x23C ) group.long ($2+0x800)++0x3 line.long 0x0 "REGG2_DOM_$1,Assign domain for SCR registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x90 0x91 0x92 0x93 0x94 0x95 0x96 0x97 0x98 0x99 0x9A 0x9B 0x9C 0x9D 0x9E 0x9F )(list 0x240 0x244 0x248 0x24C 0x250 0x254 0x258 0x25C 0x260 0x264 0x268 0x26C 0x270 0x274 0x278 0x27C ) group.long ($2+0x800)++0x3 line.long 0x0 "REGG2_DOM_$1,Assign domain for SCR registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xA0 0xA1 0xA2 0xA3 0xA4 0xA5 0xA6 0xA7 0xA8 0xA9 0xAA 0xAB 0xAC 0xAD 0xAE 0xAF )(list 0x280 0x284 0x288 0x28C 0x290 0x294 0x298 0x29C 0x2A0 0x2A4 0x2A8 0x2AC 0x2B0 0x2B4 0x2B8 0x2BC ) group.long ($2+0x800)++0x3 line.long 0x0 "REGG2_DOM_$1,Assign domain for SCR registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xB0 0xB1 0xB2 0xB3 0xB4 0xB5 0xB6 0xB7 0xB8 0xB9 0xBA 0xBB 0xBC 0xBD 0xBE 0xBF )(list 0x2C0 0x2C4 0x2C8 0x2CC 0x2D0 0x2D4 0x2D8 0x2DC 0x2E0 0x2E4 0x2E8 0x2EC 0x2F0 0x2F4 0x2F8 0x2FC ) group.long ($2+0x800)++0x3 line.long 0x0 "REGG2_DOM_$1,Assign domain for SCR registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xC0 0xC1 0xC2 0xC3 0xC4 0xC5 0xC6 0xC7 0xC8 0xC9 0xCA 0xCB 0xCC 0xCD 0xCE 0xCF )(list 0x300 0x304 0x308 0x30C 0x310 0x314 0x318 0x31C 0x320 0x324 0x328 0x32C 0x330 0x334 0x338 0x33C ) group.long ($2+0x800)++0x3 line.long 0x0 "REGG2_DOM_$1,Assign domain for SCR registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xD0 0xD1 0xD2 0xD3 0xD4 0xD5 0xD6 0xD7 0xD8 0xD9 0xDA 0xDB 0xDC 0xDD 0xDE 0xDF )(list 0x340 0x344 0x348 0x34C 0x350 0x354 0x358 0x35C 0x360 0x364 0x368 0x36C 0x370 0x374 0x378 0x37C ) group.long ($2+0x800)++0x3 line.long 0x0 "REGG2_DOM_$1,Assign domain for SCR registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xE0 0xE1 0xE2 0xE3 0xE4 0xE5 0xE6 0xE7 0xE8 0xE9 0xEA 0xEB 0xEC 0xED 0xEE 0xEF )(list 0x380 0x384 0x388 0x38C 0x390 0x394 0x398 0x39C 0x3A0 0x3A4 0x3A8 0x3AC 0x3B0 0x3B4 0x3B8 0x3BC ) group.long ($2+0x800)++0x3 line.long 0x0 "REGG2_DOM_$1,Assign domain for SCR registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xF0 0xF1 0xF2 0xF3 0xF4 0xF5 0xF6 0xF7 0xF8 0xF9 0xFA 0xFB 0xFC 0xFD 0xFE 0xFF )(list 0x3C0 0x3C4 0x3C8 0x3CC 0x3D0 0x3D4 0x3D8 0x3DC 0x3E0 0x3E4 0x3E8 0x3EC 0x3F0 0x3F4 0x3F8 0x3FC ) group.long ($2+0x800)++0x3 line.long 0x0 "REGG2_DOM_$1,Assign domain for SCR registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x4 0x8 0xC 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C ) group.long ($2+0xC00)++0x3 line.long 0x0 "REGG3_DOM_$1,Assign domain for SCR registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1A 0x1B 0x1C 0x1D 0x1E 0x1F )(list 0x40 0x44 0x48 0x4C 0x50 0x54 0x58 0x5C 0x60 0x64 0x68 0x6C 0x70 0x74 0x78 0x7C ) group.long ($2+0xC00)++0x3 line.long 0x0 "REGG3_DOM_$1,Assign domain for SCR registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x20 0x21 0x22 0x23 0x24 0x25 0x26 0x27 0x28 0x29 0x2A 0x2B 0x2C 0x2D 0x2E 0x2F )(list 0x80 0x84 0x88 0x8C 0x90 0x94 0x98 0x9C 0xA0 0xA4 0xA8 0xAC 0xB0 0xB4 0xB8 0xBC ) group.long ($2+0xC00)++0x3 line.long 0x0 "REGG3_DOM_$1,Assign domain for SCR registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x30 0x31 0x32 0x33 0x34 0x35 0x36 0x37 0x38 0x39 0x3A 0x3B 0x3C 0x3D 0x3E 0x3F )(list 0xC0 0xC4 0xC8 0xCC 0xD0 0xD4 0xD8 0xDC 0xE0 0xE4 0xE8 0xEC 0xF0 0xF4 0xF8 0xFC ) group.long ($2+0xC00)++0x3 line.long 0x0 "REGG3_DOM_$1,Assign domain for SCR registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x40 0x41 0x42 0x43 0x44 0x45 0x46 0x47 0x48 0x49 0x4A 0x4B 0x4C 0x4D 0x4E 0x4F )(list 0x100 0x104 0x108 0x10C 0x110 0x114 0x118 0x11C 0x120 0x124 0x128 0x12C 0x130 0x134 0x138 0x13C ) group.long ($2+0xC00)++0x3 line.long 0x0 "REGG3_DOM_$1,Assign domain for SCR registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x50 0x51 0x52 0x53 0x54 0x55 0x56 0x57 0x58 0x59 0x5A 0x5B 0x5C 0x5D 0x5E 0x5F )(list 0x140 0x144 0x148 0x14C 0x150 0x154 0x158 0x15C 0x160 0x164 0x168 0x16C 0x170 0x174 0x178 0x17C ) group.long ($2+0xC00)++0x3 line.long 0x0 "REGG3_DOM_$1,Assign domain for SCR registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x60 0x61 0x62 0x63 0x64 0x65 0x66 0x67 0x68 0x69 0x6A 0x6B 0x6C 0x6D 0x6E 0x6F )(list 0x180 0x184 0x188 0x18C 0x190 0x194 0x198 0x19C 0x1A0 0x1A4 0x1A8 0x1AC 0x1B0 0x1B4 0x1B8 0x1BC ) group.long ($2+0xC00)++0x3 line.long 0x0 "REGG3_DOM_$1,Assign domain for SCR registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x70 0x71 0x72 0x73 0x74 0x75 0x76 0x77 0x78 0x79 0x7A 0x7B 0x7C 0x7D 0x7E 0x7F )(list 0x1C0 0x1C4 0x1C8 0x1CC 0x1D0 0x1D4 0x1D8 0x1DC 0x1E0 0x1E4 0x1E8 0x1EC 0x1F0 0x1F4 0x1F8 0x1FC ) group.long ($2+0xC00)++0x3 line.long 0x0 "REGG3_DOM_$1,Assign domain for SCR registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x80 0x81 0x82 0x83 0x84 0x85 0x86 0x87 0x88 0x89 0x8A 0x8B 0x8C 0x8D 0x8E 0x8F )(list 0x200 0x204 0x208 0x20C 0x210 0x214 0x218 0x21C 0x220 0x224 0x228 0x22C 0x230 0x234 0x238 0x23C ) group.long ($2+0xC00)++0x3 line.long 0x0 "REGG3_DOM_$1,Assign domain for SCR registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x90 0x91 0x92 0x93 0x94 0x95 0x96 0x97 0x98 0x99 0x9A 0x9B 0x9C 0x9D 0x9E 0x9F )(list 0x240 0x244 0x248 0x24C 0x250 0x254 0x258 0x25C 0x260 0x264 0x268 0x26C 0x270 0x274 0x278 0x27C ) group.long ($2+0xC00)++0x3 line.long 0x0 "REGG3_DOM_$1,Assign domain for SCR registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xA0 0xA1 0xA2 0xA3 0xA4 0xA5 0xA6 0xA7 0xA8 0xA9 0xAA 0xAB 0xAC 0xAD 0xAE 0xAF )(list 0x280 0x284 0x288 0x28C 0x290 0x294 0x298 0x29C 0x2A0 0x2A4 0x2A8 0x2AC 0x2B0 0x2B4 0x2B8 0x2BC ) group.long ($2+0xC00)++0x3 line.long 0x0 "REGG3_DOM_$1,Assign domain for SCR registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xB0 0xB1 0xB2 0xB3 0xB4 0xB5 0xB6 0xB7 0xB8 0xB9 0xBA 0xBB 0xBC 0xBD 0xBE 0xBF )(list 0x2C0 0x2C4 0x2C8 0x2CC 0x2D0 0x2D4 0x2D8 0x2DC 0x2E0 0x2E4 0x2E8 0x2EC 0x2F0 0x2F4 0x2F8 0x2FC ) group.long ($2+0xC00)++0x3 line.long 0x0 "REGG3_DOM_$1,Assign domain for SCR registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xC0 0xC1 0xC2 0xC3 0xC4 0xC5 0xC6 0xC7 0xC8 0xC9 0xCA 0xCB 0xCC 0xCD 0xCE 0xCF )(list 0x300 0x304 0x308 0x30C 0x310 0x314 0x318 0x31C 0x320 0x324 0x328 0x32C 0x330 0x334 0x338 0x33C ) group.long ($2+0xC00)++0x3 line.long 0x0 "REGG3_DOM_$1,Assign domain for SCR registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xD0 0xD1 0xD2 0xD3 0xD4 0xD5 0xD6 0xD7 0xD8 0xD9 0xDA 0xDB 0xDC 0xDD 0xDE 0xDF )(list 0x340 0x344 0x348 0x34C 0x350 0x354 0x358 0x35C 0x360 0x364 0x368 0x36C 0x370 0x374 0x378 0x37C ) group.long ($2+0xC00)++0x3 line.long 0x0 "REGG3_DOM_$1,Assign domain for SCR registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xE0 0xE1 0xE2 0xE3 0xE4 0xE5 0xE6 0xE7 0xE8 0xE9 0xEA 0xEB 0xEC 0xED 0xEE 0xEF )(list 0x380 0x384 0x388 0x38C 0x390 0x394 0x398 0x39C 0x3A0 0x3A4 0x3A8 0x3AC 0x3B0 0x3B4 0x3B8 0x3BC ) group.long ($2+0xC00)++0x3 line.long 0x0 "REGG3_DOM_$1,Assign domain for SCR registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xF0 0xF1 0xF2 0xF3 0xF4 0xF5 0xF6 0xF7 0xF8 0xF9 0xFA 0xFB 0xFC 0xFD 0xFE 0xFF )(list 0x3C0 0x3C4 0x3C8 0x3CC 0x3D0 0x3D4 0x3D8 0x3DC 0x3E0 0x3E4 0x3E8 0x3EC 0x3F0 0x3F4 0x3F8 0x3FC ) group.long ($2+0xC00)++0x3 line.long 0x0 "REGG3_DOM_$1,Assign domain for SCR registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x4 0x8 0xC 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C ) group.long ($2+0x1000)++0x3 line.long 0x0 "REGG4_DOM_$1,Assign domain for RSTGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1A 0x1B 0x1C 0x1D 0x1E 0x1F )(list 0x40 0x44 0x48 0x4C 0x50 0x54 0x58 0x5C 0x60 0x64 0x68 0x6C 0x70 0x74 0x78 0x7C ) group.long ($2+0x1000)++0x3 line.long 0x0 "REGG4_DOM_$1,Assign domain for RSTGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x20 0x21 0x22 0x23 0x24 0x25 0x26 0x27 0x28 0x29 0x2A 0x2B 0x2C 0x2D 0x2E 0x2F )(list 0x80 0x84 0x88 0x8C 0x90 0x94 0x98 0x9C 0xA0 0xA4 0xA8 0xAC 0xB0 0xB4 0xB8 0xBC ) group.long ($2+0x1000)++0x3 line.long 0x0 "REGG4_DOM_$1,Assign domain for RSTGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x30 0x31 0x32 0x33 0x34 0x35 0x36 0x37 0x38 0x39 0x3A 0x3B 0x3C 0x3D 0x3E 0x3F )(list 0xC0 0xC4 0xC8 0xCC 0xD0 0xD4 0xD8 0xDC 0xE0 0xE4 0xE8 0xEC 0xF0 0xF4 0xF8 0xFC ) group.long ($2+0x1000)++0x3 line.long 0x0 "REGG4_DOM_$1,Assign domain for RSTGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x40 0x41 0x42 0x43 0x44 0x45 0x46 0x47 0x48 0x49 0x4A 0x4B 0x4C 0x4D 0x4E 0x4F )(list 0x100 0x104 0x108 0x10C 0x110 0x114 0x118 0x11C 0x120 0x124 0x128 0x12C 0x130 0x134 0x138 0x13C ) group.long ($2+0x1000)++0x3 line.long 0x0 "REGG4_DOM_$1,Assign domain for RSTGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x50 0x51 0x52 0x53 0x54 0x55 0x56 0x57 0x58 0x59 0x5A 0x5B 0x5C 0x5D 0x5E 0x5F )(list 0x140 0x144 0x148 0x14C 0x150 0x154 0x158 0x15C 0x160 0x164 0x168 0x16C 0x170 0x174 0x178 0x17C ) group.long ($2+0x1000)++0x3 line.long 0x0 "REGG4_DOM_$1,Assign domain for RSTGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x60 0x61 0x62 0x63 0x64 0x65 0x66 0x67 0x68 0x69 0x6A 0x6B 0x6C 0x6D 0x6E 0x6F )(list 0x180 0x184 0x188 0x18C 0x190 0x194 0x198 0x19C 0x1A0 0x1A4 0x1A8 0x1AC 0x1B0 0x1B4 0x1B8 0x1BC ) group.long ($2+0x1000)++0x3 line.long 0x0 "REGG4_DOM_$1,Assign domain for RSTGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x70 0x71 0x72 0x73 0x74 0x75 0x76 0x77 0x78 0x79 0x7A 0x7B 0x7C 0x7D 0x7E 0x7F )(list 0x1C0 0x1C4 0x1C8 0x1CC 0x1D0 0x1D4 0x1D8 0x1DC 0x1E0 0x1E4 0x1E8 0x1EC 0x1F0 0x1F4 0x1F8 0x1FC ) group.long ($2+0x1000)++0x3 line.long 0x0 "REGG4_DOM_$1,Assign domain for RSTGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x80 0x81 0x82 0x83 0x84 0x85 0x86 0x87 0x88 0x89 0x8A 0x8B 0x8C 0x8D 0x8E 0x8F )(list 0x200 0x204 0x208 0x20C 0x210 0x214 0x218 0x21C 0x220 0x224 0x228 0x22C 0x230 0x234 0x238 0x23C ) group.long ($2+0x1000)++0x3 line.long 0x0 "REGG4_DOM_$1,Assign domain for RSTGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x90 0x91 0x92 0x93 0x94 0x95 0x96 0x97 0x98 0x99 0x9A 0x9B 0x9C 0x9D 0x9E 0x9F )(list 0x240 0x244 0x248 0x24C 0x250 0x254 0x258 0x25C 0x260 0x264 0x268 0x26C 0x270 0x274 0x278 0x27C ) group.long ($2+0x1000)++0x3 line.long 0x0 "REGG4_DOM_$1,Assign domain for RSTGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xA0 0xA1 0xA2 0xA3 0xA4 0xA5 0xA6 0xA7 0xA8 0xA9 0xAA 0xAB 0xAC 0xAD 0xAE 0xAF )(list 0x280 0x284 0x288 0x28C 0x290 0x294 0x298 0x29C 0x2A0 0x2A4 0x2A8 0x2AC 0x2B0 0x2B4 0x2B8 0x2BC ) group.long ($2+0x1000)++0x3 line.long 0x0 "REGG4_DOM_$1,Assign domain for RSTGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xB0 0xB1 0xB2 0xB3 0xB4 0xB5 0xB6 0xB7 0xB8 0xB9 0xBA 0xBB 0xBC 0xBD 0xBE 0xBF )(list 0x2C0 0x2C4 0x2C8 0x2CC 0x2D0 0x2D4 0x2D8 0x2DC 0x2E0 0x2E4 0x2E8 0x2EC 0x2F0 0x2F4 0x2F8 0x2FC ) group.long ($2+0x1000)++0x3 line.long 0x0 "REGG4_DOM_$1,Assign domain for RSTGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xC0 0xC1 0xC2 0xC3 0xC4 0xC5 0xC6 0xC7 0xC8 0xC9 0xCA 0xCB 0xCC 0xCD 0xCE 0xCF )(list 0x300 0x304 0x308 0x30C 0x310 0x314 0x318 0x31C 0x320 0x324 0x328 0x32C 0x330 0x334 0x338 0x33C ) group.long ($2+0x1000)++0x3 line.long 0x0 "REGG4_DOM_$1,Assign domain for RSTGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xD0 0xD1 0xD2 0xD3 0xD4 0xD5 0xD6 0xD7 0xD8 0xD9 0xDA 0xDB 0xDC 0xDD 0xDE 0xDF )(list 0x340 0x344 0x348 0x34C 0x350 0x354 0x358 0x35C 0x360 0x364 0x368 0x36C 0x370 0x374 0x378 0x37C ) group.long ($2+0x1000)++0x3 line.long 0x0 "REGG4_DOM_$1,Assign domain for RSTGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xE0 0xE1 0xE2 0xE3 0xE4 0xE5 0xE6 0xE7 0xE8 0xE9 0xEA 0xEB 0xEC 0xED 0xEE 0xEF )(list 0x380 0x384 0x388 0x38C 0x390 0x394 0x398 0x39C 0x3A0 0x3A4 0x3A8 0x3AC 0x3B0 0x3B4 0x3B8 0x3BC ) group.long ($2+0x1000)++0x3 line.long 0x0 "REGG4_DOM_$1,Assign domain for RSTGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xF0 0xF1 0xF2 0xF3 0xF4 0xF5 0xF6 0xF7 0xF8 0xF9 0xFA 0xFB 0xFC 0xFD 0xFE 0xFF )(list 0x3C0 0x3C4 0x3C8 0x3CC 0x3D0 0x3D4 0x3D8 0x3DC 0x3E0 0x3E4 0x3E8 0x3EC 0x3F0 0x3F4 0x3F8 0x3FC ) group.long ($2+0x1000)++0x3 line.long 0x0 "REGG4_DOM_$1,Assign domain for RSTGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x4 0x8 0xC 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C ) group.long ($2+0x1400)++0x3 line.long 0x0 "REGG5_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1A 0x1B 0x1C 0x1D 0x1E 0x1F )(list 0x40 0x44 0x48 0x4C 0x50 0x54 0x58 0x5C 0x60 0x64 0x68 0x6C 0x70 0x74 0x78 0x7C ) group.long ($2+0x1400)++0x3 line.long 0x0 "REGG5_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x20 0x21 0x22 0x23 0x24 0x25 0x26 0x27 0x28 0x29 0x2A 0x2B 0x2C 0x2D 0x2E 0x2F )(list 0x80 0x84 0x88 0x8C 0x90 0x94 0x98 0x9C 0xA0 0xA4 0xA8 0xAC 0xB0 0xB4 0xB8 0xBC ) group.long ($2+0x1400)++0x3 line.long 0x0 "REGG5_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x30 0x31 0x32 0x33 0x34 0x35 0x36 0x37 0x38 0x39 0x3A 0x3B 0x3C 0x3D 0x3E 0x3F )(list 0xC0 0xC4 0xC8 0xCC 0xD0 0xD4 0xD8 0xDC 0xE0 0xE4 0xE8 0xEC 0xF0 0xF4 0xF8 0xFC ) group.long ($2+0x1400)++0x3 line.long 0x0 "REGG5_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x40 0x41 0x42 0x43 0x44 0x45 0x46 0x47 0x48 0x49 0x4A 0x4B 0x4C 0x4D 0x4E 0x4F )(list 0x100 0x104 0x108 0x10C 0x110 0x114 0x118 0x11C 0x120 0x124 0x128 0x12C 0x130 0x134 0x138 0x13C ) group.long ($2+0x1400)++0x3 line.long 0x0 "REGG5_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x50 0x51 0x52 0x53 0x54 0x55 0x56 0x57 0x58 0x59 0x5A 0x5B 0x5C 0x5D 0x5E 0x5F )(list 0x140 0x144 0x148 0x14C 0x150 0x154 0x158 0x15C 0x160 0x164 0x168 0x16C 0x170 0x174 0x178 0x17C ) group.long ($2+0x1400)++0x3 line.long 0x0 "REGG5_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x60 0x61 0x62 0x63 0x64 0x65 0x66 0x67 0x68 0x69 0x6A 0x6B 0x6C 0x6D 0x6E 0x6F )(list 0x180 0x184 0x188 0x18C 0x190 0x194 0x198 0x19C 0x1A0 0x1A4 0x1A8 0x1AC 0x1B0 0x1B4 0x1B8 0x1BC ) group.long ($2+0x1400)++0x3 line.long 0x0 "REGG5_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x70 0x71 0x72 0x73 0x74 0x75 0x76 0x77 0x78 0x79 0x7A 0x7B 0x7C 0x7D 0x7E 0x7F )(list 0x1C0 0x1C4 0x1C8 0x1CC 0x1D0 0x1D4 0x1D8 0x1DC 0x1E0 0x1E4 0x1E8 0x1EC 0x1F0 0x1F4 0x1F8 0x1FC ) group.long ($2+0x1400)++0x3 line.long 0x0 "REGG5_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x80 0x81 0x82 0x83 0x84 0x85 0x86 0x87 0x88 0x89 0x8A 0x8B 0x8C 0x8D 0x8E 0x8F )(list 0x200 0x204 0x208 0x20C 0x210 0x214 0x218 0x21C 0x220 0x224 0x228 0x22C 0x230 0x234 0x238 0x23C ) group.long ($2+0x1400)++0x3 line.long 0x0 "REGG5_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x90 0x91 0x92 0x93 0x94 0x95 0x96 0x97 0x98 0x99 0x9A 0x9B 0x9C 0x9D 0x9E 0x9F )(list 0x240 0x244 0x248 0x24C 0x250 0x254 0x258 0x25C 0x260 0x264 0x268 0x26C 0x270 0x274 0x278 0x27C ) group.long ($2+0x1400)++0x3 line.long 0x0 "REGG5_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xA0 0xA1 0xA2 0xA3 0xA4 0xA5 0xA6 0xA7 0xA8 0xA9 0xAA 0xAB 0xAC 0xAD 0xAE 0xAF )(list 0x280 0x284 0x288 0x28C 0x290 0x294 0x298 0x29C 0x2A0 0x2A4 0x2A8 0x2AC 0x2B0 0x2B4 0x2B8 0x2BC ) group.long ($2+0x1400)++0x3 line.long 0x0 "REGG5_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xB0 0xB1 0xB2 0xB3 0xB4 0xB5 0xB6 0xB7 0xB8 0xB9 0xBA 0xBB 0xBC 0xBD 0xBE 0xBF )(list 0x2C0 0x2C4 0x2C8 0x2CC 0x2D0 0x2D4 0x2D8 0x2DC 0x2E0 0x2E4 0x2E8 0x2EC 0x2F0 0x2F4 0x2F8 0x2FC ) group.long ($2+0x1400)++0x3 line.long 0x0 "REGG5_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xC0 0xC1 0xC2 0xC3 0xC4 0xC5 0xC6 0xC7 0xC8 0xC9 0xCA 0xCB 0xCC 0xCD 0xCE 0xCF )(list 0x300 0x304 0x308 0x30C 0x310 0x314 0x318 0x31C 0x320 0x324 0x328 0x32C 0x330 0x334 0x338 0x33C ) group.long ($2+0x1400)++0x3 line.long 0x0 "REGG5_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xD0 0xD1 0xD2 0xD3 0xD4 0xD5 0xD6 0xD7 0xD8 0xD9 0xDA 0xDB 0xDC 0xDD 0xDE 0xDF )(list 0x340 0x344 0x348 0x34C 0x350 0x354 0x358 0x35C 0x360 0x364 0x368 0x36C 0x370 0x374 0x378 0x37C ) group.long ($2+0x1400)++0x3 line.long 0x0 "REGG5_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xE0 0xE1 0xE2 0xE3 0xE4 0xE5 0xE6 0xE7 0xE8 0xE9 0xEA 0xEB 0xEC 0xED 0xEE 0xEF )(list 0x380 0x384 0x388 0x38C 0x390 0x394 0x398 0x39C 0x3A0 0x3A4 0x3A8 0x3AC 0x3B0 0x3B4 0x3B8 0x3BC ) group.long ($2+0x1400)++0x3 line.long 0x0 "REGG5_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xF0 0xF1 0xF2 0xF3 0xF4 0xF5 0xF6 0xF7 0xF8 0xF9 0xFA 0xFB 0xFC 0xFD 0xFE 0xFF )(list 0x3C0 0x3C4 0x3C8 0x3CC 0x3D0 0x3D4 0x3D8 0x3DC 0x3E0 0x3E4 0x3E8 0x3EC 0x3F0 0x3F4 0x3F8 0x3FC ) group.long ($2+0x1400)++0x3 line.long 0x0 "REGG5_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x4 0x8 0xC 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C ) group.long ($2+0x1800)++0x3 line.long 0x0 "REGG6_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1A 0x1B 0x1C 0x1D 0x1E 0x1F )(list 0x40 0x44 0x48 0x4C 0x50 0x54 0x58 0x5C 0x60 0x64 0x68 0x6C 0x70 0x74 0x78 0x7C ) group.long ($2+0x1800)++0x3 line.long 0x0 "REGG6_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x20 0x21 0x22 0x23 0x24 0x25 0x26 0x27 0x28 0x29 0x2A 0x2B 0x2C 0x2D 0x2E 0x2F )(list 0x80 0x84 0x88 0x8C 0x90 0x94 0x98 0x9C 0xA0 0xA4 0xA8 0xAC 0xB0 0xB4 0xB8 0xBC ) group.long ($2+0x1800)++0x3 line.long 0x0 "REGG6_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x30 0x31 0x32 0x33 0x34 0x35 0x36 0x37 0x38 0x39 0x3A 0x3B 0x3C 0x3D 0x3E 0x3F )(list 0xC0 0xC4 0xC8 0xCC 0xD0 0xD4 0xD8 0xDC 0xE0 0xE4 0xE8 0xEC 0xF0 0xF4 0xF8 0xFC ) group.long ($2+0x1800)++0x3 line.long 0x0 "REGG6_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x40 0x41 0x42 0x43 0x44 0x45 0x46 0x47 0x48 0x49 0x4A 0x4B 0x4C 0x4D 0x4E 0x4F )(list 0x100 0x104 0x108 0x10C 0x110 0x114 0x118 0x11C 0x120 0x124 0x128 0x12C 0x130 0x134 0x138 0x13C ) group.long ($2+0x1800)++0x3 line.long 0x0 "REGG6_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x50 0x51 0x52 0x53 0x54 0x55 0x56 0x57 0x58 0x59 0x5A 0x5B 0x5C 0x5D 0x5E 0x5F )(list 0x140 0x144 0x148 0x14C 0x150 0x154 0x158 0x15C 0x160 0x164 0x168 0x16C 0x170 0x174 0x178 0x17C ) group.long ($2+0x1800)++0x3 line.long 0x0 "REGG6_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x60 0x61 0x62 0x63 0x64 0x65 0x66 0x67 0x68 0x69 0x6A 0x6B 0x6C 0x6D 0x6E 0x6F )(list 0x180 0x184 0x188 0x18C 0x190 0x194 0x198 0x19C 0x1A0 0x1A4 0x1A8 0x1AC 0x1B0 0x1B4 0x1B8 0x1BC ) group.long ($2+0x1800)++0x3 line.long 0x0 "REGG6_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x70 0x71 0x72 0x73 0x74 0x75 0x76 0x77 0x78 0x79 0x7A 0x7B 0x7C 0x7D 0x7E 0x7F )(list 0x1C0 0x1C4 0x1C8 0x1CC 0x1D0 0x1D4 0x1D8 0x1DC 0x1E0 0x1E4 0x1E8 0x1EC 0x1F0 0x1F4 0x1F8 0x1FC ) group.long ($2+0x1800)++0x3 line.long 0x0 "REGG6_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x80 0x81 0x82 0x83 0x84 0x85 0x86 0x87 0x88 0x89 0x8A 0x8B 0x8C 0x8D 0x8E 0x8F )(list 0x200 0x204 0x208 0x20C 0x210 0x214 0x218 0x21C 0x220 0x224 0x228 0x22C 0x230 0x234 0x238 0x23C ) group.long ($2+0x1800)++0x3 line.long 0x0 "REGG6_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x90 0x91 0x92 0x93 0x94 0x95 0x96 0x97 0x98 0x99 0x9A 0x9B 0x9C 0x9D 0x9E 0x9F )(list 0x240 0x244 0x248 0x24C 0x250 0x254 0x258 0x25C 0x260 0x264 0x268 0x26C 0x270 0x274 0x278 0x27C ) group.long ($2+0x1800)++0x3 line.long 0x0 "REGG6_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xA0 0xA1 0xA2 0xA3 0xA4 0xA5 0xA6 0xA7 0xA8 0xA9 0xAA 0xAB 0xAC 0xAD 0xAE 0xAF )(list 0x280 0x284 0x288 0x28C 0x290 0x294 0x298 0x29C 0x2A0 0x2A4 0x2A8 0x2AC 0x2B0 0x2B4 0x2B8 0x2BC ) group.long ($2+0x1800)++0x3 line.long 0x0 "REGG6_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xB0 0xB1 0xB2 0xB3 0xB4 0xB5 0xB6 0xB7 0xB8 0xB9 0xBA 0xBB 0xBC 0xBD 0xBE 0xBF )(list 0x2C0 0x2C4 0x2C8 0x2CC 0x2D0 0x2D4 0x2D8 0x2DC 0x2E0 0x2E4 0x2E8 0x2EC 0x2F0 0x2F4 0x2F8 0x2FC ) group.long ($2+0x1800)++0x3 line.long 0x0 "REGG6_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xC0 0xC1 0xC2 0xC3 0xC4 0xC5 0xC6 0xC7 0xC8 0xC9 0xCA 0xCB 0xCC 0xCD 0xCE 0xCF )(list 0x300 0x304 0x308 0x30C 0x310 0x314 0x318 0x31C 0x320 0x324 0x328 0x32C 0x330 0x334 0x338 0x33C ) group.long ($2+0x1800)++0x3 line.long 0x0 "REGG6_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xD0 0xD1 0xD2 0xD3 0xD4 0xD5 0xD6 0xD7 0xD8 0xD9 0xDA 0xDB 0xDC 0xDD 0xDE 0xDF )(list 0x340 0x344 0x348 0x34C 0x350 0x354 0x358 0x35C 0x360 0x364 0x368 0x36C 0x370 0x374 0x378 0x37C ) group.long ($2+0x1800)++0x3 line.long 0x0 "REGG6_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xE0 0xE1 0xE2 0xE3 0xE4 0xE5 0xE6 0xE7 0xE8 0xE9 0xEA 0xEB 0xEC 0xED 0xEE 0xEF )(list 0x380 0x384 0x388 0x38C 0x390 0x394 0x398 0x39C 0x3A0 0x3A4 0x3A8 0x3AC 0x3B0 0x3B4 0x3B8 0x3BC ) group.long ($2+0x1800)++0x3 line.long 0x0 "REGG6_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xF0 0xF1 0xF2 0xF3 0xF4 0xF5 0xF6 0xF7 0xF8 0xF9 0xFA 0xFB 0xFC 0xFD 0xFE 0xFF )(list 0x3C0 0x3C4 0x3C8 0x3CC 0x3D0 0x3D4 0x3D8 0x3DC 0x3E0 0x3E4 0x3E8 0x3EC 0x3F0 0x3F4 0x3F8 0x3FC ) group.long ($2+0x1800)++0x3 line.long 0x0 "REGG6_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x4 0x8 0xC 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C ) group.long ($2+0x1C00)++0x3 line.long 0x0 "REGG7_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1A 0x1B 0x1C 0x1D 0x1E 0x1F )(list 0x40 0x44 0x48 0x4C 0x50 0x54 0x58 0x5C 0x60 0x64 0x68 0x6C 0x70 0x74 0x78 0x7C ) group.long ($2+0x1C00)++0x3 line.long 0x0 "REGG7_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x20 0x21 0x22 0x23 0x24 0x25 0x26 0x27 0x28 0x29 0x2A 0x2B 0x2C 0x2D 0x2E 0x2F )(list 0x80 0x84 0x88 0x8C 0x90 0x94 0x98 0x9C 0xA0 0xA4 0xA8 0xAC 0xB0 0xB4 0xB8 0xBC ) group.long ($2+0x1C00)++0x3 line.long 0x0 "REGG7_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x30 0x31 0x32 0x33 0x34 0x35 0x36 0x37 0x38 0x39 0x3A 0x3B 0x3C 0x3D 0x3E 0x3F )(list 0xC0 0xC4 0xC8 0xCC 0xD0 0xD4 0xD8 0xDC 0xE0 0xE4 0xE8 0xEC 0xF0 0xF4 0xF8 0xFC ) group.long ($2+0x1C00)++0x3 line.long 0x0 "REGG7_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x40 0x41 0x42 0x43 0x44 0x45 0x46 0x47 0x48 0x49 0x4A 0x4B 0x4C 0x4D 0x4E 0x4F )(list 0x100 0x104 0x108 0x10C 0x110 0x114 0x118 0x11C 0x120 0x124 0x128 0x12C 0x130 0x134 0x138 0x13C ) group.long ($2+0x1C00)++0x3 line.long 0x0 "REGG7_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x50 0x51 0x52 0x53 0x54 0x55 0x56 0x57 0x58 0x59 0x5A 0x5B 0x5C 0x5D 0x5E 0x5F )(list 0x140 0x144 0x148 0x14C 0x150 0x154 0x158 0x15C 0x160 0x164 0x168 0x16C 0x170 0x174 0x178 0x17C ) group.long ($2+0x1C00)++0x3 line.long 0x0 "REGG7_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x60 0x61 0x62 0x63 0x64 0x65 0x66 0x67 0x68 0x69 0x6A 0x6B 0x6C 0x6D 0x6E 0x6F )(list 0x180 0x184 0x188 0x18C 0x190 0x194 0x198 0x19C 0x1A0 0x1A4 0x1A8 0x1AC 0x1B0 0x1B4 0x1B8 0x1BC ) group.long ($2+0x1C00)++0x3 line.long 0x0 "REGG7_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x70 0x71 0x72 0x73 0x74 0x75 0x76 0x77 0x78 0x79 0x7A 0x7B 0x7C 0x7D 0x7E 0x7F )(list 0x1C0 0x1C4 0x1C8 0x1CC 0x1D0 0x1D4 0x1D8 0x1DC 0x1E0 0x1E4 0x1E8 0x1EC 0x1F0 0x1F4 0x1F8 0x1FC ) group.long ($2+0x1C00)++0x3 line.long 0x0 "REGG7_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x80 0x81 0x82 0x83 0x84 0x85 0x86 0x87 0x88 0x89 0x8A 0x8B 0x8C 0x8D 0x8E 0x8F )(list 0x200 0x204 0x208 0x20C 0x210 0x214 0x218 0x21C 0x220 0x224 0x228 0x22C 0x230 0x234 0x238 0x23C ) group.long ($2+0x1C00)++0x3 line.long 0x0 "REGG7_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x90 0x91 0x92 0x93 0x94 0x95 0x96 0x97 0x98 0x99 0x9A 0x9B 0x9C 0x9D 0x9E 0x9F )(list 0x240 0x244 0x248 0x24C 0x250 0x254 0x258 0x25C 0x260 0x264 0x268 0x26C 0x270 0x274 0x278 0x27C ) group.long ($2+0x1C00)++0x3 line.long 0x0 "REGG7_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xA0 0xA1 0xA2 0xA3 0xA4 0xA5 0xA6 0xA7 0xA8 0xA9 0xAA 0xAB 0xAC 0xAD 0xAE 0xAF )(list 0x280 0x284 0x288 0x28C 0x290 0x294 0x298 0x29C 0x2A0 0x2A4 0x2A8 0x2AC 0x2B0 0x2B4 0x2B8 0x2BC ) group.long ($2+0x1C00)++0x3 line.long 0x0 "REGG7_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xB0 0xB1 0xB2 0xB3 0xB4 0xB5 0xB6 0xB7 0xB8 0xB9 0xBA 0xBB 0xBC 0xBD 0xBE 0xBF )(list 0x2C0 0x2C4 0x2C8 0x2CC 0x2D0 0x2D4 0x2D8 0x2DC 0x2E0 0x2E4 0x2E8 0x2EC 0x2F0 0x2F4 0x2F8 0x2FC ) group.long ($2+0x1C00)++0x3 line.long 0x0 "REGG7_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xC0 0xC1 0xC2 0xC3 0xC4 0xC5 0xC6 0xC7 0xC8 0xC9 0xCA 0xCB 0xCC 0xCD 0xCE 0xCF )(list 0x300 0x304 0x308 0x30C 0x310 0x314 0x318 0x31C 0x320 0x324 0x328 0x32C 0x330 0x334 0x338 0x33C ) group.long ($2+0x1C00)++0x3 line.long 0x0 "REGG7_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xD0 0xD1 0xD2 0xD3 0xD4 0xD5 0xD6 0xD7 0xD8 0xD9 0xDA 0xDB 0xDC 0xDD 0xDE 0xDF )(list 0x340 0x344 0x348 0x34C 0x350 0x354 0x358 0x35C 0x360 0x364 0x368 0x36C 0x370 0x374 0x378 0x37C ) group.long ($2+0x1C00)++0x3 line.long 0x0 "REGG7_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xE0 0xE1 0xE2 0xE3 0xE4 0xE5 0xE6 0xE7 0xE8 0xE9 0xEA 0xEB 0xEC 0xED 0xEE 0xEF )(list 0x380 0x384 0x388 0x38C 0x390 0x394 0x398 0x39C 0x3A0 0x3A4 0x3A8 0x3AC 0x3B0 0x3B4 0x3B8 0x3BC ) group.long ($2+0x1C00)++0x3 line.long 0x0 "REGG7_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xF0 0xF1 0xF2 0xF3 0xF4 0xF5 0xF6 0xF7 0xF8 0xF9 0xFA 0xFB 0xFC 0xFD 0xFE 0xFF )(list 0x3C0 0x3C4 0x3C8 0x3CC 0x3D0 0x3D4 0x3D8 0x3DC 0x3E0 0x3E4 0x3E8 0x3EC 0x3F0 0x3F4 0x3F8 0x3FC ) group.long ($2+0x1C00)++0x3 line.long 0x0 "REGG7_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end group.long 0x2000++0x17 line.long 0x0 "GLB_CTL,This register provides global enable settings for permission control." bitfld.long 0x0 5. "DOM_CFG_LOCK,Lock write for DOM_CFG_MODE bit." "0,1" bitfld.long 0x0 4. "DOM_CFG_MODE,When enabled all the source setting can be configured by master from domain 0 if it is not locked. When disabled only resource manager can configure the permission of the resource." "0,1" bitfld.long 0x0 3. "PERCK_DIS_LOCK,Lock write for PERCK_DIS" "0,1" bitfld.long 0x0 2. "PERCK_DIS,All the permission check disable." "0,1" newline bitfld.long 0x0 1. "DOM_PRO_LOCK,Lock write for DOM_PRO_EN bit." "0,1" bitfld.long 0x0 0. "DOM_PRO_EN,When disabled no domain access permission check" "0,1" line.long 0x4 "RES_MGR,Resource manager register. This regster is used to assign resource manager for global resource access control" bitfld.long 0x4 17. "MID_LOCK,Lock write for MID_EN and MID_LOW and MID_HIG registers." "0,1" bitfld.long 0x4 16. "MID_EN,Master ID check enable" "0,1" bitfld.long 0x4 15. "PRI_PER_LOCK,Lock write for PRI_PER and PRI_PER_EN" "0,1" bitfld.long 0x4 13.--14. "PRI_PER,Resource manager privileged access permission. bit0 for privileged access bit1 for user access" "0,1,2,3" newline bitfld.long 0x4 12. "PRI_PER_EN,Resource manager privileged access permission enable." "0,1" bitfld.long 0x4 11. "SEC_PER_LOCK,Lock for SEC_PER and SEC_PER_LOCK" "0,1" bitfld.long 0x4 9.--10. "SEC_PER,Resource manager secure access permission. bit 0 for secure access bit 1 for non-secure access" "0,1,2,3" bitfld.long 0x4 8. "SEC_PER_EN,Resource manager secure permission enable" "0,1" bitfld.long 0x4 7. "DID_LOCK,Lock write for DID_EN and DID" "0,1" newline hexmask.long.byte 0x4 3.--6. 1. "DID,Resource manager domain ID" bitfld.long 0x4 2. "DID_EN,Resource manager Domain ID enable" "0,1" bitfld.long 0x4 1. "RES_MGR_EN_LOCK,Lock for RES_MGR_EN" "0,1" bitfld.long 0x4 0. "RES_MGR_EN,Resource manager enable. When the bit is disable there is no resource manager." "0,1" line.long 0x8 "RES_MGR_MA0,This register is used to assign master 0~31 as resource manager." hexmask.long 0x8 0.--31. 1. "MID,Assign master 0~31 for resource manager" line.long 0xC "RES_MGR_MA1,This register is used to assign master 32~63 as resource manager." hexmask.long 0xC 0.--31. 1. "MID,Indicate if master 32~63 is resource manager." line.long 0x10 "RES_MGR_MA2,This register is used to assign master 64~95 as resource manager." hexmask.long 0x10 0.--31. 1. "MID,Indicate if master 64~95 is resource manager." line.long 0x14 "RES_MGR_MA3,This register is used to assign master 96~127 as resource manager." hexmask.long 0x14 0.--31. 1. "MID,Indicate if master 96~127 is resource manager." repeat 8. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 )(list 0x0 0x14 0x28 0x3C 0x50 0x64 0x78 0x8C ) group.long ($2+0x2100)++0x3 line.long 0x0 "GRP_MGR_$1,Group Manager Register. This register is used to assign group manager for each domain" bitfld.long 0x0 17. "MID_LOCK,Lock write for MID_EN and MID_LOW and MID_HIG registers." "0,1" bitfld.long 0x0 16. "MID_EN,Master ID check enable" "0,1" bitfld.long 0x0 15. "PRI_PER_LOCK,Lock write for PRI_PER and PRI_PER_EN" "0,1" bitfld.long 0x0 13.--14. "PRI_PER,Group manager privileged access permission. bit0 for privileged access bit1 for user access" "0,1,2,3" newline bitfld.long 0x0 12. "PRI_PER_EN,Group manager privileged access permission enable." "0,1" bitfld.long 0x0 11. "SEC_PER_LOCK,Lock for SEC_PER and SEC_PER_LOCK" "0,1" bitfld.long 0x0 9.--10. "SEC_PER,Group manager secure access permission. bit 0 for secure access bit 1 for non-secure access" "0,1,2,3" bitfld.long 0x0 8. "SEC_PER_EN,Group manager secure permission enable" "0,1" bitfld.long 0x0 7. "DID_LOCK,Lock write for DID_EN and DID" "0,1" newline hexmask.long.byte 0x0 3.--6. 1. "DID,Group manager domain ID" bitfld.long 0x0 2. "DID_EN,Group manager Domain ID enable" "0,1" bitfld.long 0x0 1. "GRP_MGR_EN_LOCK,Lock write for GPR_MGR_EN" "0,1" bitfld.long 0x0 0. "GRP_MGR_EN,Group manager enable. When the bit is disable there is no resource manager." "0,1" repeat.end repeat 8. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 )(list 0x0 0x14 0x28 0x3C 0x50 0x64 0x78 0x8C ) group.long ($2+0x2104)++0x3 line.long 0x0 "GRP_MGR_MA0_$1,Assign master 0~31 for group manager 0" hexmask.long 0x0 0.--31. 1. "MID,Assign master 0~31 for resource manager" repeat.end repeat 8. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 )(list 0x0 0x14 0x28 0x3C 0x50 0x64 0x78 0x8C ) group.long ($2+0x2108)++0x3 line.long 0x0 "GRP_MGR_MA1_$1,Assign master 32~63 for group manager 0" hexmask.long 0x0 0.--31. 1. "MID,Indicate if master 32~63 is resource manager." repeat.end repeat 8. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 )(list 0x0 0x14 0x28 0x3C 0x50 0x64 0x78 0x8C ) group.long ($2+0x210C)++0x3 line.long 0x0 "GRP_MGR_MA2_$1,Assign master 64~95 for group manager 0" hexmask.long 0x0 0.--31. 1. "MID,Indicate if master 64~95 is resource manager." repeat.end repeat 8. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 )(list 0x0 0x14 0x28 0x3C 0x50 0x64 0x78 0x8C ) group.long ($2+0x2110)++0x3 line.long 0x0 "GRP_MGR_MA3_$1,Assign master 96~127 for group manager 0" hexmask.long 0x0 0.--31. 1. "MID,Indicate if master 96~127 is resource manager." repeat.end group.long 0x2200++0x3 line.long 0x0 "DOM_GID_0,Indicate which group domain 0 belong to" bitfld.long 0x0 3. "LOCK,Lock write for GID" "0,1" bitfld.long 0x0 0.--2. "GID,Group ID" "0,1,2,3,4,5,6,7" repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x18 0x30 0x48 0x60 0x78 0x90 0xA8 0xC0 0xD8 0xF0 0x108 0x120 0x138 0x150 0x168 ) group.long ($2+0x2204)++0x3 line.long 0x0 "DOM_OWN_$1,Assign owner for function domain 0." bitfld.long 0x0 17. "MID_LOCK,Lock write for MID_EN and MID_LOW and MID_HIG registers." "0,1" bitfld.long 0x0 16. "MID_EN,Master ID check enable" "0,1" bitfld.long 0x0 15. "PRI_PER_LOCK,Lock write for PRI_PER and PRI_PER_EN" "0,1" bitfld.long 0x0 13.--14. "PRI_PER,Group manager privileged access permission. bit0 for privileged access bit1 for user access" "0,1,2,3" newline bitfld.long 0x0 12. "PRI_PER_EN,Group manager privileged access permission enable." "0,1" bitfld.long 0x0 11. "SEC_PER_LOCK,Lock for SEC_PER and SEC_PER_LOCK" "0,1" bitfld.long 0x0 9.--10. "SEC_PER,Domain owner secure access permission. bit 0 for secure access bit 1 for non-secure access" "0,1,2,3" bitfld.long 0x0 8. "SEC_PER_EN,Domain owner secure permission enable" "0,1" newline bitfld.long 0x0 1. "DOM_OWN_EN_LOCK,Lock for DOM_OWN_EN" "0,1" bitfld.long 0x0 0. "DOM_OWN_EN,Domain owner enable. When the bit is disable there is no domain owner." "0,1" repeat.end repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x18 0x30 0x48 0x60 0x78 0x90 0xA8 0xC0 0xD8 0xF0 0x108 0x120 0x138 0x150 0x168 ) group.long ($2+0x2208)++0x3 line.long 0x0 "DOM_OWN_MA0_$1,Assign master 0~31 for domain owner 0" hexmask.long 0x0 0.--31. 1. "MID,Assign master 0~31 for resource manager" repeat.end repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x18 0x30 0x48 0x60 0x78 0x90 0xA8 0xC0 0xD8 0xF0 0x108 0x120 0x138 0x150 0x168 ) group.long ($2+0x220C)++0x3 line.long 0x0 "DOM_OWN_MA1_$1,Assign master 32~63 for domain owner 0" hexmask.long 0x0 0.--31. 1. "MID,Indicate if master 32~63 is resource manager." repeat.end repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x18 0x30 0x48 0x60 0x78 0x90 0xA8 0xC0 0xD8 0xF0 0x108 0x120 0x138 0x150 0x168 ) group.long ($2+0x2210)++0x3 line.long 0x0 "DOM_OWN_MA2_$1,Assign master 64~95 for domain owner 0" hexmask.long 0x0 0.--31. 1. "MID,Indicate if master 64~95 is resource manager." repeat.end repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x18 0x30 0x48 0x60 0x78 0x90 0xA8 0xC0 0xD8 0xF0 0x108 0x120 0x138 0x150 0x168 ) group.long ($2+0x2214)++0x3 line.long 0x0 "DOM_OWN_MA3_$1,Assign master 96~127 for domain owner 0" hexmask.long 0x0 0.--31. 1. "MID,Indicate if master 96~127 is resource manager." repeat.end group.long 0x2218++0x3 line.long 0x0 "DOM_GID_1,Indicate which group domain 1 belong to" bitfld.long 0x0 3. "LOCK,Lock write for GID" "0,1" bitfld.long 0x0 0.--2. "GID,Group ID" "0,1,2,3,4,5,6,7" group.long 0x2230++0x3 line.long 0x0 "DOM_GID_2,Indicate which group domain 2 belong to" bitfld.long 0x0 3. "LOCK,Lock write for GID" "0,1" bitfld.long 0x0 0.--2. "GID,Group ID" "0,1,2,3,4,5,6,7" group.long 0x2248++0x3 line.long 0x0 "DOM_GID_3,Indicate which group domain 3 belong to" bitfld.long 0x0 3. "LOCK,Lock write for GID" "0,1" bitfld.long 0x0 0.--2. "GID,Group ID" "0,1,2,3,4,5,6,7" group.long 0x2260++0x3 line.long 0x0 "DOM_GID_4,Indicate which group domain 4 belong to" bitfld.long 0x0 3. "LOCK,Lock write for GID" "0,1" bitfld.long 0x0 0.--2. "GID,Group ID" "0,1,2,3,4,5,6,7" group.long 0x2278++0x3 line.long 0x0 "DOM_GID_5,Indicate which group domain 5 belong to" bitfld.long 0x0 3. "LOCK,Lock write for GID" "0,1" bitfld.long 0x0 0.--2. "GID,Group ID" "0,1,2,3,4,5,6,7" group.long 0x2290++0x3 line.long 0x0 "DOM_GID_6,Indicate which group domain 6 belong to" bitfld.long 0x0 3. "LOCK,Lock write for GID" "0,1" bitfld.long 0x0 0.--2. "GID,Group ID" "0,1,2,3,4,5,6,7" group.long 0x22A8++0x3 line.long 0x0 "DOM_GID_7,Indicate which group domain 7 belong to" bitfld.long 0x0 3. "LOCK,Lock write for GID" "0,1" bitfld.long 0x0 0.--2. "GID,Group ID" "0,1,2,3,4,5,6,7" group.long 0x22C0++0x3 line.long 0x0 "DOM_GID_8,Indicate which group domain 8 belong to" bitfld.long 0x0 3. "LOCK,Lock write for GID" "0,1" bitfld.long 0x0 0.--2. "GID,Group ID" "0,1,2,3,4,5,6,7" group.long 0x22D8++0x3 line.long 0x0 "DOM_GID_9,Indicate which group domain 9 belong to" bitfld.long 0x0 3. "LOCK,Lock write for GID" "0,1" bitfld.long 0x0 0.--2. "GID,Group ID" "0,1,2,3,4,5,6,7" group.long 0x22F0++0x3 line.long 0x0 "DOM_GID_10,Indicate which group domain 10 belong to" bitfld.long 0x0 3. "LOCK,Lock write for GID" "0,1" bitfld.long 0x0 0.--2. "GID,Group ID" "0,1,2,3,4,5,6,7" group.long 0x2308++0x3 line.long 0x0 "DOM_GID_11,Indicate which group domain 11 belong to" bitfld.long 0x0 3. "LOCK,Lock write for GID" "0,1" bitfld.long 0x0 0.--2. "GID,Group ID" "0,1,2,3,4,5,6,7" group.long 0x2320++0x3 line.long 0x0 "DOM_GID_12,Indicate which group domain 12 belong to" bitfld.long 0x0 3. "LOCK,Lock write for GID" "0,1" bitfld.long 0x0 0.--2. "GID,Group ID" "0,1,2,3,4,5,6,7" group.long 0x2338++0x3 line.long 0x0 "DOM_GID_13,Indicate which group domain 13 belong to" bitfld.long 0x0 3. "LOCK,Lock write for GID" "0,1" bitfld.long 0x0 0.--2. "GID,Group ID" "0,1,2,3,4,5,6,7" group.long 0x2350++0x3 line.long 0x0 "DOM_GID_14,Indicate which group domain 14 belong to" bitfld.long 0x0 3. "LOCK,Lock write for GID" "0,1" bitfld.long 0x0 0.--2. "GID,Group ID" "0,1,2,3,4,5,6,7" group.long 0x2368++0x3 line.long 0x0 "DOM_GID_15,Indicate which group domain 15 belong to" bitfld.long 0x0 3. "LOCK,Lock write for GID" "0,1" bitfld.long 0x0 0.--2. "GID,Group ID" "0,1,2,3,4,5,6,7" repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x34 0x68 0x9C 0xD0 0x104 0x138 0x16C 0x1A0 0x1D4 0x208 0x23C 0x270 0x2A4 0x2D8 0x30C ) group.long ($2+0x2400)++0x3 line.long 0x0 "DOM_PER0_$1,Domain Permission Control. It can be only configured by resource manager and domain owner." bitfld.long 0x0 31. "DOM7_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 29.--30. "DOM7_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 28. "DOM7_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 27. "DOM6_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 25.--26. "DOM6_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" newline bitfld.long 0x0 24. "DOM6_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 23. "DOM5_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 21.--22. "DOM5_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 20. "DOM5_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 19. "DOM4_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" newline bitfld.long 0x0 17.--18. "DOM4_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM4_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 15. "DOM3_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 13.--14. "DOM3_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 12. "DOM3_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" newline bitfld.long 0x0 11. "DOM2_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 9.--10. "DOM2_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM2_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 7. "DOM1_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 5.--6. "DOM1_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" newline bitfld.long 0x0 4. "DOM1_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 3. "DOM0_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 1.--2. "DOM0_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM0_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" repeat.end repeat 16. (list 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1A 0x1B 0x1C 0x1D 0x1E 0x1F )(list 0x340 0x374 0x3A8 0x3DC 0x410 0x444 0x478 0x4AC 0x4E0 0x514 0x548 0x57C 0x5B0 0x5E4 0x618 0x64C ) group.long ($2+0x2400)++0x3 line.long 0x0 "DOM_PER0_$1,Domain Permission Control. It can be only configured by resource manager and domain owner." bitfld.long 0x0 31. "DOM7_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 29.--30. "DOM7_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 28. "DOM7_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 27. "DOM6_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 25.--26. "DOM6_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" newline bitfld.long 0x0 24. "DOM6_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 23. "DOM5_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 21.--22. "DOM5_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 20. "DOM5_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 19. "DOM4_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" newline bitfld.long 0x0 17.--18. "DOM4_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM4_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 15. "DOM3_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 13.--14. "DOM3_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 12. "DOM3_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" newline bitfld.long 0x0 11. "DOM2_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 9.--10. "DOM2_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM2_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 7. "DOM1_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 5.--6. "DOM1_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" newline bitfld.long 0x0 4. "DOM1_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 3. "DOM0_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 1.--2. "DOM0_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM0_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" repeat.end repeat 16. (list 0x20 0x21 0x22 0x23 0x24 0x25 0x26 0x27 0x28 0x29 0x2A 0x2B 0x2C 0x2D 0x2E 0x2F )(list 0x680 0x6B4 0x6E8 0x71C 0x750 0x784 0x7B8 0x7EC 0x820 0x854 0x888 0x8BC 0x8F0 0x924 0x958 0x98C ) group.long ($2+0x2400)++0x3 line.long 0x0 "DOM_PER0_$1,Domain Permission Control. It can be only configured by resource manager and domain owner." bitfld.long 0x0 31. "DOM7_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 29.--30. "DOM7_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 28. "DOM7_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 27. "DOM6_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 25.--26. "DOM6_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" newline bitfld.long 0x0 24. "DOM6_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 23. "DOM5_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 21.--22. "DOM5_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 20. "DOM5_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 19. "DOM4_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" newline bitfld.long 0x0 17.--18. "DOM4_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM4_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 15. "DOM3_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 13.--14. "DOM3_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 12. "DOM3_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" newline bitfld.long 0x0 11. "DOM2_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 9.--10. "DOM2_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM2_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 7. "DOM1_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 5.--6. "DOM1_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" newline bitfld.long 0x0 4. "DOM1_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 3. "DOM0_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 1.--2. "DOM0_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM0_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" repeat.end repeat 16. (list 0x30 0x31 0x32 0x33 0x34 0x35 0x36 0x37 0x38 0x39 0x3A 0x3B 0x3C 0x3D 0x3E 0x3F )(list 0x9C0 0x9F4 0xA28 0xA5C 0xA90 0xAC4 0xAF8 0xB2C 0xB60 0xB94 0xBC8 0xBFC 0xC30 0xC64 0xC98 0xCCC ) group.long ($2+0x2400)++0x3 line.long 0x0 "DOM_PER0_$1,Domain Permission Control. It can be only configured by resource manager and domain owner." bitfld.long 0x0 31. "DOM7_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 29.--30. "DOM7_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 28. "DOM7_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 27. "DOM6_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 25.--26. "DOM6_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" newline bitfld.long 0x0 24. "DOM6_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 23. "DOM5_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 21.--22. "DOM5_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 20. "DOM5_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 19. "DOM4_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" newline bitfld.long 0x0 17.--18. "DOM4_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM4_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 15. "DOM3_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 13.--14. "DOM3_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 12. "DOM3_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" newline bitfld.long 0x0 11. "DOM2_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 9.--10. "DOM2_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM2_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 7. "DOM1_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 5.--6. "DOM1_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" newline bitfld.long 0x0 4. "DOM1_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 3. "DOM0_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 1.--2. "DOM0_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM0_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" repeat.end repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x34 0x68 0x9C 0xD0 0x104 0x138 0x16C 0x1A0 0x1D4 0x208 0x23C 0x270 0x2A4 0x2D8 0x30C ) group.long ($2+0x2404)++0x3 line.long 0x0 "DOM_PER1_$1,Domain Permission Control. It can be only configured by resource manager and domain owner." bitfld.long 0x0 31. "DOM15_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 29.--30. "DOM15_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 28. "DOM15_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 27. "DOM14_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 25.--26. "DOM14_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" newline bitfld.long 0x0 24. "DOM14_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 23. "DOM13_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 21.--22. "DOM13_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 20. "DOM13_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 19. "DOM12_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" newline bitfld.long 0x0 17.--18. "DOM12_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM12_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 15. "DOM11_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 13.--14. "DOM11_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 12. "DOM11_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" newline bitfld.long 0x0 11. "DOM10_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 9.--10. "DOM10_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM10_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 7. "DOM9_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 5.--6. "DOM9_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" newline bitfld.long 0x0 4. "DOM9_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 3. "DOM8_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 1.--2. "DOM8_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM8_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" repeat.end repeat 16. (list 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1A 0x1B 0x1C 0x1D 0x1E 0x1F )(list 0x340 0x374 0x3A8 0x3DC 0x410 0x444 0x478 0x4AC 0x4E0 0x514 0x548 0x57C 0x5B0 0x5E4 0x618 0x64C ) group.long ($2+0x2404)++0x3 line.long 0x0 "DOM_PER1_$1,Domain Permission Control. It can be only configured by resource manager and domain owner." bitfld.long 0x0 31. "DOM15_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 29.--30. "DOM15_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 28. "DOM15_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 27. "DOM14_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 25.--26. "DOM14_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" newline bitfld.long 0x0 24. "DOM14_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 23. "DOM13_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 21.--22. "DOM13_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 20. "DOM13_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 19. "DOM12_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" newline bitfld.long 0x0 17.--18. "DOM12_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM12_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 15. "DOM11_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 13.--14. "DOM11_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 12. "DOM11_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" newline bitfld.long 0x0 11. "DOM10_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 9.--10. "DOM10_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM10_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 7. "DOM9_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 5.--6. "DOM9_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" newline bitfld.long 0x0 4. "DOM9_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 3. "DOM8_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 1.--2. "DOM8_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM8_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" repeat.end repeat 16. (list 0x20 0x21 0x22 0x23 0x24 0x25 0x26 0x27 0x28 0x29 0x2A 0x2B 0x2C 0x2D 0x2E 0x2F )(list 0x680 0x6B4 0x6E8 0x71C 0x750 0x784 0x7B8 0x7EC 0x820 0x854 0x888 0x8BC 0x8F0 0x924 0x958 0x98C ) group.long ($2+0x2404)++0x3 line.long 0x0 "DOM_PER1_$1,Domain Permission Control. It can be only configured by resource manager and domain owner." bitfld.long 0x0 31. "DOM15_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 29.--30. "DOM15_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 28. "DOM15_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 27. "DOM14_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 25.--26. "DOM14_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" newline bitfld.long 0x0 24. "DOM14_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 23. "DOM13_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 21.--22. "DOM13_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 20. "DOM13_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 19. "DOM12_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" newline bitfld.long 0x0 17.--18. "DOM12_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM12_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 15. "DOM11_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 13.--14. "DOM11_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 12. "DOM11_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" newline bitfld.long 0x0 11. "DOM10_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 9.--10. "DOM10_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM10_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 7. "DOM9_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 5.--6. "DOM9_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" newline bitfld.long 0x0 4. "DOM9_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 3. "DOM8_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 1.--2. "DOM8_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM8_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" repeat.end repeat 16. (list 0x30 0x31 0x32 0x33 0x34 0x35 0x36 0x37 0x38 0x39 0x3A 0x3B 0x3C 0x3D 0x3E 0x3F )(list 0x9C0 0x9F4 0xA28 0xA5C 0xA90 0xAC4 0xAF8 0xB2C 0xB60 0xB94 0xBC8 0xBFC 0xC30 0xC64 0xC98 0xCCC ) group.long ($2+0x2404)++0x3 line.long 0x0 "DOM_PER1_$1,Domain Permission Control. It can be only configured by resource manager and domain owner." bitfld.long 0x0 31. "DOM15_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 29.--30. "DOM15_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 28. "DOM15_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 27. "DOM14_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 25.--26. "DOM14_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" newline bitfld.long 0x0 24. "DOM14_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 23. "DOM13_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 21.--22. "DOM13_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 20. "DOM13_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 19. "DOM12_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" newline bitfld.long 0x0 17.--18. "DOM12_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM12_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 15. "DOM11_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 13.--14. "DOM11_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 12. "DOM11_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" newline bitfld.long 0x0 11. "DOM10_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 9.--10. "DOM10_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM10_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 7. "DOM9_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 5.--6. "DOM9_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" newline bitfld.long 0x0 4. "DOM9_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 3. "DOM8_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 1.--2. "DOM8_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM8_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" repeat.end repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x34 0x68 0x9C 0xD0 0x104 0x138 0x16C 0x1A0 0x1D4 0x208 0x23C 0x270 0x2A4 0x2D8 0x30C ) group.long ($2+0x2408)++0x3 line.long 0x0 "SEC_PER0_$1,This register is only used for resource manager to control secure access permission." bitfld.long 0x0 31. "DOM3_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM3_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM3_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM3_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM2_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM2_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM2_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM2_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM1_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM1_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM1_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM1_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM0_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM0_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM0_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM0_SEC_EN,Domain secure permission control enable" "0,1" repeat.end repeat 16. (list 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1A 0x1B 0x1C 0x1D 0x1E 0x1F )(list 0x340 0x374 0x3A8 0x3DC 0x410 0x444 0x478 0x4AC 0x4E0 0x514 0x548 0x57C 0x5B0 0x5E4 0x618 0x64C ) group.long ($2+0x2408)++0x3 line.long 0x0 "SEC_PER0_$1,This register is only used for resource manager to control secure access permission." bitfld.long 0x0 31. "DOM3_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM3_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM3_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM3_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM2_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM2_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM2_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM2_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM1_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM1_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM1_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM1_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM0_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM0_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM0_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM0_SEC_EN,Domain secure permission control enable" "0,1" repeat.end repeat 16. (list 0x20 0x21 0x22 0x23 0x24 0x25 0x26 0x27 0x28 0x29 0x2A 0x2B 0x2C 0x2D 0x2E 0x2F )(list 0x680 0x6B4 0x6E8 0x71C 0x750 0x784 0x7B8 0x7EC 0x820 0x854 0x888 0x8BC 0x8F0 0x924 0x958 0x98C ) group.long ($2+0x2408)++0x3 line.long 0x0 "SEC_PER0_$1,This register is only used for resource manager to control secure access permission." bitfld.long 0x0 31. "DOM3_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM3_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM3_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM3_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM2_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM2_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM2_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM2_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM1_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM1_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM1_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM1_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM0_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM0_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM0_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM0_SEC_EN,Domain secure permission control enable" "0,1" repeat.end repeat 16. (list 0x30 0x31 0x32 0x33 0x34 0x35 0x36 0x37 0x38 0x39 0x3A 0x3B 0x3C 0x3D 0x3E 0x3F )(list 0x9C0 0x9F4 0xA28 0xA5C 0xA90 0xAC4 0xAF8 0xB2C 0xB60 0xB94 0xBC8 0xBFC 0xC30 0xC64 0xC98 0xCCC ) group.long ($2+0x2408)++0x3 line.long 0x0 "SEC_PER0_$1,This register is only used for resource manager to control secure access permission." bitfld.long 0x0 31. "DOM3_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM3_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM3_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM3_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM2_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM2_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM2_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM2_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM1_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM1_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM1_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM1_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM0_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM0_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM0_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM0_SEC_EN,Domain secure permission control enable" "0,1" repeat.end repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x34 0x68 0x9C 0xD0 0x104 0x138 0x16C 0x1A0 0x1D4 0x208 0x23C 0x270 0x2A4 0x2D8 0x30C ) group.long ($2+0x240C)++0x3 line.long 0x0 "SEC_PER1_$1,This register is only used for resource manager to control secure access permission." bitfld.long 0x0 31. "DOM7_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM7_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM7_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM7_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM6_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM6_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM6_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM6_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM5_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM5_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM5_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM5_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM4_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM4_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM4_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM4_SEC_EN,Domain secure permission control enable" "0,1" repeat.end repeat 16. (list 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1A 0x1B 0x1C 0x1D 0x1E 0x1F )(list 0x340 0x374 0x3A8 0x3DC 0x410 0x444 0x478 0x4AC 0x4E0 0x514 0x548 0x57C 0x5B0 0x5E4 0x618 0x64C ) group.long ($2+0x240C)++0x3 line.long 0x0 "SEC_PER1_$1,This register is only used for resource manager to control secure access permission." bitfld.long 0x0 31. "DOM7_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM7_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM7_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM7_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM6_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM6_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM6_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM6_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM5_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM5_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM5_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM5_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM4_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM4_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM4_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM4_SEC_EN,Domain secure permission control enable" "0,1" repeat.end repeat 16. (list 0x20 0x21 0x22 0x23 0x24 0x25 0x26 0x27 0x28 0x29 0x2A 0x2B 0x2C 0x2D 0x2E 0x2F )(list 0x680 0x6B4 0x6E8 0x71C 0x750 0x784 0x7B8 0x7EC 0x820 0x854 0x888 0x8BC 0x8F0 0x924 0x958 0x98C ) group.long ($2+0x240C)++0x3 line.long 0x0 "SEC_PER1_$1,This register is only used for resource manager to control secure access permission." bitfld.long 0x0 31. "DOM7_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM7_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM7_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM7_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM6_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM6_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM6_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM6_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM5_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM5_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM5_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM5_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM4_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM4_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM4_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM4_SEC_EN,Domain secure permission control enable" "0,1" repeat.end repeat 16. (list 0x30 0x31 0x32 0x33 0x34 0x35 0x36 0x37 0x38 0x39 0x3A 0x3B 0x3C 0x3D 0x3E 0x3F )(list 0x9C0 0x9F4 0xA28 0xA5C 0xA90 0xAC4 0xAF8 0xB2C 0xB60 0xB94 0xBC8 0xBFC 0xC30 0xC64 0xC98 0xCCC ) group.long ($2+0x240C)++0x3 line.long 0x0 "SEC_PER1_$1,This register is only used for resource manager to control secure access permission." bitfld.long 0x0 31. "DOM7_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM7_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM7_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM7_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM6_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM6_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM6_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM6_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM5_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM5_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM5_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM5_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM4_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM4_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM4_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM4_SEC_EN,Domain secure permission control enable" "0,1" repeat.end repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x34 0x68 0x9C 0xD0 0x104 0x138 0x16C 0x1A0 0x1D4 0x208 0x23C 0x270 0x2A4 0x2D8 0x30C ) group.long ($2+0x2410)++0x3 line.long 0x0 "SEC_PER2_$1,This register is only used for resource manager to control secure access permission." bitfld.long 0x0 31. "DOM11_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM11_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM11_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM11_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM10_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM10_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM10_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM10_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM9_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM9_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM9_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM9_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM8_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM8_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM8_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM8_SEC_EN,Domain secure permission control enable" "0,1" repeat.end repeat 16. (list 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1A 0x1B 0x1C 0x1D 0x1E 0x1F )(list 0x340 0x374 0x3A8 0x3DC 0x410 0x444 0x478 0x4AC 0x4E0 0x514 0x548 0x57C 0x5B0 0x5E4 0x618 0x64C ) group.long ($2+0x2410)++0x3 line.long 0x0 "SEC_PER2_$1,This register is only used for resource manager to control secure access permission." bitfld.long 0x0 31. "DOM11_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM11_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM11_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM11_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM10_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM10_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM10_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM10_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM9_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM9_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM9_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM9_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM8_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM8_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM8_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM8_SEC_EN,Domain secure permission control enable" "0,1" repeat.end repeat 16. (list 0x20 0x21 0x22 0x23 0x24 0x25 0x26 0x27 0x28 0x29 0x2A 0x2B 0x2C 0x2D 0x2E 0x2F )(list 0x680 0x6B4 0x6E8 0x71C 0x750 0x784 0x7B8 0x7EC 0x820 0x854 0x888 0x8BC 0x8F0 0x924 0x958 0x98C ) group.long ($2+0x2410)++0x3 line.long 0x0 "SEC_PER2_$1,This register is only used for resource manager to control secure access permission." bitfld.long 0x0 31. "DOM11_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM11_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM11_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM11_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM10_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM10_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM10_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM10_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM9_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM9_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM9_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM9_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM8_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM8_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM8_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM8_SEC_EN,Domain secure permission control enable" "0,1" repeat.end repeat 16. (list 0x30 0x31 0x32 0x33 0x34 0x35 0x36 0x37 0x38 0x39 0x3A 0x3B 0x3C 0x3D 0x3E 0x3F )(list 0x9C0 0x9F4 0xA28 0xA5C 0xA90 0xAC4 0xAF8 0xB2C 0xB60 0xB94 0xBC8 0xBFC 0xC30 0xC64 0xC98 0xCCC ) group.long ($2+0x2410)++0x3 line.long 0x0 "SEC_PER2_$1,This register is only used for resource manager to control secure access permission." bitfld.long 0x0 31. "DOM11_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM11_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM11_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM11_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM10_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM10_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM10_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM10_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM9_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM9_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM9_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM9_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM8_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM8_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM8_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM8_SEC_EN,Domain secure permission control enable" "0,1" repeat.end repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x34 0x68 0x9C 0xD0 0x104 0x138 0x16C 0x1A0 0x1D4 0x208 0x23C 0x270 0x2A4 0x2D8 0x30C ) group.long ($2+0x2414)++0x3 line.long 0x0 "SEC_PER3_$1,This register is only used for resource manager to control secure access permission." bitfld.long 0x0 31. "DOM15_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM15_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM15_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM15_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM14_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM14_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM14_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM14_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM13_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM13_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM13_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM13_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM12_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM12_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM12_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM12_SEC_EN,Domain secure permission control enable" "0,1" repeat.end repeat 16. (list 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1A 0x1B 0x1C 0x1D 0x1E 0x1F )(list 0x340 0x374 0x3A8 0x3DC 0x410 0x444 0x478 0x4AC 0x4E0 0x514 0x548 0x57C 0x5B0 0x5E4 0x618 0x64C ) group.long ($2+0x2414)++0x3 line.long 0x0 "SEC_PER3_$1,This register is only used for resource manager to control secure access permission." bitfld.long 0x0 31. "DOM15_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM15_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM15_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM15_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM14_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM14_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM14_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM14_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM13_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM13_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM13_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM13_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM12_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM12_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM12_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM12_SEC_EN,Domain secure permission control enable" "0,1" repeat.end repeat 16. (list 0x20 0x21 0x22 0x23 0x24 0x25 0x26 0x27 0x28 0x29 0x2A 0x2B 0x2C 0x2D 0x2E 0x2F )(list 0x680 0x6B4 0x6E8 0x71C 0x750 0x784 0x7B8 0x7EC 0x820 0x854 0x888 0x8BC 0x8F0 0x924 0x958 0x98C ) group.long ($2+0x2414)++0x3 line.long 0x0 "SEC_PER3_$1,This register is only used for resource manager to control secure access permission." bitfld.long 0x0 31. "DOM15_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM15_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM15_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM15_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM14_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM14_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM14_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM14_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM13_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM13_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM13_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM13_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM12_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM12_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM12_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM12_SEC_EN,Domain secure permission control enable" "0,1" repeat.end repeat 16. (list 0x30 0x31 0x32 0x33 0x34 0x35 0x36 0x37 0x38 0x39 0x3A 0x3B 0x3C 0x3D 0x3E 0x3F )(list 0x9C0 0x9F4 0xA28 0xA5C 0xA90 0xAC4 0xAF8 0xB2C 0xB60 0xB94 0xBC8 0xBFC 0xC30 0xC64 0xC98 0xCCC ) group.long ($2+0x2414)++0x3 line.long 0x0 "SEC_PER3_$1,This register is only used for resource manager to control secure access permission." bitfld.long 0x0 31. "DOM15_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM15_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM15_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM15_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM14_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM14_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM14_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM14_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM13_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM13_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM13_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM13_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM12_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM12_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM12_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM12_SEC_EN,Domain secure permission control enable" "0,1" repeat.end repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x34 0x68 0x9C 0xD0 0x104 0x138 0x16C 0x1A0 0x1D4 0x208 0x23C 0x270 0x2A4 0x2D8 0x30C ) group.long ($2+0x2418)++0x3 line.long 0x0 "PRI_PER0_$1,This register is only used for resource manager to control privileged access permission." bitfld.long 0x0 31. "DOM3_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM3_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM3_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM3_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM2_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM2_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM2_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM2_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM1_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM1_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM1_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM1_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM0_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM0_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM0_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM0_PRI_EN,Domain privileged permission control enable" "0,1" repeat.end repeat 16. (list 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1A 0x1B 0x1C 0x1D 0x1E 0x1F )(list 0x340 0x374 0x3A8 0x3DC 0x410 0x444 0x478 0x4AC 0x4E0 0x514 0x548 0x57C 0x5B0 0x5E4 0x618 0x64C ) group.long ($2+0x2418)++0x3 line.long 0x0 "PRI_PER0_$1,This register is only used for resource manager to control privileged access permission." bitfld.long 0x0 31. "DOM3_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM3_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM3_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM3_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM2_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM2_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM2_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM2_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM1_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM1_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM1_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM1_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM0_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM0_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM0_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM0_PRI_EN,Domain privileged permission control enable" "0,1" repeat.end repeat 16. (list 0x20 0x21 0x22 0x23 0x24 0x25 0x26 0x27 0x28 0x29 0x2A 0x2B 0x2C 0x2D 0x2E 0x2F )(list 0x680 0x6B4 0x6E8 0x71C 0x750 0x784 0x7B8 0x7EC 0x820 0x854 0x888 0x8BC 0x8F0 0x924 0x958 0x98C ) group.long ($2+0x2418)++0x3 line.long 0x0 "PRI_PER0_$1,This register is only used for resource manager to control privileged access permission." bitfld.long 0x0 31. "DOM3_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM3_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM3_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM3_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM2_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM2_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM2_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM2_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM1_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM1_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM1_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM1_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM0_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM0_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM0_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM0_PRI_EN,Domain privileged permission control enable" "0,1" repeat.end repeat 16. (list 0x30 0x31 0x32 0x33 0x34 0x35 0x36 0x37 0x38 0x39 0x3A 0x3B 0x3C 0x3D 0x3E 0x3F )(list 0x9C0 0x9F4 0xA28 0xA5C 0xA90 0xAC4 0xAF8 0xB2C 0xB60 0xB94 0xBC8 0xBFC 0xC30 0xC64 0xC98 0xCCC ) group.long ($2+0x2418)++0x3 line.long 0x0 "PRI_PER0_$1,This register is only used for resource manager to control privileged access permission." bitfld.long 0x0 31. "DOM3_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM3_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM3_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM3_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM2_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM2_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM2_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM2_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM1_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM1_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM1_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM1_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM0_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM0_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM0_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM0_PRI_EN,Domain privileged permission control enable" "0,1" repeat.end repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x34 0x68 0x9C 0xD0 0x104 0x138 0x16C 0x1A0 0x1D4 0x208 0x23C 0x270 0x2A4 0x2D8 0x30C ) group.long ($2+0x241C)++0x3 line.long 0x0 "PRI_PER1_$1,This register is only used for resource manager to control privileged access permission." bitfld.long 0x0 31. "DOM7_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM7_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM7_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM7_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM6_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM6_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM6_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM6_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM5_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM5_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM5_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM5_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM4_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM4_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM4_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM4_PRI_EN,Domain privileged permission control enable" "0,1" repeat.end repeat 16. (list 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1A 0x1B 0x1C 0x1D 0x1E 0x1F )(list 0x340 0x374 0x3A8 0x3DC 0x410 0x444 0x478 0x4AC 0x4E0 0x514 0x548 0x57C 0x5B0 0x5E4 0x618 0x64C ) group.long ($2+0x241C)++0x3 line.long 0x0 "PRI_PER1_$1,This register is only used for resource manager to control privileged access permission." bitfld.long 0x0 31. "DOM7_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM7_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM7_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM7_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM6_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM6_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM6_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM6_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM5_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM5_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM5_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM5_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM4_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM4_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM4_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM4_PRI_EN,Domain privileged permission control enable" "0,1" repeat.end repeat 16. (list 0x20 0x21 0x22 0x23 0x24 0x25 0x26 0x27 0x28 0x29 0x2A 0x2B 0x2C 0x2D 0x2E 0x2F )(list 0x680 0x6B4 0x6E8 0x71C 0x750 0x784 0x7B8 0x7EC 0x820 0x854 0x888 0x8BC 0x8F0 0x924 0x958 0x98C ) group.long ($2+0x241C)++0x3 line.long 0x0 "PRI_PER1_$1,This register is only used for resource manager to control privileged access permission." bitfld.long 0x0 31. "DOM7_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM7_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM7_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM7_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM6_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM6_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM6_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM6_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM5_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM5_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM5_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM5_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM4_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM4_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM4_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM4_PRI_EN,Domain privileged permission control enable" "0,1" repeat.end repeat 16. (list 0x30 0x31 0x32 0x33 0x34 0x35 0x36 0x37 0x38 0x39 0x3A 0x3B 0x3C 0x3D 0x3E 0x3F )(list 0x9C0 0x9F4 0xA28 0xA5C 0xA90 0xAC4 0xAF8 0xB2C 0xB60 0xB94 0xBC8 0xBFC 0xC30 0xC64 0xC98 0xCCC ) group.long ($2+0x241C)++0x3 line.long 0x0 "PRI_PER1_$1,This register is only used for resource manager to control privileged access permission." bitfld.long 0x0 31. "DOM7_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM7_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM7_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM7_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM6_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM6_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM6_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM6_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM5_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM5_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM5_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM5_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM4_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM4_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM4_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM4_PRI_EN,Domain privileged permission control enable" "0,1" repeat.end repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x34 0x68 0x9C 0xD0 0x104 0x138 0x16C 0x1A0 0x1D4 0x208 0x23C 0x270 0x2A4 0x2D8 0x30C ) group.long ($2+0x2420)++0x3 line.long 0x0 "PRI_PER2_$1,This register is only used for resource manager to control privileged access permission." bitfld.long 0x0 31. "DOM11_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM11_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM11_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM11_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM10_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM10_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM10_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM10_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM9_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM9_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM9_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM9_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM8_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM8_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM8_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM8_PRI_EN,Domain privileged permission control enable" "0,1" repeat.end repeat 16. (list 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1A 0x1B 0x1C 0x1D 0x1E 0x1F )(list 0x340 0x374 0x3A8 0x3DC 0x410 0x444 0x478 0x4AC 0x4E0 0x514 0x548 0x57C 0x5B0 0x5E4 0x618 0x64C ) group.long ($2+0x2420)++0x3 line.long 0x0 "PRI_PER2_$1,This register is only used for resource manager to control privileged access permission." bitfld.long 0x0 31. "DOM11_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM11_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM11_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM11_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM10_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM10_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM10_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM10_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM9_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM9_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM9_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM9_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM8_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM8_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM8_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM8_PRI_EN,Domain privileged permission control enable" "0,1" repeat.end repeat 16. (list 0x20 0x21 0x22 0x23 0x24 0x25 0x26 0x27 0x28 0x29 0x2A 0x2B 0x2C 0x2D 0x2E 0x2F )(list 0x680 0x6B4 0x6E8 0x71C 0x750 0x784 0x7B8 0x7EC 0x820 0x854 0x888 0x8BC 0x8F0 0x924 0x958 0x98C ) group.long ($2+0x2420)++0x3 line.long 0x0 "PRI_PER2_$1,This register is only used for resource manager to control privileged access permission." bitfld.long 0x0 31. "DOM11_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM11_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM11_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM11_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM10_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM10_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM10_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM10_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM9_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM9_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM9_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM9_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM8_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM8_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM8_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM8_PRI_EN,Domain privileged permission control enable" "0,1" repeat.end repeat 16. (list 0x30 0x31 0x32 0x33 0x34 0x35 0x36 0x37 0x38 0x39 0x3A 0x3B 0x3C 0x3D 0x3E 0x3F )(list 0x9C0 0x9F4 0xA28 0xA5C 0xA90 0xAC4 0xAF8 0xB2C 0xB60 0xB94 0xBC8 0xBFC 0xC30 0xC64 0xC98 0xCCC ) group.long ($2+0x2420)++0x3 line.long 0x0 "PRI_PER2_$1,This register is only used for resource manager to control privileged access permission." bitfld.long 0x0 31. "DOM11_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM11_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM11_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM11_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM10_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM10_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM10_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM10_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM9_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM9_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM9_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM9_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM8_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM8_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM8_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM8_PRI_EN,Domain privileged permission control enable" "0,1" repeat.end repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x34 0x68 0x9C 0xD0 0x104 0x138 0x16C 0x1A0 0x1D4 0x208 0x23C 0x270 0x2A4 0x2D8 0x30C ) group.long ($2+0x2424)++0x3 line.long 0x0 "PRI_PER3_$1,This register is only used for resource manager to control privileged access permission." bitfld.long 0x0 31. "DOM15_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM15_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM15_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM15_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM14_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM14_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM14_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM14_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM13_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM13_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM13_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM13_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM12_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM12_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM12_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM12_PRI_EN,Domain privileged permission control enable" "0,1" repeat.end repeat 16. (list 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1A 0x1B 0x1C 0x1D 0x1E 0x1F )(list 0x340 0x374 0x3A8 0x3DC 0x410 0x444 0x478 0x4AC 0x4E0 0x514 0x548 0x57C 0x5B0 0x5E4 0x618 0x64C ) group.long ($2+0x2424)++0x3 line.long 0x0 "PRI_PER3_$1,This register is only used for resource manager to control privileged access permission." bitfld.long 0x0 31. "DOM15_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM15_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM15_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM15_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM14_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM14_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM14_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM14_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM13_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM13_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM13_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM13_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM12_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM12_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM12_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM12_PRI_EN,Domain privileged permission control enable" "0,1" repeat.end repeat 16. (list 0x20 0x21 0x22 0x23 0x24 0x25 0x26 0x27 0x28 0x29 0x2A 0x2B 0x2C 0x2D 0x2E 0x2F )(list 0x680 0x6B4 0x6E8 0x71C 0x750 0x784 0x7B8 0x7EC 0x820 0x854 0x888 0x8BC 0x8F0 0x924 0x958 0x98C ) group.long ($2+0x2424)++0x3 line.long 0x0 "PRI_PER3_$1,This register is only used for resource manager to control privileged access permission." bitfld.long 0x0 31. "DOM15_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM15_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM15_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM15_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM14_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM14_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM14_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM14_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM13_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM13_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM13_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM13_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM12_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM12_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM12_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM12_PRI_EN,Domain privileged permission control enable" "0,1" repeat.end repeat 16. (list 0x30 0x31 0x32 0x33 0x34 0x35 0x36 0x37 0x38 0x39 0x3A 0x3B 0x3C 0x3D 0x3E 0x3F )(list 0x9C0 0x9F4 0xA28 0xA5C 0xA90 0xAC4 0xAF8 0xB2C 0xB60 0xB94 0xBC8 0xBFC 0xC30 0xC64 0xC98 0xCCC ) group.long ($2+0x2424)++0x3 line.long 0x0 "PRI_PER3_$1,This register is only used for resource manager to control privileged access permission." bitfld.long 0x0 31. "DOM15_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM15_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM15_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM15_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM14_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM14_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM14_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM14_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM13_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM13_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM13_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM13_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM12_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM12_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM12_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM12_PRI_EN,Domain privileged permission control enable" "0,1" repeat.end repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x34 0x68 0x9C 0xD0 0x104 0x138 0x16C 0x1A0 0x1D4 0x208 0x23C 0x270 0x2A4 0x2D8 0x30C ) group.long ($2+0x2428)++0x3 line.long 0x0 "DOM_SEC_PER_$1,This register is only used for domain master to control secure access permission. When the domain master write this register. it only changes the secure permission for itself. When the domain master read this register. it gets permission.." bitfld.long 0x0 7. "DOM_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" newline bitfld.long 0x0 0. "DOM_SEC_EN,Domain secure permission control enable" "0,1" repeat.end repeat 16. (list 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1A 0x1B 0x1C 0x1D 0x1E 0x1F )(list 0x340 0x374 0x3A8 0x3DC 0x410 0x444 0x478 0x4AC 0x4E0 0x514 0x548 0x57C 0x5B0 0x5E4 0x618 0x64C ) group.long ($2+0x2428)++0x3 line.long 0x0 "DOM_SEC_PER_$1,This register is only used for domain master to control secure access permission. When the domain master write this register. it only changes the secure permission for itself. When the domain master read this register. it gets permission.." bitfld.long 0x0 7. "DOM_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" newline bitfld.long 0x0 0. "DOM_SEC_EN,Domain secure permission control enable" "0,1" repeat.end repeat 16. (list 0x20 0x21 0x22 0x23 0x24 0x25 0x26 0x27 0x28 0x29 0x2A 0x2B 0x2C 0x2D 0x2E 0x2F )(list 0x680 0x6B4 0x6E8 0x71C 0x750 0x784 0x7B8 0x7EC 0x820 0x854 0x888 0x8BC 0x8F0 0x924 0x958 0x98C ) group.long ($2+0x2428)++0x3 line.long 0x0 "DOM_SEC_PER_$1,This register is only used for domain master to control secure access permission. When the domain master write this register. it only changes the secure permission for itself. When the domain master read this register. it gets permission.." bitfld.long 0x0 7. "DOM_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" newline bitfld.long 0x0 0. "DOM_SEC_EN,Domain secure permission control enable" "0,1" repeat.end repeat 16. (list 0x30 0x31 0x32 0x33 0x34 0x35 0x36 0x37 0x38 0x39 0x3A 0x3B 0x3C 0x3D 0x3E 0x3F )(list 0x9C0 0x9F4 0xA28 0xA5C 0xA90 0xAC4 0xAF8 0xB2C 0xB60 0xB94 0xBC8 0xBFC 0xC30 0xC64 0xC98 0xCCC ) group.long ($2+0x2428)++0x3 line.long 0x0 "DOM_SEC_PER_$1,This register is only used for domain master to control secure access permission. When the domain master write this register. it only changes the secure permission for itself. When the domain master read this register. it gets permission.." bitfld.long 0x0 7. "DOM_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" newline bitfld.long 0x0 0. "DOM_SEC_EN,Domain secure permission control enable" "0,1" repeat.end repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x34 0x68 0x9C 0xD0 0x104 0x138 0x16C 0x1A0 0x1D4 0x208 0x23C 0x270 0x2A4 0x2D8 0x30C ) group.long ($2+0x242C)++0x3 line.long 0x0 "DOM_PRI_PER_$1,This register is only used for domain master to control secure access permission. When the domain master write this register. it only changes the secure permission for itself. When the domain master read this register. it gets permission.." bitfld.long 0x0 7. "DOM_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" newline bitfld.long 0x0 0. "DOM_PRI_EN,Domain privileged permission control enable" "0,1" repeat.end repeat 16. (list 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1A 0x1B 0x1C 0x1D 0x1E 0x1F )(list 0x340 0x374 0x3A8 0x3DC 0x410 0x444 0x478 0x4AC 0x4E0 0x514 0x548 0x57C 0x5B0 0x5E4 0x618 0x64C ) group.long ($2+0x242C)++0x3 line.long 0x0 "DOM_PRI_PER_$1,This register is only used for domain master to control secure access permission. When the domain master write this register. it only changes the secure permission for itself. When the domain master read this register. it gets permission.." bitfld.long 0x0 7. "DOM_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" newline bitfld.long 0x0 0. "DOM_PRI_EN,Domain privileged permission control enable" "0,1" repeat.end repeat 16. (list 0x20 0x21 0x22 0x23 0x24 0x25 0x26 0x27 0x28 0x29 0x2A 0x2B 0x2C 0x2D 0x2E 0x2F )(list 0x680 0x6B4 0x6E8 0x71C 0x750 0x784 0x7B8 0x7EC 0x820 0x854 0x888 0x8BC 0x8F0 0x924 0x958 0x98C ) group.long ($2+0x242C)++0x3 line.long 0x0 "DOM_PRI_PER_$1,This register is only used for domain master to control secure access permission. When the domain master write this register. it only changes the secure permission for itself. When the domain master read this register. it gets permission.." bitfld.long 0x0 7. "DOM_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" newline bitfld.long 0x0 0. "DOM_PRI_EN,Domain privileged permission control enable" "0,1" repeat.end repeat 16. (list 0x30 0x31 0x32 0x33 0x34 0x35 0x36 0x37 0x38 0x39 0x3A 0x3B 0x3C 0x3D 0x3E 0x3F )(list 0x9C0 0x9F4 0xA28 0xA5C 0xA90 0xAC4 0xAF8 0xB2C 0xB60 0xB94 0xBC8 0xBFC 0xC30 0xC64 0xC98 0xCCC ) group.long ($2+0x242C)++0x3 line.long 0x0 "DOM_PRI_PER_$1,This register is only used for domain master to control secure access permission. When the domain master write this register. it only changes the secure permission for itself. When the domain master read this register. it gets permission.." bitfld.long 0x0 7. "DOM_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" newline bitfld.long 0x0 0. "DOM_PRI_EN,Domain privileged permission control enable" "0,1" repeat.end repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x34 0x68 0x9C 0xD0 0x104 0x138 0x16C 0x1A0 0x1D4 0x208 0x23C 0x270 0x2A4 0x2D8 0x30C ) group.long ($2+0x2430)++0x3 line.long 0x0 "DOM_ASSIGN_$1,Use to assign domain for accessing DOM_SEC_PER and DOM_PRI_PER register. Only resource manager. group manager and domain owner can access this register. For write. group manager must write its owen domain ID. otherwise write accessing will.." hexmask.long.byte 0x0 0.--3. 1. "DID,accessing DOM_SEC_PER and DOM_PRI_PER register" repeat.end repeat 16. (list 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1A 0x1B 0x1C 0x1D 0x1E 0x1F )(list 0x340 0x374 0x3A8 0x3DC 0x410 0x444 0x478 0x4AC 0x4E0 0x514 0x548 0x57C 0x5B0 0x5E4 0x618 0x64C ) group.long ($2+0x2430)++0x3 line.long 0x0 "DOM_ASSIGN_$1,Use to assign domain for accessing DOM_SEC_PER and DOM_PRI_PER register. Only resource manager. group manager and domain owner can access this register. For write. group manager must write its owen domain ID. otherwise write accessing will.." hexmask.long.byte 0x0 0.--3. 1. "DID,accessing DOM_SEC_PER and DOM_PRI_PER register" repeat.end repeat 16. (list 0x20 0x21 0x22 0x23 0x24 0x25 0x26 0x27 0x28 0x29 0x2A 0x2B 0x2C 0x2D 0x2E 0x2F )(list 0x680 0x6B4 0x6E8 0x71C 0x750 0x784 0x7B8 0x7EC 0x820 0x854 0x888 0x8BC 0x8F0 0x924 0x958 0x98C ) group.long ($2+0x2430)++0x3 line.long 0x0 "DOM_ASSIGN_$1,Use to assign domain for accessing DOM_SEC_PER and DOM_PRI_PER register. Only resource manager. group manager and domain owner can access this register. For write. group manager must write its owen domain ID. otherwise write accessing will.." hexmask.long.byte 0x0 0.--3. 1. "DID,accessing DOM_SEC_PER and DOM_PRI_PER register" repeat.end repeat 16. (list 0x30 0x31 0x32 0x33 0x34 0x35 0x36 0x37 0x38 0x39 0x3A 0x3B 0x3C 0x3D 0x3E 0x3F )(list 0x9C0 0x9F4 0xA28 0xA5C 0xA90 0xAC4 0xAF8 0xB2C 0xB60 0xB94 0xBC8 0xBFC 0xC30 0xC64 0xC98 0xCCC ) group.long ($2+0x2430)++0x3 line.long 0x0 "DOM_ASSIGN_$1,Use to assign domain for accessing DOM_SEC_PER and DOM_PRI_PER register. Only resource manager. group manager and domain owner can access this register. For write. group manager must write its owen domain ID. otherwise write accessing will.." hexmask.long.byte 0x0 0.--3. 1. "DID,accessing DOM_SEC_PER and DOM_PRI_PER register" repeat.end repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x38 0x70 0xA8 0xE0 0x118 0x150 0x188 0x1C0 0x1F8 0x230 0x268 0x2A0 0x2D8 0x310 0x348 ) group.long ($2+0x3100)++0x3 line.long 0x0 "RGN_DOM_$1,Assign domain for peripheral. It can be only configured by resource and group manager" bitfld.long 0x0 31. "LOCK,When this bit is set lock write for all the bits in the register." "0,1" bitfld.long 0x0 4. "SET,Set together with DID would change permission of this resource to following setting: 1) Domain access control enabled. 2) Read/Write allowed for the domain owner. 3) Read/Write not allowed for all the other domains. If this bit is not set only DID.." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Assign domain for peripheral" repeat.end repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x38 0x70 0xA8 0xE0 0x118 0x150 0x188 0x1C0 0x1F8 0x230 0x268 0x2A0 0x2D8 0x310 0x348 ) group.long ($2+0x3104)++0x3 line.long 0x0 "RGN_DOM_PER0_$1,Domain Permission Control. It can be only configured by resource manager and domain owner." bitfld.long 0x0 31. "DOM7_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 29.--30. "DOM7_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 28. "DOM7_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 27. "DOM6_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 25.--26. "DOM6_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" newline bitfld.long 0x0 24. "DOM6_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 23. "DOM5_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 21.--22. "DOM5_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 20. "DOM5_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 19. "DOM4_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" newline bitfld.long 0x0 17.--18. "DOM4_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM4_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 15. "DOM3_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 13.--14. "DOM3_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 12. "DOM3_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" newline bitfld.long 0x0 11. "DOM2_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 9.--10. "DOM2_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM2_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 7. "DOM1_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 5.--6. "DOM1_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" newline bitfld.long 0x0 4. "DOM1_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 3. "DOM0_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 1.--2. "DOM0_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM0_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" repeat.end repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x38 0x70 0xA8 0xE0 0x118 0x150 0x188 0x1C0 0x1F8 0x230 0x268 0x2A0 0x2D8 0x310 0x348 ) group.long ($2+0x3108)++0x3 line.long 0x0 "RGN_DOM_PER1_$1,Domain Permission Control. It can be only configured by resource manager and domain owner." bitfld.long 0x0 31. "DOM15_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 29.--30. "DOM15_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 28. "DOM15_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 27. "DOM14_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 25.--26. "DOM14_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" newline bitfld.long 0x0 24. "DOM14_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 23. "DOM13_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 21.--22. "DOM13_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 20. "DOM13_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 19. "DOM12_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" newline bitfld.long 0x0 17.--18. "DOM12_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM12_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 15. "DOM11_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 13.--14. "DOM11_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 12. "DOM11_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" newline bitfld.long 0x0 11. "DOM10_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 9.--10. "DOM10_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM10_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 7. "DOM9_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 5.--6. "DOM9_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" newline bitfld.long 0x0 4. "DOM9_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 3. "DOM8_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 1.--2. "DOM8_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM8_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" repeat.end repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x38 0x70 0xA8 0xE0 0x118 0x150 0x188 0x1C0 0x1F8 0x230 0x268 0x2A0 0x2D8 0x310 0x348 ) group.long ($2+0x310C)++0x3 line.long 0x0 "RGN_SEC_PER0_$1,This register is only used for resource manager to control secure access permission." bitfld.long 0x0 31. "DOM3_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM3_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM3_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM3_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM2_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM2_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM2_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM2_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM1_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM1_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM1_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM1_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM0_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM0_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM0_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM0_SEC_EN,Domain secure permission control enable" "0,1" repeat.end repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x38 0x70 0xA8 0xE0 0x118 0x150 0x188 0x1C0 0x1F8 0x230 0x268 0x2A0 0x2D8 0x310 0x348 ) group.long ($2+0x3110)++0x3 line.long 0x0 "RGN_SEC_PER1_$1,This register is only used for resource manager to control secure access permission." bitfld.long 0x0 31. "DOM7_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM7_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM7_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM7_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM6_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM6_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM6_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM6_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM5_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM5_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM5_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM5_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM4_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM4_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM4_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM4_SEC_EN,Domain secure permission control enable" "0,1" repeat.end repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x38 0x70 0xA8 0xE0 0x118 0x150 0x188 0x1C0 0x1F8 0x230 0x268 0x2A0 0x2D8 0x310 0x348 ) group.long ($2+0x3114)++0x3 line.long 0x0 "RGN_SEC_PER2_$1,This register is only used for resource manager to control secure access permission." bitfld.long 0x0 31. "DOM11_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM11_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM11_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM11_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM10_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM10_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM10_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM10_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM9_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM9_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM9_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM9_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM8_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM8_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM8_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM8_SEC_EN,Domain secure permission control enable" "0,1" repeat.end repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x38 0x70 0xA8 0xE0 0x118 0x150 0x188 0x1C0 0x1F8 0x230 0x268 0x2A0 0x2D8 0x310 0x348 ) group.long ($2+0x3118)++0x3 line.long 0x0 "RGN_SEC_PER3_$1,This register is only used for resource manager to control secure access permission." bitfld.long 0x0 31. "DOM15_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM15_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM15_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM15_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM14_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM14_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM14_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM14_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM13_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM13_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM13_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM13_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM12_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM12_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM12_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM12_SEC_EN,Domain secure permission control enable" "0,1" repeat.end repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x38 0x70 0xA8 0xE0 0x118 0x150 0x188 0x1C0 0x1F8 0x230 0x268 0x2A0 0x2D8 0x310 0x348 ) group.long ($2+0x311C)++0x3 line.long 0x0 "RGN_PRI_PER0_$1,This register is only used for resource manager to control privileged access permission." bitfld.long 0x0 31. "DOM3_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM3_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM3_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM3_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM2_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM2_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM2_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM2_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM1_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM1_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM1_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM1_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM0_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM0_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM0_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM0_PRI_EN,Domain privileged permission control enable" "0,1" repeat.end repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x38 0x70 0xA8 0xE0 0x118 0x150 0x188 0x1C0 0x1F8 0x230 0x268 0x2A0 0x2D8 0x310 0x348 ) group.long ($2+0x3120)++0x3 line.long 0x0 "RGN_PRI_PER1_$1,This register is only used for resource manager to control privileged access permission." bitfld.long 0x0 31. "DOM7_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM7_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM7_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM7_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM6_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM6_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM6_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM6_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM5_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM5_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM5_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM5_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM4_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM4_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM4_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM4_PRI_EN,Domain privileged permission control enable" "0,1" repeat.end repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x38 0x70 0xA8 0xE0 0x118 0x150 0x188 0x1C0 0x1F8 0x230 0x268 0x2A0 0x2D8 0x310 0x348 ) group.long ($2+0x3124)++0x3 line.long 0x0 "RGN_PRI_PER2_$1,This register is only used for resource manager to control privileged access permission." bitfld.long 0x0 31. "DOM11_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM11_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM11_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM11_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM10_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM10_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM10_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM10_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM9_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM9_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM9_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM9_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM8_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM8_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM8_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM8_PRI_EN,Domain privileged permission control enable" "0,1" repeat.end repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x38 0x70 0xA8 0xE0 0x118 0x150 0x188 0x1C0 0x1F8 0x230 0x268 0x2A0 0x2D8 0x310 0x348 ) group.long ($2+0x3128)++0x3 line.long 0x0 "RGN_PRI_PER3_$1,This register is only used for resource manager to control privileged access permission." bitfld.long 0x0 31. "DOM15_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM15_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM15_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM15_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM14_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM14_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM14_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM14_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM13_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM13_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM13_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM13_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM12_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM12_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM12_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM12_PRI_EN,Domain privileged permission control enable" "0,1" repeat.end repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x38 0x70 0xA8 0xE0 0x118 0x150 0x188 0x1C0 0x1F8 0x230 0x268 0x2A0 0x2D8 0x310 0x348 ) group.long ($2+0x312C)++0x3 line.long 0x0 "RGN_DOM_SEC_PER_$1,This register is only used for domain master to control secure access permission. When the domain master write this register. it only changes the secure permission for itself. When the domain master read this register. it gets.." bitfld.long 0x0 7. "DOM_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" newline bitfld.long 0x0 0. "DOM_SEC_EN,Domain secure permission control enable" "0,1" repeat.end repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x38 0x70 0xA8 0xE0 0x118 0x150 0x188 0x1C0 0x1F8 0x230 0x268 0x2A0 0x2D8 0x310 0x348 ) group.long ($2+0x3130)++0x3 line.long 0x0 "RGN_DOM_PRI_PER_$1,This register is only used for domain master to control secure access permission. When the domain master write this register. it only changes the secure permission for itself. When the domain master read this register. it gets.." bitfld.long 0x0 7. "DOM_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" newline bitfld.long 0x0 0. "DOM_PRI_EN,Domain privileged permission control enable" "0,1" repeat.end repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x38 0x70 0xA8 0xE0 0x118 0x150 0x188 0x1C0 0x1F8 0x230 0x268 0x2A0 0x2D8 0x310 0x348 ) group.long ($2+0x3134)++0x3 line.long 0x0 "RGN_DOM_ASSIGN_$1,Use to assign domain for accessing DOM_SEC_PER and DOM_PRI_PER register. Only resource manager. group manager and domain owner can access this register. For write. group manager must write its owen domain ID. otherwise write accessing.." hexmask.long.byte 0x0 0.--3. 1. "DID,accessing DOM_SEC_PER and DOM_PRI_PER register" repeat.end tree.end tree "RPC_AP_CLKGEN" base ad:0x38800000 repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x4 0x8 0xC 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C ) group.long ($2)++0x3 line.long 0x0 "REGG0_DOM_$1,Assign domain for CKGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1A 0x1B 0x1C 0x1D 0x1E 0x1F )(list 0x40 0x44 0x48 0x4C 0x50 0x54 0x58 0x5C 0x60 0x64 0x68 0x6C 0x70 0x74 0x78 0x7C ) group.long ($2)++0x3 line.long 0x0 "REGG0_DOM_$1,Assign domain for CKGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x20 0x21 0x22 0x23 0x24 0x25 0x26 0x27 0x28 0x29 0x2A 0x2B 0x2C 0x2D 0x2E 0x2F )(list 0x80 0x84 0x88 0x8C 0x90 0x94 0x98 0x9C 0xA0 0xA4 0xA8 0xAC 0xB0 0xB4 0xB8 0xBC ) group.long ($2)++0x3 line.long 0x0 "REGG0_DOM_$1,Assign domain for CKGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x30 0x31 0x32 0x33 0x34 0x35 0x36 0x37 0x38 0x39 0x3A 0x3B 0x3C 0x3D 0x3E 0x3F )(list 0xC0 0xC4 0xC8 0xCC 0xD0 0xD4 0xD8 0xDC 0xE0 0xE4 0xE8 0xEC 0xF0 0xF4 0xF8 0xFC ) group.long ($2)++0x3 line.long 0x0 "REGG0_DOM_$1,Assign domain for CKGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x40 0x41 0x42 0x43 0x44 0x45 0x46 0x47 0x48 0x49 0x4A 0x4B 0x4C 0x4D 0x4E 0x4F )(list 0x100 0x104 0x108 0x10C 0x110 0x114 0x118 0x11C 0x120 0x124 0x128 0x12C 0x130 0x134 0x138 0x13C ) group.long ($2)++0x3 line.long 0x0 "REGG0_DOM_$1,Assign domain for CKGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x50 0x51 0x52 0x53 0x54 0x55 0x56 0x57 0x58 0x59 0x5A 0x5B 0x5C 0x5D 0x5E 0x5F )(list 0x140 0x144 0x148 0x14C 0x150 0x154 0x158 0x15C 0x160 0x164 0x168 0x16C 0x170 0x174 0x178 0x17C ) group.long ($2)++0x3 line.long 0x0 "REGG0_DOM_$1,Assign domain for CKGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x60 0x61 0x62 0x63 0x64 0x65 0x66 0x67 0x68 0x69 0x6A 0x6B 0x6C 0x6D 0x6E 0x6F )(list 0x180 0x184 0x188 0x18C 0x190 0x194 0x198 0x19C 0x1A0 0x1A4 0x1A8 0x1AC 0x1B0 0x1B4 0x1B8 0x1BC ) group.long ($2)++0x3 line.long 0x0 "REGG0_DOM_$1,Assign domain for CKGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x70 0x71 0x72 0x73 0x74 0x75 0x76 0x77 0x78 0x79 0x7A 0x7B 0x7C 0x7D 0x7E 0x7F )(list 0x1C0 0x1C4 0x1C8 0x1CC 0x1D0 0x1D4 0x1D8 0x1DC 0x1E0 0x1E4 0x1E8 0x1EC 0x1F0 0x1F4 0x1F8 0x1FC ) group.long ($2)++0x3 line.long 0x0 "REGG0_DOM_$1,Assign domain for CKGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x80 0x81 0x82 0x83 0x84 0x85 0x86 0x87 0x88 0x89 0x8A 0x8B 0x8C 0x8D 0x8E 0x8F )(list 0x200 0x204 0x208 0x20C 0x210 0x214 0x218 0x21C 0x220 0x224 0x228 0x22C 0x230 0x234 0x238 0x23C ) group.long ($2)++0x3 line.long 0x0 "REGG0_DOM_$1,Assign domain for CKGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x90 0x91 0x92 0x93 0x94 0x95 0x96 0x97 0x98 0x99 0x9A 0x9B 0x9C 0x9D 0x9E 0x9F )(list 0x240 0x244 0x248 0x24C 0x250 0x254 0x258 0x25C 0x260 0x264 0x268 0x26C 0x270 0x274 0x278 0x27C ) group.long ($2)++0x3 line.long 0x0 "REGG0_DOM_$1,Assign domain for CKGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xA0 0xA1 0xA2 0xA3 0xA4 0xA5 0xA6 0xA7 0xA8 0xA9 0xAA 0xAB 0xAC 0xAD 0xAE 0xAF )(list 0x280 0x284 0x288 0x28C 0x290 0x294 0x298 0x29C 0x2A0 0x2A4 0x2A8 0x2AC 0x2B0 0x2B4 0x2B8 0x2BC ) group.long ($2)++0x3 line.long 0x0 "REGG0_DOM_$1,Assign domain for CKGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xB0 0xB1 0xB2 0xB3 0xB4 0xB5 0xB6 0xB7 0xB8 0xB9 0xBA 0xBB 0xBC 0xBD 0xBE 0xBF )(list 0x2C0 0x2C4 0x2C8 0x2CC 0x2D0 0x2D4 0x2D8 0x2DC 0x2E0 0x2E4 0x2E8 0x2EC 0x2F0 0x2F4 0x2F8 0x2FC ) group.long ($2)++0x3 line.long 0x0 "REGG0_DOM_$1,Assign domain for CKGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xC0 0xC1 0xC2 0xC3 0xC4 0xC5 0xC6 0xC7 0xC8 0xC9 0xCA 0xCB 0xCC 0xCD 0xCE 0xCF )(list 0x300 0x304 0x308 0x30C 0x310 0x314 0x318 0x31C 0x320 0x324 0x328 0x32C 0x330 0x334 0x338 0x33C ) group.long ($2)++0x3 line.long 0x0 "REGG0_DOM_$1,Assign domain for CKGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xD0 0xD1 0xD2 0xD3 0xD4 0xD5 0xD6 0xD7 0xD8 0xD9 0xDA 0xDB 0xDC 0xDD 0xDE 0xDF )(list 0x340 0x344 0x348 0x34C 0x350 0x354 0x358 0x35C 0x360 0x364 0x368 0x36C 0x370 0x374 0x378 0x37C ) group.long ($2)++0x3 line.long 0x0 "REGG0_DOM_$1,Assign domain for CKGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xE0 0xE1 0xE2 0xE3 0xE4 0xE5 0xE6 0xE7 0xE8 0xE9 0xEA 0xEB 0xEC 0xED 0xEE 0xEF )(list 0x380 0x384 0x388 0x38C 0x390 0x394 0x398 0x39C 0x3A0 0x3A4 0x3A8 0x3AC 0x3B0 0x3B4 0x3B8 0x3BC ) group.long ($2)++0x3 line.long 0x0 "REGG0_DOM_$1,Assign domain for CKGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xF0 0xF1 0xF2 0xF3 0xF4 0xF5 0xF6 0xF7 0xF8 0xF9 0xFA 0xFB 0xFC 0xFD 0xFE 0xFF )(list 0x3C0 0x3C4 0x3C8 0x3CC 0x3D0 0x3D4 0x3D8 0x3DC 0x3E0 0x3E4 0x3E8 0x3EC 0x3F0 0x3F4 0x3F8 0x3FC ) group.long ($2)++0x3 line.long 0x0 "REGG0_DOM_$1,Assign domain for CKGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x4 0x8 0xC 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C ) group.long ($2+0x400)++0x3 line.long 0x0 "REGG1_DOM_$1,Assign domain for CKGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1A 0x1B 0x1C 0x1D 0x1E 0x1F )(list 0x40 0x44 0x48 0x4C 0x50 0x54 0x58 0x5C 0x60 0x64 0x68 0x6C 0x70 0x74 0x78 0x7C ) group.long ($2+0x400)++0x3 line.long 0x0 "REGG1_DOM_$1,Assign domain for CKGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x20 0x21 0x22 0x23 0x24 0x25 0x26 0x27 0x28 0x29 0x2A 0x2B 0x2C 0x2D 0x2E 0x2F )(list 0x80 0x84 0x88 0x8C 0x90 0x94 0x98 0x9C 0xA0 0xA4 0xA8 0xAC 0xB0 0xB4 0xB8 0xBC ) group.long ($2+0x400)++0x3 line.long 0x0 "REGG1_DOM_$1,Assign domain for CKGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x30 0x31 0x32 0x33 0x34 0x35 0x36 0x37 0x38 0x39 0x3A 0x3B 0x3C 0x3D 0x3E 0x3F )(list 0xC0 0xC4 0xC8 0xCC 0xD0 0xD4 0xD8 0xDC 0xE0 0xE4 0xE8 0xEC 0xF0 0xF4 0xF8 0xFC ) group.long ($2+0x400)++0x3 line.long 0x0 "REGG1_DOM_$1,Assign domain for CKGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x40 0x41 0x42 0x43 0x44 0x45 0x46 0x47 0x48 0x49 0x4A 0x4B 0x4C 0x4D 0x4E 0x4F )(list 0x100 0x104 0x108 0x10C 0x110 0x114 0x118 0x11C 0x120 0x124 0x128 0x12C 0x130 0x134 0x138 0x13C ) group.long ($2+0x400)++0x3 line.long 0x0 "REGG1_DOM_$1,Assign domain for CKGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x50 0x51 0x52 0x53 0x54 0x55 0x56 0x57 0x58 0x59 0x5A 0x5B 0x5C 0x5D 0x5E 0x5F )(list 0x140 0x144 0x148 0x14C 0x150 0x154 0x158 0x15C 0x160 0x164 0x168 0x16C 0x170 0x174 0x178 0x17C ) group.long ($2+0x400)++0x3 line.long 0x0 "REGG1_DOM_$1,Assign domain for CKGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x60 0x61 0x62 0x63 0x64 0x65 0x66 0x67 0x68 0x69 0x6A 0x6B 0x6C 0x6D 0x6E 0x6F )(list 0x180 0x184 0x188 0x18C 0x190 0x194 0x198 0x19C 0x1A0 0x1A4 0x1A8 0x1AC 0x1B0 0x1B4 0x1B8 0x1BC ) group.long ($2+0x400)++0x3 line.long 0x0 "REGG1_DOM_$1,Assign domain for CKGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x70 0x71 0x72 0x73 0x74 0x75 0x76 0x77 0x78 0x79 0x7A 0x7B 0x7C 0x7D 0x7E 0x7F )(list 0x1C0 0x1C4 0x1C8 0x1CC 0x1D0 0x1D4 0x1D8 0x1DC 0x1E0 0x1E4 0x1E8 0x1EC 0x1F0 0x1F4 0x1F8 0x1FC ) group.long ($2+0x400)++0x3 line.long 0x0 "REGG1_DOM_$1,Assign domain for CKGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x80 0x81 0x82 0x83 0x84 0x85 0x86 0x87 0x88 0x89 0x8A 0x8B 0x8C 0x8D 0x8E 0x8F )(list 0x200 0x204 0x208 0x20C 0x210 0x214 0x218 0x21C 0x220 0x224 0x228 0x22C 0x230 0x234 0x238 0x23C ) group.long ($2+0x400)++0x3 line.long 0x0 "REGG1_DOM_$1,Assign domain for CKGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x90 0x91 0x92 0x93 0x94 0x95 0x96 0x97 0x98 0x99 0x9A 0x9B 0x9C 0x9D 0x9E 0x9F )(list 0x240 0x244 0x248 0x24C 0x250 0x254 0x258 0x25C 0x260 0x264 0x268 0x26C 0x270 0x274 0x278 0x27C ) group.long ($2+0x400)++0x3 line.long 0x0 "REGG1_DOM_$1,Assign domain for CKGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xA0 0xA1 0xA2 0xA3 0xA4 0xA5 0xA6 0xA7 0xA8 0xA9 0xAA 0xAB 0xAC 0xAD 0xAE 0xAF )(list 0x280 0x284 0x288 0x28C 0x290 0x294 0x298 0x29C 0x2A0 0x2A4 0x2A8 0x2AC 0x2B0 0x2B4 0x2B8 0x2BC ) group.long ($2+0x400)++0x3 line.long 0x0 "REGG1_DOM_$1,Assign domain for CKGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xB0 0xB1 0xB2 0xB3 0xB4 0xB5 0xB6 0xB7 0xB8 0xB9 0xBA 0xBB 0xBC 0xBD 0xBE 0xBF )(list 0x2C0 0x2C4 0x2C8 0x2CC 0x2D0 0x2D4 0x2D8 0x2DC 0x2E0 0x2E4 0x2E8 0x2EC 0x2F0 0x2F4 0x2F8 0x2FC ) group.long ($2+0x400)++0x3 line.long 0x0 "REGG1_DOM_$1,Assign domain for CKGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xC0 0xC1 0xC2 0xC3 0xC4 0xC5 0xC6 0xC7 0xC8 0xC9 0xCA 0xCB 0xCC 0xCD 0xCE 0xCF )(list 0x300 0x304 0x308 0x30C 0x310 0x314 0x318 0x31C 0x320 0x324 0x328 0x32C 0x330 0x334 0x338 0x33C ) group.long ($2+0x400)++0x3 line.long 0x0 "REGG1_DOM_$1,Assign domain for CKGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xD0 0xD1 0xD2 0xD3 0xD4 0xD5 0xD6 0xD7 0xD8 0xD9 0xDA 0xDB 0xDC 0xDD 0xDE 0xDF )(list 0x340 0x344 0x348 0x34C 0x350 0x354 0x358 0x35C 0x360 0x364 0x368 0x36C 0x370 0x374 0x378 0x37C ) group.long ($2+0x400)++0x3 line.long 0x0 "REGG1_DOM_$1,Assign domain for CKGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xE0 0xE1 0xE2 0xE3 0xE4 0xE5 0xE6 0xE7 0xE8 0xE9 0xEA 0xEB 0xEC 0xED 0xEE 0xEF )(list 0x380 0x384 0x388 0x38C 0x390 0x394 0x398 0x39C 0x3A0 0x3A4 0x3A8 0x3AC 0x3B0 0x3B4 0x3B8 0x3BC ) group.long ($2+0x400)++0x3 line.long 0x0 "REGG1_DOM_$1,Assign domain for CKGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xF0 0xF1 0xF2 0xF3 0xF4 0xF5 0xF6 0xF7 0xF8 0xF9 0xFA 0xFB 0xFC 0xFD 0xFE 0xFF )(list 0x3C0 0x3C4 0x3C8 0x3CC 0x3D0 0x3D4 0x3D8 0x3DC 0x3E0 0x3E4 0x3E8 0x3EC 0x3F0 0x3F4 0x3F8 0x3FC ) group.long ($2+0x400)++0x3 line.long 0x0 "REGG1_DOM_$1,Assign domain for CKGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x4 0x8 0xC 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C ) group.long ($2+0x800)++0x3 line.long 0x0 "REGG2_DOM_$1,Assign domain for SCR registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1A 0x1B 0x1C 0x1D 0x1E 0x1F )(list 0x40 0x44 0x48 0x4C 0x50 0x54 0x58 0x5C 0x60 0x64 0x68 0x6C 0x70 0x74 0x78 0x7C ) group.long ($2+0x800)++0x3 line.long 0x0 "REGG2_DOM_$1,Assign domain for SCR registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x20 0x21 0x22 0x23 0x24 0x25 0x26 0x27 0x28 0x29 0x2A 0x2B 0x2C 0x2D 0x2E 0x2F )(list 0x80 0x84 0x88 0x8C 0x90 0x94 0x98 0x9C 0xA0 0xA4 0xA8 0xAC 0xB0 0xB4 0xB8 0xBC ) group.long ($2+0x800)++0x3 line.long 0x0 "REGG2_DOM_$1,Assign domain for SCR registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x30 0x31 0x32 0x33 0x34 0x35 0x36 0x37 0x38 0x39 0x3A 0x3B 0x3C 0x3D 0x3E 0x3F )(list 0xC0 0xC4 0xC8 0xCC 0xD0 0xD4 0xD8 0xDC 0xE0 0xE4 0xE8 0xEC 0xF0 0xF4 0xF8 0xFC ) group.long ($2+0x800)++0x3 line.long 0x0 "REGG2_DOM_$1,Assign domain for SCR registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x40 0x41 0x42 0x43 0x44 0x45 0x46 0x47 0x48 0x49 0x4A 0x4B 0x4C 0x4D 0x4E 0x4F )(list 0x100 0x104 0x108 0x10C 0x110 0x114 0x118 0x11C 0x120 0x124 0x128 0x12C 0x130 0x134 0x138 0x13C ) group.long ($2+0x800)++0x3 line.long 0x0 "REGG2_DOM_$1,Assign domain for SCR registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x50 0x51 0x52 0x53 0x54 0x55 0x56 0x57 0x58 0x59 0x5A 0x5B 0x5C 0x5D 0x5E 0x5F )(list 0x140 0x144 0x148 0x14C 0x150 0x154 0x158 0x15C 0x160 0x164 0x168 0x16C 0x170 0x174 0x178 0x17C ) group.long ($2+0x800)++0x3 line.long 0x0 "REGG2_DOM_$1,Assign domain for SCR registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x60 0x61 0x62 0x63 0x64 0x65 0x66 0x67 0x68 0x69 0x6A 0x6B 0x6C 0x6D 0x6E 0x6F )(list 0x180 0x184 0x188 0x18C 0x190 0x194 0x198 0x19C 0x1A0 0x1A4 0x1A8 0x1AC 0x1B0 0x1B4 0x1B8 0x1BC ) group.long ($2+0x800)++0x3 line.long 0x0 "REGG2_DOM_$1,Assign domain for SCR registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x70 0x71 0x72 0x73 0x74 0x75 0x76 0x77 0x78 0x79 0x7A 0x7B 0x7C 0x7D 0x7E 0x7F )(list 0x1C0 0x1C4 0x1C8 0x1CC 0x1D0 0x1D4 0x1D8 0x1DC 0x1E0 0x1E4 0x1E8 0x1EC 0x1F0 0x1F4 0x1F8 0x1FC ) group.long ($2+0x800)++0x3 line.long 0x0 "REGG2_DOM_$1,Assign domain for SCR registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x80 0x81 0x82 0x83 0x84 0x85 0x86 0x87 0x88 0x89 0x8A 0x8B 0x8C 0x8D 0x8E 0x8F )(list 0x200 0x204 0x208 0x20C 0x210 0x214 0x218 0x21C 0x220 0x224 0x228 0x22C 0x230 0x234 0x238 0x23C ) group.long ($2+0x800)++0x3 line.long 0x0 "REGG2_DOM_$1,Assign domain for SCR registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x90 0x91 0x92 0x93 0x94 0x95 0x96 0x97 0x98 0x99 0x9A 0x9B 0x9C 0x9D 0x9E 0x9F )(list 0x240 0x244 0x248 0x24C 0x250 0x254 0x258 0x25C 0x260 0x264 0x268 0x26C 0x270 0x274 0x278 0x27C ) group.long ($2+0x800)++0x3 line.long 0x0 "REGG2_DOM_$1,Assign domain for SCR registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xA0 0xA1 0xA2 0xA3 0xA4 0xA5 0xA6 0xA7 0xA8 0xA9 0xAA 0xAB 0xAC 0xAD 0xAE 0xAF )(list 0x280 0x284 0x288 0x28C 0x290 0x294 0x298 0x29C 0x2A0 0x2A4 0x2A8 0x2AC 0x2B0 0x2B4 0x2B8 0x2BC ) group.long ($2+0x800)++0x3 line.long 0x0 "REGG2_DOM_$1,Assign domain for SCR registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xB0 0xB1 0xB2 0xB3 0xB4 0xB5 0xB6 0xB7 0xB8 0xB9 0xBA 0xBB 0xBC 0xBD 0xBE 0xBF )(list 0x2C0 0x2C4 0x2C8 0x2CC 0x2D0 0x2D4 0x2D8 0x2DC 0x2E0 0x2E4 0x2E8 0x2EC 0x2F0 0x2F4 0x2F8 0x2FC ) group.long ($2+0x800)++0x3 line.long 0x0 "REGG2_DOM_$1,Assign domain for SCR registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xC0 0xC1 0xC2 0xC3 0xC4 0xC5 0xC6 0xC7 0xC8 0xC9 0xCA 0xCB 0xCC 0xCD 0xCE 0xCF )(list 0x300 0x304 0x308 0x30C 0x310 0x314 0x318 0x31C 0x320 0x324 0x328 0x32C 0x330 0x334 0x338 0x33C ) group.long ($2+0x800)++0x3 line.long 0x0 "REGG2_DOM_$1,Assign domain for SCR registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xD0 0xD1 0xD2 0xD3 0xD4 0xD5 0xD6 0xD7 0xD8 0xD9 0xDA 0xDB 0xDC 0xDD 0xDE 0xDF )(list 0x340 0x344 0x348 0x34C 0x350 0x354 0x358 0x35C 0x360 0x364 0x368 0x36C 0x370 0x374 0x378 0x37C ) group.long ($2+0x800)++0x3 line.long 0x0 "REGG2_DOM_$1,Assign domain for SCR registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xE0 0xE1 0xE2 0xE3 0xE4 0xE5 0xE6 0xE7 0xE8 0xE9 0xEA 0xEB 0xEC 0xED 0xEE 0xEF )(list 0x380 0x384 0x388 0x38C 0x390 0x394 0x398 0x39C 0x3A0 0x3A4 0x3A8 0x3AC 0x3B0 0x3B4 0x3B8 0x3BC ) group.long ($2+0x800)++0x3 line.long 0x0 "REGG2_DOM_$1,Assign domain for SCR registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xF0 0xF1 0xF2 0xF3 0xF4 0xF5 0xF6 0xF7 0xF8 0xF9 0xFA 0xFB 0xFC 0xFD 0xFE 0xFF )(list 0x3C0 0x3C4 0x3C8 0x3CC 0x3D0 0x3D4 0x3D8 0x3DC 0x3E0 0x3E4 0x3E8 0x3EC 0x3F0 0x3F4 0x3F8 0x3FC ) group.long ($2+0x800)++0x3 line.long 0x0 "REGG2_DOM_$1,Assign domain for SCR registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x4 0x8 0xC 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C ) group.long ($2+0xC00)++0x3 line.long 0x0 "REGG3_DOM_$1,Assign domain for SCR registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1A 0x1B 0x1C 0x1D 0x1E 0x1F )(list 0x40 0x44 0x48 0x4C 0x50 0x54 0x58 0x5C 0x60 0x64 0x68 0x6C 0x70 0x74 0x78 0x7C ) group.long ($2+0xC00)++0x3 line.long 0x0 "REGG3_DOM_$1,Assign domain for SCR registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x20 0x21 0x22 0x23 0x24 0x25 0x26 0x27 0x28 0x29 0x2A 0x2B 0x2C 0x2D 0x2E 0x2F )(list 0x80 0x84 0x88 0x8C 0x90 0x94 0x98 0x9C 0xA0 0xA4 0xA8 0xAC 0xB0 0xB4 0xB8 0xBC ) group.long ($2+0xC00)++0x3 line.long 0x0 "REGG3_DOM_$1,Assign domain for SCR registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x30 0x31 0x32 0x33 0x34 0x35 0x36 0x37 0x38 0x39 0x3A 0x3B 0x3C 0x3D 0x3E 0x3F )(list 0xC0 0xC4 0xC8 0xCC 0xD0 0xD4 0xD8 0xDC 0xE0 0xE4 0xE8 0xEC 0xF0 0xF4 0xF8 0xFC ) group.long ($2+0xC00)++0x3 line.long 0x0 "REGG3_DOM_$1,Assign domain for SCR registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x40 0x41 0x42 0x43 0x44 0x45 0x46 0x47 0x48 0x49 0x4A 0x4B 0x4C 0x4D 0x4E 0x4F )(list 0x100 0x104 0x108 0x10C 0x110 0x114 0x118 0x11C 0x120 0x124 0x128 0x12C 0x130 0x134 0x138 0x13C ) group.long ($2+0xC00)++0x3 line.long 0x0 "REGG3_DOM_$1,Assign domain for SCR registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x50 0x51 0x52 0x53 0x54 0x55 0x56 0x57 0x58 0x59 0x5A 0x5B 0x5C 0x5D 0x5E 0x5F )(list 0x140 0x144 0x148 0x14C 0x150 0x154 0x158 0x15C 0x160 0x164 0x168 0x16C 0x170 0x174 0x178 0x17C ) group.long ($2+0xC00)++0x3 line.long 0x0 "REGG3_DOM_$1,Assign domain for SCR registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x60 0x61 0x62 0x63 0x64 0x65 0x66 0x67 0x68 0x69 0x6A 0x6B 0x6C 0x6D 0x6E 0x6F )(list 0x180 0x184 0x188 0x18C 0x190 0x194 0x198 0x19C 0x1A0 0x1A4 0x1A8 0x1AC 0x1B0 0x1B4 0x1B8 0x1BC ) group.long ($2+0xC00)++0x3 line.long 0x0 "REGG3_DOM_$1,Assign domain for SCR registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x70 0x71 0x72 0x73 0x74 0x75 0x76 0x77 0x78 0x79 0x7A 0x7B 0x7C 0x7D 0x7E 0x7F )(list 0x1C0 0x1C4 0x1C8 0x1CC 0x1D0 0x1D4 0x1D8 0x1DC 0x1E0 0x1E4 0x1E8 0x1EC 0x1F0 0x1F4 0x1F8 0x1FC ) group.long ($2+0xC00)++0x3 line.long 0x0 "REGG3_DOM_$1,Assign domain for SCR registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x80 0x81 0x82 0x83 0x84 0x85 0x86 0x87 0x88 0x89 0x8A 0x8B 0x8C 0x8D 0x8E 0x8F )(list 0x200 0x204 0x208 0x20C 0x210 0x214 0x218 0x21C 0x220 0x224 0x228 0x22C 0x230 0x234 0x238 0x23C ) group.long ($2+0xC00)++0x3 line.long 0x0 "REGG3_DOM_$1,Assign domain for SCR registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x90 0x91 0x92 0x93 0x94 0x95 0x96 0x97 0x98 0x99 0x9A 0x9B 0x9C 0x9D 0x9E 0x9F )(list 0x240 0x244 0x248 0x24C 0x250 0x254 0x258 0x25C 0x260 0x264 0x268 0x26C 0x270 0x274 0x278 0x27C ) group.long ($2+0xC00)++0x3 line.long 0x0 "REGG3_DOM_$1,Assign domain for SCR registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xA0 0xA1 0xA2 0xA3 0xA4 0xA5 0xA6 0xA7 0xA8 0xA9 0xAA 0xAB 0xAC 0xAD 0xAE 0xAF )(list 0x280 0x284 0x288 0x28C 0x290 0x294 0x298 0x29C 0x2A0 0x2A4 0x2A8 0x2AC 0x2B0 0x2B4 0x2B8 0x2BC ) group.long ($2+0xC00)++0x3 line.long 0x0 "REGG3_DOM_$1,Assign domain for SCR registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xB0 0xB1 0xB2 0xB3 0xB4 0xB5 0xB6 0xB7 0xB8 0xB9 0xBA 0xBB 0xBC 0xBD 0xBE 0xBF )(list 0x2C0 0x2C4 0x2C8 0x2CC 0x2D0 0x2D4 0x2D8 0x2DC 0x2E0 0x2E4 0x2E8 0x2EC 0x2F0 0x2F4 0x2F8 0x2FC ) group.long ($2+0xC00)++0x3 line.long 0x0 "REGG3_DOM_$1,Assign domain for SCR registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xC0 0xC1 0xC2 0xC3 0xC4 0xC5 0xC6 0xC7 0xC8 0xC9 0xCA 0xCB 0xCC 0xCD 0xCE 0xCF )(list 0x300 0x304 0x308 0x30C 0x310 0x314 0x318 0x31C 0x320 0x324 0x328 0x32C 0x330 0x334 0x338 0x33C ) group.long ($2+0xC00)++0x3 line.long 0x0 "REGG3_DOM_$1,Assign domain for SCR registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xD0 0xD1 0xD2 0xD3 0xD4 0xD5 0xD6 0xD7 0xD8 0xD9 0xDA 0xDB 0xDC 0xDD 0xDE 0xDF )(list 0x340 0x344 0x348 0x34C 0x350 0x354 0x358 0x35C 0x360 0x364 0x368 0x36C 0x370 0x374 0x378 0x37C ) group.long ($2+0xC00)++0x3 line.long 0x0 "REGG3_DOM_$1,Assign domain for SCR registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xE0 0xE1 0xE2 0xE3 0xE4 0xE5 0xE6 0xE7 0xE8 0xE9 0xEA 0xEB 0xEC 0xED 0xEE 0xEF )(list 0x380 0x384 0x388 0x38C 0x390 0x394 0x398 0x39C 0x3A0 0x3A4 0x3A8 0x3AC 0x3B0 0x3B4 0x3B8 0x3BC ) group.long ($2+0xC00)++0x3 line.long 0x0 "REGG3_DOM_$1,Assign domain for SCR registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xF0 0xF1 0xF2 0xF3 0xF4 0xF5 0xF6 0xF7 0xF8 0xF9 0xFA 0xFB 0xFC 0xFD 0xFE 0xFF )(list 0x3C0 0x3C4 0x3C8 0x3CC 0x3D0 0x3D4 0x3D8 0x3DC 0x3E0 0x3E4 0x3E8 0x3EC 0x3F0 0x3F4 0x3F8 0x3FC ) group.long ($2+0xC00)++0x3 line.long 0x0 "REGG3_DOM_$1,Assign domain for SCR registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x4 0x8 0xC 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C ) group.long ($2+0x1000)++0x3 line.long 0x0 "REGG4_DOM_$1,Assign domain for RSTGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1A 0x1B 0x1C 0x1D 0x1E 0x1F )(list 0x40 0x44 0x48 0x4C 0x50 0x54 0x58 0x5C 0x60 0x64 0x68 0x6C 0x70 0x74 0x78 0x7C ) group.long ($2+0x1000)++0x3 line.long 0x0 "REGG4_DOM_$1,Assign domain for RSTGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x20 0x21 0x22 0x23 0x24 0x25 0x26 0x27 0x28 0x29 0x2A 0x2B 0x2C 0x2D 0x2E 0x2F )(list 0x80 0x84 0x88 0x8C 0x90 0x94 0x98 0x9C 0xA0 0xA4 0xA8 0xAC 0xB0 0xB4 0xB8 0xBC ) group.long ($2+0x1000)++0x3 line.long 0x0 "REGG4_DOM_$1,Assign domain for RSTGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x30 0x31 0x32 0x33 0x34 0x35 0x36 0x37 0x38 0x39 0x3A 0x3B 0x3C 0x3D 0x3E 0x3F )(list 0xC0 0xC4 0xC8 0xCC 0xD0 0xD4 0xD8 0xDC 0xE0 0xE4 0xE8 0xEC 0xF0 0xF4 0xF8 0xFC ) group.long ($2+0x1000)++0x3 line.long 0x0 "REGG4_DOM_$1,Assign domain for RSTGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x40 0x41 0x42 0x43 0x44 0x45 0x46 0x47 0x48 0x49 0x4A 0x4B 0x4C 0x4D 0x4E 0x4F )(list 0x100 0x104 0x108 0x10C 0x110 0x114 0x118 0x11C 0x120 0x124 0x128 0x12C 0x130 0x134 0x138 0x13C ) group.long ($2+0x1000)++0x3 line.long 0x0 "REGG4_DOM_$1,Assign domain for RSTGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x50 0x51 0x52 0x53 0x54 0x55 0x56 0x57 0x58 0x59 0x5A 0x5B 0x5C 0x5D 0x5E 0x5F )(list 0x140 0x144 0x148 0x14C 0x150 0x154 0x158 0x15C 0x160 0x164 0x168 0x16C 0x170 0x174 0x178 0x17C ) group.long ($2+0x1000)++0x3 line.long 0x0 "REGG4_DOM_$1,Assign domain for RSTGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x60 0x61 0x62 0x63 0x64 0x65 0x66 0x67 0x68 0x69 0x6A 0x6B 0x6C 0x6D 0x6E 0x6F )(list 0x180 0x184 0x188 0x18C 0x190 0x194 0x198 0x19C 0x1A0 0x1A4 0x1A8 0x1AC 0x1B0 0x1B4 0x1B8 0x1BC ) group.long ($2+0x1000)++0x3 line.long 0x0 "REGG4_DOM_$1,Assign domain for RSTGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x70 0x71 0x72 0x73 0x74 0x75 0x76 0x77 0x78 0x79 0x7A 0x7B 0x7C 0x7D 0x7E 0x7F )(list 0x1C0 0x1C4 0x1C8 0x1CC 0x1D0 0x1D4 0x1D8 0x1DC 0x1E0 0x1E4 0x1E8 0x1EC 0x1F0 0x1F4 0x1F8 0x1FC ) group.long ($2+0x1000)++0x3 line.long 0x0 "REGG4_DOM_$1,Assign domain for RSTGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x80 0x81 0x82 0x83 0x84 0x85 0x86 0x87 0x88 0x89 0x8A 0x8B 0x8C 0x8D 0x8E 0x8F )(list 0x200 0x204 0x208 0x20C 0x210 0x214 0x218 0x21C 0x220 0x224 0x228 0x22C 0x230 0x234 0x238 0x23C ) group.long ($2+0x1000)++0x3 line.long 0x0 "REGG4_DOM_$1,Assign domain for RSTGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x90 0x91 0x92 0x93 0x94 0x95 0x96 0x97 0x98 0x99 0x9A 0x9B 0x9C 0x9D 0x9E 0x9F )(list 0x240 0x244 0x248 0x24C 0x250 0x254 0x258 0x25C 0x260 0x264 0x268 0x26C 0x270 0x274 0x278 0x27C ) group.long ($2+0x1000)++0x3 line.long 0x0 "REGG4_DOM_$1,Assign domain for RSTGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xA0 0xA1 0xA2 0xA3 0xA4 0xA5 0xA6 0xA7 0xA8 0xA9 0xAA 0xAB 0xAC 0xAD 0xAE 0xAF )(list 0x280 0x284 0x288 0x28C 0x290 0x294 0x298 0x29C 0x2A0 0x2A4 0x2A8 0x2AC 0x2B0 0x2B4 0x2B8 0x2BC ) group.long ($2+0x1000)++0x3 line.long 0x0 "REGG4_DOM_$1,Assign domain for RSTGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xB0 0xB1 0xB2 0xB3 0xB4 0xB5 0xB6 0xB7 0xB8 0xB9 0xBA 0xBB 0xBC 0xBD 0xBE 0xBF )(list 0x2C0 0x2C4 0x2C8 0x2CC 0x2D0 0x2D4 0x2D8 0x2DC 0x2E0 0x2E4 0x2E8 0x2EC 0x2F0 0x2F4 0x2F8 0x2FC ) group.long ($2+0x1000)++0x3 line.long 0x0 "REGG4_DOM_$1,Assign domain for RSTGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xC0 0xC1 0xC2 0xC3 0xC4 0xC5 0xC6 0xC7 0xC8 0xC9 0xCA 0xCB 0xCC 0xCD 0xCE 0xCF )(list 0x300 0x304 0x308 0x30C 0x310 0x314 0x318 0x31C 0x320 0x324 0x328 0x32C 0x330 0x334 0x338 0x33C ) group.long ($2+0x1000)++0x3 line.long 0x0 "REGG4_DOM_$1,Assign domain for RSTGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xD0 0xD1 0xD2 0xD3 0xD4 0xD5 0xD6 0xD7 0xD8 0xD9 0xDA 0xDB 0xDC 0xDD 0xDE 0xDF )(list 0x340 0x344 0x348 0x34C 0x350 0x354 0x358 0x35C 0x360 0x364 0x368 0x36C 0x370 0x374 0x378 0x37C ) group.long ($2+0x1000)++0x3 line.long 0x0 "REGG4_DOM_$1,Assign domain for RSTGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xE0 0xE1 0xE2 0xE3 0xE4 0xE5 0xE6 0xE7 0xE8 0xE9 0xEA 0xEB 0xEC 0xED 0xEE 0xEF )(list 0x380 0x384 0x388 0x38C 0x390 0x394 0x398 0x39C 0x3A0 0x3A4 0x3A8 0x3AC 0x3B0 0x3B4 0x3B8 0x3BC ) group.long ($2+0x1000)++0x3 line.long 0x0 "REGG4_DOM_$1,Assign domain for RSTGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xF0 0xF1 0xF2 0xF3 0xF4 0xF5 0xF6 0xF7 0xF8 0xF9 0xFA 0xFB 0xFC 0xFD 0xFE 0xFF )(list 0x3C0 0x3C4 0x3C8 0x3CC 0x3D0 0x3D4 0x3D8 0x3DC 0x3E0 0x3E4 0x3E8 0x3EC 0x3F0 0x3F4 0x3F8 0x3FC ) group.long ($2+0x1000)++0x3 line.long 0x0 "REGG4_DOM_$1,Assign domain for RSTGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x4 0x8 0xC 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C ) group.long ($2+0x1400)++0x3 line.long 0x0 "REGG5_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1A 0x1B 0x1C 0x1D 0x1E 0x1F )(list 0x40 0x44 0x48 0x4C 0x50 0x54 0x58 0x5C 0x60 0x64 0x68 0x6C 0x70 0x74 0x78 0x7C ) group.long ($2+0x1400)++0x3 line.long 0x0 "REGG5_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x20 0x21 0x22 0x23 0x24 0x25 0x26 0x27 0x28 0x29 0x2A 0x2B 0x2C 0x2D 0x2E 0x2F )(list 0x80 0x84 0x88 0x8C 0x90 0x94 0x98 0x9C 0xA0 0xA4 0xA8 0xAC 0xB0 0xB4 0xB8 0xBC ) group.long ($2+0x1400)++0x3 line.long 0x0 "REGG5_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x30 0x31 0x32 0x33 0x34 0x35 0x36 0x37 0x38 0x39 0x3A 0x3B 0x3C 0x3D 0x3E 0x3F )(list 0xC0 0xC4 0xC8 0xCC 0xD0 0xD4 0xD8 0xDC 0xE0 0xE4 0xE8 0xEC 0xF0 0xF4 0xF8 0xFC ) group.long ($2+0x1400)++0x3 line.long 0x0 "REGG5_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x40 0x41 0x42 0x43 0x44 0x45 0x46 0x47 0x48 0x49 0x4A 0x4B 0x4C 0x4D 0x4E 0x4F )(list 0x100 0x104 0x108 0x10C 0x110 0x114 0x118 0x11C 0x120 0x124 0x128 0x12C 0x130 0x134 0x138 0x13C ) group.long ($2+0x1400)++0x3 line.long 0x0 "REGG5_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x50 0x51 0x52 0x53 0x54 0x55 0x56 0x57 0x58 0x59 0x5A 0x5B 0x5C 0x5D 0x5E 0x5F )(list 0x140 0x144 0x148 0x14C 0x150 0x154 0x158 0x15C 0x160 0x164 0x168 0x16C 0x170 0x174 0x178 0x17C ) group.long ($2+0x1400)++0x3 line.long 0x0 "REGG5_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x60 0x61 0x62 0x63 0x64 0x65 0x66 0x67 0x68 0x69 0x6A 0x6B 0x6C 0x6D 0x6E 0x6F )(list 0x180 0x184 0x188 0x18C 0x190 0x194 0x198 0x19C 0x1A0 0x1A4 0x1A8 0x1AC 0x1B0 0x1B4 0x1B8 0x1BC ) group.long ($2+0x1400)++0x3 line.long 0x0 "REGG5_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x70 0x71 0x72 0x73 0x74 0x75 0x76 0x77 0x78 0x79 0x7A 0x7B 0x7C 0x7D 0x7E 0x7F )(list 0x1C0 0x1C4 0x1C8 0x1CC 0x1D0 0x1D4 0x1D8 0x1DC 0x1E0 0x1E4 0x1E8 0x1EC 0x1F0 0x1F4 0x1F8 0x1FC ) group.long ($2+0x1400)++0x3 line.long 0x0 "REGG5_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x80 0x81 0x82 0x83 0x84 0x85 0x86 0x87 0x88 0x89 0x8A 0x8B 0x8C 0x8D 0x8E 0x8F )(list 0x200 0x204 0x208 0x20C 0x210 0x214 0x218 0x21C 0x220 0x224 0x228 0x22C 0x230 0x234 0x238 0x23C ) group.long ($2+0x1400)++0x3 line.long 0x0 "REGG5_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x90 0x91 0x92 0x93 0x94 0x95 0x96 0x97 0x98 0x99 0x9A 0x9B 0x9C 0x9D 0x9E 0x9F )(list 0x240 0x244 0x248 0x24C 0x250 0x254 0x258 0x25C 0x260 0x264 0x268 0x26C 0x270 0x274 0x278 0x27C ) group.long ($2+0x1400)++0x3 line.long 0x0 "REGG5_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xA0 0xA1 0xA2 0xA3 0xA4 0xA5 0xA6 0xA7 0xA8 0xA9 0xAA 0xAB 0xAC 0xAD 0xAE 0xAF )(list 0x280 0x284 0x288 0x28C 0x290 0x294 0x298 0x29C 0x2A0 0x2A4 0x2A8 0x2AC 0x2B0 0x2B4 0x2B8 0x2BC ) group.long ($2+0x1400)++0x3 line.long 0x0 "REGG5_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xB0 0xB1 0xB2 0xB3 0xB4 0xB5 0xB6 0xB7 0xB8 0xB9 0xBA 0xBB 0xBC 0xBD 0xBE 0xBF )(list 0x2C0 0x2C4 0x2C8 0x2CC 0x2D0 0x2D4 0x2D8 0x2DC 0x2E0 0x2E4 0x2E8 0x2EC 0x2F0 0x2F4 0x2F8 0x2FC ) group.long ($2+0x1400)++0x3 line.long 0x0 "REGG5_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xC0 0xC1 0xC2 0xC3 0xC4 0xC5 0xC6 0xC7 0xC8 0xC9 0xCA 0xCB 0xCC 0xCD 0xCE 0xCF )(list 0x300 0x304 0x308 0x30C 0x310 0x314 0x318 0x31C 0x320 0x324 0x328 0x32C 0x330 0x334 0x338 0x33C ) group.long ($2+0x1400)++0x3 line.long 0x0 "REGG5_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xD0 0xD1 0xD2 0xD3 0xD4 0xD5 0xD6 0xD7 0xD8 0xD9 0xDA 0xDB 0xDC 0xDD 0xDE 0xDF )(list 0x340 0x344 0x348 0x34C 0x350 0x354 0x358 0x35C 0x360 0x364 0x368 0x36C 0x370 0x374 0x378 0x37C ) group.long ($2+0x1400)++0x3 line.long 0x0 "REGG5_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xE0 0xE1 0xE2 0xE3 0xE4 0xE5 0xE6 0xE7 0xE8 0xE9 0xEA 0xEB 0xEC 0xED 0xEE 0xEF )(list 0x380 0x384 0x388 0x38C 0x390 0x394 0x398 0x39C 0x3A0 0x3A4 0x3A8 0x3AC 0x3B0 0x3B4 0x3B8 0x3BC ) group.long ($2+0x1400)++0x3 line.long 0x0 "REGG5_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xF0 0xF1 0xF2 0xF3 0xF4 0xF5 0xF6 0xF7 0xF8 0xF9 0xFA 0xFB 0xFC 0xFD 0xFE 0xFF )(list 0x3C0 0x3C4 0x3C8 0x3CC 0x3D0 0x3D4 0x3D8 0x3DC 0x3E0 0x3E4 0x3E8 0x3EC 0x3F0 0x3F4 0x3F8 0x3FC ) group.long ($2+0x1400)++0x3 line.long 0x0 "REGG5_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x4 0x8 0xC 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C ) group.long ($2+0x1800)++0x3 line.long 0x0 "REGG6_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1A 0x1B 0x1C 0x1D 0x1E 0x1F )(list 0x40 0x44 0x48 0x4C 0x50 0x54 0x58 0x5C 0x60 0x64 0x68 0x6C 0x70 0x74 0x78 0x7C ) group.long ($2+0x1800)++0x3 line.long 0x0 "REGG6_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x20 0x21 0x22 0x23 0x24 0x25 0x26 0x27 0x28 0x29 0x2A 0x2B 0x2C 0x2D 0x2E 0x2F )(list 0x80 0x84 0x88 0x8C 0x90 0x94 0x98 0x9C 0xA0 0xA4 0xA8 0xAC 0xB0 0xB4 0xB8 0xBC ) group.long ($2+0x1800)++0x3 line.long 0x0 "REGG6_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x30 0x31 0x32 0x33 0x34 0x35 0x36 0x37 0x38 0x39 0x3A 0x3B 0x3C 0x3D 0x3E 0x3F )(list 0xC0 0xC4 0xC8 0xCC 0xD0 0xD4 0xD8 0xDC 0xE0 0xE4 0xE8 0xEC 0xF0 0xF4 0xF8 0xFC ) group.long ($2+0x1800)++0x3 line.long 0x0 "REGG6_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x40 0x41 0x42 0x43 0x44 0x45 0x46 0x47 0x48 0x49 0x4A 0x4B 0x4C 0x4D 0x4E 0x4F )(list 0x100 0x104 0x108 0x10C 0x110 0x114 0x118 0x11C 0x120 0x124 0x128 0x12C 0x130 0x134 0x138 0x13C ) group.long ($2+0x1800)++0x3 line.long 0x0 "REGG6_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x50 0x51 0x52 0x53 0x54 0x55 0x56 0x57 0x58 0x59 0x5A 0x5B 0x5C 0x5D 0x5E 0x5F )(list 0x140 0x144 0x148 0x14C 0x150 0x154 0x158 0x15C 0x160 0x164 0x168 0x16C 0x170 0x174 0x178 0x17C ) group.long ($2+0x1800)++0x3 line.long 0x0 "REGG6_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x60 0x61 0x62 0x63 0x64 0x65 0x66 0x67 0x68 0x69 0x6A 0x6B 0x6C 0x6D 0x6E 0x6F )(list 0x180 0x184 0x188 0x18C 0x190 0x194 0x198 0x19C 0x1A0 0x1A4 0x1A8 0x1AC 0x1B0 0x1B4 0x1B8 0x1BC ) group.long ($2+0x1800)++0x3 line.long 0x0 "REGG6_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x70 0x71 0x72 0x73 0x74 0x75 0x76 0x77 0x78 0x79 0x7A 0x7B 0x7C 0x7D 0x7E 0x7F )(list 0x1C0 0x1C4 0x1C8 0x1CC 0x1D0 0x1D4 0x1D8 0x1DC 0x1E0 0x1E4 0x1E8 0x1EC 0x1F0 0x1F4 0x1F8 0x1FC ) group.long ($2+0x1800)++0x3 line.long 0x0 "REGG6_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x80 0x81 0x82 0x83 0x84 0x85 0x86 0x87 0x88 0x89 0x8A 0x8B 0x8C 0x8D 0x8E 0x8F )(list 0x200 0x204 0x208 0x20C 0x210 0x214 0x218 0x21C 0x220 0x224 0x228 0x22C 0x230 0x234 0x238 0x23C ) group.long ($2+0x1800)++0x3 line.long 0x0 "REGG6_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x90 0x91 0x92 0x93 0x94 0x95 0x96 0x97 0x98 0x99 0x9A 0x9B 0x9C 0x9D 0x9E 0x9F )(list 0x240 0x244 0x248 0x24C 0x250 0x254 0x258 0x25C 0x260 0x264 0x268 0x26C 0x270 0x274 0x278 0x27C ) group.long ($2+0x1800)++0x3 line.long 0x0 "REGG6_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xA0 0xA1 0xA2 0xA3 0xA4 0xA5 0xA6 0xA7 0xA8 0xA9 0xAA 0xAB 0xAC 0xAD 0xAE 0xAF )(list 0x280 0x284 0x288 0x28C 0x290 0x294 0x298 0x29C 0x2A0 0x2A4 0x2A8 0x2AC 0x2B0 0x2B4 0x2B8 0x2BC ) group.long ($2+0x1800)++0x3 line.long 0x0 "REGG6_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xB0 0xB1 0xB2 0xB3 0xB4 0xB5 0xB6 0xB7 0xB8 0xB9 0xBA 0xBB 0xBC 0xBD 0xBE 0xBF )(list 0x2C0 0x2C4 0x2C8 0x2CC 0x2D0 0x2D4 0x2D8 0x2DC 0x2E0 0x2E4 0x2E8 0x2EC 0x2F0 0x2F4 0x2F8 0x2FC ) group.long ($2+0x1800)++0x3 line.long 0x0 "REGG6_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xC0 0xC1 0xC2 0xC3 0xC4 0xC5 0xC6 0xC7 0xC8 0xC9 0xCA 0xCB 0xCC 0xCD 0xCE 0xCF )(list 0x300 0x304 0x308 0x30C 0x310 0x314 0x318 0x31C 0x320 0x324 0x328 0x32C 0x330 0x334 0x338 0x33C ) group.long ($2+0x1800)++0x3 line.long 0x0 "REGG6_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xD0 0xD1 0xD2 0xD3 0xD4 0xD5 0xD6 0xD7 0xD8 0xD9 0xDA 0xDB 0xDC 0xDD 0xDE 0xDF )(list 0x340 0x344 0x348 0x34C 0x350 0x354 0x358 0x35C 0x360 0x364 0x368 0x36C 0x370 0x374 0x378 0x37C ) group.long ($2+0x1800)++0x3 line.long 0x0 "REGG6_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xE0 0xE1 0xE2 0xE3 0xE4 0xE5 0xE6 0xE7 0xE8 0xE9 0xEA 0xEB 0xEC 0xED 0xEE 0xEF )(list 0x380 0x384 0x388 0x38C 0x390 0x394 0x398 0x39C 0x3A0 0x3A4 0x3A8 0x3AC 0x3B0 0x3B4 0x3B8 0x3BC ) group.long ($2+0x1800)++0x3 line.long 0x0 "REGG6_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xF0 0xF1 0xF2 0xF3 0xF4 0xF5 0xF6 0xF7 0xF8 0xF9 0xFA 0xFB 0xFC 0xFD 0xFE 0xFF )(list 0x3C0 0x3C4 0x3C8 0x3CC 0x3D0 0x3D4 0x3D8 0x3DC 0x3E0 0x3E4 0x3E8 0x3EC 0x3F0 0x3F4 0x3F8 0x3FC ) group.long ($2+0x1800)++0x3 line.long 0x0 "REGG6_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x4 0x8 0xC 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C ) group.long ($2+0x1C00)++0x3 line.long 0x0 "REGG7_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1A 0x1B 0x1C 0x1D 0x1E 0x1F )(list 0x40 0x44 0x48 0x4C 0x50 0x54 0x58 0x5C 0x60 0x64 0x68 0x6C 0x70 0x74 0x78 0x7C ) group.long ($2+0x1C00)++0x3 line.long 0x0 "REGG7_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x20 0x21 0x22 0x23 0x24 0x25 0x26 0x27 0x28 0x29 0x2A 0x2B 0x2C 0x2D 0x2E 0x2F )(list 0x80 0x84 0x88 0x8C 0x90 0x94 0x98 0x9C 0xA0 0xA4 0xA8 0xAC 0xB0 0xB4 0xB8 0xBC ) group.long ($2+0x1C00)++0x3 line.long 0x0 "REGG7_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x30 0x31 0x32 0x33 0x34 0x35 0x36 0x37 0x38 0x39 0x3A 0x3B 0x3C 0x3D 0x3E 0x3F )(list 0xC0 0xC4 0xC8 0xCC 0xD0 0xD4 0xD8 0xDC 0xE0 0xE4 0xE8 0xEC 0xF0 0xF4 0xF8 0xFC ) group.long ($2+0x1C00)++0x3 line.long 0x0 "REGG7_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x40 0x41 0x42 0x43 0x44 0x45 0x46 0x47 0x48 0x49 0x4A 0x4B 0x4C 0x4D 0x4E 0x4F )(list 0x100 0x104 0x108 0x10C 0x110 0x114 0x118 0x11C 0x120 0x124 0x128 0x12C 0x130 0x134 0x138 0x13C ) group.long ($2+0x1C00)++0x3 line.long 0x0 "REGG7_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x50 0x51 0x52 0x53 0x54 0x55 0x56 0x57 0x58 0x59 0x5A 0x5B 0x5C 0x5D 0x5E 0x5F )(list 0x140 0x144 0x148 0x14C 0x150 0x154 0x158 0x15C 0x160 0x164 0x168 0x16C 0x170 0x174 0x178 0x17C ) group.long ($2+0x1C00)++0x3 line.long 0x0 "REGG7_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x60 0x61 0x62 0x63 0x64 0x65 0x66 0x67 0x68 0x69 0x6A 0x6B 0x6C 0x6D 0x6E 0x6F )(list 0x180 0x184 0x188 0x18C 0x190 0x194 0x198 0x19C 0x1A0 0x1A4 0x1A8 0x1AC 0x1B0 0x1B4 0x1B8 0x1BC ) group.long ($2+0x1C00)++0x3 line.long 0x0 "REGG7_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x70 0x71 0x72 0x73 0x74 0x75 0x76 0x77 0x78 0x79 0x7A 0x7B 0x7C 0x7D 0x7E 0x7F )(list 0x1C0 0x1C4 0x1C8 0x1CC 0x1D0 0x1D4 0x1D8 0x1DC 0x1E0 0x1E4 0x1E8 0x1EC 0x1F0 0x1F4 0x1F8 0x1FC ) group.long ($2+0x1C00)++0x3 line.long 0x0 "REGG7_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x80 0x81 0x82 0x83 0x84 0x85 0x86 0x87 0x88 0x89 0x8A 0x8B 0x8C 0x8D 0x8E 0x8F )(list 0x200 0x204 0x208 0x20C 0x210 0x214 0x218 0x21C 0x220 0x224 0x228 0x22C 0x230 0x234 0x238 0x23C ) group.long ($2+0x1C00)++0x3 line.long 0x0 "REGG7_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x90 0x91 0x92 0x93 0x94 0x95 0x96 0x97 0x98 0x99 0x9A 0x9B 0x9C 0x9D 0x9E 0x9F )(list 0x240 0x244 0x248 0x24C 0x250 0x254 0x258 0x25C 0x260 0x264 0x268 0x26C 0x270 0x274 0x278 0x27C ) group.long ($2+0x1C00)++0x3 line.long 0x0 "REGG7_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xA0 0xA1 0xA2 0xA3 0xA4 0xA5 0xA6 0xA7 0xA8 0xA9 0xAA 0xAB 0xAC 0xAD 0xAE 0xAF )(list 0x280 0x284 0x288 0x28C 0x290 0x294 0x298 0x29C 0x2A0 0x2A4 0x2A8 0x2AC 0x2B0 0x2B4 0x2B8 0x2BC ) group.long ($2+0x1C00)++0x3 line.long 0x0 "REGG7_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xB0 0xB1 0xB2 0xB3 0xB4 0xB5 0xB6 0xB7 0xB8 0xB9 0xBA 0xBB 0xBC 0xBD 0xBE 0xBF )(list 0x2C0 0x2C4 0x2C8 0x2CC 0x2D0 0x2D4 0x2D8 0x2DC 0x2E0 0x2E4 0x2E8 0x2EC 0x2F0 0x2F4 0x2F8 0x2FC ) group.long ($2+0x1C00)++0x3 line.long 0x0 "REGG7_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xC0 0xC1 0xC2 0xC3 0xC4 0xC5 0xC6 0xC7 0xC8 0xC9 0xCA 0xCB 0xCC 0xCD 0xCE 0xCF )(list 0x300 0x304 0x308 0x30C 0x310 0x314 0x318 0x31C 0x320 0x324 0x328 0x32C 0x330 0x334 0x338 0x33C ) group.long ($2+0x1C00)++0x3 line.long 0x0 "REGG7_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xD0 0xD1 0xD2 0xD3 0xD4 0xD5 0xD6 0xD7 0xD8 0xD9 0xDA 0xDB 0xDC 0xDD 0xDE 0xDF )(list 0x340 0x344 0x348 0x34C 0x350 0x354 0x358 0x35C 0x360 0x364 0x368 0x36C 0x370 0x374 0x378 0x37C ) group.long ($2+0x1C00)++0x3 line.long 0x0 "REGG7_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xE0 0xE1 0xE2 0xE3 0xE4 0xE5 0xE6 0xE7 0xE8 0xE9 0xEA 0xEB 0xEC 0xED 0xEE 0xEF )(list 0x380 0x384 0x388 0x38C 0x390 0x394 0x398 0x39C 0x3A0 0x3A4 0x3A8 0x3AC 0x3B0 0x3B4 0x3B8 0x3BC ) group.long ($2+0x1C00)++0x3 line.long 0x0 "REGG7_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xF0 0xF1 0xF2 0xF3 0xF4 0xF5 0xF6 0xF7 0xF8 0xF9 0xFA 0xFB 0xFC 0xFD 0xFE 0xFF )(list 0x3C0 0x3C4 0x3C8 0x3CC 0x3D0 0x3D4 0x3D8 0x3DC 0x3E0 0x3E4 0x3E8 0x3EC 0x3F0 0x3F4 0x3F8 0x3FC ) group.long ($2+0x1C00)++0x3 line.long 0x0 "REGG7_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end group.long 0x2000++0x17 line.long 0x0 "GLB_CTL,This register provides global enable settings for permission control." bitfld.long 0x0 5. "DOM_CFG_LOCK,Lock write for DOM_CFG_MODE bit." "0,1" bitfld.long 0x0 4. "DOM_CFG_MODE,When enabled all the source setting can be configured by master from domain 0 if it is not locked. When disabled only resource manager can configure the permission of the resource." "0,1" bitfld.long 0x0 3. "PERCK_DIS_LOCK,Lock write for PERCK_DIS" "0,1" bitfld.long 0x0 2. "PERCK_DIS,All the permission check disable." "0,1" newline bitfld.long 0x0 1. "DOM_PRO_LOCK,Lock write for DOM_PRO_EN bit." "0,1" bitfld.long 0x0 0. "DOM_PRO_EN,When disabled no domain access permission check" "0,1" line.long 0x4 "RES_MGR,Resource manager register. This regster is used to assign resource manager for global resource access control" bitfld.long 0x4 17. "MID_LOCK,Lock write for MID_EN and MID_LOW and MID_HIG registers." "0,1" bitfld.long 0x4 16. "MID_EN,Master ID check enable" "0,1" bitfld.long 0x4 15. "PRI_PER_LOCK,Lock write for PRI_PER and PRI_PER_EN" "0,1" bitfld.long 0x4 13.--14. "PRI_PER,Resource manager privileged access permission. bit0 for privileged access bit1 for user access" "0,1,2,3" newline bitfld.long 0x4 12. "PRI_PER_EN,Resource manager privileged access permission enable." "0,1" bitfld.long 0x4 11. "SEC_PER_LOCK,Lock for SEC_PER and SEC_PER_LOCK" "0,1" bitfld.long 0x4 9.--10. "SEC_PER,Resource manager secure access permission. bit 0 for secure access bit 1 for non-secure access" "0,1,2,3" bitfld.long 0x4 8. "SEC_PER_EN,Resource manager secure permission enable" "0,1" bitfld.long 0x4 7. "DID_LOCK,Lock write for DID_EN and DID" "0,1" newline hexmask.long.byte 0x4 3.--6. 1. "DID,Resource manager domain ID" bitfld.long 0x4 2. "DID_EN,Resource manager Domain ID enable" "0,1" bitfld.long 0x4 1. "RES_MGR_EN_LOCK,Lock for RES_MGR_EN" "0,1" bitfld.long 0x4 0. "RES_MGR_EN,Resource manager enable. When the bit is disable there is no resource manager." "0,1" line.long 0x8 "RES_MGR_MA0,This register is used to assign master 0~31 as resource manager." hexmask.long 0x8 0.--31. 1. "MID,Assign master 0~31 for resource manager" line.long 0xC "RES_MGR_MA1,This register is used to assign master 32~63 as resource manager." hexmask.long 0xC 0.--31. 1. "MID,Indicate if master 32~63 is resource manager." line.long 0x10 "RES_MGR_MA2,This register is used to assign master 64~95 as resource manager." hexmask.long 0x10 0.--31. 1. "MID,Indicate if master 64~95 is resource manager." line.long 0x14 "RES_MGR_MA3,This register is used to assign master 96~127 as resource manager." hexmask.long 0x14 0.--31. 1. "MID,Indicate if master 96~127 is resource manager." repeat 8. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 )(list 0x0 0x14 0x28 0x3C 0x50 0x64 0x78 0x8C ) group.long ($2+0x2100)++0x3 line.long 0x0 "GRP_MGR_$1,Group Manager Register. This register is used to assign group manager for each domain" bitfld.long 0x0 17. "MID_LOCK,Lock write for MID_EN and MID_LOW and MID_HIG registers." "0,1" bitfld.long 0x0 16. "MID_EN,Master ID check enable" "0,1" bitfld.long 0x0 15. "PRI_PER_LOCK,Lock write for PRI_PER and PRI_PER_EN" "0,1" bitfld.long 0x0 13.--14. "PRI_PER,Group manager privileged access permission. bit0 for privileged access bit1 for user access" "0,1,2,3" newline bitfld.long 0x0 12. "PRI_PER_EN,Group manager privileged access permission enable." "0,1" bitfld.long 0x0 11. "SEC_PER_LOCK,Lock for SEC_PER and SEC_PER_LOCK" "0,1" bitfld.long 0x0 9.--10. "SEC_PER,Group manager secure access permission. bit 0 for secure access bit 1 for non-secure access" "0,1,2,3" bitfld.long 0x0 8. "SEC_PER_EN,Group manager secure permission enable" "0,1" bitfld.long 0x0 7. "DID_LOCK,Lock write for DID_EN and DID" "0,1" newline hexmask.long.byte 0x0 3.--6. 1. "DID,Group manager domain ID" bitfld.long 0x0 2. "DID_EN,Group manager Domain ID enable" "0,1" bitfld.long 0x0 1. "GRP_MGR_EN_LOCK,Lock write for GPR_MGR_EN" "0,1" bitfld.long 0x0 0. "GRP_MGR_EN,Group manager enable. When the bit is disable there is no resource manager." "0,1" repeat.end repeat 8. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 )(list 0x0 0x14 0x28 0x3C 0x50 0x64 0x78 0x8C ) group.long ($2+0x2104)++0x3 line.long 0x0 "GRP_MGR_MA0_$1,Assign master 0~31 for group manager 0" hexmask.long 0x0 0.--31. 1. "MID,Assign master 0~31 for resource manager" repeat.end repeat 8. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 )(list 0x0 0x14 0x28 0x3C 0x50 0x64 0x78 0x8C ) group.long ($2+0x2108)++0x3 line.long 0x0 "GRP_MGR_MA1_$1,Assign master 32~63 for group manager 0" hexmask.long 0x0 0.--31. 1. "MID,Indicate if master 32~63 is resource manager." repeat.end repeat 8. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 )(list 0x0 0x14 0x28 0x3C 0x50 0x64 0x78 0x8C ) group.long ($2+0x210C)++0x3 line.long 0x0 "GRP_MGR_MA2_$1,Assign master 64~95 for group manager 0" hexmask.long 0x0 0.--31. 1. "MID,Indicate if master 64~95 is resource manager." repeat.end repeat 8. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 )(list 0x0 0x14 0x28 0x3C 0x50 0x64 0x78 0x8C ) group.long ($2+0x2110)++0x3 line.long 0x0 "GRP_MGR_MA3_$1,Assign master 96~127 for group manager 0" hexmask.long 0x0 0.--31. 1. "MID,Indicate if master 96~127 is resource manager." repeat.end group.long 0x2200++0x3 line.long 0x0 "DOM_GID_0,Indicate which group domain 0 belong to" bitfld.long 0x0 3. "LOCK,Lock write for GID" "0,1" bitfld.long 0x0 0.--2. "GID,Group ID" "0,1,2,3,4,5,6,7" repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x18 0x30 0x48 0x60 0x78 0x90 0xA8 0xC0 0xD8 0xF0 0x108 0x120 0x138 0x150 0x168 ) group.long ($2+0x2204)++0x3 line.long 0x0 "DOM_OWN_$1,Assign owner for function domain 0." bitfld.long 0x0 17. "MID_LOCK,Lock write for MID_EN and MID_LOW and MID_HIG registers." "0,1" bitfld.long 0x0 16. "MID_EN,Master ID check enable" "0,1" bitfld.long 0x0 15. "PRI_PER_LOCK,Lock write for PRI_PER and PRI_PER_EN" "0,1" bitfld.long 0x0 13.--14. "PRI_PER,Group manager privileged access permission. bit0 for privileged access bit1 for user access" "0,1,2,3" newline bitfld.long 0x0 12. "PRI_PER_EN,Group manager privileged access permission enable." "0,1" bitfld.long 0x0 11. "SEC_PER_LOCK,Lock for SEC_PER and SEC_PER_LOCK" "0,1" bitfld.long 0x0 9.--10. "SEC_PER,Domain owner secure access permission. bit 0 for secure access bit 1 for non-secure access" "0,1,2,3" bitfld.long 0x0 8. "SEC_PER_EN,Domain owner secure permission enable" "0,1" newline bitfld.long 0x0 1. "DOM_OWN_EN_LOCK,Lock for DOM_OWN_EN" "0,1" bitfld.long 0x0 0. "DOM_OWN_EN,Domain owner enable. When the bit is disable there is no domain owner." "0,1" repeat.end repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x18 0x30 0x48 0x60 0x78 0x90 0xA8 0xC0 0xD8 0xF0 0x108 0x120 0x138 0x150 0x168 ) group.long ($2+0x2208)++0x3 line.long 0x0 "DOM_OWN_MA0_$1,Assign master 0~31 for domain owner 0" hexmask.long 0x0 0.--31. 1. "MID,Assign master 0~31 for resource manager" repeat.end repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x18 0x30 0x48 0x60 0x78 0x90 0xA8 0xC0 0xD8 0xF0 0x108 0x120 0x138 0x150 0x168 ) group.long ($2+0x220C)++0x3 line.long 0x0 "DOM_OWN_MA1_$1,Assign master 32~63 for domain owner 0" hexmask.long 0x0 0.--31. 1. "MID,Indicate if master 32~63 is resource manager." repeat.end repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x18 0x30 0x48 0x60 0x78 0x90 0xA8 0xC0 0xD8 0xF0 0x108 0x120 0x138 0x150 0x168 ) group.long ($2+0x2210)++0x3 line.long 0x0 "DOM_OWN_MA2_$1,Assign master 64~95 for domain owner 0" hexmask.long 0x0 0.--31. 1. "MID,Indicate if master 64~95 is resource manager." repeat.end repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x18 0x30 0x48 0x60 0x78 0x90 0xA8 0xC0 0xD8 0xF0 0x108 0x120 0x138 0x150 0x168 ) group.long ($2+0x2214)++0x3 line.long 0x0 "DOM_OWN_MA3_$1,Assign master 96~127 for domain owner 0" hexmask.long 0x0 0.--31. 1. "MID,Indicate if master 96~127 is resource manager." repeat.end group.long 0x2218++0x3 line.long 0x0 "DOM_GID_1,Indicate which group domain 1 belong to" bitfld.long 0x0 3. "LOCK,Lock write for GID" "0,1" bitfld.long 0x0 0.--2. "GID,Group ID" "0,1,2,3,4,5,6,7" group.long 0x2230++0x3 line.long 0x0 "DOM_GID_2,Indicate which group domain 2 belong to" bitfld.long 0x0 3. "LOCK,Lock write for GID" "0,1" bitfld.long 0x0 0.--2. "GID,Group ID" "0,1,2,3,4,5,6,7" group.long 0x2248++0x3 line.long 0x0 "DOM_GID_3,Indicate which group domain 3 belong to" bitfld.long 0x0 3. "LOCK,Lock write for GID" "0,1" bitfld.long 0x0 0.--2. "GID,Group ID" "0,1,2,3,4,5,6,7" group.long 0x2260++0x3 line.long 0x0 "DOM_GID_4,Indicate which group domain 4 belong to" bitfld.long 0x0 3. "LOCK,Lock write for GID" "0,1" bitfld.long 0x0 0.--2. "GID,Group ID" "0,1,2,3,4,5,6,7" group.long 0x2278++0x3 line.long 0x0 "DOM_GID_5,Indicate which group domain 5 belong to" bitfld.long 0x0 3. "LOCK,Lock write for GID" "0,1" bitfld.long 0x0 0.--2. "GID,Group ID" "0,1,2,3,4,5,6,7" group.long 0x2290++0x3 line.long 0x0 "DOM_GID_6,Indicate which group domain 6 belong to" bitfld.long 0x0 3. "LOCK,Lock write for GID" "0,1" bitfld.long 0x0 0.--2. "GID,Group ID" "0,1,2,3,4,5,6,7" group.long 0x22A8++0x3 line.long 0x0 "DOM_GID_7,Indicate which group domain 7 belong to" bitfld.long 0x0 3. "LOCK,Lock write for GID" "0,1" bitfld.long 0x0 0.--2. "GID,Group ID" "0,1,2,3,4,5,6,7" group.long 0x22C0++0x3 line.long 0x0 "DOM_GID_8,Indicate which group domain 8 belong to" bitfld.long 0x0 3. "LOCK,Lock write for GID" "0,1" bitfld.long 0x0 0.--2. "GID,Group ID" "0,1,2,3,4,5,6,7" group.long 0x22D8++0x3 line.long 0x0 "DOM_GID_9,Indicate which group domain 9 belong to" bitfld.long 0x0 3. "LOCK,Lock write for GID" "0,1" bitfld.long 0x0 0.--2. "GID,Group ID" "0,1,2,3,4,5,6,7" group.long 0x22F0++0x3 line.long 0x0 "DOM_GID_10,Indicate which group domain 10 belong to" bitfld.long 0x0 3. "LOCK,Lock write for GID" "0,1" bitfld.long 0x0 0.--2. "GID,Group ID" "0,1,2,3,4,5,6,7" group.long 0x2308++0x3 line.long 0x0 "DOM_GID_11,Indicate which group domain 11 belong to" bitfld.long 0x0 3. "LOCK,Lock write for GID" "0,1" bitfld.long 0x0 0.--2. "GID,Group ID" "0,1,2,3,4,5,6,7" group.long 0x2320++0x3 line.long 0x0 "DOM_GID_12,Indicate which group domain 12 belong to" bitfld.long 0x0 3. "LOCK,Lock write for GID" "0,1" bitfld.long 0x0 0.--2. "GID,Group ID" "0,1,2,3,4,5,6,7" group.long 0x2338++0x3 line.long 0x0 "DOM_GID_13,Indicate which group domain 13 belong to" bitfld.long 0x0 3. "LOCK,Lock write for GID" "0,1" bitfld.long 0x0 0.--2. "GID,Group ID" "0,1,2,3,4,5,6,7" group.long 0x2350++0x3 line.long 0x0 "DOM_GID_14,Indicate which group domain 14 belong to" bitfld.long 0x0 3. "LOCK,Lock write for GID" "0,1" bitfld.long 0x0 0.--2. "GID,Group ID" "0,1,2,3,4,5,6,7" group.long 0x2368++0x3 line.long 0x0 "DOM_GID_15,Indicate which group domain 15 belong to" bitfld.long 0x0 3. "LOCK,Lock write for GID" "0,1" bitfld.long 0x0 0.--2. "GID,Group ID" "0,1,2,3,4,5,6,7" repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x34 0x68 0x9C 0xD0 0x104 0x138 0x16C 0x1A0 0x1D4 0x208 0x23C 0x270 0x2A4 0x2D8 0x30C ) group.long ($2+0x2400)++0x3 line.long 0x0 "DOM_PER0_$1,Domain Permission Control. It can be only configured by resource manager and domain owner." bitfld.long 0x0 31. "DOM7_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 29.--30. "DOM7_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 28. "DOM7_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 27. "DOM6_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 25.--26. "DOM6_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" newline bitfld.long 0x0 24. "DOM6_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 23. "DOM5_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 21.--22. "DOM5_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 20. "DOM5_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 19. "DOM4_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" newline bitfld.long 0x0 17.--18. "DOM4_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM4_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 15. "DOM3_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 13.--14. "DOM3_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 12. "DOM3_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" newline bitfld.long 0x0 11. "DOM2_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 9.--10. "DOM2_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM2_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 7. "DOM1_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 5.--6. "DOM1_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" newline bitfld.long 0x0 4. "DOM1_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 3. "DOM0_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 1.--2. "DOM0_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM0_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" repeat.end repeat 16. (list 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1A 0x1B 0x1C 0x1D 0x1E 0x1F )(list 0x340 0x374 0x3A8 0x3DC 0x410 0x444 0x478 0x4AC 0x4E0 0x514 0x548 0x57C 0x5B0 0x5E4 0x618 0x64C ) group.long ($2+0x2400)++0x3 line.long 0x0 "DOM_PER0_$1,Domain Permission Control. It can be only configured by resource manager and domain owner." bitfld.long 0x0 31. "DOM7_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 29.--30. "DOM7_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 28. "DOM7_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 27. "DOM6_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 25.--26. "DOM6_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" newline bitfld.long 0x0 24. "DOM6_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 23. "DOM5_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 21.--22. "DOM5_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 20. "DOM5_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 19. "DOM4_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" newline bitfld.long 0x0 17.--18. "DOM4_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM4_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 15. "DOM3_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 13.--14. "DOM3_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 12. "DOM3_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" newline bitfld.long 0x0 11. "DOM2_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 9.--10. "DOM2_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM2_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 7. "DOM1_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 5.--6. "DOM1_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" newline bitfld.long 0x0 4. "DOM1_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 3. "DOM0_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 1.--2. "DOM0_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM0_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" repeat.end repeat 16. (list 0x20 0x21 0x22 0x23 0x24 0x25 0x26 0x27 0x28 0x29 0x2A 0x2B 0x2C 0x2D 0x2E 0x2F )(list 0x680 0x6B4 0x6E8 0x71C 0x750 0x784 0x7B8 0x7EC 0x820 0x854 0x888 0x8BC 0x8F0 0x924 0x958 0x98C ) group.long ($2+0x2400)++0x3 line.long 0x0 "DOM_PER0_$1,Domain Permission Control. It can be only configured by resource manager and domain owner." bitfld.long 0x0 31. "DOM7_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 29.--30. "DOM7_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 28. "DOM7_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 27. "DOM6_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 25.--26. "DOM6_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" newline bitfld.long 0x0 24. "DOM6_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 23. "DOM5_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 21.--22. "DOM5_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 20. "DOM5_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 19. "DOM4_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" newline bitfld.long 0x0 17.--18. "DOM4_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM4_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 15. "DOM3_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 13.--14. "DOM3_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 12. "DOM3_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" newline bitfld.long 0x0 11. "DOM2_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 9.--10. "DOM2_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM2_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 7. "DOM1_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 5.--6. "DOM1_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" newline bitfld.long 0x0 4. "DOM1_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 3. "DOM0_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 1.--2. "DOM0_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM0_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" repeat.end repeat 16. (list 0x30 0x31 0x32 0x33 0x34 0x35 0x36 0x37 0x38 0x39 0x3A 0x3B 0x3C 0x3D 0x3E 0x3F )(list 0x9C0 0x9F4 0xA28 0xA5C 0xA90 0xAC4 0xAF8 0xB2C 0xB60 0xB94 0xBC8 0xBFC 0xC30 0xC64 0xC98 0xCCC ) group.long ($2+0x2400)++0x3 line.long 0x0 "DOM_PER0_$1,Domain Permission Control. It can be only configured by resource manager and domain owner." bitfld.long 0x0 31. "DOM7_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 29.--30. "DOM7_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 28. "DOM7_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 27. "DOM6_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 25.--26. "DOM6_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" newline bitfld.long 0x0 24. "DOM6_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 23. "DOM5_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 21.--22. "DOM5_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 20. "DOM5_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 19. "DOM4_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" newline bitfld.long 0x0 17.--18. "DOM4_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM4_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 15. "DOM3_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 13.--14. "DOM3_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 12. "DOM3_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" newline bitfld.long 0x0 11. "DOM2_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 9.--10. "DOM2_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM2_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 7. "DOM1_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 5.--6. "DOM1_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" newline bitfld.long 0x0 4. "DOM1_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 3. "DOM0_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 1.--2. "DOM0_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM0_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" repeat.end repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x34 0x68 0x9C 0xD0 0x104 0x138 0x16C 0x1A0 0x1D4 0x208 0x23C 0x270 0x2A4 0x2D8 0x30C ) group.long ($2+0x2404)++0x3 line.long 0x0 "DOM_PER1_$1,Domain Permission Control. It can be only configured by resource manager and domain owner." bitfld.long 0x0 31. "DOM15_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 29.--30. "DOM15_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 28. "DOM15_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 27. "DOM14_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 25.--26. "DOM14_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" newline bitfld.long 0x0 24. "DOM14_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 23. "DOM13_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 21.--22. "DOM13_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 20. "DOM13_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 19. "DOM12_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" newline bitfld.long 0x0 17.--18. "DOM12_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM12_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 15. "DOM11_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 13.--14. "DOM11_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 12. "DOM11_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" newline bitfld.long 0x0 11. "DOM10_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 9.--10. "DOM10_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM10_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 7. "DOM9_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 5.--6. "DOM9_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" newline bitfld.long 0x0 4. "DOM9_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 3. "DOM8_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 1.--2. "DOM8_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM8_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" repeat.end repeat 16. (list 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1A 0x1B 0x1C 0x1D 0x1E 0x1F )(list 0x340 0x374 0x3A8 0x3DC 0x410 0x444 0x478 0x4AC 0x4E0 0x514 0x548 0x57C 0x5B0 0x5E4 0x618 0x64C ) group.long ($2+0x2404)++0x3 line.long 0x0 "DOM_PER1_$1,Domain Permission Control. It can be only configured by resource manager and domain owner." bitfld.long 0x0 31. "DOM15_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 29.--30. "DOM15_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 28. "DOM15_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 27. "DOM14_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 25.--26. "DOM14_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" newline bitfld.long 0x0 24. "DOM14_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 23. "DOM13_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 21.--22. "DOM13_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 20. "DOM13_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 19. "DOM12_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" newline bitfld.long 0x0 17.--18. "DOM12_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM12_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 15. "DOM11_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 13.--14. "DOM11_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 12. "DOM11_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" newline bitfld.long 0x0 11. "DOM10_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 9.--10. "DOM10_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM10_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 7. "DOM9_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 5.--6. "DOM9_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" newline bitfld.long 0x0 4. "DOM9_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 3. "DOM8_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 1.--2. "DOM8_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM8_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" repeat.end repeat 16. (list 0x20 0x21 0x22 0x23 0x24 0x25 0x26 0x27 0x28 0x29 0x2A 0x2B 0x2C 0x2D 0x2E 0x2F )(list 0x680 0x6B4 0x6E8 0x71C 0x750 0x784 0x7B8 0x7EC 0x820 0x854 0x888 0x8BC 0x8F0 0x924 0x958 0x98C ) group.long ($2+0x2404)++0x3 line.long 0x0 "DOM_PER1_$1,Domain Permission Control. It can be only configured by resource manager and domain owner." bitfld.long 0x0 31. "DOM15_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 29.--30. "DOM15_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 28. "DOM15_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 27. "DOM14_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 25.--26. "DOM14_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" newline bitfld.long 0x0 24. "DOM14_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 23. "DOM13_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 21.--22. "DOM13_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 20. "DOM13_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 19. "DOM12_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" newline bitfld.long 0x0 17.--18. "DOM12_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM12_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 15. "DOM11_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 13.--14. "DOM11_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 12. "DOM11_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" newline bitfld.long 0x0 11. "DOM10_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 9.--10. "DOM10_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM10_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 7. "DOM9_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 5.--6. "DOM9_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" newline bitfld.long 0x0 4. "DOM9_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 3. "DOM8_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 1.--2. "DOM8_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM8_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" repeat.end repeat 16. (list 0x30 0x31 0x32 0x33 0x34 0x35 0x36 0x37 0x38 0x39 0x3A 0x3B 0x3C 0x3D 0x3E 0x3F )(list 0x9C0 0x9F4 0xA28 0xA5C 0xA90 0xAC4 0xAF8 0xB2C 0xB60 0xB94 0xBC8 0xBFC 0xC30 0xC64 0xC98 0xCCC ) group.long ($2+0x2404)++0x3 line.long 0x0 "DOM_PER1_$1,Domain Permission Control. It can be only configured by resource manager and domain owner." bitfld.long 0x0 31. "DOM15_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 29.--30. "DOM15_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 28. "DOM15_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 27. "DOM14_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 25.--26. "DOM14_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" newline bitfld.long 0x0 24. "DOM14_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 23. "DOM13_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 21.--22. "DOM13_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 20. "DOM13_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 19. "DOM12_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" newline bitfld.long 0x0 17.--18. "DOM12_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM12_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 15. "DOM11_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 13.--14. "DOM11_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 12. "DOM11_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" newline bitfld.long 0x0 11. "DOM10_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 9.--10. "DOM10_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM10_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 7. "DOM9_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 5.--6. "DOM9_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" newline bitfld.long 0x0 4. "DOM9_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 3. "DOM8_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 1.--2. "DOM8_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM8_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" repeat.end repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x34 0x68 0x9C 0xD0 0x104 0x138 0x16C 0x1A0 0x1D4 0x208 0x23C 0x270 0x2A4 0x2D8 0x30C ) group.long ($2+0x2408)++0x3 line.long 0x0 "SEC_PER0_$1,This register is only used for resource manager to control secure access permission." bitfld.long 0x0 31. "DOM3_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM3_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM3_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM3_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM2_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM2_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM2_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM2_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM1_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM1_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM1_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM1_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM0_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM0_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM0_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM0_SEC_EN,Domain secure permission control enable" "0,1" repeat.end repeat 16. (list 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1A 0x1B 0x1C 0x1D 0x1E 0x1F )(list 0x340 0x374 0x3A8 0x3DC 0x410 0x444 0x478 0x4AC 0x4E0 0x514 0x548 0x57C 0x5B0 0x5E4 0x618 0x64C ) group.long ($2+0x2408)++0x3 line.long 0x0 "SEC_PER0_$1,This register is only used for resource manager to control secure access permission." bitfld.long 0x0 31. "DOM3_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM3_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM3_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM3_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM2_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM2_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM2_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM2_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM1_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM1_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM1_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM1_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM0_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM0_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM0_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM0_SEC_EN,Domain secure permission control enable" "0,1" repeat.end repeat 16. (list 0x20 0x21 0x22 0x23 0x24 0x25 0x26 0x27 0x28 0x29 0x2A 0x2B 0x2C 0x2D 0x2E 0x2F )(list 0x680 0x6B4 0x6E8 0x71C 0x750 0x784 0x7B8 0x7EC 0x820 0x854 0x888 0x8BC 0x8F0 0x924 0x958 0x98C ) group.long ($2+0x2408)++0x3 line.long 0x0 "SEC_PER0_$1,This register is only used for resource manager to control secure access permission." bitfld.long 0x0 31. "DOM3_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM3_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM3_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM3_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM2_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM2_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM2_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM2_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM1_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM1_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM1_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM1_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM0_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM0_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM0_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM0_SEC_EN,Domain secure permission control enable" "0,1" repeat.end repeat 16. (list 0x30 0x31 0x32 0x33 0x34 0x35 0x36 0x37 0x38 0x39 0x3A 0x3B 0x3C 0x3D 0x3E 0x3F )(list 0x9C0 0x9F4 0xA28 0xA5C 0xA90 0xAC4 0xAF8 0xB2C 0xB60 0xB94 0xBC8 0xBFC 0xC30 0xC64 0xC98 0xCCC ) group.long ($2+0x2408)++0x3 line.long 0x0 "SEC_PER0_$1,This register is only used for resource manager to control secure access permission." bitfld.long 0x0 31. "DOM3_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM3_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM3_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM3_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM2_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM2_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM2_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM2_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM1_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM1_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM1_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM1_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM0_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM0_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM0_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM0_SEC_EN,Domain secure permission control enable" "0,1" repeat.end repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x34 0x68 0x9C 0xD0 0x104 0x138 0x16C 0x1A0 0x1D4 0x208 0x23C 0x270 0x2A4 0x2D8 0x30C ) group.long ($2+0x240C)++0x3 line.long 0x0 "SEC_PER1_$1,This register is only used for resource manager to control secure access permission." bitfld.long 0x0 31. "DOM7_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM7_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM7_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM7_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM6_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM6_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM6_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM6_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM5_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM5_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM5_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM5_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM4_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM4_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM4_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM4_SEC_EN,Domain secure permission control enable" "0,1" repeat.end repeat 16. (list 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1A 0x1B 0x1C 0x1D 0x1E 0x1F )(list 0x340 0x374 0x3A8 0x3DC 0x410 0x444 0x478 0x4AC 0x4E0 0x514 0x548 0x57C 0x5B0 0x5E4 0x618 0x64C ) group.long ($2+0x240C)++0x3 line.long 0x0 "SEC_PER1_$1,This register is only used for resource manager to control secure access permission." bitfld.long 0x0 31. "DOM7_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM7_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM7_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM7_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM6_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM6_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM6_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM6_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM5_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM5_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM5_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM5_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM4_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM4_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM4_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM4_SEC_EN,Domain secure permission control enable" "0,1" repeat.end repeat 16. (list 0x20 0x21 0x22 0x23 0x24 0x25 0x26 0x27 0x28 0x29 0x2A 0x2B 0x2C 0x2D 0x2E 0x2F )(list 0x680 0x6B4 0x6E8 0x71C 0x750 0x784 0x7B8 0x7EC 0x820 0x854 0x888 0x8BC 0x8F0 0x924 0x958 0x98C ) group.long ($2+0x240C)++0x3 line.long 0x0 "SEC_PER1_$1,This register is only used for resource manager to control secure access permission." bitfld.long 0x0 31. "DOM7_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM7_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM7_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM7_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM6_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM6_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM6_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM6_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM5_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM5_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM5_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM5_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM4_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM4_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM4_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM4_SEC_EN,Domain secure permission control enable" "0,1" repeat.end repeat 16. (list 0x30 0x31 0x32 0x33 0x34 0x35 0x36 0x37 0x38 0x39 0x3A 0x3B 0x3C 0x3D 0x3E 0x3F )(list 0x9C0 0x9F4 0xA28 0xA5C 0xA90 0xAC4 0xAF8 0xB2C 0xB60 0xB94 0xBC8 0xBFC 0xC30 0xC64 0xC98 0xCCC ) group.long ($2+0x240C)++0x3 line.long 0x0 "SEC_PER1_$1,This register is only used for resource manager to control secure access permission." bitfld.long 0x0 31. "DOM7_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM7_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM7_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM7_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM6_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM6_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM6_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM6_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM5_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM5_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM5_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM5_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM4_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM4_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM4_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM4_SEC_EN,Domain secure permission control enable" "0,1" repeat.end repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x34 0x68 0x9C 0xD0 0x104 0x138 0x16C 0x1A0 0x1D4 0x208 0x23C 0x270 0x2A4 0x2D8 0x30C ) group.long ($2+0x2410)++0x3 line.long 0x0 "SEC_PER2_$1,This register is only used for resource manager to control secure access permission." bitfld.long 0x0 31. "DOM11_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM11_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM11_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM11_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM10_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM10_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM10_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM10_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM9_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM9_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM9_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM9_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM8_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM8_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM8_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM8_SEC_EN,Domain secure permission control enable" "0,1" repeat.end repeat 16. (list 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1A 0x1B 0x1C 0x1D 0x1E 0x1F )(list 0x340 0x374 0x3A8 0x3DC 0x410 0x444 0x478 0x4AC 0x4E0 0x514 0x548 0x57C 0x5B0 0x5E4 0x618 0x64C ) group.long ($2+0x2410)++0x3 line.long 0x0 "SEC_PER2_$1,This register is only used for resource manager to control secure access permission." bitfld.long 0x0 31. "DOM11_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM11_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM11_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM11_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM10_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM10_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM10_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM10_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM9_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM9_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM9_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM9_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM8_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM8_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM8_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM8_SEC_EN,Domain secure permission control enable" "0,1" repeat.end repeat 16. (list 0x20 0x21 0x22 0x23 0x24 0x25 0x26 0x27 0x28 0x29 0x2A 0x2B 0x2C 0x2D 0x2E 0x2F )(list 0x680 0x6B4 0x6E8 0x71C 0x750 0x784 0x7B8 0x7EC 0x820 0x854 0x888 0x8BC 0x8F0 0x924 0x958 0x98C ) group.long ($2+0x2410)++0x3 line.long 0x0 "SEC_PER2_$1,This register is only used for resource manager to control secure access permission." bitfld.long 0x0 31. "DOM11_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM11_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM11_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM11_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM10_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM10_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM10_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM10_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM9_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM9_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM9_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM9_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM8_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM8_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM8_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM8_SEC_EN,Domain secure permission control enable" "0,1" repeat.end repeat 16. (list 0x30 0x31 0x32 0x33 0x34 0x35 0x36 0x37 0x38 0x39 0x3A 0x3B 0x3C 0x3D 0x3E 0x3F )(list 0x9C0 0x9F4 0xA28 0xA5C 0xA90 0xAC4 0xAF8 0xB2C 0xB60 0xB94 0xBC8 0xBFC 0xC30 0xC64 0xC98 0xCCC ) group.long ($2+0x2410)++0x3 line.long 0x0 "SEC_PER2_$1,This register is only used for resource manager to control secure access permission." bitfld.long 0x0 31. "DOM11_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM11_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM11_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM11_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM10_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM10_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM10_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM10_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM9_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM9_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM9_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM9_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM8_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM8_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM8_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM8_SEC_EN,Domain secure permission control enable" "0,1" repeat.end repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x34 0x68 0x9C 0xD0 0x104 0x138 0x16C 0x1A0 0x1D4 0x208 0x23C 0x270 0x2A4 0x2D8 0x30C ) group.long ($2+0x2414)++0x3 line.long 0x0 "SEC_PER3_$1,This register is only used for resource manager to control secure access permission." bitfld.long 0x0 31. "DOM15_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM15_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM15_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM15_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM14_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM14_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM14_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM14_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM13_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM13_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM13_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM13_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM12_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM12_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM12_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM12_SEC_EN,Domain secure permission control enable" "0,1" repeat.end repeat 16. (list 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1A 0x1B 0x1C 0x1D 0x1E 0x1F )(list 0x340 0x374 0x3A8 0x3DC 0x410 0x444 0x478 0x4AC 0x4E0 0x514 0x548 0x57C 0x5B0 0x5E4 0x618 0x64C ) group.long ($2+0x2414)++0x3 line.long 0x0 "SEC_PER3_$1,This register is only used for resource manager to control secure access permission." bitfld.long 0x0 31. "DOM15_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM15_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM15_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM15_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM14_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM14_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM14_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM14_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM13_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM13_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM13_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM13_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM12_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM12_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM12_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM12_SEC_EN,Domain secure permission control enable" "0,1" repeat.end repeat 16. (list 0x20 0x21 0x22 0x23 0x24 0x25 0x26 0x27 0x28 0x29 0x2A 0x2B 0x2C 0x2D 0x2E 0x2F )(list 0x680 0x6B4 0x6E8 0x71C 0x750 0x784 0x7B8 0x7EC 0x820 0x854 0x888 0x8BC 0x8F0 0x924 0x958 0x98C ) group.long ($2+0x2414)++0x3 line.long 0x0 "SEC_PER3_$1,This register is only used for resource manager to control secure access permission." bitfld.long 0x0 31. "DOM15_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM15_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM15_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM15_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM14_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM14_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM14_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM14_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM13_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM13_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM13_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM13_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM12_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM12_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM12_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM12_SEC_EN,Domain secure permission control enable" "0,1" repeat.end repeat 16. (list 0x30 0x31 0x32 0x33 0x34 0x35 0x36 0x37 0x38 0x39 0x3A 0x3B 0x3C 0x3D 0x3E 0x3F )(list 0x9C0 0x9F4 0xA28 0xA5C 0xA90 0xAC4 0xAF8 0xB2C 0xB60 0xB94 0xBC8 0xBFC 0xC30 0xC64 0xC98 0xCCC ) group.long ($2+0x2414)++0x3 line.long 0x0 "SEC_PER3_$1,This register is only used for resource manager to control secure access permission." bitfld.long 0x0 31. "DOM15_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM15_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM15_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM15_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM14_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM14_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM14_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM14_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM13_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM13_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM13_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM13_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM12_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM12_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM12_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM12_SEC_EN,Domain secure permission control enable" "0,1" repeat.end repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x34 0x68 0x9C 0xD0 0x104 0x138 0x16C 0x1A0 0x1D4 0x208 0x23C 0x270 0x2A4 0x2D8 0x30C ) group.long ($2+0x2418)++0x3 line.long 0x0 "PRI_PER0_$1,This register is only used for resource manager to control privileged access permission." bitfld.long 0x0 31. "DOM3_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM3_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM3_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM3_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM2_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM2_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM2_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM2_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM1_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM1_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM1_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM1_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM0_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM0_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM0_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM0_PRI_EN,Domain privileged permission control enable" "0,1" repeat.end repeat 16. (list 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1A 0x1B 0x1C 0x1D 0x1E 0x1F )(list 0x340 0x374 0x3A8 0x3DC 0x410 0x444 0x478 0x4AC 0x4E0 0x514 0x548 0x57C 0x5B0 0x5E4 0x618 0x64C ) group.long ($2+0x2418)++0x3 line.long 0x0 "PRI_PER0_$1,This register is only used for resource manager to control privileged access permission." bitfld.long 0x0 31. "DOM3_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM3_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM3_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM3_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM2_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM2_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM2_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM2_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM1_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM1_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM1_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM1_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM0_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM0_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM0_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM0_PRI_EN,Domain privileged permission control enable" "0,1" repeat.end repeat 16. (list 0x20 0x21 0x22 0x23 0x24 0x25 0x26 0x27 0x28 0x29 0x2A 0x2B 0x2C 0x2D 0x2E 0x2F )(list 0x680 0x6B4 0x6E8 0x71C 0x750 0x784 0x7B8 0x7EC 0x820 0x854 0x888 0x8BC 0x8F0 0x924 0x958 0x98C ) group.long ($2+0x2418)++0x3 line.long 0x0 "PRI_PER0_$1,This register is only used for resource manager to control privileged access permission." bitfld.long 0x0 31. "DOM3_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM3_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM3_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM3_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM2_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM2_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM2_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM2_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM1_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM1_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM1_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM1_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM0_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM0_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM0_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM0_PRI_EN,Domain privileged permission control enable" "0,1" repeat.end repeat 16. (list 0x30 0x31 0x32 0x33 0x34 0x35 0x36 0x37 0x38 0x39 0x3A 0x3B 0x3C 0x3D 0x3E 0x3F )(list 0x9C0 0x9F4 0xA28 0xA5C 0xA90 0xAC4 0xAF8 0xB2C 0xB60 0xB94 0xBC8 0xBFC 0xC30 0xC64 0xC98 0xCCC ) group.long ($2+0x2418)++0x3 line.long 0x0 "PRI_PER0_$1,This register is only used for resource manager to control privileged access permission." bitfld.long 0x0 31. "DOM3_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM3_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM3_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM3_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM2_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM2_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM2_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM2_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM1_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM1_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM1_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM1_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM0_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM0_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM0_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM0_PRI_EN,Domain privileged permission control enable" "0,1" repeat.end repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x34 0x68 0x9C 0xD0 0x104 0x138 0x16C 0x1A0 0x1D4 0x208 0x23C 0x270 0x2A4 0x2D8 0x30C ) group.long ($2+0x241C)++0x3 line.long 0x0 "PRI_PER1_$1,This register is only used for resource manager to control privileged access permission." bitfld.long 0x0 31. "DOM7_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM7_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM7_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM7_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM6_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM6_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM6_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM6_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM5_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM5_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM5_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM5_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM4_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM4_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM4_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM4_PRI_EN,Domain privileged permission control enable" "0,1" repeat.end repeat 16. (list 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1A 0x1B 0x1C 0x1D 0x1E 0x1F )(list 0x340 0x374 0x3A8 0x3DC 0x410 0x444 0x478 0x4AC 0x4E0 0x514 0x548 0x57C 0x5B0 0x5E4 0x618 0x64C ) group.long ($2+0x241C)++0x3 line.long 0x0 "PRI_PER1_$1,This register is only used for resource manager to control privileged access permission." bitfld.long 0x0 31. "DOM7_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM7_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM7_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM7_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM6_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM6_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM6_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM6_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM5_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM5_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM5_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM5_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM4_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM4_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM4_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM4_PRI_EN,Domain privileged permission control enable" "0,1" repeat.end repeat 16. (list 0x20 0x21 0x22 0x23 0x24 0x25 0x26 0x27 0x28 0x29 0x2A 0x2B 0x2C 0x2D 0x2E 0x2F )(list 0x680 0x6B4 0x6E8 0x71C 0x750 0x784 0x7B8 0x7EC 0x820 0x854 0x888 0x8BC 0x8F0 0x924 0x958 0x98C ) group.long ($2+0x241C)++0x3 line.long 0x0 "PRI_PER1_$1,This register is only used for resource manager to control privileged access permission." bitfld.long 0x0 31. "DOM7_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM7_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM7_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM7_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM6_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM6_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM6_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM6_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM5_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM5_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM5_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM5_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM4_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM4_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM4_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM4_PRI_EN,Domain privileged permission control enable" "0,1" repeat.end repeat 16. (list 0x30 0x31 0x32 0x33 0x34 0x35 0x36 0x37 0x38 0x39 0x3A 0x3B 0x3C 0x3D 0x3E 0x3F )(list 0x9C0 0x9F4 0xA28 0xA5C 0xA90 0xAC4 0xAF8 0xB2C 0xB60 0xB94 0xBC8 0xBFC 0xC30 0xC64 0xC98 0xCCC ) group.long ($2+0x241C)++0x3 line.long 0x0 "PRI_PER1_$1,This register is only used for resource manager to control privileged access permission." bitfld.long 0x0 31. "DOM7_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM7_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM7_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM7_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM6_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM6_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM6_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM6_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM5_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM5_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM5_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM5_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM4_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM4_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM4_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM4_PRI_EN,Domain privileged permission control enable" "0,1" repeat.end repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x34 0x68 0x9C 0xD0 0x104 0x138 0x16C 0x1A0 0x1D4 0x208 0x23C 0x270 0x2A4 0x2D8 0x30C ) group.long ($2+0x2420)++0x3 line.long 0x0 "PRI_PER2_$1,This register is only used for resource manager to control privileged access permission." bitfld.long 0x0 31. "DOM11_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM11_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM11_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM11_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM10_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM10_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM10_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM10_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM9_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM9_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM9_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM9_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM8_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM8_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM8_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM8_PRI_EN,Domain privileged permission control enable" "0,1" repeat.end repeat 16. (list 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1A 0x1B 0x1C 0x1D 0x1E 0x1F )(list 0x340 0x374 0x3A8 0x3DC 0x410 0x444 0x478 0x4AC 0x4E0 0x514 0x548 0x57C 0x5B0 0x5E4 0x618 0x64C ) group.long ($2+0x2420)++0x3 line.long 0x0 "PRI_PER2_$1,This register is only used for resource manager to control privileged access permission." bitfld.long 0x0 31. "DOM11_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM11_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM11_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM11_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM10_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM10_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM10_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM10_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM9_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM9_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM9_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM9_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM8_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM8_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM8_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM8_PRI_EN,Domain privileged permission control enable" "0,1" repeat.end repeat 16. (list 0x20 0x21 0x22 0x23 0x24 0x25 0x26 0x27 0x28 0x29 0x2A 0x2B 0x2C 0x2D 0x2E 0x2F )(list 0x680 0x6B4 0x6E8 0x71C 0x750 0x784 0x7B8 0x7EC 0x820 0x854 0x888 0x8BC 0x8F0 0x924 0x958 0x98C ) group.long ($2+0x2420)++0x3 line.long 0x0 "PRI_PER2_$1,This register is only used for resource manager to control privileged access permission." bitfld.long 0x0 31. "DOM11_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM11_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM11_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM11_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM10_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM10_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM10_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM10_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM9_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM9_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM9_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM9_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM8_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM8_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM8_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM8_PRI_EN,Domain privileged permission control enable" "0,1" repeat.end repeat 16. (list 0x30 0x31 0x32 0x33 0x34 0x35 0x36 0x37 0x38 0x39 0x3A 0x3B 0x3C 0x3D 0x3E 0x3F )(list 0x9C0 0x9F4 0xA28 0xA5C 0xA90 0xAC4 0xAF8 0xB2C 0xB60 0xB94 0xBC8 0xBFC 0xC30 0xC64 0xC98 0xCCC ) group.long ($2+0x2420)++0x3 line.long 0x0 "PRI_PER2_$1,This register is only used for resource manager to control privileged access permission." bitfld.long 0x0 31. "DOM11_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM11_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM11_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM11_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM10_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM10_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM10_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM10_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM9_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM9_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM9_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM9_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM8_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM8_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM8_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM8_PRI_EN,Domain privileged permission control enable" "0,1" repeat.end repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x34 0x68 0x9C 0xD0 0x104 0x138 0x16C 0x1A0 0x1D4 0x208 0x23C 0x270 0x2A4 0x2D8 0x30C ) group.long ($2+0x2424)++0x3 line.long 0x0 "PRI_PER3_$1,This register is only used for resource manager to control privileged access permission." bitfld.long 0x0 31. "DOM15_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM15_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM15_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM15_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM14_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM14_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM14_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM14_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM13_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM13_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM13_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM13_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM12_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM12_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM12_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM12_PRI_EN,Domain privileged permission control enable" "0,1" repeat.end repeat 16. (list 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1A 0x1B 0x1C 0x1D 0x1E 0x1F )(list 0x340 0x374 0x3A8 0x3DC 0x410 0x444 0x478 0x4AC 0x4E0 0x514 0x548 0x57C 0x5B0 0x5E4 0x618 0x64C ) group.long ($2+0x2424)++0x3 line.long 0x0 "PRI_PER3_$1,This register is only used for resource manager to control privileged access permission." bitfld.long 0x0 31. "DOM15_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM15_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM15_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM15_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM14_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM14_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM14_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM14_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM13_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM13_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM13_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM13_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM12_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM12_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM12_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM12_PRI_EN,Domain privileged permission control enable" "0,1" repeat.end repeat 16. (list 0x20 0x21 0x22 0x23 0x24 0x25 0x26 0x27 0x28 0x29 0x2A 0x2B 0x2C 0x2D 0x2E 0x2F )(list 0x680 0x6B4 0x6E8 0x71C 0x750 0x784 0x7B8 0x7EC 0x820 0x854 0x888 0x8BC 0x8F0 0x924 0x958 0x98C ) group.long ($2+0x2424)++0x3 line.long 0x0 "PRI_PER3_$1,This register is only used for resource manager to control privileged access permission." bitfld.long 0x0 31. "DOM15_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM15_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM15_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM15_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM14_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM14_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM14_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM14_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM13_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM13_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM13_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM13_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM12_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM12_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM12_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM12_PRI_EN,Domain privileged permission control enable" "0,1" repeat.end repeat 16. (list 0x30 0x31 0x32 0x33 0x34 0x35 0x36 0x37 0x38 0x39 0x3A 0x3B 0x3C 0x3D 0x3E 0x3F )(list 0x9C0 0x9F4 0xA28 0xA5C 0xA90 0xAC4 0xAF8 0xB2C 0xB60 0xB94 0xBC8 0xBFC 0xC30 0xC64 0xC98 0xCCC ) group.long ($2+0x2424)++0x3 line.long 0x0 "PRI_PER3_$1,This register is only used for resource manager to control privileged access permission." bitfld.long 0x0 31. "DOM15_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM15_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM15_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM15_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM14_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM14_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM14_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM14_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM13_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM13_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM13_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM13_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM12_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM12_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM12_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM12_PRI_EN,Domain privileged permission control enable" "0,1" repeat.end repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x34 0x68 0x9C 0xD0 0x104 0x138 0x16C 0x1A0 0x1D4 0x208 0x23C 0x270 0x2A4 0x2D8 0x30C ) group.long ($2+0x2428)++0x3 line.long 0x0 "DOM_SEC_PER_$1,This register is only used for domain master to control secure access permission. When the domain master write this register. it only changes the secure permission for itself. When the domain master read this register. it gets permission.." bitfld.long 0x0 7. "DOM_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" newline bitfld.long 0x0 0. "DOM_SEC_EN,Domain secure permission control enable" "0,1" repeat.end repeat 16. (list 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1A 0x1B 0x1C 0x1D 0x1E 0x1F )(list 0x340 0x374 0x3A8 0x3DC 0x410 0x444 0x478 0x4AC 0x4E0 0x514 0x548 0x57C 0x5B0 0x5E4 0x618 0x64C ) group.long ($2+0x2428)++0x3 line.long 0x0 "DOM_SEC_PER_$1,This register is only used for domain master to control secure access permission. When the domain master write this register. it only changes the secure permission for itself. When the domain master read this register. it gets permission.." bitfld.long 0x0 7. "DOM_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" newline bitfld.long 0x0 0. "DOM_SEC_EN,Domain secure permission control enable" "0,1" repeat.end repeat 16. (list 0x20 0x21 0x22 0x23 0x24 0x25 0x26 0x27 0x28 0x29 0x2A 0x2B 0x2C 0x2D 0x2E 0x2F )(list 0x680 0x6B4 0x6E8 0x71C 0x750 0x784 0x7B8 0x7EC 0x820 0x854 0x888 0x8BC 0x8F0 0x924 0x958 0x98C ) group.long ($2+0x2428)++0x3 line.long 0x0 "DOM_SEC_PER_$1,This register is only used for domain master to control secure access permission. When the domain master write this register. it only changes the secure permission for itself. When the domain master read this register. it gets permission.." bitfld.long 0x0 7. "DOM_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" newline bitfld.long 0x0 0. "DOM_SEC_EN,Domain secure permission control enable" "0,1" repeat.end repeat 16. (list 0x30 0x31 0x32 0x33 0x34 0x35 0x36 0x37 0x38 0x39 0x3A 0x3B 0x3C 0x3D 0x3E 0x3F )(list 0x9C0 0x9F4 0xA28 0xA5C 0xA90 0xAC4 0xAF8 0xB2C 0xB60 0xB94 0xBC8 0xBFC 0xC30 0xC64 0xC98 0xCCC ) group.long ($2+0x2428)++0x3 line.long 0x0 "DOM_SEC_PER_$1,This register is only used for domain master to control secure access permission. When the domain master write this register. it only changes the secure permission for itself. When the domain master read this register. it gets permission.." bitfld.long 0x0 7. "DOM_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" newline bitfld.long 0x0 0. "DOM_SEC_EN,Domain secure permission control enable" "0,1" repeat.end repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x34 0x68 0x9C 0xD0 0x104 0x138 0x16C 0x1A0 0x1D4 0x208 0x23C 0x270 0x2A4 0x2D8 0x30C ) group.long ($2+0x242C)++0x3 line.long 0x0 "DOM_PRI_PER_$1,This register is only used for domain master to control secure access permission. When the domain master write this register. it only changes the secure permission for itself. When the domain master read this register. it gets permission.." bitfld.long 0x0 7. "DOM_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" newline bitfld.long 0x0 0. "DOM_PRI_EN,Domain privileged permission control enable" "0,1" repeat.end repeat 16. (list 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1A 0x1B 0x1C 0x1D 0x1E 0x1F )(list 0x340 0x374 0x3A8 0x3DC 0x410 0x444 0x478 0x4AC 0x4E0 0x514 0x548 0x57C 0x5B0 0x5E4 0x618 0x64C ) group.long ($2+0x242C)++0x3 line.long 0x0 "DOM_PRI_PER_$1,This register is only used for domain master to control secure access permission. When the domain master write this register. it only changes the secure permission for itself. When the domain master read this register. it gets permission.." bitfld.long 0x0 7. "DOM_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" newline bitfld.long 0x0 0. "DOM_PRI_EN,Domain privileged permission control enable" "0,1" repeat.end repeat 16. (list 0x20 0x21 0x22 0x23 0x24 0x25 0x26 0x27 0x28 0x29 0x2A 0x2B 0x2C 0x2D 0x2E 0x2F )(list 0x680 0x6B4 0x6E8 0x71C 0x750 0x784 0x7B8 0x7EC 0x820 0x854 0x888 0x8BC 0x8F0 0x924 0x958 0x98C ) group.long ($2+0x242C)++0x3 line.long 0x0 "DOM_PRI_PER_$1,This register is only used for domain master to control secure access permission. When the domain master write this register. it only changes the secure permission for itself. When the domain master read this register. it gets permission.." bitfld.long 0x0 7. "DOM_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" newline bitfld.long 0x0 0. "DOM_PRI_EN,Domain privileged permission control enable" "0,1" repeat.end repeat 16. (list 0x30 0x31 0x32 0x33 0x34 0x35 0x36 0x37 0x38 0x39 0x3A 0x3B 0x3C 0x3D 0x3E 0x3F )(list 0x9C0 0x9F4 0xA28 0xA5C 0xA90 0xAC4 0xAF8 0xB2C 0xB60 0xB94 0xBC8 0xBFC 0xC30 0xC64 0xC98 0xCCC ) group.long ($2+0x242C)++0x3 line.long 0x0 "DOM_PRI_PER_$1,This register is only used for domain master to control secure access permission. When the domain master write this register. it only changes the secure permission for itself. When the domain master read this register. it gets permission.." bitfld.long 0x0 7. "DOM_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" newline bitfld.long 0x0 0. "DOM_PRI_EN,Domain privileged permission control enable" "0,1" repeat.end repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x34 0x68 0x9C 0xD0 0x104 0x138 0x16C 0x1A0 0x1D4 0x208 0x23C 0x270 0x2A4 0x2D8 0x30C ) group.long ($2+0x2430)++0x3 line.long 0x0 "DOM_ASSIGN_$1,Use to assign domain for accessing DOM_SEC_PER and DOM_PRI_PER register. Only resource manager. group manager and domain owner can access this register. For write. group manager must write its owen domain ID. otherwise write accessing will.." hexmask.long.byte 0x0 0.--3. 1. "DID,accessing DOM_SEC_PER and DOM_PRI_PER register" repeat.end repeat 16. (list 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1A 0x1B 0x1C 0x1D 0x1E 0x1F )(list 0x340 0x374 0x3A8 0x3DC 0x410 0x444 0x478 0x4AC 0x4E0 0x514 0x548 0x57C 0x5B0 0x5E4 0x618 0x64C ) group.long ($2+0x2430)++0x3 line.long 0x0 "DOM_ASSIGN_$1,Use to assign domain for accessing DOM_SEC_PER and DOM_PRI_PER register. Only resource manager. group manager and domain owner can access this register. For write. group manager must write its owen domain ID. otherwise write accessing will.." hexmask.long.byte 0x0 0.--3. 1. "DID,accessing DOM_SEC_PER and DOM_PRI_PER register" repeat.end repeat 16. (list 0x20 0x21 0x22 0x23 0x24 0x25 0x26 0x27 0x28 0x29 0x2A 0x2B 0x2C 0x2D 0x2E 0x2F )(list 0x680 0x6B4 0x6E8 0x71C 0x750 0x784 0x7B8 0x7EC 0x820 0x854 0x888 0x8BC 0x8F0 0x924 0x958 0x98C ) group.long ($2+0x2430)++0x3 line.long 0x0 "DOM_ASSIGN_$1,Use to assign domain for accessing DOM_SEC_PER and DOM_PRI_PER register. Only resource manager. group manager and domain owner can access this register. For write. group manager must write its owen domain ID. otherwise write accessing will.." hexmask.long.byte 0x0 0.--3. 1. "DID,accessing DOM_SEC_PER and DOM_PRI_PER register" repeat.end repeat 16. (list 0x30 0x31 0x32 0x33 0x34 0x35 0x36 0x37 0x38 0x39 0x3A 0x3B 0x3C 0x3D 0x3E 0x3F )(list 0x9C0 0x9F4 0xA28 0xA5C 0xA90 0xAC4 0xAF8 0xB2C 0xB60 0xB94 0xBC8 0xBFC 0xC30 0xC64 0xC98 0xCCC ) group.long ($2+0x2430)++0x3 line.long 0x0 "DOM_ASSIGN_$1,Use to assign domain for accessing DOM_SEC_PER and DOM_PRI_PER register. Only resource manager. group manager and domain owner can access this register. For write. group manager must write its owen domain ID. otherwise write accessing will.." hexmask.long.byte 0x0 0.--3. 1. "DID,accessing DOM_SEC_PER and DOM_PRI_PER register" repeat.end repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x38 0x70 0xA8 0xE0 0x118 0x150 0x188 0x1C0 0x1F8 0x230 0x268 0x2A0 0x2D8 0x310 0x348 ) group.long ($2+0x3100)++0x3 line.long 0x0 "RGN_DOM_$1,Assign domain for peripheral. It can be only configured by resource and group manager" bitfld.long 0x0 31. "LOCK,When this bit is set lock write for all the bits in the register." "0,1" bitfld.long 0x0 4. "SET,Set together with DID would change permission of this resource to following setting: 1) Domain access control enabled. 2) Read/Write allowed for the domain owner. 3) Read/Write not allowed for all the other domains. If this bit is not set only DID.." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Assign domain for peripheral" repeat.end repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x38 0x70 0xA8 0xE0 0x118 0x150 0x188 0x1C0 0x1F8 0x230 0x268 0x2A0 0x2D8 0x310 0x348 ) group.long ($2+0x3104)++0x3 line.long 0x0 "RGN_DOM_PER0_$1,Domain Permission Control. It can be only configured by resource manager and domain owner." bitfld.long 0x0 31. "DOM7_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 29.--30. "DOM7_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 28. "DOM7_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 27. "DOM6_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 25.--26. "DOM6_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" newline bitfld.long 0x0 24. "DOM6_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 23. "DOM5_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 21.--22. "DOM5_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 20. "DOM5_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 19. "DOM4_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" newline bitfld.long 0x0 17.--18. "DOM4_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM4_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 15. "DOM3_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 13.--14. "DOM3_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 12. "DOM3_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" newline bitfld.long 0x0 11. "DOM2_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 9.--10. "DOM2_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM2_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 7. "DOM1_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 5.--6. "DOM1_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" newline bitfld.long 0x0 4. "DOM1_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 3. "DOM0_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 1.--2. "DOM0_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM0_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" repeat.end repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x38 0x70 0xA8 0xE0 0x118 0x150 0x188 0x1C0 0x1F8 0x230 0x268 0x2A0 0x2D8 0x310 0x348 ) group.long ($2+0x3108)++0x3 line.long 0x0 "RGN_DOM_PER1_$1,Domain Permission Control. It can be only configured by resource manager and domain owner." bitfld.long 0x0 31. "DOM15_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 29.--30. "DOM15_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 28. "DOM15_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 27. "DOM14_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 25.--26. "DOM14_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" newline bitfld.long 0x0 24. "DOM14_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 23. "DOM13_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 21.--22. "DOM13_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 20. "DOM13_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 19. "DOM12_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" newline bitfld.long 0x0 17.--18. "DOM12_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM12_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 15. "DOM11_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 13.--14. "DOM11_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 12. "DOM11_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" newline bitfld.long 0x0 11. "DOM10_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 9.--10. "DOM10_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM10_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 7. "DOM9_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 5.--6. "DOM9_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" newline bitfld.long 0x0 4. "DOM9_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 3. "DOM8_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 1.--2. "DOM8_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM8_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" repeat.end repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x38 0x70 0xA8 0xE0 0x118 0x150 0x188 0x1C0 0x1F8 0x230 0x268 0x2A0 0x2D8 0x310 0x348 ) group.long ($2+0x310C)++0x3 line.long 0x0 "RGN_SEC_PER0_$1,This register is only used for resource manager to control secure access permission." bitfld.long 0x0 31. "DOM3_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM3_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM3_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM3_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM2_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM2_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM2_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM2_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM1_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM1_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM1_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM1_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM0_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM0_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM0_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM0_SEC_EN,Domain secure permission control enable" "0,1" repeat.end repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x38 0x70 0xA8 0xE0 0x118 0x150 0x188 0x1C0 0x1F8 0x230 0x268 0x2A0 0x2D8 0x310 0x348 ) group.long ($2+0x3110)++0x3 line.long 0x0 "RGN_SEC_PER1_$1,This register is only used for resource manager to control secure access permission." bitfld.long 0x0 31. "DOM7_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM7_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM7_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM7_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM6_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM6_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM6_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM6_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM5_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM5_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM5_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM5_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM4_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM4_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM4_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM4_SEC_EN,Domain secure permission control enable" "0,1" repeat.end repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x38 0x70 0xA8 0xE0 0x118 0x150 0x188 0x1C0 0x1F8 0x230 0x268 0x2A0 0x2D8 0x310 0x348 ) group.long ($2+0x3114)++0x3 line.long 0x0 "RGN_SEC_PER2_$1,This register is only used for resource manager to control secure access permission." bitfld.long 0x0 31. "DOM11_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM11_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM11_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM11_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM10_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM10_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM10_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM10_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM9_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM9_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM9_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM9_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM8_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM8_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM8_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM8_SEC_EN,Domain secure permission control enable" "0,1" repeat.end repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x38 0x70 0xA8 0xE0 0x118 0x150 0x188 0x1C0 0x1F8 0x230 0x268 0x2A0 0x2D8 0x310 0x348 ) group.long ($2+0x3118)++0x3 line.long 0x0 "RGN_SEC_PER3_$1,This register is only used for resource manager to control secure access permission." bitfld.long 0x0 31. "DOM15_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM15_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM15_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM15_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM14_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM14_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM14_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM14_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM13_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM13_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM13_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM13_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM12_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM12_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM12_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM12_SEC_EN,Domain secure permission control enable" "0,1" repeat.end repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x38 0x70 0xA8 0xE0 0x118 0x150 0x188 0x1C0 0x1F8 0x230 0x268 0x2A0 0x2D8 0x310 0x348 ) group.long ($2+0x311C)++0x3 line.long 0x0 "RGN_PRI_PER0_$1,This register is only used for resource manager to control privileged access permission." bitfld.long 0x0 31. "DOM3_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM3_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM3_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM3_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM2_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM2_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM2_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM2_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM1_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM1_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM1_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM1_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM0_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM0_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM0_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM0_PRI_EN,Domain privileged permission control enable" "0,1" repeat.end repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x38 0x70 0xA8 0xE0 0x118 0x150 0x188 0x1C0 0x1F8 0x230 0x268 0x2A0 0x2D8 0x310 0x348 ) group.long ($2+0x3120)++0x3 line.long 0x0 "RGN_PRI_PER1_$1,This register is only used for resource manager to control privileged access permission." bitfld.long 0x0 31. "DOM7_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM7_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM7_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM7_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM6_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM6_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM6_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM6_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM5_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM5_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM5_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM5_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM4_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM4_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM4_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM4_PRI_EN,Domain privileged permission control enable" "0,1" repeat.end repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x38 0x70 0xA8 0xE0 0x118 0x150 0x188 0x1C0 0x1F8 0x230 0x268 0x2A0 0x2D8 0x310 0x348 ) group.long ($2+0x3124)++0x3 line.long 0x0 "RGN_PRI_PER2_$1,This register is only used for resource manager to control privileged access permission." bitfld.long 0x0 31. "DOM11_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM11_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM11_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM11_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM10_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM10_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM10_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM10_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM9_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM9_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM9_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM9_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM8_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM8_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM8_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM8_PRI_EN,Domain privileged permission control enable" "0,1" repeat.end repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x38 0x70 0xA8 0xE0 0x118 0x150 0x188 0x1C0 0x1F8 0x230 0x268 0x2A0 0x2D8 0x310 0x348 ) group.long ($2+0x3128)++0x3 line.long 0x0 "RGN_PRI_PER3_$1,This register is only used for resource manager to control privileged access permission." bitfld.long 0x0 31. "DOM15_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM15_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM15_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM15_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM14_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM14_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM14_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM14_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM13_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM13_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM13_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM13_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM12_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM12_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM12_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM12_PRI_EN,Domain privileged permission control enable" "0,1" repeat.end repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x38 0x70 0xA8 0xE0 0x118 0x150 0x188 0x1C0 0x1F8 0x230 0x268 0x2A0 0x2D8 0x310 0x348 ) group.long ($2+0x312C)++0x3 line.long 0x0 "RGN_DOM_SEC_PER_$1,This register is only used for domain master to control secure access permission. When the domain master write this register. it only changes the secure permission for itself. When the domain master read this register. it gets.." bitfld.long 0x0 7. "DOM_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" newline bitfld.long 0x0 0. "DOM_SEC_EN,Domain secure permission control enable" "0,1" repeat.end repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x38 0x70 0xA8 0xE0 0x118 0x150 0x188 0x1C0 0x1F8 0x230 0x268 0x2A0 0x2D8 0x310 0x348 ) group.long ($2+0x3130)++0x3 line.long 0x0 "RGN_DOM_PRI_PER_$1,This register is only used for domain master to control secure access permission. When the domain master write this register. it only changes the secure permission for itself. When the domain master read this register. it gets.." bitfld.long 0x0 7. "DOM_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" newline bitfld.long 0x0 0. "DOM_PRI_EN,Domain privileged permission control enable" "0,1" repeat.end repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x38 0x70 0xA8 0xE0 0x118 0x150 0x188 0x1C0 0x1F8 0x230 0x268 0x2A0 0x2D8 0x310 0x348 ) group.long ($2+0x3134)++0x3 line.long 0x0 "RGN_DOM_ASSIGN_$1,Use to assign domain for accessing DOM_SEC_PER and DOM_PRI_PER register. Only resource manager. group manager and domain owner can access this register. For write. group manager must write its owen domain ID. otherwise write accessing.." hexmask.long.byte 0x0 0.--3. 1. "DID,accessing DOM_SEC_PER and DOM_PRI_PER register" repeat.end tree.end tree "RPC_AP_RSTGEN" base ad:0x38C00000 repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x4 0x8 0xC 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C ) group.long ($2)++0x3 line.long 0x0 "REGG0_DOM_$1,Assign domain for CKGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1A 0x1B 0x1C 0x1D 0x1E 0x1F )(list 0x40 0x44 0x48 0x4C 0x50 0x54 0x58 0x5C 0x60 0x64 0x68 0x6C 0x70 0x74 0x78 0x7C ) group.long ($2)++0x3 line.long 0x0 "REGG0_DOM_$1,Assign domain for CKGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x20 0x21 0x22 0x23 0x24 0x25 0x26 0x27 0x28 0x29 0x2A 0x2B 0x2C 0x2D 0x2E 0x2F )(list 0x80 0x84 0x88 0x8C 0x90 0x94 0x98 0x9C 0xA0 0xA4 0xA8 0xAC 0xB0 0xB4 0xB8 0xBC ) group.long ($2)++0x3 line.long 0x0 "REGG0_DOM_$1,Assign domain for CKGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x30 0x31 0x32 0x33 0x34 0x35 0x36 0x37 0x38 0x39 0x3A 0x3B 0x3C 0x3D 0x3E 0x3F )(list 0xC0 0xC4 0xC8 0xCC 0xD0 0xD4 0xD8 0xDC 0xE0 0xE4 0xE8 0xEC 0xF0 0xF4 0xF8 0xFC ) group.long ($2)++0x3 line.long 0x0 "REGG0_DOM_$1,Assign domain for CKGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x40 0x41 0x42 0x43 0x44 0x45 0x46 0x47 0x48 0x49 0x4A 0x4B 0x4C 0x4D 0x4E 0x4F )(list 0x100 0x104 0x108 0x10C 0x110 0x114 0x118 0x11C 0x120 0x124 0x128 0x12C 0x130 0x134 0x138 0x13C ) group.long ($2)++0x3 line.long 0x0 "REGG0_DOM_$1,Assign domain for CKGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x50 0x51 0x52 0x53 0x54 0x55 0x56 0x57 0x58 0x59 0x5A 0x5B 0x5C 0x5D 0x5E 0x5F )(list 0x140 0x144 0x148 0x14C 0x150 0x154 0x158 0x15C 0x160 0x164 0x168 0x16C 0x170 0x174 0x178 0x17C ) group.long ($2)++0x3 line.long 0x0 "REGG0_DOM_$1,Assign domain for CKGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x60 0x61 0x62 0x63 0x64 0x65 0x66 0x67 0x68 0x69 0x6A 0x6B 0x6C 0x6D 0x6E 0x6F )(list 0x180 0x184 0x188 0x18C 0x190 0x194 0x198 0x19C 0x1A0 0x1A4 0x1A8 0x1AC 0x1B0 0x1B4 0x1B8 0x1BC ) group.long ($2)++0x3 line.long 0x0 "REGG0_DOM_$1,Assign domain for CKGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x70 0x71 0x72 0x73 0x74 0x75 0x76 0x77 0x78 0x79 0x7A 0x7B 0x7C 0x7D 0x7E 0x7F )(list 0x1C0 0x1C4 0x1C8 0x1CC 0x1D0 0x1D4 0x1D8 0x1DC 0x1E0 0x1E4 0x1E8 0x1EC 0x1F0 0x1F4 0x1F8 0x1FC ) group.long ($2)++0x3 line.long 0x0 "REGG0_DOM_$1,Assign domain for CKGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x80 0x81 0x82 0x83 0x84 0x85 0x86 0x87 0x88 0x89 0x8A 0x8B 0x8C 0x8D 0x8E 0x8F )(list 0x200 0x204 0x208 0x20C 0x210 0x214 0x218 0x21C 0x220 0x224 0x228 0x22C 0x230 0x234 0x238 0x23C ) group.long ($2)++0x3 line.long 0x0 "REGG0_DOM_$1,Assign domain for CKGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x90 0x91 0x92 0x93 0x94 0x95 0x96 0x97 0x98 0x99 0x9A 0x9B 0x9C 0x9D 0x9E 0x9F )(list 0x240 0x244 0x248 0x24C 0x250 0x254 0x258 0x25C 0x260 0x264 0x268 0x26C 0x270 0x274 0x278 0x27C ) group.long ($2)++0x3 line.long 0x0 "REGG0_DOM_$1,Assign domain for CKGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xA0 0xA1 0xA2 0xA3 0xA4 0xA5 0xA6 0xA7 0xA8 0xA9 0xAA 0xAB 0xAC 0xAD 0xAE 0xAF )(list 0x280 0x284 0x288 0x28C 0x290 0x294 0x298 0x29C 0x2A0 0x2A4 0x2A8 0x2AC 0x2B0 0x2B4 0x2B8 0x2BC ) group.long ($2)++0x3 line.long 0x0 "REGG0_DOM_$1,Assign domain for CKGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xB0 0xB1 0xB2 0xB3 0xB4 0xB5 0xB6 0xB7 0xB8 0xB9 0xBA 0xBB 0xBC 0xBD 0xBE 0xBF )(list 0x2C0 0x2C4 0x2C8 0x2CC 0x2D0 0x2D4 0x2D8 0x2DC 0x2E0 0x2E4 0x2E8 0x2EC 0x2F0 0x2F4 0x2F8 0x2FC ) group.long ($2)++0x3 line.long 0x0 "REGG0_DOM_$1,Assign domain for CKGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xC0 0xC1 0xC2 0xC3 0xC4 0xC5 0xC6 0xC7 0xC8 0xC9 0xCA 0xCB 0xCC 0xCD 0xCE 0xCF )(list 0x300 0x304 0x308 0x30C 0x310 0x314 0x318 0x31C 0x320 0x324 0x328 0x32C 0x330 0x334 0x338 0x33C ) group.long ($2)++0x3 line.long 0x0 "REGG0_DOM_$1,Assign domain for CKGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xD0 0xD1 0xD2 0xD3 0xD4 0xD5 0xD6 0xD7 0xD8 0xD9 0xDA 0xDB 0xDC 0xDD 0xDE 0xDF )(list 0x340 0x344 0x348 0x34C 0x350 0x354 0x358 0x35C 0x360 0x364 0x368 0x36C 0x370 0x374 0x378 0x37C ) group.long ($2)++0x3 line.long 0x0 "REGG0_DOM_$1,Assign domain for CKGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xE0 0xE1 0xE2 0xE3 0xE4 0xE5 0xE6 0xE7 0xE8 0xE9 0xEA 0xEB 0xEC 0xED 0xEE 0xEF )(list 0x380 0x384 0x388 0x38C 0x390 0x394 0x398 0x39C 0x3A0 0x3A4 0x3A8 0x3AC 0x3B0 0x3B4 0x3B8 0x3BC ) group.long ($2)++0x3 line.long 0x0 "REGG0_DOM_$1,Assign domain for CKGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xF0 0xF1 0xF2 0xF3 0xF4 0xF5 0xF6 0xF7 0xF8 0xF9 0xFA 0xFB 0xFC 0xFD 0xFE 0xFF )(list 0x3C0 0x3C4 0x3C8 0x3CC 0x3D0 0x3D4 0x3D8 0x3DC 0x3E0 0x3E4 0x3E8 0x3EC 0x3F0 0x3F4 0x3F8 0x3FC ) group.long ($2)++0x3 line.long 0x0 "REGG0_DOM_$1,Assign domain for CKGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x4 0x8 0xC 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C ) group.long ($2+0x400)++0x3 line.long 0x0 "REGG1_DOM_$1,Assign domain for CKGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1A 0x1B 0x1C 0x1D 0x1E 0x1F )(list 0x40 0x44 0x48 0x4C 0x50 0x54 0x58 0x5C 0x60 0x64 0x68 0x6C 0x70 0x74 0x78 0x7C ) group.long ($2+0x400)++0x3 line.long 0x0 "REGG1_DOM_$1,Assign domain for CKGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x20 0x21 0x22 0x23 0x24 0x25 0x26 0x27 0x28 0x29 0x2A 0x2B 0x2C 0x2D 0x2E 0x2F )(list 0x80 0x84 0x88 0x8C 0x90 0x94 0x98 0x9C 0xA0 0xA4 0xA8 0xAC 0xB0 0xB4 0xB8 0xBC ) group.long ($2+0x400)++0x3 line.long 0x0 "REGG1_DOM_$1,Assign domain for CKGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x30 0x31 0x32 0x33 0x34 0x35 0x36 0x37 0x38 0x39 0x3A 0x3B 0x3C 0x3D 0x3E 0x3F )(list 0xC0 0xC4 0xC8 0xCC 0xD0 0xD4 0xD8 0xDC 0xE0 0xE4 0xE8 0xEC 0xF0 0xF4 0xF8 0xFC ) group.long ($2+0x400)++0x3 line.long 0x0 "REGG1_DOM_$1,Assign domain for CKGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x40 0x41 0x42 0x43 0x44 0x45 0x46 0x47 0x48 0x49 0x4A 0x4B 0x4C 0x4D 0x4E 0x4F )(list 0x100 0x104 0x108 0x10C 0x110 0x114 0x118 0x11C 0x120 0x124 0x128 0x12C 0x130 0x134 0x138 0x13C ) group.long ($2+0x400)++0x3 line.long 0x0 "REGG1_DOM_$1,Assign domain for CKGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x50 0x51 0x52 0x53 0x54 0x55 0x56 0x57 0x58 0x59 0x5A 0x5B 0x5C 0x5D 0x5E 0x5F )(list 0x140 0x144 0x148 0x14C 0x150 0x154 0x158 0x15C 0x160 0x164 0x168 0x16C 0x170 0x174 0x178 0x17C ) group.long ($2+0x400)++0x3 line.long 0x0 "REGG1_DOM_$1,Assign domain for CKGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x60 0x61 0x62 0x63 0x64 0x65 0x66 0x67 0x68 0x69 0x6A 0x6B 0x6C 0x6D 0x6E 0x6F )(list 0x180 0x184 0x188 0x18C 0x190 0x194 0x198 0x19C 0x1A0 0x1A4 0x1A8 0x1AC 0x1B0 0x1B4 0x1B8 0x1BC ) group.long ($2+0x400)++0x3 line.long 0x0 "REGG1_DOM_$1,Assign domain for CKGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x70 0x71 0x72 0x73 0x74 0x75 0x76 0x77 0x78 0x79 0x7A 0x7B 0x7C 0x7D 0x7E 0x7F )(list 0x1C0 0x1C4 0x1C8 0x1CC 0x1D0 0x1D4 0x1D8 0x1DC 0x1E0 0x1E4 0x1E8 0x1EC 0x1F0 0x1F4 0x1F8 0x1FC ) group.long ($2+0x400)++0x3 line.long 0x0 "REGG1_DOM_$1,Assign domain for CKGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x80 0x81 0x82 0x83 0x84 0x85 0x86 0x87 0x88 0x89 0x8A 0x8B 0x8C 0x8D 0x8E 0x8F )(list 0x200 0x204 0x208 0x20C 0x210 0x214 0x218 0x21C 0x220 0x224 0x228 0x22C 0x230 0x234 0x238 0x23C ) group.long ($2+0x400)++0x3 line.long 0x0 "REGG1_DOM_$1,Assign domain for CKGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x90 0x91 0x92 0x93 0x94 0x95 0x96 0x97 0x98 0x99 0x9A 0x9B 0x9C 0x9D 0x9E 0x9F )(list 0x240 0x244 0x248 0x24C 0x250 0x254 0x258 0x25C 0x260 0x264 0x268 0x26C 0x270 0x274 0x278 0x27C ) group.long ($2+0x400)++0x3 line.long 0x0 "REGG1_DOM_$1,Assign domain for CKGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xA0 0xA1 0xA2 0xA3 0xA4 0xA5 0xA6 0xA7 0xA8 0xA9 0xAA 0xAB 0xAC 0xAD 0xAE 0xAF )(list 0x280 0x284 0x288 0x28C 0x290 0x294 0x298 0x29C 0x2A0 0x2A4 0x2A8 0x2AC 0x2B0 0x2B4 0x2B8 0x2BC ) group.long ($2+0x400)++0x3 line.long 0x0 "REGG1_DOM_$1,Assign domain for CKGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xB0 0xB1 0xB2 0xB3 0xB4 0xB5 0xB6 0xB7 0xB8 0xB9 0xBA 0xBB 0xBC 0xBD 0xBE 0xBF )(list 0x2C0 0x2C4 0x2C8 0x2CC 0x2D0 0x2D4 0x2D8 0x2DC 0x2E0 0x2E4 0x2E8 0x2EC 0x2F0 0x2F4 0x2F8 0x2FC ) group.long ($2+0x400)++0x3 line.long 0x0 "REGG1_DOM_$1,Assign domain for CKGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xC0 0xC1 0xC2 0xC3 0xC4 0xC5 0xC6 0xC7 0xC8 0xC9 0xCA 0xCB 0xCC 0xCD 0xCE 0xCF )(list 0x300 0x304 0x308 0x30C 0x310 0x314 0x318 0x31C 0x320 0x324 0x328 0x32C 0x330 0x334 0x338 0x33C ) group.long ($2+0x400)++0x3 line.long 0x0 "REGG1_DOM_$1,Assign domain for CKGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xD0 0xD1 0xD2 0xD3 0xD4 0xD5 0xD6 0xD7 0xD8 0xD9 0xDA 0xDB 0xDC 0xDD 0xDE 0xDF )(list 0x340 0x344 0x348 0x34C 0x350 0x354 0x358 0x35C 0x360 0x364 0x368 0x36C 0x370 0x374 0x378 0x37C ) group.long ($2+0x400)++0x3 line.long 0x0 "REGG1_DOM_$1,Assign domain for CKGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xE0 0xE1 0xE2 0xE3 0xE4 0xE5 0xE6 0xE7 0xE8 0xE9 0xEA 0xEB 0xEC 0xED 0xEE 0xEF )(list 0x380 0x384 0x388 0x38C 0x390 0x394 0x398 0x39C 0x3A0 0x3A4 0x3A8 0x3AC 0x3B0 0x3B4 0x3B8 0x3BC ) group.long ($2+0x400)++0x3 line.long 0x0 "REGG1_DOM_$1,Assign domain for CKGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xF0 0xF1 0xF2 0xF3 0xF4 0xF5 0xF6 0xF7 0xF8 0xF9 0xFA 0xFB 0xFC 0xFD 0xFE 0xFF )(list 0x3C0 0x3C4 0x3C8 0x3CC 0x3D0 0x3D4 0x3D8 0x3DC 0x3E0 0x3E4 0x3E8 0x3EC 0x3F0 0x3F4 0x3F8 0x3FC ) group.long ($2+0x400)++0x3 line.long 0x0 "REGG1_DOM_$1,Assign domain for CKGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x4 0x8 0xC 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C ) group.long ($2+0x800)++0x3 line.long 0x0 "REGG2_DOM_$1,Assign domain for SCR registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1A 0x1B 0x1C 0x1D 0x1E 0x1F )(list 0x40 0x44 0x48 0x4C 0x50 0x54 0x58 0x5C 0x60 0x64 0x68 0x6C 0x70 0x74 0x78 0x7C ) group.long ($2+0x800)++0x3 line.long 0x0 "REGG2_DOM_$1,Assign domain for SCR registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x20 0x21 0x22 0x23 0x24 0x25 0x26 0x27 0x28 0x29 0x2A 0x2B 0x2C 0x2D 0x2E 0x2F )(list 0x80 0x84 0x88 0x8C 0x90 0x94 0x98 0x9C 0xA0 0xA4 0xA8 0xAC 0xB0 0xB4 0xB8 0xBC ) group.long ($2+0x800)++0x3 line.long 0x0 "REGG2_DOM_$1,Assign domain for SCR registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x30 0x31 0x32 0x33 0x34 0x35 0x36 0x37 0x38 0x39 0x3A 0x3B 0x3C 0x3D 0x3E 0x3F )(list 0xC0 0xC4 0xC8 0xCC 0xD0 0xD4 0xD8 0xDC 0xE0 0xE4 0xE8 0xEC 0xF0 0xF4 0xF8 0xFC ) group.long ($2+0x800)++0x3 line.long 0x0 "REGG2_DOM_$1,Assign domain for SCR registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x40 0x41 0x42 0x43 0x44 0x45 0x46 0x47 0x48 0x49 0x4A 0x4B 0x4C 0x4D 0x4E 0x4F )(list 0x100 0x104 0x108 0x10C 0x110 0x114 0x118 0x11C 0x120 0x124 0x128 0x12C 0x130 0x134 0x138 0x13C ) group.long ($2+0x800)++0x3 line.long 0x0 "REGG2_DOM_$1,Assign domain for SCR registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x50 0x51 0x52 0x53 0x54 0x55 0x56 0x57 0x58 0x59 0x5A 0x5B 0x5C 0x5D 0x5E 0x5F )(list 0x140 0x144 0x148 0x14C 0x150 0x154 0x158 0x15C 0x160 0x164 0x168 0x16C 0x170 0x174 0x178 0x17C ) group.long ($2+0x800)++0x3 line.long 0x0 "REGG2_DOM_$1,Assign domain for SCR registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x60 0x61 0x62 0x63 0x64 0x65 0x66 0x67 0x68 0x69 0x6A 0x6B 0x6C 0x6D 0x6E 0x6F )(list 0x180 0x184 0x188 0x18C 0x190 0x194 0x198 0x19C 0x1A0 0x1A4 0x1A8 0x1AC 0x1B0 0x1B4 0x1B8 0x1BC ) group.long ($2+0x800)++0x3 line.long 0x0 "REGG2_DOM_$1,Assign domain for SCR registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x70 0x71 0x72 0x73 0x74 0x75 0x76 0x77 0x78 0x79 0x7A 0x7B 0x7C 0x7D 0x7E 0x7F )(list 0x1C0 0x1C4 0x1C8 0x1CC 0x1D0 0x1D4 0x1D8 0x1DC 0x1E0 0x1E4 0x1E8 0x1EC 0x1F0 0x1F4 0x1F8 0x1FC ) group.long ($2+0x800)++0x3 line.long 0x0 "REGG2_DOM_$1,Assign domain for SCR registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x80 0x81 0x82 0x83 0x84 0x85 0x86 0x87 0x88 0x89 0x8A 0x8B 0x8C 0x8D 0x8E 0x8F )(list 0x200 0x204 0x208 0x20C 0x210 0x214 0x218 0x21C 0x220 0x224 0x228 0x22C 0x230 0x234 0x238 0x23C ) group.long ($2+0x800)++0x3 line.long 0x0 "REGG2_DOM_$1,Assign domain for SCR registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x90 0x91 0x92 0x93 0x94 0x95 0x96 0x97 0x98 0x99 0x9A 0x9B 0x9C 0x9D 0x9E 0x9F )(list 0x240 0x244 0x248 0x24C 0x250 0x254 0x258 0x25C 0x260 0x264 0x268 0x26C 0x270 0x274 0x278 0x27C ) group.long ($2+0x800)++0x3 line.long 0x0 "REGG2_DOM_$1,Assign domain for SCR registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xA0 0xA1 0xA2 0xA3 0xA4 0xA5 0xA6 0xA7 0xA8 0xA9 0xAA 0xAB 0xAC 0xAD 0xAE 0xAF )(list 0x280 0x284 0x288 0x28C 0x290 0x294 0x298 0x29C 0x2A0 0x2A4 0x2A8 0x2AC 0x2B0 0x2B4 0x2B8 0x2BC ) group.long ($2+0x800)++0x3 line.long 0x0 "REGG2_DOM_$1,Assign domain for SCR registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xB0 0xB1 0xB2 0xB3 0xB4 0xB5 0xB6 0xB7 0xB8 0xB9 0xBA 0xBB 0xBC 0xBD 0xBE 0xBF )(list 0x2C0 0x2C4 0x2C8 0x2CC 0x2D0 0x2D4 0x2D8 0x2DC 0x2E0 0x2E4 0x2E8 0x2EC 0x2F0 0x2F4 0x2F8 0x2FC ) group.long ($2+0x800)++0x3 line.long 0x0 "REGG2_DOM_$1,Assign domain for SCR registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xC0 0xC1 0xC2 0xC3 0xC4 0xC5 0xC6 0xC7 0xC8 0xC9 0xCA 0xCB 0xCC 0xCD 0xCE 0xCF )(list 0x300 0x304 0x308 0x30C 0x310 0x314 0x318 0x31C 0x320 0x324 0x328 0x32C 0x330 0x334 0x338 0x33C ) group.long ($2+0x800)++0x3 line.long 0x0 "REGG2_DOM_$1,Assign domain for SCR registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xD0 0xD1 0xD2 0xD3 0xD4 0xD5 0xD6 0xD7 0xD8 0xD9 0xDA 0xDB 0xDC 0xDD 0xDE 0xDF )(list 0x340 0x344 0x348 0x34C 0x350 0x354 0x358 0x35C 0x360 0x364 0x368 0x36C 0x370 0x374 0x378 0x37C ) group.long ($2+0x800)++0x3 line.long 0x0 "REGG2_DOM_$1,Assign domain for SCR registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xE0 0xE1 0xE2 0xE3 0xE4 0xE5 0xE6 0xE7 0xE8 0xE9 0xEA 0xEB 0xEC 0xED 0xEE 0xEF )(list 0x380 0x384 0x388 0x38C 0x390 0x394 0x398 0x39C 0x3A0 0x3A4 0x3A8 0x3AC 0x3B0 0x3B4 0x3B8 0x3BC ) group.long ($2+0x800)++0x3 line.long 0x0 "REGG2_DOM_$1,Assign domain for SCR registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xF0 0xF1 0xF2 0xF3 0xF4 0xF5 0xF6 0xF7 0xF8 0xF9 0xFA 0xFB 0xFC 0xFD 0xFE 0xFF )(list 0x3C0 0x3C4 0x3C8 0x3CC 0x3D0 0x3D4 0x3D8 0x3DC 0x3E0 0x3E4 0x3E8 0x3EC 0x3F0 0x3F4 0x3F8 0x3FC ) group.long ($2+0x800)++0x3 line.long 0x0 "REGG2_DOM_$1,Assign domain for SCR registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x4 0x8 0xC 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C ) group.long ($2+0xC00)++0x3 line.long 0x0 "REGG3_DOM_$1,Assign domain for SCR registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1A 0x1B 0x1C 0x1D 0x1E 0x1F )(list 0x40 0x44 0x48 0x4C 0x50 0x54 0x58 0x5C 0x60 0x64 0x68 0x6C 0x70 0x74 0x78 0x7C ) group.long ($2+0xC00)++0x3 line.long 0x0 "REGG3_DOM_$1,Assign domain for SCR registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x20 0x21 0x22 0x23 0x24 0x25 0x26 0x27 0x28 0x29 0x2A 0x2B 0x2C 0x2D 0x2E 0x2F )(list 0x80 0x84 0x88 0x8C 0x90 0x94 0x98 0x9C 0xA0 0xA4 0xA8 0xAC 0xB0 0xB4 0xB8 0xBC ) group.long ($2+0xC00)++0x3 line.long 0x0 "REGG3_DOM_$1,Assign domain for SCR registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x30 0x31 0x32 0x33 0x34 0x35 0x36 0x37 0x38 0x39 0x3A 0x3B 0x3C 0x3D 0x3E 0x3F )(list 0xC0 0xC4 0xC8 0xCC 0xD0 0xD4 0xD8 0xDC 0xE0 0xE4 0xE8 0xEC 0xF0 0xF4 0xF8 0xFC ) group.long ($2+0xC00)++0x3 line.long 0x0 "REGG3_DOM_$1,Assign domain for SCR registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x40 0x41 0x42 0x43 0x44 0x45 0x46 0x47 0x48 0x49 0x4A 0x4B 0x4C 0x4D 0x4E 0x4F )(list 0x100 0x104 0x108 0x10C 0x110 0x114 0x118 0x11C 0x120 0x124 0x128 0x12C 0x130 0x134 0x138 0x13C ) group.long ($2+0xC00)++0x3 line.long 0x0 "REGG3_DOM_$1,Assign domain for SCR registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x50 0x51 0x52 0x53 0x54 0x55 0x56 0x57 0x58 0x59 0x5A 0x5B 0x5C 0x5D 0x5E 0x5F )(list 0x140 0x144 0x148 0x14C 0x150 0x154 0x158 0x15C 0x160 0x164 0x168 0x16C 0x170 0x174 0x178 0x17C ) group.long ($2+0xC00)++0x3 line.long 0x0 "REGG3_DOM_$1,Assign domain for SCR registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x60 0x61 0x62 0x63 0x64 0x65 0x66 0x67 0x68 0x69 0x6A 0x6B 0x6C 0x6D 0x6E 0x6F )(list 0x180 0x184 0x188 0x18C 0x190 0x194 0x198 0x19C 0x1A0 0x1A4 0x1A8 0x1AC 0x1B0 0x1B4 0x1B8 0x1BC ) group.long ($2+0xC00)++0x3 line.long 0x0 "REGG3_DOM_$1,Assign domain for SCR registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x70 0x71 0x72 0x73 0x74 0x75 0x76 0x77 0x78 0x79 0x7A 0x7B 0x7C 0x7D 0x7E 0x7F )(list 0x1C0 0x1C4 0x1C8 0x1CC 0x1D0 0x1D4 0x1D8 0x1DC 0x1E0 0x1E4 0x1E8 0x1EC 0x1F0 0x1F4 0x1F8 0x1FC ) group.long ($2+0xC00)++0x3 line.long 0x0 "REGG3_DOM_$1,Assign domain for SCR registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x80 0x81 0x82 0x83 0x84 0x85 0x86 0x87 0x88 0x89 0x8A 0x8B 0x8C 0x8D 0x8E 0x8F )(list 0x200 0x204 0x208 0x20C 0x210 0x214 0x218 0x21C 0x220 0x224 0x228 0x22C 0x230 0x234 0x238 0x23C ) group.long ($2+0xC00)++0x3 line.long 0x0 "REGG3_DOM_$1,Assign domain for SCR registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x90 0x91 0x92 0x93 0x94 0x95 0x96 0x97 0x98 0x99 0x9A 0x9B 0x9C 0x9D 0x9E 0x9F )(list 0x240 0x244 0x248 0x24C 0x250 0x254 0x258 0x25C 0x260 0x264 0x268 0x26C 0x270 0x274 0x278 0x27C ) group.long ($2+0xC00)++0x3 line.long 0x0 "REGG3_DOM_$1,Assign domain for SCR registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xA0 0xA1 0xA2 0xA3 0xA4 0xA5 0xA6 0xA7 0xA8 0xA9 0xAA 0xAB 0xAC 0xAD 0xAE 0xAF )(list 0x280 0x284 0x288 0x28C 0x290 0x294 0x298 0x29C 0x2A0 0x2A4 0x2A8 0x2AC 0x2B0 0x2B4 0x2B8 0x2BC ) group.long ($2+0xC00)++0x3 line.long 0x0 "REGG3_DOM_$1,Assign domain for SCR registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xB0 0xB1 0xB2 0xB3 0xB4 0xB5 0xB6 0xB7 0xB8 0xB9 0xBA 0xBB 0xBC 0xBD 0xBE 0xBF )(list 0x2C0 0x2C4 0x2C8 0x2CC 0x2D0 0x2D4 0x2D8 0x2DC 0x2E0 0x2E4 0x2E8 0x2EC 0x2F0 0x2F4 0x2F8 0x2FC ) group.long ($2+0xC00)++0x3 line.long 0x0 "REGG3_DOM_$1,Assign domain for SCR registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xC0 0xC1 0xC2 0xC3 0xC4 0xC5 0xC6 0xC7 0xC8 0xC9 0xCA 0xCB 0xCC 0xCD 0xCE 0xCF )(list 0x300 0x304 0x308 0x30C 0x310 0x314 0x318 0x31C 0x320 0x324 0x328 0x32C 0x330 0x334 0x338 0x33C ) group.long ($2+0xC00)++0x3 line.long 0x0 "REGG3_DOM_$1,Assign domain for SCR registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xD0 0xD1 0xD2 0xD3 0xD4 0xD5 0xD6 0xD7 0xD8 0xD9 0xDA 0xDB 0xDC 0xDD 0xDE 0xDF )(list 0x340 0x344 0x348 0x34C 0x350 0x354 0x358 0x35C 0x360 0x364 0x368 0x36C 0x370 0x374 0x378 0x37C ) group.long ($2+0xC00)++0x3 line.long 0x0 "REGG3_DOM_$1,Assign domain for SCR registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xE0 0xE1 0xE2 0xE3 0xE4 0xE5 0xE6 0xE7 0xE8 0xE9 0xEA 0xEB 0xEC 0xED 0xEE 0xEF )(list 0x380 0x384 0x388 0x38C 0x390 0x394 0x398 0x39C 0x3A0 0x3A4 0x3A8 0x3AC 0x3B0 0x3B4 0x3B8 0x3BC ) group.long ($2+0xC00)++0x3 line.long 0x0 "REGG3_DOM_$1,Assign domain for SCR registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xF0 0xF1 0xF2 0xF3 0xF4 0xF5 0xF6 0xF7 0xF8 0xF9 0xFA 0xFB 0xFC 0xFD 0xFE 0xFF )(list 0x3C0 0x3C4 0x3C8 0x3CC 0x3D0 0x3D4 0x3D8 0x3DC 0x3E0 0x3E4 0x3E8 0x3EC 0x3F0 0x3F4 0x3F8 0x3FC ) group.long ($2+0xC00)++0x3 line.long 0x0 "REGG3_DOM_$1,Assign domain for SCR registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x4 0x8 0xC 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C ) group.long ($2+0x1000)++0x3 line.long 0x0 "REGG4_DOM_$1,Assign domain for RSTGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1A 0x1B 0x1C 0x1D 0x1E 0x1F )(list 0x40 0x44 0x48 0x4C 0x50 0x54 0x58 0x5C 0x60 0x64 0x68 0x6C 0x70 0x74 0x78 0x7C ) group.long ($2+0x1000)++0x3 line.long 0x0 "REGG4_DOM_$1,Assign domain for RSTGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x20 0x21 0x22 0x23 0x24 0x25 0x26 0x27 0x28 0x29 0x2A 0x2B 0x2C 0x2D 0x2E 0x2F )(list 0x80 0x84 0x88 0x8C 0x90 0x94 0x98 0x9C 0xA0 0xA4 0xA8 0xAC 0xB0 0xB4 0xB8 0xBC ) group.long ($2+0x1000)++0x3 line.long 0x0 "REGG4_DOM_$1,Assign domain for RSTGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x30 0x31 0x32 0x33 0x34 0x35 0x36 0x37 0x38 0x39 0x3A 0x3B 0x3C 0x3D 0x3E 0x3F )(list 0xC0 0xC4 0xC8 0xCC 0xD0 0xD4 0xD8 0xDC 0xE0 0xE4 0xE8 0xEC 0xF0 0xF4 0xF8 0xFC ) group.long ($2+0x1000)++0x3 line.long 0x0 "REGG4_DOM_$1,Assign domain for RSTGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x40 0x41 0x42 0x43 0x44 0x45 0x46 0x47 0x48 0x49 0x4A 0x4B 0x4C 0x4D 0x4E 0x4F )(list 0x100 0x104 0x108 0x10C 0x110 0x114 0x118 0x11C 0x120 0x124 0x128 0x12C 0x130 0x134 0x138 0x13C ) group.long ($2+0x1000)++0x3 line.long 0x0 "REGG4_DOM_$1,Assign domain for RSTGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x50 0x51 0x52 0x53 0x54 0x55 0x56 0x57 0x58 0x59 0x5A 0x5B 0x5C 0x5D 0x5E 0x5F )(list 0x140 0x144 0x148 0x14C 0x150 0x154 0x158 0x15C 0x160 0x164 0x168 0x16C 0x170 0x174 0x178 0x17C ) group.long ($2+0x1000)++0x3 line.long 0x0 "REGG4_DOM_$1,Assign domain for RSTGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x60 0x61 0x62 0x63 0x64 0x65 0x66 0x67 0x68 0x69 0x6A 0x6B 0x6C 0x6D 0x6E 0x6F )(list 0x180 0x184 0x188 0x18C 0x190 0x194 0x198 0x19C 0x1A0 0x1A4 0x1A8 0x1AC 0x1B0 0x1B4 0x1B8 0x1BC ) group.long ($2+0x1000)++0x3 line.long 0x0 "REGG4_DOM_$1,Assign domain for RSTGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x70 0x71 0x72 0x73 0x74 0x75 0x76 0x77 0x78 0x79 0x7A 0x7B 0x7C 0x7D 0x7E 0x7F )(list 0x1C0 0x1C4 0x1C8 0x1CC 0x1D0 0x1D4 0x1D8 0x1DC 0x1E0 0x1E4 0x1E8 0x1EC 0x1F0 0x1F4 0x1F8 0x1FC ) group.long ($2+0x1000)++0x3 line.long 0x0 "REGG4_DOM_$1,Assign domain for RSTGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x80 0x81 0x82 0x83 0x84 0x85 0x86 0x87 0x88 0x89 0x8A 0x8B 0x8C 0x8D 0x8E 0x8F )(list 0x200 0x204 0x208 0x20C 0x210 0x214 0x218 0x21C 0x220 0x224 0x228 0x22C 0x230 0x234 0x238 0x23C ) group.long ($2+0x1000)++0x3 line.long 0x0 "REGG4_DOM_$1,Assign domain for RSTGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x90 0x91 0x92 0x93 0x94 0x95 0x96 0x97 0x98 0x99 0x9A 0x9B 0x9C 0x9D 0x9E 0x9F )(list 0x240 0x244 0x248 0x24C 0x250 0x254 0x258 0x25C 0x260 0x264 0x268 0x26C 0x270 0x274 0x278 0x27C ) group.long ($2+0x1000)++0x3 line.long 0x0 "REGG4_DOM_$1,Assign domain for RSTGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xA0 0xA1 0xA2 0xA3 0xA4 0xA5 0xA6 0xA7 0xA8 0xA9 0xAA 0xAB 0xAC 0xAD 0xAE 0xAF )(list 0x280 0x284 0x288 0x28C 0x290 0x294 0x298 0x29C 0x2A0 0x2A4 0x2A8 0x2AC 0x2B0 0x2B4 0x2B8 0x2BC ) group.long ($2+0x1000)++0x3 line.long 0x0 "REGG4_DOM_$1,Assign domain for RSTGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xB0 0xB1 0xB2 0xB3 0xB4 0xB5 0xB6 0xB7 0xB8 0xB9 0xBA 0xBB 0xBC 0xBD 0xBE 0xBF )(list 0x2C0 0x2C4 0x2C8 0x2CC 0x2D0 0x2D4 0x2D8 0x2DC 0x2E0 0x2E4 0x2E8 0x2EC 0x2F0 0x2F4 0x2F8 0x2FC ) group.long ($2+0x1000)++0x3 line.long 0x0 "REGG4_DOM_$1,Assign domain for RSTGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xC0 0xC1 0xC2 0xC3 0xC4 0xC5 0xC6 0xC7 0xC8 0xC9 0xCA 0xCB 0xCC 0xCD 0xCE 0xCF )(list 0x300 0x304 0x308 0x30C 0x310 0x314 0x318 0x31C 0x320 0x324 0x328 0x32C 0x330 0x334 0x338 0x33C ) group.long ($2+0x1000)++0x3 line.long 0x0 "REGG4_DOM_$1,Assign domain for RSTGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xD0 0xD1 0xD2 0xD3 0xD4 0xD5 0xD6 0xD7 0xD8 0xD9 0xDA 0xDB 0xDC 0xDD 0xDE 0xDF )(list 0x340 0x344 0x348 0x34C 0x350 0x354 0x358 0x35C 0x360 0x364 0x368 0x36C 0x370 0x374 0x378 0x37C ) group.long ($2+0x1000)++0x3 line.long 0x0 "REGG4_DOM_$1,Assign domain for RSTGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xE0 0xE1 0xE2 0xE3 0xE4 0xE5 0xE6 0xE7 0xE8 0xE9 0xEA 0xEB 0xEC 0xED 0xEE 0xEF )(list 0x380 0x384 0x388 0x38C 0x390 0x394 0x398 0x39C 0x3A0 0x3A4 0x3A8 0x3AC 0x3B0 0x3B4 0x3B8 0x3BC ) group.long ($2+0x1000)++0x3 line.long 0x0 "REGG4_DOM_$1,Assign domain for RSTGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xF0 0xF1 0xF2 0xF3 0xF4 0xF5 0xF6 0xF7 0xF8 0xF9 0xFA 0xFB 0xFC 0xFD 0xFE 0xFF )(list 0x3C0 0x3C4 0x3C8 0x3CC 0x3D0 0x3D4 0x3D8 0x3DC 0x3E0 0x3E4 0x3E8 0x3EC 0x3F0 0x3F4 0x3F8 0x3FC ) group.long ($2+0x1000)++0x3 line.long 0x0 "REGG4_DOM_$1,Assign domain for RSTGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x4 0x8 0xC 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C ) group.long ($2+0x1400)++0x3 line.long 0x0 "REGG5_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1A 0x1B 0x1C 0x1D 0x1E 0x1F )(list 0x40 0x44 0x48 0x4C 0x50 0x54 0x58 0x5C 0x60 0x64 0x68 0x6C 0x70 0x74 0x78 0x7C ) group.long ($2+0x1400)++0x3 line.long 0x0 "REGG5_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x20 0x21 0x22 0x23 0x24 0x25 0x26 0x27 0x28 0x29 0x2A 0x2B 0x2C 0x2D 0x2E 0x2F )(list 0x80 0x84 0x88 0x8C 0x90 0x94 0x98 0x9C 0xA0 0xA4 0xA8 0xAC 0xB0 0xB4 0xB8 0xBC ) group.long ($2+0x1400)++0x3 line.long 0x0 "REGG5_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x30 0x31 0x32 0x33 0x34 0x35 0x36 0x37 0x38 0x39 0x3A 0x3B 0x3C 0x3D 0x3E 0x3F )(list 0xC0 0xC4 0xC8 0xCC 0xD0 0xD4 0xD8 0xDC 0xE0 0xE4 0xE8 0xEC 0xF0 0xF4 0xF8 0xFC ) group.long ($2+0x1400)++0x3 line.long 0x0 "REGG5_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x40 0x41 0x42 0x43 0x44 0x45 0x46 0x47 0x48 0x49 0x4A 0x4B 0x4C 0x4D 0x4E 0x4F )(list 0x100 0x104 0x108 0x10C 0x110 0x114 0x118 0x11C 0x120 0x124 0x128 0x12C 0x130 0x134 0x138 0x13C ) group.long ($2+0x1400)++0x3 line.long 0x0 "REGG5_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x50 0x51 0x52 0x53 0x54 0x55 0x56 0x57 0x58 0x59 0x5A 0x5B 0x5C 0x5D 0x5E 0x5F )(list 0x140 0x144 0x148 0x14C 0x150 0x154 0x158 0x15C 0x160 0x164 0x168 0x16C 0x170 0x174 0x178 0x17C ) group.long ($2+0x1400)++0x3 line.long 0x0 "REGG5_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x60 0x61 0x62 0x63 0x64 0x65 0x66 0x67 0x68 0x69 0x6A 0x6B 0x6C 0x6D 0x6E 0x6F )(list 0x180 0x184 0x188 0x18C 0x190 0x194 0x198 0x19C 0x1A0 0x1A4 0x1A8 0x1AC 0x1B0 0x1B4 0x1B8 0x1BC ) group.long ($2+0x1400)++0x3 line.long 0x0 "REGG5_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x70 0x71 0x72 0x73 0x74 0x75 0x76 0x77 0x78 0x79 0x7A 0x7B 0x7C 0x7D 0x7E 0x7F )(list 0x1C0 0x1C4 0x1C8 0x1CC 0x1D0 0x1D4 0x1D8 0x1DC 0x1E0 0x1E4 0x1E8 0x1EC 0x1F0 0x1F4 0x1F8 0x1FC ) group.long ($2+0x1400)++0x3 line.long 0x0 "REGG5_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x80 0x81 0x82 0x83 0x84 0x85 0x86 0x87 0x88 0x89 0x8A 0x8B 0x8C 0x8D 0x8E 0x8F )(list 0x200 0x204 0x208 0x20C 0x210 0x214 0x218 0x21C 0x220 0x224 0x228 0x22C 0x230 0x234 0x238 0x23C ) group.long ($2+0x1400)++0x3 line.long 0x0 "REGG5_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x90 0x91 0x92 0x93 0x94 0x95 0x96 0x97 0x98 0x99 0x9A 0x9B 0x9C 0x9D 0x9E 0x9F )(list 0x240 0x244 0x248 0x24C 0x250 0x254 0x258 0x25C 0x260 0x264 0x268 0x26C 0x270 0x274 0x278 0x27C ) group.long ($2+0x1400)++0x3 line.long 0x0 "REGG5_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xA0 0xA1 0xA2 0xA3 0xA4 0xA5 0xA6 0xA7 0xA8 0xA9 0xAA 0xAB 0xAC 0xAD 0xAE 0xAF )(list 0x280 0x284 0x288 0x28C 0x290 0x294 0x298 0x29C 0x2A0 0x2A4 0x2A8 0x2AC 0x2B0 0x2B4 0x2B8 0x2BC ) group.long ($2+0x1400)++0x3 line.long 0x0 "REGG5_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xB0 0xB1 0xB2 0xB3 0xB4 0xB5 0xB6 0xB7 0xB8 0xB9 0xBA 0xBB 0xBC 0xBD 0xBE 0xBF )(list 0x2C0 0x2C4 0x2C8 0x2CC 0x2D0 0x2D4 0x2D8 0x2DC 0x2E0 0x2E4 0x2E8 0x2EC 0x2F0 0x2F4 0x2F8 0x2FC ) group.long ($2+0x1400)++0x3 line.long 0x0 "REGG5_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xC0 0xC1 0xC2 0xC3 0xC4 0xC5 0xC6 0xC7 0xC8 0xC9 0xCA 0xCB 0xCC 0xCD 0xCE 0xCF )(list 0x300 0x304 0x308 0x30C 0x310 0x314 0x318 0x31C 0x320 0x324 0x328 0x32C 0x330 0x334 0x338 0x33C ) group.long ($2+0x1400)++0x3 line.long 0x0 "REGG5_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xD0 0xD1 0xD2 0xD3 0xD4 0xD5 0xD6 0xD7 0xD8 0xD9 0xDA 0xDB 0xDC 0xDD 0xDE 0xDF )(list 0x340 0x344 0x348 0x34C 0x350 0x354 0x358 0x35C 0x360 0x364 0x368 0x36C 0x370 0x374 0x378 0x37C ) group.long ($2+0x1400)++0x3 line.long 0x0 "REGG5_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xE0 0xE1 0xE2 0xE3 0xE4 0xE5 0xE6 0xE7 0xE8 0xE9 0xEA 0xEB 0xEC 0xED 0xEE 0xEF )(list 0x380 0x384 0x388 0x38C 0x390 0x394 0x398 0x39C 0x3A0 0x3A4 0x3A8 0x3AC 0x3B0 0x3B4 0x3B8 0x3BC ) group.long ($2+0x1400)++0x3 line.long 0x0 "REGG5_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xF0 0xF1 0xF2 0xF3 0xF4 0xF5 0xF6 0xF7 0xF8 0xF9 0xFA 0xFB 0xFC 0xFD 0xFE 0xFF )(list 0x3C0 0x3C4 0x3C8 0x3CC 0x3D0 0x3D4 0x3D8 0x3DC 0x3E0 0x3E4 0x3E8 0x3EC 0x3F0 0x3F4 0x3F8 0x3FC ) group.long ($2+0x1400)++0x3 line.long 0x0 "REGG5_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x4 0x8 0xC 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C ) group.long ($2+0x1800)++0x3 line.long 0x0 "REGG6_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1A 0x1B 0x1C 0x1D 0x1E 0x1F )(list 0x40 0x44 0x48 0x4C 0x50 0x54 0x58 0x5C 0x60 0x64 0x68 0x6C 0x70 0x74 0x78 0x7C ) group.long ($2+0x1800)++0x3 line.long 0x0 "REGG6_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x20 0x21 0x22 0x23 0x24 0x25 0x26 0x27 0x28 0x29 0x2A 0x2B 0x2C 0x2D 0x2E 0x2F )(list 0x80 0x84 0x88 0x8C 0x90 0x94 0x98 0x9C 0xA0 0xA4 0xA8 0xAC 0xB0 0xB4 0xB8 0xBC ) group.long ($2+0x1800)++0x3 line.long 0x0 "REGG6_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x30 0x31 0x32 0x33 0x34 0x35 0x36 0x37 0x38 0x39 0x3A 0x3B 0x3C 0x3D 0x3E 0x3F )(list 0xC0 0xC4 0xC8 0xCC 0xD0 0xD4 0xD8 0xDC 0xE0 0xE4 0xE8 0xEC 0xF0 0xF4 0xF8 0xFC ) group.long ($2+0x1800)++0x3 line.long 0x0 "REGG6_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x40 0x41 0x42 0x43 0x44 0x45 0x46 0x47 0x48 0x49 0x4A 0x4B 0x4C 0x4D 0x4E 0x4F )(list 0x100 0x104 0x108 0x10C 0x110 0x114 0x118 0x11C 0x120 0x124 0x128 0x12C 0x130 0x134 0x138 0x13C ) group.long ($2+0x1800)++0x3 line.long 0x0 "REGG6_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x50 0x51 0x52 0x53 0x54 0x55 0x56 0x57 0x58 0x59 0x5A 0x5B 0x5C 0x5D 0x5E 0x5F )(list 0x140 0x144 0x148 0x14C 0x150 0x154 0x158 0x15C 0x160 0x164 0x168 0x16C 0x170 0x174 0x178 0x17C ) group.long ($2+0x1800)++0x3 line.long 0x0 "REGG6_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x60 0x61 0x62 0x63 0x64 0x65 0x66 0x67 0x68 0x69 0x6A 0x6B 0x6C 0x6D 0x6E 0x6F )(list 0x180 0x184 0x188 0x18C 0x190 0x194 0x198 0x19C 0x1A0 0x1A4 0x1A8 0x1AC 0x1B0 0x1B4 0x1B8 0x1BC ) group.long ($2+0x1800)++0x3 line.long 0x0 "REGG6_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x70 0x71 0x72 0x73 0x74 0x75 0x76 0x77 0x78 0x79 0x7A 0x7B 0x7C 0x7D 0x7E 0x7F )(list 0x1C0 0x1C4 0x1C8 0x1CC 0x1D0 0x1D4 0x1D8 0x1DC 0x1E0 0x1E4 0x1E8 0x1EC 0x1F0 0x1F4 0x1F8 0x1FC ) group.long ($2+0x1800)++0x3 line.long 0x0 "REGG6_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x80 0x81 0x82 0x83 0x84 0x85 0x86 0x87 0x88 0x89 0x8A 0x8B 0x8C 0x8D 0x8E 0x8F )(list 0x200 0x204 0x208 0x20C 0x210 0x214 0x218 0x21C 0x220 0x224 0x228 0x22C 0x230 0x234 0x238 0x23C ) group.long ($2+0x1800)++0x3 line.long 0x0 "REGG6_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x90 0x91 0x92 0x93 0x94 0x95 0x96 0x97 0x98 0x99 0x9A 0x9B 0x9C 0x9D 0x9E 0x9F )(list 0x240 0x244 0x248 0x24C 0x250 0x254 0x258 0x25C 0x260 0x264 0x268 0x26C 0x270 0x274 0x278 0x27C ) group.long ($2+0x1800)++0x3 line.long 0x0 "REGG6_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xA0 0xA1 0xA2 0xA3 0xA4 0xA5 0xA6 0xA7 0xA8 0xA9 0xAA 0xAB 0xAC 0xAD 0xAE 0xAF )(list 0x280 0x284 0x288 0x28C 0x290 0x294 0x298 0x29C 0x2A0 0x2A4 0x2A8 0x2AC 0x2B0 0x2B4 0x2B8 0x2BC ) group.long ($2+0x1800)++0x3 line.long 0x0 "REGG6_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xB0 0xB1 0xB2 0xB3 0xB4 0xB5 0xB6 0xB7 0xB8 0xB9 0xBA 0xBB 0xBC 0xBD 0xBE 0xBF )(list 0x2C0 0x2C4 0x2C8 0x2CC 0x2D0 0x2D4 0x2D8 0x2DC 0x2E0 0x2E4 0x2E8 0x2EC 0x2F0 0x2F4 0x2F8 0x2FC ) group.long ($2+0x1800)++0x3 line.long 0x0 "REGG6_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xC0 0xC1 0xC2 0xC3 0xC4 0xC5 0xC6 0xC7 0xC8 0xC9 0xCA 0xCB 0xCC 0xCD 0xCE 0xCF )(list 0x300 0x304 0x308 0x30C 0x310 0x314 0x318 0x31C 0x320 0x324 0x328 0x32C 0x330 0x334 0x338 0x33C ) group.long ($2+0x1800)++0x3 line.long 0x0 "REGG6_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xD0 0xD1 0xD2 0xD3 0xD4 0xD5 0xD6 0xD7 0xD8 0xD9 0xDA 0xDB 0xDC 0xDD 0xDE 0xDF )(list 0x340 0x344 0x348 0x34C 0x350 0x354 0x358 0x35C 0x360 0x364 0x368 0x36C 0x370 0x374 0x378 0x37C ) group.long ($2+0x1800)++0x3 line.long 0x0 "REGG6_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xE0 0xE1 0xE2 0xE3 0xE4 0xE5 0xE6 0xE7 0xE8 0xE9 0xEA 0xEB 0xEC 0xED 0xEE 0xEF )(list 0x380 0x384 0x388 0x38C 0x390 0x394 0x398 0x39C 0x3A0 0x3A4 0x3A8 0x3AC 0x3B0 0x3B4 0x3B8 0x3BC ) group.long ($2+0x1800)++0x3 line.long 0x0 "REGG6_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xF0 0xF1 0xF2 0xF3 0xF4 0xF5 0xF6 0xF7 0xF8 0xF9 0xFA 0xFB 0xFC 0xFD 0xFE 0xFF )(list 0x3C0 0x3C4 0x3C8 0x3CC 0x3D0 0x3D4 0x3D8 0x3DC 0x3E0 0x3E4 0x3E8 0x3EC 0x3F0 0x3F4 0x3F8 0x3FC ) group.long ($2+0x1800)++0x3 line.long 0x0 "REGG6_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x4 0x8 0xC 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C ) group.long ($2+0x1C00)++0x3 line.long 0x0 "REGG7_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1A 0x1B 0x1C 0x1D 0x1E 0x1F )(list 0x40 0x44 0x48 0x4C 0x50 0x54 0x58 0x5C 0x60 0x64 0x68 0x6C 0x70 0x74 0x78 0x7C ) group.long ($2+0x1C00)++0x3 line.long 0x0 "REGG7_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x20 0x21 0x22 0x23 0x24 0x25 0x26 0x27 0x28 0x29 0x2A 0x2B 0x2C 0x2D 0x2E 0x2F )(list 0x80 0x84 0x88 0x8C 0x90 0x94 0x98 0x9C 0xA0 0xA4 0xA8 0xAC 0xB0 0xB4 0xB8 0xBC ) group.long ($2+0x1C00)++0x3 line.long 0x0 "REGG7_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x30 0x31 0x32 0x33 0x34 0x35 0x36 0x37 0x38 0x39 0x3A 0x3B 0x3C 0x3D 0x3E 0x3F )(list 0xC0 0xC4 0xC8 0xCC 0xD0 0xD4 0xD8 0xDC 0xE0 0xE4 0xE8 0xEC 0xF0 0xF4 0xF8 0xFC ) group.long ($2+0x1C00)++0x3 line.long 0x0 "REGG7_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x40 0x41 0x42 0x43 0x44 0x45 0x46 0x47 0x48 0x49 0x4A 0x4B 0x4C 0x4D 0x4E 0x4F )(list 0x100 0x104 0x108 0x10C 0x110 0x114 0x118 0x11C 0x120 0x124 0x128 0x12C 0x130 0x134 0x138 0x13C ) group.long ($2+0x1C00)++0x3 line.long 0x0 "REGG7_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x50 0x51 0x52 0x53 0x54 0x55 0x56 0x57 0x58 0x59 0x5A 0x5B 0x5C 0x5D 0x5E 0x5F )(list 0x140 0x144 0x148 0x14C 0x150 0x154 0x158 0x15C 0x160 0x164 0x168 0x16C 0x170 0x174 0x178 0x17C ) group.long ($2+0x1C00)++0x3 line.long 0x0 "REGG7_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x60 0x61 0x62 0x63 0x64 0x65 0x66 0x67 0x68 0x69 0x6A 0x6B 0x6C 0x6D 0x6E 0x6F )(list 0x180 0x184 0x188 0x18C 0x190 0x194 0x198 0x19C 0x1A0 0x1A4 0x1A8 0x1AC 0x1B0 0x1B4 0x1B8 0x1BC ) group.long ($2+0x1C00)++0x3 line.long 0x0 "REGG7_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x70 0x71 0x72 0x73 0x74 0x75 0x76 0x77 0x78 0x79 0x7A 0x7B 0x7C 0x7D 0x7E 0x7F )(list 0x1C0 0x1C4 0x1C8 0x1CC 0x1D0 0x1D4 0x1D8 0x1DC 0x1E0 0x1E4 0x1E8 0x1EC 0x1F0 0x1F4 0x1F8 0x1FC ) group.long ($2+0x1C00)++0x3 line.long 0x0 "REGG7_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x80 0x81 0x82 0x83 0x84 0x85 0x86 0x87 0x88 0x89 0x8A 0x8B 0x8C 0x8D 0x8E 0x8F )(list 0x200 0x204 0x208 0x20C 0x210 0x214 0x218 0x21C 0x220 0x224 0x228 0x22C 0x230 0x234 0x238 0x23C ) group.long ($2+0x1C00)++0x3 line.long 0x0 "REGG7_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x90 0x91 0x92 0x93 0x94 0x95 0x96 0x97 0x98 0x99 0x9A 0x9B 0x9C 0x9D 0x9E 0x9F )(list 0x240 0x244 0x248 0x24C 0x250 0x254 0x258 0x25C 0x260 0x264 0x268 0x26C 0x270 0x274 0x278 0x27C ) group.long ($2+0x1C00)++0x3 line.long 0x0 "REGG7_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xA0 0xA1 0xA2 0xA3 0xA4 0xA5 0xA6 0xA7 0xA8 0xA9 0xAA 0xAB 0xAC 0xAD 0xAE 0xAF )(list 0x280 0x284 0x288 0x28C 0x290 0x294 0x298 0x29C 0x2A0 0x2A4 0x2A8 0x2AC 0x2B0 0x2B4 0x2B8 0x2BC ) group.long ($2+0x1C00)++0x3 line.long 0x0 "REGG7_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xB0 0xB1 0xB2 0xB3 0xB4 0xB5 0xB6 0xB7 0xB8 0xB9 0xBA 0xBB 0xBC 0xBD 0xBE 0xBF )(list 0x2C0 0x2C4 0x2C8 0x2CC 0x2D0 0x2D4 0x2D8 0x2DC 0x2E0 0x2E4 0x2E8 0x2EC 0x2F0 0x2F4 0x2F8 0x2FC ) group.long ($2+0x1C00)++0x3 line.long 0x0 "REGG7_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xC0 0xC1 0xC2 0xC3 0xC4 0xC5 0xC6 0xC7 0xC8 0xC9 0xCA 0xCB 0xCC 0xCD 0xCE 0xCF )(list 0x300 0x304 0x308 0x30C 0x310 0x314 0x318 0x31C 0x320 0x324 0x328 0x32C 0x330 0x334 0x338 0x33C ) group.long ($2+0x1C00)++0x3 line.long 0x0 "REGG7_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xD0 0xD1 0xD2 0xD3 0xD4 0xD5 0xD6 0xD7 0xD8 0xD9 0xDA 0xDB 0xDC 0xDD 0xDE 0xDF )(list 0x340 0x344 0x348 0x34C 0x350 0x354 0x358 0x35C 0x360 0x364 0x368 0x36C 0x370 0x374 0x378 0x37C ) group.long ($2+0x1C00)++0x3 line.long 0x0 "REGG7_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xE0 0xE1 0xE2 0xE3 0xE4 0xE5 0xE6 0xE7 0xE8 0xE9 0xEA 0xEB 0xEC 0xED 0xEE 0xEF )(list 0x380 0x384 0x388 0x38C 0x390 0x394 0x398 0x39C 0x3A0 0x3A4 0x3A8 0x3AC 0x3B0 0x3B4 0x3B8 0x3BC ) group.long ($2+0x1C00)++0x3 line.long 0x0 "REGG7_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xF0 0xF1 0xF2 0xF3 0xF4 0xF5 0xF6 0xF7 0xF8 0xF9 0xFA 0xFB 0xFC 0xFD 0xFE 0xFF )(list 0x3C0 0x3C4 0x3C8 0x3CC 0x3D0 0x3D4 0x3D8 0x3DC 0x3E0 0x3E4 0x3E8 0x3EC 0x3F0 0x3F4 0x3F8 0x3FC ) group.long ($2+0x1C00)++0x3 line.long 0x0 "REGG7_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end group.long 0x2000++0x17 line.long 0x0 "GLB_CTL,This register provides global enable settings for permission control." bitfld.long 0x0 5. "DOM_CFG_LOCK,Lock write for DOM_CFG_MODE bit." "0,1" bitfld.long 0x0 4. "DOM_CFG_MODE,When enabled all the source setting can be configured by master from domain 0 if it is not locked. When disabled only resource manager can configure the permission of the resource." "0,1" bitfld.long 0x0 3. "PERCK_DIS_LOCK,Lock write for PERCK_DIS" "0,1" bitfld.long 0x0 2. "PERCK_DIS,All the permission check disable." "0,1" newline bitfld.long 0x0 1. "DOM_PRO_LOCK,Lock write for DOM_PRO_EN bit." "0,1" bitfld.long 0x0 0. "DOM_PRO_EN,When disabled no domain access permission check" "0,1" line.long 0x4 "RES_MGR,Resource manager register. This regster is used to assign resource manager for global resource access control" bitfld.long 0x4 17. "MID_LOCK,Lock write for MID_EN and MID_LOW and MID_HIG registers." "0,1" bitfld.long 0x4 16. "MID_EN,Master ID check enable" "0,1" bitfld.long 0x4 15. "PRI_PER_LOCK,Lock write for PRI_PER and PRI_PER_EN" "0,1" bitfld.long 0x4 13.--14. "PRI_PER,Resource manager privileged access permission. bit0 for privileged access bit1 for user access" "0,1,2,3" newline bitfld.long 0x4 12. "PRI_PER_EN,Resource manager privileged access permission enable." "0,1" bitfld.long 0x4 11. "SEC_PER_LOCK,Lock for SEC_PER and SEC_PER_LOCK" "0,1" bitfld.long 0x4 9.--10. "SEC_PER,Resource manager secure access permission. bit 0 for secure access bit 1 for non-secure access" "0,1,2,3" bitfld.long 0x4 8. "SEC_PER_EN,Resource manager secure permission enable" "0,1" bitfld.long 0x4 7. "DID_LOCK,Lock write for DID_EN and DID" "0,1" newline hexmask.long.byte 0x4 3.--6. 1. "DID,Resource manager domain ID" bitfld.long 0x4 2. "DID_EN,Resource manager Domain ID enable" "0,1" bitfld.long 0x4 1. "RES_MGR_EN_LOCK,Lock for RES_MGR_EN" "0,1" bitfld.long 0x4 0. "RES_MGR_EN,Resource manager enable. When the bit is disable there is no resource manager." "0,1" line.long 0x8 "RES_MGR_MA0,This register is used to assign master 0~31 as resource manager." hexmask.long 0x8 0.--31. 1. "MID,Assign master 0~31 for resource manager" line.long 0xC "RES_MGR_MA1,This register is used to assign master 32~63 as resource manager." hexmask.long 0xC 0.--31. 1. "MID,Indicate if master 32~63 is resource manager." line.long 0x10 "RES_MGR_MA2,This register is used to assign master 64~95 as resource manager." hexmask.long 0x10 0.--31. 1. "MID,Indicate if master 64~95 is resource manager." line.long 0x14 "RES_MGR_MA3,This register is used to assign master 96~127 as resource manager." hexmask.long 0x14 0.--31. 1. "MID,Indicate if master 96~127 is resource manager." repeat 8. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 )(list 0x0 0x14 0x28 0x3C 0x50 0x64 0x78 0x8C ) group.long ($2+0x2100)++0x3 line.long 0x0 "GRP_MGR_$1,Group Manager Register. This register is used to assign group manager for each domain" bitfld.long 0x0 17. "MID_LOCK,Lock write for MID_EN and MID_LOW and MID_HIG registers." "0,1" bitfld.long 0x0 16. "MID_EN,Master ID check enable" "0,1" bitfld.long 0x0 15. "PRI_PER_LOCK,Lock write for PRI_PER and PRI_PER_EN" "0,1" bitfld.long 0x0 13.--14. "PRI_PER,Group manager privileged access permission. bit0 for privileged access bit1 for user access" "0,1,2,3" newline bitfld.long 0x0 12. "PRI_PER_EN,Group manager privileged access permission enable." "0,1" bitfld.long 0x0 11. "SEC_PER_LOCK,Lock for SEC_PER and SEC_PER_LOCK" "0,1" bitfld.long 0x0 9.--10. "SEC_PER,Group manager secure access permission. bit 0 for secure access bit 1 for non-secure access" "0,1,2,3" bitfld.long 0x0 8. "SEC_PER_EN,Group manager secure permission enable" "0,1" bitfld.long 0x0 7. "DID_LOCK,Lock write for DID_EN and DID" "0,1" newline hexmask.long.byte 0x0 3.--6. 1. "DID,Group manager domain ID" bitfld.long 0x0 2. "DID_EN,Group manager Domain ID enable" "0,1" bitfld.long 0x0 1. "GRP_MGR_EN_LOCK,Lock write for GPR_MGR_EN" "0,1" bitfld.long 0x0 0. "GRP_MGR_EN,Group manager enable. When the bit is disable there is no resource manager." "0,1" repeat.end repeat 8. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 )(list 0x0 0x14 0x28 0x3C 0x50 0x64 0x78 0x8C ) group.long ($2+0x2104)++0x3 line.long 0x0 "GRP_MGR_MA0_$1,Assign master 0~31 for group manager 0" hexmask.long 0x0 0.--31. 1. "MID,Assign master 0~31 for resource manager" repeat.end repeat 8. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 )(list 0x0 0x14 0x28 0x3C 0x50 0x64 0x78 0x8C ) group.long ($2+0x2108)++0x3 line.long 0x0 "GRP_MGR_MA1_$1,Assign master 32~63 for group manager 0" hexmask.long 0x0 0.--31. 1. "MID,Indicate if master 32~63 is resource manager." repeat.end repeat 8. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 )(list 0x0 0x14 0x28 0x3C 0x50 0x64 0x78 0x8C ) group.long ($2+0x210C)++0x3 line.long 0x0 "GRP_MGR_MA2_$1,Assign master 64~95 for group manager 0" hexmask.long 0x0 0.--31. 1. "MID,Indicate if master 64~95 is resource manager." repeat.end repeat 8. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 )(list 0x0 0x14 0x28 0x3C 0x50 0x64 0x78 0x8C ) group.long ($2+0x2110)++0x3 line.long 0x0 "GRP_MGR_MA3_$1,Assign master 96~127 for group manager 0" hexmask.long 0x0 0.--31. 1. "MID,Indicate if master 96~127 is resource manager." repeat.end group.long 0x2200++0x3 line.long 0x0 "DOM_GID_0,Indicate which group domain 0 belong to" bitfld.long 0x0 3. "LOCK,Lock write for GID" "0,1" bitfld.long 0x0 0.--2. "GID,Group ID" "0,1,2,3,4,5,6,7" repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x18 0x30 0x48 0x60 0x78 0x90 0xA8 0xC0 0xD8 0xF0 0x108 0x120 0x138 0x150 0x168 ) group.long ($2+0x2204)++0x3 line.long 0x0 "DOM_OWN_$1,Assign owner for function domain 0." bitfld.long 0x0 17. "MID_LOCK,Lock write for MID_EN and MID_LOW and MID_HIG registers." "0,1" bitfld.long 0x0 16. "MID_EN,Master ID check enable" "0,1" bitfld.long 0x0 15. "PRI_PER_LOCK,Lock write for PRI_PER and PRI_PER_EN" "0,1" bitfld.long 0x0 13.--14. "PRI_PER,Group manager privileged access permission. bit0 for privileged access bit1 for user access" "0,1,2,3" newline bitfld.long 0x0 12. "PRI_PER_EN,Group manager privileged access permission enable." "0,1" bitfld.long 0x0 11. "SEC_PER_LOCK,Lock for SEC_PER and SEC_PER_LOCK" "0,1" bitfld.long 0x0 9.--10. "SEC_PER,Domain owner secure access permission. bit 0 for secure access bit 1 for non-secure access" "0,1,2,3" bitfld.long 0x0 8. "SEC_PER_EN,Domain owner secure permission enable" "0,1" newline bitfld.long 0x0 1. "DOM_OWN_EN_LOCK,Lock for DOM_OWN_EN" "0,1" bitfld.long 0x0 0. "DOM_OWN_EN,Domain owner enable. When the bit is disable there is no domain owner." "0,1" repeat.end repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x18 0x30 0x48 0x60 0x78 0x90 0xA8 0xC0 0xD8 0xF0 0x108 0x120 0x138 0x150 0x168 ) group.long ($2+0x2208)++0x3 line.long 0x0 "DOM_OWN_MA0_$1,Assign master 0~31 for domain owner 0" hexmask.long 0x0 0.--31. 1. "MID,Assign master 0~31 for resource manager" repeat.end repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x18 0x30 0x48 0x60 0x78 0x90 0xA8 0xC0 0xD8 0xF0 0x108 0x120 0x138 0x150 0x168 ) group.long ($2+0x220C)++0x3 line.long 0x0 "DOM_OWN_MA1_$1,Assign master 32~63 for domain owner 0" hexmask.long 0x0 0.--31. 1. "MID,Indicate if master 32~63 is resource manager." repeat.end repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x18 0x30 0x48 0x60 0x78 0x90 0xA8 0xC0 0xD8 0xF0 0x108 0x120 0x138 0x150 0x168 ) group.long ($2+0x2210)++0x3 line.long 0x0 "DOM_OWN_MA2_$1,Assign master 64~95 for domain owner 0" hexmask.long 0x0 0.--31. 1. "MID,Indicate if master 64~95 is resource manager." repeat.end repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x18 0x30 0x48 0x60 0x78 0x90 0xA8 0xC0 0xD8 0xF0 0x108 0x120 0x138 0x150 0x168 ) group.long ($2+0x2214)++0x3 line.long 0x0 "DOM_OWN_MA3_$1,Assign master 96~127 for domain owner 0" hexmask.long 0x0 0.--31. 1. "MID,Indicate if master 96~127 is resource manager." repeat.end group.long 0x2218++0x3 line.long 0x0 "DOM_GID_1,Indicate which group domain 1 belong to" bitfld.long 0x0 3. "LOCK,Lock write for GID" "0,1" bitfld.long 0x0 0.--2. "GID,Group ID" "0,1,2,3,4,5,6,7" group.long 0x2230++0x3 line.long 0x0 "DOM_GID_2,Indicate which group domain 2 belong to" bitfld.long 0x0 3. "LOCK,Lock write for GID" "0,1" bitfld.long 0x0 0.--2. "GID,Group ID" "0,1,2,3,4,5,6,7" group.long 0x2248++0x3 line.long 0x0 "DOM_GID_3,Indicate which group domain 3 belong to" bitfld.long 0x0 3. "LOCK,Lock write for GID" "0,1" bitfld.long 0x0 0.--2. "GID,Group ID" "0,1,2,3,4,5,6,7" group.long 0x2260++0x3 line.long 0x0 "DOM_GID_4,Indicate which group domain 4 belong to" bitfld.long 0x0 3. "LOCK,Lock write for GID" "0,1" bitfld.long 0x0 0.--2. "GID,Group ID" "0,1,2,3,4,5,6,7" group.long 0x2278++0x3 line.long 0x0 "DOM_GID_5,Indicate which group domain 5 belong to" bitfld.long 0x0 3. "LOCK,Lock write for GID" "0,1" bitfld.long 0x0 0.--2. "GID,Group ID" "0,1,2,3,4,5,6,7" group.long 0x2290++0x3 line.long 0x0 "DOM_GID_6,Indicate which group domain 6 belong to" bitfld.long 0x0 3. "LOCK,Lock write for GID" "0,1" bitfld.long 0x0 0.--2. "GID,Group ID" "0,1,2,3,4,5,6,7" group.long 0x22A8++0x3 line.long 0x0 "DOM_GID_7,Indicate which group domain 7 belong to" bitfld.long 0x0 3. "LOCK,Lock write for GID" "0,1" bitfld.long 0x0 0.--2. "GID,Group ID" "0,1,2,3,4,5,6,7" group.long 0x22C0++0x3 line.long 0x0 "DOM_GID_8,Indicate which group domain 8 belong to" bitfld.long 0x0 3. "LOCK,Lock write for GID" "0,1" bitfld.long 0x0 0.--2. "GID,Group ID" "0,1,2,3,4,5,6,7" group.long 0x22D8++0x3 line.long 0x0 "DOM_GID_9,Indicate which group domain 9 belong to" bitfld.long 0x0 3. "LOCK,Lock write for GID" "0,1" bitfld.long 0x0 0.--2. "GID,Group ID" "0,1,2,3,4,5,6,7" group.long 0x22F0++0x3 line.long 0x0 "DOM_GID_10,Indicate which group domain 10 belong to" bitfld.long 0x0 3. "LOCK,Lock write for GID" "0,1" bitfld.long 0x0 0.--2. "GID,Group ID" "0,1,2,3,4,5,6,7" group.long 0x2308++0x3 line.long 0x0 "DOM_GID_11,Indicate which group domain 11 belong to" bitfld.long 0x0 3. "LOCK,Lock write for GID" "0,1" bitfld.long 0x0 0.--2. "GID,Group ID" "0,1,2,3,4,5,6,7" group.long 0x2320++0x3 line.long 0x0 "DOM_GID_12,Indicate which group domain 12 belong to" bitfld.long 0x0 3. "LOCK,Lock write for GID" "0,1" bitfld.long 0x0 0.--2. "GID,Group ID" "0,1,2,3,4,5,6,7" group.long 0x2338++0x3 line.long 0x0 "DOM_GID_13,Indicate which group domain 13 belong to" bitfld.long 0x0 3. "LOCK,Lock write for GID" "0,1" bitfld.long 0x0 0.--2. "GID,Group ID" "0,1,2,3,4,5,6,7" group.long 0x2350++0x3 line.long 0x0 "DOM_GID_14,Indicate which group domain 14 belong to" bitfld.long 0x0 3. "LOCK,Lock write for GID" "0,1" bitfld.long 0x0 0.--2. "GID,Group ID" "0,1,2,3,4,5,6,7" group.long 0x2368++0x3 line.long 0x0 "DOM_GID_15,Indicate which group domain 15 belong to" bitfld.long 0x0 3. "LOCK,Lock write for GID" "0,1" bitfld.long 0x0 0.--2. "GID,Group ID" "0,1,2,3,4,5,6,7" repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x34 0x68 0x9C 0xD0 0x104 0x138 0x16C 0x1A0 0x1D4 0x208 0x23C 0x270 0x2A4 0x2D8 0x30C ) group.long ($2+0x2400)++0x3 line.long 0x0 "DOM_PER0_$1,Domain Permission Control. It can be only configured by resource manager and domain owner." bitfld.long 0x0 31. "DOM7_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 29.--30. "DOM7_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 28. "DOM7_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 27. "DOM6_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 25.--26. "DOM6_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" newline bitfld.long 0x0 24. "DOM6_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 23. "DOM5_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 21.--22. "DOM5_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 20. "DOM5_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 19. "DOM4_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" newline bitfld.long 0x0 17.--18. "DOM4_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM4_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 15. "DOM3_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 13.--14. "DOM3_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 12. "DOM3_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" newline bitfld.long 0x0 11. "DOM2_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 9.--10. "DOM2_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM2_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 7. "DOM1_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 5.--6. "DOM1_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" newline bitfld.long 0x0 4. "DOM1_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 3. "DOM0_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 1.--2. "DOM0_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM0_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" repeat.end repeat 16. (list 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1A 0x1B 0x1C 0x1D 0x1E 0x1F )(list 0x340 0x374 0x3A8 0x3DC 0x410 0x444 0x478 0x4AC 0x4E0 0x514 0x548 0x57C 0x5B0 0x5E4 0x618 0x64C ) group.long ($2+0x2400)++0x3 line.long 0x0 "DOM_PER0_$1,Domain Permission Control. It can be only configured by resource manager and domain owner." bitfld.long 0x0 31. "DOM7_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 29.--30. "DOM7_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 28. "DOM7_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 27. "DOM6_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 25.--26. "DOM6_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" newline bitfld.long 0x0 24. "DOM6_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 23. "DOM5_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 21.--22. "DOM5_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 20. "DOM5_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 19. "DOM4_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" newline bitfld.long 0x0 17.--18. "DOM4_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM4_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 15. "DOM3_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 13.--14. "DOM3_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 12. "DOM3_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" newline bitfld.long 0x0 11. "DOM2_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 9.--10. "DOM2_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM2_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 7. "DOM1_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 5.--6. "DOM1_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" newline bitfld.long 0x0 4. "DOM1_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 3. "DOM0_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 1.--2. "DOM0_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM0_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" repeat.end repeat 16. (list 0x20 0x21 0x22 0x23 0x24 0x25 0x26 0x27 0x28 0x29 0x2A 0x2B 0x2C 0x2D 0x2E 0x2F )(list 0x680 0x6B4 0x6E8 0x71C 0x750 0x784 0x7B8 0x7EC 0x820 0x854 0x888 0x8BC 0x8F0 0x924 0x958 0x98C ) group.long ($2+0x2400)++0x3 line.long 0x0 "DOM_PER0_$1,Domain Permission Control. It can be only configured by resource manager and domain owner." bitfld.long 0x0 31. "DOM7_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 29.--30. "DOM7_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 28. "DOM7_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 27. "DOM6_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 25.--26. "DOM6_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" newline bitfld.long 0x0 24. "DOM6_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 23. "DOM5_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 21.--22. "DOM5_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 20. "DOM5_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 19. "DOM4_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" newline bitfld.long 0x0 17.--18. "DOM4_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM4_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 15. "DOM3_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 13.--14. "DOM3_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 12. "DOM3_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" newline bitfld.long 0x0 11. "DOM2_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 9.--10. "DOM2_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM2_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 7. "DOM1_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 5.--6. "DOM1_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" newline bitfld.long 0x0 4. "DOM1_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 3. "DOM0_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 1.--2. "DOM0_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM0_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" repeat.end repeat 16. (list 0x30 0x31 0x32 0x33 0x34 0x35 0x36 0x37 0x38 0x39 0x3A 0x3B 0x3C 0x3D 0x3E 0x3F )(list 0x9C0 0x9F4 0xA28 0xA5C 0xA90 0xAC4 0xAF8 0xB2C 0xB60 0xB94 0xBC8 0xBFC 0xC30 0xC64 0xC98 0xCCC ) group.long ($2+0x2400)++0x3 line.long 0x0 "DOM_PER0_$1,Domain Permission Control. It can be only configured by resource manager and domain owner." bitfld.long 0x0 31. "DOM7_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 29.--30. "DOM7_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 28. "DOM7_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 27. "DOM6_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 25.--26. "DOM6_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" newline bitfld.long 0x0 24. "DOM6_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 23. "DOM5_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 21.--22. "DOM5_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 20. "DOM5_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 19. "DOM4_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" newline bitfld.long 0x0 17.--18. "DOM4_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM4_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 15. "DOM3_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 13.--14. "DOM3_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 12. "DOM3_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" newline bitfld.long 0x0 11. "DOM2_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 9.--10. "DOM2_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM2_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 7. "DOM1_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 5.--6. "DOM1_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" newline bitfld.long 0x0 4. "DOM1_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 3. "DOM0_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 1.--2. "DOM0_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM0_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" repeat.end repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x34 0x68 0x9C 0xD0 0x104 0x138 0x16C 0x1A0 0x1D4 0x208 0x23C 0x270 0x2A4 0x2D8 0x30C ) group.long ($2+0x2404)++0x3 line.long 0x0 "DOM_PER1_$1,Domain Permission Control. It can be only configured by resource manager and domain owner." bitfld.long 0x0 31. "DOM15_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 29.--30. "DOM15_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 28. "DOM15_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 27. "DOM14_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 25.--26. "DOM14_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" newline bitfld.long 0x0 24. "DOM14_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 23. "DOM13_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 21.--22. "DOM13_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 20. "DOM13_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 19. "DOM12_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" newline bitfld.long 0x0 17.--18. "DOM12_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM12_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 15. "DOM11_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 13.--14. "DOM11_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 12. "DOM11_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" newline bitfld.long 0x0 11. "DOM10_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 9.--10. "DOM10_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM10_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 7. "DOM9_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 5.--6. "DOM9_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" newline bitfld.long 0x0 4. "DOM9_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 3. "DOM8_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 1.--2. "DOM8_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM8_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" repeat.end repeat 16. (list 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1A 0x1B 0x1C 0x1D 0x1E 0x1F )(list 0x340 0x374 0x3A8 0x3DC 0x410 0x444 0x478 0x4AC 0x4E0 0x514 0x548 0x57C 0x5B0 0x5E4 0x618 0x64C ) group.long ($2+0x2404)++0x3 line.long 0x0 "DOM_PER1_$1,Domain Permission Control. It can be only configured by resource manager and domain owner." bitfld.long 0x0 31. "DOM15_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 29.--30. "DOM15_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 28. "DOM15_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 27. "DOM14_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 25.--26. "DOM14_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" newline bitfld.long 0x0 24. "DOM14_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 23. "DOM13_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 21.--22. "DOM13_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 20. "DOM13_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 19. "DOM12_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" newline bitfld.long 0x0 17.--18. "DOM12_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM12_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 15. "DOM11_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 13.--14. "DOM11_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 12. "DOM11_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" newline bitfld.long 0x0 11. "DOM10_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 9.--10. "DOM10_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM10_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 7. "DOM9_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 5.--6. "DOM9_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" newline bitfld.long 0x0 4. "DOM9_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 3. "DOM8_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 1.--2. "DOM8_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM8_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" repeat.end repeat 16. (list 0x20 0x21 0x22 0x23 0x24 0x25 0x26 0x27 0x28 0x29 0x2A 0x2B 0x2C 0x2D 0x2E 0x2F )(list 0x680 0x6B4 0x6E8 0x71C 0x750 0x784 0x7B8 0x7EC 0x820 0x854 0x888 0x8BC 0x8F0 0x924 0x958 0x98C ) group.long ($2+0x2404)++0x3 line.long 0x0 "DOM_PER1_$1,Domain Permission Control. It can be only configured by resource manager and domain owner." bitfld.long 0x0 31. "DOM15_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 29.--30. "DOM15_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 28. "DOM15_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 27. "DOM14_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 25.--26. "DOM14_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" newline bitfld.long 0x0 24. "DOM14_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 23. "DOM13_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 21.--22. "DOM13_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 20. "DOM13_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 19. "DOM12_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" newline bitfld.long 0x0 17.--18. "DOM12_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM12_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 15. "DOM11_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 13.--14. "DOM11_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 12. "DOM11_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" newline bitfld.long 0x0 11. "DOM10_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 9.--10. "DOM10_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM10_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 7. "DOM9_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 5.--6. "DOM9_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" newline bitfld.long 0x0 4. "DOM9_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 3. "DOM8_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 1.--2. "DOM8_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM8_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" repeat.end repeat 16. (list 0x30 0x31 0x32 0x33 0x34 0x35 0x36 0x37 0x38 0x39 0x3A 0x3B 0x3C 0x3D 0x3E 0x3F )(list 0x9C0 0x9F4 0xA28 0xA5C 0xA90 0xAC4 0xAF8 0xB2C 0xB60 0xB94 0xBC8 0xBFC 0xC30 0xC64 0xC98 0xCCC ) group.long ($2+0x2404)++0x3 line.long 0x0 "DOM_PER1_$1,Domain Permission Control. It can be only configured by resource manager and domain owner." bitfld.long 0x0 31. "DOM15_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 29.--30. "DOM15_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 28. "DOM15_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 27. "DOM14_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 25.--26. "DOM14_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" newline bitfld.long 0x0 24. "DOM14_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 23. "DOM13_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 21.--22. "DOM13_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 20. "DOM13_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 19. "DOM12_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" newline bitfld.long 0x0 17.--18. "DOM12_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM12_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 15. "DOM11_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 13.--14. "DOM11_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 12. "DOM11_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" newline bitfld.long 0x0 11. "DOM10_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 9.--10. "DOM10_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM10_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 7. "DOM9_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 5.--6. "DOM9_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" newline bitfld.long 0x0 4. "DOM9_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 3. "DOM8_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 1.--2. "DOM8_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM8_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" repeat.end repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x34 0x68 0x9C 0xD0 0x104 0x138 0x16C 0x1A0 0x1D4 0x208 0x23C 0x270 0x2A4 0x2D8 0x30C ) group.long ($2+0x2408)++0x3 line.long 0x0 "SEC_PER0_$1,This register is only used for resource manager to control secure access permission." bitfld.long 0x0 31. "DOM3_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM3_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM3_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM3_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM2_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM2_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM2_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM2_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM1_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM1_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM1_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM1_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM0_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM0_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM0_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM0_SEC_EN,Domain secure permission control enable" "0,1" repeat.end repeat 16. (list 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1A 0x1B 0x1C 0x1D 0x1E 0x1F )(list 0x340 0x374 0x3A8 0x3DC 0x410 0x444 0x478 0x4AC 0x4E0 0x514 0x548 0x57C 0x5B0 0x5E4 0x618 0x64C ) group.long ($2+0x2408)++0x3 line.long 0x0 "SEC_PER0_$1,This register is only used for resource manager to control secure access permission." bitfld.long 0x0 31. "DOM3_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM3_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM3_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM3_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM2_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM2_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM2_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM2_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM1_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM1_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM1_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM1_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM0_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM0_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM0_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM0_SEC_EN,Domain secure permission control enable" "0,1" repeat.end repeat 16. (list 0x20 0x21 0x22 0x23 0x24 0x25 0x26 0x27 0x28 0x29 0x2A 0x2B 0x2C 0x2D 0x2E 0x2F )(list 0x680 0x6B4 0x6E8 0x71C 0x750 0x784 0x7B8 0x7EC 0x820 0x854 0x888 0x8BC 0x8F0 0x924 0x958 0x98C ) group.long ($2+0x2408)++0x3 line.long 0x0 "SEC_PER0_$1,This register is only used for resource manager to control secure access permission." bitfld.long 0x0 31. "DOM3_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM3_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM3_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM3_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM2_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM2_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM2_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM2_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM1_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM1_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM1_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM1_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM0_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM0_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM0_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM0_SEC_EN,Domain secure permission control enable" "0,1" repeat.end repeat 16. (list 0x30 0x31 0x32 0x33 0x34 0x35 0x36 0x37 0x38 0x39 0x3A 0x3B 0x3C 0x3D 0x3E 0x3F )(list 0x9C0 0x9F4 0xA28 0xA5C 0xA90 0xAC4 0xAF8 0xB2C 0xB60 0xB94 0xBC8 0xBFC 0xC30 0xC64 0xC98 0xCCC ) group.long ($2+0x2408)++0x3 line.long 0x0 "SEC_PER0_$1,This register is only used for resource manager to control secure access permission." bitfld.long 0x0 31. "DOM3_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM3_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM3_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM3_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM2_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM2_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM2_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM2_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM1_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM1_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM1_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM1_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM0_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM0_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM0_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM0_SEC_EN,Domain secure permission control enable" "0,1" repeat.end repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x34 0x68 0x9C 0xD0 0x104 0x138 0x16C 0x1A0 0x1D4 0x208 0x23C 0x270 0x2A4 0x2D8 0x30C ) group.long ($2+0x240C)++0x3 line.long 0x0 "SEC_PER1_$1,This register is only used for resource manager to control secure access permission." bitfld.long 0x0 31. "DOM7_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM7_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM7_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM7_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM6_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM6_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM6_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM6_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM5_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM5_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM5_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM5_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM4_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM4_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM4_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM4_SEC_EN,Domain secure permission control enable" "0,1" repeat.end repeat 16. (list 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1A 0x1B 0x1C 0x1D 0x1E 0x1F )(list 0x340 0x374 0x3A8 0x3DC 0x410 0x444 0x478 0x4AC 0x4E0 0x514 0x548 0x57C 0x5B0 0x5E4 0x618 0x64C ) group.long ($2+0x240C)++0x3 line.long 0x0 "SEC_PER1_$1,This register is only used for resource manager to control secure access permission." bitfld.long 0x0 31. "DOM7_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM7_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM7_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM7_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM6_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM6_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM6_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM6_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM5_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM5_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM5_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM5_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM4_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM4_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM4_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM4_SEC_EN,Domain secure permission control enable" "0,1" repeat.end repeat 16. (list 0x20 0x21 0x22 0x23 0x24 0x25 0x26 0x27 0x28 0x29 0x2A 0x2B 0x2C 0x2D 0x2E 0x2F )(list 0x680 0x6B4 0x6E8 0x71C 0x750 0x784 0x7B8 0x7EC 0x820 0x854 0x888 0x8BC 0x8F0 0x924 0x958 0x98C ) group.long ($2+0x240C)++0x3 line.long 0x0 "SEC_PER1_$1,This register is only used for resource manager to control secure access permission." bitfld.long 0x0 31. "DOM7_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM7_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM7_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM7_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM6_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM6_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM6_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM6_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM5_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM5_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM5_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM5_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM4_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM4_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM4_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM4_SEC_EN,Domain secure permission control enable" "0,1" repeat.end repeat 16. (list 0x30 0x31 0x32 0x33 0x34 0x35 0x36 0x37 0x38 0x39 0x3A 0x3B 0x3C 0x3D 0x3E 0x3F )(list 0x9C0 0x9F4 0xA28 0xA5C 0xA90 0xAC4 0xAF8 0xB2C 0xB60 0xB94 0xBC8 0xBFC 0xC30 0xC64 0xC98 0xCCC ) group.long ($2+0x240C)++0x3 line.long 0x0 "SEC_PER1_$1,This register is only used for resource manager to control secure access permission." bitfld.long 0x0 31. "DOM7_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM7_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM7_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM7_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM6_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM6_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM6_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM6_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM5_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM5_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM5_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM5_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM4_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM4_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM4_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM4_SEC_EN,Domain secure permission control enable" "0,1" repeat.end repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x34 0x68 0x9C 0xD0 0x104 0x138 0x16C 0x1A0 0x1D4 0x208 0x23C 0x270 0x2A4 0x2D8 0x30C ) group.long ($2+0x2410)++0x3 line.long 0x0 "SEC_PER2_$1,This register is only used for resource manager to control secure access permission." bitfld.long 0x0 31. "DOM11_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM11_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM11_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM11_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM10_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM10_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM10_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM10_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM9_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM9_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM9_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM9_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM8_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM8_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM8_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM8_SEC_EN,Domain secure permission control enable" "0,1" repeat.end repeat 16. (list 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1A 0x1B 0x1C 0x1D 0x1E 0x1F )(list 0x340 0x374 0x3A8 0x3DC 0x410 0x444 0x478 0x4AC 0x4E0 0x514 0x548 0x57C 0x5B0 0x5E4 0x618 0x64C ) group.long ($2+0x2410)++0x3 line.long 0x0 "SEC_PER2_$1,This register is only used for resource manager to control secure access permission." bitfld.long 0x0 31. "DOM11_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM11_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM11_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM11_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM10_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM10_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM10_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM10_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM9_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM9_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM9_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM9_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM8_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM8_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM8_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM8_SEC_EN,Domain secure permission control enable" "0,1" repeat.end repeat 16. (list 0x20 0x21 0x22 0x23 0x24 0x25 0x26 0x27 0x28 0x29 0x2A 0x2B 0x2C 0x2D 0x2E 0x2F )(list 0x680 0x6B4 0x6E8 0x71C 0x750 0x784 0x7B8 0x7EC 0x820 0x854 0x888 0x8BC 0x8F0 0x924 0x958 0x98C ) group.long ($2+0x2410)++0x3 line.long 0x0 "SEC_PER2_$1,This register is only used for resource manager to control secure access permission." bitfld.long 0x0 31. "DOM11_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM11_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM11_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM11_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM10_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM10_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM10_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM10_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM9_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM9_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM9_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM9_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM8_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM8_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM8_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM8_SEC_EN,Domain secure permission control enable" "0,1" repeat.end repeat 16. (list 0x30 0x31 0x32 0x33 0x34 0x35 0x36 0x37 0x38 0x39 0x3A 0x3B 0x3C 0x3D 0x3E 0x3F )(list 0x9C0 0x9F4 0xA28 0xA5C 0xA90 0xAC4 0xAF8 0xB2C 0xB60 0xB94 0xBC8 0xBFC 0xC30 0xC64 0xC98 0xCCC ) group.long ($2+0x2410)++0x3 line.long 0x0 "SEC_PER2_$1,This register is only used for resource manager to control secure access permission." bitfld.long 0x0 31. "DOM11_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM11_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM11_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM11_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM10_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM10_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM10_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM10_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM9_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM9_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM9_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM9_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM8_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM8_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM8_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM8_SEC_EN,Domain secure permission control enable" "0,1" repeat.end repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x34 0x68 0x9C 0xD0 0x104 0x138 0x16C 0x1A0 0x1D4 0x208 0x23C 0x270 0x2A4 0x2D8 0x30C ) group.long ($2+0x2414)++0x3 line.long 0x0 "SEC_PER3_$1,This register is only used for resource manager to control secure access permission." bitfld.long 0x0 31. "DOM15_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM15_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM15_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM15_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM14_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM14_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM14_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM14_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM13_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM13_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM13_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM13_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM12_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM12_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM12_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM12_SEC_EN,Domain secure permission control enable" "0,1" repeat.end repeat 16. (list 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1A 0x1B 0x1C 0x1D 0x1E 0x1F )(list 0x340 0x374 0x3A8 0x3DC 0x410 0x444 0x478 0x4AC 0x4E0 0x514 0x548 0x57C 0x5B0 0x5E4 0x618 0x64C ) group.long ($2+0x2414)++0x3 line.long 0x0 "SEC_PER3_$1,This register is only used for resource manager to control secure access permission." bitfld.long 0x0 31. "DOM15_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM15_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM15_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM15_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM14_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM14_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM14_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM14_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM13_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM13_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM13_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM13_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM12_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM12_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM12_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM12_SEC_EN,Domain secure permission control enable" "0,1" repeat.end repeat 16. (list 0x20 0x21 0x22 0x23 0x24 0x25 0x26 0x27 0x28 0x29 0x2A 0x2B 0x2C 0x2D 0x2E 0x2F )(list 0x680 0x6B4 0x6E8 0x71C 0x750 0x784 0x7B8 0x7EC 0x820 0x854 0x888 0x8BC 0x8F0 0x924 0x958 0x98C ) group.long ($2+0x2414)++0x3 line.long 0x0 "SEC_PER3_$1,This register is only used for resource manager to control secure access permission." bitfld.long 0x0 31. "DOM15_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM15_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM15_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM15_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM14_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM14_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM14_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM14_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM13_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM13_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM13_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM13_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM12_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM12_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM12_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM12_SEC_EN,Domain secure permission control enable" "0,1" repeat.end repeat 16. (list 0x30 0x31 0x32 0x33 0x34 0x35 0x36 0x37 0x38 0x39 0x3A 0x3B 0x3C 0x3D 0x3E 0x3F )(list 0x9C0 0x9F4 0xA28 0xA5C 0xA90 0xAC4 0xAF8 0xB2C 0xB60 0xB94 0xBC8 0xBFC 0xC30 0xC64 0xC98 0xCCC ) group.long ($2+0x2414)++0x3 line.long 0x0 "SEC_PER3_$1,This register is only used for resource manager to control secure access permission." bitfld.long 0x0 31. "DOM15_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM15_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM15_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM15_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM14_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM14_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM14_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM14_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM13_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM13_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM13_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM13_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM12_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM12_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM12_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM12_SEC_EN,Domain secure permission control enable" "0,1" repeat.end repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x34 0x68 0x9C 0xD0 0x104 0x138 0x16C 0x1A0 0x1D4 0x208 0x23C 0x270 0x2A4 0x2D8 0x30C ) group.long ($2+0x2418)++0x3 line.long 0x0 "PRI_PER0_$1,This register is only used for resource manager to control privileged access permission." bitfld.long 0x0 31. "DOM3_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM3_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM3_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM3_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM2_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM2_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM2_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM2_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM1_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM1_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM1_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM1_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM0_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM0_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM0_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM0_PRI_EN,Domain privileged permission control enable" "0,1" repeat.end repeat 16. (list 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1A 0x1B 0x1C 0x1D 0x1E 0x1F )(list 0x340 0x374 0x3A8 0x3DC 0x410 0x444 0x478 0x4AC 0x4E0 0x514 0x548 0x57C 0x5B0 0x5E4 0x618 0x64C ) group.long ($2+0x2418)++0x3 line.long 0x0 "PRI_PER0_$1,This register is only used for resource manager to control privileged access permission." bitfld.long 0x0 31. "DOM3_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM3_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM3_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM3_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM2_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM2_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM2_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM2_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM1_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM1_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM1_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM1_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM0_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM0_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM0_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM0_PRI_EN,Domain privileged permission control enable" "0,1" repeat.end repeat 16. (list 0x20 0x21 0x22 0x23 0x24 0x25 0x26 0x27 0x28 0x29 0x2A 0x2B 0x2C 0x2D 0x2E 0x2F )(list 0x680 0x6B4 0x6E8 0x71C 0x750 0x784 0x7B8 0x7EC 0x820 0x854 0x888 0x8BC 0x8F0 0x924 0x958 0x98C ) group.long ($2+0x2418)++0x3 line.long 0x0 "PRI_PER0_$1,This register is only used for resource manager to control privileged access permission." bitfld.long 0x0 31. "DOM3_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM3_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM3_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM3_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM2_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM2_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM2_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM2_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM1_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM1_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM1_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM1_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM0_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM0_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM0_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM0_PRI_EN,Domain privileged permission control enable" "0,1" repeat.end repeat 16. (list 0x30 0x31 0x32 0x33 0x34 0x35 0x36 0x37 0x38 0x39 0x3A 0x3B 0x3C 0x3D 0x3E 0x3F )(list 0x9C0 0x9F4 0xA28 0xA5C 0xA90 0xAC4 0xAF8 0xB2C 0xB60 0xB94 0xBC8 0xBFC 0xC30 0xC64 0xC98 0xCCC ) group.long ($2+0x2418)++0x3 line.long 0x0 "PRI_PER0_$1,This register is only used for resource manager to control privileged access permission." bitfld.long 0x0 31. "DOM3_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM3_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM3_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM3_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM2_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM2_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM2_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM2_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM1_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM1_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM1_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM1_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM0_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM0_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM0_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM0_PRI_EN,Domain privileged permission control enable" "0,1" repeat.end repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x34 0x68 0x9C 0xD0 0x104 0x138 0x16C 0x1A0 0x1D4 0x208 0x23C 0x270 0x2A4 0x2D8 0x30C ) group.long ($2+0x241C)++0x3 line.long 0x0 "PRI_PER1_$1,This register is only used for resource manager to control privileged access permission." bitfld.long 0x0 31. "DOM7_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM7_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM7_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM7_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM6_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM6_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM6_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM6_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM5_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM5_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM5_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM5_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM4_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM4_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM4_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM4_PRI_EN,Domain privileged permission control enable" "0,1" repeat.end repeat 16. (list 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1A 0x1B 0x1C 0x1D 0x1E 0x1F )(list 0x340 0x374 0x3A8 0x3DC 0x410 0x444 0x478 0x4AC 0x4E0 0x514 0x548 0x57C 0x5B0 0x5E4 0x618 0x64C ) group.long ($2+0x241C)++0x3 line.long 0x0 "PRI_PER1_$1,This register is only used for resource manager to control privileged access permission." bitfld.long 0x0 31. "DOM7_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM7_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM7_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM7_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM6_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM6_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM6_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM6_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM5_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM5_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM5_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM5_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM4_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM4_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM4_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM4_PRI_EN,Domain privileged permission control enable" "0,1" repeat.end repeat 16. (list 0x20 0x21 0x22 0x23 0x24 0x25 0x26 0x27 0x28 0x29 0x2A 0x2B 0x2C 0x2D 0x2E 0x2F )(list 0x680 0x6B4 0x6E8 0x71C 0x750 0x784 0x7B8 0x7EC 0x820 0x854 0x888 0x8BC 0x8F0 0x924 0x958 0x98C ) group.long ($2+0x241C)++0x3 line.long 0x0 "PRI_PER1_$1,This register is only used for resource manager to control privileged access permission." bitfld.long 0x0 31. "DOM7_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM7_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM7_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM7_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM6_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM6_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM6_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM6_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM5_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM5_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM5_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM5_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM4_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM4_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM4_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM4_PRI_EN,Domain privileged permission control enable" "0,1" repeat.end repeat 16. (list 0x30 0x31 0x32 0x33 0x34 0x35 0x36 0x37 0x38 0x39 0x3A 0x3B 0x3C 0x3D 0x3E 0x3F )(list 0x9C0 0x9F4 0xA28 0xA5C 0xA90 0xAC4 0xAF8 0xB2C 0xB60 0xB94 0xBC8 0xBFC 0xC30 0xC64 0xC98 0xCCC ) group.long ($2+0x241C)++0x3 line.long 0x0 "PRI_PER1_$1,This register is only used for resource manager to control privileged access permission." bitfld.long 0x0 31. "DOM7_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM7_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM7_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM7_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM6_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM6_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM6_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM6_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM5_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM5_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM5_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM5_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM4_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM4_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM4_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM4_PRI_EN,Domain privileged permission control enable" "0,1" repeat.end repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x34 0x68 0x9C 0xD0 0x104 0x138 0x16C 0x1A0 0x1D4 0x208 0x23C 0x270 0x2A4 0x2D8 0x30C ) group.long ($2+0x2420)++0x3 line.long 0x0 "PRI_PER2_$1,This register is only used for resource manager to control privileged access permission." bitfld.long 0x0 31. "DOM11_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM11_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM11_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM11_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM10_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM10_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM10_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM10_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM9_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM9_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM9_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM9_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM8_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM8_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM8_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM8_PRI_EN,Domain privileged permission control enable" "0,1" repeat.end repeat 16. (list 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1A 0x1B 0x1C 0x1D 0x1E 0x1F )(list 0x340 0x374 0x3A8 0x3DC 0x410 0x444 0x478 0x4AC 0x4E0 0x514 0x548 0x57C 0x5B0 0x5E4 0x618 0x64C ) group.long ($2+0x2420)++0x3 line.long 0x0 "PRI_PER2_$1,This register is only used for resource manager to control privileged access permission." bitfld.long 0x0 31. "DOM11_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM11_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM11_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM11_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM10_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM10_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM10_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM10_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM9_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM9_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM9_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM9_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM8_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM8_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM8_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM8_PRI_EN,Domain privileged permission control enable" "0,1" repeat.end repeat 16. (list 0x20 0x21 0x22 0x23 0x24 0x25 0x26 0x27 0x28 0x29 0x2A 0x2B 0x2C 0x2D 0x2E 0x2F )(list 0x680 0x6B4 0x6E8 0x71C 0x750 0x784 0x7B8 0x7EC 0x820 0x854 0x888 0x8BC 0x8F0 0x924 0x958 0x98C ) group.long ($2+0x2420)++0x3 line.long 0x0 "PRI_PER2_$1,This register is only used for resource manager to control privileged access permission." bitfld.long 0x0 31. "DOM11_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM11_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM11_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM11_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM10_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM10_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM10_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM10_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM9_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM9_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM9_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM9_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM8_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM8_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM8_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM8_PRI_EN,Domain privileged permission control enable" "0,1" repeat.end repeat 16. (list 0x30 0x31 0x32 0x33 0x34 0x35 0x36 0x37 0x38 0x39 0x3A 0x3B 0x3C 0x3D 0x3E 0x3F )(list 0x9C0 0x9F4 0xA28 0xA5C 0xA90 0xAC4 0xAF8 0xB2C 0xB60 0xB94 0xBC8 0xBFC 0xC30 0xC64 0xC98 0xCCC ) group.long ($2+0x2420)++0x3 line.long 0x0 "PRI_PER2_$1,This register is only used for resource manager to control privileged access permission." bitfld.long 0x0 31. "DOM11_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM11_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM11_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM11_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM10_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM10_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM10_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM10_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM9_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM9_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM9_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM9_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM8_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM8_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM8_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM8_PRI_EN,Domain privileged permission control enable" "0,1" repeat.end repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x34 0x68 0x9C 0xD0 0x104 0x138 0x16C 0x1A0 0x1D4 0x208 0x23C 0x270 0x2A4 0x2D8 0x30C ) group.long ($2+0x2424)++0x3 line.long 0x0 "PRI_PER3_$1,This register is only used for resource manager to control privileged access permission." bitfld.long 0x0 31. "DOM15_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM15_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM15_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM15_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM14_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM14_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM14_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM14_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM13_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM13_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM13_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM13_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM12_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM12_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM12_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM12_PRI_EN,Domain privileged permission control enable" "0,1" repeat.end repeat 16. (list 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1A 0x1B 0x1C 0x1D 0x1E 0x1F )(list 0x340 0x374 0x3A8 0x3DC 0x410 0x444 0x478 0x4AC 0x4E0 0x514 0x548 0x57C 0x5B0 0x5E4 0x618 0x64C ) group.long ($2+0x2424)++0x3 line.long 0x0 "PRI_PER3_$1,This register is only used for resource manager to control privileged access permission." bitfld.long 0x0 31. "DOM15_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM15_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM15_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM15_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM14_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM14_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM14_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM14_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM13_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM13_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM13_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM13_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM12_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM12_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM12_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM12_PRI_EN,Domain privileged permission control enable" "0,1" repeat.end repeat 16. (list 0x20 0x21 0x22 0x23 0x24 0x25 0x26 0x27 0x28 0x29 0x2A 0x2B 0x2C 0x2D 0x2E 0x2F )(list 0x680 0x6B4 0x6E8 0x71C 0x750 0x784 0x7B8 0x7EC 0x820 0x854 0x888 0x8BC 0x8F0 0x924 0x958 0x98C ) group.long ($2+0x2424)++0x3 line.long 0x0 "PRI_PER3_$1,This register is only used for resource manager to control privileged access permission." bitfld.long 0x0 31. "DOM15_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM15_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM15_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM15_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM14_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM14_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM14_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM14_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM13_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM13_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM13_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM13_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM12_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM12_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM12_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM12_PRI_EN,Domain privileged permission control enable" "0,1" repeat.end repeat 16. (list 0x30 0x31 0x32 0x33 0x34 0x35 0x36 0x37 0x38 0x39 0x3A 0x3B 0x3C 0x3D 0x3E 0x3F )(list 0x9C0 0x9F4 0xA28 0xA5C 0xA90 0xAC4 0xAF8 0xB2C 0xB60 0xB94 0xBC8 0xBFC 0xC30 0xC64 0xC98 0xCCC ) group.long ($2+0x2424)++0x3 line.long 0x0 "PRI_PER3_$1,This register is only used for resource manager to control privileged access permission." bitfld.long 0x0 31. "DOM15_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM15_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM15_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM15_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM14_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM14_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM14_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM14_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM13_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM13_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM13_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM13_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM12_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM12_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM12_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM12_PRI_EN,Domain privileged permission control enable" "0,1" repeat.end repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x34 0x68 0x9C 0xD0 0x104 0x138 0x16C 0x1A0 0x1D4 0x208 0x23C 0x270 0x2A4 0x2D8 0x30C ) group.long ($2+0x2428)++0x3 line.long 0x0 "DOM_SEC_PER_$1,This register is only used for domain master to control secure access permission. When the domain master write this register. it only changes the secure permission for itself. When the domain master read this register. it gets permission.." bitfld.long 0x0 7. "DOM_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" newline bitfld.long 0x0 0. "DOM_SEC_EN,Domain secure permission control enable" "0,1" repeat.end repeat 16. (list 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1A 0x1B 0x1C 0x1D 0x1E 0x1F )(list 0x340 0x374 0x3A8 0x3DC 0x410 0x444 0x478 0x4AC 0x4E0 0x514 0x548 0x57C 0x5B0 0x5E4 0x618 0x64C ) group.long ($2+0x2428)++0x3 line.long 0x0 "DOM_SEC_PER_$1,This register is only used for domain master to control secure access permission. When the domain master write this register. it only changes the secure permission for itself. When the domain master read this register. it gets permission.." bitfld.long 0x0 7. "DOM_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" newline bitfld.long 0x0 0. "DOM_SEC_EN,Domain secure permission control enable" "0,1" repeat.end repeat 16. (list 0x20 0x21 0x22 0x23 0x24 0x25 0x26 0x27 0x28 0x29 0x2A 0x2B 0x2C 0x2D 0x2E 0x2F )(list 0x680 0x6B4 0x6E8 0x71C 0x750 0x784 0x7B8 0x7EC 0x820 0x854 0x888 0x8BC 0x8F0 0x924 0x958 0x98C ) group.long ($2+0x2428)++0x3 line.long 0x0 "DOM_SEC_PER_$1,This register is only used for domain master to control secure access permission. When the domain master write this register. it only changes the secure permission for itself. When the domain master read this register. it gets permission.." bitfld.long 0x0 7. "DOM_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" newline bitfld.long 0x0 0. "DOM_SEC_EN,Domain secure permission control enable" "0,1" repeat.end repeat 16. (list 0x30 0x31 0x32 0x33 0x34 0x35 0x36 0x37 0x38 0x39 0x3A 0x3B 0x3C 0x3D 0x3E 0x3F )(list 0x9C0 0x9F4 0xA28 0xA5C 0xA90 0xAC4 0xAF8 0xB2C 0xB60 0xB94 0xBC8 0xBFC 0xC30 0xC64 0xC98 0xCCC ) group.long ($2+0x2428)++0x3 line.long 0x0 "DOM_SEC_PER_$1,This register is only used for domain master to control secure access permission. When the domain master write this register. it only changes the secure permission for itself. When the domain master read this register. it gets permission.." bitfld.long 0x0 7. "DOM_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" newline bitfld.long 0x0 0. "DOM_SEC_EN,Domain secure permission control enable" "0,1" repeat.end repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x34 0x68 0x9C 0xD0 0x104 0x138 0x16C 0x1A0 0x1D4 0x208 0x23C 0x270 0x2A4 0x2D8 0x30C ) group.long ($2+0x242C)++0x3 line.long 0x0 "DOM_PRI_PER_$1,This register is only used for domain master to control secure access permission. When the domain master write this register. it only changes the secure permission for itself. When the domain master read this register. it gets permission.." bitfld.long 0x0 7. "DOM_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" newline bitfld.long 0x0 0. "DOM_PRI_EN,Domain privileged permission control enable" "0,1" repeat.end repeat 16. (list 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1A 0x1B 0x1C 0x1D 0x1E 0x1F )(list 0x340 0x374 0x3A8 0x3DC 0x410 0x444 0x478 0x4AC 0x4E0 0x514 0x548 0x57C 0x5B0 0x5E4 0x618 0x64C ) group.long ($2+0x242C)++0x3 line.long 0x0 "DOM_PRI_PER_$1,This register is only used for domain master to control secure access permission. When the domain master write this register. it only changes the secure permission for itself. When the domain master read this register. it gets permission.." bitfld.long 0x0 7. "DOM_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" newline bitfld.long 0x0 0. "DOM_PRI_EN,Domain privileged permission control enable" "0,1" repeat.end repeat 16. (list 0x20 0x21 0x22 0x23 0x24 0x25 0x26 0x27 0x28 0x29 0x2A 0x2B 0x2C 0x2D 0x2E 0x2F )(list 0x680 0x6B4 0x6E8 0x71C 0x750 0x784 0x7B8 0x7EC 0x820 0x854 0x888 0x8BC 0x8F0 0x924 0x958 0x98C ) group.long ($2+0x242C)++0x3 line.long 0x0 "DOM_PRI_PER_$1,This register is only used for domain master to control secure access permission. When the domain master write this register. it only changes the secure permission for itself. When the domain master read this register. it gets permission.." bitfld.long 0x0 7. "DOM_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" newline bitfld.long 0x0 0. "DOM_PRI_EN,Domain privileged permission control enable" "0,1" repeat.end repeat 16. (list 0x30 0x31 0x32 0x33 0x34 0x35 0x36 0x37 0x38 0x39 0x3A 0x3B 0x3C 0x3D 0x3E 0x3F )(list 0x9C0 0x9F4 0xA28 0xA5C 0xA90 0xAC4 0xAF8 0xB2C 0xB60 0xB94 0xBC8 0xBFC 0xC30 0xC64 0xC98 0xCCC ) group.long ($2+0x242C)++0x3 line.long 0x0 "DOM_PRI_PER_$1,This register is only used for domain master to control secure access permission. When the domain master write this register. it only changes the secure permission for itself. When the domain master read this register. it gets permission.." bitfld.long 0x0 7. "DOM_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" newline bitfld.long 0x0 0. "DOM_PRI_EN,Domain privileged permission control enable" "0,1" repeat.end repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x34 0x68 0x9C 0xD0 0x104 0x138 0x16C 0x1A0 0x1D4 0x208 0x23C 0x270 0x2A4 0x2D8 0x30C ) group.long ($2+0x2430)++0x3 line.long 0x0 "DOM_ASSIGN_$1,Use to assign domain for accessing DOM_SEC_PER and DOM_PRI_PER register. Only resource manager. group manager and domain owner can access this register. For write. group manager must write its owen domain ID. otherwise write accessing will.." hexmask.long.byte 0x0 0.--3. 1. "DID,accessing DOM_SEC_PER and DOM_PRI_PER register" repeat.end repeat 16. (list 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1A 0x1B 0x1C 0x1D 0x1E 0x1F )(list 0x340 0x374 0x3A8 0x3DC 0x410 0x444 0x478 0x4AC 0x4E0 0x514 0x548 0x57C 0x5B0 0x5E4 0x618 0x64C ) group.long ($2+0x2430)++0x3 line.long 0x0 "DOM_ASSIGN_$1,Use to assign domain for accessing DOM_SEC_PER and DOM_PRI_PER register. Only resource manager. group manager and domain owner can access this register. For write. group manager must write its owen domain ID. otherwise write accessing will.." hexmask.long.byte 0x0 0.--3. 1. "DID,accessing DOM_SEC_PER and DOM_PRI_PER register" repeat.end repeat 16. (list 0x20 0x21 0x22 0x23 0x24 0x25 0x26 0x27 0x28 0x29 0x2A 0x2B 0x2C 0x2D 0x2E 0x2F )(list 0x680 0x6B4 0x6E8 0x71C 0x750 0x784 0x7B8 0x7EC 0x820 0x854 0x888 0x8BC 0x8F0 0x924 0x958 0x98C ) group.long ($2+0x2430)++0x3 line.long 0x0 "DOM_ASSIGN_$1,Use to assign domain for accessing DOM_SEC_PER and DOM_PRI_PER register. Only resource manager. group manager and domain owner can access this register. For write. group manager must write its owen domain ID. otherwise write accessing will.." hexmask.long.byte 0x0 0.--3. 1. "DID,accessing DOM_SEC_PER and DOM_PRI_PER register" repeat.end repeat 16. (list 0x30 0x31 0x32 0x33 0x34 0x35 0x36 0x37 0x38 0x39 0x3A 0x3B 0x3C 0x3D 0x3E 0x3F )(list 0x9C0 0x9F4 0xA28 0xA5C 0xA90 0xAC4 0xAF8 0xB2C 0xB60 0xB94 0xBC8 0xBFC 0xC30 0xC64 0xC98 0xCCC ) group.long ($2+0x2430)++0x3 line.long 0x0 "DOM_ASSIGN_$1,Use to assign domain for accessing DOM_SEC_PER and DOM_PRI_PER register. Only resource manager. group manager and domain owner can access this register. For write. group manager must write its owen domain ID. otherwise write accessing will.." hexmask.long.byte 0x0 0.--3. 1. "DID,accessing DOM_SEC_PER and DOM_PRI_PER register" repeat.end repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x38 0x70 0xA8 0xE0 0x118 0x150 0x188 0x1C0 0x1F8 0x230 0x268 0x2A0 0x2D8 0x310 0x348 ) group.long ($2+0x3100)++0x3 line.long 0x0 "RGN_DOM_$1,Assign domain for peripheral. It can be only configured by resource and group manager" bitfld.long 0x0 31. "LOCK,When this bit is set lock write for all the bits in the register." "0,1" bitfld.long 0x0 4. "SET,Set together with DID would change permission of this resource to following setting: 1) Domain access control enabled. 2) Read/Write allowed for the domain owner. 3) Read/Write not allowed for all the other domains. If this bit is not set only DID.." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Assign domain for peripheral" repeat.end repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x38 0x70 0xA8 0xE0 0x118 0x150 0x188 0x1C0 0x1F8 0x230 0x268 0x2A0 0x2D8 0x310 0x348 ) group.long ($2+0x3104)++0x3 line.long 0x0 "RGN_DOM_PER0_$1,Domain Permission Control. It can be only configured by resource manager and domain owner." bitfld.long 0x0 31. "DOM7_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 29.--30. "DOM7_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 28. "DOM7_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 27. "DOM6_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 25.--26. "DOM6_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" newline bitfld.long 0x0 24. "DOM6_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 23. "DOM5_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 21.--22. "DOM5_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 20. "DOM5_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 19. "DOM4_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" newline bitfld.long 0x0 17.--18. "DOM4_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM4_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 15. "DOM3_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 13.--14. "DOM3_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 12. "DOM3_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" newline bitfld.long 0x0 11. "DOM2_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 9.--10. "DOM2_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM2_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 7. "DOM1_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 5.--6. "DOM1_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" newline bitfld.long 0x0 4. "DOM1_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 3. "DOM0_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 1.--2. "DOM0_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM0_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" repeat.end repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x38 0x70 0xA8 0xE0 0x118 0x150 0x188 0x1C0 0x1F8 0x230 0x268 0x2A0 0x2D8 0x310 0x348 ) group.long ($2+0x3108)++0x3 line.long 0x0 "RGN_DOM_PER1_$1,Domain Permission Control. It can be only configured by resource manager and domain owner." bitfld.long 0x0 31. "DOM15_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 29.--30. "DOM15_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 28. "DOM15_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 27. "DOM14_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 25.--26. "DOM14_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" newline bitfld.long 0x0 24. "DOM14_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 23. "DOM13_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 21.--22. "DOM13_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 20. "DOM13_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 19. "DOM12_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" newline bitfld.long 0x0 17.--18. "DOM12_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM12_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 15. "DOM11_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 13.--14. "DOM11_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 12. "DOM11_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" newline bitfld.long 0x0 11. "DOM10_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 9.--10. "DOM10_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM10_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 7. "DOM9_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 5.--6. "DOM9_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" newline bitfld.long 0x0 4. "DOM9_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 3. "DOM8_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 1.--2. "DOM8_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM8_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" repeat.end repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x38 0x70 0xA8 0xE0 0x118 0x150 0x188 0x1C0 0x1F8 0x230 0x268 0x2A0 0x2D8 0x310 0x348 ) group.long ($2+0x310C)++0x3 line.long 0x0 "RGN_SEC_PER0_$1,This register is only used for resource manager to control secure access permission." bitfld.long 0x0 31. "DOM3_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM3_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM3_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM3_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM2_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM2_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM2_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM2_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM1_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM1_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM1_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM1_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM0_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM0_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM0_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM0_SEC_EN,Domain secure permission control enable" "0,1" repeat.end repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x38 0x70 0xA8 0xE0 0x118 0x150 0x188 0x1C0 0x1F8 0x230 0x268 0x2A0 0x2D8 0x310 0x348 ) group.long ($2+0x3110)++0x3 line.long 0x0 "RGN_SEC_PER1_$1,This register is only used for resource manager to control secure access permission." bitfld.long 0x0 31. "DOM7_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM7_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM7_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM7_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM6_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM6_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM6_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM6_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM5_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM5_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM5_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM5_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM4_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM4_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM4_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM4_SEC_EN,Domain secure permission control enable" "0,1" repeat.end repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x38 0x70 0xA8 0xE0 0x118 0x150 0x188 0x1C0 0x1F8 0x230 0x268 0x2A0 0x2D8 0x310 0x348 ) group.long ($2+0x3114)++0x3 line.long 0x0 "RGN_SEC_PER2_$1,This register is only used for resource manager to control secure access permission." bitfld.long 0x0 31. "DOM11_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM11_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM11_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM11_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM10_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM10_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM10_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM10_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM9_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM9_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM9_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM9_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM8_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM8_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM8_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM8_SEC_EN,Domain secure permission control enable" "0,1" repeat.end repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x38 0x70 0xA8 0xE0 0x118 0x150 0x188 0x1C0 0x1F8 0x230 0x268 0x2A0 0x2D8 0x310 0x348 ) group.long ($2+0x3118)++0x3 line.long 0x0 "RGN_SEC_PER3_$1,This register is only used for resource manager to control secure access permission." bitfld.long 0x0 31. "DOM15_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM15_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM15_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM15_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM14_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM14_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM14_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM14_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM13_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM13_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM13_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM13_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM12_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM12_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM12_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM12_SEC_EN,Domain secure permission control enable" "0,1" repeat.end repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x38 0x70 0xA8 0xE0 0x118 0x150 0x188 0x1C0 0x1F8 0x230 0x268 0x2A0 0x2D8 0x310 0x348 ) group.long ($2+0x311C)++0x3 line.long 0x0 "RGN_PRI_PER0_$1,This register is only used for resource manager to control privileged access permission." bitfld.long 0x0 31. "DOM3_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM3_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM3_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM3_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM2_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM2_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM2_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM2_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM1_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM1_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM1_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM1_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM0_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM0_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM0_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM0_PRI_EN,Domain privileged permission control enable" "0,1" repeat.end repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x38 0x70 0xA8 0xE0 0x118 0x150 0x188 0x1C0 0x1F8 0x230 0x268 0x2A0 0x2D8 0x310 0x348 ) group.long ($2+0x3120)++0x3 line.long 0x0 "RGN_PRI_PER1_$1,This register is only used for resource manager to control privileged access permission." bitfld.long 0x0 31. "DOM7_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM7_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM7_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM7_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM6_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM6_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM6_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM6_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM5_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM5_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM5_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM5_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM4_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM4_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM4_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM4_PRI_EN,Domain privileged permission control enable" "0,1" repeat.end repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x38 0x70 0xA8 0xE0 0x118 0x150 0x188 0x1C0 0x1F8 0x230 0x268 0x2A0 0x2D8 0x310 0x348 ) group.long ($2+0x3124)++0x3 line.long 0x0 "RGN_PRI_PER2_$1,This register is only used for resource manager to control privileged access permission." bitfld.long 0x0 31. "DOM11_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM11_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM11_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM11_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM10_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM10_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM10_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM10_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM9_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM9_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM9_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM9_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM8_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM8_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM8_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM8_PRI_EN,Domain privileged permission control enable" "0,1" repeat.end repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x38 0x70 0xA8 0xE0 0x118 0x150 0x188 0x1C0 0x1F8 0x230 0x268 0x2A0 0x2D8 0x310 0x348 ) group.long ($2+0x3128)++0x3 line.long 0x0 "RGN_PRI_PER3_$1,This register is only used for resource manager to control privileged access permission." bitfld.long 0x0 31. "DOM15_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM15_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM15_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM15_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM14_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM14_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM14_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM14_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM13_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM13_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM13_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM13_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM12_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM12_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM12_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM12_PRI_EN,Domain privileged permission control enable" "0,1" repeat.end repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x38 0x70 0xA8 0xE0 0x118 0x150 0x188 0x1C0 0x1F8 0x230 0x268 0x2A0 0x2D8 0x310 0x348 ) group.long ($2+0x312C)++0x3 line.long 0x0 "RGN_DOM_SEC_PER_$1,This register is only used for domain master to control secure access permission. When the domain master write this register. it only changes the secure permission for itself. When the domain master read this register. it gets.." bitfld.long 0x0 7. "DOM_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" newline bitfld.long 0x0 0. "DOM_SEC_EN,Domain secure permission control enable" "0,1" repeat.end repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x38 0x70 0xA8 0xE0 0x118 0x150 0x188 0x1C0 0x1F8 0x230 0x268 0x2A0 0x2D8 0x310 0x348 ) group.long ($2+0x3130)++0x3 line.long 0x0 "RGN_DOM_PRI_PER_$1,This register is only used for domain master to control secure access permission. When the domain master write this register. it only changes the secure permission for itself. When the domain master read this register. it gets.." bitfld.long 0x0 7. "DOM_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" newline bitfld.long 0x0 0. "DOM_PRI_EN,Domain privileged permission control enable" "0,1" repeat.end repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x38 0x70 0xA8 0xE0 0x118 0x150 0x188 0x1C0 0x1F8 0x230 0x268 0x2A0 0x2D8 0x310 0x348 ) group.long ($2+0x3134)++0x3 line.long 0x0 "RGN_DOM_ASSIGN_$1,Use to assign domain for accessing DOM_SEC_PER and DOM_PRI_PER register. Only resource manager. group manager and domain owner can access this register. For write. group manager must write its owen domain ID. otherwise write accessing.." hexmask.long.byte 0x0 0.--3. 1. "DID,accessing DOM_SEC_PER and DOM_PRI_PER register" repeat.end tree.end tree "RPC_AP_PINCTRL" base ad:0x38D00000 repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x4 0x8 0xC 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C ) group.long ($2)++0x3 line.long 0x0 "REGG0_DOM_$1,Assign domain for CKGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1A 0x1B 0x1C 0x1D 0x1E 0x1F )(list 0x40 0x44 0x48 0x4C 0x50 0x54 0x58 0x5C 0x60 0x64 0x68 0x6C 0x70 0x74 0x78 0x7C ) group.long ($2)++0x3 line.long 0x0 "REGG0_DOM_$1,Assign domain for CKGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x20 0x21 0x22 0x23 0x24 0x25 0x26 0x27 0x28 0x29 0x2A 0x2B 0x2C 0x2D 0x2E 0x2F )(list 0x80 0x84 0x88 0x8C 0x90 0x94 0x98 0x9C 0xA0 0xA4 0xA8 0xAC 0xB0 0xB4 0xB8 0xBC ) group.long ($2)++0x3 line.long 0x0 "REGG0_DOM_$1,Assign domain for CKGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x30 0x31 0x32 0x33 0x34 0x35 0x36 0x37 0x38 0x39 0x3A 0x3B 0x3C 0x3D 0x3E 0x3F )(list 0xC0 0xC4 0xC8 0xCC 0xD0 0xD4 0xD8 0xDC 0xE0 0xE4 0xE8 0xEC 0xF0 0xF4 0xF8 0xFC ) group.long ($2)++0x3 line.long 0x0 "REGG0_DOM_$1,Assign domain for CKGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x40 0x41 0x42 0x43 0x44 0x45 0x46 0x47 0x48 0x49 0x4A 0x4B 0x4C 0x4D 0x4E 0x4F )(list 0x100 0x104 0x108 0x10C 0x110 0x114 0x118 0x11C 0x120 0x124 0x128 0x12C 0x130 0x134 0x138 0x13C ) group.long ($2)++0x3 line.long 0x0 "REGG0_DOM_$1,Assign domain for CKGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x50 0x51 0x52 0x53 0x54 0x55 0x56 0x57 0x58 0x59 0x5A 0x5B 0x5C 0x5D 0x5E 0x5F )(list 0x140 0x144 0x148 0x14C 0x150 0x154 0x158 0x15C 0x160 0x164 0x168 0x16C 0x170 0x174 0x178 0x17C ) group.long ($2)++0x3 line.long 0x0 "REGG0_DOM_$1,Assign domain for CKGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x60 0x61 0x62 0x63 0x64 0x65 0x66 0x67 0x68 0x69 0x6A 0x6B 0x6C 0x6D 0x6E 0x6F )(list 0x180 0x184 0x188 0x18C 0x190 0x194 0x198 0x19C 0x1A0 0x1A4 0x1A8 0x1AC 0x1B0 0x1B4 0x1B8 0x1BC ) group.long ($2)++0x3 line.long 0x0 "REGG0_DOM_$1,Assign domain for CKGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x70 0x71 0x72 0x73 0x74 0x75 0x76 0x77 0x78 0x79 0x7A 0x7B 0x7C 0x7D 0x7E 0x7F )(list 0x1C0 0x1C4 0x1C8 0x1CC 0x1D0 0x1D4 0x1D8 0x1DC 0x1E0 0x1E4 0x1E8 0x1EC 0x1F0 0x1F4 0x1F8 0x1FC ) group.long ($2)++0x3 line.long 0x0 "REGG0_DOM_$1,Assign domain for CKGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x80 0x81 0x82 0x83 0x84 0x85 0x86 0x87 0x88 0x89 0x8A 0x8B 0x8C 0x8D 0x8E 0x8F )(list 0x200 0x204 0x208 0x20C 0x210 0x214 0x218 0x21C 0x220 0x224 0x228 0x22C 0x230 0x234 0x238 0x23C ) group.long ($2)++0x3 line.long 0x0 "REGG0_DOM_$1,Assign domain for CKGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x90 0x91 0x92 0x93 0x94 0x95 0x96 0x97 0x98 0x99 0x9A 0x9B 0x9C 0x9D 0x9E 0x9F )(list 0x240 0x244 0x248 0x24C 0x250 0x254 0x258 0x25C 0x260 0x264 0x268 0x26C 0x270 0x274 0x278 0x27C ) group.long ($2)++0x3 line.long 0x0 "REGG0_DOM_$1,Assign domain for CKGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xA0 0xA1 0xA2 0xA3 0xA4 0xA5 0xA6 0xA7 0xA8 0xA9 0xAA 0xAB 0xAC 0xAD 0xAE 0xAF )(list 0x280 0x284 0x288 0x28C 0x290 0x294 0x298 0x29C 0x2A0 0x2A4 0x2A8 0x2AC 0x2B0 0x2B4 0x2B8 0x2BC ) group.long ($2)++0x3 line.long 0x0 "REGG0_DOM_$1,Assign domain for CKGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xB0 0xB1 0xB2 0xB3 0xB4 0xB5 0xB6 0xB7 0xB8 0xB9 0xBA 0xBB 0xBC 0xBD 0xBE 0xBF )(list 0x2C0 0x2C4 0x2C8 0x2CC 0x2D0 0x2D4 0x2D8 0x2DC 0x2E0 0x2E4 0x2E8 0x2EC 0x2F0 0x2F4 0x2F8 0x2FC ) group.long ($2)++0x3 line.long 0x0 "REGG0_DOM_$1,Assign domain for CKGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xC0 0xC1 0xC2 0xC3 0xC4 0xC5 0xC6 0xC7 0xC8 0xC9 0xCA 0xCB 0xCC 0xCD 0xCE 0xCF )(list 0x300 0x304 0x308 0x30C 0x310 0x314 0x318 0x31C 0x320 0x324 0x328 0x32C 0x330 0x334 0x338 0x33C ) group.long ($2)++0x3 line.long 0x0 "REGG0_DOM_$1,Assign domain for CKGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xD0 0xD1 0xD2 0xD3 0xD4 0xD5 0xD6 0xD7 0xD8 0xD9 0xDA 0xDB 0xDC 0xDD 0xDE 0xDF )(list 0x340 0x344 0x348 0x34C 0x350 0x354 0x358 0x35C 0x360 0x364 0x368 0x36C 0x370 0x374 0x378 0x37C ) group.long ($2)++0x3 line.long 0x0 "REGG0_DOM_$1,Assign domain for CKGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xE0 0xE1 0xE2 0xE3 0xE4 0xE5 0xE6 0xE7 0xE8 0xE9 0xEA 0xEB 0xEC 0xED 0xEE 0xEF )(list 0x380 0x384 0x388 0x38C 0x390 0x394 0x398 0x39C 0x3A0 0x3A4 0x3A8 0x3AC 0x3B0 0x3B4 0x3B8 0x3BC ) group.long ($2)++0x3 line.long 0x0 "REGG0_DOM_$1,Assign domain for CKGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xF0 0xF1 0xF2 0xF3 0xF4 0xF5 0xF6 0xF7 0xF8 0xF9 0xFA 0xFB 0xFC 0xFD 0xFE 0xFF )(list 0x3C0 0x3C4 0x3C8 0x3CC 0x3D0 0x3D4 0x3D8 0x3DC 0x3E0 0x3E4 0x3E8 0x3EC 0x3F0 0x3F4 0x3F8 0x3FC ) group.long ($2)++0x3 line.long 0x0 "REGG0_DOM_$1,Assign domain for CKGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x4 0x8 0xC 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C ) group.long ($2+0x400)++0x3 line.long 0x0 "REGG1_DOM_$1,Assign domain for CKGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1A 0x1B 0x1C 0x1D 0x1E 0x1F )(list 0x40 0x44 0x48 0x4C 0x50 0x54 0x58 0x5C 0x60 0x64 0x68 0x6C 0x70 0x74 0x78 0x7C ) group.long ($2+0x400)++0x3 line.long 0x0 "REGG1_DOM_$1,Assign domain for CKGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x20 0x21 0x22 0x23 0x24 0x25 0x26 0x27 0x28 0x29 0x2A 0x2B 0x2C 0x2D 0x2E 0x2F )(list 0x80 0x84 0x88 0x8C 0x90 0x94 0x98 0x9C 0xA0 0xA4 0xA8 0xAC 0xB0 0xB4 0xB8 0xBC ) group.long ($2+0x400)++0x3 line.long 0x0 "REGG1_DOM_$1,Assign domain for CKGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x30 0x31 0x32 0x33 0x34 0x35 0x36 0x37 0x38 0x39 0x3A 0x3B 0x3C 0x3D 0x3E 0x3F )(list 0xC0 0xC4 0xC8 0xCC 0xD0 0xD4 0xD8 0xDC 0xE0 0xE4 0xE8 0xEC 0xF0 0xF4 0xF8 0xFC ) group.long ($2+0x400)++0x3 line.long 0x0 "REGG1_DOM_$1,Assign domain for CKGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x40 0x41 0x42 0x43 0x44 0x45 0x46 0x47 0x48 0x49 0x4A 0x4B 0x4C 0x4D 0x4E 0x4F )(list 0x100 0x104 0x108 0x10C 0x110 0x114 0x118 0x11C 0x120 0x124 0x128 0x12C 0x130 0x134 0x138 0x13C ) group.long ($2+0x400)++0x3 line.long 0x0 "REGG1_DOM_$1,Assign domain for CKGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x50 0x51 0x52 0x53 0x54 0x55 0x56 0x57 0x58 0x59 0x5A 0x5B 0x5C 0x5D 0x5E 0x5F )(list 0x140 0x144 0x148 0x14C 0x150 0x154 0x158 0x15C 0x160 0x164 0x168 0x16C 0x170 0x174 0x178 0x17C ) group.long ($2+0x400)++0x3 line.long 0x0 "REGG1_DOM_$1,Assign domain for CKGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x60 0x61 0x62 0x63 0x64 0x65 0x66 0x67 0x68 0x69 0x6A 0x6B 0x6C 0x6D 0x6E 0x6F )(list 0x180 0x184 0x188 0x18C 0x190 0x194 0x198 0x19C 0x1A0 0x1A4 0x1A8 0x1AC 0x1B0 0x1B4 0x1B8 0x1BC ) group.long ($2+0x400)++0x3 line.long 0x0 "REGG1_DOM_$1,Assign domain for CKGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x70 0x71 0x72 0x73 0x74 0x75 0x76 0x77 0x78 0x79 0x7A 0x7B 0x7C 0x7D 0x7E 0x7F )(list 0x1C0 0x1C4 0x1C8 0x1CC 0x1D0 0x1D4 0x1D8 0x1DC 0x1E0 0x1E4 0x1E8 0x1EC 0x1F0 0x1F4 0x1F8 0x1FC ) group.long ($2+0x400)++0x3 line.long 0x0 "REGG1_DOM_$1,Assign domain for CKGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x80 0x81 0x82 0x83 0x84 0x85 0x86 0x87 0x88 0x89 0x8A 0x8B 0x8C 0x8D 0x8E 0x8F )(list 0x200 0x204 0x208 0x20C 0x210 0x214 0x218 0x21C 0x220 0x224 0x228 0x22C 0x230 0x234 0x238 0x23C ) group.long ($2+0x400)++0x3 line.long 0x0 "REGG1_DOM_$1,Assign domain for CKGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x90 0x91 0x92 0x93 0x94 0x95 0x96 0x97 0x98 0x99 0x9A 0x9B 0x9C 0x9D 0x9E 0x9F )(list 0x240 0x244 0x248 0x24C 0x250 0x254 0x258 0x25C 0x260 0x264 0x268 0x26C 0x270 0x274 0x278 0x27C ) group.long ($2+0x400)++0x3 line.long 0x0 "REGG1_DOM_$1,Assign domain for CKGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xA0 0xA1 0xA2 0xA3 0xA4 0xA5 0xA6 0xA7 0xA8 0xA9 0xAA 0xAB 0xAC 0xAD 0xAE 0xAF )(list 0x280 0x284 0x288 0x28C 0x290 0x294 0x298 0x29C 0x2A0 0x2A4 0x2A8 0x2AC 0x2B0 0x2B4 0x2B8 0x2BC ) group.long ($2+0x400)++0x3 line.long 0x0 "REGG1_DOM_$1,Assign domain for CKGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xB0 0xB1 0xB2 0xB3 0xB4 0xB5 0xB6 0xB7 0xB8 0xB9 0xBA 0xBB 0xBC 0xBD 0xBE 0xBF )(list 0x2C0 0x2C4 0x2C8 0x2CC 0x2D0 0x2D4 0x2D8 0x2DC 0x2E0 0x2E4 0x2E8 0x2EC 0x2F0 0x2F4 0x2F8 0x2FC ) group.long ($2+0x400)++0x3 line.long 0x0 "REGG1_DOM_$1,Assign domain for CKGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xC0 0xC1 0xC2 0xC3 0xC4 0xC5 0xC6 0xC7 0xC8 0xC9 0xCA 0xCB 0xCC 0xCD 0xCE 0xCF )(list 0x300 0x304 0x308 0x30C 0x310 0x314 0x318 0x31C 0x320 0x324 0x328 0x32C 0x330 0x334 0x338 0x33C ) group.long ($2+0x400)++0x3 line.long 0x0 "REGG1_DOM_$1,Assign domain for CKGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xD0 0xD1 0xD2 0xD3 0xD4 0xD5 0xD6 0xD7 0xD8 0xD9 0xDA 0xDB 0xDC 0xDD 0xDE 0xDF )(list 0x340 0x344 0x348 0x34C 0x350 0x354 0x358 0x35C 0x360 0x364 0x368 0x36C 0x370 0x374 0x378 0x37C ) group.long ($2+0x400)++0x3 line.long 0x0 "REGG1_DOM_$1,Assign domain for CKGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xE0 0xE1 0xE2 0xE3 0xE4 0xE5 0xE6 0xE7 0xE8 0xE9 0xEA 0xEB 0xEC 0xED 0xEE 0xEF )(list 0x380 0x384 0x388 0x38C 0x390 0x394 0x398 0x39C 0x3A0 0x3A4 0x3A8 0x3AC 0x3B0 0x3B4 0x3B8 0x3BC ) group.long ($2+0x400)++0x3 line.long 0x0 "REGG1_DOM_$1,Assign domain for CKGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xF0 0xF1 0xF2 0xF3 0xF4 0xF5 0xF6 0xF7 0xF8 0xF9 0xFA 0xFB 0xFC 0xFD 0xFE 0xFF )(list 0x3C0 0x3C4 0x3C8 0x3CC 0x3D0 0x3D4 0x3D8 0x3DC 0x3E0 0x3E4 0x3E8 0x3EC 0x3F0 0x3F4 0x3F8 0x3FC ) group.long ($2+0x400)++0x3 line.long 0x0 "REGG1_DOM_$1,Assign domain for CKGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x4 0x8 0xC 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C ) group.long ($2+0x800)++0x3 line.long 0x0 "REGG2_DOM_$1,Assign domain for SCR registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1A 0x1B 0x1C 0x1D 0x1E 0x1F )(list 0x40 0x44 0x48 0x4C 0x50 0x54 0x58 0x5C 0x60 0x64 0x68 0x6C 0x70 0x74 0x78 0x7C ) group.long ($2+0x800)++0x3 line.long 0x0 "REGG2_DOM_$1,Assign domain for SCR registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x20 0x21 0x22 0x23 0x24 0x25 0x26 0x27 0x28 0x29 0x2A 0x2B 0x2C 0x2D 0x2E 0x2F )(list 0x80 0x84 0x88 0x8C 0x90 0x94 0x98 0x9C 0xA0 0xA4 0xA8 0xAC 0xB0 0xB4 0xB8 0xBC ) group.long ($2+0x800)++0x3 line.long 0x0 "REGG2_DOM_$1,Assign domain for SCR registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x30 0x31 0x32 0x33 0x34 0x35 0x36 0x37 0x38 0x39 0x3A 0x3B 0x3C 0x3D 0x3E 0x3F )(list 0xC0 0xC4 0xC8 0xCC 0xD0 0xD4 0xD8 0xDC 0xE0 0xE4 0xE8 0xEC 0xF0 0xF4 0xF8 0xFC ) group.long ($2+0x800)++0x3 line.long 0x0 "REGG2_DOM_$1,Assign domain for SCR registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x40 0x41 0x42 0x43 0x44 0x45 0x46 0x47 0x48 0x49 0x4A 0x4B 0x4C 0x4D 0x4E 0x4F )(list 0x100 0x104 0x108 0x10C 0x110 0x114 0x118 0x11C 0x120 0x124 0x128 0x12C 0x130 0x134 0x138 0x13C ) group.long ($2+0x800)++0x3 line.long 0x0 "REGG2_DOM_$1,Assign domain for SCR registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x50 0x51 0x52 0x53 0x54 0x55 0x56 0x57 0x58 0x59 0x5A 0x5B 0x5C 0x5D 0x5E 0x5F )(list 0x140 0x144 0x148 0x14C 0x150 0x154 0x158 0x15C 0x160 0x164 0x168 0x16C 0x170 0x174 0x178 0x17C ) group.long ($2+0x800)++0x3 line.long 0x0 "REGG2_DOM_$1,Assign domain for SCR registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x60 0x61 0x62 0x63 0x64 0x65 0x66 0x67 0x68 0x69 0x6A 0x6B 0x6C 0x6D 0x6E 0x6F )(list 0x180 0x184 0x188 0x18C 0x190 0x194 0x198 0x19C 0x1A0 0x1A4 0x1A8 0x1AC 0x1B0 0x1B4 0x1B8 0x1BC ) group.long ($2+0x800)++0x3 line.long 0x0 "REGG2_DOM_$1,Assign domain for SCR registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x70 0x71 0x72 0x73 0x74 0x75 0x76 0x77 0x78 0x79 0x7A 0x7B 0x7C 0x7D 0x7E 0x7F )(list 0x1C0 0x1C4 0x1C8 0x1CC 0x1D0 0x1D4 0x1D8 0x1DC 0x1E0 0x1E4 0x1E8 0x1EC 0x1F0 0x1F4 0x1F8 0x1FC ) group.long ($2+0x800)++0x3 line.long 0x0 "REGG2_DOM_$1,Assign domain for SCR registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x80 0x81 0x82 0x83 0x84 0x85 0x86 0x87 0x88 0x89 0x8A 0x8B 0x8C 0x8D 0x8E 0x8F )(list 0x200 0x204 0x208 0x20C 0x210 0x214 0x218 0x21C 0x220 0x224 0x228 0x22C 0x230 0x234 0x238 0x23C ) group.long ($2+0x800)++0x3 line.long 0x0 "REGG2_DOM_$1,Assign domain for SCR registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x90 0x91 0x92 0x93 0x94 0x95 0x96 0x97 0x98 0x99 0x9A 0x9B 0x9C 0x9D 0x9E 0x9F )(list 0x240 0x244 0x248 0x24C 0x250 0x254 0x258 0x25C 0x260 0x264 0x268 0x26C 0x270 0x274 0x278 0x27C ) group.long ($2+0x800)++0x3 line.long 0x0 "REGG2_DOM_$1,Assign domain for SCR registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xA0 0xA1 0xA2 0xA3 0xA4 0xA5 0xA6 0xA7 0xA8 0xA9 0xAA 0xAB 0xAC 0xAD 0xAE 0xAF )(list 0x280 0x284 0x288 0x28C 0x290 0x294 0x298 0x29C 0x2A0 0x2A4 0x2A8 0x2AC 0x2B0 0x2B4 0x2B8 0x2BC ) group.long ($2+0x800)++0x3 line.long 0x0 "REGG2_DOM_$1,Assign domain for SCR registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xB0 0xB1 0xB2 0xB3 0xB4 0xB5 0xB6 0xB7 0xB8 0xB9 0xBA 0xBB 0xBC 0xBD 0xBE 0xBF )(list 0x2C0 0x2C4 0x2C8 0x2CC 0x2D0 0x2D4 0x2D8 0x2DC 0x2E0 0x2E4 0x2E8 0x2EC 0x2F0 0x2F4 0x2F8 0x2FC ) group.long ($2+0x800)++0x3 line.long 0x0 "REGG2_DOM_$1,Assign domain for SCR registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xC0 0xC1 0xC2 0xC3 0xC4 0xC5 0xC6 0xC7 0xC8 0xC9 0xCA 0xCB 0xCC 0xCD 0xCE 0xCF )(list 0x300 0x304 0x308 0x30C 0x310 0x314 0x318 0x31C 0x320 0x324 0x328 0x32C 0x330 0x334 0x338 0x33C ) group.long ($2+0x800)++0x3 line.long 0x0 "REGG2_DOM_$1,Assign domain for SCR registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xD0 0xD1 0xD2 0xD3 0xD4 0xD5 0xD6 0xD7 0xD8 0xD9 0xDA 0xDB 0xDC 0xDD 0xDE 0xDF )(list 0x340 0x344 0x348 0x34C 0x350 0x354 0x358 0x35C 0x360 0x364 0x368 0x36C 0x370 0x374 0x378 0x37C ) group.long ($2+0x800)++0x3 line.long 0x0 "REGG2_DOM_$1,Assign domain for SCR registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xE0 0xE1 0xE2 0xE3 0xE4 0xE5 0xE6 0xE7 0xE8 0xE9 0xEA 0xEB 0xEC 0xED 0xEE 0xEF )(list 0x380 0x384 0x388 0x38C 0x390 0x394 0x398 0x39C 0x3A0 0x3A4 0x3A8 0x3AC 0x3B0 0x3B4 0x3B8 0x3BC ) group.long ($2+0x800)++0x3 line.long 0x0 "REGG2_DOM_$1,Assign domain for SCR registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xF0 0xF1 0xF2 0xF3 0xF4 0xF5 0xF6 0xF7 0xF8 0xF9 0xFA 0xFB 0xFC 0xFD 0xFE 0xFF )(list 0x3C0 0x3C4 0x3C8 0x3CC 0x3D0 0x3D4 0x3D8 0x3DC 0x3E0 0x3E4 0x3E8 0x3EC 0x3F0 0x3F4 0x3F8 0x3FC ) group.long ($2+0x800)++0x3 line.long 0x0 "REGG2_DOM_$1,Assign domain for SCR registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x4 0x8 0xC 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C ) group.long ($2+0xC00)++0x3 line.long 0x0 "REGG3_DOM_$1,Assign domain for SCR registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1A 0x1B 0x1C 0x1D 0x1E 0x1F )(list 0x40 0x44 0x48 0x4C 0x50 0x54 0x58 0x5C 0x60 0x64 0x68 0x6C 0x70 0x74 0x78 0x7C ) group.long ($2+0xC00)++0x3 line.long 0x0 "REGG3_DOM_$1,Assign domain for SCR registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x20 0x21 0x22 0x23 0x24 0x25 0x26 0x27 0x28 0x29 0x2A 0x2B 0x2C 0x2D 0x2E 0x2F )(list 0x80 0x84 0x88 0x8C 0x90 0x94 0x98 0x9C 0xA0 0xA4 0xA8 0xAC 0xB0 0xB4 0xB8 0xBC ) group.long ($2+0xC00)++0x3 line.long 0x0 "REGG3_DOM_$1,Assign domain for SCR registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x30 0x31 0x32 0x33 0x34 0x35 0x36 0x37 0x38 0x39 0x3A 0x3B 0x3C 0x3D 0x3E 0x3F )(list 0xC0 0xC4 0xC8 0xCC 0xD0 0xD4 0xD8 0xDC 0xE0 0xE4 0xE8 0xEC 0xF0 0xF4 0xF8 0xFC ) group.long ($2+0xC00)++0x3 line.long 0x0 "REGG3_DOM_$1,Assign domain for SCR registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x40 0x41 0x42 0x43 0x44 0x45 0x46 0x47 0x48 0x49 0x4A 0x4B 0x4C 0x4D 0x4E 0x4F )(list 0x100 0x104 0x108 0x10C 0x110 0x114 0x118 0x11C 0x120 0x124 0x128 0x12C 0x130 0x134 0x138 0x13C ) group.long ($2+0xC00)++0x3 line.long 0x0 "REGG3_DOM_$1,Assign domain for SCR registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x50 0x51 0x52 0x53 0x54 0x55 0x56 0x57 0x58 0x59 0x5A 0x5B 0x5C 0x5D 0x5E 0x5F )(list 0x140 0x144 0x148 0x14C 0x150 0x154 0x158 0x15C 0x160 0x164 0x168 0x16C 0x170 0x174 0x178 0x17C ) group.long ($2+0xC00)++0x3 line.long 0x0 "REGG3_DOM_$1,Assign domain for SCR registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x60 0x61 0x62 0x63 0x64 0x65 0x66 0x67 0x68 0x69 0x6A 0x6B 0x6C 0x6D 0x6E 0x6F )(list 0x180 0x184 0x188 0x18C 0x190 0x194 0x198 0x19C 0x1A0 0x1A4 0x1A8 0x1AC 0x1B0 0x1B4 0x1B8 0x1BC ) group.long ($2+0xC00)++0x3 line.long 0x0 "REGG3_DOM_$1,Assign domain for SCR registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x70 0x71 0x72 0x73 0x74 0x75 0x76 0x77 0x78 0x79 0x7A 0x7B 0x7C 0x7D 0x7E 0x7F )(list 0x1C0 0x1C4 0x1C8 0x1CC 0x1D0 0x1D4 0x1D8 0x1DC 0x1E0 0x1E4 0x1E8 0x1EC 0x1F0 0x1F4 0x1F8 0x1FC ) group.long ($2+0xC00)++0x3 line.long 0x0 "REGG3_DOM_$1,Assign domain for SCR registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x80 0x81 0x82 0x83 0x84 0x85 0x86 0x87 0x88 0x89 0x8A 0x8B 0x8C 0x8D 0x8E 0x8F )(list 0x200 0x204 0x208 0x20C 0x210 0x214 0x218 0x21C 0x220 0x224 0x228 0x22C 0x230 0x234 0x238 0x23C ) group.long ($2+0xC00)++0x3 line.long 0x0 "REGG3_DOM_$1,Assign domain for SCR registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x90 0x91 0x92 0x93 0x94 0x95 0x96 0x97 0x98 0x99 0x9A 0x9B 0x9C 0x9D 0x9E 0x9F )(list 0x240 0x244 0x248 0x24C 0x250 0x254 0x258 0x25C 0x260 0x264 0x268 0x26C 0x270 0x274 0x278 0x27C ) group.long ($2+0xC00)++0x3 line.long 0x0 "REGG3_DOM_$1,Assign domain for SCR registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xA0 0xA1 0xA2 0xA3 0xA4 0xA5 0xA6 0xA7 0xA8 0xA9 0xAA 0xAB 0xAC 0xAD 0xAE 0xAF )(list 0x280 0x284 0x288 0x28C 0x290 0x294 0x298 0x29C 0x2A0 0x2A4 0x2A8 0x2AC 0x2B0 0x2B4 0x2B8 0x2BC ) group.long ($2+0xC00)++0x3 line.long 0x0 "REGG3_DOM_$1,Assign domain for SCR registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xB0 0xB1 0xB2 0xB3 0xB4 0xB5 0xB6 0xB7 0xB8 0xB9 0xBA 0xBB 0xBC 0xBD 0xBE 0xBF )(list 0x2C0 0x2C4 0x2C8 0x2CC 0x2D0 0x2D4 0x2D8 0x2DC 0x2E0 0x2E4 0x2E8 0x2EC 0x2F0 0x2F4 0x2F8 0x2FC ) group.long ($2+0xC00)++0x3 line.long 0x0 "REGG3_DOM_$1,Assign domain for SCR registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xC0 0xC1 0xC2 0xC3 0xC4 0xC5 0xC6 0xC7 0xC8 0xC9 0xCA 0xCB 0xCC 0xCD 0xCE 0xCF )(list 0x300 0x304 0x308 0x30C 0x310 0x314 0x318 0x31C 0x320 0x324 0x328 0x32C 0x330 0x334 0x338 0x33C ) group.long ($2+0xC00)++0x3 line.long 0x0 "REGG3_DOM_$1,Assign domain for SCR registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xD0 0xD1 0xD2 0xD3 0xD4 0xD5 0xD6 0xD7 0xD8 0xD9 0xDA 0xDB 0xDC 0xDD 0xDE 0xDF )(list 0x340 0x344 0x348 0x34C 0x350 0x354 0x358 0x35C 0x360 0x364 0x368 0x36C 0x370 0x374 0x378 0x37C ) group.long ($2+0xC00)++0x3 line.long 0x0 "REGG3_DOM_$1,Assign domain for SCR registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xE0 0xE1 0xE2 0xE3 0xE4 0xE5 0xE6 0xE7 0xE8 0xE9 0xEA 0xEB 0xEC 0xED 0xEE 0xEF )(list 0x380 0x384 0x388 0x38C 0x390 0x394 0x398 0x39C 0x3A0 0x3A4 0x3A8 0x3AC 0x3B0 0x3B4 0x3B8 0x3BC ) group.long ($2+0xC00)++0x3 line.long 0x0 "REGG3_DOM_$1,Assign domain for SCR registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xF0 0xF1 0xF2 0xF3 0xF4 0xF5 0xF6 0xF7 0xF8 0xF9 0xFA 0xFB 0xFC 0xFD 0xFE 0xFF )(list 0x3C0 0x3C4 0x3C8 0x3CC 0x3D0 0x3D4 0x3D8 0x3DC 0x3E0 0x3E4 0x3E8 0x3EC 0x3F0 0x3F4 0x3F8 0x3FC ) group.long ($2+0xC00)++0x3 line.long 0x0 "REGG3_DOM_$1,Assign domain for SCR registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x4 0x8 0xC 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C ) group.long ($2+0x1000)++0x3 line.long 0x0 "REGG4_DOM_$1,Assign domain for RSTGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1A 0x1B 0x1C 0x1D 0x1E 0x1F )(list 0x40 0x44 0x48 0x4C 0x50 0x54 0x58 0x5C 0x60 0x64 0x68 0x6C 0x70 0x74 0x78 0x7C ) group.long ($2+0x1000)++0x3 line.long 0x0 "REGG4_DOM_$1,Assign domain for RSTGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x20 0x21 0x22 0x23 0x24 0x25 0x26 0x27 0x28 0x29 0x2A 0x2B 0x2C 0x2D 0x2E 0x2F )(list 0x80 0x84 0x88 0x8C 0x90 0x94 0x98 0x9C 0xA0 0xA4 0xA8 0xAC 0xB0 0xB4 0xB8 0xBC ) group.long ($2+0x1000)++0x3 line.long 0x0 "REGG4_DOM_$1,Assign domain for RSTGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x30 0x31 0x32 0x33 0x34 0x35 0x36 0x37 0x38 0x39 0x3A 0x3B 0x3C 0x3D 0x3E 0x3F )(list 0xC0 0xC4 0xC8 0xCC 0xD0 0xD4 0xD8 0xDC 0xE0 0xE4 0xE8 0xEC 0xF0 0xF4 0xF8 0xFC ) group.long ($2+0x1000)++0x3 line.long 0x0 "REGG4_DOM_$1,Assign domain for RSTGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x40 0x41 0x42 0x43 0x44 0x45 0x46 0x47 0x48 0x49 0x4A 0x4B 0x4C 0x4D 0x4E 0x4F )(list 0x100 0x104 0x108 0x10C 0x110 0x114 0x118 0x11C 0x120 0x124 0x128 0x12C 0x130 0x134 0x138 0x13C ) group.long ($2+0x1000)++0x3 line.long 0x0 "REGG4_DOM_$1,Assign domain for RSTGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x50 0x51 0x52 0x53 0x54 0x55 0x56 0x57 0x58 0x59 0x5A 0x5B 0x5C 0x5D 0x5E 0x5F )(list 0x140 0x144 0x148 0x14C 0x150 0x154 0x158 0x15C 0x160 0x164 0x168 0x16C 0x170 0x174 0x178 0x17C ) group.long ($2+0x1000)++0x3 line.long 0x0 "REGG4_DOM_$1,Assign domain for RSTGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x60 0x61 0x62 0x63 0x64 0x65 0x66 0x67 0x68 0x69 0x6A 0x6B 0x6C 0x6D 0x6E 0x6F )(list 0x180 0x184 0x188 0x18C 0x190 0x194 0x198 0x19C 0x1A0 0x1A4 0x1A8 0x1AC 0x1B0 0x1B4 0x1B8 0x1BC ) group.long ($2+0x1000)++0x3 line.long 0x0 "REGG4_DOM_$1,Assign domain for RSTGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x70 0x71 0x72 0x73 0x74 0x75 0x76 0x77 0x78 0x79 0x7A 0x7B 0x7C 0x7D 0x7E 0x7F )(list 0x1C0 0x1C4 0x1C8 0x1CC 0x1D0 0x1D4 0x1D8 0x1DC 0x1E0 0x1E4 0x1E8 0x1EC 0x1F0 0x1F4 0x1F8 0x1FC ) group.long ($2+0x1000)++0x3 line.long 0x0 "REGG4_DOM_$1,Assign domain for RSTGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x80 0x81 0x82 0x83 0x84 0x85 0x86 0x87 0x88 0x89 0x8A 0x8B 0x8C 0x8D 0x8E 0x8F )(list 0x200 0x204 0x208 0x20C 0x210 0x214 0x218 0x21C 0x220 0x224 0x228 0x22C 0x230 0x234 0x238 0x23C ) group.long ($2+0x1000)++0x3 line.long 0x0 "REGG4_DOM_$1,Assign domain for RSTGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x90 0x91 0x92 0x93 0x94 0x95 0x96 0x97 0x98 0x99 0x9A 0x9B 0x9C 0x9D 0x9E 0x9F )(list 0x240 0x244 0x248 0x24C 0x250 0x254 0x258 0x25C 0x260 0x264 0x268 0x26C 0x270 0x274 0x278 0x27C ) group.long ($2+0x1000)++0x3 line.long 0x0 "REGG4_DOM_$1,Assign domain for RSTGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xA0 0xA1 0xA2 0xA3 0xA4 0xA5 0xA6 0xA7 0xA8 0xA9 0xAA 0xAB 0xAC 0xAD 0xAE 0xAF )(list 0x280 0x284 0x288 0x28C 0x290 0x294 0x298 0x29C 0x2A0 0x2A4 0x2A8 0x2AC 0x2B0 0x2B4 0x2B8 0x2BC ) group.long ($2+0x1000)++0x3 line.long 0x0 "REGG4_DOM_$1,Assign domain for RSTGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xB0 0xB1 0xB2 0xB3 0xB4 0xB5 0xB6 0xB7 0xB8 0xB9 0xBA 0xBB 0xBC 0xBD 0xBE 0xBF )(list 0x2C0 0x2C4 0x2C8 0x2CC 0x2D0 0x2D4 0x2D8 0x2DC 0x2E0 0x2E4 0x2E8 0x2EC 0x2F0 0x2F4 0x2F8 0x2FC ) group.long ($2+0x1000)++0x3 line.long 0x0 "REGG4_DOM_$1,Assign domain for RSTGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xC0 0xC1 0xC2 0xC3 0xC4 0xC5 0xC6 0xC7 0xC8 0xC9 0xCA 0xCB 0xCC 0xCD 0xCE 0xCF )(list 0x300 0x304 0x308 0x30C 0x310 0x314 0x318 0x31C 0x320 0x324 0x328 0x32C 0x330 0x334 0x338 0x33C ) group.long ($2+0x1000)++0x3 line.long 0x0 "REGG4_DOM_$1,Assign domain for RSTGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xD0 0xD1 0xD2 0xD3 0xD4 0xD5 0xD6 0xD7 0xD8 0xD9 0xDA 0xDB 0xDC 0xDD 0xDE 0xDF )(list 0x340 0x344 0x348 0x34C 0x350 0x354 0x358 0x35C 0x360 0x364 0x368 0x36C 0x370 0x374 0x378 0x37C ) group.long ($2+0x1000)++0x3 line.long 0x0 "REGG4_DOM_$1,Assign domain for RSTGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xE0 0xE1 0xE2 0xE3 0xE4 0xE5 0xE6 0xE7 0xE8 0xE9 0xEA 0xEB 0xEC 0xED 0xEE 0xEF )(list 0x380 0x384 0x388 0x38C 0x390 0x394 0x398 0x39C 0x3A0 0x3A4 0x3A8 0x3AC 0x3B0 0x3B4 0x3B8 0x3BC ) group.long ($2+0x1000)++0x3 line.long 0x0 "REGG4_DOM_$1,Assign domain for RSTGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xF0 0xF1 0xF2 0xF3 0xF4 0xF5 0xF6 0xF7 0xF8 0xF9 0xFA 0xFB 0xFC 0xFD 0xFE 0xFF )(list 0x3C0 0x3C4 0x3C8 0x3CC 0x3D0 0x3D4 0x3D8 0x3DC 0x3E0 0x3E4 0x3E8 0x3EC 0x3F0 0x3F4 0x3F8 0x3FC ) group.long ($2+0x1000)++0x3 line.long 0x0 "REGG4_DOM_$1,Assign domain for RSTGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x4 0x8 0xC 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C ) group.long ($2+0x1400)++0x3 line.long 0x0 "REGG5_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1A 0x1B 0x1C 0x1D 0x1E 0x1F )(list 0x40 0x44 0x48 0x4C 0x50 0x54 0x58 0x5C 0x60 0x64 0x68 0x6C 0x70 0x74 0x78 0x7C ) group.long ($2+0x1400)++0x3 line.long 0x0 "REGG5_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x20 0x21 0x22 0x23 0x24 0x25 0x26 0x27 0x28 0x29 0x2A 0x2B 0x2C 0x2D 0x2E 0x2F )(list 0x80 0x84 0x88 0x8C 0x90 0x94 0x98 0x9C 0xA0 0xA4 0xA8 0xAC 0xB0 0xB4 0xB8 0xBC ) group.long ($2+0x1400)++0x3 line.long 0x0 "REGG5_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x30 0x31 0x32 0x33 0x34 0x35 0x36 0x37 0x38 0x39 0x3A 0x3B 0x3C 0x3D 0x3E 0x3F )(list 0xC0 0xC4 0xC8 0xCC 0xD0 0xD4 0xD8 0xDC 0xE0 0xE4 0xE8 0xEC 0xF0 0xF4 0xF8 0xFC ) group.long ($2+0x1400)++0x3 line.long 0x0 "REGG5_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x40 0x41 0x42 0x43 0x44 0x45 0x46 0x47 0x48 0x49 0x4A 0x4B 0x4C 0x4D 0x4E 0x4F )(list 0x100 0x104 0x108 0x10C 0x110 0x114 0x118 0x11C 0x120 0x124 0x128 0x12C 0x130 0x134 0x138 0x13C ) group.long ($2+0x1400)++0x3 line.long 0x0 "REGG5_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x50 0x51 0x52 0x53 0x54 0x55 0x56 0x57 0x58 0x59 0x5A 0x5B 0x5C 0x5D 0x5E 0x5F )(list 0x140 0x144 0x148 0x14C 0x150 0x154 0x158 0x15C 0x160 0x164 0x168 0x16C 0x170 0x174 0x178 0x17C ) group.long ($2+0x1400)++0x3 line.long 0x0 "REGG5_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x60 0x61 0x62 0x63 0x64 0x65 0x66 0x67 0x68 0x69 0x6A 0x6B 0x6C 0x6D 0x6E 0x6F )(list 0x180 0x184 0x188 0x18C 0x190 0x194 0x198 0x19C 0x1A0 0x1A4 0x1A8 0x1AC 0x1B0 0x1B4 0x1B8 0x1BC ) group.long ($2+0x1400)++0x3 line.long 0x0 "REGG5_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x70 0x71 0x72 0x73 0x74 0x75 0x76 0x77 0x78 0x79 0x7A 0x7B 0x7C 0x7D 0x7E 0x7F )(list 0x1C0 0x1C4 0x1C8 0x1CC 0x1D0 0x1D4 0x1D8 0x1DC 0x1E0 0x1E4 0x1E8 0x1EC 0x1F0 0x1F4 0x1F8 0x1FC ) group.long ($2+0x1400)++0x3 line.long 0x0 "REGG5_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x80 0x81 0x82 0x83 0x84 0x85 0x86 0x87 0x88 0x89 0x8A 0x8B 0x8C 0x8D 0x8E 0x8F )(list 0x200 0x204 0x208 0x20C 0x210 0x214 0x218 0x21C 0x220 0x224 0x228 0x22C 0x230 0x234 0x238 0x23C ) group.long ($2+0x1400)++0x3 line.long 0x0 "REGG5_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x90 0x91 0x92 0x93 0x94 0x95 0x96 0x97 0x98 0x99 0x9A 0x9B 0x9C 0x9D 0x9E 0x9F )(list 0x240 0x244 0x248 0x24C 0x250 0x254 0x258 0x25C 0x260 0x264 0x268 0x26C 0x270 0x274 0x278 0x27C ) group.long ($2+0x1400)++0x3 line.long 0x0 "REGG5_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xA0 0xA1 0xA2 0xA3 0xA4 0xA5 0xA6 0xA7 0xA8 0xA9 0xAA 0xAB 0xAC 0xAD 0xAE 0xAF )(list 0x280 0x284 0x288 0x28C 0x290 0x294 0x298 0x29C 0x2A0 0x2A4 0x2A8 0x2AC 0x2B0 0x2B4 0x2B8 0x2BC ) group.long ($2+0x1400)++0x3 line.long 0x0 "REGG5_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xB0 0xB1 0xB2 0xB3 0xB4 0xB5 0xB6 0xB7 0xB8 0xB9 0xBA 0xBB 0xBC 0xBD 0xBE 0xBF )(list 0x2C0 0x2C4 0x2C8 0x2CC 0x2D0 0x2D4 0x2D8 0x2DC 0x2E0 0x2E4 0x2E8 0x2EC 0x2F0 0x2F4 0x2F8 0x2FC ) group.long ($2+0x1400)++0x3 line.long 0x0 "REGG5_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xC0 0xC1 0xC2 0xC3 0xC4 0xC5 0xC6 0xC7 0xC8 0xC9 0xCA 0xCB 0xCC 0xCD 0xCE 0xCF )(list 0x300 0x304 0x308 0x30C 0x310 0x314 0x318 0x31C 0x320 0x324 0x328 0x32C 0x330 0x334 0x338 0x33C ) group.long ($2+0x1400)++0x3 line.long 0x0 "REGG5_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xD0 0xD1 0xD2 0xD3 0xD4 0xD5 0xD6 0xD7 0xD8 0xD9 0xDA 0xDB 0xDC 0xDD 0xDE 0xDF )(list 0x340 0x344 0x348 0x34C 0x350 0x354 0x358 0x35C 0x360 0x364 0x368 0x36C 0x370 0x374 0x378 0x37C ) group.long ($2+0x1400)++0x3 line.long 0x0 "REGG5_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xE0 0xE1 0xE2 0xE3 0xE4 0xE5 0xE6 0xE7 0xE8 0xE9 0xEA 0xEB 0xEC 0xED 0xEE 0xEF )(list 0x380 0x384 0x388 0x38C 0x390 0x394 0x398 0x39C 0x3A0 0x3A4 0x3A8 0x3AC 0x3B0 0x3B4 0x3B8 0x3BC ) group.long ($2+0x1400)++0x3 line.long 0x0 "REGG5_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xF0 0xF1 0xF2 0xF3 0xF4 0xF5 0xF6 0xF7 0xF8 0xF9 0xFA 0xFB 0xFC 0xFD 0xFE 0xFF )(list 0x3C0 0x3C4 0x3C8 0x3CC 0x3D0 0x3D4 0x3D8 0x3DC 0x3E0 0x3E4 0x3E8 0x3EC 0x3F0 0x3F4 0x3F8 0x3FC ) group.long ($2+0x1400)++0x3 line.long 0x0 "REGG5_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x4 0x8 0xC 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C ) group.long ($2+0x1800)++0x3 line.long 0x0 "REGG6_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1A 0x1B 0x1C 0x1D 0x1E 0x1F )(list 0x40 0x44 0x48 0x4C 0x50 0x54 0x58 0x5C 0x60 0x64 0x68 0x6C 0x70 0x74 0x78 0x7C ) group.long ($2+0x1800)++0x3 line.long 0x0 "REGG6_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x20 0x21 0x22 0x23 0x24 0x25 0x26 0x27 0x28 0x29 0x2A 0x2B 0x2C 0x2D 0x2E 0x2F )(list 0x80 0x84 0x88 0x8C 0x90 0x94 0x98 0x9C 0xA0 0xA4 0xA8 0xAC 0xB0 0xB4 0xB8 0xBC ) group.long ($2+0x1800)++0x3 line.long 0x0 "REGG6_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x30 0x31 0x32 0x33 0x34 0x35 0x36 0x37 0x38 0x39 0x3A 0x3B 0x3C 0x3D 0x3E 0x3F )(list 0xC0 0xC4 0xC8 0xCC 0xD0 0xD4 0xD8 0xDC 0xE0 0xE4 0xE8 0xEC 0xF0 0xF4 0xF8 0xFC ) group.long ($2+0x1800)++0x3 line.long 0x0 "REGG6_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x40 0x41 0x42 0x43 0x44 0x45 0x46 0x47 0x48 0x49 0x4A 0x4B 0x4C 0x4D 0x4E 0x4F )(list 0x100 0x104 0x108 0x10C 0x110 0x114 0x118 0x11C 0x120 0x124 0x128 0x12C 0x130 0x134 0x138 0x13C ) group.long ($2+0x1800)++0x3 line.long 0x0 "REGG6_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x50 0x51 0x52 0x53 0x54 0x55 0x56 0x57 0x58 0x59 0x5A 0x5B 0x5C 0x5D 0x5E 0x5F )(list 0x140 0x144 0x148 0x14C 0x150 0x154 0x158 0x15C 0x160 0x164 0x168 0x16C 0x170 0x174 0x178 0x17C ) group.long ($2+0x1800)++0x3 line.long 0x0 "REGG6_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x60 0x61 0x62 0x63 0x64 0x65 0x66 0x67 0x68 0x69 0x6A 0x6B 0x6C 0x6D 0x6E 0x6F )(list 0x180 0x184 0x188 0x18C 0x190 0x194 0x198 0x19C 0x1A0 0x1A4 0x1A8 0x1AC 0x1B0 0x1B4 0x1B8 0x1BC ) group.long ($2+0x1800)++0x3 line.long 0x0 "REGG6_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x70 0x71 0x72 0x73 0x74 0x75 0x76 0x77 0x78 0x79 0x7A 0x7B 0x7C 0x7D 0x7E 0x7F )(list 0x1C0 0x1C4 0x1C8 0x1CC 0x1D0 0x1D4 0x1D8 0x1DC 0x1E0 0x1E4 0x1E8 0x1EC 0x1F0 0x1F4 0x1F8 0x1FC ) group.long ($2+0x1800)++0x3 line.long 0x0 "REGG6_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x80 0x81 0x82 0x83 0x84 0x85 0x86 0x87 0x88 0x89 0x8A 0x8B 0x8C 0x8D 0x8E 0x8F )(list 0x200 0x204 0x208 0x20C 0x210 0x214 0x218 0x21C 0x220 0x224 0x228 0x22C 0x230 0x234 0x238 0x23C ) group.long ($2+0x1800)++0x3 line.long 0x0 "REGG6_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x90 0x91 0x92 0x93 0x94 0x95 0x96 0x97 0x98 0x99 0x9A 0x9B 0x9C 0x9D 0x9E 0x9F )(list 0x240 0x244 0x248 0x24C 0x250 0x254 0x258 0x25C 0x260 0x264 0x268 0x26C 0x270 0x274 0x278 0x27C ) group.long ($2+0x1800)++0x3 line.long 0x0 "REGG6_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xA0 0xA1 0xA2 0xA3 0xA4 0xA5 0xA6 0xA7 0xA8 0xA9 0xAA 0xAB 0xAC 0xAD 0xAE 0xAF )(list 0x280 0x284 0x288 0x28C 0x290 0x294 0x298 0x29C 0x2A0 0x2A4 0x2A8 0x2AC 0x2B0 0x2B4 0x2B8 0x2BC ) group.long ($2+0x1800)++0x3 line.long 0x0 "REGG6_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xB0 0xB1 0xB2 0xB3 0xB4 0xB5 0xB6 0xB7 0xB8 0xB9 0xBA 0xBB 0xBC 0xBD 0xBE 0xBF )(list 0x2C0 0x2C4 0x2C8 0x2CC 0x2D0 0x2D4 0x2D8 0x2DC 0x2E0 0x2E4 0x2E8 0x2EC 0x2F0 0x2F4 0x2F8 0x2FC ) group.long ($2+0x1800)++0x3 line.long 0x0 "REGG6_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xC0 0xC1 0xC2 0xC3 0xC4 0xC5 0xC6 0xC7 0xC8 0xC9 0xCA 0xCB 0xCC 0xCD 0xCE 0xCF )(list 0x300 0x304 0x308 0x30C 0x310 0x314 0x318 0x31C 0x320 0x324 0x328 0x32C 0x330 0x334 0x338 0x33C ) group.long ($2+0x1800)++0x3 line.long 0x0 "REGG6_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xD0 0xD1 0xD2 0xD3 0xD4 0xD5 0xD6 0xD7 0xD8 0xD9 0xDA 0xDB 0xDC 0xDD 0xDE 0xDF )(list 0x340 0x344 0x348 0x34C 0x350 0x354 0x358 0x35C 0x360 0x364 0x368 0x36C 0x370 0x374 0x378 0x37C ) group.long ($2+0x1800)++0x3 line.long 0x0 "REGG6_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xE0 0xE1 0xE2 0xE3 0xE4 0xE5 0xE6 0xE7 0xE8 0xE9 0xEA 0xEB 0xEC 0xED 0xEE 0xEF )(list 0x380 0x384 0x388 0x38C 0x390 0x394 0x398 0x39C 0x3A0 0x3A4 0x3A8 0x3AC 0x3B0 0x3B4 0x3B8 0x3BC ) group.long ($2+0x1800)++0x3 line.long 0x0 "REGG6_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xF0 0xF1 0xF2 0xF3 0xF4 0xF5 0xF6 0xF7 0xF8 0xF9 0xFA 0xFB 0xFC 0xFD 0xFE 0xFF )(list 0x3C0 0x3C4 0x3C8 0x3CC 0x3D0 0x3D4 0x3D8 0x3DC 0x3E0 0x3E4 0x3E8 0x3EC 0x3F0 0x3F4 0x3F8 0x3FC ) group.long ($2+0x1800)++0x3 line.long 0x0 "REGG6_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x4 0x8 0xC 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C ) group.long ($2+0x1C00)++0x3 line.long 0x0 "REGG7_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1A 0x1B 0x1C 0x1D 0x1E 0x1F )(list 0x40 0x44 0x48 0x4C 0x50 0x54 0x58 0x5C 0x60 0x64 0x68 0x6C 0x70 0x74 0x78 0x7C ) group.long ($2+0x1C00)++0x3 line.long 0x0 "REGG7_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x20 0x21 0x22 0x23 0x24 0x25 0x26 0x27 0x28 0x29 0x2A 0x2B 0x2C 0x2D 0x2E 0x2F )(list 0x80 0x84 0x88 0x8C 0x90 0x94 0x98 0x9C 0xA0 0xA4 0xA8 0xAC 0xB0 0xB4 0xB8 0xBC ) group.long ($2+0x1C00)++0x3 line.long 0x0 "REGG7_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x30 0x31 0x32 0x33 0x34 0x35 0x36 0x37 0x38 0x39 0x3A 0x3B 0x3C 0x3D 0x3E 0x3F )(list 0xC0 0xC4 0xC8 0xCC 0xD0 0xD4 0xD8 0xDC 0xE0 0xE4 0xE8 0xEC 0xF0 0xF4 0xF8 0xFC ) group.long ($2+0x1C00)++0x3 line.long 0x0 "REGG7_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x40 0x41 0x42 0x43 0x44 0x45 0x46 0x47 0x48 0x49 0x4A 0x4B 0x4C 0x4D 0x4E 0x4F )(list 0x100 0x104 0x108 0x10C 0x110 0x114 0x118 0x11C 0x120 0x124 0x128 0x12C 0x130 0x134 0x138 0x13C ) group.long ($2+0x1C00)++0x3 line.long 0x0 "REGG7_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x50 0x51 0x52 0x53 0x54 0x55 0x56 0x57 0x58 0x59 0x5A 0x5B 0x5C 0x5D 0x5E 0x5F )(list 0x140 0x144 0x148 0x14C 0x150 0x154 0x158 0x15C 0x160 0x164 0x168 0x16C 0x170 0x174 0x178 0x17C ) group.long ($2+0x1C00)++0x3 line.long 0x0 "REGG7_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x60 0x61 0x62 0x63 0x64 0x65 0x66 0x67 0x68 0x69 0x6A 0x6B 0x6C 0x6D 0x6E 0x6F )(list 0x180 0x184 0x188 0x18C 0x190 0x194 0x198 0x19C 0x1A0 0x1A4 0x1A8 0x1AC 0x1B0 0x1B4 0x1B8 0x1BC ) group.long ($2+0x1C00)++0x3 line.long 0x0 "REGG7_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x70 0x71 0x72 0x73 0x74 0x75 0x76 0x77 0x78 0x79 0x7A 0x7B 0x7C 0x7D 0x7E 0x7F )(list 0x1C0 0x1C4 0x1C8 0x1CC 0x1D0 0x1D4 0x1D8 0x1DC 0x1E0 0x1E4 0x1E8 0x1EC 0x1F0 0x1F4 0x1F8 0x1FC ) group.long ($2+0x1C00)++0x3 line.long 0x0 "REGG7_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x80 0x81 0x82 0x83 0x84 0x85 0x86 0x87 0x88 0x89 0x8A 0x8B 0x8C 0x8D 0x8E 0x8F )(list 0x200 0x204 0x208 0x20C 0x210 0x214 0x218 0x21C 0x220 0x224 0x228 0x22C 0x230 0x234 0x238 0x23C ) group.long ($2+0x1C00)++0x3 line.long 0x0 "REGG7_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x90 0x91 0x92 0x93 0x94 0x95 0x96 0x97 0x98 0x99 0x9A 0x9B 0x9C 0x9D 0x9E 0x9F )(list 0x240 0x244 0x248 0x24C 0x250 0x254 0x258 0x25C 0x260 0x264 0x268 0x26C 0x270 0x274 0x278 0x27C ) group.long ($2+0x1C00)++0x3 line.long 0x0 "REGG7_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xA0 0xA1 0xA2 0xA3 0xA4 0xA5 0xA6 0xA7 0xA8 0xA9 0xAA 0xAB 0xAC 0xAD 0xAE 0xAF )(list 0x280 0x284 0x288 0x28C 0x290 0x294 0x298 0x29C 0x2A0 0x2A4 0x2A8 0x2AC 0x2B0 0x2B4 0x2B8 0x2BC ) group.long ($2+0x1C00)++0x3 line.long 0x0 "REGG7_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xB0 0xB1 0xB2 0xB3 0xB4 0xB5 0xB6 0xB7 0xB8 0xB9 0xBA 0xBB 0xBC 0xBD 0xBE 0xBF )(list 0x2C0 0x2C4 0x2C8 0x2CC 0x2D0 0x2D4 0x2D8 0x2DC 0x2E0 0x2E4 0x2E8 0x2EC 0x2F0 0x2F4 0x2F8 0x2FC ) group.long ($2+0x1C00)++0x3 line.long 0x0 "REGG7_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xC0 0xC1 0xC2 0xC3 0xC4 0xC5 0xC6 0xC7 0xC8 0xC9 0xCA 0xCB 0xCC 0xCD 0xCE 0xCF )(list 0x300 0x304 0x308 0x30C 0x310 0x314 0x318 0x31C 0x320 0x324 0x328 0x32C 0x330 0x334 0x338 0x33C ) group.long ($2+0x1C00)++0x3 line.long 0x0 "REGG7_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xD0 0xD1 0xD2 0xD3 0xD4 0xD5 0xD6 0xD7 0xD8 0xD9 0xDA 0xDB 0xDC 0xDD 0xDE 0xDF )(list 0x340 0x344 0x348 0x34C 0x350 0x354 0x358 0x35C 0x360 0x364 0x368 0x36C 0x370 0x374 0x378 0x37C ) group.long ($2+0x1C00)++0x3 line.long 0x0 "REGG7_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xE0 0xE1 0xE2 0xE3 0xE4 0xE5 0xE6 0xE7 0xE8 0xE9 0xEA 0xEB 0xEC 0xED 0xEE 0xEF )(list 0x380 0x384 0x388 0x38C 0x390 0x394 0x398 0x39C 0x3A0 0x3A4 0x3A8 0x3AC 0x3B0 0x3B4 0x3B8 0x3BC ) group.long ($2+0x1C00)++0x3 line.long 0x0 "REGG7_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xF0 0xF1 0xF2 0xF3 0xF4 0xF5 0xF6 0xF7 0xF8 0xF9 0xFA 0xFB 0xFC 0xFD 0xFE 0xFF )(list 0x3C0 0x3C4 0x3C8 0x3CC 0x3D0 0x3D4 0x3D8 0x3DC 0x3E0 0x3E4 0x3E8 0x3EC 0x3F0 0x3F4 0x3F8 0x3FC ) group.long ($2+0x1C00)++0x3 line.long 0x0 "REGG7_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end group.long 0x2000++0x17 line.long 0x0 "GLB_CTL,This register provides global enable settings for permission control." bitfld.long 0x0 5. "DOM_CFG_LOCK,Lock write for DOM_CFG_MODE bit." "0,1" bitfld.long 0x0 4. "DOM_CFG_MODE,When enabled all the source setting can be configured by master from domain 0 if it is not locked. When disabled only resource manager can configure the permission of the resource." "0,1" bitfld.long 0x0 3. "PERCK_DIS_LOCK,Lock write for PERCK_DIS" "0,1" bitfld.long 0x0 2. "PERCK_DIS,All the permission check disable." "0,1" newline bitfld.long 0x0 1. "DOM_PRO_LOCK,Lock write for DOM_PRO_EN bit." "0,1" bitfld.long 0x0 0. "DOM_PRO_EN,When disabled no domain access permission check" "0,1" line.long 0x4 "RES_MGR,Resource manager register. This regster is used to assign resource manager for global resource access control" bitfld.long 0x4 17. "MID_LOCK,Lock write for MID_EN and MID_LOW and MID_HIG registers." "0,1" bitfld.long 0x4 16. "MID_EN,Master ID check enable" "0,1" bitfld.long 0x4 15. "PRI_PER_LOCK,Lock write for PRI_PER and PRI_PER_EN" "0,1" bitfld.long 0x4 13.--14. "PRI_PER,Resource manager privileged access permission. bit0 for privileged access bit1 for user access" "0,1,2,3" newline bitfld.long 0x4 12. "PRI_PER_EN,Resource manager privileged access permission enable." "0,1" bitfld.long 0x4 11. "SEC_PER_LOCK,Lock for SEC_PER and SEC_PER_LOCK" "0,1" bitfld.long 0x4 9.--10. "SEC_PER,Resource manager secure access permission. bit 0 for secure access bit 1 for non-secure access" "0,1,2,3" bitfld.long 0x4 8. "SEC_PER_EN,Resource manager secure permission enable" "0,1" bitfld.long 0x4 7. "DID_LOCK,Lock write for DID_EN and DID" "0,1" newline hexmask.long.byte 0x4 3.--6. 1. "DID,Resource manager domain ID" bitfld.long 0x4 2. "DID_EN,Resource manager Domain ID enable" "0,1" bitfld.long 0x4 1. "RES_MGR_EN_LOCK,Lock for RES_MGR_EN" "0,1" bitfld.long 0x4 0. "RES_MGR_EN,Resource manager enable. When the bit is disable there is no resource manager." "0,1" line.long 0x8 "RES_MGR_MA0,This register is used to assign master 0~31 as resource manager." hexmask.long 0x8 0.--31. 1. "MID,Assign master 0~31 for resource manager" line.long 0xC "RES_MGR_MA1,This register is used to assign master 32~63 as resource manager." hexmask.long 0xC 0.--31. 1. "MID,Indicate if master 32~63 is resource manager." line.long 0x10 "RES_MGR_MA2,This register is used to assign master 64~95 as resource manager." hexmask.long 0x10 0.--31. 1. "MID,Indicate if master 64~95 is resource manager." line.long 0x14 "RES_MGR_MA3,This register is used to assign master 96~127 as resource manager." hexmask.long 0x14 0.--31. 1. "MID,Indicate if master 96~127 is resource manager." repeat 8. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 )(list 0x0 0x14 0x28 0x3C 0x50 0x64 0x78 0x8C ) group.long ($2+0x2100)++0x3 line.long 0x0 "GRP_MGR_$1,Group Manager Register. This register is used to assign group manager for each domain" bitfld.long 0x0 17. "MID_LOCK,Lock write for MID_EN and MID_LOW and MID_HIG registers." "0,1" bitfld.long 0x0 16. "MID_EN,Master ID check enable" "0,1" bitfld.long 0x0 15. "PRI_PER_LOCK,Lock write for PRI_PER and PRI_PER_EN" "0,1" bitfld.long 0x0 13.--14. "PRI_PER,Group manager privileged access permission. bit0 for privileged access bit1 for user access" "0,1,2,3" newline bitfld.long 0x0 12. "PRI_PER_EN,Group manager privileged access permission enable." "0,1" bitfld.long 0x0 11. "SEC_PER_LOCK,Lock for SEC_PER and SEC_PER_LOCK" "0,1" bitfld.long 0x0 9.--10. "SEC_PER,Group manager secure access permission. bit 0 for secure access bit 1 for non-secure access" "0,1,2,3" bitfld.long 0x0 8. "SEC_PER_EN,Group manager secure permission enable" "0,1" bitfld.long 0x0 7. "DID_LOCK,Lock write for DID_EN and DID" "0,1" newline hexmask.long.byte 0x0 3.--6. 1. "DID,Group manager domain ID" bitfld.long 0x0 2. "DID_EN,Group manager Domain ID enable" "0,1" bitfld.long 0x0 1. "GRP_MGR_EN_LOCK,Lock write for GPR_MGR_EN" "0,1" bitfld.long 0x0 0. "GRP_MGR_EN,Group manager enable. When the bit is disable there is no resource manager." "0,1" repeat.end repeat 8. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 )(list 0x0 0x14 0x28 0x3C 0x50 0x64 0x78 0x8C ) group.long ($2+0x2104)++0x3 line.long 0x0 "GRP_MGR_MA0_$1,Assign master 0~31 for group manager 0" hexmask.long 0x0 0.--31. 1. "MID,Assign master 0~31 for resource manager" repeat.end repeat 8. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 )(list 0x0 0x14 0x28 0x3C 0x50 0x64 0x78 0x8C ) group.long ($2+0x2108)++0x3 line.long 0x0 "GRP_MGR_MA1_$1,Assign master 32~63 for group manager 0" hexmask.long 0x0 0.--31. 1. "MID,Indicate if master 32~63 is resource manager." repeat.end repeat 8. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 )(list 0x0 0x14 0x28 0x3C 0x50 0x64 0x78 0x8C ) group.long ($2+0x210C)++0x3 line.long 0x0 "GRP_MGR_MA2_$1,Assign master 64~95 for group manager 0" hexmask.long 0x0 0.--31. 1. "MID,Indicate if master 64~95 is resource manager." repeat.end repeat 8. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 )(list 0x0 0x14 0x28 0x3C 0x50 0x64 0x78 0x8C ) group.long ($2+0x2110)++0x3 line.long 0x0 "GRP_MGR_MA3_$1,Assign master 96~127 for group manager 0" hexmask.long 0x0 0.--31. 1. "MID,Indicate if master 96~127 is resource manager." repeat.end group.long 0x2200++0x3 line.long 0x0 "DOM_GID_0,Indicate which group domain 0 belong to" bitfld.long 0x0 3. "LOCK,Lock write for GID" "0,1" bitfld.long 0x0 0.--2. "GID,Group ID" "0,1,2,3,4,5,6,7" repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x18 0x30 0x48 0x60 0x78 0x90 0xA8 0xC0 0xD8 0xF0 0x108 0x120 0x138 0x150 0x168 ) group.long ($2+0x2204)++0x3 line.long 0x0 "DOM_OWN_$1,Assign owner for function domain 0." bitfld.long 0x0 17. "MID_LOCK,Lock write for MID_EN and MID_LOW and MID_HIG registers." "0,1" bitfld.long 0x0 16. "MID_EN,Master ID check enable" "0,1" bitfld.long 0x0 15. "PRI_PER_LOCK,Lock write for PRI_PER and PRI_PER_EN" "0,1" bitfld.long 0x0 13.--14. "PRI_PER,Group manager privileged access permission. bit0 for privileged access bit1 for user access" "0,1,2,3" newline bitfld.long 0x0 12. "PRI_PER_EN,Group manager privileged access permission enable." "0,1" bitfld.long 0x0 11. "SEC_PER_LOCK,Lock for SEC_PER and SEC_PER_LOCK" "0,1" bitfld.long 0x0 9.--10. "SEC_PER,Domain owner secure access permission. bit 0 for secure access bit 1 for non-secure access" "0,1,2,3" bitfld.long 0x0 8. "SEC_PER_EN,Domain owner secure permission enable" "0,1" newline bitfld.long 0x0 1. "DOM_OWN_EN_LOCK,Lock for DOM_OWN_EN" "0,1" bitfld.long 0x0 0. "DOM_OWN_EN,Domain owner enable. When the bit is disable there is no domain owner." "0,1" repeat.end repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x18 0x30 0x48 0x60 0x78 0x90 0xA8 0xC0 0xD8 0xF0 0x108 0x120 0x138 0x150 0x168 ) group.long ($2+0x2208)++0x3 line.long 0x0 "DOM_OWN_MA0_$1,Assign master 0~31 for domain owner 0" hexmask.long 0x0 0.--31. 1. "MID,Assign master 0~31 for resource manager" repeat.end repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x18 0x30 0x48 0x60 0x78 0x90 0xA8 0xC0 0xD8 0xF0 0x108 0x120 0x138 0x150 0x168 ) group.long ($2+0x220C)++0x3 line.long 0x0 "DOM_OWN_MA1_$1,Assign master 32~63 for domain owner 0" hexmask.long 0x0 0.--31. 1. "MID,Indicate if master 32~63 is resource manager." repeat.end repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x18 0x30 0x48 0x60 0x78 0x90 0xA8 0xC0 0xD8 0xF0 0x108 0x120 0x138 0x150 0x168 ) group.long ($2+0x2210)++0x3 line.long 0x0 "DOM_OWN_MA2_$1,Assign master 64~95 for domain owner 0" hexmask.long 0x0 0.--31. 1. "MID,Indicate if master 64~95 is resource manager." repeat.end repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x18 0x30 0x48 0x60 0x78 0x90 0xA8 0xC0 0xD8 0xF0 0x108 0x120 0x138 0x150 0x168 ) group.long ($2+0x2214)++0x3 line.long 0x0 "DOM_OWN_MA3_$1,Assign master 96~127 for domain owner 0" hexmask.long 0x0 0.--31. 1. "MID,Indicate if master 96~127 is resource manager." repeat.end group.long 0x2218++0x3 line.long 0x0 "DOM_GID_1,Indicate which group domain 1 belong to" bitfld.long 0x0 3. "LOCK,Lock write for GID" "0,1" bitfld.long 0x0 0.--2. "GID,Group ID" "0,1,2,3,4,5,6,7" group.long 0x2230++0x3 line.long 0x0 "DOM_GID_2,Indicate which group domain 2 belong to" bitfld.long 0x0 3. "LOCK,Lock write for GID" "0,1" bitfld.long 0x0 0.--2. "GID,Group ID" "0,1,2,3,4,5,6,7" group.long 0x2248++0x3 line.long 0x0 "DOM_GID_3,Indicate which group domain 3 belong to" bitfld.long 0x0 3. "LOCK,Lock write for GID" "0,1" bitfld.long 0x0 0.--2. "GID,Group ID" "0,1,2,3,4,5,6,7" group.long 0x2260++0x3 line.long 0x0 "DOM_GID_4,Indicate which group domain 4 belong to" bitfld.long 0x0 3. "LOCK,Lock write for GID" "0,1" bitfld.long 0x0 0.--2. "GID,Group ID" "0,1,2,3,4,5,6,7" group.long 0x2278++0x3 line.long 0x0 "DOM_GID_5,Indicate which group domain 5 belong to" bitfld.long 0x0 3. "LOCK,Lock write for GID" "0,1" bitfld.long 0x0 0.--2. "GID,Group ID" "0,1,2,3,4,5,6,7" group.long 0x2290++0x3 line.long 0x0 "DOM_GID_6,Indicate which group domain 6 belong to" bitfld.long 0x0 3. "LOCK,Lock write for GID" "0,1" bitfld.long 0x0 0.--2. "GID,Group ID" "0,1,2,3,4,5,6,7" group.long 0x22A8++0x3 line.long 0x0 "DOM_GID_7,Indicate which group domain 7 belong to" bitfld.long 0x0 3. "LOCK,Lock write for GID" "0,1" bitfld.long 0x0 0.--2. "GID,Group ID" "0,1,2,3,4,5,6,7" group.long 0x22C0++0x3 line.long 0x0 "DOM_GID_8,Indicate which group domain 8 belong to" bitfld.long 0x0 3. "LOCK,Lock write for GID" "0,1" bitfld.long 0x0 0.--2. "GID,Group ID" "0,1,2,3,4,5,6,7" group.long 0x22D8++0x3 line.long 0x0 "DOM_GID_9,Indicate which group domain 9 belong to" bitfld.long 0x0 3. "LOCK,Lock write for GID" "0,1" bitfld.long 0x0 0.--2. "GID,Group ID" "0,1,2,3,4,5,6,7" group.long 0x22F0++0x3 line.long 0x0 "DOM_GID_10,Indicate which group domain 10 belong to" bitfld.long 0x0 3. "LOCK,Lock write for GID" "0,1" bitfld.long 0x0 0.--2. "GID,Group ID" "0,1,2,3,4,5,6,7" group.long 0x2308++0x3 line.long 0x0 "DOM_GID_11,Indicate which group domain 11 belong to" bitfld.long 0x0 3. "LOCK,Lock write for GID" "0,1" bitfld.long 0x0 0.--2. "GID,Group ID" "0,1,2,3,4,5,6,7" group.long 0x2320++0x3 line.long 0x0 "DOM_GID_12,Indicate which group domain 12 belong to" bitfld.long 0x0 3. "LOCK,Lock write for GID" "0,1" bitfld.long 0x0 0.--2. "GID,Group ID" "0,1,2,3,4,5,6,7" group.long 0x2338++0x3 line.long 0x0 "DOM_GID_13,Indicate which group domain 13 belong to" bitfld.long 0x0 3. "LOCK,Lock write for GID" "0,1" bitfld.long 0x0 0.--2. "GID,Group ID" "0,1,2,3,4,5,6,7" group.long 0x2350++0x3 line.long 0x0 "DOM_GID_14,Indicate which group domain 14 belong to" bitfld.long 0x0 3. "LOCK,Lock write for GID" "0,1" bitfld.long 0x0 0.--2. "GID,Group ID" "0,1,2,3,4,5,6,7" group.long 0x2368++0x3 line.long 0x0 "DOM_GID_15,Indicate which group domain 15 belong to" bitfld.long 0x0 3. "LOCK,Lock write for GID" "0,1" bitfld.long 0x0 0.--2. "GID,Group ID" "0,1,2,3,4,5,6,7" repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x34 0x68 0x9C 0xD0 0x104 0x138 0x16C 0x1A0 0x1D4 0x208 0x23C 0x270 0x2A4 0x2D8 0x30C ) group.long ($2+0x2400)++0x3 line.long 0x0 "DOM_PER0_$1,Domain Permission Control. It can be only configured by resource manager and domain owner." bitfld.long 0x0 31. "DOM7_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 29.--30. "DOM7_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 28. "DOM7_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 27. "DOM6_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 25.--26. "DOM6_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" newline bitfld.long 0x0 24. "DOM6_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 23. "DOM5_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 21.--22. "DOM5_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 20. "DOM5_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 19. "DOM4_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" newline bitfld.long 0x0 17.--18. "DOM4_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM4_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 15. "DOM3_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 13.--14. "DOM3_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 12. "DOM3_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" newline bitfld.long 0x0 11. "DOM2_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 9.--10. "DOM2_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM2_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 7. "DOM1_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 5.--6. "DOM1_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" newline bitfld.long 0x0 4. "DOM1_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 3. "DOM0_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 1.--2. "DOM0_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM0_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" repeat.end repeat 16. (list 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1A 0x1B 0x1C 0x1D 0x1E 0x1F )(list 0x340 0x374 0x3A8 0x3DC 0x410 0x444 0x478 0x4AC 0x4E0 0x514 0x548 0x57C 0x5B0 0x5E4 0x618 0x64C ) group.long ($2+0x2400)++0x3 line.long 0x0 "DOM_PER0_$1,Domain Permission Control. It can be only configured by resource manager and domain owner." bitfld.long 0x0 31. "DOM7_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 29.--30. "DOM7_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 28. "DOM7_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 27. "DOM6_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 25.--26. "DOM6_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" newline bitfld.long 0x0 24. "DOM6_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 23. "DOM5_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 21.--22. "DOM5_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 20. "DOM5_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 19. "DOM4_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" newline bitfld.long 0x0 17.--18. "DOM4_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM4_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 15. "DOM3_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 13.--14. "DOM3_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 12. "DOM3_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" newline bitfld.long 0x0 11. "DOM2_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 9.--10. "DOM2_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM2_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 7. "DOM1_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 5.--6. "DOM1_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" newline bitfld.long 0x0 4. "DOM1_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 3. "DOM0_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 1.--2. "DOM0_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM0_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" repeat.end repeat 16. (list 0x20 0x21 0x22 0x23 0x24 0x25 0x26 0x27 0x28 0x29 0x2A 0x2B 0x2C 0x2D 0x2E 0x2F )(list 0x680 0x6B4 0x6E8 0x71C 0x750 0x784 0x7B8 0x7EC 0x820 0x854 0x888 0x8BC 0x8F0 0x924 0x958 0x98C ) group.long ($2+0x2400)++0x3 line.long 0x0 "DOM_PER0_$1,Domain Permission Control. It can be only configured by resource manager and domain owner." bitfld.long 0x0 31. "DOM7_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 29.--30. "DOM7_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 28. "DOM7_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 27. "DOM6_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 25.--26. "DOM6_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" newline bitfld.long 0x0 24. "DOM6_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 23. "DOM5_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 21.--22. "DOM5_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 20. "DOM5_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 19. "DOM4_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" newline bitfld.long 0x0 17.--18. "DOM4_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM4_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 15. "DOM3_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 13.--14. "DOM3_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 12. "DOM3_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" newline bitfld.long 0x0 11. "DOM2_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 9.--10. "DOM2_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM2_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 7. "DOM1_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 5.--6. "DOM1_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" newline bitfld.long 0x0 4. "DOM1_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 3. "DOM0_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 1.--2. "DOM0_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM0_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" repeat.end repeat 16. (list 0x30 0x31 0x32 0x33 0x34 0x35 0x36 0x37 0x38 0x39 0x3A 0x3B 0x3C 0x3D 0x3E 0x3F )(list 0x9C0 0x9F4 0xA28 0xA5C 0xA90 0xAC4 0xAF8 0xB2C 0xB60 0xB94 0xBC8 0xBFC 0xC30 0xC64 0xC98 0xCCC ) group.long ($2+0x2400)++0x3 line.long 0x0 "DOM_PER0_$1,Domain Permission Control. It can be only configured by resource manager and domain owner." bitfld.long 0x0 31. "DOM7_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 29.--30. "DOM7_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 28. "DOM7_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 27. "DOM6_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 25.--26. "DOM6_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" newline bitfld.long 0x0 24. "DOM6_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 23. "DOM5_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 21.--22. "DOM5_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 20. "DOM5_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 19. "DOM4_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" newline bitfld.long 0x0 17.--18. "DOM4_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM4_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 15. "DOM3_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 13.--14. "DOM3_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 12. "DOM3_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" newline bitfld.long 0x0 11. "DOM2_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 9.--10. "DOM2_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM2_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 7. "DOM1_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 5.--6. "DOM1_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" newline bitfld.long 0x0 4. "DOM1_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 3. "DOM0_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 1.--2. "DOM0_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM0_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" repeat.end repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x34 0x68 0x9C 0xD0 0x104 0x138 0x16C 0x1A0 0x1D4 0x208 0x23C 0x270 0x2A4 0x2D8 0x30C ) group.long ($2+0x2404)++0x3 line.long 0x0 "DOM_PER1_$1,Domain Permission Control. It can be only configured by resource manager and domain owner." bitfld.long 0x0 31. "DOM15_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 29.--30. "DOM15_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 28. "DOM15_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 27. "DOM14_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 25.--26. "DOM14_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" newline bitfld.long 0x0 24. "DOM14_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 23. "DOM13_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 21.--22. "DOM13_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 20. "DOM13_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 19. "DOM12_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" newline bitfld.long 0x0 17.--18. "DOM12_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM12_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 15. "DOM11_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 13.--14. "DOM11_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 12. "DOM11_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" newline bitfld.long 0x0 11. "DOM10_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 9.--10. "DOM10_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM10_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 7. "DOM9_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 5.--6. "DOM9_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" newline bitfld.long 0x0 4. "DOM9_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 3. "DOM8_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 1.--2. "DOM8_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM8_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" repeat.end repeat 16. (list 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1A 0x1B 0x1C 0x1D 0x1E 0x1F )(list 0x340 0x374 0x3A8 0x3DC 0x410 0x444 0x478 0x4AC 0x4E0 0x514 0x548 0x57C 0x5B0 0x5E4 0x618 0x64C ) group.long ($2+0x2404)++0x3 line.long 0x0 "DOM_PER1_$1,Domain Permission Control. It can be only configured by resource manager and domain owner." bitfld.long 0x0 31. "DOM15_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 29.--30. "DOM15_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 28. "DOM15_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 27. "DOM14_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 25.--26. "DOM14_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" newline bitfld.long 0x0 24. "DOM14_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 23. "DOM13_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 21.--22. "DOM13_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 20. "DOM13_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 19. "DOM12_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" newline bitfld.long 0x0 17.--18. "DOM12_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM12_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 15. "DOM11_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 13.--14. "DOM11_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 12. "DOM11_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" newline bitfld.long 0x0 11. "DOM10_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 9.--10. "DOM10_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM10_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 7. "DOM9_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 5.--6. "DOM9_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" newline bitfld.long 0x0 4. "DOM9_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 3. "DOM8_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 1.--2. "DOM8_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM8_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" repeat.end repeat 16. (list 0x20 0x21 0x22 0x23 0x24 0x25 0x26 0x27 0x28 0x29 0x2A 0x2B 0x2C 0x2D 0x2E 0x2F )(list 0x680 0x6B4 0x6E8 0x71C 0x750 0x784 0x7B8 0x7EC 0x820 0x854 0x888 0x8BC 0x8F0 0x924 0x958 0x98C ) group.long ($2+0x2404)++0x3 line.long 0x0 "DOM_PER1_$1,Domain Permission Control. It can be only configured by resource manager and domain owner." bitfld.long 0x0 31. "DOM15_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 29.--30. "DOM15_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 28. "DOM15_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 27. "DOM14_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 25.--26. "DOM14_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" newline bitfld.long 0x0 24. "DOM14_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 23. "DOM13_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 21.--22. "DOM13_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 20. "DOM13_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 19. "DOM12_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" newline bitfld.long 0x0 17.--18. "DOM12_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM12_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 15. "DOM11_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 13.--14. "DOM11_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 12. "DOM11_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" newline bitfld.long 0x0 11. "DOM10_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 9.--10. "DOM10_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM10_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 7. "DOM9_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 5.--6. "DOM9_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" newline bitfld.long 0x0 4. "DOM9_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 3. "DOM8_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 1.--2. "DOM8_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM8_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" repeat.end repeat 16. (list 0x30 0x31 0x32 0x33 0x34 0x35 0x36 0x37 0x38 0x39 0x3A 0x3B 0x3C 0x3D 0x3E 0x3F )(list 0x9C0 0x9F4 0xA28 0xA5C 0xA90 0xAC4 0xAF8 0xB2C 0xB60 0xB94 0xBC8 0xBFC 0xC30 0xC64 0xC98 0xCCC ) group.long ($2+0x2404)++0x3 line.long 0x0 "DOM_PER1_$1,Domain Permission Control. It can be only configured by resource manager and domain owner." bitfld.long 0x0 31. "DOM15_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 29.--30. "DOM15_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 28. "DOM15_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 27. "DOM14_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 25.--26. "DOM14_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" newline bitfld.long 0x0 24. "DOM14_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 23. "DOM13_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 21.--22. "DOM13_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 20. "DOM13_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 19. "DOM12_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" newline bitfld.long 0x0 17.--18. "DOM12_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM12_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 15. "DOM11_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 13.--14. "DOM11_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 12. "DOM11_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" newline bitfld.long 0x0 11. "DOM10_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 9.--10. "DOM10_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM10_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 7. "DOM9_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 5.--6. "DOM9_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" newline bitfld.long 0x0 4. "DOM9_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 3. "DOM8_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 1.--2. "DOM8_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM8_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" repeat.end repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x34 0x68 0x9C 0xD0 0x104 0x138 0x16C 0x1A0 0x1D4 0x208 0x23C 0x270 0x2A4 0x2D8 0x30C ) group.long ($2+0x2408)++0x3 line.long 0x0 "SEC_PER0_$1,This register is only used for resource manager to control secure access permission." bitfld.long 0x0 31. "DOM3_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM3_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM3_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM3_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM2_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM2_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM2_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM2_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM1_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM1_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM1_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM1_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM0_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM0_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM0_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM0_SEC_EN,Domain secure permission control enable" "0,1" repeat.end repeat 16. (list 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1A 0x1B 0x1C 0x1D 0x1E 0x1F )(list 0x340 0x374 0x3A8 0x3DC 0x410 0x444 0x478 0x4AC 0x4E0 0x514 0x548 0x57C 0x5B0 0x5E4 0x618 0x64C ) group.long ($2+0x2408)++0x3 line.long 0x0 "SEC_PER0_$1,This register is only used for resource manager to control secure access permission." bitfld.long 0x0 31. "DOM3_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM3_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM3_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM3_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM2_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM2_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM2_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM2_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM1_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM1_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM1_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM1_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM0_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM0_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM0_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM0_SEC_EN,Domain secure permission control enable" "0,1" repeat.end repeat 16. (list 0x20 0x21 0x22 0x23 0x24 0x25 0x26 0x27 0x28 0x29 0x2A 0x2B 0x2C 0x2D 0x2E 0x2F )(list 0x680 0x6B4 0x6E8 0x71C 0x750 0x784 0x7B8 0x7EC 0x820 0x854 0x888 0x8BC 0x8F0 0x924 0x958 0x98C ) group.long ($2+0x2408)++0x3 line.long 0x0 "SEC_PER0_$1,This register is only used for resource manager to control secure access permission." bitfld.long 0x0 31. "DOM3_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM3_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM3_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM3_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM2_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM2_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM2_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM2_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM1_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM1_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM1_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM1_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM0_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM0_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM0_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM0_SEC_EN,Domain secure permission control enable" "0,1" repeat.end repeat 16. (list 0x30 0x31 0x32 0x33 0x34 0x35 0x36 0x37 0x38 0x39 0x3A 0x3B 0x3C 0x3D 0x3E 0x3F )(list 0x9C0 0x9F4 0xA28 0xA5C 0xA90 0xAC4 0xAF8 0xB2C 0xB60 0xB94 0xBC8 0xBFC 0xC30 0xC64 0xC98 0xCCC ) group.long ($2+0x2408)++0x3 line.long 0x0 "SEC_PER0_$1,This register is only used for resource manager to control secure access permission." bitfld.long 0x0 31. "DOM3_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM3_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM3_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM3_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM2_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM2_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM2_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM2_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM1_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM1_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM1_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM1_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM0_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM0_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM0_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM0_SEC_EN,Domain secure permission control enable" "0,1" repeat.end repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x34 0x68 0x9C 0xD0 0x104 0x138 0x16C 0x1A0 0x1D4 0x208 0x23C 0x270 0x2A4 0x2D8 0x30C ) group.long ($2+0x240C)++0x3 line.long 0x0 "SEC_PER1_$1,This register is only used for resource manager to control secure access permission." bitfld.long 0x0 31. "DOM7_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM7_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM7_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM7_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM6_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM6_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM6_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM6_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM5_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM5_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM5_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM5_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM4_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM4_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM4_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM4_SEC_EN,Domain secure permission control enable" "0,1" repeat.end repeat 16. (list 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1A 0x1B 0x1C 0x1D 0x1E 0x1F )(list 0x340 0x374 0x3A8 0x3DC 0x410 0x444 0x478 0x4AC 0x4E0 0x514 0x548 0x57C 0x5B0 0x5E4 0x618 0x64C ) group.long ($2+0x240C)++0x3 line.long 0x0 "SEC_PER1_$1,This register is only used for resource manager to control secure access permission." bitfld.long 0x0 31. "DOM7_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM7_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM7_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM7_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM6_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM6_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM6_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM6_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM5_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM5_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM5_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM5_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM4_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM4_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM4_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM4_SEC_EN,Domain secure permission control enable" "0,1" repeat.end repeat 16. (list 0x20 0x21 0x22 0x23 0x24 0x25 0x26 0x27 0x28 0x29 0x2A 0x2B 0x2C 0x2D 0x2E 0x2F )(list 0x680 0x6B4 0x6E8 0x71C 0x750 0x784 0x7B8 0x7EC 0x820 0x854 0x888 0x8BC 0x8F0 0x924 0x958 0x98C ) group.long ($2+0x240C)++0x3 line.long 0x0 "SEC_PER1_$1,This register is only used for resource manager to control secure access permission." bitfld.long 0x0 31. "DOM7_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM7_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM7_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM7_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM6_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM6_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM6_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM6_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM5_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM5_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM5_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM5_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM4_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM4_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM4_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM4_SEC_EN,Domain secure permission control enable" "0,1" repeat.end repeat 16. (list 0x30 0x31 0x32 0x33 0x34 0x35 0x36 0x37 0x38 0x39 0x3A 0x3B 0x3C 0x3D 0x3E 0x3F )(list 0x9C0 0x9F4 0xA28 0xA5C 0xA90 0xAC4 0xAF8 0xB2C 0xB60 0xB94 0xBC8 0xBFC 0xC30 0xC64 0xC98 0xCCC ) group.long ($2+0x240C)++0x3 line.long 0x0 "SEC_PER1_$1,This register is only used for resource manager to control secure access permission." bitfld.long 0x0 31. "DOM7_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM7_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM7_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM7_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM6_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM6_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM6_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM6_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM5_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM5_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM5_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM5_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM4_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM4_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM4_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM4_SEC_EN,Domain secure permission control enable" "0,1" repeat.end repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x34 0x68 0x9C 0xD0 0x104 0x138 0x16C 0x1A0 0x1D4 0x208 0x23C 0x270 0x2A4 0x2D8 0x30C ) group.long ($2+0x2410)++0x3 line.long 0x0 "SEC_PER2_$1,This register is only used for resource manager to control secure access permission." bitfld.long 0x0 31. "DOM11_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM11_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM11_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM11_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM10_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM10_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM10_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM10_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM9_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM9_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM9_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM9_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM8_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM8_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM8_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM8_SEC_EN,Domain secure permission control enable" "0,1" repeat.end repeat 16. (list 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1A 0x1B 0x1C 0x1D 0x1E 0x1F )(list 0x340 0x374 0x3A8 0x3DC 0x410 0x444 0x478 0x4AC 0x4E0 0x514 0x548 0x57C 0x5B0 0x5E4 0x618 0x64C ) group.long ($2+0x2410)++0x3 line.long 0x0 "SEC_PER2_$1,This register is only used for resource manager to control secure access permission." bitfld.long 0x0 31. "DOM11_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM11_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM11_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM11_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM10_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM10_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM10_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM10_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM9_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM9_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM9_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM9_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM8_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM8_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM8_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM8_SEC_EN,Domain secure permission control enable" "0,1" repeat.end repeat 16. (list 0x20 0x21 0x22 0x23 0x24 0x25 0x26 0x27 0x28 0x29 0x2A 0x2B 0x2C 0x2D 0x2E 0x2F )(list 0x680 0x6B4 0x6E8 0x71C 0x750 0x784 0x7B8 0x7EC 0x820 0x854 0x888 0x8BC 0x8F0 0x924 0x958 0x98C ) group.long ($2+0x2410)++0x3 line.long 0x0 "SEC_PER2_$1,This register is only used for resource manager to control secure access permission." bitfld.long 0x0 31. "DOM11_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM11_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM11_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM11_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM10_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM10_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM10_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM10_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM9_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM9_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM9_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM9_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM8_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM8_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM8_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM8_SEC_EN,Domain secure permission control enable" "0,1" repeat.end repeat 16. (list 0x30 0x31 0x32 0x33 0x34 0x35 0x36 0x37 0x38 0x39 0x3A 0x3B 0x3C 0x3D 0x3E 0x3F )(list 0x9C0 0x9F4 0xA28 0xA5C 0xA90 0xAC4 0xAF8 0xB2C 0xB60 0xB94 0xBC8 0xBFC 0xC30 0xC64 0xC98 0xCCC ) group.long ($2+0x2410)++0x3 line.long 0x0 "SEC_PER2_$1,This register is only used for resource manager to control secure access permission." bitfld.long 0x0 31. "DOM11_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM11_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM11_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM11_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM10_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM10_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM10_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM10_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM9_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM9_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM9_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM9_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM8_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM8_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM8_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM8_SEC_EN,Domain secure permission control enable" "0,1" repeat.end repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x34 0x68 0x9C 0xD0 0x104 0x138 0x16C 0x1A0 0x1D4 0x208 0x23C 0x270 0x2A4 0x2D8 0x30C ) group.long ($2+0x2414)++0x3 line.long 0x0 "SEC_PER3_$1,This register is only used for resource manager to control secure access permission." bitfld.long 0x0 31. "DOM15_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM15_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM15_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM15_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM14_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM14_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM14_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM14_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM13_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM13_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM13_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM13_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM12_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM12_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM12_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM12_SEC_EN,Domain secure permission control enable" "0,1" repeat.end repeat 16. (list 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1A 0x1B 0x1C 0x1D 0x1E 0x1F )(list 0x340 0x374 0x3A8 0x3DC 0x410 0x444 0x478 0x4AC 0x4E0 0x514 0x548 0x57C 0x5B0 0x5E4 0x618 0x64C ) group.long ($2+0x2414)++0x3 line.long 0x0 "SEC_PER3_$1,This register is only used for resource manager to control secure access permission." bitfld.long 0x0 31. "DOM15_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM15_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM15_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM15_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM14_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM14_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM14_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM14_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM13_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM13_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM13_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM13_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM12_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM12_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM12_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM12_SEC_EN,Domain secure permission control enable" "0,1" repeat.end repeat 16. (list 0x20 0x21 0x22 0x23 0x24 0x25 0x26 0x27 0x28 0x29 0x2A 0x2B 0x2C 0x2D 0x2E 0x2F )(list 0x680 0x6B4 0x6E8 0x71C 0x750 0x784 0x7B8 0x7EC 0x820 0x854 0x888 0x8BC 0x8F0 0x924 0x958 0x98C ) group.long ($2+0x2414)++0x3 line.long 0x0 "SEC_PER3_$1,This register is only used for resource manager to control secure access permission." bitfld.long 0x0 31. "DOM15_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM15_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM15_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM15_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM14_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM14_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM14_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM14_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM13_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM13_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM13_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM13_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM12_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM12_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM12_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM12_SEC_EN,Domain secure permission control enable" "0,1" repeat.end repeat 16. (list 0x30 0x31 0x32 0x33 0x34 0x35 0x36 0x37 0x38 0x39 0x3A 0x3B 0x3C 0x3D 0x3E 0x3F )(list 0x9C0 0x9F4 0xA28 0xA5C 0xA90 0xAC4 0xAF8 0xB2C 0xB60 0xB94 0xBC8 0xBFC 0xC30 0xC64 0xC98 0xCCC ) group.long ($2+0x2414)++0x3 line.long 0x0 "SEC_PER3_$1,This register is only used for resource manager to control secure access permission." bitfld.long 0x0 31. "DOM15_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM15_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM15_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM15_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM14_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM14_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM14_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM14_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM13_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM13_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM13_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM13_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM12_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM12_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM12_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM12_SEC_EN,Domain secure permission control enable" "0,1" repeat.end repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x34 0x68 0x9C 0xD0 0x104 0x138 0x16C 0x1A0 0x1D4 0x208 0x23C 0x270 0x2A4 0x2D8 0x30C ) group.long ($2+0x2418)++0x3 line.long 0x0 "PRI_PER0_$1,This register is only used for resource manager to control privileged access permission." bitfld.long 0x0 31. "DOM3_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM3_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM3_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM3_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM2_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM2_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM2_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM2_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM1_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM1_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM1_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM1_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM0_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM0_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM0_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM0_PRI_EN,Domain privileged permission control enable" "0,1" repeat.end repeat 16. (list 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1A 0x1B 0x1C 0x1D 0x1E 0x1F )(list 0x340 0x374 0x3A8 0x3DC 0x410 0x444 0x478 0x4AC 0x4E0 0x514 0x548 0x57C 0x5B0 0x5E4 0x618 0x64C ) group.long ($2+0x2418)++0x3 line.long 0x0 "PRI_PER0_$1,This register is only used for resource manager to control privileged access permission." bitfld.long 0x0 31. "DOM3_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM3_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM3_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM3_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM2_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM2_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM2_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM2_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM1_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM1_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM1_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM1_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM0_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM0_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM0_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM0_PRI_EN,Domain privileged permission control enable" "0,1" repeat.end repeat 16. (list 0x20 0x21 0x22 0x23 0x24 0x25 0x26 0x27 0x28 0x29 0x2A 0x2B 0x2C 0x2D 0x2E 0x2F )(list 0x680 0x6B4 0x6E8 0x71C 0x750 0x784 0x7B8 0x7EC 0x820 0x854 0x888 0x8BC 0x8F0 0x924 0x958 0x98C ) group.long ($2+0x2418)++0x3 line.long 0x0 "PRI_PER0_$1,This register is only used for resource manager to control privileged access permission." bitfld.long 0x0 31. "DOM3_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM3_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM3_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM3_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM2_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM2_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM2_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM2_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM1_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM1_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM1_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM1_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM0_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM0_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM0_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM0_PRI_EN,Domain privileged permission control enable" "0,1" repeat.end repeat 16. (list 0x30 0x31 0x32 0x33 0x34 0x35 0x36 0x37 0x38 0x39 0x3A 0x3B 0x3C 0x3D 0x3E 0x3F )(list 0x9C0 0x9F4 0xA28 0xA5C 0xA90 0xAC4 0xAF8 0xB2C 0xB60 0xB94 0xBC8 0xBFC 0xC30 0xC64 0xC98 0xCCC ) group.long ($2+0x2418)++0x3 line.long 0x0 "PRI_PER0_$1,This register is only used for resource manager to control privileged access permission." bitfld.long 0x0 31. "DOM3_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM3_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM3_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM3_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM2_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM2_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM2_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM2_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM1_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM1_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM1_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM1_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM0_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM0_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM0_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM0_PRI_EN,Domain privileged permission control enable" "0,1" repeat.end repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x34 0x68 0x9C 0xD0 0x104 0x138 0x16C 0x1A0 0x1D4 0x208 0x23C 0x270 0x2A4 0x2D8 0x30C ) group.long ($2+0x241C)++0x3 line.long 0x0 "PRI_PER1_$1,This register is only used for resource manager to control privileged access permission." bitfld.long 0x0 31. "DOM7_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM7_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM7_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM7_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM6_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM6_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM6_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM6_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM5_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM5_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM5_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM5_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM4_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM4_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM4_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM4_PRI_EN,Domain privileged permission control enable" "0,1" repeat.end repeat 16. (list 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1A 0x1B 0x1C 0x1D 0x1E 0x1F )(list 0x340 0x374 0x3A8 0x3DC 0x410 0x444 0x478 0x4AC 0x4E0 0x514 0x548 0x57C 0x5B0 0x5E4 0x618 0x64C ) group.long ($2+0x241C)++0x3 line.long 0x0 "PRI_PER1_$1,This register is only used for resource manager to control privileged access permission." bitfld.long 0x0 31. "DOM7_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM7_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM7_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM7_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM6_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM6_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM6_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM6_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM5_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM5_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM5_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM5_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM4_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM4_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM4_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM4_PRI_EN,Domain privileged permission control enable" "0,1" repeat.end repeat 16. (list 0x20 0x21 0x22 0x23 0x24 0x25 0x26 0x27 0x28 0x29 0x2A 0x2B 0x2C 0x2D 0x2E 0x2F )(list 0x680 0x6B4 0x6E8 0x71C 0x750 0x784 0x7B8 0x7EC 0x820 0x854 0x888 0x8BC 0x8F0 0x924 0x958 0x98C ) group.long ($2+0x241C)++0x3 line.long 0x0 "PRI_PER1_$1,This register is only used for resource manager to control privileged access permission." bitfld.long 0x0 31. "DOM7_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM7_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM7_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM7_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM6_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM6_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM6_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM6_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM5_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM5_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM5_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM5_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM4_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM4_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM4_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM4_PRI_EN,Domain privileged permission control enable" "0,1" repeat.end repeat 16. (list 0x30 0x31 0x32 0x33 0x34 0x35 0x36 0x37 0x38 0x39 0x3A 0x3B 0x3C 0x3D 0x3E 0x3F )(list 0x9C0 0x9F4 0xA28 0xA5C 0xA90 0xAC4 0xAF8 0xB2C 0xB60 0xB94 0xBC8 0xBFC 0xC30 0xC64 0xC98 0xCCC ) group.long ($2+0x241C)++0x3 line.long 0x0 "PRI_PER1_$1,This register is only used for resource manager to control privileged access permission." bitfld.long 0x0 31. "DOM7_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM7_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM7_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM7_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM6_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM6_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM6_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM6_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM5_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM5_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM5_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM5_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM4_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM4_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM4_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM4_PRI_EN,Domain privileged permission control enable" "0,1" repeat.end repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x34 0x68 0x9C 0xD0 0x104 0x138 0x16C 0x1A0 0x1D4 0x208 0x23C 0x270 0x2A4 0x2D8 0x30C ) group.long ($2+0x2420)++0x3 line.long 0x0 "PRI_PER2_$1,This register is only used for resource manager to control privileged access permission." bitfld.long 0x0 31. "DOM11_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM11_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM11_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM11_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM10_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM10_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM10_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM10_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM9_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM9_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM9_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM9_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM8_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM8_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM8_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM8_PRI_EN,Domain privileged permission control enable" "0,1" repeat.end repeat 16. (list 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1A 0x1B 0x1C 0x1D 0x1E 0x1F )(list 0x340 0x374 0x3A8 0x3DC 0x410 0x444 0x478 0x4AC 0x4E0 0x514 0x548 0x57C 0x5B0 0x5E4 0x618 0x64C ) group.long ($2+0x2420)++0x3 line.long 0x0 "PRI_PER2_$1,This register is only used for resource manager to control privileged access permission." bitfld.long 0x0 31. "DOM11_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM11_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM11_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM11_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM10_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM10_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM10_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM10_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM9_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM9_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM9_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM9_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM8_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM8_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM8_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM8_PRI_EN,Domain privileged permission control enable" "0,1" repeat.end repeat 16. (list 0x20 0x21 0x22 0x23 0x24 0x25 0x26 0x27 0x28 0x29 0x2A 0x2B 0x2C 0x2D 0x2E 0x2F )(list 0x680 0x6B4 0x6E8 0x71C 0x750 0x784 0x7B8 0x7EC 0x820 0x854 0x888 0x8BC 0x8F0 0x924 0x958 0x98C ) group.long ($2+0x2420)++0x3 line.long 0x0 "PRI_PER2_$1,This register is only used for resource manager to control privileged access permission." bitfld.long 0x0 31. "DOM11_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM11_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM11_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM11_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM10_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM10_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM10_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM10_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM9_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM9_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM9_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM9_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM8_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM8_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM8_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM8_PRI_EN,Domain privileged permission control enable" "0,1" repeat.end repeat 16. (list 0x30 0x31 0x32 0x33 0x34 0x35 0x36 0x37 0x38 0x39 0x3A 0x3B 0x3C 0x3D 0x3E 0x3F )(list 0x9C0 0x9F4 0xA28 0xA5C 0xA90 0xAC4 0xAF8 0xB2C 0xB60 0xB94 0xBC8 0xBFC 0xC30 0xC64 0xC98 0xCCC ) group.long ($2+0x2420)++0x3 line.long 0x0 "PRI_PER2_$1,This register is only used for resource manager to control privileged access permission." bitfld.long 0x0 31. "DOM11_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM11_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM11_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM11_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM10_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM10_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM10_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM10_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM9_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM9_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM9_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM9_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM8_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM8_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM8_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM8_PRI_EN,Domain privileged permission control enable" "0,1" repeat.end repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x34 0x68 0x9C 0xD0 0x104 0x138 0x16C 0x1A0 0x1D4 0x208 0x23C 0x270 0x2A4 0x2D8 0x30C ) group.long ($2+0x2424)++0x3 line.long 0x0 "PRI_PER3_$1,This register is only used for resource manager to control privileged access permission." bitfld.long 0x0 31. "DOM15_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM15_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM15_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM15_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM14_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM14_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM14_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM14_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM13_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM13_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM13_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM13_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM12_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM12_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM12_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM12_PRI_EN,Domain privileged permission control enable" "0,1" repeat.end repeat 16. (list 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1A 0x1B 0x1C 0x1D 0x1E 0x1F )(list 0x340 0x374 0x3A8 0x3DC 0x410 0x444 0x478 0x4AC 0x4E0 0x514 0x548 0x57C 0x5B0 0x5E4 0x618 0x64C ) group.long ($2+0x2424)++0x3 line.long 0x0 "PRI_PER3_$1,This register is only used for resource manager to control privileged access permission." bitfld.long 0x0 31. "DOM15_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM15_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM15_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM15_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM14_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM14_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM14_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM14_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM13_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM13_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM13_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM13_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM12_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM12_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM12_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM12_PRI_EN,Domain privileged permission control enable" "0,1" repeat.end repeat 16. (list 0x20 0x21 0x22 0x23 0x24 0x25 0x26 0x27 0x28 0x29 0x2A 0x2B 0x2C 0x2D 0x2E 0x2F )(list 0x680 0x6B4 0x6E8 0x71C 0x750 0x784 0x7B8 0x7EC 0x820 0x854 0x888 0x8BC 0x8F0 0x924 0x958 0x98C ) group.long ($2+0x2424)++0x3 line.long 0x0 "PRI_PER3_$1,This register is only used for resource manager to control privileged access permission." bitfld.long 0x0 31. "DOM15_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM15_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM15_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM15_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM14_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM14_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM14_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM14_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM13_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM13_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM13_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM13_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM12_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM12_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM12_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM12_PRI_EN,Domain privileged permission control enable" "0,1" repeat.end repeat 16. (list 0x30 0x31 0x32 0x33 0x34 0x35 0x36 0x37 0x38 0x39 0x3A 0x3B 0x3C 0x3D 0x3E 0x3F )(list 0x9C0 0x9F4 0xA28 0xA5C 0xA90 0xAC4 0xAF8 0xB2C 0xB60 0xB94 0xBC8 0xBFC 0xC30 0xC64 0xC98 0xCCC ) group.long ($2+0x2424)++0x3 line.long 0x0 "PRI_PER3_$1,This register is only used for resource manager to control privileged access permission." bitfld.long 0x0 31. "DOM15_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM15_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM15_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM15_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM14_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM14_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM14_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM14_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM13_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM13_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM13_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM13_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM12_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM12_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM12_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM12_PRI_EN,Domain privileged permission control enable" "0,1" repeat.end repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x34 0x68 0x9C 0xD0 0x104 0x138 0x16C 0x1A0 0x1D4 0x208 0x23C 0x270 0x2A4 0x2D8 0x30C ) group.long ($2+0x2428)++0x3 line.long 0x0 "DOM_SEC_PER_$1,This register is only used for domain master to control secure access permission. When the domain master write this register. it only changes the secure permission for itself. When the domain master read this register. it gets permission.." bitfld.long 0x0 7. "DOM_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" newline bitfld.long 0x0 0. "DOM_SEC_EN,Domain secure permission control enable" "0,1" repeat.end repeat 16. (list 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1A 0x1B 0x1C 0x1D 0x1E 0x1F )(list 0x340 0x374 0x3A8 0x3DC 0x410 0x444 0x478 0x4AC 0x4E0 0x514 0x548 0x57C 0x5B0 0x5E4 0x618 0x64C ) group.long ($2+0x2428)++0x3 line.long 0x0 "DOM_SEC_PER_$1,This register is only used for domain master to control secure access permission. When the domain master write this register. it only changes the secure permission for itself. When the domain master read this register. it gets permission.." bitfld.long 0x0 7. "DOM_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" newline bitfld.long 0x0 0. "DOM_SEC_EN,Domain secure permission control enable" "0,1" repeat.end repeat 16. (list 0x20 0x21 0x22 0x23 0x24 0x25 0x26 0x27 0x28 0x29 0x2A 0x2B 0x2C 0x2D 0x2E 0x2F )(list 0x680 0x6B4 0x6E8 0x71C 0x750 0x784 0x7B8 0x7EC 0x820 0x854 0x888 0x8BC 0x8F0 0x924 0x958 0x98C ) group.long ($2+0x2428)++0x3 line.long 0x0 "DOM_SEC_PER_$1,This register is only used for domain master to control secure access permission. When the domain master write this register. it only changes the secure permission for itself. When the domain master read this register. it gets permission.." bitfld.long 0x0 7. "DOM_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" newline bitfld.long 0x0 0. "DOM_SEC_EN,Domain secure permission control enable" "0,1" repeat.end repeat 16. (list 0x30 0x31 0x32 0x33 0x34 0x35 0x36 0x37 0x38 0x39 0x3A 0x3B 0x3C 0x3D 0x3E 0x3F )(list 0x9C0 0x9F4 0xA28 0xA5C 0xA90 0xAC4 0xAF8 0xB2C 0xB60 0xB94 0xBC8 0xBFC 0xC30 0xC64 0xC98 0xCCC ) group.long ($2+0x2428)++0x3 line.long 0x0 "DOM_SEC_PER_$1,This register is only used for domain master to control secure access permission. When the domain master write this register. it only changes the secure permission for itself. When the domain master read this register. it gets permission.." bitfld.long 0x0 7. "DOM_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" newline bitfld.long 0x0 0. "DOM_SEC_EN,Domain secure permission control enable" "0,1" repeat.end repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x34 0x68 0x9C 0xD0 0x104 0x138 0x16C 0x1A0 0x1D4 0x208 0x23C 0x270 0x2A4 0x2D8 0x30C ) group.long ($2+0x242C)++0x3 line.long 0x0 "DOM_PRI_PER_$1,This register is only used for domain master to control secure access permission. When the domain master write this register. it only changes the secure permission for itself. When the domain master read this register. it gets permission.." bitfld.long 0x0 7. "DOM_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" newline bitfld.long 0x0 0. "DOM_PRI_EN,Domain privileged permission control enable" "0,1" repeat.end repeat 16. (list 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1A 0x1B 0x1C 0x1D 0x1E 0x1F )(list 0x340 0x374 0x3A8 0x3DC 0x410 0x444 0x478 0x4AC 0x4E0 0x514 0x548 0x57C 0x5B0 0x5E4 0x618 0x64C ) group.long ($2+0x242C)++0x3 line.long 0x0 "DOM_PRI_PER_$1,This register is only used for domain master to control secure access permission. When the domain master write this register. it only changes the secure permission for itself. When the domain master read this register. it gets permission.." bitfld.long 0x0 7. "DOM_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" newline bitfld.long 0x0 0. "DOM_PRI_EN,Domain privileged permission control enable" "0,1" repeat.end repeat 16. (list 0x20 0x21 0x22 0x23 0x24 0x25 0x26 0x27 0x28 0x29 0x2A 0x2B 0x2C 0x2D 0x2E 0x2F )(list 0x680 0x6B4 0x6E8 0x71C 0x750 0x784 0x7B8 0x7EC 0x820 0x854 0x888 0x8BC 0x8F0 0x924 0x958 0x98C ) group.long ($2+0x242C)++0x3 line.long 0x0 "DOM_PRI_PER_$1,This register is only used for domain master to control secure access permission. When the domain master write this register. it only changes the secure permission for itself. When the domain master read this register. it gets permission.." bitfld.long 0x0 7. "DOM_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" newline bitfld.long 0x0 0. "DOM_PRI_EN,Domain privileged permission control enable" "0,1" repeat.end repeat 16. (list 0x30 0x31 0x32 0x33 0x34 0x35 0x36 0x37 0x38 0x39 0x3A 0x3B 0x3C 0x3D 0x3E 0x3F )(list 0x9C0 0x9F4 0xA28 0xA5C 0xA90 0xAC4 0xAF8 0xB2C 0xB60 0xB94 0xBC8 0xBFC 0xC30 0xC64 0xC98 0xCCC ) group.long ($2+0x242C)++0x3 line.long 0x0 "DOM_PRI_PER_$1,This register is only used for domain master to control secure access permission. When the domain master write this register. it only changes the secure permission for itself. When the domain master read this register. it gets permission.." bitfld.long 0x0 7. "DOM_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" newline bitfld.long 0x0 0. "DOM_PRI_EN,Domain privileged permission control enable" "0,1" repeat.end repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x34 0x68 0x9C 0xD0 0x104 0x138 0x16C 0x1A0 0x1D4 0x208 0x23C 0x270 0x2A4 0x2D8 0x30C ) group.long ($2+0x2430)++0x3 line.long 0x0 "DOM_ASSIGN_$1,Use to assign domain for accessing DOM_SEC_PER and DOM_PRI_PER register. Only resource manager. group manager and domain owner can access this register. For write. group manager must write its owen domain ID. otherwise write accessing will.." hexmask.long.byte 0x0 0.--3. 1. "DID,accessing DOM_SEC_PER and DOM_PRI_PER register" repeat.end repeat 16. (list 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1A 0x1B 0x1C 0x1D 0x1E 0x1F )(list 0x340 0x374 0x3A8 0x3DC 0x410 0x444 0x478 0x4AC 0x4E0 0x514 0x548 0x57C 0x5B0 0x5E4 0x618 0x64C ) group.long ($2+0x2430)++0x3 line.long 0x0 "DOM_ASSIGN_$1,Use to assign domain for accessing DOM_SEC_PER and DOM_PRI_PER register. Only resource manager. group manager and domain owner can access this register. For write. group manager must write its owen domain ID. otherwise write accessing will.." hexmask.long.byte 0x0 0.--3. 1. "DID,accessing DOM_SEC_PER and DOM_PRI_PER register" repeat.end repeat 16. (list 0x20 0x21 0x22 0x23 0x24 0x25 0x26 0x27 0x28 0x29 0x2A 0x2B 0x2C 0x2D 0x2E 0x2F )(list 0x680 0x6B4 0x6E8 0x71C 0x750 0x784 0x7B8 0x7EC 0x820 0x854 0x888 0x8BC 0x8F0 0x924 0x958 0x98C ) group.long ($2+0x2430)++0x3 line.long 0x0 "DOM_ASSIGN_$1,Use to assign domain for accessing DOM_SEC_PER and DOM_PRI_PER register. Only resource manager. group manager and domain owner can access this register. For write. group manager must write its owen domain ID. otherwise write accessing will.." hexmask.long.byte 0x0 0.--3. 1. "DID,accessing DOM_SEC_PER and DOM_PRI_PER register" repeat.end repeat 16. (list 0x30 0x31 0x32 0x33 0x34 0x35 0x36 0x37 0x38 0x39 0x3A 0x3B 0x3C 0x3D 0x3E 0x3F )(list 0x9C0 0x9F4 0xA28 0xA5C 0xA90 0xAC4 0xAF8 0xB2C 0xB60 0xB94 0xBC8 0xBFC 0xC30 0xC64 0xC98 0xCCC ) group.long ($2+0x2430)++0x3 line.long 0x0 "DOM_ASSIGN_$1,Use to assign domain for accessing DOM_SEC_PER and DOM_PRI_PER register. Only resource manager. group manager and domain owner can access this register. For write. group manager must write its owen domain ID. otherwise write accessing will.." hexmask.long.byte 0x0 0.--3. 1. "DID,accessing DOM_SEC_PER and DOM_PRI_PER register" repeat.end repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x38 0x70 0xA8 0xE0 0x118 0x150 0x188 0x1C0 0x1F8 0x230 0x268 0x2A0 0x2D8 0x310 0x348 ) group.long ($2+0x3100)++0x3 line.long 0x0 "RGN_DOM_$1,Assign domain for peripheral. It can be only configured by resource and group manager" bitfld.long 0x0 31. "LOCK,When this bit is set lock write for all the bits in the register." "0,1" bitfld.long 0x0 4. "SET,Set together with DID would change permission of this resource to following setting: 1) Domain access control enabled. 2) Read/Write allowed for the domain owner. 3) Read/Write not allowed for all the other domains. If this bit is not set only DID.." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Assign domain for peripheral" repeat.end repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x38 0x70 0xA8 0xE0 0x118 0x150 0x188 0x1C0 0x1F8 0x230 0x268 0x2A0 0x2D8 0x310 0x348 ) group.long ($2+0x3104)++0x3 line.long 0x0 "RGN_DOM_PER0_$1,Domain Permission Control. It can be only configured by resource manager and domain owner." bitfld.long 0x0 31. "DOM7_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 29.--30. "DOM7_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 28. "DOM7_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 27. "DOM6_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 25.--26. "DOM6_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" newline bitfld.long 0x0 24. "DOM6_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 23. "DOM5_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 21.--22. "DOM5_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 20. "DOM5_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 19. "DOM4_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" newline bitfld.long 0x0 17.--18. "DOM4_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM4_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 15. "DOM3_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 13.--14. "DOM3_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 12. "DOM3_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" newline bitfld.long 0x0 11. "DOM2_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 9.--10. "DOM2_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM2_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 7. "DOM1_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 5.--6. "DOM1_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" newline bitfld.long 0x0 4. "DOM1_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 3. "DOM0_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 1.--2. "DOM0_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM0_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" repeat.end repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x38 0x70 0xA8 0xE0 0x118 0x150 0x188 0x1C0 0x1F8 0x230 0x268 0x2A0 0x2D8 0x310 0x348 ) group.long ($2+0x3108)++0x3 line.long 0x0 "RGN_DOM_PER1_$1,Domain Permission Control. It can be only configured by resource manager and domain owner." bitfld.long 0x0 31. "DOM15_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 29.--30. "DOM15_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 28. "DOM15_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 27. "DOM14_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 25.--26. "DOM14_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" newline bitfld.long 0x0 24. "DOM14_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 23. "DOM13_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 21.--22. "DOM13_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 20. "DOM13_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 19. "DOM12_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" newline bitfld.long 0x0 17.--18. "DOM12_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM12_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 15. "DOM11_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 13.--14. "DOM11_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 12. "DOM11_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" newline bitfld.long 0x0 11. "DOM10_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 9.--10. "DOM10_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM10_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 7. "DOM9_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 5.--6. "DOM9_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" newline bitfld.long 0x0 4. "DOM9_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 3. "DOM8_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 1.--2. "DOM8_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM8_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" repeat.end repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x38 0x70 0xA8 0xE0 0x118 0x150 0x188 0x1C0 0x1F8 0x230 0x268 0x2A0 0x2D8 0x310 0x348 ) group.long ($2+0x310C)++0x3 line.long 0x0 "RGN_SEC_PER0_$1,This register is only used for resource manager to control secure access permission." bitfld.long 0x0 31. "DOM3_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM3_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM3_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM3_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM2_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM2_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM2_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM2_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM1_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM1_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM1_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM1_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM0_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM0_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM0_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM0_SEC_EN,Domain secure permission control enable" "0,1" repeat.end repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x38 0x70 0xA8 0xE0 0x118 0x150 0x188 0x1C0 0x1F8 0x230 0x268 0x2A0 0x2D8 0x310 0x348 ) group.long ($2+0x3110)++0x3 line.long 0x0 "RGN_SEC_PER1_$1,This register is only used for resource manager to control secure access permission." bitfld.long 0x0 31. "DOM7_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM7_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM7_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM7_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM6_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM6_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM6_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM6_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM5_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM5_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM5_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM5_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM4_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM4_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM4_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM4_SEC_EN,Domain secure permission control enable" "0,1" repeat.end repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x38 0x70 0xA8 0xE0 0x118 0x150 0x188 0x1C0 0x1F8 0x230 0x268 0x2A0 0x2D8 0x310 0x348 ) group.long ($2+0x3114)++0x3 line.long 0x0 "RGN_SEC_PER2_$1,This register is only used for resource manager to control secure access permission." bitfld.long 0x0 31. "DOM11_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM11_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM11_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM11_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM10_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM10_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM10_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM10_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM9_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM9_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM9_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM9_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM8_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM8_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM8_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM8_SEC_EN,Domain secure permission control enable" "0,1" repeat.end repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x38 0x70 0xA8 0xE0 0x118 0x150 0x188 0x1C0 0x1F8 0x230 0x268 0x2A0 0x2D8 0x310 0x348 ) group.long ($2+0x3118)++0x3 line.long 0x0 "RGN_SEC_PER3_$1,This register is only used for resource manager to control secure access permission." bitfld.long 0x0 31. "DOM15_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM15_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM15_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM15_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM14_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM14_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM14_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM14_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM13_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM13_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM13_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM13_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM12_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM12_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM12_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM12_SEC_EN,Domain secure permission control enable" "0,1" repeat.end repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x38 0x70 0xA8 0xE0 0x118 0x150 0x188 0x1C0 0x1F8 0x230 0x268 0x2A0 0x2D8 0x310 0x348 ) group.long ($2+0x311C)++0x3 line.long 0x0 "RGN_PRI_PER0_$1,This register is only used for resource manager to control privileged access permission." bitfld.long 0x0 31. "DOM3_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM3_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM3_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM3_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM2_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM2_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM2_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM2_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM1_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM1_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM1_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM1_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM0_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM0_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM0_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM0_PRI_EN,Domain privileged permission control enable" "0,1" repeat.end repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x38 0x70 0xA8 0xE0 0x118 0x150 0x188 0x1C0 0x1F8 0x230 0x268 0x2A0 0x2D8 0x310 0x348 ) group.long ($2+0x3120)++0x3 line.long 0x0 "RGN_PRI_PER1_$1,This register is only used for resource manager to control privileged access permission." bitfld.long 0x0 31. "DOM7_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM7_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM7_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM7_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM6_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM6_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM6_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM6_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM5_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM5_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM5_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM5_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM4_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM4_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM4_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM4_PRI_EN,Domain privileged permission control enable" "0,1" repeat.end repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x38 0x70 0xA8 0xE0 0x118 0x150 0x188 0x1C0 0x1F8 0x230 0x268 0x2A0 0x2D8 0x310 0x348 ) group.long ($2+0x3124)++0x3 line.long 0x0 "RGN_PRI_PER2_$1,This register is only used for resource manager to control privileged access permission." bitfld.long 0x0 31. "DOM11_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM11_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM11_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM11_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM10_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM10_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM10_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM10_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM9_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM9_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM9_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM9_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM8_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM8_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM8_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM8_PRI_EN,Domain privileged permission control enable" "0,1" repeat.end repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x38 0x70 0xA8 0xE0 0x118 0x150 0x188 0x1C0 0x1F8 0x230 0x268 0x2A0 0x2D8 0x310 0x348 ) group.long ($2+0x3128)++0x3 line.long 0x0 "RGN_PRI_PER3_$1,This register is only used for resource manager to control privileged access permission." bitfld.long 0x0 31. "DOM15_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM15_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM15_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM15_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM14_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM14_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM14_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM14_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM13_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM13_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM13_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM13_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM12_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM12_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM12_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM12_PRI_EN,Domain privileged permission control enable" "0,1" repeat.end repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x38 0x70 0xA8 0xE0 0x118 0x150 0x188 0x1C0 0x1F8 0x230 0x268 0x2A0 0x2D8 0x310 0x348 ) group.long ($2+0x312C)++0x3 line.long 0x0 "RGN_DOM_SEC_PER_$1,This register is only used for domain master to control secure access permission. When the domain master write this register. it only changes the secure permission for itself. When the domain master read this register. it gets.." bitfld.long 0x0 7. "DOM_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" newline bitfld.long 0x0 0. "DOM_SEC_EN,Domain secure permission control enable" "0,1" repeat.end repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x38 0x70 0xA8 0xE0 0x118 0x150 0x188 0x1C0 0x1F8 0x230 0x268 0x2A0 0x2D8 0x310 0x348 ) group.long ($2+0x3130)++0x3 line.long 0x0 "RGN_DOM_PRI_PER_$1,This register is only used for domain master to control secure access permission. When the domain master write this register. it only changes the secure permission for itself. When the domain master read this register. it gets.." bitfld.long 0x0 7. "DOM_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" newline bitfld.long 0x0 0. "DOM_PRI_EN,Domain privileged permission control enable" "0,1" repeat.end repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x38 0x70 0xA8 0xE0 0x118 0x150 0x188 0x1C0 0x1F8 0x230 0x268 0x2A0 0x2D8 0x310 0x348 ) group.long ($2+0x3134)++0x3 line.long 0x0 "RGN_DOM_ASSIGN_$1,Use to assign domain for accessing DOM_SEC_PER and DOM_PRI_PER register. Only resource manager. group manager and domain owner can access this register. For write. group manager must write its owen domain ID. otherwise write accessing.." hexmask.long.byte 0x0 0.--3. 1. "DID,accessing DOM_SEC_PER and DOM_PRI_PER register" repeat.end tree.end tree "RPC_AP_GLOBAL" base ad:0x38FFE000 repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x4 0x8 0xC 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C ) group.long ($2)++0x3 line.long 0x0 "REGG0_DOM_$1,Assign domain for CKGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1A 0x1B 0x1C 0x1D 0x1E 0x1F )(list 0x40 0x44 0x48 0x4C 0x50 0x54 0x58 0x5C 0x60 0x64 0x68 0x6C 0x70 0x74 0x78 0x7C ) group.long ($2)++0x3 line.long 0x0 "REGG0_DOM_$1,Assign domain for CKGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x20 0x21 0x22 0x23 0x24 0x25 0x26 0x27 0x28 0x29 0x2A 0x2B 0x2C 0x2D 0x2E 0x2F )(list 0x80 0x84 0x88 0x8C 0x90 0x94 0x98 0x9C 0xA0 0xA4 0xA8 0xAC 0xB0 0xB4 0xB8 0xBC ) group.long ($2)++0x3 line.long 0x0 "REGG0_DOM_$1,Assign domain for CKGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x30 0x31 0x32 0x33 0x34 0x35 0x36 0x37 0x38 0x39 0x3A 0x3B 0x3C 0x3D 0x3E 0x3F )(list 0xC0 0xC4 0xC8 0xCC 0xD0 0xD4 0xD8 0xDC 0xE0 0xE4 0xE8 0xEC 0xF0 0xF4 0xF8 0xFC ) group.long ($2)++0x3 line.long 0x0 "REGG0_DOM_$1,Assign domain for CKGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x40 0x41 0x42 0x43 0x44 0x45 0x46 0x47 0x48 0x49 0x4A 0x4B 0x4C 0x4D 0x4E 0x4F )(list 0x100 0x104 0x108 0x10C 0x110 0x114 0x118 0x11C 0x120 0x124 0x128 0x12C 0x130 0x134 0x138 0x13C ) group.long ($2)++0x3 line.long 0x0 "REGG0_DOM_$1,Assign domain for CKGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x50 0x51 0x52 0x53 0x54 0x55 0x56 0x57 0x58 0x59 0x5A 0x5B 0x5C 0x5D 0x5E 0x5F )(list 0x140 0x144 0x148 0x14C 0x150 0x154 0x158 0x15C 0x160 0x164 0x168 0x16C 0x170 0x174 0x178 0x17C ) group.long ($2)++0x3 line.long 0x0 "REGG0_DOM_$1,Assign domain for CKGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x60 0x61 0x62 0x63 0x64 0x65 0x66 0x67 0x68 0x69 0x6A 0x6B 0x6C 0x6D 0x6E 0x6F )(list 0x180 0x184 0x188 0x18C 0x190 0x194 0x198 0x19C 0x1A0 0x1A4 0x1A8 0x1AC 0x1B0 0x1B4 0x1B8 0x1BC ) group.long ($2)++0x3 line.long 0x0 "REGG0_DOM_$1,Assign domain for CKGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x70 0x71 0x72 0x73 0x74 0x75 0x76 0x77 0x78 0x79 0x7A 0x7B 0x7C 0x7D 0x7E 0x7F )(list 0x1C0 0x1C4 0x1C8 0x1CC 0x1D0 0x1D4 0x1D8 0x1DC 0x1E0 0x1E4 0x1E8 0x1EC 0x1F0 0x1F4 0x1F8 0x1FC ) group.long ($2)++0x3 line.long 0x0 "REGG0_DOM_$1,Assign domain for CKGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x80 0x81 0x82 0x83 0x84 0x85 0x86 0x87 0x88 0x89 0x8A 0x8B 0x8C 0x8D 0x8E 0x8F )(list 0x200 0x204 0x208 0x20C 0x210 0x214 0x218 0x21C 0x220 0x224 0x228 0x22C 0x230 0x234 0x238 0x23C ) group.long ($2)++0x3 line.long 0x0 "REGG0_DOM_$1,Assign domain for CKGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x90 0x91 0x92 0x93 0x94 0x95 0x96 0x97 0x98 0x99 0x9A 0x9B 0x9C 0x9D 0x9E 0x9F )(list 0x240 0x244 0x248 0x24C 0x250 0x254 0x258 0x25C 0x260 0x264 0x268 0x26C 0x270 0x274 0x278 0x27C ) group.long ($2)++0x3 line.long 0x0 "REGG0_DOM_$1,Assign domain for CKGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xA0 0xA1 0xA2 0xA3 0xA4 0xA5 0xA6 0xA7 0xA8 0xA9 0xAA 0xAB 0xAC 0xAD 0xAE 0xAF )(list 0x280 0x284 0x288 0x28C 0x290 0x294 0x298 0x29C 0x2A0 0x2A4 0x2A8 0x2AC 0x2B0 0x2B4 0x2B8 0x2BC ) group.long ($2)++0x3 line.long 0x0 "REGG0_DOM_$1,Assign domain for CKGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xB0 0xB1 0xB2 0xB3 0xB4 0xB5 0xB6 0xB7 0xB8 0xB9 0xBA 0xBB 0xBC 0xBD 0xBE 0xBF )(list 0x2C0 0x2C4 0x2C8 0x2CC 0x2D0 0x2D4 0x2D8 0x2DC 0x2E0 0x2E4 0x2E8 0x2EC 0x2F0 0x2F4 0x2F8 0x2FC ) group.long ($2)++0x3 line.long 0x0 "REGG0_DOM_$1,Assign domain for CKGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xC0 0xC1 0xC2 0xC3 0xC4 0xC5 0xC6 0xC7 0xC8 0xC9 0xCA 0xCB 0xCC 0xCD 0xCE 0xCF )(list 0x300 0x304 0x308 0x30C 0x310 0x314 0x318 0x31C 0x320 0x324 0x328 0x32C 0x330 0x334 0x338 0x33C ) group.long ($2)++0x3 line.long 0x0 "REGG0_DOM_$1,Assign domain for CKGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xD0 0xD1 0xD2 0xD3 0xD4 0xD5 0xD6 0xD7 0xD8 0xD9 0xDA 0xDB 0xDC 0xDD 0xDE 0xDF )(list 0x340 0x344 0x348 0x34C 0x350 0x354 0x358 0x35C 0x360 0x364 0x368 0x36C 0x370 0x374 0x378 0x37C ) group.long ($2)++0x3 line.long 0x0 "REGG0_DOM_$1,Assign domain for CKGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xE0 0xE1 0xE2 0xE3 0xE4 0xE5 0xE6 0xE7 0xE8 0xE9 0xEA 0xEB 0xEC 0xED 0xEE 0xEF )(list 0x380 0x384 0x388 0x38C 0x390 0x394 0x398 0x39C 0x3A0 0x3A4 0x3A8 0x3AC 0x3B0 0x3B4 0x3B8 0x3BC ) group.long ($2)++0x3 line.long 0x0 "REGG0_DOM_$1,Assign domain for CKGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xF0 0xF1 0xF2 0xF3 0xF4 0xF5 0xF6 0xF7 0xF8 0xF9 0xFA 0xFB 0xFC 0xFD 0xFE 0xFF )(list 0x3C0 0x3C4 0x3C8 0x3CC 0x3D0 0x3D4 0x3D8 0x3DC 0x3E0 0x3E4 0x3E8 0x3EC 0x3F0 0x3F4 0x3F8 0x3FC ) group.long ($2)++0x3 line.long 0x0 "REGG0_DOM_$1,Assign domain for CKGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x4 0x8 0xC 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C ) group.long ($2+0x400)++0x3 line.long 0x0 "REGG1_DOM_$1,Assign domain for CKGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1A 0x1B 0x1C 0x1D 0x1E 0x1F )(list 0x40 0x44 0x48 0x4C 0x50 0x54 0x58 0x5C 0x60 0x64 0x68 0x6C 0x70 0x74 0x78 0x7C ) group.long ($2+0x400)++0x3 line.long 0x0 "REGG1_DOM_$1,Assign domain for CKGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x20 0x21 0x22 0x23 0x24 0x25 0x26 0x27 0x28 0x29 0x2A 0x2B 0x2C 0x2D 0x2E 0x2F )(list 0x80 0x84 0x88 0x8C 0x90 0x94 0x98 0x9C 0xA0 0xA4 0xA8 0xAC 0xB0 0xB4 0xB8 0xBC ) group.long ($2+0x400)++0x3 line.long 0x0 "REGG1_DOM_$1,Assign domain for CKGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x30 0x31 0x32 0x33 0x34 0x35 0x36 0x37 0x38 0x39 0x3A 0x3B 0x3C 0x3D 0x3E 0x3F )(list 0xC0 0xC4 0xC8 0xCC 0xD0 0xD4 0xD8 0xDC 0xE0 0xE4 0xE8 0xEC 0xF0 0xF4 0xF8 0xFC ) group.long ($2+0x400)++0x3 line.long 0x0 "REGG1_DOM_$1,Assign domain for CKGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x40 0x41 0x42 0x43 0x44 0x45 0x46 0x47 0x48 0x49 0x4A 0x4B 0x4C 0x4D 0x4E 0x4F )(list 0x100 0x104 0x108 0x10C 0x110 0x114 0x118 0x11C 0x120 0x124 0x128 0x12C 0x130 0x134 0x138 0x13C ) group.long ($2+0x400)++0x3 line.long 0x0 "REGG1_DOM_$1,Assign domain for CKGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x50 0x51 0x52 0x53 0x54 0x55 0x56 0x57 0x58 0x59 0x5A 0x5B 0x5C 0x5D 0x5E 0x5F )(list 0x140 0x144 0x148 0x14C 0x150 0x154 0x158 0x15C 0x160 0x164 0x168 0x16C 0x170 0x174 0x178 0x17C ) group.long ($2+0x400)++0x3 line.long 0x0 "REGG1_DOM_$1,Assign domain for CKGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x60 0x61 0x62 0x63 0x64 0x65 0x66 0x67 0x68 0x69 0x6A 0x6B 0x6C 0x6D 0x6E 0x6F )(list 0x180 0x184 0x188 0x18C 0x190 0x194 0x198 0x19C 0x1A0 0x1A4 0x1A8 0x1AC 0x1B0 0x1B4 0x1B8 0x1BC ) group.long ($2+0x400)++0x3 line.long 0x0 "REGG1_DOM_$1,Assign domain for CKGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x70 0x71 0x72 0x73 0x74 0x75 0x76 0x77 0x78 0x79 0x7A 0x7B 0x7C 0x7D 0x7E 0x7F )(list 0x1C0 0x1C4 0x1C8 0x1CC 0x1D0 0x1D4 0x1D8 0x1DC 0x1E0 0x1E4 0x1E8 0x1EC 0x1F0 0x1F4 0x1F8 0x1FC ) group.long ($2+0x400)++0x3 line.long 0x0 "REGG1_DOM_$1,Assign domain for CKGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x80 0x81 0x82 0x83 0x84 0x85 0x86 0x87 0x88 0x89 0x8A 0x8B 0x8C 0x8D 0x8E 0x8F )(list 0x200 0x204 0x208 0x20C 0x210 0x214 0x218 0x21C 0x220 0x224 0x228 0x22C 0x230 0x234 0x238 0x23C ) group.long ($2+0x400)++0x3 line.long 0x0 "REGG1_DOM_$1,Assign domain for CKGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x90 0x91 0x92 0x93 0x94 0x95 0x96 0x97 0x98 0x99 0x9A 0x9B 0x9C 0x9D 0x9E 0x9F )(list 0x240 0x244 0x248 0x24C 0x250 0x254 0x258 0x25C 0x260 0x264 0x268 0x26C 0x270 0x274 0x278 0x27C ) group.long ($2+0x400)++0x3 line.long 0x0 "REGG1_DOM_$1,Assign domain for CKGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xA0 0xA1 0xA2 0xA3 0xA4 0xA5 0xA6 0xA7 0xA8 0xA9 0xAA 0xAB 0xAC 0xAD 0xAE 0xAF )(list 0x280 0x284 0x288 0x28C 0x290 0x294 0x298 0x29C 0x2A0 0x2A4 0x2A8 0x2AC 0x2B0 0x2B4 0x2B8 0x2BC ) group.long ($2+0x400)++0x3 line.long 0x0 "REGG1_DOM_$1,Assign domain for CKGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xB0 0xB1 0xB2 0xB3 0xB4 0xB5 0xB6 0xB7 0xB8 0xB9 0xBA 0xBB 0xBC 0xBD 0xBE 0xBF )(list 0x2C0 0x2C4 0x2C8 0x2CC 0x2D0 0x2D4 0x2D8 0x2DC 0x2E0 0x2E4 0x2E8 0x2EC 0x2F0 0x2F4 0x2F8 0x2FC ) group.long ($2+0x400)++0x3 line.long 0x0 "REGG1_DOM_$1,Assign domain for CKGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xC0 0xC1 0xC2 0xC3 0xC4 0xC5 0xC6 0xC7 0xC8 0xC9 0xCA 0xCB 0xCC 0xCD 0xCE 0xCF )(list 0x300 0x304 0x308 0x30C 0x310 0x314 0x318 0x31C 0x320 0x324 0x328 0x32C 0x330 0x334 0x338 0x33C ) group.long ($2+0x400)++0x3 line.long 0x0 "REGG1_DOM_$1,Assign domain for CKGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xD0 0xD1 0xD2 0xD3 0xD4 0xD5 0xD6 0xD7 0xD8 0xD9 0xDA 0xDB 0xDC 0xDD 0xDE 0xDF )(list 0x340 0x344 0x348 0x34C 0x350 0x354 0x358 0x35C 0x360 0x364 0x368 0x36C 0x370 0x374 0x378 0x37C ) group.long ($2+0x400)++0x3 line.long 0x0 "REGG1_DOM_$1,Assign domain for CKGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xE0 0xE1 0xE2 0xE3 0xE4 0xE5 0xE6 0xE7 0xE8 0xE9 0xEA 0xEB 0xEC 0xED 0xEE 0xEF )(list 0x380 0x384 0x388 0x38C 0x390 0x394 0x398 0x39C 0x3A0 0x3A4 0x3A8 0x3AC 0x3B0 0x3B4 0x3B8 0x3BC ) group.long ($2+0x400)++0x3 line.long 0x0 "REGG1_DOM_$1,Assign domain for CKGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xF0 0xF1 0xF2 0xF3 0xF4 0xF5 0xF6 0xF7 0xF8 0xF9 0xFA 0xFB 0xFC 0xFD 0xFE 0xFF )(list 0x3C0 0x3C4 0x3C8 0x3CC 0x3D0 0x3D4 0x3D8 0x3DC 0x3E0 0x3E4 0x3E8 0x3EC 0x3F0 0x3F4 0x3F8 0x3FC ) group.long ($2+0x400)++0x3 line.long 0x0 "REGG1_DOM_$1,Assign domain for CKGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x4 0x8 0xC 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C ) group.long ($2+0x800)++0x3 line.long 0x0 "REGG2_DOM_$1,Assign domain for SCR registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1A 0x1B 0x1C 0x1D 0x1E 0x1F )(list 0x40 0x44 0x48 0x4C 0x50 0x54 0x58 0x5C 0x60 0x64 0x68 0x6C 0x70 0x74 0x78 0x7C ) group.long ($2+0x800)++0x3 line.long 0x0 "REGG2_DOM_$1,Assign domain for SCR registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x20 0x21 0x22 0x23 0x24 0x25 0x26 0x27 0x28 0x29 0x2A 0x2B 0x2C 0x2D 0x2E 0x2F )(list 0x80 0x84 0x88 0x8C 0x90 0x94 0x98 0x9C 0xA0 0xA4 0xA8 0xAC 0xB0 0xB4 0xB8 0xBC ) group.long ($2+0x800)++0x3 line.long 0x0 "REGG2_DOM_$1,Assign domain for SCR registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x30 0x31 0x32 0x33 0x34 0x35 0x36 0x37 0x38 0x39 0x3A 0x3B 0x3C 0x3D 0x3E 0x3F )(list 0xC0 0xC4 0xC8 0xCC 0xD0 0xD4 0xD8 0xDC 0xE0 0xE4 0xE8 0xEC 0xF0 0xF4 0xF8 0xFC ) group.long ($2+0x800)++0x3 line.long 0x0 "REGG2_DOM_$1,Assign domain for SCR registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x40 0x41 0x42 0x43 0x44 0x45 0x46 0x47 0x48 0x49 0x4A 0x4B 0x4C 0x4D 0x4E 0x4F )(list 0x100 0x104 0x108 0x10C 0x110 0x114 0x118 0x11C 0x120 0x124 0x128 0x12C 0x130 0x134 0x138 0x13C ) group.long ($2+0x800)++0x3 line.long 0x0 "REGG2_DOM_$1,Assign domain for SCR registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x50 0x51 0x52 0x53 0x54 0x55 0x56 0x57 0x58 0x59 0x5A 0x5B 0x5C 0x5D 0x5E 0x5F )(list 0x140 0x144 0x148 0x14C 0x150 0x154 0x158 0x15C 0x160 0x164 0x168 0x16C 0x170 0x174 0x178 0x17C ) group.long ($2+0x800)++0x3 line.long 0x0 "REGG2_DOM_$1,Assign domain for SCR registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x60 0x61 0x62 0x63 0x64 0x65 0x66 0x67 0x68 0x69 0x6A 0x6B 0x6C 0x6D 0x6E 0x6F )(list 0x180 0x184 0x188 0x18C 0x190 0x194 0x198 0x19C 0x1A0 0x1A4 0x1A8 0x1AC 0x1B0 0x1B4 0x1B8 0x1BC ) group.long ($2+0x800)++0x3 line.long 0x0 "REGG2_DOM_$1,Assign domain for SCR registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x70 0x71 0x72 0x73 0x74 0x75 0x76 0x77 0x78 0x79 0x7A 0x7B 0x7C 0x7D 0x7E 0x7F )(list 0x1C0 0x1C4 0x1C8 0x1CC 0x1D0 0x1D4 0x1D8 0x1DC 0x1E0 0x1E4 0x1E8 0x1EC 0x1F0 0x1F4 0x1F8 0x1FC ) group.long ($2+0x800)++0x3 line.long 0x0 "REGG2_DOM_$1,Assign domain for SCR registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x80 0x81 0x82 0x83 0x84 0x85 0x86 0x87 0x88 0x89 0x8A 0x8B 0x8C 0x8D 0x8E 0x8F )(list 0x200 0x204 0x208 0x20C 0x210 0x214 0x218 0x21C 0x220 0x224 0x228 0x22C 0x230 0x234 0x238 0x23C ) group.long ($2+0x800)++0x3 line.long 0x0 "REGG2_DOM_$1,Assign domain for SCR registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x90 0x91 0x92 0x93 0x94 0x95 0x96 0x97 0x98 0x99 0x9A 0x9B 0x9C 0x9D 0x9E 0x9F )(list 0x240 0x244 0x248 0x24C 0x250 0x254 0x258 0x25C 0x260 0x264 0x268 0x26C 0x270 0x274 0x278 0x27C ) group.long ($2+0x800)++0x3 line.long 0x0 "REGG2_DOM_$1,Assign domain for SCR registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xA0 0xA1 0xA2 0xA3 0xA4 0xA5 0xA6 0xA7 0xA8 0xA9 0xAA 0xAB 0xAC 0xAD 0xAE 0xAF )(list 0x280 0x284 0x288 0x28C 0x290 0x294 0x298 0x29C 0x2A0 0x2A4 0x2A8 0x2AC 0x2B0 0x2B4 0x2B8 0x2BC ) group.long ($2+0x800)++0x3 line.long 0x0 "REGG2_DOM_$1,Assign domain for SCR registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xB0 0xB1 0xB2 0xB3 0xB4 0xB5 0xB6 0xB7 0xB8 0xB9 0xBA 0xBB 0xBC 0xBD 0xBE 0xBF )(list 0x2C0 0x2C4 0x2C8 0x2CC 0x2D0 0x2D4 0x2D8 0x2DC 0x2E0 0x2E4 0x2E8 0x2EC 0x2F0 0x2F4 0x2F8 0x2FC ) group.long ($2+0x800)++0x3 line.long 0x0 "REGG2_DOM_$1,Assign domain for SCR registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xC0 0xC1 0xC2 0xC3 0xC4 0xC5 0xC6 0xC7 0xC8 0xC9 0xCA 0xCB 0xCC 0xCD 0xCE 0xCF )(list 0x300 0x304 0x308 0x30C 0x310 0x314 0x318 0x31C 0x320 0x324 0x328 0x32C 0x330 0x334 0x338 0x33C ) group.long ($2+0x800)++0x3 line.long 0x0 "REGG2_DOM_$1,Assign domain for SCR registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xD0 0xD1 0xD2 0xD3 0xD4 0xD5 0xD6 0xD7 0xD8 0xD9 0xDA 0xDB 0xDC 0xDD 0xDE 0xDF )(list 0x340 0x344 0x348 0x34C 0x350 0x354 0x358 0x35C 0x360 0x364 0x368 0x36C 0x370 0x374 0x378 0x37C ) group.long ($2+0x800)++0x3 line.long 0x0 "REGG2_DOM_$1,Assign domain for SCR registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xE0 0xE1 0xE2 0xE3 0xE4 0xE5 0xE6 0xE7 0xE8 0xE9 0xEA 0xEB 0xEC 0xED 0xEE 0xEF )(list 0x380 0x384 0x388 0x38C 0x390 0x394 0x398 0x39C 0x3A0 0x3A4 0x3A8 0x3AC 0x3B0 0x3B4 0x3B8 0x3BC ) group.long ($2+0x800)++0x3 line.long 0x0 "REGG2_DOM_$1,Assign domain for SCR registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xF0 0xF1 0xF2 0xF3 0xF4 0xF5 0xF6 0xF7 0xF8 0xF9 0xFA 0xFB 0xFC 0xFD 0xFE 0xFF )(list 0x3C0 0x3C4 0x3C8 0x3CC 0x3D0 0x3D4 0x3D8 0x3DC 0x3E0 0x3E4 0x3E8 0x3EC 0x3F0 0x3F4 0x3F8 0x3FC ) group.long ($2+0x800)++0x3 line.long 0x0 "REGG2_DOM_$1,Assign domain for SCR registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x4 0x8 0xC 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C ) group.long ($2+0xC00)++0x3 line.long 0x0 "REGG3_DOM_$1,Assign domain for SCR registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1A 0x1B 0x1C 0x1D 0x1E 0x1F )(list 0x40 0x44 0x48 0x4C 0x50 0x54 0x58 0x5C 0x60 0x64 0x68 0x6C 0x70 0x74 0x78 0x7C ) group.long ($2+0xC00)++0x3 line.long 0x0 "REGG3_DOM_$1,Assign domain for SCR registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x20 0x21 0x22 0x23 0x24 0x25 0x26 0x27 0x28 0x29 0x2A 0x2B 0x2C 0x2D 0x2E 0x2F )(list 0x80 0x84 0x88 0x8C 0x90 0x94 0x98 0x9C 0xA0 0xA4 0xA8 0xAC 0xB0 0xB4 0xB8 0xBC ) group.long ($2+0xC00)++0x3 line.long 0x0 "REGG3_DOM_$1,Assign domain for SCR registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x30 0x31 0x32 0x33 0x34 0x35 0x36 0x37 0x38 0x39 0x3A 0x3B 0x3C 0x3D 0x3E 0x3F )(list 0xC0 0xC4 0xC8 0xCC 0xD0 0xD4 0xD8 0xDC 0xE0 0xE4 0xE8 0xEC 0xF0 0xF4 0xF8 0xFC ) group.long ($2+0xC00)++0x3 line.long 0x0 "REGG3_DOM_$1,Assign domain for SCR registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x40 0x41 0x42 0x43 0x44 0x45 0x46 0x47 0x48 0x49 0x4A 0x4B 0x4C 0x4D 0x4E 0x4F )(list 0x100 0x104 0x108 0x10C 0x110 0x114 0x118 0x11C 0x120 0x124 0x128 0x12C 0x130 0x134 0x138 0x13C ) group.long ($2+0xC00)++0x3 line.long 0x0 "REGG3_DOM_$1,Assign domain for SCR registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x50 0x51 0x52 0x53 0x54 0x55 0x56 0x57 0x58 0x59 0x5A 0x5B 0x5C 0x5D 0x5E 0x5F )(list 0x140 0x144 0x148 0x14C 0x150 0x154 0x158 0x15C 0x160 0x164 0x168 0x16C 0x170 0x174 0x178 0x17C ) group.long ($2+0xC00)++0x3 line.long 0x0 "REGG3_DOM_$1,Assign domain for SCR registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x60 0x61 0x62 0x63 0x64 0x65 0x66 0x67 0x68 0x69 0x6A 0x6B 0x6C 0x6D 0x6E 0x6F )(list 0x180 0x184 0x188 0x18C 0x190 0x194 0x198 0x19C 0x1A0 0x1A4 0x1A8 0x1AC 0x1B0 0x1B4 0x1B8 0x1BC ) group.long ($2+0xC00)++0x3 line.long 0x0 "REGG3_DOM_$1,Assign domain for SCR registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x70 0x71 0x72 0x73 0x74 0x75 0x76 0x77 0x78 0x79 0x7A 0x7B 0x7C 0x7D 0x7E 0x7F )(list 0x1C0 0x1C4 0x1C8 0x1CC 0x1D0 0x1D4 0x1D8 0x1DC 0x1E0 0x1E4 0x1E8 0x1EC 0x1F0 0x1F4 0x1F8 0x1FC ) group.long ($2+0xC00)++0x3 line.long 0x0 "REGG3_DOM_$1,Assign domain for SCR registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x80 0x81 0x82 0x83 0x84 0x85 0x86 0x87 0x88 0x89 0x8A 0x8B 0x8C 0x8D 0x8E 0x8F )(list 0x200 0x204 0x208 0x20C 0x210 0x214 0x218 0x21C 0x220 0x224 0x228 0x22C 0x230 0x234 0x238 0x23C ) group.long ($2+0xC00)++0x3 line.long 0x0 "REGG3_DOM_$1,Assign domain for SCR registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x90 0x91 0x92 0x93 0x94 0x95 0x96 0x97 0x98 0x99 0x9A 0x9B 0x9C 0x9D 0x9E 0x9F )(list 0x240 0x244 0x248 0x24C 0x250 0x254 0x258 0x25C 0x260 0x264 0x268 0x26C 0x270 0x274 0x278 0x27C ) group.long ($2+0xC00)++0x3 line.long 0x0 "REGG3_DOM_$1,Assign domain for SCR registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xA0 0xA1 0xA2 0xA3 0xA4 0xA5 0xA6 0xA7 0xA8 0xA9 0xAA 0xAB 0xAC 0xAD 0xAE 0xAF )(list 0x280 0x284 0x288 0x28C 0x290 0x294 0x298 0x29C 0x2A0 0x2A4 0x2A8 0x2AC 0x2B0 0x2B4 0x2B8 0x2BC ) group.long ($2+0xC00)++0x3 line.long 0x0 "REGG3_DOM_$1,Assign domain for SCR registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xB0 0xB1 0xB2 0xB3 0xB4 0xB5 0xB6 0xB7 0xB8 0xB9 0xBA 0xBB 0xBC 0xBD 0xBE 0xBF )(list 0x2C0 0x2C4 0x2C8 0x2CC 0x2D0 0x2D4 0x2D8 0x2DC 0x2E0 0x2E4 0x2E8 0x2EC 0x2F0 0x2F4 0x2F8 0x2FC ) group.long ($2+0xC00)++0x3 line.long 0x0 "REGG3_DOM_$1,Assign domain for SCR registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xC0 0xC1 0xC2 0xC3 0xC4 0xC5 0xC6 0xC7 0xC8 0xC9 0xCA 0xCB 0xCC 0xCD 0xCE 0xCF )(list 0x300 0x304 0x308 0x30C 0x310 0x314 0x318 0x31C 0x320 0x324 0x328 0x32C 0x330 0x334 0x338 0x33C ) group.long ($2+0xC00)++0x3 line.long 0x0 "REGG3_DOM_$1,Assign domain for SCR registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xD0 0xD1 0xD2 0xD3 0xD4 0xD5 0xD6 0xD7 0xD8 0xD9 0xDA 0xDB 0xDC 0xDD 0xDE 0xDF )(list 0x340 0x344 0x348 0x34C 0x350 0x354 0x358 0x35C 0x360 0x364 0x368 0x36C 0x370 0x374 0x378 0x37C ) group.long ($2+0xC00)++0x3 line.long 0x0 "REGG3_DOM_$1,Assign domain for SCR registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xE0 0xE1 0xE2 0xE3 0xE4 0xE5 0xE6 0xE7 0xE8 0xE9 0xEA 0xEB 0xEC 0xED 0xEE 0xEF )(list 0x380 0x384 0x388 0x38C 0x390 0x394 0x398 0x39C 0x3A0 0x3A4 0x3A8 0x3AC 0x3B0 0x3B4 0x3B8 0x3BC ) group.long ($2+0xC00)++0x3 line.long 0x0 "REGG3_DOM_$1,Assign domain for SCR registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xF0 0xF1 0xF2 0xF3 0xF4 0xF5 0xF6 0xF7 0xF8 0xF9 0xFA 0xFB 0xFC 0xFD 0xFE 0xFF )(list 0x3C0 0x3C4 0x3C8 0x3CC 0x3D0 0x3D4 0x3D8 0x3DC 0x3E0 0x3E4 0x3E8 0x3EC 0x3F0 0x3F4 0x3F8 0x3FC ) group.long ($2+0xC00)++0x3 line.long 0x0 "REGG3_DOM_$1,Assign domain for SCR registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x4 0x8 0xC 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C ) group.long ($2+0x1000)++0x3 line.long 0x0 "REGG4_DOM_$1,Assign domain for RSTGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1A 0x1B 0x1C 0x1D 0x1E 0x1F )(list 0x40 0x44 0x48 0x4C 0x50 0x54 0x58 0x5C 0x60 0x64 0x68 0x6C 0x70 0x74 0x78 0x7C ) group.long ($2+0x1000)++0x3 line.long 0x0 "REGG4_DOM_$1,Assign domain for RSTGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x20 0x21 0x22 0x23 0x24 0x25 0x26 0x27 0x28 0x29 0x2A 0x2B 0x2C 0x2D 0x2E 0x2F )(list 0x80 0x84 0x88 0x8C 0x90 0x94 0x98 0x9C 0xA0 0xA4 0xA8 0xAC 0xB0 0xB4 0xB8 0xBC ) group.long ($2+0x1000)++0x3 line.long 0x0 "REGG4_DOM_$1,Assign domain for RSTGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x30 0x31 0x32 0x33 0x34 0x35 0x36 0x37 0x38 0x39 0x3A 0x3B 0x3C 0x3D 0x3E 0x3F )(list 0xC0 0xC4 0xC8 0xCC 0xD0 0xD4 0xD8 0xDC 0xE0 0xE4 0xE8 0xEC 0xF0 0xF4 0xF8 0xFC ) group.long ($2+0x1000)++0x3 line.long 0x0 "REGG4_DOM_$1,Assign domain for RSTGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x40 0x41 0x42 0x43 0x44 0x45 0x46 0x47 0x48 0x49 0x4A 0x4B 0x4C 0x4D 0x4E 0x4F )(list 0x100 0x104 0x108 0x10C 0x110 0x114 0x118 0x11C 0x120 0x124 0x128 0x12C 0x130 0x134 0x138 0x13C ) group.long ($2+0x1000)++0x3 line.long 0x0 "REGG4_DOM_$1,Assign domain for RSTGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x50 0x51 0x52 0x53 0x54 0x55 0x56 0x57 0x58 0x59 0x5A 0x5B 0x5C 0x5D 0x5E 0x5F )(list 0x140 0x144 0x148 0x14C 0x150 0x154 0x158 0x15C 0x160 0x164 0x168 0x16C 0x170 0x174 0x178 0x17C ) group.long ($2+0x1000)++0x3 line.long 0x0 "REGG4_DOM_$1,Assign domain for RSTGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x60 0x61 0x62 0x63 0x64 0x65 0x66 0x67 0x68 0x69 0x6A 0x6B 0x6C 0x6D 0x6E 0x6F )(list 0x180 0x184 0x188 0x18C 0x190 0x194 0x198 0x19C 0x1A0 0x1A4 0x1A8 0x1AC 0x1B0 0x1B4 0x1B8 0x1BC ) group.long ($2+0x1000)++0x3 line.long 0x0 "REGG4_DOM_$1,Assign domain for RSTGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x70 0x71 0x72 0x73 0x74 0x75 0x76 0x77 0x78 0x79 0x7A 0x7B 0x7C 0x7D 0x7E 0x7F )(list 0x1C0 0x1C4 0x1C8 0x1CC 0x1D0 0x1D4 0x1D8 0x1DC 0x1E0 0x1E4 0x1E8 0x1EC 0x1F0 0x1F4 0x1F8 0x1FC ) group.long ($2+0x1000)++0x3 line.long 0x0 "REGG4_DOM_$1,Assign domain for RSTGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x80 0x81 0x82 0x83 0x84 0x85 0x86 0x87 0x88 0x89 0x8A 0x8B 0x8C 0x8D 0x8E 0x8F )(list 0x200 0x204 0x208 0x20C 0x210 0x214 0x218 0x21C 0x220 0x224 0x228 0x22C 0x230 0x234 0x238 0x23C ) group.long ($2+0x1000)++0x3 line.long 0x0 "REGG4_DOM_$1,Assign domain for RSTGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x90 0x91 0x92 0x93 0x94 0x95 0x96 0x97 0x98 0x99 0x9A 0x9B 0x9C 0x9D 0x9E 0x9F )(list 0x240 0x244 0x248 0x24C 0x250 0x254 0x258 0x25C 0x260 0x264 0x268 0x26C 0x270 0x274 0x278 0x27C ) group.long ($2+0x1000)++0x3 line.long 0x0 "REGG4_DOM_$1,Assign domain for RSTGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xA0 0xA1 0xA2 0xA3 0xA4 0xA5 0xA6 0xA7 0xA8 0xA9 0xAA 0xAB 0xAC 0xAD 0xAE 0xAF )(list 0x280 0x284 0x288 0x28C 0x290 0x294 0x298 0x29C 0x2A0 0x2A4 0x2A8 0x2AC 0x2B0 0x2B4 0x2B8 0x2BC ) group.long ($2+0x1000)++0x3 line.long 0x0 "REGG4_DOM_$1,Assign domain for RSTGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xB0 0xB1 0xB2 0xB3 0xB4 0xB5 0xB6 0xB7 0xB8 0xB9 0xBA 0xBB 0xBC 0xBD 0xBE 0xBF )(list 0x2C0 0x2C4 0x2C8 0x2CC 0x2D0 0x2D4 0x2D8 0x2DC 0x2E0 0x2E4 0x2E8 0x2EC 0x2F0 0x2F4 0x2F8 0x2FC ) group.long ($2+0x1000)++0x3 line.long 0x0 "REGG4_DOM_$1,Assign domain for RSTGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xC0 0xC1 0xC2 0xC3 0xC4 0xC5 0xC6 0xC7 0xC8 0xC9 0xCA 0xCB 0xCC 0xCD 0xCE 0xCF )(list 0x300 0x304 0x308 0x30C 0x310 0x314 0x318 0x31C 0x320 0x324 0x328 0x32C 0x330 0x334 0x338 0x33C ) group.long ($2+0x1000)++0x3 line.long 0x0 "REGG4_DOM_$1,Assign domain for RSTGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xD0 0xD1 0xD2 0xD3 0xD4 0xD5 0xD6 0xD7 0xD8 0xD9 0xDA 0xDB 0xDC 0xDD 0xDE 0xDF )(list 0x340 0x344 0x348 0x34C 0x350 0x354 0x358 0x35C 0x360 0x364 0x368 0x36C 0x370 0x374 0x378 0x37C ) group.long ($2+0x1000)++0x3 line.long 0x0 "REGG4_DOM_$1,Assign domain for RSTGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xE0 0xE1 0xE2 0xE3 0xE4 0xE5 0xE6 0xE7 0xE8 0xE9 0xEA 0xEB 0xEC 0xED 0xEE 0xEF )(list 0x380 0x384 0x388 0x38C 0x390 0x394 0x398 0x39C 0x3A0 0x3A4 0x3A8 0x3AC 0x3B0 0x3B4 0x3B8 0x3BC ) group.long ($2+0x1000)++0x3 line.long 0x0 "REGG4_DOM_$1,Assign domain for RSTGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xF0 0xF1 0xF2 0xF3 0xF4 0xF5 0xF6 0xF7 0xF8 0xF9 0xFA 0xFB 0xFC 0xFD 0xFE 0xFF )(list 0x3C0 0x3C4 0x3C8 0x3CC 0x3D0 0x3D4 0x3D8 0x3DC 0x3E0 0x3E4 0x3E8 0x3EC 0x3F0 0x3F4 0x3F8 0x3FC ) group.long ($2+0x1000)++0x3 line.long 0x0 "REGG4_DOM_$1,Assign domain for RSTGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x4 0x8 0xC 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C ) group.long ($2+0x1400)++0x3 line.long 0x0 "REGG5_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1A 0x1B 0x1C 0x1D 0x1E 0x1F )(list 0x40 0x44 0x48 0x4C 0x50 0x54 0x58 0x5C 0x60 0x64 0x68 0x6C 0x70 0x74 0x78 0x7C ) group.long ($2+0x1400)++0x3 line.long 0x0 "REGG5_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x20 0x21 0x22 0x23 0x24 0x25 0x26 0x27 0x28 0x29 0x2A 0x2B 0x2C 0x2D 0x2E 0x2F )(list 0x80 0x84 0x88 0x8C 0x90 0x94 0x98 0x9C 0xA0 0xA4 0xA8 0xAC 0xB0 0xB4 0xB8 0xBC ) group.long ($2+0x1400)++0x3 line.long 0x0 "REGG5_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x30 0x31 0x32 0x33 0x34 0x35 0x36 0x37 0x38 0x39 0x3A 0x3B 0x3C 0x3D 0x3E 0x3F )(list 0xC0 0xC4 0xC8 0xCC 0xD0 0xD4 0xD8 0xDC 0xE0 0xE4 0xE8 0xEC 0xF0 0xF4 0xF8 0xFC ) group.long ($2+0x1400)++0x3 line.long 0x0 "REGG5_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x40 0x41 0x42 0x43 0x44 0x45 0x46 0x47 0x48 0x49 0x4A 0x4B 0x4C 0x4D 0x4E 0x4F )(list 0x100 0x104 0x108 0x10C 0x110 0x114 0x118 0x11C 0x120 0x124 0x128 0x12C 0x130 0x134 0x138 0x13C ) group.long ($2+0x1400)++0x3 line.long 0x0 "REGG5_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x50 0x51 0x52 0x53 0x54 0x55 0x56 0x57 0x58 0x59 0x5A 0x5B 0x5C 0x5D 0x5E 0x5F )(list 0x140 0x144 0x148 0x14C 0x150 0x154 0x158 0x15C 0x160 0x164 0x168 0x16C 0x170 0x174 0x178 0x17C ) group.long ($2+0x1400)++0x3 line.long 0x0 "REGG5_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x60 0x61 0x62 0x63 0x64 0x65 0x66 0x67 0x68 0x69 0x6A 0x6B 0x6C 0x6D 0x6E 0x6F )(list 0x180 0x184 0x188 0x18C 0x190 0x194 0x198 0x19C 0x1A0 0x1A4 0x1A8 0x1AC 0x1B0 0x1B4 0x1B8 0x1BC ) group.long ($2+0x1400)++0x3 line.long 0x0 "REGG5_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x70 0x71 0x72 0x73 0x74 0x75 0x76 0x77 0x78 0x79 0x7A 0x7B 0x7C 0x7D 0x7E 0x7F )(list 0x1C0 0x1C4 0x1C8 0x1CC 0x1D0 0x1D4 0x1D8 0x1DC 0x1E0 0x1E4 0x1E8 0x1EC 0x1F0 0x1F4 0x1F8 0x1FC ) group.long ($2+0x1400)++0x3 line.long 0x0 "REGG5_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x80 0x81 0x82 0x83 0x84 0x85 0x86 0x87 0x88 0x89 0x8A 0x8B 0x8C 0x8D 0x8E 0x8F )(list 0x200 0x204 0x208 0x20C 0x210 0x214 0x218 0x21C 0x220 0x224 0x228 0x22C 0x230 0x234 0x238 0x23C ) group.long ($2+0x1400)++0x3 line.long 0x0 "REGG5_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x90 0x91 0x92 0x93 0x94 0x95 0x96 0x97 0x98 0x99 0x9A 0x9B 0x9C 0x9D 0x9E 0x9F )(list 0x240 0x244 0x248 0x24C 0x250 0x254 0x258 0x25C 0x260 0x264 0x268 0x26C 0x270 0x274 0x278 0x27C ) group.long ($2+0x1400)++0x3 line.long 0x0 "REGG5_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xA0 0xA1 0xA2 0xA3 0xA4 0xA5 0xA6 0xA7 0xA8 0xA9 0xAA 0xAB 0xAC 0xAD 0xAE 0xAF )(list 0x280 0x284 0x288 0x28C 0x290 0x294 0x298 0x29C 0x2A0 0x2A4 0x2A8 0x2AC 0x2B0 0x2B4 0x2B8 0x2BC ) group.long ($2+0x1400)++0x3 line.long 0x0 "REGG5_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xB0 0xB1 0xB2 0xB3 0xB4 0xB5 0xB6 0xB7 0xB8 0xB9 0xBA 0xBB 0xBC 0xBD 0xBE 0xBF )(list 0x2C0 0x2C4 0x2C8 0x2CC 0x2D0 0x2D4 0x2D8 0x2DC 0x2E0 0x2E4 0x2E8 0x2EC 0x2F0 0x2F4 0x2F8 0x2FC ) group.long ($2+0x1400)++0x3 line.long 0x0 "REGG5_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xC0 0xC1 0xC2 0xC3 0xC4 0xC5 0xC6 0xC7 0xC8 0xC9 0xCA 0xCB 0xCC 0xCD 0xCE 0xCF )(list 0x300 0x304 0x308 0x30C 0x310 0x314 0x318 0x31C 0x320 0x324 0x328 0x32C 0x330 0x334 0x338 0x33C ) group.long ($2+0x1400)++0x3 line.long 0x0 "REGG5_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xD0 0xD1 0xD2 0xD3 0xD4 0xD5 0xD6 0xD7 0xD8 0xD9 0xDA 0xDB 0xDC 0xDD 0xDE 0xDF )(list 0x340 0x344 0x348 0x34C 0x350 0x354 0x358 0x35C 0x360 0x364 0x368 0x36C 0x370 0x374 0x378 0x37C ) group.long ($2+0x1400)++0x3 line.long 0x0 "REGG5_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xE0 0xE1 0xE2 0xE3 0xE4 0xE5 0xE6 0xE7 0xE8 0xE9 0xEA 0xEB 0xEC 0xED 0xEE 0xEF )(list 0x380 0x384 0x388 0x38C 0x390 0x394 0x398 0x39C 0x3A0 0x3A4 0x3A8 0x3AC 0x3B0 0x3B4 0x3B8 0x3BC ) group.long ($2+0x1400)++0x3 line.long 0x0 "REGG5_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xF0 0xF1 0xF2 0xF3 0xF4 0xF5 0xF6 0xF7 0xF8 0xF9 0xFA 0xFB 0xFC 0xFD 0xFE 0xFF )(list 0x3C0 0x3C4 0x3C8 0x3CC 0x3D0 0x3D4 0x3D8 0x3DC 0x3E0 0x3E4 0x3E8 0x3EC 0x3F0 0x3F4 0x3F8 0x3FC ) group.long ($2+0x1400)++0x3 line.long 0x0 "REGG5_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x4 0x8 0xC 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C ) group.long ($2+0x1800)++0x3 line.long 0x0 "REGG6_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1A 0x1B 0x1C 0x1D 0x1E 0x1F )(list 0x40 0x44 0x48 0x4C 0x50 0x54 0x58 0x5C 0x60 0x64 0x68 0x6C 0x70 0x74 0x78 0x7C ) group.long ($2+0x1800)++0x3 line.long 0x0 "REGG6_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x20 0x21 0x22 0x23 0x24 0x25 0x26 0x27 0x28 0x29 0x2A 0x2B 0x2C 0x2D 0x2E 0x2F )(list 0x80 0x84 0x88 0x8C 0x90 0x94 0x98 0x9C 0xA0 0xA4 0xA8 0xAC 0xB0 0xB4 0xB8 0xBC ) group.long ($2+0x1800)++0x3 line.long 0x0 "REGG6_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x30 0x31 0x32 0x33 0x34 0x35 0x36 0x37 0x38 0x39 0x3A 0x3B 0x3C 0x3D 0x3E 0x3F )(list 0xC0 0xC4 0xC8 0xCC 0xD0 0xD4 0xD8 0xDC 0xE0 0xE4 0xE8 0xEC 0xF0 0xF4 0xF8 0xFC ) group.long ($2+0x1800)++0x3 line.long 0x0 "REGG6_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x40 0x41 0x42 0x43 0x44 0x45 0x46 0x47 0x48 0x49 0x4A 0x4B 0x4C 0x4D 0x4E 0x4F )(list 0x100 0x104 0x108 0x10C 0x110 0x114 0x118 0x11C 0x120 0x124 0x128 0x12C 0x130 0x134 0x138 0x13C ) group.long ($2+0x1800)++0x3 line.long 0x0 "REGG6_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x50 0x51 0x52 0x53 0x54 0x55 0x56 0x57 0x58 0x59 0x5A 0x5B 0x5C 0x5D 0x5E 0x5F )(list 0x140 0x144 0x148 0x14C 0x150 0x154 0x158 0x15C 0x160 0x164 0x168 0x16C 0x170 0x174 0x178 0x17C ) group.long ($2+0x1800)++0x3 line.long 0x0 "REGG6_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x60 0x61 0x62 0x63 0x64 0x65 0x66 0x67 0x68 0x69 0x6A 0x6B 0x6C 0x6D 0x6E 0x6F )(list 0x180 0x184 0x188 0x18C 0x190 0x194 0x198 0x19C 0x1A0 0x1A4 0x1A8 0x1AC 0x1B0 0x1B4 0x1B8 0x1BC ) group.long ($2+0x1800)++0x3 line.long 0x0 "REGG6_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x70 0x71 0x72 0x73 0x74 0x75 0x76 0x77 0x78 0x79 0x7A 0x7B 0x7C 0x7D 0x7E 0x7F )(list 0x1C0 0x1C4 0x1C8 0x1CC 0x1D0 0x1D4 0x1D8 0x1DC 0x1E0 0x1E4 0x1E8 0x1EC 0x1F0 0x1F4 0x1F8 0x1FC ) group.long ($2+0x1800)++0x3 line.long 0x0 "REGG6_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x80 0x81 0x82 0x83 0x84 0x85 0x86 0x87 0x88 0x89 0x8A 0x8B 0x8C 0x8D 0x8E 0x8F )(list 0x200 0x204 0x208 0x20C 0x210 0x214 0x218 0x21C 0x220 0x224 0x228 0x22C 0x230 0x234 0x238 0x23C ) group.long ($2+0x1800)++0x3 line.long 0x0 "REGG6_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x90 0x91 0x92 0x93 0x94 0x95 0x96 0x97 0x98 0x99 0x9A 0x9B 0x9C 0x9D 0x9E 0x9F )(list 0x240 0x244 0x248 0x24C 0x250 0x254 0x258 0x25C 0x260 0x264 0x268 0x26C 0x270 0x274 0x278 0x27C ) group.long ($2+0x1800)++0x3 line.long 0x0 "REGG6_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xA0 0xA1 0xA2 0xA3 0xA4 0xA5 0xA6 0xA7 0xA8 0xA9 0xAA 0xAB 0xAC 0xAD 0xAE 0xAF )(list 0x280 0x284 0x288 0x28C 0x290 0x294 0x298 0x29C 0x2A0 0x2A4 0x2A8 0x2AC 0x2B0 0x2B4 0x2B8 0x2BC ) group.long ($2+0x1800)++0x3 line.long 0x0 "REGG6_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xB0 0xB1 0xB2 0xB3 0xB4 0xB5 0xB6 0xB7 0xB8 0xB9 0xBA 0xBB 0xBC 0xBD 0xBE 0xBF )(list 0x2C0 0x2C4 0x2C8 0x2CC 0x2D0 0x2D4 0x2D8 0x2DC 0x2E0 0x2E4 0x2E8 0x2EC 0x2F0 0x2F4 0x2F8 0x2FC ) group.long ($2+0x1800)++0x3 line.long 0x0 "REGG6_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xC0 0xC1 0xC2 0xC3 0xC4 0xC5 0xC6 0xC7 0xC8 0xC9 0xCA 0xCB 0xCC 0xCD 0xCE 0xCF )(list 0x300 0x304 0x308 0x30C 0x310 0x314 0x318 0x31C 0x320 0x324 0x328 0x32C 0x330 0x334 0x338 0x33C ) group.long ($2+0x1800)++0x3 line.long 0x0 "REGG6_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xD0 0xD1 0xD2 0xD3 0xD4 0xD5 0xD6 0xD7 0xD8 0xD9 0xDA 0xDB 0xDC 0xDD 0xDE 0xDF )(list 0x340 0x344 0x348 0x34C 0x350 0x354 0x358 0x35C 0x360 0x364 0x368 0x36C 0x370 0x374 0x378 0x37C ) group.long ($2+0x1800)++0x3 line.long 0x0 "REGG6_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xE0 0xE1 0xE2 0xE3 0xE4 0xE5 0xE6 0xE7 0xE8 0xE9 0xEA 0xEB 0xEC 0xED 0xEE 0xEF )(list 0x380 0x384 0x388 0x38C 0x390 0x394 0x398 0x39C 0x3A0 0x3A4 0x3A8 0x3AC 0x3B0 0x3B4 0x3B8 0x3BC ) group.long ($2+0x1800)++0x3 line.long 0x0 "REGG6_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xF0 0xF1 0xF2 0xF3 0xF4 0xF5 0xF6 0xF7 0xF8 0xF9 0xFA 0xFB 0xFC 0xFD 0xFE 0xFF )(list 0x3C0 0x3C4 0x3C8 0x3CC 0x3D0 0x3D4 0x3D8 0x3DC 0x3E0 0x3E4 0x3E8 0x3EC 0x3F0 0x3F4 0x3F8 0x3FC ) group.long ($2+0x1800)++0x3 line.long 0x0 "REGG6_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x4 0x8 0xC 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C ) group.long ($2+0x1C00)++0x3 line.long 0x0 "REGG7_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1A 0x1B 0x1C 0x1D 0x1E 0x1F )(list 0x40 0x44 0x48 0x4C 0x50 0x54 0x58 0x5C 0x60 0x64 0x68 0x6C 0x70 0x74 0x78 0x7C ) group.long ($2+0x1C00)++0x3 line.long 0x0 "REGG7_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x20 0x21 0x22 0x23 0x24 0x25 0x26 0x27 0x28 0x29 0x2A 0x2B 0x2C 0x2D 0x2E 0x2F )(list 0x80 0x84 0x88 0x8C 0x90 0x94 0x98 0x9C 0xA0 0xA4 0xA8 0xAC 0xB0 0xB4 0xB8 0xBC ) group.long ($2+0x1C00)++0x3 line.long 0x0 "REGG7_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x30 0x31 0x32 0x33 0x34 0x35 0x36 0x37 0x38 0x39 0x3A 0x3B 0x3C 0x3D 0x3E 0x3F )(list 0xC0 0xC4 0xC8 0xCC 0xD0 0xD4 0xD8 0xDC 0xE0 0xE4 0xE8 0xEC 0xF0 0xF4 0xF8 0xFC ) group.long ($2+0x1C00)++0x3 line.long 0x0 "REGG7_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x40 0x41 0x42 0x43 0x44 0x45 0x46 0x47 0x48 0x49 0x4A 0x4B 0x4C 0x4D 0x4E 0x4F )(list 0x100 0x104 0x108 0x10C 0x110 0x114 0x118 0x11C 0x120 0x124 0x128 0x12C 0x130 0x134 0x138 0x13C ) group.long ($2+0x1C00)++0x3 line.long 0x0 "REGG7_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x50 0x51 0x52 0x53 0x54 0x55 0x56 0x57 0x58 0x59 0x5A 0x5B 0x5C 0x5D 0x5E 0x5F )(list 0x140 0x144 0x148 0x14C 0x150 0x154 0x158 0x15C 0x160 0x164 0x168 0x16C 0x170 0x174 0x178 0x17C ) group.long ($2+0x1C00)++0x3 line.long 0x0 "REGG7_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x60 0x61 0x62 0x63 0x64 0x65 0x66 0x67 0x68 0x69 0x6A 0x6B 0x6C 0x6D 0x6E 0x6F )(list 0x180 0x184 0x188 0x18C 0x190 0x194 0x198 0x19C 0x1A0 0x1A4 0x1A8 0x1AC 0x1B0 0x1B4 0x1B8 0x1BC ) group.long ($2+0x1C00)++0x3 line.long 0x0 "REGG7_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x70 0x71 0x72 0x73 0x74 0x75 0x76 0x77 0x78 0x79 0x7A 0x7B 0x7C 0x7D 0x7E 0x7F )(list 0x1C0 0x1C4 0x1C8 0x1CC 0x1D0 0x1D4 0x1D8 0x1DC 0x1E0 0x1E4 0x1E8 0x1EC 0x1F0 0x1F4 0x1F8 0x1FC ) group.long ($2+0x1C00)++0x3 line.long 0x0 "REGG7_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x80 0x81 0x82 0x83 0x84 0x85 0x86 0x87 0x88 0x89 0x8A 0x8B 0x8C 0x8D 0x8E 0x8F )(list 0x200 0x204 0x208 0x20C 0x210 0x214 0x218 0x21C 0x220 0x224 0x228 0x22C 0x230 0x234 0x238 0x23C ) group.long ($2+0x1C00)++0x3 line.long 0x0 "REGG7_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x90 0x91 0x92 0x93 0x94 0x95 0x96 0x97 0x98 0x99 0x9A 0x9B 0x9C 0x9D 0x9E 0x9F )(list 0x240 0x244 0x248 0x24C 0x250 0x254 0x258 0x25C 0x260 0x264 0x268 0x26C 0x270 0x274 0x278 0x27C ) group.long ($2+0x1C00)++0x3 line.long 0x0 "REGG7_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xA0 0xA1 0xA2 0xA3 0xA4 0xA5 0xA6 0xA7 0xA8 0xA9 0xAA 0xAB 0xAC 0xAD 0xAE 0xAF )(list 0x280 0x284 0x288 0x28C 0x290 0x294 0x298 0x29C 0x2A0 0x2A4 0x2A8 0x2AC 0x2B0 0x2B4 0x2B8 0x2BC ) group.long ($2+0x1C00)++0x3 line.long 0x0 "REGG7_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xB0 0xB1 0xB2 0xB3 0xB4 0xB5 0xB6 0xB7 0xB8 0xB9 0xBA 0xBB 0xBC 0xBD 0xBE 0xBF )(list 0x2C0 0x2C4 0x2C8 0x2CC 0x2D0 0x2D4 0x2D8 0x2DC 0x2E0 0x2E4 0x2E8 0x2EC 0x2F0 0x2F4 0x2F8 0x2FC ) group.long ($2+0x1C00)++0x3 line.long 0x0 "REGG7_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xC0 0xC1 0xC2 0xC3 0xC4 0xC5 0xC6 0xC7 0xC8 0xC9 0xCA 0xCB 0xCC 0xCD 0xCE 0xCF )(list 0x300 0x304 0x308 0x30C 0x310 0x314 0x318 0x31C 0x320 0x324 0x328 0x32C 0x330 0x334 0x338 0x33C ) group.long ($2+0x1C00)++0x3 line.long 0x0 "REGG7_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xD0 0xD1 0xD2 0xD3 0xD4 0xD5 0xD6 0xD7 0xD8 0xD9 0xDA 0xDB 0xDC 0xDD 0xDE 0xDF )(list 0x340 0x344 0x348 0x34C 0x350 0x354 0x358 0x35C 0x360 0x364 0x368 0x36C 0x370 0x374 0x378 0x37C ) group.long ($2+0x1C00)++0x3 line.long 0x0 "REGG7_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xE0 0xE1 0xE2 0xE3 0xE4 0xE5 0xE6 0xE7 0xE8 0xE9 0xEA 0xEB 0xEC 0xED 0xEE 0xEF )(list 0x380 0x384 0x388 0x38C 0x390 0x394 0x398 0x39C 0x3A0 0x3A4 0x3A8 0x3AC 0x3B0 0x3B4 0x3B8 0x3BC ) group.long ($2+0x1C00)++0x3 line.long 0x0 "REGG7_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xF0 0xF1 0xF2 0xF3 0xF4 0xF5 0xF6 0xF7 0xF8 0xF9 0xFA 0xFB 0xFC 0xFD 0xFE 0xFF )(list 0x3C0 0x3C4 0x3C8 0x3CC 0x3D0 0x3D4 0x3D8 0x3DC 0x3E0 0x3E4 0x3E8 0x3EC 0x3F0 0x3F4 0x3F8 0x3FC ) group.long ($2+0x1C00)++0x3 line.long 0x0 "REGG7_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end group.long 0x2000++0x17 line.long 0x0 "GLB_CTL,This register provides global enable settings for permission control." bitfld.long 0x0 5. "DOM_CFG_LOCK,Lock write for DOM_CFG_MODE bit." "0,1" bitfld.long 0x0 4. "DOM_CFG_MODE,When enabled all the source setting can be configured by master from domain 0 if it is not locked. When disabled only resource manager can configure the permission of the resource." "0,1" bitfld.long 0x0 3. "PERCK_DIS_LOCK,Lock write for PERCK_DIS" "0,1" bitfld.long 0x0 2. "PERCK_DIS,All the permission check disable." "0,1" newline bitfld.long 0x0 1. "DOM_PRO_LOCK,Lock write for DOM_PRO_EN bit." "0,1" bitfld.long 0x0 0. "DOM_PRO_EN,When disabled no domain access permission check" "0,1" line.long 0x4 "RES_MGR,Resource manager register. This regster is used to assign resource manager for global resource access control" bitfld.long 0x4 17. "MID_LOCK,Lock write for MID_EN and MID_LOW and MID_HIG registers." "0,1" bitfld.long 0x4 16. "MID_EN,Master ID check enable" "0,1" bitfld.long 0x4 15. "PRI_PER_LOCK,Lock write for PRI_PER and PRI_PER_EN" "0,1" bitfld.long 0x4 13.--14. "PRI_PER,Resource manager privileged access permission. bit0 for privileged access bit1 for user access" "0,1,2,3" newline bitfld.long 0x4 12. "PRI_PER_EN,Resource manager privileged access permission enable." "0,1" bitfld.long 0x4 11. "SEC_PER_LOCK,Lock for SEC_PER and SEC_PER_LOCK" "0,1" bitfld.long 0x4 9.--10. "SEC_PER,Resource manager secure access permission. bit 0 for secure access bit 1 for non-secure access" "0,1,2,3" bitfld.long 0x4 8. "SEC_PER_EN,Resource manager secure permission enable" "0,1" bitfld.long 0x4 7. "DID_LOCK,Lock write for DID_EN and DID" "0,1" newline hexmask.long.byte 0x4 3.--6. 1. "DID,Resource manager domain ID" bitfld.long 0x4 2. "DID_EN,Resource manager Domain ID enable" "0,1" bitfld.long 0x4 1. "RES_MGR_EN_LOCK,Lock for RES_MGR_EN" "0,1" bitfld.long 0x4 0. "RES_MGR_EN,Resource manager enable. When the bit is disable there is no resource manager." "0,1" line.long 0x8 "RES_MGR_MA0,This register is used to assign master 0~31 as resource manager." hexmask.long 0x8 0.--31. 1. "MID,Assign master 0~31 for resource manager" line.long 0xC "RES_MGR_MA1,This register is used to assign master 32~63 as resource manager." hexmask.long 0xC 0.--31. 1. "MID,Indicate if master 32~63 is resource manager." line.long 0x10 "RES_MGR_MA2,This register is used to assign master 64~95 as resource manager." hexmask.long 0x10 0.--31. 1. "MID,Indicate if master 64~95 is resource manager." line.long 0x14 "RES_MGR_MA3,This register is used to assign master 96~127 as resource manager." hexmask.long 0x14 0.--31. 1. "MID,Indicate if master 96~127 is resource manager." repeat 8. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 )(list 0x0 0x14 0x28 0x3C 0x50 0x64 0x78 0x8C ) group.long ($2+0x2100)++0x3 line.long 0x0 "GRP_MGR_$1,Group Manager Register. This register is used to assign group manager for each domain" bitfld.long 0x0 17. "MID_LOCK,Lock write for MID_EN and MID_LOW and MID_HIG registers." "0,1" bitfld.long 0x0 16. "MID_EN,Master ID check enable" "0,1" bitfld.long 0x0 15. "PRI_PER_LOCK,Lock write for PRI_PER and PRI_PER_EN" "0,1" bitfld.long 0x0 13.--14. "PRI_PER,Group manager privileged access permission. bit0 for privileged access bit1 for user access" "0,1,2,3" newline bitfld.long 0x0 12. "PRI_PER_EN,Group manager privileged access permission enable." "0,1" bitfld.long 0x0 11. "SEC_PER_LOCK,Lock for SEC_PER and SEC_PER_LOCK" "0,1" bitfld.long 0x0 9.--10. "SEC_PER,Group manager secure access permission. bit 0 for secure access bit 1 for non-secure access" "0,1,2,3" bitfld.long 0x0 8. "SEC_PER_EN,Group manager secure permission enable" "0,1" bitfld.long 0x0 7. "DID_LOCK,Lock write for DID_EN and DID" "0,1" newline hexmask.long.byte 0x0 3.--6. 1. "DID,Group manager domain ID" bitfld.long 0x0 2. "DID_EN,Group manager Domain ID enable" "0,1" bitfld.long 0x0 1. "GRP_MGR_EN_LOCK,Lock write for GPR_MGR_EN" "0,1" bitfld.long 0x0 0. "GRP_MGR_EN,Group manager enable. When the bit is disable there is no resource manager." "0,1" repeat.end repeat 8. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 )(list 0x0 0x14 0x28 0x3C 0x50 0x64 0x78 0x8C ) group.long ($2+0x2104)++0x3 line.long 0x0 "GRP_MGR_MA0_$1,Assign master 0~31 for group manager 0" hexmask.long 0x0 0.--31. 1. "MID,Assign master 0~31 for resource manager" repeat.end repeat 8. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 )(list 0x0 0x14 0x28 0x3C 0x50 0x64 0x78 0x8C ) group.long ($2+0x2108)++0x3 line.long 0x0 "GRP_MGR_MA1_$1,Assign master 32~63 for group manager 0" hexmask.long 0x0 0.--31. 1. "MID,Indicate if master 32~63 is resource manager." repeat.end repeat 8. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 )(list 0x0 0x14 0x28 0x3C 0x50 0x64 0x78 0x8C ) group.long ($2+0x210C)++0x3 line.long 0x0 "GRP_MGR_MA2_$1,Assign master 64~95 for group manager 0" hexmask.long 0x0 0.--31. 1. "MID,Indicate if master 64~95 is resource manager." repeat.end repeat 8. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 )(list 0x0 0x14 0x28 0x3C 0x50 0x64 0x78 0x8C ) group.long ($2+0x2110)++0x3 line.long 0x0 "GRP_MGR_MA3_$1,Assign master 96~127 for group manager 0" hexmask.long 0x0 0.--31. 1. "MID,Indicate if master 96~127 is resource manager." repeat.end group.long 0x2200++0x3 line.long 0x0 "DOM_GID_0,Indicate which group domain 0 belong to" bitfld.long 0x0 3. "LOCK,Lock write for GID" "0,1" bitfld.long 0x0 0.--2. "GID,Group ID" "0,1,2,3,4,5,6,7" repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x18 0x30 0x48 0x60 0x78 0x90 0xA8 0xC0 0xD8 0xF0 0x108 0x120 0x138 0x150 0x168 ) group.long ($2+0x2204)++0x3 line.long 0x0 "DOM_OWN_$1,Assign owner for function domain 0." bitfld.long 0x0 17. "MID_LOCK,Lock write for MID_EN and MID_LOW and MID_HIG registers." "0,1" bitfld.long 0x0 16. "MID_EN,Master ID check enable" "0,1" bitfld.long 0x0 15. "PRI_PER_LOCK,Lock write for PRI_PER and PRI_PER_EN" "0,1" bitfld.long 0x0 13.--14. "PRI_PER,Group manager privileged access permission. bit0 for privileged access bit1 for user access" "0,1,2,3" newline bitfld.long 0x0 12. "PRI_PER_EN,Group manager privileged access permission enable." "0,1" bitfld.long 0x0 11. "SEC_PER_LOCK,Lock for SEC_PER and SEC_PER_LOCK" "0,1" bitfld.long 0x0 9.--10. "SEC_PER,Domain owner secure access permission. bit 0 for secure access bit 1 for non-secure access" "0,1,2,3" bitfld.long 0x0 8. "SEC_PER_EN,Domain owner secure permission enable" "0,1" newline bitfld.long 0x0 1. "DOM_OWN_EN_LOCK,Lock for DOM_OWN_EN" "0,1" bitfld.long 0x0 0. "DOM_OWN_EN,Domain owner enable. When the bit is disable there is no domain owner." "0,1" repeat.end repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x18 0x30 0x48 0x60 0x78 0x90 0xA8 0xC0 0xD8 0xF0 0x108 0x120 0x138 0x150 0x168 ) group.long ($2+0x2208)++0x3 line.long 0x0 "DOM_OWN_MA0_$1,Assign master 0~31 for domain owner 0" hexmask.long 0x0 0.--31. 1. "MID,Assign master 0~31 for resource manager" repeat.end repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x18 0x30 0x48 0x60 0x78 0x90 0xA8 0xC0 0xD8 0xF0 0x108 0x120 0x138 0x150 0x168 ) group.long ($2+0x220C)++0x3 line.long 0x0 "DOM_OWN_MA1_$1,Assign master 32~63 for domain owner 0" hexmask.long 0x0 0.--31. 1. "MID,Indicate if master 32~63 is resource manager." repeat.end repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x18 0x30 0x48 0x60 0x78 0x90 0xA8 0xC0 0xD8 0xF0 0x108 0x120 0x138 0x150 0x168 ) group.long ($2+0x2210)++0x3 line.long 0x0 "DOM_OWN_MA2_$1,Assign master 64~95 for domain owner 0" hexmask.long 0x0 0.--31. 1. "MID,Indicate if master 64~95 is resource manager." repeat.end repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x18 0x30 0x48 0x60 0x78 0x90 0xA8 0xC0 0xD8 0xF0 0x108 0x120 0x138 0x150 0x168 ) group.long ($2+0x2214)++0x3 line.long 0x0 "DOM_OWN_MA3_$1,Assign master 96~127 for domain owner 0" hexmask.long 0x0 0.--31. 1. "MID,Indicate if master 96~127 is resource manager." repeat.end group.long 0x2218++0x3 line.long 0x0 "DOM_GID_1,Indicate which group domain 1 belong to" bitfld.long 0x0 3. "LOCK,Lock write for GID" "0,1" bitfld.long 0x0 0.--2. "GID,Group ID" "0,1,2,3,4,5,6,7" group.long 0x2230++0x3 line.long 0x0 "DOM_GID_2,Indicate which group domain 2 belong to" bitfld.long 0x0 3. "LOCK,Lock write for GID" "0,1" bitfld.long 0x0 0.--2. "GID,Group ID" "0,1,2,3,4,5,6,7" group.long 0x2248++0x3 line.long 0x0 "DOM_GID_3,Indicate which group domain 3 belong to" bitfld.long 0x0 3. "LOCK,Lock write for GID" "0,1" bitfld.long 0x0 0.--2. "GID,Group ID" "0,1,2,3,4,5,6,7" group.long 0x2260++0x3 line.long 0x0 "DOM_GID_4,Indicate which group domain 4 belong to" bitfld.long 0x0 3. "LOCK,Lock write for GID" "0,1" bitfld.long 0x0 0.--2. "GID,Group ID" "0,1,2,3,4,5,6,7" group.long 0x2278++0x3 line.long 0x0 "DOM_GID_5,Indicate which group domain 5 belong to" bitfld.long 0x0 3. "LOCK,Lock write for GID" "0,1" bitfld.long 0x0 0.--2. "GID,Group ID" "0,1,2,3,4,5,6,7" group.long 0x2290++0x3 line.long 0x0 "DOM_GID_6,Indicate which group domain 6 belong to" bitfld.long 0x0 3. "LOCK,Lock write for GID" "0,1" bitfld.long 0x0 0.--2. "GID,Group ID" "0,1,2,3,4,5,6,7" group.long 0x22A8++0x3 line.long 0x0 "DOM_GID_7,Indicate which group domain 7 belong to" bitfld.long 0x0 3. "LOCK,Lock write for GID" "0,1" bitfld.long 0x0 0.--2. "GID,Group ID" "0,1,2,3,4,5,6,7" group.long 0x22C0++0x3 line.long 0x0 "DOM_GID_8,Indicate which group domain 8 belong to" bitfld.long 0x0 3. "LOCK,Lock write for GID" "0,1" bitfld.long 0x0 0.--2. "GID,Group ID" "0,1,2,3,4,5,6,7" group.long 0x22D8++0x3 line.long 0x0 "DOM_GID_9,Indicate which group domain 9 belong to" bitfld.long 0x0 3. "LOCK,Lock write for GID" "0,1" bitfld.long 0x0 0.--2. "GID,Group ID" "0,1,2,3,4,5,6,7" group.long 0x22F0++0x3 line.long 0x0 "DOM_GID_10,Indicate which group domain 10 belong to" bitfld.long 0x0 3. "LOCK,Lock write for GID" "0,1" bitfld.long 0x0 0.--2. "GID,Group ID" "0,1,2,3,4,5,6,7" group.long 0x2308++0x3 line.long 0x0 "DOM_GID_11,Indicate which group domain 11 belong to" bitfld.long 0x0 3. "LOCK,Lock write for GID" "0,1" bitfld.long 0x0 0.--2. "GID,Group ID" "0,1,2,3,4,5,6,7" group.long 0x2320++0x3 line.long 0x0 "DOM_GID_12,Indicate which group domain 12 belong to" bitfld.long 0x0 3. "LOCK,Lock write for GID" "0,1" bitfld.long 0x0 0.--2. "GID,Group ID" "0,1,2,3,4,5,6,7" group.long 0x2338++0x3 line.long 0x0 "DOM_GID_13,Indicate which group domain 13 belong to" bitfld.long 0x0 3. "LOCK,Lock write for GID" "0,1" bitfld.long 0x0 0.--2. "GID,Group ID" "0,1,2,3,4,5,6,7" group.long 0x2350++0x3 line.long 0x0 "DOM_GID_14,Indicate which group domain 14 belong to" bitfld.long 0x0 3. "LOCK,Lock write for GID" "0,1" bitfld.long 0x0 0.--2. "GID,Group ID" "0,1,2,3,4,5,6,7" group.long 0x2368++0x3 line.long 0x0 "DOM_GID_15,Indicate which group domain 15 belong to" bitfld.long 0x0 3. "LOCK,Lock write for GID" "0,1" bitfld.long 0x0 0.--2. "GID,Group ID" "0,1,2,3,4,5,6,7" repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x34 0x68 0x9C 0xD0 0x104 0x138 0x16C 0x1A0 0x1D4 0x208 0x23C 0x270 0x2A4 0x2D8 0x30C ) group.long ($2+0x2400)++0x3 line.long 0x0 "DOM_PER0_$1,Domain Permission Control. It can be only configured by resource manager and domain owner." bitfld.long 0x0 31. "DOM7_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 29.--30. "DOM7_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 28. "DOM7_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 27. "DOM6_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 25.--26. "DOM6_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" newline bitfld.long 0x0 24. "DOM6_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 23. "DOM5_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 21.--22. "DOM5_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 20. "DOM5_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 19. "DOM4_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" newline bitfld.long 0x0 17.--18. "DOM4_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM4_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 15. "DOM3_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 13.--14. "DOM3_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 12. "DOM3_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" newline bitfld.long 0x0 11. "DOM2_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 9.--10. "DOM2_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM2_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 7. "DOM1_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 5.--6. "DOM1_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" newline bitfld.long 0x0 4. "DOM1_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 3. "DOM0_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 1.--2. "DOM0_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM0_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" repeat.end repeat 16. (list 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1A 0x1B 0x1C 0x1D 0x1E 0x1F )(list 0x340 0x374 0x3A8 0x3DC 0x410 0x444 0x478 0x4AC 0x4E0 0x514 0x548 0x57C 0x5B0 0x5E4 0x618 0x64C ) group.long ($2+0x2400)++0x3 line.long 0x0 "DOM_PER0_$1,Domain Permission Control. It can be only configured by resource manager and domain owner." bitfld.long 0x0 31. "DOM7_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 29.--30. "DOM7_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 28. "DOM7_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 27. "DOM6_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 25.--26. "DOM6_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" newline bitfld.long 0x0 24. "DOM6_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 23. "DOM5_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 21.--22. "DOM5_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 20. "DOM5_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 19. "DOM4_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" newline bitfld.long 0x0 17.--18. "DOM4_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM4_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 15. "DOM3_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 13.--14. "DOM3_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 12. "DOM3_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" newline bitfld.long 0x0 11. "DOM2_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 9.--10. "DOM2_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM2_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 7. "DOM1_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 5.--6. "DOM1_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" newline bitfld.long 0x0 4. "DOM1_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 3. "DOM0_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 1.--2. "DOM0_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM0_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" repeat.end repeat 16. (list 0x20 0x21 0x22 0x23 0x24 0x25 0x26 0x27 0x28 0x29 0x2A 0x2B 0x2C 0x2D 0x2E 0x2F )(list 0x680 0x6B4 0x6E8 0x71C 0x750 0x784 0x7B8 0x7EC 0x820 0x854 0x888 0x8BC 0x8F0 0x924 0x958 0x98C ) group.long ($2+0x2400)++0x3 line.long 0x0 "DOM_PER0_$1,Domain Permission Control. It can be only configured by resource manager and domain owner." bitfld.long 0x0 31. "DOM7_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 29.--30. "DOM7_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 28. "DOM7_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 27. "DOM6_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 25.--26. "DOM6_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" newline bitfld.long 0x0 24. "DOM6_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 23. "DOM5_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 21.--22. "DOM5_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 20. "DOM5_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 19. "DOM4_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" newline bitfld.long 0x0 17.--18. "DOM4_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM4_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 15. "DOM3_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 13.--14. "DOM3_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 12. "DOM3_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" newline bitfld.long 0x0 11. "DOM2_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 9.--10. "DOM2_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM2_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 7. "DOM1_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 5.--6. "DOM1_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" newline bitfld.long 0x0 4. "DOM1_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 3. "DOM0_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 1.--2. "DOM0_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM0_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" repeat.end repeat 16. (list 0x30 0x31 0x32 0x33 0x34 0x35 0x36 0x37 0x38 0x39 0x3A 0x3B 0x3C 0x3D 0x3E 0x3F )(list 0x9C0 0x9F4 0xA28 0xA5C 0xA90 0xAC4 0xAF8 0xB2C 0xB60 0xB94 0xBC8 0xBFC 0xC30 0xC64 0xC98 0xCCC ) group.long ($2+0x2400)++0x3 line.long 0x0 "DOM_PER0_$1,Domain Permission Control. It can be only configured by resource manager and domain owner." bitfld.long 0x0 31. "DOM7_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 29.--30. "DOM7_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 28. "DOM7_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 27. "DOM6_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 25.--26. "DOM6_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" newline bitfld.long 0x0 24. "DOM6_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 23. "DOM5_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 21.--22. "DOM5_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 20. "DOM5_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 19. "DOM4_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" newline bitfld.long 0x0 17.--18. "DOM4_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM4_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 15. "DOM3_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 13.--14. "DOM3_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 12. "DOM3_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" newline bitfld.long 0x0 11. "DOM2_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 9.--10. "DOM2_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM2_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 7. "DOM1_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 5.--6. "DOM1_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" newline bitfld.long 0x0 4. "DOM1_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 3. "DOM0_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 1.--2. "DOM0_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM0_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" repeat.end repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x34 0x68 0x9C 0xD0 0x104 0x138 0x16C 0x1A0 0x1D4 0x208 0x23C 0x270 0x2A4 0x2D8 0x30C ) group.long ($2+0x2404)++0x3 line.long 0x0 "DOM_PER1_$1,Domain Permission Control. It can be only configured by resource manager and domain owner." bitfld.long 0x0 31. "DOM15_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 29.--30. "DOM15_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 28. "DOM15_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 27. "DOM14_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 25.--26. "DOM14_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" newline bitfld.long 0x0 24. "DOM14_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 23. "DOM13_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 21.--22. "DOM13_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 20. "DOM13_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 19. "DOM12_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" newline bitfld.long 0x0 17.--18. "DOM12_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM12_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 15. "DOM11_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 13.--14. "DOM11_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 12. "DOM11_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" newline bitfld.long 0x0 11. "DOM10_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 9.--10. "DOM10_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM10_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 7. "DOM9_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 5.--6. "DOM9_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" newline bitfld.long 0x0 4. "DOM9_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 3. "DOM8_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 1.--2. "DOM8_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM8_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" repeat.end repeat 16. (list 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1A 0x1B 0x1C 0x1D 0x1E 0x1F )(list 0x340 0x374 0x3A8 0x3DC 0x410 0x444 0x478 0x4AC 0x4E0 0x514 0x548 0x57C 0x5B0 0x5E4 0x618 0x64C ) group.long ($2+0x2404)++0x3 line.long 0x0 "DOM_PER1_$1,Domain Permission Control. It can be only configured by resource manager and domain owner." bitfld.long 0x0 31. "DOM15_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 29.--30. "DOM15_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 28. "DOM15_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 27. "DOM14_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 25.--26. "DOM14_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" newline bitfld.long 0x0 24. "DOM14_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 23. "DOM13_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 21.--22. "DOM13_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 20. "DOM13_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 19. "DOM12_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" newline bitfld.long 0x0 17.--18. "DOM12_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM12_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 15. "DOM11_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 13.--14. "DOM11_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 12. "DOM11_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" newline bitfld.long 0x0 11. "DOM10_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 9.--10. "DOM10_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM10_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 7. "DOM9_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 5.--6. "DOM9_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" newline bitfld.long 0x0 4. "DOM9_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 3. "DOM8_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 1.--2. "DOM8_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM8_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" repeat.end repeat 16. (list 0x20 0x21 0x22 0x23 0x24 0x25 0x26 0x27 0x28 0x29 0x2A 0x2B 0x2C 0x2D 0x2E 0x2F )(list 0x680 0x6B4 0x6E8 0x71C 0x750 0x784 0x7B8 0x7EC 0x820 0x854 0x888 0x8BC 0x8F0 0x924 0x958 0x98C ) group.long ($2+0x2404)++0x3 line.long 0x0 "DOM_PER1_$1,Domain Permission Control. It can be only configured by resource manager and domain owner." bitfld.long 0x0 31. "DOM15_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 29.--30. "DOM15_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 28. "DOM15_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 27. "DOM14_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 25.--26. "DOM14_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" newline bitfld.long 0x0 24. "DOM14_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 23. "DOM13_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 21.--22. "DOM13_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 20. "DOM13_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 19. "DOM12_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" newline bitfld.long 0x0 17.--18. "DOM12_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM12_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 15. "DOM11_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 13.--14. "DOM11_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 12. "DOM11_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" newline bitfld.long 0x0 11. "DOM10_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 9.--10. "DOM10_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM10_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 7. "DOM9_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 5.--6. "DOM9_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" newline bitfld.long 0x0 4. "DOM9_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 3. "DOM8_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 1.--2. "DOM8_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM8_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" repeat.end repeat 16. (list 0x30 0x31 0x32 0x33 0x34 0x35 0x36 0x37 0x38 0x39 0x3A 0x3B 0x3C 0x3D 0x3E 0x3F )(list 0x9C0 0x9F4 0xA28 0xA5C 0xA90 0xAC4 0xAF8 0xB2C 0xB60 0xB94 0xBC8 0xBFC 0xC30 0xC64 0xC98 0xCCC ) group.long ($2+0x2404)++0x3 line.long 0x0 "DOM_PER1_$1,Domain Permission Control. It can be only configured by resource manager and domain owner." bitfld.long 0x0 31. "DOM15_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 29.--30. "DOM15_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 28. "DOM15_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 27. "DOM14_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 25.--26. "DOM14_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" newline bitfld.long 0x0 24. "DOM14_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 23. "DOM13_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 21.--22. "DOM13_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 20. "DOM13_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 19. "DOM12_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" newline bitfld.long 0x0 17.--18. "DOM12_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM12_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 15. "DOM11_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 13.--14. "DOM11_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 12. "DOM11_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" newline bitfld.long 0x0 11. "DOM10_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 9.--10. "DOM10_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM10_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 7. "DOM9_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 5.--6. "DOM9_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" newline bitfld.long 0x0 4. "DOM9_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 3. "DOM8_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 1.--2. "DOM8_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM8_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" repeat.end repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x34 0x68 0x9C 0xD0 0x104 0x138 0x16C 0x1A0 0x1D4 0x208 0x23C 0x270 0x2A4 0x2D8 0x30C ) group.long ($2+0x2408)++0x3 line.long 0x0 "SEC_PER0_$1,This register is only used for resource manager to control secure access permission." bitfld.long 0x0 31. "DOM3_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM3_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM3_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM3_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM2_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM2_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM2_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM2_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM1_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM1_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM1_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM1_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM0_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM0_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM0_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM0_SEC_EN,Domain secure permission control enable" "0,1" repeat.end repeat 16. (list 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1A 0x1B 0x1C 0x1D 0x1E 0x1F )(list 0x340 0x374 0x3A8 0x3DC 0x410 0x444 0x478 0x4AC 0x4E0 0x514 0x548 0x57C 0x5B0 0x5E4 0x618 0x64C ) group.long ($2+0x2408)++0x3 line.long 0x0 "SEC_PER0_$1,This register is only used for resource manager to control secure access permission." bitfld.long 0x0 31. "DOM3_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM3_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM3_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM3_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM2_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM2_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM2_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM2_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM1_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM1_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM1_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM1_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM0_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM0_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM0_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM0_SEC_EN,Domain secure permission control enable" "0,1" repeat.end repeat 16. (list 0x20 0x21 0x22 0x23 0x24 0x25 0x26 0x27 0x28 0x29 0x2A 0x2B 0x2C 0x2D 0x2E 0x2F )(list 0x680 0x6B4 0x6E8 0x71C 0x750 0x784 0x7B8 0x7EC 0x820 0x854 0x888 0x8BC 0x8F0 0x924 0x958 0x98C ) group.long ($2+0x2408)++0x3 line.long 0x0 "SEC_PER0_$1,This register is only used for resource manager to control secure access permission." bitfld.long 0x0 31. "DOM3_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM3_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM3_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM3_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM2_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM2_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM2_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM2_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM1_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM1_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM1_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM1_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM0_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM0_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM0_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM0_SEC_EN,Domain secure permission control enable" "0,1" repeat.end repeat 16. (list 0x30 0x31 0x32 0x33 0x34 0x35 0x36 0x37 0x38 0x39 0x3A 0x3B 0x3C 0x3D 0x3E 0x3F )(list 0x9C0 0x9F4 0xA28 0xA5C 0xA90 0xAC4 0xAF8 0xB2C 0xB60 0xB94 0xBC8 0xBFC 0xC30 0xC64 0xC98 0xCCC ) group.long ($2+0x2408)++0x3 line.long 0x0 "SEC_PER0_$1,This register is only used for resource manager to control secure access permission." bitfld.long 0x0 31. "DOM3_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM3_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM3_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM3_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM2_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM2_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM2_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM2_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM1_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM1_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM1_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM1_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM0_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM0_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM0_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM0_SEC_EN,Domain secure permission control enable" "0,1" repeat.end repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x34 0x68 0x9C 0xD0 0x104 0x138 0x16C 0x1A0 0x1D4 0x208 0x23C 0x270 0x2A4 0x2D8 0x30C ) group.long ($2+0x240C)++0x3 line.long 0x0 "SEC_PER1_$1,This register is only used for resource manager to control secure access permission." bitfld.long 0x0 31. "DOM7_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM7_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM7_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM7_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM6_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM6_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM6_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM6_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM5_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM5_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM5_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM5_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM4_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM4_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM4_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM4_SEC_EN,Domain secure permission control enable" "0,1" repeat.end repeat 16. (list 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1A 0x1B 0x1C 0x1D 0x1E 0x1F )(list 0x340 0x374 0x3A8 0x3DC 0x410 0x444 0x478 0x4AC 0x4E0 0x514 0x548 0x57C 0x5B0 0x5E4 0x618 0x64C ) group.long ($2+0x240C)++0x3 line.long 0x0 "SEC_PER1_$1,This register is only used for resource manager to control secure access permission." bitfld.long 0x0 31. "DOM7_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM7_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM7_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM7_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM6_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM6_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM6_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM6_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM5_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM5_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM5_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM5_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM4_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM4_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM4_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM4_SEC_EN,Domain secure permission control enable" "0,1" repeat.end repeat 16. (list 0x20 0x21 0x22 0x23 0x24 0x25 0x26 0x27 0x28 0x29 0x2A 0x2B 0x2C 0x2D 0x2E 0x2F )(list 0x680 0x6B4 0x6E8 0x71C 0x750 0x784 0x7B8 0x7EC 0x820 0x854 0x888 0x8BC 0x8F0 0x924 0x958 0x98C ) group.long ($2+0x240C)++0x3 line.long 0x0 "SEC_PER1_$1,This register is only used for resource manager to control secure access permission." bitfld.long 0x0 31. "DOM7_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM7_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM7_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM7_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM6_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM6_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM6_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM6_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM5_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM5_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM5_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM5_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM4_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM4_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM4_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM4_SEC_EN,Domain secure permission control enable" "0,1" repeat.end repeat 16. (list 0x30 0x31 0x32 0x33 0x34 0x35 0x36 0x37 0x38 0x39 0x3A 0x3B 0x3C 0x3D 0x3E 0x3F )(list 0x9C0 0x9F4 0xA28 0xA5C 0xA90 0xAC4 0xAF8 0xB2C 0xB60 0xB94 0xBC8 0xBFC 0xC30 0xC64 0xC98 0xCCC ) group.long ($2+0x240C)++0x3 line.long 0x0 "SEC_PER1_$1,This register is only used for resource manager to control secure access permission." bitfld.long 0x0 31. "DOM7_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM7_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM7_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM7_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM6_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM6_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM6_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM6_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM5_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM5_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM5_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM5_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM4_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM4_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM4_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM4_SEC_EN,Domain secure permission control enable" "0,1" repeat.end repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x34 0x68 0x9C 0xD0 0x104 0x138 0x16C 0x1A0 0x1D4 0x208 0x23C 0x270 0x2A4 0x2D8 0x30C ) group.long ($2+0x2410)++0x3 line.long 0x0 "SEC_PER2_$1,This register is only used for resource manager to control secure access permission." bitfld.long 0x0 31. "DOM11_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM11_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM11_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM11_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM10_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM10_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM10_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM10_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM9_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM9_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM9_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM9_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM8_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM8_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM8_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM8_SEC_EN,Domain secure permission control enable" "0,1" repeat.end repeat 16. (list 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1A 0x1B 0x1C 0x1D 0x1E 0x1F )(list 0x340 0x374 0x3A8 0x3DC 0x410 0x444 0x478 0x4AC 0x4E0 0x514 0x548 0x57C 0x5B0 0x5E4 0x618 0x64C ) group.long ($2+0x2410)++0x3 line.long 0x0 "SEC_PER2_$1,This register is only used for resource manager to control secure access permission." bitfld.long 0x0 31. "DOM11_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM11_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM11_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM11_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM10_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM10_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM10_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM10_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM9_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM9_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM9_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM9_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM8_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM8_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM8_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM8_SEC_EN,Domain secure permission control enable" "0,1" repeat.end repeat 16. (list 0x20 0x21 0x22 0x23 0x24 0x25 0x26 0x27 0x28 0x29 0x2A 0x2B 0x2C 0x2D 0x2E 0x2F )(list 0x680 0x6B4 0x6E8 0x71C 0x750 0x784 0x7B8 0x7EC 0x820 0x854 0x888 0x8BC 0x8F0 0x924 0x958 0x98C ) group.long ($2+0x2410)++0x3 line.long 0x0 "SEC_PER2_$1,This register is only used for resource manager to control secure access permission." bitfld.long 0x0 31. "DOM11_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM11_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM11_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM11_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM10_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM10_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM10_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM10_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM9_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM9_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM9_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM9_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM8_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM8_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM8_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM8_SEC_EN,Domain secure permission control enable" "0,1" repeat.end repeat 16. (list 0x30 0x31 0x32 0x33 0x34 0x35 0x36 0x37 0x38 0x39 0x3A 0x3B 0x3C 0x3D 0x3E 0x3F )(list 0x9C0 0x9F4 0xA28 0xA5C 0xA90 0xAC4 0xAF8 0xB2C 0xB60 0xB94 0xBC8 0xBFC 0xC30 0xC64 0xC98 0xCCC ) group.long ($2+0x2410)++0x3 line.long 0x0 "SEC_PER2_$1,This register is only used for resource manager to control secure access permission." bitfld.long 0x0 31. "DOM11_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM11_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM11_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM11_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM10_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM10_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM10_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM10_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM9_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM9_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM9_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM9_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM8_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM8_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM8_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM8_SEC_EN,Domain secure permission control enable" "0,1" repeat.end repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x34 0x68 0x9C 0xD0 0x104 0x138 0x16C 0x1A0 0x1D4 0x208 0x23C 0x270 0x2A4 0x2D8 0x30C ) group.long ($2+0x2414)++0x3 line.long 0x0 "SEC_PER3_$1,This register is only used for resource manager to control secure access permission." bitfld.long 0x0 31. "DOM15_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM15_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM15_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM15_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM14_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM14_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM14_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM14_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM13_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM13_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM13_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM13_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM12_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM12_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM12_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM12_SEC_EN,Domain secure permission control enable" "0,1" repeat.end repeat 16. (list 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1A 0x1B 0x1C 0x1D 0x1E 0x1F )(list 0x340 0x374 0x3A8 0x3DC 0x410 0x444 0x478 0x4AC 0x4E0 0x514 0x548 0x57C 0x5B0 0x5E4 0x618 0x64C ) group.long ($2+0x2414)++0x3 line.long 0x0 "SEC_PER3_$1,This register is only used for resource manager to control secure access permission." bitfld.long 0x0 31. "DOM15_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM15_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM15_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM15_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM14_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM14_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM14_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM14_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM13_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM13_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM13_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM13_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM12_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM12_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM12_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM12_SEC_EN,Domain secure permission control enable" "0,1" repeat.end repeat 16. (list 0x20 0x21 0x22 0x23 0x24 0x25 0x26 0x27 0x28 0x29 0x2A 0x2B 0x2C 0x2D 0x2E 0x2F )(list 0x680 0x6B4 0x6E8 0x71C 0x750 0x784 0x7B8 0x7EC 0x820 0x854 0x888 0x8BC 0x8F0 0x924 0x958 0x98C ) group.long ($2+0x2414)++0x3 line.long 0x0 "SEC_PER3_$1,This register is only used for resource manager to control secure access permission." bitfld.long 0x0 31. "DOM15_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM15_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM15_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM15_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM14_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM14_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM14_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM14_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM13_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM13_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM13_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM13_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM12_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM12_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM12_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM12_SEC_EN,Domain secure permission control enable" "0,1" repeat.end repeat 16. (list 0x30 0x31 0x32 0x33 0x34 0x35 0x36 0x37 0x38 0x39 0x3A 0x3B 0x3C 0x3D 0x3E 0x3F )(list 0x9C0 0x9F4 0xA28 0xA5C 0xA90 0xAC4 0xAF8 0xB2C 0xB60 0xB94 0xBC8 0xBFC 0xC30 0xC64 0xC98 0xCCC ) group.long ($2+0x2414)++0x3 line.long 0x0 "SEC_PER3_$1,This register is only used for resource manager to control secure access permission." bitfld.long 0x0 31. "DOM15_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM15_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM15_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM15_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM14_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM14_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM14_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM14_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM13_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM13_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM13_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM13_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM12_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM12_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM12_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM12_SEC_EN,Domain secure permission control enable" "0,1" repeat.end repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x34 0x68 0x9C 0xD0 0x104 0x138 0x16C 0x1A0 0x1D4 0x208 0x23C 0x270 0x2A4 0x2D8 0x30C ) group.long ($2+0x2418)++0x3 line.long 0x0 "PRI_PER0_$1,This register is only used for resource manager to control privileged access permission." bitfld.long 0x0 31. "DOM3_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM3_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM3_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM3_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM2_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM2_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM2_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM2_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM1_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM1_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM1_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM1_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM0_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM0_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM0_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM0_PRI_EN,Domain privileged permission control enable" "0,1" repeat.end repeat 16. (list 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1A 0x1B 0x1C 0x1D 0x1E 0x1F )(list 0x340 0x374 0x3A8 0x3DC 0x410 0x444 0x478 0x4AC 0x4E0 0x514 0x548 0x57C 0x5B0 0x5E4 0x618 0x64C ) group.long ($2+0x2418)++0x3 line.long 0x0 "PRI_PER0_$1,This register is only used for resource manager to control privileged access permission." bitfld.long 0x0 31. "DOM3_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM3_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM3_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM3_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM2_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM2_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM2_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM2_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM1_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM1_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM1_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM1_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM0_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM0_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM0_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM0_PRI_EN,Domain privileged permission control enable" "0,1" repeat.end repeat 16. (list 0x20 0x21 0x22 0x23 0x24 0x25 0x26 0x27 0x28 0x29 0x2A 0x2B 0x2C 0x2D 0x2E 0x2F )(list 0x680 0x6B4 0x6E8 0x71C 0x750 0x784 0x7B8 0x7EC 0x820 0x854 0x888 0x8BC 0x8F0 0x924 0x958 0x98C ) group.long ($2+0x2418)++0x3 line.long 0x0 "PRI_PER0_$1,This register is only used for resource manager to control privileged access permission." bitfld.long 0x0 31. "DOM3_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM3_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM3_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM3_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM2_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM2_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM2_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM2_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM1_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM1_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM1_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM1_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM0_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM0_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM0_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM0_PRI_EN,Domain privileged permission control enable" "0,1" repeat.end repeat 16. (list 0x30 0x31 0x32 0x33 0x34 0x35 0x36 0x37 0x38 0x39 0x3A 0x3B 0x3C 0x3D 0x3E 0x3F )(list 0x9C0 0x9F4 0xA28 0xA5C 0xA90 0xAC4 0xAF8 0xB2C 0xB60 0xB94 0xBC8 0xBFC 0xC30 0xC64 0xC98 0xCCC ) group.long ($2+0x2418)++0x3 line.long 0x0 "PRI_PER0_$1,This register is only used for resource manager to control privileged access permission." bitfld.long 0x0 31. "DOM3_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM3_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM3_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM3_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM2_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM2_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM2_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM2_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM1_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM1_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM1_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM1_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM0_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM0_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM0_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM0_PRI_EN,Domain privileged permission control enable" "0,1" repeat.end repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x34 0x68 0x9C 0xD0 0x104 0x138 0x16C 0x1A0 0x1D4 0x208 0x23C 0x270 0x2A4 0x2D8 0x30C ) group.long ($2+0x241C)++0x3 line.long 0x0 "PRI_PER1_$1,This register is only used for resource manager to control privileged access permission." bitfld.long 0x0 31. "DOM7_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM7_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM7_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM7_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM6_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM6_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM6_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM6_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM5_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM5_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM5_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM5_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM4_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM4_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM4_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM4_PRI_EN,Domain privileged permission control enable" "0,1" repeat.end repeat 16. (list 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1A 0x1B 0x1C 0x1D 0x1E 0x1F )(list 0x340 0x374 0x3A8 0x3DC 0x410 0x444 0x478 0x4AC 0x4E0 0x514 0x548 0x57C 0x5B0 0x5E4 0x618 0x64C ) group.long ($2+0x241C)++0x3 line.long 0x0 "PRI_PER1_$1,This register is only used for resource manager to control privileged access permission." bitfld.long 0x0 31. "DOM7_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM7_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM7_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM7_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM6_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM6_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM6_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM6_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM5_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM5_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM5_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM5_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM4_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM4_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM4_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM4_PRI_EN,Domain privileged permission control enable" "0,1" repeat.end repeat 16. (list 0x20 0x21 0x22 0x23 0x24 0x25 0x26 0x27 0x28 0x29 0x2A 0x2B 0x2C 0x2D 0x2E 0x2F )(list 0x680 0x6B4 0x6E8 0x71C 0x750 0x784 0x7B8 0x7EC 0x820 0x854 0x888 0x8BC 0x8F0 0x924 0x958 0x98C ) group.long ($2+0x241C)++0x3 line.long 0x0 "PRI_PER1_$1,This register is only used for resource manager to control privileged access permission." bitfld.long 0x0 31. "DOM7_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM7_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM7_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM7_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM6_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM6_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM6_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM6_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM5_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM5_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM5_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM5_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM4_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM4_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM4_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM4_PRI_EN,Domain privileged permission control enable" "0,1" repeat.end repeat 16. (list 0x30 0x31 0x32 0x33 0x34 0x35 0x36 0x37 0x38 0x39 0x3A 0x3B 0x3C 0x3D 0x3E 0x3F )(list 0x9C0 0x9F4 0xA28 0xA5C 0xA90 0xAC4 0xAF8 0xB2C 0xB60 0xB94 0xBC8 0xBFC 0xC30 0xC64 0xC98 0xCCC ) group.long ($2+0x241C)++0x3 line.long 0x0 "PRI_PER1_$1,This register is only used for resource manager to control privileged access permission." bitfld.long 0x0 31. "DOM7_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM7_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM7_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM7_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM6_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM6_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM6_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM6_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM5_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM5_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM5_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM5_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM4_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM4_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM4_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM4_PRI_EN,Domain privileged permission control enable" "0,1" repeat.end repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x34 0x68 0x9C 0xD0 0x104 0x138 0x16C 0x1A0 0x1D4 0x208 0x23C 0x270 0x2A4 0x2D8 0x30C ) group.long ($2+0x2420)++0x3 line.long 0x0 "PRI_PER2_$1,This register is only used for resource manager to control privileged access permission." bitfld.long 0x0 31. "DOM11_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM11_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM11_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM11_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM10_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM10_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM10_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM10_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM9_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM9_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM9_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM9_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM8_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM8_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM8_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM8_PRI_EN,Domain privileged permission control enable" "0,1" repeat.end repeat 16. (list 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1A 0x1B 0x1C 0x1D 0x1E 0x1F )(list 0x340 0x374 0x3A8 0x3DC 0x410 0x444 0x478 0x4AC 0x4E0 0x514 0x548 0x57C 0x5B0 0x5E4 0x618 0x64C ) group.long ($2+0x2420)++0x3 line.long 0x0 "PRI_PER2_$1,This register is only used for resource manager to control privileged access permission." bitfld.long 0x0 31. "DOM11_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM11_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM11_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM11_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM10_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM10_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM10_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM10_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM9_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM9_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM9_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM9_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM8_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM8_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM8_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM8_PRI_EN,Domain privileged permission control enable" "0,1" repeat.end repeat 16. (list 0x20 0x21 0x22 0x23 0x24 0x25 0x26 0x27 0x28 0x29 0x2A 0x2B 0x2C 0x2D 0x2E 0x2F )(list 0x680 0x6B4 0x6E8 0x71C 0x750 0x784 0x7B8 0x7EC 0x820 0x854 0x888 0x8BC 0x8F0 0x924 0x958 0x98C ) group.long ($2+0x2420)++0x3 line.long 0x0 "PRI_PER2_$1,This register is only used for resource manager to control privileged access permission." bitfld.long 0x0 31. "DOM11_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM11_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM11_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM11_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM10_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM10_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM10_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM10_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM9_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM9_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM9_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM9_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM8_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM8_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM8_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM8_PRI_EN,Domain privileged permission control enable" "0,1" repeat.end repeat 16. (list 0x30 0x31 0x32 0x33 0x34 0x35 0x36 0x37 0x38 0x39 0x3A 0x3B 0x3C 0x3D 0x3E 0x3F )(list 0x9C0 0x9F4 0xA28 0xA5C 0xA90 0xAC4 0xAF8 0xB2C 0xB60 0xB94 0xBC8 0xBFC 0xC30 0xC64 0xC98 0xCCC ) group.long ($2+0x2420)++0x3 line.long 0x0 "PRI_PER2_$1,This register is only used for resource manager to control privileged access permission." bitfld.long 0x0 31. "DOM11_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM11_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM11_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM11_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM10_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM10_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM10_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM10_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM9_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM9_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM9_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM9_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM8_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM8_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM8_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM8_PRI_EN,Domain privileged permission control enable" "0,1" repeat.end repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x34 0x68 0x9C 0xD0 0x104 0x138 0x16C 0x1A0 0x1D4 0x208 0x23C 0x270 0x2A4 0x2D8 0x30C ) group.long ($2+0x2424)++0x3 line.long 0x0 "PRI_PER3_$1,This register is only used for resource manager to control privileged access permission." bitfld.long 0x0 31. "DOM15_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM15_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM15_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM15_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM14_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM14_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM14_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM14_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM13_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM13_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM13_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM13_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM12_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM12_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM12_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM12_PRI_EN,Domain privileged permission control enable" "0,1" repeat.end repeat 16. (list 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1A 0x1B 0x1C 0x1D 0x1E 0x1F )(list 0x340 0x374 0x3A8 0x3DC 0x410 0x444 0x478 0x4AC 0x4E0 0x514 0x548 0x57C 0x5B0 0x5E4 0x618 0x64C ) group.long ($2+0x2424)++0x3 line.long 0x0 "PRI_PER3_$1,This register is only used for resource manager to control privileged access permission." bitfld.long 0x0 31. "DOM15_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM15_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM15_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM15_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM14_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM14_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM14_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM14_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM13_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM13_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM13_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM13_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM12_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM12_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM12_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM12_PRI_EN,Domain privileged permission control enable" "0,1" repeat.end repeat 16. (list 0x20 0x21 0x22 0x23 0x24 0x25 0x26 0x27 0x28 0x29 0x2A 0x2B 0x2C 0x2D 0x2E 0x2F )(list 0x680 0x6B4 0x6E8 0x71C 0x750 0x784 0x7B8 0x7EC 0x820 0x854 0x888 0x8BC 0x8F0 0x924 0x958 0x98C ) group.long ($2+0x2424)++0x3 line.long 0x0 "PRI_PER3_$1,This register is only used for resource manager to control privileged access permission." bitfld.long 0x0 31. "DOM15_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM15_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM15_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM15_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM14_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM14_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM14_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM14_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM13_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM13_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM13_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM13_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM12_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM12_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM12_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM12_PRI_EN,Domain privileged permission control enable" "0,1" repeat.end repeat 16. (list 0x30 0x31 0x32 0x33 0x34 0x35 0x36 0x37 0x38 0x39 0x3A 0x3B 0x3C 0x3D 0x3E 0x3F )(list 0x9C0 0x9F4 0xA28 0xA5C 0xA90 0xAC4 0xAF8 0xB2C 0xB60 0xB94 0xBC8 0xBFC 0xC30 0xC64 0xC98 0xCCC ) group.long ($2+0x2424)++0x3 line.long 0x0 "PRI_PER3_$1,This register is only used for resource manager to control privileged access permission." bitfld.long 0x0 31. "DOM15_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM15_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM15_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM15_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM14_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM14_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM14_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM14_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM13_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM13_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM13_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM13_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM12_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM12_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM12_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM12_PRI_EN,Domain privileged permission control enable" "0,1" repeat.end repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x34 0x68 0x9C 0xD0 0x104 0x138 0x16C 0x1A0 0x1D4 0x208 0x23C 0x270 0x2A4 0x2D8 0x30C ) group.long ($2+0x2428)++0x3 line.long 0x0 "DOM_SEC_PER_$1,This register is only used for domain master to control secure access permission. When the domain master write this register. it only changes the secure permission for itself. When the domain master read this register. it gets permission.." bitfld.long 0x0 7. "DOM_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" newline bitfld.long 0x0 0. "DOM_SEC_EN,Domain secure permission control enable" "0,1" repeat.end repeat 16. (list 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1A 0x1B 0x1C 0x1D 0x1E 0x1F )(list 0x340 0x374 0x3A8 0x3DC 0x410 0x444 0x478 0x4AC 0x4E0 0x514 0x548 0x57C 0x5B0 0x5E4 0x618 0x64C ) group.long ($2+0x2428)++0x3 line.long 0x0 "DOM_SEC_PER_$1,This register is only used for domain master to control secure access permission. When the domain master write this register. it only changes the secure permission for itself. When the domain master read this register. it gets permission.." bitfld.long 0x0 7. "DOM_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" newline bitfld.long 0x0 0. "DOM_SEC_EN,Domain secure permission control enable" "0,1" repeat.end repeat 16. (list 0x20 0x21 0x22 0x23 0x24 0x25 0x26 0x27 0x28 0x29 0x2A 0x2B 0x2C 0x2D 0x2E 0x2F )(list 0x680 0x6B4 0x6E8 0x71C 0x750 0x784 0x7B8 0x7EC 0x820 0x854 0x888 0x8BC 0x8F0 0x924 0x958 0x98C ) group.long ($2+0x2428)++0x3 line.long 0x0 "DOM_SEC_PER_$1,This register is only used for domain master to control secure access permission. When the domain master write this register. it only changes the secure permission for itself. When the domain master read this register. it gets permission.." bitfld.long 0x0 7. "DOM_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" newline bitfld.long 0x0 0. "DOM_SEC_EN,Domain secure permission control enable" "0,1" repeat.end repeat 16. (list 0x30 0x31 0x32 0x33 0x34 0x35 0x36 0x37 0x38 0x39 0x3A 0x3B 0x3C 0x3D 0x3E 0x3F )(list 0x9C0 0x9F4 0xA28 0xA5C 0xA90 0xAC4 0xAF8 0xB2C 0xB60 0xB94 0xBC8 0xBFC 0xC30 0xC64 0xC98 0xCCC ) group.long ($2+0x2428)++0x3 line.long 0x0 "DOM_SEC_PER_$1,This register is only used for domain master to control secure access permission. When the domain master write this register. it only changes the secure permission for itself. When the domain master read this register. it gets permission.." bitfld.long 0x0 7. "DOM_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" newline bitfld.long 0x0 0. "DOM_SEC_EN,Domain secure permission control enable" "0,1" repeat.end repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x34 0x68 0x9C 0xD0 0x104 0x138 0x16C 0x1A0 0x1D4 0x208 0x23C 0x270 0x2A4 0x2D8 0x30C ) group.long ($2+0x242C)++0x3 line.long 0x0 "DOM_PRI_PER_$1,This register is only used for domain master to control secure access permission. When the domain master write this register. it only changes the secure permission for itself. When the domain master read this register. it gets permission.." bitfld.long 0x0 7. "DOM_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" newline bitfld.long 0x0 0. "DOM_PRI_EN,Domain privileged permission control enable" "0,1" repeat.end repeat 16. (list 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1A 0x1B 0x1C 0x1D 0x1E 0x1F )(list 0x340 0x374 0x3A8 0x3DC 0x410 0x444 0x478 0x4AC 0x4E0 0x514 0x548 0x57C 0x5B0 0x5E4 0x618 0x64C ) group.long ($2+0x242C)++0x3 line.long 0x0 "DOM_PRI_PER_$1,This register is only used for domain master to control secure access permission. When the domain master write this register. it only changes the secure permission for itself. When the domain master read this register. it gets permission.." bitfld.long 0x0 7. "DOM_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" newline bitfld.long 0x0 0. "DOM_PRI_EN,Domain privileged permission control enable" "0,1" repeat.end repeat 16. (list 0x20 0x21 0x22 0x23 0x24 0x25 0x26 0x27 0x28 0x29 0x2A 0x2B 0x2C 0x2D 0x2E 0x2F )(list 0x680 0x6B4 0x6E8 0x71C 0x750 0x784 0x7B8 0x7EC 0x820 0x854 0x888 0x8BC 0x8F0 0x924 0x958 0x98C ) group.long ($2+0x242C)++0x3 line.long 0x0 "DOM_PRI_PER_$1,This register is only used for domain master to control secure access permission. When the domain master write this register. it only changes the secure permission for itself. When the domain master read this register. it gets permission.." bitfld.long 0x0 7. "DOM_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" newline bitfld.long 0x0 0. "DOM_PRI_EN,Domain privileged permission control enable" "0,1" repeat.end repeat 16. (list 0x30 0x31 0x32 0x33 0x34 0x35 0x36 0x37 0x38 0x39 0x3A 0x3B 0x3C 0x3D 0x3E 0x3F )(list 0x9C0 0x9F4 0xA28 0xA5C 0xA90 0xAC4 0xAF8 0xB2C 0xB60 0xB94 0xBC8 0xBFC 0xC30 0xC64 0xC98 0xCCC ) group.long ($2+0x242C)++0x3 line.long 0x0 "DOM_PRI_PER_$1,This register is only used for domain master to control secure access permission. When the domain master write this register. it only changes the secure permission for itself. When the domain master read this register. it gets permission.." bitfld.long 0x0 7. "DOM_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" newline bitfld.long 0x0 0. "DOM_PRI_EN,Domain privileged permission control enable" "0,1" repeat.end repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x34 0x68 0x9C 0xD0 0x104 0x138 0x16C 0x1A0 0x1D4 0x208 0x23C 0x270 0x2A4 0x2D8 0x30C ) group.long ($2+0x2430)++0x3 line.long 0x0 "DOM_ASSIGN_$1,Use to assign domain for accessing DOM_SEC_PER and DOM_PRI_PER register. Only resource manager. group manager and domain owner can access this register. For write. group manager must write its owen domain ID. otherwise write accessing will.." hexmask.long.byte 0x0 0.--3. 1. "DID,accessing DOM_SEC_PER and DOM_PRI_PER register" repeat.end repeat 16. (list 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1A 0x1B 0x1C 0x1D 0x1E 0x1F )(list 0x340 0x374 0x3A8 0x3DC 0x410 0x444 0x478 0x4AC 0x4E0 0x514 0x548 0x57C 0x5B0 0x5E4 0x618 0x64C ) group.long ($2+0x2430)++0x3 line.long 0x0 "DOM_ASSIGN_$1,Use to assign domain for accessing DOM_SEC_PER and DOM_PRI_PER register. Only resource manager. group manager and domain owner can access this register. For write. group manager must write its owen domain ID. otherwise write accessing will.." hexmask.long.byte 0x0 0.--3. 1. "DID,accessing DOM_SEC_PER and DOM_PRI_PER register" repeat.end repeat 16. (list 0x20 0x21 0x22 0x23 0x24 0x25 0x26 0x27 0x28 0x29 0x2A 0x2B 0x2C 0x2D 0x2E 0x2F )(list 0x680 0x6B4 0x6E8 0x71C 0x750 0x784 0x7B8 0x7EC 0x820 0x854 0x888 0x8BC 0x8F0 0x924 0x958 0x98C ) group.long ($2+0x2430)++0x3 line.long 0x0 "DOM_ASSIGN_$1,Use to assign domain for accessing DOM_SEC_PER and DOM_PRI_PER register. Only resource manager. group manager and domain owner can access this register. For write. group manager must write its owen domain ID. otherwise write accessing will.." hexmask.long.byte 0x0 0.--3. 1. "DID,accessing DOM_SEC_PER and DOM_PRI_PER register" repeat.end repeat 16. (list 0x30 0x31 0x32 0x33 0x34 0x35 0x36 0x37 0x38 0x39 0x3A 0x3B 0x3C 0x3D 0x3E 0x3F )(list 0x9C0 0x9F4 0xA28 0xA5C 0xA90 0xAC4 0xAF8 0xB2C 0xB60 0xB94 0xBC8 0xBFC 0xC30 0xC64 0xC98 0xCCC ) group.long ($2+0x2430)++0x3 line.long 0x0 "DOM_ASSIGN_$1,Use to assign domain for accessing DOM_SEC_PER and DOM_PRI_PER register. Only resource manager. group manager and domain owner can access this register. For write. group manager must write its owen domain ID. otherwise write accessing will.." hexmask.long.byte 0x0 0.--3. 1. "DID,accessing DOM_SEC_PER and DOM_PRI_PER register" repeat.end repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x38 0x70 0xA8 0xE0 0x118 0x150 0x188 0x1C0 0x1F8 0x230 0x268 0x2A0 0x2D8 0x310 0x348 ) group.long ($2+0x3100)++0x3 line.long 0x0 "RGN_DOM_$1,Assign domain for peripheral. It can be only configured by resource and group manager" bitfld.long 0x0 31. "LOCK,When this bit is set lock write for all the bits in the register." "0,1" bitfld.long 0x0 4. "SET,Set together with DID would change permission of this resource to following setting: 1) Domain access control enabled. 2) Read/Write allowed for the domain owner. 3) Read/Write not allowed for all the other domains. If this bit is not set only DID.." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Assign domain for peripheral" repeat.end repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x38 0x70 0xA8 0xE0 0x118 0x150 0x188 0x1C0 0x1F8 0x230 0x268 0x2A0 0x2D8 0x310 0x348 ) group.long ($2+0x3104)++0x3 line.long 0x0 "RGN_DOM_PER0_$1,Domain Permission Control. It can be only configured by resource manager and domain owner." bitfld.long 0x0 31. "DOM7_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 29.--30. "DOM7_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 28. "DOM7_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 27. "DOM6_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 25.--26. "DOM6_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" newline bitfld.long 0x0 24. "DOM6_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 23. "DOM5_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 21.--22. "DOM5_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 20. "DOM5_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 19. "DOM4_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" newline bitfld.long 0x0 17.--18. "DOM4_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM4_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 15. "DOM3_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 13.--14. "DOM3_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 12. "DOM3_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" newline bitfld.long 0x0 11. "DOM2_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 9.--10. "DOM2_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM2_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 7. "DOM1_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 5.--6. "DOM1_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" newline bitfld.long 0x0 4. "DOM1_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 3. "DOM0_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 1.--2. "DOM0_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM0_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" repeat.end repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x38 0x70 0xA8 0xE0 0x118 0x150 0x188 0x1C0 0x1F8 0x230 0x268 0x2A0 0x2D8 0x310 0x348 ) group.long ($2+0x3108)++0x3 line.long 0x0 "RGN_DOM_PER1_$1,Domain Permission Control. It can be only configured by resource manager and domain owner." bitfld.long 0x0 31. "DOM15_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 29.--30. "DOM15_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 28. "DOM15_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 27. "DOM14_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 25.--26. "DOM14_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" newline bitfld.long 0x0 24. "DOM14_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 23. "DOM13_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 21.--22. "DOM13_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 20. "DOM13_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 19. "DOM12_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" newline bitfld.long 0x0 17.--18. "DOM12_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM12_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 15. "DOM11_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 13.--14. "DOM11_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 12. "DOM11_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" newline bitfld.long 0x0 11. "DOM10_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 9.--10. "DOM10_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM10_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 7. "DOM9_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 5.--6. "DOM9_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" newline bitfld.long 0x0 4. "DOM9_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 3. "DOM8_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 1.--2. "DOM8_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM8_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" repeat.end repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x38 0x70 0xA8 0xE0 0x118 0x150 0x188 0x1C0 0x1F8 0x230 0x268 0x2A0 0x2D8 0x310 0x348 ) group.long ($2+0x310C)++0x3 line.long 0x0 "RGN_SEC_PER0_$1,This register is only used for resource manager to control secure access permission." bitfld.long 0x0 31. "DOM3_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM3_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM3_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM3_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM2_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM2_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM2_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM2_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM1_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM1_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM1_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM1_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM0_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM0_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM0_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM0_SEC_EN,Domain secure permission control enable" "0,1" repeat.end repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x38 0x70 0xA8 0xE0 0x118 0x150 0x188 0x1C0 0x1F8 0x230 0x268 0x2A0 0x2D8 0x310 0x348 ) group.long ($2+0x3110)++0x3 line.long 0x0 "RGN_SEC_PER1_$1,This register is only used for resource manager to control secure access permission." bitfld.long 0x0 31. "DOM7_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM7_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM7_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM7_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM6_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM6_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM6_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM6_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM5_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM5_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM5_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM5_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM4_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM4_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM4_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM4_SEC_EN,Domain secure permission control enable" "0,1" repeat.end repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x38 0x70 0xA8 0xE0 0x118 0x150 0x188 0x1C0 0x1F8 0x230 0x268 0x2A0 0x2D8 0x310 0x348 ) group.long ($2+0x3114)++0x3 line.long 0x0 "RGN_SEC_PER2_$1,This register is only used for resource manager to control secure access permission." bitfld.long 0x0 31. "DOM11_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM11_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM11_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM11_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM10_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM10_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM10_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM10_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM9_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM9_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM9_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM9_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM8_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM8_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM8_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM8_SEC_EN,Domain secure permission control enable" "0,1" repeat.end repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x38 0x70 0xA8 0xE0 0x118 0x150 0x188 0x1C0 0x1F8 0x230 0x268 0x2A0 0x2D8 0x310 0x348 ) group.long ($2+0x3118)++0x3 line.long 0x0 "RGN_SEC_PER3_$1,This register is only used for resource manager to control secure access permission." bitfld.long 0x0 31. "DOM15_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM15_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM15_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM15_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM14_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM14_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM14_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM14_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM13_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM13_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM13_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM13_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM12_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM12_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM12_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM12_SEC_EN,Domain secure permission control enable" "0,1" repeat.end repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x38 0x70 0xA8 0xE0 0x118 0x150 0x188 0x1C0 0x1F8 0x230 0x268 0x2A0 0x2D8 0x310 0x348 ) group.long ($2+0x311C)++0x3 line.long 0x0 "RGN_PRI_PER0_$1,This register is only used for resource manager to control privileged access permission." bitfld.long 0x0 31. "DOM3_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM3_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM3_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM3_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM2_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM2_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM2_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM2_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM1_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM1_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM1_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM1_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM0_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM0_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM0_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM0_PRI_EN,Domain privileged permission control enable" "0,1" repeat.end repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x38 0x70 0xA8 0xE0 0x118 0x150 0x188 0x1C0 0x1F8 0x230 0x268 0x2A0 0x2D8 0x310 0x348 ) group.long ($2+0x3120)++0x3 line.long 0x0 "RGN_PRI_PER1_$1,This register is only used for resource manager to control privileged access permission." bitfld.long 0x0 31. "DOM7_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM7_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM7_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM7_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM6_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM6_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM6_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM6_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM5_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM5_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM5_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM5_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM4_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM4_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM4_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM4_PRI_EN,Domain privileged permission control enable" "0,1" repeat.end repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x38 0x70 0xA8 0xE0 0x118 0x150 0x188 0x1C0 0x1F8 0x230 0x268 0x2A0 0x2D8 0x310 0x348 ) group.long ($2+0x3124)++0x3 line.long 0x0 "RGN_PRI_PER2_$1,This register is only used for resource manager to control privileged access permission." bitfld.long 0x0 31. "DOM11_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM11_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM11_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM11_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM10_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM10_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM10_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM10_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM9_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM9_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM9_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM9_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM8_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM8_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM8_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM8_PRI_EN,Domain privileged permission control enable" "0,1" repeat.end repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x38 0x70 0xA8 0xE0 0x118 0x150 0x188 0x1C0 0x1F8 0x230 0x268 0x2A0 0x2D8 0x310 0x348 ) group.long ($2+0x3128)++0x3 line.long 0x0 "RGN_PRI_PER3_$1,This register is only used for resource manager to control privileged access permission." bitfld.long 0x0 31. "DOM15_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM15_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM15_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM15_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM14_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM14_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM14_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM14_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM13_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM13_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM13_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM13_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM12_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM12_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM12_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM12_PRI_EN,Domain privileged permission control enable" "0,1" repeat.end repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x38 0x70 0xA8 0xE0 0x118 0x150 0x188 0x1C0 0x1F8 0x230 0x268 0x2A0 0x2D8 0x310 0x348 ) group.long ($2+0x312C)++0x3 line.long 0x0 "RGN_DOM_SEC_PER_$1,This register is only used for domain master to control secure access permission. When the domain master write this register. it only changes the secure permission for itself. When the domain master read this register. it gets.." bitfld.long 0x0 7. "DOM_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" newline bitfld.long 0x0 0. "DOM_SEC_EN,Domain secure permission control enable" "0,1" repeat.end repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x38 0x70 0xA8 0xE0 0x118 0x150 0x188 0x1C0 0x1F8 0x230 0x268 0x2A0 0x2D8 0x310 0x348 ) group.long ($2+0x3130)++0x3 line.long 0x0 "RGN_DOM_PRI_PER_$1,This register is only used for domain master to control secure access permission. When the domain master write this register. it only changes the secure permission for itself. When the domain master read this register. it gets.." bitfld.long 0x0 7. "DOM_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" newline bitfld.long 0x0 0. "DOM_PRI_EN,Domain privileged permission control enable" "0,1" repeat.end repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x38 0x70 0xA8 0xE0 0x118 0x150 0x188 0x1C0 0x1F8 0x230 0x268 0x2A0 0x2D8 0x310 0x348 ) group.long ($2+0x3134)++0x3 line.long 0x0 "RGN_DOM_ASSIGN_$1,Use to assign domain for accessing DOM_SEC_PER and DOM_PRI_PER register. Only resource manager. group manager and domain owner can access this register. For write. group manager must write its owen domain ID. otherwise write accessing.." hexmask.long.byte 0x0 0.--3. 1. "DID,accessing DOM_SEC_PER and DOM_PRI_PER register" repeat.end tree.end tree "RPC_SAFETY_CLKGEN" base ad:0x3C800000 repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x4 0x8 0xC 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C ) group.long ($2)++0x3 line.long 0x0 "REGG0_DOM_$1,Assign domain for CKGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1A 0x1B 0x1C 0x1D 0x1E 0x1F )(list 0x40 0x44 0x48 0x4C 0x50 0x54 0x58 0x5C 0x60 0x64 0x68 0x6C 0x70 0x74 0x78 0x7C ) group.long ($2)++0x3 line.long 0x0 "REGG0_DOM_$1,Assign domain for CKGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x20 0x21 0x22 0x23 0x24 0x25 0x26 0x27 0x28 0x29 0x2A 0x2B 0x2C 0x2D 0x2E 0x2F )(list 0x80 0x84 0x88 0x8C 0x90 0x94 0x98 0x9C 0xA0 0xA4 0xA8 0xAC 0xB0 0xB4 0xB8 0xBC ) group.long ($2)++0x3 line.long 0x0 "REGG0_DOM_$1,Assign domain for CKGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x30 0x31 0x32 0x33 0x34 0x35 0x36 0x37 0x38 0x39 0x3A 0x3B 0x3C 0x3D 0x3E 0x3F )(list 0xC0 0xC4 0xC8 0xCC 0xD0 0xD4 0xD8 0xDC 0xE0 0xE4 0xE8 0xEC 0xF0 0xF4 0xF8 0xFC ) group.long ($2)++0x3 line.long 0x0 "REGG0_DOM_$1,Assign domain for CKGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x40 0x41 0x42 0x43 0x44 0x45 0x46 0x47 0x48 0x49 0x4A 0x4B 0x4C 0x4D 0x4E 0x4F )(list 0x100 0x104 0x108 0x10C 0x110 0x114 0x118 0x11C 0x120 0x124 0x128 0x12C 0x130 0x134 0x138 0x13C ) group.long ($2)++0x3 line.long 0x0 "REGG0_DOM_$1,Assign domain for CKGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x50 0x51 0x52 0x53 0x54 0x55 0x56 0x57 0x58 0x59 0x5A 0x5B 0x5C 0x5D 0x5E 0x5F )(list 0x140 0x144 0x148 0x14C 0x150 0x154 0x158 0x15C 0x160 0x164 0x168 0x16C 0x170 0x174 0x178 0x17C ) group.long ($2)++0x3 line.long 0x0 "REGG0_DOM_$1,Assign domain for CKGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x60 0x61 0x62 0x63 0x64 0x65 0x66 0x67 0x68 0x69 0x6A 0x6B 0x6C 0x6D 0x6E 0x6F )(list 0x180 0x184 0x188 0x18C 0x190 0x194 0x198 0x19C 0x1A0 0x1A4 0x1A8 0x1AC 0x1B0 0x1B4 0x1B8 0x1BC ) group.long ($2)++0x3 line.long 0x0 "REGG0_DOM_$1,Assign domain for CKGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x70 0x71 0x72 0x73 0x74 0x75 0x76 0x77 0x78 0x79 0x7A 0x7B 0x7C 0x7D 0x7E 0x7F )(list 0x1C0 0x1C4 0x1C8 0x1CC 0x1D0 0x1D4 0x1D8 0x1DC 0x1E0 0x1E4 0x1E8 0x1EC 0x1F0 0x1F4 0x1F8 0x1FC ) group.long ($2)++0x3 line.long 0x0 "REGG0_DOM_$1,Assign domain for CKGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x80 0x81 0x82 0x83 0x84 0x85 0x86 0x87 0x88 0x89 0x8A 0x8B 0x8C 0x8D 0x8E 0x8F )(list 0x200 0x204 0x208 0x20C 0x210 0x214 0x218 0x21C 0x220 0x224 0x228 0x22C 0x230 0x234 0x238 0x23C ) group.long ($2)++0x3 line.long 0x0 "REGG0_DOM_$1,Assign domain for CKGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x90 0x91 0x92 0x93 0x94 0x95 0x96 0x97 0x98 0x99 0x9A 0x9B 0x9C 0x9D 0x9E 0x9F )(list 0x240 0x244 0x248 0x24C 0x250 0x254 0x258 0x25C 0x260 0x264 0x268 0x26C 0x270 0x274 0x278 0x27C ) group.long ($2)++0x3 line.long 0x0 "REGG0_DOM_$1,Assign domain for CKGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xA0 0xA1 0xA2 0xA3 0xA4 0xA5 0xA6 0xA7 0xA8 0xA9 0xAA 0xAB 0xAC 0xAD 0xAE 0xAF )(list 0x280 0x284 0x288 0x28C 0x290 0x294 0x298 0x29C 0x2A0 0x2A4 0x2A8 0x2AC 0x2B0 0x2B4 0x2B8 0x2BC ) group.long ($2)++0x3 line.long 0x0 "REGG0_DOM_$1,Assign domain for CKGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xB0 0xB1 0xB2 0xB3 0xB4 0xB5 0xB6 0xB7 0xB8 0xB9 0xBA 0xBB 0xBC 0xBD 0xBE 0xBF )(list 0x2C0 0x2C4 0x2C8 0x2CC 0x2D0 0x2D4 0x2D8 0x2DC 0x2E0 0x2E4 0x2E8 0x2EC 0x2F0 0x2F4 0x2F8 0x2FC ) group.long ($2)++0x3 line.long 0x0 "REGG0_DOM_$1,Assign domain for CKGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xC0 0xC1 0xC2 0xC3 0xC4 0xC5 0xC6 0xC7 0xC8 0xC9 0xCA 0xCB 0xCC 0xCD 0xCE 0xCF )(list 0x300 0x304 0x308 0x30C 0x310 0x314 0x318 0x31C 0x320 0x324 0x328 0x32C 0x330 0x334 0x338 0x33C ) group.long ($2)++0x3 line.long 0x0 "REGG0_DOM_$1,Assign domain for CKGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xD0 0xD1 0xD2 0xD3 0xD4 0xD5 0xD6 0xD7 0xD8 0xD9 0xDA 0xDB 0xDC 0xDD 0xDE 0xDF )(list 0x340 0x344 0x348 0x34C 0x350 0x354 0x358 0x35C 0x360 0x364 0x368 0x36C 0x370 0x374 0x378 0x37C ) group.long ($2)++0x3 line.long 0x0 "REGG0_DOM_$1,Assign domain for CKGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xE0 0xE1 0xE2 0xE3 0xE4 0xE5 0xE6 0xE7 0xE8 0xE9 0xEA 0xEB 0xEC 0xED 0xEE 0xEF )(list 0x380 0x384 0x388 0x38C 0x390 0x394 0x398 0x39C 0x3A0 0x3A4 0x3A8 0x3AC 0x3B0 0x3B4 0x3B8 0x3BC ) group.long ($2)++0x3 line.long 0x0 "REGG0_DOM_$1,Assign domain for CKGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xF0 0xF1 0xF2 0xF3 0xF4 0xF5 0xF6 0xF7 0xF8 0xF9 0xFA 0xFB 0xFC 0xFD 0xFE 0xFF )(list 0x3C0 0x3C4 0x3C8 0x3CC 0x3D0 0x3D4 0x3D8 0x3DC 0x3E0 0x3E4 0x3E8 0x3EC 0x3F0 0x3F4 0x3F8 0x3FC ) group.long ($2)++0x3 line.long 0x0 "REGG0_DOM_$1,Assign domain for CKGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x4 0x8 0xC 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C ) group.long ($2+0x400)++0x3 line.long 0x0 "REGG1_DOM_$1,Assign domain for CKGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1A 0x1B 0x1C 0x1D 0x1E 0x1F )(list 0x40 0x44 0x48 0x4C 0x50 0x54 0x58 0x5C 0x60 0x64 0x68 0x6C 0x70 0x74 0x78 0x7C ) group.long ($2+0x400)++0x3 line.long 0x0 "REGG1_DOM_$1,Assign domain for CKGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x20 0x21 0x22 0x23 0x24 0x25 0x26 0x27 0x28 0x29 0x2A 0x2B 0x2C 0x2D 0x2E 0x2F )(list 0x80 0x84 0x88 0x8C 0x90 0x94 0x98 0x9C 0xA0 0xA4 0xA8 0xAC 0xB0 0xB4 0xB8 0xBC ) group.long ($2+0x400)++0x3 line.long 0x0 "REGG1_DOM_$1,Assign domain for CKGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x30 0x31 0x32 0x33 0x34 0x35 0x36 0x37 0x38 0x39 0x3A 0x3B 0x3C 0x3D 0x3E 0x3F )(list 0xC0 0xC4 0xC8 0xCC 0xD0 0xD4 0xD8 0xDC 0xE0 0xE4 0xE8 0xEC 0xF0 0xF4 0xF8 0xFC ) group.long ($2+0x400)++0x3 line.long 0x0 "REGG1_DOM_$1,Assign domain for CKGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x40 0x41 0x42 0x43 0x44 0x45 0x46 0x47 0x48 0x49 0x4A 0x4B 0x4C 0x4D 0x4E 0x4F )(list 0x100 0x104 0x108 0x10C 0x110 0x114 0x118 0x11C 0x120 0x124 0x128 0x12C 0x130 0x134 0x138 0x13C ) group.long ($2+0x400)++0x3 line.long 0x0 "REGG1_DOM_$1,Assign domain for CKGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x50 0x51 0x52 0x53 0x54 0x55 0x56 0x57 0x58 0x59 0x5A 0x5B 0x5C 0x5D 0x5E 0x5F )(list 0x140 0x144 0x148 0x14C 0x150 0x154 0x158 0x15C 0x160 0x164 0x168 0x16C 0x170 0x174 0x178 0x17C ) group.long ($2+0x400)++0x3 line.long 0x0 "REGG1_DOM_$1,Assign domain for CKGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x60 0x61 0x62 0x63 0x64 0x65 0x66 0x67 0x68 0x69 0x6A 0x6B 0x6C 0x6D 0x6E 0x6F )(list 0x180 0x184 0x188 0x18C 0x190 0x194 0x198 0x19C 0x1A0 0x1A4 0x1A8 0x1AC 0x1B0 0x1B4 0x1B8 0x1BC ) group.long ($2+0x400)++0x3 line.long 0x0 "REGG1_DOM_$1,Assign domain for CKGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x70 0x71 0x72 0x73 0x74 0x75 0x76 0x77 0x78 0x79 0x7A 0x7B 0x7C 0x7D 0x7E 0x7F )(list 0x1C0 0x1C4 0x1C8 0x1CC 0x1D0 0x1D4 0x1D8 0x1DC 0x1E0 0x1E4 0x1E8 0x1EC 0x1F0 0x1F4 0x1F8 0x1FC ) group.long ($2+0x400)++0x3 line.long 0x0 "REGG1_DOM_$1,Assign domain for CKGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x80 0x81 0x82 0x83 0x84 0x85 0x86 0x87 0x88 0x89 0x8A 0x8B 0x8C 0x8D 0x8E 0x8F )(list 0x200 0x204 0x208 0x20C 0x210 0x214 0x218 0x21C 0x220 0x224 0x228 0x22C 0x230 0x234 0x238 0x23C ) group.long ($2+0x400)++0x3 line.long 0x0 "REGG1_DOM_$1,Assign domain for CKGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x90 0x91 0x92 0x93 0x94 0x95 0x96 0x97 0x98 0x99 0x9A 0x9B 0x9C 0x9D 0x9E 0x9F )(list 0x240 0x244 0x248 0x24C 0x250 0x254 0x258 0x25C 0x260 0x264 0x268 0x26C 0x270 0x274 0x278 0x27C ) group.long ($2+0x400)++0x3 line.long 0x0 "REGG1_DOM_$1,Assign domain for CKGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xA0 0xA1 0xA2 0xA3 0xA4 0xA5 0xA6 0xA7 0xA8 0xA9 0xAA 0xAB 0xAC 0xAD 0xAE 0xAF )(list 0x280 0x284 0x288 0x28C 0x290 0x294 0x298 0x29C 0x2A0 0x2A4 0x2A8 0x2AC 0x2B0 0x2B4 0x2B8 0x2BC ) group.long ($2+0x400)++0x3 line.long 0x0 "REGG1_DOM_$1,Assign domain for CKGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xB0 0xB1 0xB2 0xB3 0xB4 0xB5 0xB6 0xB7 0xB8 0xB9 0xBA 0xBB 0xBC 0xBD 0xBE 0xBF )(list 0x2C0 0x2C4 0x2C8 0x2CC 0x2D0 0x2D4 0x2D8 0x2DC 0x2E0 0x2E4 0x2E8 0x2EC 0x2F0 0x2F4 0x2F8 0x2FC ) group.long ($2+0x400)++0x3 line.long 0x0 "REGG1_DOM_$1,Assign domain for CKGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xC0 0xC1 0xC2 0xC3 0xC4 0xC5 0xC6 0xC7 0xC8 0xC9 0xCA 0xCB 0xCC 0xCD 0xCE 0xCF )(list 0x300 0x304 0x308 0x30C 0x310 0x314 0x318 0x31C 0x320 0x324 0x328 0x32C 0x330 0x334 0x338 0x33C ) group.long ($2+0x400)++0x3 line.long 0x0 "REGG1_DOM_$1,Assign domain for CKGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xD0 0xD1 0xD2 0xD3 0xD4 0xD5 0xD6 0xD7 0xD8 0xD9 0xDA 0xDB 0xDC 0xDD 0xDE 0xDF )(list 0x340 0x344 0x348 0x34C 0x350 0x354 0x358 0x35C 0x360 0x364 0x368 0x36C 0x370 0x374 0x378 0x37C ) group.long ($2+0x400)++0x3 line.long 0x0 "REGG1_DOM_$1,Assign domain for CKGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xE0 0xE1 0xE2 0xE3 0xE4 0xE5 0xE6 0xE7 0xE8 0xE9 0xEA 0xEB 0xEC 0xED 0xEE 0xEF )(list 0x380 0x384 0x388 0x38C 0x390 0x394 0x398 0x39C 0x3A0 0x3A4 0x3A8 0x3AC 0x3B0 0x3B4 0x3B8 0x3BC ) group.long ($2+0x400)++0x3 line.long 0x0 "REGG1_DOM_$1,Assign domain for CKGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xF0 0xF1 0xF2 0xF3 0xF4 0xF5 0xF6 0xF7 0xF8 0xF9 0xFA 0xFB 0xFC 0xFD 0xFE 0xFF )(list 0x3C0 0x3C4 0x3C8 0x3CC 0x3D0 0x3D4 0x3D8 0x3DC 0x3E0 0x3E4 0x3E8 0x3EC 0x3F0 0x3F4 0x3F8 0x3FC ) group.long ($2+0x400)++0x3 line.long 0x0 "REGG1_DOM_$1,Assign domain for CKGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x4 0x8 0xC 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C ) group.long ($2+0x800)++0x3 line.long 0x0 "REGG2_DOM_$1,Assign domain for SCR registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1A 0x1B 0x1C 0x1D 0x1E 0x1F )(list 0x40 0x44 0x48 0x4C 0x50 0x54 0x58 0x5C 0x60 0x64 0x68 0x6C 0x70 0x74 0x78 0x7C ) group.long ($2+0x800)++0x3 line.long 0x0 "REGG2_DOM_$1,Assign domain for SCR registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x20 0x21 0x22 0x23 0x24 0x25 0x26 0x27 0x28 0x29 0x2A 0x2B 0x2C 0x2D 0x2E 0x2F )(list 0x80 0x84 0x88 0x8C 0x90 0x94 0x98 0x9C 0xA0 0xA4 0xA8 0xAC 0xB0 0xB4 0xB8 0xBC ) group.long ($2+0x800)++0x3 line.long 0x0 "REGG2_DOM_$1,Assign domain for SCR registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x30 0x31 0x32 0x33 0x34 0x35 0x36 0x37 0x38 0x39 0x3A 0x3B 0x3C 0x3D 0x3E 0x3F )(list 0xC0 0xC4 0xC8 0xCC 0xD0 0xD4 0xD8 0xDC 0xE0 0xE4 0xE8 0xEC 0xF0 0xF4 0xF8 0xFC ) group.long ($2+0x800)++0x3 line.long 0x0 "REGG2_DOM_$1,Assign domain for SCR registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x40 0x41 0x42 0x43 0x44 0x45 0x46 0x47 0x48 0x49 0x4A 0x4B 0x4C 0x4D 0x4E 0x4F )(list 0x100 0x104 0x108 0x10C 0x110 0x114 0x118 0x11C 0x120 0x124 0x128 0x12C 0x130 0x134 0x138 0x13C ) group.long ($2+0x800)++0x3 line.long 0x0 "REGG2_DOM_$1,Assign domain for SCR registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x50 0x51 0x52 0x53 0x54 0x55 0x56 0x57 0x58 0x59 0x5A 0x5B 0x5C 0x5D 0x5E 0x5F )(list 0x140 0x144 0x148 0x14C 0x150 0x154 0x158 0x15C 0x160 0x164 0x168 0x16C 0x170 0x174 0x178 0x17C ) group.long ($2+0x800)++0x3 line.long 0x0 "REGG2_DOM_$1,Assign domain for SCR registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x60 0x61 0x62 0x63 0x64 0x65 0x66 0x67 0x68 0x69 0x6A 0x6B 0x6C 0x6D 0x6E 0x6F )(list 0x180 0x184 0x188 0x18C 0x190 0x194 0x198 0x19C 0x1A0 0x1A4 0x1A8 0x1AC 0x1B0 0x1B4 0x1B8 0x1BC ) group.long ($2+0x800)++0x3 line.long 0x0 "REGG2_DOM_$1,Assign domain for SCR registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x70 0x71 0x72 0x73 0x74 0x75 0x76 0x77 0x78 0x79 0x7A 0x7B 0x7C 0x7D 0x7E 0x7F )(list 0x1C0 0x1C4 0x1C8 0x1CC 0x1D0 0x1D4 0x1D8 0x1DC 0x1E0 0x1E4 0x1E8 0x1EC 0x1F0 0x1F4 0x1F8 0x1FC ) group.long ($2+0x800)++0x3 line.long 0x0 "REGG2_DOM_$1,Assign domain for SCR registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x80 0x81 0x82 0x83 0x84 0x85 0x86 0x87 0x88 0x89 0x8A 0x8B 0x8C 0x8D 0x8E 0x8F )(list 0x200 0x204 0x208 0x20C 0x210 0x214 0x218 0x21C 0x220 0x224 0x228 0x22C 0x230 0x234 0x238 0x23C ) group.long ($2+0x800)++0x3 line.long 0x0 "REGG2_DOM_$1,Assign domain for SCR registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x90 0x91 0x92 0x93 0x94 0x95 0x96 0x97 0x98 0x99 0x9A 0x9B 0x9C 0x9D 0x9E 0x9F )(list 0x240 0x244 0x248 0x24C 0x250 0x254 0x258 0x25C 0x260 0x264 0x268 0x26C 0x270 0x274 0x278 0x27C ) group.long ($2+0x800)++0x3 line.long 0x0 "REGG2_DOM_$1,Assign domain for SCR registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xA0 0xA1 0xA2 0xA3 0xA4 0xA5 0xA6 0xA7 0xA8 0xA9 0xAA 0xAB 0xAC 0xAD 0xAE 0xAF )(list 0x280 0x284 0x288 0x28C 0x290 0x294 0x298 0x29C 0x2A0 0x2A4 0x2A8 0x2AC 0x2B0 0x2B4 0x2B8 0x2BC ) group.long ($2+0x800)++0x3 line.long 0x0 "REGG2_DOM_$1,Assign domain for SCR registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xB0 0xB1 0xB2 0xB3 0xB4 0xB5 0xB6 0xB7 0xB8 0xB9 0xBA 0xBB 0xBC 0xBD 0xBE 0xBF )(list 0x2C0 0x2C4 0x2C8 0x2CC 0x2D0 0x2D4 0x2D8 0x2DC 0x2E0 0x2E4 0x2E8 0x2EC 0x2F0 0x2F4 0x2F8 0x2FC ) group.long ($2+0x800)++0x3 line.long 0x0 "REGG2_DOM_$1,Assign domain for SCR registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xC0 0xC1 0xC2 0xC3 0xC4 0xC5 0xC6 0xC7 0xC8 0xC9 0xCA 0xCB 0xCC 0xCD 0xCE 0xCF )(list 0x300 0x304 0x308 0x30C 0x310 0x314 0x318 0x31C 0x320 0x324 0x328 0x32C 0x330 0x334 0x338 0x33C ) group.long ($2+0x800)++0x3 line.long 0x0 "REGG2_DOM_$1,Assign domain for SCR registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xD0 0xD1 0xD2 0xD3 0xD4 0xD5 0xD6 0xD7 0xD8 0xD9 0xDA 0xDB 0xDC 0xDD 0xDE 0xDF )(list 0x340 0x344 0x348 0x34C 0x350 0x354 0x358 0x35C 0x360 0x364 0x368 0x36C 0x370 0x374 0x378 0x37C ) group.long ($2+0x800)++0x3 line.long 0x0 "REGG2_DOM_$1,Assign domain for SCR registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xE0 0xE1 0xE2 0xE3 0xE4 0xE5 0xE6 0xE7 0xE8 0xE9 0xEA 0xEB 0xEC 0xED 0xEE 0xEF )(list 0x380 0x384 0x388 0x38C 0x390 0x394 0x398 0x39C 0x3A0 0x3A4 0x3A8 0x3AC 0x3B0 0x3B4 0x3B8 0x3BC ) group.long ($2+0x800)++0x3 line.long 0x0 "REGG2_DOM_$1,Assign domain for SCR registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xF0 0xF1 0xF2 0xF3 0xF4 0xF5 0xF6 0xF7 0xF8 0xF9 0xFA 0xFB 0xFC 0xFD 0xFE 0xFF )(list 0x3C0 0x3C4 0x3C8 0x3CC 0x3D0 0x3D4 0x3D8 0x3DC 0x3E0 0x3E4 0x3E8 0x3EC 0x3F0 0x3F4 0x3F8 0x3FC ) group.long ($2+0x800)++0x3 line.long 0x0 "REGG2_DOM_$1,Assign domain for SCR registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x4 0x8 0xC 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C ) group.long ($2+0xC00)++0x3 line.long 0x0 "REGG3_DOM_$1,Assign domain for SCR registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1A 0x1B 0x1C 0x1D 0x1E 0x1F )(list 0x40 0x44 0x48 0x4C 0x50 0x54 0x58 0x5C 0x60 0x64 0x68 0x6C 0x70 0x74 0x78 0x7C ) group.long ($2+0xC00)++0x3 line.long 0x0 "REGG3_DOM_$1,Assign domain for SCR registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x20 0x21 0x22 0x23 0x24 0x25 0x26 0x27 0x28 0x29 0x2A 0x2B 0x2C 0x2D 0x2E 0x2F )(list 0x80 0x84 0x88 0x8C 0x90 0x94 0x98 0x9C 0xA0 0xA4 0xA8 0xAC 0xB0 0xB4 0xB8 0xBC ) group.long ($2+0xC00)++0x3 line.long 0x0 "REGG3_DOM_$1,Assign domain for SCR registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x30 0x31 0x32 0x33 0x34 0x35 0x36 0x37 0x38 0x39 0x3A 0x3B 0x3C 0x3D 0x3E 0x3F )(list 0xC0 0xC4 0xC8 0xCC 0xD0 0xD4 0xD8 0xDC 0xE0 0xE4 0xE8 0xEC 0xF0 0xF4 0xF8 0xFC ) group.long ($2+0xC00)++0x3 line.long 0x0 "REGG3_DOM_$1,Assign domain for SCR registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x40 0x41 0x42 0x43 0x44 0x45 0x46 0x47 0x48 0x49 0x4A 0x4B 0x4C 0x4D 0x4E 0x4F )(list 0x100 0x104 0x108 0x10C 0x110 0x114 0x118 0x11C 0x120 0x124 0x128 0x12C 0x130 0x134 0x138 0x13C ) group.long ($2+0xC00)++0x3 line.long 0x0 "REGG3_DOM_$1,Assign domain for SCR registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x50 0x51 0x52 0x53 0x54 0x55 0x56 0x57 0x58 0x59 0x5A 0x5B 0x5C 0x5D 0x5E 0x5F )(list 0x140 0x144 0x148 0x14C 0x150 0x154 0x158 0x15C 0x160 0x164 0x168 0x16C 0x170 0x174 0x178 0x17C ) group.long ($2+0xC00)++0x3 line.long 0x0 "REGG3_DOM_$1,Assign domain for SCR registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x60 0x61 0x62 0x63 0x64 0x65 0x66 0x67 0x68 0x69 0x6A 0x6B 0x6C 0x6D 0x6E 0x6F )(list 0x180 0x184 0x188 0x18C 0x190 0x194 0x198 0x19C 0x1A0 0x1A4 0x1A8 0x1AC 0x1B0 0x1B4 0x1B8 0x1BC ) group.long ($2+0xC00)++0x3 line.long 0x0 "REGG3_DOM_$1,Assign domain for SCR registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x70 0x71 0x72 0x73 0x74 0x75 0x76 0x77 0x78 0x79 0x7A 0x7B 0x7C 0x7D 0x7E 0x7F )(list 0x1C0 0x1C4 0x1C8 0x1CC 0x1D0 0x1D4 0x1D8 0x1DC 0x1E0 0x1E4 0x1E8 0x1EC 0x1F0 0x1F4 0x1F8 0x1FC ) group.long ($2+0xC00)++0x3 line.long 0x0 "REGG3_DOM_$1,Assign domain for SCR registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x80 0x81 0x82 0x83 0x84 0x85 0x86 0x87 0x88 0x89 0x8A 0x8B 0x8C 0x8D 0x8E 0x8F )(list 0x200 0x204 0x208 0x20C 0x210 0x214 0x218 0x21C 0x220 0x224 0x228 0x22C 0x230 0x234 0x238 0x23C ) group.long ($2+0xC00)++0x3 line.long 0x0 "REGG3_DOM_$1,Assign domain for SCR registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x90 0x91 0x92 0x93 0x94 0x95 0x96 0x97 0x98 0x99 0x9A 0x9B 0x9C 0x9D 0x9E 0x9F )(list 0x240 0x244 0x248 0x24C 0x250 0x254 0x258 0x25C 0x260 0x264 0x268 0x26C 0x270 0x274 0x278 0x27C ) group.long ($2+0xC00)++0x3 line.long 0x0 "REGG3_DOM_$1,Assign domain for SCR registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xA0 0xA1 0xA2 0xA3 0xA4 0xA5 0xA6 0xA7 0xA8 0xA9 0xAA 0xAB 0xAC 0xAD 0xAE 0xAF )(list 0x280 0x284 0x288 0x28C 0x290 0x294 0x298 0x29C 0x2A0 0x2A4 0x2A8 0x2AC 0x2B0 0x2B4 0x2B8 0x2BC ) group.long ($2+0xC00)++0x3 line.long 0x0 "REGG3_DOM_$1,Assign domain for SCR registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xB0 0xB1 0xB2 0xB3 0xB4 0xB5 0xB6 0xB7 0xB8 0xB9 0xBA 0xBB 0xBC 0xBD 0xBE 0xBF )(list 0x2C0 0x2C4 0x2C8 0x2CC 0x2D0 0x2D4 0x2D8 0x2DC 0x2E0 0x2E4 0x2E8 0x2EC 0x2F0 0x2F4 0x2F8 0x2FC ) group.long ($2+0xC00)++0x3 line.long 0x0 "REGG3_DOM_$1,Assign domain for SCR registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xC0 0xC1 0xC2 0xC3 0xC4 0xC5 0xC6 0xC7 0xC8 0xC9 0xCA 0xCB 0xCC 0xCD 0xCE 0xCF )(list 0x300 0x304 0x308 0x30C 0x310 0x314 0x318 0x31C 0x320 0x324 0x328 0x32C 0x330 0x334 0x338 0x33C ) group.long ($2+0xC00)++0x3 line.long 0x0 "REGG3_DOM_$1,Assign domain for SCR registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xD0 0xD1 0xD2 0xD3 0xD4 0xD5 0xD6 0xD7 0xD8 0xD9 0xDA 0xDB 0xDC 0xDD 0xDE 0xDF )(list 0x340 0x344 0x348 0x34C 0x350 0x354 0x358 0x35C 0x360 0x364 0x368 0x36C 0x370 0x374 0x378 0x37C ) group.long ($2+0xC00)++0x3 line.long 0x0 "REGG3_DOM_$1,Assign domain for SCR registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xE0 0xE1 0xE2 0xE3 0xE4 0xE5 0xE6 0xE7 0xE8 0xE9 0xEA 0xEB 0xEC 0xED 0xEE 0xEF )(list 0x380 0x384 0x388 0x38C 0x390 0x394 0x398 0x39C 0x3A0 0x3A4 0x3A8 0x3AC 0x3B0 0x3B4 0x3B8 0x3BC ) group.long ($2+0xC00)++0x3 line.long 0x0 "REGG3_DOM_$1,Assign domain for SCR registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xF0 0xF1 0xF2 0xF3 0xF4 0xF5 0xF6 0xF7 0xF8 0xF9 0xFA 0xFB 0xFC 0xFD 0xFE 0xFF )(list 0x3C0 0x3C4 0x3C8 0x3CC 0x3D0 0x3D4 0x3D8 0x3DC 0x3E0 0x3E4 0x3E8 0x3EC 0x3F0 0x3F4 0x3F8 0x3FC ) group.long ($2+0xC00)++0x3 line.long 0x0 "REGG3_DOM_$1,Assign domain for SCR registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x4 0x8 0xC 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C ) group.long ($2+0x1000)++0x3 line.long 0x0 "REGG4_DOM_$1,Assign domain for RSTGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1A 0x1B 0x1C 0x1D 0x1E 0x1F )(list 0x40 0x44 0x48 0x4C 0x50 0x54 0x58 0x5C 0x60 0x64 0x68 0x6C 0x70 0x74 0x78 0x7C ) group.long ($2+0x1000)++0x3 line.long 0x0 "REGG4_DOM_$1,Assign domain for RSTGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x20 0x21 0x22 0x23 0x24 0x25 0x26 0x27 0x28 0x29 0x2A 0x2B 0x2C 0x2D 0x2E 0x2F )(list 0x80 0x84 0x88 0x8C 0x90 0x94 0x98 0x9C 0xA0 0xA4 0xA8 0xAC 0xB0 0xB4 0xB8 0xBC ) group.long ($2+0x1000)++0x3 line.long 0x0 "REGG4_DOM_$1,Assign domain for RSTGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x30 0x31 0x32 0x33 0x34 0x35 0x36 0x37 0x38 0x39 0x3A 0x3B 0x3C 0x3D 0x3E 0x3F )(list 0xC0 0xC4 0xC8 0xCC 0xD0 0xD4 0xD8 0xDC 0xE0 0xE4 0xE8 0xEC 0xF0 0xF4 0xF8 0xFC ) group.long ($2+0x1000)++0x3 line.long 0x0 "REGG4_DOM_$1,Assign domain for RSTGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x40 0x41 0x42 0x43 0x44 0x45 0x46 0x47 0x48 0x49 0x4A 0x4B 0x4C 0x4D 0x4E 0x4F )(list 0x100 0x104 0x108 0x10C 0x110 0x114 0x118 0x11C 0x120 0x124 0x128 0x12C 0x130 0x134 0x138 0x13C ) group.long ($2+0x1000)++0x3 line.long 0x0 "REGG4_DOM_$1,Assign domain for RSTGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x50 0x51 0x52 0x53 0x54 0x55 0x56 0x57 0x58 0x59 0x5A 0x5B 0x5C 0x5D 0x5E 0x5F )(list 0x140 0x144 0x148 0x14C 0x150 0x154 0x158 0x15C 0x160 0x164 0x168 0x16C 0x170 0x174 0x178 0x17C ) group.long ($2+0x1000)++0x3 line.long 0x0 "REGG4_DOM_$1,Assign domain for RSTGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x60 0x61 0x62 0x63 0x64 0x65 0x66 0x67 0x68 0x69 0x6A 0x6B 0x6C 0x6D 0x6E 0x6F )(list 0x180 0x184 0x188 0x18C 0x190 0x194 0x198 0x19C 0x1A0 0x1A4 0x1A8 0x1AC 0x1B0 0x1B4 0x1B8 0x1BC ) group.long ($2+0x1000)++0x3 line.long 0x0 "REGG4_DOM_$1,Assign domain for RSTGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x70 0x71 0x72 0x73 0x74 0x75 0x76 0x77 0x78 0x79 0x7A 0x7B 0x7C 0x7D 0x7E 0x7F )(list 0x1C0 0x1C4 0x1C8 0x1CC 0x1D0 0x1D4 0x1D8 0x1DC 0x1E0 0x1E4 0x1E8 0x1EC 0x1F0 0x1F4 0x1F8 0x1FC ) group.long ($2+0x1000)++0x3 line.long 0x0 "REGG4_DOM_$1,Assign domain for RSTGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x80 0x81 0x82 0x83 0x84 0x85 0x86 0x87 0x88 0x89 0x8A 0x8B 0x8C 0x8D 0x8E 0x8F )(list 0x200 0x204 0x208 0x20C 0x210 0x214 0x218 0x21C 0x220 0x224 0x228 0x22C 0x230 0x234 0x238 0x23C ) group.long ($2+0x1000)++0x3 line.long 0x0 "REGG4_DOM_$1,Assign domain for RSTGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x90 0x91 0x92 0x93 0x94 0x95 0x96 0x97 0x98 0x99 0x9A 0x9B 0x9C 0x9D 0x9E 0x9F )(list 0x240 0x244 0x248 0x24C 0x250 0x254 0x258 0x25C 0x260 0x264 0x268 0x26C 0x270 0x274 0x278 0x27C ) group.long ($2+0x1000)++0x3 line.long 0x0 "REGG4_DOM_$1,Assign domain for RSTGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xA0 0xA1 0xA2 0xA3 0xA4 0xA5 0xA6 0xA7 0xA8 0xA9 0xAA 0xAB 0xAC 0xAD 0xAE 0xAF )(list 0x280 0x284 0x288 0x28C 0x290 0x294 0x298 0x29C 0x2A0 0x2A4 0x2A8 0x2AC 0x2B0 0x2B4 0x2B8 0x2BC ) group.long ($2+0x1000)++0x3 line.long 0x0 "REGG4_DOM_$1,Assign domain for RSTGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xB0 0xB1 0xB2 0xB3 0xB4 0xB5 0xB6 0xB7 0xB8 0xB9 0xBA 0xBB 0xBC 0xBD 0xBE 0xBF )(list 0x2C0 0x2C4 0x2C8 0x2CC 0x2D0 0x2D4 0x2D8 0x2DC 0x2E0 0x2E4 0x2E8 0x2EC 0x2F0 0x2F4 0x2F8 0x2FC ) group.long ($2+0x1000)++0x3 line.long 0x0 "REGG4_DOM_$1,Assign domain for RSTGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xC0 0xC1 0xC2 0xC3 0xC4 0xC5 0xC6 0xC7 0xC8 0xC9 0xCA 0xCB 0xCC 0xCD 0xCE 0xCF )(list 0x300 0x304 0x308 0x30C 0x310 0x314 0x318 0x31C 0x320 0x324 0x328 0x32C 0x330 0x334 0x338 0x33C ) group.long ($2+0x1000)++0x3 line.long 0x0 "REGG4_DOM_$1,Assign domain for RSTGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xD0 0xD1 0xD2 0xD3 0xD4 0xD5 0xD6 0xD7 0xD8 0xD9 0xDA 0xDB 0xDC 0xDD 0xDE 0xDF )(list 0x340 0x344 0x348 0x34C 0x350 0x354 0x358 0x35C 0x360 0x364 0x368 0x36C 0x370 0x374 0x378 0x37C ) group.long ($2+0x1000)++0x3 line.long 0x0 "REGG4_DOM_$1,Assign domain for RSTGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xE0 0xE1 0xE2 0xE3 0xE4 0xE5 0xE6 0xE7 0xE8 0xE9 0xEA 0xEB 0xEC 0xED 0xEE 0xEF )(list 0x380 0x384 0x388 0x38C 0x390 0x394 0x398 0x39C 0x3A0 0x3A4 0x3A8 0x3AC 0x3B0 0x3B4 0x3B8 0x3BC ) group.long ($2+0x1000)++0x3 line.long 0x0 "REGG4_DOM_$1,Assign domain for RSTGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xF0 0xF1 0xF2 0xF3 0xF4 0xF5 0xF6 0xF7 0xF8 0xF9 0xFA 0xFB 0xFC 0xFD 0xFE 0xFF )(list 0x3C0 0x3C4 0x3C8 0x3CC 0x3D0 0x3D4 0x3D8 0x3DC 0x3E0 0x3E4 0x3E8 0x3EC 0x3F0 0x3F4 0x3F8 0x3FC ) group.long ($2+0x1000)++0x3 line.long 0x0 "REGG4_DOM_$1,Assign domain for RSTGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x4 0x8 0xC 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C ) group.long ($2+0x1400)++0x3 line.long 0x0 "REGG5_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1A 0x1B 0x1C 0x1D 0x1E 0x1F )(list 0x40 0x44 0x48 0x4C 0x50 0x54 0x58 0x5C 0x60 0x64 0x68 0x6C 0x70 0x74 0x78 0x7C ) group.long ($2+0x1400)++0x3 line.long 0x0 "REGG5_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x20 0x21 0x22 0x23 0x24 0x25 0x26 0x27 0x28 0x29 0x2A 0x2B 0x2C 0x2D 0x2E 0x2F )(list 0x80 0x84 0x88 0x8C 0x90 0x94 0x98 0x9C 0xA0 0xA4 0xA8 0xAC 0xB0 0xB4 0xB8 0xBC ) group.long ($2+0x1400)++0x3 line.long 0x0 "REGG5_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x30 0x31 0x32 0x33 0x34 0x35 0x36 0x37 0x38 0x39 0x3A 0x3B 0x3C 0x3D 0x3E 0x3F )(list 0xC0 0xC4 0xC8 0xCC 0xD0 0xD4 0xD8 0xDC 0xE0 0xE4 0xE8 0xEC 0xF0 0xF4 0xF8 0xFC ) group.long ($2+0x1400)++0x3 line.long 0x0 "REGG5_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x40 0x41 0x42 0x43 0x44 0x45 0x46 0x47 0x48 0x49 0x4A 0x4B 0x4C 0x4D 0x4E 0x4F )(list 0x100 0x104 0x108 0x10C 0x110 0x114 0x118 0x11C 0x120 0x124 0x128 0x12C 0x130 0x134 0x138 0x13C ) group.long ($2+0x1400)++0x3 line.long 0x0 "REGG5_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x50 0x51 0x52 0x53 0x54 0x55 0x56 0x57 0x58 0x59 0x5A 0x5B 0x5C 0x5D 0x5E 0x5F )(list 0x140 0x144 0x148 0x14C 0x150 0x154 0x158 0x15C 0x160 0x164 0x168 0x16C 0x170 0x174 0x178 0x17C ) group.long ($2+0x1400)++0x3 line.long 0x0 "REGG5_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x60 0x61 0x62 0x63 0x64 0x65 0x66 0x67 0x68 0x69 0x6A 0x6B 0x6C 0x6D 0x6E 0x6F )(list 0x180 0x184 0x188 0x18C 0x190 0x194 0x198 0x19C 0x1A0 0x1A4 0x1A8 0x1AC 0x1B0 0x1B4 0x1B8 0x1BC ) group.long ($2+0x1400)++0x3 line.long 0x0 "REGG5_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x70 0x71 0x72 0x73 0x74 0x75 0x76 0x77 0x78 0x79 0x7A 0x7B 0x7C 0x7D 0x7E 0x7F )(list 0x1C0 0x1C4 0x1C8 0x1CC 0x1D0 0x1D4 0x1D8 0x1DC 0x1E0 0x1E4 0x1E8 0x1EC 0x1F0 0x1F4 0x1F8 0x1FC ) group.long ($2+0x1400)++0x3 line.long 0x0 "REGG5_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x80 0x81 0x82 0x83 0x84 0x85 0x86 0x87 0x88 0x89 0x8A 0x8B 0x8C 0x8D 0x8E 0x8F )(list 0x200 0x204 0x208 0x20C 0x210 0x214 0x218 0x21C 0x220 0x224 0x228 0x22C 0x230 0x234 0x238 0x23C ) group.long ($2+0x1400)++0x3 line.long 0x0 "REGG5_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x90 0x91 0x92 0x93 0x94 0x95 0x96 0x97 0x98 0x99 0x9A 0x9B 0x9C 0x9D 0x9E 0x9F )(list 0x240 0x244 0x248 0x24C 0x250 0x254 0x258 0x25C 0x260 0x264 0x268 0x26C 0x270 0x274 0x278 0x27C ) group.long ($2+0x1400)++0x3 line.long 0x0 "REGG5_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xA0 0xA1 0xA2 0xA3 0xA4 0xA5 0xA6 0xA7 0xA8 0xA9 0xAA 0xAB 0xAC 0xAD 0xAE 0xAF )(list 0x280 0x284 0x288 0x28C 0x290 0x294 0x298 0x29C 0x2A0 0x2A4 0x2A8 0x2AC 0x2B0 0x2B4 0x2B8 0x2BC ) group.long ($2+0x1400)++0x3 line.long 0x0 "REGG5_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xB0 0xB1 0xB2 0xB3 0xB4 0xB5 0xB6 0xB7 0xB8 0xB9 0xBA 0xBB 0xBC 0xBD 0xBE 0xBF )(list 0x2C0 0x2C4 0x2C8 0x2CC 0x2D0 0x2D4 0x2D8 0x2DC 0x2E0 0x2E4 0x2E8 0x2EC 0x2F0 0x2F4 0x2F8 0x2FC ) group.long ($2+0x1400)++0x3 line.long 0x0 "REGG5_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xC0 0xC1 0xC2 0xC3 0xC4 0xC5 0xC6 0xC7 0xC8 0xC9 0xCA 0xCB 0xCC 0xCD 0xCE 0xCF )(list 0x300 0x304 0x308 0x30C 0x310 0x314 0x318 0x31C 0x320 0x324 0x328 0x32C 0x330 0x334 0x338 0x33C ) group.long ($2+0x1400)++0x3 line.long 0x0 "REGG5_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xD0 0xD1 0xD2 0xD3 0xD4 0xD5 0xD6 0xD7 0xD8 0xD9 0xDA 0xDB 0xDC 0xDD 0xDE 0xDF )(list 0x340 0x344 0x348 0x34C 0x350 0x354 0x358 0x35C 0x360 0x364 0x368 0x36C 0x370 0x374 0x378 0x37C ) group.long ($2+0x1400)++0x3 line.long 0x0 "REGG5_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xE0 0xE1 0xE2 0xE3 0xE4 0xE5 0xE6 0xE7 0xE8 0xE9 0xEA 0xEB 0xEC 0xED 0xEE 0xEF )(list 0x380 0x384 0x388 0x38C 0x390 0x394 0x398 0x39C 0x3A0 0x3A4 0x3A8 0x3AC 0x3B0 0x3B4 0x3B8 0x3BC ) group.long ($2+0x1400)++0x3 line.long 0x0 "REGG5_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xF0 0xF1 0xF2 0xF3 0xF4 0xF5 0xF6 0xF7 0xF8 0xF9 0xFA 0xFB 0xFC 0xFD 0xFE 0xFF )(list 0x3C0 0x3C4 0x3C8 0x3CC 0x3D0 0x3D4 0x3D8 0x3DC 0x3E0 0x3E4 0x3E8 0x3EC 0x3F0 0x3F4 0x3F8 0x3FC ) group.long ($2+0x1400)++0x3 line.long 0x0 "REGG5_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x4 0x8 0xC 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C ) group.long ($2+0x1800)++0x3 line.long 0x0 "REGG6_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1A 0x1B 0x1C 0x1D 0x1E 0x1F )(list 0x40 0x44 0x48 0x4C 0x50 0x54 0x58 0x5C 0x60 0x64 0x68 0x6C 0x70 0x74 0x78 0x7C ) group.long ($2+0x1800)++0x3 line.long 0x0 "REGG6_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x20 0x21 0x22 0x23 0x24 0x25 0x26 0x27 0x28 0x29 0x2A 0x2B 0x2C 0x2D 0x2E 0x2F )(list 0x80 0x84 0x88 0x8C 0x90 0x94 0x98 0x9C 0xA0 0xA4 0xA8 0xAC 0xB0 0xB4 0xB8 0xBC ) group.long ($2+0x1800)++0x3 line.long 0x0 "REGG6_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x30 0x31 0x32 0x33 0x34 0x35 0x36 0x37 0x38 0x39 0x3A 0x3B 0x3C 0x3D 0x3E 0x3F )(list 0xC0 0xC4 0xC8 0xCC 0xD0 0xD4 0xD8 0xDC 0xE0 0xE4 0xE8 0xEC 0xF0 0xF4 0xF8 0xFC ) group.long ($2+0x1800)++0x3 line.long 0x0 "REGG6_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x40 0x41 0x42 0x43 0x44 0x45 0x46 0x47 0x48 0x49 0x4A 0x4B 0x4C 0x4D 0x4E 0x4F )(list 0x100 0x104 0x108 0x10C 0x110 0x114 0x118 0x11C 0x120 0x124 0x128 0x12C 0x130 0x134 0x138 0x13C ) group.long ($2+0x1800)++0x3 line.long 0x0 "REGG6_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x50 0x51 0x52 0x53 0x54 0x55 0x56 0x57 0x58 0x59 0x5A 0x5B 0x5C 0x5D 0x5E 0x5F )(list 0x140 0x144 0x148 0x14C 0x150 0x154 0x158 0x15C 0x160 0x164 0x168 0x16C 0x170 0x174 0x178 0x17C ) group.long ($2+0x1800)++0x3 line.long 0x0 "REGG6_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x60 0x61 0x62 0x63 0x64 0x65 0x66 0x67 0x68 0x69 0x6A 0x6B 0x6C 0x6D 0x6E 0x6F )(list 0x180 0x184 0x188 0x18C 0x190 0x194 0x198 0x19C 0x1A0 0x1A4 0x1A8 0x1AC 0x1B0 0x1B4 0x1B8 0x1BC ) group.long ($2+0x1800)++0x3 line.long 0x0 "REGG6_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x70 0x71 0x72 0x73 0x74 0x75 0x76 0x77 0x78 0x79 0x7A 0x7B 0x7C 0x7D 0x7E 0x7F )(list 0x1C0 0x1C4 0x1C8 0x1CC 0x1D0 0x1D4 0x1D8 0x1DC 0x1E0 0x1E4 0x1E8 0x1EC 0x1F0 0x1F4 0x1F8 0x1FC ) group.long ($2+0x1800)++0x3 line.long 0x0 "REGG6_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x80 0x81 0x82 0x83 0x84 0x85 0x86 0x87 0x88 0x89 0x8A 0x8B 0x8C 0x8D 0x8E 0x8F )(list 0x200 0x204 0x208 0x20C 0x210 0x214 0x218 0x21C 0x220 0x224 0x228 0x22C 0x230 0x234 0x238 0x23C ) group.long ($2+0x1800)++0x3 line.long 0x0 "REGG6_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x90 0x91 0x92 0x93 0x94 0x95 0x96 0x97 0x98 0x99 0x9A 0x9B 0x9C 0x9D 0x9E 0x9F )(list 0x240 0x244 0x248 0x24C 0x250 0x254 0x258 0x25C 0x260 0x264 0x268 0x26C 0x270 0x274 0x278 0x27C ) group.long ($2+0x1800)++0x3 line.long 0x0 "REGG6_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xA0 0xA1 0xA2 0xA3 0xA4 0xA5 0xA6 0xA7 0xA8 0xA9 0xAA 0xAB 0xAC 0xAD 0xAE 0xAF )(list 0x280 0x284 0x288 0x28C 0x290 0x294 0x298 0x29C 0x2A0 0x2A4 0x2A8 0x2AC 0x2B0 0x2B4 0x2B8 0x2BC ) group.long ($2+0x1800)++0x3 line.long 0x0 "REGG6_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xB0 0xB1 0xB2 0xB3 0xB4 0xB5 0xB6 0xB7 0xB8 0xB9 0xBA 0xBB 0xBC 0xBD 0xBE 0xBF )(list 0x2C0 0x2C4 0x2C8 0x2CC 0x2D0 0x2D4 0x2D8 0x2DC 0x2E0 0x2E4 0x2E8 0x2EC 0x2F0 0x2F4 0x2F8 0x2FC ) group.long ($2+0x1800)++0x3 line.long 0x0 "REGG6_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xC0 0xC1 0xC2 0xC3 0xC4 0xC5 0xC6 0xC7 0xC8 0xC9 0xCA 0xCB 0xCC 0xCD 0xCE 0xCF )(list 0x300 0x304 0x308 0x30C 0x310 0x314 0x318 0x31C 0x320 0x324 0x328 0x32C 0x330 0x334 0x338 0x33C ) group.long ($2+0x1800)++0x3 line.long 0x0 "REGG6_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xD0 0xD1 0xD2 0xD3 0xD4 0xD5 0xD6 0xD7 0xD8 0xD9 0xDA 0xDB 0xDC 0xDD 0xDE 0xDF )(list 0x340 0x344 0x348 0x34C 0x350 0x354 0x358 0x35C 0x360 0x364 0x368 0x36C 0x370 0x374 0x378 0x37C ) group.long ($2+0x1800)++0x3 line.long 0x0 "REGG6_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xE0 0xE1 0xE2 0xE3 0xE4 0xE5 0xE6 0xE7 0xE8 0xE9 0xEA 0xEB 0xEC 0xED 0xEE 0xEF )(list 0x380 0x384 0x388 0x38C 0x390 0x394 0x398 0x39C 0x3A0 0x3A4 0x3A8 0x3AC 0x3B0 0x3B4 0x3B8 0x3BC ) group.long ($2+0x1800)++0x3 line.long 0x0 "REGG6_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xF0 0xF1 0xF2 0xF3 0xF4 0xF5 0xF6 0xF7 0xF8 0xF9 0xFA 0xFB 0xFC 0xFD 0xFE 0xFF )(list 0x3C0 0x3C4 0x3C8 0x3CC 0x3D0 0x3D4 0x3D8 0x3DC 0x3E0 0x3E4 0x3E8 0x3EC 0x3F0 0x3F4 0x3F8 0x3FC ) group.long ($2+0x1800)++0x3 line.long 0x0 "REGG6_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x4 0x8 0xC 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C ) group.long ($2+0x1C00)++0x3 line.long 0x0 "REGG7_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1A 0x1B 0x1C 0x1D 0x1E 0x1F )(list 0x40 0x44 0x48 0x4C 0x50 0x54 0x58 0x5C 0x60 0x64 0x68 0x6C 0x70 0x74 0x78 0x7C ) group.long ($2+0x1C00)++0x3 line.long 0x0 "REGG7_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x20 0x21 0x22 0x23 0x24 0x25 0x26 0x27 0x28 0x29 0x2A 0x2B 0x2C 0x2D 0x2E 0x2F )(list 0x80 0x84 0x88 0x8C 0x90 0x94 0x98 0x9C 0xA0 0xA4 0xA8 0xAC 0xB0 0xB4 0xB8 0xBC ) group.long ($2+0x1C00)++0x3 line.long 0x0 "REGG7_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x30 0x31 0x32 0x33 0x34 0x35 0x36 0x37 0x38 0x39 0x3A 0x3B 0x3C 0x3D 0x3E 0x3F )(list 0xC0 0xC4 0xC8 0xCC 0xD0 0xD4 0xD8 0xDC 0xE0 0xE4 0xE8 0xEC 0xF0 0xF4 0xF8 0xFC ) group.long ($2+0x1C00)++0x3 line.long 0x0 "REGG7_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x40 0x41 0x42 0x43 0x44 0x45 0x46 0x47 0x48 0x49 0x4A 0x4B 0x4C 0x4D 0x4E 0x4F )(list 0x100 0x104 0x108 0x10C 0x110 0x114 0x118 0x11C 0x120 0x124 0x128 0x12C 0x130 0x134 0x138 0x13C ) group.long ($2+0x1C00)++0x3 line.long 0x0 "REGG7_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x50 0x51 0x52 0x53 0x54 0x55 0x56 0x57 0x58 0x59 0x5A 0x5B 0x5C 0x5D 0x5E 0x5F )(list 0x140 0x144 0x148 0x14C 0x150 0x154 0x158 0x15C 0x160 0x164 0x168 0x16C 0x170 0x174 0x178 0x17C ) group.long ($2+0x1C00)++0x3 line.long 0x0 "REGG7_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x60 0x61 0x62 0x63 0x64 0x65 0x66 0x67 0x68 0x69 0x6A 0x6B 0x6C 0x6D 0x6E 0x6F )(list 0x180 0x184 0x188 0x18C 0x190 0x194 0x198 0x19C 0x1A0 0x1A4 0x1A8 0x1AC 0x1B0 0x1B4 0x1B8 0x1BC ) group.long ($2+0x1C00)++0x3 line.long 0x0 "REGG7_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x70 0x71 0x72 0x73 0x74 0x75 0x76 0x77 0x78 0x79 0x7A 0x7B 0x7C 0x7D 0x7E 0x7F )(list 0x1C0 0x1C4 0x1C8 0x1CC 0x1D0 0x1D4 0x1D8 0x1DC 0x1E0 0x1E4 0x1E8 0x1EC 0x1F0 0x1F4 0x1F8 0x1FC ) group.long ($2+0x1C00)++0x3 line.long 0x0 "REGG7_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x80 0x81 0x82 0x83 0x84 0x85 0x86 0x87 0x88 0x89 0x8A 0x8B 0x8C 0x8D 0x8E 0x8F )(list 0x200 0x204 0x208 0x20C 0x210 0x214 0x218 0x21C 0x220 0x224 0x228 0x22C 0x230 0x234 0x238 0x23C ) group.long ($2+0x1C00)++0x3 line.long 0x0 "REGG7_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x90 0x91 0x92 0x93 0x94 0x95 0x96 0x97 0x98 0x99 0x9A 0x9B 0x9C 0x9D 0x9E 0x9F )(list 0x240 0x244 0x248 0x24C 0x250 0x254 0x258 0x25C 0x260 0x264 0x268 0x26C 0x270 0x274 0x278 0x27C ) group.long ($2+0x1C00)++0x3 line.long 0x0 "REGG7_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xA0 0xA1 0xA2 0xA3 0xA4 0xA5 0xA6 0xA7 0xA8 0xA9 0xAA 0xAB 0xAC 0xAD 0xAE 0xAF )(list 0x280 0x284 0x288 0x28C 0x290 0x294 0x298 0x29C 0x2A0 0x2A4 0x2A8 0x2AC 0x2B0 0x2B4 0x2B8 0x2BC ) group.long ($2+0x1C00)++0x3 line.long 0x0 "REGG7_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xB0 0xB1 0xB2 0xB3 0xB4 0xB5 0xB6 0xB7 0xB8 0xB9 0xBA 0xBB 0xBC 0xBD 0xBE 0xBF )(list 0x2C0 0x2C4 0x2C8 0x2CC 0x2D0 0x2D4 0x2D8 0x2DC 0x2E0 0x2E4 0x2E8 0x2EC 0x2F0 0x2F4 0x2F8 0x2FC ) group.long ($2+0x1C00)++0x3 line.long 0x0 "REGG7_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xC0 0xC1 0xC2 0xC3 0xC4 0xC5 0xC6 0xC7 0xC8 0xC9 0xCA 0xCB 0xCC 0xCD 0xCE 0xCF )(list 0x300 0x304 0x308 0x30C 0x310 0x314 0x318 0x31C 0x320 0x324 0x328 0x32C 0x330 0x334 0x338 0x33C ) group.long ($2+0x1C00)++0x3 line.long 0x0 "REGG7_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xD0 0xD1 0xD2 0xD3 0xD4 0xD5 0xD6 0xD7 0xD8 0xD9 0xDA 0xDB 0xDC 0xDD 0xDE 0xDF )(list 0x340 0x344 0x348 0x34C 0x350 0x354 0x358 0x35C 0x360 0x364 0x368 0x36C 0x370 0x374 0x378 0x37C ) group.long ($2+0x1C00)++0x3 line.long 0x0 "REGG7_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xE0 0xE1 0xE2 0xE3 0xE4 0xE5 0xE6 0xE7 0xE8 0xE9 0xEA 0xEB 0xEC 0xED 0xEE 0xEF )(list 0x380 0x384 0x388 0x38C 0x390 0x394 0x398 0x39C 0x3A0 0x3A4 0x3A8 0x3AC 0x3B0 0x3B4 0x3B8 0x3BC ) group.long ($2+0x1C00)++0x3 line.long 0x0 "REGG7_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xF0 0xF1 0xF2 0xF3 0xF4 0xF5 0xF6 0xF7 0xF8 0xF9 0xFA 0xFB 0xFC 0xFD 0xFE 0xFF )(list 0x3C0 0x3C4 0x3C8 0x3CC 0x3D0 0x3D4 0x3D8 0x3DC 0x3E0 0x3E4 0x3E8 0x3EC 0x3F0 0x3F4 0x3F8 0x3FC ) group.long ($2+0x1C00)++0x3 line.long 0x0 "REGG7_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end group.long 0x2000++0x17 line.long 0x0 "GLB_CTL,This register provides global enable settings for permission control." bitfld.long 0x0 5. "DOM_CFG_LOCK,Lock write for DOM_CFG_MODE bit." "0,1" bitfld.long 0x0 4. "DOM_CFG_MODE,When enabled all the source setting can be configured by master from domain 0 if it is not locked. When disabled only resource manager can configure the permission of the resource." "0,1" bitfld.long 0x0 3. "PERCK_DIS_LOCK,Lock write for PERCK_DIS" "0,1" bitfld.long 0x0 2. "PERCK_DIS,All the permission check disable." "0,1" newline bitfld.long 0x0 1. "DOM_PRO_LOCK,Lock write for DOM_PRO_EN bit." "0,1" bitfld.long 0x0 0. "DOM_PRO_EN,When disabled no domain access permission check" "0,1" line.long 0x4 "RES_MGR,Resource manager register. This regster is used to assign resource manager for global resource access control" bitfld.long 0x4 17. "MID_LOCK,Lock write for MID_EN and MID_LOW and MID_HIG registers." "0,1" bitfld.long 0x4 16. "MID_EN,Master ID check enable" "0,1" bitfld.long 0x4 15. "PRI_PER_LOCK,Lock write for PRI_PER and PRI_PER_EN" "0,1" bitfld.long 0x4 13.--14. "PRI_PER,Resource manager privileged access permission. bit0 for privileged access bit1 for user access" "0,1,2,3" newline bitfld.long 0x4 12. "PRI_PER_EN,Resource manager privileged access permission enable." "0,1" bitfld.long 0x4 11. "SEC_PER_LOCK,Lock for SEC_PER and SEC_PER_LOCK" "0,1" bitfld.long 0x4 9.--10. "SEC_PER,Resource manager secure access permission. bit 0 for secure access bit 1 for non-secure access" "0,1,2,3" bitfld.long 0x4 8. "SEC_PER_EN,Resource manager secure permission enable" "0,1" bitfld.long 0x4 7. "DID_LOCK,Lock write for DID_EN and DID" "0,1" newline hexmask.long.byte 0x4 3.--6. 1. "DID,Resource manager domain ID" bitfld.long 0x4 2. "DID_EN,Resource manager Domain ID enable" "0,1" bitfld.long 0x4 1. "RES_MGR_EN_LOCK,Lock for RES_MGR_EN" "0,1" bitfld.long 0x4 0. "RES_MGR_EN,Resource manager enable. When the bit is disable there is no resource manager." "0,1" line.long 0x8 "RES_MGR_MA0,This register is used to assign master 0~31 as resource manager." hexmask.long 0x8 0.--31. 1. "MID,Assign master 0~31 for resource manager" line.long 0xC "RES_MGR_MA1,This register is used to assign master 32~63 as resource manager." hexmask.long 0xC 0.--31. 1. "MID,Indicate if master 32~63 is resource manager." line.long 0x10 "RES_MGR_MA2,This register is used to assign master 64~95 as resource manager." hexmask.long 0x10 0.--31. 1. "MID,Indicate if master 64~95 is resource manager." line.long 0x14 "RES_MGR_MA3,This register is used to assign master 96~127 as resource manager." hexmask.long 0x14 0.--31. 1. "MID,Indicate if master 96~127 is resource manager." repeat 8. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 )(list 0x0 0x14 0x28 0x3C 0x50 0x64 0x78 0x8C ) group.long ($2+0x2100)++0x3 line.long 0x0 "GRP_MGR_$1,Group Manager Register. This register is used to assign group manager for each domain" bitfld.long 0x0 17. "MID_LOCK,Lock write for MID_EN and MID_LOW and MID_HIG registers." "0,1" bitfld.long 0x0 16. "MID_EN,Master ID check enable" "0,1" bitfld.long 0x0 15. "PRI_PER_LOCK,Lock write for PRI_PER and PRI_PER_EN" "0,1" bitfld.long 0x0 13.--14. "PRI_PER,Group manager privileged access permission. bit0 for privileged access bit1 for user access" "0,1,2,3" newline bitfld.long 0x0 12. "PRI_PER_EN,Group manager privileged access permission enable." "0,1" bitfld.long 0x0 11. "SEC_PER_LOCK,Lock for SEC_PER and SEC_PER_LOCK" "0,1" bitfld.long 0x0 9.--10. "SEC_PER,Group manager secure access permission. bit 0 for secure access bit 1 for non-secure access" "0,1,2,3" bitfld.long 0x0 8. "SEC_PER_EN,Group manager secure permission enable" "0,1" bitfld.long 0x0 7. "DID_LOCK,Lock write for DID_EN and DID" "0,1" newline hexmask.long.byte 0x0 3.--6. 1. "DID,Group manager domain ID" bitfld.long 0x0 2. "DID_EN,Group manager Domain ID enable" "0,1" bitfld.long 0x0 1. "GRP_MGR_EN_LOCK,Lock write for GPR_MGR_EN" "0,1" bitfld.long 0x0 0. "GRP_MGR_EN,Group manager enable. When the bit is disable there is no resource manager." "0,1" repeat.end repeat 8. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 )(list 0x0 0x14 0x28 0x3C 0x50 0x64 0x78 0x8C ) group.long ($2+0x2104)++0x3 line.long 0x0 "GRP_MGR_MA0_$1,Assign master 0~31 for group manager 0" hexmask.long 0x0 0.--31. 1. "MID,Assign master 0~31 for resource manager" repeat.end repeat 8. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 )(list 0x0 0x14 0x28 0x3C 0x50 0x64 0x78 0x8C ) group.long ($2+0x2108)++0x3 line.long 0x0 "GRP_MGR_MA1_$1,Assign master 32~63 for group manager 0" hexmask.long 0x0 0.--31. 1. "MID,Indicate if master 32~63 is resource manager." repeat.end repeat 8. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 )(list 0x0 0x14 0x28 0x3C 0x50 0x64 0x78 0x8C ) group.long ($2+0x210C)++0x3 line.long 0x0 "GRP_MGR_MA2_$1,Assign master 64~95 for group manager 0" hexmask.long 0x0 0.--31. 1. "MID,Indicate if master 64~95 is resource manager." repeat.end repeat 8. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 )(list 0x0 0x14 0x28 0x3C 0x50 0x64 0x78 0x8C ) group.long ($2+0x2110)++0x3 line.long 0x0 "GRP_MGR_MA3_$1,Assign master 96~127 for group manager 0" hexmask.long 0x0 0.--31. 1. "MID,Indicate if master 96~127 is resource manager." repeat.end group.long 0x2200++0x3 line.long 0x0 "DOM_GID_0,Indicate which group domain 0 belong to" bitfld.long 0x0 3. "LOCK,Lock write for GID" "0,1" bitfld.long 0x0 0.--2. "GID,Group ID" "0,1,2,3,4,5,6,7" repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x18 0x30 0x48 0x60 0x78 0x90 0xA8 0xC0 0xD8 0xF0 0x108 0x120 0x138 0x150 0x168 ) group.long ($2+0x2204)++0x3 line.long 0x0 "DOM_OWN_$1,Assign owner for function domain 0." bitfld.long 0x0 17. "MID_LOCK,Lock write for MID_EN and MID_LOW and MID_HIG registers." "0,1" bitfld.long 0x0 16. "MID_EN,Master ID check enable" "0,1" bitfld.long 0x0 15. "PRI_PER_LOCK,Lock write for PRI_PER and PRI_PER_EN" "0,1" bitfld.long 0x0 13.--14. "PRI_PER,Group manager privileged access permission. bit0 for privileged access bit1 for user access" "0,1,2,3" newline bitfld.long 0x0 12. "PRI_PER_EN,Group manager privileged access permission enable." "0,1" bitfld.long 0x0 11. "SEC_PER_LOCK,Lock for SEC_PER and SEC_PER_LOCK" "0,1" bitfld.long 0x0 9.--10. "SEC_PER,Domain owner secure access permission. bit 0 for secure access bit 1 for non-secure access" "0,1,2,3" bitfld.long 0x0 8. "SEC_PER_EN,Domain owner secure permission enable" "0,1" newline bitfld.long 0x0 1. "DOM_OWN_EN_LOCK,Lock for DOM_OWN_EN" "0,1" bitfld.long 0x0 0. "DOM_OWN_EN,Domain owner enable. When the bit is disable there is no domain owner." "0,1" repeat.end repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x18 0x30 0x48 0x60 0x78 0x90 0xA8 0xC0 0xD8 0xF0 0x108 0x120 0x138 0x150 0x168 ) group.long ($2+0x2208)++0x3 line.long 0x0 "DOM_OWN_MA0_$1,Assign master 0~31 for domain owner 0" hexmask.long 0x0 0.--31. 1. "MID,Assign master 0~31 for resource manager" repeat.end repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x18 0x30 0x48 0x60 0x78 0x90 0xA8 0xC0 0xD8 0xF0 0x108 0x120 0x138 0x150 0x168 ) group.long ($2+0x220C)++0x3 line.long 0x0 "DOM_OWN_MA1_$1,Assign master 32~63 for domain owner 0" hexmask.long 0x0 0.--31. 1. "MID,Indicate if master 32~63 is resource manager." repeat.end repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x18 0x30 0x48 0x60 0x78 0x90 0xA8 0xC0 0xD8 0xF0 0x108 0x120 0x138 0x150 0x168 ) group.long ($2+0x2210)++0x3 line.long 0x0 "DOM_OWN_MA2_$1,Assign master 64~95 for domain owner 0" hexmask.long 0x0 0.--31. 1. "MID,Indicate if master 64~95 is resource manager." repeat.end repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x18 0x30 0x48 0x60 0x78 0x90 0xA8 0xC0 0xD8 0xF0 0x108 0x120 0x138 0x150 0x168 ) group.long ($2+0x2214)++0x3 line.long 0x0 "DOM_OWN_MA3_$1,Assign master 96~127 for domain owner 0" hexmask.long 0x0 0.--31. 1. "MID,Indicate if master 96~127 is resource manager." repeat.end group.long 0x2218++0x3 line.long 0x0 "DOM_GID_1,Indicate which group domain 1 belong to" bitfld.long 0x0 3. "LOCK,Lock write for GID" "0,1" bitfld.long 0x0 0.--2. "GID,Group ID" "0,1,2,3,4,5,6,7" group.long 0x2230++0x3 line.long 0x0 "DOM_GID_2,Indicate which group domain 2 belong to" bitfld.long 0x0 3. "LOCK,Lock write for GID" "0,1" bitfld.long 0x0 0.--2. "GID,Group ID" "0,1,2,3,4,5,6,7" group.long 0x2248++0x3 line.long 0x0 "DOM_GID_3,Indicate which group domain 3 belong to" bitfld.long 0x0 3. "LOCK,Lock write for GID" "0,1" bitfld.long 0x0 0.--2. "GID,Group ID" "0,1,2,3,4,5,6,7" group.long 0x2260++0x3 line.long 0x0 "DOM_GID_4,Indicate which group domain 4 belong to" bitfld.long 0x0 3. "LOCK,Lock write for GID" "0,1" bitfld.long 0x0 0.--2. "GID,Group ID" "0,1,2,3,4,5,6,7" group.long 0x2278++0x3 line.long 0x0 "DOM_GID_5,Indicate which group domain 5 belong to" bitfld.long 0x0 3. "LOCK,Lock write for GID" "0,1" bitfld.long 0x0 0.--2. "GID,Group ID" "0,1,2,3,4,5,6,7" group.long 0x2290++0x3 line.long 0x0 "DOM_GID_6,Indicate which group domain 6 belong to" bitfld.long 0x0 3. "LOCK,Lock write for GID" "0,1" bitfld.long 0x0 0.--2. "GID,Group ID" "0,1,2,3,4,5,6,7" group.long 0x22A8++0x3 line.long 0x0 "DOM_GID_7,Indicate which group domain 7 belong to" bitfld.long 0x0 3. "LOCK,Lock write for GID" "0,1" bitfld.long 0x0 0.--2. "GID,Group ID" "0,1,2,3,4,5,6,7" group.long 0x22C0++0x3 line.long 0x0 "DOM_GID_8,Indicate which group domain 8 belong to" bitfld.long 0x0 3. "LOCK,Lock write for GID" "0,1" bitfld.long 0x0 0.--2. "GID,Group ID" "0,1,2,3,4,5,6,7" group.long 0x22D8++0x3 line.long 0x0 "DOM_GID_9,Indicate which group domain 9 belong to" bitfld.long 0x0 3. "LOCK,Lock write for GID" "0,1" bitfld.long 0x0 0.--2. "GID,Group ID" "0,1,2,3,4,5,6,7" group.long 0x22F0++0x3 line.long 0x0 "DOM_GID_10,Indicate which group domain 10 belong to" bitfld.long 0x0 3. "LOCK,Lock write for GID" "0,1" bitfld.long 0x0 0.--2. "GID,Group ID" "0,1,2,3,4,5,6,7" group.long 0x2308++0x3 line.long 0x0 "DOM_GID_11,Indicate which group domain 11 belong to" bitfld.long 0x0 3. "LOCK,Lock write for GID" "0,1" bitfld.long 0x0 0.--2. "GID,Group ID" "0,1,2,3,4,5,6,7" group.long 0x2320++0x3 line.long 0x0 "DOM_GID_12,Indicate which group domain 12 belong to" bitfld.long 0x0 3. "LOCK,Lock write for GID" "0,1" bitfld.long 0x0 0.--2. "GID,Group ID" "0,1,2,3,4,5,6,7" group.long 0x2338++0x3 line.long 0x0 "DOM_GID_13,Indicate which group domain 13 belong to" bitfld.long 0x0 3. "LOCK,Lock write for GID" "0,1" bitfld.long 0x0 0.--2. "GID,Group ID" "0,1,2,3,4,5,6,7" group.long 0x2350++0x3 line.long 0x0 "DOM_GID_14,Indicate which group domain 14 belong to" bitfld.long 0x0 3. "LOCK,Lock write for GID" "0,1" bitfld.long 0x0 0.--2. "GID,Group ID" "0,1,2,3,4,5,6,7" group.long 0x2368++0x3 line.long 0x0 "DOM_GID_15,Indicate which group domain 15 belong to" bitfld.long 0x0 3. "LOCK,Lock write for GID" "0,1" bitfld.long 0x0 0.--2. "GID,Group ID" "0,1,2,3,4,5,6,7" repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x34 0x68 0x9C 0xD0 0x104 0x138 0x16C 0x1A0 0x1D4 0x208 0x23C 0x270 0x2A4 0x2D8 0x30C ) group.long ($2+0x2400)++0x3 line.long 0x0 "DOM_PER0_$1,Domain Permission Control. It can be only configured by resource manager and domain owner." bitfld.long 0x0 31. "DOM7_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 29.--30. "DOM7_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 28. "DOM7_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 27. "DOM6_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 25.--26. "DOM6_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" newline bitfld.long 0x0 24. "DOM6_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 23. "DOM5_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 21.--22. "DOM5_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 20. "DOM5_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 19. "DOM4_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" newline bitfld.long 0x0 17.--18. "DOM4_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM4_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 15. "DOM3_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 13.--14. "DOM3_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 12. "DOM3_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" newline bitfld.long 0x0 11. "DOM2_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 9.--10. "DOM2_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM2_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 7. "DOM1_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 5.--6. "DOM1_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" newline bitfld.long 0x0 4. "DOM1_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 3. "DOM0_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 1.--2. "DOM0_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM0_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" repeat.end repeat 16. (list 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1A 0x1B 0x1C 0x1D 0x1E 0x1F )(list 0x340 0x374 0x3A8 0x3DC 0x410 0x444 0x478 0x4AC 0x4E0 0x514 0x548 0x57C 0x5B0 0x5E4 0x618 0x64C ) group.long ($2+0x2400)++0x3 line.long 0x0 "DOM_PER0_$1,Domain Permission Control. It can be only configured by resource manager and domain owner." bitfld.long 0x0 31. "DOM7_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 29.--30. "DOM7_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 28. "DOM7_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 27. "DOM6_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 25.--26. "DOM6_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" newline bitfld.long 0x0 24. "DOM6_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 23. "DOM5_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 21.--22. "DOM5_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 20. "DOM5_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 19. "DOM4_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" newline bitfld.long 0x0 17.--18. "DOM4_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM4_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 15. "DOM3_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 13.--14. "DOM3_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 12. "DOM3_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" newline bitfld.long 0x0 11. "DOM2_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 9.--10. "DOM2_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM2_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 7. "DOM1_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 5.--6. "DOM1_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" newline bitfld.long 0x0 4. "DOM1_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 3. "DOM0_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 1.--2. "DOM0_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM0_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" repeat.end repeat 16. (list 0x20 0x21 0x22 0x23 0x24 0x25 0x26 0x27 0x28 0x29 0x2A 0x2B 0x2C 0x2D 0x2E 0x2F )(list 0x680 0x6B4 0x6E8 0x71C 0x750 0x784 0x7B8 0x7EC 0x820 0x854 0x888 0x8BC 0x8F0 0x924 0x958 0x98C ) group.long ($2+0x2400)++0x3 line.long 0x0 "DOM_PER0_$1,Domain Permission Control. It can be only configured by resource manager and domain owner." bitfld.long 0x0 31. "DOM7_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 29.--30. "DOM7_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 28. "DOM7_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 27. "DOM6_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 25.--26. "DOM6_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" newline bitfld.long 0x0 24. "DOM6_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 23. "DOM5_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 21.--22. "DOM5_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 20. "DOM5_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 19. "DOM4_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" newline bitfld.long 0x0 17.--18. "DOM4_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM4_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 15. "DOM3_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 13.--14. "DOM3_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 12. "DOM3_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" newline bitfld.long 0x0 11. "DOM2_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 9.--10. "DOM2_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM2_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 7. "DOM1_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 5.--6. "DOM1_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" newline bitfld.long 0x0 4. "DOM1_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 3. "DOM0_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 1.--2. "DOM0_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM0_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" repeat.end repeat 16. (list 0x30 0x31 0x32 0x33 0x34 0x35 0x36 0x37 0x38 0x39 0x3A 0x3B 0x3C 0x3D 0x3E 0x3F )(list 0x9C0 0x9F4 0xA28 0xA5C 0xA90 0xAC4 0xAF8 0xB2C 0xB60 0xB94 0xBC8 0xBFC 0xC30 0xC64 0xC98 0xCCC ) group.long ($2+0x2400)++0x3 line.long 0x0 "DOM_PER0_$1,Domain Permission Control. It can be only configured by resource manager and domain owner." bitfld.long 0x0 31. "DOM7_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 29.--30. "DOM7_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 28. "DOM7_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 27. "DOM6_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 25.--26. "DOM6_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" newline bitfld.long 0x0 24. "DOM6_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 23. "DOM5_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 21.--22. "DOM5_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 20. "DOM5_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 19. "DOM4_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" newline bitfld.long 0x0 17.--18. "DOM4_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM4_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 15. "DOM3_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 13.--14. "DOM3_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 12. "DOM3_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" newline bitfld.long 0x0 11. "DOM2_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 9.--10. "DOM2_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM2_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 7. "DOM1_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 5.--6. "DOM1_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" newline bitfld.long 0x0 4. "DOM1_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 3. "DOM0_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 1.--2. "DOM0_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM0_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" repeat.end repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x34 0x68 0x9C 0xD0 0x104 0x138 0x16C 0x1A0 0x1D4 0x208 0x23C 0x270 0x2A4 0x2D8 0x30C ) group.long ($2+0x2404)++0x3 line.long 0x0 "DOM_PER1_$1,Domain Permission Control. It can be only configured by resource manager and domain owner." bitfld.long 0x0 31. "DOM15_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 29.--30. "DOM15_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 28. "DOM15_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 27. "DOM14_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 25.--26. "DOM14_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" newline bitfld.long 0x0 24. "DOM14_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 23. "DOM13_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 21.--22. "DOM13_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 20. "DOM13_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 19. "DOM12_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" newline bitfld.long 0x0 17.--18. "DOM12_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM12_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 15. "DOM11_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 13.--14. "DOM11_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 12. "DOM11_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" newline bitfld.long 0x0 11. "DOM10_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 9.--10. "DOM10_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM10_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 7. "DOM9_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 5.--6. "DOM9_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" newline bitfld.long 0x0 4. "DOM9_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 3. "DOM8_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 1.--2. "DOM8_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM8_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" repeat.end repeat 16. (list 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1A 0x1B 0x1C 0x1D 0x1E 0x1F )(list 0x340 0x374 0x3A8 0x3DC 0x410 0x444 0x478 0x4AC 0x4E0 0x514 0x548 0x57C 0x5B0 0x5E4 0x618 0x64C ) group.long ($2+0x2404)++0x3 line.long 0x0 "DOM_PER1_$1,Domain Permission Control. It can be only configured by resource manager and domain owner." bitfld.long 0x0 31. "DOM15_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 29.--30. "DOM15_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 28. "DOM15_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 27. "DOM14_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 25.--26. "DOM14_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" newline bitfld.long 0x0 24. "DOM14_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 23. "DOM13_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 21.--22. "DOM13_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 20. "DOM13_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 19. "DOM12_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" newline bitfld.long 0x0 17.--18. "DOM12_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM12_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 15. "DOM11_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 13.--14. "DOM11_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 12. "DOM11_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" newline bitfld.long 0x0 11. "DOM10_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 9.--10. "DOM10_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM10_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 7. "DOM9_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 5.--6. "DOM9_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" newline bitfld.long 0x0 4. "DOM9_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 3. "DOM8_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 1.--2. "DOM8_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM8_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" repeat.end repeat 16. (list 0x20 0x21 0x22 0x23 0x24 0x25 0x26 0x27 0x28 0x29 0x2A 0x2B 0x2C 0x2D 0x2E 0x2F )(list 0x680 0x6B4 0x6E8 0x71C 0x750 0x784 0x7B8 0x7EC 0x820 0x854 0x888 0x8BC 0x8F0 0x924 0x958 0x98C ) group.long ($2+0x2404)++0x3 line.long 0x0 "DOM_PER1_$1,Domain Permission Control. It can be only configured by resource manager and domain owner." bitfld.long 0x0 31. "DOM15_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 29.--30. "DOM15_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 28. "DOM15_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 27. "DOM14_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 25.--26. "DOM14_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" newline bitfld.long 0x0 24. "DOM14_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 23. "DOM13_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 21.--22. "DOM13_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 20. "DOM13_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 19. "DOM12_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" newline bitfld.long 0x0 17.--18. "DOM12_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM12_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 15. "DOM11_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 13.--14. "DOM11_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 12. "DOM11_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" newline bitfld.long 0x0 11. "DOM10_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 9.--10. "DOM10_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM10_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 7. "DOM9_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 5.--6. "DOM9_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" newline bitfld.long 0x0 4. "DOM9_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 3. "DOM8_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 1.--2. "DOM8_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM8_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" repeat.end repeat 16. (list 0x30 0x31 0x32 0x33 0x34 0x35 0x36 0x37 0x38 0x39 0x3A 0x3B 0x3C 0x3D 0x3E 0x3F )(list 0x9C0 0x9F4 0xA28 0xA5C 0xA90 0xAC4 0xAF8 0xB2C 0xB60 0xB94 0xBC8 0xBFC 0xC30 0xC64 0xC98 0xCCC ) group.long ($2+0x2404)++0x3 line.long 0x0 "DOM_PER1_$1,Domain Permission Control. It can be only configured by resource manager and domain owner." bitfld.long 0x0 31. "DOM15_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 29.--30. "DOM15_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 28. "DOM15_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 27. "DOM14_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 25.--26. "DOM14_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" newline bitfld.long 0x0 24. "DOM14_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 23. "DOM13_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 21.--22. "DOM13_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 20. "DOM13_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 19. "DOM12_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" newline bitfld.long 0x0 17.--18. "DOM12_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM12_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 15. "DOM11_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 13.--14. "DOM11_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 12. "DOM11_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" newline bitfld.long 0x0 11. "DOM10_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 9.--10. "DOM10_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM10_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 7. "DOM9_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 5.--6. "DOM9_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" newline bitfld.long 0x0 4. "DOM9_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 3. "DOM8_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 1.--2. "DOM8_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM8_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" repeat.end repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x34 0x68 0x9C 0xD0 0x104 0x138 0x16C 0x1A0 0x1D4 0x208 0x23C 0x270 0x2A4 0x2D8 0x30C ) group.long ($2+0x2408)++0x3 line.long 0x0 "SEC_PER0_$1,This register is only used for resource manager to control secure access permission." bitfld.long 0x0 31. "DOM3_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM3_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM3_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM3_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM2_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM2_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM2_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM2_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM1_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM1_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM1_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM1_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM0_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM0_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM0_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM0_SEC_EN,Domain secure permission control enable" "0,1" repeat.end repeat 16. (list 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1A 0x1B 0x1C 0x1D 0x1E 0x1F )(list 0x340 0x374 0x3A8 0x3DC 0x410 0x444 0x478 0x4AC 0x4E0 0x514 0x548 0x57C 0x5B0 0x5E4 0x618 0x64C ) group.long ($2+0x2408)++0x3 line.long 0x0 "SEC_PER0_$1,This register is only used for resource manager to control secure access permission." bitfld.long 0x0 31. "DOM3_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM3_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM3_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM3_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM2_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM2_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM2_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM2_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM1_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM1_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM1_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM1_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM0_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM0_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM0_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM0_SEC_EN,Domain secure permission control enable" "0,1" repeat.end repeat 16. (list 0x20 0x21 0x22 0x23 0x24 0x25 0x26 0x27 0x28 0x29 0x2A 0x2B 0x2C 0x2D 0x2E 0x2F )(list 0x680 0x6B4 0x6E8 0x71C 0x750 0x784 0x7B8 0x7EC 0x820 0x854 0x888 0x8BC 0x8F0 0x924 0x958 0x98C ) group.long ($2+0x2408)++0x3 line.long 0x0 "SEC_PER0_$1,This register is only used for resource manager to control secure access permission." bitfld.long 0x0 31. "DOM3_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM3_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM3_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM3_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM2_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM2_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM2_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM2_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM1_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM1_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM1_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM1_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM0_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM0_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM0_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM0_SEC_EN,Domain secure permission control enable" "0,1" repeat.end repeat 16. (list 0x30 0x31 0x32 0x33 0x34 0x35 0x36 0x37 0x38 0x39 0x3A 0x3B 0x3C 0x3D 0x3E 0x3F )(list 0x9C0 0x9F4 0xA28 0xA5C 0xA90 0xAC4 0xAF8 0xB2C 0xB60 0xB94 0xBC8 0xBFC 0xC30 0xC64 0xC98 0xCCC ) group.long ($2+0x2408)++0x3 line.long 0x0 "SEC_PER0_$1,This register is only used for resource manager to control secure access permission." bitfld.long 0x0 31. "DOM3_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM3_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM3_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM3_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM2_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM2_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM2_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM2_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM1_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM1_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM1_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM1_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM0_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM0_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM0_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM0_SEC_EN,Domain secure permission control enable" "0,1" repeat.end repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x34 0x68 0x9C 0xD0 0x104 0x138 0x16C 0x1A0 0x1D4 0x208 0x23C 0x270 0x2A4 0x2D8 0x30C ) group.long ($2+0x240C)++0x3 line.long 0x0 "SEC_PER1_$1,This register is only used for resource manager to control secure access permission." bitfld.long 0x0 31. "DOM7_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM7_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM7_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM7_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM6_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM6_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM6_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM6_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM5_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM5_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM5_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM5_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM4_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM4_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM4_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM4_SEC_EN,Domain secure permission control enable" "0,1" repeat.end repeat 16. (list 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1A 0x1B 0x1C 0x1D 0x1E 0x1F )(list 0x340 0x374 0x3A8 0x3DC 0x410 0x444 0x478 0x4AC 0x4E0 0x514 0x548 0x57C 0x5B0 0x5E4 0x618 0x64C ) group.long ($2+0x240C)++0x3 line.long 0x0 "SEC_PER1_$1,This register is only used for resource manager to control secure access permission." bitfld.long 0x0 31. "DOM7_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM7_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM7_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM7_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM6_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM6_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM6_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM6_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM5_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM5_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM5_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM5_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM4_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM4_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM4_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM4_SEC_EN,Domain secure permission control enable" "0,1" repeat.end repeat 16. (list 0x20 0x21 0x22 0x23 0x24 0x25 0x26 0x27 0x28 0x29 0x2A 0x2B 0x2C 0x2D 0x2E 0x2F )(list 0x680 0x6B4 0x6E8 0x71C 0x750 0x784 0x7B8 0x7EC 0x820 0x854 0x888 0x8BC 0x8F0 0x924 0x958 0x98C ) group.long ($2+0x240C)++0x3 line.long 0x0 "SEC_PER1_$1,This register is only used for resource manager to control secure access permission." bitfld.long 0x0 31. "DOM7_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM7_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM7_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM7_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM6_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM6_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM6_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM6_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM5_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM5_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM5_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM5_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM4_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM4_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM4_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM4_SEC_EN,Domain secure permission control enable" "0,1" repeat.end repeat 16. (list 0x30 0x31 0x32 0x33 0x34 0x35 0x36 0x37 0x38 0x39 0x3A 0x3B 0x3C 0x3D 0x3E 0x3F )(list 0x9C0 0x9F4 0xA28 0xA5C 0xA90 0xAC4 0xAF8 0xB2C 0xB60 0xB94 0xBC8 0xBFC 0xC30 0xC64 0xC98 0xCCC ) group.long ($2+0x240C)++0x3 line.long 0x0 "SEC_PER1_$1,This register is only used for resource manager to control secure access permission." bitfld.long 0x0 31. "DOM7_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM7_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM7_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM7_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM6_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM6_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM6_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM6_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM5_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM5_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM5_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM5_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM4_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM4_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM4_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM4_SEC_EN,Domain secure permission control enable" "0,1" repeat.end repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x34 0x68 0x9C 0xD0 0x104 0x138 0x16C 0x1A0 0x1D4 0x208 0x23C 0x270 0x2A4 0x2D8 0x30C ) group.long ($2+0x2410)++0x3 line.long 0x0 "SEC_PER2_$1,This register is only used for resource manager to control secure access permission." bitfld.long 0x0 31. "DOM11_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM11_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM11_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM11_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM10_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM10_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM10_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM10_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM9_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM9_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM9_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM9_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM8_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM8_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM8_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM8_SEC_EN,Domain secure permission control enable" "0,1" repeat.end repeat 16. (list 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1A 0x1B 0x1C 0x1D 0x1E 0x1F )(list 0x340 0x374 0x3A8 0x3DC 0x410 0x444 0x478 0x4AC 0x4E0 0x514 0x548 0x57C 0x5B0 0x5E4 0x618 0x64C ) group.long ($2+0x2410)++0x3 line.long 0x0 "SEC_PER2_$1,This register is only used for resource manager to control secure access permission." bitfld.long 0x0 31. "DOM11_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM11_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM11_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM11_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM10_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM10_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM10_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM10_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM9_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM9_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM9_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM9_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM8_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM8_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM8_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM8_SEC_EN,Domain secure permission control enable" "0,1" repeat.end repeat 16. (list 0x20 0x21 0x22 0x23 0x24 0x25 0x26 0x27 0x28 0x29 0x2A 0x2B 0x2C 0x2D 0x2E 0x2F )(list 0x680 0x6B4 0x6E8 0x71C 0x750 0x784 0x7B8 0x7EC 0x820 0x854 0x888 0x8BC 0x8F0 0x924 0x958 0x98C ) group.long ($2+0x2410)++0x3 line.long 0x0 "SEC_PER2_$1,This register is only used for resource manager to control secure access permission." bitfld.long 0x0 31. "DOM11_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM11_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM11_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM11_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM10_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM10_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM10_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM10_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM9_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM9_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM9_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM9_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM8_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM8_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM8_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM8_SEC_EN,Domain secure permission control enable" "0,1" repeat.end repeat 16. (list 0x30 0x31 0x32 0x33 0x34 0x35 0x36 0x37 0x38 0x39 0x3A 0x3B 0x3C 0x3D 0x3E 0x3F )(list 0x9C0 0x9F4 0xA28 0xA5C 0xA90 0xAC4 0xAF8 0xB2C 0xB60 0xB94 0xBC8 0xBFC 0xC30 0xC64 0xC98 0xCCC ) group.long ($2+0x2410)++0x3 line.long 0x0 "SEC_PER2_$1,This register is only used for resource manager to control secure access permission." bitfld.long 0x0 31. "DOM11_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM11_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM11_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM11_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM10_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM10_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM10_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM10_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM9_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM9_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM9_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM9_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM8_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM8_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM8_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM8_SEC_EN,Domain secure permission control enable" "0,1" repeat.end repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x34 0x68 0x9C 0xD0 0x104 0x138 0x16C 0x1A0 0x1D4 0x208 0x23C 0x270 0x2A4 0x2D8 0x30C ) group.long ($2+0x2414)++0x3 line.long 0x0 "SEC_PER3_$1,This register is only used for resource manager to control secure access permission." bitfld.long 0x0 31. "DOM15_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM15_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM15_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM15_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM14_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM14_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM14_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM14_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM13_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM13_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM13_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM13_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM12_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM12_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM12_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM12_SEC_EN,Domain secure permission control enable" "0,1" repeat.end repeat 16. (list 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1A 0x1B 0x1C 0x1D 0x1E 0x1F )(list 0x340 0x374 0x3A8 0x3DC 0x410 0x444 0x478 0x4AC 0x4E0 0x514 0x548 0x57C 0x5B0 0x5E4 0x618 0x64C ) group.long ($2+0x2414)++0x3 line.long 0x0 "SEC_PER3_$1,This register is only used for resource manager to control secure access permission." bitfld.long 0x0 31. "DOM15_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM15_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM15_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM15_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM14_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM14_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM14_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM14_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM13_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM13_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM13_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM13_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM12_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM12_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM12_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM12_SEC_EN,Domain secure permission control enable" "0,1" repeat.end repeat 16. (list 0x20 0x21 0x22 0x23 0x24 0x25 0x26 0x27 0x28 0x29 0x2A 0x2B 0x2C 0x2D 0x2E 0x2F )(list 0x680 0x6B4 0x6E8 0x71C 0x750 0x784 0x7B8 0x7EC 0x820 0x854 0x888 0x8BC 0x8F0 0x924 0x958 0x98C ) group.long ($2+0x2414)++0x3 line.long 0x0 "SEC_PER3_$1,This register is only used for resource manager to control secure access permission." bitfld.long 0x0 31. "DOM15_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM15_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM15_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM15_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM14_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM14_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM14_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM14_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM13_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM13_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM13_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM13_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM12_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM12_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM12_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM12_SEC_EN,Domain secure permission control enable" "0,1" repeat.end repeat 16. (list 0x30 0x31 0x32 0x33 0x34 0x35 0x36 0x37 0x38 0x39 0x3A 0x3B 0x3C 0x3D 0x3E 0x3F )(list 0x9C0 0x9F4 0xA28 0xA5C 0xA90 0xAC4 0xAF8 0xB2C 0xB60 0xB94 0xBC8 0xBFC 0xC30 0xC64 0xC98 0xCCC ) group.long ($2+0x2414)++0x3 line.long 0x0 "SEC_PER3_$1,This register is only used for resource manager to control secure access permission." bitfld.long 0x0 31. "DOM15_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM15_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM15_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM15_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM14_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM14_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM14_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM14_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM13_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM13_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM13_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM13_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM12_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM12_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM12_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM12_SEC_EN,Domain secure permission control enable" "0,1" repeat.end repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x34 0x68 0x9C 0xD0 0x104 0x138 0x16C 0x1A0 0x1D4 0x208 0x23C 0x270 0x2A4 0x2D8 0x30C ) group.long ($2+0x2418)++0x3 line.long 0x0 "PRI_PER0_$1,This register is only used for resource manager to control privileged access permission." bitfld.long 0x0 31. "DOM3_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM3_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM3_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM3_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM2_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM2_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM2_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM2_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM1_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM1_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM1_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM1_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM0_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM0_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM0_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM0_PRI_EN,Domain privileged permission control enable" "0,1" repeat.end repeat 16. (list 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1A 0x1B 0x1C 0x1D 0x1E 0x1F )(list 0x340 0x374 0x3A8 0x3DC 0x410 0x444 0x478 0x4AC 0x4E0 0x514 0x548 0x57C 0x5B0 0x5E4 0x618 0x64C ) group.long ($2+0x2418)++0x3 line.long 0x0 "PRI_PER0_$1,This register is only used for resource manager to control privileged access permission." bitfld.long 0x0 31. "DOM3_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM3_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM3_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM3_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM2_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM2_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM2_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM2_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM1_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM1_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM1_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM1_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM0_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM0_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM0_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM0_PRI_EN,Domain privileged permission control enable" "0,1" repeat.end repeat 16. (list 0x20 0x21 0x22 0x23 0x24 0x25 0x26 0x27 0x28 0x29 0x2A 0x2B 0x2C 0x2D 0x2E 0x2F )(list 0x680 0x6B4 0x6E8 0x71C 0x750 0x784 0x7B8 0x7EC 0x820 0x854 0x888 0x8BC 0x8F0 0x924 0x958 0x98C ) group.long ($2+0x2418)++0x3 line.long 0x0 "PRI_PER0_$1,This register is only used for resource manager to control privileged access permission." bitfld.long 0x0 31. "DOM3_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM3_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM3_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM3_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM2_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM2_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM2_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM2_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM1_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM1_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM1_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM1_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM0_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM0_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM0_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM0_PRI_EN,Domain privileged permission control enable" "0,1" repeat.end repeat 16. (list 0x30 0x31 0x32 0x33 0x34 0x35 0x36 0x37 0x38 0x39 0x3A 0x3B 0x3C 0x3D 0x3E 0x3F )(list 0x9C0 0x9F4 0xA28 0xA5C 0xA90 0xAC4 0xAF8 0xB2C 0xB60 0xB94 0xBC8 0xBFC 0xC30 0xC64 0xC98 0xCCC ) group.long ($2+0x2418)++0x3 line.long 0x0 "PRI_PER0_$1,This register is only used for resource manager to control privileged access permission." bitfld.long 0x0 31. "DOM3_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM3_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM3_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM3_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM2_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM2_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM2_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM2_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM1_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM1_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM1_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM1_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM0_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM0_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM0_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM0_PRI_EN,Domain privileged permission control enable" "0,1" repeat.end repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x34 0x68 0x9C 0xD0 0x104 0x138 0x16C 0x1A0 0x1D4 0x208 0x23C 0x270 0x2A4 0x2D8 0x30C ) group.long ($2+0x241C)++0x3 line.long 0x0 "PRI_PER1_$1,This register is only used for resource manager to control privileged access permission." bitfld.long 0x0 31. "DOM7_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM7_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM7_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM7_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM6_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM6_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM6_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM6_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM5_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM5_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM5_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM5_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM4_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM4_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM4_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM4_PRI_EN,Domain privileged permission control enable" "0,1" repeat.end repeat 16. (list 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1A 0x1B 0x1C 0x1D 0x1E 0x1F )(list 0x340 0x374 0x3A8 0x3DC 0x410 0x444 0x478 0x4AC 0x4E0 0x514 0x548 0x57C 0x5B0 0x5E4 0x618 0x64C ) group.long ($2+0x241C)++0x3 line.long 0x0 "PRI_PER1_$1,This register is only used for resource manager to control privileged access permission." bitfld.long 0x0 31. "DOM7_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM7_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM7_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM7_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM6_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM6_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM6_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM6_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM5_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM5_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM5_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM5_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM4_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM4_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM4_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM4_PRI_EN,Domain privileged permission control enable" "0,1" repeat.end repeat 16. (list 0x20 0x21 0x22 0x23 0x24 0x25 0x26 0x27 0x28 0x29 0x2A 0x2B 0x2C 0x2D 0x2E 0x2F )(list 0x680 0x6B4 0x6E8 0x71C 0x750 0x784 0x7B8 0x7EC 0x820 0x854 0x888 0x8BC 0x8F0 0x924 0x958 0x98C ) group.long ($2+0x241C)++0x3 line.long 0x0 "PRI_PER1_$1,This register is only used for resource manager to control privileged access permission." bitfld.long 0x0 31. "DOM7_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM7_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM7_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM7_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM6_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM6_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM6_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM6_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM5_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM5_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM5_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM5_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM4_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM4_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM4_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM4_PRI_EN,Domain privileged permission control enable" "0,1" repeat.end repeat 16. (list 0x30 0x31 0x32 0x33 0x34 0x35 0x36 0x37 0x38 0x39 0x3A 0x3B 0x3C 0x3D 0x3E 0x3F )(list 0x9C0 0x9F4 0xA28 0xA5C 0xA90 0xAC4 0xAF8 0xB2C 0xB60 0xB94 0xBC8 0xBFC 0xC30 0xC64 0xC98 0xCCC ) group.long ($2+0x241C)++0x3 line.long 0x0 "PRI_PER1_$1,This register is only used for resource manager to control privileged access permission." bitfld.long 0x0 31. "DOM7_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM7_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM7_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM7_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM6_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM6_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM6_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM6_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM5_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM5_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM5_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM5_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM4_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM4_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM4_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM4_PRI_EN,Domain privileged permission control enable" "0,1" repeat.end repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x34 0x68 0x9C 0xD0 0x104 0x138 0x16C 0x1A0 0x1D4 0x208 0x23C 0x270 0x2A4 0x2D8 0x30C ) group.long ($2+0x2420)++0x3 line.long 0x0 "PRI_PER2_$1,This register is only used for resource manager to control privileged access permission." bitfld.long 0x0 31. "DOM11_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM11_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM11_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM11_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM10_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM10_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM10_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM10_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM9_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM9_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM9_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM9_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM8_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM8_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM8_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM8_PRI_EN,Domain privileged permission control enable" "0,1" repeat.end repeat 16. (list 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1A 0x1B 0x1C 0x1D 0x1E 0x1F )(list 0x340 0x374 0x3A8 0x3DC 0x410 0x444 0x478 0x4AC 0x4E0 0x514 0x548 0x57C 0x5B0 0x5E4 0x618 0x64C ) group.long ($2+0x2420)++0x3 line.long 0x0 "PRI_PER2_$1,This register is only used for resource manager to control privileged access permission." bitfld.long 0x0 31. "DOM11_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM11_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM11_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM11_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM10_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM10_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM10_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM10_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM9_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM9_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM9_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM9_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM8_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM8_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM8_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM8_PRI_EN,Domain privileged permission control enable" "0,1" repeat.end repeat 16. (list 0x20 0x21 0x22 0x23 0x24 0x25 0x26 0x27 0x28 0x29 0x2A 0x2B 0x2C 0x2D 0x2E 0x2F )(list 0x680 0x6B4 0x6E8 0x71C 0x750 0x784 0x7B8 0x7EC 0x820 0x854 0x888 0x8BC 0x8F0 0x924 0x958 0x98C ) group.long ($2+0x2420)++0x3 line.long 0x0 "PRI_PER2_$1,This register is only used for resource manager to control privileged access permission." bitfld.long 0x0 31. "DOM11_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM11_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM11_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM11_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM10_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM10_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM10_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM10_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM9_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM9_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM9_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM9_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM8_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM8_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM8_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM8_PRI_EN,Domain privileged permission control enable" "0,1" repeat.end repeat 16. (list 0x30 0x31 0x32 0x33 0x34 0x35 0x36 0x37 0x38 0x39 0x3A 0x3B 0x3C 0x3D 0x3E 0x3F )(list 0x9C0 0x9F4 0xA28 0xA5C 0xA90 0xAC4 0xAF8 0xB2C 0xB60 0xB94 0xBC8 0xBFC 0xC30 0xC64 0xC98 0xCCC ) group.long ($2+0x2420)++0x3 line.long 0x0 "PRI_PER2_$1,This register is only used for resource manager to control privileged access permission." bitfld.long 0x0 31. "DOM11_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM11_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM11_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM11_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM10_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM10_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM10_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM10_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM9_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM9_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM9_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM9_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM8_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM8_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM8_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM8_PRI_EN,Domain privileged permission control enable" "0,1" repeat.end repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x34 0x68 0x9C 0xD0 0x104 0x138 0x16C 0x1A0 0x1D4 0x208 0x23C 0x270 0x2A4 0x2D8 0x30C ) group.long ($2+0x2424)++0x3 line.long 0x0 "PRI_PER3_$1,This register is only used for resource manager to control privileged access permission." bitfld.long 0x0 31. "DOM15_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM15_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM15_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM15_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM14_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM14_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM14_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM14_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM13_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM13_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM13_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM13_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM12_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM12_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM12_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM12_PRI_EN,Domain privileged permission control enable" "0,1" repeat.end repeat 16. (list 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1A 0x1B 0x1C 0x1D 0x1E 0x1F )(list 0x340 0x374 0x3A8 0x3DC 0x410 0x444 0x478 0x4AC 0x4E0 0x514 0x548 0x57C 0x5B0 0x5E4 0x618 0x64C ) group.long ($2+0x2424)++0x3 line.long 0x0 "PRI_PER3_$1,This register is only used for resource manager to control privileged access permission." bitfld.long 0x0 31. "DOM15_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM15_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM15_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM15_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM14_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM14_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM14_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM14_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM13_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM13_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM13_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM13_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM12_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM12_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM12_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM12_PRI_EN,Domain privileged permission control enable" "0,1" repeat.end repeat 16. (list 0x20 0x21 0x22 0x23 0x24 0x25 0x26 0x27 0x28 0x29 0x2A 0x2B 0x2C 0x2D 0x2E 0x2F )(list 0x680 0x6B4 0x6E8 0x71C 0x750 0x784 0x7B8 0x7EC 0x820 0x854 0x888 0x8BC 0x8F0 0x924 0x958 0x98C ) group.long ($2+0x2424)++0x3 line.long 0x0 "PRI_PER3_$1,This register is only used for resource manager to control privileged access permission." bitfld.long 0x0 31. "DOM15_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM15_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM15_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM15_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM14_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM14_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM14_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM14_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM13_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM13_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM13_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM13_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM12_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM12_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM12_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM12_PRI_EN,Domain privileged permission control enable" "0,1" repeat.end repeat 16. (list 0x30 0x31 0x32 0x33 0x34 0x35 0x36 0x37 0x38 0x39 0x3A 0x3B 0x3C 0x3D 0x3E 0x3F )(list 0x9C0 0x9F4 0xA28 0xA5C 0xA90 0xAC4 0xAF8 0xB2C 0xB60 0xB94 0xBC8 0xBFC 0xC30 0xC64 0xC98 0xCCC ) group.long ($2+0x2424)++0x3 line.long 0x0 "PRI_PER3_$1,This register is only used for resource manager to control privileged access permission." bitfld.long 0x0 31. "DOM15_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM15_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM15_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM15_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM14_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM14_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM14_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM14_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM13_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM13_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM13_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM13_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM12_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM12_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM12_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM12_PRI_EN,Domain privileged permission control enable" "0,1" repeat.end repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x34 0x68 0x9C 0xD0 0x104 0x138 0x16C 0x1A0 0x1D4 0x208 0x23C 0x270 0x2A4 0x2D8 0x30C ) group.long ($2+0x2428)++0x3 line.long 0x0 "DOM_SEC_PER_$1,This register is only used for domain master to control secure access permission. When the domain master write this register. it only changes the secure permission for itself. When the domain master read this register. it gets permission.." bitfld.long 0x0 7. "DOM_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" newline bitfld.long 0x0 0. "DOM_SEC_EN,Domain secure permission control enable" "0,1" repeat.end repeat 16. (list 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1A 0x1B 0x1C 0x1D 0x1E 0x1F )(list 0x340 0x374 0x3A8 0x3DC 0x410 0x444 0x478 0x4AC 0x4E0 0x514 0x548 0x57C 0x5B0 0x5E4 0x618 0x64C ) group.long ($2+0x2428)++0x3 line.long 0x0 "DOM_SEC_PER_$1,This register is only used for domain master to control secure access permission. When the domain master write this register. it only changes the secure permission for itself. When the domain master read this register. it gets permission.." bitfld.long 0x0 7. "DOM_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" newline bitfld.long 0x0 0. "DOM_SEC_EN,Domain secure permission control enable" "0,1" repeat.end repeat 16. (list 0x20 0x21 0x22 0x23 0x24 0x25 0x26 0x27 0x28 0x29 0x2A 0x2B 0x2C 0x2D 0x2E 0x2F )(list 0x680 0x6B4 0x6E8 0x71C 0x750 0x784 0x7B8 0x7EC 0x820 0x854 0x888 0x8BC 0x8F0 0x924 0x958 0x98C ) group.long ($2+0x2428)++0x3 line.long 0x0 "DOM_SEC_PER_$1,This register is only used for domain master to control secure access permission. When the domain master write this register. it only changes the secure permission for itself. When the domain master read this register. it gets permission.." bitfld.long 0x0 7. "DOM_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" newline bitfld.long 0x0 0. "DOM_SEC_EN,Domain secure permission control enable" "0,1" repeat.end repeat 16. (list 0x30 0x31 0x32 0x33 0x34 0x35 0x36 0x37 0x38 0x39 0x3A 0x3B 0x3C 0x3D 0x3E 0x3F )(list 0x9C0 0x9F4 0xA28 0xA5C 0xA90 0xAC4 0xAF8 0xB2C 0xB60 0xB94 0xBC8 0xBFC 0xC30 0xC64 0xC98 0xCCC ) group.long ($2+0x2428)++0x3 line.long 0x0 "DOM_SEC_PER_$1,This register is only used for domain master to control secure access permission. When the domain master write this register. it only changes the secure permission for itself. When the domain master read this register. it gets permission.." bitfld.long 0x0 7. "DOM_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" newline bitfld.long 0x0 0. "DOM_SEC_EN,Domain secure permission control enable" "0,1" repeat.end repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x34 0x68 0x9C 0xD0 0x104 0x138 0x16C 0x1A0 0x1D4 0x208 0x23C 0x270 0x2A4 0x2D8 0x30C ) group.long ($2+0x242C)++0x3 line.long 0x0 "DOM_PRI_PER_$1,This register is only used for domain master to control secure access permission. When the domain master write this register. it only changes the secure permission for itself. When the domain master read this register. it gets permission.." bitfld.long 0x0 7. "DOM_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" newline bitfld.long 0x0 0. "DOM_PRI_EN,Domain privileged permission control enable" "0,1" repeat.end repeat 16. (list 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1A 0x1B 0x1C 0x1D 0x1E 0x1F )(list 0x340 0x374 0x3A8 0x3DC 0x410 0x444 0x478 0x4AC 0x4E0 0x514 0x548 0x57C 0x5B0 0x5E4 0x618 0x64C ) group.long ($2+0x242C)++0x3 line.long 0x0 "DOM_PRI_PER_$1,This register is only used for domain master to control secure access permission. When the domain master write this register. it only changes the secure permission for itself. When the domain master read this register. it gets permission.." bitfld.long 0x0 7. "DOM_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" newline bitfld.long 0x0 0. "DOM_PRI_EN,Domain privileged permission control enable" "0,1" repeat.end repeat 16. (list 0x20 0x21 0x22 0x23 0x24 0x25 0x26 0x27 0x28 0x29 0x2A 0x2B 0x2C 0x2D 0x2E 0x2F )(list 0x680 0x6B4 0x6E8 0x71C 0x750 0x784 0x7B8 0x7EC 0x820 0x854 0x888 0x8BC 0x8F0 0x924 0x958 0x98C ) group.long ($2+0x242C)++0x3 line.long 0x0 "DOM_PRI_PER_$1,This register is only used for domain master to control secure access permission. When the domain master write this register. it only changes the secure permission for itself. When the domain master read this register. it gets permission.." bitfld.long 0x0 7. "DOM_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" newline bitfld.long 0x0 0. "DOM_PRI_EN,Domain privileged permission control enable" "0,1" repeat.end repeat 16. (list 0x30 0x31 0x32 0x33 0x34 0x35 0x36 0x37 0x38 0x39 0x3A 0x3B 0x3C 0x3D 0x3E 0x3F )(list 0x9C0 0x9F4 0xA28 0xA5C 0xA90 0xAC4 0xAF8 0xB2C 0xB60 0xB94 0xBC8 0xBFC 0xC30 0xC64 0xC98 0xCCC ) group.long ($2+0x242C)++0x3 line.long 0x0 "DOM_PRI_PER_$1,This register is only used for domain master to control secure access permission. When the domain master write this register. it only changes the secure permission for itself. When the domain master read this register. it gets permission.." bitfld.long 0x0 7. "DOM_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" newline bitfld.long 0x0 0. "DOM_PRI_EN,Domain privileged permission control enable" "0,1" repeat.end repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x34 0x68 0x9C 0xD0 0x104 0x138 0x16C 0x1A0 0x1D4 0x208 0x23C 0x270 0x2A4 0x2D8 0x30C ) group.long ($2+0x2430)++0x3 line.long 0x0 "DOM_ASSIGN_$1,Use to assign domain for accessing DOM_SEC_PER and DOM_PRI_PER register. Only resource manager. group manager and domain owner can access this register. For write. group manager must write its owen domain ID. otherwise write accessing will.." hexmask.long.byte 0x0 0.--3. 1. "DID,accessing DOM_SEC_PER and DOM_PRI_PER register" repeat.end repeat 16. (list 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1A 0x1B 0x1C 0x1D 0x1E 0x1F )(list 0x340 0x374 0x3A8 0x3DC 0x410 0x444 0x478 0x4AC 0x4E0 0x514 0x548 0x57C 0x5B0 0x5E4 0x618 0x64C ) group.long ($2+0x2430)++0x3 line.long 0x0 "DOM_ASSIGN_$1,Use to assign domain for accessing DOM_SEC_PER and DOM_PRI_PER register. Only resource manager. group manager and domain owner can access this register. For write. group manager must write its owen domain ID. otherwise write accessing will.." hexmask.long.byte 0x0 0.--3. 1. "DID,accessing DOM_SEC_PER and DOM_PRI_PER register" repeat.end repeat 16. (list 0x20 0x21 0x22 0x23 0x24 0x25 0x26 0x27 0x28 0x29 0x2A 0x2B 0x2C 0x2D 0x2E 0x2F )(list 0x680 0x6B4 0x6E8 0x71C 0x750 0x784 0x7B8 0x7EC 0x820 0x854 0x888 0x8BC 0x8F0 0x924 0x958 0x98C ) group.long ($2+0x2430)++0x3 line.long 0x0 "DOM_ASSIGN_$1,Use to assign domain for accessing DOM_SEC_PER and DOM_PRI_PER register. Only resource manager. group manager and domain owner can access this register. For write. group manager must write its owen domain ID. otherwise write accessing will.." hexmask.long.byte 0x0 0.--3. 1. "DID,accessing DOM_SEC_PER and DOM_PRI_PER register" repeat.end repeat 16. (list 0x30 0x31 0x32 0x33 0x34 0x35 0x36 0x37 0x38 0x39 0x3A 0x3B 0x3C 0x3D 0x3E 0x3F )(list 0x9C0 0x9F4 0xA28 0xA5C 0xA90 0xAC4 0xAF8 0xB2C 0xB60 0xB94 0xBC8 0xBFC 0xC30 0xC64 0xC98 0xCCC ) group.long ($2+0x2430)++0x3 line.long 0x0 "DOM_ASSIGN_$1,Use to assign domain for accessing DOM_SEC_PER and DOM_PRI_PER register. Only resource manager. group manager and domain owner can access this register. For write. group manager must write its owen domain ID. otherwise write accessing will.." hexmask.long.byte 0x0 0.--3. 1. "DID,accessing DOM_SEC_PER and DOM_PRI_PER register" repeat.end repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x38 0x70 0xA8 0xE0 0x118 0x150 0x188 0x1C0 0x1F8 0x230 0x268 0x2A0 0x2D8 0x310 0x348 ) group.long ($2+0x3100)++0x3 line.long 0x0 "RGN_DOM_$1,Assign domain for peripheral. It can be only configured by resource and group manager" bitfld.long 0x0 31. "LOCK,When this bit is set lock write for all the bits in the register." "0,1" bitfld.long 0x0 4. "SET,Set together with DID would change permission of this resource to following setting: 1) Domain access control enabled. 2) Read/Write allowed for the domain owner. 3) Read/Write not allowed for all the other domains. If this bit is not set only DID.." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Assign domain for peripheral" repeat.end repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x38 0x70 0xA8 0xE0 0x118 0x150 0x188 0x1C0 0x1F8 0x230 0x268 0x2A0 0x2D8 0x310 0x348 ) group.long ($2+0x3104)++0x3 line.long 0x0 "RGN_DOM_PER0_$1,Domain Permission Control. It can be only configured by resource manager and domain owner." bitfld.long 0x0 31. "DOM7_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 29.--30. "DOM7_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 28. "DOM7_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 27. "DOM6_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 25.--26. "DOM6_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" newline bitfld.long 0x0 24. "DOM6_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 23. "DOM5_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 21.--22. "DOM5_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 20. "DOM5_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 19. "DOM4_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" newline bitfld.long 0x0 17.--18. "DOM4_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM4_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 15. "DOM3_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 13.--14. "DOM3_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 12. "DOM3_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" newline bitfld.long 0x0 11. "DOM2_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 9.--10. "DOM2_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM2_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 7. "DOM1_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 5.--6. "DOM1_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" newline bitfld.long 0x0 4. "DOM1_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 3. "DOM0_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 1.--2. "DOM0_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM0_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" repeat.end repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x38 0x70 0xA8 0xE0 0x118 0x150 0x188 0x1C0 0x1F8 0x230 0x268 0x2A0 0x2D8 0x310 0x348 ) group.long ($2+0x3108)++0x3 line.long 0x0 "RGN_DOM_PER1_$1,Domain Permission Control. It can be only configured by resource manager and domain owner." bitfld.long 0x0 31. "DOM15_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 29.--30. "DOM15_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 28. "DOM15_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 27. "DOM14_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 25.--26. "DOM14_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" newline bitfld.long 0x0 24. "DOM14_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 23. "DOM13_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 21.--22. "DOM13_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 20. "DOM13_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 19. "DOM12_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" newline bitfld.long 0x0 17.--18. "DOM12_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM12_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 15. "DOM11_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 13.--14. "DOM11_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 12. "DOM11_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" newline bitfld.long 0x0 11. "DOM10_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 9.--10. "DOM10_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM10_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 7. "DOM9_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 5.--6. "DOM9_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" newline bitfld.long 0x0 4. "DOM9_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 3. "DOM8_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 1.--2. "DOM8_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM8_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" repeat.end repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x38 0x70 0xA8 0xE0 0x118 0x150 0x188 0x1C0 0x1F8 0x230 0x268 0x2A0 0x2D8 0x310 0x348 ) group.long ($2+0x310C)++0x3 line.long 0x0 "RGN_SEC_PER0_$1,This register is only used for resource manager to control secure access permission." bitfld.long 0x0 31. "DOM3_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM3_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM3_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM3_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM2_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM2_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM2_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM2_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM1_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM1_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM1_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM1_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM0_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM0_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM0_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM0_SEC_EN,Domain secure permission control enable" "0,1" repeat.end repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x38 0x70 0xA8 0xE0 0x118 0x150 0x188 0x1C0 0x1F8 0x230 0x268 0x2A0 0x2D8 0x310 0x348 ) group.long ($2+0x3110)++0x3 line.long 0x0 "RGN_SEC_PER1_$1,This register is only used for resource manager to control secure access permission." bitfld.long 0x0 31. "DOM7_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM7_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM7_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM7_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM6_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM6_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM6_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM6_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM5_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM5_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM5_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM5_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM4_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM4_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM4_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM4_SEC_EN,Domain secure permission control enable" "0,1" repeat.end repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x38 0x70 0xA8 0xE0 0x118 0x150 0x188 0x1C0 0x1F8 0x230 0x268 0x2A0 0x2D8 0x310 0x348 ) group.long ($2+0x3114)++0x3 line.long 0x0 "RGN_SEC_PER2_$1,This register is only used for resource manager to control secure access permission." bitfld.long 0x0 31. "DOM11_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM11_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM11_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM11_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM10_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM10_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM10_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM10_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM9_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM9_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM9_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM9_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM8_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM8_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM8_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM8_SEC_EN,Domain secure permission control enable" "0,1" repeat.end repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x38 0x70 0xA8 0xE0 0x118 0x150 0x188 0x1C0 0x1F8 0x230 0x268 0x2A0 0x2D8 0x310 0x348 ) group.long ($2+0x3118)++0x3 line.long 0x0 "RGN_SEC_PER3_$1,This register is only used for resource manager to control secure access permission." bitfld.long 0x0 31. "DOM15_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM15_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM15_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM15_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM14_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM14_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM14_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM14_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM13_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM13_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM13_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM13_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM12_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM12_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM12_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM12_SEC_EN,Domain secure permission control enable" "0,1" repeat.end repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x38 0x70 0xA8 0xE0 0x118 0x150 0x188 0x1C0 0x1F8 0x230 0x268 0x2A0 0x2D8 0x310 0x348 ) group.long ($2+0x311C)++0x3 line.long 0x0 "RGN_PRI_PER0_$1,This register is only used for resource manager to control privileged access permission." bitfld.long 0x0 31. "DOM3_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM3_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM3_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM3_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM2_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM2_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM2_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM2_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM1_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM1_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM1_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM1_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM0_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM0_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM0_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM0_PRI_EN,Domain privileged permission control enable" "0,1" repeat.end repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x38 0x70 0xA8 0xE0 0x118 0x150 0x188 0x1C0 0x1F8 0x230 0x268 0x2A0 0x2D8 0x310 0x348 ) group.long ($2+0x3120)++0x3 line.long 0x0 "RGN_PRI_PER1_$1,This register is only used for resource manager to control privileged access permission." bitfld.long 0x0 31. "DOM7_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM7_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM7_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM7_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM6_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM6_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM6_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM6_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM5_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM5_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM5_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM5_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM4_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM4_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM4_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM4_PRI_EN,Domain privileged permission control enable" "0,1" repeat.end repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x38 0x70 0xA8 0xE0 0x118 0x150 0x188 0x1C0 0x1F8 0x230 0x268 0x2A0 0x2D8 0x310 0x348 ) group.long ($2+0x3124)++0x3 line.long 0x0 "RGN_PRI_PER2_$1,This register is only used for resource manager to control privileged access permission." bitfld.long 0x0 31. "DOM11_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM11_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM11_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM11_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM10_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM10_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM10_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM10_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM9_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM9_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM9_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM9_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM8_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM8_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM8_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM8_PRI_EN,Domain privileged permission control enable" "0,1" repeat.end repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x38 0x70 0xA8 0xE0 0x118 0x150 0x188 0x1C0 0x1F8 0x230 0x268 0x2A0 0x2D8 0x310 0x348 ) group.long ($2+0x3128)++0x3 line.long 0x0 "RGN_PRI_PER3_$1,This register is only used for resource manager to control privileged access permission." bitfld.long 0x0 31. "DOM15_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM15_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM15_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM15_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM14_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM14_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM14_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM14_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM13_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM13_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM13_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM13_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM12_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM12_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM12_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM12_PRI_EN,Domain privileged permission control enable" "0,1" repeat.end repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x38 0x70 0xA8 0xE0 0x118 0x150 0x188 0x1C0 0x1F8 0x230 0x268 0x2A0 0x2D8 0x310 0x348 ) group.long ($2+0x312C)++0x3 line.long 0x0 "RGN_DOM_SEC_PER_$1,This register is only used for domain master to control secure access permission. When the domain master write this register. it only changes the secure permission for itself. When the domain master read this register. it gets.." bitfld.long 0x0 7. "DOM_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" newline bitfld.long 0x0 0. "DOM_SEC_EN,Domain secure permission control enable" "0,1" repeat.end repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x38 0x70 0xA8 0xE0 0x118 0x150 0x188 0x1C0 0x1F8 0x230 0x268 0x2A0 0x2D8 0x310 0x348 ) group.long ($2+0x3130)++0x3 line.long 0x0 "RGN_DOM_PRI_PER_$1,This register is only used for domain master to control secure access permission. When the domain master write this register. it only changes the secure permission for itself. When the domain master read this register. it gets.." bitfld.long 0x0 7. "DOM_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" newline bitfld.long 0x0 0. "DOM_PRI_EN,Domain privileged permission control enable" "0,1" repeat.end repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x38 0x70 0xA8 0xE0 0x118 0x150 0x188 0x1C0 0x1F8 0x230 0x268 0x2A0 0x2D8 0x310 0x348 ) group.long ($2+0x3134)++0x3 line.long 0x0 "RGN_DOM_ASSIGN_$1,Use to assign domain for accessing DOM_SEC_PER and DOM_PRI_PER register. Only resource manager. group manager and domain owner can access this register. For write. group manager must write its owen domain ID. otherwise write accessing.." hexmask.long.byte 0x0 0.--3. 1. "DID,accessing DOM_SEC_PER and DOM_PRI_PER register" repeat.end tree.end tree "RPC_SAFETY_SCR" base ad:0x3CA00000 repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x4 0x8 0xC 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C ) group.long ($2)++0x3 line.long 0x0 "REGG0_DOM_$1,Assign domain for CKGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1A 0x1B 0x1C 0x1D 0x1E 0x1F )(list 0x40 0x44 0x48 0x4C 0x50 0x54 0x58 0x5C 0x60 0x64 0x68 0x6C 0x70 0x74 0x78 0x7C ) group.long ($2)++0x3 line.long 0x0 "REGG0_DOM_$1,Assign domain for CKGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x20 0x21 0x22 0x23 0x24 0x25 0x26 0x27 0x28 0x29 0x2A 0x2B 0x2C 0x2D 0x2E 0x2F )(list 0x80 0x84 0x88 0x8C 0x90 0x94 0x98 0x9C 0xA0 0xA4 0xA8 0xAC 0xB0 0xB4 0xB8 0xBC ) group.long ($2)++0x3 line.long 0x0 "REGG0_DOM_$1,Assign domain for CKGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x30 0x31 0x32 0x33 0x34 0x35 0x36 0x37 0x38 0x39 0x3A 0x3B 0x3C 0x3D 0x3E 0x3F )(list 0xC0 0xC4 0xC8 0xCC 0xD0 0xD4 0xD8 0xDC 0xE0 0xE4 0xE8 0xEC 0xF0 0xF4 0xF8 0xFC ) group.long ($2)++0x3 line.long 0x0 "REGG0_DOM_$1,Assign domain for CKGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x40 0x41 0x42 0x43 0x44 0x45 0x46 0x47 0x48 0x49 0x4A 0x4B 0x4C 0x4D 0x4E 0x4F )(list 0x100 0x104 0x108 0x10C 0x110 0x114 0x118 0x11C 0x120 0x124 0x128 0x12C 0x130 0x134 0x138 0x13C ) group.long ($2)++0x3 line.long 0x0 "REGG0_DOM_$1,Assign domain for CKGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x50 0x51 0x52 0x53 0x54 0x55 0x56 0x57 0x58 0x59 0x5A 0x5B 0x5C 0x5D 0x5E 0x5F )(list 0x140 0x144 0x148 0x14C 0x150 0x154 0x158 0x15C 0x160 0x164 0x168 0x16C 0x170 0x174 0x178 0x17C ) group.long ($2)++0x3 line.long 0x0 "REGG0_DOM_$1,Assign domain for CKGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x60 0x61 0x62 0x63 0x64 0x65 0x66 0x67 0x68 0x69 0x6A 0x6B 0x6C 0x6D 0x6E 0x6F )(list 0x180 0x184 0x188 0x18C 0x190 0x194 0x198 0x19C 0x1A0 0x1A4 0x1A8 0x1AC 0x1B0 0x1B4 0x1B8 0x1BC ) group.long ($2)++0x3 line.long 0x0 "REGG0_DOM_$1,Assign domain for CKGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x70 0x71 0x72 0x73 0x74 0x75 0x76 0x77 0x78 0x79 0x7A 0x7B 0x7C 0x7D 0x7E 0x7F )(list 0x1C0 0x1C4 0x1C8 0x1CC 0x1D0 0x1D4 0x1D8 0x1DC 0x1E0 0x1E4 0x1E8 0x1EC 0x1F0 0x1F4 0x1F8 0x1FC ) group.long ($2)++0x3 line.long 0x0 "REGG0_DOM_$1,Assign domain for CKGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x80 0x81 0x82 0x83 0x84 0x85 0x86 0x87 0x88 0x89 0x8A 0x8B 0x8C 0x8D 0x8E 0x8F )(list 0x200 0x204 0x208 0x20C 0x210 0x214 0x218 0x21C 0x220 0x224 0x228 0x22C 0x230 0x234 0x238 0x23C ) group.long ($2)++0x3 line.long 0x0 "REGG0_DOM_$1,Assign domain for CKGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x90 0x91 0x92 0x93 0x94 0x95 0x96 0x97 0x98 0x99 0x9A 0x9B 0x9C 0x9D 0x9E 0x9F )(list 0x240 0x244 0x248 0x24C 0x250 0x254 0x258 0x25C 0x260 0x264 0x268 0x26C 0x270 0x274 0x278 0x27C ) group.long ($2)++0x3 line.long 0x0 "REGG0_DOM_$1,Assign domain for CKGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xA0 0xA1 0xA2 0xA3 0xA4 0xA5 0xA6 0xA7 0xA8 0xA9 0xAA 0xAB 0xAC 0xAD 0xAE 0xAF )(list 0x280 0x284 0x288 0x28C 0x290 0x294 0x298 0x29C 0x2A0 0x2A4 0x2A8 0x2AC 0x2B0 0x2B4 0x2B8 0x2BC ) group.long ($2)++0x3 line.long 0x0 "REGG0_DOM_$1,Assign domain for CKGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xB0 0xB1 0xB2 0xB3 0xB4 0xB5 0xB6 0xB7 0xB8 0xB9 0xBA 0xBB 0xBC 0xBD 0xBE 0xBF )(list 0x2C0 0x2C4 0x2C8 0x2CC 0x2D0 0x2D4 0x2D8 0x2DC 0x2E0 0x2E4 0x2E8 0x2EC 0x2F0 0x2F4 0x2F8 0x2FC ) group.long ($2)++0x3 line.long 0x0 "REGG0_DOM_$1,Assign domain for CKGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xC0 0xC1 0xC2 0xC3 0xC4 0xC5 0xC6 0xC7 0xC8 0xC9 0xCA 0xCB 0xCC 0xCD 0xCE 0xCF )(list 0x300 0x304 0x308 0x30C 0x310 0x314 0x318 0x31C 0x320 0x324 0x328 0x32C 0x330 0x334 0x338 0x33C ) group.long ($2)++0x3 line.long 0x0 "REGG0_DOM_$1,Assign domain for CKGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xD0 0xD1 0xD2 0xD3 0xD4 0xD5 0xD6 0xD7 0xD8 0xD9 0xDA 0xDB 0xDC 0xDD 0xDE 0xDF )(list 0x340 0x344 0x348 0x34C 0x350 0x354 0x358 0x35C 0x360 0x364 0x368 0x36C 0x370 0x374 0x378 0x37C ) group.long ($2)++0x3 line.long 0x0 "REGG0_DOM_$1,Assign domain for CKGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xE0 0xE1 0xE2 0xE3 0xE4 0xE5 0xE6 0xE7 0xE8 0xE9 0xEA 0xEB 0xEC 0xED 0xEE 0xEF )(list 0x380 0x384 0x388 0x38C 0x390 0x394 0x398 0x39C 0x3A0 0x3A4 0x3A8 0x3AC 0x3B0 0x3B4 0x3B8 0x3BC ) group.long ($2)++0x3 line.long 0x0 "REGG0_DOM_$1,Assign domain for CKGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xF0 0xF1 0xF2 0xF3 0xF4 0xF5 0xF6 0xF7 0xF8 0xF9 0xFA 0xFB 0xFC 0xFD 0xFE 0xFF )(list 0x3C0 0x3C4 0x3C8 0x3CC 0x3D0 0x3D4 0x3D8 0x3DC 0x3E0 0x3E4 0x3E8 0x3EC 0x3F0 0x3F4 0x3F8 0x3FC ) group.long ($2)++0x3 line.long 0x0 "REGG0_DOM_$1,Assign domain for CKGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x4 0x8 0xC 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C ) group.long ($2+0x400)++0x3 line.long 0x0 "REGG1_DOM_$1,Assign domain for CKGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1A 0x1B 0x1C 0x1D 0x1E 0x1F )(list 0x40 0x44 0x48 0x4C 0x50 0x54 0x58 0x5C 0x60 0x64 0x68 0x6C 0x70 0x74 0x78 0x7C ) group.long ($2+0x400)++0x3 line.long 0x0 "REGG1_DOM_$1,Assign domain for CKGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x20 0x21 0x22 0x23 0x24 0x25 0x26 0x27 0x28 0x29 0x2A 0x2B 0x2C 0x2D 0x2E 0x2F )(list 0x80 0x84 0x88 0x8C 0x90 0x94 0x98 0x9C 0xA0 0xA4 0xA8 0xAC 0xB0 0xB4 0xB8 0xBC ) group.long ($2+0x400)++0x3 line.long 0x0 "REGG1_DOM_$1,Assign domain for CKGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x30 0x31 0x32 0x33 0x34 0x35 0x36 0x37 0x38 0x39 0x3A 0x3B 0x3C 0x3D 0x3E 0x3F )(list 0xC0 0xC4 0xC8 0xCC 0xD0 0xD4 0xD8 0xDC 0xE0 0xE4 0xE8 0xEC 0xF0 0xF4 0xF8 0xFC ) group.long ($2+0x400)++0x3 line.long 0x0 "REGG1_DOM_$1,Assign domain for CKGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x40 0x41 0x42 0x43 0x44 0x45 0x46 0x47 0x48 0x49 0x4A 0x4B 0x4C 0x4D 0x4E 0x4F )(list 0x100 0x104 0x108 0x10C 0x110 0x114 0x118 0x11C 0x120 0x124 0x128 0x12C 0x130 0x134 0x138 0x13C ) group.long ($2+0x400)++0x3 line.long 0x0 "REGG1_DOM_$1,Assign domain for CKGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x50 0x51 0x52 0x53 0x54 0x55 0x56 0x57 0x58 0x59 0x5A 0x5B 0x5C 0x5D 0x5E 0x5F )(list 0x140 0x144 0x148 0x14C 0x150 0x154 0x158 0x15C 0x160 0x164 0x168 0x16C 0x170 0x174 0x178 0x17C ) group.long ($2+0x400)++0x3 line.long 0x0 "REGG1_DOM_$1,Assign domain for CKGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x60 0x61 0x62 0x63 0x64 0x65 0x66 0x67 0x68 0x69 0x6A 0x6B 0x6C 0x6D 0x6E 0x6F )(list 0x180 0x184 0x188 0x18C 0x190 0x194 0x198 0x19C 0x1A0 0x1A4 0x1A8 0x1AC 0x1B0 0x1B4 0x1B8 0x1BC ) group.long ($2+0x400)++0x3 line.long 0x0 "REGG1_DOM_$1,Assign domain for CKGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x70 0x71 0x72 0x73 0x74 0x75 0x76 0x77 0x78 0x79 0x7A 0x7B 0x7C 0x7D 0x7E 0x7F )(list 0x1C0 0x1C4 0x1C8 0x1CC 0x1D0 0x1D4 0x1D8 0x1DC 0x1E0 0x1E4 0x1E8 0x1EC 0x1F0 0x1F4 0x1F8 0x1FC ) group.long ($2+0x400)++0x3 line.long 0x0 "REGG1_DOM_$1,Assign domain for CKGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x80 0x81 0x82 0x83 0x84 0x85 0x86 0x87 0x88 0x89 0x8A 0x8B 0x8C 0x8D 0x8E 0x8F )(list 0x200 0x204 0x208 0x20C 0x210 0x214 0x218 0x21C 0x220 0x224 0x228 0x22C 0x230 0x234 0x238 0x23C ) group.long ($2+0x400)++0x3 line.long 0x0 "REGG1_DOM_$1,Assign domain for CKGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x90 0x91 0x92 0x93 0x94 0x95 0x96 0x97 0x98 0x99 0x9A 0x9B 0x9C 0x9D 0x9E 0x9F )(list 0x240 0x244 0x248 0x24C 0x250 0x254 0x258 0x25C 0x260 0x264 0x268 0x26C 0x270 0x274 0x278 0x27C ) group.long ($2+0x400)++0x3 line.long 0x0 "REGG1_DOM_$1,Assign domain for CKGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xA0 0xA1 0xA2 0xA3 0xA4 0xA5 0xA6 0xA7 0xA8 0xA9 0xAA 0xAB 0xAC 0xAD 0xAE 0xAF )(list 0x280 0x284 0x288 0x28C 0x290 0x294 0x298 0x29C 0x2A0 0x2A4 0x2A8 0x2AC 0x2B0 0x2B4 0x2B8 0x2BC ) group.long ($2+0x400)++0x3 line.long 0x0 "REGG1_DOM_$1,Assign domain for CKGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xB0 0xB1 0xB2 0xB3 0xB4 0xB5 0xB6 0xB7 0xB8 0xB9 0xBA 0xBB 0xBC 0xBD 0xBE 0xBF )(list 0x2C0 0x2C4 0x2C8 0x2CC 0x2D0 0x2D4 0x2D8 0x2DC 0x2E0 0x2E4 0x2E8 0x2EC 0x2F0 0x2F4 0x2F8 0x2FC ) group.long ($2+0x400)++0x3 line.long 0x0 "REGG1_DOM_$1,Assign domain for CKGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xC0 0xC1 0xC2 0xC3 0xC4 0xC5 0xC6 0xC7 0xC8 0xC9 0xCA 0xCB 0xCC 0xCD 0xCE 0xCF )(list 0x300 0x304 0x308 0x30C 0x310 0x314 0x318 0x31C 0x320 0x324 0x328 0x32C 0x330 0x334 0x338 0x33C ) group.long ($2+0x400)++0x3 line.long 0x0 "REGG1_DOM_$1,Assign domain for CKGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xD0 0xD1 0xD2 0xD3 0xD4 0xD5 0xD6 0xD7 0xD8 0xD9 0xDA 0xDB 0xDC 0xDD 0xDE 0xDF )(list 0x340 0x344 0x348 0x34C 0x350 0x354 0x358 0x35C 0x360 0x364 0x368 0x36C 0x370 0x374 0x378 0x37C ) group.long ($2+0x400)++0x3 line.long 0x0 "REGG1_DOM_$1,Assign domain for CKGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xE0 0xE1 0xE2 0xE3 0xE4 0xE5 0xE6 0xE7 0xE8 0xE9 0xEA 0xEB 0xEC 0xED 0xEE 0xEF )(list 0x380 0x384 0x388 0x38C 0x390 0x394 0x398 0x39C 0x3A0 0x3A4 0x3A8 0x3AC 0x3B0 0x3B4 0x3B8 0x3BC ) group.long ($2+0x400)++0x3 line.long 0x0 "REGG1_DOM_$1,Assign domain for CKGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xF0 0xF1 0xF2 0xF3 0xF4 0xF5 0xF6 0xF7 0xF8 0xF9 0xFA 0xFB 0xFC 0xFD 0xFE 0xFF )(list 0x3C0 0x3C4 0x3C8 0x3CC 0x3D0 0x3D4 0x3D8 0x3DC 0x3E0 0x3E4 0x3E8 0x3EC 0x3F0 0x3F4 0x3F8 0x3FC ) group.long ($2+0x400)++0x3 line.long 0x0 "REGG1_DOM_$1,Assign domain for CKGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x4 0x8 0xC 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C ) group.long ($2+0x800)++0x3 line.long 0x0 "REGG2_DOM_$1,Assign domain for SCR registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1A 0x1B 0x1C 0x1D 0x1E 0x1F )(list 0x40 0x44 0x48 0x4C 0x50 0x54 0x58 0x5C 0x60 0x64 0x68 0x6C 0x70 0x74 0x78 0x7C ) group.long ($2+0x800)++0x3 line.long 0x0 "REGG2_DOM_$1,Assign domain for SCR registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x20 0x21 0x22 0x23 0x24 0x25 0x26 0x27 0x28 0x29 0x2A 0x2B 0x2C 0x2D 0x2E 0x2F )(list 0x80 0x84 0x88 0x8C 0x90 0x94 0x98 0x9C 0xA0 0xA4 0xA8 0xAC 0xB0 0xB4 0xB8 0xBC ) group.long ($2+0x800)++0x3 line.long 0x0 "REGG2_DOM_$1,Assign domain for SCR registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x30 0x31 0x32 0x33 0x34 0x35 0x36 0x37 0x38 0x39 0x3A 0x3B 0x3C 0x3D 0x3E 0x3F )(list 0xC0 0xC4 0xC8 0xCC 0xD0 0xD4 0xD8 0xDC 0xE0 0xE4 0xE8 0xEC 0xF0 0xF4 0xF8 0xFC ) group.long ($2+0x800)++0x3 line.long 0x0 "REGG2_DOM_$1,Assign domain for SCR registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x40 0x41 0x42 0x43 0x44 0x45 0x46 0x47 0x48 0x49 0x4A 0x4B 0x4C 0x4D 0x4E 0x4F )(list 0x100 0x104 0x108 0x10C 0x110 0x114 0x118 0x11C 0x120 0x124 0x128 0x12C 0x130 0x134 0x138 0x13C ) group.long ($2+0x800)++0x3 line.long 0x0 "REGG2_DOM_$1,Assign domain for SCR registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x50 0x51 0x52 0x53 0x54 0x55 0x56 0x57 0x58 0x59 0x5A 0x5B 0x5C 0x5D 0x5E 0x5F )(list 0x140 0x144 0x148 0x14C 0x150 0x154 0x158 0x15C 0x160 0x164 0x168 0x16C 0x170 0x174 0x178 0x17C ) group.long ($2+0x800)++0x3 line.long 0x0 "REGG2_DOM_$1,Assign domain for SCR registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x60 0x61 0x62 0x63 0x64 0x65 0x66 0x67 0x68 0x69 0x6A 0x6B 0x6C 0x6D 0x6E 0x6F )(list 0x180 0x184 0x188 0x18C 0x190 0x194 0x198 0x19C 0x1A0 0x1A4 0x1A8 0x1AC 0x1B0 0x1B4 0x1B8 0x1BC ) group.long ($2+0x800)++0x3 line.long 0x0 "REGG2_DOM_$1,Assign domain for SCR registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x70 0x71 0x72 0x73 0x74 0x75 0x76 0x77 0x78 0x79 0x7A 0x7B 0x7C 0x7D 0x7E 0x7F )(list 0x1C0 0x1C4 0x1C8 0x1CC 0x1D0 0x1D4 0x1D8 0x1DC 0x1E0 0x1E4 0x1E8 0x1EC 0x1F0 0x1F4 0x1F8 0x1FC ) group.long ($2+0x800)++0x3 line.long 0x0 "REGG2_DOM_$1,Assign domain for SCR registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x80 0x81 0x82 0x83 0x84 0x85 0x86 0x87 0x88 0x89 0x8A 0x8B 0x8C 0x8D 0x8E 0x8F )(list 0x200 0x204 0x208 0x20C 0x210 0x214 0x218 0x21C 0x220 0x224 0x228 0x22C 0x230 0x234 0x238 0x23C ) group.long ($2+0x800)++0x3 line.long 0x0 "REGG2_DOM_$1,Assign domain for SCR registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x90 0x91 0x92 0x93 0x94 0x95 0x96 0x97 0x98 0x99 0x9A 0x9B 0x9C 0x9D 0x9E 0x9F )(list 0x240 0x244 0x248 0x24C 0x250 0x254 0x258 0x25C 0x260 0x264 0x268 0x26C 0x270 0x274 0x278 0x27C ) group.long ($2+0x800)++0x3 line.long 0x0 "REGG2_DOM_$1,Assign domain for SCR registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xA0 0xA1 0xA2 0xA3 0xA4 0xA5 0xA6 0xA7 0xA8 0xA9 0xAA 0xAB 0xAC 0xAD 0xAE 0xAF )(list 0x280 0x284 0x288 0x28C 0x290 0x294 0x298 0x29C 0x2A0 0x2A4 0x2A8 0x2AC 0x2B0 0x2B4 0x2B8 0x2BC ) group.long ($2+0x800)++0x3 line.long 0x0 "REGG2_DOM_$1,Assign domain for SCR registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xB0 0xB1 0xB2 0xB3 0xB4 0xB5 0xB6 0xB7 0xB8 0xB9 0xBA 0xBB 0xBC 0xBD 0xBE 0xBF )(list 0x2C0 0x2C4 0x2C8 0x2CC 0x2D0 0x2D4 0x2D8 0x2DC 0x2E0 0x2E4 0x2E8 0x2EC 0x2F0 0x2F4 0x2F8 0x2FC ) group.long ($2+0x800)++0x3 line.long 0x0 "REGG2_DOM_$1,Assign domain for SCR registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xC0 0xC1 0xC2 0xC3 0xC4 0xC5 0xC6 0xC7 0xC8 0xC9 0xCA 0xCB 0xCC 0xCD 0xCE 0xCF )(list 0x300 0x304 0x308 0x30C 0x310 0x314 0x318 0x31C 0x320 0x324 0x328 0x32C 0x330 0x334 0x338 0x33C ) group.long ($2+0x800)++0x3 line.long 0x0 "REGG2_DOM_$1,Assign domain for SCR registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xD0 0xD1 0xD2 0xD3 0xD4 0xD5 0xD6 0xD7 0xD8 0xD9 0xDA 0xDB 0xDC 0xDD 0xDE 0xDF )(list 0x340 0x344 0x348 0x34C 0x350 0x354 0x358 0x35C 0x360 0x364 0x368 0x36C 0x370 0x374 0x378 0x37C ) group.long ($2+0x800)++0x3 line.long 0x0 "REGG2_DOM_$1,Assign domain for SCR registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xE0 0xE1 0xE2 0xE3 0xE4 0xE5 0xE6 0xE7 0xE8 0xE9 0xEA 0xEB 0xEC 0xED 0xEE 0xEF )(list 0x380 0x384 0x388 0x38C 0x390 0x394 0x398 0x39C 0x3A0 0x3A4 0x3A8 0x3AC 0x3B0 0x3B4 0x3B8 0x3BC ) group.long ($2+0x800)++0x3 line.long 0x0 "REGG2_DOM_$1,Assign domain for SCR registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xF0 0xF1 0xF2 0xF3 0xF4 0xF5 0xF6 0xF7 0xF8 0xF9 0xFA 0xFB 0xFC 0xFD 0xFE 0xFF )(list 0x3C0 0x3C4 0x3C8 0x3CC 0x3D0 0x3D4 0x3D8 0x3DC 0x3E0 0x3E4 0x3E8 0x3EC 0x3F0 0x3F4 0x3F8 0x3FC ) group.long ($2+0x800)++0x3 line.long 0x0 "REGG2_DOM_$1,Assign domain for SCR registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x4 0x8 0xC 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C ) group.long ($2+0xC00)++0x3 line.long 0x0 "REGG3_DOM_$1,Assign domain for SCR registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1A 0x1B 0x1C 0x1D 0x1E 0x1F )(list 0x40 0x44 0x48 0x4C 0x50 0x54 0x58 0x5C 0x60 0x64 0x68 0x6C 0x70 0x74 0x78 0x7C ) group.long ($2+0xC00)++0x3 line.long 0x0 "REGG3_DOM_$1,Assign domain for SCR registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x20 0x21 0x22 0x23 0x24 0x25 0x26 0x27 0x28 0x29 0x2A 0x2B 0x2C 0x2D 0x2E 0x2F )(list 0x80 0x84 0x88 0x8C 0x90 0x94 0x98 0x9C 0xA0 0xA4 0xA8 0xAC 0xB0 0xB4 0xB8 0xBC ) group.long ($2+0xC00)++0x3 line.long 0x0 "REGG3_DOM_$1,Assign domain for SCR registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x30 0x31 0x32 0x33 0x34 0x35 0x36 0x37 0x38 0x39 0x3A 0x3B 0x3C 0x3D 0x3E 0x3F )(list 0xC0 0xC4 0xC8 0xCC 0xD0 0xD4 0xD8 0xDC 0xE0 0xE4 0xE8 0xEC 0xF0 0xF4 0xF8 0xFC ) group.long ($2+0xC00)++0x3 line.long 0x0 "REGG3_DOM_$1,Assign domain for SCR registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x40 0x41 0x42 0x43 0x44 0x45 0x46 0x47 0x48 0x49 0x4A 0x4B 0x4C 0x4D 0x4E 0x4F )(list 0x100 0x104 0x108 0x10C 0x110 0x114 0x118 0x11C 0x120 0x124 0x128 0x12C 0x130 0x134 0x138 0x13C ) group.long ($2+0xC00)++0x3 line.long 0x0 "REGG3_DOM_$1,Assign domain for SCR registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x50 0x51 0x52 0x53 0x54 0x55 0x56 0x57 0x58 0x59 0x5A 0x5B 0x5C 0x5D 0x5E 0x5F )(list 0x140 0x144 0x148 0x14C 0x150 0x154 0x158 0x15C 0x160 0x164 0x168 0x16C 0x170 0x174 0x178 0x17C ) group.long ($2+0xC00)++0x3 line.long 0x0 "REGG3_DOM_$1,Assign domain for SCR registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x60 0x61 0x62 0x63 0x64 0x65 0x66 0x67 0x68 0x69 0x6A 0x6B 0x6C 0x6D 0x6E 0x6F )(list 0x180 0x184 0x188 0x18C 0x190 0x194 0x198 0x19C 0x1A0 0x1A4 0x1A8 0x1AC 0x1B0 0x1B4 0x1B8 0x1BC ) group.long ($2+0xC00)++0x3 line.long 0x0 "REGG3_DOM_$1,Assign domain for SCR registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x70 0x71 0x72 0x73 0x74 0x75 0x76 0x77 0x78 0x79 0x7A 0x7B 0x7C 0x7D 0x7E 0x7F )(list 0x1C0 0x1C4 0x1C8 0x1CC 0x1D0 0x1D4 0x1D8 0x1DC 0x1E0 0x1E4 0x1E8 0x1EC 0x1F0 0x1F4 0x1F8 0x1FC ) group.long ($2+0xC00)++0x3 line.long 0x0 "REGG3_DOM_$1,Assign domain for SCR registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x80 0x81 0x82 0x83 0x84 0x85 0x86 0x87 0x88 0x89 0x8A 0x8B 0x8C 0x8D 0x8E 0x8F )(list 0x200 0x204 0x208 0x20C 0x210 0x214 0x218 0x21C 0x220 0x224 0x228 0x22C 0x230 0x234 0x238 0x23C ) group.long ($2+0xC00)++0x3 line.long 0x0 "REGG3_DOM_$1,Assign domain for SCR registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x90 0x91 0x92 0x93 0x94 0x95 0x96 0x97 0x98 0x99 0x9A 0x9B 0x9C 0x9D 0x9E 0x9F )(list 0x240 0x244 0x248 0x24C 0x250 0x254 0x258 0x25C 0x260 0x264 0x268 0x26C 0x270 0x274 0x278 0x27C ) group.long ($2+0xC00)++0x3 line.long 0x0 "REGG3_DOM_$1,Assign domain for SCR registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xA0 0xA1 0xA2 0xA3 0xA4 0xA5 0xA6 0xA7 0xA8 0xA9 0xAA 0xAB 0xAC 0xAD 0xAE 0xAF )(list 0x280 0x284 0x288 0x28C 0x290 0x294 0x298 0x29C 0x2A0 0x2A4 0x2A8 0x2AC 0x2B0 0x2B4 0x2B8 0x2BC ) group.long ($2+0xC00)++0x3 line.long 0x0 "REGG3_DOM_$1,Assign domain for SCR registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xB0 0xB1 0xB2 0xB3 0xB4 0xB5 0xB6 0xB7 0xB8 0xB9 0xBA 0xBB 0xBC 0xBD 0xBE 0xBF )(list 0x2C0 0x2C4 0x2C8 0x2CC 0x2D0 0x2D4 0x2D8 0x2DC 0x2E0 0x2E4 0x2E8 0x2EC 0x2F0 0x2F4 0x2F8 0x2FC ) group.long ($2+0xC00)++0x3 line.long 0x0 "REGG3_DOM_$1,Assign domain for SCR registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xC0 0xC1 0xC2 0xC3 0xC4 0xC5 0xC6 0xC7 0xC8 0xC9 0xCA 0xCB 0xCC 0xCD 0xCE 0xCF )(list 0x300 0x304 0x308 0x30C 0x310 0x314 0x318 0x31C 0x320 0x324 0x328 0x32C 0x330 0x334 0x338 0x33C ) group.long ($2+0xC00)++0x3 line.long 0x0 "REGG3_DOM_$1,Assign domain for SCR registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xD0 0xD1 0xD2 0xD3 0xD4 0xD5 0xD6 0xD7 0xD8 0xD9 0xDA 0xDB 0xDC 0xDD 0xDE 0xDF )(list 0x340 0x344 0x348 0x34C 0x350 0x354 0x358 0x35C 0x360 0x364 0x368 0x36C 0x370 0x374 0x378 0x37C ) group.long ($2+0xC00)++0x3 line.long 0x0 "REGG3_DOM_$1,Assign domain for SCR registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xE0 0xE1 0xE2 0xE3 0xE4 0xE5 0xE6 0xE7 0xE8 0xE9 0xEA 0xEB 0xEC 0xED 0xEE 0xEF )(list 0x380 0x384 0x388 0x38C 0x390 0x394 0x398 0x39C 0x3A0 0x3A4 0x3A8 0x3AC 0x3B0 0x3B4 0x3B8 0x3BC ) group.long ($2+0xC00)++0x3 line.long 0x0 "REGG3_DOM_$1,Assign domain for SCR registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xF0 0xF1 0xF2 0xF3 0xF4 0xF5 0xF6 0xF7 0xF8 0xF9 0xFA 0xFB 0xFC 0xFD 0xFE 0xFF )(list 0x3C0 0x3C4 0x3C8 0x3CC 0x3D0 0x3D4 0x3D8 0x3DC 0x3E0 0x3E4 0x3E8 0x3EC 0x3F0 0x3F4 0x3F8 0x3FC ) group.long ($2+0xC00)++0x3 line.long 0x0 "REGG3_DOM_$1,Assign domain for SCR registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x4 0x8 0xC 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C ) group.long ($2+0x1000)++0x3 line.long 0x0 "REGG4_DOM_$1,Assign domain for RSTGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1A 0x1B 0x1C 0x1D 0x1E 0x1F )(list 0x40 0x44 0x48 0x4C 0x50 0x54 0x58 0x5C 0x60 0x64 0x68 0x6C 0x70 0x74 0x78 0x7C ) group.long ($2+0x1000)++0x3 line.long 0x0 "REGG4_DOM_$1,Assign domain for RSTGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x20 0x21 0x22 0x23 0x24 0x25 0x26 0x27 0x28 0x29 0x2A 0x2B 0x2C 0x2D 0x2E 0x2F )(list 0x80 0x84 0x88 0x8C 0x90 0x94 0x98 0x9C 0xA0 0xA4 0xA8 0xAC 0xB0 0xB4 0xB8 0xBC ) group.long ($2+0x1000)++0x3 line.long 0x0 "REGG4_DOM_$1,Assign domain for RSTGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x30 0x31 0x32 0x33 0x34 0x35 0x36 0x37 0x38 0x39 0x3A 0x3B 0x3C 0x3D 0x3E 0x3F )(list 0xC0 0xC4 0xC8 0xCC 0xD0 0xD4 0xD8 0xDC 0xE0 0xE4 0xE8 0xEC 0xF0 0xF4 0xF8 0xFC ) group.long ($2+0x1000)++0x3 line.long 0x0 "REGG4_DOM_$1,Assign domain for RSTGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x40 0x41 0x42 0x43 0x44 0x45 0x46 0x47 0x48 0x49 0x4A 0x4B 0x4C 0x4D 0x4E 0x4F )(list 0x100 0x104 0x108 0x10C 0x110 0x114 0x118 0x11C 0x120 0x124 0x128 0x12C 0x130 0x134 0x138 0x13C ) group.long ($2+0x1000)++0x3 line.long 0x0 "REGG4_DOM_$1,Assign domain for RSTGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x50 0x51 0x52 0x53 0x54 0x55 0x56 0x57 0x58 0x59 0x5A 0x5B 0x5C 0x5D 0x5E 0x5F )(list 0x140 0x144 0x148 0x14C 0x150 0x154 0x158 0x15C 0x160 0x164 0x168 0x16C 0x170 0x174 0x178 0x17C ) group.long ($2+0x1000)++0x3 line.long 0x0 "REGG4_DOM_$1,Assign domain for RSTGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x60 0x61 0x62 0x63 0x64 0x65 0x66 0x67 0x68 0x69 0x6A 0x6B 0x6C 0x6D 0x6E 0x6F )(list 0x180 0x184 0x188 0x18C 0x190 0x194 0x198 0x19C 0x1A0 0x1A4 0x1A8 0x1AC 0x1B0 0x1B4 0x1B8 0x1BC ) group.long ($2+0x1000)++0x3 line.long 0x0 "REGG4_DOM_$1,Assign domain for RSTGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x70 0x71 0x72 0x73 0x74 0x75 0x76 0x77 0x78 0x79 0x7A 0x7B 0x7C 0x7D 0x7E 0x7F )(list 0x1C0 0x1C4 0x1C8 0x1CC 0x1D0 0x1D4 0x1D8 0x1DC 0x1E0 0x1E4 0x1E8 0x1EC 0x1F0 0x1F4 0x1F8 0x1FC ) group.long ($2+0x1000)++0x3 line.long 0x0 "REGG4_DOM_$1,Assign domain for RSTGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x80 0x81 0x82 0x83 0x84 0x85 0x86 0x87 0x88 0x89 0x8A 0x8B 0x8C 0x8D 0x8E 0x8F )(list 0x200 0x204 0x208 0x20C 0x210 0x214 0x218 0x21C 0x220 0x224 0x228 0x22C 0x230 0x234 0x238 0x23C ) group.long ($2+0x1000)++0x3 line.long 0x0 "REGG4_DOM_$1,Assign domain for RSTGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x90 0x91 0x92 0x93 0x94 0x95 0x96 0x97 0x98 0x99 0x9A 0x9B 0x9C 0x9D 0x9E 0x9F )(list 0x240 0x244 0x248 0x24C 0x250 0x254 0x258 0x25C 0x260 0x264 0x268 0x26C 0x270 0x274 0x278 0x27C ) group.long ($2+0x1000)++0x3 line.long 0x0 "REGG4_DOM_$1,Assign domain for RSTGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xA0 0xA1 0xA2 0xA3 0xA4 0xA5 0xA6 0xA7 0xA8 0xA9 0xAA 0xAB 0xAC 0xAD 0xAE 0xAF )(list 0x280 0x284 0x288 0x28C 0x290 0x294 0x298 0x29C 0x2A0 0x2A4 0x2A8 0x2AC 0x2B0 0x2B4 0x2B8 0x2BC ) group.long ($2+0x1000)++0x3 line.long 0x0 "REGG4_DOM_$1,Assign domain for RSTGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xB0 0xB1 0xB2 0xB3 0xB4 0xB5 0xB6 0xB7 0xB8 0xB9 0xBA 0xBB 0xBC 0xBD 0xBE 0xBF )(list 0x2C0 0x2C4 0x2C8 0x2CC 0x2D0 0x2D4 0x2D8 0x2DC 0x2E0 0x2E4 0x2E8 0x2EC 0x2F0 0x2F4 0x2F8 0x2FC ) group.long ($2+0x1000)++0x3 line.long 0x0 "REGG4_DOM_$1,Assign domain for RSTGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xC0 0xC1 0xC2 0xC3 0xC4 0xC5 0xC6 0xC7 0xC8 0xC9 0xCA 0xCB 0xCC 0xCD 0xCE 0xCF )(list 0x300 0x304 0x308 0x30C 0x310 0x314 0x318 0x31C 0x320 0x324 0x328 0x32C 0x330 0x334 0x338 0x33C ) group.long ($2+0x1000)++0x3 line.long 0x0 "REGG4_DOM_$1,Assign domain for RSTGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xD0 0xD1 0xD2 0xD3 0xD4 0xD5 0xD6 0xD7 0xD8 0xD9 0xDA 0xDB 0xDC 0xDD 0xDE 0xDF )(list 0x340 0x344 0x348 0x34C 0x350 0x354 0x358 0x35C 0x360 0x364 0x368 0x36C 0x370 0x374 0x378 0x37C ) group.long ($2+0x1000)++0x3 line.long 0x0 "REGG4_DOM_$1,Assign domain for RSTGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xE0 0xE1 0xE2 0xE3 0xE4 0xE5 0xE6 0xE7 0xE8 0xE9 0xEA 0xEB 0xEC 0xED 0xEE 0xEF )(list 0x380 0x384 0x388 0x38C 0x390 0x394 0x398 0x39C 0x3A0 0x3A4 0x3A8 0x3AC 0x3B0 0x3B4 0x3B8 0x3BC ) group.long ($2+0x1000)++0x3 line.long 0x0 "REGG4_DOM_$1,Assign domain for RSTGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xF0 0xF1 0xF2 0xF3 0xF4 0xF5 0xF6 0xF7 0xF8 0xF9 0xFA 0xFB 0xFC 0xFD 0xFE 0xFF )(list 0x3C0 0x3C4 0x3C8 0x3CC 0x3D0 0x3D4 0x3D8 0x3DC 0x3E0 0x3E4 0x3E8 0x3EC 0x3F0 0x3F4 0x3F8 0x3FC ) group.long ($2+0x1000)++0x3 line.long 0x0 "REGG4_DOM_$1,Assign domain for RSTGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x4 0x8 0xC 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C ) group.long ($2+0x1400)++0x3 line.long 0x0 "REGG5_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1A 0x1B 0x1C 0x1D 0x1E 0x1F )(list 0x40 0x44 0x48 0x4C 0x50 0x54 0x58 0x5C 0x60 0x64 0x68 0x6C 0x70 0x74 0x78 0x7C ) group.long ($2+0x1400)++0x3 line.long 0x0 "REGG5_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x20 0x21 0x22 0x23 0x24 0x25 0x26 0x27 0x28 0x29 0x2A 0x2B 0x2C 0x2D 0x2E 0x2F )(list 0x80 0x84 0x88 0x8C 0x90 0x94 0x98 0x9C 0xA0 0xA4 0xA8 0xAC 0xB0 0xB4 0xB8 0xBC ) group.long ($2+0x1400)++0x3 line.long 0x0 "REGG5_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x30 0x31 0x32 0x33 0x34 0x35 0x36 0x37 0x38 0x39 0x3A 0x3B 0x3C 0x3D 0x3E 0x3F )(list 0xC0 0xC4 0xC8 0xCC 0xD0 0xD4 0xD8 0xDC 0xE0 0xE4 0xE8 0xEC 0xF0 0xF4 0xF8 0xFC ) group.long ($2+0x1400)++0x3 line.long 0x0 "REGG5_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x40 0x41 0x42 0x43 0x44 0x45 0x46 0x47 0x48 0x49 0x4A 0x4B 0x4C 0x4D 0x4E 0x4F )(list 0x100 0x104 0x108 0x10C 0x110 0x114 0x118 0x11C 0x120 0x124 0x128 0x12C 0x130 0x134 0x138 0x13C ) group.long ($2+0x1400)++0x3 line.long 0x0 "REGG5_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x50 0x51 0x52 0x53 0x54 0x55 0x56 0x57 0x58 0x59 0x5A 0x5B 0x5C 0x5D 0x5E 0x5F )(list 0x140 0x144 0x148 0x14C 0x150 0x154 0x158 0x15C 0x160 0x164 0x168 0x16C 0x170 0x174 0x178 0x17C ) group.long ($2+0x1400)++0x3 line.long 0x0 "REGG5_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x60 0x61 0x62 0x63 0x64 0x65 0x66 0x67 0x68 0x69 0x6A 0x6B 0x6C 0x6D 0x6E 0x6F )(list 0x180 0x184 0x188 0x18C 0x190 0x194 0x198 0x19C 0x1A0 0x1A4 0x1A8 0x1AC 0x1B0 0x1B4 0x1B8 0x1BC ) group.long ($2+0x1400)++0x3 line.long 0x0 "REGG5_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x70 0x71 0x72 0x73 0x74 0x75 0x76 0x77 0x78 0x79 0x7A 0x7B 0x7C 0x7D 0x7E 0x7F )(list 0x1C0 0x1C4 0x1C8 0x1CC 0x1D0 0x1D4 0x1D8 0x1DC 0x1E0 0x1E4 0x1E8 0x1EC 0x1F0 0x1F4 0x1F8 0x1FC ) group.long ($2+0x1400)++0x3 line.long 0x0 "REGG5_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x80 0x81 0x82 0x83 0x84 0x85 0x86 0x87 0x88 0x89 0x8A 0x8B 0x8C 0x8D 0x8E 0x8F )(list 0x200 0x204 0x208 0x20C 0x210 0x214 0x218 0x21C 0x220 0x224 0x228 0x22C 0x230 0x234 0x238 0x23C ) group.long ($2+0x1400)++0x3 line.long 0x0 "REGG5_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x90 0x91 0x92 0x93 0x94 0x95 0x96 0x97 0x98 0x99 0x9A 0x9B 0x9C 0x9D 0x9E 0x9F )(list 0x240 0x244 0x248 0x24C 0x250 0x254 0x258 0x25C 0x260 0x264 0x268 0x26C 0x270 0x274 0x278 0x27C ) group.long ($2+0x1400)++0x3 line.long 0x0 "REGG5_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xA0 0xA1 0xA2 0xA3 0xA4 0xA5 0xA6 0xA7 0xA8 0xA9 0xAA 0xAB 0xAC 0xAD 0xAE 0xAF )(list 0x280 0x284 0x288 0x28C 0x290 0x294 0x298 0x29C 0x2A0 0x2A4 0x2A8 0x2AC 0x2B0 0x2B4 0x2B8 0x2BC ) group.long ($2+0x1400)++0x3 line.long 0x0 "REGG5_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xB0 0xB1 0xB2 0xB3 0xB4 0xB5 0xB6 0xB7 0xB8 0xB9 0xBA 0xBB 0xBC 0xBD 0xBE 0xBF )(list 0x2C0 0x2C4 0x2C8 0x2CC 0x2D0 0x2D4 0x2D8 0x2DC 0x2E0 0x2E4 0x2E8 0x2EC 0x2F0 0x2F4 0x2F8 0x2FC ) group.long ($2+0x1400)++0x3 line.long 0x0 "REGG5_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xC0 0xC1 0xC2 0xC3 0xC4 0xC5 0xC6 0xC7 0xC8 0xC9 0xCA 0xCB 0xCC 0xCD 0xCE 0xCF )(list 0x300 0x304 0x308 0x30C 0x310 0x314 0x318 0x31C 0x320 0x324 0x328 0x32C 0x330 0x334 0x338 0x33C ) group.long ($2+0x1400)++0x3 line.long 0x0 "REGG5_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xD0 0xD1 0xD2 0xD3 0xD4 0xD5 0xD6 0xD7 0xD8 0xD9 0xDA 0xDB 0xDC 0xDD 0xDE 0xDF )(list 0x340 0x344 0x348 0x34C 0x350 0x354 0x358 0x35C 0x360 0x364 0x368 0x36C 0x370 0x374 0x378 0x37C ) group.long ($2+0x1400)++0x3 line.long 0x0 "REGG5_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xE0 0xE1 0xE2 0xE3 0xE4 0xE5 0xE6 0xE7 0xE8 0xE9 0xEA 0xEB 0xEC 0xED 0xEE 0xEF )(list 0x380 0x384 0x388 0x38C 0x390 0x394 0x398 0x39C 0x3A0 0x3A4 0x3A8 0x3AC 0x3B0 0x3B4 0x3B8 0x3BC ) group.long ($2+0x1400)++0x3 line.long 0x0 "REGG5_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xF0 0xF1 0xF2 0xF3 0xF4 0xF5 0xF6 0xF7 0xF8 0xF9 0xFA 0xFB 0xFC 0xFD 0xFE 0xFF )(list 0x3C0 0x3C4 0x3C8 0x3CC 0x3D0 0x3D4 0x3D8 0x3DC 0x3E0 0x3E4 0x3E8 0x3EC 0x3F0 0x3F4 0x3F8 0x3FC ) group.long ($2+0x1400)++0x3 line.long 0x0 "REGG5_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x4 0x8 0xC 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C ) group.long ($2+0x1800)++0x3 line.long 0x0 "REGG6_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1A 0x1B 0x1C 0x1D 0x1E 0x1F )(list 0x40 0x44 0x48 0x4C 0x50 0x54 0x58 0x5C 0x60 0x64 0x68 0x6C 0x70 0x74 0x78 0x7C ) group.long ($2+0x1800)++0x3 line.long 0x0 "REGG6_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x20 0x21 0x22 0x23 0x24 0x25 0x26 0x27 0x28 0x29 0x2A 0x2B 0x2C 0x2D 0x2E 0x2F )(list 0x80 0x84 0x88 0x8C 0x90 0x94 0x98 0x9C 0xA0 0xA4 0xA8 0xAC 0xB0 0xB4 0xB8 0xBC ) group.long ($2+0x1800)++0x3 line.long 0x0 "REGG6_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x30 0x31 0x32 0x33 0x34 0x35 0x36 0x37 0x38 0x39 0x3A 0x3B 0x3C 0x3D 0x3E 0x3F )(list 0xC0 0xC4 0xC8 0xCC 0xD0 0xD4 0xD8 0xDC 0xE0 0xE4 0xE8 0xEC 0xF0 0xF4 0xF8 0xFC ) group.long ($2+0x1800)++0x3 line.long 0x0 "REGG6_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x40 0x41 0x42 0x43 0x44 0x45 0x46 0x47 0x48 0x49 0x4A 0x4B 0x4C 0x4D 0x4E 0x4F )(list 0x100 0x104 0x108 0x10C 0x110 0x114 0x118 0x11C 0x120 0x124 0x128 0x12C 0x130 0x134 0x138 0x13C ) group.long ($2+0x1800)++0x3 line.long 0x0 "REGG6_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x50 0x51 0x52 0x53 0x54 0x55 0x56 0x57 0x58 0x59 0x5A 0x5B 0x5C 0x5D 0x5E 0x5F )(list 0x140 0x144 0x148 0x14C 0x150 0x154 0x158 0x15C 0x160 0x164 0x168 0x16C 0x170 0x174 0x178 0x17C ) group.long ($2+0x1800)++0x3 line.long 0x0 "REGG6_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x60 0x61 0x62 0x63 0x64 0x65 0x66 0x67 0x68 0x69 0x6A 0x6B 0x6C 0x6D 0x6E 0x6F )(list 0x180 0x184 0x188 0x18C 0x190 0x194 0x198 0x19C 0x1A0 0x1A4 0x1A8 0x1AC 0x1B0 0x1B4 0x1B8 0x1BC ) group.long ($2+0x1800)++0x3 line.long 0x0 "REGG6_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x70 0x71 0x72 0x73 0x74 0x75 0x76 0x77 0x78 0x79 0x7A 0x7B 0x7C 0x7D 0x7E 0x7F )(list 0x1C0 0x1C4 0x1C8 0x1CC 0x1D0 0x1D4 0x1D8 0x1DC 0x1E0 0x1E4 0x1E8 0x1EC 0x1F0 0x1F4 0x1F8 0x1FC ) group.long ($2+0x1800)++0x3 line.long 0x0 "REGG6_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x80 0x81 0x82 0x83 0x84 0x85 0x86 0x87 0x88 0x89 0x8A 0x8B 0x8C 0x8D 0x8E 0x8F )(list 0x200 0x204 0x208 0x20C 0x210 0x214 0x218 0x21C 0x220 0x224 0x228 0x22C 0x230 0x234 0x238 0x23C ) group.long ($2+0x1800)++0x3 line.long 0x0 "REGG6_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x90 0x91 0x92 0x93 0x94 0x95 0x96 0x97 0x98 0x99 0x9A 0x9B 0x9C 0x9D 0x9E 0x9F )(list 0x240 0x244 0x248 0x24C 0x250 0x254 0x258 0x25C 0x260 0x264 0x268 0x26C 0x270 0x274 0x278 0x27C ) group.long ($2+0x1800)++0x3 line.long 0x0 "REGG6_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xA0 0xA1 0xA2 0xA3 0xA4 0xA5 0xA6 0xA7 0xA8 0xA9 0xAA 0xAB 0xAC 0xAD 0xAE 0xAF )(list 0x280 0x284 0x288 0x28C 0x290 0x294 0x298 0x29C 0x2A0 0x2A4 0x2A8 0x2AC 0x2B0 0x2B4 0x2B8 0x2BC ) group.long ($2+0x1800)++0x3 line.long 0x0 "REGG6_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xB0 0xB1 0xB2 0xB3 0xB4 0xB5 0xB6 0xB7 0xB8 0xB9 0xBA 0xBB 0xBC 0xBD 0xBE 0xBF )(list 0x2C0 0x2C4 0x2C8 0x2CC 0x2D0 0x2D4 0x2D8 0x2DC 0x2E0 0x2E4 0x2E8 0x2EC 0x2F0 0x2F4 0x2F8 0x2FC ) group.long ($2+0x1800)++0x3 line.long 0x0 "REGG6_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xC0 0xC1 0xC2 0xC3 0xC4 0xC5 0xC6 0xC7 0xC8 0xC9 0xCA 0xCB 0xCC 0xCD 0xCE 0xCF )(list 0x300 0x304 0x308 0x30C 0x310 0x314 0x318 0x31C 0x320 0x324 0x328 0x32C 0x330 0x334 0x338 0x33C ) group.long ($2+0x1800)++0x3 line.long 0x0 "REGG6_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xD0 0xD1 0xD2 0xD3 0xD4 0xD5 0xD6 0xD7 0xD8 0xD9 0xDA 0xDB 0xDC 0xDD 0xDE 0xDF )(list 0x340 0x344 0x348 0x34C 0x350 0x354 0x358 0x35C 0x360 0x364 0x368 0x36C 0x370 0x374 0x378 0x37C ) group.long ($2+0x1800)++0x3 line.long 0x0 "REGG6_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xE0 0xE1 0xE2 0xE3 0xE4 0xE5 0xE6 0xE7 0xE8 0xE9 0xEA 0xEB 0xEC 0xED 0xEE 0xEF )(list 0x380 0x384 0x388 0x38C 0x390 0x394 0x398 0x39C 0x3A0 0x3A4 0x3A8 0x3AC 0x3B0 0x3B4 0x3B8 0x3BC ) group.long ($2+0x1800)++0x3 line.long 0x0 "REGG6_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xF0 0xF1 0xF2 0xF3 0xF4 0xF5 0xF6 0xF7 0xF8 0xF9 0xFA 0xFB 0xFC 0xFD 0xFE 0xFF )(list 0x3C0 0x3C4 0x3C8 0x3CC 0x3D0 0x3D4 0x3D8 0x3DC 0x3E0 0x3E4 0x3E8 0x3EC 0x3F0 0x3F4 0x3F8 0x3FC ) group.long ($2+0x1800)++0x3 line.long 0x0 "REGG6_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x4 0x8 0xC 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C ) group.long ($2+0x1C00)++0x3 line.long 0x0 "REGG7_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1A 0x1B 0x1C 0x1D 0x1E 0x1F )(list 0x40 0x44 0x48 0x4C 0x50 0x54 0x58 0x5C 0x60 0x64 0x68 0x6C 0x70 0x74 0x78 0x7C ) group.long ($2+0x1C00)++0x3 line.long 0x0 "REGG7_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x20 0x21 0x22 0x23 0x24 0x25 0x26 0x27 0x28 0x29 0x2A 0x2B 0x2C 0x2D 0x2E 0x2F )(list 0x80 0x84 0x88 0x8C 0x90 0x94 0x98 0x9C 0xA0 0xA4 0xA8 0xAC 0xB0 0xB4 0xB8 0xBC ) group.long ($2+0x1C00)++0x3 line.long 0x0 "REGG7_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x30 0x31 0x32 0x33 0x34 0x35 0x36 0x37 0x38 0x39 0x3A 0x3B 0x3C 0x3D 0x3E 0x3F )(list 0xC0 0xC4 0xC8 0xCC 0xD0 0xD4 0xD8 0xDC 0xE0 0xE4 0xE8 0xEC 0xF0 0xF4 0xF8 0xFC ) group.long ($2+0x1C00)++0x3 line.long 0x0 "REGG7_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x40 0x41 0x42 0x43 0x44 0x45 0x46 0x47 0x48 0x49 0x4A 0x4B 0x4C 0x4D 0x4E 0x4F )(list 0x100 0x104 0x108 0x10C 0x110 0x114 0x118 0x11C 0x120 0x124 0x128 0x12C 0x130 0x134 0x138 0x13C ) group.long ($2+0x1C00)++0x3 line.long 0x0 "REGG7_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x50 0x51 0x52 0x53 0x54 0x55 0x56 0x57 0x58 0x59 0x5A 0x5B 0x5C 0x5D 0x5E 0x5F )(list 0x140 0x144 0x148 0x14C 0x150 0x154 0x158 0x15C 0x160 0x164 0x168 0x16C 0x170 0x174 0x178 0x17C ) group.long ($2+0x1C00)++0x3 line.long 0x0 "REGG7_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x60 0x61 0x62 0x63 0x64 0x65 0x66 0x67 0x68 0x69 0x6A 0x6B 0x6C 0x6D 0x6E 0x6F )(list 0x180 0x184 0x188 0x18C 0x190 0x194 0x198 0x19C 0x1A0 0x1A4 0x1A8 0x1AC 0x1B0 0x1B4 0x1B8 0x1BC ) group.long ($2+0x1C00)++0x3 line.long 0x0 "REGG7_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x70 0x71 0x72 0x73 0x74 0x75 0x76 0x77 0x78 0x79 0x7A 0x7B 0x7C 0x7D 0x7E 0x7F )(list 0x1C0 0x1C4 0x1C8 0x1CC 0x1D0 0x1D4 0x1D8 0x1DC 0x1E0 0x1E4 0x1E8 0x1EC 0x1F0 0x1F4 0x1F8 0x1FC ) group.long ($2+0x1C00)++0x3 line.long 0x0 "REGG7_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x80 0x81 0x82 0x83 0x84 0x85 0x86 0x87 0x88 0x89 0x8A 0x8B 0x8C 0x8D 0x8E 0x8F )(list 0x200 0x204 0x208 0x20C 0x210 0x214 0x218 0x21C 0x220 0x224 0x228 0x22C 0x230 0x234 0x238 0x23C ) group.long ($2+0x1C00)++0x3 line.long 0x0 "REGG7_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x90 0x91 0x92 0x93 0x94 0x95 0x96 0x97 0x98 0x99 0x9A 0x9B 0x9C 0x9D 0x9E 0x9F )(list 0x240 0x244 0x248 0x24C 0x250 0x254 0x258 0x25C 0x260 0x264 0x268 0x26C 0x270 0x274 0x278 0x27C ) group.long ($2+0x1C00)++0x3 line.long 0x0 "REGG7_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xA0 0xA1 0xA2 0xA3 0xA4 0xA5 0xA6 0xA7 0xA8 0xA9 0xAA 0xAB 0xAC 0xAD 0xAE 0xAF )(list 0x280 0x284 0x288 0x28C 0x290 0x294 0x298 0x29C 0x2A0 0x2A4 0x2A8 0x2AC 0x2B0 0x2B4 0x2B8 0x2BC ) group.long ($2+0x1C00)++0x3 line.long 0x0 "REGG7_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xB0 0xB1 0xB2 0xB3 0xB4 0xB5 0xB6 0xB7 0xB8 0xB9 0xBA 0xBB 0xBC 0xBD 0xBE 0xBF )(list 0x2C0 0x2C4 0x2C8 0x2CC 0x2D0 0x2D4 0x2D8 0x2DC 0x2E0 0x2E4 0x2E8 0x2EC 0x2F0 0x2F4 0x2F8 0x2FC ) group.long ($2+0x1C00)++0x3 line.long 0x0 "REGG7_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xC0 0xC1 0xC2 0xC3 0xC4 0xC5 0xC6 0xC7 0xC8 0xC9 0xCA 0xCB 0xCC 0xCD 0xCE 0xCF )(list 0x300 0x304 0x308 0x30C 0x310 0x314 0x318 0x31C 0x320 0x324 0x328 0x32C 0x330 0x334 0x338 0x33C ) group.long ($2+0x1C00)++0x3 line.long 0x0 "REGG7_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xD0 0xD1 0xD2 0xD3 0xD4 0xD5 0xD6 0xD7 0xD8 0xD9 0xDA 0xDB 0xDC 0xDD 0xDE 0xDF )(list 0x340 0x344 0x348 0x34C 0x350 0x354 0x358 0x35C 0x360 0x364 0x368 0x36C 0x370 0x374 0x378 0x37C ) group.long ($2+0x1C00)++0x3 line.long 0x0 "REGG7_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xE0 0xE1 0xE2 0xE3 0xE4 0xE5 0xE6 0xE7 0xE8 0xE9 0xEA 0xEB 0xEC 0xED 0xEE 0xEF )(list 0x380 0x384 0x388 0x38C 0x390 0x394 0x398 0x39C 0x3A0 0x3A4 0x3A8 0x3AC 0x3B0 0x3B4 0x3B8 0x3BC ) group.long ($2+0x1C00)++0x3 line.long 0x0 "REGG7_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xF0 0xF1 0xF2 0xF3 0xF4 0xF5 0xF6 0xF7 0xF8 0xF9 0xFA 0xFB 0xFC 0xFD 0xFE 0xFF )(list 0x3C0 0x3C4 0x3C8 0x3CC 0x3D0 0x3D4 0x3D8 0x3DC 0x3E0 0x3E4 0x3E8 0x3EC 0x3F0 0x3F4 0x3F8 0x3FC ) group.long ($2+0x1C00)++0x3 line.long 0x0 "REGG7_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end group.long 0x2000++0x17 line.long 0x0 "GLB_CTL,This register provides global enable settings for permission control." bitfld.long 0x0 5. "DOM_CFG_LOCK,Lock write for DOM_CFG_MODE bit." "0,1" bitfld.long 0x0 4. "DOM_CFG_MODE,When enabled all the source setting can be configured by master from domain 0 if it is not locked. When disabled only resource manager can configure the permission of the resource." "0,1" bitfld.long 0x0 3. "PERCK_DIS_LOCK,Lock write for PERCK_DIS" "0,1" bitfld.long 0x0 2. "PERCK_DIS,All the permission check disable." "0,1" newline bitfld.long 0x0 1. "DOM_PRO_LOCK,Lock write for DOM_PRO_EN bit." "0,1" bitfld.long 0x0 0. "DOM_PRO_EN,When disabled no domain access permission check" "0,1" line.long 0x4 "RES_MGR,Resource manager register. This regster is used to assign resource manager for global resource access control" bitfld.long 0x4 17. "MID_LOCK,Lock write for MID_EN and MID_LOW and MID_HIG registers." "0,1" bitfld.long 0x4 16. "MID_EN,Master ID check enable" "0,1" bitfld.long 0x4 15. "PRI_PER_LOCK,Lock write for PRI_PER and PRI_PER_EN" "0,1" bitfld.long 0x4 13.--14. "PRI_PER,Resource manager privileged access permission. bit0 for privileged access bit1 for user access" "0,1,2,3" newline bitfld.long 0x4 12. "PRI_PER_EN,Resource manager privileged access permission enable." "0,1" bitfld.long 0x4 11. "SEC_PER_LOCK,Lock for SEC_PER and SEC_PER_LOCK" "0,1" bitfld.long 0x4 9.--10. "SEC_PER,Resource manager secure access permission. bit 0 for secure access bit 1 for non-secure access" "0,1,2,3" bitfld.long 0x4 8. "SEC_PER_EN,Resource manager secure permission enable" "0,1" bitfld.long 0x4 7. "DID_LOCK,Lock write for DID_EN and DID" "0,1" newline hexmask.long.byte 0x4 3.--6. 1. "DID,Resource manager domain ID" bitfld.long 0x4 2. "DID_EN,Resource manager Domain ID enable" "0,1" bitfld.long 0x4 1. "RES_MGR_EN_LOCK,Lock for RES_MGR_EN" "0,1" bitfld.long 0x4 0. "RES_MGR_EN,Resource manager enable. When the bit is disable there is no resource manager." "0,1" line.long 0x8 "RES_MGR_MA0,This register is used to assign master 0~31 as resource manager." hexmask.long 0x8 0.--31. 1. "MID,Assign master 0~31 for resource manager" line.long 0xC "RES_MGR_MA1,This register is used to assign master 32~63 as resource manager." hexmask.long 0xC 0.--31. 1. "MID,Indicate if master 32~63 is resource manager." line.long 0x10 "RES_MGR_MA2,This register is used to assign master 64~95 as resource manager." hexmask.long 0x10 0.--31. 1. "MID,Indicate if master 64~95 is resource manager." line.long 0x14 "RES_MGR_MA3,This register is used to assign master 96~127 as resource manager." hexmask.long 0x14 0.--31. 1. "MID,Indicate if master 96~127 is resource manager." repeat 8. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 )(list 0x0 0x14 0x28 0x3C 0x50 0x64 0x78 0x8C ) group.long ($2+0x2100)++0x3 line.long 0x0 "GRP_MGR_$1,Group Manager Register. This register is used to assign group manager for each domain" bitfld.long 0x0 17. "MID_LOCK,Lock write for MID_EN and MID_LOW and MID_HIG registers." "0,1" bitfld.long 0x0 16. "MID_EN,Master ID check enable" "0,1" bitfld.long 0x0 15. "PRI_PER_LOCK,Lock write for PRI_PER and PRI_PER_EN" "0,1" bitfld.long 0x0 13.--14. "PRI_PER,Group manager privileged access permission. bit0 for privileged access bit1 for user access" "0,1,2,3" newline bitfld.long 0x0 12. "PRI_PER_EN,Group manager privileged access permission enable." "0,1" bitfld.long 0x0 11. "SEC_PER_LOCK,Lock for SEC_PER and SEC_PER_LOCK" "0,1" bitfld.long 0x0 9.--10. "SEC_PER,Group manager secure access permission. bit 0 for secure access bit 1 for non-secure access" "0,1,2,3" bitfld.long 0x0 8. "SEC_PER_EN,Group manager secure permission enable" "0,1" bitfld.long 0x0 7. "DID_LOCK,Lock write for DID_EN and DID" "0,1" newline hexmask.long.byte 0x0 3.--6. 1. "DID,Group manager domain ID" bitfld.long 0x0 2. "DID_EN,Group manager Domain ID enable" "0,1" bitfld.long 0x0 1. "GRP_MGR_EN_LOCK,Lock write for GPR_MGR_EN" "0,1" bitfld.long 0x0 0. "GRP_MGR_EN,Group manager enable. When the bit is disable there is no resource manager." "0,1" repeat.end repeat 8. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 )(list 0x0 0x14 0x28 0x3C 0x50 0x64 0x78 0x8C ) group.long ($2+0x2104)++0x3 line.long 0x0 "GRP_MGR_MA0_$1,Assign master 0~31 for group manager 0" hexmask.long 0x0 0.--31. 1. "MID,Assign master 0~31 for resource manager" repeat.end repeat 8. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 )(list 0x0 0x14 0x28 0x3C 0x50 0x64 0x78 0x8C ) group.long ($2+0x2108)++0x3 line.long 0x0 "GRP_MGR_MA1_$1,Assign master 32~63 for group manager 0" hexmask.long 0x0 0.--31. 1. "MID,Indicate if master 32~63 is resource manager." repeat.end repeat 8. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 )(list 0x0 0x14 0x28 0x3C 0x50 0x64 0x78 0x8C ) group.long ($2+0x210C)++0x3 line.long 0x0 "GRP_MGR_MA2_$1,Assign master 64~95 for group manager 0" hexmask.long 0x0 0.--31. 1. "MID,Indicate if master 64~95 is resource manager." repeat.end repeat 8. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 )(list 0x0 0x14 0x28 0x3C 0x50 0x64 0x78 0x8C ) group.long ($2+0x2110)++0x3 line.long 0x0 "GRP_MGR_MA3_$1,Assign master 96~127 for group manager 0" hexmask.long 0x0 0.--31. 1. "MID,Indicate if master 96~127 is resource manager." repeat.end group.long 0x2200++0x3 line.long 0x0 "DOM_GID_0,Indicate which group domain 0 belong to" bitfld.long 0x0 3. "LOCK,Lock write for GID" "0,1" bitfld.long 0x0 0.--2. "GID,Group ID" "0,1,2,3,4,5,6,7" repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x18 0x30 0x48 0x60 0x78 0x90 0xA8 0xC0 0xD8 0xF0 0x108 0x120 0x138 0x150 0x168 ) group.long ($2+0x2204)++0x3 line.long 0x0 "DOM_OWN_$1,Assign owner for function domain 0." bitfld.long 0x0 17. "MID_LOCK,Lock write for MID_EN and MID_LOW and MID_HIG registers." "0,1" bitfld.long 0x0 16. "MID_EN,Master ID check enable" "0,1" bitfld.long 0x0 15. "PRI_PER_LOCK,Lock write for PRI_PER and PRI_PER_EN" "0,1" bitfld.long 0x0 13.--14. "PRI_PER,Group manager privileged access permission. bit0 for privileged access bit1 for user access" "0,1,2,3" newline bitfld.long 0x0 12. "PRI_PER_EN,Group manager privileged access permission enable." "0,1" bitfld.long 0x0 11. "SEC_PER_LOCK,Lock for SEC_PER and SEC_PER_LOCK" "0,1" bitfld.long 0x0 9.--10. "SEC_PER,Domain owner secure access permission. bit 0 for secure access bit 1 for non-secure access" "0,1,2,3" bitfld.long 0x0 8. "SEC_PER_EN,Domain owner secure permission enable" "0,1" newline bitfld.long 0x0 1. "DOM_OWN_EN_LOCK,Lock for DOM_OWN_EN" "0,1" bitfld.long 0x0 0. "DOM_OWN_EN,Domain owner enable. When the bit is disable there is no domain owner." "0,1" repeat.end repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x18 0x30 0x48 0x60 0x78 0x90 0xA8 0xC0 0xD8 0xF0 0x108 0x120 0x138 0x150 0x168 ) group.long ($2+0x2208)++0x3 line.long 0x0 "DOM_OWN_MA0_$1,Assign master 0~31 for domain owner 0" hexmask.long 0x0 0.--31. 1. "MID,Assign master 0~31 for resource manager" repeat.end repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x18 0x30 0x48 0x60 0x78 0x90 0xA8 0xC0 0xD8 0xF0 0x108 0x120 0x138 0x150 0x168 ) group.long ($2+0x220C)++0x3 line.long 0x0 "DOM_OWN_MA1_$1,Assign master 32~63 for domain owner 0" hexmask.long 0x0 0.--31. 1. "MID,Indicate if master 32~63 is resource manager." repeat.end repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x18 0x30 0x48 0x60 0x78 0x90 0xA8 0xC0 0xD8 0xF0 0x108 0x120 0x138 0x150 0x168 ) group.long ($2+0x2210)++0x3 line.long 0x0 "DOM_OWN_MA2_$1,Assign master 64~95 for domain owner 0" hexmask.long 0x0 0.--31. 1. "MID,Indicate if master 64~95 is resource manager." repeat.end repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x18 0x30 0x48 0x60 0x78 0x90 0xA8 0xC0 0xD8 0xF0 0x108 0x120 0x138 0x150 0x168 ) group.long ($2+0x2214)++0x3 line.long 0x0 "DOM_OWN_MA3_$1,Assign master 96~127 for domain owner 0" hexmask.long 0x0 0.--31. 1. "MID,Indicate if master 96~127 is resource manager." repeat.end group.long 0x2218++0x3 line.long 0x0 "DOM_GID_1,Indicate which group domain 1 belong to" bitfld.long 0x0 3. "LOCK,Lock write for GID" "0,1" bitfld.long 0x0 0.--2. "GID,Group ID" "0,1,2,3,4,5,6,7" group.long 0x2230++0x3 line.long 0x0 "DOM_GID_2,Indicate which group domain 2 belong to" bitfld.long 0x0 3. "LOCK,Lock write for GID" "0,1" bitfld.long 0x0 0.--2. "GID,Group ID" "0,1,2,3,4,5,6,7" group.long 0x2248++0x3 line.long 0x0 "DOM_GID_3,Indicate which group domain 3 belong to" bitfld.long 0x0 3. "LOCK,Lock write for GID" "0,1" bitfld.long 0x0 0.--2. "GID,Group ID" "0,1,2,3,4,5,6,7" group.long 0x2260++0x3 line.long 0x0 "DOM_GID_4,Indicate which group domain 4 belong to" bitfld.long 0x0 3. "LOCK,Lock write for GID" "0,1" bitfld.long 0x0 0.--2. "GID,Group ID" "0,1,2,3,4,5,6,7" group.long 0x2278++0x3 line.long 0x0 "DOM_GID_5,Indicate which group domain 5 belong to" bitfld.long 0x0 3. "LOCK,Lock write for GID" "0,1" bitfld.long 0x0 0.--2. "GID,Group ID" "0,1,2,3,4,5,6,7" group.long 0x2290++0x3 line.long 0x0 "DOM_GID_6,Indicate which group domain 6 belong to" bitfld.long 0x0 3. "LOCK,Lock write for GID" "0,1" bitfld.long 0x0 0.--2. "GID,Group ID" "0,1,2,3,4,5,6,7" group.long 0x22A8++0x3 line.long 0x0 "DOM_GID_7,Indicate which group domain 7 belong to" bitfld.long 0x0 3. "LOCK,Lock write for GID" "0,1" bitfld.long 0x0 0.--2. "GID,Group ID" "0,1,2,3,4,5,6,7" group.long 0x22C0++0x3 line.long 0x0 "DOM_GID_8,Indicate which group domain 8 belong to" bitfld.long 0x0 3. "LOCK,Lock write for GID" "0,1" bitfld.long 0x0 0.--2. "GID,Group ID" "0,1,2,3,4,5,6,7" group.long 0x22D8++0x3 line.long 0x0 "DOM_GID_9,Indicate which group domain 9 belong to" bitfld.long 0x0 3. "LOCK,Lock write for GID" "0,1" bitfld.long 0x0 0.--2. "GID,Group ID" "0,1,2,3,4,5,6,7" group.long 0x22F0++0x3 line.long 0x0 "DOM_GID_10,Indicate which group domain 10 belong to" bitfld.long 0x0 3. "LOCK,Lock write for GID" "0,1" bitfld.long 0x0 0.--2. "GID,Group ID" "0,1,2,3,4,5,6,7" group.long 0x2308++0x3 line.long 0x0 "DOM_GID_11,Indicate which group domain 11 belong to" bitfld.long 0x0 3. "LOCK,Lock write for GID" "0,1" bitfld.long 0x0 0.--2. "GID,Group ID" "0,1,2,3,4,5,6,7" group.long 0x2320++0x3 line.long 0x0 "DOM_GID_12,Indicate which group domain 12 belong to" bitfld.long 0x0 3. "LOCK,Lock write for GID" "0,1" bitfld.long 0x0 0.--2. "GID,Group ID" "0,1,2,3,4,5,6,7" group.long 0x2338++0x3 line.long 0x0 "DOM_GID_13,Indicate which group domain 13 belong to" bitfld.long 0x0 3. "LOCK,Lock write for GID" "0,1" bitfld.long 0x0 0.--2. "GID,Group ID" "0,1,2,3,4,5,6,7" group.long 0x2350++0x3 line.long 0x0 "DOM_GID_14,Indicate which group domain 14 belong to" bitfld.long 0x0 3. "LOCK,Lock write for GID" "0,1" bitfld.long 0x0 0.--2. "GID,Group ID" "0,1,2,3,4,5,6,7" group.long 0x2368++0x3 line.long 0x0 "DOM_GID_15,Indicate which group domain 15 belong to" bitfld.long 0x0 3. "LOCK,Lock write for GID" "0,1" bitfld.long 0x0 0.--2. "GID,Group ID" "0,1,2,3,4,5,6,7" repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x34 0x68 0x9C 0xD0 0x104 0x138 0x16C 0x1A0 0x1D4 0x208 0x23C 0x270 0x2A4 0x2D8 0x30C ) group.long ($2+0x2400)++0x3 line.long 0x0 "DOM_PER0_$1,Domain Permission Control. It can be only configured by resource manager and domain owner." bitfld.long 0x0 31. "DOM7_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 29.--30. "DOM7_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 28. "DOM7_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 27. "DOM6_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 25.--26. "DOM6_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" newline bitfld.long 0x0 24. "DOM6_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 23. "DOM5_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 21.--22. "DOM5_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 20. "DOM5_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 19. "DOM4_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" newline bitfld.long 0x0 17.--18. "DOM4_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM4_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 15. "DOM3_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 13.--14. "DOM3_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 12. "DOM3_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" newline bitfld.long 0x0 11. "DOM2_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 9.--10. "DOM2_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM2_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 7. "DOM1_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 5.--6. "DOM1_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" newline bitfld.long 0x0 4. "DOM1_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 3. "DOM0_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 1.--2. "DOM0_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM0_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" repeat.end repeat 16. (list 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1A 0x1B 0x1C 0x1D 0x1E 0x1F )(list 0x340 0x374 0x3A8 0x3DC 0x410 0x444 0x478 0x4AC 0x4E0 0x514 0x548 0x57C 0x5B0 0x5E4 0x618 0x64C ) group.long ($2+0x2400)++0x3 line.long 0x0 "DOM_PER0_$1,Domain Permission Control. It can be only configured by resource manager and domain owner." bitfld.long 0x0 31. "DOM7_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 29.--30. "DOM7_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 28. "DOM7_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 27. "DOM6_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 25.--26. "DOM6_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" newline bitfld.long 0x0 24. "DOM6_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 23. "DOM5_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 21.--22. "DOM5_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 20. "DOM5_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 19. "DOM4_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" newline bitfld.long 0x0 17.--18. "DOM4_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM4_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 15. "DOM3_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 13.--14. "DOM3_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 12. "DOM3_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" newline bitfld.long 0x0 11. "DOM2_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 9.--10. "DOM2_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM2_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 7. "DOM1_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 5.--6. "DOM1_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" newline bitfld.long 0x0 4. "DOM1_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 3. "DOM0_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 1.--2. "DOM0_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM0_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" repeat.end repeat 16. (list 0x20 0x21 0x22 0x23 0x24 0x25 0x26 0x27 0x28 0x29 0x2A 0x2B 0x2C 0x2D 0x2E 0x2F )(list 0x680 0x6B4 0x6E8 0x71C 0x750 0x784 0x7B8 0x7EC 0x820 0x854 0x888 0x8BC 0x8F0 0x924 0x958 0x98C ) group.long ($2+0x2400)++0x3 line.long 0x0 "DOM_PER0_$1,Domain Permission Control. It can be only configured by resource manager and domain owner." bitfld.long 0x0 31. "DOM7_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 29.--30. "DOM7_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 28. "DOM7_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 27. "DOM6_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 25.--26. "DOM6_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" newline bitfld.long 0x0 24. "DOM6_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 23. "DOM5_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 21.--22. "DOM5_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 20. "DOM5_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 19. "DOM4_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" newline bitfld.long 0x0 17.--18. "DOM4_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM4_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 15. "DOM3_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 13.--14. "DOM3_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 12. "DOM3_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" newline bitfld.long 0x0 11. "DOM2_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 9.--10. "DOM2_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM2_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 7. "DOM1_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 5.--6. "DOM1_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" newline bitfld.long 0x0 4. "DOM1_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 3. "DOM0_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 1.--2. "DOM0_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM0_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" repeat.end repeat 16. (list 0x30 0x31 0x32 0x33 0x34 0x35 0x36 0x37 0x38 0x39 0x3A 0x3B 0x3C 0x3D 0x3E 0x3F )(list 0x9C0 0x9F4 0xA28 0xA5C 0xA90 0xAC4 0xAF8 0xB2C 0xB60 0xB94 0xBC8 0xBFC 0xC30 0xC64 0xC98 0xCCC ) group.long ($2+0x2400)++0x3 line.long 0x0 "DOM_PER0_$1,Domain Permission Control. It can be only configured by resource manager and domain owner." bitfld.long 0x0 31. "DOM7_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 29.--30. "DOM7_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 28. "DOM7_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 27. "DOM6_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 25.--26. "DOM6_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" newline bitfld.long 0x0 24. "DOM6_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 23. "DOM5_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 21.--22. "DOM5_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 20. "DOM5_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 19. "DOM4_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" newline bitfld.long 0x0 17.--18. "DOM4_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM4_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 15. "DOM3_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 13.--14. "DOM3_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 12. "DOM3_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" newline bitfld.long 0x0 11. "DOM2_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 9.--10. "DOM2_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM2_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 7. "DOM1_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 5.--6. "DOM1_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" newline bitfld.long 0x0 4. "DOM1_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 3. "DOM0_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 1.--2. "DOM0_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM0_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" repeat.end repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x34 0x68 0x9C 0xD0 0x104 0x138 0x16C 0x1A0 0x1D4 0x208 0x23C 0x270 0x2A4 0x2D8 0x30C ) group.long ($2+0x2404)++0x3 line.long 0x0 "DOM_PER1_$1,Domain Permission Control. It can be only configured by resource manager and domain owner." bitfld.long 0x0 31. "DOM15_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 29.--30. "DOM15_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 28. "DOM15_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 27. "DOM14_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 25.--26. "DOM14_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" newline bitfld.long 0x0 24. "DOM14_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 23. "DOM13_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 21.--22. "DOM13_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 20. "DOM13_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 19. "DOM12_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" newline bitfld.long 0x0 17.--18. "DOM12_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM12_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 15. "DOM11_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 13.--14. "DOM11_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 12. "DOM11_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" newline bitfld.long 0x0 11. "DOM10_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 9.--10. "DOM10_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM10_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 7. "DOM9_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 5.--6. "DOM9_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" newline bitfld.long 0x0 4. "DOM9_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 3. "DOM8_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 1.--2. "DOM8_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM8_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" repeat.end repeat 16. (list 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1A 0x1B 0x1C 0x1D 0x1E 0x1F )(list 0x340 0x374 0x3A8 0x3DC 0x410 0x444 0x478 0x4AC 0x4E0 0x514 0x548 0x57C 0x5B0 0x5E4 0x618 0x64C ) group.long ($2+0x2404)++0x3 line.long 0x0 "DOM_PER1_$1,Domain Permission Control. It can be only configured by resource manager and domain owner." bitfld.long 0x0 31. "DOM15_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 29.--30. "DOM15_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 28. "DOM15_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 27. "DOM14_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 25.--26. "DOM14_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" newline bitfld.long 0x0 24. "DOM14_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 23. "DOM13_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 21.--22. "DOM13_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 20. "DOM13_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 19. "DOM12_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" newline bitfld.long 0x0 17.--18. "DOM12_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM12_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 15. "DOM11_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 13.--14. "DOM11_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 12. "DOM11_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" newline bitfld.long 0x0 11. "DOM10_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 9.--10. "DOM10_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM10_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 7. "DOM9_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 5.--6. "DOM9_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" newline bitfld.long 0x0 4. "DOM9_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 3. "DOM8_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 1.--2. "DOM8_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM8_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" repeat.end repeat 16. (list 0x20 0x21 0x22 0x23 0x24 0x25 0x26 0x27 0x28 0x29 0x2A 0x2B 0x2C 0x2D 0x2E 0x2F )(list 0x680 0x6B4 0x6E8 0x71C 0x750 0x784 0x7B8 0x7EC 0x820 0x854 0x888 0x8BC 0x8F0 0x924 0x958 0x98C ) group.long ($2+0x2404)++0x3 line.long 0x0 "DOM_PER1_$1,Domain Permission Control. It can be only configured by resource manager and domain owner." bitfld.long 0x0 31. "DOM15_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 29.--30. "DOM15_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 28. "DOM15_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 27. "DOM14_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 25.--26. "DOM14_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" newline bitfld.long 0x0 24. "DOM14_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 23. "DOM13_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 21.--22. "DOM13_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 20. "DOM13_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 19. "DOM12_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" newline bitfld.long 0x0 17.--18. "DOM12_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM12_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 15. "DOM11_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 13.--14. "DOM11_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 12. "DOM11_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" newline bitfld.long 0x0 11. "DOM10_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 9.--10. "DOM10_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM10_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 7. "DOM9_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 5.--6. "DOM9_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" newline bitfld.long 0x0 4. "DOM9_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 3. "DOM8_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 1.--2. "DOM8_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM8_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" repeat.end repeat 16. (list 0x30 0x31 0x32 0x33 0x34 0x35 0x36 0x37 0x38 0x39 0x3A 0x3B 0x3C 0x3D 0x3E 0x3F )(list 0x9C0 0x9F4 0xA28 0xA5C 0xA90 0xAC4 0xAF8 0xB2C 0xB60 0xB94 0xBC8 0xBFC 0xC30 0xC64 0xC98 0xCCC ) group.long ($2+0x2404)++0x3 line.long 0x0 "DOM_PER1_$1,Domain Permission Control. It can be only configured by resource manager and domain owner." bitfld.long 0x0 31. "DOM15_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 29.--30. "DOM15_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 28. "DOM15_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 27. "DOM14_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 25.--26. "DOM14_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" newline bitfld.long 0x0 24. "DOM14_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 23. "DOM13_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 21.--22. "DOM13_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 20. "DOM13_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 19. "DOM12_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" newline bitfld.long 0x0 17.--18. "DOM12_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM12_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 15. "DOM11_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 13.--14. "DOM11_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 12. "DOM11_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" newline bitfld.long 0x0 11. "DOM10_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 9.--10. "DOM10_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM10_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 7. "DOM9_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 5.--6. "DOM9_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" newline bitfld.long 0x0 4. "DOM9_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 3. "DOM8_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 1.--2. "DOM8_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM8_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" repeat.end repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x34 0x68 0x9C 0xD0 0x104 0x138 0x16C 0x1A0 0x1D4 0x208 0x23C 0x270 0x2A4 0x2D8 0x30C ) group.long ($2+0x2408)++0x3 line.long 0x0 "SEC_PER0_$1,This register is only used for resource manager to control secure access permission." bitfld.long 0x0 31. "DOM3_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM3_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM3_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM3_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM2_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM2_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM2_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM2_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM1_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM1_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM1_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM1_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM0_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM0_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM0_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM0_SEC_EN,Domain secure permission control enable" "0,1" repeat.end repeat 16. (list 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1A 0x1B 0x1C 0x1D 0x1E 0x1F )(list 0x340 0x374 0x3A8 0x3DC 0x410 0x444 0x478 0x4AC 0x4E0 0x514 0x548 0x57C 0x5B0 0x5E4 0x618 0x64C ) group.long ($2+0x2408)++0x3 line.long 0x0 "SEC_PER0_$1,This register is only used for resource manager to control secure access permission." bitfld.long 0x0 31. "DOM3_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM3_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM3_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM3_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM2_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM2_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM2_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM2_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM1_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM1_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM1_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM1_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM0_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM0_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM0_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM0_SEC_EN,Domain secure permission control enable" "0,1" repeat.end repeat 16. (list 0x20 0x21 0x22 0x23 0x24 0x25 0x26 0x27 0x28 0x29 0x2A 0x2B 0x2C 0x2D 0x2E 0x2F )(list 0x680 0x6B4 0x6E8 0x71C 0x750 0x784 0x7B8 0x7EC 0x820 0x854 0x888 0x8BC 0x8F0 0x924 0x958 0x98C ) group.long ($2+0x2408)++0x3 line.long 0x0 "SEC_PER0_$1,This register is only used for resource manager to control secure access permission." bitfld.long 0x0 31. "DOM3_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM3_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM3_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM3_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM2_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM2_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM2_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM2_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM1_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM1_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM1_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM1_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM0_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM0_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM0_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM0_SEC_EN,Domain secure permission control enable" "0,1" repeat.end repeat 16. (list 0x30 0x31 0x32 0x33 0x34 0x35 0x36 0x37 0x38 0x39 0x3A 0x3B 0x3C 0x3D 0x3E 0x3F )(list 0x9C0 0x9F4 0xA28 0xA5C 0xA90 0xAC4 0xAF8 0xB2C 0xB60 0xB94 0xBC8 0xBFC 0xC30 0xC64 0xC98 0xCCC ) group.long ($2+0x2408)++0x3 line.long 0x0 "SEC_PER0_$1,This register is only used for resource manager to control secure access permission." bitfld.long 0x0 31. "DOM3_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM3_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM3_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM3_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM2_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM2_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM2_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM2_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM1_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM1_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM1_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM1_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM0_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM0_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM0_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM0_SEC_EN,Domain secure permission control enable" "0,1" repeat.end repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x34 0x68 0x9C 0xD0 0x104 0x138 0x16C 0x1A0 0x1D4 0x208 0x23C 0x270 0x2A4 0x2D8 0x30C ) group.long ($2+0x240C)++0x3 line.long 0x0 "SEC_PER1_$1,This register is only used for resource manager to control secure access permission." bitfld.long 0x0 31. "DOM7_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM7_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM7_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM7_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM6_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM6_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM6_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM6_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM5_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM5_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM5_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM5_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM4_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM4_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM4_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM4_SEC_EN,Domain secure permission control enable" "0,1" repeat.end repeat 16. (list 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1A 0x1B 0x1C 0x1D 0x1E 0x1F )(list 0x340 0x374 0x3A8 0x3DC 0x410 0x444 0x478 0x4AC 0x4E0 0x514 0x548 0x57C 0x5B0 0x5E4 0x618 0x64C ) group.long ($2+0x240C)++0x3 line.long 0x0 "SEC_PER1_$1,This register is only used for resource manager to control secure access permission." bitfld.long 0x0 31. "DOM7_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM7_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM7_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM7_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM6_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM6_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM6_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM6_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM5_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM5_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM5_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM5_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM4_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM4_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM4_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM4_SEC_EN,Domain secure permission control enable" "0,1" repeat.end repeat 16. (list 0x20 0x21 0x22 0x23 0x24 0x25 0x26 0x27 0x28 0x29 0x2A 0x2B 0x2C 0x2D 0x2E 0x2F )(list 0x680 0x6B4 0x6E8 0x71C 0x750 0x784 0x7B8 0x7EC 0x820 0x854 0x888 0x8BC 0x8F0 0x924 0x958 0x98C ) group.long ($2+0x240C)++0x3 line.long 0x0 "SEC_PER1_$1,This register is only used for resource manager to control secure access permission." bitfld.long 0x0 31. "DOM7_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM7_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM7_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM7_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM6_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM6_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM6_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM6_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM5_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM5_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM5_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM5_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM4_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM4_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM4_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM4_SEC_EN,Domain secure permission control enable" "0,1" repeat.end repeat 16. (list 0x30 0x31 0x32 0x33 0x34 0x35 0x36 0x37 0x38 0x39 0x3A 0x3B 0x3C 0x3D 0x3E 0x3F )(list 0x9C0 0x9F4 0xA28 0xA5C 0xA90 0xAC4 0xAF8 0xB2C 0xB60 0xB94 0xBC8 0xBFC 0xC30 0xC64 0xC98 0xCCC ) group.long ($2+0x240C)++0x3 line.long 0x0 "SEC_PER1_$1,This register is only used for resource manager to control secure access permission." bitfld.long 0x0 31. "DOM7_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM7_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM7_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM7_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM6_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM6_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM6_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM6_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM5_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM5_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM5_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM5_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM4_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM4_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM4_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM4_SEC_EN,Domain secure permission control enable" "0,1" repeat.end repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x34 0x68 0x9C 0xD0 0x104 0x138 0x16C 0x1A0 0x1D4 0x208 0x23C 0x270 0x2A4 0x2D8 0x30C ) group.long ($2+0x2410)++0x3 line.long 0x0 "SEC_PER2_$1,This register is only used for resource manager to control secure access permission." bitfld.long 0x0 31. "DOM11_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM11_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM11_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM11_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM10_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM10_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM10_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM10_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM9_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM9_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM9_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM9_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM8_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM8_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM8_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM8_SEC_EN,Domain secure permission control enable" "0,1" repeat.end repeat 16. (list 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1A 0x1B 0x1C 0x1D 0x1E 0x1F )(list 0x340 0x374 0x3A8 0x3DC 0x410 0x444 0x478 0x4AC 0x4E0 0x514 0x548 0x57C 0x5B0 0x5E4 0x618 0x64C ) group.long ($2+0x2410)++0x3 line.long 0x0 "SEC_PER2_$1,This register is only used for resource manager to control secure access permission." bitfld.long 0x0 31. "DOM11_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM11_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM11_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM11_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM10_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM10_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM10_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM10_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM9_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM9_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM9_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM9_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM8_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM8_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM8_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM8_SEC_EN,Domain secure permission control enable" "0,1" repeat.end repeat 16. (list 0x20 0x21 0x22 0x23 0x24 0x25 0x26 0x27 0x28 0x29 0x2A 0x2B 0x2C 0x2D 0x2E 0x2F )(list 0x680 0x6B4 0x6E8 0x71C 0x750 0x784 0x7B8 0x7EC 0x820 0x854 0x888 0x8BC 0x8F0 0x924 0x958 0x98C ) group.long ($2+0x2410)++0x3 line.long 0x0 "SEC_PER2_$1,This register is only used for resource manager to control secure access permission." bitfld.long 0x0 31. "DOM11_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM11_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM11_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM11_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM10_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM10_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM10_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM10_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM9_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM9_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM9_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM9_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM8_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM8_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM8_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM8_SEC_EN,Domain secure permission control enable" "0,1" repeat.end repeat 16. (list 0x30 0x31 0x32 0x33 0x34 0x35 0x36 0x37 0x38 0x39 0x3A 0x3B 0x3C 0x3D 0x3E 0x3F )(list 0x9C0 0x9F4 0xA28 0xA5C 0xA90 0xAC4 0xAF8 0xB2C 0xB60 0xB94 0xBC8 0xBFC 0xC30 0xC64 0xC98 0xCCC ) group.long ($2+0x2410)++0x3 line.long 0x0 "SEC_PER2_$1,This register is only used for resource manager to control secure access permission." bitfld.long 0x0 31. "DOM11_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM11_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM11_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM11_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM10_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM10_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM10_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM10_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM9_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM9_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM9_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM9_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM8_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM8_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM8_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM8_SEC_EN,Domain secure permission control enable" "0,1" repeat.end repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x34 0x68 0x9C 0xD0 0x104 0x138 0x16C 0x1A0 0x1D4 0x208 0x23C 0x270 0x2A4 0x2D8 0x30C ) group.long ($2+0x2414)++0x3 line.long 0x0 "SEC_PER3_$1,This register is only used for resource manager to control secure access permission." bitfld.long 0x0 31. "DOM15_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM15_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM15_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM15_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM14_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM14_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM14_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM14_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM13_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM13_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM13_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM13_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM12_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM12_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM12_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM12_SEC_EN,Domain secure permission control enable" "0,1" repeat.end repeat 16. (list 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1A 0x1B 0x1C 0x1D 0x1E 0x1F )(list 0x340 0x374 0x3A8 0x3DC 0x410 0x444 0x478 0x4AC 0x4E0 0x514 0x548 0x57C 0x5B0 0x5E4 0x618 0x64C ) group.long ($2+0x2414)++0x3 line.long 0x0 "SEC_PER3_$1,This register is only used for resource manager to control secure access permission." bitfld.long 0x0 31. "DOM15_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM15_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM15_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM15_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM14_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM14_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM14_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM14_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM13_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM13_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM13_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM13_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM12_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM12_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM12_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM12_SEC_EN,Domain secure permission control enable" "0,1" repeat.end repeat 16. (list 0x20 0x21 0x22 0x23 0x24 0x25 0x26 0x27 0x28 0x29 0x2A 0x2B 0x2C 0x2D 0x2E 0x2F )(list 0x680 0x6B4 0x6E8 0x71C 0x750 0x784 0x7B8 0x7EC 0x820 0x854 0x888 0x8BC 0x8F0 0x924 0x958 0x98C ) group.long ($2+0x2414)++0x3 line.long 0x0 "SEC_PER3_$1,This register is only used for resource manager to control secure access permission." bitfld.long 0x0 31. "DOM15_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM15_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM15_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM15_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM14_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM14_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM14_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM14_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM13_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM13_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM13_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM13_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM12_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM12_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM12_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM12_SEC_EN,Domain secure permission control enable" "0,1" repeat.end repeat 16. (list 0x30 0x31 0x32 0x33 0x34 0x35 0x36 0x37 0x38 0x39 0x3A 0x3B 0x3C 0x3D 0x3E 0x3F )(list 0x9C0 0x9F4 0xA28 0xA5C 0xA90 0xAC4 0xAF8 0xB2C 0xB60 0xB94 0xBC8 0xBFC 0xC30 0xC64 0xC98 0xCCC ) group.long ($2+0x2414)++0x3 line.long 0x0 "SEC_PER3_$1,This register is only used for resource manager to control secure access permission." bitfld.long 0x0 31. "DOM15_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM15_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM15_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM15_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM14_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM14_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM14_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM14_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM13_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM13_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM13_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM13_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM12_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM12_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM12_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM12_SEC_EN,Domain secure permission control enable" "0,1" repeat.end repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x34 0x68 0x9C 0xD0 0x104 0x138 0x16C 0x1A0 0x1D4 0x208 0x23C 0x270 0x2A4 0x2D8 0x30C ) group.long ($2+0x2418)++0x3 line.long 0x0 "PRI_PER0_$1,This register is only used for resource manager to control privileged access permission." bitfld.long 0x0 31. "DOM3_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM3_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM3_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM3_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM2_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM2_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM2_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM2_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM1_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM1_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM1_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM1_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM0_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM0_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM0_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM0_PRI_EN,Domain privileged permission control enable" "0,1" repeat.end repeat 16. (list 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1A 0x1B 0x1C 0x1D 0x1E 0x1F )(list 0x340 0x374 0x3A8 0x3DC 0x410 0x444 0x478 0x4AC 0x4E0 0x514 0x548 0x57C 0x5B0 0x5E4 0x618 0x64C ) group.long ($2+0x2418)++0x3 line.long 0x0 "PRI_PER0_$1,This register is only used for resource manager to control privileged access permission." bitfld.long 0x0 31. "DOM3_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM3_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM3_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM3_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM2_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM2_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM2_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM2_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM1_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM1_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM1_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM1_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM0_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM0_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM0_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM0_PRI_EN,Domain privileged permission control enable" "0,1" repeat.end repeat 16. (list 0x20 0x21 0x22 0x23 0x24 0x25 0x26 0x27 0x28 0x29 0x2A 0x2B 0x2C 0x2D 0x2E 0x2F )(list 0x680 0x6B4 0x6E8 0x71C 0x750 0x784 0x7B8 0x7EC 0x820 0x854 0x888 0x8BC 0x8F0 0x924 0x958 0x98C ) group.long ($2+0x2418)++0x3 line.long 0x0 "PRI_PER0_$1,This register is only used for resource manager to control privileged access permission." bitfld.long 0x0 31. "DOM3_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM3_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM3_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM3_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM2_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM2_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM2_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM2_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM1_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM1_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM1_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM1_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM0_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM0_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM0_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM0_PRI_EN,Domain privileged permission control enable" "0,1" repeat.end repeat 16. (list 0x30 0x31 0x32 0x33 0x34 0x35 0x36 0x37 0x38 0x39 0x3A 0x3B 0x3C 0x3D 0x3E 0x3F )(list 0x9C0 0x9F4 0xA28 0xA5C 0xA90 0xAC4 0xAF8 0xB2C 0xB60 0xB94 0xBC8 0xBFC 0xC30 0xC64 0xC98 0xCCC ) group.long ($2+0x2418)++0x3 line.long 0x0 "PRI_PER0_$1,This register is only used for resource manager to control privileged access permission." bitfld.long 0x0 31. "DOM3_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM3_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM3_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM3_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM2_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM2_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM2_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM2_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM1_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM1_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM1_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM1_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM0_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM0_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM0_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM0_PRI_EN,Domain privileged permission control enable" "0,1" repeat.end repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x34 0x68 0x9C 0xD0 0x104 0x138 0x16C 0x1A0 0x1D4 0x208 0x23C 0x270 0x2A4 0x2D8 0x30C ) group.long ($2+0x241C)++0x3 line.long 0x0 "PRI_PER1_$1,This register is only used for resource manager to control privileged access permission." bitfld.long 0x0 31. "DOM7_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM7_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM7_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM7_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM6_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM6_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM6_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM6_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM5_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM5_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM5_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM5_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM4_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM4_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM4_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM4_PRI_EN,Domain privileged permission control enable" "0,1" repeat.end repeat 16. (list 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1A 0x1B 0x1C 0x1D 0x1E 0x1F )(list 0x340 0x374 0x3A8 0x3DC 0x410 0x444 0x478 0x4AC 0x4E0 0x514 0x548 0x57C 0x5B0 0x5E4 0x618 0x64C ) group.long ($2+0x241C)++0x3 line.long 0x0 "PRI_PER1_$1,This register is only used for resource manager to control privileged access permission." bitfld.long 0x0 31. "DOM7_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM7_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM7_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM7_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM6_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM6_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM6_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM6_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM5_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM5_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM5_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM5_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM4_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM4_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM4_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM4_PRI_EN,Domain privileged permission control enable" "0,1" repeat.end repeat 16. (list 0x20 0x21 0x22 0x23 0x24 0x25 0x26 0x27 0x28 0x29 0x2A 0x2B 0x2C 0x2D 0x2E 0x2F )(list 0x680 0x6B4 0x6E8 0x71C 0x750 0x784 0x7B8 0x7EC 0x820 0x854 0x888 0x8BC 0x8F0 0x924 0x958 0x98C ) group.long ($2+0x241C)++0x3 line.long 0x0 "PRI_PER1_$1,This register is only used for resource manager to control privileged access permission." bitfld.long 0x0 31. "DOM7_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM7_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM7_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM7_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM6_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM6_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM6_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM6_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM5_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM5_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM5_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM5_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM4_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM4_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM4_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM4_PRI_EN,Domain privileged permission control enable" "0,1" repeat.end repeat 16. (list 0x30 0x31 0x32 0x33 0x34 0x35 0x36 0x37 0x38 0x39 0x3A 0x3B 0x3C 0x3D 0x3E 0x3F )(list 0x9C0 0x9F4 0xA28 0xA5C 0xA90 0xAC4 0xAF8 0xB2C 0xB60 0xB94 0xBC8 0xBFC 0xC30 0xC64 0xC98 0xCCC ) group.long ($2+0x241C)++0x3 line.long 0x0 "PRI_PER1_$1,This register is only used for resource manager to control privileged access permission." bitfld.long 0x0 31. "DOM7_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM7_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM7_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM7_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM6_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM6_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM6_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM6_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM5_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM5_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM5_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM5_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM4_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM4_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM4_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM4_PRI_EN,Domain privileged permission control enable" "0,1" repeat.end repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x34 0x68 0x9C 0xD0 0x104 0x138 0x16C 0x1A0 0x1D4 0x208 0x23C 0x270 0x2A4 0x2D8 0x30C ) group.long ($2+0x2420)++0x3 line.long 0x0 "PRI_PER2_$1,This register is only used for resource manager to control privileged access permission." bitfld.long 0x0 31. "DOM11_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM11_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM11_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM11_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM10_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM10_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM10_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM10_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM9_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM9_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM9_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM9_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM8_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM8_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM8_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM8_PRI_EN,Domain privileged permission control enable" "0,1" repeat.end repeat 16. (list 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1A 0x1B 0x1C 0x1D 0x1E 0x1F )(list 0x340 0x374 0x3A8 0x3DC 0x410 0x444 0x478 0x4AC 0x4E0 0x514 0x548 0x57C 0x5B0 0x5E4 0x618 0x64C ) group.long ($2+0x2420)++0x3 line.long 0x0 "PRI_PER2_$1,This register is only used for resource manager to control privileged access permission." bitfld.long 0x0 31. "DOM11_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM11_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM11_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM11_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM10_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM10_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM10_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM10_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM9_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM9_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM9_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM9_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM8_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM8_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM8_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM8_PRI_EN,Domain privileged permission control enable" "0,1" repeat.end repeat 16. (list 0x20 0x21 0x22 0x23 0x24 0x25 0x26 0x27 0x28 0x29 0x2A 0x2B 0x2C 0x2D 0x2E 0x2F )(list 0x680 0x6B4 0x6E8 0x71C 0x750 0x784 0x7B8 0x7EC 0x820 0x854 0x888 0x8BC 0x8F0 0x924 0x958 0x98C ) group.long ($2+0x2420)++0x3 line.long 0x0 "PRI_PER2_$1,This register is only used for resource manager to control privileged access permission." bitfld.long 0x0 31. "DOM11_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM11_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM11_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM11_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM10_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM10_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM10_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM10_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM9_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM9_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM9_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM9_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM8_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM8_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM8_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM8_PRI_EN,Domain privileged permission control enable" "0,1" repeat.end repeat 16. (list 0x30 0x31 0x32 0x33 0x34 0x35 0x36 0x37 0x38 0x39 0x3A 0x3B 0x3C 0x3D 0x3E 0x3F )(list 0x9C0 0x9F4 0xA28 0xA5C 0xA90 0xAC4 0xAF8 0xB2C 0xB60 0xB94 0xBC8 0xBFC 0xC30 0xC64 0xC98 0xCCC ) group.long ($2+0x2420)++0x3 line.long 0x0 "PRI_PER2_$1,This register is only used for resource manager to control privileged access permission." bitfld.long 0x0 31. "DOM11_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM11_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM11_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM11_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM10_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM10_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM10_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM10_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM9_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM9_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM9_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM9_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM8_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM8_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM8_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM8_PRI_EN,Domain privileged permission control enable" "0,1" repeat.end repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x34 0x68 0x9C 0xD0 0x104 0x138 0x16C 0x1A0 0x1D4 0x208 0x23C 0x270 0x2A4 0x2D8 0x30C ) group.long ($2+0x2424)++0x3 line.long 0x0 "PRI_PER3_$1,This register is only used for resource manager to control privileged access permission." bitfld.long 0x0 31. "DOM15_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM15_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM15_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM15_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM14_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM14_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM14_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM14_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM13_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM13_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM13_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM13_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM12_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM12_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM12_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM12_PRI_EN,Domain privileged permission control enable" "0,1" repeat.end repeat 16. (list 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1A 0x1B 0x1C 0x1D 0x1E 0x1F )(list 0x340 0x374 0x3A8 0x3DC 0x410 0x444 0x478 0x4AC 0x4E0 0x514 0x548 0x57C 0x5B0 0x5E4 0x618 0x64C ) group.long ($2+0x2424)++0x3 line.long 0x0 "PRI_PER3_$1,This register is only used for resource manager to control privileged access permission." bitfld.long 0x0 31. "DOM15_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM15_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM15_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM15_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM14_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM14_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM14_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM14_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM13_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM13_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM13_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM13_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM12_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM12_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM12_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM12_PRI_EN,Domain privileged permission control enable" "0,1" repeat.end repeat 16. (list 0x20 0x21 0x22 0x23 0x24 0x25 0x26 0x27 0x28 0x29 0x2A 0x2B 0x2C 0x2D 0x2E 0x2F )(list 0x680 0x6B4 0x6E8 0x71C 0x750 0x784 0x7B8 0x7EC 0x820 0x854 0x888 0x8BC 0x8F0 0x924 0x958 0x98C ) group.long ($2+0x2424)++0x3 line.long 0x0 "PRI_PER3_$1,This register is only used for resource manager to control privileged access permission." bitfld.long 0x0 31. "DOM15_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM15_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM15_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM15_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM14_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM14_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM14_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM14_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM13_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM13_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM13_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM13_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM12_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM12_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM12_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM12_PRI_EN,Domain privileged permission control enable" "0,1" repeat.end repeat 16. (list 0x30 0x31 0x32 0x33 0x34 0x35 0x36 0x37 0x38 0x39 0x3A 0x3B 0x3C 0x3D 0x3E 0x3F )(list 0x9C0 0x9F4 0xA28 0xA5C 0xA90 0xAC4 0xAF8 0xB2C 0xB60 0xB94 0xBC8 0xBFC 0xC30 0xC64 0xC98 0xCCC ) group.long ($2+0x2424)++0x3 line.long 0x0 "PRI_PER3_$1,This register is only used for resource manager to control privileged access permission." bitfld.long 0x0 31. "DOM15_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM15_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM15_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM15_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM14_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM14_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM14_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM14_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM13_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM13_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM13_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM13_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM12_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM12_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM12_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM12_PRI_EN,Domain privileged permission control enable" "0,1" repeat.end repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x34 0x68 0x9C 0xD0 0x104 0x138 0x16C 0x1A0 0x1D4 0x208 0x23C 0x270 0x2A4 0x2D8 0x30C ) group.long ($2+0x2428)++0x3 line.long 0x0 "DOM_SEC_PER_$1,This register is only used for domain master to control secure access permission. When the domain master write this register. it only changes the secure permission for itself. When the domain master read this register. it gets permission.." bitfld.long 0x0 7. "DOM_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" newline bitfld.long 0x0 0. "DOM_SEC_EN,Domain secure permission control enable" "0,1" repeat.end repeat 16. (list 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1A 0x1B 0x1C 0x1D 0x1E 0x1F )(list 0x340 0x374 0x3A8 0x3DC 0x410 0x444 0x478 0x4AC 0x4E0 0x514 0x548 0x57C 0x5B0 0x5E4 0x618 0x64C ) group.long ($2+0x2428)++0x3 line.long 0x0 "DOM_SEC_PER_$1,This register is only used for domain master to control secure access permission. When the domain master write this register. it only changes the secure permission for itself. When the domain master read this register. it gets permission.." bitfld.long 0x0 7. "DOM_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" newline bitfld.long 0x0 0. "DOM_SEC_EN,Domain secure permission control enable" "0,1" repeat.end repeat 16. (list 0x20 0x21 0x22 0x23 0x24 0x25 0x26 0x27 0x28 0x29 0x2A 0x2B 0x2C 0x2D 0x2E 0x2F )(list 0x680 0x6B4 0x6E8 0x71C 0x750 0x784 0x7B8 0x7EC 0x820 0x854 0x888 0x8BC 0x8F0 0x924 0x958 0x98C ) group.long ($2+0x2428)++0x3 line.long 0x0 "DOM_SEC_PER_$1,This register is only used for domain master to control secure access permission. When the domain master write this register. it only changes the secure permission for itself. When the domain master read this register. it gets permission.." bitfld.long 0x0 7. "DOM_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" newline bitfld.long 0x0 0. "DOM_SEC_EN,Domain secure permission control enable" "0,1" repeat.end repeat 16. (list 0x30 0x31 0x32 0x33 0x34 0x35 0x36 0x37 0x38 0x39 0x3A 0x3B 0x3C 0x3D 0x3E 0x3F )(list 0x9C0 0x9F4 0xA28 0xA5C 0xA90 0xAC4 0xAF8 0xB2C 0xB60 0xB94 0xBC8 0xBFC 0xC30 0xC64 0xC98 0xCCC ) group.long ($2+0x2428)++0x3 line.long 0x0 "DOM_SEC_PER_$1,This register is only used for domain master to control secure access permission. When the domain master write this register. it only changes the secure permission for itself. When the domain master read this register. it gets permission.." bitfld.long 0x0 7. "DOM_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" newline bitfld.long 0x0 0. "DOM_SEC_EN,Domain secure permission control enable" "0,1" repeat.end repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x34 0x68 0x9C 0xD0 0x104 0x138 0x16C 0x1A0 0x1D4 0x208 0x23C 0x270 0x2A4 0x2D8 0x30C ) group.long ($2+0x242C)++0x3 line.long 0x0 "DOM_PRI_PER_$1,This register is only used for domain master to control secure access permission. When the domain master write this register. it only changes the secure permission for itself. When the domain master read this register. it gets permission.." bitfld.long 0x0 7. "DOM_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" newline bitfld.long 0x0 0. "DOM_PRI_EN,Domain privileged permission control enable" "0,1" repeat.end repeat 16. (list 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1A 0x1B 0x1C 0x1D 0x1E 0x1F )(list 0x340 0x374 0x3A8 0x3DC 0x410 0x444 0x478 0x4AC 0x4E0 0x514 0x548 0x57C 0x5B0 0x5E4 0x618 0x64C ) group.long ($2+0x242C)++0x3 line.long 0x0 "DOM_PRI_PER_$1,This register is only used for domain master to control secure access permission. When the domain master write this register. it only changes the secure permission for itself. When the domain master read this register. it gets permission.." bitfld.long 0x0 7. "DOM_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" newline bitfld.long 0x0 0. "DOM_PRI_EN,Domain privileged permission control enable" "0,1" repeat.end repeat 16. (list 0x20 0x21 0x22 0x23 0x24 0x25 0x26 0x27 0x28 0x29 0x2A 0x2B 0x2C 0x2D 0x2E 0x2F )(list 0x680 0x6B4 0x6E8 0x71C 0x750 0x784 0x7B8 0x7EC 0x820 0x854 0x888 0x8BC 0x8F0 0x924 0x958 0x98C ) group.long ($2+0x242C)++0x3 line.long 0x0 "DOM_PRI_PER_$1,This register is only used for domain master to control secure access permission. When the domain master write this register. it only changes the secure permission for itself. When the domain master read this register. it gets permission.." bitfld.long 0x0 7. "DOM_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" newline bitfld.long 0x0 0. "DOM_PRI_EN,Domain privileged permission control enable" "0,1" repeat.end repeat 16. (list 0x30 0x31 0x32 0x33 0x34 0x35 0x36 0x37 0x38 0x39 0x3A 0x3B 0x3C 0x3D 0x3E 0x3F )(list 0x9C0 0x9F4 0xA28 0xA5C 0xA90 0xAC4 0xAF8 0xB2C 0xB60 0xB94 0xBC8 0xBFC 0xC30 0xC64 0xC98 0xCCC ) group.long ($2+0x242C)++0x3 line.long 0x0 "DOM_PRI_PER_$1,This register is only used for domain master to control secure access permission. When the domain master write this register. it only changes the secure permission for itself. When the domain master read this register. it gets permission.." bitfld.long 0x0 7. "DOM_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" newline bitfld.long 0x0 0. "DOM_PRI_EN,Domain privileged permission control enable" "0,1" repeat.end repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x34 0x68 0x9C 0xD0 0x104 0x138 0x16C 0x1A0 0x1D4 0x208 0x23C 0x270 0x2A4 0x2D8 0x30C ) group.long ($2+0x2430)++0x3 line.long 0x0 "DOM_ASSIGN_$1,Use to assign domain for accessing DOM_SEC_PER and DOM_PRI_PER register. Only resource manager. group manager and domain owner can access this register. For write. group manager must write its owen domain ID. otherwise write accessing will.." hexmask.long.byte 0x0 0.--3. 1. "DID,accessing DOM_SEC_PER and DOM_PRI_PER register" repeat.end repeat 16. (list 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1A 0x1B 0x1C 0x1D 0x1E 0x1F )(list 0x340 0x374 0x3A8 0x3DC 0x410 0x444 0x478 0x4AC 0x4E0 0x514 0x548 0x57C 0x5B0 0x5E4 0x618 0x64C ) group.long ($2+0x2430)++0x3 line.long 0x0 "DOM_ASSIGN_$1,Use to assign domain for accessing DOM_SEC_PER and DOM_PRI_PER register. Only resource manager. group manager and domain owner can access this register. For write. group manager must write its owen domain ID. otherwise write accessing will.." hexmask.long.byte 0x0 0.--3. 1. "DID,accessing DOM_SEC_PER and DOM_PRI_PER register" repeat.end repeat 16. (list 0x20 0x21 0x22 0x23 0x24 0x25 0x26 0x27 0x28 0x29 0x2A 0x2B 0x2C 0x2D 0x2E 0x2F )(list 0x680 0x6B4 0x6E8 0x71C 0x750 0x784 0x7B8 0x7EC 0x820 0x854 0x888 0x8BC 0x8F0 0x924 0x958 0x98C ) group.long ($2+0x2430)++0x3 line.long 0x0 "DOM_ASSIGN_$1,Use to assign domain for accessing DOM_SEC_PER and DOM_PRI_PER register. Only resource manager. group manager and domain owner can access this register. For write. group manager must write its owen domain ID. otherwise write accessing will.." hexmask.long.byte 0x0 0.--3. 1. "DID,accessing DOM_SEC_PER and DOM_PRI_PER register" repeat.end repeat 16. (list 0x30 0x31 0x32 0x33 0x34 0x35 0x36 0x37 0x38 0x39 0x3A 0x3B 0x3C 0x3D 0x3E 0x3F )(list 0x9C0 0x9F4 0xA28 0xA5C 0xA90 0xAC4 0xAF8 0xB2C 0xB60 0xB94 0xBC8 0xBFC 0xC30 0xC64 0xC98 0xCCC ) group.long ($2+0x2430)++0x3 line.long 0x0 "DOM_ASSIGN_$1,Use to assign domain for accessing DOM_SEC_PER and DOM_PRI_PER register. Only resource manager. group manager and domain owner can access this register. For write. group manager must write its owen domain ID. otherwise write accessing will.." hexmask.long.byte 0x0 0.--3. 1. "DID,accessing DOM_SEC_PER and DOM_PRI_PER register" repeat.end repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x38 0x70 0xA8 0xE0 0x118 0x150 0x188 0x1C0 0x1F8 0x230 0x268 0x2A0 0x2D8 0x310 0x348 ) group.long ($2+0x3100)++0x3 line.long 0x0 "RGN_DOM_$1,Assign domain for peripheral. It can be only configured by resource and group manager" bitfld.long 0x0 31. "LOCK,When this bit is set lock write for all the bits in the register." "0,1" bitfld.long 0x0 4. "SET,Set together with DID would change permission of this resource to following setting: 1) Domain access control enabled. 2) Read/Write allowed for the domain owner. 3) Read/Write not allowed for all the other domains. If this bit is not set only DID.." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Assign domain for peripheral" repeat.end repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x38 0x70 0xA8 0xE0 0x118 0x150 0x188 0x1C0 0x1F8 0x230 0x268 0x2A0 0x2D8 0x310 0x348 ) group.long ($2+0x3104)++0x3 line.long 0x0 "RGN_DOM_PER0_$1,Domain Permission Control. It can be only configured by resource manager and domain owner." bitfld.long 0x0 31. "DOM7_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 29.--30. "DOM7_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 28. "DOM7_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 27. "DOM6_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 25.--26. "DOM6_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" newline bitfld.long 0x0 24. "DOM6_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 23. "DOM5_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 21.--22. "DOM5_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 20. "DOM5_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 19. "DOM4_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" newline bitfld.long 0x0 17.--18. "DOM4_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM4_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 15. "DOM3_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 13.--14. "DOM3_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 12. "DOM3_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" newline bitfld.long 0x0 11. "DOM2_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 9.--10. "DOM2_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM2_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 7. "DOM1_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 5.--6. "DOM1_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" newline bitfld.long 0x0 4. "DOM1_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 3. "DOM0_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 1.--2. "DOM0_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM0_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" repeat.end repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x38 0x70 0xA8 0xE0 0x118 0x150 0x188 0x1C0 0x1F8 0x230 0x268 0x2A0 0x2D8 0x310 0x348 ) group.long ($2+0x3108)++0x3 line.long 0x0 "RGN_DOM_PER1_$1,Domain Permission Control. It can be only configured by resource manager and domain owner." bitfld.long 0x0 31. "DOM15_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 29.--30. "DOM15_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 28. "DOM15_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 27. "DOM14_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 25.--26. "DOM14_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" newline bitfld.long 0x0 24. "DOM14_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 23. "DOM13_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 21.--22. "DOM13_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 20. "DOM13_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 19. "DOM12_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" newline bitfld.long 0x0 17.--18. "DOM12_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM12_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 15. "DOM11_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 13.--14. "DOM11_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 12. "DOM11_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" newline bitfld.long 0x0 11. "DOM10_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 9.--10. "DOM10_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM10_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 7. "DOM9_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 5.--6. "DOM9_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" newline bitfld.long 0x0 4. "DOM9_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 3. "DOM8_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 1.--2. "DOM8_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM8_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" repeat.end repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x38 0x70 0xA8 0xE0 0x118 0x150 0x188 0x1C0 0x1F8 0x230 0x268 0x2A0 0x2D8 0x310 0x348 ) group.long ($2+0x310C)++0x3 line.long 0x0 "RGN_SEC_PER0_$1,This register is only used for resource manager to control secure access permission." bitfld.long 0x0 31. "DOM3_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM3_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM3_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM3_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM2_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM2_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM2_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM2_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM1_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM1_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM1_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM1_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM0_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM0_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM0_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM0_SEC_EN,Domain secure permission control enable" "0,1" repeat.end repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x38 0x70 0xA8 0xE0 0x118 0x150 0x188 0x1C0 0x1F8 0x230 0x268 0x2A0 0x2D8 0x310 0x348 ) group.long ($2+0x3110)++0x3 line.long 0x0 "RGN_SEC_PER1_$1,This register is only used for resource manager to control secure access permission." bitfld.long 0x0 31. "DOM7_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM7_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM7_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM7_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM6_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM6_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM6_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM6_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM5_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM5_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM5_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM5_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM4_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM4_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM4_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM4_SEC_EN,Domain secure permission control enable" "0,1" repeat.end repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x38 0x70 0xA8 0xE0 0x118 0x150 0x188 0x1C0 0x1F8 0x230 0x268 0x2A0 0x2D8 0x310 0x348 ) group.long ($2+0x3114)++0x3 line.long 0x0 "RGN_SEC_PER2_$1,This register is only used for resource manager to control secure access permission." bitfld.long 0x0 31. "DOM11_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM11_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM11_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM11_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM10_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM10_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM10_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM10_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM9_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM9_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM9_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM9_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM8_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM8_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM8_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM8_SEC_EN,Domain secure permission control enable" "0,1" repeat.end repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x38 0x70 0xA8 0xE0 0x118 0x150 0x188 0x1C0 0x1F8 0x230 0x268 0x2A0 0x2D8 0x310 0x348 ) group.long ($2+0x3118)++0x3 line.long 0x0 "RGN_SEC_PER3_$1,This register is only used for resource manager to control secure access permission." bitfld.long 0x0 31. "DOM15_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM15_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM15_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM15_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM14_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM14_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM14_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM14_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM13_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM13_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM13_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM13_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM12_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM12_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM12_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM12_SEC_EN,Domain secure permission control enable" "0,1" repeat.end repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x38 0x70 0xA8 0xE0 0x118 0x150 0x188 0x1C0 0x1F8 0x230 0x268 0x2A0 0x2D8 0x310 0x348 ) group.long ($2+0x311C)++0x3 line.long 0x0 "RGN_PRI_PER0_$1,This register is only used for resource manager to control privileged access permission." bitfld.long 0x0 31. "DOM3_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM3_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM3_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM3_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM2_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM2_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM2_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM2_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM1_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM1_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM1_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM1_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM0_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM0_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM0_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM0_PRI_EN,Domain privileged permission control enable" "0,1" repeat.end repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x38 0x70 0xA8 0xE0 0x118 0x150 0x188 0x1C0 0x1F8 0x230 0x268 0x2A0 0x2D8 0x310 0x348 ) group.long ($2+0x3120)++0x3 line.long 0x0 "RGN_PRI_PER1_$1,This register is only used for resource manager to control privileged access permission." bitfld.long 0x0 31. "DOM7_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM7_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM7_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM7_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM6_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM6_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM6_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM6_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM5_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM5_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM5_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM5_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM4_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM4_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM4_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM4_PRI_EN,Domain privileged permission control enable" "0,1" repeat.end repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x38 0x70 0xA8 0xE0 0x118 0x150 0x188 0x1C0 0x1F8 0x230 0x268 0x2A0 0x2D8 0x310 0x348 ) group.long ($2+0x3124)++0x3 line.long 0x0 "RGN_PRI_PER2_$1,This register is only used for resource manager to control privileged access permission." bitfld.long 0x0 31. "DOM11_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM11_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM11_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM11_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM10_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM10_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM10_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM10_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM9_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM9_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM9_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM9_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM8_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM8_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM8_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM8_PRI_EN,Domain privileged permission control enable" "0,1" repeat.end repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x38 0x70 0xA8 0xE0 0x118 0x150 0x188 0x1C0 0x1F8 0x230 0x268 0x2A0 0x2D8 0x310 0x348 ) group.long ($2+0x3128)++0x3 line.long 0x0 "RGN_PRI_PER3_$1,This register is only used for resource manager to control privileged access permission." bitfld.long 0x0 31. "DOM15_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM15_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM15_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM15_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM14_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM14_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM14_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM14_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM13_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM13_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM13_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM13_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM12_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM12_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM12_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM12_PRI_EN,Domain privileged permission control enable" "0,1" repeat.end repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x38 0x70 0xA8 0xE0 0x118 0x150 0x188 0x1C0 0x1F8 0x230 0x268 0x2A0 0x2D8 0x310 0x348 ) group.long ($2+0x312C)++0x3 line.long 0x0 "RGN_DOM_SEC_PER_$1,This register is only used for domain master to control secure access permission. When the domain master write this register. it only changes the secure permission for itself. When the domain master read this register. it gets.." bitfld.long 0x0 7. "DOM_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" newline bitfld.long 0x0 0. "DOM_SEC_EN,Domain secure permission control enable" "0,1" repeat.end repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x38 0x70 0xA8 0xE0 0x118 0x150 0x188 0x1C0 0x1F8 0x230 0x268 0x2A0 0x2D8 0x310 0x348 ) group.long ($2+0x3130)++0x3 line.long 0x0 "RGN_DOM_PRI_PER_$1,This register is only used for domain master to control secure access permission. When the domain master write this register. it only changes the secure permission for itself. When the domain master read this register. it gets.." bitfld.long 0x0 7. "DOM_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" newline bitfld.long 0x0 0. "DOM_PRI_EN,Domain privileged permission control enable" "0,1" repeat.end repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x38 0x70 0xA8 0xE0 0x118 0x150 0x188 0x1C0 0x1F8 0x230 0x268 0x2A0 0x2D8 0x310 0x348 ) group.long ($2+0x3134)++0x3 line.long 0x0 "RGN_DOM_ASSIGN_$1,Use to assign domain for accessing DOM_SEC_PER and DOM_PRI_PER register. Only resource manager. group manager and domain owner can access this register. For write. group manager must write its owen domain ID. otherwise write accessing.." hexmask.long.byte 0x0 0.--3. 1. "DID,accessing DOM_SEC_PER and DOM_PRI_PER register" repeat.end tree.end tree "RPC_SAFETY_RSTGEN" base ad:0x3CC00000 repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x4 0x8 0xC 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C ) group.long ($2)++0x3 line.long 0x0 "REGG0_DOM_$1,Assign domain for CKGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1A 0x1B 0x1C 0x1D 0x1E 0x1F )(list 0x40 0x44 0x48 0x4C 0x50 0x54 0x58 0x5C 0x60 0x64 0x68 0x6C 0x70 0x74 0x78 0x7C ) group.long ($2)++0x3 line.long 0x0 "REGG0_DOM_$1,Assign domain for CKGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x20 0x21 0x22 0x23 0x24 0x25 0x26 0x27 0x28 0x29 0x2A 0x2B 0x2C 0x2D 0x2E 0x2F )(list 0x80 0x84 0x88 0x8C 0x90 0x94 0x98 0x9C 0xA0 0xA4 0xA8 0xAC 0xB0 0xB4 0xB8 0xBC ) group.long ($2)++0x3 line.long 0x0 "REGG0_DOM_$1,Assign domain for CKGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x30 0x31 0x32 0x33 0x34 0x35 0x36 0x37 0x38 0x39 0x3A 0x3B 0x3C 0x3D 0x3E 0x3F )(list 0xC0 0xC4 0xC8 0xCC 0xD0 0xD4 0xD8 0xDC 0xE0 0xE4 0xE8 0xEC 0xF0 0xF4 0xF8 0xFC ) group.long ($2)++0x3 line.long 0x0 "REGG0_DOM_$1,Assign domain for CKGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x40 0x41 0x42 0x43 0x44 0x45 0x46 0x47 0x48 0x49 0x4A 0x4B 0x4C 0x4D 0x4E 0x4F )(list 0x100 0x104 0x108 0x10C 0x110 0x114 0x118 0x11C 0x120 0x124 0x128 0x12C 0x130 0x134 0x138 0x13C ) group.long ($2)++0x3 line.long 0x0 "REGG0_DOM_$1,Assign domain for CKGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x50 0x51 0x52 0x53 0x54 0x55 0x56 0x57 0x58 0x59 0x5A 0x5B 0x5C 0x5D 0x5E 0x5F )(list 0x140 0x144 0x148 0x14C 0x150 0x154 0x158 0x15C 0x160 0x164 0x168 0x16C 0x170 0x174 0x178 0x17C ) group.long ($2)++0x3 line.long 0x0 "REGG0_DOM_$1,Assign domain for CKGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x60 0x61 0x62 0x63 0x64 0x65 0x66 0x67 0x68 0x69 0x6A 0x6B 0x6C 0x6D 0x6E 0x6F )(list 0x180 0x184 0x188 0x18C 0x190 0x194 0x198 0x19C 0x1A0 0x1A4 0x1A8 0x1AC 0x1B0 0x1B4 0x1B8 0x1BC ) group.long ($2)++0x3 line.long 0x0 "REGG0_DOM_$1,Assign domain for CKGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x70 0x71 0x72 0x73 0x74 0x75 0x76 0x77 0x78 0x79 0x7A 0x7B 0x7C 0x7D 0x7E 0x7F )(list 0x1C0 0x1C4 0x1C8 0x1CC 0x1D0 0x1D4 0x1D8 0x1DC 0x1E0 0x1E4 0x1E8 0x1EC 0x1F0 0x1F4 0x1F8 0x1FC ) group.long ($2)++0x3 line.long 0x0 "REGG0_DOM_$1,Assign domain for CKGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x80 0x81 0x82 0x83 0x84 0x85 0x86 0x87 0x88 0x89 0x8A 0x8B 0x8C 0x8D 0x8E 0x8F )(list 0x200 0x204 0x208 0x20C 0x210 0x214 0x218 0x21C 0x220 0x224 0x228 0x22C 0x230 0x234 0x238 0x23C ) group.long ($2)++0x3 line.long 0x0 "REGG0_DOM_$1,Assign domain for CKGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x90 0x91 0x92 0x93 0x94 0x95 0x96 0x97 0x98 0x99 0x9A 0x9B 0x9C 0x9D 0x9E 0x9F )(list 0x240 0x244 0x248 0x24C 0x250 0x254 0x258 0x25C 0x260 0x264 0x268 0x26C 0x270 0x274 0x278 0x27C ) group.long ($2)++0x3 line.long 0x0 "REGG0_DOM_$1,Assign domain for CKGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xA0 0xA1 0xA2 0xA3 0xA4 0xA5 0xA6 0xA7 0xA8 0xA9 0xAA 0xAB 0xAC 0xAD 0xAE 0xAF )(list 0x280 0x284 0x288 0x28C 0x290 0x294 0x298 0x29C 0x2A0 0x2A4 0x2A8 0x2AC 0x2B0 0x2B4 0x2B8 0x2BC ) group.long ($2)++0x3 line.long 0x0 "REGG0_DOM_$1,Assign domain for CKGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xB0 0xB1 0xB2 0xB3 0xB4 0xB5 0xB6 0xB7 0xB8 0xB9 0xBA 0xBB 0xBC 0xBD 0xBE 0xBF )(list 0x2C0 0x2C4 0x2C8 0x2CC 0x2D0 0x2D4 0x2D8 0x2DC 0x2E0 0x2E4 0x2E8 0x2EC 0x2F0 0x2F4 0x2F8 0x2FC ) group.long ($2)++0x3 line.long 0x0 "REGG0_DOM_$1,Assign domain for CKGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xC0 0xC1 0xC2 0xC3 0xC4 0xC5 0xC6 0xC7 0xC8 0xC9 0xCA 0xCB 0xCC 0xCD 0xCE 0xCF )(list 0x300 0x304 0x308 0x30C 0x310 0x314 0x318 0x31C 0x320 0x324 0x328 0x32C 0x330 0x334 0x338 0x33C ) group.long ($2)++0x3 line.long 0x0 "REGG0_DOM_$1,Assign domain for CKGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xD0 0xD1 0xD2 0xD3 0xD4 0xD5 0xD6 0xD7 0xD8 0xD9 0xDA 0xDB 0xDC 0xDD 0xDE 0xDF )(list 0x340 0x344 0x348 0x34C 0x350 0x354 0x358 0x35C 0x360 0x364 0x368 0x36C 0x370 0x374 0x378 0x37C ) group.long ($2)++0x3 line.long 0x0 "REGG0_DOM_$1,Assign domain for CKGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xE0 0xE1 0xE2 0xE3 0xE4 0xE5 0xE6 0xE7 0xE8 0xE9 0xEA 0xEB 0xEC 0xED 0xEE 0xEF )(list 0x380 0x384 0x388 0x38C 0x390 0x394 0x398 0x39C 0x3A0 0x3A4 0x3A8 0x3AC 0x3B0 0x3B4 0x3B8 0x3BC ) group.long ($2)++0x3 line.long 0x0 "REGG0_DOM_$1,Assign domain for CKGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xF0 0xF1 0xF2 0xF3 0xF4 0xF5 0xF6 0xF7 0xF8 0xF9 0xFA 0xFB 0xFC 0xFD 0xFE 0xFF )(list 0x3C0 0x3C4 0x3C8 0x3CC 0x3D0 0x3D4 0x3D8 0x3DC 0x3E0 0x3E4 0x3E8 0x3EC 0x3F0 0x3F4 0x3F8 0x3FC ) group.long ($2)++0x3 line.long 0x0 "REGG0_DOM_$1,Assign domain for CKGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x4 0x8 0xC 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C ) group.long ($2+0x400)++0x3 line.long 0x0 "REGG1_DOM_$1,Assign domain for CKGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1A 0x1B 0x1C 0x1D 0x1E 0x1F )(list 0x40 0x44 0x48 0x4C 0x50 0x54 0x58 0x5C 0x60 0x64 0x68 0x6C 0x70 0x74 0x78 0x7C ) group.long ($2+0x400)++0x3 line.long 0x0 "REGG1_DOM_$1,Assign domain for CKGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x20 0x21 0x22 0x23 0x24 0x25 0x26 0x27 0x28 0x29 0x2A 0x2B 0x2C 0x2D 0x2E 0x2F )(list 0x80 0x84 0x88 0x8C 0x90 0x94 0x98 0x9C 0xA0 0xA4 0xA8 0xAC 0xB0 0xB4 0xB8 0xBC ) group.long ($2+0x400)++0x3 line.long 0x0 "REGG1_DOM_$1,Assign domain for CKGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x30 0x31 0x32 0x33 0x34 0x35 0x36 0x37 0x38 0x39 0x3A 0x3B 0x3C 0x3D 0x3E 0x3F )(list 0xC0 0xC4 0xC8 0xCC 0xD0 0xD4 0xD8 0xDC 0xE0 0xE4 0xE8 0xEC 0xF0 0xF4 0xF8 0xFC ) group.long ($2+0x400)++0x3 line.long 0x0 "REGG1_DOM_$1,Assign domain for CKGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x40 0x41 0x42 0x43 0x44 0x45 0x46 0x47 0x48 0x49 0x4A 0x4B 0x4C 0x4D 0x4E 0x4F )(list 0x100 0x104 0x108 0x10C 0x110 0x114 0x118 0x11C 0x120 0x124 0x128 0x12C 0x130 0x134 0x138 0x13C ) group.long ($2+0x400)++0x3 line.long 0x0 "REGG1_DOM_$1,Assign domain for CKGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x50 0x51 0x52 0x53 0x54 0x55 0x56 0x57 0x58 0x59 0x5A 0x5B 0x5C 0x5D 0x5E 0x5F )(list 0x140 0x144 0x148 0x14C 0x150 0x154 0x158 0x15C 0x160 0x164 0x168 0x16C 0x170 0x174 0x178 0x17C ) group.long ($2+0x400)++0x3 line.long 0x0 "REGG1_DOM_$1,Assign domain for CKGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x60 0x61 0x62 0x63 0x64 0x65 0x66 0x67 0x68 0x69 0x6A 0x6B 0x6C 0x6D 0x6E 0x6F )(list 0x180 0x184 0x188 0x18C 0x190 0x194 0x198 0x19C 0x1A0 0x1A4 0x1A8 0x1AC 0x1B0 0x1B4 0x1B8 0x1BC ) group.long ($2+0x400)++0x3 line.long 0x0 "REGG1_DOM_$1,Assign domain for CKGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x70 0x71 0x72 0x73 0x74 0x75 0x76 0x77 0x78 0x79 0x7A 0x7B 0x7C 0x7D 0x7E 0x7F )(list 0x1C0 0x1C4 0x1C8 0x1CC 0x1D0 0x1D4 0x1D8 0x1DC 0x1E0 0x1E4 0x1E8 0x1EC 0x1F0 0x1F4 0x1F8 0x1FC ) group.long ($2+0x400)++0x3 line.long 0x0 "REGG1_DOM_$1,Assign domain for CKGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x80 0x81 0x82 0x83 0x84 0x85 0x86 0x87 0x88 0x89 0x8A 0x8B 0x8C 0x8D 0x8E 0x8F )(list 0x200 0x204 0x208 0x20C 0x210 0x214 0x218 0x21C 0x220 0x224 0x228 0x22C 0x230 0x234 0x238 0x23C ) group.long ($2+0x400)++0x3 line.long 0x0 "REGG1_DOM_$1,Assign domain for CKGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x90 0x91 0x92 0x93 0x94 0x95 0x96 0x97 0x98 0x99 0x9A 0x9B 0x9C 0x9D 0x9E 0x9F )(list 0x240 0x244 0x248 0x24C 0x250 0x254 0x258 0x25C 0x260 0x264 0x268 0x26C 0x270 0x274 0x278 0x27C ) group.long ($2+0x400)++0x3 line.long 0x0 "REGG1_DOM_$1,Assign domain for CKGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xA0 0xA1 0xA2 0xA3 0xA4 0xA5 0xA6 0xA7 0xA8 0xA9 0xAA 0xAB 0xAC 0xAD 0xAE 0xAF )(list 0x280 0x284 0x288 0x28C 0x290 0x294 0x298 0x29C 0x2A0 0x2A4 0x2A8 0x2AC 0x2B0 0x2B4 0x2B8 0x2BC ) group.long ($2+0x400)++0x3 line.long 0x0 "REGG1_DOM_$1,Assign domain for CKGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xB0 0xB1 0xB2 0xB3 0xB4 0xB5 0xB6 0xB7 0xB8 0xB9 0xBA 0xBB 0xBC 0xBD 0xBE 0xBF )(list 0x2C0 0x2C4 0x2C8 0x2CC 0x2D0 0x2D4 0x2D8 0x2DC 0x2E0 0x2E4 0x2E8 0x2EC 0x2F0 0x2F4 0x2F8 0x2FC ) group.long ($2+0x400)++0x3 line.long 0x0 "REGG1_DOM_$1,Assign domain for CKGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xC0 0xC1 0xC2 0xC3 0xC4 0xC5 0xC6 0xC7 0xC8 0xC9 0xCA 0xCB 0xCC 0xCD 0xCE 0xCF )(list 0x300 0x304 0x308 0x30C 0x310 0x314 0x318 0x31C 0x320 0x324 0x328 0x32C 0x330 0x334 0x338 0x33C ) group.long ($2+0x400)++0x3 line.long 0x0 "REGG1_DOM_$1,Assign domain for CKGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xD0 0xD1 0xD2 0xD3 0xD4 0xD5 0xD6 0xD7 0xD8 0xD9 0xDA 0xDB 0xDC 0xDD 0xDE 0xDF )(list 0x340 0x344 0x348 0x34C 0x350 0x354 0x358 0x35C 0x360 0x364 0x368 0x36C 0x370 0x374 0x378 0x37C ) group.long ($2+0x400)++0x3 line.long 0x0 "REGG1_DOM_$1,Assign domain for CKGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xE0 0xE1 0xE2 0xE3 0xE4 0xE5 0xE6 0xE7 0xE8 0xE9 0xEA 0xEB 0xEC 0xED 0xEE 0xEF )(list 0x380 0x384 0x388 0x38C 0x390 0x394 0x398 0x39C 0x3A0 0x3A4 0x3A8 0x3AC 0x3B0 0x3B4 0x3B8 0x3BC ) group.long ($2+0x400)++0x3 line.long 0x0 "REGG1_DOM_$1,Assign domain for CKGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xF0 0xF1 0xF2 0xF3 0xF4 0xF5 0xF6 0xF7 0xF8 0xF9 0xFA 0xFB 0xFC 0xFD 0xFE 0xFF )(list 0x3C0 0x3C4 0x3C8 0x3CC 0x3D0 0x3D4 0x3D8 0x3DC 0x3E0 0x3E4 0x3E8 0x3EC 0x3F0 0x3F4 0x3F8 0x3FC ) group.long ($2+0x400)++0x3 line.long 0x0 "REGG1_DOM_$1,Assign domain for CKGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x4 0x8 0xC 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C ) group.long ($2+0x800)++0x3 line.long 0x0 "REGG2_DOM_$1,Assign domain for SCR registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1A 0x1B 0x1C 0x1D 0x1E 0x1F )(list 0x40 0x44 0x48 0x4C 0x50 0x54 0x58 0x5C 0x60 0x64 0x68 0x6C 0x70 0x74 0x78 0x7C ) group.long ($2+0x800)++0x3 line.long 0x0 "REGG2_DOM_$1,Assign domain for SCR registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x20 0x21 0x22 0x23 0x24 0x25 0x26 0x27 0x28 0x29 0x2A 0x2B 0x2C 0x2D 0x2E 0x2F )(list 0x80 0x84 0x88 0x8C 0x90 0x94 0x98 0x9C 0xA0 0xA4 0xA8 0xAC 0xB0 0xB4 0xB8 0xBC ) group.long ($2+0x800)++0x3 line.long 0x0 "REGG2_DOM_$1,Assign domain for SCR registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x30 0x31 0x32 0x33 0x34 0x35 0x36 0x37 0x38 0x39 0x3A 0x3B 0x3C 0x3D 0x3E 0x3F )(list 0xC0 0xC4 0xC8 0xCC 0xD0 0xD4 0xD8 0xDC 0xE0 0xE4 0xE8 0xEC 0xF0 0xF4 0xF8 0xFC ) group.long ($2+0x800)++0x3 line.long 0x0 "REGG2_DOM_$1,Assign domain for SCR registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x40 0x41 0x42 0x43 0x44 0x45 0x46 0x47 0x48 0x49 0x4A 0x4B 0x4C 0x4D 0x4E 0x4F )(list 0x100 0x104 0x108 0x10C 0x110 0x114 0x118 0x11C 0x120 0x124 0x128 0x12C 0x130 0x134 0x138 0x13C ) group.long ($2+0x800)++0x3 line.long 0x0 "REGG2_DOM_$1,Assign domain for SCR registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x50 0x51 0x52 0x53 0x54 0x55 0x56 0x57 0x58 0x59 0x5A 0x5B 0x5C 0x5D 0x5E 0x5F )(list 0x140 0x144 0x148 0x14C 0x150 0x154 0x158 0x15C 0x160 0x164 0x168 0x16C 0x170 0x174 0x178 0x17C ) group.long ($2+0x800)++0x3 line.long 0x0 "REGG2_DOM_$1,Assign domain for SCR registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x60 0x61 0x62 0x63 0x64 0x65 0x66 0x67 0x68 0x69 0x6A 0x6B 0x6C 0x6D 0x6E 0x6F )(list 0x180 0x184 0x188 0x18C 0x190 0x194 0x198 0x19C 0x1A0 0x1A4 0x1A8 0x1AC 0x1B0 0x1B4 0x1B8 0x1BC ) group.long ($2+0x800)++0x3 line.long 0x0 "REGG2_DOM_$1,Assign domain for SCR registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x70 0x71 0x72 0x73 0x74 0x75 0x76 0x77 0x78 0x79 0x7A 0x7B 0x7C 0x7D 0x7E 0x7F )(list 0x1C0 0x1C4 0x1C8 0x1CC 0x1D0 0x1D4 0x1D8 0x1DC 0x1E0 0x1E4 0x1E8 0x1EC 0x1F0 0x1F4 0x1F8 0x1FC ) group.long ($2+0x800)++0x3 line.long 0x0 "REGG2_DOM_$1,Assign domain for SCR registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x80 0x81 0x82 0x83 0x84 0x85 0x86 0x87 0x88 0x89 0x8A 0x8B 0x8C 0x8D 0x8E 0x8F )(list 0x200 0x204 0x208 0x20C 0x210 0x214 0x218 0x21C 0x220 0x224 0x228 0x22C 0x230 0x234 0x238 0x23C ) group.long ($2+0x800)++0x3 line.long 0x0 "REGG2_DOM_$1,Assign domain for SCR registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x90 0x91 0x92 0x93 0x94 0x95 0x96 0x97 0x98 0x99 0x9A 0x9B 0x9C 0x9D 0x9E 0x9F )(list 0x240 0x244 0x248 0x24C 0x250 0x254 0x258 0x25C 0x260 0x264 0x268 0x26C 0x270 0x274 0x278 0x27C ) group.long ($2+0x800)++0x3 line.long 0x0 "REGG2_DOM_$1,Assign domain for SCR registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xA0 0xA1 0xA2 0xA3 0xA4 0xA5 0xA6 0xA7 0xA8 0xA9 0xAA 0xAB 0xAC 0xAD 0xAE 0xAF )(list 0x280 0x284 0x288 0x28C 0x290 0x294 0x298 0x29C 0x2A0 0x2A4 0x2A8 0x2AC 0x2B0 0x2B4 0x2B8 0x2BC ) group.long ($2+0x800)++0x3 line.long 0x0 "REGG2_DOM_$1,Assign domain for SCR registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xB0 0xB1 0xB2 0xB3 0xB4 0xB5 0xB6 0xB7 0xB8 0xB9 0xBA 0xBB 0xBC 0xBD 0xBE 0xBF )(list 0x2C0 0x2C4 0x2C8 0x2CC 0x2D0 0x2D4 0x2D8 0x2DC 0x2E0 0x2E4 0x2E8 0x2EC 0x2F0 0x2F4 0x2F8 0x2FC ) group.long ($2+0x800)++0x3 line.long 0x0 "REGG2_DOM_$1,Assign domain for SCR registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xC0 0xC1 0xC2 0xC3 0xC4 0xC5 0xC6 0xC7 0xC8 0xC9 0xCA 0xCB 0xCC 0xCD 0xCE 0xCF )(list 0x300 0x304 0x308 0x30C 0x310 0x314 0x318 0x31C 0x320 0x324 0x328 0x32C 0x330 0x334 0x338 0x33C ) group.long ($2+0x800)++0x3 line.long 0x0 "REGG2_DOM_$1,Assign domain for SCR registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xD0 0xD1 0xD2 0xD3 0xD4 0xD5 0xD6 0xD7 0xD8 0xD9 0xDA 0xDB 0xDC 0xDD 0xDE 0xDF )(list 0x340 0x344 0x348 0x34C 0x350 0x354 0x358 0x35C 0x360 0x364 0x368 0x36C 0x370 0x374 0x378 0x37C ) group.long ($2+0x800)++0x3 line.long 0x0 "REGG2_DOM_$1,Assign domain for SCR registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xE0 0xE1 0xE2 0xE3 0xE4 0xE5 0xE6 0xE7 0xE8 0xE9 0xEA 0xEB 0xEC 0xED 0xEE 0xEF )(list 0x380 0x384 0x388 0x38C 0x390 0x394 0x398 0x39C 0x3A0 0x3A4 0x3A8 0x3AC 0x3B0 0x3B4 0x3B8 0x3BC ) group.long ($2+0x800)++0x3 line.long 0x0 "REGG2_DOM_$1,Assign domain for SCR registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xF0 0xF1 0xF2 0xF3 0xF4 0xF5 0xF6 0xF7 0xF8 0xF9 0xFA 0xFB 0xFC 0xFD 0xFE 0xFF )(list 0x3C0 0x3C4 0x3C8 0x3CC 0x3D0 0x3D4 0x3D8 0x3DC 0x3E0 0x3E4 0x3E8 0x3EC 0x3F0 0x3F4 0x3F8 0x3FC ) group.long ($2+0x800)++0x3 line.long 0x0 "REGG2_DOM_$1,Assign domain for SCR registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x4 0x8 0xC 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C ) group.long ($2+0xC00)++0x3 line.long 0x0 "REGG3_DOM_$1,Assign domain for SCR registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1A 0x1B 0x1C 0x1D 0x1E 0x1F )(list 0x40 0x44 0x48 0x4C 0x50 0x54 0x58 0x5C 0x60 0x64 0x68 0x6C 0x70 0x74 0x78 0x7C ) group.long ($2+0xC00)++0x3 line.long 0x0 "REGG3_DOM_$1,Assign domain for SCR registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x20 0x21 0x22 0x23 0x24 0x25 0x26 0x27 0x28 0x29 0x2A 0x2B 0x2C 0x2D 0x2E 0x2F )(list 0x80 0x84 0x88 0x8C 0x90 0x94 0x98 0x9C 0xA0 0xA4 0xA8 0xAC 0xB0 0xB4 0xB8 0xBC ) group.long ($2+0xC00)++0x3 line.long 0x0 "REGG3_DOM_$1,Assign domain for SCR registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x30 0x31 0x32 0x33 0x34 0x35 0x36 0x37 0x38 0x39 0x3A 0x3B 0x3C 0x3D 0x3E 0x3F )(list 0xC0 0xC4 0xC8 0xCC 0xD0 0xD4 0xD8 0xDC 0xE0 0xE4 0xE8 0xEC 0xF0 0xF4 0xF8 0xFC ) group.long ($2+0xC00)++0x3 line.long 0x0 "REGG3_DOM_$1,Assign domain for SCR registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x40 0x41 0x42 0x43 0x44 0x45 0x46 0x47 0x48 0x49 0x4A 0x4B 0x4C 0x4D 0x4E 0x4F )(list 0x100 0x104 0x108 0x10C 0x110 0x114 0x118 0x11C 0x120 0x124 0x128 0x12C 0x130 0x134 0x138 0x13C ) group.long ($2+0xC00)++0x3 line.long 0x0 "REGG3_DOM_$1,Assign domain for SCR registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x50 0x51 0x52 0x53 0x54 0x55 0x56 0x57 0x58 0x59 0x5A 0x5B 0x5C 0x5D 0x5E 0x5F )(list 0x140 0x144 0x148 0x14C 0x150 0x154 0x158 0x15C 0x160 0x164 0x168 0x16C 0x170 0x174 0x178 0x17C ) group.long ($2+0xC00)++0x3 line.long 0x0 "REGG3_DOM_$1,Assign domain for SCR registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x60 0x61 0x62 0x63 0x64 0x65 0x66 0x67 0x68 0x69 0x6A 0x6B 0x6C 0x6D 0x6E 0x6F )(list 0x180 0x184 0x188 0x18C 0x190 0x194 0x198 0x19C 0x1A0 0x1A4 0x1A8 0x1AC 0x1B0 0x1B4 0x1B8 0x1BC ) group.long ($2+0xC00)++0x3 line.long 0x0 "REGG3_DOM_$1,Assign domain for SCR registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x70 0x71 0x72 0x73 0x74 0x75 0x76 0x77 0x78 0x79 0x7A 0x7B 0x7C 0x7D 0x7E 0x7F )(list 0x1C0 0x1C4 0x1C8 0x1CC 0x1D0 0x1D4 0x1D8 0x1DC 0x1E0 0x1E4 0x1E8 0x1EC 0x1F0 0x1F4 0x1F8 0x1FC ) group.long ($2+0xC00)++0x3 line.long 0x0 "REGG3_DOM_$1,Assign domain for SCR registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x80 0x81 0x82 0x83 0x84 0x85 0x86 0x87 0x88 0x89 0x8A 0x8B 0x8C 0x8D 0x8E 0x8F )(list 0x200 0x204 0x208 0x20C 0x210 0x214 0x218 0x21C 0x220 0x224 0x228 0x22C 0x230 0x234 0x238 0x23C ) group.long ($2+0xC00)++0x3 line.long 0x0 "REGG3_DOM_$1,Assign domain for SCR registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x90 0x91 0x92 0x93 0x94 0x95 0x96 0x97 0x98 0x99 0x9A 0x9B 0x9C 0x9D 0x9E 0x9F )(list 0x240 0x244 0x248 0x24C 0x250 0x254 0x258 0x25C 0x260 0x264 0x268 0x26C 0x270 0x274 0x278 0x27C ) group.long ($2+0xC00)++0x3 line.long 0x0 "REGG3_DOM_$1,Assign domain for SCR registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xA0 0xA1 0xA2 0xA3 0xA4 0xA5 0xA6 0xA7 0xA8 0xA9 0xAA 0xAB 0xAC 0xAD 0xAE 0xAF )(list 0x280 0x284 0x288 0x28C 0x290 0x294 0x298 0x29C 0x2A0 0x2A4 0x2A8 0x2AC 0x2B0 0x2B4 0x2B8 0x2BC ) group.long ($2+0xC00)++0x3 line.long 0x0 "REGG3_DOM_$1,Assign domain for SCR registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xB0 0xB1 0xB2 0xB3 0xB4 0xB5 0xB6 0xB7 0xB8 0xB9 0xBA 0xBB 0xBC 0xBD 0xBE 0xBF )(list 0x2C0 0x2C4 0x2C8 0x2CC 0x2D0 0x2D4 0x2D8 0x2DC 0x2E0 0x2E4 0x2E8 0x2EC 0x2F0 0x2F4 0x2F8 0x2FC ) group.long ($2+0xC00)++0x3 line.long 0x0 "REGG3_DOM_$1,Assign domain for SCR registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xC0 0xC1 0xC2 0xC3 0xC4 0xC5 0xC6 0xC7 0xC8 0xC9 0xCA 0xCB 0xCC 0xCD 0xCE 0xCF )(list 0x300 0x304 0x308 0x30C 0x310 0x314 0x318 0x31C 0x320 0x324 0x328 0x32C 0x330 0x334 0x338 0x33C ) group.long ($2+0xC00)++0x3 line.long 0x0 "REGG3_DOM_$1,Assign domain for SCR registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xD0 0xD1 0xD2 0xD3 0xD4 0xD5 0xD6 0xD7 0xD8 0xD9 0xDA 0xDB 0xDC 0xDD 0xDE 0xDF )(list 0x340 0x344 0x348 0x34C 0x350 0x354 0x358 0x35C 0x360 0x364 0x368 0x36C 0x370 0x374 0x378 0x37C ) group.long ($2+0xC00)++0x3 line.long 0x0 "REGG3_DOM_$1,Assign domain for SCR registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xE0 0xE1 0xE2 0xE3 0xE4 0xE5 0xE6 0xE7 0xE8 0xE9 0xEA 0xEB 0xEC 0xED 0xEE 0xEF )(list 0x380 0x384 0x388 0x38C 0x390 0x394 0x398 0x39C 0x3A0 0x3A4 0x3A8 0x3AC 0x3B0 0x3B4 0x3B8 0x3BC ) group.long ($2+0xC00)++0x3 line.long 0x0 "REGG3_DOM_$1,Assign domain for SCR registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xF0 0xF1 0xF2 0xF3 0xF4 0xF5 0xF6 0xF7 0xF8 0xF9 0xFA 0xFB 0xFC 0xFD 0xFE 0xFF )(list 0x3C0 0x3C4 0x3C8 0x3CC 0x3D0 0x3D4 0x3D8 0x3DC 0x3E0 0x3E4 0x3E8 0x3EC 0x3F0 0x3F4 0x3F8 0x3FC ) group.long ($2+0xC00)++0x3 line.long 0x0 "REGG3_DOM_$1,Assign domain for SCR registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x4 0x8 0xC 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C ) group.long ($2+0x1000)++0x3 line.long 0x0 "REGG4_DOM_$1,Assign domain for RSTGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1A 0x1B 0x1C 0x1D 0x1E 0x1F )(list 0x40 0x44 0x48 0x4C 0x50 0x54 0x58 0x5C 0x60 0x64 0x68 0x6C 0x70 0x74 0x78 0x7C ) group.long ($2+0x1000)++0x3 line.long 0x0 "REGG4_DOM_$1,Assign domain for RSTGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x20 0x21 0x22 0x23 0x24 0x25 0x26 0x27 0x28 0x29 0x2A 0x2B 0x2C 0x2D 0x2E 0x2F )(list 0x80 0x84 0x88 0x8C 0x90 0x94 0x98 0x9C 0xA0 0xA4 0xA8 0xAC 0xB0 0xB4 0xB8 0xBC ) group.long ($2+0x1000)++0x3 line.long 0x0 "REGG4_DOM_$1,Assign domain for RSTGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x30 0x31 0x32 0x33 0x34 0x35 0x36 0x37 0x38 0x39 0x3A 0x3B 0x3C 0x3D 0x3E 0x3F )(list 0xC0 0xC4 0xC8 0xCC 0xD0 0xD4 0xD8 0xDC 0xE0 0xE4 0xE8 0xEC 0xF0 0xF4 0xF8 0xFC ) group.long ($2+0x1000)++0x3 line.long 0x0 "REGG4_DOM_$1,Assign domain for RSTGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x40 0x41 0x42 0x43 0x44 0x45 0x46 0x47 0x48 0x49 0x4A 0x4B 0x4C 0x4D 0x4E 0x4F )(list 0x100 0x104 0x108 0x10C 0x110 0x114 0x118 0x11C 0x120 0x124 0x128 0x12C 0x130 0x134 0x138 0x13C ) group.long ($2+0x1000)++0x3 line.long 0x0 "REGG4_DOM_$1,Assign domain for RSTGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x50 0x51 0x52 0x53 0x54 0x55 0x56 0x57 0x58 0x59 0x5A 0x5B 0x5C 0x5D 0x5E 0x5F )(list 0x140 0x144 0x148 0x14C 0x150 0x154 0x158 0x15C 0x160 0x164 0x168 0x16C 0x170 0x174 0x178 0x17C ) group.long ($2+0x1000)++0x3 line.long 0x0 "REGG4_DOM_$1,Assign domain for RSTGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x60 0x61 0x62 0x63 0x64 0x65 0x66 0x67 0x68 0x69 0x6A 0x6B 0x6C 0x6D 0x6E 0x6F )(list 0x180 0x184 0x188 0x18C 0x190 0x194 0x198 0x19C 0x1A0 0x1A4 0x1A8 0x1AC 0x1B0 0x1B4 0x1B8 0x1BC ) group.long ($2+0x1000)++0x3 line.long 0x0 "REGG4_DOM_$1,Assign domain for RSTGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x70 0x71 0x72 0x73 0x74 0x75 0x76 0x77 0x78 0x79 0x7A 0x7B 0x7C 0x7D 0x7E 0x7F )(list 0x1C0 0x1C4 0x1C8 0x1CC 0x1D0 0x1D4 0x1D8 0x1DC 0x1E0 0x1E4 0x1E8 0x1EC 0x1F0 0x1F4 0x1F8 0x1FC ) group.long ($2+0x1000)++0x3 line.long 0x0 "REGG4_DOM_$1,Assign domain for RSTGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x80 0x81 0x82 0x83 0x84 0x85 0x86 0x87 0x88 0x89 0x8A 0x8B 0x8C 0x8D 0x8E 0x8F )(list 0x200 0x204 0x208 0x20C 0x210 0x214 0x218 0x21C 0x220 0x224 0x228 0x22C 0x230 0x234 0x238 0x23C ) group.long ($2+0x1000)++0x3 line.long 0x0 "REGG4_DOM_$1,Assign domain for RSTGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x90 0x91 0x92 0x93 0x94 0x95 0x96 0x97 0x98 0x99 0x9A 0x9B 0x9C 0x9D 0x9E 0x9F )(list 0x240 0x244 0x248 0x24C 0x250 0x254 0x258 0x25C 0x260 0x264 0x268 0x26C 0x270 0x274 0x278 0x27C ) group.long ($2+0x1000)++0x3 line.long 0x0 "REGG4_DOM_$1,Assign domain for RSTGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xA0 0xA1 0xA2 0xA3 0xA4 0xA5 0xA6 0xA7 0xA8 0xA9 0xAA 0xAB 0xAC 0xAD 0xAE 0xAF )(list 0x280 0x284 0x288 0x28C 0x290 0x294 0x298 0x29C 0x2A0 0x2A4 0x2A8 0x2AC 0x2B0 0x2B4 0x2B8 0x2BC ) group.long ($2+0x1000)++0x3 line.long 0x0 "REGG4_DOM_$1,Assign domain for RSTGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xB0 0xB1 0xB2 0xB3 0xB4 0xB5 0xB6 0xB7 0xB8 0xB9 0xBA 0xBB 0xBC 0xBD 0xBE 0xBF )(list 0x2C0 0x2C4 0x2C8 0x2CC 0x2D0 0x2D4 0x2D8 0x2DC 0x2E0 0x2E4 0x2E8 0x2EC 0x2F0 0x2F4 0x2F8 0x2FC ) group.long ($2+0x1000)++0x3 line.long 0x0 "REGG4_DOM_$1,Assign domain for RSTGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xC0 0xC1 0xC2 0xC3 0xC4 0xC5 0xC6 0xC7 0xC8 0xC9 0xCA 0xCB 0xCC 0xCD 0xCE 0xCF )(list 0x300 0x304 0x308 0x30C 0x310 0x314 0x318 0x31C 0x320 0x324 0x328 0x32C 0x330 0x334 0x338 0x33C ) group.long ($2+0x1000)++0x3 line.long 0x0 "REGG4_DOM_$1,Assign domain for RSTGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xD0 0xD1 0xD2 0xD3 0xD4 0xD5 0xD6 0xD7 0xD8 0xD9 0xDA 0xDB 0xDC 0xDD 0xDE 0xDF )(list 0x340 0x344 0x348 0x34C 0x350 0x354 0x358 0x35C 0x360 0x364 0x368 0x36C 0x370 0x374 0x378 0x37C ) group.long ($2+0x1000)++0x3 line.long 0x0 "REGG4_DOM_$1,Assign domain for RSTGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xE0 0xE1 0xE2 0xE3 0xE4 0xE5 0xE6 0xE7 0xE8 0xE9 0xEA 0xEB 0xEC 0xED 0xEE 0xEF )(list 0x380 0x384 0x388 0x38C 0x390 0x394 0x398 0x39C 0x3A0 0x3A4 0x3A8 0x3AC 0x3B0 0x3B4 0x3B8 0x3BC ) group.long ($2+0x1000)++0x3 line.long 0x0 "REGG4_DOM_$1,Assign domain for RSTGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xF0 0xF1 0xF2 0xF3 0xF4 0xF5 0xF6 0xF7 0xF8 0xF9 0xFA 0xFB 0xFC 0xFD 0xFE 0xFF )(list 0x3C0 0x3C4 0x3C8 0x3CC 0x3D0 0x3D4 0x3D8 0x3DC 0x3E0 0x3E4 0x3E8 0x3EC 0x3F0 0x3F4 0x3F8 0x3FC ) group.long ($2+0x1000)++0x3 line.long 0x0 "REGG4_DOM_$1,Assign domain for RSTGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x4 0x8 0xC 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C ) group.long ($2+0x1400)++0x3 line.long 0x0 "REGG5_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1A 0x1B 0x1C 0x1D 0x1E 0x1F )(list 0x40 0x44 0x48 0x4C 0x50 0x54 0x58 0x5C 0x60 0x64 0x68 0x6C 0x70 0x74 0x78 0x7C ) group.long ($2+0x1400)++0x3 line.long 0x0 "REGG5_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x20 0x21 0x22 0x23 0x24 0x25 0x26 0x27 0x28 0x29 0x2A 0x2B 0x2C 0x2D 0x2E 0x2F )(list 0x80 0x84 0x88 0x8C 0x90 0x94 0x98 0x9C 0xA0 0xA4 0xA8 0xAC 0xB0 0xB4 0xB8 0xBC ) group.long ($2+0x1400)++0x3 line.long 0x0 "REGG5_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x30 0x31 0x32 0x33 0x34 0x35 0x36 0x37 0x38 0x39 0x3A 0x3B 0x3C 0x3D 0x3E 0x3F )(list 0xC0 0xC4 0xC8 0xCC 0xD0 0xD4 0xD8 0xDC 0xE0 0xE4 0xE8 0xEC 0xF0 0xF4 0xF8 0xFC ) group.long ($2+0x1400)++0x3 line.long 0x0 "REGG5_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x40 0x41 0x42 0x43 0x44 0x45 0x46 0x47 0x48 0x49 0x4A 0x4B 0x4C 0x4D 0x4E 0x4F )(list 0x100 0x104 0x108 0x10C 0x110 0x114 0x118 0x11C 0x120 0x124 0x128 0x12C 0x130 0x134 0x138 0x13C ) group.long ($2+0x1400)++0x3 line.long 0x0 "REGG5_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x50 0x51 0x52 0x53 0x54 0x55 0x56 0x57 0x58 0x59 0x5A 0x5B 0x5C 0x5D 0x5E 0x5F )(list 0x140 0x144 0x148 0x14C 0x150 0x154 0x158 0x15C 0x160 0x164 0x168 0x16C 0x170 0x174 0x178 0x17C ) group.long ($2+0x1400)++0x3 line.long 0x0 "REGG5_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x60 0x61 0x62 0x63 0x64 0x65 0x66 0x67 0x68 0x69 0x6A 0x6B 0x6C 0x6D 0x6E 0x6F )(list 0x180 0x184 0x188 0x18C 0x190 0x194 0x198 0x19C 0x1A0 0x1A4 0x1A8 0x1AC 0x1B0 0x1B4 0x1B8 0x1BC ) group.long ($2+0x1400)++0x3 line.long 0x0 "REGG5_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x70 0x71 0x72 0x73 0x74 0x75 0x76 0x77 0x78 0x79 0x7A 0x7B 0x7C 0x7D 0x7E 0x7F )(list 0x1C0 0x1C4 0x1C8 0x1CC 0x1D0 0x1D4 0x1D8 0x1DC 0x1E0 0x1E4 0x1E8 0x1EC 0x1F0 0x1F4 0x1F8 0x1FC ) group.long ($2+0x1400)++0x3 line.long 0x0 "REGG5_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x80 0x81 0x82 0x83 0x84 0x85 0x86 0x87 0x88 0x89 0x8A 0x8B 0x8C 0x8D 0x8E 0x8F )(list 0x200 0x204 0x208 0x20C 0x210 0x214 0x218 0x21C 0x220 0x224 0x228 0x22C 0x230 0x234 0x238 0x23C ) group.long ($2+0x1400)++0x3 line.long 0x0 "REGG5_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x90 0x91 0x92 0x93 0x94 0x95 0x96 0x97 0x98 0x99 0x9A 0x9B 0x9C 0x9D 0x9E 0x9F )(list 0x240 0x244 0x248 0x24C 0x250 0x254 0x258 0x25C 0x260 0x264 0x268 0x26C 0x270 0x274 0x278 0x27C ) group.long ($2+0x1400)++0x3 line.long 0x0 "REGG5_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xA0 0xA1 0xA2 0xA3 0xA4 0xA5 0xA6 0xA7 0xA8 0xA9 0xAA 0xAB 0xAC 0xAD 0xAE 0xAF )(list 0x280 0x284 0x288 0x28C 0x290 0x294 0x298 0x29C 0x2A0 0x2A4 0x2A8 0x2AC 0x2B0 0x2B4 0x2B8 0x2BC ) group.long ($2+0x1400)++0x3 line.long 0x0 "REGG5_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xB0 0xB1 0xB2 0xB3 0xB4 0xB5 0xB6 0xB7 0xB8 0xB9 0xBA 0xBB 0xBC 0xBD 0xBE 0xBF )(list 0x2C0 0x2C4 0x2C8 0x2CC 0x2D0 0x2D4 0x2D8 0x2DC 0x2E0 0x2E4 0x2E8 0x2EC 0x2F0 0x2F4 0x2F8 0x2FC ) group.long ($2+0x1400)++0x3 line.long 0x0 "REGG5_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xC0 0xC1 0xC2 0xC3 0xC4 0xC5 0xC6 0xC7 0xC8 0xC9 0xCA 0xCB 0xCC 0xCD 0xCE 0xCF )(list 0x300 0x304 0x308 0x30C 0x310 0x314 0x318 0x31C 0x320 0x324 0x328 0x32C 0x330 0x334 0x338 0x33C ) group.long ($2+0x1400)++0x3 line.long 0x0 "REGG5_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xD0 0xD1 0xD2 0xD3 0xD4 0xD5 0xD6 0xD7 0xD8 0xD9 0xDA 0xDB 0xDC 0xDD 0xDE 0xDF )(list 0x340 0x344 0x348 0x34C 0x350 0x354 0x358 0x35C 0x360 0x364 0x368 0x36C 0x370 0x374 0x378 0x37C ) group.long ($2+0x1400)++0x3 line.long 0x0 "REGG5_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xE0 0xE1 0xE2 0xE3 0xE4 0xE5 0xE6 0xE7 0xE8 0xE9 0xEA 0xEB 0xEC 0xED 0xEE 0xEF )(list 0x380 0x384 0x388 0x38C 0x390 0x394 0x398 0x39C 0x3A0 0x3A4 0x3A8 0x3AC 0x3B0 0x3B4 0x3B8 0x3BC ) group.long ($2+0x1400)++0x3 line.long 0x0 "REGG5_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xF0 0xF1 0xF2 0xF3 0xF4 0xF5 0xF6 0xF7 0xF8 0xF9 0xFA 0xFB 0xFC 0xFD 0xFE 0xFF )(list 0x3C0 0x3C4 0x3C8 0x3CC 0x3D0 0x3D4 0x3D8 0x3DC 0x3E0 0x3E4 0x3E8 0x3EC 0x3F0 0x3F4 0x3F8 0x3FC ) group.long ($2+0x1400)++0x3 line.long 0x0 "REGG5_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x4 0x8 0xC 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C ) group.long ($2+0x1800)++0x3 line.long 0x0 "REGG6_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1A 0x1B 0x1C 0x1D 0x1E 0x1F )(list 0x40 0x44 0x48 0x4C 0x50 0x54 0x58 0x5C 0x60 0x64 0x68 0x6C 0x70 0x74 0x78 0x7C ) group.long ($2+0x1800)++0x3 line.long 0x0 "REGG6_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x20 0x21 0x22 0x23 0x24 0x25 0x26 0x27 0x28 0x29 0x2A 0x2B 0x2C 0x2D 0x2E 0x2F )(list 0x80 0x84 0x88 0x8C 0x90 0x94 0x98 0x9C 0xA0 0xA4 0xA8 0xAC 0xB0 0xB4 0xB8 0xBC ) group.long ($2+0x1800)++0x3 line.long 0x0 "REGG6_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x30 0x31 0x32 0x33 0x34 0x35 0x36 0x37 0x38 0x39 0x3A 0x3B 0x3C 0x3D 0x3E 0x3F )(list 0xC0 0xC4 0xC8 0xCC 0xD0 0xD4 0xD8 0xDC 0xE0 0xE4 0xE8 0xEC 0xF0 0xF4 0xF8 0xFC ) group.long ($2+0x1800)++0x3 line.long 0x0 "REGG6_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x40 0x41 0x42 0x43 0x44 0x45 0x46 0x47 0x48 0x49 0x4A 0x4B 0x4C 0x4D 0x4E 0x4F )(list 0x100 0x104 0x108 0x10C 0x110 0x114 0x118 0x11C 0x120 0x124 0x128 0x12C 0x130 0x134 0x138 0x13C ) group.long ($2+0x1800)++0x3 line.long 0x0 "REGG6_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x50 0x51 0x52 0x53 0x54 0x55 0x56 0x57 0x58 0x59 0x5A 0x5B 0x5C 0x5D 0x5E 0x5F )(list 0x140 0x144 0x148 0x14C 0x150 0x154 0x158 0x15C 0x160 0x164 0x168 0x16C 0x170 0x174 0x178 0x17C ) group.long ($2+0x1800)++0x3 line.long 0x0 "REGG6_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x60 0x61 0x62 0x63 0x64 0x65 0x66 0x67 0x68 0x69 0x6A 0x6B 0x6C 0x6D 0x6E 0x6F )(list 0x180 0x184 0x188 0x18C 0x190 0x194 0x198 0x19C 0x1A0 0x1A4 0x1A8 0x1AC 0x1B0 0x1B4 0x1B8 0x1BC ) group.long ($2+0x1800)++0x3 line.long 0x0 "REGG6_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x70 0x71 0x72 0x73 0x74 0x75 0x76 0x77 0x78 0x79 0x7A 0x7B 0x7C 0x7D 0x7E 0x7F )(list 0x1C0 0x1C4 0x1C8 0x1CC 0x1D0 0x1D4 0x1D8 0x1DC 0x1E0 0x1E4 0x1E8 0x1EC 0x1F0 0x1F4 0x1F8 0x1FC ) group.long ($2+0x1800)++0x3 line.long 0x0 "REGG6_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x80 0x81 0x82 0x83 0x84 0x85 0x86 0x87 0x88 0x89 0x8A 0x8B 0x8C 0x8D 0x8E 0x8F )(list 0x200 0x204 0x208 0x20C 0x210 0x214 0x218 0x21C 0x220 0x224 0x228 0x22C 0x230 0x234 0x238 0x23C ) group.long ($2+0x1800)++0x3 line.long 0x0 "REGG6_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x90 0x91 0x92 0x93 0x94 0x95 0x96 0x97 0x98 0x99 0x9A 0x9B 0x9C 0x9D 0x9E 0x9F )(list 0x240 0x244 0x248 0x24C 0x250 0x254 0x258 0x25C 0x260 0x264 0x268 0x26C 0x270 0x274 0x278 0x27C ) group.long ($2+0x1800)++0x3 line.long 0x0 "REGG6_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xA0 0xA1 0xA2 0xA3 0xA4 0xA5 0xA6 0xA7 0xA8 0xA9 0xAA 0xAB 0xAC 0xAD 0xAE 0xAF )(list 0x280 0x284 0x288 0x28C 0x290 0x294 0x298 0x29C 0x2A0 0x2A4 0x2A8 0x2AC 0x2B0 0x2B4 0x2B8 0x2BC ) group.long ($2+0x1800)++0x3 line.long 0x0 "REGG6_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xB0 0xB1 0xB2 0xB3 0xB4 0xB5 0xB6 0xB7 0xB8 0xB9 0xBA 0xBB 0xBC 0xBD 0xBE 0xBF )(list 0x2C0 0x2C4 0x2C8 0x2CC 0x2D0 0x2D4 0x2D8 0x2DC 0x2E0 0x2E4 0x2E8 0x2EC 0x2F0 0x2F4 0x2F8 0x2FC ) group.long ($2+0x1800)++0x3 line.long 0x0 "REGG6_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xC0 0xC1 0xC2 0xC3 0xC4 0xC5 0xC6 0xC7 0xC8 0xC9 0xCA 0xCB 0xCC 0xCD 0xCE 0xCF )(list 0x300 0x304 0x308 0x30C 0x310 0x314 0x318 0x31C 0x320 0x324 0x328 0x32C 0x330 0x334 0x338 0x33C ) group.long ($2+0x1800)++0x3 line.long 0x0 "REGG6_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xD0 0xD1 0xD2 0xD3 0xD4 0xD5 0xD6 0xD7 0xD8 0xD9 0xDA 0xDB 0xDC 0xDD 0xDE 0xDF )(list 0x340 0x344 0x348 0x34C 0x350 0x354 0x358 0x35C 0x360 0x364 0x368 0x36C 0x370 0x374 0x378 0x37C ) group.long ($2+0x1800)++0x3 line.long 0x0 "REGG6_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xE0 0xE1 0xE2 0xE3 0xE4 0xE5 0xE6 0xE7 0xE8 0xE9 0xEA 0xEB 0xEC 0xED 0xEE 0xEF )(list 0x380 0x384 0x388 0x38C 0x390 0x394 0x398 0x39C 0x3A0 0x3A4 0x3A8 0x3AC 0x3B0 0x3B4 0x3B8 0x3BC ) group.long ($2+0x1800)++0x3 line.long 0x0 "REGG6_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xF0 0xF1 0xF2 0xF3 0xF4 0xF5 0xF6 0xF7 0xF8 0xF9 0xFA 0xFB 0xFC 0xFD 0xFE 0xFF )(list 0x3C0 0x3C4 0x3C8 0x3CC 0x3D0 0x3D4 0x3D8 0x3DC 0x3E0 0x3E4 0x3E8 0x3EC 0x3F0 0x3F4 0x3F8 0x3FC ) group.long ($2+0x1800)++0x3 line.long 0x0 "REGG6_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x4 0x8 0xC 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C ) group.long ($2+0x1C00)++0x3 line.long 0x0 "REGG7_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1A 0x1B 0x1C 0x1D 0x1E 0x1F )(list 0x40 0x44 0x48 0x4C 0x50 0x54 0x58 0x5C 0x60 0x64 0x68 0x6C 0x70 0x74 0x78 0x7C ) group.long ($2+0x1C00)++0x3 line.long 0x0 "REGG7_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x20 0x21 0x22 0x23 0x24 0x25 0x26 0x27 0x28 0x29 0x2A 0x2B 0x2C 0x2D 0x2E 0x2F )(list 0x80 0x84 0x88 0x8C 0x90 0x94 0x98 0x9C 0xA0 0xA4 0xA8 0xAC 0xB0 0xB4 0xB8 0xBC ) group.long ($2+0x1C00)++0x3 line.long 0x0 "REGG7_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x30 0x31 0x32 0x33 0x34 0x35 0x36 0x37 0x38 0x39 0x3A 0x3B 0x3C 0x3D 0x3E 0x3F )(list 0xC0 0xC4 0xC8 0xCC 0xD0 0xD4 0xD8 0xDC 0xE0 0xE4 0xE8 0xEC 0xF0 0xF4 0xF8 0xFC ) group.long ($2+0x1C00)++0x3 line.long 0x0 "REGG7_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x40 0x41 0x42 0x43 0x44 0x45 0x46 0x47 0x48 0x49 0x4A 0x4B 0x4C 0x4D 0x4E 0x4F )(list 0x100 0x104 0x108 0x10C 0x110 0x114 0x118 0x11C 0x120 0x124 0x128 0x12C 0x130 0x134 0x138 0x13C ) group.long ($2+0x1C00)++0x3 line.long 0x0 "REGG7_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x50 0x51 0x52 0x53 0x54 0x55 0x56 0x57 0x58 0x59 0x5A 0x5B 0x5C 0x5D 0x5E 0x5F )(list 0x140 0x144 0x148 0x14C 0x150 0x154 0x158 0x15C 0x160 0x164 0x168 0x16C 0x170 0x174 0x178 0x17C ) group.long ($2+0x1C00)++0x3 line.long 0x0 "REGG7_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x60 0x61 0x62 0x63 0x64 0x65 0x66 0x67 0x68 0x69 0x6A 0x6B 0x6C 0x6D 0x6E 0x6F )(list 0x180 0x184 0x188 0x18C 0x190 0x194 0x198 0x19C 0x1A0 0x1A4 0x1A8 0x1AC 0x1B0 0x1B4 0x1B8 0x1BC ) group.long ($2+0x1C00)++0x3 line.long 0x0 "REGG7_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x70 0x71 0x72 0x73 0x74 0x75 0x76 0x77 0x78 0x79 0x7A 0x7B 0x7C 0x7D 0x7E 0x7F )(list 0x1C0 0x1C4 0x1C8 0x1CC 0x1D0 0x1D4 0x1D8 0x1DC 0x1E0 0x1E4 0x1E8 0x1EC 0x1F0 0x1F4 0x1F8 0x1FC ) group.long ($2+0x1C00)++0x3 line.long 0x0 "REGG7_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x80 0x81 0x82 0x83 0x84 0x85 0x86 0x87 0x88 0x89 0x8A 0x8B 0x8C 0x8D 0x8E 0x8F )(list 0x200 0x204 0x208 0x20C 0x210 0x214 0x218 0x21C 0x220 0x224 0x228 0x22C 0x230 0x234 0x238 0x23C ) group.long ($2+0x1C00)++0x3 line.long 0x0 "REGG7_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x90 0x91 0x92 0x93 0x94 0x95 0x96 0x97 0x98 0x99 0x9A 0x9B 0x9C 0x9D 0x9E 0x9F )(list 0x240 0x244 0x248 0x24C 0x250 0x254 0x258 0x25C 0x260 0x264 0x268 0x26C 0x270 0x274 0x278 0x27C ) group.long ($2+0x1C00)++0x3 line.long 0x0 "REGG7_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xA0 0xA1 0xA2 0xA3 0xA4 0xA5 0xA6 0xA7 0xA8 0xA9 0xAA 0xAB 0xAC 0xAD 0xAE 0xAF )(list 0x280 0x284 0x288 0x28C 0x290 0x294 0x298 0x29C 0x2A0 0x2A4 0x2A8 0x2AC 0x2B0 0x2B4 0x2B8 0x2BC ) group.long ($2+0x1C00)++0x3 line.long 0x0 "REGG7_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xB0 0xB1 0xB2 0xB3 0xB4 0xB5 0xB6 0xB7 0xB8 0xB9 0xBA 0xBB 0xBC 0xBD 0xBE 0xBF )(list 0x2C0 0x2C4 0x2C8 0x2CC 0x2D0 0x2D4 0x2D8 0x2DC 0x2E0 0x2E4 0x2E8 0x2EC 0x2F0 0x2F4 0x2F8 0x2FC ) group.long ($2+0x1C00)++0x3 line.long 0x0 "REGG7_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xC0 0xC1 0xC2 0xC3 0xC4 0xC5 0xC6 0xC7 0xC8 0xC9 0xCA 0xCB 0xCC 0xCD 0xCE 0xCF )(list 0x300 0x304 0x308 0x30C 0x310 0x314 0x318 0x31C 0x320 0x324 0x328 0x32C 0x330 0x334 0x338 0x33C ) group.long ($2+0x1C00)++0x3 line.long 0x0 "REGG7_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xD0 0xD1 0xD2 0xD3 0xD4 0xD5 0xD6 0xD7 0xD8 0xD9 0xDA 0xDB 0xDC 0xDD 0xDE 0xDF )(list 0x340 0x344 0x348 0x34C 0x350 0x354 0x358 0x35C 0x360 0x364 0x368 0x36C 0x370 0x374 0x378 0x37C ) group.long ($2+0x1C00)++0x3 line.long 0x0 "REGG7_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xE0 0xE1 0xE2 0xE3 0xE4 0xE5 0xE6 0xE7 0xE8 0xE9 0xEA 0xEB 0xEC 0xED 0xEE 0xEF )(list 0x380 0x384 0x388 0x38C 0x390 0x394 0x398 0x39C 0x3A0 0x3A4 0x3A8 0x3AC 0x3B0 0x3B4 0x3B8 0x3BC ) group.long ($2+0x1C00)++0x3 line.long 0x0 "REGG7_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xF0 0xF1 0xF2 0xF3 0xF4 0xF5 0xF6 0xF7 0xF8 0xF9 0xFA 0xFB 0xFC 0xFD 0xFE 0xFF )(list 0x3C0 0x3C4 0x3C8 0x3CC 0x3D0 0x3D4 0x3D8 0x3DC 0x3E0 0x3E4 0x3E8 0x3EC 0x3F0 0x3F4 0x3F8 0x3FC ) group.long ($2+0x1C00)++0x3 line.long 0x0 "REGG7_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end group.long 0x2000++0x17 line.long 0x0 "GLB_CTL,This register provides global enable settings for permission control." bitfld.long 0x0 5. "DOM_CFG_LOCK,Lock write for DOM_CFG_MODE bit." "0,1" bitfld.long 0x0 4. "DOM_CFG_MODE,When enabled all the source setting can be configured by master from domain 0 if it is not locked. When disabled only resource manager can configure the permission of the resource." "0,1" bitfld.long 0x0 3. "PERCK_DIS_LOCK,Lock write for PERCK_DIS" "0,1" bitfld.long 0x0 2. "PERCK_DIS,All the permission check disable." "0,1" newline bitfld.long 0x0 1. "DOM_PRO_LOCK,Lock write for DOM_PRO_EN bit." "0,1" bitfld.long 0x0 0. "DOM_PRO_EN,When disabled no domain access permission check" "0,1" line.long 0x4 "RES_MGR,Resource manager register. This regster is used to assign resource manager for global resource access control" bitfld.long 0x4 17. "MID_LOCK,Lock write for MID_EN and MID_LOW and MID_HIG registers." "0,1" bitfld.long 0x4 16. "MID_EN,Master ID check enable" "0,1" bitfld.long 0x4 15. "PRI_PER_LOCK,Lock write for PRI_PER and PRI_PER_EN" "0,1" bitfld.long 0x4 13.--14. "PRI_PER,Resource manager privileged access permission. bit0 for privileged access bit1 for user access" "0,1,2,3" newline bitfld.long 0x4 12. "PRI_PER_EN,Resource manager privileged access permission enable." "0,1" bitfld.long 0x4 11. "SEC_PER_LOCK,Lock for SEC_PER and SEC_PER_LOCK" "0,1" bitfld.long 0x4 9.--10. "SEC_PER,Resource manager secure access permission. bit 0 for secure access bit 1 for non-secure access" "0,1,2,3" bitfld.long 0x4 8. "SEC_PER_EN,Resource manager secure permission enable" "0,1" bitfld.long 0x4 7. "DID_LOCK,Lock write for DID_EN and DID" "0,1" newline hexmask.long.byte 0x4 3.--6. 1. "DID,Resource manager domain ID" bitfld.long 0x4 2. "DID_EN,Resource manager Domain ID enable" "0,1" bitfld.long 0x4 1. "RES_MGR_EN_LOCK,Lock for RES_MGR_EN" "0,1" bitfld.long 0x4 0. "RES_MGR_EN,Resource manager enable. When the bit is disable there is no resource manager." "0,1" line.long 0x8 "RES_MGR_MA0,This register is used to assign master 0~31 as resource manager." hexmask.long 0x8 0.--31. 1. "MID,Assign master 0~31 for resource manager" line.long 0xC "RES_MGR_MA1,This register is used to assign master 32~63 as resource manager." hexmask.long 0xC 0.--31. 1. "MID,Indicate if master 32~63 is resource manager." line.long 0x10 "RES_MGR_MA2,This register is used to assign master 64~95 as resource manager." hexmask.long 0x10 0.--31. 1. "MID,Indicate if master 64~95 is resource manager." line.long 0x14 "RES_MGR_MA3,This register is used to assign master 96~127 as resource manager." hexmask.long 0x14 0.--31. 1. "MID,Indicate if master 96~127 is resource manager." repeat 8. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 )(list 0x0 0x14 0x28 0x3C 0x50 0x64 0x78 0x8C ) group.long ($2+0x2100)++0x3 line.long 0x0 "GRP_MGR_$1,Group Manager Register. This register is used to assign group manager for each domain" bitfld.long 0x0 17. "MID_LOCK,Lock write for MID_EN and MID_LOW and MID_HIG registers." "0,1" bitfld.long 0x0 16. "MID_EN,Master ID check enable" "0,1" bitfld.long 0x0 15. "PRI_PER_LOCK,Lock write for PRI_PER and PRI_PER_EN" "0,1" bitfld.long 0x0 13.--14. "PRI_PER,Group manager privileged access permission. bit0 for privileged access bit1 for user access" "0,1,2,3" newline bitfld.long 0x0 12. "PRI_PER_EN,Group manager privileged access permission enable." "0,1" bitfld.long 0x0 11. "SEC_PER_LOCK,Lock for SEC_PER and SEC_PER_LOCK" "0,1" bitfld.long 0x0 9.--10. "SEC_PER,Group manager secure access permission. bit 0 for secure access bit 1 for non-secure access" "0,1,2,3" bitfld.long 0x0 8. "SEC_PER_EN,Group manager secure permission enable" "0,1" bitfld.long 0x0 7. "DID_LOCK,Lock write for DID_EN and DID" "0,1" newline hexmask.long.byte 0x0 3.--6. 1. "DID,Group manager domain ID" bitfld.long 0x0 2. "DID_EN,Group manager Domain ID enable" "0,1" bitfld.long 0x0 1. "GRP_MGR_EN_LOCK,Lock write for GPR_MGR_EN" "0,1" bitfld.long 0x0 0. "GRP_MGR_EN,Group manager enable. When the bit is disable there is no resource manager." "0,1" repeat.end repeat 8. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 )(list 0x0 0x14 0x28 0x3C 0x50 0x64 0x78 0x8C ) group.long ($2+0x2104)++0x3 line.long 0x0 "GRP_MGR_MA0_$1,Assign master 0~31 for group manager 0" hexmask.long 0x0 0.--31. 1. "MID,Assign master 0~31 for resource manager" repeat.end repeat 8. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 )(list 0x0 0x14 0x28 0x3C 0x50 0x64 0x78 0x8C ) group.long ($2+0x2108)++0x3 line.long 0x0 "GRP_MGR_MA1_$1,Assign master 32~63 for group manager 0" hexmask.long 0x0 0.--31. 1. "MID,Indicate if master 32~63 is resource manager." repeat.end repeat 8. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 )(list 0x0 0x14 0x28 0x3C 0x50 0x64 0x78 0x8C ) group.long ($2+0x210C)++0x3 line.long 0x0 "GRP_MGR_MA2_$1,Assign master 64~95 for group manager 0" hexmask.long 0x0 0.--31. 1. "MID,Indicate if master 64~95 is resource manager." repeat.end repeat 8. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 )(list 0x0 0x14 0x28 0x3C 0x50 0x64 0x78 0x8C ) group.long ($2+0x2110)++0x3 line.long 0x0 "GRP_MGR_MA3_$1,Assign master 96~127 for group manager 0" hexmask.long 0x0 0.--31. 1. "MID,Indicate if master 96~127 is resource manager." repeat.end group.long 0x2200++0x3 line.long 0x0 "DOM_GID_0,Indicate which group domain 0 belong to" bitfld.long 0x0 3. "LOCK,Lock write for GID" "0,1" bitfld.long 0x0 0.--2. "GID,Group ID" "0,1,2,3,4,5,6,7" repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x18 0x30 0x48 0x60 0x78 0x90 0xA8 0xC0 0xD8 0xF0 0x108 0x120 0x138 0x150 0x168 ) group.long ($2+0x2204)++0x3 line.long 0x0 "DOM_OWN_$1,Assign owner for function domain 0." bitfld.long 0x0 17. "MID_LOCK,Lock write for MID_EN and MID_LOW and MID_HIG registers." "0,1" bitfld.long 0x0 16. "MID_EN,Master ID check enable" "0,1" bitfld.long 0x0 15. "PRI_PER_LOCK,Lock write for PRI_PER and PRI_PER_EN" "0,1" bitfld.long 0x0 13.--14. "PRI_PER,Group manager privileged access permission. bit0 for privileged access bit1 for user access" "0,1,2,3" newline bitfld.long 0x0 12. "PRI_PER_EN,Group manager privileged access permission enable." "0,1" bitfld.long 0x0 11. "SEC_PER_LOCK,Lock for SEC_PER and SEC_PER_LOCK" "0,1" bitfld.long 0x0 9.--10. "SEC_PER,Domain owner secure access permission. bit 0 for secure access bit 1 for non-secure access" "0,1,2,3" bitfld.long 0x0 8. "SEC_PER_EN,Domain owner secure permission enable" "0,1" newline bitfld.long 0x0 1. "DOM_OWN_EN_LOCK,Lock for DOM_OWN_EN" "0,1" bitfld.long 0x0 0. "DOM_OWN_EN,Domain owner enable. When the bit is disable there is no domain owner." "0,1" repeat.end repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x18 0x30 0x48 0x60 0x78 0x90 0xA8 0xC0 0xD8 0xF0 0x108 0x120 0x138 0x150 0x168 ) group.long ($2+0x2208)++0x3 line.long 0x0 "DOM_OWN_MA0_$1,Assign master 0~31 for domain owner 0" hexmask.long 0x0 0.--31. 1. "MID,Assign master 0~31 for resource manager" repeat.end repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x18 0x30 0x48 0x60 0x78 0x90 0xA8 0xC0 0xD8 0xF0 0x108 0x120 0x138 0x150 0x168 ) group.long ($2+0x220C)++0x3 line.long 0x0 "DOM_OWN_MA1_$1,Assign master 32~63 for domain owner 0" hexmask.long 0x0 0.--31. 1. "MID,Indicate if master 32~63 is resource manager." repeat.end repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x18 0x30 0x48 0x60 0x78 0x90 0xA8 0xC0 0xD8 0xF0 0x108 0x120 0x138 0x150 0x168 ) group.long ($2+0x2210)++0x3 line.long 0x0 "DOM_OWN_MA2_$1,Assign master 64~95 for domain owner 0" hexmask.long 0x0 0.--31. 1. "MID,Indicate if master 64~95 is resource manager." repeat.end repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x18 0x30 0x48 0x60 0x78 0x90 0xA8 0xC0 0xD8 0xF0 0x108 0x120 0x138 0x150 0x168 ) group.long ($2+0x2214)++0x3 line.long 0x0 "DOM_OWN_MA3_$1,Assign master 96~127 for domain owner 0" hexmask.long 0x0 0.--31. 1. "MID,Indicate if master 96~127 is resource manager." repeat.end group.long 0x2218++0x3 line.long 0x0 "DOM_GID_1,Indicate which group domain 1 belong to" bitfld.long 0x0 3. "LOCK,Lock write for GID" "0,1" bitfld.long 0x0 0.--2. "GID,Group ID" "0,1,2,3,4,5,6,7" group.long 0x2230++0x3 line.long 0x0 "DOM_GID_2,Indicate which group domain 2 belong to" bitfld.long 0x0 3. "LOCK,Lock write for GID" "0,1" bitfld.long 0x0 0.--2. "GID,Group ID" "0,1,2,3,4,5,6,7" group.long 0x2248++0x3 line.long 0x0 "DOM_GID_3,Indicate which group domain 3 belong to" bitfld.long 0x0 3. "LOCK,Lock write for GID" "0,1" bitfld.long 0x0 0.--2. "GID,Group ID" "0,1,2,3,4,5,6,7" group.long 0x2260++0x3 line.long 0x0 "DOM_GID_4,Indicate which group domain 4 belong to" bitfld.long 0x0 3. "LOCK,Lock write for GID" "0,1" bitfld.long 0x0 0.--2. "GID,Group ID" "0,1,2,3,4,5,6,7" group.long 0x2278++0x3 line.long 0x0 "DOM_GID_5,Indicate which group domain 5 belong to" bitfld.long 0x0 3. "LOCK,Lock write for GID" "0,1" bitfld.long 0x0 0.--2. "GID,Group ID" "0,1,2,3,4,5,6,7" group.long 0x2290++0x3 line.long 0x0 "DOM_GID_6,Indicate which group domain 6 belong to" bitfld.long 0x0 3. "LOCK,Lock write for GID" "0,1" bitfld.long 0x0 0.--2. "GID,Group ID" "0,1,2,3,4,5,6,7" group.long 0x22A8++0x3 line.long 0x0 "DOM_GID_7,Indicate which group domain 7 belong to" bitfld.long 0x0 3. "LOCK,Lock write for GID" "0,1" bitfld.long 0x0 0.--2. "GID,Group ID" "0,1,2,3,4,5,6,7" group.long 0x22C0++0x3 line.long 0x0 "DOM_GID_8,Indicate which group domain 8 belong to" bitfld.long 0x0 3. "LOCK,Lock write for GID" "0,1" bitfld.long 0x0 0.--2. "GID,Group ID" "0,1,2,3,4,5,6,7" group.long 0x22D8++0x3 line.long 0x0 "DOM_GID_9,Indicate which group domain 9 belong to" bitfld.long 0x0 3. "LOCK,Lock write for GID" "0,1" bitfld.long 0x0 0.--2. "GID,Group ID" "0,1,2,3,4,5,6,7" group.long 0x22F0++0x3 line.long 0x0 "DOM_GID_10,Indicate which group domain 10 belong to" bitfld.long 0x0 3. "LOCK,Lock write for GID" "0,1" bitfld.long 0x0 0.--2. "GID,Group ID" "0,1,2,3,4,5,6,7" group.long 0x2308++0x3 line.long 0x0 "DOM_GID_11,Indicate which group domain 11 belong to" bitfld.long 0x0 3. "LOCK,Lock write for GID" "0,1" bitfld.long 0x0 0.--2. "GID,Group ID" "0,1,2,3,4,5,6,7" group.long 0x2320++0x3 line.long 0x0 "DOM_GID_12,Indicate which group domain 12 belong to" bitfld.long 0x0 3. "LOCK,Lock write for GID" "0,1" bitfld.long 0x0 0.--2. "GID,Group ID" "0,1,2,3,4,5,6,7" group.long 0x2338++0x3 line.long 0x0 "DOM_GID_13,Indicate which group domain 13 belong to" bitfld.long 0x0 3. "LOCK,Lock write for GID" "0,1" bitfld.long 0x0 0.--2. "GID,Group ID" "0,1,2,3,4,5,6,7" group.long 0x2350++0x3 line.long 0x0 "DOM_GID_14,Indicate which group domain 14 belong to" bitfld.long 0x0 3. "LOCK,Lock write for GID" "0,1" bitfld.long 0x0 0.--2. "GID,Group ID" "0,1,2,3,4,5,6,7" group.long 0x2368++0x3 line.long 0x0 "DOM_GID_15,Indicate which group domain 15 belong to" bitfld.long 0x0 3. "LOCK,Lock write for GID" "0,1" bitfld.long 0x0 0.--2. "GID,Group ID" "0,1,2,3,4,5,6,7" repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x34 0x68 0x9C 0xD0 0x104 0x138 0x16C 0x1A0 0x1D4 0x208 0x23C 0x270 0x2A4 0x2D8 0x30C ) group.long ($2+0x2400)++0x3 line.long 0x0 "DOM_PER0_$1,Domain Permission Control. It can be only configured by resource manager and domain owner." bitfld.long 0x0 31. "DOM7_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 29.--30. "DOM7_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 28. "DOM7_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 27. "DOM6_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 25.--26. "DOM6_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" newline bitfld.long 0x0 24. "DOM6_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 23. "DOM5_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 21.--22. "DOM5_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 20. "DOM5_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 19. "DOM4_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" newline bitfld.long 0x0 17.--18. "DOM4_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM4_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 15. "DOM3_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 13.--14. "DOM3_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 12. "DOM3_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" newline bitfld.long 0x0 11. "DOM2_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 9.--10. "DOM2_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM2_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 7. "DOM1_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 5.--6. "DOM1_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" newline bitfld.long 0x0 4. "DOM1_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 3. "DOM0_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 1.--2. "DOM0_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM0_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" repeat.end repeat 16. (list 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1A 0x1B 0x1C 0x1D 0x1E 0x1F )(list 0x340 0x374 0x3A8 0x3DC 0x410 0x444 0x478 0x4AC 0x4E0 0x514 0x548 0x57C 0x5B0 0x5E4 0x618 0x64C ) group.long ($2+0x2400)++0x3 line.long 0x0 "DOM_PER0_$1,Domain Permission Control. It can be only configured by resource manager and domain owner." bitfld.long 0x0 31. "DOM7_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 29.--30. "DOM7_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 28. "DOM7_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 27. "DOM6_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 25.--26. "DOM6_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" newline bitfld.long 0x0 24. "DOM6_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 23. "DOM5_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 21.--22. "DOM5_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 20. "DOM5_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 19. "DOM4_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" newline bitfld.long 0x0 17.--18. "DOM4_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM4_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 15. "DOM3_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 13.--14. "DOM3_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 12. "DOM3_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" newline bitfld.long 0x0 11. "DOM2_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 9.--10. "DOM2_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM2_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 7. "DOM1_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 5.--6. "DOM1_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" newline bitfld.long 0x0 4. "DOM1_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 3. "DOM0_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 1.--2. "DOM0_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM0_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" repeat.end repeat 16. (list 0x20 0x21 0x22 0x23 0x24 0x25 0x26 0x27 0x28 0x29 0x2A 0x2B 0x2C 0x2D 0x2E 0x2F )(list 0x680 0x6B4 0x6E8 0x71C 0x750 0x784 0x7B8 0x7EC 0x820 0x854 0x888 0x8BC 0x8F0 0x924 0x958 0x98C ) group.long ($2+0x2400)++0x3 line.long 0x0 "DOM_PER0_$1,Domain Permission Control. It can be only configured by resource manager and domain owner." bitfld.long 0x0 31. "DOM7_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 29.--30. "DOM7_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 28. "DOM7_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 27. "DOM6_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 25.--26. "DOM6_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" newline bitfld.long 0x0 24. "DOM6_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 23. "DOM5_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 21.--22. "DOM5_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 20. "DOM5_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 19. "DOM4_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" newline bitfld.long 0x0 17.--18. "DOM4_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM4_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 15. "DOM3_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 13.--14. "DOM3_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 12. "DOM3_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" newline bitfld.long 0x0 11. "DOM2_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 9.--10. "DOM2_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM2_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 7. "DOM1_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 5.--6. "DOM1_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" newline bitfld.long 0x0 4. "DOM1_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 3. "DOM0_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 1.--2. "DOM0_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM0_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" repeat.end repeat 16. (list 0x30 0x31 0x32 0x33 0x34 0x35 0x36 0x37 0x38 0x39 0x3A 0x3B 0x3C 0x3D 0x3E 0x3F )(list 0x9C0 0x9F4 0xA28 0xA5C 0xA90 0xAC4 0xAF8 0xB2C 0xB60 0xB94 0xBC8 0xBFC 0xC30 0xC64 0xC98 0xCCC ) group.long ($2+0x2400)++0x3 line.long 0x0 "DOM_PER0_$1,Domain Permission Control. It can be only configured by resource manager and domain owner." bitfld.long 0x0 31. "DOM7_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 29.--30. "DOM7_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 28. "DOM7_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 27. "DOM6_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 25.--26. "DOM6_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" newline bitfld.long 0x0 24. "DOM6_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 23. "DOM5_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 21.--22. "DOM5_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 20. "DOM5_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 19. "DOM4_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" newline bitfld.long 0x0 17.--18. "DOM4_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM4_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 15. "DOM3_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 13.--14. "DOM3_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 12. "DOM3_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" newline bitfld.long 0x0 11. "DOM2_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 9.--10. "DOM2_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM2_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 7. "DOM1_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 5.--6. "DOM1_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" newline bitfld.long 0x0 4. "DOM1_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 3. "DOM0_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 1.--2. "DOM0_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM0_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" repeat.end repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x34 0x68 0x9C 0xD0 0x104 0x138 0x16C 0x1A0 0x1D4 0x208 0x23C 0x270 0x2A4 0x2D8 0x30C ) group.long ($2+0x2404)++0x3 line.long 0x0 "DOM_PER1_$1,Domain Permission Control. It can be only configured by resource manager and domain owner." bitfld.long 0x0 31. "DOM15_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 29.--30. "DOM15_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 28. "DOM15_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 27. "DOM14_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 25.--26. "DOM14_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" newline bitfld.long 0x0 24. "DOM14_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 23. "DOM13_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 21.--22. "DOM13_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 20. "DOM13_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 19. "DOM12_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" newline bitfld.long 0x0 17.--18. "DOM12_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM12_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 15. "DOM11_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 13.--14. "DOM11_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 12. "DOM11_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" newline bitfld.long 0x0 11. "DOM10_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 9.--10. "DOM10_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM10_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 7. "DOM9_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 5.--6. "DOM9_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" newline bitfld.long 0x0 4. "DOM9_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 3. "DOM8_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 1.--2. "DOM8_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM8_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" repeat.end repeat 16. (list 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1A 0x1B 0x1C 0x1D 0x1E 0x1F )(list 0x340 0x374 0x3A8 0x3DC 0x410 0x444 0x478 0x4AC 0x4E0 0x514 0x548 0x57C 0x5B0 0x5E4 0x618 0x64C ) group.long ($2+0x2404)++0x3 line.long 0x0 "DOM_PER1_$1,Domain Permission Control. It can be only configured by resource manager and domain owner." bitfld.long 0x0 31. "DOM15_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 29.--30. "DOM15_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 28. "DOM15_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 27. "DOM14_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 25.--26. "DOM14_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" newline bitfld.long 0x0 24. "DOM14_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 23. "DOM13_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 21.--22. "DOM13_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 20. "DOM13_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 19. "DOM12_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" newline bitfld.long 0x0 17.--18. "DOM12_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM12_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 15. "DOM11_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 13.--14. "DOM11_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 12. "DOM11_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" newline bitfld.long 0x0 11. "DOM10_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 9.--10. "DOM10_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM10_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 7. "DOM9_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 5.--6. "DOM9_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" newline bitfld.long 0x0 4. "DOM9_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 3. "DOM8_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 1.--2. "DOM8_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM8_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" repeat.end repeat 16. (list 0x20 0x21 0x22 0x23 0x24 0x25 0x26 0x27 0x28 0x29 0x2A 0x2B 0x2C 0x2D 0x2E 0x2F )(list 0x680 0x6B4 0x6E8 0x71C 0x750 0x784 0x7B8 0x7EC 0x820 0x854 0x888 0x8BC 0x8F0 0x924 0x958 0x98C ) group.long ($2+0x2404)++0x3 line.long 0x0 "DOM_PER1_$1,Domain Permission Control. It can be only configured by resource manager and domain owner." bitfld.long 0x0 31. "DOM15_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 29.--30. "DOM15_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 28. "DOM15_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 27. "DOM14_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 25.--26. "DOM14_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" newline bitfld.long 0x0 24. "DOM14_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 23. "DOM13_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 21.--22. "DOM13_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 20. "DOM13_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 19. "DOM12_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" newline bitfld.long 0x0 17.--18. "DOM12_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM12_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 15. "DOM11_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 13.--14. "DOM11_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 12. "DOM11_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" newline bitfld.long 0x0 11. "DOM10_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 9.--10. "DOM10_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM10_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 7. "DOM9_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 5.--6. "DOM9_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" newline bitfld.long 0x0 4. "DOM9_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 3. "DOM8_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 1.--2. "DOM8_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM8_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" repeat.end repeat 16. (list 0x30 0x31 0x32 0x33 0x34 0x35 0x36 0x37 0x38 0x39 0x3A 0x3B 0x3C 0x3D 0x3E 0x3F )(list 0x9C0 0x9F4 0xA28 0xA5C 0xA90 0xAC4 0xAF8 0xB2C 0xB60 0xB94 0xBC8 0xBFC 0xC30 0xC64 0xC98 0xCCC ) group.long ($2+0x2404)++0x3 line.long 0x0 "DOM_PER1_$1,Domain Permission Control. It can be only configured by resource manager and domain owner." bitfld.long 0x0 31. "DOM15_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 29.--30. "DOM15_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 28. "DOM15_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 27. "DOM14_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 25.--26. "DOM14_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" newline bitfld.long 0x0 24. "DOM14_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 23. "DOM13_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 21.--22. "DOM13_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 20. "DOM13_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 19. "DOM12_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" newline bitfld.long 0x0 17.--18. "DOM12_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM12_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 15. "DOM11_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 13.--14. "DOM11_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 12. "DOM11_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" newline bitfld.long 0x0 11. "DOM10_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 9.--10. "DOM10_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM10_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 7. "DOM9_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 5.--6. "DOM9_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" newline bitfld.long 0x0 4. "DOM9_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 3. "DOM8_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 1.--2. "DOM8_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM8_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" repeat.end repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x34 0x68 0x9C 0xD0 0x104 0x138 0x16C 0x1A0 0x1D4 0x208 0x23C 0x270 0x2A4 0x2D8 0x30C ) group.long ($2+0x2408)++0x3 line.long 0x0 "SEC_PER0_$1,This register is only used for resource manager to control secure access permission." bitfld.long 0x0 31. "DOM3_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM3_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM3_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM3_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM2_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM2_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM2_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM2_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM1_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM1_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM1_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM1_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM0_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM0_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM0_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM0_SEC_EN,Domain secure permission control enable" "0,1" repeat.end repeat 16. (list 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1A 0x1B 0x1C 0x1D 0x1E 0x1F )(list 0x340 0x374 0x3A8 0x3DC 0x410 0x444 0x478 0x4AC 0x4E0 0x514 0x548 0x57C 0x5B0 0x5E4 0x618 0x64C ) group.long ($2+0x2408)++0x3 line.long 0x0 "SEC_PER0_$1,This register is only used for resource manager to control secure access permission." bitfld.long 0x0 31. "DOM3_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM3_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM3_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM3_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM2_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM2_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM2_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM2_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM1_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM1_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM1_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM1_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM0_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM0_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM0_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM0_SEC_EN,Domain secure permission control enable" "0,1" repeat.end repeat 16. (list 0x20 0x21 0x22 0x23 0x24 0x25 0x26 0x27 0x28 0x29 0x2A 0x2B 0x2C 0x2D 0x2E 0x2F )(list 0x680 0x6B4 0x6E8 0x71C 0x750 0x784 0x7B8 0x7EC 0x820 0x854 0x888 0x8BC 0x8F0 0x924 0x958 0x98C ) group.long ($2+0x2408)++0x3 line.long 0x0 "SEC_PER0_$1,This register is only used for resource manager to control secure access permission." bitfld.long 0x0 31. "DOM3_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM3_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM3_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM3_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM2_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM2_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM2_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM2_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM1_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM1_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM1_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM1_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM0_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM0_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM0_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM0_SEC_EN,Domain secure permission control enable" "0,1" repeat.end repeat 16. (list 0x30 0x31 0x32 0x33 0x34 0x35 0x36 0x37 0x38 0x39 0x3A 0x3B 0x3C 0x3D 0x3E 0x3F )(list 0x9C0 0x9F4 0xA28 0xA5C 0xA90 0xAC4 0xAF8 0xB2C 0xB60 0xB94 0xBC8 0xBFC 0xC30 0xC64 0xC98 0xCCC ) group.long ($2+0x2408)++0x3 line.long 0x0 "SEC_PER0_$1,This register is only used for resource manager to control secure access permission." bitfld.long 0x0 31. "DOM3_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM3_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM3_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM3_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM2_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM2_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM2_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM2_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM1_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM1_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM1_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM1_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM0_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM0_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM0_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM0_SEC_EN,Domain secure permission control enable" "0,1" repeat.end repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x34 0x68 0x9C 0xD0 0x104 0x138 0x16C 0x1A0 0x1D4 0x208 0x23C 0x270 0x2A4 0x2D8 0x30C ) group.long ($2+0x240C)++0x3 line.long 0x0 "SEC_PER1_$1,This register is only used for resource manager to control secure access permission." bitfld.long 0x0 31. "DOM7_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM7_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM7_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM7_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM6_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM6_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM6_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM6_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM5_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM5_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM5_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM5_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM4_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM4_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM4_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM4_SEC_EN,Domain secure permission control enable" "0,1" repeat.end repeat 16. (list 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1A 0x1B 0x1C 0x1D 0x1E 0x1F )(list 0x340 0x374 0x3A8 0x3DC 0x410 0x444 0x478 0x4AC 0x4E0 0x514 0x548 0x57C 0x5B0 0x5E4 0x618 0x64C ) group.long ($2+0x240C)++0x3 line.long 0x0 "SEC_PER1_$1,This register is only used for resource manager to control secure access permission." bitfld.long 0x0 31. "DOM7_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM7_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM7_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM7_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM6_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM6_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM6_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM6_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM5_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM5_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM5_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM5_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM4_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM4_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM4_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM4_SEC_EN,Domain secure permission control enable" "0,1" repeat.end repeat 16. (list 0x20 0x21 0x22 0x23 0x24 0x25 0x26 0x27 0x28 0x29 0x2A 0x2B 0x2C 0x2D 0x2E 0x2F )(list 0x680 0x6B4 0x6E8 0x71C 0x750 0x784 0x7B8 0x7EC 0x820 0x854 0x888 0x8BC 0x8F0 0x924 0x958 0x98C ) group.long ($2+0x240C)++0x3 line.long 0x0 "SEC_PER1_$1,This register is only used for resource manager to control secure access permission." bitfld.long 0x0 31. "DOM7_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM7_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM7_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM7_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM6_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM6_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM6_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM6_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM5_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM5_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM5_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM5_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM4_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM4_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM4_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM4_SEC_EN,Domain secure permission control enable" "0,1" repeat.end repeat 16. (list 0x30 0x31 0x32 0x33 0x34 0x35 0x36 0x37 0x38 0x39 0x3A 0x3B 0x3C 0x3D 0x3E 0x3F )(list 0x9C0 0x9F4 0xA28 0xA5C 0xA90 0xAC4 0xAF8 0xB2C 0xB60 0xB94 0xBC8 0xBFC 0xC30 0xC64 0xC98 0xCCC ) group.long ($2+0x240C)++0x3 line.long 0x0 "SEC_PER1_$1,This register is only used for resource manager to control secure access permission." bitfld.long 0x0 31. "DOM7_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM7_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM7_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM7_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM6_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM6_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM6_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM6_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM5_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM5_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM5_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM5_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM4_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM4_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM4_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM4_SEC_EN,Domain secure permission control enable" "0,1" repeat.end repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x34 0x68 0x9C 0xD0 0x104 0x138 0x16C 0x1A0 0x1D4 0x208 0x23C 0x270 0x2A4 0x2D8 0x30C ) group.long ($2+0x2410)++0x3 line.long 0x0 "SEC_PER2_$1,This register is only used for resource manager to control secure access permission." bitfld.long 0x0 31. "DOM11_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM11_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM11_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM11_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM10_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM10_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM10_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM10_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM9_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM9_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM9_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM9_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM8_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM8_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM8_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM8_SEC_EN,Domain secure permission control enable" "0,1" repeat.end repeat 16. (list 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1A 0x1B 0x1C 0x1D 0x1E 0x1F )(list 0x340 0x374 0x3A8 0x3DC 0x410 0x444 0x478 0x4AC 0x4E0 0x514 0x548 0x57C 0x5B0 0x5E4 0x618 0x64C ) group.long ($2+0x2410)++0x3 line.long 0x0 "SEC_PER2_$1,This register is only used for resource manager to control secure access permission." bitfld.long 0x0 31. "DOM11_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM11_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM11_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM11_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM10_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM10_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM10_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM10_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM9_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM9_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM9_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM9_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM8_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM8_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM8_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM8_SEC_EN,Domain secure permission control enable" "0,1" repeat.end repeat 16. (list 0x20 0x21 0x22 0x23 0x24 0x25 0x26 0x27 0x28 0x29 0x2A 0x2B 0x2C 0x2D 0x2E 0x2F )(list 0x680 0x6B4 0x6E8 0x71C 0x750 0x784 0x7B8 0x7EC 0x820 0x854 0x888 0x8BC 0x8F0 0x924 0x958 0x98C ) group.long ($2+0x2410)++0x3 line.long 0x0 "SEC_PER2_$1,This register is only used for resource manager to control secure access permission." bitfld.long 0x0 31. "DOM11_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM11_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM11_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM11_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM10_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM10_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM10_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM10_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM9_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM9_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM9_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM9_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM8_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM8_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM8_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM8_SEC_EN,Domain secure permission control enable" "0,1" repeat.end repeat 16. (list 0x30 0x31 0x32 0x33 0x34 0x35 0x36 0x37 0x38 0x39 0x3A 0x3B 0x3C 0x3D 0x3E 0x3F )(list 0x9C0 0x9F4 0xA28 0xA5C 0xA90 0xAC4 0xAF8 0xB2C 0xB60 0xB94 0xBC8 0xBFC 0xC30 0xC64 0xC98 0xCCC ) group.long ($2+0x2410)++0x3 line.long 0x0 "SEC_PER2_$1,This register is only used for resource manager to control secure access permission." bitfld.long 0x0 31. "DOM11_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM11_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM11_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM11_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM10_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM10_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM10_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM10_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM9_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM9_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM9_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM9_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM8_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM8_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM8_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM8_SEC_EN,Domain secure permission control enable" "0,1" repeat.end repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x34 0x68 0x9C 0xD0 0x104 0x138 0x16C 0x1A0 0x1D4 0x208 0x23C 0x270 0x2A4 0x2D8 0x30C ) group.long ($2+0x2414)++0x3 line.long 0x0 "SEC_PER3_$1,This register is only used for resource manager to control secure access permission." bitfld.long 0x0 31. "DOM15_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM15_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM15_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM15_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM14_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM14_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM14_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM14_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM13_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM13_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM13_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM13_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM12_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM12_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM12_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM12_SEC_EN,Domain secure permission control enable" "0,1" repeat.end repeat 16. (list 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1A 0x1B 0x1C 0x1D 0x1E 0x1F )(list 0x340 0x374 0x3A8 0x3DC 0x410 0x444 0x478 0x4AC 0x4E0 0x514 0x548 0x57C 0x5B0 0x5E4 0x618 0x64C ) group.long ($2+0x2414)++0x3 line.long 0x0 "SEC_PER3_$1,This register is only used for resource manager to control secure access permission." bitfld.long 0x0 31. "DOM15_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM15_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM15_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM15_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM14_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM14_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM14_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM14_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM13_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM13_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM13_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM13_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM12_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM12_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM12_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM12_SEC_EN,Domain secure permission control enable" "0,1" repeat.end repeat 16. (list 0x20 0x21 0x22 0x23 0x24 0x25 0x26 0x27 0x28 0x29 0x2A 0x2B 0x2C 0x2D 0x2E 0x2F )(list 0x680 0x6B4 0x6E8 0x71C 0x750 0x784 0x7B8 0x7EC 0x820 0x854 0x888 0x8BC 0x8F0 0x924 0x958 0x98C ) group.long ($2+0x2414)++0x3 line.long 0x0 "SEC_PER3_$1,This register is only used for resource manager to control secure access permission." bitfld.long 0x0 31. "DOM15_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM15_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM15_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM15_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM14_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM14_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM14_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM14_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM13_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM13_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM13_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM13_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM12_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM12_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM12_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM12_SEC_EN,Domain secure permission control enable" "0,1" repeat.end repeat 16. (list 0x30 0x31 0x32 0x33 0x34 0x35 0x36 0x37 0x38 0x39 0x3A 0x3B 0x3C 0x3D 0x3E 0x3F )(list 0x9C0 0x9F4 0xA28 0xA5C 0xA90 0xAC4 0xAF8 0xB2C 0xB60 0xB94 0xBC8 0xBFC 0xC30 0xC64 0xC98 0xCCC ) group.long ($2+0x2414)++0x3 line.long 0x0 "SEC_PER3_$1,This register is only used for resource manager to control secure access permission." bitfld.long 0x0 31. "DOM15_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM15_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM15_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM15_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM14_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM14_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM14_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM14_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM13_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM13_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM13_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM13_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM12_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM12_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM12_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM12_SEC_EN,Domain secure permission control enable" "0,1" repeat.end repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x34 0x68 0x9C 0xD0 0x104 0x138 0x16C 0x1A0 0x1D4 0x208 0x23C 0x270 0x2A4 0x2D8 0x30C ) group.long ($2+0x2418)++0x3 line.long 0x0 "PRI_PER0_$1,This register is only used for resource manager to control privileged access permission." bitfld.long 0x0 31. "DOM3_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM3_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM3_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM3_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM2_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM2_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM2_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM2_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM1_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM1_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM1_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM1_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM0_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM0_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM0_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM0_PRI_EN,Domain privileged permission control enable" "0,1" repeat.end repeat 16. (list 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1A 0x1B 0x1C 0x1D 0x1E 0x1F )(list 0x340 0x374 0x3A8 0x3DC 0x410 0x444 0x478 0x4AC 0x4E0 0x514 0x548 0x57C 0x5B0 0x5E4 0x618 0x64C ) group.long ($2+0x2418)++0x3 line.long 0x0 "PRI_PER0_$1,This register is only used for resource manager to control privileged access permission." bitfld.long 0x0 31. "DOM3_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM3_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM3_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM3_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM2_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM2_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM2_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM2_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM1_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM1_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM1_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM1_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM0_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM0_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM0_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM0_PRI_EN,Domain privileged permission control enable" "0,1" repeat.end repeat 16. (list 0x20 0x21 0x22 0x23 0x24 0x25 0x26 0x27 0x28 0x29 0x2A 0x2B 0x2C 0x2D 0x2E 0x2F )(list 0x680 0x6B4 0x6E8 0x71C 0x750 0x784 0x7B8 0x7EC 0x820 0x854 0x888 0x8BC 0x8F0 0x924 0x958 0x98C ) group.long ($2+0x2418)++0x3 line.long 0x0 "PRI_PER0_$1,This register is only used for resource manager to control privileged access permission." bitfld.long 0x0 31. "DOM3_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM3_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM3_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM3_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM2_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM2_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM2_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM2_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM1_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM1_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM1_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM1_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM0_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM0_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM0_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM0_PRI_EN,Domain privileged permission control enable" "0,1" repeat.end repeat 16. (list 0x30 0x31 0x32 0x33 0x34 0x35 0x36 0x37 0x38 0x39 0x3A 0x3B 0x3C 0x3D 0x3E 0x3F )(list 0x9C0 0x9F4 0xA28 0xA5C 0xA90 0xAC4 0xAF8 0xB2C 0xB60 0xB94 0xBC8 0xBFC 0xC30 0xC64 0xC98 0xCCC ) group.long ($2+0x2418)++0x3 line.long 0x0 "PRI_PER0_$1,This register is only used for resource manager to control privileged access permission." bitfld.long 0x0 31. "DOM3_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM3_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM3_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM3_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM2_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM2_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM2_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM2_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM1_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM1_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM1_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM1_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM0_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM0_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM0_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM0_PRI_EN,Domain privileged permission control enable" "0,1" repeat.end repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x34 0x68 0x9C 0xD0 0x104 0x138 0x16C 0x1A0 0x1D4 0x208 0x23C 0x270 0x2A4 0x2D8 0x30C ) group.long ($2+0x241C)++0x3 line.long 0x0 "PRI_PER1_$1,This register is only used for resource manager to control privileged access permission." bitfld.long 0x0 31. "DOM7_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM7_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM7_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM7_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM6_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM6_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM6_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM6_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM5_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM5_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM5_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM5_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM4_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM4_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM4_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM4_PRI_EN,Domain privileged permission control enable" "0,1" repeat.end repeat 16. (list 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1A 0x1B 0x1C 0x1D 0x1E 0x1F )(list 0x340 0x374 0x3A8 0x3DC 0x410 0x444 0x478 0x4AC 0x4E0 0x514 0x548 0x57C 0x5B0 0x5E4 0x618 0x64C ) group.long ($2+0x241C)++0x3 line.long 0x0 "PRI_PER1_$1,This register is only used for resource manager to control privileged access permission." bitfld.long 0x0 31. "DOM7_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM7_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM7_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM7_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM6_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM6_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM6_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM6_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM5_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM5_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM5_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM5_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM4_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM4_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM4_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM4_PRI_EN,Domain privileged permission control enable" "0,1" repeat.end repeat 16. (list 0x20 0x21 0x22 0x23 0x24 0x25 0x26 0x27 0x28 0x29 0x2A 0x2B 0x2C 0x2D 0x2E 0x2F )(list 0x680 0x6B4 0x6E8 0x71C 0x750 0x784 0x7B8 0x7EC 0x820 0x854 0x888 0x8BC 0x8F0 0x924 0x958 0x98C ) group.long ($2+0x241C)++0x3 line.long 0x0 "PRI_PER1_$1,This register is only used for resource manager to control privileged access permission." bitfld.long 0x0 31. "DOM7_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM7_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM7_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM7_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM6_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM6_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM6_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM6_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM5_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM5_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM5_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM5_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM4_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM4_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM4_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM4_PRI_EN,Domain privileged permission control enable" "0,1" repeat.end repeat 16. (list 0x30 0x31 0x32 0x33 0x34 0x35 0x36 0x37 0x38 0x39 0x3A 0x3B 0x3C 0x3D 0x3E 0x3F )(list 0x9C0 0x9F4 0xA28 0xA5C 0xA90 0xAC4 0xAF8 0xB2C 0xB60 0xB94 0xBC8 0xBFC 0xC30 0xC64 0xC98 0xCCC ) group.long ($2+0x241C)++0x3 line.long 0x0 "PRI_PER1_$1,This register is only used for resource manager to control privileged access permission." bitfld.long 0x0 31. "DOM7_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM7_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM7_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM7_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM6_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM6_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM6_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM6_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM5_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM5_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM5_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM5_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM4_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM4_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM4_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM4_PRI_EN,Domain privileged permission control enable" "0,1" repeat.end repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x34 0x68 0x9C 0xD0 0x104 0x138 0x16C 0x1A0 0x1D4 0x208 0x23C 0x270 0x2A4 0x2D8 0x30C ) group.long ($2+0x2420)++0x3 line.long 0x0 "PRI_PER2_$1,This register is only used for resource manager to control privileged access permission." bitfld.long 0x0 31. "DOM11_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM11_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM11_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM11_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM10_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM10_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM10_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM10_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM9_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM9_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM9_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM9_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM8_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM8_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM8_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM8_PRI_EN,Domain privileged permission control enable" "0,1" repeat.end repeat 16. (list 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1A 0x1B 0x1C 0x1D 0x1E 0x1F )(list 0x340 0x374 0x3A8 0x3DC 0x410 0x444 0x478 0x4AC 0x4E0 0x514 0x548 0x57C 0x5B0 0x5E4 0x618 0x64C ) group.long ($2+0x2420)++0x3 line.long 0x0 "PRI_PER2_$1,This register is only used for resource manager to control privileged access permission." bitfld.long 0x0 31. "DOM11_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM11_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM11_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM11_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM10_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM10_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM10_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM10_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM9_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM9_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM9_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM9_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM8_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM8_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM8_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM8_PRI_EN,Domain privileged permission control enable" "0,1" repeat.end repeat 16. (list 0x20 0x21 0x22 0x23 0x24 0x25 0x26 0x27 0x28 0x29 0x2A 0x2B 0x2C 0x2D 0x2E 0x2F )(list 0x680 0x6B4 0x6E8 0x71C 0x750 0x784 0x7B8 0x7EC 0x820 0x854 0x888 0x8BC 0x8F0 0x924 0x958 0x98C ) group.long ($2+0x2420)++0x3 line.long 0x0 "PRI_PER2_$1,This register is only used for resource manager to control privileged access permission." bitfld.long 0x0 31. "DOM11_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM11_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM11_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM11_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM10_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM10_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM10_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM10_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM9_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM9_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM9_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM9_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM8_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM8_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM8_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM8_PRI_EN,Domain privileged permission control enable" "0,1" repeat.end repeat 16. (list 0x30 0x31 0x32 0x33 0x34 0x35 0x36 0x37 0x38 0x39 0x3A 0x3B 0x3C 0x3D 0x3E 0x3F )(list 0x9C0 0x9F4 0xA28 0xA5C 0xA90 0xAC4 0xAF8 0xB2C 0xB60 0xB94 0xBC8 0xBFC 0xC30 0xC64 0xC98 0xCCC ) group.long ($2+0x2420)++0x3 line.long 0x0 "PRI_PER2_$1,This register is only used for resource manager to control privileged access permission." bitfld.long 0x0 31. "DOM11_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM11_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM11_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM11_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM10_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM10_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM10_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM10_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM9_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM9_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM9_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM9_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM8_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM8_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM8_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM8_PRI_EN,Domain privileged permission control enable" "0,1" repeat.end repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x34 0x68 0x9C 0xD0 0x104 0x138 0x16C 0x1A0 0x1D4 0x208 0x23C 0x270 0x2A4 0x2D8 0x30C ) group.long ($2+0x2424)++0x3 line.long 0x0 "PRI_PER3_$1,This register is only used for resource manager to control privileged access permission." bitfld.long 0x0 31. "DOM15_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM15_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM15_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM15_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM14_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM14_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM14_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM14_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM13_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM13_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM13_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM13_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM12_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM12_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM12_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM12_PRI_EN,Domain privileged permission control enable" "0,1" repeat.end repeat 16. (list 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1A 0x1B 0x1C 0x1D 0x1E 0x1F )(list 0x340 0x374 0x3A8 0x3DC 0x410 0x444 0x478 0x4AC 0x4E0 0x514 0x548 0x57C 0x5B0 0x5E4 0x618 0x64C ) group.long ($2+0x2424)++0x3 line.long 0x0 "PRI_PER3_$1,This register is only used for resource manager to control privileged access permission." bitfld.long 0x0 31. "DOM15_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM15_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM15_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM15_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM14_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM14_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM14_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM14_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM13_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM13_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM13_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM13_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM12_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM12_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM12_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM12_PRI_EN,Domain privileged permission control enable" "0,1" repeat.end repeat 16. (list 0x20 0x21 0x22 0x23 0x24 0x25 0x26 0x27 0x28 0x29 0x2A 0x2B 0x2C 0x2D 0x2E 0x2F )(list 0x680 0x6B4 0x6E8 0x71C 0x750 0x784 0x7B8 0x7EC 0x820 0x854 0x888 0x8BC 0x8F0 0x924 0x958 0x98C ) group.long ($2+0x2424)++0x3 line.long 0x0 "PRI_PER3_$1,This register is only used for resource manager to control privileged access permission." bitfld.long 0x0 31. "DOM15_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM15_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM15_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM15_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM14_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM14_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM14_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM14_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM13_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM13_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM13_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM13_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM12_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM12_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM12_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM12_PRI_EN,Domain privileged permission control enable" "0,1" repeat.end repeat 16. (list 0x30 0x31 0x32 0x33 0x34 0x35 0x36 0x37 0x38 0x39 0x3A 0x3B 0x3C 0x3D 0x3E 0x3F )(list 0x9C0 0x9F4 0xA28 0xA5C 0xA90 0xAC4 0xAF8 0xB2C 0xB60 0xB94 0xBC8 0xBFC 0xC30 0xC64 0xC98 0xCCC ) group.long ($2+0x2424)++0x3 line.long 0x0 "PRI_PER3_$1,This register is only used for resource manager to control privileged access permission." bitfld.long 0x0 31. "DOM15_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM15_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM15_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM15_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM14_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM14_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM14_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM14_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM13_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM13_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM13_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM13_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM12_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM12_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM12_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM12_PRI_EN,Domain privileged permission control enable" "0,1" repeat.end repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x34 0x68 0x9C 0xD0 0x104 0x138 0x16C 0x1A0 0x1D4 0x208 0x23C 0x270 0x2A4 0x2D8 0x30C ) group.long ($2+0x2428)++0x3 line.long 0x0 "DOM_SEC_PER_$1,This register is only used for domain master to control secure access permission. When the domain master write this register. it only changes the secure permission for itself. When the domain master read this register. it gets permission.." bitfld.long 0x0 7. "DOM_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" newline bitfld.long 0x0 0. "DOM_SEC_EN,Domain secure permission control enable" "0,1" repeat.end repeat 16. (list 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1A 0x1B 0x1C 0x1D 0x1E 0x1F )(list 0x340 0x374 0x3A8 0x3DC 0x410 0x444 0x478 0x4AC 0x4E0 0x514 0x548 0x57C 0x5B0 0x5E4 0x618 0x64C ) group.long ($2+0x2428)++0x3 line.long 0x0 "DOM_SEC_PER_$1,This register is only used for domain master to control secure access permission. When the domain master write this register. it only changes the secure permission for itself. When the domain master read this register. it gets permission.." bitfld.long 0x0 7. "DOM_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" newline bitfld.long 0x0 0. "DOM_SEC_EN,Domain secure permission control enable" "0,1" repeat.end repeat 16. (list 0x20 0x21 0x22 0x23 0x24 0x25 0x26 0x27 0x28 0x29 0x2A 0x2B 0x2C 0x2D 0x2E 0x2F )(list 0x680 0x6B4 0x6E8 0x71C 0x750 0x784 0x7B8 0x7EC 0x820 0x854 0x888 0x8BC 0x8F0 0x924 0x958 0x98C ) group.long ($2+0x2428)++0x3 line.long 0x0 "DOM_SEC_PER_$1,This register is only used for domain master to control secure access permission. When the domain master write this register. it only changes the secure permission for itself. When the domain master read this register. it gets permission.." bitfld.long 0x0 7. "DOM_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" newline bitfld.long 0x0 0. "DOM_SEC_EN,Domain secure permission control enable" "0,1" repeat.end repeat 16. (list 0x30 0x31 0x32 0x33 0x34 0x35 0x36 0x37 0x38 0x39 0x3A 0x3B 0x3C 0x3D 0x3E 0x3F )(list 0x9C0 0x9F4 0xA28 0xA5C 0xA90 0xAC4 0xAF8 0xB2C 0xB60 0xB94 0xBC8 0xBFC 0xC30 0xC64 0xC98 0xCCC ) group.long ($2+0x2428)++0x3 line.long 0x0 "DOM_SEC_PER_$1,This register is only used for domain master to control secure access permission. When the domain master write this register. it only changes the secure permission for itself. When the domain master read this register. it gets permission.." bitfld.long 0x0 7. "DOM_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" newline bitfld.long 0x0 0. "DOM_SEC_EN,Domain secure permission control enable" "0,1" repeat.end repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x34 0x68 0x9C 0xD0 0x104 0x138 0x16C 0x1A0 0x1D4 0x208 0x23C 0x270 0x2A4 0x2D8 0x30C ) group.long ($2+0x242C)++0x3 line.long 0x0 "DOM_PRI_PER_$1,This register is only used for domain master to control secure access permission. When the domain master write this register. it only changes the secure permission for itself. When the domain master read this register. it gets permission.." bitfld.long 0x0 7. "DOM_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" newline bitfld.long 0x0 0. "DOM_PRI_EN,Domain privileged permission control enable" "0,1" repeat.end repeat 16. (list 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1A 0x1B 0x1C 0x1D 0x1E 0x1F )(list 0x340 0x374 0x3A8 0x3DC 0x410 0x444 0x478 0x4AC 0x4E0 0x514 0x548 0x57C 0x5B0 0x5E4 0x618 0x64C ) group.long ($2+0x242C)++0x3 line.long 0x0 "DOM_PRI_PER_$1,This register is only used for domain master to control secure access permission. When the domain master write this register. it only changes the secure permission for itself. When the domain master read this register. it gets permission.." bitfld.long 0x0 7. "DOM_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" newline bitfld.long 0x0 0. "DOM_PRI_EN,Domain privileged permission control enable" "0,1" repeat.end repeat 16. (list 0x20 0x21 0x22 0x23 0x24 0x25 0x26 0x27 0x28 0x29 0x2A 0x2B 0x2C 0x2D 0x2E 0x2F )(list 0x680 0x6B4 0x6E8 0x71C 0x750 0x784 0x7B8 0x7EC 0x820 0x854 0x888 0x8BC 0x8F0 0x924 0x958 0x98C ) group.long ($2+0x242C)++0x3 line.long 0x0 "DOM_PRI_PER_$1,This register is only used for domain master to control secure access permission. When the domain master write this register. it only changes the secure permission for itself. When the domain master read this register. it gets permission.." bitfld.long 0x0 7. "DOM_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" newline bitfld.long 0x0 0. "DOM_PRI_EN,Domain privileged permission control enable" "0,1" repeat.end repeat 16. (list 0x30 0x31 0x32 0x33 0x34 0x35 0x36 0x37 0x38 0x39 0x3A 0x3B 0x3C 0x3D 0x3E 0x3F )(list 0x9C0 0x9F4 0xA28 0xA5C 0xA90 0xAC4 0xAF8 0xB2C 0xB60 0xB94 0xBC8 0xBFC 0xC30 0xC64 0xC98 0xCCC ) group.long ($2+0x242C)++0x3 line.long 0x0 "DOM_PRI_PER_$1,This register is only used for domain master to control secure access permission. When the domain master write this register. it only changes the secure permission for itself. When the domain master read this register. it gets permission.." bitfld.long 0x0 7. "DOM_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" newline bitfld.long 0x0 0. "DOM_PRI_EN,Domain privileged permission control enable" "0,1" repeat.end repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x34 0x68 0x9C 0xD0 0x104 0x138 0x16C 0x1A0 0x1D4 0x208 0x23C 0x270 0x2A4 0x2D8 0x30C ) group.long ($2+0x2430)++0x3 line.long 0x0 "DOM_ASSIGN_$1,Use to assign domain for accessing DOM_SEC_PER and DOM_PRI_PER register. Only resource manager. group manager and domain owner can access this register. For write. group manager must write its owen domain ID. otherwise write accessing will.." hexmask.long.byte 0x0 0.--3. 1. "DID,accessing DOM_SEC_PER and DOM_PRI_PER register" repeat.end repeat 16. (list 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1A 0x1B 0x1C 0x1D 0x1E 0x1F )(list 0x340 0x374 0x3A8 0x3DC 0x410 0x444 0x478 0x4AC 0x4E0 0x514 0x548 0x57C 0x5B0 0x5E4 0x618 0x64C ) group.long ($2+0x2430)++0x3 line.long 0x0 "DOM_ASSIGN_$1,Use to assign domain for accessing DOM_SEC_PER and DOM_PRI_PER register. Only resource manager. group manager and domain owner can access this register. For write. group manager must write its owen domain ID. otherwise write accessing will.." hexmask.long.byte 0x0 0.--3. 1. "DID,accessing DOM_SEC_PER and DOM_PRI_PER register" repeat.end repeat 16. (list 0x20 0x21 0x22 0x23 0x24 0x25 0x26 0x27 0x28 0x29 0x2A 0x2B 0x2C 0x2D 0x2E 0x2F )(list 0x680 0x6B4 0x6E8 0x71C 0x750 0x784 0x7B8 0x7EC 0x820 0x854 0x888 0x8BC 0x8F0 0x924 0x958 0x98C ) group.long ($2+0x2430)++0x3 line.long 0x0 "DOM_ASSIGN_$1,Use to assign domain for accessing DOM_SEC_PER and DOM_PRI_PER register. Only resource manager. group manager and domain owner can access this register. For write. group manager must write its owen domain ID. otherwise write accessing will.." hexmask.long.byte 0x0 0.--3. 1. "DID,accessing DOM_SEC_PER and DOM_PRI_PER register" repeat.end repeat 16. (list 0x30 0x31 0x32 0x33 0x34 0x35 0x36 0x37 0x38 0x39 0x3A 0x3B 0x3C 0x3D 0x3E 0x3F )(list 0x9C0 0x9F4 0xA28 0xA5C 0xA90 0xAC4 0xAF8 0xB2C 0xB60 0xB94 0xBC8 0xBFC 0xC30 0xC64 0xC98 0xCCC ) group.long ($2+0x2430)++0x3 line.long 0x0 "DOM_ASSIGN_$1,Use to assign domain for accessing DOM_SEC_PER and DOM_PRI_PER register. Only resource manager. group manager and domain owner can access this register. For write. group manager must write its owen domain ID. otherwise write accessing will.." hexmask.long.byte 0x0 0.--3. 1. "DID,accessing DOM_SEC_PER and DOM_PRI_PER register" repeat.end repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x38 0x70 0xA8 0xE0 0x118 0x150 0x188 0x1C0 0x1F8 0x230 0x268 0x2A0 0x2D8 0x310 0x348 ) group.long ($2+0x3100)++0x3 line.long 0x0 "RGN_DOM_$1,Assign domain for peripheral. It can be only configured by resource and group manager" bitfld.long 0x0 31. "LOCK,When this bit is set lock write for all the bits in the register." "0,1" bitfld.long 0x0 4. "SET,Set together with DID would change permission of this resource to following setting: 1) Domain access control enabled. 2) Read/Write allowed for the domain owner. 3) Read/Write not allowed for all the other domains. If this bit is not set only DID.." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Assign domain for peripheral" repeat.end repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x38 0x70 0xA8 0xE0 0x118 0x150 0x188 0x1C0 0x1F8 0x230 0x268 0x2A0 0x2D8 0x310 0x348 ) group.long ($2+0x3104)++0x3 line.long 0x0 "RGN_DOM_PER0_$1,Domain Permission Control. It can be only configured by resource manager and domain owner." bitfld.long 0x0 31. "DOM7_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 29.--30. "DOM7_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 28. "DOM7_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 27. "DOM6_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 25.--26. "DOM6_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" newline bitfld.long 0x0 24. "DOM6_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 23. "DOM5_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 21.--22. "DOM5_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 20. "DOM5_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 19. "DOM4_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" newline bitfld.long 0x0 17.--18. "DOM4_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM4_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 15. "DOM3_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 13.--14. "DOM3_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 12. "DOM3_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" newline bitfld.long 0x0 11. "DOM2_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 9.--10. "DOM2_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM2_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 7. "DOM1_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 5.--6. "DOM1_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" newline bitfld.long 0x0 4. "DOM1_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 3. "DOM0_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 1.--2. "DOM0_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM0_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" repeat.end repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x38 0x70 0xA8 0xE0 0x118 0x150 0x188 0x1C0 0x1F8 0x230 0x268 0x2A0 0x2D8 0x310 0x348 ) group.long ($2+0x3108)++0x3 line.long 0x0 "RGN_DOM_PER1_$1,Domain Permission Control. It can be only configured by resource manager and domain owner." bitfld.long 0x0 31. "DOM15_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 29.--30. "DOM15_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 28. "DOM15_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 27. "DOM14_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 25.--26. "DOM14_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" newline bitfld.long 0x0 24. "DOM14_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 23. "DOM13_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 21.--22. "DOM13_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 20. "DOM13_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 19. "DOM12_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" newline bitfld.long 0x0 17.--18. "DOM12_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM12_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 15. "DOM11_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 13.--14. "DOM11_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 12. "DOM11_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" newline bitfld.long 0x0 11. "DOM10_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 9.--10. "DOM10_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM10_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 7. "DOM9_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 5.--6. "DOM9_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" newline bitfld.long 0x0 4. "DOM9_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 3. "DOM8_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 1.--2. "DOM8_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM8_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" repeat.end repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x38 0x70 0xA8 0xE0 0x118 0x150 0x188 0x1C0 0x1F8 0x230 0x268 0x2A0 0x2D8 0x310 0x348 ) group.long ($2+0x310C)++0x3 line.long 0x0 "RGN_SEC_PER0_$1,This register is only used for resource manager to control secure access permission." bitfld.long 0x0 31. "DOM3_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM3_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM3_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM3_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM2_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM2_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM2_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM2_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM1_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM1_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM1_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM1_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM0_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM0_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM0_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM0_SEC_EN,Domain secure permission control enable" "0,1" repeat.end repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x38 0x70 0xA8 0xE0 0x118 0x150 0x188 0x1C0 0x1F8 0x230 0x268 0x2A0 0x2D8 0x310 0x348 ) group.long ($2+0x3110)++0x3 line.long 0x0 "RGN_SEC_PER1_$1,This register is only used for resource manager to control secure access permission." bitfld.long 0x0 31. "DOM7_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM7_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM7_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM7_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM6_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM6_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM6_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM6_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM5_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM5_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM5_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM5_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM4_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM4_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM4_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM4_SEC_EN,Domain secure permission control enable" "0,1" repeat.end repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x38 0x70 0xA8 0xE0 0x118 0x150 0x188 0x1C0 0x1F8 0x230 0x268 0x2A0 0x2D8 0x310 0x348 ) group.long ($2+0x3114)++0x3 line.long 0x0 "RGN_SEC_PER2_$1,This register is only used for resource manager to control secure access permission." bitfld.long 0x0 31. "DOM11_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM11_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM11_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM11_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM10_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM10_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM10_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM10_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM9_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM9_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM9_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM9_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM8_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM8_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM8_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM8_SEC_EN,Domain secure permission control enable" "0,1" repeat.end repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x38 0x70 0xA8 0xE0 0x118 0x150 0x188 0x1C0 0x1F8 0x230 0x268 0x2A0 0x2D8 0x310 0x348 ) group.long ($2+0x3118)++0x3 line.long 0x0 "RGN_SEC_PER3_$1,This register is only used for resource manager to control secure access permission." bitfld.long 0x0 31. "DOM15_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM15_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM15_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM15_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM14_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM14_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM14_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM14_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM13_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM13_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM13_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM13_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM12_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM12_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM12_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM12_SEC_EN,Domain secure permission control enable" "0,1" repeat.end repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x38 0x70 0xA8 0xE0 0x118 0x150 0x188 0x1C0 0x1F8 0x230 0x268 0x2A0 0x2D8 0x310 0x348 ) group.long ($2+0x311C)++0x3 line.long 0x0 "RGN_PRI_PER0_$1,This register is only used for resource manager to control privileged access permission." bitfld.long 0x0 31. "DOM3_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM3_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM3_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM3_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM2_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM2_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM2_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM2_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM1_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM1_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM1_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM1_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM0_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM0_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM0_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM0_PRI_EN,Domain privileged permission control enable" "0,1" repeat.end repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x38 0x70 0xA8 0xE0 0x118 0x150 0x188 0x1C0 0x1F8 0x230 0x268 0x2A0 0x2D8 0x310 0x348 ) group.long ($2+0x3120)++0x3 line.long 0x0 "RGN_PRI_PER1_$1,This register is only used for resource manager to control privileged access permission." bitfld.long 0x0 31. "DOM7_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM7_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM7_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM7_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM6_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM6_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM6_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM6_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM5_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM5_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM5_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM5_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM4_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM4_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM4_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM4_PRI_EN,Domain privileged permission control enable" "0,1" repeat.end repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x38 0x70 0xA8 0xE0 0x118 0x150 0x188 0x1C0 0x1F8 0x230 0x268 0x2A0 0x2D8 0x310 0x348 ) group.long ($2+0x3124)++0x3 line.long 0x0 "RGN_PRI_PER2_$1,This register is only used for resource manager to control privileged access permission." bitfld.long 0x0 31. "DOM11_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM11_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM11_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM11_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM10_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM10_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM10_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM10_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM9_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM9_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM9_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM9_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM8_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM8_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM8_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM8_PRI_EN,Domain privileged permission control enable" "0,1" repeat.end repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x38 0x70 0xA8 0xE0 0x118 0x150 0x188 0x1C0 0x1F8 0x230 0x268 0x2A0 0x2D8 0x310 0x348 ) group.long ($2+0x3128)++0x3 line.long 0x0 "RGN_PRI_PER3_$1,This register is only used for resource manager to control privileged access permission." bitfld.long 0x0 31. "DOM15_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM15_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM15_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM15_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM14_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM14_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM14_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM14_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM13_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM13_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM13_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM13_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM12_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM12_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM12_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM12_PRI_EN,Domain privileged permission control enable" "0,1" repeat.end repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x38 0x70 0xA8 0xE0 0x118 0x150 0x188 0x1C0 0x1F8 0x230 0x268 0x2A0 0x2D8 0x310 0x348 ) group.long ($2+0x312C)++0x3 line.long 0x0 "RGN_DOM_SEC_PER_$1,This register is only used for domain master to control secure access permission. When the domain master write this register. it only changes the secure permission for itself. When the domain master read this register. it gets.." bitfld.long 0x0 7. "DOM_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" newline bitfld.long 0x0 0. "DOM_SEC_EN,Domain secure permission control enable" "0,1" repeat.end repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x38 0x70 0xA8 0xE0 0x118 0x150 0x188 0x1C0 0x1F8 0x230 0x268 0x2A0 0x2D8 0x310 0x348 ) group.long ($2+0x3130)++0x3 line.long 0x0 "RGN_DOM_PRI_PER_$1,This register is only used for domain master to control secure access permission. When the domain master write this register. it only changes the secure permission for itself. When the domain master read this register. it gets.." bitfld.long 0x0 7. "DOM_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" newline bitfld.long 0x0 0. "DOM_PRI_EN,Domain privileged permission control enable" "0,1" repeat.end repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x38 0x70 0xA8 0xE0 0x118 0x150 0x188 0x1C0 0x1F8 0x230 0x268 0x2A0 0x2D8 0x310 0x348 ) group.long ($2+0x3134)++0x3 line.long 0x0 "RGN_DOM_ASSIGN_$1,Use to assign domain for accessing DOM_SEC_PER and DOM_PRI_PER register. Only resource manager. group manager and domain owner can access this register. For write. group manager must write its owen domain ID. otherwise write accessing.." hexmask.long.byte 0x0 0.--3. 1. "DID,accessing DOM_SEC_PER and DOM_PRI_PER register" repeat.end tree.end tree "RPC_SAFETY_PINCTRL" base ad:0x3CD00000 repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x4 0x8 0xC 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C ) group.long ($2)++0x3 line.long 0x0 "REGG0_DOM_$1,Assign domain for CKGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1A 0x1B 0x1C 0x1D 0x1E 0x1F )(list 0x40 0x44 0x48 0x4C 0x50 0x54 0x58 0x5C 0x60 0x64 0x68 0x6C 0x70 0x74 0x78 0x7C ) group.long ($2)++0x3 line.long 0x0 "REGG0_DOM_$1,Assign domain for CKGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x20 0x21 0x22 0x23 0x24 0x25 0x26 0x27 0x28 0x29 0x2A 0x2B 0x2C 0x2D 0x2E 0x2F )(list 0x80 0x84 0x88 0x8C 0x90 0x94 0x98 0x9C 0xA0 0xA4 0xA8 0xAC 0xB0 0xB4 0xB8 0xBC ) group.long ($2)++0x3 line.long 0x0 "REGG0_DOM_$1,Assign domain for CKGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x30 0x31 0x32 0x33 0x34 0x35 0x36 0x37 0x38 0x39 0x3A 0x3B 0x3C 0x3D 0x3E 0x3F )(list 0xC0 0xC4 0xC8 0xCC 0xD0 0xD4 0xD8 0xDC 0xE0 0xE4 0xE8 0xEC 0xF0 0xF4 0xF8 0xFC ) group.long ($2)++0x3 line.long 0x0 "REGG0_DOM_$1,Assign domain for CKGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x40 0x41 0x42 0x43 0x44 0x45 0x46 0x47 0x48 0x49 0x4A 0x4B 0x4C 0x4D 0x4E 0x4F )(list 0x100 0x104 0x108 0x10C 0x110 0x114 0x118 0x11C 0x120 0x124 0x128 0x12C 0x130 0x134 0x138 0x13C ) group.long ($2)++0x3 line.long 0x0 "REGG0_DOM_$1,Assign domain for CKGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x50 0x51 0x52 0x53 0x54 0x55 0x56 0x57 0x58 0x59 0x5A 0x5B 0x5C 0x5D 0x5E 0x5F )(list 0x140 0x144 0x148 0x14C 0x150 0x154 0x158 0x15C 0x160 0x164 0x168 0x16C 0x170 0x174 0x178 0x17C ) group.long ($2)++0x3 line.long 0x0 "REGG0_DOM_$1,Assign domain for CKGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x60 0x61 0x62 0x63 0x64 0x65 0x66 0x67 0x68 0x69 0x6A 0x6B 0x6C 0x6D 0x6E 0x6F )(list 0x180 0x184 0x188 0x18C 0x190 0x194 0x198 0x19C 0x1A0 0x1A4 0x1A8 0x1AC 0x1B0 0x1B4 0x1B8 0x1BC ) group.long ($2)++0x3 line.long 0x0 "REGG0_DOM_$1,Assign domain for CKGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x70 0x71 0x72 0x73 0x74 0x75 0x76 0x77 0x78 0x79 0x7A 0x7B 0x7C 0x7D 0x7E 0x7F )(list 0x1C0 0x1C4 0x1C8 0x1CC 0x1D0 0x1D4 0x1D8 0x1DC 0x1E0 0x1E4 0x1E8 0x1EC 0x1F0 0x1F4 0x1F8 0x1FC ) group.long ($2)++0x3 line.long 0x0 "REGG0_DOM_$1,Assign domain for CKGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x80 0x81 0x82 0x83 0x84 0x85 0x86 0x87 0x88 0x89 0x8A 0x8B 0x8C 0x8D 0x8E 0x8F )(list 0x200 0x204 0x208 0x20C 0x210 0x214 0x218 0x21C 0x220 0x224 0x228 0x22C 0x230 0x234 0x238 0x23C ) group.long ($2)++0x3 line.long 0x0 "REGG0_DOM_$1,Assign domain for CKGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x90 0x91 0x92 0x93 0x94 0x95 0x96 0x97 0x98 0x99 0x9A 0x9B 0x9C 0x9D 0x9E 0x9F )(list 0x240 0x244 0x248 0x24C 0x250 0x254 0x258 0x25C 0x260 0x264 0x268 0x26C 0x270 0x274 0x278 0x27C ) group.long ($2)++0x3 line.long 0x0 "REGG0_DOM_$1,Assign domain for CKGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xA0 0xA1 0xA2 0xA3 0xA4 0xA5 0xA6 0xA7 0xA8 0xA9 0xAA 0xAB 0xAC 0xAD 0xAE 0xAF )(list 0x280 0x284 0x288 0x28C 0x290 0x294 0x298 0x29C 0x2A0 0x2A4 0x2A8 0x2AC 0x2B0 0x2B4 0x2B8 0x2BC ) group.long ($2)++0x3 line.long 0x0 "REGG0_DOM_$1,Assign domain for CKGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xB0 0xB1 0xB2 0xB3 0xB4 0xB5 0xB6 0xB7 0xB8 0xB9 0xBA 0xBB 0xBC 0xBD 0xBE 0xBF )(list 0x2C0 0x2C4 0x2C8 0x2CC 0x2D0 0x2D4 0x2D8 0x2DC 0x2E0 0x2E4 0x2E8 0x2EC 0x2F0 0x2F4 0x2F8 0x2FC ) group.long ($2)++0x3 line.long 0x0 "REGG0_DOM_$1,Assign domain for CKGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xC0 0xC1 0xC2 0xC3 0xC4 0xC5 0xC6 0xC7 0xC8 0xC9 0xCA 0xCB 0xCC 0xCD 0xCE 0xCF )(list 0x300 0x304 0x308 0x30C 0x310 0x314 0x318 0x31C 0x320 0x324 0x328 0x32C 0x330 0x334 0x338 0x33C ) group.long ($2)++0x3 line.long 0x0 "REGG0_DOM_$1,Assign domain for CKGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xD0 0xD1 0xD2 0xD3 0xD4 0xD5 0xD6 0xD7 0xD8 0xD9 0xDA 0xDB 0xDC 0xDD 0xDE 0xDF )(list 0x340 0x344 0x348 0x34C 0x350 0x354 0x358 0x35C 0x360 0x364 0x368 0x36C 0x370 0x374 0x378 0x37C ) group.long ($2)++0x3 line.long 0x0 "REGG0_DOM_$1,Assign domain for CKGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xE0 0xE1 0xE2 0xE3 0xE4 0xE5 0xE6 0xE7 0xE8 0xE9 0xEA 0xEB 0xEC 0xED 0xEE 0xEF )(list 0x380 0x384 0x388 0x38C 0x390 0x394 0x398 0x39C 0x3A0 0x3A4 0x3A8 0x3AC 0x3B0 0x3B4 0x3B8 0x3BC ) group.long ($2)++0x3 line.long 0x0 "REGG0_DOM_$1,Assign domain for CKGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xF0 0xF1 0xF2 0xF3 0xF4 0xF5 0xF6 0xF7 0xF8 0xF9 0xFA 0xFB 0xFC 0xFD 0xFE 0xFF )(list 0x3C0 0x3C4 0x3C8 0x3CC 0x3D0 0x3D4 0x3D8 0x3DC 0x3E0 0x3E4 0x3E8 0x3EC 0x3F0 0x3F4 0x3F8 0x3FC ) group.long ($2)++0x3 line.long 0x0 "REGG0_DOM_$1,Assign domain for CKGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x4 0x8 0xC 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C ) group.long ($2+0x400)++0x3 line.long 0x0 "REGG1_DOM_$1,Assign domain for CKGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1A 0x1B 0x1C 0x1D 0x1E 0x1F )(list 0x40 0x44 0x48 0x4C 0x50 0x54 0x58 0x5C 0x60 0x64 0x68 0x6C 0x70 0x74 0x78 0x7C ) group.long ($2+0x400)++0x3 line.long 0x0 "REGG1_DOM_$1,Assign domain for CKGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x20 0x21 0x22 0x23 0x24 0x25 0x26 0x27 0x28 0x29 0x2A 0x2B 0x2C 0x2D 0x2E 0x2F )(list 0x80 0x84 0x88 0x8C 0x90 0x94 0x98 0x9C 0xA0 0xA4 0xA8 0xAC 0xB0 0xB4 0xB8 0xBC ) group.long ($2+0x400)++0x3 line.long 0x0 "REGG1_DOM_$1,Assign domain for CKGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x30 0x31 0x32 0x33 0x34 0x35 0x36 0x37 0x38 0x39 0x3A 0x3B 0x3C 0x3D 0x3E 0x3F )(list 0xC0 0xC4 0xC8 0xCC 0xD0 0xD4 0xD8 0xDC 0xE0 0xE4 0xE8 0xEC 0xF0 0xF4 0xF8 0xFC ) group.long ($2+0x400)++0x3 line.long 0x0 "REGG1_DOM_$1,Assign domain for CKGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x40 0x41 0x42 0x43 0x44 0x45 0x46 0x47 0x48 0x49 0x4A 0x4B 0x4C 0x4D 0x4E 0x4F )(list 0x100 0x104 0x108 0x10C 0x110 0x114 0x118 0x11C 0x120 0x124 0x128 0x12C 0x130 0x134 0x138 0x13C ) group.long ($2+0x400)++0x3 line.long 0x0 "REGG1_DOM_$1,Assign domain for CKGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x50 0x51 0x52 0x53 0x54 0x55 0x56 0x57 0x58 0x59 0x5A 0x5B 0x5C 0x5D 0x5E 0x5F )(list 0x140 0x144 0x148 0x14C 0x150 0x154 0x158 0x15C 0x160 0x164 0x168 0x16C 0x170 0x174 0x178 0x17C ) group.long ($2+0x400)++0x3 line.long 0x0 "REGG1_DOM_$1,Assign domain for CKGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x60 0x61 0x62 0x63 0x64 0x65 0x66 0x67 0x68 0x69 0x6A 0x6B 0x6C 0x6D 0x6E 0x6F )(list 0x180 0x184 0x188 0x18C 0x190 0x194 0x198 0x19C 0x1A0 0x1A4 0x1A8 0x1AC 0x1B0 0x1B4 0x1B8 0x1BC ) group.long ($2+0x400)++0x3 line.long 0x0 "REGG1_DOM_$1,Assign domain for CKGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x70 0x71 0x72 0x73 0x74 0x75 0x76 0x77 0x78 0x79 0x7A 0x7B 0x7C 0x7D 0x7E 0x7F )(list 0x1C0 0x1C4 0x1C8 0x1CC 0x1D0 0x1D4 0x1D8 0x1DC 0x1E0 0x1E4 0x1E8 0x1EC 0x1F0 0x1F4 0x1F8 0x1FC ) group.long ($2+0x400)++0x3 line.long 0x0 "REGG1_DOM_$1,Assign domain for CKGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x80 0x81 0x82 0x83 0x84 0x85 0x86 0x87 0x88 0x89 0x8A 0x8B 0x8C 0x8D 0x8E 0x8F )(list 0x200 0x204 0x208 0x20C 0x210 0x214 0x218 0x21C 0x220 0x224 0x228 0x22C 0x230 0x234 0x238 0x23C ) group.long ($2+0x400)++0x3 line.long 0x0 "REGG1_DOM_$1,Assign domain for CKGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x90 0x91 0x92 0x93 0x94 0x95 0x96 0x97 0x98 0x99 0x9A 0x9B 0x9C 0x9D 0x9E 0x9F )(list 0x240 0x244 0x248 0x24C 0x250 0x254 0x258 0x25C 0x260 0x264 0x268 0x26C 0x270 0x274 0x278 0x27C ) group.long ($2+0x400)++0x3 line.long 0x0 "REGG1_DOM_$1,Assign domain for CKGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xA0 0xA1 0xA2 0xA3 0xA4 0xA5 0xA6 0xA7 0xA8 0xA9 0xAA 0xAB 0xAC 0xAD 0xAE 0xAF )(list 0x280 0x284 0x288 0x28C 0x290 0x294 0x298 0x29C 0x2A0 0x2A4 0x2A8 0x2AC 0x2B0 0x2B4 0x2B8 0x2BC ) group.long ($2+0x400)++0x3 line.long 0x0 "REGG1_DOM_$1,Assign domain for CKGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xB0 0xB1 0xB2 0xB3 0xB4 0xB5 0xB6 0xB7 0xB8 0xB9 0xBA 0xBB 0xBC 0xBD 0xBE 0xBF )(list 0x2C0 0x2C4 0x2C8 0x2CC 0x2D0 0x2D4 0x2D8 0x2DC 0x2E0 0x2E4 0x2E8 0x2EC 0x2F0 0x2F4 0x2F8 0x2FC ) group.long ($2+0x400)++0x3 line.long 0x0 "REGG1_DOM_$1,Assign domain for CKGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xC0 0xC1 0xC2 0xC3 0xC4 0xC5 0xC6 0xC7 0xC8 0xC9 0xCA 0xCB 0xCC 0xCD 0xCE 0xCF )(list 0x300 0x304 0x308 0x30C 0x310 0x314 0x318 0x31C 0x320 0x324 0x328 0x32C 0x330 0x334 0x338 0x33C ) group.long ($2+0x400)++0x3 line.long 0x0 "REGG1_DOM_$1,Assign domain for CKGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xD0 0xD1 0xD2 0xD3 0xD4 0xD5 0xD6 0xD7 0xD8 0xD9 0xDA 0xDB 0xDC 0xDD 0xDE 0xDF )(list 0x340 0x344 0x348 0x34C 0x350 0x354 0x358 0x35C 0x360 0x364 0x368 0x36C 0x370 0x374 0x378 0x37C ) group.long ($2+0x400)++0x3 line.long 0x0 "REGG1_DOM_$1,Assign domain for CKGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xE0 0xE1 0xE2 0xE3 0xE4 0xE5 0xE6 0xE7 0xE8 0xE9 0xEA 0xEB 0xEC 0xED 0xEE 0xEF )(list 0x380 0x384 0x388 0x38C 0x390 0x394 0x398 0x39C 0x3A0 0x3A4 0x3A8 0x3AC 0x3B0 0x3B4 0x3B8 0x3BC ) group.long ($2+0x400)++0x3 line.long 0x0 "REGG1_DOM_$1,Assign domain for CKGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xF0 0xF1 0xF2 0xF3 0xF4 0xF5 0xF6 0xF7 0xF8 0xF9 0xFA 0xFB 0xFC 0xFD 0xFE 0xFF )(list 0x3C0 0x3C4 0x3C8 0x3CC 0x3D0 0x3D4 0x3D8 0x3DC 0x3E0 0x3E4 0x3E8 0x3EC 0x3F0 0x3F4 0x3F8 0x3FC ) group.long ($2+0x400)++0x3 line.long 0x0 "REGG1_DOM_$1,Assign domain for CKGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x4 0x8 0xC 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C ) group.long ($2+0x800)++0x3 line.long 0x0 "REGG2_DOM_$1,Assign domain for SCR registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1A 0x1B 0x1C 0x1D 0x1E 0x1F )(list 0x40 0x44 0x48 0x4C 0x50 0x54 0x58 0x5C 0x60 0x64 0x68 0x6C 0x70 0x74 0x78 0x7C ) group.long ($2+0x800)++0x3 line.long 0x0 "REGG2_DOM_$1,Assign domain for SCR registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x20 0x21 0x22 0x23 0x24 0x25 0x26 0x27 0x28 0x29 0x2A 0x2B 0x2C 0x2D 0x2E 0x2F )(list 0x80 0x84 0x88 0x8C 0x90 0x94 0x98 0x9C 0xA0 0xA4 0xA8 0xAC 0xB0 0xB4 0xB8 0xBC ) group.long ($2+0x800)++0x3 line.long 0x0 "REGG2_DOM_$1,Assign domain for SCR registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x30 0x31 0x32 0x33 0x34 0x35 0x36 0x37 0x38 0x39 0x3A 0x3B 0x3C 0x3D 0x3E 0x3F )(list 0xC0 0xC4 0xC8 0xCC 0xD0 0xD4 0xD8 0xDC 0xE0 0xE4 0xE8 0xEC 0xF0 0xF4 0xF8 0xFC ) group.long ($2+0x800)++0x3 line.long 0x0 "REGG2_DOM_$1,Assign domain for SCR registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x40 0x41 0x42 0x43 0x44 0x45 0x46 0x47 0x48 0x49 0x4A 0x4B 0x4C 0x4D 0x4E 0x4F )(list 0x100 0x104 0x108 0x10C 0x110 0x114 0x118 0x11C 0x120 0x124 0x128 0x12C 0x130 0x134 0x138 0x13C ) group.long ($2+0x800)++0x3 line.long 0x0 "REGG2_DOM_$1,Assign domain for SCR registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x50 0x51 0x52 0x53 0x54 0x55 0x56 0x57 0x58 0x59 0x5A 0x5B 0x5C 0x5D 0x5E 0x5F )(list 0x140 0x144 0x148 0x14C 0x150 0x154 0x158 0x15C 0x160 0x164 0x168 0x16C 0x170 0x174 0x178 0x17C ) group.long ($2+0x800)++0x3 line.long 0x0 "REGG2_DOM_$1,Assign domain for SCR registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x60 0x61 0x62 0x63 0x64 0x65 0x66 0x67 0x68 0x69 0x6A 0x6B 0x6C 0x6D 0x6E 0x6F )(list 0x180 0x184 0x188 0x18C 0x190 0x194 0x198 0x19C 0x1A0 0x1A4 0x1A8 0x1AC 0x1B0 0x1B4 0x1B8 0x1BC ) group.long ($2+0x800)++0x3 line.long 0x0 "REGG2_DOM_$1,Assign domain for SCR registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x70 0x71 0x72 0x73 0x74 0x75 0x76 0x77 0x78 0x79 0x7A 0x7B 0x7C 0x7D 0x7E 0x7F )(list 0x1C0 0x1C4 0x1C8 0x1CC 0x1D0 0x1D4 0x1D8 0x1DC 0x1E0 0x1E4 0x1E8 0x1EC 0x1F0 0x1F4 0x1F8 0x1FC ) group.long ($2+0x800)++0x3 line.long 0x0 "REGG2_DOM_$1,Assign domain for SCR registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x80 0x81 0x82 0x83 0x84 0x85 0x86 0x87 0x88 0x89 0x8A 0x8B 0x8C 0x8D 0x8E 0x8F )(list 0x200 0x204 0x208 0x20C 0x210 0x214 0x218 0x21C 0x220 0x224 0x228 0x22C 0x230 0x234 0x238 0x23C ) group.long ($2+0x800)++0x3 line.long 0x0 "REGG2_DOM_$1,Assign domain for SCR registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x90 0x91 0x92 0x93 0x94 0x95 0x96 0x97 0x98 0x99 0x9A 0x9B 0x9C 0x9D 0x9E 0x9F )(list 0x240 0x244 0x248 0x24C 0x250 0x254 0x258 0x25C 0x260 0x264 0x268 0x26C 0x270 0x274 0x278 0x27C ) group.long ($2+0x800)++0x3 line.long 0x0 "REGG2_DOM_$1,Assign domain for SCR registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xA0 0xA1 0xA2 0xA3 0xA4 0xA5 0xA6 0xA7 0xA8 0xA9 0xAA 0xAB 0xAC 0xAD 0xAE 0xAF )(list 0x280 0x284 0x288 0x28C 0x290 0x294 0x298 0x29C 0x2A0 0x2A4 0x2A8 0x2AC 0x2B0 0x2B4 0x2B8 0x2BC ) group.long ($2+0x800)++0x3 line.long 0x0 "REGG2_DOM_$1,Assign domain for SCR registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xB0 0xB1 0xB2 0xB3 0xB4 0xB5 0xB6 0xB7 0xB8 0xB9 0xBA 0xBB 0xBC 0xBD 0xBE 0xBF )(list 0x2C0 0x2C4 0x2C8 0x2CC 0x2D0 0x2D4 0x2D8 0x2DC 0x2E0 0x2E4 0x2E8 0x2EC 0x2F0 0x2F4 0x2F8 0x2FC ) group.long ($2+0x800)++0x3 line.long 0x0 "REGG2_DOM_$1,Assign domain for SCR registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xC0 0xC1 0xC2 0xC3 0xC4 0xC5 0xC6 0xC7 0xC8 0xC9 0xCA 0xCB 0xCC 0xCD 0xCE 0xCF )(list 0x300 0x304 0x308 0x30C 0x310 0x314 0x318 0x31C 0x320 0x324 0x328 0x32C 0x330 0x334 0x338 0x33C ) group.long ($2+0x800)++0x3 line.long 0x0 "REGG2_DOM_$1,Assign domain for SCR registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xD0 0xD1 0xD2 0xD3 0xD4 0xD5 0xD6 0xD7 0xD8 0xD9 0xDA 0xDB 0xDC 0xDD 0xDE 0xDF )(list 0x340 0x344 0x348 0x34C 0x350 0x354 0x358 0x35C 0x360 0x364 0x368 0x36C 0x370 0x374 0x378 0x37C ) group.long ($2+0x800)++0x3 line.long 0x0 "REGG2_DOM_$1,Assign domain for SCR registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xE0 0xE1 0xE2 0xE3 0xE4 0xE5 0xE6 0xE7 0xE8 0xE9 0xEA 0xEB 0xEC 0xED 0xEE 0xEF )(list 0x380 0x384 0x388 0x38C 0x390 0x394 0x398 0x39C 0x3A0 0x3A4 0x3A8 0x3AC 0x3B0 0x3B4 0x3B8 0x3BC ) group.long ($2+0x800)++0x3 line.long 0x0 "REGG2_DOM_$1,Assign domain for SCR registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xF0 0xF1 0xF2 0xF3 0xF4 0xF5 0xF6 0xF7 0xF8 0xF9 0xFA 0xFB 0xFC 0xFD 0xFE 0xFF )(list 0x3C0 0x3C4 0x3C8 0x3CC 0x3D0 0x3D4 0x3D8 0x3DC 0x3E0 0x3E4 0x3E8 0x3EC 0x3F0 0x3F4 0x3F8 0x3FC ) group.long ($2+0x800)++0x3 line.long 0x0 "REGG2_DOM_$1,Assign domain for SCR registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x4 0x8 0xC 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C ) group.long ($2+0xC00)++0x3 line.long 0x0 "REGG3_DOM_$1,Assign domain for SCR registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1A 0x1B 0x1C 0x1D 0x1E 0x1F )(list 0x40 0x44 0x48 0x4C 0x50 0x54 0x58 0x5C 0x60 0x64 0x68 0x6C 0x70 0x74 0x78 0x7C ) group.long ($2+0xC00)++0x3 line.long 0x0 "REGG3_DOM_$1,Assign domain for SCR registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x20 0x21 0x22 0x23 0x24 0x25 0x26 0x27 0x28 0x29 0x2A 0x2B 0x2C 0x2D 0x2E 0x2F )(list 0x80 0x84 0x88 0x8C 0x90 0x94 0x98 0x9C 0xA0 0xA4 0xA8 0xAC 0xB0 0xB4 0xB8 0xBC ) group.long ($2+0xC00)++0x3 line.long 0x0 "REGG3_DOM_$1,Assign domain for SCR registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x30 0x31 0x32 0x33 0x34 0x35 0x36 0x37 0x38 0x39 0x3A 0x3B 0x3C 0x3D 0x3E 0x3F )(list 0xC0 0xC4 0xC8 0xCC 0xD0 0xD4 0xD8 0xDC 0xE0 0xE4 0xE8 0xEC 0xF0 0xF4 0xF8 0xFC ) group.long ($2+0xC00)++0x3 line.long 0x0 "REGG3_DOM_$1,Assign domain for SCR registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x40 0x41 0x42 0x43 0x44 0x45 0x46 0x47 0x48 0x49 0x4A 0x4B 0x4C 0x4D 0x4E 0x4F )(list 0x100 0x104 0x108 0x10C 0x110 0x114 0x118 0x11C 0x120 0x124 0x128 0x12C 0x130 0x134 0x138 0x13C ) group.long ($2+0xC00)++0x3 line.long 0x0 "REGG3_DOM_$1,Assign domain for SCR registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x50 0x51 0x52 0x53 0x54 0x55 0x56 0x57 0x58 0x59 0x5A 0x5B 0x5C 0x5D 0x5E 0x5F )(list 0x140 0x144 0x148 0x14C 0x150 0x154 0x158 0x15C 0x160 0x164 0x168 0x16C 0x170 0x174 0x178 0x17C ) group.long ($2+0xC00)++0x3 line.long 0x0 "REGG3_DOM_$1,Assign domain for SCR registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x60 0x61 0x62 0x63 0x64 0x65 0x66 0x67 0x68 0x69 0x6A 0x6B 0x6C 0x6D 0x6E 0x6F )(list 0x180 0x184 0x188 0x18C 0x190 0x194 0x198 0x19C 0x1A0 0x1A4 0x1A8 0x1AC 0x1B0 0x1B4 0x1B8 0x1BC ) group.long ($2+0xC00)++0x3 line.long 0x0 "REGG3_DOM_$1,Assign domain for SCR registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x70 0x71 0x72 0x73 0x74 0x75 0x76 0x77 0x78 0x79 0x7A 0x7B 0x7C 0x7D 0x7E 0x7F )(list 0x1C0 0x1C4 0x1C8 0x1CC 0x1D0 0x1D4 0x1D8 0x1DC 0x1E0 0x1E4 0x1E8 0x1EC 0x1F0 0x1F4 0x1F8 0x1FC ) group.long ($2+0xC00)++0x3 line.long 0x0 "REGG3_DOM_$1,Assign domain for SCR registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x80 0x81 0x82 0x83 0x84 0x85 0x86 0x87 0x88 0x89 0x8A 0x8B 0x8C 0x8D 0x8E 0x8F )(list 0x200 0x204 0x208 0x20C 0x210 0x214 0x218 0x21C 0x220 0x224 0x228 0x22C 0x230 0x234 0x238 0x23C ) group.long ($2+0xC00)++0x3 line.long 0x0 "REGG3_DOM_$1,Assign domain for SCR registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x90 0x91 0x92 0x93 0x94 0x95 0x96 0x97 0x98 0x99 0x9A 0x9B 0x9C 0x9D 0x9E 0x9F )(list 0x240 0x244 0x248 0x24C 0x250 0x254 0x258 0x25C 0x260 0x264 0x268 0x26C 0x270 0x274 0x278 0x27C ) group.long ($2+0xC00)++0x3 line.long 0x0 "REGG3_DOM_$1,Assign domain for SCR registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xA0 0xA1 0xA2 0xA3 0xA4 0xA5 0xA6 0xA7 0xA8 0xA9 0xAA 0xAB 0xAC 0xAD 0xAE 0xAF )(list 0x280 0x284 0x288 0x28C 0x290 0x294 0x298 0x29C 0x2A0 0x2A4 0x2A8 0x2AC 0x2B0 0x2B4 0x2B8 0x2BC ) group.long ($2+0xC00)++0x3 line.long 0x0 "REGG3_DOM_$1,Assign domain for SCR registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xB0 0xB1 0xB2 0xB3 0xB4 0xB5 0xB6 0xB7 0xB8 0xB9 0xBA 0xBB 0xBC 0xBD 0xBE 0xBF )(list 0x2C0 0x2C4 0x2C8 0x2CC 0x2D0 0x2D4 0x2D8 0x2DC 0x2E0 0x2E4 0x2E8 0x2EC 0x2F0 0x2F4 0x2F8 0x2FC ) group.long ($2+0xC00)++0x3 line.long 0x0 "REGG3_DOM_$1,Assign domain for SCR registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xC0 0xC1 0xC2 0xC3 0xC4 0xC5 0xC6 0xC7 0xC8 0xC9 0xCA 0xCB 0xCC 0xCD 0xCE 0xCF )(list 0x300 0x304 0x308 0x30C 0x310 0x314 0x318 0x31C 0x320 0x324 0x328 0x32C 0x330 0x334 0x338 0x33C ) group.long ($2+0xC00)++0x3 line.long 0x0 "REGG3_DOM_$1,Assign domain for SCR registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xD0 0xD1 0xD2 0xD3 0xD4 0xD5 0xD6 0xD7 0xD8 0xD9 0xDA 0xDB 0xDC 0xDD 0xDE 0xDF )(list 0x340 0x344 0x348 0x34C 0x350 0x354 0x358 0x35C 0x360 0x364 0x368 0x36C 0x370 0x374 0x378 0x37C ) group.long ($2+0xC00)++0x3 line.long 0x0 "REGG3_DOM_$1,Assign domain for SCR registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xE0 0xE1 0xE2 0xE3 0xE4 0xE5 0xE6 0xE7 0xE8 0xE9 0xEA 0xEB 0xEC 0xED 0xEE 0xEF )(list 0x380 0x384 0x388 0x38C 0x390 0x394 0x398 0x39C 0x3A0 0x3A4 0x3A8 0x3AC 0x3B0 0x3B4 0x3B8 0x3BC ) group.long ($2+0xC00)++0x3 line.long 0x0 "REGG3_DOM_$1,Assign domain for SCR registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xF0 0xF1 0xF2 0xF3 0xF4 0xF5 0xF6 0xF7 0xF8 0xF9 0xFA 0xFB 0xFC 0xFD 0xFE 0xFF )(list 0x3C0 0x3C4 0x3C8 0x3CC 0x3D0 0x3D4 0x3D8 0x3DC 0x3E0 0x3E4 0x3E8 0x3EC 0x3F0 0x3F4 0x3F8 0x3FC ) group.long ($2+0xC00)++0x3 line.long 0x0 "REGG3_DOM_$1,Assign domain for SCR registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x4 0x8 0xC 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C ) group.long ($2+0x1000)++0x3 line.long 0x0 "REGG4_DOM_$1,Assign domain for RSTGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1A 0x1B 0x1C 0x1D 0x1E 0x1F )(list 0x40 0x44 0x48 0x4C 0x50 0x54 0x58 0x5C 0x60 0x64 0x68 0x6C 0x70 0x74 0x78 0x7C ) group.long ($2+0x1000)++0x3 line.long 0x0 "REGG4_DOM_$1,Assign domain for RSTGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x20 0x21 0x22 0x23 0x24 0x25 0x26 0x27 0x28 0x29 0x2A 0x2B 0x2C 0x2D 0x2E 0x2F )(list 0x80 0x84 0x88 0x8C 0x90 0x94 0x98 0x9C 0xA0 0xA4 0xA8 0xAC 0xB0 0xB4 0xB8 0xBC ) group.long ($2+0x1000)++0x3 line.long 0x0 "REGG4_DOM_$1,Assign domain for RSTGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x30 0x31 0x32 0x33 0x34 0x35 0x36 0x37 0x38 0x39 0x3A 0x3B 0x3C 0x3D 0x3E 0x3F )(list 0xC0 0xC4 0xC8 0xCC 0xD0 0xD4 0xD8 0xDC 0xE0 0xE4 0xE8 0xEC 0xF0 0xF4 0xF8 0xFC ) group.long ($2+0x1000)++0x3 line.long 0x0 "REGG4_DOM_$1,Assign domain for RSTGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x40 0x41 0x42 0x43 0x44 0x45 0x46 0x47 0x48 0x49 0x4A 0x4B 0x4C 0x4D 0x4E 0x4F )(list 0x100 0x104 0x108 0x10C 0x110 0x114 0x118 0x11C 0x120 0x124 0x128 0x12C 0x130 0x134 0x138 0x13C ) group.long ($2+0x1000)++0x3 line.long 0x0 "REGG4_DOM_$1,Assign domain for RSTGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x50 0x51 0x52 0x53 0x54 0x55 0x56 0x57 0x58 0x59 0x5A 0x5B 0x5C 0x5D 0x5E 0x5F )(list 0x140 0x144 0x148 0x14C 0x150 0x154 0x158 0x15C 0x160 0x164 0x168 0x16C 0x170 0x174 0x178 0x17C ) group.long ($2+0x1000)++0x3 line.long 0x0 "REGG4_DOM_$1,Assign domain for RSTGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x60 0x61 0x62 0x63 0x64 0x65 0x66 0x67 0x68 0x69 0x6A 0x6B 0x6C 0x6D 0x6E 0x6F )(list 0x180 0x184 0x188 0x18C 0x190 0x194 0x198 0x19C 0x1A0 0x1A4 0x1A8 0x1AC 0x1B0 0x1B4 0x1B8 0x1BC ) group.long ($2+0x1000)++0x3 line.long 0x0 "REGG4_DOM_$1,Assign domain for RSTGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x70 0x71 0x72 0x73 0x74 0x75 0x76 0x77 0x78 0x79 0x7A 0x7B 0x7C 0x7D 0x7E 0x7F )(list 0x1C0 0x1C4 0x1C8 0x1CC 0x1D0 0x1D4 0x1D8 0x1DC 0x1E0 0x1E4 0x1E8 0x1EC 0x1F0 0x1F4 0x1F8 0x1FC ) group.long ($2+0x1000)++0x3 line.long 0x0 "REGG4_DOM_$1,Assign domain for RSTGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x80 0x81 0x82 0x83 0x84 0x85 0x86 0x87 0x88 0x89 0x8A 0x8B 0x8C 0x8D 0x8E 0x8F )(list 0x200 0x204 0x208 0x20C 0x210 0x214 0x218 0x21C 0x220 0x224 0x228 0x22C 0x230 0x234 0x238 0x23C ) group.long ($2+0x1000)++0x3 line.long 0x0 "REGG4_DOM_$1,Assign domain for RSTGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x90 0x91 0x92 0x93 0x94 0x95 0x96 0x97 0x98 0x99 0x9A 0x9B 0x9C 0x9D 0x9E 0x9F )(list 0x240 0x244 0x248 0x24C 0x250 0x254 0x258 0x25C 0x260 0x264 0x268 0x26C 0x270 0x274 0x278 0x27C ) group.long ($2+0x1000)++0x3 line.long 0x0 "REGG4_DOM_$1,Assign domain for RSTGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xA0 0xA1 0xA2 0xA3 0xA4 0xA5 0xA6 0xA7 0xA8 0xA9 0xAA 0xAB 0xAC 0xAD 0xAE 0xAF )(list 0x280 0x284 0x288 0x28C 0x290 0x294 0x298 0x29C 0x2A0 0x2A4 0x2A8 0x2AC 0x2B0 0x2B4 0x2B8 0x2BC ) group.long ($2+0x1000)++0x3 line.long 0x0 "REGG4_DOM_$1,Assign domain for RSTGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xB0 0xB1 0xB2 0xB3 0xB4 0xB5 0xB6 0xB7 0xB8 0xB9 0xBA 0xBB 0xBC 0xBD 0xBE 0xBF )(list 0x2C0 0x2C4 0x2C8 0x2CC 0x2D0 0x2D4 0x2D8 0x2DC 0x2E0 0x2E4 0x2E8 0x2EC 0x2F0 0x2F4 0x2F8 0x2FC ) group.long ($2+0x1000)++0x3 line.long 0x0 "REGG4_DOM_$1,Assign domain for RSTGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xC0 0xC1 0xC2 0xC3 0xC4 0xC5 0xC6 0xC7 0xC8 0xC9 0xCA 0xCB 0xCC 0xCD 0xCE 0xCF )(list 0x300 0x304 0x308 0x30C 0x310 0x314 0x318 0x31C 0x320 0x324 0x328 0x32C 0x330 0x334 0x338 0x33C ) group.long ($2+0x1000)++0x3 line.long 0x0 "REGG4_DOM_$1,Assign domain for RSTGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xD0 0xD1 0xD2 0xD3 0xD4 0xD5 0xD6 0xD7 0xD8 0xD9 0xDA 0xDB 0xDC 0xDD 0xDE 0xDF )(list 0x340 0x344 0x348 0x34C 0x350 0x354 0x358 0x35C 0x360 0x364 0x368 0x36C 0x370 0x374 0x378 0x37C ) group.long ($2+0x1000)++0x3 line.long 0x0 "REGG4_DOM_$1,Assign domain for RSTGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xE0 0xE1 0xE2 0xE3 0xE4 0xE5 0xE6 0xE7 0xE8 0xE9 0xEA 0xEB 0xEC 0xED 0xEE 0xEF )(list 0x380 0x384 0x388 0x38C 0x390 0x394 0x398 0x39C 0x3A0 0x3A4 0x3A8 0x3AC 0x3B0 0x3B4 0x3B8 0x3BC ) group.long ($2+0x1000)++0x3 line.long 0x0 "REGG4_DOM_$1,Assign domain for RSTGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xF0 0xF1 0xF2 0xF3 0xF4 0xF5 0xF6 0xF7 0xF8 0xF9 0xFA 0xFB 0xFC 0xFD 0xFE 0xFF )(list 0x3C0 0x3C4 0x3C8 0x3CC 0x3D0 0x3D4 0x3D8 0x3DC 0x3E0 0x3E4 0x3E8 0x3EC 0x3F0 0x3F4 0x3F8 0x3FC ) group.long ($2+0x1000)++0x3 line.long 0x0 "REGG4_DOM_$1,Assign domain for RSTGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x4 0x8 0xC 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C ) group.long ($2+0x1400)++0x3 line.long 0x0 "REGG5_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1A 0x1B 0x1C 0x1D 0x1E 0x1F )(list 0x40 0x44 0x48 0x4C 0x50 0x54 0x58 0x5C 0x60 0x64 0x68 0x6C 0x70 0x74 0x78 0x7C ) group.long ($2+0x1400)++0x3 line.long 0x0 "REGG5_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x20 0x21 0x22 0x23 0x24 0x25 0x26 0x27 0x28 0x29 0x2A 0x2B 0x2C 0x2D 0x2E 0x2F )(list 0x80 0x84 0x88 0x8C 0x90 0x94 0x98 0x9C 0xA0 0xA4 0xA8 0xAC 0xB0 0xB4 0xB8 0xBC ) group.long ($2+0x1400)++0x3 line.long 0x0 "REGG5_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x30 0x31 0x32 0x33 0x34 0x35 0x36 0x37 0x38 0x39 0x3A 0x3B 0x3C 0x3D 0x3E 0x3F )(list 0xC0 0xC4 0xC8 0xCC 0xD0 0xD4 0xD8 0xDC 0xE0 0xE4 0xE8 0xEC 0xF0 0xF4 0xF8 0xFC ) group.long ($2+0x1400)++0x3 line.long 0x0 "REGG5_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x40 0x41 0x42 0x43 0x44 0x45 0x46 0x47 0x48 0x49 0x4A 0x4B 0x4C 0x4D 0x4E 0x4F )(list 0x100 0x104 0x108 0x10C 0x110 0x114 0x118 0x11C 0x120 0x124 0x128 0x12C 0x130 0x134 0x138 0x13C ) group.long ($2+0x1400)++0x3 line.long 0x0 "REGG5_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x50 0x51 0x52 0x53 0x54 0x55 0x56 0x57 0x58 0x59 0x5A 0x5B 0x5C 0x5D 0x5E 0x5F )(list 0x140 0x144 0x148 0x14C 0x150 0x154 0x158 0x15C 0x160 0x164 0x168 0x16C 0x170 0x174 0x178 0x17C ) group.long ($2+0x1400)++0x3 line.long 0x0 "REGG5_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x60 0x61 0x62 0x63 0x64 0x65 0x66 0x67 0x68 0x69 0x6A 0x6B 0x6C 0x6D 0x6E 0x6F )(list 0x180 0x184 0x188 0x18C 0x190 0x194 0x198 0x19C 0x1A0 0x1A4 0x1A8 0x1AC 0x1B0 0x1B4 0x1B8 0x1BC ) group.long ($2+0x1400)++0x3 line.long 0x0 "REGG5_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x70 0x71 0x72 0x73 0x74 0x75 0x76 0x77 0x78 0x79 0x7A 0x7B 0x7C 0x7D 0x7E 0x7F )(list 0x1C0 0x1C4 0x1C8 0x1CC 0x1D0 0x1D4 0x1D8 0x1DC 0x1E0 0x1E4 0x1E8 0x1EC 0x1F0 0x1F4 0x1F8 0x1FC ) group.long ($2+0x1400)++0x3 line.long 0x0 "REGG5_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x80 0x81 0x82 0x83 0x84 0x85 0x86 0x87 0x88 0x89 0x8A 0x8B 0x8C 0x8D 0x8E 0x8F )(list 0x200 0x204 0x208 0x20C 0x210 0x214 0x218 0x21C 0x220 0x224 0x228 0x22C 0x230 0x234 0x238 0x23C ) group.long ($2+0x1400)++0x3 line.long 0x0 "REGG5_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x90 0x91 0x92 0x93 0x94 0x95 0x96 0x97 0x98 0x99 0x9A 0x9B 0x9C 0x9D 0x9E 0x9F )(list 0x240 0x244 0x248 0x24C 0x250 0x254 0x258 0x25C 0x260 0x264 0x268 0x26C 0x270 0x274 0x278 0x27C ) group.long ($2+0x1400)++0x3 line.long 0x0 "REGG5_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xA0 0xA1 0xA2 0xA3 0xA4 0xA5 0xA6 0xA7 0xA8 0xA9 0xAA 0xAB 0xAC 0xAD 0xAE 0xAF )(list 0x280 0x284 0x288 0x28C 0x290 0x294 0x298 0x29C 0x2A0 0x2A4 0x2A8 0x2AC 0x2B0 0x2B4 0x2B8 0x2BC ) group.long ($2+0x1400)++0x3 line.long 0x0 "REGG5_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xB0 0xB1 0xB2 0xB3 0xB4 0xB5 0xB6 0xB7 0xB8 0xB9 0xBA 0xBB 0xBC 0xBD 0xBE 0xBF )(list 0x2C0 0x2C4 0x2C8 0x2CC 0x2D0 0x2D4 0x2D8 0x2DC 0x2E0 0x2E4 0x2E8 0x2EC 0x2F0 0x2F4 0x2F8 0x2FC ) group.long ($2+0x1400)++0x3 line.long 0x0 "REGG5_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xC0 0xC1 0xC2 0xC3 0xC4 0xC5 0xC6 0xC7 0xC8 0xC9 0xCA 0xCB 0xCC 0xCD 0xCE 0xCF )(list 0x300 0x304 0x308 0x30C 0x310 0x314 0x318 0x31C 0x320 0x324 0x328 0x32C 0x330 0x334 0x338 0x33C ) group.long ($2+0x1400)++0x3 line.long 0x0 "REGG5_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xD0 0xD1 0xD2 0xD3 0xD4 0xD5 0xD6 0xD7 0xD8 0xD9 0xDA 0xDB 0xDC 0xDD 0xDE 0xDF )(list 0x340 0x344 0x348 0x34C 0x350 0x354 0x358 0x35C 0x360 0x364 0x368 0x36C 0x370 0x374 0x378 0x37C ) group.long ($2+0x1400)++0x3 line.long 0x0 "REGG5_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xE0 0xE1 0xE2 0xE3 0xE4 0xE5 0xE6 0xE7 0xE8 0xE9 0xEA 0xEB 0xEC 0xED 0xEE 0xEF )(list 0x380 0x384 0x388 0x38C 0x390 0x394 0x398 0x39C 0x3A0 0x3A4 0x3A8 0x3AC 0x3B0 0x3B4 0x3B8 0x3BC ) group.long ($2+0x1400)++0x3 line.long 0x0 "REGG5_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xF0 0xF1 0xF2 0xF3 0xF4 0xF5 0xF6 0xF7 0xF8 0xF9 0xFA 0xFB 0xFC 0xFD 0xFE 0xFF )(list 0x3C0 0x3C4 0x3C8 0x3CC 0x3D0 0x3D4 0x3D8 0x3DC 0x3E0 0x3E4 0x3E8 0x3EC 0x3F0 0x3F4 0x3F8 0x3FC ) group.long ($2+0x1400)++0x3 line.long 0x0 "REGG5_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x4 0x8 0xC 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C ) group.long ($2+0x1800)++0x3 line.long 0x0 "REGG6_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1A 0x1B 0x1C 0x1D 0x1E 0x1F )(list 0x40 0x44 0x48 0x4C 0x50 0x54 0x58 0x5C 0x60 0x64 0x68 0x6C 0x70 0x74 0x78 0x7C ) group.long ($2+0x1800)++0x3 line.long 0x0 "REGG6_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x20 0x21 0x22 0x23 0x24 0x25 0x26 0x27 0x28 0x29 0x2A 0x2B 0x2C 0x2D 0x2E 0x2F )(list 0x80 0x84 0x88 0x8C 0x90 0x94 0x98 0x9C 0xA0 0xA4 0xA8 0xAC 0xB0 0xB4 0xB8 0xBC ) group.long ($2+0x1800)++0x3 line.long 0x0 "REGG6_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x30 0x31 0x32 0x33 0x34 0x35 0x36 0x37 0x38 0x39 0x3A 0x3B 0x3C 0x3D 0x3E 0x3F )(list 0xC0 0xC4 0xC8 0xCC 0xD0 0xD4 0xD8 0xDC 0xE0 0xE4 0xE8 0xEC 0xF0 0xF4 0xF8 0xFC ) group.long ($2+0x1800)++0x3 line.long 0x0 "REGG6_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x40 0x41 0x42 0x43 0x44 0x45 0x46 0x47 0x48 0x49 0x4A 0x4B 0x4C 0x4D 0x4E 0x4F )(list 0x100 0x104 0x108 0x10C 0x110 0x114 0x118 0x11C 0x120 0x124 0x128 0x12C 0x130 0x134 0x138 0x13C ) group.long ($2+0x1800)++0x3 line.long 0x0 "REGG6_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x50 0x51 0x52 0x53 0x54 0x55 0x56 0x57 0x58 0x59 0x5A 0x5B 0x5C 0x5D 0x5E 0x5F )(list 0x140 0x144 0x148 0x14C 0x150 0x154 0x158 0x15C 0x160 0x164 0x168 0x16C 0x170 0x174 0x178 0x17C ) group.long ($2+0x1800)++0x3 line.long 0x0 "REGG6_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x60 0x61 0x62 0x63 0x64 0x65 0x66 0x67 0x68 0x69 0x6A 0x6B 0x6C 0x6D 0x6E 0x6F )(list 0x180 0x184 0x188 0x18C 0x190 0x194 0x198 0x19C 0x1A0 0x1A4 0x1A8 0x1AC 0x1B0 0x1B4 0x1B8 0x1BC ) group.long ($2+0x1800)++0x3 line.long 0x0 "REGG6_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x70 0x71 0x72 0x73 0x74 0x75 0x76 0x77 0x78 0x79 0x7A 0x7B 0x7C 0x7D 0x7E 0x7F )(list 0x1C0 0x1C4 0x1C8 0x1CC 0x1D0 0x1D4 0x1D8 0x1DC 0x1E0 0x1E4 0x1E8 0x1EC 0x1F0 0x1F4 0x1F8 0x1FC ) group.long ($2+0x1800)++0x3 line.long 0x0 "REGG6_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x80 0x81 0x82 0x83 0x84 0x85 0x86 0x87 0x88 0x89 0x8A 0x8B 0x8C 0x8D 0x8E 0x8F )(list 0x200 0x204 0x208 0x20C 0x210 0x214 0x218 0x21C 0x220 0x224 0x228 0x22C 0x230 0x234 0x238 0x23C ) group.long ($2+0x1800)++0x3 line.long 0x0 "REGG6_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x90 0x91 0x92 0x93 0x94 0x95 0x96 0x97 0x98 0x99 0x9A 0x9B 0x9C 0x9D 0x9E 0x9F )(list 0x240 0x244 0x248 0x24C 0x250 0x254 0x258 0x25C 0x260 0x264 0x268 0x26C 0x270 0x274 0x278 0x27C ) group.long ($2+0x1800)++0x3 line.long 0x0 "REGG6_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xA0 0xA1 0xA2 0xA3 0xA4 0xA5 0xA6 0xA7 0xA8 0xA9 0xAA 0xAB 0xAC 0xAD 0xAE 0xAF )(list 0x280 0x284 0x288 0x28C 0x290 0x294 0x298 0x29C 0x2A0 0x2A4 0x2A8 0x2AC 0x2B0 0x2B4 0x2B8 0x2BC ) group.long ($2+0x1800)++0x3 line.long 0x0 "REGG6_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xB0 0xB1 0xB2 0xB3 0xB4 0xB5 0xB6 0xB7 0xB8 0xB9 0xBA 0xBB 0xBC 0xBD 0xBE 0xBF )(list 0x2C0 0x2C4 0x2C8 0x2CC 0x2D0 0x2D4 0x2D8 0x2DC 0x2E0 0x2E4 0x2E8 0x2EC 0x2F0 0x2F4 0x2F8 0x2FC ) group.long ($2+0x1800)++0x3 line.long 0x0 "REGG6_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xC0 0xC1 0xC2 0xC3 0xC4 0xC5 0xC6 0xC7 0xC8 0xC9 0xCA 0xCB 0xCC 0xCD 0xCE 0xCF )(list 0x300 0x304 0x308 0x30C 0x310 0x314 0x318 0x31C 0x320 0x324 0x328 0x32C 0x330 0x334 0x338 0x33C ) group.long ($2+0x1800)++0x3 line.long 0x0 "REGG6_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xD0 0xD1 0xD2 0xD3 0xD4 0xD5 0xD6 0xD7 0xD8 0xD9 0xDA 0xDB 0xDC 0xDD 0xDE 0xDF )(list 0x340 0x344 0x348 0x34C 0x350 0x354 0x358 0x35C 0x360 0x364 0x368 0x36C 0x370 0x374 0x378 0x37C ) group.long ($2+0x1800)++0x3 line.long 0x0 "REGG6_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xE0 0xE1 0xE2 0xE3 0xE4 0xE5 0xE6 0xE7 0xE8 0xE9 0xEA 0xEB 0xEC 0xED 0xEE 0xEF )(list 0x380 0x384 0x388 0x38C 0x390 0x394 0x398 0x39C 0x3A0 0x3A4 0x3A8 0x3AC 0x3B0 0x3B4 0x3B8 0x3BC ) group.long ($2+0x1800)++0x3 line.long 0x0 "REGG6_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xF0 0xF1 0xF2 0xF3 0xF4 0xF5 0xF6 0xF7 0xF8 0xF9 0xFA 0xFB 0xFC 0xFD 0xFE 0xFF )(list 0x3C0 0x3C4 0x3C8 0x3CC 0x3D0 0x3D4 0x3D8 0x3DC 0x3E0 0x3E4 0x3E8 0x3EC 0x3F0 0x3F4 0x3F8 0x3FC ) group.long ($2+0x1800)++0x3 line.long 0x0 "REGG6_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x4 0x8 0xC 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C ) group.long ($2+0x1C00)++0x3 line.long 0x0 "REGG7_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1A 0x1B 0x1C 0x1D 0x1E 0x1F )(list 0x40 0x44 0x48 0x4C 0x50 0x54 0x58 0x5C 0x60 0x64 0x68 0x6C 0x70 0x74 0x78 0x7C ) group.long ($2+0x1C00)++0x3 line.long 0x0 "REGG7_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x20 0x21 0x22 0x23 0x24 0x25 0x26 0x27 0x28 0x29 0x2A 0x2B 0x2C 0x2D 0x2E 0x2F )(list 0x80 0x84 0x88 0x8C 0x90 0x94 0x98 0x9C 0xA0 0xA4 0xA8 0xAC 0xB0 0xB4 0xB8 0xBC ) group.long ($2+0x1C00)++0x3 line.long 0x0 "REGG7_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x30 0x31 0x32 0x33 0x34 0x35 0x36 0x37 0x38 0x39 0x3A 0x3B 0x3C 0x3D 0x3E 0x3F )(list 0xC0 0xC4 0xC8 0xCC 0xD0 0xD4 0xD8 0xDC 0xE0 0xE4 0xE8 0xEC 0xF0 0xF4 0xF8 0xFC ) group.long ($2+0x1C00)++0x3 line.long 0x0 "REGG7_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x40 0x41 0x42 0x43 0x44 0x45 0x46 0x47 0x48 0x49 0x4A 0x4B 0x4C 0x4D 0x4E 0x4F )(list 0x100 0x104 0x108 0x10C 0x110 0x114 0x118 0x11C 0x120 0x124 0x128 0x12C 0x130 0x134 0x138 0x13C ) group.long ($2+0x1C00)++0x3 line.long 0x0 "REGG7_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x50 0x51 0x52 0x53 0x54 0x55 0x56 0x57 0x58 0x59 0x5A 0x5B 0x5C 0x5D 0x5E 0x5F )(list 0x140 0x144 0x148 0x14C 0x150 0x154 0x158 0x15C 0x160 0x164 0x168 0x16C 0x170 0x174 0x178 0x17C ) group.long ($2+0x1C00)++0x3 line.long 0x0 "REGG7_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x60 0x61 0x62 0x63 0x64 0x65 0x66 0x67 0x68 0x69 0x6A 0x6B 0x6C 0x6D 0x6E 0x6F )(list 0x180 0x184 0x188 0x18C 0x190 0x194 0x198 0x19C 0x1A0 0x1A4 0x1A8 0x1AC 0x1B0 0x1B4 0x1B8 0x1BC ) group.long ($2+0x1C00)++0x3 line.long 0x0 "REGG7_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x70 0x71 0x72 0x73 0x74 0x75 0x76 0x77 0x78 0x79 0x7A 0x7B 0x7C 0x7D 0x7E 0x7F )(list 0x1C0 0x1C4 0x1C8 0x1CC 0x1D0 0x1D4 0x1D8 0x1DC 0x1E0 0x1E4 0x1E8 0x1EC 0x1F0 0x1F4 0x1F8 0x1FC ) group.long ($2+0x1C00)++0x3 line.long 0x0 "REGG7_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x80 0x81 0x82 0x83 0x84 0x85 0x86 0x87 0x88 0x89 0x8A 0x8B 0x8C 0x8D 0x8E 0x8F )(list 0x200 0x204 0x208 0x20C 0x210 0x214 0x218 0x21C 0x220 0x224 0x228 0x22C 0x230 0x234 0x238 0x23C ) group.long ($2+0x1C00)++0x3 line.long 0x0 "REGG7_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x90 0x91 0x92 0x93 0x94 0x95 0x96 0x97 0x98 0x99 0x9A 0x9B 0x9C 0x9D 0x9E 0x9F )(list 0x240 0x244 0x248 0x24C 0x250 0x254 0x258 0x25C 0x260 0x264 0x268 0x26C 0x270 0x274 0x278 0x27C ) group.long ($2+0x1C00)++0x3 line.long 0x0 "REGG7_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xA0 0xA1 0xA2 0xA3 0xA4 0xA5 0xA6 0xA7 0xA8 0xA9 0xAA 0xAB 0xAC 0xAD 0xAE 0xAF )(list 0x280 0x284 0x288 0x28C 0x290 0x294 0x298 0x29C 0x2A0 0x2A4 0x2A8 0x2AC 0x2B0 0x2B4 0x2B8 0x2BC ) group.long ($2+0x1C00)++0x3 line.long 0x0 "REGG7_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xB0 0xB1 0xB2 0xB3 0xB4 0xB5 0xB6 0xB7 0xB8 0xB9 0xBA 0xBB 0xBC 0xBD 0xBE 0xBF )(list 0x2C0 0x2C4 0x2C8 0x2CC 0x2D0 0x2D4 0x2D8 0x2DC 0x2E0 0x2E4 0x2E8 0x2EC 0x2F0 0x2F4 0x2F8 0x2FC ) group.long ($2+0x1C00)++0x3 line.long 0x0 "REGG7_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xC0 0xC1 0xC2 0xC3 0xC4 0xC5 0xC6 0xC7 0xC8 0xC9 0xCA 0xCB 0xCC 0xCD 0xCE 0xCF )(list 0x300 0x304 0x308 0x30C 0x310 0x314 0x318 0x31C 0x320 0x324 0x328 0x32C 0x330 0x334 0x338 0x33C ) group.long ($2+0x1C00)++0x3 line.long 0x0 "REGG7_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xD0 0xD1 0xD2 0xD3 0xD4 0xD5 0xD6 0xD7 0xD8 0xD9 0xDA 0xDB 0xDC 0xDD 0xDE 0xDF )(list 0x340 0x344 0x348 0x34C 0x350 0x354 0x358 0x35C 0x360 0x364 0x368 0x36C 0x370 0x374 0x378 0x37C ) group.long ($2+0x1C00)++0x3 line.long 0x0 "REGG7_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xE0 0xE1 0xE2 0xE3 0xE4 0xE5 0xE6 0xE7 0xE8 0xE9 0xEA 0xEB 0xEC 0xED 0xEE 0xEF )(list 0x380 0x384 0x388 0x38C 0x390 0x394 0x398 0x39C 0x3A0 0x3A4 0x3A8 0x3AC 0x3B0 0x3B4 0x3B8 0x3BC ) group.long ($2+0x1C00)++0x3 line.long 0x0 "REGG7_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xF0 0xF1 0xF2 0xF3 0xF4 0xF5 0xF6 0xF7 0xF8 0xF9 0xFA 0xFB 0xFC 0xFD 0xFE 0xFF )(list 0x3C0 0x3C4 0x3C8 0x3CC 0x3D0 0x3D4 0x3D8 0x3DC 0x3E0 0x3E4 0x3E8 0x3EC 0x3F0 0x3F4 0x3F8 0x3FC ) group.long ($2+0x1C00)++0x3 line.long 0x0 "REGG7_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end group.long 0x2000++0x17 line.long 0x0 "GLB_CTL,This register provides global enable settings for permission control." bitfld.long 0x0 5. "DOM_CFG_LOCK,Lock write for DOM_CFG_MODE bit." "0,1" bitfld.long 0x0 4. "DOM_CFG_MODE,When enabled all the source setting can be configured by master from domain 0 if it is not locked. When disabled only resource manager can configure the permission of the resource." "0,1" bitfld.long 0x0 3. "PERCK_DIS_LOCK,Lock write for PERCK_DIS" "0,1" bitfld.long 0x0 2. "PERCK_DIS,All the permission check disable." "0,1" newline bitfld.long 0x0 1. "DOM_PRO_LOCK,Lock write for DOM_PRO_EN bit." "0,1" bitfld.long 0x0 0. "DOM_PRO_EN,When disabled no domain access permission check" "0,1" line.long 0x4 "RES_MGR,Resource manager register. This regster is used to assign resource manager for global resource access control" bitfld.long 0x4 17. "MID_LOCK,Lock write for MID_EN and MID_LOW and MID_HIG registers." "0,1" bitfld.long 0x4 16. "MID_EN,Master ID check enable" "0,1" bitfld.long 0x4 15. "PRI_PER_LOCK,Lock write for PRI_PER and PRI_PER_EN" "0,1" bitfld.long 0x4 13.--14. "PRI_PER,Resource manager privileged access permission. bit0 for privileged access bit1 for user access" "0,1,2,3" newline bitfld.long 0x4 12. "PRI_PER_EN,Resource manager privileged access permission enable." "0,1" bitfld.long 0x4 11. "SEC_PER_LOCK,Lock for SEC_PER and SEC_PER_LOCK" "0,1" bitfld.long 0x4 9.--10. "SEC_PER,Resource manager secure access permission. bit 0 for secure access bit 1 for non-secure access" "0,1,2,3" bitfld.long 0x4 8. "SEC_PER_EN,Resource manager secure permission enable" "0,1" bitfld.long 0x4 7. "DID_LOCK,Lock write for DID_EN and DID" "0,1" newline hexmask.long.byte 0x4 3.--6. 1. "DID,Resource manager domain ID" bitfld.long 0x4 2. "DID_EN,Resource manager Domain ID enable" "0,1" bitfld.long 0x4 1. "RES_MGR_EN_LOCK,Lock for RES_MGR_EN" "0,1" bitfld.long 0x4 0. "RES_MGR_EN,Resource manager enable. When the bit is disable there is no resource manager." "0,1" line.long 0x8 "RES_MGR_MA0,This register is used to assign master 0~31 as resource manager." hexmask.long 0x8 0.--31. 1. "MID,Assign master 0~31 for resource manager" line.long 0xC "RES_MGR_MA1,This register is used to assign master 32~63 as resource manager." hexmask.long 0xC 0.--31. 1. "MID,Indicate if master 32~63 is resource manager." line.long 0x10 "RES_MGR_MA2,This register is used to assign master 64~95 as resource manager." hexmask.long 0x10 0.--31. 1. "MID,Indicate if master 64~95 is resource manager." line.long 0x14 "RES_MGR_MA3,This register is used to assign master 96~127 as resource manager." hexmask.long 0x14 0.--31. 1. "MID,Indicate if master 96~127 is resource manager." repeat 8. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 )(list 0x0 0x14 0x28 0x3C 0x50 0x64 0x78 0x8C ) group.long ($2+0x2100)++0x3 line.long 0x0 "GRP_MGR_$1,Group Manager Register. This register is used to assign group manager for each domain" bitfld.long 0x0 17. "MID_LOCK,Lock write for MID_EN and MID_LOW and MID_HIG registers." "0,1" bitfld.long 0x0 16. "MID_EN,Master ID check enable" "0,1" bitfld.long 0x0 15. "PRI_PER_LOCK,Lock write for PRI_PER and PRI_PER_EN" "0,1" bitfld.long 0x0 13.--14. "PRI_PER,Group manager privileged access permission. bit0 for privileged access bit1 for user access" "0,1,2,3" newline bitfld.long 0x0 12. "PRI_PER_EN,Group manager privileged access permission enable." "0,1" bitfld.long 0x0 11. "SEC_PER_LOCK,Lock for SEC_PER and SEC_PER_LOCK" "0,1" bitfld.long 0x0 9.--10. "SEC_PER,Group manager secure access permission. bit 0 for secure access bit 1 for non-secure access" "0,1,2,3" bitfld.long 0x0 8. "SEC_PER_EN,Group manager secure permission enable" "0,1" bitfld.long 0x0 7. "DID_LOCK,Lock write for DID_EN and DID" "0,1" newline hexmask.long.byte 0x0 3.--6. 1. "DID,Group manager domain ID" bitfld.long 0x0 2. "DID_EN,Group manager Domain ID enable" "0,1" bitfld.long 0x0 1. "GRP_MGR_EN_LOCK,Lock write for GPR_MGR_EN" "0,1" bitfld.long 0x0 0. "GRP_MGR_EN,Group manager enable. When the bit is disable there is no resource manager." "0,1" repeat.end repeat 8. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 )(list 0x0 0x14 0x28 0x3C 0x50 0x64 0x78 0x8C ) group.long ($2+0x2104)++0x3 line.long 0x0 "GRP_MGR_MA0_$1,Assign master 0~31 for group manager 0" hexmask.long 0x0 0.--31. 1. "MID,Assign master 0~31 for resource manager" repeat.end repeat 8. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 )(list 0x0 0x14 0x28 0x3C 0x50 0x64 0x78 0x8C ) group.long ($2+0x2108)++0x3 line.long 0x0 "GRP_MGR_MA1_$1,Assign master 32~63 for group manager 0" hexmask.long 0x0 0.--31. 1. "MID,Indicate if master 32~63 is resource manager." repeat.end repeat 8. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 )(list 0x0 0x14 0x28 0x3C 0x50 0x64 0x78 0x8C ) group.long ($2+0x210C)++0x3 line.long 0x0 "GRP_MGR_MA2_$1,Assign master 64~95 for group manager 0" hexmask.long 0x0 0.--31. 1. "MID,Indicate if master 64~95 is resource manager." repeat.end repeat 8. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 )(list 0x0 0x14 0x28 0x3C 0x50 0x64 0x78 0x8C ) group.long ($2+0x2110)++0x3 line.long 0x0 "GRP_MGR_MA3_$1,Assign master 96~127 for group manager 0" hexmask.long 0x0 0.--31. 1. "MID,Indicate if master 96~127 is resource manager." repeat.end group.long 0x2200++0x3 line.long 0x0 "DOM_GID_0,Indicate which group domain 0 belong to" bitfld.long 0x0 3. "LOCK,Lock write for GID" "0,1" bitfld.long 0x0 0.--2. "GID,Group ID" "0,1,2,3,4,5,6,7" repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x18 0x30 0x48 0x60 0x78 0x90 0xA8 0xC0 0xD8 0xF0 0x108 0x120 0x138 0x150 0x168 ) group.long ($2+0x2204)++0x3 line.long 0x0 "DOM_OWN_$1,Assign owner for function domain 0." bitfld.long 0x0 17. "MID_LOCK,Lock write for MID_EN and MID_LOW and MID_HIG registers." "0,1" bitfld.long 0x0 16. "MID_EN,Master ID check enable" "0,1" bitfld.long 0x0 15. "PRI_PER_LOCK,Lock write for PRI_PER and PRI_PER_EN" "0,1" bitfld.long 0x0 13.--14. "PRI_PER,Group manager privileged access permission. bit0 for privileged access bit1 for user access" "0,1,2,3" newline bitfld.long 0x0 12. "PRI_PER_EN,Group manager privileged access permission enable." "0,1" bitfld.long 0x0 11. "SEC_PER_LOCK,Lock for SEC_PER and SEC_PER_LOCK" "0,1" bitfld.long 0x0 9.--10. "SEC_PER,Domain owner secure access permission. bit 0 for secure access bit 1 for non-secure access" "0,1,2,3" bitfld.long 0x0 8. "SEC_PER_EN,Domain owner secure permission enable" "0,1" newline bitfld.long 0x0 1. "DOM_OWN_EN_LOCK,Lock for DOM_OWN_EN" "0,1" bitfld.long 0x0 0. "DOM_OWN_EN,Domain owner enable. When the bit is disable there is no domain owner." "0,1" repeat.end repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x18 0x30 0x48 0x60 0x78 0x90 0xA8 0xC0 0xD8 0xF0 0x108 0x120 0x138 0x150 0x168 ) group.long ($2+0x2208)++0x3 line.long 0x0 "DOM_OWN_MA0_$1,Assign master 0~31 for domain owner 0" hexmask.long 0x0 0.--31. 1. "MID,Assign master 0~31 for resource manager" repeat.end repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x18 0x30 0x48 0x60 0x78 0x90 0xA8 0xC0 0xD8 0xF0 0x108 0x120 0x138 0x150 0x168 ) group.long ($2+0x220C)++0x3 line.long 0x0 "DOM_OWN_MA1_$1,Assign master 32~63 for domain owner 0" hexmask.long 0x0 0.--31. 1. "MID,Indicate if master 32~63 is resource manager." repeat.end repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x18 0x30 0x48 0x60 0x78 0x90 0xA8 0xC0 0xD8 0xF0 0x108 0x120 0x138 0x150 0x168 ) group.long ($2+0x2210)++0x3 line.long 0x0 "DOM_OWN_MA2_$1,Assign master 64~95 for domain owner 0" hexmask.long 0x0 0.--31. 1. "MID,Indicate if master 64~95 is resource manager." repeat.end repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x18 0x30 0x48 0x60 0x78 0x90 0xA8 0xC0 0xD8 0xF0 0x108 0x120 0x138 0x150 0x168 ) group.long ($2+0x2214)++0x3 line.long 0x0 "DOM_OWN_MA3_$1,Assign master 96~127 for domain owner 0" hexmask.long 0x0 0.--31. 1. "MID,Indicate if master 96~127 is resource manager." repeat.end group.long 0x2218++0x3 line.long 0x0 "DOM_GID_1,Indicate which group domain 1 belong to" bitfld.long 0x0 3. "LOCK,Lock write for GID" "0,1" bitfld.long 0x0 0.--2. "GID,Group ID" "0,1,2,3,4,5,6,7" group.long 0x2230++0x3 line.long 0x0 "DOM_GID_2,Indicate which group domain 2 belong to" bitfld.long 0x0 3. "LOCK,Lock write for GID" "0,1" bitfld.long 0x0 0.--2. "GID,Group ID" "0,1,2,3,4,5,6,7" group.long 0x2248++0x3 line.long 0x0 "DOM_GID_3,Indicate which group domain 3 belong to" bitfld.long 0x0 3. "LOCK,Lock write for GID" "0,1" bitfld.long 0x0 0.--2. "GID,Group ID" "0,1,2,3,4,5,6,7" group.long 0x2260++0x3 line.long 0x0 "DOM_GID_4,Indicate which group domain 4 belong to" bitfld.long 0x0 3. "LOCK,Lock write for GID" "0,1" bitfld.long 0x0 0.--2. "GID,Group ID" "0,1,2,3,4,5,6,7" group.long 0x2278++0x3 line.long 0x0 "DOM_GID_5,Indicate which group domain 5 belong to" bitfld.long 0x0 3. "LOCK,Lock write for GID" "0,1" bitfld.long 0x0 0.--2. "GID,Group ID" "0,1,2,3,4,5,6,7" group.long 0x2290++0x3 line.long 0x0 "DOM_GID_6,Indicate which group domain 6 belong to" bitfld.long 0x0 3. "LOCK,Lock write for GID" "0,1" bitfld.long 0x0 0.--2. "GID,Group ID" "0,1,2,3,4,5,6,7" group.long 0x22A8++0x3 line.long 0x0 "DOM_GID_7,Indicate which group domain 7 belong to" bitfld.long 0x0 3. "LOCK,Lock write for GID" "0,1" bitfld.long 0x0 0.--2. "GID,Group ID" "0,1,2,3,4,5,6,7" group.long 0x22C0++0x3 line.long 0x0 "DOM_GID_8,Indicate which group domain 8 belong to" bitfld.long 0x0 3. "LOCK,Lock write for GID" "0,1" bitfld.long 0x0 0.--2. "GID,Group ID" "0,1,2,3,4,5,6,7" group.long 0x22D8++0x3 line.long 0x0 "DOM_GID_9,Indicate which group domain 9 belong to" bitfld.long 0x0 3. "LOCK,Lock write for GID" "0,1" bitfld.long 0x0 0.--2. "GID,Group ID" "0,1,2,3,4,5,6,7" group.long 0x22F0++0x3 line.long 0x0 "DOM_GID_10,Indicate which group domain 10 belong to" bitfld.long 0x0 3. "LOCK,Lock write for GID" "0,1" bitfld.long 0x0 0.--2. "GID,Group ID" "0,1,2,3,4,5,6,7" group.long 0x2308++0x3 line.long 0x0 "DOM_GID_11,Indicate which group domain 11 belong to" bitfld.long 0x0 3. "LOCK,Lock write for GID" "0,1" bitfld.long 0x0 0.--2. "GID,Group ID" "0,1,2,3,4,5,6,7" group.long 0x2320++0x3 line.long 0x0 "DOM_GID_12,Indicate which group domain 12 belong to" bitfld.long 0x0 3. "LOCK,Lock write for GID" "0,1" bitfld.long 0x0 0.--2. "GID,Group ID" "0,1,2,3,4,5,6,7" group.long 0x2338++0x3 line.long 0x0 "DOM_GID_13,Indicate which group domain 13 belong to" bitfld.long 0x0 3. "LOCK,Lock write for GID" "0,1" bitfld.long 0x0 0.--2. "GID,Group ID" "0,1,2,3,4,5,6,7" group.long 0x2350++0x3 line.long 0x0 "DOM_GID_14,Indicate which group domain 14 belong to" bitfld.long 0x0 3. "LOCK,Lock write for GID" "0,1" bitfld.long 0x0 0.--2. "GID,Group ID" "0,1,2,3,4,5,6,7" group.long 0x2368++0x3 line.long 0x0 "DOM_GID_15,Indicate which group domain 15 belong to" bitfld.long 0x0 3. "LOCK,Lock write for GID" "0,1" bitfld.long 0x0 0.--2. "GID,Group ID" "0,1,2,3,4,5,6,7" repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x34 0x68 0x9C 0xD0 0x104 0x138 0x16C 0x1A0 0x1D4 0x208 0x23C 0x270 0x2A4 0x2D8 0x30C ) group.long ($2+0x2400)++0x3 line.long 0x0 "DOM_PER0_$1,Domain Permission Control. It can be only configured by resource manager and domain owner." bitfld.long 0x0 31. "DOM7_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 29.--30. "DOM7_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 28. "DOM7_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 27. "DOM6_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 25.--26. "DOM6_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" newline bitfld.long 0x0 24. "DOM6_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 23. "DOM5_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 21.--22. "DOM5_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 20. "DOM5_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 19. "DOM4_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" newline bitfld.long 0x0 17.--18. "DOM4_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM4_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 15. "DOM3_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 13.--14. "DOM3_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 12. "DOM3_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" newline bitfld.long 0x0 11. "DOM2_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 9.--10. "DOM2_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM2_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 7. "DOM1_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 5.--6. "DOM1_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" newline bitfld.long 0x0 4. "DOM1_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 3. "DOM0_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 1.--2. "DOM0_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM0_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" repeat.end repeat 16. (list 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1A 0x1B 0x1C 0x1D 0x1E 0x1F )(list 0x340 0x374 0x3A8 0x3DC 0x410 0x444 0x478 0x4AC 0x4E0 0x514 0x548 0x57C 0x5B0 0x5E4 0x618 0x64C ) group.long ($2+0x2400)++0x3 line.long 0x0 "DOM_PER0_$1,Domain Permission Control. It can be only configured by resource manager and domain owner." bitfld.long 0x0 31. "DOM7_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 29.--30. "DOM7_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 28. "DOM7_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 27. "DOM6_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 25.--26. "DOM6_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" newline bitfld.long 0x0 24. "DOM6_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 23. "DOM5_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 21.--22. "DOM5_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 20. "DOM5_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 19. "DOM4_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" newline bitfld.long 0x0 17.--18. "DOM4_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM4_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 15. "DOM3_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 13.--14. "DOM3_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 12. "DOM3_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" newline bitfld.long 0x0 11. "DOM2_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 9.--10. "DOM2_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM2_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 7. "DOM1_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 5.--6. "DOM1_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" newline bitfld.long 0x0 4. "DOM1_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 3. "DOM0_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 1.--2. "DOM0_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM0_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" repeat.end repeat 16. (list 0x20 0x21 0x22 0x23 0x24 0x25 0x26 0x27 0x28 0x29 0x2A 0x2B 0x2C 0x2D 0x2E 0x2F )(list 0x680 0x6B4 0x6E8 0x71C 0x750 0x784 0x7B8 0x7EC 0x820 0x854 0x888 0x8BC 0x8F0 0x924 0x958 0x98C ) group.long ($2+0x2400)++0x3 line.long 0x0 "DOM_PER0_$1,Domain Permission Control. It can be only configured by resource manager and domain owner." bitfld.long 0x0 31. "DOM7_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 29.--30. "DOM7_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 28. "DOM7_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 27. "DOM6_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 25.--26. "DOM6_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" newline bitfld.long 0x0 24. "DOM6_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 23. "DOM5_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 21.--22. "DOM5_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 20. "DOM5_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 19. "DOM4_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" newline bitfld.long 0x0 17.--18. "DOM4_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM4_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 15. "DOM3_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 13.--14. "DOM3_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 12. "DOM3_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" newline bitfld.long 0x0 11. "DOM2_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 9.--10. "DOM2_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM2_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 7. "DOM1_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 5.--6. "DOM1_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" newline bitfld.long 0x0 4. "DOM1_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 3. "DOM0_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 1.--2. "DOM0_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM0_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" repeat.end repeat 16. (list 0x30 0x31 0x32 0x33 0x34 0x35 0x36 0x37 0x38 0x39 0x3A 0x3B 0x3C 0x3D 0x3E 0x3F )(list 0x9C0 0x9F4 0xA28 0xA5C 0xA90 0xAC4 0xAF8 0xB2C 0xB60 0xB94 0xBC8 0xBFC 0xC30 0xC64 0xC98 0xCCC ) group.long ($2+0x2400)++0x3 line.long 0x0 "DOM_PER0_$1,Domain Permission Control. It can be only configured by resource manager and domain owner." bitfld.long 0x0 31. "DOM7_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 29.--30. "DOM7_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 28. "DOM7_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 27. "DOM6_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 25.--26. "DOM6_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" newline bitfld.long 0x0 24. "DOM6_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 23. "DOM5_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 21.--22. "DOM5_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 20. "DOM5_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 19. "DOM4_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" newline bitfld.long 0x0 17.--18. "DOM4_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM4_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 15. "DOM3_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 13.--14. "DOM3_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 12. "DOM3_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" newline bitfld.long 0x0 11. "DOM2_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 9.--10. "DOM2_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM2_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 7. "DOM1_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 5.--6. "DOM1_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" newline bitfld.long 0x0 4. "DOM1_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 3. "DOM0_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 1.--2. "DOM0_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM0_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" repeat.end repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x34 0x68 0x9C 0xD0 0x104 0x138 0x16C 0x1A0 0x1D4 0x208 0x23C 0x270 0x2A4 0x2D8 0x30C ) group.long ($2+0x2404)++0x3 line.long 0x0 "DOM_PER1_$1,Domain Permission Control. It can be only configured by resource manager and domain owner." bitfld.long 0x0 31. "DOM15_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 29.--30. "DOM15_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 28. "DOM15_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 27. "DOM14_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 25.--26. "DOM14_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" newline bitfld.long 0x0 24. "DOM14_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 23. "DOM13_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 21.--22. "DOM13_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 20. "DOM13_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 19. "DOM12_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" newline bitfld.long 0x0 17.--18. "DOM12_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM12_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 15. "DOM11_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 13.--14. "DOM11_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 12. "DOM11_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" newline bitfld.long 0x0 11. "DOM10_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 9.--10. "DOM10_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM10_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 7. "DOM9_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 5.--6. "DOM9_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" newline bitfld.long 0x0 4. "DOM9_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 3. "DOM8_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 1.--2. "DOM8_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM8_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" repeat.end repeat 16. (list 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1A 0x1B 0x1C 0x1D 0x1E 0x1F )(list 0x340 0x374 0x3A8 0x3DC 0x410 0x444 0x478 0x4AC 0x4E0 0x514 0x548 0x57C 0x5B0 0x5E4 0x618 0x64C ) group.long ($2+0x2404)++0x3 line.long 0x0 "DOM_PER1_$1,Domain Permission Control. It can be only configured by resource manager and domain owner." bitfld.long 0x0 31. "DOM15_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 29.--30. "DOM15_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 28. "DOM15_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 27. "DOM14_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 25.--26. "DOM14_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" newline bitfld.long 0x0 24. "DOM14_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 23. "DOM13_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 21.--22. "DOM13_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 20. "DOM13_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 19. "DOM12_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" newline bitfld.long 0x0 17.--18. "DOM12_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM12_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 15. "DOM11_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 13.--14. "DOM11_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 12. "DOM11_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" newline bitfld.long 0x0 11. "DOM10_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 9.--10. "DOM10_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM10_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 7. "DOM9_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 5.--6. "DOM9_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" newline bitfld.long 0x0 4. "DOM9_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 3. "DOM8_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 1.--2. "DOM8_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM8_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" repeat.end repeat 16. (list 0x20 0x21 0x22 0x23 0x24 0x25 0x26 0x27 0x28 0x29 0x2A 0x2B 0x2C 0x2D 0x2E 0x2F )(list 0x680 0x6B4 0x6E8 0x71C 0x750 0x784 0x7B8 0x7EC 0x820 0x854 0x888 0x8BC 0x8F0 0x924 0x958 0x98C ) group.long ($2+0x2404)++0x3 line.long 0x0 "DOM_PER1_$1,Domain Permission Control. It can be only configured by resource manager and domain owner." bitfld.long 0x0 31. "DOM15_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 29.--30. "DOM15_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 28. "DOM15_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 27. "DOM14_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 25.--26. "DOM14_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" newline bitfld.long 0x0 24. "DOM14_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 23. "DOM13_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 21.--22. "DOM13_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 20. "DOM13_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 19. "DOM12_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" newline bitfld.long 0x0 17.--18. "DOM12_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM12_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 15. "DOM11_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 13.--14. "DOM11_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 12. "DOM11_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" newline bitfld.long 0x0 11. "DOM10_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 9.--10. "DOM10_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM10_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 7. "DOM9_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 5.--6. "DOM9_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" newline bitfld.long 0x0 4. "DOM9_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 3. "DOM8_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 1.--2. "DOM8_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM8_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" repeat.end repeat 16. (list 0x30 0x31 0x32 0x33 0x34 0x35 0x36 0x37 0x38 0x39 0x3A 0x3B 0x3C 0x3D 0x3E 0x3F )(list 0x9C0 0x9F4 0xA28 0xA5C 0xA90 0xAC4 0xAF8 0xB2C 0xB60 0xB94 0xBC8 0xBFC 0xC30 0xC64 0xC98 0xCCC ) group.long ($2+0x2404)++0x3 line.long 0x0 "DOM_PER1_$1,Domain Permission Control. It can be only configured by resource manager and domain owner." bitfld.long 0x0 31. "DOM15_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 29.--30. "DOM15_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 28. "DOM15_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 27. "DOM14_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 25.--26. "DOM14_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" newline bitfld.long 0x0 24. "DOM14_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 23. "DOM13_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 21.--22. "DOM13_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 20. "DOM13_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 19. "DOM12_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" newline bitfld.long 0x0 17.--18. "DOM12_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM12_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 15. "DOM11_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 13.--14. "DOM11_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 12. "DOM11_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" newline bitfld.long 0x0 11. "DOM10_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 9.--10. "DOM10_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM10_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 7. "DOM9_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 5.--6. "DOM9_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" newline bitfld.long 0x0 4. "DOM9_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 3. "DOM8_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 1.--2. "DOM8_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM8_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" repeat.end repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x34 0x68 0x9C 0xD0 0x104 0x138 0x16C 0x1A0 0x1D4 0x208 0x23C 0x270 0x2A4 0x2D8 0x30C ) group.long ($2+0x2408)++0x3 line.long 0x0 "SEC_PER0_$1,This register is only used for resource manager to control secure access permission." bitfld.long 0x0 31. "DOM3_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM3_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM3_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM3_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM2_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM2_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM2_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM2_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM1_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM1_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM1_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM1_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM0_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM0_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM0_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM0_SEC_EN,Domain secure permission control enable" "0,1" repeat.end repeat 16. (list 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1A 0x1B 0x1C 0x1D 0x1E 0x1F )(list 0x340 0x374 0x3A8 0x3DC 0x410 0x444 0x478 0x4AC 0x4E0 0x514 0x548 0x57C 0x5B0 0x5E4 0x618 0x64C ) group.long ($2+0x2408)++0x3 line.long 0x0 "SEC_PER0_$1,This register is only used for resource manager to control secure access permission." bitfld.long 0x0 31. "DOM3_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM3_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM3_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM3_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM2_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM2_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM2_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM2_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM1_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM1_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM1_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM1_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM0_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM0_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM0_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM0_SEC_EN,Domain secure permission control enable" "0,1" repeat.end repeat 16. (list 0x20 0x21 0x22 0x23 0x24 0x25 0x26 0x27 0x28 0x29 0x2A 0x2B 0x2C 0x2D 0x2E 0x2F )(list 0x680 0x6B4 0x6E8 0x71C 0x750 0x784 0x7B8 0x7EC 0x820 0x854 0x888 0x8BC 0x8F0 0x924 0x958 0x98C ) group.long ($2+0x2408)++0x3 line.long 0x0 "SEC_PER0_$1,This register is only used for resource manager to control secure access permission." bitfld.long 0x0 31. "DOM3_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM3_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM3_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM3_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM2_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM2_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM2_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM2_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM1_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM1_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM1_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM1_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM0_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM0_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM0_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM0_SEC_EN,Domain secure permission control enable" "0,1" repeat.end repeat 16. (list 0x30 0x31 0x32 0x33 0x34 0x35 0x36 0x37 0x38 0x39 0x3A 0x3B 0x3C 0x3D 0x3E 0x3F )(list 0x9C0 0x9F4 0xA28 0xA5C 0xA90 0xAC4 0xAF8 0xB2C 0xB60 0xB94 0xBC8 0xBFC 0xC30 0xC64 0xC98 0xCCC ) group.long ($2+0x2408)++0x3 line.long 0x0 "SEC_PER0_$1,This register is only used for resource manager to control secure access permission." bitfld.long 0x0 31. "DOM3_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM3_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM3_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM3_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM2_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM2_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM2_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM2_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM1_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM1_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM1_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM1_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM0_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM0_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM0_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM0_SEC_EN,Domain secure permission control enable" "0,1" repeat.end repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x34 0x68 0x9C 0xD0 0x104 0x138 0x16C 0x1A0 0x1D4 0x208 0x23C 0x270 0x2A4 0x2D8 0x30C ) group.long ($2+0x240C)++0x3 line.long 0x0 "SEC_PER1_$1,This register is only used for resource manager to control secure access permission." bitfld.long 0x0 31. "DOM7_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM7_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM7_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM7_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM6_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM6_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM6_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM6_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM5_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM5_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM5_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM5_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM4_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM4_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM4_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM4_SEC_EN,Domain secure permission control enable" "0,1" repeat.end repeat 16. (list 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1A 0x1B 0x1C 0x1D 0x1E 0x1F )(list 0x340 0x374 0x3A8 0x3DC 0x410 0x444 0x478 0x4AC 0x4E0 0x514 0x548 0x57C 0x5B0 0x5E4 0x618 0x64C ) group.long ($2+0x240C)++0x3 line.long 0x0 "SEC_PER1_$1,This register is only used for resource manager to control secure access permission." bitfld.long 0x0 31. "DOM7_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM7_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM7_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM7_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM6_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM6_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM6_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM6_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM5_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM5_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM5_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM5_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM4_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM4_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM4_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM4_SEC_EN,Domain secure permission control enable" "0,1" repeat.end repeat 16. (list 0x20 0x21 0x22 0x23 0x24 0x25 0x26 0x27 0x28 0x29 0x2A 0x2B 0x2C 0x2D 0x2E 0x2F )(list 0x680 0x6B4 0x6E8 0x71C 0x750 0x784 0x7B8 0x7EC 0x820 0x854 0x888 0x8BC 0x8F0 0x924 0x958 0x98C ) group.long ($2+0x240C)++0x3 line.long 0x0 "SEC_PER1_$1,This register is only used for resource manager to control secure access permission." bitfld.long 0x0 31. "DOM7_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM7_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM7_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM7_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM6_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM6_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM6_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM6_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM5_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM5_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM5_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM5_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM4_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM4_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM4_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM4_SEC_EN,Domain secure permission control enable" "0,1" repeat.end repeat 16. (list 0x30 0x31 0x32 0x33 0x34 0x35 0x36 0x37 0x38 0x39 0x3A 0x3B 0x3C 0x3D 0x3E 0x3F )(list 0x9C0 0x9F4 0xA28 0xA5C 0xA90 0xAC4 0xAF8 0xB2C 0xB60 0xB94 0xBC8 0xBFC 0xC30 0xC64 0xC98 0xCCC ) group.long ($2+0x240C)++0x3 line.long 0x0 "SEC_PER1_$1,This register is only used for resource manager to control secure access permission." bitfld.long 0x0 31. "DOM7_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM7_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM7_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM7_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM6_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM6_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM6_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM6_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM5_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM5_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM5_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM5_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM4_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM4_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM4_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM4_SEC_EN,Domain secure permission control enable" "0,1" repeat.end repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x34 0x68 0x9C 0xD0 0x104 0x138 0x16C 0x1A0 0x1D4 0x208 0x23C 0x270 0x2A4 0x2D8 0x30C ) group.long ($2+0x2410)++0x3 line.long 0x0 "SEC_PER2_$1,This register is only used for resource manager to control secure access permission." bitfld.long 0x0 31. "DOM11_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM11_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM11_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM11_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM10_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM10_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM10_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM10_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM9_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM9_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM9_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM9_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM8_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM8_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM8_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM8_SEC_EN,Domain secure permission control enable" "0,1" repeat.end repeat 16. (list 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1A 0x1B 0x1C 0x1D 0x1E 0x1F )(list 0x340 0x374 0x3A8 0x3DC 0x410 0x444 0x478 0x4AC 0x4E0 0x514 0x548 0x57C 0x5B0 0x5E4 0x618 0x64C ) group.long ($2+0x2410)++0x3 line.long 0x0 "SEC_PER2_$1,This register is only used for resource manager to control secure access permission." bitfld.long 0x0 31. "DOM11_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM11_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM11_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM11_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM10_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM10_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM10_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM10_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM9_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM9_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM9_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM9_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM8_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM8_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM8_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM8_SEC_EN,Domain secure permission control enable" "0,1" repeat.end repeat 16. (list 0x20 0x21 0x22 0x23 0x24 0x25 0x26 0x27 0x28 0x29 0x2A 0x2B 0x2C 0x2D 0x2E 0x2F )(list 0x680 0x6B4 0x6E8 0x71C 0x750 0x784 0x7B8 0x7EC 0x820 0x854 0x888 0x8BC 0x8F0 0x924 0x958 0x98C ) group.long ($2+0x2410)++0x3 line.long 0x0 "SEC_PER2_$1,This register is only used for resource manager to control secure access permission." bitfld.long 0x0 31. "DOM11_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM11_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM11_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM11_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM10_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM10_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM10_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM10_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM9_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM9_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM9_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM9_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM8_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM8_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM8_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM8_SEC_EN,Domain secure permission control enable" "0,1" repeat.end repeat 16. (list 0x30 0x31 0x32 0x33 0x34 0x35 0x36 0x37 0x38 0x39 0x3A 0x3B 0x3C 0x3D 0x3E 0x3F )(list 0x9C0 0x9F4 0xA28 0xA5C 0xA90 0xAC4 0xAF8 0xB2C 0xB60 0xB94 0xBC8 0xBFC 0xC30 0xC64 0xC98 0xCCC ) group.long ($2+0x2410)++0x3 line.long 0x0 "SEC_PER2_$1,This register is only used for resource manager to control secure access permission." bitfld.long 0x0 31. "DOM11_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM11_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM11_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM11_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM10_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM10_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM10_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM10_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM9_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM9_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM9_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM9_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM8_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM8_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM8_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM8_SEC_EN,Domain secure permission control enable" "0,1" repeat.end repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x34 0x68 0x9C 0xD0 0x104 0x138 0x16C 0x1A0 0x1D4 0x208 0x23C 0x270 0x2A4 0x2D8 0x30C ) group.long ($2+0x2414)++0x3 line.long 0x0 "SEC_PER3_$1,This register is only used for resource manager to control secure access permission." bitfld.long 0x0 31. "DOM15_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM15_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM15_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM15_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM14_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM14_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM14_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM14_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM13_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM13_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM13_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM13_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM12_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM12_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM12_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM12_SEC_EN,Domain secure permission control enable" "0,1" repeat.end repeat 16. (list 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1A 0x1B 0x1C 0x1D 0x1E 0x1F )(list 0x340 0x374 0x3A8 0x3DC 0x410 0x444 0x478 0x4AC 0x4E0 0x514 0x548 0x57C 0x5B0 0x5E4 0x618 0x64C ) group.long ($2+0x2414)++0x3 line.long 0x0 "SEC_PER3_$1,This register is only used for resource manager to control secure access permission." bitfld.long 0x0 31. "DOM15_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM15_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM15_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM15_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM14_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM14_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM14_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM14_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM13_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM13_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM13_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM13_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM12_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM12_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM12_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM12_SEC_EN,Domain secure permission control enable" "0,1" repeat.end repeat 16. (list 0x20 0x21 0x22 0x23 0x24 0x25 0x26 0x27 0x28 0x29 0x2A 0x2B 0x2C 0x2D 0x2E 0x2F )(list 0x680 0x6B4 0x6E8 0x71C 0x750 0x784 0x7B8 0x7EC 0x820 0x854 0x888 0x8BC 0x8F0 0x924 0x958 0x98C ) group.long ($2+0x2414)++0x3 line.long 0x0 "SEC_PER3_$1,This register is only used for resource manager to control secure access permission." bitfld.long 0x0 31. "DOM15_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM15_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM15_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM15_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM14_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM14_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM14_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM14_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM13_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM13_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM13_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM13_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM12_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM12_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM12_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM12_SEC_EN,Domain secure permission control enable" "0,1" repeat.end repeat 16. (list 0x30 0x31 0x32 0x33 0x34 0x35 0x36 0x37 0x38 0x39 0x3A 0x3B 0x3C 0x3D 0x3E 0x3F )(list 0x9C0 0x9F4 0xA28 0xA5C 0xA90 0xAC4 0xAF8 0xB2C 0xB60 0xB94 0xBC8 0xBFC 0xC30 0xC64 0xC98 0xCCC ) group.long ($2+0x2414)++0x3 line.long 0x0 "SEC_PER3_$1,This register is only used for resource manager to control secure access permission." bitfld.long 0x0 31. "DOM15_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM15_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM15_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM15_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM14_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM14_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM14_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM14_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM13_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM13_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM13_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM13_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM12_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM12_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM12_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM12_SEC_EN,Domain secure permission control enable" "0,1" repeat.end repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x34 0x68 0x9C 0xD0 0x104 0x138 0x16C 0x1A0 0x1D4 0x208 0x23C 0x270 0x2A4 0x2D8 0x30C ) group.long ($2+0x2418)++0x3 line.long 0x0 "PRI_PER0_$1,This register is only used for resource manager to control privileged access permission." bitfld.long 0x0 31. "DOM3_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM3_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM3_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM3_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM2_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM2_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM2_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM2_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM1_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM1_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM1_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM1_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM0_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM0_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM0_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM0_PRI_EN,Domain privileged permission control enable" "0,1" repeat.end repeat 16. (list 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1A 0x1B 0x1C 0x1D 0x1E 0x1F )(list 0x340 0x374 0x3A8 0x3DC 0x410 0x444 0x478 0x4AC 0x4E0 0x514 0x548 0x57C 0x5B0 0x5E4 0x618 0x64C ) group.long ($2+0x2418)++0x3 line.long 0x0 "PRI_PER0_$1,This register is only used for resource manager to control privileged access permission." bitfld.long 0x0 31. "DOM3_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM3_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM3_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM3_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM2_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM2_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM2_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM2_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM1_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM1_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM1_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM1_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM0_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM0_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM0_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM0_PRI_EN,Domain privileged permission control enable" "0,1" repeat.end repeat 16. (list 0x20 0x21 0x22 0x23 0x24 0x25 0x26 0x27 0x28 0x29 0x2A 0x2B 0x2C 0x2D 0x2E 0x2F )(list 0x680 0x6B4 0x6E8 0x71C 0x750 0x784 0x7B8 0x7EC 0x820 0x854 0x888 0x8BC 0x8F0 0x924 0x958 0x98C ) group.long ($2+0x2418)++0x3 line.long 0x0 "PRI_PER0_$1,This register is only used for resource manager to control privileged access permission." bitfld.long 0x0 31. "DOM3_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM3_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM3_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM3_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM2_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM2_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM2_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM2_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM1_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM1_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM1_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM1_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM0_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM0_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM0_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM0_PRI_EN,Domain privileged permission control enable" "0,1" repeat.end repeat 16. (list 0x30 0x31 0x32 0x33 0x34 0x35 0x36 0x37 0x38 0x39 0x3A 0x3B 0x3C 0x3D 0x3E 0x3F )(list 0x9C0 0x9F4 0xA28 0xA5C 0xA90 0xAC4 0xAF8 0xB2C 0xB60 0xB94 0xBC8 0xBFC 0xC30 0xC64 0xC98 0xCCC ) group.long ($2+0x2418)++0x3 line.long 0x0 "PRI_PER0_$1,This register is only used for resource manager to control privileged access permission." bitfld.long 0x0 31. "DOM3_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM3_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM3_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM3_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM2_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM2_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM2_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM2_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM1_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM1_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM1_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM1_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM0_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM0_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM0_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM0_PRI_EN,Domain privileged permission control enable" "0,1" repeat.end repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x34 0x68 0x9C 0xD0 0x104 0x138 0x16C 0x1A0 0x1D4 0x208 0x23C 0x270 0x2A4 0x2D8 0x30C ) group.long ($2+0x241C)++0x3 line.long 0x0 "PRI_PER1_$1,This register is only used for resource manager to control privileged access permission." bitfld.long 0x0 31. "DOM7_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM7_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM7_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM7_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM6_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM6_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM6_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM6_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM5_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM5_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM5_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM5_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM4_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM4_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM4_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM4_PRI_EN,Domain privileged permission control enable" "0,1" repeat.end repeat 16. (list 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1A 0x1B 0x1C 0x1D 0x1E 0x1F )(list 0x340 0x374 0x3A8 0x3DC 0x410 0x444 0x478 0x4AC 0x4E0 0x514 0x548 0x57C 0x5B0 0x5E4 0x618 0x64C ) group.long ($2+0x241C)++0x3 line.long 0x0 "PRI_PER1_$1,This register is only used for resource manager to control privileged access permission." bitfld.long 0x0 31. "DOM7_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM7_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM7_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM7_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM6_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM6_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM6_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM6_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM5_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM5_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM5_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM5_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM4_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM4_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM4_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM4_PRI_EN,Domain privileged permission control enable" "0,1" repeat.end repeat 16. (list 0x20 0x21 0x22 0x23 0x24 0x25 0x26 0x27 0x28 0x29 0x2A 0x2B 0x2C 0x2D 0x2E 0x2F )(list 0x680 0x6B4 0x6E8 0x71C 0x750 0x784 0x7B8 0x7EC 0x820 0x854 0x888 0x8BC 0x8F0 0x924 0x958 0x98C ) group.long ($2+0x241C)++0x3 line.long 0x0 "PRI_PER1_$1,This register is only used for resource manager to control privileged access permission." bitfld.long 0x0 31. "DOM7_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM7_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM7_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM7_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM6_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM6_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM6_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM6_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM5_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM5_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM5_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM5_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM4_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM4_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM4_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM4_PRI_EN,Domain privileged permission control enable" "0,1" repeat.end repeat 16. (list 0x30 0x31 0x32 0x33 0x34 0x35 0x36 0x37 0x38 0x39 0x3A 0x3B 0x3C 0x3D 0x3E 0x3F )(list 0x9C0 0x9F4 0xA28 0xA5C 0xA90 0xAC4 0xAF8 0xB2C 0xB60 0xB94 0xBC8 0xBFC 0xC30 0xC64 0xC98 0xCCC ) group.long ($2+0x241C)++0x3 line.long 0x0 "PRI_PER1_$1,This register is only used for resource manager to control privileged access permission." bitfld.long 0x0 31. "DOM7_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM7_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM7_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM7_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM6_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM6_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM6_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM6_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM5_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM5_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM5_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM5_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM4_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM4_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM4_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM4_PRI_EN,Domain privileged permission control enable" "0,1" repeat.end repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x34 0x68 0x9C 0xD0 0x104 0x138 0x16C 0x1A0 0x1D4 0x208 0x23C 0x270 0x2A4 0x2D8 0x30C ) group.long ($2+0x2420)++0x3 line.long 0x0 "PRI_PER2_$1,This register is only used for resource manager to control privileged access permission." bitfld.long 0x0 31. "DOM11_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM11_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM11_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM11_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM10_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM10_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM10_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM10_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM9_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM9_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM9_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM9_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM8_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM8_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM8_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM8_PRI_EN,Domain privileged permission control enable" "0,1" repeat.end repeat 16. (list 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1A 0x1B 0x1C 0x1D 0x1E 0x1F )(list 0x340 0x374 0x3A8 0x3DC 0x410 0x444 0x478 0x4AC 0x4E0 0x514 0x548 0x57C 0x5B0 0x5E4 0x618 0x64C ) group.long ($2+0x2420)++0x3 line.long 0x0 "PRI_PER2_$1,This register is only used for resource manager to control privileged access permission." bitfld.long 0x0 31. "DOM11_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM11_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM11_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM11_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM10_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM10_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM10_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM10_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM9_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM9_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM9_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM9_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM8_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM8_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM8_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM8_PRI_EN,Domain privileged permission control enable" "0,1" repeat.end repeat 16. (list 0x20 0x21 0x22 0x23 0x24 0x25 0x26 0x27 0x28 0x29 0x2A 0x2B 0x2C 0x2D 0x2E 0x2F )(list 0x680 0x6B4 0x6E8 0x71C 0x750 0x784 0x7B8 0x7EC 0x820 0x854 0x888 0x8BC 0x8F0 0x924 0x958 0x98C ) group.long ($2+0x2420)++0x3 line.long 0x0 "PRI_PER2_$1,This register is only used for resource manager to control privileged access permission." bitfld.long 0x0 31. "DOM11_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM11_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM11_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM11_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM10_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM10_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM10_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM10_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM9_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM9_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM9_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM9_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM8_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM8_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM8_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM8_PRI_EN,Domain privileged permission control enable" "0,1" repeat.end repeat 16. (list 0x30 0x31 0x32 0x33 0x34 0x35 0x36 0x37 0x38 0x39 0x3A 0x3B 0x3C 0x3D 0x3E 0x3F )(list 0x9C0 0x9F4 0xA28 0xA5C 0xA90 0xAC4 0xAF8 0xB2C 0xB60 0xB94 0xBC8 0xBFC 0xC30 0xC64 0xC98 0xCCC ) group.long ($2+0x2420)++0x3 line.long 0x0 "PRI_PER2_$1,This register is only used for resource manager to control privileged access permission." bitfld.long 0x0 31. "DOM11_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM11_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM11_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM11_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM10_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM10_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM10_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM10_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM9_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM9_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM9_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM9_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM8_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM8_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM8_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM8_PRI_EN,Domain privileged permission control enable" "0,1" repeat.end repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x34 0x68 0x9C 0xD0 0x104 0x138 0x16C 0x1A0 0x1D4 0x208 0x23C 0x270 0x2A4 0x2D8 0x30C ) group.long ($2+0x2424)++0x3 line.long 0x0 "PRI_PER3_$1,This register is only used for resource manager to control privileged access permission." bitfld.long 0x0 31. "DOM15_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM15_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM15_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM15_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM14_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM14_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM14_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM14_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM13_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM13_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM13_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM13_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM12_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM12_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM12_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM12_PRI_EN,Domain privileged permission control enable" "0,1" repeat.end repeat 16. (list 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1A 0x1B 0x1C 0x1D 0x1E 0x1F )(list 0x340 0x374 0x3A8 0x3DC 0x410 0x444 0x478 0x4AC 0x4E0 0x514 0x548 0x57C 0x5B0 0x5E4 0x618 0x64C ) group.long ($2+0x2424)++0x3 line.long 0x0 "PRI_PER3_$1,This register is only used for resource manager to control privileged access permission." bitfld.long 0x0 31. "DOM15_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM15_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM15_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM15_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM14_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM14_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM14_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM14_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM13_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM13_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM13_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM13_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM12_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM12_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM12_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM12_PRI_EN,Domain privileged permission control enable" "0,1" repeat.end repeat 16. (list 0x20 0x21 0x22 0x23 0x24 0x25 0x26 0x27 0x28 0x29 0x2A 0x2B 0x2C 0x2D 0x2E 0x2F )(list 0x680 0x6B4 0x6E8 0x71C 0x750 0x784 0x7B8 0x7EC 0x820 0x854 0x888 0x8BC 0x8F0 0x924 0x958 0x98C ) group.long ($2+0x2424)++0x3 line.long 0x0 "PRI_PER3_$1,This register is only used for resource manager to control privileged access permission." bitfld.long 0x0 31. "DOM15_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM15_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM15_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM15_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM14_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM14_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM14_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM14_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM13_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM13_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM13_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM13_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM12_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM12_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM12_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM12_PRI_EN,Domain privileged permission control enable" "0,1" repeat.end repeat 16. (list 0x30 0x31 0x32 0x33 0x34 0x35 0x36 0x37 0x38 0x39 0x3A 0x3B 0x3C 0x3D 0x3E 0x3F )(list 0x9C0 0x9F4 0xA28 0xA5C 0xA90 0xAC4 0xAF8 0xB2C 0xB60 0xB94 0xBC8 0xBFC 0xC30 0xC64 0xC98 0xCCC ) group.long ($2+0x2424)++0x3 line.long 0x0 "PRI_PER3_$1,This register is only used for resource manager to control privileged access permission." bitfld.long 0x0 31. "DOM15_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM15_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM15_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM15_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM14_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM14_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM14_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM14_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM13_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM13_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM13_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM13_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM12_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM12_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM12_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM12_PRI_EN,Domain privileged permission control enable" "0,1" repeat.end repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x34 0x68 0x9C 0xD0 0x104 0x138 0x16C 0x1A0 0x1D4 0x208 0x23C 0x270 0x2A4 0x2D8 0x30C ) group.long ($2+0x2428)++0x3 line.long 0x0 "DOM_SEC_PER_$1,This register is only used for domain master to control secure access permission. When the domain master write this register. it only changes the secure permission for itself. When the domain master read this register. it gets permission.." bitfld.long 0x0 7. "DOM_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" newline bitfld.long 0x0 0. "DOM_SEC_EN,Domain secure permission control enable" "0,1" repeat.end repeat 16. (list 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1A 0x1B 0x1C 0x1D 0x1E 0x1F )(list 0x340 0x374 0x3A8 0x3DC 0x410 0x444 0x478 0x4AC 0x4E0 0x514 0x548 0x57C 0x5B0 0x5E4 0x618 0x64C ) group.long ($2+0x2428)++0x3 line.long 0x0 "DOM_SEC_PER_$1,This register is only used for domain master to control secure access permission. When the domain master write this register. it only changes the secure permission for itself. When the domain master read this register. it gets permission.." bitfld.long 0x0 7. "DOM_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" newline bitfld.long 0x0 0. "DOM_SEC_EN,Domain secure permission control enable" "0,1" repeat.end repeat 16. (list 0x20 0x21 0x22 0x23 0x24 0x25 0x26 0x27 0x28 0x29 0x2A 0x2B 0x2C 0x2D 0x2E 0x2F )(list 0x680 0x6B4 0x6E8 0x71C 0x750 0x784 0x7B8 0x7EC 0x820 0x854 0x888 0x8BC 0x8F0 0x924 0x958 0x98C ) group.long ($2+0x2428)++0x3 line.long 0x0 "DOM_SEC_PER_$1,This register is only used for domain master to control secure access permission. When the domain master write this register. it only changes the secure permission for itself. When the domain master read this register. it gets permission.." bitfld.long 0x0 7. "DOM_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" newline bitfld.long 0x0 0. "DOM_SEC_EN,Domain secure permission control enable" "0,1" repeat.end repeat 16. (list 0x30 0x31 0x32 0x33 0x34 0x35 0x36 0x37 0x38 0x39 0x3A 0x3B 0x3C 0x3D 0x3E 0x3F )(list 0x9C0 0x9F4 0xA28 0xA5C 0xA90 0xAC4 0xAF8 0xB2C 0xB60 0xB94 0xBC8 0xBFC 0xC30 0xC64 0xC98 0xCCC ) group.long ($2+0x2428)++0x3 line.long 0x0 "DOM_SEC_PER_$1,This register is only used for domain master to control secure access permission. When the domain master write this register. it only changes the secure permission for itself. When the domain master read this register. it gets permission.." bitfld.long 0x0 7. "DOM_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" newline bitfld.long 0x0 0. "DOM_SEC_EN,Domain secure permission control enable" "0,1" repeat.end repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x34 0x68 0x9C 0xD0 0x104 0x138 0x16C 0x1A0 0x1D4 0x208 0x23C 0x270 0x2A4 0x2D8 0x30C ) group.long ($2+0x242C)++0x3 line.long 0x0 "DOM_PRI_PER_$1,This register is only used for domain master to control secure access permission. When the domain master write this register. it only changes the secure permission for itself. When the domain master read this register. it gets permission.." bitfld.long 0x0 7. "DOM_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" newline bitfld.long 0x0 0. "DOM_PRI_EN,Domain privileged permission control enable" "0,1" repeat.end repeat 16. (list 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1A 0x1B 0x1C 0x1D 0x1E 0x1F )(list 0x340 0x374 0x3A8 0x3DC 0x410 0x444 0x478 0x4AC 0x4E0 0x514 0x548 0x57C 0x5B0 0x5E4 0x618 0x64C ) group.long ($2+0x242C)++0x3 line.long 0x0 "DOM_PRI_PER_$1,This register is only used for domain master to control secure access permission. When the domain master write this register. it only changes the secure permission for itself. When the domain master read this register. it gets permission.." bitfld.long 0x0 7. "DOM_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" newline bitfld.long 0x0 0. "DOM_PRI_EN,Domain privileged permission control enable" "0,1" repeat.end repeat 16. (list 0x20 0x21 0x22 0x23 0x24 0x25 0x26 0x27 0x28 0x29 0x2A 0x2B 0x2C 0x2D 0x2E 0x2F )(list 0x680 0x6B4 0x6E8 0x71C 0x750 0x784 0x7B8 0x7EC 0x820 0x854 0x888 0x8BC 0x8F0 0x924 0x958 0x98C ) group.long ($2+0x242C)++0x3 line.long 0x0 "DOM_PRI_PER_$1,This register is only used for domain master to control secure access permission. When the domain master write this register. it only changes the secure permission for itself. When the domain master read this register. it gets permission.." bitfld.long 0x0 7. "DOM_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" newline bitfld.long 0x0 0. "DOM_PRI_EN,Domain privileged permission control enable" "0,1" repeat.end repeat 16. (list 0x30 0x31 0x32 0x33 0x34 0x35 0x36 0x37 0x38 0x39 0x3A 0x3B 0x3C 0x3D 0x3E 0x3F )(list 0x9C0 0x9F4 0xA28 0xA5C 0xA90 0xAC4 0xAF8 0xB2C 0xB60 0xB94 0xBC8 0xBFC 0xC30 0xC64 0xC98 0xCCC ) group.long ($2+0x242C)++0x3 line.long 0x0 "DOM_PRI_PER_$1,This register is only used for domain master to control secure access permission. When the domain master write this register. it only changes the secure permission for itself. When the domain master read this register. it gets permission.." bitfld.long 0x0 7. "DOM_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" newline bitfld.long 0x0 0. "DOM_PRI_EN,Domain privileged permission control enable" "0,1" repeat.end repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x34 0x68 0x9C 0xD0 0x104 0x138 0x16C 0x1A0 0x1D4 0x208 0x23C 0x270 0x2A4 0x2D8 0x30C ) group.long ($2+0x2430)++0x3 line.long 0x0 "DOM_ASSIGN_$1,Use to assign domain for accessing DOM_SEC_PER and DOM_PRI_PER register. Only resource manager. group manager and domain owner can access this register. For write. group manager must write its owen domain ID. otherwise write accessing will.." hexmask.long.byte 0x0 0.--3. 1. "DID,accessing DOM_SEC_PER and DOM_PRI_PER register" repeat.end repeat 16. (list 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1A 0x1B 0x1C 0x1D 0x1E 0x1F )(list 0x340 0x374 0x3A8 0x3DC 0x410 0x444 0x478 0x4AC 0x4E0 0x514 0x548 0x57C 0x5B0 0x5E4 0x618 0x64C ) group.long ($2+0x2430)++0x3 line.long 0x0 "DOM_ASSIGN_$1,Use to assign domain for accessing DOM_SEC_PER and DOM_PRI_PER register. Only resource manager. group manager and domain owner can access this register. For write. group manager must write its owen domain ID. otherwise write accessing will.." hexmask.long.byte 0x0 0.--3. 1. "DID,accessing DOM_SEC_PER and DOM_PRI_PER register" repeat.end repeat 16. (list 0x20 0x21 0x22 0x23 0x24 0x25 0x26 0x27 0x28 0x29 0x2A 0x2B 0x2C 0x2D 0x2E 0x2F )(list 0x680 0x6B4 0x6E8 0x71C 0x750 0x784 0x7B8 0x7EC 0x820 0x854 0x888 0x8BC 0x8F0 0x924 0x958 0x98C ) group.long ($2+0x2430)++0x3 line.long 0x0 "DOM_ASSIGN_$1,Use to assign domain for accessing DOM_SEC_PER and DOM_PRI_PER register. Only resource manager. group manager and domain owner can access this register. For write. group manager must write its owen domain ID. otherwise write accessing will.." hexmask.long.byte 0x0 0.--3. 1. "DID,accessing DOM_SEC_PER and DOM_PRI_PER register" repeat.end repeat 16. (list 0x30 0x31 0x32 0x33 0x34 0x35 0x36 0x37 0x38 0x39 0x3A 0x3B 0x3C 0x3D 0x3E 0x3F )(list 0x9C0 0x9F4 0xA28 0xA5C 0xA90 0xAC4 0xAF8 0xB2C 0xB60 0xB94 0xBC8 0xBFC 0xC30 0xC64 0xC98 0xCCC ) group.long ($2+0x2430)++0x3 line.long 0x0 "DOM_ASSIGN_$1,Use to assign domain for accessing DOM_SEC_PER and DOM_PRI_PER register. Only resource manager. group manager and domain owner can access this register. For write. group manager must write its owen domain ID. otherwise write accessing will.." hexmask.long.byte 0x0 0.--3. 1. "DID,accessing DOM_SEC_PER and DOM_PRI_PER register" repeat.end repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x38 0x70 0xA8 0xE0 0x118 0x150 0x188 0x1C0 0x1F8 0x230 0x268 0x2A0 0x2D8 0x310 0x348 ) group.long ($2+0x3100)++0x3 line.long 0x0 "RGN_DOM_$1,Assign domain for peripheral. It can be only configured by resource and group manager" bitfld.long 0x0 31. "LOCK,When this bit is set lock write for all the bits in the register." "0,1" bitfld.long 0x0 4. "SET,Set together with DID would change permission of this resource to following setting: 1) Domain access control enabled. 2) Read/Write allowed for the domain owner. 3) Read/Write not allowed for all the other domains. If this bit is not set only DID.." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Assign domain for peripheral" repeat.end repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x38 0x70 0xA8 0xE0 0x118 0x150 0x188 0x1C0 0x1F8 0x230 0x268 0x2A0 0x2D8 0x310 0x348 ) group.long ($2+0x3104)++0x3 line.long 0x0 "RGN_DOM_PER0_$1,Domain Permission Control. It can be only configured by resource manager and domain owner." bitfld.long 0x0 31. "DOM7_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 29.--30. "DOM7_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 28. "DOM7_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 27. "DOM6_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 25.--26. "DOM6_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" newline bitfld.long 0x0 24. "DOM6_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 23. "DOM5_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 21.--22. "DOM5_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 20. "DOM5_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 19. "DOM4_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" newline bitfld.long 0x0 17.--18. "DOM4_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM4_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 15. "DOM3_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 13.--14. "DOM3_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 12. "DOM3_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" newline bitfld.long 0x0 11. "DOM2_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 9.--10. "DOM2_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM2_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 7. "DOM1_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 5.--6. "DOM1_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" newline bitfld.long 0x0 4. "DOM1_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 3. "DOM0_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 1.--2. "DOM0_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM0_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" repeat.end repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x38 0x70 0xA8 0xE0 0x118 0x150 0x188 0x1C0 0x1F8 0x230 0x268 0x2A0 0x2D8 0x310 0x348 ) group.long ($2+0x3108)++0x3 line.long 0x0 "RGN_DOM_PER1_$1,Domain Permission Control. It can be only configured by resource manager and domain owner." bitfld.long 0x0 31. "DOM15_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 29.--30. "DOM15_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 28. "DOM15_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 27. "DOM14_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 25.--26. "DOM14_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" newline bitfld.long 0x0 24. "DOM14_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 23. "DOM13_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 21.--22. "DOM13_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 20. "DOM13_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 19. "DOM12_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" newline bitfld.long 0x0 17.--18. "DOM12_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM12_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 15. "DOM11_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 13.--14. "DOM11_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 12. "DOM11_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" newline bitfld.long 0x0 11. "DOM10_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 9.--10. "DOM10_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM10_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 7. "DOM9_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 5.--6. "DOM9_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" newline bitfld.long 0x0 4. "DOM9_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 3. "DOM8_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 1.--2. "DOM8_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM8_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" repeat.end repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x38 0x70 0xA8 0xE0 0x118 0x150 0x188 0x1C0 0x1F8 0x230 0x268 0x2A0 0x2D8 0x310 0x348 ) group.long ($2+0x310C)++0x3 line.long 0x0 "RGN_SEC_PER0_$1,This register is only used for resource manager to control secure access permission." bitfld.long 0x0 31. "DOM3_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM3_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM3_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM3_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM2_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM2_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM2_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM2_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM1_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM1_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM1_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM1_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM0_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM0_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM0_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM0_SEC_EN,Domain secure permission control enable" "0,1" repeat.end repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x38 0x70 0xA8 0xE0 0x118 0x150 0x188 0x1C0 0x1F8 0x230 0x268 0x2A0 0x2D8 0x310 0x348 ) group.long ($2+0x3110)++0x3 line.long 0x0 "RGN_SEC_PER1_$1,This register is only used for resource manager to control secure access permission." bitfld.long 0x0 31. "DOM7_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM7_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM7_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM7_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM6_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM6_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM6_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM6_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM5_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM5_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM5_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM5_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM4_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM4_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM4_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM4_SEC_EN,Domain secure permission control enable" "0,1" repeat.end repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x38 0x70 0xA8 0xE0 0x118 0x150 0x188 0x1C0 0x1F8 0x230 0x268 0x2A0 0x2D8 0x310 0x348 ) group.long ($2+0x3114)++0x3 line.long 0x0 "RGN_SEC_PER2_$1,This register is only used for resource manager to control secure access permission." bitfld.long 0x0 31. "DOM11_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM11_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM11_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM11_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM10_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM10_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM10_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM10_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM9_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM9_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM9_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM9_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM8_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM8_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM8_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM8_SEC_EN,Domain secure permission control enable" "0,1" repeat.end repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x38 0x70 0xA8 0xE0 0x118 0x150 0x188 0x1C0 0x1F8 0x230 0x268 0x2A0 0x2D8 0x310 0x348 ) group.long ($2+0x3118)++0x3 line.long 0x0 "RGN_SEC_PER3_$1,This register is only used for resource manager to control secure access permission." bitfld.long 0x0 31. "DOM15_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM15_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM15_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM15_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM14_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM14_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM14_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM14_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM13_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM13_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM13_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM13_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM12_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM12_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM12_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM12_SEC_EN,Domain secure permission control enable" "0,1" repeat.end repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x38 0x70 0xA8 0xE0 0x118 0x150 0x188 0x1C0 0x1F8 0x230 0x268 0x2A0 0x2D8 0x310 0x348 ) group.long ($2+0x311C)++0x3 line.long 0x0 "RGN_PRI_PER0_$1,This register is only used for resource manager to control privileged access permission." bitfld.long 0x0 31. "DOM3_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM3_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM3_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM3_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM2_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM2_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM2_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM2_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM1_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM1_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM1_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM1_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM0_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM0_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM0_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM0_PRI_EN,Domain privileged permission control enable" "0,1" repeat.end repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x38 0x70 0xA8 0xE0 0x118 0x150 0x188 0x1C0 0x1F8 0x230 0x268 0x2A0 0x2D8 0x310 0x348 ) group.long ($2+0x3120)++0x3 line.long 0x0 "RGN_PRI_PER1_$1,This register is only used for resource manager to control privileged access permission." bitfld.long 0x0 31. "DOM7_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM7_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM7_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM7_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM6_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM6_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM6_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM6_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM5_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM5_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM5_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM5_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM4_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM4_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM4_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM4_PRI_EN,Domain privileged permission control enable" "0,1" repeat.end repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x38 0x70 0xA8 0xE0 0x118 0x150 0x188 0x1C0 0x1F8 0x230 0x268 0x2A0 0x2D8 0x310 0x348 ) group.long ($2+0x3124)++0x3 line.long 0x0 "RGN_PRI_PER2_$1,This register is only used for resource manager to control privileged access permission." bitfld.long 0x0 31. "DOM11_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM11_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM11_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM11_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM10_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM10_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM10_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM10_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM9_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM9_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM9_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM9_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM8_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM8_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM8_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM8_PRI_EN,Domain privileged permission control enable" "0,1" repeat.end repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x38 0x70 0xA8 0xE0 0x118 0x150 0x188 0x1C0 0x1F8 0x230 0x268 0x2A0 0x2D8 0x310 0x348 ) group.long ($2+0x3128)++0x3 line.long 0x0 "RGN_PRI_PER3_$1,This register is only used for resource manager to control privileged access permission." bitfld.long 0x0 31. "DOM15_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM15_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM15_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM15_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM14_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM14_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM14_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM14_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM13_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM13_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM13_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM13_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM12_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM12_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM12_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM12_PRI_EN,Domain privileged permission control enable" "0,1" repeat.end repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x38 0x70 0xA8 0xE0 0x118 0x150 0x188 0x1C0 0x1F8 0x230 0x268 0x2A0 0x2D8 0x310 0x348 ) group.long ($2+0x312C)++0x3 line.long 0x0 "RGN_DOM_SEC_PER_$1,This register is only used for domain master to control secure access permission. When the domain master write this register. it only changes the secure permission for itself. When the domain master read this register. it gets.." bitfld.long 0x0 7. "DOM_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" newline bitfld.long 0x0 0. "DOM_SEC_EN,Domain secure permission control enable" "0,1" repeat.end repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x38 0x70 0xA8 0xE0 0x118 0x150 0x188 0x1C0 0x1F8 0x230 0x268 0x2A0 0x2D8 0x310 0x348 ) group.long ($2+0x3130)++0x3 line.long 0x0 "RGN_DOM_PRI_PER_$1,This register is only used for domain master to control secure access permission. When the domain master write this register. it only changes the secure permission for itself. When the domain master read this register. it gets.." bitfld.long 0x0 7. "DOM_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" newline bitfld.long 0x0 0. "DOM_PRI_EN,Domain privileged permission control enable" "0,1" repeat.end repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x38 0x70 0xA8 0xE0 0x118 0x150 0x188 0x1C0 0x1F8 0x230 0x268 0x2A0 0x2D8 0x310 0x348 ) group.long ($2+0x3134)++0x3 line.long 0x0 "RGN_DOM_ASSIGN_$1,Use to assign domain for accessing DOM_SEC_PER and DOM_PRI_PER register. Only resource manager. group manager and domain owner can access this register. For write. group manager must write its owen domain ID. otherwise write accessing.." hexmask.long.byte 0x0 0.--3. 1. "DID,accessing DOM_SEC_PER and DOM_PRI_PER register" repeat.end tree.end tree "RPC_SAFETY_GLOBAL" base ad:0x3CFFE000 repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x4 0x8 0xC 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C ) group.long ($2)++0x3 line.long 0x0 "REGG0_DOM_$1,Assign domain for CKGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1A 0x1B 0x1C 0x1D 0x1E 0x1F )(list 0x40 0x44 0x48 0x4C 0x50 0x54 0x58 0x5C 0x60 0x64 0x68 0x6C 0x70 0x74 0x78 0x7C ) group.long ($2)++0x3 line.long 0x0 "REGG0_DOM_$1,Assign domain for CKGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x20 0x21 0x22 0x23 0x24 0x25 0x26 0x27 0x28 0x29 0x2A 0x2B 0x2C 0x2D 0x2E 0x2F )(list 0x80 0x84 0x88 0x8C 0x90 0x94 0x98 0x9C 0xA0 0xA4 0xA8 0xAC 0xB0 0xB4 0xB8 0xBC ) group.long ($2)++0x3 line.long 0x0 "REGG0_DOM_$1,Assign domain for CKGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x30 0x31 0x32 0x33 0x34 0x35 0x36 0x37 0x38 0x39 0x3A 0x3B 0x3C 0x3D 0x3E 0x3F )(list 0xC0 0xC4 0xC8 0xCC 0xD0 0xD4 0xD8 0xDC 0xE0 0xE4 0xE8 0xEC 0xF0 0xF4 0xF8 0xFC ) group.long ($2)++0x3 line.long 0x0 "REGG0_DOM_$1,Assign domain for CKGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x40 0x41 0x42 0x43 0x44 0x45 0x46 0x47 0x48 0x49 0x4A 0x4B 0x4C 0x4D 0x4E 0x4F )(list 0x100 0x104 0x108 0x10C 0x110 0x114 0x118 0x11C 0x120 0x124 0x128 0x12C 0x130 0x134 0x138 0x13C ) group.long ($2)++0x3 line.long 0x0 "REGG0_DOM_$1,Assign domain for CKGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x50 0x51 0x52 0x53 0x54 0x55 0x56 0x57 0x58 0x59 0x5A 0x5B 0x5C 0x5D 0x5E 0x5F )(list 0x140 0x144 0x148 0x14C 0x150 0x154 0x158 0x15C 0x160 0x164 0x168 0x16C 0x170 0x174 0x178 0x17C ) group.long ($2)++0x3 line.long 0x0 "REGG0_DOM_$1,Assign domain for CKGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x60 0x61 0x62 0x63 0x64 0x65 0x66 0x67 0x68 0x69 0x6A 0x6B 0x6C 0x6D 0x6E 0x6F )(list 0x180 0x184 0x188 0x18C 0x190 0x194 0x198 0x19C 0x1A0 0x1A4 0x1A8 0x1AC 0x1B0 0x1B4 0x1B8 0x1BC ) group.long ($2)++0x3 line.long 0x0 "REGG0_DOM_$1,Assign domain for CKGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x70 0x71 0x72 0x73 0x74 0x75 0x76 0x77 0x78 0x79 0x7A 0x7B 0x7C 0x7D 0x7E 0x7F )(list 0x1C0 0x1C4 0x1C8 0x1CC 0x1D0 0x1D4 0x1D8 0x1DC 0x1E0 0x1E4 0x1E8 0x1EC 0x1F0 0x1F4 0x1F8 0x1FC ) group.long ($2)++0x3 line.long 0x0 "REGG0_DOM_$1,Assign domain for CKGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x80 0x81 0x82 0x83 0x84 0x85 0x86 0x87 0x88 0x89 0x8A 0x8B 0x8C 0x8D 0x8E 0x8F )(list 0x200 0x204 0x208 0x20C 0x210 0x214 0x218 0x21C 0x220 0x224 0x228 0x22C 0x230 0x234 0x238 0x23C ) group.long ($2)++0x3 line.long 0x0 "REGG0_DOM_$1,Assign domain for CKGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x90 0x91 0x92 0x93 0x94 0x95 0x96 0x97 0x98 0x99 0x9A 0x9B 0x9C 0x9D 0x9E 0x9F )(list 0x240 0x244 0x248 0x24C 0x250 0x254 0x258 0x25C 0x260 0x264 0x268 0x26C 0x270 0x274 0x278 0x27C ) group.long ($2)++0x3 line.long 0x0 "REGG0_DOM_$1,Assign domain for CKGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xA0 0xA1 0xA2 0xA3 0xA4 0xA5 0xA6 0xA7 0xA8 0xA9 0xAA 0xAB 0xAC 0xAD 0xAE 0xAF )(list 0x280 0x284 0x288 0x28C 0x290 0x294 0x298 0x29C 0x2A0 0x2A4 0x2A8 0x2AC 0x2B0 0x2B4 0x2B8 0x2BC ) group.long ($2)++0x3 line.long 0x0 "REGG0_DOM_$1,Assign domain for CKGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xB0 0xB1 0xB2 0xB3 0xB4 0xB5 0xB6 0xB7 0xB8 0xB9 0xBA 0xBB 0xBC 0xBD 0xBE 0xBF )(list 0x2C0 0x2C4 0x2C8 0x2CC 0x2D0 0x2D4 0x2D8 0x2DC 0x2E0 0x2E4 0x2E8 0x2EC 0x2F0 0x2F4 0x2F8 0x2FC ) group.long ($2)++0x3 line.long 0x0 "REGG0_DOM_$1,Assign domain for CKGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xC0 0xC1 0xC2 0xC3 0xC4 0xC5 0xC6 0xC7 0xC8 0xC9 0xCA 0xCB 0xCC 0xCD 0xCE 0xCF )(list 0x300 0x304 0x308 0x30C 0x310 0x314 0x318 0x31C 0x320 0x324 0x328 0x32C 0x330 0x334 0x338 0x33C ) group.long ($2)++0x3 line.long 0x0 "REGG0_DOM_$1,Assign domain for CKGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xD0 0xD1 0xD2 0xD3 0xD4 0xD5 0xD6 0xD7 0xD8 0xD9 0xDA 0xDB 0xDC 0xDD 0xDE 0xDF )(list 0x340 0x344 0x348 0x34C 0x350 0x354 0x358 0x35C 0x360 0x364 0x368 0x36C 0x370 0x374 0x378 0x37C ) group.long ($2)++0x3 line.long 0x0 "REGG0_DOM_$1,Assign domain for CKGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xE0 0xE1 0xE2 0xE3 0xE4 0xE5 0xE6 0xE7 0xE8 0xE9 0xEA 0xEB 0xEC 0xED 0xEE 0xEF )(list 0x380 0x384 0x388 0x38C 0x390 0x394 0x398 0x39C 0x3A0 0x3A4 0x3A8 0x3AC 0x3B0 0x3B4 0x3B8 0x3BC ) group.long ($2)++0x3 line.long 0x0 "REGG0_DOM_$1,Assign domain for CKGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xF0 0xF1 0xF2 0xF3 0xF4 0xF5 0xF6 0xF7 0xF8 0xF9 0xFA 0xFB 0xFC 0xFD 0xFE 0xFF )(list 0x3C0 0x3C4 0x3C8 0x3CC 0x3D0 0x3D4 0x3D8 0x3DC 0x3E0 0x3E4 0x3E8 0x3EC 0x3F0 0x3F4 0x3F8 0x3FC ) group.long ($2)++0x3 line.long 0x0 "REGG0_DOM_$1,Assign domain for CKGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x4 0x8 0xC 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C ) group.long ($2+0x400)++0x3 line.long 0x0 "REGG1_DOM_$1,Assign domain for CKGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1A 0x1B 0x1C 0x1D 0x1E 0x1F )(list 0x40 0x44 0x48 0x4C 0x50 0x54 0x58 0x5C 0x60 0x64 0x68 0x6C 0x70 0x74 0x78 0x7C ) group.long ($2+0x400)++0x3 line.long 0x0 "REGG1_DOM_$1,Assign domain for CKGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x20 0x21 0x22 0x23 0x24 0x25 0x26 0x27 0x28 0x29 0x2A 0x2B 0x2C 0x2D 0x2E 0x2F )(list 0x80 0x84 0x88 0x8C 0x90 0x94 0x98 0x9C 0xA0 0xA4 0xA8 0xAC 0xB0 0xB4 0xB8 0xBC ) group.long ($2+0x400)++0x3 line.long 0x0 "REGG1_DOM_$1,Assign domain for CKGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x30 0x31 0x32 0x33 0x34 0x35 0x36 0x37 0x38 0x39 0x3A 0x3B 0x3C 0x3D 0x3E 0x3F )(list 0xC0 0xC4 0xC8 0xCC 0xD0 0xD4 0xD8 0xDC 0xE0 0xE4 0xE8 0xEC 0xF0 0xF4 0xF8 0xFC ) group.long ($2+0x400)++0x3 line.long 0x0 "REGG1_DOM_$1,Assign domain for CKGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x40 0x41 0x42 0x43 0x44 0x45 0x46 0x47 0x48 0x49 0x4A 0x4B 0x4C 0x4D 0x4E 0x4F )(list 0x100 0x104 0x108 0x10C 0x110 0x114 0x118 0x11C 0x120 0x124 0x128 0x12C 0x130 0x134 0x138 0x13C ) group.long ($2+0x400)++0x3 line.long 0x0 "REGG1_DOM_$1,Assign domain for CKGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x50 0x51 0x52 0x53 0x54 0x55 0x56 0x57 0x58 0x59 0x5A 0x5B 0x5C 0x5D 0x5E 0x5F )(list 0x140 0x144 0x148 0x14C 0x150 0x154 0x158 0x15C 0x160 0x164 0x168 0x16C 0x170 0x174 0x178 0x17C ) group.long ($2+0x400)++0x3 line.long 0x0 "REGG1_DOM_$1,Assign domain for CKGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x60 0x61 0x62 0x63 0x64 0x65 0x66 0x67 0x68 0x69 0x6A 0x6B 0x6C 0x6D 0x6E 0x6F )(list 0x180 0x184 0x188 0x18C 0x190 0x194 0x198 0x19C 0x1A0 0x1A4 0x1A8 0x1AC 0x1B0 0x1B4 0x1B8 0x1BC ) group.long ($2+0x400)++0x3 line.long 0x0 "REGG1_DOM_$1,Assign domain for CKGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x70 0x71 0x72 0x73 0x74 0x75 0x76 0x77 0x78 0x79 0x7A 0x7B 0x7C 0x7D 0x7E 0x7F )(list 0x1C0 0x1C4 0x1C8 0x1CC 0x1D0 0x1D4 0x1D8 0x1DC 0x1E0 0x1E4 0x1E8 0x1EC 0x1F0 0x1F4 0x1F8 0x1FC ) group.long ($2+0x400)++0x3 line.long 0x0 "REGG1_DOM_$1,Assign domain for CKGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x80 0x81 0x82 0x83 0x84 0x85 0x86 0x87 0x88 0x89 0x8A 0x8B 0x8C 0x8D 0x8E 0x8F )(list 0x200 0x204 0x208 0x20C 0x210 0x214 0x218 0x21C 0x220 0x224 0x228 0x22C 0x230 0x234 0x238 0x23C ) group.long ($2+0x400)++0x3 line.long 0x0 "REGG1_DOM_$1,Assign domain for CKGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x90 0x91 0x92 0x93 0x94 0x95 0x96 0x97 0x98 0x99 0x9A 0x9B 0x9C 0x9D 0x9E 0x9F )(list 0x240 0x244 0x248 0x24C 0x250 0x254 0x258 0x25C 0x260 0x264 0x268 0x26C 0x270 0x274 0x278 0x27C ) group.long ($2+0x400)++0x3 line.long 0x0 "REGG1_DOM_$1,Assign domain for CKGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xA0 0xA1 0xA2 0xA3 0xA4 0xA5 0xA6 0xA7 0xA8 0xA9 0xAA 0xAB 0xAC 0xAD 0xAE 0xAF )(list 0x280 0x284 0x288 0x28C 0x290 0x294 0x298 0x29C 0x2A0 0x2A4 0x2A8 0x2AC 0x2B0 0x2B4 0x2B8 0x2BC ) group.long ($2+0x400)++0x3 line.long 0x0 "REGG1_DOM_$1,Assign domain for CKGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xB0 0xB1 0xB2 0xB3 0xB4 0xB5 0xB6 0xB7 0xB8 0xB9 0xBA 0xBB 0xBC 0xBD 0xBE 0xBF )(list 0x2C0 0x2C4 0x2C8 0x2CC 0x2D0 0x2D4 0x2D8 0x2DC 0x2E0 0x2E4 0x2E8 0x2EC 0x2F0 0x2F4 0x2F8 0x2FC ) group.long ($2+0x400)++0x3 line.long 0x0 "REGG1_DOM_$1,Assign domain for CKGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xC0 0xC1 0xC2 0xC3 0xC4 0xC5 0xC6 0xC7 0xC8 0xC9 0xCA 0xCB 0xCC 0xCD 0xCE 0xCF )(list 0x300 0x304 0x308 0x30C 0x310 0x314 0x318 0x31C 0x320 0x324 0x328 0x32C 0x330 0x334 0x338 0x33C ) group.long ($2+0x400)++0x3 line.long 0x0 "REGG1_DOM_$1,Assign domain for CKGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xD0 0xD1 0xD2 0xD3 0xD4 0xD5 0xD6 0xD7 0xD8 0xD9 0xDA 0xDB 0xDC 0xDD 0xDE 0xDF )(list 0x340 0x344 0x348 0x34C 0x350 0x354 0x358 0x35C 0x360 0x364 0x368 0x36C 0x370 0x374 0x378 0x37C ) group.long ($2+0x400)++0x3 line.long 0x0 "REGG1_DOM_$1,Assign domain for CKGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xE0 0xE1 0xE2 0xE3 0xE4 0xE5 0xE6 0xE7 0xE8 0xE9 0xEA 0xEB 0xEC 0xED 0xEE 0xEF )(list 0x380 0x384 0x388 0x38C 0x390 0x394 0x398 0x39C 0x3A0 0x3A4 0x3A8 0x3AC 0x3B0 0x3B4 0x3B8 0x3BC ) group.long ($2+0x400)++0x3 line.long 0x0 "REGG1_DOM_$1,Assign domain for CKGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xF0 0xF1 0xF2 0xF3 0xF4 0xF5 0xF6 0xF7 0xF8 0xF9 0xFA 0xFB 0xFC 0xFD 0xFE 0xFF )(list 0x3C0 0x3C4 0x3C8 0x3CC 0x3D0 0x3D4 0x3D8 0x3DC 0x3E0 0x3E4 0x3E8 0x3EC 0x3F0 0x3F4 0x3F8 0x3FC ) group.long ($2+0x400)++0x3 line.long 0x0 "REGG1_DOM_$1,Assign domain for CKGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x4 0x8 0xC 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C ) group.long ($2+0x800)++0x3 line.long 0x0 "REGG2_DOM_$1,Assign domain for SCR registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1A 0x1B 0x1C 0x1D 0x1E 0x1F )(list 0x40 0x44 0x48 0x4C 0x50 0x54 0x58 0x5C 0x60 0x64 0x68 0x6C 0x70 0x74 0x78 0x7C ) group.long ($2+0x800)++0x3 line.long 0x0 "REGG2_DOM_$1,Assign domain for SCR registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x20 0x21 0x22 0x23 0x24 0x25 0x26 0x27 0x28 0x29 0x2A 0x2B 0x2C 0x2D 0x2E 0x2F )(list 0x80 0x84 0x88 0x8C 0x90 0x94 0x98 0x9C 0xA0 0xA4 0xA8 0xAC 0xB0 0xB4 0xB8 0xBC ) group.long ($2+0x800)++0x3 line.long 0x0 "REGG2_DOM_$1,Assign domain for SCR registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x30 0x31 0x32 0x33 0x34 0x35 0x36 0x37 0x38 0x39 0x3A 0x3B 0x3C 0x3D 0x3E 0x3F )(list 0xC0 0xC4 0xC8 0xCC 0xD0 0xD4 0xD8 0xDC 0xE0 0xE4 0xE8 0xEC 0xF0 0xF4 0xF8 0xFC ) group.long ($2+0x800)++0x3 line.long 0x0 "REGG2_DOM_$1,Assign domain for SCR registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x40 0x41 0x42 0x43 0x44 0x45 0x46 0x47 0x48 0x49 0x4A 0x4B 0x4C 0x4D 0x4E 0x4F )(list 0x100 0x104 0x108 0x10C 0x110 0x114 0x118 0x11C 0x120 0x124 0x128 0x12C 0x130 0x134 0x138 0x13C ) group.long ($2+0x800)++0x3 line.long 0x0 "REGG2_DOM_$1,Assign domain for SCR registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x50 0x51 0x52 0x53 0x54 0x55 0x56 0x57 0x58 0x59 0x5A 0x5B 0x5C 0x5D 0x5E 0x5F )(list 0x140 0x144 0x148 0x14C 0x150 0x154 0x158 0x15C 0x160 0x164 0x168 0x16C 0x170 0x174 0x178 0x17C ) group.long ($2+0x800)++0x3 line.long 0x0 "REGG2_DOM_$1,Assign domain for SCR registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x60 0x61 0x62 0x63 0x64 0x65 0x66 0x67 0x68 0x69 0x6A 0x6B 0x6C 0x6D 0x6E 0x6F )(list 0x180 0x184 0x188 0x18C 0x190 0x194 0x198 0x19C 0x1A0 0x1A4 0x1A8 0x1AC 0x1B0 0x1B4 0x1B8 0x1BC ) group.long ($2+0x800)++0x3 line.long 0x0 "REGG2_DOM_$1,Assign domain for SCR registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x70 0x71 0x72 0x73 0x74 0x75 0x76 0x77 0x78 0x79 0x7A 0x7B 0x7C 0x7D 0x7E 0x7F )(list 0x1C0 0x1C4 0x1C8 0x1CC 0x1D0 0x1D4 0x1D8 0x1DC 0x1E0 0x1E4 0x1E8 0x1EC 0x1F0 0x1F4 0x1F8 0x1FC ) group.long ($2+0x800)++0x3 line.long 0x0 "REGG2_DOM_$1,Assign domain for SCR registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x80 0x81 0x82 0x83 0x84 0x85 0x86 0x87 0x88 0x89 0x8A 0x8B 0x8C 0x8D 0x8E 0x8F )(list 0x200 0x204 0x208 0x20C 0x210 0x214 0x218 0x21C 0x220 0x224 0x228 0x22C 0x230 0x234 0x238 0x23C ) group.long ($2+0x800)++0x3 line.long 0x0 "REGG2_DOM_$1,Assign domain for SCR registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x90 0x91 0x92 0x93 0x94 0x95 0x96 0x97 0x98 0x99 0x9A 0x9B 0x9C 0x9D 0x9E 0x9F )(list 0x240 0x244 0x248 0x24C 0x250 0x254 0x258 0x25C 0x260 0x264 0x268 0x26C 0x270 0x274 0x278 0x27C ) group.long ($2+0x800)++0x3 line.long 0x0 "REGG2_DOM_$1,Assign domain for SCR registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xA0 0xA1 0xA2 0xA3 0xA4 0xA5 0xA6 0xA7 0xA8 0xA9 0xAA 0xAB 0xAC 0xAD 0xAE 0xAF )(list 0x280 0x284 0x288 0x28C 0x290 0x294 0x298 0x29C 0x2A0 0x2A4 0x2A8 0x2AC 0x2B0 0x2B4 0x2B8 0x2BC ) group.long ($2+0x800)++0x3 line.long 0x0 "REGG2_DOM_$1,Assign domain for SCR registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xB0 0xB1 0xB2 0xB3 0xB4 0xB5 0xB6 0xB7 0xB8 0xB9 0xBA 0xBB 0xBC 0xBD 0xBE 0xBF )(list 0x2C0 0x2C4 0x2C8 0x2CC 0x2D0 0x2D4 0x2D8 0x2DC 0x2E0 0x2E4 0x2E8 0x2EC 0x2F0 0x2F4 0x2F8 0x2FC ) group.long ($2+0x800)++0x3 line.long 0x0 "REGG2_DOM_$1,Assign domain for SCR registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xC0 0xC1 0xC2 0xC3 0xC4 0xC5 0xC6 0xC7 0xC8 0xC9 0xCA 0xCB 0xCC 0xCD 0xCE 0xCF )(list 0x300 0x304 0x308 0x30C 0x310 0x314 0x318 0x31C 0x320 0x324 0x328 0x32C 0x330 0x334 0x338 0x33C ) group.long ($2+0x800)++0x3 line.long 0x0 "REGG2_DOM_$1,Assign domain for SCR registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xD0 0xD1 0xD2 0xD3 0xD4 0xD5 0xD6 0xD7 0xD8 0xD9 0xDA 0xDB 0xDC 0xDD 0xDE 0xDF )(list 0x340 0x344 0x348 0x34C 0x350 0x354 0x358 0x35C 0x360 0x364 0x368 0x36C 0x370 0x374 0x378 0x37C ) group.long ($2+0x800)++0x3 line.long 0x0 "REGG2_DOM_$1,Assign domain for SCR registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xE0 0xE1 0xE2 0xE3 0xE4 0xE5 0xE6 0xE7 0xE8 0xE9 0xEA 0xEB 0xEC 0xED 0xEE 0xEF )(list 0x380 0x384 0x388 0x38C 0x390 0x394 0x398 0x39C 0x3A0 0x3A4 0x3A8 0x3AC 0x3B0 0x3B4 0x3B8 0x3BC ) group.long ($2+0x800)++0x3 line.long 0x0 "REGG2_DOM_$1,Assign domain for SCR registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xF0 0xF1 0xF2 0xF3 0xF4 0xF5 0xF6 0xF7 0xF8 0xF9 0xFA 0xFB 0xFC 0xFD 0xFE 0xFF )(list 0x3C0 0x3C4 0x3C8 0x3CC 0x3D0 0x3D4 0x3D8 0x3DC 0x3E0 0x3E4 0x3E8 0x3EC 0x3F0 0x3F4 0x3F8 0x3FC ) group.long ($2+0x800)++0x3 line.long 0x0 "REGG2_DOM_$1,Assign domain for SCR registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x4 0x8 0xC 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C ) group.long ($2+0xC00)++0x3 line.long 0x0 "REGG3_DOM_$1,Assign domain for SCR registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1A 0x1B 0x1C 0x1D 0x1E 0x1F )(list 0x40 0x44 0x48 0x4C 0x50 0x54 0x58 0x5C 0x60 0x64 0x68 0x6C 0x70 0x74 0x78 0x7C ) group.long ($2+0xC00)++0x3 line.long 0x0 "REGG3_DOM_$1,Assign domain for SCR registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x20 0x21 0x22 0x23 0x24 0x25 0x26 0x27 0x28 0x29 0x2A 0x2B 0x2C 0x2D 0x2E 0x2F )(list 0x80 0x84 0x88 0x8C 0x90 0x94 0x98 0x9C 0xA0 0xA4 0xA8 0xAC 0xB0 0xB4 0xB8 0xBC ) group.long ($2+0xC00)++0x3 line.long 0x0 "REGG3_DOM_$1,Assign domain for SCR registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x30 0x31 0x32 0x33 0x34 0x35 0x36 0x37 0x38 0x39 0x3A 0x3B 0x3C 0x3D 0x3E 0x3F )(list 0xC0 0xC4 0xC8 0xCC 0xD0 0xD4 0xD8 0xDC 0xE0 0xE4 0xE8 0xEC 0xF0 0xF4 0xF8 0xFC ) group.long ($2+0xC00)++0x3 line.long 0x0 "REGG3_DOM_$1,Assign domain for SCR registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x40 0x41 0x42 0x43 0x44 0x45 0x46 0x47 0x48 0x49 0x4A 0x4B 0x4C 0x4D 0x4E 0x4F )(list 0x100 0x104 0x108 0x10C 0x110 0x114 0x118 0x11C 0x120 0x124 0x128 0x12C 0x130 0x134 0x138 0x13C ) group.long ($2+0xC00)++0x3 line.long 0x0 "REGG3_DOM_$1,Assign domain for SCR registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x50 0x51 0x52 0x53 0x54 0x55 0x56 0x57 0x58 0x59 0x5A 0x5B 0x5C 0x5D 0x5E 0x5F )(list 0x140 0x144 0x148 0x14C 0x150 0x154 0x158 0x15C 0x160 0x164 0x168 0x16C 0x170 0x174 0x178 0x17C ) group.long ($2+0xC00)++0x3 line.long 0x0 "REGG3_DOM_$1,Assign domain for SCR registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x60 0x61 0x62 0x63 0x64 0x65 0x66 0x67 0x68 0x69 0x6A 0x6B 0x6C 0x6D 0x6E 0x6F )(list 0x180 0x184 0x188 0x18C 0x190 0x194 0x198 0x19C 0x1A0 0x1A4 0x1A8 0x1AC 0x1B0 0x1B4 0x1B8 0x1BC ) group.long ($2+0xC00)++0x3 line.long 0x0 "REGG3_DOM_$1,Assign domain for SCR registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x70 0x71 0x72 0x73 0x74 0x75 0x76 0x77 0x78 0x79 0x7A 0x7B 0x7C 0x7D 0x7E 0x7F )(list 0x1C0 0x1C4 0x1C8 0x1CC 0x1D0 0x1D4 0x1D8 0x1DC 0x1E0 0x1E4 0x1E8 0x1EC 0x1F0 0x1F4 0x1F8 0x1FC ) group.long ($2+0xC00)++0x3 line.long 0x0 "REGG3_DOM_$1,Assign domain for SCR registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x80 0x81 0x82 0x83 0x84 0x85 0x86 0x87 0x88 0x89 0x8A 0x8B 0x8C 0x8D 0x8E 0x8F )(list 0x200 0x204 0x208 0x20C 0x210 0x214 0x218 0x21C 0x220 0x224 0x228 0x22C 0x230 0x234 0x238 0x23C ) group.long ($2+0xC00)++0x3 line.long 0x0 "REGG3_DOM_$1,Assign domain for SCR registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x90 0x91 0x92 0x93 0x94 0x95 0x96 0x97 0x98 0x99 0x9A 0x9B 0x9C 0x9D 0x9E 0x9F )(list 0x240 0x244 0x248 0x24C 0x250 0x254 0x258 0x25C 0x260 0x264 0x268 0x26C 0x270 0x274 0x278 0x27C ) group.long ($2+0xC00)++0x3 line.long 0x0 "REGG3_DOM_$1,Assign domain for SCR registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xA0 0xA1 0xA2 0xA3 0xA4 0xA5 0xA6 0xA7 0xA8 0xA9 0xAA 0xAB 0xAC 0xAD 0xAE 0xAF )(list 0x280 0x284 0x288 0x28C 0x290 0x294 0x298 0x29C 0x2A0 0x2A4 0x2A8 0x2AC 0x2B0 0x2B4 0x2B8 0x2BC ) group.long ($2+0xC00)++0x3 line.long 0x0 "REGG3_DOM_$1,Assign domain for SCR registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xB0 0xB1 0xB2 0xB3 0xB4 0xB5 0xB6 0xB7 0xB8 0xB9 0xBA 0xBB 0xBC 0xBD 0xBE 0xBF )(list 0x2C0 0x2C4 0x2C8 0x2CC 0x2D0 0x2D4 0x2D8 0x2DC 0x2E0 0x2E4 0x2E8 0x2EC 0x2F0 0x2F4 0x2F8 0x2FC ) group.long ($2+0xC00)++0x3 line.long 0x0 "REGG3_DOM_$1,Assign domain for SCR registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xC0 0xC1 0xC2 0xC3 0xC4 0xC5 0xC6 0xC7 0xC8 0xC9 0xCA 0xCB 0xCC 0xCD 0xCE 0xCF )(list 0x300 0x304 0x308 0x30C 0x310 0x314 0x318 0x31C 0x320 0x324 0x328 0x32C 0x330 0x334 0x338 0x33C ) group.long ($2+0xC00)++0x3 line.long 0x0 "REGG3_DOM_$1,Assign domain for SCR registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xD0 0xD1 0xD2 0xD3 0xD4 0xD5 0xD6 0xD7 0xD8 0xD9 0xDA 0xDB 0xDC 0xDD 0xDE 0xDF )(list 0x340 0x344 0x348 0x34C 0x350 0x354 0x358 0x35C 0x360 0x364 0x368 0x36C 0x370 0x374 0x378 0x37C ) group.long ($2+0xC00)++0x3 line.long 0x0 "REGG3_DOM_$1,Assign domain for SCR registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xE0 0xE1 0xE2 0xE3 0xE4 0xE5 0xE6 0xE7 0xE8 0xE9 0xEA 0xEB 0xEC 0xED 0xEE 0xEF )(list 0x380 0x384 0x388 0x38C 0x390 0x394 0x398 0x39C 0x3A0 0x3A4 0x3A8 0x3AC 0x3B0 0x3B4 0x3B8 0x3BC ) group.long ($2+0xC00)++0x3 line.long 0x0 "REGG3_DOM_$1,Assign domain for SCR registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xF0 0xF1 0xF2 0xF3 0xF4 0xF5 0xF6 0xF7 0xF8 0xF9 0xFA 0xFB 0xFC 0xFD 0xFE 0xFF )(list 0x3C0 0x3C4 0x3C8 0x3CC 0x3D0 0x3D4 0x3D8 0x3DC 0x3E0 0x3E4 0x3E8 0x3EC 0x3F0 0x3F4 0x3F8 0x3FC ) group.long ($2+0xC00)++0x3 line.long 0x0 "REGG3_DOM_$1,Assign domain for SCR registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x4 0x8 0xC 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C ) group.long ($2+0x1000)++0x3 line.long 0x0 "REGG4_DOM_$1,Assign domain for RSTGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1A 0x1B 0x1C 0x1D 0x1E 0x1F )(list 0x40 0x44 0x48 0x4C 0x50 0x54 0x58 0x5C 0x60 0x64 0x68 0x6C 0x70 0x74 0x78 0x7C ) group.long ($2+0x1000)++0x3 line.long 0x0 "REGG4_DOM_$1,Assign domain for RSTGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x20 0x21 0x22 0x23 0x24 0x25 0x26 0x27 0x28 0x29 0x2A 0x2B 0x2C 0x2D 0x2E 0x2F )(list 0x80 0x84 0x88 0x8C 0x90 0x94 0x98 0x9C 0xA0 0xA4 0xA8 0xAC 0xB0 0xB4 0xB8 0xBC ) group.long ($2+0x1000)++0x3 line.long 0x0 "REGG4_DOM_$1,Assign domain for RSTGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x30 0x31 0x32 0x33 0x34 0x35 0x36 0x37 0x38 0x39 0x3A 0x3B 0x3C 0x3D 0x3E 0x3F )(list 0xC0 0xC4 0xC8 0xCC 0xD0 0xD4 0xD8 0xDC 0xE0 0xE4 0xE8 0xEC 0xF0 0xF4 0xF8 0xFC ) group.long ($2+0x1000)++0x3 line.long 0x0 "REGG4_DOM_$1,Assign domain for RSTGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x40 0x41 0x42 0x43 0x44 0x45 0x46 0x47 0x48 0x49 0x4A 0x4B 0x4C 0x4D 0x4E 0x4F )(list 0x100 0x104 0x108 0x10C 0x110 0x114 0x118 0x11C 0x120 0x124 0x128 0x12C 0x130 0x134 0x138 0x13C ) group.long ($2+0x1000)++0x3 line.long 0x0 "REGG4_DOM_$1,Assign domain for RSTGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x50 0x51 0x52 0x53 0x54 0x55 0x56 0x57 0x58 0x59 0x5A 0x5B 0x5C 0x5D 0x5E 0x5F )(list 0x140 0x144 0x148 0x14C 0x150 0x154 0x158 0x15C 0x160 0x164 0x168 0x16C 0x170 0x174 0x178 0x17C ) group.long ($2+0x1000)++0x3 line.long 0x0 "REGG4_DOM_$1,Assign domain for RSTGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x60 0x61 0x62 0x63 0x64 0x65 0x66 0x67 0x68 0x69 0x6A 0x6B 0x6C 0x6D 0x6E 0x6F )(list 0x180 0x184 0x188 0x18C 0x190 0x194 0x198 0x19C 0x1A0 0x1A4 0x1A8 0x1AC 0x1B0 0x1B4 0x1B8 0x1BC ) group.long ($2+0x1000)++0x3 line.long 0x0 "REGG4_DOM_$1,Assign domain for RSTGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x70 0x71 0x72 0x73 0x74 0x75 0x76 0x77 0x78 0x79 0x7A 0x7B 0x7C 0x7D 0x7E 0x7F )(list 0x1C0 0x1C4 0x1C8 0x1CC 0x1D0 0x1D4 0x1D8 0x1DC 0x1E0 0x1E4 0x1E8 0x1EC 0x1F0 0x1F4 0x1F8 0x1FC ) group.long ($2+0x1000)++0x3 line.long 0x0 "REGG4_DOM_$1,Assign domain for RSTGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x80 0x81 0x82 0x83 0x84 0x85 0x86 0x87 0x88 0x89 0x8A 0x8B 0x8C 0x8D 0x8E 0x8F )(list 0x200 0x204 0x208 0x20C 0x210 0x214 0x218 0x21C 0x220 0x224 0x228 0x22C 0x230 0x234 0x238 0x23C ) group.long ($2+0x1000)++0x3 line.long 0x0 "REGG4_DOM_$1,Assign domain for RSTGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x90 0x91 0x92 0x93 0x94 0x95 0x96 0x97 0x98 0x99 0x9A 0x9B 0x9C 0x9D 0x9E 0x9F )(list 0x240 0x244 0x248 0x24C 0x250 0x254 0x258 0x25C 0x260 0x264 0x268 0x26C 0x270 0x274 0x278 0x27C ) group.long ($2+0x1000)++0x3 line.long 0x0 "REGG4_DOM_$1,Assign domain for RSTGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xA0 0xA1 0xA2 0xA3 0xA4 0xA5 0xA6 0xA7 0xA8 0xA9 0xAA 0xAB 0xAC 0xAD 0xAE 0xAF )(list 0x280 0x284 0x288 0x28C 0x290 0x294 0x298 0x29C 0x2A0 0x2A4 0x2A8 0x2AC 0x2B0 0x2B4 0x2B8 0x2BC ) group.long ($2+0x1000)++0x3 line.long 0x0 "REGG4_DOM_$1,Assign domain for RSTGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xB0 0xB1 0xB2 0xB3 0xB4 0xB5 0xB6 0xB7 0xB8 0xB9 0xBA 0xBB 0xBC 0xBD 0xBE 0xBF )(list 0x2C0 0x2C4 0x2C8 0x2CC 0x2D0 0x2D4 0x2D8 0x2DC 0x2E0 0x2E4 0x2E8 0x2EC 0x2F0 0x2F4 0x2F8 0x2FC ) group.long ($2+0x1000)++0x3 line.long 0x0 "REGG4_DOM_$1,Assign domain for RSTGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xC0 0xC1 0xC2 0xC3 0xC4 0xC5 0xC6 0xC7 0xC8 0xC9 0xCA 0xCB 0xCC 0xCD 0xCE 0xCF )(list 0x300 0x304 0x308 0x30C 0x310 0x314 0x318 0x31C 0x320 0x324 0x328 0x32C 0x330 0x334 0x338 0x33C ) group.long ($2+0x1000)++0x3 line.long 0x0 "REGG4_DOM_$1,Assign domain for RSTGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xD0 0xD1 0xD2 0xD3 0xD4 0xD5 0xD6 0xD7 0xD8 0xD9 0xDA 0xDB 0xDC 0xDD 0xDE 0xDF )(list 0x340 0x344 0x348 0x34C 0x350 0x354 0x358 0x35C 0x360 0x364 0x368 0x36C 0x370 0x374 0x378 0x37C ) group.long ($2+0x1000)++0x3 line.long 0x0 "REGG4_DOM_$1,Assign domain for RSTGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xE0 0xE1 0xE2 0xE3 0xE4 0xE5 0xE6 0xE7 0xE8 0xE9 0xEA 0xEB 0xEC 0xED 0xEE 0xEF )(list 0x380 0x384 0x388 0x38C 0x390 0x394 0x398 0x39C 0x3A0 0x3A4 0x3A8 0x3AC 0x3B0 0x3B4 0x3B8 0x3BC ) group.long ($2+0x1000)++0x3 line.long 0x0 "REGG4_DOM_$1,Assign domain for RSTGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xF0 0xF1 0xF2 0xF3 0xF4 0xF5 0xF6 0xF7 0xF8 0xF9 0xFA 0xFB 0xFC 0xFD 0xFE 0xFF )(list 0x3C0 0x3C4 0x3C8 0x3CC 0x3D0 0x3D4 0x3D8 0x3DC 0x3E0 0x3E4 0x3E8 0x3EC 0x3F0 0x3F4 0x3F8 0x3FC ) group.long ($2+0x1000)++0x3 line.long 0x0 "REGG4_DOM_$1,Assign domain for RSTGEN registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x4 0x8 0xC 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C ) group.long ($2+0x1400)++0x3 line.long 0x0 "REGG5_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1A 0x1B 0x1C 0x1D 0x1E 0x1F )(list 0x40 0x44 0x48 0x4C 0x50 0x54 0x58 0x5C 0x60 0x64 0x68 0x6C 0x70 0x74 0x78 0x7C ) group.long ($2+0x1400)++0x3 line.long 0x0 "REGG5_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x20 0x21 0x22 0x23 0x24 0x25 0x26 0x27 0x28 0x29 0x2A 0x2B 0x2C 0x2D 0x2E 0x2F )(list 0x80 0x84 0x88 0x8C 0x90 0x94 0x98 0x9C 0xA0 0xA4 0xA8 0xAC 0xB0 0xB4 0xB8 0xBC ) group.long ($2+0x1400)++0x3 line.long 0x0 "REGG5_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x30 0x31 0x32 0x33 0x34 0x35 0x36 0x37 0x38 0x39 0x3A 0x3B 0x3C 0x3D 0x3E 0x3F )(list 0xC0 0xC4 0xC8 0xCC 0xD0 0xD4 0xD8 0xDC 0xE0 0xE4 0xE8 0xEC 0xF0 0xF4 0xF8 0xFC ) group.long ($2+0x1400)++0x3 line.long 0x0 "REGG5_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x40 0x41 0x42 0x43 0x44 0x45 0x46 0x47 0x48 0x49 0x4A 0x4B 0x4C 0x4D 0x4E 0x4F )(list 0x100 0x104 0x108 0x10C 0x110 0x114 0x118 0x11C 0x120 0x124 0x128 0x12C 0x130 0x134 0x138 0x13C ) group.long ($2+0x1400)++0x3 line.long 0x0 "REGG5_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x50 0x51 0x52 0x53 0x54 0x55 0x56 0x57 0x58 0x59 0x5A 0x5B 0x5C 0x5D 0x5E 0x5F )(list 0x140 0x144 0x148 0x14C 0x150 0x154 0x158 0x15C 0x160 0x164 0x168 0x16C 0x170 0x174 0x178 0x17C ) group.long ($2+0x1400)++0x3 line.long 0x0 "REGG5_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x60 0x61 0x62 0x63 0x64 0x65 0x66 0x67 0x68 0x69 0x6A 0x6B 0x6C 0x6D 0x6E 0x6F )(list 0x180 0x184 0x188 0x18C 0x190 0x194 0x198 0x19C 0x1A0 0x1A4 0x1A8 0x1AC 0x1B0 0x1B4 0x1B8 0x1BC ) group.long ($2+0x1400)++0x3 line.long 0x0 "REGG5_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x70 0x71 0x72 0x73 0x74 0x75 0x76 0x77 0x78 0x79 0x7A 0x7B 0x7C 0x7D 0x7E 0x7F )(list 0x1C0 0x1C4 0x1C8 0x1CC 0x1D0 0x1D4 0x1D8 0x1DC 0x1E0 0x1E4 0x1E8 0x1EC 0x1F0 0x1F4 0x1F8 0x1FC ) group.long ($2+0x1400)++0x3 line.long 0x0 "REGG5_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x80 0x81 0x82 0x83 0x84 0x85 0x86 0x87 0x88 0x89 0x8A 0x8B 0x8C 0x8D 0x8E 0x8F )(list 0x200 0x204 0x208 0x20C 0x210 0x214 0x218 0x21C 0x220 0x224 0x228 0x22C 0x230 0x234 0x238 0x23C ) group.long ($2+0x1400)++0x3 line.long 0x0 "REGG5_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x90 0x91 0x92 0x93 0x94 0x95 0x96 0x97 0x98 0x99 0x9A 0x9B 0x9C 0x9D 0x9E 0x9F )(list 0x240 0x244 0x248 0x24C 0x250 0x254 0x258 0x25C 0x260 0x264 0x268 0x26C 0x270 0x274 0x278 0x27C ) group.long ($2+0x1400)++0x3 line.long 0x0 "REGG5_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xA0 0xA1 0xA2 0xA3 0xA4 0xA5 0xA6 0xA7 0xA8 0xA9 0xAA 0xAB 0xAC 0xAD 0xAE 0xAF )(list 0x280 0x284 0x288 0x28C 0x290 0x294 0x298 0x29C 0x2A0 0x2A4 0x2A8 0x2AC 0x2B0 0x2B4 0x2B8 0x2BC ) group.long ($2+0x1400)++0x3 line.long 0x0 "REGG5_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xB0 0xB1 0xB2 0xB3 0xB4 0xB5 0xB6 0xB7 0xB8 0xB9 0xBA 0xBB 0xBC 0xBD 0xBE 0xBF )(list 0x2C0 0x2C4 0x2C8 0x2CC 0x2D0 0x2D4 0x2D8 0x2DC 0x2E0 0x2E4 0x2E8 0x2EC 0x2F0 0x2F4 0x2F8 0x2FC ) group.long ($2+0x1400)++0x3 line.long 0x0 "REGG5_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xC0 0xC1 0xC2 0xC3 0xC4 0xC5 0xC6 0xC7 0xC8 0xC9 0xCA 0xCB 0xCC 0xCD 0xCE 0xCF )(list 0x300 0x304 0x308 0x30C 0x310 0x314 0x318 0x31C 0x320 0x324 0x328 0x32C 0x330 0x334 0x338 0x33C ) group.long ($2+0x1400)++0x3 line.long 0x0 "REGG5_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xD0 0xD1 0xD2 0xD3 0xD4 0xD5 0xD6 0xD7 0xD8 0xD9 0xDA 0xDB 0xDC 0xDD 0xDE 0xDF )(list 0x340 0x344 0x348 0x34C 0x350 0x354 0x358 0x35C 0x360 0x364 0x368 0x36C 0x370 0x374 0x378 0x37C ) group.long ($2+0x1400)++0x3 line.long 0x0 "REGG5_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xE0 0xE1 0xE2 0xE3 0xE4 0xE5 0xE6 0xE7 0xE8 0xE9 0xEA 0xEB 0xEC 0xED 0xEE 0xEF )(list 0x380 0x384 0x388 0x38C 0x390 0x394 0x398 0x39C 0x3A0 0x3A4 0x3A8 0x3AC 0x3B0 0x3B4 0x3B8 0x3BC ) group.long ($2+0x1400)++0x3 line.long 0x0 "REGG5_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xF0 0xF1 0xF2 0xF3 0xF4 0xF5 0xF6 0xF7 0xF8 0xF9 0xFA 0xFB 0xFC 0xFD 0xFE 0xFF )(list 0x3C0 0x3C4 0x3C8 0x3CC 0x3D0 0x3D4 0x3D8 0x3DC 0x3E0 0x3E4 0x3E8 0x3EC 0x3F0 0x3F4 0x3F8 0x3FC ) group.long ($2+0x1400)++0x3 line.long 0x0 "REGG5_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x4 0x8 0xC 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C ) group.long ($2+0x1800)++0x3 line.long 0x0 "REGG6_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1A 0x1B 0x1C 0x1D 0x1E 0x1F )(list 0x40 0x44 0x48 0x4C 0x50 0x54 0x58 0x5C 0x60 0x64 0x68 0x6C 0x70 0x74 0x78 0x7C ) group.long ($2+0x1800)++0x3 line.long 0x0 "REGG6_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x20 0x21 0x22 0x23 0x24 0x25 0x26 0x27 0x28 0x29 0x2A 0x2B 0x2C 0x2D 0x2E 0x2F )(list 0x80 0x84 0x88 0x8C 0x90 0x94 0x98 0x9C 0xA0 0xA4 0xA8 0xAC 0xB0 0xB4 0xB8 0xBC ) group.long ($2+0x1800)++0x3 line.long 0x0 "REGG6_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x30 0x31 0x32 0x33 0x34 0x35 0x36 0x37 0x38 0x39 0x3A 0x3B 0x3C 0x3D 0x3E 0x3F )(list 0xC0 0xC4 0xC8 0xCC 0xD0 0xD4 0xD8 0xDC 0xE0 0xE4 0xE8 0xEC 0xF0 0xF4 0xF8 0xFC ) group.long ($2+0x1800)++0x3 line.long 0x0 "REGG6_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x40 0x41 0x42 0x43 0x44 0x45 0x46 0x47 0x48 0x49 0x4A 0x4B 0x4C 0x4D 0x4E 0x4F )(list 0x100 0x104 0x108 0x10C 0x110 0x114 0x118 0x11C 0x120 0x124 0x128 0x12C 0x130 0x134 0x138 0x13C ) group.long ($2+0x1800)++0x3 line.long 0x0 "REGG6_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x50 0x51 0x52 0x53 0x54 0x55 0x56 0x57 0x58 0x59 0x5A 0x5B 0x5C 0x5D 0x5E 0x5F )(list 0x140 0x144 0x148 0x14C 0x150 0x154 0x158 0x15C 0x160 0x164 0x168 0x16C 0x170 0x174 0x178 0x17C ) group.long ($2+0x1800)++0x3 line.long 0x0 "REGG6_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x60 0x61 0x62 0x63 0x64 0x65 0x66 0x67 0x68 0x69 0x6A 0x6B 0x6C 0x6D 0x6E 0x6F )(list 0x180 0x184 0x188 0x18C 0x190 0x194 0x198 0x19C 0x1A0 0x1A4 0x1A8 0x1AC 0x1B0 0x1B4 0x1B8 0x1BC ) group.long ($2+0x1800)++0x3 line.long 0x0 "REGG6_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x70 0x71 0x72 0x73 0x74 0x75 0x76 0x77 0x78 0x79 0x7A 0x7B 0x7C 0x7D 0x7E 0x7F )(list 0x1C0 0x1C4 0x1C8 0x1CC 0x1D0 0x1D4 0x1D8 0x1DC 0x1E0 0x1E4 0x1E8 0x1EC 0x1F0 0x1F4 0x1F8 0x1FC ) group.long ($2+0x1800)++0x3 line.long 0x0 "REGG6_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x80 0x81 0x82 0x83 0x84 0x85 0x86 0x87 0x88 0x89 0x8A 0x8B 0x8C 0x8D 0x8E 0x8F )(list 0x200 0x204 0x208 0x20C 0x210 0x214 0x218 0x21C 0x220 0x224 0x228 0x22C 0x230 0x234 0x238 0x23C ) group.long ($2+0x1800)++0x3 line.long 0x0 "REGG6_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x90 0x91 0x92 0x93 0x94 0x95 0x96 0x97 0x98 0x99 0x9A 0x9B 0x9C 0x9D 0x9E 0x9F )(list 0x240 0x244 0x248 0x24C 0x250 0x254 0x258 0x25C 0x260 0x264 0x268 0x26C 0x270 0x274 0x278 0x27C ) group.long ($2+0x1800)++0x3 line.long 0x0 "REGG6_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xA0 0xA1 0xA2 0xA3 0xA4 0xA5 0xA6 0xA7 0xA8 0xA9 0xAA 0xAB 0xAC 0xAD 0xAE 0xAF )(list 0x280 0x284 0x288 0x28C 0x290 0x294 0x298 0x29C 0x2A0 0x2A4 0x2A8 0x2AC 0x2B0 0x2B4 0x2B8 0x2BC ) group.long ($2+0x1800)++0x3 line.long 0x0 "REGG6_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xB0 0xB1 0xB2 0xB3 0xB4 0xB5 0xB6 0xB7 0xB8 0xB9 0xBA 0xBB 0xBC 0xBD 0xBE 0xBF )(list 0x2C0 0x2C4 0x2C8 0x2CC 0x2D0 0x2D4 0x2D8 0x2DC 0x2E0 0x2E4 0x2E8 0x2EC 0x2F0 0x2F4 0x2F8 0x2FC ) group.long ($2+0x1800)++0x3 line.long 0x0 "REGG6_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xC0 0xC1 0xC2 0xC3 0xC4 0xC5 0xC6 0xC7 0xC8 0xC9 0xCA 0xCB 0xCC 0xCD 0xCE 0xCF )(list 0x300 0x304 0x308 0x30C 0x310 0x314 0x318 0x31C 0x320 0x324 0x328 0x32C 0x330 0x334 0x338 0x33C ) group.long ($2+0x1800)++0x3 line.long 0x0 "REGG6_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xD0 0xD1 0xD2 0xD3 0xD4 0xD5 0xD6 0xD7 0xD8 0xD9 0xDA 0xDB 0xDC 0xDD 0xDE 0xDF )(list 0x340 0x344 0x348 0x34C 0x350 0x354 0x358 0x35C 0x360 0x364 0x368 0x36C 0x370 0x374 0x378 0x37C ) group.long ($2+0x1800)++0x3 line.long 0x0 "REGG6_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xE0 0xE1 0xE2 0xE3 0xE4 0xE5 0xE6 0xE7 0xE8 0xE9 0xEA 0xEB 0xEC 0xED 0xEE 0xEF )(list 0x380 0x384 0x388 0x38C 0x390 0x394 0x398 0x39C 0x3A0 0x3A4 0x3A8 0x3AC 0x3B0 0x3B4 0x3B8 0x3BC ) group.long ($2+0x1800)++0x3 line.long 0x0 "REGG6_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xF0 0xF1 0xF2 0xF3 0xF4 0xF5 0xF6 0xF7 0xF8 0xF9 0xFA 0xFB 0xFC 0xFD 0xFE 0xFF )(list 0x3C0 0x3C4 0x3C8 0x3CC 0x3D0 0x3D4 0x3D8 0x3DC 0x3E0 0x3E4 0x3E8 0x3EC 0x3F0 0x3F4 0x3F8 0x3FC ) group.long ($2+0x1800)++0x3 line.long 0x0 "REGG6_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x4 0x8 0xC 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C ) group.long ($2+0x1C00)++0x3 line.long 0x0 "REGG7_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1A 0x1B 0x1C 0x1D 0x1E 0x1F )(list 0x40 0x44 0x48 0x4C 0x50 0x54 0x58 0x5C 0x60 0x64 0x68 0x6C 0x70 0x74 0x78 0x7C ) group.long ($2+0x1C00)++0x3 line.long 0x0 "REGG7_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x20 0x21 0x22 0x23 0x24 0x25 0x26 0x27 0x28 0x29 0x2A 0x2B 0x2C 0x2D 0x2E 0x2F )(list 0x80 0x84 0x88 0x8C 0x90 0x94 0x98 0x9C 0xA0 0xA4 0xA8 0xAC 0xB0 0xB4 0xB8 0xBC ) group.long ($2+0x1C00)++0x3 line.long 0x0 "REGG7_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x30 0x31 0x32 0x33 0x34 0x35 0x36 0x37 0x38 0x39 0x3A 0x3B 0x3C 0x3D 0x3E 0x3F )(list 0xC0 0xC4 0xC8 0xCC 0xD0 0xD4 0xD8 0xDC 0xE0 0xE4 0xE8 0xEC 0xF0 0xF4 0xF8 0xFC ) group.long ($2+0x1C00)++0x3 line.long 0x0 "REGG7_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x40 0x41 0x42 0x43 0x44 0x45 0x46 0x47 0x48 0x49 0x4A 0x4B 0x4C 0x4D 0x4E 0x4F )(list 0x100 0x104 0x108 0x10C 0x110 0x114 0x118 0x11C 0x120 0x124 0x128 0x12C 0x130 0x134 0x138 0x13C ) group.long ($2+0x1C00)++0x3 line.long 0x0 "REGG7_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x50 0x51 0x52 0x53 0x54 0x55 0x56 0x57 0x58 0x59 0x5A 0x5B 0x5C 0x5D 0x5E 0x5F )(list 0x140 0x144 0x148 0x14C 0x150 0x154 0x158 0x15C 0x160 0x164 0x168 0x16C 0x170 0x174 0x178 0x17C ) group.long ($2+0x1C00)++0x3 line.long 0x0 "REGG7_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x60 0x61 0x62 0x63 0x64 0x65 0x66 0x67 0x68 0x69 0x6A 0x6B 0x6C 0x6D 0x6E 0x6F )(list 0x180 0x184 0x188 0x18C 0x190 0x194 0x198 0x19C 0x1A0 0x1A4 0x1A8 0x1AC 0x1B0 0x1B4 0x1B8 0x1BC ) group.long ($2+0x1C00)++0x3 line.long 0x0 "REGG7_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x70 0x71 0x72 0x73 0x74 0x75 0x76 0x77 0x78 0x79 0x7A 0x7B 0x7C 0x7D 0x7E 0x7F )(list 0x1C0 0x1C4 0x1C8 0x1CC 0x1D0 0x1D4 0x1D8 0x1DC 0x1E0 0x1E4 0x1E8 0x1EC 0x1F0 0x1F4 0x1F8 0x1FC ) group.long ($2+0x1C00)++0x3 line.long 0x0 "REGG7_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x80 0x81 0x82 0x83 0x84 0x85 0x86 0x87 0x88 0x89 0x8A 0x8B 0x8C 0x8D 0x8E 0x8F )(list 0x200 0x204 0x208 0x20C 0x210 0x214 0x218 0x21C 0x220 0x224 0x228 0x22C 0x230 0x234 0x238 0x23C ) group.long ($2+0x1C00)++0x3 line.long 0x0 "REGG7_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0x90 0x91 0x92 0x93 0x94 0x95 0x96 0x97 0x98 0x99 0x9A 0x9B 0x9C 0x9D 0x9E 0x9F )(list 0x240 0x244 0x248 0x24C 0x250 0x254 0x258 0x25C 0x260 0x264 0x268 0x26C 0x270 0x274 0x278 0x27C ) group.long ($2+0x1C00)++0x3 line.long 0x0 "REGG7_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xA0 0xA1 0xA2 0xA3 0xA4 0xA5 0xA6 0xA7 0xA8 0xA9 0xAA 0xAB 0xAC 0xAD 0xAE 0xAF )(list 0x280 0x284 0x288 0x28C 0x290 0x294 0x298 0x29C 0x2A0 0x2A4 0x2A8 0x2AC 0x2B0 0x2B4 0x2B8 0x2BC ) group.long ($2+0x1C00)++0x3 line.long 0x0 "REGG7_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xB0 0xB1 0xB2 0xB3 0xB4 0xB5 0xB6 0xB7 0xB8 0xB9 0xBA 0xBB 0xBC 0xBD 0xBE 0xBF )(list 0x2C0 0x2C4 0x2C8 0x2CC 0x2D0 0x2D4 0x2D8 0x2DC 0x2E0 0x2E4 0x2E8 0x2EC 0x2F0 0x2F4 0x2F8 0x2FC ) group.long ($2+0x1C00)++0x3 line.long 0x0 "REGG7_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xC0 0xC1 0xC2 0xC3 0xC4 0xC5 0xC6 0xC7 0xC8 0xC9 0xCA 0xCB 0xCC 0xCD 0xCE 0xCF )(list 0x300 0x304 0x308 0x30C 0x310 0x314 0x318 0x31C 0x320 0x324 0x328 0x32C 0x330 0x334 0x338 0x33C ) group.long ($2+0x1C00)++0x3 line.long 0x0 "REGG7_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xD0 0xD1 0xD2 0xD3 0xD4 0xD5 0xD6 0xD7 0xD8 0xD9 0xDA 0xDB 0xDC 0xDD 0xDE 0xDF )(list 0x340 0x344 0x348 0x34C 0x350 0x354 0x358 0x35C 0x360 0x364 0x368 0x36C 0x370 0x374 0x378 0x37C ) group.long ($2+0x1C00)++0x3 line.long 0x0 "REGG7_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xE0 0xE1 0xE2 0xE3 0xE4 0xE5 0xE6 0xE7 0xE8 0xE9 0xEA 0xEB 0xEC 0xED 0xEE 0xEF )(list 0x380 0x384 0x388 0x38C 0x390 0x394 0x398 0x39C 0x3A0 0x3A4 0x3A8 0x3AC 0x3B0 0x3B4 0x3B8 0x3BC ) group.long ($2+0x1C00)++0x3 line.long 0x0 "REGG7_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end repeat 16. (list 0xF0 0xF1 0xF2 0xF3 0xF4 0xF5 0xF6 0xF7 0xF8 0xF9 0xFA 0xFB 0xFC 0xFD 0xFE 0xFF )(list 0x3C0 0x3C4 0x3C8 0x3CC 0x3D0 0x3D4 0x3D8 0x3DC 0x3E0 0x3E4 0x3E8 0x3EC 0x3F0 0x3F4 0x3F8 0x3FC ) group.long ($2+0x1C00)++0x3 line.long 0x0 "REGG7_DOM_$1,Assign domain for IOMUX_CTRL registers." bitfld.long 0x0 7. "PER_SEL_LOCK,Lock write for PER_SEL" "0,1" bitfld.long 0x0 5.--6. "PER_SEL,Select one of 4 permision setting for domain." "0,1,2,3" bitfld.long 0x0 4. "DID_LOCK,Lock write for DID and DOM_SET." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Domain ID for register" repeat.end group.long 0x2000++0x17 line.long 0x0 "GLB_CTL,This register provides global enable settings for permission control." bitfld.long 0x0 5. "DOM_CFG_LOCK,Lock write for DOM_CFG_MODE bit." "0,1" bitfld.long 0x0 4. "DOM_CFG_MODE,When enabled all the source setting can be configured by master from domain 0 if it is not locked. When disabled only resource manager can configure the permission of the resource." "0,1" bitfld.long 0x0 3. "PERCK_DIS_LOCK,Lock write for PERCK_DIS" "0,1" bitfld.long 0x0 2. "PERCK_DIS,All the permission check disable." "0,1" newline bitfld.long 0x0 1. "DOM_PRO_LOCK,Lock write for DOM_PRO_EN bit." "0,1" bitfld.long 0x0 0. "DOM_PRO_EN,When disabled no domain access permission check" "0,1" line.long 0x4 "RES_MGR,Resource manager register. This regster is used to assign resource manager for global resource access control" bitfld.long 0x4 17. "MID_LOCK,Lock write for MID_EN and MID_LOW and MID_HIG registers." "0,1" bitfld.long 0x4 16. "MID_EN,Master ID check enable" "0,1" bitfld.long 0x4 15. "PRI_PER_LOCK,Lock write for PRI_PER and PRI_PER_EN" "0,1" bitfld.long 0x4 13.--14. "PRI_PER,Resource manager privileged access permission. bit0 for privileged access bit1 for user access" "0,1,2,3" newline bitfld.long 0x4 12. "PRI_PER_EN,Resource manager privileged access permission enable." "0,1" bitfld.long 0x4 11. "SEC_PER_LOCK,Lock for SEC_PER and SEC_PER_LOCK" "0,1" bitfld.long 0x4 9.--10. "SEC_PER,Resource manager secure access permission. bit 0 for secure access bit 1 for non-secure access" "0,1,2,3" bitfld.long 0x4 8. "SEC_PER_EN,Resource manager secure permission enable" "0,1" bitfld.long 0x4 7. "DID_LOCK,Lock write for DID_EN and DID" "0,1" newline hexmask.long.byte 0x4 3.--6. 1. "DID,Resource manager domain ID" bitfld.long 0x4 2. "DID_EN,Resource manager Domain ID enable" "0,1" bitfld.long 0x4 1. "RES_MGR_EN_LOCK,Lock for RES_MGR_EN" "0,1" bitfld.long 0x4 0. "RES_MGR_EN,Resource manager enable. When the bit is disable there is no resource manager." "0,1" line.long 0x8 "RES_MGR_MA0,This register is used to assign master 0~31 as resource manager." hexmask.long 0x8 0.--31. 1. "MID,Assign master 0~31 for resource manager" line.long 0xC "RES_MGR_MA1,This register is used to assign master 32~63 as resource manager." hexmask.long 0xC 0.--31. 1. "MID,Indicate if master 32~63 is resource manager." line.long 0x10 "RES_MGR_MA2,This register is used to assign master 64~95 as resource manager." hexmask.long 0x10 0.--31. 1. "MID,Indicate if master 64~95 is resource manager." line.long 0x14 "RES_MGR_MA3,This register is used to assign master 96~127 as resource manager." hexmask.long 0x14 0.--31. 1. "MID,Indicate if master 96~127 is resource manager." repeat 8. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 )(list 0x0 0x14 0x28 0x3C 0x50 0x64 0x78 0x8C ) group.long ($2+0x2100)++0x3 line.long 0x0 "GRP_MGR_$1,Group Manager Register. This register is used to assign group manager for each domain" bitfld.long 0x0 17. "MID_LOCK,Lock write for MID_EN and MID_LOW and MID_HIG registers." "0,1" bitfld.long 0x0 16. "MID_EN,Master ID check enable" "0,1" bitfld.long 0x0 15. "PRI_PER_LOCK,Lock write for PRI_PER and PRI_PER_EN" "0,1" bitfld.long 0x0 13.--14. "PRI_PER,Group manager privileged access permission. bit0 for privileged access bit1 for user access" "0,1,2,3" newline bitfld.long 0x0 12. "PRI_PER_EN,Group manager privileged access permission enable." "0,1" bitfld.long 0x0 11. "SEC_PER_LOCK,Lock for SEC_PER and SEC_PER_LOCK" "0,1" bitfld.long 0x0 9.--10. "SEC_PER,Group manager secure access permission. bit 0 for secure access bit 1 for non-secure access" "0,1,2,3" bitfld.long 0x0 8. "SEC_PER_EN,Group manager secure permission enable" "0,1" bitfld.long 0x0 7. "DID_LOCK,Lock write for DID_EN and DID" "0,1" newline hexmask.long.byte 0x0 3.--6. 1. "DID,Group manager domain ID" bitfld.long 0x0 2. "DID_EN,Group manager Domain ID enable" "0,1" bitfld.long 0x0 1. "GRP_MGR_EN_LOCK,Lock write for GPR_MGR_EN" "0,1" bitfld.long 0x0 0. "GRP_MGR_EN,Group manager enable. When the bit is disable there is no resource manager." "0,1" repeat.end repeat 8. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 )(list 0x0 0x14 0x28 0x3C 0x50 0x64 0x78 0x8C ) group.long ($2+0x2104)++0x3 line.long 0x0 "GRP_MGR_MA0_$1,Assign master 0~31 for group manager 0" hexmask.long 0x0 0.--31. 1. "MID,Assign master 0~31 for resource manager" repeat.end repeat 8. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 )(list 0x0 0x14 0x28 0x3C 0x50 0x64 0x78 0x8C ) group.long ($2+0x2108)++0x3 line.long 0x0 "GRP_MGR_MA1_$1,Assign master 32~63 for group manager 0" hexmask.long 0x0 0.--31. 1. "MID,Indicate if master 32~63 is resource manager." repeat.end repeat 8. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 )(list 0x0 0x14 0x28 0x3C 0x50 0x64 0x78 0x8C ) group.long ($2+0x210C)++0x3 line.long 0x0 "GRP_MGR_MA2_$1,Assign master 64~95 for group manager 0" hexmask.long 0x0 0.--31. 1. "MID,Indicate if master 64~95 is resource manager." repeat.end repeat 8. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 )(list 0x0 0x14 0x28 0x3C 0x50 0x64 0x78 0x8C ) group.long ($2+0x2110)++0x3 line.long 0x0 "GRP_MGR_MA3_$1,Assign master 96~127 for group manager 0" hexmask.long 0x0 0.--31. 1. "MID,Indicate if master 96~127 is resource manager." repeat.end group.long 0x2200++0x3 line.long 0x0 "DOM_GID_0,Indicate which group domain 0 belong to" bitfld.long 0x0 3. "LOCK,Lock write for GID" "0,1" bitfld.long 0x0 0.--2. "GID,Group ID" "0,1,2,3,4,5,6,7" repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x18 0x30 0x48 0x60 0x78 0x90 0xA8 0xC0 0xD8 0xF0 0x108 0x120 0x138 0x150 0x168 ) group.long ($2+0x2204)++0x3 line.long 0x0 "DOM_OWN_$1,Assign owner for function domain 0." bitfld.long 0x0 17. "MID_LOCK,Lock write for MID_EN and MID_LOW and MID_HIG registers." "0,1" bitfld.long 0x0 16. "MID_EN,Master ID check enable" "0,1" bitfld.long 0x0 15. "PRI_PER_LOCK,Lock write for PRI_PER and PRI_PER_EN" "0,1" bitfld.long 0x0 13.--14. "PRI_PER,Group manager privileged access permission. bit0 for privileged access bit1 for user access" "0,1,2,3" newline bitfld.long 0x0 12. "PRI_PER_EN,Group manager privileged access permission enable." "0,1" bitfld.long 0x0 11. "SEC_PER_LOCK,Lock for SEC_PER and SEC_PER_LOCK" "0,1" bitfld.long 0x0 9.--10. "SEC_PER,Domain owner secure access permission. bit 0 for secure access bit 1 for non-secure access" "0,1,2,3" bitfld.long 0x0 8. "SEC_PER_EN,Domain owner secure permission enable" "0,1" newline bitfld.long 0x0 1. "DOM_OWN_EN_LOCK,Lock for DOM_OWN_EN" "0,1" bitfld.long 0x0 0. "DOM_OWN_EN,Domain owner enable. When the bit is disable there is no domain owner." "0,1" repeat.end repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x18 0x30 0x48 0x60 0x78 0x90 0xA8 0xC0 0xD8 0xF0 0x108 0x120 0x138 0x150 0x168 ) group.long ($2+0x2208)++0x3 line.long 0x0 "DOM_OWN_MA0_$1,Assign master 0~31 for domain owner 0" hexmask.long 0x0 0.--31. 1. "MID,Assign master 0~31 for resource manager" repeat.end repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x18 0x30 0x48 0x60 0x78 0x90 0xA8 0xC0 0xD8 0xF0 0x108 0x120 0x138 0x150 0x168 ) group.long ($2+0x220C)++0x3 line.long 0x0 "DOM_OWN_MA1_$1,Assign master 32~63 for domain owner 0" hexmask.long 0x0 0.--31. 1. "MID,Indicate if master 32~63 is resource manager." repeat.end repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x18 0x30 0x48 0x60 0x78 0x90 0xA8 0xC0 0xD8 0xF0 0x108 0x120 0x138 0x150 0x168 ) group.long ($2+0x2210)++0x3 line.long 0x0 "DOM_OWN_MA2_$1,Assign master 64~95 for domain owner 0" hexmask.long 0x0 0.--31. 1. "MID,Indicate if master 64~95 is resource manager." repeat.end repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x18 0x30 0x48 0x60 0x78 0x90 0xA8 0xC0 0xD8 0xF0 0x108 0x120 0x138 0x150 0x168 ) group.long ($2+0x2214)++0x3 line.long 0x0 "DOM_OWN_MA3_$1,Assign master 96~127 for domain owner 0" hexmask.long 0x0 0.--31. 1. "MID,Indicate if master 96~127 is resource manager." repeat.end group.long 0x2218++0x3 line.long 0x0 "DOM_GID_1,Indicate which group domain 1 belong to" bitfld.long 0x0 3. "LOCK,Lock write for GID" "0,1" bitfld.long 0x0 0.--2. "GID,Group ID" "0,1,2,3,4,5,6,7" group.long 0x2230++0x3 line.long 0x0 "DOM_GID_2,Indicate which group domain 2 belong to" bitfld.long 0x0 3. "LOCK,Lock write for GID" "0,1" bitfld.long 0x0 0.--2. "GID,Group ID" "0,1,2,3,4,5,6,7" group.long 0x2248++0x3 line.long 0x0 "DOM_GID_3,Indicate which group domain 3 belong to" bitfld.long 0x0 3. "LOCK,Lock write for GID" "0,1" bitfld.long 0x0 0.--2. "GID,Group ID" "0,1,2,3,4,5,6,7" group.long 0x2260++0x3 line.long 0x0 "DOM_GID_4,Indicate which group domain 4 belong to" bitfld.long 0x0 3. "LOCK,Lock write for GID" "0,1" bitfld.long 0x0 0.--2. "GID,Group ID" "0,1,2,3,4,5,6,7" group.long 0x2278++0x3 line.long 0x0 "DOM_GID_5,Indicate which group domain 5 belong to" bitfld.long 0x0 3. "LOCK,Lock write for GID" "0,1" bitfld.long 0x0 0.--2. "GID,Group ID" "0,1,2,3,4,5,6,7" group.long 0x2290++0x3 line.long 0x0 "DOM_GID_6,Indicate which group domain 6 belong to" bitfld.long 0x0 3. "LOCK,Lock write for GID" "0,1" bitfld.long 0x0 0.--2. "GID,Group ID" "0,1,2,3,4,5,6,7" group.long 0x22A8++0x3 line.long 0x0 "DOM_GID_7,Indicate which group domain 7 belong to" bitfld.long 0x0 3. "LOCK,Lock write for GID" "0,1" bitfld.long 0x0 0.--2. "GID,Group ID" "0,1,2,3,4,5,6,7" group.long 0x22C0++0x3 line.long 0x0 "DOM_GID_8,Indicate which group domain 8 belong to" bitfld.long 0x0 3. "LOCK,Lock write for GID" "0,1" bitfld.long 0x0 0.--2. "GID,Group ID" "0,1,2,3,4,5,6,7" group.long 0x22D8++0x3 line.long 0x0 "DOM_GID_9,Indicate which group domain 9 belong to" bitfld.long 0x0 3. "LOCK,Lock write for GID" "0,1" bitfld.long 0x0 0.--2. "GID,Group ID" "0,1,2,3,4,5,6,7" group.long 0x22F0++0x3 line.long 0x0 "DOM_GID_10,Indicate which group domain 10 belong to" bitfld.long 0x0 3. "LOCK,Lock write for GID" "0,1" bitfld.long 0x0 0.--2. "GID,Group ID" "0,1,2,3,4,5,6,7" group.long 0x2308++0x3 line.long 0x0 "DOM_GID_11,Indicate which group domain 11 belong to" bitfld.long 0x0 3. "LOCK,Lock write for GID" "0,1" bitfld.long 0x0 0.--2. "GID,Group ID" "0,1,2,3,4,5,6,7" group.long 0x2320++0x3 line.long 0x0 "DOM_GID_12,Indicate which group domain 12 belong to" bitfld.long 0x0 3. "LOCK,Lock write for GID" "0,1" bitfld.long 0x0 0.--2. "GID,Group ID" "0,1,2,3,4,5,6,7" group.long 0x2338++0x3 line.long 0x0 "DOM_GID_13,Indicate which group domain 13 belong to" bitfld.long 0x0 3. "LOCK,Lock write for GID" "0,1" bitfld.long 0x0 0.--2. "GID,Group ID" "0,1,2,3,4,5,6,7" group.long 0x2350++0x3 line.long 0x0 "DOM_GID_14,Indicate which group domain 14 belong to" bitfld.long 0x0 3. "LOCK,Lock write for GID" "0,1" bitfld.long 0x0 0.--2. "GID,Group ID" "0,1,2,3,4,5,6,7" group.long 0x2368++0x3 line.long 0x0 "DOM_GID_15,Indicate which group domain 15 belong to" bitfld.long 0x0 3. "LOCK,Lock write for GID" "0,1" bitfld.long 0x0 0.--2. "GID,Group ID" "0,1,2,3,4,5,6,7" repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x34 0x68 0x9C 0xD0 0x104 0x138 0x16C 0x1A0 0x1D4 0x208 0x23C 0x270 0x2A4 0x2D8 0x30C ) group.long ($2+0x2400)++0x3 line.long 0x0 "DOM_PER0_$1,Domain Permission Control. It can be only configured by resource manager and domain owner." bitfld.long 0x0 31. "DOM7_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 29.--30. "DOM7_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 28. "DOM7_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 27. "DOM6_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 25.--26. "DOM6_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" newline bitfld.long 0x0 24. "DOM6_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 23. "DOM5_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 21.--22. "DOM5_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 20. "DOM5_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 19. "DOM4_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" newline bitfld.long 0x0 17.--18. "DOM4_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM4_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 15. "DOM3_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 13.--14. "DOM3_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 12. "DOM3_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" newline bitfld.long 0x0 11. "DOM2_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 9.--10. "DOM2_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM2_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 7. "DOM1_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 5.--6. "DOM1_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" newline bitfld.long 0x0 4. "DOM1_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 3. "DOM0_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 1.--2. "DOM0_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM0_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" repeat.end repeat 16. (list 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1A 0x1B 0x1C 0x1D 0x1E 0x1F )(list 0x340 0x374 0x3A8 0x3DC 0x410 0x444 0x478 0x4AC 0x4E0 0x514 0x548 0x57C 0x5B0 0x5E4 0x618 0x64C ) group.long ($2+0x2400)++0x3 line.long 0x0 "DOM_PER0_$1,Domain Permission Control. It can be only configured by resource manager and domain owner." bitfld.long 0x0 31. "DOM7_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 29.--30. "DOM7_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 28. "DOM7_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 27. "DOM6_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 25.--26. "DOM6_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" newline bitfld.long 0x0 24. "DOM6_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 23. "DOM5_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 21.--22. "DOM5_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 20. "DOM5_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 19. "DOM4_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" newline bitfld.long 0x0 17.--18. "DOM4_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM4_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 15. "DOM3_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 13.--14. "DOM3_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 12. "DOM3_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" newline bitfld.long 0x0 11. "DOM2_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 9.--10. "DOM2_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM2_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 7. "DOM1_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 5.--6. "DOM1_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" newline bitfld.long 0x0 4. "DOM1_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 3. "DOM0_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 1.--2. "DOM0_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM0_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" repeat.end repeat 16. (list 0x20 0x21 0x22 0x23 0x24 0x25 0x26 0x27 0x28 0x29 0x2A 0x2B 0x2C 0x2D 0x2E 0x2F )(list 0x680 0x6B4 0x6E8 0x71C 0x750 0x784 0x7B8 0x7EC 0x820 0x854 0x888 0x8BC 0x8F0 0x924 0x958 0x98C ) group.long ($2+0x2400)++0x3 line.long 0x0 "DOM_PER0_$1,Domain Permission Control. It can be only configured by resource manager and domain owner." bitfld.long 0x0 31. "DOM7_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 29.--30. "DOM7_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 28. "DOM7_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 27. "DOM6_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 25.--26. "DOM6_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" newline bitfld.long 0x0 24. "DOM6_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 23. "DOM5_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 21.--22. "DOM5_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 20. "DOM5_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 19. "DOM4_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" newline bitfld.long 0x0 17.--18. "DOM4_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM4_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 15. "DOM3_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 13.--14. "DOM3_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 12. "DOM3_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" newline bitfld.long 0x0 11. "DOM2_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 9.--10. "DOM2_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM2_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 7. "DOM1_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 5.--6. "DOM1_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" newline bitfld.long 0x0 4. "DOM1_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 3. "DOM0_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 1.--2. "DOM0_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM0_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" repeat.end repeat 16. (list 0x30 0x31 0x32 0x33 0x34 0x35 0x36 0x37 0x38 0x39 0x3A 0x3B 0x3C 0x3D 0x3E 0x3F )(list 0x9C0 0x9F4 0xA28 0xA5C 0xA90 0xAC4 0xAF8 0xB2C 0xB60 0xB94 0xBC8 0xBFC 0xC30 0xC64 0xC98 0xCCC ) group.long ($2+0x2400)++0x3 line.long 0x0 "DOM_PER0_$1,Domain Permission Control. It can be only configured by resource manager and domain owner." bitfld.long 0x0 31. "DOM7_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 29.--30. "DOM7_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 28. "DOM7_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 27. "DOM6_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 25.--26. "DOM6_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" newline bitfld.long 0x0 24. "DOM6_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 23. "DOM5_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 21.--22. "DOM5_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 20. "DOM5_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 19. "DOM4_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" newline bitfld.long 0x0 17.--18. "DOM4_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM4_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 15. "DOM3_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 13.--14. "DOM3_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 12. "DOM3_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" newline bitfld.long 0x0 11. "DOM2_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 9.--10. "DOM2_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM2_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 7. "DOM1_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 5.--6. "DOM1_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" newline bitfld.long 0x0 4. "DOM1_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 3. "DOM0_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 1.--2. "DOM0_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM0_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" repeat.end repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x34 0x68 0x9C 0xD0 0x104 0x138 0x16C 0x1A0 0x1D4 0x208 0x23C 0x270 0x2A4 0x2D8 0x30C ) group.long ($2+0x2404)++0x3 line.long 0x0 "DOM_PER1_$1,Domain Permission Control. It can be only configured by resource manager and domain owner." bitfld.long 0x0 31. "DOM15_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 29.--30. "DOM15_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 28. "DOM15_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 27. "DOM14_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 25.--26. "DOM14_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" newline bitfld.long 0x0 24. "DOM14_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 23. "DOM13_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 21.--22. "DOM13_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 20. "DOM13_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 19. "DOM12_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" newline bitfld.long 0x0 17.--18. "DOM12_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM12_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 15. "DOM11_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 13.--14. "DOM11_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 12. "DOM11_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" newline bitfld.long 0x0 11. "DOM10_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 9.--10. "DOM10_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM10_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 7. "DOM9_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 5.--6. "DOM9_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" newline bitfld.long 0x0 4. "DOM9_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 3. "DOM8_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 1.--2. "DOM8_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM8_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" repeat.end repeat 16. (list 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1A 0x1B 0x1C 0x1D 0x1E 0x1F )(list 0x340 0x374 0x3A8 0x3DC 0x410 0x444 0x478 0x4AC 0x4E0 0x514 0x548 0x57C 0x5B0 0x5E4 0x618 0x64C ) group.long ($2+0x2404)++0x3 line.long 0x0 "DOM_PER1_$1,Domain Permission Control. It can be only configured by resource manager and domain owner." bitfld.long 0x0 31. "DOM15_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 29.--30. "DOM15_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 28. "DOM15_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 27. "DOM14_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 25.--26. "DOM14_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" newline bitfld.long 0x0 24. "DOM14_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 23. "DOM13_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 21.--22. "DOM13_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 20. "DOM13_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 19. "DOM12_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" newline bitfld.long 0x0 17.--18. "DOM12_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM12_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 15. "DOM11_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 13.--14. "DOM11_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 12. "DOM11_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" newline bitfld.long 0x0 11. "DOM10_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 9.--10. "DOM10_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM10_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 7. "DOM9_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 5.--6. "DOM9_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" newline bitfld.long 0x0 4. "DOM9_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 3. "DOM8_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 1.--2. "DOM8_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM8_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" repeat.end repeat 16. (list 0x20 0x21 0x22 0x23 0x24 0x25 0x26 0x27 0x28 0x29 0x2A 0x2B 0x2C 0x2D 0x2E 0x2F )(list 0x680 0x6B4 0x6E8 0x71C 0x750 0x784 0x7B8 0x7EC 0x820 0x854 0x888 0x8BC 0x8F0 0x924 0x958 0x98C ) group.long ($2+0x2404)++0x3 line.long 0x0 "DOM_PER1_$1,Domain Permission Control. It can be only configured by resource manager and domain owner." bitfld.long 0x0 31. "DOM15_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 29.--30. "DOM15_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 28. "DOM15_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 27. "DOM14_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 25.--26. "DOM14_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" newline bitfld.long 0x0 24. "DOM14_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 23. "DOM13_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 21.--22. "DOM13_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 20. "DOM13_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 19. "DOM12_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" newline bitfld.long 0x0 17.--18. "DOM12_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM12_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 15. "DOM11_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 13.--14. "DOM11_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 12. "DOM11_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" newline bitfld.long 0x0 11. "DOM10_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 9.--10. "DOM10_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM10_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 7. "DOM9_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 5.--6. "DOM9_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" newline bitfld.long 0x0 4. "DOM9_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 3. "DOM8_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 1.--2. "DOM8_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM8_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" repeat.end repeat 16. (list 0x30 0x31 0x32 0x33 0x34 0x35 0x36 0x37 0x38 0x39 0x3A 0x3B 0x3C 0x3D 0x3E 0x3F )(list 0x9C0 0x9F4 0xA28 0xA5C 0xA90 0xAC4 0xAF8 0xB2C 0xB60 0xB94 0xBC8 0xBFC 0xC30 0xC64 0xC98 0xCCC ) group.long ($2+0x2404)++0x3 line.long 0x0 "DOM_PER1_$1,Domain Permission Control. It can be only configured by resource manager and domain owner." bitfld.long 0x0 31. "DOM15_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 29.--30. "DOM15_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 28. "DOM15_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 27. "DOM14_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 25.--26. "DOM14_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" newline bitfld.long 0x0 24. "DOM14_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 23. "DOM13_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 21.--22. "DOM13_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 20. "DOM13_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 19. "DOM12_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" newline bitfld.long 0x0 17.--18. "DOM12_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM12_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 15. "DOM11_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 13.--14. "DOM11_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 12. "DOM11_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" newline bitfld.long 0x0 11. "DOM10_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 9.--10. "DOM10_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM10_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 7. "DOM9_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 5.--6. "DOM9_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" newline bitfld.long 0x0 4. "DOM9_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 3. "DOM8_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 1.--2. "DOM8_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM8_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" repeat.end repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x34 0x68 0x9C 0xD0 0x104 0x138 0x16C 0x1A0 0x1D4 0x208 0x23C 0x270 0x2A4 0x2D8 0x30C ) group.long ($2+0x2408)++0x3 line.long 0x0 "SEC_PER0_$1,This register is only used for resource manager to control secure access permission." bitfld.long 0x0 31. "DOM3_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM3_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM3_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM3_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM2_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM2_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM2_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM2_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM1_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM1_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM1_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM1_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM0_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM0_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM0_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM0_SEC_EN,Domain secure permission control enable" "0,1" repeat.end repeat 16. (list 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1A 0x1B 0x1C 0x1D 0x1E 0x1F )(list 0x340 0x374 0x3A8 0x3DC 0x410 0x444 0x478 0x4AC 0x4E0 0x514 0x548 0x57C 0x5B0 0x5E4 0x618 0x64C ) group.long ($2+0x2408)++0x3 line.long 0x0 "SEC_PER0_$1,This register is only used for resource manager to control secure access permission." bitfld.long 0x0 31. "DOM3_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM3_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM3_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM3_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM2_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM2_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM2_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM2_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM1_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM1_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM1_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM1_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM0_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM0_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM0_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM0_SEC_EN,Domain secure permission control enable" "0,1" repeat.end repeat 16. (list 0x20 0x21 0x22 0x23 0x24 0x25 0x26 0x27 0x28 0x29 0x2A 0x2B 0x2C 0x2D 0x2E 0x2F )(list 0x680 0x6B4 0x6E8 0x71C 0x750 0x784 0x7B8 0x7EC 0x820 0x854 0x888 0x8BC 0x8F0 0x924 0x958 0x98C ) group.long ($2+0x2408)++0x3 line.long 0x0 "SEC_PER0_$1,This register is only used for resource manager to control secure access permission." bitfld.long 0x0 31. "DOM3_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM3_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM3_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM3_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM2_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM2_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM2_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM2_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM1_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM1_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM1_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM1_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM0_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM0_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM0_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM0_SEC_EN,Domain secure permission control enable" "0,1" repeat.end repeat 16. (list 0x30 0x31 0x32 0x33 0x34 0x35 0x36 0x37 0x38 0x39 0x3A 0x3B 0x3C 0x3D 0x3E 0x3F )(list 0x9C0 0x9F4 0xA28 0xA5C 0xA90 0xAC4 0xAF8 0xB2C 0xB60 0xB94 0xBC8 0xBFC 0xC30 0xC64 0xC98 0xCCC ) group.long ($2+0x2408)++0x3 line.long 0x0 "SEC_PER0_$1,This register is only used for resource manager to control secure access permission." bitfld.long 0x0 31. "DOM3_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM3_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM3_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM3_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM2_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM2_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM2_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM2_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM1_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM1_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM1_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM1_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM0_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM0_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM0_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM0_SEC_EN,Domain secure permission control enable" "0,1" repeat.end repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x34 0x68 0x9C 0xD0 0x104 0x138 0x16C 0x1A0 0x1D4 0x208 0x23C 0x270 0x2A4 0x2D8 0x30C ) group.long ($2+0x240C)++0x3 line.long 0x0 "SEC_PER1_$1,This register is only used for resource manager to control secure access permission." bitfld.long 0x0 31. "DOM7_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM7_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM7_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM7_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM6_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM6_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM6_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM6_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM5_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM5_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM5_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM5_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM4_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM4_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM4_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM4_SEC_EN,Domain secure permission control enable" "0,1" repeat.end repeat 16. (list 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1A 0x1B 0x1C 0x1D 0x1E 0x1F )(list 0x340 0x374 0x3A8 0x3DC 0x410 0x444 0x478 0x4AC 0x4E0 0x514 0x548 0x57C 0x5B0 0x5E4 0x618 0x64C ) group.long ($2+0x240C)++0x3 line.long 0x0 "SEC_PER1_$1,This register is only used for resource manager to control secure access permission." bitfld.long 0x0 31. "DOM7_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM7_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM7_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM7_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM6_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM6_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM6_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM6_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM5_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM5_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM5_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM5_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM4_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM4_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM4_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM4_SEC_EN,Domain secure permission control enable" "0,1" repeat.end repeat 16. (list 0x20 0x21 0x22 0x23 0x24 0x25 0x26 0x27 0x28 0x29 0x2A 0x2B 0x2C 0x2D 0x2E 0x2F )(list 0x680 0x6B4 0x6E8 0x71C 0x750 0x784 0x7B8 0x7EC 0x820 0x854 0x888 0x8BC 0x8F0 0x924 0x958 0x98C ) group.long ($2+0x240C)++0x3 line.long 0x0 "SEC_PER1_$1,This register is only used for resource manager to control secure access permission." bitfld.long 0x0 31. "DOM7_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM7_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM7_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM7_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM6_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM6_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM6_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM6_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM5_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM5_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM5_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM5_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM4_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM4_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM4_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM4_SEC_EN,Domain secure permission control enable" "0,1" repeat.end repeat 16. (list 0x30 0x31 0x32 0x33 0x34 0x35 0x36 0x37 0x38 0x39 0x3A 0x3B 0x3C 0x3D 0x3E 0x3F )(list 0x9C0 0x9F4 0xA28 0xA5C 0xA90 0xAC4 0xAF8 0xB2C 0xB60 0xB94 0xBC8 0xBFC 0xC30 0xC64 0xC98 0xCCC ) group.long ($2+0x240C)++0x3 line.long 0x0 "SEC_PER1_$1,This register is only used for resource manager to control secure access permission." bitfld.long 0x0 31. "DOM7_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM7_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM7_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM7_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM6_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM6_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM6_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM6_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM5_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM5_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM5_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM5_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM4_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM4_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM4_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM4_SEC_EN,Domain secure permission control enable" "0,1" repeat.end repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x34 0x68 0x9C 0xD0 0x104 0x138 0x16C 0x1A0 0x1D4 0x208 0x23C 0x270 0x2A4 0x2D8 0x30C ) group.long ($2+0x2410)++0x3 line.long 0x0 "SEC_PER2_$1,This register is only used for resource manager to control secure access permission." bitfld.long 0x0 31. "DOM11_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM11_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM11_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM11_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM10_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM10_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM10_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM10_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM9_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM9_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM9_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM9_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM8_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM8_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM8_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM8_SEC_EN,Domain secure permission control enable" "0,1" repeat.end repeat 16. (list 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1A 0x1B 0x1C 0x1D 0x1E 0x1F )(list 0x340 0x374 0x3A8 0x3DC 0x410 0x444 0x478 0x4AC 0x4E0 0x514 0x548 0x57C 0x5B0 0x5E4 0x618 0x64C ) group.long ($2+0x2410)++0x3 line.long 0x0 "SEC_PER2_$1,This register is only used for resource manager to control secure access permission." bitfld.long 0x0 31. "DOM11_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM11_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM11_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM11_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM10_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM10_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM10_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM10_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM9_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM9_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM9_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM9_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM8_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM8_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM8_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM8_SEC_EN,Domain secure permission control enable" "0,1" repeat.end repeat 16. (list 0x20 0x21 0x22 0x23 0x24 0x25 0x26 0x27 0x28 0x29 0x2A 0x2B 0x2C 0x2D 0x2E 0x2F )(list 0x680 0x6B4 0x6E8 0x71C 0x750 0x784 0x7B8 0x7EC 0x820 0x854 0x888 0x8BC 0x8F0 0x924 0x958 0x98C ) group.long ($2+0x2410)++0x3 line.long 0x0 "SEC_PER2_$1,This register is only used for resource manager to control secure access permission." bitfld.long 0x0 31. "DOM11_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM11_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM11_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM11_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM10_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM10_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM10_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM10_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM9_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM9_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM9_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM9_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM8_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM8_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM8_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM8_SEC_EN,Domain secure permission control enable" "0,1" repeat.end repeat 16. (list 0x30 0x31 0x32 0x33 0x34 0x35 0x36 0x37 0x38 0x39 0x3A 0x3B 0x3C 0x3D 0x3E 0x3F )(list 0x9C0 0x9F4 0xA28 0xA5C 0xA90 0xAC4 0xAF8 0xB2C 0xB60 0xB94 0xBC8 0xBFC 0xC30 0xC64 0xC98 0xCCC ) group.long ($2+0x2410)++0x3 line.long 0x0 "SEC_PER2_$1,This register is only used for resource manager to control secure access permission." bitfld.long 0x0 31. "DOM11_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM11_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM11_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM11_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM10_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM10_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM10_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM10_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM9_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM9_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM9_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM9_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM8_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM8_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM8_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM8_SEC_EN,Domain secure permission control enable" "0,1" repeat.end repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x34 0x68 0x9C 0xD0 0x104 0x138 0x16C 0x1A0 0x1D4 0x208 0x23C 0x270 0x2A4 0x2D8 0x30C ) group.long ($2+0x2414)++0x3 line.long 0x0 "SEC_PER3_$1,This register is only used for resource manager to control secure access permission." bitfld.long 0x0 31. "DOM15_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM15_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM15_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM15_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM14_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM14_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM14_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM14_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM13_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM13_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM13_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM13_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM12_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM12_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM12_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM12_SEC_EN,Domain secure permission control enable" "0,1" repeat.end repeat 16. (list 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1A 0x1B 0x1C 0x1D 0x1E 0x1F )(list 0x340 0x374 0x3A8 0x3DC 0x410 0x444 0x478 0x4AC 0x4E0 0x514 0x548 0x57C 0x5B0 0x5E4 0x618 0x64C ) group.long ($2+0x2414)++0x3 line.long 0x0 "SEC_PER3_$1,This register is only used for resource manager to control secure access permission." bitfld.long 0x0 31. "DOM15_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM15_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM15_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM15_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM14_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM14_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM14_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM14_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM13_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM13_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM13_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM13_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM12_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM12_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM12_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM12_SEC_EN,Domain secure permission control enable" "0,1" repeat.end repeat 16. (list 0x20 0x21 0x22 0x23 0x24 0x25 0x26 0x27 0x28 0x29 0x2A 0x2B 0x2C 0x2D 0x2E 0x2F )(list 0x680 0x6B4 0x6E8 0x71C 0x750 0x784 0x7B8 0x7EC 0x820 0x854 0x888 0x8BC 0x8F0 0x924 0x958 0x98C ) group.long ($2+0x2414)++0x3 line.long 0x0 "SEC_PER3_$1,This register is only used for resource manager to control secure access permission." bitfld.long 0x0 31. "DOM15_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM15_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM15_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM15_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM14_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM14_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM14_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM14_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM13_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM13_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM13_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM13_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM12_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM12_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM12_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM12_SEC_EN,Domain secure permission control enable" "0,1" repeat.end repeat 16. (list 0x30 0x31 0x32 0x33 0x34 0x35 0x36 0x37 0x38 0x39 0x3A 0x3B 0x3C 0x3D 0x3E 0x3F )(list 0x9C0 0x9F4 0xA28 0xA5C 0xA90 0xAC4 0xAF8 0xB2C 0xB60 0xB94 0xBC8 0xBFC 0xC30 0xC64 0xC98 0xCCC ) group.long ($2+0x2414)++0x3 line.long 0x0 "SEC_PER3_$1,This register is only used for resource manager to control secure access permission." bitfld.long 0x0 31. "DOM15_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM15_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM15_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM15_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM14_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM14_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM14_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM14_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM13_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM13_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM13_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM13_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM12_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM12_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM12_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM12_SEC_EN,Domain secure permission control enable" "0,1" repeat.end repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x34 0x68 0x9C 0xD0 0x104 0x138 0x16C 0x1A0 0x1D4 0x208 0x23C 0x270 0x2A4 0x2D8 0x30C ) group.long ($2+0x2418)++0x3 line.long 0x0 "PRI_PER0_$1,This register is only used for resource manager to control privileged access permission." bitfld.long 0x0 31. "DOM3_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM3_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM3_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM3_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM2_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM2_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM2_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM2_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM1_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM1_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM1_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM1_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM0_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM0_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM0_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM0_PRI_EN,Domain privileged permission control enable" "0,1" repeat.end repeat 16. (list 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1A 0x1B 0x1C 0x1D 0x1E 0x1F )(list 0x340 0x374 0x3A8 0x3DC 0x410 0x444 0x478 0x4AC 0x4E0 0x514 0x548 0x57C 0x5B0 0x5E4 0x618 0x64C ) group.long ($2+0x2418)++0x3 line.long 0x0 "PRI_PER0_$1,This register is only used for resource manager to control privileged access permission." bitfld.long 0x0 31. "DOM3_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM3_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM3_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM3_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM2_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM2_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM2_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM2_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM1_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM1_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM1_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM1_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM0_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM0_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM0_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM0_PRI_EN,Domain privileged permission control enable" "0,1" repeat.end repeat 16. (list 0x20 0x21 0x22 0x23 0x24 0x25 0x26 0x27 0x28 0x29 0x2A 0x2B 0x2C 0x2D 0x2E 0x2F )(list 0x680 0x6B4 0x6E8 0x71C 0x750 0x784 0x7B8 0x7EC 0x820 0x854 0x888 0x8BC 0x8F0 0x924 0x958 0x98C ) group.long ($2+0x2418)++0x3 line.long 0x0 "PRI_PER0_$1,This register is only used for resource manager to control privileged access permission." bitfld.long 0x0 31. "DOM3_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM3_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM3_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM3_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM2_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM2_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM2_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM2_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM1_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM1_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM1_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM1_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM0_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM0_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM0_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM0_PRI_EN,Domain privileged permission control enable" "0,1" repeat.end repeat 16. (list 0x30 0x31 0x32 0x33 0x34 0x35 0x36 0x37 0x38 0x39 0x3A 0x3B 0x3C 0x3D 0x3E 0x3F )(list 0x9C0 0x9F4 0xA28 0xA5C 0xA90 0xAC4 0xAF8 0xB2C 0xB60 0xB94 0xBC8 0xBFC 0xC30 0xC64 0xC98 0xCCC ) group.long ($2+0x2418)++0x3 line.long 0x0 "PRI_PER0_$1,This register is only used for resource manager to control privileged access permission." bitfld.long 0x0 31. "DOM3_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM3_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM3_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM3_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM2_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM2_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM2_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM2_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM1_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM1_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM1_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM1_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM0_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM0_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM0_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM0_PRI_EN,Domain privileged permission control enable" "0,1" repeat.end repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x34 0x68 0x9C 0xD0 0x104 0x138 0x16C 0x1A0 0x1D4 0x208 0x23C 0x270 0x2A4 0x2D8 0x30C ) group.long ($2+0x241C)++0x3 line.long 0x0 "PRI_PER1_$1,This register is only used for resource manager to control privileged access permission." bitfld.long 0x0 31. "DOM7_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM7_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM7_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM7_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM6_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM6_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM6_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM6_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM5_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM5_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM5_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM5_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM4_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM4_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM4_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM4_PRI_EN,Domain privileged permission control enable" "0,1" repeat.end repeat 16. (list 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1A 0x1B 0x1C 0x1D 0x1E 0x1F )(list 0x340 0x374 0x3A8 0x3DC 0x410 0x444 0x478 0x4AC 0x4E0 0x514 0x548 0x57C 0x5B0 0x5E4 0x618 0x64C ) group.long ($2+0x241C)++0x3 line.long 0x0 "PRI_PER1_$1,This register is only used for resource manager to control privileged access permission." bitfld.long 0x0 31. "DOM7_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM7_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM7_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM7_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM6_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM6_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM6_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM6_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM5_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM5_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM5_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM5_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM4_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM4_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM4_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM4_PRI_EN,Domain privileged permission control enable" "0,1" repeat.end repeat 16. (list 0x20 0x21 0x22 0x23 0x24 0x25 0x26 0x27 0x28 0x29 0x2A 0x2B 0x2C 0x2D 0x2E 0x2F )(list 0x680 0x6B4 0x6E8 0x71C 0x750 0x784 0x7B8 0x7EC 0x820 0x854 0x888 0x8BC 0x8F0 0x924 0x958 0x98C ) group.long ($2+0x241C)++0x3 line.long 0x0 "PRI_PER1_$1,This register is only used for resource manager to control privileged access permission." bitfld.long 0x0 31. "DOM7_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM7_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM7_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM7_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM6_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM6_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM6_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM6_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM5_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM5_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM5_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM5_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM4_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM4_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM4_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM4_PRI_EN,Domain privileged permission control enable" "0,1" repeat.end repeat 16. (list 0x30 0x31 0x32 0x33 0x34 0x35 0x36 0x37 0x38 0x39 0x3A 0x3B 0x3C 0x3D 0x3E 0x3F )(list 0x9C0 0x9F4 0xA28 0xA5C 0xA90 0xAC4 0xAF8 0xB2C 0xB60 0xB94 0xBC8 0xBFC 0xC30 0xC64 0xC98 0xCCC ) group.long ($2+0x241C)++0x3 line.long 0x0 "PRI_PER1_$1,This register is only used for resource manager to control privileged access permission." bitfld.long 0x0 31. "DOM7_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM7_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM7_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM7_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM6_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM6_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM6_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM6_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM5_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM5_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM5_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM5_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM4_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM4_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM4_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM4_PRI_EN,Domain privileged permission control enable" "0,1" repeat.end repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x34 0x68 0x9C 0xD0 0x104 0x138 0x16C 0x1A0 0x1D4 0x208 0x23C 0x270 0x2A4 0x2D8 0x30C ) group.long ($2+0x2420)++0x3 line.long 0x0 "PRI_PER2_$1,This register is only used for resource manager to control privileged access permission." bitfld.long 0x0 31. "DOM11_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM11_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM11_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM11_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM10_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM10_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM10_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM10_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM9_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM9_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM9_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM9_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM8_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM8_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM8_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM8_PRI_EN,Domain privileged permission control enable" "0,1" repeat.end repeat 16. (list 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1A 0x1B 0x1C 0x1D 0x1E 0x1F )(list 0x340 0x374 0x3A8 0x3DC 0x410 0x444 0x478 0x4AC 0x4E0 0x514 0x548 0x57C 0x5B0 0x5E4 0x618 0x64C ) group.long ($2+0x2420)++0x3 line.long 0x0 "PRI_PER2_$1,This register is only used for resource manager to control privileged access permission." bitfld.long 0x0 31. "DOM11_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM11_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM11_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM11_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM10_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM10_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM10_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM10_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM9_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM9_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM9_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM9_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM8_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM8_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM8_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM8_PRI_EN,Domain privileged permission control enable" "0,1" repeat.end repeat 16. (list 0x20 0x21 0x22 0x23 0x24 0x25 0x26 0x27 0x28 0x29 0x2A 0x2B 0x2C 0x2D 0x2E 0x2F )(list 0x680 0x6B4 0x6E8 0x71C 0x750 0x784 0x7B8 0x7EC 0x820 0x854 0x888 0x8BC 0x8F0 0x924 0x958 0x98C ) group.long ($2+0x2420)++0x3 line.long 0x0 "PRI_PER2_$1,This register is only used for resource manager to control privileged access permission." bitfld.long 0x0 31. "DOM11_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM11_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM11_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM11_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM10_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM10_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM10_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM10_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM9_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM9_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM9_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM9_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM8_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM8_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM8_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM8_PRI_EN,Domain privileged permission control enable" "0,1" repeat.end repeat 16. (list 0x30 0x31 0x32 0x33 0x34 0x35 0x36 0x37 0x38 0x39 0x3A 0x3B 0x3C 0x3D 0x3E 0x3F )(list 0x9C0 0x9F4 0xA28 0xA5C 0xA90 0xAC4 0xAF8 0xB2C 0xB60 0xB94 0xBC8 0xBFC 0xC30 0xC64 0xC98 0xCCC ) group.long ($2+0x2420)++0x3 line.long 0x0 "PRI_PER2_$1,This register is only used for resource manager to control privileged access permission." bitfld.long 0x0 31. "DOM11_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM11_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM11_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM11_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM10_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM10_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM10_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM10_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM9_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM9_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM9_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM9_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM8_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM8_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM8_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM8_PRI_EN,Domain privileged permission control enable" "0,1" repeat.end repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x34 0x68 0x9C 0xD0 0x104 0x138 0x16C 0x1A0 0x1D4 0x208 0x23C 0x270 0x2A4 0x2D8 0x30C ) group.long ($2+0x2424)++0x3 line.long 0x0 "PRI_PER3_$1,This register is only used for resource manager to control privileged access permission." bitfld.long 0x0 31. "DOM15_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM15_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM15_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM15_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM14_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM14_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM14_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM14_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM13_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM13_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM13_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM13_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM12_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM12_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM12_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM12_PRI_EN,Domain privileged permission control enable" "0,1" repeat.end repeat 16. (list 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1A 0x1B 0x1C 0x1D 0x1E 0x1F )(list 0x340 0x374 0x3A8 0x3DC 0x410 0x444 0x478 0x4AC 0x4E0 0x514 0x548 0x57C 0x5B0 0x5E4 0x618 0x64C ) group.long ($2+0x2424)++0x3 line.long 0x0 "PRI_PER3_$1,This register is only used for resource manager to control privileged access permission." bitfld.long 0x0 31. "DOM15_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM15_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM15_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM15_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM14_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM14_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM14_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM14_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM13_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM13_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM13_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM13_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM12_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM12_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM12_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM12_PRI_EN,Domain privileged permission control enable" "0,1" repeat.end repeat 16. (list 0x20 0x21 0x22 0x23 0x24 0x25 0x26 0x27 0x28 0x29 0x2A 0x2B 0x2C 0x2D 0x2E 0x2F )(list 0x680 0x6B4 0x6E8 0x71C 0x750 0x784 0x7B8 0x7EC 0x820 0x854 0x888 0x8BC 0x8F0 0x924 0x958 0x98C ) group.long ($2+0x2424)++0x3 line.long 0x0 "PRI_PER3_$1,This register is only used for resource manager to control privileged access permission." bitfld.long 0x0 31. "DOM15_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM15_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM15_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM15_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM14_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM14_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM14_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM14_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM13_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM13_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM13_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM13_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM12_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM12_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM12_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM12_PRI_EN,Domain privileged permission control enable" "0,1" repeat.end repeat 16. (list 0x30 0x31 0x32 0x33 0x34 0x35 0x36 0x37 0x38 0x39 0x3A 0x3B 0x3C 0x3D 0x3E 0x3F )(list 0x9C0 0x9F4 0xA28 0xA5C 0xA90 0xAC4 0xAF8 0xB2C 0xB60 0xB94 0xBC8 0xBFC 0xC30 0xC64 0xC98 0xCCC ) group.long ($2+0x2424)++0x3 line.long 0x0 "PRI_PER3_$1,This register is only used for resource manager to control privileged access permission." bitfld.long 0x0 31. "DOM15_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM15_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM15_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM15_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM14_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM14_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM14_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM14_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM13_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM13_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM13_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM13_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM12_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM12_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM12_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM12_PRI_EN,Domain privileged permission control enable" "0,1" repeat.end repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x34 0x68 0x9C 0xD0 0x104 0x138 0x16C 0x1A0 0x1D4 0x208 0x23C 0x270 0x2A4 0x2D8 0x30C ) group.long ($2+0x2428)++0x3 line.long 0x0 "DOM_SEC_PER_$1,This register is only used for domain master to control secure access permission. When the domain master write this register. it only changes the secure permission for itself. When the domain master read this register. it gets permission.." bitfld.long 0x0 7. "DOM_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" newline bitfld.long 0x0 0. "DOM_SEC_EN,Domain secure permission control enable" "0,1" repeat.end repeat 16. (list 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1A 0x1B 0x1C 0x1D 0x1E 0x1F )(list 0x340 0x374 0x3A8 0x3DC 0x410 0x444 0x478 0x4AC 0x4E0 0x514 0x548 0x57C 0x5B0 0x5E4 0x618 0x64C ) group.long ($2+0x2428)++0x3 line.long 0x0 "DOM_SEC_PER_$1,This register is only used for domain master to control secure access permission. When the domain master write this register. it only changes the secure permission for itself. When the domain master read this register. it gets permission.." bitfld.long 0x0 7. "DOM_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" newline bitfld.long 0x0 0. "DOM_SEC_EN,Domain secure permission control enable" "0,1" repeat.end repeat 16. (list 0x20 0x21 0x22 0x23 0x24 0x25 0x26 0x27 0x28 0x29 0x2A 0x2B 0x2C 0x2D 0x2E 0x2F )(list 0x680 0x6B4 0x6E8 0x71C 0x750 0x784 0x7B8 0x7EC 0x820 0x854 0x888 0x8BC 0x8F0 0x924 0x958 0x98C ) group.long ($2+0x2428)++0x3 line.long 0x0 "DOM_SEC_PER_$1,This register is only used for domain master to control secure access permission. When the domain master write this register. it only changes the secure permission for itself. When the domain master read this register. it gets permission.." bitfld.long 0x0 7. "DOM_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" newline bitfld.long 0x0 0. "DOM_SEC_EN,Domain secure permission control enable" "0,1" repeat.end repeat 16. (list 0x30 0x31 0x32 0x33 0x34 0x35 0x36 0x37 0x38 0x39 0x3A 0x3B 0x3C 0x3D 0x3E 0x3F )(list 0x9C0 0x9F4 0xA28 0xA5C 0xA90 0xAC4 0xAF8 0xB2C 0xB60 0xB94 0xBC8 0xBFC 0xC30 0xC64 0xC98 0xCCC ) group.long ($2+0x2428)++0x3 line.long 0x0 "DOM_SEC_PER_$1,This register is only used for domain master to control secure access permission. When the domain master write this register. it only changes the secure permission for itself. When the domain master read this register. it gets permission.." bitfld.long 0x0 7. "DOM_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" newline bitfld.long 0x0 0. "DOM_SEC_EN,Domain secure permission control enable" "0,1" repeat.end repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x34 0x68 0x9C 0xD0 0x104 0x138 0x16C 0x1A0 0x1D4 0x208 0x23C 0x270 0x2A4 0x2D8 0x30C ) group.long ($2+0x242C)++0x3 line.long 0x0 "DOM_PRI_PER_$1,This register is only used for domain master to control secure access permission. When the domain master write this register. it only changes the secure permission for itself. When the domain master read this register. it gets permission.." bitfld.long 0x0 7. "DOM_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" newline bitfld.long 0x0 0. "DOM_PRI_EN,Domain privileged permission control enable" "0,1" repeat.end repeat 16. (list 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1A 0x1B 0x1C 0x1D 0x1E 0x1F )(list 0x340 0x374 0x3A8 0x3DC 0x410 0x444 0x478 0x4AC 0x4E0 0x514 0x548 0x57C 0x5B0 0x5E4 0x618 0x64C ) group.long ($2+0x242C)++0x3 line.long 0x0 "DOM_PRI_PER_$1,This register is only used for domain master to control secure access permission. When the domain master write this register. it only changes the secure permission for itself. When the domain master read this register. it gets permission.." bitfld.long 0x0 7. "DOM_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" newline bitfld.long 0x0 0. "DOM_PRI_EN,Domain privileged permission control enable" "0,1" repeat.end repeat 16. (list 0x20 0x21 0x22 0x23 0x24 0x25 0x26 0x27 0x28 0x29 0x2A 0x2B 0x2C 0x2D 0x2E 0x2F )(list 0x680 0x6B4 0x6E8 0x71C 0x750 0x784 0x7B8 0x7EC 0x820 0x854 0x888 0x8BC 0x8F0 0x924 0x958 0x98C ) group.long ($2+0x242C)++0x3 line.long 0x0 "DOM_PRI_PER_$1,This register is only used for domain master to control secure access permission. When the domain master write this register. it only changes the secure permission for itself. When the domain master read this register. it gets permission.." bitfld.long 0x0 7. "DOM_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" newline bitfld.long 0x0 0. "DOM_PRI_EN,Domain privileged permission control enable" "0,1" repeat.end repeat 16. (list 0x30 0x31 0x32 0x33 0x34 0x35 0x36 0x37 0x38 0x39 0x3A 0x3B 0x3C 0x3D 0x3E 0x3F )(list 0x9C0 0x9F4 0xA28 0xA5C 0xA90 0xAC4 0xAF8 0xB2C 0xB60 0xB94 0xBC8 0xBFC 0xC30 0xC64 0xC98 0xCCC ) group.long ($2+0x242C)++0x3 line.long 0x0 "DOM_PRI_PER_$1,This register is only used for domain master to control secure access permission. When the domain master write this register. it only changes the secure permission for itself. When the domain master read this register. it gets permission.." bitfld.long 0x0 7. "DOM_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" newline bitfld.long 0x0 0. "DOM_PRI_EN,Domain privileged permission control enable" "0,1" repeat.end repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x34 0x68 0x9C 0xD0 0x104 0x138 0x16C 0x1A0 0x1D4 0x208 0x23C 0x270 0x2A4 0x2D8 0x30C ) group.long ($2+0x2430)++0x3 line.long 0x0 "DOM_ASSIGN_$1,Use to assign domain for accessing DOM_SEC_PER and DOM_PRI_PER register. Only resource manager. group manager and domain owner can access this register. For write. group manager must write its owen domain ID. otherwise write accessing will.." hexmask.long.byte 0x0 0.--3. 1. "DID,accessing DOM_SEC_PER and DOM_PRI_PER register" repeat.end repeat 16. (list 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1A 0x1B 0x1C 0x1D 0x1E 0x1F )(list 0x340 0x374 0x3A8 0x3DC 0x410 0x444 0x478 0x4AC 0x4E0 0x514 0x548 0x57C 0x5B0 0x5E4 0x618 0x64C ) group.long ($2+0x2430)++0x3 line.long 0x0 "DOM_ASSIGN_$1,Use to assign domain for accessing DOM_SEC_PER and DOM_PRI_PER register. Only resource manager. group manager and domain owner can access this register. For write. group manager must write its owen domain ID. otherwise write accessing will.." hexmask.long.byte 0x0 0.--3. 1. "DID,accessing DOM_SEC_PER and DOM_PRI_PER register" repeat.end repeat 16. (list 0x20 0x21 0x22 0x23 0x24 0x25 0x26 0x27 0x28 0x29 0x2A 0x2B 0x2C 0x2D 0x2E 0x2F )(list 0x680 0x6B4 0x6E8 0x71C 0x750 0x784 0x7B8 0x7EC 0x820 0x854 0x888 0x8BC 0x8F0 0x924 0x958 0x98C ) group.long ($2+0x2430)++0x3 line.long 0x0 "DOM_ASSIGN_$1,Use to assign domain for accessing DOM_SEC_PER and DOM_PRI_PER register. Only resource manager. group manager and domain owner can access this register. For write. group manager must write its owen domain ID. otherwise write accessing will.." hexmask.long.byte 0x0 0.--3. 1. "DID,accessing DOM_SEC_PER and DOM_PRI_PER register" repeat.end repeat 16. (list 0x30 0x31 0x32 0x33 0x34 0x35 0x36 0x37 0x38 0x39 0x3A 0x3B 0x3C 0x3D 0x3E 0x3F )(list 0x9C0 0x9F4 0xA28 0xA5C 0xA90 0xAC4 0xAF8 0xB2C 0xB60 0xB94 0xBC8 0xBFC 0xC30 0xC64 0xC98 0xCCC ) group.long ($2+0x2430)++0x3 line.long 0x0 "DOM_ASSIGN_$1,Use to assign domain for accessing DOM_SEC_PER and DOM_PRI_PER register. Only resource manager. group manager and domain owner can access this register. For write. group manager must write its owen domain ID. otherwise write accessing will.." hexmask.long.byte 0x0 0.--3. 1. "DID,accessing DOM_SEC_PER and DOM_PRI_PER register" repeat.end repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x38 0x70 0xA8 0xE0 0x118 0x150 0x188 0x1C0 0x1F8 0x230 0x268 0x2A0 0x2D8 0x310 0x348 ) group.long ($2+0x3100)++0x3 line.long 0x0 "RGN_DOM_$1,Assign domain for peripheral. It can be only configured by resource and group manager" bitfld.long 0x0 31. "LOCK,When this bit is set lock write for all the bits in the register." "0,1" bitfld.long 0x0 4. "SET,Set together with DID would change permission of this resource to following setting: 1) Domain access control enabled. 2) Read/Write allowed for the domain owner. 3) Read/Write not allowed for all the other domains. If this bit is not set only DID.." "0,1" hexmask.long.byte 0x0 0.--3. 1. "DID,Assign domain for peripheral" repeat.end repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x38 0x70 0xA8 0xE0 0x118 0x150 0x188 0x1C0 0x1F8 0x230 0x268 0x2A0 0x2D8 0x310 0x348 ) group.long ($2+0x3104)++0x3 line.long 0x0 "RGN_DOM_PER0_$1,Domain Permission Control. It can be only configured by resource manager and domain owner." bitfld.long 0x0 31. "DOM7_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 29.--30. "DOM7_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 28. "DOM7_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 27. "DOM6_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 25.--26. "DOM6_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" newline bitfld.long 0x0 24. "DOM6_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 23. "DOM5_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 21.--22. "DOM5_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 20. "DOM5_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 19. "DOM4_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" newline bitfld.long 0x0 17.--18. "DOM4_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM4_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 15. "DOM3_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 13.--14. "DOM3_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 12. "DOM3_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" newline bitfld.long 0x0 11. "DOM2_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 9.--10. "DOM2_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM2_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 7. "DOM1_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 5.--6. "DOM1_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" newline bitfld.long 0x0 4. "DOM1_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 3. "DOM0_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 1.--2. "DOM0_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM0_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" repeat.end repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x38 0x70 0xA8 0xE0 0x118 0x150 0x188 0x1C0 0x1F8 0x230 0x268 0x2A0 0x2D8 0x310 0x348 ) group.long ($2+0x3108)++0x3 line.long 0x0 "RGN_DOM_PER1_$1,Domain Permission Control. It can be only configured by resource manager and domain owner." bitfld.long 0x0 31. "DOM15_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 29.--30. "DOM15_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 28. "DOM15_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 27. "DOM14_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 25.--26. "DOM14_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" newline bitfld.long 0x0 24. "DOM14_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 23. "DOM13_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 21.--22. "DOM13_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 20. "DOM13_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 19. "DOM12_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" newline bitfld.long 0x0 17.--18. "DOM12_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM12_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 15. "DOM11_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 13.--14. "DOM11_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 12. "DOM11_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" newline bitfld.long 0x0 11. "DOM10_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 9.--10. "DOM10_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM10_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 7. "DOM9_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 5.--6. "DOM9_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" newline bitfld.long 0x0 4. "DOM9_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" bitfld.long 0x0 3. "DOM8_LOCK,Domain permission control lock. Once this bit is set corresponding DOMx_PER and DOMx_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 1.--2. "DOM8_PER,Domain permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM8_EN,Domain permission control enable 1 : enable 0 : disable" "disable,enable" repeat.end repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x38 0x70 0xA8 0xE0 0x118 0x150 0x188 0x1C0 0x1F8 0x230 0x268 0x2A0 0x2D8 0x310 0x348 ) group.long ($2+0x310C)++0x3 line.long 0x0 "RGN_SEC_PER0_$1,This register is only used for resource manager to control secure access permission." bitfld.long 0x0 31. "DOM3_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM3_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM3_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM3_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM2_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM2_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM2_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM2_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM1_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM1_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM1_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM1_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM0_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM0_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM0_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM0_SEC_EN,Domain secure permission control enable" "0,1" repeat.end repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x38 0x70 0xA8 0xE0 0x118 0x150 0x188 0x1C0 0x1F8 0x230 0x268 0x2A0 0x2D8 0x310 0x348 ) group.long ($2+0x3110)++0x3 line.long 0x0 "RGN_SEC_PER1_$1,This register is only used for resource manager to control secure access permission." bitfld.long 0x0 31. "DOM7_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM7_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM7_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM7_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM6_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM6_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM6_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM6_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM5_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM5_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM5_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM5_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM4_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM4_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM4_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM4_SEC_EN,Domain secure permission control enable" "0,1" repeat.end repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x38 0x70 0xA8 0xE0 0x118 0x150 0x188 0x1C0 0x1F8 0x230 0x268 0x2A0 0x2D8 0x310 0x348 ) group.long ($2+0x3114)++0x3 line.long 0x0 "RGN_SEC_PER2_$1,This register is only used for resource manager to control secure access permission." bitfld.long 0x0 31. "DOM11_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM11_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM11_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM11_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM10_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM10_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM10_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM10_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM9_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM9_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM9_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM9_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM8_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM8_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM8_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM8_SEC_EN,Domain secure permission control enable" "0,1" repeat.end repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x38 0x70 0xA8 0xE0 0x118 0x150 0x188 0x1C0 0x1F8 0x230 0x268 0x2A0 0x2D8 0x310 0x348 ) group.long ($2+0x3118)++0x3 line.long 0x0 "RGN_SEC_PER3_$1,This register is only used for resource manager to control secure access permission." bitfld.long 0x0 31. "DOM15_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM15_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM15_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM15_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM14_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM14_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM14_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM14_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM13_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM13_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM13_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM13_SEC_EN,Domain secure permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM12_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM12_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM12_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM12_SEC_EN,Domain secure permission control enable" "0,1" repeat.end repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x38 0x70 0xA8 0xE0 0x118 0x150 0x188 0x1C0 0x1F8 0x230 0x268 0x2A0 0x2D8 0x310 0x348 ) group.long ($2+0x311C)++0x3 line.long 0x0 "RGN_PRI_PER0_$1,This register is only used for resource manager to control privileged access permission." bitfld.long 0x0 31. "DOM3_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM3_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM3_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM3_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM2_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM2_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM2_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM2_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM1_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM1_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM1_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM1_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM0_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM0_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM0_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM0_PRI_EN,Domain privileged permission control enable" "0,1" repeat.end repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x38 0x70 0xA8 0xE0 0x118 0x150 0x188 0x1C0 0x1F8 0x230 0x268 0x2A0 0x2D8 0x310 0x348 ) group.long ($2+0x3120)++0x3 line.long 0x0 "RGN_PRI_PER1_$1,This register is only used for resource manager to control privileged access permission." bitfld.long 0x0 31. "DOM7_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM7_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM7_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM7_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM6_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM6_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM6_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM6_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM5_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM5_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM5_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM5_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM4_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM4_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM4_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM4_PRI_EN,Domain privileged permission control enable" "0,1" repeat.end repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x38 0x70 0xA8 0xE0 0x118 0x150 0x188 0x1C0 0x1F8 0x230 0x268 0x2A0 0x2D8 0x310 0x348 ) group.long ($2+0x3124)++0x3 line.long 0x0 "RGN_PRI_PER2_$1,This register is only used for resource manager to control privileged access permission." bitfld.long 0x0 31. "DOM11_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM11_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM11_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM11_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM10_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM10_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM10_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM10_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM9_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM9_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM9_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM9_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM8_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM8_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM8_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM8_PRI_EN,Domain privileged permission control enable" "0,1" repeat.end repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x38 0x70 0xA8 0xE0 0x118 0x150 0x188 0x1C0 0x1F8 0x230 0x268 0x2A0 0x2D8 0x310 0x348 ) group.long ($2+0x3128)++0x3 line.long 0x0 "RGN_PRI_PER3_$1,This register is only used for resource manager to control privileged access permission." bitfld.long 0x0 31. "DOM15_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 27.--28. "DOM15_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 25.--26. "DOM15_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 24. "DOM15_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 23. "DOM14_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 19.--20. "DOM14_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 17.--18. "DOM14_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 16. "DOM14_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 15. "DOM13_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 11.--12. "DOM13_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 9.--10. "DOM13_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 8. "DOM13_PRI_EN,Domain privileged permission control enable" "0,1" newline bitfld.long 0x0 7. "DOM12_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM12_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM12_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 0. "DOM12_PRI_EN,Domain privileged permission control enable" "0,1" repeat.end repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x38 0x70 0xA8 0xE0 0x118 0x150 0x188 0x1C0 0x1F8 0x230 0x268 0x2A0 0x2D8 0x310 0x348 ) group.long ($2+0x312C)++0x3 line.long 0x0 "RGN_DOM_SEC_PER_$1,This register is only used for domain master to control secure access permission. When the domain master write this register. it only changes the secure permission for itself. When the domain master read this register. it gets.." bitfld.long 0x0 7. "DOM_LOCK,Domain secure access permission control lock. Once this bit is set corresponding DOMx_SEC_PER DOMx_NSE_PER DOMx_SEC_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM_NSE_PER,Domain non-secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM_SEC_PER,Domain secure access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" newline bitfld.long 0x0 0. "DOM_SEC_EN,Domain secure permission control enable" "0,1" repeat.end repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x38 0x70 0xA8 0xE0 0x118 0x150 0x188 0x1C0 0x1F8 0x230 0x268 0x2A0 0x2D8 0x310 0x348 ) group.long ($2+0x3130)++0x3 line.long 0x0 "RGN_DOM_PRI_PER_$1,This register is only used for domain master to control secure access permission. When the domain master write this register. it only changes the secure permission for itself. When the domain master read this register. it gets.." bitfld.long 0x0 7. "DOM_LOCK,Domain privileged access permission control lock. Once this bit is set corresponding DOMx_PRI_PER DOMx_USE_PER DOMx_PRI_EN and DOMx_LOCK can not be written again." "0,1" bitfld.long 0x0 3.--4. "DOM_USE_PER,Domain user access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" bitfld.long 0x0 1.--2. "DOM_PRI_PER,Domain privileged access permission 2'b11 : RW 2'b10 : WO 2'b01 : RO 2'b00 : NONE" "NONE,RO,WO,RW" newline bitfld.long 0x0 0. "DOM_PRI_EN,Domain privileged permission control enable" "0,1" repeat.end repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x38 0x70 0xA8 0xE0 0x118 0x150 0x188 0x1C0 0x1F8 0x230 0x268 0x2A0 0x2D8 0x310 0x348 ) group.long ($2+0x3134)++0x3 line.long 0x0 "RGN_DOM_ASSIGN_$1,Use to assign domain for accessing DOM_SEC_PER and DOM_PRI_PER register. Only resource manager. group manager and domain owner can access this register. For write. group manager must write its owen domain ID. otherwise write accessing.." hexmask.long.byte 0x0 0.--3. 1. "DID,accessing DOM_SEC_PER and DOM_PRI_PER register" repeat.end tree.end endif tree.end tree "RSTGEN (Reset Generation Controller)" sif (CORENAME()=="CORTEXR5F") tree "RSTGEN_RTC" base ad:0xF1890000 group.long 0x0++0x3 line.long 0x0 "RSTGEN_GLOBAL_RST_EN_0,rstgen global reset enble" bitfld.long 0x0 31. "GLB_RST_LOCK,rstgen global reset lock. 1: GLB_RST_EN locked. 0: GLB_RST_EN unlocked can be programmed. this bit can also lock itself" "GLB_RST_EN unlocked,GLB_RST_EN locked" newline hexmask.long.word 0x0 0.--10. 1. "GLB_RST_EN,rstgen global reset enable control bit0: self software reset enable bit1: sem reset enable bit2: dbg reset enable bit[10:3]: watchdog reset enable only lower bit are used according to watchdog number. For safe_ss bit[3] for wdt1 For sec_ss.." repeat 2. (list 0x0 0x1 )(list 0x0 0x8 ) group.long ($2+0x4)++0x3 line.long 0x0 "RSTGEN_CORE_RST_EN_$1,rstgen core reset enable" bitfld.long 0x0 31. "CORE_RST_LOCK,core reset lock. 1: WDT_RST_EN/DBG_RST_EN/SW_RST_EN locked. 0: WDT_RST_EN/DBG_RST_EN/SW_RST_EN unlocked can be programmed this bit can also lock itself" "WDT_RST_EN/DBG_RST_EN/SW_RST_EN unlocked,WDT_RST_EN/DBG_RST_EN/SW_RST_EN locked" rbitfld.long 0x0 30. "SW_RST_EN_STA,core software reset enable status: 1: enable active 0: enable not active" "enable not active,enable active" newline bitfld.long 0x0 2. "WDT_RST_EN,core watchdog reset enable the default reset value corresponding to the boot core is 1'b1 otherwise it's 1'b0 1: wdt reset core enable. 0: wdt reset core disable." "wdt reset core disable,wdt reset core enable" newline bitfld.long 0x0 1. "DBG_RST_EN,core debugger reset enable reserved" "0,1" bitfld.long 0x0 0. "SW_RST_EN,core software reset enable need to check the status in bit30 after set it 1: core software reset enable. 0: core software reset disable." "core software reset disable,core software reset enable" repeat.end repeat 2. (list 0x0 0x1 )(list 0x0 0x8 ) group.long ($2+0x8)++0x3 line.long 0x0 "RSTGEN_CORE_SW_RST_$1,rstgen core software reset" rbitfld.long 0x0 30. "CORE_RST_STA,core reset status. 1: core reset is released. 0: core under reset." "core under reset,core reset is released" newline rbitfld.long 0x0 29. "STATIC_RST_B_STA,core software static reset status polling this bit to check whether the register program is done" "0,1" newline bitfld.long 0x0 1. "AUTO_CLR_RST,core software auto clear reset write one to trigger reset and it can be auto cleared core will re-start automatically." "0,1" bitfld.long 0x0 0. "STATIC_RST_B,core software static reset need to check the status in bit29 after set it 0: reset 1: reset release" "reset,reset release" repeat.end group.long 0x44++0xB line.long 0x0 "RSTGEN_SW_SELF_RST,rstgen software global reset for itself" bitfld.long 0x0 31. "SW_GLB_RST_LOCK,software global reset lock. 1: SW_GLB_RST locked. 0: SW_GLB_RST unlocked can be programmed. this bit can also lock itself" "SW_GLB_RST unlocked,SW_GLB_RST locked" newline bitfld.long 0x0 0. "SW_GLB_RST,software global reset for rstgen itself. For RTC rstgen trigger this bit to reset RTC/SAF/AP. For SAF rstgen trigger this bit to reset SAF/AP. For AP rstgen trigger this bit to reset AP." "0,1" line.long 0x4 "RSTGEN_SW_OTH_RST,rstgen software global reset for other rstgen" bitfld.long 0x4 31. "SW_GLB_RST_LOCK,software global reset lock. 1: SW_GLB_RST locked. 0: SW_GLB_RST unlocked can be programmed." "SW_GLB_RST unlocked,SW_GLB_RST locked" newline bitfld.long 0x4 0. "SW_GLB_RST,software global reset for other rstgen for RTC rstgen this bit is reserved. for SAF rstgen trigger this bit to reset AP. for AP rstgen this bit is reserved." "0,1" line.long 0x8 "RSTGEN_RST_STA,record the reset root which cause global reset" hexmask.long 0x8 0.--31. 1. "RST_STA,reset root recording. bit[31:16]: reserved bit[15:0]: the last reset source. reset root recording. bit[15:4]: wdt reset bit[3]: dbg reset bit[2]: sem reset bit[1]: self sw reset bit[0]: pre sw reset For safe_ss bit[4] for wdt1 RST_STA can only.." repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) group.long ($2+0x50)++0x3 line.long 0x0 "RSTGEN_GENERAL_REG_$1,rstgen general registers" hexmask.long 0x0 0.--31. 1. "GENERAL_REG,general register in Rstgen can only be cleared by POR or software programming. For RTC it can only be cleared by power on reset or software programming. For SAF it can only be cleared by safe ss reset or software programming. For AP it.." repeat.end group.long 0x90++0x3 line.long 0x0 "RSTGEN_ISO_EN_0,rstgen ap secondary domain isolation control" bitfld.long 0x0 0. "ISO_B,isolation control bit 0: isolated 1: not isolated only used for AP domain. RSTGEN_ISO_EN_0: PCIE RSTGEN_ISO_EN_1: USB RSTGEN_ISO_EN_2: CPU1 RSTGEN_ISO_EN_3: GPU1 RSTGEN_ISO_EN_4: DDR" "PCIE,USB" repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) group.long ($2+0x100)++0x3 line.long 0x0 "RSTGEN_MODULE_RST_$1,rstgen module reset register" bitfld.long 0x0 31. "MODULE_RST_LOCK,module reset enable lock. 1: MODULE_RST_EN/MODULE_RST_N locked. 0: MODULE_RST_EN/MODULE_RST_N unlocked and can be programmed. this bit can also lock itself" "MODULE_RST_EN/MODULE_RST_N unlocked,MODULE_RST_EN/MODULE_RST_N locked" rbitfld.long 0x0 30. "MODULE_RST_STA,module reset status. 1: module reset is released. 0: module is under reset. it is recommened to check this bit after software reset released by software and before any operation to the corresponding IP." "module is under reset,module reset is released" newline bitfld.long 0x0 1. "MODULE_RST_EN,module reset enable for each ip. need to set this field before set MODULE_RST_N and please read it back to make sure it is set correctly before set MODULE_RST_N. can refer to Reset table for the reset index information." "0,1" newline bitfld.long 0x0 0. "MODULE_RST_N,module reset for each ip. can refer to Reset table for the reset index information. 0: module under reset. 1: module reset released. After set this bit please check MODULE_RST_STA to check whether it is affective." "module under reset,module reset released" repeat.end tree.end tree "RSTGEN_AP" base ad:0xF8400000 group.long 0x0++0x3 line.long 0x0 "RSTGEN_GLOBAL_RST_EN_0,rstgen global reset enble" bitfld.long 0x0 31. "GLB_RST_LOCK,rstgen global reset lock. 1: GLB_RST_EN locked. 0: GLB_RST_EN unlocked can be programmed. this bit can also lock itself" "GLB_RST_EN unlocked,GLB_RST_EN locked" newline hexmask.long.word 0x0 0.--10. 1. "GLB_RST_EN,rstgen global reset enable control bit0: self software reset enable bit1: sem reset enable bit2: dbg reset enable bit[10:3]: watchdog reset enable only lower bit are used according to watchdog number. For safe_ss bit[3] for wdt1 For sec_ss.." repeat 2. (list 0x0 0x1 )(list 0x0 0x8 ) group.long ($2+0x4)++0x3 line.long 0x0 "RSTGEN_CORE_RST_EN_$1,rstgen core reset enable" bitfld.long 0x0 31. "CORE_RST_LOCK,core reset lock. 1: WDT_RST_EN/DBG_RST_EN/SW_RST_EN locked. 0: WDT_RST_EN/DBG_RST_EN/SW_RST_EN unlocked can be programmed this bit can also lock itself" "WDT_RST_EN/DBG_RST_EN/SW_RST_EN unlocked,WDT_RST_EN/DBG_RST_EN/SW_RST_EN locked" rbitfld.long 0x0 30. "SW_RST_EN_STA,core software reset enable status: 1: enable active 0: enable not active" "enable not active,enable active" newline bitfld.long 0x0 2. "WDT_RST_EN,core watchdog reset enable the default reset value corresponding to the boot core is 1'b1 otherwise it's 1'b0 1: wdt reset core enable. 0: wdt reset core disable." "wdt reset core disable,wdt reset core enable" newline bitfld.long 0x0 1. "DBG_RST_EN,core debugger reset enable reserved" "0,1" bitfld.long 0x0 0. "SW_RST_EN,core software reset enable need to check the status in bit30 after set it 1: core software reset enable. 0: core software reset disable." "core software reset disable,core software reset enable" repeat.end repeat 2. (list 0x0 0x1 )(list 0x0 0x8 ) group.long ($2+0x8)++0x3 line.long 0x0 "RSTGEN_CORE_SW_RST_$1,rstgen core software reset" rbitfld.long 0x0 30. "CORE_RST_STA,core reset status. 1: core reset is released. 0: core under reset." "core under reset,core reset is released" newline rbitfld.long 0x0 29. "STATIC_RST_B_STA,core software static reset status polling this bit to check whether the register program is done" "0,1" newline bitfld.long 0x0 1. "AUTO_CLR_RST,core software auto clear reset write one to trigger reset and it can be auto cleared core will re-start automatically." "0,1" bitfld.long 0x0 0. "STATIC_RST_B,core software static reset need to check the status in bit29 after set it 0: reset 1: reset release" "reset,reset release" repeat.end group.long 0x44++0xB line.long 0x0 "RSTGEN_SW_SELF_RST,rstgen software global reset for itself" bitfld.long 0x0 31. "SW_GLB_RST_LOCK,software global reset lock. 1: SW_GLB_RST locked. 0: SW_GLB_RST unlocked can be programmed. this bit can also lock itself" "SW_GLB_RST unlocked,SW_GLB_RST locked" newline bitfld.long 0x0 0. "SW_GLB_RST,software global reset for rstgen itself. For RTC rstgen trigger this bit to reset RTC/SAF/AP. For SAF rstgen trigger this bit to reset SAF/AP. For AP rstgen trigger this bit to reset AP." "0,1" line.long 0x4 "RSTGEN_SW_OTH_RST,rstgen software global reset for other rstgen" bitfld.long 0x4 31. "SW_GLB_RST_LOCK,software global reset lock. 1: SW_GLB_RST locked. 0: SW_GLB_RST unlocked can be programmed." "SW_GLB_RST unlocked,SW_GLB_RST locked" newline bitfld.long 0x4 0. "SW_GLB_RST,software global reset for other rstgen for RTC rstgen this bit is reserved. for SAF rstgen trigger this bit to reset AP. for AP rstgen this bit is reserved." "0,1" line.long 0x8 "RSTGEN_RST_STA,record the reset root which cause global reset" hexmask.long 0x8 0.--31. 1. "RST_STA,reset root recording. bit[31:16]: reserved bit[15:0]: the last reset source. reset root recording. bit[15:4]: wdt reset bit[3]: dbg reset bit[2]: sem reset bit[1]: self sw reset bit[0]: pre sw reset For safe_ss bit[4] for wdt1 RST_STA can only.." repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) group.long ($2+0x50)++0x3 line.long 0x0 "RSTGEN_GENERAL_REG_$1,rstgen general registers" hexmask.long 0x0 0.--31. 1. "GENERAL_REG,general register in Rstgen can only be cleared by POR or software programming. For RTC it can only be cleared by power on reset or software programming. For SAF it can only be cleared by safe ss reset or software programming. For AP it.." repeat.end group.long 0x90++0x3 line.long 0x0 "RSTGEN_ISO_EN_0,rstgen ap secondary domain isolation control" bitfld.long 0x0 0. "ISO_B,isolation control bit 0: isolated 1: not isolated only used for AP domain. RSTGEN_ISO_EN_0: PCIE RSTGEN_ISO_EN_1: USB RSTGEN_ISO_EN_2: CPU1 RSTGEN_ISO_EN_3: GPU1 RSTGEN_ISO_EN_4: DDR" "PCIE,USB" repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) group.long ($2+0x100)++0x3 line.long 0x0 "RSTGEN_MODULE_RST_$1,rstgen module reset register" bitfld.long 0x0 31. "MODULE_RST_LOCK,module reset enable lock. 1: MODULE_RST_EN/MODULE_RST_N locked. 0: MODULE_RST_EN/MODULE_RST_N unlocked and can be programmed. this bit can also lock itself" "MODULE_RST_EN/MODULE_RST_N unlocked,MODULE_RST_EN/MODULE_RST_N locked" rbitfld.long 0x0 30. "MODULE_RST_STA,module reset status. 1: module reset is released. 0: module is under reset. it is recommened to check this bit after software reset released by software and before any operation to the corresponding IP." "module is under reset,module reset is released" newline bitfld.long 0x0 1. "MODULE_RST_EN,module reset enable for each ip. need to set this field before set MODULE_RST_N and please read it back to make sure it is set correctly before set MODULE_RST_N. can refer to Reset table for the reset index information." "0,1" newline bitfld.long 0x0 0. "MODULE_RST_N,module reset for each ip. can refer to Reset table for the reset index information. 0: module under reset. 1: module reset released. After set this bit please check MODULE_RST_STA to check whether it is affective." "module under reset,module reset released" repeat.end tree.end tree "RSTGEN_SAFETY" base ad:0xFC400000 group.long 0x0++0x3 line.long 0x0 "RSTGEN_GLOBAL_RST_EN_0,rstgen global reset enble" bitfld.long 0x0 31. "GLB_RST_LOCK,rstgen global reset lock. 1: GLB_RST_EN locked. 0: GLB_RST_EN unlocked can be programmed. this bit can also lock itself" "GLB_RST_EN unlocked,GLB_RST_EN locked" newline hexmask.long.word 0x0 0.--10. 1. "GLB_RST_EN,rstgen global reset enable control bit0: self software reset enable bit1: sem reset enable bit2: dbg reset enable bit[10:3]: watchdog reset enable only lower bit are used according to watchdog number. For safe_ss bit[3] for wdt1 For sec_ss.." repeat 2. (list 0x0 0x1 )(list 0x0 0x8 ) group.long ($2+0x4)++0x3 line.long 0x0 "RSTGEN_CORE_RST_EN_$1,rstgen core reset enable" bitfld.long 0x0 31. "CORE_RST_LOCK,core reset lock. 1: WDT_RST_EN/DBG_RST_EN/SW_RST_EN locked. 0: WDT_RST_EN/DBG_RST_EN/SW_RST_EN unlocked can be programmed this bit can also lock itself" "WDT_RST_EN/DBG_RST_EN/SW_RST_EN unlocked,WDT_RST_EN/DBG_RST_EN/SW_RST_EN locked" rbitfld.long 0x0 30. "SW_RST_EN_STA,core software reset enable status: 1: enable active 0: enable not active" "enable not active,enable active" newline bitfld.long 0x0 2. "WDT_RST_EN,core watchdog reset enable the default reset value corresponding to the boot core is 1'b1 otherwise it's 1'b0 1: wdt reset core enable. 0: wdt reset core disable." "wdt reset core disable,wdt reset core enable" newline bitfld.long 0x0 1. "DBG_RST_EN,core debugger reset enable reserved" "0,1" bitfld.long 0x0 0. "SW_RST_EN,core software reset enable need to check the status in bit30 after set it 1: core software reset enable. 0: core software reset disable." "core software reset disable,core software reset enable" repeat.end repeat 2. (list 0x0 0x1 )(list 0x0 0x8 ) group.long ($2+0x8)++0x3 line.long 0x0 "RSTGEN_CORE_SW_RST_$1,rstgen core software reset" rbitfld.long 0x0 30. "CORE_RST_STA,core reset status. 1: core reset is released. 0: core under reset." "core under reset,core reset is released" newline rbitfld.long 0x0 29. "STATIC_RST_B_STA,core software static reset status polling this bit to check whether the register program is done" "0,1" newline bitfld.long 0x0 1. "AUTO_CLR_RST,core software auto clear reset write one to trigger reset and it can be auto cleared core will re-start automatically." "0,1" bitfld.long 0x0 0. "STATIC_RST_B,core software static reset need to check the status in bit29 after set it 0: reset 1: reset release" "reset,reset release" repeat.end group.long 0x44++0xB line.long 0x0 "RSTGEN_SW_SELF_RST,rstgen software global reset for itself" bitfld.long 0x0 31. "SW_GLB_RST_LOCK,software global reset lock. 1: SW_GLB_RST locked. 0: SW_GLB_RST unlocked can be programmed. this bit can also lock itself" "SW_GLB_RST unlocked,SW_GLB_RST locked" newline bitfld.long 0x0 0. "SW_GLB_RST,software global reset for rstgen itself. For RTC rstgen trigger this bit to reset RTC/SAF/AP. For SAF rstgen trigger this bit to reset SAF/AP. For AP rstgen trigger this bit to reset AP." "0,1" line.long 0x4 "RSTGEN_SW_OTH_RST,rstgen software global reset for other rstgen" bitfld.long 0x4 31. "SW_GLB_RST_LOCK,software global reset lock. 1: SW_GLB_RST locked. 0: SW_GLB_RST unlocked can be programmed." "SW_GLB_RST unlocked,SW_GLB_RST locked" newline bitfld.long 0x4 0. "SW_GLB_RST,software global reset for other rstgen for RTC rstgen this bit is reserved. for SAF rstgen trigger this bit to reset AP. for AP rstgen this bit is reserved." "0,1" line.long 0x8 "RSTGEN_RST_STA,record the reset root which cause global reset" hexmask.long 0x8 0.--31. 1. "RST_STA,reset root recording. bit[31:16]: reserved bit[15:0]: the last reset source. reset root recording. bit[15:4]: wdt reset bit[3]: dbg reset bit[2]: sem reset bit[1]: self sw reset bit[0]: pre sw reset For safe_ss bit[4] for wdt1 RST_STA can only.." repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) group.long ($2+0x50)++0x3 line.long 0x0 "RSTGEN_GENERAL_REG_$1,rstgen general registers" hexmask.long 0x0 0.--31. 1. "GENERAL_REG,general register in Rstgen can only be cleared by POR or software programming. For RTC it can only be cleared by power on reset or software programming. For SAF it can only be cleared by safe ss reset or software programming. For AP it.." repeat.end group.long 0x90++0x3 line.long 0x0 "RSTGEN_ISO_EN_0,rstgen ap secondary domain isolation control" bitfld.long 0x0 0. "ISO_B,isolation control bit 0: isolated 1: not isolated only used for AP domain. RSTGEN_ISO_EN_0: PCIE RSTGEN_ISO_EN_1: USB RSTGEN_ISO_EN_2: CPU1 RSTGEN_ISO_EN_3: GPU1 RSTGEN_ISO_EN_4: DDR" "PCIE,USB" repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) group.long ($2+0x100)++0x3 line.long 0x0 "RSTGEN_MODULE_RST_$1,rstgen module reset register" bitfld.long 0x0 31. "MODULE_RST_LOCK,module reset enable lock. 1: MODULE_RST_EN/MODULE_RST_N locked. 0: MODULE_RST_EN/MODULE_RST_N unlocked and can be programmed. this bit can also lock itself" "MODULE_RST_EN/MODULE_RST_N unlocked,MODULE_RST_EN/MODULE_RST_N locked" rbitfld.long 0x0 30. "MODULE_RST_STA,module reset status. 1: module reset is released. 0: module is under reset. it is recommened to check this bit after software reset released by software and before any operation to the corresponding IP." "module is under reset,module reset is released" newline bitfld.long 0x0 1. "MODULE_RST_EN,module reset enable for each ip. need to set this field before set MODULE_RST_N and please read it back to make sure it is set correctly before set MODULE_RST_N. can refer to Reset table for the reset index information." "0,1" newline bitfld.long 0x0 0. "MODULE_RST_N,module reset for each ip. can refer to Reset table for the reset index information. 0: module under reset. 1: module reset released. After set this bit please check MODULE_RST_STA to check whether it is affective." "module under reset,module reset released" repeat.end tree.end elif (CORENAME()=="CORTEXA55") tree "RSTGEN_RTC" base ad:0x31890000 group.long 0x0++0x3 line.long 0x0 "RSTGEN_GLOBAL_RST_EN_0,rstgen global reset enble" bitfld.long 0x0 31. "GLB_RST_LOCK,rstgen global reset lock. 1: GLB_RST_EN locked. 0: GLB_RST_EN unlocked can be programmed. this bit can also lock itself" "GLB_RST_EN unlocked,GLB_RST_EN locked" newline hexmask.long.word 0x0 0.--10. 1. "GLB_RST_EN,rstgen global reset enable control bit0: self software reset enable bit1: sem reset enable bit2: dbg reset enable bit[10:3]: watchdog reset enable only lower bit are used according to watchdog number. For safe_ss bit[3] for wdt1 For sec_ss.." repeat 2. (list 0x0 0x1 )(list 0x0 0x8 ) group.long ($2+0x4)++0x3 line.long 0x0 "RSTGEN_CORE_RST_EN_$1,rstgen core reset enable" bitfld.long 0x0 31. "CORE_RST_LOCK,core reset lock. 1: WDT_RST_EN/DBG_RST_EN/SW_RST_EN locked. 0: WDT_RST_EN/DBG_RST_EN/SW_RST_EN unlocked can be programmed this bit can also lock itself" "WDT_RST_EN/DBG_RST_EN/SW_RST_EN unlocked,WDT_RST_EN/DBG_RST_EN/SW_RST_EN locked" rbitfld.long 0x0 30. "SW_RST_EN_STA,core software reset enable status: 1: enable active 0: enable not active" "enable not active,enable active" newline bitfld.long 0x0 2. "WDT_RST_EN,core watchdog reset enable the default reset value corresponding to the boot core is 1'b1 otherwise it's 1'b0 1: wdt reset core enable. 0: wdt reset core disable." "wdt reset core disable,wdt reset core enable" newline bitfld.long 0x0 1. "DBG_RST_EN,core debugger reset enable reserved" "0,1" bitfld.long 0x0 0. "SW_RST_EN,core software reset enable need to check the status in bit30 after set it 1: core software reset enable. 0: core software reset disable." "core software reset disable,core software reset enable" repeat.end repeat 2. (list 0x0 0x1 )(list 0x0 0x8 ) group.long ($2+0x8)++0x3 line.long 0x0 "RSTGEN_CORE_SW_RST_$1,rstgen core software reset" rbitfld.long 0x0 30. "CORE_RST_STA,core reset status. 1: core reset is released. 0: core under reset." "core under reset,core reset is released" newline rbitfld.long 0x0 29. "STATIC_RST_B_STA,core software static reset status polling this bit to check whether the register program is done" "0,1" newline bitfld.long 0x0 1. "AUTO_CLR_RST,core software auto clear reset write one to trigger reset and it can be auto cleared core will re-start automatically." "0,1" bitfld.long 0x0 0. "STATIC_RST_B,core software static reset need to check the status in bit29 after set it 0: reset 1: reset release" "reset,reset release" repeat.end group.long 0x44++0xB line.long 0x0 "RSTGEN_SW_SELF_RST,rstgen software global reset for itself" bitfld.long 0x0 31. "SW_GLB_RST_LOCK,software global reset lock. 1: SW_GLB_RST locked. 0: SW_GLB_RST unlocked can be programmed. this bit can also lock itself" "SW_GLB_RST unlocked,SW_GLB_RST locked" newline bitfld.long 0x0 0. "SW_GLB_RST,software global reset for rstgen itself. For RTC rstgen trigger this bit to reset RTC/SAF/AP. For SAF rstgen trigger this bit to reset SAF/AP. For AP rstgen trigger this bit to reset AP." "0,1" line.long 0x4 "RSTGEN_SW_OTH_RST,rstgen software global reset for other rstgen" bitfld.long 0x4 31. "SW_GLB_RST_LOCK,software global reset lock. 1: SW_GLB_RST locked. 0: SW_GLB_RST unlocked can be programmed." "SW_GLB_RST unlocked,SW_GLB_RST locked" newline bitfld.long 0x4 0. "SW_GLB_RST,software global reset for other rstgen for RTC rstgen this bit is reserved. for SAF rstgen trigger this bit to reset AP. for AP rstgen this bit is reserved." "0,1" line.long 0x8 "RSTGEN_RST_STA,record the reset root which cause global reset" hexmask.long 0x8 0.--31. 1. "RST_STA,reset root recording. bit[31:16]: reserved bit[15:0]: the last reset source. reset root recording. bit[15:4]: wdt reset bit[3]: dbg reset bit[2]: sem reset bit[1]: self sw reset bit[0]: pre sw reset For safe_ss bit[4] for wdt1 RST_STA can only.." repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) group.long ($2+0x50)++0x3 line.long 0x0 "RSTGEN_GENERAL_REG_$1,rstgen general registers" hexmask.long 0x0 0.--31. 1. "GENERAL_REG,general register in Rstgen can only be cleared by POR or software programming. For RTC it can only be cleared by power on reset or software programming. For SAF it can only be cleared by safe ss reset or software programming. For AP it.." repeat.end group.long 0x90++0x3 line.long 0x0 "RSTGEN_ISO_EN_0,rstgen ap secondary domain isolation control" bitfld.long 0x0 0. "ISO_B,isolation control bit 0: isolated 1: not isolated only used for AP domain. RSTGEN_ISO_EN_0: PCIE RSTGEN_ISO_EN_1: USB RSTGEN_ISO_EN_2: CPU1 RSTGEN_ISO_EN_3: GPU1 RSTGEN_ISO_EN_4: DDR" "PCIE,USB" repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) group.long ($2+0x100)++0x3 line.long 0x0 "RSTGEN_MODULE_RST_$1,rstgen module reset register" bitfld.long 0x0 31. "MODULE_RST_LOCK,module reset enable lock. 1: MODULE_RST_EN/MODULE_RST_N locked. 0: MODULE_RST_EN/MODULE_RST_N unlocked and can be programmed. this bit can also lock itself" "MODULE_RST_EN/MODULE_RST_N unlocked,MODULE_RST_EN/MODULE_RST_N locked" rbitfld.long 0x0 30. "MODULE_RST_STA,module reset status. 1: module reset is released. 0: module is under reset. it is recommened to check this bit after software reset released by software and before any operation to the corresponding IP." "module is under reset,module reset is released" newline bitfld.long 0x0 1. "MODULE_RST_EN,module reset enable for each ip. need to set this field before set MODULE_RST_N and please read it back to make sure it is set correctly before set MODULE_RST_N. can refer to Reset table for the reset index information." "0,1" newline bitfld.long 0x0 0. "MODULE_RST_N,module reset for each ip. can refer to Reset table for the reset index information. 0: module under reset. 1: module reset released. After set this bit please check MODULE_RST_STA to check whether it is affective." "module under reset,module reset released" repeat.end tree.end tree "RSTGEN_AP" base ad:0x38400000 group.long 0x0++0x3 line.long 0x0 "RSTGEN_GLOBAL_RST_EN_0,rstgen global reset enble" bitfld.long 0x0 31. "GLB_RST_LOCK,rstgen global reset lock. 1: GLB_RST_EN locked. 0: GLB_RST_EN unlocked can be programmed. this bit can also lock itself" "GLB_RST_EN unlocked,GLB_RST_EN locked" newline hexmask.long.word 0x0 0.--10. 1. "GLB_RST_EN,rstgen global reset enable control bit0: self software reset enable bit1: sem reset enable bit2: dbg reset enable bit[10:3]: watchdog reset enable only lower bit are used according to watchdog number. For safe_ss bit[3] for wdt1 For sec_ss.." repeat 2. (list 0x0 0x1 )(list 0x0 0x8 ) group.long ($2+0x4)++0x3 line.long 0x0 "RSTGEN_CORE_RST_EN_$1,rstgen core reset enable" bitfld.long 0x0 31. "CORE_RST_LOCK,core reset lock. 1: WDT_RST_EN/DBG_RST_EN/SW_RST_EN locked. 0: WDT_RST_EN/DBG_RST_EN/SW_RST_EN unlocked can be programmed this bit can also lock itself" "WDT_RST_EN/DBG_RST_EN/SW_RST_EN unlocked,WDT_RST_EN/DBG_RST_EN/SW_RST_EN locked" rbitfld.long 0x0 30. "SW_RST_EN_STA,core software reset enable status: 1: enable active 0: enable not active" "enable not active,enable active" newline bitfld.long 0x0 2. "WDT_RST_EN,core watchdog reset enable the default reset value corresponding to the boot core is 1'b1 otherwise it's 1'b0 1: wdt reset core enable. 0: wdt reset core disable." "wdt reset core disable,wdt reset core enable" newline bitfld.long 0x0 1. "DBG_RST_EN,core debugger reset enable reserved" "0,1" bitfld.long 0x0 0. "SW_RST_EN,core software reset enable need to check the status in bit30 after set it 1: core software reset enable. 0: core software reset disable." "core software reset disable,core software reset enable" repeat.end repeat 2. (list 0x0 0x1 )(list 0x0 0x8 ) group.long ($2+0x8)++0x3 line.long 0x0 "RSTGEN_CORE_SW_RST_$1,rstgen core software reset" rbitfld.long 0x0 30. "CORE_RST_STA,core reset status. 1: core reset is released. 0: core under reset." "core under reset,core reset is released" newline rbitfld.long 0x0 29. "STATIC_RST_B_STA,core software static reset status polling this bit to check whether the register program is done" "0,1" newline bitfld.long 0x0 1. "AUTO_CLR_RST,core software auto clear reset write one to trigger reset and it can be auto cleared core will re-start automatically." "0,1" bitfld.long 0x0 0. "STATIC_RST_B,core software static reset need to check the status in bit29 after set it 0: reset 1: reset release" "reset,reset release" repeat.end group.long 0x44++0xB line.long 0x0 "RSTGEN_SW_SELF_RST,rstgen software global reset for itself" bitfld.long 0x0 31. "SW_GLB_RST_LOCK,software global reset lock. 1: SW_GLB_RST locked. 0: SW_GLB_RST unlocked can be programmed. this bit can also lock itself" "SW_GLB_RST unlocked,SW_GLB_RST locked" newline bitfld.long 0x0 0. "SW_GLB_RST,software global reset for rstgen itself. For RTC rstgen trigger this bit to reset RTC/SAF/AP. For SAF rstgen trigger this bit to reset SAF/AP. For AP rstgen trigger this bit to reset AP." "0,1" line.long 0x4 "RSTGEN_SW_OTH_RST,rstgen software global reset for other rstgen" bitfld.long 0x4 31. "SW_GLB_RST_LOCK,software global reset lock. 1: SW_GLB_RST locked. 0: SW_GLB_RST unlocked can be programmed." "SW_GLB_RST unlocked,SW_GLB_RST locked" newline bitfld.long 0x4 0. "SW_GLB_RST,software global reset for other rstgen for RTC rstgen this bit is reserved. for SAF rstgen trigger this bit to reset AP. for AP rstgen this bit is reserved." "0,1" line.long 0x8 "RSTGEN_RST_STA,record the reset root which cause global reset" hexmask.long 0x8 0.--31. 1. "RST_STA,reset root recording. bit[31:16]: reserved bit[15:0]: the last reset source. reset root recording. bit[15:4]: wdt reset bit[3]: dbg reset bit[2]: sem reset bit[1]: self sw reset bit[0]: pre sw reset For safe_ss bit[4] for wdt1 RST_STA can only.." repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) group.long ($2+0x50)++0x3 line.long 0x0 "RSTGEN_GENERAL_REG_$1,rstgen general registers" hexmask.long 0x0 0.--31. 1. "GENERAL_REG,general register in Rstgen can only be cleared by POR or software programming. For RTC it can only be cleared by power on reset or software programming. For SAF it can only be cleared by safe ss reset or software programming. For AP it.." repeat.end group.long 0x90++0x3 line.long 0x0 "RSTGEN_ISO_EN_0,rstgen ap secondary domain isolation control" bitfld.long 0x0 0. "ISO_B,isolation control bit 0: isolated 1: not isolated only used for AP domain. RSTGEN_ISO_EN_0: PCIE RSTGEN_ISO_EN_1: USB RSTGEN_ISO_EN_2: CPU1 RSTGEN_ISO_EN_3: GPU1 RSTGEN_ISO_EN_4: DDR" "PCIE,USB" repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) group.long ($2+0x100)++0x3 line.long 0x0 "RSTGEN_MODULE_RST_$1,rstgen module reset register" bitfld.long 0x0 31. "MODULE_RST_LOCK,module reset enable lock. 1: MODULE_RST_EN/MODULE_RST_N locked. 0: MODULE_RST_EN/MODULE_RST_N unlocked and can be programmed. this bit can also lock itself" "MODULE_RST_EN/MODULE_RST_N unlocked,MODULE_RST_EN/MODULE_RST_N locked" rbitfld.long 0x0 30. "MODULE_RST_STA,module reset status. 1: module reset is released. 0: module is under reset. it is recommened to check this bit after software reset released by software and before any operation to the corresponding IP." "module is under reset,module reset is released" newline bitfld.long 0x0 1. "MODULE_RST_EN,module reset enable for each ip. need to set this field before set MODULE_RST_N and please read it back to make sure it is set correctly before set MODULE_RST_N. can refer to Reset table for the reset index information." "0,1" newline bitfld.long 0x0 0. "MODULE_RST_N,module reset for each ip. can refer to Reset table for the reset index information. 0: module under reset. 1: module reset released. After set this bit please check MODULE_RST_STA to check whether it is affective." "module under reset,module reset released" repeat.end tree.end tree "RSTGEN_SAFETY" base ad:0x3C400000 group.long 0x0++0x3 line.long 0x0 "RSTGEN_GLOBAL_RST_EN_0,rstgen global reset enble" bitfld.long 0x0 31. "GLB_RST_LOCK,rstgen global reset lock. 1: GLB_RST_EN locked. 0: GLB_RST_EN unlocked can be programmed. this bit can also lock itself" "GLB_RST_EN unlocked,GLB_RST_EN locked" newline hexmask.long.word 0x0 0.--10. 1. "GLB_RST_EN,rstgen global reset enable control bit0: self software reset enable bit1: sem reset enable bit2: dbg reset enable bit[10:3]: watchdog reset enable only lower bit are used according to watchdog number. For safe_ss bit[3] for wdt1 For sec_ss.." repeat 2. (list 0x0 0x1 )(list 0x0 0x8 ) group.long ($2+0x4)++0x3 line.long 0x0 "RSTGEN_CORE_RST_EN_$1,rstgen core reset enable" bitfld.long 0x0 31. "CORE_RST_LOCK,core reset lock. 1: WDT_RST_EN/DBG_RST_EN/SW_RST_EN locked. 0: WDT_RST_EN/DBG_RST_EN/SW_RST_EN unlocked can be programmed this bit can also lock itself" "WDT_RST_EN/DBG_RST_EN/SW_RST_EN unlocked,WDT_RST_EN/DBG_RST_EN/SW_RST_EN locked" rbitfld.long 0x0 30. "SW_RST_EN_STA,core software reset enable status: 1: enable active 0: enable not active" "enable not active,enable active" newline bitfld.long 0x0 2. "WDT_RST_EN,core watchdog reset enable the default reset value corresponding to the boot core is 1'b1 otherwise it's 1'b0 1: wdt reset core enable. 0: wdt reset core disable." "wdt reset core disable,wdt reset core enable" newline bitfld.long 0x0 1. "DBG_RST_EN,core debugger reset enable reserved" "0,1" bitfld.long 0x0 0. "SW_RST_EN,core software reset enable need to check the status in bit30 after set it 1: core software reset enable. 0: core software reset disable." "core software reset disable,core software reset enable" repeat.end repeat 2. (list 0x0 0x1 )(list 0x0 0x8 ) group.long ($2+0x8)++0x3 line.long 0x0 "RSTGEN_CORE_SW_RST_$1,rstgen core software reset" rbitfld.long 0x0 30. "CORE_RST_STA,core reset status. 1: core reset is released. 0: core under reset." "core under reset,core reset is released" newline rbitfld.long 0x0 29. "STATIC_RST_B_STA,core software static reset status polling this bit to check whether the register program is done" "0,1" newline bitfld.long 0x0 1. "AUTO_CLR_RST,core software auto clear reset write one to trigger reset and it can be auto cleared core will re-start automatically." "0,1" bitfld.long 0x0 0. "STATIC_RST_B,core software static reset need to check the status in bit29 after set it 0: reset 1: reset release" "reset,reset release" repeat.end group.long 0x44++0xB line.long 0x0 "RSTGEN_SW_SELF_RST,rstgen software global reset for itself" bitfld.long 0x0 31. "SW_GLB_RST_LOCK,software global reset lock. 1: SW_GLB_RST locked. 0: SW_GLB_RST unlocked can be programmed. this bit can also lock itself" "SW_GLB_RST unlocked,SW_GLB_RST locked" newline bitfld.long 0x0 0. "SW_GLB_RST,software global reset for rstgen itself. For RTC rstgen trigger this bit to reset RTC/SAF/AP. For SAF rstgen trigger this bit to reset SAF/AP. For AP rstgen trigger this bit to reset AP." "0,1" line.long 0x4 "RSTGEN_SW_OTH_RST,rstgen software global reset for other rstgen" bitfld.long 0x4 31. "SW_GLB_RST_LOCK,software global reset lock. 1: SW_GLB_RST locked. 0: SW_GLB_RST unlocked can be programmed." "SW_GLB_RST unlocked,SW_GLB_RST locked" newline bitfld.long 0x4 0. "SW_GLB_RST,software global reset for other rstgen for RTC rstgen this bit is reserved. for SAF rstgen trigger this bit to reset AP. for AP rstgen this bit is reserved." "0,1" line.long 0x8 "RSTGEN_RST_STA,record the reset root which cause global reset" hexmask.long 0x8 0.--31. 1. "RST_STA,reset root recording. bit[31:16]: reserved bit[15:0]: the last reset source. reset root recording. bit[15:4]: wdt reset bit[3]: dbg reset bit[2]: sem reset bit[1]: self sw reset bit[0]: pre sw reset For safe_ss bit[4] for wdt1 RST_STA can only.." repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) group.long ($2+0x50)++0x3 line.long 0x0 "RSTGEN_GENERAL_REG_$1,rstgen general registers" hexmask.long 0x0 0.--31. 1. "GENERAL_REG,general register in Rstgen can only be cleared by POR or software programming. For RTC it can only be cleared by power on reset or software programming. For SAF it can only be cleared by safe ss reset or software programming. For AP it.." repeat.end group.long 0x90++0x3 line.long 0x0 "RSTGEN_ISO_EN_0,rstgen ap secondary domain isolation control" bitfld.long 0x0 0. "ISO_B,isolation control bit 0: isolated 1: not isolated only used for AP domain. RSTGEN_ISO_EN_0: PCIE RSTGEN_ISO_EN_1: USB RSTGEN_ISO_EN_2: CPU1 RSTGEN_ISO_EN_3: GPU1 RSTGEN_ISO_EN_4: DDR" "PCIE,USB" repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) group.long ($2+0x100)++0x3 line.long 0x0 "RSTGEN_MODULE_RST_$1,rstgen module reset register" bitfld.long 0x0 31. "MODULE_RST_LOCK,module reset enable lock. 1: MODULE_RST_EN/MODULE_RST_N locked. 0: MODULE_RST_EN/MODULE_RST_N unlocked and can be programmed. this bit can also lock itself" "MODULE_RST_EN/MODULE_RST_N unlocked,MODULE_RST_EN/MODULE_RST_N locked" rbitfld.long 0x0 30. "MODULE_RST_STA,module reset status. 1: module reset is released. 0: module is under reset. it is recommened to check this bit after software reset released by software and before any operation to the corresponding IP." "module is under reset,module reset is released" newline bitfld.long 0x0 1. "MODULE_RST_EN,module reset enable for each ip. need to set this field before set MODULE_RST_N and please read it back to make sure it is set correctly before set MODULE_RST_N. can refer to Reset table for the reset index information." "0,1" newline bitfld.long 0x0 0. "MODULE_RST_N,module reset for each ip. can refer to Reset table for the reset index information. 0: module under reset. 1: module reset released. After set this bit please check MODULE_RST_STA to check whether it is affective." "module under reset,module reset released" repeat.end tree.end endif tree.end tree "RTC (Real-Time Clock)" sif (CORENAME()=="CORTEXR5F") repeat 2. (increment 1. 1.) (list ad:0xF1800000 ad:0xF1810000) tree "RTC$1" base $2 group.long 0x0++0x23 line.long 0x0 "SEC_RTC_CTRL,secure RTC controller" bitfld.long 0x0 31. "LOCK,sticky bit once set the rtc_enable secure_enable privilege_enable can't be changed" "0,1" newline bitfld.long 0x0 2. "PRIVILEGE_ENABLE,secure enable 1- privileged access only 0- both privileged/user access is allowed" "both privileged/user access is allowed,privileged access only" bitfld.long 0x0 1. "SECURE_ENABLE,secure enable 1- secure access only 0- both secure/nonsecure access is allowed" "both secure/nonsecure access is allowed,secure access only" newline bitfld.long 0x0 0. "RTC_ENABLE,RTC enable" "0,1" line.long 0x4 "RTC_H,48bit- RTC high register" hexmask.long.word 0x4 0.--15. 1. "RTC_H,high bit" line.long 0x8 "RTC_L,48bit- RTC low register" hexmask.long 0x8 0.--31. 1. "RTC_L,low bit" line.long 0xC "AUTO_ADJUST,RTC auto adjust function controller" hexmask.long.byte 0xC 16.--23. 1. "PERIOD,define the adjust period when happen" newline hexmask.long.byte 0xC 8.--15. 1. "CYCLE,auto adjust cycle amount of cycles to be adjusted" newline bitfld.long 0xC 1. "ADJUST_DIRECTION,auto adjust direction 0: increase 1: decrease" "increase,decrease" bitfld.long 0xC 0. "ENABLE,auto adjust enable" "0,1" line.long 0x10 "TIMER_H,compare timer value 48bit high bit" hexmask.long.word 0x10 0.--15. 1. "TIMER_H,high bit" line.long 0x14 "TIMER_L,compare timer value 48bit low bit" hexmask.long 0x14 0.--31. 1. "TIMER_L,low bit" line.long 0x18 "WAKEUP_CTRL,wake-up control" bitfld.long 0x18 6. "DISABLE_CLEAR,rtc_disable clear" "0,1" newline bitfld.long 0x18 5. "OVERFLOW_CLEAR,rtc_overflow clear" "0,1" bitfld.long 0x18 4. "CLEAR,write 1 to clear IRQ status" "0,1" newline bitfld.long 0x18 3. "STATUS,wake-up status RTC equal or larger than RTL timer value" "0,1" bitfld.long 0x18 2. "REQ_ENABLE,req enable 1- generate req when wakeup_status is 1" "?,generate req when wakeup_status is 1" newline bitfld.long 0x18 1. "IRQ_ENABLE,irq enable 1- generate IRQ when wakeup_status is 1" "?,generate IRQ when wakeup_status is 1" bitfld.long 0x18 0. "ENABLE,wake up enable" "0,1" line.long 0x1C "PERIODICAL_CRTL,periodical irq control" hexmask.long.byte 0x1C 3.--6. 1. "FREQ,freq slect irq period 32768/(2^(freq+1))" newline bitfld.long 0x1C 0. "IRQ_ENABLE,irq enable" "0,1" line.long 0x20 "VIOLATION_INT,violation interrupt" bitfld.long 0x20 3. "DISABLE_STATUS,disable violation interrupt status" "0,1" newline bitfld.long 0x20 2. "OVERFLOW_STATS,overflow violation interrupt status overflow_clear also will clear the interrupt" "0,1" bitfld.long 0x20 0.--1. "MASK,violation interrupt mask bit0--overflow mask bit1-- disable mask" "overflow mask,disable mask,?,?" tree.end repeat.end elif (CORENAME()=="CORTEXA55") repeat 2. (increment 1. 1.) (list ad:0x31800000 ad:0x31810000) tree "RTC$1" base $2 group.long 0x0++0x23 line.long 0x0 "SEC_RTC_CTRL,secure RTC controller" bitfld.long 0x0 31. "LOCK,sticky bit once set the rtc_enable secure_enable privilege_enable can't be changed" "0,1" newline bitfld.long 0x0 2. "PRIVILEGE_ENABLE,secure enable 1- privileged access only 0- both privileged/user access is allowed" "both privileged/user access is allowed,privileged access only" bitfld.long 0x0 1. "SECURE_ENABLE,secure enable 1- secure access only 0- both secure/nonsecure access is allowed" "both secure/nonsecure access is allowed,secure access only" newline bitfld.long 0x0 0. "RTC_ENABLE,RTC enable" "0,1" line.long 0x4 "RTC_H,48bit- RTC high register" hexmask.long.word 0x4 0.--15. 1. "RTC_H,high bit" line.long 0x8 "RTC_L,48bit- RTC low register" hexmask.long 0x8 0.--31. 1. "RTC_L,low bit" line.long 0xC "AUTO_ADJUST,RTC auto adjust function controller" hexmask.long.byte 0xC 16.--23. 1. "PERIOD,define the adjust period when happen" newline hexmask.long.byte 0xC 8.--15. 1. "CYCLE,auto adjust cycle amount of cycles to be adjusted" newline bitfld.long 0xC 1. "ADJUST_DIRECTION,auto adjust direction 0: increase 1: decrease" "increase,decrease" bitfld.long 0xC 0. "ENABLE,auto adjust enable" "0,1" line.long 0x10 "TIMER_H,compare timer value 48bit high bit" hexmask.long.word 0x10 0.--15. 1. "TIMER_H,high bit" line.long 0x14 "TIMER_L,compare timer value 48bit low bit" hexmask.long 0x14 0.--31. 1. "TIMER_L,low bit" line.long 0x18 "WAKEUP_CTRL,wake-up control" bitfld.long 0x18 6. "DISABLE_CLEAR,rtc_disable clear" "0,1" newline bitfld.long 0x18 5. "OVERFLOW_CLEAR,rtc_overflow clear" "0,1" bitfld.long 0x18 4. "CLEAR,write 1 to clear IRQ status" "0,1" newline bitfld.long 0x18 3. "STATUS,wake-up status RTC equal or larger than RTL timer value" "0,1" bitfld.long 0x18 2. "REQ_ENABLE,req enable 1- generate req when wakeup_status is 1" "?,generate req when wakeup_status is 1" newline bitfld.long 0x18 1. "IRQ_ENABLE,irq enable 1- generate IRQ when wakeup_status is 1" "?,generate IRQ when wakeup_status is 1" bitfld.long 0x18 0. "ENABLE,wake up enable" "0,1" line.long 0x1C "PERIODICAL_CRTL,periodical irq control" hexmask.long.byte 0x1C 3.--6. 1. "FREQ,freq slect irq period 32768/(2^(freq+1))" newline bitfld.long 0x1C 0. "IRQ_ENABLE,irq enable" "0,1" line.long 0x20 "VIOLATION_INT,violation interrupt" bitfld.long 0x20 3. "DISABLE_STATUS,disable violation interrupt status" "0,1" newline bitfld.long 0x20 2. "OVERFLOW_STATS,overflow violation interrupt status overflow_clear also will clear the interrupt" "0,1" bitfld.long 0x20 0.--1. "MASK,violation interrupt mask bit0--overflow mask bit1-- disable mask" "overflow mask,disable mask,?,?" tree.end repeat.end endif tree.end tree "SCR (System Control Register)" sif (CORENAME()=="CORTEXR5F") tree "SCR_AP" base ad:0xF8200000 group.long 0x0++0x6F line.long 0x0 "SCR_RW,SYSTEM CONTROL REGISTER READ/WRITE" hexmask.long 0x0 0.--31. 1. "SC_REG,system control register setting" line.long 0x4 "SCR_RW,SYSTEM CONTROL REGISTER READ/WRITE" hexmask.long 0x4 0.--31. 1. "SC_REG,system control register setting" line.long 0x8 "SCR_RW,SYSTEM CONTROL REGISTER READ/WRITE" hexmask.long 0x8 0.--31. 1. "SC_REG,system control register setting" line.long 0xC "SCR_RW,SYSTEM CONTROL REGISTER READ/WRITE" hexmask.long 0xC 0.--31. 1. "SC_REG,system control register setting" line.long 0x10 "SCR_RW,SYSTEM CONTROL REGISTER READ/WRITE" hexmask.long 0x10 0.--31. 1. "SC_REG,system control register setting" line.long 0x14 "SCR_RW,SYSTEM CONTROL REGISTER READ/WRITE" hexmask.long 0x14 0.--31. 1. "SC_REG,system control register setting" line.long 0x18 "SCR_RW,SYSTEM CONTROL REGISTER READ/WRITE" hexmask.long 0x18 0.--31. 1. "SC_REG,system control register setting" line.long 0x1C "SCR_RW,SYSTEM CONTROL REGISTER READ/WRITE" hexmask.long 0x1C 0.--31. 1. "SC_REG,system control register setting" line.long 0x20 "SCR_RW,SYSTEM CONTROL REGISTER READ/WRITE" hexmask.long 0x20 0.--31. 1. "SC_REG,system control register setting" line.long 0x24 "SCR_RW,SYSTEM CONTROL REGISTER READ/WRITE" hexmask.long 0x24 0.--31. 1. "SC_REG,system control register setting" line.long 0x28 "SCR_RW,SYSTEM CONTROL REGISTER READ/WRITE" hexmask.long 0x28 0.--31. 1. "SC_REG,system control register setting" line.long 0x2C "SCR_RW,SYSTEM CONTROL REGISTER READ/WRITE" hexmask.long 0x2C 0.--31. 1. "SC_REG,system control register setting" line.long 0x30 "SCR_RW,SYSTEM CONTROL REGISTER READ/WRITE" hexmask.long 0x30 0.--31. 1. "SC_REG,system control register setting" line.long 0x34 "SCR_RW,SYSTEM CONTROL REGISTER READ/WRITE" hexmask.long 0x34 0.--31. 1. "SC_REG,system control register setting" line.long 0x38 "SCR_RW,SYSTEM CONTROL REGISTER READ/WRITE" hexmask.long 0x38 0.--31. 1. "SC_REG,system control register setting" line.long 0x3C "SCR_RW,SYSTEM CONTROL REGISTER READ/WRITE" hexmask.long 0x3C 0.--31. 1. "SC_REG,system control register setting" line.long 0x40 "SCR_RW,SYSTEM CONTROL REGISTER READ/WRITE" hexmask.long 0x40 0.--31. 1. "SC_REG,system control register setting" line.long 0x44 "SCR_RW,SYSTEM CONTROL REGISTER READ/WRITE" hexmask.long 0x44 0.--31. 1. "SC_REG,system control register setting" line.long 0x48 "SCR_RW,SYSTEM CONTROL REGISTER READ/WRITE" hexmask.long 0x48 0.--31. 1. "SC_REG,system control register setting" line.long 0x4C "SCR_RW,SYSTEM CONTROL REGISTER READ/WRITE" hexmask.long 0x4C 0.--31. 1. "SC_REG,system control register setting" line.long 0x50 "SCR_RW,SYSTEM CONTROL REGISTER READ/WRITE" hexmask.long 0x50 0.--31. 1. "SC_REG,system control register setting" line.long 0x54 "SCR_RW,SYSTEM CONTROL REGISTER READ/WRITE" hexmask.long 0x54 0.--31. 1. "SC_REG,system control register setting" line.long 0x58 "SCR_RW,SYSTEM CONTROL REGISTER READ/WRITE" hexmask.long 0x58 0.--31. 1. "SC_REG,system control register setting" line.long 0x5C "SCR_RW,SYSTEM CONTROL REGISTER READ/WRITE" hexmask.long 0x5C 0.--31. 1. "SC_REG,system control register setting" line.long 0x60 "SCR_RW,SYSTEM CONTROL REGISTER READ/WRITE" hexmask.long 0x60 0.--31. 1. "SC_REG,system control register setting" line.long 0x64 "SCR_RW,SYSTEM CONTROL REGISTER READ/WRITE" hexmask.long 0x64 0.--31. 1. "SC_REG,system control register setting" line.long 0x68 "SCR_RW,SYSTEM CONTROL REGISTER READ/WRITE" hexmask.long 0x68 0.--31. 1. "SC_REG,system control register setting" line.long 0x6C "SCR_RW,SYSTEM CONTROL REGISTER READ/WRITE" hexmask.long 0x6C 0.--31. 1. "SC_REG,system control register setting" rgroup.long 0x100++0xF line.long 0x0 "SCR_RO,SYSTEM CONTROL REGISTER READ ONLY" hexmask.long 0x0 0.--31. 1. "SC_REG,system control register for Read-Only status." line.long 0x4 "SCR_RO,SYSTEM CONTROL REGISTER READ ONLY" hexmask.long 0x4 0.--31. 1. "SC_REG,system control register for Read-Only status." line.long 0x8 "SCR_RO,SYSTEM CONTROL REGISTER READ ONLY" hexmask.long 0x8 0.--31. 1. "SC_REG,system control register for Read-Only status." line.long 0xC "SCR_RO,SYSTEM CONTROL REGISTER READ ONLY" hexmask.long 0xC 0.--31. 1. "SC_REG,system control register for Read-Only status." repeat 16. (list 0x10 0x10 0x10 0x10 0x10 0x10 0x10 0x10 0x10 0x10 0x10 0x10 0x10 0x10 0x10 0x10 )(list 0x0 0x4 0x8 0xC 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C ) group.long ($2+0x200)++0x3 line.long 0x0 "SCR_L$1,SYSTEM CONTROL REGISTER WITH STICKY AND LOCK" bitfld.long 0x0 31. "SC_STICKY_15,system control register used to lock the corresponding bit in lower half word or as sticky bit" "0,1" bitfld.long 0x0 30. "SC_STICKY_14,system control register used to lock the corresponding bit in lower half word or as sticky bit" "0,1" bitfld.long 0x0 29. "SC_STICKY_13,system control register used to lock the corresponding bit in lower half word or as sticky bit" "0,1" bitfld.long 0x0 28. "SC_STICKY_12,system control register used to lock the corresponding bit in lower half word or as sticky bit" "0,1" bitfld.long 0x0 27. "SC_STICKY_11,system control register used to lock the corresponding bit in lower half word or as sticky bit" "0,1" bitfld.long 0x0 26. "SC_STICKY_10,system control register used to lock the corresponding bit in lower half word or as sticky bit" "0,1" newline bitfld.long 0x0 25. "SC_STICKY_9,system control register used to lock the corresponding bit in lower half word or as sticky bit" "0,1" bitfld.long 0x0 24. "SC_STICKY_8,system control register used to lock the corresponding bit in lower half word or as sticky bit" "0,1" bitfld.long 0x0 23. "SC_STICKY_7,system control register used to lock the corresponding bit in lower half word or as sticky bit" "0,1" bitfld.long 0x0 22. "SC_STICKY_6,system control register used to lock the corresponding bit in lower half word or as sticky bit" "0,1" bitfld.long 0x0 21. "SC_STICKY_5,system control register used to lock the corresponding bit in lower half word or as sticky bit" "0,1" bitfld.long 0x0 20. "SC_STICKY_4,system control register used to lock the corresponding bit in lower half word or as sticky bit" "0,1" newline bitfld.long 0x0 19. "SC_STICKY_3,system control register used to lock the corresponding bit in lower half word or as sticky bit" "0,1" bitfld.long 0x0 18. "SC_STICKY_2,system control register used to lock the corresponding bit in lower half word or as sticky bit" "0,1" bitfld.long 0x0 17. "SC_STICKY_1,system control register used to lock the corresponding bit in lower half word or as sticky bit" "0,1" bitfld.long 0x0 16. "SC_STICKY_0,system control register used to lock the corresponding bit in lower half word or as sticky bit" "0,1" bitfld.long 0x0 15. "SC_REG_15,system control register for read/write can be locked by corrsponding bit in upper half word" "0,1" bitfld.long 0x0 14. "SC_REG_14,system control register for read/write can be locked by corrsponding bit in upper half word" "0,1" newline bitfld.long 0x0 13. "SC_REG_13,system control register for read/write can be locked by corrsponding bit in upper half word" "0,1" bitfld.long 0x0 12. "SC_REG_12,system control register for read/write can be locked by corrsponding bit in upper half word" "0,1" bitfld.long 0x0 11. "SC_REG_11,system control register for read/write can be locked by corrsponding bit in upper half word" "0,1" bitfld.long 0x0 10. "SC_REG_10,system control register for read/write can be locked by corrsponding bit in upper half word" "0,1" bitfld.long 0x0 9. "SC_REG_9,system control register for read/write can be locked by corrsponding bit in upper half word" "0,1" bitfld.long 0x0 8. "SC_REG_8,system control register for read/write can be locked by corrsponding bit in upper half word" "0,1" newline bitfld.long 0x0 7. "SC_REG_7,system control register for read/write can be locked by corrsponding bit in upper half word" "0,1" bitfld.long 0x0 6. "SC_REG_6,system control register for read/write can be locked by corrsponding bit in upper half word" "0,1" bitfld.long 0x0 5. "SC_REG_5,system control register for read/write can be locked by corrsponding bit in upper half word" "0,1" bitfld.long 0x0 4. "SC_REG_4,system control register for read/write can be locked by corrsponding bit in upper half word" "0,1" bitfld.long 0x0 3. "SC_REG_3,system control register for read/write can be locked by corrsponding bit in upper half word" "0,1" bitfld.long 0x0 2. "SC_REG_2,system control register for read/write can be locked by corrsponding bit in upper half word" "0,1" newline bitfld.long 0x0 1. "SC_REG_1,system control register for read/write can be locked by corrsponding bit in upper half word" "0,1" bitfld.long 0x0 0. "SC_REG_0,system control register for read/write can be locked by corrsponding bit in upper half word" "0,1" repeat.end repeat 16. (list 0x10 0x10 0x10 0x10 0x10 0x10 0x10 0x10 0x10 0x10 0x10 0x10 0x10 0x10 0x10 0x10 )(list 0x40 0x44 0x48 0x4C 0x50 0x54 0x58 0x5C 0x60 0x64 0x68 0x6C 0x70 0x74 0x78 0x7C ) group.long ($2+0x200)++0x3 line.long 0x0 "SCR_L$1,SYSTEM CONTROL REGISTER WITH STICKY AND LOCK" bitfld.long 0x0 31. "SC_STICKY_15,system control register used to lock the corresponding bit in lower half word or as sticky bit" "0,1" bitfld.long 0x0 30. "SC_STICKY_14,system control register used to lock the corresponding bit in lower half word or as sticky bit" "0,1" bitfld.long 0x0 29. "SC_STICKY_13,system control register used to lock the corresponding bit in lower half word or as sticky bit" "0,1" bitfld.long 0x0 28. "SC_STICKY_12,system control register used to lock the corresponding bit in lower half word or as sticky bit" "0,1" bitfld.long 0x0 27. "SC_STICKY_11,system control register used to lock the corresponding bit in lower half word or as sticky bit" "0,1" bitfld.long 0x0 26. "SC_STICKY_10,system control register used to lock the corresponding bit in lower half word or as sticky bit" "0,1" newline bitfld.long 0x0 25. "SC_STICKY_9,system control register used to lock the corresponding bit in lower half word or as sticky bit" "0,1" bitfld.long 0x0 24. "SC_STICKY_8,system control register used to lock the corresponding bit in lower half word or as sticky bit" "0,1" bitfld.long 0x0 23. "SC_STICKY_7,system control register used to lock the corresponding bit in lower half word or as sticky bit" "0,1" bitfld.long 0x0 22. "SC_STICKY_6,system control register used to lock the corresponding bit in lower half word or as sticky bit" "0,1" bitfld.long 0x0 21. "SC_STICKY_5,system control register used to lock the corresponding bit in lower half word or as sticky bit" "0,1" bitfld.long 0x0 20. "SC_STICKY_4,system control register used to lock the corresponding bit in lower half word or as sticky bit" "0,1" newline bitfld.long 0x0 19. "SC_STICKY_3,system control register used to lock the corresponding bit in lower half word or as sticky bit" "0,1" bitfld.long 0x0 18. "SC_STICKY_2,system control register used to lock the corresponding bit in lower half word or as sticky bit" "0,1" bitfld.long 0x0 17. "SC_STICKY_1,system control register used to lock the corresponding bit in lower half word or as sticky bit" "0,1" bitfld.long 0x0 16. "SC_STICKY_0,system control register used to lock the corresponding bit in lower half word or as sticky bit" "0,1" bitfld.long 0x0 15. "SC_REG_15,system control register for read/write can be locked by corrsponding bit in upper half word" "0,1" bitfld.long 0x0 14. "SC_REG_14,system control register for read/write can be locked by corrsponding bit in upper half word" "0,1" newline bitfld.long 0x0 13. "SC_REG_13,system control register for read/write can be locked by corrsponding bit in upper half word" "0,1" bitfld.long 0x0 12. "SC_REG_12,system control register for read/write can be locked by corrsponding bit in upper half word" "0,1" bitfld.long 0x0 11. "SC_REG_11,system control register for read/write can be locked by corrsponding bit in upper half word" "0,1" bitfld.long 0x0 10. "SC_REG_10,system control register for read/write can be locked by corrsponding bit in upper half word" "0,1" bitfld.long 0x0 9. "SC_REG_9,system control register for read/write can be locked by corrsponding bit in upper half word" "0,1" bitfld.long 0x0 8. "SC_REG_8,system control register for read/write can be locked by corrsponding bit in upper half word" "0,1" newline bitfld.long 0x0 7. "SC_REG_7,system control register for read/write can be locked by corrsponding bit in upper half word" "0,1" bitfld.long 0x0 6. "SC_REG_6,system control register for read/write can be locked by corrsponding bit in upper half word" "0,1" bitfld.long 0x0 5. "SC_REG_5,system control register for read/write can be locked by corrsponding bit in upper half word" "0,1" bitfld.long 0x0 4. "SC_REG_4,system control register for read/write can be locked by corrsponding bit in upper half word" "0,1" bitfld.long 0x0 3. "SC_REG_3,system control register for read/write can be locked by corrsponding bit in upper half word" "0,1" bitfld.long 0x0 2. "SC_REG_2,system control register for read/write can be locked by corrsponding bit in upper half word" "0,1" newline bitfld.long 0x0 1. "SC_REG_1,system control register for read/write can be locked by corrsponding bit in upper half word" "0,1" bitfld.long 0x0 0. "SC_REG_0,system control register for read/write can be locked by corrsponding bit in upper half word" "0,1" repeat.end repeat 4. (list 0x10 0x10 0x10 0x10 )(list 0x80 0x84 0x88 0x8C ) group.long ($2+0x200)++0x3 line.long 0x0 "SCR_L$1,SYSTEM CONTROL REGISTER WITH STICKY AND LOCK" bitfld.long 0x0 31. "SC_STICKY_15,system control register used to lock the corresponding bit in lower half word or as sticky bit" "0,1" bitfld.long 0x0 30. "SC_STICKY_14,system control register used to lock the corresponding bit in lower half word or as sticky bit" "0,1" bitfld.long 0x0 29. "SC_STICKY_13,system control register used to lock the corresponding bit in lower half word or as sticky bit" "0,1" bitfld.long 0x0 28. "SC_STICKY_12,system control register used to lock the corresponding bit in lower half word or as sticky bit" "0,1" bitfld.long 0x0 27. "SC_STICKY_11,system control register used to lock the corresponding bit in lower half word or as sticky bit" "0,1" bitfld.long 0x0 26. "SC_STICKY_10,system control register used to lock the corresponding bit in lower half word or as sticky bit" "0,1" newline bitfld.long 0x0 25. "SC_STICKY_9,system control register used to lock the corresponding bit in lower half word or as sticky bit" "0,1" bitfld.long 0x0 24. "SC_STICKY_8,system control register used to lock the corresponding bit in lower half word or as sticky bit" "0,1" bitfld.long 0x0 23. "SC_STICKY_7,system control register used to lock the corresponding bit in lower half word or as sticky bit" "0,1" bitfld.long 0x0 22. "SC_STICKY_6,system control register used to lock the corresponding bit in lower half word or as sticky bit" "0,1" bitfld.long 0x0 21. "SC_STICKY_5,system control register used to lock the corresponding bit in lower half word or as sticky bit" "0,1" bitfld.long 0x0 20. "SC_STICKY_4,system control register used to lock the corresponding bit in lower half word or as sticky bit" "0,1" newline bitfld.long 0x0 19. "SC_STICKY_3,system control register used to lock the corresponding bit in lower half word or as sticky bit" "0,1" bitfld.long 0x0 18. "SC_STICKY_2,system control register used to lock the corresponding bit in lower half word or as sticky bit" "0,1" bitfld.long 0x0 17. "SC_STICKY_1,system control register used to lock the corresponding bit in lower half word or as sticky bit" "0,1" bitfld.long 0x0 16. "SC_STICKY_0,system control register used to lock the corresponding bit in lower half word or as sticky bit" "0,1" bitfld.long 0x0 15. "SC_REG_15,system control register for read/write can be locked by corrsponding bit in upper half word" "0,1" bitfld.long 0x0 14. "SC_REG_14,system control register for read/write can be locked by corrsponding bit in upper half word" "0,1" newline bitfld.long 0x0 13. "SC_REG_13,system control register for read/write can be locked by corrsponding bit in upper half word" "0,1" bitfld.long 0x0 12. "SC_REG_12,system control register for read/write can be locked by corrsponding bit in upper half word" "0,1" bitfld.long 0x0 11. "SC_REG_11,system control register for read/write can be locked by corrsponding bit in upper half word" "0,1" bitfld.long 0x0 10. "SC_REG_10,system control register for read/write can be locked by corrsponding bit in upper half word" "0,1" bitfld.long 0x0 9. "SC_REG_9,system control register for read/write can be locked by corrsponding bit in upper half word" "0,1" bitfld.long 0x0 8. "SC_REG_8,system control register for read/write can be locked by corrsponding bit in upper half word" "0,1" newline bitfld.long 0x0 7. "SC_REG_7,system control register for read/write can be locked by corrsponding bit in upper half word" "0,1" bitfld.long 0x0 6. "SC_REG_6,system control register for read/write can be locked by corrsponding bit in upper half word" "0,1" bitfld.long 0x0 5. "SC_REG_5,system control register for read/write can be locked by corrsponding bit in upper half word" "0,1" bitfld.long 0x0 4. "SC_REG_4,system control register for read/write can be locked by corrsponding bit in upper half word" "0,1" bitfld.long 0x0 3. "SC_REG_3,system control register for read/write can be locked by corrsponding bit in upper half word" "0,1" bitfld.long 0x0 2. "SC_REG_2,system control register for read/write can be locked by corrsponding bit in upper half word" "0,1" newline bitfld.long 0x0 1. "SC_REG_1,system control register for read/write can be locked by corrsponding bit in upper half word" "0,1" bitfld.long 0x0 0. "SC_REG_0,system control register for read/write can be locked by corrsponding bit in upper half word" "0,1" repeat.end repeat 16. (list 0x1F 0x1F 0x1F 0x1F 0x1F 0x1F 0x1F 0x1F 0x1F 0x1F 0x1F 0x1F 0x1F 0x1F 0x1F 0x1F )(list 0x0 0x4 0x8 0xC 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C ) group.long ($2+0x400)++0x3 line.long 0x0 "SCR_L$1,SYSTEM CONTROL REGISTER WITH 31BIT LOCK" bitfld.long 0x0 31. "SC_LOCK,lock bit for bit[30:0]" "0,1" hexmask.long 0x0 0.--30. 1. "SC_REG,system control register for read/write can be locked by bit[31]" repeat.end repeat 12. (list 0x1F 0x1F 0x1F 0x1F 0x1F 0x1F 0x1F 0x1F 0x1F 0x1F 0x1F 0x1F )(list 0x40 0x44 0x48 0x4C 0x50 0x54 0x58 0x5C 0x60 0x64 0x68 0x6C ) group.long ($2+0x400)++0x3 line.long 0x0 "SCR_L$1,SYSTEM CONTROL REGISTER WITH 31BIT LOCK" bitfld.long 0x0 31. "SC_LOCK,lock bit for bit[30:0]" "0,1" hexmask.long 0x0 0.--30. 1. "SC_REG,system control register for read/write can be locked by bit[31]" repeat.end repeat 16. (list 0x10 0x10 0x10 0x10 0x10 0x10 0x10 0x10 0x10 0x10 0x10 0x10 0x10 0x10 0x10 0x10 )(list 0x0 0x4 0x8 0xC 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C ) group.long ($2+0x600)++0x3 line.long 0x0 "SCR_R16W$1,SYSTEM CONTROL REGISTER WITH HALF RW HALF RO" hexmask.long.word 0x0 16.--31. 1. "SC_ROREG,system control register for read only" hexmask.long.word 0x0 0.--15. 1. "SC_REG,system control register for read/write" repeat.end repeat 16. (list 0x10 0x10 0x10 0x10 0x10 0x10 0x10 0x10 0x10 0x10 0x10 0x10 0x10 0x10 0x10 0x10 )(list 0x40 0x44 0x48 0x4C 0x50 0x54 0x58 0x5C 0x60 0x64 0x68 0x6C 0x70 0x74 0x78 0x7C ) group.long ($2+0x600)++0x3 line.long 0x0 "SCR_R16W$1,SYSTEM CONTROL REGISTER WITH HALF RW HALF RO" hexmask.long.word 0x0 16.--31. 1. "SC_ROREG,system control register for read only" hexmask.long.word 0x0 0.--15. 1. "SC_REG,system control register for read/write" repeat.end repeat 8. (list 0x10 0x10 0x10 0x10 0x10 0x10 0x10 0x10 )(list 0x80 0x84 0x88 0x8C 0x90 0x94 0x98 0x9C ) group.long ($2+0x600)++0x3 line.long 0x0 "SCR_R16W$1,SYSTEM CONTROL REGISTER WITH HALF RW HALF RO" hexmask.long.word 0x0 16.--31. 1. "SC_ROREG,system control register for read only" hexmask.long.word 0x0 0.--15. 1. "SC_REG,system control register for read/write" repeat.end tree.end tree "SCR_SAFETY" base ad:0xFC200000 group.long 0x0++0x6F line.long 0x0 "SCR_RW,SYSTEM CONTROL REGISTER READ/WRITE" hexmask.long 0x0 0.--31. 1. "SC_REG,system control register setting" line.long 0x4 "SCR_RW,SYSTEM CONTROL REGISTER READ/WRITE" hexmask.long 0x4 0.--31. 1. "SC_REG,system control register setting" line.long 0x8 "SCR_RW,SYSTEM CONTROL REGISTER READ/WRITE" hexmask.long 0x8 0.--31. 1. "SC_REG,system control register setting" line.long 0xC "SCR_RW,SYSTEM CONTROL REGISTER READ/WRITE" hexmask.long 0xC 0.--31. 1. "SC_REG,system control register setting" line.long 0x10 "SCR_RW,SYSTEM CONTROL REGISTER READ/WRITE" hexmask.long 0x10 0.--31. 1. "SC_REG,system control register setting" line.long 0x14 "SCR_RW,SYSTEM CONTROL REGISTER READ/WRITE" hexmask.long 0x14 0.--31. 1. "SC_REG,system control register setting" line.long 0x18 "SCR_RW,SYSTEM CONTROL REGISTER READ/WRITE" hexmask.long 0x18 0.--31. 1. "SC_REG,system control register setting" line.long 0x1C "SCR_RW,SYSTEM CONTROL REGISTER READ/WRITE" hexmask.long 0x1C 0.--31. 1. "SC_REG,system control register setting" line.long 0x20 "SCR_RW,SYSTEM CONTROL REGISTER READ/WRITE" hexmask.long 0x20 0.--31. 1. "SC_REG,system control register setting" line.long 0x24 "SCR_RW,SYSTEM CONTROL REGISTER READ/WRITE" hexmask.long 0x24 0.--31. 1. "SC_REG,system control register setting" line.long 0x28 "SCR_RW,SYSTEM CONTROL REGISTER READ/WRITE" hexmask.long 0x28 0.--31. 1. "SC_REG,system control register setting" line.long 0x2C "SCR_RW,SYSTEM CONTROL REGISTER READ/WRITE" hexmask.long 0x2C 0.--31. 1. "SC_REG,system control register setting" line.long 0x30 "SCR_RW,SYSTEM CONTROL REGISTER READ/WRITE" hexmask.long 0x30 0.--31. 1. "SC_REG,system control register setting" line.long 0x34 "SCR_RW,SYSTEM CONTROL REGISTER READ/WRITE" hexmask.long 0x34 0.--31. 1. "SC_REG,system control register setting" line.long 0x38 "SCR_RW,SYSTEM CONTROL REGISTER READ/WRITE" hexmask.long 0x38 0.--31. 1. "SC_REG,system control register setting" line.long 0x3C "SCR_RW,SYSTEM CONTROL REGISTER READ/WRITE" hexmask.long 0x3C 0.--31. 1. "SC_REG,system control register setting" line.long 0x40 "SCR_RW,SYSTEM CONTROL REGISTER READ/WRITE" hexmask.long 0x40 0.--31. 1. "SC_REG,system control register setting" line.long 0x44 "SCR_RW,SYSTEM CONTROL REGISTER READ/WRITE" hexmask.long 0x44 0.--31. 1. "SC_REG,system control register setting" line.long 0x48 "SCR_RW,SYSTEM CONTROL REGISTER READ/WRITE" hexmask.long 0x48 0.--31. 1. "SC_REG,system control register setting" line.long 0x4C "SCR_RW,SYSTEM CONTROL REGISTER READ/WRITE" hexmask.long 0x4C 0.--31. 1. "SC_REG,system control register setting" line.long 0x50 "SCR_RW,SYSTEM CONTROL REGISTER READ/WRITE" hexmask.long 0x50 0.--31. 1. "SC_REG,system control register setting" line.long 0x54 "SCR_RW,SYSTEM CONTROL REGISTER READ/WRITE" hexmask.long 0x54 0.--31. 1. "SC_REG,system control register setting" line.long 0x58 "SCR_RW,SYSTEM CONTROL REGISTER READ/WRITE" hexmask.long 0x58 0.--31. 1. "SC_REG,system control register setting" line.long 0x5C "SCR_RW,SYSTEM CONTROL REGISTER READ/WRITE" hexmask.long 0x5C 0.--31. 1. "SC_REG,system control register setting" line.long 0x60 "SCR_RW,SYSTEM CONTROL REGISTER READ/WRITE" hexmask.long 0x60 0.--31. 1. "SC_REG,system control register setting" line.long 0x64 "SCR_RW,SYSTEM CONTROL REGISTER READ/WRITE" hexmask.long 0x64 0.--31. 1. "SC_REG,system control register setting" line.long 0x68 "SCR_RW,SYSTEM CONTROL REGISTER READ/WRITE" hexmask.long 0x68 0.--31. 1. "SC_REG,system control register setting" line.long 0x6C "SCR_RW,SYSTEM CONTROL REGISTER READ/WRITE" hexmask.long 0x6C 0.--31. 1. "SC_REG,system control register setting" rgroup.long 0x100++0xF line.long 0x0 "SCR_RO,SYSTEM CONTROL REGISTER READ ONLY" hexmask.long 0x0 0.--31. 1. "SC_REG,system control register for Read-Only status." line.long 0x4 "SCR_RO,SYSTEM CONTROL REGISTER READ ONLY" hexmask.long 0x4 0.--31. 1. "SC_REG,system control register for Read-Only status." line.long 0x8 "SCR_RO,SYSTEM CONTROL REGISTER READ ONLY" hexmask.long 0x8 0.--31. 1. "SC_REG,system control register for Read-Only status." line.long 0xC "SCR_RO,SYSTEM CONTROL REGISTER READ ONLY" hexmask.long 0xC 0.--31. 1. "SC_REG,system control register for Read-Only status." repeat 16. (list 0x10 0x10 0x10 0x10 0x10 0x10 0x10 0x10 0x10 0x10 0x10 0x10 0x10 0x10 0x10 0x10 )(list 0x0 0x4 0x8 0xC 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C ) group.long ($2+0x200)++0x3 line.long 0x0 "SCR_L$1,SYSTEM CONTROL REGISTER WITH STICKY AND LOCK" bitfld.long 0x0 31. "SC_STICKY_15,system control register used to lock the corresponding bit in lower half word or as sticky bit" "0,1" bitfld.long 0x0 30. "SC_STICKY_14,system control register used to lock the corresponding bit in lower half word or as sticky bit" "0,1" bitfld.long 0x0 29. "SC_STICKY_13,system control register used to lock the corresponding bit in lower half word or as sticky bit" "0,1" bitfld.long 0x0 28. "SC_STICKY_12,system control register used to lock the corresponding bit in lower half word or as sticky bit" "0,1" bitfld.long 0x0 27. "SC_STICKY_11,system control register used to lock the corresponding bit in lower half word or as sticky bit" "0,1" bitfld.long 0x0 26. "SC_STICKY_10,system control register used to lock the corresponding bit in lower half word or as sticky bit" "0,1" newline bitfld.long 0x0 25. "SC_STICKY_9,system control register used to lock the corresponding bit in lower half word or as sticky bit" "0,1" bitfld.long 0x0 24. "SC_STICKY_8,system control register used to lock the corresponding bit in lower half word or as sticky bit" "0,1" bitfld.long 0x0 23. "SC_STICKY_7,system control register used to lock the corresponding bit in lower half word or as sticky bit" "0,1" bitfld.long 0x0 22. "SC_STICKY_6,system control register used to lock the corresponding bit in lower half word or as sticky bit" "0,1" bitfld.long 0x0 21. "SC_STICKY_5,system control register used to lock the corresponding bit in lower half word or as sticky bit" "0,1" bitfld.long 0x0 20. "SC_STICKY_4,system control register used to lock the corresponding bit in lower half word or as sticky bit" "0,1" newline bitfld.long 0x0 19. "SC_STICKY_3,system control register used to lock the corresponding bit in lower half word or as sticky bit" "0,1" bitfld.long 0x0 18. "SC_STICKY_2,system control register used to lock the corresponding bit in lower half word or as sticky bit" "0,1" bitfld.long 0x0 17. "SC_STICKY_1,system control register used to lock the corresponding bit in lower half word or as sticky bit" "0,1" bitfld.long 0x0 16. "SC_STICKY_0,system control register used to lock the corresponding bit in lower half word or as sticky bit" "0,1" bitfld.long 0x0 15. "SC_REG_15,system control register for read/write can be locked by corrsponding bit in upper half word" "0,1" bitfld.long 0x0 14. "SC_REG_14,system control register for read/write can be locked by corrsponding bit in upper half word" "0,1" newline bitfld.long 0x0 13. "SC_REG_13,system control register for read/write can be locked by corrsponding bit in upper half word" "0,1" bitfld.long 0x0 12. "SC_REG_12,system control register for read/write can be locked by corrsponding bit in upper half word" "0,1" bitfld.long 0x0 11. "SC_REG_11,system control register for read/write can be locked by corrsponding bit in upper half word" "0,1" bitfld.long 0x0 10. "SC_REG_10,system control register for read/write can be locked by corrsponding bit in upper half word" "0,1" bitfld.long 0x0 9. "SC_REG_9,system control register for read/write can be locked by corrsponding bit in upper half word" "0,1" bitfld.long 0x0 8. "SC_REG_8,system control register for read/write can be locked by corrsponding bit in upper half word" "0,1" newline bitfld.long 0x0 7. "SC_REG_7,system control register for read/write can be locked by corrsponding bit in upper half word" "0,1" bitfld.long 0x0 6. "SC_REG_6,system control register for read/write can be locked by corrsponding bit in upper half word" "0,1" bitfld.long 0x0 5. "SC_REG_5,system control register for read/write can be locked by corrsponding bit in upper half word" "0,1" bitfld.long 0x0 4. "SC_REG_4,system control register for read/write can be locked by corrsponding bit in upper half word" "0,1" bitfld.long 0x0 3. "SC_REG_3,system control register for read/write can be locked by corrsponding bit in upper half word" "0,1" bitfld.long 0x0 2. "SC_REG_2,system control register for read/write can be locked by corrsponding bit in upper half word" "0,1" newline bitfld.long 0x0 1. "SC_REG_1,system control register for read/write can be locked by corrsponding bit in upper half word" "0,1" bitfld.long 0x0 0. "SC_REG_0,system control register for read/write can be locked by corrsponding bit in upper half word" "0,1" repeat.end repeat 16. (list 0x10 0x10 0x10 0x10 0x10 0x10 0x10 0x10 0x10 0x10 0x10 0x10 0x10 0x10 0x10 0x10 )(list 0x40 0x44 0x48 0x4C 0x50 0x54 0x58 0x5C 0x60 0x64 0x68 0x6C 0x70 0x74 0x78 0x7C ) group.long ($2+0x200)++0x3 line.long 0x0 "SCR_L$1,SYSTEM CONTROL REGISTER WITH STICKY AND LOCK" bitfld.long 0x0 31. "SC_STICKY_15,system control register used to lock the corresponding bit in lower half word or as sticky bit" "0,1" bitfld.long 0x0 30. "SC_STICKY_14,system control register used to lock the corresponding bit in lower half word or as sticky bit" "0,1" bitfld.long 0x0 29. "SC_STICKY_13,system control register used to lock the corresponding bit in lower half word or as sticky bit" "0,1" bitfld.long 0x0 28. "SC_STICKY_12,system control register used to lock the corresponding bit in lower half word or as sticky bit" "0,1" bitfld.long 0x0 27. "SC_STICKY_11,system control register used to lock the corresponding bit in lower half word or as sticky bit" "0,1" bitfld.long 0x0 26. "SC_STICKY_10,system control register used to lock the corresponding bit in lower half word or as sticky bit" "0,1" newline bitfld.long 0x0 25. "SC_STICKY_9,system control register used to lock the corresponding bit in lower half word or as sticky bit" "0,1" bitfld.long 0x0 24. "SC_STICKY_8,system control register used to lock the corresponding bit in lower half word or as sticky bit" "0,1" bitfld.long 0x0 23. "SC_STICKY_7,system control register used to lock the corresponding bit in lower half word or as sticky bit" "0,1" bitfld.long 0x0 22. "SC_STICKY_6,system control register used to lock the corresponding bit in lower half word or as sticky bit" "0,1" bitfld.long 0x0 21. "SC_STICKY_5,system control register used to lock the corresponding bit in lower half word or as sticky bit" "0,1" bitfld.long 0x0 20. "SC_STICKY_4,system control register used to lock the corresponding bit in lower half word or as sticky bit" "0,1" newline bitfld.long 0x0 19. "SC_STICKY_3,system control register used to lock the corresponding bit in lower half word or as sticky bit" "0,1" bitfld.long 0x0 18. "SC_STICKY_2,system control register used to lock the corresponding bit in lower half word or as sticky bit" "0,1" bitfld.long 0x0 17. "SC_STICKY_1,system control register used to lock the corresponding bit in lower half word or as sticky bit" "0,1" bitfld.long 0x0 16. "SC_STICKY_0,system control register used to lock the corresponding bit in lower half word or as sticky bit" "0,1" bitfld.long 0x0 15. "SC_REG_15,system control register for read/write can be locked by corrsponding bit in upper half word" "0,1" bitfld.long 0x0 14. "SC_REG_14,system control register for read/write can be locked by corrsponding bit in upper half word" "0,1" newline bitfld.long 0x0 13. "SC_REG_13,system control register for read/write can be locked by corrsponding bit in upper half word" "0,1" bitfld.long 0x0 12. "SC_REG_12,system control register for read/write can be locked by corrsponding bit in upper half word" "0,1" bitfld.long 0x0 11. "SC_REG_11,system control register for read/write can be locked by corrsponding bit in upper half word" "0,1" bitfld.long 0x0 10. "SC_REG_10,system control register for read/write can be locked by corrsponding bit in upper half word" "0,1" bitfld.long 0x0 9. "SC_REG_9,system control register for read/write can be locked by corrsponding bit in upper half word" "0,1" bitfld.long 0x0 8. "SC_REG_8,system control register for read/write can be locked by corrsponding bit in upper half word" "0,1" newline bitfld.long 0x0 7. "SC_REG_7,system control register for read/write can be locked by corrsponding bit in upper half word" "0,1" bitfld.long 0x0 6. "SC_REG_6,system control register for read/write can be locked by corrsponding bit in upper half word" "0,1" bitfld.long 0x0 5. "SC_REG_5,system control register for read/write can be locked by corrsponding bit in upper half word" "0,1" bitfld.long 0x0 4. "SC_REG_4,system control register for read/write can be locked by corrsponding bit in upper half word" "0,1" bitfld.long 0x0 3. "SC_REG_3,system control register for read/write can be locked by corrsponding bit in upper half word" "0,1" bitfld.long 0x0 2. "SC_REG_2,system control register for read/write can be locked by corrsponding bit in upper half word" "0,1" newline bitfld.long 0x0 1. "SC_REG_1,system control register for read/write can be locked by corrsponding bit in upper half word" "0,1" bitfld.long 0x0 0. "SC_REG_0,system control register for read/write can be locked by corrsponding bit in upper half word" "0,1" repeat.end repeat 4. (list 0x10 0x10 0x10 0x10 )(list 0x80 0x84 0x88 0x8C ) group.long ($2+0x200)++0x3 line.long 0x0 "SCR_L$1,SYSTEM CONTROL REGISTER WITH STICKY AND LOCK" bitfld.long 0x0 31. "SC_STICKY_15,system control register used to lock the corresponding bit in lower half word or as sticky bit" "0,1" bitfld.long 0x0 30. "SC_STICKY_14,system control register used to lock the corresponding bit in lower half word or as sticky bit" "0,1" bitfld.long 0x0 29. "SC_STICKY_13,system control register used to lock the corresponding bit in lower half word or as sticky bit" "0,1" bitfld.long 0x0 28. "SC_STICKY_12,system control register used to lock the corresponding bit in lower half word or as sticky bit" "0,1" bitfld.long 0x0 27. "SC_STICKY_11,system control register used to lock the corresponding bit in lower half word or as sticky bit" "0,1" bitfld.long 0x0 26. "SC_STICKY_10,system control register used to lock the corresponding bit in lower half word or as sticky bit" "0,1" newline bitfld.long 0x0 25. "SC_STICKY_9,system control register used to lock the corresponding bit in lower half word or as sticky bit" "0,1" bitfld.long 0x0 24. "SC_STICKY_8,system control register used to lock the corresponding bit in lower half word or as sticky bit" "0,1" bitfld.long 0x0 23. "SC_STICKY_7,system control register used to lock the corresponding bit in lower half word or as sticky bit" "0,1" bitfld.long 0x0 22. "SC_STICKY_6,system control register used to lock the corresponding bit in lower half word or as sticky bit" "0,1" bitfld.long 0x0 21. "SC_STICKY_5,system control register used to lock the corresponding bit in lower half word or as sticky bit" "0,1" bitfld.long 0x0 20. "SC_STICKY_4,system control register used to lock the corresponding bit in lower half word or as sticky bit" "0,1" newline bitfld.long 0x0 19. "SC_STICKY_3,system control register used to lock the corresponding bit in lower half word or as sticky bit" "0,1" bitfld.long 0x0 18. "SC_STICKY_2,system control register used to lock the corresponding bit in lower half word or as sticky bit" "0,1" bitfld.long 0x0 17. "SC_STICKY_1,system control register used to lock the corresponding bit in lower half word or as sticky bit" "0,1" bitfld.long 0x0 16. "SC_STICKY_0,system control register used to lock the corresponding bit in lower half word or as sticky bit" "0,1" bitfld.long 0x0 15. "SC_REG_15,system control register for read/write can be locked by corrsponding bit in upper half word" "0,1" bitfld.long 0x0 14. "SC_REG_14,system control register for read/write can be locked by corrsponding bit in upper half word" "0,1" newline bitfld.long 0x0 13. "SC_REG_13,system control register for read/write can be locked by corrsponding bit in upper half word" "0,1" bitfld.long 0x0 12. "SC_REG_12,system control register for read/write can be locked by corrsponding bit in upper half word" "0,1" bitfld.long 0x0 11. "SC_REG_11,system control register for read/write can be locked by corrsponding bit in upper half word" "0,1" bitfld.long 0x0 10. "SC_REG_10,system control register for read/write can be locked by corrsponding bit in upper half word" "0,1" bitfld.long 0x0 9. "SC_REG_9,system control register for read/write can be locked by corrsponding bit in upper half word" "0,1" bitfld.long 0x0 8. "SC_REG_8,system control register for read/write can be locked by corrsponding bit in upper half word" "0,1" newline bitfld.long 0x0 7. "SC_REG_7,system control register for read/write can be locked by corrsponding bit in upper half word" "0,1" bitfld.long 0x0 6. "SC_REG_6,system control register for read/write can be locked by corrsponding bit in upper half word" "0,1" bitfld.long 0x0 5. "SC_REG_5,system control register for read/write can be locked by corrsponding bit in upper half word" "0,1" bitfld.long 0x0 4. "SC_REG_4,system control register for read/write can be locked by corrsponding bit in upper half word" "0,1" bitfld.long 0x0 3. "SC_REG_3,system control register for read/write can be locked by corrsponding bit in upper half word" "0,1" bitfld.long 0x0 2. "SC_REG_2,system control register for read/write can be locked by corrsponding bit in upper half word" "0,1" newline bitfld.long 0x0 1. "SC_REG_1,system control register for read/write can be locked by corrsponding bit in upper half word" "0,1" bitfld.long 0x0 0. "SC_REG_0,system control register for read/write can be locked by corrsponding bit in upper half word" "0,1" repeat.end repeat 16. (list 0x1F 0x1F 0x1F 0x1F 0x1F 0x1F 0x1F 0x1F 0x1F 0x1F 0x1F 0x1F 0x1F 0x1F 0x1F 0x1F )(list 0x0 0x4 0x8 0xC 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C ) group.long ($2+0x400)++0x3 line.long 0x0 "SCR_L$1,SYSTEM CONTROL REGISTER WITH 31BIT LOCK" bitfld.long 0x0 31. "SC_LOCK,lock bit for bit[30:0]" "0,1" hexmask.long 0x0 0.--30. 1. "SC_REG,system control register for read/write can be locked by bit[31]" repeat.end repeat 12. (list 0x1F 0x1F 0x1F 0x1F 0x1F 0x1F 0x1F 0x1F 0x1F 0x1F 0x1F 0x1F )(list 0x40 0x44 0x48 0x4C 0x50 0x54 0x58 0x5C 0x60 0x64 0x68 0x6C ) group.long ($2+0x400)++0x3 line.long 0x0 "SCR_L$1,SYSTEM CONTROL REGISTER WITH 31BIT LOCK" bitfld.long 0x0 31. "SC_LOCK,lock bit for bit[30:0]" "0,1" hexmask.long 0x0 0.--30. 1. "SC_REG,system control register for read/write can be locked by bit[31]" repeat.end repeat 16. (list 0x10 0x10 0x10 0x10 0x10 0x10 0x10 0x10 0x10 0x10 0x10 0x10 0x10 0x10 0x10 0x10 )(list 0x0 0x4 0x8 0xC 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C ) group.long ($2+0x600)++0x3 line.long 0x0 "SCR_R16W$1,SYSTEM CONTROL REGISTER WITH HALF RW HALF RO" hexmask.long.word 0x0 16.--31. 1. "SC_ROREG,system control register for read only" hexmask.long.word 0x0 0.--15. 1. "SC_REG,system control register for read/write" repeat.end repeat 16. (list 0x10 0x10 0x10 0x10 0x10 0x10 0x10 0x10 0x10 0x10 0x10 0x10 0x10 0x10 0x10 0x10 )(list 0x40 0x44 0x48 0x4C 0x50 0x54 0x58 0x5C 0x60 0x64 0x68 0x6C 0x70 0x74 0x78 0x7C ) group.long ($2+0x600)++0x3 line.long 0x0 "SCR_R16W$1,SYSTEM CONTROL REGISTER WITH HALF RW HALF RO" hexmask.long.word 0x0 16.--31. 1. "SC_ROREG,system control register for read only" hexmask.long.word 0x0 0.--15. 1. "SC_REG,system control register for read/write" repeat.end repeat 8. (list 0x10 0x10 0x10 0x10 0x10 0x10 0x10 0x10 )(list 0x80 0x84 0x88 0x8C 0x90 0x94 0x98 0x9C ) group.long ($2+0x600)++0x3 line.long 0x0 "SCR_R16W$1,SYSTEM CONTROL REGISTER WITH HALF RW HALF RO" hexmask.long.word 0x0 16.--31. 1. "SC_ROREG,system control register for read only" hexmask.long.word 0x0 0.--15. 1. "SC_REG,system control register for read/write" repeat.end tree.end elif (CORENAME()=="CORTEXA55") tree "SCR_AP" base ad:0x38200000 group.long 0x0++0x6F line.long 0x0 "SCR_RW,SYSTEM CONTROL REGISTER READ/WRITE" hexmask.long 0x0 0.--31. 1. "SC_REG,system control register setting" line.long 0x4 "SCR_RW,SYSTEM CONTROL REGISTER READ/WRITE" hexmask.long 0x4 0.--31. 1. "SC_REG,system control register setting" line.long 0x8 "SCR_RW,SYSTEM CONTROL REGISTER READ/WRITE" hexmask.long 0x8 0.--31. 1. "SC_REG,system control register setting" line.long 0xC "SCR_RW,SYSTEM CONTROL REGISTER READ/WRITE" hexmask.long 0xC 0.--31. 1. "SC_REG,system control register setting" line.long 0x10 "SCR_RW,SYSTEM CONTROL REGISTER READ/WRITE" hexmask.long 0x10 0.--31. 1. "SC_REG,system control register setting" line.long 0x14 "SCR_RW,SYSTEM CONTROL REGISTER READ/WRITE" hexmask.long 0x14 0.--31. 1. "SC_REG,system control register setting" line.long 0x18 "SCR_RW,SYSTEM CONTROL REGISTER READ/WRITE" hexmask.long 0x18 0.--31. 1. "SC_REG,system control register setting" line.long 0x1C "SCR_RW,SYSTEM CONTROL REGISTER READ/WRITE" hexmask.long 0x1C 0.--31. 1. "SC_REG,system control register setting" line.long 0x20 "SCR_RW,SYSTEM CONTROL REGISTER READ/WRITE" hexmask.long 0x20 0.--31. 1. "SC_REG,system control register setting" line.long 0x24 "SCR_RW,SYSTEM CONTROL REGISTER READ/WRITE" hexmask.long 0x24 0.--31. 1. "SC_REG,system control register setting" line.long 0x28 "SCR_RW,SYSTEM CONTROL REGISTER READ/WRITE" hexmask.long 0x28 0.--31. 1. "SC_REG,system control register setting" line.long 0x2C "SCR_RW,SYSTEM CONTROL REGISTER READ/WRITE" hexmask.long 0x2C 0.--31. 1. "SC_REG,system control register setting" line.long 0x30 "SCR_RW,SYSTEM CONTROL REGISTER READ/WRITE" hexmask.long 0x30 0.--31. 1. "SC_REG,system control register setting" line.long 0x34 "SCR_RW,SYSTEM CONTROL REGISTER READ/WRITE" hexmask.long 0x34 0.--31. 1. "SC_REG,system control register setting" line.long 0x38 "SCR_RW,SYSTEM CONTROL REGISTER READ/WRITE" hexmask.long 0x38 0.--31. 1. "SC_REG,system control register setting" line.long 0x3C "SCR_RW,SYSTEM CONTROL REGISTER READ/WRITE" hexmask.long 0x3C 0.--31. 1. "SC_REG,system control register setting" line.long 0x40 "SCR_RW,SYSTEM CONTROL REGISTER READ/WRITE" hexmask.long 0x40 0.--31. 1. "SC_REG,system control register setting" line.long 0x44 "SCR_RW,SYSTEM CONTROL REGISTER READ/WRITE" hexmask.long 0x44 0.--31. 1. "SC_REG,system control register setting" line.long 0x48 "SCR_RW,SYSTEM CONTROL REGISTER READ/WRITE" hexmask.long 0x48 0.--31. 1. "SC_REG,system control register setting" line.long 0x4C "SCR_RW,SYSTEM CONTROL REGISTER READ/WRITE" hexmask.long 0x4C 0.--31. 1. "SC_REG,system control register setting" line.long 0x50 "SCR_RW,SYSTEM CONTROL REGISTER READ/WRITE" hexmask.long 0x50 0.--31. 1. "SC_REG,system control register setting" line.long 0x54 "SCR_RW,SYSTEM CONTROL REGISTER READ/WRITE" hexmask.long 0x54 0.--31. 1. "SC_REG,system control register setting" line.long 0x58 "SCR_RW,SYSTEM CONTROL REGISTER READ/WRITE" hexmask.long 0x58 0.--31. 1. "SC_REG,system control register setting" line.long 0x5C "SCR_RW,SYSTEM CONTROL REGISTER READ/WRITE" hexmask.long 0x5C 0.--31. 1. "SC_REG,system control register setting" line.long 0x60 "SCR_RW,SYSTEM CONTROL REGISTER READ/WRITE" hexmask.long 0x60 0.--31. 1. "SC_REG,system control register setting" line.long 0x64 "SCR_RW,SYSTEM CONTROL REGISTER READ/WRITE" hexmask.long 0x64 0.--31. 1. "SC_REG,system control register setting" line.long 0x68 "SCR_RW,SYSTEM CONTROL REGISTER READ/WRITE" hexmask.long 0x68 0.--31. 1. "SC_REG,system control register setting" line.long 0x6C "SCR_RW,SYSTEM CONTROL REGISTER READ/WRITE" hexmask.long 0x6C 0.--31. 1. "SC_REG,system control register setting" rgroup.long 0x100++0xF line.long 0x0 "SCR_RO,SYSTEM CONTROL REGISTER READ ONLY" hexmask.long 0x0 0.--31. 1. "SC_REG,system control register for Read-Only status." line.long 0x4 "SCR_RO,SYSTEM CONTROL REGISTER READ ONLY" hexmask.long 0x4 0.--31. 1. "SC_REG,system control register for Read-Only status." line.long 0x8 "SCR_RO,SYSTEM CONTROL REGISTER READ ONLY" hexmask.long 0x8 0.--31. 1. "SC_REG,system control register for Read-Only status." line.long 0xC "SCR_RO,SYSTEM CONTROL REGISTER READ ONLY" hexmask.long 0xC 0.--31. 1. "SC_REG,system control register for Read-Only status." repeat 16. (list 0x10 0x10 0x10 0x10 0x10 0x10 0x10 0x10 0x10 0x10 0x10 0x10 0x10 0x10 0x10 0x10 )(list 0x0 0x4 0x8 0xC 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C ) group.long ($2+0x200)++0x3 line.long 0x0 "SCR_L$1,SYSTEM CONTROL REGISTER WITH STICKY AND LOCK" bitfld.long 0x0 31. "SC_STICKY_15,system control register used to lock the corresponding bit in lower half word or as sticky bit" "0,1" bitfld.long 0x0 30. "SC_STICKY_14,system control register used to lock the corresponding bit in lower half word or as sticky bit" "0,1" bitfld.long 0x0 29. "SC_STICKY_13,system control register used to lock the corresponding bit in lower half word or as sticky bit" "0,1" bitfld.long 0x0 28. "SC_STICKY_12,system control register used to lock the corresponding bit in lower half word or as sticky bit" "0,1" bitfld.long 0x0 27. "SC_STICKY_11,system control register used to lock the corresponding bit in lower half word or as sticky bit" "0,1" bitfld.long 0x0 26. "SC_STICKY_10,system control register used to lock the corresponding bit in lower half word or as sticky bit" "0,1" newline bitfld.long 0x0 25. "SC_STICKY_9,system control register used to lock the corresponding bit in lower half word or as sticky bit" "0,1" bitfld.long 0x0 24. "SC_STICKY_8,system control register used to lock the corresponding bit in lower half word or as sticky bit" "0,1" bitfld.long 0x0 23. "SC_STICKY_7,system control register used to lock the corresponding bit in lower half word or as sticky bit" "0,1" bitfld.long 0x0 22. "SC_STICKY_6,system control register used to lock the corresponding bit in lower half word or as sticky bit" "0,1" bitfld.long 0x0 21. "SC_STICKY_5,system control register used to lock the corresponding bit in lower half word or as sticky bit" "0,1" bitfld.long 0x0 20. "SC_STICKY_4,system control register used to lock the corresponding bit in lower half word or as sticky bit" "0,1" newline bitfld.long 0x0 19. "SC_STICKY_3,system control register used to lock the corresponding bit in lower half word or as sticky bit" "0,1" bitfld.long 0x0 18. "SC_STICKY_2,system control register used to lock the corresponding bit in lower half word or as sticky bit" "0,1" bitfld.long 0x0 17. "SC_STICKY_1,system control register used to lock the corresponding bit in lower half word or as sticky bit" "0,1" bitfld.long 0x0 16. "SC_STICKY_0,system control register used to lock the corresponding bit in lower half word or as sticky bit" "0,1" bitfld.long 0x0 15. "SC_REG_15,system control register for read/write can be locked by corrsponding bit in upper half word" "0,1" bitfld.long 0x0 14. "SC_REG_14,system control register for read/write can be locked by corrsponding bit in upper half word" "0,1" newline bitfld.long 0x0 13. "SC_REG_13,system control register for read/write can be locked by corrsponding bit in upper half word" "0,1" bitfld.long 0x0 12. "SC_REG_12,system control register for read/write can be locked by corrsponding bit in upper half word" "0,1" bitfld.long 0x0 11. "SC_REG_11,system control register for read/write can be locked by corrsponding bit in upper half word" "0,1" bitfld.long 0x0 10. "SC_REG_10,system control register for read/write can be locked by corrsponding bit in upper half word" "0,1" bitfld.long 0x0 9. "SC_REG_9,system control register for read/write can be locked by corrsponding bit in upper half word" "0,1" bitfld.long 0x0 8. "SC_REG_8,system control register for read/write can be locked by corrsponding bit in upper half word" "0,1" newline bitfld.long 0x0 7. "SC_REG_7,system control register for read/write can be locked by corrsponding bit in upper half word" "0,1" bitfld.long 0x0 6. "SC_REG_6,system control register for read/write can be locked by corrsponding bit in upper half word" "0,1" bitfld.long 0x0 5. "SC_REG_5,system control register for read/write can be locked by corrsponding bit in upper half word" "0,1" bitfld.long 0x0 4. "SC_REG_4,system control register for read/write can be locked by corrsponding bit in upper half word" "0,1" bitfld.long 0x0 3. "SC_REG_3,system control register for read/write can be locked by corrsponding bit in upper half word" "0,1" bitfld.long 0x0 2. "SC_REG_2,system control register for read/write can be locked by corrsponding bit in upper half word" "0,1" newline bitfld.long 0x0 1. "SC_REG_1,system control register for read/write can be locked by corrsponding bit in upper half word" "0,1" bitfld.long 0x0 0. "SC_REG_0,system control register for read/write can be locked by corrsponding bit in upper half word" "0,1" repeat.end repeat 16. (list 0x10 0x10 0x10 0x10 0x10 0x10 0x10 0x10 0x10 0x10 0x10 0x10 0x10 0x10 0x10 0x10 )(list 0x40 0x44 0x48 0x4C 0x50 0x54 0x58 0x5C 0x60 0x64 0x68 0x6C 0x70 0x74 0x78 0x7C ) group.long ($2+0x200)++0x3 line.long 0x0 "SCR_L$1,SYSTEM CONTROL REGISTER WITH STICKY AND LOCK" bitfld.long 0x0 31. "SC_STICKY_15,system control register used to lock the corresponding bit in lower half word or as sticky bit" "0,1" bitfld.long 0x0 30. "SC_STICKY_14,system control register used to lock the corresponding bit in lower half word or as sticky bit" "0,1" bitfld.long 0x0 29. "SC_STICKY_13,system control register used to lock the corresponding bit in lower half word or as sticky bit" "0,1" bitfld.long 0x0 28. "SC_STICKY_12,system control register used to lock the corresponding bit in lower half word or as sticky bit" "0,1" bitfld.long 0x0 27. "SC_STICKY_11,system control register used to lock the corresponding bit in lower half word or as sticky bit" "0,1" bitfld.long 0x0 26. "SC_STICKY_10,system control register used to lock the corresponding bit in lower half word or as sticky bit" "0,1" newline bitfld.long 0x0 25. "SC_STICKY_9,system control register used to lock the corresponding bit in lower half word or as sticky bit" "0,1" bitfld.long 0x0 24. "SC_STICKY_8,system control register used to lock the corresponding bit in lower half word or as sticky bit" "0,1" bitfld.long 0x0 23. "SC_STICKY_7,system control register used to lock the corresponding bit in lower half word or as sticky bit" "0,1" bitfld.long 0x0 22. "SC_STICKY_6,system control register used to lock the corresponding bit in lower half word or as sticky bit" "0,1" bitfld.long 0x0 21. "SC_STICKY_5,system control register used to lock the corresponding bit in lower half word or as sticky bit" "0,1" bitfld.long 0x0 20. "SC_STICKY_4,system control register used to lock the corresponding bit in lower half word or as sticky bit" "0,1" newline bitfld.long 0x0 19. "SC_STICKY_3,system control register used to lock the corresponding bit in lower half word or as sticky bit" "0,1" bitfld.long 0x0 18. "SC_STICKY_2,system control register used to lock the corresponding bit in lower half word or as sticky bit" "0,1" bitfld.long 0x0 17. "SC_STICKY_1,system control register used to lock the corresponding bit in lower half word or as sticky bit" "0,1" bitfld.long 0x0 16. "SC_STICKY_0,system control register used to lock the corresponding bit in lower half word or as sticky bit" "0,1" bitfld.long 0x0 15. "SC_REG_15,system control register for read/write can be locked by corrsponding bit in upper half word" "0,1" bitfld.long 0x0 14. "SC_REG_14,system control register for read/write can be locked by corrsponding bit in upper half word" "0,1" newline bitfld.long 0x0 13. "SC_REG_13,system control register for read/write can be locked by corrsponding bit in upper half word" "0,1" bitfld.long 0x0 12. "SC_REG_12,system control register for read/write can be locked by corrsponding bit in upper half word" "0,1" bitfld.long 0x0 11. "SC_REG_11,system control register for read/write can be locked by corrsponding bit in upper half word" "0,1" bitfld.long 0x0 10. "SC_REG_10,system control register for read/write can be locked by corrsponding bit in upper half word" "0,1" bitfld.long 0x0 9. "SC_REG_9,system control register for read/write can be locked by corrsponding bit in upper half word" "0,1" bitfld.long 0x0 8. "SC_REG_8,system control register for read/write can be locked by corrsponding bit in upper half word" "0,1" newline bitfld.long 0x0 7. "SC_REG_7,system control register for read/write can be locked by corrsponding bit in upper half word" "0,1" bitfld.long 0x0 6. "SC_REG_6,system control register for read/write can be locked by corrsponding bit in upper half word" "0,1" bitfld.long 0x0 5. "SC_REG_5,system control register for read/write can be locked by corrsponding bit in upper half word" "0,1" bitfld.long 0x0 4. "SC_REG_4,system control register for read/write can be locked by corrsponding bit in upper half word" "0,1" bitfld.long 0x0 3. "SC_REG_3,system control register for read/write can be locked by corrsponding bit in upper half word" "0,1" bitfld.long 0x0 2. "SC_REG_2,system control register for read/write can be locked by corrsponding bit in upper half word" "0,1" newline bitfld.long 0x0 1. "SC_REG_1,system control register for read/write can be locked by corrsponding bit in upper half word" "0,1" bitfld.long 0x0 0. "SC_REG_0,system control register for read/write can be locked by corrsponding bit in upper half word" "0,1" repeat.end repeat 4. (list 0x10 0x10 0x10 0x10 )(list 0x80 0x84 0x88 0x8C ) group.long ($2+0x200)++0x3 line.long 0x0 "SCR_L$1,SYSTEM CONTROL REGISTER WITH STICKY AND LOCK" bitfld.long 0x0 31. "SC_STICKY_15,system control register used to lock the corresponding bit in lower half word or as sticky bit" "0,1" bitfld.long 0x0 30. "SC_STICKY_14,system control register used to lock the corresponding bit in lower half word or as sticky bit" "0,1" bitfld.long 0x0 29. "SC_STICKY_13,system control register used to lock the corresponding bit in lower half word or as sticky bit" "0,1" bitfld.long 0x0 28. "SC_STICKY_12,system control register used to lock the corresponding bit in lower half word or as sticky bit" "0,1" bitfld.long 0x0 27. "SC_STICKY_11,system control register used to lock the corresponding bit in lower half word or as sticky bit" "0,1" bitfld.long 0x0 26. "SC_STICKY_10,system control register used to lock the corresponding bit in lower half word or as sticky bit" "0,1" newline bitfld.long 0x0 25. "SC_STICKY_9,system control register used to lock the corresponding bit in lower half word or as sticky bit" "0,1" bitfld.long 0x0 24. "SC_STICKY_8,system control register used to lock the corresponding bit in lower half word or as sticky bit" "0,1" bitfld.long 0x0 23. "SC_STICKY_7,system control register used to lock the corresponding bit in lower half word or as sticky bit" "0,1" bitfld.long 0x0 22. "SC_STICKY_6,system control register used to lock the corresponding bit in lower half word or as sticky bit" "0,1" bitfld.long 0x0 21. "SC_STICKY_5,system control register used to lock the corresponding bit in lower half word or as sticky bit" "0,1" bitfld.long 0x0 20. "SC_STICKY_4,system control register used to lock the corresponding bit in lower half word or as sticky bit" "0,1" newline bitfld.long 0x0 19. "SC_STICKY_3,system control register used to lock the corresponding bit in lower half word or as sticky bit" "0,1" bitfld.long 0x0 18. "SC_STICKY_2,system control register used to lock the corresponding bit in lower half word or as sticky bit" "0,1" bitfld.long 0x0 17. "SC_STICKY_1,system control register used to lock the corresponding bit in lower half word or as sticky bit" "0,1" bitfld.long 0x0 16. "SC_STICKY_0,system control register used to lock the corresponding bit in lower half word or as sticky bit" "0,1" bitfld.long 0x0 15. "SC_REG_15,system control register for read/write can be locked by corrsponding bit in upper half word" "0,1" bitfld.long 0x0 14. "SC_REG_14,system control register for read/write can be locked by corrsponding bit in upper half word" "0,1" newline bitfld.long 0x0 13. "SC_REG_13,system control register for read/write can be locked by corrsponding bit in upper half word" "0,1" bitfld.long 0x0 12. "SC_REG_12,system control register for read/write can be locked by corrsponding bit in upper half word" "0,1" bitfld.long 0x0 11. "SC_REG_11,system control register for read/write can be locked by corrsponding bit in upper half word" "0,1" bitfld.long 0x0 10. "SC_REG_10,system control register for read/write can be locked by corrsponding bit in upper half word" "0,1" bitfld.long 0x0 9. "SC_REG_9,system control register for read/write can be locked by corrsponding bit in upper half word" "0,1" bitfld.long 0x0 8. "SC_REG_8,system control register for read/write can be locked by corrsponding bit in upper half word" "0,1" newline bitfld.long 0x0 7. "SC_REG_7,system control register for read/write can be locked by corrsponding bit in upper half word" "0,1" bitfld.long 0x0 6. "SC_REG_6,system control register for read/write can be locked by corrsponding bit in upper half word" "0,1" bitfld.long 0x0 5. "SC_REG_5,system control register for read/write can be locked by corrsponding bit in upper half word" "0,1" bitfld.long 0x0 4. "SC_REG_4,system control register for read/write can be locked by corrsponding bit in upper half word" "0,1" bitfld.long 0x0 3. "SC_REG_3,system control register for read/write can be locked by corrsponding bit in upper half word" "0,1" bitfld.long 0x0 2. "SC_REG_2,system control register for read/write can be locked by corrsponding bit in upper half word" "0,1" newline bitfld.long 0x0 1. "SC_REG_1,system control register for read/write can be locked by corrsponding bit in upper half word" "0,1" bitfld.long 0x0 0. "SC_REG_0,system control register for read/write can be locked by corrsponding bit in upper half word" "0,1" repeat.end repeat 16. (list 0x1F 0x1F 0x1F 0x1F 0x1F 0x1F 0x1F 0x1F 0x1F 0x1F 0x1F 0x1F 0x1F 0x1F 0x1F 0x1F )(list 0x0 0x4 0x8 0xC 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C ) group.long ($2+0x400)++0x3 line.long 0x0 "SCR_L$1,SYSTEM CONTROL REGISTER WITH 31BIT LOCK" bitfld.long 0x0 31. "SC_LOCK,lock bit for bit[30:0]" "0,1" hexmask.long 0x0 0.--30. 1. "SC_REG,system control register for read/write can be locked by bit[31]" repeat.end repeat 12. (list 0x1F 0x1F 0x1F 0x1F 0x1F 0x1F 0x1F 0x1F 0x1F 0x1F 0x1F 0x1F )(list 0x40 0x44 0x48 0x4C 0x50 0x54 0x58 0x5C 0x60 0x64 0x68 0x6C ) group.long ($2+0x400)++0x3 line.long 0x0 "SCR_L$1,SYSTEM CONTROL REGISTER WITH 31BIT LOCK" bitfld.long 0x0 31. "SC_LOCK,lock bit for bit[30:0]" "0,1" hexmask.long 0x0 0.--30. 1. "SC_REG,system control register for read/write can be locked by bit[31]" repeat.end repeat 16. (list 0x10 0x10 0x10 0x10 0x10 0x10 0x10 0x10 0x10 0x10 0x10 0x10 0x10 0x10 0x10 0x10 )(list 0x0 0x4 0x8 0xC 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C ) group.long ($2+0x600)++0x3 line.long 0x0 "SCR_R16W$1,SYSTEM CONTROL REGISTER WITH HALF RW HALF RO" hexmask.long.word 0x0 16.--31. 1. "SC_ROREG,system control register for read only" hexmask.long.word 0x0 0.--15. 1. "SC_REG,system control register for read/write" repeat.end repeat 16. (list 0x10 0x10 0x10 0x10 0x10 0x10 0x10 0x10 0x10 0x10 0x10 0x10 0x10 0x10 0x10 0x10 )(list 0x40 0x44 0x48 0x4C 0x50 0x54 0x58 0x5C 0x60 0x64 0x68 0x6C 0x70 0x74 0x78 0x7C ) group.long ($2+0x600)++0x3 line.long 0x0 "SCR_R16W$1,SYSTEM CONTROL REGISTER WITH HALF RW HALF RO" hexmask.long.word 0x0 16.--31. 1. "SC_ROREG,system control register for read only" hexmask.long.word 0x0 0.--15. 1. "SC_REG,system control register for read/write" repeat.end repeat 8. (list 0x10 0x10 0x10 0x10 0x10 0x10 0x10 0x10 )(list 0x80 0x84 0x88 0x8C 0x90 0x94 0x98 0x9C ) group.long ($2+0x600)++0x3 line.long 0x0 "SCR_R16W$1,SYSTEM CONTROL REGISTER WITH HALF RW HALF RO" hexmask.long.word 0x0 16.--31. 1. "SC_ROREG,system control register for read only" hexmask.long.word 0x0 0.--15. 1. "SC_REG,system control register for read/write" repeat.end tree.end tree "SCR_SAFETY" base ad:0x3C200000 group.long 0x0++0x6F line.long 0x0 "SCR_RW,SYSTEM CONTROL REGISTER READ/WRITE" hexmask.long 0x0 0.--31. 1. "SC_REG,system control register setting" line.long 0x4 "SCR_RW,SYSTEM CONTROL REGISTER READ/WRITE" hexmask.long 0x4 0.--31. 1. "SC_REG,system control register setting" line.long 0x8 "SCR_RW,SYSTEM CONTROL REGISTER READ/WRITE" hexmask.long 0x8 0.--31. 1. "SC_REG,system control register setting" line.long 0xC "SCR_RW,SYSTEM CONTROL REGISTER READ/WRITE" hexmask.long 0xC 0.--31. 1. "SC_REG,system control register setting" line.long 0x10 "SCR_RW,SYSTEM CONTROL REGISTER READ/WRITE" hexmask.long 0x10 0.--31. 1. "SC_REG,system control register setting" line.long 0x14 "SCR_RW,SYSTEM CONTROL REGISTER READ/WRITE" hexmask.long 0x14 0.--31. 1. "SC_REG,system control register setting" line.long 0x18 "SCR_RW,SYSTEM CONTROL REGISTER READ/WRITE" hexmask.long 0x18 0.--31. 1. "SC_REG,system control register setting" line.long 0x1C "SCR_RW,SYSTEM CONTROL REGISTER READ/WRITE" hexmask.long 0x1C 0.--31. 1. "SC_REG,system control register setting" line.long 0x20 "SCR_RW,SYSTEM CONTROL REGISTER READ/WRITE" hexmask.long 0x20 0.--31. 1. "SC_REG,system control register setting" line.long 0x24 "SCR_RW,SYSTEM CONTROL REGISTER READ/WRITE" hexmask.long 0x24 0.--31. 1. "SC_REG,system control register setting" line.long 0x28 "SCR_RW,SYSTEM CONTROL REGISTER READ/WRITE" hexmask.long 0x28 0.--31. 1. "SC_REG,system control register setting" line.long 0x2C "SCR_RW,SYSTEM CONTROL REGISTER READ/WRITE" hexmask.long 0x2C 0.--31. 1. "SC_REG,system control register setting" line.long 0x30 "SCR_RW,SYSTEM CONTROL REGISTER READ/WRITE" hexmask.long 0x30 0.--31. 1. "SC_REG,system control register setting" line.long 0x34 "SCR_RW,SYSTEM CONTROL REGISTER READ/WRITE" hexmask.long 0x34 0.--31. 1. "SC_REG,system control register setting" line.long 0x38 "SCR_RW,SYSTEM CONTROL REGISTER READ/WRITE" hexmask.long 0x38 0.--31. 1. "SC_REG,system control register setting" line.long 0x3C "SCR_RW,SYSTEM CONTROL REGISTER READ/WRITE" hexmask.long 0x3C 0.--31. 1. "SC_REG,system control register setting" line.long 0x40 "SCR_RW,SYSTEM CONTROL REGISTER READ/WRITE" hexmask.long 0x40 0.--31. 1. "SC_REG,system control register setting" line.long 0x44 "SCR_RW,SYSTEM CONTROL REGISTER READ/WRITE" hexmask.long 0x44 0.--31. 1. "SC_REG,system control register setting" line.long 0x48 "SCR_RW,SYSTEM CONTROL REGISTER READ/WRITE" hexmask.long 0x48 0.--31. 1. "SC_REG,system control register setting" line.long 0x4C "SCR_RW,SYSTEM CONTROL REGISTER READ/WRITE" hexmask.long 0x4C 0.--31. 1. "SC_REG,system control register setting" line.long 0x50 "SCR_RW,SYSTEM CONTROL REGISTER READ/WRITE" hexmask.long 0x50 0.--31. 1. "SC_REG,system control register setting" line.long 0x54 "SCR_RW,SYSTEM CONTROL REGISTER READ/WRITE" hexmask.long 0x54 0.--31. 1. "SC_REG,system control register setting" line.long 0x58 "SCR_RW,SYSTEM CONTROL REGISTER READ/WRITE" hexmask.long 0x58 0.--31. 1. "SC_REG,system control register setting" line.long 0x5C "SCR_RW,SYSTEM CONTROL REGISTER READ/WRITE" hexmask.long 0x5C 0.--31. 1. "SC_REG,system control register setting" line.long 0x60 "SCR_RW,SYSTEM CONTROL REGISTER READ/WRITE" hexmask.long 0x60 0.--31. 1. "SC_REG,system control register setting" line.long 0x64 "SCR_RW,SYSTEM CONTROL REGISTER READ/WRITE" hexmask.long 0x64 0.--31. 1. "SC_REG,system control register setting" line.long 0x68 "SCR_RW,SYSTEM CONTROL REGISTER READ/WRITE" hexmask.long 0x68 0.--31. 1. "SC_REG,system control register setting" line.long 0x6C "SCR_RW,SYSTEM CONTROL REGISTER READ/WRITE" hexmask.long 0x6C 0.--31. 1. "SC_REG,system control register setting" rgroup.long 0x100++0xF line.long 0x0 "SCR_RO,SYSTEM CONTROL REGISTER READ ONLY" hexmask.long 0x0 0.--31. 1. "SC_REG,system control register for Read-Only status." line.long 0x4 "SCR_RO,SYSTEM CONTROL REGISTER READ ONLY" hexmask.long 0x4 0.--31. 1. "SC_REG,system control register for Read-Only status." line.long 0x8 "SCR_RO,SYSTEM CONTROL REGISTER READ ONLY" hexmask.long 0x8 0.--31. 1. "SC_REG,system control register for Read-Only status." line.long 0xC "SCR_RO,SYSTEM CONTROL REGISTER READ ONLY" hexmask.long 0xC 0.--31. 1. "SC_REG,system control register for Read-Only status." repeat 16. (list 0x10 0x10 0x10 0x10 0x10 0x10 0x10 0x10 0x10 0x10 0x10 0x10 0x10 0x10 0x10 0x10 )(list 0x0 0x4 0x8 0xC 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C ) group.long ($2+0x200)++0x3 line.long 0x0 "SCR_L$1,SYSTEM CONTROL REGISTER WITH STICKY AND LOCK" bitfld.long 0x0 31. "SC_STICKY_15,system control register used to lock the corresponding bit in lower half word or as sticky bit" "0,1" bitfld.long 0x0 30. "SC_STICKY_14,system control register used to lock the corresponding bit in lower half word or as sticky bit" "0,1" bitfld.long 0x0 29. "SC_STICKY_13,system control register used to lock the corresponding bit in lower half word or as sticky bit" "0,1" bitfld.long 0x0 28. "SC_STICKY_12,system control register used to lock the corresponding bit in lower half word or as sticky bit" "0,1" bitfld.long 0x0 27. "SC_STICKY_11,system control register used to lock the corresponding bit in lower half word or as sticky bit" "0,1" bitfld.long 0x0 26. "SC_STICKY_10,system control register used to lock the corresponding bit in lower half word or as sticky bit" "0,1" newline bitfld.long 0x0 25. "SC_STICKY_9,system control register used to lock the corresponding bit in lower half word or as sticky bit" "0,1" bitfld.long 0x0 24. "SC_STICKY_8,system control register used to lock the corresponding bit in lower half word or as sticky bit" "0,1" bitfld.long 0x0 23. "SC_STICKY_7,system control register used to lock the corresponding bit in lower half word or as sticky bit" "0,1" bitfld.long 0x0 22. "SC_STICKY_6,system control register used to lock the corresponding bit in lower half word or as sticky bit" "0,1" bitfld.long 0x0 21. "SC_STICKY_5,system control register used to lock the corresponding bit in lower half word or as sticky bit" "0,1" bitfld.long 0x0 20. "SC_STICKY_4,system control register used to lock the corresponding bit in lower half word or as sticky bit" "0,1" newline bitfld.long 0x0 19. "SC_STICKY_3,system control register used to lock the corresponding bit in lower half word or as sticky bit" "0,1" bitfld.long 0x0 18. "SC_STICKY_2,system control register used to lock the corresponding bit in lower half word or as sticky bit" "0,1" bitfld.long 0x0 17. "SC_STICKY_1,system control register used to lock the corresponding bit in lower half word or as sticky bit" "0,1" bitfld.long 0x0 16. "SC_STICKY_0,system control register used to lock the corresponding bit in lower half word or as sticky bit" "0,1" bitfld.long 0x0 15. "SC_REG_15,system control register for read/write can be locked by corrsponding bit in upper half word" "0,1" bitfld.long 0x0 14. "SC_REG_14,system control register for read/write can be locked by corrsponding bit in upper half word" "0,1" newline bitfld.long 0x0 13. "SC_REG_13,system control register for read/write can be locked by corrsponding bit in upper half word" "0,1" bitfld.long 0x0 12. "SC_REG_12,system control register for read/write can be locked by corrsponding bit in upper half word" "0,1" bitfld.long 0x0 11. "SC_REG_11,system control register for read/write can be locked by corrsponding bit in upper half word" "0,1" bitfld.long 0x0 10. "SC_REG_10,system control register for read/write can be locked by corrsponding bit in upper half word" "0,1" bitfld.long 0x0 9. "SC_REG_9,system control register for read/write can be locked by corrsponding bit in upper half word" "0,1" bitfld.long 0x0 8. "SC_REG_8,system control register for read/write can be locked by corrsponding bit in upper half word" "0,1" newline bitfld.long 0x0 7. "SC_REG_7,system control register for read/write can be locked by corrsponding bit in upper half word" "0,1" bitfld.long 0x0 6. "SC_REG_6,system control register for read/write can be locked by corrsponding bit in upper half word" "0,1" bitfld.long 0x0 5. "SC_REG_5,system control register for read/write can be locked by corrsponding bit in upper half word" "0,1" bitfld.long 0x0 4. "SC_REG_4,system control register for read/write can be locked by corrsponding bit in upper half word" "0,1" bitfld.long 0x0 3. "SC_REG_3,system control register for read/write can be locked by corrsponding bit in upper half word" "0,1" bitfld.long 0x0 2. "SC_REG_2,system control register for read/write can be locked by corrsponding bit in upper half word" "0,1" newline bitfld.long 0x0 1. "SC_REG_1,system control register for read/write can be locked by corrsponding bit in upper half word" "0,1" bitfld.long 0x0 0. "SC_REG_0,system control register for read/write can be locked by corrsponding bit in upper half word" "0,1" repeat.end repeat 16. (list 0x10 0x10 0x10 0x10 0x10 0x10 0x10 0x10 0x10 0x10 0x10 0x10 0x10 0x10 0x10 0x10 )(list 0x40 0x44 0x48 0x4C 0x50 0x54 0x58 0x5C 0x60 0x64 0x68 0x6C 0x70 0x74 0x78 0x7C ) group.long ($2+0x200)++0x3 line.long 0x0 "SCR_L$1,SYSTEM CONTROL REGISTER WITH STICKY AND LOCK" bitfld.long 0x0 31. "SC_STICKY_15,system control register used to lock the corresponding bit in lower half word or as sticky bit" "0,1" bitfld.long 0x0 30. "SC_STICKY_14,system control register used to lock the corresponding bit in lower half word or as sticky bit" "0,1" bitfld.long 0x0 29. "SC_STICKY_13,system control register used to lock the corresponding bit in lower half word or as sticky bit" "0,1" bitfld.long 0x0 28. "SC_STICKY_12,system control register used to lock the corresponding bit in lower half word or as sticky bit" "0,1" bitfld.long 0x0 27. "SC_STICKY_11,system control register used to lock the corresponding bit in lower half word or as sticky bit" "0,1" bitfld.long 0x0 26. "SC_STICKY_10,system control register used to lock the corresponding bit in lower half word or as sticky bit" "0,1" newline bitfld.long 0x0 25. "SC_STICKY_9,system control register used to lock the corresponding bit in lower half word or as sticky bit" "0,1" bitfld.long 0x0 24. "SC_STICKY_8,system control register used to lock the corresponding bit in lower half word or as sticky bit" "0,1" bitfld.long 0x0 23. "SC_STICKY_7,system control register used to lock the corresponding bit in lower half word or as sticky bit" "0,1" bitfld.long 0x0 22. "SC_STICKY_6,system control register used to lock the corresponding bit in lower half word or as sticky bit" "0,1" bitfld.long 0x0 21. "SC_STICKY_5,system control register used to lock the corresponding bit in lower half word or as sticky bit" "0,1" bitfld.long 0x0 20. "SC_STICKY_4,system control register used to lock the corresponding bit in lower half word or as sticky bit" "0,1" newline bitfld.long 0x0 19. "SC_STICKY_3,system control register used to lock the corresponding bit in lower half word or as sticky bit" "0,1" bitfld.long 0x0 18. "SC_STICKY_2,system control register used to lock the corresponding bit in lower half word or as sticky bit" "0,1" bitfld.long 0x0 17. "SC_STICKY_1,system control register used to lock the corresponding bit in lower half word or as sticky bit" "0,1" bitfld.long 0x0 16. "SC_STICKY_0,system control register used to lock the corresponding bit in lower half word or as sticky bit" "0,1" bitfld.long 0x0 15. "SC_REG_15,system control register for read/write can be locked by corrsponding bit in upper half word" "0,1" bitfld.long 0x0 14. "SC_REG_14,system control register for read/write can be locked by corrsponding bit in upper half word" "0,1" newline bitfld.long 0x0 13. "SC_REG_13,system control register for read/write can be locked by corrsponding bit in upper half word" "0,1" bitfld.long 0x0 12. "SC_REG_12,system control register for read/write can be locked by corrsponding bit in upper half word" "0,1" bitfld.long 0x0 11. "SC_REG_11,system control register for read/write can be locked by corrsponding bit in upper half word" "0,1" bitfld.long 0x0 10. "SC_REG_10,system control register for read/write can be locked by corrsponding bit in upper half word" "0,1" bitfld.long 0x0 9. "SC_REG_9,system control register for read/write can be locked by corrsponding bit in upper half word" "0,1" bitfld.long 0x0 8. "SC_REG_8,system control register for read/write can be locked by corrsponding bit in upper half word" "0,1" newline bitfld.long 0x0 7. "SC_REG_7,system control register for read/write can be locked by corrsponding bit in upper half word" "0,1" bitfld.long 0x0 6. "SC_REG_6,system control register for read/write can be locked by corrsponding bit in upper half word" "0,1" bitfld.long 0x0 5. "SC_REG_5,system control register for read/write can be locked by corrsponding bit in upper half word" "0,1" bitfld.long 0x0 4. "SC_REG_4,system control register for read/write can be locked by corrsponding bit in upper half word" "0,1" bitfld.long 0x0 3. "SC_REG_3,system control register for read/write can be locked by corrsponding bit in upper half word" "0,1" bitfld.long 0x0 2. "SC_REG_2,system control register for read/write can be locked by corrsponding bit in upper half word" "0,1" newline bitfld.long 0x0 1. "SC_REG_1,system control register for read/write can be locked by corrsponding bit in upper half word" "0,1" bitfld.long 0x0 0. "SC_REG_0,system control register for read/write can be locked by corrsponding bit in upper half word" "0,1" repeat.end repeat 4. (list 0x10 0x10 0x10 0x10 )(list 0x80 0x84 0x88 0x8C ) group.long ($2+0x200)++0x3 line.long 0x0 "SCR_L$1,SYSTEM CONTROL REGISTER WITH STICKY AND LOCK" bitfld.long 0x0 31. "SC_STICKY_15,system control register used to lock the corresponding bit in lower half word or as sticky bit" "0,1" bitfld.long 0x0 30. "SC_STICKY_14,system control register used to lock the corresponding bit in lower half word or as sticky bit" "0,1" bitfld.long 0x0 29. "SC_STICKY_13,system control register used to lock the corresponding bit in lower half word or as sticky bit" "0,1" bitfld.long 0x0 28. "SC_STICKY_12,system control register used to lock the corresponding bit in lower half word or as sticky bit" "0,1" bitfld.long 0x0 27. "SC_STICKY_11,system control register used to lock the corresponding bit in lower half word or as sticky bit" "0,1" bitfld.long 0x0 26. "SC_STICKY_10,system control register used to lock the corresponding bit in lower half word or as sticky bit" "0,1" newline bitfld.long 0x0 25. "SC_STICKY_9,system control register used to lock the corresponding bit in lower half word or as sticky bit" "0,1" bitfld.long 0x0 24. "SC_STICKY_8,system control register used to lock the corresponding bit in lower half word or as sticky bit" "0,1" bitfld.long 0x0 23. "SC_STICKY_7,system control register used to lock the corresponding bit in lower half word or as sticky bit" "0,1" bitfld.long 0x0 22. "SC_STICKY_6,system control register used to lock the corresponding bit in lower half word or as sticky bit" "0,1" bitfld.long 0x0 21. "SC_STICKY_5,system control register used to lock the corresponding bit in lower half word or as sticky bit" "0,1" bitfld.long 0x0 20. "SC_STICKY_4,system control register used to lock the corresponding bit in lower half word or as sticky bit" "0,1" newline bitfld.long 0x0 19. "SC_STICKY_3,system control register used to lock the corresponding bit in lower half word or as sticky bit" "0,1" bitfld.long 0x0 18. "SC_STICKY_2,system control register used to lock the corresponding bit in lower half word or as sticky bit" "0,1" bitfld.long 0x0 17. "SC_STICKY_1,system control register used to lock the corresponding bit in lower half word or as sticky bit" "0,1" bitfld.long 0x0 16. "SC_STICKY_0,system control register used to lock the corresponding bit in lower half word or as sticky bit" "0,1" bitfld.long 0x0 15. "SC_REG_15,system control register for read/write can be locked by corrsponding bit in upper half word" "0,1" bitfld.long 0x0 14. "SC_REG_14,system control register for read/write can be locked by corrsponding bit in upper half word" "0,1" newline bitfld.long 0x0 13. "SC_REG_13,system control register for read/write can be locked by corrsponding bit in upper half word" "0,1" bitfld.long 0x0 12. "SC_REG_12,system control register for read/write can be locked by corrsponding bit in upper half word" "0,1" bitfld.long 0x0 11. "SC_REG_11,system control register for read/write can be locked by corrsponding bit in upper half word" "0,1" bitfld.long 0x0 10. "SC_REG_10,system control register for read/write can be locked by corrsponding bit in upper half word" "0,1" bitfld.long 0x0 9. "SC_REG_9,system control register for read/write can be locked by corrsponding bit in upper half word" "0,1" bitfld.long 0x0 8. "SC_REG_8,system control register for read/write can be locked by corrsponding bit in upper half word" "0,1" newline bitfld.long 0x0 7. "SC_REG_7,system control register for read/write can be locked by corrsponding bit in upper half word" "0,1" bitfld.long 0x0 6. "SC_REG_6,system control register for read/write can be locked by corrsponding bit in upper half word" "0,1" bitfld.long 0x0 5. "SC_REG_5,system control register for read/write can be locked by corrsponding bit in upper half word" "0,1" bitfld.long 0x0 4. "SC_REG_4,system control register for read/write can be locked by corrsponding bit in upper half word" "0,1" bitfld.long 0x0 3. "SC_REG_3,system control register for read/write can be locked by corrsponding bit in upper half word" "0,1" bitfld.long 0x0 2. "SC_REG_2,system control register for read/write can be locked by corrsponding bit in upper half word" "0,1" newline bitfld.long 0x0 1. "SC_REG_1,system control register for read/write can be locked by corrsponding bit in upper half word" "0,1" bitfld.long 0x0 0. "SC_REG_0,system control register for read/write can be locked by corrsponding bit in upper half word" "0,1" repeat.end repeat 16. (list 0x1F 0x1F 0x1F 0x1F 0x1F 0x1F 0x1F 0x1F 0x1F 0x1F 0x1F 0x1F 0x1F 0x1F 0x1F 0x1F )(list 0x0 0x4 0x8 0xC 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C ) group.long ($2+0x400)++0x3 line.long 0x0 "SCR_L$1,SYSTEM CONTROL REGISTER WITH 31BIT LOCK" bitfld.long 0x0 31. "SC_LOCK,lock bit for bit[30:0]" "0,1" hexmask.long 0x0 0.--30. 1. "SC_REG,system control register for read/write can be locked by bit[31]" repeat.end repeat 12. (list 0x1F 0x1F 0x1F 0x1F 0x1F 0x1F 0x1F 0x1F 0x1F 0x1F 0x1F 0x1F )(list 0x40 0x44 0x48 0x4C 0x50 0x54 0x58 0x5C 0x60 0x64 0x68 0x6C ) group.long ($2+0x400)++0x3 line.long 0x0 "SCR_L$1,SYSTEM CONTROL REGISTER WITH 31BIT LOCK" bitfld.long 0x0 31. "SC_LOCK,lock bit for bit[30:0]" "0,1" hexmask.long 0x0 0.--30. 1. "SC_REG,system control register for read/write can be locked by bit[31]" repeat.end repeat 16. (list 0x10 0x10 0x10 0x10 0x10 0x10 0x10 0x10 0x10 0x10 0x10 0x10 0x10 0x10 0x10 0x10 )(list 0x0 0x4 0x8 0xC 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C ) group.long ($2+0x600)++0x3 line.long 0x0 "SCR_R16W$1,SYSTEM CONTROL REGISTER WITH HALF RW HALF RO" hexmask.long.word 0x0 16.--31. 1. "SC_ROREG,system control register for read only" hexmask.long.word 0x0 0.--15. 1. "SC_REG,system control register for read/write" repeat.end repeat 16. (list 0x10 0x10 0x10 0x10 0x10 0x10 0x10 0x10 0x10 0x10 0x10 0x10 0x10 0x10 0x10 0x10 )(list 0x40 0x44 0x48 0x4C 0x50 0x54 0x58 0x5C 0x60 0x64 0x68 0x6C 0x70 0x74 0x78 0x7C ) group.long ($2+0x600)++0x3 line.long 0x0 "SCR_R16W$1,SYSTEM CONTROL REGISTER WITH HALF RW HALF RO" hexmask.long.word 0x0 16.--31. 1. "SC_ROREG,system control register for read only" hexmask.long.word 0x0 0.--15. 1. "SC_REG,system control register for read/write" repeat.end repeat 8. (list 0x10 0x10 0x10 0x10 0x10 0x10 0x10 0x10 )(list 0x80 0x84 0x88 0x8C 0x90 0x94 0x98 0x9C ) group.long ($2+0x600)++0x3 line.long 0x0 "SCR_R16W$1,SYSTEM CONTROL REGISTER WITH HALF RW HALF RO" hexmask.long.word 0x0 16.--31. 1. "SC_ROREG,system control register for read only" hexmask.long.word 0x0 0.--15. 1. "SC_REG,system control register for read/write" repeat.end tree.end endif tree.end tree "SEC_STORAGE (Secure Storage)" sif (CORENAME()=="CORTEXR5F") tree "SEC_STORAGE1" base ad:0xF18A0000 group.long 0x0++0x23 line.long 0x0 "VLK,volatile key storage" hexmask.long 0x0 0.--31. 1. "VLK,volatile key" line.long 0x4 "VLK,volatile key storage" hexmask.long 0x4 0.--31. 1. "VLK,volatile key" line.long 0x8 "VLK,volatile key storage" hexmask.long 0x8 0.--31. 1. "VLK,volatile key" line.long 0xC "VLK,volatile key storage" hexmask.long 0xC 0.--31. 1. "VLK,volatile key" line.long 0x10 "VLK,volatile key storage" hexmask.long 0x10 0.--31. 1. "VLK,volatile key" line.long 0x14 "VLK,volatile key storage" hexmask.long 0x14 0.--31. 1. "VLK,volatile key" line.long 0x18 "VLK,volatile key storage" hexmask.long 0x18 0.--31. 1. "VLK,volatile key" line.long 0x1C "VLK,volatile key storage" hexmask.long 0x1C 0.--31. 1. "VLK,volatile key" line.long 0x20 "VLK_CRC,volatile key CRC" hexmask.long 0x20 0.--31. 1. "VLK_CRC,VLK_CRC" group.long 0x30++0x13 line.long 0x0 "VLK_HLOCK_AP,0: vlk key can be used by AP 1: vlk key can't be used by AP" bitfld.long 0x0 0. "LOCK,AP core permission" "0,1" line.long 0x4 "VLK_HLOCK_SAFETY,0: vlk key can be used by SAFETY 1: vlk key can't be used by SAFETY" bitfld.long 0x4 0. "LOCK,SAFETY core permission" "0,1" line.long 0x8 "VLK_PROT,0: vlk key not protected by tamper 1: vlk key protected by tamper" bitfld.long 0x8 0. "PROT,tamper protected permission" "0,1" line.long 0xC "VLK_LOCK,once set. locked for read & write for VLK & VLK_CRC. locked for write to VLK_HLOCK_AP/SAFETY" bitfld.long 0xC 0. "LOCK,lock permission" "0,1" line.long 0x10 "VLK_CRC_EN,1: vlk_crc enable 0 : vlk_crc disable" bitfld.long 0x10 4. "ALL_LOW,crc check reslut is 0x00000000" "0,1" bitfld.long 0x10 3. "ALL_HIGH,crc check reslut is 0xFFFFFFFF" "0,1" bitfld.long 0x10 2. "ERROR,crc check error" "0,1" bitfld.long 0x10 1. "DONE,crc check done" "0,1" bitfld.long 0x10 0. "EN,vlk_crc enable or not" "0,1" group.long 0x50++0x7 line.long 0x0 "VIO_MASK,Secure Violation Mask" hexmask.long.byte 0x0 0.--7. 1. "MASK,default 8'b11111111 means all disabled" line.long 0x4 "VIO_MASK_LOCK,sticky bit. set to lock VIO_MASK" bitfld.long 0x4 0. "LOCK,lock permission" "0,1" repeat 16. (list 0x1 0x1 0x1 0x1 0x1 0x1 0x1 0x1 0x2 0x2 0x2 0x2 0x2 0x2 0x2 0x2 )(list 0x0 0x4 0x8 0xC 0x10 0x14 0x18 0x1C 0x100 0x104 0x108 0x10C 0x110 0x114 0x118 0x11C ) group.long ($2+0x100)++0x3 line.long 0x0 "GP_$1,General Purpose Storage" hexmask.long 0x0 0.--31. 1. "GP,General Purpose Storage" repeat.end repeat 8. (list 0x3 0x3 0x3 0x3 0x3 0x3 0x3 0x3 )(list 0x200 0x204 0x208 0x20C 0x210 0x214 0x218 0x21C ) group.long ($2+0x100)++0x3 line.long 0x0 "GP_$1,General Purpose Storage" hexmask.long 0x0 0.--31. 1. "GP,General Purpose Storage" repeat.end group.long 0x120++0x7 line.long 0x0 "GP_1_PROT,0: gp_1 not protected by tamper 1: gp_1 protected by tamper" bitfld.long 0x0 0. "PROT,tamper protected permission" "0,1" line.long 0x4 "GP_1_LOCK,once set. locked for write to GP_1" bitfld.long 0x4 0. "LOCK,lock permission" "0,1" group.long 0x220++0x7 line.long 0x0 "GP_2_PROT,0: gp_2 not protected by tamper 1: gp_2 protected by tamper" bitfld.long 0x0 0. "PROT,tamper protected permission" "0,1" line.long 0x4 "GP_2_LOCK,once set. locked for write to GP_2" bitfld.long 0x4 0. "LOCK,lock permission" "0,1" group.long 0x320++0x7 line.long 0x0 "GP_3_PROT,0: gp_3 not protected by tamper 1: gp_3 protected by tamper" bitfld.long 0x0 0. "PROT,tamper protected permission" "0,1" line.long 0x4 "GP_3_LOCK,once set. locked for write to GP_3" bitfld.long 0x4 0. "LOCK,lock permission" "0,1" tree.end tree "SEC_STORAGE2" base ad:0xF18B0000 group.long 0x0++0x23 line.long 0x0 "VLK,volatile key storage" hexmask.long 0x0 0.--31. 1. "VLK,volatile key" line.long 0x4 "VLK,volatile key storage" hexmask.long 0x4 0.--31. 1. "VLK,volatile key" line.long 0x8 "VLK,volatile key storage" hexmask.long 0x8 0.--31. 1. "VLK,volatile key" line.long 0xC "VLK,volatile key storage" hexmask.long 0xC 0.--31. 1. "VLK,volatile key" line.long 0x10 "VLK,volatile key storage" hexmask.long 0x10 0.--31. 1. "VLK,volatile key" line.long 0x14 "VLK,volatile key storage" hexmask.long 0x14 0.--31. 1. "VLK,volatile key" line.long 0x18 "VLK,volatile key storage" hexmask.long 0x18 0.--31. 1. "VLK,volatile key" line.long 0x1C "VLK,volatile key storage" hexmask.long 0x1C 0.--31. 1. "VLK,volatile key" line.long 0x20 "VLK_CRC,volatile key CRC" hexmask.long 0x20 0.--31. 1. "VLK_CRC,VLK_CRC" group.long 0x30++0x13 line.long 0x0 "VLK_HLOCK_AP,0: vlk key can be used by AP 1: vlk key can't be used by AP" bitfld.long 0x0 0. "LOCK,AP core permission" "0,1" line.long 0x4 "VLK_HLOCK_SAFETY,0: vlk key can be used by SAFETY 1: vlk key can't be used by SAFETY" bitfld.long 0x4 0. "LOCK,SAFETY core permission" "0,1" line.long 0x8 "VLK_PROT,0: vlk key not protected by tamper 1: vlk key protected by tamper" bitfld.long 0x8 0. "PROT,tamper protected permission" "0,1" line.long 0xC "VLK_LOCK,once set. locked for read & write for VLK & VLK_CRC. locked for write to VLK_HLOCK_AP/SAFETY" bitfld.long 0xC 0. "LOCK,lock permission" "0,1" line.long 0x10 "VLK_CRC_EN,1: vlk_crc enable 0 : vlk_crc disable" bitfld.long 0x10 4. "ALL_LOW,crc check reslut is 0x00000000" "0,1" bitfld.long 0x10 3. "ALL_HIGH,crc check reslut is 0xFFFFFFFF" "0,1" bitfld.long 0x10 2. "ERROR,crc check error" "0,1" bitfld.long 0x10 1. "DONE,crc check done" "0,1" bitfld.long 0x10 0. "EN,vlk_crc enable or not" "0,1" group.long 0x50++0x7 line.long 0x0 "VIO_MASK,Secure Violation Mask" hexmask.long.byte 0x0 0.--7. 1. "MASK,default 8'b11111111 means all disabled" line.long 0x4 "VIO_MASK_LOCK,sticky bit. set to lock VIO_MASK" bitfld.long 0x4 0. "LOCK,lock permission" "0,1" repeat 16. (list 0x1 0x1 0x1 0x1 0x1 0x1 0x1 0x1 0x2 0x2 0x2 0x2 0x2 0x2 0x2 0x2 )(list 0x0 0x4 0x8 0xC 0x10 0x14 0x18 0x1C 0x100 0x104 0x108 0x10C 0x110 0x114 0x118 0x11C ) group.long ($2+0x100)++0x3 line.long 0x0 "GP_$1,General Purpose Storage" hexmask.long 0x0 0.--31. 1. "GP,General Purpose Storage" repeat.end repeat 8. (list 0x3 0x3 0x3 0x3 0x3 0x3 0x3 0x3 )(list 0x200 0x204 0x208 0x20C 0x210 0x214 0x218 0x21C ) group.long ($2+0x100)++0x3 line.long 0x0 "GP_$1,General Purpose Storage" hexmask.long 0x0 0.--31. 1. "GP,General Purpose Storage" repeat.end group.long 0x120++0x7 line.long 0x0 "GP_1_PROT,0: gp_1 not protected by tamper 1: gp_1 protected by tamper" bitfld.long 0x0 0. "PROT,tamper protected permission" "0,1" line.long 0x4 "GP_1_LOCK,once set. locked for write to GP_1" bitfld.long 0x4 0. "LOCK,lock permission" "0,1" group.long 0x220++0x7 line.long 0x0 "GP_2_PROT,0: gp_2 not protected by tamper 1: gp_2 protected by tamper" bitfld.long 0x0 0. "PROT,tamper protected permission" "0,1" line.long 0x4 "GP_2_LOCK,once set. locked for write to GP_2" bitfld.long 0x4 0. "LOCK,lock permission" "0,1" group.long 0x320++0x7 line.long 0x0 "GP_3_PROT,0: gp_3 not protected by tamper 1: gp_3 protected by tamper" bitfld.long 0x0 0. "PROT,tamper protected permission" "0,1" line.long 0x4 "GP_3_LOCK,once set. locked for write to GP_3" bitfld.long 0x4 0. "LOCK,lock permission" "0,1" tree.end elif (CORENAME()=="CORTEXA55") tree "SEC_STORAGE1" base ad:0x318A0000 group.long 0x0++0x23 line.long 0x0 "VLK,volatile key storage" hexmask.long 0x0 0.--31. 1. "VLK,volatile key" line.long 0x4 "VLK,volatile key storage" hexmask.long 0x4 0.--31. 1. "VLK,volatile key" line.long 0x8 "VLK,volatile key storage" hexmask.long 0x8 0.--31. 1. "VLK,volatile key" line.long 0xC "VLK,volatile key storage" hexmask.long 0xC 0.--31. 1. "VLK,volatile key" line.long 0x10 "VLK,volatile key storage" hexmask.long 0x10 0.--31. 1. "VLK,volatile key" line.long 0x14 "VLK,volatile key storage" hexmask.long 0x14 0.--31. 1. "VLK,volatile key" line.long 0x18 "VLK,volatile key storage" hexmask.long 0x18 0.--31. 1. "VLK,volatile key" line.long 0x1C "VLK,volatile key storage" hexmask.long 0x1C 0.--31. 1. "VLK,volatile key" line.long 0x20 "VLK_CRC,volatile key CRC" hexmask.long 0x20 0.--31. 1. "VLK_CRC,VLK_CRC" group.long 0x30++0x13 line.long 0x0 "VLK_HLOCK_AP,0: vlk key can be used by AP 1: vlk key can't be used by AP" bitfld.long 0x0 0. "LOCK,AP core permission" "0,1" line.long 0x4 "VLK_HLOCK_SAFETY,0: vlk key can be used by SAFETY 1: vlk key can't be used by SAFETY" bitfld.long 0x4 0. "LOCK,SAFETY core permission" "0,1" line.long 0x8 "VLK_PROT,0: vlk key not protected by tamper 1: vlk key protected by tamper" bitfld.long 0x8 0. "PROT,tamper protected permission" "0,1" line.long 0xC "VLK_LOCK,once set. locked for read & write for VLK & VLK_CRC. locked for write to VLK_HLOCK_AP/SAFETY" bitfld.long 0xC 0. "LOCK,lock permission" "0,1" line.long 0x10 "VLK_CRC_EN,1: vlk_crc enable 0 : vlk_crc disable" bitfld.long 0x10 4. "ALL_LOW,crc check reslut is 0x00000000" "0,1" bitfld.long 0x10 3. "ALL_HIGH,crc check reslut is 0xFFFFFFFF" "0,1" bitfld.long 0x10 2. "ERROR,crc check error" "0,1" bitfld.long 0x10 1. "DONE,crc check done" "0,1" bitfld.long 0x10 0. "EN,vlk_crc enable or not" "0,1" group.long 0x50++0x7 line.long 0x0 "VIO_MASK,Secure Violation Mask" hexmask.long.byte 0x0 0.--7. 1. "MASK,default 8'b11111111 means all disabled" line.long 0x4 "VIO_MASK_LOCK,sticky bit. set to lock VIO_MASK" bitfld.long 0x4 0. "LOCK,lock permission" "0,1" repeat 16. (list 0x1 0x1 0x1 0x1 0x1 0x1 0x1 0x1 0x2 0x2 0x2 0x2 0x2 0x2 0x2 0x2 )(list 0x0 0x4 0x8 0xC 0x10 0x14 0x18 0x1C 0x100 0x104 0x108 0x10C 0x110 0x114 0x118 0x11C ) group.long ($2+0x100)++0x3 line.long 0x0 "GP_$1,General Purpose Storage" hexmask.long 0x0 0.--31. 1. "GP,General Purpose Storage" repeat.end repeat 8. (list 0x3 0x3 0x3 0x3 0x3 0x3 0x3 0x3 )(list 0x200 0x204 0x208 0x20C 0x210 0x214 0x218 0x21C ) group.long ($2+0x100)++0x3 line.long 0x0 "GP_$1,General Purpose Storage" hexmask.long 0x0 0.--31. 1. "GP,General Purpose Storage" repeat.end group.long 0x120++0x7 line.long 0x0 "GP_1_PROT,0: gp_1 not protected by tamper 1: gp_1 protected by tamper" bitfld.long 0x0 0. "PROT,tamper protected permission" "0,1" line.long 0x4 "GP_1_LOCK,once set. locked for write to GP_1" bitfld.long 0x4 0. "LOCK,lock permission" "0,1" group.long 0x220++0x7 line.long 0x0 "GP_2_PROT,0: gp_2 not protected by tamper 1: gp_2 protected by tamper" bitfld.long 0x0 0. "PROT,tamper protected permission" "0,1" line.long 0x4 "GP_2_LOCK,once set. locked for write to GP_2" bitfld.long 0x4 0. "LOCK,lock permission" "0,1" group.long 0x320++0x7 line.long 0x0 "GP_3_PROT,0: gp_3 not protected by tamper 1: gp_3 protected by tamper" bitfld.long 0x0 0. "PROT,tamper protected permission" "0,1" line.long 0x4 "GP_3_LOCK,once set. locked for write to GP_3" bitfld.long 0x4 0. "LOCK,lock permission" "0,1" tree.end tree "SEC_STORAGE2" base ad:0x318B0000 group.long 0x0++0x23 line.long 0x0 "VLK,volatile key storage" hexmask.long 0x0 0.--31. 1. "VLK,volatile key" line.long 0x4 "VLK,volatile key storage" hexmask.long 0x4 0.--31. 1. "VLK,volatile key" line.long 0x8 "VLK,volatile key storage" hexmask.long 0x8 0.--31. 1. "VLK,volatile key" line.long 0xC "VLK,volatile key storage" hexmask.long 0xC 0.--31. 1. "VLK,volatile key" line.long 0x10 "VLK,volatile key storage" hexmask.long 0x10 0.--31. 1. "VLK,volatile key" line.long 0x14 "VLK,volatile key storage" hexmask.long 0x14 0.--31. 1. "VLK,volatile key" line.long 0x18 "VLK,volatile key storage" hexmask.long 0x18 0.--31. 1. "VLK,volatile key" line.long 0x1C "VLK,volatile key storage" hexmask.long 0x1C 0.--31. 1. "VLK,volatile key" line.long 0x20 "VLK_CRC,volatile key CRC" hexmask.long 0x20 0.--31. 1. "VLK_CRC,VLK_CRC" group.long 0x30++0x13 line.long 0x0 "VLK_HLOCK_AP,0: vlk key can be used by AP 1: vlk key can't be used by AP" bitfld.long 0x0 0. "LOCK,AP core permission" "0,1" line.long 0x4 "VLK_HLOCK_SAFETY,0: vlk key can be used by SAFETY 1: vlk key can't be used by SAFETY" bitfld.long 0x4 0. "LOCK,SAFETY core permission" "0,1" line.long 0x8 "VLK_PROT,0: vlk key not protected by tamper 1: vlk key protected by tamper" bitfld.long 0x8 0. "PROT,tamper protected permission" "0,1" line.long 0xC "VLK_LOCK,once set. locked for read & write for VLK & VLK_CRC. locked for write to VLK_HLOCK_AP/SAFETY" bitfld.long 0xC 0. "LOCK,lock permission" "0,1" line.long 0x10 "VLK_CRC_EN,1: vlk_crc enable 0 : vlk_crc disable" bitfld.long 0x10 4. "ALL_LOW,crc check reslut is 0x00000000" "0,1" bitfld.long 0x10 3. "ALL_HIGH,crc check reslut is 0xFFFFFFFF" "0,1" bitfld.long 0x10 2. "ERROR,crc check error" "0,1" bitfld.long 0x10 1. "DONE,crc check done" "0,1" bitfld.long 0x10 0. "EN,vlk_crc enable or not" "0,1" group.long 0x50++0x7 line.long 0x0 "VIO_MASK,Secure Violation Mask" hexmask.long.byte 0x0 0.--7. 1. "MASK,default 8'b11111111 means all disabled" line.long 0x4 "VIO_MASK_LOCK,sticky bit. set to lock VIO_MASK" bitfld.long 0x4 0. "LOCK,lock permission" "0,1" repeat 16. (list 0x1 0x1 0x1 0x1 0x1 0x1 0x1 0x1 0x2 0x2 0x2 0x2 0x2 0x2 0x2 0x2 )(list 0x0 0x4 0x8 0xC 0x10 0x14 0x18 0x1C 0x100 0x104 0x108 0x10C 0x110 0x114 0x118 0x11C ) group.long ($2+0x100)++0x3 line.long 0x0 "GP_$1,General Purpose Storage" hexmask.long 0x0 0.--31. 1. "GP,General Purpose Storage" repeat.end repeat 8. (list 0x3 0x3 0x3 0x3 0x3 0x3 0x3 0x3 )(list 0x200 0x204 0x208 0x20C 0x210 0x214 0x218 0x21C ) group.long ($2+0x100)++0x3 line.long 0x0 "GP_$1,General Purpose Storage" hexmask.long 0x0 0.--31. 1. "GP,General Purpose Storage" repeat.end group.long 0x120++0x7 line.long 0x0 "GP_1_PROT,0: gp_1 not protected by tamper 1: gp_1 protected by tamper" bitfld.long 0x0 0. "PROT,tamper protected permission" "0,1" line.long 0x4 "GP_1_LOCK,once set. locked for write to GP_1" bitfld.long 0x4 0. "LOCK,lock permission" "0,1" group.long 0x220++0x7 line.long 0x0 "GP_2_PROT,0: gp_2 not protected by tamper 1: gp_2 protected by tamper" bitfld.long 0x0 0. "PROT,tamper protected permission" "0,1" line.long 0x4 "GP_2_LOCK,once set. locked for write to GP_2" bitfld.long 0x4 0. "LOCK,lock permission" "0,1" group.long 0x320++0x7 line.long 0x0 "GP_3_PROT,0: gp_3 not protected by tamper 1: gp_3 protected by tamper" bitfld.long 0x0 0. "PROT,tamper protected permission" "0,1" line.long 0x4 "GP_3_LOCK,once set. locked for write to GP_3" bitfld.long 0x4 0. "LOCK,lock permission" "0,1" tree.end endif tree.end tree "SEM (Safety Error Manager)" sif (CORENAME()=="CORTEXR5F") repeat 2. (increment 1. 1.) (list ad:0xF0320000 ad:0xF0330000) tree "SEM$1" base $2 tree "AB0 (Address Block 0 of sem)" group.long 0x0++0xB line.long 0x0 "SEM_COMMON_SET,SEM common settings" hexmask.long.byte 0x0 24.--31. 1. "CMP_ENABLE,compare output enable bits for int0-7" bitfld.long 0x0 23. "SIG_MON_GLB_EN,signal monitor global enable" "0,1" bitfld.long 0x0 17. "EI_GLOBAL_EN_LOCK,Error Injection Global Enable Lock bit" "0,1" newline bitfld.long 0x0 16. "EI_GLOBAL_EN,Error Injection Global Enable" "0,1" hexmask.long.byte 0x0 12.--15. 1. "ERROR_DIV,error divider ratio for waveform A" bitfld.long 0x0 11. "ERROR_WAVE_SEL,waveform A/B selection for normal/recoverable error" "0,1" bitfld.long 0x0 10. "FATAL_HIGH_LOW,fatal error High or Low selection" "0,1" newline bitfld.long 0x0 8.--9. "SEM_INT_DC4_SEL,SEM_INT DC4 selection" "0,1,2,3" bitfld.long 0x0 6.--7. "SEM_INT_DC3_SEL,SEM_INT DC3 selection" "0,1,2,3" bitfld.long 0x0 4.--5. "SEM_INT_DC2_SEL,SEM_INT DC2 selection" "0,1,2,3" bitfld.long 0x0 2.--3. "SEM_INT_DC1_SEL,SEM_INT DC1 selection" "0,1,2,3" newline bitfld.long 0x0 0.--1. "SEM_INT_DC0_SEL,SEM_INT DC0 selection" "0,1,2,3" line.long 0x4 "INT_TRIG,int0-7 trigger" hexmask.long.byte 0x4 0.--7. 1. "INT_TRIG,int0-int7 trigger" line.long 0x8 "INT_ENABLE_OVRD,int0-7 enable override" hexmask.long.byte 0x8 8.--15. 1. "INT_ENABLE_OVRD_VAL,int0-7 enable override value" hexmask.long.byte 0x8 0.--7. 1. "INT_ENABLE_OVRD_EN,int0-7 enable override enable" group.long 0x10++0x3 line.long 0x0 "IO_WAVE_CTRL,IO_WAVE_CTRL" bitfld.long 0x0 31. "LOCK,LOCK ctrl" "0,1" bitfld.long 0x0 2.--3. "LEVEL_CFG,the level io when normal [2] and recoverable err[3] take place" "0,1,2,3" bitfld.long 0x0 0.--1. "LEVEL_EN,if set the normal and recoverable output will be set as level [0] normal [1] recover case" "0,1,2,3" repeat 10. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 )(list 0x0 0x4 0x8 0xC 0x10 0x14 0x18 0x1C 0x20 0x24 ) rgroup.long ($2+0x80)++0x3 line.long 0x0 "INT_STATUS$1,interrupt status" hexmask.long 0x0 0.--31. 1. "INT_STATUS0,Interrupt status" repeat.end repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x4 0x8 0xC 0x10 0x14 0x18 0x1C 0x20 0x24 0x80 0x84 0x88 0x8C 0x90 0x94 ) group.long ($2+0x100)++0x3 line.long 0x0 "INT_ENABLE_$1,interrupt enable for int_0" hexmask.long 0x0 0.--31. 1. "INT_ENABLE_00,interrupt enable for int0" repeat.end repeat 16. (list 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1A 0x1B 0x1C 0x1D 0x1E 0x1F )(list 0x98 0x9C 0xA0 0xA4 0x100 0x104 0x108 0x10C 0x110 0x114 0x118 0x11C 0x120 0x124 0x180 0x184 ) group.long ($2+0x100)++0x3 line.long 0x0 "INT_ENABLE_$1,interrupt enable for int_0" hexmask.long 0x0 0.--31. 1. "INT_ENABLE_00,interrupt enable for int0" repeat.end repeat 16. (list 0x20 0x21 0x22 0x23 0x24 0x25 0x26 0x27 0x28 0x29 0x2A 0x2B 0x2C 0x2D 0x2E 0x2F )(list 0x188 0x18C 0x190 0x194 0x198 0x19C 0x1A0 0x1A4 0x200 0x204 0x208 0x20C 0x210 0x214 0x218 0x21C ) group.long ($2+0x100)++0x3 line.long 0x0 "INT_ENABLE_$1,interrupt enable for int_0" hexmask.long 0x0 0.--31. 1. "INT_ENABLE_00,interrupt enable for int0" repeat.end repeat 16. (list 0x30 0x31 0x32 0x33 0x34 0x35 0x36 0x37 0x38 0x39 0x3A 0x3B 0x3C 0x3D 0x3E 0x3F )(list 0x220 0x224 0x280 0x284 0x288 0x28C 0x290 0x294 0x298 0x29C 0x2A0 0x2A4 0x300 0x304 0x308 0x30C ) group.long ($2+0x100)++0x3 line.long 0x0 "INT_ENABLE_$1,interrupt enable for int_0" hexmask.long 0x0 0.--31. 1. "INT_ENABLE_00,interrupt enable for int0" repeat.end repeat 16. (list 0x40 0x41 0x42 0x43 0x44 0x45 0x46 0x47 0x48 0x49 0x4A 0x4B 0x4C 0x4D 0x4E 0x4F )(list 0x310 0x314 0x318 0x31C 0x320 0x324 0x380 0x384 0x388 0x38C 0x390 0x394 0x398 0x39C 0x3A0 0x3A4 ) group.long ($2+0x100)++0x3 line.long 0x0 "INT_ENABLE_$1,interrupt enable for int_0" hexmask.long 0x0 0.--31. 1. "INT_ENABLE_00,interrupt enable for int0" repeat.end repeat 6. (list 0x0 0x1 0x2 0x3 0x4 0x5 )(list 0x0 0x4 0x8 0xC 0x10 0x14 ) group.long ($2+0x500)++0x3 line.long 0x0 "TGT_VALUE$1,target value" hexmask.long 0x0 0.--31. 1. "TGT_VALUE0,monitor target value" repeat.end repeat 6. (list 0x0 0x1 0x2 0x3 0x4 0x5 )(list 0x0 0x4 0x8 0xC 0x10 0x14 ) group.long ($2+0x580)++0x3 line.long 0x0 "SIG_MON_ENABLE$1,signal monitor enable" hexmask.long 0x0 0.--31. 1. "SIG_MON_ENABLE0,monitor enable" repeat.end tree.end tree "ABT (Address Block 0 of sem)" group.long 0x0++0x3 line.long 0x0 "CE0_STAT,1 the CIPHER of CE0 is busy" hexmask.long.byte 0x0 24.--31. 1. "CMP_ENABLE,compare output enable bits for int0-7" newline bitfld.long 0x0 23. "SIG_MON_GLB_EN,signal monitor global enable" "0,1" newline bitfld.long 0x0 17. "EI_GLOBAL_EN_LOCK,Error Injection Global Enable Lock bit" "0,1" newline hexmask.long.word 0x0 16.--31. 1. "RESERVED,1 the CIPHER of CE0 is busy" newline bitfld.long 0x0 16. "EI_GLOBAL_EN,Error Injection Global Enable" "0,1" newline hexmask.long.byte 0x0 8.--15. 1. "RESERVED,CE0 error status one bit indicate one type of error" newline bitfld.long 0x0 6.--7. "RESERVED,1: the DMA operation of ce0 has error 0: the DMA of CE0 has no error" "the DMA of CE0 has no error,the DMA operation of ce0 has error,?,?" newline rbitfld.long 0x0 5. "PKE_BUSY,1: PKE is busy 0:PKE is idle" "?,PKE is busy 0:PKE is idle" newline rbitfld.long 0x0 4. "GENKEY_BUSY,1. CE0 generate key function is busy" "0,1" newline rbitfld.long 0x0 3. "HASH_BUSY,1: the HASH of CE0 is busy" "?,the HASH of CE0 is busy" newline rbitfld.long 0x0 2. "CIPHER_BUSY,1 the CIPHER of CE0 is busy" "0,1" newline rbitfld.long 0x0 1. "GETRNDNUM_BUSY,1: get random number function of CE0 is busy" "?,get random number function of CE0 is busy" newline rbitfld.long 0x0 0. "DMA_BUSY,1: the DMA of CE0 is busy 0: the DMA of CE0 is idle" "the DMA of CE0 is idle,the DMA of CE0 is busy" rgroup.long 0x4++0x3 line.long 0x0 "CE0_ERRSTAT,'the error status of hash sequencer the bit 0 ~ 3 are [sram_wr_err] [sram rd err] [rdma_err] [wdma err]'" hexmask.long.byte 0x0 24.--27. 1. "SKC_ERR_STAT,'the error status of skc sequencer the bit 0 ~ 3 are [sram wr err] [ rand number fetch err] [ secure violation occurs] [reserved]'" group.long 0x8++0x43 line.long 0x0 "INT_ENABLE_OVRD,int0-7 enable override" hexmask.long.byte 0x0 8.--15. 1. "INT_ENABLE_OVRD_VAL,int0-7 enable override value" newline hexmask.long.byte 0x0 0.--7. 1. "INT_ENABLE_OVRD_EN,int0-7 enable override enable" line.long 0x4 "CE0_CIPHER_CTRL,1 the header will be saved into dst memory 0: header will not be saved" bitfld.long 0x4 31. "CIPHER_HEADER_SAVE,1 the header will be saved into dst memory 0: header will not be saved" "header will not be saved,?" newline bitfld.long 0x4 28.--29. "CIPHER_KEY2TYPE,key 2 type 10: input keyport 00: secure sram public area 01: secure area others: reserved" "secure sram public area,secure area others: reserved,?,?" newline bitfld.long 0x4 25.--26. "CIPHER_KEYTYPE,key type 10: input keyport 00: secure sram public area 01: secure area others: reserved" "secure sram public area,secure area others: reserved,?,?" newline hexmask.long.word 0x4 16.--24. 1. "AESMODE,'AES mode XTS : 010000000 ECB : 000000001 CBC : 000000010 CTR : 000000100 CFB : 000001000 OFB : 000010000 CCM : 000100000 GCM : 001000000 XTS : 010000000 CMAC: 100000000'" newline bitfld.long 0x4 13. "CIPHER_SAVE,0: normal mode last part of the message 1: operation context will be saved at the end of operation" "normal mode last part of the message,operation context will be saved at the end of.." newline bitfld.long 0x4 12. "CIPHER_LOAD,0 : normal mode first start of the message 1: operation restart from previously save context" "normal mode first start of the message,operation restart from previously save context" newline bitfld.long 0x4 11. "CIPHER_DECKEYCAL,0 use the input key for decryption operations 1: use the pre-calculation of the key is done before" "?,use the pre-calculation of the key is done before" newline bitfld.long 0x4 9.--10. "CIPHER_KEYSIZE,key size 00: 128bit key 01: 256 bit key 10: 192bit key 11: reserved" "0,1,2,3" newline bitfld.long 0x4 8. "CIPHERMODE,0 encryption 1 decryption" "0,1" newline bitfld.long 0x4 0. "CIPHER_GO,'write 1 to this bit will start the cipher operation'" "0,1" line.long 0x8 "CE0_CIPHER_HEADER_LEN,'cipher data header length in bytes'" bitfld.long 0x8 31. "LOCK,LOCK ctrl" "0,1" newline bitfld.long 0x8 2.--3. "LEVEL_CFG,the level io when normal [2] and recoverable err[3] take place" "0,1,2,3" newline bitfld.long 0x8 0.--1. "LEVEL_EN,if set the normal and recoverable output will be set as level [0] normal [1] recover case" "0,1,2,3" newline hexmask.long 0x8 0.--31. 1. "CIPHER_HEADER_LEN,'cipher data header length in bytes'" line.long 0xC "CE0_CIPHER_KEY_ADDR,key2 address in secure SRAM or keyport" hexmask.long.word 0xC 16.--31. 1. "CIPHER_KEY2_ADDR,key2 address in secure SRAM or keyport" newline hexmask.long.word 0xC 0.--15. 1. "CIPHER_KEY_ADDR,CIPHER_KEY_ADDR address in secure SRAM or keyport" line.long 0x10 "CE0_CIPHER_SRC_ADDR,cipher data source address in bytes" hexmask.long 0x10 0.--31. 1. "CIPHER_SRC_ADDR,cipher data source address in bytes" line.long 0x14 "CE0_CIPHER_SRC_ADDR_H,011: CE SRAM Secure AREA 001:CE SRAM public area 000:external memories other: reserved" bitfld.long 0x14 8.--10. "CIPHER_SRC_TYPE,011: CE SRAM Secure AREA 001:CE SRAM public area 000:external memories other: reserved" "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x14 0.--7. 1. "CIPHER_SRC_ADDR_H,the high part of CE0 cipher source address" line.long 0x18 "CE0_CIPHER_DST_ADDR,CE0 cipher data destination address" hexmask.long 0x18 0.--31. 1. "CIPHER_DST_ADDR,CE0 cipher data destination address" line.long 0x1C "CE0_CIPHER_DST_ADDR_H,011: CE SRAM Secure AREA 001:CE SRAM public area 000:external memories other: reserved" bitfld.long 0x1C 8.--10. "CIPHER_DST_TYPE,011: CE SRAM Secure AREA 001:CE SRAM public area 000:external memories other: reserved" "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x1C 0.--7. 1. "CIPHER_DST_ADDR_H,CE0 cipher data destination address" line.long 0x20 "CE0_CIPHER_IV_CONTEXT_ADDR,CIPHER context storage address the context is always stored into SRAM secure area" hexmask.long.word 0x20 16.--31. 1. "CIPHER_CONTEXT_ADDR,CIPHER context storage address the context is always stored into SRAM secure area" newline hexmask.long.word 0x20 0.--15. 1. "CIPHER_IV_ADDR,CIPHER iv storage address the iv is always stored into SRAM secure area" line.long 0x24 "CE0_CIPHER_PAYLOAD_LEN,CIPHER_PAYLOAD_LEN including the header length in byte" hexmask.long 0x24 0.--31. 1. "CIPHER_PAYLOAD_LEN,CIPHER_PAYLOAD_LEN including the header length in byte" line.long 0x28 "CE0_HASH_CTRL,reserved" newline bitfld.long 0x28 24. "HASH_HMAC_EN,1: hmac is enabled 0: hmac is disabled" "hmac is disabled,hmac is enabled" newline bitfld.long 0x28 19. "HASH_KEY,1 need to load key 0 donot load key" "0,1" newline bitfld.long 0x28 18. "HASH_INIT_SECURE,1 load IV from secure area 0: load IV from public area" "load IV from public area,?" newline bitfld.long 0x28 17. "HASH_INIT,1 load IV for the hash 0 not load initial vector" "0,1" newline bitfld.long 0x28 16. "HASH_SHAUPDATE,0 final SHA224 output 7 words and SHA384 output 6 words 1: update SHA224/384 output 8 words please don't use this feature in hmac mode" "?,update SHA224/384 output 8 words please don't.." newline bitfld.long 0x28 15. "HASH_PADDINGEN,0: bypass padding logic 1: use hw padding logic" "bypass padding logic,use hw padding logic" newline hexmask.long.byte 0x28 8.--14. 1. "HASH_MODE,0000001 MD5 0000010 SHA1 0000100 SHA224 0001000 SHA256 0010000 SHA384 0100000 SHA512 1000000 SM3" newline bitfld.long 0x28 0. "HASH_GO,HASH Calculation start" "0,1" line.long 0x2C "CE0_HASH_KEYIV_ADDR,HASH initial vection address" hexmask.long.word 0x2C 16.--31. 1. "HASH_IV_ADDR,HASH initial vection address" line.long 0x30 "CE0_HMAC_KEY_CTRL,CE0 hash key length in CE SRAM" hexmask.long.word 0x30 16.--31. 1. "HMAC_KEY_LEN,CE0 hash key length in CE SRAM" line.long 0x34 "CE0_HASH_CALC_LEN,CE0 hash calculation length in bytes" hexmask.long 0x34 0.--31. 1. "HASH_CALC_LEN,CE0 hash calculation length in bytes" line.long 0x38 "CE0_HASH_SRC_ADDR,CE0 HASH SRC ADDR" hexmask.long 0x38 0.--31. 1. "HASH_SRC_ADDR,CE0 HASH SRC ADDR" line.long 0x3C "CE0_HASH_SRC_ADDR_H,000: external memory 001: CE SRAM public area 011 CE sram secure area 1xx: SKC key interface space" bitfld.long 0x3C 8.--10. "HASH_SRC_TYPE,000: external memory 001: CE SRAM public area 011 CE sram secure area 1xx: SKC key interface space" "external memory,CE SRAM public area 011 CE sram secure area 1xx:..,?,?,?,?,?,?" newline hexmask.long.byte 0x3C 0.--7. 1. "HASH_SRC_ADDR_H,the high part of CE0 hash src address" line.long 0x40 "CE0_HASH_DST_ADDR,the dst address in secure SRAM" hexmask.long.word 0x40 16.--31. 1. "HASH_DST_ADDR,the dst address in secure SRAM" wgroup.long 0x50++0x3 line.long 0x0 "CE0_DMA_CTRL,write 1 to this register start CE0 DMA operation" bitfld.long 0x0 11. "DMA_GO,write 1 to this register start CE0 DMA operation" "0,1" group.long 0x54++0x13 line.long 0x0 "CE0_DMA_SRC_ADDR,CE0 dma source addr" hexmask.long 0x0 0.--31. 1. "DMA_SRC_ADDR,CE0 dma source addr" line.long 0x4 "CE0_DMA_SRC_ADDR_H,011: CE SRAM Secure AREA 001:CE SRAM public area 000:external memories other: reserved" bitfld.long 0x4 8.--10. "DMA_SRC_TYPE,011: CE SRAM Secure AREA 001:CE SRAM public area 000:external memories other: reserved" "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x4 0.--7. 1. "DMA_SRC_ADDR_H,CE0 dma source addr high part" line.long 0x8 "CE0_DMA_DST_ADDR,CE1 DMA DST ADDR" hexmask.long 0x8 0.--31. 1. "DMA_DST_ADDR,CE1 DMA DST ADDR" line.long 0xC "CE0_DMA_DST_ADDR_H,011: CE SRAM Secure AREA 001:CE SRAM public area 000:external memories other: reserved" bitfld.long 0xC 8.--10. "DMA_DST_TYPE,011: CE SRAM Secure AREA 001:CE SRAM public area 000:external memories other: reserved" "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0xC 0.--7. 1. "DMA_DST_ADDR_H,CE1 DMA DST ADDR high part" line.long 0x10 "CE0_DMA_LEN,DMA transfer length in byte" hexmask.long.word 0x10 0.--15. 1. "DMA_LEN,DMA transfer length in byte" group.long 0x80++0xB line.long 0x0 "CE0_PK_POINTERREG,'unused'" rbitfld.long 0x0 31. "CANFD6_IPI_INT_CE,ipi_int_ce from CANFD6 Correctable error interrupt" "0,1" newline rbitfld.long 0x0 30. "CANFD5_IPI_INT_NCEFA,ipi_int_ncefa from CANFD5 Non correctable error int internal" "0,1" newline rbitfld.long 0x0 29. "CANFD5_IPI_INT_NCEHA,ipi_int_nceha from CANFD5 Non correctable error int host" "0,1" newline hexmask.long.byte 0x0 28.--31. 1. "RESERVED,'unused'" newline rbitfld.long 0x0 28. "CANFD5_IPI_INT_CE,ipi_int_ce from CANFD5 Correctable error interrupt" "0,1" newline hexmask.long.byte 0x0 24.--27. 1. "PK_OPPTRN,'When executing primitive arithmetic operations" newline hexmask.long.byte 0x0 20.--23. 1. "RESERVED,'unused'" newline hexmask.long.byte 0x0 16.--19. 1. "PK_OPPTRC,'When executing primitive arithmetic operations" newline hexmask.long.byte 0x0 12.--15. 1. "RESERVED,'unused'" newline hexmask.long.byte 0x0 8.--11. 1. "PK_OPPTRB,'When executing primitive arithmetic operations" newline hexmask.long.byte 0x0 4.--7. 1. "RESERVED,'unused'" newline hexmask.long.byte 0x0 0.--3. 1. "PK_OPPTRA,'When executing primitive arithmetic operations" line.long 0x4 "CE0_PK_COMMANDREG,PK_CALCR2" rbitfld.long 0x4 31. "CANFD6_IPI_INT_NCEFA,ipi_int_nceha from CANFD6 Non correctable error int host" "0,1" newline rbitfld.long 0x4 30. "NOC_SEC_S_13_MAINSGLDATAECCERR,s_13_mainSglDataEccErr from NOC_SEC None" "0,1" newline rbitfld.long 0x4 29. "NOC_SEC_S_3_MAINSGLDATAECCERR,s_3_mainSglDataEccErr from NOC_SEC None" "0,1" newline rbitfld.long 0x4 28. "NOC_SEC_S_2_MAINSGLDATAECCERR,s_2_mainSglDataEccErr from NOC_SEC None" "0,1" newline rbitfld.long 0x4 27. "NOC_SEC_S_1_MAINSGLECCERR,s_1_mainSglEccErr from NOC_SEC None" "0,1" newline rbitfld.long 0x4 26. "NOC_SEC_S_0_MAINSGLECCERR,s_0_mainSglEccErr from NOC_SEC None" "0,1" newline rbitfld.long 0x4 25. "NOC_SEC_M_9_I_MAININITIATOR_TIMEOUT_FAULT,m_9_I_mainInitiator_Timeout_Fault from NOC_SEC None" "0,1" newline rbitfld.long 0x4 24. "NOC_SEC_M_8_I_MAININITIATOR_TIMEOUT_FAULT,m_8_I_mainInitiator_Timeout_Fault from NOC_SEC None" "0,1" newline rbitfld.long 0x4 23. "NOC_SEC_M_7_I_MAININITIATOR_TIMEOUT_FAULT,m_7_I_mainInitiator_Timeout_Fault from NOC_SEC None" "0,1" newline rbitfld.long 0x4 22. "NOC_SEC_M_6_I_MAININITIATOR_TIMEOUT_FAULT,m_6_I_mainInitiator_Timeout_Fault from NOC_SEC None" "0,1" newline rbitfld.long 0x4 21. "NOC_SEC_M_5_I_MAININITIATOR_TIMEOUT_FAULT,m_5_I_mainInitiator_Timeout_Fault from NOC_SEC None" "0,1" newline rbitfld.long 0x4 20. "NOC_SEC_M_5_MAINSGLDATAECCERR,m_5_mainSglDataEccErr from NOC_SEC None" "0,1" newline hexmask.long.byte 0x4 20.--23. 1. "PK_SELCURVE,'Enable accelerator for specific curve modulus: 0x0: No acceleration (default) 0x1: P256 0x2: P384 0x3: P521/E-521 0x4: P192 0x5: Curve25519/Ed25519 This field has no effect when the optional acceleration hardware is not included.'" newline hexmask.long.word 0x4 8.--18. 1. "PK_SIZE,'Of Operands (in data memory) This field defines the size (= number of bytes minus one) of the operands for the current operation. Possible values are limited by the maximum supported operand size. Examples: 0x014 -> ECC on curve K-163 0x01F ->.." newline bitfld.long 0x4 7. "PK_FIELD,''0': Field is GF(p) '1': Field is GF(2m)'" "0,1" newline hexmask.long.byte 0x4 0.--6. 1. "PK_TYPE,'of operation This field defines the operation to be performed. See table below for details.'" line.long 0x8 "CE0_PKE_CTRL,'Writing a 1 to this bit will reset the pke_seq logic'" rbitfld.long 0x8 31. "NOC_VSN_PD_VSN_MAINLATENTINT,s_17_mainSglDataEccErr from NOC_SEC None" "0,1" newline rbitfld.long 0x8 30. "NOC_MAIN_M_17_I_MAININITIATOR_TIMEOUT_FAULT,m_17_I_mainInitiator_Timeout_Fault from NOC_MAIN None" "0,1" newline rbitfld.long 0x8 29. "NOC_MAIN_M_14_I_MAININITIATOR_TIMEOUT_FAULT,m_14_I_mainInitiator_Timeout_Fault from NOC_MAIN None" "0,1" newline rbitfld.long 0x8 28. "NOC_MAIN_M_13_I_MAININITIATOR_TIMEOUT_FAULT,m_13_I_mainInitiator_Timeout_Fault from NOC_MAIN None" "0,1" newline rbitfld.long 0x8 27. "NOC_MAIN_M_12_I_MAININITIATOR_TIMEOUT_FAULT,m_12_I_mainInitiator_Timeout_Fault from NOC_MAIN None" "0,1" newline rbitfld.long 0x8 26. "NOC_MAIN_M_12_MAINSGLARADDRECCERR,m_12_mainSglArAddrEccErr from NOC_MAIN None OR m_12_mainSglAwAddrEccErr from NOC_MAIN None OR m_12_mainSglDataEccErr from NOC_MAIN None" "0,1" newline rbitfld.long 0x8 25. "NOC_MAIN_M_11_I_MAININITIATOR_TIMEOUT_FAULT,m_11_I_mainInitiator_Timeout_Fault from NOC_MAIN None" "0,1" newline rbitfld.long 0x8 24. "NOC_MAIN_M_11_MAINSGLARADDRECCERR,m_11_mainSglArAddrEccErr from NOC_MAIN None OR m_11_mainSglAwAddrEccErr from NOC_MAIN None OR m_11_mainSglDataEccErr from NOC_MAIN None" "0,1" newline rbitfld.long 0x8 23. "NOC_MAIN_M_10_I_MAININITIATOR_TIMEOUT_FAULT,m_10_I_mainInitiator_Timeout_Fault from NOC_MAIN None" "0,1" newline rbitfld.long 0x8 22. "NOC_MAIN_M_9_I_MAININITIATOR_TIMEOUT_FAULT,m_9_I_mainInitiator_Timeout_Fault from NOC_MAIN None" "0,1" newline rbitfld.long 0x8 21. "NOC_MAIN_M_8_I_MAININITIATOR_TIMEOUT_FAULT,m_8_I_mainInitiator_Timeout_Fault from NOC_MAIN None" "0,1" newline rbitfld.long 0x8 20. "NOC_MAIN_M_7_I_MAININITIATOR_TIMEOUT_FAULT,m_7_I_mainInitiator_Timeout_Fault from NOC_MAIN None" "0,1" newline rbitfld.long 0x8 19. "NOC_MAIN_M_6_I_MAININITIATOR_TIMEOUT_FAULT,m_6_I_mainInitiator_Timeout_Fault from NOC_MAIN None" "0,1" newline rbitfld.long 0x8 18. "NOC_MAIN_M_5_I_MAININITIATOR_TIMEOUT_FAULT,m_5_I_mainInitiator_Timeout_Fault from NOC_MAIN None" "0,1" newline rbitfld.long 0x8 17. "NOC_MAIN_M_4_I_MAININITIATOR_TIMEOUT_FAULT,m_4_I_mainInitiator_Timeout_Fault from NOC_MAIN None" "0,1" newline rbitfld.long 0x8 16. "NOC_MAIN_M_3_I_MAININITIATOR_TIMEOUT_FAULT,m_3_I_mainInitiator_Timeout_Fault from NOC_MAIN None" "0,1" newline rbitfld.long 0x8 15. "NOC_MAIN_M_2_I_MAININITIATOR_TIMEOUT_FAULT,m_2_I_mainInitiator_Timeout_Fault from NOC_MAIN None" "0,1" newline rbitfld.long 0x8 14. "NOC_MAIN_M_1_I_MAININITIATOR_TIMEOUT_FAULT,m_1_I_mainInitiator_Timeout_Fault from NOC_MAIN None" "0,1" newline rbitfld.long 0x8 13. "NOC_MAIN_M_0_I_MAININITIATOR_TIMEOUT_FAULT,m_0_I_mainInitiator_Timeout_Fault from NOC_MAIN None" "0,1" newline rbitfld.long 0x8 12. "NOC_MAIN_SOC_MAINMISSIONINT,SOC_mainMissionInt from NOC_MAIN None OR ~SOC_mainMissionIntBar from NOC_MAIN None" "0,1" newline rbitfld.long 0x8 11. "NOC_MAIN_SOC_MAINLATENTINT,SOC_mainLatentInt from NOC_MAIN None OR ~SOC_mainLatentIntBar from NOC_MAIN None" "0,1" newline rbitfld.long 0x8 10. "NOC_VSN_S_3_MAINSGLDATAECCERR,s_3_mainSglDataEccErr from NOC_VSN None" "0,1" newline rbitfld.long 0x8 9. "NOC_VSN_S_0_MAINSGLDATAECCERR,s_0_mainSglDataEccErr from NOC_VSN None OR PFaultInfoValid from VDSP None" "0,1" newline rbitfld.long 0x8 8. "NOC_VSN_M_2_I_MAININITIATOR_TIMEOUT_FAULT,m_2_I_mainInitiator_Timeout_Fault from NOC_VSN None" "0,1" newline rbitfld.long 0x8 7. "NOC_VSN_M_2_MAINSGLARADDRECCERR,m_2_mainSglArAddrEccErr from NOC_VSN None OR m_2_mainSglAwAddrEccErr from NOC_VSN None OR m_2_mainSglDataEccErr from NOC_VSN None" "0,1" newline rbitfld.long 0x8 6. "NOC_VSN_M_1_I_MAININITIATOR_TIMEOUT_FAULT,m_1_I_mainInitiator_Timeout_Fault from NOC_VSN None" "0,1" newline rbitfld.long 0x8 5. "NOC_VSN_M_1_MAINSGLARADDRECCERR,m_1_mainSglArAddrEccErr from NOC_VSN None OR m_1_mainSglAwAddrEccErr from NOC_VSN None OR m_1_mainSglDataEccErr from NOC_VSN None" "0,1" newline rbitfld.long 0x8 4. "NOC_VSN_M_0_I_MAININITIATOR_TIMEOUT_FAULT,m_0_I_mainInitiator_Timeout_Fault from NOC_VSN None" "0,1" newline rbitfld.long 0x8 3. "NOC_VSN_M_0_MAINSGLARADDRECCERR,m_0_mainSglArAddrEccErr from NOC_VSN None OR m_0_mainSglAwAddrEccErr from NOC_VSN None OR m_0_mainSglDataEccErr from NOC_VSN None" "0,1" newline rbitfld.long 0x8 2. "NOC_VSN_PD_VSN_MAINMISSIONINT,PD_VSN_mainMissionInt from NOC_VSN None OR ~PD_VSN_mainMissionIntBar from NOC_VSN None" "0,1" newline rbitfld.long 0x8 1. "NOC_VSN_PD_VSN_MAINLATENTINT,PD_VSN_mainLatentInt from NOC_VSN None OR ~PD_VSN_mainLatentIntBar from NOC_VSN None" "0,1" newline bitfld.long 0x8 0. "PKE_GO,'Writing a '1' starts the processing.'" "0,1" rgroup.long 0x8C++0x7 line.long 0x0 "CE0_PK_STATUSREG,'unused'" bitfld.long 0x0 31. "NOC_MAIN_M_20_I_MAININITIATOR_TIMEOUT_FAULT,m_19_I_mainInitiator_Timeout_Fault from NOC_MAIN None" "0,1" newline bitfld.long 0x0 30. "NOC_SAF_M_5_I_MAININITIATOR_TIMEOUT_FAULT,m_5_I_mainInitiator_Timeout_Fault from NOC_SAF None" "0,1" newline bitfld.long 0x0 29. "NOC_SAF_M_4_I_MAININITIATOR_TIMEOUT_FAULT,m_4_I_mainInitiator_Timeout_Fault from NOC_SAF None" "0,1" newline bitfld.long 0x0 28. "NOC_SAF_M_4_MAINDUPL_SGLARADDRECCERR,m_4_mainDupl_SglArAddrEccErr from NOC_SAF None OR m_4_mainDupl_SglAwAddrEccErr from NOC_SAF None OR m_4_mainDupl_SglDataEccErr from NOC_SAF None" "0,1" newline bitfld.long 0x0 27. "NOC_SAF_M_4_MAINMAIN_SGLARADDRECCERR,m_4_mainMain_SglArAddrEccErr from NOC_SAF None OR m_4_mainMain_SglAwAddrEccErr from NOC_SAF None OR m_4_mainMain_SglDataEccErr from NOC_SAF None" "0,1" newline bitfld.long 0x0 26. "NOC_SAF_M_3_I_MAININITIATOR_TIMEOUT_FAULT,m_3_I_mainInitiator_Timeout_Fault from NOC_SAF None" "0,1" newline bitfld.long 0x0 25. "NOC_SAF_M_2_I_MAININITIATOR_TIMEOUT_FAULT,m_2_I_mainInitiator_Timeout_Fault from NOC_SAF None" "0,1" newline bitfld.long 0x0 24. "NOC_SAF_M_1_I_MAININITIATOR_TIMEOUT_FAULT,m_1_I_mainInitiator_Timeout_Fault from NOC_SAF None" "0,1" newline bitfld.long 0x0 23. "NOC_SAF_M_1_MAINMAIN_SGLECCERR,m_1_mainMain_SglEccErr from NOC_SAF None" "0,1" newline bitfld.long 0x0 22. "NOC_SAF_M_1_MAINDUPL_SGLECCERR,m_1_mainDupl_SglEccErr from NOC_SAF None" "0,1" newline bitfld.long 0x0 21. "NOC_SAF_M_0_I_MAININITIATOR_TIMEOUT_FAULT,m_0_I_mainInitiator_Timeout_Fault from NOC_SAF None" "0,1" newline bitfld.long 0x0 20. "NOC_SAF_M_0_MAINMAIN_SGLECCERR,m_0_mainMain_SglEccErr from NOC_SAF None" "0,1" newline bitfld.long 0x0 19. "NOC_SAF_M_0_MAINDUPL_SGLECCERR,m_0_mainDupl_SglEccErr from NOC_SAF None" "0,1" newline bitfld.long 0x0 18. "NOC_SAF_PD_SAF_MAINMISSIONINT,PD_SAF_mainMissionInt from NOC_SAF None OR ~PD_SAF_mainMissionIntBar from NOC_SAF None" "0,1" newline hexmask.long.word 0x0 18.--31. 1. "RESERVED,'unused'" newline bitfld.long 0x0 17. "PK_INTERRUPT,'status This bit reflects the IRQ output value. It is set to '1' when the operation is finished. It is cleared when the CPU writes the bit 1 of Control Register.'" "0,1" newline bitfld.long 0x0 16. "PK_BUSY,'This bit reflects the BUSY output value. It is set to '1' when the operation starts and it is cleared when the operation is finished.'" "0,1" newline bitfld.long 0x0 14.--15. "RESERVED,'unused'" "0,1,2,3" newline bitfld.long 0x0 13. "PK_NOTQUADRATICRESIDUE,PK_NOTQUADRATICRESIDUE" "0,1" newline bitfld.long 0x0 12. "PK_COMPOSITE,PK_COMPOSITE" "0,1" newline bitfld.long 0x0 11. "PK_NOTINVERTIBLE,PK_NOTINVERTIBLE" "0,1" newline bitfld.long 0x0 10. "PK_PARAM_AB_NOTVALID,PK_PARAM_AB_NOTVALID" "0,1" newline bitfld.long 0x0 9. "PK_SIGNATURE_NOTVALID,PK_SIGNATURE_NOTVALID" "0,1" newline bitfld.long 0x0 8. "PK_NOTIMPLEMENTED,PK_NOTIMPLEMENTED" "0,1" newline bitfld.long 0x0 7. "PK_PARAM_N_NOTVALID,PK_PARAM_N_NOTVALID" "0,1" newline bitfld.long 0x0 6. "PK_COUPLE_NOTVALID,PK_COUPLE_NOTVALID" "0,1" newline bitfld.long 0x0 5. "PK_POINT_PX_ATINFINITY,PK_POINT_PX_ATINFINITY" "0,1" newline bitfld.long 0x0 4. "PK_POINT_PX_NOTONCURVE,PK_POINT_PX_NOTONCURVE" "0,1" newline hexmask.long.byte 0x0 0.--3. 1. "PK_FAIL_ADDRESS,'These bits indicate which data location generated the error flag. They are not available for all error flags.'" line.long 0x4 "INT_STATUS4,crc32_irq from DC2 None" bitfld.long 0x4 31. "NOC_SAF_S_0_MAINMAIN_SGLECCERR,s_0_mainDupl_SglEccErr from NOC_SAF None" "0,1" newline bitfld.long 0x4 30. "DC2_DC_CH_UNDERRUN,dc_ch_underrun from DC2 None" "0,1" newline bitfld.long 0x4 29. "DC1_CRC32_IRQ,crc32_irq from DC1 None" "0,1" newline bitfld.long 0x4 28. "DC1_DC_CH_UNDERRUN,dc_ch_underrun from DC1 None" "0,1" newline bitfld.long 0x4 27. "DDR_SS_DDR_SS_FUNC_SAF_NONFATL_INT,ddr_ss_func_saf_nonfatl_int from DDR_SS None" "0,1" newline bitfld.long 0x4 26. "DDR_SS_DDR_SS_FUNC_SAF_FATL_INT,ddr_ss_func_saf_fatl_int from DDR_SS None" "0,1" newline bitfld.long 0x4 25. "BIPC_ENET1_ECC_ERR_MULTIPLE,ecc_err_multiple from BIPC_ENET1 None" "0,1" newline bitfld.long 0x4 24. "BIPC_ENET1_ECC_ERR_SINGLE,ecc_err_single from BIPC_ENET1 None" "0,1" newline bitfld.long 0x4 23. "BIPC_VDSP_ECC_ERR_MULTIPLE,ecc_err_multiple from BIPC_VDSP None" "0,1" newline bitfld.long 0x4 22. "BIPC_VDSP_ECC_ERR_SINGLE,ecc_err_single from BIPC_VDSP None" "0,1" newline bitfld.long 0x4 21. "BIPC_DDR_ECC_ERR_MULTIPLE,ecc_err_multiple from BIPC_DDR None" "0,1" newline bitfld.long 0x4 20. "BIPC_DDR_ECC_ERR_SINGLE,ecc_err_single from BIPC_DDR None" "0,1" newline bitfld.long 0x4 19. "MPC_DDR_UNC_ERR_INT,unc_err_int from MPC_DDR None" "0,1" newline bitfld.long 0x4 18. "MPC_DDR_COR_ERR_INT,cor_err_int from MPC_DDR None" "0,1" newline bitfld.long 0x4 17. "MPC_ROMC2_UNC_ERR_INT,unc_err_int from MPC_ROMC2 None" "0,1" newline bitfld.long 0x4 16. "MPC_ROMC2_COR_ERR_INT,cor_err_int from MPC_ROMC2 None" "0,1" newline bitfld.long 0x4 15. "MPC_IRAM4_UNC_ERR_INT,unc_err_int from MPC_IRAM4 None" "0,1" newline bitfld.long 0x4 14. "MPC_IRAM4_COR_ERR_INT,cor_err_int from MPC_IRAM4 None" "0,1" newline bitfld.long 0x4 13. "MPC_IRAM3_UNC_ERR_INT,unc_err_int from MPC_IRAM3 None" "0,1" newline bitfld.long 0x4 12. "MPC_IRAM3_COR_ERR_INT,cor_err_int from MPC_IRAM3 None" "0,1" newline bitfld.long 0x4 11. "MPC_IRAM2_UNC_ERR_INT,unc_err_int from MPC_IRAM2 None" "0,1" newline bitfld.long 0x4 10. "MPC_IRAM2_COR_ERR_INT,cor_err_int from MPC_IRAM2 None" "0,1" newline bitfld.long 0x4 9. "MPC_IRAM1_UNC_ERR_INT,unc_err_int from MPC_IRAM1 None" "0,1" newline bitfld.long 0x4 8. "MPC_IRAM1_COR_ERR_INT,cor_err_int from MPC_IRAM1 None" "0,1" newline bitfld.long 0x4 7. "NOC_SAF_S_4_MAINMAIN_SGLDATAECCERR,s_4_mainMain_SglDataEccErr from NOC_SAF None" "0,1" newline bitfld.long 0x4 6. "NOC_SAF_S_4_MAINDUPL_SGLDATAECCERR,s_4_mainDupl_SglDataEccErr from NOC_SAF None" "0,1" newline bitfld.long 0x4 5. "NOC_SAF_S_2_MAINMAIN_SGLDATAECCERR,s_2_mainMain_SglDataEccErr from NOC_SAF None" "0,1" newline bitfld.long 0x4 4. "NOC_SAF_S_2_MAINDUPL_SGLDATAECCERR,s_2_mainDupl_SglDataEccErr from NOC_SAF None" "0,1" newline bitfld.long 0x4 3. "NOC_SAF_S_1_MAINMAIN_SGLDATAECCERR,s_1_mainMain_SglDataEccErr from NOC_SAF None" "0,1" newline bitfld.long 0x4 2. "NOC_SAF_S_1_MAINDUPL_SGLDATAECCERR,s_1_mainDupl_SglDataEccErr from NOC_SAF None" "0,1" newline bitfld.long 0x4 1. "NOC_SAF_S_0_MAINMAIN_SGLECCERR,s_0_mainMain_SglEccErr from NOC_SAF None" "0,1" group.long 0x94++0x3 line.long 0x0 "CE0_PK_TIMER,'The timer counts the number of clock cycles when the PK engine is busy. It is not cleared automatically. It can be written by software (when the PK is idle). The register is updated at the end of every operation (reading it when the PK.." rbitfld.long 0x0 31. "DC3_CRC32_IRQ,dc_ch_underrun from DC3 None" "0,1" newline rbitfld.long 0x0 30. "CR5_SAF_PPHCORR0,pphcorr0 from CR5_SAF data errors on reads by the AHB Peripheral Port" "0,1" newline rbitfld.long 0x0 29. "CR5_SAF_PPXCORR0,ppxcorr0 from CR5_SAF data errors on reads by the AXI Peripheral Port" "0,1" newline rbitfld.long 0x0 28. "CR5_SAF_AXISCORR0,axiscorr0 from CR5_SAF data errors on writes to the AXI Slave" "0,1" newline rbitfld.long 0x0 27. "CR5_SAF_AXIMCORR0,aximcorr0 from CR5_SAF data errors on reads by the AXI Master" "0,1" newline rbitfld.long 0x0 26. "OSPI2_O_IRQ_UNCORR,o_irq_uncorr from OSPI2 None" "0,1" newline rbitfld.long 0x0 25. "OSPI2_O_IRQ_CORR,o_irq_corr from OSPI2 None" "0,1" newline rbitfld.long 0x0 24. "OSPI1_O_IRQ_UNCORR,o_irq_uncorr from OSPI1 None" "0,1" newline rbitfld.long 0x0 23. "OSPI1_O_IRQ_CORR,o_irq_corr from OSPI1 None" "0,1" newline rbitfld.long 0x0 22. "EFUSEC_FATAL_ERR_INT,fatal_err_int from EFUSEC None" "0,1" newline rbitfld.long 0x0 21. "EFUSEC_NORMAL_ERR_INT,normal_err_int from EFUSEC None" "0,1" newline rbitfld.long 0x0 20. "PCIE_SS_O_PCIEX1_SAFETY_CORR,o_pciex1_safety_corr from PCIE_SS PCIE correctable error" "0,1" newline rbitfld.long 0x0 19. "PCIE_SS_O_PCIEX1_SAFETY_UNCORR,o_pciex1_safety_uncorr from PCIE_SS PCIE non correctable error" "0,1" newline rbitfld.long 0x0 18. "PCIE_SS_O_PCIEX2_SAFETY_CORR,o_pciex2_safety_corr from PCIE_SS PCIE correctable error" "0,1" newline rbitfld.long 0x0 17. "PCIE_SS_O_PCIEX2_SAFETY_UNCORR,o_pciex2_safety_uncorr from PCIE_SS PCIE non correctable error" "0,1" newline rbitfld.long 0x0 16. "ADC_CHANNEL_EVENT4,channel_event4 from ADC None OR channel_event5 from ADC None OR channel_event6 from ADC None OR channel_event7 from ADC None" "0,1" newline rbitfld.long 0x0 15. "ADC_CHANNEL_EVENT3,channel_event3 from ADC None" "0,1" newline rbitfld.long 0x0 14. "ADC_CHANNEL_EVENT2,channel_event2 from ADC None" "0,1" newline rbitfld.long 0x0 13. "ADC_CHANNEL_EVENT1,channel_event1 from ADC None" "0,1" newline rbitfld.long 0x0 12. "ADC_CHANNEL_EVENT0,channel_event0 from ADC None" "0,1" newline rbitfld.long 0x0 11. "VDSP_DOUBLEEXCEPTIONERROR,DoubleExceptionError from VDSP None" "0,1" newline rbitfld.long 0x0 10. "VDSP_PFATALERROR,PFatalError from VDSP None" "0,1" newline rbitfld.long 0x0 9. "VDSP_ERRORCORRECTED,ErrorCorrected from VDSP None" "0,1" newline rbitfld.long 0x0 8. "DP3_DP_CH_UNDERRUN,dp_ch_underrun from DP3 None" "0,1" newline rbitfld.long 0x0 7. "DP2_DP_CH_UNDERRUN,dp_ch_underrun from DP2 None" "0,1" newline rbitfld.long 0x0 6. "DP1_DP_CH_UNDERRUN,dp_ch_underrun from DP1 None" "0,1" newline rbitfld.long 0x0 5. "DC5_CRC32_IRQ,crc32_irq from DC5 None" "0,1" newline rbitfld.long 0x0 4. "DC5_DC_CH_UNDERRUN,dc_ch_underrun from DC5 None" "0,1" newline rbitfld.long 0x0 3. "DC4_CRC32_IRQ,crc32_irq from DC4 None" "0,1" newline rbitfld.long 0x0 2. "DC4_DC_CH_UNDERRUN,dc_ch_underrun from DC4 None" "0,1" newline rbitfld.long 0x0 1. "DC3_CRC32_IRQ,crc32_irq from DC3 None" "0,1" newline hexmask.long 0x0 0.--31. 1. "PK_TIMER,'The timer counts the number of clock cycles when the PK engine is busy. It is not cleared automatically. It can be written by software (when the PK is idle). The register is updated at the end of every operation (reading it when the PK engine.." rgroup.long 0x98++0x3 line.long 0x0 "CE0_PK_HWCONFIGREG,'State of DisableCM input (high when counter-measures are disabled)'" bitfld.long 0x0 31. "CR5_SAF_AXIMFATAL0[2],aximfatal0[1] from CR5_SAF data errors and any parity errors on the AXI master" "0,1" newline bitfld.long 0x0 30. "CR5_SEC_PPXFATAL0[0],ppxfatal0[0] from CR5_SEC data errors and any parity errors on the AXI Peripheral Port" "0,1" newline bitfld.long 0x0 29. "CR5_SEC_AXISFATAL0[4],axisfatal0[4] from CR5_SEC data errors and any parity errors on the AXI slave" "0,1" newline bitfld.long 0x0 28. "CR5_SEC_AXISFATAL0[3],axisfatal0[3] from CR5_SEC data errors and any parity errors on the AXI slave" "0,1" newline bitfld.long 0x0 27. "CR5_SEC_AXISFATAL0[2],axisfatal0[2] from CR5_SEC data errors and any parity errors on the AXI slave" "0,1" newline bitfld.long 0x0 26. "CR5_SEC_AXISFATAL0[1],axisfatal0[1] from CR5_SEC data errors and any parity errors on the AXI slave" "0,1" newline bitfld.long 0x0 25. "CR5_SEC_AXISFATAL0[0],axisfatal0[0] from CR5_SEC data errors and any parity errors on the AXI slave" "0,1" newline hexmask.long.byte 0x0 25.--30. 1. "RESERVED,'unused'" newline bitfld.long 0x0 24. "PK_25519,'Support Curve25519/Ed25519 acceleration'" "0,1" newline bitfld.long 0x0 23. "PK_P192,'Support ECC P192 acceleration'" "0,1" newline bitfld.long 0x0 22. "PK_P521,'Support ECC P521 acceleration'" "0,1" newline bitfld.long 0x0 21. "PK_P384,'Support ECC P384 acceleration'" "0,1" newline bitfld.long 0x0 20. "PK_P256,'Support ECC P256 acceleration'" "0,1" newline bitfld.long 0x0 18.--19. "RESERVED,'unused'" "0,1,2,3" newline bitfld.long 0x0 17. "PK_BINARYFIELD,'Support binary field'" "0,1" newline bitfld.long 0x0 16. "PK_PRIMEFIELD,'Support prime field'" "0,1" newline hexmask.long.byte 0x0 12.--15. 1. "PK_NBMULT,'Number of multipliers: 0x0: 1 multiplier 0x1: 4 multipliers 0x2: 16 multipliers 0x4: 64 multipliers 0x8: 256 multipliers'" newline hexmask.long.word 0x0 0.--11. 1. "PK_MAXOPSIZE,'Maximum operand size (number of bytes) 4096 bytes'" group.long 0x9C++0xB line.long 0x0 "CE0_PK_RESULTS_CTRL,'pke results output select each bit correspnding to the operand position of the pke data memory'" rbitfld.long 0x0 31. "CR5_SEC_PPXFATAL0[3],ppxfatal0[2] from CR5_SEC data errors and any parity errors on the AXI Peripheral Port" "0,1" newline rbitfld.long 0x0 30. "REMAP_CR5_MP_AW_IRQ,irq from REMAP_CR5_MP_AW Remap Address field check error" "0,1" newline rbitfld.long 0x0 29. "REMAP_CR5_SEC_AR_IRQ,irq from REMAP_CR5_SEC_AR Remap Address field check error" "0,1" newline rbitfld.long 0x0 28. "REMAP_CR5_SEC_AW_IRQ,irq from REMAP_CR5_SEC_AW Remap Address field check error" "0,1" newline rbitfld.long 0x0 27. "REMAP_CR5_SAF_AR_IRQ,irq from REMAP_CR5_SAF_AR Remap Address field check error" "0,1" newline rbitfld.long 0x0 26. "REMAP_CR5_SAF_AW_IRQ,irq from REMAP_CR5_SAF_AW Remap Address field check error" "0,1" newline rbitfld.long 0x0 25. "CR5_MP_DCCMOUT2[0],dccmout2[0] from CR5_MP LockStep compare fail" "0,1" newline rbitfld.long 0x0 24. "CR5_MP_DCCMOUT[0],dccmout[0] from CR5_MP LockStep compare fail" "0,1" newline rbitfld.long 0x0 23. "CR5_MP_PPXFATAL0[4],ppxfatal0[4] from CR5_MP data errors and any parity errors on the AXI Peripheral Port" "0,1" newline rbitfld.long 0x0 22. "CR5_MP_PPXFATAL0[3],ppxfatal0[3] from CR5_MP data errors and any parity errors on the AXI Peripheral Port" "0,1" newline rbitfld.long 0x0 21. "CR5_MP_PPXFATAL0[2],ppxfatal0[2] from CR5_MP data errors and any parity errors on the AXI Peripheral Port" "0,1" newline rbitfld.long 0x0 20. "CR5_MP_PPXFATAL0[1],ppxfatal0[1] from CR5_MP data errors and any parity errors on the AXI Peripheral Port" "0,1" newline rbitfld.long 0x0 19. "CR5_MP_PPXFATAL0[0],ppxfatal0[0] from CR5_MP data errors and any parity errors on the AXI Peripheral Port" "0,1" newline rbitfld.long 0x0 18. "CR5_MP_AXISFATAL0[4],axisfatal0[4] from CR5_MP data errors and any parity errors on the AXI slave" "0,1" newline rbitfld.long 0x0 17. "CR5_MP_AXISFATAL0[3],axisfatal0[3] from CR5_MP data errors and any parity errors on the AXI slave" "0,1" newline hexmask.long.word 0x0 16.--31. 1. "PKE_RESULTS_OP_LEN,'pke results each operand length in bytes'" newline rbitfld.long 0x0 16. "CR5_MP_AXISFATAL0[2],axisfatal0[2] from CR5_MP data errors and any parity errors on the AXI slave" "0,1" line.long 0x4 "CE0_PK_RESULTS_DST_ADDR,'pke results dma dst address low 32bit'" rbitfld.long 0x4 31. "CPU1_~NFAULTIRQ[1],~nFAULTIRQ[0] from CPU1 Fault indicator for a detected 1-bit or 2-bit ECC or Parity error in the L3 RAMs" "?,bit or 2-bit ECC or Parity error in the L3 RAMs" newline rbitfld.long 0x4 30. "PWR_LAT_SAF_RTC_POWER_LAT,rtc_power_lat from PWR_LAT_SAF RTC domain power fail" "0,1" newline rbitfld.long 0x4 29. "XTAL_AP_TO_LOST_INT,to_lost_int from XTAL_AP xtal_saf lost" "0,1" newline rbitfld.long 0x4 28. "XTAL_AP_TO_UNST_INT,to_unst_int from XTAL_AP xtal_saf un-stable" "0,1" newline rbitfld.long 0x4 27. "XTAL_AP_FR_UNST_INT,fr_unst_int from XTAL_AP xtal_ap un-stable" "0,1" newline rbitfld.long 0x4 26. "XTAL_SAF_TO_LOST_INT,to_lost_int from XTAL_SAF xtal_ap lost" "0,1" newline rbitfld.long 0x4 25. "XTAL_SAF_TO_UNST_INT,to_unst_int from XTAL_SAF xtal_ap un-stable" "0,1" newline rbitfld.long 0x4 24. "XTAL_SAF_FR_UNST_INT,fr_unst_int from XTAL_SAF xtal_saf un-stable" "0,1" newline rbitfld.long 0x4 23. "RC_24M_SOC_XTAL_LOST_INT,soc_xtal_lost_int from RC_24M soc xtal lost" "0,1" newline rbitfld.long 0x4 22. "RC_24M_SOC_XTAL_UNST_INT,soc_xtal_unst_int from RC_24M soc xtal un-stable" "0,1" newline rbitfld.long 0x4 21. "RC_24M_SOC_OSC_UNST_INT,soc_osc_unst_int from RC_24M osc un-stable according to soc xtal" "0,1" newline rbitfld.long 0x4 20. "RC_24M_SAF_XTAL_LOST_INT,saf_xtal_lost_int from RC_24M safety xtal lost" "0,1" newline rbitfld.long 0x4 19. "RC_24M_SAF_XTAL_UNST_INT,saf_xtal_unst_int from RC_24M safety xtal un-stable" "0,1" newline rbitfld.long 0x4 18. "RC_24M_SAF_OSC_UNST_INT,saf_osc_unst_int from RC_24M osc un-stable according to saf xtal" "0,1" newline rbitfld.long 0x4 17. "CPU2_~NERRIRQ[1],~nERRIRQ[1] from CPU2 Error indicator for an ECC error that causes potential data corruption or loss of coherency in the Core0 L1 or L2 RAMs" "0,1" newline rbitfld.long 0x4 16. "CPU2_~NERRIRQ[0],~nERRIRQ[0] from CPU2 Error indicator for an ECC error that causes potential data corruption or loss of coherency in the L3 RAMs" "0,1" newline rbitfld.long 0x4 15. "CPU2_~NFAULTIRQ[1],~nFAULTIRQ[1] from CPU2 Fault indicator for a detected 1-bit or 2-bit ECC or Parity error in the Core0 L1 or L2 RAMs" "?,bit or 2-bit ECC or Parity error in the Core0 L1.." newline rbitfld.long 0x4 14. "CPU2_~NFAULTIRQ[0],~nFAULTIRQ[0] from CPU2 Fault indicator for a detected 1-bit or 2-bit ECC or Parity error in the L3 RAMs" "?,bit or 2-bit ECC or Parity error in the L3 RAMs" newline rbitfld.long 0x4 13. "CPU1_~NERRIRQ[6],~nERRIRQ[6] from CPU1 Error indicator for an ECC error that causes potential data corruption or loss of coherency in the Core3 L1 or L2 RAMs" "0,1" newline rbitfld.long 0x4 12. "CPU1_~NERRIRQ[5],~nERRIRQ[5] from CPU1 Error indicator for an ECC error that causes potential data corruption or loss of coherency in the Core2 L1 or L2 RAMs" "0,1" newline rbitfld.long 0x4 11. "CPU1_~NERRIRQ[4],~nERRIRQ[4] from CPU1 Error indicator for an ECC error that causes potential data corruption or loss of coherency in the Core3 L1 or L2 RAMs" "0,1" newline rbitfld.long 0x4 10. "CPU1_~NERRIRQ[3],~nERRIRQ[3] from CPU1 Error indicator for an ECC error that causes potential data corruption or loss of coherency in the Core2 L1 or L2 RAMs" "0,1" newline rbitfld.long 0x4 9. "CPU1_~NERRIRQ[2],~nERRIRQ[2] from CPU1 Error indicator for an ECC error that causes potential data corruption or loss of coherency in the Core1 L1 or L2 RAMs" "0,1" newline rbitfld.long 0x4 8. "CPU1_~NERRIRQ[1],~nERRIRQ[1] from CPU1 Error indicator for an ECC error that causes potential data corruption or loss of coherency in the Core0 L1 or L2 RAMs" "0,1" newline rbitfld.long 0x4 7. "CPU1_~NERRIRQ[0],~nERRIRQ[0] from CPU1 Error indicator for an ECC error that causes potential data corruption or loss of coherency in the L3 RAMs" "0,1" newline rbitfld.long 0x4 6. "CPU1_~NFAULTIRQ[6],~nFAULTIRQ[6] from CPU1 Fault indicator for a detected 1-bit or 2-bit ECC or Parity error in the Core3 L1 or L2 RAMs" "?,bit or 2-bit ECC or Parity error in the Core3 L1.." newline rbitfld.long 0x4 5. "CPU1_~NFAULTIRQ[5],~nFAULTIRQ[5] from CPU1 Fault indicator for a detected 1-bit or 2-bit ECC or Parity error in the Core2 L1 or L2 RAMs" "?,bit or 2-bit ECC or Parity error in the Core2 L1.." newline rbitfld.long 0x4 4. "CPU1_~NFAULTIRQ[4],~nFAULTIRQ[4] from CPU1 Fault indicator for a detected 1-bit or 2-bit ECC or Parity error in the Core3 L1 or L2 RAMs" "?,bit or 2-bit ECC or Parity error in the Core3 L1.." newline rbitfld.long 0x4 3. "CPU1_~NFAULTIRQ[3],~nFAULTIRQ[3] from CPU1 Fault indicator for a detected 1-bit or 2-bit ECC or Parity error in the Core2 L1 or L2 RAMs" "?,bit or 2-bit ECC or Parity error in the Core2 L1.." newline rbitfld.long 0x4 2. "CPU1_~NFAULTIRQ[2],~nFAULTIRQ[2] from CPU1 Fault indicator for a detected 1-bit or 2-bit ECC or Parity error in the Core1 L1 or L2 RAMs" "?,bit or 2-bit ECC or Parity error in the Core1 L1.." newline rbitfld.long 0x4 1. "CPU1_~NFAULTIRQ[1],~nFAULTIRQ[1] from CPU1 Fault indicator for a detected 1-bit or 2-bit ECC or Parity error in the Core0 L1 or L2 RAMs" "?,bit or 2-bit ECC or Parity error in the Core0 L1.." newline hexmask.long 0x4 0.--31. 1. "PKE_RESULTS_DST_ADDR,'pke results dma dst address low 32bit'" line.long 0x8 "CE0_PK_RESULTS_DST_ADDR_H,'pke results dma dst address high 8bit'" rbitfld.long 0x8 30. "PWR_LAT_RTC_SAF_POWER_LAT,saf_power_lat from PWR_LAT_SAF SAF power fail" "0,1" newline rbitfld.long 0x8 29. "PVT_SNS_SAF_PVT_INT_0,pvt_int_0 from PVT_SNS_SAF None" "0,1" newline rbitfld.long 0x8 28. "PVT_SNS_SEC_PVT_INT_1,pvt_int_1 from PVT_SNS_SEC None" "0,1" newline rbitfld.long 0x8 27. "PVT_SNS_SEC_PVT_INT_0,pvt_int_0 from PVT_SNS_SEC None" "0,1" newline rbitfld.long 0x8 26. "WDT8_ILL_SEQ_REFR_INT,ill_seq_refr_int from WDT8 None" "0,1" newline rbitfld.long 0x8 25. "WDT8_ILL_WIN_REFR_INT,ill_win_refr_int from WDT8 None" "0,1" newline rbitfld.long 0x8 24. "WDT8_OVFLOW_INT,ovflow_int from WDT8 None" "0,1" newline rbitfld.long 0x8 23. "WDT7_ILL_SEQ_REFR_INT,ill_seq_refr_int from WDT7 None" "0,1" newline rbitfld.long 0x8 22. "WDT7_ILL_WIN_REFR_INT,ill_win_refr_int from WDT7 None" "0,1" newline rbitfld.long 0x8 21. "WDT7_OVFLOW_INT,ovflow_int from WDT7 None" "0,1" newline rbitfld.long 0x8 20. "WDT6_ILL_SEQ_REFR_INT,ill_seq_refr_int from WDT6 None" "0,1" newline rbitfld.long 0x8 19. "WDT6_ILL_WIN_REFR_INT,ill_win_refr_int from WDT6 None" "0,1" newline rbitfld.long 0x8 18. "WDT6_OVFLOW_INT,ovflow_int from WDT6 None" "0,1" newline rbitfld.long 0x8 17. "WDT5_ILL_SEQ_REFR_INT,ill_seq_refr_int from WDT5 None" "0,1" newline rbitfld.long 0x8 16. "WDT5_ILL_WIN_REFR_INT,ill_win_refr_int from WDT5 None" "0,1" newline rbitfld.long 0x8 15. "WDT5_OVFLOW_INT,ovflow_int from WDT5 None" "0,1" newline rbitfld.long 0x8 14. "WDT4_ILL_SEQ_REFR_INT,ill_seq_refr_int from WDT4 None" "0,1" newline rbitfld.long 0x8 13. "WDT4_ILL_WIN_REFR_INT,ill_win_refr_int from WDT4 None" "0,1" newline rbitfld.long 0x8 12. "WDT4_OVFLOW_INT,ovflow_int from WDT4 None" "0,1" newline rbitfld.long 0x8 11. "WDT3_ILL_SEQ_REFR_INT,ill_seq_refr_int from WDT3 None" "0,1" newline rbitfld.long 0x8 10. "WDT3_ILL_WIN_REFR_INT,ill_win_refr_int from WDT3 None" "0,1" newline rbitfld.long 0x8 9. "WDT3_OVFLOW_INT,ovflow_int from WDT3 None" "0,1" newline bitfld.long 0x8 8.--10. "PKE_RESULTS_DST_TYPE,'pke results dma dst data type 011: CE SRAM Secure AREA 001:CE SRAM public area 000:external memories other: reserved'" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x8 8. "WDT2_ILL_SEQ_REFR_INT,ill_seq_refr_int from WDT2 None" "0,1" group.long 0x100++0x7 line.long 0x0 "CE0_TRNG_STATUS,'1: the value in the random number register of CE0 is valid" rbitfld.long 0x0 1. "RNG_READY,'1: the value in the random number register of CE0 is valid" "?,the value in the random number register of CE0.." newline hexmask.long 0x0 0.--31. 1. "INT_ENABLE_00,interrupt enable for int0" line.long 0x4 "CE0_TRNG_STATUS,'1: the value in the random number register of CE0 is valid" rbitfld.long 0x4 1. "RNG_READY,'1: the value in the random number register of CE0 is valid" "?,the value in the random number register of CE0.." newline hexmask.long 0x4 0.--31. 1. "INT_ENABLE_01,interrupt enable for int0" rgroup.long 0x104++0x3 line.long 0x0 "CE0_TRNG_NUM0,CE0 the random number0 value" hexmask.long 0x0 0.--31. 1. "TRNG_NUM0,CE0 the random number0 value" group.long 0x108++0x3 line.long 0x0 "CE0_TRNG_STATUS,'1: the value in the random number register of CE0 is valid" rbitfld.long 0x0 1. "RNG_READY,'1: the value in the random number register of CE0 is valid" "?,the value in the random number register of CE0.." newline hexmask.long 0x0 0.--31. 1. "INT_ENABLE_02,interrupt enable for int0" rgroup.long 0x108++0x3 line.long 0x0 "CE0_TRNG_NUM1,CE0 the random number1 value" hexmask.long 0x0 0.--31. 1. "TRNG_NUM1,CE0 the random number1 value" group.long 0x10C++0xB line.long 0x0 "CE0_TRNG_STATUS,'1: the value in the random number register of CE0 is valid" rbitfld.long 0x0 1. "RNG_READY,'1: the value in the random number register of CE0 is valid" "?,the value in the random number register of CE0.." newline hexmask.long 0x0 0.--31. 1. "INT_ENABLE_03,interrupt enable for int0" line.long 0x4 "CE0_TRNG_STATUS,'1: the value in the random number register of CE0 is valid" rbitfld.long 0x4 1. "RNG_READY,'1: the value in the random number register of CE0 is valid" "?,the value in the random number register of CE0.." newline hexmask.long 0x4 0.--31. 1. "INT_ENABLE_04,interrupt enable for int0" line.long 0x8 "CE0_TRNG_STATUS,'1: the value in the random number register of CE0 is valid" rbitfld.long 0x8 1. "RNG_READY,'1: the value in the random number register of CE0 is valid" "?,the value in the random number register of CE0.." newline hexmask.long 0x8 0.--31. 1. "INT_ENABLE_05,interrupt enable for int0" rgroup.long 0x114++0x3 line.long 0x0 "CE0_HRNG_NUM,CE0 the hybird random number value" hexmask.long 0x0 0.--31. 1. "HRNG_NUM,CE0 the hybird random number value" group.long 0x118++0xB line.long 0x0 "CE0_TRNG_STATUS,'1: the value in the random number register of CE0 is valid" rbitfld.long 0x0 1. "RNG_READY,'1: the value in the random number register of CE0 is valid" "?,the value in the random number register of CE0.." newline hexmask.long 0x0 0.--31. 1. "INT_ENABLE_06,interrupt enable for int0" line.long 0x4 "CE0_TRNG_STATUS,'1: the value in the random number register of CE0 is valid" rbitfld.long 0x4 1. "RNG_READY,'1: the value in the random number register of CE0 is valid" "?,the value in the random number register of CE0.." newline hexmask.long 0x4 0.--31. 1. "INT_ENABLE_07,interrupt enable for int0" line.long 0x8 "CE0_TRNG_STATUS,'1: the value in the random number register of CE0 is valid" rbitfld.long 0x8 1. "RNG_READY,'1: the value in the random number register of CE0 is valid" "?,the value in the random number register of CE0.." newline hexmask.long 0x8 0.--31. 1. "INT_ENABLE_08,interrupt enable for int0" wgroup.long 0x120++0x3 line.long 0x0 "CE0_SKC_CTRL,CE0 secure FSM start trigger" bitfld.long 0x0 8. "SKC_GO,CE0 secure FSM start trigger" "0,1" group.long 0x124++0x3 line.long 0x0 "CE0_TRNG_STATUS,'1: the value in the random number register of CE0 is valid" rbitfld.long 0x0 1. "RNG_READY,'1: the value in the random number register of CE0 is valid" "?,the value in the random number register of CE0.." newline hexmask.long 0x0 0.--31. 1. "INT_ENABLE_09,interrupt enable for int0" group.long 0x124++0x7 line.long 0x0 "CE0_SKC_RNG_ADDR,CE0 random number generation address in CE sram the address granularity is 8 bytes" hexmask.long.byte 0x0 24.--30. 1. "SKC_RNG_LEN,'numbers of bits to generate into sram granularity is 256 bit'" newline hexmask.long.word 0x0 13.--25. 1. "SKC_RNG_ADDR,CE0 random number generation address in CE sram the address granularity is 8 bytes" line.long 0x4 "CE0_SKC_KEYBLOB_CTRL,CE0 key blob control 1: is key blob :0 : is the secret data" bitfld.long 0x4 0. "SKC_KEYBLOB_CTRL,CE0 key blob control 1: is key blob :0 : is the secret data" "?,is key blob :0 : is the secret data" group.long 0x140++0x3 line.long 0x0 "CE0_INTEN,RESERVED" newline bitfld.long 0x0 13. "DMA_FIFOERROR_INTEN,DMA fifo error interrupt" "0,1" newline bitfld.long 0x0 12. "PKE_INTEGRITY_ERROR_INTEN,ALGORITHM_INTEGRITY interrupt" "0,1" newline bitfld.long 0x0 11. "HASH_INTEGRITY_ERROR_INTEN,ALGORITHM_INTEGRITY_ERROR interrupt" "0,1" newline bitfld.long 0x0 10. "CIPHER_INTEGRITY_ERROR_INTEN,ALGORITHM_INTEGRITY_ERROR interrupt" "0,1" newline bitfld.long 0x0 9. "SKC_INTEGRITY_ERROR_INTEN,SKC_INTEGRITY_ERROR interrupt" "0,1" newline bitfld.long 0x0 8. "DMA_INTEGRITY_ERROR_INTEN,ALGORITHM_INTEGRITY interrupt" "0,1" newline bitfld.long 0x0 4. "PKE_DONE_INTEN,PKE_DONE interrupt" "0,1" newline bitfld.long 0x0 3. "HASH_DONE_INTEN,HASH_DONE interrupt" "0,1" newline bitfld.long 0x0 2. "CIPHER_DONE_INTEN,CIPHER_DONE_INTEN" "0,1" newline bitfld.long 0x0 1. "SKC_DONE_INTEN,KEYgen done interrupt enable" "0,1" newline bitfld.long 0x0 0. "DMA_DONE_INTEN,DMA_DONE interrupt" "0,1" rgroup.long 0x144++0x3 line.long 0x0 "CE0_INTSTAT,RESERVED" newline bitfld.long 0x0 13. "DMA_FIFOERROR_INTSTAT,SSRAM_DMAFIFO error interrupt" "0,1" newline bitfld.long 0x0 12. "PKE_INTEGRITY_ERROR_INTSTAT,ALGORITHM_INTEGRITY interrupt" "0,1" newline bitfld.long 0x0 11. "HASH_INTEGRITY_ERROR_INTSTAT,ALGORITHM_INTEGRITY_ERROR interrupt" "0,1" newline bitfld.long 0x0 10. "CIPHER_INTEGRITY_ERROR_INTSTAT,ALGORITHM_INTEGRITY_ERROR interrupt" "0,1" newline bitfld.long 0x0 9. "SKC_INTEGRITY_ERROR_INTSTAT,SKC_INTEGRITY_ERROR interrupt" "0,1" newline bitfld.long 0x0 8. "DMA_INTEGRITY_ERROR_INTSTAT,ALGORITHM_INTEGRITY interrupt" "0,1" newline bitfld.long 0x0 4. "PKE_DONE_INTSTAT,PKE_DONE interrupt" "0,1" newline bitfld.long 0x0 3. "HASH_DONE_INTSTAT,HASH_DONE interrupt" "0,1" newline bitfld.long 0x0 2. "CIPHER_DONE_INTSTAT,CIPHER_DONE_INTSTATE" "0,1" newline bitfld.long 0x0 1. "SKC_DONE_INTSTAT,KEYgen done interrupt enable" "0,1" newline bitfld.long 0x0 0. "DMA_DONE_INTSTAT,DMA_DONE interrupt" "0,1" wgroup.long 0x148++0x3 line.long 0x0 "CE0_INTCLR,RESERVED" newline bitfld.long 0x0 13. "DMA_FIFOERROR_INTCLR,SSRAM_DMAFIFO error interrupt" "0,1" newline bitfld.long 0x0 12. "PKE_INTEGRITY_ERROR_INTCLR,ALGORITHM_INTEGRITY interrupt" "0,1" newline bitfld.long 0x0 11. "HASH_INTEGRITY_ERROR_INTCLR,ALGORITHM_INTEGRITY_ERROR interrupt" "0,1" newline bitfld.long 0x0 10. "CIPHER_INTEGRITY_ERROR_INTCLR,ALGORITHM_INTEGRITY_ERROR interrupt" "0,1" newline bitfld.long 0x0 9. "SKC_INTEGRITY_ERROR_INTCLR,SKC_INTEGRITY_ERROR interrupt" "0,1" newline bitfld.long 0x0 8. "DMA_INTEGRITY_ERROR_INTCLR,ALGORITHM_INTEGRITY interrupt" "0,1" newline bitfld.long 0x0 4. "PKE_DONE_INTCLR,PKE_DONE interrupt" "0,1" newline bitfld.long 0x0 3. "HASH_DONE_INTCLR,HASH_DONE interrupt" "0,1" newline bitfld.long 0x0 2. "CIPHER_DONE_INTCLR,CIPHER_DONE_INTCLRE" "0,1" newline bitfld.long 0x0 1. "SKC_DONE_INTCLR,KEYgen done interrupt enable" "0,1" newline bitfld.long 0x0 0. "DMA_DONE_INTCLR,DMA_DONE interrupt" "0,1" repeat 16. (list 0xA 0xB 0xC 0xD 0xE 0xF 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 )(list 0x0 0x4 0x8 0xC 0x10 0x14 0x18 0x1C 0x20 0x24 0x80 0x84 0x88 0x8C 0x90 0x94 ) group.long ($2+0x180)++0x3 line.long 0x0 "INT_ENABLE_$1,interrupt enable for int_1" hexmask.long 0x0 0.--31. 1. "INT_ENABLE_10,interrupt enable for int1" repeat.end repeat 16. (list 0x1A 0x1B 0x1C 0x1D 0x1E 0x1F 0x20 0x21 0x22 0x23 0x24 0x25 0x26 0x27 0x28 0x29 )(list 0x98 0x9C 0xA0 0xA4 0x100 0x104 0x108 0x10C 0x110 0x114 0x118 0x11C 0x120 0x124 0x180 0x184 ) group.long ($2+0x180)++0x3 line.long 0x0 "INT_ENABLE_$1,interrupt enable for int_1" hexmask.long 0x0 0.--31. 1. "INT_ENABLE_10,interrupt enable for int1" repeat.end repeat 16. (list 0x2A 0x2B 0x2C 0x2D 0x2E 0x2F 0x30 0x31 0x32 0x33 0x34 0x35 0x36 0x37 0x38 0x39 )(list 0x188 0x18C 0x190 0x194 0x198 0x19C 0x1A0 0x1A4 0x200 0x204 0x208 0x20C 0x210 0x214 0x218 0x21C ) group.long ($2+0x180)++0x3 line.long 0x0 "INT_ENABLE_$1,interrupt enable for int_1" hexmask.long 0x0 0.--31. 1. "INT_ENABLE_10,interrupt enable for int1" repeat.end repeat 16. (list 0x3A 0x3B 0x3C 0x3D 0x3E 0x3F 0x40 0x41 0x42 0x43 0x44 0x45 0x46 0x47 0x48 0x49 )(list 0x220 0x224 0x280 0x284 0x288 0x28C 0x290 0x294 0x298 0x29C 0x2A0 0x2A4 0x300 0x304 0x308 0x30C ) group.long ($2+0x180)++0x3 line.long 0x0 "INT_ENABLE_$1,interrupt enable for int_1" hexmask.long 0x0 0.--31. 1. "INT_ENABLE_10,interrupt enable for int1" repeat.end repeat 6. (list 0x4A 0x4B 0x4C 0x4D 0x4E 0x4F )(list 0x310 0x314 0x318 0x31C 0x320 0x324 ) group.long ($2+0x180)++0x3 line.long 0x0 "INT_ENABLE_$1,interrupt enable for int_1" hexmask.long 0x0 0.--31. 1. "INT_ENABLE_10,interrupt enable for int1" repeat.end repeat 6. (list 0x0 0x1 0x2 0x3 0x4 0x5 )(list 0x0 0x4 0x8 0xC 0x10 0x14 ) group.long ($2+0x500)++0x3 line.long 0x0 "TGT_VALUE$1,target value" hexmask.long 0x0 0.--31. 1. "TGT_VALUE0,monitor target value" repeat.end repeat 6. (list 0x0 0x1 0x2 0x3 0x4 0x5 )(list 0x0 0x4 0x8 0xC 0x10 0x14 ) group.long ($2+0x580)++0x3 line.long 0x0 "SIG_MON_ENABLE$1,signal monitor enable" hexmask.long 0x0 0.--31. 1. "SIG_MON_ENABLE0,monitor enable" repeat.end rgroup.long 0x8000++0x3 line.long 0x0 "SECURE_CTRL,'the corresponding bits enable the secure violation source'" hexmask.long.byte 0x0 24.--31. 1. "CE_SRAM_SIZE_VIO,the CE sram size size is not correct" group.long 0x8004++0x17 line.long 0x0 "SESRAM_SIZE,the secure sram size CE1" bitfld.long 0x0 31. "RESERVED,the secure sram size CE1" "0,1" line.long 0x4 "SESRAM_SIZE_CONT,the secure sram size CE1" bitfld.long 0x4 31. "RESERVED,the secure sram size CE1" "0,1" line.long 0x8 "SESRAM_SASIZE,the secure sram size CE1" bitfld.long 0x8 31. "RESERVED,the secure sram size CE1" "0,1" line.long 0xC "SESRAM_SASIZE_CONT,the secure sram size CE1" bitfld.long 0xC 31. "RESERVED,the secure sram size CE1" "0,1" line.long 0x10 "VCE_SINATURE_MASK,'the mask for the vce to generate signature from id'" hexmask.long 0x10 0.--31. 1. "VCE_SINATURE_MASK,'the mask for the vce to generate signature from id'" line.long 0x14 "VCE_SINATURE_MASK_HIGH,'the mask for the vce to generate signature from id high part'" hexmask.long.byte 0x14 0.--7. 1. "VCE_SINATURE_MASK_HIGH,'the mask for the vce to generate signature from id high part'" group.long 0x8020++0x7 line.long 0x0 "HRNG_CTRL,'the counter to control the frequency for the hrng LFSF load the feedback cycle'" hexmask.long.byte 0x0 8.--11. 1. "HRNG_LOAD_CNT,'the counter to control the frequency for the hrng LFSF load the feedback cycle'" newline bitfld.long 0x0 0. "NOISE_ENABLE,'1: enable the noise source for the hrng 0: disable the noise source'" "disable the noise source',enable the noise source for the hrng" line.long 0x4 "HRNG_SEED_CTRL,'write 1 to this bit will load the seed into the hrng auto clear'" bitfld.long 0x4 31. "LOAD_SEED_GO,'write 1 to this bit will load the seed into the hrng auto clear'" "0,1" newline hexmask.long 0x4 0.--30. 1. "SEED_NUM,'the seed number" wgroup.long 0x8030++0x3 line.long 0x0 "TRNG_CTRL,'write this bit will start the trng sequencer to fetch the random number for all VCEs'" bitfld.long 0x0 0. "CE_TRNG_SEQ_GO,'write this bit will start the trng sequencer to fetch the random number for all VCEs'" "0,1" group.long 0x8050++0x3 line.long 0x0 "DEBUG_BUS_SEL,'debug bus select'" hexmask.long.word 0x0 0.--15. 1. "DEBUG_BUS_SEL,'debug bus select'" rgroup.long 0x8054++0x3 line.long 0x0 "DEBUG_BUS_STATUS,'debug bus output'" hexmask.long 0x0 0.--31. 1. "DEBUG_BUS_STATUS,'debug bus output'" group.long 0x8100++0x3 line.long 0x0 "TRNG_CONTROL,'Enable write of the samples in the FIFO during start-up'" bitfld.long 0x0 20. "TRNG_FIFOWRITESTARTUP,'Enable write of the samples in the FIFO during start-up'" "0,1" newline hexmask.long.byte 0x0 16.--19. 1. "TRNG_NB128BITBLOCKS,'Number of 128 bit blocks used in AES-CBCMAC post-processing. This value cannot be zero.'" newline bitfld.long 0x0 15. "TRNG_AIS31TESTSEL,'Select input to the AIS31 test module 0: Before conditioning 1: After conditioning'" "Before conditioning,After conditioning'" newline bitfld.long 0x0 14. "TRNG_HEALTHTESTSEL,'Select input to health test module 0: Before conditioning 1: After conditioning'" "Before conditioning,After conditioning'" newline bitfld.long 0x0 13. "TRNG_AIS31BYPASS,'Bypass AIS31 tests such that the results of the start-up and online tests do not affect the FSM state'" "0,1" newline bitfld.long 0x0 12. "TRNG_HEALTHTESTBYPASS,'Bypass NIST tests such that the results of the start-up and online test do not affect the FSM state'" "0,1" newline bitfld.long 0x0 11. "TRNG_FORCERUN,'Force oscillators to run when FIFO is full'" "0,1" newline bitfld.long 0x0 10. "TRNG_INTENALM,'Interrupt enable for AIS31 noise alarm'" "0,1" newline bitfld.long 0x0 9. "TRNG_INTENPRE,'Interrupt enable for AIS31 preliminary noise alarm'" "0,1" newline bitfld.long 0x0 8. "TRNG_SOFTRESET,'Software reset 0: Normal mode 1: The continuous test" "Normal mode,The continuous test" newline bitfld.long 0x0 7. "TRNG_INTENFULL,'Interrupt enable for FIFO full'" "0,1" newline bitfld.long 0x0 5. "TRNG_INTENPROP,'Interrupt enable for Adaptive Proportion Test failure (1024-sample window)'" "0,1" newline bitfld.long 0x0 4. "TRNG_INTENREP,'Interrupt enable for Repetition Count Test failure'" "0,1" newline bitfld.long 0x0 3. "TRNG_CONDBYPASS,'0: the conditioning function is used (normal mode) 1: the conditioning function is bypassed (to observe entropy source directly).'" "the conditioning function is used,the conditioning function is bypassed" newline bitfld.long 0x0 2. "TRNG_TESTEN,'Select input for conditioning function and continuous tests: 0: Noise source (normal mode) 1: Test data register (test mode)'" "Noise source,Test data register" newline bitfld.long 0x0 1. "TRNG_LFSREN,TRNG_LFSREN" "0,1" newline bitfld.long 0x0 0. "TRNG_ENABLE,'Enable the NDRNG.'" "0,1" rgroup.long 0x8104++0x3 line.long 0x0 "TRNG_FIFOTHD,'FIFO level below which the module leaves the idle state to refill the fifo" hexmask.long 0x0 0.--31. 1. "TRNG_FIFOLEVEL,'Number of 32 bits words of random available in the FIFO. Any write to this register clears the FullInt flag in the Status register.'" rgroup.long 0x810C++0x3 line.long 0x0 "TRNG_FIFODEPTH,'Depth Maximum number of 32 bits words that can be stored in the FIFO: 2g_fifodepth.'" hexmask.long 0x0 0.--31. 1. "TRNG_FIFODEPTH,'Depth Maximum number of 32 bits words that can be stored in the FIFO: 2g_fifodepth.'" group.long 0x8110++0xF line.long 0x0 "TRNG_KEY0REG,'Key (MSB)'" hexmask.long 0x0 0.--31. 1. "TRNG_KEY0REG,'Key (MSB)'" line.long 0x4 "TRNG_KEY1REG,'Key'" hexmask.long 0x4 0.--31. 1. "TRNG_KEY1REG,'Key'" line.long 0x8 "TRNG_KEY2REG,'Key'" hexmask.long 0x8 0.--31. 1. "TRNG_KEY2REG,'Key'" line.long 0xC "TRNG_KEY3REG,'Key (LSB)'" hexmask.long 0xC 0.--31. 1. "TRNG_KEY3REG,'Key (LSB)'" wgroup.long 0x8120++0x3 line.long 0x0 "TRNG_TESTDATA,'feed known data to the conditioning function or to the continous tests.'" hexmask.long 0x0 0.--31. 1. "TRNG_TESTDATA,'feed known data to the conditioning function or to the continous tests.'" group.long 0x8124++0x7 line.long 0x0 "TRNG_REPTHRESREG,'Repetition Test Count Cut-Off value'" hexmask.long 0x0 0.--31. 1. "TRNG_REPTHRESREG,'Repetition Test Count Cut-Off value'" line.long 0x4 "TRNG_PROPTHRESREG,'Adaptive Proportion Test (1024-sample window) Cut-Off value'" hexmask.long 0x4 0.--31. 1. "TRNG_PROPTHRESREG,'Adaptive Proportion Test (1024-sample window) Cut-Off value'" group.long 0x8130++0x27 line.long 0x0 "TRNG_STATUS,'Set when a FIFO data read is performed while the NDRNG is disabled AND has its FIFO empty (FIFOLevel = 0)'" bitfld.long 0x0 11. "TRNG_FIFOACCFAIL,'Set when a FIFO data read is performed while the NDRNG is disabled AND has its FIFO empty (FIFOLevel = 0)'" "0,1" newline rbitfld.long 0x0 10. "TRNG_STARTUPFAIL,'Start-up test failure'" "0,1" newline rbitfld.long 0x0 9. "TRNG_ALMINT,'AIS31 noise alarm interrupt status'" "0,1" newline bitfld.long 0x0 8. "TRNG_PREINT,'AIS31 preliminary noise alarm interrupt status'" "0,1" newline bitfld.long 0x0 7. "TRNG_FULLINT,'FIFO full status'" "0,1" newline bitfld.long 0x0 5. "TRNG_PROPFAIL,'NIST-800-90B adaptive Proportion Test (1024-sample window) interrupt status'" "0,1" newline bitfld.long 0x0 4. "TRNG_REPFAIL,'NIST-800-90B repetition Count Test interrupt status'" "0,1" newline rbitfld.long 0x0 1.--3. "TRNG_STATE,'State of the control FSM (see Figure 7-1) 000: Reset 001: Startup 010: Idle (Rings On) 011: Idle (Rings Off) 100: Fill FIFO 101: Error 110: Unused 111: Unused'" "Reset,Startup,?,?,?,?,?,?" newline rbitfld.long 0x0 0. "TRNG_TESTDATABUSY,'High when data written to TestData register is being processed. (see section 4.7)'" "0,1" line.long 0x4 "TRNG_INITWAITVAL,'Number of clock cycles to wait before sampling data from the noise source. All 16 bits are reset high (reset value = 0xFFFF).'" hexmask.long.word 0x4 0.--15. 1. "TRNG_INITWAITVAL,'Number of clock cycles to wait before sampling data from the noise source. All 16 bits are reset high (reset value = 0xFFFF).'" line.long 0x8 "TRNG_DISABLEOSC,'Disable oscillator rings #0 to #31'" hexmask.long 0x8 0.--31. 1. "TRNG_DISABLEOS0,'Disable oscillator rings #0 to #31'" line.long 0xC "TRNG_DISABLEOSC1,'Disable oscillator rings #32 to #63'" hexmask.long 0xC 0.--31. 1. "TRNG_DISABLEOS1,'Disable oscillator rings #32 to #63'" line.long 0x10 "TRNG_SWOFFTMRVAL,'Number of clk cycles to wait before stopping the rings after the FIFO is full. '" hexmask.long.word 0x10 0.--15. 1. "TRNG_SWOFFTMRVAL,'Number of clk cycles to wait before stopping the rings after the FIFO is full. '" line.long 0x14 "TRNG_CLKDIV,'Sample clock divider. The frequency at which the outputs of the rings are sampled is given by Fs = Fpclk/(ClkDiv + 1).'" hexmask.long.byte 0x14 0.--7. 1. "TRNG_CLKDIV,'Sample clock divider. The frequency at which the outputs of the rings are sampled is given by Fs = Fpclk/(ClkDiv + 1).'" line.long 0x18 "TRNG_AIS31CONF0,'Online threshold'" hexmask.long.word 0x18 16.--31. 1. "TRNG_ONLINETHRESH,'Online threshold'" newline hexmask.long.word 0x18 0.--15. 1. "TRNG_STARTUPTHRESH,'Start-up test threshold'" line.long 0x1C "TRNG_AIS31CONF1,'Expected history value'" hexmask.long.word 0x1C 16.--31. 1. "TRNG_HEXPECTEDVALUE,'Expected history value'" newline hexmask.long.word 0x1C 0.--15. 1. "TRNG_ONLINEREPTHRESH,'Online repeat threshold'" line.long 0x20 "TRNG_AIS31CONF2,'Maximum allowed history valu'" hexmask.long.word 0x20 16.--31. 1. "TRNG_HMAX,'Maximum allowed history valu'" newline hexmask.long.word 0x20 0.--15. 1. "TRNG_HMIN,'Minimum allowed history value'" line.long 0x24 "TRNG_AIS31STATUS,TRNG_PRELIMNOISEALARMREP" rbitfld.long 0x24 17. "TRNG_PRELIMNOISEALARMREP,TRNG_PRELIMNOISEALARMREP" "0,1" newline rbitfld.long 0x24 16. "TRNG_PRELIMNOISEALARMRNG,'Last preliminary noise alarm occurred due to history value out of range'" "0,1" newline hexmask.long.word 0x24 0.--15. 1. "TRNG_NUMPRELIMALARMS,'Number of preliminary noise alarms since counter was last cleared'" rgroup.long 0x8158++0x3 line.long 0x0 "TRNG_HWCONF,'Generic g_AIS31Full value'" bitfld.long 0x0 9. "TRNG_AIS31FULL,'Generic g_AIS31Full value'" "0,1" newline bitfld.long 0x0 8. "TRNG_AIS31,'Generic g_AIS31 value'" "0,1" newline hexmask.long.byte 0x0 0.--7. 1. "TRNG_NUMBOFRINGS,'Generic g_NumRings value'" tree.end tree "ABC (Address Block 0 of sem)" group.long 0x0++0xB line.long 0x0 "SEM_COMMON_SET,SEM common settings" hexmask.long.byte 0x0 24.--31. 1. "CMP_ENABLE,compare output enable bits for int0-7" newline bitfld.long 0x0 23. "SIG_MON_GLB_EN,signal monitor global enable" "0,1" newline bitfld.long 0x0 17. "EI_GLOBAL_EN_LOCK,Error Injection Global Enable Lock bit" "0,1" newline bitfld.long 0x0 16. "EI_GLOBAL_EN,Error Injection Global Enable" "0,1" newline hexmask.long.byte 0x0 12.--15. 1. "ERROR_DIV,error divider ratio for waveform A" newline bitfld.long 0x0 11. "ERROR_WAVE_SEL,waveform A/B selection for normal/recoverable error" "0,1" newline bitfld.long 0x0 10. "FATAL_HIGH_LOW,fatal error High or Low selection" "0,1" newline bitfld.long 0x0 8.--9. "SEM_INT_DC4_SEL,SEM_INT DC4 selection" "0,1,2,3" newline bitfld.long 0x0 6.--7. "SEM_INT_DC3_SEL,SEM_INT DC3 selection" "0,1,2,3" newline bitfld.long 0x0 4.--5. "SEM_INT_DC2_SEL,SEM_INT DC2 selection" "0,1,2,3" newline bitfld.long 0x0 2.--3. "SEM_INT_DC1_SEL,SEM_INT DC1 selection" "0,1,2,3" newline bitfld.long 0x0 0.--1. "SEM_INT_DC0_SEL,SEM_INT DC0 selection" "0,1,2,3" line.long 0x4 "INT_TRIG,int0-7 trigger" hexmask.long.byte 0x4 0.--7. 1. "INT_TRIG,int0-int7 trigger" line.long 0x8 "INT_ENABLE_OVRD,int0-7 enable override" hexmask.long.byte 0x8 8.--15. 1. "INT_ENABLE_OVRD_VAL,int0-7 enable override value" newline hexmask.long.byte 0x8 0.--7. 1. "INT_ENABLE_OVRD_EN,int0-7 enable override enable" group.long 0x10++0x3 line.long 0x0 "IO_WAVE_CTRL,IO_WAVE_CTRL" bitfld.long 0x0 31. "LOCK,LOCK ctrl" "0,1" newline bitfld.long 0x0 2.--3. "LEVEL_CFG,the level io when normal [2] and recoverable err[3] take place" "0,1,2,3" newline bitfld.long 0x0 0.--1. "LEVEL_EN,if set the normal and recoverable output will be set as level [0] normal [1] recover case" "0,1,2,3" repeat 9. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 )(list 0x0 0x4 0x8 0xC 0x10 0x14 0x18 0x1C 0x20 ) rgroup.long ($2+0x80)++0x3 line.long 0x0 "INT_STATUS$1,Interrupt status" bitfld.long 0x0 31. "CANFD6_IPI_INT_CE,ipi_int_ce from CANFD6 Correctable error interrupt" "0,1" newline bitfld.long 0x0 30. "CANFD5_IPI_INT_NCEFA,ipi_int_ncefa from CANFD5 Non correctable error int internal" "0,1" newline bitfld.long 0x0 29. "CANFD5_IPI_INT_NCEHA,ipi_int_nceha from CANFD5 Non correctable error int host" "0,1" newline bitfld.long 0x0 28. "CANFD5_IPI_INT_CE,ipi_int_ce from CANFD5 Correctable error interrupt" "0,1" newline bitfld.long 0x0 27. "CANFD4_IPI_INT_NCEFA,ipi_int_ncefa from CANFD4 Non correctable error int internal" "0,1" newline bitfld.long 0x0 26. "CANFD4_IPI_INT_NCEHA,ipi_int_nceha from CANFD4 Non correctable error int host" "0,1" newline bitfld.long 0x0 25. "CANFD4_IPI_INT_CE,ipi_int_ce from CANFD4 Correctable error interrupt" "0,1" newline bitfld.long 0x0 24. "CANFD3_IPI_INT_NCEFA,ipi_int_ncefa from CANFD3 Non correctable error int internal" "0,1" newline bitfld.long 0x0 23. "CANFD3_IPI_INT_NCEHA,ipi_int_nceha from CANFD3 Non correctable error int host" "0,1" newline bitfld.long 0x0 22. "CANFD3_IPI_INT_CE,ipi_int_ce from CANFD3 Correctable error interrupt" "0,1" newline bitfld.long 0x0 21. "CANFD2_IPI_INT_NCEFA,ipi_int_ncefa from CANFD2 Non correctable error int internal" "0,1" newline bitfld.long 0x0 20. "CANFD2_IPI_INT_NCEHA,ipi_int_nceha from CANFD2 Non correctable error int host" "0,1" newline bitfld.long 0x0 19. "CANFD2_IPI_INT_CE,ipi_int_ce from CANFD2 Correctable error interrupt" "0,1" newline bitfld.long 0x0 18. "CANFD1_IPI_INT_NCEFA,ipi_int_ncefa from CANFD1 Non correctable error int internal" "0,1" newline bitfld.long 0x0 17. "CANFD1_IPI_INT_NCEHA,ipi_int_nceha from CANFD1 Non correctable error int host" "0,1" newline bitfld.long 0x0 16. "CANFD1_IPI_INT_CE,ipi_int_ce from CANFD1 Correctable error interrupt" "0,1" newline bitfld.long 0x0 15. "ENET2_SBD_SFTY_UE_INTR_O,sbd_sfty_ue_intr_o from ENET2 None" "0,1" newline bitfld.long 0x0 14. "ENET2_SBD_SFTY_CE_INTR_O,sbd_sfty_ce_intr_o from ENET2 None" "0,1" newline bitfld.long 0x0 13. "ENET1_SBD_SFTY_UE_INTR_O,sbd_sfty_ue_intr_o from ENET1 None" "0,1" newline bitfld.long 0x0 12. "ENET1_SBD_SFTY_CE_INTR_O,sbd_sfty_ce_intr_o from ENET1 None" "0,1" newline bitfld.long 0x0 11. "ROMC2_MUL_ERR_INT,mul_err_int from ROMC2 None" "0,1" newline bitfld.long 0x0 10. "ROMC2_SIG_ERR_INT,sig_err_int from ROMC2 None" "0,1" newline bitfld.long 0x0 9. "ROMC1_MUL_ERR_INT,mul_err_int from ROMC1 None" "0,1" newline bitfld.long 0x0 8. "ROMC1_SIG_ERR_INT,sig_err_int from ROMC1 None" "0,1" newline bitfld.long 0x0 7. "IRAM4_MUL_ERR_INT,mul_err_int from IRAM4 None" "0,1" newline bitfld.long 0x0 6. "IRAM4_SIG_ERR_INT,sig_err_int from IRAM4 None" "0,1" newline bitfld.long 0x0 5. "IRAM3_MUL_ERR_INT,mul_err_int from IRAM3 None" "0,1" newline bitfld.long 0x0 4. "IRAM3_SIG_ERR_INT,sig_err_int from IRAM3 None" "0,1" newline bitfld.long 0x0 3. "IRAM2_MUL_ERR_INT,mul_err_int from IRAM2 None" "0,1" newline bitfld.long 0x0 2. "IRAM2_SIG_ERR_INT,sig_err_int from IRAM2 None" "0,1" newline bitfld.long 0x0 1. "IRAM1_MUL_ERR_INT,mul_err_int from IRAM1 None" "0,1" newline bitfld.long 0x0 0. "IRAM1_SIG_ERR_INT,sig_err_int from IRAM1 None" "0,1" repeat.end rgroup.long 0xA4++0x3 line.long 0x0 "INT_STATUS9,Interrupt status" bitfld.long 0x0 30. "PVT_SNS_SAF_PVT_INT_1,pvt_int_1 from PVT_SNS_SAF None" "0,1" newline bitfld.long 0x0 29. "PVT_SNS_SAF_PVT_INT_0,pvt_int_0 from PVT_SNS_SAF None" "0,1" newline bitfld.long 0x0 28. "PVT_SNS_SEC_PVT_INT_1,pvt_int_1 from PVT_SNS_SEC None" "0,1" newline bitfld.long 0x0 27. "PVT_SNS_SEC_PVT_INT_0,pvt_int_0 from PVT_SNS_SEC None" "0,1" newline bitfld.long 0x0 26. "WDT8_ILL_SEQ_REFR_INT,ill_seq_refr_int from WDT8 None" "0,1" newline bitfld.long 0x0 25. "WDT8_ILL_WIN_REFR_INT,ill_win_refr_int from WDT8 None" "0,1" newline bitfld.long 0x0 24. "WDT8_OVFLOW_INT,ovflow_int from WDT8 None" "0,1" newline bitfld.long 0x0 23. "WDT7_ILL_SEQ_REFR_INT,ill_seq_refr_int from WDT7 None" "0,1" newline bitfld.long 0x0 22. "WDT7_ILL_WIN_REFR_INT,ill_win_refr_int from WDT7 None" "0,1" newline bitfld.long 0x0 21. "WDT7_OVFLOW_INT,ovflow_int from WDT7 None" "0,1" newline bitfld.long 0x0 20. "WDT6_ILL_SEQ_REFR_INT,ill_seq_refr_int from WDT6 None" "0,1" newline bitfld.long 0x0 19. "WDT6_ILL_WIN_REFR_INT,ill_win_refr_int from WDT6 None" "0,1" newline bitfld.long 0x0 18. "WDT6_OVFLOW_INT,ovflow_int from WDT6 None" "0,1" newline bitfld.long 0x0 17. "WDT5_ILL_SEQ_REFR_INT,ill_seq_refr_int from WDT5 None" "0,1" newline bitfld.long 0x0 16. "WDT5_ILL_WIN_REFR_INT,ill_win_refr_int from WDT5 None" "0,1" newline bitfld.long 0x0 15. "WDT5_OVFLOW_INT,ovflow_int from WDT5 None" "0,1" newline bitfld.long 0x0 14. "WDT4_ILL_SEQ_REFR_INT,ill_seq_refr_int from WDT4 None" "0,1" newline bitfld.long 0x0 13. "WDT4_ILL_WIN_REFR_INT,ill_win_refr_int from WDT4 None" "0,1" newline bitfld.long 0x0 12. "WDT4_OVFLOW_INT,ovflow_int from WDT4 None" "0,1" newline bitfld.long 0x0 11. "WDT3_ILL_SEQ_REFR_INT,ill_seq_refr_int from WDT3 None" "0,1" newline bitfld.long 0x0 10. "WDT3_ILL_WIN_REFR_INT,ill_win_refr_int from WDT3 None" "0,1" newline bitfld.long 0x0 9. "WDT3_OVFLOW_INT,ovflow_int from WDT3 None" "0,1" newline bitfld.long 0x0 8. "WDT2_ILL_SEQ_REFR_INT,ill_seq_refr_int from WDT2 None" "0,1" newline bitfld.long 0x0 7. "WDT2_ILL_WIN_REFR_INT,ill_win_refr_int from WDT2 None" "0,1" newline bitfld.long 0x0 6. "WDT2_OVFLOW_INT,ovflow_int from WDT2 None" "0,1" newline bitfld.long 0x0 5. "WDT1_ILL_SEQ_REFR_INT,ill_seq_refr_int from WDT1 None" "0,1" newline bitfld.long 0x0 4. "WDT1_ILL_WIN_REFR_INT,ill_win_refr_int from WDT1 None" "0,1" newline bitfld.long 0x0 3. "WDT1_OVFLOW_INT,ovflow_int from WDT1 None" "0,1" newline bitfld.long 0x0 2. "PWR_LAT_RTC_AP_POWER_LAT,ap_power_lat from PWR_LAT_RTC AP domain power fail" "0,1" newline bitfld.long 0x0 1. "PWR_LAT_RTC_SAF_POWER_LAT,saf_power_lat from PWR_LAT_RTC SAF domain power fail" "0,1" newline bitfld.long 0x0 0. "PWR_LAT_SAF_SAF_POWER_LAT,saf_power_lat from PWR_LAT_SAF SAF power fail" "0,1" group.long 0x100++0x3 line.long 0x0 "INT_ENABLE_00,Interrupt Enable 0" bitfld.long 0x0 31. "CANFD6_IPI_INT_CE,ipi_int_ce from CANFD6 Correctable error interrupt" "0,1" newline bitfld.long 0x0 30. "CANFD5_IPI_INT_NCEFA,ipi_int_ncefa from CANFD5 Non correctable error int internal" "0,1" newline bitfld.long 0x0 29. "CANFD5_IPI_INT_NCEHA,ipi_int_nceha from CANFD5 Non correctable error int host" "0,1" newline bitfld.long 0x0 28. "CANFD5_IPI_INT_CE,ipi_int_ce from CANFD5 Correctable error interrupt" "0,1" newline bitfld.long 0x0 27. "CANFD4_IPI_INT_NCEFA,ipi_int_ncefa from CANFD4 Non correctable error int internal" "0,1" newline bitfld.long 0x0 26. "CANFD4_IPI_INT_NCEHA,ipi_int_nceha from CANFD4 Non correctable error int host" "0,1" newline bitfld.long 0x0 25. "CANFD4_IPI_INT_CE,ipi_int_ce from CANFD4 Correctable error interrupt" "0,1" newline bitfld.long 0x0 24. "CANFD3_IPI_INT_NCEFA,ipi_int_ncefa from CANFD3 Non correctable error int internal" "0,1" newline bitfld.long 0x0 23. "CANFD3_IPI_INT_NCEHA,ipi_int_nceha from CANFD3 Non correctable error int host" "0,1" newline bitfld.long 0x0 22. "CANFD3_IPI_INT_CE,ipi_int_ce from CANFD3 Correctable error interrupt" "0,1" newline bitfld.long 0x0 21. "CANFD2_IPI_INT_NCEFA,ipi_int_ncefa from CANFD2 Non correctable error int internal" "0,1" newline bitfld.long 0x0 20. "CANFD2_IPI_INT_NCEHA,ipi_int_nceha from CANFD2 Non correctable error int host" "0,1" newline bitfld.long 0x0 19. "CANFD2_IPI_INT_CE,ipi_int_ce from CANFD2 Correctable error interrupt" "0,1" newline bitfld.long 0x0 18. "CANFD1_IPI_INT_NCEFA,ipi_int_ncefa from CANFD1 Non correctable error int internal" "0,1" newline bitfld.long 0x0 17. "CANFD1_IPI_INT_NCEHA,ipi_int_nceha from CANFD1 Non correctable error int host" "0,1" newline bitfld.long 0x0 16. "CANFD1_IPI_INT_CE,ipi_int_ce from CANFD1 Correctable error interrupt" "0,1" newline bitfld.long 0x0 15. "ENET2_SBD_SFTY_UE_INTR_O,sbd_sfty_ue_intr_o from ENET2 None" "0,1" newline bitfld.long 0x0 14. "ENET2_SBD_SFTY_CE_INTR_O,sbd_sfty_ce_intr_o from ENET2 None" "0,1" newline bitfld.long 0x0 13. "ENET1_SBD_SFTY_UE_INTR_O,sbd_sfty_ue_intr_o from ENET1 None" "0,1" newline bitfld.long 0x0 12. "ENET1_SBD_SFTY_CE_INTR_O,sbd_sfty_ce_intr_o from ENET1 None" "0,1" newline bitfld.long 0x0 11. "RWMC2_MUL_ERR_INT,mul_err_int from RWMC2 None" "0,1" newline bitfld.long 0x0 10. "RWMC2_SIG_ERR_INT,sig_err_int from RWMC2 None" "0,1" newline bitfld.long 0x0 9. "RWMC1_MUL_ERR_INT,mul_err_int from RWMC1 None" "0,1" newline bitfld.long 0x0 8. "RWMC1_SIG_ERR_INT,sig_err_int from RWMC1 None" "0,1" newline bitfld.long 0x0 7. "IRAM4_MUL_ERR_INT,mul_err_int from IRAM4 None" "0,1" newline bitfld.long 0x0 6. "IRAM4_SIG_ERR_INT,sig_err_int from IRAM4 None" "0,1" newline bitfld.long 0x0 5. "IRAM3_MUL_ERR_INT,mul_err_int from IRAM3 None" "0,1" newline bitfld.long 0x0 4. "IRAM3_SIG_ERR_INT,sig_err_int from IRAM3 None" "0,1" newline bitfld.long 0x0 3. "IRAM2_MUL_ERR_INT,mul_err_int from IRAM2 None" "0,1" newline bitfld.long 0x0 2. "IRAM2_SIG_ERR_INT,sig_err_int from IRAM2 None" "0,1" newline bitfld.long 0x0 1. "IRAM1_MUL_ERR_INT,mul_err_int from IRAM1 None" "0,1" newline bitfld.long 0x0 0. "IRAM1_SIG_ERR_INT,sig_err_int from IRAM1 None" "0,1" repeat 16. (list 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0xA 0xB 0xC 0xD 0xE 0xF 0x10 0x11 )(list 0x0 0x4 0x8 0xC 0x10 0x14 0x18 0x1C 0x7C 0x80 0x84 0x88 0x8C 0x90 0x94 0x98 ) rgroup.long ($2+0x104)++0x3 line.long 0x0 "INT_ENABLE_$1,Interrupt Enable 0" bitfld.long 0x0 31. "NOC_SEC_S_14_MAINSGLDATAECCERR,s_14_mainSglDataEccErr from NOC_SEC None" "0,1" newline bitfld.long 0x0 30. "NOC_SEC_S_13_MAINSGLDATAECCERR,s_13_mainSglDataEccErr from NOC_SEC None" "0,1" newline bitfld.long 0x0 29. "NOC_SEC_S_3_MAINSGLDATAECCERR,s_3_mainSglDataEccErr from NOC_SEC None" "0,1" newline bitfld.long 0x0 28. "NOC_SEC_S_2_MAINSGLDATAECCERR,s_2_mainSglDataEccErr from NOC_SEC None" "0,1" newline bitfld.long 0x0 27. "NOC_SEC_S_1_MAINSGLECCERR,s_1_mainSglEccErr from NOC_SEC None" "0,1" newline bitfld.long 0x0 26. "NOC_SEC_S_0_MAINSGLECCERR,s_0_mainSglEccErr from NOC_SEC None" "0,1" newline bitfld.long 0x0 25. "NOC_SEC_M_9_I_MAININITIATOR_TIMEOUT_FAULT,m_9_I_mainInitiator_Timeout_Fault from NOC_SEC None" "0,1" newline bitfld.long 0x0 24. "NOC_SEC_M_8_I_MAININITIATOR_TIMEOUT_FAULT,m_8_I_mainInitiator_Timeout_Fault from NOC_SEC None" "0,1" newline bitfld.long 0x0 23. "NOC_SEC_M_7_I_MAININITIATOR_TIMEOUT_FAULT,m_7_I_mainInitiator_Timeout_Fault from NOC_SEC None" "0,1" newline bitfld.long 0x0 22. "NOC_SEC_M_6_I_MAININITIATOR_TIMEOUT_FAULT,m_6_I_mainInitiator_Timeout_Fault from NOC_SEC None" "0,1" newline bitfld.long 0x0 21. "NOC_SEC_M_5_I_MAININITIATOR_TIMEOUT_FAULT,m_5_I_mainInitiator_Timeout_Fault from NOC_SEC None" "0,1" newline bitfld.long 0x0 20. "NOC_SEC_M_5_MAINSGLDATAECCERR,m_5_mainSglDataEccErr from NOC_SEC None" "0,1" newline bitfld.long 0x0 19. "NOC_SEC_M_5_MAINSGLAWADDRECCERR,m_5_mainSglAwAddrEccErr from NOC_SEC None" "0,1" newline bitfld.long 0x0 18. "NOC_SEC_M_5_MAINSGLARADDRECCERR,m_5_mainSglArAddrEccErr from NOC_SEC None" "0,1" newline bitfld.long 0x0 17. "NOC_SEC_M_3_I_MAININITIATOR_TIMEOUT_FAULT,m_3_I_mainInitiator_Timeout_Fault from NOC_SEC None" "0,1" newline bitfld.long 0x0 16. "NOC_SEC_M_3_MAINSGLECCERR,m_3_mainSglEccErr from NOC_SEC Actually m_1_mainSglEccErr" "0,1" newline bitfld.long 0x0 15. "NOC_SEC_M_2_I_MAININITIATOR_TIMEOUT_FAULT,m_2_I_mainInitiator_Timeout_Fault from NOC_SEC None" "0,1" newline bitfld.long 0x0 14. "NOC_SEC_M_2_MAINSGLECCERR,m_2_mainSglEccErr from NOC_SEC Actually m_0_mainSglEccErr" "0,1" newline bitfld.long 0x0 13. "NOC_SEC_M_1_I_MAININITIATOR_TIMEOUT_FAULT,m_1_I_mainInitiator_Timeout_Fault from NOC_SEC None" "0,1" newline bitfld.long 0x0 12. "NOC_SEC_M_1_MAINSGLECCERR,m_1_mainSglEccErr from NOC_SEC Actually m_3_mainSglEccErr" "0,1" newline bitfld.long 0x0 11. "NOC_SEC_M_0_I_MAININITIATOR_TIMEOUT_FAULT,m_0_I_mainInitiator_Timeout_Fault from NOC_SEC None" "0,1" newline bitfld.long 0x0 10. "NOC_SEC_M_0_MAINSGLECCERR,m_0_mainSglEccErr from NOC_SEC Actually m_2_mainSglEccErr" "0,1" newline bitfld.long 0x0 9. "NOC_SEC_PD_SEC_MAINMISSIONINT,PD_SEC_mainMissionInt from NOC_SEC None OR ~PD_SEC_mainMissionIntBar from NOC_SEC None" "0,1" newline bitfld.long 0x0 8. "NOC_SEC_PD_SEC_MAINLATENTINT,PD_SEC_mainLatentInt from NOC_SEC None OR ~PD_SEC_mainLatentIntBar from NOC_SEC None" "0,1" newline bitfld.long 0x0 7. "CANFD8_IPI_INT_NCEFA,ipi_int_ncefa from CANFD8 Non correctable error int internal" "0,1" newline bitfld.long 0x0 6. "CANFD8_IPI_INT_NCEHA,ipi_int_nceha from CANFD8 Non correctable error int host" "0,1" newline bitfld.long 0x0 5. "CANFD8_IPI_INT_CE,ipi_int_ce from CANFD8 Correctable error interrupt" "0,1" newline bitfld.long 0x0 4. "CANFD7_IPI_INT_NCEFA,ipi_int_ncefa from CANFD7 Non correctable error int internal" "0,1" newline bitfld.long 0x0 3. "CANFD7_IPI_INT_NCEHA,ipi_int_nceha from CANFD7 Non correctable error int host" "0,1" newline bitfld.long 0x0 2. "CANFD7_IPI_INT_CE,ipi_int_ce from CANFD7 Correctable error interrupt" "0,1" newline bitfld.long 0x0 1. "CANFD6_IPI_INT_NCEFA,ipi_int_ncefa from CANFD6 Non correctable error int internal" "0,1" newline bitfld.long 0x0 0. "CANFD6_IPI_INT_NCEHA,ipi_int_nceha from CANFD6 Non correctable error int host" "0,1" repeat.end repeat 15. (list 0x12 0x14 0x15 0x16 0x17 0x18 0x19 0x1A 0x1B 0x1C 0x1E 0x1F 0x24 0x25 0x26 )(list 0x9C 0xFC 0x100 0x104 0x108 0x10C 0x110 0x114 0x118 0x11C 0x17C 0x180 0x194 0x198 0x19C ) rgroup.long ($2+0x104)++0x3 line.long 0x0 "INT_ENABLE_$1,Interrupt Enable 0" bitfld.long 0x0 31. "NOC_SEC_S_14_MAINSGLDATAECCERR,s_14_mainSglDataEccErr from NOC_SEC None" "0,1" newline bitfld.long 0x0 30. "NOC_SEC_S_13_MAINSGLDATAECCERR,s_13_mainSglDataEccErr from NOC_SEC None" "0,1" newline bitfld.long 0x0 29. "NOC_SEC_S_3_MAINSGLDATAECCERR,s_3_mainSglDataEccErr from NOC_SEC None" "0,1" newline bitfld.long 0x0 28. "NOC_SEC_S_2_MAINSGLDATAECCERR,s_2_mainSglDataEccErr from NOC_SEC None" "0,1" newline bitfld.long 0x0 27. "NOC_SEC_S_1_MAINSGLECCERR,s_1_mainSglEccErr from NOC_SEC None" "0,1" newline bitfld.long 0x0 26. "NOC_SEC_S_0_MAINSGLECCERR,s_0_mainSglEccErr from NOC_SEC None" "0,1" newline bitfld.long 0x0 25. "NOC_SEC_M_9_I_MAININITIATOR_TIMEOUT_FAULT,m_9_I_mainInitiator_Timeout_Fault from NOC_SEC None" "0,1" newline bitfld.long 0x0 24. "NOC_SEC_M_8_I_MAININITIATOR_TIMEOUT_FAULT,m_8_I_mainInitiator_Timeout_Fault from NOC_SEC None" "0,1" newline bitfld.long 0x0 23. "NOC_SEC_M_7_I_MAININITIATOR_TIMEOUT_FAULT,m_7_I_mainInitiator_Timeout_Fault from NOC_SEC None" "0,1" newline bitfld.long 0x0 22. "NOC_SEC_M_6_I_MAININITIATOR_TIMEOUT_FAULT,m_6_I_mainInitiator_Timeout_Fault from NOC_SEC None" "0,1" newline bitfld.long 0x0 21. "NOC_SEC_M_5_I_MAININITIATOR_TIMEOUT_FAULT,m_5_I_mainInitiator_Timeout_Fault from NOC_SEC None" "0,1" newline bitfld.long 0x0 20. "NOC_SEC_M_5_MAINSGLDATAECCERR,m_5_mainSglDataEccErr from NOC_SEC None" "0,1" newline bitfld.long 0x0 19. "NOC_SEC_M_5_MAINSGLAWADDRECCERR,m_5_mainSglAwAddrEccErr from NOC_SEC None" "0,1" newline bitfld.long 0x0 18. "NOC_SEC_M_5_MAINSGLARADDRECCERR,m_5_mainSglArAddrEccErr from NOC_SEC None" "0,1" newline bitfld.long 0x0 17. "NOC_SEC_M_3_I_MAININITIATOR_TIMEOUT_FAULT,m_3_I_mainInitiator_Timeout_Fault from NOC_SEC None" "0,1" newline bitfld.long 0x0 16. "NOC_SEC_M_3_MAINSGLECCERR,m_3_mainSglEccErr from NOC_SEC Actually m_1_mainSglEccErr" "0,1" newline bitfld.long 0x0 15. "NOC_SEC_M_2_I_MAININITIATOR_TIMEOUT_FAULT,m_2_I_mainInitiator_Timeout_Fault from NOC_SEC None" "0,1" newline bitfld.long 0x0 14. "NOC_SEC_M_2_MAINSGLECCERR,m_2_mainSglEccErr from NOC_SEC Actually m_0_mainSglEccErr" "0,1" newline bitfld.long 0x0 13. "NOC_SEC_M_1_I_MAININITIATOR_TIMEOUT_FAULT,m_1_I_mainInitiator_Timeout_Fault from NOC_SEC None" "0,1" newline bitfld.long 0x0 12. "NOC_SEC_M_1_MAINSGLECCERR,m_1_mainSglEccErr from NOC_SEC Actually m_3_mainSglEccErr" "0,1" newline bitfld.long 0x0 11. "NOC_SEC_M_0_I_MAININITIATOR_TIMEOUT_FAULT,m_0_I_mainInitiator_Timeout_Fault from NOC_SEC None" "0,1" newline bitfld.long 0x0 10. "NOC_SEC_M_0_MAINSGLECCERR,m_0_mainSglEccErr from NOC_SEC Actually m_2_mainSglEccErr" "0,1" newline bitfld.long 0x0 9. "NOC_SEC_PD_SEC_MAINMISSIONINT,PD_SEC_mainMissionInt from NOC_SEC None OR ~PD_SEC_mainMissionIntBar from NOC_SEC None" "0,1" newline bitfld.long 0x0 8. "NOC_SEC_PD_SEC_MAINLATENTINT,PD_SEC_mainLatentInt from NOC_SEC None OR ~PD_SEC_mainLatentIntBar from NOC_SEC None" "0,1" newline bitfld.long 0x0 7. "CANFD8_IPI_INT_NCEFA,ipi_int_ncefa from CANFD8 Non correctable error int internal" "0,1" newline bitfld.long 0x0 6. "CANFD8_IPI_INT_NCEHA,ipi_int_nceha from CANFD8 Non correctable error int host" "0,1" newline bitfld.long 0x0 5. "CANFD8_IPI_INT_CE,ipi_int_ce from CANFD8 Correctable error interrupt" "0,1" newline bitfld.long 0x0 4. "CANFD7_IPI_INT_NCEFA,ipi_int_ncefa from CANFD7 Non correctable error int internal" "0,1" newline bitfld.long 0x0 3. "CANFD7_IPI_INT_NCEHA,ipi_int_nceha from CANFD7 Non correctable error int host" "0,1" newline bitfld.long 0x0 2. "CANFD7_IPI_INT_CE,ipi_int_ce from CANFD7 Correctable error interrupt" "0,1" newline bitfld.long 0x0 1. "CANFD6_IPI_INT_NCEFA,ipi_int_ncefa from CANFD6 Non correctable error int internal" "0,1" newline bitfld.long 0x0 0. "CANFD6_IPI_INT_NCEHA,ipi_int_nceha from CANFD6 Non correctable error int host" "0,1" repeat.end repeat 4. (list 0x9 0x13 0x1D 0x27 )(list 0x0 0x80 0x100 0x180 ) rgroup.long ($2+0x124)++0x3 line.long 0x0 "INT_ENABLE_$1,Interrupt Enable 0" bitfld.long 0x0 30. "PVT_SNS_SAF_PVT_INT_1,pvt_int_1 from PVT_SNS_SAF None" "0,1" newline bitfld.long 0x0 29. "PVT_SNS_SAF_PVT_INT_0,pvt_int_0 from PVT_SNS_SAF None" "0,1" newline bitfld.long 0x0 28. "PVT_SNS_SEC_PVT_INT_1,pvt_int_1 from PVT_SNS_SEC None" "0,1" newline bitfld.long 0x0 27. "PVT_SNS_SEC_PVT_INT_0,pvt_int_0 from PVT_SNS_SEC None" "0,1" newline bitfld.long 0x0 26. "WDT8_ILL_SEQ_REFR_INT,ill_seq_refr_int from WDT8 None" "0,1" newline bitfld.long 0x0 25. "WDT8_ILL_WIN_REFR_INT,ill_win_refr_int from WDT8 None" "0,1" newline bitfld.long 0x0 24. "WDT8_OVFLOW_INT,ovflow_int from WDT8 None" "0,1" newline bitfld.long 0x0 23. "WDT7_ILL_SEQ_REFR_INT,ill_seq_refr_int from WDT7 None" "0,1" newline bitfld.long 0x0 22. "WDT7_ILL_WIN_REFR_INT,ill_win_refr_int from WDT7 None" "0,1" newline bitfld.long 0x0 21. "WDT7_OVFLOW_INT,ovflow_int from WDT7 None" "0,1" newline bitfld.long 0x0 20. "WDT6_ILL_SEQ_REFR_INT,ill_seq_refr_int from WDT6 None" "0,1" newline bitfld.long 0x0 19. "WDT6_ILL_WIN_REFR_INT,ill_win_refr_int from WDT6 None" "0,1" newline bitfld.long 0x0 18. "WDT6_OVFLOW_INT,ovflow_int from WDT6 None" "0,1" newline bitfld.long 0x0 17. "WDT5_ILL_SEQ_REFR_INT,ill_seq_refr_int from WDT5 None" "0,1" newline bitfld.long 0x0 16. "WDT5_ILL_WIN_REFR_INT,ill_win_refr_int from WDT5 None" "0,1" newline bitfld.long 0x0 15. "WDT5_OVFLOW_INT,ovflow_int from WDT5 None" "0,1" newline bitfld.long 0x0 14. "WDT4_ILL_SEQ_REFR_INT,ill_seq_refr_int from WDT4 None" "0,1" newline bitfld.long 0x0 13. "WDT4_ILL_WIN_REFR_INT,ill_win_refr_int from WDT4 None" "0,1" newline bitfld.long 0x0 12. "WDT4_OVFLOW_INT,ovflow_int from WDT4 None" "0,1" newline bitfld.long 0x0 11. "WDT3_ILL_SEQ_REFR_INT,ill_seq_refr_int from WDT3 None" "0,1" newline bitfld.long 0x0 10. "WDT3_ILL_WIN_REFR_INT,ill_win_refr_int from WDT3 None" "0,1" newline bitfld.long 0x0 9. "WDT3_OVFLOW_INT,ovflow_int from WDT3 None" "0,1" newline bitfld.long 0x0 8. "WDT2_ILL_SEQ_REFR_INT,ill_seq_refr_int from WDT2 None" "0,1" newline bitfld.long 0x0 7. "WDT2_ILL_WIN_REFR_INT,ill_win_refr_int from WDT2 None" "0,1" newline bitfld.long 0x0 6. "WDT2_OVFLOW_INT,ovflow_int from WDT2 None" "0,1" newline bitfld.long 0x0 5. "WDT1_ILL_SEQ_REFR_INT,ill_seq_refr_int from WDT1 None" "0,1" newline bitfld.long 0x0 4. "WDT1_ILL_WIN_REFR_INT,ill_win_refr_int from WDT1 None" "0,1" newline bitfld.long 0x0 3. "WDT1_OVFLOW_INT,ovflow_int from WDT1 None" "0,1" newline bitfld.long 0x0 2. "PWR_LAT_RTC_AP_POWER_LAT,ap_power_lat from PWR_LAT_RTC AP domain power fail" "0,1" newline bitfld.long 0x0 1. "PWR_LAT_RTC_SAF_POWER_LAT,saf_power_lat from PWR_LAT_RTC SAF domain power fail" "0,1" newline bitfld.long 0x0 0. "PWR_LAT_SAF_SAF_POWER_LAT,saf_power_lat from PWR_LAT_SAF SAF power fail" "0,1" repeat.end repeat 5. (list 0x20 0x2A 0x34 0x3E 0x48 )(list 0x0 0x80 0x100 0x180 0x200 ) rgroup.long ($2+0x288)++0x3 line.long 0x0 "INT_ENABLE_$1,m_18_I_mainInitiator_Timeout_Fault from NOC_MAIN None" bitfld.long 0x0 31. "NOC_MAIN_M_18_I_MAININITIATOR_TIMEOUT_FAULT,m_18_I_mainInitiator_Timeout_Fault from NOC_MAIN None" "0,1" newline bitfld.long 0x0 30. "NOC_MAIN_M_17_I_MAININITIATOR_TIMEOUT_FAULT,m_17_I_mainInitiator_Timeout_Fault from NOC_MAIN None" "0,1" newline bitfld.long 0x0 29. "NOC_MAIN_M_14_I_MAININITIATOR_TIMEOUT_FAULT,m_14_I_mainInitiator_Timeout_Fault from NOC_MAIN None" "0,1" newline bitfld.long 0x0 28. "NOC_MAIN_M_13_I_MAININITIATOR_TIMEOUT_FAULT,m_13_I_mainInitiator_Timeout_Fault from NOC_MAIN None" "0,1" newline bitfld.long 0x0 27. "NOC_MAIN_M_12_I_MAININITIATOR_TIMEOUT_FAULT,m_12_I_mainInitiator_Timeout_Fault from NOC_MAIN None" "0,1" newline bitfld.long 0x0 26. "NOC_MAIN_M_12_MAINSGLARADDRECCERR,m_12_mainSglArAddrEccErr from NOC_MAIN None OR m_12_mainSglAwAddrEccErr from NOC_MAIN None OR m_12_mainSglDataEccErr from NOC_MAIN None" "0,1" newline bitfld.long 0x0 25. "NOC_MAIN_M_11_I_MAININITIATOR_TIMEOUT_FAULT,m_11_I_mainInitiator_Timeout_Fault from NOC_MAIN None" "0,1" newline bitfld.long 0x0 24. "NOC_MAIN_M_11_MAINSGLARADDRECCERR,m_11_mainSglArAddrEccErr from NOC_MAIN None OR m_11_mainSglAwAddrEccErr from NOC_MAIN None OR m_11_mainSglDataEccErr from NOC_MAIN None" "0,1" newline bitfld.long 0x0 23. "NOC_MAIN_M_10_I_MAININITIATOR_TIMEOUT_FAULT,m_10_I_mainInitiator_Timeout_Fault from NOC_MAIN None" "0,1" newline bitfld.long 0x0 22. "NOC_MAIN_M_9_I_MAININITIATOR_TIMEOUT_FAULT,m_9_I_mainInitiator_Timeout_Fault from NOC_MAIN None" "0,1" newline bitfld.long 0x0 21. "NOC_MAIN_M_8_I_MAININITIATOR_TIMEOUT_FAULT,m_8_I_mainInitiator_Timeout_Fault from NOC_MAIN None" "0,1" newline bitfld.long 0x0 20. "NOC_MAIN_M_7_I_MAININITIATOR_TIMEOUT_FAULT,m_7_I_mainInitiator_Timeout_Fault from NOC_MAIN None" "0,1" newline bitfld.long 0x0 19. "NOC_MAIN_M_6_I_MAININITIATOR_TIMEOUT_FAULT,m_6_I_mainInitiator_Timeout_Fault from NOC_MAIN None" "0,1" newline bitfld.long 0x0 18. "NOC_MAIN_M_5_I_MAININITIATOR_TIMEOUT_FAULT,m_5_I_mainInitiator_Timeout_Fault from NOC_MAIN None" "0,1" newline bitfld.long 0x0 17. "NOC_MAIN_M_4_I_MAININITIATOR_TIMEOUT_FAULT,m_4_I_mainInitiator_Timeout_Fault from NOC_MAIN None" "0,1" newline bitfld.long 0x0 16. "NOC_MAIN_M_3_I_MAININITIATOR_TIMEOUT_FAULT,m_3_I_mainInitiator_Timeout_Fault from NOC_MAIN None" "0,1" newline bitfld.long 0x0 15. "NOC_MAIN_M_2_I_MAININITIATOR_TIMEOUT_FAULT,m_2_I_mainInitiator_Timeout_Fault from NOC_MAIN None" "0,1" newline bitfld.long 0x0 14. "NOC_MAIN_M_1_I_MAININITIATOR_TIMEOUT_FAULT,m_1_I_mainInitiator_Timeout_Fault from NOC_MAIN None" "0,1" newline bitfld.long 0x0 13. "NOC_MAIN_M_0_I_MAININITIATOR_TIMEOUT_FAULT,m_0_I_mainInitiator_Timeout_Fault from NOC_MAIN None" "0,1" newline bitfld.long 0x0 12. "NOC_MAIN_SOC_MAINMISSIONINT,SOC_mainMissionInt from NOC_MAIN None OR ~SOC_mainMissionIntBar from NOC_MAIN None" "0,1" newline bitfld.long 0x0 11. "NOC_MAIN_SOC_MAINLATENTINT,SOC_mainLatentInt from NOC_MAIN None OR ~SOC_mainLatentIntBar from NOC_MAIN None" "0,1" newline bitfld.long 0x0 10. "NOC_VSN_S_3_MAINSGLDATAECCERR,s_3_mainSglDataEccErr from NOC_VSN None" "0,1" newline bitfld.long 0x0 9. "NOC_VSN_S_0_MAINSGLDATAECCERR,s_0_mainSglDataEccErr from NOC_VSN None OR PFaultInfoValid from VDSP None" "0,1" newline bitfld.long 0x0 8. "NOC_VSN_M_2_I_MAININITIATOR_TIMEOUT_FAULT,m_2_I_mainInitiator_Timeout_Fault from NOC_VSN None" "0,1" newline bitfld.long 0x0 7. "NOC_VSN_M_2_MAINSGLARADDRECCERR,m_2_mainSglArAddrEccErr from NOC_VSN None OR m_2_mainSglAwAddrEccErr from NOC_VSN None OR m_2_mainSglDataEccErr from NOC_VSN None" "0,1" newline bitfld.long 0x0 6. "NOC_VSN_M_1_I_MAININITIATOR_TIMEOUT_FAULT,m_1_I_mainInitiator_Timeout_Fault from NOC_VSN None" "0,1" newline bitfld.long 0x0 5. "NOC_VSN_M_1_MAINSGLARADDRECCERR,m_1_mainSglArAddrEccErr from NOC_VSN None OR m_1_mainSglAwAddrEccErr from NOC_VSN None OR m_1_mainSglDataEccErr from NOC_VSN None" "0,1" newline bitfld.long 0x0 4. "NOC_VSN_M_0_I_MAININITIATOR_TIMEOUT_FAULT,m_0_I_mainInitiator_Timeout_Fault from NOC_VSN None" "0,1" newline bitfld.long 0x0 3. "NOC_VSN_M_0_MAINSGLARADDRECCERR,m_0_mainSglArAddrEccErr from NOC_VSN None OR m_0_mainSglAwAddrEccErr from NOC_VSN None OR m_0_mainSglDataEccErr from NOC_VSN None" "0,1" newline bitfld.long 0x0 2. "NOC_VSN_PD_VSN_MAINMISSIONINT,PD_VSN_mainMissionInt from NOC_VSN None OR ~PD_VSN_mainMissionIntBar from NOC_VSN None" "0,1" newline bitfld.long 0x0 1. "NOC_VSN_PD_VSN_MAINLATENTINT,PD_VSN_mainLatentInt from NOC_VSN None OR ~PD_VSN_mainLatentIntBar from NOC_VSN None" "0,1" newline bitfld.long 0x0 0. "NOC_SEC_S_17_MAINSGLDATAECCERR,s_17_mainSglDataEccErr from NOC_SEC None" "0,1" repeat.end repeat 5. (list 0x21 0x2B 0x35 0x3F 0x49 )(list 0x0 0x80 0x100 0x180 0x200 ) rgroup.long ($2+0x28C)++0x3 line.long 0x0 "INT_ENABLE_$1,m_6_I_mainInitiator_Timeout_Fault from NOC_SAF None" bitfld.long 0x0 31. "NOC_SAF_M_6_I_MAININITIATOR_TIMEOUT_FAULT,m_6_I_mainInitiator_Timeout_Fault from NOC_SAF None" "0,1" newline bitfld.long 0x0 30. "NOC_SAF_M_5_I_MAININITIATOR_TIMEOUT_FAULT,m_5_I_mainInitiator_Timeout_Fault from NOC_SAF None" "0,1" newline bitfld.long 0x0 29. "NOC_SAF_M_4_I_MAININITIATOR_TIMEOUT_FAULT,m_4_I_mainInitiator_Timeout_Fault from NOC_SAF None" "0,1" newline bitfld.long 0x0 28. "NOC_SAF_M_4_MAINDUPL_SGLARADDRECCERR,m_4_mainDupl_SglArAddrEccErr from NOC_SAF None OR m_4_mainDupl_SglAwAddrEccErr from NOC_SAF None OR m_4_mainDupl_SglDataEccErr from NOC_SAF None" "0,1" newline bitfld.long 0x0 27. "NOC_SAF_M_4_MAINMAIN_SGLARADDRECCERR,m_4_mainMain_SglArAddrEccErr from NOC_SAF None OR m_4_mainMain_SglAwAddrEccErr from NOC_SAF None OR m_4_mainMain_SglDataEccErr from NOC_SAF None" "0,1" newline bitfld.long 0x0 26. "NOC_SAF_M_3_I_MAININITIATOR_TIMEOUT_FAULT,m_3_I_mainInitiator_Timeout_Fault from NOC_SAF None" "0,1" newline bitfld.long 0x0 25. "NOC_SAF_M_2_I_MAININITIATOR_TIMEOUT_FAULT,m_2_I_mainInitiator_Timeout_Fault from NOC_SAF None" "0,1" newline bitfld.long 0x0 24. "NOC_SAF_M_1_I_MAININITIATOR_TIMEOUT_FAULT,m_1_I_mainInitiator_Timeout_Fault from NOC_SAF None" "0,1" newline bitfld.long 0x0 23. "NOC_SAF_M_1_MAINMAIN_SGLECCERR,m_1_mainMain_SglEccErr from NOC_SAF None" "0,1" newline bitfld.long 0x0 22. "NOC_SAF_M_1_MAINDUPL_SGLECCERR,m_1_mainDupl_SglEccErr from NOC_SAF None" "0,1" newline bitfld.long 0x0 21. "NOC_SAF_M_0_I_MAININITIATOR_TIMEOUT_FAULT,m_0_I_mainInitiator_Timeout_Fault from NOC_SAF None" "0,1" newline bitfld.long 0x0 20. "NOC_SAF_M_0_MAINMAIN_SGLECCERR,m_0_mainMain_SglEccErr from NOC_SAF None" "0,1" newline bitfld.long 0x0 19. "NOC_SAF_M_0_MAINDUPL_SGLECCERR,m_0_mainDupl_SglEccErr from NOC_SAF None" "0,1" newline bitfld.long 0x0 18. "NOC_SAF_PD_SAF_MAINMISSIONINT,PD_SAF_mainMissionInt from NOC_SAF None OR ~PD_SAF_mainMissionIntBar from NOC_SAF None" "0,1" newline bitfld.long 0x0 17. "NOC_SAF_PD_SAF_MAINLATENTINT,PD_SAF_mainLatentInt from NOC_SAF None OR ~PD_SAF_mainLatentIntBar from NOC_SAF None" "0,1" newline bitfld.long 0x0 16. "NOC_MAINB_M_2_I_MAININITIATOR_TIMEOUT_FAULT,m_2_I_mainInitiator_Timeout_Fault from NOC_MAINB None" "0,1" newline bitfld.long 0x0 15. "NOC_MAINB_M_1_I_MAININITIATOR_TIMEOUT_FAULT,m_1_I_mainInitiator_Timeout_Fault from NOC_MAINB None" "0,1" newline bitfld.long 0x0 14. "NOC_MAINB_M_0_I_MAININITIATOR_TIMEOUT_FAULT,m_0_I_mainInitiator_Timeout_Fault from NOC_MAINB None" "0,1" newline bitfld.long 0x0 13. "NOC_MAINB_M_0_MAINSGLARADDRECCERR,m_0_mainSglArAddrEccErr from NOC_MAINB None OR m_0_mainSglAwAddrEccErr from NOC_MAINB None OR m_0_mainSglDataEccErr from NOC_MAINB None" "0,1" newline bitfld.long 0x0 12. "NOC_MAINB_HPIB_MAINMISSIONINT,HPIb_mainMissionInt from NOC_MAINB None OR ~SAF_mainMissionIntBar from NOC_MAINB None" "0,1" newline bitfld.long 0x0 11. "NOC_MAINB_HPIB_MAINLATENTINT,HPIb_mainLatentInt from NOC_MAINB None OR ~SAF_mainLatentIntBar from NOC_MAINB None" "0,1" newline bitfld.long 0x0 10. "NOC_MAIN_S_11_MAINSGLDATAECCERR,s_11_mainSglDataEccErr from NOC_MAIN None" "0,1" newline bitfld.long 0x0 9. "NOC_MAIN_S_4_MAINSGLDATAECCERR,s_4_mainSglDataEccErr from NOC_MAIN None" "0,1" newline bitfld.long 0x0 8. "NOC_MAIN_S_3_MAINSGLDATAECCERR,s_3_mainSglDataEccErr from NOC_MAIN None" "0,1" newline bitfld.long 0x0 7. "NOC_MAIN_S_0_SBP_MAINSGLDATAECCERR,s_0_sbp_mainSglDataEccErr from NOC_MAIN None" "0,1" newline bitfld.long 0x0 6. "NOC_MAIN_M_16_I_MAININITIATOR_TIMEOUT_FAULT,m_16_I_mainInitiator_Timeout_Fault from NOC_MAIN None OR m_24_I_mainInitiator_Timeout_Fault from NOC_MAIN None" "0,1" newline bitfld.long 0x0 5. "NOC_MAIN_M_24_MAINSGLARADDRECCERR,m_24_mainSglArAddrEccErr from NOC_MAIN None OR m_24_mainSglAwAddrEccErr from NOC_MAIN None OR m_24_mainSglDataEccErr from NOC_MAIN None" "0,1" newline bitfld.long 0x0 4. "NOC_MAIN_M_23_I_MAININITIATOR_TIMEOUT_FAULT,m_23_I_mainInitiator_Timeout_Fault from NOC_MAIN None" "0,1" newline bitfld.long 0x0 3. "NOC_MAIN_M_22_I_MAININITIATOR_TIMEOUT_FAULT,m_22_I_mainInitiator_Timeout_Fault from NOC_MAIN None" "0,1" newline bitfld.long 0x0 2. "NOC_MAIN_M_21_I_MAININITIATOR_TIMEOUT_FAULT,m_21_I_mainInitiator_Timeout_Fault from NOC_MAIN None" "0,1" newline bitfld.long 0x0 1. "NOC_MAIN_M_20_I_MAININITIATOR_TIMEOUT_FAULT,m_20_I_mainInitiator_Timeout_Fault from NOC_MAIN None" "0,1" newline bitfld.long 0x0 0. "NOC_MAIN_M_19_I_MAININITIATOR_TIMEOUT_FAULT,m_19_I_mainInitiator_Timeout_Fault from NOC_MAIN None" "0,1" repeat.end repeat 5. (list 0x22 0x2C 0x36 0x40 0x4A )(list 0x0 0x80 0x100 0x180 0x200 ) rgroup.long ($2+0x290)++0x3 line.long 0x0 "INT_ENABLE_$1,crc32_irq from DC2 None" bitfld.long 0x0 31. "DC2_CRC32_IRQ,crc32_irq from DC2 None" "0,1" newline bitfld.long 0x0 30. "DC2_DC_CH_UNDERRUN,dc_ch_underrun from DC2 None" "0,1" newline bitfld.long 0x0 29. "DC1_CRC32_IRQ,crc32_irq from DC1 None" "0,1" newline bitfld.long 0x0 28. "DC1_DC_CH_UNDERRUN,dc_ch_underrun from DC1 None" "0,1" newline bitfld.long 0x0 27. "DDR_SS_DDR_SS_FUNC_SAF_NONFATL_INT,ddr_ss_func_saf_nonfatl_int from DDR_SS None" "0,1" newline bitfld.long 0x0 26. "DDR_SS_DDR_SS_FUNC_SAF_FATL_INT,ddr_ss_func_saf_fatl_int from DDR_SS None" "0,1" newline bitfld.long 0x0 25. "BIPC_ENET1_ECC_ERR_MULTIPLE,ecc_err_multiple from BIPC_ENET1 None" "0,1" newline bitfld.long 0x0 24. "BIPC_ENET1_ECC_ERR_SINGLE,ecc_err_single from BIPC_ENET1 None" "0,1" newline bitfld.long 0x0 23. "BIPC_VDSP_ECC_ERR_MULTIPLE,ecc_err_multiple from BIPC_VDSP None" "0,1" newline bitfld.long 0x0 22. "BIPC_VDSP_ECC_ERR_SINGLE,ecc_err_single from BIPC_VDSP None" "0,1" newline bitfld.long 0x0 21. "BIPC_DDR_ECC_ERR_MULTIPLE,ecc_err_multiple from BIPC_DDR None" "0,1" newline bitfld.long 0x0 20. "BIPC_DDR_ECC_ERR_SINGLE,ecc_err_single from BIPC_DDR None" "0,1" newline bitfld.long 0x0 19. "MPC_DDR_UNC_ERR_INT,unc_err_int from MPC_DDR None" "0,1" newline bitfld.long 0x0 18. "MPC_DDR_COR_ERR_INT,cor_err_int from MPC_DDR None" "0,1" newline bitfld.long 0x0 17. "MPC_ROMC2_UNC_ERR_INT,unc_err_int from MPC_ROMC2 None" "0,1" newline bitfld.long 0x0 16. "MPC_ROMC2_COR_ERR_INT,cor_err_int from MPC_ROMC2 None" "0,1" newline bitfld.long 0x0 15. "MPC_IRAM4_UNC_ERR_INT,unc_err_int from MPC_IRAM4 None" "0,1" newline bitfld.long 0x0 14. "MPC_IRAM4_COR_ERR_INT,cor_err_int from MPC_IRAM4 None" "0,1" newline bitfld.long 0x0 13. "MPC_IRAM3_UNC_ERR_INT,unc_err_int from MPC_IRAM3 None" "0,1" newline bitfld.long 0x0 12. "MPC_IRAM3_COR_ERR_INT,cor_err_int from MPC_IRAM3 None" "0,1" newline bitfld.long 0x0 11. "MPC_IRAM2_UNC_ERR_INT,unc_err_int from MPC_IRAM2 None" "0,1" newline bitfld.long 0x0 10. "MPC_IRAM2_COR_ERR_INT,cor_err_int from MPC_IRAM2 None" "0,1" newline bitfld.long 0x0 9. "MPC_IRAM1_UNC_ERR_INT,unc_err_int from MPC_IRAM1 None" "0,1" newline bitfld.long 0x0 8. "MPC_IRAM1_COR_ERR_INT,cor_err_int from MPC_IRAM1 None" "0,1" newline bitfld.long 0x0 7. "NOC_SAF_S_4_MAINMAIN_SGLDATAECCERR,s_4_mainMain_SglDataEccErr from NOC_SAF None" "0,1" newline bitfld.long 0x0 6. "NOC_SAF_S_4_MAINDUPL_SGLDATAECCERR,s_4_mainDupl_SglDataEccErr from NOC_SAF None" "0,1" newline bitfld.long 0x0 5. "NOC_SAF_S_2_MAINMAIN_SGLDATAECCERR,s_2_mainMain_SglDataEccErr from NOC_SAF None" "0,1" newline bitfld.long 0x0 4. "NOC_SAF_S_2_MAINDUPL_SGLDATAECCERR,s_2_mainDupl_SglDataEccErr from NOC_SAF None" "0,1" newline bitfld.long 0x0 3. "NOC_SAF_S_1_MAINMAIN_SGLDATAECCERR,s_1_mainMain_SglDataEccErr from NOC_SAF None" "0,1" newline bitfld.long 0x0 2. "NOC_SAF_S_1_MAINDUPL_SGLDATAECCERR,s_1_mainDupl_SglDataEccErr from NOC_SAF None" "0,1" newline bitfld.long 0x0 1. "NOC_SAF_S_0_MAINMAIN_SGLECCERR,s_0_mainMain_SglEccErr from NOC_SAF None" "0,1" newline bitfld.long 0x0 0. "NOC_SAF_S_0_MAINDUPL_SGLECCERR,s_0_mainDupl_SglEccErr from NOC_SAF None" "0,1" repeat.end repeat 5. (list 0x23 0x2D 0x37 0x41 0x4B )(list 0x0 0x80 0x100 0x180 0x200 ) rgroup.long ($2+0x294)++0x3 line.long 0x0 "INT_ENABLE_$1,aximfatal0[0] from CR5_SAF data errors and any parity errors on the AXI master" bitfld.long 0x0 31. "CR5_SAF_AXIMFATAL0[0],aximfatal0[0] from CR5_SAF data errors and any parity errors on the AXI master" "0,1" newline bitfld.long 0x0 30. "CR5_SAF_PPHCORR0,pphcorr0 from CR5_SAF data errors on reads by the AHB Peripheral Port" "0,1" newline bitfld.long 0x0 29. "CR5_SAF_PPXCORR0,ppxcorr0 from CR5_SAF data errors on reads by the AXI Peripheral Port" "0,1" newline bitfld.long 0x0 28. "CR5_SAF_AXISCORR0,axiscorr0 from CR5_SAF data errors on writes to the AXI Slave" "0,1" newline bitfld.long 0x0 27. "CR5_SAF_AXIMCORR0,aximcorr0 from CR5_SAF data errors on reads by the AXI Master" "0,1" newline bitfld.long 0x0 26. "OSPI2_O_IRQ_UNCORR,o_irq_uncorr from OSPI2 None" "0,1" newline bitfld.long 0x0 25. "OSPI2_O_IRQ_CORR,o_irq_corr from OSPI2 None" "0,1" newline bitfld.long 0x0 24. "OSPI1_O_IRQ_UNCORR,o_irq_uncorr from OSPI1 None" "0,1" newline bitfld.long 0x0 23. "OSPI1_O_IRQ_CORR,o_irq_corr from OSPI1 None" "0,1" newline bitfld.long 0x0 22. "EFUSEC_FATAL_ERR_INT,fatal_err_int from EFUSEC None" "0,1" newline bitfld.long 0x0 21. "EFUSEC_NORMAL_ERR_INT,normal_err_int from EFUSEC None" "0,1" newline bitfld.long 0x0 20. "PCIE_SS_O_PCIEX1_SAFETY_CORR,o_pciex1_safety_corr from PCIE_SS PCIE correctable error" "0,1" newline bitfld.long 0x0 19. "PCIE_SS_O_PCIEX1_SAFETY_UNCORR,o_pciex1_safety_uncorr from PCIE_SS PCIE non correctable error" "0,1" newline bitfld.long 0x0 18. "PCIE_SS_O_PCIEX2_SAFETY_CORR,o_pciex2_safety_corr from PCIE_SS PCIE correctable error" "0,1" newline bitfld.long 0x0 17. "PCIE_SS_O_PCIEX2_SAFETY_UNCORR,o_pciex2_safety_uncorr from PCIE_SS PCIE non correctable error" "0,1" newline bitfld.long 0x0 16. "ADC_CHANNEL_EVENT4,channel_event4 from ADC None OR channel_event5 from ADC None OR channel_event6 from ADC None OR channel_event7 from ADC None" "0,1" newline bitfld.long 0x0 15. "ADC_CHANNEL_EVENT3,channel_event3 from ADC None" "0,1" newline bitfld.long 0x0 14. "ADC_CHANNEL_EVENT2,channel_event2 from ADC None" "0,1" newline bitfld.long 0x0 13. "ADC_CHANNEL_EVENT1,channel_event1 from ADC None" "0,1" newline bitfld.long 0x0 12. "ADC_CHANNEL_EVENT0,channel_event0 from ADC None" "0,1" newline bitfld.long 0x0 11. "VDSP_DOUBLEEXCEPTIONERROR,DoubleExceptionError from VDSP None" "0,1" newline bitfld.long 0x0 10. "VDSP_PFATALERROR,PFatalError from VDSP None" "0,1" newline bitfld.long 0x0 9. "VDSP_ERRORCORRECTED,ErrorCorrected from VDSP None" "0,1" newline bitfld.long 0x0 8. "DP3_DP_CH_UNDERRUN,dp_ch_underrun from DP3 None" "0,1" newline bitfld.long 0x0 7. "DP2_DP_CH_UNDERRUN,dp_ch_underrun from DP2 None" "0,1" newline bitfld.long 0x0 6. "DP1_DP_CH_UNDERRUN,dp_ch_underrun from DP1 None" "0,1" newline bitfld.long 0x0 5. "DC5_CRC32_IRQ,crc32_irq from DC5 None" "0,1" newline bitfld.long 0x0 4. "DC5_DC_CH_UNDERRUN,dc_ch_underrun from DC5 None" "0,1" newline bitfld.long 0x0 3. "DC4_CRC32_IRQ,crc32_irq from DC4 None" "0,1" newline bitfld.long 0x0 2. "DC4_DC_CH_UNDERRUN,dc_ch_underrun from DC4 None" "0,1" newline bitfld.long 0x0 1. "DC3_CRC32_IRQ,crc32_irq from DC3 None" "0,1" newline bitfld.long 0x0 0. "DC3_DC_CH_UNDERRUN,dc_ch_underrun from DC3 None" "0,1" repeat.end repeat 4. (list 0x28 0x32 0x3C 0x46 )(list 0x0 0x80 0x100 0x180 ) rgroup.long ($2+0x300)++0x3 line.long 0x0 "INT_ENABLE_$1,ipi_int_ce from CANFD6 Correctable error interrupt" bitfld.long 0x0 31. "CANFD6_IPI_INT_CE,ipi_int_ce from CANFD6 Correctable error interrupt" "0,1" newline bitfld.long 0x0 30. "CANFD5_IPI_INT_NCEFA,ipi_int_ncefa from CANFD5 Non correctable error int internal" "0,1" newline bitfld.long 0x0 29. "CANFD5_IPI_INT_NCEHA,ipi_int_nceha from CANFD5 Non correctable error int host" "0,1" newline bitfld.long 0x0 28. "CANFD5_IPI_INT_CE,ipi_int_ce from CANFD5 Correctable error interrupt" "0,1" newline bitfld.long 0x0 27. "CANFD4_IPI_INT_NCEFA,ipi_int_ncefa from CANFD4 Non correctable error int internal" "0,1" newline bitfld.long 0x0 26. "CANFD4_IPI_INT_NCEHA,ipi_int_nceha from CANFD4 Non correctable error int host" "0,1" newline bitfld.long 0x0 25. "CANFD4_IPI_INT_CE,ipi_int_ce from CANFD4 Correctable error interrupt" "0,1" newline bitfld.long 0x0 24. "CANFD3_IPI_INT_NCEFA,ipi_int_ncefa from CANFD3 Non correctable error int internal" "0,1" newline bitfld.long 0x0 23. "CANFD3_IPI_INT_NCEHA,ipi_int_nceha from CANFD3 Non correctable error int host" "0,1" newline bitfld.long 0x0 22. "CANFD3_IPI_INT_CE,ipi_int_ce from CANFD3 Correctable error interrupt" "0,1" newline bitfld.long 0x0 21. "CANFD2_IPI_INT_NCEFA,ipi_int_ncefa from CANFD2 Non correctable error int internal" "0,1" newline bitfld.long 0x0 20. "CANFD2_IPI_INT_NCEHA,ipi_int_nceha from CANFD2 Non correctable error int host" "0,1" newline bitfld.long 0x0 19. "CANFD2_IPI_INT_CE,ipi_int_ce from CANFD2 Correctable error interrupt" "0,1" newline bitfld.long 0x0 18. "CANFD1_IPI_INT_NCEFA,ipi_int_ncefa from CANFD1 Non correctable error int internal" "0,1" newline bitfld.long 0x0 17. "CANFD1_IPI_INT_NCEHA,ipi_int_nceha from CANFD1 Non correctable error int host" "0,1" newline bitfld.long 0x0 16. "CANFD1_IPI_INT_CE,ipi_int_ce from CANFD1 Correctable error interrupt" "0,1" newline bitfld.long 0x0 15. "ENET2_SBD_SFTY_UE_INTR_O,sbd_sfty_ue_intr_o from ENET2 None" "0,1" newline bitfld.long 0x0 14. "ENET2_SBD_SFTY_CE_INTR_O,sbd_sfty_ce_intr_o from ENET2 None" "0,1" newline bitfld.long 0x0 13. "ENET1_SBD_SFTY_UE_INTR_O,sbd_sfty_ue_intr_o from ENET1 None" "0,1" newline bitfld.long 0x0 12. "ENET1_SBD_SFTY_CE_INTR_O,sbd_sfty_ce_intr_o from ENET1 None" "0,1" newline bitfld.long 0x0 11. "ROMC2_MUL_ERR_INT,mul_err_int from ROMC2 None" "0,1" newline bitfld.long 0x0 10. "ROMC2_SIG_ERR_INT,sig_err_int from ROMC2 None" "0,1" newline bitfld.long 0x0 9. "ROMC1_MUL_ERR_INT,mul_err_int from ROMC1 None" "0,1" newline bitfld.long 0x0 8. "ROMC1_SIG_ERR_INT,sig_err_int from ROMC1 None" "0,1" newline bitfld.long 0x0 7. "IRAM4_MUL_ERR_INT,mul_err_int from IRAM4 None" "0,1" newline bitfld.long 0x0 6. "IRAM4_SIG_ERR_INT,sig_err_int from IRAM4 None" "0,1" newline bitfld.long 0x0 5. "IRAM3_MUL_ERR_INT,mul_err_int from IRAM3 None" "0,1" newline bitfld.long 0x0 4. "IRAM3_SIG_ERR_INT,sig_err_int from IRAM3 None" "0,1" newline bitfld.long 0x0 3. "IRAM2_MUL_ERR_INT,mul_err_int from IRAM2 None" "0,1" newline bitfld.long 0x0 2. "IRAM2_SIG_ERR_INT,sig_err_int from IRAM2 None" "0,1" newline bitfld.long 0x0 1. "IRAM1_MUL_ERR_INT,mul_err_int from IRAM1 None" "0,1" newline bitfld.long 0x0 0. "IRAM1_SIG_ERR_INT,sig_err_int from IRAM1 None" "0,1" repeat.end repeat 4. (list 0x29 0x33 0x3D 0x47 )(list 0x0 0x80 0x100 0x180 ) rgroup.long ($2+0x304)++0x3 line.long 0x0 "INT_ENABLE_$1,s_14_mainSglDataEccErr from NOC_SEC None" bitfld.long 0x0 31. "NOC_SEC_S_14_MAINSGLDATAECCERR,s_14_mainSglDataEccErr from NOC_SEC None" "0,1" newline bitfld.long 0x0 30. "NOC_SEC_S_13_MAINSGLDATAECCERR,s_13_mainSglDataEccErr from NOC_SEC None" "0,1" newline bitfld.long 0x0 29. "NOC_SEC_S_3_MAINSGLDATAECCERR,s_3_mainSglDataEccErr from NOC_SEC None" "0,1" newline bitfld.long 0x0 28. "NOC_SEC_S_2_MAINSGLDATAECCERR,s_2_mainSglDataEccErr from NOC_SEC None" "0,1" newline bitfld.long 0x0 27. "NOC_SEC_S_1_MAINSGLECCERR,s_1_mainSglEccErr from NOC_SEC None" "0,1" newline bitfld.long 0x0 26. "NOC_SEC_S_0_MAINSGLECCERR,s_0_mainSglEccErr from NOC_SEC None" "0,1" newline bitfld.long 0x0 25. "NOC_SEC_M_9_I_MAININITIATOR_TIMEOUT_FAULT,m_9_I_mainInitiator_Timeout_Fault from NOC_SEC None" "0,1" newline bitfld.long 0x0 24. "NOC_SEC_M_8_I_MAININITIATOR_TIMEOUT_FAULT,m_8_I_mainInitiator_Timeout_Fault from NOC_SEC None" "0,1" newline bitfld.long 0x0 23. "NOC_SEC_M_7_I_MAININITIATOR_TIMEOUT_FAULT,m_7_I_mainInitiator_Timeout_Fault from NOC_SEC None" "0,1" newline bitfld.long 0x0 22. "NOC_SEC_M_6_I_MAININITIATOR_TIMEOUT_FAULT,m_6_I_mainInitiator_Timeout_Fault from NOC_SEC None" "0,1" newline bitfld.long 0x0 21. "NOC_SEC_M_5_I_MAININITIATOR_TIMEOUT_FAULT,m_5_I_mainInitiator_Timeout_Fault from NOC_SEC None" "0,1" newline bitfld.long 0x0 20. "NOC_SEC_M_5_MAINSGLDATAECCERR,m_5_mainSglDataEccErr from NOC_SEC None" "0,1" newline bitfld.long 0x0 19. "NOC_SEC_M_5_MAINSGLAWADDRECCERR,m_5_mainSglAwAddrEccErr from NOC_SEC None" "0,1" newline bitfld.long 0x0 18. "NOC_SEC_M_5_MAINSGLARADDRECCERR,m_5_mainSglArAddrEccErr from NOC_SEC None" "0,1" newline bitfld.long 0x0 17. "NOC_SEC_M_3_I_MAININITIATOR_TIMEOUT_FAULT,m_3_I_mainInitiator_Timeout_Fault from NOC_SEC None" "0,1" newline bitfld.long 0x0 16. "NOC_SEC_M_3_MAINSGLECCERR,m_3_mainSglEccErr from NOC_SEC Actually m_1_mainSglEccErr" "0,1" newline bitfld.long 0x0 15. "NOC_SEC_M_2_I_MAININITIATOR_TIMEOUT_FAULT,m_2_I_mainInitiator_Timeout_Fault from NOC_SEC None" "0,1" newline bitfld.long 0x0 14. "NOC_SEC_M_2_MAINSGLECCERR,m_2_mainSglEccErr from NOC_SEC Actually m_0_mainSglEccErr" "0,1" newline bitfld.long 0x0 13. "NOC_SEC_M_1_I_MAININITIATOR_TIMEOUT_FAULT,m_1_I_mainInitiator_Timeout_Fault from NOC_SEC None" "0,1" newline bitfld.long 0x0 12. "NOC_SEC_M_1_MAINSGLECCERR,m_1_mainSglEccErr from NOC_SEC Actually m_3_mainSglEccErr" "0,1" newline bitfld.long 0x0 11. "NOC_SEC_M_0_I_MAININITIATOR_TIMEOUT_FAULT,m_0_I_mainInitiator_Timeout_Fault from NOC_SEC None" "0,1" newline bitfld.long 0x0 10. "NOC_SEC_M_0_MAINSGLECCERR,m_0_mainSglEccErr from NOC_SEC Actually m_2_mainSglEccErr" "0,1" newline bitfld.long 0x0 9. "NOC_SEC_PD_SEC_MAINMISSIONINT,PD_SEC_mainMissionInt from NOC_SEC None OR ~PD_SEC_mainMissionIntBar from NOC_SEC None" "0,1" newline bitfld.long 0x0 8. "NOC_SEC_PD_SEC_MAINLATENTINT,PD_SEC_mainLatentInt from NOC_SEC None OR ~PD_SEC_mainLatentIntBar from NOC_SEC None" "0,1" newline bitfld.long 0x0 7. "CANFD8_IPI_INT_NCEFA,ipi_int_ncefa from CANFD8 Non correctable error int internal" "0,1" newline bitfld.long 0x0 6. "CANFD8_IPI_INT_NCEHA,ipi_int_nceha from CANFD8 Non correctable error int host" "0,1" newline bitfld.long 0x0 5. "CANFD8_IPI_INT_CE,ipi_int_ce from CANFD8 Correctable error interrupt" "0,1" newline bitfld.long 0x0 4. "CANFD7_IPI_INT_NCEFA,ipi_int_ncefa from CANFD7 Non correctable error int internal" "0,1" newline bitfld.long 0x0 3. "CANFD7_IPI_INT_NCEHA,ipi_int_nceha from CANFD7 Non correctable error int host" "0,1" newline bitfld.long 0x0 2. "CANFD7_IPI_INT_CE,ipi_int_ce from CANFD7 Correctable error interrupt" "0,1" newline bitfld.long 0x0 1. "CANFD6_IPI_INT_NCEFA,ipi_int_ncefa from CANFD6 Non correctable error int internal" "0,1" newline bitfld.long 0x0 0. "CANFD6_IPI_INT_NCEHA,ipi_int_nceha from CANFD6 Non correctable error int host" "0,1" repeat.end repeat 4. (list 0x2E 0x38 0x42 0x4C )(list 0x0 0x80 0x100 0x180 ) rgroup.long ($2+0x318)++0x3 line.long 0x0 "INT_ENABLE_$1,ppxfatal0[1] from CR5_SEC data errors and any parity errors on the AXI Peripheral Port" bitfld.long 0x0 31. "CR5_SEC_PPXFATAL0[1],ppxfatal0[1] from CR5_SEC data errors and any parity errors on the AXI Peripheral Port" "0,1" newline bitfld.long 0x0 30. "CR5_SEC_PPXFATAL0[0],ppxfatal0[0] from CR5_SEC data errors and any parity errors on the AXI Peripheral Port" "0,1" newline bitfld.long 0x0 29. "CR5_SEC_AXISFATAL0[4],axisfatal0[4] from CR5_SEC data errors and any parity errors on the AXI slave" "0,1" newline bitfld.long 0x0 28. "CR5_SEC_AXISFATAL0[3],axisfatal0[3] from CR5_SEC data errors and any parity errors on the AXI slave" "0,1" newline bitfld.long 0x0 27. "CR5_SEC_AXISFATAL0[2],axisfatal0[2] from CR5_SEC data errors and any parity errors on the AXI slave" "0,1" newline bitfld.long 0x0 26. "CR5_SEC_AXISFATAL0[1],axisfatal0[1] from CR5_SEC data errors and any parity errors on the AXI slave" "0,1" newline bitfld.long 0x0 25. "CR5_SEC_AXISFATAL0[0],axisfatal0[0] from CR5_SEC data errors and any parity errors on the AXI slave" "0,1" newline bitfld.long 0x0 24. "CR5_SEC_AXIMFATAL0[4],aximfatal0[4] from CR5_SEC data errors and any parity errors on the AXI master" "0,1" newline bitfld.long 0x0 23. "CR5_SEC_AXIMFATAL0[3],aximfatal0[3] from CR5_SEC data errors and any parity errors on the AXI master" "0,1" newline bitfld.long 0x0 22. "CR5_SEC_AXIMFATAL0[2],aximfatal0[2] from CR5_SEC data errors and any parity errors on the AXI master" "0,1" newline bitfld.long 0x0 21. "CR5_SEC_AXIMFATAL0[1],aximfatal0[1] from CR5_SEC data errors and any parity errors on the AXI master" "0,1" newline bitfld.long 0x0 20. "CR5_SEC_AXIMFATAL0[0],aximfatal0[0] from CR5_SEC data errors and any parity errors on the AXI master" "0,1" newline bitfld.long 0x0 19. "CR5_SEC_PPHCORR0,pphcorr0 from CR5_SEC data errors on reads by the AHB Peripheral Port" "0,1" newline bitfld.long 0x0 18. "CR5_SEC_PPXCORR0,ppxcorr0 from CR5_SEC data errors on reads by the AXI Peripheral Port" "0,1" newline bitfld.long 0x0 17. "CR5_SEC_AXISCORR0,axiscorr0 from CR5_SEC data errors on writes to the AXI Slave" "0,1" newline bitfld.long 0x0 16. "CR5_SEC_AXIMCORR0,aximcorr0 from CR5_SEC data errors on reads by the AXI Master" "0,1" newline bitfld.long 0x0 15. "CR5_SAF_DCCMOUT2[0],dccmout2[0] from CR5_SAF LockStep compare fail" "0,1" newline bitfld.long 0x0 14. "CR5_SAF_DCCMOUT[0],dccmout[0] from CR5_SAF LockStep compare fail" "0,1" newline bitfld.long 0x0 13. "CR5_SAF_PPXFATAL0[4],ppxfatal0[4] from CR5_SAF data errors and any parity errors on the AXI Peripheral Port" "0,1" newline bitfld.long 0x0 12. "CR5_SAF_PPXFATAL0[3],ppxfatal0[3] from CR5_SAF data errors and any parity errors on the AXI Peripheral Port" "0,1" newline bitfld.long 0x0 11. "CR5_SAF_PPXFATAL0[2],ppxfatal0[2] from CR5_SAF data errors and any parity errors on the AXI Peripheral Port" "0,1" newline bitfld.long 0x0 10. "CR5_SAF_PPXFATAL0[1],ppxfatal0[1] from CR5_SAF data errors and any parity errors on the AXI Peripheral Port" "0,1" newline bitfld.long 0x0 9. "CR5_SAF_PPXFATAL0[0],ppxfatal0[0] from CR5_SAF data errors and any parity errors on the AXI Peripheral Port" "0,1" newline bitfld.long 0x0 8. "CR5_SAF_AXISFATAL0[4],axisfatal0[4] from CR5_SAF data errors and any parity errors on the AXI slave" "0,1" newline bitfld.long 0x0 7. "CR5_SAF_AXISFATAL0[3],axisfatal0[3] from CR5_SAF data errors and any parity errors on the AXI slave" "0,1" newline bitfld.long 0x0 6. "CR5_SAF_AXISFATAL0[2],axisfatal0[2] from CR5_SAF data errors and any parity errors on the AXI slave" "0,1" newline bitfld.long 0x0 5. "CR5_SAF_AXISFATAL0[1],axisfatal0[1] from CR5_SAF data errors and any parity errors on the AXI slave" "0,1" newline bitfld.long 0x0 4. "CR5_SAF_AXISFATAL0[0],axisfatal0[0] from CR5_SAF data errors and any parity errors on the AXI slave" "0,1" newline bitfld.long 0x0 3. "CR5_SAF_AXIMFATAL0[4],aximfatal0[4] from CR5_SAF data errors and any parity errors on the AXI master" "0,1" newline bitfld.long 0x0 2. "CR5_SAF_AXIMFATAL0[3],aximfatal0[3] from CR5_SAF data errors and any parity errors on the AXI master" "0,1" newline bitfld.long 0x0 1. "CR5_SAF_AXIMFATAL0[2],aximfatal0[2] from CR5_SAF data errors and any parity errors on the AXI master" "0,1" newline bitfld.long 0x0 0. "CR5_SAF_AXIMFATAL0[1],aximfatal0[1] from CR5_SAF data errors and any parity errors on the AXI master" "0,1" repeat.end repeat 4. (list 0x2F 0x39 0x43 0x4D )(list 0x0 0x80 0x100 0x180 ) rgroup.long ($2+0x31C)++0x3 line.long 0x0 "INT_ENABLE_$1,irq from REMAP_CR5_MP_AR Remap Address field check error" bitfld.long 0x0 31. "REMAP_CR5_MP_AR_IRQ,irq from REMAP_CR5_MP_AR Remap Address field check error" "0,1" newline bitfld.long 0x0 30. "REMAP_CR5_MP_AW_IRQ,irq from REMAP_CR5_MP_AW Remap Address field check error" "0,1" newline bitfld.long 0x0 29. "REMAP_CR5_SEC_AR_IRQ,irq from REMAP_CR5_SEC_AR Remap Address field check error" "0,1" newline bitfld.long 0x0 28. "REMAP_CR5_SEC_AW_IRQ,irq from REMAP_CR5_SEC_AW Remap Address field check error" "0,1" newline bitfld.long 0x0 27. "REMAP_CR5_SAF_AR_IRQ,irq from REMAP_CR5_SAF_AR Remap Address field check error" "0,1" newline bitfld.long 0x0 26. "REMAP_CR5_SAF_AW_IRQ,irq from REMAP_CR5_SAF_AW Remap Address field check error" "0,1" newline bitfld.long 0x0 25. "CR5_MP_DCCMOUT2[0],dccmout2[0] from CR5_MP LockStep compare fail" "0,1" newline bitfld.long 0x0 24. "CR5_MP_DCCMOUT[0],dccmout[0] from CR5_MP LockStep compare fail" "0,1" newline bitfld.long 0x0 23. "CR5_MP_PPXFATAL0[4],ppxfatal0[4] from CR5_MP data errors and any parity errors on the AXI Peripheral Port" "0,1" newline bitfld.long 0x0 22. "CR5_MP_PPXFATAL0[3],ppxfatal0[3] from CR5_MP data errors and any parity errors on the AXI Peripheral Port" "0,1" newline bitfld.long 0x0 21. "CR5_MP_PPXFATAL0[2],ppxfatal0[2] from CR5_MP data errors and any parity errors on the AXI Peripheral Port" "0,1" newline bitfld.long 0x0 20. "CR5_MP_PPXFATAL0[1],ppxfatal0[1] from CR5_MP data errors and any parity errors on the AXI Peripheral Port" "0,1" newline bitfld.long 0x0 19. "CR5_MP_PPXFATAL0[0],ppxfatal0[0] from CR5_MP data errors and any parity errors on the AXI Peripheral Port" "0,1" newline bitfld.long 0x0 18. "CR5_MP_AXISFATAL0[4],axisfatal0[4] from CR5_MP data errors and any parity errors on the AXI slave" "0,1" newline bitfld.long 0x0 17. "CR5_MP_AXISFATAL0[3],axisfatal0[3] from CR5_MP data errors and any parity errors on the AXI slave" "0,1" newline bitfld.long 0x0 16. "CR5_MP_AXISFATAL0[2],axisfatal0[2] from CR5_MP data errors and any parity errors on the AXI slave" "0,1" newline bitfld.long 0x0 15. "CR5_MP_AXISFATAL0[1],axisfatal0[1] from CR5_MP data errors and any parity errors on the AXI slave" "0,1" newline bitfld.long 0x0 14. "CR5_MP_AXISFATAL0[0],axisfatal0[0] from CR5_MP data errors and any parity errors on the AXI slave" "0,1" newline bitfld.long 0x0 13. "CR5_MP_AXIMFATAL0[4],aximfatal0[4] from CR5_MP data errors and any parity errors on the AXI master" "0,1" newline bitfld.long 0x0 12. "CR5_MP_AXIMFATAL0[3],aximfatal0[3] from CR5_MP data errors and any parity errors on the AXI master" "0,1" newline bitfld.long 0x0 11. "CR5_MP_AXIMFATAL0[2],aximfatal0[2] from CR5_MP data errors and any parity errors on the AXI master" "0,1" newline bitfld.long 0x0 10. "CR5_MP_AXIMFATAL0[1],aximfatal0[1] from CR5_MP data errors and any parity errors on the AXI master" "0,1" newline bitfld.long 0x0 9. "CR5_MP_AXIMFATAL0[0],aximfatal0[0] from CR5_MP data errors and any parity errors on the AXI master" "0,1" newline bitfld.long 0x0 8. "RC_RTC_RTC_32K_NG_INT,rtc_32k_ng_int from RC_RTC RC or XTAL 32K clock is lost" "0,1" newline bitfld.long 0x0 7. "CR5_MP_PPXCORR0,ppxcorr0 from CR5_MP data errors on reads by the AXI Peripheral Port" "0,1" newline bitfld.long 0x0 6. "CR5_MP_AXISCORR0,axiscorr0 from CR5_MP data errors on writes to the AXI Slave" "0,1" newline bitfld.long 0x0 5. "CR5_MP_AXIMCORR0,aximcorr0 from CR5_MP data errors on reads by the AXI Master" "0,1" newline bitfld.long 0x0 4. "CR5_SEC_DCCMOUT2[0],dccmout2[0] from CR5_SEC LockStep compare fail" "0,1" newline bitfld.long 0x0 3. "CR5_SEC_DCCMOUT[0],dccmout[0] from CR5_SEC LockStep compare fail" "0,1" newline bitfld.long 0x0 2. "CR5_SEC_PPXFATAL0[4],ppxfatal0[4] from CR5_SEC data errors and any parity errors on the AXI Peripheral Port" "0,1" newline bitfld.long 0x0 1. "CR5_SEC_PPXFATAL0[3],ppxfatal0[3] from CR5_SEC data errors and any parity errors on the AXI Peripheral Port" "0,1" newline bitfld.long 0x0 0. "CR5_SEC_PPXFATAL0[2],ppxfatal0[2] from CR5_SEC data errors and any parity errors on the AXI Peripheral Port" "0,1" repeat.end repeat 4. (list 0x30 0x3A 0x44 0x4E )(list 0x0 0x80 0x100 0x180 ) rgroup.long ($2+0x320)++0x3 line.long 0x0 "INT_ENABLE_$1,ap_power_lat from PWR_LAT_SAF AP domain power fail" bitfld.long 0x0 31. "PWR_LAT_SAF_AP_POWER_LAT,ap_power_lat from PWR_LAT_SAF AP domain power fail" "0,1" newline bitfld.long 0x0 30. "PWR_LAT_SAF_RTC_POWER_LAT,rtc_power_lat from PWR_LAT_SAF RTC domain power fail" "0,1" newline bitfld.long 0x0 29. "XTAL_AP_TO_LOST_INT,to_lost_int from XTAL_AP xtal_saf lost" "0,1" newline bitfld.long 0x0 28. "XTAL_AP_TO_UNST_INT,to_unst_int from XTAL_AP xtal_saf un-stable" "0,1" newline bitfld.long 0x0 27. "XTAL_AP_FR_UNST_INT,fr_unst_int from XTAL_AP xtal_ap un-stable" "0,1" newline bitfld.long 0x0 26. "XTAL_SAF_TO_LOST_INT,to_lost_int from XTAL_SAF xtal_ap lost" "0,1" newline bitfld.long 0x0 25. "XTAL_SAF_TO_UNST_INT,to_unst_int from XTAL_SAF xtal_ap un-stable" "0,1" newline bitfld.long 0x0 24. "XTAL_SAF_FR_UNST_INT,fr_unst_int from XTAL_SAF xtal_saf un-stable" "0,1" newline bitfld.long 0x0 23. "RC_24M_SOC_XTAL_LOST_INT,soc_xtal_lost_int from RC_24M soc xtal lost" "0,1" newline bitfld.long 0x0 22. "RC_24M_SOC_XTAL_UNST_INT,soc_xtal_unst_int from RC_24M soc xtal un-stable" "0,1" newline bitfld.long 0x0 21. "RC_24M_SOC_OSC_UNST_INT,soc_osc_unst_int from RC_24M osc un-stable according to soc xtal" "0,1" newline bitfld.long 0x0 20. "RC_24M_SAF_XTAL_LOST_INT,saf_xtal_lost_int from RC_24M safety xtal lost" "0,1" newline bitfld.long 0x0 19. "RC_24M_SAF_XTAL_UNST_INT,saf_xtal_unst_int from RC_24M safety xtal un-stable" "0,1" newline bitfld.long 0x0 18. "RC_24M_SAF_OSC_UNST_INT,saf_osc_unst_int from RC_24M osc un-stable according to saf xtal" "0,1" newline bitfld.long 0x0 17. "CPU2_~NERRIRQ[1],~nERRIRQ[1] from CPU2 Error indicator for an ECC error that causes potential data corruption or loss of coherency in the Core0 L1 or L2 RAMs" "0,1" newline bitfld.long 0x0 16. "CPU2_~NERRIRQ[0],~nERRIRQ[0] from CPU2 Error indicator for an ECC error that causes potential data corruption or loss of coherency in the L3 RAMs" "0,1" newline bitfld.long 0x0 15. "CPU2_~NFAULTIRQ[1],~nFAULTIRQ[1] from CPU2 Fault indicator for a detected 1-bit or 2-bit ECC or Parity error in the Core0 L1 or L2 RAMs" "?,bit or 2-bit ECC or Parity error in the Core0 L1.." newline bitfld.long 0x0 14. "CPU2_~NFAULTIRQ[0],~nFAULTIRQ[0] from CPU2 Fault indicator for a detected 1-bit or 2-bit ECC or Parity error in the L3 RAMs" "?,bit or 2-bit ECC or Parity error in the L3 RAMs" newline bitfld.long 0x0 13. "CPU1_~NERRIRQ[6],~nERRIRQ[6] from CPU1 Error indicator for an ECC error that causes potential data corruption or loss of coherency in the Core3 L1 or L2 RAMs" "0,1" newline bitfld.long 0x0 12. "CPU1_~NERRIRQ[5],~nERRIRQ[5] from CPU1 Error indicator for an ECC error that causes potential data corruption or loss of coherency in the Core2 L1 or L2 RAMs" "0,1" newline bitfld.long 0x0 11. "CPU1_~NERRIRQ[4],~nERRIRQ[4] from CPU1 Error indicator for an ECC error that causes potential data corruption or loss of coherency in the Core3 L1 or L2 RAMs" "0,1" newline bitfld.long 0x0 10. "CPU1_~NERRIRQ[3],~nERRIRQ[3] from CPU1 Error indicator for an ECC error that causes potential data corruption or loss of coherency in the Core2 L1 or L2 RAMs" "0,1" newline bitfld.long 0x0 9. "CPU1_~NERRIRQ[2],~nERRIRQ[2] from CPU1 Error indicator for an ECC error that causes potential data corruption or loss of coherency in the Core1 L1 or L2 RAMs" "0,1" newline bitfld.long 0x0 8. "CPU1_~NERRIRQ[1],~nERRIRQ[1] from CPU1 Error indicator for an ECC error that causes potential data corruption or loss of coherency in the Core0 L1 or L2 RAMs" "0,1" newline bitfld.long 0x0 7. "CPU1_~NERRIRQ[0],~nERRIRQ[0] from CPU1 Error indicator for an ECC error that causes potential data corruption or loss of coherency in the L3 RAMs" "0,1" newline bitfld.long 0x0 6. "CPU1_~NFAULTIRQ[6],~nFAULTIRQ[6] from CPU1 Fault indicator for a detected 1-bit or 2-bit ECC or Parity error in the Core3 L1 or L2 RAMs" "?,bit or 2-bit ECC or Parity error in the Core3 L1.." newline bitfld.long 0x0 5. "CPU1_~NFAULTIRQ[5],~nFAULTIRQ[5] from CPU1 Fault indicator for a detected 1-bit or 2-bit ECC or Parity error in the Core2 L1 or L2 RAMs" "?,bit or 2-bit ECC or Parity error in the Core2 L1.." newline bitfld.long 0x0 4. "CPU1_~NFAULTIRQ[4],~nFAULTIRQ[4] from CPU1 Fault indicator for a detected 1-bit or 2-bit ECC or Parity error in the Core3 L1 or L2 RAMs" "?,bit or 2-bit ECC or Parity error in the Core3 L1.." newline bitfld.long 0x0 3. "CPU1_~NFAULTIRQ[3],~nFAULTIRQ[3] from CPU1 Fault indicator for a detected 1-bit or 2-bit ECC or Parity error in the Core2 L1 or L2 RAMs" "?,bit or 2-bit ECC or Parity error in the Core2 L1.." newline bitfld.long 0x0 2. "CPU1_~NFAULTIRQ[2],~nFAULTIRQ[2] from CPU1 Fault indicator for a detected 1-bit or 2-bit ECC or Parity error in the Core1 L1 or L2 RAMs" "?,bit or 2-bit ECC or Parity error in the Core1 L1.." newline bitfld.long 0x0 1. "CPU1_~NFAULTIRQ[1],~nFAULTIRQ[1] from CPU1 Fault indicator for a detected 1-bit or 2-bit ECC or Parity error in the Core0 L1 or L2 RAMs" "?,bit or 2-bit ECC or Parity error in the Core0 L1.." newline bitfld.long 0x0 0. "CPU1_~NFAULTIRQ[0],~nFAULTIRQ[0] from CPU1 Fault indicator for a detected 1-bit or 2-bit ECC or Parity error in the L3 RAMs" "?,bit or 2-bit ECC or Parity error in the L3 RAMs" repeat.end repeat 4. (list 0x31 0x3B 0x45 0x4F )(list 0x0 0x80 0x100 0x180 ) rgroup.long ($2+0x324)++0x3 line.long 0x0 "INT_ENABLE_$1,pvt_int_1 from PVT_SNS_SAF None" bitfld.long 0x0 30. "PVT_SNS_SAF_PVT_INT_1,pvt_int_1 from PVT_SNS_SAF None" "0,1" newline bitfld.long 0x0 29. "PVT_SNS_SAF_PVT_INT_0,pvt_int_0 from PVT_SNS_SAF None" "0,1" newline bitfld.long 0x0 28. "PVT_SNS_SEC_PVT_INT_1,pvt_int_1 from PVT_SNS_SEC None" "0,1" newline bitfld.long 0x0 27. "PVT_SNS_SEC_PVT_INT_0,pvt_int_0 from PVT_SNS_SEC None" "0,1" newline bitfld.long 0x0 26. "WDT8_ILL_SEQ_REFR_INT,ill_seq_refr_int from WDT8 None" "0,1" newline bitfld.long 0x0 25. "WDT8_ILL_WIN_REFR_INT,ill_win_refr_int from WDT8 None" "0,1" newline bitfld.long 0x0 24. "WDT8_OVFLOW_INT,ovflow_int from WDT8 None" "0,1" newline bitfld.long 0x0 23. "WDT7_ILL_SEQ_REFR_INT,ill_seq_refr_int from WDT7 None" "0,1" newline bitfld.long 0x0 22. "WDT7_ILL_WIN_REFR_INT,ill_win_refr_int from WDT7 None" "0,1" newline bitfld.long 0x0 21. "WDT7_OVFLOW_INT,ovflow_int from WDT7 None" "0,1" newline bitfld.long 0x0 20. "WDT6_ILL_SEQ_REFR_INT,ill_seq_refr_int from WDT6 None" "0,1" newline bitfld.long 0x0 19. "WDT6_ILL_WIN_REFR_INT,ill_win_refr_int from WDT6 None" "0,1" newline bitfld.long 0x0 18. "WDT6_OVFLOW_INT,ovflow_int from WDT6 None" "0,1" newline bitfld.long 0x0 17. "WDT5_ILL_SEQ_REFR_INT,ill_seq_refr_int from WDT5 None" "0,1" newline bitfld.long 0x0 16. "WDT5_ILL_WIN_REFR_INT,ill_win_refr_int from WDT5 None" "0,1" newline bitfld.long 0x0 15. "WDT5_OVFLOW_INT,ovflow_int from WDT5 None" "0,1" newline bitfld.long 0x0 14. "WDT4_ILL_SEQ_REFR_INT,ill_seq_refr_int from WDT4 None" "0,1" newline bitfld.long 0x0 13. "WDT4_ILL_WIN_REFR_INT,ill_win_refr_int from WDT4 None" "0,1" newline bitfld.long 0x0 12. "WDT4_OVFLOW_INT,ovflow_int from WDT4 None" "0,1" newline bitfld.long 0x0 11. "WDT3_ILL_SEQ_REFR_INT,ill_seq_refr_int from WDT3 None" "0,1" newline bitfld.long 0x0 10. "WDT3_ILL_WIN_REFR_INT,ill_win_refr_int from WDT3 None" "0,1" newline bitfld.long 0x0 9. "WDT3_OVFLOW_INT,ovflow_int from WDT3 None" "0,1" newline bitfld.long 0x0 8. "WDT2_ILL_SEQ_REFR_INT,ill_seq_refr_int from WDT2 None" "0,1" newline bitfld.long 0x0 7. "WDT2_ILL_WIN_REFR_INT,ill_win_refr_int from WDT2 None" "0,1" newline bitfld.long 0x0 6. "WDT2_OVFLOW_INT,ovflow_int from WDT2 None" "0,1" newline bitfld.long 0x0 5. "WDT1_ILL_SEQ_REFR_INT,ill_seq_refr_int from WDT1 None" "0,1" newline bitfld.long 0x0 4. "WDT1_ILL_WIN_REFR_INT,ill_win_refr_int from WDT1 None" "0,1" newline bitfld.long 0x0 3. "WDT1_OVFLOW_INT,ovflow_int from WDT1 None" "0,1" newline bitfld.long 0x0 2. "PWR_LAT_RTC_AP_POWER_LAT,ap_power_lat from PWR_LAT_RTC AP domain power fail" "0,1" newline bitfld.long 0x0 1. "PWR_LAT_RTC_SAF_POWER_LAT,saf_power_lat from PWR_LAT_RTC SAF domain power fail" "0,1" newline bitfld.long 0x0 0. "PWR_LAT_SAF_SAF_POWER_LAT,saf_power_lat from PWR_LAT_SAF SAF power fail" "0,1" repeat.end repeat 6. (list 0x0 0x1 0x2 0x3 0x4 0x5 )(list 0x0 0x4 0x8 0xC 0x10 0x14 ) group.long ($2+0x500)++0x3 line.long 0x0 "TGT_VALUE$1,target value" hexmask.long 0x0 0.--31. 1. "TGT_VALUE0,monitor target value" repeat.end repeat 6. (list 0x0 0x1 0x2 0x3 0x4 0x5 )(list 0x0 0x4 0x8 0xC 0x10 0x14 ) group.long ($2+0x580)++0x3 line.long 0x0 "SIG_MON_ENABLE$1,signal monitor enable" hexmask.long 0x0 0.--31. 1. "SIG_MON_ENABLE0,monitor enable" repeat.end tree.end tree "AB1 (Address Block of sem)" group.long 0x0++0xB line.long 0x0 "SEM_COMMON_SET,SEM common settings" hexmask.long.byte 0x0 24.--31. 1. "CMP_ENABLE,compare output enable bits for int0-7" bitfld.long 0x0 23. "SIG_MON_GLB_EN,signal monitor global enable" "0,1" bitfld.long 0x0 17. "EI_GLOBAL_EN_LOCK,Error Injection Global Enable Lock bit" "0,1" newline bitfld.long 0x0 16. "EI_GLOBAL_EN,Error Injection Global Enable" "0,1" hexmask.long.byte 0x0 12.--15. 1. "ERROR_DIV,error divider ratio for waveform A" bitfld.long 0x0 11. "ERROR_WAVE_SEL,waveform A/B selection for normal/recoverable error" "0,1" newline bitfld.long 0x0 10. "FATAL_HIGH_LOW,fatal error High or Low selection" "0,1" bitfld.long 0x0 8.--9. "SEM_INT_DC4_SEL,SEM_INT DC4 selection" "0,1,2,3" bitfld.long 0x0 6.--7. "SEM_INT_DC3_SEL,SEM_INT DC3 selection" "0,1,2,3" newline bitfld.long 0x0 4.--5. "SEM_INT_DC2_SEL,SEM_INT DC2 selection" "0,1,2,3" bitfld.long 0x0 2.--3. "SEM_INT_DC1_SEL,SEM_INT DC1 selection" "0,1,2,3" bitfld.long 0x0 0.--1. "SEM_INT_DC0_SEL,SEM_INT DC0 selection" "0,1,2,3" line.long 0x4 "INT_TRIG,int0-7 trigger" hexmask.long.byte 0x4 0.--7. 1. "INT_TRIG,int0-int7 trigger" line.long 0x8 "INT_ENABLE_OVRD,int0-7 enable override" hexmask.long.byte 0x8 8.--15. 1. "INT_ENABLE_OVRD_VAL,int0-7 enable override value" hexmask.long.byte 0x8 0.--7. 1. "INT_ENABLE_OVRD_EN,int0-7 enable override enable" repeat 9. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 )(list 0x0 0x4 0x8 0xC 0x10 0x14 0x18 0x1C 0x20 ) rgroup.long ($2+0x80)++0x3 line.long 0x0 "INT_STATUS$1,Interrupt Status" bitfld.long 0x0 31. "CANFD6_IPI_INT_CE,ipi_int_ce from CANFD6 Correctable error interrupt" "0,1" bitfld.long 0x0 30. "CANFD5_IPI_INT_NCEFA,ipi_int_ncefa from CANFD5 Non correctable error int internal" "0,1" bitfld.long 0x0 29. "CANFD5_IPI_INT_NCEHA,ipi_int_nceha from CANFD5 Non correctable error int host" "0,1" newline bitfld.long 0x0 28. "CANFD5_IPI_INT_CE,ipi_int_ce from CANFD5 Correctable error interrupt" "0,1" bitfld.long 0x0 27. "CANFD4_IPI_INT_NCEFA,ipi_int_ncefa from CANFD4 Non correctable error int internal" "0,1" bitfld.long 0x0 26. "CANFD4_IPI_INT_NCEHA,ipi_int_nceha from CANFD4 Non correctable error int host" "0,1" newline bitfld.long 0x0 25. "CANFD4_IPI_INT_CE,ipi_int_ce from CANFD4 Correctable error interrupt" "0,1" bitfld.long 0x0 24. "CANFD3_IPI_INT_NCEFA,ipi_int_ncefa from CANFD3 Non correctable error int internal" "0,1" bitfld.long 0x0 23. "CANFD3_IPI_INT_NCEHA,ipi_int_nceha from CANFD3 Non correctable error int host" "0,1" newline bitfld.long 0x0 22. "CANFD3_IPI_INT_CE,ipi_int_ce from CANFD3 Correctable error interrupt" "0,1" bitfld.long 0x0 21. "CANFD2_IPI_INT_NCEFA,ipi_int_ncefa from CANFD2 Non correctable error int internal" "0,1" bitfld.long 0x0 20. "CANFD2_IPI_INT_NCEHA,ipi_int_nceha from CANFD2 Non correctable error int host" "0,1" newline bitfld.long 0x0 19. "CANFD2_IPI_INT_CE,ipi_int_ce from CANFD2 Correctable error interrupt" "0,1" bitfld.long 0x0 18. "CANFD1_IPI_INT_NCEFA,ipi_int_ncefa from CANFD1 Non correctable error int internal" "0,1" bitfld.long 0x0 17. "CANFD1_IPI_INT_NCEHA,ipi_int_nceha from CANFD1 Non correctable error int host" "0,1" newline bitfld.long 0x0 16. "CANFD1_IPI_INT_CE,ipi_int_ce from CANFD1 Correctable error interrupt" "0,1" bitfld.long 0x0 15. "ENET2_SBD_SFTY_UE_INTR_O,sbd_sfty_ue_intr_o from ENET2" "0,1" bitfld.long 0x0 14. "ENET2_SBD_SFTY_CE_INTR_O,sbd_sfty_ce_intr_o from ENET2" "0,1" newline bitfld.long 0x0 13. "ENET1_SBD_SFTY_UE_INTR_O,sbd_sfty_ue_intr_o from ENET1" "0,1" bitfld.long 0x0 12. "ENET1_SBD_SFTY_CE_INTR_O,sbd_sfty_ce_intr_o from ENET1" "0,1" bitfld.long 0x0 11. "ROMC2_MUL_ERR_INT,mul_err_int from ROMC2" "0,1" newline bitfld.long 0x0 10. "ROMC2_SIG_ERR_INT,sig_err_int from ROMC2" "0,1" bitfld.long 0x0 9. "ROMC1_MUL_ERR_INT,mul_err_int from ROMC1" "0,1" bitfld.long 0x0 8. "ROMC1_SIG_ERR_INT,sig_err_int from ROMC1" "0,1" newline bitfld.long 0x0 7. "IRAM4_MUL_ERR_INT,mul_err_int from IRAM4" "0,1" bitfld.long 0x0 6. "IRAM4_SIG_ERR_INT,sig_err_int from IRAM4" "0,1" bitfld.long 0x0 5. "IRAM3_MUL_ERR_INT,mul_err_int from IRAM3" "0,1" newline bitfld.long 0x0 4. "IRAM3_SIG_ERR_INT,sig_err_int from IRAM3" "0,1" bitfld.long 0x0 3. "IRAM2_MUL_ERR_INT,mul_err_int from IRAM2" "0,1" bitfld.long 0x0 2. "IRAM2_SIG_ERR_INT,sig_err_int from IRAM2" "0,1" newline bitfld.long 0x0 1. "IRAM1_MUL_ERR_INT,mul_err_int from IRAM1" "0,1" bitfld.long 0x0 0. "IRAM1_SIG_ERR_INT,sig_err_int from IRAM1" "0,1" repeat.end rgroup.long 0xA4++0x3 line.long 0x0 "INT_STATUS9,Interrupt Status" bitfld.long 0x0 30. "PVT_SNS_SAF_PVT_INT_1,pvt_int_1 from PVT_SNS_SAF" "0,1" bitfld.long 0x0 29. "PVT_SNS_SAF_PVT_INT_0,pvt_int_0 from PVT_SNS_SAF" "0,1" bitfld.long 0x0 28. "PVT_SNS_SEC_PVT_INT_1,pvt_int_1 from PVT_SNS_SEC" "0,1" newline bitfld.long 0x0 27. "PVT_SNS_SEC_PVT_INT_0,pvt_int_0 from PVT_SNS_SEC" "0,1" bitfld.long 0x0 26. "WDT8_ILL_SEQ_REFR_INT,ill_seq_refr_int from WDT8" "0,1" bitfld.long 0x0 25. "WDT8_ILL_WIN_REFR_INT,ill_win_refr_int from WDT8" "0,1" newline bitfld.long 0x0 24. "WDT8_OVFLOW_INT,ovflow_int from WDT8" "0,1" bitfld.long 0x0 23. "WDT7_ILL_SEQ_REFR_INT,ill_seq_refr_int from WDT7" "0,1" bitfld.long 0x0 22. "WDT7_ILL_WIN_REFR_INT,ill_win_refr_int from WDT7" "0,1" newline bitfld.long 0x0 21. "WDT7_OVFLOW_INT,ovflow_int from WDT7" "0,1" bitfld.long 0x0 20. "WDT6_ILL_SEQ_REFR_INT,ill_seq_refr_int from WDT6" "0,1" bitfld.long 0x0 19. "WDT6_ILL_WIN_REFR_INT,ill_win_refr_int from WDT6" "0,1" newline bitfld.long 0x0 18. "WDT6_OVFLOW_INT,ovflow_int from WDT6" "0,1" bitfld.long 0x0 17. "WDT5_ILL_SEQ_REFR_INT,ill_seq_refr_int from WDT5" "0,1" bitfld.long 0x0 16. "WDT5_ILL_WIN_REFR_INT,ill_win_refr_int from WDT5" "0,1" newline bitfld.long 0x0 15. "WDT5_OVFLOW_INT,ovflow_int from WDT5" "0,1" bitfld.long 0x0 14. "WDT4_ILL_SEQ_REFR_INT,ill_seq_refr_int from WDT4" "0,1" bitfld.long 0x0 13. "WDT4_ILL_WIN_REFR_INT,ill_win_refr_int from WDT4" "0,1" newline bitfld.long 0x0 12. "WDT4_OVFLOW_INT,ovflow_int from WDT4" "0,1" bitfld.long 0x0 11. "WDT3_ILL_SEQ_REFR_INT,ill_seq_refr_int from WDT3" "0,1" bitfld.long 0x0 10. "WDT3_ILL_WIN_REFR_INT,ill_win_refr_int from WDT3" "0,1" newline bitfld.long 0x0 9. "WDT3_OVFLOW_INT,ovflow_int from WDT3" "0,1" bitfld.long 0x0 8. "WDT2_ILL_SEQ_REFR_INT,ill_seq_refr_int from WDT2" "0,1" bitfld.long 0x0 7. "WDT2_ILL_WIN_REFR_INT,ill_win_refr_int from WDT2" "0,1" newline bitfld.long 0x0 6. "WDT2_OVFLOW_INT,ovflow_int from WDT2" "0,1" bitfld.long 0x0 5. "WDT1_ILL_SEQ_REFR_INT,ill_seq_refr_int from WDT1" "0,1" bitfld.long 0x0 4. "WDT1_ILL_WIN_REFR_INT,ill_win_refr_int from WDT1" "0,1" newline bitfld.long 0x0 3. "WDT1_OVFLOW_INT,ovflow_int from WDT1" "0,1" bitfld.long 0x0 2. "PWR_LAT_RTC_AP_POWER_LAT,ap_power_lat from PWR_LAT_RTC AP domain power fail" "0,1" bitfld.long 0x0 1. "PWR_LAT_RTC_SAF_POWER_LAT,saf_power_lat from PWR_LAT_RTC SAF domain power fail" "0,1" newline bitfld.long 0x0 0. "PWR_LAT_SAF_SAF_POWER_LAT,saf_power_lat from PWR_LAT_SAF SAF power fail" "0,1" repeat 9. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 )(list 0x0 0x4 0x8 0xC 0x10 0x14 0x18 0x1C 0x20 ) group.long ($2+0x100)++0x3 line.long 0x0 "INT_ENABLE_$1,Interrupt Enable 0 for correctable error output to PIN" bitfld.long 0x0 31. "CANFD6_IPI_INT_CE,ipi_int_ce from CANFD6 Correctable error interrupt" "0,1" bitfld.long 0x0 30. "CANFD5_IPI_INT_NCEFA,ipi_int_ncefa from CANFD5 Non correctable error int internal" "0,1" bitfld.long 0x0 29. "CANFD5_IPI_INT_NCEHA,ipi_int_nceha from CANFD5 Non correctable error int host" "0,1" newline bitfld.long 0x0 28. "CANFD5_IPI_INT_CE,ipi_int_ce from CANFD5 Correctable error interrupt" "0,1" bitfld.long 0x0 27. "CANFD4_IPI_INT_NCEFA,ipi_int_ncefa from CANFD4 Non correctable error int internal" "0,1" bitfld.long 0x0 26. "CANFD4_IPI_INT_NCEHA,ipi_int_nceha from CANFD4 Non correctable error int host" "0,1" newline bitfld.long 0x0 25. "CANFD4_IPI_INT_CE,ipi_int_ce from CANFD4 Correctable error interrupt" "0,1" bitfld.long 0x0 24. "CANFD3_IPI_INT_NCEFA,ipi_int_ncefa from CANFD3 Non correctable error int internal" "0,1" bitfld.long 0x0 23. "CANFD3_IPI_INT_NCEHA,ipi_int_nceha from CANFD3 Non correctable error int host" "0,1" newline bitfld.long 0x0 22. "CANFD3_IPI_INT_CE,ipi_int_ce from CANFD3 Correctable error interrupt" "0,1" bitfld.long 0x0 21. "CANFD2_IPI_INT_NCEFA,ipi_int_ncefa from CANFD2 Non correctable error int internal" "0,1" bitfld.long 0x0 20. "CANFD2_IPI_INT_NCEHA,ipi_int_nceha from CANFD2 Non correctable error int host" "0,1" newline bitfld.long 0x0 19. "CANFD2_IPI_INT_CE,ipi_int_ce from CANFD2 Correctable error interrupt" "0,1" bitfld.long 0x0 18. "CANFD1_IPI_INT_NCEFA,ipi_int_ncefa from CANFD1 Non correctable error int internal" "0,1" bitfld.long 0x0 17. "CANFD1_IPI_INT_NCEHA,ipi_int_nceha from CANFD1 Non correctable error int host" "0,1" newline bitfld.long 0x0 16. "CANFD1_IPI_INT_CE,ipi_int_ce from CANFD1 Correctable error interrupt" "0,1" bitfld.long 0x0 15. "ENET2_SBD_SFTY_UE_INTR_O,sbd_sfty_ue_intr_o from ENET2" "0,1" bitfld.long 0x0 14. "ENET2_SBD_SFTY_CE_INTR_O,sbd_sfty_ce_intr_o from ENET2" "0,1" newline bitfld.long 0x0 13. "ENET1_SBD_SFTY_UE_INTR_O,sbd_sfty_ue_intr_o from ENET1" "0,1" bitfld.long 0x0 12. "ENET1_SBD_SFTY_CE_INTR_O,sbd_sfty_ce_intr_o from ENET1" "0,1" bitfld.long 0x0 11. "RWMC2_MUL_ERR_INT,mul_err_int from RWMC2" "0,1" newline bitfld.long 0x0 10. "RWMC2_SIG_ERR_INT,sig_err_int from RWMC2" "0,1" bitfld.long 0x0 9. "RWMC1_MUL_ERR_INT,mul_err_int from RWMC1" "0,1" bitfld.long 0x0 8. "RWMC1_SIG_ERR_INT,sig_err_int from RWMC1" "0,1" newline bitfld.long 0x0 7. "IRAM4_MUL_ERR_INT,mul_err_int from IRAM4" "0,1" bitfld.long 0x0 6. "IRAM4_SIG_ERR_INT,sig_err_int from IRAM4" "0,1" bitfld.long 0x0 5. "IRAM3_MUL_ERR_INT,mul_err_int from IRAM3" "0,1" newline bitfld.long 0x0 4. "IRAM3_SIG_ERR_INT,sig_err_int from IRAM3" "0,1" bitfld.long 0x0 3. "IRAM2_MUL_ERR_INT,mul_err_int from IRAM2" "0,1" bitfld.long 0x0 2. "IRAM2_SIG_ERR_INT,sig_err_int from IRAM2" "0,1" newline bitfld.long 0x0 1. "IRAM1_MUL_ERR_INT,mul_err_int from IRAM1" "0,1" bitfld.long 0x0 0. "IRAM1_SIG_ERR_INT,sig_err_int from IRAM1" "0,1" repeat.end group.long 0x124++0x3 line.long 0x0 "INT_ENABLE_09,Interrupt Enable 0 for correctable error output to PIN" bitfld.long 0x0 30. "PVT_SNS_SAF_PVT_INT_1,pvt_int_1 from PVT_SNS_SAF" "0,1" bitfld.long 0x0 29. "PVT_SNS_SAF_PVT_INT_0,pvt_int_0 from PVT_SNS_SAF" "0,1" bitfld.long 0x0 28. "PVT_SNS_SEC_PVT_INT_1,pvt_int_1 from PVT_SNS_SEC" "0,1" newline bitfld.long 0x0 27. "PVT_SNS_SEC_PVT_INT_0,pvt_int_0 from PVT_SNS_SEC" "0,1" bitfld.long 0x0 26. "WDT8_ILL_SEQ_REFR_INT,ill_seq_refr_int from WDT8" "0,1" bitfld.long 0x0 25. "WDT8_ILL_WIN_REFR_INT,ill_win_refr_int from WDT8" "0,1" newline bitfld.long 0x0 24. "WDT8_OVFLOW_INT,ovflow_int from WDT8" "0,1" bitfld.long 0x0 23. "WDT7_ILL_SEQ_REFR_INT,ill_seq_refr_int from WDT7" "0,1" bitfld.long 0x0 22. "WDT7_ILL_WIN_REFR_INT,ill_win_refr_int from WDT7" "0,1" newline bitfld.long 0x0 21. "WDT7_OVFLOW_INT,ovflow_int from WDT7" "0,1" bitfld.long 0x0 20. "WDT6_ILL_SEQ_REFR_INT,ill_seq_refr_int from WDT6" "0,1" bitfld.long 0x0 19. "WDT6_ILL_WIN_REFR_INT,ill_win_refr_int from WDT6" "0,1" newline bitfld.long 0x0 18. "WDT6_OVFLOW_INT,ovflow_int from WDT6" "0,1" bitfld.long 0x0 17. "WDT5_ILL_SEQ_REFR_INT,ill_seq_refr_int from WDT5" "0,1" bitfld.long 0x0 16. "WDT5_ILL_WIN_REFR_INT,ill_win_refr_int from WDT5" "0,1" newline bitfld.long 0x0 15. "WDT5_OVFLOW_INT,ovflow_int from WDT5" "0,1" bitfld.long 0x0 14. "WDT4_ILL_SEQ_REFR_INT,ill_seq_refr_int from WDT4" "0,1" bitfld.long 0x0 13. "WDT4_ILL_WIN_REFR_INT,ill_win_refr_int from WDT4" "0,1" newline bitfld.long 0x0 12. "WDT4_OVFLOW_INT,ovflow_int from WDT4" "0,1" bitfld.long 0x0 11. "WDT3_ILL_SEQ_REFR_INT,ill_seq_refr_int from WDT3" "0,1" bitfld.long 0x0 10. "WDT3_ILL_WIN_REFR_INT,ill_win_refr_int from WDT3" "0,1" newline bitfld.long 0x0 9. "WDT3_OVFLOW_INT,ovflow_int from WDT3" "0,1" bitfld.long 0x0 8. "WDT2_ILL_SEQ_REFR_INT,ill_seq_refr_int from WDT2" "0,1" bitfld.long 0x0 7. "WDT2_ILL_WIN_REFR_INT,ill_win_refr_int from WDT2" "0,1" newline bitfld.long 0x0 6. "WDT2_OVFLOW_INT,ovflow_int from WDT2" "0,1" bitfld.long 0x0 5. "WDT1_ILL_SEQ_REFR_INT,ill_seq_refr_int from WDT1" "0,1" bitfld.long 0x0 4. "WDT1_ILL_WIN_REFR_INT,ill_win_refr_int from WDT1" "0,1" newline bitfld.long 0x0 3. "WDT1_OVFLOW_INT,ovflow_int from WDT1" "0,1" bitfld.long 0x0 2. "PWR_LAT_RTC_AP_POWER_LAT,ap_power_lat from PWR_LAT_RTC AP domain power fail" "0,1" bitfld.long 0x0 1. "PWR_LAT_RTC_SAF_POWER_LAT,saf_power_lat from PWR_LAT_RTC SAF domain power fail" "0,1" newline bitfld.long 0x0 0. "PWR_LAT_SAF_SAF_POWER_LAT,saf_power_lat from PWR_LAT_SAF SAF power fail" "0,1" repeat 9. (list 0xA 0xB 0xC 0xD 0xE 0xF 0x10 0x11 0x12 )(list 0x0 0x4 0x8 0xC 0x10 0x14 0x18 0x1C 0x20 ) group.long ($2+0x180)++0x3 line.long 0x0 "INT_ENABLE_$1,Interrupt Enable 1 for fatal error output to PIN" bitfld.long 0x0 31. "CANFD6_IPI_INT_CE,ipi_int_ce from CANFD6 Correctable error interrupt" "0,1" bitfld.long 0x0 30. "CANFD5_IPI_INT_NCEFA,ipi_int_ncefa from CANFD5 Non correctable error int internal" "0,1" bitfld.long 0x0 29. "CANFD5_IPI_INT_NCEHA,ipi_int_nceha from CANFD5 Non correctable error int host" "0,1" newline bitfld.long 0x0 28. "CANFD5_IPI_INT_CE,ipi_int_ce from CANFD5 Correctable error interrupt" "0,1" bitfld.long 0x0 27. "CANFD4_IPI_INT_NCEFA,ipi_int_ncefa from CANFD4 Non correctable error int internal" "0,1" bitfld.long 0x0 26. "CANFD4_IPI_INT_NCEHA,ipi_int_nceha from CANFD4 Non correctable error int host" "0,1" newline bitfld.long 0x0 25. "CANFD4_IPI_INT_CE,ipi_int_ce from CANFD4 Correctable error interrupt" "0,1" bitfld.long 0x0 24. "CANFD3_IPI_INT_NCEFA,ipi_int_ncefa from CANFD3 Non correctable error int internal" "0,1" bitfld.long 0x0 23. "CANFD3_IPI_INT_NCEHA,ipi_int_nceha from CANFD3 Non correctable error int host" "0,1" newline bitfld.long 0x0 22. "CANFD3_IPI_INT_CE,ipi_int_ce from CANFD3 Correctable error interrupt" "0,1" bitfld.long 0x0 21. "CANFD2_IPI_INT_NCEFA,ipi_int_ncefa from CANFD2 Non correctable error int internal" "0,1" bitfld.long 0x0 20. "CANFD2_IPI_INT_NCEHA,ipi_int_nceha from CANFD2 Non correctable error int host" "0,1" newline bitfld.long 0x0 19. "CANFD2_IPI_INT_CE,ipi_int_ce from CANFD2 Correctable error interrupt" "0,1" bitfld.long 0x0 18. "CANFD1_IPI_INT_NCEFA,ipi_int_ncefa from CANFD1 Non correctable error int internal" "0,1" bitfld.long 0x0 17. "CANFD1_IPI_INT_NCEHA,ipi_int_nceha from CANFD1 Non correctable error int host" "0,1" newline bitfld.long 0x0 16. "CANFD1_IPI_INT_CE,ipi_int_ce from CANFD1 Correctable error interrupt" "0,1" bitfld.long 0x0 15. "ENET2_SBD_SFTY_UE_INTR_O,sbd_sfty_ue_intr_o from ENET2" "0,1" bitfld.long 0x0 14. "ENET2_SBD_SFTY_CE_INTR_O,sbd_sfty_ce_intr_o from ENET2" "0,1" newline bitfld.long 0x0 13. "ENET1_SBD_SFTY_UE_INTR_O,sbd_sfty_ue_intr_o from ENET1" "0,1" bitfld.long 0x0 12. "ENET1_SBD_SFTY_CE_INTR_O,sbd_sfty_ce_intr_o from ENET1" "0,1" bitfld.long 0x0 11. "RWMC2_MUL_ERR_INT,mul_err_int from RWMC2" "0,1" newline bitfld.long 0x0 10. "RWMC2_SIG_ERR_INT,sig_err_int from RWMC2" "0,1" bitfld.long 0x0 9. "RWMC1_MUL_ERR_INT,mul_err_int from RWMC1" "0,1" bitfld.long 0x0 8. "RWMC1_SIG_ERR_INT,sig_err_int from RWMC1" "0,1" newline bitfld.long 0x0 7. "IRAM4_MUL_ERR_INT,mul_err_int from IRAM4" "0,1" bitfld.long 0x0 6. "IRAM4_SIG_ERR_INT,sig_err_int from IRAM4" "0,1" bitfld.long 0x0 5. "IRAM3_MUL_ERR_INT,mul_err_int from IRAM3" "0,1" newline bitfld.long 0x0 4. "IRAM3_SIG_ERR_INT,sig_err_int from IRAM3" "0,1" bitfld.long 0x0 3. "IRAM2_MUL_ERR_INT,mul_err_int from IRAM2" "0,1" bitfld.long 0x0 2. "IRAM2_SIG_ERR_INT,sig_err_int from IRAM2" "0,1" newline bitfld.long 0x0 1. "IRAM1_MUL_ERR_INT,mul_err_int from IRAM1" "0,1" bitfld.long 0x0 0. "IRAM1_SIG_ERR_INT,sig_err_int from IRAM1" "0,1" repeat.end group.long 0x1A4++0x3 line.long 0x0 "INT_ENABLE_19,Interrupt Enable 1 for fatal error output to PIN" bitfld.long 0x0 30. "PVT_SNS_SAF_PVT_INT_1,pvt_int_1 from PVT_SNS_SAF" "0,1" bitfld.long 0x0 29. "PVT_SNS_SAF_PVT_INT_0,pvt_int_0 from PVT_SNS_SAF" "0,1" bitfld.long 0x0 28. "PVT_SNS_SEC_PVT_INT_1,pvt_int_1 from PVT_SNS_SEC" "0,1" newline bitfld.long 0x0 27. "PVT_SNS_SEC_PVT_INT_0,pvt_int_0 from PVT_SNS_SEC" "0,1" bitfld.long 0x0 26. "WDT8_ILL_SEQ_REFR_INT,ill_seq_refr_int from WDT8" "0,1" bitfld.long 0x0 25. "WDT8_ILL_WIN_REFR_INT,ill_win_refr_int from WDT8" "0,1" newline bitfld.long 0x0 24. "WDT8_OVFLOW_INT,ovflow_int from WDT8" "0,1" bitfld.long 0x0 23. "WDT7_ILL_SEQ_REFR_INT,ill_seq_refr_int from WDT7" "0,1" bitfld.long 0x0 22. "WDT7_ILL_WIN_REFR_INT,ill_win_refr_int from WDT7" "0,1" newline bitfld.long 0x0 21. "WDT7_OVFLOW_INT,ovflow_int from WDT7" "0,1" bitfld.long 0x0 20. "WDT6_ILL_SEQ_REFR_INT,ill_seq_refr_int from WDT6" "0,1" bitfld.long 0x0 19. "WDT6_ILL_WIN_REFR_INT,ill_win_refr_int from WDT6" "0,1" newline bitfld.long 0x0 18. "WDT6_OVFLOW_INT,ovflow_int from WDT6" "0,1" bitfld.long 0x0 17. "WDT5_ILL_SEQ_REFR_INT,ill_seq_refr_int from WDT5" "0,1" bitfld.long 0x0 16. "WDT5_ILL_WIN_REFR_INT,ill_win_refr_int from WDT5" "0,1" newline bitfld.long 0x0 15. "WDT5_OVFLOW_INT,ovflow_int from WDT5" "0,1" bitfld.long 0x0 14. "WDT4_ILL_SEQ_REFR_INT,ill_seq_refr_int from WDT4" "0,1" bitfld.long 0x0 13. "WDT4_ILL_WIN_REFR_INT,ill_win_refr_int from WDT4" "0,1" newline bitfld.long 0x0 12. "WDT4_OVFLOW_INT,ovflow_int from WDT4" "0,1" bitfld.long 0x0 11. "WDT3_ILL_SEQ_REFR_INT,ill_seq_refr_int from WDT3" "0,1" bitfld.long 0x0 10. "WDT3_ILL_WIN_REFR_INT,ill_win_refr_int from WDT3" "0,1" newline bitfld.long 0x0 9. "WDT3_OVFLOW_INT,ovflow_int from WDT3" "0,1" bitfld.long 0x0 8. "WDT2_ILL_SEQ_REFR_INT,ill_seq_refr_int from WDT2" "0,1" bitfld.long 0x0 7. "WDT2_ILL_WIN_REFR_INT,ill_win_refr_int from WDT2" "0,1" newline bitfld.long 0x0 6. "WDT2_OVFLOW_INT,ovflow_int from WDT2" "0,1" bitfld.long 0x0 5. "WDT1_ILL_SEQ_REFR_INT,ill_seq_refr_int from WDT1" "0,1" bitfld.long 0x0 4. "WDT1_ILL_WIN_REFR_INT,ill_win_refr_int from WDT1" "0,1" newline bitfld.long 0x0 3. "WDT1_OVFLOW_INT,ovflow_int from WDT1" "0,1" bitfld.long 0x0 2. "PWR_LAT_RTC_AP_POWER_LAT,ap_power_lat from PWR_LAT_RTC AP domain power fail" "0,1" bitfld.long 0x0 1. "PWR_LAT_RTC_SAF_POWER_LAT,saf_power_lat from PWR_LAT_RTC SAF domain power fail" "0,1" newline bitfld.long 0x0 0. "PWR_LAT_SAF_SAF_POWER_LAT,saf_power_lat from PWR_LAT_SAF SAF power fail" "0,1" repeat 9. (list 0x14 0x15 0x16 0x17 0x18 0x19 0x1A 0x1B 0x1C )(list 0x0 0x4 0x8 0xC 0x10 0x14 0x18 0x1C 0x20 ) group.long ($2+0x200)++0x3 line.long 0x0 "INT_ENABLE_$1,Interrupt Enable 2 for error output to CPU" bitfld.long 0x0 31. "CANFD6_IPI_INT_CE,ipi_int_ce from CANFD6 Correctable error interrupt" "0,1" bitfld.long 0x0 30. "CANFD5_IPI_INT_NCEFA,ipi_int_ncefa from CANFD5 Non correctable error int internal" "0,1" bitfld.long 0x0 29. "CANFD5_IPI_INT_NCEHA,ipi_int_nceha from CANFD5 Non correctable error int host" "0,1" newline bitfld.long 0x0 28. "CANFD5_IPI_INT_CE,ipi_int_ce from CANFD5 Correctable error interrupt" "0,1" bitfld.long 0x0 27. "CANFD4_IPI_INT_NCEFA,ipi_int_ncefa from CANFD4 Non correctable error int internal" "0,1" bitfld.long 0x0 26. "CANFD4_IPI_INT_NCEHA,ipi_int_nceha from CANFD4 Non correctable error int host" "0,1" newline bitfld.long 0x0 25. "CANFD4_IPI_INT_CE,ipi_int_ce from CANFD4 Correctable error interrupt" "0,1" bitfld.long 0x0 24. "CANFD3_IPI_INT_NCEFA,ipi_int_ncefa from CANFD3 Non correctable error int internal" "0,1" bitfld.long 0x0 23. "CANFD3_IPI_INT_NCEHA,ipi_int_nceha from CANFD3 Non correctable error int host" "0,1" newline bitfld.long 0x0 22. "CANFD3_IPI_INT_CE,ipi_int_ce from CANFD3 Correctable error interrupt" "0,1" bitfld.long 0x0 21. "CANFD2_IPI_INT_NCEFA,ipi_int_ncefa from CANFD2 Non correctable error int internal" "0,1" bitfld.long 0x0 20. "CANFD2_IPI_INT_NCEHA,ipi_int_nceha from CANFD2 Non correctable error int host" "0,1" newline bitfld.long 0x0 19. "CANFD2_IPI_INT_CE,ipi_int_ce from CANFD2 Correctable error interrupt" "0,1" bitfld.long 0x0 18. "CANFD1_IPI_INT_NCEFA,ipi_int_ncefa from CANFD1 Non correctable error int internal" "0,1" bitfld.long 0x0 17. "CANFD1_IPI_INT_NCEHA,ipi_int_nceha from CANFD1 Non correctable error int host" "0,1" newline bitfld.long 0x0 16. "CANFD1_IPI_INT_CE,ipi_int_ce from CANFD1 Correctable error interrupt" "0,1" bitfld.long 0x0 15. "ENET2_SBD_SFTY_UE_INTR_O,sbd_sfty_ue_intr_o from ENET2" "0,1" bitfld.long 0x0 14. "ENET2_SBD_SFTY_CE_INTR_O,sbd_sfty_ce_intr_o from ENET2" "0,1" newline bitfld.long 0x0 13. "ENET1_SBD_SFTY_UE_INTR_O,sbd_sfty_ue_intr_o from ENET1" "0,1" bitfld.long 0x0 12. "ENET1_SBD_SFTY_CE_INTR_O,sbd_sfty_ce_intr_o from ENET1" "0,1" bitfld.long 0x0 11. "RWMC2_MUL_ERR_INT,mul_err_int from RWMC2" "0,1" newline bitfld.long 0x0 10. "RWMC2_SIG_ERR_INT,sig_err_int from RWMC2" "0,1" bitfld.long 0x0 9. "RWMC1_MUL_ERR_INT,mul_err_int from RWMC1" "0,1" bitfld.long 0x0 8. "RWMC1_SIG_ERR_INT,sig_err_int from RWMC1" "0,1" newline bitfld.long 0x0 7. "IRAM4_MUL_ERR_INT,mul_err_int from IRAM4" "0,1" bitfld.long 0x0 6. "IRAM4_SIG_ERR_INT,sig_err_int from IRAM4" "0,1" bitfld.long 0x0 5. "IRAM3_MUL_ERR_INT,mul_err_int from IRAM3" "0,1" newline bitfld.long 0x0 4. "IRAM3_SIG_ERR_INT,sig_err_int from IRAM3" "0,1" bitfld.long 0x0 3. "IRAM2_MUL_ERR_INT,mul_err_int from IRAM2" "0,1" bitfld.long 0x0 2. "IRAM2_SIG_ERR_INT,sig_err_int from IRAM2" "0,1" newline bitfld.long 0x0 1. "IRAM1_MUL_ERR_INT,mul_err_int from IRAM1" "0,1" bitfld.long 0x0 0. "IRAM1_SIG_ERR_INT,sig_err_int from IRAM1" "0,1" repeat.end group.long 0x224++0x3 line.long 0x0 "INT_ENABLE_29,Interrupt Enable 2 for error output to CPU" bitfld.long 0x0 30. "PVT_SNS_SAF_PVT_INT_1,pvt_int_1 from PVT_SNS_SAF" "0,1" bitfld.long 0x0 29. "PVT_SNS_SAF_PVT_INT_0,pvt_int_0 from PVT_SNS_SAF" "0,1" bitfld.long 0x0 28. "PVT_SNS_SEC_PVT_INT_1,pvt_int_1 from PVT_SNS_SEC" "0,1" newline bitfld.long 0x0 27. "PVT_SNS_SEC_PVT_INT_0,pvt_int_0 from PVT_SNS_SEC" "0,1" bitfld.long 0x0 26. "WDT8_ILL_SEQ_REFR_INT,ill_seq_refr_int from WDT8" "0,1" bitfld.long 0x0 25. "WDT8_ILL_WIN_REFR_INT,ill_win_refr_int from WDT8" "0,1" newline bitfld.long 0x0 24. "WDT8_OVFLOW_INT,ovflow_int from WDT8" "0,1" bitfld.long 0x0 23. "WDT7_ILL_SEQ_REFR_INT,ill_seq_refr_int from WDT7" "0,1" bitfld.long 0x0 22. "WDT7_ILL_WIN_REFR_INT,ill_win_refr_int from WDT7" "0,1" newline bitfld.long 0x0 21. "WDT7_OVFLOW_INT,ovflow_int from WDT7" "0,1" bitfld.long 0x0 20. "WDT6_ILL_SEQ_REFR_INT,ill_seq_refr_int from WDT6" "0,1" bitfld.long 0x0 19. "WDT6_ILL_WIN_REFR_INT,ill_win_refr_int from WDT6" "0,1" newline bitfld.long 0x0 18. "WDT6_OVFLOW_INT,ovflow_int from WDT6" "0,1" bitfld.long 0x0 17. "WDT5_ILL_SEQ_REFR_INT,ill_seq_refr_int from WDT5" "0,1" bitfld.long 0x0 16. "WDT5_ILL_WIN_REFR_INT,ill_win_refr_int from WDT5" "0,1" newline bitfld.long 0x0 15. "WDT5_OVFLOW_INT,ovflow_int from WDT5" "0,1" bitfld.long 0x0 14. "WDT4_ILL_SEQ_REFR_INT,ill_seq_refr_int from WDT4" "0,1" bitfld.long 0x0 13. "WDT4_ILL_WIN_REFR_INT,ill_win_refr_int from WDT4" "0,1" newline bitfld.long 0x0 12. "WDT4_OVFLOW_INT,ovflow_int from WDT4" "0,1" bitfld.long 0x0 11. "WDT3_ILL_SEQ_REFR_INT,ill_seq_refr_int from WDT3" "0,1" bitfld.long 0x0 10. "WDT3_ILL_WIN_REFR_INT,ill_win_refr_int from WDT3" "0,1" newline bitfld.long 0x0 9. "WDT3_OVFLOW_INT,ovflow_int from WDT3" "0,1" bitfld.long 0x0 8. "WDT2_ILL_SEQ_REFR_INT,ill_seq_refr_int from WDT2" "0,1" bitfld.long 0x0 7. "WDT2_ILL_WIN_REFR_INT,ill_win_refr_int from WDT2" "0,1" newline bitfld.long 0x0 6. "WDT2_OVFLOW_INT,ovflow_int from WDT2" "0,1" bitfld.long 0x0 5. "WDT1_ILL_SEQ_REFR_INT,ill_seq_refr_int from WDT1" "0,1" bitfld.long 0x0 4. "WDT1_ILL_WIN_REFR_INT,ill_win_refr_int from WDT1" "0,1" newline bitfld.long 0x0 3. "WDT1_OVFLOW_INT,ovflow_int from WDT1" "0,1" bitfld.long 0x0 2. "PWR_LAT_RTC_AP_POWER_LAT,ap_power_lat from PWR_LAT_RTC AP domain power fail" "0,1" bitfld.long 0x0 1. "PWR_LAT_RTC_SAF_POWER_LAT,saf_power_lat from PWR_LAT_RTC SAF domain power fail" "0,1" newline bitfld.long 0x0 0. "PWR_LAT_SAF_SAF_POWER_LAT,saf_power_lat from PWR_LAT_SAF SAF power fail" "0,1" repeat 9. (list 0x1E 0x1F 0x20 0x21 0x22 0x23 0x24 0x25 0x26 )(list 0x0 0x4 0x8 0xC 0x10 0x14 0x18 0x1C 0x20 ) group.long ($2+0x280)++0x3 line.long 0x0 "INT_ENABLE_$1,Interrupt Enable 3 for error output to rstgen" bitfld.long 0x0 31. "CANFD6_IPI_INT_CE,ipi_int_ce from CANFD6 Correctable error interrupt" "0,1" bitfld.long 0x0 30. "CANFD5_IPI_INT_NCEFA,ipi_int_ncefa from CANFD5 Non correctable error int internal" "0,1" bitfld.long 0x0 29. "CANFD5_IPI_INT_NCEHA,ipi_int_nceha from CANFD5 Non correctable error int host" "0,1" newline bitfld.long 0x0 28. "CANFD5_IPI_INT_CE,ipi_int_ce from CANFD5 Correctable error interrupt" "0,1" bitfld.long 0x0 27. "CANFD4_IPI_INT_NCEFA,ipi_int_ncefa from CANFD4 Non correctable error int internal" "0,1" bitfld.long 0x0 26. "CANFD4_IPI_INT_NCEHA,ipi_int_nceha from CANFD4 Non correctable error int host" "0,1" newline bitfld.long 0x0 25. "CANFD4_IPI_INT_CE,ipi_int_ce from CANFD4 Correctable error interrupt" "0,1" bitfld.long 0x0 24. "CANFD3_IPI_INT_NCEFA,ipi_int_ncefa from CANFD3 Non correctable error int internal" "0,1" bitfld.long 0x0 23. "CANFD3_IPI_INT_NCEHA,ipi_int_nceha from CANFD3 Non correctable error int host" "0,1" newline bitfld.long 0x0 22. "CANFD3_IPI_INT_CE,ipi_int_ce from CANFD3 Correctable error interrupt" "0,1" bitfld.long 0x0 21. "CANFD2_IPI_INT_NCEFA,ipi_int_ncefa from CANFD2 Non correctable error int internal" "0,1" bitfld.long 0x0 20. "CANFD2_IPI_INT_NCEHA,ipi_int_nceha from CANFD2 Non correctable error int host" "0,1" newline bitfld.long 0x0 19. "CANFD2_IPI_INT_CE,ipi_int_ce from CANFD2 Correctable error interrupt" "0,1" bitfld.long 0x0 18. "CANFD1_IPI_INT_NCEFA,ipi_int_ncefa from CANFD1 Non correctable error int internal" "0,1" bitfld.long 0x0 17. "CANFD1_IPI_INT_NCEHA,ipi_int_nceha from CANFD1 Non correctable error int host" "0,1" newline bitfld.long 0x0 16. "CANFD1_IPI_INT_CE,ipi_int_ce from CANFD1 Correctable error interrupt" "0,1" bitfld.long 0x0 15. "ENET2_SBD_SFTY_UE_INTR_O,sbd_sfty_ue_intr_o from ENET2" "0,1" bitfld.long 0x0 14. "ENET2_SBD_SFTY_CE_INTR_O,sbd_sfty_ce_intr_o from ENET2" "0,1" newline bitfld.long 0x0 13. "ENET1_SBD_SFTY_UE_INTR_O,sbd_sfty_ue_intr_o from ENET1" "0,1" bitfld.long 0x0 12. "ENET1_SBD_SFTY_CE_INTR_O,sbd_sfty_ce_intr_o from ENET1" "0,1" bitfld.long 0x0 11. "RWMC2_MUL_ERR_INT,mul_err_int from RWMC2" "0,1" newline bitfld.long 0x0 10. "RWMC2_SIG_ERR_INT,sig_err_int from RWMC2" "0,1" bitfld.long 0x0 9. "RWMC1_MUL_ERR_INT,mul_err_int from RWMC1" "0,1" bitfld.long 0x0 8. "RWMC1_SIG_ERR_INT,sig_err_int from RWMC1" "0,1" newline bitfld.long 0x0 7. "IRAM4_MUL_ERR_INT,mul_err_int from IRAM4" "0,1" bitfld.long 0x0 6. "IRAM4_SIG_ERR_INT,sig_err_int from IRAM4" "0,1" bitfld.long 0x0 5. "IRAM3_MUL_ERR_INT,mul_err_int from IRAM3" "0,1" newline bitfld.long 0x0 4. "IRAM3_SIG_ERR_INT,sig_err_int from IRAM3" "0,1" bitfld.long 0x0 3. "IRAM2_MUL_ERR_INT,mul_err_int from IRAM2" "0,1" bitfld.long 0x0 2. "IRAM2_SIG_ERR_INT,sig_err_int from IRAM2" "0,1" newline bitfld.long 0x0 1. "IRAM1_MUL_ERR_INT,mul_err_int from IRAM1" "0,1" bitfld.long 0x0 0. "IRAM1_SIG_ERR_INT,sig_err_int from IRAM1" "0,1" repeat.end group.long 0x2A4++0x3 line.long 0x0 "INT_ENABLE_39,Interrupt Enable 3 for error output to rstgen" bitfld.long 0x0 30. "PVT_SNS_SAF_PVT_INT_1,pvt_int_1 from PVT_SNS_SAF" "0,1" bitfld.long 0x0 29. "PVT_SNS_SAF_PVT_INT_0,pvt_int_0 from PVT_SNS_SAF" "0,1" bitfld.long 0x0 28. "PVT_SNS_SEC_PVT_INT_1,pvt_int_1 from PVT_SNS_SEC" "0,1" newline bitfld.long 0x0 27. "PVT_SNS_SEC_PVT_INT_0,pvt_int_0 from PVT_SNS_SEC" "0,1" bitfld.long 0x0 26. "WDT8_ILL_SEQ_REFR_INT,ill_seq_refr_int from WDT8" "0,1" bitfld.long 0x0 25. "WDT8_ILL_WIN_REFR_INT,ill_win_refr_int from WDT8" "0,1" newline bitfld.long 0x0 24. "WDT8_OVFLOW_INT,ovflow_int from WDT8" "0,1" bitfld.long 0x0 23. "WDT7_ILL_SEQ_REFR_INT,ill_seq_refr_int from WDT7" "0,1" bitfld.long 0x0 22. "WDT7_ILL_WIN_REFR_INT,ill_win_refr_int from WDT7" "0,1" newline bitfld.long 0x0 21. "WDT7_OVFLOW_INT,ovflow_int from WDT7" "0,1" bitfld.long 0x0 20. "WDT6_ILL_SEQ_REFR_INT,ill_seq_refr_int from WDT6" "0,1" bitfld.long 0x0 19. "WDT6_ILL_WIN_REFR_INT,ill_win_refr_int from WDT6" "0,1" newline bitfld.long 0x0 18. "WDT6_OVFLOW_INT,ovflow_int from WDT6" "0,1" bitfld.long 0x0 17. "WDT5_ILL_SEQ_REFR_INT,ill_seq_refr_int from WDT5" "0,1" bitfld.long 0x0 16. "WDT5_ILL_WIN_REFR_INT,ill_win_refr_int from WDT5" "0,1" newline bitfld.long 0x0 15. "WDT5_OVFLOW_INT,ovflow_int from WDT5" "0,1" bitfld.long 0x0 14. "WDT4_ILL_SEQ_REFR_INT,ill_seq_refr_int from WDT4" "0,1" bitfld.long 0x0 13. "WDT4_ILL_WIN_REFR_INT,ill_win_refr_int from WDT4" "0,1" newline bitfld.long 0x0 12. "WDT4_OVFLOW_INT,ovflow_int from WDT4" "0,1" bitfld.long 0x0 11. "WDT3_ILL_SEQ_REFR_INT,ill_seq_refr_int from WDT3" "0,1" bitfld.long 0x0 10. "WDT3_ILL_WIN_REFR_INT,ill_win_refr_int from WDT3" "0,1" newline bitfld.long 0x0 9. "WDT3_OVFLOW_INT,ovflow_int from WDT3" "0,1" bitfld.long 0x0 8. "WDT2_ILL_SEQ_REFR_INT,ill_seq_refr_int from WDT2" "0,1" bitfld.long 0x0 7. "WDT2_ILL_WIN_REFR_INT,ill_win_refr_int from WDT2" "0,1" newline bitfld.long 0x0 6. "WDT2_OVFLOW_INT,ovflow_int from WDT2" "0,1" bitfld.long 0x0 5. "WDT1_ILL_SEQ_REFR_INT,ill_seq_refr_int from WDT1" "0,1" bitfld.long 0x0 4. "WDT1_ILL_WIN_REFR_INT,ill_win_refr_int from WDT1" "0,1" newline bitfld.long 0x0 3. "WDT1_OVFLOW_INT,ovflow_int from WDT1" "0,1" bitfld.long 0x0 2. "PWR_LAT_RTC_AP_POWER_LAT,ap_power_lat from PWR_LAT_RTC AP domain power fail" "0,1" bitfld.long 0x0 1. "PWR_LAT_RTC_SAF_POWER_LAT,saf_power_lat from PWR_LAT_RTC SAF domain power fail" "0,1" newline bitfld.long 0x0 0. "PWR_LAT_SAF_SAF_POWER_LAT,saf_power_lat from PWR_LAT_SAF SAF power fail" "0,1" repeat 9. (list 0x28 0x29 0x2A 0x2B 0x2C 0x2D 0x2E 0x2F 0x30 )(list 0x0 0x4 0x8 0xC 0x10 0x14 0x18 0x1C 0x20 ) group.long ($2+0x300)++0x3 line.long 0x0 "INT_ENABLE_$1,Interrupt Enable 4 for error output to DC" bitfld.long 0x0 31. "CANFD6_IPI_INT_CE,ipi_int_ce from CANFD6 Correctable error interrupt" "0,1" bitfld.long 0x0 30. "CANFD5_IPI_INT_NCEFA,ipi_int_ncefa from CANFD5 Non correctable error int internal" "0,1" bitfld.long 0x0 29. "CANFD5_IPI_INT_NCEHA,ipi_int_nceha from CANFD5 Non correctable error int host" "0,1" newline bitfld.long 0x0 28. "CANFD5_IPI_INT_CE,ipi_int_ce from CANFD5 Correctable error interrupt" "0,1" bitfld.long 0x0 27. "CANFD4_IPI_INT_NCEFA,ipi_int_ncefa from CANFD4 Non correctable error int internal" "0,1" bitfld.long 0x0 26. "CANFD4_IPI_INT_NCEHA,ipi_int_nceha from CANFD4 Non correctable error int host" "0,1" newline bitfld.long 0x0 25. "CANFD4_IPI_INT_CE,ipi_int_ce from CANFD4 Correctable error interrupt" "0,1" bitfld.long 0x0 24. "CANFD3_IPI_INT_NCEFA,ipi_int_ncefa from CANFD3 Non correctable error int internal" "0,1" bitfld.long 0x0 23. "CANFD3_IPI_INT_NCEHA,ipi_int_nceha from CANFD3 Non correctable error int host" "0,1" newline bitfld.long 0x0 22. "CANFD3_IPI_INT_CE,ipi_int_ce from CANFD3 Correctable error interrupt" "0,1" bitfld.long 0x0 21. "CANFD2_IPI_INT_NCEFA,ipi_int_ncefa from CANFD2 Non correctable error int internal" "0,1" bitfld.long 0x0 20. "CANFD2_IPI_INT_NCEHA,ipi_int_nceha from CANFD2 Non correctable error int host" "0,1" newline bitfld.long 0x0 19. "CANFD2_IPI_INT_CE,ipi_int_ce from CANFD2 Correctable error interrupt" "0,1" bitfld.long 0x0 18. "CANFD1_IPI_INT_NCEFA,ipi_int_ncefa from CANFD1 Non correctable error int internal" "0,1" bitfld.long 0x0 17. "CANFD1_IPI_INT_NCEHA,ipi_int_nceha from CANFD1 Non correctable error int host" "0,1" newline bitfld.long 0x0 16. "CANFD1_IPI_INT_CE,ipi_int_ce from CANFD1 Correctable error interrupt" "0,1" bitfld.long 0x0 15. "ENET2_SBD_SFTY_UE_INTR_O,sbd_sfty_ue_intr_o from ENET2" "0,1" bitfld.long 0x0 14. "ENET2_SBD_SFTY_CE_INTR_O,sbd_sfty_ce_intr_o from ENET2" "0,1" newline bitfld.long 0x0 13. "ENET1_SBD_SFTY_UE_INTR_O,sbd_sfty_ue_intr_o from ENET1" "0,1" bitfld.long 0x0 12. "ENET1_SBD_SFTY_CE_INTR_O,sbd_sfty_ce_intr_o from ENET1" "0,1" bitfld.long 0x0 11. "RWMC2_MUL_ERR_INT,mul_err_int from RWMC2" "0,1" newline bitfld.long 0x0 10. "RWMC2_SIG_ERR_INT,sig_err_int from RWMC2" "0,1" bitfld.long 0x0 9. "RWMC1_MUL_ERR_INT,mul_err_int from RWMC1" "0,1" bitfld.long 0x0 8. "RWMC1_SIG_ERR_INT,sig_err_int from RWMC1" "0,1" newline bitfld.long 0x0 7. "IRAM4_MUL_ERR_INT,mul_err_int from IRAM4" "0,1" bitfld.long 0x0 6. "IRAM4_SIG_ERR_INT,sig_err_int from IRAM4" "0,1" bitfld.long 0x0 5. "IRAM3_MUL_ERR_INT,mul_err_int from IRAM3" "0,1" newline bitfld.long 0x0 4. "IRAM3_SIG_ERR_INT,sig_err_int from IRAM3" "0,1" bitfld.long 0x0 3. "IRAM2_MUL_ERR_INT,mul_err_int from IRAM2" "0,1" bitfld.long 0x0 2. "IRAM2_SIG_ERR_INT,sig_err_int from IRAM2" "0,1" newline bitfld.long 0x0 1. "IRAM1_MUL_ERR_INT,mul_err_int from IRAM1" "0,1" bitfld.long 0x0 0. "IRAM1_SIG_ERR_INT,sig_err_int from IRAM1" "0,1" repeat.end group.long 0x324++0x3 line.long 0x0 "INT_ENABLE_49,Interrupt Enable 4 for error output to DC" bitfld.long 0x0 30. "PVT_SNS_SAF_PVT_INT_1,pvt_int_1 from PVT_SNS_SAF" "0,1" bitfld.long 0x0 29. "PVT_SNS_SAF_PVT_INT_0,pvt_int_0 from PVT_SNS_SAF" "0,1" bitfld.long 0x0 28. "PVT_SNS_SEC_PVT_INT_1,pvt_int_1 from PVT_SNS_SEC" "0,1" newline bitfld.long 0x0 27. "PVT_SNS_SEC_PVT_INT_0,pvt_int_0 from PVT_SNS_SEC" "0,1" bitfld.long 0x0 26. "WDT8_ILL_SEQ_REFR_INT,ill_seq_refr_int from WDT8" "0,1" bitfld.long 0x0 25. "WDT8_ILL_WIN_REFR_INT,ill_win_refr_int from WDT8" "0,1" newline bitfld.long 0x0 24. "WDT8_OVFLOW_INT,ovflow_int from WDT8" "0,1" bitfld.long 0x0 23. "WDT7_ILL_SEQ_REFR_INT,ill_seq_refr_int from WDT7" "0,1" bitfld.long 0x0 22. "WDT7_ILL_WIN_REFR_INT,ill_win_refr_int from WDT7" "0,1" newline bitfld.long 0x0 21. "WDT7_OVFLOW_INT,ovflow_int from WDT7" "0,1" bitfld.long 0x0 20. "WDT6_ILL_SEQ_REFR_INT,ill_seq_refr_int from WDT6" "0,1" bitfld.long 0x0 19. "WDT6_ILL_WIN_REFR_INT,ill_win_refr_int from WDT6" "0,1" newline bitfld.long 0x0 18. "WDT6_OVFLOW_INT,ovflow_int from WDT6" "0,1" bitfld.long 0x0 17. "WDT5_ILL_SEQ_REFR_INT,ill_seq_refr_int from WDT5" "0,1" bitfld.long 0x0 16. "WDT5_ILL_WIN_REFR_INT,ill_win_refr_int from WDT5" "0,1" newline bitfld.long 0x0 15. "WDT5_OVFLOW_INT,ovflow_int from WDT5" "0,1" bitfld.long 0x0 14. "WDT4_ILL_SEQ_REFR_INT,ill_seq_refr_int from WDT4" "0,1" bitfld.long 0x0 13. "WDT4_ILL_WIN_REFR_INT,ill_win_refr_int from WDT4" "0,1" newline bitfld.long 0x0 12. "WDT4_OVFLOW_INT,ovflow_int from WDT4" "0,1" bitfld.long 0x0 11. "WDT3_ILL_SEQ_REFR_INT,ill_seq_refr_int from WDT3" "0,1" bitfld.long 0x0 10. "WDT3_ILL_WIN_REFR_INT,ill_win_refr_int from WDT3" "0,1" newline bitfld.long 0x0 9. "WDT3_OVFLOW_INT,ovflow_int from WDT3" "0,1" bitfld.long 0x0 8. "WDT2_ILL_SEQ_REFR_INT,ill_seq_refr_int from WDT2" "0,1" bitfld.long 0x0 7. "WDT2_ILL_WIN_REFR_INT,ill_win_refr_int from WDT2" "0,1" newline bitfld.long 0x0 6. "WDT2_OVFLOW_INT,ovflow_int from WDT2" "0,1" bitfld.long 0x0 5. "WDT1_ILL_SEQ_REFR_INT,ill_seq_refr_int from WDT1" "0,1" bitfld.long 0x0 4. "WDT1_ILL_WIN_REFR_INT,ill_win_refr_int from WDT1" "0,1" newline bitfld.long 0x0 3. "WDT1_OVFLOW_INT,ovflow_int from WDT1" "0,1" bitfld.long 0x0 2. "PWR_LAT_RTC_AP_POWER_LAT,ap_power_lat from PWR_LAT_RTC AP domain power fail" "0,1" bitfld.long 0x0 1. "PWR_LAT_RTC_SAF_POWER_LAT,saf_power_lat from PWR_LAT_RTC SAF domain power fail" "0,1" newline bitfld.long 0x0 0. "PWR_LAT_SAF_SAF_POWER_LAT,saf_power_lat from PWR_LAT_SAF SAF power fail" "0,1" repeat 9. (list 0x32 0x33 0x34 0x35 0x36 0x37 0x38 0x39 0x3A )(list 0x0 0x4 0x8 0xC 0x10 0x14 0x18 0x1C 0x20 ) group.long ($2+0x380)++0x3 line.long 0x0 "INT_ENABLE_$1,Interrupt Enable 5 for error output to DC" bitfld.long 0x0 31. "CANFD6_IPI_INT_CE,ipi_int_ce from CANFD6 Correctable error interrupt" "0,1" bitfld.long 0x0 30. "CANFD5_IPI_INT_NCEFA,ipi_int_ncefa from CANFD5 Non correctable error int internal" "0,1" bitfld.long 0x0 29. "CANFD5_IPI_INT_NCEHA,ipi_int_nceha from CANFD5 Non correctable error int host" "0,1" newline bitfld.long 0x0 28. "CANFD5_IPI_INT_CE,ipi_int_ce from CANFD5 Correctable error interrupt" "0,1" bitfld.long 0x0 27. "CANFD4_IPI_INT_NCEFA,ipi_int_ncefa from CANFD4 Non correctable error int internal" "0,1" bitfld.long 0x0 26. "CANFD4_IPI_INT_NCEHA,ipi_int_nceha from CANFD4 Non correctable error int host" "0,1" newline bitfld.long 0x0 25. "CANFD4_IPI_INT_CE,ipi_int_ce from CANFD4 Correctable error interrupt" "0,1" bitfld.long 0x0 24. "CANFD3_IPI_INT_NCEFA,ipi_int_ncefa from CANFD3 Non correctable error int internal" "0,1" bitfld.long 0x0 23. "CANFD3_IPI_INT_NCEHA,ipi_int_nceha from CANFD3 Non correctable error int host" "0,1" newline bitfld.long 0x0 22. "CANFD3_IPI_INT_CE,ipi_int_ce from CANFD3 Correctable error interrupt" "0,1" bitfld.long 0x0 21. "CANFD2_IPI_INT_NCEFA,ipi_int_ncefa from CANFD2 Non correctable error int internal" "0,1" bitfld.long 0x0 20. "CANFD2_IPI_INT_NCEHA,ipi_int_nceha from CANFD2 Non correctable error int host" "0,1" newline bitfld.long 0x0 19. "CANFD2_IPI_INT_CE,ipi_int_ce from CANFD2 Correctable error interrupt" "0,1" bitfld.long 0x0 18. "CANFD1_IPI_INT_NCEFA,ipi_int_ncefa from CANFD1 Non correctable error int internal" "0,1" bitfld.long 0x0 17. "CANFD1_IPI_INT_NCEHA,ipi_int_nceha from CANFD1 Non correctable error int host" "0,1" newline bitfld.long 0x0 16. "CANFD1_IPI_INT_CE,ipi_int_ce from CANFD1 Correctable error interrupt" "0,1" bitfld.long 0x0 15. "ENET2_SBD_SFTY_UE_INTR_O,sbd_sfty_ue_intr_o from ENET2" "0,1" bitfld.long 0x0 14. "ENET2_SBD_SFTY_CE_INTR_O,sbd_sfty_ce_intr_o from ENET2" "0,1" newline bitfld.long 0x0 13. "ENET1_SBD_SFTY_UE_INTR_O,sbd_sfty_ue_intr_o from ENET1" "0,1" bitfld.long 0x0 12. "ENET1_SBD_SFTY_CE_INTR_O,sbd_sfty_ce_intr_o from ENET1" "0,1" bitfld.long 0x0 11. "RWMC2_MUL_ERR_INT,mul_err_int from RWMC2" "0,1" newline bitfld.long 0x0 10. "RWMC2_SIG_ERR_INT,sig_err_int from RWMC2" "0,1" bitfld.long 0x0 9. "RWMC1_MUL_ERR_INT,mul_err_int from RWMC1" "0,1" bitfld.long 0x0 8. "RWMC1_SIG_ERR_INT,sig_err_int from RWMC1" "0,1" newline bitfld.long 0x0 7. "IRAM4_MUL_ERR_INT,mul_err_int from IRAM4" "0,1" bitfld.long 0x0 6. "IRAM4_SIG_ERR_INT,sig_err_int from IRAM4" "0,1" bitfld.long 0x0 5. "IRAM3_MUL_ERR_INT,mul_err_int from IRAM3" "0,1" newline bitfld.long 0x0 4. "IRAM3_SIG_ERR_INT,sig_err_int from IRAM3" "0,1" bitfld.long 0x0 3. "IRAM2_MUL_ERR_INT,mul_err_int from IRAM2" "0,1" bitfld.long 0x0 2. "IRAM2_SIG_ERR_INT,sig_err_int from IRAM2" "0,1" newline bitfld.long 0x0 1. "IRAM1_MUL_ERR_INT,mul_err_int from IRAM1" "0,1" bitfld.long 0x0 0. "IRAM1_SIG_ERR_INT,sig_err_int from IRAM1" "0,1" repeat.end group.long 0x3A4++0x3 line.long 0x0 "INT_ENABLE_59,Interrupt Enable 5 for error output to DC" bitfld.long 0x0 30. "PVT_SNS_SAF_PVT_INT_1,pvt_int_1 from PVT_SNS_SAF" "0,1" bitfld.long 0x0 29. "PVT_SNS_SAF_PVT_INT_0,pvt_int_0 from PVT_SNS_SAF" "0,1" bitfld.long 0x0 28. "PVT_SNS_SEC_PVT_INT_1,pvt_int_1 from PVT_SNS_SEC" "0,1" newline bitfld.long 0x0 27. "PVT_SNS_SEC_PVT_INT_0,pvt_int_0 from PVT_SNS_SEC" "0,1" bitfld.long 0x0 26. "WDT8_ILL_SEQ_REFR_INT,ill_seq_refr_int from WDT8" "0,1" bitfld.long 0x0 25. "WDT8_ILL_WIN_REFR_INT,ill_win_refr_int from WDT8" "0,1" newline bitfld.long 0x0 24. "WDT8_OVFLOW_INT,ovflow_int from WDT8" "0,1" bitfld.long 0x0 23. "WDT7_ILL_SEQ_REFR_INT,ill_seq_refr_int from WDT7" "0,1" bitfld.long 0x0 22. "WDT7_ILL_WIN_REFR_INT,ill_win_refr_int from WDT7" "0,1" newline bitfld.long 0x0 21. "WDT7_OVFLOW_INT,ovflow_int from WDT7" "0,1" bitfld.long 0x0 20. "WDT6_ILL_SEQ_REFR_INT,ill_seq_refr_int from WDT6" "0,1" bitfld.long 0x0 19. "WDT6_ILL_WIN_REFR_INT,ill_win_refr_int from WDT6" "0,1" newline bitfld.long 0x0 18. "WDT6_OVFLOW_INT,ovflow_int from WDT6" "0,1" bitfld.long 0x0 17. "WDT5_ILL_SEQ_REFR_INT,ill_seq_refr_int from WDT5" "0,1" bitfld.long 0x0 16. "WDT5_ILL_WIN_REFR_INT,ill_win_refr_int from WDT5" "0,1" newline bitfld.long 0x0 15. "WDT5_OVFLOW_INT,ovflow_int from WDT5" "0,1" bitfld.long 0x0 14. "WDT4_ILL_SEQ_REFR_INT,ill_seq_refr_int from WDT4" "0,1" bitfld.long 0x0 13. "WDT4_ILL_WIN_REFR_INT,ill_win_refr_int from WDT4" "0,1" newline bitfld.long 0x0 12. "WDT4_OVFLOW_INT,ovflow_int from WDT4" "0,1" bitfld.long 0x0 11. "WDT3_ILL_SEQ_REFR_INT,ill_seq_refr_int from WDT3" "0,1" bitfld.long 0x0 10. "WDT3_ILL_WIN_REFR_INT,ill_win_refr_int from WDT3" "0,1" newline bitfld.long 0x0 9. "WDT3_OVFLOW_INT,ovflow_int from WDT3" "0,1" bitfld.long 0x0 8. "WDT2_ILL_SEQ_REFR_INT,ill_seq_refr_int from WDT2" "0,1" bitfld.long 0x0 7. "WDT2_ILL_WIN_REFR_INT,ill_win_refr_int from WDT2" "0,1" newline bitfld.long 0x0 6. "WDT2_OVFLOW_INT,ovflow_int from WDT2" "0,1" bitfld.long 0x0 5. "WDT1_ILL_SEQ_REFR_INT,ill_seq_refr_int from WDT1" "0,1" bitfld.long 0x0 4. "WDT1_ILL_WIN_REFR_INT,ill_win_refr_int from WDT1" "0,1" newline bitfld.long 0x0 3. "WDT1_OVFLOW_INT,ovflow_int from WDT1" "0,1" bitfld.long 0x0 2. "PWR_LAT_RTC_AP_POWER_LAT,ap_power_lat from PWR_LAT_RTC AP domain power fail" "0,1" bitfld.long 0x0 1. "PWR_LAT_RTC_SAF_POWER_LAT,saf_power_lat from PWR_LAT_RTC SAF domain power fail" "0,1" newline bitfld.long 0x0 0. "PWR_LAT_SAF_SAF_POWER_LAT,saf_power_lat from PWR_LAT_SAF SAF power fail" "0,1" repeat 9. (list 0x3C 0x3D 0x3E 0x3F 0x40 0x41 0x42 0x43 0x44 )(list 0x0 0x4 0x8 0xC 0x10 0x14 0x18 0x1C 0x20 ) group.long ($2+0x400)++0x3 line.long 0x0 "INT_ENABLE_$1,Interrupt Enable 6 for error output to DC" bitfld.long 0x0 31. "CANFD6_IPI_INT_CE,ipi_int_ce from CANFD6 Correctable error interrupt" "0,1" bitfld.long 0x0 30. "CANFD5_IPI_INT_NCEFA,ipi_int_ncefa from CANFD5 Non correctable error int internal" "0,1" bitfld.long 0x0 29. "CANFD5_IPI_INT_NCEHA,ipi_int_nceha from CANFD5 Non correctable error int host" "0,1" newline bitfld.long 0x0 28. "CANFD5_IPI_INT_CE,ipi_int_ce from CANFD5 Correctable error interrupt" "0,1" bitfld.long 0x0 27. "CANFD4_IPI_INT_NCEFA,ipi_int_ncefa from CANFD4 Non correctable error int internal" "0,1" bitfld.long 0x0 26. "CANFD4_IPI_INT_NCEHA,ipi_int_nceha from CANFD4 Non correctable error int host" "0,1" newline bitfld.long 0x0 25. "CANFD4_IPI_INT_CE,ipi_int_ce from CANFD4 Correctable error interrupt" "0,1" bitfld.long 0x0 24. "CANFD3_IPI_INT_NCEFA,ipi_int_ncefa from CANFD3 Non correctable error int internal" "0,1" bitfld.long 0x0 23. "CANFD3_IPI_INT_NCEHA,ipi_int_nceha from CANFD3 Non correctable error int host" "0,1" newline bitfld.long 0x0 22. "CANFD3_IPI_INT_CE,ipi_int_ce from CANFD3 Correctable error interrupt" "0,1" bitfld.long 0x0 21. "CANFD2_IPI_INT_NCEFA,ipi_int_ncefa from CANFD2 Non correctable error int internal" "0,1" bitfld.long 0x0 20. "CANFD2_IPI_INT_NCEHA,ipi_int_nceha from CANFD2 Non correctable error int host" "0,1" newline bitfld.long 0x0 19. "CANFD2_IPI_INT_CE,ipi_int_ce from CANFD2 Correctable error interrupt" "0,1" bitfld.long 0x0 18. "CANFD1_IPI_INT_NCEFA,ipi_int_ncefa from CANFD1 Non correctable error int internal" "0,1" bitfld.long 0x0 17. "CANFD1_IPI_INT_NCEHA,ipi_int_nceha from CANFD1 Non correctable error int host" "0,1" newline bitfld.long 0x0 16. "CANFD1_IPI_INT_CE,ipi_int_ce from CANFD1 Correctable error interrupt" "0,1" bitfld.long 0x0 15. "ENET2_SBD_SFTY_UE_INTR_O,sbd_sfty_ue_intr_o from ENET2" "0,1" bitfld.long 0x0 14. "ENET2_SBD_SFTY_CE_INTR_O,sbd_sfty_ce_intr_o from ENET2" "0,1" newline bitfld.long 0x0 13. "ENET1_SBD_SFTY_UE_INTR_O,sbd_sfty_ue_intr_o from ENET1" "0,1" bitfld.long 0x0 12. "ENET1_SBD_SFTY_CE_INTR_O,sbd_sfty_ce_intr_o from ENET1" "0,1" bitfld.long 0x0 11. "RWMC2_MUL_ERR_INT,mul_err_int from RWMC2" "0,1" newline bitfld.long 0x0 10. "RWMC2_SIG_ERR_INT,sig_err_int from RWMC2" "0,1" bitfld.long 0x0 9. "RWMC1_MUL_ERR_INT,mul_err_int from RWMC1" "0,1" bitfld.long 0x0 8. "RWMC1_SIG_ERR_INT,sig_err_int from RWMC1" "0,1" newline bitfld.long 0x0 7. "IRAM4_MUL_ERR_INT,mul_err_int from IRAM4" "0,1" bitfld.long 0x0 6. "IRAM4_SIG_ERR_INT,sig_err_int from IRAM4" "0,1" bitfld.long 0x0 5. "IRAM3_MUL_ERR_INT,mul_err_int from IRAM3" "0,1" newline bitfld.long 0x0 4. "IRAM3_SIG_ERR_INT,sig_err_int from IRAM3" "0,1" bitfld.long 0x0 3. "IRAM2_MUL_ERR_INT,mul_err_int from IRAM2" "0,1" bitfld.long 0x0 2. "IRAM2_SIG_ERR_INT,sig_err_int from IRAM2" "0,1" newline bitfld.long 0x0 1. "IRAM1_MUL_ERR_INT,mul_err_int from IRAM1" "0,1" bitfld.long 0x0 0. "IRAM1_SIG_ERR_INT,sig_err_int from IRAM1" "0,1" repeat.end group.long 0x424++0x3 line.long 0x0 "INT_ENABLE_69,Interrupt Enable 6 for error output to DC" bitfld.long 0x0 30. "PVT_SNS_SAF_PVT_INT_1,pvt_int_1 from PVT_SNS_SAF" "0,1" bitfld.long 0x0 29. "PVT_SNS_SAF_PVT_INT_0,pvt_int_0 from PVT_SNS_SAF" "0,1" bitfld.long 0x0 28. "PVT_SNS_SEC_PVT_INT_1,pvt_int_1 from PVT_SNS_SEC" "0,1" newline bitfld.long 0x0 27. "PVT_SNS_SEC_PVT_INT_0,pvt_int_0 from PVT_SNS_SEC" "0,1" bitfld.long 0x0 26. "WDT8_ILL_SEQ_REFR_INT,ill_seq_refr_int from WDT8" "0,1" bitfld.long 0x0 25. "WDT8_ILL_WIN_REFR_INT,ill_win_refr_int from WDT8" "0,1" newline bitfld.long 0x0 24. "WDT8_OVFLOW_INT,ovflow_int from WDT8" "0,1" bitfld.long 0x0 23. "WDT7_ILL_SEQ_REFR_INT,ill_seq_refr_int from WDT7" "0,1" bitfld.long 0x0 22. "WDT7_ILL_WIN_REFR_INT,ill_win_refr_int from WDT7" "0,1" newline bitfld.long 0x0 21. "WDT7_OVFLOW_INT,ovflow_int from WDT7" "0,1" bitfld.long 0x0 20. "WDT6_ILL_SEQ_REFR_INT,ill_seq_refr_int from WDT6" "0,1" bitfld.long 0x0 19. "WDT6_ILL_WIN_REFR_INT,ill_win_refr_int from WDT6" "0,1" newline bitfld.long 0x0 18. "WDT6_OVFLOW_INT,ovflow_int from WDT6" "0,1" bitfld.long 0x0 17. "WDT5_ILL_SEQ_REFR_INT,ill_seq_refr_int from WDT5" "0,1" bitfld.long 0x0 16. "WDT5_ILL_WIN_REFR_INT,ill_win_refr_int from WDT5" "0,1" newline bitfld.long 0x0 15. "WDT5_OVFLOW_INT,ovflow_int from WDT5" "0,1" bitfld.long 0x0 14. "WDT4_ILL_SEQ_REFR_INT,ill_seq_refr_int from WDT4" "0,1" bitfld.long 0x0 13. "WDT4_ILL_WIN_REFR_INT,ill_win_refr_int from WDT4" "0,1" newline bitfld.long 0x0 12. "WDT4_OVFLOW_INT,ovflow_int from WDT4" "0,1" bitfld.long 0x0 11. "WDT3_ILL_SEQ_REFR_INT,ill_seq_refr_int from WDT3" "0,1" bitfld.long 0x0 10. "WDT3_ILL_WIN_REFR_INT,ill_win_refr_int from WDT3" "0,1" newline bitfld.long 0x0 9. "WDT3_OVFLOW_INT,ovflow_int from WDT3" "0,1" bitfld.long 0x0 8. "WDT2_ILL_SEQ_REFR_INT,ill_seq_refr_int from WDT2" "0,1" bitfld.long 0x0 7. "WDT2_ILL_WIN_REFR_INT,ill_win_refr_int from WDT2" "0,1" newline bitfld.long 0x0 6. "WDT2_OVFLOW_INT,ovflow_int from WDT2" "0,1" bitfld.long 0x0 5. "WDT1_ILL_SEQ_REFR_INT,ill_seq_refr_int from WDT1" "0,1" bitfld.long 0x0 4. "WDT1_ILL_WIN_REFR_INT,ill_win_refr_int from WDT1" "0,1" newline bitfld.long 0x0 3. "WDT1_OVFLOW_INT,ovflow_int from WDT1" "0,1" bitfld.long 0x0 2. "PWR_LAT_RTC_AP_POWER_LAT,ap_power_lat from PWR_LAT_RTC AP domain power fail" "0,1" bitfld.long 0x0 1. "PWR_LAT_RTC_SAF_POWER_LAT,saf_power_lat from PWR_LAT_RTC SAF domain power fail" "0,1" newline bitfld.long 0x0 0. "PWR_LAT_SAF_SAF_POWER_LAT,saf_power_lat from PWR_LAT_SAF SAF power fail" "0,1" repeat 9. (list 0x46 0x47 0x48 0x49 0x4A 0x4B 0x4C 0x4D 0x4E )(list 0x0 0x4 0x8 0xC 0x10 0x14 0x18 0x1C 0x20 ) group.long ($2+0x480)++0x3 line.long 0x0 "INT_ENABLE_$1,Interrupt Enable 7 for error output to DC" bitfld.long 0x0 31. "CANFD6_IPI_INT_CE,ipi_int_ce from CANFD6 Correctable error interrupt" "0,1" bitfld.long 0x0 30. "CANFD5_IPI_INT_NCEFA,ipi_int_ncefa from CANFD5 Non correctable error int internal" "0,1" bitfld.long 0x0 29. "CANFD5_IPI_INT_NCEHA,ipi_int_nceha from CANFD5 Non correctable error int host" "0,1" newline bitfld.long 0x0 28. "CANFD5_IPI_INT_CE,ipi_int_ce from CANFD5 Correctable error interrupt" "0,1" bitfld.long 0x0 27. "CANFD4_IPI_INT_NCEFA,ipi_int_ncefa from CANFD4 Non correctable error int internal" "0,1" bitfld.long 0x0 26. "CANFD4_IPI_INT_NCEHA,ipi_int_nceha from CANFD4 Non correctable error int host" "0,1" newline bitfld.long 0x0 25. "CANFD4_IPI_INT_CE,ipi_int_ce from CANFD4 Correctable error interrupt" "0,1" bitfld.long 0x0 24. "CANFD3_IPI_INT_NCEFA,ipi_int_ncefa from CANFD3 Non correctable error int internal" "0,1" bitfld.long 0x0 23. "CANFD3_IPI_INT_NCEHA,ipi_int_nceha from CANFD3 Non correctable error int host" "0,1" newline bitfld.long 0x0 22. "CANFD3_IPI_INT_CE,ipi_int_ce from CANFD3 Correctable error interrupt" "0,1" bitfld.long 0x0 21. "CANFD2_IPI_INT_NCEFA,ipi_int_ncefa from CANFD2 Non correctable error int internal" "0,1" bitfld.long 0x0 20. "CANFD2_IPI_INT_NCEHA,ipi_int_nceha from CANFD2 Non correctable error int host" "0,1" newline bitfld.long 0x0 19. "CANFD2_IPI_INT_CE,ipi_int_ce from CANFD2 Correctable error interrupt" "0,1" bitfld.long 0x0 18. "CANFD1_IPI_INT_NCEFA,ipi_int_ncefa from CANFD1 Non correctable error int internal" "0,1" bitfld.long 0x0 17. "CANFD1_IPI_INT_NCEHA,ipi_int_nceha from CANFD1 Non correctable error int host" "0,1" newline bitfld.long 0x0 16. "CANFD1_IPI_INT_CE,ipi_int_ce from CANFD1 Correctable error interrupt" "0,1" bitfld.long 0x0 15. "ENET2_SBD_SFTY_UE_INTR_O,sbd_sfty_ue_intr_o from ENET2" "0,1" bitfld.long 0x0 14. "ENET2_SBD_SFTY_CE_INTR_O,sbd_sfty_ce_intr_o from ENET2" "0,1" newline bitfld.long 0x0 13. "ENET1_SBD_SFTY_UE_INTR_O,sbd_sfty_ue_intr_o from ENET1" "0,1" bitfld.long 0x0 12. "ENET1_SBD_SFTY_CE_INTR_O,sbd_sfty_ce_intr_o from ENET1" "0,1" bitfld.long 0x0 11. "RWMC2_MUL_ERR_INT,mul_err_int from RWMC2" "0,1" newline bitfld.long 0x0 10. "RWMC2_SIG_ERR_INT,sig_err_int from RWMC2" "0,1" bitfld.long 0x0 9. "RWMC1_MUL_ERR_INT,mul_err_int from RWMC1" "0,1" bitfld.long 0x0 8. "RWMC1_SIG_ERR_INT,sig_err_int from RWMC1" "0,1" newline bitfld.long 0x0 7. "IRAM4_MUL_ERR_INT,mul_err_int from IRAM4" "0,1" bitfld.long 0x0 6. "IRAM4_SIG_ERR_INT,sig_err_int from IRAM4" "0,1" bitfld.long 0x0 5. "IRAM3_MUL_ERR_INT,mul_err_int from IRAM3" "0,1" newline bitfld.long 0x0 4. "IRAM3_SIG_ERR_INT,sig_err_int from IRAM3" "0,1" bitfld.long 0x0 3. "IRAM2_MUL_ERR_INT,mul_err_int from IRAM2" "0,1" bitfld.long 0x0 2. "IRAM2_SIG_ERR_INT,sig_err_int from IRAM2" "0,1" newline bitfld.long 0x0 1. "IRAM1_MUL_ERR_INT,mul_err_int from IRAM1" "0,1" bitfld.long 0x0 0. "IRAM1_SIG_ERR_INT,sig_err_int from IRAM1" "0,1" repeat.end group.long 0x4A4++0x3 line.long 0x0 "INT_ENABLE_79,Interrupt Enable 7 for error output to DC" bitfld.long 0x0 30. "PVT_SNS_SAF_PVT_INT_1,pvt_int_1 from PVT_SNS_SAF" "0,1" bitfld.long 0x0 29. "PVT_SNS_SAF_PVT_INT_0,pvt_int_0 from PVT_SNS_SAF" "0,1" bitfld.long 0x0 28. "PVT_SNS_SEC_PVT_INT_1,pvt_int_1 from PVT_SNS_SEC" "0,1" newline bitfld.long 0x0 27. "PVT_SNS_SEC_PVT_INT_0,pvt_int_0 from PVT_SNS_SEC" "0,1" bitfld.long 0x0 26. "WDT8_ILL_SEQ_REFR_INT,ill_seq_refr_int from WDT8" "0,1" bitfld.long 0x0 25. "WDT8_ILL_WIN_REFR_INT,ill_win_refr_int from WDT8" "0,1" newline bitfld.long 0x0 24. "WDT8_OVFLOW_INT,ovflow_int from WDT8" "0,1" bitfld.long 0x0 23. "WDT7_ILL_SEQ_REFR_INT,ill_seq_refr_int from WDT7" "0,1" bitfld.long 0x0 22. "WDT7_ILL_WIN_REFR_INT,ill_win_refr_int from WDT7" "0,1" newline bitfld.long 0x0 21. "WDT7_OVFLOW_INT,ovflow_int from WDT7" "0,1" bitfld.long 0x0 20. "WDT6_ILL_SEQ_REFR_INT,ill_seq_refr_int from WDT6" "0,1" bitfld.long 0x0 19. "WDT6_ILL_WIN_REFR_INT,ill_win_refr_int from WDT6" "0,1" newline bitfld.long 0x0 18. "WDT6_OVFLOW_INT,ovflow_int from WDT6" "0,1" bitfld.long 0x0 17. "WDT5_ILL_SEQ_REFR_INT,ill_seq_refr_int from WDT5" "0,1" bitfld.long 0x0 16. "WDT5_ILL_WIN_REFR_INT,ill_win_refr_int from WDT5" "0,1" newline bitfld.long 0x0 15. "WDT5_OVFLOW_INT,ovflow_int from WDT5" "0,1" bitfld.long 0x0 14. "WDT4_ILL_SEQ_REFR_INT,ill_seq_refr_int from WDT4" "0,1" bitfld.long 0x0 13. "WDT4_ILL_WIN_REFR_INT,ill_win_refr_int from WDT4" "0,1" newline bitfld.long 0x0 12. "WDT4_OVFLOW_INT,ovflow_int from WDT4" "0,1" bitfld.long 0x0 11. "WDT3_ILL_SEQ_REFR_INT,ill_seq_refr_int from WDT3" "0,1" bitfld.long 0x0 10. "WDT3_ILL_WIN_REFR_INT,ill_win_refr_int from WDT3" "0,1" newline bitfld.long 0x0 9. "WDT3_OVFLOW_INT,ovflow_int from WDT3" "0,1" bitfld.long 0x0 8. "WDT2_ILL_SEQ_REFR_INT,ill_seq_refr_int from WDT2" "0,1" bitfld.long 0x0 7. "WDT2_ILL_WIN_REFR_INT,ill_win_refr_int from WDT2" "0,1" newline bitfld.long 0x0 6. "WDT2_OVFLOW_INT,ovflow_int from WDT2" "0,1" bitfld.long 0x0 5. "WDT1_ILL_SEQ_REFR_INT,ill_seq_refr_int from WDT1" "0,1" bitfld.long 0x0 4. "WDT1_ILL_WIN_REFR_INT,ill_win_refr_int from WDT1" "0,1" newline bitfld.long 0x0 3. "WDT1_OVFLOW_INT,ovflow_int from WDT1" "0,1" bitfld.long 0x0 2. "PWR_LAT_RTC_AP_POWER_LAT,ap_power_lat from PWR_LAT_RTC AP domain power fail" "0,1" bitfld.long 0x0 1. "PWR_LAT_RTC_SAF_POWER_LAT,saf_power_lat from PWR_LAT_RTC SAF domain power fail" "0,1" newline bitfld.long 0x0 0. "PWR_LAT_SAF_SAF_POWER_LAT,saf_power_lat from PWR_LAT_SAF SAF power fail" "0,1" group.long 0x500++0x17 line.long 0x0 "TGT_VALUE_0,signal monitor target value" hexmask.long.tbyte 0x0 12.--31. 1. "EFUSE_MISC_CFG,[69:12] efusec_misc_cfg[31:12]" bitfld.long 0x0 11. "IRAM4_ECC_DISABLE_MON,[11:11] iram4_ecc_disable_mon" "0,1" bitfld.long 0x0 10. "IRAM3_ECC_DISABLE_MON,[10:10] iram3_ecc_disable_mon" "0,1" newline bitfld.long 0x0 9. "IRAM2_ECC_DISABLE_MON,[9:9] iram2_ecc_disable_mon" "0,1" hexmask.long.word 0x0 0.--8. 1. "EFUSEC_MISC_CFG,[8:0] efusec_misc_cfg[8:0]" line.long 0x4 "TGT_VALUE_1,signal monitor target value" hexmask.long 0x4 0.--31. 1. "EFUSE_MISC_CFG,[69:12] efusec_misc_cfg[63:32]" line.long 0x8 "TGT_VALUE_2,signal monitor target value" hexmask.long.byte 0x8 25.--31. 1. "EFUSEC_MISC_CFG,[95:89] efusec_misc_cfg[95:89]" bitfld.long 0x8 24. "I_SEM1_INT_PAD_MON,[88:88] i_sem1_int_pad_mon" "0,1" bitfld.long 0x8 23. "I_SEM1_INT_CPU_HPI_MON,[87:87] i_sem1_int_cpu_hpi_mon" "0,1" newline bitfld.long 0x8 22. "I_SEM1_INT_CPU_SEC_MON,[86:86] i_sem1_int_cpu_sec_mon" "0,1" bitfld.long 0x8 21. "SEM1_SEM_INT_CPU,[85:85] sem1_sem_int_cpu" "0,1" bitfld.long 0x8 20. "I_SEM1_INT_DC5_MON,[84:84] i_sem1_int_dc5_mon" "0,1" newline bitfld.long 0x8 19. "I_SEM1_INT_DC4_MON,[83:83] i_sem1_int_dc4_mon" "0,1" bitfld.long 0x8 18. "I_SEM1_INT_DC3_MON,[82:82] i_sem1_int_dc3_mon" "0,1" bitfld.long 0x8 17. "I_SEM1_INT_DC2_MON,[81:81] i_sem1_int_dc2_mon" "0,1" newline bitfld.long 0x8 16. "I_SEM1_INT_DC1_MON,[80:80] i_sem1_int_dc1_mon" "0,1" bitfld.long 0x8 15. "I_SEM1_INT_SYS_SEC_MON,[79:79] i_sem1_int_sys_sec_mon" "0,1" bitfld.long 0x8 14. "I_SEM1_INT_SYS_RTC_MON,[78:78] i_sem1_int_sys_rtc_mon" "0,1" newline bitfld.long 0x8 13. "SEM1_SEM_INT_SYS,[77:77] sem1_sem_int_sys" "0,1" bitfld.long 0x8 12. "USER_MAC_DIS_HPI_MON,[76:76] user_mac_dis_hpi_mon" "0,1" bitfld.long 0x8 11. "USER_MAC_DIS_SEC_MON,[75:75] user_mac_dis_sec_mon" "0,1" newline bitfld.long 0x8 10. "PROD_ENABLE_MON,[74:74] prod_enable_mon" "0,1" bitfld.long 0x8 9. "GPU2_ASTC_DISABLE_MON,[73:73] gpu2_astc_disable_mon" "0,1" bitfld.long 0x8 8. "GPU1_ASTC_DISABLE_MON,[72:72] gpu1_astc_disable_mon" "0,1" newline bitfld.long 0x8 7. "APBMUX2_GPV_HPIB_SELECT,[71:71] apbmux2_gpv_hpib_select" "0,1" bitfld.long 0x8 6. "FUSE_SAF_DISABLE,[70:70] fuse_saf_disable" "0,1" hexmask.long.byte 0x8 0.--5. 1. "EFUSE_MISC_CFG,[69:12] efusec_misc_cfg[69:64]" line.long 0xC "TGT_VALUE_3,signal monitor target value" bitfld.long 0xC 30.--31. "EFUSEC_MISC_CFG,[127:126] efusec_misc_cfg[127:126]" "0,1,2,3" bitfld.long 0xC 29. "ALL_DBG_DISABLE_MON,[125:125] all_dbg_disable_mon" "0,1" hexmask.long.byte 0xC 23.--28. 1. "EFUSEC_MISC_CFG,[124:119] efusec_misc_cfg[124:119]" newline bitfld.long 0xC 22. "SEC_SAFETY_DISABLE_MON,[118:118] sec_safety_disable_mon" "0,1" bitfld.long 0xC 20.--21. "EFUSEC_MISC_CFG,[117:116] efusec_misc_cfg[117:116]" "0,1,2,3" bitfld.long 0xC 19. "GPU2_DBG_DISABLE_MON,[115:115] gpu2_dbg_disable_mon" "0,1" newline bitfld.long 0xC 18. "GPU1_DBG_DISABLE_MON,[114:114] gpu1_dbg_disable_mon" "0,1" bitfld.long 0xC 17. "ADSP_DBG_DISABLE_MON,[113:113] adsp_dbg_disable_mon" "0,1" bitfld.long 0xC 16. "VDSP_DBG_DISABLE_MON,[112:112] vdsp_dbg_disable_mon" "0,1" newline bitfld.long 0xC 15. "PARA_BOOT_DISABLE_MON,[111:111] para_boot_disable_mon" "0,1" bitfld.long 0xC 14. "EFUSEC_MISC_CFG,[110:110] efusec_misc_cfg[110]" "0,1" bitfld.long 0xC 13. "USER_MAC_DISABLE_MON,[109:109] user_mac_disable_mon" "0,1" newline bitfld.long 0xC 10.--12. "EFUSEC_MISC_CFG,[108:106] efusec_misc_cfg[108:106]" "0,1,2,3,4,5,6,7" bitfld.long 0xC 9. "PVT_SEC_SENS_EN_MON,[105:105] pvt_sec_sens_en_mon" "0,1" hexmask.long.word 0xC 0.--8. 1. "EFUSEC_MISC_CFG,[104:96] efusec_misc_cfg[104:96]" line.long 0x10 "TGT_VALUE_4,signal monitor target value" bitfld.long 0x10 31. "APBMUX2_BIPC_ENET1_SELECT,[159:159] apbmux2_bipc_enet1_select" "0,1" bitfld.long 0x10 30. "APBMUX2_PVT_SNS_SAF_SELECT,[158:158] apbmux2_pvt_sns_saf_select" "0,1" bitfld.long 0x10 29. "APBMUX2_PLL2_SELECT,[157:157] apbmux2_pll2_select" "0,1" newline bitfld.long 0x10 28. "APBMUX2_PLL1_SELECT,[156:156] apbmux2_pll1_select" "0,1" bitfld.long 0x10 27. "APBMUX2_RC_24M_SELECT,[155:155] apbmux2_rc_24m_select" "0,1" bitfld.long 0x10 26. "APBMUX2_DMA1_SELECT,[154:154] apbmux2_dma1_select" "0,1" newline bitfld.long 0x10 25. "APBMUX2_WDT1_SELECT,[153:153] apbmux2_wdt1_select" "0,1" bitfld.long 0x10 24. "APBMUX2_PWM2_SELECT,[152:152] apbmux2_pwm2_select" "0,1" bitfld.long 0x10 23. "APBMUX2_PWM1_SELECT,[151:151] apbmux2_pwm1_select" "0,1" newline bitfld.long 0x10 22. "APBMUX2_TIMER2_SELECT,[150:150] apbmux2_timer2_select" "0,1" bitfld.long 0x10 21. "APBMUX2_TIMER1_SELECT,[149:149] apbmux2_timer1_select" "0,1" bitfld.long 0x10 20. "APBMUX2_ENET1_SELECT,[148:148] apbmux2_enet1_select" "0,1" newline bitfld.long 0x10 19. "APBMUX2_UART8_SELECT,[147:147] apbmux2_uart8_select" "0,1" bitfld.long 0x10 18. "APBMUX2_UART7_SELECT,[146:146] apbmux2_uart7_select" "0,1" bitfld.long 0x10 17. "APBMUX2_UART6_SELECT,[145:145] apbmux2_uart6_select" "0,1" newline bitfld.long 0x10 16. "APBMUX2_UART5_SELECT,[144:144] apbmux2_uart5_select" "0,1" bitfld.long 0x10 15. "APBMUX2_UART4_SELECT,[143:143] apbmux2_uart4_select" "0,1" bitfld.long 0x10 14. "APBMUX2_UART3_SELECT,[142:142] apbmux2_uart3_select" "0,1" newline bitfld.long 0x10 13. "APBMUX2_UART2_SELECT,[141:141] apbmux2_uart2_select" "0,1" bitfld.long 0x10 12. "APBMUX2_UART1_SELECT,[140:140] apbmux2_uart1_select" "0,1" bitfld.long 0x10 11. "APBMUX2_I2C4_SELECT,[139:139] apbmux2_i2c4_select" "0,1" newline bitfld.long 0x10 10. "APBMUX2_I2C3_SELECT,[138:138] apbmux2_i2c3_select" "0,1" bitfld.long 0x10 9. "APBMUX2_I2C2_SELECT,[137:137] apbmux2_i2c2_select" "0,1" bitfld.long 0x10 8. "APBMUX2_I2C1_SELECT,[136:136] apbmux2_i2c1_select" "0,1" newline bitfld.long 0x10 7. "APBMUX2_CANFD4_SELECT,[135:135] apbmux2_canfd4_select" "0,1" bitfld.long 0x10 6. "APBMUX2_CANFD3_SELECT,[134:134] apbmux2_canfd3_select" "0,1" bitfld.long 0x10 5. "APBMUX2_CANFD2_SELECT,[133:133] apbmux2_canfd2_select" "0,1" newline bitfld.long 0x10 4. "APBMUX2_CANFD1_SELECT,[132:132] apbmux2_canfd1_select" "0,1" bitfld.long 0x10 3. "APBMUX2_OSPI1_SELECT,[131:131] apbmux2_ospi1_select" "0,1" bitfld.long 0x10 2. "APBMUX2_PWRCTRL_SELECT,[130:130] apbmux2_pwrctrl_select" "0,1" newline bitfld.long 0x10 1. "APBMUX2_CE1_SELECT,[129:129] apbmux2_ce1_select" "0,1" bitfld.long 0x10 0. "APBMUX2_SEM1_SELECT,[128:128] apbmux2_sem1_select" "0,1" line.long 0x14 "TGT_VALUE_5,signal monitor target value" bitfld.long 0x14 23. "APBMUX2_SEC_STORAGE2_SELECT,[183:183] apbmux2_sec_storage2_select" "0,1" bitfld.long 0x14 22. "APBMUX2_SEC_STORAGE1_SELECT,[182:182] apbmux2_sec_storage1_select" "0,1" bitfld.long 0x14 21. "APBMUX2_RSTGEN_RTC_SELECT,[181:181] apbmux2_rstgen_rtc_select" "0,1" newline bitfld.long 0x14 20. "APBMUX2_PMU_SELECT,[180:180] apbmux2_pmu_select" "0,1" bitfld.long 0x14 19. "APBMUX2_RTC2_SELECT,[179:179] apbmux2_rtc2_select" "0,1" bitfld.long 0x14 18. "APBMUX2_RTC1_SELECT,[178:178] apbmux2_rtc1_select" "0,1" newline bitfld.long 0x14 17. "APBMUX2_XTAL_RTC_SELECT,[177:177] apbmux2_xtal_rtc_select" "0,1" bitfld.long 0x14 16. "APBMUX2_IOMUX_CTRL_RTC_SELECT,[176:176] apbmux2_iomux_ctrl_rtc_select" "0,1" bitfld.long 0x14 15. "APBMUX2_RC_RTC_SELECT,[175:175] apbmux2_rc_rtc_select" "0,1" newline bitfld.long 0x14 14. "APBMUX2_TM_SELECT,[174:174] apbmux2_tm_select" "0,1" bitfld.long 0x14 13. "AXISLVMUX_CE1_SELECT,[173:173] axislvmux_ce1_select" "0,1" bitfld.long 0x14 12. "AXISLVMUX_DMA1_SELECT,[172:172] axislvmux_dma1_select" "0,1" newline bitfld.long 0x14 11. "AXISLVMUX_OSPI1_SELECT,[171:171] axislvmux_ospi1_select" "0,1" bitfld.long 0x14 10. "AXISLVMUX_IRAM1_SELECT,[170:170] axislvmux_iram1_select" "0,1" bitfld.long 0x14 9. "APBMUX2_EIC_SAFE_SELECT,[169:169] apbmux2_eic_safe_select" "0,1" newline bitfld.long 0x14 8. "APBMUX2_XTAL_SAF_SELECT,[168:168] apbmux2_xtal_saf_select" "0,1" bitfld.long 0x14 7. "APBMUX2_RPC_SAF_SELECT,[167:167] apbmux2_rpc_saf_select" "0,1" bitfld.long 0x14 6. "APBMUX2_SPI4_SELECT,[166:166] apbmux2_spi4_select" "0,1" newline bitfld.long 0x14 5. "APBMUX2_SPI3_SELECT,[165:165] apbmux2_spi3_select" "0,1" bitfld.long 0x14 4. "APBMUX2_SPI2_SELECT,[164:164] apbmux2_spi2_select" "0,1" bitfld.long 0x14 3. "APBMUX2_SPI1_SELECT,[163:163] apbmux2_spi1_select" "0,1" newline bitfld.long 0x14 2. "APBMUX2_IRAM1_SELECT,[162:162] apbmux2_iram1_select" "0,1" bitfld.long 0x14 1. "APBMUX2_I2S_SC2_SELECT,[161:161] apbmux2_i2s_sc2_select" "0,1" bitfld.long 0x14 0. "APBMUX2_I2S_SC1_SELECT,[160:160] apbmux2_i2s_sc1_select" "0,1" group.long 0x580++0x17 line.long 0x0 "SIG_MON_ENABLE_0,signal monitor enable" hexmask.long.tbyte 0x0 12.--31. 1. "EFUSE_MISC_CFG,[69:12] efusec_misc_cfg[31:12]" bitfld.long 0x0 11. "IRAM4_ECC_DISABLE_MON,[11:11] iram4_ecc_disable_mon" "0,1" bitfld.long 0x0 10. "IRAM3_ECC_DISABLE_MON,[10:10] iram3_ecc_disable_mon" "0,1" newline bitfld.long 0x0 9. "IRAM2_ECC_DISABLE_MON,[9:9] iram2_ecc_disable_mon" "0,1" hexmask.long.word 0x0 0.--8. 1. "EFUSEC_MISC_CFG,[8:0] efusec_misc_cfg[8:0]" line.long 0x4 "SIG_MON_ENABLE_1,signal monitor enable" hexmask.long 0x4 0.--31. 1. "EFUSE_MISC_CFG,[69:12] efusec_misc_cfg[63:32]" line.long 0x8 "SIG_MON_ENABLE_2,signal monitor enable" hexmask.long.byte 0x8 25.--31. 1. "EFUSEC_MISC_CFG,[95:89] efusec_misc_cfg[95:89]" bitfld.long 0x8 24. "I_SEM1_INT_PAD_MON,[88:88] i_sem1_int_pad_mon" "0,1" bitfld.long 0x8 23. "I_SEM1_INT_CPU_HPI_MON,[87:87] i_sem1_int_cpu_hpi_mon" "0,1" newline bitfld.long 0x8 22. "I_SEM1_INT_CPU_SEC_MON,[86:86] i_sem1_int_cpu_sec_mon" "0,1" bitfld.long 0x8 21. "SEM1_SEM_INT_CPU,[85:85] sem1_sem_int_cpu" "0,1" bitfld.long 0x8 20. "I_SEM1_INT_DC5_MON,[84:84] i_sem1_int_dc5_mon" "0,1" newline bitfld.long 0x8 19. "I_SEM1_INT_DC4_MON,[83:83] i_sem1_int_dc4_mon" "0,1" bitfld.long 0x8 18. "I_SEM1_INT_DC3_MON,[82:82] i_sem1_int_dc3_mon" "0,1" bitfld.long 0x8 17. "I_SEM1_INT_DC2_MON,[81:81] i_sem1_int_dc2_mon" "0,1" newline bitfld.long 0x8 16. "I_SEM1_INT_DC1_MON,[80:80] i_sem1_int_dc1_mon" "0,1" bitfld.long 0x8 15. "I_SEM1_INT_SYS_SEC_MON,[79:79] i_sem1_int_sys_sec_mon" "0,1" bitfld.long 0x8 14. "I_SEM1_INT_SYS_RTC_MON,[78:78] i_sem1_int_sys_rtc_mon" "0,1" newline bitfld.long 0x8 13. "SEM1_SEM_INT_SYS,[77:77] sem1_sem_int_sys" "0,1" bitfld.long 0x8 12. "USER_MAC_DIS_HPI_MON,[76:76] user_mac_dis_hpi_mon" "0,1" bitfld.long 0x8 11. "USER_MAC_DIS_SEC_MON,[75:75] user_mac_dis_sec_mon" "0,1" newline bitfld.long 0x8 10. "PROD_ENABLE_MON,[74:74] prod_enable_mon" "0,1" bitfld.long 0x8 9. "GPU2_ASTC_DISABLE_MON,[73:73] gpu2_astc_disable_mon" "0,1" bitfld.long 0x8 8. "GPU1_ASTC_DISABLE_MON,[72:72] gpu1_astc_disable_mon" "0,1" newline bitfld.long 0x8 7. "APBMUX2_GPV_HPIB_SELECT,[71:71] apbmux2_gpv_hpib_select" "0,1" bitfld.long 0x8 6. "FUSE_SAF_DISABLE,[70:70] fuse_saf_disable" "0,1" hexmask.long.byte 0x8 0.--5. 1. "EFUSE_MISC_CFG,[69:12] efusec_misc_cfg[69:64]" line.long 0xC "SIG_MON_ENABLE_3,signal monitor enable" bitfld.long 0xC 30.--31. "EFUSEC_MISC_CFG,[127:126] efusec_misc_cfg[127:126]" "0,1,2,3" bitfld.long 0xC 29. "ALL_DBG_DISABLE_MON,[125:125] all_dbg_disable_mon" "0,1" hexmask.long.byte 0xC 23.--28. 1. "EFUSEC_MISC_CFG,[124:119] efusec_misc_cfg[124:119]" newline bitfld.long 0xC 22. "SEC_SAFETY_DISABLE_MON,[118:118] sec_safety_disable_mon" "0,1" bitfld.long 0xC 20.--21. "EFUSEC_MISC_CFG,[117:116] efusec_misc_cfg[117:116]" "0,1,2,3" bitfld.long 0xC 19. "GPU2_DBG_DISABLE_MON,[115:115] gpu2_dbg_disable_mon" "0,1" newline bitfld.long 0xC 18. "GPU1_DBG_DISABLE_MON,[114:114] gpu1_dbg_disable_mon" "0,1" bitfld.long 0xC 17. "ADSP_DBG_DISABLE_MON,[113:113] adsp_dbg_disable_mon" "0,1" bitfld.long 0xC 16. "VDSP_DBG_DISABLE_MON,[112:112] vdsp_dbg_disable_mon" "0,1" newline bitfld.long 0xC 15. "PARA_BOOT_DISABLE_MON,[111:111] para_boot_disable_mon" "0,1" bitfld.long 0xC 14. "EFUSEC_MISC_CFG,[110:110] efusec_misc_cfg[110]" "0,1" bitfld.long 0xC 13. "USER_MAC_DISABLE_MON,[109:109] user_mac_disable_mon" "0,1" newline bitfld.long 0xC 10.--12. "EFUSEC_MISC_CFG,[108:106] efusec_misc_cfg[108:106]" "0,1,2,3,4,5,6,7" bitfld.long 0xC 9. "PVT_SEC_SENS_EN_MON,[105:105] pvt_sec_sens_en_mon" "0,1" hexmask.long.word 0xC 0.--8. 1. "EFUSEC_MISC_CFG,[104:96] efusec_misc_cfg[104:96]" line.long 0x10 "SIG_MON_ENABLE_4,signal monitor enable" bitfld.long 0x10 31. "APBMUX2_BIPC_ENET1_SELECT,[159:159] apbmux2_bipc_enet1_select" "0,1" bitfld.long 0x10 30. "APBMUX2_PVT_SNS_SAF_SELECT,[158:158] apbmux2_pvt_sns_saf_select" "0,1" bitfld.long 0x10 29. "APBMUX2_PLL2_SELECT,[157:157] apbmux2_pll2_select" "0,1" newline bitfld.long 0x10 28. "APBMUX2_PLL1_SELECT,[156:156] apbmux2_pll1_select" "0,1" bitfld.long 0x10 27. "APBMUX2_RC_24M_SELECT,[155:155] apbmux2_rc_24m_select" "0,1" bitfld.long 0x10 26. "APBMUX2_DMA1_SELECT,[154:154] apbmux2_dma1_select" "0,1" newline bitfld.long 0x10 25. "APBMUX2_WDT1_SELECT,[153:153] apbmux2_wdt1_select" "0,1" bitfld.long 0x10 24. "APBMUX2_PWM2_SELECT,[152:152] apbmux2_pwm2_select" "0,1" bitfld.long 0x10 23. "APBMUX2_PWM1_SELECT,[151:151] apbmux2_pwm1_select" "0,1" newline bitfld.long 0x10 22. "APBMUX2_TIMER2_SELECT,[150:150] apbmux2_timer2_select" "0,1" bitfld.long 0x10 21. "APBMUX2_TIMER1_SELECT,[149:149] apbmux2_timer1_select" "0,1" bitfld.long 0x10 20. "APBMUX2_ENET1_SELECT,[148:148] apbmux2_enet1_select" "0,1" newline bitfld.long 0x10 19. "APBMUX2_UART8_SELECT,[147:147] apbmux2_uart8_select" "0,1" bitfld.long 0x10 18. "APBMUX2_UART7_SELECT,[146:146] apbmux2_uart7_select" "0,1" bitfld.long 0x10 17. "APBMUX2_UART6_SELECT,[145:145] apbmux2_uart6_select" "0,1" newline bitfld.long 0x10 16. "APBMUX2_UART5_SELECT,[144:144] apbmux2_uart5_select" "0,1" bitfld.long 0x10 15. "APBMUX2_UART4_SELECT,[143:143] apbmux2_uart4_select" "0,1" bitfld.long 0x10 14. "APBMUX2_UART3_SELECT,[142:142] apbmux2_uart3_select" "0,1" newline bitfld.long 0x10 13. "APBMUX2_UART2_SELECT,[141:141] apbmux2_uart2_select" "0,1" bitfld.long 0x10 12. "APBMUX2_UART1_SELECT,[140:140] apbmux2_uart1_select" "0,1" bitfld.long 0x10 11. "APBMUX2_I2C4_SELECT,[139:139] apbmux2_i2c4_select" "0,1" newline bitfld.long 0x10 10. "APBMUX2_I2C3_SELECT,[138:138] apbmux2_i2c3_select" "0,1" bitfld.long 0x10 9. "APBMUX2_I2C2_SELECT,[137:137] apbmux2_i2c2_select" "0,1" bitfld.long 0x10 8. "APBMUX2_I2C1_SELECT,[136:136] apbmux2_i2c1_select" "0,1" newline bitfld.long 0x10 7. "APBMUX2_CANFD4_SELECT,[135:135] apbmux2_canfd4_select" "0,1" bitfld.long 0x10 6. "APBMUX2_CANFD3_SELECT,[134:134] apbmux2_canfd3_select" "0,1" bitfld.long 0x10 5. "APBMUX2_CANFD2_SELECT,[133:133] apbmux2_canfd2_select" "0,1" newline bitfld.long 0x10 4. "APBMUX2_CANFD1_SELECT,[132:132] apbmux2_canfd1_select" "0,1" bitfld.long 0x10 3. "APBMUX2_OSPI1_SELECT,[131:131] apbmux2_ospi1_select" "0,1" bitfld.long 0x10 2. "APBMUX2_PWRCTRL_SELECT,[130:130] apbmux2_pwrctrl_select" "0,1" newline bitfld.long 0x10 1. "APBMUX2_CE1_SELECT,[129:129] apbmux2_ce1_select" "0,1" bitfld.long 0x10 0. "APBMUX2_SEM1_SELECT,[128:128] apbmux2_sem1_select" "0,1" line.long 0x14 "SIG_MON_ENABLE_5,signal monitor enable" bitfld.long 0x14 23. "APBMUX2_SEC_STORAGE2_SELECT,[183:183] apbmux2_sec_storage2_select" "0,1" bitfld.long 0x14 22. "APBMUX2_SEC_STORAGE1_SELECT,[182:182] apbmux2_sec_storage1_select" "0,1" bitfld.long 0x14 21. "APBMUX2_RSTGEN_RTC_SELECT,[181:181] apbmux2_rstgen_rtc_select" "0,1" newline bitfld.long 0x14 20. "APBMUX2_PMU_SELECT,[180:180] apbmux2_pmu_select" "0,1" bitfld.long 0x14 19. "APBMUX2_RTC2_SELECT,[179:179] apbmux2_rtc2_select" "0,1" bitfld.long 0x14 18. "APBMUX2_RTC1_SELECT,[178:178] apbmux2_rtc1_select" "0,1" newline bitfld.long 0x14 17. "APBMUX2_XTAL_RTC_SELECT,[177:177] apbmux2_xtal_rtc_select" "0,1" bitfld.long 0x14 16. "APBMUX2_IOMUX_CTRL_RTC_SELECT,[176:176] apbmux2_iomux_ctrl_rtc_select" "0,1" bitfld.long 0x14 15. "APBMUX2_RC_RTC_SELECT,[175:175] apbmux2_rc_rtc_select" "0,1" newline bitfld.long 0x14 14. "APBMUX2_TM_SELECT,[174:174] apbmux2_tm_select" "0,1" bitfld.long 0x14 13. "AXISLVMUX_CE1_SELECT,[173:173] axislvmux_ce1_select" "0,1" bitfld.long 0x14 12. "AXISLVMUX_DMA1_SELECT,[172:172] axislvmux_dma1_select" "0,1" newline bitfld.long 0x14 11. "AXISLVMUX_OSPI1_SELECT,[171:171] axislvmux_ospi1_select" "0,1" bitfld.long 0x14 10. "AXISLVMUX_IRAM1_SELECT,[170:170] axislvmux_iram1_select" "0,1" bitfld.long 0x14 9. "APBMUX2_EIC_SAFE_SELECT,[169:169] apbmux2_eic_safe_select" "0,1" newline bitfld.long 0x14 8. "APBMUX2_XTAL_SAF_SELECT,[168:168] apbmux2_xtal_saf_select" "0,1" bitfld.long 0x14 7. "APBMUX2_RPC_SAF_SELECT,[167:167] apbmux2_rpc_saf_select" "0,1" bitfld.long 0x14 6. "APBMUX2_SPI4_SELECT,[166:166] apbmux2_spi4_select" "0,1" newline bitfld.long 0x14 5. "APBMUX2_SPI3_SELECT,[165:165] apbmux2_spi3_select" "0,1" bitfld.long 0x14 4. "APBMUX2_SPI2_SELECT,[164:164] apbmux2_spi2_select" "0,1" bitfld.long 0x14 3. "APBMUX2_SPI1_SELECT,[163:163] apbmux2_spi1_select" "0,1" newline bitfld.long 0x14 2. "APBMUX2_IRAM1_SELECT,[162:162] apbmux2_iram1_select" "0,1" bitfld.long 0x14 1. "APBMUX2_I2S_SC2_SELECT,[161:161] apbmux2_i2s_sc2_select" "0,1" bitfld.long 0x14 0. "APBMUX2_I2S_SC1_SELECT,[160:160] apbmux2_i2s_sc1_select" "0,1" tree.end tree.end repeat.end elif (CORENAME()=="CORTEXA55") repeat 2. (increment 1. 1.) (list ad:0x30320000 ad:0x30330000) tree "SEM$1" base $2 tree "AB0 (Address Block 0 of sem)" group.long 0x0++0xB line.long 0x0 "SEM_COMMON_SET,SEM common settings" hexmask.long.byte 0x0 24.--31. 1. "CMP_ENABLE,compare output enable bits for int0-7" bitfld.long 0x0 23. "SIG_MON_GLB_EN,signal monitor global enable" "0,1" bitfld.long 0x0 17. "EI_GLOBAL_EN_LOCK,Error Injection Global Enable Lock bit" "0,1" newline bitfld.long 0x0 16. "EI_GLOBAL_EN,Error Injection Global Enable" "0,1" hexmask.long.byte 0x0 12.--15. 1. "ERROR_DIV,error divider ratio for waveform A" bitfld.long 0x0 11. "ERROR_WAVE_SEL,waveform A/B selection for normal/recoverable error" "0,1" bitfld.long 0x0 10. "FATAL_HIGH_LOW,fatal error High or Low selection" "0,1" newline bitfld.long 0x0 8.--9. "SEM_INT_DC4_SEL,SEM_INT DC4 selection" "0,1,2,3" bitfld.long 0x0 6.--7. "SEM_INT_DC3_SEL,SEM_INT DC3 selection" "0,1,2,3" bitfld.long 0x0 4.--5. "SEM_INT_DC2_SEL,SEM_INT DC2 selection" "0,1,2,3" bitfld.long 0x0 2.--3. "SEM_INT_DC1_SEL,SEM_INT DC1 selection" "0,1,2,3" newline bitfld.long 0x0 0.--1. "SEM_INT_DC0_SEL,SEM_INT DC0 selection" "0,1,2,3" line.long 0x4 "INT_TRIG,int0-7 trigger" hexmask.long.byte 0x4 0.--7. 1. "INT_TRIG,int0-int7 trigger" line.long 0x8 "INT_ENABLE_OVRD,int0-7 enable override" hexmask.long.byte 0x8 8.--15. 1. "INT_ENABLE_OVRD_VAL,int0-7 enable override value" hexmask.long.byte 0x8 0.--7. 1. "INT_ENABLE_OVRD_EN,int0-7 enable override enable" group.long 0x10++0x3 line.long 0x0 "IO_WAVE_CTRL,IO_WAVE_CTRL" bitfld.long 0x0 31. "LOCK,LOCK ctrl" "0,1" bitfld.long 0x0 2.--3. "LEVEL_CFG,the level io when normal [2] and recoverable err[3] take place" "0,1,2,3" bitfld.long 0x0 0.--1. "LEVEL_EN,if set the normal and recoverable output will be set as level [0] normal [1] recover case" "0,1,2,3" repeat 10. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 )(list 0x0 0x4 0x8 0xC 0x10 0x14 0x18 0x1C 0x20 0x24 ) rgroup.long ($2+0x80)++0x3 line.long 0x0 "INT_STATUS$1,interrupt status" hexmask.long 0x0 0.--31. 1. "INT_STATUS0,Interrupt status" repeat.end repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x4 0x8 0xC 0x10 0x14 0x18 0x1C 0x20 0x24 0x80 0x84 0x88 0x8C 0x90 0x94 ) group.long ($2+0x100)++0x3 line.long 0x0 "INT_ENABLE_$1,interrupt enable for int_0" hexmask.long 0x0 0.--31. 1. "INT_ENABLE_00,interrupt enable for int0" repeat.end repeat 16. (list 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1A 0x1B 0x1C 0x1D 0x1E 0x1F )(list 0x98 0x9C 0xA0 0xA4 0x100 0x104 0x108 0x10C 0x110 0x114 0x118 0x11C 0x120 0x124 0x180 0x184 ) group.long ($2+0x100)++0x3 line.long 0x0 "INT_ENABLE_$1,interrupt enable for int_0" hexmask.long 0x0 0.--31. 1. "INT_ENABLE_00,interrupt enable for int0" repeat.end repeat 16. (list 0x20 0x21 0x22 0x23 0x24 0x25 0x26 0x27 0x28 0x29 0x2A 0x2B 0x2C 0x2D 0x2E 0x2F )(list 0x188 0x18C 0x190 0x194 0x198 0x19C 0x1A0 0x1A4 0x200 0x204 0x208 0x20C 0x210 0x214 0x218 0x21C ) group.long ($2+0x100)++0x3 line.long 0x0 "INT_ENABLE_$1,interrupt enable for int_0" hexmask.long 0x0 0.--31. 1. "INT_ENABLE_00,interrupt enable for int0" repeat.end repeat 16. (list 0x30 0x31 0x32 0x33 0x34 0x35 0x36 0x37 0x38 0x39 0x3A 0x3B 0x3C 0x3D 0x3E 0x3F )(list 0x220 0x224 0x280 0x284 0x288 0x28C 0x290 0x294 0x298 0x29C 0x2A0 0x2A4 0x300 0x304 0x308 0x30C ) group.long ($2+0x100)++0x3 line.long 0x0 "INT_ENABLE_$1,interrupt enable for int_0" hexmask.long 0x0 0.--31. 1. "INT_ENABLE_00,interrupt enable for int0" repeat.end repeat 16. (list 0x40 0x41 0x42 0x43 0x44 0x45 0x46 0x47 0x48 0x49 0x4A 0x4B 0x4C 0x4D 0x4E 0x4F )(list 0x310 0x314 0x318 0x31C 0x320 0x324 0x380 0x384 0x388 0x38C 0x390 0x394 0x398 0x39C 0x3A0 0x3A4 ) group.long ($2+0x100)++0x3 line.long 0x0 "INT_ENABLE_$1,interrupt enable for int_0" hexmask.long 0x0 0.--31. 1. "INT_ENABLE_00,interrupt enable for int0" repeat.end repeat 6. (list 0x0 0x1 0x2 0x3 0x4 0x5 )(list 0x0 0x4 0x8 0xC 0x10 0x14 ) group.long ($2+0x500)++0x3 line.long 0x0 "TGT_VALUE$1,target value" hexmask.long 0x0 0.--31. 1. "TGT_VALUE0,monitor target value" repeat.end repeat 6. (list 0x0 0x1 0x2 0x3 0x4 0x5 )(list 0x0 0x4 0x8 0xC 0x10 0x14 ) group.long ($2+0x580)++0x3 line.long 0x0 "SIG_MON_ENABLE$1,signal monitor enable" hexmask.long 0x0 0.--31. 1. "SIG_MON_ENABLE0,monitor enable" repeat.end tree.end tree "ABT (Address Block 0 of sem)" group.long 0x0++0x3 line.long 0x0 "CE0_STAT,1 the CIPHER of CE0 is busy" hexmask.long.byte 0x0 24.--31. 1. "CMP_ENABLE,compare output enable bits for int0-7" newline bitfld.long 0x0 23. "SIG_MON_GLB_EN,signal monitor global enable" "0,1" newline bitfld.long 0x0 17. "EI_GLOBAL_EN_LOCK,Error Injection Global Enable Lock bit" "0,1" newline hexmask.long.word 0x0 16.--31. 1. "RESERVED,1 the CIPHER of CE0 is busy" newline bitfld.long 0x0 16. "EI_GLOBAL_EN,Error Injection Global Enable" "0,1" newline hexmask.long.byte 0x0 8.--15. 1. "RESERVED,CE0 error status one bit indicate one type of error" newline bitfld.long 0x0 6.--7. "RESERVED,1: the DMA operation of ce0 has error 0: the DMA of CE0 has no error" "the DMA of CE0 has no error,the DMA operation of ce0 has error,?,?" newline rbitfld.long 0x0 5. "PKE_BUSY,1: PKE is busy 0:PKE is idle" "?,PKE is busy 0:PKE is idle" newline rbitfld.long 0x0 4. "GENKEY_BUSY,1. CE0 generate key function is busy" "0,1" newline rbitfld.long 0x0 3. "HASH_BUSY,1: the HASH of CE0 is busy" "?,the HASH of CE0 is busy" newline rbitfld.long 0x0 2. "CIPHER_BUSY,1 the CIPHER of CE0 is busy" "0,1" newline rbitfld.long 0x0 1. "GETRNDNUM_BUSY,1: get random number function of CE0 is busy" "?,get random number function of CE0 is busy" newline rbitfld.long 0x0 0. "DMA_BUSY,1: the DMA of CE0 is busy 0: the DMA of CE0 is idle" "the DMA of CE0 is idle,the DMA of CE0 is busy" rgroup.long 0x4++0x3 line.long 0x0 "CE0_ERRSTAT,'the error status of hash sequencer the bit 0 ~ 3 are [sram_wr_err] [sram rd err] [rdma_err] [wdma err]'" hexmask.long.byte 0x0 24.--27. 1. "SKC_ERR_STAT,'the error status of skc sequencer the bit 0 ~ 3 are [sram wr err] [ rand number fetch err] [ secure violation occurs] [reserved]'" group.long 0x8++0x43 line.long 0x0 "INT_ENABLE_OVRD,int0-7 enable override" hexmask.long.byte 0x0 8.--15. 1. "INT_ENABLE_OVRD_VAL,int0-7 enable override value" newline hexmask.long.byte 0x0 0.--7. 1. "INT_ENABLE_OVRD_EN,int0-7 enable override enable" line.long 0x4 "CE0_CIPHER_CTRL,1 the header will be saved into dst memory 0: header will not be saved" bitfld.long 0x4 31. "CIPHER_HEADER_SAVE,1 the header will be saved into dst memory 0: header will not be saved" "header will not be saved,?" newline bitfld.long 0x4 28.--29. "CIPHER_KEY2TYPE,key 2 type 10: input keyport 00: secure sram public area 01: secure area others: reserved" "secure sram public area,secure area others: reserved,?,?" newline bitfld.long 0x4 25.--26. "CIPHER_KEYTYPE,key type 10: input keyport 00: secure sram public area 01: secure area others: reserved" "secure sram public area,secure area others: reserved,?,?" newline hexmask.long.word 0x4 16.--24. 1. "AESMODE,'AES mode XTS : 010000000 ECB : 000000001 CBC : 000000010 CTR : 000000100 CFB : 000001000 OFB : 000010000 CCM : 000100000 GCM : 001000000 XTS : 010000000 CMAC: 100000000'" newline bitfld.long 0x4 13. "CIPHER_SAVE,0: normal mode last part of the message 1: operation context will be saved at the end of operation" "normal mode last part of the message,operation context will be saved at the end of.." newline bitfld.long 0x4 12. "CIPHER_LOAD,0 : normal mode first start of the message 1: operation restart from previously save context" "normal mode first start of the message,operation restart from previously save context" newline bitfld.long 0x4 11. "CIPHER_DECKEYCAL,0 use the input key for decryption operations 1: use the pre-calculation of the key is done before" "?,use the pre-calculation of the key is done before" newline bitfld.long 0x4 9.--10. "CIPHER_KEYSIZE,key size 00: 128bit key 01: 256 bit key 10: 192bit key 11: reserved" "0,1,2,3" newline bitfld.long 0x4 8. "CIPHERMODE,0 encryption 1 decryption" "0,1" newline bitfld.long 0x4 0. "CIPHER_GO,'write 1 to this bit will start the cipher operation'" "0,1" line.long 0x8 "CE0_CIPHER_HEADER_LEN,'cipher data header length in bytes'" bitfld.long 0x8 31. "LOCK,LOCK ctrl" "0,1" newline bitfld.long 0x8 2.--3. "LEVEL_CFG,the level io when normal [2] and recoverable err[3] take place" "0,1,2,3" newline bitfld.long 0x8 0.--1. "LEVEL_EN,if set the normal and recoverable output will be set as level [0] normal [1] recover case" "0,1,2,3" newline hexmask.long 0x8 0.--31. 1. "CIPHER_HEADER_LEN,'cipher data header length in bytes'" line.long 0xC "CE0_CIPHER_KEY_ADDR,key2 address in secure SRAM or keyport" hexmask.long.word 0xC 16.--31. 1. "CIPHER_KEY2_ADDR,key2 address in secure SRAM or keyport" newline hexmask.long.word 0xC 0.--15. 1. "CIPHER_KEY_ADDR,CIPHER_KEY_ADDR address in secure SRAM or keyport" line.long 0x10 "CE0_CIPHER_SRC_ADDR,cipher data source address in bytes" hexmask.long 0x10 0.--31. 1. "CIPHER_SRC_ADDR,cipher data source address in bytes" line.long 0x14 "CE0_CIPHER_SRC_ADDR_H,011: CE SRAM Secure AREA 001:CE SRAM public area 000:external memories other: reserved" bitfld.long 0x14 8.--10. "CIPHER_SRC_TYPE,011: CE SRAM Secure AREA 001:CE SRAM public area 000:external memories other: reserved" "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x14 0.--7. 1. "CIPHER_SRC_ADDR_H,the high part of CE0 cipher source address" line.long 0x18 "CE0_CIPHER_DST_ADDR,CE0 cipher data destination address" hexmask.long 0x18 0.--31. 1. "CIPHER_DST_ADDR,CE0 cipher data destination address" line.long 0x1C "CE0_CIPHER_DST_ADDR_H,011: CE SRAM Secure AREA 001:CE SRAM public area 000:external memories other: reserved" bitfld.long 0x1C 8.--10. "CIPHER_DST_TYPE,011: CE SRAM Secure AREA 001:CE SRAM public area 000:external memories other: reserved" "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x1C 0.--7. 1. "CIPHER_DST_ADDR_H,CE0 cipher data destination address" line.long 0x20 "CE0_CIPHER_IV_CONTEXT_ADDR,CIPHER context storage address the context is always stored into SRAM secure area" hexmask.long.word 0x20 16.--31. 1. "CIPHER_CONTEXT_ADDR,CIPHER context storage address the context is always stored into SRAM secure area" newline hexmask.long.word 0x20 0.--15. 1. "CIPHER_IV_ADDR,CIPHER iv storage address the iv is always stored into SRAM secure area" line.long 0x24 "CE0_CIPHER_PAYLOAD_LEN,CIPHER_PAYLOAD_LEN including the header length in byte" hexmask.long 0x24 0.--31. 1. "CIPHER_PAYLOAD_LEN,CIPHER_PAYLOAD_LEN including the header length in byte" line.long 0x28 "CE0_HASH_CTRL,reserved" newline bitfld.long 0x28 24. "HASH_HMAC_EN,1: hmac is enabled 0: hmac is disabled" "hmac is disabled,hmac is enabled" newline bitfld.long 0x28 19. "HASH_KEY,1 need to load key 0 donot load key" "0,1" newline bitfld.long 0x28 18. "HASH_INIT_SECURE,1 load IV from secure area 0: load IV from public area" "load IV from public area,?" newline bitfld.long 0x28 17. "HASH_INIT,1 load IV for the hash 0 not load initial vector" "0,1" newline bitfld.long 0x28 16. "HASH_SHAUPDATE,0 final SHA224 output 7 words and SHA384 output 6 words 1: update SHA224/384 output 8 words please don't use this feature in hmac mode" "?,update SHA224/384 output 8 words please don't.." newline bitfld.long 0x28 15. "HASH_PADDINGEN,0: bypass padding logic 1: use hw padding logic" "bypass padding logic,use hw padding logic" newline hexmask.long.byte 0x28 8.--14. 1. "HASH_MODE,0000001 MD5 0000010 SHA1 0000100 SHA224 0001000 SHA256 0010000 SHA384 0100000 SHA512 1000000 SM3" newline bitfld.long 0x28 0. "HASH_GO,HASH Calculation start" "0,1" line.long 0x2C "CE0_HASH_KEYIV_ADDR,HASH initial vection address" hexmask.long.word 0x2C 16.--31. 1. "HASH_IV_ADDR,HASH initial vection address" line.long 0x30 "CE0_HMAC_KEY_CTRL,CE0 hash key length in CE SRAM" hexmask.long.word 0x30 16.--31. 1. "HMAC_KEY_LEN,CE0 hash key length in CE SRAM" line.long 0x34 "CE0_HASH_CALC_LEN,CE0 hash calculation length in bytes" hexmask.long 0x34 0.--31. 1. "HASH_CALC_LEN,CE0 hash calculation length in bytes" line.long 0x38 "CE0_HASH_SRC_ADDR,CE0 HASH SRC ADDR" hexmask.long 0x38 0.--31. 1. "HASH_SRC_ADDR,CE0 HASH SRC ADDR" line.long 0x3C "CE0_HASH_SRC_ADDR_H,000: external memory 001: CE SRAM public area 011 CE sram secure area 1xx: SKC key interface space" bitfld.long 0x3C 8.--10. "HASH_SRC_TYPE,000: external memory 001: CE SRAM public area 011 CE sram secure area 1xx: SKC key interface space" "external memory,CE SRAM public area 011 CE sram secure area 1xx:..,?,?,?,?,?,?" newline hexmask.long.byte 0x3C 0.--7. 1. "HASH_SRC_ADDR_H,the high part of CE0 hash src address" line.long 0x40 "CE0_HASH_DST_ADDR,the dst address in secure SRAM" hexmask.long.word 0x40 16.--31. 1. "HASH_DST_ADDR,the dst address in secure SRAM" wgroup.long 0x50++0x3 line.long 0x0 "CE0_DMA_CTRL,write 1 to this register start CE0 DMA operation" bitfld.long 0x0 11. "DMA_GO,write 1 to this register start CE0 DMA operation" "0,1" group.long 0x54++0x13 line.long 0x0 "CE0_DMA_SRC_ADDR,CE0 dma source addr" hexmask.long 0x0 0.--31. 1. "DMA_SRC_ADDR,CE0 dma source addr" line.long 0x4 "CE0_DMA_SRC_ADDR_H,011: CE SRAM Secure AREA 001:CE SRAM public area 000:external memories other: reserved" bitfld.long 0x4 8.--10. "DMA_SRC_TYPE,011: CE SRAM Secure AREA 001:CE SRAM public area 000:external memories other: reserved" "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0x4 0.--7. 1. "DMA_SRC_ADDR_H,CE0 dma source addr high part" line.long 0x8 "CE0_DMA_DST_ADDR,CE1 DMA DST ADDR" hexmask.long 0x8 0.--31. 1. "DMA_DST_ADDR,CE1 DMA DST ADDR" line.long 0xC "CE0_DMA_DST_ADDR_H,011: CE SRAM Secure AREA 001:CE SRAM public area 000:external memories other: reserved" bitfld.long 0xC 8.--10. "DMA_DST_TYPE,011: CE SRAM Secure AREA 001:CE SRAM public area 000:external memories other: reserved" "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0xC 0.--7. 1. "DMA_DST_ADDR_H,CE1 DMA DST ADDR high part" line.long 0x10 "CE0_DMA_LEN,DMA transfer length in byte" hexmask.long.word 0x10 0.--15. 1. "DMA_LEN,DMA transfer length in byte" group.long 0x80++0xB line.long 0x0 "CE0_PK_POINTERREG,'unused'" rbitfld.long 0x0 31. "CANFD6_IPI_INT_CE,ipi_int_ce from CANFD6 Correctable error interrupt" "0,1" newline rbitfld.long 0x0 30. "CANFD5_IPI_INT_NCEFA,ipi_int_ncefa from CANFD5 Non correctable error int internal" "0,1" newline rbitfld.long 0x0 29. "CANFD5_IPI_INT_NCEHA,ipi_int_nceha from CANFD5 Non correctable error int host" "0,1" newline hexmask.long.byte 0x0 28.--31. 1. "RESERVED,'unused'" newline rbitfld.long 0x0 28. "CANFD5_IPI_INT_CE,ipi_int_ce from CANFD5 Correctable error interrupt" "0,1" newline hexmask.long.byte 0x0 24.--27. 1. "PK_OPPTRN,'When executing primitive arithmetic operations" newline hexmask.long.byte 0x0 20.--23. 1. "RESERVED,'unused'" newline hexmask.long.byte 0x0 16.--19. 1. "PK_OPPTRC,'When executing primitive arithmetic operations" newline hexmask.long.byte 0x0 12.--15. 1. "RESERVED,'unused'" newline hexmask.long.byte 0x0 8.--11. 1. "PK_OPPTRB,'When executing primitive arithmetic operations" newline hexmask.long.byte 0x0 4.--7. 1. "RESERVED,'unused'" newline hexmask.long.byte 0x0 0.--3. 1. "PK_OPPTRA,'When executing primitive arithmetic operations" line.long 0x4 "CE0_PK_COMMANDREG,PK_CALCR2" rbitfld.long 0x4 31. "CANFD6_IPI_INT_NCEFA,ipi_int_nceha from CANFD6 Non correctable error int host" "0,1" newline rbitfld.long 0x4 30. "NOC_SEC_S_13_MAINSGLDATAECCERR,s_13_mainSglDataEccErr from NOC_SEC None" "0,1" newline rbitfld.long 0x4 29. "NOC_SEC_S_3_MAINSGLDATAECCERR,s_3_mainSglDataEccErr from NOC_SEC None" "0,1" newline rbitfld.long 0x4 28. "NOC_SEC_S_2_MAINSGLDATAECCERR,s_2_mainSglDataEccErr from NOC_SEC None" "0,1" newline rbitfld.long 0x4 27. "NOC_SEC_S_1_MAINSGLECCERR,s_1_mainSglEccErr from NOC_SEC None" "0,1" newline rbitfld.long 0x4 26. "NOC_SEC_S_0_MAINSGLECCERR,s_0_mainSglEccErr from NOC_SEC None" "0,1" newline rbitfld.long 0x4 25. "NOC_SEC_M_9_I_MAININITIATOR_TIMEOUT_FAULT,m_9_I_mainInitiator_Timeout_Fault from NOC_SEC None" "0,1" newline rbitfld.long 0x4 24. "NOC_SEC_M_8_I_MAININITIATOR_TIMEOUT_FAULT,m_8_I_mainInitiator_Timeout_Fault from NOC_SEC None" "0,1" newline rbitfld.long 0x4 23. "NOC_SEC_M_7_I_MAININITIATOR_TIMEOUT_FAULT,m_7_I_mainInitiator_Timeout_Fault from NOC_SEC None" "0,1" newline rbitfld.long 0x4 22. "NOC_SEC_M_6_I_MAININITIATOR_TIMEOUT_FAULT,m_6_I_mainInitiator_Timeout_Fault from NOC_SEC None" "0,1" newline rbitfld.long 0x4 21. "NOC_SEC_M_5_I_MAININITIATOR_TIMEOUT_FAULT,m_5_I_mainInitiator_Timeout_Fault from NOC_SEC None" "0,1" newline rbitfld.long 0x4 20. "NOC_SEC_M_5_MAINSGLDATAECCERR,m_5_mainSglDataEccErr from NOC_SEC None" "0,1" newline hexmask.long.byte 0x4 20.--23. 1. "PK_SELCURVE,'Enable accelerator for specific curve modulus: 0x0: No acceleration (default) 0x1: P256 0x2: P384 0x3: P521/E-521 0x4: P192 0x5: Curve25519/Ed25519 This field has no effect when the optional acceleration hardware is not included.'" newline hexmask.long.word 0x4 8.--18. 1. "PK_SIZE,'Of Operands (in data memory) This field defines the size (= number of bytes minus one) of the operands for the current operation. Possible values are limited by the maximum supported operand size. Examples: 0x014 -> ECC on curve K-163 0x01F ->.." newline bitfld.long 0x4 7. "PK_FIELD,''0': Field is GF(p) '1': Field is GF(2m)'" "0,1" newline hexmask.long.byte 0x4 0.--6. 1. "PK_TYPE,'of operation This field defines the operation to be performed. See table below for details.'" line.long 0x8 "CE0_PKE_CTRL,'Writing a 1 to this bit will reset the pke_seq logic'" rbitfld.long 0x8 31. "NOC_VSN_PD_VSN_MAINLATENTINT,s_17_mainSglDataEccErr from NOC_SEC None" "0,1" newline rbitfld.long 0x8 30. "NOC_MAIN_M_17_I_MAININITIATOR_TIMEOUT_FAULT,m_17_I_mainInitiator_Timeout_Fault from NOC_MAIN None" "0,1" newline rbitfld.long 0x8 29. "NOC_MAIN_M_14_I_MAININITIATOR_TIMEOUT_FAULT,m_14_I_mainInitiator_Timeout_Fault from NOC_MAIN None" "0,1" newline rbitfld.long 0x8 28. "NOC_MAIN_M_13_I_MAININITIATOR_TIMEOUT_FAULT,m_13_I_mainInitiator_Timeout_Fault from NOC_MAIN None" "0,1" newline rbitfld.long 0x8 27. "NOC_MAIN_M_12_I_MAININITIATOR_TIMEOUT_FAULT,m_12_I_mainInitiator_Timeout_Fault from NOC_MAIN None" "0,1" newline rbitfld.long 0x8 26. "NOC_MAIN_M_12_MAINSGLARADDRECCERR,m_12_mainSglArAddrEccErr from NOC_MAIN None OR m_12_mainSglAwAddrEccErr from NOC_MAIN None OR m_12_mainSglDataEccErr from NOC_MAIN None" "0,1" newline rbitfld.long 0x8 25. "NOC_MAIN_M_11_I_MAININITIATOR_TIMEOUT_FAULT,m_11_I_mainInitiator_Timeout_Fault from NOC_MAIN None" "0,1" newline rbitfld.long 0x8 24. "NOC_MAIN_M_11_MAINSGLARADDRECCERR,m_11_mainSglArAddrEccErr from NOC_MAIN None OR m_11_mainSglAwAddrEccErr from NOC_MAIN None OR m_11_mainSglDataEccErr from NOC_MAIN None" "0,1" newline rbitfld.long 0x8 23. "NOC_MAIN_M_10_I_MAININITIATOR_TIMEOUT_FAULT,m_10_I_mainInitiator_Timeout_Fault from NOC_MAIN None" "0,1" newline rbitfld.long 0x8 22. "NOC_MAIN_M_9_I_MAININITIATOR_TIMEOUT_FAULT,m_9_I_mainInitiator_Timeout_Fault from NOC_MAIN None" "0,1" newline rbitfld.long 0x8 21. "NOC_MAIN_M_8_I_MAININITIATOR_TIMEOUT_FAULT,m_8_I_mainInitiator_Timeout_Fault from NOC_MAIN None" "0,1" newline rbitfld.long 0x8 20. "NOC_MAIN_M_7_I_MAININITIATOR_TIMEOUT_FAULT,m_7_I_mainInitiator_Timeout_Fault from NOC_MAIN None" "0,1" newline rbitfld.long 0x8 19. "NOC_MAIN_M_6_I_MAININITIATOR_TIMEOUT_FAULT,m_6_I_mainInitiator_Timeout_Fault from NOC_MAIN None" "0,1" newline rbitfld.long 0x8 18. "NOC_MAIN_M_5_I_MAININITIATOR_TIMEOUT_FAULT,m_5_I_mainInitiator_Timeout_Fault from NOC_MAIN None" "0,1" newline rbitfld.long 0x8 17. "NOC_MAIN_M_4_I_MAININITIATOR_TIMEOUT_FAULT,m_4_I_mainInitiator_Timeout_Fault from NOC_MAIN None" "0,1" newline rbitfld.long 0x8 16. "NOC_MAIN_M_3_I_MAININITIATOR_TIMEOUT_FAULT,m_3_I_mainInitiator_Timeout_Fault from NOC_MAIN None" "0,1" newline rbitfld.long 0x8 15. "NOC_MAIN_M_2_I_MAININITIATOR_TIMEOUT_FAULT,m_2_I_mainInitiator_Timeout_Fault from NOC_MAIN None" "0,1" newline rbitfld.long 0x8 14. "NOC_MAIN_M_1_I_MAININITIATOR_TIMEOUT_FAULT,m_1_I_mainInitiator_Timeout_Fault from NOC_MAIN None" "0,1" newline rbitfld.long 0x8 13. "NOC_MAIN_M_0_I_MAININITIATOR_TIMEOUT_FAULT,m_0_I_mainInitiator_Timeout_Fault from NOC_MAIN None" "0,1" newline rbitfld.long 0x8 12. "NOC_MAIN_SOC_MAINMISSIONINT,SOC_mainMissionInt from NOC_MAIN None OR ~SOC_mainMissionIntBar from NOC_MAIN None" "0,1" newline rbitfld.long 0x8 11. "NOC_MAIN_SOC_MAINLATENTINT,SOC_mainLatentInt from NOC_MAIN None OR ~SOC_mainLatentIntBar from NOC_MAIN None" "0,1" newline rbitfld.long 0x8 10. "NOC_VSN_S_3_MAINSGLDATAECCERR,s_3_mainSglDataEccErr from NOC_VSN None" "0,1" newline rbitfld.long 0x8 9. "NOC_VSN_S_0_MAINSGLDATAECCERR,s_0_mainSglDataEccErr from NOC_VSN None OR PFaultInfoValid from VDSP None" "0,1" newline rbitfld.long 0x8 8. "NOC_VSN_M_2_I_MAININITIATOR_TIMEOUT_FAULT,m_2_I_mainInitiator_Timeout_Fault from NOC_VSN None" "0,1" newline rbitfld.long 0x8 7. "NOC_VSN_M_2_MAINSGLARADDRECCERR,m_2_mainSglArAddrEccErr from NOC_VSN None OR m_2_mainSglAwAddrEccErr from NOC_VSN None OR m_2_mainSglDataEccErr from NOC_VSN None" "0,1" newline rbitfld.long 0x8 6. "NOC_VSN_M_1_I_MAININITIATOR_TIMEOUT_FAULT,m_1_I_mainInitiator_Timeout_Fault from NOC_VSN None" "0,1" newline rbitfld.long 0x8 5. "NOC_VSN_M_1_MAINSGLARADDRECCERR,m_1_mainSglArAddrEccErr from NOC_VSN None OR m_1_mainSglAwAddrEccErr from NOC_VSN None OR m_1_mainSglDataEccErr from NOC_VSN None" "0,1" newline rbitfld.long 0x8 4. "NOC_VSN_M_0_I_MAININITIATOR_TIMEOUT_FAULT,m_0_I_mainInitiator_Timeout_Fault from NOC_VSN None" "0,1" newline rbitfld.long 0x8 3. "NOC_VSN_M_0_MAINSGLARADDRECCERR,m_0_mainSglArAddrEccErr from NOC_VSN None OR m_0_mainSglAwAddrEccErr from NOC_VSN None OR m_0_mainSglDataEccErr from NOC_VSN None" "0,1" newline rbitfld.long 0x8 2. "NOC_VSN_PD_VSN_MAINMISSIONINT,PD_VSN_mainMissionInt from NOC_VSN None OR ~PD_VSN_mainMissionIntBar from NOC_VSN None" "0,1" newline rbitfld.long 0x8 1. "NOC_VSN_PD_VSN_MAINLATENTINT,PD_VSN_mainLatentInt from NOC_VSN None OR ~PD_VSN_mainLatentIntBar from NOC_VSN None" "0,1" newline bitfld.long 0x8 0. "PKE_GO,'Writing a '1' starts the processing.'" "0,1" rgroup.long 0x8C++0x7 line.long 0x0 "CE0_PK_STATUSREG,'unused'" bitfld.long 0x0 31. "NOC_MAIN_M_20_I_MAININITIATOR_TIMEOUT_FAULT,m_19_I_mainInitiator_Timeout_Fault from NOC_MAIN None" "0,1" newline bitfld.long 0x0 30. "NOC_SAF_M_5_I_MAININITIATOR_TIMEOUT_FAULT,m_5_I_mainInitiator_Timeout_Fault from NOC_SAF None" "0,1" newline bitfld.long 0x0 29. "NOC_SAF_M_4_I_MAININITIATOR_TIMEOUT_FAULT,m_4_I_mainInitiator_Timeout_Fault from NOC_SAF None" "0,1" newline bitfld.long 0x0 28. "NOC_SAF_M_4_MAINDUPL_SGLARADDRECCERR,m_4_mainDupl_SglArAddrEccErr from NOC_SAF None OR m_4_mainDupl_SglAwAddrEccErr from NOC_SAF None OR m_4_mainDupl_SglDataEccErr from NOC_SAF None" "0,1" newline bitfld.long 0x0 27. "NOC_SAF_M_4_MAINMAIN_SGLARADDRECCERR,m_4_mainMain_SglArAddrEccErr from NOC_SAF None OR m_4_mainMain_SglAwAddrEccErr from NOC_SAF None OR m_4_mainMain_SglDataEccErr from NOC_SAF None" "0,1" newline bitfld.long 0x0 26. "NOC_SAF_M_3_I_MAININITIATOR_TIMEOUT_FAULT,m_3_I_mainInitiator_Timeout_Fault from NOC_SAF None" "0,1" newline bitfld.long 0x0 25. "NOC_SAF_M_2_I_MAININITIATOR_TIMEOUT_FAULT,m_2_I_mainInitiator_Timeout_Fault from NOC_SAF None" "0,1" newline bitfld.long 0x0 24. "NOC_SAF_M_1_I_MAININITIATOR_TIMEOUT_FAULT,m_1_I_mainInitiator_Timeout_Fault from NOC_SAF None" "0,1" newline bitfld.long 0x0 23. "NOC_SAF_M_1_MAINMAIN_SGLECCERR,m_1_mainMain_SglEccErr from NOC_SAF None" "0,1" newline bitfld.long 0x0 22. "NOC_SAF_M_1_MAINDUPL_SGLECCERR,m_1_mainDupl_SglEccErr from NOC_SAF None" "0,1" newline bitfld.long 0x0 21. "NOC_SAF_M_0_I_MAININITIATOR_TIMEOUT_FAULT,m_0_I_mainInitiator_Timeout_Fault from NOC_SAF None" "0,1" newline bitfld.long 0x0 20. "NOC_SAF_M_0_MAINMAIN_SGLECCERR,m_0_mainMain_SglEccErr from NOC_SAF None" "0,1" newline bitfld.long 0x0 19. "NOC_SAF_M_0_MAINDUPL_SGLECCERR,m_0_mainDupl_SglEccErr from NOC_SAF None" "0,1" newline bitfld.long 0x0 18. "NOC_SAF_PD_SAF_MAINMISSIONINT,PD_SAF_mainMissionInt from NOC_SAF None OR ~PD_SAF_mainMissionIntBar from NOC_SAF None" "0,1" newline hexmask.long.word 0x0 18.--31. 1. "RESERVED,'unused'" newline bitfld.long 0x0 17. "PK_INTERRUPT,'status This bit reflects the IRQ output value. It is set to '1' when the operation is finished. It is cleared when the CPU writes the bit 1 of Control Register.'" "0,1" newline bitfld.long 0x0 16. "PK_BUSY,'This bit reflects the BUSY output value. It is set to '1' when the operation starts and it is cleared when the operation is finished.'" "0,1" newline bitfld.long 0x0 14.--15. "RESERVED,'unused'" "0,1,2,3" newline bitfld.long 0x0 13. "PK_NOTQUADRATICRESIDUE,PK_NOTQUADRATICRESIDUE" "0,1" newline bitfld.long 0x0 12. "PK_COMPOSITE,PK_COMPOSITE" "0,1" newline bitfld.long 0x0 11. "PK_NOTINVERTIBLE,PK_NOTINVERTIBLE" "0,1" newline bitfld.long 0x0 10. "PK_PARAM_AB_NOTVALID,PK_PARAM_AB_NOTVALID" "0,1" newline bitfld.long 0x0 9. "PK_SIGNATURE_NOTVALID,PK_SIGNATURE_NOTVALID" "0,1" newline bitfld.long 0x0 8. "PK_NOTIMPLEMENTED,PK_NOTIMPLEMENTED" "0,1" newline bitfld.long 0x0 7. "PK_PARAM_N_NOTVALID,PK_PARAM_N_NOTVALID" "0,1" newline bitfld.long 0x0 6. "PK_COUPLE_NOTVALID,PK_COUPLE_NOTVALID" "0,1" newline bitfld.long 0x0 5. "PK_POINT_PX_ATINFINITY,PK_POINT_PX_ATINFINITY" "0,1" newline bitfld.long 0x0 4. "PK_POINT_PX_NOTONCURVE,PK_POINT_PX_NOTONCURVE" "0,1" newline hexmask.long.byte 0x0 0.--3. 1. "PK_FAIL_ADDRESS,'These bits indicate which data location generated the error flag. They are not available for all error flags.'" line.long 0x4 "INT_STATUS4,crc32_irq from DC2 None" bitfld.long 0x4 31. "NOC_SAF_S_0_MAINMAIN_SGLECCERR,s_0_mainDupl_SglEccErr from NOC_SAF None" "0,1" newline bitfld.long 0x4 30. "DC2_DC_CH_UNDERRUN,dc_ch_underrun from DC2 None" "0,1" newline bitfld.long 0x4 29. "DC1_CRC32_IRQ,crc32_irq from DC1 None" "0,1" newline bitfld.long 0x4 28. "DC1_DC_CH_UNDERRUN,dc_ch_underrun from DC1 None" "0,1" newline bitfld.long 0x4 27. "DDR_SS_DDR_SS_FUNC_SAF_NONFATL_INT,ddr_ss_func_saf_nonfatl_int from DDR_SS None" "0,1" newline bitfld.long 0x4 26. "DDR_SS_DDR_SS_FUNC_SAF_FATL_INT,ddr_ss_func_saf_fatl_int from DDR_SS None" "0,1" newline bitfld.long 0x4 25. "BIPC_ENET1_ECC_ERR_MULTIPLE,ecc_err_multiple from BIPC_ENET1 None" "0,1" newline bitfld.long 0x4 24. "BIPC_ENET1_ECC_ERR_SINGLE,ecc_err_single from BIPC_ENET1 None" "0,1" newline bitfld.long 0x4 23. "BIPC_VDSP_ECC_ERR_MULTIPLE,ecc_err_multiple from BIPC_VDSP None" "0,1" newline bitfld.long 0x4 22. "BIPC_VDSP_ECC_ERR_SINGLE,ecc_err_single from BIPC_VDSP None" "0,1" newline bitfld.long 0x4 21. "BIPC_DDR_ECC_ERR_MULTIPLE,ecc_err_multiple from BIPC_DDR None" "0,1" newline bitfld.long 0x4 20. "BIPC_DDR_ECC_ERR_SINGLE,ecc_err_single from BIPC_DDR None" "0,1" newline bitfld.long 0x4 19. "MPC_DDR_UNC_ERR_INT,unc_err_int from MPC_DDR None" "0,1" newline bitfld.long 0x4 18. "MPC_DDR_COR_ERR_INT,cor_err_int from MPC_DDR None" "0,1" newline bitfld.long 0x4 17. "MPC_ROMC2_UNC_ERR_INT,unc_err_int from MPC_ROMC2 None" "0,1" newline bitfld.long 0x4 16. "MPC_ROMC2_COR_ERR_INT,cor_err_int from MPC_ROMC2 None" "0,1" newline bitfld.long 0x4 15. "MPC_IRAM4_UNC_ERR_INT,unc_err_int from MPC_IRAM4 None" "0,1" newline bitfld.long 0x4 14. "MPC_IRAM4_COR_ERR_INT,cor_err_int from MPC_IRAM4 None" "0,1" newline bitfld.long 0x4 13. "MPC_IRAM3_UNC_ERR_INT,unc_err_int from MPC_IRAM3 None" "0,1" newline bitfld.long 0x4 12. "MPC_IRAM3_COR_ERR_INT,cor_err_int from MPC_IRAM3 None" "0,1" newline bitfld.long 0x4 11. "MPC_IRAM2_UNC_ERR_INT,unc_err_int from MPC_IRAM2 None" "0,1" newline bitfld.long 0x4 10. "MPC_IRAM2_COR_ERR_INT,cor_err_int from MPC_IRAM2 None" "0,1" newline bitfld.long 0x4 9. "MPC_IRAM1_UNC_ERR_INT,unc_err_int from MPC_IRAM1 None" "0,1" newline bitfld.long 0x4 8. "MPC_IRAM1_COR_ERR_INT,cor_err_int from MPC_IRAM1 None" "0,1" newline bitfld.long 0x4 7. "NOC_SAF_S_4_MAINMAIN_SGLDATAECCERR,s_4_mainMain_SglDataEccErr from NOC_SAF None" "0,1" newline bitfld.long 0x4 6. "NOC_SAF_S_4_MAINDUPL_SGLDATAECCERR,s_4_mainDupl_SglDataEccErr from NOC_SAF None" "0,1" newline bitfld.long 0x4 5. "NOC_SAF_S_2_MAINMAIN_SGLDATAECCERR,s_2_mainMain_SglDataEccErr from NOC_SAF None" "0,1" newline bitfld.long 0x4 4. "NOC_SAF_S_2_MAINDUPL_SGLDATAECCERR,s_2_mainDupl_SglDataEccErr from NOC_SAF None" "0,1" newline bitfld.long 0x4 3. "NOC_SAF_S_1_MAINMAIN_SGLDATAECCERR,s_1_mainMain_SglDataEccErr from NOC_SAF None" "0,1" newline bitfld.long 0x4 2. "NOC_SAF_S_1_MAINDUPL_SGLDATAECCERR,s_1_mainDupl_SglDataEccErr from NOC_SAF None" "0,1" newline bitfld.long 0x4 1. "NOC_SAF_S_0_MAINMAIN_SGLECCERR,s_0_mainMain_SglEccErr from NOC_SAF None" "0,1" group.long 0x94++0x3 line.long 0x0 "CE0_PK_TIMER,'The timer counts the number of clock cycles when the PK engine is busy. It is not cleared automatically. It can be written by software (when the PK is idle). The register is updated at the end of every operation (reading it when the PK.." rbitfld.long 0x0 31. "DC3_CRC32_IRQ,dc_ch_underrun from DC3 None" "0,1" newline rbitfld.long 0x0 30. "CR5_SAF_PPHCORR0,pphcorr0 from CR5_SAF data errors on reads by the AHB Peripheral Port" "0,1" newline rbitfld.long 0x0 29. "CR5_SAF_PPXCORR0,ppxcorr0 from CR5_SAF data errors on reads by the AXI Peripheral Port" "0,1" newline rbitfld.long 0x0 28. "CR5_SAF_AXISCORR0,axiscorr0 from CR5_SAF data errors on writes to the AXI Slave" "0,1" newline rbitfld.long 0x0 27. "CR5_SAF_AXIMCORR0,aximcorr0 from CR5_SAF data errors on reads by the AXI Master" "0,1" newline rbitfld.long 0x0 26. "OSPI2_O_IRQ_UNCORR,o_irq_uncorr from OSPI2 None" "0,1" newline rbitfld.long 0x0 25. "OSPI2_O_IRQ_CORR,o_irq_corr from OSPI2 None" "0,1" newline rbitfld.long 0x0 24. "OSPI1_O_IRQ_UNCORR,o_irq_uncorr from OSPI1 None" "0,1" newline rbitfld.long 0x0 23. "OSPI1_O_IRQ_CORR,o_irq_corr from OSPI1 None" "0,1" newline rbitfld.long 0x0 22. "EFUSEC_FATAL_ERR_INT,fatal_err_int from EFUSEC None" "0,1" newline rbitfld.long 0x0 21. "EFUSEC_NORMAL_ERR_INT,normal_err_int from EFUSEC None" "0,1" newline rbitfld.long 0x0 20. "PCIE_SS_O_PCIEX1_SAFETY_CORR,o_pciex1_safety_corr from PCIE_SS PCIE correctable error" "0,1" newline rbitfld.long 0x0 19. "PCIE_SS_O_PCIEX1_SAFETY_UNCORR,o_pciex1_safety_uncorr from PCIE_SS PCIE non correctable error" "0,1" newline rbitfld.long 0x0 18. "PCIE_SS_O_PCIEX2_SAFETY_CORR,o_pciex2_safety_corr from PCIE_SS PCIE correctable error" "0,1" newline rbitfld.long 0x0 17. "PCIE_SS_O_PCIEX2_SAFETY_UNCORR,o_pciex2_safety_uncorr from PCIE_SS PCIE non correctable error" "0,1" newline rbitfld.long 0x0 16. "ADC_CHANNEL_EVENT4,channel_event4 from ADC None OR channel_event5 from ADC None OR channel_event6 from ADC None OR channel_event7 from ADC None" "0,1" newline rbitfld.long 0x0 15. "ADC_CHANNEL_EVENT3,channel_event3 from ADC None" "0,1" newline rbitfld.long 0x0 14. "ADC_CHANNEL_EVENT2,channel_event2 from ADC None" "0,1" newline rbitfld.long 0x0 13. "ADC_CHANNEL_EVENT1,channel_event1 from ADC None" "0,1" newline rbitfld.long 0x0 12. "ADC_CHANNEL_EVENT0,channel_event0 from ADC None" "0,1" newline rbitfld.long 0x0 11. "VDSP_DOUBLEEXCEPTIONERROR,DoubleExceptionError from VDSP None" "0,1" newline rbitfld.long 0x0 10. "VDSP_PFATALERROR,PFatalError from VDSP None" "0,1" newline rbitfld.long 0x0 9. "VDSP_ERRORCORRECTED,ErrorCorrected from VDSP None" "0,1" newline rbitfld.long 0x0 8. "DP3_DP_CH_UNDERRUN,dp_ch_underrun from DP3 None" "0,1" newline rbitfld.long 0x0 7. "DP2_DP_CH_UNDERRUN,dp_ch_underrun from DP2 None" "0,1" newline rbitfld.long 0x0 6. "DP1_DP_CH_UNDERRUN,dp_ch_underrun from DP1 None" "0,1" newline rbitfld.long 0x0 5. "DC5_CRC32_IRQ,crc32_irq from DC5 None" "0,1" newline rbitfld.long 0x0 4. "DC5_DC_CH_UNDERRUN,dc_ch_underrun from DC5 None" "0,1" newline rbitfld.long 0x0 3. "DC4_CRC32_IRQ,crc32_irq from DC4 None" "0,1" newline rbitfld.long 0x0 2. "DC4_DC_CH_UNDERRUN,dc_ch_underrun from DC4 None" "0,1" newline rbitfld.long 0x0 1. "DC3_CRC32_IRQ,crc32_irq from DC3 None" "0,1" newline hexmask.long 0x0 0.--31. 1. "PK_TIMER,'The timer counts the number of clock cycles when the PK engine is busy. It is not cleared automatically. It can be written by software (when the PK is idle). The register is updated at the end of every operation (reading it when the PK engine.." rgroup.long 0x98++0x3 line.long 0x0 "CE0_PK_HWCONFIGREG,'State of DisableCM input (high when counter-measures are disabled)'" bitfld.long 0x0 31. "CR5_SAF_AXIMFATAL0[2],aximfatal0[1] from CR5_SAF data errors and any parity errors on the AXI master" "0,1" newline bitfld.long 0x0 30. "CR5_SEC_PPXFATAL0[0],ppxfatal0[0] from CR5_SEC data errors and any parity errors on the AXI Peripheral Port" "0,1" newline bitfld.long 0x0 29. "CR5_SEC_AXISFATAL0[4],axisfatal0[4] from CR5_SEC data errors and any parity errors on the AXI slave" "0,1" newline bitfld.long 0x0 28. "CR5_SEC_AXISFATAL0[3],axisfatal0[3] from CR5_SEC data errors and any parity errors on the AXI slave" "0,1" newline bitfld.long 0x0 27. "CR5_SEC_AXISFATAL0[2],axisfatal0[2] from CR5_SEC data errors and any parity errors on the AXI slave" "0,1" newline bitfld.long 0x0 26. "CR5_SEC_AXISFATAL0[1],axisfatal0[1] from CR5_SEC data errors and any parity errors on the AXI slave" "0,1" newline bitfld.long 0x0 25. "CR5_SEC_AXISFATAL0[0],axisfatal0[0] from CR5_SEC data errors and any parity errors on the AXI slave" "0,1" newline hexmask.long.byte 0x0 25.--30. 1. "RESERVED,'unused'" newline bitfld.long 0x0 24. "PK_25519,'Support Curve25519/Ed25519 acceleration'" "0,1" newline bitfld.long 0x0 23. "PK_P192,'Support ECC P192 acceleration'" "0,1" newline bitfld.long 0x0 22. "PK_P521,'Support ECC P521 acceleration'" "0,1" newline bitfld.long 0x0 21. "PK_P384,'Support ECC P384 acceleration'" "0,1" newline bitfld.long 0x0 20. "PK_P256,'Support ECC P256 acceleration'" "0,1" newline bitfld.long 0x0 18.--19. "RESERVED,'unused'" "0,1,2,3" newline bitfld.long 0x0 17. "PK_BINARYFIELD,'Support binary field'" "0,1" newline bitfld.long 0x0 16. "PK_PRIMEFIELD,'Support prime field'" "0,1" newline hexmask.long.byte 0x0 12.--15. 1. "PK_NBMULT,'Number of multipliers: 0x0: 1 multiplier 0x1: 4 multipliers 0x2: 16 multipliers 0x4: 64 multipliers 0x8: 256 multipliers'" newline hexmask.long.word 0x0 0.--11. 1. "PK_MAXOPSIZE,'Maximum operand size (number of bytes) 4096 bytes'" group.long 0x9C++0xB line.long 0x0 "CE0_PK_RESULTS_CTRL,'pke results output select each bit correspnding to the operand position of the pke data memory'" rbitfld.long 0x0 31. "CR5_SEC_PPXFATAL0[3],ppxfatal0[2] from CR5_SEC data errors and any parity errors on the AXI Peripheral Port" "0,1" newline rbitfld.long 0x0 30. "REMAP_CR5_MP_AW_IRQ,irq from REMAP_CR5_MP_AW Remap Address field check error" "0,1" newline rbitfld.long 0x0 29. "REMAP_CR5_SEC_AR_IRQ,irq from REMAP_CR5_SEC_AR Remap Address field check error" "0,1" newline rbitfld.long 0x0 28. "REMAP_CR5_SEC_AW_IRQ,irq from REMAP_CR5_SEC_AW Remap Address field check error" "0,1" newline rbitfld.long 0x0 27. "REMAP_CR5_SAF_AR_IRQ,irq from REMAP_CR5_SAF_AR Remap Address field check error" "0,1" newline rbitfld.long 0x0 26. "REMAP_CR5_SAF_AW_IRQ,irq from REMAP_CR5_SAF_AW Remap Address field check error" "0,1" newline rbitfld.long 0x0 25. "CR5_MP_DCCMOUT2[0],dccmout2[0] from CR5_MP LockStep compare fail" "0,1" newline rbitfld.long 0x0 24. "CR5_MP_DCCMOUT[0],dccmout[0] from CR5_MP LockStep compare fail" "0,1" newline rbitfld.long 0x0 23. "CR5_MP_PPXFATAL0[4],ppxfatal0[4] from CR5_MP data errors and any parity errors on the AXI Peripheral Port" "0,1" newline rbitfld.long 0x0 22. "CR5_MP_PPXFATAL0[3],ppxfatal0[3] from CR5_MP data errors and any parity errors on the AXI Peripheral Port" "0,1" newline rbitfld.long 0x0 21. "CR5_MP_PPXFATAL0[2],ppxfatal0[2] from CR5_MP data errors and any parity errors on the AXI Peripheral Port" "0,1" newline rbitfld.long 0x0 20. "CR5_MP_PPXFATAL0[1],ppxfatal0[1] from CR5_MP data errors and any parity errors on the AXI Peripheral Port" "0,1" newline rbitfld.long 0x0 19. "CR5_MP_PPXFATAL0[0],ppxfatal0[0] from CR5_MP data errors and any parity errors on the AXI Peripheral Port" "0,1" newline rbitfld.long 0x0 18. "CR5_MP_AXISFATAL0[4],axisfatal0[4] from CR5_MP data errors and any parity errors on the AXI slave" "0,1" newline rbitfld.long 0x0 17. "CR5_MP_AXISFATAL0[3],axisfatal0[3] from CR5_MP data errors and any parity errors on the AXI slave" "0,1" newline hexmask.long.word 0x0 16.--31. 1. "PKE_RESULTS_OP_LEN,'pke results each operand length in bytes'" newline rbitfld.long 0x0 16. "CR5_MP_AXISFATAL0[2],axisfatal0[2] from CR5_MP data errors and any parity errors on the AXI slave" "0,1" line.long 0x4 "CE0_PK_RESULTS_DST_ADDR,'pke results dma dst address low 32bit'" rbitfld.long 0x4 31. "CPU1_~NFAULTIRQ[1],~nFAULTIRQ[0] from CPU1 Fault indicator for a detected 1-bit or 2-bit ECC or Parity error in the L3 RAMs" "?,bit or 2-bit ECC or Parity error in the L3 RAMs" newline rbitfld.long 0x4 30. "PWR_LAT_SAF_RTC_POWER_LAT,rtc_power_lat from PWR_LAT_SAF RTC domain power fail" "0,1" newline rbitfld.long 0x4 29. "XTAL_AP_TO_LOST_INT,to_lost_int from XTAL_AP xtal_saf lost" "0,1" newline rbitfld.long 0x4 28. "XTAL_AP_TO_UNST_INT,to_unst_int from XTAL_AP xtal_saf un-stable" "0,1" newline rbitfld.long 0x4 27. "XTAL_AP_FR_UNST_INT,fr_unst_int from XTAL_AP xtal_ap un-stable" "0,1" newline rbitfld.long 0x4 26. "XTAL_SAF_TO_LOST_INT,to_lost_int from XTAL_SAF xtal_ap lost" "0,1" newline rbitfld.long 0x4 25. "XTAL_SAF_TO_UNST_INT,to_unst_int from XTAL_SAF xtal_ap un-stable" "0,1" newline rbitfld.long 0x4 24. "XTAL_SAF_FR_UNST_INT,fr_unst_int from XTAL_SAF xtal_saf un-stable" "0,1" newline rbitfld.long 0x4 23. "RC_24M_SOC_XTAL_LOST_INT,soc_xtal_lost_int from RC_24M soc xtal lost" "0,1" newline rbitfld.long 0x4 22. "RC_24M_SOC_XTAL_UNST_INT,soc_xtal_unst_int from RC_24M soc xtal un-stable" "0,1" newline rbitfld.long 0x4 21. "RC_24M_SOC_OSC_UNST_INT,soc_osc_unst_int from RC_24M osc un-stable according to soc xtal" "0,1" newline rbitfld.long 0x4 20. "RC_24M_SAF_XTAL_LOST_INT,saf_xtal_lost_int from RC_24M safety xtal lost" "0,1" newline rbitfld.long 0x4 19. "RC_24M_SAF_XTAL_UNST_INT,saf_xtal_unst_int from RC_24M safety xtal un-stable" "0,1" newline rbitfld.long 0x4 18. "RC_24M_SAF_OSC_UNST_INT,saf_osc_unst_int from RC_24M osc un-stable according to saf xtal" "0,1" newline rbitfld.long 0x4 17. "CPU2_~NERRIRQ[1],~nERRIRQ[1] from CPU2 Error indicator for an ECC error that causes potential data corruption or loss of coherency in the Core0 L1 or L2 RAMs" "0,1" newline rbitfld.long 0x4 16. "CPU2_~NERRIRQ[0],~nERRIRQ[0] from CPU2 Error indicator for an ECC error that causes potential data corruption or loss of coherency in the L3 RAMs" "0,1" newline rbitfld.long 0x4 15. "CPU2_~NFAULTIRQ[1],~nFAULTIRQ[1] from CPU2 Fault indicator for a detected 1-bit or 2-bit ECC or Parity error in the Core0 L1 or L2 RAMs" "?,bit or 2-bit ECC or Parity error in the Core0 L1.." newline rbitfld.long 0x4 14. "CPU2_~NFAULTIRQ[0],~nFAULTIRQ[0] from CPU2 Fault indicator for a detected 1-bit or 2-bit ECC or Parity error in the L3 RAMs" "?,bit or 2-bit ECC or Parity error in the L3 RAMs" newline rbitfld.long 0x4 13. "CPU1_~NERRIRQ[6],~nERRIRQ[6] from CPU1 Error indicator for an ECC error that causes potential data corruption or loss of coherency in the Core3 L1 or L2 RAMs" "0,1" newline rbitfld.long 0x4 12. "CPU1_~NERRIRQ[5],~nERRIRQ[5] from CPU1 Error indicator for an ECC error that causes potential data corruption or loss of coherency in the Core2 L1 or L2 RAMs" "0,1" newline rbitfld.long 0x4 11. "CPU1_~NERRIRQ[4],~nERRIRQ[4] from CPU1 Error indicator for an ECC error that causes potential data corruption or loss of coherency in the Core3 L1 or L2 RAMs" "0,1" newline rbitfld.long 0x4 10. "CPU1_~NERRIRQ[3],~nERRIRQ[3] from CPU1 Error indicator for an ECC error that causes potential data corruption or loss of coherency in the Core2 L1 or L2 RAMs" "0,1" newline rbitfld.long 0x4 9. "CPU1_~NERRIRQ[2],~nERRIRQ[2] from CPU1 Error indicator for an ECC error that causes potential data corruption or loss of coherency in the Core1 L1 or L2 RAMs" "0,1" newline rbitfld.long 0x4 8. "CPU1_~NERRIRQ[1],~nERRIRQ[1] from CPU1 Error indicator for an ECC error that causes potential data corruption or loss of coherency in the Core0 L1 or L2 RAMs" "0,1" newline rbitfld.long 0x4 7. "CPU1_~NERRIRQ[0],~nERRIRQ[0] from CPU1 Error indicator for an ECC error that causes potential data corruption or loss of coherency in the L3 RAMs" "0,1" newline rbitfld.long 0x4 6. "CPU1_~NFAULTIRQ[6],~nFAULTIRQ[6] from CPU1 Fault indicator for a detected 1-bit or 2-bit ECC or Parity error in the Core3 L1 or L2 RAMs" "?,bit or 2-bit ECC or Parity error in the Core3 L1.." newline rbitfld.long 0x4 5. "CPU1_~NFAULTIRQ[5],~nFAULTIRQ[5] from CPU1 Fault indicator for a detected 1-bit or 2-bit ECC or Parity error in the Core2 L1 or L2 RAMs" "?,bit or 2-bit ECC or Parity error in the Core2 L1.." newline rbitfld.long 0x4 4. "CPU1_~NFAULTIRQ[4],~nFAULTIRQ[4] from CPU1 Fault indicator for a detected 1-bit or 2-bit ECC or Parity error in the Core3 L1 or L2 RAMs" "?,bit or 2-bit ECC or Parity error in the Core3 L1.." newline rbitfld.long 0x4 3. "CPU1_~NFAULTIRQ[3],~nFAULTIRQ[3] from CPU1 Fault indicator for a detected 1-bit or 2-bit ECC or Parity error in the Core2 L1 or L2 RAMs" "?,bit or 2-bit ECC or Parity error in the Core2 L1.." newline rbitfld.long 0x4 2. "CPU1_~NFAULTIRQ[2],~nFAULTIRQ[2] from CPU1 Fault indicator for a detected 1-bit or 2-bit ECC or Parity error in the Core1 L1 or L2 RAMs" "?,bit or 2-bit ECC or Parity error in the Core1 L1.." newline rbitfld.long 0x4 1. "CPU1_~NFAULTIRQ[1],~nFAULTIRQ[1] from CPU1 Fault indicator for a detected 1-bit or 2-bit ECC or Parity error in the Core0 L1 or L2 RAMs" "?,bit or 2-bit ECC or Parity error in the Core0 L1.." newline hexmask.long 0x4 0.--31. 1. "PKE_RESULTS_DST_ADDR,'pke results dma dst address low 32bit'" line.long 0x8 "CE0_PK_RESULTS_DST_ADDR_H,'pke results dma dst address high 8bit'" rbitfld.long 0x8 30. "PWR_LAT_RTC_SAF_POWER_LAT,saf_power_lat from PWR_LAT_SAF SAF power fail" "0,1" newline rbitfld.long 0x8 29. "PVT_SNS_SAF_PVT_INT_0,pvt_int_0 from PVT_SNS_SAF None" "0,1" newline rbitfld.long 0x8 28. "PVT_SNS_SEC_PVT_INT_1,pvt_int_1 from PVT_SNS_SEC None" "0,1" newline rbitfld.long 0x8 27. "PVT_SNS_SEC_PVT_INT_0,pvt_int_0 from PVT_SNS_SEC None" "0,1" newline rbitfld.long 0x8 26. "WDT8_ILL_SEQ_REFR_INT,ill_seq_refr_int from WDT8 None" "0,1" newline rbitfld.long 0x8 25. "WDT8_ILL_WIN_REFR_INT,ill_win_refr_int from WDT8 None" "0,1" newline rbitfld.long 0x8 24. "WDT8_OVFLOW_INT,ovflow_int from WDT8 None" "0,1" newline rbitfld.long 0x8 23. "WDT7_ILL_SEQ_REFR_INT,ill_seq_refr_int from WDT7 None" "0,1" newline rbitfld.long 0x8 22. "WDT7_ILL_WIN_REFR_INT,ill_win_refr_int from WDT7 None" "0,1" newline rbitfld.long 0x8 21. "WDT7_OVFLOW_INT,ovflow_int from WDT7 None" "0,1" newline rbitfld.long 0x8 20. "WDT6_ILL_SEQ_REFR_INT,ill_seq_refr_int from WDT6 None" "0,1" newline rbitfld.long 0x8 19. "WDT6_ILL_WIN_REFR_INT,ill_win_refr_int from WDT6 None" "0,1" newline rbitfld.long 0x8 18. "WDT6_OVFLOW_INT,ovflow_int from WDT6 None" "0,1" newline rbitfld.long 0x8 17. "WDT5_ILL_SEQ_REFR_INT,ill_seq_refr_int from WDT5 None" "0,1" newline rbitfld.long 0x8 16. "WDT5_ILL_WIN_REFR_INT,ill_win_refr_int from WDT5 None" "0,1" newline rbitfld.long 0x8 15. "WDT5_OVFLOW_INT,ovflow_int from WDT5 None" "0,1" newline rbitfld.long 0x8 14. "WDT4_ILL_SEQ_REFR_INT,ill_seq_refr_int from WDT4 None" "0,1" newline rbitfld.long 0x8 13. "WDT4_ILL_WIN_REFR_INT,ill_win_refr_int from WDT4 None" "0,1" newline rbitfld.long 0x8 12. "WDT4_OVFLOW_INT,ovflow_int from WDT4 None" "0,1" newline rbitfld.long 0x8 11. "WDT3_ILL_SEQ_REFR_INT,ill_seq_refr_int from WDT3 None" "0,1" newline rbitfld.long 0x8 10. "WDT3_ILL_WIN_REFR_INT,ill_win_refr_int from WDT3 None" "0,1" newline rbitfld.long 0x8 9. "WDT3_OVFLOW_INT,ovflow_int from WDT3 None" "0,1" newline bitfld.long 0x8 8.--10. "PKE_RESULTS_DST_TYPE,'pke results dma dst data type 011: CE SRAM Secure AREA 001:CE SRAM public area 000:external memories other: reserved'" "0,1,2,3,4,5,6,7" newline rbitfld.long 0x8 8. "WDT2_ILL_SEQ_REFR_INT,ill_seq_refr_int from WDT2 None" "0,1" group.long 0x100++0x7 line.long 0x0 "CE0_TRNG_STATUS,'1: the value in the random number register of CE0 is valid" rbitfld.long 0x0 1. "RNG_READY,'1: the value in the random number register of CE0 is valid" "?,the value in the random number register of CE0.." newline hexmask.long 0x0 0.--31. 1. "INT_ENABLE_00,interrupt enable for int0" line.long 0x4 "CE0_TRNG_STATUS,'1: the value in the random number register of CE0 is valid" rbitfld.long 0x4 1. "RNG_READY,'1: the value in the random number register of CE0 is valid" "?,the value in the random number register of CE0.." newline hexmask.long 0x4 0.--31. 1. "INT_ENABLE_01,interrupt enable for int0" rgroup.long 0x104++0x3 line.long 0x0 "CE0_TRNG_NUM0,CE0 the random number0 value" hexmask.long 0x0 0.--31. 1. "TRNG_NUM0,CE0 the random number0 value" group.long 0x108++0x3 line.long 0x0 "CE0_TRNG_STATUS,'1: the value in the random number register of CE0 is valid" rbitfld.long 0x0 1. "RNG_READY,'1: the value in the random number register of CE0 is valid" "?,the value in the random number register of CE0.." newline hexmask.long 0x0 0.--31. 1. "INT_ENABLE_02,interrupt enable for int0" rgroup.long 0x108++0x3 line.long 0x0 "CE0_TRNG_NUM1,CE0 the random number1 value" hexmask.long 0x0 0.--31. 1. "TRNG_NUM1,CE0 the random number1 value" group.long 0x10C++0xB line.long 0x0 "CE0_TRNG_STATUS,'1: the value in the random number register of CE0 is valid" rbitfld.long 0x0 1. "RNG_READY,'1: the value in the random number register of CE0 is valid" "?,the value in the random number register of CE0.." newline hexmask.long 0x0 0.--31. 1. "INT_ENABLE_03,interrupt enable for int0" line.long 0x4 "CE0_TRNG_STATUS,'1: the value in the random number register of CE0 is valid" rbitfld.long 0x4 1. "RNG_READY,'1: the value in the random number register of CE0 is valid" "?,the value in the random number register of CE0.." newline hexmask.long 0x4 0.--31. 1. "INT_ENABLE_04,interrupt enable for int0" line.long 0x8 "CE0_TRNG_STATUS,'1: the value in the random number register of CE0 is valid" rbitfld.long 0x8 1. "RNG_READY,'1: the value in the random number register of CE0 is valid" "?,the value in the random number register of CE0.." newline hexmask.long 0x8 0.--31. 1. "INT_ENABLE_05,interrupt enable for int0" rgroup.long 0x114++0x3 line.long 0x0 "CE0_HRNG_NUM,CE0 the hybird random number value" hexmask.long 0x0 0.--31. 1. "HRNG_NUM,CE0 the hybird random number value" group.long 0x118++0xB line.long 0x0 "CE0_TRNG_STATUS,'1: the value in the random number register of CE0 is valid" rbitfld.long 0x0 1. "RNG_READY,'1: the value in the random number register of CE0 is valid" "?,the value in the random number register of CE0.." newline hexmask.long 0x0 0.--31. 1. "INT_ENABLE_06,interrupt enable for int0" line.long 0x4 "CE0_TRNG_STATUS,'1: the value in the random number register of CE0 is valid" rbitfld.long 0x4 1. "RNG_READY,'1: the value in the random number register of CE0 is valid" "?,the value in the random number register of CE0.." newline hexmask.long 0x4 0.--31. 1. "INT_ENABLE_07,interrupt enable for int0" line.long 0x8 "CE0_TRNG_STATUS,'1: the value in the random number register of CE0 is valid" rbitfld.long 0x8 1. "RNG_READY,'1: the value in the random number register of CE0 is valid" "?,the value in the random number register of CE0.." newline hexmask.long 0x8 0.--31. 1. "INT_ENABLE_08,interrupt enable for int0" wgroup.long 0x120++0x3 line.long 0x0 "CE0_SKC_CTRL,CE0 secure FSM start trigger" bitfld.long 0x0 8. "SKC_GO,CE0 secure FSM start trigger" "0,1" group.long 0x124++0x3 line.long 0x0 "CE0_TRNG_STATUS,'1: the value in the random number register of CE0 is valid" rbitfld.long 0x0 1. "RNG_READY,'1: the value in the random number register of CE0 is valid" "?,the value in the random number register of CE0.." newline hexmask.long 0x0 0.--31. 1. "INT_ENABLE_09,interrupt enable for int0" group.long 0x124++0x7 line.long 0x0 "CE0_SKC_RNG_ADDR,CE0 random number generation address in CE sram the address granularity is 8 bytes" hexmask.long.byte 0x0 24.--30. 1. "SKC_RNG_LEN,'numbers of bits to generate into sram granularity is 256 bit'" newline hexmask.long.word 0x0 13.--25. 1. "SKC_RNG_ADDR,CE0 random number generation address in CE sram the address granularity is 8 bytes" line.long 0x4 "CE0_SKC_KEYBLOB_CTRL,CE0 key blob control 1: is key blob :0 : is the secret data" bitfld.long 0x4 0. "SKC_KEYBLOB_CTRL,CE0 key blob control 1: is key blob :0 : is the secret data" "?,is key blob :0 : is the secret data" group.long 0x140++0x3 line.long 0x0 "CE0_INTEN,RESERVED" newline bitfld.long 0x0 13. "DMA_FIFOERROR_INTEN,DMA fifo error interrupt" "0,1" newline bitfld.long 0x0 12. "PKE_INTEGRITY_ERROR_INTEN,ALGORITHM_INTEGRITY interrupt" "0,1" newline bitfld.long 0x0 11. "HASH_INTEGRITY_ERROR_INTEN,ALGORITHM_INTEGRITY_ERROR interrupt" "0,1" newline bitfld.long 0x0 10. "CIPHER_INTEGRITY_ERROR_INTEN,ALGORITHM_INTEGRITY_ERROR interrupt" "0,1" newline bitfld.long 0x0 9. "SKC_INTEGRITY_ERROR_INTEN,SKC_INTEGRITY_ERROR interrupt" "0,1" newline bitfld.long 0x0 8. "DMA_INTEGRITY_ERROR_INTEN,ALGORITHM_INTEGRITY interrupt" "0,1" newline bitfld.long 0x0 4. "PKE_DONE_INTEN,PKE_DONE interrupt" "0,1" newline bitfld.long 0x0 3. "HASH_DONE_INTEN,HASH_DONE interrupt" "0,1" newline bitfld.long 0x0 2. "CIPHER_DONE_INTEN,CIPHER_DONE_INTEN" "0,1" newline bitfld.long 0x0 1. "SKC_DONE_INTEN,KEYgen done interrupt enable" "0,1" newline bitfld.long 0x0 0. "DMA_DONE_INTEN,DMA_DONE interrupt" "0,1" rgroup.long 0x144++0x3 line.long 0x0 "CE0_INTSTAT,RESERVED" newline bitfld.long 0x0 13. "DMA_FIFOERROR_INTSTAT,SSRAM_DMAFIFO error interrupt" "0,1" newline bitfld.long 0x0 12. "PKE_INTEGRITY_ERROR_INTSTAT,ALGORITHM_INTEGRITY interrupt" "0,1" newline bitfld.long 0x0 11. "HASH_INTEGRITY_ERROR_INTSTAT,ALGORITHM_INTEGRITY_ERROR interrupt" "0,1" newline bitfld.long 0x0 10. "CIPHER_INTEGRITY_ERROR_INTSTAT,ALGORITHM_INTEGRITY_ERROR interrupt" "0,1" newline bitfld.long 0x0 9. "SKC_INTEGRITY_ERROR_INTSTAT,SKC_INTEGRITY_ERROR interrupt" "0,1" newline bitfld.long 0x0 8. "DMA_INTEGRITY_ERROR_INTSTAT,ALGORITHM_INTEGRITY interrupt" "0,1" newline bitfld.long 0x0 4. "PKE_DONE_INTSTAT,PKE_DONE interrupt" "0,1" newline bitfld.long 0x0 3. "HASH_DONE_INTSTAT,HASH_DONE interrupt" "0,1" newline bitfld.long 0x0 2. "CIPHER_DONE_INTSTAT,CIPHER_DONE_INTSTATE" "0,1" newline bitfld.long 0x0 1. "SKC_DONE_INTSTAT,KEYgen done interrupt enable" "0,1" newline bitfld.long 0x0 0. "DMA_DONE_INTSTAT,DMA_DONE interrupt" "0,1" wgroup.long 0x148++0x3 line.long 0x0 "CE0_INTCLR,RESERVED" newline bitfld.long 0x0 13. "DMA_FIFOERROR_INTCLR,SSRAM_DMAFIFO error interrupt" "0,1" newline bitfld.long 0x0 12. "PKE_INTEGRITY_ERROR_INTCLR,ALGORITHM_INTEGRITY interrupt" "0,1" newline bitfld.long 0x0 11. "HASH_INTEGRITY_ERROR_INTCLR,ALGORITHM_INTEGRITY_ERROR interrupt" "0,1" newline bitfld.long 0x0 10. "CIPHER_INTEGRITY_ERROR_INTCLR,ALGORITHM_INTEGRITY_ERROR interrupt" "0,1" newline bitfld.long 0x0 9. "SKC_INTEGRITY_ERROR_INTCLR,SKC_INTEGRITY_ERROR interrupt" "0,1" newline bitfld.long 0x0 8. "DMA_INTEGRITY_ERROR_INTCLR,ALGORITHM_INTEGRITY interrupt" "0,1" newline bitfld.long 0x0 4. "PKE_DONE_INTCLR,PKE_DONE interrupt" "0,1" newline bitfld.long 0x0 3. "HASH_DONE_INTCLR,HASH_DONE interrupt" "0,1" newline bitfld.long 0x0 2. "CIPHER_DONE_INTCLR,CIPHER_DONE_INTCLRE" "0,1" newline bitfld.long 0x0 1. "SKC_DONE_INTCLR,KEYgen done interrupt enable" "0,1" newline bitfld.long 0x0 0. "DMA_DONE_INTCLR,DMA_DONE interrupt" "0,1" repeat 16. (list 0xA 0xB 0xC 0xD 0xE 0xF 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 )(list 0x0 0x4 0x8 0xC 0x10 0x14 0x18 0x1C 0x20 0x24 0x80 0x84 0x88 0x8C 0x90 0x94 ) group.long ($2+0x180)++0x3 line.long 0x0 "INT_ENABLE_$1,interrupt enable for int_1" hexmask.long 0x0 0.--31. 1. "INT_ENABLE_10,interrupt enable for int1" repeat.end repeat 16. (list 0x1A 0x1B 0x1C 0x1D 0x1E 0x1F 0x20 0x21 0x22 0x23 0x24 0x25 0x26 0x27 0x28 0x29 )(list 0x98 0x9C 0xA0 0xA4 0x100 0x104 0x108 0x10C 0x110 0x114 0x118 0x11C 0x120 0x124 0x180 0x184 ) group.long ($2+0x180)++0x3 line.long 0x0 "INT_ENABLE_$1,interrupt enable for int_1" hexmask.long 0x0 0.--31. 1. "INT_ENABLE_10,interrupt enable for int1" repeat.end repeat 16. (list 0x2A 0x2B 0x2C 0x2D 0x2E 0x2F 0x30 0x31 0x32 0x33 0x34 0x35 0x36 0x37 0x38 0x39 )(list 0x188 0x18C 0x190 0x194 0x198 0x19C 0x1A0 0x1A4 0x200 0x204 0x208 0x20C 0x210 0x214 0x218 0x21C ) group.long ($2+0x180)++0x3 line.long 0x0 "INT_ENABLE_$1,interrupt enable for int_1" hexmask.long 0x0 0.--31. 1. "INT_ENABLE_10,interrupt enable for int1" repeat.end repeat 16. (list 0x3A 0x3B 0x3C 0x3D 0x3E 0x3F 0x40 0x41 0x42 0x43 0x44 0x45 0x46 0x47 0x48 0x49 )(list 0x220 0x224 0x280 0x284 0x288 0x28C 0x290 0x294 0x298 0x29C 0x2A0 0x2A4 0x300 0x304 0x308 0x30C ) group.long ($2+0x180)++0x3 line.long 0x0 "INT_ENABLE_$1,interrupt enable for int_1" hexmask.long 0x0 0.--31. 1. "INT_ENABLE_10,interrupt enable for int1" repeat.end repeat 6. (list 0x4A 0x4B 0x4C 0x4D 0x4E 0x4F )(list 0x310 0x314 0x318 0x31C 0x320 0x324 ) group.long ($2+0x180)++0x3 line.long 0x0 "INT_ENABLE_$1,interrupt enable for int_1" hexmask.long 0x0 0.--31. 1. "INT_ENABLE_10,interrupt enable for int1" repeat.end repeat 6. (list 0x0 0x1 0x2 0x3 0x4 0x5 )(list 0x0 0x4 0x8 0xC 0x10 0x14 ) group.long ($2+0x500)++0x3 line.long 0x0 "TGT_VALUE$1,target value" hexmask.long 0x0 0.--31. 1. "TGT_VALUE0,monitor target value" repeat.end repeat 6. (list 0x0 0x1 0x2 0x3 0x4 0x5 )(list 0x0 0x4 0x8 0xC 0x10 0x14 ) group.long ($2+0x580)++0x3 line.long 0x0 "SIG_MON_ENABLE$1,signal monitor enable" hexmask.long 0x0 0.--31. 1. "SIG_MON_ENABLE0,monitor enable" repeat.end rgroup.long 0x8000++0x3 line.long 0x0 "SECURE_CTRL,'the corresponding bits enable the secure violation source'" hexmask.long.byte 0x0 24.--31. 1. "CE_SRAM_SIZE_VIO,the CE sram size size is not correct" group.long 0x8004++0x17 line.long 0x0 "SESRAM_SIZE,the secure sram size CE1" bitfld.long 0x0 31. "RESERVED,the secure sram size CE1" "0,1" line.long 0x4 "SESRAM_SIZE_CONT,the secure sram size CE1" bitfld.long 0x4 31. "RESERVED,the secure sram size CE1" "0,1" line.long 0x8 "SESRAM_SASIZE,the secure sram size CE1" bitfld.long 0x8 31. "RESERVED,the secure sram size CE1" "0,1" line.long 0xC "SESRAM_SASIZE_CONT,the secure sram size CE1" bitfld.long 0xC 31. "RESERVED,the secure sram size CE1" "0,1" line.long 0x10 "VCE_SINATURE_MASK,'the mask for the vce to generate signature from id'" hexmask.long 0x10 0.--31. 1. "VCE_SINATURE_MASK,'the mask for the vce to generate signature from id'" line.long 0x14 "VCE_SINATURE_MASK_HIGH,'the mask for the vce to generate signature from id high part'" hexmask.long.byte 0x14 0.--7. 1. "VCE_SINATURE_MASK_HIGH,'the mask for the vce to generate signature from id high part'" group.long 0x8020++0x7 line.long 0x0 "HRNG_CTRL,'the counter to control the frequency for the hrng LFSF load the feedback cycle'" hexmask.long.byte 0x0 8.--11. 1. "HRNG_LOAD_CNT,'the counter to control the frequency for the hrng LFSF load the feedback cycle'" newline bitfld.long 0x0 0. "NOISE_ENABLE,'1: enable the noise source for the hrng 0: disable the noise source'" "disable the noise source',enable the noise source for the hrng" line.long 0x4 "HRNG_SEED_CTRL,'write 1 to this bit will load the seed into the hrng auto clear'" bitfld.long 0x4 31. "LOAD_SEED_GO,'write 1 to this bit will load the seed into the hrng auto clear'" "0,1" newline hexmask.long 0x4 0.--30. 1. "SEED_NUM,'the seed number" wgroup.long 0x8030++0x3 line.long 0x0 "TRNG_CTRL,'write this bit will start the trng sequencer to fetch the random number for all VCEs'" bitfld.long 0x0 0. "CE_TRNG_SEQ_GO,'write this bit will start the trng sequencer to fetch the random number for all VCEs'" "0,1" group.long 0x8050++0x3 line.long 0x0 "DEBUG_BUS_SEL,'debug bus select'" hexmask.long.word 0x0 0.--15. 1. "DEBUG_BUS_SEL,'debug bus select'" rgroup.long 0x8054++0x3 line.long 0x0 "DEBUG_BUS_STATUS,'debug bus output'" hexmask.long 0x0 0.--31. 1. "DEBUG_BUS_STATUS,'debug bus output'" group.long 0x8100++0x3 line.long 0x0 "TRNG_CONTROL,'Enable write of the samples in the FIFO during start-up'" bitfld.long 0x0 20. "TRNG_FIFOWRITESTARTUP,'Enable write of the samples in the FIFO during start-up'" "0,1" newline hexmask.long.byte 0x0 16.--19. 1. "TRNG_NB128BITBLOCKS,'Number of 128 bit blocks used in AES-CBCMAC post-processing. This value cannot be zero.'" newline bitfld.long 0x0 15. "TRNG_AIS31TESTSEL,'Select input to the AIS31 test module 0: Before conditioning 1: After conditioning'" "Before conditioning,After conditioning'" newline bitfld.long 0x0 14. "TRNG_HEALTHTESTSEL,'Select input to health test module 0: Before conditioning 1: After conditioning'" "Before conditioning,After conditioning'" newline bitfld.long 0x0 13. "TRNG_AIS31BYPASS,'Bypass AIS31 tests such that the results of the start-up and online tests do not affect the FSM state'" "0,1" newline bitfld.long 0x0 12. "TRNG_HEALTHTESTBYPASS,'Bypass NIST tests such that the results of the start-up and online test do not affect the FSM state'" "0,1" newline bitfld.long 0x0 11. "TRNG_FORCERUN,'Force oscillators to run when FIFO is full'" "0,1" newline bitfld.long 0x0 10. "TRNG_INTENALM,'Interrupt enable for AIS31 noise alarm'" "0,1" newline bitfld.long 0x0 9. "TRNG_INTENPRE,'Interrupt enable for AIS31 preliminary noise alarm'" "0,1" newline bitfld.long 0x0 8. "TRNG_SOFTRESET,'Software reset 0: Normal mode 1: The continuous test" "Normal mode,The continuous test" newline bitfld.long 0x0 7. "TRNG_INTENFULL,'Interrupt enable for FIFO full'" "0,1" newline bitfld.long 0x0 5. "TRNG_INTENPROP,'Interrupt enable for Adaptive Proportion Test failure (1024-sample window)'" "0,1" newline bitfld.long 0x0 4. "TRNG_INTENREP,'Interrupt enable for Repetition Count Test failure'" "0,1" newline bitfld.long 0x0 3. "TRNG_CONDBYPASS,'0: the conditioning function is used (normal mode) 1: the conditioning function is bypassed (to observe entropy source directly).'" "the conditioning function is used,the conditioning function is bypassed" newline bitfld.long 0x0 2. "TRNG_TESTEN,'Select input for conditioning function and continuous tests: 0: Noise source (normal mode) 1: Test data register (test mode)'" "Noise source,Test data register" newline bitfld.long 0x0 1. "TRNG_LFSREN,TRNG_LFSREN" "0,1" newline bitfld.long 0x0 0. "TRNG_ENABLE,'Enable the NDRNG.'" "0,1" rgroup.long 0x8104++0x3 line.long 0x0 "TRNG_FIFOTHD,'FIFO level below which the module leaves the idle state to refill the fifo" hexmask.long 0x0 0.--31. 1. "TRNG_FIFOLEVEL,'Number of 32 bits words of random available in the FIFO. Any write to this register clears the FullInt flag in the Status register.'" rgroup.long 0x810C++0x3 line.long 0x0 "TRNG_FIFODEPTH,'Depth Maximum number of 32 bits words that can be stored in the FIFO: 2g_fifodepth.'" hexmask.long 0x0 0.--31. 1. "TRNG_FIFODEPTH,'Depth Maximum number of 32 bits words that can be stored in the FIFO: 2g_fifodepth.'" group.long 0x8110++0xF line.long 0x0 "TRNG_KEY0REG,'Key (MSB)'" hexmask.long 0x0 0.--31. 1. "TRNG_KEY0REG,'Key (MSB)'" line.long 0x4 "TRNG_KEY1REG,'Key'" hexmask.long 0x4 0.--31. 1. "TRNG_KEY1REG,'Key'" line.long 0x8 "TRNG_KEY2REG,'Key'" hexmask.long 0x8 0.--31. 1. "TRNG_KEY2REG,'Key'" line.long 0xC "TRNG_KEY3REG,'Key (LSB)'" hexmask.long 0xC 0.--31. 1. "TRNG_KEY3REG,'Key (LSB)'" wgroup.long 0x8120++0x3 line.long 0x0 "TRNG_TESTDATA,'feed known data to the conditioning function or to the continous tests.'" hexmask.long 0x0 0.--31. 1. "TRNG_TESTDATA,'feed known data to the conditioning function or to the continous tests.'" group.long 0x8124++0x7 line.long 0x0 "TRNG_REPTHRESREG,'Repetition Test Count Cut-Off value'" hexmask.long 0x0 0.--31. 1. "TRNG_REPTHRESREG,'Repetition Test Count Cut-Off value'" line.long 0x4 "TRNG_PROPTHRESREG,'Adaptive Proportion Test (1024-sample window) Cut-Off value'" hexmask.long 0x4 0.--31. 1. "TRNG_PROPTHRESREG,'Adaptive Proportion Test (1024-sample window) Cut-Off value'" group.long 0x8130++0x27 line.long 0x0 "TRNG_STATUS,'Set when a FIFO data read is performed while the NDRNG is disabled AND has its FIFO empty (FIFOLevel = 0)'" bitfld.long 0x0 11. "TRNG_FIFOACCFAIL,'Set when a FIFO data read is performed while the NDRNG is disabled AND has its FIFO empty (FIFOLevel = 0)'" "0,1" newline rbitfld.long 0x0 10. "TRNG_STARTUPFAIL,'Start-up test failure'" "0,1" newline rbitfld.long 0x0 9. "TRNG_ALMINT,'AIS31 noise alarm interrupt status'" "0,1" newline bitfld.long 0x0 8. "TRNG_PREINT,'AIS31 preliminary noise alarm interrupt status'" "0,1" newline bitfld.long 0x0 7. "TRNG_FULLINT,'FIFO full status'" "0,1" newline bitfld.long 0x0 5. "TRNG_PROPFAIL,'NIST-800-90B adaptive Proportion Test (1024-sample window) interrupt status'" "0,1" newline bitfld.long 0x0 4. "TRNG_REPFAIL,'NIST-800-90B repetition Count Test interrupt status'" "0,1" newline rbitfld.long 0x0 1.--3. "TRNG_STATE,'State of the control FSM (see Figure 7-1) 000: Reset 001: Startup 010: Idle (Rings On) 011: Idle (Rings Off) 100: Fill FIFO 101: Error 110: Unused 111: Unused'" "Reset,Startup,?,?,?,?,?,?" newline rbitfld.long 0x0 0. "TRNG_TESTDATABUSY,'High when data written to TestData register is being processed. (see section 4.7)'" "0,1" line.long 0x4 "TRNG_INITWAITVAL,'Number of clock cycles to wait before sampling data from the noise source. All 16 bits are reset high (reset value = 0xFFFF).'" hexmask.long.word 0x4 0.--15. 1. "TRNG_INITWAITVAL,'Number of clock cycles to wait before sampling data from the noise source. All 16 bits are reset high (reset value = 0xFFFF).'" line.long 0x8 "TRNG_DISABLEOSC,'Disable oscillator rings #0 to #31'" hexmask.long 0x8 0.--31. 1. "TRNG_DISABLEOS0,'Disable oscillator rings #0 to #31'" line.long 0xC "TRNG_DISABLEOSC1,'Disable oscillator rings #32 to #63'" hexmask.long 0xC 0.--31. 1. "TRNG_DISABLEOS1,'Disable oscillator rings #32 to #63'" line.long 0x10 "TRNG_SWOFFTMRVAL,'Number of clk cycles to wait before stopping the rings after the FIFO is full. '" hexmask.long.word 0x10 0.--15. 1. "TRNG_SWOFFTMRVAL,'Number of clk cycles to wait before stopping the rings after the FIFO is full. '" line.long 0x14 "TRNG_CLKDIV,'Sample clock divider. The frequency at which the outputs of the rings are sampled is given by Fs = Fpclk/(ClkDiv + 1).'" hexmask.long.byte 0x14 0.--7. 1. "TRNG_CLKDIV,'Sample clock divider. The frequency at which the outputs of the rings are sampled is given by Fs = Fpclk/(ClkDiv + 1).'" line.long 0x18 "TRNG_AIS31CONF0,'Online threshold'" hexmask.long.word 0x18 16.--31. 1. "TRNG_ONLINETHRESH,'Online threshold'" newline hexmask.long.word 0x18 0.--15. 1. "TRNG_STARTUPTHRESH,'Start-up test threshold'" line.long 0x1C "TRNG_AIS31CONF1,'Expected history value'" hexmask.long.word 0x1C 16.--31. 1. "TRNG_HEXPECTEDVALUE,'Expected history value'" newline hexmask.long.word 0x1C 0.--15. 1. "TRNG_ONLINEREPTHRESH,'Online repeat threshold'" line.long 0x20 "TRNG_AIS31CONF2,'Maximum allowed history valu'" hexmask.long.word 0x20 16.--31. 1. "TRNG_HMAX,'Maximum allowed history valu'" newline hexmask.long.word 0x20 0.--15. 1. "TRNG_HMIN,'Minimum allowed history value'" line.long 0x24 "TRNG_AIS31STATUS,TRNG_PRELIMNOISEALARMREP" rbitfld.long 0x24 17. "TRNG_PRELIMNOISEALARMREP,TRNG_PRELIMNOISEALARMREP" "0,1" newline rbitfld.long 0x24 16. "TRNG_PRELIMNOISEALARMRNG,'Last preliminary noise alarm occurred due to history value out of range'" "0,1" newline hexmask.long.word 0x24 0.--15. 1. "TRNG_NUMPRELIMALARMS,'Number of preliminary noise alarms since counter was last cleared'" rgroup.long 0x8158++0x3 line.long 0x0 "TRNG_HWCONF,'Generic g_AIS31Full value'" bitfld.long 0x0 9. "TRNG_AIS31FULL,'Generic g_AIS31Full value'" "0,1" newline bitfld.long 0x0 8. "TRNG_AIS31,'Generic g_AIS31 value'" "0,1" newline hexmask.long.byte 0x0 0.--7. 1. "TRNG_NUMBOFRINGS,'Generic g_NumRings value'" tree.end tree "ABC (Address Block 0 of sem)" group.long 0x0++0xB line.long 0x0 "SEM_COMMON_SET,SEM common settings" hexmask.long.byte 0x0 24.--31. 1. "CMP_ENABLE,compare output enable bits for int0-7" newline bitfld.long 0x0 23. "SIG_MON_GLB_EN,signal monitor global enable" "0,1" newline bitfld.long 0x0 17. "EI_GLOBAL_EN_LOCK,Error Injection Global Enable Lock bit" "0,1" newline bitfld.long 0x0 16. "EI_GLOBAL_EN,Error Injection Global Enable" "0,1" newline hexmask.long.byte 0x0 12.--15. 1. "ERROR_DIV,error divider ratio for waveform A" newline bitfld.long 0x0 11. "ERROR_WAVE_SEL,waveform A/B selection for normal/recoverable error" "0,1" newline bitfld.long 0x0 10. "FATAL_HIGH_LOW,fatal error High or Low selection" "0,1" newline bitfld.long 0x0 8.--9. "SEM_INT_DC4_SEL,SEM_INT DC4 selection" "0,1,2,3" newline bitfld.long 0x0 6.--7. "SEM_INT_DC3_SEL,SEM_INT DC3 selection" "0,1,2,3" newline bitfld.long 0x0 4.--5. "SEM_INT_DC2_SEL,SEM_INT DC2 selection" "0,1,2,3" newline bitfld.long 0x0 2.--3. "SEM_INT_DC1_SEL,SEM_INT DC1 selection" "0,1,2,3" newline bitfld.long 0x0 0.--1. "SEM_INT_DC0_SEL,SEM_INT DC0 selection" "0,1,2,3" line.long 0x4 "INT_TRIG,int0-7 trigger" hexmask.long.byte 0x4 0.--7. 1. "INT_TRIG,int0-int7 trigger" line.long 0x8 "INT_ENABLE_OVRD,int0-7 enable override" hexmask.long.byte 0x8 8.--15. 1. "INT_ENABLE_OVRD_VAL,int0-7 enable override value" newline hexmask.long.byte 0x8 0.--7. 1. "INT_ENABLE_OVRD_EN,int0-7 enable override enable" group.long 0x10++0x3 line.long 0x0 "IO_WAVE_CTRL,IO_WAVE_CTRL" bitfld.long 0x0 31. "LOCK,LOCK ctrl" "0,1" newline bitfld.long 0x0 2.--3. "LEVEL_CFG,the level io when normal [2] and recoverable err[3] take place" "0,1,2,3" newline bitfld.long 0x0 0.--1. "LEVEL_EN,if set the normal and recoverable output will be set as level [0] normal [1] recover case" "0,1,2,3" repeat 9. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 )(list 0x0 0x4 0x8 0xC 0x10 0x14 0x18 0x1C 0x20 ) rgroup.long ($2+0x80)++0x3 line.long 0x0 "INT_STATUS$1,Interrupt status" bitfld.long 0x0 31. "CANFD6_IPI_INT_CE,ipi_int_ce from CANFD6 Correctable error interrupt" "0,1" newline bitfld.long 0x0 30. "CANFD5_IPI_INT_NCEFA,ipi_int_ncefa from CANFD5 Non correctable error int internal" "0,1" newline bitfld.long 0x0 29. "CANFD5_IPI_INT_NCEHA,ipi_int_nceha from CANFD5 Non correctable error int host" "0,1" newline bitfld.long 0x0 28. "CANFD5_IPI_INT_CE,ipi_int_ce from CANFD5 Correctable error interrupt" "0,1" newline bitfld.long 0x0 27. "CANFD4_IPI_INT_NCEFA,ipi_int_ncefa from CANFD4 Non correctable error int internal" "0,1" newline bitfld.long 0x0 26. "CANFD4_IPI_INT_NCEHA,ipi_int_nceha from CANFD4 Non correctable error int host" "0,1" newline bitfld.long 0x0 25. "CANFD4_IPI_INT_CE,ipi_int_ce from CANFD4 Correctable error interrupt" "0,1" newline bitfld.long 0x0 24. "CANFD3_IPI_INT_NCEFA,ipi_int_ncefa from CANFD3 Non correctable error int internal" "0,1" newline bitfld.long 0x0 23. "CANFD3_IPI_INT_NCEHA,ipi_int_nceha from CANFD3 Non correctable error int host" "0,1" newline bitfld.long 0x0 22. "CANFD3_IPI_INT_CE,ipi_int_ce from CANFD3 Correctable error interrupt" "0,1" newline bitfld.long 0x0 21. "CANFD2_IPI_INT_NCEFA,ipi_int_ncefa from CANFD2 Non correctable error int internal" "0,1" newline bitfld.long 0x0 20. "CANFD2_IPI_INT_NCEHA,ipi_int_nceha from CANFD2 Non correctable error int host" "0,1" newline bitfld.long 0x0 19. "CANFD2_IPI_INT_CE,ipi_int_ce from CANFD2 Correctable error interrupt" "0,1" newline bitfld.long 0x0 18. "CANFD1_IPI_INT_NCEFA,ipi_int_ncefa from CANFD1 Non correctable error int internal" "0,1" newline bitfld.long 0x0 17. "CANFD1_IPI_INT_NCEHA,ipi_int_nceha from CANFD1 Non correctable error int host" "0,1" newline bitfld.long 0x0 16. "CANFD1_IPI_INT_CE,ipi_int_ce from CANFD1 Correctable error interrupt" "0,1" newline bitfld.long 0x0 15. "ENET2_SBD_SFTY_UE_INTR_O,sbd_sfty_ue_intr_o from ENET2 None" "0,1" newline bitfld.long 0x0 14. "ENET2_SBD_SFTY_CE_INTR_O,sbd_sfty_ce_intr_o from ENET2 None" "0,1" newline bitfld.long 0x0 13. "ENET1_SBD_SFTY_UE_INTR_O,sbd_sfty_ue_intr_o from ENET1 None" "0,1" newline bitfld.long 0x0 12. "ENET1_SBD_SFTY_CE_INTR_O,sbd_sfty_ce_intr_o from ENET1 None" "0,1" newline bitfld.long 0x0 11. "ROMC2_MUL_ERR_INT,mul_err_int from ROMC2 None" "0,1" newline bitfld.long 0x0 10. "ROMC2_SIG_ERR_INT,sig_err_int from ROMC2 None" "0,1" newline bitfld.long 0x0 9. "ROMC1_MUL_ERR_INT,mul_err_int from ROMC1 None" "0,1" newline bitfld.long 0x0 8. "ROMC1_SIG_ERR_INT,sig_err_int from ROMC1 None" "0,1" newline bitfld.long 0x0 7. "IRAM4_MUL_ERR_INT,mul_err_int from IRAM4 None" "0,1" newline bitfld.long 0x0 6. "IRAM4_SIG_ERR_INT,sig_err_int from IRAM4 None" "0,1" newline bitfld.long 0x0 5. "IRAM3_MUL_ERR_INT,mul_err_int from IRAM3 None" "0,1" newline bitfld.long 0x0 4. "IRAM3_SIG_ERR_INT,sig_err_int from IRAM3 None" "0,1" newline bitfld.long 0x0 3. "IRAM2_MUL_ERR_INT,mul_err_int from IRAM2 None" "0,1" newline bitfld.long 0x0 2. "IRAM2_SIG_ERR_INT,sig_err_int from IRAM2 None" "0,1" newline bitfld.long 0x0 1. "IRAM1_MUL_ERR_INT,mul_err_int from IRAM1 None" "0,1" newline bitfld.long 0x0 0. "IRAM1_SIG_ERR_INT,sig_err_int from IRAM1 None" "0,1" repeat.end rgroup.long 0xA4++0x3 line.long 0x0 "INT_STATUS9,Interrupt status" bitfld.long 0x0 30. "PVT_SNS_SAF_PVT_INT_1,pvt_int_1 from PVT_SNS_SAF None" "0,1" newline bitfld.long 0x0 29. "PVT_SNS_SAF_PVT_INT_0,pvt_int_0 from PVT_SNS_SAF None" "0,1" newline bitfld.long 0x0 28. "PVT_SNS_SEC_PVT_INT_1,pvt_int_1 from PVT_SNS_SEC None" "0,1" newline bitfld.long 0x0 27. "PVT_SNS_SEC_PVT_INT_0,pvt_int_0 from PVT_SNS_SEC None" "0,1" newline bitfld.long 0x0 26. "WDT8_ILL_SEQ_REFR_INT,ill_seq_refr_int from WDT8 None" "0,1" newline bitfld.long 0x0 25. "WDT8_ILL_WIN_REFR_INT,ill_win_refr_int from WDT8 None" "0,1" newline bitfld.long 0x0 24. "WDT8_OVFLOW_INT,ovflow_int from WDT8 None" "0,1" newline bitfld.long 0x0 23. "WDT7_ILL_SEQ_REFR_INT,ill_seq_refr_int from WDT7 None" "0,1" newline bitfld.long 0x0 22. "WDT7_ILL_WIN_REFR_INT,ill_win_refr_int from WDT7 None" "0,1" newline bitfld.long 0x0 21. "WDT7_OVFLOW_INT,ovflow_int from WDT7 None" "0,1" newline bitfld.long 0x0 20. "WDT6_ILL_SEQ_REFR_INT,ill_seq_refr_int from WDT6 None" "0,1" newline bitfld.long 0x0 19. "WDT6_ILL_WIN_REFR_INT,ill_win_refr_int from WDT6 None" "0,1" newline bitfld.long 0x0 18. "WDT6_OVFLOW_INT,ovflow_int from WDT6 None" "0,1" newline bitfld.long 0x0 17. "WDT5_ILL_SEQ_REFR_INT,ill_seq_refr_int from WDT5 None" "0,1" newline bitfld.long 0x0 16. "WDT5_ILL_WIN_REFR_INT,ill_win_refr_int from WDT5 None" "0,1" newline bitfld.long 0x0 15. "WDT5_OVFLOW_INT,ovflow_int from WDT5 None" "0,1" newline bitfld.long 0x0 14. "WDT4_ILL_SEQ_REFR_INT,ill_seq_refr_int from WDT4 None" "0,1" newline bitfld.long 0x0 13. "WDT4_ILL_WIN_REFR_INT,ill_win_refr_int from WDT4 None" "0,1" newline bitfld.long 0x0 12. "WDT4_OVFLOW_INT,ovflow_int from WDT4 None" "0,1" newline bitfld.long 0x0 11. "WDT3_ILL_SEQ_REFR_INT,ill_seq_refr_int from WDT3 None" "0,1" newline bitfld.long 0x0 10. "WDT3_ILL_WIN_REFR_INT,ill_win_refr_int from WDT3 None" "0,1" newline bitfld.long 0x0 9. "WDT3_OVFLOW_INT,ovflow_int from WDT3 None" "0,1" newline bitfld.long 0x0 8. "WDT2_ILL_SEQ_REFR_INT,ill_seq_refr_int from WDT2 None" "0,1" newline bitfld.long 0x0 7. "WDT2_ILL_WIN_REFR_INT,ill_win_refr_int from WDT2 None" "0,1" newline bitfld.long 0x0 6. "WDT2_OVFLOW_INT,ovflow_int from WDT2 None" "0,1" newline bitfld.long 0x0 5. "WDT1_ILL_SEQ_REFR_INT,ill_seq_refr_int from WDT1 None" "0,1" newline bitfld.long 0x0 4. "WDT1_ILL_WIN_REFR_INT,ill_win_refr_int from WDT1 None" "0,1" newline bitfld.long 0x0 3. "WDT1_OVFLOW_INT,ovflow_int from WDT1 None" "0,1" newline bitfld.long 0x0 2. "PWR_LAT_RTC_AP_POWER_LAT,ap_power_lat from PWR_LAT_RTC AP domain power fail" "0,1" newline bitfld.long 0x0 1. "PWR_LAT_RTC_SAF_POWER_LAT,saf_power_lat from PWR_LAT_RTC SAF domain power fail" "0,1" newline bitfld.long 0x0 0. "PWR_LAT_SAF_SAF_POWER_LAT,saf_power_lat from PWR_LAT_SAF SAF power fail" "0,1" group.long 0x100++0x3 line.long 0x0 "INT_ENABLE_00,Interrupt Enable 0" bitfld.long 0x0 31. "CANFD6_IPI_INT_CE,ipi_int_ce from CANFD6 Correctable error interrupt" "0,1" newline bitfld.long 0x0 30. "CANFD5_IPI_INT_NCEFA,ipi_int_ncefa from CANFD5 Non correctable error int internal" "0,1" newline bitfld.long 0x0 29. "CANFD5_IPI_INT_NCEHA,ipi_int_nceha from CANFD5 Non correctable error int host" "0,1" newline bitfld.long 0x0 28. "CANFD5_IPI_INT_CE,ipi_int_ce from CANFD5 Correctable error interrupt" "0,1" newline bitfld.long 0x0 27. "CANFD4_IPI_INT_NCEFA,ipi_int_ncefa from CANFD4 Non correctable error int internal" "0,1" newline bitfld.long 0x0 26. "CANFD4_IPI_INT_NCEHA,ipi_int_nceha from CANFD4 Non correctable error int host" "0,1" newline bitfld.long 0x0 25. "CANFD4_IPI_INT_CE,ipi_int_ce from CANFD4 Correctable error interrupt" "0,1" newline bitfld.long 0x0 24. "CANFD3_IPI_INT_NCEFA,ipi_int_ncefa from CANFD3 Non correctable error int internal" "0,1" newline bitfld.long 0x0 23. "CANFD3_IPI_INT_NCEHA,ipi_int_nceha from CANFD3 Non correctable error int host" "0,1" newline bitfld.long 0x0 22. "CANFD3_IPI_INT_CE,ipi_int_ce from CANFD3 Correctable error interrupt" "0,1" newline bitfld.long 0x0 21. "CANFD2_IPI_INT_NCEFA,ipi_int_ncefa from CANFD2 Non correctable error int internal" "0,1" newline bitfld.long 0x0 20. "CANFD2_IPI_INT_NCEHA,ipi_int_nceha from CANFD2 Non correctable error int host" "0,1" newline bitfld.long 0x0 19. "CANFD2_IPI_INT_CE,ipi_int_ce from CANFD2 Correctable error interrupt" "0,1" newline bitfld.long 0x0 18. "CANFD1_IPI_INT_NCEFA,ipi_int_ncefa from CANFD1 Non correctable error int internal" "0,1" newline bitfld.long 0x0 17. "CANFD1_IPI_INT_NCEHA,ipi_int_nceha from CANFD1 Non correctable error int host" "0,1" newline bitfld.long 0x0 16. "CANFD1_IPI_INT_CE,ipi_int_ce from CANFD1 Correctable error interrupt" "0,1" newline bitfld.long 0x0 15. "ENET2_SBD_SFTY_UE_INTR_O,sbd_sfty_ue_intr_o from ENET2 None" "0,1" newline bitfld.long 0x0 14. "ENET2_SBD_SFTY_CE_INTR_O,sbd_sfty_ce_intr_o from ENET2 None" "0,1" newline bitfld.long 0x0 13. "ENET1_SBD_SFTY_UE_INTR_O,sbd_sfty_ue_intr_o from ENET1 None" "0,1" newline bitfld.long 0x0 12. "ENET1_SBD_SFTY_CE_INTR_O,sbd_sfty_ce_intr_o from ENET1 None" "0,1" newline bitfld.long 0x0 11. "RWMC2_MUL_ERR_INT,mul_err_int from RWMC2 None" "0,1" newline bitfld.long 0x0 10. "RWMC2_SIG_ERR_INT,sig_err_int from RWMC2 None" "0,1" newline bitfld.long 0x0 9. "RWMC1_MUL_ERR_INT,mul_err_int from RWMC1 None" "0,1" newline bitfld.long 0x0 8. "RWMC1_SIG_ERR_INT,sig_err_int from RWMC1 None" "0,1" newline bitfld.long 0x0 7. "IRAM4_MUL_ERR_INT,mul_err_int from IRAM4 None" "0,1" newline bitfld.long 0x0 6. "IRAM4_SIG_ERR_INT,sig_err_int from IRAM4 None" "0,1" newline bitfld.long 0x0 5. "IRAM3_MUL_ERR_INT,mul_err_int from IRAM3 None" "0,1" newline bitfld.long 0x0 4. "IRAM3_SIG_ERR_INT,sig_err_int from IRAM3 None" "0,1" newline bitfld.long 0x0 3. "IRAM2_MUL_ERR_INT,mul_err_int from IRAM2 None" "0,1" newline bitfld.long 0x0 2. "IRAM2_SIG_ERR_INT,sig_err_int from IRAM2 None" "0,1" newline bitfld.long 0x0 1. "IRAM1_MUL_ERR_INT,mul_err_int from IRAM1 None" "0,1" newline bitfld.long 0x0 0. "IRAM1_SIG_ERR_INT,sig_err_int from IRAM1 None" "0,1" repeat 16. (list 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0xA 0xB 0xC 0xD 0xE 0xF 0x10 0x11 )(list 0x0 0x4 0x8 0xC 0x10 0x14 0x18 0x1C 0x7C 0x80 0x84 0x88 0x8C 0x90 0x94 0x98 ) rgroup.long ($2+0x104)++0x3 line.long 0x0 "INT_ENABLE_$1,Interrupt Enable 0" bitfld.long 0x0 31. "NOC_SEC_S_14_MAINSGLDATAECCERR,s_14_mainSglDataEccErr from NOC_SEC None" "0,1" newline bitfld.long 0x0 30. "NOC_SEC_S_13_MAINSGLDATAECCERR,s_13_mainSglDataEccErr from NOC_SEC None" "0,1" newline bitfld.long 0x0 29. "NOC_SEC_S_3_MAINSGLDATAECCERR,s_3_mainSglDataEccErr from NOC_SEC None" "0,1" newline bitfld.long 0x0 28. "NOC_SEC_S_2_MAINSGLDATAECCERR,s_2_mainSglDataEccErr from NOC_SEC None" "0,1" newline bitfld.long 0x0 27. "NOC_SEC_S_1_MAINSGLECCERR,s_1_mainSglEccErr from NOC_SEC None" "0,1" newline bitfld.long 0x0 26. "NOC_SEC_S_0_MAINSGLECCERR,s_0_mainSglEccErr from NOC_SEC None" "0,1" newline bitfld.long 0x0 25. "NOC_SEC_M_9_I_MAININITIATOR_TIMEOUT_FAULT,m_9_I_mainInitiator_Timeout_Fault from NOC_SEC None" "0,1" newline bitfld.long 0x0 24. "NOC_SEC_M_8_I_MAININITIATOR_TIMEOUT_FAULT,m_8_I_mainInitiator_Timeout_Fault from NOC_SEC None" "0,1" newline bitfld.long 0x0 23. "NOC_SEC_M_7_I_MAININITIATOR_TIMEOUT_FAULT,m_7_I_mainInitiator_Timeout_Fault from NOC_SEC None" "0,1" newline bitfld.long 0x0 22. "NOC_SEC_M_6_I_MAININITIATOR_TIMEOUT_FAULT,m_6_I_mainInitiator_Timeout_Fault from NOC_SEC None" "0,1" newline bitfld.long 0x0 21. "NOC_SEC_M_5_I_MAININITIATOR_TIMEOUT_FAULT,m_5_I_mainInitiator_Timeout_Fault from NOC_SEC None" "0,1" newline bitfld.long 0x0 20. "NOC_SEC_M_5_MAINSGLDATAECCERR,m_5_mainSglDataEccErr from NOC_SEC None" "0,1" newline bitfld.long 0x0 19. "NOC_SEC_M_5_MAINSGLAWADDRECCERR,m_5_mainSglAwAddrEccErr from NOC_SEC None" "0,1" newline bitfld.long 0x0 18. "NOC_SEC_M_5_MAINSGLARADDRECCERR,m_5_mainSglArAddrEccErr from NOC_SEC None" "0,1" newline bitfld.long 0x0 17. "NOC_SEC_M_3_I_MAININITIATOR_TIMEOUT_FAULT,m_3_I_mainInitiator_Timeout_Fault from NOC_SEC None" "0,1" newline bitfld.long 0x0 16. "NOC_SEC_M_3_MAINSGLECCERR,m_3_mainSglEccErr from NOC_SEC Actually m_1_mainSglEccErr" "0,1" newline bitfld.long 0x0 15. "NOC_SEC_M_2_I_MAININITIATOR_TIMEOUT_FAULT,m_2_I_mainInitiator_Timeout_Fault from NOC_SEC None" "0,1" newline bitfld.long 0x0 14. "NOC_SEC_M_2_MAINSGLECCERR,m_2_mainSglEccErr from NOC_SEC Actually m_0_mainSglEccErr" "0,1" newline bitfld.long 0x0 13. "NOC_SEC_M_1_I_MAININITIATOR_TIMEOUT_FAULT,m_1_I_mainInitiator_Timeout_Fault from NOC_SEC None" "0,1" newline bitfld.long 0x0 12. "NOC_SEC_M_1_MAINSGLECCERR,m_1_mainSglEccErr from NOC_SEC Actually m_3_mainSglEccErr" "0,1" newline bitfld.long 0x0 11. "NOC_SEC_M_0_I_MAININITIATOR_TIMEOUT_FAULT,m_0_I_mainInitiator_Timeout_Fault from NOC_SEC None" "0,1" newline bitfld.long 0x0 10. "NOC_SEC_M_0_MAINSGLECCERR,m_0_mainSglEccErr from NOC_SEC Actually m_2_mainSglEccErr" "0,1" newline bitfld.long 0x0 9. "NOC_SEC_PD_SEC_MAINMISSIONINT,PD_SEC_mainMissionInt from NOC_SEC None OR ~PD_SEC_mainMissionIntBar from NOC_SEC None" "0,1" newline bitfld.long 0x0 8. "NOC_SEC_PD_SEC_MAINLATENTINT,PD_SEC_mainLatentInt from NOC_SEC None OR ~PD_SEC_mainLatentIntBar from NOC_SEC None" "0,1" newline bitfld.long 0x0 7. "CANFD8_IPI_INT_NCEFA,ipi_int_ncefa from CANFD8 Non correctable error int internal" "0,1" newline bitfld.long 0x0 6. "CANFD8_IPI_INT_NCEHA,ipi_int_nceha from CANFD8 Non correctable error int host" "0,1" newline bitfld.long 0x0 5. "CANFD8_IPI_INT_CE,ipi_int_ce from CANFD8 Correctable error interrupt" "0,1" newline bitfld.long 0x0 4. "CANFD7_IPI_INT_NCEFA,ipi_int_ncefa from CANFD7 Non correctable error int internal" "0,1" newline bitfld.long 0x0 3. "CANFD7_IPI_INT_NCEHA,ipi_int_nceha from CANFD7 Non correctable error int host" "0,1" newline bitfld.long 0x0 2. "CANFD7_IPI_INT_CE,ipi_int_ce from CANFD7 Correctable error interrupt" "0,1" newline bitfld.long 0x0 1. "CANFD6_IPI_INT_NCEFA,ipi_int_ncefa from CANFD6 Non correctable error int internal" "0,1" newline bitfld.long 0x0 0. "CANFD6_IPI_INT_NCEHA,ipi_int_nceha from CANFD6 Non correctable error int host" "0,1" repeat.end repeat 15. (list 0x12 0x14 0x15 0x16 0x17 0x18 0x19 0x1A 0x1B 0x1C 0x1E 0x1F 0x24 0x25 0x26 )(list 0x9C 0xFC 0x100 0x104 0x108 0x10C 0x110 0x114 0x118 0x11C 0x17C 0x180 0x194 0x198 0x19C ) rgroup.long ($2+0x104)++0x3 line.long 0x0 "INT_ENABLE_$1,Interrupt Enable 0" bitfld.long 0x0 31. "NOC_SEC_S_14_MAINSGLDATAECCERR,s_14_mainSglDataEccErr from NOC_SEC None" "0,1" newline bitfld.long 0x0 30. "NOC_SEC_S_13_MAINSGLDATAECCERR,s_13_mainSglDataEccErr from NOC_SEC None" "0,1" newline bitfld.long 0x0 29. "NOC_SEC_S_3_MAINSGLDATAECCERR,s_3_mainSglDataEccErr from NOC_SEC None" "0,1" newline bitfld.long 0x0 28. "NOC_SEC_S_2_MAINSGLDATAECCERR,s_2_mainSglDataEccErr from NOC_SEC None" "0,1" newline bitfld.long 0x0 27. "NOC_SEC_S_1_MAINSGLECCERR,s_1_mainSglEccErr from NOC_SEC None" "0,1" newline bitfld.long 0x0 26. "NOC_SEC_S_0_MAINSGLECCERR,s_0_mainSglEccErr from NOC_SEC None" "0,1" newline bitfld.long 0x0 25. "NOC_SEC_M_9_I_MAININITIATOR_TIMEOUT_FAULT,m_9_I_mainInitiator_Timeout_Fault from NOC_SEC None" "0,1" newline bitfld.long 0x0 24. "NOC_SEC_M_8_I_MAININITIATOR_TIMEOUT_FAULT,m_8_I_mainInitiator_Timeout_Fault from NOC_SEC None" "0,1" newline bitfld.long 0x0 23. "NOC_SEC_M_7_I_MAININITIATOR_TIMEOUT_FAULT,m_7_I_mainInitiator_Timeout_Fault from NOC_SEC None" "0,1" newline bitfld.long 0x0 22. "NOC_SEC_M_6_I_MAININITIATOR_TIMEOUT_FAULT,m_6_I_mainInitiator_Timeout_Fault from NOC_SEC None" "0,1" newline bitfld.long 0x0 21. "NOC_SEC_M_5_I_MAININITIATOR_TIMEOUT_FAULT,m_5_I_mainInitiator_Timeout_Fault from NOC_SEC None" "0,1" newline bitfld.long 0x0 20. "NOC_SEC_M_5_MAINSGLDATAECCERR,m_5_mainSglDataEccErr from NOC_SEC None" "0,1" newline bitfld.long 0x0 19. "NOC_SEC_M_5_MAINSGLAWADDRECCERR,m_5_mainSglAwAddrEccErr from NOC_SEC None" "0,1" newline bitfld.long 0x0 18. "NOC_SEC_M_5_MAINSGLARADDRECCERR,m_5_mainSglArAddrEccErr from NOC_SEC None" "0,1" newline bitfld.long 0x0 17. "NOC_SEC_M_3_I_MAININITIATOR_TIMEOUT_FAULT,m_3_I_mainInitiator_Timeout_Fault from NOC_SEC None" "0,1" newline bitfld.long 0x0 16. "NOC_SEC_M_3_MAINSGLECCERR,m_3_mainSglEccErr from NOC_SEC Actually m_1_mainSglEccErr" "0,1" newline bitfld.long 0x0 15. "NOC_SEC_M_2_I_MAININITIATOR_TIMEOUT_FAULT,m_2_I_mainInitiator_Timeout_Fault from NOC_SEC None" "0,1" newline bitfld.long 0x0 14. "NOC_SEC_M_2_MAINSGLECCERR,m_2_mainSglEccErr from NOC_SEC Actually m_0_mainSglEccErr" "0,1" newline bitfld.long 0x0 13. "NOC_SEC_M_1_I_MAININITIATOR_TIMEOUT_FAULT,m_1_I_mainInitiator_Timeout_Fault from NOC_SEC None" "0,1" newline bitfld.long 0x0 12. "NOC_SEC_M_1_MAINSGLECCERR,m_1_mainSglEccErr from NOC_SEC Actually m_3_mainSglEccErr" "0,1" newline bitfld.long 0x0 11. "NOC_SEC_M_0_I_MAININITIATOR_TIMEOUT_FAULT,m_0_I_mainInitiator_Timeout_Fault from NOC_SEC None" "0,1" newline bitfld.long 0x0 10. "NOC_SEC_M_0_MAINSGLECCERR,m_0_mainSglEccErr from NOC_SEC Actually m_2_mainSglEccErr" "0,1" newline bitfld.long 0x0 9. "NOC_SEC_PD_SEC_MAINMISSIONINT,PD_SEC_mainMissionInt from NOC_SEC None OR ~PD_SEC_mainMissionIntBar from NOC_SEC None" "0,1" newline bitfld.long 0x0 8. "NOC_SEC_PD_SEC_MAINLATENTINT,PD_SEC_mainLatentInt from NOC_SEC None OR ~PD_SEC_mainLatentIntBar from NOC_SEC None" "0,1" newline bitfld.long 0x0 7. "CANFD8_IPI_INT_NCEFA,ipi_int_ncefa from CANFD8 Non correctable error int internal" "0,1" newline bitfld.long 0x0 6. "CANFD8_IPI_INT_NCEHA,ipi_int_nceha from CANFD8 Non correctable error int host" "0,1" newline bitfld.long 0x0 5. "CANFD8_IPI_INT_CE,ipi_int_ce from CANFD8 Correctable error interrupt" "0,1" newline bitfld.long 0x0 4. "CANFD7_IPI_INT_NCEFA,ipi_int_ncefa from CANFD7 Non correctable error int internal" "0,1" newline bitfld.long 0x0 3. "CANFD7_IPI_INT_NCEHA,ipi_int_nceha from CANFD7 Non correctable error int host" "0,1" newline bitfld.long 0x0 2. "CANFD7_IPI_INT_CE,ipi_int_ce from CANFD7 Correctable error interrupt" "0,1" newline bitfld.long 0x0 1. "CANFD6_IPI_INT_NCEFA,ipi_int_ncefa from CANFD6 Non correctable error int internal" "0,1" newline bitfld.long 0x0 0. "CANFD6_IPI_INT_NCEHA,ipi_int_nceha from CANFD6 Non correctable error int host" "0,1" repeat.end repeat 4. (list 0x9 0x13 0x1D 0x27 )(list 0x0 0x80 0x100 0x180 ) rgroup.long ($2+0x124)++0x3 line.long 0x0 "INT_ENABLE_$1,Interrupt Enable 0" bitfld.long 0x0 30. "PVT_SNS_SAF_PVT_INT_1,pvt_int_1 from PVT_SNS_SAF None" "0,1" newline bitfld.long 0x0 29. "PVT_SNS_SAF_PVT_INT_0,pvt_int_0 from PVT_SNS_SAF None" "0,1" newline bitfld.long 0x0 28. "PVT_SNS_SEC_PVT_INT_1,pvt_int_1 from PVT_SNS_SEC None" "0,1" newline bitfld.long 0x0 27. "PVT_SNS_SEC_PVT_INT_0,pvt_int_0 from PVT_SNS_SEC None" "0,1" newline bitfld.long 0x0 26. "WDT8_ILL_SEQ_REFR_INT,ill_seq_refr_int from WDT8 None" "0,1" newline bitfld.long 0x0 25. "WDT8_ILL_WIN_REFR_INT,ill_win_refr_int from WDT8 None" "0,1" newline bitfld.long 0x0 24. "WDT8_OVFLOW_INT,ovflow_int from WDT8 None" "0,1" newline bitfld.long 0x0 23. "WDT7_ILL_SEQ_REFR_INT,ill_seq_refr_int from WDT7 None" "0,1" newline bitfld.long 0x0 22. "WDT7_ILL_WIN_REFR_INT,ill_win_refr_int from WDT7 None" "0,1" newline bitfld.long 0x0 21. "WDT7_OVFLOW_INT,ovflow_int from WDT7 None" "0,1" newline bitfld.long 0x0 20. "WDT6_ILL_SEQ_REFR_INT,ill_seq_refr_int from WDT6 None" "0,1" newline bitfld.long 0x0 19. "WDT6_ILL_WIN_REFR_INT,ill_win_refr_int from WDT6 None" "0,1" newline bitfld.long 0x0 18. "WDT6_OVFLOW_INT,ovflow_int from WDT6 None" "0,1" newline bitfld.long 0x0 17. "WDT5_ILL_SEQ_REFR_INT,ill_seq_refr_int from WDT5 None" "0,1" newline bitfld.long 0x0 16. "WDT5_ILL_WIN_REFR_INT,ill_win_refr_int from WDT5 None" "0,1" newline bitfld.long 0x0 15. "WDT5_OVFLOW_INT,ovflow_int from WDT5 None" "0,1" newline bitfld.long 0x0 14. "WDT4_ILL_SEQ_REFR_INT,ill_seq_refr_int from WDT4 None" "0,1" newline bitfld.long 0x0 13. "WDT4_ILL_WIN_REFR_INT,ill_win_refr_int from WDT4 None" "0,1" newline bitfld.long 0x0 12. "WDT4_OVFLOW_INT,ovflow_int from WDT4 None" "0,1" newline bitfld.long 0x0 11. "WDT3_ILL_SEQ_REFR_INT,ill_seq_refr_int from WDT3 None" "0,1" newline bitfld.long 0x0 10. "WDT3_ILL_WIN_REFR_INT,ill_win_refr_int from WDT3 None" "0,1" newline bitfld.long 0x0 9. "WDT3_OVFLOW_INT,ovflow_int from WDT3 None" "0,1" newline bitfld.long 0x0 8. "WDT2_ILL_SEQ_REFR_INT,ill_seq_refr_int from WDT2 None" "0,1" newline bitfld.long 0x0 7. "WDT2_ILL_WIN_REFR_INT,ill_win_refr_int from WDT2 None" "0,1" newline bitfld.long 0x0 6. "WDT2_OVFLOW_INT,ovflow_int from WDT2 None" "0,1" newline bitfld.long 0x0 5. "WDT1_ILL_SEQ_REFR_INT,ill_seq_refr_int from WDT1 None" "0,1" newline bitfld.long 0x0 4. "WDT1_ILL_WIN_REFR_INT,ill_win_refr_int from WDT1 None" "0,1" newline bitfld.long 0x0 3. "WDT1_OVFLOW_INT,ovflow_int from WDT1 None" "0,1" newline bitfld.long 0x0 2. "PWR_LAT_RTC_AP_POWER_LAT,ap_power_lat from PWR_LAT_RTC AP domain power fail" "0,1" newline bitfld.long 0x0 1. "PWR_LAT_RTC_SAF_POWER_LAT,saf_power_lat from PWR_LAT_RTC SAF domain power fail" "0,1" newline bitfld.long 0x0 0. "PWR_LAT_SAF_SAF_POWER_LAT,saf_power_lat from PWR_LAT_SAF SAF power fail" "0,1" repeat.end repeat 5. (list 0x20 0x2A 0x34 0x3E 0x48 )(list 0x0 0x80 0x100 0x180 0x200 ) rgroup.long ($2+0x288)++0x3 line.long 0x0 "INT_ENABLE_$1,m_18_I_mainInitiator_Timeout_Fault from NOC_MAIN None" bitfld.long 0x0 31. "NOC_MAIN_M_18_I_MAININITIATOR_TIMEOUT_FAULT,m_18_I_mainInitiator_Timeout_Fault from NOC_MAIN None" "0,1" newline bitfld.long 0x0 30. "NOC_MAIN_M_17_I_MAININITIATOR_TIMEOUT_FAULT,m_17_I_mainInitiator_Timeout_Fault from NOC_MAIN None" "0,1" newline bitfld.long 0x0 29. "NOC_MAIN_M_14_I_MAININITIATOR_TIMEOUT_FAULT,m_14_I_mainInitiator_Timeout_Fault from NOC_MAIN None" "0,1" newline bitfld.long 0x0 28. "NOC_MAIN_M_13_I_MAININITIATOR_TIMEOUT_FAULT,m_13_I_mainInitiator_Timeout_Fault from NOC_MAIN None" "0,1" newline bitfld.long 0x0 27. "NOC_MAIN_M_12_I_MAININITIATOR_TIMEOUT_FAULT,m_12_I_mainInitiator_Timeout_Fault from NOC_MAIN None" "0,1" newline bitfld.long 0x0 26. "NOC_MAIN_M_12_MAINSGLARADDRECCERR,m_12_mainSglArAddrEccErr from NOC_MAIN None OR m_12_mainSglAwAddrEccErr from NOC_MAIN None OR m_12_mainSglDataEccErr from NOC_MAIN None" "0,1" newline bitfld.long 0x0 25. "NOC_MAIN_M_11_I_MAININITIATOR_TIMEOUT_FAULT,m_11_I_mainInitiator_Timeout_Fault from NOC_MAIN None" "0,1" newline bitfld.long 0x0 24. "NOC_MAIN_M_11_MAINSGLARADDRECCERR,m_11_mainSglArAddrEccErr from NOC_MAIN None OR m_11_mainSglAwAddrEccErr from NOC_MAIN None OR m_11_mainSglDataEccErr from NOC_MAIN None" "0,1" newline bitfld.long 0x0 23. "NOC_MAIN_M_10_I_MAININITIATOR_TIMEOUT_FAULT,m_10_I_mainInitiator_Timeout_Fault from NOC_MAIN None" "0,1" newline bitfld.long 0x0 22. "NOC_MAIN_M_9_I_MAININITIATOR_TIMEOUT_FAULT,m_9_I_mainInitiator_Timeout_Fault from NOC_MAIN None" "0,1" newline bitfld.long 0x0 21. "NOC_MAIN_M_8_I_MAININITIATOR_TIMEOUT_FAULT,m_8_I_mainInitiator_Timeout_Fault from NOC_MAIN None" "0,1" newline bitfld.long 0x0 20. "NOC_MAIN_M_7_I_MAININITIATOR_TIMEOUT_FAULT,m_7_I_mainInitiator_Timeout_Fault from NOC_MAIN None" "0,1" newline bitfld.long 0x0 19. "NOC_MAIN_M_6_I_MAININITIATOR_TIMEOUT_FAULT,m_6_I_mainInitiator_Timeout_Fault from NOC_MAIN None" "0,1" newline bitfld.long 0x0 18. "NOC_MAIN_M_5_I_MAININITIATOR_TIMEOUT_FAULT,m_5_I_mainInitiator_Timeout_Fault from NOC_MAIN None" "0,1" newline bitfld.long 0x0 17. "NOC_MAIN_M_4_I_MAININITIATOR_TIMEOUT_FAULT,m_4_I_mainInitiator_Timeout_Fault from NOC_MAIN None" "0,1" newline bitfld.long 0x0 16. "NOC_MAIN_M_3_I_MAININITIATOR_TIMEOUT_FAULT,m_3_I_mainInitiator_Timeout_Fault from NOC_MAIN None" "0,1" newline bitfld.long 0x0 15. "NOC_MAIN_M_2_I_MAININITIATOR_TIMEOUT_FAULT,m_2_I_mainInitiator_Timeout_Fault from NOC_MAIN None" "0,1" newline bitfld.long 0x0 14. "NOC_MAIN_M_1_I_MAININITIATOR_TIMEOUT_FAULT,m_1_I_mainInitiator_Timeout_Fault from NOC_MAIN None" "0,1" newline bitfld.long 0x0 13. "NOC_MAIN_M_0_I_MAININITIATOR_TIMEOUT_FAULT,m_0_I_mainInitiator_Timeout_Fault from NOC_MAIN None" "0,1" newline bitfld.long 0x0 12. "NOC_MAIN_SOC_MAINMISSIONINT,SOC_mainMissionInt from NOC_MAIN None OR ~SOC_mainMissionIntBar from NOC_MAIN None" "0,1" newline bitfld.long 0x0 11. "NOC_MAIN_SOC_MAINLATENTINT,SOC_mainLatentInt from NOC_MAIN None OR ~SOC_mainLatentIntBar from NOC_MAIN None" "0,1" newline bitfld.long 0x0 10. "NOC_VSN_S_3_MAINSGLDATAECCERR,s_3_mainSglDataEccErr from NOC_VSN None" "0,1" newline bitfld.long 0x0 9. "NOC_VSN_S_0_MAINSGLDATAECCERR,s_0_mainSglDataEccErr from NOC_VSN None OR PFaultInfoValid from VDSP None" "0,1" newline bitfld.long 0x0 8. "NOC_VSN_M_2_I_MAININITIATOR_TIMEOUT_FAULT,m_2_I_mainInitiator_Timeout_Fault from NOC_VSN None" "0,1" newline bitfld.long 0x0 7. "NOC_VSN_M_2_MAINSGLARADDRECCERR,m_2_mainSglArAddrEccErr from NOC_VSN None OR m_2_mainSglAwAddrEccErr from NOC_VSN None OR m_2_mainSglDataEccErr from NOC_VSN None" "0,1" newline bitfld.long 0x0 6. "NOC_VSN_M_1_I_MAININITIATOR_TIMEOUT_FAULT,m_1_I_mainInitiator_Timeout_Fault from NOC_VSN None" "0,1" newline bitfld.long 0x0 5. "NOC_VSN_M_1_MAINSGLARADDRECCERR,m_1_mainSglArAddrEccErr from NOC_VSN None OR m_1_mainSglAwAddrEccErr from NOC_VSN None OR m_1_mainSglDataEccErr from NOC_VSN None" "0,1" newline bitfld.long 0x0 4. "NOC_VSN_M_0_I_MAININITIATOR_TIMEOUT_FAULT,m_0_I_mainInitiator_Timeout_Fault from NOC_VSN None" "0,1" newline bitfld.long 0x0 3. "NOC_VSN_M_0_MAINSGLARADDRECCERR,m_0_mainSglArAddrEccErr from NOC_VSN None OR m_0_mainSglAwAddrEccErr from NOC_VSN None OR m_0_mainSglDataEccErr from NOC_VSN None" "0,1" newline bitfld.long 0x0 2. "NOC_VSN_PD_VSN_MAINMISSIONINT,PD_VSN_mainMissionInt from NOC_VSN None OR ~PD_VSN_mainMissionIntBar from NOC_VSN None" "0,1" newline bitfld.long 0x0 1. "NOC_VSN_PD_VSN_MAINLATENTINT,PD_VSN_mainLatentInt from NOC_VSN None OR ~PD_VSN_mainLatentIntBar from NOC_VSN None" "0,1" newline bitfld.long 0x0 0. "NOC_SEC_S_17_MAINSGLDATAECCERR,s_17_mainSglDataEccErr from NOC_SEC None" "0,1" repeat.end repeat 5. (list 0x21 0x2B 0x35 0x3F 0x49 )(list 0x0 0x80 0x100 0x180 0x200 ) rgroup.long ($2+0x28C)++0x3 line.long 0x0 "INT_ENABLE_$1,m_6_I_mainInitiator_Timeout_Fault from NOC_SAF None" bitfld.long 0x0 31. "NOC_SAF_M_6_I_MAININITIATOR_TIMEOUT_FAULT,m_6_I_mainInitiator_Timeout_Fault from NOC_SAF None" "0,1" newline bitfld.long 0x0 30. "NOC_SAF_M_5_I_MAININITIATOR_TIMEOUT_FAULT,m_5_I_mainInitiator_Timeout_Fault from NOC_SAF None" "0,1" newline bitfld.long 0x0 29. "NOC_SAF_M_4_I_MAININITIATOR_TIMEOUT_FAULT,m_4_I_mainInitiator_Timeout_Fault from NOC_SAF None" "0,1" newline bitfld.long 0x0 28. "NOC_SAF_M_4_MAINDUPL_SGLARADDRECCERR,m_4_mainDupl_SglArAddrEccErr from NOC_SAF None OR m_4_mainDupl_SglAwAddrEccErr from NOC_SAF None OR m_4_mainDupl_SglDataEccErr from NOC_SAF None" "0,1" newline bitfld.long 0x0 27. "NOC_SAF_M_4_MAINMAIN_SGLARADDRECCERR,m_4_mainMain_SglArAddrEccErr from NOC_SAF None OR m_4_mainMain_SglAwAddrEccErr from NOC_SAF None OR m_4_mainMain_SglDataEccErr from NOC_SAF None" "0,1" newline bitfld.long 0x0 26. "NOC_SAF_M_3_I_MAININITIATOR_TIMEOUT_FAULT,m_3_I_mainInitiator_Timeout_Fault from NOC_SAF None" "0,1" newline bitfld.long 0x0 25. "NOC_SAF_M_2_I_MAININITIATOR_TIMEOUT_FAULT,m_2_I_mainInitiator_Timeout_Fault from NOC_SAF None" "0,1" newline bitfld.long 0x0 24. "NOC_SAF_M_1_I_MAININITIATOR_TIMEOUT_FAULT,m_1_I_mainInitiator_Timeout_Fault from NOC_SAF None" "0,1" newline bitfld.long 0x0 23. "NOC_SAF_M_1_MAINMAIN_SGLECCERR,m_1_mainMain_SglEccErr from NOC_SAF None" "0,1" newline bitfld.long 0x0 22. "NOC_SAF_M_1_MAINDUPL_SGLECCERR,m_1_mainDupl_SglEccErr from NOC_SAF None" "0,1" newline bitfld.long 0x0 21. "NOC_SAF_M_0_I_MAININITIATOR_TIMEOUT_FAULT,m_0_I_mainInitiator_Timeout_Fault from NOC_SAF None" "0,1" newline bitfld.long 0x0 20. "NOC_SAF_M_0_MAINMAIN_SGLECCERR,m_0_mainMain_SglEccErr from NOC_SAF None" "0,1" newline bitfld.long 0x0 19. "NOC_SAF_M_0_MAINDUPL_SGLECCERR,m_0_mainDupl_SglEccErr from NOC_SAF None" "0,1" newline bitfld.long 0x0 18. "NOC_SAF_PD_SAF_MAINMISSIONINT,PD_SAF_mainMissionInt from NOC_SAF None OR ~PD_SAF_mainMissionIntBar from NOC_SAF None" "0,1" newline bitfld.long 0x0 17. "NOC_SAF_PD_SAF_MAINLATENTINT,PD_SAF_mainLatentInt from NOC_SAF None OR ~PD_SAF_mainLatentIntBar from NOC_SAF None" "0,1" newline bitfld.long 0x0 16. "NOC_MAINB_M_2_I_MAININITIATOR_TIMEOUT_FAULT,m_2_I_mainInitiator_Timeout_Fault from NOC_MAINB None" "0,1" newline bitfld.long 0x0 15. "NOC_MAINB_M_1_I_MAININITIATOR_TIMEOUT_FAULT,m_1_I_mainInitiator_Timeout_Fault from NOC_MAINB None" "0,1" newline bitfld.long 0x0 14. "NOC_MAINB_M_0_I_MAININITIATOR_TIMEOUT_FAULT,m_0_I_mainInitiator_Timeout_Fault from NOC_MAINB None" "0,1" newline bitfld.long 0x0 13. "NOC_MAINB_M_0_MAINSGLARADDRECCERR,m_0_mainSglArAddrEccErr from NOC_MAINB None OR m_0_mainSglAwAddrEccErr from NOC_MAINB None OR m_0_mainSglDataEccErr from NOC_MAINB None" "0,1" newline bitfld.long 0x0 12. "NOC_MAINB_HPIB_MAINMISSIONINT,HPIb_mainMissionInt from NOC_MAINB None OR ~SAF_mainMissionIntBar from NOC_MAINB None" "0,1" newline bitfld.long 0x0 11. "NOC_MAINB_HPIB_MAINLATENTINT,HPIb_mainLatentInt from NOC_MAINB None OR ~SAF_mainLatentIntBar from NOC_MAINB None" "0,1" newline bitfld.long 0x0 10. "NOC_MAIN_S_11_MAINSGLDATAECCERR,s_11_mainSglDataEccErr from NOC_MAIN None" "0,1" newline bitfld.long 0x0 9. "NOC_MAIN_S_4_MAINSGLDATAECCERR,s_4_mainSglDataEccErr from NOC_MAIN None" "0,1" newline bitfld.long 0x0 8. "NOC_MAIN_S_3_MAINSGLDATAECCERR,s_3_mainSglDataEccErr from NOC_MAIN None" "0,1" newline bitfld.long 0x0 7. "NOC_MAIN_S_0_SBP_MAINSGLDATAECCERR,s_0_sbp_mainSglDataEccErr from NOC_MAIN None" "0,1" newline bitfld.long 0x0 6. "NOC_MAIN_M_16_I_MAININITIATOR_TIMEOUT_FAULT,m_16_I_mainInitiator_Timeout_Fault from NOC_MAIN None OR m_24_I_mainInitiator_Timeout_Fault from NOC_MAIN None" "0,1" newline bitfld.long 0x0 5. "NOC_MAIN_M_24_MAINSGLARADDRECCERR,m_24_mainSglArAddrEccErr from NOC_MAIN None OR m_24_mainSglAwAddrEccErr from NOC_MAIN None OR m_24_mainSglDataEccErr from NOC_MAIN None" "0,1" newline bitfld.long 0x0 4. "NOC_MAIN_M_23_I_MAININITIATOR_TIMEOUT_FAULT,m_23_I_mainInitiator_Timeout_Fault from NOC_MAIN None" "0,1" newline bitfld.long 0x0 3. "NOC_MAIN_M_22_I_MAININITIATOR_TIMEOUT_FAULT,m_22_I_mainInitiator_Timeout_Fault from NOC_MAIN None" "0,1" newline bitfld.long 0x0 2. "NOC_MAIN_M_21_I_MAININITIATOR_TIMEOUT_FAULT,m_21_I_mainInitiator_Timeout_Fault from NOC_MAIN None" "0,1" newline bitfld.long 0x0 1. "NOC_MAIN_M_20_I_MAININITIATOR_TIMEOUT_FAULT,m_20_I_mainInitiator_Timeout_Fault from NOC_MAIN None" "0,1" newline bitfld.long 0x0 0. "NOC_MAIN_M_19_I_MAININITIATOR_TIMEOUT_FAULT,m_19_I_mainInitiator_Timeout_Fault from NOC_MAIN None" "0,1" repeat.end repeat 5. (list 0x22 0x2C 0x36 0x40 0x4A )(list 0x0 0x80 0x100 0x180 0x200 ) rgroup.long ($2+0x290)++0x3 line.long 0x0 "INT_ENABLE_$1,crc32_irq from DC2 None" bitfld.long 0x0 31. "DC2_CRC32_IRQ,crc32_irq from DC2 None" "0,1" newline bitfld.long 0x0 30. "DC2_DC_CH_UNDERRUN,dc_ch_underrun from DC2 None" "0,1" newline bitfld.long 0x0 29. "DC1_CRC32_IRQ,crc32_irq from DC1 None" "0,1" newline bitfld.long 0x0 28. "DC1_DC_CH_UNDERRUN,dc_ch_underrun from DC1 None" "0,1" newline bitfld.long 0x0 27. "DDR_SS_DDR_SS_FUNC_SAF_NONFATL_INT,ddr_ss_func_saf_nonfatl_int from DDR_SS None" "0,1" newline bitfld.long 0x0 26. "DDR_SS_DDR_SS_FUNC_SAF_FATL_INT,ddr_ss_func_saf_fatl_int from DDR_SS None" "0,1" newline bitfld.long 0x0 25. "BIPC_ENET1_ECC_ERR_MULTIPLE,ecc_err_multiple from BIPC_ENET1 None" "0,1" newline bitfld.long 0x0 24. "BIPC_ENET1_ECC_ERR_SINGLE,ecc_err_single from BIPC_ENET1 None" "0,1" newline bitfld.long 0x0 23. "BIPC_VDSP_ECC_ERR_MULTIPLE,ecc_err_multiple from BIPC_VDSP None" "0,1" newline bitfld.long 0x0 22. "BIPC_VDSP_ECC_ERR_SINGLE,ecc_err_single from BIPC_VDSP None" "0,1" newline bitfld.long 0x0 21. "BIPC_DDR_ECC_ERR_MULTIPLE,ecc_err_multiple from BIPC_DDR None" "0,1" newline bitfld.long 0x0 20. "BIPC_DDR_ECC_ERR_SINGLE,ecc_err_single from BIPC_DDR None" "0,1" newline bitfld.long 0x0 19. "MPC_DDR_UNC_ERR_INT,unc_err_int from MPC_DDR None" "0,1" newline bitfld.long 0x0 18. "MPC_DDR_COR_ERR_INT,cor_err_int from MPC_DDR None" "0,1" newline bitfld.long 0x0 17. "MPC_ROMC2_UNC_ERR_INT,unc_err_int from MPC_ROMC2 None" "0,1" newline bitfld.long 0x0 16. "MPC_ROMC2_COR_ERR_INT,cor_err_int from MPC_ROMC2 None" "0,1" newline bitfld.long 0x0 15. "MPC_IRAM4_UNC_ERR_INT,unc_err_int from MPC_IRAM4 None" "0,1" newline bitfld.long 0x0 14. "MPC_IRAM4_COR_ERR_INT,cor_err_int from MPC_IRAM4 None" "0,1" newline bitfld.long 0x0 13. "MPC_IRAM3_UNC_ERR_INT,unc_err_int from MPC_IRAM3 None" "0,1" newline bitfld.long 0x0 12. "MPC_IRAM3_COR_ERR_INT,cor_err_int from MPC_IRAM3 None" "0,1" newline bitfld.long 0x0 11. "MPC_IRAM2_UNC_ERR_INT,unc_err_int from MPC_IRAM2 None" "0,1" newline bitfld.long 0x0 10. "MPC_IRAM2_COR_ERR_INT,cor_err_int from MPC_IRAM2 None" "0,1" newline bitfld.long 0x0 9. "MPC_IRAM1_UNC_ERR_INT,unc_err_int from MPC_IRAM1 None" "0,1" newline bitfld.long 0x0 8. "MPC_IRAM1_COR_ERR_INT,cor_err_int from MPC_IRAM1 None" "0,1" newline bitfld.long 0x0 7. "NOC_SAF_S_4_MAINMAIN_SGLDATAECCERR,s_4_mainMain_SglDataEccErr from NOC_SAF None" "0,1" newline bitfld.long 0x0 6. "NOC_SAF_S_4_MAINDUPL_SGLDATAECCERR,s_4_mainDupl_SglDataEccErr from NOC_SAF None" "0,1" newline bitfld.long 0x0 5. "NOC_SAF_S_2_MAINMAIN_SGLDATAECCERR,s_2_mainMain_SglDataEccErr from NOC_SAF None" "0,1" newline bitfld.long 0x0 4. "NOC_SAF_S_2_MAINDUPL_SGLDATAECCERR,s_2_mainDupl_SglDataEccErr from NOC_SAF None" "0,1" newline bitfld.long 0x0 3. "NOC_SAF_S_1_MAINMAIN_SGLDATAECCERR,s_1_mainMain_SglDataEccErr from NOC_SAF None" "0,1" newline bitfld.long 0x0 2. "NOC_SAF_S_1_MAINDUPL_SGLDATAECCERR,s_1_mainDupl_SglDataEccErr from NOC_SAF None" "0,1" newline bitfld.long 0x0 1. "NOC_SAF_S_0_MAINMAIN_SGLECCERR,s_0_mainMain_SglEccErr from NOC_SAF None" "0,1" newline bitfld.long 0x0 0. "NOC_SAF_S_0_MAINDUPL_SGLECCERR,s_0_mainDupl_SglEccErr from NOC_SAF None" "0,1" repeat.end repeat 5. (list 0x23 0x2D 0x37 0x41 0x4B )(list 0x0 0x80 0x100 0x180 0x200 ) rgroup.long ($2+0x294)++0x3 line.long 0x0 "INT_ENABLE_$1,aximfatal0[0] from CR5_SAF data errors and any parity errors on the AXI master" bitfld.long 0x0 31. "CR5_SAF_AXIMFATAL0[0],aximfatal0[0] from CR5_SAF data errors and any parity errors on the AXI master" "0,1" newline bitfld.long 0x0 30. "CR5_SAF_PPHCORR0,pphcorr0 from CR5_SAF data errors on reads by the AHB Peripheral Port" "0,1" newline bitfld.long 0x0 29. "CR5_SAF_PPXCORR0,ppxcorr0 from CR5_SAF data errors on reads by the AXI Peripheral Port" "0,1" newline bitfld.long 0x0 28. "CR5_SAF_AXISCORR0,axiscorr0 from CR5_SAF data errors on writes to the AXI Slave" "0,1" newline bitfld.long 0x0 27. "CR5_SAF_AXIMCORR0,aximcorr0 from CR5_SAF data errors on reads by the AXI Master" "0,1" newline bitfld.long 0x0 26. "OSPI2_O_IRQ_UNCORR,o_irq_uncorr from OSPI2 None" "0,1" newline bitfld.long 0x0 25. "OSPI2_O_IRQ_CORR,o_irq_corr from OSPI2 None" "0,1" newline bitfld.long 0x0 24. "OSPI1_O_IRQ_UNCORR,o_irq_uncorr from OSPI1 None" "0,1" newline bitfld.long 0x0 23. "OSPI1_O_IRQ_CORR,o_irq_corr from OSPI1 None" "0,1" newline bitfld.long 0x0 22. "EFUSEC_FATAL_ERR_INT,fatal_err_int from EFUSEC None" "0,1" newline bitfld.long 0x0 21. "EFUSEC_NORMAL_ERR_INT,normal_err_int from EFUSEC None" "0,1" newline bitfld.long 0x0 20. "PCIE_SS_O_PCIEX1_SAFETY_CORR,o_pciex1_safety_corr from PCIE_SS PCIE correctable error" "0,1" newline bitfld.long 0x0 19. "PCIE_SS_O_PCIEX1_SAFETY_UNCORR,o_pciex1_safety_uncorr from PCIE_SS PCIE non correctable error" "0,1" newline bitfld.long 0x0 18. "PCIE_SS_O_PCIEX2_SAFETY_CORR,o_pciex2_safety_corr from PCIE_SS PCIE correctable error" "0,1" newline bitfld.long 0x0 17. "PCIE_SS_O_PCIEX2_SAFETY_UNCORR,o_pciex2_safety_uncorr from PCIE_SS PCIE non correctable error" "0,1" newline bitfld.long 0x0 16. "ADC_CHANNEL_EVENT4,channel_event4 from ADC None OR channel_event5 from ADC None OR channel_event6 from ADC None OR channel_event7 from ADC None" "0,1" newline bitfld.long 0x0 15. "ADC_CHANNEL_EVENT3,channel_event3 from ADC None" "0,1" newline bitfld.long 0x0 14. "ADC_CHANNEL_EVENT2,channel_event2 from ADC None" "0,1" newline bitfld.long 0x0 13. "ADC_CHANNEL_EVENT1,channel_event1 from ADC None" "0,1" newline bitfld.long 0x0 12. "ADC_CHANNEL_EVENT0,channel_event0 from ADC None" "0,1" newline bitfld.long 0x0 11. "VDSP_DOUBLEEXCEPTIONERROR,DoubleExceptionError from VDSP None" "0,1" newline bitfld.long 0x0 10. "VDSP_PFATALERROR,PFatalError from VDSP None" "0,1" newline bitfld.long 0x0 9. "VDSP_ERRORCORRECTED,ErrorCorrected from VDSP None" "0,1" newline bitfld.long 0x0 8. "DP3_DP_CH_UNDERRUN,dp_ch_underrun from DP3 None" "0,1" newline bitfld.long 0x0 7. "DP2_DP_CH_UNDERRUN,dp_ch_underrun from DP2 None" "0,1" newline bitfld.long 0x0 6. "DP1_DP_CH_UNDERRUN,dp_ch_underrun from DP1 None" "0,1" newline bitfld.long 0x0 5. "DC5_CRC32_IRQ,crc32_irq from DC5 None" "0,1" newline bitfld.long 0x0 4. "DC5_DC_CH_UNDERRUN,dc_ch_underrun from DC5 None" "0,1" newline bitfld.long 0x0 3. "DC4_CRC32_IRQ,crc32_irq from DC4 None" "0,1" newline bitfld.long 0x0 2. "DC4_DC_CH_UNDERRUN,dc_ch_underrun from DC4 None" "0,1" newline bitfld.long 0x0 1. "DC3_CRC32_IRQ,crc32_irq from DC3 None" "0,1" newline bitfld.long 0x0 0. "DC3_DC_CH_UNDERRUN,dc_ch_underrun from DC3 None" "0,1" repeat.end repeat 4. (list 0x28 0x32 0x3C 0x46 )(list 0x0 0x80 0x100 0x180 ) rgroup.long ($2+0x300)++0x3 line.long 0x0 "INT_ENABLE_$1,ipi_int_ce from CANFD6 Correctable error interrupt" bitfld.long 0x0 31. "CANFD6_IPI_INT_CE,ipi_int_ce from CANFD6 Correctable error interrupt" "0,1" newline bitfld.long 0x0 30. "CANFD5_IPI_INT_NCEFA,ipi_int_ncefa from CANFD5 Non correctable error int internal" "0,1" newline bitfld.long 0x0 29. "CANFD5_IPI_INT_NCEHA,ipi_int_nceha from CANFD5 Non correctable error int host" "0,1" newline bitfld.long 0x0 28. "CANFD5_IPI_INT_CE,ipi_int_ce from CANFD5 Correctable error interrupt" "0,1" newline bitfld.long 0x0 27. "CANFD4_IPI_INT_NCEFA,ipi_int_ncefa from CANFD4 Non correctable error int internal" "0,1" newline bitfld.long 0x0 26. "CANFD4_IPI_INT_NCEHA,ipi_int_nceha from CANFD4 Non correctable error int host" "0,1" newline bitfld.long 0x0 25. "CANFD4_IPI_INT_CE,ipi_int_ce from CANFD4 Correctable error interrupt" "0,1" newline bitfld.long 0x0 24. "CANFD3_IPI_INT_NCEFA,ipi_int_ncefa from CANFD3 Non correctable error int internal" "0,1" newline bitfld.long 0x0 23. "CANFD3_IPI_INT_NCEHA,ipi_int_nceha from CANFD3 Non correctable error int host" "0,1" newline bitfld.long 0x0 22. "CANFD3_IPI_INT_CE,ipi_int_ce from CANFD3 Correctable error interrupt" "0,1" newline bitfld.long 0x0 21. "CANFD2_IPI_INT_NCEFA,ipi_int_ncefa from CANFD2 Non correctable error int internal" "0,1" newline bitfld.long 0x0 20. "CANFD2_IPI_INT_NCEHA,ipi_int_nceha from CANFD2 Non correctable error int host" "0,1" newline bitfld.long 0x0 19. "CANFD2_IPI_INT_CE,ipi_int_ce from CANFD2 Correctable error interrupt" "0,1" newline bitfld.long 0x0 18. "CANFD1_IPI_INT_NCEFA,ipi_int_ncefa from CANFD1 Non correctable error int internal" "0,1" newline bitfld.long 0x0 17. "CANFD1_IPI_INT_NCEHA,ipi_int_nceha from CANFD1 Non correctable error int host" "0,1" newline bitfld.long 0x0 16. "CANFD1_IPI_INT_CE,ipi_int_ce from CANFD1 Correctable error interrupt" "0,1" newline bitfld.long 0x0 15. "ENET2_SBD_SFTY_UE_INTR_O,sbd_sfty_ue_intr_o from ENET2 None" "0,1" newline bitfld.long 0x0 14. "ENET2_SBD_SFTY_CE_INTR_O,sbd_sfty_ce_intr_o from ENET2 None" "0,1" newline bitfld.long 0x0 13. "ENET1_SBD_SFTY_UE_INTR_O,sbd_sfty_ue_intr_o from ENET1 None" "0,1" newline bitfld.long 0x0 12. "ENET1_SBD_SFTY_CE_INTR_O,sbd_sfty_ce_intr_o from ENET1 None" "0,1" newline bitfld.long 0x0 11. "ROMC2_MUL_ERR_INT,mul_err_int from ROMC2 None" "0,1" newline bitfld.long 0x0 10. "ROMC2_SIG_ERR_INT,sig_err_int from ROMC2 None" "0,1" newline bitfld.long 0x0 9. "ROMC1_MUL_ERR_INT,mul_err_int from ROMC1 None" "0,1" newline bitfld.long 0x0 8. "ROMC1_SIG_ERR_INT,sig_err_int from ROMC1 None" "0,1" newline bitfld.long 0x0 7. "IRAM4_MUL_ERR_INT,mul_err_int from IRAM4 None" "0,1" newline bitfld.long 0x0 6. "IRAM4_SIG_ERR_INT,sig_err_int from IRAM4 None" "0,1" newline bitfld.long 0x0 5. "IRAM3_MUL_ERR_INT,mul_err_int from IRAM3 None" "0,1" newline bitfld.long 0x0 4. "IRAM3_SIG_ERR_INT,sig_err_int from IRAM3 None" "0,1" newline bitfld.long 0x0 3. "IRAM2_MUL_ERR_INT,mul_err_int from IRAM2 None" "0,1" newline bitfld.long 0x0 2. "IRAM2_SIG_ERR_INT,sig_err_int from IRAM2 None" "0,1" newline bitfld.long 0x0 1. "IRAM1_MUL_ERR_INT,mul_err_int from IRAM1 None" "0,1" newline bitfld.long 0x0 0. "IRAM1_SIG_ERR_INT,sig_err_int from IRAM1 None" "0,1" repeat.end repeat 4. (list 0x29 0x33 0x3D 0x47 )(list 0x0 0x80 0x100 0x180 ) rgroup.long ($2+0x304)++0x3 line.long 0x0 "INT_ENABLE_$1,s_14_mainSglDataEccErr from NOC_SEC None" bitfld.long 0x0 31. "NOC_SEC_S_14_MAINSGLDATAECCERR,s_14_mainSglDataEccErr from NOC_SEC None" "0,1" newline bitfld.long 0x0 30. "NOC_SEC_S_13_MAINSGLDATAECCERR,s_13_mainSglDataEccErr from NOC_SEC None" "0,1" newline bitfld.long 0x0 29. "NOC_SEC_S_3_MAINSGLDATAECCERR,s_3_mainSglDataEccErr from NOC_SEC None" "0,1" newline bitfld.long 0x0 28. "NOC_SEC_S_2_MAINSGLDATAECCERR,s_2_mainSglDataEccErr from NOC_SEC None" "0,1" newline bitfld.long 0x0 27. "NOC_SEC_S_1_MAINSGLECCERR,s_1_mainSglEccErr from NOC_SEC None" "0,1" newline bitfld.long 0x0 26. "NOC_SEC_S_0_MAINSGLECCERR,s_0_mainSglEccErr from NOC_SEC None" "0,1" newline bitfld.long 0x0 25. "NOC_SEC_M_9_I_MAININITIATOR_TIMEOUT_FAULT,m_9_I_mainInitiator_Timeout_Fault from NOC_SEC None" "0,1" newline bitfld.long 0x0 24. "NOC_SEC_M_8_I_MAININITIATOR_TIMEOUT_FAULT,m_8_I_mainInitiator_Timeout_Fault from NOC_SEC None" "0,1" newline bitfld.long 0x0 23. "NOC_SEC_M_7_I_MAININITIATOR_TIMEOUT_FAULT,m_7_I_mainInitiator_Timeout_Fault from NOC_SEC None" "0,1" newline bitfld.long 0x0 22. "NOC_SEC_M_6_I_MAININITIATOR_TIMEOUT_FAULT,m_6_I_mainInitiator_Timeout_Fault from NOC_SEC None" "0,1" newline bitfld.long 0x0 21. "NOC_SEC_M_5_I_MAININITIATOR_TIMEOUT_FAULT,m_5_I_mainInitiator_Timeout_Fault from NOC_SEC None" "0,1" newline bitfld.long 0x0 20. "NOC_SEC_M_5_MAINSGLDATAECCERR,m_5_mainSglDataEccErr from NOC_SEC None" "0,1" newline bitfld.long 0x0 19. "NOC_SEC_M_5_MAINSGLAWADDRECCERR,m_5_mainSglAwAddrEccErr from NOC_SEC None" "0,1" newline bitfld.long 0x0 18. "NOC_SEC_M_5_MAINSGLARADDRECCERR,m_5_mainSglArAddrEccErr from NOC_SEC None" "0,1" newline bitfld.long 0x0 17. "NOC_SEC_M_3_I_MAININITIATOR_TIMEOUT_FAULT,m_3_I_mainInitiator_Timeout_Fault from NOC_SEC None" "0,1" newline bitfld.long 0x0 16. "NOC_SEC_M_3_MAINSGLECCERR,m_3_mainSglEccErr from NOC_SEC Actually m_1_mainSglEccErr" "0,1" newline bitfld.long 0x0 15. "NOC_SEC_M_2_I_MAININITIATOR_TIMEOUT_FAULT,m_2_I_mainInitiator_Timeout_Fault from NOC_SEC None" "0,1" newline bitfld.long 0x0 14. "NOC_SEC_M_2_MAINSGLECCERR,m_2_mainSglEccErr from NOC_SEC Actually m_0_mainSglEccErr" "0,1" newline bitfld.long 0x0 13. "NOC_SEC_M_1_I_MAININITIATOR_TIMEOUT_FAULT,m_1_I_mainInitiator_Timeout_Fault from NOC_SEC None" "0,1" newline bitfld.long 0x0 12. "NOC_SEC_M_1_MAINSGLECCERR,m_1_mainSglEccErr from NOC_SEC Actually m_3_mainSglEccErr" "0,1" newline bitfld.long 0x0 11. "NOC_SEC_M_0_I_MAININITIATOR_TIMEOUT_FAULT,m_0_I_mainInitiator_Timeout_Fault from NOC_SEC None" "0,1" newline bitfld.long 0x0 10. "NOC_SEC_M_0_MAINSGLECCERR,m_0_mainSglEccErr from NOC_SEC Actually m_2_mainSglEccErr" "0,1" newline bitfld.long 0x0 9. "NOC_SEC_PD_SEC_MAINMISSIONINT,PD_SEC_mainMissionInt from NOC_SEC None OR ~PD_SEC_mainMissionIntBar from NOC_SEC None" "0,1" newline bitfld.long 0x0 8. "NOC_SEC_PD_SEC_MAINLATENTINT,PD_SEC_mainLatentInt from NOC_SEC None OR ~PD_SEC_mainLatentIntBar from NOC_SEC None" "0,1" newline bitfld.long 0x0 7. "CANFD8_IPI_INT_NCEFA,ipi_int_ncefa from CANFD8 Non correctable error int internal" "0,1" newline bitfld.long 0x0 6. "CANFD8_IPI_INT_NCEHA,ipi_int_nceha from CANFD8 Non correctable error int host" "0,1" newline bitfld.long 0x0 5. "CANFD8_IPI_INT_CE,ipi_int_ce from CANFD8 Correctable error interrupt" "0,1" newline bitfld.long 0x0 4. "CANFD7_IPI_INT_NCEFA,ipi_int_ncefa from CANFD7 Non correctable error int internal" "0,1" newline bitfld.long 0x0 3. "CANFD7_IPI_INT_NCEHA,ipi_int_nceha from CANFD7 Non correctable error int host" "0,1" newline bitfld.long 0x0 2. "CANFD7_IPI_INT_CE,ipi_int_ce from CANFD7 Correctable error interrupt" "0,1" newline bitfld.long 0x0 1. "CANFD6_IPI_INT_NCEFA,ipi_int_ncefa from CANFD6 Non correctable error int internal" "0,1" newline bitfld.long 0x0 0. "CANFD6_IPI_INT_NCEHA,ipi_int_nceha from CANFD6 Non correctable error int host" "0,1" repeat.end repeat 4. (list 0x2E 0x38 0x42 0x4C )(list 0x0 0x80 0x100 0x180 ) rgroup.long ($2+0x318)++0x3 line.long 0x0 "INT_ENABLE_$1,ppxfatal0[1] from CR5_SEC data errors and any parity errors on the AXI Peripheral Port" bitfld.long 0x0 31. "CR5_SEC_PPXFATAL0[1],ppxfatal0[1] from CR5_SEC data errors and any parity errors on the AXI Peripheral Port" "0,1" newline bitfld.long 0x0 30. "CR5_SEC_PPXFATAL0[0],ppxfatal0[0] from CR5_SEC data errors and any parity errors on the AXI Peripheral Port" "0,1" newline bitfld.long 0x0 29. "CR5_SEC_AXISFATAL0[4],axisfatal0[4] from CR5_SEC data errors and any parity errors on the AXI slave" "0,1" newline bitfld.long 0x0 28. "CR5_SEC_AXISFATAL0[3],axisfatal0[3] from CR5_SEC data errors and any parity errors on the AXI slave" "0,1" newline bitfld.long 0x0 27. "CR5_SEC_AXISFATAL0[2],axisfatal0[2] from CR5_SEC data errors and any parity errors on the AXI slave" "0,1" newline bitfld.long 0x0 26. "CR5_SEC_AXISFATAL0[1],axisfatal0[1] from CR5_SEC data errors and any parity errors on the AXI slave" "0,1" newline bitfld.long 0x0 25. "CR5_SEC_AXISFATAL0[0],axisfatal0[0] from CR5_SEC data errors and any parity errors on the AXI slave" "0,1" newline bitfld.long 0x0 24. "CR5_SEC_AXIMFATAL0[4],aximfatal0[4] from CR5_SEC data errors and any parity errors on the AXI master" "0,1" newline bitfld.long 0x0 23. "CR5_SEC_AXIMFATAL0[3],aximfatal0[3] from CR5_SEC data errors and any parity errors on the AXI master" "0,1" newline bitfld.long 0x0 22. "CR5_SEC_AXIMFATAL0[2],aximfatal0[2] from CR5_SEC data errors and any parity errors on the AXI master" "0,1" newline bitfld.long 0x0 21. "CR5_SEC_AXIMFATAL0[1],aximfatal0[1] from CR5_SEC data errors and any parity errors on the AXI master" "0,1" newline bitfld.long 0x0 20. "CR5_SEC_AXIMFATAL0[0],aximfatal0[0] from CR5_SEC data errors and any parity errors on the AXI master" "0,1" newline bitfld.long 0x0 19. "CR5_SEC_PPHCORR0,pphcorr0 from CR5_SEC data errors on reads by the AHB Peripheral Port" "0,1" newline bitfld.long 0x0 18. "CR5_SEC_PPXCORR0,ppxcorr0 from CR5_SEC data errors on reads by the AXI Peripheral Port" "0,1" newline bitfld.long 0x0 17. "CR5_SEC_AXISCORR0,axiscorr0 from CR5_SEC data errors on writes to the AXI Slave" "0,1" newline bitfld.long 0x0 16. "CR5_SEC_AXIMCORR0,aximcorr0 from CR5_SEC data errors on reads by the AXI Master" "0,1" newline bitfld.long 0x0 15. "CR5_SAF_DCCMOUT2[0],dccmout2[0] from CR5_SAF LockStep compare fail" "0,1" newline bitfld.long 0x0 14. "CR5_SAF_DCCMOUT[0],dccmout[0] from CR5_SAF LockStep compare fail" "0,1" newline bitfld.long 0x0 13. "CR5_SAF_PPXFATAL0[4],ppxfatal0[4] from CR5_SAF data errors and any parity errors on the AXI Peripheral Port" "0,1" newline bitfld.long 0x0 12. "CR5_SAF_PPXFATAL0[3],ppxfatal0[3] from CR5_SAF data errors and any parity errors on the AXI Peripheral Port" "0,1" newline bitfld.long 0x0 11. "CR5_SAF_PPXFATAL0[2],ppxfatal0[2] from CR5_SAF data errors and any parity errors on the AXI Peripheral Port" "0,1" newline bitfld.long 0x0 10. "CR5_SAF_PPXFATAL0[1],ppxfatal0[1] from CR5_SAF data errors and any parity errors on the AXI Peripheral Port" "0,1" newline bitfld.long 0x0 9. "CR5_SAF_PPXFATAL0[0],ppxfatal0[0] from CR5_SAF data errors and any parity errors on the AXI Peripheral Port" "0,1" newline bitfld.long 0x0 8. "CR5_SAF_AXISFATAL0[4],axisfatal0[4] from CR5_SAF data errors and any parity errors on the AXI slave" "0,1" newline bitfld.long 0x0 7. "CR5_SAF_AXISFATAL0[3],axisfatal0[3] from CR5_SAF data errors and any parity errors on the AXI slave" "0,1" newline bitfld.long 0x0 6. "CR5_SAF_AXISFATAL0[2],axisfatal0[2] from CR5_SAF data errors and any parity errors on the AXI slave" "0,1" newline bitfld.long 0x0 5. "CR5_SAF_AXISFATAL0[1],axisfatal0[1] from CR5_SAF data errors and any parity errors on the AXI slave" "0,1" newline bitfld.long 0x0 4. "CR5_SAF_AXISFATAL0[0],axisfatal0[0] from CR5_SAF data errors and any parity errors on the AXI slave" "0,1" newline bitfld.long 0x0 3. "CR5_SAF_AXIMFATAL0[4],aximfatal0[4] from CR5_SAF data errors and any parity errors on the AXI master" "0,1" newline bitfld.long 0x0 2. "CR5_SAF_AXIMFATAL0[3],aximfatal0[3] from CR5_SAF data errors and any parity errors on the AXI master" "0,1" newline bitfld.long 0x0 1. "CR5_SAF_AXIMFATAL0[2],aximfatal0[2] from CR5_SAF data errors and any parity errors on the AXI master" "0,1" newline bitfld.long 0x0 0. "CR5_SAF_AXIMFATAL0[1],aximfatal0[1] from CR5_SAF data errors and any parity errors on the AXI master" "0,1" repeat.end repeat 4. (list 0x2F 0x39 0x43 0x4D )(list 0x0 0x80 0x100 0x180 ) rgroup.long ($2+0x31C)++0x3 line.long 0x0 "INT_ENABLE_$1,irq from REMAP_CR5_MP_AR Remap Address field check error" bitfld.long 0x0 31. "REMAP_CR5_MP_AR_IRQ,irq from REMAP_CR5_MP_AR Remap Address field check error" "0,1" newline bitfld.long 0x0 30. "REMAP_CR5_MP_AW_IRQ,irq from REMAP_CR5_MP_AW Remap Address field check error" "0,1" newline bitfld.long 0x0 29. "REMAP_CR5_SEC_AR_IRQ,irq from REMAP_CR5_SEC_AR Remap Address field check error" "0,1" newline bitfld.long 0x0 28. "REMAP_CR5_SEC_AW_IRQ,irq from REMAP_CR5_SEC_AW Remap Address field check error" "0,1" newline bitfld.long 0x0 27. "REMAP_CR5_SAF_AR_IRQ,irq from REMAP_CR5_SAF_AR Remap Address field check error" "0,1" newline bitfld.long 0x0 26. "REMAP_CR5_SAF_AW_IRQ,irq from REMAP_CR5_SAF_AW Remap Address field check error" "0,1" newline bitfld.long 0x0 25. "CR5_MP_DCCMOUT2[0],dccmout2[0] from CR5_MP LockStep compare fail" "0,1" newline bitfld.long 0x0 24. "CR5_MP_DCCMOUT[0],dccmout[0] from CR5_MP LockStep compare fail" "0,1" newline bitfld.long 0x0 23. "CR5_MP_PPXFATAL0[4],ppxfatal0[4] from CR5_MP data errors and any parity errors on the AXI Peripheral Port" "0,1" newline bitfld.long 0x0 22. "CR5_MP_PPXFATAL0[3],ppxfatal0[3] from CR5_MP data errors and any parity errors on the AXI Peripheral Port" "0,1" newline bitfld.long 0x0 21. "CR5_MP_PPXFATAL0[2],ppxfatal0[2] from CR5_MP data errors and any parity errors on the AXI Peripheral Port" "0,1" newline bitfld.long 0x0 20. "CR5_MP_PPXFATAL0[1],ppxfatal0[1] from CR5_MP data errors and any parity errors on the AXI Peripheral Port" "0,1" newline bitfld.long 0x0 19. "CR5_MP_PPXFATAL0[0],ppxfatal0[0] from CR5_MP data errors and any parity errors on the AXI Peripheral Port" "0,1" newline bitfld.long 0x0 18. "CR5_MP_AXISFATAL0[4],axisfatal0[4] from CR5_MP data errors and any parity errors on the AXI slave" "0,1" newline bitfld.long 0x0 17. "CR5_MP_AXISFATAL0[3],axisfatal0[3] from CR5_MP data errors and any parity errors on the AXI slave" "0,1" newline bitfld.long 0x0 16. "CR5_MP_AXISFATAL0[2],axisfatal0[2] from CR5_MP data errors and any parity errors on the AXI slave" "0,1" newline bitfld.long 0x0 15. "CR5_MP_AXISFATAL0[1],axisfatal0[1] from CR5_MP data errors and any parity errors on the AXI slave" "0,1" newline bitfld.long 0x0 14. "CR5_MP_AXISFATAL0[0],axisfatal0[0] from CR5_MP data errors and any parity errors on the AXI slave" "0,1" newline bitfld.long 0x0 13. "CR5_MP_AXIMFATAL0[4],aximfatal0[4] from CR5_MP data errors and any parity errors on the AXI master" "0,1" newline bitfld.long 0x0 12. "CR5_MP_AXIMFATAL0[3],aximfatal0[3] from CR5_MP data errors and any parity errors on the AXI master" "0,1" newline bitfld.long 0x0 11. "CR5_MP_AXIMFATAL0[2],aximfatal0[2] from CR5_MP data errors and any parity errors on the AXI master" "0,1" newline bitfld.long 0x0 10. "CR5_MP_AXIMFATAL0[1],aximfatal0[1] from CR5_MP data errors and any parity errors on the AXI master" "0,1" newline bitfld.long 0x0 9. "CR5_MP_AXIMFATAL0[0],aximfatal0[0] from CR5_MP data errors and any parity errors on the AXI master" "0,1" newline bitfld.long 0x0 8. "RC_RTC_RTC_32K_NG_INT,rtc_32k_ng_int from RC_RTC RC or XTAL 32K clock is lost" "0,1" newline bitfld.long 0x0 7. "CR5_MP_PPXCORR0,ppxcorr0 from CR5_MP data errors on reads by the AXI Peripheral Port" "0,1" newline bitfld.long 0x0 6. "CR5_MP_AXISCORR0,axiscorr0 from CR5_MP data errors on writes to the AXI Slave" "0,1" newline bitfld.long 0x0 5. "CR5_MP_AXIMCORR0,aximcorr0 from CR5_MP data errors on reads by the AXI Master" "0,1" newline bitfld.long 0x0 4. "CR5_SEC_DCCMOUT2[0],dccmout2[0] from CR5_SEC LockStep compare fail" "0,1" newline bitfld.long 0x0 3. "CR5_SEC_DCCMOUT[0],dccmout[0] from CR5_SEC LockStep compare fail" "0,1" newline bitfld.long 0x0 2. "CR5_SEC_PPXFATAL0[4],ppxfatal0[4] from CR5_SEC data errors and any parity errors on the AXI Peripheral Port" "0,1" newline bitfld.long 0x0 1. "CR5_SEC_PPXFATAL0[3],ppxfatal0[3] from CR5_SEC data errors and any parity errors on the AXI Peripheral Port" "0,1" newline bitfld.long 0x0 0. "CR5_SEC_PPXFATAL0[2],ppxfatal0[2] from CR5_SEC data errors and any parity errors on the AXI Peripheral Port" "0,1" repeat.end repeat 4. (list 0x30 0x3A 0x44 0x4E )(list 0x0 0x80 0x100 0x180 ) rgroup.long ($2+0x320)++0x3 line.long 0x0 "INT_ENABLE_$1,ap_power_lat from PWR_LAT_SAF AP domain power fail" bitfld.long 0x0 31. "PWR_LAT_SAF_AP_POWER_LAT,ap_power_lat from PWR_LAT_SAF AP domain power fail" "0,1" newline bitfld.long 0x0 30. "PWR_LAT_SAF_RTC_POWER_LAT,rtc_power_lat from PWR_LAT_SAF RTC domain power fail" "0,1" newline bitfld.long 0x0 29. "XTAL_AP_TO_LOST_INT,to_lost_int from XTAL_AP xtal_saf lost" "0,1" newline bitfld.long 0x0 28. "XTAL_AP_TO_UNST_INT,to_unst_int from XTAL_AP xtal_saf un-stable" "0,1" newline bitfld.long 0x0 27. "XTAL_AP_FR_UNST_INT,fr_unst_int from XTAL_AP xtal_ap un-stable" "0,1" newline bitfld.long 0x0 26. "XTAL_SAF_TO_LOST_INT,to_lost_int from XTAL_SAF xtal_ap lost" "0,1" newline bitfld.long 0x0 25. "XTAL_SAF_TO_UNST_INT,to_unst_int from XTAL_SAF xtal_ap un-stable" "0,1" newline bitfld.long 0x0 24. "XTAL_SAF_FR_UNST_INT,fr_unst_int from XTAL_SAF xtal_saf un-stable" "0,1" newline bitfld.long 0x0 23. "RC_24M_SOC_XTAL_LOST_INT,soc_xtal_lost_int from RC_24M soc xtal lost" "0,1" newline bitfld.long 0x0 22. "RC_24M_SOC_XTAL_UNST_INT,soc_xtal_unst_int from RC_24M soc xtal un-stable" "0,1" newline bitfld.long 0x0 21. "RC_24M_SOC_OSC_UNST_INT,soc_osc_unst_int from RC_24M osc un-stable according to soc xtal" "0,1" newline bitfld.long 0x0 20. "RC_24M_SAF_XTAL_LOST_INT,saf_xtal_lost_int from RC_24M safety xtal lost" "0,1" newline bitfld.long 0x0 19. "RC_24M_SAF_XTAL_UNST_INT,saf_xtal_unst_int from RC_24M safety xtal un-stable" "0,1" newline bitfld.long 0x0 18. "RC_24M_SAF_OSC_UNST_INT,saf_osc_unst_int from RC_24M osc un-stable according to saf xtal" "0,1" newline bitfld.long 0x0 17. "CPU2_~NERRIRQ[1],~nERRIRQ[1] from CPU2 Error indicator for an ECC error that causes potential data corruption or loss of coherency in the Core0 L1 or L2 RAMs" "0,1" newline bitfld.long 0x0 16. "CPU2_~NERRIRQ[0],~nERRIRQ[0] from CPU2 Error indicator for an ECC error that causes potential data corruption or loss of coherency in the L3 RAMs" "0,1" newline bitfld.long 0x0 15. "CPU2_~NFAULTIRQ[1],~nFAULTIRQ[1] from CPU2 Fault indicator for a detected 1-bit or 2-bit ECC or Parity error in the Core0 L1 or L2 RAMs" "?,bit or 2-bit ECC or Parity error in the Core0 L1.." newline bitfld.long 0x0 14. "CPU2_~NFAULTIRQ[0],~nFAULTIRQ[0] from CPU2 Fault indicator for a detected 1-bit or 2-bit ECC or Parity error in the L3 RAMs" "?,bit or 2-bit ECC or Parity error in the L3 RAMs" newline bitfld.long 0x0 13. "CPU1_~NERRIRQ[6],~nERRIRQ[6] from CPU1 Error indicator for an ECC error that causes potential data corruption or loss of coherency in the Core3 L1 or L2 RAMs" "0,1" newline bitfld.long 0x0 12. "CPU1_~NERRIRQ[5],~nERRIRQ[5] from CPU1 Error indicator for an ECC error that causes potential data corruption or loss of coherency in the Core2 L1 or L2 RAMs" "0,1" newline bitfld.long 0x0 11. "CPU1_~NERRIRQ[4],~nERRIRQ[4] from CPU1 Error indicator for an ECC error that causes potential data corruption or loss of coherency in the Core3 L1 or L2 RAMs" "0,1" newline bitfld.long 0x0 10. "CPU1_~NERRIRQ[3],~nERRIRQ[3] from CPU1 Error indicator for an ECC error that causes potential data corruption or loss of coherency in the Core2 L1 or L2 RAMs" "0,1" newline bitfld.long 0x0 9. "CPU1_~NERRIRQ[2],~nERRIRQ[2] from CPU1 Error indicator for an ECC error that causes potential data corruption or loss of coherency in the Core1 L1 or L2 RAMs" "0,1" newline bitfld.long 0x0 8. "CPU1_~NERRIRQ[1],~nERRIRQ[1] from CPU1 Error indicator for an ECC error that causes potential data corruption or loss of coherency in the Core0 L1 or L2 RAMs" "0,1" newline bitfld.long 0x0 7. "CPU1_~NERRIRQ[0],~nERRIRQ[0] from CPU1 Error indicator for an ECC error that causes potential data corruption or loss of coherency in the L3 RAMs" "0,1" newline bitfld.long 0x0 6. "CPU1_~NFAULTIRQ[6],~nFAULTIRQ[6] from CPU1 Fault indicator for a detected 1-bit or 2-bit ECC or Parity error in the Core3 L1 or L2 RAMs" "?,bit or 2-bit ECC or Parity error in the Core3 L1.." newline bitfld.long 0x0 5. "CPU1_~NFAULTIRQ[5],~nFAULTIRQ[5] from CPU1 Fault indicator for a detected 1-bit or 2-bit ECC or Parity error in the Core2 L1 or L2 RAMs" "?,bit or 2-bit ECC or Parity error in the Core2 L1.." newline bitfld.long 0x0 4. "CPU1_~NFAULTIRQ[4],~nFAULTIRQ[4] from CPU1 Fault indicator for a detected 1-bit or 2-bit ECC or Parity error in the Core3 L1 or L2 RAMs" "?,bit or 2-bit ECC or Parity error in the Core3 L1.." newline bitfld.long 0x0 3. "CPU1_~NFAULTIRQ[3],~nFAULTIRQ[3] from CPU1 Fault indicator for a detected 1-bit or 2-bit ECC or Parity error in the Core2 L1 or L2 RAMs" "?,bit or 2-bit ECC or Parity error in the Core2 L1.." newline bitfld.long 0x0 2. "CPU1_~NFAULTIRQ[2],~nFAULTIRQ[2] from CPU1 Fault indicator for a detected 1-bit or 2-bit ECC or Parity error in the Core1 L1 or L2 RAMs" "?,bit or 2-bit ECC or Parity error in the Core1 L1.." newline bitfld.long 0x0 1. "CPU1_~NFAULTIRQ[1],~nFAULTIRQ[1] from CPU1 Fault indicator for a detected 1-bit or 2-bit ECC or Parity error in the Core0 L1 or L2 RAMs" "?,bit or 2-bit ECC or Parity error in the Core0 L1.." newline bitfld.long 0x0 0. "CPU1_~NFAULTIRQ[0],~nFAULTIRQ[0] from CPU1 Fault indicator for a detected 1-bit or 2-bit ECC or Parity error in the L3 RAMs" "?,bit or 2-bit ECC or Parity error in the L3 RAMs" repeat.end repeat 4. (list 0x31 0x3B 0x45 0x4F )(list 0x0 0x80 0x100 0x180 ) rgroup.long ($2+0x324)++0x3 line.long 0x0 "INT_ENABLE_$1,pvt_int_1 from PVT_SNS_SAF None" bitfld.long 0x0 30. "PVT_SNS_SAF_PVT_INT_1,pvt_int_1 from PVT_SNS_SAF None" "0,1" newline bitfld.long 0x0 29. "PVT_SNS_SAF_PVT_INT_0,pvt_int_0 from PVT_SNS_SAF None" "0,1" newline bitfld.long 0x0 28. "PVT_SNS_SEC_PVT_INT_1,pvt_int_1 from PVT_SNS_SEC None" "0,1" newline bitfld.long 0x0 27. "PVT_SNS_SEC_PVT_INT_0,pvt_int_0 from PVT_SNS_SEC None" "0,1" newline bitfld.long 0x0 26. "WDT8_ILL_SEQ_REFR_INT,ill_seq_refr_int from WDT8 None" "0,1" newline bitfld.long 0x0 25. "WDT8_ILL_WIN_REFR_INT,ill_win_refr_int from WDT8 None" "0,1" newline bitfld.long 0x0 24. "WDT8_OVFLOW_INT,ovflow_int from WDT8 None" "0,1" newline bitfld.long 0x0 23. "WDT7_ILL_SEQ_REFR_INT,ill_seq_refr_int from WDT7 None" "0,1" newline bitfld.long 0x0 22. "WDT7_ILL_WIN_REFR_INT,ill_win_refr_int from WDT7 None" "0,1" newline bitfld.long 0x0 21. "WDT7_OVFLOW_INT,ovflow_int from WDT7 None" "0,1" newline bitfld.long 0x0 20. "WDT6_ILL_SEQ_REFR_INT,ill_seq_refr_int from WDT6 None" "0,1" newline bitfld.long 0x0 19. "WDT6_ILL_WIN_REFR_INT,ill_win_refr_int from WDT6 None" "0,1" newline bitfld.long 0x0 18. "WDT6_OVFLOW_INT,ovflow_int from WDT6 None" "0,1" newline bitfld.long 0x0 17. "WDT5_ILL_SEQ_REFR_INT,ill_seq_refr_int from WDT5 None" "0,1" newline bitfld.long 0x0 16. "WDT5_ILL_WIN_REFR_INT,ill_win_refr_int from WDT5 None" "0,1" newline bitfld.long 0x0 15. "WDT5_OVFLOW_INT,ovflow_int from WDT5 None" "0,1" newline bitfld.long 0x0 14. "WDT4_ILL_SEQ_REFR_INT,ill_seq_refr_int from WDT4 None" "0,1" newline bitfld.long 0x0 13. "WDT4_ILL_WIN_REFR_INT,ill_win_refr_int from WDT4 None" "0,1" newline bitfld.long 0x0 12. "WDT4_OVFLOW_INT,ovflow_int from WDT4 None" "0,1" newline bitfld.long 0x0 11. "WDT3_ILL_SEQ_REFR_INT,ill_seq_refr_int from WDT3 None" "0,1" newline bitfld.long 0x0 10. "WDT3_ILL_WIN_REFR_INT,ill_win_refr_int from WDT3 None" "0,1" newline bitfld.long 0x0 9. "WDT3_OVFLOW_INT,ovflow_int from WDT3 None" "0,1" newline bitfld.long 0x0 8. "WDT2_ILL_SEQ_REFR_INT,ill_seq_refr_int from WDT2 None" "0,1" newline bitfld.long 0x0 7. "WDT2_ILL_WIN_REFR_INT,ill_win_refr_int from WDT2 None" "0,1" newline bitfld.long 0x0 6. "WDT2_OVFLOW_INT,ovflow_int from WDT2 None" "0,1" newline bitfld.long 0x0 5. "WDT1_ILL_SEQ_REFR_INT,ill_seq_refr_int from WDT1 None" "0,1" newline bitfld.long 0x0 4. "WDT1_ILL_WIN_REFR_INT,ill_win_refr_int from WDT1 None" "0,1" newline bitfld.long 0x0 3. "WDT1_OVFLOW_INT,ovflow_int from WDT1 None" "0,1" newline bitfld.long 0x0 2. "PWR_LAT_RTC_AP_POWER_LAT,ap_power_lat from PWR_LAT_RTC AP domain power fail" "0,1" newline bitfld.long 0x0 1. "PWR_LAT_RTC_SAF_POWER_LAT,saf_power_lat from PWR_LAT_RTC SAF domain power fail" "0,1" newline bitfld.long 0x0 0. "PWR_LAT_SAF_SAF_POWER_LAT,saf_power_lat from PWR_LAT_SAF SAF power fail" "0,1" repeat.end repeat 6. (list 0x0 0x1 0x2 0x3 0x4 0x5 )(list 0x0 0x4 0x8 0xC 0x10 0x14 ) group.long ($2+0x500)++0x3 line.long 0x0 "TGT_VALUE$1,target value" hexmask.long 0x0 0.--31. 1. "TGT_VALUE0,monitor target value" repeat.end repeat 6. (list 0x0 0x1 0x2 0x3 0x4 0x5 )(list 0x0 0x4 0x8 0xC 0x10 0x14 ) group.long ($2+0x580)++0x3 line.long 0x0 "SIG_MON_ENABLE$1,signal monitor enable" hexmask.long 0x0 0.--31. 1. "SIG_MON_ENABLE0,monitor enable" repeat.end tree.end tree "AB1 (Address Block of sem)" group.long 0x0++0xB line.long 0x0 "SEM_COMMON_SET,SEM common settings" hexmask.long.byte 0x0 24.--31. 1. "CMP_ENABLE,compare output enable bits for int0-7" bitfld.long 0x0 23. "SIG_MON_GLB_EN,signal monitor global enable" "0,1" bitfld.long 0x0 17. "EI_GLOBAL_EN_LOCK,Error Injection Global Enable Lock bit" "0,1" newline bitfld.long 0x0 16. "EI_GLOBAL_EN,Error Injection Global Enable" "0,1" hexmask.long.byte 0x0 12.--15. 1. "ERROR_DIV,error divider ratio for waveform A" bitfld.long 0x0 11. "ERROR_WAVE_SEL,waveform A/B selection for normal/recoverable error" "0,1" newline bitfld.long 0x0 10. "FATAL_HIGH_LOW,fatal error High or Low selection" "0,1" bitfld.long 0x0 8.--9. "SEM_INT_DC4_SEL,SEM_INT DC4 selection" "0,1,2,3" bitfld.long 0x0 6.--7. "SEM_INT_DC3_SEL,SEM_INT DC3 selection" "0,1,2,3" newline bitfld.long 0x0 4.--5. "SEM_INT_DC2_SEL,SEM_INT DC2 selection" "0,1,2,3" bitfld.long 0x0 2.--3. "SEM_INT_DC1_SEL,SEM_INT DC1 selection" "0,1,2,3" bitfld.long 0x0 0.--1. "SEM_INT_DC0_SEL,SEM_INT DC0 selection" "0,1,2,3" line.long 0x4 "INT_TRIG,int0-7 trigger" hexmask.long.byte 0x4 0.--7. 1. "INT_TRIG,int0-int7 trigger" line.long 0x8 "INT_ENABLE_OVRD,int0-7 enable override" hexmask.long.byte 0x8 8.--15. 1. "INT_ENABLE_OVRD_VAL,int0-7 enable override value" hexmask.long.byte 0x8 0.--7. 1. "INT_ENABLE_OVRD_EN,int0-7 enable override enable" repeat 9. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 )(list 0x0 0x4 0x8 0xC 0x10 0x14 0x18 0x1C 0x20 ) rgroup.long ($2+0x80)++0x3 line.long 0x0 "INT_STATUS$1,Interrupt Status" bitfld.long 0x0 31. "CANFD6_IPI_INT_CE,ipi_int_ce from CANFD6 Correctable error interrupt" "0,1" bitfld.long 0x0 30. "CANFD5_IPI_INT_NCEFA,ipi_int_ncefa from CANFD5 Non correctable error int internal" "0,1" bitfld.long 0x0 29. "CANFD5_IPI_INT_NCEHA,ipi_int_nceha from CANFD5 Non correctable error int host" "0,1" newline bitfld.long 0x0 28. "CANFD5_IPI_INT_CE,ipi_int_ce from CANFD5 Correctable error interrupt" "0,1" bitfld.long 0x0 27. "CANFD4_IPI_INT_NCEFA,ipi_int_ncefa from CANFD4 Non correctable error int internal" "0,1" bitfld.long 0x0 26. "CANFD4_IPI_INT_NCEHA,ipi_int_nceha from CANFD4 Non correctable error int host" "0,1" newline bitfld.long 0x0 25. "CANFD4_IPI_INT_CE,ipi_int_ce from CANFD4 Correctable error interrupt" "0,1" bitfld.long 0x0 24. "CANFD3_IPI_INT_NCEFA,ipi_int_ncefa from CANFD3 Non correctable error int internal" "0,1" bitfld.long 0x0 23. "CANFD3_IPI_INT_NCEHA,ipi_int_nceha from CANFD3 Non correctable error int host" "0,1" newline bitfld.long 0x0 22. "CANFD3_IPI_INT_CE,ipi_int_ce from CANFD3 Correctable error interrupt" "0,1" bitfld.long 0x0 21. "CANFD2_IPI_INT_NCEFA,ipi_int_ncefa from CANFD2 Non correctable error int internal" "0,1" bitfld.long 0x0 20. "CANFD2_IPI_INT_NCEHA,ipi_int_nceha from CANFD2 Non correctable error int host" "0,1" newline bitfld.long 0x0 19. "CANFD2_IPI_INT_CE,ipi_int_ce from CANFD2 Correctable error interrupt" "0,1" bitfld.long 0x0 18. "CANFD1_IPI_INT_NCEFA,ipi_int_ncefa from CANFD1 Non correctable error int internal" "0,1" bitfld.long 0x0 17. "CANFD1_IPI_INT_NCEHA,ipi_int_nceha from CANFD1 Non correctable error int host" "0,1" newline bitfld.long 0x0 16. "CANFD1_IPI_INT_CE,ipi_int_ce from CANFD1 Correctable error interrupt" "0,1" bitfld.long 0x0 15. "ENET2_SBD_SFTY_UE_INTR_O,sbd_sfty_ue_intr_o from ENET2" "0,1" bitfld.long 0x0 14. "ENET2_SBD_SFTY_CE_INTR_O,sbd_sfty_ce_intr_o from ENET2" "0,1" newline bitfld.long 0x0 13. "ENET1_SBD_SFTY_UE_INTR_O,sbd_sfty_ue_intr_o from ENET1" "0,1" bitfld.long 0x0 12. "ENET1_SBD_SFTY_CE_INTR_O,sbd_sfty_ce_intr_o from ENET1" "0,1" bitfld.long 0x0 11. "ROMC2_MUL_ERR_INT,mul_err_int from ROMC2" "0,1" newline bitfld.long 0x0 10. "ROMC2_SIG_ERR_INT,sig_err_int from ROMC2" "0,1" bitfld.long 0x0 9. "ROMC1_MUL_ERR_INT,mul_err_int from ROMC1" "0,1" bitfld.long 0x0 8. "ROMC1_SIG_ERR_INT,sig_err_int from ROMC1" "0,1" newline bitfld.long 0x0 7. "IRAM4_MUL_ERR_INT,mul_err_int from IRAM4" "0,1" bitfld.long 0x0 6. "IRAM4_SIG_ERR_INT,sig_err_int from IRAM4" "0,1" bitfld.long 0x0 5. "IRAM3_MUL_ERR_INT,mul_err_int from IRAM3" "0,1" newline bitfld.long 0x0 4. "IRAM3_SIG_ERR_INT,sig_err_int from IRAM3" "0,1" bitfld.long 0x0 3. "IRAM2_MUL_ERR_INT,mul_err_int from IRAM2" "0,1" bitfld.long 0x0 2. "IRAM2_SIG_ERR_INT,sig_err_int from IRAM2" "0,1" newline bitfld.long 0x0 1. "IRAM1_MUL_ERR_INT,mul_err_int from IRAM1" "0,1" bitfld.long 0x0 0. "IRAM1_SIG_ERR_INT,sig_err_int from IRAM1" "0,1" repeat.end rgroup.long 0xA4++0x3 line.long 0x0 "INT_STATUS9,Interrupt Status" bitfld.long 0x0 30. "PVT_SNS_SAF_PVT_INT_1,pvt_int_1 from PVT_SNS_SAF" "0,1" bitfld.long 0x0 29. "PVT_SNS_SAF_PVT_INT_0,pvt_int_0 from PVT_SNS_SAF" "0,1" bitfld.long 0x0 28. "PVT_SNS_SEC_PVT_INT_1,pvt_int_1 from PVT_SNS_SEC" "0,1" newline bitfld.long 0x0 27. "PVT_SNS_SEC_PVT_INT_0,pvt_int_0 from PVT_SNS_SEC" "0,1" bitfld.long 0x0 26. "WDT8_ILL_SEQ_REFR_INT,ill_seq_refr_int from WDT8" "0,1" bitfld.long 0x0 25. "WDT8_ILL_WIN_REFR_INT,ill_win_refr_int from WDT8" "0,1" newline bitfld.long 0x0 24. "WDT8_OVFLOW_INT,ovflow_int from WDT8" "0,1" bitfld.long 0x0 23. "WDT7_ILL_SEQ_REFR_INT,ill_seq_refr_int from WDT7" "0,1" bitfld.long 0x0 22. "WDT7_ILL_WIN_REFR_INT,ill_win_refr_int from WDT7" "0,1" newline bitfld.long 0x0 21. "WDT7_OVFLOW_INT,ovflow_int from WDT7" "0,1" bitfld.long 0x0 20. "WDT6_ILL_SEQ_REFR_INT,ill_seq_refr_int from WDT6" "0,1" bitfld.long 0x0 19. "WDT6_ILL_WIN_REFR_INT,ill_win_refr_int from WDT6" "0,1" newline bitfld.long 0x0 18. "WDT6_OVFLOW_INT,ovflow_int from WDT6" "0,1" bitfld.long 0x0 17. "WDT5_ILL_SEQ_REFR_INT,ill_seq_refr_int from WDT5" "0,1" bitfld.long 0x0 16. "WDT5_ILL_WIN_REFR_INT,ill_win_refr_int from WDT5" "0,1" newline bitfld.long 0x0 15. "WDT5_OVFLOW_INT,ovflow_int from WDT5" "0,1" bitfld.long 0x0 14. "WDT4_ILL_SEQ_REFR_INT,ill_seq_refr_int from WDT4" "0,1" bitfld.long 0x0 13. "WDT4_ILL_WIN_REFR_INT,ill_win_refr_int from WDT4" "0,1" newline bitfld.long 0x0 12. "WDT4_OVFLOW_INT,ovflow_int from WDT4" "0,1" bitfld.long 0x0 11. "WDT3_ILL_SEQ_REFR_INT,ill_seq_refr_int from WDT3" "0,1" bitfld.long 0x0 10. "WDT3_ILL_WIN_REFR_INT,ill_win_refr_int from WDT3" "0,1" newline bitfld.long 0x0 9. "WDT3_OVFLOW_INT,ovflow_int from WDT3" "0,1" bitfld.long 0x0 8. "WDT2_ILL_SEQ_REFR_INT,ill_seq_refr_int from WDT2" "0,1" bitfld.long 0x0 7. "WDT2_ILL_WIN_REFR_INT,ill_win_refr_int from WDT2" "0,1" newline bitfld.long 0x0 6. "WDT2_OVFLOW_INT,ovflow_int from WDT2" "0,1" bitfld.long 0x0 5. "WDT1_ILL_SEQ_REFR_INT,ill_seq_refr_int from WDT1" "0,1" bitfld.long 0x0 4. "WDT1_ILL_WIN_REFR_INT,ill_win_refr_int from WDT1" "0,1" newline bitfld.long 0x0 3. "WDT1_OVFLOW_INT,ovflow_int from WDT1" "0,1" bitfld.long 0x0 2. "PWR_LAT_RTC_AP_POWER_LAT,ap_power_lat from PWR_LAT_RTC AP domain power fail" "0,1" bitfld.long 0x0 1. "PWR_LAT_RTC_SAF_POWER_LAT,saf_power_lat from PWR_LAT_RTC SAF domain power fail" "0,1" newline bitfld.long 0x0 0. "PWR_LAT_SAF_SAF_POWER_LAT,saf_power_lat from PWR_LAT_SAF SAF power fail" "0,1" repeat 9. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 )(list 0x0 0x4 0x8 0xC 0x10 0x14 0x18 0x1C 0x20 ) group.long ($2+0x100)++0x3 line.long 0x0 "INT_ENABLE_$1,Interrupt Enable 0 for correctable error output to PIN" bitfld.long 0x0 31. "CANFD6_IPI_INT_CE,ipi_int_ce from CANFD6 Correctable error interrupt" "0,1" bitfld.long 0x0 30. "CANFD5_IPI_INT_NCEFA,ipi_int_ncefa from CANFD5 Non correctable error int internal" "0,1" bitfld.long 0x0 29. "CANFD5_IPI_INT_NCEHA,ipi_int_nceha from CANFD5 Non correctable error int host" "0,1" newline bitfld.long 0x0 28. "CANFD5_IPI_INT_CE,ipi_int_ce from CANFD5 Correctable error interrupt" "0,1" bitfld.long 0x0 27. "CANFD4_IPI_INT_NCEFA,ipi_int_ncefa from CANFD4 Non correctable error int internal" "0,1" bitfld.long 0x0 26. "CANFD4_IPI_INT_NCEHA,ipi_int_nceha from CANFD4 Non correctable error int host" "0,1" newline bitfld.long 0x0 25. "CANFD4_IPI_INT_CE,ipi_int_ce from CANFD4 Correctable error interrupt" "0,1" bitfld.long 0x0 24. "CANFD3_IPI_INT_NCEFA,ipi_int_ncefa from CANFD3 Non correctable error int internal" "0,1" bitfld.long 0x0 23. "CANFD3_IPI_INT_NCEHA,ipi_int_nceha from CANFD3 Non correctable error int host" "0,1" newline bitfld.long 0x0 22. "CANFD3_IPI_INT_CE,ipi_int_ce from CANFD3 Correctable error interrupt" "0,1" bitfld.long 0x0 21. "CANFD2_IPI_INT_NCEFA,ipi_int_ncefa from CANFD2 Non correctable error int internal" "0,1" bitfld.long 0x0 20. "CANFD2_IPI_INT_NCEHA,ipi_int_nceha from CANFD2 Non correctable error int host" "0,1" newline bitfld.long 0x0 19. "CANFD2_IPI_INT_CE,ipi_int_ce from CANFD2 Correctable error interrupt" "0,1" bitfld.long 0x0 18. "CANFD1_IPI_INT_NCEFA,ipi_int_ncefa from CANFD1 Non correctable error int internal" "0,1" bitfld.long 0x0 17. "CANFD1_IPI_INT_NCEHA,ipi_int_nceha from CANFD1 Non correctable error int host" "0,1" newline bitfld.long 0x0 16. "CANFD1_IPI_INT_CE,ipi_int_ce from CANFD1 Correctable error interrupt" "0,1" bitfld.long 0x0 15. "ENET2_SBD_SFTY_UE_INTR_O,sbd_sfty_ue_intr_o from ENET2" "0,1" bitfld.long 0x0 14. "ENET2_SBD_SFTY_CE_INTR_O,sbd_sfty_ce_intr_o from ENET2" "0,1" newline bitfld.long 0x0 13. "ENET1_SBD_SFTY_UE_INTR_O,sbd_sfty_ue_intr_o from ENET1" "0,1" bitfld.long 0x0 12. "ENET1_SBD_SFTY_CE_INTR_O,sbd_sfty_ce_intr_o from ENET1" "0,1" bitfld.long 0x0 11. "RWMC2_MUL_ERR_INT,mul_err_int from RWMC2" "0,1" newline bitfld.long 0x0 10. "RWMC2_SIG_ERR_INT,sig_err_int from RWMC2" "0,1" bitfld.long 0x0 9. "RWMC1_MUL_ERR_INT,mul_err_int from RWMC1" "0,1" bitfld.long 0x0 8. "RWMC1_SIG_ERR_INT,sig_err_int from RWMC1" "0,1" newline bitfld.long 0x0 7. "IRAM4_MUL_ERR_INT,mul_err_int from IRAM4" "0,1" bitfld.long 0x0 6. "IRAM4_SIG_ERR_INT,sig_err_int from IRAM4" "0,1" bitfld.long 0x0 5. "IRAM3_MUL_ERR_INT,mul_err_int from IRAM3" "0,1" newline bitfld.long 0x0 4. "IRAM3_SIG_ERR_INT,sig_err_int from IRAM3" "0,1" bitfld.long 0x0 3. "IRAM2_MUL_ERR_INT,mul_err_int from IRAM2" "0,1" bitfld.long 0x0 2. "IRAM2_SIG_ERR_INT,sig_err_int from IRAM2" "0,1" newline bitfld.long 0x0 1. "IRAM1_MUL_ERR_INT,mul_err_int from IRAM1" "0,1" bitfld.long 0x0 0. "IRAM1_SIG_ERR_INT,sig_err_int from IRAM1" "0,1" repeat.end group.long 0x124++0x3 line.long 0x0 "INT_ENABLE_09,Interrupt Enable 0 for correctable error output to PIN" bitfld.long 0x0 30. "PVT_SNS_SAF_PVT_INT_1,pvt_int_1 from PVT_SNS_SAF" "0,1" bitfld.long 0x0 29. "PVT_SNS_SAF_PVT_INT_0,pvt_int_0 from PVT_SNS_SAF" "0,1" bitfld.long 0x0 28. "PVT_SNS_SEC_PVT_INT_1,pvt_int_1 from PVT_SNS_SEC" "0,1" newline bitfld.long 0x0 27. "PVT_SNS_SEC_PVT_INT_0,pvt_int_0 from PVT_SNS_SEC" "0,1" bitfld.long 0x0 26. "WDT8_ILL_SEQ_REFR_INT,ill_seq_refr_int from WDT8" "0,1" bitfld.long 0x0 25. "WDT8_ILL_WIN_REFR_INT,ill_win_refr_int from WDT8" "0,1" newline bitfld.long 0x0 24. "WDT8_OVFLOW_INT,ovflow_int from WDT8" "0,1" bitfld.long 0x0 23. "WDT7_ILL_SEQ_REFR_INT,ill_seq_refr_int from WDT7" "0,1" bitfld.long 0x0 22. "WDT7_ILL_WIN_REFR_INT,ill_win_refr_int from WDT7" "0,1" newline bitfld.long 0x0 21. "WDT7_OVFLOW_INT,ovflow_int from WDT7" "0,1" bitfld.long 0x0 20. "WDT6_ILL_SEQ_REFR_INT,ill_seq_refr_int from WDT6" "0,1" bitfld.long 0x0 19. "WDT6_ILL_WIN_REFR_INT,ill_win_refr_int from WDT6" "0,1" newline bitfld.long 0x0 18. "WDT6_OVFLOW_INT,ovflow_int from WDT6" "0,1" bitfld.long 0x0 17. "WDT5_ILL_SEQ_REFR_INT,ill_seq_refr_int from WDT5" "0,1" bitfld.long 0x0 16. "WDT5_ILL_WIN_REFR_INT,ill_win_refr_int from WDT5" "0,1" newline bitfld.long 0x0 15. "WDT5_OVFLOW_INT,ovflow_int from WDT5" "0,1" bitfld.long 0x0 14. "WDT4_ILL_SEQ_REFR_INT,ill_seq_refr_int from WDT4" "0,1" bitfld.long 0x0 13. "WDT4_ILL_WIN_REFR_INT,ill_win_refr_int from WDT4" "0,1" newline bitfld.long 0x0 12. "WDT4_OVFLOW_INT,ovflow_int from WDT4" "0,1" bitfld.long 0x0 11. "WDT3_ILL_SEQ_REFR_INT,ill_seq_refr_int from WDT3" "0,1" bitfld.long 0x0 10. "WDT3_ILL_WIN_REFR_INT,ill_win_refr_int from WDT3" "0,1" newline bitfld.long 0x0 9. "WDT3_OVFLOW_INT,ovflow_int from WDT3" "0,1" bitfld.long 0x0 8. "WDT2_ILL_SEQ_REFR_INT,ill_seq_refr_int from WDT2" "0,1" bitfld.long 0x0 7. "WDT2_ILL_WIN_REFR_INT,ill_win_refr_int from WDT2" "0,1" newline bitfld.long 0x0 6. "WDT2_OVFLOW_INT,ovflow_int from WDT2" "0,1" bitfld.long 0x0 5. "WDT1_ILL_SEQ_REFR_INT,ill_seq_refr_int from WDT1" "0,1" bitfld.long 0x0 4. "WDT1_ILL_WIN_REFR_INT,ill_win_refr_int from WDT1" "0,1" newline bitfld.long 0x0 3. "WDT1_OVFLOW_INT,ovflow_int from WDT1" "0,1" bitfld.long 0x0 2. "PWR_LAT_RTC_AP_POWER_LAT,ap_power_lat from PWR_LAT_RTC AP domain power fail" "0,1" bitfld.long 0x0 1. "PWR_LAT_RTC_SAF_POWER_LAT,saf_power_lat from PWR_LAT_RTC SAF domain power fail" "0,1" newline bitfld.long 0x0 0. "PWR_LAT_SAF_SAF_POWER_LAT,saf_power_lat from PWR_LAT_SAF SAF power fail" "0,1" repeat 9. (list 0xA 0xB 0xC 0xD 0xE 0xF 0x10 0x11 0x12 )(list 0x0 0x4 0x8 0xC 0x10 0x14 0x18 0x1C 0x20 ) group.long ($2+0x180)++0x3 line.long 0x0 "INT_ENABLE_$1,Interrupt Enable 1 for fatal error output to PIN" bitfld.long 0x0 31. "CANFD6_IPI_INT_CE,ipi_int_ce from CANFD6 Correctable error interrupt" "0,1" bitfld.long 0x0 30. "CANFD5_IPI_INT_NCEFA,ipi_int_ncefa from CANFD5 Non correctable error int internal" "0,1" bitfld.long 0x0 29. "CANFD5_IPI_INT_NCEHA,ipi_int_nceha from CANFD5 Non correctable error int host" "0,1" newline bitfld.long 0x0 28. "CANFD5_IPI_INT_CE,ipi_int_ce from CANFD5 Correctable error interrupt" "0,1" bitfld.long 0x0 27. "CANFD4_IPI_INT_NCEFA,ipi_int_ncefa from CANFD4 Non correctable error int internal" "0,1" bitfld.long 0x0 26. "CANFD4_IPI_INT_NCEHA,ipi_int_nceha from CANFD4 Non correctable error int host" "0,1" newline bitfld.long 0x0 25. "CANFD4_IPI_INT_CE,ipi_int_ce from CANFD4 Correctable error interrupt" "0,1" bitfld.long 0x0 24. "CANFD3_IPI_INT_NCEFA,ipi_int_ncefa from CANFD3 Non correctable error int internal" "0,1" bitfld.long 0x0 23. "CANFD3_IPI_INT_NCEHA,ipi_int_nceha from CANFD3 Non correctable error int host" "0,1" newline bitfld.long 0x0 22. "CANFD3_IPI_INT_CE,ipi_int_ce from CANFD3 Correctable error interrupt" "0,1" bitfld.long 0x0 21. "CANFD2_IPI_INT_NCEFA,ipi_int_ncefa from CANFD2 Non correctable error int internal" "0,1" bitfld.long 0x0 20. "CANFD2_IPI_INT_NCEHA,ipi_int_nceha from CANFD2 Non correctable error int host" "0,1" newline bitfld.long 0x0 19. "CANFD2_IPI_INT_CE,ipi_int_ce from CANFD2 Correctable error interrupt" "0,1" bitfld.long 0x0 18. "CANFD1_IPI_INT_NCEFA,ipi_int_ncefa from CANFD1 Non correctable error int internal" "0,1" bitfld.long 0x0 17. "CANFD1_IPI_INT_NCEHA,ipi_int_nceha from CANFD1 Non correctable error int host" "0,1" newline bitfld.long 0x0 16. "CANFD1_IPI_INT_CE,ipi_int_ce from CANFD1 Correctable error interrupt" "0,1" bitfld.long 0x0 15. "ENET2_SBD_SFTY_UE_INTR_O,sbd_sfty_ue_intr_o from ENET2" "0,1" bitfld.long 0x0 14. "ENET2_SBD_SFTY_CE_INTR_O,sbd_sfty_ce_intr_o from ENET2" "0,1" newline bitfld.long 0x0 13. "ENET1_SBD_SFTY_UE_INTR_O,sbd_sfty_ue_intr_o from ENET1" "0,1" bitfld.long 0x0 12. "ENET1_SBD_SFTY_CE_INTR_O,sbd_sfty_ce_intr_o from ENET1" "0,1" bitfld.long 0x0 11. "RWMC2_MUL_ERR_INT,mul_err_int from RWMC2" "0,1" newline bitfld.long 0x0 10. "RWMC2_SIG_ERR_INT,sig_err_int from RWMC2" "0,1" bitfld.long 0x0 9. "RWMC1_MUL_ERR_INT,mul_err_int from RWMC1" "0,1" bitfld.long 0x0 8. "RWMC1_SIG_ERR_INT,sig_err_int from RWMC1" "0,1" newline bitfld.long 0x0 7. "IRAM4_MUL_ERR_INT,mul_err_int from IRAM4" "0,1" bitfld.long 0x0 6. "IRAM4_SIG_ERR_INT,sig_err_int from IRAM4" "0,1" bitfld.long 0x0 5. "IRAM3_MUL_ERR_INT,mul_err_int from IRAM3" "0,1" newline bitfld.long 0x0 4. "IRAM3_SIG_ERR_INT,sig_err_int from IRAM3" "0,1" bitfld.long 0x0 3. "IRAM2_MUL_ERR_INT,mul_err_int from IRAM2" "0,1" bitfld.long 0x0 2. "IRAM2_SIG_ERR_INT,sig_err_int from IRAM2" "0,1" newline bitfld.long 0x0 1. "IRAM1_MUL_ERR_INT,mul_err_int from IRAM1" "0,1" bitfld.long 0x0 0. "IRAM1_SIG_ERR_INT,sig_err_int from IRAM1" "0,1" repeat.end group.long 0x1A4++0x3 line.long 0x0 "INT_ENABLE_19,Interrupt Enable 1 for fatal error output to PIN" bitfld.long 0x0 30. "PVT_SNS_SAF_PVT_INT_1,pvt_int_1 from PVT_SNS_SAF" "0,1" bitfld.long 0x0 29. "PVT_SNS_SAF_PVT_INT_0,pvt_int_0 from PVT_SNS_SAF" "0,1" bitfld.long 0x0 28. "PVT_SNS_SEC_PVT_INT_1,pvt_int_1 from PVT_SNS_SEC" "0,1" newline bitfld.long 0x0 27. "PVT_SNS_SEC_PVT_INT_0,pvt_int_0 from PVT_SNS_SEC" "0,1" bitfld.long 0x0 26. "WDT8_ILL_SEQ_REFR_INT,ill_seq_refr_int from WDT8" "0,1" bitfld.long 0x0 25. "WDT8_ILL_WIN_REFR_INT,ill_win_refr_int from WDT8" "0,1" newline bitfld.long 0x0 24. "WDT8_OVFLOW_INT,ovflow_int from WDT8" "0,1" bitfld.long 0x0 23. "WDT7_ILL_SEQ_REFR_INT,ill_seq_refr_int from WDT7" "0,1" bitfld.long 0x0 22. "WDT7_ILL_WIN_REFR_INT,ill_win_refr_int from WDT7" "0,1" newline bitfld.long 0x0 21. "WDT7_OVFLOW_INT,ovflow_int from WDT7" "0,1" bitfld.long 0x0 20. "WDT6_ILL_SEQ_REFR_INT,ill_seq_refr_int from WDT6" "0,1" bitfld.long 0x0 19. "WDT6_ILL_WIN_REFR_INT,ill_win_refr_int from WDT6" "0,1" newline bitfld.long 0x0 18. "WDT6_OVFLOW_INT,ovflow_int from WDT6" "0,1" bitfld.long 0x0 17. "WDT5_ILL_SEQ_REFR_INT,ill_seq_refr_int from WDT5" "0,1" bitfld.long 0x0 16. "WDT5_ILL_WIN_REFR_INT,ill_win_refr_int from WDT5" "0,1" newline bitfld.long 0x0 15. "WDT5_OVFLOW_INT,ovflow_int from WDT5" "0,1" bitfld.long 0x0 14. "WDT4_ILL_SEQ_REFR_INT,ill_seq_refr_int from WDT4" "0,1" bitfld.long 0x0 13. "WDT4_ILL_WIN_REFR_INT,ill_win_refr_int from WDT4" "0,1" newline bitfld.long 0x0 12. "WDT4_OVFLOW_INT,ovflow_int from WDT4" "0,1" bitfld.long 0x0 11. "WDT3_ILL_SEQ_REFR_INT,ill_seq_refr_int from WDT3" "0,1" bitfld.long 0x0 10. "WDT3_ILL_WIN_REFR_INT,ill_win_refr_int from WDT3" "0,1" newline bitfld.long 0x0 9. "WDT3_OVFLOW_INT,ovflow_int from WDT3" "0,1" bitfld.long 0x0 8. "WDT2_ILL_SEQ_REFR_INT,ill_seq_refr_int from WDT2" "0,1" bitfld.long 0x0 7. "WDT2_ILL_WIN_REFR_INT,ill_win_refr_int from WDT2" "0,1" newline bitfld.long 0x0 6. "WDT2_OVFLOW_INT,ovflow_int from WDT2" "0,1" bitfld.long 0x0 5. "WDT1_ILL_SEQ_REFR_INT,ill_seq_refr_int from WDT1" "0,1" bitfld.long 0x0 4. "WDT1_ILL_WIN_REFR_INT,ill_win_refr_int from WDT1" "0,1" newline bitfld.long 0x0 3. "WDT1_OVFLOW_INT,ovflow_int from WDT1" "0,1" bitfld.long 0x0 2. "PWR_LAT_RTC_AP_POWER_LAT,ap_power_lat from PWR_LAT_RTC AP domain power fail" "0,1" bitfld.long 0x0 1. "PWR_LAT_RTC_SAF_POWER_LAT,saf_power_lat from PWR_LAT_RTC SAF domain power fail" "0,1" newline bitfld.long 0x0 0. "PWR_LAT_SAF_SAF_POWER_LAT,saf_power_lat from PWR_LAT_SAF SAF power fail" "0,1" repeat 9. (list 0x14 0x15 0x16 0x17 0x18 0x19 0x1A 0x1B 0x1C )(list 0x0 0x4 0x8 0xC 0x10 0x14 0x18 0x1C 0x20 ) group.long ($2+0x200)++0x3 line.long 0x0 "INT_ENABLE_$1,Interrupt Enable 2 for error output to CPU" bitfld.long 0x0 31. "CANFD6_IPI_INT_CE,ipi_int_ce from CANFD6 Correctable error interrupt" "0,1" bitfld.long 0x0 30. "CANFD5_IPI_INT_NCEFA,ipi_int_ncefa from CANFD5 Non correctable error int internal" "0,1" bitfld.long 0x0 29. "CANFD5_IPI_INT_NCEHA,ipi_int_nceha from CANFD5 Non correctable error int host" "0,1" newline bitfld.long 0x0 28. "CANFD5_IPI_INT_CE,ipi_int_ce from CANFD5 Correctable error interrupt" "0,1" bitfld.long 0x0 27. "CANFD4_IPI_INT_NCEFA,ipi_int_ncefa from CANFD4 Non correctable error int internal" "0,1" bitfld.long 0x0 26. "CANFD4_IPI_INT_NCEHA,ipi_int_nceha from CANFD4 Non correctable error int host" "0,1" newline bitfld.long 0x0 25. "CANFD4_IPI_INT_CE,ipi_int_ce from CANFD4 Correctable error interrupt" "0,1" bitfld.long 0x0 24. "CANFD3_IPI_INT_NCEFA,ipi_int_ncefa from CANFD3 Non correctable error int internal" "0,1" bitfld.long 0x0 23. "CANFD3_IPI_INT_NCEHA,ipi_int_nceha from CANFD3 Non correctable error int host" "0,1" newline bitfld.long 0x0 22. "CANFD3_IPI_INT_CE,ipi_int_ce from CANFD3 Correctable error interrupt" "0,1" bitfld.long 0x0 21. "CANFD2_IPI_INT_NCEFA,ipi_int_ncefa from CANFD2 Non correctable error int internal" "0,1" bitfld.long 0x0 20. "CANFD2_IPI_INT_NCEHA,ipi_int_nceha from CANFD2 Non correctable error int host" "0,1" newline bitfld.long 0x0 19. "CANFD2_IPI_INT_CE,ipi_int_ce from CANFD2 Correctable error interrupt" "0,1" bitfld.long 0x0 18. "CANFD1_IPI_INT_NCEFA,ipi_int_ncefa from CANFD1 Non correctable error int internal" "0,1" bitfld.long 0x0 17. "CANFD1_IPI_INT_NCEHA,ipi_int_nceha from CANFD1 Non correctable error int host" "0,1" newline bitfld.long 0x0 16. "CANFD1_IPI_INT_CE,ipi_int_ce from CANFD1 Correctable error interrupt" "0,1" bitfld.long 0x0 15. "ENET2_SBD_SFTY_UE_INTR_O,sbd_sfty_ue_intr_o from ENET2" "0,1" bitfld.long 0x0 14. "ENET2_SBD_SFTY_CE_INTR_O,sbd_sfty_ce_intr_o from ENET2" "0,1" newline bitfld.long 0x0 13. "ENET1_SBD_SFTY_UE_INTR_O,sbd_sfty_ue_intr_o from ENET1" "0,1" bitfld.long 0x0 12. "ENET1_SBD_SFTY_CE_INTR_O,sbd_sfty_ce_intr_o from ENET1" "0,1" bitfld.long 0x0 11. "RWMC2_MUL_ERR_INT,mul_err_int from RWMC2" "0,1" newline bitfld.long 0x0 10. "RWMC2_SIG_ERR_INT,sig_err_int from RWMC2" "0,1" bitfld.long 0x0 9. "RWMC1_MUL_ERR_INT,mul_err_int from RWMC1" "0,1" bitfld.long 0x0 8. "RWMC1_SIG_ERR_INT,sig_err_int from RWMC1" "0,1" newline bitfld.long 0x0 7. "IRAM4_MUL_ERR_INT,mul_err_int from IRAM4" "0,1" bitfld.long 0x0 6. "IRAM4_SIG_ERR_INT,sig_err_int from IRAM4" "0,1" bitfld.long 0x0 5. "IRAM3_MUL_ERR_INT,mul_err_int from IRAM3" "0,1" newline bitfld.long 0x0 4. "IRAM3_SIG_ERR_INT,sig_err_int from IRAM3" "0,1" bitfld.long 0x0 3. "IRAM2_MUL_ERR_INT,mul_err_int from IRAM2" "0,1" bitfld.long 0x0 2. "IRAM2_SIG_ERR_INT,sig_err_int from IRAM2" "0,1" newline bitfld.long 0x0 1. "IRAM1_MUL_ERR_INT,mul_err_int from IRAM1" "0,1" bitfld.long 0x0 0. "IRAM1_SIG_ERR_INT,sig_err_int from IRAM1" "0,1" repeat.end group.long 0x224++0x3 line.long 0x0 "INT_ENABLE_29,Interrupt Enable 2 for error output to CPU" bitfld.long 0x0 30. "PVT_SNS_SAF_PVT_INT_1,pvt_int_1 from PVT_SNS_SAF" "0,1" bitfld.long 0x0 29. "PVT_SNS_SAF_PVT_INT_0,pvt_int_0 from PVT_SNS_SAF" "0,1" bitfld.long 0x0 28. "PVT_SNS_SEC_PVT_INT_1,pvt_int_1 from PVT_SNS_SEC" "0,1" newline bitfld.long 0x0 27. "PVT_SNS_SEC_PVT_INT_0,pvt_int_0 from PVT_SNS_SEC" "0,1" bitfld.long 0x0 26. "WDT8_ILL_SEQ_REFR_INT,ill_seq_refr_int from WDT8" "0,1" bitfld.long 0x0 25. "WDT8_ILL_WIN_REFR_INT,ill_win_refr_int from WDT8" "0,1" newline bitfld.long 0x0 24. "WDT8_OVFLOW_INT,ovflow_int from WDT8" "0,1" bitfld.long 0x0 23. "WDT7_ILL_SEQ_REFR_INT,ill_seq_refr_int from WDT7" "0,1" bitfld.long 0x0 22. "WDT7_ILL_WIN_REFR_INT,ill_win_refr_int from WDT7" "0,1" newline bitfld.long 0x0 21. "WDT7_OVFLOW_INT,ovflow_int from WDT7" "0,1" bitfld.long 0x0 20. "WDT6_ILL_SEQ_REFR_INT,ill_seq_refr_int from WDT6" "0,1" bitfld.long 0x0 19. "WDT6_ILL_WIN_REFR_INT,ill_win_refr_int from WDT6" "0,1" newline bitfld.long 0x0 18. "WDT6_OVFLOW_INT,ovflow_int from WDT6" "0,1" bitfld.long 0x0 17. "WDT5_ILL_SEQ_REFR_INT,ill_seq_refr_int from WDT5" "0,1" bitfld.long 0x0 16. "WDT5_ILL_WIN_REFR_INT,ill_win_refr_int from WDT5" "0,1" newline bitfld.long 0x0 15. "WDT5_OVFLOW_INT,ovflow_int from WDT5" "0,1" bitfld.long 0x0 14. "WDT4_ILL_SEQ_REFR_INT,ill_seq_refr_int from WDT4" "0,1" bitfld.long 0x0 13. "WDT4_ILL_WIN_REFR_INT,ill_win_refr_int from WDT4" "0,1" newline bitfld.long 0x0 12. "WDT4_OVFLOW_INT,ovflow_int from WDT4" "0,1" bitfld.long 0x0 11. "WDT3_ILL_SEQ_REFR_INT,ill_seq_refr_int from WDT3" "0,1" bitfld.long 0x0 10. "WDT3_ILL_WIN_REFR_INT,ill_win_refr_int from WDT3" "0,1" newline bitfld.long 0x0 9. "WDT3_OVFLOW_INT,ovflow_int from WDT3" "0,1" bitfld.long 0x0 8. "WDT2_ILL_SEQ_REFR_INT,ill_seq_refr_int from WDT2" "0,1" bitfld.long 0x0 7. "WDT2_ILL_WIN_REFR_INT,ill_win_refr_int from WDT2" "0,1" newline bitfld.long 0x0 6. "WDT2_OVFLOW_INT,ovflow_int from WDT2" "0,1" bitfld.long 0x0 5. "WDT1_ILL_SEQ_REFR_INT,ill_seq_refr_int from WDT1" "0,1" bitfld.long 0x0 4. "WDT1_ILL_WIN_REFR_INT,ill_win_refr_int from WDT1" "0,1" newline bitfld.long 0x0 3. "WDT1_OVFLOW_INT,ovflow_int from WDT1" "0,1" bitfld.long 0x0 2. "PWR_LAT_RTC_AP_POWER_LAT,ap_power_lat from PWR_LAT_RTC AP domain power fail" "0,1" bitfld.long 0x0 1. "PWR_LAT_RTC_SAF_POWER_LAT,saf_power_lat from PWR_LAT_RTC SAF domain power fail" "0,1" newline bitfld.long 0x0 0. "PWR_LAT_SAF_SAF_POWER_LAT,saf_power_lat from PWR_LAT_SAF SAF power fail" "0,1" repeat 9. (list 0x1E 0x1F 0x20 0x21 0x22 0x23 0x24 0x25 0x26 )(list 0x0 0x4 0x8 0xC 0x10 0x14 0x18 0x1C 0x20 ) group.long ($2+0x280)++0x3 line.long 0x0 "INT_ENABLE_$1,Interrupt Enable 3 for error output to rstgen" bitfld.long 0x0 31. "CANFD6_IPI_INT_CE,ipi_int_ce from CANFD6 Correctable error interrupt" "0,1" bitfld.long 0x0 30. "CANFD5_IPI_INT_NCEFA,ipi_int_ncefa from CANFD5 Non correctable error int internal" "0,1" bitfld.long 0x0 29. "CANFD5_IPI_INT_NCEHA,ipi_int_nceha from CANFD5 Non correctable error int host" "0,1" newline bitfld.long 0x0 28. "CANFD5_IPI_INT_CE,ipi_int_ce from CANFD5 Correctable error interrupt" "0,1" bitfld.long 0x0 27. "CANFD4_IPI_INT_NCEFA,ipi_int_ncefa from CANFD4 Non correctable error int internal" "0,1" bitfld.long 0x0 26. "CANFD4_IPI_INT_NCEHA,ipi_int_nceha from CANFD4 Non correctable error int host" "0,1" newline bitfld.long 0x0 25. "CANFD4_IPI_INT_CE,ipi_int_ce from CANFD4 Correctable error interrupt" "0,1" bitfld.long 0x0 24. "CANFD3_IPI_INT_NCEFA,ipi_int_ncefa from CANFD3 Non correctable error int internal" "0,1" bitfld.long 0x0 23. "CANFD3_IPI_INT_NCEHA,ipi_int_nceha from CANFD3 Non correctable error int host" "0,1" newline bitfld.long 0x0 22. "CANFD3_IPI_INT_CE,ipi_int_ce from CANFD3 Correctable error interrupt" "0,1" bitfld.long 0x0 21. "CANFD2_IPI_INT_NCEFA,ipi_int_ncefa from CANFD2 Non correctable error int internal" "0,1" bitfld.long 0x0 20. "CANFD2_IPI_INT_NCEHA,ipi_int_nceha from CANFD2 Non correctable error int host" "0,1" newline bitfld.long 0x0 19. "CANFD2_IPI_INT_CE,ipi_int_ce from CANFD2 Correctable error interrupt" "0,1" bitfld.long 0x0 18. "CANFD1_IPI_INT_NCEFA,ipi_int_ncefa from CANFD1 Non correctable error int internal" "0,1" bitfld.long 0x0 17. "CANFD1_IPI_INT_NCEHA,ipi_int_nceha from CANFD1 Non correctable error int host" "0,1" newline bitfld.long 0x0 16. "CANFD1_IPI_INT_CE,ipi_int_ce from CANFD1 Correctable error interrupt" "0,1" bitfld.long 0x0 15. "ENET2_SBD_SFTY_UE_INTR_O,sbd_sfty_ue_intr_o from ENET2" "0,1" bitfld.long 0x0 14. "ENET2_SBD_SFTY_CE_INTR_O,sbd_sfty_ce_intr_o from ENET2" "0,1" newline bitfld.long 0x0 13. "ENET1_SBD_SFTY_UE_INTR_O,sbd_sfty_ue_intr_o from ENET1" "0,1" bitfld.long 0x0 12. "ENET1_SBD_SFTY_CE_INTR_O,sbd_sfty_ce_intr_o from ENET1" "0,1" bitfld.long 0x0 11. "RWMC2_MUL_ERR_INT,mul_err_int from RWMC2" "0,1" newline bitfld.long 0x0 10. "RWMC2_SIG_ERR_INT,sig_err_int from RWMC2" "0,1" bitfld.long 0x0 9. "RWMC1_MUL_ERR_INT,mul_err_int from RWMC1" "0,1" bitfld.long 0x0 8. "RWMC1_SIG_ERR_INT,sig_err_int from RWMC1" "0,1" newline bitfld.long 0x0 7. "IRAM4_MUL_ERR_INT,mul_err_int from IRAM4" "0,1" bitfld.long 0x0 6. "IRAM4_SIG_ERR_INT,sig_err_int from IRAM4" "0,1" bitfld.long 0x0 5. "IRAM3_MUL_ERR_INT,mul_err_int from IRAM3" "0,1" newline bitfld.long 0x0 4. "IRAM3_SIG_ERR_INT,sig_err_int from IRAM3" "0,1" bitfld.long 0x0 3. "IRAM2_MUL_ERR_INT,mul_err_int from IRAM2" "0,1" bitfld.long 0x0 2. "IRAM2_SIG_ERR_INT,sig_err_int from IRAM2" "0,1" newline bitfld.long 0x0 1. "IRAM1_MUL_ERR_INT,mul_err_int from IRAM1" "0,1" bitfld.long 0x0 0. "IRAM1_SIG_ERR_INT,sig_err_int from IRAM1" "0,1" repeat.end group.long 0x2A4++0x3 line.long 0x0 "INT_ENABLE_39,Interrupt Enable 3 for error output to rstgen" bitfld.long 0x0 30. "PVT_SNS_SAF_PVT_INT_1,pvt_int_1 from PVT_SNS_SAF" "0,1" bitfld.long 0x0 29. "PVT_SNS_SAF_PVT_INT_0,pvt_int_0 from PVT_SNS_SAF" "0,1" bitfld.long 0x0 28. "PVT_SNS_SEC_PVT_INT_1,pvt_int_1 from PVT_SNS_SEC" "0,1" newline bitfld.long 0x0 27. "PVT_SNS_SEC_PVT_INT_0,pvt_int_0 from PVT_SNS_SEC" "0,1" bitfld.long 0x0 26. "WDT8_ILL_SEQ_REFR_INT,ill_seq_refr_int from WDT8" "0,1" bitfld.long 0x0 25. "WDT8_ILL_WIN_REFR_INT,ill_win_refr_int from WDT8" "0,1" newline bitfld.long 0x0 24. "WDT8_OVFLOW_INT,ovflow_int from WDT8" "0,1" bitfld.long 0x0 23. "WDT7_ILL_SEQ_REFR_INT,ill_seq_refr_int from WDT7" "0,1" bitfld.long 0x0 22. "WDT7_ILL_WIN_REFR_INT,ill_win_refr_int from WDT7" "0,1" newline bitfld.long 0x0 21. "WDT7_OVFLOW_INT,ovflow_int from WDT7" "0,1" bitfld.long 0x0 20. "WDT6_ILL_SEQ_REFR_INT,ill_seq_refr_int from WDT6" "0,1" bitfld.long 0x0 19. "WDT6_ILL_WIN_REFR_INT,ill_win_refr_int from WDT6" "0,1" newline bitfld.long 0x0 18. "WDT6_OVFLOW_INT,ovflow_int from WDT6" "0,1" bitfld.long 0x0 17. "WDT5_ILL_SEQ_REFR_INT,ill_seq_refr_int from WDT5" "0,1" bitfld.long 0x0 16. "WDT5_ILL_WIN_REFR_INT,ill_win_refr_int from WDT5" "0,1" newline bitfld.long 0x0 15. "WDT5_OVFLOW_INT,ovflow_int from WDT5" "0,1" bitfld.long 0x0 14. "WDT4_ILL_SEQ_REFR_INT,ill_seq_refr_int from WDT4" "0,1" bitfld.long 0x0 13. "WDT4_ILL_WIN_REFR_INT,ill_win_refr_int from WDT4" "0,1" newline bitfld.long 0x0 12. "WDT4_OVFLOW_INT,ovflow_int from WDT4" "0,1" bitfld.long 0x0 11. "WDT3_ILL_SEQ_REFR_INT,ill_seq_refr_int from WDT3" "0,1" bitfld.long 0x0 10. "WDT3_ILL_WIN_REFR_INT,ill_win_refr_int from WDT3" "0,1" newline bitfld.long 0x0 9. "WDT3_OVFLOW_INT,ovflow_int from WDT3" "0,1" bitfld.long 0x0 8. "WDT2_ILL_SEQ_REFR_INT,ill_seq_refr_int from WDT2" "0,1" bitfld.long 0x0 7. "WDT2_ILL_WIN_REFR_INT,ill_win_refr_int from WDT2" "0,1" newline bitfld.long 0x0 6. "WDT2_OVFLOW_INT,ovflow_int from WDT2" "0,1" bitfld.long 0x0 5. "WDT1_ILL_SEQ_REFR_INT,ill_seq_refr_int from WDT1" "0,1" bitfld.long 0x0 4. "WDT1_ILL_WIN_REFR_INT,ill_win_refr_int from WDT1" "0,1" newline bitfld.long 0x0 3. "WDT1_OVFLOW_INT,ovflow_int from WDT1" "0,1" bitfld.long 0x0 2. "PWR_LAT_RTC_AP_POWER_LAT,ap_power_lat from PWR_LAT_RTC AP domain power fail" "0,1" bitfld.long 0x0 1. "PWR_LAT_RTC_SAF_POWER_LAT,saf_power_lat from PWR_LAT_RTC SAF domain power fail" "0,1" newline bitfld.long 0x0 0. "PWR_LAT_SAF_SAF_POWER_LAT,saf_power_lat from PWR_LAT_SAF SAF power fail" "0,1" repeat 9. (list 0x28 0x29 0x2A 0x2B 0x2C 0x2D 0x2E 0x2F 0x30 )(list 0x0 0x4 0x8 0xC 0x10 0x14 0x18 0x1C 0x20 ) group.long ($2+0x300)++0x3 line.long 0x0 "INT_ENABLE_$1,Interrupt Enable 4 for error output to DC" bitfld.long 0x0 31. "CANFD6_IPI_INT_CE,ipi_int_ce from CANFD6 Correctable error interrupt" "0,1" bitfld.long 0x0 30. "CANFD5_IPI_INT_NCEFA,ipi_int_ncefa from CANFD5 Non correctable error int internal" "0,1" bitfld.long 0x0 29. "CANFD5_IPI_INT_NCEHA,ipi_int_nceha from CANFD5 Non correctable error int host" "0,1" newline bitfld.long 0x0 28. "CANFD5_IPI_INT_CE,ipi_int_ce from CANFD5 Correctable error interrupt" "0,1" bitfld.long 0x0 27. "CANFD4_IPI_INT_NCEFA,ipi_int_ncefa from CANFD4 Non correctable error int internal" "0,1" bitfld.long 0x0 26. "CANFD4_IPI_INT_NCEHA,ipi_int_nceha from CANFD4 Non correctable error int host" "0,1" newline bitfld.long 0x0 25. "CANFD4_IPI_INT_CE,ipi_int_ce from CANFD4 Correctable error interrupt" "0,1" bitfld.long 0x0 24. "CANFD3_IPI_INT_NCEFA,ipi_int_ncefa from CANFD3 Non correctable error int internal" "0,1" bitfld.long 0x0 23. "CANFD3_IPI_INT_NCEHA,ipi_int_nceha from CANFD3 Non correctable error int host" "0,1" newline bitfld.long 0x0 22. "CANFD3_IPI_INT_CE,ipi_int_ce from CANFD3 Correctable error interrupt" "0,1" bitfld.long 0x0 21. "CANFD2_IPI_INT_NCEFA,ipi_int_ncefa from CANFD2 Non correctable error int internal" "0,1" bitfld.long 0x0 20. "CANFD2_IPI_INT_NCEHA,ipi_int_nceha from CANFD2 Non correctable error int host" "0,1" newline bitfld.long 0x0 19. "CANFD2_IPI_INT_CE,ipi_int_ce from CANFD2 Correctable error interrupt" "0,1" bitfld.long 0x0 18. "CANFD1_IPI_INT_NCEFA,ipi_int_ncefa from CANFD1 Non correctable error int internal" "0,1" bitfld.long 0x0 17. "CANFD1_IPI_INT_NCEHA,ipi_int_nceha from CANFD1 Non correctable error int host" "0,1" newline bitfld.long 0x0 16. "CANFD1_IPI_INT_CE,ipi_int_ce from CANFD1 Correctable error interrupt" "0,1" bitfld.long 0x0 15. "ENET2_SBD_SFTY_UE_INTR_O,sbd_sfty_ue_intr_o from ENET2" "0,1" bitfld.long 0x0 14. "ENET2_SBD_SFTY_CE_INTR_O,sbd_sfty_ce_intr_o from ENET2" "0,1" newline bitfld.long 0x0 13. "ENET1_SBD_SFTY_UE_INTR_O,sbd_sfty_ue_intr_o from ENET1" "0,1" bitfld.long 0x0 12. "ENET1_SBD_SFTY_CE_INTR_O,sbd_sfty_ce_intr_o from ENET1" "0,1" bitfld.long 0x0 11. "RWMC2_MUL_ERR_INT,mul_err_int from RWMC2" "0,1" newline bitfld.long 0x0 10. "RWMC2_SIG_ERR_INT,sig_err_int from RWMC2" "0,1" bitfld.long 0x0 9. "RWMC1_MUL_ERR_INT,mul_err_int from RWMC1" "0,1" bitfld.long 0x0 8. "RWMC1_SIG_ERR_INT,sig_err_int from RWMC1" "0,1" newline bitfld.long 0x0 7. "IRAM4_MUL_ERR_INT,mul_err_int from IRAM4" "0,1" bitfld.long 0x0 6. "IRAM4_SIG_ERR_INT,sig_err_int from IRAM4" "0,1" bitfld.long 0x0 5. "IRAM3_MUL_ERR_INT,mul_err_int from IRAM3" "0,1" newline bitfld.long 0x0 4. "IRAM3_SIG_ERR_INT,sig_err_int from IRAM3" "0,1" bitfld.long 0x0 3. "IRAM2_MUL_ERR_INT,mul_err_int from IRAM2" "0,1" bitfld.long 0x0 2. "IRAM2_SIG_ERR_INT,sig_err_int from IRAM2" "0,1" newline bitfld.long 0x0 1. "IRAM1_MUL_ERR_INT,mul_err_int from IRAM1" "0,1" bitfld.long 0x0 0. "IRAM1_SIG_ERR_INT,sig_err_int from IRAM1" "0,1" repeat.end group.long 0x324++0x3 line.long 0x0 "INT_ENABLE_49,Interrupt Enable 4 for error output to DC" bitfld.long 0x0 30. "PVT_SNS_SAF_PVT_INT_1,pvt_int_1 from PVT_SNS_SAF" "0,1" bitfld.long 0x0 29. "PVT_SNS_SAF_PVT_INT_0,pvt_int_0 from PVT_SNS_SAF" "0,1" bitfld.long 0x0 28. "PVT_SNS_SEC_PVT_INT_1,pvt_int_1 from PVT_SNS_SEC" "0,1" newline bitfld.long 0x0 27. "PVT_SNS_SEC_PVT_INT_0,pvt_int_0 from PVT_SNS_SEC" "0,1" bitfld.long 0x0 26. "WDT8_ILL_SEQ_REFR_INT,ill_seq_refr_int from WDT8" "0,1" bitfld.long 0x0 25. "WDT8_ILL_WIN_REFR_INT,ill_win_refr_int from WDT8" "0,1" newline bitfld.long 0x0 24. "WDT8_OVFLOW_INT,ovflow_int from WDT8" "0,1" bitfld.long 0x0 23. "WDT7_ILL_SEQ_REFR_INT,ill_seq_refr_int from WDT7" "0,1" bitfld.long 0x0 22. "WDT7_ILL_WIN_REFR_INT,ill_win_refr_int from WDT7" "0,1" newline bitfld.long 0x0 21. "WDT7_OVFLOW_INT,ovflow_int from WDT7" "0,1" bitfld.long 0x0 20. "WDT6_ILL_SEQ_REFR_INT,ill_seq_refr_int from WDT6" "0,1" bitfld.long 0x0 19. "WDT6_ILL_WIN_REFR_INT,ill_win_refr_int from WDT6" "0,1" newline bitfld.long 0x0 18. "WDT6_OVFLOW_INT,ovflow_int from WDT6" "0,1" bitfld.long 0x0 17. "WDT5_ILL_SEQ_REFR_INT,ill_seq_refr_int from WDT5" "0,1" bitfld.long 0x0 16. "WDT5_ILL_WIN_REFR_INT,ill_win_refr_int from WDT5" "0,1" newline bitfld.long 0x0 15. "WDT5_OVFLOW_INT,ovflow_int from WDT5" "0,1" bitfld.long 0x0 14. "WDT4_ILL_SEQ_REFR_INT,ill_seq_refr_int from WDT4" "0,1" bitfld.long 0x0 13. "WDT4_ILL_WIN_REFR_INT,ill_win_refr_int from WDT4" "0,1" newline bitfld.long 0x0 12. "WDT4_OVFLOW_INT,ovflow_int from WDT4" "0,1" bitfld.long 0x0 11. "WDT3_ILL_SEQ_REFR_INT,ill_seq_refr_int from WDT3" "0,1" bitfld.long 0x0 10. "WDT3_ILL_WIN_REFR_INT,ill_win_refr_int from WDT3" "0,1" newline bitfld.long 0x0 9. "WDT3_OVFLOW_INT,ovflow_int from WDT3" "0,1" bitfld.long 0x0 8. "WDT2_ILL_SEQ_REFR_INT,ill_seq_refr_int from WDT2" "0,1" bitfld.long 0x0 7. "WDT2_ILL_WIN_REFR_INT,ill_win_refr_int from WDT2" "0,1" newline bitfld.long 0x0 6. "WDT2_OVFLOW_INT,ovflow_int from WDT2" "0,1" bitfld.long 0x0 5. "WDT1_ILL_SEQ_REFR_INT,ill_seq_refr_int from WDT1" "0,1" bitfld.long 0x0 4. "WDT1_ILL_WIN_REFR_INT,ill_win_refr_int from WDT1" "0,1" newline bitfld.long 0x0 3. "WDT1_OVFLOW_INT,ovflow_int from WDT1" "0,1" bitfld.long 0x0 2. "PWR_LAT_RTC_AP_POWER_LAT,ap_power_lat from PWR_LAT_RTC AP domain power fail" "0,1" bitfld.long 0x0 1. "PWR_LAT_RTC_SAF_POWER_LAT,saf_power_lat from PWR_LAT_RTC SAF domain power fail" "0,1" newline bitfld.long 0x0 0. "PWR_LAT_SAF_SAF_POWER_LAT,saf_power_lat from PWR_LAT_SAF SAF power fail" "0,1" repeat 9. (list 0x32 0x33 0x34 0x35 0x36 0x37 0x38 0x39 0x3A )(list 0x0 0x4 0x8 0xC 0x10 0x14 0x18 0x1C 0x20 ) group.long ($2+0x380)++0x3 line.long 0x0 "INT_ENABLE_$1,Interrupt Enable 5 for error output to DC" bitfld.long 0x0 31. "CANFD6_IPI_INT_CE,ipi_int_ce from CANFD6 Correctable error interrupt" "0,1" bitfld.long 0x0 30. "CANFD5_IPI_INT_NCEFA,ipi_int_ncefa from CANFD5 Non correctable error int internal" "0,1" bitfld.long 0x0 29. "CANFD5_IPI_INT_NCEHA,ipi_int_nceha from CANFD5 Non correctable error int host" "0,1" newline bitfld.long 0x0 28. "CANFD5_IPI_INT_CE,ipi_int_ce from CANFD5 Correctable error interrupt" "0,1" bitfld.long 0x0 27. "CANFD4_IPI_INT_NCEFA,ipi_int_ncefa from CANFD4 Non correctable error int internal" "0,1" bitfld.long 0x0 26. "CANFD4_IPI_INT_NCEHA,ipi_int_nceha from CANFD4 Non correctable error int host" "0,1" newline bitfld.long 0x0 25. "CANFD4_IPI_INT_CE,ipi_int_ce from CANFD4 Correctable error interrupt" "0,1" bitfld.long 0x0 24. "CANFD3_IPI_INT_NCEFA,ipi_int_ncefa from CANFD3 Non correctable error int internal" "0,1" bitfld.long 0x0 23. "CANFD3_IPI_INT_NCEHA,ipi_int_nceha from CANFD3 Non correctable error int host" "0,1" newline bitfld.long 0x0 22. "CANFD3_IPI_INT_CE,ipi_int_ce from CANFD3 Correctable error interrupt" "0,1" bitfld.long 0x0 21. "CANFD2_IPI_INT_NCEFA,ipi_int_ncefa from CANFD2 Non correctable error int internal" "0,1" bitfld.long 0x0 20. "CANFD2_IPI_INT_NCEHA,ipi_int_nceha from CANFD2 Non correctable error int host" "0,1" newline bitfld.long 0x0 19. "CANFD2_IPI_INT_CE,ipi_int_ce from CANFD2 Correctable error interrupt" "0,1" bitfld.long 0x0 18. "CANFD1_IPI_INT_NCEFA,ipi_int_ncefa from CANFD1 Non correctable error int internal" "0,1" bitfld.long 0x0 17. "CANFD1_IPI_INT_NCEHA,ipi_int_nceha from CANFD1 Non correctable error int host" "0,1" newline bitfld.long 0x0 16. "CANFD1_IPI_INT_CE,ipi_int_ce from CANFD1 Correctable error interrupt" "0,1" bitfld.long 0x0 15. "ENET2_SBD_SFTY_UE_INTR_O,sbd_sfty_ue_intr_o from ENET2" "0,1" bitfld.long 0x0 14. "ENET2_SBD_SFTY_CE_INTR_O,sbd_sfty_ce_intr_o from ENET2" "0,1" newline bitfld.long 0x0 13. "ENET1_SBD_SFTY_UE_INTR_O,sbd_sfty_ue_intr_o from ENET1" "0,1" bitfld.long 0x0 12. "ENET1_SBD_SFTY_CE_INTR_O,sbd_sfty_ce_intr_o from ENET1" "0,1" bitfld.long 0x0 11. "RWMC2_MUL_ERR_INT,mul_err_int from RWMC2" "0,1" newline bitfld.long 0x0 10. "RWMC2_SIG_ERR_INT,sig_err_int from RWMC2" "0,1" bitfld.long 0x0 9. "RWMC1_MUL_ERR_INT,mul_err_int from RWMC1" "0,1" bitfld.long 0x0 8. "RWMC1_SIG_ERR_INT,sig_err_int from RWMC1" "0,1" newline bitfld.long 0x0 7. "IRAM4_MUL_ERR_INT,mul_err_int from IRAM4" "0,1" bitfld.long 0x0 6. "IRAM4_SIG_ERR_INT,sig_err_int from IRAM4" "0,1" bitfld.long 0x0 5. "IRAM3_MUL_ERR_INT,mul_err_int from IRAM3" "0,1" newline bitfld.long 0x0 4. "IRAM3_SIG_ERR_INT,sig_err_int from IRAM3" "0,1" bitfld.long 0x0 3. "IRAM2_MUL_ERR_INT,mul_err_int from IRAM2" "0,1" bitfld.long 0x0 2. "IRAM2_SIG_ERR_INT,sig_err_int from IRAM2" "0,1" newline bitfld.long 0x0 1. "IRAM1_MUL_ERR_INT,mul_err_int from IRAM1" "0,1" bitfld.long 0x0 0. "IRAM1_SIG_ERR_INT,sig_err_int from IRAM1" "0,1" repeat.end group.long 0x3A4++0x3 line.long 0x0 "INT_ENABLE_59,Interrupt Enable 5 for error output to DC" bitfld.long 0x0 30. "PVT_SNS_SAF_PVT_INT_1,pvt_int_1 from PVT_SNS_SAF" "0,1" bitfld.long 0x0 29. "PVT_SNS_SAF_PVT_INT_0,pvt_int_0 from PVT_SNS_SAF" "0,1" bitfld.long 0x0 28. "PVT_SNS_SEC_PVT_INT_1,pvt_int_1 from PVT_SNS_SEC" "0,1" newline bitfld.long 0x0 27. "PVT_SNS_SEC_PVT_INT_0,pvt_int_0 from PVT_SNS_SEC" "0,1" bitfld.long 0x0 26. "WDT8_ILL_SEQ_REFR_INT,ill_seq_refr_int from WDT8" "0,1" bitfld.long 0x0 25. "WDT8_ILL_WIN_REFR_INT,ill_win_refr_int from WDT8" "0,1" newline bitfld.long 0x0 24. "WDT8_OVFLOW_INT,ovflow_int from WDT8" "0,1" bitfld.long 0x0 23. "WDT7_ILL_SEQ_REFR_INT,ill_seq_refr_int from WDT7" "0,1" bitfld.long 0x0 22. "WDT7_ILL_WIN_REFR_INT,ill_win_refr_int from WDT7" "0,1" newline bitfld.long 0x0 21. "WDT7_OVFLOW_INT,ovflow_int from WDT7" "0,1" bitfld.long 0x0 20. "WDT6_ILL_SEQ_REFR_INT,ill_seq_refr_int from WDT6" "0,1" bitfld.long 0x0 19. "WDT6_ILL_WIN_REFR_INT,ill_win_refr_int from WDT6" "0,1" newline bitfld.long 0x0 18. "WDT6_OVFLOW_INT,ovflow_int from WDT6" "0,1" bitfld.long 0x0 17. "WDT5_ILL_SEQ_REFR_INT,ill_seq_refr_int from WDT5" "0,1" bitfld.long 0x0 16. "WDT5_ILL_WIN_REFR_INT,ill_win_refr_int from WDT5" "0,1" newline bitfld.long 0x0 15. "WDT5_OVFLOW_INT,ovflow_int from WDT5" "0,1" bitfld.long 0x0 14. "WDT4_ILL_SEQ_REFR_INT,ill_seq_refr_int from WDT4" "0,1" bitfld.long 0x0 13. "WDT4_ILL_WIN_REFR_INT,ill_win_refr_int from WDT4" "0,1" newline bitfld.long 0x0 12. "WDT4_OVFLOW_INT,ovflow_int from WDT4" "0,1" bitfld.long 0x0 11. "WDT3_ILL_SEQ_REFR_INT,ill_seq_refr_int from WDT3" "0,1" bitfld.long 0x0 10. "WDT3_ILL_WIN_REFR_INT,ill_win_refr_int from WDT3" "0,1" newline bitfld.long 0x0 9. "WDT3_OVFLOW_INT,ovflow_int from WDT3" "0,1" bitfld.long 0x0 8. "WDT2_ILL_SEQ_REFR_INT,ill_seq_refr_int from WDT2" "0,1" bitfld.long 0x0 7. "WDT2_ILL_WIN_REFR_INT,ill_win_refr_int from WDT2" "0,1" newline bitfld.long 0x0 6. "WDT2_OVFLOW_INT,ovflow_int from WDT2" "0,1" bitfld.long 0x0 5. "WDT1_ILL_SEQ_REFR_INT,ill_seq_refr_int from WDT1" "0,1" bitfld.long 0x0 4. "WDT1_ILL_WIN_REFR_INT,ill_win_refr_int from WDT1" "0,1" newline bitfld.long 0x0 3. "WDT1_OVFLOW_INT,ovflow_int from WDT1" "0,1" bitfld.long 0x0 2. "PWR_LAT_RTC_AP_POWER_LAT,ap_power_lat from PWR_LAT_RTC AP domain power fail" "0,1" bitfld.long 0x0 1. "PWR_LAT_RTC_SAF_POWER_LAT,saf_power_lat from PWR_LAT_RTC SAF domain power fail" "0,1" newline bitfld.long 0x0 0. "PWR_LAT_SAF_SAF_POWER_LAT,saf_power_lat from PWR_LAT_SAF SAF power fail" "0,1" repeat 9. (list 0x3C 0x3D 0x3E 0x3F 0x40 0x41 0x42 0x43 0x44 )(list 0x0 0x4 0x8 0xC 0x10 0x14 0x18 0x1C 0x20 ) group.long ($2+0x400)++0x3 line.long 0x0 "INT_ENABLE_$1,Interrupt Enable 6 for error output to DC" bitfld.long 0x0 31. "CANFD6_IPI_INT_CE,ipi_int_ce from CANFD6 Correctable error interrupt" "0,1" bitfld.long 0x0 30. "CANFD5_IPI_INT_NCEFA,ipi_int_ncefa from CANFD5 Non correctable error int internal" "0,1" bitfld.long 0x0 29. "CANFD5_IPI_INT_NCEHA,ipi_int_nceha from CANFD5 Non correctable error int host" "0,1" newline bitfld.long 0x0 28. "CANFD5_IPI_INT_CE,ipi_int_ce from CANFD5 Correctable error interrupt" "0,1" bitfld.long 0x0 27. "CANFD4_IPI_INT_NCEFA,ipi_int_ncefa from CANFD4 Non correctable error int internal" "0,1" bitfld.long 0x0 26. "CANFD4_IPI_INT_NCEHA,ipi_int_nceha from CANFD4 Non correctable error int host" "0,1" newline bitfld.long 0x0 25. "CANFD4_IPI_INT_CE,ipi_int_ce from CANFD4 Correctable error interrupt" "0,1" bitfld.long 0x0 24. "CANFD3_IPI_INT_NCEFA,ipi_int_ncefa from CANFD3 Non correctable error int internal" "0,1" bitfld.long 0x0 23. "CANFD3_IPI_INT_NCEHA,ipi_int_nceha from CANFD3 Non correctable error int host" "0,1" newline bitfld.long 0x0 22. "CANFD3_IPI_INT_CE,ipi_int_ce from CANFD3 Correctable error interrupt" "0,1" bitfld.long 0x0 21. "CANFD2_IPI_INT_NCEFA,ipi_int_ncefa from CANFD2 Non correctable error int internal" "0,1" bitfld.long 0x0 20. "CANFD2_IPI_INT_NCEHA,ipi_int_nceha from CANFD2 Non correctable error int host" "0,1" newline bitfld.long 0x0 19. "CANFD2_IPI_INT_CE,ipi_int_ce from CANFD2 Correctable error interrupt" "0,1" bitfld.long 0x0 18. "CANFD1_IPI_INT_NCEFA,ipi_int_ncefa from CANFD1 Non correctable error int internal" "0,1" bitfld.long 0x0 17. "CANFD1_IPI_INT_NCEHA,ipi_int_nceha from CANFD1 Non correctable error int host" "0,1" newline bitfld.long 0x0 16. "CANFD1_IPI_INT_CE,ipi_int_ce from CANFD1 Correctable error interrupt" "0,1" bitfld.long 0x0 15. "ENET2_SBD_SFTY_UE_INTR_O,sbd_sfty_ue_intr_o from ENET2" "0,1" bitfld.long 0x0 14. "ENET2_SBD_SFTY_CE_INTR_O,sbd_sfty_ce_intr_o from ENET2" "0,1" newline bitfld.long 0x0 13. "ENET1_SBD_SFTY_UE_INTR_O,sbd_sfty_ue_intr_o from ENET1" "0,1" bitfld.long 0x0 12. "ENET1_SBD_SFTY_CE_INTR_O,sbd_sfty_ce_intr_o from ENET1" "0,1" bitfld.long 0x0 11. "RWMC2_MUL_ERR_INT,mul_err_int from RWMC2" "0,1" newline bitfld.long 0x0 10. "RWMC2_SIG_ERR_INT,sig_err_int from RWMC2" "0,1" bitfld.long 0x0 9. "RWMC1_MUL_ERR_INT,mul_err_int from RWMC1" "0,1" bitfld.long 0x0 8. "RWMC1_SIG_ERR_INT,sig_err_int from RWMC1" "0,1" newline bitfld.long 0x0 7. "IRAM4_MUL_ERR_INT,mul_err_int from IRAM4" "0,1" bitfld.long 0x0 6. "IRAM4_SIG_ERR_INT,sig_err_int from IRAM4" "0,1" bitfld.long 0x0 5. "IRAM3_MUL_ERR_INT,mul_err_int from IRAM3" "0,1" newline bitfld.long 0x0 4. "IRAM3_SIG_ERR_INT,sig_err_int from IRAM3" "0,1" bitfld.long 0x0 3. "IRAM2_MUL_ERR_INT,mul_err_int from IRAM2" "0,1" bitfld.long 0x0 2. "IRAM2_SIG_ERR_INT,sig_err_int from IRAM2" "0,1" newline bitfld.long 0x0 1. "IRAM1_MUL_ERR_INT,mul_err_int from IRAM1" "0,1" bitfld.long 0x0 0. "IRAM1_SIG_ERR_INT,sig_err_int from IRAM1" "0,1" repeat.end group.long 0x424++0x3 line.long 0x0 "INT_ENABLE_69,Interrupt Enable 6 for error output to DC" bitfld.long 0x0 30. "PVT_SNS_SAF_PVT_INT_1,pvt_int_1 from PVT_SNS_SAF" "0,1" bitfld.long 0x0 29. "PVT_SNS_SAF_PVT_INT_0,pvt_int_0 from PVT_SNS_SAF" "0,1" bitfld.long 0x0 28. "PVT_SNS_SEC_PVT_INT_1,pvt_int_1 from PVT_SNS_SEC" "0,1" newline bitfld.long 0x0 27. "PVT_SNS_SEC_PVT_INT_0,pvt_int_0 from PVT_SNS_SEC" "0,1" bitfld.long 0x0 26. "WDT8_ILL_SEQ_REFR_INT,ill_seq_refr_int from WDT8" "0,1" bitfld.long 0x0 25. "WDT8_ILL_WIN_REFR_INT,ill_win_refr_int from WDT8" "0,1" newline bitfld.long 0x0 24. "WDT8_OVFLOW_INT,ovflow_int from WDT8" "0,1" bitfld.long 0x0 23. "WDT7_ILL_SEQ_REFR_INT,ill_seq_refr_int from WDT7" "0,1" bitfld.long 0x0 22. "WDT7_ILL_WIN_REFR_INT,ill_win_refr_int from WDT7" "0,1" newline bitfld.long 0x0 21. "WDT7_OVFLOW_INT,ovflow_int from WDT7" "0,1" bitfld.long 0x0 20. "WDT6_ILL_SEQ_REFR_INT,ill_seq_refr_int from WDT6" "0,1" bitfld.long 0x0 19. "WDT6_ILL_WIN_REFR_INT,ill_win_refr_int from WDT6" "0,1" newline bitfld.long 0x0 18. "WDT6_OVFLOW_INT,ovflow_int from WDT6" "0,1" bitfld.long 0x0 17. "WDT5_ILL_SEQ_REFR_INT,ill_seq_refr_int from WDT5" "0,1" bitfld.long 0x0 16. "WDT5_ILL_WIN_REFR_INT,ill_win_refr_int from WDT5" "0,1" newline bitfld.long 0x0 15. "WDT5_OVFLOW_INT,ovflow_int from WDT5" "0,1" bitfld.long 0x0 14. "WDT4_ILL_SEQ_REFR_INT,ill_seq_refr_int from WDT4" "0,1" bitfld.long 0x0 13. "WDT4_ILL_WIN_REFR_INT,ill_win_refr_int from WDT4" "0,1" newline bitfld.long 0x0 12. "WDT4_OVFLOW_INT,ovflow_int from WDT4" "0,1" bitfld.long 0x0 11. "WDT3_ILL_SEQ_REFR_INT,ill_seq_refr_int from WDT3" "0,1" bitfld.long 0x0 10. "WDT3_ILL_WIN_REFR_INT,ill_win_refr_int from WDT3" "0,1" newline bitfld.long 0x0 9. "WDT3_OVFLOW_INT,ovflow_int from WDT3" "0,1" bitfld.long 0x0 8. "WDT2_ILL_SEQ_REFR_INT,ill_seq_refr_int from WDT2" "0,1" bitfld.long 0x0 7. "WDT2_ILL_WIN_REFR_INT,ill_win_refr_int from WDT2" "0,1" newline bitfld.long 0x0 6. "WDT2_OVFLOW_INT,ovflow_int from WDT2" "0,1" bitfld.long 0x0 5. "WDT1_ILL_SEQ_REFR_INT,ill_seq_refr_int from WDT1" "0,1" bitfld.long 0x0 4. "WDT1_ILL_WIN_REFR_INT,ill_win_refr_int from WDT1" "0,1" newline bitfld.long 0x0 3. "WDT1_OVFLOW_INT,ovflow_int from WDT1" "0,1" bitfld.long 0x0 2. "PWR_LAT_RTC_AP_POWER_LAT,ap_power_lat from PWR_LAT_RTC AP domain power fail" "0,1" bitfld.long 0x0 1. "PWR_LAT_RTC_SAF_POWER_LAT,saf_power_lat from PWR_LAT_RTC SAF domain power fail" "0,1" newline bitfld.long 0x0 0. "PWR_LAT_SAF_SAF_POWER_LAT,saf_power_lat from PWR_LAT_SAF SAF power fail" "0,1" repeat 9. (list 0x46 0x47 0x48 0x49 0x4A 0x4B 0x4C 0x4D 0x4E )(list 0x0 0x4 0x8 0xC 0x10 0x14 0x18 0x1C 0x20 ) group.long ($2+0x480)++0x3 line.long 0x0 "INT_ENABLE_$1,Interrupt Enable 7 for error output to DC" bitfld.long 0x0 31. "CANFD6_IPI_INT_CE,ipi_int_ce from CANFD6 Correctable error interrupt" "0,1" bitfld.long 0x0 30. "CANFD5_IPI_INT_NCEFA,ipi_int_ncefa from CANFD5 Non correctable error int internal" "0,1" bitfld.long 0x0 29. "CANFD5_IPI_INT_NCEHA,ipi_int_nceha from CANFD5 Non correctable error int host" "0,1" newline bitfld.long 0x0 28. "CANFD5_IPI_INT_CE,ipi_int_ce from CANFD5 Correctable error interrupt" "0,1" bitfld.long 0x0 27. "CANFD4_IPI_INT_NCEFA,ipi_int_ncefa from CANFD4 Non correctable error int internal" "0,1" bitfld.long 0x0 26. "CANFD4_IPI_INT_NCEHA,ipi_int_nceha from CANFD4 Non correctable error int host" "0,1" newline bitfld.long 0x0 25. "CANFD4_IPI_INT_CE,ipi_int_ce from CANFD4 Correctable error interrupt" "0,1" bitfld.long 0x0 24. "CANFD3_IPI_INT_NCEFA,ipi_int_ncefa from CANFD3 Non correctable error int internal" "0,1" bitfld.long 0x0 23. "CANFD3_IPI_INT_NCEHA,ipi_int_nceha from CANFD3 Non correctable error int host" "0,1" newline bitfld.long 0x0 22. "CANFD3_IPI_INT_CE,ipi_int_ce from CANFD3 Correctable error interrupt" "0,1" bitfld.long 0x0 21. "CANFD2_IPI_INT_NCEFA,ipi_int_ncefa from CANFD2 Non correctable error int internal" "0,1" bitfld.long 0x0 20. "CANFD2_IPI_INT_NCEHA,ipi_int_nceha from CANFD2 Non correctable error int host" "0,1" newline bitfld.long 0x0 19. "CANFD2_IPI_INT_CE,ipi_int_ce from CANFD2 Correctable error interrupt" "0,1" bitfld.long 0x0 18. "CANFD1_IPI_INT_NCEFA,ipi_int_ncefa from CANFD1 Non correctable error int internal" "0,1" bitfld.long 0x0 17. "CANFD1_IPI_INT_NCEHA,ipi_int_nceha from CANFD1 Non correctable error int host" "0,1" newline bitfld.long 0x0 16. "CANFD1_IPI_INT_CE,ipi_int_ce from CANFD1 Correctable error interrupt" "0,1" bitfld.long 0x0 15. "ENET2_SBD_SFTY_UE_INTR_O,sbd_sfty_ue_intr_o from ENET2" "0,1" bitfld.long 0x0 14. "ENET2_SBD_SFTY_CE_INTR_O,sbd_sfty_ce_intr_o from ENET2" "0,1" newline bitfld.long 0x0 13. "ENET1_SBD_SFTY_UE_INTR_O,sbd_sfty_ue_intr_o from ENET1" "0,1" bitfld.long 0x0 12. "ENET1_SBD_SFTY_CE_INTR_O,sbd_sfty_ce_intr_o from ENET1" "0,1" bitfld.long 0x0 11. "RWMC2_MUL_ERR_INT,mul_err_int from RWMC2" "0,1" newline bitfld.long 0x0 10. "RWMC2_SIG_ERR_INT,sig_err_int from RWMC2" "0,1" bitfld.long 0x0 9. "RWMC1_MUL_ERR_INT,mul_err_int from RWMC1" "0,1" bitfld.long 0x0 8. "RWMC1_SIG_ERR_INT,sig_err_int from RWMC1" "0,1" newline bitfld.long 0x0 7. "IRAM4_MUL_ERR_INT,mul_err_int from IRAM4" "0,1" bitfld.long 0x0 6. "IRAM4_SIG_ERR_INT,sig_err_int from IRAM4" "0,1" bitfld.long 0x0 5. "IRAM3_MUL_ERR_INT,mul_err_int from IRAM3" "0,1" newline bitfld.long 0x0 4. "IRAM3_SIG_ERR_INT,sig_err_int from IRAM3" "0,1" bitfld.long 0x0 3. "IRAM2_MUL_ERR_INT,mul_err_int from IRAM2" "0,1" bitfld.long 0x0 2. "IRAM2_SIG_ERR_INT,sig_err_int from IRAM2" "0,1" newline bitfld.long 0x0 1. "IRAM1_MUL_ERR_INT,mul_err_int from IRAM1" "0,1" bitfld.long 0x0 0. "IRAM1_SIG_ERR_INT,sig_err_int from IRAM1" "0,1" repeat.end group.long 0x4A4++0x3 line.long 0x0 "INT_ENABLE_79,Interrupt Enable 7 for error output to DC" bitfld.long 0x0 30. "PVT_SNS_SAF_PVT_INT_1,pvt_int_1 from PVT_SNS_SAF" "0,1" bitfld.long 0x0 29. "PVT_SNS_SAF_PVT_INT_0,pvt_int_0 from PVT_SNS_SAF" "0,1" bitfld.long 0x0 28. "PVT_SNS_SEC_PVT_INT_1,pvt_int_1 from PVT_SNS_SEC" "0,1" newline bitfld.long 0x0 27. "PVT_SNS_SEC_PVT_INT_0,pvt_int_0 from PVT_SNS_SEC" "0,1" bitfld.long 0x0 26. "WDT8_ILL_SEQ_REFR_INT,ill_seq_refr_int from WDT8" "0,1" bitfld.long 0x0 25. "WDT8_ILL_WIN_REFR_INT,ill_win_refr_int from WDT8" "0,1" newline bitfld.long 0x0 24. "WDT8_OVFLOW_INT,ovflow_int from WDT8" "0,1" bitfld.long 0x0 23. "WDT7_ILL_SEQ_REFR_INT,ill_seq_refr_int from WDT7" "0,1" bitfld.long 0x0 22. "WDT7_ILL_WIN_REFR_INT,ill_win_refr_int from WDT7" "0,1" newline bitfld.long 0x0 21. "WDT7_OVFLOW_INT,ovflow_int from WDT7" "0,1" bitfld.long 0x0 20. "WDT6_ILL_SEQ_REFR_INT,ill_seq_refr_int from WDT6" "0,1" bitfld.long 0x0 19. "WDT6_ILL_WIN_REFR_INT,ill_win_refr_int from WDT6" "0,1" newline bitfld.long 0x0 18. "WDT6_OVFLOW_INT,ovflow_int from WDT6" "0,1" bitfld.long 0x0 17. "WDT5_ILL_SEQ_REFR_INT,ill_seq_refr_int from WDT5" "0,1" bitfld.long 0x0 16. "WDT5_ILL_WIN_REFR_INT,ill_win_refr_int from WDT5" "0,1" newline bitfld.long 0x0 15. "WDT5_OVFLOW_INT,ovflow_int from WDT5" "0,1" bitfld.long 0x0 14. "WDT4_ILL_SEQ_REFR_INT,ill_seq_refr_int from WDT4" "0,1" bitfld.long 0x0 13. "WDT4_ILL_WIN_REFR_INT,ill_win_refr_int from WDT4" "0,1" newline bitfld.long 0x0 12. "WDT4_OVFLOW_INT,ovflow_int from WDT4" "0,1" bitfld.long 0x0 11. "WDT3_ILL_SEQ_REFR_INT,ill_seq_refr_int from WDT3" "0,1" bitfld.long 0x0 10. "WDT3_ILL_WIN_REFR_INT,ill_win_refr_int from WDT3" "0,1" newline bitfld.long 0x0 9. "WDT3_OVFLOW_INT,ovflow_int from WDT3" "0,1" bitfld.long 0x0 8. "WDT2_ILL_SEQ_REFR_INT,ill_seq_refr_int from WDT2" "0,1" bitfld.long 0x0 7. "WDT2_ILL_WIN_REFR_INT,ill_win_refr_int from WDT2" "0,1" newline bitfld.long 0x0 6. "WDT2_OVFLOW_INT,ovflow_int from WDT2" "0,1" bitfld.long 0x0 5. "WDT1_ILL_SEQ_REFR_INT,ill_seq_refr_int from WDT1" "0,1" bitfld.long 0x0 4. "WDT1_ILL_WIN_REFR_INT,ill_win_refr_int from WDT1" "0,1" newline bitfld.long 0x0 3. "WDT1_OVFLOW_INT,ovflow_int from WDT1" "0,1" bitfld.long 0x0 2. "PWR_LAT_RTC_AP_POWER_LAT,ap_power_lat from PWR_LAT_RTC AP domain power fail" "0,1" bitfld.long 0x0 1. "PWR_LAT_RTC_SAF_POWER_LAT,saf_power_lat from PWR_LAT_RTC SAF domain power fail" "0,1" newline bitfld.long 0x0 0. "PWR_LAT_SAF_SAF_POWER_LAT,saf_power_lat from PWR_LAT_SAF SAF power fail" "0,1" group.long 0x500++0x17 line.long 0x0 "TGT_VALUE_0,signal monitor target value" hexmask.long.tbyte 0x0 12.--31. 1. "EFUSE_MISC_CFG,[69:12] efusec_misc_cfg[31:12]" bitfld.long 0x0 11. "IRAM4_ECC_DISABLE_MON,[11:11] iram4_ecc_disable_mon" "0,1" bitfld.long 0x0 10. "IRAM3_ECC_DISABLE_MON,[10:10] iram3_ecc_disable_mon" "0,1" newline bitfld.long 0x0 9. "IRAM2_ECC_DISABLE_MON,[9:9] iram2_ecc_disable_mon" "0,1" hexmask.long.word 0x0 0.--8. 1. "EFUSEC_MISC_CFG,[8:0] efusec_misc_cfg[8:0]" line.long 0x4 "TGT_VALUE_1,signal monitor target value" hexmask.long 0x4 0.--31. 1. "EFUSE_MISC_CFG,[69:12] efusec_misc_cfg[63:32]" line.long 0x8 "TGT_VALUE_2,signal monitor target value" hexmask.long.byte 0x8 25.--31. 1. "EFUSEC_MISC_CFG,[95:89] efusec_misc_cfg[95:89]" bitfld.long 0x8 24. "I_SEM1_INT_PAD_MON,[88:88] i_sem1_int_pad_mon" "0,1" bitfld.long 0x8 23. "I_SEM1_INT_CPU_HPI_MON,[87:87] i_sem1_int_cpu_hpi_mon" "0,1" newline bitfld.long 0x8 22. "I_SEM1_INT_CPU_SEC_MON,[86:86] i_sem1_int_cpu_sec_mon" "0,1" bitfld.long 0x8 21. "SEM1_SEM_INT_CPU,[85:85] sem1_sem_int_cpu" "0,1" bitfld.long 0x8 20. "I_SEM1_INT_DC5_MON,[84:84] i_sem1_int_dc5_mon" "0,1" newline bitfld.long 0x8 19. "I_SEM1_INT_DC4_MON,[83:83] i_sem1_int_dc4_mon" "0,1" bitfld.long 0x8 18. "I_SEM1_INT_DC3_MON,[82:82] i_sem1_int_dc3_mon" "0,1" bitfld.long 0x8 17. "I_SEM1_INT_DC2_MON,[81:81] i_sem1_int_dc2_mon" "0,1" newline bitfld.long 0x8 16. "I_SEM1_INT_DC1_MON,[80:80] i_sem1_int_dc1_mon" "0,1" bitfld.long 0x8 15. "I_SEM1_INT_SYS_SEC_MON,[79:79] i_sem1_int_sys_sec_mon" "0,1" bitfld.long 0x8 14. "I_SEM1_INT_SYS_RTC_MON,[78:78] i_sem1_int_sys_rtc_mon" "0,1" newline bitfld.long 0x8 13. "SEM1_SEM_INT_SYS,[77:77] sem1_sem_int_sys" "0,1" bitfld.long 0x8 12. "USER_MAC_DIS_HPI_MON,[76:76] user_mac_dis_hpi_mon" "0,1" bitfld.long 0x8 11. "USER_MAC_DIS_SEC_MON,[75:75] user_mac_dis_sec_mon" "0,1" newline bitfld.long 0x8 10. "PROD_ENABLE_MON,[74:74] prod_enable_mon" "0,1" bitfld.long 0x8 9. "GPU2_ASTC_DISABLE_MON,[73:73] gpu2_astc_disable_mon" "0,1" bitfld.long 0x8 8. "GPU1_ASTC_DISABLE_MON,[72:72] gpu1_astc_disable_mon" "0,1" newline bitfld.long 0x8 7. "APBMUX2_GPV_HPIB_SELECT,[71:71] apbmux2_gpv_hpib_select" "0,1" bitfld.long 0x8 6. "FUSE_SAF_DISABLE,[70:70] fuse_saf_disable" "0,1" hexmask.long.byte 0x8 0.--5. 1. "EFUSE_MISC_CFG,[69:12] efusec_misc_cfg[69:64]" line.long 0xC "TGT_VALUE_3,signal monitor target value" bitfld.long 0xC 30.--31. "EFUSEC_MISC_CFG,[127:126] efusec_misc_cfg[127:126]" "0,1,2,3" bitfld.long 0xC 29. "ALL_DBG_DISABLE_MON,[125:125] all_dbg_disable_mon" "0,1" hexmask.long.byte 0xC 23.--28. 1. "EFUSEC_MISC_CFG,[124:119] efusec_misc_cfg[124:119]" newline bitfld.long 0xC 22. "SEC_SAFETY_DISABLE_MON,[118:118] sec_safety_disable_mon" "0,1" bitfld.long 0xC 20.--21. "EFUSEC_MISC_CFG,[117:116] efusec_misc_cfg[117:116]" "0,1,2,3" bitfld.long 0xC 19. "GPU2_DBG_DISABLE_MON,[115:115] gpu2_dbg_disable_mon" "0,1" newline bitfld.long 0xC 18. "GPU1_DBG_DISABLE_MON,[114:114] gpu1_dbg_disable_mon" "0,1" bitfld.long 0xC 17. "ADSP_DBG_DISABLE_MON,[113:113] adsp_dbg_disable_mon" "0,1" bitfld.long 0xC 16. "VDSP_DBG_DISABLE_MON,[112:112] vdsp_dbg_disable_mon" "0,1" newline bitfld.long 0xC 15. "PARA_BOOT_DISABLE_MON,[111:111] para_boot_disable_mon" "0,1" bitfld.long 0xC 14. "EFUSEC_MISC_CFG,[110:110] efusec_misc_cfg[110]" "0,1" bitfld.long 0xC 13. "USER_MAC_DISABLE_MON,[109:109] user_mac_disable_mon" "0,1" newline bitfld.long 0xC 10.--12. "EFUSEC_MISC_CFG,[108:106] efusec_misc_cfg[108:106]" "0,1,2,3,4,5,6,7" bitfld.long 0xC 9. "PVT_SEC_SENS_EN_MON,[105:105] pvt_sec_sens_en_mon" "0,1" hexmask.long.word 0xC 0.--8. 1. "EFUSEC_MISC_CFG,[104:96] efusec_misc_cfg[104:96]" line.long 0x10 "TGT_VALUE_4,signal monitor target value" bitfld.long 0x10 31. "APBMUX2_BIPC_ENET1_SELECT,[159:159] apbmux2_bipc_enet1_select" "0,1" bitfld.long 0x10 30. "APBMUX2_PVT_SNS_SAF_SELECT,[158:158] apbmux2_pvt_sns_saf_select" "0,1" bitfld.long 0x10 29. "APBMUX2_PLL2_SELECT,[157:157] apbmux2_pll2_select" "0,1" newline bitfld.long 0x10 28. "APBMUX2_PLL1_SELECT,[156:156] apbmux2_pll1_select" "0,1" bitfld.long 0x10 27. "APBMUX2_RC_24M_SELECT,[155:155] apbmux2_rc_24m_select" "0,1" bitfld.long 0x10 26. "APBMUX2_DMA1_SELECT,[154:154] apbmux2_dma1_select" "0,1" newline bitfld.long 0x10 25. "APBMUX2_WDT1_SELECT,[153:153] apbmux2_wdt1_select" "0,1" bitfld.long 0x10 24. "APBMUX2_PWM2_SELECT,[152:152] apbmux2_pwm2_select" "0,1" bitfld.long 0x10 23. "APBMUX2_PWM1_SELECT,[151:151] apbmux2_pwm1_select" "0,1" newline bitfld.long 0x10 22. "APBMUX2_TIMER2_SELECT,[150:150] apbmux2_timer2_select" "0,1" bitfld.long 0x10 21. "APBMUX2_TIMER1_SELECT,[149:149] apbmux2_timer1_select" "0,1" bitfld.long 0x10 20. "APBMUX2_ENET1_SELECT,[148:148] apbmux2_enet1_select" "0,1" newline bitfld.long 0x10 19. "APBMUX2_UART8_SELECT,[147:147] apbmux2_uart8_select" "0,1" bitfld.long 0x10 18. "APBMUX2_UART7_SELECT,[146:146] apbmux2_uart7_select" "0,1" bitfld.long 0x10 17. "APBMUX2_UART6_SELECT,[145:145] apbmux2_uart6_select" "0,1" newline bitfld.long 0x10 16. "APBMUX2_UART5_SELECT,[144:144] apbmux2_uart5_select" "0,1" bitfld.long 0x10 15. "APBMUX2_UART4_SELECT,[143:143] apbmux2_uart4_select" "0,1" bitfld.long 0x10 14. "APBMUX2_UART3_SELECT,[142:142] apbmux2_uart3_select" "0,1" newline bitfld.long 0x10 13. "APBMUX2_UART2_SELECT,[141:141] apbmux2_uart2_select" "0,1" bitfld.long 0x10 12. "APBMUX2_UART1_SELECT,[140:140] apbmux2_uart1_select" "0,1" bitfld.long 0x10 11. "APBMUX2_I2C4_SELECT,[139:139] apbmux2_i2c4_select" "0,1" newline bitfld.long 0x10 10. "APBMUX2_I2C3_SELECT,[138:138] apbmux2_i2c3_select" "0,1" bitfld.long 0x10 9. "APBMUX2_I2C2_SELECT,[137:137] apbmux2_i2c2_select" "0,1" bitfld.long 0x10 8. "APBMUX2_I2C1_SELECT,[136:136] apbmux2_i2c1_select" "0,1" newline bitfld.long 0x10 7. "APBMUX2_CANFD4_SELECT,[135:135] apbmux2_canfd4_select" "0,1" bitfld.long 0x10 6. "APBMUX2_CANFD3_SELECT,[134:134] apbmux2_canfd3_select" "0,1" bitfld.long 0x10 5. "APBMUX2_CANFD2_SELECT,[133:133] apbmux2_canfd2_select" "0,1" newline bitfld.long 0x10 4. "APBMUX2_CANFD1_SELECT,[132:132] apbmux2_canfd1_select" "0,1" bitfld.long 0x10 3. "APBMUX2_OSPI1_SELECT,[131:131] apbmux2_ospi1_select" "0,1" bitfld.long 0x10 2. "APBMUX2_PWRCTRL_SELECT,[130:130] apbmux2_pwrctrl_select" "0,1" newline bitfld.long 0x10 1. "APBMUX2_CE1_SELECT,[129:129] apbmux2_ce1_select" "0,1" bitfld.long 0x10 0. "APBMUX2_SEM1_SELECT,[128:128] apbmux2_sem1_select" "0,1" line.long 0x14 "TGT_VALUE_5,signal monitor target value" bitfld.long 0x14 23. "APBMUX2_SEC_STORAGE2_SELECT,[183:183] apbmux2_sec_storage2_select" "0,1" bitfld.long 0x14 22. "APBMUX2_SEC_STORAGE1_SELECT,[182:182] apbmux2_sec_storage1_select" "0,1" bitfld.long 0x14 21. "APBMUX2_RSTGEN_RTC_SELECT,[181:181] apbmux2_rstgen_rtc_select" "0,1" newline bitfld.long 0x14 20. "APBMUX2_PMU_SELECT,[180:180] apbmux2_pmu_select" "0,1" bitfld.long 0x14 19. "APBMUX2_RTC2_SELECT,[179:179] apbmux2_rtc2_select" "0,1" bitfld.long 0x14 18. "APBMUX2_RTC1_SELECT,[178:178] apbmux2_rtc1_select" "0,1" newline bitfld.long 0x14 17. "APBMUX2_XTAL_RTC_SELECT,[177:177] apbmux2_xtal_rtc_select" "0,1" bitfld.long 0x14 16. "APBMUX2_IOMUX_CTRL_RTC_SELECT,[176:176] apbmux2_iomux_ctrl_rtc_select" "0,1" bitfld.long 0x14 15. "APBMUX2_RC_RTC_SELECT,[175:175] apbmux2_rc_rtc_select" "0,1" newline bitfld.long 0x14 14. "APBMUX2_TM_SELECT,[174:174] apbmux2_tm_select" "0,1" bitfld.long 0x14 13. "AXISLVMUX_CE1_SELECT,[173:173] axislvmux_ce1_select" "0,1" bitfld.long 0x14 12. "AXISLVMUX_DMA1_SELECT,[172:172] axislvmux_dma1_select" "0,1" newline bitfld.long 0x14 11. "AXISLVMUX_OSPI1_SELECT,[171:171] axislvmux_ospi1_select" "0,1" bitfld.long 0x14 10. "AXISLVMUX_IRAM1_SELECT,[170:170] axislvmux_iram1_select" "0,1" bitfld.long 0x14 9. "APBMUX2_EIC_SAFE_SELECT,[169:169] apbmux2_eic_safe_select" "0,1" newline bitfld.long 0x14 8. "APBMUX2_XTAL_SAF_SELECT,[168:168] apbmux2_xtal_saf_select" "0,1" bitfld.long 0x14 7. "APBMUX2_RPC_SAF_SELECT,[167:167] apbmux2_rpc_saf_select" "0,1" bitfld.long 0x14 6. "APBMUX2_SPI4_SELECT,[166:166] apbmux2_spi4_select" "0,1" newline bitfld.long 0x14 5. "APBMUX2_SPI3_SELECT,[165:165] apbmux2_spi3_select" "0,1" bitfld.long 0x14 4. "APBMUX2_SPI2_SELECT,[164:164] apbmux2_spi2_select" "0,1" bitfld.long 0x14 3. "APBMUX2_SPI1_SELECT,[163:163] apbmux2_spi1_select" "0,1" newline bitfld.long 0x14 2. "APBMUX2_IRAM1_SELECT,[162:162] apbmux2_iram1_select" "0,1" bitfld.long 0x14 1. "APBMUX2_I2S_SC2_SELECT,[161:161] apbmux2_i2s_sc2_select" "0,1" bitfld.long 0x14 0. "APBMUX2_I2S_SC1_SELECT,[160:160] apbmux2_i2s_sc1_select" "0,1" group.long 0x580++0x17 line.long 0x0 "SIG_MON_ENABLE_0,signal monitor enable" hexmask.long.tbyte 0x0 12.--31. 1. "EFUSE_MISC_CFG,[69:12] efusec_misc_cfg[31:12]" bitfld.long 0x0 11. "IRAM4_ECC_DISABLE_MON,[11:11] iram4_ecc_disable_mon" "0,1" bitfld.long 0x0 10. "IRAM3_ECC_DISABLE_MON,[10:10] iram3_ecc_disable_mon" "0,1" newline bitfld.long 0x0 9. "IRAM2_ECC_DISABLE_MON,[9:9] iram2_ecc_disable_mon" "0,1" hexmask.long.word 0x0 0.--8. 1. "EFUSEC_MISC_CFG,[8:0] efusec_misc_cfg[8:0]" line.long 0x4 "SIG_MON_ENABLE_1,signal monitor enable" hexmask.long 0x4 0.--31. 1. "EFUSE_MISC_CFG,[69:12] efusec_misc_cfg[63:32]" line.long 0x8 "SIG_MON_ENABLE_2,signal monitor enable" hexmask.long.byte 0x8 25.--31. 1. "EFUSEC_MISC_CFG,[95:89] efusec_misc_cfg[95:89]" bitfld.long 0x8 24. "I_SEM1_INT_PAD_MON,[88:88] i_sem1_int_pad_mon" "0,1" bitfld.long 0x8 23. "I_SEM1_INT_CPU_HPI_MON,[87:87] i_sem1_int_cpu_hpi_mon" "0,1" newline bitfld.long 0x8 22. "I_SEM1_INT_CPU_SEC_MON,[86:86] i_sem1_int_cpu_sec_mon" "0,1" bitfld.long 0x8 21. "SEM1_SEM_INT_CPU,[85:85] sem1_sem_int_cpu" "0,1" bitfld.long 0x8 20. "I_SEM1_INT_DC5_MON,[84:84] i_sem1_int_dc5_mon" "0,1" newline bitfld.long 0x8 19. "I_SEM1_INT_DC4_MON,[83:83] i_sem1_int_dc4_mon" "0,1" bitfld.long 0x8 18. "I_SEM1_INT_DC3_MON,[82:82] i_sem1_int_dc3_mon" "0,1" bitfld.long 0x8 17. "I_SEM1_INT_DC2_MON,[81:81] i_sem1_int_dc2_mon" "0,1" newline bitfld.long 0x8 16. "I_SEM1_INT_DC1_MON,[80:80] i_sem1_int_dc1_mon" "0,1" bitfld.long 0x8 15. "I_SEM1_INT_SYS_SEC_MON,[79:79] i_sem1_int_sys_sec_mon" "0,1" bitfld.long 0x8 14. "I_SEM1_INT_SYS_RTC_MON,[78:78] i_sem1_int_sys_rtc_mon" "0,1" newline bitfld.long 0x8 13. "SEM1_SEM_INT_SYS,[77:77] sem1_sem_int_sys" "0,1" bitfld.long 0x8 12. "USER_MAC_DIS_HPI_MON,[76:76] user_mac_dis_hpi_mon" "0,1" bitfld.long 0x8 11. "USER_MAC_DIS_SEC_MON,[75:75] user_mac_dis_sec_mon" "0,1" newline bitfld.long 0x8 10. "PROD_ENABLE_MON,[74:74] prod_enable_mon" "0,1" bitfld.long 0x8 9. "GPU2_ASTC_DISABLE_MON,[73:73] gpu2_astc_disable_mon" "0,1" bitfld.long 0x8 8. "GPU1_ASTC_DISABLE_MON,[72:72] gpu1_astc_disable_mon" "0,1" newline bitfld.long 0x8 7. "APBMUX2_GPV_HPIB_SELECT,[71:71] apbmux2_gpv_hpib_select" "0,1" bitfld.long 0x8 6. "FUSE_SAF_DISABLE,[70:70] fuse_saf_disable" "0,1" hexmask.long.byte 0x8 0.--5. 1. "EFUSE_MISC_CFG,[69:12] efusec_misc_cfg[69:64]" line.long 0xC "SIG_MON_ENABLE_3,signal monitor enable" bitfld.long 0xC 30.--31. "EFUSEC_MISC_CFG,[127:126] efusec_misc_cfg[127:126]" "0,1,2,3" bitfld.long 0xC 29. "ALL_DBG_DISABLE_MON,[125:125] all_dbg_disable_mon" "0,1" hexmask.long.byte 0xC 23.--28. 1. "EFUSEC_MISC_CFG,[124:119] efusec_misc_cfg[124:119]" newline bitfld.long 0xC 22. "SEC_SAFETY_DISABLE_MON,[118:118] sec_safety_disable_mon" "0,1" bitfld.long 0xC 20.--21. "EFUSEC_MISC_CFG,[117:116] efusec_misc_cfg[117:116]" "0,1,2,3" bitfld.long 0xC 19. "GPU2_DBG_DISABLE_MON,[115:115] gpu2_dbg_disable_mon" "0,1" newline bitfld.long 0xC 18. "GPU1_DBG_DISABLE_MON,[114:114] gpu1_dbg_disable_mon" "0,1" bitfld.long 0xC 17. "ADSP_DBG_DISABLE_MON,[113:113] adsp_dbg_disable_mon" "0,1" bitfld.long 0xC 16. "VDSP_DBG_DISABLE_MON,[112:112] vdsp_dbg_disable_mon" "0,1" newline bitfld.long 0xC 15. "PARA_BOOT_DISABLE_MON,[111:111] para_boot_disable_mon" "0,1" bitfld.long 0xC 14. "EFUSEC_MISC_CFG,[110:110] efusec_misc_cfg[110]" "0,1" bitfld.long 0xC 13. "USER_MAC_DISABLE_MON,[109:109] user_mac_disable_mon" "0,1" newline bitfld.long 0xC 10.--12. "EFUSEC_MISC_CFG,[108:106] efusec_misc_cfg[108:106]" "0,1,2,3,4,5,6,7" bitfld.long 0xC 9. "PVT_SEC_SENS_EN_MON,[105:105] pvt_sec_sens_en_mon" "0,1" hexmask.long.word 0xC 0.--8. 1. "EFUSEC_MISC_CFG,[104:96] efusec_misc_cfg[104:96]" line.long 0x10 "SIG_MON_ENABLE_4,signal monitor enable" bitfld.long 0x10 31. "APBMUX2_BIPC_ENET1_SELECT,[159:159] apbmux2_bipc_enet1_select" "0,1" bitfld.long 0x10 30. "APBMUX2_PVT_SNS_SAF_SELECT,[158:158] apbmux2_pvt_sns_saf_select" "0,1" bitfld.long 0x10 29. "APBMUX2_PLL2_SELECT,[157:157] apbmux2_pll2_select" "0,1" newline bitfld.long 0x10 28. "APBMUX2_PLL1_SELECT,[156:156] apbmux2_pll1_select" "0,1" bitfld.long 0x10 27. "APBMUX2_RC_24M_SELECT,[155:155] apbmux2_rc_24m_select" "0,1" bitfld.long 0x10 26. "APBMUX2_DMA1_SELECT,[154:154] apbmux2_dma1_select" "0,1" newline bitfld.long 0x10 25. "APBMUX2_WDT1_SELECT,[153:153] apbmux2_wdt1_select" "0,1" bitfld.long 0x10 24. "APBMUX2_PWM2_SELECT,[152:152] apbmux2_pwm2_select" "0,1" bitfld.long 0x10 23. "APBMUX2_PWM1_SELECT,[151:151] apbmux2_pwm1_select" "0,1" newline bitfld.long 0x10 22. "APBMUX2_TIMER2_SELECT,[150:150] apbmux2_timer2_select" "0,1" bitfld.long 0x10 21. "APBMUX2_TIMER1_SELECT,[149:149] apbmux2_timer1_select" "0,1" bitfld.long 0x10 20. "APBMUX2_ENET1_SELECT,[148:148] apbmux2_enet1_select" "0,1" newline bitfld.long 0x10 19. "APBMUX2_UART8_SELECT,[147:147] apbmux2_uart8_select" "0,1" bitfld.long 0x10 18. "APBMUX2_UART7_SELECT,[146:146] apbmux2_uart7_select" "0,1" bitfld.long 0x10 17. "APBMUX2_UART6_SELECT,[145:145] apbmux2_uart6_select" "0,1" newline bitfld.long 0x10 16. "APBMUX2_UART5_SELECT,[144:144] apbmux2_uart5_select" "0,1" bitfld.long 0x10 15. "APBMUX2_UART4_SELECT,[143:143] apbmux2_uart4_select" "0,1" bitfld.long 0x10 14. "APBMUX2_UART3_SELECT,[142:142] apbmux2_uart3_select" "0,1" newline bitfld.long 0x10 13. "APBMUX2_UART2_SELECT,[141:141] apbmux2_uart2_select" "0,1" bitfld.long 0x10 12. "APBMUX2_UART1_SELECT,[140:140] apbmux2_uart1_select" "0,1" bitfld.long 0x10 11. "APBMUX2_I2C4_SELECT,[139:139] apbmux2_i2c4_select" "0,1" newline bitfld.long 0x10 10. "APBMUX2_I2C3_SELECT,[138:138] apbmux2_i2c3_select" "0,1" bitfld.long 0x10 9. "APBMUX2_I2C2_SELECT,[137:137] apbmux2_i2c2_select" "0,1" bitfld.long 0x10 8. "APBMUX2_I2C1_SELECT,[136:136] apbmux2_i2c1_select" "0,1" newline bitfld.long 0x10 7. "APBMUX2_CANFD4_SELECT,[135:135] apbmux2_canfd4_select" "0,1" bitfld.long 0x10 6. "APBMUX2_CANFD3_SELECT,[134:134] apbmux2_canfd3_select" "0,1" bitfld.long 0x10 5. "APBMUX2_CANFD2_SELECT,[133:133] apbmux2_canfd2_select" "0,1" newline bitfld.long 0x10 4. "APBMUX2_CANFD1_SELECT,[132:132] apbmux2_canfd1_select" "0,1" bitfld.long 0x10 3. "APBMUX2_OSPI1_SELECT,[131:131] apbmux2_ospi1_select" "0,1" bitfld.long 0x10 2. "APBMUX2_PWRCTRL_SELECT,[130:130] apbmux2_pwrctrl_select" "0,1" newline bitfld.long 0x10 1. "APBMUX2_CE1_SELECT,[129:129] apbmux2_ce1_select" "0,1" bitfld.long 0x10 0. "APBMUX2_SEM1_SELECT,[128:128] apbmux2_sem1_select" "0,1" line.long 0x14 "SIG_MON_ENABLE_5,signal monitor enable" bitfld.long 0x14 23. "APBMUX2_SEC_STORAGE2_SELECT,[183:183] apbmux2_sec_storage2_select" "0,1" bitfld.long 0x14 22. "APBMUX2_SEC_STORAGE1_SELECT,[182:182] apbmux2_sec_storage1_select" "0,1" bitfld.long 0x14 21. "APBMUX2_RSTGEN_RTC_SELECT,[181:181] apbmux2_rstgen_rtc_select" "0,1" newline bitfld.long 0x14 20. "APBMUX2_PMU_SELECT,[180:180] apbmux2_pmu_select" "0,1" bitfld.long 0x14 19. "APBMUX2_RTC2_SELECT,[179:179] apbmux2_rtc2_select" "0,1" bitfld.long 0x14 18. "APBMUX2_RTC1_SELECT,[178:178] apbmux2_rtc1_select" "0,1" newline bitfld.long 0x14 17. "APBMUX2_XTAL_RTC_SELECT,[177:177] apbmux2_xtal_rtc_select" "0,1" bitfld.long 0x14 16. "APBMUX2_IOMUX_CTRL_RTC_SELECT,[176:176] apbmux2_iomux_ctrl_rtc_select" "0,1" bitfld.long 0x14 15. "APBMUX2_RC_RTC_SELECT,[175:175] apbmux2_rc_rtc_select" "0,1" newline bitfld.long 0x14 14. "APBMUX2_TM_SELECT,[174:174] apbmux2_tm_select" "0,1" bitfld.long 0x14 13. "AXISLVMUX_CE1_SELECT,[173:173] axislvmux_ce1_select" "0,1" bitfld.long 0x14 12. "AXISLVMUX_DMA1_SELECT,[172:172] axislvmux_dma1_select" "0,1" newline bitfld.long 0x14 11. "AXISLVMUX_OSPI1_SELECT,[171:171] axislvmux_ospi1_select" "0,1" bitfld.long 0x14 10. "AXISLVMUX_IRAM1_SELECT,[170:170] axislvmux_iram1_select" "0,1" bitfld.long 0x14 9. "APBMUX2_EIC_SAFE_SELECT,[169:169] apbmux2_eic_safe_select" "0,1" newline bitfld.long 0x14 8. "APBMUX2_XTAL_SAF_SELECT,[168:168] apbmux2_xtal_saf_select" "0,1" bitfld.long 0x14 7. "APBMUX2_RPC_SAF_SELECT,[167:167] apbmux2_rpc_saf_select" "0,1" bitfld.long 0x14 6. "APBMUX2_SPI4_SELECT,[166:166] apbmux2_spi4_select" "0,1" newline bitfld.long 0x14 5. "APBMUX2_SPI3_SELECT,[165:165] apbmux2_spi3_select" "0,1" bitfld.long 0x14 4. "APBMUX2_SPI2_SELECT,[164:164] apbmux2_spi2_select" "0,1" bitfld.long 0x14 3. "APBMUX2_SPI1_SELECT,[163:163] apbmux2_spi1_select" "0,1" newline bitfld.long 0x14 2. "APBMUX2_IRAM1_SELECT,[162:162] apbmux2_iram1_select" "0,1" bitfld.long 0x14 1. "APBMUX2_I2S_SC2_SELECT,[161:161] apbmux2_i2s_sc2_select" "0,1" bitfld.long 0x14 0. "APBMUX2_I2S_SC1_SELECT,[160:160] apbmux2_i2s_sc1_select" "0,1" tree.end tree.end repeat.end endif tree.end tree "SPDIF (Sony/Philips Digital Interface)" sif (CORENAME()=="CORTEXR5F") repeat 4. (increment 1. 1.) (list ad:0xF0580000 ad:0xF0590000 ad:0xF05A0000 ad:0xF05B0000) tree "SPDIF$1" base $2 group.long 0x0++0xB line.long 0x0 "SPDIF_CTRL,'SPDIF control register'" bitfld.long 0x0 31. "INTREQ_MASK,Bit masking all interrupt requests. When'0'allinterruptsare masked when '1' interrupts use individual masks. Sampled on the rising clock edge." "0,1" bitfld.long 0x0 30. "BEGIN_MASK,Bit masking interrupt generation after receiving block begin preamble. When '1' interrupt request generation is enabled otherwise it is disabled. Sampled on the rising clock edge." "0,1" bitfld.long 0x0 29. "LOCK_MASK,Bit masking interrupt generation after receiver becomes synchronized with input data stream (i.e. it is in lock condition). When '1' interrupt request generation is enabled otherwise it is disabled. Sampled on the rising clock edge." "0,1" bitfld.long 0x0 28. "SYNCERR_MASK,Bit masking interrupt generation after synchronization error occurrence. When '1' interrupt request generation is enabled otherwise it is disabled. Sampled on the rising clock edge." "0,1" bitfld.long 0x0 27. "AFULL_MASK,Bit masking interrupt request generation after FIFO becomes almost full. When '1' interrupt request generation is enabled otherwise it is disabled. Sampled on the rising clock edge." "0,1" bitfld.long 0x0 26. "FULL_MASK,Bit masking interrupt request generation after FIFO becomes full. When '1' interrupt request generation is enabled otherwise it is disabled. Sampled on the rising clock edge." "0,1" newline bitfld.long 0x0 25. "AEMPTY_MASK,Bit masking interrupt request generation after FIFO becomes almost empty. When '1' interrupt request generation is enabled otherwise it is disabled. Sampled on the rising clock edge." "0,1" bitfld.long 0x0 24. "EMPTY_MASK,Bit masking interrupt request generation after FIFO becomes empty. When '1' interrupt request generation is enabled otherwise it is disabled. Sampled on the rising clock edge." "0,1" bitfld.long 0x0 23. "OVRERR_MASK,Bit masking interrupt request generation after overrun error occurrence. When '1' interrupt request generation is enabled otherwise it is disabled. Sampled on the rising clock edge." "0,1" bitfld.long 0x0 22. "UNDERR_MASK,Bit masking interrupt request generation after underrun error occurrence. When '1' interrupt request generation is enabled otherwise it is disabled. Sampled on the rising clock edge." "0,1" bitfld.long 0x0 21. "PARITY_MASK,Bit masking interrupt request generation after parityo occurred '1' (parityo state is depended on the paritycheck bit). When '1' interrupt request generation is enabled otherwise it is disabled. Sampled on the rising clock edge." "0,1" rbitfld.long 0x0 20. "RESERVED,unused" "0,1" newline bitfld.long 0x0 19. "USE_FIFO_IF,Use direct FIFO interface: 0 - direct FIFO interface is disabled and APB access to the FIFO is enabled. 1 - direct FIFO interface is enabled and APB access to the FIFO is disabled." "0,1" bitfld.long 0x0 18. "SETPREAMBB,This bit is valid only when working as transmitter. When '0' first preamble B after reset is transmitted with first valid sub-frame. When '1' first preamble B is transmitted after preambledel (in the INT_REG register) frames regardless of.." "0,1" bitfld.long 0x0 17. "DUPLICATE,This bit is valid only when working as transmitter in single-channel mode. When this bit is '1' data carried in the left (primary) channel are duplicated in the right (secondary) channel. When this bit is '0' data carried in the secondary.." "0,1" bitfld.long 0x0 16. "CHANNEL_MODE,When '1' the single-channel (monophonic) mode is forced.While working as receiver only subframes from left (primary) channel are written into FIFO. Data from right channel are discarded. And while working as transmitter data from FIFO are.." "0,1" bitfld.long 0x0 15. "VALIDITYCHECK,When '1' the validity bit in received frame is checked if it's low the frame is written else the frame is discarded. When validitycheck is '0' the validity bit in frame isn't checked and all frames are written. Sampled on the rising.." "0,1" bitfld.long 0x0 14. "PARITYGEN,When '1' a parity bit is generated inside the core and added to a transmitted sub-frame. When '0' the value from the parity bit from FIFO is transmitted in sub-frame. Sampled on the rising clock edge." "0,1" newline bitfld.long 0x0 13. "PARITYCHECK,When '1' - check on a parity error in received subframe the parityo is asserted when a parity error has been detected. When '0' - parity bit received in a sub-frame is repeated on the parityo. Sampled on the rising clock edge." "0,1" bitfld.long 0x0 12. "TR_MODE,Direction control (transmitter - '1' / receiver -'0'). Sampled on the rising clock edge" "0,1" bitfld.long 0x0 11. "CLK_ENABLE,Clock enable for the SPDIF core and FIFO. When '1' the clock is blocked and the modules are in power save mode. When '0' the clock feeds the modules. Sampled on the rising clock edge." "0,1" bitfld.long 0x0 10. "FIFO_ENABLE,FIFO enable. When '0' FIFO pointers are reset to zero. Threshold levels for FIFO are unchanged. This bit is automatically set back to '1' after the reset is propagated to the clk_spdif clock domain and back. It takes few clock cycles depends.." "0,1" bitfld.long 0x0 9. "SPDIF_ENABLE,SPDIF core enable. Value '0' causes reset of SPDIF block configuration SFR bits are unchanged. Value '1' enables SPDIF module. Sampled on the rising clock edge." "0,1" bitfld.long 0x0 8. "SFR_ENABLE,Bit controlling SFR block synchronous reset. When '0' all bits in SFR registers are reset to default values. It causes reset of all modules. This bit is automatically set back to '1' after the reset is propagated to the clk_spdif clock domain.." "0,1" newline hexmask.long.byte 0x0 0.--7. 1. "TSAMPLERATE,Transmission sample rate. Determines sample rate for transmission signal. Sampled on the rising clock edge." line.long 0x4 "INT_REG,'Interrupt register'" rbitfld.long 0x4 31. "RESERVED,Unused" "0,1" bitfld.long 0x4 30. "BLOCK_BEGIN,When '1' it indicates start of a new block in received data. It is set to '1' when sub-frame with preamble 'B' has been received and written into FIFO. Once it is set to '1' it holds its value until writing '0'. Updated on the rising clock.." "0,1" bitfld.long 0x4 29. "LOCK,When '1' it indicates that receiver has become synchronized with input data stream (i.e. it is in lock condition). Once it is set to '1' it holds its value until writing '0'. Updated on the rising clock edge." "0,1" bitfld.long 0x4 28. "SYNCERR,When '1' it indicates receiver synchronization error. It is a source of an interrupt request. Once it is set to '1' it holds its value until writing '0' even when synchronization error condition disappears. Updated on the rising clock edge." "0,1" bitfld.long 0x4 27. "FIFO_AFULL,FIFO almost full flag. When the FIFO is almost full this bit is set to '1'. It is a source of an interrupt request. Once it is set to '1' it holds its value until writing '0' even when FIFO almost full condition disappears. Updated on the.." "0,1" bitfld.long 0x4 26. "FIFO_FULL,FIFO full flag. When the FIFO is full this bit is set to '1'. It is a source of an interrupt request. Once it is set to '1' it holds its value until writing '0' even when FIFO full condition disappears. Updated on the rising clock edge." "0,1" newline bitfld.long 0x4 25. "FIFO_AEMPTY,FIFO almost empty flag. When the FIFO is almost empty this bit is set to '1'. It is a source of an interrupt request. Once it is set to '1' it holds its value until writing '0' even when FIFO almost empty condition disappears. Updated on the.." "0,1" bitfld.long 0x4 24. "FIFO_EMPTY,FIFO empty flag. When the FIFO is empty this bit is set to '1'. It is a source of an interrupt request. Once it is set to '1' it holds its value until writing '0' even when FIFO empty condition disappears. Updated on the rising clock edge." "0,1" bitfld.long 0x4 23. "RDATA_OVRERR,Receiver data overrun error. When the error condition occurred this bit is set to '1'. It is a source of an interrupt request. It is cleared only by writing '0' to this bit clearing this bit also resets the FIFO pointers. Configuration.." "0,1" bitfld.long 0x4 22. "TDATA_UNDERR,Transmitter data underrun error. When the error condition occurred this bit is set to '1'. It is a source of an interrupt request. It is cleared only by writing '0' to this bit. Configuration registers contents are preserved as well." "0,1" bitfld.long 0x4 21. "PARITYO,Parity error. This bit is depended on parity_check bit. If the parity_check bit is '1' - this bit indicates a parity error in received sub-frame the parityo is asserted when a parity error has been detected. When parity_check is '0' - parity bit.." "0,1" newline hexmask.long.byte 0x4 8.--11. 1. "PREAMBLEDEL,First 'preamble B' delay. This field is valid only when working as transmitter and setpreambb bit in SPDIF_CTRL register is set. When the setpreambb is not active the preambledel fied has to be filled with zeros. It is number of frames needed.." hexmask.long.byte 0x4 0.--7. 1. "RSAMPLERATE,Receive sample rate. Indicates sample rate of data block that has been just received. Updated on the rising clock edge." line.long 0x8 "FIFO_CTRL,'FIFO control register'" hexmask.long.byte 0x8 16.--21. 1. "AFULL_THRESHOLD,Determines threshold for almost full flag in the FIFO. Sampled on the rising clock edge." hexmask.long.byte 0x8 0.--5. 1. "AEMPTY_THRESHOLD,Determines threshold for almost empty flag in the FIFO. When this field equals to all 0s the FIFO almost empty flag is not generated. Sampled on the rising clock edge." rgroup.long 0xC++0x3 line.long 0x0 "STAT_REG,'FIFO status register'" bitfld.long 0x0 31. "RIGHT_LEFT,A HIGH ('1') value indicates that left channel sub-frame has been received and written into FIFO; while a LOW ('0') value indicates that right channel sub-frame has been received and written into FIFO. Updated on the rising clock edge." "0,1" bitfld.long 0x0 30. "BEGIN_FLAG,When '1' it indicates start of a new block in received data. It is set to '1' when sub-frame with preamble 'B' has been received and written into FIFO and it's cleared when next sub-frame has been received. Updated on the rising clock edge." "0,1" bitfld.long 0x0 29. "LOCK_FLAG,When '1' it indicates that receiver has become synchronized with input data stream (i.e. it is in lock condition) and when synchronization is lost it's cleared. Updated on the rising clock edge." "0,1" bitfld.long 0x0 28. "SYNCERR_FLAG,When '1' it indicates receiver synchronization error and when synchronization error condition disappears it's cleared. Updated on the rising clock edge." "0,1" bitfld.long 0x0 27. "AFULL_FLAG,FIFO almost full flag. When the FIFO is almost full this bit is set to '1' and when FIFO almost full condition disappears it's cleared. Updated on the rising clock edge." "0,1" bitfld.long 0x0 26. "FULL_FLAG,FIFO full flag. When the FIFO is full this bit is set to '1' and when FIFO full condition disappears it's cleared. Updated on the rising clock edge." "0,1" newline bitfld.long 0x0 25. "AEMPTY_FLAG,FIFO almost empty flag. When the FIFO is almost empty this bit is set to '1'and when FIFO almost empty condition disappears it's cleared. Updated on the rising clock edge." "0,1" bitfld.long 0x0 24. "EMPTY_FLAG,FIFO empty flag. When the FIFO is empty this bit is set to '1' and when the FIFO isn't empty it's cleared. Updated on the rising clock edge." "0,1" bitfld.long 0x0 23. "OVRERR_FLAG,Receiver data overrun error. When the error condition occurred this bit is set to '1' and when the error condition disappears it's cleared. Updated on the rising clock edge." "0,1" bitfld.long 0x0 22. "UNDERR_FLAG,Transmitter data underrun flag. When the error condition occurred this bit is set to '1' and when the error condition disappears it is cleared. Updated on the rising clock edge." "0,1" bitfld.long 0x0 21. "PARITY_FLAG,Parity flag. This bit is depended on parity_check bit. If the parity_check bit is '1' - this bit indicates a parity error in received sub-frame the parityo is asserted when a parity error has been detected and it is cleared when a sub-frame.." "0,1" hexmask.long.word 0x0 7.--20. 1. "RESERVED,unused" newline hexmask.long.byte 0x0 0.--6. 1. "FIFO_LEVEL,Indicates transmit/receive FIFO level. Updated on the rising clock edge." tree.end repeat.end elif (CORENAME()=="CORTEXA55") repeat 4. (increment 1. 1.) (list ad:0x30580000 ad:0x30590000 ad:0x305A0000 ad:0x305B0000) tree "SPDIF$1" base $2 group.long 0x0++0xB line.long 0x0 "SPDIF_CTRL,'SPDIF control register'" bitfld.long 0x0 31. "INTREQ_MASK,Bit masking all interrupt requests. When'0'allinterruptsare masked when '1' interrupts use individual masks. Sampled on the rising clock edge." "0,1" bitfld.long 0x0 30. "BEGIN_MASK,Bit masking interrupt generation after receiving block begin preamble. When '1' interrupt request generation is enabled otherwise it is disabled. Sampled on the rising clock edge." "0,1" bitfld.long 0x0 29. "LOCK_MASK,Bit masking interrupt generation after receiver becomes synchronized with input data stream (i.e. it is in lock condition). When '1' interrupt request generation is enabled otherwise it is disabled. Sampled on the rising clock edge." "0,1" bitfld.long 0x0 28. "SYNCERR_MASK,Bit masking interrupt generation after synchronization error occurrence. When '1' interrupt request generation is enabled otherwise it is disabled. Sampled on the rising clock edge." "0,1" bitfld.long 0x0 27. "AFULL_MASK,Bit masking interrupt request generation after FIFO becomes almost full. When '1' interrupt request generation is enabled otherwise it is disabled. Sampled on the rising clock edge." "0,1" bitfld.long 0x0 26. "FULL_MASK,Bit masking interrupt request generation after FIFO becomes full. When '1' interrupt request generation is enabled otherwise it is disabled. Sampled on the rising clock edge." "0,1" newline bitfld.long 0x0 25. "AEMPTY_MASK,Bit masking interrupt request generation after FIFO becomes almost empty. When '1' interrupt request generation is enabled otherwise it is disabled. Sampled on the rising clock edge." "0,1" bitfld.long 0x0 24. "EMPTY_MASK,Bit masking interrupt request generation after FIFO becomes empty. When '1' interrupt request generation is enabled otherwise it is disabled. Sampled on the rising clock edge." "0,1" bitfld.long 0x0 23. "OVRERR_MASK,Bit masking interrupt request generation after overrun error occurrence. When '1' interrupt request generation is enabled otherwise it is disabled. Sampled on the rising clock edge." "0,1" bitfld.long 0x0 22. "UNDERR_MASK,Bit masking interrupt request generation after underrun error occurrence. When '1' interrupt request generation is enabled otherwise it is disabled. Sampled on the rising clock edge." "0,1" bitfld.long 0x0 21. "PARITY_MASK,Bit masking interrupt request generation after parityo occurred '1' (parityo state is depended on the paritycheck bit). When '1' interrupt request generation is enabled otherwise it is disabled. Sampled on the rising clock edge." "0,1" rbitfld.long 0x0 20. "RESERVED,unused" "0,1" newline bitfld.long 0x0 19. "USE_FIFO_IF,Use direct FIFO interface: 0 - direct FIFO interface is disabled and APB access to the FIFO is enabled. 1 - direct FIFO interface is enabled and APB access to the FIFO is disabled." "0,1" bitfld.long 0x0 18. "SETPREAMBB,This bit is valid only when working as transmitter. When '0' first preamble B after reset is transmitted with first valid sub-frame. When '1' first preamble B is transmitted after preambledel (in the INT_REG register) frames regardless of.." "0,1" bitfld.long 0x0 17. "DUPLICATE,This bit is valid only when working as transmitter in single-channel mode. When this bit is '1' data carried in the left (primary) channel are duplicated in the right (secondary) channel. When this bit is '0' data carried in the secondary.." "0,1" bitfld.long 0x0 16. "CHANNEL_MODE,When '1' the single-channel (monophonic) mode is forced.While working as receiver only subframes from left (primary) channel are written into FIFO. Data from right channel are discarded. And while working as transmitter data from FIFO are.." "0,1" bitfld.long 0x0 15. "VALIDITYCHECK,When '1' the validity bit in received frame is checked if it's low the frame is written else the frame is discarded. When validitycheck is '0' the validity bit in frame isn't checked and all frames are written. Sampled on the rising.." "0,1" bitfld.long 0x0 14. "PARITYGEN,When '1' a parity bit is generated inside the core and added to a transmitted sub-frame. When '0' the value from the parity bit from FIFO is transmitted in sub-frame. Sampled on the rising clock edge." "0,1" newline bitfld.long 0x0 13. "PARITYCHECK,When '1' - check on a parity error in received subframe the parityo is asserted when a parity error has been detected. When '0' - parity bit received in a sub-frame is repeated on the parityo. Sampled on the rising clock edge." "0,1" bitfld.long 0x0 12. "TR_MODE,Direction control (transmitter - '1' / receiver -'0'). Sampled on the rising clock edge" "0,1" bitfld.long 0x0 11. "CLK_ENABLE,Clock enable for the SPDIF core and FIFO. When '1' the clock is blocked and the modules are in power save mode. When '0' the clock feeds the modules. Sampled on the rising clock edge." "0,1" bitfld.long 0x0 10. "FIFO_ENABLE,FIFO enable. When '0' FIFO pointers are reset to zero. Threshold levels for FIFO are unchanged. This bit is automatically set back to '1' after the reset is propagated to the clk_spdif clock domain and back. It takes few clock cycles depends.." "0,1" bitfld.long 0x0 9. "SPDIF_ENABLE,SPDIF core enable. Value '0' causes reset of SPDIF block configuration SFR bits are unchanged. Value '1' enables SPDIF module. Sampled on the rising clock edge." "0,1" bitfld.long 0x0 8. "SFR_ENABLE,Bit controlling SFR block synchronous reset. When '0' all bits in SFR registers are reset to default values. It causes reset of all modules. This bit is automatically set back to '1' after the reset is propagated to the clk_spdif clock domain.." "0,1" newline hexmask.long.byte 0x0 0.--7. 1. "TSAMPLERATE,Transmission sample rate. Determines sample rate for transmission signal. Sampled on the rising clock edge." line.long 0x4 "INT_REG,'Interrupt register'" rbitfld.long 0x4 31. "RESERVED,Unused" "0,1" bitfld.long 0x4 30. "BLOCK_BEGIN,When '1' it indicates start of a new block in received data. It is set to '1' when sub-frame with preamble 'B' has been received and written into FIFO. Once it is set to '1' it holds its value until writing '0'. Updated on the rising clock.." "0,1" bitfld.long 0x4 29. "LOCK,When '1' it indicates that receiver has become synchronized with input data stream (i.e. it is in lock condition). Once it is set to '1' it holds its value until writing '0'. Updated on the rising clock edge." "0,1" bitfld.long 0x4 28. "SYNCERR,When '1' it indicates receiver synchronization error. It is a source of an interrupt request. Once it is set to '1' it holds its value until writing '0' even when synchronization error condition disappears. Updated on the rising clock edge." "0,1" bitfld.long 0x4 27. "FIFO_AFULL,FIFO almost full flag. When the FIFO is almost full this bit is set to '1'. It is a source of an interrupt request. Once it is set to '1' it holds its value until writing '0' even when FIFO almost full condition disappears. Updated on the.." "0,1" bitfld.long 0x4 26. "FIFO_FULL,FIFO full flag. When the FIFO is full this bit is set to '1'. It is a source of an interrupt request. Once it is set to '1' it holds its value until writing '0' even when FIFO full condition disappears. Updated on the rising clock edge." "0,1" newline bitfld.long 0x4 25. "FIFO_AEMPTY,FIFO almost empty flag. When the FIFO is almost empty this bit is set to '1'. It is a source of an interrupt request. Once it is set to '1' it holds its value until writing '0' even when FIFO almost empty condition disappears. Updated on the.." "0,1" bitfld.long 0x4 24. "FIFO_EMPTY,FIFO empty flag. When the FIFO is empty this bit is set to '1'. It is a source of an interrupt request. Once it is set to '1' it holds its value until writing '0' even when FIFO empty condition disappears. Updated on the rising clock edge." "0,1" bitfld.long 0x4 23. "RDATA_OVRERR,Receiver data overrun error. When the error condition occurred this bit is set to '1'. It is a source of an interrupt request. It is cleared only by writing '0' to this bit clearing this bit also resets the FIFO pointers. Configuration.." "0,1" bitfld.long 0x4 22. "TDATA_UNDERR,Transmitter data underrun error. When the error condition occurred this bit is set to '1'. It is a source of an interrupt request. It is cleared only by writing '0' to this bit. Configuration registers contents are preserved as well." "0,1" bitfld.long 0x4 21. "PARITYO,Parity error. This bit is depended on parity_check bit. If the parity_check bit is '1' - this bit indicates a parity error in received sub-frame the parityo is asserted when a parity error has been detected. When parity_check is '0' - parity bit.." "0,1" newline hexmask.long.byte 0x4 8.--11. 1. "PREAMBLEDEL,First 'preamble B' delay. This field is valid only when working as transmitter and setpreambb bit in SPDIF_CTRL register is set. When the setpreambb is not active the preambledel fied has to be filled with zeros. It is number of frames needed.." hexmask.long.byte 0x4 0.--7. 1. "RSAMPLERATE,Receive sample rate. Indicates sample rate of data block that has been just received. Updated on the rising clock edge." line.long 0x8 "FIFO_CTRL,'FIFO control register'" hexmask.long.byte 0x8 16.--21. 1. "AFULL_THRESHOLD,Determines threshold for almost full flag in the FIFO. Sampled on the rising clock edge." hexmask.long.byte 0x8 0.--5. 1. "AEMPTY_THRESHOLD,Determines threshold for almost empty flag in the FIFO. When this field equals to all 0s the FIFO almost empty flag is not generated. Sampled on the rising clock edge." rgroup.long 0xC++0x3 line.long 0x0 "STAT_REG,'FIFO status register'" bitfld.long 0x0 31. "RIGHT_LEFT,A HIGH ('1') value indicates that left channel sub-frame has been received and written into FIFO; while a LOW ('0') value indicates that right channel sub-frame has been received and written into FIFO. Updated on the rising clock edge." "0,1" bitfld.long 0x0 30. "BEGIN_FLAG,When '1' it indicates start of a new block in received data. It is set to '1' when sub-frame with preamble 'B' has been received and written into FIFO and it's cleared when next sub-frame has been received. Updated on the rising clock edge." "0,1" bitfld.long 0x0 29. "LOCK_FLAG,When '1' it indicates that receiver has become synchronized with input data stream (i.e. it is in lock condition) and when synchronization is lost it's cleared. Updated on the rising clock edge." "0,1" bitfld.long 0x0 28. "SYNCERR_FLAG,When '1' it indicates receiver synchronization error and when synchronization error condition disappears it's cleared. Updated on the rising clock edge." "0,1" bitfld.long 0x0 27. "AFULL_FLAG,FIFO almost full flag. When the FIFO is almost full this bit is set to '1' and when FIFO almost full condition disappears it's cleared. Updated on the rising clock edge." "0,1" bitfld.long 0x0 26. "FULL_FLAG,FIFO full flag. When the FIFO is full this bit is set to '1' and when FIFO full condition disappears it's cleared. Updated on the rising clock edge." "0,1" newline bitfld.long 0x0 25. "AEMPTY_FLAG,FIFO almost empty flag. When the FIFO is almost empty this bit is set to '1'and when FIFO almost empty condition disappears it's cleared. Updated on the rising clock edge." "0,1" bitfld.long 0x0 24. "EMPTY_FLAG,FIFO empty flag. When the FIFO is empty this bit is set to '1' and when the FIFO isn't empty it's cleared. Updated on the rising clock edge." "0,1" bitfld.long 0x0 23. "OVRERR_FLAG,Receiver data overrun error. When the error condition occurred this bit is set to '1' and when the error condition disappears it's cleared. Updated on the rising clock edge." "0,1" bitfld.long 0x0 22. "UNDERR_FLAG,Transmitter data underrun flag. When the error condition occurred this bit is set to '1' and when the error condition disappears it is cleared. Updated on the rising clock edge." "0,1" bitfld.long 0x0 21. "PARITY_FLAG,Parity flag. This bit is depended on parity_check bit. If the parity_check bit is '1' - this bit indicates a parity error in received sub-frame the parityo is asserted when a parity error has been detected and it is cleared when a sub-frame.." "0,1" hexmask.long.word 0x0 7.--20. 1. "RESERVED,unused" newline hexmask.long.byte 0x0 0.--6. 1. "FIFO_LEVEL,Indicates transmit/receive FIFO level. Updated on the rising clock edge." tree.end repeat.end endif tree.end tree "SPI (Serial Peripheral Interface)" sif (CORENAME()=="CORTEXR5F") tree "SPI_SLAVE" repeat 8. (increment 1. 1.) (list ad:0xF0380000 ad:0xF0390000 ad:0xF03A0000 ad:0xF03B0000 ad:0xF09A0000 ad:0xF09B0000 ad:0xF09C0000 ad:0xF09D0000) tree "SPI$1" base $2 group.long 0x0++0x1F line.long 0x0 "CTRLR0,This register controls the serial data transfer. It is impossible to write to this register when the DW_apb_ssi is enabled. The DW_apb_ssi is enabled and disabled by writing to the SSIENR register. Reset Value: SSI_CTRLR0_RST" hexmask.long.byte 0x0 25.--31. 1. "RSVD_CTRLR0,SSTE Reserved bits - Read Only" bitfld.long 0x0 24. "SSTE,Slave Select Toggle Enable. When operating in SPI mode with clock phase (SCPH) set to 0 this register controls the behavior of the slave select line (ss_*_n) between data frames. If this register field is set to 1 the ss_*_n line will toggle.." "0,1" newline rbitfld.long 0x0 23. "RSVD_CTRLR0_23,CTRLR0_23 Reserved bits - Read Only" "0,1" rbitfld.long 0x0 21.--22. "SPI_FRF,SPI Frame Format: Selects data frame format for Transmitting/Receiving the data Bits only valid when SSI_SPI_MODE is either set to 'Dual' or 'Quad' or 'Octal' mode. When SSI_SPI_MODE is configured for 'Dual Mode' 10/11 combination is reserved." "Standard SPI Frame Format,Dual SPI Frame Format,Quad SPI Frame Format,Octal SPI Frame Format" newline hexmask.long.byte 0x0 16.--20. 1. "DFS_32,Data Frame Size in 32-bit transfer size mode. Used to select the data frame size in 32-bit transfer mode. These bits are only valid when SSI_MAX_XFER_SIZE is configured to 32. When the data frame size is programmed to be less than 32 bits the.." hexmask.long.byte 0x0 12.--15. 1. "CFS,Control Frame Size. Selects the length of the control word for the Microwire frame format. 0x0: 1-bit Control Word 0x1: 2-bit Control Word 0x2: 3-bit Control Word 0x3: 4-bit Control Word 0x4: 5-bit Control Word 0x5: 6-bit Control Word 0x6: 7-bit.." newline bitfld.long 0x0 11. "SRL,Shift Register Loop. Used for testing purposes only. When internally active connects the transmit shift register output to the receive shift register input. Can be used in both serial-slave and serial-master modes. When the DW_apb_ssi is configured.." "Normal mode operation,Test mode: Tx & Rx shift reg connected" rbitfld.long 0x0 10. "RSVD_SLV_OE,SLV_OE Reserved field - Read-only" "0,1" newline bitfld.long 0x0 8.--9. "TMOD,Transfer Mode. Selects the mode of transfer for serial communication. This field does not affect the transfer duplicity. Only indicates whether the receive or transmit data are valid. In transmit-only mode data received from the external device is.." "Transmit & receive,Transmit only mode or Write,Receive only mode or Read,EEPROM Read mode" bitfld.long 0x0 7. "SCPOL,Serial Clock Polarity. Valid when the frame format (FRF) is set to Motorola SPI. Used to select the polarity of the inactive serial clock which is held inactive when the DW_apb_ssi master is not actively transferring data on the serial bus. 0x1:.." "Inactive state of serial clock is low,Inactive state of serial clock is high" newline bitfld.long 0x0 6. "SCPH,Serial Clock Phase. Valid when the frame format (FRF) is set to Motorola SPI. The serial clock phase selects the relationship of the serial clock with the slave select signal. When SCPH = 0 data are captured on the first edge of the serial clock." "Serial clock toggles in middle of first data bit,Serial clock toggles at start of first data bit" bitfld.long 0x0 4.--5. "FRF,Frame Format. Selects which serial protocol transfers the data. 0x0: Motorolla SPI Frame Format 0x2: National Microwire Frame Format 0x3: Reserved value 0x1: Texas Instruments SSP Frame Format" "Motorolla SPI Frame Format,Texas Instruments SSP Frame Format,National Microwire Frame Format,Reserved value" newline hexmask.long.byte 0x0 0.--3. 1. "DFS,Data Frame Size. This register field is only valid when SSI_MAX_XFER_SIZE is configured to 16. If SSI_MAX_XFER_SIZE is configured to 32 then writing to this field will not have any effect. Selects the data frame length. When the data frame size is.." line.long 0x4 "CTRLR1,This register exists only when the DW_apb_ssi is configured as a master device. When the DW_apb_ssi is configured as a serial slave. writing to this location has no effect; reading from this location returns 0. Control register 1 controls the end.." hexmask.long.word 0x4 16.--31. 1. "RSVD_CTRLR1,CTRLR1 Reserved bits - Read Only" hexmask.long.word 0x4 0.--15. 1. "NDF,Number of Data Frames. When TMOD = 10 or TMOD = 11 this register field sets the number of data frames to be continuously received by the DW_apb_ssi. The DW_apb_ssi continues to receive serial data until the number of data frames received is equal.." line.long 0x8 "SSIENR,This register enables and disables the DW_apb_ssi. Reset Value: 0x0" hexmask.long 0x8 1.--31. 1. "RSVD_SSIENR,SSIENR Reserved bits - Read Only" bitfld.long 0x8 0. "SSI_EN,SSI Enable. Enables and disables all DW_apb_ssi operations. When disabled all serial transfers are halted immediately. Transmit and receive FIFO buffers are cleared when the device is disabled. It is impossible to program some of the DW_apb_ssi.." "Disables Serial Transfer,Enables Serial Transfer" line.long 0xC "MWCR,This register controls the direction of the data word for the half-duplex Microwire serial protocol. It is impossible to write to this register when the DW_apb_ssi is enabled. The DW_apb_ssi is enabled and disabled by writing to the SSIENR register." hexmask.long 0xC 3.--31. 1. "RSVD_MWCR,MWCR Reserved bits - Read Only" bitfld.long 0xC 2. "MHS,Microwire Handshaking. Relevant only when the DW_apb_ssi is configured as a serial-master device. When configured as a serial slave this bit field has no functionality. Used to enable and disable the busy/ready handshaking interface for the.." "Handshaking interface is disabled,Handshaking interface is enabled" newline bitfld.long 0xC 1. "MDD,Microwire Control. Defines the direction of the data word when the Microwire serial protocol is used. When this bit is set to 0 the data word is received by the DW_apb_ssi MacroCell from the external serial device. When this bit is set to 1 the.." "SSI receives data,SSI transmits data" bitfld.long 0xC 0. "MWMOD,Microwire Transfer Mode. Defines whether the Microwire transfer is sequential or non-sequential. When sequential mode is used only one control word is needed to transmit or receive a block of data words. When non-sequential mode is used there.." "Non-Sequential Microwire Transfer,Sequential Microwire Transfer" line.long 0x10 "SER,This register is valid only when the DW_apb_ssi is configured as a master device. When the DW_apb_ssi is configured as a serial slave. writing to this location has no effect; reading from this location returns 0. The register enables the individual.." hexmask.long 0x10 4.--31. 1. "RSVD_SER,SER Reserved bits - Read Only" hexmask.long.byte 0x10 0.--3. 1. "SER,Slave Select Enable Flag. Each bit in this register corresponds to a slave select line (ss_x_n) from the DW_apb_ssi master. When a bit in this register is set (1) the corresponding slave select line from the master is activated when a serial.." line.long 0x14 "BAUDR,This register is valid only when the DW_apb_ssi is configured as a master device. When the DW_apb_ssi is configured as a serial slave. writing to this location has no effect; reading from this location returns 0. The register derives the frequency.." hexmask.long.word 0x14 16.--31. 1. "RSVD_BAUDR,BAUDR Reserved bits - Read Only" hexmask.long.word 0x14 0.--15. 1. "SCKDV,SSI Clock Divider. The LSB for this field is always set to 0 and is unaffected by a write operation which ensures an even value is held in this register. If the value is 0 the serial output clock (sclk_out) is disabled. The frequency of the.." line.long 0x18 "TXFTLR,This register controls the threshold value for the transmit FIFO memory. The DW_apb_ssi is enabled and disabled by writing to the SSIENR register. Reset Value: 0x0" hexmask.long 0x18 3.--31. 1. "RSVD_TXFTLR,TXFTLR Reserved bits - Read Only" bitfld.long 0x18 0.--2. "TFT,Transmit FIFO Threshold. Controls the level of entries (or below) at which the transmit FIFO controller triggers an interrupt. The FIFO depth is configurable in the range 2-256; this register is sized to the number of address bits needed to access.." "0,1,2,3,4,5,6,7" line.long 0x1C "RXFTLR,This register controls the threshold value for the receive FIFO memory. The DW_apb_ssi is enabled and disabled by writing to the SSIENR register. Reset Value: 0x0" hexmask.long 0x1C 3.--31. 1. "RSVD_RXFTLR,RXFTLR Reserved bits - Read Only" bitfld.long 0x1C 0.--2. "RFT,Receive FIFO Threshold. Controls the level of entries (or above) at which the receive FIFO controller triggers an interrupt. The FIFO depth is configurable in the range 2-256. This register is sized to the number of address bits needed to access the.." "0,1,2,3,4,5,6,7" rgroup.long 0x20++0xB line.long 0x0 "TXFLR,This register contains the number of valid data entries in the transmit FIFO memory. Reset Value: 0x0" hexmask.long 0x0 4.--31. 1. "RSVD_TXFLR,TXFLR Reserved bits - Read Only" hexmask.long.byte 0x0 0.--3. 1. "TXTFL,Transmit FIFO Level. Contains the number of valid data entries in the transmit FIFO." line.long 0x4 "RXFLR,This register contains the number of valid data entries in the receive FIFO memory. This register can be ready at any time. Reset Value: 0x0" hexmask.long 0x4 4.--31. 1. "RSVD_RXFLR,RXFLR Reserved bits - Read Only" hexmask.long.byte 0x4 0.--3. 1. "RXTFL,Receive FIFO Level. Contains the number of valid data entries in the receive FIFO." line.long 0x8 "SR,This is a read-only register used to indicate the current transfer status. FIFO status. and any transmission/reception errors that may have occurred. The status register may be read at any time. None of the bits in this register request an interrupt." hexmask.long 0x8 7.--31. 1. "RSVD_SR,SR Reserved bits - Read Only" bitfld.long 0x8 6. "DCOL,Data Collision Error. Relevant only when the DW_apb_ssi is configured as a master device. This bit will be set if ss_in_n input is asserted by other master when the DW_apb_ssi master is in the middle of the transfer. This informs the processor that.." "No Error,Transmit Data Collision Error" newline bitfld.long 0x8 5. "RSVD_TXE,TXE Reserved field - read-only" "0,1" bitfld.long 0x8 4. "RFF,Receive FIFO Full. When the receive FIFO is completely full this bit is set. When the receive FIFO contains one or more empty location this bit is cleared. 0x1: Receive FIFO is full 0x0: Receive FIFO is not full" "Receive FIFO is not full,Receive FIFO is full" newline bitfld.long 0x8 3. "RFNE,Receive FIFO Not Empty. Set when the receive FIFO contains one or more entries and is cleared when the receive FIFO is empty. This bit can be polled by software to completely empty the receive FIFO. 0x0: Receive FIFO is empty 0x1: Receive FIFO is.." "Receive FIFO is empty,Receive FIFO is not empty" bitfld.long 0x8 2. "TFE,Transmit FIFO Empty. When the transmit FIFO is completely empty this bit is set. When the transmit FIFO contains one or more valid entries this bit is cleared. This bit field does not request an interrupt. 0x1: Transmit FIFO is empty 0x0: Transmit.." "Transmit FIFO is not empty,Transmit FIFO is empty" newline bitfld.long 0x8 1. "TFNF,Transmit FIFO Not Full. Set when the transmit FIFO contains one or more empty locations and is cleared when the FIFO is full. 0x0: Transmit FIFO is full 0x1: Transmit FIFO is not Full" "Transmit FIFO is full,Transmit FIFO is not Full" bitfld.long 0x8 0. "BUSY,SSI Busy Flag. When set indicates that a serial transfer is in progress; when cleared indicates that the DW_apb_ssi is idle or disabled. 0x1: DW_apb_ssi is actively transferring data 0x0: DW_apb_ssi is idle or disabled" "DW_apb_ssi is idle or disabled,DW_apb_ssi is actively transferring data" group.long 0x2C++0x3 line.long 0x0 "IMR,This read/write reigster masks or enables all interrupts generated by the DW_apb_ssi. When the DW_apb_ssi is configured as a slave device. the MSTIM bit field is not present. This changes the reset value from 0x3F for serial-master configurations to.." hexmask.long 0x0 6.--31. 1. "RSVD_IMR,IMR Reserved bits - Read Only" bitfld.long 0x0 5. "MSTIM,Multi-Master Contention Interrupt Mask. This bit field is not present if the DW_apb_ssi is configured as a serial-slave device. 0x0: ssi_mst_intr interrupt is masked 0x1: ssi_mst_intr interrupt is not masked" "ssi_mst_intr interrupt is masked,ssi_mst_intr interrupt is not masked" newline bitfld.long 0x0 4. "RXFIM,Receive FIFO Full Interrupt Mask 0x0: ssi_rxf_intr interrupt is masked 0x1: ssi_rxf_intr interrupt is not masked" "ssi_rxf_intr interrupt is masked,ssi_rxf_intr interrupt is not masked" bitfld.long 0x0 3. "RXOIM,Receive FIFO Overflow Interrupt Mask 0x0: ssi_rxo_intr interrupt is masked 0x1: ssi_rxo_intr interrupt is not masked" "ssi_rxo_intr interrupt is masked,ssi_rxo_intr interrupt is not masked" newline bitfld.long 0x0 2. "RXUIM,Receive FIFO Underflow Interrupt Mask 0x0: ssi_rxu_intr interrupt is masked 0x1: ssi_rxu_intr interrupt is not masked" "ssi_rxu_intr interrupt is masked,ssi_rxu_intr interrupt is not masked" bitfld.long 0x0 1. "TXOIM,Transmit FIFO Overflow Interrupt Mask 0x0: ssi_txo_intr interrupt is masked 0x1: ssi_txo_intr interrupt is not masked" "ssi_txo_intr interrupt is masked,ssi_txo_intr interrupt is not masked" newline bitfld.long 0x0 0. "TXEIM,Transmit FIFO Empty Interrupt Mask 0x0: ssi_txe_intr interrupt is masked 0x1: ssi_txe_intr interrupt is not masked" "ssi_txe_intr interrupt is masked,ssi_txe_intr interrupt is not masked" rgroup.long 0x30++0x1B line.long 0x0 "ISR,This register reports the status of the DW_apb_ssi interrupts after they have been masked. Reset Value: 0x0" hexmask.long 0x0 6.--31. 1. "RSVD_ISR,ISR Reserved bits - Read Only" bitfld.long 0x0 5. "MSTIS,Multi-Master Contention Interrupt Status. This bit field is not present if the DW_apb_ssi is configured as a serial-slave device. 0x1: ssi_mst_intr interrupt is active after masking 0x0: ssi_mst_intr interrupt not active after masking" "ssi_mst_intr interrupt not active after masking,ssi_mst_intr interrupt is active after masking" newline bitfld.long 0x0 4. "RXFIS,Receive FIFO Full Interrupt Status 0x1: ssi_rxf_intr interrupt is full after masking 0x0: ssi_rxf_intr interrupt is not active after masking" "ssi_rxf_intr interrupt is not active after masking,ssi_rxf_intr interrupt is full after masking" bitfld.long 0x0 3. "RXOIS,Receive FIFO Overflow Interrupt Status 0x1: ssi_rxo_intr interrupt is active after masking 0x0: ssi_rxo_intr interrupt is not active after masking" "ssi_rxo_intr interrupt is not active after masking,ssi_rxo_intr interrupt is active after masking" newline bitfld.long 0x0 2. "RXUIS,Receive FIFO Underflow Interrupt Status 0x1: ssi_rxu_intr interrupt is active after masking 0x0: ssi_rxu_intr interrupt is not active after masking" "ssi_rxu_intr interrupt is not active after masking,ssi_rxu_intr interrupt is active after masking" bitfld.long 0x0 1. "TXOIS,Transmit FIFO Overflow Interrupt Status 0x1: ssi_txo_intr interrupt is active after masking 0x0: ssi_txo_intr interrupt is not active after masking" "ssi_txo_intr interrupt is not active after masking,ssi_txo_intr interrupt is active after masking" newline bitfld.long 0x0 0. "TXEIS,Transmit FIFO Empty Interrupt Status 0x1: ssi_txe_intr interrupt is active after masking 0x0: ssi_txe_intr interrupt is not active after masking" "ssi_txe_intr interrupt is not active after masking,ssi_txe_intr interrupt is active after masking" line.long 0x4 "RISR,This read-only register reports the status of the DW_apb_ssi interrupts prior to masking. Reset Value: 0x0" hexmask.long 0x4 6.--31. 1. "RSVD_RISR,RISR Reserved bits - Read Only" bitfld.long 0x4 5. "MSTIR,Multi-Master Contention Raw Interrupt Status. This bit field is not present if the DW_apb_ssi is configured as a serial-slave device. 0x1: ssi_mst_intr interrupt is active prior masking 0x0: ssi_mst_intr interrupt is not active prior to masking" "ssi_mst_intr interrupt is not active prior to..,ssi_mst_intr interrupt is active prior masking" newline bitfld.long 0x4 4. "RXFIR,Receive FIFO Full Raw Interrupt Status 0x1: ssi_rxf_intr interrupt is active prior to masking 0x0: ssi_rxf_intr interrupt is not active prior to masking" "ssi_rxf_intr interrupt is not active prior to..,ssi_rxf_intr interrupt is active prior to masking" bitfld.long 0x4 3. "RXOIR,Receive FIFO Overflow Raw Interrupt Status 0x1: ssi_rxo_intr interrupt is not active prior to masking 0x0: ssi_rxo_intr interrupt is active prior masking" "ssi_rxo_intr interrupt is active prior masking,ssi_rxo_intr interrupt is not active prior to.." newline bitfld.long 0x4 2. "RXUIR,Receive FIFO Underflow Raw Interrupt Status 0x1: ssi_rxu_intr interrupt is active prior to masking 0x0: ssi_rxu_intr interrupt is not active prior to masking" "ssi_rxu_intr interrupt is not active prior to..,ssi_rxu_intr interrupt is active prior to masking" bitfld.long 0x4 1. "TXOIR,Transmit FIFO Overflow Raw Interrupt Status 0x1: ssi_txo_intr interrupt is active prior masking 0x0: ssi_txo_intr interrupt is not active prior to masking" "ssi_txo_intr interrupt is not active prior to..,ssi_txo_intr interrupt is active prior masking" newline bitfld.long 0x4 0. "TXEIR,Transmit FIFO Empty Raw Interrupt Status 0x1: ssi_txe_intr interrupt is active prior masking 0x0: ssi_txe_intr interrupt is not active prior to masking" "ssi_txe_intr interrupt is not active prior to..,ssi_txe_intr interrupt is active prior masking" line.long 0x8 "TXOICR,Transmit FIFO Overflow Interrupt Clear Register. Reset Value: 0x0" hexmask.long 0x8 1.--31. 1. "RSVD_TXOICR,TXOICR Reserved bits - Read Only" bitfld.long 0x8 0. "TXOICR,Clear Transmit FIFO Overflow Interrupt. This register reflects the status of the interrupt. A read from this register clears the ssi_txo_intr interrupt; writing has no effect." "0,1" line.long 0xC "RXOICR,Receive FIFO Overflow Interrupt Clear Register. Reset Value: 0x0" hexmask.long 0xC 1.--31. 1. "RSVD_RXOICR,RXOICR Reserved bits - Read Only" bitfld.long 0xC 0. "RXOICR,Clear Receive FIFO Overflow Interrupt. This register reflects the status of the interrupt. A read from this register clears the ssi_rxo_intr interrupt; writing has no effect." "0,1" line.long 0x10 "RXUICR,Receive FIFO Underflow Interrupt Clear Register. Reset Value: 0x0" hexmask.long 0x10 1.--31. 1. "RSVD_RXUICR,RXUICR Reserved bits - Read Only" bitfld.long 0x10 0. "RXUICR,Clear Receive FIFO Underflow Interrupt. This register reflects the status of the interrupt. A read from this register clears the ssi_rxu_intr interrupt; writing has no effect." "0,1" line.long 0x14 "MSTICR,Multi-Master Interrupt Clear Register. Reset Value: 0x0" hexmask.long 0x14 1.--31. 1. "RSVD_MSTICR,MSTICR Reserved bits - Read Only" bitfld.long 0x14 0. "MSTICR,Clear Multi-Master Contention Interrupt. This register reflects the status of the interrupt. A read from this register clears the ssi_mst_intr interrupt; writing has no effect." "0,1" line.long 0x18 "ICR,Interrupt Clear Register. Reset Value: 0x0" hexmask.long 0x18 1.--31. 1. "RSVD_ICR,ICR Reserved bits - Read Only" bitfld.long 0x18 0. "ICR,Clear Interrupts. This register is set if any of the interrupts below are active. A read clears the ssi_txo_intr ssi_rxu_intr ssi_rxo_intr and the ssi_mst_intr interrupts. Writing to this register has no effect." "0,1" group.long 0x4C++0xB line.long 0x0 "DMACR,This register is only valid when DW_apb_ssi is configured with a set of DMA Controller interface signals (SSI_HAS_DMA = 1). When DW_apb_ssi is not configured for DMA operation. this register will not exist and writing to the register's address will.." hexmask.long 0x0 2.--31. 1. "RSVD_DMACR,DMACR Reserved bits - Read Only" bitfld.long 0x0 1. "TDMAE,Transmit DMA Enable. This bit enables/disables the transmit FIFO DMA channel. 0x0: Transmit DMA disabled 0x1: Transmit DMA enabled" "Transmit DMA disabled,Transmit DMA enabled" newline bitfld.long 0x0 0. "RDMAE,Receive DMA Enable. This bit enables/disables the receive FIFO DMA channel 0x0: Receive DMA disabled 0x1: Receive DMA enabled" "Receive DMA disabled,Receive DMA enabled" line.long 0x4 "DMATDLR,This register is only valid when the DW_apb_ssi is configured with a set of DMA interface signals (SSI_HAS_DMA = 1). When DW_apb_ssi is not configured for DMA operation. this register will not exist and writing to its address will have no effect;.." hexmask.long 0x4 3.--31. 1. "RSVD_DMATDLR,DMATDLR Reserved bits - Read Only" bitfld.long 0x4 0.--2. "DMATDL,Transmit Data Level. This bit field controls the level at which a DMA request is made by the transmit logic. It is equal to the watermark level; that is the dma_tx_req signal is generated when the number of valid data entries in the transmit FIFO.." "0,1,2,3,4,5,6,7" line.long 0x8 "DMARDLR,This register is only valid when DW_apb_ssi is configured with a set of DMA interface signals (SSI_HAS_DMA = 1). When DW_apb_ssi is not configured for DMA operation. this register will not exist and writing to its address will have no effect;.." hexmask.long 0x8 3.--31. 1. "RSVD_DMARDLR,DMARDLR Reserved bits - Read Only" bitfld.long 0x8 0.--2. "DMARDL,Receive Data Level. This bit field controls the level at which a DMA request is made by the receive logic. The watermark level = DMARDL+1; that is dma_rx_req is generated when the number of valid data entries in the receive FIFO is equal to or.." "0,1,2,3,4,5,6,7" rgroup.long 0x58++0x7 line.long 0x0 "IDR,This register contains the peripherals identification code. which is written into the register at configuration time using coreConsultant. Reset Value: SSI_ID" hexmask.long 0x0 0.--31. 1. "IDCODE,Identification code. The register contains the peripheral's identification code which is written into the register at configuration time using CoreConsultant." line.long 0x4 "SSI_VERSION_ID,This read-only register stores the specific DW_apb_ssi component version. Reset Value: SSI_VERSION_ID" hexmask.long 0x4 0.--31. 1. "SSI_COMP_VERSION,Contains the hex representation of the Synopsys component version. Consists of ASCII value for each number in the version followed by *. For example 32_30_31_2A represents the version 2.01*." repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x4 0x8 0xC 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C ) group.long ($2+0x60)++0x3 line.long 0x0 "DR$1,The DW_apb_ssi data register is a 16/32-bit (depending on SSI_MAX_XFER_SIZE) read/write buffer for the transmit/receive FIFOs. If the configuration parameter SSI_MAX_XFER_SIZE is set to 32. then all 32 bits are valid. otherwise. only 16 bits.." hexmask.long 0x0 0.--31. 1. "DR,Data Register. When writing to this register you must right-justify the data. Read data are automatically right-justified. If SSI_MAX_XFER_SIZE configuration parameter is set to 32 all 32 bits are valid. Otherwise only 16 bits ([15:0]) of the.." repeat.end repeat 16. (list 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1A 0x1B 0x1C 0x1D 0x1E 0x1F )(list 0x40 0x44 0x48 0x4C 0x50 0x54 0x58 0x5C 0x60 0x64 0x68 0x6C 0x70 0x74 0x78 0x7C ) group.long ($2+0x60)++0x3 line.long 0x0 "DR$1,The DW_apb_ssi data register is a 16/32-bit (depending on SSI_MAX_XFER_SIZE) read/write buffer for the transmit/receive FIFOs. If the configuration parameter SSI_MAX_XFER_SIZE is set to 32. then all 32 bits are valid. otherwise. only 16 bits.." hexmask.long 0x0 0.--31. 1. "DR,Data Register. When writing to this register you must right-justify the data. Read data are automatically right-justified. If SSI_MAX_XFER_SIZE configuration parameter is set to 32 all 32 bits are valid. Otherwise only 16 bits ([15:0]) of the.." repeat.end repeat 4. (list 0x20 0x21 0x22 0x23 )(list 0x80 0x84 0x88 0x8C ) group.long ($2+0x60)++0x3 line.long 0x0 "DR$1,The DW_apb_ssi data register is a 16/32-bit (depending on SSI_MAX_XFER_SIZE) read/write buffer for the transmit/receive FIFOs. If the configuration parameter SSI_MAX_XFER_SIZE is set to 32. then all 32 bits are valid. otherwise. only 16 bits.." hexmask.long 0x0 0.--31. 1. "DR,Data Register. When writing to this register you must right-justify the data. Read data are automatically right-justified. If SSI_MAX_XFER_SIZE configuration parameter is set to 32 all 32 bits are valid. Otherwise only 16 bits ([15:0]) of the.." repeat.end rgroup.long 0xFC++0x3 line.long 0x0 "RSVD,RSVD - Reserved address location." hexmask.long 0x0 0.--31. 1. "RSVD,RSVD 31to0 Reserved address location" tree.end repeat.end tree.end tree "SPI_MASTER" repeat 8. (increment 1. 1.) (list ad:0xF0380000 ad:0xF0390000 ad:0xF03A0000 ad:0xF03B0000 ad:0xF09A0000 ad:0xF09B0000 ad:0xF09C0000 ad:0xF09D0000) tree "SPI$1" base $2 group.long 0x0++0x3 line.long 0x0 "CTRLR0,This register controls the serial data transfer. It is impossible to write to this register when the DW_apb_ssi is enabled. The DW_apb_ssi is enabled and disabled by writing to the SSIENR register. Reset Value: SSI_CTRLR0_RST" hexmask.long.byte 0x0 25.--31. 1. "RSVD_CTRLR0,SSTE Reserved bits - Read Only" bitfld.long 0x0 24. "SSTE,Slave Select Toggle Enable. When operating in SPI mode with clock phase (SCPH) set to 0 this register controls the behavior of the slave select line (ss_*_n) between data frames. If this register field is set to 1 the ss_*_n line will toggle.." "0,1" newline rbitfld.long 0x0 23. "RSVD_CTRLR0_23,CTRLR0_23 Reserved bits - Read Only" "0,1" rbitfld.long 0x0 21.--22. "SPI_FRF,SPI Frame Format: Selects data frame format for Transmitting/Receiving the data Bits only valid when SSI_SPI_MODE is either set to 'Dual' or 'Quad' or 'Octal' mode. When SSI_SPI_MODE is configured for 'Dual Mode' 10/11 combination is reserved." "Standard SPI Frame Format,Dual SPI Frame Format,Quad SPI Frame Format,Octal SPI Frame Format" newline hexmask.long.byte 0x0 16.--20. 1. "DFS_32,Data Frame Size in 32-bit transfer size mode. Used to select the data frame size in 32-bit transfer mode. These bits are only valid when SSI_MAX_XFER_SIZE is configured to 32. When the data frame size is programmed to be less than 32 bits the.." hexmask.long.byte 0x0 12.--15. 1. "CFS,Control Frame Size. Selects the length of the control word for the Microwire frame format. 0x0: 1-bit Control Word 0x1: 2-bit Control Word 0x2: 3-bit Control Word 0x3: 4-bit Control Word 0x4: 5-bit Control Word 0x5: 6-bit Control Word 0x6: 7-bit.." newline bitfld.long 0x0 11. "SRL,Shift Register Loop. Used for testing purposes only. When internally active connects the transmit shift register output to the receive shift register input. Can be used in both serial-slave and serial-master modes. When the DW_apb_ssi is configured.." "Normal mode operation,Test mode: Tx & Rx shift reg connected" bitfld.long 0x0 10. "SLV_OE,Slave Output Enable. Relevant only when the DW_apb_ssi is configured as a serial-slave device. When configured as a serial master this bit field has no functionality. This bit enables or disables the setting of the ssi_oe_n output from the.." "Slave Output is enabled,Slave Output is disabled" newline bitfld.long 0x0 8.--9. "TMOD,Transfer Mode. Selects the mode of transfer for serial communication. This field does not affect the transfer duplicity. Only indicates whether the receive or transmit data are valid. In transmit-only mode data received from the external device is.." "Transmit & receive,Transmit only mode or Write,Receive only mode or Read,EEPROM Read mode" bitfld.long 0x0 7. "SCPOL,Serial Clock Polarity. Valid when the frame format (FRF) is set to Motorola SPI. Used to select the polarity of the inactive serial clock which is held inactive when the DW_apb_ssi master is not actively transferring data on the serial bus. 0x1:.." "Inactive state of serial clock is low,Inactive state of serial clock is high" newline bitfld.long 0x0 6. "SCPH,Serial Clock Phase. Valid when the frame format (FRF) is set to Motorola SPI. The serial clock phase selects the relationship of the serial clock with the slave select signal. When SCPH = 0 data are captured on the first edge of the serial clock." "Serial clock toggles in middle of first data bit,Serial clock toggles at start of first data bit" bitfld.long 0x0 4.--5. "FRF,Frame Format. Selects which serial protocol transfers the data. 0x0: Motorolla SPI Frame Format 0x2: National Microwire Frame Format 0x3: Reserved value 0x1: Texas Instruments SSP Frame Format" "Motorolla SPI Frame Format,Texas Instruments SSP Frame Format,National Microwire Frame Format,Reserved value" newline hexmask.long.byte 0x0 0.--3. 1. "DFS,Data Frame Size. This register field is only valid when SSI_MAX_XFER_SIZE is configured to 16. If SSI_MAX_XFER_SIZE is configured to 32 then writing to this field will not have any effect. Selects the data frame length. When the data frame size is.." group.long 0x8++0x7 line.long 0x0 "SSIENR,This register enables and disables the DW_apb_ssi. Reset Value: 0x0" hexmask.long 0x0 1.--31. 1. "RSVD_SSIENR,SSIENR Reserved bits - Read Only" bitfld.long 0x0 0. "SSI_EN,SSI Enable. Enables and disables all DW_apb_ssi operations. When disabled all serial transfers are halted immediately. Transmit and receive FIFO buffers are cleared when the device is disabled. It is impossible to program some of the DW_apb_ssi.." "Disables Serial Transfer,Enables Serial Transfer" line.long 0x4 "MWCR,This register controls the direction of the data word for the half-duplex Microwire serial protocol. It is impossible to write to this register when the DW_apb_ssi is enabled. The DW_apb_ssi is enabled and disabled by writing to the SSIENR register." hexmask.long 0x4 3.--31. 1. "RSVD_MWCR,MWCR Reserved bits - Read Only" rbitfld.long 0x4 2. "RSVD_MHS,MHS Reserved field - read-only" "0,1" newline bitfld.long 0x4 1. "MDD,Microwire Control. Defines the direction of the data word when the Microwire serial protocol is used. When this bit is set to 0 the data word is received by the DW_apb_ssi MacroCell from the external serial device. When this bit is set to 1 the.." "SSI receives data,SSI transmits data" bitfld.long 0x4 0. "MWMOD,Microwire Transfer Mode. Defines whether the Microwire transfer is sequential or non-sequential. When sequential mode is used only one control word is needed to transmit or receive a block of data words. When non-sequential mode is used there.." "Non-Sequential Microwire Transfer,Sequential Microwire Transfer" group.long 0x18++0x7 line.long 0x0 "TXFTLR,This register controls the threshold value for the transmit FIFO memory. The DW_apb_ssi is enabled and disabled by writing to the SSIENR register. Reset Value: 0x0" hexmask.long 0x0 3.--31. 1. "RSVD_TXFTLR,TXFTLR Reserved bits - Read Only" bitfld.long 0x0 0.--2. "TFT,Transmit FIFO Threshold. Controls the level of entries (or below) at which the transmit FIFO controller triggers an interrupt. The FIFO depth is configurable in the range 2-256; this register is sized to the number of address bits needed to access.." "0,1,2,3,4,5,6,7" line.long 0x4 "RXFTLR,This register controls the threshold value for the receive FIFO memory. The DW_apb_ssi is enabled and disabled by writing to the SSIENR register. Reset Value: 0x0" hexmask.long 0x4 3.--31. 1. "RSVD_RXFTLR,RXFTLR Reserved bits - Read Only" bitfld.long 0x4 0.--2. "RFT,Receive FIFO Threshold. Controls the level of entries (or above) at which the receive FIFO controller triggers an interrupt. The FIFO depth is configurable in the range 2-256. This register is sized to the number of address bits needed to access the.." "0,1,2,3,4,5,6,7" rgroup.long 0x20++0xB line.long 0x0 "TXFLR,This register contains the number of valid data entries in the transmit FIFO memory. Reset Value: 0x0" hexmask.long 0x0 4.--31. 1. "RSVD_TXFLR,TXFLR Reserved bits - Read Only" hexmask.long.byte 0x0 0.--3. 1. "TXTFL,Transmit FIFO Level. Contains the number of valid data entries in the transmit FIFO." line.long 0x4 "RXFLR,This register contains the number of valid data entries in the receive FIFO memory. This register can be ready at any time. Reset Value: 0x0" hexmask.long 0x4 4.--31. 1. "RSVD_RXFLR,RXFLR Reserved bits - Read Only" hexmask.long.byte 0x4 0.--3. 1. "RXTFL,Receive FIFO Level. Contains the number of valid data entries in the receive FIFO." line.long 0x8 "SR,This is a read-only register used to indicate the current transfer status. FIFO status. and any transmission/reception errors that may have occurred. The status register may be read at any time. None of the bits in this register request an interrupt." hexmask.long 0x8 7.--31. 1. "RSVD_SR,SR Reserved bits - Read Only" bitfld.long 0x8 6. "RSVD_DCOL,DCOL Reserved field - read-only" "0,1" newline bitfld.long 0x8 5. "TXE,Transmission Error. Set if the transmit FIFO is empty when a transfer is started. This bit can be set only when the DW_apb_ssi is configured as a slave device. Data from the previous transmission is resent on the txd line. This bit is cleared when.." "No Error,Transmission Error" bitfld.long 0x8 4. "RFF,Receive FIFO Full. When the receive FIFO is completely full this bit is set. When the receive FIFO contains one or more empty location this bit is cleared. 0x1: Receive FIFO is full 0x0: Receive FIFO is not full" "Receive FIFO is not full,Receive FIFO is full" newline bitfld.long 0x8 3. "RFNE,Receive FIFO Not Empty. Set when the receive FIFO contains one or more entries and is cleared when the receive FIFO is empty. This bit can be polled by software to completely empty the receive FIFO. 0x0: Receive FIFO is empty 0x1: Receive FIFO is.." "Receive FIFO is empty,Receive FIFO is not empty" bitfld.long 0x8 2. "TFE,Transmit FIFO Empty. When the transmit FIFO is completely empty this bit is set. When the transmit FIFO contains one or more valid entries this bit is cleared. This bit field does not request an interrupt. 0x1: Transmit FIFO is empty 0x0: Transmit.." "Transmit FIFO is not empty,Transmit FIFO is empty" newline bitfld.long 0x8 1. "TFNF,Transmit FIFO Not Full. Set when the transmit FIFO contains one or more empty locations and is cleared when the FIFO is full. 0x0: Transmit FIFO is full 0x1: Transmit FIFO is not Full" "Transmit FIFO is full,Transmit FIFO is not Full" bitfld.long 0x8 0. "BUSY,SSI Busy Flag. When set indicates that a serial transfer is in progress; when cleared indicates that the DW_apb_ssi is idle or disabled. 0x1: DW_apb_ssi is actively transferring data 0x0: DW_apb_ssi is idle or disabled" "DW_apb_ssi is idle or disabled,DW_apb_ssi is actively transferring data" group.long 0x2C++0x3 line.long 0x0 "IMR,This read/write reigster masks or enables all interrupts generated by the DW_apb_ssi. When the DW_apb_ssi is configured as a slave device. the MSTIM bit field is not present. This changes the reset value from 0x3F for serial-master configurations to.." hexmask.long 0x0 6.--31. 1. "RSVD_IMR,IMR Reserved bits - Read Only" rbitfld.long 0x0 5. "RSVD_MSTIM,MSTIM Reserved field - read-only" "0,1" newline bitfld.long 0x0 4. "RXFIM,Receive FIFO Full Interrupt Mask 0x0: ssi_rxf_intr interrupt is masked 0x1: ssi_rxf_intr interrupt is not masked" "ssi_rxf_intr interrupt is masked,ssi_rxf_intr interrupt is not masked" bitfld.long 0x0 3. "RXOIM,Receive FIFO Overflow Interrupt Mask 0x0: ssi_rxo_intr interrupt is masked 0x1: ssi_rxo_intr interrupt is not masked" "ssi_rxo_intr interrupt is masked,ssi_rxo_intr interrupt is not masked" newline bitfld.long 0x0 2. "RXUIM,Receive FIFO Underflow Interrupt Mask 0x0: ssi_rxu_intr interrupt is masked 0x1: ssi_rxu_intr interrupt is not masked" "ssi_rxu_intr interrupt is masked,ssi_rxu_intr interrupt is not masked" bitfld.long 0x0 1. "TXOIM,Transmit FIFO Overflow Interrupt Mask 0x0: ssi_txo_intr interrupt is masked 0x1: ssi_txo_intr interrupt is not masked" "ssi_txo_intr interrupt is masked,ssi_txo_intr interrupt is not masked" newline bitfld.long 0x0 0. "TXEIM,Transmit FIFO Empty Interrupt Mask 0x0: ssi_txe_intr interrupt is masked 0x1: ssi_txe_intr interrupt is not masked" "ssi_txe_intr interrupt is masked,ssi_txe_intr interrupt is not masked" rgroup.long 0x30++0x1B line.long 0x0 "ISR,This register reports the status of the DW_apb_ssi interrupts after they have been masked. Reset Value: 0x0" hexmask.long 0x0 6.--31. 1. "RSVD_ISR,ISR Reserved bits - Read Only" bitfld.long 0x0 5. "RSVD_MSTIS,MSTIS Reserved field - read-only" "0,1" newline bitfld.long 0x0 4. "RXFIS,Receive FIFO Full Interrupt Status 0x1: ssi_rxf_intr interrupt is full after masking 0x0: ssi_rxf_intr interrupt is not active after masking" "ssi_rxf_intr interrupt is not active after masking,ssi_rxf_intr interrupt is full after masking" bitfld.long 0x0 3. "RXOIS,Receive FIFO Overflow Interrupt Status 0x1: ssi_rxo_intr interrupt is active after masking 0x0: ssi_rxo_intr interrupt is not active after masking" "ssi_rxo_intr interrupt is not active after masking,ssi_rxo_intr interrupt is active after masking" newline bitfld.long 0x0 2. "RXUIS,Receive FIFO Underflow Interrupt Status 0x1: ssi_rxu_intr interrupt is active after masking 0x0: ssi_rxu_intr interrupt is not active after masking" "ssi_rxu_intr interrupt is not active after masking,ssi_rxu_intr interrupt is active after masking" bitfld.long 0x0 1. "TXOIS,Transmit FIFO Overflow Interrupt Status 0x1: ssi_txo_intr interrupt is active after masking 0x0: ssi_txo_intr interrupt is not active after masking" "ssi_txo_intr interrupt is not active after masking,ssi_txo_intr interrupt is active after masking" newline bitfld.long 0x0 0. "TXEIS,Transmit FIFO Empty Interrupt Status 0x1: ssi_txe_intr interrupt is active after masking 0x0: ssi_txe_intr interrupt is not active after masking" "ssi_txe_intr interrupt is not active after masking,ssi_txe_intr interrupt is active after masking" line.long 0x4 "RISR,This read-only register reports the status of the DW_apb_ssi interrupts prior to masking. Reset Value: 0x0" hexmask.long 0x4 6.--31. 1. "RSVD_RISR,RISR Reserved bits - Read Only" bitfld.long 0x4 5. "RSVD_MSTIR,MSTIR Reserved field - read-only" "0,1" newline bitfld.long 0x4 4. "RXFIR,Receive FIFO Full Raw Interrupt Status 0x1: ssi_rxf_intr interrupt is active prior to masking 0x0: ssi_rxf_intr interrupt is not active prior to masking" "ssi_rxf_intr interrupt is not active prior to..,ssi_rxf_intr interrupt is active prior to masking" bitfld.long 0x4 3. "RXOIR,Receive FIFO Overflow Raw Interrupt Status 0x1: ssi_rxo_intr interrupt is not active prior to masking 0x0: ssi_rxo_intr interrupt is active prior masking" "ssi_rxo_intr interrupt is active prior masking,ssi_rxo_intr interrupt is not active prior to.." newline bitfld.long 0x4 2. "RXUIR,Receive FIFO Underflow Raw Interrupt Status 0x1: ssi_rxu_intr interrupt is active prior to masking 0x0: ssi_rxu_intr interrupt is not active prior to masking" "ssi_rxu_intr interrupt is not active prior to..,ssi_rxu_intr interrupt is active prior to masking" bitfld.long 0x4 1. "TXOIR,Transmit FIFO Overflow Raw Interrupt Status 0x1: ssi_txo_intr interrupt is active prior masking 0x0: ssi_txo_intr interrupt is not active prior to masking" "ssi_txo_intr interrupt is not active prior to..,ssi_txo_intr interrupt is active prior masking" newline bitfld.long 0x4 0. "TXEIR,Transmit FIFO Empty Raw Interrupt Status 0x1: ssi_txe_intr interrupt is active prior masking 0x0: ssi_txe_intr interrupt is not active prior to masking" "ssi_txe_intr interrupt is not active prior to..,ssi_txe_intr interrupt is active prior masking" line.long 0x8 "TXOICR,Transmit FIFO Overflow Interrupt Clear Register. Reset Value: 0x0" hexmask.long 0x8 1.--31. 1. "RSVD_TXOICR,TXOICR Reserved bits - Read Only" bitfld.long 0x8 0. "TXOICR,Clear Transmit FIFO Overflow Interrupt. This register reflects the status of the interrupt. A read from this register clears the ssi_txo_intr interrupt; writing has no effect." "0,1" line.long 0xC "RXOICR,Receive FIFO Overflow Interrupt Clear Register. Reset Value: 0x0" hexmask.long 0xC 1.--31. 1. "RSVD_RXOICR,RXOICR Reserved bits - Read Only" bitfld.long 0xC 0. "RXOICR,Clear Receive FIFO Overflow Interrupt. This register reflects the status of the interrupt. A read from this register clears the ssi_rxo_intr interrupt; writing has no effect." "0,1" line.long 0x10 "RXUICR,Receive FIFO Underflow Interrupt Clear Register. Reset Value: 0x0" hexmask.long 0x10 1.--31. 1. "RSVD_RXUICR,RXUICR Reserved bits - Read Only" bitfld.long 0x10 0. "RXUICR,Clear Receive FIFO Underflow Interrupt. This register reflects the status of the interrupt. A read from this register clears the ssi_rxu_intr interrupt; writing has no effect." "0,1" line.long 0x14 "MSTICR,Multi-Master Interrupt Clear Register. Reset Value: 0x0" hexmask.long 0x14 1.--31. 1. "RSVD_MSTICR,MSTICR Reserved bits - Read Only" bitfld.long 0x14 0. "MSTICR,Clear Multi-Master Contention Interrupt. This register reflects the status of the interrupt. A read from this register clears the ssi_mst_intr interrupt; writing has no effect." "0,1" line.long 0x18 "ICR,Interrupt Clear Register. Reset Value: 0x0" hexmask.long 0x18 1.--31. 1. "RSVD_ICR,ICR Reserved bits - Read Only" bitfld.long 0x18 0. "ICR,Clear Interrupts. This register is set if any of the interrupts below are active. A read clears the ssi_txo_intr ssi_rxu_intr ssi_rxo_intr and the ssi_mst_intr interrupts. Writing to this register has no effect." "0,1" group.long 0x4C++0xB line.long 0x0 "DMACR,This register is only valid when DW_apb_ssi is configured with a set of DMA Controller interface signals (SSI_HAS_DMA = 1). When DW_apb_ssi is not configured for DMA operation. this register will not exist and writing to the register's address will.." hexmask.long 0x0 2.--31. 1. "RSVD_DMACR,DMACR Reserved bits - Read Only" bitfld.long 0x0 1. "TDMAE,Transmit DMA Enable. This bit enables/disables the transmit FIFO DMA channel. 0x0: Transmit DMA disabled 0x1: Transmit DMA enabled" "Transmit DMA disabled,Transmit DMA enabled" newline bitfld.long 0x0 0. "RDMAE,Receive DMA Enable. This bit enables/disables the receive FIFO DMA channel 0x0: Receive DMA disabled 0x1: Receive DMA enabled" "Receive DMA disabled,Receive DMA enabled" line.long 0x4 "DMATDLR,This register is only valid when the DW_apb_ssi is configured with a set of DMA interface signals (SSI_HAS_DMA = 1). When DW_apb_ssi is not configured for DMA operation. this register will not exist and writing to its address will have no effect;.." hexmask.long 0x4 3.--31. 1. "RSVD_DMATDLR,DMATDLR Reserved bits - Read Only" bitfld.long 0x4 0.--2. "DMATDL,Transmit Data Level. This bit field controls the level at which a DMA request is made by the transmit logic. It is equal to the watermark level; that is the dma_tx_req signal is generated when the number of valid data entries in the transmit FIFO.." "0,1,2,3,4,5,6,7" line.long 0x8 "DMARDLR,This register is only valid when DW_apb_ssi is configured with a set of DMA interface signals (SSI_HAS_DMA = 1). When DW_apb_ssi is not configured for DMA operation. this register will not exist and writing to its address will have no effect;.." hexmask.long 0x8 3.--31. 1. "RSVD_DMARDLR,DMARDLR Reserved bits - Read Only" bitfld.long 0x8 0.--2. "DMARDL,Receive Data Level. This bit field controls the level at which a DMA request is made by the receive logic. The watermark level = DMARDL+1; that is dma_rx_req is generated when the number of valid data entries in the receive FIFO is equal to or.." "0,1,2,3,4,5,6,7" rgroup.long 0x58++0x7 line.long 0x0 "IDR,This register contains the peripherals identification code. which is written into the register at configuration time using coreConsultant. Reset Value: SSI_ID" hexmask.long 0x0 0.--31. 1. "IDCODE,Identification code. The register contains the peripheral's identification code which is written into the register at configuration time using CoreConsultant." line.long 0x4 "SSI_VERSION_ID,This read-only register stores the specific DW_apb_ssi component version. Reset Value: SSI_VERSION_ID" hexmask.long 0x4 0.--31. 1. "SSI_COMP_VERSION,Contains the hex representation of the Synopsys component version. Consists of ASCII value for each number in the version followed by *. For example 32_30_31_2A represents the version 2.01*." repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x4 0x8 0xC 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C ) group.long ($2+0x60)++0x3 line.long 0x0 "DR$1,The DW_apb_ssi data register is a 16/32-bit (depending on SSI_MAX_XFER_SIZE) read/write buffer for the transmit/receive FIFOs. If the configuration parameter SSI_MAX_XFER_SIZE is set to 32. then all 32 bits are valid. otherwise. only 16 bits.." hexmask.long 0x0 0.--31. 1. "DR,Data Register. When writing to this register you must right-justify the data. Read data are automatically right-justified. If SSI_MAX_XFER_SIZE configuration parameter is set to 32 all 32 bits are valid. Otherwise only 16 bits ([15:0]) of the.." repeat.end repeat 16. (list 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1A 0x1B 0x1C 0x1D 0x1E 0x1F )(list 0x40 0x44 0x48 0x4C 0x50 0x54 0x58 0x5C 0x60 0x64 0x68 0x6C 0x70 0x74 0x78 0x7C ) group.long ($2+0x60)++0x3 line.long 0x0 "DR$1,The DW_apb_ssi data register is a 16/32-bit (depending on SSI_MAX_XFER_SIZE) read/write buffer for the transmit/receive FIFOs. If the configuration parameter SSI_MAX_XFER_SIZE is set to 32. then all 32 bits are valid. otherwise. only 16 bits.." hexmask.long 0x0 0.--31. 1. "DR,Data Register. When writing to this register you must right-justify the data. Read data are automatically right-justified. If SSI_MAX_XFER_SIZE configuration parameter is set to 32 all 32 bits are valid. Otherwise only 16 bits ([15:0]) of the.." repeat.end repeat 4. (list 0x20 0x21 0x22 0x23 )(list 0x80 0x84 0x88 0x8C ) group.long ($2+0x60)++0x3 line.long 0x0 "DR$1,The DW_apb_ssi data register is a 16/32-bit (depending on SSI_MAX_XFER_SIZE) read/write buffer for the transmit/receive FIFOs. If the configuration parameter SSI_MAX_XFER_SIZE is set to 32. then all 32 bits are valid. otherwise. only 16 bits.." hexmask.long 0x0 0.--31. 1. "DR,Data Register. When writing to this register you must right-justify the data. Read data are automatically right-justified. If SSI_MAX_XFER_SIZE configuration parameter is set to 32 all 32 bits are valid. Otherwise only 16 bits ([15:0]) of the.." repeat.end rgroup.long 0xFC++0x3 line.long 0x0 "RSVD,RSVD - Reserved address location." hexmask.long 0x0 0.--31. 1. "RESERVED,RSVD 31to0 Reserved address location" tree.end repeat.end tree.end elif (CORENAME()=="CORTEXA55") tree "SPI_SLAVE" repeat 8. (increment 1. 1.) (list ad:0x30380000 ad:0x30390000 ad:0x303A0000 ad:0x303B0000 ad:0x309A0000 ad:0x309B0000 ad:0x309C0000 ad:0x309D0000) tree "SPI$1" base $2 group.long 0x0++0x1F line.long 0x0 "CTRLR0,This register controls the serial data transfer. It is impossible to write to this register when the DW_apb_ssi is enabled. The DW_apb_ssi is enabled and disabled by writing to the SSIENR register. Reset Value: SSI_CTRLR0_RST" hexmask.long.byte 0x0 25.--31. 1. "RSVD_CTRLR0,SSTE Reserved bits - Read Only" bitfld.long 0x0 24. "SSTE,Slave Select Toggle Enable. When operating in SPI mode with clock phase (SCPH) set to 0 this register controls the behavior of the slave select line (ss_*_n) between data frames. If this register field is set to 1 the ss_*_n line will toggle.." "0,1" newline rbitfld.long 0x0 23. "RSVD_CTRLR0_23,CTRLR0_23 Reserved bits - Read Only" "0,1" rbitfld.long 0x0 21.--22. "SPI_FRF,SPI Frame Format: Selects data frame format for Transmitting/Receiving the data Bits only valid when SSI_SPI_MODE is either set to 'Dual' or 'Quad' or 'Octal' mode. When SSI_SPI_MODE is configured for 'Dual Mode' 10/11 combination is reserved." "Standard SPI Frame Format,Dual SPI Frame Format,Quad SPI Frame Format,Octal SPI Frame Format" newline hexmask.long.byte 0x0 16.--20. 1. "DFS_32,Data Frame Size in 32-bit transfer size mode. Used to select the data frame size in 32-bit transfer mode. These bits are only valid when SSI_MAX_XFER_SIZE is configured to 32. When the data frame size is programmed to be less than 32 bits the.." hexmask.long.byte 0x0 12.--15. 1. "CFS,Control Frame Size. Selects the length of the control word for the Microwire frame format. 0x0: 1-bit Control Word 0x1: 2-bit Control Word 0x2: 3-bit Control Word 0x3: 4-bit Control Word 0x4: 5-bit Control Word 0x5: 6-bit Control Word 0x6: 7-bit.." newline bitfld.long 0x0 11. "SRL,Shift Register Loop. Used for testing purposes only. When internally active connects the transmit shift register output to the receive shift register input. Can be used in both serial-slave and serial-master modes. When the DW_apb_ssi is configured.." "Normal mode operation,Test mode: Tx & Rx shift reg connected" rbitfld.long 0x0 10. "RSVD_SLV_OE,SLV_OE Reserved field - Read-only" "0,1" newline bitfld.long 0x0 8.--9. "TMOD,Transfer Mode. Selects the mode of transfer for serial communication. This field does not affect the transfer duplicity. Only indicates whether the receive or transmit data are valid. In transmit-only mode data received from the external device is.." "Transmit & receive,Transmit only mode or Write,Receive only mode or Read,EEPROM Read mode" bitfld.long 0x0 7. "SCPOL,Serial Clock Polarity. Valid when the frame format (FRF) is set to Motorola SPI. Used to select the polarity of the inactive serial clock which is held inactive when the DW_apb_ssi master is not actively transferring data on the serial bus. 0x1:.." "Inactive state of serial clock is low,Inactive state of serial clock is high" newline bitfld.long 0x0 6. "SCPH,Serial Clock Phase. Valid when the frame format (FRF) is set to Motorola SPI. The serial clock phase selects the relationship of the serial clock with the slave select signal. When SCPH = 0 data are captured on the first edge of the serial clock." "Serial clock toggles in middle of first data bit,Serial clock toggles at start of first data bit" bitfld.long 0x0 4.--5. "FRF,Frame Format. Selects which serial protocol transfers the data. 0x0: Motorolla SPI Frame Format 0x2: National Microwire Frame Format 0x3: Reserved value 0x1: Texas Instruments SSP Frame Format" "Motorolla SPI Frame Format,Texas Instruments SSP Frame Format,National Microwire Frame Format,Reserved value" newline hexmask.long.byte 0x0 0.--3. 1. "DFS,Data Frame Size. This register field is only valid when SSI_MAX_XFER_SIZE is configured to 16. If SSI_MAX_XFER_SIZE is configured to 32 then writing to this field will not have any effect. Selects the data frame length. When the data frame size is.." line.long 0x4 "CTRLR1,This register exists only when the DW_apb_ssi is configured as a master device. When the DW_apb_ssi is configured as a serial slave. writing to this location has no effect; reading from this location returns 0. Control register 1 controls the end.." hexmask.long.word 0x4 16.--31. 1. "RSVD_CTRLR1,CTRLR1 Reserved bits - Read Only" hexmask.long.word 0x4 0.--15. 1. "NDF,Number of Data Frames. When TMOD = 10 or TMOD = 11 this register field sets the number of data frames to be continuously received by the DW_apb_ssi. The DW_apb_ssi continues to receive serial data until the number of data frames received is equal.." line.long 0x8 "SSIENR,This register enables and disables the DW_apb_ssi. Reset Value: 0x0" hexmask.long 0x8 1.--31. 1. "RSVD_SSIENR,SSIENR Reserved bits - Read Only" bitfld.long 0x8 0. "SSI_EN,SSI Enable. Enables and disables all DW_apb_ssi operations. When disabled all serial transfers are halted immediately. Transmit and receive FIFO buffers are cleared when the device is disabled. It is impossible to program some of the DW_apb_ssi.." "Disables Serial Transfer,Enables Serial Transfer" line.long 0xC "MWCR,This register controls the direction of the data word for the half-duplex Microwire serial protocol. It is impossible to write to this register when the DW_apb_ssi is enabled. The DW_apb_ssi is enabled and disabled by writing to the SSIENR register." hexmask.long 0xC 3.--31. 1. "RSVD_MWCR,MWCR Reserved bits - Read Only" bitfld.long 0xC 2. "MHS,Microwire Handshaking. Relevant only when the DW_apb_ssi is configured as a serial-master device. When configured as a serial slave this bit field has no functionality. Used to enable and disable the busy/ready handshaking interface for the.." "Handshaking interface is disabled,Handshaking interface is enabled" newline bitfld.long 0xC 1. "MDD,Microwire Control. Defines the direction of the data word when the Microwire serial protocol is used. When this bit is set to 0 the data word is received by the DW_apb_ssi MacroCell from the external serial device. When this bit is set to 1 the.." "SSI receives data,SSI transmits data" bitfld.long 0xC 0. "MWMOD,Microwire Transfer Mode. Defines whether the Microwire transfer is sequential or non-sequential. When sequential mode is used only one control word is needed to transmit or receive a block of data words. When non-sequential mode is used there.." "Non-Sequential Microwire Transfer,Sequential Microwire Transfer" line.long 0x10 "SER,This register is valid only when the DW_apb_ssi is configured as a master device. When the DW_apb_ssi is configured as a serial slave. writing to this location has no effect; reading from this location returns 0. The register enables the individual.." hexmask.long 0x10 4.--31. 1. "RSVD_SER,SER Reserved bits - Read Only" hexmask.long.byte 0x10 0.--3. 1. "SER,Slave Select Enable Flag. Each bit in this register corresponds to a slave select line (ss_x_n) from the DW_apb_ssi master. When a bit in this register is set (1) the corresponding slave select line from the master is activated when a serial.." line.long 0x14 "BAUDR,This register is valid only when the DW_apb_ssi is configured as a master device. When the DW_apb_ssi is configured as a serial slave. writing to this location has no effect; reading from this location returns 0. The register derives the frequency.." hexmask.long.word 0x14 16.--31. 1. "RSVD_BAUDR,BAUDR Reserved bits - Read Only" hexmask.long.word 0x14 0.--15. 1. "SCKDV,SSI Clock Divider. The LSB for this field is always set to 0 and is unaffected by a write operation which ensures an even value is held in this register. If the value is 0 the serial output clock (sclk_out) is disabled. The frequency of the.." line.long 0x18 "TXFTLR,This register controls the threshold value for the transmit FIFO memory. The DW_apb_ssi is enabled and disabled by writing to the SSIENR register. Reset Value: 0x0" hexmask.long 0x18 3.--31. 1. "RSVD_TXFTLR,TXFTLR Reserved bits - Read Only" bitfld.long 0x18 0.--2. "TFT,Transmit FIFO Threshold. Controls the level of entries (or below) at which the transmit FIFO controller triggers an interrupt. The FIFO depth is configurable in the range 2-256; this register is sized to the number of address bits needed to access.." "0,1,2,3,4,5,6,7" line.long 0x1C "RXFTLR,This register controls the threshold value for the receive FIFO memory. The DW_apb_ssi is enabled and disabled by writing to the SSIENR register. Reset Value: 0x0" hexmask.long 0x1C 3.--31. 1. "RSVD_RXFTLR,RXFTLR Reserved bits - Read Only" bitfld.long 0x1C 0.--2. "RFT,Receive FIFO Threshold. Controls the level of entries (or above) at which the receive FIFO controller triggers an interrupt. The FIFO depth is configurable in the range 2-256. This register is sized to the number of address bits needed to access the.." "0,1,2,3,4,5,6,7" rgroup.long 0x20++0xB line.long 0x0 "TXFLR,This register contains the number of valid data entries in the transmit FIFO memory. Reset Value: 0x0" hexmask.long 0x0 4.--31. 1. "RSVD_TXFLR,TXFLR Reserved bits - Read Only" hexmask.long.byte 0x0 0.--3. 1. "TXTFL,Transmit FIFO Level. Contains the number of valid data entries in the transmit FIFO." line.long 0x4 "RXFLR,This register contains the number of valid data entries in the receive FIFO memory. This register can be ready at any time. Reset Value: 0x0" hexmask.long 0x4 4.--31. 1. "RSVD_RXFLR,RXFLR Reserved bits - Read Only" hexmask.long.byte 0x4 0.--3. 1. "RXTFL,Receive FIFO Level. Contains the number of valid data entries in the receive FIFO." line.long 0x8 "SR,This is a read-only register used to indicate the current transfer status. FIFO status. and any transmission/reception errors that may have occurred. The status register may be read at any time. None of the bits in this register request an interrupt." hexmask.long 0x8 7.--31. 1. "RSVD_SR,SR Reserved bits - Read Only" bitfld.long 0x8 6. "DCOL,Data Collision Error. Relevant only when the DW_apb_ssi is configured as a master device. This bit will be set if ss_in_n input is asserted by other master when the DW_apb_ssi master is in the middle of the transfer. This informs the processor that.." "No Error,Transmit Data Collision Error" newline bitfld.long 0x8 5. "RSVD_TXE,TXE Reserved field - read-only" "0,1" bitfld.long 0x8 4. "RFF,Receive FIFO Full. When the receive FIFO is completely full this bit is set. When the receive FIFO contains one or more empty location this bit is cleared. 0x1: Receive FIFO is full 0x0: Receive FIFO is not full" "Receive FIFO is not full,Receive FIFO is full" newline bitfld.long 0x8 3. "RFNE,Receive FIFO Not Empty. Set when the receive FIFO contains one or more entries and is cleared when the receive FIFO is empty. This bit can be polled by software to completely empty the receive FIFO. 0x0: Receive FIFO is empty 0x1: Receive FIFO is.." "Receive FIFO is empty,Receive FIFO is not empty" bitfld.long 0x8 2. "TFE,Transmit FIFO Empty. When the transmit FIFO is completely empty this bit is set. When the transmit FIFO contains one or more valid entries this bit is cleared. This bit field does not request an interrupt. 0x1: Transmit FIFO is empty 0x0: Transmit.." "Transmit FIFO is not empty,Transmit FIFO is empty" newline bitfld.long 0x8 1. "TFNF,Transmit FIFO Not Full. Set when the transmit FIFO contains one or more empty locations and is cleared when the FIFO is full. 0x0: Transmit FIFO is full 0x1: Transmit FIFO is not Full" "Transmit FIFO is full,Transmit FIFO is not Full" bitfld.long 0x8 0. "BUSY,SSI Busy Flag. When set indicates that a serial transfer is in progress; when cleared indicates that the DW_apb_ssi is idle or disabled. 0x1: DW_apb_ssi is actively transferring data 0x0: DW_apb_ssi is idle or disabled" "DW_apb_ssi is idle or disabled,DW_apb_ssi is actively transferring data" group.long 0x2C++0x3 line.long 0x0 "IMR,This read/write reigster masks or enables all interrupts generated by the DW_apb_ssi. When the DW_apb_ssi is configured as a slave device. the MSTIM bit field is not present. This changes the reset value from 0x3F for serial-master configurations to.." hexmask.long 0x0 6.--31. 1. "RSVD_IMR,IMR Reserved bits - Read Only" bitfld.long 0x0 5. "MSTIM,Multi-Master Contention Interrupt Mask. This bit field is not present if the DW_apb_ssi is configured as a serial-slave device. 0x0: ssi_mst_intr interrupt is masked 0x1: ssi_mst_intr interrupt is not masked" "ssi_mst_intr interrupt is masked,ssi_mst_intr interrupt is not masked" newline bitfld.long 0x0 4. "RXFIM,Receive FIFO Full Interrupt Mask 0x0: ssi_rxf_intr interrupt is masked 0x1: ssi_rxf_intr interrupt is not masked" "ssi_rxf_intr interrupt is masked,ssi_rxf_intr interrupt is not masked" bitfld.long 0x0 3. "RXOIM,Receive FIFO Overflow Interrupt Mask 0x0: ssi_rxo_intr interrupt is masked 0x1: ssi_rxo_intr interrupt is not masked" "ssi_rxo_intr interrupt is masked,ssi_rxo_intr interrupt is not masked" newline bitfld.long 0x0 2. "RXUIM,Receive FIFO Underflow Interrupt Mask 0x0: ssi_rxu_intr interrupt is masked 0x1: ssi_rxu_intr interrupt is not masked" "ssi_rxu_intr interrupt is masked,ssi_rxu_intr interrupt is not masked" bitfld.long 0x0 1. "TXOIM,Transmit FIFO Overflow Interrupt Mask 0x0: ssi_txo_intr interrupt is masked 0x1: ssi_txo_intr interrupt is not masked" "ssi_txo_intr interrupt is masked,ssi_txo_intr interrupt is not masked" newline bitfld.long 0x0 0. "TXEIM,Transmit FIFO Empty Interrupt Mask 0x0: ssi_txe_intr interrupt is masked 0x1: ssi_txe_intr interrupt is not masked" "ssi_txe_intr interrupt is masked,ssi_txe_intr interrupt is not masked" rgroup.long 0x30++0x1B line.long 0x0 "ISR,This register reports the status of the DW_apb_ssi interrupts after they have been masked. Reset Value: 0x0" hexmask.long 0x0 6.--31. 1. "RSVD_ISR,ISR Reserved bits - Read Only" bitfld.long 0x0 5. "MSTIS,Multi-Master Contention Interrupt Status. This bit field is not present if the DW_apb_ssi is configured as a serial-slave device. 0x1: ssi_mst_intr interrupt is active after masking 0x0: ssi_mst_intr interrupt not active after masking" "ssi_mst_intr interrupt not active after masking,ssi_mst_intr interrupt is active after masking" newline bitfld.long 0x0 4. "RXFIS,Receive FIFO Full Interrupt Status 0x1: ssi_rxf_intr interrupt is full after masking 0x0: ssi_rxf_intr interrupt is not active after masking" "ssi_rxf_intr interrupt is not active after masking,ssi_rxf_intr interrupt is full after masking" bitfld.long 0x0 3. "RXOIS,Receive FIFO Overflow Interrupt Status 0x1: ssi_rxo_intr interrupt is active after masking 0x0: ssi_rxo_intr interrupt is not active after masking" "ssi_rxo_intr interrupt is not active after masking,ssi_rxo_intr interrupt is active after masking" newline bitfld.long 0x0 2. "RXUIS,Receive FIFO Underflow Interrupt Status 0x1: ssi_rxu_intr interrupt is active after masking 0x0: ssi_rxu_intr interrupt is not active after masking" "ssi_rxu_intr interrupt is not active after masking,ssi_rxu_intr interrupt is active after masking" bitfld.long 0x0 1. "TXOIS,Transmit FIFO Overflow Interrupt Status 0x1: ssi_txo_intr interrupt is active after masking 0x0: ssi_txo_intr interrupt is not active after masking" "ssi_txo_intr interrupt is not active after masking,ssi_txo_intr interrupt is active after masking" newline bitfld.long 0x0 0. "TXEIS,Transmit FIFO Empty Interrupt Status 0x1: ssi_txe_intr interrupt is active after masking 0x0: ssi_txe_intr interrupt is not active after masking" "ssi_txe_intr interrupt is not active after masking,ssi_txe_intr interrupt is active after masking" line.long 0x4 "RISR,This read-only register reports the status of the DW_apb_ssi interrupts prior to masking. Reset Value: 0x0" hexmask.long 0x4 6.--31. 1. "RSVD_RISR,RISR Reserved bits - Read Only" bitfld.long 0x4 5. "MSTIR,Multi-Master Contention Raw Interrupt Status. This bit field is not present if the DW_apb_ssi is configured as a serial-slave device. 0x1: ssi_mst_intr interrupt is active prior masking 0x0: ssi_mst_intr interrupt is not active prior to masking" "ssi_mst_intr interrupt is not active prior to..,ssi_mst_intr interrupt is active prior masking" newline bitfld.long 0x4 4. "RXFIR,Receive FIFO Full Raw Interrupt Status 0x1: ssi_rxf_intr interrupt is active prior to masking 0x0: ssi_rxf_intr interrupt is not active prior to masking" "ssi_rxf_intr interrupt is not active prior to..,ssi_rxf_intr interrupt is active prior to masking" bitfld.long 0x4 3. "RXOIR,Receive FIFO Overflow Raw Interrupt Status 0x1: ssi_rxo_intr interrupt is not active prior to masking 0x0: ssi_rxo_intr interrupt is active prior masking" "ssi_rxo_intr interrupt is active prior masking,ssi_rxo_intr interrupt is not active prior to.." newline bitfld.long 0x4 2. "RXUIR,Receive FIFO Underflow Raw Interrupt Status 0x1: ssi_rxu_intr interrupt is active prior to masking 0x0: ssi_rxu_intr interrupt is not active prior to masking" "ssi_rxu_intr interrupt is not active prior to..,ssi_rxu_intr interrupt is active prior to masking" bitfld.long 0x4 1. "TXOIR,Transmit FIFO Overflow Raw Interrupt Status 0x1: ssi_txo_intr interrupt is active prior masking 0x0: ssi_txo_intr interrupt is not active prior to masking" "ssi_txo_intr interrupt is not active prior to..,ssi_txo_intr interrupt is active prior masking" newline bitfld.long 0x4 0. "TXEIR,Transmit FIFO Empty Raw Interrupt Status 0x1: ssi_txe_intr interrupt is active prior masking 0x0: ssi_txe_intr interrupt is not active prior to masking" "ssi_txe_intr interrupt is not active prior to..,ssi_txe_intr interrupt is active prior masking" line.long 0x8 "TXOICR,Transmit FIFO Overflow Interrupt Clear Register. Reset Value: 0x0" hexmask.long 0x8 1.--31. 1. "RSVD_TXOICR,TXOICR Reserved bits - Read Only" bitfld.long 0x8 0. "TXOICR,Clear Transmit FIFO Overflow Interrupt. This register reflects the status of the interrupt. A read from this register clears the ssi_txo_intr interrupt; writing has no effect." "0,1" line.long 0xC "RXOICR,Receive FIFO Overflow Interrupt Clear Register. Reset Value: 0x0" hexmask.long 0xC 1.--31. 1. "RSVD_RXOICR,RXOICR Reserved bits - Read Only" bitfld.long 0xC 0. "RXOICR,Clear Receive FIFO Overflow Interrupt. This register reflects the status of the interrupt. A read from this register clears the ssi_rxo_intr interrupt; writing has no effect." "0,1" line.long 0x10 "RXUICR,Receive FIFO Underflow Interrupt Clear Register. Reset Value: 0x0" hexmask.long 0x10 1.--31. 1. "RSVD_RXUICR,RXUICR Reserved bits - Read Only" bitfld.long 0x10 0. "RXUICR,Clear Receive FIFO Underflow Interrupt. This register reflects the status of the interrupt. A read from this register clears the ssi_rxu_intr interrupt; writing has no effect." "0,1" line.long 0x14 "MSTICR,Multi-Master Interrupt Clear Register. Reset Value: 0x0" hexmask.long 0x14 1.--31. 1. "RSVD_MSTICR,MSTICR Reserved bits - Read Only" bitfld.long 0x14 0. "MSTICR,Clear Multi-Master Contention Interrupt. This register reflects the status of the interrupt. A read from this register clears the ssi_mst_intr interrupt; writing has no effect." "0,1" line.long 0x18 "ICR,Interrupt Clear Register. Reset Value: 0x0" hexmask.long 0x18 1.--31. 1. "RSVD_ICR,ICR Reserved bits - Read Only" bitfld.long 0x18 0. "ICR,Clear Interrupts. This register is set if any of the interrupts below are active. A read clears the ssi_txo_intr ssi_rxu_intr ssi_rxo_intr and the ssi_mst_intr interrupts. Writing to this register has no effect." "0,1" group.long 0x4C++0xB line.long 0x0 "DMACR,This register is only valid when DW_apb_ssi is configured with a set of DMA Controller interface signals (SSI_HAS_DMA = 1). When DW_apb_ssi is not configured for DMA operation. this register will not exist and writing to the register's address will.." hexmask.long 0x0 2.--31. 1. "RSVD_DMACR,DMACR Reserved bits - Read Only" bitfld.long 0x0 1. "TDMAE,Transmit DMA Enable. This bit enables/disables the transmit FIFO DMA channel. 0x0: Transmit DMA disabled 0x1: Transmit DMA enabled" "Transmit DMA disabled,Transmit DMA enabled" newline bitfld.long 0x0 0. "RDMAE,Receive DMA Enable. This bit enables/disables the receive FIFO DMA channel 0x0: Receive DMA disabled 0x1: Receive DMA enabled" "Receive DMA disabled,Receive DMA enabled" line.long 0x4 "DMATDLR,This register is only valid when the DW_apb_ssi is configured with a set of DMA interface signals (SSI_HAS_DMA = 1). When DW_apb_ssi is not configured for DMA operation. this register will not exist and writing to its address will have no effect;.." hexmask.long 0x4 3.--31. 1. "RSVD_DMATDLR,DMATDLR Reserved bits - Read Only" bitfld.long 0x4 0.--2. "DMATDL,Transmit Data Level. This bit field controls the level at which a DMA request is made by the transmit logic. It is equal to the watermark level; that is the dma_tx_req signal is generated when the number of valid data entries in the transmit FIFO.." "0,1,2,3,4,5,6,7" line.long 0x8 "DMARDLR,This register is only valid when DW_apb_ssi is configured with a set of DMA interface signals (SSI_HAS_DMA = 1). When DW_apb_ssi is not configured for DMA operation. this register will not exist and writing to its address will have no effect;.." hexmask.long 0x8 3.--31. 1. "RSVD_DMARDLR,DMARDLR Reserved bits - Read Only" bitfld.long 0x8 0.--2. "DMARDL,Receive Data Level. This bit field controls the level at which a DMA request is made by the receive logic. The watermark level = DMARDL+1; that is dma_rx_req is generated when the number of valid data entries in the receive FIFO is equal to or.." "0,1,2,3,4,5,6,7" rgroup.long 0x58++0x7 line.long 0x0 "IDR,This register contains the peripherals identification code. which is written into the register at configuration time using coreConsultant. Reset Value: SSI_ID" hexmask.long 0x0 0.--31. 1. "IDCODE,Identification code. The register contains the peripheral's identification code which is written into the register at configuration time using CoreConsultant." line.long 0x4 "SSI_VERSION_ID,This read-only register stores the specific DW_apb_ssi component version. Reset Value: SSI_VERSION_ID" hexmask.long 0x4 0.--31. 1. "SSI_COMP_VERSION,Contains the hex representation of the Synopsys component version. Consists of ASCII value for each number in the version followed by *. For example 32_30_31_2A represents the version 2.01*." repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x4 0x8 0xC 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C ) group.long ($2+0x60)++0x3 line.long 0x0 "DR$1,The DW_apb_ssi data register is a 16/32-bit (depending on SSI_MAX_XFER_SIZE) read/write buffer for the transmit/receive FIFOs. If the configuration parameter SSI_MAX_XFER_SIZE is set to 32. then all 32 bits are valid. otherwise. only 16 bits.." hexmask.long 0x0 0.--31. 1. "DR,Data Register. When writing to this register you must right-justify the data. Read data are automatically right-justified. If SSI_MAX_XFER_SIZE configuration parameter is set to 32 all 32 bits are valid. Otherwise only 16 bits ([15:0]) of the.." repeat.end repeat 16. (list 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1A 0x1B 0x1C 0x1D 0x1E 0x1F )(list 0x40 0x44 0x48 0x4C 0x50 0x54 0x58 0x5C 0x60 0x64 0x68 0x6C 0x70 0x74 0x78 0x7C ) group.long ($2+0x60)++0x3 line.long 0x0 "DR$1,The DW_apb_ssi data register is a 16/32-bit (depending on SSI_MAX_XFER_SIZE) read/write buffer for the transmit/receive FIFOs. If the configuration parameter SSI_MAX_XFER_SIZE is set to 32. then all 32 bits are valid. otherwise. only 16 bits.." hexmask.long 0x0 0.--31. 1. "DR,Data Register. When writing to this register you must right-justify the data. Read data are automatically right-justified. If SSI_MAX_XFER_SIZE configuration parameter is set to 32 all 32 bits are valid. Otherwise only 16 bits ([15:0]) of the.." repeat.end repeat 4. (list 0x20 0x21 0x22 0x23 )(list 0x80 0x84 0x88 0x8C ) group.long ($2+0x60)++0x3 line.long 0x0 "DR$1,The DW_apb_ssi data register is a 16/32-bit (depending on SSI_MAX_XFER_SIZE) read/write buffer for the transmit/receive FIFOs. If the configuration parameter SSI_MAX_XFER_SIZE is set to 32. then all 32 bits are valid. otherwise. only 16 bits.." hexmask.long 0x0 0.--31. 1. "DR,Data Register. When writing to this register you must right-justify the data. Read data are automatically right-justified. If SSI_MAX_XFER_SIZE configuration parameter is set to 32 all 32 bits are valid. Otherwise only 16 bits ([15:0]) of the.." repeat.end rgroup.long 0xFC++0x3 line.long 0x0 "RSVD,RSVD - Reserved address location." hexmask.long 0x0 0.--31. 1. "RSVD,RSVD 31to0 Reserved address location" tree.end repeat.end tree.end tree "SPI_MASTER" repeat 8. (increment 1. 1.) (list ad:0x30380000 ad:0x30390000 ad:0x303A0000 ad:0x303B0000 ad:0x309A0000 ad:0x309B0000 ad:0x309C0000 ad:0x309D0000) tree "SPI$1" base $2 group.long 0x0++0x3 line.long 0x0 "CTRLR0,This register controls the serial data transfer. It is impossible to write to this register when the DW_apb_ssi is enabled. The DW_apb_ssi is enabled and disabled by writing to the SSIENR register. Reset Value: SSI_CTRLR0_RST" hexmask.long.byte 0x0 25.--31. 1. "RSVD_CTRLR0,SSTE Reserved bits - Read Only" bitfld.long 0x0 24. "SSTE,Slave Select Toggle Enable. When operating in SPI mode with clock phase (SCPH) set to 0 this register controls the behavior of the slave select line (ss_*_n) between data frames. If this register field is set to 1 the ss_*_n line will toggle.." "0,1" newline rbitfld.long 0x0 23. "RSVD_CTRLR0_23,CTRLR0_23 Reserved bits - Read Only" "0,1" rbitfld.long 0x0 21.--22. "SPI_FRF,SPI Frame Format: Selects data frame format for Transmitting/Receiving the data Bits only valid when SSI_SPI_MODE is either set to 'Dual' or 'Quad' or 'Octal' mode. When SSI_SPI_MODE is configured for 'Dual Mode' 10/11 combination is reserved." "Standard SPI Frame Format,Dual SPI Frame Format,Quad SPI Frame Format,Octal SPI Frame Format" newline hexmask.long.byte 0x0 16.--20. 1. "DFS_32,Data Frame Size in 32-bit transfer size mode. Used to select the data frame size in 32-bit transfer mode. These bits are only valid when SSI_MAX_XFER_SIZE is configured to 32. When the data frame size is programmed to be less than 32 bits the.." hexmask.long.byte 0x0 12.--15. 1. "CFS,Control Frame Size. Selects the length of the control word for the Microwire frame format. 0x0: 1-bit Control Word 0x1: 2-bit Control Word 0x2: 3-bit Control Word 0x3: 4-bit Control Word 0x4: 5-bit Control Word 0x5: 6-bit Control Word 0x6: 7-bit.." newline bitfld.long 0x0 11. "SRL,Shift Register Loop. Used for testing purposes only. When internally active connects the transmit shift register output to the receive shift register input. Can be used in both serial-slave and serial-master modes. When the DW_apb_ssi is configured.." "Normal mode operation,Test mode: Tx & Rx shift reg connected" bitfld.long 0x0 10. "SLV_OE,Slave Output Enable. Relevant only when the DW_apb_ssi is configured as a serial-slave device. When configured as a serial master this bit field has no functionality. This bit enables or disables the setting of the ssi_oe_n output from the.." "Slave Output is enabled,Slave Output is disabled" newline bitfld.long 0x0 8.--9. "TMOD,Transfer Mode. Selects the mode of transfer for serial communication. This field does not affect the transfer duplicity. Only indicates whether the receive or transmit data are valid. In transmit-only mode data received from the external device is.." "Transmit & receive,Transmit only mode or Write,Receive only mode or Read,EEPROM Read mode" bitfld.long 0x0 7. "SCPOL,Serial Clock Polarity. Valid when the frame format (FRF) is set to Motorola SPI. Used to select the polarity of the inactive serial clock which is held inactive when the DW_apb_ssi master is not actively transferring data on the serial bus. 0x1:.." "Inactive state of serial clock is low,Inactive state of serial clock is high" newline bitfld.long 0x0 6. "SCPH,Serial Clock Phase. Valid when the frame format (FRF) is set to Motorola SPI. The serial clock phase selects the relationship of the serial clock with the slave select signal. When SCPH = 0 data are captured on the first edge of the serial clock." "Serial clock toggles in middle of first data bit,Serial clock toggles at start of first data bit" bitfld.long 0x0 4.--5. "FRF,Frame Format. Selects which serial protocol transfers the data. 0x0: Motorolla SPI Frame Format 0x2: National Microwire Frame Format 0x3: Reserved value 0x1: Texas Instruments SSP Frame Format" "Motorolla SPI Frame Format,Texas Instruments SSP Frame Format,National Microwire Frame Format,Reserved value" newline hexmask.long.byte 0x0 0.--3. 1. "DFS,Data Frame Size. This register field is only valid when SSI_MAX_XFER_SIZE is configured to 16. If SSI_MAX_XFER_SIZE is configured to 32 then writing to this field will not have any effect. Selects the data frame length. When the data frame size is.." group.long 0x8++0x7 line.long 0x0 "SSIENR,This register enables and disables the DW_apb_ssi. Reset Value: 0x0" hexmask.long 0x0 1.--31. 1. "RSVD_SSIENR,SSIENR Reserved bits - Read Only" bitfld.long 0x0 0. "SSI_EN,SSI Enable. Enables and disables all DW_apb_ssi operations. When disabled all serial transfers are halted immediately. Transmit and receive FIFO buffers are cleared when the device is disabled. It is impossible to program some of the DW_apb_ssi.." "Disables Serial Transfer,Enables Serial Transfer" line.long 0x4 "MWCR,This register controls the direction of the data word for the half-duplex Microwire serial protocol. It is impossible to write to this register when the DW_apb_ssi is enabled. The DW_apb_ssi is enabled and disabled by writing to the SSIENR register." hexmask.long 0x4 3.--31. 1. "RSVD_MWCR,MWCR Reserved bits - Read Only" rbitfld.long 0x4 2. "RSVD_MHS,MHS Reserved field - read-only" "0,1" newline bitfld.long 0x4 1. "MDD,Microwire Control. Defines the direction of the data word when the Microwire serial protocol is used. When this bit is set to 0 the data word is received by the DW_apb_ssi MacroCell from the external serial device. When this bit is set to 1 the.." "SSI receives data,SSI transmits data" bitfld.long 0x4 0. "MWMOD,Microwire Transfer Mode. Defines whether the Microwire transfer is sequential or non-sequential. When sequential mode is used only one control word is needed to transmit or receive a block of data words. When non-sequential mode is used there.." "Non-Sequential Microwire Transfer,Sequential Microwire Transfer" group.long 0x18++0x7 line.long 0x0 "TXFTLR,This register controls the threshold value for the transmit FIFO memory. The DW_apb_ssi is enabled and disabled by writing to the SSIENR register. Reset Value: 0x0" hexmask.long 0x0 3.--31. 1. "RSVD_TXFTLR,TXFTLR Reserved bits - Read Only" bitfld.long 0x0 0.--2. "TFT,Transmit FIFO Threshold. Controls the level of entries (or below) at which the transmit FIFO controller triggers an interrupt. The FIFO depth is configurable in the range 2-256; this register is sized to the number of address bits needed to access.." "0,1,2,3,4,5,6,7" line.long 0x4 "RXFTLR,This register controls the threshold value for the receive FIFO memory. The DW_apb_ssi is enabled and disabled by writing to the SSIENR register. Reset Value: 0x0" hexmask.long 0x4 3.--31. 1. "RSVD_RXFTLR,RXFTLR Reserved bits - Read Only" bitfld.long 0x4 0.--2. "RFT,Receive FIFO Threshold. Controls the level of entries (or above) at which the receive FIFO controller triggers an interrupt. The FIFO depth is configurable in the range 2-256. This register is sized to the number of address bits needed to access the.." "0,1,2,3,4,5,6,7" rgroup.long 0x20++0xB line.long 0x0 "TXFLR,This register contains the number of valid data entries in the transmit FIFO memory. Reset Value: 0x0" hexmask.long 0x0 4.--31. 1. "RSVD_TXFLR,TXFLR Reserved bits - Read Only" hexmask.long.byte 0x0 0.--3. 1. "TXTFL,Transmit FIFO Level. Contains the number of valid data entries in the transmit FIFO." line.long 0x4 "RXFLR,This register contains the number of valid data entries in the receive FIFO memory. This register can be ready at any time. Reset Value: 0x0" hexmask.long 0x4 4.--31. 1. "RSVD_RXFLR,RXFLR Reserved bits - Read Only" hexmask.long.byte 0x4 0.--3. 1. "RXTFL,Receive FIFO Level. Contains the number of valid data entries in the receive FIFO." line.long 0x8 "SR,This is a read-only register used to indicate the current transfer status. FIFO status. and any transmission/reception errors that may have occurred. The status register may be read at any time. None of the bits in this register request an interrupt." hexmask.long 0x8 7.--31. 1. "RSVD_SR,SR Reserved bits - Read Only" bitfld.long 0x8 6. "RSVD_DCOL,DCOL Reserved field - read-only" "0,1" newline bitfld.long 0x8 5. "TXE,Transmission Error. Set if the transmit FIFO is empty when a transfer is started. This bit can be set only when the DW_apb_ssi is configured as a slave device. Data from the previous transmission is resent on the txd line. This bit is cleared when.." "No Error,Transmission Error" bitfld.long 0x8 4. "RFF,Receive FIFO Full. When the receive FIFO is completely full this bit is set. When the receive FIFO contains one or more empty location this bit is cleared. 0x1: Receive FIFO is full 0x0: Receive FIFO is not full" "Receive FIFO is not full,Receive FIFO is full" newline bitfld.long 0x8 3. "RFNE,Receive FIFO Not Empty. Set when the receive FIFO contains one or more entries and is cleared when the receive FIFO is empty. This bit can be polled by software to completely empty the receive FIFO. 0x0: Receive FIFO is empty 0x1: Receive FIFO is.." "Receive FIFO is empty,Receive FIFO is not empty" bitfld.long 0x8 2. "TFE,Transmit FIFO Empty. When the transmit FIFO is completely empty this bit is set. When the transmit FIFO contains one or more valid entries this bit is cleared. This bit field does not request an interrupt. 0x1: Transmit FIFO is empty 0x0: Transmit.." "Transmit FIFO is not empty,Transmit FIFO is empty" newline bitfld.long 0x8 1. "TFNF,Transmit FIFO Not Full. Set when the transmit FIFO contains one or more empty locations and is cleared when the FIFO is full. 0x0: Transmit FIFO is full 0x1: Transmit FIFO is not Full" "Transmit FIFO is full,Transmit FIFO is not Full" bitfld.long 0x8 0. "BUSY,SSI Busy Flag. When set indicates that a serial transfer is in progress; when cleared indicates that the DW_apb_ssi is idle or disabled. 0x1: DW_apb_ssi is actively transferring data 0x0: DW_apb_ssi is idle or disabled" "DW_apb_ssi is idle or disabled,DW_apb_ssi is actively transferring data" group.long 0x2C++0x3 line.long 0x0 "IMR,This read/write reigster masks or enables all interrupts generated by the DW_apb_ssi. When the DW_apb_ssi is configured as a slave device. the MSTIM bit field is not present. This changes the reset value from 0x3F for serial-master configurations to.." hexmask.long 0x0 6.--31. 1. "RSVD_IMR,IMR Reserved bits - Read Only" rbitfld.long 0x0 5. "RSVD_MSTIM,MSTIM Reserved field - read-only" "0,1" newline bitfld.long 0x0 4. "RXFIM,Receive FIFO Full Interrupt Mask 0x0: ssi_rxf_intr interrupt is masked 0x1: ssi_rxf_intr interrupt is not masked" "ssi_rxf_intr interrupt is masked,ssi_rxf_intr interrupt is not masked" bitfld.long 0x0 3. "RXOIM,Receive FIFO Overflow Interrupt Mask 0x0: ssi_rxo_intr interrupt is masked 0x1: ssi_rxo_intr interrupt is not masked" "ssi_rxo_intr interrupt is masked,ssi_rxo_intr interrupt is not masked" newline bitfld.long 0x0 2. "RXUIM,Receive FIFO Underflow Interrupt Mask 0x0: ssi_rxu_intr interrupt is masked 0x1: ssi_rxu_intr interrupt is not masked" "ssi_rxu_intr interrupt is masked,ssi_rxu_intr interrupt is not masked" bitfld.long 0x0 1. "TXOIM,Transmit FIFO Overflow Interrupt Mask 0x0: ssi_txo_intr interrupt is masked 0x1: ssi_txo_intr interrupt is not masked" "ssi_txo_intr interrupt is masked,ssi_txo_intr interrupt is not masked" newline bitfld.long 0x0 0. "TXEIM,Transmit FIFO Empty Interrupt Mask 0x0: ssi_txe_intr interrupt is masked 0x1: ssi_txe_intr interrupt is not masked" "ssi_txe_intr interrupt is masked,ssi_txe_intr interrupt is not masked" rgroup.long 0x30++0x1B line.long 0x0 "ISR,This register reports the status of the DW_apb_ssi interrupts after they have been masked. Reset Value: 0x0" hexmask.long 0x0 6.--31. 1. "RSVD_ISR,ISR Reserved bits - Read Only" bitfld.long 0x0 5. "RSVD_MSTIS,MSTIS Reserved field - read-only" "0,1" newline bitfld.long 0x0 4. "RXFIS,Receive FIFO Full Interrupt Status 0x1: ssi_rxf_intr interrupt is full after masking 0x0: ssi_rxf_intr interrupt is not active after masking" "ssi_rxf_intr interrupt is not active after masking,ssi_rxf_intr interrupt is full after masking" bitfld.long 0x0 3. "RXOIS,Receive FIFO Overflow Interrupt Status 0x1: ssi_rxo_intr interrupt is active after masking 0x0: ssi_rxo_intr interrupt is not active after masking" "ssi_rxo_intr interrupt is not active after masking,ssi_rxo_intr interrupt is active after masking" newline bitfld.long 0x0 2. "RXUIS,Receive FIFO Underflow Interrupt Status 0x1: ssi_rxu_intr interrupt is active after masking 0x0: ssi_rxu_intr interrupt is not active after masking" "ssi_rxu_intr interrupt is not active after masking,ssi_rxu_intr interrupt is active after masking" bitfld.long 0x0 1. "TXOIS,Transmit FIFO Overflow Interrupt Status 0x1: ssi_txo_intr interrupt is active after masking 0x0: ssi_txo_intr interrupt is not active after masking" "ssi_txo_intr interrupt is not active after masking,ssi_txo_intr interrupt is active after masking" newline bitfld.long 0x0 0. "TXEIS,Transmit FIFO Empty Interrupt Status 0x1: ssi_txe_intr interrupt is active after masking 0x0: ssi_txe_intr interrupt is not active after masking" "ssi_txe_intr interrupt is not active after masking,ssi_txe_intr interrupt is active after masking" line.long 0x4 "RISR,This read-only register reports the status of the DW_apb_ssi interrupts prior to masking. Reset Value: 0x0" hexmask.long 0x4 6.--31. 1. "RSVD_RISR,RISR Reserved bits - Read Only" bitfld.long 0x4 5. "RSVD_MSTIR,MSTIR Reserved field - read-only" "0,1" newline bitfld.long 0x4 4. "RXFIR,Receive FIFO Full Raw Interrupt Status 0x1: ssi_rxf_intr interrupt is active prior to masking 0x0: ssi_rxf_intr interrupt is not active prior to masking" "ssi_rxf_intr interrupt is not active prior to..,ssi_rxf_intr interrupt is active prior to masking" bitfld.long 0x4 3. "RXOIR,Receive FIFO Overflow Raw Interrupt Status 0x1: ssi_rxo_intr interrupt is not active prior to masking 0x0: ssi_rxo_intr interrupt is active prior masking" "ssi_rxo_intr interrupt is active prior masking,ssi_rxo_intr interrupt is not active prior to.." newline bitfld.long 0x4 2. "RXUIR,Receive FIFO Underflow Raw Interrupt Status 0x1: ssi_rxu_intr interrupt is active prior to masking 0x0: ssi_rxu_intr interrupt is not active prior to masking" "ssi_rxu_intr interrupt is not active prior to..,ssi_rxu_intr interrupt is active prior to masking" bitfld.long 0x4 1. "TXOIR,Transmit FIFO Overflow Raw Interrupt Status 0x1: ssi_txo_intr interrupt is active prior masking 0x0: ssi_txo_intr interrupt is not active prior to masking" "ssi_txo_intr interrupt is not active prior to..,ssi_txo_intr interrupt is active prior masking" newline bitfld.long 0x4 0. "TXEIR,Transmit FIFO Empty Raw Interrupt Status 0x1: ssi_txe_intr interrupt is active prior masking 0x0: ssi_txe_intr interrupt is not active prior to masking" "ssi_txe_intr interrupt is not active prior to..,ssi_txe_intr interrupt is active prior masking" line.long 0x8 "TXOICR,Transmit FIFO Overflow Interrupt Clear Register. Reset Value: 0x0" hexmask.long 0x8 1.--31. 1. "RSVD_TXOICR,TXOICR Reserved bits - Read Only" bitfld.long 0x8 0. "TXOICR,Clear Transmit FIFO Overflow Interrupt. This register reflects the status of the interrupt. A read from this register clears the ssi_txo_intr interrupt; writing has no effect." "0,1" line.long 0xC "RXOICR,Receive FIFO Overflow Interrupt Clear Register. Reset Value: 0x0" hexmask.long 0xC 1.--31. 1. "RSVD_RXOICR,RXOICR Reserved bits - Read Only" bitfld.long 0xC 0. "RXOICR,Clear Receive FIFO Overflow Interrupt. This register reflects the status of the interrupt. A read from this register clears the ssi_rxo_intr interrupt; writing has no effect." "0,1" line.long 0x10 "RXUICR,Receive FIFO Underflow Interrupt Clear Register. Reset Value: 0x0" hexmask.long 0x10 1.--31. 1. "RSVD_RXUICR,RXUICR Reserved bits - Read Only" bitfld.long 0x10 0. "RXUICR,Clear Receive FIFO Underflow Interrupt. This register reflects the status of the interrupt. A read from this register clears the ssi_rxu_intr interrupt; writing has no effect." "0,1" line.long 0x14 "MSTICR,Multi-Master Interrupt Clear Register. Reset Value: 0x0" hexmask.long 0x14 1.--31. 1. "RSVD_MSTICR,MSTICR Reserved bits - Read Only" bitfld.long 0x14 0. "MSTICR,Clear Multi-Master Contention Interrupt. This register reflects the status of the interrupt. A read from this register clears the ssi_mst_intr interrupt; writing has no effect." "0,1" line.long 0x18 "ICR,Interrupt Clear Register. Reset Value: 0x0" hexmask.long 0x18 1.--31. 1. "RSVD_ICR,ICR Reserved bits - Read Only" bitfld.long 0x18 0. "ICR,Clear Interrupts. This register is set if any of the interrupts below are active. A read clears the ssi_txo_intr ssi_rxu_intr ssi_rxo_intr and the ssi_mst_intr interrupts. Writing to this register has no effect." "0,1" group.long 0x4C++0xB line.long 0x0 "DMACR,This register is only valid when DW_apb_ssi is configured with a set of DMA Controller interface signals (SSI_HAS_DMA = 1). When DW_apb_ssi is not configured for DMA operation. this register will not exist and writing to the register's address will.." hexmask.long 0x0 2.--31. 1. "RSVD_DMACR,DMACR Reserved bits - Read Only" bitfld.long 0x0 1. "TDMAE,Transmit DMA Enable. This bit enables/disables the transmit FIFO DMA channel. 0x0: Transmit DMA disabled 0x1: Transmit DMA enabled" "Transmit DMA disabled,Transmit DMA enabled" newline bitfld.long 0x0 0. "RDMAE,Receive DMA Enable. This bit enables/disables the receive FIFO DMA channel 0x0: Receive DMA disabled 0x1: Receive DMA enabled" "Receive DMA disabled,Receive DMA enabled" line.long 0x4 "DMATDLR,This register is only valid when the DW_apb_ssi is configured with a set of DMA interface signals (SSI_HAS_DMA = 1). When DW_apb_ssi is not configured for DMA operation. this register will not exist and writing to its address will have no effect;.." hexmask.long 0x4 3.--31. 1. "RSVD_DMATDLR,DMATDLR Reserved bits - Read Only" bitfld.long 0x4 0.--2. "DMATDL,Transmit Data Level. This bit field controls the level at which a DMA request is made by the transmit logic. It is equal to the watermark level; that is the dma_tx_req signal is generated when the number of valid data entries in the transmit FIFO.." "0,1,2,3,4,5,6,7" line.long 0x8 "DMARDLR,This register is only valid when DW_apb_ssi is configured with a set of DMA interface signals (SSI_HAS_DMA = 1). When DW_apb_ssi is not configured for DMA operation. this register will not exist and writing to its address will have no effect;.." hexmask.long 0x8 3.--31. 1. "RSVD_DMARDLR,DMARDLR Reserved bits - Read Only" bitfld.long 0x8 0.--2. "DMARDL,Receive Data Level. This bit field controls the level at which a DMA request is made by the receive logic. The watermark level = DMARDL+1; that is dma_rx_req is generated when the number of valid data entries in the receive FIFO is equal to or.." "0,1,2,3,4,5,6,7" rgroup.long 0x58++0x7 line.long 0x0 "IDR,This register contains the peripherals identification code. which is written into the register at configuration time using coreConsultant. Reset Value: SSI_ID" hexmask.long 0x0 0.--31. 1. "IDCODE,Identification code. The register contains the peripheral's identification code which is written into the register at configuration time using CoreConsultant." line.long 0x4 "SSI_VERSION_ID,This read-only register stores the specific DW_apb_ssi component version. Reset Value: SSI_VERSION_ID" hexmask.long 0x4 0.--31. 1. "SSI_COMP_VERSION,Contains the hex representation of the Synopsys component version. Consists of ASCII value for each number in the version followed by *. For example 32_30_31_2A represents the version 2.01*." repeat 16. (list 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x4 0x8 0xC 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 0x3C ) group.long ($2+0x60)++0x3 line.long 0x0 "DR$1,The DW_apb_ssi data register is a 16/32-bit (depending on SSI_MAX_XFER_SIZE) read/write buffer for the transmit/receive FIFOs. If the configuration parameter SSI_MAX_XFER_SIZE is set to 32. then all 32 bits are valid. otherwise. only 16 bits.." hexmask.long 0x0 0.--31. 1. "DR,Data Register. When writing to this register you must right-justify the data. Read data are automatically right-justified. If SSI_MAX_XFER_SIZE configuration parameter is set to 32 all 32 bits are valid. Otherwise only 16 bits ([15:0]) of the.." repeat.end repeat 16. (list 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1A 0x1B 0x1C 0x1D 0x1E 0x1F )(list 0x40 0x44 0x48 0x4C 0x50 0x54 0x58 0x5C 0x60 0x64 0x68 0x6C 0x70 0x74 0x78 0x7C ) group.long ($2+0x60)++0x3 line.long 0x0 "DR$1,The DW_apb_ssi data register is a 16/32-bit (depending on SSI_MAX_XFER_SIZE) read/write buffer for the transmit/receive FIFOs. If the configuration parameter SSI_MAX_XFER_SIZE is set to 32. then all 32 bits are valid. otherwise. only 16 bits.." hexmask.long 0x0 0.--31. 1. "DR,Data Register. When writing to this register you must right-justify the data. Read data are automatically right-justified. If SSI_MAX_XFER_SIZE configuration parameter is set to 32 all 32 bits are valid. Otherwise only 16 bits ([15:0]) of the.." repeat.end repeat 4. (list 0x20 0x21 0x22 0x23 )(list 0x80 0x84 0x88 0x8C ) group.long ($2+0x60)++0x3 line.long 0x0 "DR$1,The DW_apb_ssi data register is a 16/32-bit (depending on SSI_MAX_XFER_SIZE) read/write buffer for the transmit/receive FIFOs. If the configuration parameter SSI_MAX_XFER_SIZE is set to 32. then all 32 bits are valid. otherwise. only 16 bits.." hexmask.long 0x0 0.--31. 1. "DR,Data Register. When writing to this register you must right-justify the data. Read data are automatically right-justified. If SSI_MAX_XFER_SIZE configuration parameter is set to 32 all 32 bits are valid. Otherwise only 16 bits ([15:0]) of the.." repeat.end rgroup.long 0xFC++0x3 line.long 0x0 "RSVD,RSVD - Reserved address location." hexmask.long 0x0 0.--31. 1. "RESERVED,RSVD 31to0 Reserved address location" tree.end repeat.end tree.end endif tree.end tree "TM (Tamper Monitor)" sif (CORENAME()=="CORTEXR5F") base ad:0xF1880000 group.long 0x0++0x7 line.long 0x0 "LFSR_CTR,Linear-feadback shift register control for pin tamper" bitfld.long 0x0 4. "LOCK,sticky lock bit to the register" "0,1" bitfld.long 0x0 1.--3. "UPDATE_FREQ,the frequency of the LFSR update 000: 4 cycles 001: 8 cycles 010:16 cycles .... 111:512cycle" "0,1,2,3,4,5,6,7" bitfld.long 0x0 0. "ENABLE,enable LFSR and global counter generate the pattern" "0,1" line.long 0x4 "LFSR_SEED,Linear-feadback shift seed" hexmask.long 0x4 0.--31. 1. "SEED,seed" repeat 6. (list 0x0 0x1 0x2 0x3 0x4 0x5 )(list 0x0 0x4 0x8 0xC 0x10 0x14 ) group.long ($2+0x10)++0x3 line.long 0x0 "PIN_TAMPER_$1,tamper_pin tamper control" bitfld.long 0x0 12. "CLEAR,clear the violation invalid when locked" "0,1" bitfld.long 0x0 9.--11. "COMP_FREQ,how often to compare 000: 4 cycles 001: 8 cycles 010:16 cycles .... 111:512cycle" "0,1,2,3,4,5,6,7" bitfld.long 0x0 8. "DUTY_CYCLE_EN,duty cycle enable/disable" "0,1" bitfld.long 0x0 7. "MASK,mask the violation" "0,1" newline rbitfld.long 0x0 6. "VIOLATION,violation set one to clear" "0,1" bitfld.long 0x0 5. "LOCK,sticky lock bit to the register" "0,1" bitfld.long 0x0 4. "PULL_SEL,pad control: select pull up or down" "0,1" bitfld.long 0x0 3. "PULL_EN,pad control: enable the internal pull up/down" "0,1" bitfld.long 0x0 2. "LEVEL,expected level only when in passive mode" "0,1" newline bitfld.long 0x0 0.--1. "MODE,work mode 00: disable 01: passive mode 10: active output mode 11: active input mode" "disable,passive mode,?,?" repeat.end group.long 0x40++0x3 line.long 0x0 "ON_DIE_TAMPER_0,on_die_tamper(PIN check with feedback) tamper control" bitfld.long 0x0 12. "CLEAR,clear the violation invalid when lock is 1" "0,1" bitfld.long 0x0 9.--11. "COMP_FREQ,how often to compare 000: 4 cycles 001: 8 cycles 010:16 cycles .... 111:512cycle" "0,1,2,3,4,5,6,7" bitfld.long 0x0 8. "DUTY_CYCLE_EN,duty cycle enable/disable" "0,1" bitfld.long 0x0 7. "MASK,mask the violation" "0,1" newline rbitfld.long 0x0 6. "VIOLATION,violation set one to clear" "0,1" bitfld.long 0x0 5. "LOCK,sticky lock bit to the register" "0,1" bitfld.long 0x0 0.--1. "MODE,work mode 00: disable 01: passive mode 10: active output mode 11: active input mode" "disable,passive mode,?,?" group.long 0x50++0x7 line.long 0x0 "CLOCK_TAMPER,clock_tamper(clock checked by other clock) control" hexmask.long.word 0x0 16.--31. 1. "CHECK_TIME,how often to check" bitfld.long 0x0 12. "CLEAR,clear the violation invalid when lock is 1" "0,1" bitfld.long 0x0 9.--11. "PROBE_FREQ,how often to probe 000: 2 cycles 001: 4 cycles 010: 8 cycles .... 111:256cycle" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 7. "MASK,mask the violation" "0,1" rbitfld.long 0x0 6. "VIOLATION,violation set one to clear" "0,1" bitfld.long 0x0 5. "LOCK,sticky lock bit to the register" "0,1" bitfld.long 0x0 0. "EN,work mode 0: disable 1: enable" "disable,enable" line.long 0x4 "CLOCK_TAMPER_THRESHOLD,XTAL clolck count threshold" hexmask.long.word 0x4 16.--31. 1. "HIGH,high threshold" hexmask.long.word 0x4 0.--15. 1. "LOW,low threshold" elif (CORENAME()=="CORTEXA55") base ad:0x31880000 group.long 0x0++0x7 line.long 0x0 "LFSR_CTR,Linear-feadback shift register control for pin tamper" bitfld.long 0x0 4. "LOCK,sticky lock bit to the register" "0,1" bitfld.long 0x0 1.--3. "UPDATE_FREQ,the frequency of the LFSR update 000: 4 cycles 001: 8 cycles 010:16 cycles .... 111:512cycle" "0,1,2,3,4,5,6,7" bitfld.long 0x0 0. "ENABLE,enable LFSR and global counter generate the pattern" "0,1" line.long 0x4 "LFSR_SEED,Linear-feadback shift seed" hexmask.long 0x4 0.--31. 1. "SEED,seed" repeat 6. (list 0x0 0x1 0x2 0x3 0x4 0x5 )(list 0x0 0x4 0x8 0xC 0x10 0x14 ) group.long ($2+0x10)++0x3 line.long 0x0 "PIN_TAMPER_$1,tamper_pin tamper control" bitfld.long 0x0 12. "CLEAR,clear the violation invalid when locked" "0,1" bitfld.long 0x0 9.--11. "COMP_FREQ,how often to compare 000: 4 cycles 001: 8 cycles 010:16 cycles .... 111:512cycle" "0,1,2,3,4,5,6,7" bitfld.long 0x0 8. "DUTY_CYCLE_EN,duty cycle enable/disable" "0,1" bitfld.long 0x0 7. "MASK,mask the violation" "0,1" newline rbitfld.long 0x0 6. "VIOLATION,violation set one to clear" "0,1" bitfld.long 0x0 5. "LOCK,sticky lock bit to the register" "0,1" bitfld.long 0x0 4. "PULL_SEL,pad control: select pull up or down" "0,1" bitfld.long 0x0 3. "PULL_EN,pad control: enable the internal pull up/down" "0,1" bitfld.long 0x0 2. "LEVEL,expected level only when in passive mode" "0,1" newline bitfld.long 0x0 0.--1. "MODE,work mode 00: disable 01: passive mode 10: active output mode 11: active input mode" "disable,passive mode,?,?" repeat.end group.long 0x40++0x3 line.long 0x0 "ON_DIE_TAMPER_0,on_die_tamper(PIN check with feedback) tamper control" bitfld.long 0x0 12. "CLEAR,clear the violation invalid when lock is 1" "0,1" bitfld.long 0x0 9.--11. "COMP_FREQ,how often to compare 000: 4 cycles 001: 8 cycles 010:16 cycles .... 111:512cycle" "0,1,2,3,4,5,6,7" bitfld.long 0x0 8. "DUTY_CYCLE_EN,duty cycle enable/disable" "0,1" bitfld.long 0x0 7. "MASK,mask the violation" "0,1" newline rbitfld.long 0x0 6. "VIOLATION,violation set one to clear" "0,1" bitfld.long 0x0 5. "LOCK,sticky lock bit to the register" "0,1" bitfld.long 0x0 0.--1. "MODE,work mode 00: disable 01: passive mode 10: active output mode 11: active input mode" "disable,passive mode,?,?" group.long 0x50++0x7 line.long 0x0 "CLOCK_TAMPER,clock_tamper(clock checked by other clock) control" hexmask.long.word 0x0 16.--31. 1. "CHECK_TIME,how often to check" bitfld.long 0x0 12. "CLEAR,clear the violation invalid when lock is 1" "0,1" bitfld.long 0x0 9.--11. "PROBE_FREQ,how often to probe 000: 2 cycles 001: 4 cycles 010: 8 cycles .... 111:256cycle" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 7. "MASK,mask the violation" "0,1" rbitfld.long 0x0 6. "VIOLATION,violation set one to clear" "0,1" bitfld.long 0x0 5. "LOCK,sticky lock bit to the register" "0,1" bitfld.long 0x0 0. "EN,work mode 0: disable 1: enable" "disable,enable" line.long 0x4 "CLOCK_TAMPER_THRESHOLD,XTAL clolck count threshold" hexmask.long.word 0x4 16.--31. 1. "HIGH,high threshold" hexmask.long.word 0x4 0.--15. 1. "LOW,low threshold" endif tree.end tree "TMR (Generic Timer)" sif (CORENAME()=="CORTEXR5F") repeat 8. (increment 1. 1.) (list ad:0xF0180000 ad:0xF0190000 ad:0xF08B0000 ad:0xF08C0000 ad:0xF08D0000 ad:0xF08E0000 ad:0xF08F0000 ad:0xF0900000) tree "TMR$1" base $2 group.long 0x0++0xB line.long 0x0 "INT_STA,This register provides interrupt status." bitfld.long 0x0 23. "FIFO_D_OVERRUN,When set indicates FIFO D is overrrun in dma mode" "0,1" newline bitfld.long 0x0 22. "FIFO_C_OVERRUN,When set indicates FIFO C is overrrun in dma mode" "0,1" bitfld.long 0x0 21. "FIFO_B_OVERRUN,When set indicates FIFO B is overrrun in dma mode" "0,1" newline bitfld.long 0x0 20. "FIFO_A_OVERRUN,When set indicates FIFO A is overrrun in dma mode" "0,1" bitfld.long 0x0 19. "FIFO_D_UNDERRUN,When set indicates FIFO D is underrun in dma mode" "0,1" newline bitfld.long 0x0 18. "FIFO_C_UNDERRUN,When set indicates FIFO C is underrun in dma mode" "0,1" bitfld.long 0x0 17. "FIFO_B_UNDERRUN,When set indicates FIFO B is underrun in dma mode" "0,1" newline bitfld.long 0x0 16. "FIFO_A_UNDERRUN,When set indicates FIFO A is underrun in dma mode" "0,1" newline bitfld.long 0x0 14. "CNT_LOCAL_A_UNF,When set indicates CNT_LOCAL_A is underflow" "0,1" bitfld.long 0x0 13. "CNT_LOCAL_D_OVF,When set indicates CNT_LOCAL_D is overflow" "0,1" newline bitfld.long 0x0 12. "CNT_LOCAL_C_OVF,When set indicates CNT_LOCAL_C is overflow" "0,1" bitfld.long 0x0 11. "CNT_LOCAL_B_OVF,When set indicates CNT_LOCAL_B is overflow" "0,1" newline bitfld.long 0x0 10. "CNT_LOCAL_A_OVF,When set indicates CNT_LOCAL_A is overflow" "0,1" bitfld.long 0x0 9. "CNT_G1_OVF,When set indicates CNT_G1 is overflow" "0,1" newline bitfld.long 0x0 8. "CNT_G0_OVF,When set indicates CNT_G0 overflow" "0,1" bitfld.long 0x0 7. "CMP_D,When set indicates compare D event happens" "0,1" newline bitfld.long 0x0 6. "CMP_C,When set indicates compare C event happens" "0,1" bitfld.long 0x0 5. "CMP_B,When set indicates compare B event happens" "0,1" newline bitfld.long 0x0 4. "CMP_A,When set indicates compare A event happens" "0,1" bitfld.long 0x0 3. "CPT_D,When set indicates capture D event happens" "0,1" newline bitfld.long 0x0 2. "CPT_C,When set indicates capture C event happens" "0,1" bitfld.long 0x0 1. "CPT_B,When set indicates capture B event happens" "0,1" newline bitfld.long 0x0 0. "CPT_A,When set indicates capture A event happens" "0,1" line.long 0x4 "INT_STA_EN,This register provides enable bits for interrupt status." bitfld.long 0x4 23. "FIFO_D_OVERRUN,FIFO D overrun interrput status enable" "0,1" newline bitfld.long 0x4 22. "FIFO_C_OVERRUN,FIFO C overrun interrput status enable" "0,1" bitfld.long 0x4 21. "FIFO_B_OVERRUN,FIFO B overrun interrput status enable" "0,1" newline bitfld.long 0x4 20. "FIFO_A_OVERRUN,FIFO A overrun interrput status enable" "0,1" bitfld.long 0x4 19. "FIFO_D_UNDERRUN,FIFO D underrun interrput status enable" "0,1" newline bitfld.long 0x4 18. "FIFO_C_UNDERRUN,FIFO C underrun interrput status enable" "0,1" bitfld.long 0x4 17. "FIFO_B_UNDERRUN,FIFO B underrun interrput status enable" "0,1" newline bitfld.long 0x4 16. "FIFO_A_UNDERRUN,FIFO A underrun interrput status enable" "0,1" newline bitfld.long 0x4 14. "CNT_LOCAL_A_UNF,CNT_LOCAL_A underflow interrupt status enable" "0,1" bitfld.long 0x4 13. "CNT_LOCAL_D_OVF,CNT_LOCAL_D overflow interrupt status enable" "0,1" newline bitfld.long 0x4 12. "CNT_LOCAL_C_OVF,CNT_LOCAL_C overflow interrupt status enable" "0,1" bitfld.long 0x4 11. "CNT_LOCAL_B_OVF,CNT_LOCAL_B overflow interrupt status enable" "0,1" newline bitfld.long 0x4 10. "CNT_LOCAL_A_OVF,CNT_LOCAL_A overflow interrupt status enable" "0,1" bitfld.long 0x4 9. "CNT_G1_OVF,CNT_G1 overflow interrupt status enable" "0,1" newline bitfld.long 0x4 8. "CNT_G0_OVF,CNT_G0 overflow interrupt status enable" "0,1" bitfld.long 0x4 7. "CMP_D,Compare D event interrupt status enable" "0,1" newline bitfld.long 0x4 6. "CMP_C,Compare C event interrupt status enable" "0,1" bitfld.long 0x4 5. "CMP_B,Compare B event interrupt status enable" "0,1" newline bitfld.long 0x4 4. "CMP_A,Compare A event interrupt status enable" "0,1" bitfld.long 0x4 3. "CPT_D,Capture D event interrupt status enable" "0,1" newline bitfld.long 0x4 2. "CPT_C,Capture C event interrupt status enable" "0,1" bitfld.long 0x4 1. "CPT_B,Capture B event interrupt status enable" "0,1" newline bitfld.long 0x4 0. "CPT_A,Capture A event interrupt status enable" "0,1" line.long 0x8 "INT_SIG_EN,This register provides enable bits for interrupt signal." bitfld.long 0x8 23. "FIFO_D_OVERRUN,FIFO D overrun interrupt signal enable" "0,1" newline bitfld.long 0x8 22. "FIFO_C_OVERRUN,FIFO C overrun interrupt signal enable" "0,1" bitfld.long 0x8 21. "FIFO_B_OVERRUN,FIFO B overrun interrupt signal enable" "0,1" newline bitfld.long 0x8 20. "FIFO_A_OVERRUN,FIFO A overrun interrupt signal enable" "0,1" bitfld.long 0x8 19. "FIFO_D_UNDERRUN,FIFO D underrun interrupt signal enable" "0,1" newline bitfld.long 0x8 18. "FIFO_C_UNDERRUN,FIFO C underrun interrupt signal enable" "0,1" bitfld.long 0x8 17. "FIFO_B_UNDERRUN,FIFO B underrun interrupt signal enable" "0,1" newline bitfld.long 0x8 16. "FIFO_A_UNDERRUN,FIFO A underrun interrupt signal enable" "0,1" newline bitfld.long 0x8 14. "CNT_LOCAL_A_UNF,CNT_LOCAL_A underflow interrupt signal enable" "0,1" bitfld.long 0x8 13. "CNT_LOCAL_D_OVF,CNT_LOCAL_D overflow interrupt signal enable" "0,1" newline bitfld.long 0x8 12. "CNT_LOCAL_C_OVF,CNT_LOCAL_C overflow interrupt signal enable" "0,1" bitfld.long 0x8 11. "CNT_LOCAL_B_OVF,CNT_LOCAL_B overflow interrupt signal enable" "0,1" newline bitfld.long 0x8 10. "CNT_LOCAL_A_OVF,CNT_LOCAL_A overflow interrupt signal enable" "0,1" bitfld.long 0x8 9. "CNT_G1_OVF,CNT_G1 overflow interrupt signal enable" "0,1" newline bitfld.long 0x8 8. "CNT_G0_OVF,CNT_G0 overflow interrupt signal enable" "0,1" bitfld.long 0x8 7. "CMP_D,Compare D event interrupt signal enable" "0,1" newline bitfld.long 0x8 6. "CMP_C,Compare C event interrupt signal enable" "0,1" bitfld.long 0x8 5. "CMP_B,Compare B event interrupt signal enable" "0,1" newline bitfld.long 0x8 4. "CMP_A,Compare A event interrupt signal enable" "0,1" bitfld.long 0x8 3. "CPT_D,Capture D event interrupt signal enable" "0,1" newline bitfld.long 0x8 2. "CPT_C,Capture C event interrupt signal enable" "0,1" bitfld.long 0x8 1. "CPT_B,Capture B event interrupt signal enable" "0,1" newline bitfld.long 0x8 0. "CPT_A,Capture A event interrupt signal enable" "0,1" group.long 0x10++0xB line.long 0x0 "DMA_CTRL,This register provides the control setting for DMA mode" hexmask.long.byte 0x0 28.--31. 1. "CHN_D_WML,Water mark level for channel D FIFO. When channnel D FIFO is used for capture function dma D request will be asserted if data number in FIFO is greater than or equal to CHN_D_WML. When channnel D FIFO is used for compare function dma D.." hexmask.long.byte 0x0 24.--27. 1. "CHN_C_WML,Water mark level for channel C FIFO. When channnel C FIFO is used for capture function dma C request will be asserted if data number in FIFO is greater than or equal to CHN_C_WML. When channnel C FIFO is used for compare function dma C.." newline hexmask.long.byte 0x0 20.--23. 1. "CHN_B_WML,Water mark level for channel B FIFO. When channnel B FIFO is used for capture function dma B request will be asserted if data number in FIFO is greater than or equal to CHN_B_WML. When channnel A FIFO is used for compare function dma A.." hexmask.long.byte 0x0 16.--19. 1. "CHN_A_WML,Water mark level for channel A FIFO. When channnel A FIFO is used for capture function dma A request will be asserted if data number in FIFO is greater than or equal to CHN_A_WML. When channnel A FIFO is used for compare function dma A.." newline bitfld.long 0x0 13. "CNT_OVF_SEL,Select DMA requrest for CNT_G0 or CNT_G1 overflow. 1: Use to update CNT_G1 overflow register 0: Use to update CNT_G0 overflow register." "Use to update CNT_G0 overflow register,Use to update CNT_G1 overflow register" newline bitfld.long 0x0 11.--12. "CHN_D_SEL,Select dma request working for CNT_LOCAL_D overflow or CAPTURE D/COMPARE D channel 1x: Use for CNT_LOCAL_D timer 01: Use for capture channel D. 00: Use for compare channel D." "Use for compare channel D,Use for capture channel D,?,?" bitfld.long 0x0 9.--10. "CHN_C_SEL,Select dma request working for CNT_LOCAL_C overflow or CAPTURE C/COMPARE C channel 1x: Use for CNT_LOCAL_C timer 01: Use for capture channel C. 00: Use for compare channel C." "Use for compare channel C,Use for capture channel C,?,?" newline bitfld.long 0x0 7.--8. "CHN_B_SEL,Select dma request working for CNT_LOCAL_B overflow or CAPTURE B/COMPARE B channel 1x: Use for CNT_LOCAL_B timer 01: Use for capture channel B. 00: Use for compare channel B." "Use for compare channel B,Use for capture channel B,?,?" bitfld.long 0x0 5.--6. "CHN_A_SEL,Select dma request working for CNT_LOCAL_A overflow or CAPTURE A/COMPARE A channel 1x: Use for CNT_LOCAL_A timer 01: Use for capture channel A. 00: Use for compare channel A." "Use for compare channel A,Use for capture channel A,?,?" newline bitfld.long 0x0 4. "CNT_OVF_EN,Enable dma request for CNT_G0 or CNT_G1 overflow." "0,1" bitfld.long 0x0 3. "CHN_D_EN,Enable dma request for CNT_LOCAL_D overflow or CAPTURE D/COMPARE D channel according to channel D FIFO WML." "0,1" newline bitfld.long 0x0 2. "CHN_C_EN,Enable dma request for CNT_LOCAL_C overflow or CAPTURE C/COMPARE C channel according to channel C FIFO WML." "0,1" bitfld.long 0x0 1. "CHN_B_EN,Enable dma request for CNT_LOCAL_B overflow or CAPTURE B/COMPARE B channel according to channel B FIFO WML." "0,1" newline bitfld.long 0x0 0. "CHN_A_EN,Enable dma request for CNT_LOCAL_A overflow or CAPTURE A/COMPARE A channel according to channle A FIFO WML." "0,1" line.long 0x4 "DMA_SIG_MASK,The register contains the masks for dma request hardware output." bitfld.long 0x4 4. "CNT_OVF,Mask timer overflow dma request hardware output" "0,1" newline bitfld.long 0x4 3. "CHN_D,Mask channel D dma request hardware output" "0,1" bitfld.long 0x4 2. "CHN_C,Mask channel C dma request hardware output" "0,1" newline bitfld.long 0x4 1. "CHN_B,Mask channel B dma request hardware output" "0,1" bitfld.long 0x4 0. "CHN_A,Mask channel A dma request hardware output" "0,1" line.long 0x8 "SW_RST,This register controls software reset" bitfld.long 0x8 19. "CHN_D_SOFT_RST,Reset channel D FIFO.Write 1 to reset channel D FIFO. Then wait for one timer clock period. Finally write 0 to deassert reset." "0,1" newline bitfld.long 0x8 18. "CHN_C_SOFT_RST,Reset channel C FIFO.Write 1 to reset channel C FIFO. Then wait for one timer clock period. Finally write 0 to deassert reset." "0,1" bitfld.long 0x8 17. "CHN_B_SOFT_RST,Reset channel B FIFO. Write 1 to reset channel B FIFO. Then wait for one timer clock period. Finally write 0 to deassert reset." "0,1" newline bitfld.long 0x8 16. "CHN_A_SOFT_RST,Reset channel A FIFO. Write 1 to reset channel A FIFO. Then wait for one timer clock period. Finally write 0 to deassert reset." "0,1" rgroup.long 0x1C++0x3 line.long 0x0 "FIFO_STA,This register provides FIFO status information." bitfld.long 0x0 31. "FIFO_ERR_D,Indicates FIFO D is underrun or overrun." "0,1" hexmask.long.byte 0x0 26.--30. 1. "FIFO_ENTRIES_D,Indicates data numbers of FIFO D." newline bitfld.long 0x0 25. "FIFO_EMPTY_D,Indicates FIFO D is empty." "0,1" bitfld.long 0x0 24. "FIFO_FULL_D,Indicates FIFO D is full." "0,1" newline bitfld.long 0x0 23. "FIFO_ERR_C,Indicates FIFO C is underrun or overrun." "0,1" hexmask.long.byte 0x0 18.--22. 1. "FIFO_ENTRIES_C,Indicates data numbers of FIFO C." newline bitfld.long 0x0 17. "FIFO_EMPTY_C,Indicates FIFO C is empty." "0,1" bitfld.long 0x0 16. "FIFO_FULL_C,Indicates FIFO C is full." "0,1" newline bitfld.long 0x0 15. "FIFO_ERR_B,Indicates FIFO B is underrun or overrun." "0,1" hexmask.long.byte 0x0 10.--14. 1. "FIFO_ENTRIES_B,Indicates data numbers of FIFO B." newline bitfld.long 0x0 9. "FIFO_EMPTY_B,Indicates FIFO B is empty." "0,1" bitfld.long 0x0 8. "FIFO_FULL_B,Indicates FIFO B is full." "0,1" newline bitfld.long 0x0 7. "FIFO_ERR_A,Indicates FIFO A is underrun or overrun." "0,1" hexmask.long.byte 0x0 2.--6. 1. "FIFO_ENTRIES_A,Indicates data numbers of FIFO A." newline bitfld.long 0x0 1. "FIFO_EMPTY_A,Indicates FIFO A is empty." "0,1" bitfld.long 0x0 0. "FIFO_FULL_A,Indicates FIFO A is full." "0,1" group.long 0x20++0x1F line.long 0x0 "TIM_CLK_CONFIG,This register provides clock configuration for timer clock" bitfld.long 0x0 16.--17. "SRC_CLK_SEL,Clock source select. 00: High frequency(HF) clock update to 400mhz. 01: Alternative High frequency(AHF) clock update to 400mhz. 10: Low frenquency(LF) clock typically from 24mhz OSC. 11: Low power(LP) clock typically from low speed on.." "High frequency,Alternative High frequency,?,?" newline hexmask.long.word 0x0 0.--15. 1. "DIV_NUM,Divider number for timer clock." line.long 0x4 "CNT_CONFIG,Timer counter configuration for CNT_G0.CNT_G1 and CNT_LOCAL timer." bitfld.long 0x4 16. "INDEX_EDGE_SEL,Select which edge of INDEX(cpt_d) can reset CNT_LOCAL_A timer. 1. Negedge 0. Posedge" "0,1" newline bitfld.long 0x4 15. "HOME_EDGE_SEL,Select which edge of HOME(cpt_c) can reset CNT_LOCAL_A timer. 1. Negedge 0. Posedge" "0,1" bitfld.long 0x4 14. "INDEX_RST_EN,Enable CNT_LOCAL_A timer can be reset by INDEX(cpt_flt_d) singal." "0,1" newline bitfld.long 0x4 13. "HOME_RST_EN,Enable CNT_LOCAL_A timer can be reset by HOME(cpt_flt_c) singal." "0,1" bitfld.long 0x4 12. "QUADRATURE_MODE,Enable quadrature mode for CNT_LOCAL_A timer" "0,1" newline bitfld.long 0x4 11. "LOCAL_D_RST_EN,When this bit is set CNT_LOCAL_D will be reset by compare event or first capture event." "0,1" bitfld.long 0x4 10. "LOCAL_C_RST_EN,When this bit is set CNT_LOCAL_C will be reset by compare event or first capture event." "0,1" newline bitfld.long 0x4 9. "LOCAL_B_RST_EN,When this bit is set CNT_LOCAL_B will be reset by compare event or first capture event." "0,1" bitfld.long 0x4 8. "LOCAL_A_RST_EN,When this bit is set CNT_LOCAL_A will be reset by compare event or first capture event." "0,1" newline bitfld.long 0x4 6. "CASCADE_MODE,When this bit is set CNT_G1 only increase when CNT_G0 is overflowed. In this setup CNT_G0 can work as a 64 bit timer if CNT_G0_OVF_VAL is 32'hffffffff." "0,1" newline bitfld.long 0x4 5. "CNT_LOCAL_D_RLD,SW force reload for CNT_LOCAL_D. After this bit is set CNT_LOCAL_D will be reset to 0 and new OVF_VAL in CNT_LOCAL_D_OVF will be effective. Then this bit will be auto cleared by HW." "0,1" bitfld.long 0x4 4. "CNT_LOCAL_C_RLD,SW force reload for CNT_LOCAL_C. After this bit is set CNT_LOCAL_C will be reset to 0 and new OVF_VAL in CNT_LOCAL_C_OVF will be effective. Then this bit will be auto cleared by HW." "0,1" newline bitfld.long 0x4 3. "CNT_LOCAL_B_RLD,SW force reload for CNT_LOCAL_B. After this bit is set CNT_LOCAL_B will be reset to 0 and new OVF_VAL in CNT_LOCAL_B_OVF will be effective. Then this bit will be auto cleared by HW." "0,1" bitfld.long 0x4 2. "CNT_LOCAL_A_RLD,SW force reload for CNT_LOCAL_A. After this bit is set CNT_LOCAL_A will be reset to 0 and new OVF_VAL in CNT_LOCAL_A_OVF will be effective. Then this bit will be auto cleared by HW." "0,1" newline bitfld.long 0x4 1. "CNT_G1_RLD,SW force reload for CNT_G1. After this bit is set CNT_G1 will be reset to 0 and new OVF_VAL in CNT_G1 will be effective. Then this bit will be auto cleared by HW." "0,1" bitfld.long 0x4 0. "CNT_G0_RLD,SW force reload for CNT_G0. After this bit is set CNT_G0 will be reset to 0 and new OVF_VAL in CNT_G0 will be effective. Then this bit will be auto cleared by HW." "0,1" line.long 0x8 "CNT_G0_OVF,This register is used to update overflow value for CNT_G0." hexmask.long 0x8 0.--31. 1. "OVF_VAL,When CNT_G0 reach OVF_VAL it will be reset to 0. After write new value new OVF_VAL value will not be effective until one overrflow happens or CNT_G0_RLD in CNT_CONFIG register is set" line.long 0xC "CNT_G1_OVF,This register is used to update overflow value for CNT_G1." hexmask.long 0xC 0.--31. 1. "OVF_VAL,When CNT_G1 reach OVF_VAL it will be reset to 0. After write new value new OVF_VAL value will not be effective until one overrflow happens or CNT_G1_RLD in CNT_CONFIG register is set" line.long 0x10 "CNT_LOCAL_A_OVF,This register is used to update overflow value for CNT_LOCAL_A." hexmask.long 0x10 0.--31. 1. "OVF_VAL,When CNT_LOCAL_A reach OVF_VAL it will be reset to 0. After write new value new OVF_VAL value will not be effective until one overrflow happens or CNT_LOCAL_A_RLD in CNT_CONFIG register is set" line.long 0x14 "CNT_LOCAL_B_OVF,This register is used to update overflow value for CNT_LOCAL_B." hexmask.long 0x14 0.--31. 1. "OVF_VAL,When CNT_LOCAL_B reach OVF_VAL it will be reset to 0. After write new value new OVF_VAL value will not be effective until one overrflow happens or CNT_LOCAL_B_RLD in CNT_CONFIG register is set" line.long 0x18 "CNT_LOCAL_C_OVF,This register is used to update overflow value for CNT_LOCAL_C." hexmask.long 0x18 0.--31. 1. "OVF_VAL,When CNT_LOCAL_C reach OVF_VAL it will be reset to 0. After write new value new OVF_VAL value will not be effective until one overrflow happens or CNT_LOCAL_C_RLD in CNT_CONFIG register is set" line.long 0x1C "CNT_LOCAL_D_OVF,This register is used to update overflow value for CNT_LOCAL_D." hexmask.long 0x1C 0.--31. 1. "OVF_VAL,When CNT_LOCAL_D reach OVF_VAL it will be reset to 0. After write new value new OVF_VAL value will not be effective until one overrflow happens or CNT_LOCAL_D_RLD in CNT_CONFIG register is set" rgroup.long 0x40++0x17 line.long 0x0 "CNT_G0,CNT_G0 timer counter" hexmask.long 0x0 0.--31. 1. "TIMER,Timer counter value" line.long 0x4 "CNT_G1,CNT_G1 timer counter" hexmask.long 0x4 0.--31. 1. "TIMER,Timer counter value" line.long 0x8 "CNT_LOCAL_A,CNT_LOCAL_A timer counter" hexmask.long 0x8 0.--31. 1. "TIMER,Timer counter value" line.long 0xC "CNT_LOCAL_B,CNT_LOCAL_B timer counter" hexmask.long 0xC 0.--31. 1. "TIMER,Timer counter value" line.long 0x10 "CNT_LOCAL_C,CNT_LOCAL_C timer counter" hexmask.long 0x10 0.--31. 1. "TIMER,Timer counter value" line.long 0x14 "CNT_LOCAL_D,CNT_LOCAL_D timer counter" hexmask.long 0x14 0.--31. 1. "TIMER,Timer counter value" group.long 0x60++0xB line.long 0x0 "CMP_A_VAL_UPT,Indicate Software has updated compare value for channel A. Hardware will auto update all the compare value to shadow register. Use for no-DMA mode." bitfld.long 0x0 0. "UPT,Indicate software has updated compare value." "0,1" line.long 0x4 "CMP0_A_VAL,This reigister provides compare 0 value for compare channel A in no-DMA mode." hexmask.long 0x4 0.--31. 1. "DATA,Compare value." line.long 0x8 "CMP1_A_VAL,This reigister provides compare 1 value for compare channel A in no-DMA mode." hexmask.long 0x8 0.--31. 1. "DATA,Compare value." group.long 0x70++0xB line.long 0x0 "CMP_B_VAL_UPT,Indicate Software has updated compare value for channel B. Hardware will auto update all the compare value to shadow register. Use for no-DMA mode." bitfld.long 0x0 0. "UPT,Indicate software has updated compare value." "0,1" line.long 0x4 "CMP0_B_VAL,This reigister provides compare 0 value for compare channel B in no-DMA mode." hexmask.long 0x4 0.--31. 1. "DATA,Compare value." line.long 0x8 "CMP1_B_VAL,This reigister provides compare 1 value for compare channel B in no-DMA mode." hexmask.long 0x8 0.--31. 1. "DATA,Compare value." group.long 0x80++0xB line.long 0x0 "CMP_C_VAL_UPT,Indicate Software has updated compare value for channel C. Hardware will auto update all the compare value to shadow register. Use for no-DMA mode." bitfld.long 0x0 0. "UPT,Indicate software has updated compare value." "0,1" line.long 0x4 "CMP0_C_VAL,This reigister provides compare 0 value for compare channel C in no-DMA mode." hexmask.long 0x4 0.--31. 1. "DATA,Compare value." line.long 0x8 "CMP1_C_VAL,This reigister provides compare 1 value for compare channel C in no-DMA mode." hexmask.long 0x8 0.--31. 1. "DATA,Compare value." group.long 0x90++0xB line.long 0x0 "CMP_D_VAL_UPT,Indicate Software has updated compare value for channel D. Hardware will auto update all the compare value to shadow register. Use for no-DMA mode." bitfld.long 0x0 0. "UPT,Indicate software has updated compare value." "0,1" line.long 0x4 "CMP0_D_VAL,This reigister provides compare 0 value for compare channel D in no-DMA mode." hexmask.long 0x4 0.--31. 1. "DATA,Compare value." line.long 0x8 "CMP1_D_VAL,This reigister provides compare 1 value for compare channel D in no-DMA mode." hexmask.long 0x8 0.--31. 1. "DATA,Compare value." group.long 0xA0++0x4F line.long 0x0 "FIFO_A,This register provides FIFO entry for capture and compare channel A." hexmask.long 0x0 0.--31. 1. "DATA,FIFO entry" line.long 0x4 "FIFO_B,This register provides FIFO entry for capture and compare channel B." hexmask.long 0x4 0.--31. 1. "DATA,FIFO entry" line.long 0x8 "FIFO_C,This register provides FIFO entry for capture and compare channel C." hexmask.long 0x8 0.--31. 1. "DATA,FIFO entry" line.long 0xC "FIFO_D,This register provides FIFO entry for capture and compare channel D." hexmask.long 0xC 0.--31. 1. "DATA,FIFO entry" line.long 0x10 "CNT_G0_INIT,This register is used to update CNT_G0 initial value." hexmask.long 0x10 0.--31. 1. "VALUE,Write this register can directly update time counter value." line.long 0x14 "CNT_G1_INIT,This register is used to update CNT_G1 initial value." hexmask.long 0x14 0.--31. 1. "VALUE,Write this register can directly update time counter value." line.long 0x18 "CNT_LOCAL_A_INIT,This register is used to update CNT_LOCAL_A initial value." hexmask.long 0x18 0.--31. 1. "VALUE,Write this register can directly update time counter value." line.long 0x1C "CNT_LOCAL_B_INIT,This register is used to update CNT_LOCAL_B initial value." hexmask.long 0x1C 0.--31. 1. "VALUE,Write this register can directly update time counter value." line.long 0x20 "CNT_LOCAL_C_INIT,This register is used to update CNT_LOCAL_C initial value." hexmask.long 0x20 0.--31. 1. "VALUE,Write this register can directly update time counter value." line.long 0x24 "CNT_LOCAL_D_INIT,This register is used to update CNT_LOCAL_D initial value." hexmask.long 0x24 0.--31. 1. "VALUE,Write this register can directly update time counter value." line.long 0x28 "CPT_FLT,This reigster provides filter setting for capture input." hexmask.long.byte 0x28 28.--31. 1. "FLT_BAND_WID_D,Filter bandwith for capture channel D. 0~15 indicate 2~17 clock cycles width" newline bitfld.long 0x28 24. "FLT_DIS_D,When this bit is set filter is disabled for capture channel D." "0,1" hexmask.long.byte 0x28 20.--23. 1. "FLT_BAND_WID_C,Filter bandwith for capture channel C. 0~15 indicate 2~17 clock cycles width" newline bitfld.long 0x28 16. "FLT_DIS_C,When this bit is set filter is disabled for capture channel C." "0,1" newline hexmask.long.byte 0x28 12.--15. 1. "FLT_BAND_WID_B,Filter bandwith for capture channel B. 0~15 indicate 2~17 clock cycles width" newline bitfld.long 0x28 8. "FLT_DIS_B,When this bit is set filter is disabled for capture channel B." "0,1" hexmask.long.byte 0x28 4.--7. 1. "FLT_BAND_WID_A,Filter bandwith for capture channel A. 0~15 indicate 2~17 clock cycles width" newline bitfld.long 0x28 0. "FLT_DIS_A,When this bit is set filter is disabled for capture channel A." "0,1" line.long 0x2C "SSE_CTRL,This register controls signal synthsis engine function" bitfld.long 0x2C 14.--15. "CPT_CMP_SEL_D,Select one of compare output signals for capture channle D input synthesis." "0,1,2,3" newline bitfld.long 0x2C 12.--13. "CPT_CMP_SEL_C,Select one of compare output signals for capture channle C input synthesis." "0,1,2,3" bitfld.long 0x2C 10.--11. "CPT_CMP_SEL_B,Select one of compare output signals for capture channle B input synthesis." "0,1,2,3" newline bitfld.long 0x2C 8.--9. "CPT_CMP_SEL_A,Select one of compare output signals for capture channle A input synthesis." "0,1,2,3" bitfld.long 0x2C 7. "CMP_D_SYS_EN,Synthesis CMP_A CMP_B CMP_C and CMP_D inputs and timer_clk signals into one signal for compare channel D." "0,1" newline bitfld.long 0x2C 6. "CMP_C_SYS_EN,Synthesis CMP_A CMP_B CMP_C and CMP_D inputs and timer_clk signals into one signal for compare channel C." "0,1" bitfld.long 0x2C 5. "CMP_B_SYS_EN,Synthesis CMP_A CMP_B CMP_C and CMP_D inputs and timer_clk signals into one signal for compare channel B." "0,1" newline bitfld.long 0x2C 4. "CMP_A_SYS_EN,Synthesis CMP_A CMP_B CMP_C and CMP_D inputs and timer_clk signals into one signal for compare channel A." "0,1" bitfld.long 0x2C 3. "CPT_D_SYS_EN,Synthesis CPT_A CPT_B CPT_C and CPT_D inputs and one of compare output signals into one signal for capture channel D." "0,1" newline bitfld.long 0x2C 2. "CPT_C_SYS_EN,Synthesis CPT_A CPT_B CPT_C and CPT_D inputs and one of compare output signals into one signal for capture channel C." "0,1" bitfld.long 0x2C 1. "CPT_B_SYS_EN,Synthesis CPT_A CPT_B CPT_C and CPT_D inputs and one of compare output signals into one signal for capture channel B." "0,1" newline bitfld.long 0x2C 0. "CPT_A_SYS_EN,Synthesis CPT_A CPT_B CPT_C and CPT_D inputs and one of compare output signals into one signal for capture channel A." "0,1" line.long 0x30 "SSE_CPT_A,Signal synthesis for CAPTURE A input." hexmask.long 0x30 0.--31. 1. "SSE,Signal synthesis to drive one logic output from 5 logic inputs." line.long 0x34 "SSE_CPT_B,Signal synthesis for CAPTURE B input" hexmask.long 0x34 0.--31. 1. "SSE,Signal synthesis to drive one logic output from 5 logical inputs." line.long 0x38 "SSE_CPT_C,Signal synthesis for CAPTURE C input" hexmask.long 0x38 0.--31. 1. "SSE,Signal synthesis to drive one logic output from 5 logical inputs." line.long 0x3C "SSE_CPT_D,Signal synthesis for CAPTURE D input" hexmask.long 0x3C 0.--31. 1. "SSE,Signal synthesis to drive one logic output from 5 logical inputs." line.long 0x40 "SSE_CMP_A,Signal synthesis for COMPARE A output" hexmask.long 0x40 0.--31. 1. "SSE,Signal synthesis to drive one logic output from 5 logical inputs." line.long 0x44 "SSE_CMP_B,Signal synthesis for COMPARE B output" hexmask.long 0x44 0.--31. 1. "SSE,Signal synthesis to drive one logic output from 5 logical inputs." line.long 0x48 "SSE_CMP_C,Signal synthesis for COMPARE C output" hexmask.long 0x48 0.--31. 1. "SSE,Signal synthesis to drive one logic output from 5 logical inputs." line.long 0x4C "SSE_CMP_D,Signal synthesis for COMPARE D output" hexmask.long 0x4C 0.--31. 1. "SSE,Signal synthesis to drive one logic output from 5 logical inputs." group.long 0x100++0x1F line.long 0x0 "CPT_A_CONFIG,This register provides configuration for capture channel A." bitfld.long 0x0 5.--6. "CPT_TRIG_MODE,When detect below event on capture singal capture current timer counter value. 00: rising edge. 01: falling edge. 10: signal toggle. 11: Do not generate capture event for any change. Do not use." "rising edge,falling edge,?,?" newline bitfld.long 0x0 3.--4. "CNT_SEL,Capture timer select 00: CNT_G0 01: CNT_G0+CNT_G1 64 bit timer. Do not use for DUAL_CPT_MODE. 10: local_timer 11: always capture 0 value. Do not use." "CNT_G0,CNT_G0+CNT_G1 64 bit timer,?,?" bitfld.long 0x0 2. "DUAL_CPT_MODE,In this mode only generate one capture event for 2 consecutive capture.Pls note it can only be used for one time capture mode(SINGLE_MODE=1)." "0,1" newline bitfld.long 0x0 1. "SINGLE_MODE,1: Only generate one time capture event. Then auto clear EN bit. 0: Continously capture until SW clear EN bit." "Continously capture until SW clear EN bit,Only generate one time capture event" bitfld.long 0x0 0. "EN,Enable capture function. In single mode this bit will be auto cleared after compare event happens.In consecutive compare mode compare will keep working until SW clear this bit." "0,1" line.long 0x4 "CPT_B_CONFIG,This register provides configuration for capture channel B." bitfld.long 0x4 5.--6. "CPT_TRIG_MODE,When detect below event on capture singal capture current timer counter value. 00: rising edge. 01: falling edge. 10: signal toggle. 11: Do not generate capture event for any change. Do not use." "rising edge,falling edge,?,?" newline bitfld.long 0x4 3.--4. "CNT_SEL,Capture timer select 00: CNT_G0 01: CNT_G0+CNT_G1 64 bit timer. Do not use for DUAL_CPT_MODE. 10: local_timer 11: always capture value. Do not use." "CNT_G0,CNT_G0+CNT_G1 64 bit timer,?,?" bitfld.long 0x4 2. "DUAL_CPT_MODE,In this mode only generate one capture event for 2 consecutive capture. Pls note it can only be used for one time capture mode(SINGLE_MODE=1)." "0,1" newline bitfld.long 0x4 1. "SINGLE_MODE,1: Only generate one time capture event. Then auto clear EN bit. 0: Continously capture until SW clear EN bit." "Continously capture until SW clear EN bit,Only generate one time capture event" bitfld.long 0x4 0. "EN,Enable capture function. In single mode this bit will be auto cleared after compare event happens.In consecutive compare mode compare will keep working until SW clear this bit." "0,1" line.long 0x8 "CPT_C_CONFIG,This register provides configuration for capture channel C." bitfld.long 0x8 5.--6. "CPT_TRIG_MODE,When detect below event on capture singal capture current timer counter value. 00: rising edge. 01: falling edge. 10: signal toggle. 11: Do not generate capture event for any change. Do not use." "rising edge,falling edge,?,?" newline bitfld.long 0x8 3.--4. "CNT_SEL,Capture timer select 00: CNT_G0 01: CNT_G0+CNT_G1 64 bit timer. Do not use for DUAL_CPT_MODE. 10: local_timer 11: always capture 0 value. Do not use." "CNT_G0,CNT_G0+CNT_G1 64 bit timer,?,?" bitfld.long 0x8 2. "DUAL_CPT_MODE,In this mode only generate one capture event for 2 consecutive capture. Pls note it can only be used for one time capture mode(SINGLE_MODE=1)." "0,1" newline bitfld.long 0x8 1. "SINGLE_MODE,1: Only generate one time capture event. Then auto clear EN bit. 0: Continously capture until SW clear EN bit." "Continously capture until SW clear EN bit,Only generate one time capture event" bitfld.long 0x8 0. "EN,Enable capture function. In single mode this bit will be auto cleared after compare event happens.In consecutive compare mode compare will keep working until SW clear this bit." "0,1" line.long 0xC "CPT_D_CONFIG,This register provides configuration for capture channel D." bitfld.long 0xC 5.--6. "CPT_TRIG_MODE,When detect below event on capture singal capture current timer counter value. 00: rising edge. 01: falling edge. 10: signal toggle. 11: Do not generate capture event for any change. Do not use." "rising edge,falling edge,?,?" newline bitfld.long 0xC 3.--4. "CNT_SEL,Capture timer select 00: CNT_G0 01: CNT_G0+CNT_G1 64 bit timer. Do not use for DUAL_CPT_MODE. 10: local_timer 11: always capture 0 value. Do not use." "CNT_G0,CNT_G0+CNT_G1 64 bit timer,?,?" bitfld.long 0xC 2. "DUAL_CPT_MODE,In this mode only generate one capture event for 2 consecutive capture. Pls note it can only be used for one time capture mode(SINGLE_MODE=1)." "0,1" newline bitfld.long 0xC 1. "SINGLE_MODE,1: Only generate one time capture event. Then auto clear EN bit. 0: Continously capture until SW clear EN bit." "Continously capture until SW clear EN bit,Only generate one time capture event" bitfld.long 0xC 0. "EN,Enable capture function. In single mode this bit will be auto cleared after compare event happens.In consecutive compare mode compare will keep working until SW clear this bit." "0,1" line.long 0x10 "CMP_A_CONFIG,This register provides configuration or compare channel A." hexmask.long.byte 0x10 24.--31. 1. "CMP1_PULSE_WID,Width when output second positive or negative pulse in dual compare mode." hexmask.long.byte 0x10 16.--23. 1. "CMP0_PULSE_WID,Width when output positive or negative pulse." newline bitfld.long 0x10 15. "FRC_LOW,Force compare out to low." "0,1" bitfld.long 0x10 14. "FRC_HIGH,Force compare out to high." "0,1" newline bitfld.long 0x10 7.--9. "CMP1_OUT_MODE,Second compare output mode in dual compare mode 000: Positive pulse. 001: Negative pulse 010: Signal toggle. 011: Level high. 100: Level low. Other value: keep" "Positive pulse,Negative pulse,?,?,?,?,?,?" newline bitfld.long 0x10 4.--6. "CMP0_OUT_MODE,Compare output mode 000: Positive pulse. 001: Negative pulse 010: Signal toggle. 011: Level high. 100: Level low. Other value: keep" "Positive pulse,Negative pulse,?,?,?,?,?,?" bitfld.long 0x10 3. "CNT_SEL,Timer select for comparing. 1: select local timer for comparing. 0: select CNT_G0 for comparing." "select CNT_G0 for comparing,select local timer for comparing" newline bitfld.long 0x10 2. "DUAL_CMP_MODE,In this mode only generate one compare event for 2 consecutive compare." "0,1" bitfld.long 0x10 1. "SINGLE_MODE,1: only generate one time compare event. Then auto clear EN bit. 0. Continously compare until SW clear EN bit." "?,only generate one time compare event" newline bitfld.long 0x10 0. "EN,Enable compare function.In single mode this bit will be auto cleared after compare event happens.In consecutive compare mode compare will keep working until SW clear this bit." "0,1" line.long 0x14 "CMP_B_CONFIG,This register provides configuration for compare channel B." hexmask.long.byte 0x14 24.--31. 1. "CMP1_PULSE_WID,Width when output second positive or negative pulse in dual compare mode." hexmask.long.byte 0x14 16.--23. 1. "CMP0_PULSE_WID,Width when output positive or negative pulse." newline bitfld.long 0x14 15. "FRC_LOW,Force compare out to low." "0,1" bitfld.long 0x14 14. "FRC_HIGH,Force compare out to high." "0,1" newline bitfld.long 0x14 7.--9. "CMP1_OUT_MODE,Second compare output mode in dual compare mode 000: Positive pulse. 001: Negative pulse 010: Signal toggle. 011: Level high. 100: Level low. Other value: keep" "Positive pulse,Negative pulse,?,?,?,?,?,?" newline bitfld.long 0x14 4.--6. "CMP0_OUT_MODE,Compare output mode 000: Positive pulse. 001: Negative pulse 010: Signal toggle. 011: Level high. 100: Level low. Other value: keep" "Positive pulse,Negative pulse,?,?,?,?,?,?" bitfld.long 0x14 3. "CNT_SEL,Timer select for comparing. 1: select local timer for comparing. 0: select CNT_G0 for comparing." "select CNT_G0 for comparing,select local timer for comparing" newline bitfld.long 0x14 2. "DUAL_CMP_MODE,In this mode only generate one compare event for 2 consecutive compare." "0,1" bitfld.long 0x14 1. "SINGLE_MODE,1: only generate one time compare event. Then auto clear EN bit. 0. Continously compare until SW clear EN bit." "?,only generate one time compare event" newline bitfld.long 0x14 0. "EN,Enable compare function.In single mode this bit will be auto cleared after compare event happens.In consecutive compare mode compare will keep working until SW clear this bit." "0,1" line.long 0x18 "CMP_C_CONFIG,This register provides configuration for compare channel C." hexmask.long.byte 0x18 24.--31. 1. "CMP1_PULSE_WID,Width when output second positive or negative pulse in dual compare mode." hexmask.long.byte 0x18 16.--23. 1. "CMP0_PULSE_WID,Width when output positive or negative pulse." newline bitfld.long 0x18 15. "FRC_LOW,Force compare out to low." "0,1" bitfld.long 0x18 14. "FRC_HIGH,Force compare out to high." "0,1" newline bitfld.long 0x18 7.--9. "CMP1_OUT_MODE,Second compare output mode in dual compare mode 000: Positive pulse. 001: Negative pulse 010: Signal toggle. 011: Level high. 100: Level low. Other value: keep" "Positive pulse,Negative pulse,?,?,?,?,?,?" newline bitfld.long 0x18 4.--6. "CMP0_OUT_MODE,Compare output mode 000: Positive pulse. 001: Negative pulse 010: Signal toggle. 011: Level high. 100: Level low. Other value: keep" "Positive pulse,Negative pulse,?,?,?,?,?,?" bitfld.long 0x18 3. "CNT_SEL,Timer select for comparing. 1: select local timer for comparing. 0: select CNT_G0 for comparing." "select CNT_G0 for comparing,select local timer for comparing" newline bitfld.long 0x18 2. "DUAL_CMP_MODE,In this mode only generate one compare event for 2 consecutive compare." "0,1" bitfld.long 0x18 1. "SINGLE_MODE,1: only generate one time compare event. Then auto clear EN bit. 0. Continously compare until SW clear EN bit." "?,only generate one time compare event" newline bitfld.long 0x18 0. "EN,Enable compare function.In single mode this bit will be auto cleared after compare event happens.In consecutive compare mode compare will keep working until SW clear this bit." "0,1" line.long 0x1C "CMP_D_CONFIG,This register provides configuration for compare channel D ." hexmask.long.byte 0x1C 24.--31. 1. "CMP1_PULSE_WID,Width when output second positive or negative pulse in dual compare mode." hexmask.long.byte 0x1C 16.--23. 1. "CMP0_PULSE_WID,Width when output positive or negative pulse." newline bitfld.long 0x1C 15. "FRC_LOW,Force compare out to low." "0,1" bitfld.long 0x1C 14. "FRC_HIGH,Force compare out to high." "0,1" newline bitfld.long 0x1C 7.--9. "CMP1_OUT_MODE,Second compare output mode in dual compare mode 000: Positive pulse. 001: Negative pulse 010: Signal toggle. 011: Level high. 100: Level low. Other value: keep" "Positive pulse,Negative pulse,?,?,?,?,?,?" newline bitfld.long 0x1C 4.--6. "CMP0_OUT_MODE,Compare output mode 000: Positive pulse. 001: Negative pulse 010: Signal toggle. 011: Level high. 100: Level low. Other value: keep" "Positive pulse,Negative pulse,?,?,?,?,?,?" bitfld.long 0x1C 3. "CNT_SEL,Timer select for comparing. 1: select local timer for comparing. 0: select CNT_G0 for comparing." "select CNT_G0 for comparing,select local timer for comparing" newline bitfld.long 0x1C 2. "DUAL_CMP_MODE,In this mode only generate one compare event for 2 consecutive compare." "0,1" bitfld.long 0x1C 1. "SINGLE_MODE,1: only generate one time compare event. Then auto clear EN bit. 0. Continously compare until SW clear EN bit." "?,only generate one time compare event" newline bitfld.long 0x1C 0. "EN,Enable compare function.In single mode this bit will be auto cleared after compare event happens.In consecutive compare mode compare will keep working until SW clear this bit." "0,1" tree.end repeat.end elif (CORENAME()=="CORTEXA55") repeat 8. (increment 1. 1.) (list ad:0x30180000 ad:0x30190000 ad:0x308B0000 ad:0x308C0000 ad:0x308D0000 ad:0x308E0000 ad:0x308F0000 ad:0x30900000) tree "TMR$1" base $2 group.long 0x0++0xB line.long 0x0 "INT_STA,This register provides interrupt status." bitfld.long 0x0 23. "FIFO_D_OVERRUN,When set indicates FIFO D is overrrun in dma mode" "0,1" newline bitfld.long 0x0 22. "FIFO_C_OVERRUN,When set indicates FIFO C is overrrun in dma mode" "0,1" bitfld.long 0x0 21. "FIFO_B_OVERRUN,When set indicates FIFO B is overrrun in dma mode" "0,1" newline bitfld.long 0x0 20. "FIFO_A_OVERRUN,When set indicates FIFO A is overrrun in dma mode" "0,1" bitfld.long 0x0 19. "FIFO_D_UNDERRUN,When set indicates FIFO D is underrun in dma mode" "0,1" newline bitfld.long 0x0 18. "FIFO_C_UNDERRUN,When set indicates FIFO C is underrun in dma mode" "0,1" bitfld.long 0x0 17. "FIFO_B_UNDERRUN,When set indicates FIFO B is underrun in dma mode" "0,1" newline bitfld.long 0x0 16. "FIFO_A_UNDERRUN,When set indicates FIFO A is underrun in dma mode" "0,1" newline bitfld.long 0x0 14. "CNT_LOCAL_A_UNF,When set indicates CNT_LOCAL_A is underflow" "0,1" bitfld.long 0x0 13. "CNT_LOCAL_D_OVF,When set indicates CNT_LOCAL_D is overflow" "0,1" newline bitfld.long 0x0 12. "CNT_LOCAL_C_OVF,When set indicates CNT_LOCAL_C is overflow" "0,1" bitfld.long 0x0 11. "CNT_LOCAL_B_OVF,When set indicates CNT_LOCAL_B is overflow" "0,1" newline bitfld.long 0x0 10. "CNT_LOCAL_A_OVF,When set indicates CNT_LOCAL_A is overflow" "0,1" bitfld.long 0x0 9. "CNT_G1_OVF,When set indicates CNT_G1 is overflow" "0,1" newline bitfld.long 0x0 8. "CNT_G0_OVF,When set indicates CNT_G0 overflow" "0,1" bitfld.long 0x0 7. "CMP_D,When set indicates compare D event happens" "0,1" newline bitfld.long 0x0 6. "CMP_C,When set indicates compare C event happens" "0,1" bitfld.long 0x0 5. "CMP_B,When set indicates compare B event happens" "0,1" newline bitfld.long 0x0 4. "CMP_A,When set indicates compare A event happens" "0,1" bitfld.long 0x0 3. "CPT_D,When set indicates capture D event happens" "0,1" newline bitfld.long 0x0 2. "CPT_C,When set indicates capture C event happens" "0,1" bitfld.long 0x0 1. "CPT_B,When set indicates capture B event happens" "0,1" newline bitfld.long 0x0 0. "CPT_A,When set indicates capture A event happens" "0,1" line.long 0x4 "INT_STA_EN,This register provides enable bits for interrupt status." bitfld.long 0x4 23. "FIFO_D_OVERRUN,FIFO D overrun interrput status enable" "0,1" newline bitfld.long 0x4 22. "FIFO_C_OVERRUN,FIFO C overrun interrput status enable" "0,1" bitfld.long 0x4 21. "FIFO_B_OVERRUN,FIFO B overrun interrput status enable" "0,1" newline bitfld.long 0x4 20. "FIFO_A_OVERRUN,FIFO A overrun interrput status enable" "0,1" bitfld.long 0x4 19. "FIFO_D_UNDERRUN,FIFO D underrun interrput status enable" "0,1" newline bitfld.long 0x4 18. "FIFO_C_UNDERRUN,FIFO C underrun interrput status enable" "0,1" bitfld.long 0x4 17. "FIFO_B_UNDERRUN,FIFO B underrun interrput status enable" "0,1" newline bitfld.long 0x4 16. "FIFO_A_UNDERRUN,FIFO A underrun interrput status enable" "0,1" newline bitfld.long 0x4 14. "CNT_LOCAL_A_UNF,CNT_LOCAL_A underflow interrupt status enable" "0,1" bitfld.long 0x4 13. "CNT_LOCAL_D_OVF,CNT_LOCAL_D overflow interrupt status enable" "0,1" newline bitfld.long 0x4 12. "CNT_LOCAL_C_OVF,CNT_LOCAL_C overflow interrupt status enable" "0,1" bitfld.long 0x4 11. "CNT_LOCAL_B_OVF,CNT_LOCAL_B overflow interrupt status enable" "0,1" newline bitfld.long 0x4 10. "CNT_LOCAL_A_OVF,CNT_LOCAL_A overflow interrupt status enable" "0,1" bitfld.long 0x4 9. "CNT_G1_OVF,CNT_G1 overflow interrupt status enable" "0,1" newline bitfld.long 0x4 8. "CNT_G0_OVF,CNT_G0 overflow interrupt status enable" "0,1" bitfld.long 0x4 7. "CMP_D,Compare D event interrupt status enable" "0,1" newline bitfld.long 0x4 6. "CMP_C,Compare C event interrupt status enable" "0,1" bitfld.long 0x4 5. "CMP_B,Compare B event interrupt status enable" "0,1" newline bitfld.long 0x4 4. "CMP_A,Compare A event interrupt status enable" "0,1" bitfld.long 0x4 3. "CPT_D,Capture D event interrupt status enable" "0,1" newline bitfld.long 0x4 2. "CPT_C,Capture C event interrupt status enable" "0,1" bitfld.long 0x4 1. "CPT_B,Capture B event interrupt status enable" "0,1" newline bitfld.long 0x4 0. "CPT_A,Capture A event interrupt status enable" "0,1" line.long 0x8 "INT_SIG_EN,This register provides enable bits for interrupt signal." bitfld.long 0x8 23. "FIFO_D_OVERRUN,FIFO D overrun interrupt signal enable" "0,1" newline bitfld.long 0x8 22. "FIFO_C_OVERRUN,FIFO C overrun interrupt signal enable" "0,1" bitfld.long 0x8 21. "FIFO_B_OVERRUN,FIFO B overrun interrupt signal enable" "0,1" newline bitfld.long 0x8 20. "FIFO_A_OVERRUN,FIFO A overrun interrupt signal enable" "0,1" bitfld.long 0x8 19. "FIFO_D_UNDERRUN,FIFO D underrun interrupt signal enable" "0,1" newline bitfld.long 0x8 18. "FIFO_C_UNDERRUN,FIFO C underrun interrupt signal enable" "0,1" bitfld.long 0x8 17. "FIFO_B_UNDERRUN,FIFO B underrun interrupt signal enable" "0,1" newline bitfld.long 0x8 16. "FIFO_A_UNDERRUN,FIFO A underrun interrupt signal enable" "0,1" newline bitfld.long 0x8 14. "CNT_LOCAL_A_UNF,CNT_LOCAL_A underflow interrupt signal enable" "0,1" bitfld.long 0x8 13. "CNT_LOCAL_D_OVF,CNT_LOCAL_D overflow interrupt signal enable" "0,1" newline bitfld.long 0x8 12. "CNT_LOCAL_C_OVF,CNT_LOCAL_C overflow interrupt signal enable" "0,1" bitfld.long 0x8 11. "CNT_LOCAL_B_OVF,CNT_LOCAL_B overflow interrupt signal enable" "0,1" newline bitfld.long 0x8 10. "CNT_LOCAL_A_OVF,CNT_LOCAL_A overflow interrupt signal enable" "0,1" bitfld.long 0x8 9. "CNT_G1_OVF,CNT_G1 overflow interrupt signal enable" "0,1" newline bitfld.long 0x8 8. "CNT_G0_OVF,CNT_G0 overflow interrupt signal enable" "0,1" bitfld.long 0x8 7. "CMP_D,Compare D event interrupt signal enable" "0,1" newline bitfld.long 0x8 6. "CMP_C,Compare C event interrupt signal enable" "0,1" bitfld.long 0x8 5. "CMP_B,Compare B event interrupt signal enable" "0,1" newline bitfld.long 0x8 4. "CMP_A,Compare A event interrupt signal enable" "0,1" bitfld.long 0x8 3. "CPT_D,Capture D event interrupt signal enable" "0,1" newline bitfld.long 0x8 2. "CPT_C,Capture C event interrupt signal enable" "0,1" bitfld.long 0x8 1. "CPT_B,Capture B event interrupt signal enable" "0,1" newline bitfld.long 0x8 0. "CPT_A,Capture A event interrupt signal enable" "0,1" group.long 0x10++0xB line.long 0x0 "DMA_CTRL,This register provides the control setting for DMA mode" hexmask.long.byte 0x0 28.--31. 1. "CHN_D_WML,Water mark level for channel D FIFO. When channnel D FIFO is used for capture function dma D request will be asserted if data number in FIFO is greater than or equal to CHN_D_WML. When channnel D FIFO is used for compare function dma D.." hexmask.long.byte 0x0 24.--27. 1. "CHN_C_WML,Water mark level for channel C FIFO. When channnel C FIFO is used for capture function dma C request will be asserted if data number in FIFO is greater than or equal to CHN_C_WML. When channnel C FIFO is used for compare function dma C.." newline hexmask.long.byte 0x0 20.--23. 1. "CHN_B_WML,Water mark level for channel B FIFO. When channnel B FIFO is used for capture function dma B request will be asserted if data number in FIFO is greater than or equal to CHN_B_WML. When channnel A FIFO is used for compare function dma A.." hexmask.long.byte 0x0 16.--19. 1. "CHN_A_WML,Water mark level for channel A FIFO. When channnel A FIFO is used for capture function dma A request will be asserted if data number in FIFO is greater than or equal to CHN_A_WML. When channnel A FIFO is used for compare function dma A.." newline bitfld.long 0x0 13. "CNT_OVF_SEL,Select DMA requrest for CNT_G0 or CNT_G1 overflow. 1: Use to update CNT_G1 overflow register 0: Use to update CNT_G0 overflow register." "Use to update CNT_G0 overflow register,Use to update CNT_G1 overflow register" newline bitfld.long 0x0 11.--12. "CHN_D_SEL,Select dma request working for CNT_LOCAL_D overflow or CAPTURE D/COMPARE D channel 1x: Use for CNT_LOCAL_D timer 01: Use for capture channel D. 00: Use for compare channel D." "Use for compare channel D,Use for capture channel D,?,?" bitfld.long 0x0 9.--10. "CHN_C_SEL,Select dma request working for CNT_LOCAL_C overflow or CAPTURE C/COMPARE C channel 1x: Use for CNT_LOCAL_C timer 01: Use for capture channel C. 00: Use for compare channel C." "Use for compare channel C,Use for capture channel C,?,?" newline bitfld.long 0x0 7.--8. "CHN_B_SEL,Select dma request working for CNT_LOCAL_B overflow or CAPTURE B/COMPARE B channel 1x: Use for CNT_LOCAL_B timer 01: Use for capture channel B. 00: Use for compare channel B." "Use for compare channel B,Use for capture channel B,?,?" bitfld.long 0x0 5.--6. "CHN_A_SEL,Select dma request working for CNT_LOCAL_A overflow or CAPTURE A/COMPARE A channel 1x: Use for CNT_LOCAL_A timer 01: Use for capture channel A. 00: Use for compare channel A." "Use for compare channel A,Use for capture channel A,?,?" newline bitfld.long 0x0 4. "CNT_OVF_EN,Enable dma request for CNT_G0 or CNT_G1 overflow." "0,1" bitfld.long 0x0 3. "CHN_D_EN,Enable dma request for CNT_LOCAL_D overflow or CAPTURE D/COMPARE D channel according to channel D FIFO WML." "0,1" newline bitfld.long 0x0 2. "CHN_C_EN,Enable dma request for CNT_LOCAL_C overflow or CAPTURE C/COMPARE C channel according to channel C FIFO WML." "0,1" bitfld.long 0x0 1. "CHN_B_EN,Enable dma request for CNT_LOCAL_B overflow or CAPTURE B/COMPARE B channel according to channel B FIFO WML." "0,1" newline bitfld.long 0x0 0. "CHN_A_EN,Enable dma request for CNT_LOCAL_A overflow or CAPTURE A/COMPARE A channel according to channle A FIFO WML." "0,1" line.long 0x4 "DMA_SIG_MASK,The register contains the masks for dma request hardware output." bitfld.long 0x4 4. "CNT_OVF,Mask timer overflow dma request hardware output" "0,1" newline bitfld.long 0x4 3. "CHN_D,Mask channel D dma request hardware output" "0,1" bitfld.long 0x4 2. "CHN_C,Mask channel C dma request hardware output" "0,1" newline bitfld.long 0x4 1. "CHN_B,Mask channel B dma request hardware output" "0,1" bitfld.long 0x4 0. "CHN_A,Mask channel A dma request hardware output" "0,1" line.long 0x8 "SW_RST,This register controls software reset" bitfld.long 0x8 19. "CHN_D_SOFT_RST,Reset channel D FIFO.Write 1 to reset channel D FIFO. Then wait for one timer clock period. Finally write 0 to deassert reset." "0,1" newline bitfld.long 0x8 18. "CHN_C_SOFT_RST,Reset channel C FIFO.Write 1 to reset channel C FIFO. Then wait for one timer clock period. Finally write 0 to deassert reset." "0,1" bitfld.long 0x8 17. "CHN_B_SOFT_RST,Reset channel B FIFO. Write 1 to reset channel B FIFO. Then wait for one timer clock period. Finally write 0 to deassert reset." "0,1" newline bitfld.long 0x8 16. "CHN_A_SOFT_RST,Reset channel A FIFO. Write 1 to reset channel A FIFO. Then wait for one timer clock period. Finally write 0 to deassert reset." "0,1" rgroup.long 0x1C++0x3 line.long 0x0 "FIFO_STA,This register provides FIFO status information." bitfld.long 0x0 31. "FIFO_ERR_D,Indicates FIFO D is underrun or overrun." "0,1" hexmask.long.byte 0x0 26.--30. 1. "FIFO_ENTRIES_D,Indicates data numbers of FIFO D." newline bitfld.long 0x0 25. "FIFO_EMPTY_D,Indicates FIFO D is empty." "0,1" bitfld.long 0x0 24. "FIFO_FULL_D,Indicates FIFO D is full." "0,1" newline bitfld.long 0x0 23. "FIFO_ERR_C,Indicates FIFO C is underrun or overrun." "0,1" hexmask.long.byte 0x0 18.--22. 1. "FIFO_ENTRIES_C,Indicates data numbers of FIFO C." newline bitfld.long 0x0 17. "FIFO_EMPTY_C,Indicates FIFO C is empty." "0,1" bitfld.long 0x0 16. "FIFO_FULL_C,Indicates FIFO C is full." "0,1" newline bitfld.long 0x0 15. "FIFO_ERR_B,Indicates FIFO B is underrun or overrun." "0,1" hexmask.long.byte 0x0 10.--14. 1. "FIFO_ENTRIES_B,Indicates data numbers of FIFO B." newline bitfld.long 0x0 9. "FIFO_EMPTY_B,Indicates FIFO B is empty." "0,1" bitfld.long 0x0 8. "FIFO_FULL_B,Indicates FIFO B is full." "0,1" newline bitfld.long 0x0 7. "FIFO_ERR_A,Indicates FIFO A is underrun or overrun." "0,1" hexmask.long.byte 0x0 2.--6. 1. "FIFO_ENTRIES_A,Indicates data numbers of FIFO A." newline bitfld.long 0x0 1. "FIFO_EMPTY_A,Indicates FIFO A is empty." "0,1" bitfld.long 0x0 0. "FIFO_FULL_A,Indicates FIFO A is full." "0,1" group.long 0x20++0x1F line.long 0x0 "TIM_CLK_CONFIG,This register provides clock configuration for timer clock" bitfld.long 0x0 16.--17. "SRC_CLK_SEL,Clock source select. 00: High frequency(HF) clock update to 400mhz. 01: Alternative High frequency(AHF) clock update to 400mhz. 10: Low frenquency(LF) clock typically from 24mhz OSC. 11: Low power(LP) clock typically from low speed on.." "High frequency,Alternative High frequency,?,?" newline hexmask.long.word 0x0 0.--15. 1. "DIV_NUM,Divider number for timer clock." line.long 0x4 "CNT_CONFIG,Timer counter configuration for CNT_G0.CNT_G1 and CNT_LOCAL timer." bitfld.long 0x4 16. "INDEX_EDGE_SEL,Select which edge of INDEX(cpt_d) can reset CNT_LOCAL_A timer. 1. Negedge 0. Posedge" "0,1" newline bitfld.long 0x4 15. "HOME_EDGE_SEL,Select which edge of HOME(cpt_c) can reset CNT_LOCAL_A timer. 1. Negedge 0. Posedge" "0,1" bitfld.long 0x4 14. "INDEX_RST_EN,Enable CNT_LOCAL_A timer can be reset by INDEX(cpt_flt_d) singal." "0,1" newline bitfld.long 0x4 13. "HOME_RST_EN,Enable CNT_LOCAL_A timer can be reset by HOME(cpt_flt_c) singal." "0,1" bitfld.long 0x4 12. "QUADRATURE_MODE,Enable quadrature mode for CNT_LOCAL_A timer" "0,1" newline bitfld.long 0x4 11. "LOCAL_D_RST_EN,When this bit is set CNT_LOCAL_D will be reset by compare event or first capture event." "0,1" bitfld.long 0x4 10. "LOCAL_C_RST_EN,When this bit is set CNT_LOCAL_C will be reset by compare event or first capture event." "0,1" newline bitfld.long 0x4 9. "LOCAL_B_RST_EN,When this bit is set CNT_LOCAL_B will be reset by compare event or first capture event." "0,1" bitfld.long 0x4 8. "LOCAL_A_RST_EN,When this bit is set CNT_LOCAL_A will be reset by compare event or first capture event." "0,1" newline bitfld.long 0x4 6. "CASCADE_MODE,When this bit is set CNT_G1 only increase when CNT_G0 is overflowed. In this setup CNT_G0 can work as a 64 bit timer if CNT_G0_OVF_VAL is 32'hffffffff." "0,1" newline bitfld.long 0x4 5. "CNT_LOCAL_D_RLD,SW force reload for CNT_LOCAL_D. After this bit is set CNT_LOCAL_D will be reset to 0 and new OVF_VAL in CNT_LOCAL_D_OVF will be effective. Then this bit will be auto cleared by HW." "0,1" bitfld.long 0x4 4. "CNT_LOCAL_C_RLD,SW force reload for CNT_LOCAL_C. After this bit is set CNT_LOCAL_C will be reset to 0 and new OVF_VAL in CNT_LOCAL_C_OVF will be effective. Then this bit will be auto cleared by HW." "0,1" newline bitfld.long 0x4 3. "CNT_LOCAL_B_RLD,SW force reload for CNT_LOCAL_B. After this bit is set CNT_LOCAL_B will be reset to 0 and new OVF_VAL in CNT_LOCAL_B_OVF will be effective. Then this bit will be auto cleared by HW." "0,1" bitfld.long 0x4 2. "CNT_LOCAL_A_RLD,SW force reload for CNT_LOCAL_A. After this bit is set CNT_LOCAL_A will be reset to 0 and new OVF_VAL in CNT_LOCAL_A_OVF will be effective. Then this bit will be auto cleared by HW." "0,1" newline bitfld.long 0x4 1. "CNT_G1_RLD,SW force reload for CNT_G1. After this bit is set CNT_G1 will be reset to 0 and new OVF_VAL in CNT_G1 will be effective. Then this bit will be auto cleared by HW." "0,1" bitfld.long 0x4 0. "CNT_G0_RLD,SW force reload for CNT_G0. After this bit is set CNT_G0 will be reset to 0 and new OVF_VAL in CNT_G0 will be effective. Then this bit will be auto cleared by HW." "0,1" line.long 0x8 "CNT_G0_OVF,This register is used to update overflow value for CNT_G0." hexmask.long 0x8 0.--31. 1. "OVF_VAL,When CNT_G0 reach OVF_VAL it will be reset to 0. After write new value new OVF_VAL value will not be effective until one overrflow happens or CNT_G0_RLD in CNT_CONFIG register is set" line.long 0xC "CNT_G1_OVF,This register is used to update overflow value for CNT_G1." hexmask.long 0xC 0.--31. 1. "OVF_VAL,When CNT_G1 reach OVF_VAL it will be reset to 0. After write new value new OVF_VAL value will not be effective until one overrflow happens or CNT_G1_RLD in CNT_CONFIG register is set" line.long 0x10 "CNT_LOCAL_A_OVF,This register is used to update overflow value for CNT_LOCAL_A." hexmask.long 0x10 0.--31. 1. "OVF_VAL,When CNT_LOCAL_A reach OVF_VAL it will be reset to 0. After write new value new OVF_VAL value will not be effective until one overrflow happens or CNT_LOCAL_A_RLD in CNT_CONFIG register is set" line.long 0x14 "CNT_LOCAL_B_OVF,This register is used to update overflow value for CNT_LOCAL_B." hexmask.long 0x14 0.--31. 1. "OVF_VAL,When CNT_LOCAL_B reach OVF_VAL it will be reset to 0. After write new value new OVF_VAL value will not be effective until one overrflow happens or CNT_LOCAL_B_RLD in CNT_CONFIG register is set" line.long 0x18 "CNT_LOCAL_C_OVF,This register is used to update overflow value for CNT_LOCAL_C." hexmask.long 0x18 0.--31. 1. "OVF_VAL,When CNT_LOCAL_C reach OVF_VAL it will be reset to 0. After write new value new OVF_VAL value will not be effective until one overrflow happens or CNT_LOCAL_C_RLD in CNT_CONFIG register is set" line.long 0x1C "CNT_LOCAL_D_OVF,This register is used to update overflow value for CNT_LOCAL_D." hexmask.long 0x1C 0.--31. 1. "OVF_VAL,When CNT_LOCAL_D reach OVF_VAL it will be reset to 0. After write new value new OVF_VAL value will not be effective until one overrflow happens or CNT_LOCAL_D_RLD in CNT_CONFIG register is set" rgroup.long 0x40++0x17 line.long 0x0 "CNT_G0,CNT_G0 timer counter" hexmask.long 0x0 0.--31. 1. "TIMER,Timer counter value" line.long 0x4 "CNT_G1,CNT_G1 timer counter" hexmask.long 0x4 0.--31. 1. "TIMER,Timer counter value" line.long 0x8 "CNT_LOCAL_A,CNT_LOCAL_A timer counter" hexmask.long 0x8 0.--31. 1. "TIMER,Timer counter value" line.long 0xC "CNT_LOCAL_B,CNT_LOCAL_B timer counter" hexmask.long 0xC 0.--31. 1. "TIMER,Timer counter value" line.long 0x10 "CNT_LOCAL_C,CNT_LOCAL_C timer counter" hexmask.long 0x10 0.--31. 1. "TIMER,Timer counter value" line.long 0x14 "CNT_LOCAL_D,CNT_LOCAL_D timer counter" hexmask.long 0x14 0.--31. 1. "TIMER,Timer counter value" group.long 0x60++0xB line.long 0x0 "CMP_A_VAL_UPT,Indicate Software has updated compare value for channel A. Hardware will auto update all the compare value to shadow register. Use for no-DMA mode." bitfld.long 0x0 0. "UPT,Indicate software has updated compare value." "0,1" line.long 0x4 "CMP0_A_VAL,This reigister provides compare 0 value for compare channel A in no-DMA mode." hexmask.long 0x4 0.--31. 1. "DATA,Compare value." line.long 0x8 "CMP1_A_VAL,This reigister provides compare 1 value for compare channel A in no-DMA mode." hexmask.long 0x8 0.--31. 1. "DATA,Compare value." group.long 0x70++0xB line.long 0x0 "CMP_B_VAL_UPT,Indicate Software has updated compare value for channel B. Hardware will auto update all the compare value to shadow register. Use for no-DMA mode." bitfld.long 0x0 0. "UPT,Indicate software has updated compare value." "0,1" line.long 0x4 "CMP0_B_VAL,This reigister provides compare 0 value for compare channel B in no-DMA mode." hexmask.long 0x4 0.--31. 1. "DATA,Compare value." line.long 0x8 "CMP1_B_VAL,This reigister provides compare 1 value for compare channel B in no-DMA mode." hexmask.long 0x8 0.--31. 1. "DATA,Compare value." group.long 0x80++0xB line.long 0x0 "CMP_C_VAL_UPT,Indicate Software has updated compare value for channel C. Hardware will auto update all the compare value to shadow register. Use for no-DMA mode." bitfld.long 0x0 0. "UPT,Indicate software has updated compare value." "0,1" line.long 0x4 "CMP0_C_VAL,This reigister provides compare 0 value for compare channel C in no-DMA mode." hexmask.long 0x4 0.--31. 1. "DATA,Compare value." line.long 0x8 "CMP1_C_VAL,This reigister provides compare 1 value for compare channel C in no-DMA mode." hexmask.long 0x8 0.--31. 1. "DATA,Compare value." group.long 0x90++0xB line.long 0x0 "CMP_D_VAL_UPT,Indicate Software has updated compare value for channel D. Hardware will auto update all the compare value to shadow register. Use for no-DMA mode." bitfld.long 0x0 0. "UPT,Indicate software has updated compare value." "0,1" line.long 0x4 "CMP0_D_VAL,This reigister provides compare 0 value for compare channel D in no-DMA mode." hexmask.long 0x4 0.--31. 1. "DATA,Compare value." line.long 0x8 "CMP1_D_VAL,This reigister provides compare 1 value for compare channel D in no-DMA mode." hexmask.long 0x8 0.--31. 1. "DATA,Compare value." group.long 0xA0++0x4F line.long 0x0 "FIFO_A,This register provides FIFO entry for capture and compare channel A." hexmask.long 0x0 0.--31. 1. "DATA,FIFO entry" line.long 0x4 "FIFO_B,This register provides FIFO entry for capture and compare channel B." hexmask.long 0x4 0.--31. 1. "DATA,FIFO entry" line.long 0x8 "FIFO_C,This register provides FIFO entry for capture and compare channel C." hexmask.long 0x8 0.--31. 1. "DATA,FIFO entry" line.long 0xC "FIFO_D,This register provides FIFO entry for capture and compare channel D." hexmask.long 0xC 0.--31. 1. "DATA,FIFO entry" line.long 0x10 "CNT_G0_INIT,This register is used to update CNT_G0 initial value." hexmask.long 0x10 0.--31. 1. "VALUE,Write this register can directly update time counter value." line.long 0x14 "CNT_G1_INIT,This register is used to update CNT_G1 initial value." hexmask.long 0x14 0.--31. 1. "VALUE,Write this register can directly update time counter value." line.long 0x18 "CNT_LOCAL_A_INIT,This register is used to update CNT_LOCAL_A initial value." hexmask.long 0x18 0.--31. 1. "VALUE,Write this register can directly update time counter value." line.long 0x1C "CNT_LOCAL_B_INIT,This register is used to update CNT_LOCAL_B initial value." hexmask.long 0x1C 0.--31. 1. "VALUE,Write this register can directly update time counter value." line.long 0x20 "CNT_LOCAL_C_INIT,This register is used to update CNT_LOCAL_C initial value." hexmask.long 0x20 0.--31. 1. "VALUE,Write this register can directly update time counter value." line.long 0x24 "CNT_LOCAL_D_INIT,This register is used to update CNT_LOCAL_D initial value." hexmask.long 0x24 0.--31. 1. "VALUE,Write this register can directly update time counter value." line.long 0x28 "CPT_FLT,This reigster provides filter setting for capture input." hexmask.long.byte 0x28 28.--31. 1. "FLT_BAND_WID_D,Filter bandwith for capture channel D. 0~15 indicate 2~17 clock cycles width" newline bitfld.long 0x28 24. "FLT_DIS_D,When this bit is set filter is disabled for capture channel D." "0,1" hexmask.long.byte 0x28 20.--23. 1. "FLT_BAND_WID_C,Filter bandwith for capture channel C. 0~15 indicate 2~17 clock cycles width" newline bitfld.long 0x28 16. "FLT_DIS_C,When this bit is set filter is disabled for capture channel C." "0,1" newline hexmask.long.byte 0x28 12.--15. 1. "FLT_BAND_WID_B,Filter bandwith for capture channel B. 0~15 indicate 2~17 clock cycles width" newline bitfld.long 0x28 8. "FLT_DIS_B,When this bit is set filter is disabled for capture channel B." "0,1" hexmask.long.byte 0x28 4.--7. 1. "FLT_BAND_WID_A,Filter bandwith for capture channel A. 0~15 indicate 2~17 clock cycles width" newline bitfld.long 0x28 0. "FLT_DIS_A,When this bit is set filter is disabled for capture channel A." "0,1" line.long 0x2C "SSE_CTRL,This register controls signal synthsis engine function" bitfld.long 0x2C 14.--15. "CPT_CMP_SEL_D,Select one of compare output signals for capture channle D input synthesis." "0,1,2,3" newline bitfld.long 0x2C 12.--13. "CPT_CMP_SEL_C,Select one of compare output signals for capture channle C input synthesis." "0,1,2,3" bitfld.long 0x2C 10.--11. "CPT_CMP_SEL_B,Select one of compare output signals for capture channle B input synthesis." "0,1,2,3" newline bitfld.long 0x2C 8.--9. "CPT_CMP_SEL_A,Select one of compare output signals for capture channle A input synthesis." "0,1,2,3" bitfld.long 0x2C 7. "CMP_D_SYS_EN,Synthesis CMP_A CMP_B CMP_C and CMP_D inputs and timer_clk signals into one signal for compare channel D." "0,1" newline bitfld.long 0x2C 6. "CMP_C_SYS_EN,Synthesis CMP_A CMP_B CMP_C and CMP_D inputs and timer_clk signals into one signal for compare channel C." "0,1" bitfld.long 0x2C 5. "CMP_B_SYS_EN,Synthesis CMP_A CMP_B CMP_C and CMP_D inputs and timer_clk signals into one signal for compare channel B." "0,1" newline bitfld.long 0x2C 4. "CMP_A_SYS_EN,Synthesis CMP_A CMP_B CMP_C and CMP_D inputs and timer_clk signals into one signal for compare channel A." "0,1" bitfld.long 0x2C 3. "CPT_D_SYS_EN,Synthesis CPT_A CPT_B CPT_C and CPT_D inputs and one of compare output signals into one signal for capture channel D." "0,1" newline bitfld.long 0x2C 2. "CPT_C_SYS_EN,Synthesis CPT_A CPT_B CPT_C and CPT_D inputs and one of compare output signals into one signal for capture channel C." "0,1" bitfld.long 0x2C 1. "CPT_B_SYS_EN,Synthesis CPT_A CPT_B CPT_C and CPT_D inputs and one of compare output signals into one signal for capture channel B." "0,1" newline bitfld.long 0x2C 0. "CPT_A_SYS_EN,Synthesis CPT_A CPT_B CPT_C and CPT_D inputs and one of compare output signals into one signal for capture channel A." "0,1" line.long 0x30 "SSE_CPT_A,Signal synthesis for CAPTURE A input." hexmask.long 0x30 0.--31. 1. "SSE,Signal synthesis to drive one logic output from 5 logic inputs." line.long 0x34 "SSE_CPT_B,Signal synthesis for CAPTURE B input" hexmask.long 0x34 0.--31. 1. "SSE,Signal synthesis to drive one logic output from 5 logical inputs." line.long 0x38 "SSE_CPT_C,Signal synthesis for CAPTURE C input" hexmask.long 0x38 0.--31. 1. "SSE,Signal synthesis to drive one logic output from 5 logical inputs." line.long 0x3C "SSE_CPT_D,Signal synthesis for CAPTURE D input" hexmask.long 0x3C 0.--31. 1. "SSE,Signal synthesis to drive one logic output from 5 logical inputs." line.long 0x40 "SSE_CMP_A,Signal synthesis for COMPARE A output" hexmask.long 0x40 0.--31. 1. "SSE,Signal synthesis to drive one logic output from 5 logical inputs." line.long 0x44 "SSE_CMP_B,Signal synthesis for COMPARE B output" hexmask.long 0x44 0.--31. 1. "SSE,Signal synthesis to drive one logic output from 5 logical inputs." line.long 0x48 "SSE_CMP_C,Signal synthesis for COMPARE C output" hexmask.long 0x48 0.--31. 1. "SSE,Signal synthesis to drive one logic output from 5 logical inputs." line.long 0x4C "SSE_CMP_D,Signal synthesis for COMPARE D output" hexmask.long 0x4C 0.--31. 1. "SSE,Signal synthesis to drive one logic output from 5 logical inputs." group.long 0x100++0x1F line.long 0x0 "CPT_A_CONFIG,This register provides configuration for capture channel A." bitfld.long 0x0 5.--6. "CPT_TRIG_MODE,When detect below event on capture singal capture current timer counter value. 00: rising edge. 01: falling edge. 10: signal toggle. 11: Do not generate capture event for any change. Do not use." "rising edge,falling edge,?,?" newline bitfld.long 0x0 3.--4. "CNT_SEL,Capture timer select 00: CNT_G0 01: CNT_G0+CNT_G1 64 bit timer. Do not use for DUAL_CPT_MODE. 10: local_timer 11: always capture 0 value. Do not use." "CNT_G0,CNT_G0+CNT_G1 64 bit timer,?,?" bitfld.long 0x0 2. "DUAL_CPT_MODE,In this mode only generate one capture event for 2 consecutive capture.Pls note it can only be used for one time capture mode(SINGLE_MODE=1)." "0,1" newline bitfld.long 0x0 1. "SINGLE_MODE,1: Only generate one time capture event. Then auto clear EN bit. 0: Continously capture until SW clear EN bit." "Continously capture until SW clear EN bit,Only generate one time capture event" bitfld.long 0x0 0. "EN,Enable capture function. In single mode this bit will be auto cleared after compare event happens.In consecutive compare mode compare will keep working until SW clear this bit." "0,1" line.long 0x4 "CPT_B_CONFIG,This register provides configuration for capture channel B." bitfld.long 0x4 5.--6. "CPT_TRIG_MODE,When detect below event on capture singal capture current timer counter value. 00: rising edge. 01: falling edge. 10: signal toggle. 11: Do not generate capture event for any change. Do not use." "rising edge,falling edge,?,?" newline bitfld.long 0x4 3.--4. "CNT_SEL,Capture timer select 00: CNT_G0 01: CNT_G0+CNT_G1 64 bit timer. Do not use for DUAL_CPT_MODE. 10: local_timer 11: always capture value. Do not use." "CNT_G0,CNT_G0+CNT_G1 64 bit timer,?,?" bitfld.long 0x4 2. "DUAL_CPT_MODE,In this mode only generate one capture event for 2 consecutive capture. Pls note it can only be used for one time capture mode(SINGLE_MODE=1)." "0,1" newline bitfld.long 0x4 1. "SINGLE_MODE,1: Only generate one time capture event. Then auto clear EN bit. 0: Continously capture until SW clear EN bit." "Continously capture until SW clear EN bit,Only generate one time capture event" bitfld.long 0x4 0. "EN,Enable capture function. In single mode this bit will be auto cleared after compare event happens.In consecutive compare mode compare will keep working until SW clear this bit." "0,1" line.long 0x8 "CPT_C_CONFIG,This register provides configuration for capture channel C." bitfld.long 0x8 5.--6. "CPT_TRIG_MODE,When detect below event on capture singal capture current timer counter value. 00: rising edge. 01: falling edge. 10: signal toggle. 11: Do not generate capture event for any change. Do not use." "rising edge,falling edge,?,?" newline bitfld.long 0x8 3.--4. "CNT_SEL,Capture timer select 00: CNT_G0 01: CNT_G0+CNT_G1 64 bit timer. Do not use for DUAL_CPT_MODE. 10: local_timer 11: always capture 0 value. Do not use." "CNT_G0,CNT_G0+CNT_G1 64 bit timer,?,?" bitfld.long 0x8 2. "DUAL_CPT_MODE,In this mode only generate one capture event for 2 consecutive capture. Pls note it can only be used for one time capture mode(SINGLE_MODE=1)." "0,1" newline bitfld.long 0x8 1. "SINGLE_MODE,1: Only generate one time capture event. Then auto clear EN bit. 0: Continously capture until SW clear EN bit." "Continously capture until SW clear EN bit,Only generate one time capture event" bitfld.long 0x8 0. "EN,Enable capture function. In single mode this bit will be auto cleared after compare event happens.In consecutive compare mode compare will keep working until SW clear this bit." "0,1" line.long 0xC "CPT_D_CONFIG,This register provides configuration for capture channel D." bitfld.long 0xC 5.--6. "CPT_TRIG_MODE,When detect below event on capture singal capture current timer counter value. 00: rising edge. 01: falling edge. 10: signal toggle. 11: Do not generate capture event for any change. Do not use." "rising edge,falling edge,?,?" newline bitfld.long 0xC 3.--4. "CNT_SEL,Capture timer select 00: CNT_G0 01: CNT_G0+CNT_G1 64 bit timer. Do not use for DUAL_CPT_MODE. 10: local_timer 11: always capture 0 value. Do not use." "CNT_G0,CNT_G0+CNT_G1 64 bit timer,?,?" bitfld.long 0xC 2. "DUAL_CPT_MODE,In this mode only generate one capture event for 2 consecutive capture. Pls note it can only be used for one time capture mode(SINGLE_MODE=1)." "0,1" newline bitfld.long 0xC 1. "SINGLE_MODE,1: Only generate one time capture event. Then auto clear EN bit. 0: Continously capture until SW clear EN bit." "Continously capture until SW clear EN bit,Only generate one time capture event" bitfld.long 0xC 0. "EN,Enable capture function. In single mode this bit will be auto cleared after compare event happens.In consecutive compare mode compare will keep working until SW clear this bit." "0,1" line.long 0x10 "CMP_A_CONFIG,This register provides configuration or compare channel A." hexmask.long.byte 0x10 24.--31. 1. "CMP1_PULSE_WID,Width when output second positive or negative pulse in dual compare mode." hexmask.long.byte 0x10 16.--23. 1. "CMP0_PULSE_WID,Width when output positive or negative pulse." newline bitfld.long 0x10 15. "FRC_LOW,Force compare out to low." "0,1" bitfld.long 0x10 14. "FRC_HIGH,Force compare out to high." "0,1" newline bitfld.long 0x10 7.--9. "CMP1_OUT_MODE,Second compare output mode in dual compare mode 000: Positive pulse. 001: Negative pulse 010: Signal toggle. 011: Level high. 100: Level low. Other value: keep" "Positive pulse,Negative pulse,?,?,?,?,?,?" newline bitfld.long 0x10 4.--6. "CMP0_OUT_MODE,Compare output mode 000: Positive pulse. 001: Negative pulse 010: Signal toggle. 011: Level high. 100: Level low. Other value: keep" "Positive pulse,Negative pulse,?,?,?,?,?,?" bitfld.long 0x10 3. "CNT_SEL,Timer select for comparing. 1: select local timer for comparing. 0: select CNT_G0 for comparing." "select CNT_G0 for comparing,select local timer for comparing" newline bitfld.long 0x10 2. "DUAL_CMP_MODE,In this mode only generate one compare event for 2 consecutive compare." "0,1" bitfld.long 0x10 1. "SINGLE_MODE,1: only generate one time compare event. Then auto clear EN bit. 0. Continously compare until SW clear EN bit." "?,only generate one time compare event" newline bitfld.long 0x10 0. "EN,Enable compare function.In single mode this bit will be auto cleared after compare event happens.In consecutive compare mode compare will keep working until SW clear this bit." "0,1" line.long 0x14 "CMP_B_CONFIG,This register provides configuration for compare channel B." hexmask.long.byte 0x14 24.--31. 1. "CMP1_PULSE_WID,Width when output second positive or negative pulse in dual compare mode." hexmask.long.byte 0x14 16.--23. 1. "CMP0_PULSE_WID,Width when output positive or negative pulse." newline bitfld.long 0x14 15. "FRC_LOW,Force compare out to low." "0,1" bitfld.long 0x14 14. "FRC_HIGH,Force compare out to high." "0,1" newline bitfld.long 0x14 7.--9. "CMP1_OUT_MODE,Second compare output mode in dual compare mode 000: Positive pulse. 001: Negative pulse 010: Signal toggle. 011: Level high. 100: Level low. Other value: keep" "Positive pulse,Negative pulse,?,?,?,?,?,?" newline bitfld.long 0x14 4.--6. "CMP0_OUT_MODE,Compare output mode 000: Positive pulse. 001: Negative pulse 010: Signal toggle. 011: Level high. 100: Level low. Other value: keep" "Positive pulse,Negative pulse,?,?,?,?,?,?" bitfld.long 0x14 3. "CNT_SEL,Timer select for comparing. 1: select local timer for comparing. 0: select CNT_G0 for comparing." "select CNT_G0 for comparing,select local timer for comparing" newline bitfld.long 0x14 2. "DUAL_CMP_MODE,In this mode only generate one compare event for 2 consecutive compare." "0,1" bitfld.long 0x14 1. "SINGLE_MODE,1: only generate one time compare event. Then auto clear EN bit. 0. Continously compare until SW clear EN bit." "?,only generate one time compare event" newline bitfld.long 0x14 0. "EN,Enable compare function.In single mode this bit will be auto cleared after compare event happens.In consecutive compare mode compare will keep working until SW clear this bit." "0,1" line.long 0x18 "CMP_C_CONFIG,This register provides configuration for compare channel C." hexmask.long.byte 0x18 24.--31. 1. "CMP1_PULSE_WID,Width when output second positive or negative pulse in dual compare mode." hexmask.long.byte 0x18 16.--23. 1. "CMP0_PULSE_WID,Width when output positive or negative pulse." newline bitfld.long 0x18 15. "FRC_LOW,Force compare out to low." "0,1" bitfld.long 0x18 14. "FRC_HIGH,Force compare out to high." "0,1" newline bitfld.long 0x18 7.--9. "CMP1_OUT_MODE,Second compare output mode in dual compare mode 000: Positive pulse. 001: Negative pulse 010: Signal toggle. 011: Level high. 100: Level low. Other value: keep" "Positive pulse,Negative pulse,?,?,?,?,?,?" newline bitfld.long 0x18 4.--6. "CMP0_OUT_MODE,Compare output mode 000: Positive pulse. 001: Negative pulse 010: Signal toggle. 011: Level high. 100: Level low. Other value: keep" "Positive pulse,Negative pulse,?,?,?,?,?,?" bitfld.long 0x18 3. "CNT_SEL,Timer select for comparing. 1: select local timer for comparing. 0: select CNT_G0 for comparing." "select CNT_G0 for comparing,select local timer for comparing" newline bitfld.long 0x18 2. "DUAL_CMP_MODE,In this mode only generate one compare event for 2 consecutive compare." "0,1" bitfld.long 0x18 1. "SINGLE_MODE,1: only generate one time compare event. Then auto clear EN bit. 0. Continously compare until SW clear EN bit." "?,only generate one time compare event" newline bitfld.long 0x18 0. "EN,Enable compare function.In single mode this bit will be auto cleared after compare event happens.In consecutive compare mode compare will keep working until SW clear this bit." "0,1" line.long 0x1C "CMP_D_CONFIG,This register provides configuration for compare channel D ." hexmask.long.byte 0x1C 24.--31. 1. "CMP1_PULSE_WID,Width when output second positive or negative pulse in dual compare mode." hexmask.long.byte 0x1C 16.--23. 1. "CMP0_PULSE_WID,Width when output positive or negative pulse." newline bitfld.long 0x1C 15. "FRC_LOW,Force compare out to low." "0,1" bitfld.long 0x1C 14. "FRC_HIGH,Force compare out to high." "0,1" newline bitfld.long 0x1C 7.--9. "CMP1_OUT_MODE,Second compare output mode in dual compare mode 000: Positive pulse. 001: Negative pulse 010: Signal toggle. 011: Level high. 100: Level low. Other value: keep" "Positive pulse,Negative pulse,?,?,?,?,?,?" newline bitfld.long 0x1C 4.--6. "CMP0_OUT_MODE,Compare output mode 000: Positive pulse. 001: Negative pulse 010: Signal toggle. 011: Level high. 100: Level low. Other value: keep" "Positive pulse,Negative pulse,?,?,?,?,?,?" bitfld.long 0x1C 3. "CNT_SEL,Timer select for comparing. 1: select local timer for comparing. 0: select CNT_G0 for comparing." "select CNT_G0 for comparing,select local timer for comparing" newline bitfld.long 0x1C 2. "DUAL_CMP_MODE,In this mode only generate one compare event for 2 consecutive compare." "0,1" bitfld.long 0x1C 1. "SINGLE_MODE,1: only generate one time compare event. Then auto clear EN bit. 0. Continously compare until SW clear EN bit." "?,only generate one time compare event" newline bitfld.long 0x1C 0. "EN,Enable compare function.In single mode this bit will be auto cleared after compare event happens.In consecutive compare mode compare will keep working until SW clear this bit." "0,1" tree.end repeat.end endif tree.end tree "UART (Universal Asynchronous Receiver and Transmitter)" sif (CORENAME()=="CORTEXR5F") repeat 8. (increment 1. 1.) (list ad:0xF00F0000 ad:0xF0100000 ad:0xF0110000 ad:0xF0120000 ad:0xF0130000 ad:0xF0140000 ad:0xF0150000 ad:0xF0160000) tree "UART$1" base $2 group.long 0x0++0x3 line.long 0x0 "RBR,Receive Buffer Register" hexmask.long.tbyte 0x0 9.--31. 1. "RSVD_THR,RBR 31to9or8 Reserved bits and read as zero (0)" group.long 0x0++0x3 line.long 0x0 "DLL,Divisor Latch Low Register. Reset Value: 0x0" hexmask.long.tbyte 0x0 8.--31. 1. "RSVD_DLL_31TO8,DLL 31to8 Reserved bits and read as zero (0). Exists: Always" hexmask.long.byte 0x0 0.--7. 1. "DLL,Divisor Latch (Low). This register makes up the lower 8-bits of a 16-bit read/write. Divisor Latch register that contains the baud rate divisor for the UART. The output baud rate is equal to the serial clock frequency divided by sixteen times the.." group.long 0x0++0x7 line.long 0x0 "THR,Transmitting Holding Register" hexmask.long.tbyte 0x0 9.--31. 1. "RSVD_THR,THR 31to9 Reserved bits and read as zero (0). Exists: Always" hexmask.long.word 0x0 0.--8. 1. "THR,Tansmit Holding Register. This register contains data to be transmitted on the serial output port (sout) in UART mode or the serial infrared output (sir_out_n) in infrared mode. Data should only be written to the THR when the THR Empty (THRE) bit.." line.long 0x4 "DLH,Divisor Latch High Register." hexmask.long.tbyte 0x4 9.--31. 1. "RSVD_THR,THR 31to9 Reserved bits and read as zero (0). Exists: Always" hexmask.long.word 0x4 0.--8. 1. "THR,Tansmit Holding Register. This register contains data to be transmitted on the serial output port (sout) in UART mode or the serial infrared output (sir_out_n) in infrared mode. Data should only be written to the THR when the THR Empty (THRE) bit.." group.long 0x4++0x7 line.long 0x0 "DLH,Divisor Latch High Register." hexmask.long.tbyte 0x0 9.--31. 1. "RSVD_THR,THR 31to9 Reserved bits and read as zero (0). Exists: Always" hexmask.long.word 0x0 0.--8. 1. "THR,Tansmit Holding Register. This register contains data to be transmitted on the serial output port (sout) in UART mode or the serial infrared output (sir_out_n) in infrared mode. Data should only be written to the THR when the THR Empty (THRE) bit.." line.long 0x4 "FCR,FIFO Control Register." hexmask.long.tbyte 0x4 8.--31. 1. "RSVD_FCR,FCR 31to8 Reserved bits and read as zero (0). Exist: Always" bitfld.long 0x4 6.--7. "RT,RCVR Trigger (or RT). This is used to select the trigger level in the receiver FIFO at which the Received Data Available Interrupt will be generated. In auto flow control mode it is used to determine when the rts_n signal will be de-asserted only.." "0,1,2,3" newline bitfld.long 0x4 4.--5. "TET,RCVR Trigger (or RT). This is used to select the trigger level in the receiver FIFO at which the Received Data Available Interrupt will be generated. In auto flow control mode it is used to determine when the rts_n signal will be de-asserted only.." "0,1,2,3" bitfld.long 0x4 3. "DMAM,DMA Mode or (DMAM). This determines the DMA signalling mode used for the dma_tx_req_n and dma_rx_req_n output signals. Values: - 0x0 (MODE0): Mode 0 - 0x1 (MODE1): Mode 1 Exists: Always" "0,1" newline bitfld.long 0x4 2. "XFIFOR,XMIT FIFO Reset (or XFIFOR). This resets the control portion of the transmit FIFO and treats the FIFO as empty. This will also de-assert the DMA TX request and single signals. Note that this bit is 'self-clearing' and it is not necessary to clear.." "0,1" bitfld.long 0x4 1. "RFIFOR,RCVR FIFO Reset (or RFIFOR). This resets the control portion of the receive FIFO and treats the FIFO as empty. This will also de-assert the DMA RX request and single signals. Note that this bit is 'self-clearing' and it is not necessary to clear.." "0,1" newline bitfld.long 0x4 0. "FIFOE,FIFO Enable (or FIFOE). This enables/disables the transmit (XMIT) and receive (RCVR) FIFOs. Whenever the value of this bit is changed both the XMIT and RCVR controller portion of FIFOs is reset. Values: - 0x0 (DISABLED): FIFO is disabled - 0x1.." "0,1" group.long 0x8++0xB line.long 0x0 "FCR,FIFO Control Register." hexmask.long.tbyte 0x0 8.--31. 1. "RSVD_FCR,FCR 31to8 Reserved bits and read as zero (0). Exist: Always" bitfld.long 0x0 6.--7. "RT,RCVR Trigger (or RT). This is used to select the trigger level in the receiver FIFO at which the Received Data Available Interrupt will be generated. In auto flow control mode it is used to determine when the rts_n signal will be de-asserted only.." "0,1,2,3" newline bitfld.long 0x0 4.--5. "TET,RCVR Trigger (or RT). This is used to select the trigger level in the receiver FIFO at which the Received Data Available Interrupt will be generated. In auto flow control mode it is used to determine when the rts_n signal will be de-asserted only.." "0,1,2,3" bitfld.long 0x0 3. "DMAM,DMA Mode or (DMAM). This determines the DMA signalling mode used for the dma_tx_req_n and dma_rx_req_n output signals. Values: - 0x0 (MODE0): Mode 0 - 0x1 (MODE1): Mode 1 Exists: Always" "0,1" newline bitfld.long 0x0 2. "XFIFOR,XMIT FIFO Reset (or XFIFOR). This resets the control portion of the transmit FIFO and treats the FIFO as empty. This will also de-assert the DMA TX request and single signals. Note that this bit is 'self-clearing' and it is not necessary to clear.." "0,1" bitfld.long 0x0 1. "RFIFOR,RCVR FIFO Reset (or RFIFOR). This resets the control portion of the receive FIFO and treats the FIFO as empty. This will also de-assert the DMA RX request and single signals. Note that this bit is 'self-clearing' and it is not necessary to clear.." "0,1" newline bitfld.long 0x0 0. "FIFOE,FIFO Enable (or FIFOE). This enables/disables the transmit (XMIT) and receive (RCVR) FIFOs. Whenever the value of this bit is changed both the XMIT and RCVR controller portion of FIFOs is reset. Values: - 0x0 (DISABLED): FIFO is disabled - 0x1.." "0,1" line.long 0x4 "LCR,Line Control Register Reset Value: 0x0" hexmask.long.tbyte 0x4 8.--31. 1. "RSVD_LCR_31TO8,LCR 31to8 Reserved bits and read as 0." bitfld.long 0x4 7. "DLAB,Divisor Latch Access Bit. If UART_16550_COMPATIBLE == NO then writeable only when UART is not busy (USR[0]is zero) otherwise always writable and always readable. This bit is used to enable reading and writing of the Divisor Latch register (DLL and.." "Divisor Latch register is writable only when..,?" newline bitfld.long 0x4 6. "BC,Break Control Bit. This is used to cause a break condition to be transmitted to the receiving device. If set to one the serial output is forced to the spacing (logic 0) state. When not in Loopback Mode as determined by MCR[4] the sout line is forced.." "Serial output is released for data transmission,Serial output is forced to spacing state" bitfld.long 0x4 5. "SP,Stick Parity. If UART_16550_COMPATIBLE = NO then writeable only when UART is not busy (USR[0] is 0); otherwise always writable and always readable. This bit is used to force parity value. When PEN EPS and Stick Parity are set to 1 the parity bit is.." "Stick parity disabled,Stick parity enabled" newline bitfld.long 0x4 4. "EPS,Even Parity Select. If UART_16550_COMPATIBLE == NO then writeable only when UART is not busy (USR[0] is zero) otherwise always writable and always readable. This is used to select between even and odd parity when parity is enabled (PEN set to.." "an odd parity is transmitted or checked,an even parity is transmitted or checked" bitfld.long 0x4 3. "PEN,Parity Enable. If UART_16550_COMPATIBLE == NO then writeable only when UART is not busy (USR[0] is zero) otherwise always writable and always readable. This bit is used to enable and disable parity generation and detection in transmitted and.." "disable parity,enable parity" newline bitfld.long 0x4 2. "STOP,Number of stop bits. If UART_16550_COMPATIBLE == NO then writeable only when UART is not busy (USR[0] is zero) otherwise always writable and always readable. This is used to select the number of stop bits per character that the peripheral will.." "0,1" bitfld.long 0x4 0.--1. "DLS,Data Length Select (or CLS as used in legacy). If UART_16550_COMPATIBLE == NO then writeable only when UART is not busy (USR[0] is zero) otherwise always writable and always readable. When DLS_E in LCR_EXT is set to 0 this register is used to.." "0,1,2,3" line.long 0x8 "MCR,Modem Control Register Reset Value: 0x0" hexmask.long 0x8 7.--31. 1. "RSVD_MCR_31TO7,MCR 31to7 Reserved bits read as 0." bitfld.long 0x8 6. "SIRE,SIR Mode Enable. Writeable only when SIR_MODE == Enabled always readable. This is used to enable/disable the IrDA SIR Mode features as described in section 'IrDA 1.0 SIR Protocol' in the databook. Note: To enable SIR mode write the appropriate.." "IrDA SIR Mode disabled,IrDA SIR Mode enabled" newline bitfld.long 0x8 5. "AFCE,Auto Flow Control Enable. Writeable only when AFCE_MODE == Enabled always readable. When FIFOs are enabled and the Auto Flow Control Enable (AFCE) bit is set Auto Flow Control features are enabled as described in section 'Auto Flow Control' in.." "Auto Flow Control Mode disabled,Auto Flow Control Mode enabled" bitfld.long 0x8 4. "LOOPBACK,LoopBack Bit. This is used to put the UART into a diagnostic mode for test purposes. If operating in UART mode (SIR_MODE != Enabled OR NOT active MCR[6] set to zero) data on the sout line is held high while serial data output is looped back.." "Loopback mode disabled,Loopback mode enabled" newline bitfld.long 0x8 3. "OUT2,OUT2 . This is used to directly control the user-designated Output2 (out2_n) output. The value written to this location is inverted and driven out on out2_n. Note that in Loopback mode (MCR[4] set to one) the out2_n output is held inactive high.." "out2_n de-asserted,out2_n asserted" bitfld.long 0x8 2. "OUT1,OUT1 . This is used to directly control the user-designated Output1 (out1_n) output. The value written to this location is inverted and driven out on out1_n. Note that in Loopback mode (MCR[4] set to one) the out1_n output is held inactive high.." "out1_n de-asserted,out1_n asserted" newline bitfld.long 0x8 1. "RTS,Request to Send. This is used to directly control the Request to Send (rts_n) output. The Request To Send (rts_n) output is used to inform the modem or data set that the UART is ready to exchange data. When Auto RTS Flow Control is not enabled.." "Request to Send rts_n de-asserted,Request to Send rts_n asserted" bitfld.long 0x8 0. "DTR,Data Terminal Ready. This is used to directly control the Data Terminal Ready (dtr_n) output. The value written to this location is inverted and driven out on dtr_n. The Data Terminal Ready output is used to inform the modem or data set that the UART.." "dtr_n de-asserted,dtr_n asserted" rgroup.long 0x14++0x7 line.long 0x0 "LSR,Line Status Register Reset Value: 0x60" hexmask.long.tbyte 0x0 9.--31. 1. "RSVD_LSR_31TO9,LSR 31to9 Reserved bits read as zero." bitfld.long 0x0 8. "ADDR_RCVD,Address Received Bit. If 9Bit data mode (LCR_EXT[0]=1) is enabled this bit is used to indicate the 9th bit of the receive data is set to 1. This bit can also be used to indicate whether the incoming character is address or data. - 1 =.." "Indicates the character is data,Indicates the character is address" newline bitfld.long 0x0 7. "RFE,Receiver FIFO Error bit. This bit is only relevant when FIFO_MODE != NONE AND FIFO's are enabled (FCR[0] set to one). This is used to indicate if there is at least one parity error framing error or break indication in the FIFO. This bit is cleared.." "No error in RX FIFO,Error in RX FIFO" bitfld.long 0x0 6. "TEMT,Transmitter Empty bit. If in FIFO mode (FIFO_MODE != NONE) and FIFO's enabled (FCR[0] set to one) this bit is set whenever the Transmitter Shift Register and the FIFO are both empty. If in the non-FIFO mode or FIFO's are disabled this bit is set.." "Transmitter not empty,Transmitter empty" newline bitfld.long 0x0 5. "THRE,Transmit Holding Register Empty bit. If THRE_MODE_USER = Disabled or THRE mode is disabled (IER[7] set to zero) and regardless of FIFO's being implemented/enabled or not this bit indicates that the THR or TX FIFO is empty. This bit is set whenever.." "THRE interrupt control is disabled,THRE interrupt control is enabled" bitfld.long 0x0 4. "BI,Break Interrupt bit. This is used to indicate the detection of a break sequence on the serial input data. If in UART mode it is set whenever the serial input sin is held in a logic '0' state for longer than the sum of start time + data bits + parity.." "No break sequence detected,Break sequence detected" newline bitfld.long 0x0 3. "FE,Framing Error bit. This is used to indicate the occurrence of a framing error in the receiver. A framing error occurs when the receiver does not detect a valid STOP bit in the received data. In the FIFO mode since the framing error is associated with.." "no framing error,framing error" bitfld.long 0x0 2. "PE,Parity Error bit. This is used to indicate the occurrence of a parity error in the receiver if the Parity Enable (PEN) bit (LCR[3]) is set. In the FIFO mode since the parity error is associated with a character received it is revealed when the.." "no parity error,parity error" newline bitfld.long 0x0 1. "OE,Overrun error bit. This is used to indicate the occurrence of an overrun error. This occurs if a new data character was received before the previous data was read. In the non-FIFO mode the OE bit is set when a new character arrives in the receiver.." "no overrun error,overrun error" bitfld.long 0x0 0. "DR,Data Ready bit. This is used to indicate that the receiver contains at least one character in the RBR or the receiver FIFO. This bit is cleared when the RBR is read in the non-FIFO mode or when the receiver FIFO is empty in the FIFO mode. Reset.." "data not ready,data ready" line.long 0x4 "MSR,Whenever bits 0. 1. 2 or 3 is set to logic one. to indicate a change on the modem control inputs. a modem status interrupt will be generated if enabled via the IER regardless of when the change occurred. The bits (bits 0. 1. 3) can be set after a.." hexmask.long.tbyte 0x4 8.--31. 1. "RSVD_MSR_31TO8,MSR 31to8 Reserved bits read as 0." bitfld.long 0x4 7. "DCD,Data Carrier Detect. This is used to indicate the current state of the modem control line dcd_n. That is this bit is the complement dcd_n. When the Data Carrier Detect input (dcd_n) is asserted it is an indication that the carrier has been detected.." "dcd_n input is de-asserted,dcd_n input is asserted" newline bitfld.long 0x4 6. "RI,Ring Indicator. This is used to indicate the current state of the modem control line ri_n. That is this bit is the complement ri_n. When the Ring Indicator input (ri_n) is asserted it is an indication that a telephone ringing signal has been received.." "ri_n input is de-asserted,ri_n input is asserted" bitfld.long 0x4 5. "DSR,Data Set Ready. This is used to indicate the current state of the modem control line dsr_n. That is this bit is the complement dsr_n. When the Data Set Ready input (dsr_n) is asserted it is an indication that the modem or data set is ready to.." "dsr_n input is de-asserted,dsr_n input is asserted" newline bitfld.long 0x4 4. "CTS,Clear to Send. This is used to indicate the current state of the modem control line cts_n. That is this bit is the complement cts_n. When the Clear to Send input (cts_n) is asserted it is an indication that the modem or data set is ready to exchange.." "cts_n input is de-asserted,cts_n input is asserted" bitfld.long 0x4 3. "DDCD,Delta Data Carrier Detect. This is used to indicate that the modem control line dcd_n has changed since the last time the MSR was read. Reading the MSR clears the DDCD bit. In Loopback Mode (MCR[4] set to one) DDCD reflects changes on MCR[3].." "No change on dcd_n since last read of MSR,change on dcd_n since last read of MSR" newline bitfld.long 0x4 2. "TERI,Trailing Edge of Ring Indicator. This is used to indicate that a change on the input ri_n (from an active low to an inactive high state) has occurred since the last time the MSR was read. Reading the MSR clears the TERI bit. In Loopback Mode.." "no change on ri_n since last read of MSR,change on ri_n since last read of MSR" bitfld.long 0x4 1. "DDSR,Delta Data Set Ready. This is used to indicate that the modem control line dsr_n has changed since the last time the MSR was read. Reading the MSR clears the DDSR bit. In Loopback Mode (MCR[4] set to one) DDSR reflects changes on MCR[0] (DTR). Note.." "no change on dsr_n since last read of MSR,change on dsr_n since last read of MSR" newline bitfld.long 0x4 0. "DCTS,Delta Clear to Send. This is used to indicate that the modem control line cts_n has changed since the last time the MSR was read. Reading the MSR clears the DCTS bit. In Loopback Mode (MCR[4] set to one) DCTS reflects changes on MCR[1] (RTS). Note.." "no change on cts_n since last read of MSR,change on cts_n since last read of MSR" group.long 0x1C++0x3 line.long 0x0 "SCR,Scratchpad Register Reset Value: 0x0" hexmask.long.tbyte 0x0 8.--31. 1. "RSVD_SCR_31TO8,SCR 31to8 Reserved bits read as 0." hexmask.long.byte 0x0 0.--7. 1. "SCR,This register is for programmers to use as a temporary storage space. It has no defined purpose in the DW_apb_uart. Reset Value: 0x0" rgroup.long 0x30++0x3 line.long 0x0 "SRBR0,This register is valid only when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW = YES). If shadow registers are not implemented. this register does not exist and reading from this register address returns 0." hexmask.long.tbyte 0x0 9.--31. 1. "RSVD_SRBRN,SRBR0 31 to SRBRN_REG_SIZE Reserved bits read read as 0." hexmask.long.word 0x0 0.--8. 1. "SRBRN,Shadow Receive Buffer Register n. This is a shadow register for the RBR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains the data byte received on the serial input port.." repeat 15. (list 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x4 0x8 0xC 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 ) rgroup.long ($2+0x34)++0x3 line.long 0x0 "SRBR$1,Shadow Receive Buffer Register 1" hexmask.long.tbyte 0x0 9.--31. 1. "RSVD_SRBR1,SRBR1 31to9or8 Reserved bits read as 0." hexmask.long.word 0x0 0.--8. 1. "SRBR1,See SRBR0 description" repeat.end group.long 0x70++0x3 line.long 0x0 "FAR,FIFO Access Register" hexmask.long 0x0 1.--31. 1. "RSVD_FAR_31TO1,FAR 31to1 Reserved bits read as 0." bitfld.long 0x0 0. "FAR,Writes will have no effect when FIFO_ACCESS == No always readable. This register is use to enable a FIFO access mode for testing so that the receive FIFO can be written by the master and the transmit FIFO can be read by the master when FIFO's are.." "FIFO access mode disabled,FIFO access mode enabled" rgroup.long 0x74++0x3 line.long 0x0 "TFR,This register is valid only when the DW_apb_uart is configured to have the FIFO access test mode available (FIFO_ACCESS = YES). If not configured. this register does not exist and reading from this register address returns 0. Reset Value: 0x0'" hexmask.long.tbyte 0x0 8.--31. 1. "RSVD_TFR_31TO8,TFR 31to8 Reserved bits read as 0." hexmask.long.byte 0x0 0.--7. 1. "TFR,Transmit FIFO Read. These bits are only valid when FIFO access mode is enabled (FAR[0] is set to one). When FIFO's are implemented and enabled reading this register gives the data at the top of the transmit FIFO. Each consecutive read pops the.." group.long 0x78++0x3 line.long 0x0 "RFW,This register is valid only when the DW_apb_uart is configured to have the FIFO access test mode available (FIFO_ACCESS = YES). If not configured. this register does not exist and reading from this register address returns 0. Reset Value: 0x0'" hexmask.long.tbyte 0x0 10.--31. 1. "RSVD_RFW_31TO10,RFW 31to10 Reserved bits read as 0." bitfld.long 0x0 9. "RFFE,Receive FIFO Framing Error. These bits are only valid when FIFO access mode is enabled (FAR[0] is set to one). When FIFO's are implemented and enabled this bit is used to write framing error detection information to the receive FIFO. When FIFO's.." "Frame error disabled,Frame error enabled" newline bitfld.long 0x0 8. "RFPE,Receive FIFO Parity Error. These bits are only valid when FIFO access mode is enabled (FAR[0] is set to one). When FIFO's are implemented and enabled this bit is used to write parity error detection information to the receive FIFO. When FIFO's are.." "Parity error disabled,Parity error enabled" hexmask.long.byte 0x0 0.--7. 1. "RFWD,Receive FIFO Write Data. These bits are only valid when FIFO access mode is enabled (FAR[0] is set to one). When FIFO's are implemented and enabled the data that is written to the RFWD is pushed into the receive FIFO. Each consecutive write pushes.." rgroup.long 0x7C++0xB line.long 0x0 "USR,UART Status register. Reset Value: 0x6" hexmask.long 0x0 5.--31. 1. "RSVD_USR_31TO5,USR 31to5 Reserved bits read as 0." bitfld.long 0x0 4. "RFF,Receive FIFO Full. This bit is only valid when FIFO_STAT == YES. This is used to indicate that the receive FIFO is completely full. That is: This bit is cleared when the RX FIFO is no longer full. Reset Value: 0x0 0x1: Receive FIFO full 0x0: Receive.." "Receive FIFO not full,Receive FIFO full" newline bitfld.long 0x0 3. "RFNE,Receive FIFO Not Empty. This bit is only valid when FIFO_STAT == YES. This is used to indicate that the receive FIFO contains one or more entries. This bit is cleared when the RX FIFO is empty. Reset Value: 0x0 0x0: Receive FIFO is empty 0x1:.." "Receive FIFO is empty,Receive FIFO is not empty" bitfld.long 0x0 2. "TFE,Transmit FIFO Empty. This bit is only valid when FIFO_STAT == YES. This is used to indicate that the transmit FIFO is completely empty. This bit is cleared when the TX FIFO is no longer empty. Reset Value: 0x1 0x1: Transmit FIFO is empty 0x0:.." "Transmit FIFO is not empty,Transmit FIFO is empty" newline bitfld.long 0x0 1. "TFNF,Transmit FIFO Not Full. This bit is only valid when FIFO_STAT == YES. This is used to indicate that the transmit FIFO in not full. This bit is cleared when the TX FIFO is full. Reset Value: 0x1 0x0: Transmit FIFO is full 0x1: Transmit FIFO is not full" "Transmit FIFO is full,Transmit FIFO is not full" bitfld.long 0x0 0. "RSVD_BUSY,UART Busy. This bit is only valid when UART_16550_COMPATIBLE == YES. This indicates that a serial transfer is in progress when cleared indicates that the DW_apb_uart is idle or inactive. This bit will be set to 1 (busy) under any of the.." "DW_apb_uart is idle or inactive,DW_apb_uart is busy" line.long 0x4 "TFL,TFL register is valid only when the DW_apb_uart is configured to have additional FIFO status registers implemented (FIFO_STAT = YES). If status registers are not implemented. this register does not exist and reading from this register address returns.." hexmask.long 0x4 6.--31. 1. "RSVD_TFL_31TOADDR_WIDTH,TFL 31 to ADDR_WIDTH Reserved bits read as 0." hexmask.long.byte 0x4 0.--5. 1. "TFL,Transmit FIFO Level. This indicates the number of data entries in the transmit FIFO. Reset Value: 0x0" line.long 0x8 "RFL,RFL register is valid only when the DW_apb_uart is configured to have additional FIFO status registers implemented (FIFO_STAT = YES). If status registers are not implemented. this register does not exist and reading from this register address returns.." hexmask.long 0x8 6.--31. 1. "RSVD_RFL_31TOADDR_WIDTH,RFL 31 to ADDR_WIDTH Reserved bits read as 0." hexmask.long.byte 0x8 0.--5. 1. "RFL,Receive FIFO Level. This is indicates the number of data entries in the receive FIFO. Reset Value: 0x0" group.long 0x88++0x47 line.long 0x0 "SRR,This register is valid only when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW = YES). If shadow registers are not implemented. this register does not exist and reading from this register address returns 0. For.." hexmask.long 0x0 3.--31. 1. "RSVD_SRR_31TO3,SRR 31to3 Reserved bits read as 0." bitfld.long 0x0 2. "XFR,XMIT FIFO Reset. Writes will have no effect when FIFO_MODE == NONE. This is a shadow register for the XMIT FIFO Reset bit (FCR[2]). This can be used to remove the burden on software having to store previously written FCR values (which are pretty.." "0,1" newline bitfld.long 0x0 1. "RFR,RCVR FIFO Reset. Writes will have no effect when FIFO_MODE == NONE. This is a shadow register for the RCVR FIFO Reset bit (FCR[1]). This can be used to remove the burden on software having to store previously written FCR values (which are pretty.." "0,1" bitfld.long 0x0 0. "UR,UART Reset. This asynchronously resets the DW_apb_uart and synchronously removes the reset assertion. For a two clock implementation both pclk and sclk domains will be reset. Reset Value: 0x0 0x0: No Uart Reset 0x1: Uart reset" "No Uart Reset,Uart reset" line.long 0x4 "SRTS,SRTS register is valid only when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW = YES). If shadow registers are not implemented. this register does not exist and reading from this register address returns 0." hexmask.long 0x4 1.--31. 1. "RSVD_SRTS_31TO1,SRTS 31to1 Reserved bits read as 0." bitfld.long 0x4 0. "SRTS,Shadow Request to Send. This is a shadow register for the RTS bit (MCR[1]) this can be used to remove the burden of having to performing a read modify write on the MCR. This is used to directly control the Request to Send (rts_n) output. The.." "Shadow Request to Send uart_rts_n logic1,Shadow Request to Send uart_rts_n logic0" line.long 0x8 "SBCR,SBCR register is valid only when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW = YES). If shadow registers are not implemented. this register does not exist and reading from this register address returns 0." hexmask.long 0x8 1.--31. 1. "RSVD_SBCR_31TO1,SBCR 31to1 Reserved bits read as 0." bitfld.long 0x8 0. "SBCB,Shadow Break Control Bit. This is a shadow register for the Break bit (LCR[6]) this can be used to remove the burden of having to performing a read modify write on the LCR. This is used to cause a break condition to be transmitted to the receiving.." "No spacing on serial output,Serial output forced to the spacing" line.long 0xC "SDMAM,This register is valid only when the DW_apb_uart is configured to have additional FIFO registers implemented (FIFO_MODE != None) and additional shadow registers implemented (SHADOW = YES). If these registers are not implemented. this register does.." hexmask.long 0xC 1.--31. 1. "RSVD_SDMAM_31TO1,SDMAM 31to1 Reserved bits read as 0." bitfld.long 0xC 0. "SDMAM,Shadow DMA Mode. This is a shadow register for the DMA mode bit (FCR[3]). This can be used to remove the burden of having to store the previously written value to the FCR in memory and having to mask this value so that only the DMA Mode bit gets.." "Mode 0,Mode 1" line.long 0x10 "SFE,SFE register is valid only when the DW_apb_uart is configured to have additional FIFO registers implemented (FIFO_MODE != None) and additional shadow registers implemented (SHADOW = YES). If these registers are not implemented. this register does not.." hexmask.long 0x10 1.--31. 1. "RSVD_SFE_31TO1,SFE 31to1 Reserved bits read as 0." bitfld.long 0x10 0. "SFE,Shadow FIFO Enable. This is a shadow register for the FIFO enable bit (FCR[0]). This can be used to remove the burden of having to store the previously written value to the FCR in memory and having to mask this value so that only the FIFO enable bit.." "FIFOs are disabled,FIFOs are enabled" line.long 0x14 "SRT,SRT register is valid only when the DW_apb_uart is configured to have additional FIFO registers implemented (FIFO_MODE != None) and additional shadow registers implemented (SHADOW = YES). If these registers are not implemented. this register does not.." hexmask.long 0x14 2.--31. 1. "RSVD_SRT_31TO2,SRT 31to2 Reserved bits read as 0." bitfld.long 0x14 0.--1. "SRT,Shadow RCVR Trigger. This is a shadow register for the RCVR trigger bits (FCR[7:6]). This can be used to remove the burden of having to store the previously written value to the FCR in memory and having to mask this value so that only the RCVR.." "?,FIFO 1/4 full,FIFO 1/2 full,FIFO 2 less than full" line.long 0x18 "STET,This register is valid only when the DW_apb_uart is configured to have FIFOs implemented (FIFO_MODE != NONE) and THRE interrupt support implemented (THRE_MODE_USER = Enabled) and additional shadow registers implemented (SHADOW = YES). If FIFOs are.." hexmask.long 0x18 2.--31. 1. "RSVD_STET_31TO2,STET 31to2 Reserved bits read as 0." bitfld.long 0x18 0.--1. "STET,Shadow TX Empty Trigger. This is a shadow register for the TX empty trigger bits (FCR[5:4]). This can be used to remove the burden of having to store the previously written value to the FCR in memory and having to mask this value so that only the TX.." "FIFO empty,?,FIFO 1/4 full,FIFO 1/2 full" line.long 0x1C "HTX,Halt TX Reset Value: 0x0" hexmask.long 0x1C 1.--31. 1. "RSVD_HTX_31TO1,HTX 31to1 Reserved bits read as 0." bitfld.long 0x1C 0. "HTX,Halt TX. Writes will have no effect when FIFO_MODE == NONE always readable. This register is use to halt transmissions for testing so that the transmit FIFO can be filled by the master when FIFO's are implemented and enabled. Note if FIFO's are.." "Halt Transmission disabled,Halt Transmission enabled" line.long 0x20 "DMASA,DMA Software Acknowledge Register Reset Value: 0x0" hexmask.long 0x20 1.--31. 1. "RSVD_DMASA_31TO1,DMASA 31to1 Reserved bits read as 0." bitfld.long 0x20 0. "DMASA,DMA Software Acknowledge. Writes will have no effect when DMA_EXTRA == No. This register is use to perform DMA software acknowledge if a transfer needs to be terminated due to an error condition. For example if the DMA disables the channel then.." "?,DMA software acknowledge" line.long 0x24 "TCR,This register is used to enable or disable RS485 mode and also control the polarity values for Driven enable (de) and Receiver Enable (re) signals. This register is only valid when the DW_apb_uart is configured to have RS485 interface implemented.." hexmask.long 0x24 5.--31. 1. "RSVD_TCR_31TO5,TCR 31to5 Reserved bits read as 0." bitfld.long 0x24 3.--4. "XFER_MODE,Transfer Mode. - 0: In this mode transmit and receive can happen simultaneously. The user can enable DE_EN RE_EN at any point of time. Turn around timing as programmed in the TAT register is not applicable in this mode. - 1: In this mode DE.." "In this mode,In this mode,In this mode,?" newline bitfld.long 0x24 2. "DE_POL,Driver Enable Polarity. - 1: DE signal is active high - 0: DE signal is active low Reset Value: UART_DE_POL" "DE signal is active low,DE signal is active high" bitfld.long 0x24 1. "RE_POL,Receiver Enable Polarity. - 1: RE signal is active high - 0: RE signal is active low Reset Value: UART_RE_POL" "RE signal is active low,RE signal is active high" newline bitfld.long 0x24 0. "RS485_EN,RS485 Transfer Enable. - 0 : In this mode the transfers are still in the RS232 mode. All other fields in this register are reserved and register DE_EN/RE_EN/TAT are also reserved. - 1 : In this mode the transfers will happen in RS485 mode. All.." "In this mode,In this mode" line.long 0x28 "DE_EN,The Driver Output Enable Register (DE_EN) is used to control the assertion and de-assertion of the DE signal. This register is only valid when the DW_apb_uart is configured to have RS485 interface implemented (UART_RS485_INTERFACE_EN = ENABLED). If.." hexmask.long 0x28 1.--31. 1. "RSVD_DE_EN_31TO1,DE_EN 31to1 Reserved bits read as 0." bitfld.long 0x28 0. "DE_ENABLE,DE Enable control. The 'DE Enable' register bit is used to control assertion and de-assertion of 'de' signal. - 0: De-assert 'de' signal - 1: Assert 'de' signal Reset Value: 0x0" "De-assert 'de' signal,Assert 'de' signal" line.long 0x2C "RE_EN,The Receiver Output Enable Register (RE_EN) is used to control the assertion and de-assertion of the RE signal. This register is only valid when the DW_apb_uart is configured to have RS485 interface implemented (UART_RS485_INTERFACE_EN = ENABLED)." hexmask.long 0x2C 1.--31. 1. "RSVD_RE_EN_31TO1,RE_EN 31to1 Reserved bits read as 0." bitfld.long 0x2C 0. "RE_ENABLE,RE Enable control. The 'RE Enable' register bit is used to control assertion and de-assertion of 're' signal. - 0: De-assert 're' signal - 1: Assert 're' signal Reset Value: 0x0" "De-assert 're' signal,Assert 're' signal" line.long 0x30 "DET,The Driver Output Enable Timing Register (DET) is used to control the DE assertion and de-assertion timings of 'de' signal. This register is only valid when the DW_apb_uart is configured to have RS485 interface implemented (UART_RS485_INTERFACE =.." hexmask.long.byte 0x30 24.--31. 1. "RSVD_DE_DEAT_31TO24,DET 31to24 Reserved bits read as 0." hexmask.long.byte 0x30 16.--23. 1. "DE_DE-ASSERTION_TIME,Driver Enable de-assertion time. This field controls the amount of time (in terms of number of serial clock periods) between the end of stop bit on the sout to the falling edge of Driver output enable signal. Reset Value: 0x0" newline hexmask.long.byte 0x30 8.--15. 1. "RSVD_DE_AT_15TO8,DET 15to8 Reserved bits read as 0." hexmask.long.byte 0x30 0.--7. 1. "DE_ASSERTION_TIME,Driver Enable assertion time. This field controls the amount of time (in terms of number of serial clock periods) between the assertion of rising edge of Driver output enable signal to serial transmit enable. Any data in transmit buffer.." line.long 0x34 "TAT,The TurnAround Timing Register (TAT) is used to hold the turnaround time between switching of 're' and 'de' signals. This register is only valid when the DW_apb_uart is configured to have the RS485 interface implemented (UART_RS485_INTERFACE_EN =.." hexmask.long.word 0x34 16.--31. 1. "RE_TO_DE,Receiver Enable to Driver Enable TurnAround time. Turnaround time (in terms of serial clock) for RE De-assertion to DE assertion. Note: - If the DE assertion time in the DET register is 0 then the actual value is the programmed value + 3. - If.." hexmask.long.word 0x34 0.--15. 1. "DE_TO_RE,Driver Enable to Receiver Enable TurnAround time. Turnaround time (in terms of serial clock) for DE De-assertion to RE assertion. Note: The actual time is the programmed value + 1. Reset Value: 0x0" line.long 0x38 "DLF,This register is only valid when the DW_apb_uart is configured to have Fractional Baud rate Divisor implemented (FRACTIONAL_BAUD_DIVISOR_EN = ENABLED). If Fractional Baud rate divisor is not implemented. this register does not exist and reading from.." hexmask.long 0x38 4.--31. 1. "RSVD_DLF,DLF 31 to DLF_SIZE Reserved bits read as 0." hexmask.long.byte 0x38 0.--3. 1. "DLF,Fractional part of divisor. The fractional value is added to integer value set by DLH DLL. Fractional value is determined by (Divisor Fraction value)/(2^DLF_SIZE). For information on DLF values to be programmed for DLF_SIZE=4 see the 'Fractional.." line.long 0x3C "RAR,Receive Address Register Reset Value: 0x0" hexmask.long.tbyte 0x3C 8.--31. 1. "RSVD_RAR_31TO8,RAR 31to8 Reserved bits read as 0." hexmask.long.byte 0x3C 0.--7. 1. "RAR,This is an address matching register during receive mode. If the 9-th bit is set in the incoming character then the remaining 8-bits will be checked against this register value. If the match happens then sub-sequent characters with 9-th bit set to 0.." line.long 0x40 "TAR,Transmit Address Register Reset Value: 0x0" hexmask.long.tbyte 0x40 8.--31. 1. "RSVD_TAR_31TO8,TAR 31to8 Reserved bits read as 0." hexmask.long.byte 0x40 0.--7. 1. "TAR,This is an address matching register during transmit mode. If DLS_E (LCR_EXT[0]) bit is enabled then DW_apb_uart will send the 9-bit character with 9-th bit set to 1 and remaining 8-bit address will be sent from this register provided 'SEND_ADDR'.." line.long 0x44 "LCR_EXT,Line Extended Control Register Reset Value: 0x0" hexmask.long 0x44 4.--31. 1. "RSVD_LCR_EXT,LCR_EXT 31to4 Reserved bits read as 0." bitfld.long 0x44 3. "TRANSMIT_MODE,Transmit mode control bit. This bit is used to control the type of transmit mode during 9-bit data transfers. - 1: In this mode of operation Transmit Holding Register (THR) and Shadow Transmit Holding Register (STHR) are 9-bit wide. The.." "In this mode of operation,In this mode of operation" newline bitfld.long 0x44 2. "SEND_ADDR,Send address control bit. This bit is used as a control knob for the user to determine when to send the address during transmit mode. - 1 = 9-bit character will be transmitted with 9-th bit set to 1 and the remaining 8-bits will match to what.." "0,1" bitfld.long 0x44 1. "ADDR_MATCH,Address Match Mode.This bit is used to enable the address match feature during receive. - 1 = Address match mode; DW_apb_uart will wait until the incoming character with 9-th bit set to 1. And further checks to see if the address matches with.." "Normal mode; DW_apb_uart will start to receive..,Address match mode; DW_apb_uart will wait until.." newline bitfld.long 0x44 0. "DLS_E,Extension for DLS. This bit is used to enable 9-bit data for transmit and receive transfers. Reset Value: 0x0" "0,1" rgroup.long 0xF4++0xB line.long 0x0 "CPR,Component Parameter Register.This register is valid only when UART_ADD_ENCODED_PARAMS = 1. If the UART_ADD_ENCODED_PARAMS parameter is not set. this register does not exist and reading from this register address returns 0. Reset Value:.." hexmask.long.byte 0x0 24.--31. 1. "RSVD_CPR_31TO24,CPR 31to24 Reserved bits read as 0." hexmask.long.byte 0x0 16.--23. 1. "FIFO_MODE,Encoding of FIFO_MODE configuration parameter value. 0x0: FIFO mode is 0 0x40: FIFO mode is 1024 0x8: FIFO mode is 128 0x1: FIFO mode is 16 0x80: FIFO mode is 2048 0x10: FIFO mode is 256 0x2: FIFO mode is 32 0x20: FIFO mode is 512 0x4: FIFO.." newline bitfld.long 0x0 14.--15. "RSVD_CPR_15TO14,CPR 15to14 Reserved bits read as 0." "0,1,2,3" bitfld.long 0x0 13. "DMA_EXTRA,Encoding of DMA_EXTRA configuration parameter value. 0x0: DMA_EXTRA disabled 0x1: DMA_EXTRA enabled" "DMA_EXTRA disabled,DMA_EXTRA enabled" newline bitfld.long 0x0 12. "UART_ADD_ENCODED_PARAMS,Encoding of UART_ADD_ENCODED_PARAMS configuration parameter value. 0x0: UART_ADD_ENCODED_PARAMS disabled 0x1: UART_ADD_ENCODED_PARAMS enabled" "UART_ADD_ENCODED_PARAMS disabled,UART_ADD_ENCODED_PARAMS enabled" bitfld.long 0x0 11. "SHADOW,Encoding of SHADOW configuration parameter value. 0x0: SHADOW disabled 0x1: SHADOW enabled" "SHADOW disabled,SHADOW enabled" newline bitfld.long 0x0 10. "FIFO_STAT,Encoding of FIFO_STAT configuration parameter value. 0x0: FIFO_STAT disabled 0x1: FIFO_STAT enabled" "FIFO_STAT disabled,FIFO_STAT enabled" bitfld.long 0x0 9. "FIFO_ACCESS,Encoding of FIFO_ACCESS configuration parameter value. 0x0: FIFO_ACCESS disabled 0x1: FIFO ACCESS enabled" "FIFO_ACCESS disabled,FIFO ACCESS enabled" newline bitfld.long 0x0 8. "ADDITIONAL_FEAT,Encoding of ADDITIONAL_FEATURES configuration parameter value. 0x0: Additional features disabled 0x1: Additional features enabled" "Additional features disabled,Additional features enabled" bitfld.long 0x0 7. "SIR_LP_MODE,Encoding of SIR_LP_MODE configuration parameter value. 0x0: SIR_LP mode disabled 0x1: SIR_LP mode enabled" "SIR_LP mode disabled,SIR_LP mode enabled" newline bitfld.long 0x0 6. "SIR_MODE,Encoding of SIR_MODE configuration parameter value. 0x0: SIR mode disabled 0x1: SIR mode enabled" "SIR mode disabled,SIR mode enabled" bitfld.long 0x0 5. "THRE_MODE,Encoding of THRE_MODE configuration parameter value. 0x0: THRE mode disabled 0x1: THRE mode enabled" "THRE mode disabled,THRE mode enabled" newline bitfld.long 0x0 4. "AFCE_MODE,Encoding of AFCE_MODE configuration parameter value. 0x0: AFCE mode disabled 0x1: AFCE mode enabled" "AFCE mode disabled,AFCE mode enabled" bitfld.long 0x0 2.--3. "RSVD_CPR_3TO2,CPR 3to2 Reserved bits read as 0." "0,1,2,3" newline bitfld.long 0x0 0.--1. "APB_DATA_WIDTH,Encoding of APB_DATA_WIDTH configuration parameter value. 0x1: APB data width is 16 bits 0x2: APB data width is 32 bits 0x0: APB data width is 8 bits" "APB data width is 8 bits,APB data width is 16 bits,APB data width is 32 bits,?" line.long 0x4 "UCV,This register is valid only when the DW_apb_uart is configured to have additional features implemented (ADDITIONAL_FEATURES = YES). If additional features are not implemented. this register does not exist and reading from this register address.." hexmask.long 0x4 0.--31. 1. "UART_COMPONENT_VERSION,ASCII value for each number in the version followed by *. For example 32_30_31_2A represents the version 2.01*" line.long 0x8 "CTR,This register is valid only when the DW_apb_uart is configured to have additional features implemented (ADDITIONAL_FEATURES = YES). If additional features are not implemented. this register does not exist and reading from this register address.." hexmask.long 0x8 0.--31. 1. "PERIPHERAL_ID,This register contains the peripherals identification code. Reset Value: 0x44570110" tree.end repeat.end repeat 8. (increment 9. 1.) (list ad:0xF04C0000 ad:0xF04D0000 ad:0xF04E0000 ad:0xF04F0000 ad:0xF0500000 ad:0xF0510000 ad:0xF0520000 ad:0xF0530000) tree "UART$1" base $2 group.long 0x0++0x3 line.long 0x0 "RBR,Receive Buffer Register" hexmask.long.tbyte 0x0 9.--31. 1. "RSVD_THR,RBR 31to9or8 Reserved bits and read as zero (0)" group.long 0x0++0x3 line.long 0x0 "DLL,Divisor Latch Low Register. Reset Value: 0x0" hexmask.long.tbyte 0x0 8.--31. 1. "RSVD_DLL_31TO8,DLL 31to8 Reserved bits and read as zero (0). Exists: Always" hexmask.long.byte 0x0 0.--7. 1. "DLL,Divisor Latch (Low). This register makes up the lower 8-bits of a 16-bit read/write. Divisor Latch register that contains the baud rate divisor for the UART. The output baud rate is equal to the serial clock frequency divided by sixteen times the.." group.long 0x0++0x7 line.long 0x0 "THR,Transmitting Holding Register" hexmask.long.tbyte 0x0 9.--31. 1. "RSVD_THR,THR 31to9 Reserved bits and read as zero (0). Exists: Always" hexmask.long.word 0x0 0.--8. 1. "THR,Tansmit Holding Register. This register contains data to be transmitted on the serial output port (sout) in UART mode or the serial infrared output (sir_out_n) in infrared mode. Data should only be written to the THR when the THR Empty (THRE) bit.." line.long 0x4 "DLH,Divisor Latch High Register." hexmask.long.tbyte 0x4 9.--31. 1. "RSVD_THR,THR 31to9 Reserved bits and read as zero (0). Exists: Always" hexmask.long.word 0x4 0.--8. 1. "THR,Tansmit Holding Register. This register contains data to be transmitted on the serial output port (sout) in UART mode or the serial infrared output (sir_out_n) in infrared mode. Data should only be written to the THR when the THR Empty (THRE) bit.." group.long 0x4++0x7 line.long 0x0 "DLH,Divisor Latch High Register." hexmask.long.tbyte 0x0 9.--31. 1. "RSVD_THR,THR 31to9 Reserved bits and read as zero (0). Exists: Always" hexmask.long.word 0x0 0.--8. 1. "THR,Tansmit Holding Register. This register contains data to be transmitted on the serial output port (sout) in UART mode or the serial infrared output (sir_out_n) in infrared mode. Data should only be written to the THR when the THR Empty (THRE) bit.." line.long 0x4 "FCR,FIFO Control Register." hexmask.long.tbyte 0x4 8.--31. 1. "RSVD_FCR,FCR 31to8 Reserved bits and read as zero (0). Exist: Always" bitfld.long 0x4 6.--7. "RT,RCVR Trigger (or RT). This is used to select the trigger level in the receiver FIFO at which the Received Data Available Interrupt will be generated. In auto flow control mode it is used to determine when the rts_n signal will be de-asserted only.." "0,1,2,3" newline bitfld.long 0x4 4.--5. "TET,RCVR Trigger (or RT). This is used to select the trigger level in the receiver FIFO at which the Received Data Available Interrupt will be generated. In auto flow control mode it is used to determine when the rts_n signal will be de-asserted only.." "0,1,2,3" bitfld.long 0x4 3. "DMAM,DMA Mode or (DMAM). This determines the DMA signalling mode used for the dma_tx_req_n and dma_rx_req_n output signals. Values: - 0x0 (MODE0): Mode 0 - 0x1 (MODE1): Mode 1 Exists: Always" "0,1" newline bitfld.long 0x4 2. "XFIFOR,XMIT FIFO Reset (or XFIFOR). This resets the control portion of the transmit FIFO and treats the FIFO as empty. This will also de-assert the DMA TX request and single signals. Note that this bit is 'self-clearing' and it is not necessary to clear.." "0,1" bitfld.long 0x4 1. "RFIFOR,RCVR FIFO Reset (or RFIFOR). This resets the control portion of the receive FIFO and treats the FIFO as empty. This will also de-assert the DMA RX request and single signals. Note that this bit is 'self-clearing' and it is not necessary to clear.." "0,1" newline bitfld.long 0x4 0. "FIFOE,FIFO Enable (or FIFOE). This enables/disables the transmit (XMIT) and receive (RCVR) FIFOs. Whenever the value of this bit is changed both the XMIT and RCVR controller portion of FIFOs is reset. Values: - 0x0 (DISABLED): FIFO is disabled - 0x1.." "0,1" group.long 0x8++0xB line.long 0x0 "FCR,FIFO Control Register." hexmask.long.tbyte 0x0 8.--31. 1. "RSVD_FCR,FCR 31to8 Reserved bits and read as zero (0). Exist: Always" bitfld.long 0x0 6.--7. "RT,RCVR Trigger (or RT). This is used to select the trigger level in the receiver FIFO at which the Received Data Available Interrupt will be generated. In auto flow control mode it is used to determine when the rts_n signal will be de-asserted only.." "0,1,2,3" newline bitfld.long 0x0 4.--5. "TET,RCVR Trigger (or RT). This is used to select the trigger level in the receiver FIFO at which the Received Data Available Interrupt will be generated. In auto flow control mode it is used to determine when the rts_n signal will be de-asserted only.." "0,1,2,3" bitfld.long 0x0 3. "DMAM,DMA Mode or (DMAM). This determines the DMA signalling mode used for the dma_tx_req_n and dma_rx_req_n output signals. Values: - 0x0 (MODE0): Mode 0 - 0x1 (MODE1): Mode 1 Exists: Always" "0,1" newline bitfld.long 0x0 2. "XFIFOR,XMIT FIFO Reset (or XFIFOR). This resets the control portion of the transmit FIFO and treats the FIFO as empty. This will also de-assert the DMA TX request and single signals. Note that this bit is 'self-clearing' and it is not necessary to clear.." "0,1" bitfld.long 0x0 1. "RFIFOR,RCVR FIFO Reset (or RFIFOR). This resets the control portion of the receive FIFO and treats the FIFO as empty. This will also de-assert the DMA RX request and single signals. Note that this bit is 'self-clearing' and it is not necessary to clear.." "0,1" newline bitfld.long 0x0 0. "FIFOE,FIFO Enable (or FIFOE). This enables/disables the transmit (XMIT) and receive (RCVR) FIFOs. Whenever the value of this bit is changed both the XMIT and RCVR controller portion of FIFOs is reset. Values: - 0x0 (DISABLED): FIFO is disabled - 0x1.." "0,1" line.long 0x4 "LCR,Line Control Register Reset Value: 0x0" hexmask.long.tbyte 0x4 8.--31. 1. "RSVD_LCR_31TO8,LCR 31to8 Reserved bits and read as 0." bitfld.long 0x4 7. "DLAB,Divisor Latch Access Bit. If UART_16550_COMPATIBLE == NO then writeable only when UART is not busy (USR[0]is zero) otherwise always writable and always readable. This bit is used to enable reading and writing of the Divisor Latch register (DLL and.." "Divisor Latch register is writable only when..,?" newline bitfld.long 0x4 6. "BC,Break Control Bit. This is used to cause a break condition to be transmitted to the receiving device. If set to one the serial output is forced to the spacing (logic 0) state. When not in Loopback Mode as determined by MCR[4] the sout line is forced.." "Serial output is released for data transmission,Serial output is forced to spacing state" bitfld.long 0x4 5. "SP,Stick Parity. If UART_16550_COMPATIBLE = NO then writeable only when UART is not busy (USR[0] is 0); otherwise always writable and always readable. This bit is used to force parity value. When PEN EPS and Stick Parity are set to 1 the parity bit is.." "Stick parity disabled,Stick parity enabled" newline bitfld.long 0x4 4. "EPS,Even Parity Select. If UART_16550_COMPATIBLE == NO then writeable only when UART is not busy (USR[0] is zero) otherwise always writable and always readable. This is used to select between even and odd parity when parity is enabled (PEN set to.." "an odd parity is transmitted or checked,an even parity is transmitted or checked" bitfld.long 0x4 3. "PEN,Parity Enable. If UART_16550_COMPATIBLE == NO then writeable only when UART is not busy (USR[0] is zero) otherwise always writable and always readable. This bit is used to enable and disable parity generation and detection in transmitted and.." "disable parity,enable parity" newline bitfld.long 0x4 2. "STOP,Number of stop bits. If UART_16550_COMPATIBLE == NO then writeable only when UART is not busy (USR[0] is zero) otherwise always writable and always readable. This is used to select the number of stop bits per character that the peripheral will.." "0,1" bitfld.long 0x4 0.--1. "DLS,Data Length Select (or CLS as used in legacy). If UART_16550_COMPATIBLE == NO then writeable only when UART is not busy (USR[0] is zero) otherwise always writable and always readable. When DLS_E in LCR_EXT is set to 0 this register is used to.." "0,1,2,3" line.long 0x8 "MCR,Modem Control Register Reset Value: 0x0" hexmask.long 0x8 7.--31. 1. "RSVD_MCR_31TO7,MCR 31to7 Reserved bits read as 0." bitfld.long 0x8 6. "SIRE,SIR Mode Enable. Writeable only when SIR_MODE == Enabled always readable. This is used to enable/disable the IrDA SIR Mode features as described in section 'IrDA 1.0 SIR Protocol' in the databook. Note: To enable SIR mode write the appropriate.." "IrDA SIR Mode disabled,IrDA SIR Mode enabled" newline bitfld.long 0x8 5. "AFCE,Auto Flow Control Enable. Writeable only when AFCE_MODE == Enabled always readable. When FIFOs are enabled and the Auto Flow Control Enable (AFCE) bit is set Auto Flow Control features are enabled as described in section 'Auto Flow Control' in.." "Auto Flow Control Mode disabled,Auto Flow Control Mode enabled" bitfld.long 0x8 4. "LOOPBACK,LoopBack Bit. This is used to put the UART into a diagnostic mode for test purposes. If operating in UART mode (SIR_MODE != Enabled OR NOT active MCR[6] set to zero) data on the sout line is held high while serial data output is looped back.." "Loopback mode disabled,Loopback mode enabled" newline bitfld.long 0x8 3. "OUT2,OUT2 . This is used to directly control the user-designated Output2 (out2_n) output. The value written to this location is inverted and driven out on out2_n. Note that in Loopback mode (MCR[4] set to one) the out2_n output is held inactive high.." "out2_n de-asserted,out2_n asserted" bitfld.long 0x8 2. "OUT1,OUT1 . This is used to directly control the user-designated Output1 (out1_n) output. The value written to this location is inverted and driven out on out1_n. Note that in Loopback mode (MCR[4] set to one) the out1_n output is held inactive high.." "out1_n de-asserted,out1_n asserted" newline bitfld.long 0x8 1. "RTS,Request to Send. This is used to directly control the Request to Send (rts_n) output. The Request To Send (rts_n) output is used to inform the modem or data set that the UART is ready to exchange data. When Auto RTS Flow Control is not enabled.." "Request to Send rts_n de-asserted,Request to Send rts_n asserted" bitfld.long 0x8 0. "DTR,Data Terminal Ready. This is used to directly control the Data Terminal Ready (dtr_n) output. The value written to this location is inverted and driven out on dtr_n. The Data Terminal Ready output is used to inform the modem or data set that the UART.." "dtr_n de-asserted,dtr_n asserted" rgroup.long 0x14++0x7 line.long 0x0 "LSR,Line Status Register Reset Value: 0x60" hexmask.long.tbyte 0x0 9.--31. 1. "RSVD_LSR_31TO9,LSR 31to9 Reserved bits read as zero." bitfld.long 0x0 8. "ADDR_RCVD,Address Received Bit. If 9Bit data mode (LCR_EXT[0]=1) is enabled this bit is used to indicate the 9th bit of the receive data is set to 1. This bit can also be used to indicate whether the incoming character is address or data. - 1 =.." "Indicates the character is data,Indicates the character is address" newline bitfld.long 0x0 7. "RFE,Receiver FIFO Error bit. This bit is only relevant when FIFO_MODE != NONE AND FIFO's are enabled (FCR[0] set to one). This is used to indicate if there is at least one parity error framing error or break indication in the FIFO. This bit is cleared.." "No error in RX FIFO,Error in RX FIFO" bitfld.long 0x0 6. "TEMT,Transmitter Empty bit. If in FIFO mode (FIFO_MODE != NONE) and FIFO's enabled (FCR[0] set to one) this bit is set whenever the Transmitter Shift Register and the FIFO are both empty. If in the non-FIFO mode or FIFO's are disabled this bit is set.." "Transmitter not empty,Transmitter empty" newline bitfld.long 0x0 5. "THRE,Transmit Holding Register Empty bit. If THRE_MODE_USER = Disabled or THRE mode is disabled (IER[7] set to zero) and regardless of FIFO's being implemented/enabled or not this bit indicates that the THR or TX FIFO is empty. This bit is set whenever.." "THRE interrupt control is disabled,THRE interrupt control is enabled" bitfld.long 0x0 4. "BI,Break Interrupt bit. This is used to indicate the detection of a break sequence on the serial input data. If in UART mode it is set whenever the serial input sin is held in a logic '0' state for longer than the sum of start time + data bits + parity.." "No break sequence detected,Break sequence detected" newline bitfld.long 0x0 3. "FE,Framing Error bit. This is used to indicate the occurrence of a framing error in the receiver. A framing error occurs when the receiver does not detect a valid STOP bit in the received data. In the FIFO mode since the framing error is associated with.." "no framing error,framing error" bitfld.long 0x0 2. "PE,Parity Error bit. This is used to indicate the occurrence of a parity error in the receiver if the Parity Enable (PEN) bit (LCR[3]) is set. In the FIFO mode since the parity error is associated with a character received it is revealed when the.." "no parity error,parity error" newline bitfld.long 0x0 1. "OE,Overrun error bit. This is used to indicate the occurrence of an overrun error. This occurs if a new data character was received before the previous data was read. In the non-FIFO mode the OE bit is set when a new character arrives in the receiver.." "no overrun error,overrun error" bitfld.long 0x0 0. "DR,Data Ready bit. This is used to indicate that the receiver contains at least one character in the RBR or the receiver FIFO. This bit is cleared when the RBR is read in the non-FIFO mode or when the receiver FIFO is empty in the FIFO mode. Reset.." "data not ready,data ready" line.long 0x4 "MSR,Whenever bits 0. 1. 2 or 3 is set to logic one. to indicate a change on the modem control inputs. a modem status interrupt will be generated if enabled via the IER regardless of when the change occurred. The bits (bits 0. 1. 3) can be set after a.." hexmask.long.tbyte 0x4 8.--31. 1. "RSVD_MSR_31TO8,MSR 31to8 Reserved bits read as 0." bitfld.long 0x4 7. "DCD,Data Carrier Detect. This is used to indicate the current state of the modem control line dcd_n. That is this bit is the complement dcd_n. When the Data Carrier Detect input (dcd_n) is asserted it is an indication that the carrier has been detected.." "dcd_n input is de-asserted,dcd_n input is asserted" newline bitfld.long 0x4 6. "RI,Ring Indicator. This is used to indicate the current state of the modem control line ri_n. That is this bit is the complement ri_n. When the Ring Indicator input (ri_n) is asserted it is an indication that a telephone ringing signal has been received.." "ri_n input is de-asserted,ri_n input is asserted" bitfld.long 0x4 5. "DSR,Data Set Ready. This is used to indicate the current state of the modem control line dsr_n. That is this bit is the complement dsr_n. When the Data Set Ready input (dsr_n) is asserted it is an indication that the modem or data set is ready to.." "dsr_n input is de-asserted,dsr_n input is asserted" newline bitfld.long 0x4 4. "CTS,Clear to Send. This is used to indicate the current state of the modem control line cts_n. That is this bit is the complement cts_n. When the Clear to Send input (cts_n) is asserted it is an indication that the modem or data set is ready to exchange.." "cts_n input is de-asserted,cts_n input is asserted" bitfld.long 0x4 3. "DDCD,Delta Data Carrier Detect. This is used to indicate that the modem control line dcd_n has changed since the last time the MSR was read. Reading the MSR clears the DDCD bit. In Loopback Mode (MCR[4] set to one) DDCD reflects changes on MCR[3].." "No change on dcd_n since last read of MSR,change on dcd_n since last read of MSR" newline bitfld.long 0x4 2. "TERI,Trailing Edge of Ring Indicator. This is used to indicate that a change on the input ri_n (from an active low to an inactive high state) has occurred since the last time the MSR was read. Reading the MSR clears the TERI bit. In Loopback Mode.." "no change on ri_n since last read of MSR,change on ri_n since last read of MSR" bitfld.long 0x4 1. "DDSR,Delta Data Set Ready. This is used to indicate that the modem control line dsr_n has changed since the last time the MSR was read. Reading the MSR clears the DDSR bit. In Loopback Mode (MCR[4] set to one) DDSR reflects changes on MCR[0] (DTR). Note.." "no change on dsr_n since last read of MSR,change on dsr_n since last read of MSR" newline bitfld.long 0x4 0. "DCTS,Delta Clear to Send. This is used to indicate that the modem control line cts_n has changed since the last time the MSR was read. Reading the MSR clears the DCTS bit. In Loopback Mode (MCR[4] set to one) DCTS reflects changes on MCR[1] (RTS). Note.." "no change on cts_n since last read of MSR,change on cts_n since last read of MSR" group.long 0x1C++0x3 line.long 0x0 "SCR,Scratchpad Register Reset Value: 0x0" hexmask.long.tbyte 0x0 8.--31. 1. "RSVD_SCR_31TO8,SCR 31to8 Reserved bits read as 0." hexmask.long.byte 0x0 0.--7. 1. "SCR,This register is for programmers to use as a temporary storage space. It has no defined purpose in the DW_apb_uart. Reset Value: 0x0" rgroup.long 0x30++0x3 line.long 0x0 "SRBR0,This register is valid only when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW = YES). If shadow registers are not implemented. this register does not exist and reading from this register address returns 0." hexmask.long.tbyte 0x0 9.--31. 1. "RSVD_SRBRN,SRBR0 31 to SRBRN_REG_SIZE Reserved bits read read as 0." hexmask.long.word 0x0 0.--8. 1. "SRBRN,Shadow Receive Buffer Register n. This is a shadow register for the RBR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains the data byte received on the serial input port.." repeat 15. (list 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x4 0x8 0xC 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 ) rgroup.long ($2+0x34)++0x3 line.long 0x0 "SRBR$1,Shadow Receive Buffer Register 1" hexmask.long.tbyte 0x0 9.--31. 1. "RSVD_SRBR1,SRBR1 31to9or8 Reserved bits read as 0." hexmask.long.word 0x0 0.--8. 1. "SRBR1,See SRBR0 description" repeat.end group.long 0x70++0x3 line.long 0x0 "FAR,FIFO Access Register" hexmask.long 0x0 1.--31. 1. "RSVD_FAR_31TO1,FAR 31to1 Reserved bits read as 0." bitfld.long 0x0 0. "FAR,Writes will have no effect when FIFO_ACCESS == No always readable. This register is use to enable a FIFO access mode for testing so that the receive FIFO can be written by the master and the transmit FIFO can be read by the master when FIFO's are.." "FIFO access mode disabled,FIFO access mode enabled" rgroup.long 0x74++0x3 line.long 0x0 "TFR,This register is valid only when the DW_apb_uart is configured to have the FIFO access test mode available (FIFO_ACCESS = YES). If not configured. this register does not exist and reading from this register address returns 0. Reset Value: 0x0'" hexmask.long.tbyte 0x0 8.--31. 1. "RSVD_TFR_31TO8,TFR 31to8 Reserved bits read as 0." hexmask.long.byte 0x0 0.--7. 1. "TFR,Transmit FIFO Read. These bits are only valid when FIFO access mode is enabled (FAR[0] is set to one). When FIFO's are implemented and enabled reading this register gives the data at the top of the transmit FIFO. Each consecutive read pops the.." group.long 0x78++0x3 line.long 0x0 "RFW,This register is valid only when the DW_apb_uart is configured to have the FIFO access test mode available (FIFO_ACCESS = YES). If not configured. this register does not exist and reading from this register address returns 0. Reset Value: 0x0'" hexmask.long.tbyte 0x0 10.--31. 1. "RSVD_RFW_31TO10,RFW 31to10 Reserved bits read as 0." bitfld.long 0x0 9. "RFFE,Receive FIFO Framing Error. These bits are only valid when FIFO access mode is enabled (FAR[0] is set to one). When FIFO's are implemented and enabled this bit is used to write framing error detection information to the receive FIFO. When FIFO's.." "Frame error disabled,Frame error enabled" newline bitfld.long 0x0 8. "RFPE,Receive FIFO Parity Error. These bits are only valid when FIFO access mode is enabled (FAR[0] is set to one). When FIFO's are implemented and enabled this bit is used to write parity error detection information to the receive FIFO. When FIFO's are.." "Parity error disabled,Parity error enabled" hexmask.long.byte 0x0 0.--7. 1. "RFWD,Receive FIFO Write Data. These bits are only valid when FIFO access mode is enabled (FAR[0] is set to one). When FIFO's are implemented and enabled the data that is written to the RFWD is pushed into the receive FIFO. Each consecutive write pushes.." rgroup.long 0x7C++0xB line.long 0x0 "USR,UART Status register. Reset Value: 0x6" hexmask.long 0x0 5.--31. 1. "RSVD_USR_31TO5,USR 31to5 Reserved bits read as 0." bitfld.long 0x0 4. "RFF,Receive FIFO Full. This bit is only valid when FIFO_STAT == YES. This is used to indicate that the receive FIFO is completely full. That is: This bit is cleared when the RX FIFO is no longer full. Reset Value: 0x0 0x1: Receive FIFO full 0x0: Receive.." "Receive FIFO not full,Receive FIFO full" newline bitfld.long 0x0 3. "RFNE,Receive FIFO Not Empty. This bit is only valid when FIFO_STAT == YES. This is used to indicate that the receive FIFO contains one or more entries. This bit is cleared when the RX FIFO is empty. Reset Value: 0x0 0x0: Receive FIFO is empty 0x1:.." "Receive FIFO is empty,Receive FIFO is not empty" bitfld.long 0x0 2. "TFE,Transmit FIFO Empty. This bit is only valid when FIFO_STAT == YES. This is used to indicate that the transmit FIFO is completely empty. This bit is cleared when the TX FIFO is no longer empty. Reset Value: 0x1 0x1: Transmit FIFO is empty 0x0:.." "Transmit FIFO is not empty,Transmit FIFO is empty" newline bitfld.long 0x0 1. "TFNF,Transmit FIFO Not Full. This bit is only valid when FIFO_STAT == YES. This is used to indicate that the transmit FIFO in not full. This bit is cleared when the TX FIFO is full. Reset Value: 0x1 0x0: Transmit FIFO is full 0x1: Transmit FIFO is not full" "Transmit FIFO is full,Transmit FIFO is not full" bitfld.long 0x0 0. "RSVD_BUSY,UART Busy. This bit is only valid when UART_16550_COMPATIBLE == YES. This indicates that a serial transfer is in progress when cleared indicates that the DW_apb_uart is idle or inactive. This bit will be set to 1 (busy) under any of the.." "DW_apb_uart is idle or inactive,DW_apb_uart is busy" line.long 0x4 "TFL,TFL register is valid only when the DW_apb_uart is configured to have additional FIFO status registers implemented (FIFO_STAT = YES). If status registers are not implemented. this register does not exist and reading from this register address returns.." hexmask.long 0x4 6.--31. 1. "RSVD_TFL_31TOADDR_WIDTH,TFL 31 to ADDR_WIDTH Reserved bits read as 0." hexmask.long.byte 0x4 0.--5. 1. "TFL,Transmit FIFO Level. This indicates the number of data entries in the transmit FIFO. Reset Value: 0x0" line.long 0x8 "RFL,RFL register is valid only when the DW_apb_uart is configured to have additional FIFO status registers implemented (FIFO_STAT = YES). If status registers are not implemented. this register does not exist and reading from this register address returns.." hexmask.long 0x8 6.--31. 1. "RSVD_RFL_31TOADDR_WIDTH,RFL 31 to ADDR_WIDTH Reserved bits read as 0." hexmask.long.byte 0x8 0.--5. 1. "RFL,Receive FIFO Level. This is indicates the number of data entries in the receive FIFO. Reset Value: 0x0" group.long 0x88++0x47 line.long 0x0 "SRR,This register is valid only when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW = YES). If shadow registers are not implemented. this register does not exist and reading from this register address returns 0. For.." hexmask.long 0x0 3.--31. 1. "RSVD_SRR_31TO3,SRR 31to3 Reserved bits read as 0." bitfld.long 0x0 2. "XFR,XMIT FIFO Reset. Writes will have no effect when FIFO_MODE == NONE. This is a shadow register for the XMIT FIFO Reset bit (FCR[2]). This can be used to remove the burden on software having to store previously written FCR values (which are pretty.." "0,1" newline bitfld.long 0x0 1. "RFR,RCVR FIFO Reset. Writes will have no effect when FIFO_MODE == NONE. This is a shadow register for the RCVR FIFO Reset bit (FCR[1]). This can be used to remove the burden on software having to store previously written FCR values (which are pretty.." "0,1" bitfld.long 0x0 0. "UR,UART Reset. This asynchronously resets the DW_apb_uart and synchronously removes the reset assertion. For a two clock implementation both pclk and sclk domains will be reset. Reset Value: 0x0 0x0: No Uart Reset 0x1: Uart reset" "No Uart Reset,Uart reset" line.long 0x4 "SRTS,SRTS register is valid only when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW = YES). If shadow registers are not implemented. this register does not exist and reading from this register address returns 0." hexmask.long 0x4 1.--31. 1. "RSVD_SRTS_31TO1,SRTS 31to1 Reserved bits read as 0." bitfld.long 0x4 0. "SRTS,Shadow Request to Send. This is a shadow register for the RTS bit (MCR[1]) this can be used to remove the burden of having to performing a read modify write on the MCR. This is used to directly control the Request to Send (rts_n) output. The.." "Shadow Request to Send uart_rts_n logic1,Shadow Request to Send uart_rts_n logic0" line.long 0x8 "SBCR,SBCR register is valid only when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW = YES). If shadow registers are not implemented. this register does not exist and reading from this register address returns 0." hexmask.long 0x8 1.--31. 1. "RSVD_SBCR_31TO1,SBCR 31to1 Reserved bits read as 0." bitfld.long 0x8 0. "SBCB,Shadow Break Control Bit. This is a shadow register for the Break bit (LCR[6]) this can be used to remove the burden of having to performing a read modify write on the LCR. This is used to cause a break condition to be transmitted to the receiving.." "No spacing on serial output,Serial output forced to the spacing" line.long 0xC "SDMAM,This register is valid only when the DW_apb_uart is configured to have additional FIFO registers implemented (FIFO_MODE != None) and additional shadow registers implemented (SHADOW = YES). If these registers are not implemented. this register does.." hexmask.long 0xC 1.--31. 1. "RSVD_SDMAM_31TO1,SDMAM 31to1 Reserved bits read as 0." bitfld.long 0xC 0. "SDMAM,Shadow DMA Mode. This is a shadow register for the DMA mode bit (FCR[3]). This can be used to remove the burden of having to store the previously written value to the FCR in memory and having to mask this value so that only the DMA Mode bit gets.." "Mode 0,Mode 1" line.long 0x10 "SFE,SFE register is valid only when the DW_apb_uart is configured to have additional FIFO registers implemented (FIFO_MODE != None) and additional shadow registers implemented (SHADOW = YES). If these registers are not implemented. this register does not.." hexmask.long 0x10 1.--31. 1. "RSVD_SFE_31TO1,SFE 31to1 Reserved bits read as 0." bitfld.long 0x10 0. "SFE,Shadow FIFO Enable. This is a shadow register for the FIFO enable bit (FCR[0]). This can be used to remove the burden of having to store the previously written value to the FCR in memory and having to mask this value so that only the FIFO enable bit.." "FIFOs are disabled,FIFOs are enabled" line.long 0x14 "SRT,SRT register is valid only when the DW_apb_uart is configured to have additional FIFO registers implemented (FIFO_MODE != None) and additional shadow registers implemented (SHADOW = YES). If these registers are not implemented. this register does not.." hexmask.long 0x14 2.--31. 1. "RSVD_SRT_31TO2,SRT 31to2 Reserved bits read as 0." bitfld.long 0x14 0.--1. "SRT,Shadow RCVR Trigger. This is a shadow register for the RCVR trigger bits (FCR[7:6]). This can be used to remove the burden of having to store the previously written value to the FCR in memory and having to mask this value so that only the RCVR.." "?,FIFO 1/4 full,FIFO 1/2 full,FIFO 2 less than full" line.long 0x18 "STET,This register is valid only when the DW_apb_uart is configured to have FIFOs implemented (FIFO_MODE != NONE) and THRE interrupt support implemented (THRE_MODE_USER = Enabled) and additional shadow registers implemented (SHADOW = YES). If FIFOs are.." hexmask.long 0x18 2.--31. 1. "RSVD_STET_31TO2,STET 31to2 Reserved bits read as 0." bitfld.long 0x18 0.--1. "STET,Shadow TX Empty Trigger. This is a shadow register for the TX empty trigger bits (FCR[5:4]). This can be used to remove the burden of having to store the previously written value to the FCR in memory and having to mask this value so that only the TX.." "FIFO empty,?,FIFO 1/4 full,FIFO 1/2 full" line.long 0x1C "HTX,Halt TX Reset Value: 0x0" hexmask.long 0x1C 1.--31. 1. "RSVD_HTX_31TO1,HTX 31to1 Reserved bits read as 0." bitfld.long 0x1C 0. "HTX,Halt TX. Writes will have no effect when FIFO_MODE == NONE always readable. This register is use to halt transmissions for testing so that the transmit FIFO can be filled by the master when FIFO's are implemented and enabled. Note if FIFO's are.." "Halt Transmission disabled,Halt Transmission enabled" line.long 0x20 "DMASA,DMA Software Acknowledge Register Reset Value: 0x0" hexmask.long 0x20 1.--31. 1. "RSVD_DMASA_31TO1,DMASA 31to1 Reserved bits read as 0." bitfld.long 0x20 0. "DMASA,DMA Software Acknowledge. Writes will have no effect when DMA_EXTRA == No. This register is use to perform DMA software acknowledge if a transfer needs to be terminated due to an error condition. For example if the DMA disables the channel then.." "?,DMA software acknowledge" line.long 0x24 "TCR,This register is used to enable or disable RS485 mode and also control the polarity values for Driven enable (de) and Receiver Enable (re) signals. This register is only valid when the DW_apb_uart is configured to have RS485 interface implemented.." hexmask.long 0x24 5.--31. 1. "RSVD_TCR_31TO5,TCR 31to5 Reserved bits read as 0." bitfld.long 0x24 3.--4. "XFER_MODE,Transfer Mode. - 0: In this mode transmit and receive can happen simultaneously. The user can enable DE_EN RE_EN at any point of time. Turn around timing as programmed in the TAT register is not applicable in this mode. - 1: In this mode DE.." "In this mode,In this mode,In this mode,?" newline bitfld.long 0x24 2. "DE_POL,Driver Enable Polarity. - 1: DE signal is active high - 0: DE signal is active low Reset Value: UART_DE_POL" "DE signal is active low,DE signal is active high" bitfld.long 0x24 1. "RE_POL,Receiver Enable Polarity. - 1: RE signal is active high - 0: RE signal is active low Reset Value: UART_RE_POL" "RE signal is active low,RE signal is active high" newline bitfld.long 0x24 0. "RS485_EN,RS485 Transfer Enable. - 0 : In this mode the transfers are still in the RS232 mode. All other fields in this register are reserved and register DE_EN/RE_EN/TAT are also reserved. - 1 : In this mode the transfers will happen in RS485 mode. All.." "In this mode,In this mode" line.long 0x28 "DE_EN,The Driver Output Enable Register (DE_EN) is used to control the assertion and de-assertion of the DE signal. This register is only valid when the DW_apb_uart is configured to have RS485 interface implemented (UART_RS485_INTERFACE_EN = ENABLED). If.." hexmask.long 0x28 1.--31. 1. "RSVD_DE_EN_31TO1,DE_EN 31to1 Reserved bits read as 0." bitfld.long 0x28 0. "DE_ENABLE,DE Enable control. The 'DE Enable' register bit is used to control assertion and de-assertion of 'de' signal. - 0: De-assert 'de' signal - 1: Assert 'de' signal Reset Value: 0x0" "De-assert 'de' signal,Assert 'de' signal" line.long 0x2C "RE_EN,The Receiver Output Enable Register (RE_EN) is used to control the assertion and de-assertion of the RE signal. This register is only valid when the DW_apb_uart is configured to have RS485 interface implemented (UART_RS485_INTERFACE_EN = ENABLED)." hexmask.long 0x2C 1.--31. 1. "RSVD_RE_EN_31TO1,RE_EN 31to1 Reserved bits read as 0." bitfld.long 0x2C 0. "RE_ENABLE,RE Enable control. The 'RE Enable' register bit is used to control assertion and de-assertion of 're' signal. - 0: De-assert 're' signal - 1: Assert 're' signal Reset Value: 0x0" "De-assert 're' signal,Assert 're' signal" line.long 0x30 "DET,The Driver Output Enable Timing Register (DET) is used to control the DE assertion and de-assertion timings of 'de' signal. This register is only valid when the DW_apb_uart is configured to have RS485 interface implemented (UART_RS485_INTERFACE =.." hexmask.long.byte 0x30 24.--31. 1. "RSVD_DE_DEAT_31TO24,DET 31to24 Reserved bits read as 0." hexmask.long.byte 0x30 16.--23. 1. "DE_DE-ASSERTION_TIME,Driver Enable de-assertion time. This field controls the amount of time (in terms of number of serial clock periods) between the end of stop bit on the sout to the falling edge of Driver output enable signal. Reset Value: 0x0" newline hexmask.long.byte 0x30 8.--15. 1. "RSVD_DE_AT_15TO8,DET 15to8 Reserved bits read as 0." hexmask.long.byte 0x30 0.--7. 1. "DE_ASSERTION_TIME,Driver Enable assertion time. This field controls the amount of time (in terms of number of serial clock periods) between the assertion of rising edge of Driver output enable signal to serial transmit enable. Any data in transmit buffer.." line.long 0x34 "TAT,The TurnAround Timing Register (TAT) is used to hold the turnaround time between switching of 're' and 'de' signals. This register is only valid when the DW_apb_uart is configured to have the RS485 interface implemented (UART_RS485_INTERFACE_EN =.." hexmask.long.word 0x34 16.--31. 1. "RE_TO_DE,Receiver Enable to Driver Enable TurnAround time. Turnaround time (in terms of serial clock) for RE De-assertion to DE assertion. Note: - If the DE assertion time in the DET register is 0 then the actual value is the programmed value + 3. - If.." hexmask.long.word 0x34 0.--15. 1. "DE_TO_RE,Driver Enable to Receiver Enable TurnAround time. Turnaround time (in terms of serial clock) for DE De-assertion to RE assertion. Note: The actual time is the programmed value + 1. Reset Value: 0x0" line.long 0x38 "DLF,This register is only valid when the DW_apb_uart is configured to have Fractional Baud rate Divisor implemented (FRACTIONAL_BAUD_DIVISOR_EN = ENABLED). If Fractional Baud rate divisor is not implemented. this register does not exist and reading from.." hexmask.long 0x38 4.--31. 1. "RSVD_DLF,DLF 31 to DLF_SIZE Reserved bits read as 0." hexmask.long.byte 0x38 0.--3. 1. "DLF,Fractional part of divisor. The fractional value is added to integer value set by DLH DLL. Fractional value is determined by (Divisor Fraction value)/(2^DLF_SIZE). For information on DLF values to be programmed for DLF_SIZE=4 see the 'Fractional.." line.long 0x3C "RAR,Receive Address Register Reset Value: 0x0" hexmask.long.tbyte 0x3C 8.--31. 1. "RSVD_RAR_31TO8,RAR 31to8 Reserved bits read as 0." hexmask.long.byte 0x3C 0.--7. 1. "RAR,This is an address matching register during receive mode. If the 9-th bit is set in the incoming character then the remaining 8-bits will be checked against this register value. If the match happens then sub-sequent characters with 9-th bit set to 0.." line.long 0x40 "TAR,Transmit Address Register Reset Value: 0x0" hexmask.long.tbyte 0x40 8.--31. 1. "RSVD_TAR_31TO8,TAR 31to8 Reserved bits read as 0." hexmask.long.byte 0x40 0.--7. 1. "TAR,This is an address matching register during transmit mode. If DLS_E (LCR_EXT[0]) bit is enabled then DW_apb_uart will send the 9-bit character with 9-th bit set to 1 and remaining 8-bit address will be sent from this register provided 'SEND_ADDR'.." line.long 0x44 "LCR_EXT,Line Extended Control Register Reset Value: 0x0" hexmask.long 0x44 4.--31. 1. "RSVD_LCR_EXT,LCR_EXT 31to4 Reserved bits read as 0." bitfld.long 0x44 3. "TRANSMIT_MODE,Transmit mode control bit. This bit is used to control the type of transmit mode during 9-bit data transfers. - 1: In this mode of operation Transmit Holding Register (THR) and Shadow Transmit Holding Register (STHR) are 9-bit wide. The.." "In this mode of operation,In this mode of operation" newline bitfld.long 0x44 2. "SEND_ADDR,Send address control bit. This bit is used as a control knob for the user to determine when to send the address during transmit mode. - 1 = 9-bit character will be transmitted with 9-th bit set to 1 and the remaining 8-bits will match to what.." "0,1" bitfld.long 0x44 1. "ADDR_MATCH,Address Match Mode.This bit is used to enable the address match feature during receive. - 1 = Address match mode; DW_apb_uart will wait until the incoming character with 9-th bit set to 1. And further checks to see if the address matches with.." "Normal mode; DW_apb_uart will start to receive..,Address match mode; DW_apb_uart will wait until.." newline bitfld.long 0x44 0. "DLS_E,Extension for DLS. This bit is used to enable 9-bit data for transmit and receive transfers. Reset Value: 0x0" "0,1" rgroup.long 0xF4++0xB line.long 0x0 "CPR,Component Parameter Register.This register is valid only when UART_ADD_ENCODED_PARAMS = 1. If the UART_ADD_ENCODED_PARAMS parameter is not set. this register does not exist and reading from this register address returns 0. Reset Value:.." hexmask.long.byte 0x0 24.--31. 1. "RSVD_CPR_31TO24,CPR 31to24 Reserved bits read as 0." hexmask.long.byte 0x0 16.--23. 1. "FIFO_MODE,Encoding of FIFO_MODE configuration parameter value. 0x0: FIFO mode is 0 0x40: FIFO mode is 1024 0x8: FIFO mode is 128 0x1: FIFO mode is 16 0x80: FIFO mode is 2048 0x10: FIFO mode is 256 0x2: FIFO mode is 32 0x20: FIFO mode is 512 0x4: FIFO.." newline bitfld.long 0x0 14.--15. "RSVD_CPR_15TO14,CPR 15to14 Reserved bits read as 0." "0,1,2,3" bitfld.long 0x0 13. "DMA_EXTRA,Encoding of DMA_EXTRA configuration parameter value. 0x0: DMA_EXTRA disabled 0x1: DMA_EXTRA enabled" "DMA_EXTRA disabled,DMA_EXTRA enabled" newline bitfld.long 0x0 12. "UART_ADD_ENCODED_PARAMS,Encoding of UART_ADD_ENCODED_PARAMS configuration parameter value. 0x0: UART_ADD_ENCODED_PARAMS disabled 0x1: UART_ADD_ENCODED_PARAMS enabled" "UART_ADD_ENCODED_PARAMS disabled,UART_ADD_ENCODED_PARAMS enabled" bitfld.long 0x0 11. "SHADOW,Encoding of SHADOW configuration parameter value. 0x0: SHADOW disabled 0x1: SHADOW enabled" "SHADOW disabled,SHADOW enabled" newline bitfld.long 0x0 10. "FIFO_STAT,Encoding of FIFO_STAT configuration parameter value. 0x0: FIFO_STAT disabled 0x1: FIFO_STAT enabled" "FIFO_STAT disabled,FIFO_STAT enabled" bitfld.long 0x0 9. "FIFO_ACCESS,Encoding of FIFO_ACCESS configuration parameter value. 0x0: FIFO_ACCESS disabled 0x1: FIFO ACCESS enabled" "FIFO_ACCESS disabled,FIFO ACCESS enabled" newline bitfld.long 0x0 8. "ADDITIONAL_FEAT,Encoding of ADDITIONAL_FEATURES configuration parameter value. 0x0: Additional features disabled 0x1: Additional features enabled" "Additional features disabled,Additional features enabled" bitfld.long 0x0 7. "SIR_LP_MODE,Encoding of SIR_LP_MODE configuration parameter value. 0x0: SIR_LP mode disabled 0x1: SIR_LP mode enabled" "SIR_LP mode disabled,SIR_LP mode enabled" newline bitfld.long 0x0 6. "SIR_MODE,Encoding of SIR_MODE configuration parameter value. 0x0: SIR mode disabled 0x1: SIR mode enabled" "SIR mode disabled,SIR mode enabled" bitfld.long 0x0 5. "THRE_MODE,Encoding of THRE_MODE configuration parameter value. 0x0: THRE mode disabled 0x1: THRE mode enabled" "THRE mode disabled,THRE mode enabled" newline bitfld.long 0x0 4. "AFCE_MODE,Encoding of AFCE_MODE configuration parameter value. 0x0: AFCE mode disabled 0x1: AFCE mode enabled" "AFCE mode disabled,AFCE mode enabled" bitfld.long 0x0 2.--3. "RSVD_CPR_3TO2,CPR 3to2 Reserved bits read as 0." "0,1,2,3" newline bitfld.long 0x0 0.--1. "APB_DATA_WIDTH,Encoding of APB_DATA_WIDTH configuration parameter value. 0x1: APB data width is 16 bits 0x2: APB data width is 32 bits 0x0: APB data width is 8 bits" "APB data width is 8 bits,APB data width is 16 bits,APB data width is 32 bits,?" line.long 0x4 "UCV,This register is valid only when the DW_apb_uart is configured to have additional features implemented (ADDITIONAL_FEATURES = YES). If additional features are not implemented. this register does not exist and reading from this register address.." hexmask.long 0x4 0.--31. 1. "UART_COMPONENT_VERSION,ASCII value for each number in the version followed by *. For example 32_30_31_2A represents the version 2.01*" line.long 0x8 "CTR,This register is valid only when the DW_apb_uart is configured to have additional features implemented (ADDITIONAL_FEATURES = YES). If additional features are not implemented. this register does not exist and reading from this register address.." hexmask.long 0x8 0.--31. 1. "PERIPHERAL_ID,This register contains the peripherals identification code. Reset Value: 0x44570110" tree.end repeat.end elif (CORENAME()=="CORTEXA55") repeat 8. (increment 1. 1.) (list ad:0x300F0000 ad:0x30100000 ad:0x30110000 ad:0x30120000 ad:0x30130000 ad:0x30140000 ad:0x30150000 ad:0x30160000) tree "UART$1" base $2 group.long 0x0++0x3 line.long 0x0 "RBR,Receive Buffer Register" hexmask.long.tbyte 0x0 9.--31. 1. "RSVD_THR,RBR 31to9or8 Reserved bits and read as zero (0)" group.long 0x0++0x3 line.long 0x0 "DLL,Divisor Latch Low Register. Reset Value: 0x0" hexmask.long.tbyte 0x0 8.--31. 1. "RSVD_DLL_31TO8,DLL 31to8 Reserved bits and read as zero (0). Exists: Always" hexmask.long.byte 0x0 0.--7. 1. "DLL,Divisor Latch (Low). This register makes up the lower 8-bits of a 16-bit read/write. Divisor Latch register that contains the baud rate divisor for the UART. The output baud rate is equal to the serial clock frequency divided by sixteen times the.." group.long 0x0++0x7 line.long 0x0 "THR,Transmitting Holding Register" hexmask.long.tbyte 0x0 9.--31. 1. "RSVD_THR,THR 31to9 Reserved bits and read as zero (0). Exists: Always" hexmask.long.word 0x0 0.--8. 1. "THR,Tansmit Holding Register. This register contains data to be transmitted on the serial output port (sout) in UART mode or the serial infrared output (sir_out_n) in infrared mode. Data should only be written to the THR when the THR Empty (THRE) bit.." line.long 0x4 "DLH,Divisor Latch High Register." hexmask.long.tbyte 0x4 9.--31. 1. "RSVD_THR,THR 31to9 Reserved bits and read as zero (0). Exists: Always" hexmask.long.word 0x4 0.--8. 1. "THR,Tansmit Holding Register. This register contains data to be transmitted on the serial output port (sout) in UART mode or the serial infrared output (sir_out_n) in infrared mode. Data should only be written to the THR when the THR Empty (THRE) bit.." group.long 0x4++0x7 line.long 0x0 "DLH,Divisor Latch High Register." hexmask.long.tbyte 0x0 9.--31. 1. "RSVD_THR,THR 31to9 Reserved bits and read as zero (0). Exists: Always" hexmask.long.word 0x0 0.--8. 1. "THR,Tansmit Holding Register. This register contains data to be transmitted on the serial output port (sout) in UART mode or the serial infrared output (sir_out_n) in infrared mode. Data should only be written to the THR when the THR Empty (THRE) bit.." line.long 0x4 "FCR,FIFO Control Register." hexmask.long.tbyte 0x4 8.--31. 1. "RSVD_FCR,FCR 31to8 Reserved bits and read as zero (0). Exist: Always" bitfld.long 0x4 6.--7. "RT,RCVR Trigger (or RT). This is used to select the trigger level in the receiver FIFO at which the Received Data Available Interrupt will be generated. In auto flow control mode it is used to determine when the rts_n signal will be de-asserted only.." "0,1,2,3" newline bitfld.long 0x4 4.--5. "TET,RCVR Trigger (or RT). This is used to select the trigger level in the receiver FIFO at which the Received Data Available Interrupt will be generated. In auto flow control mode it is used to determine when the rts_n signal will be de-asserted only.." "0,1,2,3" bitfld.long 0x4 3. "DMAM,DMA Mode or (DMAM). This determines the DMA signalling mode used for the dma_tx_req_n and dma_rx_req_n output signals. Values: - 0x0 (MODE0): Mode 0 - 0x1 (MODE1): Mode 1 Exists: Always" "0,1" newline bitfld.long 0x4 2. "XFIFOR,XMIT FIFO Reset (or XFIFOR). This resets the control portion of the transmit FIFO and treats the FIFO as empty. This will also de-assert the DMA TX request and single signals. Note that this bit is 'self-clearing' and it is not necessary to clear.." "0,1" bitfld.long 0x4 1. "RFIFOR,RCVR FIFO Reset (or RFIFOR). This resets the control portion of the receive FIFO and treats the FIFO as empty. This will also de-assert the DMA RX request and single signals. Note that this bit is 'self-clearing' and it is not necessary to clear.." "0,1" newline bitfld.long 0x4 0. "FIFOE,FIFO Enable (or FIFOE). This enables/disables the transmit (XMIT) and receive (RCVR) FIFOs. Whenever the value of this bit is changed both the XMIT and RCVR controller portion of FIFOs is reset. Values: - 0x0 (DISABLED): FIFO is disabled - 0x1.." "0,1" group.long 0x8++0xB line.long 0x0 "FCR,FIFO Control Register." hexmask.long.tbyte 0x0 8.--31. 1. "RSVD_FCR,FCR 31to8 Reserved bits and read as zero (0). Exist: Always" bitfld.long 0x0 6.--7. "RT,RCVR Trigger (or RT). This is used to select the trigger level in the receiver FIFO at which the Received Data Available Interrupt will be generated. In auto flow control mode it is used to determine when the rts_n signal will be de-asserted only.." "0,1,2,3" newline bitfld.long 0x0 4.--5. "TET,RCVR Trigger (or RT). This is used to select the trigger level in the receiver FIFO at which the Received Data Available Interrupt will be generated. In auto flow control mode it is used to determine when the rts_n signal will be de-asserted only.." "0,1,2,3" bitfld.long 0x0 3. "DMAM,DMA Mode or (DMAM). This determines the DMA signalling mode used for the dma_tx_req_n and dma_rx_req_n output signals. Values: - 0x0 (MODE0): Mode 0 - 0x1 (MODE1): Mode 1 Exists: Always" "0,1" newline bitfld.long 0x0 2. "XFIFOR,XMIT FIFO Reset (or XFIFOR). This resets the control portion of the transmit FIFO and treats the FIFO as empty. This will also de-assert the DMA TX request and single signals. Note that this bit is 'self-clearing' and it is not necessary to clear.." "0,1" bitfld.long 0x0 1. "RFIFOR,RCVR FIFO Reset (or RFIFOR). This resets the control portion of the receive FIFO and treats the FIFO as empty. This will also de-assert the DMA RX request and single signals. Note that this bit is 'self-clearing' and it is not necessary to clear.." "0,1" newline bitfld.long 0x0 0. "FIFOE,FIFO Enable (or FIFOE). This enables/disables the transmit (XMIT) and receive (RCVR) FIFOs. Whenever the value of this bit is changed both the XMIT and RCVR controller portion of FIFOs is reset. Values: - 0x0 (DISABLED): FIFO is disabled - 0x1.." "0,1" line.long 0x4 "LCR,Line Control Register Reset Value: 0x0" hexmask.long.tbyte 0x4 8.--31. 1. "RSVD_LCR_31TO8,LCR 31to8 Reserved bits and read as 0." bitfld.long 0x4 7. "DLAB,Divisor Latch Access Bit. If UART_16550_COMPATIBLE == NO then writeable only when UART is not busy (USR[0]is zero) otherwise always writable and always readable. This bit is used to enable reading and writing of the Divisor Latch register (DLL and.." "Divisor Latch register is writable only when..,?" newline bitfld.long 0x4 6. "BC,Break Control Bit. This is used to cause a break condition to be transmitted to the receiving device. If set to one the serial output is forced to the spacing (logic 0) state. When not in Loopback Mode as determined by MCR[4] the sout line is forced.." "Serial output is released for data transmission,Serial output is forced to spacing state" bitfld.long 0x4 5. "SP,Stick Parity. If UART_16550_COMPATIBLE = NO then writeable only when UART is not busy (USR[0] is 0); otherwise always writable and always readable. This bit is used to force parity value. When PEN EPS and Stick Parity are set to 1 the parity bit is.." "Stick parity disabled,Stick parity enabled" newline bitfld.long 0x4 4. "EPS,Even Parity Select. If UART_16550_COMPATIBLE == NO then writeable only when UART is not busy (USR[0] is zero) otherwise always writable and always readable. This is used to select between even and odd parity when parity is enabled (PEN set to.." "an odd parity is transmitted or checked,an even parity is transmitted or checked" bitfld.long 0x4 3. "PEN,Parity Enable. If UART_16550_COMPATIBLE == NO then writeable only when UART is not busy (USR[0] is zero) otherwise always writable and always readable. This bit is used to enable and disable parity generation and detection in transmitted and.." "disable parity,enable parity" newline bitfld.long 0x4 2. "STOP,Number of stop bits. If UART_16550_COMPATIBLE == NO then writeable only when UART is not busy (USR[0] is zero) otherwise always writable and always readable. This is used to select the number of stop bits per character that the peripheral will.." "0,1" bitfld.long 0x4 0.--1. "DLS,Data Length Select (or CLS as used in legacy). If UART_16550_COMPATIBLE == NO then writeable only when UART is not busy (USR[0] is zero) otherwise always writable and always readable. When DLS_E in LCR_EXT is set to 0 this register is used to.." "0,1,2,3" line.long 0x8 "MCR,Modem Control Register Reset Value: 0x0" hexmask.long 0x8 7.--31. 1. "RSVD_MCR_31TO7,MCR 31to7 Reserved bits read as 0." bitfld.long 0x8 6. "SIRE,SIR Mode Enable. Writeable only when SIR_MODE == Enabled always readable. This is used to enable/disable the IrDA SIR Mode features as described in section 'IrDA 1.0 SIR Protocol' in the databook. Note: To enable SIR mode write the appropriate.." "IrDA SIR Mode disabled,IrDA SIR Mode enabled" newline bitfld.long 0x8 5. "AFCE,Auto Flow Control Enable. Writeable only when AFCE_MODE == Enabled always readable. When FIFOs are enabled and the Auto Flow Control Enable (AFCE) bit is set Auto Flow Control features are enabled as described in section 'Auto Flow Control' in.." "Auto Flow Control Mode disabled,Auto Flow Control Mode enabled" bitfld.long 0x8 4. "LOOPBACK,LoopBack Bit. This is used to put the UART into a diagnostic mode for test purposes. If operating in UART mode (SIR_MODE != Enabled OR NOT active MCR[6] set to zero) data on the sout line is held high while serial data output is looped back.." "Loopback mode disabled,Loopback mode enabled" newline bitfld.long 0x8 3. "OUT2,OUT2 . This is used to directly control the user-designated Output2 (out2_n) output. The value written to this location is inverted and driven out on out2_n. Note that in Loopback mode (MCR[4] set to one) the out2_n output is held inactive high.." "out2_n de-asserted,out2_n asserted" bitfld.long 0x8 2. "OUT1,OUT1 . This is used to directly control the user-designated Output1 (out1_n) output. The value written to this location is inverted and driven out on out1_n. Note that in Loopback mode (MCR[4] set to one) the out1_n output is held inactive high.." "out1_n de-asserted,out1_n asserted" newline bitfld.long 0x8 1. "RTS,Request to Send. This is used to directly control the Request to Send (rts_n) output. The Request To Send (rts_n) output is used to inform the modem or data set that the UART is ready to exchange data. When Auto RTS Flow Control is not enabled.." "Request to Send rts_n de-asserted,Request to Send rts_n asserted" bitfld.long 0x8 0. "DTR,Data Terminal Ready. This is used to directly control the Data Terminal Ready (dtr_n) output. The value written to this location is inverted and driven out on dtr_n. The Data Terminal Ready output is used to inform the modem or data set that the UART.." "dtr_n de-asserted,dtr_n asserted" rgroup.long 0x14++0x7 line.long 0x0 "LSR,Line Status Register Reset Value: 0x60" hexmask.long.tbyte 0x0 9.--31. 1. "RSVD_LSR_31TO9,LSR 31to9 Reserved bits read as zero." bitfld.long 0x0 8. "ADDR_RCVD,Address Received Bit. If 9Bit data mode (LCR_EXT[0]=1) is enabled this bit is used to indicate the 9th bit of the receive data is set to 1. This bit can also be used to indicate whether the incoming character is address or data. - 1 =.." "Indicates the character is data,Indicates the character is address" newline bitfld.long 0x0 7. "RFE,Receiver FIFO Error bit. This bit is only relevant when FIFO_MODE != NONE AND FIFO's are enabled (FCR[0] set to one). This is used to indicate if there is at least one parity error framing error or break indication in the FIFO. This bit is cleared.." "No error in RX FIFO,Error in RX FIFO" bitfld.long 0x0 6. "TEMT,Transmitter Empty bit. If in FIFO mode (FIFO_MODE != NONE) and FIFO's enabled (FCR[0] set to one) this bit is set whenever the Transmitter Shift Register and the FIFO are both empty. If in the non-FIFO mode or FIFO's are disabled this bit is set.." "Transmitter not empty,Transmitter empty" newline bitfld.long 0x0 5. "THRE,Transmit Holding Register Empty bit. If THRE_MODE_USER = Disabled or THRE mode is disabled (IER[7] set to zero) and regardless of FIFO's being implemented/enabled or not this bit indicates that the THR or TX FIFO is empty. This bit is set whenever.." "THRE interrupt control is disabled,THRE interrupt control is enabled" bitfld.long 0x0 4. "BI,Break Interrupt bit. This is used to indicate the detection of a break sequence on the serial input data. If in UART mode it is set whenever the serial input sin is held in a logic '0' state for longer than the sum of start time + data bits + parity.." "No break sequence detected,Break sequence detected" newline bitfld.long 0x0 3. "FE,Framing Error bit. This is used to indicate the occurrence of a framing error in the receiver. A framing error occurs when the receiver does not detect a valid STOP bit in the received data. In the FIFO mode since the framing error is associated with.." "no framing error,framing error" bitfld.long 0x0 2. "PE,Parity Error bit. This is used to indicate the occurrence of a parity error in the receiver if the Parity Enable (PEN) bit (LCR[3]) is set. In the FIFO mode since the parity error is associated with a character received it is revealed when the.." "no parity error,parity error" newline bitfld.long 0x0 1. "OE,Overrun error bit. This is used to indicate the occurrence of an overrun error. This occurs if a new data character was received before the previous data was read. In the non-FIFO mode the OE bit is set when a new character arrives in the receiver.." "no overrun error,overrun error" bitfld.long 0x0 0. "DR,Data Ready bit. This is used to indicate that the receiver contains at least one character in the RBR or the receiver FIFO. This bit is cleared when the RBR is read in the non-FIFO mode or when the receiver FIFO is empty in the FIFO mode. Reset.." "data not ready,data ready" line.long 0x4 "MSR,Whenever bits 0. 1. 2 or 3 is set to logic one. to indicate a change on the modem control inputs. a modem status interrupt will be generated if enabled via the IER regardless of when the change occurred. The bits (bits 0. 1. 3) can be set after a.." hexmask.long.tbyte 0x4 8.--31. 1. "RSVD_MSR_31TO8,MSR 31to8 Reserved bits read as 0." bitfld.long 0x4 7. "DCD,Data Carrier Detect. This is used to indicate the current state of the modem control line dcd_n. That is this bit is the complement dcd_n. When the Data Carrier Detect input (dcd_n) is asserted it is an indication that the carrier has been detected.." "dcd_n input is de-asserted,dcd_n input is asserted" newline bitfld.long 0x4 6. "RI,Ring Indicator. This is used to indicate the current state of the modem control line ri_n. That is this bit is the complement ri_n. When the Ring Indicator input (ri_n) is asserted it is an indication that a telephone ringing signal has been received.." "ri_n input is de-asserted,ri_n input is asserted" bitfld.long 0x4 5. "DSR,Data Set Ready. This is used to indicate the current state of the modem control line dsr_n. That is this bit is the complement dsr_n. When the Data Set Ready input (dsr_n) is asserted it is an indication that the modem or data set is ready to.." "dsr_n input is de-asserted,dsr_n input is asserted" newline bitfld.long 0x4 4. "CTS,Clear to Send. This is used to indicate the current state of the modem control line cts_n. That is this bit is the complement cts_n. When the Clear to Send input (cts_n) is asserted it is an indication that the modem or data set is ready to exchange.." "cts_n input is de-asserted,cts_n input is asserted" bitfld.long 0x4 3. "DDCD,Delta Data Carrier Detect. This is used to indicate that the modem control line dcd_n has changed since the last time the MSR was read. Reading the MSR clears the DDCD bit. In Loopback Mode (MCR[4] set to one) DDCD reflects changes on MCR[3].." "No change on dcd_n since last read of MSR,change on dcd_n since last read of MSR" newline bitfld.long 0x4 2. "TERI,Trailing Edge of Ring Indicator. This is used to indicate that a change on the input ri_n (from an active low to an inactive high state) has occurred since the last time the MSR was read. Reading the MSR clears the TERI bit. In Loopback Mode.." "no change on ri_n since last read of MSR,change on ri_n since last read of MSR" bitfld.long 0x4 1. "DDSR,Delta Data Set Ready. This is used to indicate that the modem control line dsr_n has changed since the last time the MSR was read. Reading the MSR clears the DDSR bit. In Loopback Mode (MCR[4] set to one) DDSR reflects changes on MCR[0] (DTR). Note.." "no change on dsr_n since last read of MSR,change on dsr_n since last read of MSR" newline bitfld.long 0x4 0. "DCTS,Delta Clear to Send. This is used to indicate that the modem control line cts_n has changed since the last time the MSR was read. Reading the MSR clears the DCTS bit. In Loopback Mode (MCR[4] set to one) DCTS reflects changes on MCR[1] (RTS). Note.." "no change on cts_n since last read of MSR,change on cts_n since last read of MSR" group.long 0x1C++0x3 line.long 0x0 "SCR,Scratchpad Register Reset Value: 0x0" hexmask.long.tbyte 0x0 8.--31. 1. "RSVD_SCR_31TO8,SCR 31to8 Reserved bits read as 0." hexmask.long.byte 0x0 0.--7. 1. "SCR,This register is for programmers to use as a temporary storage space. It has no defined purpose in the DW_apb_uart. Reset Value: 0x0" rgroup.long 0x30++0x3 line.long 0x0 "SRBR0,This register is valid only when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW = YES). If shadow registers are not implemented. this register does not exist and reading from this register address returns 0." hexmask.long.tbyte 0x0 9.--31. 1. "RSVD_SRBRN,SRBR0 31 to SRBRN_REG_SIZE Reserved bits read read as 0." hexmask.long.word 0x0 0.--8. 1. "SRBRN,Shadow Receive Buffer Register n. This is a shadow register for the RBR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains the data byte received on the serial input port.." repeat 15. (list 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x4 0x8 0xC 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 ) rgroup.long ($2+0x34)++0x3 line.long 0x0 "SRBR$1,Shadow Receive Buffer Register 1" hexmask.long.tbyte 0x0 9.--31. 1. "RSVD_SRBR1,SRBR1 31to9or8 Reserved bits read as 0." hexmask.long.word 0x0 0.--8. 1. "SRBR1,See SRBR0 description" repeat.end group.long 0x70++0x3 line.long 0x0 "FAR,FIFO Access Register" hexmask.long 0x0 1.--31. 1. "RSVD_FAR_31TO1,FAR 31to1 Reserved bits read as 0." bitfld.long 0x0 0. "FAR,Writes will have no effect when FIFO_ACCESS == No always readable. This register is use to enable a FIFO access mode for testing so that the receive FIFO can be written by the master and the transmit FIFO can be read by the master when FIFO's are.." "FIFO access mode disabled,FIFO access mode enabled" rgroup.long 0x74++0x3 line.long 0x0 "TFR,This register is valid only when the DW_apb_uart is configured to have the FIFO access test mode available (FIFO_ACCESS = YES). If not configured. this register does not exist and reading from this register address returns 0. Reset Value: 0x0'" hexmask.long.tbyte 0x0 8.--31. 1. "RSVD_TFR_31TO8,TFR 31to8 Reserved bits read as 0." hexmask.long.byte 0x0 0.--7. 1. "TFR,Transmit FIFO Read. These bits are only valid when FIFO access mode is enabled (FAR[0] is set to one). When FIFO's are implemented and enabled reading this register gives the data at the top of the transmit FIFO. Each consecutive read pops the.." group.long 0x78++0x3 line.long 0x0 "RFW,This register is valid only when the DW_apb_uart is configured to have the FIFO access test mode available (FIFO_ACCESS = YES). If not configured. this register does not exist and reading from this register address returns 0. Reset Value: 0x0'" hexmask.long.tbyte 0x0 10.--31. 1. "RSVD_RFW_31TO10,RFW 31to10 Reserved bits read as 0." bitfld.long 0x0 9. "RFFE,Receive FIFO Framing Error. These bits are only valid when FIFO access mode is enabled (FAR[0] is set to one). When FIFO's are implemented and enabled this bit is used to write framing error detection information to the receive FIFO. When FIFO's.." "Frame error disabled,Frame error enabled" newline bitfld.long 0x0 8. "RFPE,Receive FIFO Parity Error. These bits are only valid when FIFO access mode is enabled (FAR[0] is set to one). When FIFO's are implemented and enabled this bit is used to write parity error detection information to the receive FIFO. When FIFO's are.." "Parity error disabled,Parity error enabled" hexmask.long.byte 0x0 0.--7. 1. "RFWD,Receive FIFO Write Data. These bits are only valid when FIFO access mode is enabled (FAR[0] is set to one). When FIFO's are implemented and enabled the data that is written to the RFWD is pushed into the receive FIFO. Each consecutive write pushes.." rgroup.long 0x7C++0xB line.long 0x0 "USR,UART Status register. Reset Value: 0x6" hexmask.long 0x0 5.--31. 1. "RSVD_USR_31TO5,USR 31to5 Reserved bits read as 0." bitfld.long 0x0 4. "RFF,Receive FIFO Full. This bit is only valid when FIFO_STAT == YES. This is used to indicate that the receive FIFO is completely full. That is: This bit is cleared when the RX FIFO is no longer full. Reset Value: 0x0 0x1: Receive FIFO full 0x0: Receive.." "Receive FIFO not full,Receive FIFO full" newline bitfld.long 0x0 3. "RFNE,Receive FIFO Not Empty. This bit is only valid when FIFO_STAT == YES. This is used to indicate that the receive FIFO contains one or more entries. This bit is cleared when the RX FIFO is empty. Reset Value: 0x0 0x0: Receive FIFO is empty 0x1:.." "Receive FIFO is empty,Receive FIFO is not empty" bitfld.long 0x0 2. "TFE,Transmit FIFO Empty. This bit is only valid when FIFO_STAT == YES. This is used to indicate that the transmit FIFO is completely empty. This bit is cleared when the TX FIFO is no longer empty. Reset Value: 0x1 0x1: Transmit FIFO is empty 0x0:.." "Transmit FIFO is not empty,Transmit FIFO is empty" newline bitfld.long 0x0 1. "TFNF,Transmit FIFO Not Full. This bit is only valid when FIFO_STAT == YES. This is used to indicate that the transmit FIFO in not full. This bit is cleared when the TX FIFO is full. Reset Value: 0x1 0x0: Transmit FIFO is full 0x1: Transmit FIFO is not full" "Transmit FIFO is full,Transmit FIFO is not full" bitfld.long 0x0 0. "RSVD_BUSY,UART Busy. This bit is only valid when UART_16550_COMPATIBLE == YES. This indicates that a serial transfer is in progress when cleared indicates that the DW_apb_uart is idle or inactive. This bit will be set to 1 (busy) under any of the.." "DW_apb_uart is idle or inactive,DW_apb_uart is busy" line.long 0x4 "TFL,TFL register is valid only when the DW_apb_uart is configured to have additional FIFO status registers implemented (FIFO_STAT = YES). If status registers are not implemented. this register does not exist and reading from this register address returns.." hexmask.long 0x4 6.--31. 1. "RSVD_TFL_31TOADDR_WIDTH,TFL 31 to ADDR_WIDTH Reserved bits read as 0." hexmask.long.byte 0x4 0.--5. 1. "TFL,Transmit FIFO Level. This indicates the number of data entries in the transmit FIFO. Reset Value: 0x0" line.long 0x8 "RFL,RFL register is valid only when the DW_apb_uart is configured to have additional FIFO status registers implemented (FIFO_STAT = YES). If status registers are not implemented. this register does not exist and reading from this register address returns.." hexmask.long 0x8 6.--31. 1. "RSVD_RFL_31TOADDR_WIDTH,RFL 31 to ADDR_WIDTH Reserved bits read as 0." hexmask.long.byte 0x8 0.--5. 1. "RFL,Receive FIFO Level. This is indicates the number of data entries in the receive FIFO. Reset Value: 0x0" group.long 0x88++0x47 line.long 0x0 "SRR,This register is valid only when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW = YES). If shadow registers are not implemented. this register does not exist and reading from this register address returns 0. For.." hexmask.long 0x0 3.--31. 1. "RSVD_SRR_31TO3,SRR 31to3 Reserved bits read as 0." bitfld.long 0x0 2. "XFR,XMIT FIFO Reset. Writes will have no effect when FIFO_MODE == NONE. This is a shadow register for the XMIT FIFO Reset bit (FCR[2]). This can be used to remove the burden on software having to store previously written FCR values (which are pretty.." "0,1" newline bitfld.long 0x0 1. "RFR,RCVR FIFO Reset. Writes will have no effect when FIFO_MODE == NONE. This is a shadow register for the RCVR FIFO Reset bit (FCR[1]). This can be used to remove the burden on software having to store previously written FCR values (which are pretty.." "0,1" bitfld.long 0x0 0. "UR,UART Reset. This asynchronously resets the DW_apb_uart and synchronously removes the reset assertion. For a two clock implementation both pclk and sclk domains will be reset. Reset Value: 0x0 0x0: No Uart Reset 0x1: Uart reset" "No Uart Reset,Uart reset" line.long 0x4 "SRTS,SRTS register is valid only when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW = YES). If shadow registers are not implemented. this register does not exist and reading from this register address returns 0." hexmask.long 0x4 1.--31. 1. "RSVD_SRTS_31TO1,SRTS 31to1 Reserved bits read as 0." bitfld.long 0x4 0. "SRTS,Shadow Request to Send. This is a shadow register for the RTS bit (MCR[1]) this can be used to remove the burden of having to performing a read modify write on the MCR. This is used to directly control the Request to Send (rts_n) output. The.." "Shadow Request to Send uart_rts_n logic1,Shadow Request to Send uart_rts_n logic0" line.long 0x8 "SBCR,SBCR register is valid only when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW = YES). If shadow registers are not implemented. this register does not exist and reading from this register address returns 0." hexmask.long 0x8 1.--31. 1. "RSVD_SBCR_31TO1,SBCR 31to1 Reserved bits read as 0." bitfld.long 0x8 0. "SBCB,Shadow Break Control Bit. This is a shadow register for the Break bit (LCR[6]) this can be used to remove the burden of having to performing a read modify write on the LCR. This is used to cause a break condition to be transmitted to the receiving.." "No spacing on serial output,Serial output forced to the spacing" line.long 0xC "SDMAM,This register is valid only when the DW_apb_uart is configured to have additional FIFO registers implemented (FIFO_MODE != None) and additional shadow registers implemented (SHADOW = YES). If these registers are not implemented. this register does.." hexmask.long 0xC 1.--31. 1. "RSVD_SDMAM_31TO1,SDMAM 31to1 Reserved bits read as 0." bitfld.long 0xC 0. "SDMAM,Shadow DMA Mode. This is a shadow register for the DMA mode bit (FCR[3]). This can be used to remove the burden of having to store the previously written value to the FCR in memory and having to mask this value so that only the DMA Mode bit gets.." "Mode 0,Mode 1" line.long 0x10 "SFE,SFE register is valid only when the DW_apb_uart is configured to have additional FIFO registers implemented (FIFO_MODE != None) and additional shadow registers implemented (SHADOW = YES). If these registers are not implemented. this register does not.." hexmask.long 0x10 1.--31. 1. "RSVD_SFE_31TO1,SFE 31to1 Reserved bits read as 0." bitfld.long 0x10 0. "SFE,Shadow FIFO Enable. This is a shadow register for the FIFO enable bit (FCR[0]). This can be used to remove the burden of having to store the previously written value to the FCR in memory and having to mask this value so that only the FIFO enable bit.." "FIFOs are disabled,FIFOs are enabled" line.long 0x14 "SRT,SRT register is valid only when the DW_apb_uart is configured to have additional FIFO registers implemented (FIFO_MODE != None) and additional shadow registers implemented (SHADOW = YES). If these registers are not implemented. this register does not.." hexmask.long 0x14 2.--31. 1. "RSVD_SRT_31TO2,SRT 31to2 Reserved bits read as 0." bitfld.long 0x14 0.--1. "SRT,Shadow RCVR Trigger. This is a shadow register for the RCVR trigger bits (FCR[7:6]). This can be used to remove the burden of having to store the previously written value to the FCR in memory and having to mask this value so that only the RCVR.." "?,FIFO 1/4 full,FIFO 1/2 full,FIFO 2 less than full" line.long 0x18 "STET,This register is valid only when the DW_apb_uart is configured to have FIFOs implemented (FIFO_MODE != NONE) and THRE interrupt support implemented (THRE_MODE_USER = Enabled) and additional shadow registers implemented (SHADOW = YES). If FIFOs are.." hexmask.long 0x18 2.--31. 1. "RSVD_STET_31TO2,STET 31to2 Reserved bits read as 0." bitfld.long 0x18 0.--1. "STET,Shadow TX Empty Trigger. This is a shadow register for the TX empty trigger bits (FCR[5:4]). This can be used to remove the burden of having to store the previously written value to the FCR in memory and having to mask this value so that only the TX.." "FIFO empty,?,FIFO 1/4 full,FIFO 1/2 full" line.long 0x1C "HTX,Halt TX Reset Value: 0x0" hexmask.long 0x1C 1.--31. 1. "RSVD_HTX_31TO1,HTX 31to1 Reserved bits read as 0." bitfld.long 0x1C 0. "HTX,Halt TX. Writes will have no effect when FIFO_MODE == NONE always readable. This register is use to halt transmissions for testing so that the transmit FIFO can be filled by the master when FIFO's are implemented and enabled. Note if FIFO's are.." "Halt Transmission disabled,Halt Transmission enabled" line.long 0x20 "DMASA,DMA Software Acknowledge Register Reset Value: 0x0" hexmask.long 0x20 1.--31. 1. "RSVD_DMASA_31TO1,DMASA 31to1 Reserved bits read as 0." bitfld.long 0x20 0. "DMASA,DMA Software Acknowledge. Writes will have no effect when DMA_EXTRA == No. This register is use to perform DMA software acknowledge if a transfer needs to be terminated due to an error condition. For example if the DMA disables the channel then.." "?,DMA software acknowledge" line.long 0x24 "TCR,This register is used to enable or disable RS485 mode and also control the polarity values for Driven enable (de) and Receiver Enable (re) signals. This register is only valid when the DW_apb_uart is configured to have RS485 interface implemented.." hexmask.long 0x24 5.--31. 1. "RSVD_TCR_31TO5,TCR 31to5 Reserved bits read as 0." bitfld.long 0x24 3.--4. "XFER_MODE,Transfer Mode. - 0: In this mode transmit and receive can happen simultaneously. The user can enable DE_EN RE_EN at any point of time. Turn around timing as programmed in the TAT register is not applicable in this mode. - 1: In this mode DE.." "In this mode,In this mode,In this mode,?" newline bitfld.long 0x24 2. "DE_POL,Driver Enable Polarity. - 1: DE signal is active high - 0: DE signal is active low Reset Value: UART_DE_POL" "DE signal is active low,DE signal is active high" bitfld.long 0x24 1. "RE_POL,Receiver Enable Polarity. - 1: RE signal is active high - 0: RE signal is active low Reset Value: UART_RE_POL" "RE signal is active low,RE signal is active high" newline bitfld.long 0x24 0. "RS485_EN,RS485 Transfer Enable. - 0 : In this mode the transfers are still in the RS232 mode. All other fields in this register are reserved and register DE_EN/RE_EN/TAT are also reserved. - 1 : In this mode the transfers will happen in RS485 mode. All.." "In this mode,In this mode" line.long 0x28 "DE_EN,The Driver Output Enable Register (DE_EN) is used to control the assertion and de-assertion of the DE signal. This register is only valid when the DW_apb_uart is configured to have RS485 interface implemented (UART_RS485_INTERFACE_EN = ENABLED). If.." hexmask.long 0x28 1.--31. 1. "RSVD_DE_EN_31TO1,DE_EN 31to1 Reserved bits read as 0." bitfld.long 0x28 0. "DE_ENABLE,DE Enable control. The 'DE Enable' register bit is used to control assertion and de-assertion of 'de' signal. - 0: De-assert 'de' signal - 1: Assert 'de' signal Reset Value: 0x0" "De-assert 'de' signal,Assert 'de' signal" line.long 0x2C "RE_EN,The Receiver Output Enable Register (RE_EN) is used to control the assertion and de-assertion of the RE signal. This register is only valid when the DW_apb_uart is configured to have RS485 interface implemented (UART_RS485_INTERFACE_EN = ENABLED)." hexmask.long 0x2C 1.--31. 1. "RSVD_RE_EN_31TO1,RE_EN 31to1 Reserved bits read as 0." bitfld.long 0x2C 0. "RE_ENABLE,RE Enable control. The 'RE Enable' register bit is used to control assertion and de-assertion of 're' signal. - 0: De-assert 're' signal - 1: Assert 're' signal Reset Value: 0x0" "De-assert 're' signal,Assert 're' signal" line.long 0x30 "DET,The Driver Output Enable Timing Register (DET) is used to control the DE assertion and de-assertion timings of 'de' signal. This register is only valid when the DW_apb_uart is configured to have RS485 interface implemented (UART_RS485_INTERFACE =.." hexmask.long.byte 0x30 24.--31. 1. "RSVD_DE_DEAT_31TO24,DET 31to24 Reserved bits read as 0." hexmask.long.byte 0x30 16.--23. 1. "DE_DE-ASSERTION_TIME,Driver Enable de-assertion time. This field controls the amount of time (in terms of number of serial clock periods) between the end of stop bit on the sout to the falling edge of Driver output enable signal. Reset Value: 0x0" newline hexmask.long.byte 0x30 8.--15. 1. "RSVD_DE_AT_15TO8,DET 15to8 Reserved bits read as 0." hexmask.long.byte 0x30 0.--7. 1. "DE_ASSERTION_TIME,Driver Enable assertion time. This field controls the amount of time (in terms of number of serial clock periods) between the assertion of rising edge of Driver output enable signal to serial transmit enable. Any data in transmit buffer.." line.long 0x34 "TAT,The TurnAround Timing Register (TAT) is used to hold the turnaround time between switching of 're' and 'de' signals. This register is only valid when the DW_apb_uart is configured to have the RS485 interface implemented (UART_RS485_INTERFACE_EN =.." hexmask.long.word 0x34 16.--31. 1. "RE_TO_DE,Receiver Enable to Driver Enable TurnAround time. Turnaround time (in terms of serial clock) for RE De-assertion to DE assertion. Note: - If the DE assertion time in the DET register is 0 then the actual value is the programmed value + 3. - If.." hexmask.long.word 0x34 0.--15. 1. "DE_TO_RE,Driver Enable to Receiver Enable TurnAround time. Turnaround time (in terms of serial clock) for DE De-assertion to RE assertion. Note: The actual time is the programmed value + 1. Reset Value: 0x0" line.long 0x38 "DLF,This register is only valid when the DW_apb_uart is configured to have Fractional Baud rate Divisor implemented (FRACTIONAL_BAUD_DIVISOR_EN = ENABLED). If Fractional Baud rate divisor is not implemented. this register does not exist and reading from.." hexmask.long 0x38 4.--31. 1. "RSVD_DLF,DLF 31 to DLF_SIZE Reserved bits read as 0." hexmask.long.byte 0x38 0.--3. 1. "DLF,Fractional part of divisor. The fractional value is added to integer value set by DLH DLL. Fractional value is determined by (Divisor Fraction value)/(2^DLF_SIZE). For information on DLF values to be programmed for DLF_SIZE=4 see the 'Fractional.." line.long 0x3C "RAR,Receive Address Register Reset Value: 0x0" hexmask.long.tbyte 0x3C 8.--31. 1. "RSVD_RAR_31TO8,RAR 31to8 Reserved bits read as 0." hexmask.long.byte 0x3C 0.--7. 1. "RAR,This is an address matching register during receive mode. If the 9-th bit is set in the incoming character then the remaining 8-bits will be checked against this register value. If the match happens then sub-sequent characters with 9-th bit set to 0.." line.long 0x40 "TAR,Transmit Address Register Reset Value: 0x0" hexmask.long.tbyte 0x40 8.--31. 1. "RSVD_TAR_31TO8,TAR 31to8 Reserved bits read as 0." hexmask.long.byte 0x40 0.--7. 1. "TAR,This is an address matching register during transmit mode. If DLS_E (LCR_EXT[0]) bit is enabled then DW_apb_uart will send the 9-bit character with 9-th bit set to 1 and remaining 8-bit address will be sent from this register provided 'SEND_ADDR'.." line.long 0x44 "LCR_EXT,Line Extended Control Register Reset Value: 0x0" hexmask.long 0x44 4.--31. 1. "RSVD_LCR_EXT,LCR_EXT 31to4 Reserved bits read as 0." bitfld.long 0x44 3. "TRANSMIT_MODE,Transmit mode control bit. This bit is used to control the type of transmit mode during 9-bit data transfers. - 1: In this mode of operation Transmit Holding Register (THR) and Shadow Transmit Holding Register (STHR) are 9-bit wide. The.." "In this mode of operation,In this mode of operation" newline bitfld.long 0x44 2. "SEND_ADDR,Send address control bit. This bit is used as a control knob for the user to determine when to send the address during transmit mode. - 1 = 9-bit character will be transmitted with 9-th bit set to 1 and the remaining 8-bits will match to what.." "0,1" bitfld.long 0x44 1. "ADDR_MATCH,Address Match Mode.This bit is used to enable the address match feature during receive. - 1 = Address match mode; DW_apb_uart will wait until the incoming character with 9-th bit set to 1. And further checks to see if the address matches with.." "Normal mode; DW_apb_uart will start to receive..,Address match mode; DW_apb_uart will wait until.." newline bitfld.long 0x44 0. "DLS_E,Extension for DLS. This bit is used to enable 9-bit data for transmit and receive transfers. Reset Value: 0x0" "0,1" rgroup.long 0xF4++0xB line.long 0x0 "CPR,Component Parameter Register.This register is valid only when UART_ADD_ENCODED_PARAMS = 1. If the UART_ADD_ENCODED_PARAMS parameter is not set. this register does not exist and reading from this register address returns 0. Reset Value:.." hexmask.long.byte 0x0 24.--31. 1. "RSVD_CPR_31TO24,CPR 31to24 Reserved bits read as 0." hexmask.long.byte 0x0 16.--23. 1. "FIFO_MODE,Encoding of FIFO_MODE configuration parameter value. 0x0: FIFO mode is 0 0x40: FIFO mode is 1024 0x8: FIFO mode is 128 0x1: FIFO mode is 16 0x80: FIFO mode is 2048 0x10: FIFO mode is 256 0x2: FIFO mode is 32 0x20: FIFO mode is 512 0x4: FIFO.." newline bitfld.long 0x0 14.--15. "RSVD_CPR_15TO14,CPR 15to14 Reserved bits read as 0." "0,1,2,3" bitfld.long 0x0 13. "DMA_EXTRA,Encoding of DMA_EXTRA configuration parameter value. 0x0: DMA_EXTRA disabled 0x1: DMA_EXTRA enabled" "DMA_EXTRA disabled,DMA_EXTRA enabled" newline bitfld.long 0x0 12. "UART_ADD_ENCODED_PARAMS,Encoding of UART_ADD_ENCODED_PARAMS configuration parameter value. 0x0: UART_ADD_ENCODED_PARAMS disabled 0x1: UART_ADD_ENCODED_PARAMS enabled" "UART_ADD_ENCODED_PARAMS disabled,UART_ADD_ENCODED_PARAMS enabled" bitfld.long 0x0 11. "SHADOW,Encoding of SHADOW configuration parameter value. 0x0: SHADOW disabled 0x1: SHADOW enabled" "SHADOW disabled,SHADOW enabled" newline bitfld.long 0x0 10. "FIFO_STAT,Encoding of FIFO_STAT configuration parameter value. 0x0: FIFO_STAT disabled 0x1: FIFO_STAT enabled" "FIFO_STAT disabled,FIFO_STAT enabled" bitfld.long 0x0 9. "FIFO_ACCESS,Encoding of FIFO_ACCESS configuration parameter value. 0x0: FIFO_ACCESS disabled 0x1: FIFO ACCESS enabled" "FIFO_ACCESS disabled,FIFO ACCESS enabled" newline bitfld.long 0x0 8. "ADDITIONAL_FEAT,Encoding of ADDITIONAL_FEATURES configuration parameter value. 0x0: Additional features disabled 0x1: Additional features enabled" "Additional features disabled,Additional features enabled" bitfld.long 0x0 7. "SIR_LP_MODE,Encoding of SIR_LP_MODE configuration parameter value. 0x0: SIR_LP mode disabled 0x1: SIR_LP mode enabled" "SIR_LP mode disabled,SIR_LP mode enabled" newline bitfld.long 0x0 6. "SIR_MODE,Encoding of SIR_MODE configuration parameter value. 0x0: SIR mode disabled 0x1: SIR mode enabled" "SIR mode disabled,SIR mode enabled" bitfld.long 0x0 5. "THRE_MODE,Encoding of THRE_MODE configuration parameter value. 0x0: THRE mode disabled 0x1: THRE mode enabled" "THRE mode disabled,THRE mode enabled" newline bitfld.long 0x0 4. "AFCE_MODE,Encoding of AFCE_MODE configuration parameter value. 0x0: AFCE mode disabled 0x1: AFCE mode enabled" "AFCE mode disabled,AFCE mode enabled" bitfld.long 0x0 2.--3. "RSVD_CPR_3TO2,CPR 3to2 Reserved bits read as 0." "0,1,2,3" newline bitfld.long 0x0 0.--1. "APB_DATA_WIDTH,Encoding of APB_DATA_WIDTH configuration parameter value. 0x1: APB data width is 16 bits 0x2: APB data width is 32 bits 0x0: APB data width is 8 bits" "APB data width is 8 bits,APB data width is 16 bits,APB data width is 32 bits,?" line.long 0x4 "UCV,This register is valid only when the DW_apb_uart is configured to have additional features implemented (ADDITIONAL_FEATURES = YES). If additional features are not implemented. this register does not exist and reading from this register address.." hexmask.long 0x4 0.--31. 1. "UART_COMPONENT_VERSION,ASCII value for each number in the version followed by *. For example 32_30_31_2A represents the version 2.01*" line.long 0x8 "CTR,This register is valid only when the DW_apb_uart is configured to have additional features implemented (ADDITIONAL_FEATURES = YES). If additional features are not implemented. this register does not exist and reading from this register address.." hexmask.long 0x8 0.--31. 1. "PERIPHERAL_ID,This register contains the peripherals identification code. Reset Value: 0x44570110" tree.end repeat.end repeat 8. (increment 9. 1.) (list ad:0x304C0000 ad:0x304D0000 ad:0x304E0000 ad:0x304F0000 ad:0x30500000 ad:0x30510000 ad:0x30520000 ad:0x30530000) tree "UART$1" base $2 group.long 0x0++0x3 line.long 0x0 "RBR,Receive Buffer Register" hexmask.long.tbyte 0x0 9.--31. 1. "RSVD_THR,RBR 31to9or8 Reserved bits and read as zero (0)" group.long 0x0++0x3 line.long 0x0 "DLL,Divisor Latch Low Register. Reset Value: 0x0" hexmask.long.tbyte 0x0 8.--31. 1. "RSVD_DLL_31TO8,DLL 31to8 Reserved bits and read as zero (0). Exists: Always" hexmask.long.byte 0x0 0.--7. 1. "DLL,Divisor Latch (Low). This register makes up the lower 8-bits of a 16-bit read/write. Divisor Latch register that contains the baud rate divisor for the UART. The output baud rate is equal to the serial clock frequency divided by sixteen times the.." group.long 0x0++0x7 line.long 0x0 "THR,Transmitting Holding Register" hexmask.long.tbyte 0x0 9.--31. 1. "RSVD_THR,THR 31to9 Reserved bits and read as zero (0). Exists: Always" hexmask.long.word 0x0 0.--8. 1. "THR,Tansmit Holding Register. This register contains data to be transmitted on the serial output port (sout) in UART mode or the serial infrared output (sir_out_n) in infrared mode. Data should only be written to the THR when the THR Empty (THRE) bit.." line.long 0x4 "DLH,Divisor Latch High Register." hexmask.long.tbyte 0x4 9.--31. 1. "RSVD_THR,THR 31to9 Reserved bits and read as zero (0). Exists: Always" hexmask.long.word 0x4 0.--8. 1. "THR,Tansmit Holding Register. This register contains data to be transmitted on the serial output port (sout) in UART mode or the serial infrared output (sir_out_n) in infrared mode. Data should only be written to the THR when the THR Empty (THRE) bit.." group.long 0x4++0x7 line.long 0x0 "DLH,Divisor Latch High Register." hexmask.long.tbyte 0x0 9.--31. 1. "RSVD_THR,THR 31to9 Reserved bits and read as zero (0). Exists: Always" hexmask.long.word 0x0 0.--8. 1. "THR,Tansmit Holding Register. This register contains data to be transmitted on the serial output port (sout) in UART mode or the serial infrared output (sir_out_n) in infrared mode. Data should only be written to the THR when the THR Empty (THRE) bit.." line.long 0x4 "FCR,FIFO Control Register." hexmask.long.tbyte 0x4 8.--31. 1. "RSVD_FCR,FCR 31to8 Reserved bits and read as zero (0). Exist: Always" bitfld.long 0x4 6.--7. "RT,RCVR Trigger (or RT). This is used to select the trigger level in the receiver FIFO at which the Received Data Available Interrupt will be generated. In auto flow control mode it is used to determine when the rts_n signal will be de-asserted only.." "0,1,2,3" newline bitfld.long 0x4 4.--5. "TET,RCVR Trigger (or RT). This is used to select the trigger level in the receiver FIFO at which the Received Data Available Interrupt will be generated. In auto flow control mode it is used to determine when the rts_n signal will be de-asserted only.." "0,1,2,3" bitfld.long 0x4 3. "DMAM,DMA Mode or (DMAM). This determines the DMA signalling mode used for the dma_tx_req_n and dma_rx_req_n output signals. Values: - 0x0 (MODE0): Mode 0 - 0x1 (MODE1): Mode 1 Exists: Always" "0,1" newline bitfld.long 0x4 2. "XFIFOR,XMIT FIFO Reset (or XFIFOR). This resets the control portion of the transmit FIFO and treats the FIFO as empty. This will also de-assert the DMA TX request and single signals. Note that this bit is 'self-clearing' and it is not necessary to clear.." "0,1" bitfld.long 0x4 1. "RFIFOR,RCVR FIFO Reset (or RFIFOR). This resets the control portion of the receive FIFO and treats the FIFO as empty. This will also de-assert the DMA RX request and single signals. Note that this bit is 'self-clearing' and it is not necessary to clear.." "0,1" newline bitfld.long 0x4 0. "FIFOE,FIFO Enable (or FIFOE). This enables/disables the transmit (XMIT) and receive (RCVR) FIFOs. Whenever the value of this bit is changed both the XMIT and RCVR controller portion of FIFOs is reset. Values: - 0x0 (DISABLED): FIFO is disabled - 0x1.." "0,1" group.long 0x8++0xB line.long 0x0 "FCR,FIFO Control Register." hexmask.long.tbyte 0x0 8.--31. 1. "RSVD_FCR,FCR 31to8 Reserved bits and read as zero (0). Exist: Always" bitfld.long 0x0 6.--7. "RT,RCVR Trigger (or RT). This is used to select the trigger level in the receiver FIFO at which the Received Data Available Interrupt will be generated. In auto flow control mode it is used to determine when the rts_n signal will be de-asserted only.." "0,1,2,3" newline bitfld.long 0x0 4.--5. "TET,RCVR Trigger (or RT). This is used to select the trigger level in the receiver FIFO at which the Received Data Available Interrupt will be generated. In auto flow control mode it is used to determine when the rts_n signal will be de-asserted only.." "0,1,2,3" bitfld.long 0x0 3. "DMAM,DMA Mode or (DMAM). This determines the DMA signalling mode used for the dma_tx_req_n and dma_rx_req_n output signals. Values: - 0x0 (MODE0): Mode 0 - 0x1 (MODE1): Mode 1 Exists: Always" "0,1" newline bitfld.long 0x0 2. "XFIFOR,XMIT FIFO Reset (or XFIFOR). This resets the control portion of the transmit FIFO and treats the FIFO as empty. This will also de-assert the DMA TX request and single signals. Note that this bit is 'self-clearing' and it is not necessary to clear.." "0,1" bitfld.long 0x0 1. "RFIFOR,RCVR FIFO Reset (or RFIFOR). This resets the control portion of the receive FIFO and treats the FIFO as empty. This will also de-assert the DMA RX request and single signals. Note that this bit is 'self-clearing' and it is not necessary to clear.." "0,1" newline bitfld.long 0x0 0. "FIFOE,FIFO Enable (or FIFOE). This enables/disables the transmit (XMIT) and receive (RCVR) FIFOs. Whenever the value of this bit is changed both the XMIT and RCVR controller portion of FIFOs is reset. Values: - 0x0 (DISABLED): FIFO is disabled - 0x1.." "0,1" line.long 0x4 "LCR,Line Control Register Reset Value: 0x0" hexmask.long.tbyte 0x4 8.--31. 1. "RSVD_LCR_31TO8,LCR 31to8 Reserved bits and read as 0." bitfld.long 0x4 7. "DLAB,Divisor Latch Access Bit. If UART_16550_COMPATIBLE == NO then writeable only when UART is not busy (USR[0]is zero) otherwise always writable and always readable. This bit is used to enable reading and writing of the Divisor Latch register (DLL and.." "Divisor Latch register is writable only when..,?" newline bitfld.long 0x4 6. "BC,Break Control Bit. This is used to cause a break condition to be transmitted to the receiving device. If set to one the serial output is forced to the spacing (logic 0) state. When not in Loopback Mode as determined by MCR[4] the sout line is forced.." "Serial output is released for data transmission,Serial output is forced to spacing state" bitfld.long 0x4 5. "SP,Stick Parity. If UART_16550_COMPATIBLE = NO then writeable only when UART is not busy (USR[0] is 0); otherwise always writable and always readable. This bit is used to force parity value. When PEN EPS and Stick Parity are set to 1 the parity bit is.." "Stick parity disabled,Stick parity enabled" newline bitfld.long 0x4 4. "EPS,Even Parity Select. If UART_16550_COMPATIBLE == NO then writeable only when UART is not busy (USR[0] is zero) otherwise always writable and always readable. This is used to select between even and odd parity when parity is enabled (PEN set to.." "an odd parity is transmitted or checked,an even parity is transmitted or checked" bitfld.long 0x4 3. "PEN,Parity Enable. If UART_16550_COMPATIBLE == NO then writeable only when UART is not busy (USR[0] is zero) otherwise always writable and always readable. This bit is used to enable and disable parity generation and detection in transmitted and.." "disable parity,enable parity" newline bitfld.long 0x4 2. "STOP,Number of stop bits. If UART_16550_COMPATIBLE == NO then writeable only when UART is not busy (USR[0] is zero) otherwise always writable and always readable. This is used to select the number of stop bits per character that the peripheral will.." "0,1" bitfld.long 0x4 0.--1. "DLS,Data Length Select (or CLS as used in legacy). If UART_16550_COMPATIBLE == NO then writeable only when UART is not busy (USR[0] is zero) otherwise always writable and always readable. When DLS_E in LCR_EXT is set to 0 this register is used to.." "0,1,2,3" line.long 0x8 "MCR,Modem Control Register Reset Value: 0x0" hexmask.long 0x8 7.--31. 1. "RSVD_MCR_31TO7,MCR 31to7 Reserved bits read as 0." bitfld.long 0x8 6. "SIRE,SIR Mode Enable. Writeable only when SIR_MODE == Enabled always readable. This is used to enable/disable the IrDA SIR Mode features as described in section 'IrDA 1.0 SIR Protocol' in the databook. Note: To enable SIR mode write the appropriate.." "IrDA SIR Mode disabled,IrDA SIR Mode enabled" newline bitfld.long 0x8 5. "AFCE,Auto Flow Control Enable. Writeable only when AFCE_MODE == Enabled always readable. When FIFOs are enabled and the Auto Flow Control Enable (AFCE) bit is set Auto Flow Control features are enabled as described in section 'Auto Flow Control' in.." "Auto Flow Control Mode disabled,Auto Flow Control Mode enabled" bitfld.long 0x8 4. "LOOPBACK,LoopBack Bit. This is used to put the UART into a diagnostic mode for test purposes. If operating in UART mode (SIR_MODE != Enabled OR NOT active MCR[6] set to zero) data on the sout line is held high while serial data output is looped back.." "Loopback mode disabled,Loopback mode enabled" newline bitfld.long 0x8 3. "OUT2,OUT2 . This is used to directly control the user-designated Output2 (out2_n) output. The value written to this location is inverted and driven out on out2_n. Note that in Loopback mode (MCR[4] set to one) the out2_n output is held inactive high.." "out2_n de-asserted,out2_n asserted" bitfld.long 0x8 2. "OUT1,OUT1 . This is used to directly control the user-designated Output1 (out1_n) output. The value written to this location is inverted and driven out on out1_n. Note that in Loopback mode (MCR[4] set to one) the out1_n output is held inactive high.." "out1_n de-asserted,out1_n asserted" newline bitfld.long 0x8 1. "RTS,Request to Send. This is used to directly control the Request to Send (rts_n) output. The Request To Send (rts_n) output is used to inform the modem or data set that the UART is ready to exchange data. When Auto RTS Flow Control is not enabled.." "Request to Send rts_n de-asserted,Request to Send rts_n asserted" bitfld.long 0x8 0. "DTR,Data Terminal Ready. This is used to directly control the Data Terminal Ready (dtr_n) output. The value written to this location is inverted and driven out on dtr_n. The Data Terminal Ready output is used to inform the modem or data set that the UART.." "dtr_n de-asserted,dtr_n asserted" rgroup.long 0x14++0x7 line.long 0x0 "LSR,Line Status Register Reset Value: 0x60" hexmask.long.tbyte 0x0 9.--31. 1. "RSVD_LSR_31TO9,LSR 31to9 Reserved bits read as zero." bitfld.long 0x0 8. "ADDR_RCVD,Address Received Bit. If 9Bit data mode (LCR_EXT[0]=1) is enabled this bit is used to indicate the 9th bit of the receive data is set to 1. This bit can also be used to indicate whether the incoming character is address or data. - 1 =.." "Indicates the character is data,Indicates the character is address" newline bitfld.long 0x0 7. "RFE,Receiver FIFO Error bit. This bit is only relevant when FIFO_MODE != NONE AND FIFO's are enabled (FCR[0] set to one). This is used to indicate if there is at least one parity error framing error or break indication in the FIFO. This bit is cleared.." "No error in RX FIFO,Error in RX FIFO" bitfld.long 0x0 6. "TEMT,Transmitter Empty bit. If in FIFO mode (FIFO_MODE != NONE) and FIFO's enabled (FCR[0] set to one) this bit is set whenever the Transmitter Shift Register and the FIFO are both empty. If in the non-FIFO mode or FIFO's are disabled this bit is set.." "Transmitter not empty,Transmitter empty" newline bitfld.long 0x0 5. "THRE,Transmit Holding Register Empty bit. If THRE_MODE_USER = Disabled or THRE mode is disabled (IER[7] set to zero) and regardless of FIFO's being implemented/enabled or not this bit indicates that the THR or TX FIFO is empty. This bit is set whenever.." "THRE interrupt control is disabled,THRE interrupt control is enabled" bitfld.long 0x0 4. "BI,Break Interrupt bit. This is used to indicate the detection of a break sequence on the serial input data. If in UART mode it is set whenever the serial input sin is held in a logic '0' state for longer than the sum of start time + data bits + parity.." "No break sequence detected,Break sequence detected" newline bitfld.long 0x0 3. "FE,Framing Error bit. This is used to indicate the occurrence of a framing error in the receiver. A framing error occurs when the receiver does not detect a valid STOP bit in the received data. In the FIFO mode since the framing error is associated with.." "no framing error,framing error" bitfld.long 0x0 2. "PE,Parity Error bit. This is used to indicate the occurrence of a parity error in the receiver if the Parity Enable (PEN) bit (LCR[3]) is set. In the FIFO mode since the parity error is associated with a character received it is revealed when the.." "no parity error,parity error" newline bitfld.long 0x0 1. "OE,Overrun error bit. This is used to indicate the occurrence of an overrun error. This occurs if a new data character was received before the previous data was read. In the non-FIFO mode the OE bit is set when a new character arrives in the receiver.." "no overrun error,overrun error" bitfld.long 0x0 0. "DR,Data Ready bit. This is used to indicate that the receiver contains at least one character in the RBR or the receiver FIFO. This bit is cleared when the RBR is read in the non-FIFO mode or when the receiver FIFO is empty in the FIFO mode. Reset.." "data not ready,data ready" line.long 0x4 "MSR,Whenever bits 0. 1. 2 or 3 is set to logic one. to indicate a change on the modem control inputs. a modem status interrupt will be generated if enabled via the IER regardless of when the change occurred. The bits (bits 0. 1. 3) can be set after a.." hexmask.long.tbyte 0x4 8.--31. 1. "RSVD_MSR_31TO8,MSR 31to8 Reserved bits read as 0." bitfld.long 0x4 7. "DCD,Data Carrier Detect. This is used to indicate the current state of the modem control line dcd_n. That is this bit is the complement dcd_n. When the Data Carrier Detect input (dcd_n) is asserted it is an indication that the carrier has been detected.." "dcd_n input is de-asserted,dcd_n input is asserted" newline bitfld.long 0x4 6. "RI,Ring Indicator. This is used to indicate the current state of the modem control line ri_n. That is this bit is the complement ri_n. When the Ring Indicator input (ri_n) is asserted it is an indication that a telephone ringing signal has been received.." "ri_n input is de-asserted,ri_n input is asserted" bitfld.long 0x4 5. "DSR,Data Set Ready. This is used to indicate the current state of the modem control line dsr_n. That is this bit is the complement dsr_n. When the Data Set Ready input (dsr_n) is asserted it is an indication that the modem or data set is ready to.." "dsr_n input is de-asserted,dsr_n input is asserted" newline bitfld.long 0x4 4. "CTS,Clear to Send. This is used to indicate the current state of the modem control line cts_n. That is this bit is the complement cts_n. When the Clear to Send input (cts_n) is asserted it is an indication that the modem or data set is ready to exchange.." "cts_n input is de-asserted,cts_n input is asserted" bitfld.long 0x4 3. "DDCD,Delta Data Carrier Detect. This is used to indicate that the modem control line dcd_n has changed since the last time the MSR was read. Reading the MSR clears the DDCD bit. In Loopback Mode (MCR[4] set to one) DDCD reflects changes on MCR[3].." "No change on dcd_n since last read of MSR,change on dcd_n since last read of MSR" newline bitfld.long 0x4 2. "TERI,Trailing Edge of Ring Indicator. This is used to indicate that a change on the input ri_n (from an active low to an inactive high state) has occurred since the last time the MSR was read. Reading the MSR clears the TERI bit. In Loopback Mode.." "no change on ri_n since last read of MSR,change on ri_n since last read of MSR" bitfld.long 0x4 1. "DDSR,Delta Data Set Ready. This is used to indicate that the modem control line dsr_n has changed since the last time the MSR was read. Reading the MSR clears the DDSR bit. In Loopback Mode (MCR[4] set to one) DDSR reflects changes on MCR[0] (DTR). Note.." "no change on dsr_n since last read of MSR,change on dsr_n since last read of MSR" newline bitfld.long 0x4 0. "DCTS,Delta Clear to Send. This is used to indicate that the modem control line cts_n has changed since the last time the MSR was read. Reading the MSR clears the DCTS bit. In Loopback Mode (MCR[4] set to one) DCTS reflects changes on MCR[1] (RTS). Note.." "no change on cts_n since last read of MSR,change on cts_n since last read of MSR" group.long 0x1C++0x3 line.long 0x0 "SCR,Scratchpad Register Reset Value: 0x0" hexmask.long.tbyte 0x0 8.--31. 1. "RSVD_SCR_31TO8,SCR 31to8 Reserved bits read as 0." hexmask.long.byte 0x0 0.--7. 1. "SCR,This register is for programmers to use as a temporary storage space. It has no defined purpose in the DW_apb_uart. Reset Value: 0x0" rgroup.long 0x30++0x3 line.long 0x0 "SRBR0,This register is valid only when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW = YES). If shadow registers are not implemented. this register does not exist and reading from this register address returns 0." hexmask.long.tbyte 0x0 9.--31. 1. "RSVD_SRBRN,SRBR0 31 to SRBRN_REG_SIZE Reserved bits read read as 0." hexmask.long.word 0x0 0.--8. 1. "SRBRN,Shadow Receive Buffer Register n. This is a shadow register for the RBR and has been allocated sixteen 32-bit locations so as to accommodate burst accesses from the master. This register contains the data byte received on the serial input port.." repeat 15. (list 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xA 0xB 0xC 0xD 0xE 0xF )(list 0x0 0x4 0x8 0xC 0x10 0x14 0x18 0x1C 0x20 0x24 0x28 0x2C 0x30 0x34 0x38 ) rgroup.long ($2+0x34)++0x3 line.long 0x0 "SRBR$1,Shadow Receive Buffer Register 1" hexmask.long.tbyte 0x0 9.--31. 1. "RSVD_SRBR1,SRBR1 31to9or8 Reserved bits read as 0." hexmask.long.word 0x0 0.--8. 1. "SRBR1,See SRBR0 description" repeat.end group.long 0x70++0x3 line.long 0x0 "FAR,FIFO Access Register" hexmask.long 0x0 1.--31. 1. "RSVD_FAR_31TO1,FAR 31to1 Reserved bits read as 0." bitfld.long 0x0 0. "FAR,Writes will have no effect when FIFO_ACCESS == No always readable. This register is use to enable a FIFO access mode for testing so that the receive FIFO can be written by the master and the transmit FIFO can be read by the master when FIFO's are.." "FIFO access mode disabled,FIFO access mode enabled" rgroup.long 0x74++0x3 line.long 0x0 "TFR,This register is valid only when the DW_apb_uart is configured to have the FIFO access test mode available (FIFO_ACCESS = YES). If not configured. this register does not exist and reading from this register address returns 0. Reset Value: 0x0'" hexmask.long.tbyte 0x0 8.--31. 1. "RSVD_TFR_31TO8,TFR 31to8 Reserved bits read as 0." hexmask.long.byte 0x0 0.--7. 1. "TFR,Transmit FIFO Read. These bits are only valid when FIFO access mode is enabled (FAR[0] is set to one). When FIFO's are implemented and enabled reading this register gives the data at the top of the transmit FIFO. Each consecutive read pops the.." group.long 0x78++0x3 line.long 0x0 "RFW,This register is valid only when the DW_apb_uart is configured to have the FIFO access test mode available (FIFO_ACCESS = YES). If not configured. this register does not exist and reading from this register address returns 0. Reset Value: 0x0'" hexmask.long.tbyte 0x0 10.--31. 1. "RSVD_RFW_31TO10,RFW 31to10 Reserved bits read as 0." bitfld.long 0x0 9. "RFFE,Receive FIFO Framing Error. These bits are only valid when FIFO access mode is enabled (FAR[0] is set to one). When FIFO's are implemented and enabled this bit is used to write framing error detection information to the receive FIFO. When FIFO's.." "Frame error disabled,Frame error enabled" newline bitfld.long 0x0 8. "RFPE,Receive FIFO Parity Error. These bits are only valid when FIFO access mode is enabled (FAR[0] is set to one). When FIFO's are implemented and enabled this bit is used to write parity error detection information to the receive FIFO. When FIFO's are.." "Parity error disabled,Parity error enabled" hexmask.long.byte 0x0 0.--7. 1. "RFWD,Receive FIFO Write Data. These bits are only valid when FIFO access mode is enabled (FAR[0] is set to one). When FIFO's are implemented and enabled the data that is written to the RFWD is pushed into the receive FIFO. Each consecutive write pushes.." rgroup.long 0x7C++0xB line.long 0x0 "USR,UART Status register. Reset Value: 0x6" hexmask.long 0x0 5.--31. 1. "RSVD_USR_31TO5,USR 31to5 Reserved bits read as 0." bitfld.long 0x0 4. "RFF,Receive FIFO Full. This bit is only valid when FIFO_STAT == YES. This is used to indicate that the receive FIFO is completely full. That is: This bit is cleared when the RX FIFO is no longer full. Reset Value: 0x0 0x1: Receive FIFO full 0x0: Receive.." "Receive FIFO not full,Receive FIFO full" newline bitfld.long 0x0 3. "RFNE,Receive FIFO Not Empty. This bit is only valid when FIFO_STAT == YES. This is used to indicate that the receive FIFO contains one or more entries. This bit is cleared when the RX FIFO is empty. Reset Value: 0x0 0x0: Receive FIFO is empty 0x1:.." "Receive FIFO is empty,Receive FIFO is not empty" bitfld.long 0x0 2. "TFE,Transmit FIFO Empty. This bit is only valid when FIFO_STAT == YES. This is used to indicate that the transmit FIFO is completely empty. This bit is cleared when the TX FIFO is no longer empty. Reset Value: 0x1 0x1: Transmit FIFO is empty 0x0:.." "Transmit FIFO is not empty,Transmit FIFO is empty" newline bitfld.long 0x0 1. "TFNF,Transmit FIFO Not Full. This bit is only valid when FIFO_STAT == YES. This is used to indicate that the transmit FIFO in not full. This bit is cleared when the TX FIFO is full. Reset Value: 0x1 0x0: Transmit FIFO is full 0x1: Transmit FIFO is not full" "Transmit FIFO is full,Transmit FIFO is not full" bitfld.long 0x0 0. "RSVD_BUSY,UART Busy. This bit is only valid when UART_16550_COMPATIBLE == YES. This indicates that a serial transfer is in progress when cleared indicates that the DW_apb_uart is idle or inactive. This bit will be set to 1 (busy) under any of the.." "DW_apb_uart is idle or inactive,DW_apb_uart is busy" line.long 0x4 "TFL,TFL register is valid only when the DW_apb_uart is configured to have additional FIFO status registers implemented (FIFO_STAT = YES). If status registers are not implemented. this register does not exist and reading from this register address returns.." hexmask.long 0x4 6.--31. 1. "RSVD_TFL_31TOADDR_WIDTH,TFL 31 to ADDR_WIDTH Reserved bits read as 0." hexmask.long.byte 0x4 0.--5. 1. "TFL,Transmit FIFO Level. This indicates the number of data entries in the transmit FIFO. Reset Value: 0x0" line.long 0x8 "RFL,RFL register is valid only when the DW_apb_uart is configured to have additional FIFO status registers implemented (FIFO_STAT = YES). If status registers are not implemented. this register does not exist and reading from this register address returns.." hexmask.long 0x8 6.--31. 1. "RSVD_RFL_31TOADDR_WIDTH,RFL 31 to ADDR_WIDTH Reserved bits read as 0." hexmask.long.byte 0x8 0.--5. 1. "RFL,Receive FIFO Level. This is indicates the number of data entries in the receive FIFO. Reset Value: 0x0" group.long 0x88++0x47 line.long 0x0 "SRR,This register is valid only when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW = YES). If shadow registers are not implemented. this register does not exist and reading from this register address returns 0. For.." hexmask.long 0x0 3.--31. 1. "RSVD_SRR_31TO3,SRR 31to3 Reserved bits read as 0." bitfld.long 0x0 2. "XFR,XMIT FIFO Reset. Writes will have no effect when FIFO_MODE == NONE. This is a shadow register for the XMIT FIFO Reset bit (FCR[2]). This can be used to remove the burden on software having to store previously written FCR values (which are pretty.." "0,1" newline bitfld.long 0x0 1. "RFR,RCVR FIFO Reset. Writes will have no effect when FIFO_MODE == NONE. This is a shadow register for the RCVR FIFO Reset bit (FCR[1]). This can be used to remove the burden on software having to store previously written FCR values (which are pretty.." "0,1" bitfld.long 0x0 0. "UR,UART Reset. This asynchronously resets the DW_apb_uart and synchronously removes the reset assertion. For a two clock implementation both pclk and sclk domains will be reset. Reset Value: 0x0 0x0: No Uart Reset 0x1: Uart reset" "No Uart Reset,Uart reset" line.long 0x4 "SRTS,SRTS register is valid only when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW = YES). If shadow registers are not implemented. this register does not exist and reading from this register address returns 0." hexmask.long 0x4 1.--31. 1. "RSVD_SRTS_31TO1,SRTS 31to1 Reserved bits read as 0." bitfld.long 0x4 0. "SRTS,Shadow Request to Send. This is a shadow register for the RTS bit (MCR[1]) this can be used to remove the burden of having to performing a read modify write on the MCR. This is used to directly control the Request to Send (rts_n) output. The.." "Shadow Request to Send uart_rts_n logic1,Shadow Request to Send uart_rts_n logic0" line.long 0x8 "SBCR,SBCR register is valid only when the DW_apb_uart is configured to have additional shadow registers implemented (SHADOW = YES). If shadow registers are not implemented. this register does not exist and reading from this register address returns 0." hexmask.long 0x8 1.--31. 1. "RSVD_SBCR_31TO1,SBCR 31to1 Reserved bits read as 0." bitfld.long 0x8 0. "SBCB,Shadow Break Control Bit. This is a shadow register for the Break bit (LCR[6]) this can be used to remove the burden of having to performing a read modify write on the LCR. This is used to cause a break condition to be transmitted to the receiving.." "No spacing on serial output,Serial output forced to the spacing" line.long 0xC "SDMAM,This register is valid only when the DW_apb_uart is configured to have additional FIFO registers implemented (FIFO_MODE != None) and additional shadow registers implemented (SHADOW = YES). If these registers are not implemented. this register does.." hexmask.long 0xC 1.--31. 1. "RSVD_SDMAM_31TO1,SDMAM 31to1 Reserved bits read as 0." bitfld.long 0xC 0. "SDMAM,Shadow DMA Mode. This is a shadow register for the DMA mode bit (FCR[3]). This can be used to remove the burden of having to store the previously written value to the FCR in memory and having to mask this value so that only the DMA Mode bit gets.." "Mode 0,Mode 1" line.long 0x10 "SFE,SFE register is valid only when the DW_apb_uart is configured to have additional FIFO registers implemented (FIFO_MODE != None) and additional shadow registers implemented (SHADOW = YES). If these registers are not implemented. this register does not.." hexmask.long 0x10 1.--31. 1. "RSVD_SFE_31TO1,SFE 31to1 Reserved bits read as 0." bitfld.long 0x10 0. "SFE,Shadow FIFO Enable. This is a shadow register for the FIFO enable bit (FCR[0]). This can be used to remove the burden of having to store the previously written value to the FCR in memory and having to mask this value so that only the FIFO enable bit.." "FIFOs are disabled,FIFOs are enabled" line.long 0x14 "SRT,SRT register is valid only when the DW_apb_uart is configured to have additional FIFO registers implemented (FIFO_MODE != None) and additional shadow registers implemented (SHADOW = YES). If these registers are not implemented. this register does not.." hexmask.long 0x14 2.--31. 1. "RSVD_SRT_31TO2,SRT 31to2 Reserved bits read as 0." bitfld.long 0x14 0.--1. "SRT,Shadow RCVR Trigger. This is a shadow register for the RCVR trigger bits (FCR[7:6]). This can be used to remove the burden of having to store the previously written value to the FCR in memory and having to mask this value so that only the RCVR.." "?,FIFO 1/4 full,FIFO 1/2 full,FIFO 2 less than full" line.long 0x18 "STET,This register is valid only when the DW_apb_uart is configured to have FIFOs implemented (FIFO_MODE != NONE) and THRE interrupt support implemented (THRE_MODE_USER = Enabled) and additional shadow registers implemented (SHADOW = YES). If FIFOs are.." hexmask.long 0x18 2.--31. 1. "RSVD_STET_31TO2,STET 31to2 Reserved bits read as 0." bitfld.long 0x18 0.--1. "STET,Shadow TX Empty Trigger. This is a shadow register for the TX empty trigger bits (FCR[5:4]). This can be used to remove the burden of having to store the previously written value to the FCR in memory and having to mask this value so that only the TX.." "FIFO empty,?,FIFO 1/4 full,FIFO 1/2 full" line.long 0x1C "HTX,Halt TX Reset Value: 0x0" hexmask.long 0x1C 1.--31. 1. "RSVD_HTX_31TO1,HTX 31to1 Reserved bits read as 0." bitfld.long 0x1C 0. "HTX,Halt TX. Writes will have no effect when FIFO_MODE == NONE always readable. This register is use to halt transmissions for testing so that the transmit FIFO can be filled by the master when FIFO's are implemented and enabled. Note if FIFO's are.." "Halt Transmission disabled,Halt Transmission enabled" line.long 0x20 "DMASA,DMA Software Acknowledge Register Reset Value: 0x0" hexmask.long 0x20 1.--31. 1. "RSVD_DMASA_31TO1,DMASA 31to1 Reserved bits read as 0." bitfld.long 0x20 0. "DMASA,DMA Software Acknowledge. Writes will have no effect when DMA_EXTRA == No. This register is use to perform DMA software acknowledge if a transfer needs to be terminated due to an error condition. For example if the DMA disables the channel then.." "?,DMA software acknowledge" line.long 0x24 "TCR,This register is used to enable or disable RS485 mode and also control the polarity values for Driven enable (de) and Receiver Enable (re) signals. This register is only valid when the DW_apb_uart is configured to have RS485 interface implemented.." hexmask.long 0x24 5.--31. 1. "RSVD_TCR_31TO5,TCR 31to5 Reserved bits read as 0." bitfld.long 0x24 3.--4. "XFER_MODE,Transfer Mode. - 0: In this mode transmit and receive can happen simultaneously. The user can enable DE_EN RE_EN at any point of time. Turn around timing as programmed in the TAT register is not applicable in this mode. - 1: In this mode DE.." "In this mode,In this mode,In this mode,?" newline bitfld.long 0x24 2. "DE_POL,Driver Enable Polarity. - 1: DE signal is active high - 0: DE signal is active low Reset Value: UART_DE_POL" "DE signal is active low,DE signal is active high" bitfld.long 0x24 1. "RE_POL,Receiver Enable Polarity. - 1: RE signal is active high - 0: RE signal is active low Reset Value: UART_RE_POL" "RE signal is active low,RE signal is active high" newline bitfld.long 0x24 0. "RS485_EN,RS485 Transfer Enable. - 0 : In this mode the transfers are still in the RS232 mode. All other fields in this register are reserved and register DE_EN/RE_EN/TAT are also reserved. - 1 : In this mode the transfers will happen in RS485 mode. All.." "In this mode,In this mode" line.long 0x28 "DE_EN,The Driver Output Enable Register (DE_EN) is used to control the assertion and de-assertion of the DE signal. This register is only valid when the DW_apb_uart is configured to have RS485 interface implemented (UART_RS485_INTERFACE_EN = ENABLED). If.." hexmask.long 0x28 1.--31. 1. "RSVD_DE_EN_31TO1,DE_EN 31to1 Reserved bits read as 0." bitfld.long 0x28 0. "DE_ENABLE,DE Enable control. The 'DE Enable' register bit is used to control assertion and de-assertion of 'de' signal. - 0: De-assert 'de' signal - 1: Assert 'de' signal Reset Value: 0x0" "De-assert 'de' signal,Assert 'de' signal" line.long 0x2C "RE_EN,The Receiver Output Enable Register (RE_EN) is used to control the assertion and de-assertion of the RE signal. This register is only valid when the DW_apb_uart is configured to have RS485 interface implemented (UART_RS485_INTERFACE_EN = ENABLED)." hexmask.long 0x2C 1.--31. 1. "RSVD_RE_EN_31TO1,RE_EN 31to1 Reserved bits read as 0." bitfld.long 0x2C 0. "RE_ENABLE,RE Enable control. The 'RE Enable' register bit is used to control assertion and de-assertion of 're' signal. - 0: De-assert 're' signal - 1: Assert 're' signal Reset Value: 0x0" "De-assert 're' signal,Assert 're' signal" line.long 0x30 "DET,The Driver Output Enable Timing Register (DET) is used to control the DE assertion and de-assertion timings of 'de' signal. This register is only valid when the DW_apb_uart is configured to have RS485 interface implemented (UART_RS485_INTERFACE =.." hexmask.long.byte 0x30 24.--31. 1. "RSVD_DE_DEAT_31TO24,DET 31to24 Reserved bits read as 0." hexmask.long.byte 0x30 16.--23. 1. "DE_DE-ASSERTION_TIME,Driver Enable de-assertion time. This field controls the amount of time (in terms of number of serial clock periods) between the end of stop bit on the sout to the falling edge of Driver output enable signal. Reset Value: 0x0" newline hexmask.long.byte 0x30 8.--15. 1. "RSVD_DE_AT_15TO8,DET 15to8 Reserved bits read as 0." hexmask.long.byte 0x30 0.--7. 1. "DE_ASSERTION_TIME,Driver Enable assertion time. This field controls the amount of time (in terms of number of serial clock periods) between the assertion of rising edge of Driver output enable signal to serial transmit enable. Any data in transmit buffer.." line.long 0x34 "TAT,The TurnAround Timing Register (TAT) is used to hold the turnaround time between switching of 're' and 'de' signals. This register is only valid when the DW_apb_uart is configured to have the RS485 interface implemented (UART_RS485_INTERFACE_EN =.." hexmask.long.word 0x34 16.--31. 1. "RE_TO_DE,Receiver Enable to Driver Enable TurnAround time. Turnaround time (in terms of serial clock) for RE De-assertion to DE assertion. Note: - If the DE assertion time in the DET register is 0 then the actual value is the programmed value + 3. - If.." hexmask.long.word 0x34 0.--15. 1. "DE_TO_RE,Driver Enable to Receiver Enable TurnAround time. Turnaround time (in terms of serial clock) for DE De-assertion to RE assertion. Note: The actual time is the programmed value + 1. Reset Value: 0x0" line.long 0x38 "DLF,This register is only valid when the DW_apb_uart is configured to have Fractional Baud rate Divisor implemented (FRACTIONAL_BAUD_DIVISOR_EN = ENABLED). If Fractional Baud rate divisor is not implemented. this register does not exist and reading from.." hexmask.long 0x38 4.--31. 1. "RSVD_DLF,DLF 31 to DLF_SIZE Reserved bits read as 0." hexmask.long.byte 0x38 0.--3. 1. "DLF,Fractional part of divisor. The fractional value is added to integer value set by DLH DLL. Fractional value is determined by (Divisor Fraction value)/(2^DLF_SIZE). For information on DLF values to be programmed for DLF_SIZE=4 see the 'Fractional.." line.long 0x3C "RAR,Receive Address Register Reset Value: 0x0" hexmask.long.tbyte 0x3C 8.--31. 1. "RSVD_RAR_31TO8,RAR 31to8 Reserved bits read as 0." hexmask.long.byte 0x3C 0.--7. 1. "RAR,This is an address matching register during receive mode. If the 9-th bit is set in the incoming character then the remaining 8-bits will be checked against this register value. If the match happens then sub-sequent characters with 9-th bit set to 0.." line.long 0x40 "TAR,Transmit Address Register Reset Value: 0x0" hexmask.long.tbyte 0x40 8.--31. 1. "RSVD_TAR_31TO8,TAR 31to8 Reserved bits read as 0." hexmask.long.byte 0x40 0.--7. 1. "TAR,This is an address matching register during transmit mode. If DLS_E (LCR_EXT[0]) bit is enabled then DW_apb_uart will send the 9-bit character with 9-th bit set to 1 and remaining 8-bit address will be sent from this register provided 'SEND_ADDR'.." line.long 0x44 "LCR_EXT,Line Extended Control Register Reset Value: 0x0" hexmask.long 0x44 4.--31. 1. "RSVD_LCR_EXT,LCR_EXT 31to4 Reserved bits read as 0." bitfld.long 0x44 3. "TRANSMIT_MODE,Transmit mode control bit. This bit is used to control the type of transmit mode during 9-bit data transfers. - 1: In this mode of operation Transmit Holding Register (THR) and Shadow Transmit Holding Register (STHR) are 9-bit wide. The.." "In this mode of operation,In this mode of operation" newline bitfld.long 0x44 2. "SEND_ADDR,Send address control bit. This bit is used as a control knob for the user to determine when to send the address during transmit mode. - 1 = 9-bit character will be transmitted with 9-th bit set to 1 and the remaining 8-bits will match to what.." "0,1" bitfld.long 0x44 1. "ADDR_MATCH,Address Match Mode.This bit is used to enable the address match feature during receive. - 1 = Address match mode; DW_apb_uart will wait until the incoming character with 9-th bit set to 1. And further checks to see if the address matches with.." "Normal mode; DW_apb_uart will start to receive..,Address match mode; DW_apb_uart will wait until.." newline bitfld.long 0x44 0. "DLS_E,Extension for DLS. This bit is used to enable 9-bit data for transmit and receive transfers. Reset Value: 0x0" "0,1" rgroup.long 0xF4++0xB line.long 0x0 "CPR,Component Parameter Register.This register is valid only when UART_ADD_ENCODED_PARAMS = 1. If the UART_ADD_ENCODED_PARAMS parameter is not set. this register does not exist and reading from this register address returns 0. Reset Value:.." hexmask.long.byte 0x0 24.--31. 1. "RSVD_CPR_31TO24,CPR 31to24 Reserved bits read as 0." hexmask.long.byte 0x0 16.--23. 1. "FIFO_MODE,Encoding of FIFO_MODE configuration parameter value. 0x0: FIFO mode is 0 0x40: FIFO mode is 1024 0x8: FIFO mode is 128 0x1: FIFO mode is 16 0x80: FIFO mode is 2048 0x10: FIFO mode is 256 0x2: FIFO mode is 32 0x20: FIFO mode is 512 0x4: FIFO.." newline bitfld.long 0x0 14.--15. "RSVD_CPR_15TO14,CPR 15to14 Reserved bits read as 0." "0,1,2,3" bitfld.long 0x0 13. "DMA_EXTRA,Encoding of DMA_EXTRA configuration parameter value. 0x0: DMA_EXTRA disabled 0x1: DMA_EXTRA enabled" "DMA_EXTRA disabled,DMA_EXTRA enabled" newline bitfld.long 0x0 12. "UART_ADD_ENCODED_PARAMS,Encoding of UART_ADD_ENCODED_PARAMS configuration parameter value. 0x0: UART_ADD_ENCODED_PARAMS disabled 0x1: UART_ADD_ENCODED_PARAMS enabled" "UART_ADD_ENCODED_PARAMS disabled,UART_ADD_ENCODED_PARAMS enabled" bitfld.long 0x0 11. "SHADOW,Encoding of SHADOW configuration parameter value. 0x0: SHADOW disabled 0x1: SHADOW enabled" "SHADOW disabled,SHADOW enabled" newline bitfld.long 0x0 10. "FIFO_STAT,Encoding of FIFO_STAT configuration parameter value. 0x0: FIFO_STAT disabled 0x1: FIFO_STAT enabled" "FIFO_STAT disabled,FIFO_STAT enabled" bitfld.long 0x0 9. "FIFO_ACCESS,Encoding of FIFO_ACCESS configuration parameter value. 0x0: FIFO_ACCESS disabled 0x1: FIFO ACCESS enabled" "FIFO_ACCESS disabled,FIFO ACCESS enabled" newline bitfld.long 0x0 8. "ADDITIONAL_FEAT,Encoding of ADDITIONAL_FEATURES configuration parameter value. 0x0: Additional features disabled 0x1: Additional features enabled" "Additional features disabled,Additional features enabled" bitfld.long 0x0 7. "SIR_LP_MODE,Encoding of SIR_LP_MODE configuration parameter value. 0x0: SIR_LP mode disabled 0x1: SIR_LP mode enabled" "SIR_LP mode disabled,SIR_LP mode enabled" newline bitfld.long 0x0 6. "SIR_MODE,Encoding of SIR_MODE configuration parameter value. 0x0: SIR mode disabled 0x1: SIR mode enabled" "SIR mode disabled,SIR mode enabled" bitfld.long 0x0 5. "THRE_MODE,Encoding of THRE_MODE configuration parameter value. 0x0: THRE mode disabled 0x1: THRE mode enabled" "THRE mode disabled,THRE mode enabled" newline bitfld.long 0x0 4. "AFCE_MODE,Encoding of AFCE_MODE configuration parameter value. 0x0: AFCE mode disabled 0x1: AFCE mode enabled" "AFCE mode disabled,AFCE mode enabled" bitfld.long 0x0 2.--3. "RSVD_CPR_3TO2,CPR 3to2 Reserved bits read as 0." "0,1,2,3" newline bitfld.long 0x0 0.--1. "APB_DATA_WIDTH,Encoding of APB_DATA_WIDTH configuration parameter value. 0x1: APB data width is 16 bits 0x2: APB data width is 32 bits 0x0: APB data width is 8 bits" "APB data width is 8 bits,APB data width is 16 bits,APB data width is 32 bits,?" line.long 0x4 "UCV,This register is valid only when the DW_apb_uart is configured to have additional features implemented (ADDITIONAL_FEATURES = YES). If additional features are not implemented. this register does not exist and reading from this register address.." hexmask.long 0x4 0.--31. 1. "UART_COMPONENT_VERSION,ASCII value for each number in the version followed by *. For example 32_30_31_2A represents the version 2.01*" line.long 0x8 "CTR,This register is valid only when the DW_apb_uart is configured to have additional features implemented (ADDITIONAL_FEATURES = YES). If additional features are not implemented. this register does not exist and reading from this register address.." hexmask.long 0x8 0.--31. 1. "PERIPHERAL_ID,This register contains the peripherals identification code. Reset Value: 0x44570110" tree.end repeat.end endif tree.end tree "USB1 (USB Controller 1)" sif (CORENAME()=="CORTEXR5F") tree "USB1" base ad:0xF1220000 tree "DWC_usb3_block_gbl (USB 3.0 Global Register Block)" group.long (0x0+0x49408)++0x1F line.long 0x0 "GSBUSCFG0,Global SoC Bus Configuration Register 0 This register configures system bus DMA options for the master bus. which may be configured as AHB. AXI. or Native. Options include burst length and cache type (bufferable/posted. cacheable/snoop. and so.." hexmask.long.byte 0x0 28.--31. 1. "DATRDREQINFO,DATRDREQINFO AHB-prot/AXI-cache/OCP-ReqInfo for Data Read (DatRdReqInfo) Input to BUS-GM." newline hexmask.long.byte 0x0 24.--27. 1. "DESRDREQINFO,DESRDREQINFO AHB-prot/AXI-cache/OCP-ReqInfo for Descriptor Read (DesRdReqInfo). Input to BUS-GM." newline hexmask.long.byte 0x0 20.--23. 1. "DATWRREQINFO,DATWRREQINFO AHB-prot/AXI-cache/OCP-ReqInfo for Data Write (DatWrReqInfo). Input to BUS-GM." newline hexmask.long.byte 0x0 16.--19. 1. "DESWRREQINFO,DESWRREQINFO AHB-prot/AXI-cache/OCP-ReqInfo for Descriptor Write (DesWrReqInfo) Input to BUS-GM." newline hexmask.long.byte 0x0 12.--15. 1. "RESERVED_15_12,Reserved for future use" newline bitfld.long 0x0 11. "DATBIGEND,Data Access is Big Endian This bit controls the endian mode for data accesses. - Little-endian (default); - Big-endian; In big-endian mode DMA access (both read and write) for packet data a Byte Invariant Big-Endian mode (see 'Little-Endian.." "0,1" newline bitfld.long 0x0 10. "DESBIGEND,Descriptor Access is Big Endian This bit controls the endian mode for descriptor accesses. - Little-endian (default) - Big-endian In big-endian mode DMA access (both read and write) for descriptors uses a Byte Invariant Big-Endian mode (see.." "0,1" newline rbitfld.long 0x0 8.--9. "RESERVED_9_8,Reserved" "0,1,2,3" newline bitfld.long 0x0 7. "INCR256BRSTENA,INCR256 Burst Type Enable Input to BUS-GM. For the AHB/AXI configuration if software set this bit to 1 the AHB/AXI master uses INCR to do the 256-beat burst." "0,1" newline bitfld.long 0x0 6. "INCR128BRSTENA,INCR128 Burst Type Enable Input to BUS-GM; For the AHB/AXI configuration if software set this bit to 1 the AHB/AXI master uses INCR to do the 128-beat burst." "0,1" newline bitfld.long 0x0 5. "INCR64BRSTENA,INCR64 Burst Type Enable - Input to BUS-GM; For the AHB/AXI configuration if software set this bit to 1 the AHB/AXI master uses INCR to do the 64-beat burst." "0,1" newline bitfld.long 0x0 4. "INCR32BRSTENA,INCR32 Burst Type Enable Input to BUS-GM; For the AHB/AXI configuration if software set this bit to 1 the AHB/AXI master uses INCR to do the 32-beat burst." "0,1" newline bitfld.long 0x0 3. "INCR16BRSTENA,INCR16 Burst Type Enable Input to BUS-GM. For the AHB/AXI configuration if software set this bit to '1' the AHB/AXI master uses INCR to do the 16-beat burst." "0,1" newline bitfld.long 0x0 2. "INCR8BRSTENA,INCR8 Burst Type Enable Input to BUS-GM; For the AHB/AXI configuration if software set this bit to '1' the AHB/AXI master uses INCR to do the 8-beat burst." "0,1" newline bitfld.long 0x0 1. "INCR4BRSTENA,INCR4 Burst Type Enable Input to BUS-GM; For the AXI configuration when this bit is enabled the controller is allowed to do bursts of beat length 1 2 and 4. It is highly recommended that this bit is enabled to prevent descriptor reads and.." "0,1" newline bitfld.long 0x0 0. "INCRBRSTENA,Undefined Length INCR Burst Type Enable (INCRBrstEna) Input to BUS-GM; This bit determines the set of burst lengths the master interface uses. It works in conjunction with the GSBUSCFG0[7:1] enables (INCR256/128/64/32/16/8/4). 0: INCRX burst.." "INCRX burst mode,INCR" line.long 0x4 "GSBUSCFG1,Global SoC Bus Configuration Register 1 xHCI Register Power-On Value: If you are using a standard xHCI host driver. make sure to set the register's power-on value during coreConsultant configuration (DWC_USB3_GSBUSCFG1_INIT parameter) because.." hexmask.long.tbyte 0x4 13.--31. 1. "RESERVED_31_13,Reserved" newline bitfld.long 0x4 12. "EN1KPAGE,1k Page Boundary Enable By default (this bit is disabled) the AXI breaks transfers at the 4k page boundary. When this bit is enabled the AXI master (DMA data) breaks transfers at the 1k page boundary." "0,1" newline hexmask.long.byte 0x4 8.--11. 1. "PIPETRANSLIMIT,AXI Pipelined Transfers Burst Request Limit The field controls the number of outstanding pipelined transfer requests the AXI master pushes to the AXI slave. When the AXI master reaches this limit it does not make any more requests on the.." newline hexmask.long.byte 0x4 0.--7. 1. "RESERVED_7_0,Reserved" line.long 0x8 "GTXTHRCFG,Global Tx Threshold Control Register For more information on - Using this register. refer to 'Packet Threshold and Burst Features for High Latency Systems' section in the Databook. - Selecting values for the fields of this register. see the.." rbitfld.long 0x8 31. "RESERVED_31,Reserved" "0,1" newline rbitfld.long 0x8 30. "RESERVED_30,Reserved" "0,1" newline bitfld.long 0x8 29. "USBTXPKTCNTSEL,USB Transmit Packet Count Enable This field enables/disables the USB transmission multi-packet thresholding: - 0: USB transmission multi-packet thresholding is disabled; the controller can start transmission on the USB after the entire.." "USB transmission multi-packet thresholding is..,USB transmission multi-packet thresholding is.." newline rbitfld.long 0x8 28. "RESERVED_28,Reserved" "0,1" newline hexmask.long.byte 0x8 24.--27. 1. "USBTXPKTCNT,USB Transmit Packet Count This field specifies the number of packets that must be in the TXFIFO before the controller can start transmission for the corresponding USB transaction (burst). This field is only valid when the USB Transmit Packet.." newline hexmask.long.byte 0x8 16.--23. 1. "USBMAXTXBURSTSIZE,USB Maximum TX Burst Size When UsbTxPktCntSel is one this field specifies the Maximum Bulk OUT burst the controller can do. When the system bus is slower than the USB TX FIFO can underrun during a long burst. User can program a.." newline rbitfld.long 0x8 15. "RESERVED_15,Reserved_15" "0,1" newline rbitfld.long 0x8 14. "RESERVED_14,Reserved1(Rsvd/Rs) Register field must write only 0 by the application. The read value must be treated as X (unknown)." "0,1" newline rbitfld.long 0x8 11.--13. "RESERVED_13_11,Reserved (Rsvd/Rs) The register field must write only 0 by the application. The read value must be treated as X (unknown)." "0,1,2,3,4,5,6,7" newline hexmask.long.word 0x8 0.--10. 1. "RESERVED_10_0,Reserved for future use" line.long 0xC "GRXTHRCFG,Global Rx Threshold Control Register In a normal case. a Tx burst starts as soon as one packet is prefetched; an Rx burst starts as soon as 1-packet space is available. This works well as long as the system bus is faster than the USB 3.0 bus (a.." rbitfld.long 0xC 30.--31. "RESERVED_31_30,Reserved" "0,1,2,3" newline bitfld.long 0xC 29. "USBRXPKTCNTSEL,USB Receive Packet Count Enable This field enables/disables the USB reception multi-packet thresholding: - 0: The controller can only start reception on the USB when the RX FIFO has space for at least one packet. - 1: The controller can.." "The controller can only start reception on the..,The controller can only start reception on the.." newline rbitfld.long 0xC 28. "RESERVED_28,Reserved" "0,1" newline hexmask.long.byte 0xC 24.--27. 1. "USBRXPKTCNT,USB Receive Packet Count In host mode this field specifies the space (in terms of the number of packets) that must be available in the RX FIFO before the controller can start the corresponding USB RX transaction (burst). In device mode this.." newline hexmask.long.byte 0xC 19.--23. 1. "USBMAXRXBURSTSIZE,USB Maximum Receive Burst Size In host mode this field specifies the Maximum Bulk IN burst the DWC_usb3 controller can perform. When the system bus is slower than the USB RX FIFO can overrun during a long burst. You can program a.." newline rbitfld.long 0xC 16.--18. "RESERVED_18_16,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0xC 15. "RESERVED_15,Reserved" "0,1" newline rbitfld.long 0xC 13.--14. "RESERVED_14_13,Reserved" "0,1,2,3" newline hexmask.long.word 0xC 0.--12. 1. "RESVISOCOUTSPC,Space reserved in Rx FIFO for ISOC OUT In host mode this field is not applicable and must be programmed to 0. In device mode this value represents the amount of space to be reserved for ISOC OUT packets. The value to be programmed should.." line.long 0x10 "GCTL,Global Core Control Register Refer to /src/DWC_usb3_params.v for details on `DWC_USB3_GCTL_INIT. Note: When Hibernation is not enabled. you can write any value to GblHibernationEn. It always returns 0 when read." hexmask.long.word 0x10 19.--31. 1. "PWRDNSCALE,Power Down Scale (PwrDnScale) The USB3 suspend_clk input replaces pipe3_rx_pclk as a clock source to a small part of the USB3 controller that operates when the SS PHY is in its lowest power (P3) state and therefore does not provide a clock." newline bitfld.long 0x10 18. "MASTERFILTBYPASS,Master Filter Bypass When this bit is set to 1'b1 irrespective of the parameter `DWC_USB3_EN_BUS_FILTERS chosen all the filters in the DWC_usb3_filter module are bypassed. The double synchronizers to mac_clk preceding the filters are.." "0,1" newline bitfld.long 0x10 17. "BYPSSETADDR,Bypass SetAddress in Device Mode. When BYPSSETADDR bit is set the device controller uses the value in the DCFG[DevAddr] bits directly for comparing the device address in the tokens. For simulation you can use this feature to avoid sending.." "0,1" newline bitfld.long 0x10 16. "U2RSTECN,U2RSTECN If the SuperSpeed connection fails during POLL or LMP exchange the device connects at non-SS mode. If this bit is set then device attempts three more times to connect at SS even if it previously failed to operate in SS mode. For each.." "0,1" newline bitfld.long 0x10 14.--15. "FRMSCLDWN,FRMSCLDWN This field scales down device view of a SOF/USOF/ITP duration. For SS/HS mode: - Value of 2'h3 implements interval to be 15.625 us - Value of 2'h2 implements interval to be 31.25 us - Value of 2'h1 implements interval to be 62.5 us -.." "0,1,2,3" newline bitfld.long 0x10 12.--13. "PRTCAPDIR,PRTCAPDIR: Port Capability Direction (PrtCapDir) - 2'b01: for Host configurations - 2'b10: for Device configurations Note: For static Host-only/Device-only applications use DRD Host or DRD Device mode. The combination of GCTL.PrtCapDir=2'b11.." "?,for Host configurations,for Device configurations,?" newline bitfld.long 0x10 11. "CORESOFTRESET,Core Soft Reset (CoreSoftReset) - 1'b0 - No soft reset - 1'b1 - Soft reset to controller Clears the interrupts and all the CSRs except the following registers: - GCTL - GUCTL - GSTS - GSNPSID - GGPIO - GUID - GUSB2PHYCFGn registers -.." "No soft reset,Soft reset to controller" newline bitfld.long 0x10 10. "SOFITPSYNC,SOFITPSYNC If this bit is set to '0' operating in host mode the controller keeps the UTMI/ULPI PHY on the first port in a non-suspended state whenever there is a SuperSpeed port that is not in Rx.Detect SS.Disable and U3. If this bit is set.." "0,1" newline bitfld.long 0x10 9. "U1U2TIMERSCALE,Disable U1/U2 timer Scaledown (U1U2TimerScale). If set to '1' along with GCTL[5:4] (ScaleDown) = 2'bX1 disables the scale down of U1/U2 inactive timer values. This is for simulation mode only." "0,1" newline bitfld.long 0x10 8. "DEBUGATTACH,Debug Attach When this bit is set - SS Link proceeds directly to the Polling link state (after RUN/STOP in the DCTL register is asserted) without checking remote termination; - Link LFPS polling timeout is infinite; - Polling timeout during.." "0,1" newline bitfld.long 0x10 6.--7. "RAMCLKSEL,RAM Clock Select (RAMClkSel) - 2'b00: bus clock - 2'b01: pipe clock (Only used in device mode) - 2'b10: In device mode pipe/2 clock.In Host mode controller switches ram_clk between pipe/2 clock mac2_clk and bus_clk based on the status of.." "bus clock,pipe clock,In device mode,In device mode" newline bitfld.long 0x10 4.--5. "SCALEDOWN,Scale-Down Mode (ScaleDown) When Scale-Down mode is enabled for simulation the controller uses scaled-down timing values resulting in faster simulations. When Scale-Down mode is disabled actual timing values are used. This is required for.." "Disables all scale-downs,Enables scaled down SS timing and repeat values..,No TxEq training sequences are sent,Enables bit 0 and bit 1 scale-down timing values" newline bitfld.long 0x10 3. "DISSCRAMBLE,Disable Scrambling (DisScramble) Transmit request to Link Partner on next transition to Recovery or Polling." "0,1" newline bitfld.long 0x10 2. "U2EXIT_LFPS,U2EXIT_LFPS If this bit is - 0: the link treats 248ns LFPS as a valid U2 exit. - 1: the link waits for 8us of LFPS before it detects a valid U2 exit. This bit is added to improve interoperability with a third-party host/device controller." "the link treats 248ns LFPS as a valid U2 exit,the link waits for 8us of LFPS before it detects.." newline rbitfld.long 0x10 1. "GBLHIBERNATIONEN,GblHibernationEn This bit enables hibernation at the global level. If hibernation is not enabled through this bit the PMU immediately accepts the D0->D3 and D3->D0 power state change requests but does not save or restore any controller.." "D3 and D3,?" newline bitfld.long 0x10 0. "DSBLCLKGTNG,Disable Clock Gating (DsblClkGtng) This bit is set to 1 and the controller is in Low Power mode internal clock gating is disabled. You can set this bit to 1'b1 after Power On Reset." "0,1" line.long 0x14 "GPMSTS,Global Power Management Status Register This debug register gives information on which event caused the hibernation exit. It provides internal status and state machine information. and is for Synopsys use only for debugging purposes. This register.." hexmask.long.byte 0x14 28.--31. 1. "PORTSEL,Global Power Management Status Register PortSel This field selects the port number." newline hexmask.long.word 0x14 17.--27. 1. "RESERVED_27_17,Reserved" newline hexmask.long.byte 0x14 12.--16. 1. "U3WAKEUP,U3Wakeup This field gives the following USB 3.0 port wakeup conditions: - Bit [12]: Overcurrent Detected - Bit [13]: Resume Detected - Bit [14]: Connect Detected - Bit [15]: Disconnect Detected - Bit [16]: Last Connection State" newline rbitfld.long 0x14 10.--11. "RESERVED_10_11,Reserved" "0,1,2,3" newline hexmask.long.word 0x14 0.--9. 1. "U2WAKEUP,U2Wakeup This field indicates the following USB 2.0 port wakeup conditions: - Bit [0]: Overcurrent Detected - Bit [1]: Resume Detected - Bit [2]: Connect Detected - Bit [3]: Disconnect Detected - Bit [4]: Last Connection State - Bit [5]: ID.." line.long 0x18 "GSTS,Global Status Register" hexmask.long.word 0x18 20.--31. 1. "CBELT,Current BELT Value In Host mode this field indicates the minimum value of all received device BELT values and the BELT value that is set by the Set Latency Tolerance Value command." newline hexmask.long.byte 0x18 12.--19. 1. "RESERVED_19_12,Reserved" newline rbitfld.long 0x18 11. "SSIC_IP,This field is not used." "0,1" newline rbitfld.long 0x18 10. "OTG_IP,This field is not used." "0,1" newline rbitfld.long 0x18 9. "BC_IP,Battery Charger Interrupt Pending This field indicates that there is a pending interrupt pertaining to BC in BCEVT register." "0,1" newline rbitfld.long 0x18 8. "ADP_IP,This field is not used." "0,1" newline rbitfld.long 0x18 7. "HOST_IP,Host Interrupt Pending: This field indicates that there is a pending interrupt pertaining to xHC in the Host event queue." "0,1" newline rbitfld.long 0x18 6. "DEVICE_IP,Device Interrupt Pending This field indicates that there is a pending interrupt pertaining to peripheral (device) operation in the Device event queue." "0,1" newline bitfld.long 0x18 5. "CSRTIMEOUT,CSR Timeout When this bit is 1'b1 it indicates that the software performed a write or read to a controller register that could not be completed within `DWC_USB3_CSR_ACCESS_TIMEOUT bus clock cycles (default: h1FFFF)." "0,1" newline bitfld.long 0x18 4. "BUSERRADDRVLD,Bus Error Address Valid (BusErrAddrVld) Indicates that the GBUSERRADDR register is valid and reports the first bus address that encounters a bus error. Note: Only supported in AHB and AXI configurations." "0,1" newline rbitfld.long 0x18 2.--3. "RESERVED_3_2,Reserved" "0,1,2,3" newline rbitfld.long 0x18 0.--1. "CURMOD,Current Mode of Operation (CurMod) Indicates the current mode of operation: - 2'b00: Device mode - 2'b01: Host mode" "Device mode,Host mode,?,?" line.long 0x1C "GUCTL1,Global User Control Register 1" bitfld.long 0x1C 31. "DEV_DECOUPLE_L1L2_EVT,DEV_DECOUPLE_L1L2_EVT - 0: Default behavior no change in device events L1/L2U3 events are not decoupled (old behavior of v2.90a and before) - 1: Feature enabled L1 and L2 events are separated when operating in 2.0 mode. Separate.." "Default behavior,Feature enabled" newline bitfld.long 0x1C 30. "DS_RXDET_MAX_TOUT_CTRL,DS_RXDET_MAX_TOUT_CTRL This bit is used to control the tRxDetectTimeoutDFP timer for the SuperSpeed link. - 0: Default behavior; 12ms is used as tRxDetectTimeoutDFP. - 1: 120ms is used as the tRxDetectTimeoutDFP. This bit is used.." "Default behavior; 12ms is used as..,?" newline bitfld.long 0x1C 29. "FILTER_SE0_FSLS_EOP,FILTER_SE0_FSLS_EOP - 0: Default behavior no change in Linestate check for SE0 detection in FS/LS - 1: Feature enabled FS/LS SE0 is filtered for 2 clocks for detecting EOP This bit is applicable for FS/LS operation. If this feature.." "Default behavior,Feature enabled" newline bitfld.long 0x1C 28. "TX_IPGAP_LINECHECK_DIS,TX_IPGAP_LINECHECK_DIS - 0: Default behavior no change in Linestate check - 1: Feature enabled 2.0 MAC disables Linestate check during HS transmit This bit is applicable for HS operation of u2mac. If this feature is enabled then.." "Default behavior,Feature enabled" newline bitfld.long 0x1C 27. "DEV_TRB_OUT_SPR_IND,DEV_TRB_OUT_SPR_IND - 0: Default behavior no change in TRB status dword - 1: Feature enabled OUT TRB status indicates Short Packet This bit is applicable for device mode only (and ignored in host mode). If the device application.." "Default behavior,Feature enabled" newline bitfld.long 0x1C 26. "DEV_FORCE_20_CLK_FOR_30_CLK,DEV_FORCE_20_CLK_FOR_30_CLK - 0: Default behavior Uses 3.0 clock when operating in 2.0 mode - 1: Feature enabled This bit is applicable (and to be set) for device mode (DCFG.Speed != SS) only. In the 3.0 device controller if.." "Default behavior,Feature enabled" newline bitfld.long 0x1C 25. "P3_IN_U2,P3_IN_U2 - 0: Default behavior When SuperSpeed link is in U2 PowerState P2 is attempted on the PIPE Interface. - 1: When SuperSpeed link is in U2 PowerState P3 is attempted if GUSB3PIPECTL[17] is set. Setting this bit enables P3 Power State.." "Default behavior,When SuperSpeed link is in U2" newline bitfld.long 0x1C 24. "DEV_L1_EXIT_BY_HW,DEV_L1_EXIT_BY_HW - 0: Default behavior disables device L1 hardware exit logic - 1: feature enabled This bit is applicable for device mode (2.0) only. This field enables device controller sending remote wakeup for L1 if the device.." "Default behavior,feature enabled" newline bitfld.long 0x1C 21.--23. "IP_GAP_ADD_ON,This register field is used to add on to the default inter packet gap setting in the USB 2.0 MAC. This should be programmed to a non zero value only in case where you need to increase the default inter packet delay calculations in the USB.." "0,1,2,3,4,5,6,7" newline bitfld.long 0x1C 20. "DEV_LSP_TAIL_LOCK_DIS,DEV_LSP_TAIL_LOCK_DIS - 0: Default behavior enables device lsp lock logic for tail TRB update - 1: Fix disabled This is a bug fix for STAR 9000716195 that affects the CSP mode for OUT endpoints in device mode. The issue is that.." "Default behavior,Fix disabled" newline bitfld.long 0x1C 19. "NAK_PER_ENH_FS,NAK_PER_ENH_FS - 1: Enables performance enhancement for FS async endpoints in the presence of NAKs - 0: Enhancement not applied If a periodic endpoint is present and if a bulk endpoint which is also active is being NAKed by the device.." "Enhancement not applied,Enables performance enhancement for FS async.." newline bitfld.long 0x1C 18. "NAK_PER_ENH_HS,NAK_PER_ENH_HS - 1: Enables performance enhancement for HS async endpoints in the presence of NAKs - 0: Enhancement not applied If a periodic endpoint is present and if a bulk endpoint which is also active is being NAKed by the device.." "Enhancement not applied,Enables performance enhancement for HS async.." newline bitfld.long 0x1C 17. "PARKMODE_DISABLE_SS,PARKMODE_DISABLE_SS This bit is used only in host mode and is for debug purpose only. When this bit is set to '1' all SS bus instances in park mode are disabled." "0,1" newline bitfld.long 0x1C 16. "PARKMODE_DISABLE_HS,PARKMODE_DISABLE_HS This bit is used only in host mode. When this bit is set to '1' all HS bus instances park mode are disabled. To improve performance in park mode the xHCI scheduler queues in three requests of 4 packets each for.." "0,1" newline bitfld.long 0x1C 15. "PARKMODE_DISABLE_FSLS,PARKMODE_DISABLE_FSLS This bit is used only in host mode and is for debug purpose only. When this bit is set to '1' all FS/LS bus instances in park mode disabled." "0,1" newline rbitfld.long 0x1C 13.--14. "RESERVED_14_13,Reserved" "0,1,2,3" newline rbitfld.long 0x1C 12. "DISUSB2REFCLKGTNG,Disable ref_clk gating for 2.0 PHY (DisUSB2RefClkGtng) If ref_clk gating is disabled then the ref_clk input cannot be turned off to the USB 2.0 PHY and controller. This is independent of the GCTL[DisClkGtng] setting. - 1'b0: ref_clk.." "ref_clk gating enabled for USB 2,ref_clk gating disabled for USB 2" newline rbitfld.long 0x1C 11. "DISREFCLKGTNG,Disable ref_clk gating (DisRefClkGtng) If the ref_clk gating is disabled then input ref_clk cannot be turned off to SSPHY and controller. This is independent of GCTL[DisClkGtng] setting. - 1'b0: ref_clk gating Enabled for SSPHY - 1'b1:.." "ref_clk gating Enabled for SSPHY,ref_clk gating Disabled for SSPHY" newline bitfld.long 0x1C 10. "RESUME_OPMODE_HS_HOST,RESUME_OPMODE_HS_HOST This bit is used only in host mode and is for USB 2.0 opmode behavior in HS Resume. - When this bit is set to '1' the UTMI/ULPI opmode will be changed to 'normal' along with HS terminations after EOR. This.." "0,1" newline bitfld.long 0x1C 9. "DEV_HS_NYET_BULK_SPR,DEV_HS_NYET_BULK_SPR - 0: Default behavior no change in device response - 1: Feature enabled HS bulk OUT short packet gets NYET response This bit is applicable for device mode only (and ignored in host mode) to be used in 2.0.." "Default behavior,Feature enabled" newline bitfld.long 0x1C 8. "L1_SUSP_THRLD_EN_FOR_HOST,L1_SUSP_THRLD_EN_FOR_HOST This bit is used only in host mode. The host controller asserts the utmi_l1_suspend_n and utmi_sleep_n output signals (see 'LPM Interface Signals' table in the Databook) as follows: The controller.." "0,1" newline hexmask.long.byte 0x1C 4.--7. 1. "L1_SUSP_THRLD_FOR_HOST,L1_SUSP_THRLD_FOR_HOST This field is effective only when the L1_SUSP_THRLD_EN_FOR_HOST bit is set to 1. For more details refer to the description of the L1_SUSP_THRLD_EN_FOR_HOST bit." newline bitfld.long 0x1C 3. "HC_ERRATA_ENABLE,Host ELD Enable (HELDEn) When this bit is set to 1 it enables the Exit Latency Delta (ELD) support defined in the xHCI 1.0 Errata. This bit is used only in the host mode. This bit has to be set to 1 in Host mode." "0,1" newline bitfld.long 0x1C 2. "HC_PARCHK_DISABLE,Host Parameter Check Disable (HParChkDisable) When this bit is set to '0' (by default) the xHC checks that the input slot/EP context fields comply to the xHCI Specification. Upon detection of a parameter error during command execution.." "0,1" newline bitfld.long 0x1C 1. "OVRLD_L1_SUSP_COM,OVRLD_L1_SUSP_COM If this bit is set the utmi_l1_suspend_com_n is overloaded with the utmi_sleep_n signal. This bit is usually set if the PHY stops the port clock during L1 sleep condition. Note: The recommended connection for the.." "For Synopsys PHY,?" newline bitfld.long 0x1C 0. "LOA_FILTER_EN,LOA_FILTER_EN If this bit is set the USB 2.0 port babble is checked at least three consecutive times before the port is disabled. This prevents false triggering of the babble condition when using low quality cables. Note: This bit is valid.." "0,1" rgroup.long (0x20+0x49408)++0x3 line.long 0x0 "GSNPSID,Global Synopsys ID Register This is a read-only register that contains the release number of the controller." hexmask.long 0x0 0.--31. 1. "SYNOPSYSID,Synopsys ID - SynopsysID[31:16] indicates Core Identification Number. 0x5533 is ASCII for U3 (DWC_usb3). - SynopsysID[15:0] indicates the release number. Current Release is 3.30a. Software uses this register to configure release-specific.." group.long (0x24+0x49408)++0xB line.long 0x0 "GGPIO,Global General Purpose Input/Output Register The application can use this register for general purpose input and output ports or for debugging." hexmask.long.word 0x0 16.--31. 1. "GPO,General Purpose Output The value of this field is driven out on the gp_out[15:0] output port." newline hexmask.long.word 0x0 0.--15. 1. "GPI,General Purpose Input The read value of this field reflects the gp_in[15:0] input signal value. Note: Register bit-bash test should not check for reset value of this field since its not predictable; depends on the gp_in port." line.long 0x4 "GUID,Global User ID Register This is a read/write register containing the User ID. The power-on value for this register is specified as the User Identification Register. Power-on value during coreConsultant configuration (parameter DWC_USB3_USERID). This.." hexmask.long 0x4 0.--31. 1. "USERID,USERID Application-programmable ID field." line.long 0x8 "GUCTL,Global User Control Register: This register provides a few options for the software to control the controller behavior in the Host mode. Most of the options are used to improve host inter-operability with different devices." hexmask.long.word 0x8 22.--31. 1. "REFCLKPER,REFCLKPER This field indicates in terms of nano seconds the period of ref_clk. The default value of this register is set to 'h8 (8ns/125 MHz). This field needs to be updated during power-on initialization if GCTL.SOFITPSYNC or.." newline bitfld.long 0x8 21. "NOEXTRDL,No Extra Delay Between SOF and the First Packet(NoExtrDl) Some HS devices misbehave when the host sends a packet immediately after a SOF. However adding an extra delay between a SOF and the first packet can reduce the USB data rate and.." "Host waits for 2 microseconds after a SOF before..,Host doesn't wait after a SOF before it sends.." newline rbitfld.long 0x8 18.--20. "RESERVED_20_18,Reserved" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 17. "SPRSCTRLTRANSEN,Sparse Control Transaction Enable Some devices are slow in responding to Control transfers. Scheduling multiple transactions in one microframe/frame can cause these devices to misbehave. If this bit is set to 1'b1 the host controller.." "0,1" newline bitfld.long 0x8 16. "RESBWHSEPS,Reserving 85% Bandwidth for HS Periodic EPs (ResBwHSEPS) By default HC reserves 80% of the bandwidth for periodic EPs. If this bit is set the bandwidth is relaxed to 85% to accommodate two high speed high bandwidth ISOC EPs. USB 2.0.." "0,1" newline rbitfld.long 0x8 15. "RESERVED_15,Reserved" "0,1" newline bitfld.long 0x8 14. "USBHSTINAUTORETRYEN,Host IN Auto Retry (USBHstInAutoRetryEn) When set this field enables the Auto Retry feature. For IN transfers (non-isochronous) that encounter data packets with CRC errors or internal overrun scenarios the auto retry feature causes.." "Auto Retry Disabled,Auto Retry Enabled" newline bitfld.long 0x8 13. "ENOVERLAPCHK,Enable Check for LFPS Overlap During Remote Ux Exit: If this bit is set to - 1'b1: The SuperSpeed link when exiting U1/U2/U3 waits for either the remote link LFPS or TS1/TS2 training symbols before it confirms that the LFPS handshake is.." "When the link exists U1/U2/U3 because of a..,The SuperSpeed link when exiting U1/U2/U3 waits.." newline bitfld.long 0x8 12. "EXTCAPSUPPTEN,External Extended Capability Support Enable (ExtCapSuptEN) When set this field enables extended capabilities to be implemented outside the controller. When the ExtCapSupEN is set and the Debug Capability is enabled the Next Capability.." "0,1" newline bitfld.long 0x8 11. "INSRTEXTRFSBODI,Insert Extra Delay Between FS Bulk OUT Transactions (InsrtExtrFSBODl). Some FS devices are slow to receive Bulk OUT data and can get stuck when there are consecutive Bulk OUT transactions with short inter-transaction delays. This bit is.." "Host doesn't insert extra delay between..,Host inserts about 12us extra delay between.." newline bitfld.long 0x8 9.--10. "DTCT,Device Timeout Coarse Tuning (DTCT) This field is a Host mode parameter which determines how long the host waits for a response from device before considering a timeout. The controller first checks the DTCT value. If it is 0 then the timeout value.." "0,1,2,3" newline hexmask.long.word 0x8 0.--8. 1. "DTFT,Device Timeout Fine Tuning (DTFT) This field is a Host mode parameter which determines how long the host waits for a response from device before considering a timeout. For the DTFT field to take effect DTCT must be set to 2'b00. The DTFT value is.." rgroup.long (0x30+0x49408)++0x7 line.long 0x0 "GBUSERRADDRLO,Gobal SoC Bus Error Address Register - Low This is an alternate register for the GBUSERRADDR register." hexmask.long 0x0 0.--31. 1. "BUSERRADDR,Bus Address - Low (BusAddrLo) This register contains the lower 32 bits of the first bus address that encountered a SoC bus error. It is valid when the GSTS.BusErrAddrVld field is 1. It can only be cleared by resetting the controller. Note:.." line.long 0x4 "GBUSERRADDRHI,Gobal SoC Bus Error Address Register - High This is an alternate register for the GBUSERRADDR register." hexmask.long 0x4 0.--31. 1. "BUSERRADDR,Bus Address - High (BusAddrHi) This register contains the higher 32 bits of the first bus address that encountered a SoC bus error. It is valid when the GSTS.BusErrAddrVld field is 1. It can only be cleared by resetting the controller. Note:.." group.long (0x38+0x49408)++0x7 line.long 0x0 "GPRTBIMAPLO,Global SS Port to Bus Instance Mapping Register - Low This is an alternate register for the GPRTBIMAP register. Register fields are read-write with respect to number of port instantiated. writeAsRead constraint is added to limit side effects.." hexmask.long.byte 0x0 28.--31. 1. "BINUM8,BINUM8: SS USB Instance Number for Port 8. Application-programmable ID field." newline hexmask.long.byte 0x0 24.--27. 1. "BINUM7,BINUM7: SS USB Instance Number for Port 7. Application-programmable ID field." newline hexmask.long.byte 0x0 20.--23. 1. "BINUM6,BINUM6: SS USB Instance Number for Port 6. Application-programmable ID field." newline hexmask.long.byte 0x0 16.--19. 1. "BINUM5,BINUM5: SS USB Instance Number for Port 5. Application-programmable ID field." newline hexmask.long.byte 0x0 12.--15. 1. "BINUM4,BINUM4: SS USB Instance Number for Port 4. Application-programmable ID field." newline hexmask.long.byte 0x0 8.--11. 1. "BINUM3,BINUM3: SS USB Instance Number for Port 3. Application-programmable ID field." newline hexmask.long.byte 0x0 4.--7. 1. "BINUM2,BINUM2: SS USB Instance Number for Port 2. Application-programmable ID field." newline hexmask.long.byte 0x0 0.--3. 1. "BINUM1,BINUM1: SS USB Instance Number for Port 1. Application-programmable ID field." line.long 0x4 "GPRTBIMAPHI,Global SS Port to Bus Instance Mapping Register - High This is an alternate register for the GPRTBIMAP register. For a configuration with number of USB 3.0 ports same as number of SS Bus Instances. do not remap during debug session. If you.." hexmask.long.byte 0x4 28.--31. 1. "RESERVED_31_28,Reserved" newline hexmask.long.byte 0x4 24.--27. 1. "BINUM15,BINUM15: SS USB Instance Number for Port 15. Application-programmable ID field." newline hexmask.long.byte 0x4 20.--23. 1. "BINUM14,BINUM14: SS USB Instance Number for Port 14. Application-programmable ID field." newline hexmask.long.byte 0x4 16.--19. 1. "BINUM13,BINUM13: SS USB Instance Number for Port 13. Application-programmable ID field." newline hexmask.long.byte 0x4 12.--15. 1. "BINUM12,BINUM12: SS USB Instance Number for Port 12. Application-programmable ID field." newline hexmask.long.byte 0x4 8.--11. 1. "BINUM11,BINUM11: SS USB Instance Number for Port 11. Application-programmable ID field." newline hexmask.long.byte 0x4 4.--7. 1. "BINUM10,BINUM10: SS USB Instance Number for Port 10. Application-programmable ID field." newline hexmask.long.byte 0x4 0.--3. 1. "BINUM9,BINUM9: SS USB Instance Number for Port 9. Application-programmable ID field." rgroup.long (0x40+0x49408)++0x7 line.long 0x0 "GHWPARAMS0,Global Hardware Parameters Register 0 This register contains the hardware configuration options that you can select in the coreConsultant GUI. For a description of each parameter. refer to the 'Parameter Descriptions' chapter in the Databook." hexmask.long.byte 0x0 24.--31. 1. "GHWPARAMS0_31_24,`DWC_USB3_AWIDTH" newline hexmask.long.byte 0x0 16.--23. 1. "GHWPARAMS0_23_16,`DWC_USB3_SDWIDTH" newline hexmask.long.byte 0x0 8.--15. 1. "GHWPARAMS0_15_8,`DWC_USB3_MDWIDTH" newline bitfld.long 0x0 6.--7. "GHWPARAMS0_7_6,`DWC_USB3_SBUS_TYPE" "0,1,2,3" newline bitfld.long 0x0 3.--5. "GHWPARAMS0_5_3,`DWC_USB3_MBUS_TYPE" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 0.--2. "GHWPARAMS0_2_0,`DWC_USB3_MODE" "0,1,2,3,4,5,6,7" line.long 0x4 "GHWPARAMS1,Global Hardware Parameters Register 1 This register contains the hardware configuration options that you can select in the coreConsultant GUI. For a description of each parameter. refer to the 'Parameter Descriptions' chapter in the Databook." bitfld.long 0x4 31. "GHWPARAMS1_31,`DWC_USB3_EN_DBC" "0,1" newline bitfld.long 0x4 30. "GHWPARAMS1_30,`DWC_USB3_RM_OPT_FEATURES" "0,1" newline bitfld.long 0x4 29. "GHWPARAMS1_29,Reserved1" "0,1" newline bitfld.long 0x4 28. "GHWPARAMS1_28,`DWC_USB3_RAM_BUS_CLKS_SYNC" "0,1" newline bitfld.long 0x4 27. "GHWPARAMS1_27,`DWC_USB3_MAC_RAM_CLKS_SYNC" "0,1" newline bitfld.long 0x4 26. "GHWPARAMS1_26,`DWC_USB3_MAC_PHY_CLKS_SYNC" "0,1" newline bitfld.long 0x4 24.--25. "GHWPARAMS1_25_24,`DWC_USB3_EN_PWROPT" "0,1,2,3" newline bitfld.long 0x4 23. "GHWPARAMS1_23,`DWC_USB3_SPRAM_TYP" "0,1" newline bitfld.long 0x4 21.--22. "GHWPARAMS1_22_21,`DWC_USB3_NUM_RAMS" "0,1,2,3" newline hexmask.long.byte 0x4 15.--20. 1. "GHWPARAMS1_20_15,`DWC_USB3_DEVICE_NUM_INT For details on `DWC_USB3_DEVICE_NUM_INT refer to /src/DWC_usb3_params.v file." newline bitfld.long 0x4 12.--14. "GHWPARAMS1_14_12,`DWC_USB3_ASPACEWIDTH" "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 9.--11. "GHWPARAMS1_11_9,`DWC_USB3_REQINFOWIDTH" "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 6.--8. "GHWPARAMS1_8_6,`DWC_USB3_DATAINFOWIDTH" "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 3.--5. "GHWPARAMS1_5_3,`DWC_USB3_BURSTWIDTH-1" "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 0.--2. "GHWPARAMS1_2_0,`DWC_USB3_IDWIDTH-1" "0,1,2,3,4,5,6,7" repeat 2. (list 0x2 0x8 )(list 0x0 0x4B8 ) rgroup.long ($2+0x48+0x49408)++0x3 line.long 0x0 "GHWPARAMS$1,Global Hardware Parameters Register 2 This register contains the hardware configuration options that you can select in the coreConsultant GUI. For a description of each parameter. refer to the 'Parameter Descriptions' chapter in the Databook." hexmask.long 0x0 0.--31. 1. "GHWPARAMS2_31_0,`DWC_USB3_USERID" repeat.end rgroup.long (0x4C+0x49408)++0x13 line.long 0x0 "GHWPARAMS3,Global Hardware Parameters Register 3 This register contains the hardware configuration options that you can select in the coreConsultant GUI. For a description of each parameter. refer to the 'Parameter Descriptions' chapter in the Databook." bitfld.long 0x0 31. "GHWPARAMS3_31,Reserved" "0,1" newline hexmask.long.byte 0x0 23.--30. 1. "GHWPARAMS3_30_23,`DWC_USB3_CACHE_TOTAL_XFER_RESOURCES" newline hexmask.long.byte 0x0 18.--22. 1. "GHWPARAMS3_22_18,`DWC_USB3_NUM_IN_EPS" newline hexmask.long.byte 0x0 12.--17. 1. "GHWPARAMS3_17_12,`DWC_USB3_NUM_EPS" newline bitfld.long 0x0 11. "GHWPARAMS3_11,`DWC_USB3_ULPI_CARKIT" "0,1" newline bitfld.long 0x0 10. "GHWPARAMS3_10,`DWC_USB3_VENDOR_CTL_INTERFACE" "0,1" newline bitfld.long 0x0 8.--9. "GHWPARAMS3_9_8,Reserved" "0,1,2,3" newline bitfld.long 0x0 6.--7. "GHWPARAMS3_7_6,`DWC_USB3_HSPHY_DWIDTH" "0,1,2,3" newline bitfld.long 0x0 4.--5. "GHWPARAMS3_5_4,`DWC_USB3_FSPHY_INTERFACE" "0,1,2,3" newline bitfld.long 0x0 2.--3. "GHWPARAMS3_3_2,`DWC_USB3_HSPHY_INTERFACE" "0,1,2,3" newline bitfld.long 0x0 0.--1. "GHWPARAMS3_1_0,`DWC_USB3_SSPHY_INTERFACE" "0,1,2,3" line.long 0x4 "GHWPARAMS4,Global Hardware Parameters Register 4 This register contains the hardware configuration options that you can select in the coreConsultant GUI. For a description of each parameter. refer to the 'Parameter Descriptions' chapter in the Databook." hexmask.long.byte 0x4 28.--31. 1. "GHWPARAMS4_31_28,`DWC_USB3_BMU_LSP_DEPTH" newline hexmask.long.byte 0x4 24.--27. 1. "GHWPARAMS4_27_24,`DWC_USB3_BMU_PTL_DEPTH-1" newline bitfld.long 0x4 23. "GHWPARAMS4_23,`DWC_USB3_EN_ISOC_SUPT" "0,1" newline bitfld.long 0x4 22. "GHWPARAMS4_22,Reserved" "0,1" newline bitfld.long 0x4 21. "GHWPARAMS4_21,`DWC_USB3_EXT_BUFF_CONTROL" "0,1" newline hexmask.long.byte 0x4 17.--20. 1. "GHWPARAMS4_20_17,`DWC_USB3_NUM_SS_USB_INSTANCES" newline hexmask.long.byte 0x4 13.--16. 1. "GHWPARAMS4_16_13,`DWC_USB3_HIBER_SCRATCHBUFS Number of external scratchpad buffers the controller requires to save its internal state in the device mode. Each buffer is assumed to be 4KB. The scratchpad buffer array must have this many buffer pointers." newline bitfld.long 0x4 12. "GHWPARAMS4_12,Reserved" "0,1" newline bitfld.long 0x4 11. "GHWPARAMS4_11,Reserved" "0,1" newline bitfld.long 0x4 9.--10. "GHWPARAMS4_10_9,Reserved" "0,1,2,3" newline bitfld.long 0x4 7.--8. "GHWPARAMS4_8_7,Reserved" "0,1,2,3" newline bitfld.long 0x4 6. "GHWPARAMS4_6,Reserved" "0,1" newline hexmask.long.byte 0x4 0.--5. 1. "GHWPARAMS4_5_0,`DWC_USB3_CACHE_TRBS_PER_TRANSFER" line.long 0x8 "GHWPARAMS5,Global Hardware Parameters Register 5 This register contains the hardware configuration options that you can select in the coreConsultant GUI. For a description of each parameter. refer to the 'Parameter Descriptions' chapter in the Databook." hexmask.long.byte 0x8 28.--31. 1. "GHWPARAMS5_31_28,Reserved" newline hexmask.long.byte 0x8 22.--27. 1. "GHWPARAMS5_27_22,`DWC_USB3_DFQ_FIFO_DEPTH" newline hexmask.long.byte 0x8 16.--21. 1. "GHWPARAMS5_21_16,`DWC_USB3_DWQ_FIFO_DEPTH" newline hexmask.long.byte 0x8 10.--15. 1. "GHWPARAMS5_15_10,`DWC_USB3_TXQ_FIFO_DEPTH" newline hexmask.long.byte 0x8 4.--9. 1. "GHWPARAMS5_9_4,`DWC_USB3_RXQ_FIFO_DEPTH" newline hexmask.long.byte 0x8 0.--3. 1. "GHWPARAMS5_3_0,`DWC_USB3_BMU_BUSGM_DEPTH" line.long 0xC "GHWPARAMS6,Global Hardware Parameters Register 6 This register contains the hardware configuration options that you can select in the coreConsultant GUI. For a description of each parameter. refer to the 'Parameter Descriptions' chapter in the Databook." hexmask.long.word 0xC 16.--31. 1. "GHWPARAMS6_31_16,`DWC_USB3_RAM0_DEPTH" newline bitfld.long 0xC 15. "BUSFLTRSSUPPORT,`DWC_USB3_EN_BUS_FILTERS" "0,1" newline bitfld.long 0xC 14. "BCSUPPORT,`DWC_USB3_EN_BC" "0,1" newline bitfld.long 0xC 13. "OTG_SS_SUPPORT,Reserved" "0,1" newline bitfld.long 0xC 12. "ADPSUPPORT,`DWC_USB3_EN_ADP" "0,1" newline bitfld.long 0xC 11. "HNPSUPPORT,Reserved" "0,1" newline bitfld.long 0xC 10. "SRPSUPPORT,Reserved" "0,1" newline bitfld.long 0xC 8.--9. "GHWPARAMS6_9_8,Reserved" "0,1,2,3" newline bitfld.long 0xC 7. "GHWPARAMS6_7,`DWC_USB3_EN_FPGA" "0,1" newline bitfld.long 0xC 6. "GHWPARAMS6_6,`DWC_USB3_EN_DBG_PORTS" "0,1" newline hexmask.long.byte 0xC 0.--5. 1. "GHWPARAMS6_5_0,`DWC_USB3_PSQ_FIFO_DEPTH" line.long 0x10 "GHWPARAMS7,Global Hardware Parameters Register 7 This register contains the hardware configuration options that you can select in the coreConsultant GUI. For a description of each parameter. refer to the 'Parameter Descriptions' chapter in the Databook." hexmask.long.word 0x10 16.--31. 1. "GHWPARAMS7_31_16,`DWC_USB3_RAM2_DEPTH" newline hexmask.long.word 0x10 0.--15. 1. "GHWPARAMS7_15_0,`DWC_USB3_RAM1_DEPTH" group.long (0x60+0x49408)++0x3 line.long 0x0 "GDBGFIFOSPACE,Global Debug Queue/FIFO Space Available Register Bit Bash test should not be done on this debug register." hexmask.long.word 0x0 16.--31. 1. "SPACE_AVAILABLE,SPACE_AVAILABLE" newline hexmask.long.byte 0x0 9.--15. 1. "RESERVED_15_9,Reserved" newline hexmask.long.word 0x0 0.--8. 1. "FIFO_QUEUE_SELECT,FIFO/Queue Select (or) Port-Select - FIFO/Queue Select[8:5] indicates the FIFO/Queue Type - FIFO/Queue Select[4:0] indicates the FIFO/Queue Number For example 9'b0_0010_0001 refers to RxFIFO_1 and 9'b0_0101_1110 refers to TxReqQ_30. -.." rgroup.long (0x64+0x49408)++0xB line.long 0x0 "GDBGLTSSM,Global Debug LTSSM Register In multi-port host configuration. the port-number is defined by Port-Select[3:0] field in the GDBGFIFOSPACE register. Note: - GDBGLTSSM register is not applicable for USB 2.0-only mode. - Bit Bash test should not be.." bitfld.long 0x0 31. "RESERVED_31_31,Reserved" "0,1" newline bitfld.long 0x0 30. "RXELECIDLE,RxElecidle For description of RxElecIdle see table 5-4 'Status Interface Signals' of the PIPE3 Specification." "0,1" newline bitfld.long 0x0 29. "X3_XS_SWAPPING,Reserved" "0,1" newline bitfld.long 0x0 28. "X3_DS_HOST_SHUTDOWN,Reserved" "0,1" newline bitfld.long 0x0 27. "PRTDIRECTION,Reserved" "0,1" newline bitfld.long 0x0 26. "LTDBTIMEOUT,LTDB Timeout (LTDBTimeout)" "0,1" newline hexmask.long.byte 0x0 22.--25. 1. "LTDBLINKSTATE,LTDB Link State (LTDBLinkState)" newline hexmask.long.byte 0x0 18.--21. 1. "LTDBSUBSTATE,LTDB Sub-State (LTDBSubState)" newline bitfld.long 0x0 17. "ELASTICBUFFERMODE,Elastic Buffer Mode (ElasticBufferMode) For field definition refer to Table 5-3 of the PIPE3 specification." "0,1" newline bitfld.long 0x0 16. "TXELECLDLE,Tx Elec Idle (TxElecIdle) For field definition refer to Table 5-3 of the PIPE3 specification." "0,1" newline bitfld.long 0x0 15. "RXPOLARITY,Rx Polarity (RxPolarity) For field definition refer to Table 5-3 of the PIPE3 specification." "0,1" newline bitfld.long 0x0 14. "TXDETRXLOOPBACK,Tx Detect Rx/Loopback (TxDetRxLoopback) For field definition refer to Table 5-3 of the PIPE3 specification." "0,1" newline bitfld.long 0x0 11.--13. "LTDBPHYCMDSTATE,LTSSM PHY command State (LTDBPhyCmdState) - 000: PHY_IDLE (PHY command state is in IDLE. No PHY request pending) - 001: PHY_DET (Request to start Receiver detection) - 010: PHY_DET_3 (Wait for Phy_Status (Receiver detection)) - 011:.." "P1/P2/P3 request),PHY_DET,?,?,?,?,?,?" newline bitfld.long 0x0 9.--10. "POWERDOWN,POWERDOWN (PowerDown) For field definition refer to Table 5-3 of the PIPE3 specification." "0,1,2,3" newline bitfld.long 0x0 8. "RXEQTRAIN,RxEq Train For field definition refer to Table 5-3 of the PIPE3 specification." "0,1" newline bitfld.long 0x0 6.--7. "TXDEEMPHASIS,TXDEEMPHASIS (TxDeemphasis) For field definition refer to Table 5-3 of the PIPE3 specification." "0,1,2,3" newline bitfld.long 0x0 3.--5. "LTDBCLKSTATE,LTSSM Clock State (LTDBClkState) In multi-port host configuration the port number is defined by Port-Select[3:0] field in the GDBGFIFOSPACE register. Note: GDBGLTSSM register is not applicable for USB 2.0-only mode. - 000: CLK_NORM (PHY is.." "CLK_NORM,CLK_TO_P3,?,?,?,?,?,?" newline bitfld.long 0x0 2. "TXSWING,Tx Swing (TxSwing) For field definition refer to Table 5-3 of the PIPE3 specification." "0,1" newline bitfld.long 0x0 1. "RXTERMINATION,Rx Termination (RxTermination) For details on `DWC_USB3_PIPE_RXTERM_RESET_VAL refer to /src/DWC_usb3_params.v" "0,1" newline bitfld.long 0x0 0. "TXONESZEROS,Tx Ones/Zeros (TxOnesZeros) For field definition refer to Table 5-3 of the PIPE3 specification." "0,1" line.long 0x4 "GDBGLNMCC,Global Debug LNMCC Register Bit Bash test should not be done on this debug register." hexmask.long.tbyte 0x4 9.--31. 1. "RESERVED_31_9,Reserved" newline hexmask.long.word 0x4 0.--8. 1. "LNMCC_BERC,This field indicates the bit error rate information for the port selected in the GDBGFIFOSPACE.PortSelect field. This field is for debug purposes only." line.long 0x8 "GDBGBMU,Global Debug BMU Register Bit Bash test should not be done on this debug register." hexmask.long.tbyte 0x8 8.--31. 1. "BMU_BCU,BMU_BCU Debug information" newline hexmask.long.byte 0x8 4.--7. 1. "BMU_DCU,BMU_DCU Debug information" newline hexmask.long.byte 0x8 0.--3. 1. "BMU_CCU,BMU_CCU Debug information" group.long (0x70+0x49408)++0x3 line.long 0x0 "GDBGLSPMUX_HST,Global Debug LSP MUX Register - Host This register is for internal use only. If DWC_USB3_PRESERVE_LOGIC_ANALYZER_SELECT is enabled during controller configuration. then the default values readout is X (Undefined). Bit Bash test should not.." hexmask.long.byte 0x0 24.--31. 1. "RESERVED_31_24,Reserved" newline hexmask.long.byte 0x0 16.--23. 1. "LOGIC_ANALYZER_TRACE,logic_analyzer_trace Port MUX Select Currently only bits[21:16] are used. For details on how the mux controls the debug traces refer to the 'assign logic_analyzer_trace =' code section in the DWC_usb3.v file. A value of 6'h3F drives.." newline rbitfld.long 0x0 14.--15. "RESERVED_15_14,Reserved" "0,1,2,3" newline hexmask.long.word 0x0 0.--13. 1. "HOSTSELECT,Device LSP Select Selects the LSP debug information presented in the GDBGLSP register in host mode." rgroup.long (0x74+0x49408)++0x3 line.long 0x0 "GDBGLSP,Global Debug LSP Register This register is for internal debug purposes only. This register is for internal use only. If DWC_USB3_PRESERVE_LOGIC_ANALYZER_SELECT is enabled during controller configuration. then the default values readout is X.." hexmask.long 0x0 0.--31. 1. "LSPDEBUG,LSP Debug Information" repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) rgroup.long ($2+0x78+0x49408)++0x3 line.long 0x0 "GDBGEPINFO$1,Global Debug Endpoint Information Register 0 This register is for internal use only. If DWC_USB3_PRESERVE_LOGIC_ANALYZER_SELECT is enabled during controller configuration. then the default values readout is X (Undefined). Bit Bash test.." hexmask.long 0x0 0.--31. 1. "EPDEBUG,Endpoint Debug Information bits[31:0]" repeat.end group.long (0x80+0x49408)++0xF line.long 0x0 "GPRTBIMAP_HSLO,Global High-Speed Port to Bus Instance Mapping Register - Low This is an alternate register for the GPRTBIMAP_HS register. - Register fields are read-write with respect to number of port instantiated. writeAsRead constraint is added to.." hexmask.long.byte 0x0 28.--31. 1. "BINUM8,BINUM8: HS USB Instance Number for Port 8. Application-programmable ID field." newline hexmask.long.byte 0x0 24.--27. 1. "BINUM7,BINUM7: HS USB Instance Number for Port 7. Application-programmable ID field." newline hexmask.long.byte 0x0 20.--23. 1. "BINUM6,BINUM6 USB Instance Number for Port 6. Application-programmable ID field." newline hexmask.long.byte 0x0 16.--19. 1. "BINUM5,BINUM5: HS USB Instance Number for Port 5. Application-programmable ID field." newline hexmask.long.byte 0x0 12.--15. 1. "BINUM4,BINUM4: HS USB Instance Number for Port 4. Application-programmable ID field." newline hexmask.long.byte 0x0 8.--11. 1. "BINUM3,BINUM3: HS USB Instance Number for Port 3. Application-programmable ID field." newline hexmask.long.byte 0x0 4.--7. 1. "BINUM2,BINUM2: HS USB Instance Number for Port 2. Application-programmable ID field." newline hexmask.long.byte 0x0 0.--3. 1. "BINUM1,BINUM1: HS USB Instance Number for Port 1. Application-programmable ID field." line.long 0x4 "GPRTBIMAP_HSHI,Global High-Speed Port to Bus Instance Mapping Register - High This is an alternate register for the GPRTBIMAP_HS register. - Register fields are read-write with respect to number of port instantiated. writeAsRead constraint is added to.." hexmask.long.byte 0x4 28.--31. 1. "RESERVED_31_28,Reserved" newline hexmask.long.byte 0x4 24.--27. 1. "BINUM15,BINUM15: HS USB Instance Number for Port 15. Application-programmable ID field." newline hexmask.long.byte 0x4 20.--23. 1. "BINUM14,BINUM14: HS USB Instance Number for Port 14. Application-programmable ID field." newline hexmask.long.byte 0x4 16.--19. 1. "BINUM13,BINUM13: HS USB Instance Number for Port 13. Application-programmable ID field." newline hexmask.long.byte 0x4 12.--15. 1. "BINUM12,BINUM12: HS USB Instance Number for Port 12. SApplication-programmable ID field." newline hexmask.long.byte 0x4 8.--11. 1. "BINUM11,BINUM11: HS USB Instance Number for 11. Application-programmable ID field." newline hexmask.long.byte 0x4 4.--7. 1. "BINUM10,BINUM10: HS USB Instance Number for Port 10. Application-programmable ID field." newline hexmask.long.byte 0x4 0.--3. 1. "BINUM9,BINUM9: HS USB Instance Number for Port 9. Application-programmable ID field." line.long 0x8 "GPRTBIMAP_FSLO,Global Full-Speed Port to Bus Instance Mapping Register - Low This is an alternate register for the GPRTBIMAP_FS register. - Register fields are read-write with respect to number of port instantiated. writeAsRead constraint is added to.." hexmask.long.byte 0x8 28.--31. 1. "BINUM8,BINUM8: FS USB Instance Number for Port 8. Application-programmable ID field." newline hexmask.long.byte 0x8 24.--27. 1. "BINUM7,BINUM7: FS USB Instance Number for Port 7. Application-programmable ID field." newline hexmask.long.byte 0x8 20.--23. 1. "BINUM6,BINUM6: FS USB Instance Number for Port 6. Application-programmable ID field." newline hexmask.long.byte 0x8 16.--19. 1. "BINUM5,BINUM5: FS USB Instance Number for Port 5. Application-programmable ID field." newline hexmask.long.byte 0x8 12.--15. 1. "BINUM4,BINUM4: FS USB Instance Number for Port 4. Application-programmable ID field." newline hexmask.long.byte 0x8 8.--11. 1. "BINUM3,BINUM3: FS USB Instance Number for Port 3. Application-programmable ID field." newline hexmask.long.byte 0x8 4.--7. 1. "BINUM2,BINUM2: FS USB Instance Number for Port 2. Application-programmable ID field." newline hexmask.long.byte 0x8 0.--3. 1. "BINUM1,BINUM1: FS USB Instance Number for Port 1. Application-programmable ID field." line.long 0xC "GPRTBIMAP_FSHI,Global Full-Speed Port to Bus Instance Mapping Register - High This is an alternate register for the GPRTBIMAP_FS register. - Register fields are read-write with respect to number of port instantiated. writeAsRead constraint is added to.." hexmask.long.byte 0xC 28.--31. 1. "RESERVED_31_28,Reserved" newline hexmask.long.byte 0xC 24.--27. 1. "BINUM15,BINUM15: FS USB Instance Number for Port 15. Application-programmable ID field" newline hexmask.long.byte 0xC 20.--23. 1. "BINUM14,BINUM14: FS USB Instance Number for Port 14. Application-programmable ID field" newline hexmask.long.byte 0xC 16.--19. 1. "BINUM13,BINUM13: FS USB Instance Number for Port 13. Application-programmable ID field" newline hexmask.long.byte 0xC 12.--15. 1. "BINUM12,BINUM12: FS USB Instance Number for Port 12. Application-programmable ID field" newline hexmask.long.byte 0xC 8.--11. 1. "BINUM11,BINUM11: FS USB Instance Number for Port 11. Application-programmable ID field" newline hexmask.long.byte 0xC 4.--7. 1. "BINUM10,BINUM10: FS USB Instance Number for Port 10. Application-programmable ID field" newline hexmask.long.byte 0xC 0.--3. 1. "BINUM9,BINUM9: FS USB Instance Number for Port 9. Application-programmable ID field." repeat 2. (list 0x5E 0x62 )(list 0x0 0x4 ) rgroup.long ($2+0x94+0x49408)++0x3 line.long 0x0 "RESERVED_$1,Future Reserved Register at offset 0x94" hexmask.long 0x0 0.--31. 1. "RESERVED_31_0,Future use Register field" repeat.end group.long (0x9C+0x49408)++0x3 line.long 0x0 "GUCTL2,Global User Control Register 2: This register provides a few options for the software to control the controller behavior in the Host and device mode. Most of the options are used to improve inter-operability with different hosts and devices." hexmask.long.byte 0x0 26.--31. 1. "RESERVED_31_26,Reserved" newline hexmask.long.byte 0x0 19.--25. 1. "EN_HP_PM_TIMER,This register field is used to set new HP and PM timers. - To enable PM timer set GUCTL2[19] bit as 1. - To enable HP timer set GUCTL2[20] bit as 1. Default value of HP timer is 4us when HP PM timer is not enabled; when new HP timer is.." newline hexmask.long.byte 0x0 15.--18. 1. "NOLOWPWRDUR,No Low Power Duration (NOLOWPWRDUR) This bit is applicable for device mode only and is ignored in host mode. After starting a transfer on a SS ISOC endpoint the application must program these bits to prevent the device to lose frame.." newline bitfld.long 0x0 14. "RST_ACTBITLATER,Enable clearing of the command active bit for the ENDXFER command after the command execution is completed. This bit is valid in device mode only." "0,1" newline rbitfld.long 0x0 13. "RESERVED_13,Reserved for future use" "0,1" newline bitfld.long 0x0 12. "ENABLEEPCACHEEVICT,Enable Evicting Endpoint cache after Flow Control for bulk endpoints. In 3.00a release a performance enhancement was done to keep the non-stream capable bulk IN endpoint in cache after flow control. Setting this bit will disable this.." "0,1" newline bitfld.long 0x0 11. "DISABLECFC,Disable xHCI Errata Feature Contiguous Frame ID Capability This field controls the xHCI Errata feature Contiguous FrameID capability. When set the xHCI HCCPARAMS1 bit 11 will be set to 0 indicating that CFC is not supported. Disable this.." "0,1" newline hexmask.long.byte 0x0 5.--10. 1. "RXPINGDURATION,Recieve Ping Maximum Duration This field is relevant to Host mode and controls the maximum duration of received LFPS to be treated as a Ping LFPS. The Max duration of the Ping LFPS is controlled by programming this value and is in terms of.." newline hexmask.long.byte 0x0 0.--4. 1. "TXPINGDURATION,Transmit Ping Maximum Duration This field is relevant to Device mode and controls the maximum duration for which the controller should instruct the PHY to transmit a Ping LFPS. The duration of the Ping LFPS is controlled by programming.." group.long (0x100+0x49408)++0x3 line.long 0x0 "GUSB2PHYCFG,Global USB2 PHY Configuration Register The application must program this register before starting any transactions on either the SoC bus or the USB. In Device-only configurations. only one register is needed. In Host mode. per-port registers.." bitfld.long 0x0 31. "PHYSOFTRST,UTMI PHY Soft Reset (PHYSoftRst) Causes the usb2phy_reset signal to be asserted to reset a UTMI PHY. Not applicable to ULPI because ULPI PHYs are reset via their FunctionControl.Reset register and the controller automatically writes to this.." "0,1" newline bitfld.long 0x0 30. "U2_FREECLK_EXISTS,U2_FREECLK_EXISTS Specifies whether your USB 2.0 PHY provides a free-running PHY clock which is active when the clock control input is active. If your USB 2.0 PHY provides a free-running PHY clock it must be connected to the.." "USB 2,USB 2" newline bitfld.long 0x0 29. "ULPI_LPM_WITH_OPMODE_CHK,ULPI_LPM_WITH_OPMODE_CHK Support the LPM over ULPI without NOPID token to the ULPI PHY. If this bit is set the ULPI PHY is expected to qualify the EXT PID with OPMODE=2'b00 for LPM and not treat it as a NOPID. Check with your.." "A NOPID is sent before sending an EXTPID for LPM;,An EXTPID is sent without previously sending a.." newline rbitfld.long 0x0 27.--28. "HSIC_CON_WIDTH_ADJ,HSIC_CON_WIDTH_ADJ This bit is used in the HSIC device mode of operation. By default the connect duration for the HSIC device controller is thrice the strobe period. You can change this duration to 4 5 or 6 times the strobe period.." "0,1,2,3" newline rbitfld.long 0x0 26. "INV_SEL_HSIC,INV_SEL_HSIC The application driver uses this bit to control the HSIC enable/disable function. When set to '1' this bit overrides and functionally inverts the 'if_select_hsic' input signal. If {INV_SEL_HSIC if_select_hsic} is: - 00: HSIC.." "HSIC Capability is disabled,HSIC Capability is enabled" newline bitfld.long 0x0 25. "OVRD_FSLS_DISC_TIME,Overriding the FS/LS disconnect time to 32us. - If this value is 0 the FS/LS disconnect time is set to 2.5us as per the USB specification. - If this value is non-0 the disconnect detection time is set to 32us. Normally this value.." "0,1" newline bitfld.long 0x0 22.--24. "LSTRD,LS Turnaround Time (LSTRDTIM) This field indicates the value of the Rx-to-Tx packet gap for LS devices. The encoding is as follows: - 0: 2 bit times - 1: 2.5 bit times - 2: 3 bit times - 3: 3.5 bit times - 4: 4 bit times - 5: 4.5 bit times - 6: 5.." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 19.--21. "LSIPD,LS Inter-Packet Time (LSIPD) This field indicates the value of Tx-to-Tx packet gap for LS devices. The encoding is as follows: - 0: 2 bit times - 1: 2.5 bit times - 2: 3 bit times - 3: 3.5 bit times - 4: 4 bit times - 5: 4.5 bit times - 6: 5 bit.." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 18. "ULPIEXTVBUSINDIACTOR,ULPI External VBUS Indicator (ULPIExtVbusIndicator) Indicates the ULPI PHY VBUS over-current indicator. - 1'b0: PHY uses an internal VBUS valid comparator. - 1'b1: PHY uses an external VBUS valid comparator. Valid only when RTL.." "PHY uses an internal VBUS valid comparator,PHY uses an external VBUS valid comparator" newline bitfld.long 0x0 17. "ULPIEXTVBUSDRV,ULPI External VBUS Drive (ULPIExtVbusDrv) Selects supply source to drive 5V on VBUS in the ULPI PHY. - 1'b0: PHY drives VBUS with internal charge pump (default). - 1'b1: PHY drives VBUS with an external supply. (Only when RTL parameter.." "PHY drives VBUS with internal charge pump,PHY drives VBUS with an external supply" newline rbitfld.long 0x0 16. "RESERVED_16,Reserved" "0,1" newline bitfld.long 0x0 15. "ULPIAUTORES,ULPI Auto Resume (ULPIAutoRes) Sets the AutoResume bit in Interface Control register on the ULPI PHY. - 1'b0: PHY does not use the AutoResume feature. - 1'b1: PHY uses the AutoResume feature. Valid only when RTL parameter.." "PHY does not use the AutoResume feature,PHY uses the AutoResume feature" newline rbitfld.long 0x0 14. "RESERVED_14,Reserved" "0,1" newline hexmask.long.byte 0x0 10.--13. 1. "USBTRDTIM,USB 2.0 Turnaround Time (USBTrdTim) Sets the turnaround time in PHY clocks. Specifies the response time for a MAC request to the Packet FIFO Controller (PFC) to fetch data from the DFIFO (SPRAM). The following are the required values for the.." newline bitfld.long 0x0 9. "XCVRDLY,Transceiver Delay: Enables a delay between the assertion of the UTMI/ULPI Transceiver Select signal (for HS) and the assertion of the TxValid signal during a HS Chirp. When this bit is set to 1 a delay (of approximately 2.5 us) is introduced.." "0,1" newline bitfld.long 0x0 8. "ENBLSLPM,Enable utmi_sleep_n and utmi_l1_suspend_n (EnblSlpM) The application uses this bit to control utmi_sleep_n and utmi_l1_suspend_n assertion to the PHY in the L1 state. - 1'b0: utmi_sleep_n and utmi_l1_suspend_n assertion from the controller is.." "utmi_sleep_n and utmi_l1_suspend_n assertion..,utmi_sleep_n and utmi_l1_suspend_n assertion.." newline bitfld.long 0x0 7. "PHYSEL,USB 2.0 High-Speed PHY or USB 1.1 Full-Speed Serial Transceiver Select The application uses this bit to select a high-speed PHY or a full-speed transceiver. - 1'b0: USB 2.0 high-speed UTMI+ or ULPI PHY. This bit is always 0 with Write Only.." "USB 2,USB 1" newline bitfld.long 0x0 6. "SUSPENDUSB20,Suspend USB2.0 HS/FS/LS PHY (SusPHY) When set USB2.0 PHY enters Suspend mode if Suspend conditions are valid. For DRD configurations it is recommended that this bit is set to 0 during coreConsultant configuration. If it is set to 1 then.." "0,1" newline rbitfld.long 0x0 5. "FSINTF,Full-Speed Serial Interface Select (FSIntf) The application uses this bit to select a unidirectional or bidirectional USB 1.1 full-speed serial transceiver interface. - 1'b0: 6-pin unidirectional full-speed serial interface. This bit is set to 0.." "0,1" newline rbitfld.long 0x0 4. "ULPI_UTMI_SEL,ULPI or UTMI+ Select (ULPI_UTMI_Sel) The application uses this bit to select a UTMI+ or ULPI Interface. - 1'b0: UTMI+ Interface - 1'b1: ULPI Interface This bit is writable only if UTMI+ and ULPI is specified for High-Speed PHY Interface(s).." "UTMI+ Interface,ULPI Interface" newline bitfld.long 0x0 3. "PHYIF,PHY Interface (PHYIf) If UTMI+ is selected the application uses this bit to configure the controller to support a UTMI+ PHY with an 8- or 16-bit interface. - 1'b0: 8 bits - 1'b1: 16 bits ULPI Mode: 1'b0 Note: - All the enabled 2.0 ports must have.." "0,1" newline bitfld.long 0x0 0.--2. "TOUTCAL,HS/FS Timeout Calibration (TOutCal) The number of PHY clocks as indicated by the application in this field is multiplied by a bit-time factor; this factor is added to the high-speed/full-speed interpacket timeout duration in the controller to.." "0,1,2,3,4,5,6,7" rgroup.long (0x140+0x49408)++0x3 line.long 0x0 "GUSB2I2CCTL,Reserved Register" hexmask.long 0x0 0.--31. 1. "RESERVED_31_0,Reserved for future use" group.long (0x180+0x49408)++0x3 line.long 0x0 "GUSB2PHYACC_ULPI,Global USB 2.0 ULPI PHY Vendor Control Register The application uses this register to access the PHY registers. This register is always implemented when the ULPI PHY Interface is enabled during coreConsultant configuration (parameter.." hexmask.long.byte 0x0 27.--31. 1. "RESERVED_31_27,Reserved" newline rbitfld.long 0x0 26. "DISUIPIDRVR,DISUIPIDRVR" "0,1" newline bitfld.long 0x0 25. "NEWREGREQ,New Register Request The application sets this bit for a new vendor control access. Setting this bit to 1 asserts the utmi_vcontrolload_n (1'b0) on the UTMI interface." "0,1" newline rbitfld.long 0x0 24. "VSTSDONE,VSTSDONE" "0,1" newline bitfld.long 0x0 23. "VSTSBSY,VSTSBSY" "0,1" newline bitfld.long 0x0 22. "REGWR,Register Write The application sets this bit for register writes and clears it for register reads. Note: This bit is applicable for ULPI register read/write access only." "0,1" newline hexmask.long.byte 0x0 16.--21. 1. "REGADDR,Register Address The 6-bit PHY register address for immediate PHY Register Set access. Set to 6'h2F for Extended PHY Register Set access. Note: These bits are applicable for ULPI only." newline hexmask.long.byte 0x0 8.--15. 1. "EXTREGADDR,EXTREGADDR" newline hexmask.long.byte 0x0 0.--7. 1. "REGDATA,REGDATA" group.long (0x1C0+0x49408)++0x3 line.long 0x0 "GUSB3PIPECTL,Global USB 3.0 PIPE Control Register The application uses this register to configure the USB3 PHY and PIPE interface. Device-only configuration requires only one register. In Host mode. registers are implemented for each port. For more.." bitfld.long 0x0 31. "PHYSOFTRST,USB3 PHY Soft Reset After setting this bit to '1' the software needs to clear this bit. For more information refer to Figure 'Software Resets and PHY Clock Sequencing and Requirements' in the Databook." "0,1" newline bitfld.long 0x0 30. "HSTPRTCMPL,HstPrtCmpl This feature tests the PIPE PHY compliance patterns without having to have a test fixture on the USB 3.0 cable. This bit enables placing the SS port link into a compliance state. By default this bit must be set to 1'b0. In.." "0,1" newline bitfld.long 0x0 29. "U2P3OK,P3 OK for SSInactive (SSIP3ok) - 0: During link state SS.Inactive put PHY in P2 (Default) - 1: During link state SS.Inactive put PHY in P3." "During link state SS,During link state SS" newline bitfld.long 0x0 28. "DISRXDETP3,Disabled receiver detection in P3 (DisRxDetP3) - 0: If PHY is in P3 and controller needs to perform receiver detection The controller performs receiver detection in P3. (Default) - 1: If PHY is in P3 and controller needs to perform receiver.." "If PHY is in P3 and controller needs to perform..,If PHY is in P3 and controller needs to perform.." newline bitfld.long 0x0 27. "UX_EXIT_IN_PX,Ux Exit in Px (Ux_exit_in_Px) - 0: The controller does U1/U2/U3 exit in PHY power state P0 (default behavior). - 1: The controller does U1/U2/U3 exit in PHY power state P1/P2/P3 respectively. Note: This bit is used by third-party SS PHY. It.." "The controller does U1/U2/U3 exit in PHY power..,The controller does U1/U2/U3 exit in PHY power.." newline bitfld.long 0x0 26. "PING_ENHANCEMENT_EN,Ping Enhancement Enable (ping_enhancement_en) When set the Downstream port U1 ping receive timeout becomes 500 ms instead of 300 ms. Minimum Ping.LFPS receive duration is 8 ns (one mac3_clk). This field is valid for the downstream.." "0,1" newline bitfld.long 0x0 25. "U1U2EXITFAIL_TO_RECOV,U1U2exitfail to Recovery (u1u2exitfail_to_recov) When set and U1/U2 LFPS handshake fails the LTSSM transitions from U1/U2 to Recovery instead of SS Inactive. If Recovery fails then the LTSSM can enter SS.Inactive. This is an.." "0,1" newline bitfld.long 0x0 24. "REQUEST_P1P2P3,Always Request P1/P2/P3 for U1/U2/U3 (request_p1p2p3) When set the controller always requests PHY power change from P0 to P1/P2/P3 during U0 to U1/U2/U3 transition. If this bit is 0 and immediate Ux exit (remotely initiated or locally.." "0,1" newline bitfld.long 0x0 23. "STARTRXDETU3RXDET,Start Receiver Detection in U3/Rx.Detect (StartRxdetU3RxDet) If DWC_USB3_GUSB3PIPECTL_INIT[22] is set and the link is in either U3 or Rx.Detect state the controller starts receiver detection on the rising edge of this bit. This can.." "0,1" newline bitfld.long 0x0 22. "DISRXDETU3RXDET,Disable Receiver Detection in U3/Rx.Det When set the controller does not handle receiver detection in either U3 or Rx.Detect states. DWC_USB3_GUSB3PIPECTL_INIT[23] must be used to start receiver detection manually. This bit can only be.." "0,1" newline bitfld.long 0x0 19.--21. "DELAYP1P2P3,Delay P1P2P3 Delay P0 to P1/P2/P3 request when entering U1/U2/U3 until (DWC_USB3_GUSB3PIPECTL_INIT[21:19]*8) 8B10B error occurs or Pipe3_RxValid drops to 0. DWC_USB3_GUSB3PIPECTL_INIT[18] must be 1 to enable this functionality." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 18. "DELAYP1TRANS,Delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. - 1'b1: When entering U1/U2/U3 delay the transition to P1/P2/P3 until the pipe3 signals Pipe3_RxElecIdle is 1 and pipe3_RxValid is 0 -.." "When entering U1/U2/U3,When entering U1/U2/U3" newline bitfld.long 0x0 17. "SUSPENDENABLE,Suspend USB3.0 SS PHY (Suspend_en) When set and if Suspend conditions are valid the USB 3.0 PHY enters Suspend mode. For DRD configurations it is recommended that this bit is set to '0' during coreConsultant configuration. If it is set.." "0,1" newline rbitfld.long 0x0 15.--16. "DATWIDTH,PIPE Data Width (DatWidth) - 2'b00: 32 bits - 2'b01: 16 bits One clock after reset these bits receive the value seen on the pipe3_DataBusWidth. The simulation testbench uses the coreConsultant parameter to configure the VIP. These bits in the.." "0,1,2,3" newline bitfld.long 0x0 14. "ABORTRXDETINU2,Abort Rx Detect in U2 (AbortRxDetInU2) When set and the link state is U2 the controller will abort receiver detection if it receives U2 exit LFPS from the remote link partner. This bit is for the downstream port only. Note: This bit is.." "0,1" newline bitfld.long 0x0 13. "SKIPRXDET,Skip Rx Detect: When set the controller skips Rx Detection if pipe3_RxElecIdle is low. Skip is defined as waiting for the appropriate timeout then repeating the operation." "0,1" newline bitfld.long 0x0 12. "LFPSP0ALGN,LFPS P0 Align: When set - The controller deasserts LFPS transmission on the clock edge that it requests Phy power state 0 when exiting U1 U2 or U3 low power states. Otherwise LFPS transmission is asserted one clock earlier. - The.." "0,1" newline bitfld.long 0x0 11. "P3P2TRANOK,P3 P2 Transitions OK (P3P2TranOK) When set the controller transitions directly from Phy power state P2 to P3 or from state P3 to P2. When not set P0 is always entered as an intermediate state during transitions between P2 and P3 as defined.." "0,1" newline bitfld.long 0x0 10. "P3EXSIGP2,P3 Exit Signal in P2 (P3ExSigP2) When this bit is set the controller always changes the PHY power state to P2 before attempting a U3 exit handshake. This bit is used only for some non-Synopsys PHYs that cannot do LFPS in P3. Note: This bit is.." "0,1" newline bitfld.long 0x0 9. "LFPSFILTER,LFPS Filter (LFPSFilt) When set filter LFPS reception with pipe3_RxValid in PHY power state P0 that is ignore LFPS reception from the PHY unless both pipe3_Rxelecidle and pipe3_RxValid are deasserted." "0,1" newline bitfld.long 0x0 8. "RX_DETECT_TO_POLLING_LFPS_CONTROL,RX_DETECT to Polling.LFPS Control - 1'b0 (Default): Enables a 400us delay to start Polling LFPS after RX_DETECT. This allows VCM offset to settle to a proper level. - 1'b1: Disables the 400us delay to start Polling LFPS.." "?,Disables the 400us delay to start Polling LFPS.." newline bitfld.long 0x0 7. "SSICEN,This field is not used." "0,1" newline bitfld.long 0x0 6. "TX_SWING,Tx Swing (TxSwing) Refer to the PIPE3 specification." "0,1" newline bitfld.long 0x0 3.--5. "TX_MARGIN,Tx Margin[2:0] (TxMargin) Refer to Table 5-3 of the PIPE3 Specification." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 1.--2. "SS_TX_DE_EMPHASIS,Tx Deemphasis (TxDeemphasis) The value driven to the PHY is controlled by the LTSSM during USB3 Compliance mode. (Refer to Table 5-3 of the PIPE3 specification.)" "0,1,2,3" newline bitfld.long 0x0 0. "ELASTIC_BUFFER_MODE,Elastic Buffer Mode (ElasticBufferMode) (Refer to Table 5-3 of the PIPE3 specification.)" "0,1" group.long (0x200+0x49408)++0x3 line.long 0x0 "GTXFIFOSIZ0,Global Transmit FIFO Size Register This register specifies the RAM start address and depth (both in MDWIDTH-bit words) for each implemented TxFIFO. The number of TxFIFOs depends on the configuration parameters including the number of Device.." hexmask.long.word 0x0 16.--31. 1. "TXFSTADDR_N,Transmit FIFOn RAM Start Address This field contains the memory start address for TxFIFOn in MDWIDTH-bit words." newline hexmask.long.word 0x0 0.--15. 1. "TXFDEP_N,TxFIFO Depth This field contains the depth of TxFIFOn in MDWIDTH-bit words. - Minimum value: 32 - Maximum value: 32 768 For more information see 'Integrating the Controller' chapter in the User Guide." repeat 6. (list 0x1 0x3 0x4 0x5 0x6 0x7 )(list 0x0 0x8 0xC 0x10 0x14 0x18 ) group.long ($2+0x204+0x49408)++0x3 line.long 0x0 "GTXFIFOSIZ$1,Register GTXFIFOSIZ 1" hexmask.long.word 0x0 16.--31. 1. "TXFSTADDR_N,Transmit FIFOn RAM Start Address This field contains the memory start address for TxFIFOn in MDWIDTH-bit words." newline hexmask.long.word 0x0 0.--15. 1. "TXFDEP_N,TXFDEP_N" repeat.end group.long (0x208+0x49408)++0x3 line.long 0x0 "GTXFIFOSIZ2,Transmit FIFOn RAM Start Address This field contains the memory start address for TxFIFOn in MDWIDTH-bit words." hexmask.long.word 0x0 16.--31. 1. "TXFSTADDR_N,Transmit FIFOn RAM Start Address This field contains the memory start address for TxFIFOn in MDWIDTH-bit words." newline hexmask.long.word 0x0 0.--15. 1. "TXFDEP_N,TxFIFO Depth This field contains the depth of TxFIFOn in MDWIDTH-bit words. - Minimum value: 32 - Maximum value: 32 768 For more information see 'Integrating the Controller' chapter in the User Guide." group.long (0x280+0x49408)++0x3 line.long 0x0 "GRXFIFOSIZ0,Global Receive FIFO Size Register This register specifies the RAM start address and depth (both in MDWIDTH-bit words) for each implemented RxFIFO. The number of RxFIFOs depends on the configuration parameters including the number of Host Bus.." hexmask.long.word 0x0 16.--31. 1. "RXFSTADDR_N,RxFIFOn RAM Start Address (RxFStAddr_n) This field contains the memory start address for RxFIFOn in MDWIDTH-bit words." newline hexmask.long.word 0x0 0.--15. 1. "RXFDEP_N,RxFIFO Depth (RxFDep_n) This field contains the depth of RxFIFOn in MDWIDTH-bit words. - Minimum value: 32 - Maximum value: 16 384" repeat 2. (list 0x1 0x2 )(list 0x0 0x4 ) group.long ($2+0x284+0x49408)++0x3 line.long 0x0 "GRXFIFOSIZ$1,Register" hexmask.long.word 0x0 16.--31. 1. "RXFSTADDR_N,RXFSTADDR_N" newline hexmask.long.word 0x0 0.--15. 1. "RXFDEP_N,RxFIFO Depth This field contains the depth of RxFIFOn in MDWIDTH-bit words. - Minimum value: 32 - Maximum value: 16 384" repeat.end group.long (0x300+0x49408)++0xF line.long 0x0 "GEVNTADRLO,Global Event Buffer Address (Low) Register This is an alternate register for the GEVNTADRn register." hexmask.long 0x0 0.--31. 1. "EVNTADRLO,Event Buffer Address (EvntAdrLo) Holds the lower 32 bits of start address of the external memory for the Event Buffer. During operation hardware does not update this address." line.long 0x4 "GEVNTADRHI,Global Event Buffer Address (High) Register This is an alternate register for the GEVNTADRn register." hexmask.long 0x4 0.--31. 1. "EVNTADRHI,Event Buffer Address (EvntAdrHi) Holds the higher 32 bits of start address of the external memory for the Event Buffer. During operation hardware does not update this address." line.long 0x8 "GEVNTSIZ,Global Event Buffer Size Register This register holds the Event Buffer Size and the Event Interrupt Mask bit. During power-on initialization. software must initialize the size with the number of bytes allocated for the Event Buffer. The Event.." bitfld.long 0x8 31. "EVNTINTRPTMASK,Event Interrupt Mask (EvntIntMask). When set to '1' this prevents the interrupt from being generated. However even when the mask is set the events are queued." "0,1" newline hexmask.long.word 0x8 16.--30. 1. "RESERVED_30_16,Reserved" newline hexmask.long.word 0x8 0.--15. 1. "EVENTSIZ,Event Buffer Size in bytes (EVNTSiz) Holds the size of the Event Buffer in bytes; must be a multiple of four. This is programmed by software once during initialization. The minimum size of the event buffer is 32 bytes." line.long 0xC "GEVNTCOUNT,Global Event Buffer Count Register This register holds the number of valid bytes in the Event Buffer. During initialization. software must initialize the count by writing 0 to the Event Count field. Each time the hardware writes a new event to.." bitfld.long 0xC 31. "EVNT_HANDLER_BUSY,Event Handler Busy Device software event handler busy indication. The controller sets this bit when the interrupt line is asserted due to pending events. Software clears this bit (with 1'b1) when it has finished processing the events.." "0,1" newline hexmask.long.word 0xC 16.--30. 1. "RESERVED_30_16,Reserved" newline hexmask.long.word 0xC 0.--15. 1. "EVNTCOUNT,Event Count (EVNTCount) When read returns the number of valid events in the Event Buffer (in bytes). When written hardware decrements the count by the value written. When Interrupt moderation is enabled (that is DEVICE_IMODI!= 0) the.." group.long (0x50C+0x49408)++0x7 line.long 0x0 "GUCTL3,Global User Control Register 3 This register provides a few options for the software to control the controller behavior in the Host mode. Most of the options are used to improve host inter-operability with different devices." hexmask.long.word 0x0 17.--31. 1. "RESERVED_31_17,Reserved" newline bitfld.long 0x0 16. "SCH_PING_EARLY,Enable SuperSpeed Ping Transaction Packet scheduling early in the microframe. This bit is valid in Host mode only." "0,1" newline hexmask.long.word 0x0 0.--15. 1. "RESERVED_15_0,Reserved" line.long 0x4 "GTXFIFOPRIDEV,Global Device TX FIFO DMA Priority Register This register specifies the relative DMA priority level among the Device TXFIFOs (one per IN endpoint). Each register bit[n] controls the priority (1: high. 0: low) of each TXFIFO[n]. When.." hexmask.long.tbyte 0x4 8.--31. 1. "RESERVED_31_N,Reserved" newline hexmask.long.byte 0x4 0.--7. 1. "GTXFIFOPRIDEV,Device TxFIFO priority" group.long (0x518+0x49408)++0xF line.long 0x0 "GTXFIFOPRIHST,Global Host TX FIFO DMA Priority Register This register specifies the relative DMA priority level among the Host TXFIFOs (one per USB bus instance) within the associated speed group (SS or HS/FSLS). Each register bit[n] controls the.." hexmask.long 0x0 4.--31. 1. "RESERVED_31_16,Reserved" newline hexmask.long.byte 0x0 0.--3. 1. "GTXFIFOPRIHST,Host TxFIFO priority" line.long 0x4 "GRXFIFOPRIHST,Global Host RX FIFO DMA Priority Register This register specifies the relative DMA priority level among the Host RXFIFOs (one per USB bus instance) within the associated speed group (SS or HS/FSLS). Each register bit[n] controls the.." hexmask.long 0x4 3.--31. 1. "RESERVED_31_16,Reserved" newline bitfld.long 0x4 0.--2. "GRXFIFOPRIHST,Host RxFIFO priority" "0,1,2,3,4,5,6,7" line.long 0x8 "GFIFOPRIDBC,Global Host Debug Capability DMA Priority Register This register specifies the relative priority of the RXFIFOs and TXFIFOs associated with the DbC mode. It overrides the priority assigned in the corresponding indexes of the Host RXFIFO and.." hexmask.long 0x8 2.--31. 1. "RESERVED_31_2,Reserved" newline bitfld.long 0x8 0.--1. "GFIFOPRIDBC,Host DbC DMA priority" "0,1,2,3" line.long 0xC "GDMAHLRATIO,Global Host FIFO DMA High-Low Priority Ratio Register This register specifies the relative priority of the SS FIFOs with respect to the HS/FSLS FIFOs. The DMA arbiter prioritizes the HS/FSLS round-robin arbiter group every DMA High-Low.." hexmask.long.tbyte 0xC 13.--31. 1. "RESERVED_31_13,Reserved" newline hexmask.long.byte 0xC 8.--12. 1. "HSTRXFIFO,Host RXFIFO DMA High-Low Priority" newline rbitfld.long 0xC 5.--7. "RESERVED_7_5,Reserved" "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0xC 0.--4. 1. "HSTTXFIFO,Host TXFIFO DMA High-Low Priority" group.long (0x530+0x49408)++0x3 line.long 0x0 "GFLADJ,Global Frame Length Adjustment Register This register provides options for the software to control the controller behavior with respect to SOF (Start of Frame) and ITP (Isochronous Timestamp Packet) timers and frame timer functionality. It.." bitfld.long 0x0 31. "GFLADJ_REFCLK_240MHZDECR_PLS1,GFLADJ_REFCLK_240MHZDECR_PLS1 This field indicates that the decrement value that the controller applies for each ref_clk must be GFLADJ_REFCLK_240MHZ_DECR and GFLADJ_REFCLK_240MHZ_DECR +1 alternatively on each ref_clk. Set.." "0,1" newline hexmask.long.byte 0x0 24.--30. 1. "GFLADJ_REFCLK_240MHZ_DECR,This field indicates the decrement value that the controller applies for each ref_clk in order to derive a frame timer in terms of a 240-MHz clock. This field must be programmed to a non-zero value only if GFLADJ_REFCLK_LPM_SEL.." newline bitfld.long 0x0 23. "GFLADJ_REFCLK_LPM_SEL,This bit enables the functionality of running SOF/ITP counters on the ref_clk. This bit must not be set to '1' if GCTL.SOFITPSYNC bit is set to '1'. Similarly if GFLADJ_REFCLK_LPM_SEL set to '1' GCTL.SOFITPSYNC must not be set to.." "0,1" newline rbitfld.long 0x0 22. "RESERVED_22,Reserved for future use" "0,1" newline hexmask.long.word 0x0 8.--21. 1. "GFLADJ_REFCLK_FLADJ,This field indicates the frame length adjustment to be applied when SOF/ITP counter is running on the ref_clk. This register value is used to adjust the ITP interval when GCTL[SOFITPSYNC] is set to '1'; SOF and ITP interval when.." newline bitfld.long 0x0 7. "GFLADJ_30MHZ_SDBND_SEL,GFLADJ_30MHZ_SDBND_SEL This field selects whether to use the input signal fladj_30mhz_reg or the GFLADJ.GFLADJ_30MHZ to adjust the frame length for the SOF/ITP. When this bit is set to - 1 the controller uses the register field.." "0,1" newline rbitfld.long 0x0 6. "RESERVED_6,Reserved for future use" "0,1" newline hexmask.long.byte 0x0 0.--5. 1. "GFLADJ_30MHZ,GFLADJ_30MHZ This field indicates the value that is used for frame length adjustment instead of considering from the sideband input signal fladj_30mhz_reg. This enables post-silicon frame length adjustment in case the input signal.." group.long (0x540+0x49408)++0x3 line.long 0x0 "GUSB2RHBCTL,Global USB 2.0 Root Hub Control Register The application must program this register before starting any transactions on the USB if a non-default value is desired. In Host mode. per-port registers are implemented." hexmask.long 0x0 4.--31. 1. "RESERVED_31_4,Reserved" newline hexmask.long.byte 0x0 0.--3. 1. "OVRD_L1TIMEOUT,Overriding the driver programmed L1TIMEOUT value. If this value is 0 the L1 Timeout value is taken from the xHCI PORTHLPMC register. If this value is non-0 then this will override the L1 Timeout value programmed in the xHCI PORTHLPMC.." tree.end tree "DWC_usb3_block_ecc (USB 3.0 ECC Register Block)" rgroup.long (0x850+0x53248)++0xB line.long 0x0 "BRSERRCNT,Block RAM Single Bit Error Count. 8 bit count for each of the 3 RAMs." hexmask.long.byte 0x0 24.--31. 1. "RESERVED_31_24,Reserved" hexmask.long.byte 0x0 16.--23. 1. "RAM2SERRCNT,RAM2 Single bit Error Count" hexmask.long.byte 0x0 8.--15. 1. "RAM1SERRCNT,RAM1 Single bit Error Count" hexmask.long.byte 0x0 0.--7. 1. "RAM0SERRCNT,RAM0 Single bit Error Count" line.long 0x4 "BRMERRCNT,Block RAM Multiple Bit Error Count. 8 bit count for each of the 3 RAMs." hexmask.long.byte 0x4 24.--31. 1. "RESERVED_31_24,Reserved" hexmask.long.byte 0x4 16.--23. 1. "RAM2MERRCNT,RAM2 Multiple bit Error Count" hexmask.long.byte 0x4 8.--15. 1. "RAM1MERRCNT,RAM1 Multiple bit Error Count" hexmask.long.byte 0x4 0.--7. 1. "RAM0MERRCNT,RAM0 Multiple bit Error Count" line.long 0x8 "BRMECCERR,Block RAM ECC Error Vector Register" hexmask.long.tbyte 0x8 8.--31. 1. "RESERVED_31_8,Reserved" bitfld.long 0x8 7. "RAMSERR,RAM Single bit Error Status" "0,1" bitfld.long 0x8 6. "RAMMERR,RAM Multiple bit Error Status" "0,1" bitfld.long 0x8 3.--5. "RAMSERRVEC,RAM Single Error Vector" "0,1,2,3,4,5,6,7" bitfld.long 0x8 0.--2. "RAMMERRVEC,RAM Multiple Error Vector" "0,1,2,3,4,5,6,7" group.long (0x85C+0x53248)++0x3 line.long 0x0 "BRERRCTL,Block RAM ECC Error Control Register" hexmask.long 0x0 4.--31. 1. "RESERVED_31_4,Reserved" bitfld.long 0x0 3. "ECCERRINJECT,This bit should be used for testing purposes only. - 1: Inject ECC error - 0: No ECC error injected" "No ECC error injected,Inject ECC error" bitfld.long 0x0 2. "ECCEN,ECC Enable (1) or Disable (0)" "0,1" bitfld.long 0x0 1. "RSERRCLR,RAM Single bit Error Clear" "0,1" bitfld.long 0x0 0. "RMERRCLR,RAM Multiple bit Error Clear" "0,1" rgroup.long (0x860+0x53248)++0xB line.long 0x0 "BRAM0ADDRERR,Block RAM Address of RAM0 having uncorrectable error" hexmask.long.word 0x0 16.--31. 1. "RESERVED_31_16,Reserved" hexmask.long.word 0x0 0.--15. 1. "RAM0ADDRLOC,RAM0 Address Location" line.long 0x4 "BRAM1ADDRERR,Block RAM Address of RAM1 having uncorrectable error" hexmask.long.word 0x4 16.--31. 1. "RESERVED_31_16,Reserved" hexmask.long.word 0x4 0.--15. 1. "RAM1ADDRLOC,RAM1 Address Location" line.long 0x8 "BRAM2ADDRERR,Block RAM Address of RAM2 having uncorrectable error" hexmask.long.word 0x8 16.--31. 1. "RESERVED_31_16,Reserved" hexmask.long.word 0x8 0.--15. 1. "RAM2ADDRLOC,RAM1 Address Location" tree.end tree "DWC_usb3_block_dev (USB 3.0 Device Register Block)" group.long (0x0+0x50944)++0x17 line.long 0x0 "DCFG,Device Configuration Register. This register configures the controller in Device mode after power-on or after certain control commands or enumeration. Do not make changes to this register after initial programming." hexmask.long.byte 0x0 25.--31. 1. "RESERVED_31_25,Reserved" rbitfld.long 0x0 24. "RESERVED_24,reserved" "0,1" newline bitfld.long 0x0 23. "IGNSTRMPP,IgnoreStreamPP This bit only affects stream-capable bulk endpoints. When this bit is set to '0' and the controller receives a Data Packet with the Packet Pending (PP) bit set to 0 for OUT endpoints or it receives an ACK with the NumP field set.." "0,1" bitfld.long 0x0 22. "LPMCAP,LPM Capable The application uses this bit to control the LPM capabilities of the DWC_usb3 controller. If the controller operates as a non-LPM-capable device it cannot respond to LPM transactions. - 1'b0: LPM capability is not enabled. - 1'b1: LPM.." "LPM capability is not enabled,LPM capability is enabled" newline hexmask.long.byte 0x0 17.--21. 1. "NUMP,Number of Receive Buffers. This bit indicates the number of receive buffers to be reported in the ACK TP. The DWC_usb3 controller uses this field for non-control endpoints if GRXTHRCFG.UsbRxPktCntSel is set to '0'. The application can program this.." hexmask.long.byte 0x0 12.--16. 1. "INTRNUM,Interrupt number Indicates interrupt/EventQ number on which non-endpoint-specific device-related interrupts (see DEVT) are generated." newline rbitfld.long 0x0 10.--11. "RESERVED_10_11,Reserved" "0,1,2,3" hexmask.long.byte 0x0 3.--9. 1. "DEVADDR,Device Address. The application must perform the following: - Program this field after every SetAddress request. - Reset this field to zero after USB reset." newline bitfld.long 0x0 0.--2. "DEVSPD,Device Speed. Indicates the speed at which the application requires the controller to connect or the maximum speed the application can support. However the actual bus speed is determined only after the chirp sequence is completed and is based.." "High-speed,Full-speed,?,?,SuperSpeed,?,?,?" line.long 0x4 "DCTL,Device Control Register Note: When Hibernation is not enabled using GCTL.GblHibernationEn field. - you can write any value to CSS. CRS. L1HibernationEn. and KeepConnect fields - L1HibernationEn. and KeepConnect fields always return 0 when read in.." bitfld.long 0x4 31. "RUN_STOP,Run/Stop The software writes 1 to this bit to start the device controller operation. To stop the device controller operation the software must remove any active transfers and write 0 to this bit. When the controller is stopped it sets the.." "0,1" bitfld.long 0x4 30. "CSFTRST,Core Soft Reset Resets the all clock domains as follows: - This bit clears the interrupts and all the CSRs except GSTS GSNPSID GGPIO GUID GUSB2PHYCFGn registers GUSB3PIPECTLn registers DCFG DCTL DEVTEN and DSTS registers. - All module.." "0,1" newline rbitfld.long 0x4 29. "RESERVED_29,Reserved1" "0,1" hexmask.long.byte 0x4 24.--28. 1. "HIRDTHRES,HIRD Threshold (HIRD_Thres) The controller asserts output signals utmi_l1_suspend_n and utmi_sleep_n (see 'LPM Interface Signals' table in the Databook) on the basis of this signal: The controller asserts utmi_l1_suspend_n to put the PHY into.." newline hexmask.long.byte 0x4 20.--23. 1. "LPM_NYET_THRES,LPM NYET Threshold When LPM Errata is enabled: Bits [23:20]: LPM NYET Response Threshold (LPM_NYET_thres) Handshake response to LPM token specified by device application. Response depends on DCFG.LPMCap. - DCFG.LPMCap is 1'b0 - The.." bitfld.long 0x4 19. "KEEPCONNECT,Keep Connect When '1' this bit enables the save and restore programming model by preventing the controller from disconnecting from the host when DCTL.RunStop is set to '0'. It also enables the Hibernation Request Event to be generated when.." "0,1" newline bitfld.long 0x4 18. "L1HIBERNATIONEN,L1HibernationEn When this bit is set along with KeepConnect the device controller generates a Hibernation Request Event if L1 is enabled and the HIRD value in the LPM token is larger than the threshold programmed in DCTL.HIRD_Thres. The.." "0,1" bitfld.long 0x4 17. "CRS,Controller Restore State (CRS) This command is similar to the USBCMD.CRS bit in host mode and initiates the restore process. When software sets this bit to '1' the controller immediately sets DSTS.RSS to '1'. When the controller has finished the.." "0,1" newline bitfld.long 0x4 16. "CSS,Controller Save State (CSS) This command is similar to the USBCMD.CSS bit in host mode and initiates the save process. When software sets this bit to '1' the controller immediately sets DSTS.SSS to '1'. When the controller has finished the save.." "0,1" rbitfld.long 0x4 13.--15. "RESERVED_15_13,Reserved" "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 12. "INITU2ENA,Initiate U2 Enable - 1'b0: May not initiate U2 (default) - 1'b1: May initiate U2 On USB reset hardware clears this bit to 0. Software sets this bit after receiving SetFeature(U2_ENABLE) and clears this bit when ClearFeature(U2_ENABLE) is.." "May not initiate U2,May initiate U2" bitfld.long 0x4 11. "ACCEPTU2ENA,Accept U2 Enable - 1'b0: Reject U2 except when Force_LinkPM_Accept bit is set (default) - 1'b1: Controller accepts transition to U2 state if nothing is pending on the application side. On USB reset hardware clears this bit to 0. Software.." "Reject U2 except when Force_LinkPM_Accept bit is..,Controller accepts transition to U2 state if.." newline bitfld.long 0x4 10. "INITU1ENA,Initiate U1 Enable - 1'b0: May not initiate U1 (default); - 1'b1: May initiate U1. On USB reset hardware clears this bit to 0. Software sets this bit after receiving SetFeature(U1_ENABLE) and clears this bit when ClearFeature(U1_ENABLE) is.." "May not initiate U1,May initiate U1" bitfld.long 0x4 9. "ACCEPTU1ENA,Accept U1 Enable - 1'b0: Controller rejects U1 except when Force_LinkPM_Accept bit is set (default) - 1'b1: Controller accepts transition to U1 state if nothing is pending on the application side. On USB reset hardware clears this bit to 0." "Controller rejects U1 except when..,Controller accepts transition to U1 state if.." newline hexmask.long.byte 0x4 5.--8. 1. "ULSTCHNGREQ,ULSTCHNGREQ Software writes this field to issue a USB/Link state change request. A change in this field indicates a new request to the controller. If software wants to issue the same request back-to-back it must write a 0 to this field.." hexmask.long.byte 0x4 1.--4. 1. "TSTCTL,Test Control - 4'b000: Test mode disabled - 4'b001: Test_J mode - 4'b010: Test_K mode - 4'b011: Test_SE0_NAK mode - 4'b100: Test_Packet mode - 4'b101: Test_Force_Enable - Others: Reserved" newline rbitfld.long 0x4 0. "RESERVED_0,Reserved" "0,1" line.long 0x8 "DEVTEN,Device Event Enable Register This register controls the generation of device-specific events (see 'Event Buffer Content for Device-Specific Events (DEVT)' section). If an enable bit is set to 0. the event will not be generated." hexmask.long.word 0x8 17.--31. 1. "RESERVED_31_17,Reserved" bitfld.long 0x8 16. "ECCERREN,ECC Error Enable. If this bit is set to 1 the controller reports an ECC error to the software when an uncorrectable ECC occurs internally." "0,1" newline rbitfld.long 0x8 15. "RESERVED_15,Reserved" "0,1" bitfld.long 0x8 14. "L1WKUPEVTEN,L1 Resume Detected Event Enable. Note: If GUCTL1[DEV_DECOUPLE_L1L2_EVT] is enabled then this bit is for L1 Resume Detected Event Enable." "0,1" newline bitfld.long 0x8 12. "VENDEVTSTRCVDEN,Vendor Device Test LMP Received Event (VndrDevTstRcvedEn)" "0,1" rbitfld.long 0x8 11. "RESERVED_11,Reserved" "0,1" newline rbitfld.long 0x8 10. "RESERVED_10,Reserved" "0,1" bitfld.long 0x8 9. "ERRTICERREVTEN,Erratic Error Event Enable" "0,1" newline bitfld.long 0x8 8. "L1SUSPEN,L1 Suspend Event Enable Note: Only if GUCTL1[DEV_DECOUPLE_L1L2_EVT] is enabled this bit is for L1 Suspend Event Enable." "0,1" bitfld.long 0x8 7. "SOFTEVTEN,Start of (u)frame" "0,1" newline bitfld.long 0x8 6. "U3L2L1SUSPEN,U3/L2 or U3/L2L1 Suspend Event Enable. Note: - If GUCTL1[DEV_DECOUPLE_L1L2_EVT] is enabled then this bit is for U3/L2 Suspend Event Enable. - If GUCTL1[DEV_DECOUPLE_L1L2_EVT] is not enabled then this bit is for U3/L2L1 Suspend Event Enable." "0,1" bitfld.long 0x8 5. "HIBERNATIONREQEVTEN,This bit enables/disables the generation of the Hibernation Request Event." "0,1" newline bitfld.long 0x8 4. "WKUPEVTEN,U3/L2 or U3/L2L1 Resume Detected Event Enable. Note: - If GUCTL1[DEV_DECOUPLE_L1L2_EVT] is enabled then this bit is for U3/L2 Resume Detected Event Enable. - If GUCTL1[DEV_DECOUPLE_L1L2_EVT] is not enabled then this bit is for U3/L2L1 Resume.." "0,1" bitfld.long 0x8 3. "ULSTCNGEN,USB/Link State Change Event Enable" "0,1" newline bitfld.long 0x8 2. "CONNECTDONEEVTEN,Connection Done Enable" "0,1" bitfld.long 0x8 1. "USBRSTEVTEN,USB Reset Enable" "0,1" newline bitfld.long 0x8 0. "DISSCONNEVTEN,Disconnect Detected Event Enable" "0,1" line.long 0xC "DSTS,Device Status Register This register indicates the status of the device controller with respect to USB-related events. Note: When Hibernation is not enabled. RSS and SSS fields always return 0 when read." rbitfld.long 0xC 30.--31. "RESERVED_31_30,Reserved" "0,1,2,3" rbitfld.long 0xC 29. "DCNRD,Device Controller Not Ready The bit indicates that the controller is in the process of completing the state transitions after exiting from hibernation. To complete the state transitions it takes 256 bus clock cycles from the time DCTL[31].Run/Stop.." "0,1" newline bitfld.long 0xC 28. "SRE,Save Restore Error. Currently not supported." "0,1" rbitfld.long 0xC 26.--27. "RESERVED_27_26,Reserved" "0,1,2,3" newline rbitfld.long 0xC 25. "RSS,RSS Restore State Status This bit is similar to the USBSTS.RSS in host mode. When the controller finishes the restore process it completes the command by setting DSTS.RSS to '0'." "0,1" rbitfld.long 0xC 24. "SSS,SSS Save State Status This bit is similar to the USBSTS.SSS in host mode. When the controller has finished the save process it completes the command by setting DSTS.SSS to '0'." "0,1" newline rbitfld.long 0xC 23. "COREIDLE,Core Idle The bit indicates that the controller finished transferring all RxFIFO data to system memory writing out all completed descriptors and all Event Counts are zero. Note: While testing for Reset values mask out the read value. This bit.." "0,1" rbitfld.long 0xC 22. "DEVCTRLHLT,Device Controller Halted This bit is set to 0 when the Run/Stop bit in the DCTL register is set to 1. The controller sets this bit to 1 when after SW sets Run/Stop to 0 the controller is idle and the lower layer finishes the disconnect.." "0,1" newline hexmask.long.byte 0xC 18.--21. 1. "USBLNKST,USBLNKST. USB/Link State In SS mode: LTSSM State - 4'h0: U0 - 4'h1: U1 - 4'h2: U2 - 4'h3: U3 - 4'h4: SS_DIS - 4'h5: RX_DET - 4'h6: SS_INACT - 4'h7: POLL - 4'h8: RECOV - 4'h9: HRESET - 4'ha: CMPLY - 4'hb: LPBK - 4'hf: Resume/Reset In HS/FS/LS.." rbitfld.long 0xC 17. "RXFIFOEMPTY,RxFIFO Empty." "0,1" newline hexmask.long.word 0xC 3.--16. 1. "SOFFN,Frame/Microframe Number of the Received SOF. When the controller is operating at SuperSpeed - [16:3] indicates the uframe/ITP number When the controller is operating at high-speed - [16:6] indicates the frame number - [5:3] indicates the.." rbitfld.long 0xC 0.--2. "CONNECTSPD,Connected Speed (ConnectSpd) Indicates the speed at which the DWC_usb3 controller has come up after speed detection through a chirp sequence. - 3'b100: SuperSpeed (PHY clock is running at 125 or 250 MHz) - 3'b000: High-speed (PHY clock is.." "High-speed,Full-speed,?,?,SuperSpeed,?,?,?" line.long 0x10 "DGCMDPAR,Device Generic Command Parameter Register This register indicates the device command parameter. This must be programmed before or along with the device command. The available device commands are listed in DGCMD register." hexmask.long 0x10 0.--31. 1. "PARAMETER,PARAMETER" line.long 0x14 "DGCMD,Device Generic Command Register This register enables software to program the controller using a single generic command interface to send link management packets and notifications. This register contains command. control. and status fields relevant.." hexmask.long.word 0x14 16.--31. 1. "RESERVED_31_16,Reserved" hexmask.long.byte 0x14 12.--15. 1. "CMDSTATUS,Command Status - 1: CmdErr: Indicates that the device controller encountered an error while processing the command. - 0: Indicates command success" newline rbitfld.long 0x14 11. "RESERVED_11,Reserved" "0,1" bitfld.long 0x14 10. "CMDACT,Command Active The software sets this bit to 1 to enable the device controller to execute the generic command. The device controller sets this bit to 0 after executing the command." "0,1" newline rbitfld.long 0x14 9. "RESERVED_9,Reserved" "0,1" bitfld.long 0x14 8. "CMDIOC,Command Interrupt on Complete When this bit is set the device controller issues a Generic Command Completion event after executing the command. Note that this interrupt is mapped to DCFG.IntrNum. Note: This field must not set to '1' if the.." "0,1" newline hexmask.long.byte 0x14 0.--7. 1. "CMDTYP,CMDTYP Generic Command Type Specifies the type of generic command the software driver is requesting the controller to perform. - 02h: Set Periodic Parameters - 04h: Set Scratchpad Buffer Array Address Lo - 05h: Set Scratchpad Buffer Array Address.." group.long (0x20+0x50944)++0x3 line.long 0x0 "DALEPENA,Device Active USB Endpoint Enable Register. This register indicates whether a USB endpoint is active in a given configuration or interface." hexmask.long 0x0 0.--31. 1. "USBACTEP,USBACTEP USB Active Endpoints (USBActEP) This field indicates if a USB endpoint is active in the current configuration and interface. It applies to USB IN endpoints 0.15 and OUT endpoints 0.15 with one bit for each of the 32 possible endpoints." rgroup.long (0x24+0x50944)++0x3 line.long 0x0 "RSVD,Reserved" hexmask.long 0x0 0.--31. 1. "RESERVED_31_0,Reserved" group.long (0x100+0x50944)++0xF line.long 0x0 "DEPCMDPAR2,Device Physical Endpoint-n Command Parameter 2 Register (DEPCMDPAR2n) This register indicates the physical endpoint command Parameter 2. It must be programmed before issuing the command." hexmask.long 0x0 0.--31. 1. "PARAMETER,PARAMETER" line.long 0x4 "DEPCMDPAR1,Device Physical Endpoint-n Command Parameter 1 Register (DEPCMDPAR1n)" hexmask.long 0x4 0.--31. 1. "PARAMETER,PARAMETER" line.long 0x8 "DEPCMDPAR0,Device Physical Endpoint-n Command Parameter 0 Register (DEPCMDPAR0n)" hexmask.long 0x8 0.--31. 1. "PARAMETER,PARAMETER" line.long 0xC "DEPCMD,Device Physical Endpoint-n Command Register This register enables software to issue physical endpoint-specific commands. This register contains command. control. and status fields relevant to the current generic command. while the DEPCMDPAR[2:0]n.." hexmask.long.word 0xC 16.--31. 1. "COMMANDPARAM,Command Parameters or Event Parameters Command Parameters (CommandParam) when this register is written: For Start Transfer command: - [31:16]: StreamID. The USB StreamID assigned to this transfer For Start Transfer command applied to an.." hexmask.long.byte 0xC 12.--15. 1. "CMDSTATUS,Command Completion Status (CmdStatus) Additional information about the completion of this command is available in this field. The information is in the same format as bits 15:12 of the Endpoint Command Complete event see 'Device Endpoint-n.." newline bitfld.long 0xC 11. "HIPRI_FORCERM,HighPriority/ForceRM (HiPri_ForceRM) - HighPriority: Only valid for Start Transfer command - ForceRM: Only valid for End Transfer command - ClearPendIN: Only valid for Clear Stall command . Software sets this bit to clear any pending IN.." "0,1" bitfld.long 0xC 10. "CMDACT,Command Active (CmdAct) Software sets this bit to 1 to enable the device endpoint controller to execute the generic command. The device controller sets this bit to 0 when the CmdStatus field is valid and the endpoint is ready to accept another.." "0,1" newline rbitfld.long 0xC 9. "RESERVED_9,Reserved" "0,1" bitfld.long 0xC 8. "CMDIOC,CMDIOC Command Interrupt on Complete (CmdIOC) When this bit is set the device controller issues a generic Endpoint Command Complete event after executing the command. Note that this interrupt is mapped to DEPCFG.IntrNum. When the DEPCFG command.." "0,1" newline hexmask.long.byte 0xC 4.--7. 1. "RESERVED_7_4,Reserved" hexmask.long.byte 0xC 0.--3. 1. "CMDTYP,Command Type Specifies the type of command the software driver is requesting the controller to perform. - 00h: Reserved - 01h: Set Endpoint Configuration - -64 or 96-bit Parameter - 02h: Set Endpoint Transfer Resource Configuration - 32-bit.." group.long (0x300+0x50944)++0x3 line.long 0x0 "DEV_IMOD,Device Interrupt Moderation Register (DEV_IMOD) This register controls the Interrupt Moderation feature that allows the device software to throttle the interrupt rate. Key Functions: - Interrupt Moderation is enabled only when the IMOD Interval.." hexmask.long.word 0x0 16.--31. 1. "DEVICE_IMODC,Interrupt Moderation Down Counter Loaded with the DEVICE_IMODI value whenever the hardware interrupt(n) line is de-asserted from the asserted state counts down to 0 and stops. The interrupt(n) is signaled whenever this counter is 0.." hexmask.long.word 0x0 0.--15. 1. "DEVICE_IMODI,Moderation Interval (DEVICE_IMODI) This field holds the minimum inter-interrupt interval between events. The interval is specified in terms of 250ns increments. A value of 0 disables the interrupt throttling logic and interrupts are.." tree.end tree "DWC_usb3_block_bc (USB 3.0 BC Register Block)" group.long (0x0+0x52272)++0x3 line.long 0x0 "BCFG,BC Configuration Register" hexmask.long 0x0 2.--31. 1. "RESERVED_31_2,Reserved" bitfld.long 0x0 1. "IDDIG_SEL,This field is not used." "0,1" bitfld.long 0x0 0. "CHIRP_EN,Chirp Enable When this bit is 1'b1 the controller asserts the bc_chirp_on output signal to indicate an imminent chirp." "0,1" group.long (0x8+0x52272)++0x7 line.long 0x0 "BCEVT,BC Event Register Writing 1 to the info bit in this register clears the register bit and the associated interrupt." hexmask.long.byte 0x0 25.--31. 1. "RESERVED_31_25,Reserved" bitfld.long 0x0 24. "MV_CHNGEVNT,Multi-Valued input changed Event: This event indicates that there is a change in the value of at least one ACA pin value. This bit is present only if DWC_USB3_EN_BC = 1 otherwise it is Reserved." "0,1" hexmask.long.tbyte 0x0 5.--23. 1. "RESERVED_23_5,Reserved" hexmask.long.byte 0x0 0.--4. 1. "MULTVALIDBC,Multi Valued ID pin Indicates the Battery Charger ACA inputs. - MultValIdBc[4]: bc_rid_float - MultValIdBc[3]: bc_rid_gnd - MultValIdBc[2]: bc_rid_a - MultValIdBc[1]: bc_rid_b - MultValIdBc[0]: bc_rid_c" line.long 0x4 "BCEVTEN,BC Event Enable Register" hexmask.long.byte 0x4 25.--31. 1. "RESERVED_31_25,Reserved" bitfld.long 0x4 24. "MV_CHNGEVNTENA,BCEvtInfoEna[0] Multi-Valued input changed Event Enable (MV_ChngEvntEn) When this bit is set MV_ChngEvnt in BCEVT register is enabled." "0,1" hexmask.long.tbyte 0x4 0.--23. 1. "RESERVED_23_0,Reserved" tree.end tree "DWC_usb3_block_link (USB 3.0 Link Register Block)" group.long (0x0+0x53248)++0x3 line.long 0x0 "LU1LFPSRXTIM,U1/U2 LFPS Rx Timer Register - Link Layer Register for U1/U2 LFPS RX Timers. - This register is common for all SS ports." hexmask.long.word 0x0 16.--31. 1. "RESERVED_16_31,Reserved" hexmask.long.byte 0x0 8.--15. 1. "U1U2_LFPS_EXIT_RX_CLK,Programmable U1U2 LFPS EXIT RX CLKS - Applicable to Remote Partner initiated Ux exit: Time to recognize valid Ux exit request from the remote partner. - This field is encoded as the pipe clk (8ns) count for the LFPS. -- 1: 8ns -- 2:.." hexmask.long.byte 0x0 0.--7. 1. "U1U2_EXIT_RSP_RX_CLK,Programmable U1U2 EXIT RESP RX CLKS - Applicable to locally initiated Ux exit: Minimum LFPS reception from remote to consider Ux exit handshake is successful. - This field is encoded as the pipe clk (8ns) count for the LFPS. -- 1:.." group.long (0x20+0x53248)++0xB line.long 0x0 "LINK_SETTINGS,Link Setting Register - Link Layer User Control Register for enabling Link/PHY-specific options. - This register is common for all SS ports." bitfld.long 0x0 31. "RESERVED_31,Reserved" "0,1" bitfld.long 0x0 28.--30. "U1_RESID_TIMER_US,Programmable U1 MIN RESIDENCY TIMER This field specifies U1 MIN RESIDENCY TIMER value in us. Set to 0 to disable the timer." "0,1,2,3,4,5,6,7" bitfld.long 0x0 27. "RESERVED_27,Reserved" "0,1" newline bitfld.long 0x0 24.--26. "PM_LC_TIMER_US,Programmable PM_LC_TIMER This field specifies PM_LC_TIMER value in us." "0,1,2,3,4,5,6,7" hexmask.long.byte 0x0 20.--23. 1. "PM_ENTRY_TIMER_US,Programmable PM_ENTRY_TIMER This field specifies PM_ENTRY_TIMER value in us." hexmask.long.tbyte 0x0 0.--19. 1. "RESERVED_0_19,Reserved" line.long 0x4 "LLUCTL,Link User Control Register - Link Layer User Control Register for enabling Link/PHY-specific options. - This register is common for all SS ports." bitfld.long 0x4 30.--31. "RESERVED_30_31,Reserved" "0,1,2,3" bitfld.long 0x4 29. "SUPPORT_P4_PG,PHY P4 Power gate mode (PG) is enabled. Set this bit if the PHY supports PG mode in P4. This bit is used only for Synopsys PHY." "0,1" bitfld.long 0x4 28. "SUPPORT_P4,Support PHY P3.CPM and P4 Power States. When this bit is set the controller puts the PHY in P3.CPM or P4 in certain states. This bit is used only for Synopsys PHY." "0,1" newline hexmask.long.byte 0x4 24.--27. 1. "RESERVED_24_27,Reserved" bitfld.long 0x4 23. "DISRXDET_LTSSM_TIMER_OVRRD,DisRxDet_LTSSM_Timer_Ovrrd. When DisRxDetU3RxDet is asserted in Polling or U1 the timeout expires immediately." "0,1" hexmask.long.word 0x4 13.--22. 1. "RESERVED_13_22,Reserved" newline bitfld.long 0x4 12. "U2P3CPMOK,P3CPM OK for U2/SSInactive (U2P3CPMok) - 0: During link state U2/SS.Inactive put PHY in P2 (Default) - 1: During link state U2/SS.Inactive put PHY in P3CPM. Note: For a port if both GUCTL1[25]=1 and LUCTL[12]=1 LUCTL[12]=1 takes priority." "During link state U2/SS,During link state U2/SS" bitfld.long 0x4 11. "EN_RESET_PIPE_AFTER_PHY_MUX,en_reset_pipe_after_phy_mux. The controller issues USB 3.0 PHY reset after DisRxDetU3RxDet is de-asserted." "0,1" bitfld.long 0x4 8.--10. "RESERVED_8_10,Reserved" "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 7. "MASK_PIPE_RESET,Mask pipe reset. If this bit is set controller blocks pipe_reset_n from going to the PHY when DisRxDetU3RxDet=1." "0,1" bitfld.long 0x4 6. "RESERVED_6,Reserved" "0,1" bitfld.long 0x4 5. "NO_UX_EXIT_P0_TRANS,no_ux_exit_p0_trans. Link LTSSM detects Ux_exit LFPS when P0 transition is on-going by default. If this bit is set Link LTSSM may miss Ux_exit LFPS when P0 transition is happening." "0,1" newline hexmask.long.byte 0x4 0.--4. 1. "RESERVED_0_4,Reserved" line.long 0x8 "LPTMDPDELAY,Link Datapath Delay Register - Link Layer Timer Register for P3CPM/P4 Residency. - This register is common for all SS ports." hexmask.long.word 0x8 22.--31. 1. "RESERVED_22_31,Reserved" hexmask.long.word 0x8 10.--21. 1. "P3CPMP4_RESIDENCY,p3cpmp4 residency timer value. Minimum number of suspend_clk periods that the controller needs to stay in P3.CPM or P4 before exiting P3.CPM or P4. This field is used only for Synopsys PHY." hexmask.long.word 0x8 0.--9. 1. "RESERVED_0_9,Reserved" tree.end tree "DWC_usb3_block_debug (USB 3.0 Debug Register Block)" group.long (0x0+0x55296)++0x3 line.long 0x0 "U3RHBDBG,U3 Root Hub Debug Register" hexmask.long 0x0 4.--31. 1. "RESERVED_1,Reserved_1" bitfld.long 0x0 3. "TPCFG_TOUT_CTRL,tpcfg_tout_ctrl This bit controls the USB 3.0 port configuration timeout duration. - 1: The port configuration timeout counter resets when the link is not in U0. - 0: The port configuration timeout counter does not reset if the link.." "The port configuration timeout counter does not..,The port configuration timeout counter resets.." rbitfld.long 0x0 0.--2. "RESERVED_0_2,Reserved_0_2" "0,1,2,3,4,5,6,7" tree.end tree "DWC_usb3_block_eXtensible_Host_Cntrl_Cap_Regs (USB 3.0 eXtensible Host Controller Capability Register Block)" rgroup.long (0x0+0x55296)++0x1F line.long 0x0 "CAPLENGTH,Capability Registers Length Host Controller Operational Registers = Base address + CAPLENGTH where CAPLENGTH is `DWC_USB3_HOST_CAP_REG_LEN whose default value is 20h." hexmask.long.word 0x0 16.--31. 1. "HCIVERSION,HC Interface Version Number (HCIVERSION)" hexmask.long.byte 0x0 8.--15. 1. "RESERVED_15_8,Reserved" hexmask.long.byte 0x0 0.--7. 1. "CAPLENGTH,Capability Registers Length (CAPLENGTH)" line.long 0x4 "HCSPARAMS1,Structural Parameters 1 Register For register definitions. refer to the xHCI specification." hexmask.long.byte 0x4 24.--31. 1. "MAXPORTS,Number of Ports (MaxPorts) - Number of ports implemented is defined by the parameter (`DWC_USB3_HOST_NUM_U2_ROOT_PORTS + `DWC_USB3_HOST_NUM_U3_ROOT_PORTS) - Number of ports enabled is controlled by the controller input signals.." hexmask.long.byte 0x4 19.--23. 1. "RESERVED_23_19,Reserved" hexmask.long.word 0x4 8.--18. 1. "MAXINTRS,Number of Interrupters (MaxIntrs) Defined by the configurable parameter `DWC_USB3_HOST_NUM_INTERRUPTER_SUPT" hexmask.long.byte 0x4 0.--7. 1. "MAXSLOTS,Number of device slots (MaxSlots) Defined by configurable parameter `DWC_USB3_NUM_DEVICE_SUPT" line.long 0x8 "HCSPARAMS2,Structural Parameters 2 Register For register definitions. refer to the xHCI specification." hexmask.long.byte 0x8 27.--31. 1. "MAXSCRATCHPADBUFS,Max Scratchpad Bufs Lo The value is calculated based on chosen configuration parameter values. Possible values are 1-4." bitfld.long 0x8 26. "SPR,Scratchpad Restore (SPR)" "0,1" hexmask.long.byte 0x8 21.--25. 1. "MAXSCRATCHPADBUFS_HI,Max Scratchpad Bufs HI The controller automatically updates this field." hexmask.long.word 0x8 8.--20. 1. "RESERVED_20_8,Reserved" newline hexmask.long.byte 0x8 4.--7. 1. "ERSTMAX,Event Ring Segment Table Max (ERST Max)" hexmask.long.byte 0x8 0.--3. 1. "IST,Isochronous Scheduling Threshold (IST)" line.long 0xC "HCSPARAMS3,Structural Parameters 3 Register For register definitions. refer to the xHCI specification." hexmask.long.word 0xC 16.--31. 1. "U2_DEVICE_EXIT_LAT,U2 Device Exit Latency" hexmask.long.byte 0xC 8.--15. 1. "RESERVED_15_8,Reserved" hexmask.long.byte 0xC 0.--7. 1. "U1_DEVICE_EXIT_LAT,U1 Device Exit Latency" line.long 0x10 "HCCPARAMS1,Capability Parameters 1 Register For register definitions. refer to the xHCI specification." hexmask.long.word 0x10 16.--31. 1. "XECP,xHCI Extended Capabilities Pointer (xECP) Based on configuration controller automatically updates it. Refer to /src/DWC_usb3_params.v for details on DWC_USB3_HC_XECP." hexmask.long.byte 0x10 12.--15. 1. "MAXPSASIZE,Maximum Primary Stream Array Size (MaxPSASize) For a description of this standard USB register field see the eXtensible Host Controller Interface for Universal Serial Bus (USB) Specification 3.0." bitfld.long 0x10 11. "CFC,Contiguous Frame ID Capability (CFC)" "0,1" bitfld.long 0x10 10. "SEC,Stopped EDLTA Capability (SEC) For a description of this standard USB register field see the eXtensible Host Controller Interface for Universal Serial Bus (USB) Specification 3.0." "0,1" newline bitfld.long 0x10 9. "SPC,Short Packet Capability (SPC) For a description of this standard USB register field see the eXtensible Host Controller Interface for Universal Serial Bus (USB) Specification 3.0." "0,1" bitfld.long 0x10 8. "PAE,Parse All Event Data (PAE) For a description of this standard USB register field see the eXtensible Host Controller Interface for Universal Serial Bus (USB) Specification 3.0." "0,1" bitfld.long 0x10 7. "NSS,No Secondary SID Support (NSS) For a description of this standard USB register field see the eXtensible Host Controller Interface for Universal Serial Bus (USB) Specification 3.0." "0,1" bitfld.long 0x10 6. "LTC,Latency Tolerance Messaging Capability (LTC) For a description of this standard USB register field see the eXtensible Host Controller Interface for Universal Serial Bus (USB) Specification 3.0." "0,1" newline bitfld.long 0x10 5. "LHRC,Light HC Reset Capability For a description of this standard USB register field see the eXtensible Host Controller Interface for Universal Serial Bus (USB) Specification 3.0." "0,1" bitfld.long 0x10 4. "PIND,Port Indicators (PIND) For a description of this standard USB register field see the eXtensible Host Controller Interface for Universal Serial Bus (USB) Specification 3.0." "0,1" bitfld.long 0x10 3. "PPC,Port Power Control For a description of this standard USB register field see the eXtensible Host Controller Interface for Universal Serial Bus (USB) Specification 3.0." "0,1" bitfld.long 0x10 2. "CSZ,Context Size (CSZ) For a description of this standard USB register field see the eXtensible Host Controller Interface for Universal Serial Bus (USB) Specification 3.0." "0,1" newline bitfld.long 0x10 1. "BNC,BW Negotiation Capability (BNC) For a description of this standard USB register field see the eXtensible Host Controller Interface for Universal Serial Bus (USB) Specification 3.0." "0,1" bitfld.long 0x10 0. "AC64,64-bit Addressing Capability (AC64) For a description of this standard USB register field see the eXtensible Host Controller Interface for Universal Serial Bus (USB) Specification 3.0." "0,1" line.long 0x14 "DBOFF,Doorbell Offset Register For register definitions. refer to the xHCI specification." hexmask.long 0x14 2.--31. 1. "DOORBELL_ARRAY_OFFSET,Doorbell Array Offset - RO Based on configuration the controller automatically updates it. For a description of this standard USB register field see the eXtensible Host Controller Interface for Universal Serial Bus (USB).." bitfld.long 0x14 0.--1. "RESERVED_1_0,Reserved" "0,1,2,3" line.long 0x18 "RTSOFF,Runtime Register Space Offset Register" hexmask.long 0x18 5.--31. 1. "RUNTIME_REG_SPACE_OFFSET,Runtime Register Space Offset Based on configuration the controller automatically updates it. For a description of this standard USB register field see the eXtensible Host Controller Interface for Universal Serial Bus (USB).." hexmask.long.byte 0x18 0.--4. 1. "RESERVED_4_0,Reserved" line.long 0x1C "HCCPARAMS2,Host Controller Capability Parameters 2 For register definitions. refer to the xHCI specification." hexmask.long 0x1C 6.--31. 1. "RESERVED_31_6,Reserved" bitfld.long 0x1C 5. "CIC,Configuration Information Capability (CIC) For a description of this standard USB register field see the eXtensible Host Controller I nterface for Universal Serial Bus (USB) Specification 3.0." "0,1" bitfld.long 0x1C 4. "LEC,Large ESIT Payload Capability (LEC) For a description of this standard USB register field see the eXtensible Host Controller I nterface for Universal Serial Bus (USB) Specification 3.0." "0,1" bitfld.long 0x1C 3. "CTC,Compliance Transition Capability (CTC) For a description of this standard USB register field see the eXtensible Host Controller I nterface for Universal Serial Bus (USB) Specification 3.0." "0,1" newline bitfld.long 0x1C 2. "FSC,Force Save Context Capability (FSC) For a description of this standard USB register field see the eXtensible Host Controller I nterface for Universal Serial Bus (USB) Specification 3.0." "0,1" bitfld.long 0x1C 1. "CMC,Configure Endpoint Command Max Exit Latency Too Large Capability (CMC) For a description of this standard USB register field see the eXtensible Host Controller I nterface for Universal Serial Bus (USB) Specification 3.0." "0,1" bitfld.long 0x1C 0. "U3C,U3 Entry Capability (U3C) For a description of this standard USB register field see the eXtensible Host Controller I nterface for Universal Serial Bus (USB) Specification 3.0." "0,1" tree.end tree "DWC_usb3_block_Host_Cntrl_Oper_Regs (USB3 Host Cntrl Oper Regs Block)" group.long (0x0+0x32)++0x7 line.long 0x0 "USBCMD,USB Command Register For a description of this standard USB register field see the eXtensible Host Controller Interface for Universal Serial Bus (USB) Specification 3.0." hexmask.long.tbyte 0x0 14.--31. 1. "RESERVED_31_14,Reserved" bitfld.long 0x0 13. "CME,CEM Enable For a description of this standard USB register field see the eXtensible Host Controller Interface for Universal Serial Bus (USB) Specification 3.0." "0,1" rbitfld.long 0x0 12. "RESERVED_12,Reserved" "0,1" bitfld.long 0x0 11. "EU3S,EU3S For a description of this standard USB register field see the eXtensible Host Controller Interface for Universal Serial Bus (USB) Specification 3.0." "0,1" bitfld.long 0x0 10. "EWE,EWE For a description of this standard USB register field see the eXtensible Host Controller Interface for Universal Serial Bus (USB) Specification 3.0." "0,1" newline bitfld.long 0x0 9. "CRS,Controller Restore State This command is similar to the USBCMD.CRS bit in host mode and initiates the restore process. When software sets this bit to '1' the controller immediately sets DSTS.RSS to '1'. When the controller has finished the restore.." "0,1" bitfld.long 0x0 8. "CSS,Controller Save State This command is similar to the USBCMD.CSS bit in host mode and initiates the save process. When software sets this bit to '1' the controller immediately sets DSTS.SSS to '1'. When the controller has finished the save process.." "0,1" bitfld.long 0x0 7. "LHCRST,Light Host Controller Reset For a description of this standard USB register field see the eXtensible Host Controller Interface for Universal Serial Bus (USB) Specification 3.0. The following bits reset the internal logic of the host controller." "0,1" rbitfld.long 0x0 4.--6. "RESERVED_6_4,Reserved" "0,1,2,3,4,5,6,7" bitfld.long 0x0 3. "HSEE,HSEE For a description of this standard USB register field see the eXtensible Host Controller Interface for Universal Serial Bus (USB) Specification 3.0." "0,1" newline bitfld.long 0x0 2. "INTE,INTE For a description of this standard USB register field see the eXtensible Host Controller Interface for Universal Serial Bus (USB) Specification 3.0." "0,1" bitfld.long 0x0 1. "HCRST,HCRST The following bits reset the internal logic of the host controller. Under soft reset some CSR accesses may fail (Timeout). - HCRST - LHCRST Bit Bash register testing is not recommended." "0,1" bitfld.long 0x0 0. "R_S,R_S For a description of this standard USB register field see the eXtensible Host Controller Interface for Universal Serial Bus (USB) Specification 3.0. Due to side-effects this reguster field is not recommended for Bit-Bash testing." "0,1" line.long 0x4 "USBSTS,USB Status Register Bit Definitions For a description of this standard USB register field. see the eXtensible Host Controller Interface for Universal Serial Bus (USB) Specification 3.0." hexmask.long.tbyte 0x4 13.--31. 1. "RESERVED_31_13,Reserved" rbitfld.long 0x4 12. "HCE,Host Controller Error (HCE) - RO Default = 0. '0' = No internal xHC error conditions exist and '1' = Internal xHC error condition. This flag must be set to indicate that an internal error condition has been detected which requires software to reset.." "0,1" rbitfld.long 0x4 11. "CNR,Controller Not Ready (CNR) - RO Default = '1'. '0' = Ready and '1' = Not Ready. Software must not write to thes Doorbell or Operational register of the xHC other than the USBSTS register until CNR = '0'. This flag is set by the xHC after a Chip.." "0,1" bitfld.long 0x4 10. "SRE,Save/Restore Error This bit is currently not supported." "0,1" rbitfld.long 0x4 9. "RSS,Restore State Status This bit is similar to the USBSTS.RSS in host mode. When the controller has finished the restore process it completes the command by setting DSTS.RSS to '0'." "0,1" newline rbitfld.long 0x4 8. "SSS,Save State Status This bit is similar to the USBSTS.SSS in host mode. When the controller has finished the save process it completes the command by setting DSTS.SSS to '0'." "0,1" rbitfld.long 0x4 5.--7. "RESERVED_7_5,Reserved" "0,1,2,3,4,5,6,7" bitfld.long 0x4 4. "PCD,Reset Value for PCD" "0,1" bitfld.long 0x4 3. "EINT,Reset Value for EINT" "0,1" bitfld.long 0x4 2. "HSE,HSE For a description of this standard USB register field see the eXtensible Host Controller Interface for Universal Serial Bus (USB) Specification 3.0.." "0,1" newline rbitfld.long 0x4 1. "RESERVED_1,Reserved" "0,1" rbitfld.long 0x4 0. "HCH,HCH For a description of this standard USB register field see the eXtensible Host Controller Interface for Universal Serial Bus (USB) Specification 3.0." "0,1" rgroup.long (0x8+0x32)++0x3 line.long 0x0 "PAGESIZE,Page Size Register Bit Definitions Use this register to enable or disable the reporting of specific USB Device Notification Transaction Packets being received. A Notification Enable (Nx. where x = 0 to 15) flag is defined for each of the 16.." hexmask.long.word 0x0 16.--31. 1. "RESERVED_31_16,Reserved" hexmask.long.word 0x0 0.--15. 1. "PAGE_SIZE,PAGE_SIZE" group.long (0x14+0x32)++0xB line.long 0x0 "DNCTRL,Device Notification Register Bit Definitions For a description of this standard USB register field see the eXtensible Host Controller Interface for Universal Serial Bus (USB) Specification 3.0." hexmask.long.word 0x0 16.--31. 1. "RESERVED_31_16,Reserved" hexmask.long.word 0x0 0.--15. 1. "N0_N15,N0_N15 For a description of this standard USB register field see the eXtensible Host Controller Interface for Universal Serial Bus (USB) Specification 3.0." line.long 0x4 "CRCR_LO,CRCR_LO For a description of this standard USB register field. see the eXtensible Host Controller Interface for Universal Serial Bus (USB) Specification 3.0." hexmask.long 0x4 6.--31. 1. "CMD_RING_PNTR,CMD_RING_PNTR For a description of this standard USB register field see the eXtensible Host Controller Interface for Universal Serial Bus (USB) Specification 3.0." rbitfld.long 0x4 4.--5. "RESERVED_5_4,Reserved" "0,1,2,3" rbitfld.long 0x4 3. "CRR,CRR For a description of this standard USB register field see the eXtensible Host Controller Interface for Universal Serial Bus (USB) Specification 3.0." "0,1" bitfld.long 0x4 2. "CA,CA For a description of this standard USB register field see the eXtensible Host Controller Interface for Universal Serial Bus (USB) Specification 3.0." "0,1" bitfld.long 0x4 1. "CS,CS For a description of this standard USB register field see the eXtensible Host Controller Interface for Universal Serial Bus (USB) Specification 3.0." "0,1" newline bitfld.long 0x4 0. "RCS,RCS For a description of this standard USB register field see the eXtensible Host Controller Interface for Universal Serial Bus (USB) Specification 3.0." "0,1" line.long 0x8 "CRCR_HI,CRCR_HI" hexmask.long 0x8 0.--31. 1. "CMD_RING_PNTR,COMMAND_RING_POINTER Reading this field always returns '0'. For a description of this standard USB register field see the eXtensible Host Controller Interface for Universal Serial Bus (USB) Specification 3.0." group.long (0x30+0x32)++0xB line.long 0x0 "DCBAAP_LO,DCBAAP_LO" hexmask.long 0x0 6.--31. 1. "DEVICE_CONTEXT_BAAP,DEVICE_CONTEXT_BAAP For a description of this standard USB register field see the eXtensible Host Controller Interface for Universal Serial Bus (USB) Specification 3.0." hexmask.long.byte 0x0 0.--5. 1. "RESERVED_5_0,Reserved" line.long 0x4 "DCBAAP_HI,DCBAAP_HI For a description of this standard USB register field. see the eXtensible Host Controller Interface for Universal Serial Bus (USB) Specification 3.0." hexmask.long 0x4 0.--31. 1. "DEVICE_CONTEXT_BAAP,DEVICE_CONTEXT_BAAP" line.long 0x8 "CONFIG,Configure Register Bit Definitions This register is in the Aux Power well. It is only reset by platform hardware during a cold reset or in response to a Host Controller Reset (HCRST). The initial conditions of a port are described in section 4.19.." hexmask.long.tbyte 0x8 10.--31. 1. "RESERVED_31_10,Reserved" bitfld.long 0x8 9. "CIE,Configuration Information Enable For a description of this standard USB register field see the eXtensible Host Controller Interface for Universal Serial Bus (USB) Specification 3.0." "0,1" bitfld.long 0x8 8. "U3E,U3 Entry Enable For a description of this standard USB register field see the eXtensible Host Controller Interface for Universal Serial Bus (USB) Specification 3.0." "0,1" hexmask.long.byte 0x8 0.--7. 1. "MAXSLOTSEN,MAXSLOTSEN For a description of this standard USB register field see the eXtensible Host Controller Interface for Universal Serial Bus (USB) Specification 3.0." tree.end tree "DWC_usb3_block_Host_Cntrl_Port_Reg_Set (USB3 Host Cntrl Port Reg Set Block)" group.long (0x0+0x1056)++0x7 line.long 0x0 "PORTSC_20,Port Status and Control Register Bit Definitions The PORTSC Register Access fails (Timeout) if the UTMI/ULPI clock is not running or one of the following bits is asserted. - PR - ORC" rbitfld.long 0x0 31. "RESERVED_31,Reserved For a description of this standard USB register field see the eXtensible Host Controller Interface for Universal Serial Bus (USB) Specification 3.0. Programming this field with random data will cause side effect i.e. Register Access.." "0,1" rbitfld.long 0x0 30. "DR,Reset Value For a description of this standard USB register field see the eXtensible Host Controller Interface for Universal Serial Bus (USB) Specification 3.0." "0,1" rbitfld.long 0x0 28.--29. "RESERVED_29_28,Reserved" "0,1,2,3" bitfld.long 0x0 27. "WOE,WOE For a description of this standard USB register field see the eXtensible Host Controller Interface for Universal Serial Bus (USB) Specification 3.0." "0,1" newline bitfld.long 0x0 26. "WDE,WDE For a description of this standard USB register field see the eXtensible Host Controller Interface for Universal Serial Bus (USB) Specification 3.0." "0,1" bitfld.long 0x0 25. "WCE,WCE For a description of this standard USB register field see the eXtensible Host Controller Interface for Universal Serial Bus (USB) Specification 3.0." "0,1" rbitfld.long 0x0 24. "CAS,Cold Attach Status For a description of this standard USB register field see the eXtensible Host Controller Interface for Universal Serial Bus (USB) Specification 3.0." "0,1" rbitfld.long 0x0 23. "RESERVED_23,Reserved For a description of this standard USB register field see the eXtensible Host Controller Interface for Universal Serial Bus (USB) Specification 3.0." "0,1" newline bitfld.long 0x0 22. "PLC,PLC For a description of this standard USB register field see the eXtensible Host Controller Interface for Universal Serial Bus (USB) Specification 3.0." "0,1" bitfld.long 0x0 21. "PRC,PRC For a description of this standard USB register field see the eXtensible Host Controller Interface for Universal Serial Bus (USB) Specification 3.0. Programming this field with random data will cause side effect. Bit Bash register testing is not.." "0,1" bitfld.long 0x0 20. "OCC,OCC For a description of this standard USB register field see the eXtensible Host Controller Interface for Universal Serial Bus (USB) Specification 3.0." "0,1" bitfld.long 0x0 19. "RESERVED_19,WRC For a description of this standard USB register field see the eXtensible Host Controller Interface for Universal Serial Bus (USB) Specification 3.0." "0,1" newline bitfld.long 0x0 18. "PEC,PEC For a description of this standard USB register field see the eXtensible Host Controller Interface for Universal Serial Bus (USB) Specification 3.0." "0,1" bitfld.long 0x0 17. "CSC,CSC For a description of this standard USB register field see the eXtensible Host Controller Interface for Universal Serial Bus (USB) Specification 3.0." "0,1" bitfld.long 0x0 16. "LWS,LWS For a description of this standard USB register field see the eXtensible Host Controller Interface for Universal Serial Bus (USB) Specification 3.0." "0,1" bitfld.long 0x0 14.--15. "PIC,PIC For a description of this standard USB register field see the eXtensible Host Controller Interface for Universal Serial Bus (USB) Specification 3.0." "0,1,2,3" newline hexmask.long.byte 0x0 10.--13. 1. "PORTSPEED,PORTSPEED For a description of this standard USB register field see the eXtensible Host Controller Interface for Universal Serial Bus (USB) Specification 3.0." bitfld.long 0x0 9. "PP,PP For a description of this standard USB register field see the eXtensible Host Controller Interface for Universal Serial Bus (USB) Specification 3.0." "0,1" hexmask.long.byte 0x0 5.--8. 1. "PLS,PLS For a description of this standard USB register field see the eXtensible Host Controller Interface for Universal Serial Bus (USB) Specification 3.0." bitfld.long 0x0 4. "PR,PR set_register_field_attribute DWC_usb3_map/DWC_usb3_block_Host_Cntrl_Port_Reg_Set/PORTSC_20_REGS/PORTSC_20/PR VolatileMemory 1 Programming this field with random data will cause side effect. Bit Bash register testing is not recommended." "0,1" newline rbitfld.long 0x0 3. "OCA,OCA For a description of this standard USB register field see the eXtensible Host Controller Interface for Universal Serial Bus (USB) Specification 3.0." "0,1" rbitfld.long 0x0 2. "RESERVED_2,Reserved" "0,1" bitfld.long 0x0 1. "PED,PED For a description of this standard USB register field see the eXtensible Host Controller Interface for Universal Serial Bus (USB) Specification 3.0." "0,1" rbitfld.long 0x0 0. "CCS,CCS For a description of this standard USB register field see the eXtensible Host Controller Interface for Universal Serial Bus (USB) Specification 3.0." "0,1" line.long 0x4 "PORTPMSC_20,USB3 Port Power Management Status and Control Register Bit Definitions This register is in the Aux Power well. It is only reset by platform hardware during a cold reset or in response to a Host Controller Reset (HCRST). Programming this field.." hexmask.long.byte 0x4 28.--31. 1. "PRTTSTCTRL,Port Test Control For a description of this standard USB register field see the eXtensible Host Controller Interface for Universal Serial Bus (USB) Specification 3.0." hexmask.long.word 0x4 17.--27. 1. "RESERVED_27_17,Reserved" bitfld.long 0x4 16. "HLE,Port Test Control For a description of this standard USB register field see the eXtensible Host Controller Interface for Universal Serial Bus (USB) Specification 3.0." "0,1" hexmask.long.byte 0x4 8.--15. 1. "L1DSLOT,L1DSLOT For a description of this standard USB register field see the eXtensible Host Controller Interface for Universal Serial Bus (USB) Specification 3.0." newline hexmask.long.byte 0x4 4.--7. 1. "HIRD,Host Initiated Resume Duration (HIRD) - RW. Default = '0'. System software sets this field to indicate to the recipient device how long the xHC will drive resume if it (the xHC) initiates an exit from L1. The HIRD value is encoded as follows: Value.." bitfld.long 0x4 3. "RWE,RWE Port Test Control For a description of this standard USB register field see the eXtensible Host Controller Interface for Universal Serial Bus (USB) Specification 3.0." "0,1" rbitfld.long 0x4 0.--2. "L1S,L1 Status (L1S) - RO. Default = 0. This field is used by software to determine whether an L1-based suspend request (LMP transaction) was successful specifically: Value Meaning 0 Invalid - This field is ignored by software. - 1 Success - Port.." "?,based suspend request,?,?,?,?,?,?" rgroup.long (0x8+0x1056)++0x3 line.long 0x0 "PORTLI_20,Port Link Info Register Programming this field with random data will cause side effect i.e. Register Access will fail (Timeout) if the pipe clock is not running or reset is asserted . Bit Bash register testing is not recommended." hexmask.long 0x0 0.--31. 1. "RESERVED_31_0,Reserved" group.long (0xC+0x1056)++0xB line.long 0x0 "PORTHLPMC_20,USB2 Port Hardware LPM Control Register Bit Definitions For a description of this standard USB register field. see the eXtensible Host Controller Interface for Universal Serial Bus (USB) Specification 3.0." hexmask.long.tbyte 0x0 14.--31. 1. "RESERVED_31_14,Reserved For a description of this standard USB register field see the eXtensible Host Controller Interface for Universal Serial Bus (USB) Specification 3.0." hexmask.long.byte 0x0 10.--13. 1. "HIRDD,PORTHLPMC_20 HIRDD" hexmask.long.byte 0x0 2.--9. 1. "L1_TIMEOUT,PORTHLPMC_20 L1_TIMEOUT. For a description of this standard USB register field see the eXtensible Host Controller Interface for Universal Serial Bus (USB) Specification 3.0." bitfld.long 0x0 0.--1. "HIRDM,Host Initiated Resume Duration Mode (HIRDM) - RWS. Default = 0h. Indicates which HIRD value must be used. The following are permissible values: Value Description 0 Initiate L1 using HIRD only on timeout. (default) 1 Initiate L1 using HIRDD on.." "0,1,2,3" line.long 0x4 "PORTSC_30,Port Status and Control Register Bit Definitions The PORTSC Register Access fails (Timeout) if the UTMI/ULPI clock is not running or one of the following bits is asserted. - PR - ORC - WPR" bitfld.long 0x4 31. "WPR,Reset Value For a description of this standard USB register field see the eXtensible Host Controller Interface for Universal Serial Bus (USB) Specification 3.0. Programming this field with random data will cause side effect i.e. Register Access will.." "0,1" rbitfld.long 0x4 30. "DR,Reset Value For a description of this standard USB register field see the eXtensible Host Controller Interface for Universal Serial Bus (USB) Specification 3.0." "0,1" rbitfld.long 0x4 28.--29. "RESERVED_29_28,Reserved" "0,1,2,3" bitfld.long 0x4 27. "WOE,WOE For a description of this standard USB register field see the eXtensible Host Controller Interface for Universal Serial Bus (USB) Specification 3.0." "0,1" newline bitfld.long 0x4 26. "WDE,WDE For a description of this standard USB register field see the eXtensible Host Controller Interface for Universal Serial Bus (USB) Specification 3.0." "0,1" bitfld.long 0x4 25. "WCE,WCE For a description of this standard USB register field see the eXtensible Host Controller Interface for Universal Serial Bus (USB) Specification 3.0." "0,1" rbitfld.long 0x4 24. "CAS,Cold Attach Status For a description of this standard USB register field see the eXtensible Host Controller Interface for Universal Serial Bus (USB) Specification 3.0." "0,1" bitfld.long 0x4 23. "CEC,CEC For a description of this standard USB register field see the eXtensible Host Controller Interface for Universal Serial Bus (USB) Specification 3.0." "0,1" newline bitfld.long 0x4 22. "PLC,PLC For a description of this standard USB register field see the eXtensible Host Controller Interface for Universal Serial Bus (USB) Specification 3.0." "0,1" bitfld.long 0x4 21. "PRC,PRC For a description of this standard USB register field see the eXtensible Host Controller Interface for Universal Serial Bus (USB) Specification 3.0. Programming this field with random data will cause side effect. Bit Bash register testing is not.." "0,1" bitfld.long 0x4 20. "OCC,OCC For a description of this standard USB register field see the eXtensible Host Controller Interface for Universal Serial Bus (USB) Specification 3.0." "0,1" bitfld.long 0x4 19. "WRC,WRC For a description of this standard USB register field see the eXtensible Host Controller Interface for Universal Serial Bus (USB) Specification 3.0." "0,1" newline bitfld.long 0x4 18. "PEC,PEC For a description of this standard USB register field see the eXtensible Host Controller Interface for Universal Serial Bus (USB) Specification 3.0." "0,1" bitfld.long 0x4 17. "CSC,CSC For a description of this standard USB register field see the eXtensible Host Controller Interface for Universal Serial Bus (USB) Specification 3.0." "0,1" bitfld.long 0x4 16. "LWS,LWS For a description of this standard USB register field see the eXtensible Host Controller Interface for Universal Serial Bus (USB) Specification 3.0." "0,1" bitfld.long 0x4 14.--15. "PIC,PIC For a description of this standard USB register field see the eXtensible Host Controller Interface for Universal Serial Bus (USB) Specification 3.0." "0,1,2,3" newline hexmask.long.byte 0x4 10.--13. 1. "PORTSPEED,PORTSPEED For a description of this standard USB register field see the eXtensible Host Controller Interface for Universal Serial Bus (USB) Specification 3.0." bitfld.long 0x4 9. "PP,PP For a description of this standard USB register field see the eXtensible Host Controller Interface for Universal Serial Bus (USB) Specification 3.0." "0,1" hexmask.long.byte 0x4 5.--8. 1. "PLS,PLS For a description of this standard USB register field see the eXtensible Host Controller Interface for Universal Serial Bus (USB) Specification 3.0." bitfld.long 0x4 4. "PR,PR set_register_field_attribute DWC_usb3_map/DWC_usb3_block_Host_Cntrl_Port_Reg_Set/PORTSC_30_REGS/PORTSC_30/PR VolatileMemory 1 Programming this field with random data will cause side effect. Bit Bash register testing is not recommended." "0,1" newline rbitfld.long 0x4 3. "OCA,OCA For a description of this standard USB register field see the eXtensible Host Controller Interface for Universal Serial Bus (USB) Specification 3.0." "0,1" rbitfld.long 0x4 2. "RESERVED_2,Reserved" "0,1" bitfld.long 0x4 1. "PED,PED For a description of this standard USB register field see the eXtensible Host Controller Interface for Universal Serial Bus (USB) Specification 3.0." "0,1" rbitfld.long 0x4 0. "CCS,CCS For a description of this standard USB register field see the eXtensible Host Controller Interface for Universal Serial Bus (USB) Specification 3.0." "0,1" line.long 0x8 "PORTPMSC_30,USB3 Port Power Management Status and Control Register Bit Definitions This register is in the Aux Power well. It is only reset by platform hardware during a cold reset or in response to a Host Controller Reset (HCRST). Programming this field.." hexmask.long.word 0x8 17.--31. 1. "RESERVED_31_17,Reserved" bitfld.long 0x8 16. "FLA,FLA For a description of this standard USB register field see the eXtensible Host Controller Interface for Universal Serial Bus (USB) Specification 3.0." "0,1" hexmask.long.byte 0x8 8.--15. 1. "U2_TIMEOUT,U2_TIMEOUT For a description of this standard USB register field see the eXtensible Host Controller Interface for Universal Serial Bus (USB) Specification 3.0." hexmask.long.byte 0x8 0.--7. 1. "U1_TIMEOUT,U1_TIMEOUT For a description of this standard USB register field see the eXtensible Host Controller Interface for Universal Serial Bus (USB) Specification 3.0." rgroup.long (0x18+0x1056)++0x7 line.long 0x0 "PORTLI_30,Port Link Info Register Programming this field with random data will cause side effect i.e. Register Access will fail (Timeout) if the pipe clock is not running or reset is asserted . Bit Bash register testing is not recommended." hexmask.long.word 0x0 16.--31. 1. "RESERVED_31_16,Reserved" hexmask.long.word 0x0 0.--15. 1. "LINK_ERROR_COUNT,LINK_ERROR_COUNT For a description of this standard USB register field see the eXtensible Host Controller Interface for Universal Serial Bus (USB) Specification 3.0." line.long 0x4 "PORTHLPMC_30,USB2 Port Hardware LPM Control Register Bit Definitions For a description of this standard USB register field. see the eXtensible Host Controller Interface for Universal Serial Bus (USB) Specification 3.0." hexmask.long 0x4 0.--31. 1. "RESERVED_31_0,Reserved For a description of this standard USB register field see the eXtensible Host Controller Interface for Universal Serial Bus (USB) Specification 3.0." tree.end tree "DWC_usb3_block_Host_Cntrl_Runtime_Regs (USB3 Host Cntrl Runtime Regs Block)" rgroup.long (0x0+0x1088)++0x7 line.long 0x0 "MFINDEX,Microframe Index Register Bit Definitions For a description of this standard USB register field. see the eXtensible Host Controller Interface for Universal Serial Bus (USB) Specification 3.0." hexmask.long.tbyte 0x0 14.--31. 1. "RESERVED_31_14,Reserved" hexmask.long.word 0x0 0.--13. 1. "MICROFRAME_INDEX,MICROFRAME_INDEX For a description of this standard USB register field see the eXtensible Host Controller Interface for Universal Serial Bus (USB) Specification 3.0." line.long 0x4 "RSVDZ,RsvdZ For a description of this standard USB register field. see the eXtensible Host Controller Interface for Universal Serial Bus (USB) Specification 3.0." hexmask.long 0x4 0.--31. 1. "RESERVED_31_0,Reserved" tree.end tree "DWC_usb3_block_Interrupter_Regs (USB3 Interrupter Regs Block)" group.long (0x0+0x1120)++0xB line.long 0x0 "IMAN,Interrupter Management Register Bit Definitions For a description of this standard USB register field. see the eXtensible Host Controller Interface for Universal Serial Bus (USB) Specification 3.0." hexmask.long 0x0 2.--31. 1. "RESERVED_31_2,Reserved" bitfld.long 0x0 1. "IE,IE For a description of this standard USB register field see the eXtensible Host Controller Interface for Universal Serial Bus (USB) Specification 3.0." "0,1" bitfld.long 0x0 0. "IP,IP Interrupt Pending For a description of this standard USB register field see the eXtensible Host Controller Interface for Universal Serial Bus (USB) Specification 3.0." "0,1" line.long 0x4 "IMOD,Interrupter Moderation Register The software may use this register to pace (or even out) the delivery of interrupts to the host CPU. This register provides a guaranteed inter-interrupt delay between interrupts asserted by the xHC. regardless of USB.." hexmask.long.word 0x4 16.--31. 1. "IMODC,Interrupt Moderation Counter (IMODC) - RW. Default = undefined. Down counter. Loaded with the IMODI value whenever IP is cleared to '0' counts down to '0' and stops. The associated interrupt is signaled whenever this counter is '0' the Event.." hexmask.long.word 0x4 0.--15. 1. "IMODI,Interrupt Moderation Interval (IMODI) - RW. Default = '4000' (~1ms). Minimum inter-interrupt interval. The interval is specified in 250ns increments. A value of '0' disables interrupt throttling logic and interrupts is generated immediately if IP =.." line.long 0x8 "ERSTSZ,Event Ring Segment Table Size Register Bit Definitions For a description of this standard USB register field. see the eXtensible Host Controller Interface for Universal Serial Bus (USB) Specification 3.0." hexmask.long.word 0x8 16.--31. 1. "RESERVED_31_16,Reserved" hexmask.long.word 0x8 0.--15. 1. "ERS_TABLE_SIZE,ERS_TABLE_SIZE For a description of this standard USB register field see the eXtensible Host Controller Interface for Universal Serial Bus (USB) Specification 3.0." rgroup.long (0xC+0x1120)++0x3 line.long 0x0 "RSVDP,RsvdP" hexmask.long 0x0 0.--31. 1. "RESERVED_31_0,Reserved" group.long (0x10+0x1120)++0xF line.long 0x0 "ERSTBA_LO,ERSTBA_LO" hexmask.long 0x0 6.--31. 1. "ERS_TABLE_BAR,ERS_TABLE_BAR" hexmask.long.byte 0x0 0.--5. 1. "RESERVED_5_0,Reserved" line.long 0x4 "ERSTBA_HI,ERSTBA_HI" hexmask.long 0x4 0.--31. 1. "ERS_TABLE_BAR,ERS_TABLE_BAR For a description of this standard USB register field see the eXtensible Host Controller Interface for Universal Serial Bus (USB) Specification 3.0." line.long 0x8 "ERDP_LO,ERDP_LO For a description of this standard USB register field. see the eXtensible Host Controller Interface for Universal Serial Bus (USB) Specification 3.0." hexmask.long 0x8 4.--31. 1. "ERD_PNTR,ERD_PNTR For a description of this standard USB register field see the eXtensible Host Controller Interface for Universal Serial Bus (USB) Specification 3.0." bitfld.long 0x8 3. "EHB,HC OS Owned SemaphoreERS_TABLE_SIZEHC BIOS Owned Semaphore USB SMI Enable SMI on Host System Error Enable - SMI on OS Ownership Enable - SMI on PCI Command Enable - SMI on BAR Enable - SMI on Event Interrupt - SMI on Host System Error - SMI on OS.." "0,1" bitfld.long 0x8 0.--2. "DESI,DESI - For a description of this standard USB register field see the eXtensible Host Controller Interface for Universal Serial Bus (USB) Specification 3.0." "0,1,2,3,4,5,6,7" line.long 0xC "ERDP_HI,ERDP_HI" hexmask.long 0xC 0.--31. 1. "ERD_PNTR,ERD_PNTR For a description of this standard USB register field see the eXtensible Host Controller Interface for Universal Serial Bus (USB) Specification 3.0." tree.end tree "DWC_usb3_block_Doorbell_Register (USB3 Doorbell Reg Block)" group.long (0x0+0x1152)++0x3 line.long 0x0 "DB,Doorbell Register Bit Field Definitions For a description of this standard USB register field. see the eXtensible Host Controller Interface for Universal Serial Bus (USB) Specification 3.0. Programming this field with random data will cause side.." hexmask.long.word 0x0 16.--31. 1. "DB_STREAM_ID,DB_STREAM_ID For a description of this standard USB register field see the eXtensible Host Controller Interface for Universal Serial Bus (USB) Specification 3.0." hexmask.long.byte 0x0 8.--15. 1. "RESERVED_15_8,Reserved" hexmask.long.byte 0x0 0.--7. 1. "DB_TARGET,DB_TARGET For a description of this standard USB register field see the eXtensible Host Controller Interface for Universal Serial Bus (USB) Specification 3.0." tree.end tree "DWC_usb3_block_HC_Extended_Capability_Register (USB3 HC Extended Capability Register Block)" group.long (0x0+0x2176)++0x7 line.long 0x0 "USBLEGSUP,USBLEGSUP" hexmask.long.byte 0x0 25.--31. 1. "RESERVED_31_25,Reserved" bitfld.long 0x0 24. "HC_OS_OWNED,HC_OS_OWNED SEMAPHORE For a description of this standard USB register field see the eXtensible Host Controller Interface for Universal Serial Bus (USB) Specification 3.0." "0,1" hexmask.long.byte 0x0 17.--23. 1. "RESERVED_23_17,Reserved" bitfld.long 0x0 16. "HC_BIOS_OWNED,HC_BIOS_OWNED SEMAPHORE For a description of this standard USB register field see the eXtensible Host Controller Interface for Universal Serial Bus (USB) Specification 3.0." "0,1" newline hexmask.long.byte 0x0 8.--15. 1. "NEXT_CAPABILITY_POINTER,NEXT_CAPABILITY_POINTER For a description of this standard USB register field see the eXtensible Host Controller Interface for Universal Serial Bus (USB) Specification 3.0." hexmask.long.byte 0x0 0.--7. 1. "CAPABILITY_ID,CAPABILITY_ID set_register_field_attribute DWC_usb3_map/DWC_usb3_block_HC_Extended_Capability_Register/USBLEGSUP/CAPABILITY_ID RegisterResetValue 0x1 For a description of this standard USB register field see the eXtensible Host Controller.." line.long 0x4 "USBLEGCTLSTS,USBLEGCTLSTS" bitfld.long 0x4 31. "SMI_ON_BAR,SMI_ON_BAR For a description of this standard USB register field see the eXtensible Host Controller Interface for Universal Serial Bus (USB) Specification 3.0." "0,1" bitfld.long 0x4 30. "SMI_ON_PCI,SMI_ON_PCI COMMAND For a description of this standard USB register field see the eXtensible Host Controller Interface for Universal Serial Bus (USB) Specification 3.0." "0,1" bitfld.long 0x4 29. "SMI_ON_OS,SMI_ON_OS OWNERSHIP CHANGE For a description of this standard USB register field see the eXtensible Host Controller Interface for Universal Serial Bus (USB) Specification 3.0." "0,1" hexmask.long.byte 0x4 21.--28. 1. "RESERVED_28_21,Reserved" newline rbitfld.long 0x4 20. "SMI_ON_HOST,SMI_ON_HOST SYSTEM ERROR For a description of this standard USB register field see the eXtensible Host Controller Interface for Universal Serial Bus (USB) Specification 3.0." "0,1" rbitfld.long 0x4 17.--19. "RESERVED_19_17,Reserved" "0,1,2,3,4,5,6,7" rbitfld.long 0x4 16. "SMI_ON_EVENT,SMI_ON_EVENT INTERRUPT For a description of this standard USB register field see the eXtensible Host Controller Interface for Universal Serial Bus (USB) Specification 3.0." "0,1" bitfld.long 0x4 15. "SMI_ON_BAR_E,SMI_ON_BAR ENABLE For a description of this standard USB register field see the eXtensible Host Controller Interface for Universal Serial Bus (USB) Specification 3.0." "0,1" newline bitfld.long 0x4 14. "SMI_ON_PCI_E,SMI_ON_PCI COMMAND ENABLE For a description of this standard USB register field see the eXtensible Host Controller Interface for Universal Serial Bus (USB) Specification 3.0." "0,1" bitfld.long 0x4 13. "SMI_ON_OS_E,SMI_ON_OS OWNERSHIP ENABLE For a description of this standard USB register field see the eXtensible Host Controller Interface for Universal Serial Bus (USB) Specification 3.0." "0,1" hexmask.long.byte 0x4 5.--12. 1. "RESERVED_12_5,Reserved" bitfld.long 0x4 4. "SMI_ON_HOST_E,SMI_ON_HOST SYSTEM ERROR ENABLE For a description of this standard USB register field see the eXtensible Host Controller Interface for Universal Serial Bus (USB) Specification 3.0." "0,1" newline rbitfld.long 0x4 1.--3. "RESERVED_3_1,Reserved" "0,1,2,3,4,5,6,7" bitfld.long 0x4 0. "USB_SMI_ENABLE,USB_SMI_ENABLE For a description of this standard USB register field see the eXtensible Host Controller Interface for Universal Serial Bus (USB) Specification 3.0." "0,1" tree.end tree "DWC_usb3_block_xHCI_Supt_USB20_Prt_Cap (USB3 xHCI Supported Protocol Capability (USB 2.0) Block)" rgroup.long (0x0+0x2192)++0xF line.long 0x0 "SUPTPRT2_DW0,SUPTPRT2_DW0" hexmask.long.byte 0x0 24.--31. 1. "MAJOR_REVISION,MAJOR_REVISION" hexmask.long.byte 0x0 16.--23. 1. "MINOR_REVISION,MINOR_REVISION" hexmask.long.byte 0x0 8.--15. 1. "NEXT_CAPABILITY_POINTER,NEXT_CAPABILITY_POINTER" newline hexmask.long.byte 0x0 0.--7. 1. "CAPABILITY_ID,CAPABILITY_ID For a description of this standard USB register field see the eXtensible Host Controller Interface for Universal Serial Bus (USB) Specification 3.0." line.long 0x4 "SUPTPRT2_DW1,Register SUPTPRT2_DW1" hexmask.long 0x4 0.--31. 1. "NAME_STRING,NAME_STRING For a description of this standard USB register field see the eXtensible Host Controller Interface for Universal Serial Bus (USB) Specification 3.0." line.long 0x8 "SUPTPRT2_DW2,xHCI Supported Protocol Capability_ Data Word 2 For a description of other register fields. see section 7.2 of the eXtensible Host Controller Interface for Universal Serial Bus (USB) Specification 3.0." hexmask.long.byte 0x8 28.--31. 1. "PSIC,PSIC" bitfld.long 0x8 25.--27. "MHD,Hub Depth For a description of this standard USB register field see the eXtensible Host Controller Interface for Universal Serial Bus (USB) Specification 3.0." "0,1,2,3,4,5,6,7" hexmask.long.byte 0x8 21.--24. 1. "RESERVED_24_21,Reserved" newline bitfld.long 0x8 20. "BLC,BESL LPM Capability. When this bit is set to: - 1: The ports described by this xHCI Supported Protocol Capability applies BESL timing to the BESL and BESLD fields of the PORTPMSC and PORTHLPMC registers. - 0: The ports described by this xHCI.." "The ports described by this xHCI Supported..,The ports described by this xHCI Supported.." bitfld.long 0x8 19. "HLC,Compatible Port Offset. Compatible Port Count Refer to Table 7-3 in the Databook." "0,1" bitfld.long 0x8 18. "IHI,IHI" "0,1" newline bitfld.long 0x8 17. "HSO,HSO" "0,1" hexmask.long.byte 0x8 8.--15. 1. "COMPATIBLE_PORT_COUNT,COMPATIBLE_PORT_COUNT For a description of this standard USB register field see the eXtensible Host Controller Interface for Universal Serial Bus (USB) Specification 3.0." hexmask.long.byte 0x8 0.--7. 1. "COMPATIBLE_PORT_OFFSET,COMPATIBLE_PORT_OFFSET For a description of this standard USB register field see the eXtensible Host Controller Interface for Universal Serial Bus (USB) Specification 3.0." line.long 0xC "SUPTPRT2_DW3,Register SUPTPRT2_DW3" hexmask.long 0xC 5.--31. 1. "RESERVED_31_5,Reserved" hexmask.long.byte 0xC 0.--4. 1. "PROTCL_SLT_TY,Protocol Slot Type" tree.end tree "DWC_usb3_block_xHCI_Supt_USB30_Prt_Cap (USB3 xHCI Supported Protocol Capability (USB 3.0) Block)" rgroup.long (0x0+0x2208)++0xF line.long 0x0 "SUPTPRT3_DW0,Register SUPTPRT3_DW0" hexmask.long.byte 0x0 24.--31. 1. "MAJOR_REVISION,MAJOR_REVISION For a description of this standard USB register field see the eXtensible Host Controller Interface for Universal Serial Bus (USB) Specification 3.0." hexmask.long.byte 0x0 16.--23. 1. "MINOR_REVISION,MINOR_REVISION For a description of this standard USB register field see the eXtensible Host Controller Interface for Universal Serial Bus (USB) Specification 3.0." hexmask.long.byte 0x0 8.--15. 1. "NEXT_CAPABILITY_POINTER,NEXT_CAPABILITY_POINTER For a description of this standard USB register field see the eXtensible Host Controller Interface for Universal Serial Bus (USB) Specification 3.0." hexmask.long.byte 0x0 0.--7. 1. "CAPABILITY_ID,CAPABILITY_ID For a description of this standard USB register field see the eXtensible Host Controller Interface for Universal Serial Bus (USB) Specification 3.0." line.long 0x4 "SUPTPRT3_DW1,Register SUPTPRT3_DW1" hexmask.long 0x4 0.--31. 1. "NAME_STRING,NAME_STRING For a description of this standard USB register field see the eXtensible Host Controller Interface for Universal Serial Bus (USB) Specification 3.0." line.long 0x8 "SUPTPRT3_DW2,SUPTPRT3_DW2 For a description of this standard USB register field. see the eXtensible Host Controller Interface for Universal Serial Bus (USB) Specification 3.0." hexmask.long.byte 0x8 28.--31. 1. "PSIC,PSIC" bitfld.long 0x8 25.--27. "MHD,Hub Depth For a description of this standard USB register field see the eXtensible Host Controller Interface for Universal Serial Bus (USB) Specification 3.0." "0,1,2,3,4,5,6,7" hexmask.long.byte 0x8 8.--15. 1. "COMPATIBLE_PORT_COUNT,COMPATIBLE_PORT_COUNT For a description of this standard USB register field see the eXtensible Host Controller Interface for Universal Serial Bus (USB) Specification 3.0." hexmask.long.byte 0x8 0.--7. 1. "COMPATIBLE_PORT_OFFSET,COMPATIBLE_PORT_OFFSET For a description of this standard USB register field see the eXtensible Host Controller Interface for Universal Serial Bus (USB) Specification 3.0." line.long 0xC "SUPTPRT3_DW3,SUPTPRT3_DW3" hexmask.long 0xC 5.--31. 1. "RESERVED_31_5,Reserved" hexmask.long.byte 0xC 0.--4. 1. "PROTCL_SLT_TY,Protocol Slot Type" tree.end tree "DWC_usb3_block_Debug_Capability_Structure (USB3 Debug Capability Structure Block)" rgroup.long (0x0+0x2224)++0x3 line.long 0x0 "DCID,DCID" hexmask.long.word 0x0 21.--31. 1. "RESERVED_31_21,Reserved" hexmask.long.byte 0x0 16.--20. 1. "DCERSTMAX,DCERSTMAX" hexmask.long.byte 0x0 8.--15. 1. "NEXT_CAPABILITY_POINTER,NEXT_CAPABILITY_POINTER" hexmask.long.byte 0x0 0.--7. 1. "CAPABILITY_ID,CAPABILITY_ID" group.long (0x4+0x2224)++0x7 line.long 0x0 "DCDB,Register DCDB" hexmask.long.word 0x0 16.--31. 1. "RESERVED_31_16,Reserved" hexmask.long.byte 0x0 8.--15. 1. "DBTARGET,DBTARGET" hexmask.long.byte 0x0 0.--7. 1. "RESERVED_7_0,Reserved" line.long 0x4 "DCERSTSZ,DCERSTSZ" hexmask.long.word 0x4 16.--31. 1. "RESERVED_31_16,Reserved" hexmask.long.word 0x4 0.--15. 1. "ERS_TABLE_SIZE,ERS_TABLE_SIZE" group.long (0x10+0x2224)++0x13 line.long 0x0 "DCERSTBA_LO,DCERSTBA_LO" hexmask.long 0x0 4.--31. 1. "ERS_TABLE_BAR,ERS_TABLE_BAR" hexmask.long.byte 0x0 0.--3. 1. "RESERVED_3_0,Reserved" line.long 0x4 "DCERSTBA_HI,Register DCERSTBA_HI" hexmask.long 0x4 0.--31. 1. "ERS_TABLE_BAR,ERS_TABLE_BAR" line.long 0x8 "DCERDP_LO,DCERDP_LO" hexmask.long 0x8 4.--31. 1. "DEQUEUE_POINTER,DEQUEUE_POINTER" rbitfld.long 0x8 3. "RESERVED_3,Reserved" "0,1" bitfld.long 0x8 0.--2. "DESI,DESI" "0,1,2,3,4,5,6,7" line.long 0xC "DCERDP_HI,DCERDP_HI" hexmask.long 0xC 0.--31. 1. "DEQUEUE_POINTER,DEQUEUE_POINTER" line.long 0x10 "DCCTRL,DCCTRL" bitfld.long 0x10 31. "DCE,DCE" "0,1" hexmask.long.byte 0x10 24.--30. 1. "DEVICE_ADDRESS,DEVICE_ADDRESS" hexmask.long.byte 0x10 16.--23. 1. "DEBUG_MAX_BURST_SIZE,DEBUG_PROTOCOL" hexmask.long.word 0x10 5.--15. 1. "RESERVED_15_5,Reserved" newline bitfld.long 0x10 4. "DRC,DRC" "0,1" bitfld.long 0x10 3. "HIT,HIT" "0,1" bitfld.long 0x10 2. "HOT,HOT" "0,1" bitfld.long 0x10 1. "LSE,LSE" "0,1" newline rbitfld.long 0x10 0. "DCR,DCR" "0,1" rgroup.long (0x24+0x2224)++0x3 line.long 0x0 "DCST,DCST" hexmask.long.byte 0x0 24.--31. 1. "DEBUG_PORT_NUMBER,DEBUG_PORT_NUMBER" hexmask.long.tbyte 0x0 2.--23. 1. "RESERVED_23_2,Reserved" bitfld.long 0x0 1. "SBR,SBR" "0,1" bitfld.long 0x0 0. "ER,ER" "0,1" group.long (0x28+0x2224)++0x3 line.long 0x0 "DCPORTSC,Register DCPORTSC" hexmask.long.byte 0x0 24.--31. 1. "RESERVED_31_24,Reserved" bitfld.long 0x0 23. "CEC,CEC" "0,1" bitfld.long 0x0 22. "PLC,PLC" "0,1" bitfld.long 0x0 21. "PRC,PRC" "0,1" newline rbitfld.long 0x0 18.--20. "RESERVED_20_18,Reserved" "0,1,2,3,4,5,6,7" bitfld.long 0x0 17. "CSC,CSC" "0,1" rbitfld.long 0x0 14.--16. "RESERVED_16_14,Reserved" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x0 10.--13. 1. "PORTSPEED,PORTSPEED" newline rbitfld.long 0x0 9. "RESERVED_9,Reserved" "0,1" hexmask.long.byte 0x0 5.--8. 1. "PLS,PLS" rbitfld.long 0x0 4. "PR,PR" "0,1" rbitfld.long 0x0 2.--3. "RESERVED_3_2,Reserved" "0,1,2,3" newline bitfld.long 0x0 1. "PED,PED" "0,1" rbitfld.long 0x0 0. "CCS,CCS" "0,1" group.long (0x30+0x2224)++0xF line.long 0x0 "DCCP_LO,DCCP_LO" hexmask.long 0x0 4.--31. 1. "DCCPR,DCCPR" hexmask.long.byte 0x0 0.--3. 1. "RESERVED_3_0,Reserved" line.long 0x4 "DCCP_HI,Register DCCP_HI" hexmask.long 0x4 0.--31. 1. "DCCPR,DCCPR" line.long 0x8 "DCDDI1,Register DCDDI1" hexmask.long.word 0x8 16.--31. 1. "VENDORID,VENDORID" hexmask.long.byte 0x8 8.--15. 1. "RESERVED_15_8,Reserved" hexmask.long.byte 0x8 0.--7. 1. "DBCPROTOCOL,DBCPROTOCOL" line.long 0xC "DCDDI2,Register DCDDI2" hexmask.long.word 0xC 16.--31. 1. "DEVICEREV,DEVICEREV" hexmask.long.word 0xC 0.--15. 1. "PRODUCTID,PRODUCTID" tree.end tree.end tree "USB1_NCR" base ad:0xF122D000 group.long 0x0++0x3 line.long 0x0 "INTEN,INTEN" bitfld.long 0x0 15. "INTEN_RSVD8,INTEN_RSVD8" "0,1" newline bitfld.long 0x0 14. "INTEN_RSVD7,INTEN_RSVD7" "0,1" bitfld.long 0x0 13. "INTEN_RSVD6,INTEN_RSVD6" "0,1" newline bitfld.long 0x0 12. "INTEN_RSVD5,INTEN_RSVD5" "0,1" bitfld.long 0x0 11. "INTEN_RSVD4,INTEN_RSVD4" "0,1" newline bitfld.long 0x0 10. "INTEN_RSVD3,INTEN_RSVD3" "0,1" bitfld.long 0x0 9. "INTEN_RSVD2,INTEN_RSVD2" "0,1" newline bitfld.long 0x0 8. "INTEN_RSVD1,INTEN_RSVD1" "0,1" bitfld.long 0x0 7. "INTEN_RSVD0,INTEN_RSVD0" "0,1" newline bitfld.long 0x0 6. "INTEN_WAKEUP,WAKEUP interrupt enalbe 1:enable 0:disable" "disable,enable" bitfld.long 0x0 5. "INTEN_HOST_LEGACY_SMI_INTERRUPT,HOST_LEGACY_SMI_INTERRUPT enable 1:enable 0:disable" "disable,enable" newline bitfld.long 0x0 4. "INTEN_PME_GENERATION,Power Management Event (PME) interrupt enable 1: enable 0:disable" "disable,enable" bitfld.long 0x0 3. "INTEN_BC_INTERRUPT,Battery Charger interrupt enable 1:enable 0:disable" "disable,enable" newline bitfld.long 0x0 2. "INTEN_CHGDET,Battery Charger Detect interrupt 1:enable 0:disable" "disable,enable" bitfld.long 0x0 1. "INTEN_HOST_SYSTEM_ERR,host_system_err interrupt enable. host_system_err can occur when the host controller encounters an 'Error' response in the AHB the AXI or the Native Master Bus. 1:enable 0:disable" "disable,enable" newline bitfld.long 0x0 0. "INTEN_CORE_INTERRUPT,USB CORE INTERRUPT enable 1:enable 0:disable" "disable,enable" group.long 0x10++0x7 line.long 0x0 "CTRL_0,CTRL_0" bitfld.long 0x0 29.--31. "DEBOUNCECTL,Enables Bus Filters for the following UTMI/ULPI signals and PIPE3PowerControl input signal from the PHY. utmiotg_vbusvalid utmisrp_bvalid pipe3_PowerPresent" "0,1,2,3,4,5,6,7" bitfld.long 0x0 28. "WAKEBYIDCHG,WAKEBYIDCHG" "0,1" newline bitfld.long 0x0 27. "WAKEBYVBUSCHG,WAKEBYVBUSCHG" "0,1" bitfld.long 0x0 26. "WAKEBYDPDMCHG,WAKEBYDPDMCHG" "0,1" newline bitfld.long 0x0 25. "WAKEBYREMOTEWAKE,WAKEBYREMOTEWAKE" "0,1" bitfld.long 0x0 24. "WAKEBYHSDSCNNT,WAKEBYHSDSCNNT" "0,1" newline bitfld.long 0x0 23. "WAKEBYHSCNNT,WAKEBYHSCNNT" "0,1" bitfld.long 0x0 22. "WAKEBYOC,WAKEBYOC" "0,1" newline bitfld.long 0x0 21. "XHC_BME,This signal is used to disable the bus mastering capability of the xHC. In a PCI system it comes from the Bus Master Enable (BME) bit of the Device Control Register in the PCI Configuration register space. 1'b0: Bus mastering capability is.." "Bus mastering capability is disabled,Bus mastering capability is enabled" hexmask.long.byte 0x0 17.--20. 1. "BUS_FILTER_BYPASS,Bus Filter Bypass. Disables the internal bus filters that are enabled by DWC_USB3_EN_BUS_FILTERS coreConsultant parameter. This static signal is present only when DWC_USB3_EN_BUS_FILTERS is 1. It is expected that this signal is set or.." newline hexmask.long.byte 0x0 11.--16. 1. "FLADJ_30MHZ_REG,HS Jitter Adjustment. Indicates the correction required to accommodate mac3 clock and utmi clock jitter to measure 125 's duration. With fladj_30mhz_reg tied to zero the high speed 125us micro-frame is counted for 123933ns. You must.." bitfld.long 0x0 10. "HOST_LEGACY_SMI_BAR_WR,PCI Base Address register (BAR) write: one clock pulse. The PCIe interface need to generate one clock pulse during PCIe Base Address register (BAR) write. Active State: High" "0,1" newline bitfld.long 0x0 9. "HOST_LEGACY_SMI_PCI_CMD_REG_WR,PCI command register write: one clock pulse. The PCIe interface needs to generate one clock pulse during PCIe command register write. Tie this low if you are not using Legacy support. Active State: High" "0,1" bitfld.long 0x0 8. "HOST_MSI_ENABLE,This enables the pulse type interrupt signal (one bus clock cycle) 'interrupt' port instead of level-sensitive interrupt. When interfacing to PCIe this allows you to easily map 'interrupt' to MSI in the PCIe controller. MSI can only be.." "0,1" newline bitfld.long 0x0 7. "HOST_PORT_POWER_CONTROL_PRESENT,This port defines the bit [3] of Capability Parameters (HCCPARAMS). Change the PPC value through the pin Port Power Control (PPC). This indicates whether the host controller implementation includes port power control..." "Indicates that the port does not have port power..,Indicates that the port has port power switches" bitfld.long 0x0 6. "DISRXDETU3RXDET,DisRxDetU3RxDet of USB 3.0 SS Ports This input signal requests the controller to stop issuing more PHY commands and release the PIPE ownership. The controller acknowledges this request by asserting the DisRxDetU3RxDet_ack signal. This.." "0,1" newline bitfld.long 0x0 5. "STARTRXDETU3RXDET,StartRxdetU3RxDet of USB 3.0 SS Ports This signal is the Start Receiver Detection in U3/Rx.Detect (StartRxdetU3RxDet). If DisRxDetU3RxDet is set and the link is in either U3 or Rx.Detect state the controller starts receiver detection.." "0,1" bitfld.long 0x0 4. "HOST_U3_PORT_DISABLE,USB 3.0 SS Port Disable control. 0: Port Enabled 1: Port Disabled This signal when '1' stops reporting connect/disconnect events the port and keeps the port in disabled state. This could be used for security reasons where.." "Port Enabled,Port Disabled" newline bitfld.long 0x0 3. "HOST_U2_PORT_DISABLE,USB 2.0 Port Disable control. 0: Port Enabled 1: Port Disabled When '1' this signal stops reporting connect/disconnect events the port and keeps the port in disabled state. This could be used for security reasons where.." "Port Enabled,Port Disabled When '1'" bitfld.long 0x0 1.--2. "HUB_PORT_PERM_ATTACH,Indicates if the device attached to a downstream port is permanently attached or not. 0: Not permanently attached 1: Permanently attached The lower bits are for USB 2.0 ports and the higher bits are for USB 3.0 SS ports:.." "Not permanently attached,Permanently attached,?,?" newline bitfld.long 0x0 0. "PME_EN,In host mode when hibernation is disabled (GCTL.GblHibernationEn=0) this input enables the controller to generate the pme_generation signal. unused in: Device mode Host mode when hibernation is enabled (GCTL.GblHibernationEn=1)" "0,1" line.long 0x4 "CTRL_1,CTRL_1" hexmask.long.word 0x4 22.--31. 1. "RSVD0,RSVD0" hexmask.long.byte 0x4 18.--21. 1. "RAM_DEBUG_SEL,ram_debug_sel: 0x0-0x7: internal RAM0 0x8-0xB:internal RAM1 0xC-0xF:internal RAM2" newline bitfld.long 0x4 16.--17. "CTRL_REF_SEL,ctrl_ref_clk select: 0 : i_ref_alt_clk_p 1 : i_ref_alt_clk_p 2: i_suspend_clk 3:i_ref_output_clk" "i_ref_alt_clk_p,i_ref_alt_clk_p,i_suspend_clk,i_ref_output_clk" hexmask.long.word 0x4 6.--15. 1. "DRVRSM32KCTRL1,DRVRSM32KCTRL1" newline hexmask.long.byte 0x4 1.--5. 1. "DRVRSM32KCTRL0,DRVRSM32KCTRL0" bitfld.long 0x4 0. "DRVRSM32KEN,DRVRSM32KEN" "0,1" repeat 6. (list 0x2 0x3 0x4 0x5 0x6 0x7 )(list 0x0 0x4 0x8 0xC 0x10 0x14 ) group.long ($2+0x18)++0x3 line.long 0x0 "CTRL_$1,CTRL_2" hexmask.long 0x0 0.--31. 1. "RSVD0,RSVD0" repeat.end group.long 0x80++0x3 line.long 0x0 "INTR,INTR" bitfld.long 0x0 15. "INTR_RSVD8,INTR_RSVD8" "0,1" newline bitfld.long 0x0 14. "INTR_RSVD7,INTR_RSVD7" "0,1" bitfld.long 0x0 13. "INTR_RSVD6,INTR_RSVD6" "0,1" newline bitfld.long 0x0 12. "INTR_RSVD5,INTR_RSVD5" "0,1" bitfld.long 0x0 11. "INTR_RSVD4,INTR_RSVD4" "0,1" newline bitfld.long 0x0 10. "INTR_RSVD3,INTR_RSVD3" "0,1" bitfld.long 0x0 9. "INTR_RSVD2,INTR_RSVD2" "0,1" newline bitfld.long 0x0 8. "INTR_RSVD1,INTR_RSVD1" "0,1" bitfld.long 0x0 7. "INTR_RSVD0,INTR_RSVD0" "0,1" newline bitfld.long 0x0 6. "INTR_WAKEUP,INTR_WAKEUP" "0,1" bitfld.long 0x0 5. "INTR_HOST_LEGACY_SMI_INTERRUPT,INTR_HOST_LEGACY_SMI_INTERRUPT" "0,1" newline bitfld.long 0x0 4. "INTR_PME_GENERATION,INTR_PME_GENERATION" "0,1" bitfld.long 0x0 3. "INTR_BC_INTERRUPT,INTR_BC_INTERRUPT" "0,1" newline bitfld.long 0x0 2. "INTR_CHGDET,INTR_CHGDET" "0,1" bitfld.long 0x0 1. "INTR_HOST_SYSTEM_ERR,INTR_HOST_SYSTEM_ERR" "0,1" newline bitfld.long 0x0 0. "INTR_CORE_INTERRUPT,INTR_CORE_INTERRUPT" "0,1" rgroup.long 0x90++0x7 line.long 0x0 "STS_0,STS_0" bitfld.long 0x0 1. "SUSPEND_CLK_ACTIVE,indicate the SUSPEND_CLK is ACTIVE or not 1: active 0:inactive" "inactive,active" newline bitfld.long 0x0 0. "ACLK_ACTIVE,indicate the bus clk is ACTIVE or not 1: active 0:inactive" "inactive,active" line.long 0x4 "STS_1,STS_1" bitfld.long 0x4 17. "DISRXDETU3RXDET_ACK,DisRxDetU3RxDet_ack of USB 3.0 SS Ports This signal is an acknowledgment of DisRxDetU3RxDet. When this signal is 1'b1 the controller releases the ownership of the the PIPE interface and does not issue PHY commands to the PIPE.." "0,1" newline bitfld.long 0x4 14.--16. "CLK_GATE_CTRL,Clock gating control This signal indicates the clock gating controls used for gating RAM and bus clocks. Bit[0] is gating control for bus_clk bit[1] and bit[2] is for ram_clk_in. This output must be used only for debug purposes." "0,1,2,3,4,5,6,7" bitfld.long 0x4 12.--13. "OPERATIONAL_MODE,Port Capability Direction 2'b01: for default Host operation (Power on value allowed only when DWC_USB3_MODE=1) 2'b10: for default Device operation (Power on value allowed only when DWC_USB3_MODE!=1)" "?,for default Host operation,for default Device operation,?" newline hexmask.long.word 0x4 0.--11. 1. "HOST_CURRENT_BELT,Current BELT Value. This signal indicates the minimum value of all received BELT values and the BELT that is set by the Set LTV command. This signal is valid only in Host mode." repeat 9. (list 0x2 0x3 0x4 0x5 0x7 0x8 0x9 0xA 0xB )(list 0x0 0x4 0x8 0xC 0x14 0x18 0x1C 0x20 0x24 ) rgroup.long ($2+0x98)++0x3 line.long 0x0 "STS_$1,STS_2" hexmask.long 0x0 0.--31. 1. "LOGIC_ANALYZER_TRACE_0,LOGIC_ANALYZER_TRACE_0" repeat.end rgroup.long 0xA8++0x3 line.long 0x0 "STS_6,STS_6" bitfld.long 0x0 0.--2. "DEBUG_2,DEBUG_2" "0,1,2,3,4,5,6,7" tree.end tree "USB_PHY1" base ad:0xF1240000 rgroup.word 0x0++0x1 line.word 0x0 "SUP_DIG_IDCODE_LO,Low 16 bits of IDCODE" newline hexmask.word 0x0 0.--15. 1. "DATA," rgroup.word 0x4++0x1 line.word 0x0 "SUP_DIG_IDCODE_HI,High 16 bits of IDCODE" newline hexmask.word 0x0 0.--15. 1. "DATA," group.word 0x8++0x1 line.word 0x0 "SUP_DIG_DEBUG,Debug controls" newline hexmask.word 0x0 7.--15. 1. "RESERVED_15_7,Reserved for Future use" newline bitfld.word 0x0 5.--6. "DTB_SEL,The lane DTB's are OR'd together with the support DTB signals selected with the below encodings 0 - none 1 - reset_ctl DTB output 2 - scope DTB output 3 - rtune DTB output" "none,reset_ctl DTB output,scope DTB output,rtune DTB output" newline hexmask.word.byte 0x0 0.--4. 1. "TX_VREF_SEL," group.word 0xC++0x1 line.word 0x0 "SUP_DIG_RTUNE_DEBUG,Resistor tuning debug controls" newline rbitfld.word 0x0 15. "RESERVED_15_15,Reserved for Future use" "0,1" newline hexmask.word 0x0 5.--14. 1. "VALUE,Value to use when triggering SET_VAL field only the 6 LSB's are used when setting rx or tx cal values (USER2 - read-write and custom)" newline bitfld.word 0x0 3.--4. "TYPE,Type of manual tuning or register read/write to execute 0 - ADC or read/write rt_value 1 - Rx tune or read/write rx_cal_val (only 6 bits) 2 - Tx tune or read/write tx_cal_val (only 6 bits) 3 - Resref detect (no affect when triggering SET_VAL.." "ADC,Rx tune,read-write and custom),Resref detect" newline bitfld.word 0x0 2. "SET_VAL,Set value Write to a 1 to manually write the register specified by the TYPE field to the value in the VALUE field (USER2 - read-write and custom)" "0,1" newline bitfld.word 0x0 1. "MAN_TUNE,Write to a 1 to do a manual tuning specified by TYPE field starting a manual tune while a tune is currently running can cause unpredictable results. For use only when you know the state of the rtune circuit. (USER2 - read-write and custom)" "0,1" newline bitfld.word 0x0 0. "FLIP_COMP,Invert analog comparator output (USER2 - read-write and custom)" "0,1" rgroup.word 0x10++0x1 line.word 0x0 "SUP_DIG_RTUNE_STAT,Resistor tuning register status" newline hexmask.word.byte 0x0 10.--15. 1. "RESERVED_15_10,Reserved for Future use" newline hexmask.word 0x0 0.--9. 1. "STAT,Current value of the register specifed by the TYPE field in the debug control register. Set the TYPE field in the DEBUG register and then do a read of this register. (RU - read-only volatile)" group.word 0x14++0x1 line.word 0x0 "SUP_DIG_SS_PHASE,Current MPLL phase selector value" newline bitfld.word 0x0 13.--15. "REF_SEL_DIV,Reference Divisor to get better resolution and lower PPM errors when synthesizing from a non-integer reference clock. NOTE: Default value is 4. One is added in hardware to give a range of 1 to 8. (volatile and 2 reads needed to read value)" "0,1,2,3,4,5,6,7" newline bitfld.word 0x0 12. "PH_SEL,Phase Mixer Clock select. 1: is pmix. 0 is VCO. (volatile and 2 reads needed to read value)" "?,is pmix" newline bitfld.word 0x0 11. "ZERO_FREQ,Zero frequency register. NOTES: Must be set for PHASE writes to stick (volatile and 2 reads needed to read value)" "0,1" newline hexmask.word 0x0 2.--10. 1. "VAL,Phase value from zero reference (volatile and 2 reads needed to read value)" newline bitfld.word 0x0 0.--1. "DTHR,Bits below the useful resolution (volatile and 2 reads needed to read value)" "0,1,2,3" group.word 0x18++0x1 line.word 0x0 "SUP_DIG_SS_FREQ,Frequency Control for Spread Spectrum" newline rbitfld.word 0x0 15. "RESERVED_15_15,Reserved for Future use" "0,1" newline bitfld.word 0x0 14. "FREQ_OVRD,Frequency Reigster Override. NOTE: Must be set for PHASE writes to stick (volatile and 2 reads needed to read value)" "0,1" newline hexmask.word.byte 0x0 7.--13. 1. "FREQ_PK,Peak Frequency Value (for changing direction) (volatile and 2 reads needed to read value)" newline hexmask.word.byte 0x0 0.--6. 1. "FREQ_CNT_INIT,Initial Frequency Counter Value (volatile and 2 reads needed to read value)" group.word 0x1C++0x1 line.word 0x0 "SUP_DIG_HSP_SS_PHASE,Current HSP_PMIX SSC phase sel value" newline hexmask.word.byte 0x0 11.--15. 1. "RESERVED_15_11,Reserved for Future use" newline hexmask.word.byte 0x0 4.--10. 1. "VAL,SSC phase value from zero reference (volatile and 2 reads needed to read value)" newline hexmask.word.byte 0x0 0.--3. 1. "DTHR,Bits below the useful resolution (volatile and 2 reads needed to read value)" group.word 0x20++0x1 line.word 0x0 "SUP_DIG_MPLL_CNT_CTL,Control for fixed or variable MPLL Count Selection" newline hexmask.word 0x0 1.--15. 1. "RESERVED_15_1,Reserved for Future use" newline bitfld.word 0x0 0. "VAR_CNT_EN,Selects variable count when enabled (Default = fixed count)" "0,1" group.word 0x24++0x1 line.word 0x0 "SUP_DIG_CR_PARA_ALU_CTL,Control for CR Parallel ALU access" newline hexmask.word 0x0 5.--15. 1. "RESERVED_15_5,Reserved for Future use" newline hexmask.word.byte 0x0 1.--4. 1. "CR_PARA_ALU_OPCODE,Opcode for the ALU when CR para access is enabled. Valid opcodes are as follows: 0 - Zero the accumulator 1 - Add control register read result to accumulator 2 - Add control register write data to accumulator 3 - Shift accumulator left.." newline bitfld.word 0x0 0. "CR_PARA_ALU_ACCESS_EN,Enable access to the ALU through the CR parallel bus." "0,1" rgroup.word 0x28++0x1 line.word 0x0 "SUP_DIG_CR_PARA_ALU_FLAGS,Flags from the ALU when CR para access is enabled." newline hexmask.word 0x0 4.--15. 1. "RESERVED_15_4,Reserved for Future use" newline hexmask.word.byte 0x0 0.--3. 1. "DATA,Flags from the ALU when CR para access is enabled. Valid ALU flags: 0 - Signedness used for next ADD_PHSEL command. (1=signed 0=unsigned) 1 - Signedness for ADD_PHSEL command has been chosen by a previous ADD_PHSEL command. 2 - Error detected.." group.word 0x40++0x1 line.word 0x0 "SUP_DIG_ATEOVRD,Override values for incoming controls from ASIC" newline hexmask.word 0x0 3.--15. 1. "RESERVED_15_3,Reserved for Future use" newline bitfld.word 0x0 2. "ATEOVRD_EN,Override enable for ATE signals. NOTE: This register is only accessible through cregs. Does not retain state during reset or ATPG. (USER2 - read-write and custom)" "0,1" newline bitfld.word 0x0 1. "REF_USB2_EN,Override value for USB HSP PHY ref_clk enable. (USER2 - read-write and custom)" "0,1" newline bitfld.word 0x0 0. "REF_CLKDIV2,Override value for SSP ref_clk pre-scaler. (USER2 - read-write and custom)" "0,1" group.word 0x44++0x1 line.word 0x0 "SUP_DIG_MPLL_OVRD_IN_LO,Override values for incoming RTUNE and MPLL controls from ASIC" newline bitfld.word 0x0 15. "RES_ACK_IN_OVRD,Override enable for res_ack_in" "0,1" newline bitfld.word 0x0 14. "RES_ACK_IN,Override value for res_ack_in" "0,1" newline bitfld.word 0x0 13. "RES_REQ_IN_OVRD,Override enable for res_req_in" "0,1" newline bitfld.word 0x0 12. "RES_REQ_IN,Override value for res_req_in" "0,1" newline bitfld.word 0x0 11. "RTUNE_REQ_OVRD,Override enable for rtune_req" "0,1" newline bitfld.word 0x0 10. "RTUNE_REQ,Override value for rtune_req" "0,1" newline bitfld.word 0x0 9. "MPLL_MULTIPLIER_OVRD,Override enable for mpll_multipler" "0,1" newline hexmask.word.byte 0x0 2.--8. 1. "MPLL_MULTIPLIER,Override value for mpll_multipler" newline bitfld.word 0x0 1. "MPLL_EN_OVRD,Override enable for mpll_en" "0,1" newline bitfld.word 0x0 0. "MPLL_EN,Override value for mpll_en" "0,1" group.word 0x48++0x1 line.word 0x0 "SUP_DIG_MPLL_OVRD_IN_HI,Override values for incoming VBOOST LVL and MPLL controls from ASIC" newline bitfld.word 0x0 13.--15. "TX_VBOOST_LVL,Override value for tx_vboost_lvl. Override enabled using LEVEL_EN from LEVEL_OVRD_IN register." "0,1,2,3,4,5,6,7" newline bitfld.word 0x0 12. "MPLL_REFSSC_CLK_EN_OVRD,Override enable for mpll_refssc_clk_en" "0,1" newline bitfld.word 0x0 11. "MPLL_REFSSC_CLK_EN,Override value for mpll_refssc_clk_en" "0,1" newline bitfld.word 0x0 10. "MPLL_RST,Reset the MPLL state machine Writing the register with this bit set will reset the MPLL power up/down FSM regardless of the current state of the register bit." "0,1" newline bitfld.word 0x0 9. "FSEL_OVRD,Override enable for fsel[2:0]" "0,1" newline bitfld.word 0x0 6.--8. "FSEL,Override value for fsel [2:0]" "0,1,2,3,4,5,6,7" newline bitfld.word 0x0 5. "MPLL_WORD_CLK_EN_OVRD,Override enable for mpll_word_clk_en" "0,1" newline bitfld.word 0x0 4. "MPLL_WORD_CLK_EN,Override value for mpll_word_clk_en" "0,1" newline bitfld.word 0x0 3. "MPLL_DWORD_CLK_EN_OVRD,Override enable for mpll_dword_clk_en" "0,1" newline bitfld.word 0x0 2. "MPLL_DWORD_CLK_EN,Override value for mpll_dword_clk_en" "0,1" newline bitfld.word 0x0 1. "MPLL_QWORD_CLK_EN_OVRD,Override enable for mpll_qword_clk_en" "0,1" newline bitfld.word 0x0 0. "MPLL_QWORD_CLK_EN,Override value for mpll_qword_clk_en" "0,1" group.word 0x4C++0x1 line.word 0x0 "SUP_DIG_SSC_OVRD_IN,Override values for incoming SSC controls from ASIC" newline rbitfld.word 0x0 14.--15. "RESERVED_15_14,Reserved for Future use" "0,1,2,3" newline bitfld.word 0x0 13. "SSC_OVRD_IN_EN,Override enable for Spread Spectrum generator." "0,1" newline bitfld.word 0x0 12. "SSC_EN,Override value for SSC enable." "0,1" newline bitfld.word 0x0 9.--11. "SSC_RANGE,Override value for SSC modulation range." "0,1,2,3,4,5,6,7" newline hexmask.word 0x0 0.--8. 1. "SSC_REF_CLK_SEL,Override value for reference clock scaling" group.word 0x50++0x1 line.word 0x0 "SUP_DIG_BS_OVRD_IN,Override values for incoming BS controls from ASIC" newline hexmask.word.byte 0x0 12.--15. 1. "RESERVED_15_12,Reserved for Future use" newline bitfld.word 0x0 11. "EN,Enable override values for all inputs controlled by this register" "0,1" newline bitfld.word 0x0 10. "INVERT,Override value for bs_invert" "0,1" newline bitfld.word 0x0 9. "INIT,Override value for bs_init" "0,1" newline bitfld.word 0x0 8. "HIGHZ,Override value for bs_highz" "0,1" newline bitfld.word 0x0 7. "CLAMP,Override value for bs_clamp" "0,1" newline bitfld.word 0x0 6. "EXTEST_AC,Override value for bs_extest_ac" "0,1" newline bitfld.word 0x0 5. "EXTEST,Override value for bs_extest" "0,1" newline bitfld.word 0x0 4. "PRELOAD,Override value for bs_preload" "0,1" newline bitfld.word 0x0 3. "UPDATE_DR,Override value for bs_update_dr" "0,1" newline bitfld.word 0x0 2. "CAPTURE_DR,Override value for bs_capture_dr" "0,1" newline bitfld.word 0x0 1. "SHIFT_DR,Override value for bs_shift_dr" "0,1" newline bitfld.word 0x0 0. "IN,Override value for bs_in" "0,1" group.word 0x54++0x1 line.word 0x0 "SUP_DIG_LEVEL_OVRD_IN,Override values for acjt_level and los_level" newline bitfld.word 0x0 13.--15. "LOS_BIAS,Override value for los_bias" "0,1,2,3,4,5,6,7" newline bitfld.word 0x0 12. "MPLL_HALF_RATE_OVRD,Enable override value for mpll_half_rate" "0,1" newline bitfld.word 0x0 11. "MPLL_HALF_RATE,Override value for mpll_half_rate" "0,1" newline bitfld.word 0x0 10. "LEVEL_EN,Enable override values for tx_vboost_lvl/los_bias/los_level/acjt_level inputs controlled by this and MPLL_OVRD_IN_HI registers" "0,1" newline hexmask.word.byte 0x0 5.--9. 1. "ACJT_LEVEL,Override value for acjt_level" newline hexmask.word.byte 0x0 0.--4. 1. "LOS_LEVEL,Override value for los_level" group.word 0x58++0x1 line.word 0x0 "SUP_DIG_SUP_OVRD_OUT,Override values for support block" newline hexmask.word.byte 0x0 10.--15. 1. "RESERVED_15_10,Reserved for Future use" newline bitfld.word 0x0 9. "MPLL_STATE_OVRD,Override enable for mpll_state output" "0,1" newline bitfld.word 0x0 8. "MPLL_STATE,Override value for mpll_state output" "0,1" newline bitfld.word 0x0 7. "BS_OUT_OVRD,Override enable for bs_out output" "0,1" newline bitfld.word 0x0 6. "BS_OUT,Override value for bs_out output" "0,1" newline bitfld.word 0x0 5. "RTUNE_ACK_OVRD,Override enable for rtune_ack output" "0,1" newline bitfld.word 0x0 4. "RTUNE_ACK,Override value for rtune_ack output" "0,1" newline bitfld.word 0x0 3. "RES_REQ_OUT_OVRD,Override enable for res_req_out output" "0,1" newline bitfld.word 0x0 2. "RES_REQ_OUT,Override value for res_req_out output" "0,1" newline bitfld.word 0x0 1. "RES_ACK_OUT_OVRD,Override enable for res_ack_out output" "0,1" newline bitfld.word 0x0 0. "RES_ACK_OUT,Override value for res_ack_out output" "0,1" rgroup.word 0x5C++0x1 line.word 0x0 "SUP_DIG_MPLL_ASIC_IN,Current values for incoming MPLL controls from ASIC" newline bitfld.word 0x0 15. "RESERVED_15_15,Reserved for Future use" "0,1" newline bitfld.word 0x0 14. "MPLL_REFSSC_CLK_EN,Value from ASIC for mpll_refssc_clk_en (RU - read-only volatile)" "0,1" newline bitfld.word 0x0 13. "MPLL_WORD_CLK_EN,Value from ASIC for mpll_word_clk_en (RU - read-only volatile)" "0,1" newline bitfld.word 0x0 12. "MPLL_DWORD_CLK_EN,Value from ASIC for mpll_dword_clk_en (RU - read-only volatile)" "0,1" newline bitfld.word 0x0 11. "MPLL_QWORD_CLK_EN,Value from ASIC for mpll_qword_clk_en (RU - read-only volatile)" "0,1" newline bitfld.word 0x0 10. "RES_ACK_IN,Value from ASIC for res_ack_in (RU - read-only volatile)" "0,1" newline bitfld.word 0x0 9. "RES_REQ_IN,Value from ASIC for res_req_in (RU - read-only volatile)" "0,1" newline bitfld.word 0x0 8. "RTUNE_REQ,Value from ASIC for rtune_req (RU - read-only volatile)" "0,1" newline hexmask.word.byte 0x0 1.--7. 1. "MPLL_MULTIPLIER,Value from ASIC for mpll_multiplier (RU - read-only volatile)" newline bitfld.word 0x0 0. "MPLL_EN,Value from ASIC for mpll_en (RU - read-only volatile)" "0,1" rgroup.word 0x60++0x1 line.word 0x0 "SUP_DIG_BS_ASIC_IN,Current values for incoming boundary scan controls from ASIC" newline bitfld.word 0x0 14.--15. "RESERVED_15_14,Reserved for Future use" "0,1,2,3" newline bitfld.word 0x0 11.--13. "TX_VBOOST_LVL,Value from ASIC for tx_vboost_lvl -- Not as bs_* signal but we're out of bits. (RU - read-only volatile)" "0,1,2,3,4,5,6,7" newline bitfld.word 0x0 10. "INVERT,Value from ASIC for bs_invert (RU - read-only volatile)" "0,1" newline bitfld.word 0x0 9. "INIT,Value from ASIC for bs_init (RU - read-only volatile)" "0,1" newline bitfld.word 0x0 8. "HIGHZ,Value from ASIC for bs_highz (RU - read-only volatile)" "0,1" newline bitfld.word 0x0 7. "CLAMP,Value from ASIC for bs_clamp (RU - read-only volatile)" "0,1" newline bitfld.word 0x0 6. "EXTEST_AC,Value from ASIC for bs_extest_ac (RU - read-only volatile)" "0,1" newline bitfld.word 0x0 5. "EXTEST,Value from ASIC for bs_extest (RU - read-only volatile)" "0,1" newline bitfld.word 0x0 4. "PRELOAD,Value from ASIC for bs_preload (RU - read-only volatile)" "0,1" newline bitfld.word 0x0 3. "UPDATE_DR,Value from ASIC for bs_update_dr (RU - read-only volatile)" "0,1" newline bitfld.word 0x0 2. "CAPTURE_DR,Value from ASIC for bs_capture_dr (RU - read-only volatile)" "0,1" newline bitfld.word 0x0 1. "SHIFT_DR,Value from ASIC for bs_shift_dr (RU - read-only volatile)" "0,1" newline bitfld.word 0x0 0. "IN,Value from ASIC for bs_in (RU - read-only volatile)" "0,1" rgroup.word 0x64++0x1 line.word 0x0 "SUP_DIG_LEVEL_ASIC_IN,Current values for incoming los/acjt level. MPLL half rate mode and vreg bypass from ASIC" newline bitfld.word 0x0 15. "RESERVED_15_15,Reserved for Future use" "0,1" newline bitfld.word 0x0 12.--14. "LOS_BIAS,Value from ASIC for los_bias (RU - read-only volatile)" "0,1,2,3,4,5,6,7" newline bitfld.word 0x0 11. "MPLL_HALF_RATE,Value from ASIC for mpll_half_rate (RU - read-only volatile)" "0,1" newline bitfld.word 0x0 10. "VREG_BYPASS,Value from ASIC for vreg_bypass (RU - read-only volatile)" "0,1" newline hexmask.word.byte 0x0 5.--9. 1. "ACJT_LEVEL,Value from ASIC for acjt_level (RU - read-only volatile)" newline hexmask.word.byte 0x0 0.--4. 1. "LOS_LEVEL,Value from ASIC for los_level (RU - read-only volatile)" rgroup.word 0x68++0x1 line.word 0x0 "SUP_DIG_SSC_ASIC_IN,Current values for incoming SSC controls from ASIC" newline bitfld.word 0x0 15. "SS_EN,Value from ASIC for ssc_en (RU - read-only volatile)" "0,1" newline bitfld.word 0x0 12.--14. "SSC_RANGE,Value from ASIC for ssc_range (RU - read-only volatile)" "0,1,2,3,4,5,6,7" newline hexmask.word 0x0 3.--11. 1. "SSC_REF_CLK_SEL,Value from ASIC for ssc_ref_clk_sel (RU - read-only volatile)" newline bitfld.word 0x0 0.--2. "FSEL,Value from ASIC for fsel (RU - read-only volatile)" "0,1,2,3,4,5,6,7" rgroup.word 0x6C++0x1 line.word 0x0 "SUP_DIG_SUP_ASIC_OUT,Current values for outgoing support block controls to ASIC" newline hexmask.word 0x0 5.--15. 1. "RESERVED_15_5,Reserved for Future use" newline bitfld.word 0x0 4. "MPLL_STATE,Value from PHY for mpll_state output (RU - read-only volatile)" "0,1" newline bitfld.word 0x0 3. "BS_OUT,Value from PHY for bs_out output (RU - read-only volatile)" "0,1" newline bitfld.word 0x0 2. "RTUNE_ACK,Value from PHY for rtune_ack output (RU - read-only volatile)" "0,1" newline bitfld.word 0x0 1. "RES_REQ_OUT,Value from PHY for res_req_out output (RU - read-only volatile)" "0,1" newline bitfld.word 0x0 0. "RES_ACK_OUT,Value from PHY for res_ack_out output (RU - read-only volatile)" "0,1" rgroup.word 0x70++0x1 line.word 0x0 "SUP_DIG_ATEOVRD_STATUS,USB3_SUP_DIG_ATEOVRD_STATUS" newline hexmask.word.byte 0x0 10.--15. 1. "RESERVED_15_10,Reserved for Future use" newline bitfld.word 0x0 8.--9. "DTB_OUT,Value from dtb_out bus. (RU - read-only volatile)" "0,1,2,3" newline bitfld.word 0x0 7. "REF_SSP_EN,Value from ASIC for ref_ssp_en. (RU - read-only volatile)" "0,1" newline bitfld.word 0x0 6. "REF_USE_PAD,Value from ASIC for ref_use_pad. (RU - read-only volatile)" "0,1" newline bitfld.word 0x0 5. "PHY_RESET_IN,Value from ASIC for phy_reset (RU - read-only volatile)" "0,1" newline bitfld.word 0x0 4. "REF_CLKDIV2_IN,Value from ASIC for ref_clkdiv2 (RU - read-only volatile)" "0,1" newline bitfld.word 0x0 3. "REF_USB2_EN_IN,Value from ASIC for ref_usb2_en (RU - read-only volatile)" "0,1" newline bitfld.word 0x0 2. "ATEOVRD_EN,When set values from ATEOVRD register are being sent to PHY (RU - read-only volatile)" "0,1" newline bitfld.word 0x0 1. "REF_CLKDIV2_OUT,Value from ATEOVRD for ref_clkdiv2 (RU - read-only volatile)" "0,1" newline bitfld.word 0x0 0. "REF_USB2_EN_OUT,Value from ATEOVRD for ref_usb2_en (RU - read-only volatile)" "0,1" group.word 0x74++0x1 line.word 0x0 "SUP_DIG_HSP_OVRD_IN,Override values for HSP" newline hexmask.word 0x0 4.--15. 1. "RESERVED_15_4,Reserved for Future use" newline bitfld.word 0x0 3. "HSP_PLL_OVRD,Override enable for HSP pll_pu signal" "0,1" newline bitfld.word 0x0 2. "HSP_PLL_PU,Override value for HSP pll_pu signal" "0,1" newline bitfld.word 0x0 1. "HSP_BIAS_OVRD,Override enable for HSP bias_pu signal" "0,1" newline bitfld.word 0x0 0. "HSP_BIAS_PU,Override value for HSP bias_pu signal" "0,1" rgroup.word 0x78++0x1 line.word 0x0 "SUP_DIG_HSP_ASIC_IN,Current values for incoming HSP & REF XO controls from ASIC" newline hexmask.word 0x0 4.--15. 1. "RESERVED_15_4,Reserved for Future use" newline bitfld.word 0x0 3. "REF_USE_XO,Value from ASIC for ref_use_xo (RU - read-only volatile)" "0,1" newline bitfld.word 0x0 2. "REF_XO_EN,Value from ASIC for ref_xo_en (RU - read-only volatile)" "0,1" newline bitfld.word 0x0 1. "HSP_PLL_PU,Value from ASIC for hsp_pll_pu (RU - read-only volatile)" "0,1" newline bitfld.word 0x0 0. "HSP_BIAS_PU,Value from ASIC for hsp_bias_pu (RU - read-only volatile)" "0,1" group.word 0x80++0x1 line.word 0x0 "SUP_DIG_SCOPE_ENABLES,Scope Counter configuration" newline hexmask.word 0x0 5.--15. 1. "RESERVED_15_5,Reserved for Future use" newline bitfld.word 0x0 3.--4. "LANE_SELECT,Scope Counter Input select" "0,1,2,3" newline bitfld.word 0x0 2. "MASK_SATURATION_MODE,Method of mask saturation. When 1 Saturate when the first mask_counter reaches sample_limit. When 0 Saturate when all mask_counters have reached sample_limit." "0,1" newline bitfld.word 0x0 1. "MASK_EN,Enable scope_mask input for tracking count values. Clears registers when deasserted." "0,1" newline bitfld.word 0x0 0. "XOR_EN,Use scope_xor input for count values." "0,1" group.word 0x84++0x1 line.word 0x0 "SUP_DIG_SCOPE_SAMPLES,Number of samples to count" newline hexmask.word 0x0 0.--15. 1. "SAMPLES,Number of Sample to count." rgroup.word 0x88++0x1 line.word 0x0 "SUP_DIG_SCOPE_COUNT,Results of scope counting" newline hexmask.word 0x0 0.--15. 1. "COUNT,A write to this register will start the counting process The value of FFFF indicates counting still in progress. Asserting MASK_EN will also start the counting if in MASK mode. (RU - read-only volatile)" group.word 0x8C++0x1 line.word 0x0 "SUP_DIG_SCOPE_CTL,Masked scope counting Start and Status" newline hexmask.word 0x0 2.--15. 1. "RESERVED_15_2,Reserved for Future use" newline bitfld.word 0x0 1. "MASK_START,A write to this register will start the counting process The value of FFFF indicates counting still in progress Write will trigger mask counting. (USER1 - read-write volatile)" "?,read-write volatile)" newline bitfld.word 0x0 0. "MASK_SATURATION,When assert mask registers have saturated. (USER1 - read-write volatile)" "?,read-write volatile)" repeat 8. (list 0x0 0x1 0xA 0xB 0x64 0x65 0x6E 0x6F )(list 0x0 0x4 0x8 0xC 0x10 0x14 0x18 0x1C ) group.word ($2+0x90)++0x1 line.word 0x0 "SUP_DIG_SCOPE_MASK_$1,Current count value for mask_000" newline hexmask.word 0x0 0.--15. 1. "MASK_VAL_000,Starting count value of mask register. (volatile and 2 reads needed to read value)" repeat.end group.word 0xC0++0x1 line.word 0x0 "SUP_ANA_MPLL_LOOP_CTL,MPLL loop control bits" newline hexmask.word.byte 0x0 8.--15. 1. "RESERVED_15_8,Reserved for Future use" newline hexmask.word.byte 0x0 4.--7. 1. "PROP_CNTRL,Charge pump proportional current setting" newline bitfld.word 0x0 2.--3. "INT_CNTRL,Charge pump integrating current setting" "0,1,2,3" newline bitfld.word 0x0 1. "GD,Measure MPLL local GD" "0,1" newline bitfld.word 0x0 0. "VMB,Measure MPLL Master Bias Voltage" "0,1" repeat 2. (list 0x1 0x2 )(list 0x0 0x4 ) group.word ($2+0xC4)++0x1 line.word 0x0 "SUP_ANA_MPLL_ATB_MEAS$1,ATB Select bits" newline hexmask.word.byte 0x0 8.--15. 1. "RESERVED_15_8,Reserved for Future use" newline bitfld.word 0x0 7. "VPSF,puts vpsf on atb_s_p" "0,1" newline bitfld.word 0x0 6. "VREF,puts vref from charge pump on atb_s_p" "0,1" newline bitfld.word 0x0 5. "VCNTRL,puts vcntrl on atb_s_m" "0,1" newline bitfld.word 0x0 4. "GD,puts gd on atb_s_m" "0,1" newline bitfld.word 0x0 3. "IVCO,puts VCO current/93 on atb_f_m" "0,1" newline bitfld.word 0x0 2. "VP,puts vpa on atb_s_m" "0,1" newline bitfld.word 0x0 1. "VP_CP,puts vp_cp on atb_s_p" "0,1" newline bitfld.word 0x0 0. "VREG_MPLL,puts vreg_mpll on atb_s_p" "0,1" repeat.end group.word 0xCC++0x1 line.word 0x0 "SUP_ANA_MPLL_OVRD,Local overrides" newline hexmask.word.byte 0x0 8.--15. 1. "RESERVED_15_8,Reserved for Future use" newline bitfld.word 0x0 7. "PWRON_LCL,local power_on value" "0,1" newline bitfld.word 0x0 6. "EN_PWRON_LCL,Enable local control of power_on" "0,1" newline bitfld.word 0x0 5. "GS_LCL,local gear_shift value" "0,1" newline bitfld.word 0x0 4. "EN_GS_LCL,Enable local control of gear_shift" "0,1" newline bitfld.word 0x0 3. "RST_LCL,local reset value" "0,1" newline bitfld.word 0x0 2. "EN_RST_LCL,enable local control of reset" "0,1" newline bitfld.word 0x0 1. "PMIX_CLK_SEL_LCL,local pmix_clk_sel value" "0,1" newline bitfld.word 0x0 0. "EN_PMIX_CLK_SEL_LCL,enable local control of pmix_clk_sel" "0,1" group.word 0xD0++0x1 line.word 0x0 "SUP_ANA_RTUNE_RTUNE_CTRL,RTUNE control bits" newline hexmask.word.byte 0x0 8.--15. 1. "RESERVED_15_8,Reserved for Future use" newline bitfld.word 0x0 7. "RT_PWRON_FRC_ON,When set forces RTUNE block to be on" "0,1" newline bitfld.word 0x0 6. "X4_FRC_OFF,When set do not multiply test current by 4" "0,1" newline bitfld.word 0x0 4.--5. "RT_DAC_MODE,Margin DAC mode control bits(00=powerdown 01=DAC drives atb_s_p/m directly 10=DAC drives atb_s_p/m to the RX in margining mode 11=illegal state)" "powerdown,DAC drives atb_s_p/m directly,?,?" newline bitfld.word 0x0 3. "RT_DAC_CHOP,Margin DAC chop control bit. ref to ssp analog engineering doc 8.5" "0,1" newline bitfld.word 0x0 2. "RT_ATB,RTUNE ATB mode control bit (1=RTUNE performs ADC on ATB input 0=not accessing ATB. refer to ssp analog engineering specification 8.1.4)" "not accessing ATB,RTUNE performs ADC on ATB input" newline bitfld.word 0x0 1. "RT_SEL_ATBP,RTUNE ATB sense input select bit (1=atb_s_p 0=atb_s_m)" "atb_s_m),atb_s_p" newline bitfld.word 0x0 0. "RT_SEL_ATBF,RTUNE ATB input select bit (1=atb_fm 0=atb_s_p/m)" "atb_s_p/m),atb_fm" group.word 0xD4++0x1 line.word 0x0 "SUP_ANA_ATB_SWITCHYARD_CTRL,ATB_SWITCHYARD control bits" newline hexmask.word.byte 0x0 8.--15. 1. "RESERVED_15_8,Reserved for Future use" newline bitfld.word 0x0 7. "ASM_GD,Connect gd to atb_s_m" "0,1" newline bitfld.word 0x0 6. "ASP_VP,Connect vp to atb_s_p" "0,1" newline bitfld.word 0x0 5. "ASP_VBG,Connect vbg to atb_s_p" "0,1" newline bitfld.word 0x0 4. "ASP_VPHREG,Connect vphreg to atb_s_m" "0,1" newline bitfld.word 0x0 3. "ATEST_AFM,drive ATEST from atb_f_m" "0,1" newline bitfld.word 0x0 2. "ATEST_AFP,drive ATEST from atb_f_p" "0,1" newline bitfld.word 0x0 1. "ATEST_ASM,Connet ATEST to atb_s_m" "0,1" newline bitfld.word 0x0 0. "ATEST_ASP,Connect ATEST to atb_s_p" "0,1" group.word 0xD8++0x1 line.word 0x0 "SUP_ANA_SSC_CLK_CNTRL,controls sscf reference clock rate" newline hexmask.word.byte 0x0 8.--15. 1. "RESERVED_15_8,Reserved for Future use" newline bitfld.word 0x0 7. "NC,Reserved" "0,1" newline hexmask.word.byte 0x0 0.--6. 1. "SSC_CLK_DIV125,set ssc reference clock to be 20MHz" group.word 0xDC++0x1 line.word 0x0 "SUP_ANA_HSP_CLK_DIG_CNTRL0,controls HSP phase clock. and resolution" newline hexmask.word.byte 0x0 8.--15. 1. "RESERVED_15_8,Reserved for Future use" newline bitfld.word 0x0 7. "NUM_OVERRIDE,Set the value to 1 to enable using values from creg bit 6 downto 0" "0,1" newline bitfld.word 0x0 4.--6. "GATE_PMIX_BITS,Set gate_pmix_bits to gate the corresponding MSB of the 7-bit PMIX phase select bits" "?,?,?,?,?,?,?,bit PMIX phase select bits" newline bitfld.word 0x0 3. "HALF_CLK_EN,Set to 1 for 1.25GHz updates to HSP PMIX. Set to 0 for 2.5GHz updates to PMIX." "0,1" newline bitfld.word 0x0 2. "UCLK_EN_N,Set to 1 to disable update clock. Set to 0 to enable update clock. When clock is enabled phase updates are allowed." "0,1" newline bitfld.word 0x0 1. "EN_HSPPMIX_VPMIX,Set to 1 to connect the regulated HSP PMIX supply to the atb_s_p bus" "0,1" newline bitfld.word 0x0 0. "EN_HSPPMIX_FRC_VPMIX,Set to 1 to force override of HSP PMIX regulator voltage to voltage on atb_s_m" "0,1" group.word 0xE0++0x1 line.word 0x0 "SUP_ANA_HSP_CLK_DIG_CNTRL1,Lower and Upper Phase Increment Values" newline hexmask.word.byte 0x0 8.--15. 1. "RESERVED_15_8,Reserved for Future use" newline hexmask.word.byte 0x0 4.--7. 1. "UPPER_INT,These bits are only used when num_override is set to 1. Upper integer for phase increments of 2.5 to 2.4 GHz conversion. This is the phase increment that is applied 6 times in every 25 for 1.25 GHz increments and 3 times in every 25 for 2.5GHz" newline hexmask.word.byte 0x0 0.--3. 1. "LOWER_INT,These bits are only used when num_override is set to 1. Lower integer for phase increments of 2.5 to 2.4 GHz conversion. This phase increment is applied 19 times in every 25 for 1.25 GHz increments and 22 times in every 25 for 2.5GHz." group.word 0x1000++0x1 line.word 0x0 "LANE0_DIG_TX_OVRD_IN_LO,Override values for incoming TX controls from ASIC" newline bitfld.word 0x0 15. "LANE_IF_WIDTH_OVRD,Override enable for lane interface width" "0,1" newline bitfld.word 0x0 14. "LANE_IF_WIDTH,Override value for lane interface width" "0,1" newline bitfld.word 0x0 13. "TX_DETECT_RX_REQ_OVRD,Override enable for tx_detect_rx_req" "0,1" newline bitfld.word 0x0 12. "TX_DETECT_RX_REQ,Override value for tx_detect_rx_req" "0,1" newline bitfld.word 0x0 11. "TX_BEACON_EN_OVRD,Override enable for tx_beacon_en" "0,1" newline bitfld.word 0x0 10. "TX_BEACON_EN,Override value for tx_beacon_en" "0,1" newline bitfld.word 0x0 9. "TX_CM_EN_OVRD,Override enable for tx_cm_en" "0,1" newline bitfld.word 0x0 8. "TX_CM_EN,Override value for tx_cm_en" "0,1" newline bitfld.word 0x0 7. "TX_EN_OVRD,Override enable for tx_en" "0,1" newline bitfld.word 0x0 6. "TX_EN,Override value for tx_en" "0,1" newline bitfld.word 0x0 5. "TX_DATA_EN_OVRD,Override enable for tx_data_en" "0,1" newline bitfld.word 0x0 4. "TX_DATA_EN,Override value for tx_data_en" "0,1" newline bitfld.word 0x0 3. "TX_INVERT_OVRD,Override enable for tx_invert" "0,1" newline bitfld.word 0x0 2. "TX_INVERT,Override value for tx_invert" "0,1" newline bitfld.word 0x0 1. "TX_LOOPBK_EN_OVRD,Override enable for loopbk_en" "0,1" newline bitfld.word 0x0 0. "LOOPBK_EN,Override value for loopbk_en" "0,1" group.word 0x1004++0x1 line.word 0x0 "LANE0_DIG_TX_OVRD_IN_HI,Override values for incoming TX controls from ASIC" newline hexmask.word.byte 0x0 10.--15. 1. "RESERVED_15_10,Reserved for Future use" newline bitfld.word 0x0 9. "TX_VBOOST_EN_OVRD,Override enable for tx_vboost_en" "0,1" newline bitfld.word 0x0 8. "TX_VBOOST_EN,Override value for tx_vboost_en" "0,1" newline bitfld.word 0x0 7. "TX_RESET_OVRD,Override enable for tx_reset" "0,1" newline bitfld.word 0x0 6. "TX_RESET,Override value for tx_reset" "0,1" newline bitfld.word 0x0 5. "TX_NYQUIST_DATA,Override incoming data to nyquist" "0,1" newline bitfld.word 0x0 4. "TX_CLK_OUT_EN_OVRD,Override enable for tx_clk_out_en." "0,1" newline bitfld.word 0x0 3. "TX_CLK_OUT_EN,Override incomming tx_clk_out_en." "0,1" newline bitfld.word 0x0 2. "TX_RATE_OVRD,Override enable for tx_rate." "0,1" newline bitfld.word 0x0 0.--1. "TX_RATE,Override incomming tx lane rate." "0,1,2,3" group.word 0x1008++0x1 line.word 0x0 "LANE0_DIG_TX_OVRD_DRV_LO,Override values for incoming TX drive controls from ASIC" newline rbitfld.word 0x0 15. "RESERVED_15_15,Reserved for Future use" "0,1" newline bitfld.word 0x0 14. "EN,Enable override values for all inputs controlled by this register" "0,1" newline hexmask.word.byte 0x0 7.--13. 1. "PREEMPH,Override value for transmit preemphasis." newline hexmask.word.byte 0x0 0.--6. 1. "AMPLITUDE,Override value for transmit amplitude." group.word 0x100C++0x1 line.word 0x0 "LANE0_DIG_TX_OVRD_DRV_HI,Override values for incoming TX drive controls from ASIC" newline hexmask.word 0x0 6.--15. 1. "RESERVED_15_6,Reserved for Future use" newline bitfld.word 0x0 5. "EN,Enable override values for all inputs controlled by this register" "0,1" newline hexmask.word.byte 0x0 0.--4. 1. "TERM_OFFSET,Override value for tx_term_offset (tx_ana_vcmref_boost)" group.word 0x1010++0x1 line.word 0x0 "LANE0_DIG_TX_OVRD_OUT,Override values for outgoing TX controls to ASIC" newline hexmask.word.byte 0x0 8.--15. 1. "RESERVED_15_8,Reserved for Future use" newline bitfld.word 0x0 7. "TX_STATE_OVRD,Override enable for tx_state" "0,1" newline bitfld.word 0x0 6. "TX_STATE,Override value for tx_state" "0,1" newline bitfld.word 0x0 5. "TX_CM_STATE_OVRD,Override enable for tx_cm_state" "0,1" newline bitfld.word 0x0 4. "TX_CM_STATE,Override value for tx_cm_state" "0,1" newline bitfld.word 0x0 3. "TX_DETECT_RX_ACK_OVRD,Override enable for tx_detect_rx_ack" "0,1" newline bitfld.word 0x0 2. "TX_DETECT_RX_ACK,Override value for tx_detect_rx_ack" "0,1" newline bitfld.word 0x0 1. "DETECT_RX_RES_OVRD,Override enable for tx_detect_rx_res" "0,1" newline bitfld.word 0x0 0. "DETECT_RX_RES,Override value for tx_detect_rx_res" "0,1" group.word 0x1014++0x1 line.word 0x0 "LANE0_DIG_RX_OVRD_IN_LO,Override values for incoming RX controls from ASIC" newline rbitfld.word 0x0 14.--15. "RESERVED_15_14,Reserved for Future use" "0,1,2,3" newline bitfld.word 0x0 13. "RX_LOS_EN_OVRD,Override enable for rx_los_en" "0,1" newline bitfld.word 0x0 12. "RX_LOS_EN,Override value for rx_los_en" "0,1" newline bitfld.word 0x0 11. "RX_TERM_EN_OVRD,Override enable for rx_term_en" "0,1" newline bitfld.word 0x0 10. "RX_TERM_EN,Override value for rx_term_en" "0,1" newline bitfld.word 0x0 9. "RX_BIT_SHIFT_OVRD,Override enable for rx_bit_shift" "0,1" newline bitfld.word 0x0 8. "RX_BIT_SHIFT,Override value for rx_bit_shift" "0,1" newline bitfld.word 0x0 7. "RX_ALIGN_EN_OVRD,Override enable for rx_align_en" "0,1" newline bitfld.word 0x0 6. "RX_ALIGN_EN,Override value for rx_align_en" "0,1" newline bitfld.word 0x0 5. "RX_DATA_EN_OVRD,Override enable for rx_data_en" "0,1" newline bitfld.word 0x0 4. "RX_DATA_EN,Override value for rx_data_en" "0,1" newline bitfld.word 0x0 3. "RX_PLL_EN_OVRD,Override enable for rx_pll_en" "0,1" newline bitfld.word 0x0 2. "RX_PLL_EN,Override value for rx_pll_en" "0,1" newline bitfld.word 0x0 1. "RX_INVERT_OVRD,Override enable for rx_invert" "0,1" newline bitfld.word 0x0 0. "RX_INVERT,Override value for rx_invert" "0,1" group.word 0x1018++0x1 line.word 0x0 "LANE0_DIG_RX_OVRD_IN_HI,Override values for incoming RX controls from ASIC" newline rbitfld.word 0x0 14.--15. "RESERVED_15_14,Reserved for Future use" "0,1,2,3" newline bitfld.word 0x0 13. "RX_RESET_OVRD,Override enable for rx_reset" "0,1" newline bitfld.word 0x0 12. "RX_RESET,Override value for rx_reset" "0,1" newline bitfld.word 0x0 11. "RX_EQ_OVRD,Override enable for rx_eq" "0,1" newline bitfld.word 0x0 8.--10. "RX_EQ,Override value for rx_eq" "0,1,2,3,4,5,6,7" newline bitfld.word 0x0 7. "RX_EQ_EN_OVRD,Override enable for rx_eq_en" "0,1" newline bitfld.word 0x0 6. "RX_EQ_EN,Override value for rx_eq_en" "0,1" newline bitfld.word 0x0 5. "RX_LOS_FILTER_OVRD,Override enable for rx_los_filter" "0,1" newline bitfld.word 0x0 3.--4. "RX_LOS_FILTER,Override value for rx_los_filter" "0,1,2,3" newline bitfld.word 0x0 2. "RX_RATE_OVRD,Override enable for rx_rate" "0,1" newline bitfld.word 0x0 0.--1. "RX_RATE,Override value for rx_rate" "0,1,2,3" group.word 0x101C++0x1 line.word 0x0 "LANE0_DIG_RX_OVRD_OUT,Override values for outgoing RX controls to ASIC" newline hexmask.word 0x0 7.--15. 1. "RESERVED_15_7,Reserved for Future use" newline bitfld.word 0x0 6. "ZERO_DATA,Override data output to all zeros" "0,1" newline bitfld.word 0x0 5. "LOS_OVRD,Override value for rx_los" "0,1" newline bitfld.word 0x0 4. "LOS,Override value for rx_los" "0,1" newline bitfld.word 0x0 3. "PLL_STATE_OVRD,Override enable for rx_pll_state" "0,1" newline bitfld.word 0x0 2. "PLL_STATE,Override value for rx_pll_state" "0,1" newline bitfld.word 0x0 1. "VALID_OVRD,Override enable for rx_valid" "0,1" newline bitfld.word 0x0 0. "VALID,Override value for rx_valid" "0,1" rgroup.word 0x1020++0x1 line.word 0x0 "LANE0_DIG_TX_ASIC_IN,Current values for incoming TX controls from ASIC" newline bitfld.word 0x0 14.--15. "RESERVED_15_14,Reserved for Future use" "0,1,2,3" newline bitfld.word 0x0 13. "LANE_IF_WIDTH,Value from ASIC for lane_if_width (RU - read-only volatile)" "0,1" newline bitfld.word 0x0 12. "DATA_EN_S,Value from ASIC for tx_data_en_s (RU - read-only volatile)" "0,1" newline bitfld.word 0x0 11. "TX_VBOOST_EN,Value from ASIC for tx_vboost_en (RU - read-only volatile)" "0,1" newline bitfld.word 0x0 10. "TX_CLK_OUT_EN,Value from ASIC for tx_clk_out_en (RU - read-only volatile)" "0,1" newline bitfld.word 0x0 9. "DETECT_RX_REQ,Value from ASIC for tx_detect_rx_req (RU - read-only volatile)" "0,1" newline bitfld.word 0x0 8. "BEACON_EN,Value from ASIC for tx_beacon_en (RU - read-only volatile)" "0,1" newline bitfld.word 0x0 7. "CM_EN,Value from ASIC for tx_cm_en (RU - read-only volatile)" "0,1" newline bitfld.word 0x0 6. "TX_EN,Value from ASIC for tx_en (RU - read-only volatile)" "0,1" newline bitfld.word 0x0 5. "DATA_EN,Value from ASIC for tx_data_en (RU - read-only volatile)" "0,1" newline bitfld.word 0x0 4. "TX_RESET,Value from ASIC for tx_reset (RU - read-only volatile)" "0,1" newline bitfld.word 0x0 3. "INVERT,Value from ASIC for tx_invert (RU - read-only volatile)" "0,1" newline bitfld.word 0x0 2. "LOOPBK_EN,Value from ASIC for loopbk_en (RU - read-only volatile)" "0,1" newline bitfld.word 0x0 0.--1. "TX_RATE,Value from ASIC for tx_rate (RU - read-only volatile)" "0,1,2,3" rgroup.word 0x1024++0x1 line.word 0x0 "LANE0_DIG_TX_ASIC_DRV_LO,Current values for incoming TX level controls from ASIC" newline bitfld.word 0x0 14.--15. "RESERVED_15_14,Reserved for Future use" "0,1,2,3" newline hexmask.word.byte 0x0 7.--13. 1. "PREEMPH,Value from ASIC for tx_preemph (RU - read-only volatile)" newline hexmask.word.byte 0x0 0.--6. 1. "AMPLITUDE,Value from ASIC for tx_amplitude (RU - read-only volatile)" rgroup.word 0x1028++0x1 line.word 0x0 "LANE0_DIG_TX_ASIC_DRV_HI,Current values for incoming TX level controls from ASIC" newline hexmask.word 0x0 5.--15. 1. "RESERVED_15_5,Reserved for Future use" newline hexmask.word.byte 0x0 0.--4. 1. "TERM_OFFSET,Value from ASIC for tx_term_offset (RU - read-only volatile)" rgroup.word 0x102C++0x1 line.word 0x0 "LANE0_DIG_TX_ASIC_OUT,Current values for outgoing TX status controls from PHY" newline hexmask.word 0x0 5.--15. 1. "RESERVED_15_5,Reserved for Future use" newline bitfld.word 0x0 4. "STATE,Value from PHY for tx_state (RU - read-only volatile)" "0,1" newline bitfld.word 0x0 3. "CM_STATE,Value from PHY for tx_cm_state (RU - read-only volatile)" "0,1" newline bitfld.word 0x0 2. "DETECT_RX_ACK,Value from PHY for tx_detect_rx_ack (RU - read-only volatile)" "0,1" newline bitfld.word 0x0 1. "RESERVED,Always returns 0 (RU - read-only volatile)" "0,1" newline bitfld.word 0x0 0. "DETECT_RX_RES,Value from PHY for tx_detect_rx_res (RU - read-only volatile)" "0,1" rgroup.word 0x1030++0x1 line.word 0x0 "LANE0_DIG_RX_ASIC_IN,Current values for incoming RX controls from ASIC" newline bitfld.word 0x0 15. "RX_EQ_EN,Value from ASIC for rx_eq_en (RU - read-only volatile)" "0,1" newline bitfld.word 0x0 12.--14. "RX_EQ,Value from ASIC for rx_eq (RU - read-only volatile)" "0,1,2,3,4,5,6,7" newline bitfld.word 0x0 10.--11. "LOS_FILTER,Value from ASIC for rx_los_filter (RU - read-only volatile)" "0,1,2,3" newline bitfld.word 0x0 9. "LOS_EN,Value from ASIC for rx_los_en (RU - read-only volatile)" "0,1" newline bitfld.word 0x0 8. "TERM_EN,Value from ASIC for rx_term_en (RU - read-only volatile)" "0,1" newline bitfld.word 0x0 7. "CLK_SHIFT,Value from ASIC for rx_bit_shift (RU - read-only volatile)" "0,1" newline bitfld.word 0x0 6. "ALIGN_EN,Value from ASIC for rx_align_en (RU - read-only volatile)" "0,1" newline bitfld.word 0x0 5. "DATA_EN,Value from ASIC for rx_data_en (RU - read-only volatile)" "0,1" newline bitfld.word 0x0 4. "PLL_EN,Value from ASIC for rx_pll_en (RU - read-only volatile)" "0,1" newline bitfld.word 0x0 3. "RX_RESET,Value from ASIC for rx_reset (RU - read-only volatile)" "0,1" newline bitfld.word 0x0 2. "INVERT,Value from ASIC for rx_invert (RU - read-only volatile)" "0,1" newline bitfld.word 0x0 0.--1. "RX_RATE,Value from ASIC for rx_rate (RU - read-only volatile)" "0,1,2,3" rgroup.word 0x1034++0x1 line.word 0x0 "LANE0_DIG_RX_ASIC_OUT,Current values for outgoing RX status controls from PHY" newline hexmask.word 0x0 3.--15. 1. "RESERVED_15_3,Reserved for Future use" newline bitfld.word 0x0 2. "LOS,Value from PHY for rx_los (RU - read-only volatile)" "0,1" newline bitfld.word 0x0 1. "PLL_STATE,Value from PHY for rx_pll_state (RU - read-only volatile)" "0,1" newline bitfld.word 0x0 0. "VALID,Value from PHY for rx_valid (RU - read-only volatile)" "0,1" group.word 0x1040++0x1 line.word 0x0 "LANE0_DIG_TX_DEBUG,Transmit debug controls" newline rbitfld.word 0x0 13.--15. "RESERVED_15_13,Reserved for Future use" "0,1,2,3,4,5,6,7" newline bitfld.word 0x0 12. "KEEP_TX_REFGEN,Keep TX voltage regulator ON until TX clocks are OFF" "0,1" newline hexmask.word.byte 0x0 4.--11. 1. "RXDET_MEAS_TIME,Time to wait for rxdet measurement (* 4/2/1 refclk cycles based on multiplier)" newline bitfld.word 0x0 3. "DETECT_RX_ALWAYS,Always signal 1 for rx_detect ignoring analog" "0,1" newline bitfld.word 0x0 0.--2. "DTB_SEL,Selects data to drive on DTB 0 - disabled 1 - mag_update/sub signals 2 - mag_high/add signals 3 - clock aligner early/shift signals 4 - analog/asic clocks 5 - tx_state counter/lbert strobe 6 - noclk_ref_rst/dig_rst 7 -.." "disabled,mag_update/sub signals,mag_high/add signals,clock aligner early/shift signals,analog/asic clocks,tx_state counter/lbert strobe,noclk_ref_rst/dig_rst,tx_ana_rxdetp_high/tx_ana_rxdetm_high" group.word 0x1044++0x1 line.word 0x0 "LANE0_DIG_TX_CM_WAIT_TIME_OVRD,USB3_LANE0_DIG_TX_CM_WAIT_TIME_OVRD" newline hexmask.word.byte 0x0 11.--15. 1. "RESERVED_15_11,Reserved for Future use" newline bitfld.word 0x0 10. "CM_TIME_OVRD_EN,Override enable for common mode charging wait time." "0,1" newline hexmask.word 0x0 0.--9. 1. "CM_TIME_OVRD,Time to wait in ref clock cycles for LFPS common mode charging (This value x32 is used for VCMHOLD charging method)" rgroup.word 0x1048++0x1 line.word 0x0 "LANE0_DIG_TX_VMD_FSM_TX_VCM_0,Calculated values for N_USE and N_TRISTATE. Also TX ANA configuration shift register output." newline bitfld.word 0x0 15. "SHIFT_OUT,Current value from TX_ANAs configuration shift register. (RU - read-only volatile)" "0,1" newline bitfld.word 0x0 14. "DONE,Configuration is done (RU - read-only volatile)" "0,1" newline hexmask.word.byte 0x0 7.--13. 1. "N_USE,Value from VMD for legs to use. (RU - read-only volatile)" newline hexmask.word.byte 0x0 0.--6. 1. "N_TRISTATE,Value from VMD for number of tristate legs. (RU - read-only volatile)" rgroup.word 0x104C++0x1 line.word 0x0 "LANE0_DIG_TX_VMD_FSM_TX_VCM_1,Calculated values for N_FIXED and N_TRAILER." newline bitfld.word 0x0 15. "FIXED_DONE,N_FIXED Multiplication has completed. (RU - read-only volatile)" "0,1" newline bitfld.word 0x0 14. "TRA_DONE,N_TRAILER Multiplication has completed. (RU - read-only volatile)" "0,1" newline hexmask.word.byte 0x0 7.--13. 1. "N_FIXED,Value from VMD for number of fixed driver legs. (RU - read-only volatile)" newline hexmask.word.byte 0x0 0.--6. 1. "N_TRAILER,Value from VMD for number of trailer legs. (RU - read-only volatile)" group.word 0x1050++0x1 line.word 0x0 "LANE0_DIG_TX_VMD_FSM_TX_VCM_DEBUG_IN,Access the TX_ANA VMD Control Shift Register" newline hexmask.word 0x0 4.--15. 1. "RESERVED_15_4,Reserved for Future use" newline bitfld.word 0x0 3. "CONFIG_OVRD,Override the Voltage Mode Driver Configuration FSM and access the shift chain directly. (volatile and 2 reads needed to read value)" "0,1" newline bitfld.word 0x0 2. "CONFIG_LOAD,Override value for the Voltage Mode Driver Configuration FSM's config load. (volatile and 2 reads needed to read value)" "0,1" newline bitfld.word 0x0 1. "CONFIG_CLK,Override value for the Voltage Mode Driver Configuration FSM's config clk. (volatile and 2 reads needed to read value)" "0,1" newline bitfld.word 0x0 0. "CONFIG_DATA,Override value for the Voltage Mode Driver Configuration FSM's config data. (volatile and 2 reads needed to read value)" "0,1" group.word 0x1054++0x1 line.word 0x0 "LANE0_DIG_TX_LBERT_CTL,Pattern Generator controls" newline rbitfld.word 0x0 15. "RESERVED_15_15,Reserved for Future use" "0,1" newline hexmask.word 0x0 5.--14. 1. "PAT0,10 bit pattern for modes using PAT0 (5-7). Ignored for other MODEs." newline bitfld.word 0x0 4. "TRIGGER_ERR,Single shot inversion the LSB of the current symbol. Any write of a 1 to this bit will insert an error. Maintain mode and pattern from setup." "0,1" newline hexmask.word.byte 0x0 0.--3. 1. "MODE,Pattern to generate When changing modes you must change to disabled first 0 - disabled 1 - lfsr31. X^31 + X^28 + 1 2 - lfsr23. X^23 + X^18 + 1 3 - lfsr15. X^15 + X^14 + 1 4 - lfsr7. X^7 + X^6 + 1 5 - fixed word (PAT0) 6 - DC balanced word (PAT0.." group.word 0x1058++0x1 line.word 0x0 "LANE0_DIG_RX_LBERT_CTL,Pattern Matcher controls" newline hexmask.word 0x0 5.--15. 1. "RESERVED_15_5,Reserved for Future use" newline bitfld.word 0x0 4. "SYNC,Synchronize pattern matcher with incoming data A write of a one to this bit will reset the error counter and start a synchronization of the PM. There is no need to write this back to zero to run normally." "0,1" newline hexmask.word.byte 0x0 0.--3. 1. "MODE,Pattern to match When changing modes you must change to disabled first 0 - disabled 1 - lfsr31: X^31 + X^28 + 1 2 - lfsr23: X^23 + X^18 + 1 3 - lfsr15: X^15 + X^14 + 1 4 - lfsr7 : X^7 + X^6 + 1 5 - d[n] = d[n-10] 6 - d[n] = !d[n-10] 7 - d[n] =.." group.word 0x105C++0x1 line.word 0x0 "LANE0_DIG_RX_LBERT_ERR,Pattern match error counter" newline bitfld.word 0x0 15. "OV14,A read of this register or a sync of the Pattern Matcher resets the error count. If all bits of this register are 1 the error counter has saturated. If the status If active multiply COUNT by 128. If OV14=1 and COUNT=2^15-1 signals overflow of.." "0,1" newline hexmask.word 0x0 0.--14. 1. "COUNT,Current error count If OV14 field is active then multiply count by 128 to get the actual count. (volatile and 2 reads needed to read value)" group.word 0x1060++0x1 line.word 0x0 "LANE0_DIG_RX_SCOPE_CTL,Control bits for per-transciever scope portion" newline rbitfld.word 0x0 14.--15. "RESERVED_15_14,Reserved for Future use" "0,1,2,3" newline bitfld.word 0x0 12.--13. "RX_VALID_CTL,When to Start Sampling control based on rx_valid. 0 = Ignore rx_valid. 1 = Heed rx_valid. 2 = Wait for rising_edge on rx_valid." "Ignore rx_valid,Heed rx_valid,Wait for rising_edge on rx_valid,?" newline hexmask.word 0x0 3.--11. 1. "DELAY,number of cycles to skip between samples" newline bitfld.word 0x0 0.--2. "MODE,sampling mode of counters NOTE: WORD is 20 bits. 0 = off 1 = sample data every WORD*(1+DELAY) bits from the digital recovered path. 2 = sample data every WORD*(1+DELAY) + 1 bits from the digital recovered path. 3 = sample data every WORD*(1+DELAY) +.." "off,sample data every WORD*,sample data every WORD*,sample data every WORD*,sample data every WORD*,?,?,?" group.word 0x1064++0x1 line.word 0x0 "LANE0_DIG_RX_SCOPE_PHASE,Scope sampling phase." newline rbitfld.word 0x0 15. "RESERVED_15_15,Reserved for Future use" "0,1" newline hexmask.word.byte 0x0 10.--14. 1. "BASE,which bit to sample when MODE = 1 or 4" newline bitfld.word 0x0 8.--9. "SCOPE_DELAY,How many clocks to delay the analog scope_data." "0,1,2,3" newline bitfld.word 0x0 7. "SCOPE_SEL,Select Sampling Mode. 0 - Before AFE Sampling 1 - After AFE Sampling" "Before AFE Sampling,After AFE Sampling" newline bitfld.word 0x0 6. "UPDATE,Update Sampling phase. Write a 1." "0,1" newline hexmask.word.byte 0x0 0.--5. 1. "SAMPLE_PHASE,Sampling Phase" group.word 0x1068++0x1 line.word 0x0 "LANE0_DIG_RX_DPLL_FREQ,Current frequency integrator value." newline rbitfld.word 0x0 13.--15. "RESERVED_15_13,Reserved for Future use" "0,1,2,3,4,5,6,7" newline hexmask.word 0x0 1.--12. 1. "VAL,Freq is 1.526*VAL ppm from the reference When mpll_slow is set the ppm is half the eqn above (volatile and 2 reads needed to read value)" newline bitfld.word 0x0 0. "DTHR,Bits below the useful resolution (volatile and 2 reads needed to read value)" "0,1" group.word 0x106C++0x1 line.word 0x0 "LANE0_DIG_RX_CDR_CTL,Control bits for receiver in recovered domain" newline hexmask.word.byte 0x0 12.--15. 1. "DTB_SEL,select to drive various signals onto the dtb 0 - disabled 1 - pll_ana_rst pll_count from rx_pwr_ctl 2 - com_good_high/low from aligner 3 - com_bad_high/low from aligner 4 - shift_in_prog ana_odd_data from aligner 5 - low bits of XAUI align FSM.." newline bitfld.word 0x0 11. "ALWAYS_REALIGN,realign on any misaligned comma" "0,1" newline bitfld.word 0x0 10. "FAST_START,decrease startup steps by 50%" "0,1" newline bitfld.word 0x0 8.--9. "FRUG_VALUE,override value for FRUG" "0,1,2,3" newline bitfld.word 0x0 6.--7. "PHUG_VALUE,override value for PHUG" "0,1,2,3" newline bitfld.word 0x0 5. "OVRD_DPLL_GAIN,Override PHUG and FRUG values" "0,1" newline bitfld.word 0x0 4. "PHDET_POL,Reverse polarity of phase error" "0,1" newline bitfld.word 0x0 2.--3. "PHDET_EDGE,Edges to use for phase detection. 11 - Use both edges 10 - Use rising edges only 01 - Use falling edges only 00 - Ignore all edges" "Ignore all edges,Use falling edges only,?,?" newline bitfld.word 0x0 0.--1. "PHDET_EN,Enable phase detecter. top bit is odd slicers bottom is even" "0,1,2,3" rgroup.word 0x1070++0x1 line.word 0x0 "LANE0_DIG_RX_CDR_CDR_FSM_DEBUG,Current values for CDR and Adaptation FSM." newline bitfld.word 0x0 13.--15. "ADAP_RX_EQ,Equalization setting from adaptation FSM. (RU - read-only volatile)" "0,1,2,3,4,5,6,7" newline bitfld.word 0x0 10.--12. "RX_EQ_CTR,Initial centre point from equalization FSM. (RU - read-only volatile)" "0,1,2,3,4,5,6,7" newline bitfld.word 0x0 7.--9. "RX_ANA_EQ,Equalization setting to Analog. (RU - read-only volatile)" "0,1,2,3,4,5,6,7" newline bitfld.word 0x0 6. "ADAP_RX_VALID,Adaptation has completed and locked. (RU - read-only volatile)" "0,1" newline bitfld.word 0x0 5. "CDR_EN_ADAP,Adapatation loop is enabling the CDR. (RU - read-only volatile)" "0,1" newline bitfld.word 0x0 4. "CDR_EN_EQ,Equalization loop is enabling the CDR. (RU - read-only volatile)" "0,1" newline bitfld.word 0x0 3. "ALIGNED,Datapath is bit-aligned. (RU - read-only volatile)" "0,1" newline bitfld.word 0x0 2. "CDR_RX_VALID,CDR has locked to incoming data stream. (RU - read-only volatile)" "0,1" newline bitfld.word 0x0 1. "CDR_TIMEOUT,CDR has not locked to datastream and has timed-out. (RU - read-only volatile)" "0,1" newline bitfld.word 0x0 0. "CDR_EN,CDR has been enabled. (RU - read-only volatile)" "0,1" group.word 0x1074++0x1 line.word 0x0 "LANE0_DIG_RX_CDR_LOCK_VEC_OVRD,Control bits for receiver in recovered domain" newline hexmask.word.byte 0x0 11.--15. 1. "ADAP_CTR_LEVEL,Ammount of earlies that increment the adaptation counter (times 32 Default is 512). (volatile and 2 reads needed to read value)" newline bitfld.word 0x0 10. "ADAP_POLARITY,If asserted invert default adaptation adjustment for equalization. IF early decrease equalization. Normal mode is to decrease. (volatile and 2 reads needed to read value)" "0,1" newline bitfld.word 0x0 9. "LOCK_VECTOR_OVRD,Override enable for the rx_eq outputs. (volatile and 2 reads needed to read value)" "0,1" newline bitfld.word 0x0 8. "LOCK_VECTOR_EN,Override value for the locked_vector output completion. (volatile and 2 reads needed to read value)" "0,1" newline hexmask.word.byte 0x0 0.--7. 1. "LOCK_VECTOR,Override value for the locked_vector. (volatile and 2 reads needed to read value)" rgroup.word 0x1078++0x1 line.word 0x0 "LANE0_DIG_RX_CDR_LOCK_VEC,Current values for the locked vector.." newline hexmask.word.byte 0x0 12.--15. 1. "RESERVED_15_12,Reserved for Future use" newline bitfld.word 0x0 9.--11. "EQ_RX_EQ,Equalization setting from the Equalization Loop. (RU - read-only volatile)" "0,1,2,3,4,5,6,7" newline bitfld.word 0x0 8. "EQ_LOCKED_VECTOR_EN,Equalization locked vector has been filled. (RU - read-only volatile)" "0,1" newline hexmask.word.byte 0x0 0.--7. 1. "EQ_LOCKED_VECTOR,Results of equalization loop. (RU - read-only volatile)" rgroup.word 0x107C++0x1 line.word 0x0 "LANE0_DIG_RX_CDR_ADAP_FSM,Observation of adaptation FSM register." newline hexmask.word.byte 0x0 11.--15. 1. "MSTR_CTR,Master count register. (RU - read-only volatile)" newline hexmask.word.byte 0x0 7.--10. 1. "LOOP_CTR,Loop count register. (RU - read-only volatile)" newline hexmask.word.byte 0x0 3.--6. 1. "ADAP_CTR,Adaptation count register. (RU - read-only volatile)" newline bitfld.word 0x0 0.--2. "ADAP_STATE,Adaptation State. NOTE: ADAP_RESET = 3'b000 ADAP_LOCK = 3'b001 ADAP_SUFF = 3'b010 ADAP_LOOP = 3'b011 ADAP_MSTR = 3'b100 ADAP_DONE = 3'b101 (RU - read-only volatile)" "0,1,2,3,4,5,6,7" group.word 0x1080++0x1 line.word 0x0 "LANE0_ANA_RX_ATB0,ATB Control Register" newline hexmask.word.byte 0x0 8.--15. 1. "RESERVED_15_8,Reserved for Future use" newline bitfld.word 0x0 7. "EN_ATB,Enable ATB sensing and forcing on internal RX nodes" "0,1" newline bitfld.word 0x0 6. "EN_MARG,Enable margining mode in receiver; it puts EQ common mode output on atb_f_m" "0,1" newline bitfld.word 0x0 5. "EN_ATB_RM_F,Enable atb_f_p on negative-side termination resistor" "0,1" newline bitfld.word 0x0 4. "EN_ATB_RM_S,Enable atb_s_m on negative-side termination resistor" "0,1" newline bitfld.word 0x0 3. "EN_ATB_RP_F,Enable atb_f_p on positive-side termination resistor" "0,1" newline bitfld.word 0x0 2. "EN_ATB_RP_S,Enable atb_s_p on positive-side termination resistor" "0,1" newline bitfld.word 0x0 1. "EN_ATB_VOS,Put rxafe filtered outputs vo_p on atb_s_p and vo_m on atb_s_m" "0,1" newline bitfld.word 0x0 0. "EN_ATB_VOFF,Put rxafe voff_p on atb_s_p and voff_m on atb_s_m" "0,1" group.word 0x1084++0x1 line.word 0x0 "LANE0_ANA_RX_ATB1,ATB and Misc Control Register" newline hexmask.word.byte 0x0 8.--15. 1. "RESERVED_15_8,Reserved for Future use" newline bitfld.word 0x0 6.--7. "RX_DCC_IQ_OFFSET_H_4_3,Code which helps to manually tune reference voltage (r-string dac) for IQ opamp and correct input offset (rx_dcc_iq_offset_h_4_3 bit)" "0,1,2,3" newline bitfld.word 0x0 5. "EN_ATB_VLOS,Enable sensing of LOS reference voltage on atb_s_p" "0,1" newline bitfld.word 0x0 4. "EN_ATB_VRF,Enable sensing of vref_rx (RX Bias B.G. Voltage) on atb_s_p" "0,1" newline bitfld.word 0x0 3. "MEAS_GD,Enable sensing of local gd in RX; ties gd to atb_s_m" "0,1" newline bitfld.word 0x0 2. "MEAS_VP,Enable sensing of local vp in RX; ties vp to atb_s_p" "0,1" newline bitfld.word 0x0 0.--1. "RX_DCC_IQ_OFFSET_H_2_1,Code which helps to manually tune reference voltage (r-string dac) for IQ opamp and correct input offset (rx_dcc_iq_offset_h_2_1 bit)" "0,1,2,3" group.word 0x1088++0x1 line.word 0x0 "LANE0_ANA_RX_ENPWR0,RX State Control Register" newline hexmask.word.byte 0x0 8.--15. 1. "RESERVED_15_8,Reserved for Future use" newline bitfld.word 0x0 7. "CTL_RXPWRON,MUX select for AFE en to select between CTL_RXPWRON=0 rx_afe_en (External signal) or CTL_RXPWRON=1 LCL_RXPWRON" "0,1" newline bitfld.word 0x0 6. "LCL_RXPWRON,Enable/Disable RX AFE .This bit is only selected when CTL_RXPWRON = 1" "0,1" newline bitfld.word 0x0 5. "CTL_EN_LOS,MUX select for LOS en to select between CTL_EN_LOS=0 rx_los_en (External signal) or CTL_EN_LOS=1 LCL_EN_LOS" "0,1" newline bitfld.word 0x0 4. "LCL_EN_LOS,Enable/Disable LOS.This bit is only selected when CTL_EN_LOS = 1" "0,1" newline bitfld.word 0x0 3. "CTL_RXCK,MUX select for RX Clock en to select between CTL_RXCK=0 rx_clock_en (External signal) or CTL_RXCK=1 LCL_RXCK." "0,1" newline bitfld.word 0x0 2. "LCL_RXCK,Enable/Disable en_rx_clock (RX clock enable).This bit is only selected when CTL_RXCK = 1" "0,1" newline bitfld.word 0x0 1. "CTL_ACJT,MUX select for ACJTAG to select between CTL_ACJTG=0 rx_acjtg_en (External signal) or CTL_ACJTG=1 LCL_ACJT." "0,1" newline bitfld.word 0x0 0. "LCL_ACJT,Enable/Disable acjtag block This bit is only selected when CTL_ACJTG = 1" "0,1" group.word 0x108C++0x1 line.word 0x0 "LANE0_ANA_RX_PMIX_PHASE,Phase select Value" newline hexmask.word.byte 0x0 8.--15. 1. "RESERVED_15_8,Reserved for Future use" newline hexmask.word.byte 0x0 0.--7. 1. "PHASE,Write to bits 8 to 1 of the phase select register in the phase mixer through the CDR (USER2 volatile - read-write volatile and custom)" group.word 0x1090++0x1 line.word 0x0 "LANE0_ANA_RX_ENPWR1,Additional RX State Control Register" newline hexmask.word.byte 0x0 8.--15. 1. "RESERVED_15_8,Reserved for Future use" newline bitfld.word 0x0 7. "CTL_PHASE_REG_RST,MUX select for Phase Register Reset to select between CTL_PHASE_REG_RST=0 rx_phase_reg_rst (External signal) or CTL_PHASE_REG_RST=1 LCL_PHASE_REG_RST" "0,1" newline bitfld.word 0x0 6. "LCL_PHASE_REG_RST,Reset phase register.This bit is only selected when CTL_PHASE_REG_RST= 1" "0,1" newline bitfld.word 0x0 5. "CTL_BST,MUX select for AFE Boost to select between CTL_BST=0 rx_aeq[2:0] (External signal) or CTL_BST=1 LCL_BST" "0,1" newline bitfld.word 0x0 2.--4. "LCL_BST,RX Boost (equalization) Value" "0,1,2,3,4,5,6,7" newline bitfld.word 0x0 1. "CTL_RXTERM,MUX select for RX Term enable to select between CTL_RXTERM=0 rx_term_en (External signal) or CTL_RXTERM=1 LCL_RXTERM" "0,1" newline bitfld.word 0x0 0. "LCL_RXTERM,Enable/disable RX termination when CTL_RXTERM = 1" "0,1" group.word 0x1094++0x1 line.word 0x0 "LANE0_ANA_RX_ENPWR2,Yet another RX State Control Register" newline hexmask.word.byte 0x0 8.--15. 1. "RESERVED_15_8,Reserved for Future use" newline bitfld.word 0x0 7. "EN_RXPMIX_TST,Enable XOR gate to test linearity of RX phase mixer using atb_s_p and atb_s_m" "0,1" newline bitfld.word 0x0 6. "EN_RXPMIX_VPMIX,Put vreg_pmix on atb_s_p" "0,1" newline bitfld.word 0x0 5. "EN_RXPMIX_VRX,Put vreg_rx on atb_s_p" "0,1" newline bitfld.word 0x0 4. "RX_DCC_IQ_OFFSET_H_0,Code which helps to manually tune reference voltage (r-string dac) for IQ opamp and correct input offset (rx_dcc_iq_offset_h_0 bit)" "0,1" newline bitfld.word 0x0 3. "EN_RXPMIX_FRC_VPMIX_H,Connecting vbg_in to vbg (in case of 0) or to atb_s_m_int (in case of 1)" "0,1" newline bitfld.word 0x0 2. "RX_SCOPE_ATB_2,Put XOR of RX SCOPE PMIX input and output on atb_s_p" "0,1" newline bitfld.word 0x0 1. "RX_SCOPE_ATB_1,Put RX SCOPE regulated VP on atb_s_p" "0,1" newline bitfld.word 0x0 0. "RX_SCOPE_ATB_0,Have RX SCOPE reference for regulator use atb_f_p as a reference instead of VP/VBG" "0,1" group.word 0x1098++0x1 line.word 0x0 "LANE0_ANA_RX_SCOPE_VDCC,RX Scope controls and clock DCC control voltage probe" newline hexmask.word.byte 0x0 8.--15. 1. "RESERVED_15_8,Reserved for Future use" newline bitfld.word 0x0 6.--7. "VDCC,Probe DCC control voltage" "0,1,2,3" newline bitfld.word 0x0 5. "NC5,Reserved" "0,1" newline bitfld.word 0x0 4. "RX_SCOPE_SLEW,Set high for low RX clock frqeuencies (625MHz) for RX Scope to work correctly" "0,1" newline bitfld.word 0x0 3. "RX_SCOPE_FDIV20,Divide scope output clock by 20 instead of 10" "0,1" newline bitfld.word 0x0 2. "RX_LOS_LFPS_EN_BIT_2,In case of rx_los_lfps_en_cntrl = 1/0 reg_rx_los_lfps_en/rx_ana_los_lfps_en signal directly applied to rx_los circuit through I101 multiplexer." "0,1" newline bitfld.word 0x0 1. "RX_DCC_IQ_OFFSET_EN_H,Select ref voltage for IQ opamp from testmode part (in case of 1) or from ordinary resistive dividers (in case of 0)." "0,1" newline bitfld.word 0x0 0. "RX_LOS_LFPS_EN,Enables the RX LOS LFPS mode use when you want to detect incoming LFPS signals USB3.0" "0,1" group.word 0x10AC++0x1 line.word 0x0 "LANE0_ANA_TX_TXDRV_CNTRL,Register 3" newline hexmask.word.byte 0x0 8.--15. 1. "RESERVED_15_8,Reserved for Future use" newline bitfld.word 0x0 7. "PULL_DN_REG,register bit that causes the calibrated TX bits to pull down in a common mode fashion. If pull_dn_reg and tx_pull_up are both high then pull_dn_reg wins" "0,1" newline bitfld.word 0x0 6. "PULL_UP_REG,Register override for tx_pull_up. Used when ovrd_pull_up is HIGH causes calibrated TX bits to pull up in a common mode fashion unless pull_dn_reg is HIGH" "0,1" newline bitfld.word 0x0 5. "OVRD_PULL_UP,Selects local value of pull_up_reg instead of tx_pull_up" "0,1" newline bitfld.word 0x0 4. "VCM_HOLD_REG,Register override for tx_vcm_hold. Used when ovrd_vcm_hold is HIGH controls the TX common mode hold circuitry" "0,1" newline bitfld.word 0x0 3. "OVRD_VCM_HOLD,Selects local value of vcm_hold_reg instead of tx_vcm_hold to control state of TX common mode hold circuitry" "0,1" newline bitfld.word 0x0 2. "REFGEN_PWRDN_OVRD_N,Set LOW for TX regulator not to turn on when RX clock is enabled. Default is for TX regulator to turn on when RX or TX clock is enabled" "0,1" newline bitfld.word 0x0 1. "NOCONN_1,Reserved" "0,1" newline bitfld.word 0x0 0. "NOCONN_0,Reserved" "0,1" group.word 0x10B0++0x1 line.word 0x0 "LANE0_ANA_TX_POWER_CTL,Register 4" newline hexmask.word.byte 0x0 8.--15. 1. "RESERVED_15_8,Reserved for Future use" newline bitfld.word 0x0 7. "OVRD_EN,Enables local overrides for all signals in this register except for TX_DIV_CLK_EN which doesn't need this signal" "0,1" newline bitfld.word 0x0 6. "SERIAL_EN_REG,Forces state of tx_serial_en when OVRD_EN is 1" "0,1" newline bitfld.word 0x0 5. "CLK_EN_REG,Forces state of tx_clk_en when OVRD_EN is 1" "0,1" newline bitfld.word 0x0 4. "DATA_EN_REG,Forces state of tx_data_en when OVRD_EN is HIGH" "0,1" newline bitfld.word 0x0 3. "REFGEN_EN_REG,Register override value for tx_refgen_en. Controls the TX regulator biasing circuitry and the rxdetect comparators when OVRD_EN is HIGH. This function may be overridden by the state of refgen_pwdn_reg" "0,1" newline bitfld.word 0x0 2. "TX_DIV_CLK_EN,Enables the div clock that goes from the TX to the undersampler more appropriately called tx_sampler_clk_en this clock comes after the optional divide by 2 or 4 tx_clk_en must be HIGH to get a clock out" "0,1" newline bitfld.word 0x0 1. "REFGEN_PDN_REG,Register override for refgen pwdn. Used when OVRD_EN is HIGH. Controls the TX regulator biasing circuitry and the rxdetect comparators when OVRD_EN is HIGH" "0,1" newline bitfld.word 0x0 0. "LFPS_HIGH_PRIORITY,When this is set high LFPS priority becomes higher than tx_data" "0,1" group.word 0x10B4++0x1 line.word 0x0 "LANE0_ANA_TX_ALT_BLOCK,Register 5" newline hexmask.word.byte 0x0 8.--15. 1. "RESERVED_15_8,Reserved for Future use" newline bitfld.word 0x0 7. "EN_ALT_BUS,Enables the TX for alt bus mode powers up the TX regulator biasing circuitry and the rxdetect comparators. Needed if manually running the alt bus features" "0,1" newline bitfld.word 0x0 5.--6. "DRV_SOURCE_REG,Forces state of tx_data_source when OVRD_ALT_BUS is HIGH. 00 = serializer data or alt oscillator vp/vph/vphreg/vptx if selected 01 = jtag data differential 10 = LFPS oscillator differential 11 = jtag data common mode drive for test" "serializer data or alt oscillator..,jtag data differential,?,?" newline bitfld.word 0x0 4. "JTAG_DATA_REG,Forces state of jtag_data when OVRD_ALT_BUS is HIGH" "0,1" newline bitfld.word 0x0 1.--3. "TX_RINGO_CNTRL,Enables and connects the various test oscillators to the transmit pins must set drv_source_reg bus correctly. 0XX = All oscillators are disabled 100 = HV oscillator enabled 101 = SVT oscillator enabled 110 = LVT oscillator enabled 111.." "0,1,2,3,4,5,6,7" newline bitfld.word 0x0 0. "OVRD_ALT_BUS,Enables local overrides for alt-bus control signals: DRV_SOURCE_REG and JTAG_DATA_REG" "0,1" group.word 0x10B8++0x1 line.word 0x0 "LANE0_ANA_TX_ALT_AND_LOOPBACK,Register 6" newline hexmask.word.byte 0x0 8.--15. 1. "RESERVED_15_8,Reserved for Future use" newline bitfld.word 0x0 7. "OVRD_TX_LB,Enables the override of the tx_lb_en" "0,1" newline bitfld.word 0x0 6. "TX_LB_EN_REG,Forces state of tx_lb_en when OVRD_TX_LB is enabled" "0,1" newline bitfld.word 0x0 5. "ATB_VPTX,Connects vptx to atb_s_p and gd to atb_s_m" "0,1" newline bitfld.word 0x0 4. "ATB_VREG_TX,Connects TX regulator input reference to atb_s_p and gd to atb_s_m" "0,1" newline bitfld.word 0x0 3. "ATB_VDCCP,Connects vdcc_p to atb_s_p" "0,1" newline bitfld.word 0x0 2. "ATB_VDCCM,Connects vdcc_m to atb_s_m" "0,1" newline bitfld.word 0x0 1. "NOCONN_01,Reserved" "0,1" newline bitfld.word 0x0 0. "SELECT_PMIX_CLK,select pmix_clk for TX clock for ATE test mode" "0,1" group.word 0x10BC++0x1 line.word 0x0 "LANE0_ANA_TX_TX_ATB_REG,Register 7" newline hexmask.word.byte 0x0 8.--15. 1. "RESERVED_15_8,Reserved for Future use" newline bitfld.word 0x0 7. "ATB_PBIAS,Connect real pmos_bias voltage for TX PMOS driver pull up path to atb_s_p and local ground at the pmos_bias block to atb_s_m" "0,1" newline bitfld.word 0x0 6. "ATB_VCM_REP,Connect common mode replica voltage in pmos_bias block to atb_s_p and local ground to atb_s_m" "0,1" newline bitfld.word 0x0 5. "ATB_RXDETREF,Connect RX detect block reference voltage to atb_s_p and local ground to atb_s_m" "0,1" newline bitfld.word 0x0 4. "ATB_TXFP,Connect tx_p to atb_f_p" "0,1" newline bitfld.word 0x0 3. "ATB_TXFM,Connect tx_m to atb_f_m" "0,1" newline bitfld.word 0x0 2. "ATB_TXSP,Connect tx_p to atb_s_p" "0,1" newline bitfld.word 0x0 1. "ATB_TXSM,Connect tx_m to atb_s_m" "0,1" newline bitfld.word 0x0 0. "ATB_VCM,Connect tx_p/tx_m common mode voltage onto atb_s_p and local ground onto atb_s_m" "0,1" group.word 0x10C0++0x1 line.word 0x0 "LANE0_ANA_TX_TX_BOOST,Register 8" newline hexmask.word.byte 0x0 8.--15. 1. "RESERVED_15_8,Reserved for Future use" newline bitfld.word 0x0 7. "OVRD_VBOOST_EN,Enables the overrides on VBOOST_EN_REG" "0,1" newline bitfld.word 0x0 6. "VBOOST_EN_REG,Forces state of tx_vboost_en when OVRD_VBOOST_EN is HIGH" "0,1" newline bitfld.word 0x0 5. "VCON_EN_N,Forces state of vcon_en_n" "0,1" newline bitfld.word 0x0 4. "ATB_VBOOST,Connects vboost to atb_s_p and local ground to Atb_s_m" "0,1" newline bitfld.word 0x0 3. "ATB_VCMBOOST,Connects vcmboost to atb_s_p and local ground to atb_s_m." "0,1" newline bitfld.word 0x0 2. "ATB_F_VBOOST_REF,Enables forcing of tx_vboost_vref through atb_f_p from external" "0,1" newline bitfld.word 0x0 1. "OVRD_VREG_DECAP,Enables override of vreg_decap_en_n signal" "0,1" newline bitfld.word 0x0 0. "VREG_DECAP_EN_N_REG,Forces state of vreg_decap_en_n control signal. Controls whether extra decoupling is switched in for TX regulator output." "0,1" group.word 0x1100++0x1 line.word 0x0 "LANE0_DIG_RX_CDR_FSM_INIT_CTL,Control bits for CDR init phase portion" newline hexmask.word.byte 0x0 9.--15. 1. "RESERVED_15_9,Reserved for Future use" newline bitfld.word 0x0 8. "INIT_CNT_OVRD,Active high override enable bit to select the override INIT_CNT register 0 = Disabled 1 = Enabled" "Disabled,Enabled" newline hexmask.word.byte 0x0 0.--7. 1. "INIT_CNT,Override value for CDR Init Phase" group.word 0x1104++0x1 line.word 0x0 "LANE0_DIG_RX_CDR_FSM_TRACK_CTL,Control bits for CDR track phase portion" newline hexmask.word.byte 0x0 9.--15. 1. "RESERVED_15_9,Reserved for Future use" newline bitfld.word 0x0 8. "TRACK_CNT_OVRD,Active high override enable bit to select the override TRACK_CNT register 0 = Disabled 1 = Enabled" "Disabled,Enabled" newline hexmask.word.byte 0x0 0.--7. 1. "TRACK_CNT,Override value for CDR Track Phase" group.word 0x1108++0x1 line.word 0x0 "LANE0_DIG_RX_CDR_FSM_LOCK_CTL,Control bits for CDR lock phase portion" newline hexmask.word.byte 0x0 9.--15. 1. "RESERVED_15_9,Reserved for Future use" newline bitfld.word 0x0 8. "LOCK_CNT_OVRD,Active high override enable bit to select the override LOCK_CNT register 0 = Disabled 1 = Enabled" "Disabled,Enabled" newline hexmask.word.byte 0x0 0.--7. 1. "LOCK_CNT,Override value for CDR Lock Phase" repeat 9. (list 0x0 0x1 0x2 0x3 0x4 0x8 0x9 0xB 0xC )(list 0x0 0x4 0x8 0xC 0x10 0x20 0x24 0x2C 0x30 ) rgroup.word ($2+0x2000)++0x1 line.word 0x0 "PORT0_STAT_RO_$1,Status Register 0" newline hexmask.word 0x0 4.--15. 1. "RESERVED_15_4,Reserved for Future use" newline bitfld.word 0x0 3. "PLL_LOCK,analog PLL Lock Signal" "0,1" newline bitfld.word 0x0 2. "RX_SQUELCH,analog RX Squelch Signal" "0,1" newline bitfld.word 0x0 1. "RESERVED_1,Reserved" "0,1" newline bitfld.word 0x0 0. "RESERVED_0,Reserved" "0,1" repeat.end repeat 7. (list 0x5 0x6 0x7 0xA 0xD 0xE 0xF )(list 0x0 0x4 0x8 0x14 0x20 0x24 0x28 ) rgroup.word ($2+0x2014)++0x1 line.word 0x0 "PORT0_STAT_RO_$1,Status Register 5" newline hexmask.word 0x0 4.--15. 1. "RESERVED_15_4,Reserved for Future use" newline hexmask.word.byte 0x0 0.--3. 1. "DATAOUT,UTMI+ Output DATAOUT" repeat.end repeat 2. (list 0x0 0x6 )(list 0x0 0x18 ) group.word ($2+0x2040)++0x1 line.word 0x0 "PORT0_OVRD_RW_$1,Override Register 0" newline hexmask.word.byte 0x0 8.--15. 1. "RESERVED_15_8,Reserved for Future use" newline hexmask.word.byte 0x0 4.--7. 1. "OVERRD_ADDR_OVRD_EN,Override Enable for overrd_addr [7:4]" newline hexmask.word.byte 0x0 0.--3. 1. "OVERRD_ADDR,Analog Test Control Override Address [3:0]" repeat.end repeat 10. (list 0x1 0x2 0x3 0x4 0x8 0x9 0xA 0xB 0xE 0xF )(list 0x0 0x4 0x8 0xC 0x1C 0x20 0x24 0x28 0x34 0x38 ) group.word ($2+0x2044)++0x1 line.word 0x0 "PORT0_OVRD_RW_$1,Override Register 1" newline hexmask.word.byte 0x0 8.--15. 1. "RESERVED_15_8,Reserved for Future use" newline bitfld.word 0x0 7. "VBUS_VALID_PU_OVRD_EN,Override Enable for vbus_valid_pu" "0,1" newline bitfld.word 0x0 6. "OTG_PU_OVRD_EN,Override Enable for otg_pu" "0,1" newline bitfld.word 0x0 5. "TX_VREF_VREG_PU_OVRD_EN,Override Enable for tx_vref_vreg_pu" "0,1" newline bitfld.word 0x0 4. "SQRX_PU_OVRD_EN,Override Enable for sqrx_pu" "0,1" newline bitfld.word 0x0 3. "VBUS_VALID_PU,DRVVBUS Input" "0,1" newline bitfld.word 0x0 2. "OTG_PU,OTGDISABLE Input" "0,1" newline bitfld.word 0x0 1. "TX_VREF_VREG_PU,TX hs_driver Comparator Power Up" "0,1" newline bitfld.word 0x0 0. "SQRX_PU,RX squelch Comparator Power Up" "0,1" repeat.end group.word 0x2054++0x1 line.word 0x0 "PORT0_OVRD_RW_5,Override Register 5" newline hexmask.word.byte 0x0 8.--15. 1. "RESERVED_15_8,Reserved for Future use" newline bitfld.word 0x0 6.--7. "XO_CLK_DIV_OVRD_EN,Override Enable for xo_clk_div" "0,1,2,3" newline bitfld.word 0x0 5. "MSTR_OVERRD_BIT_OVRD_EN,Override Enable for mstr_overrd_bit" "0,1" newline bitfld.word 0x0 4. "OVERRD_ADDR_4_OVRD_EN,Override Enable for overrd_addr_4" "0,1" newline bitfld.word 0x0 2.--3. "XO_CLK_DIV,setting reference clock division" "0,1,2,3" newline bitfld.word 0x0 1. "MSTR_OVERRD_BIT,Analog Test Control Master Override" "0,1" newline bitfld.word 0x0 0. "OVERRD_ADDR_4,Analog Test Control Override Address [4]" "0,1" group.word 0x205C++0x1 line.word 0x0 "PORT0_OVRD_RW_7,Override Register 7" newline hexmask.word.byte 0x0 8.--15. 1. "RESERVED_15_8,Reserved for Future use" newline bitfld.word 0x0 7. "TX_LS_EN_OVRD_EN,Override Enable for tx_ls_en" "0,1" newline bitfld.word 0x0 4.--6. "PWR_SEQ_CLK_DIV_OVRD_EN,Override Enable for pwr_seq_clk_div" "0,1,2,3,4,5,6,7" newline bitfld.word 0x0 3. "TX_LS_EN,TX LS Enable" "0,1" newline bitfld.word 0x0 0.--2. "PWR_SEQ_CLK_DIV,setting power_sequence division" "0,1,2,3,4,5,6,7" group.word 0x2070++0x1 line.word 0x0 "PORT0_OVRD_RW_12,Override Register 12" newline hexmask.word.byte 0x0 8.--15. 1. "RESERVED_15_8,Reserved for Future use" newline bitfld.word 0x0 7. "RES_ACK_OUT_OVRD_EN,Override Enable for res_ack_out" "0,1" newline bitfld.word 0x0 5.--6. "PLL_CLK_DIV_OVRD_EN,Override Enable for pll_clk_div" "0,1,2,3" newline bitfld.word 0x0 4. "PLL_RESET_OVRD_EN,Override Enable for pll_reset" "0,1" newline bitfld.word 0x0 3. "RES_ACK_OUT,Ack resistor tune external requirement" "0,1" newline bitfld.word 0x0 1.--2. "PLL_CLK_DIV,setting MPLL division" "0,1,2,3" newline bitfld.word 0x0 0. "PLL_RESET,MPLL gear_shift" "0,1" group.word 0x2074++0x1 line.word 0x0 "PORT0_OVRD_RW_13,Override Register 13" newline hexmask.word.byte 0x0 8.--15. 1. "RESERVED_15_8,Reserved for Future use" newline bitfld.word 0x0 7. "BIST_MODE_OVRD_EN,Override Enable for bist_mode" "0,1" newline bitfld.word 0x0 6. "TEST_PKT_RPT_OVRD_EN,Override Enable for test_pkt_rpt" "0,1" newline bitfld.word 0x0 4.--5. "XO_CLK_SEL_OVRD_EN,Override Enable for xo_clk_sel" "0,1,2,3" newline bitfld.word 0x0 3. "BIST_MODE,BIST Mode" "0,1" newline bitfld.word 0x0 2. "TEST_PKT_RPT,BIST Test Packet Mode" "0,1" newline bitfld.word 0x0 0.--1. "XO_CLK_SEL,Reference Clock Selection" "0,1,2,3" rgroup.word 0x8000++0x1 line.word 0x0 "SUPX_DIG_IDCODE_LO,Low 16 bits of IDCODE" newline hexmask.word 0x0 0.--15. 1. "DATA," rgroup.word 0x8004++0x1 line.word 0x0 "SUPX_DIG_IDCODE_HI,High 16 bits of IDCODE" newline hexmask.word 0x0 0.--15. 1. "DATA," group.word 0x8008++0x1 line.word 0x0 "SUPX_DIG_DEBUG,Debug controls" newline hexmask.word 0x0 7.--15. 1. "RESERVED_15_7,Reserved for Future use" newline bitfld.word 0x0 5.--6. "DTB_SEL,The lane DTB's are OR'd together with the support DTB signals selected with the below encodings 0 - none 1 - reset_ctl DTB output 2 - scope DTB output 3 - rtune DTB output" "none,reset_ctl DTB output,scope DTB output,rtune DTB output" newline hexmask.word.byte 0x0 0.--4. 1. "TX_VREF_SEL," group.word 0x800C++0x1 line.word 0x0 "SUPX_DIG_RTUNE_DEBUG,Resistor tuning debug controls" newline rbitfld.word 0x0 15. "RESERVED_15_15,Reserved for Future use" "0,1" newline hexmask.word 0x0 5.--14. 1. "VALUE,Value to use when triggering SET_VAL field only the 6 LSB's are used when setting rx or tx cal values (USER2 - read-write and custom)" newline bitfld.word 0x0 3.--4. "TYPE,Type of manual tuning or register read/write to execute 0 - ADC or read/write rt_value 1 - Rx tune or read/write rx_cal_val (only 6 bits) 2 - Tx tune or read/write tx_cal_val (only 6 bits) 3 - Resref detect (no affect when triggering SET_VAL.." "ADC,Rx tune,read-write and custom),Resref detect" newline bitfld.word 0x0 2. "SET_VAL,Set value Write to a 1 to manually write the register specified by the TYPE field to the value in the VALUE field (USER2 - read-write and custom)" "0,1" newline bitfld.word 0x0 1. "MAN_TUNE,Write to a 1 to do a manual tuning specified by TYPE field starting a manual tune while a tune is currently running can cause unpredictable results. For use only when you know the state of the rtune circuit. (USER2 - read-write and custom)" "0,1" newline bitfld.word 0x0 0. "FLIP_COMP,Invert analog comparator output (USER2 - read-write and custom)" "0,1" rgroup.word 0x8010++0x1 line.word 0x0 "SUPX_DIG_RTUNE_STAT,Resistor tuning register status" newline hexmask.word.byte 0x0 10.--15. 1. "RESERVED_15_10,Reserved for Future use" newline hexmask.word 0x0 0.--9. 1. "STAT,Current value of the register specifed by the TYPE field in the debug control register. Set the TYPE field in the DEBUG register and then do a read of this register. (RU - read-only volatile)" group.word 0x8014++0x1 line.word 0x0 "SUPX_DIG_SS_PHASE,Current MPLL phase selector value" newline bitfld.word 0x0 13.--15. "REF_SEL_DIV,Reference Divisor to get better resolution and lower PPM errors when synthesizing from a non-integer reference clock. NOTE: Default value is 4. One is added in hardware to give a range of 1 to 8. (volatile and 2 reads needed to read value)" "0,1,2,3,4,5,6,7" newline bitfld.word 0x0 12. "PH_SEL,Phase Mixer Clock select. 1: is pmix. 0 is VCO. (volatile and 2 reads needed to read value)" "?,is pmix" newline bitfld.word 0x0 11. "ZERO_FREQ,Zero frequency register. NOTES: Must be set for PHASE writes to stick (volatile and 2 reads needed to read value)" "0,1" newline hexmask.word 0x0 2.--10. 1. "VAL,Phase value from zero reference (volatile and 2 reads needed to read value)" newline bitfld.word 0x0 0.--1. "DTHR,Bits below the useful resolution (volatile and 2 reads needed to read value)" "0,1,2,3" group.word 0x8018++0x1 line.word 0x0 "SUPX_DIG_SS_FREQ,Frequency Control for Spread Spectrum" newline rbitfld.word 0x0 15. "RESERVED_15_15,Reserved for Future use" "0,1" newline bitfld.word 0x0 14. "FREQ_OVRD,Frequency Reigster Override. NOTE: Must be set for PHASE writes to stick (volatile and 2 reads needed to read value)" "0,1" newline hexmask.word.byte 0x0 7.--13. 1. "FREQ_PK,Peak Frequency Value (for changing direction) (volatile and 2 reads needed to read value)" newline hexmask.word.byte 0x0 0.--6. 1. "FREQ_CNT_INIT,Initial Frequency Counter Value (volatile and 2 reads needed to read value)" group.word 0x801C++0x1 line.word 0x0 "SUPX_DIG_HSP_SS_PHASE,Current HSP_PMIX SSC phase sel value" newline hexmask.word.byte 0x0 11.--15. 1. "RESERVED_15_11,Reserved for Future use" newline hexmask.word.byte 0x0 4.--10. 1. "VAL,SSC phase value from zero reference (volatile and 2 reads needed to read value)" newline hexmask.word.byte 0x0 0.--3. 1. "DTHR,Bits below the useful resolution (volatile and 2 reads needed to read value)" group.word 0x8020++0x1 line.word 0x0 "SUPX_DIG_MPLL_CNT_CTL,Control for fixed or variable MPLL Count Selection" newline hexmask.word 0x0 1.--15. 1. "RESERVED_15_1,Reserved for Future use" newline bitfld.word 0x0 0. "VAR_CNT_EN,Selects variable count when enabled (Default = fixed count)" "0,1" group.word 0x8024++0x1 line.word 0x0 "SUPX_DIG_CR_PARA_ALU_CTL,Control for CR Parallel ALU access" newline hexmask.word 0x0 5.--15. 1. "RESERVED_15_5,Reserved for Future use" newline hexmask.word.byte 0x0 1.--4. 1. "CR_PARA_ALU_OPCODE,Opcode for the ALU when CR para access is enabled. Valid opcodes are as follows: 0 - Zero the accumulator 1 - Add control register read result to accumulator 2 - Add control register write data to accumulator 3 - Shift accumulator left.." newline bitfld.word 0x0 0. "CR_PARA_ALU_ACCESS_EN,Enable access to the ALU through the CR parallel bus." "0,1" rgroup.word 0x8028++0x1 line.word 0x0 "SUPX_DIG_CR_PARA_ALU_FLAGS,Flags from the ALU when CR para access is enabled." newline hexmask.word 0x0 4.--15. 1. "RESERVED_15_4,Reserved for Future use" newline hexmask.word.byte 0x0 0.--3. 1. "DATA,Flags from the ALU when CR para access is enabled. Valid ALU flags: 0 - Signedness used for next ADD_PHSEL command. (1=signed 0=unsigned) 1 - Signedness for ADD_PHSEL command has been chosen by a previous ADD_PHSEL command. 2 - Error detected.." group.word 0x8040++0x1 line.word 0x0 "SUPX_DIG_ATEOVRD,Override values for incoming controls from ASIC" newline hexmask.word 0x0 3.--15. 1. "RESERVED_15_3,Reserved for Future use" newline bitfld.word 0x0 2. "ATEOVRD_EN,Override enable for ATE signals. NOTE: This register is only accessible through cregs. Does not retain state during reset or ATPG. (USER2 - read-write and custom)" "0,1" newline bitfld.word 0x0 1. "REF_USB2_EN,Override value for USB HSP PHY ref_clk enable. (USER2 - read-write and custom)" "0,1" newline bitfld.word 0x0 0. "REF_CLKDIV2,Override value for SSP ref_clk pre-scaler. (USER2 - read-write and custom)" "0,1" group.word 0x8044++0x1 line.word 0x0 "SUPX_DIG_MPLL_OVRD_IN_LO,Override values for incoming RTUNE and MPLL controls from ASIC" newline bitfld.word 0x0 15. "RES_ACK_IN_OVRD,Override enable for res_ack_in" "0,1" newline bitfld.word 0x0 14. "RES_ACK_IN,Override value for res_ack_in" "0,1" newline bitfld.word 0x0 13. "RES_REQ_IN_OVRD,Override enable for res_req_in" "0,1" newline bitfld.word 0x0 12. "RES_REQ_IN,Override value for res_req_in" "0,1" newline bitfld.word 0x0 11. "RTUNE_REQ_OVRD,Override enable for rtune_req" "0,1" newline bitfld.word 0x0 10. "RTUNE_REQ,Override value for rtune_req" "0,1" newline bitfld.word 0x0 9. "MPLL_MULTIPLIER_OVRD,Override enable for mpll_multipler" "0,1" newline hexmask.word.byte 0x0 2.--8. 1. "MPLL_MULTIPLIER,Override value for mpll_multipler" newline bitfld.word 0x0 1. "MPLL_EN_OVRD,Override enable for mpll_en" "0,1" newline bitfld.word 0x0 0. "MPLL_EN,Override value for mpll_en" "0,1" group.word 0x8048++0x1 line.word 0x0 "SUPX_DIG_MPLL_OVRD_IN_HI,Override values for incoming VBOOST LVL and MPLL controls from ASIC" newline bitfld.word 0x0 13.--15. "TX_VBOOST_LVL,Override value for tx_vboost_lvl. Override enabled using LEVEL_EN from LEVEL_OVRD_IN register." "0,1,2,3,4,5,6,7" newline bitfld.word 0x0 12. "MPLL_REFSSC_CLK_EN_OVRD,Override enable for mpll_refssc_clk_en" "0,1" newline bitfld.word 0x0 11. "MPLL_REFSSC_CLK_EN,Override value for mpll_refssc_clk_en" "0,1" newline bitfld.word 0x0 10. "MPLL_RST,Reset the MPLL state machine Writing the register with this bit set will reset the MPLL power up/down FSM regardless of the current state of the register bit." "0,1" newline bitfld.word 0x0 9. "FSEL_OVRD,Override enable for fsel[2:0]" "0,1" newline bitfld.word 0x0 6.--8. "FSEL,Override value for fsel [2:0]" "0,1,2,3,4,5,6,7" newline bitfld.word 0x0 5. "MPLL_WORD_CLK_EN_OVRD,Override enable for mpll_word_clk_en" "0,1" newline bitfld.word 0x0 4. "MPLL_WORD_CLK_EN,Override value for mpll_word_clk_en" "0,1" newline bitfld.word 0x0 3. "MPLL_DWORD_CLK_EN_OVRD,Override enable for mpll_dword_clk_en" "0,1" newline bitfld.word 0x0 2. "MPLL_DWORD_CLK_EN,Override value for mpll_dword_clk_en" "0,1" newline bitfld.word 0x0 1. "MPLL_QWORD_CLK_EN_OVRD,Override enable for mpll_qword_clk_en" "0,1" newline bitfld.word 0x0 0. "MPLL_QWORD_CLK_EN,Override value for mpll_qword_clk_en" "0,1" group.word 0x804C++0x1 line.word 0x0 "SUPX_DIG_SSC_OVRD_IN,Override values for incoming SSC controls from ASIC" newline rbitfld.word 0x0 14.--15. "RESERVED_15_14,Reserved for Future use" "0,1,2,3" newline bitfld.word 0x0 13. "SSC_OVRD_IN_EN,Override enable for Spread Spectrum generator." "0,1" newline bitfld.word 0x0 12. "SSC_EN,Override value for SSC enable." "0,1" newline bitfld.word 0x0 9.--11. "SSC_RANGE,Override value for SSC modulation range." "0,1,2,3,4,5,6,7" newline hexmask.word 0x0 0.--8. 1. "SSC_REF_CLK_SEL,Override value for reference clock scaling" group.word 0x8050++0x1 line.word 0x0 "SUPX_DIG_BS_OVRD_IN,Override values for incoming BS controls from ASIC" newline hexmask.word.byte 0x0 12.--15. 1. "RESERVED_15_12,Reserved for Future use" newline bitfld.word 0x0 11. "EN,Enable override values for all inputs controlled by this register" "0,1" newline bitfld.word 0x0 10. "INVERT,Override value for bs_invert" "0,1" newline bitfld.word 0x0 9. "INIT,Override value for bs_init" "0,1" newline bitfld.word 0x0 8. "HIGHZ,Override value for bs_highz" "0,1" newline bitfld.word 0x0 7. "CLAMP,Override value for bs_clamp" "0,1" newline bitfld.word 0x0 6. "EXTEST_AC,Override value for bs_extest_ac" "0,1" newline bitfld.word 0x0 5. "EXTEST,Override value for bs_extest" "0,1" newline bitfld.word 0x0 4. "PRELOAD,Override value for bs_preload" "0,1" newline bitfld.word 0x0 3. "UPDATE_DR,Override value for bs_update_dr" "0,1" newline bitfld.word 0x0 2. "CAPTURE_DR,Override value for bs_capture_dr" "0,1" newline bitfld.word 0x0 1. "SHIFT_DR,Override value for bs_shift_dr" "0,1" newline bitfld.word 0x0 0. "IN,Override value for bs_in" "0,1" group.word 0x8054++0x1 line.word 0x0 "SUPX_DIG_LEVEL_OVRD_IN,Override values for acjt_level and los_level" newline bitfld.word 0x0 13.--15. "LOS_BIAS,Override value for los_bias" "0,1,2,3,4,5,6,7" newline bitfld.word 0x0 12. "MPLL_HALF_RATE_OVRD,Enable override value for mpll_half_rate" "0,1" newline bitfld.word 0x0 11. "MPLL_HALF_RATE,Override value for mpll_half_rate" "0,1" newline bitfld.word 0x0 10. "LEVEL_EN,Enable override values for tx_vboost_lvl/los_bias/los_level/acjt_level inputs controlled by this and MPLL_OVRD_IN_HI registers" "0,1" newline hexmask.word.byte 0x0 5.--9. 1. "ACJT_LEVEL,Override value for acjt_level" newline hexmask.word.byte 0x0 0.--4. 1. "LOS_LEVEL,Override value for los_level" group.word 0x8058++0x1 line.word 0x0 "SUPX_DIG_SUP_OVRD_OUT,Override values for support block" newline hexmask.word.byte 0x0 10.--15. 1. "RESERVED_15_10,Reserved for Future use" newline bitfld.word 0x0 9. "MPLL_STATE_OVRD,Override enable for mpll_state output" "0,1" newline bitfld.word 0x0 8. "MPLL_STATE,Override value for mpll_state output" "0,1" newline bitfld.word 0x0 7. "BS_OUT_OVRD,Override enable for bs_out output" "0,1" newline bitfld.word 0x0 6. "BS_OUT,Override value for bs_out output" "0,1" newline bitfld.word 0x0 5. "RTUNE_ACK_OVRD,Override enable for rtune_ack output" "0,1" newline bitfld.word 0x0 4. "RTUNE_ACK,Override value for rtune_ack output" "0,1" newline bitfld.word 0x0 3. "RES_REQ_OUT_OVRD,Override enable for res_req_out output" "0,1" newline bitfld.word 0x0 2. "RES_REQ_OUT,Override value for res_req_out output" "0,1" newline bitfld.word 0x0 1. "RES_ACK_OUT_OVRD,Override enable for res_ack_out output" "0,1" newline bitfld.word 0x0 0. "RES_ACK_OUT,Override value for res_ack_out output" "0,1" rgroup.word 0x805C++0x1 line.word 0x0 "SUPX_DIG_MPLL_ASIC_IN,Current values for incoming MPLL controls from ASIC" newline bitfld.word 0x0 15. "RESERVED_15_15,Reserved for Future use" "0,1" newline bitfld.word 0x0 14. "MPLL_REFSSC_CLK_EN,Value from ASIC for mpll_refssc_clk_en (RU - read-only volatile)" "0,1" newline bitfld.word 0x0 13. "MPLL_WORD_CLK_EN,Value from ASIC for mpll_word_clk_en (RU - read-only volatile)" "0,1" newline bitfld.word 0x0 12. "MPLL_DWORD_CLK_EN,Value from ASIC for mpll_dword_clk_en (RU - read-only volatile)" "0,1" newline bitfld.word 0x0 11. "MPLL_QWORD_CLK_EN,Value from ASIC for mpll_qword_clk_en (RU - read-only volatile)" "0,1" newline bitfld.word 0x0 10. "RES_ACK_IN,Value from ASIC for res_ack_in (RU - read-only volatile)" "0,1" newline bitfld.word 0x0 9. "RES_REQ_IN,Value from ASIC for res_req_in (RU - read-only volatile)" "0,1" newline bitfld.word 0x0 8. "RTUNE_REQ,Value from ASIC for rtune_req (RU - read-only volatile)" "0,1" newline hexmask.word.byte 0x0 1.--7. 1. "MPLL_MULTIPLIER,Value from ASIC for mpll_multiplier (RU - read-only volatile)" newline bitfld.word 0x0 0. "MPLL_EN,Value from ASIC for mpll_en (RU - read-only volatile)" "0,1" rgroup.word 0x8060++0x1 line.word 0x0 "SUPX_DIG_BS_ASIC_IN,Current values for incoming boundary scan controls from ASIC" newline bitfld.word 0x0 14.--15. "RESERVED_15_14,Reserved for Future use" "0,1,2,3" newline bitfld.word 0x0 11.--13. "TX_VBOOST_LVL,Value from ASIC for tx_vboost_lvl -- Not as bs_* signal but we're out of bits. (RU - read-only volatile)" "0,1,2,3,4,5,6,7" newline bitfld.word 0x0 10. "INVERT,Value from ASIC for bs_invert (RU - read-only volatile)" "0,1" newline bitfld.word 0x0 9. "INIT,Value from ASIC for bs_init (RU - read-only volatile)" "0,1" newline bitfld.word 0x0 8. "HIGHZ,Value from ASIC for bs_highz (RU - read-only volatile)" "0,1" newline bitfld.word 0x0 7. "CLAMP,Value from ASIC for bs_clamp (RU - read-only volatile)" "0,1" newline bitfld.word 0x0 6. "EXTEST_AC,Value from ASIC for bs_extest_ac (RU - read-only volatile)" "0,1" newline bitfld.word 0x0 5. "EXTEST,Value from ASIC for bs_extest (RU - read-only volatile)" "0,1" newline bitfld.word 0x0 4. "PRELOAD,Value from ASIC for bs_preload (RU - read-only volatile)" "0,1" newline bitfld.word 0x0 3. "UPDATE_DR,Value from ASIC for bs_update_dr (RU - read-only volatile)" "0,1" newline bitfld.word 0x0 2. "CAPTURE_DR,Value from ASIC for bs_capture_dr (RU - read-only volatile)" "0,1" newline bitfld.word 0x0 1. "SHIFT_DR,Value from ASIC for bs_shift_dr (RU - read-only volatile)" "0,1" newline bitfld.word 0x0 0. "IN,Value from ASIC for bs_in (RU - read-only volatile)" "0,1" rgroup.word 0x8064++0x1 line.word 0x0 "SUPX_DIG_LEVEL_ASIC_IN,Current values for incoming los/acjt level. MPLL half rate mode and vreg bypass from ASIC" newline bitfld.word 0x0 15. "RESERVED_15_15,Reserved for Future use" "0,1" newline bitfld.word 0x0 12.--14. "LOS_BIAS,Value from ASIC for los_bias (RU - read-only volatile)" "0,1,2,3,4,5,6,7" newline bitfld.word 0x0 11. "MPLL_HALF_RATE,Value from ASIC for mpll_half_rate (RU - read-only volatile)" "0,1" newline bitfld.word 0x0 10. "VREG_BYPASS,Value from ASIC for vreg_bypass (RU - read-only volatile)" "0,1" newline hexmask.word.byte 0x0 5.--9. 1. "ACJT_LEVEL,Value from ASIC for acjt_level (RU - read-only volatile)" newline hexmask.word.byte 0x0 0.--4. 1. "LOS_LEVEL,Value from ASIC for los_level (RU - read-only volatile)" rgroup.word 0x8068++0x1 line.word 0x0 "SUPX_DIG_SSC_ASIC_IN,Current values for incoming SSC controls from ASIC" newline bitfld.word 0x0 15. "SS_EN,Value from ASIC for ssc_en (RU - read-only volatile)" "0,1" newline bitfld.word 0x0 12.--14. "SSC_RANGE,Value from ASIC for ssc_range (RU - read-only volatile)" "0,1,2,3,4,5,6,7" newline hexmask.word 0x0 3.--11. 1. "SSC_REF_CLK_SEL,Value from ASIC for ssc_ref_clk_sel (RU - read-only volatile)" newline bitfld.word 0x0 0.--2. "FSEL,Value from ASIC for fsel (RU - read-only volatile)" "0,1,2,3,4,5,6,7" rgroup.word 0x806C++0x1 line.word 0x0 "SUPX_DIG_SUP_ASIC_OUT,Current values for outgoing support block controls to ASIC" newline hexmask.word 0x0 5.--15. 1. "RESERVED_15_5,Reserved for Future use" newline bitfld.word 0x0 4. "MPLL_STATE,Value from PHY for mpll_state output (RU - read-only volatile)" "0,1" newline bitfld.word 0x0 3. "BS_OUT,Value from PHY for bs_out output (RU - read-only volatile)" "0,1" newline bitfld.word 0x0 2. "RTUNE_ACK,Value from PHY for rtune_ack output (RU - read-only volatile)" "0,1" newline bitfld.word 0x0 1. "RES_REQ_OUT,Value from PHY for res_req_out output (RU - read-only volatile)" "0,1" newline bitfld.word 0x0 0. "RES_ACK_OUT,Value from PHY for res_ack_out output (RU - read-only volatile)" "0,1" rgroup.word 0x8070++0x1 line.word 0x0 "SUPX_DIG_ATEOVRD_STATUS,USB3_SUPX_DIG_ATEOVRD_STATUS" newline hexmask.word.byte 0x0 10.--15. 1. "RESERVED_15_10,Reserved for Future use" newline bitfld.word 0x0 8.--9. "DTB_OUT,Value from dtb_out bus. (RU - read-only volatile)" "0,1,2,3" newline bitfld.word 0x0 7. "REF_SSP_EN,Value from ASIC for ref_ssp_en. (RU - read-only volatile)" "0,1" newline bitfld.word 0x0 6. "REF_USE_PAD,Value from ASIC for ref_use_pad. (RU - read-only volatile)" "0,1" newline bitfld.word 0x0 5. "PHY_RESET_IN,Value from ASIC for phy_reset (RU - read-only volatile)" "0,1" newline bitfld.word 0x0 4. "REF_CLKDIV2_IN,Value from ASIC for ref_clkdiv2 (RU - read-only volatile)" "0,1" newline bitfld.word 0x0 3. "REF_USB2_EN_IN,Value from ASIC for ref_usb2_en (RU - read-only volatile)" "0,1" newline bitfld.word 0x0 2. "ATEOVRD_EN,When set values from ATEOVRD register are being sent to PHY (RU - read-only volatile)" "0,1" newline bitfld.word 0x0 1. "REF_CLKDIV2_OUT,Value from ATEOVRD for ref_clkdiv2 (RU - read-only volatile)" "0,1" newline bitfld.word 0x0 0. "REF_USB2_EN_OUT,Value from ATEOVRD for ref_usb2_en (RU - read-only volatile)" "0,1" group.word 0x8074++0x1 line.word 0x0 "SUPX_DIG_HSP_OVRD_IN,Override values for HSP" newline hexmask.word 0x0 4.--15. 1. "RESERVED_15_4,Reserved for Future use" newline bitfld.word 0x0 3. "HSP_PLL_OVRD,Override enable for HSP pll_pu signal" "0,1" newline bitfld.word 0x0 2. "HSP_PLL_PU,Override value for HSP pll_pu signal" "0,1" newline bitfld.word 0x0 1. "HSP_BIAS_OVRD,Override enable for HSP bias_pu signal" "0,1" newline bitfld.word 0x0 0. "HSP_BIAS_PU,Override value for HSP bias_pu signal" "0,1" rgroup.word 0x8078++0x1 line.word 0x0 "SUPX_DIG_HSP_ASIC_IN,Current values for incoming HSP & REF XO controls from ASIC" newline hexmask.word 0x0 4.--15. 1. "RESERVED_15_4,Reserved for Future use" newline bitfld.word 0x0 3. "REF_USE_XO,Value from ASIC for ref_use_xo (RU - read-only volatile)" "0,1" newline bitfld.word 0x0 2. "REF_XO_EN,Value from ASIC for ref_xo_en (RU - read-only volatile)" "0,1" newline bitfld.word 0x0 1. "HSP_PLL_PU,Value from ASIC for hsp_pll_pu (RU - read-only volatile)" "0,1" newline bitfld.word 0x0 0. "HSP_BIAS_PU,Value from ASIC for hsp_bias_pu (RU - read-only volatile)" "0,1" group.word 0x8080++0x1 line.word 0x0 "SUPX_DIG_SCOPE_ENABLES,Scope Counter configuration" newline hexmask.word 0x0 5.--15. 1. "RESERVED_15_5,Reserved for Future use" newline bitfld.word 0x0 3.--4. "LANE_SELECT,Scope Counter Input select" "0,1,2,3" newline bitfld.word 0x0 2. "MASK_SATURATION_MODE,Method of mask saturation. When 1 Saturate when the first mask_counter reaches sample_limit. When 0 Saturate when all mask_counters have reached sample_limit." "0,1" newline bitfld.word 0x0 1. "MASK_EN,Enable scope_mask input for tracking count values. Clears registers when deasserted." "0,1" newline bitfld.word 0x0 0. "XOR_EN,Use scope_xor input for count values." "0,1" group.word 0x8084++0x1 line.word 0x0 "SUPX_DIG_SCOPE_SAMPLES,Number of samples to count" newline hexmask.word 0x0 0.--15. 1. "SAMPLES,Number of Sample to count." rgroup.word 0x8088++0x1 line.word 0x0 "SUPX_DIG_SCOPE_COUNT,Results of scope counting" newline hexmask.word 0x0 0.--15. 1. "COUNT,A write to this register will start the counting process The value of FFFF indicates counting still in progress. Asserting MASK_EN will also start the counting if in MASK mode. (RU - read-only volatile)" group.word 0x808C++0x1 line.word 0x0 "SUPX_DIG_SCOPE_CTL,Masked scope counting Start and Status" newline hexmask.word 0x0 2.--15. 1. "RESERVED_15_2,Reserved for Future use" newline bitfld.word 0x0 1. "MASK_START,A write to this register will start the counting process The value of FFFF indicates counting still in progress Write will trigger mask counting. (USER1 - read-write volatile)" "?,read-write volatile)" newline bitfld.word 0x0 0. "MASK_SATURATION,When assert mask registers have saturated. (USER1 - read-write volatile)" "?,read-write volatile)" repeat 8. (list 0x0 0x1 0xA 0xB 0x64 0x65 0x6E 0x6F )(list 0x0 0x4 0x8 0xC 0x10 0x14 0x18 0x1C ) group.word ($2+0x8090)++0x1 line.word 0x0 "SUPX_DIG_SCOPE_MASK_$1,Current count value for mask_000" newline hexmask.word 0x0 0.--15. 1. "MASK_VAL_000,Starting count value of mask register. (volatile and 2 reads needed to read value)" repeat.end group.word 0x80C0++0x1 line.word 0x0 "SUPX_ANA_MPLL_LOOP_CTL,MPLL loop control bits" newline hexmask.word.byte 0x0 8.--15. 1. "RESERVED_15_8,Reserved for Future use" newline hexmask.word.byte 0x0 4.--7. 1. "PROP_CNTRL,Charge pump proportional current setting" newline bitfld.word 0x0 2.--3. "INT_CNTRL,Charge pump integrating current setting" "0,1,2,3" newline bitfld.word 0x0 1. "GD,Measure MPLL local GD" "0,1" newline bitfld.word 0x0 0. "VMB,Measure MPLL Master Bias Voltage" "0,1" repeat 2. (list 0x1 0x2 )(list 0x0 0x4 ) group.word ($2+0x80C4)++0x1 line.word 0x0 "SUPX_ANA_MPLL_ATB_MEAS$1,ATB Select bits" newline hexmask.word.byte 0x0 8.--15. 1. "RESERVED_15_8,Reserved for Future use" newline bitfld.word 0x0 7. "VPSF,puts vpsf on atb_s_p" "0,1" newline bitfld.word 0x0 6. "VREF,puts vref from charge pump on atb_s_p" "0,1" newline bitfld.word 0x0 5. "VCNTRL,puts vcntrl on atb_s_m" "0,1" newline bitfld.word 0x0 4. "GD,puts gd on atb_s_m" "0,1" newline bitfld.word 0x0 3. "IVCO,puts VCO current/93 on atb_f_m" "0,1" newline bitfld.word 0x0 2. "VP,puts vpa on atb_s_m" "0,1" newline bitfld.word 0x0 1. "VP_CP,puts vp_cp on atb_s_p" "0,1" newline bitfld.word 0x0 0. "VREG_MPLL,puts vreg_mpll on atb_s_p" "0,1" repeat.end group.word 0x80CC++0x1 line.word 0x0 "SUPX_ANA_MPLL_OVRD,Local overrides" newline hexmask.word.byte 0x0 8.--15. 1. "RESERVED_15_8,Reserved for Future use" newline bitfld.word 0x0 7. "PWRON_LCL,local power_on value" "0,1" newline bitfld.word 0x0 6. "EN_PWRON_LCL,Enable local control of power_on" "0,1" newline bitfld.word 0x0 5. "GS_LCL,local gear_shift value" "0,1" newline bitfld.word 0x0 4. "EN_GS_LCL,Enable local control of gear_shift" "0,1" newline bitfld.word 0x0 3. "RST_LCL,local reset value" "0,1" newline bitfld.word 0x0 2. "EN_RST_LCL,enable local control of reset" "0,1" newline bitfld.word 0x0 1. "PMIX_CLK_SEL_LCL,local pmix_clk_sel value" "0,1" newline bitfld.word 0x0 0. "EN_PMIX_CLK_SEL_LCL,enable local control of pmix_clk_sel" "0,1" group.word 0x80D0++0x1 line.word 0x0 "SUPX_ANA_RTUNE_RTUNE_CTRL,RTUNE control bits" newline hexmask.word.byte 0x0 8.--15. 1. "RESERVED_15_8,Reserved for Future use" newline bitfld.word 0x0 7. "RT_PWRON_FRC_ON,When set forces RTUNE block to be on" "0,1" newline bitfld.word 0x0 6. "X4_FRC_OFF,When set do not multiply test current by 4" "0,1" newline bitfld.word 0x0 4.--5. "RT_DAC_MODE,Margin DAC mode control bits(00=powerdown 01=DAC drives atb_s_p/m directly 10=DAC drives atb_s_p/m to the RX in margining mode 11=illegal state)" "powerdown,DAC drives atb_s_p/m directly,?,?" newline bitfld.word 0x0 3. "RT_DAC_CHOP,Margin DAC chop control bit. ref to ssp analog engineering doc 8.5" "0,1" newline bitfld.word 0x0 2. "RT_ATB,RTUNE ATB mode control bit (1=RTUNE performs ADC on ATB input 0=not accessing ATB. refer to ssp analog engineering specification 8.1.4)" "not accessing ATB,RTUNE performs ADC on ATB input" newline bitfld.word 0x0 1. "RT_SEL_ATBP,RTUNE ATB sense input select bit (1=atb_s_p 0=atb_s_m)" "atb_s_m),atb_s_p" newline bitfld.word 0x0 0. "RT_SEL_ATBF,RTUNE ATB input select bit (1=atb_fm 0=atb_s_p/m)" "atb_s_p/m),atb_fm" group.word 0x80D4++0x1 line.word 0x0 "SUPX_ANA_ATB_SWITCHYARD_CTRL,ATB_SWITCHYARD control bits" newline hexmask.word.byte 0x0 8.--15. 1. "RESERVED_15_8,Reserved for Future use" newline bitfld.word 0x0 7. "ASM_GD,Connect gd to atb_s_m" "0,1" newline bitfld.word 0x0 6. "ASP_VP,Connect vp to atb_s_p" "0,1" newline bitfld.word 0x0 5. "ASP_VBG,Connect vbg to atb_s_p" "0,1" newline bitfld.word 0x0 4. "ASP_VPHREG,Connect vphreg to atb_s_m" "0,1" newline bitfld.word 0x0 3. "ATEST_AFM,drive ATEST from atb_f_m" "0,1" newline bitfld.word 0x0 2. "ATEST_AFP,drive ATEST from atb_f_p" "0,1" newline bitfld.word 0x0 1. "ATEST_ASM,Connet ATEST to atb_s_m" "0,1" newline bitfld.word 0x0 0. "ATEST_ASP,Connect ATEST to atb_s_p" "0,1" group.word 0x80D8++0x1 line.word 0x0 "SUPX_ANA_SSC_CLK_CNTRL,controls sscf reference clock rate" newline hexmask.word.byte 0x0 8.--15. 1. "RESERVED_15_8,Reserved for Future use" newline bitfld.word 0x0 7. "NC,Reserved" "0,1" newline hexmask.word.byte 0x0 0.--6. 1. "SSC_CLK_DIV125,set ssc reference clock to be 20MHz" group.word 0x80DC++0x1 line.word 0x0 "SUPX_ANA_HSP_CLK_DIG_CNTRL0,controls HSP phase clock. and resolution" newline hexmask.word.byte 0x0 8.--15. 1. "RESERVED_15_8,Reserved for Future use" newline bitfld.word 0x0 7. "NUM_OVERRIDE,Set the value to 1 to enable using values from creg bit 6 downto 0" "0,1" newline bitfld.word 0x0 4.--6. "GATE_PMIX_BITS,Set gate_pmix_bits to gate the corresponding MSB of the 7-bit PMIX phase select bits" "?,?,?,?,?,?,?,bit PMIX phase select bits" newline bitfld.word 0x0 3. "HALF_CLK_EN,Set to 1 for 1.25GHz updates to HSP PMIX. Set to 0 for 2.5GHz updates to PMIX." "0,1" newline bitfld.word 0x0 2. "UCLK_EN_N,Set to 1 to disable update clock. Set to 0 to enable update clock. When clock is enabled phase updates are allowed." "0,1" newline bitfld.word 0x0 1. "EN_HSPPMIX_VPMIX,Set to 1 to connect the regulated HSP PMIX supply to the atb_s_p bus" "0,1" newline bitfld.word 0x0 0. "EN_HSPPMIX_FRC_VPMIX,Set to 1 to force override of HSP PMIX regulator voltage to voltage on atb_s_m" "0,1" group.word 0x80E0++0x1 line.word 0x0 "SUPX_ANA_HSP_CLK_DIG_CNTRL1,Lower and Upper Phase Increment Values" newline hexmask.word.byte 0x0 8.--15. 1. "RESERVED_15_8,Reserved for Future use" newline hexmask.word.byte 0x0 4.--7. 1. "UPPER_INT,These bits are only used when num_override is set to 1. Upper integer for phase increments of 2.5 to 2.4 GHz conversion. This is the phase increment that is applied 6 times in every 25 for 1.25 GHz increments and 3 times in every 25 for 2.5GHz" newline hexmask.word.byte 0x0 0.--3. 1. "LOWER_INT,These bits are only used when num_override is set to 1. Lower integer for phase increments of 2.5 to 2.4 GHz conversion. This phase increment is applied 19 times in every 25 for 1.25 GHz increments and 22 times in every 25 for 2.5GHz." group.word 0x9000++0x1 line.word 0x0 "LANEX_DIG_TX_OVRD_IN_LO,Override values for incoming TX controls from ASIC" newline bitfld.word 0x0 15. "LANE_IF_WIDTH_OVRD,Override enable for lane interface width" "0,1" newline bitfld.word 0x0 14. "LANE_IF_WIDTH,Override value for lane interface width" "0,1" newline bitfld.word 0x0 13. "TX_DETECT_RX_REQ_OVRD,Override enable for tx_detect_rx_req" "0,1" newline bitfld.word 0x0 12. "TX_DETECT_RX_REQ,Override value for tx_detect_rx_req" "0,1" newline bitfld.word 0x0 11. "TX_BEACON_EN_OVRD,Override enable for tx_beacon_en" "0,1" newline bitfld.word 0x0 10. "TX_BEACON_EN,Override value for tx_beacon_en" "0,1" newline bitfld.word 0x0 9. "TX_CM_EN_OVRD,Override enable for tx_cm_en" "0,1" newline bitfld.word 0x0 8. "TX_CM_EN,Override value for tx_cm_en" "0,1" newline bitfld.word 0x0 7. "TX_EN_OVRD,Override enable for tx_en" "0,1" newline bitfld.word 0x0 6. "TX_EN,Override value for tx_en" "0,1" newline bitfld.word 0x0 5. "TX_DATA_EN_OVRD,Override enable for tx_data_en" "0,1" newline bitfld.word 0x0 4. "TX_DATA_EN,Override value for tx_data_en" "0,1" newline bitfld.word 0x0 3. "TX_INVERT_OVRD,Override enable for tx_invert" "0,1" newline bitfld.word 0x0 2. "TX_INVERT,Override value for tx_invert" "0,1" newline bitfld.word 0x0 1. "TX_LOOPBK_EN_OVRD,Override enable for loopbk_en" "0,1" newline bitfld.word 0x0 0. "LOOPBK_EN,Override value for loopbk_en" "0,1" group.word 0x9004++0x1 line.word 0x0 "LANEX_DIG_TX_OVRD_IN_HI,Override values for incoming TX controls from ASIC" newline hexmask.word.byte 0x0 10.--15. 1. "RESERVED_15_10,Reserved for Future use" newline bitfld.word 0x0 9. "TX_VBOOST_EN_OVRD,Override enable for tx_vboost_en" "0,1" newline bitfld.word 0x0 8. "TX_VBOOST_EN,Override value for tx_vboost_en" "0,1" newline bitfld.word 0x0 7. "TX_RESET_OVRD,Override enable for tx_reset" "0,1" newline bitfld.word 0x0 6. "TX_RESET,Override value for tx_reset" "0,1" newline bitfld.word 0x0 5. "TX_NYQUIST_DATA,Override incoming data to nyquist" "0,1" newline bitfld.word 0x0 4. "TX_CLK_OUT_EN_OVRD,Override enable for tx_clk_out_en." "0,1" newline bitfld.word 0x0 3. "TX_CLK_OUT_EN,Override incomming tx_clk_out_en." "0,1" newline bitfld.word 0x0 2. "TX_RATE_OVRD,Override enable for tx_rate." "0,1" newline bitfld.word 0x0 0.--1. "TX_RATE,Override incomming tx lane rate." "0,1,2,3" group.word 0x9008++0x1 line.word 0x0 "LANEX_DIG_TX_OVRD_DRV_LO,Override values for incoming TX drive controls from ASIC" newline rbitfld.word 0x0 15. "RESERVED_15_15,Reserved for Future use" "0,1" newline bitfld.word 0x0 14. "EN,Enable override values for all inputs controlled by this register" "0,1" newline hexmask.word.byte 0x0 7.--13. 1. "PREEMPH,Override value for transmit preemphasis." newline hexmask.word.byte 0x0 0.--6. 1. "AMPLITUDE,Override value for transmit amplitude." group.word 0x900C++0x1 line.word 0x0 "LANEX_DIG_TX_OVRD_DRV_HI,Override values for incoming TX drive controls from ASIC" newline hexmask.word 0x0 6.--15. 1. "RESERVED_15_6,Reserved for Future use" newline bitfld.word 0x0 5. "EN,Enable override values for all inputs controlled by this register" "0,1" newline hexmask.word.byte 0x0 0.--4. 1. "TERM_OFFSET,Override value for tx_term_offset (tx_ana_vcmref_boost)" group.word 0x9010++0x1 line.word 0x0 "LANEX_DIG_TX_OVRD_OUT,Override values for outgoing TX controls to ASIC" newline hexmask.word.byte 0x0 8.--15. 1. "RESERVED_15_8,Reserved for Future use" newline bitfld.word 0x0 7. "TX_STATE_OVRD,Override enable for tx_state" "0,1" newline bitfld.word 0x0 6. "TX_STATE,Override value for tx_state" "0,1" newline bitfld.word 0x0 5. "TX_CM_STATE_OVRD,Override enable for tx_cm_state" "0,1" newline bitfld.word 0x0 4. "TX_CM_STATE,Override value for tx_cm_state" "0,1" newline bitfld.word 0x0 3. "TX_DETECT_RX_ACK_OVRD,Override enable for tx_detect_rx_ack" "0,1" newline bitfld.word 0x0 2. "TX_DETECT_RX_ACK,Override value for tx_detect_rx_ack" "0,1" newline bitfld.word 0x0 1. "DETECT_RX_RES_OVRD,Override enable for tx_detect_rx_res" "0,1" newline bitfld.word 0x0 0. "DETECT_RX_RES,Override value for tx_detect_rx_res" "0,1" group.word 0x9014++0x1 line.word 0x0 "LANEX_DIG_RX_OVRD_IN_LO,Override values for incoming RX controls from ASIC" newline rbitfld.word 0x0 14.--15. "RESERVED_15_14,Reserved for Future use" "0,1,2,3" newline bitfld.word 0x0 13. "RX_LOS_EN_OVRD,Override enable for rx_los_en" "0,1" newline bitfld.word 0x0 12. "RX_LOS_EN,Override value for rx_los_en" "0,1" newline bitfld.word 0x0 11. "RX_TERM_EN_OVRD,Override enable for rx_term_en" "0,1" newline bitfld.word 0x0 10. "RX_TERM_EN,Override value for rx_term_en" "0,1" newline bitfld.word 0x0 9. "RX_BIT_SHIFT_OVRD,Override enable for rx_bit_shift" "0,1" newline bitfld.word 0x0 8. "RX_BIT_SHIFT,Override value for rx_bit_shift" "0,1" newline bitfld.word 0x0 7. "RX_ALIGN_EN_OVRD,Override enable for rx_align_en" "0,1" newline bitfld.word 0x0 6. "RX_ALIGN_EN,Override value for rx_align_en" "0,1" newline bitfld.word 0x0 5. "RX_DATA_EN_OVRD,Override enable for rx_data_en" "0,1" newline bitfld.word 0x0 4. "RX_DATA_EN,Override value for rx_data_en" "0,1" newline bitfld.word 0x0 3. "RX_PLL_EN_OVRD,Override enable for rx_pll_en" "0,1" newline bitfld.word 0x0 2. "RX_PLL_EN,Override value for rx_pll_en" "0,1" newline bitfld.word 0x0 1. "RX_INVERT_OVRD,Override enable for rx_invert" "0,1" newline bitfld.word 0x0 0. "RX_INVERT,Override value for rx_invert" "0,1" group.word 0x9018++0x1 line.word 0x0 "LANEX_DIG_RX_OVRD_IN_HI,Override values for incoming RX controls from ASIC" newline rbitfld.word 0x0 14.--15. "RESERVED_15_14,Reserved for Future use" "0,1,2,3" newline bitfld.word 0x0 13. "RX_RESET_OVRD,Override enable for rx_reset" "0,1" newline bitfld.word 0x0 12. "RX_RESET,Override value for rx_reset" "0,1" newline bitfld.word 0x0 11. "RX_EQ_OVRD,Override enable for rx_eq" "0,1" newline bitfld.word 0x0 8.--10. "RX_EQ,Override value for rx_eq" "0,1,2,3,4,5,6,7" newline bitfld.word 0x0 7. "RX_EQ_EN_OVRD,Override enable for rx_eq_en" "0,1" newline bitfld.word 0x0 6. "RX_EQ_EN,Override value for rx_eq_en" "0,1" newline bitfld.word 0x0 5. "RX_LOS_FILTER_OVRD,Override enable for rx_los_filter" "0,1" newline bitfld.word 0x0 3.--4. "RX_LOS_FILTER,Override value for rx_los_filter" "0,1,2,3" newline bitfld.word 0x0 2. "RX_RATE_OVRD,Override enable for rx_rate" "0,1" newline bitfld.word 0x0 0.--1. "RX_RATE,Override value for rx_rate" "0,1,2,3" group.word 0x901C++0x1 line.word 0x0 "LANEX_DIG_RX_OVRD_OUT,Override values for outgoing RX controls to ASIC" newline hexmask.word 0x0 7.--15. 1. "RESERVED_15_7,Reserved for Future use" newline bitfld.word 0x0 6. "ZERO_DATA,Override data output to all zeros" "0,1" newline bitfld.word 0x0 5. "LOS_OVRD,Override value for rx_los" "0,1" newline bitfld.word 0x0 4. "LOS,Override value for rx_los" "0,1" newline bitfld.word 0x0 3. "PLL_STATE_OVRD,Override enable for rx_pll_state" "0,1" newline bitfld.word 0x0 2. "PLL_STATE,Override value for rx_pll_state" "0,1" newline bitfld.word 0x0 1. "VALID_OVRD,Override enable for rx_valid" "0,1" newline bitfld.word 0x0 0. "VALID,Override value for rx_valid" "0,1" rgroup.word 0x9020++0x1 line.word 0x0 "LANEX_DIG_TX_ASIC_IN,Current values for incoming TX controls from ASIC" newline bitfld.word 0x0 14.--15. "RESERVED_15_14,Reserved for Future use" "0,1,2,3" newline bitfld.word 0x0 13. "LANE_IF_WIDTH,Value from ASIC for lane_if_width (RU - read-only volatile)" "0,1" newline bitfld.word 0x0 12. "DATA_EN_S,Value from ASIC for tx_data_en_s (RU - read-only volatile)" "0,1" newline bitfld.word 0x0 11. "TX_VBOOST_EN,Value from ASIC for tx_vboost_en (RU - read-only volatile)" "0,1" newline bitfld.word 0x0 10. "TX_CLK_OUT_EN,Value from ASIC for tx_clk_out_en (RU - read-only volatile)" "0,1" newline bitfld.word 0x0 9. "DETECT_RX_REQ,Value from ASIC for tx_detect_rx_req (RU - read-only volatile)" "0,1" newline bitfld.word 0x0 8. "BEACON_EN,Value from ASIC for tx_beacon_en (RU - read-only volatile)" "0,1" newline bitfld.word 0x0 7. "CM_EN,Value from ASIC for tx_cm_en (RU - read-only volatile)" "0,1" newline bitfld.word 0x0 6. "TX_EN,Value from ASIC for tx_en (RU - read-only volatile)" "0,1" newline bitfld.word 0x0 5. "DATA_EN,Value from ASIC for tx_data_en (RU - read-only volatile)" "0,1" newline bitfld.word 0x0 4. "TX_RESET,Value from ASIC for tx_reset (RU - read-only volatile)" "0,1" newline bitfld.word 0x0 3. "INVERT,Value from ASIC for tx_invert (RU - read-only volatile)" "0,1" newline bitfld.word 0x0 2. "LOOPBK_EN,Value from ASIC for loopbk_en (RU - read-only volatile)" "0,1" newline bitfld.word 0x0 0.--1. "TX_RATE,Value from ASIC for tx_rate (RU - read-only volatile)" "0,1,2,3" rgroup.word 0x9024++0x1 line.word 0x0 "LANEX_DIG_TX_ASIC_DRV_LO,Current values for incoming TX level controls from ASIC" newline bitfld.word 0x0 14.--15. "RESERVED_15_14,Reserved for Future use" "0,1,2,3" newline hexmask.word.byte 0x0 7.--13. 1. "PREEMPH,Value from ASIC for tx_preemph (RU - read-only volatile)" newline hexmask.word.byte 0x0 0.--6. 1. "AMPLITUDE,Value from ASIC for tx_amplitude (RU - read-only volatile)" rgroup.word 0x9028++0x1 line.word 0x0 "LANEX_DIG_TX_ASIC_DRV_HI,Current values for incoming TX level controls from ASIC" newline hexmask.word 0x0 5.--15. 1. "RESERVED_15_5,Reserved for Future use" newline hexmask.word.byte 0x0 0.--4. 1. "TERM_OFFSET,Value from ASIC for tx_term_offset (RU - read-only volatile)" rgroup.word 0x902C++0x1 line.word 0x0 "LANEX_DIG_TX_ASIC_OUT,Current values for outgoing TX status controls from PHY" newline hexmask.word 0x0 5.--15. 1. "RESERVED_15_5,Reserved for Future use" newline bitfld.word 0x0 4. "STATE,Value from PHY for tx_state (RU - read-only volatile)" "0,1" newline bitfld.word 0x0 3. "CM_STATE,Value from PHY for tx_cm_state (RU - read-only volatile)" "0,1" newline bitfld.word 0x0 2. "DETECT_RX_ACK,Value from PHY for tx_detect_rx_ack (RU - read-only volatile)" "0,1" newline bitfld.word 0x0 1. "RESERVED,Always returns 0 (RU - read-only volatile)" "0,1" newline bitfld.word 0x0 0. "DETECT_RX_RES,Value from PHY for tx_detect_rx_res (RU - read-only volatile)" "0,1" rgroup.word 0x9030++0x1 line.word 0x0 "LANEX_DIG_RX_ASIC_IN,Current values for incoming RX controls from ASIC" newline bitfld.word 0x0 15. "RX_EQ_EN,Value from ASIC for rx_eq_en (RU - read-only volatile)" "0,1" newline bitfld.word 0x0 12.--14. "RX_EQ,Value from ASIC for rx_eq (RU - read-only volatile)" "0,1,2,3,4,5,6,7" newline bitfld.word 0x0 10.--11. "LOS_FILTER,Value from ASIC for rx_los_filter (RU - read-only volatile)" "0,1,2,3" newline bitfld.word 0x0 9. "LOS_EN,Value from ASIC for rx_los_en (RU - read-only volatile)" "0,1" newline bitfld.word 0x0 8. "TERM_EN,Value from ASIC for rx_term_en (RU - read-only volatile)" "0,1" newline bitfld.word 0x0 7. "CLK_SHIFT,Value from ASIC for rx_bit_shift (RU - read-only volatile)" "0,1" newline bitfld.word 0x0 6. "ALIGN_EN,Value from ASIC for rx_align_en (RU - read-only volatile)" "0,1" newline bitfld.word 0x0 5. "DATA_EN,Value from ASIC for rx_data_en (RU - read-only volatile)" "0,1" newline bitfld.word 0x0 4. "PLL_EN,Value from ASIC for rx_pll_en (RU - read-only volatile)" "0,1" newline bitfld.word 0x0 3. "RX_RESET,Value from ASIC for rx_reset (RU - read-only volatile)" "0,1" newline bitfld.word 0x0 2. "INVERT,Value from ASIC for rx_invert (RU - read-only volatile)" "0,1" newline bitfld.word 0x0 0.--1. "RX_RATE,Value from ASIC for rx_rate (RU - read-only volatile)" "0,1,2,3" rgroup.word 0x9034++0x1 line.word 0x0 "LANEX_DIG_RX_ASIC_OUT,Current values for outgoing RX status controls from PHY" newline hexmask.word 0x0 3.--15. 1. "RESERVED_15_3,Reserved for Future use" newline bitfld.word 0x0 2. "LOS,Value from PHY for rx_los (RU - read-only volatile)" "0,1" newline bitfld.word 0x0 1. "PLL_STATE,Value from PHY for rx_pll_state (RU - read-only volatile)" "0,1" newline bitfld.word 0x0 0. "VALID,Value from PHY for rx_valid (RU - read-only volatile)" "0,1" group.word 0x9040++0x1 line.word 0x0 "LANEX_DIG_TX_DEBUG,Transmit debug controls" newline rbitfld.word 0x0 13.--15. "RESERVED_15_13,Reserved for Future use" "0,1,2,3,4,5,6,7" newline bitfld.word 0x0 12. "KEEP_TX_REFGEN,Keep TX voltage regulator ON until TX clocks are OFF" "0,1" newline hexmask.word.byte 0x0 4.--11. 1. "RXDET_MEAS_TIME,Time to wait for rxdet measurement (* 4/2/1 refclk cycles based on multiplier)" newline bitfld.word 0x0 3. "DETECT_RX_ALWAYS,Always signal 1 for rx_detect ignoring analog" "0,1" newline bitfld.word 0x0 0.--2. "DTB_SEL,Selects data to drive on DTB 0 - disabled 1 - mag_update/sub signals 2 - mag_high/add signals 3 - clock aligner early/shift signals 4 - analog/asic clocks 5 - tx_state counter/lbert strobe 6 - noclk_ref_rst/dig_rst 7 -.." "disabled,mag_update/sub signals,mag_high/add signals,clock aligner early/shift signals,analog/asic clocks,tx_state counter/lbert strobe,noclk_ref_rst/dig_rst,tx_ana_rxdetp_high/tx_ana_rxdetm_high" group.word 0x9044++0x1 line.word 0x0 "LANEX_DIG_TX_CM_WAIT_TIME_OVRD,USB3_LANEX_DIG_TX_CM_WAIT_TIME_OVRD" newline hexmask.word.byte 0x0 11.--15. 1. "RESERVED_15_11,Reserved for Future use" newline bitfld.word 0x0 10. "CM_TIME_OVRD_EN,Override enable for common mode charging wait time." "0,1" newline hexmask.word 0x0 0.--9. 1. "CM_TIME_OVRD,Time to wait in ref clock cycles for LFPS common mode charging (This value x32 is used for VCMHOLD charging method)" rgroup.word 0x9048++0x1 line.word 0x0 "LANEX_DIG_TX_VMD_FSM_TX_VCM_0,Calculated values for N_USE and N_TRISTATE. Also TX ANA configuration shift register output." newline bitfld.word 0x0 15. "SHIFT_OUT,Current value from TX_ANAs configuration shift register. (RU - read-only volatile)" "0,1" newline bitfld.word 0x0 14. "DONE,Configuration is done (RU - read-only volatile)" "0,1" newline hexmask.word.byte 0x0 7.--13. 1. "N_USE,Value from VMD for legs to use. (RU - read-only volatile)" newline hexmask.word.byte 0x0 0.--6. 1. "N_TRISTATE,Value from VMD for number of tristate legs. (RU - read-only volatile)" rgroup.word 0x904C++0x1 line.word 0x0 "LANEX_DIG_TX_VMD_FSM_TX_VCM_1,Calculated values for N_FIXED and N_TRAILER." newline bitfld.word 0x0 15. "FIXED_DONE,N_FIXED Multiplication has completed. (RU - read-only volatile)" "0,1" newline bitfld.word 0x0 14. "TRA_DONE,N_TRAILER Multiplication has completed. (RU - read-only volatile)" "0,1" newline hexmask.word.byte 0x0 7.--13. 1. "N_FIXED,Value from VMD for number of fixed driver legs. (RU - read-only volatile)" newline hexmask.word.byte 0x0 0.--6. 1. "N_TRAILER,Value from VMD for number of trailer legs. (RU - read-only volatile)" group.word 0x9050++0x1 line.word 0x0 "LANEX_DIG_TX_VMD_FSM_TX_VCM_DEBUG_IN,Access the TX_ANA VMD Control Shift Register" newline hexmask.word 0x0 4.--15. 1. "RESERVED_15_4,Reserved for Future use" newline bitfld.word 0x0 3. "CONFIG_OVRD,Override the Voltage Mode Driver Configuration FSM and access the shift chain directly. (volatile and 2 reads needed to read value)" "0,1" newline bitfld.word 0x0 2. "CONFIG_LOAD,Override value for the Voltage Mode Driver Configuration FSM's config load. (volatile and 2 reads needed to read value)" "0,1" newline bitfld.word 0x0 1. "CONFIG_CLK,Override value for the Voltage Mode Driver Configuration FSM's config clk. (volatile and 2 reads needed to read value)" "0,1" newline bitfld.word 0x0 0. "CONFIG_DATA,Override value for the Voltage Mode Driver Configuration FSM's config data. (volatile and 2 reads needed to read value)" "0,1" group.word 0x9054++0x1 line.word 0x0 "LANEX_DIG_TX_LBERT_CTL,Pattern Generator controls" newline rbitfld.word 0x0 15. "RESERVED_15_15,Reserved for Future use" "0,1" newline hexmask.word 0x0 5.--14. 1. "PAT0,10 bit pattern for modes using PAT0 (5-7). Ignored for other MODEs." newline bitfld.word 0x0 4. "TRIGGER_ERR,Single shot inversion the LSB of the current symbol. Any write of a 1 to this bit will insert an error. Maintain mode and pattern from setup." "0,1" newline hexmask.word.byte 0x0 0.--3. 1. "MODE,Pattern to generate When changing modes you must change to disabled first 0 - disabled 1 - lfsr31. X^31 + X^28 + 1 2 - lfsr23. X^23 + X^18 + 1 3 - lfsr15. X^15 + X^14 + 1 4 - lfsr7. X^7 + X^6 + 1 5 - fixed word (PAT0) 6 - DC balanced word (PAT0.." group.word 0x9058++0x1 line.word 0x0 "LANEX_DIG_RX_LBERT_CTL,Pattern Matcher controls" newline hexmask.word 0x0 5.--15. 1. "RESERVED_15_5,Reserved for Future use" newline bitfld.word 0x0 4. "SYNC,Synchronize pattern matcher with incoming data A write of a one to this bit will reset the error counter and start a synchronization of the PM. There is no need to write this back to zero to run normally." "0,1" newline hexmask.word.byte 0x0 0.--3. 1. "MODE,Pattern to match When changing modes you must change to disabled first 0 - disabled 1 - lfsr31: X^31 + X^28 + 1 2 - lfsr23: X^23 + X^18 + 1 3 - lfsr15: X^15 + X^14 + 1 4 - lfsr7 : X^7 + X^6 + 1 5 - d[n] = d[n-10] 6 - d[n] = !d[n-10] 7 - d[n] =.." group.word 0x905C++0x1 line.word 0x0 "LANEX_DIG_RX_LBERT_ERR,Pattern match error counter" newline bitfld.word 0x0 15. "OV14,A read of this register or a sync of the Pattern Matcher resets the error count. If all bits of this register are 1 the error counter has saturated. If the status If active multiply COUNT by 128. If OV14=1 and COUNT=2^15-1 signals overflow of.." "0,1" newline hexmask.word 0x0 0.--14. 1. "COUNT,Current error count If OV14 field is active then multiply count by 128 to get the actual count. (volatile and 2 reads needed to read value)" group.word 0x9060++0x1 line.word 0x0 "LANEX_DIG_RX_SCOPE_CTL,Control bits for per-transciever scope portion" newline rbitfld.word 0x0 14.--15. "RESERVED_15_14,Reserved for Future use" "0,1,2,3" newline bitfld.word 0x0 12.--13. "RX_VALID_CTL,When to Start Sampling control based on rx_valid. 0 = Ignore rx_valid. 1 = Heed rx_valid. 2 = Wait for rising_edge on rx_valid." "Ignore rx_valid,Heed rx_valid,Wait for rising_edge on rx_valid,?" newline hexmask.word 0x0 3.--11. 1. "DELAY,number of cycles to skip between samples" newline bitfld.word 0x0 0.--2. "MODE,sampling mode of counters NOTE: WORD is 20 bits. 0 = off 1 = sample data every WORD*(1+DELAY) bits from the digital recovered path. 2 = sample data every WORD*(1+DELAY) + 1 bits from the digital recovered path. 3 = sample data every WORD*(1+DELAY) +.." "off,sample data every WORD*,sample data every WORD*,sample data every WORD*,sample data every WORD*,?,?,?" group.word 0x9064++0x1 line.word 0x0 "LANEX_DIG_RX_SCOPE_PHASE,Scope sampling phase." newline rbitfld.word 0x0 15. "RESERVED_15_15,Reserved for Future use" "0,1" newline hexmask.word.byte 0x0 10.--14. 1. "BASE,which bit to sample when MODE = 1 or 4" newline bitfld.word 0x0 8.--9. "SCOPE_DELAY,How many clocks to delay the analog scope_data." "0,1,2,3" newline bitfld.word 0x0 7. "SCOPE_SEL,Select Sampling Mode. 0 - Before AFE Sampling 1 - After AFE Sampling" "Before AFE Sampling,After AFE Sampling" newline bitfld.word 0x0 6. "UPDATE,Update Sampling phase. Write a 1." "0,1" newline hexmask.word.byte 0x0 0.--5. 1. "SAMPLE_PHASE,Sampling Phase" group.word 0x9068++0x1 line.word 0x0 "LANEX_DIG_RX_DPLL_FREQ,Current frequency integrator value." newline rbitfld.word 0x0 13.--15. "RESERVED_15_13,Reserved for Future use" "0,1,2,3,4,5,6,7" newline hexmask.word 0x0 1.--12. 1. "VAL,Freq is 1.526*VAL ppm from the reference When mpll_slow is set the ppm is half the eqn above (volatile and 2 reads needed to read value)" newline bitfld.word 0x0 0. "DTHR,Bits below the useful resolution (volatile and 2 reads needed to read value)" "0,1" group.word 0x906C++0x1 line.word 0x0 "LANEX_DIG_RX_CDR_CTL,Control bits for receiver in recovered domain" newline hexmask.word.byte 0x0 12.--15. 1. "DTB_SEL,select to drive various signals onto the dtb 0 - disabled 1 - pll_ana_rst pll_count from rx_pwr_ctl 2 - com_good_high/low from aligner 3 - com_bad_high/low from aligner 4 - shift_in_prog ana_odd_data from aligner 5 - low bits of XAUI align FSM.." newline bitfld.word 0x0 11. "ALWAYS_REALIGN,realign on any misaligned comma" "0,1" newline bitfld.word 0x0 10. "FAST_START,decrease startup steps by 50%" "0,1" newline bitfld.word 0x0 8.--9. "FRUG_VALUE,override value for FRUG" "0,1,2,3" newline bitfld.word 0x0 6.--7. "PHUG_VALUE,override value for PHUG" "0,1,2,3" newline bitfld.word 0x0 5. "OVRD_DPLL_GAIN,Override PHUG and FRUG values" "0,1" newline bitfld.word 0x0 4. "PHDET_POL,Reverse polarity of phase error" "0,1" newline bitfld.word 0x0 2.--3. "PHDET_EDGE,Edges to use for phase detection. 11 - Use both edges 10 - Use rising edges only 01 - Use falling edges only 00 - Ignore all edges" "Ignore all edges,Use falling edges only,?,?" newline bitfld.word 0x0 0.--1. "PHDET_EN,Enable phase detecter. top bit is odd slicers bottom is even" "0,1,2,3" rgroup.word 0x9070++0x1 line.word 0x0 "LANEX_DIG_RX_CDR_CDR_FSM_DEBUG,Current values for CDR and Adaptation FSM." newline bitfld.word 0x0 13.--15. "ADAP_RX_EQ,Equalization setting from adaptation FSM. (RU - read-only volatile)" "0,1,2,3,4,5,6,7" newline bitfld.word 0x0 10.--12. "RX_EQ_CTR,Initial centre point from equalization FSM. (RU - read-only volatile)" "0,1,2,3,4,5,6,7" newline bitfld.word 0x0 7.--9. "RX_ANA_EQ,Equalization setting to Analog. (RU - read-only volatile)" "0,1,2,3,4,5,6,7" newline bitfld.word 0x0 6. "ADAP_RX_VALID,Adaptation has completed and locked. (RU - read-only volatile)" "0,1" newline bitfld.word 0x0 5. "CDR_EN_ADAP,Adapatation loop is enabling the CDR. (RU - read-only volatile)" "0,1" newline bitfld.word 0x0 4. "CDR_EN_EQ,Equalization loop is enabling the CDR. (RU - read-only volatile)" "0,1" newline bitfld.word 0x0 3. "ALIGNED,Datapath is bit-aligned. (RU - read-only volatile)" "0,1" newline bitfld.word 0x0 2. "CDR_RX_VALID,CDR has locked to incoming data stream. (RU - read-only volatile)" "0,1" newline bitfld.word 0x0 1. "CDR_TIMEOUT,CDR has not locked to datastream and has timed-out. (RU - read-only volatile)" "0,1" newline bitfld.word 0x0 0. "CDR_EN,CDR has been enabled. (RU - read-only volatile)" "0,1" group.word 0x9074++0x1 line.word 0x0 "LANEX_DIG_RX_CDR_LOCK_VEC_OVRD,Control bits for receiver in recovered domain" newline hexmask.word.byte 0x0 11.--15. 1. "ADAP_CTR_LEVEL,Ammount of earlies that increment the adaptation counter (times 32 Default is 512). (volatile and 2 reads needed to read value)" newline bitfld.word 0x0 10. "ADAP_POLARITY,If asserted invert default adaptation adjustment for equalization. IF early decrease equalization. Normal mode is to decrease. (volatile and 2 reads needed to read value)" "0,1" newline bitfld.word 0x0 9. "LOCK_VECTOR_OVRD,Override enable for the rx_eq outputs. (volatile and 2 reads needed to read value)" "0,1" newline bitfld.word 0x0 8. "LOCK_VECTOR_EN,Override value for the locked_vector output completion. (volatile and 2 reads needed to read value)" "0,1" newline hexmask.word.byte 0x0 0.--7. 1. "LOCK_VECTOR,Override value for the locked_vector. (volatile and 2 reads needed to read value)" rgroup.word 0x9078++0x1 line.word 0x0 "LANEX_DIG_RX_CDR_LOCK_VEC,Current values for the locked vector.." newline hexmask.word.byte 0x0 12.--15. 1. "RESERVED_15_12,Reserved for Future use" newline bitfld.word 0x0 9.--11. "EQ_RX_EQ,Equalization setting from the Equalization Loop. (RU - read-only volatile)" "0,1,2,3,4,5,6,7" newline bitfld.word 0x0 8. "EQ_LOCKED_VECTOR_EN,Equalization locked vector has been filled. (RU - read-only volatile)" "0,1" newline hexmask.word.byte 0x0 0.--7. 1. "EQ_LOCKED_VECTOR,Results of equalization loop. (RU - read-only volatile)" rgroup.word 0x907C++0x1 line.word 0x0 "LANEX_DIG_RX_CDR_ADAP_FSM,Observation of adaptation FSM register." newline hexmask.word.byte 0x0 11.--15. 1. "MSTR_CTR,Master count register. (RU - read-only volatile)" newline hexmask.word.byte 0x0 7.--10. 1. "LOOP_CTR,Loop count register. (RU - read-only volatile)" newline hexmask.word.byte 0x0 3.--6. 1. "ADAP_CTR,Adaptation count register. (RU - read-only volatile)" newline bitfld.word 0x0 0.--2. "ADAP_STATE,Adaptation State. NOTE: ADAP_RESET = 3'b000 ADAP_LOCK = 3'b001 ADAP_SUFF = 3'b010 ADAP_LOOP = 3'b011 ADAP_MSTR = 3'b100 ADAP_DONE = 3'b101 (RU - read-only volatile)" "0,1,2,3,4,5,6,7" group.word 0x9080++0x1 line.word 0x0 "LANEX_ANA_RX_ATB0,ATB Control Register" newline hexmask.word.byte 0x0 8.--15. 1. "RESERVED_15_8,Reserved for Future use" newline bitfld.word 0x0 7. "EN_ATB,Enable ATB sensing and forcing on internal RX nodes" "0,1" newline bitfld.word 0x0 6. "EN_MARG,Enable margining mode in receiver; it puts EQ common mode output on atb_f_m" "0,1" newline bitfld.word 0x0 5. "EN_ATB_RM_F,Enable atb_f_p on negative-side termination resistor" "0,1" newline bitfld.word 0x0 4. "EN_ATB_RM_S,Enable atb_s_m on negative-side termination resistor" "0,1" newline bitfld.word 0x0 3. "EN_ATB_RP_F,Enable atb_f_p on positive-side termination resistor" "0,1" newline bitfld.word 0x0 2. "EN_ATB_RP_S,Enable atb_s_p on positive-side termination resistor" "0,1" newline bitfld.word 0x0 1. "EN_ATB_VOS,Put rxafe filtered outputs vo_p on atb_s_p and vo_m on atb_s_m" "0,1" newline bitfld.word 0x0 0. "EN_ATB_VOFF,Put rxafe voff_p on atb_s_p and voff_m on atb_s_m" "0,1" group.word 0x9084++0x1 line.word 0x0 "LANEX_ANA_RX_ATB1,ATB and Misc Control Register" newline hexmask.word.byte 0x0 8.--15. 1. "RESERVED_15_8,Reserved for Future use" newline bitfld.word 0x0 6.--7. "RX_DCC_IQ_OFFSET_H_4_3,Code which helps to manually tune reference voltage (r-string dac) for IQ opamp and correct input offset (rx_dcc_iq_offset_h_4_3 bit)" "0,1,2,3" newline bitfld.word 0x0 5. "EN_ATB_VLOS,Enable sensing of LOS reference voltage on atb_s_p" "0,1" newline bitfld.word 0x0 4. "EN_ATB_VRF,Enable sensing of vref_rx (RX Bias B.G. Voltage) on atb_s_p" "0,1" newline bitfld.word 0x0 3. "MEAS_GD,Enable sensing of local gd in RX; ties gd to atb_s_m" "0,1" newline bitfld.word 0x0 2. "MEAS_VP,Enable sensing of local vp in RX; ties vp to atb_s_p" "0,1" newline bitfld.word 0x0 0.--1. "RX_DCC_IQ_OFFSET_H_2_1,Code which helps to manually tune reference voltage (r-string dac) for IQ opamp and correct input offset (rx_dcc_iq_offset_h_2_1 bit)" "0,1,2,3" group.word 0x9088++0x1 line.word 0x0 "LANEX_ANA_RX_ENPWR0,RX State Control Register" newline hexmask.word.byte 0x0 8.--15. 1. "RESERVED_15_8,Reserved for Future use" newline bitfld.word 0x0 7. "CTL_RXPWRON,MUX select for AFE en to select between CTL_RXPWRON=0 rx_afe_en (External signal) or CTL_RXPWRON=1 LCL_RXPWRON" "0,1" newline bitfld.word 0x0 6. "LCL_RXPWRON,Enable/Disable RX AFE .This bit is only selected when CTL_RXPWRON = 1" "0,1" newline bitfld.word 0x0 5. "CTL_EN_LOS,MUX select for LOS en to select between CTL_EN_LOS=0 rx_los_en (External signal) or CTL_EN_LOS=1 LCL_EN_LOS" "0,1" newline bitfld.word 0x0 4. "LCL_EN_LOS,Enable/Disable LOS.This bit is only selected when CTL_EN_LOS = 1" "0,1" newline bitfld.word 0x0 3. "CTL_RXCK,MUX select for RX Clock en to select between CTL_RXCK=0 rx_clock_en (External signal) or CTL_RXCK=1 LCL_RXCK." "0,1" newline bitfld.word 0x0 2. "LCL_RXCK,Enable/Disable en_rx_clock (RX clock enable).This bit is only selected when CTL_RXCK = 1" "0,1" newline bitfld.word 0x0 1. "CTL_ACJT,MUX select for ACJTAG to select between CTL_ACJTG=0 rx_acjtg_en (External signal) or CTL_ACJTG=1 LCL_ACJT." "0,1" newline bitfld.word 0x0 0. "LCL_ACJT,Enable/Disable acjtag block This bit is only selected when CTL_ACJTG = 1" "0,1" group.word 0x908C++0x1 line.word 0x0 "LANEX_ANA_RX_PMIX_PHASE,Phase select Value" newline hexmask.word.byte 0x0 8.--15. 1. "RESERVED_15_8,Reserved for Future use" newline hexmask.word.byte 0x0 0.--7. 1. "PHASE,Write to bits 8 to 1 of the phase select register in the phase mixer through the CDR (USER2 volatile - read-write volatile and custom)" group.word 0x9090++0x1 line.word 0x0 "LANEX_ANA_RX_ENPWR1,Additional RX State Control Register" newline hexmask.word.byte 0x0 8.--15. 1. "RESERVED_15_8,Reserved for Future use" newline bitfld.word 0x0 7. "CTL_PHASE_REG_RST,MUX select for Phase Register Reset to select between CTL_PHASE_REG_RST=0 rx_phase_reg_rst (External signal) or CTL_PHASE_REG_RST=1 LCL_PHASE_REG_RST" "0,1" newline bitfld.word 0x0 6. "LCL_PHASE_REG_RST,Reset phase register.This bit is only selected when CTL_PHASE_REG_RST= 1" "0,1" newline bitfld.word 0x0 5. "CTL_BST,MUX select for AFE Boost to select between CTL_BST=0 rx_aeq[2:0] (External signal) or CTL_BST=1 LCL_BST" "0,1" newline bitfld.word 0x0 2.--4. "LCL_BST,RX Boost (equalization) Value" "0,1,2,3,4,5,6,7" newline bitfld.word 0x0 1. "CTL_RXTERM,MUX select for RX Term enable to select between CTL_RXTERM=0 rx_term_en (External signal) or CTL_RXTERM=1 LCL_RXTERM" "0,1" newline bitfld.word 0x0 0. "LCL_RXTERM,Enable/disable RX termination when CTL_RXTERM = 1" "0,1" group.word 0x9094++0x1 line.word 0x0 "LANEX_ANA_RX_ENPWR2,Yet another RX State Control Register" newline hexmask.word.byte 0x0 8.--15. 1. "RESERVED_15_8,Reserved for Future use" newline bitfld.word 0x0 7. "EN_RXPMIX_TST,Enable XOR gate to test linearity of RX phase mixer using atb_s_p and atb_s_m" "0,1" newline bitfld.word 0x0 6. "EN_RXPMIX_VPMIX,Put vreg_pmix on atb_s_p" "0,1" newline bitfld.word 0x0 5. "EN_RXPMIX_VRX,Put vreg_rx on atb_s_p" "0,1" newline bitfld.word 0x0 4. "RX_DCC_IQ_OFFSET_H_0,Code which helps to manually tune reference voltage (r-string dac) for IQ opamp and correct input offset (rx_dcc_iq_offset_h_0 bit)" "0,1" newline bitfld.word 0x0 3. "EN_RXPMIX_FRC_VPMIX_H,Connecting vbg_in to vbg (in case of 0) or to atb_s_m_int (in case of 1)" "0,1" newline bitfld.word 0x0 2. "RX_SCOPE_ATB_2,Put XOR of RX SCOPE PMIX input and output on atb_s_p" "0,1" newline bitfld.word 0x0 1. "RX_SCOPE_ATB_1,Put RX SCOPE regulated VP on atb_s_p" "0,1" newline bitfld.word 0x0 0. "RX_SCOPE_ATB_0,Have RX SCOPE reference for regulator use atb_f_p as a reference instead of VP/VBG" "0,1" group.word 0x9098++0x1 line.word 0x0 "LANEX_ANA_RX_SCOPE_VDCC,RX Scope controls and clock DCC control voltage probe" newline hexmask.word.byte 0x0 8.--15. 1. "RESERVED_15_8,Reserved for Future use" newline bitfld.word 0x0 6.--7. "VDCC,Probe DCC control voltage" "0,1,2,3" newline bitfld.word 0x0 5. "NC5,Reserved" "0,1" newline bitfld.word 0x0 4. "RX_SCOPE_SLEW,Set high for low RX clock frqeuencies (625MHz) for RX Scope to work correctly" "0,1" newline bitfld.word 0x0 3. "RX_SCOPE_FDIV20,Divide scope output clock by 20 instead of 10" "0,1" newline bitfld.word 0x0 2. "RX_LOS_LFPS_EN_BIT_2,In case of rx_los_lfps_en_cntrl = 1/0 reg_rx_los_lfps_en/rx_ana_los_lfps_en signal directly applied to rx_los circuit through I101 multiplexer." "0,1" newline bitfld.word 0x0 1. "RX_DCC_IQ_OFFSET_EN_H,Select ref voltage for IQ opamp from testmode part (in case of 1) or from ordinary resistive dividers (in case of 0)." "0,1" newline bitfld.word 0x0 0. "RX_LOS_LFPS_EN,Enables the RX LOS LFPS mode use when you want to detect incoming LFPS signals USB3.0" "0,1" group.word 0x90AC++0x1 line.word 0x0 "LANEX_ANA_TX_TXDRV_CNTRL,Register 3" newline hexmask.word.byte 0x0 8.--15. 1. "RESERVED_15_8,Reserved for Future use" newline bitfld.word 0x0 7. "PULL_DN_REG,register bit that causes the calibrated TX bits to pull down in a common mode fashion. If pull_dn_reg and tx_pull_up are both high then pull_dn_reg wins" "0,1" newline bitfld.word 0x0 6. "PULL_UP_REG,Register override for tx_pull_up. Used when ovrd_pull_up is HIGH causes calibrated TX bits to pull up in a common mode fashion unless pull_dn_reg is HIGH" "0,1" newline bitfld.word 0x0 5. "OVRD_PULL_UP,Selects local value of pull_up_reg instead of tx_pull_up" "0,1" newline bitfld.word 0x0 4. "VCM_HOLD_REG,Register override for tx_vcm_hold. Used when ovrd_vcm_hold is HIGH controls the TX common mode hold circuitry" "0,1" newline bitfld.word 0x0 3. "OVRD_VCM_HOLD,Selects local value of vcm_hold_reg instead of tx_vcm_hold to control state of TX common mode hold circuitry" "0,1" newline bitfld.word 0x0 2. "REFGEN_PWRDN_OVRD_N,Set LOW for TX regulator not to turn on when RX clock is enabled. Default is for TX regulator to turn on when RX or TX clock is enabled" "0,1" newline bitfld.word 0x0 1. "NOCONN_1,Reserved" "0,1" newline bitfld.word 0x0 0. "NOCONN_0,Reserved" "0,1" group.word 0x90B0++0x1 line.word 0x0 "LANEX_ANA_TX_POWER_CTL,Register 4" newline hexmask.word.byte 0x0 8.--15. 1. "RESERVED_15_8,Reserved for Future use" newline bitfld.word 0x0 7. "OVRD_EN,Enables local overrides for all signals in this register except for TX_DIV_CLK_EN which doesn't need this signal" "0,1" newline bitfld.word 0x0 6. "SERIAL_EN_REG,Forces state of tx_serial_en when OVRD_EN is 1" "0,1" newline bitfld.word 0x0 5. "CLK_EN_REG,Forces state of tx_clk_en when OVRD_EN is 1" "0,1" newline bitfld.word 0x0 4. "DATA_EN_REG,Forces state of tx_data_en when OVRD_EN is HIGH" "0,1" newline bitfld.word 0x0 3. "REFGEN_EN_REG,Register override value for tx_refgen_en. Controls the TX regulator biasing circuitry and the rxdetect comparators when OVRD_EN is HIGH. This function may be overridden by the state of refgen_pwdn_reg" "0,1" newline bitfld.word 0x0 2. "TX_DIV_CLK_EN,Enables the div clock that goes from the TX to the undersampler more appropriately called tx_sampler_clk_en this clock comes after the optional divide by 2 or 4 tx_clk_en must be HIGH to get a clock out" "0,1" newline bitfld.word 0x0 1. "REFGEN_PDN_REG,Register override for refgen pwdn. Used when OVRD_EN is HIGH. Controls the TX regulator biasing circuitry and the rxdetect comparators when OVRD_EN is HIGH" "0,1" newline bitfld.word 0x0 0. "LFPS_HIGH_PRIORITY,When this is set high LFPS priority becomes higher than tx_data" "0,1" group.word 0x90B4++0x1 line.word 0x0 "LANEX_ANA_TX_ALT_BLOCK,Register 5" newline hexmask.word.byte 0x0 8.--15. 1. "RESERVED_15_8,Reserved for Future use" newline bitfld.word 0x0 7. "EN_ALT_BUS,Enables the TX for alt bus mode powers up the TX regulator biasing circuitry and the rxdetect comparators. Needed if manually running the alt bus features" "0,1" newline bitfld.word 0x0 5.--6. "DRV_SOURCE_REG,Forces state of tx_data_source when OVRD_ALT_BUS is HIGH. 00 = serializer data or alt oscillator vp/vph/vphreg/vptx if selected 01 = jtag data differential 10 = LFPS oscillator differential 11 = jtag data common mode drive for test" "serializer data or alt oscillator..,jtag data differential,?,?" newline bitfld.word 0x0 4. "JTAG_DATA_REG,Forces state of jtag_data when OVRD_ALT_BUS is HIGH" "0,1" newline bitfld.word 0x0 1.--3. "TX_RINGO_CNTRL,Enables and connects the various test oscillators to the transmit pins must set drv_source_reg bus correctly. 0XX = All oscillators are disabled 100 = HV oscillator enabled 101 = SVT oscillator enabled 110 = LVT oscillator enabled 111.." "0,1,2,3,4,5,6,7" newline bitfld.word 0x0 0. "OVRD_ALT_BUS,Enables local overrides for alt-bus control signals: DRV_SOURCE_REG and JTAG_DATA_REG" "0,1" group.word 0x90B8++0x1 line.word 0x0 "LANEX_ANA_TX_ALT_AND_LOOPBACK,Register 6" newline hexmask.word.byte 0x0 8.--15. 1. "RESERVED_15_8,Reserved for Future use" newline bitfld.word 0x0 7. "OVRD_TX_LB,Enables the override of the tx_lb_en" "0,1" newline bitfld.word 0x0 6. "TX_LB_EN_REG,Forces state of tx_lb_en when OVRD_TX_LB is enabled" "0,1" newline bitfld.word 0x0 5. "ATB_VPTX,Connects vptx to atb_s_p and gd to atb_s_m" "0,1" newline bitfld.word 0x0 4. "ATB_VREG_TX,Connects TX regulator input reference to atb_s_p and gd to atb_s_m" "0,1" newline bitfld.word 0x0 3. "ATB_VDCCP,Connects vdcc_p to atb_s_p" "0,1" newline bitfld.word 0x0 2. "ATB_VDCCM,Connects vdcc_m to atb_s_m" "0,1" newline bitfld.word 0x0 1. "NOCONN_01,Reserved" "0,1" newline bitfld.word 0x0 0. "SELECT_PMIX_CLK,select pmix_clk for TX clock for ATE test mode" "0,1" group.word 0x90BC++0x1 line.word 0x0 "LANEX_ANA_TX_TX_ATB_REG,Register 7" newline hexmask.word.byte 0x0 8.--15. 1. "RESERVED_15_8,Reserved for Future use" newline bitfld.word 0x0 7. "ATB_PBIAS,Connect real pmos_bias voltage for TX PMOS driver pull up path to atb_s_p and local ground at the pmos_bias block to atb_s_m" "0,1" newline bitfld.word 0x0 6. "ATB_VCM_REP,Connect common mode replica voltage in pmos_bias block to atb_s_p and local ground to atb_s_m" "0,1" newline bitfld.word 0x0 5. "ATB_RXDETREF,Connect RX detect block reference voltage to atb_s_p and local ground to atb_s_m" "0,1" newline bitfld.word 0x0 4. "ATB_TXFP,Connect tx_p to atb_f_p" "0,1" newline bitfld.word 0x0 3. "ATB_TXFM,Connect tx_m to atb_f_m" "0,1" newline bitfld.word 0x0 2. "ATB_TXSP,Connect tx_p to atb_s_p" "0,1" newline bitfld.word 0x0 1. "ATB_TXSM,Connect tx_m to atb_s_m" "0,1" newline bitfld.word 0x0 0. "ATB_VCM,Connect tx_p/tx_m common mode voltage onto atb_s_p and local ground onto atb_s_m" "0,1" group.word 0x90C0++0x1 line.word 0x0 "LANEX_ANA_TX_TX_BOOST,Register 8" newline hexmask.word.byte 0x0 8.--15. 1. "RESERVED_15_8,Reserved for Future use" newline bitfld.word 0x0 7. "OVRD_VBOOST_EN,Enables the overrides on VBOOST_EN_REG" "0,1" newline bitfld.word 0x0 6. "VBOOST_EN_REG,Forces state of tx_vboost_en when OVRD_VBOOST_EN is HIGH" "0,1" newline bitfld.word 0x0 5. "VCON_EN_N,Forces state of vcon_en_n" "0,1" newline bitfld.word 0x0 4. "ATB_VBOOST,Connects vboost to atb_s_p and local ground to Atb_s_m" "0,1" newline bitfld.word 0x0 3. "ATB_VCMBOOST,Connects vcmboost to atb_s_p and local ground to atb_s_m." "0,1" newline bitfld.word 0x0 2. "ATB_F_VBOOST_REF,Enables forcing of tx_vboost_vref through atb_f_p from external" "0,1" newline bitfld.word 0x0 1. "OVRD_VREG_DECAP,Enables override of vreg_decap_en_n signal" "0,1" newline bitfld.word 0x0 0. "VREG_DECAP_EN_N_REG,Forces state of vreg_decap_en_n control signal. Controls whether extra decoupling is switched in for TX regulator output." "0,1" group.word 0x9100++0x1 line.word 0x0 "LANEX_DIG_RX_CDR_FSM_INIT_CTL,Control bits for CDR init phase portion" newline hexmask.word.byte 0x0 9.--15. 1. "RESERVED_15_9,Reserved for Future use" newline bitfld.word 0x0 8. "INIT_CNT_OVRD,Active high override enable bit to select the override INIT_CNT register 0 = Disabled 1 = Enabled" "Disabled,Enabled" newline hexmask.word.byte 0x0 0.--7. 1. "INIT_CNT,Override value for CDR Init Phase" group.word 0x9104++0x1 line.word 0x0 "LANEX_DIG_RX_CDR_FSM_TRACK_CTL,Control bits for CDR track phase portion" newline hexmask.word.byte 0x0 9.--15. 1. "RESERVED_15_9,Reserved for Future use" newline bitfld.word 0x0 8. "TRACK_CNT_OVRD,Active high override enable bit to select the override TRACK_CNT register 0 = Disabled 1 = Enabled" "Disabled,Enabled" newline hexmask.word.byte 0x0 0.--7. 1. "TRACK_CNT,Override value for CDR Track Phase" group.word 0x9108++0x1 line.word 0x0 "LANEX_DIG_RX_CDR_FSM_LOCK_CTL,Control bits for CDR lock phase portion" newline hexmask.word.byte 0x0 9.--15. 1. "RESERVED_15_9,Reserved for Future use" newline bitfld.word 0x0 8. "LOCK_CNT_OVRD,Active high override enable bit to select the override LOCK_CNT register 0 = Disabled 1 = Enabled" "Disabled,Enabled" newline hexmask.word.byte 0x0 0.--7. 1. "LOCK_CNT,Override value for CDR Lock Phase" repeat 9. (list 0x0 0x1 0x2 0x3 0x4 0x8 0x9 0xB 0xC )(list 0x0 0x4 0x8 0xC 0x10 0x20 0x24 0x2C 0x30 ) rgroup.word ($2+0xA000)++0x1 line.word 0x0 "PORTX_STAT_RO_$1,Status Register 0" newline hexmask.word 0x0 4.--15. 1. "RESERVED_15_4,Reserved for Future use" newline bitfld.word 0x0 3. "PLL_LOCK,analog PLL Lock Signal" "0,1" newline bitfld.word 0x0 2. "RX_SQUELCH,analog RX Squelch Signal" "0,1" newline bitfld.word 0x0 1. "RESERVED_1,Reserved" "0,1" newline bitfld.word 0x0 0. "RESERVED_0,Reserved" "0,1" repeat.end repeat 7. (list 0x5 0x6 0x7 0xA 0xD 0xE 0xF )(list 0x0 0x4 0x8 0x14 0x20 0x24 0x28 ) rgroup.word ($2+0xA014)++0x1 line.word 0x0 "PORTX_STAT_RO_$1,Status Register 5" newline hexmask.word 0x0 4.--15. 1. "RESERVED_15_4,Reserved for Future use" newline hexmask.word.byte 0x0 0.--3. 1. "DATAOUT,UTMI+ Output DATAOUT" repeat.end repeat 2. (list 0x0 0x6 )(list 0x0 0x18 ) group.word ($2+0xA040)++0x1 line.word 0x0 "PORTX_OVRD_RW_$1,Override Register 0" newline hexmask.word.byte 0x0 8.--15. 1. "RESERVED_15_8,Reserved for Future use" newline hexmask.word.byte 0x0 4.--7. 1. "OVERRD_ADDR_OVRD_EN,Override Enable for overrd_addr [7:4]" newline hexmask.word.byte 0x0 0.--3. 1. "OVERRD_ADDR,Analog Test Control Override Address [3:0]" repeat.end repeat 10. (list 0x1 0x2 0x3 0x4 0x8 0x9 0xA 0xB 0xE 0xF )(list 0x0 0x4 0x8 0xC 0x1C 0x20 0x24 0x28 0x34 0x38 ) group.word ($2+0xA044)++0x1 line.word 0x0 "PORTX_OVRD_RW_$1,Override Register 1" newline hexmask.word.byte 0x0 8.--15. 1. "RESERVED_15_8,Reserved for Future use" newline bitfld.word 0x0 7. "VBUS_VALID_PU_OVRD_EN,Override Enable for vbus_valid_pu" "0,1" newline bitfld.word 0x0 6. "OTG_PU_OVRD_EN,Override Enable for otg_pu" "0,1" newline bitfld.word 0x0 5. "TX_VREF_VREG_PU_OVRD_EN,Override Enable for tx_vref_vreg_pu" "0,1" newline bitfld.word 0x0 4. "SQRX_PU_OVRD_EN,Override Enable for sqrx_pu" "0,1" newline bitfld.word 0x0 3. "VBUS_VALID_PU,DRVVBUS Input" "0,1" newline bitfld.word 0x0 2. "OTG_PU,OTGDISABLE Input" "0,1" newline bitfld.word 0x0 1. "TX_VREF_VREG_PU,TX hs_driver Comparator Power Up" "0,1" newline bitfld.word 0x0 0. "SQRX_PU,RX squelch Comparator Power Up" "0,1" repeat.end group.word 0xA054++0x1 line.word 0x0 "PORTX_OVRD_RW_5,Override Register 5" newline hexmask.word.byte 0x0 8.--15. 1. "RESERVED_15_8,Reserved for Future use" newline bitfld.word 0x0 6.--7. "XO_CLK_DIV_OVRD_EN,Override Enable for xo_clk_div" "0,1,2,3" newline bitfld.word 0x0 5. "MSTR_OVERRD_BIT_OVRD_EN,Override Enable for mstr_overrd_bit" "0,1" newline bitfld.word 0x0 4. "OVERRD_ADDR_4_OVRD_EN,Override Enable for overrd_addr_4" "0,1" newline bitfld.word 0x0 2.--3. "XO_CLK_DIV,setting reference clock division" "0,1,2,3" newline bitfld.word 0x0 1. "MSTR_OVERRD_BIT,Analog Test Control Master Override" "0,1" newline bitfld.word 0x0 0. "OVERRD_ADDR_4,Analog Test Control Override Address [4]" "0,1" group.word 0xA05C++0x1 line.word 0x0 "PORTX_OVRD_RW_7,Override Register 7" newline hexmask.word.byte 0x0 8.--15. 1. "RESERVED_15_8,Reserved for Future use" newline bitfld.word 0x0 7. "TX_LS_EN_OVRD_EN,Override Enable for tx_ls_en" "0,1" newline bitfld.word 0x0 4.--6. "PWR_SEQ_CLK_DIV_OVRD_EN,Override Enable for pwr_seq_clk_div" "0,1,2,3,4,5,6,7" newline bitfld.word 0x0 3. "TX_LS_EN,TX LS Enable" "0,1" newline bitfld.word 0x0 0.--2. "PWR_SEQ_CLK_DIV,setting power_sequence division" "0,1,2,3,4,5,6,7" group.word 0xA070++0x1 line.word 0x0 "PORTX_OVRD_RW_12,Override Register 12" newline hexmask.word.byte 0x0 8.--15. 1. "RESERVED_15_8,Reserved for Future use" newline bitfld.word 0x0 7. "RES_ACK_OUT_OVRD_EN,Override Enable for res_ack_out" "0,1" newline bitfld.word 0x0 5.--6. "PLL_CLK_DIV_OVRD_EN,Override Enable for pll_clk_div" "0,1,2,3" newline bitfld.word 0x0 4. "PLL_RESET_OVRD_EN,Override Enable for pll_reset" "0,1" newline bitfld.word 0x0 3. "RES_ACK_OUT,Ack resistor tune external requirement" "0,1" newline bitfld.word 0x0 1.--2. "PLL_CLK_DIV,setting MPLL division" "0,1,2,3" newline bitfld.word 0x0 0. "PLL_RESET,MPLL gear_shift" "0,1" group.word 0xA074++0x1 line.word 0x0 "PORTX_OVRD_RW_13,Override Register 13" newline hexmask.word.byte 0x0 8.--15. 1. "RESERVED_15_8,Reserved for Future use" newline bitfld.word 0x0 7. "BIST_MODE_OVRD_EN,Override Enable for bist_mode" "0,1" newline bitfld.word 0x0 6. "TEST_PKT_RPT_OVRD_EN,Override Enable for test_pkt_rpt" "0,1" newline bitfld.word 0x0 4.--5. "XO_CLK_SEL_OVRD_EN,Override Enable for xo_clk_sel" "0,1,2,3" newline bitfld.word 0x0 3. "BIST_MODE,BIST Mode" "0,1" newline bitfld.word 0x0 2. "TEST_PKT_RPT,BIST Test Packet Mode" "0,1" newline bitfld.word 0x0 0.--1. "XO_CLK_SEL,Reference Clock Selection" "0,1,2,3" tree.end tree "USB_PHY1_NCR" base ad:0xF1250000 group.long 0x0++0x13 line.long 0x0 "CTRL_0,CTRL_0" bitfld.long 0x0 31. "TEST_BURNIN,All Circuits Activator" "0,1" bitfld.long 0x0 28.--30. "TX_VBOOST_LVL,TX Voltage Boost Level Sets the boosted transmit launch amplitude (mVppd)." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 25.--27. "SSC_RANGE,Spread Spectrum Clock Range Selects the range of spread spectrum modulation when ssc_en is asserted and the PHY is spreading the high-speed transmit clocks. Applies a fixed offset to the phase accumulator." "0,1,2,3,4,5,6,7" bitfld.long 0x0 24. "SSC_EN,Spread Spectrum Enable Enables spread spectrum clock production (0.5% down-spread at ~ 31.5 KHz) in the USB 3.0 femtoPHY. Set this signal to 1'b1." "0,1" newline bitfld.long 0x0 23. "RTUNE_REQ,Resistor Tune Request Assertion triggers a resistor tune request (if one is not already in progress). When this signal is asserted rtune_ack goes high until calibration of the termination impedances is complete. Note that termination.." "0,1" bitfld.long 0x0 22. "REF_USE_XO,Use External Crystal Oscillator" "0,1" newline bitfld.long 0x0 21. "REF_XO_EN,Crystal Oscillator Always On Enable" "0,1" bitfld.long 0x0 20. "REF_REPEAT_CLK_EN,Clock Repeater Buffer Enable" "0,1" newline bitfld.long 0x0 19. "REF_CLKDIV2,Input Reference Clock Divider Control If the input reference clock frequency is greater than 100 MHz this signal must be asserted. The reference clock frequency is then divided by 2 to keep it in the range required by the MPLL. When this.." "0,1" bitfld.long 0x0 18. "REF_USE_PAD,Select Reference Clock Connected to ref_pad_clk_\{p m\} When asserted selects the external ref_pad_clk_\{p m\} inputs as the reference clock source. When ref_use_pad is de-asserted ref_alt_clk_\{p m\} are selected for an on-chip reference.." "0,1" newline bitfld.long 0x0 17. "REF_SSP_EN,Reference Clock Enable for SS function. Enables the reference clock to the prescaler. The ref_ssp_en signal must remain de-asserted until the reference clock is running at the appropriate frequency at which point ref_ssp_en can be asserted." "0,1" hexmask.long.word 0x0 8.--16. 1. "SSC_REF_CLK_SEL,Spread Spectrum Reference Clock Shifting Enables non-standard oscillator frequencies to generate targeted MPLL output rates. Input corresponds to frequency-synthesis coefficient. ssc_ref_clk_sel[8:6] = modulous -1.." newline bitfld.long 0x0 7. "ALT_CLK_EN,Alternate Clock Enable Enables the ref_pcs_clk and ref_pipe_pclk output clocks (if necessary powers up the MPLL)." "0,1" newline bitfld.long 0x0 2. "PIPE_RESET_N,PIPE_RESET_N" "0,1" bitfld.long 0x0 1. "PORTRESET,When asserted this customer-specific signal resets the corresponding port's USB2.0 transmit and receive logic without disabling the clocks within the USB 3.0 femtoPHY. 1: The transmit and receive finite state machines (FSMs) are reset and.." "The transmit and receive FSMs are operational,The transmit and receive finite state machines" newline bitfld.long 0x0 0. "PHY_RESET,Core and State Machine Reset Resets the core and all state machines including the JTAG interface with the exception of the reference clock buffer. Asserting phy_reset triggers the assertion of the tx<#>_reset and rx<#>_reset signals." "0,1" line.long 0x4 "CTRL_1,CTRL_1" bitfld.long 0x4 29.--31. "COMPDISTUNE0,Disconnect Threshold Adjustment Adjusts the voltage level for the threshold used to detect a disconnect event at the host. To enable tuning at the board level connect this bus to a register. 111: + 4.5% 110: + 3% 101: + 1.5%.." "0,1,2,3,4,5,6,7" bitfld.long 0x4 26.--28. "LOS_BIAS,Loss-of-Signal Detector Threshold Level Control Sets the LOS detection threshold level. To enable tuning at the board level connect this bus to a register. 111: 135 mV 110: 120 mV 101: 105 mV 100: 90 mV 011: 75 mV 010:.." "Invalid,?,?,?,?,?,?,?" newline hexmask.long.byte 0x4 21.--25. 1. "LOS_LEVEL,Loss-of-Signal Detector Sensitivity Level Control" bitfld.long 0x4 20. "TEST_POWERDOWN_SSP,SS Function Circuits Power-Down Control Powers down all SS function circuitry in the PHY for IDDQ testing." "0,1" newline bitfld.long 0x4 19. "TEST_POWERDOWN_HSP,HS Function Circuits Power-Down Control Powers down all HS function circuitry in the PHY for IDDQ testing. Before asserting this signal ensure that VDATSRCENB<#> VDATDETENB<#> DCDENB<#> BYPASSSEL<#> and test_burnin are set to 1'b0." "0,1" hexmask.long.byte 0x4 13.--18. 1. "FSEL,Selects the reference clock frequency used for both SS and HS operations. The value for fsel combined with the other clock and enable signals determine the clock frequency used for SS and HS operations and if a shared or separate reference clock is.." newline hexmask.long.byte 0x4 8.--12. 1. "ACJT_LEVEL,1149.6 Receiver Sensitivity Level Control Selects the sensitivity level for the 1149.6 receiver for AC JTAG. Set the level based on the amplitude of the incoming Step during AC JTAG boundary scan testing." bitfld.long 0x4 7. "MPLL_REFSSC_CLK_EN,Double-Word Clock Enable" "0,1" newline hexmask.long.byte 0x4 0.--6. 1. "MPLL_MULTIPLIER,MPLL Frequency Multiplier Control Multiplies the reference clock to a frequency suitable for intended operating speed." line.long 0x8 "CTRL_2,CTRL_2" bitfld.long 0x8 31. "CHRGSEL0,Battery Charging Source Select Determines whether current is sourced onto or sunk from DP<#> or DM<#>. 1: Data source voltage (VDAT_SRC) is sourced onto DM<#> and sunk from DP<#>. 0: Data source voltage (VDAT_SRC) is sourced onto DP<#>.." "Data source voltage,Data source voltage" bitfld.long 0x8 30. "LANE0_TX2RX_LOOPBK,Loopback. When this signal is asserted data from the transmit predriver is looped back to the receive slicers. LOS is bypassed and based on the tx0_en input so that rx0_los = !tx0_data_en." "0,1" newline bitfld.long 0x8 29. "LANE0_EXT_PCLK_REQ,External PIPE Clock Enable Request. When asserted this signal enables the pipeX_pclk output regardless of power state (along with the associated increase in power consumption). You can use this input to enable pipeX_pclk in the P3.." "0,1" hexmask.long.byte 0x8 23.--28. 1. "PCS_TX_DEEMPH_6DB,TX De-Emphasis at 6 dB This static value sets the TX driver de-emphasis value when pipeP_tx_deemph[1:0] is set to 2'b10 (according to the PIPE3 specification). This bus is provided for completeness and as a second potential launch.." newline hexmask.long.byte 0x8 17.--22. 1. "PCS_TX_DEEMPH_3P5DB,TX De-Emphasis at 3.5 dB This static value sets the TX driver de-emphasis value when pipeX_tx_deemph[1:0] is set to 2'b01 (according to the PIPE3 specification). To enable tuning at the board level for RX eye compliance connect this.." hexmask.long.word 0x8 7.--16. 1. "PCS_RX_LOS_MASK_VAL,Configurable Loss-of-Signal Mask Width Sets the number of reference clock cycles to mask the incoming LFPS in U3 and U2 states. Masks the incoming LFPS for the number of reference clock cycles equal to the value of.." newline hexmask.long.byte 0x8 0.--6. 1. "PCS_TX_SWING_FULL,TX Amplitude (Full Swing Mode) This static value sets the launch amplitude of the transmitter. To enable tuning at the board level for RX eye compliance connect this signal to a register." line.long 0xC "CTRL_3,CTRL_3" bitfld.long 0xC 31. "VATESTENB,Analog Test Pin Select Enables analog test voltages to be placed on the ID<#> pin. 1: Analog test voltages can be viewed or applied on ID<#>. 0: Analog test voltages cannot be viewed or applied on ID<#>." "Analog test voltages cannot be viewed or applied..,Analog test voltages can be viewed or applied on.." bitfld.long 0xC 28.--30. "SQRXTUNE0,Adjusts the voltage level for the threshold used to detect valid high-speed data." "0,1,2,3,4,5,6,7" newline bitfld.long 0xC 27. "RX0LOSLFPSEN,Enables the RX LOS LFPS mode use when you want to detect incoming LFPS signals USB3.0" "0,1" bitfld.long 0xC 26. "RETENABLEN,Lowered Digital Supply Indicator." "0,1" newline bitfld.long 0xC 24.--25. "REFCLKSEL,Reference Clock Select for PLL Block" "0,1,2,3" bitfld.long 0xC 21.--23. "OTGTUNE0,VBUS Valid Threshold Adjustment This bus adjusts the voltage level for the VBUS<#> valid threshold. To enable tuning at the board level connect this bus to a register. 111: + 9% 110: + 6% 101: + 3% 100: 0 (default) 011: - 3%.." "0,1,2,3,4,5,6,7" newline bitfld.long 0xC 20. "OTGDISABLE0,OTG Block Disable This controller signal powers down the OTG block which disables the VBUS Valid and Session End comparators. The Session Valid comparator (the output of which is used to enable the pull-up resistor on DP<#> in Device mode).." "OTG block is powered up,OTG block is powered down" bitfld.long 0xC 19. "LOOPBACKENB0,Loopback Test Enable This controller signal places the USB 3.0 femtoPHY in HS Loopback mode which concurrently enables the HS receive and transmit logic. 1: During HS data transmission the HS receive logic is enabled. 0: During HS.." "During HS data transmission,During HS data transmission" newline bitfld.long 0xC 18. "HSXCVREXTCTL0,HS Transceiver Asynchronous Control. This signal asynchronously selects the HS transceiver TX/RX path and can be used with the bypass signals to perform proprietary tests on the HS TX / RX paths. (For information about the bypass signals.." "FS TX/RX path is selected,HS TX/RX path is selected" bitfld.long 0xC 16.--17. "CHRGSRCPUENB0,Charger Source Pull-Up Enable." "0,1,2,3" newline bitfld.long 0xC 15. "AUTORSMENB0,AUTORSMENB0" "0,1" bitfld.long 0xC 14. "ATERESET,Reset Input from Automatic Test Equipment When the USB 3.0 femtoPHY is powered up (not in Suspend or Sleep mode) an automatic tester can use this test signal to disable PHYCLOCK<#> and FREECLK then re-enable them with an aligned phase. 1:.." "PHYCLOCK<#> and FREECLK outputs are available..,PHYCLOCK<#> and FREECLK outputs are disabled" newline bitfld.long 0xC 13. "FSSE0EXT0,USB 1.1 SE0 Generation This controller signal sets the USB (2.0) to an SE0 state. This signal is valid only if FSXCVROWNER<#> is set to 1'b1 and TXENABLEN<#> is set to 1'b0. 1: D+ and D- lines are driven to an SE0 state. 0: D+ and D-.." "D+ and D,D+ and D" bitfld.long 0xC 12. "FSDATAEXT0,USB 1.1 Transmit Data This controller signal sets the USB (2.0) to either a J or K state. This signal is valid only if FSXCVROWNER<#> is set to 1'b1 TXENABLEN<#> is set to 1'b0 and FSSE0EXT<#> is set to 1'b0. 1: D+ and D- lines are.." "D+ and D,D+ and D" newline bitfld.long 0xC 11. "TXENABLEN0,USB 1.1 Data Enable This controller signal enables the FSDATAEXT<#> and FSSE0EXT<#> inputs. TXENABLEN<#> is valid only when the FSXCVROWNER<#> signal is set to 1'b1. 1: FSDATAEXT<#> and FSSE0EXT<#> are disabled. 0: FSDATAEXT<#> and.." "FSDATAEXT<#> and FSSE0EXT<#> are enabled,FSDATAEXT<#> and FSSE0EXT<#> are disabled" bitfld.long 0xC 10. "TXBITSTUFFENH0,High-Byte Transmit Bit-Stuffing Enable This controller signal controls bit stuffing on DATAINH<#>[7:0] when OPMODE<#>[1:0] = 2'b11. 1: Bit stuffing is enabled. 0: Bit stuffing is disabled." "Bit stuffing is disabled,Bit stuffing is enabled" newline bitfld.long 0xC 9. "TXBITSTUFFEN0,Low-Byte Transmit Bit-Stuffing Enable This controller signal controls bit stuffing on DATAIN<#>[7:0] when OPMODE<#>[1:0] = 2'b11. 1: Bit stuffing is enabled. 0: Bit stuffing is disabled." "Bit stuffing is disabled,Bit stuffing is enabled" bitfld.long 0xC 8. "IDPULLUP0,Analog ID Input Sample Enable This controller signal controls ID<#> line sampling. 1: ID<#> pin sampling is enabled and the IDDIG0 output is valid. 0: ID<#> pin sampling is disabled and the IDDIG0 output is not valid." "ID<#> pin sampling is disabled,ID<#> pin sampling is enabled" newline bitfld.long 0xC 7. "VDATSRCENB0,Battery Charging Sourcing Select Enables or disables sourcing for battery charging. 1: Data source voltage (VDAT_SRC) is enabled. 0: Data source voltage (VDAT_SRC) is disabled. During USB 3.0 femtoPHY normal operation set this signal.." "Data source voltage,Data source voltage" bitfld.long 0xC 6. "VDATDETENB0,Battery Charging Attach/Connect Detection Enable Enables or disables attach/connect detection. 1: Data detect voltage (CHG_DET) is enabled. 0: Data detect voltage (CHG_DET) is disabled. During USB 3.0 femtoPHY normal operation set.." "Data detect voltage,Data detect voltage" newline bitfld.long 0xC 5. "DCDENB0,Data Contact Detection Enable. Enables current sourcing on the D+ line. For special applications the IDP_SRC control and the RDM_DWN control are separated. For standard DCD operation in accordance with the Battery Charger v1.2 specification.." "IDP_SRC current is disabled,IDP_SRC current is sourced onto DP<#>" hexmask.long.byte 0xC 0.--4. 1. "LANE0_TX_TERM_OFFSET,Transmitter Termination Offset" line.long 0x10 "CTRL_4,CTRL_4" bitfld.long 0x10 31. "REF_CLK_SW_32K,REF_CLK switch to 32K" "0,1" bitfld.long 0x10 28.--30. "CR_CKDIV,CR clock div" "0,1,2,3,4,5,6,7" newline bitfld.long 0x10 27. "CR_MODE,CR mode" "0,1" bitfld.long 0x10 26. "COMMONONN,Common Block Power-Down Control Controls the power-down signals in the PLL block when the USB 3.0 femtoPHY is in Suspend or Sleep mode. 1: In Suspend or Sleep mode the PLL block is powered down. 0: In Suspend or Sleep mode the PLL.." "In Suspend or Sleep mode,In Suspend or Sleep mode" newline bitfld.long 0x10 25. "BYPASSSEL0,Transmitter Digital Bypass Select Enables/disables Transmitter Digital Bypass mode. The standard FS UART mode is selected by setting HSXCVREXTCTL<#> to 1'b0 and a proprietary HS test mode is selected by setting HSXCVREXTCTL<#> to 1'b1. 1:.." "Transmitter Digital Bypass mode is disabled,Transmitter Digital Bypass mode is enabled" bitfld.long 0x10 24. "BYPASSDPEN0,DP<#> Transmitter Digital Bypass Enable. Enables/disables the DP<#> FS/LS driver (if HSXCVREXTCTL<#> is set to 1'b0) or the DP<#> and DM<#> HS driver (if HSXCVREXTCTL<#> is set to 1'b1) in Transmitter Digital Bypass mode. FS mode is the.." "DP<#> FS/LS driver,DP<#> FS/LS driver" newline bitfld.long 0x10 23. "BYPASSDPDATA0,Data for DP<#> Transmitter Digital Bypass. In Transmitter Digital Bypass mode this signal provides the data that is transmitted on DP<#>. To use this signal BYPASSSEL<#> must be set to 1'b1. When HSXCVREXTCTL<#> is set to 1'b0 the FS/LS.." "HS driver transmits K,HS driver transmits J" bitfld.long 0x10 22. "BYPASSDMEN0,DM<#> Transmitter Digital Bypass Enable. Enables/disables the DM<#> FS/LS driver (if HSXCVREXTCTL<#> is set to 1'b0) in Transmitter Digital Bypass mode. FS mode is the standard UART mode. To use this mode BYPASSSEL<#> must be set to 1'b1." "DM<#> FS/LS driver,DM<#> FS/LS driver" newline bitfld.long 0x10 21. "BYPASSDMDATA0,Data for DM<#> Transmitter Digital Bypass. In Transmitter Digital Bypass mode this signal provides the data that is transmitted on DM<#>. To use this signal BYPASSSEL<#> must be set to 1'b1. When HSXCVREXTCTL<#> is set to 1'b0 the FS/LS.." "DM<#> FS/LS driver drives to a low state,DM<#> FS/LS driver drives to a high state" bitfld.long 0x10 20. "VBUSVLDEXTSEL0,External VBUS Valid Select Selects the VBUSVLDEXT<#> input or the internal Session Valid comparator to indicate when the VBUS<#> signal on the USB cable is valid. 1: VBUSVLDEXT<#> input is used. 0: Internal Session Valid comparator.." "Internal Session Valid comparator is used,VBUSVLDEXT<#> input is used" newline bitfld.long 0x10 19. "VBUSVLDEXT0,External VBUS Valid Indicator Valid in Device mode and only when the VBUSVLDEXTSEL0 signal is set to 1'b1. VBUSVLDEXT<#> indicates whether the VBUS<#> signal on the USB cable is valid. In addition VBUSVLDEXT<#> enables the pull- up resistor.." "VBUS<#> signal is not valid,VBUS<#> signal is valid" bitfld.long 0x10 17.--18. "VDATREFTUNE0,Data Detect Voltage Adjustment. Adjusts the threshold voltage level (Vdat_ref) used to detect data during charger-type detection. 11: - 20% 10: - 10% 01: 0 (default) 00: + 10%" "0,1,2,3" newline hexmask.long.byte 0x10 13.--16. 1. "TXVREFTUNE0,HS DC Voltage Level Adjustment Adjusts the high-speed DC level voltage. To enable tuning at the board level connect this bus to a register. 1111: + 8.75% 1110: + 7.5% 1101: + 6.25% 1100: + 5% 1011: + 3.75% 1010: +.." bitfld.long 0x10 11.--12. "TXRISETUNE0,HS Transmitter Rise/Fall Time Adjustment Adjusts the rise/fall times of the high-speed waveform. To enable tuning at the board level connect this bit to a register. 11: - 10% 10: 0 (default) 01: + 15% 00: + 20%" "0,1,2,3" newline bitfld.long 0x10 9.--10. "TXRESTUNE0,USB Source Impedance Adjustment Some applications require additional devices to be added on the USB such as a series switch which can add significant series resistance. This bus adjusts the driver source impedance (for both pull-up/pull-down.." "0,1,2,3" bitfld.long 0x10 8. "TXPREEMPPULSETUNE0,HS Transmitter Pre-Emphasis Duration Control This signal controls the duration for which the HS pre-emphasis current is sourced onto DP<#> or DM<#>. The HS Transmitter pre- emphasis duration is defined in terms of unit amounts. One.." "Long,Short" newline bitfld.long 0x10 6.--7. "TXPREEMPAMPTUNE0,HS Transmitter Pre-Emphasis Current Control This signal controls the amount of current sourced to DP<#> and DM<#> after a J-to-K or K-to-J transition. The HS Transmitter pre- emphasis current is defined in terms of unit amounts. One unit.." "Disabled,?,?,?" bitfld.long 0x10 4.--5. "TXHSXVTUNE0,Transmitter High-Speed Crossover Adjustment This bus adjusts the voltage at which the DP<#> and DM<#> signals cross while transmitting in HS mode. 11: 0 (default) 10: + 15 mV 01: - 15 mV 00: Reserved" "Reserved,?,?,?" newline hexmask.long.byte 0x10 0.--3. 1. "TXFSLSTUNE0,FS/LS Source Impedance Adjustment Adjusts the low- and full-speed single-ended source impedance while driving high. To enable tuning at the board level connect this bus to a register. 1111: - 5% 0111: -2.5% 0011: 0 (default).." repeat 3. (list 0x5 0x6 0x7 )(list 0x0 0x4 0x8 ) group.long ($2+0x14)++0x3 line.long 0x0 "CTRL_$1,CTRL_5" hexmask.long 0x0 0.--31. 1. "RSVD0,RSVD0" repeat.end rgroup.long 0x80++0x3 line.long 0x0 "STS_0,STS_0" hexmask.long.tbyte 0x0 12.--31. 1. "RSVD0,RSVD0" bitfld.long 0x0 11. "BVALID0,B-Device Session Valid Indicator This controller signal is output from the USB 3.0 femtoPHY's Session. Valid comparator and indicates whether the session for a B-device is valid. 1: Session for the B-device is valid. 0: Session for the.." "Session for the B-device is not valid,Session for the B-device is valid" newline bitfld.long 0x0 10. "AVALID0,A-Device Session Valid Indicator This controller signal is output from the USB 3.0 femtoPHY's Session. Valid comparator and indicates whether the session for an A-device is valid. 1: Session for the A-device is valid. 0: Session for the.." "Session for the A-device is not valid,Session for the A-device is valid" bitfld.long 0x0 9. "OTGSESSVLD0,OTG Device Session Valid Indicator (Low Voltage) This controller signal is output from the USB 3.0 femtoPHY's Session Valid comparator and indicates whether the voltage on VBUS is below the OTG Device Session Valid threshold. 1: The.." "The voltage on VBUS is below the OTG Device..,The voltage on VBUS is above the OTG Device.." newline bitfld.long 0x0 8. "IDDIG0,Mini A/B Plug Indicator This controller signal indicates whether the connected plug is a mini- A or mini-B plug. This signal must be valid within 20 ms after the IDPULLUP0 signal is set to 1'b1. 1: Connected plug is a mini-B plug. 0:.." "Connected plug is a mini-A plug,Connected plug is a mini-B plug" bitfld.long 0x0 7. "HSSQUELCH0,HS Squelch Detector Asynchronous Output. This signal asynchronously outputs the state of the HS squelch detector and can be used with the bypass signals to perform proprietary tests on the HS RX block. (For information about the bypass signals.." "If HSXCVREXTCTL<#> is set to 1'b1,If HSXCVREXTCTL<#> is set to 1'b1" newline bitfld.long 0x0 6. "HSRXDAT0,HS Transceiver Asynchronous Data Output. This signal asynchronously outputs the state of the HS receiver and can be used with the bypass signals to perform proprietary tests on the HS RX block. (For information about the bypass signals see the.." "If HSXCVREXTCTL<#> is set to 1'b1 and..,If HSXCVREXTCTL<#> is set to 1'b1 and.." bitfld.long 0x0 5. "FSVPLUS0,Single-Ended D+ Indicator This controller signal indicates the state of the D+ line in normal operation. 1: Voltage on D+ is high. 0: Voltage on D+ is low." "Voltage on D+ is low,Voltage on D+ is high" newline bitfld.long 0x0 4. "FSVMINUS0,Single-Ended D- Indicator This controller signal indicates the state of the D- line in normal operation. 1: Voltage on D- is high. 0: Voltage on D- is low." "Voltage on D,Voltage on D" bitfld.long 0x0 3. "FSLSRCV0,Differential Data Receive Indicator This controller signal indicates the state of differential data on the USB (2.0) during normal operation. 1: Voltage on D+ is greater than the voltage on D-. 0: Voltage on D+ is less than the voltage.." "Voltage on D+ is less than the voltage on D,Voltage on D+ is greater than the voltage on D" newline bitfld.long 0x0 2. "RTUNE_ACK,Resistor Tune Acknowledge While asserted indicates that a resistor tune is still in progress." "0,1" bitfld.long 0x0 1. "REF_CLKREQ_N,Reference Clock Removal Acknowledge" "0,1" newline bitfld.long 0x0 0. "ALT_CLK_REQ,Alternate Clock Source Request Indicates that the alternate clocks are needed by the slave PCS (that is to boot the master MPLL). Connect to alt_clk_en on the master." "0,1" repeat 7. (list 0x1 0x2 0x3 0x4 0x5 0x6 0x7 )(list 0x0 0x4 0x8 0xC 0x10 0x14 0x18 ) rgroup.long ($2+0x84)++0x3 line.long 0x0 "STS_$1,STS_1" hexmask.long 0x0 0.--31. 1. "RSVD0,RSVD0" repeat.end tree.end elif (CORENAME()=="CORTEXA55") tree "USB1" base ad:0x31220000 tree "DWC_usb3_block_gbl (USB 3.0 Global Register Block)" group.long (0x0+0x49408)++0x1F line.long 0x0 "GSBUSCFG0,Global SoC Bus Configuration Register 0 This register configures system bus DMA options for the master bus. which may be configured as AHB. AXI. or Native. Options include burst length and cache type (bufferable/posted. cacheable/snoop. and so.." hexmask.long.byte 0x0 28.--31. 1. "DATRDREQINFO,DATRDREQINFO AHB-prot/AXI-cache/OCP-ReqInfo for Data Read (DatRdReqInfo) Input to BUS-GM." newline hexmask.long.byte 0x0 24.--27. 1. "DESRDREQINFO,DESRDREQINFO AHB-prot/AXI-cache/OCP-ReqInfo for Descriptor Read (DesRdReqInfo). Input to BUS-GM." newline hexmask.long.byte 0x0 20.--23. 1. "DATWRREQINFO,DATWRREQINFO AHB-prot/AXI-cache/OCP-ReqInfo for Data Write (DatWrReqInfo). Input to BUS-GM." newline hexmask.long.byte 0x0 16.--19. 1. "DESWRREQINFO,DESWRREQINFO AHB-prot/AXI-cache/OCP-ReqInfo for Descriptor Write (DesWrReqInfo) Input to BUS-GM." newline hexmask.long.byte 0x0 12.--15. 1. "RESERVED_15_12,Reserved for future use" newline bitfld.long 0x0 11. "DATBIGEND,Data Access is Big Endian This bit controls the endian mode for data accesses. - Little-endian (default); - Big-endian; In big-endian mode DMA access (both read and write) for packet data a Byte Invariant Big-Endian mode (see 'Little-Endian.." "0,1" newline bitfld.long 0x0 10. "DESBIGEND,Descriptor Access is Big Endian This bit controls the endian mode for descriptor accesses. - Little-endian (default) - Big-endian In big-endian mode DMA access (both read and write) for descriptors uses a Byte Invariant Big-Endian mode (see.." "0,1" newline rbitfld.long 0x0 8.--9. "RESERVED_9_8,Reserved" "0,1,2,3" newline bitfld.long 0x0 7. "INCR256BRSTENA,INCR256 Burst Type Enable Input to BUS-GM. For the AHB/AXI configuration if software set this bit to 1 the AHB/AXI master uses INCR to do the 256-beat burst." "0,1" newline bitfld.long 0x0 6. "INCR128BRSTENA,INCR128 Burst Type Enable Input to BUS-GM; For the AHB/AXI configuration if software set this bit to 1 the AHB/AXI master uses INCR to do the 128-beat burst." "0,1" newline bitfld.long 0x0 5. "INCR64BRSTENA,INCR64 Burst Type Enable - Input to BUS-GM; For the AHB/AXI configuration if software set this bit to 1 the AHB/AXI master uses INCR to do the 64-beat burst." "0,1" newline bitfld.long 0x0 4. "INCR32BRSTENA,INCR32 Burst Type Enable Input to BUS-GM; For the AHB/AXI configuration if software set this bit to 1 the AHB/AXI master uses INCR to do the 32-beat burst." "0,1" newline bitfld.long 0x0 3. "INCR16BRSTENA,INCR16 Burst Type Enable Input to BUS-GM. For the AHB/AXI configuration if software set this bit to '1' the AHB/AXI master uses INCR to do the 16-beat burst." "0,1" newline bitfld.long 0x0 2. "INCR8BRSTENA,INCR8 Burst Type Enable Input to BUS-GM; For the AHB/AXI configuration if software set this bit to '1' the AHB/AXI master uses INCR to do the 8-beat burst." "0,1" newline bitfld.long 0x0 1. "INCR4BRSTENA,INCR4 Burst Type Enable Input to BUS-GM; For the AXI configuration when this bit is enabled the controller is allowed to do bursts of beat length 1 2 and 4. It is highly recommended that this bit is enabled to prevent descriptor reads and.." "0,1" newline bitfld.long 0x0 0. "INCRBRSTENA,Undefined Length INCR Burst Type Enable (INCRBrstEna) Input to BUS-GM; This bit determines the set of burst lengths the master interface uses. It works in conjunction with the GSBUSCFG0[7:1] enables (INCR256/128/64/32/16/8/4). 0: INCRX burst.." "INCRX burst mode,INCR" line.long 0x4 "GSBUSCFG1,Global SoC Bus Configuration Register 1 xHCI Register Power-On Value: If you are using a standard xHCI host driver. make sure to set the register's power-on value during coreConsultant configuration (DWC_USB3_GSBUSCFG1_INIT parameter) because.." hexmask.long.tbyte 0x4 13.--31. 1. "RESERVED_31_13,Reserved" newline bitfld.long 0x4 12. "EN1KPAGE,1k Page Boundary Enable By default (this bit is disabled) the AXI breaks transfers at the 4k page boundary. When this bit is enabled the AXI master (DMA data) breaks transfers at the 1k page boundary." "0,1" newline hexmask.long.byte 0x4 8.--11. 1. "PIPETRANSLIMIT,AXI Pipelined Transfers Burst Request Limit The field controls the number of outstanding pipelined transfer requests the AXI master pushes to the AXI slave. When the AXI master reaches this limit it does not make any more requests on the.." newline hexmask.long.byte 0x4 0.--7. 1. "RESERVED_7_0,Reserved" line.long 0x8 "GTXTHRCFG,Global Tx Threshold Control Register For more information on - Using this register. refer to 'Packet Threshold and Burst Features for High Latency Systems' section in the Databook. - Selecting values for the fields of this register. see the.." rbitfld.long 0x8 31. "RESERVED_31,Reserved" "0,1" newline rbitfld.long 0x8 30. "RESERVED_30,Reserved" "0,1" newline bitfld.long 0x8 29. "USBTXPKTCNTSEL,USB Transmit Packet Count Enable This field enables/disables the USB transmission multi-packet thresholding: - 0: USB transmission multi-packet thresholding is disabled; the controller can start transmission on the USB after the entire.." "USB transmission multi-packet thresholding is..,USB transmission multi-packet thresholding is.." newline rbitfld.long 0x8 28. "RESERVED_28,Reserved" "0,1" newline hexmask.long.byte 0x8 24.--27. 1. "USBTXPKTCNT,USB Transmit Packet Count This field specifies the number of packets that must be in the TXFIFO before the controller can start transmission for the corresponding USB transaction (burst). This field is only valid when the USB Transmit Packet.." newline hexmask.long.byte 0x8 16.--23. 1. "USBMAXTXBURSTSIZE,USB Maximum TX Burst Size When UsbTxPktCntSel is one this field specifies the Maximum Bulk OUT burst the controller can do. When the system bus is slower than the USB TX FIFO can underrun during a long burst. User can program a.." newline rbitfld.long 0x8 15. "RESERVED_15,Reserved_15" "0,1" newline rbitfld.long 0x8 14. "RESERVED_14,Reserved1(Rsvd/Rs) Register field must write only 0 by the application. The read value must be treated as X (unknown)." "0,1" newline rbitfld.long 0x8 11.--13. "RESERVED_13_11,Reserved (Rsvd/Rs) The register field must write only 0 by the application. The read value must be treated as X (unknown)." "0,1,2,3,4,5,6,7" newline hexmask.long.word 0x8 0.--10. 1. "RESERVED_10_0,Reserved for future use" line.long 0xC "GRXTHRCFG,Global Rx Threshold Control Register In a normal case. a Tx burst starts as soon as one packet is prefetched; an Rx burst starts as soon as 1-packet space is available. This works well as long as the system bus is faster than the USB 3.0 bus (a.." rbitfld.long 0xC 30.--31. "RESERVED_31_30,Reserved" "0,1,2,3" newline bitfld.long 0xC 29. "USBRXPKTCNTSEL,USB Receive Packet Count Enable This field enables/disables the USB reception multi-packet thresholding: - 0: The controller can only start reception on the USB when the RX FIFO has space for at least one packet. - 1: The controller can.." "The controller can only start reception on the..,The controller can only start reception on the.." newline rbitfld.long 0xC 28. "RESERVED_28,Reserved" "0,1" newline hexmask.long.byte 0xC 24.--27. 1. "USBRXPKTCNT,USB Receive Packet Count In host mode this field specifies the space (in terms of the number of packets) that must be available in the RX FIFO before the controller can start the corresponding USB RX transaction (burst). In device mode this.." newline hexmask.long.byte 0xC 19.--23. 1. "USBMAXRXBURSTSIZE,USB Maximum Receive Burst Size In host mode this field specifies the Maximum Bulk IN burst the DWC_usb3 controller can perform. When the system bus is slower than the USB RX FIFO can overrun during a long burst. You can program a.." newline rbitfld.long 0xC 16.--18. "RESERVED_18_16,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0xC 15. "RESERVED_15,Reserved" "0,1" newline rbitfld.long 0xC 13.--14. "RESERVED_14_13,Reserved" "0,1,2,3" newline hexmask.long.word 0xC 0.--12. 1. "RESVISOCOUTSPC,Space reserved in Rx FIFO for ISOC OUT In host mode this field is not applicable and must be programmed to 0. In device mode this value represents the amount of space to be reserved for ISOC OUT packets. The value to be programmed should.." line.long 0x10 "GCTL,Global Core Control Register Refer to /src/DWC_usb3_params.v for details on `DWC_USB3_GCTL_INIT. Note: When Hibernation is not enabled. you can write any value to GblHibernationEn. It always returns 0 when read." hexmask.long.word 0x10 19.--31. 1. "PWRDNSCALE,Power Down Scale (PwrDnScale) The USB3 suspend_clk input replaces pipe3_rx_pclk as a clock source to a small part of the USB3 controller that operates when the SS PHY is in its lowest power (P3) state and therefore does not provide a clock." newline bitfld.long 0x10 18. "MASTERFILTBYPASS,Master Filter Bypass When this bit is set to 1'b1 irrespective of the parameter `DWC_USB3_EN_BUS_FILTERS chosen all the filters in the DWC_usb3_filter module are bypassed. The double synchronizers to mac_clk preceding the filters are.." "0,1" newline bitfld.long 0x10 17. "BYPSSETADDR,Bypass SetAddress in Device Mode. When BYPSSETADDR bit is set the device controller uses the value in the DCFG[DevAddr] bits directly for comparing the device address in the tokens. For simulation you can use this feature to avoid sending.." "0,1" newline bitfld.long 0x10 16. "U2RSTECN,U2RSTECN If the SuperSpeed connection fails during POLL or LMP exchange the device connects at non-SS mode. If this bit is set then device attempts three more times to connect at SS even if it previously failed to operate in SS mode. For each.." "0,1" newline bitfld.long 0x10 14.--15. "FRMSCLDWN,FRMSCLDWN This field scales down device view of a SOF/USOF/ITP duration. For SS/HS mode: - Value of 2'h3 implements interval to be 15.625 us - Value of 2'h2 implements interval to be 31.25 us - Value of 2'h1 implements interval to be 62.5 us -.." "0,1,2,3" newline bitfld.long 0x10 12.--13. "PRTCAPDIR,PRTCAPDIR: Port Capability Direction (PrtCapDir) - 2'b01: for Host configurations - 2'b10: for Device configurations Note: For static Host-only/Device-only applications use DRD Host or DRD Device mode. The combination of GCTL.PrtCapDir=2'b11.." "?,for Host configurations,for Device configurations,?" newline bitfld.long 0x10 11. "CORESOFTRESET,Core Soft Reset (CoreSoftReset) - 1'b0 - No soft reset - 1'b1 - Soft reset to controller Clears the interrupts and all the CSRs except the following registers: - GCTL - GUCTL - GSTS - GSNPSID - GGPIO - GUID - GUSB2PHYCFGn registers -.." "No soft reset,Soft reset to controller" newline bitfld.long 0x10 10. "SOFITPSYNC,SOFITPSYNC If this bit is set to '0' operating in host mode the controller keeps the UTMI/ULPI PHY on the first port in a non-suspended state whenever there is a SuperSpeed port that is not in Rx.Detect SS.Disable and U3. If this bit is set.." "0,1" newline bitfld.long 0x10 9. "U1U2TIMERSCALE,Disable U1/U2 timer Scaledown (U1U2TimerScale). If set to '1' along with GCTL[5:4] (ScaleDown) = 2'bX1 disables the scale down of U1/U2 inactive timer values. This is for simulation mode only." "0,1" newline bitfld.long 0x10 8. "DEBUGATTACH,Debug Attach When this bit is set - SS Link proceeds directly to the Polling link state (after RUN/STOP in the DCTL register is asserted) without checking remote termination; - Link LFPS polling timeout is infinite; - Polling timeout during.." "0,1" newline bitfld.long 0x10 6.--7. "RAMCLKSEL,RAM Clock Select (RAMClkSel) - 2'b00: bus clock - 2'b01: pipe clock (Only used in device mode) - 2'b10: In device mode pipe/2 clock.In Host mode controller switches ram_clk between pipe/2 clock mac2_clk and bus_clk based on the status of.." "bus clock,pipe clock,In device mode,In device mode" newline bitfld.long 0x10 4.--5. "SCALEDOWN,Scale-Down Mode (ScaleDown) When Scale-Down mode is enabled for simulation the controller uses scaled-down timing values resulting in faster simulations. When Scale-Down mode is disabled actual timing values are used. This is required for.." "Disables all scale-downs,Enables scaled down SS timing and repeat values..,No TxEq training sequences are sent,Enables bit 0 and bit 1 scale-down timing values" newline bitfld.long 0x10 3. "DISSCRAMBLE,Disable Scrambling (DisScramble) Transmit request to Link Partner on next transition to Recovery or Polling." "0,1" newline bitfld.long 0x10 2. "U2EXIT_LFPS,U2EXIT_LFPS If this bit is - 0: the link treats 248ns LFPS as a valid U2 exit. - 1: the link waits for 8us of LFPS before it detects a valid U2 exit. This bit is added to improve interoperability with a third-party host/device controller." "the link treats 248ns LFPS as a valid U2 exit,the link waits for 8us of LFPS before it detects.." newline rbitfld.long 0x10 1. "GBLHIBERNATIONEN,GblHibernationEn This bit enables hibernation at the global level. If hibernation is not enabled through this bit the PMU immediately accepts the D0->D3 and D3->D0 power state change requests but does not save or restore any controller.." "D3 and D3,?" newline bitfld.long 0x10 0. "DSBLCLKGTNG,Disable Clock Gating (DsblClkGtng) This bit is set to 1 and the controller is in Low Power mode internal clock gating is disabled. You can set this bit to 1'b1 after Power On Reset." "0,1" line.long 0x14 "GPMSTS,Global Power Management Status Register This debug register gives information on which event caused the hibernation exit. It provides internal status and state machine information. and is for Synopsys use only for debugging purposes. This register.." hexmask.long.byte 0x14 28.--31. 1. "PORTSEL,Global Power Management Status Register PortSel This field selects the port number." newline hexmask.long.word 0x14 17.--27. 1. "RESERVED_27_17,Reserved" newline hexmask.long.byte 0x14 12.--16. 1. "U3WAKEUP,U3Wakeup This field gives the following USB 3.0 port wakeup conditions: - Bit [12]: Overcurrent Detected - Bit [13]: Resume Detected - Bit [14]: Connect Detected - Bit [15]: Disconnect Detected - Bit [16]: Last Connection State" newline rbitfld.long 0x14 10.--11. "RESERVED_10_11,Reserved" "0,1,2,3" newline hexmask.long.word 0x14 0.--9. 1. "U2WAKEUP,U2Wakeup This field indicates the following USB 2.0 port wakeup conditions: - Bit [0]: Overcurrent Detected - Bit [1]: Resume Detected - Bit [2]: Connect Detected - Bit [3]: Disconnect Detected - Bit [4]: Last Connection State - Bit [5]: ID.." line.long 0x18 "GSTS,Global Status Register" hexmask.long.word 0x18 20.--31. 1. "CBELT,Current BELT Value In Host mode this field indicates the minimum value of all received device BELT values and the BELT value that is set by the Set Latency Tolerance Value command." newline hexmask.long.byte 0x18 12.--19. 1. "RESERVED_19_12,Reserved" newline rbitfld.long 0x18 11. "SSIC_IP,This field is not used." "0,1" newline rbitfld.long 0x18 10. "OTG_IP,This field is not used." "0,1" newline rbitfld.long 0x18 9. "BC_IP,Battery Charger Interrupt Pending This field indicates that there is a pending interrupt pertaining to BC in BCEVT register." "0,1" newline rbitfld.long 0x18 8. "ADP_IP,This field is not used." "0,1" newline rbitfld.long 0x18 7. "HOST_IP,Host Interrupt Pending: This field indicates that there is a pending interrupt pertaining to xHC in the Host event queue." "0,1" newline rbitfld.long 0x18 6. "DEVICE_IP,Device Interrupt Pending This field indicates that there is a pending interrupt pertaining to peripheral (device) operation in the Device event queue." "0,1" newline bitfld.long 0x18 5. "CSRTIMEOUT,CSR Timeout When this bit is 1'b1 it indicates that the software performed a write or read to a controller register that could not be completed within `DWC_USB3_CSR_ACCESS_TIMEOUT bus clock cycles (default: h1FFFF)." "0,1" newline bitfld.long 0x18 4. "BUSERRADDRVLD,Bus Error Address Valid (BusErrAddrVld) Indicates that the GBUSERRADDR register is valid and reports the first bus address that encounters a bus error. Note: Only supported in AHB and AXI configurations." "0,1" newline rbitfld.long 0x18 2.--3. "RESERVED_3_2,Reserved" "0,1,2,3" newline rbitfld.long 0x18 0.--1. "CURMOD,Current Mode of Operation (CurMod) Indicates the current mode of operation: - 2'b00: Device mode - 2'b01: Host mode" "Device mode,Host mode,?,?" line.long 0x1C "GUCTL1,Global User Control Register 1" bitfld.long 0x1C 31. "DEV_DECOUPLE_L1L2_EVT,DEV_DECOUPLE_L1L2_EVT - 0: Default behavior no change in device events L1/L2U3 events are not decoupled (old behavior of v2.90a and before) - 1: Feature enabled L1 and L2 events are separated when operating in 2.0 mode. Separate.." "Default behavior,Feature enabled" newline bitfld.long 0x1C 30. "DS_RXDET_MAX_TOUT_CTRL,DS_RXDET_MAX_TOUT_CTRL This bit is used to control the tRxDetectTimeoutDFP timer for the SuperSpeed link. - 0: Default behavior; 12ms is used as tRxDetectTimeoutDFP. - 1: 120ms is used as the tRxDetectTimeoutDFP. This bit is used.." "Default behavior; 12ms is used as..,?" newline bitfld.long 0x1C 29. "FILTER_SE0_FSLS_EOP,FILTER_SE0_FSLS_EOP - 0: Default behavior no change in Linestate check for SE0 detection in FS/LS - 1: Feature enabled FS/LS SE0 is filtered for 2 clocks for detecting EOP This bit is applicable for FS/LS operation. If this feature.." "Default behavior,Feature enabled" newline bitfld.long 0x1C 28. "TX_IPGAP_LINECHECK_DIS,TX_IPGAP_LINECHECK_DIS - 0: Default behavior no change in Linestate check - 1: Feature enabled 2.0 MAC disables Linestate check during HS transmit This bit is applicable for HS operation of u2mac. If this feature is enabled then.." "Default behavior,Feature enabled" newline bitfld.long 0x1C 27. "DEV_TRB_OUT_SPR_IND,DEV_TRB_OUT_SPR_IND - 0: Default behavior no change in TRB status dword - 1: Feature enabled OUT TRB status indicates Short Packet This bit is applicable for device mode only (and ignored in host mode). If the device application.." "Default behavior,Feature enabled" newline bitfld.long 0x1C 26. "DEV_FORCE_20_CLK_FOR_30_CLK,DEV_FORCE_20_CLK_FOR_30_CLK - 0: Default behavior Uses 3.0 clock when operating in 2.0 mode - 1: Feature enabled This bit is applicable (and to be set) for device mode (DCFG.Speed != SS) only. In the 3.0 device controller if.." "Default behavior,Feature enabled" newline bitfld.long 0x1C 25. "P3_IN_U2,P3_IN_U2 - 0: Default behavior When SuperSpeed link is in U2 PowerState P2 is attempted on the PIPE Interface. - 1: When SuperSpeed link is in U2 PowerState P3 is attempted if GUSB3PIPECTL[17] is set. Setting this bit enables P3 Power State.." "Default behavior,When SuperSpeed link is in U2" newline bitfld.long 0x1C 24. "DEV_L1_EXIT_BY_HW,DEV_L1_EXIT_BY_HW - 0: Default behavior disables device L1 hardware exit logic - 1: feature enabled This bit is applicable for device mode (2.0) only. This field enables device controller sending remote wakeup for L1 if the device.." "Default behavior,feature enabled" newline bitfld.long 0x1C 21.--23. "IP_GAP_ADD_ON,This register field is used to add on to the default inter packet gap setting in the USB 2.0 MAC. This should be programmed to a non zero value only in case where you need to increase the default inter packet delay calculations in the USB.." "0,1,2,3,4,5,6,7" newline bitfld.long 0x1C 20. "DEV_LSP_TAIL_LOCK_DIS,DEV_LSP_TAIL_LOCK_DIS - 0: Default behavior enables device lsp lock logic for tail TRB update - 1: Fix disabled This is a bug fix for STAR 9000716195 that affects the CSP mode for OUT endpoints in device mode. The issue is that.." "Default behavior,Fix disabled" newline bitfld.long 0x1C 19. "NAK_PER_ENH_FS,NAK_PER_ENH_FS - 1: Enables performance enhancement for FS async endpoints in the presence of NAKs - 0: Enhancement not applied If a periodic endpoint is present and if a bulk endpoint which is also active is being NAKed by the device.." "Enhancement not applied,Enables performance enhancement for FS async.." newline bitfld.long 0x1C 18. "NAK_PER_ENH_HS,NAK_PER_ENH_HS - 1: Enables performance enhancement for HS async endpoints in the presence of NAKs - 0: Enhancement not applied If a periodic endpoint is present and if a bulk endpoint which is also active is being NAKed by the device.." "Enhancement not applied,Enables performance enhancement for HS async.." newline bitfld.long 0x1C 17. "PARKMODE_DISABLE_SS,PARKMODE_DISABLE_SS This bit is used only in host mode and is for debug purpose only. When this bit is set to '1' all SS bus instances in park mode are disabled." "0,1" newline bitfld.long 0x1C 16. "PARKMODE_DISABLE_HS,PARKMODE_DISABLE_HS This bit is used only in host mode. When this bit is set to '1' all HS bus instances park mode are disabled. To improve performance in park mode the xHCI scheduler queues in three requests of 4 packets each for.." "0,1" newline bitfld.long 0x1C 15. "PARKMODE_DISABLE_FSLS,PARKMODE_DISABLE_FSLS This bit is used only in host mode and is for debug purpose only. When this bit is set to '1' all FS/LS bus instances in park mode disabled." "0,1" newline rbitfld.long 0x1C 13.--14. "RESERVED_14_13,Reserved" "0,1,2,3" newline rbitfld.long 0x1C 12. "DISUSB2REFCLKGTNG,Disable ref_clk gating for 2.0 PHY (DisUSB2RefClkGtng) If ref_clk gating is disabled then the ref_clk input cannot be turned off to the USB 2.0 PHY and controller. This is independent of the GCTL[DisClkGtng] setting. - 1'b0: ref_clk.." "ref_clk gating enabled for USB 2,ref_clk gating disabled for USB 2" newline rbitfld.long 0x1C 11. "DISREFCLKGTNG,Disable ref_clk gating (DisRefClkGtng) If the ref_clk gating is disabled then input ref_clk cannot be turned off to SSPHY and controller. This is independent of GCTL[DisClkGtng] setting. - 1'b0: ref_clk gating Enabled for SSPHY - 1'b1:.." "ref_clk gating Enabled for SSPHY,ref_clk gating Disabled for SSPHY" newline bitfld.long 0x1C 10. "RESUME_OPMODE_HS_HOST,RESUME_OPMODE_HS_HOST This bit is used only in host mode and is for USB 2.0 opmode behavior in HS Resume. - When this bit is set to '1' the UTMI/ULPI opmode will be changed to 'normal' along with HS terminations after EOR. This.." "0,1" newline bitfld.long 0x1C 9. "DEV_HS_NYET_BULK_SPR,DEV_HS_NYET_BULK_SPR - 0: Default behavior no change in device response - 1: Feature enabled HS bulk OUT short packet gets NYET response This bit is applicable for device mode only (and ignored in host mode) to be used in 2.0.." "Default behavior,Feature enabled" newline bitfld.long 0x1C 8. "L1_SUSP_THRLD_EN_FOR_HOST,L1_SUSP_THRLD_EN_FOR_HOST This bit is used only in host mode. The host controller asserts the utmi_l1_suspend_n and utmi_sleep_n output signals (see 'LPM Interface Signals' table in the Databook) as follows: The controller.." "0,1" newline hexmask.long.byte 0x1C 4.--7. 1. "L1_SUSP_THRLD_FOR_HOST,L1_SUSP_THRLD_FOR_HOST This field is effective only when the L1_SUSP_THRLD_EN_FOR_HOST bit is set to 1. For more details refer to the description of the L1_SUSP_THRLD_EN_FOR_HOST bit." newline bitfld.long 0x1C 3. "HC_ERRATA_ENABLE,Host ELD Enable (HELDEn) When this bit is set to 1 it enables the Exit Latency Delta (ELD) support defined in the xHCI 1.0 Errata. This bit is used only in the host mode. This bit has to be set to 1 in Host mode." "0,1" newline bitfld.long 0x1C 2. "HC_PARCHK_DISABLE,Host Parameter Check Disable (HParChkDisable) When this bit is set to '0' (by default) the xHC checks that the input slot/EP context fields comply to the xHCI Specification. Upon detection of a parameter error during command execution.." "0,1" newline bitfld.long 0x1C 1. "OVRLD_L1_SUSP_COM,OVRLD_L1_SUSP_COM If this bit is set the utmi_l1_suspend_com_n is overloaded with the utmi_sleep_n signal. This bit is usually set if the PHY stops the port clock during L1 sleep condition. Note: The recommended connection for the.." "For Synopsys PHY,?" newline bitfld.long 0x1C 0. "LOA_FILTER_EN,LOA_FILTER_EN If this bit is set the USB 2.0 port babble is checked at least three consecutive times before the port is disabled. This prevents false triggering of the babble condition when using low quality cables. Note: This bit is valid.." "0,1" rgroup.long (0x20+0x49408)++0x3 line.long 0x0 "GSNPSID,Global Synopsys ID Register This is a read-only register that contains the release number of the controller." hexmask.long 0x0 0.--31. 1. "SYNOPSYSID,Synopsys ID - SynopsysID[31:16] indicates Core Identification Number. 0x5533 is ASCII for U3 (DWC_usb3). - SynopsysID[15:0] indicates the release number. Current Release is 3.30a. Software uses this register to configure release-specific.." group.long (0x24+0x49408)++0xB line.long 0x0 "GGPIO,Global General Purpose Input/Output Register The application can use this register for general purpose input and output ports or for debugging." hexmask.long.word 0x0 16.--31. 1. "GPO,General Purpose Output The value of this field is driven out on the gp_out[15:0] output port." newline hexmask.long.word 0x0 0.--15. 1. "GPI,General Purpose Input The read value of this field reflects the gp_in[15:0] input signal value. Note: Register bit-bash test should not check for reset value of this field since its not predictable; depends on the gp_in port." line.long 0x4 "GUID,Global User ID Register This is a read/write register containing the User ID. The power-on value for this register is specified as the User Identification Register. Power-on value during coreConsultant configuration (parameter DWC_USB3_USERID). This.." hexmask.long 0x4 0.--31. 1. "USERID,USERID Application-programmable ID field." line.long 0x8 "GUCTL,Global User Control Register: This register provides a few options for the software to control the controller behavior in the Host mode. Most of the options are used to improve host inter-operability with different devices." hexmask.long.word 0x8 22.--31. 1. "REFCLKPER,REFCLKPER This field indicates in terms of nano seconds the period of ref_clk. The default value of this register is set to 'h8 (8ns/125 MHz). This field needs to be updated during power-on initialization if GCTL.SOFITPSYNC or.." newline bitfld.long 0x8 21. "NOEXTRDL,No Extra Delay Between SOF and the First Packet(NoExtrDl) Some HS devices misbehave when the host sends a packet immediately after a SOF. However adding an extra delay between a SOF and the first packet can reduce the USB data rate and.." "Host waits for 2 microseconds after a SOF before..,Host doesn't wait after a SOF before it sends.." newline rbitfld.long 0x8 18.--20. "RESERVED_20_18,Reserved" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 17. "SPRSCTRLTRANSEN,Sparse Control Transaction Enable Some devices are slow in responding to Control transfers. Scheduling multiple transactions in one microframe/frame can cause these devices to misbehave. If this bit is set to 1'b1 the host controller.." "0,1" newline bitfld.long 0x8 16. "RESBWHSEPS,Reserving 85% Bandwidth for HS Periodic EPs (ResBwHSEPS) By default HC reserves 80% of the bandwidth for periodic EPs. If this bit is set the bandwidth is relaxed to 85% to accommodate two high speed high bandwidth ISOC EPs. USB 2.0.." "0,1" newline rbitfld.long 0x8 15. "RESERVED_15,Reserved" "0,1" newline bitfld.long 0x8 14. "USBHSTINAUTORETRYEN,Host IN Auto Retry (USBHstInAutoRetryEn) When set this field enables the Auto Retry feature. For IN transfers (non-isochronous) that encounter data packets with CRC errors or internal overrun scenarios the auto retry feature causes.." "Auto Retry Disabled,Auto Retry Enabled" newline bitfld.long 0x8 13. "ENOVERLAPCHK,Enable Check for LFPS Overlap During Remote Ux Exit: If this bit is set to - 1'b1: The SuperSpeed link when exiting U1/U2/U3 waits for either the remote link LFPS or TS1/TS2 training symbols before it confirms that the LFPS handshake is.." "When the link exists U1/U2/U3 because of a..,The SuperSpeed link when exiting U1/U2/U3 waits.." newline bitfld.long 0x8 12. "EXTCAPSUPPTEN,External Extended Capability Support Enable (ExtCapSuptEN) When set this field enables extended capabilities to be implemented outside the controller. When the ExtCapSupEN is set and the Debug Capability is enabled the Next Capability.." "0,1" newline bitfld.long 0x8 11. "INSRTEXTRFSBODI,Insert Extra Delay Between FS Bulk OUT Transactions (InsrtExtrFSBODl). Some FS devices are slow to receive Bulk OUT data and can get stuck when there are consecutive Bulk OUT transactions with short inter-transaction delays. This bit is.." "Host doesn't insert extra delay between..,Host inserts about 12us extra delay between.." newline bitfld.long 0x8 9.--10. "DTCT,Device Timeout Coarse Tuning (DTCT) This field is a Host mode parameter which determines how long the host waits for a response from device before considering a timeout. The controller first checks the DTCT value. If it is 0 then the timeout value.." "0,1,2,3" newline hexmask.long.word 0x8 0.--8. 1. "DTFT,Device Timeout Fine Tuning (DTFT) This field is a Host mode parameter which determines how long the host waits for a response from device before considering a timeout. For the DTFT field to take effect DTCT must be set to 2'b00. The DTFT value is.." rgroup.long (0x30+0x49408)++0x7 line.long 0x0 "GBUSERRADDRLO,Gobal SoC Bus Error Address Register - Low This is an alternate register for the GBUSERRADDR register." hexmask.long 0x0 0.--31. 1. "BUSERRADDR,Bus Address - Low (BusAddrLo) This register contains the lower 32 bits of the first bus address that encountered a SoC bus error. It is valid when the GSTS.BusErrAddrVld field is 1. It can only be cleared by resetting the controller. Note:.." line.long 0x4 "GBUSERRADDRHI,Gobal SoC Bus Error Address Register - High This is an alternate register for the GBUSERRADDR register." hexmask.long 0x4 0.--31. 1. "BUSERRADDR,Bus Address - High (BusAddrHi) This register contains the higher 32 bits of the first bus address that encountered a SoC bus error. It is valid when the GSTS.BusErrAddrVld field is 1. It can only be cleared by resetting the controller. Note:.." group.long (0x38+0x49408)++0x7 line.long 0x0 "GPRTBIMAPLO,Global SS Port to Bus Instance Mapping Register - Low This is an alternate register for the GPRTBIMAP register. Register fields are read-write with respect to number of port instantiated. writeAsRead constraint is added to limit side effects.." hexmask.long.byte 0x0 28.--31. 1. "BINUM8,BINUM8: SS USB Instance Number for Port 8. Application-programmable ID field." newline hexmask.long.byte 0x0 24.--27. 1. "BINUM7,BINUM7: SS USB Instance Number for Port 7. Application-programmable ID field." newline hexmask.long.byte 0x0 20.--23. 1. "BINUM6,BINUM6: SS USB Instance Number for Port 6. Application-programmable ID field." newline hexmask.long.byte 0x0 16.--19. 1. "BINUM5,BINUM5: SS USB Instance Number for Port 5. Application-programmable ID field." newline hexmask.long.byte 0x0 12.--15. 1. "BINUM4,BINUM4: SS USB Instance Number for Port 4. Application-programmable ID field." newline hexmask.long.byte 0x0 8.--11. 1. "BINUM3,BINUM3: SS USB Instance Number for Port 3. Application-programmable ID field." newline hexmask.long.byte 0x0 4.--7. 1. "BINUM2,BINUM2: SS USB Instance Number for Port 2. Application-programmable ID field." newline hexmask.long.byte 0x0 0.--3. 1. "BINUM1,BINUM1: SS USB Instance Number for Port 1. Application-programmable ID field." line.long 0x4 "GPRTBIMAPHI,Global SS Port to Bus Instance Mapping Register - High This is an alternate register for the GPRTBIMAP register. For a configuration with number of USB 3.0 ports same as number of SS Bus Instances. do not remap during debug session. If you.." hexmask.long.byte 0x4 28.--31. 1. "RESERVED_31_28,Reserved" newline hexmask.long.byte 0x4 24.--27. 1. "BINUM15,BINUM15: SS USB Instance Number for Port 15. Application-programmable ID field." newline hexmask.long.byte 0x4 20.--23. 1. "BINUM14,BINUM14: SS USB Instance Number for Port 14. Application-programmable ID field." newline hexmask.long.byte 0x4 16.--19. 1. "BINUM13,BINUM13: SS USB Instance Number for Port 13. Application-programmable ID field." newline hexmask.long.byte 0x4 12.--15. 1. "BINUM12,BINUM12: SS USB Instance Number for Port 12. Application-programmable ID field." newline hexmask.long.byte 0x4 8.--11. 1. "BINUM11,BINUM11: SS USB Instance Number for Port 11. Application-programmable ID field." newline hexmask.long.byte 0x4 4.--7. 1. "BINUM10,BINUM10: SS USB Instance Number for Port 10. Application-programmable ID field." newline hexmask.long.byte 0x4 0.--3. 1. "BINUM9,BINUM9: SS USB Instance Number for Port 9. Application-programmable ID field." rgroup.long (0x40+0x49408)++0x7 line.long 0x0 "GHWPARAMS0,Global Hardware Parameters Register 0 This register contains the hardware configuration options that you can select in the coreConsultant GUI. For a description of each parameter. refer to the 'Parameter Descriptions' chapter in the Databook." hexmask.long.byte 0x0 24.--31. 1. "GHWPARAMS0_31_24,`DWC_USB3_AWIDTH" newline hexmask.long.byte 0x0 16.--23. 1. "GHWPARAMS0_23_16,`DWC_USB3_SDWIDTH" newline hexmask.long.byte 0x0 8.--15. 1. "GHWPARAMS0_15_8,`DWC_USB3_MDWIDTH" newline bitfld.long 0x0 6.--7. "GHWPARAMS0_7_6,`DWC_USB3_SBUS_TYPE" "0,1,2,3" newline bitfld.long 0x0 3.--5. "GHWPARAMS0_5_3,`DWC_USB3_MBUS_TYPE" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 0.--2. "GHWPARAMS0_2_0,`DWC_USB3_MODE" "0,1,2,3,4,5,6,7" line.long 0x4 "GHWPARAMS1,Global Hardware Parameters Register 1 This register contains the hardware configuration options that you can select in the coreConsultant GUI. For a description of each parameter. refer to the 'Parameter Descriptions' chapter in the Databook." bitfld.long 0x4 31. "GHWPARAMS1_31,`DWC_USB3_EN_DBC" "0,1" newline bitfld.long 0x4 30. "GHWPARAMS1_30,`DWC_USB3_RM_OPT_FEATURES" "0,1" newline bitfld.long 0x4 29. "GHWPARAMS1_29,Reserved1" "0,1" newline bitfld.long 0x4 28. "GHWPARAMS1_28,`DWC_USB3_RAM_BUS_CLKS_SYNC" "0,1" newline bitfld.long 0x4 27. "GHWPARAMS1_27,`DWC_USB3_MAC_RAM_CLKS_SYNC" "0,1" newline bitfld.long 0x4 26. "GHWPARAMS1_26,`DWC_USB3_MAC_PHY_CLKS_SYNC" "0,1" newline bitfld.long 0x4 24.--25. "GHWPARAMS1_25_24,`DWC_USB3_EN_PWROPT" "0,1,2,3" newline bitfld.long 0x4 23. "GHWPARAMS1_23,`DWC_USB3_SPRAM_TYP" "0,1" newline bitfld.long 0x4 21.--22. "GHWPARAMS1_22_21,`DWC_USB3_NUM_RAMS" "0,1,2,3" newline hexmask.long.byte 0x4 15.--20. 1. "GHWPARAMS1_20_15,`DWC_USB3_DEVICE_NUM_INT For details on `DWC_USB3_DEVICE_NUM_INT refer to /src/DWC_usb3_params.v file." newline bitfld.long 0x4 12.--14. "GHWPARAMS1_14_12,`DWC_USB3_ASPACEWIDTH" "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 9.--11. "GHWPARAMS1_11_9,`DWC_USB3_REQINFOWIDTH" "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 6.--8. "GHWPARAMS1_8_6,`DWC_USB3_DATAINFOWIDTH" "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 3.--5. "GHWPARAMS1_5_3,`DWC_USB3_BURSTWIDTH-1" "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 0.--2. "GHWPARAMS1_2_0,`DWC_USB3_IDWIDTH-1" "0,1,2,3,4,5,6,7" repeat 2. (list 0x2 0x8 )(list 0x0 0x4B8 ) rgroup.long ($2+0x48+0x49408)++0x3 line.long 0x0 "GHWPARAMS$1,Global Hardware Parameters Register 2 This register contains the hardware configuration options that you can select in the coreConsultant GUI. For a description of each parameter. refer to the 'Parameter Descriptions' chapter in the Databook." hexmask.long 0x0 0.--31. 1. "GHWPARAMS2_31_0,`DWC_USB3_USERID" repeat.end rgroup.long (0x4C+0x49408)++0x13 line.long 0x0 "GHWPARAMS3,Global Hardware Parameters Register 3 This register contains the hardware configuration options that you can select in the coreConsultant GUI. For a description of each parameter. refer to the 'Parameter Descriptions' chapter in the Databook." bitfld.long 0x0 31. "GHWPARAMS3_31,Reserved" "0,1" newline hexmask.long.byte 0x0 23.--30. 1. "GHWPARAMS3_30_23,`DWC_USB3_CACHE_TOTAL_XFER_RESOURCES" newline hexmask.long.byte 0x0 18.--22. 1. "GHWPARAMS3_22_18,`DWC_USB3_NUM_IN_EPS" newline hexmask.long.byte 0x0 12.--17. 1. "GHWPARAMS3_17_12,`DWC_USB3_NUM_EPS" newline bitfld.long 0x0 11. "GHWPARAMS3_11,`DWC_USB3_ULPI_CARKIT" "0,1" newline bitfld.long 0x0 10. "GHWPARAMS3_10,`DWC_USB3_VENDOR_CTL_INTERFACE" "0,1" newline bitfld.long 0x0 8.--9. "GHWPARAMS3_9_8,Reserved" "0,1,2,3" newline bitfld.long 0x0 6.--7. "GHWPARAMS3_7_6,`DWC_USB3_HSPHY_DWIDTH" "0,1,2,3" newline bitfld.long 0x0 4.--5. "GHWPARAMS3_5_4,`DWC_USB3_FSPHY_INTERFACE" "0,1,2,3" newline bitfld.long 0x0 2.--3. "GHWPARAMS3_3_2,`DWC_USB3_HSPHY_INTERFACE" "0,1,2,3" newline bitfld.long 0x0 0.--1. "GHWPARAMS3_1_0,`DWC_USB3_SSPHY_INTERFACE" "0,1,2,3" line.long 0x4 "GHWPARAMS4,Global Hardware Parameters Register 4 This register contains the hardware configuration options that you can select in the coreConsultant GUI. For a description of each parameter. refer to the 'Parameter Descriptions' chapter in the Databook." hexmask.long.byte 0x4 28.--31. 1. "GHWPARAMS4_31_28,`DWC_USB3_BMU_LSP_DEPTH" newline hexmask.long.byte 0x4 24.--27. 1. "GHWPARAMS4_27_24,`DWC_USB3_BMU_PTL_DEPTH-1" newline bitfld.long 0x4 23. "GHWPARAMS4_23,`DWC_USB3_EN_ISOC_SUPT" "0,1" newline bitfld.long 0x4 22. "GHWPARAMS4_22,Reserved" "0,1" newline bitfld.long 0x4 21. "GHWPARAMS4_21,`DWC_USB3_EXT_BUFF_CONTROL" "0,1" newline hexmask.long.byte 0x4 17.--20. 1. "GHWPARAMS4_20_17,`DWC_USB3_NUM_SS_USB_INSTANCES" newline hexmask.long.byte 0x4 13.--16. 1. "GHWPARAMS4_16_13,`DWC_USB3_HIBER_SCRATCHBUFS Number of external scratchpad buffers the controller requires to save its internal state in the device mode. Each buffer is assumed to be 4KB. The scratchpad buffer array must have this many buffer pointers." newline bitfld.long 0x4 12. "GHWPARAMS4_12,Reserved" "0,1" newline bitfld.long 0x4 11. "GHWPARAMS4_11,Reserved" "0,1" newline bitfld.long 0x4 9.--10. "GHWPARAMS4_10_9,Reserved" "0,1,2,3" newline bitfld.long 0x4 7.--8. "GHWPARAMS4_8_7,Reserved" "0,1,2,3" newline bitfld.long 0x4 6. "GHWPARAMS4_6,Reserved" "0,1" newline hexmask.long.byte 0x4 0.--5. 1. "GHWPARAMS4_5_0,`DWC_USB3_CACHE_TRBS_PER_TRANSFER" line.long 0x8 "GHWPARAMS5,Global Hardware Parameters Register 5 This register contains the hardware configuration options that you can select in the coreConsultant GUI. For a description of each parameter. refer to the 'Parameter Descriptions' chapter in the Databook." hexmask.long.byte 0x8 28.--31. 1. "GHWPARAMS5_31_28,Reserved" newline hexmask.long.byte 0x8 22.--27. 1. "GHWPARAMS5_27_22,`DWC_USB3_DFQ_FIFO_DEPTH" newline hexmask.long.byte 0x8 16.--21. 1. "GHWPARAMS5_21_16,`DWC_USB3_DWQ_FIFO_DEPTH" newline hexmask.long.byte 0x8 10.--15. 1. "GHWPARAMS5_15_10,`DWC_USB3_TXQ_FIFO_DEPTH" newline hexmask.long.byte 0x8 4.--9. 1. "GHWPARAMS5_9_4,`DWC_USB3_RXQ_FIFO_DEPTH" newline hexmask.long.byte 0x8 0.--3. 1. "GHWPARAMS5_3_0,`DWC_USB3_BMU_BUSGM_DEPTH" line.long 0xC "GHWPARAMS6,Global Hardware Parameters Register 6 This register contains the hardware configuration options that you can select in the coreConsultant GUI. For a description of each parameter. refer to the 'Parameter Descriptions' chapter in the Databook." hexmask.long.word 0xC 16.--31. 1. "GHWPARAMS6_31_16,`DWC_USB3_RAM0_DEPTH" newline bitfld.long 0xC 15. "BUSFLTRSSUPPORT,`DWC_USB3_EN_BUS_FILTERS" "0,1" newline bitfld.long 0xC 14. "BCSUPPORT,`DWC_USB3_EN_BC" "0,1" newline bitfld.long 0xC 13. "OTG_SS_SUPPORT,Reserved" "0,1" newline bitfld.long 0xC 12. "ADPSUPPORT,`DWC_USB3_EN_ADP" "0,1" newline bitfld.long 0xC 11. "HNPSUPPORT,Reserved" "0,1" newline bitfld.long 0xC 10. "SRPSUPPORT,Reserved" "0,1" newline bitfld.long 0xC 8.--9. "GHWPARAMS6_9_8,Reserved" "0,1,2,3" newline bitfld.long 0xC 7. "GHWPARAMS6_7,`DWC_USB3_EN_FPGA" "0,1" newline bitfld.long 0xC 6. "GHWPARAMS6_6,`DWC_USB3_EN_DBG_PORTS" "0,1" newline hexmask.long.byte 0xC 0.--5. 1. "GHWPARAMS6_5_0,`DWC_USB3_PSQ_FIFO_DEPTH" line.long 0x10 "GHWPARAMS7,Global Hardware Parameters Register 7 This register contains the hardware configuration options that you can select in the coreConsultant GUI. For a description of each parameter. refer to the 'Parameter Descriptions' chapter in the Databook." hexmask.long.word 0x10 16.--31. 1. "GHWPARAMS7_31_16,`DWC_USB3_RAM2_DEPTH" newline hexmask.long.word 0x10 0.--15. 1. "GHWPARAMS7_15_0,`DWC_USB3_RAM1_DEPTH" group.long (0x60+0x49408)++0x3 line.long 0x0 "GDBGFIFOSPACE,Global Debug Queue/FIFO Space Available Register Bit Bash test should not be done on this debug register." hexmask.long.word 0x0 16.--31. 1. "SPACE_AVAILABLE,SPACE_AVAILABLE" newline hexmask.long.byte 0x0 9.--15. 1. "RESERVED_15_9,Reserved" newline hexmask.long.word 0x0 0.--8. 1. "FIFO_QUEUE_SELECT,FIFO/Queue Select (or) Port-Select - FIFO/Queue Select[8:5] indicates the FIFO/Queue Type - FIFO/Queue Select[4:0] indicates the FIFO/Queue Number For example 9'b0_0010_0001 refers to RxFIFO_1 and 9'b0_0101_1110 refers to TxReqQ_30. -.." rgroup.long (0x64+0x49408)++0xB line.long 0x0 "GDBGLTSSM,Global Debug LTSSM Register In multi-port host configuration. the port-number is defined by Port-Select[3:0] field in the GDBGFIFOSPACE register. Note: - GDBGLTSSM register is not applicable for USB 2.0-only mode. - Bit Bash test should not be.." bitfld.long 0x0 31. "RESERVED_31_31,Reserved" "0,1" newline bitfld.long 0x0 30. "RXELECIDLE,RxElecidle For description of RxElecIdle see table 5-4 'Status Interface Signals' of the PIPE3 Specification." "0,1" newline bitfld.long 0x0 29. "X3_XS_SWAPPING,Reserved" "0,1" newline bitfld.long 0x0 28. "X3_DS_HOST_SHUTDOWN,Reserved" "0,1" newline bitfld.long 0x0 27. "PRTDIRECTION,Reserved" "0,1" newline bitfld.long 0x0 26. "LTDBTIMEOUT,LTDB Timeout (LTDBTimeout)" "0,1" newline hexmask.long.byte 0x0 22.--25. 1. "LTDBLINKSTATE,LTDB Link State (LTDBLinkState)" newline hexmask.long.byte 0x0 18.--21. 1. "LTDBSUBSTATE,LTDB Sub-State (LTDBSubState)" newline bitfld.long 0x0 17. "ELASTICBUFFERMODE,Elastic Buffer Mode (ElasticBufferMode) For field definition refer to Table 5-3 of the PIPE3 specification." "0,1" newline bitfld.long 0x0 16. "TXELECLDLE,Tx Elec Idle (TxElecIdle) For field definition refer to Table 5-3 of the PIPE3 specification." "0,1" newline bitfld.long 0x0 15. "RXPOLARITY,Rx Polarity (RxPolarity) For field definition refer to Table 5-3 of the PIPE3 specification." "0,1" newline bitfld.long 0x0 14. "TXDETRXLOOPBACK,Tx Detect Rx/Loopback (TxDetRxLoopback) For field definition refer to Table 5-3 of the PIPE3 specification." "0,1" newline bitfld.long 0x0 11.--13. "LTDBPHYCMDSTATE,LTSSM PHY command State (LTDBPhyCmdState) - 000: PHY_IDLE (PHY command state is in IDLE. No PHY request pending) - 001: PHY_DET (Request to start Receiver detection) - 010: PHY_DET_3 (Wait for Phy_Status (Receiver detection)) - 011:.." "P1/P2/P3 request),PHY_DET,?,?,?,?,?,?" newline bitfld.long 0x0 9.--10. "POWERDOWN,POWERDOWN (PowerDown) For field definition refer to Table 5-3 of the PIPE3 specification." "0,1,2,3" newline bitfld.long 0x0 8. "RXEQTRAIN,RxEq Train For field definition refer to Table 5-3 of the PIPE3 specification." "0,1" newline bitfld.long 0x0 6.--7. "TXDEEMPHASIS,TXDEEMPHASIS (TxDeemphasis) For field definition refer to Table 5-3 of the PIPE3 specification." "0,1,2,3" newline bitfld.long 0x0 3.--5. "LTDBCLKSTATE,LTSSM Clock State (LTDBClkState) In multi-port host configuration the port number is defined by Port-Select[3:0] field in the GDBGFIFOSPACE register. Note: GDBGLTSSM register is not applicable for USB 2.0-only mode. - 000: CLK_NORM (PHY is.." "CLK_NORM,CLK_TO_P3,?,?,?,?,?,?" newline bitfld.long 0x0 2. "TXSWING,Tx Swing (TxSwing) For field definition refer to Table 5-3 of the PIPE3 specification." "0,1" newline bitfld.long 0x0 1. "RXTERMINATION,Rx Termination (RxTermination) For details on `DWC_USB3_PIPE_RXTERM_RESET_VAL refer to /src/DWC_usb3_params.v" "0,1" newline bitfld.long 0x0 0. "TXONESZEROS,Tx Ones/Zeros (TxOnesZeros) For field definition refer to Table 5-3 of the PIPE3 specification." "0,1" line.long 0x4 "GDBGLNMCC,Global Debug LNMCC Register Bit Bash test should not be done on this debug register." hexmask.long.tbyte 0x4 9.--31. 1. "RESERVED_31_9,Reserved" newline hexmask.long.word 0x4 0.--8. 1. "LNMCC_BERC,This field indicates the bit error rate information for the port selected in the GDBGFIFOSPACE.PortSelect field. This field is for debug purposes only." line.long 0x8 "GDBGBMU,Global Debug BMU Register Bit Bash test should not be done on this debug register." hexmask.long.tbyte 0x8 8.--31. 1. "BMU_BCU,BMU_BCU Debug information" newline hexmask.long.byte 0x8 4.--7. 1. "BMU_DCU,BMU_DCU Debug information" newline hexmask.long.byte 0x8 0.--3. 1. "BMU_CCU,BMU_CCU Debug information" group.long (0x70+0x49408)++0x3 line.long 0x0 "GDBGLSPMUX_HST,Global Debug LSP MUX Register - Host This register is for internal use only. If DWC_USB3_PRESERVE_LOGIC_ANALYZER_SELECT is enabled during controller configuration. then the default values readout is X (Undefined). Bit Bash test should not.." hexmask.long.byte 0x0 24.--31. 1. "RESERVED_31_24,Reserved" newline hexmask.long.byte 0x0 16.--23. 1. "LOGIC_ANALYZER_TRACE,logic_analyzer_trace Port MUX Select Currently only bits[21:16] are used. For details on how the mux controls the debug traces refer to the 'assign logic_analyzer_trace =' code section in the DWC_usb3.v file. A value of 6'h3F drives.." newline rbitfld.long 0x0 14.--15. "RESERVED_15_14,Reserved" "0,1,2,3" newline hexmask.long.word 0x0 0.--13. 1. "HOSTSELECT,Device LSP Select Selects the LSP debug information presented in the GDBGLSP register in host mode." rgroup.long (0x74+0x49408)++0x3 line.long 0x0 "GDBGLSP,Global Debug LSP Register This register is for internal debug purposes only. This register is for internal use only. If DWC_USB3_PRESERVE_LOGIC_ANALYZER_SELECT is enabled during controller configuration. then the default values readout is X.." hexmask.long 0x0 0.--31. 1. "LSPDEBUG,LSP Debug Information" repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) rgroup.long ($2+0x78+0x49408)++0x3 line.long 0x0 "GDBGEPINFO$1,Global Debug Endpoint Information Register 0 This register is for internal use only. If DWC_USB3_PRESERVE_LOGIC_ANALYZER_SELECT is enabled during controller configuration. then the default values readout is X (Undefined). Bit Bash test.." hexmask.long 0x0 0.--31. 1. "EPDEBUG,Endpoint Debug Information bits[31:0]" repeat.end group.long (0x80+0x49408)++0xF line.long 0x0 "GPRTBIMAP_HSLO,Global High-Speed Port to Bus Instance Mapping Register - Low This is an alternate register for the GPRTBIMAP_HS register. - Register fields are read-write with respect to number of port instantiated. writeAsRead constraint is added to.." hexmask.long.byte 0x0 28.--31. 1. "BINUM8,BINUM8: HS USB Instance Number for Port 8. Application-programmable ID field." newline hexmask.long.byte 0x0 24.--27. 1. "BINUM7,BINUM7: HS USB Instance Number for Port 7. Application-programmable ID field." newline hexmask.long.byte 0x0 20.--23. 1. "BINUM6,BINUM6 USB Instance Number for Port 6. Application-programmable ID field." newline hexmask.long.byte 0x0 16.--19. 1. "BINUM5,BINUM5: HS USB Instance Number for Port 5. Application-programmable ID field." newline hexmask.long.byte 0x0 12.--15. 1. "BINUM4,BINUM4: HS USB Instance Number for Port 4. Application-programmable ID field." newline hexmask.long.byte 0x0 8.--11. 1. "BINUM3,BINUM3: HS USB Instance Number for Port 3. Application-programmable ID field." newline hexmask.long.byte 0x0 4.--7. 1. "BINUM2,BINUM2: HS USB Instance Number for Port 2. Application-programmable ID field." newline hexmask.long.byte 0x0 0.--3. 1. "BINUM1,BINUM1: HS USB Instance Number for Port 1. Application-programmable ID field." line.long 0x4 "GPRTBIMAP_HSHI,Global High-Speed Port to Bus Instance Mapping Register - High This is an alternate register for the GPRTBIMAP_HS register. - Register fields are read-write with respect to number of port instantiated. writeAsRead constraint is added to.." hexmask.long.byte 0x4 28.--31. 1. "RESERVED_31_28,Reserved" newline hexmask.long.byte 0x4 24.--27. 1. "BINUM15,BINUM15: HS USB Instance Number for Port 15. Application-programmable ID field." newline hexmask.long.byte 0x4 20.--23. 1. "BINUM14,BINUM14: HS USB Instance Number for Port 14. Application-programmable ID field." newline hexmask.long.byte 0x4 16.--19. 1. "BINUM13,BINUM13: HS USB Instance Number for Port 13. Application-programmable ID field." newline hexmask.long.byte 0x4 12.--15. 1. "BINUM12,BINUM12: HS USB Instance Number for Port 12. SApplication-programmable ID field." newline hexmask.long.byte 0x4 8.--11. 1. "BINUM11,BINUM11: HS USB Instance Number for 11. Application-programmable ID field." newline hexmask.long.byte 0x4 4.--7. 1. "BINUM10,BINUM10: HS USB Instance Number for Port 10. Application-programmable ID field." newline hexmask.long.byte 0x4 0.--3. 1. "BINUM9,BINUM9: HS USB Instance Number for Port 9. Application-programmable ID field." line.long 0x8 "GPRTBIMAP_FSLO,Global Full-Speed Port to Bus Instance Mapping Register - Low This is an alternate register for the GPRTBIMAP_FS register. - Register fields are read-write with respect to number of port instantiated. writeAsRead constraint is added to.." hexmask.long.byte 0x8 28.--31. 1. "BINUM8,BINUM8: FS USB Instance Number for Port 8. Application-programmable ID field." newline hexmask.long.byte 0x8 24.--27. 1. "BINUM7,BINUM7: FS USB Instance Number for Port 7. Application-programmable ID field." newline hexmask.long.byte 0x8 20.--23. 1. "BINUM6,BINUM6: FS USB Instance Number for Port 6. Application-programmable ID field." newline hexmask.long.byte 0x8 16.--19. 1. "BINUM5,BINUM5: FS USB Instance Number for Port 5. Application-programmable ID field." newline hexmask.long.byte 0x8 12.--15. 1. "BINUM4,BINUM4: FS USB Instance Number for Port 4. Application-programmable ID field." newline hexmask.long.byte 0x8 8.--11. 1. "BINUM3,BINUM3: FS USB Instance Number for Port 3. Application-programmable ID field." newline hexmask.long.byte 0x8 4.--7. 1. "BINUM2,BINUM2: FS USB Instance Number for Port 2. Application-programmable ID field." newline hexmask.long.byte 0x8 0.--3. 1. "BINUM1,BINUM1: FS USB Instance Number for Port 1. Application-programmable ID field." line.long 0xC "GPRTBIMAP_FSHI,Global Full-Speed Port to Bus Instance Mapping Register - High This is an alternate register for the GPRTBIMAP_FS register. - Register fields are read-write with respect to number of port instantiated. writeAsRead constraint is added to.." hexmask.long.byte 0xC 28.--31. 1. "RESERVED_31_28,Reserved" newline hexmask.long.byte 0xC 24.--27. 1. "BINUM15,BINUM15: FS USB Instance Number for Port 15. Application-programmable ID field" newline hexmask.long.byte 0xC 20.--23. 1. "BINUM14,BINUM14: FS USB Instance Number for Port 14. Application-programmable ID field" newline hexmask.long.byte 0xC 16.--19. 1. "BINUM13,BINUM13: FS USB Instance Number for Port 13. Application-programmable ID field" newline hexmask.long.byte 0xC 12.--15. 1. "BINUM12,BINUM12: FS USB Instance Number for Port 12. Application-programmable ID field" newline hexmask.long.byte 0xC 8.--11. 1. "BINUM11,BINUM11: FS USB Instance Number for Port 11. Application-programmable ID field" newline hexmask.long.byte 0xC 4.--7. 1. "BINUM10,BINUM10: FS USB Instance Number for Port 10. Application-programmable ID field" newline hexmask.long.byte 0xC 0.--3. 1. "BINUM9,BINUM9: FS USB Instance Number for Port 9. Application-programmable ID field." repeat 2. (list 0x5E 0x62 )(list 0x0 0x4 ) rgroup.long ($2+0x94+0x49408)++0x3 line.long 0x0 "RESERVED_$1,Future Reserved Register at offset 0x94" hexmask.long 0x0 0.--31. 1. "RESERVED_31_0,Future use Register field" repeat.end group.long (0x9C+0x49408)++0x3 line.long 0x0 "GUCTL2,Global User Control Register 2: This register provides a few options for the software to control the controller behavior in the Host and device mode. Most of the options are used to improve inter-operability with different hosts and devices." hexmask.long.byte 0x0 26.--31. 1. "RESERVED_31_26,Reserved" newline hexmask.long.byte 0x0 19.--25. 1. "EN_HP_PM_TIMER,This register field is used to set new HP and PM timers. - To enable PM timer set GUCTL2[19] bit as 1. - To enable HP timer set GUCTL2[20] bit as 1. Default value of HP timer is 4us when HP PM timer is not enabled; when new HP timer is.." newline hexmask.long.byte 0x0 15.--18. 1. "NOLOWPWRDUR,No Low Power Duration (NOLOWPWRDUR) This bit is applicable for device mode only and is ignored in host mode. After starting a transfer on a SS ISOC endpoint the application must program these bits to prevent the device to lose frame.." newline bitfld.long 0x0 14. "RST_ACTBITLATER,Enable clearing of the command active bit for the ENDXFER command after the command execution is completed. This bit is valid in device mode only." "0,1" newline rbitfld.long 0x0 13. "RESERVED_13,Reserved for future use" "0,1" newline bitfld.long 0x0 12. "ENABLEEPCACHEEVICT,Enable Evicting Endpoint cache after Flow Control for bulk endpoints. In 3.00a release a performance enhancement was done to keep the non-stream capable bulk IN endpoint in cache after flow control. Setting this bit will disable this.." "0,1" newline bitfld.long 0x0 11. "DISABLECFC,Disable xHCI Errata Feature Contiguous Frame ID Capability This field controls the xHCI Errata feature Contiguous FrameID capability. When set the xHCI HCCPARAMS1 bit 11 will be set to 0 indicating that CFC is not supported. Disable this.." "0,1" newline hexmask.long.byte 0x0 5.--10. 1. "RXPINGDURATION,Recieve Ping Maximum Duration This field is relevant to Host mode and controls the maximum duration of received LFPS to be treated as a Ping LFPS. The Max duration of the Ping LFPS is controlled by programming this value and is in terms of.." newline hexmask.long.byte 0x0 0.--4. 1. "TXPINGDURATION,Transmit Ping Maximum Duration This field is relevant to Device mode and controls the maximum duration for which the controller should instruct the PHY to transmit a Ping LFPS. The duration of the Ping LFPS is controlled by programming.." group.long (0x100+0x49408)++0x3 line.long 0x0 "GUSB2PHYCFG,Global USB2 PHY Configuration Register The application must program this register before starting any transactions on either the SoC bus or the USB. In Device-only configurations. only one register is needed. In Host mode. per-port registers.." bitfld.long 0x0 31. "PHYSOFTRST,UTMI PHY Soft Reset (PHYSoftRst) Causes the usb2phy_reset signal to be asserted to reset a UTMI PHY. Not applicable to ULPI because ULPI PHYs are reset via their FunctionControl.Reset register and the controller automatically writes to this.." "0,1" newline bitfld.long 0x0 30. "U2_FREECLK_EXISTS,U2_FREECLK_EXISTS Specifies whether your USB 2.0 PHY provides a free-running PHY clock which is active when the clock control input is active. If your USB 2.0 PHY provides a free-running PHY clock it must be connected to the.." "USB 2,USB 2" newline bitfld.long 0x0 29. "ULPI_LPM_WITH_OPMODE_CHK,ULPI_LPM_WITH_OPMODE_CHK Support the LPM over ULPI without NOPID token to the ULPI PHY. If this bit is set the ULPI PHY is expected to qualify the EXT PID with OPMODE=2'b00 for LPM and not treat it as a NOPID. Check with your.." "A NOPID is sent before sending an EXTPID for LPM;,An EXTPID is sent without previously sending a.." newline rbitfld.long 0x0 27.--28. "HSIC_CON_WIDTH_ADJ,HSIC_CON_WIDTH_ADJ This bit is used in the HSIC device mode of operation. By default the connect duration for the HSIC device controller is thrice the strobe period. You can change this duration to 4 5 or 6 times the strobe period.." "0,1,2,3" newline rbitfld.long 0x0 26. "INV_SEL_HSIC,INV_SEL_HSIC The application driver uses this bit to control the HSIC enable/disable function. When set to '1' this bit overrides and functionally inverts the 'if_select_hsic' input signal. If {INV_SEL_HSIC if_select_hsic} is: - 00: HSIC.." "HSIC Capability is disabled,HSIC Capability is enabled" newline bitfld.long 0x0 25. "OVRD_FSLS_DISC_TIME,Overriding the FS/LS disconnect time to 32us. - If this value is 0 the FS/LS disconnect time is set to 2.5us as per the USB specification. - If this value is non-0 the disconnect detection time is set to 32us. Normally this value.." "0,1" newline bitfld.long 0x0 22.--24. "LSTRD,LS Turnaround Time (LSTRDTIM) This field indicates the value of the Rx-to-Tx packet gap for LS devices. The encoding is as follows: - 0: 2 bit times - 1: 2.5 bit times - 2: 3 bit times - 3: 3.5 bit times - 4: 4 bit times - 5: 4.5 bit times - 6: 5.." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 19.--21. "LSIPD,LS Inter-Packet Time (LSIPD) This field indicates the value of Tx-to-Tx packet gap for LS devices. The encoding is as follows: - 0: 2 bit times - 1: 2.5 bit times - 2: 3 bit times - 3: 3.5 bit times - 4: 4 bit times - 5: 4.5 bit times - 6: 5 bit.." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 18. "ULPIEXTVBUSINDIACTOR,ULPI External VBUS Indicator (ULPIExtVbusIndicator) Indicates the ULPI PHY VBUS over-current indicator. - 1'b0: PHY uses an internal VBUS valid comparator. - 1'b1: PHY uses an external VBUS valid comparator. Valid only when RTL.." "PHY uses an internal VBUS valid comparator,PHY uses an external VBUS valid comparator" newline bitfld.long 0x0 17. "ULPIEXTVBUSDRV,ULPI External VBUS Drive (ULPIExtVbusDrv) Selects supply source to drive 5V on VBUS in the ULPI PHY. - 1'b0: PHY drives VBUS with internal charge pump (default). - 1'b1: PHY drives VBUS with an external supply. (Only when RTL parameter.." "PHY drives VBUS with internal charge pump,PHY drives VBUS with an external supply" newline rbitfld.long 0x0 16. "RESERVED_16,Reserved" "0,1" newline bitfld.long 0x0 15. "ULPIAUTORES,ULPI Auto Resume (ULPIAutoRes) Sets the AutoResume bit in Interface Control register on the ULPI PHY. - 1'b0: PHY does not use the AutoResume feature. - 1'b1: PHY uses the AutoResume feature. Valid only when RTL parameter.." "PHY does not use the AutoResume feature,PHY uses the AutoResume feature" newline rbitfld.long 0x0 14. "RESERVED_14,Reserved" "0,1" newline hexmask.long.byte 0x0 10.--13. 1. "USBTRDTIM,USB 2.0 Turnaround Time (USBTrdTim) Sets the turnaround time in PHY clocks. Specifies the response time for a MAC request to the Packet FIFO Controller (PFC) to fetch data from the DFIFO (SPRAM). The following are the required values for the.." newline bitfld.long 0x0 9. "XCVRDLY,Transceiver Delay: Enables a delay between the assertion of the UTMI/ULPI Transceiver Select signal (for HS) and the assertion of the TxValid signal during a HS Chirp. When this bit is set to 1 a delay (of approximately 2.5 us) is introduced.." "0,1" newline bitfld.long 0x0 8. "ENBLSLPM,Enable utmi_sleep_n and utmi_l1_suspend_n (EnblSlpM) The application uses this bit to control utmi_sleep_n and utmi_l1_suspend_n assertion to the PHY in the L1 state. - 1'b0: utmi_sleep_n and utmi_l1_suspend_n assertion from the controller is.." "utmi_sleep_n and utmi_l1_suspend_n assertion..,utmi_sleep_n and utmi_l1_suspend_n assertion.." newline bitfld.long 0x0 7. "PHYSEL,USB 2.0 High-Speed PHY or USB 1.1 Full-Speed Serial Transceiver Select The application uses this bit to select a high-speed PHY or a full-speed transceiver. - 1'b0: USB 2.0 high-speed UTMI+ or ULPI PHY. This bit is always 0 with Write Only.." "USB 2,USB 1" newline bitfld.long 0x0 6. "SUSPENDUSB20,Suspend USB2.0 HS/FS/LS PHY (SusPHY) When set USB2.0 PHY enters Suspend mode if Suspend conditions are valid. For DRD configurations it is recommended that this bit is set to 0 during coreConsultant configuration. If it is set to 1 then.." "0,1" newline rbitfld.long 0x0 5. "FSINTF,Full-Speed Serial Interface Select (FSIntf) The application uses this bit to select a unidirectional or bidirectional USB 1.1 full-speed serial transceiver interface. - 1'b0: 6-pin unidirectional full-speed serial interface. This bit is set to 0.." "0,1" newline rbitfld.long 0x0 4. "ULPI_UTMI_SEL,ULPI or UTMI+ Select (ULPI_UTMI_Sel) The application uses this bit to select a UTMI+ or ULPI Interface. - 1'b0: UTMI+ Interface - 1'b1: ULPI Interface This bit is writable only if UTMI+ and ULPI is specified for High-Speed PHY Interface(s).." "UTMI+ Interface,ULPI Interface" newline bitfld.long 0x0 3. "PHYIF,PHY Interface (PHYIf) If UTMI+ is selected the application uses this bit to configure the controller to support a UTMI+ PHY with an 8- or 16-bit interface. - 1'b0: 8 bits - 1'b1: 16 bits ULPI Mode: 1'b0 Note: - All the enabled 2.0 ports must have.." "0,1" newline bitfld.long 0x0 0.--2. "TOUTCAL,HS/FS Timeout Calibration (TOutCal) The number of PHY clocks as indicated by the application in this field is multiplied by a bit-time factor; this factor is added to the high-speed/full-speed interpacket timeout duration in the controller to.." "0,1,2,3,4,5,6,7" rgroup.long (0x140+0x49408)++0x3 line.long 0x0 "GUSB2I2CCTL,Reserved Register" hexmask.long 0x0 0.--31. 1. "RESERVED_31_0,Reserved for future use" group.long (0x180+0x49408)++0x3 line.long 0x0 "GUSB2PHYACC_ULPI,Global USB 2.0 ULPI PHY Vendor Control Register The application uses this register to access the PHY registers. This register is always implemented when the ULPI PHY Interface is enabled during coreConsultant configuration (parameter.." hexmask.long.byte 0x0 27.--31. 1. "RESERVED_31_27,Reserved" newline rbitfld.long 0x0 26. "DISUIPIDRVR,DISUIPIDRVR" "0,1" newline bitfld.long 0x0 25. "NEWREGREQ,New Register Request The application sets this bit for a new vendor control access. Setting this bit to 1 asserts the utmi_vcontrolload_n (1'b0) on the UTMI interface." "0,1" newline rbitfld.long 0x0 24. "VSTSDONE,VSTSDONE" "0,1" newline bitfld.long 0x0 23. "VSTSBSY,VSTSBSY" "0,1" newline bitfld.long 0x0 22. "REGWR,Register Write The application sets this bit for register writes and clears it for register reads. Note: This bit is applicable for ULPI register read/write access only." "0,1" newline hexmask.long.byte 0x0 16.--21. 1. "REGADDR,Register Address The 6-bit PHY register address for immediate PHY Register Set access. Set to 6'h2F for Extended PHY Register Set access. Note: These bits are applicable for ULPI only." newline hexmask.long.byte 0x0 8.--15. 1. "EXTREGADDR,EXTREGADDR" newline hexmask.long.byte 0x0 0.--7. 1. "REGDATA,REGDATA" group.long (0x1C0+0x49408)++0x3 line.long 0x0 "GUSB3PIPECTL,Global USB 3.0 PIPE Control Register The application uses this register to configure the USB3 PHY and PIPE interface. Device-only configuration requires only one register. In Host mode. registers are implemented for each port. For more.." bitfld.long 0x0 31. "PHYSOFTRST,USB3 PHY Soft Reset After setting this bit to '1' the software needs to clear this bit. For more information refer to Figure 'Software Resets and PHY Clock Sequencing and Requirements' in the Databook." "0,1" newline bitfld.long 0x0 30. "HSTPRTCMPL,HstPrtCmpl This feature tests the PIPE PHY compliance patterns without having to have a test fixture on the USB 3.0 cable. This bit enables placing the SS port link into a compliance state. By default this bit must be set to 1'b0. In.." "0,1" newline bitfld.long 0x0 29. "U2P3OK,P3 OK for SSInactive (SSIP3ok) - 0: During link state SS.Inactive put PHY in P2 (Default) - 1: During link state SS.Inactive put PHY in P3." "During link state SS,During link state SS" newline bitfld.long 0x0 28. "DISRXDETP3,Disabled receiver detection in P3 (DisRxDetP3) - 0: If PHY is in P3 and controller needs to perform receiver detection The controller performs receiver detection in P3. (Default) - 1: If PHY is in P3 and controller needs to perform receiver.." "If PHY is in P3 and controller needs to perform..,If PHY is in P3 and controller needs to perform.." newline bitfld.long 0x0 27. "UX_EXIT_IN_PX,Ux Exit in Px (Ux_exit_in_Px) - 0: The controller does U1/U2/U3 exit in PHY power state P0 (default behavior). - 1: The controller does U1/U2/U3 exit in PHY power state P1/P2/P3 respectively. Note: This bit is used by third-party SS PHY. It.." "The controller does U1/U2/U3 exit in PHY power..,The controller does U1/U2/U3 exit in PHY power.." newline bitfld.long 0x0 26. "PING_ENHANCEMENT_EN,Ping Enhancement Enable (ping_enhancement_en) When set the Downstream port U1 ping receive timeout becomes 500 ms instead of 300 ms. Minimum Ping.LFPS receive duration is 8 ns (one mac3_clk). This field is valid for the downstream.." "0,1" newline bitfld.long 0x0 25. "U1U2EXITFAIL_TO_RECOV,U1U2exitfail to Recovery (u1u2exitfail_to_recov) When set and U1/U2 LFPS handshake fails the LTSSM transitions from U1/U2 to Recovery instead of SS Inactive. If Recovery fails then the LTSSM can enter SS.Inactive. This is an.." "0,1" newline bitfld.long 0x0 24. "REQUEST_P1P2P3,Always Request P1/P2/P3 for U1/U2/U3 (request_p1p2p3) When set the controller always requests PHY power change from P0 to P1/P2/P3 during U0 to U1/U2/U3 transition. If this bit is 0 and immediate Ux exit (remotely initiated or locally.." "0,1" newline bitfld.long 0x0 23. "STARTRXDETU3RXDET,Start Receiver Detection in U3/Rx.Detect (StartRxdetU3RxDet) If DWC_USB3_GUSB3PIPECTL_INIT[22] is set and the link is in either U3 or Rx.Detect state the controller starts receiver detection on the rising edge of this bit. This can.." "0,1" newline bitfld.long 0x0 22. "DISRXDETU3RXDET,Disable Receiver Detection in U3/Rx.Det When set the controller does not handle receiver detection in either U3 or Rx.Detect states. DWC_USB3_GUSB3PIPECTL_INIT[23] must be used to start receiver detection manually. This bit can only be.." "0,1" newline bitfld.long 0x0 19.--21. "DELAYP1P2P3,Delay P1P2P3 Delay P0 to P1/P2/P3 request when entering U1/U2/U3 until (DWC_USB3_GUSB3PIPECTL_INIT[21:19]*8) 8B10B error occurs or Pipe3_RxValid drops to 0. DWC_USB3_GUSB3PIPECTL_INIT[18] must be 1 to enable this functionality." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 18. "DELAYP1TRANS,Delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. - 1'b1: When entering U1/U2/U3 delay the transition to P1/P2/P3 until the pipe3 signals Pipe3_RxElecIdle is 1 and pipe3_RxValid is 0 -.." "When entering U1/U2/U3,When entering U1/U2/U3" newline bitfld.long 0x0 17. "SUSPENDENABLE,Suspend USB3.0 SS PHY (Suspend_en) When set and if Suspend conditions are valid the USB 3.0 PHY enters Suspend mode. For DRD configurations it is recommended that this bit is set to '0' during coreConsultant configuration. If it is set.." "0,1" newline rbitfld.long 0x0 15.--16. "DATWIDTH,PIPE Data Width (DatWidth) - 2'b00: 32 bits - 2'b01: 16 bits One clock after reset these bits receive the value seen on the pipe3_DataBusWidth. The simulation testbench uses the coreConsultant parameter to configure the VIP. These bits in the.." "0,1,2,3" newline bitfld.long 0x0 14. "ABORTRXDETINU2,Abort Rx Detect in U2 (AbortRxDetInU2) When set and the link state is U2 the controller will abort receiver detection if it receives U2 exit LFPS from the remote link partner. This bit is for the downstream port only. Note: This bit is.." "0,1" newline bitfld.long 0x0 13. "SKIPRXDET,Skip Rx Detect: When set the controller skips Rx Detection if pipe3_RxElecIdle is low. Skip is defined as waiting for the appropriate timeout then repeating the operation." "0,1" newline bitfld.long 0x0 12. "LFPSP0ALGN,LFPS P0 Align: When set - The controller deasserts LFPS transmission on the clock edge that it requests Phy power state 0 when exiting U1 U2 or U3 low power states. Otherwise LFPS transmission is asserted one clock earlier. - The.." "0,1" newline bitfld.long 0x0 11. "P3P2TRANOK,P3 P2 Transitions OK (P3P2TranOK) When set the controller transitions directly from Phy power state P2 to P3 or from state P3 to P2. When not set P0 is always entered as an intermediate state during transitions between P2 and P3 as defined.." "0,1" newline bitfld.long 0x0 10. "P3EXSIGP2,P3 Exit Signal in P2 (P3ExSigP2) When this bit is set the controller always changes the PHY power state to P2 before attempting a U3 exit handshake. This bit is used only for some non-Synopsys PHYs that cannot do LFPS in P3. Note: This bit is.." "0,1" newline bitfld.long 0x0 9. "LFPSFILTER,LFPS Filter (LFPSFilt) When set filter LFPS reception with pipe3_RxValid in PHY power state P0 that is ignore LFPS reception from the PHY unless both pipe3_Rxelecidle and pipe3_RxValid are deasserted." "0,1" newline bitfld.long 0x0 8. "RX_DETECT_TO_POLLING_LFPS_CONTROL,RX_DETECT to Polling.LFPS Control - 1'b0 (Default): Enables a 400us delay to start Polling LFPS after RX_DETECT. This allows VCM offset to settle to a proper level. - 1'b1: Disables the 400us delay to start Polling LFPS.." "?,Disables the 400us delay to start Polling LFPS.." newline bitfld.long 0x0 7. "SSICEN,This field is not used." "0,1" newline bitfld.long 0x0 6. "TX_SWING,Tx Swing (TxSwing) Refer to the PIPE3 specification." "0,1" newline bitfld.long 0x0 3.--5. "TX_MARGIN,Tx Margin[2:0] (TxMargin) Refer to Table 5-3 of the PIPE3 Specification." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 1.--2. "SS_TX_DE_EMPHASIS,Tx Deemphasis (TxDeemphasis) The value driven to the PHY is controlled by the LTSSM during USB3 Compliance mode. (Refer to Table 5-3 of the PIPE3 specification.)" "0,1,2,3" newline bitfld.long 0x0 0. "ELASTIC_BUFFER_MODE,Elastic Buffer Mode (ElasticBufferMode) (Refer to Table 5-3 of the PIPE3 specification.)" "0,1" group.long (0x200+0x49408)++0x3 line.long 0x0 "GTXFIFOSIZ0,Global Transmit FIFO Size Register This register specifies the RAM start address and depth (both in MDWIDTH-bit words) for each implemented TxFIFO. The number of TxFIFOs depends on the configuration parameters including the number of Device.." hexmask.long.word 0x0 16.--31. 1. "TXFSTADDR_N,Transmit FIFOn RAM Start Address This field contains the memory start address for TxFIFOn in MDWIDTH-bit words." newline hexmask.long.word 0x0 0.--15. 1. "TXFDEP_N,TxFIFO Depth This field contains the depth of TxFIFOn in MDWIDTH-bit words. - Minimum value: 32 - Maximum value: 32 768 For more information see 'Integrating the Controller' chapter in the User Guide." repeat 6. (list 0x1 0x3 0x4 0x5 0x6 0x7 )(list 0x0 0x8 0xC 0x10 0x14 0x18 ) group.long ($2+0x204+0x49408)++0x3 line.long 0x0 "GTXFIFOSIZ$1,Register GTXFIFOSIZ 1" hexmask.long.word 0x0 16.--31. 1. "TXFSTADDR_N,Transmit FIFOn RAM Start Address This field contains the memory start address for TxFIFOn in MDWIDTH-bit words." newline hexmask.long.word 0x0 0.--15. 1. "TXFDEP_N,TXFDEP_N" repeat.end group.long (0x208+0x49408)++0x3 line.long 0x0 "GTXFIFOSIZ2,Transmit FIFOn RAM Start Address This field contains the memory start address for TxFIFOn in MDWIDTH-bit words." hexmask.long.word 0x0 16.--31. 1. "TXFSTADDR_N,Transmit FIFOn RAM Start Address This field contains the memory start address for TxFIFOn in MDWIDTH-bit words." newline hexmask.long.word 0x0 0.--15. 1. "TXFDEP_N,TxFIFO Depth This field contains the depth of TxFIFOn in MDWIDTH-bit words. - Minimum value: 32 - Maximum value: 32 768 For more information see 'Integrating the Controller' chapter in the User Guide." group.long (0x280+0x49408)++0x3 line.long 0x0 "GRXFIFOSIZ0,Global Receive FIFO Size Register This register specifies the RAM start address and depth (both in MDWIDTH-bit words) for each implemented RxFIFO. The number of RxFIFOs depends on the configuration parameters including the number of Host Bus.." hexmask.long.word 0x0 16.--31. 1. "RXFSTADDR_N,RxFIFOn RAM Start Address (RxFStAddr_n) This field contains the memory start address for RxFIFOn in MDWIDTH-bit words." newline hexmask.long.word 0x0 0.--15. 1. "RXFDEP_N,RxFIFO Depth (RxFDep_n) This field contains the depth of RxFIFOn in MDWIDTH-bit words. - Minimum value: 32 - Maximum value: 16 384" repeat 2. (list 0x1 0x2 )(list 0x0 0x4 ) group.long ($2+0x284+0x49408)++0x3 line.long 0x0 "GRXFIFOSIZ$1,Register" hexmask.long.word 0x0 16.--31. 1. "RXFSTADDR_N,RXFSTADDR_N" newline hexmask.long.word 0x0 0.--15. 1. "RXFDEP_N,RxFIFO Depth This field contains the depth of RxFIFOn in MDWIDTH-bit words. - Minimum value: 32 - Maximum value: 16 384" repeat.end group.long (0x300+0x49408)++0xF line.long 0x0 "GEVNTADRLO,Global Event Buffer Address (Low) Register This is an alternate register for the GEVNTADRn register." hexmask.long 0x0 0.--31. 1. "EVNTADRLO,Event Buffer Address (EvntAdrLo) Holds the lower 32 bits of start address of the external memory for the Event Buffer. During operation hardware does not update this address." line.long 0x4 "GEVNTADRHI,Global Event Buffer Address (High) Register This is an alternate register for the GEVNTADRn register." hexmask.long 0x4 0.--31. 1. "EVNTADRHI,Event Buffer Address (EvntAdrHi) Holds the higher 32 bits of start address of the external memory for the Event Buffer. During operation hardware does not update this address." line.long 0x8 "GEVNTSIZ,Global Event Buffer Size Register This register holds the Event Buffer Size and the Event Interrupt Mask bit. During power-on initialization. software must initialize the size with the number of bytes allocated for the Event Buffer. The Event.." bitfld.long 0x8 31. "EVNTINTRPTMASK,Event Interrupt Mask (EvntIntMask). When set to '1' this prevents the interrupt from being generated. However even when the mask is set the events are queued." "0,1" newline hexmask.long.word 0x8 16.--30. 1. "RESERVED_30_16,Reserved" newline hexmask.long.word 0x8 0.--15. 1. "EVENTSIZ,Event Buffer Size in bytes (EVNTSiz) Holds the size of the Event Buffer in bytes; must be a multiple of four. This is programmed by software once during initialization. The minimum size of the event buffer is 32 bytes." line.long 0xC "GEVNTCOUNT,Global Event Buffer Count Register This register holds the number of valid bytes in the Event Buffer. During initialization. software must initialize the count by writing 0 to the Event Count field. Each time the hardware writes a new event to.." bitfld.long 0xC 31. "EVNT_HANDLER_BUSY,Event Handler Busy Device software event handler busy indication. The controller sets this bit when the interrupt line is asserted due to pending events. Software clears this bit (with 1'b1) when it has finished processing the events.." "0,1" newline hexmask.long.word 0xC 16.--30. 1. "RESERVED_30_16,Reserved" newline hexmask.long.word 0xC 0.--15. 1. "EVNTCOUNT,Event Count (EVNTCount) When read returns the number of valid events in the Event Buffer (in bytes). When written hardware decrements the count by the value written. When Interrupt moderation is enabled (that is DEVICE_IMODI!= 0) the.." group.long (0x50C+0x49408)++0x7 line.long 0x0 "GUCTL3,Global User Control Register 3 This register provides a few options for the software to control the controller behavior in the Host mode. Most of the options are used to improve host inter-operability with different devices." hexmask.long.word 0x0 17.--31. 1. "RESERVED_31_17,Reserved" newline bitfld.long 0x0 16. "SCH_PING_EARLY,Enable SuperSpeed Ping Transaction Packet scheduling early in the microframe. This bit is valid in Host mode only." "0,1" newline hexmask.long.word 0x0 0.--15. 1. "RESERVED_15_0,Reserved" line.long 0x4 "GTXFIFOPRIDEV,Global Device TX FIFO DMA Priority Register This register specifies the relative DMA priority level among the Device TXFIFOs (one per IN endpoint). Each register bit[n] controls the priority (1: high. 0: low) of each TXFIFO[n]. When.." hexmask.long.tbyte 0x4 8.--31. 1. "RESERVED_31_N,Reserved" newline hexmask.long.byte 0x4 0.--7. 1. "GTXFIFOPRIDEV,Device TxFIFO priority" group.long (0x518+0x49408)++0xF line.long 0x0 "GTXFIFOPRIHST,Global Host TX FIFO DMA Priority Register This register specifies the relative DMA priority level among the Host TXFIFOs (one per USB bus instance) within the associated speed group (SS or HS/FSLS). Each register bit[n] controls the.." hexmask.long 0x0 4.--31. 1. "RESERVED_31_16,Reserved" newline hexmask.long.byte 0x0 0.--3. 1. "GTXFIFOPRIHST,Host TxFIFO priority" line.long 0x4 "GRXFIFOPRIHST,Global Host RX FIFO DMA Priority Register This register specifies the relative DMA priority level among the Host RXFIFOs (one per USB bus instance) within the associated speed group (SS or HS/FSLS). Each register bit[n] controls the.." hexmask.long 0x4 3.--31. 1. "RESERVED_31_16,Reserved" newline bitfld.long 0x4 0.--2. "GRXFIFOPRIHST,Host RxFIFO priority" "0,1,2,3,4,5,6,7" line.long 0x8 "GFIFOPRIDBC,Global Host Debug Capability DMA Priority Register This register specifies the relative priority of the RXFIFOs and TXFIFOs associated with the DbC mode. It overrides the priority assigned in the corresponding indexes of the Host RXFIFO and.." hexmask.long 0x8 2.--31. 1. "RESERVED_31_2,Reserved" newline bitfld.long 0x8 0.--1. "GFIFOPRIDBC,Host DbC DMA priority" "0,1,2,3" line.long 0xC "GDMAHLRATIO,Global Host FIFO DMA High-Low Priority Ratio Register This register specifies the relative priority of the SS FIFOs with respect to the HS/FSLS FIFOs. The DMA arbiter prioritizes the HS/FSLS round-robin arbiter group every DMA High-Low.." hexmask.long.tbyte 0xC 13.--31. 1. "RESERVED_31_13,Reserved" newline hexmask.long.byte 0xC 8.--12. 1. "HSTRXFIFO,Host RXFIFO DMA High-Low Priority" newline rbitfld.long 0xC 5.--7. "RESERVED_7_5,Reserved" "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0xC 0.--4. 1. "HSTTXFIFO,Host TXFIFO DMA High-Low Priority" group.long (0x530+0x49408)++0x3 line.long 0x0 "GFLADJ,Global Frame Length Adjustment Register This register provides options for the software to control the controller behavior with respect to SOF (Start of Frame) and ITP (Isochronous Timestamp Packet) timers and frame timer functionality. It.." bitfld.long 0x0 31. "GFLADJ_REFCLK_240MHZDECR_PLS1,GFLADJ_REFCLK_240MHZDECR_PLS1 This field indicates that the decrement value that the controller applies for each ref_clk must be GFLADJ_REFCLK_240MHZ_DECR and GFLADJ_REFCLK_240MHZ_DECR +1 alternatively on each ref_clk. Set.." "0,1" newline hexmask.long.byte 0x0 24.--30. 1. "GFLADJ_REFCLK_240MHZ_DECR,This field indicates the decrement value that the controller applies for each ref_clk in order to derive a frame timer in terms of a 240-MHz clock. This field must be programmed to a non-zero value only if GFLADJ_REFCLK_LPM_SEL.." newline bitfld.long 0x0 23. "GFLADJ_REFCLK_LPM_SEL,This bit enables the functionality of running SOF/ITP counters on the ref_clk. This bit must not be set to '1' if GCTL.SOFITPSYNC bit is set to '1'. Similarly if GFLADJ_REFCLK_LPM_SEL set to '1' GCTL.SOFITPSYNC must not be set to.." "0,1" newline rbitfld.long 0x0 22. "RESERVED_22,Reserved for future use" "0,1" newline hexmask.long.word 0x0 8.--21. 1. "GFLADJ_REFCLK_FLADJ,This field indicates the frame length adjustment to be applied when SOF/ITP counter is running on the ref_clk. This register value is used to adjust the ITP interval when GCTL[SOFITPSYNC] is set to '1'; SOF and ITP interval when.." newline bitfld.long 0x0 7. "GFLADJ_30MHZ_SDBND_SEL,GFLADJ_30MHZ_SDBND_SEL This field selects whether to use the input signal fladj_30mhz_reg or the GFLADJ.GFLADJ_30MHZ to adjust the frame length for the SOF/ITP. When this bit is set to - 1 the controller uses the register field.." "0,1" newline rbitfld.long 0x0 6. "RESERVED_6,Reserved for future use" "0,1" newline hexmask.long.byte 0x0 0.--5. 1. "GFLADJ_30MHZ,GFLADJ_30MHZ This field indicates the value that is used for frame length adjustment instead of considering from the sideband input signal fladj_30mhz_reg. This enables post-silicon frame length adjustment in case the input signal.." group.long (0x540+0x49408)++0x3 line.long 0x0 "GUSB2RHBCTL,Global USB 2.0 Root Hub Control Register The application must program this register before starting any transactions on the USB if a non-default value is desired. In Host mode. per-port registers are implemented." hexmask.long 0x0 4.--31. 1. "RESERVED_31_4,Reserved" newline hexmask.long.byte 0x0 0.--3. 1. "OVRD_L1TIMEOUT,Overriding the driver programmed L1TIMEOUT value. If this value is 0 the L1 Timeout value is taken from the xHCI PORTHLPMC register. If this value is non-0 then this will override the L1 Timeout value programmed in the xHCI PORTHLPMC.." tree.end tree "DWC_usb3_block_ecc (USB 3.0 ECC Register Block)" rgroup.long (0x850+0x53248)++0xB line.long 0x0 "BRSERRCNT,Block RAM Single Bit Error Count. 8 bit count for each of the 3 RAMs." hexmask.long.byte 0x0 24.--31. 1. "RESERVED_31_24,Reserved" hexmask.long.byte 0x0 16.--23. 1. "RAM2SERRCNT,RAM2 Single bit Error Count" hexmask.long.byte 0x0 8.--15. 1. "RAM1SERRCNT,RAM1 Single bit Error Count" hexmask.long.byte 0x0 0.--7. 1. "RAM0SERRCNT,RAM0 Single bit Error Count" line.long 0x4 "BRMERRCNT,Block RAM Multiple Bit Error Count. 8 bit count for each of the 3 RAMs." hexmask.long.byte 0x4 24.--31. 1. "RESERVED_31_24,Reserved" hexmask.long.byte 0x4 16.--23. 1. "RAM2MERRCNT,RAM2 Multiple bit Error Count" hexmask.long.byte 0x4 8.--15. 1. "RAM1MERRCNT,RAM1 Multiple bit Error Count" hexmask.long.byte 0x4 0.--7. 1. "RAM0MERRCNT,RAM0 Multiple bit Error Count" line.long 0x8 "BRMECCERR,Block RAM ECC Error Vector Register" hexmask.long.tbyte 0x8 8.--31. 1. "RESERVED_31_8,Reserved" bitfld.long 0x8 7. "RAMSERR,RAM Single bit Error Status" "0,1" bitfld.long 0x8 6. "RAMMERR,RAM Multiple bit Error Status" "0,1" bitfld.long 0x8 3.--5. "RAMSERRVEC,RAM Single Error Vector" "0,1,2,3,4,5,6,7" bitfld.long 0x8 0.--2. "RAMMERRVEC,RAM Multiple Error Vector" "0,1,2,3,4,5,6,7" group.long (0x85C+0x53248)++0x3 line.long 0x0 "BRERRCTL,Block RAM ECC Error Control Register" hexmask.long 0x0 4.--31. 1. "RESERVED_31_4,Reserved" bitfld.long 0x0 3. "ECCERRINJECT,This bit should be used for testing purposes only. - 1: Inject ECC error - 0: No ECC error injected" "No ECC error injected,Inject ECC error" bitfld.long 0x0 2. "ECCEN,ECC Enable (1) or Disable (0)" "0,1" bitfld.long 0x0 1. "RSERRCLR,RAM Single bit Error Clear" "0,1" bitfld.long 0x0 0. "RMERRCLR,RAM Multiple bit Error Clear" "0,1" rgroup.long (0x860+0x53248)++0xB line.long 0x0 "BRAM0ADDRERR,Block RAM Address of RAM0 having uncorrectable error" hexmask.long.word 0x0 16.--31. 1. "RESERVED_31_16,Reserved" hexmask.long.word 0x0 0.--15. 1. "RAM0ADDRLOC,RAM0 Address Location" line.long 0x4 "BRAM1ADDRERR,Block RAM Address of RAM1 having uncorrectable error" hexmask.long.word 0x4 16.--31. 1. "RESERVED_31_16,Reserved" hexmask.long.word 0x4 0.--15. 1. "RAM1ADDRLOC,RAM1 Address Location" line.long 0x8 "BRAM2ADDRERR,Block RAM Address of RAM2 having uncorrectable error" hexmask.long.word 0x8 16.--31. 1. "RESERVED_31_16,Reserved" hexmask.long.word 0x8 0.--15. 1. "RAM2ADDRLOC,RAM1 Address Location" tree.end tree "DWC_usb3_block_dev (USB 3.0 Device Register Block)" group.long (0x0+0x50944)++0x17 line.long 0x0 "DCFG,Device Configuration Register. This register configures the controller in Device mode after power-on or after certain control commands or enumeration. Do not make changes to this register after initial programming." hexmask.long.byte 0x0 25.--31. 1. "RESERVED_31_25,Reserved" rbitfld.long 0x0 24. "RESERVED_24,reserved" "0,1" newline bitfld.long 0x0 23. "IGNSTRMPP,IgnoreStreamPP This bit only affects stream-capable bulk endpoints. When this bit is set to '0' and the controller receives a Data Packet with the Packet Pending (PP) bit set to 0 for OUT endpoints or it receives an ACK with the NumP field set.." "0,1" bitfld.long 0x0 22. "LPMCAP,LPM Capable The application uses this bit to control the LPM capabilities of the DWC_usb3 controller. If the controller operates as a non-LPM-capable device it cannot respond to LPM transactions. - 1'b0: LPM capability is not enabled. - 1'b1: LPM.." "LPM capability is not enabled,LPM capability is enabled" newline hexmask.long.byte 0x0 17.--21. 1. "NUMP,Number of Receive Buffers. This bit indicates the number of receive buffers to be reported in the ACK TP. The DWC_usb3 controller uses this field for non-control endpoints if GRXTHRCFG.UsbRxPktCntSel is set to '0'. The application can program this.." hexmask.long.byte 0x0 12.--16. 1. "INTRNUM,Interrupt number Indicates interrupt/EventQ number on which non-endpoint-specific device-related interrupts (see DEVT) are generated." newline rbitfld.long 0x0 10.--11. "RESERVED_10_11,Reserved" "0,1,2,3" hexmask.long.byte 0x0 3.--9. 1. "DEVADDR,Device Address. The application must perform the following: - Program this field after every SetAddress request. - Reset this field to zero after USB reset." newline bitfld.long 0x0 0.--2. "DEVSPD,Device Speed. Indicates the speed at which the application requires the controller to connect or the maximum speed the application can support. However the actual bus speed is determined only after the chirp sequence is completed and is based.." "High-speed,Full-speed,?,?,SuperSpeed,?,?,?" line.long 0x4 "DCTL,Device Control Register Note: When Hibernation is not enabled using GCTL.GblHibernationEn field. - you can write any value to CSS. CRS. L1HibernationEn. and KeepConnect fields - L1HibernationEn. and KeepConnect fields always return 0 when read in.." bitfld.long 0x4 31. "RUN_STOP,Run/Stop The software writes 1 to this bit to start the device controller operation. To stop the device controller operation the software must remove any active transfers and write 0 to this bit. When the controller is stopped it sets the.." "0,1" bitfld.long 0x4 30. "CSFTRST,Core Soft Reset Resets the all clock domains as follows: - This bit clears the interrupts and all the CSRs except GSTS GSNPSID GGPIO GUID GUSB2PHYCFGn registers GUSB3PIPECTLn registers DCFG DCTL DEVTEN and DSTS registers. - All module.." "0,1" newline rbitfld.long 0x4 29. "RESERVED_29,Reserved1" "0,1" hexmask.long.byte 0x4 24.--28. 1. "HIRDTHRES,HIRD Threshold (HIRD_Thres) The controller asserts output signals utmi_l1_suspend_n and utmi_sleep_n (see 'LPM Interface Signals' table in the Databook) on the basis of this signal: The controller asserts utmi_l1_suspend_n to put the PHY into.." newline hexmask.long.byte 0x4 20.--23. 1. "LPM_NYET_THRES,LPM NYET Threshold When LPM Errata is enabled: Bits [23:20]: LPM NYET Response Threshold (LPM_NYET_thres) Handshake response to LPM token specified by device application. Response depends on DCFG.LPMCap. - DCFG.LPMCap is 1'b0 - The.." bitfld.long 0x4 19. "KEEPCONNECT,Keep Connect When '1' this bit enables the save and restore programming model by preventing the controller from disconnecting from the host when DCTL.RunStop is set to '0'. It also enables the Hibernation Request Event to be generated when.." "0,1" newline bitfld.long 0x4 18. "L1HIBERNATIONEN,L1HibernationEn When this bit is set along with KeepConnect the device controller generates a Hibernation Request Event if L1 is enabled and the HIRD value in the LPM token is larger than the threshold programmed in DCTL.HIRD_Thres. The.." "0,1" bitfld.long 0x4 17. "CRS,Controller Restore State (CRS) This command is similar to the USBCMD.CRS bit in host mode and initiates the restore process. When software sets this bit to '1' the controller immediately sets DSTS.RSS to '1'. When the controller has finished the.." "0,1" newline bitfld.long 0x4 16. "CSS,Controller Save State (CSS) This command is similar to the USBCMD.CSS bit in host mode and initiates the save process. When software sets this bit to '1' the controller immediately sets DSTS.SSS to '1'. When the controller has finished the save.." "0,1" rbitfld.long 0x4 13.--15. "RESERVED_15_13,Reserved" "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 12. "INITU2ENA,Initiate U2 Enable - 1'b0: May not initiate U2 (default) - 1'b1: May initiate U2 On USB reset hardware clears this bit to 0. Software sets this bit after receiving SetFeature(U2_ENABLE) and clears this bit when ClearFeature(U2_ENABLE) is.." "May not initiate U2,May initiate U2" bitfld.long 0x4 11. "ACCEPTU2ENA,Accept U2 Enable - 1'b0: Reject U2 except when Force_LinkPM_Accept bit is set (default) - 1'b1: Controller accepts transition to U2 state if nothing is pending on the application side. On USB reset hardware clears this bit to 0. Software.." "Reject U2 except when Force_LinkPM_Accept bit is..,Controller accepts transition to U2 state if.." newline bitfld.long 0x4 10. "INITU1ENA,Initiate U1 Enable - 1'b0: May not initiate U1 (default); - 1'b1: May initiate U1. On USB reset hardware clears this bit to 0. Software sets this bit after receiving SetFeature(U1_ENABLE) and clears this bit when ClearFeature(U1_ENABLE) is.." "May not initiate U1,May initiate U1" bitfld.long 0x4 9. "ACCEPTU1ENA,Accept U1 Enable - 1'b0: Controller rejects U1 except when Force_LinkPM_Accept bit is set (default) - 1'b1: Controller accepts transition to U1 state if nothing is pending on the application side. On USB reset hardware clears this bit to 0." "Controller rejects U1 except when..,Controller accepts transition to U1 state if.." newline hexmask.long.byte 0x4 5.--8. 1. "ULSTCHNGREQ,ULSTCHNGREQ Software writes this field to issue a USB/Link state change request. A change in this field indicates a new request to the controller. If software wants to issue the same request back-to-back it must write a 0 to this field.." hexmask.long.byte 0x4 1.--4. 1. "TSTCTL,Test Control - 4'b000: Test mode disabled - 4'b001: Test_J mode - 4'b010: Test_K mode - 4'b011: Test_SE0_NAK mode - 4'b100: Test_Packet mode - 4'b101: Test_Force_Enable - Others: Reserved" newline rbitfld.long 0x4 0. "RESERVED_0,Reserved" "0,1" line.long 0x8 "DEVTEN,Device Event Enable Register This register controls the generation of device-specific events (see 'Event Buffer Content for Device-Specific Events (DEVT)' section). If an enable bit is set to 0. the event will not be generated." hexmask.long.word 0x8 17.--31. 1. "RESERVED_31_17,Reserved" bitfld.long 0x8 16. "ECCERREN,ECC Error Enable. If this bit is set to 1 the controller reports an ECC error to the software when an uncorrectable ECC occurs internally." "0,1" newline rbitfld.long 0x8 15. "RESERVED_15,Reserved" "0,1" bitfld.long 0x8 14. "L1WKUPEVTEN,L1 Resume Detected Event Enable. Note: If GUCTL1[DEV_DECOUPLE_L1L2_EVT] is enabled then this bit is for L1 Resume Detected Event Enable." "0,1" newline bitfld.long 0x8 12. "VENDEVTSTRCVDEN,Vendor Device Test LMP Received Event (VndrDevTstRcvedEn)" "0,1" rbitfld.long 0x8 11. "RESERVED_11,Reserved" "0,1" newline rbitfld.long 0x8 10. "RESERVED_10,Reserved" "0,1" bitfld.long 0x8 9. "ERRTICERREVTEN,Erratic Error Event Enable" "0,1" newline bitfld.long 0x8 8. "L1SUSPEN,L1 Suspend Event Enable Note: Only if GUCTL1[DEV_DECOUPLE_L1L2_EVT] is enabled this bit is for L1 Suspend Event Enable." "0,1" bitfld.long 0x8 7. "SOFTEVTEN,Start of (u)frame" "0,1" newline bitfld.long 0x8 6. "U3L2L1SUSPEN,U3/L2 or U3/L2L1 Suspend Event Enable. Note: - If GUCTL1[DEV_DECOUPLE_L1L2_EVT] is enabled then this bit is for U3/L2 Suspend Event Enable. - If GUCTL1[DEV_DECOUPLE_L1L2_EVT] is not enabled then this bit is for U3/L2L1 Suspend Event Enable." "0,1" bitfld.long 0x8 5. "HIBERNATIONREQEVTEN,This bit enables/disables the generation of the Hibernation Request Event." "0,1" newline bitfld.long 0x8 4. "WKUPEVTEN,U3/L2 or U3/L2L1 Resume Detected Event Enable. Note: - If GUCTL1[DEV_DECOUPLE_L1L2_EVT] is enabled then this bit is for U3/L2 Resume Detected Event Enable. - If GUCTL1[DEV_DECOUPLE_L1L2_EVT] is not enabled then this bit is for U3/L2L1 Resume.." "0,1" bitfld.long 0x8 3. "ULSTCNGEN,USB/Link State Change Event Enable" "0,1" newline bitfld.long 0x8 2. "CONNECTDONEEVTEN,Connection Done Enable" "0,1" bitfld.long 0x8 1. "USBRSTEVTEN,USB Reset Enable" "0,1" newline bitfld.long 0x8 0. "DISSCONNEVTEN,Disconnect Detected Event Enable" "0,1" line.long 0xC "DSTS,Device Status Register This register indicates the status of the device controller with respect to USB-related events. Note: When Hibernation is not enabled. RSS and SSS fields always return 0 when read." rbitfld.long 0xC 30.--31. "RESERVED_31_30,Reserved" "0,1,2,3" rbitfld.long 0xC 29. "DCNRD,Device Controller Not Ready The bit indicates that the controller is in the process of completing the state transitions after exiting from hibernation. To complete the state transitions it takes 256 bus clock cycles from the time DCTL[31].Run/Stop.." "0,1" newline bitfld.long 0xC 28. "SRE,Save Restore Error. Currently not supported." "0,1" rbitfld.long 0xC 26.--27. "RESERVED_27_26,Reserved" "0,1,2,3" newline rbitfld.long 0xC 25. "RSS,RSS Restore State Status This bit is similar to the USBSTS.RSS in host mode. When the controller finishes the restore process it completes the command by setting DSTS.RSS to '0'." "0,1" rbitfld.long 0xC 24. "SSS,SSS Save State Status This bit is similar to the USBSTS.SSS in host mode. When the controller has finished the save process it completes the command by setting DSTS.SSS to '0'." "0,1" newline rbitfld.long 0xC 23. "COREIDLE,Core Idle The bit indicates that the controller finished transferring all RxFIFO data to system memory writing out all completed descriptors and all Event Counts are zero. Note: While testing for Reset values mask out the read value. This bit.." "0,1" rbitfld.long 0xC 22. "DEVCTRLHLT,Device Controller Halted This bit is set to 0 when the Run/Stop bit in the DCTL register is set to 1. The controller sets this bit to 1 when after SW sets Run/Stop to 0 the controller is idle and the lower layer finishes the disconnect.." "0,1" newline hexmask.long.byte 0xC 18.--21. 1. "USBLNKST,USBLNKST. USB/Link State In SS mode: LTSSM State - 4'h0: U0 - 4'h1: U1 - 4'h2: U2 - 4'h3: U3 - 4'h4: SS_DIS - 4'h5: RX_DET - 4'h6: SS_INACT - 4'h7: POLL - 4'h8: RECOV - 4'h9: HRESET - 4'ha: CMPLY - 4'hb: LPBK - 4'hf: Resume/Reset In HS/FS/LS.." rbitfld.long 0xC 17. "RXFIFOEMPTY,RxFIFO Empty." "0,1" newline hexmask.long.word 0xC 3.--16. 1. "SOFFN,Frame/Microframe Number of the Received SOF. When the controller is operating at SuperSpeed - [16:3] indicates the uframe/ITP number When the controller is operating at high-speed - [16:6] indicates the frame number - [5:3] indicates the.." rbitfld.long 0xC 0.--2. "CONNECTSPD,Connected Speed (ConnectSpd) Indicates the speed at which the DWC_usb3 controller has come up after speed detection through a chirp sequence. - 3'b100: SuperSpeed (PHY clock is running at 125 or 250 MHz) - 3'b000: High-speed (PHY clock is.." "High-speed,Full-speed,?,?,SuperSpeed,?,?,?" line.long 0x10 "DGCMDPAR,Device Generic Command Parameter Register This register indicates the device command parameter. This must be programmed before or along with the device command. The available device commands are listed in DGCMD register." hexmask.long 0x10 0.--31. 1. "PARAMETER,PARAMETER" line.long 0x14 "DGCMD,Device Generic Command Register This register enables software to program the controller using a single generic command interface to send link management packets and notifications. This register contains command. control. and status fields relevant.." hexmask.long.word 0x14 16.--31. 1. "RESERVED_31_16,Reserved" hexmask.long.byte 0x14 12.--15. 1. "CMDSTATUS,Command Status - 1: CmdErr: Indicates that the device controller encountered an error while processing the command. - 0: Indicates command success" newline rbitfld.long 0x14 11. "RESERVED_11,Reserved" "0,1" bitfld.long 0x14 10. "CMDACT,Command Active The software sets this bit to 1 to enable the device controller to execute the generic command. The device controller sets this bit to 0 after executing the command." "0,1" newline rbitfld.long 0x14 9. "RESERVED_9,Reserved" "0,1" bitfld.long 0x14 8. "CMDIOC,Command Interrupt on Complete When this bit is set the device controller issues a Generic Command Completion event after executing the command. Note that this interrupt is mapped to DCFG.IntrNum. Note: This field must not set to '1' if the.." "0,1" newline hexmask.long.byte 0x14 0.--7. 1. "CMDTYP,CMDTYP Generic Command Type Specifies the type of generic command the software driver is requesting the controller to perform. - 02h: Set Periodic Parameters - 04h: Set Scratchpad Buffer Array Address Lo - 05h: Set Scratchpad Buffer Array Address.." group.long (0x20+0x50944)++0x3 line.long 0x0 "DALEPENA,Device Active USB Endpoint Enable Register. This register indicates whether a USB endpoint is active in a given configuration or interface." hexmask.long 0x0 0.--31. 1. "USBACTEP,USBACTEP USB Active Endpoints (USBActEP) This field indicates if a USB endpoint is active in the current configuration and interface. It applies to USB IN endpoints 0.15 and OUT endpoints 0.15 with one bit for each of the 32 possible endpoints." rgroup.long (0x24+0x50944)++0x3 line.long 0x0 "RSVD,Reserved" hexmask.long 0x0 0.--31. 1. "RESERVED_31_0,Reserved" group.long (0x100+0x50944)++0xF line.long 0x0 "DEPCMDPAR2,Device Physical Endpoint-n Command Parameter 2 Register (DEPCMDPAR2n) This register indicates the physical endpoint command Parameter 2. It must be programmed before issuing the command." hexmask.long 0x0 0.--31. 1. "PARAMETER,PARAMETER" line.long 0x4 "DEPCMDPAR1,Device Physical Endpoint-n Command Parameter 1 Register (DEPCMDPAR1n)" hexmask.long 0x4 0.--31. 1. "PARAMETER,PARAMETER" line.long 0x8 "DEPCMDPAR0,Device Physical Endpoint-n Command Parameter 0 Register (DEPCMDPAR0n)" hexmask.long 0x8 0.--31. 1. "PARAMETER,PARAMETER" line.long 0xC "DEPCMD,Device Physical Endpoint-n Command Register This register enables software to issue physical endpoint-specific commands. This register contains command. control. and status fields relevant to the current generic command. while the DEPCMDPAR[2:0]n.." hexmask.long.word 0xC 16.--31. 1. "COMMANDPARAM,Command Parameters or Event Parameters Command Parameters (CommandParam) when this register is written: For Start Transfer command: - [31:16]: StreamID. The USB StreamID assigned to this transfer For Start Transfer command applied to an.." hexmask.long.byte 0xC 12.--15. 1. "CMDSTATUS,Command Completion Status (CmdStatus) Additional information about the completion of this command is available in this field. The information is in the same format as bits 15:12 of the Endpoint Command Complete event see 'Device Endpoint-n.." newline bitfld.long 0xC 11. "HIPRI_FORCERM,HighPriority/ForceRM (HiPri_ForceRM) - HighPriority: Only valid for Start Transfer command - ForceRM: Only valid for End Transfer command - ClearPendIN: Only valid for Clear Stall command . Software sets this bit to clear any pending IN.." "0,1" bitfld.long 0xC 10. "CMDACT,Command Active (CmdAct) Software sets this bit to 1 to enable the device endpoint controller to execute the generic command. The device controller sets this bit to 0 when the CmdStatus field is valid and the endpoint is ready to accept another.." "0,1" newline rbitfld.long 0xC 9. "RESERVED_9,Reserved" "0,1" bitfld.long 0xC 8. "CMDIOC,CMDIOC Command Interrupt on Complete (CmdIOC) When this bit is set the device controller issues a generic Endpoint Command Complete event after executing the command. Note that this interrupt is mapped to DEPCFG.IntrNum. When the DEPCFG command.." "0,1" newline hexmask.long.byte 0xC 4.--7. 1. "RESERVED_7_4,Reserved" hexmask.long.byte 0xC 0.--3. 1. "CMDTYP,Command Type Specifies the type of command the software driver is requesting the controller to perform. - 00h: Reserved - 01h: Set Endpoint Configuration - -64 or 96-bit Parameter - 02h: Set Endpoint Transfer Resource Configuration - 32-bit.." group.long (0x300+0x50944)++0x3 line.long 0x0 "DEV_IMOD,Device Interrupt Moderation Register (DEV_IMOD) This register controls the Interrupt Moderation feature that allows the device software to throttle the interrupt rate. Key Functions: - Interrupt Moderation is enabled only when the IMOD Interval.." hexmask.long.word 0x0 16.--31. 1. "DEVICE_IMODC,Interrupt Moderation Down Counter Loaded with the DEVICE_IMODI value whenever the hardware interrupt(n) line is de-asserted from the asserted state counts down to 0 and stops. The interrupt(n) is signaled whenever this counter is 0.." hexmask.long.word 0x0 0.--15. 1. "DEVICE_IMODI,Moderation Interval (DEVICE_IMODI) This field holds the minimum inter-interrupt interval between events. The interval is specified in terms of 250ns increments. A value of 0 disables the interrupt throttling logic and interrupts are.." tree.end tree "DWC_usb3_block_bc (USB 3.0 BC Register Block)" group.long (0x0+0x52272)++0x3 line.long 0x0 "BCFG,BC Configuration Register" hexmask.long 0x0 2.--31. 1. "RESERVED_31_2,Reserved" bitfld.long 0x0 1. "IDDIG_SEL,This field is not used." "0,1" bitfld.long 0x0 0. "CHIRP_EN,Chirp Enable When this bit is 1'b1 the controller asserts the bc_chirp_on output signal to indicate an imminent chirp." "0,1" group.long (0x8+0x52272)++0x7 line.long 0x0 "BCEVT,BC Event Register Writing 1 to the info bit in this register clears the register bit and the associated interrupt." hexmask.long.byte 0x0 25.--31. 1. "RESERVED_31_25,Reserved" bitfld.long 0x0 24. "MV_CHNGEVNT,Multi-Valued input changed Event: This event indicates that there is a change in the value of at least one ACA pin value. This bit is present only if DWC_USB3_EN_BC = 1 otherwise it is Reserved." "0,1" hexmask.long.tbyte 0x0 5.--23. 1. "RESERVED_23_5,Reserved" hexmask.long.byte 0x0 0.--4. 1. "MULTVALIDBC,Multi Valued ID pin Indicates the Battery Charger ACA inputs. - MultValIdBc[4]: bc_rid_float - MultValIdBc[3]: bc_rid_gnd - MultValIdBc[2]: bc_rid_a - MultValIdBc[1]: bc_rid_b - MultValIdBc[0]: bc_rid_c" line.long 0x4 "BCEVTEN,BC Event Enable Register" hexmask.long.byte 0x4 25.--31. 1. "RESERVED_31_25,Reserved" bitfld.long 0x4 24. "MV_CHNGEVNTENA,BCEvtInfoEna[0] Multi-Valued input changed Event Enable (MV_ChngEvntEn) When this bit is set MV_ChngEvnt in BCEVT register is enabled." "0,1" hexmask.long.tbyte 0x4 0.--23. 1. "RESERVED_23_0,Reserved" tree.end tree "DWC_usb3_block_link (USB 3.0 Link Register Block)" group.long (0x0+0x53248)++0x3 line.long 0x0 "LU1LFPSRXTIM,U1/U2 LFPS Rx Timer Register - Link Layer Register for U1/U2 LFPS RX Timers. - This register is common for all SS ports." hexmask.long.word 0x0 16.--31. 1. "RESERVED_16_31,Reserved" hexmask.long.byte 0x0 8.--15. 1. "U1U2_LFPS_EXIT_RX_CLK,Programmable U1U2 LFPS EXIT RX CLKS - Applicable to Remote Partner initiated Ux exit: Time to recognize valid Ux exit request from the remote partner. - This field is encoded as the pipe clk (8ns) count for the LFPS. -- 1: 8ns -- 2:.." hexmask.long.byte 0x0 0.--7. 1. "U1U2_EXIT_RSP_RX_CLK,Programmable U1U2 EXIT RESP RX CLKS - Applicable to locally initiated Ux exit: Minimum LFPS reception from remote to consider Ux exit handshake is successful. - This field is encoded as the pipe clk (8ns) count for the LFPS. -- 1:.." group.long (0x20+0x53248)++0xB line.long 0x0 "LINK_SETTINGS,Link Setting Register - Link Layer User Control Register for enabling Link/PHY-specific options. - This register is common for all SS ports." bitfld.long 0x0 31. "RESERVED_31,Reserved" "0,1" bitfld.long 0x0 28.--30. "U1_RESID_TIMER_US,Programmable U1 MIN RESIDENCY TIMER This field specifies U1 MIN RESIDENCY TIMER value in us. Set to 0 to disable the timer." "0,1,2,3,4,5,6,7" bitfld.long 0x0 27. "RESERVED_27,Reserved" "0,1" newline bitfld.long 0x0 24.--26. "PM_LC_TIMER_US,Programmable PM_LC_TIMER This field specifies PM_LC_TIMER value in us." "0,1,2,3,4,5,6,7" hexmask.long.byte 0x0 20.--23. 1. "PM_ENTRY_TIMER_US,Programmable PM_ENTRY_TIMER This field specifies PM_ENTRY_TIMER value in us." hexmask.long.tbyte 0x0 0.--19. 1. "RESERVED_0_19,Reserved" line.long 0x4 "LLUCTL,Link User Control Register - Link Layer User Control Register for enabling Link/PHY-specific options. - This register is common for all SS ports." bitfld.long 0x4 30.--31. "RESERVED_30_31,Reserved" "0,1,2,3" bitfld.long 0x4 29. "SUPPORT_P4_PG,PHY P4 Power gate mode (PG) is enabled. Set this bit if the PHY supports PG mode in P4. This bit is used only for Synopsys PHY." "0,1" bitfld.long 0x4 28. "SUPPORT_P4,Support PHY P3.CPM and P4 Power States. When this bit is set the controller puts the PHY in P3.CPM or P4 in certain states. This bit is used only for Synopsys PHY." "0,1" newline hexmask.long.byte 0x4 24.--27. 1. "RESERVED_24_27,Reserved" bitfld.long 0x4 23. "DISRXDET_LTSSM_TIMER_OVRRD,DisRxDet_LTSSM_Timer_Ovrrd. When DisRxDetU3RxDet is asserted in Polling or U1 the timeout expires immediately." "0,1" hexmask.long.word 0x4 13.--22. 1. "RESERVED_13_22,Reserved" newline bitfld.long 0x4 12. "U2P3CPMOK,P3CPM OK for U2/SSInactive (U2P3CPMok) - 0: During link state U2/SS.Inactive put PHY in P2 (Default) - 1: During link state U2/SS.Inactive put PHY in P3CPM. Note: For a port if both GUCTL1[25]=1 and LUCTL[12]=1 LUCTL[12]=1 takes priority." "During link state U2/SS,During link state U2/SS" bitfld.long 0x4 11. "EN_RESET_PIPE_AFTER_PHY_MUX,en_reset_pipe_after_phy_mux. The controller issues USB 3.0 PHY reset after DisRxDetU3RxDet is de-asserted." "0,1" bitfld.long 0x4 8.--10. "RESERVED_8_10,Reserved" "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 7. "MASK_PIPE_RESET,Mask pipe reset. If this bit is set controller blocks pipe_reset_n from going to the PHY when DisRxDetU3RxDet=1." "0,1" bitfld.long 0x4 6. "RESERVED_6,Reserved" "0,1" bitfld.long 0x4 5. "NO_UX_EXIT_P0_TRANS,no_ux_exit_p0_trans. Link LTSSM detects Ux_exit LFPS when P0 transition is on-going by default. If this bit is set Link LTSSM may miss Ux_exit LFPS when P0 transition is happening." "0,1" newline hexmask.long.byte 0x4 0.--4. 1. "RESERVED_0_4,Reserved" line.long 0x8 "LPTMDPDELAY,Link Datapath Delay Register - Link Layer Timer Register for P3CPM/P4 Residency. - This register is common for all SS ports." hexmask.long.word 0x8 22.--31. 1. "RESERVED_22_31,Reserved" hexmask.long.word 0x8 10.--21. 1. "P3CPMP4_RESIDENCY,p3cpmp4 residency timer value. Minimum number of suspend_clk periods that the controller needs to stay in P3.CPM or P4 before exiting P3.CPM or P4. This field is used only for Synopsys PHY." hexmask.long.word 0x8 0.--9. 1. "RESERVED_0_9,Reserved" tree.end tree "DWC_usb3_block_debug (USB 3.0 Debug Register Block)" group.long (0x0+0x55296)++0x3 line.long 0x0 "U3RHBDBG,U3 Root Hub Debug Register" hexmask.long 0x0 4.--31. 1. "RESERVED_1,Reserved_1" bitfld.long 0x0 3. "TPCFG_TOUT_CTRL,tpcfg_tout_ctrl This bit controls the USB 3.0 port configuration timeout duration. - 1: The port configuration timeout counter resets when the link is not in U0. - 0: The port configuration timeout counter does not reset if the link.." "The port configuration timeout counter does not..,The port configuration timeout counter resets.." rbitfld.long 0x0 0.--2. "RESERVED_0_2,Reserved_0_2" "0,1,2,3,4,5,6,7" tree.end tree "DWC_usb3_block_eXtensible_Host_Cntrl_Cap_Regs (USB 3.0 eXtensible Host Controller Capability Register Block)" rgroup.long (0x0+0x55296)++0x1F line.long 0x0 "CAPLENGTH,Capability Registers Length Host Controller Operational Registers = Base address + CAPLENGTH where CAPLENGTH is `DWC_USB3_HOST_CAP_REG_LEN whose default value is 20h." hexmask.long.word 0x0 16.--31. 1. "HCIVERSION,HC Interface Version Number (HCIVERSION)" hexmask.long.byte 0x0 8.--15. 1. "RESERVED_15_8,Reserved" hexmask.long.byte 0x0 0.--7. 1. "CAPLENGTH,Capability Registers Length (CAPLENGTH)" line.long 0x4 "HCSPARAMS1,Structural Parameters 1 Register For register definitions. refer to the xHCI specification." hexmask.long.byte 0x4 24.--31. 1. "MAXPORTS,Number of Ports (MaxPorts) - Number of ports implemented is defined by the parameter (`DWC_USB3_HOST_NUM_U2_ROOT_PORTS + `DWC_USB3_HOST_NUM_U3_ROOT_PORTS) - Number of ports enabled is controlled by the controller input signals.." hexmask.long.byte 0x4 19.--23. 1. "RESERVED_23_19,Reserved" hexmask.long.word 0x4 8.--18. 1. "MAXINTRS,Number of Interrupters (MaxIntrs) Defined by the configurable parameter `DWC_USB3_HOST_NUM_INTERRUPTER_SUPT" hexmask.long.byte 0x4 0.--7. 1. "MAXSLOTS,Number of device slots (MaxSlots) Defined by configurable parameter `DWC_USB3_NUM_DEVICE_SUPT" line.long 0x8 "HCSPARAMS2,Structural Parameters 2 Register For register definitions. refer to the xHCI specification." hexmask.long.byte 0x8 27.--31. 1. "MAXSCRATCHPADBUFS,Max Scratchpad Bufs Lo The value is calculated based on chosen configuration parameter values. Possible values are 1-4." bitfld.long 0x8 26. "SPR,Scratchpad Restore (SPR)" "0,1" hexmask.long.byte 0x8 21.--25. 1. "MAXSCRATCHPADBUFS_HI,Max Scratchpad Bufs HI The controller automatically updates this field." hexmask.long.word 0x8 8.--20. 1. "RESERVED_20_8,Reserved" newline hexmask.long.byte 0x8 4.--7. 1. "ERSTMAX,Event Ring Segment Table Max (ERST Max)" hexmask.long.byte 0x8 0.--3. 1. "IST,Isochronous Scheduling Threshold (IST)" line.long 0xC "HCSPARAMS3,Structural Parameters 3 Register For register definitions. refer to the xHCI specification." hexmask.long.word 0xC 16.--31. 1. "U2_DEVICE_EXIT_LAT,U2 Device Exit Latency" hexmask.long.byte 0xC 8.--15. 1. "RESERVED_15_8,Reserved" hexmask.long.byte 0xC 0.--7. 1. "U1_DEVICE_EXIT_LAT,U1 Device Exit Latency" line.long 0x10 "HCCPARAMS1,Capability Parameters 1 Register For register definitions. refer to the xHCI specification." hexmask.long.word 0x10 16.--31. 1. "XECP,xHCI Extended Capabilities Pointer (xECP) Based on configuration controller automatically updates it. Refer to /src/DWC_usb3_params.v for details on DWC_USB3_HC_XECP." hexmask.long.byte 0x10 12.--15. 1. "MAXPSASIZE,Maximum Primary Stream Array Size (MaxPSASize) For a description of this standard USB register field see the eXtensible Host Controller Interface for Universal Serial Bus (USB) Specification 3.0." bitfld.long 0x10 11. "CFC,Contiguous Frame ID Capability (CFC)" "0,1" bitfld.long 0x10 10. "SEC,Stopped EDLTA Capability (SEC) For a description of this standard USB register field see the eXtensible Host Controller Interface for Universal Serial Bus (USB) Specification 3.0." "0,1" newline bitfld.long 0x10 9. "SPC,Short Packet Capability (SPC) For a description of this standard USB register field see the eXtensible Host Controller Interface for Universal Serial Bus (USB) Specification 3.0." "0,1" bitfld.long 0x10 8. "PAE,Parse All Event Data (PAE) For a description of this standard USB register field see the eXtensible Host Controller Interface for Universal Serial Bus (USB) Specification 3.0." "0,1" bitfld.long 0x10 7. "NSS,No Secondary SID Support (NSS) For a description of this standard USB register field see the eXtensible Host Controller Interface for Universal Serial Bus (USB) Specification 3.0." "0,1" bitfld.long 0x10 6. "LTC,Latency Tolerance Messaging Capability (LTC) For a description of this standard USB register field see the eXtensible Host Controller Interface for Universal Serial Bus (USB) Specification 3.0." "0,1" newline bitfld.long 0x10 5. "LHRC,Light HC Reset Capability For a description of this standard USB register field see the eXtensible Host Controller Interface for Universal Serial Bus (USB) Specification 3.0." "0,1" bitfld.long 0x10 4. "PIND,Port Indicators (PIND) For a description of this standard USB register field see the eXtensible Host Controller Interface for Universal Serial Bus (USB) Specification 3.0." "0,1" bitfld.long 0x10 3. "PPC,Port Power Control For a description of this standard USB register field see the eXtensible Host Controller Interface for Universal Serial Bus (USB) Specification 3.0." "0,1" bitfld.long 0x10 2. "CSZ,Context Size (CSZ) For a description of this standard USB register field see the eXtensible Host Controller Interface for Universal Serial Bus (USB) Specification 3.0." "0,1" newline bitfld.long 0x10 1. "BNC,BW Negotiation Capability (BNC) For a description of this standard USB register field see the eXtensible Host Controller Interface for Universal Serial Bus (USB) Specification 3.0." "0,1" bitfld.long 0x10 0. "AC64,64-bit Addressing Capability (AC64) For a description of this standard USB register field see the eXtensible Host Controller Interface for Universal Serial Bus (USB) Specification 3.0." "0,1" line.long 0x14 "DBOFF,Doorbell Offset Register For register definitions. refer to the xHCI specification." hexmask.long 0x14 2.--31. 1. "DOORBELL_ARRAY_OFFSET,Doorbell Array Offset - RO Based on configuration the controller automatically updates it. For a description of this standard USB register field see the eXtensible Host Controller Interface for Universal Serial Bus (USB).." bitfld.long 0x14 0.--1. "RESERVED_1_0,Reserved" "0,1,2,3" line.long 0x18 "RTSOFF,Runtime Register Space Offset Register" hexmask.long 0x18 5.--31. 1. "RUNTIME_REG_SPACE_OFFSET,Runtime Register Space Offset Based on configuration the controller automatically updates it. For a description of this standard USB register field see the eXtensible Host Controller Interface for Universal Serial Bus (USB).." hexmask.long.byte 0x18 0.--4. 1. "RESERVED_4_0,Reserved" line.long 0x1C "HCCPARAMS2,Host Controller Capability Parameters 2 For register definitions. refer to the xHCI specification." hexmask.long 0x1C 6.--31. 1. "RESERVED_31_6,Reserved" bitfld.long 0x1C 5. "CIC,Configuration Information Capability (CIC) For a description of this standard USB register field see the eXtensible Host Controller I nterface for Universal Serial Bus (USB) Specification 3.0." "0,1" bitfld.long 0x1C 4. "LEC,Large ESIT Payload Capability (LEC) For a description of this standard USB register field see the eXtensible Host Controller I nterface for Universal Serial Bus (USB) Specification 3.0." "0,1" bitfld.long 0x1C 3. "CTC,Compliance Transition Capability (CTC) For a description of this standard USB register field see the eXtensible Host Controller I nterface for Universal Serial Bus (USB) Specification 3.0." "0,1" newline bitfld.long 0x1C 2. "FSC,Force Save Context Capability (FSC) For a description of this standard USB register field see the eXtensible Host Controller I nterface for Universal Serial Bus (USB) Specification 3.0." "0,1" bitfld.long 0x1C 1. "CMC,Configure Endpoint Command Max Exit Latency Too Large Capability (CMC) For a description of this standard USB register field see the eXtensible Host Controller I nterface for Universal Serial Bus (USB) Specification 3.0." "0,1" bitfld.long 0x1C 0. "U3C,U3 Entry Capability (U3C) For a description of this standard USB register field see the eXtensible Host Controller I nterface for Universal Serial Bus (USB) Specification 3.0." "0,1" tree.end tree "DWC_usb3_block_Host_Cntrl_Oper_Regs (USB3 Host Cntrl Oper Regs Block)" group.long (0x0+0x32)++0x7 line.long 0x0 "USBCMD,USB Command Register For a description of this standard USB register field see the eXtensible Host Controller Interface for Universal Serial Bus (USB) Specification 3.0." hexmask.long.tbyte 0x0 14.--31. 1. "RESERVED_31_14,Reserved" bitfld.long 0x0 13. "CME,CEM Enable For a description of this standard USB register field see the eXtensible Host Controller Interface for Universal Serial Bus (USB) Specification 3.0." "0,1" rbitfld.long 0x0 12. "RESERVED_12,Reserved" "0,1" bitfld.long 0x0 11. "EU3S,EU3S For a description of this standard USB register field see the eXtensible Host Controller Interface for Universal Serial Bus (USB) Specification 3.0." "0,1" bitfld.long 0x0 10. "EWE,EWE For a description of this standard USB register field see the eXtensible Host Controller Interface for Universal Serial Bus (USB) Specification 3.0." "0,1" newline bitfld.long 0x0 9. "CRS,Controller Restore State This command is similar to the USBCMD.CRS bit in host mode and initiates the restore process. When software sets this bit to '1' the controller immediately sets DSTS.RSS to '1'. When the controller has finished the restore.." "0,1" bitfld.long 0x0 8. "CSS,Controller Save State This command is similar to the USBCMD.CSS bit in host mode and initiates the save process. When software sets this bit to '1' the controller immediately sets DSTS.SSS to '1'. When the controller has finished the save process.." "0,1" bitfld.long 0x0 7. "LHCRST,Light Host Controller Reset For a description of this standard USB register field see the eXtensible Host Controller Interface for Universal Serial Bus (USB) Specification 3.0. The following bits reset the internal logic of the host controller." "0,1" rbitfld.long 0x0 4.--6. "RESERVED_6_4,Reserved" "0,1,2,3,4,5,6,7" bitfld.long 0x0 3. "HSEE,HSEE For a description of this standard USB register field see the eXtensible Host Controller Interface for Universal Serial Bus (USB) Specification 3.0." "0,1" newline bitfld.long 0x0 2. "INTE,INTE For a description of this standard USB register field see the eXtensible Host Controller Interface for Universal Serial Bus (USB) Specification 3.0." "0,1" bitfld.long 0x0 1. "HCRST,HCRST The following bits reset the internal logic of the host controller. Under soft reset some CSR accesses may fail (Timeout). - HCRST - LHCRST Bit Bash register testing is not recommended." "0,1" bitfld.long 0x0 0. "R_S,R_S For a description of this standard USB register field see the eXtensible Host Controller Interface for Universal Serial Bus (USB) Specification 3.0. Due to side-effects this reguster field is not recommended for Bit-Bash testing." "0,1" line.long 0x4 "USBSTS,USB Status Register Bit Definitions For a description of this standard USB register field. see the eXtensible Host Controller Interface for Universal Serial Bus (USB) Specification 3.0." hexmask.long.tbyte 0x4 13.--31. 1. "RESERVED_31_13,Reserved" rbitfld.long 0x4 12. "HCE,Host Controller Error (HCE) - RO Default = 0. '0' = No internal xHC error conditions exist and '1' = Internal xHC error condition. This flag must be set to indicate that an internal error condition has been detected which requires software to reset.." "0,1" rbitfld.long 0x4 11. "CNR,Controller Not Ready (CNR) - RO Default = '1'. '0' = Ready and '1' = Not Ready. Software must not write to thes Doorbell or Operational register of the xHC other than the USBSTS register until CNR = '0'. This flag is set by the xHC after a Chip.." "0,1" bitfld.long 0x4 10. "SRE,Save/Restore Error This bit is currently not supported." "0,1" rbitfld.long 0x4 9. "RSS,Restore State Status This bit is similar to the USBSTS.RSS in host mode. When the controller has finished the restore process it completes the command by setting DSTS.RSS to '0'." "0,1" newline rbitfld.long 0x4 8. "SSS,Save State Status This bit is similar to the USBSTS.SSS in host mode. When the controller has finished the save process it completes the command by setting DSTS.SSS to '0'." "0,1" rbitfld.long 0x4 5.--7. "RESERVED_7_5,Reserved" "0,1,2,3,4,5,6,7" bitfld.long 0x4 4. "PCD,Reset Value for PCD" "0,1" bitfld.long 0x4 3. "EINT,Reset Value for EINT" "0,1" bitfld.long 0x4 2. "HSE,HSE For a description of this standard USB register field see the eXtensible Host Controller Interface for Universal Serial Bus (USB) Specification 3.0.." "0,1" newline rbitfld.long 0x4 1. "RESERVED_1,Reserved" "0,1" rbitfld.long 0x4 0. "HCH,HCH For a description of this standard USB register field see the eXtensible Host Controller Interface for Universal Serial Bus (USB) Specification 3.0." "0,1" rgroup.long (0x8+0x32)++0x3 line.long 0x0 "PAGESIZE,Page Size Register Bit Definitions Use this register to enable or disable the reporting of specific USB Device Notification Transaction Packets being received. A Notification Enable (Nx. where x = 0 to 15) flag is defined for each of the 16.." hexmask.long.word 0x0 16.--31. 1. "RESERVED_31_16,Reserved" hexmask.long.word 0x0 0.--15. 1. "PAGE_SIZE,PAGE_SIZE" group.long (0x14+0x32)++0xB line.long 0x0 "DNCTRL,Device Notification Register Bit Definitions For a description of this standard USB register field see the eXtensible Host Controller Interface for Universal Serial Bus (USB) Specification 3.0." hexmask.long.word 0x0 16.--31. 1. "RESERVED_31_16,Reserved" hexmask.long.word 0x0 0.--15. 1. "N0_N15,N0_N15 For a description of this standard USB register field see the eXtensible Host Controller Interface for Universal Serial Bus (USB) Specification 3.0." line.long 0x4 "CRCR_LO,CRCR_LO For a description of this standard USB register field. see the eXtensible Host Controller Interface for Universal Serial Bus (USB) Specification 3.0." hexmask.long 0x4 6.--31. 1. "CMD_RING_PNTR,CMD_RING_PNTR For a description of this standard USB register field see the eXtensible Host Controller Interface for Universal Serial Bus (USB) Specification 3.0." rbitfld.long 0x4 4.--5. "RESERVED_5_4,Reserved" "0,1,2,3" rbitfld.long 0x4 3. "CRR,CRR For a description of this standard USB register field see the eXtensible Host Controller Interface for Universal Serial Bus (USB) Specification 3.0." "0,1" bitfld.long 0x4 2. "CA,CA For a description of this standard USB register field see the eXtensible Host Controller Interface for Universal Serial Bus (USB) Specification 3.0." "0,1" bitfld.long 0x4 1. "CS,CS For a description of this standard USB register field see the eXtensible Host Controller Interface for Universal Serial Bus (USB) Specification 3.0." "0,1" newline bitfld.long 0x4 0. "RCS,RCS For a description of this standard USB register field see the eXtensible Host Controller Interface for Universal Serial Bus (USB) Specification 3.0." "0,1" line.long 0x8 "CRCR_HI,CRCR_HI" hexmask.long 0x8 0.--31. 1. "CMD_RING_PNTR,COMMAND_RING_POINTER Reading this field always returns '0'. For a description of this standard USB register field see the eXtensible Host Controller Interface for Universal Serial Bus (USB) Specification 3.0." group.long (0x30+0x32)++0xB line.long 0x0 "DCBAAP_LO,DCBAAP_LO" hexmask.long 0x0 6.--31. 1. "DEVICE_CONTEXT_BAAP,DEVICE_CONTEXT_BAAP For a description of this standard USB register field see the eXtensible Host Controller Interface for Universal Serial Bus (USB) Specification 3.0." hexmask.long.byte 0x0 0.--5. 1. "RESERVED_5_0,Reserved" line.long 0x4 "DCBAAP_HI,DCBAAP_HI For a description of this standard USB register field. see the eXtensible Host Controller Interface for Universal Serial Bus (USB) Specification 3.0." hexmask.long 0x4 0.--31. 1. "DEVICE_CONTEXT_BAAP,DEVICE_CONTEXT_BAAP" line.long 0x8 "CONFIG,Configure Register Bit Definitions This register is in the Aux Power well. It is only reset by platform hardware during a cold reset or in response to a Host Controller Reset (HCRST). The initial conditions of a port are described in section 4.19.." hexmask.long.tbyte 0x8 10.--31. 1. "RESERVED_31_10,Reserved" bitfld.long 0x8 9. "CIE,Configuration Information Enable For a description of this standard USB register field see the eXtensible Host Controller Interface for Universal Serial Bus (USB) Specification 3.0." "0,1" bitfld.long 0x8 8. "U3E,U3 Entry Enable For a description of this standard USB register field see the eXtensible Host Controller Interface for Universal Serial Bus (USB) Specification 3.0." "0,1" hexmask.long.byte 0x8 0.--7. 1. "MAXSLOTSEN,MAXSLOTSEN For a description of this standard USB register field see the eXtensible Host Controller Interface for Universal Serial Bus (USB) Specification 3.0." tree.end tree "DWC_usb3_block_Host_Cntrl_Port_Reg_Set (USB3 Host Cntrl Port Reg Set Block)" group.long (0x0+0x1056)++0x7 line.long 0x0 "PORTSC_20,Port Status and Control Register Bit Definitions The PORTSC Register Access fails (Timeout) if the UTMI/ULPI clock is not running or one of the following bits is asserted. - PR - ORC" rbitfld.long 0x0 31. "RESERVED_31,Reserved For a description of this standard USB register field see the eXtensible Host Controller Interface for Universal Serial Bus (USB) Specification 3.0. Programming this field with random data will cause side effect i.e. Register Access.." "0,1" rbitfld.long 0x0 30. "DR,Reset Value For a description of this standard USB register field see the eXtensible Host Controller Interface for Universal Serial Bus (USB) Specification 3.0." "0,1" rbitfld.long 0x0 28.--29. "RESERVED_29_28,Reserved" "0,1,2,3" bitfld.long 0x0 27. "WOE,WOE For a description of this standard USB register field see the eXtensible Host Controller Interface for Universal Serial Bus (USB) Specification 3.0." "0,1" newline bitfld.long 0x0 26. "WDE,WDE For a description of this standard USB register field see the eXtensible Host Controller Interface for Universal Serial Bus (USB) Specification 3.0." "0,1" bitfld.long 0x0 25. "WCE,WCE For a description of this standard USB register field see the eXtensible Host Controller Interface for Universal Serial Bus (USB) Specification 3.0." "0,1" rbitfld.long 0x0 24. "CAS,Cold Attach Status For a description of this standard USB register field see the eXtensible Host Controller Interface for Universal Serial Bus (USB) Specification 3.0." "0,1" rbitfld.long 0x0 23. "RESERVED_23,Reserved For a description of this standard USB register field see the eXtensible Host Controller Interface for Universal Serial Bus (USB) Specification 3.0." "0,1" newline bitfld.long 0x0 22. "PLC,PLC For a description of this standard USB register field see the eXtensible Host Controller Interface for Universal Serial Bus (USB) Specification 3.0." "0,1" bitfld.long 0x0 21. "PRC,PRC For a description of this standard USB register field see the eXtensible Host Controller Interface for Universal Serial Bus (USB) Specification 3.0. Programming this field with random data will cause side effect. Bit Bash register testing is not.." "0,1" bitfld.long 0x0 20. "OCC,OCC For a description of this standard USB register field see the eXtensible Host Controller Interface for Universal Serial Bus (USB) Specification 3.0." "0,1" bitfld.long 0x0 19. "RESERVED_19,WRC For a description of this standard USB register field see the eXtensible Host Controller Interface for Universal Serial Bus (USB) Specification 3.0." "0,1" newline bitfld.long 0x0 18. "PEC,PEC For a description of this standard USB register field see the eXtensible Host Controller Interface for Universal Serial Bus (USB) Specification 3.0." "0,1" bitfld.long 0x0 17. "CSC,CSC For a description of this standard USB register field see the eXtensible Host Controller Interface for Universal Serial Bus (USB) Specification 3.0." "0,1" bitfld.long 0x0 16. "LWS,LWS For a description of this standard USB register field see the eXtensible Host Controller Interface for Universal Serial Bus (USB) Specification 3.0." "0,1" bitfld.long 0x0 14.--15. "PIC,PIC For a description of this standard USB register field see the eXtensible Host Controller Interface for Universal Serial Bus (USB) Specification 3.0." "0,1,2,3" newline hexmask.long.byte 0x0 10.--13. 1. "PORTSPEED,PORTSPEED For a description of this standard USB register field see the eXtensible Host Controller Interface for Universal Serial Bus (USB) Specification 3.0." bitfld.long 0x0 9. "PP,PP For a description of this standard USB register field see the eXtensible Host Controller Interface for Universal Serial Bus (USB) Specification 3.0." "0,1" hexmask.long.byte 0x0 5.--8. 1. "PLS,PLS For a description of this standard USB register field see the eXtensible Host Controller Interface for Universal Serial Bus (USB) Specification 3.0." bitfld.long 0x0 4. "PR,PR set_register_field_attribute DWC_usb3_map/DWC_usb3_block_Host_Cntrl_Port_Reg_Set/PORTSC_20_REGS/PORTSC_20/PR VolatileMemory 1 Programming this field with random data will cause side effect. Bit Bash register testing is not recommended." "0,1" newline rbitfld.long 0x0 3. "OCA,OCA For a description of this standard USB register field see the eXtensible Host Controller Interface for Universal Serial Bus (USB) Specification 3.0." "0,1" rbitfld.long 0x0 2. "RESERVED_2,Reserved" "0,1" bitfld.long 0x0 1. "PED,PED For a description of this standard USB register field see the eXtensible Host Controller Interface for Universal Serial Bus (USB) Specification 3.0." "0,1" rbitfld.long 0x0 0. "CCS,CCS For a description of this standard USB register field see the eXtensible Host Controller Interface for Universal Serial Bus (USB) Specification 3.0." "0,1" line.long 0x4 "PORTPMSC_20,USB3 Port Power Management Status and Control Register Bit Definitions This register is in the Aux Power well. It is only reset by platform hardware during a cold reset or in response to a Host Controller Reset (HCRST). Programming this field.." hexmask.long.byte 0x4 28.--31. 1. "PRTTSTCTRL,Port Test Control For a description of this standard USB register field see the eXtensible Host Controller Interface for Universal Serial Bus (USB) Specification 3.0." hexmask.long.word 0x4 17.--27. 1. "RESERVED_27_17,Reserved" bitfld.long 0x4 16. "HLE,Port Test Control For a description of this standard USB register field see the eXtensible Host Controller Interface for Universal Serial Bus (USB) Specification 3.0." "0,1" hexmask.long.byte 0x4 8.--15. 1. "L1DSLOT,L1DSLOT For a description of this standard USB register field see the eXtensible Host Controller Interface for Universal Serial Bus (USB) Specification 3.0." newline hexmask.long.byte 0x4 4.--7. 1. "HIRD,Host Initiated Resume Duration (HIRD) - RW. Default = '0'. System software sets this field to indicate to the recipient device how long the xHC will drive resume if it (the xHC) initiates an exit from L1. The HIRD value is encoded as follows: Value.." bitfld.long 0x4 3. "RWE,RWE Port Test Control For a description of this standard USB register field see the eXtensible Host Controller Interface for Universal Serial Bus (USB) Specification 3.0." "0,1" rbitfld.long 0x4 0.--2. "L1S,L1 Status (L1S) - RO. Default = 0. This field is used by software to determine whether an L1-based suspend request (LMP transaction) was successful specifically: Value Meaning 0 Invalid - This field is ignored by software. - 1 Success - Port.." "?,based suspend request,?,?,?,?,?,?" rgroup.long (0x8+0x1056)++0x3 line.long 0x0 "PORTLI_20,Port Link Info Register Programming this field with random data will cause side effect i.e. Register Access will fail (Timeout) if the pipe clock is not running or reset is asserted . Bit Bash register testing is not recommended." hexmask.long 0x0 0.--31. 1. "RESERVED_31_0,Reserved" group.long (0xC+0x1056)++0xB line.long 0x0 "PORTHLPMC_20,USB2 Port Hardware LPM Control Register Bit Definitions For a description of this standard USB register field. see the eXtensible Host Controller Interface for Universal Serial Bus (USB) Specification 3.0." hexmask.long.tbyte 0x0 14.--31. 1. "RESERVED_31_14,Reserved For a description of this standard USB register field see the eXtensible Host Controller Interface for Universal Serial Bus (USB) Specification 3.0." hexmask.long.byte 0x0 10.--13. 1. "HIRDD,PORTHLPMC_20 HIRDD" hexmask.long.byte 0x0 2.--9. 1. "L1_TIMEOUT,PORTHLPMC_20 L1_TIMEOUT. For a description of this standard USB register field see the eXtensible Host Controller Interface for Universal Serial Bus (USB) Specification 3.0." bitfld.long 0x0 0.--1. "HIRDM,Host Initiated Resume Duration Mode (HIRDM) - RWS. Default = 0h. Indicates which HIRD value must be used. The following are permissible values: Value Description 0 Initiate L1 using HIRD only on timeout. (default) 1 Initiate L1 using HIRDD on.." "0,1,2,3" line.long 0x4 "PORTSC_30,Port Status and Control Register Bit Definitions The PORTSC Register Access fails (Timeout) if the UTMI/ULPI clock is not running or one of the following bits is asserted. - PR - ORC - WPR" bitfld.long 0x4 31. "WPR,Reset Value For a description of this standard USB register field see the eXtensible Host Controller Interface for Universal Serial Bus (USB) Specification 3.0. Programming this field with random data will cause side effect i.e. Register Access will.." "0,1" rbitfld.long 0x4 30. "DR,Reset Value For a description of this standard USB register field see the eXtensible Host Controller Interface for Universal Serial Bus (USB) Specification 3.0." "0,1" rbitfld.long 0x4 28.--29. "RESERVED_29_28,Reserved" "0,1,2,3" bitfld.long 0x4 27. "WOE,WOE For a description of this standard USB register field see the eXtensible Host Controller Interface for Universal Serial Bus (USB) Specification 3.0." "0,1" newline bitfld.long 0x4 26. "WDE,WDE For a description of this standard USB register field see the eXtensible Host Controller Interface for Universal Serial Bus (USB) Specification 3.0." "0,1" bitfld.long 0x4 25. "WCE,WCE For a description of this standard USB register field see the eXtensible Host Controller Interface for Universal Serial Bus (USB) Specification 3.0." "0,1" rbitfld.long 0x4 24. "CAS,Cold Attach Status For a description of this standard USB register field see the eXtensible Host Controller Interface for Universal Serial Bus (USB) Specification 3.0." "0,1" bitfld.long 0x4 23. "CEC,CEC For a description of this standard USB register field see the eXtensible Host Controller Interface for Universal Serial Bus (USB) Specification 3.0." "0,1" newline bitfld.long 0x4 22. "PLC,PLC For a description of this standard USB register field see the eXtensible Host Controller Interface for Universal Serial Bus (USB) Specification 3.0." "0,1" bitfld.long 0x4 21. "PRC,PRC For a description of this standard USB register field see the eXtensible Host Controller Interface for Universal Serial Bus (USB) Specification 3.0. Programming this field with random data will cause side effect. Bit Bash register testing is not.." "0,1" bitfld.long 0x4 20. "OCC,OCC For a description of this standard USB register field see the eXtensible Host Controller Interface for Universal Serial Bus (USB) Specification 3.0." "0,1" bitfld.long 0x4 19. "WRC,WRC For a description of this standard USB register field see the eXtensible Host Controller Interface for Universal Serial Bus (USB) Specification 3.0." "0,1" newline bitfld.long 0x4 18. "PEC,PEC For a description of this standard USB register field see the eXtensible Host Controller Interface for Universal Serial Bus (USB) Specification 3.0." "0,1" bitfld.long 0x4 17. "CSC,CSC For a description of this standard USB register field see the eXtensible Host Controller Interface for Universal Serial Bus (USB) Specification 3.0." "0,1" bitfld.long 0x4 16. "LWS,LWS For a description of this standard USB register field see the eXtensible Host Controller Interface for Universal Serial Bus (USB) Specification 3.0." "0,1" bitfld.long 0x4 14.--15. "PIC,PIC For a description of this standard USB register field see the eXtensible Host Controller Interface for Universal Serial Bus (USB) Specification 3.0." "0,1,2,3" newline hexmask.long.byte 0x4 10.--13. 1. "PORTSPEED,PORTSPEED For a description of this standard USB register field see the eXtensible Host Controller Interface for Universal Serial Bus (USB) Specification 3.0." bitfld.long 0x4 9. "PP,PP For a description of this standard USB register field see the eXtensible Host Controller Interface for Universal Serial Bus (USB) Specification 3.0." "0,1" hexmask.long.byte 0x4 5.--8. 1. "PLS,PLS For a description of this standard USB register field see the eXtensible Host Controller Interface for Universal Serial Bus (USB) Specification 3.0." bitfld.long 0x4 4. "PR,PR set_register_field_attribute DWC_usb3_map/DWC_usb3_block_Host_Cntrl_Port_Reg_Set/PORTSC_30_REGS/PORTSC_30/PR VolatileMemory 1 Programming this field with random data will cause side effect. Bit Bash register testing is not recommended." "0,1" newline rbitfld.long 0x4 3. "OCA,OCA For a description of this standard USB register field see the eXtensible Host Controller Interface for Universal Serial Bus (USB) Specification 3.0." "0,1" rbitfld.long 0x4 2. "RESERVED_2,Reserved" "0,1" bitfld.long 0x4 1. "PED,PED For a description of this standard USB register field see the eXtensible Host Controller Interface for Universal Serial Bus (USB) Specification 3.0." "0,1" rbitfld.long 0x4 0. "CCS,CCS For a description of this standard USB register field see the eXtensible Host Controller Interface for Universal Serial Bus (USB) Specification 3.0." "0,1" line.long 0x8 "PORTPMSC_30,USB3 Port Power Management Status and Control Register Bit Definitions This register is in the Aux Power well. It is only reset by platform hardware during a cold reset or in response to a Host Controller Reset (HCRST). Programming this field.." hexmask.long.word 0x8 17.--31. 1. "RESERVED_31_17,Reserved" bitfld.long 0x8 16. "FLA,FLA For a description of this standard USB register field see the eXtensible Host Controller Interface for Universal Serial Bus (USB) Specification 3.0." "0,1" hexmask.long.byte 0x8 8.--15. 1. "U2_TIMEOUT,U2_TIMEOUT For a description of this standard USB register field see the eXtensible Host Controller Interface for Universal Serial Bus (USB) Specification 3.0." hexmask.long.byte 0x8 0.--7. 1. "U1_TIMEOUT,U1_TIMEOUT For a description of this standard USB register field see the eXtensible Host Controller Interface for Universal Serial Bus (USB) Specification 3.0." rgroup.long (0x18+0x1056)++0x7 line.long 0x0 "PORTLI_30,Port Link Info Register Programming this field with random data will cause side effect i.e. Register Access will fail (Timeout) if the pipe clock is not running or reset is asserted . Bit Bash register testing is not recommended." hexmask.long.word 0x0 16.--31. 1. "RESERVED_31_16,Reserved" hexmask.long.word 0x0 0.--15. 1. "LINK_ERROR_COUNT,LINK_ERROR_COUNT For a description of this standard USB register field see the eXtensible Host Controller Interface for Universal Serial Bus (USB) Specification 3.0." line.long 0x4 "PORTHLPMC_30,USB2 Port Hardware LPM Control Register Bit Definitions For a description of this standard USB register field. see the eXtensible Host Controller Interface for Universal Serial Bus (USB) Specification 3.0." hexmask.long 0x4 0.--31. 1. "RESERVED_31_0,Reserved For a description of this standard USB register field see the eXtensible Host Controller Interface for Universal Serial Bus (USB) Specification 3.0." tree.end tree "DWC_usb3_block_Host_Cntrl_Runtime_Regs (USB3 Host Cntrl Runtime Regs Block)" rgroup.long (0x0+0x1088)++0x7 line.long 0x0 "MFINDEX,Microframe Index Register Bit Definitions For a description of this standard USB register field. see the eXtensible Host Controller Interface for Universal Serial Bus (USB) Specification 3.0." hexmask.long.tbyte 0x0 14.--31. 1. "RESERVED_31_14,Reserved" hexmask.long.word 0x0 0.--13. 1. "MICROFRAME_INDEX,MICROFRAME_INDEX For a description of this standard USB register field see the eXtensible Host Controller Interface for Universal Serial Bus (USB) Specification 3.0." line.long 0x4 "RSVDZ,RsvdZ For a description of this standard USB register field. see the eXtensible Host Controller Interface for Universal Serial Bus (USB) Specification 3.0." hexmask.long 0x4 0.--31. 1. "RESERVED_31_0,Reserved" tree.end tree "DWC_usb3_block_Interrupter_Regs (USB3 Interrupter Regs Block)" group.long (0x0+0x1120)++0xB line.long 0x0 "IMAN,Interrupter Management Register Bit Definitions For a description of this standard USB register field. see the eXtensible Host Controller Interface for Universal Serial Bus (USB) Specification 3.0." hexmask.long 0x0 2.--31. 1. "RESERVED_31_2,Reserved" bitfld.long 0x0 1. "IE,IE For a description of this standard USB register field see the eXtensible Host Controller Interface for Universal Serial Bus (USB) Specification 3.0." "0,1" bitfld.long 0x0 0. "IP,IP Interrupt Pending For a description of this standard USB register field see the eXtensible Host Controller Interface for Universal Serial Bus (USB) Specification 3.0." "0,1" line.long 0x4 "IMOD,Interrupter Moderation Register The software may use this register to pace (or even out) the delivery of interrupts to the host CPU. This register provides a guaranteed inter-interrupt delay between interrupts asserted by the xHC. regardless of USB.." hexmask.long.word 0x4 16.--31. 1. "IMODC,Interrupt Moderation Counter (IMODC) - RW. Default = undefined. Down counter. Loaded with the IMODI value whenever IP is cleared to '0' counts down to '0' and stops. The associated interrupt is signaled whenever this counter is '0' the Event.." hexmask.long.word 0x4 0.--15. 1. "IMODI,Interrupt Moderation Interval (IMODI) - RW. Default = '4000' (~1ms). Minimum inter-interrupt interval. The interval is specified in 250ns increments. A value of '0' disables interrupt throttling logic and interrupts is generated immediately if IP =.." line.long 0x8 "ERSTSZ,Event Ring Segment Table Size Register Bit Definitions For a description of this standard USB register field. see the eXtensible Host Controller Interface for Universal Serial Bus (USB) Specification 3.0." hexmask.long.word 0x8 16.--31. 1. "RESERVED_31_16,Reserved" hexmask.long.word 0x8 0.--15. 1. "ERS_TABLE_SIZE,ERS_TABLE_SIZE For a description of this standard USB register field see the eXtensible Host Controller Interface for Universal Serial Bus (USB) Specification 3.0." rgroup.long (0xC+0x1120)++0x3 line.long 0x0 "RSVDP,RsvdP" hexmask.long 0x0 0.--31. 1. "RESERVED_31_0,Reserved" group.long (0x10+0x1120)++0xF line.long 0x0 "ERSTBA_LO,ERSTBA_LO" hexmask.long 0x0 6.--31. 1. "ERS_TABLE_BAR,ERS_TABLE_BAR" hexmask.long.byte 0x0 0.--5. 1. "RESERVED_5_0,Reserved" line.long 0x4 "ERSTBA_HI,ERSTBA_HI" hexmask.long 0x4 0.--31. 1. "ERS_TABLE_BAR,ERS_TABLE_BAR For a description of this standard USB register field see the eXtensible Host Controller Interface for Universal Serial Bus (USB) Specification 3.0." line.long 0x8 "ERDP_LO,ERDP_LO For a description of this standard USB register field. see the eXtensible Host Controller Interface for Universal Serial Bus (USB) Specification 3.0." hexmask.long 0x8 4.--31. 1. "ERD_PNTR,ERD_PNTR For a description of this standard USB register field see the eXtensible Host Controller Interface for Universal Serial Bus (USB) Specification 3.0." bitfld.long 0x8 3. "EHB,HC OS Owned SemaphoreERS_TABLE_SIZEHC BIOS Owned Semaphore USB SMI Enable SMI on Host System Error Enable - SMI on OS Ownership Enable - SMI on PCI Command Enable - SMI on BAR Enable - SMI on Event Interrupt - SMI on Host System Error - SMI on OS.." "0,1" bitfld.long 0x8 0.--2. "DESI,DESI - For a description of this standard USB register field see the eXtensible Host Controller Interface for Universal Serial Bus (USB) Specification 3.0." "0,1,2,3,4,5,6,7" line.long 0xC "ERDP_HI,ERDP_HI" hexmask.long 0xC 0.--31. 1. "ERD_PNTR,ERD_PNTR For a description of this standard USB register field see the eXtensible Host Controller Interface for Universal Serial Bus (USB) Specification 3.0." tree.end tree "DWC_usb3_block_Doorbell_Register (USB3 Doorbell Reg Block)" group.long (0x0+0x1152)++0x3 line.long 0x0 "DB,Doorbell Register Bit Field Definitions For a description of this standard USB register field. see the eXtensible Host Controller Interface for Universal Serial Bus (USB) Specification 3.0. Programming this field with random data will cause side.." hexmask.long.word 0x0 16.--31. 1. "DB_STREAM_ID,DB_STREAM_ID For a description of this standard USB register field see the eXtensible Host Controller Interface for Universal Serial Bus (USB) Specification 3.0." hexmask.long.byte 0x0 8.--15. 1. "RESERVED_15_8,Reserved" hexmask.long.byte 0x0 0.--7. 1. "DB_TARGET,DB_TARGET For a description of this standard USB register field see the eXtensible Host Controller Interface for Universal Serial Bus (USB) Specification 3.0." tree.end tree "DWC_usb3_block_HC_Extended_Capability_Register (USB3 HC Extended Capability Register Block)" group.long (0x0+0x2176)++0x7 line.long 0x0 "USBLEGSUP,USBLEGSUP" hexmask.long.byte 0x0 25.--31. 1. "RESERVED_31_25,Reserved" bitfld.long 0x0 24. "HC_OS_OWNED,HC_OS_OWNED SEMAPHORE For a description of this standard USB register field see the eXtensible Host Controller Interface for Universal Serial Bus (USB) Specification 3.0." "0,1" hexmask.long.byte 0x0 17.--23. 1. "RESERVED_23_17,Reserved" bitfld.long 0x0 16. "HC_BIOS_OWNED,HC_BIOS_OWNED SEMAPHORE For a description of this standard USB register field see the eXtensible Host Controller Interface for Universal Serial Bus (USB) Specification 3.0." "0,1" newline hexmask.long.byte 0x0 8.--15. 1. "NEXT_CAPABILITY_POINTER,NEXT_CAPABILITY_POINTER For a description of this standard USB register field see the eXtensible Host Controller Interface for Universal Serial Bus (USB) Specification 3.0." hexmask.long.byte 0x0 0.--7. 1. "CAPABILITY_ID,CAPABILITY_ID set_register_field_attribute DWC_usb3_map/DWC_usb3_block_HC_Extended_Capability_Register/USBLEGSUP/CAPABILITY_ID RegisterResetValue 0x1 For a description of this standard USB register field see the eXtensible Host Controller.." line.long 0x4 "USBLEGCTLSTS,USBLEGCTLSTS" bitfld.long 0x4 31. "SMI_ON_BAR,SMI_ON_BAR For a description of this standard USB register field see the eXtensible Host Controller Interface for Universal Serial Bus (USB) Specification 3.0." "0,1" bitfld.long 0x4 30. "SMI_ON_PCI,SMI_ON_PCI COMMAND For a description of this standard USB register field see the eXtensible Host Controller Interface for Universal Serial Bus (USB) Specification 3.0." "0,1" bitfld.long 0x4 29. "SMI_ON_OS,SMI_ON_OS OWNERSHIP CHANGE For a description of this standard USB register field see the eXtensible Host Controller Interface for Universal Serial Bus (USB) Specification 3.0." "0,1" hexmask.long.byte 0x4 21.--28. 1. "RESERVED_28_21,Reserved" newline rbitfld.long 0x4 20. "SMI_ON_HOST,SMI_ON_HOST SYSTEM ERROR For a description of this standard USB register field see the eXtensible Host Controller Interface for Universal Serial Bus (USB) Specification 3.0." "0,1" rbitfld.long 0x4 17.--19. "RESERVED_19_17,Reserved" "0,1,2,3,4,5,6,7" rbitfld.long 0x4 16. "SMI_ON_EVENT,SMI_ON_EVENT INTERRUPT For a description of this standard USB register field see the eXtensible Host Controller Interface for Universal Serial Bus (USB) Specification 3.0." "0,1" bitfld.long 0x4 15. "SMI_ON_BAR_E,SMI_ON_BAR ENABLE For a description of this standard USB register field see the eXtensible Host Controller Interface for Universal Serial Bus (USB) Specification 3.0." "0,1" newline bitfld.long 0x4 14. "SMI_ON_PCI_E,SMI_ON_PCI COMMAND ENABLE For a description of this standard USB register field see the eXtensible Host Controller Interface for Universal Serial Bus (USB) Specification 3.0." "0,1" bitfld.long 0x4 13. "SMI_ON_OS_E,SMI_ON_OS OWNERSHIP ENABLE For a description of this standard USB register field see the eXtensible Host Controller Interface for Universal Serial Bus (USB) Specification 3.0." "0,1" hexmask.long.byte 0x4 5.--12. 1. "RESERVED_12_5,Reserved" bitfld.long 0x4 4. "SMI_ON_HOST_E,SMI_ON_HOST SYSTEM ERROR ENABLE For a description of this standard USB register field see the eXtensible Host Controller Interface for Universal Serial Bus (USB) Specification 3.0." "0,1" newline rbitfld.long 0x4 1.--3. "RESERVED_3_1,Reserved" "0,1,2,3,4,5,6,7" bitfld.long 0x4 0. "USB_SMI_ENABLE,USB_SMI_ENABLE For a description of this standard USB register field see the eXtensible Host Controller Interface for Universal Serial Bus (USB) Specification 3.0." "0,1" tree.end tree "DWC_usb3_block_xHCI_Supt_USB20_Prt_Cap (USB3 xHCI Supported Protocol Capability (USB 2.0) Block)" rgroup.long (0x0+0x2192)++0xF line.long 0x0 "SUPTPRT2_DW0,SUPTPRT2_DW0" hexmask.long.byte 0x0 24.--31. 1. "MAJOR_REVISION,MAJOR_REVISION" hexmask.long.byte 0x0 16.--23. 1. "MINOR_REVISION,MINOR_REVISION" hexmask.long.byte 0x0 8.--15. 1. "NEXT_CAPABILITY_POINTER,NEXT_CAPABILITY_POINTER" newline hexmask.long.byte 0x0 0.--7. 1. "CAPABILITY_ID,CAPABILITY_ID For a description of this standard USB register field see the eXtensible Host Controller Interface for Universal Serial Bus (USB) Specification 3.0." line.long 0x4 "SUPTPRT2_DW1,Register SUPTPRT2_DW1" hexmask.long 0x4 0.--31. 1. "NAME_STRING,NAME_STRING For a description of this standard USB register field see the eXtensible Host Controller Interface for Universal Serial Bus (USB) Specification 3.0." line.long 0x8 "SUPTPRT2_DW2,xHCI Supported Protocol Capability_ Data Word 2 For a description of other register fields. see section 7.2 of the eXtensible Host Controller Interface for Universal Serial Bus (USB) Specification 3.0." hexmask.long.byte 0x8 28.--31. 1. "PSIC,PSIC" bitfld.long 0x8 25.--27. "MHD,Hub Depth For a description of this standard USB register field see the eXtensible Host Controller Interface for Universal Serial Bus (USB) Specification 3.0." "0,1,2,3,4,5,6,7" hexmask.long.byte 0x8 21.--24. 1. "RESERVED_24_21,Reserved" newline bitfld.long 0x8 20. "BLC,BESL LPM Capability. When this bit is set to: - 1: The ports described by this xHCI Supported Protocol Capability applies BESL timing to the BESL and BESLD fields of the PORTPMSC and PORTHLPMC registers. - 0: The ports described by this xHCI.." "The ports described by this xHCI Supported..,The ports described by this xHCI Supported.." bitfld.long 0x8 19. "HLC,Compatible Port Offset. Compatible Port Count Refer to Table 7-3 in the Databook." "0,1" bitfld.long 0x8 18. "IHI,IHI" "0,1" newline bitfld.long 0x8 17. "HSO,HSO" "0,1" hexmask.long.byte 0x8 8.--15. 1. "COMPATIBLE_PORT_COUNT,COMPATIBLE_PORT_COUNT For a description of this standard USB register field see the eXtensible Host Controller Interface for Universal Serial Bus (USB) Specification 3.0." hexmask.long.byte 0x8 0.--7. 1. "COMPATIBLE_PORT_OFFSET,COMPATIBLE_PORT_OFFSET For a description of this standard USB register field see the eXtensible Host Controller Interface for Universal Serial Bus (USB) Specification 3.0." line.long 0xC "SUPTPRT2_DW3,Register SUPTPRT2_DW3" hexmask.long 0xC 5.--31. 1. "RESERVED_31_5,Reserved" hexmask.long.byte 0xC 0.--4. 1. "PROTCL_SLT_TY,Protocol Slot Type" tree.end tree "DWC_usb3_block_xHCI_Supt_USB30_Prt_Cap (USB3 xHCI Supported Protocol Capability (USB 3.0) Block)" rgroup.long (0x0+0x2208)++0xF line.long 0x0 "SUPTPRT3_DW0,Register SUPTPRT3_DW0" hexmask.long.byte 0x0 24.--31. 1. "MAJOR_REVISION,MAJOR_REVISION For a description of this standard USB register field see the eXtensible Host Controller Interface for Universal Serial Bus (USB) Specification 3.0." hexmask.long.byte 0x0 16.--23. 1. "MINOR_REVISION,MINOR_REVISION For a description of this standard USB register field see the eXtensible Host Controller Interface for Universal Serial Bus (USB) Specification 3.0." hexmask.long.byte 0x0 8.--15. 1. "NEXT_CAPABILITY_POINTER,NEXT_CAPABILITY_POINTER For a description of this standard USB register field see the eXtensible Host Controller Interface for Universal Serial Bus (USB) Specification 3.0." hexmask.long.byte 0x0 0.--7. 1. "CAPABILITY_ID,CAPABILITY_ID For a description of this standard USB register field see the eXtensible Host Controller Interface for Universal Serial Bus (USB) Specification 3.0." line.long 0x4 "SUPTPRT3_DW1,Register SUPTPRT3_DW1" hexmask.long 0x4 0.--31. 1. "NAME_STRING,NAME_STRING For a description of this standard USB register field see the eXtensible Host Controller Interface for Universal Serial Bus (USB) Specification 3.0." line.long 0x8 "SUPTPRT3_DW2,SUPTPRT3_DW2 For a description of this standard USB register field. see the eXtensible Host Controller Interface for Universal Serial Bus (USB) Specification 3.0." hexmask.long.byte 0x8 28.--31. 1. "PSIC,PSIC" bitfld.long 0x8 25.--27. "MHD,Hub Depth For a description of this standard USB register field see the eXtensible Host Controller Interface for Universal Serial Bus (USB) Specification 3.0." "0,1,2,3,4,5,6,7" hexmask.long.byte 0x8 8.--15. 1. "COMPATIBLE_PORT_COUNT,COMPATIBLE_PORT_COUNT For a description of this standard USB register field see the eXtensible Host Controller Interface for Universal Serial Bus (USB) Specification 3.0." hexmask.long.byte 0x8 0.--7. 1. "COMPATIBLE_PORT_OFFSET,COMPATIBLE_PORT_OFFSET For a description of this standard USB register field see the eXtensible Host Controller Interface for Universal Serial Bus (USB) Specification 3.0." line.long 0xC "SUPTPRT3_DW3,SUPTPRT3_DW3" hexmask.long 0xC 5.--31. 1. "RESERVED_31_5,Reserved" hexmask.long.byte 0xC 0.--4. 1. "PROTCL_SLT_TY,Protocol Slot Type" tree.end tree "DWC_usb3_block_Debug_Capability_Structure (USB3 Debug Capability Structure Block)" rgroup.long (0x0+0x2224)++0x3 line.long 0x0 "DCID,DCID" hexmask.long.word 0x0 21.--31. 1. "RESERVED_31_21,Reserved" hexmask.long.byte 0x0 16.--20. 1. "DCERSTMAX,DCERSTMAX" hexmask.long.byte 0x0 8.--15. 1. "NEXT_CAPABILITY_POINTER,NEXT_CAPABILITY_POINTER" hexmask.long.byte 0x0 0.--7. 1. "CAPABILITY_ID,CAPABILITY_ID" group.long (0x4+0x2224)++0x7 line.long 0x0 "DCDB,Register DCDB" hexmask.long.word 0x0 16.--31. 1. "RESERVED_31_16,Reserved" hexmask.long.byte 0x0 8.--15. 1. "DBTARGET,DBTARGET" hexmask.long.byte 0x0 0.--7. 1. "RESERVED_7_0,Reserved" line.long 0x4 "DCERSTSZ,DCERSTSZ" hexmask.long.word 0x4 16.--31. 1. "RESERVED_31_16,Reserved" hexmask.long.word 0x4 0.--15. 1. "ERS_TABLE_SIZE,ERS_TABLE_SIZE" group.long (0x10+0x2224)++0x13 line.long 0x0 "DCERSTBA_LO,DCERSTBA_LO" hexmask.long 0x0 4.--31. 1. "ERS_TABLE_BAR,ERS_TABLE_BAR" hexmask.long.byte 0x0 0.--3. 1. "RESERVED_3_0,Reserved" line.long 0x4 "DCERSTBA_HI,Register DCERSTBA_HI" hexmask.long 0x4 0.--31. 1. "ERS_TABLE_BAR,ERS_TABLE_BAR" line.long 0x8 "DCERDP_LO,DCERDP_LO" hexmask.long 0x8 4.--31. 1. "DEQUEUE_POINTER,DEQUEUE_POINTER" rbitfld.long 0x8 3. "RESERVED_3,Reserved" "0,1" bitfld.long 0x8 0.--2. "DESI,DESI" "0,1,2,3,4,5,6,7" line.long 0xC "DCERDP_HI,DCERDP_HI" hexmask.long 0xC 0.--31. 1. "DEQUEUE_POINTER,DEQUEUE_POINTER" line.long 0x10 "DCCTRL,DCCTRL" bitfld.long 0x10 31. "DCE,DCE" "0,1" hexmask.long.byte 0x10 24.--30. 1. "DEVICE_ADDRESS,DEVICE_ADDRESS" hexmask.long.byte 0x10 16.--23. 1. "DEBUG_MAX_BURST_SIZE,DEBUG_PROTOCOL" hexmask.long.word 0x10 5.--15. 1. "RESERVED_15_5,Reserved" newline bitfld.long 0x10 4. "DRC,DRC" "0,1" bitfld.long 0x10 3. "HIT,HIT" "0,1" bitfld.long 0x10 2. "HOT,HOT" "0,1" bitfld.long 0x10 1. "LSE,LSE" "0,1" newline rbitfld.long 0x10 0. "DCR,DCR" "0,1" rgroup.long (0x24+0x2224)++0x3 line.long 0x0 "DCST,DCST" hexmask.long.byte 0x0 24.--31. 1. "DEBUG_PORT_NUMBER,DEBUG_PORT_NUMBER" hexmask.long.tbyte 0x0 2.--23. 1. "RESERVED_23_2,Reserved" bitfld.long 0x0 1. "SBR,SBR" "0,1" bitfld.long 0x0 0. "ER,ER" "0,1" group.long (0x28+0x2224)++0x3 line.long 0x0 "DCPORTSC,Register DCPORTSC" hexmask.long.byte 0x0 24.--31. 1. "RESERVED_31_24,Reserved" bitfld.long 0x0 23. "CEC,CEC" "0,1" bitfld.long 0x0 22. "PLC,PLC" "0,1" bitfld.long 0x0 21. "PRC,PRC" "0,1" newline rbitfld.long 0x0 18.--20. "RESERVED_20_18,Reserved" "0,1,2,3,4,5,6,7" bitfld.long 0x0 17. "CSC,CSC" "0,1" rbitfld.long 0x0 14.--16. "RESERVED_16_14,Reserved" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x0 10.--13. 1. "PORTSPEED,PORTSPEED" newline rbitfld.long 0x0 9. "RESERVED_9,Reserved" "0,1" hexmask.long.byte 0x0 5.--8. 1. "PLS,PLS" rbitfld.long 0x0 4. "PR,PR" "0,1" rbitfld.long 0x0 2.--3. "RESERVED_3_2,Reserved" "0,1,2,3" newline bitfld.long 0x0 1. "PED,PED" "0,1" rbitfld.long 0x0 0. "CCS,CCS" "0,1" group.long (0x30+0x2224)++0xF line.long 0x0 "DCCP_LO,DCCP_LO" hexmask.long 0x0 4.--31. 1. "DCCPR,DCCPR" hexmask.long.byte 0x0 0.--3. 1. "RESERVED_3_0,Reserved" line.long 0x4 "DCCP_HI,Register DCCP_HI" hexmask.long 0x4 0.--31. 1. "DCCPR,DCCPR" line.long 0x8 "DCDDI1,Register DCDDI1" hexmask.long.word 0x8 16.--31. 1. "VENDORID,VENDORID" hexmask.long.byte 0x8 8.--15. 1. "RESERVED_15_8,Reserved" hexmask.long.byte 0x8 0.--7. 1. "DBCPROTOCOL,DBCPROTOCOL" line.long 0xC "DCDDI2,Register DCDDI2" hexmask.long.word 0xC 16.--31. 1. "DEVICEREV,DEVICEREV" hexmask.long.word 0xC 0.--15. 1. "PRODUCTID,PRODUCTID" tree.end tree.end tree "USB1_NCR" base ad:0x3122D000 group.long 0x0++0x3 line.long 0x0 "INTEN,INTEN" bitfld.long 0x0 15. "INTEN_RSVD8,INTEN_RSVD8" "0,1" newline bitfld.long 0x0 14. "INTEN_RSVD7,INTEN_RSVD7" "0,1" bitfld.long 0x0 13. "INTEN_RSVD6,INTEN_RSVD6" "0,1" newline bitfld.long 0x0 12. "INTEN_RSVD5,INTEN_RSVD5" "0,1" bitfld.long 0x0 11. "INTEN_RSVD4,INTEN_RSVD4" "0,1" newline bitfld.long 0x0 10. "INTEN_RSVD3,INTEN_RSVD3" "0,1" bitfld.long 0x0 9. "INTEN_RSVD2,INTEN_RSVD2" "0,1" newline bitfld.long 0x0 8. "INTEN_RSVD1,INTEN_RSVD1" "0,1" bitfld.long 0x0 7. "INTEN_RSVD0,INTEN_RSVD0" "0,1" newline bitfld.long 0x0 6. "INTEN_WAKEUP,WAKEUP interrupt enalbe 1:enable 0:disable" "disable,enable" bitfld.long 0x0 5. "INTEN_HOST_LEGACY_SMI_INTERRUPT,HOST_LEGACY_SMI_INTERRUPT enable 1:enable 0:disable" "disable,enable" newline bitfld.long 0x0 4. "INTEN_PME_GENERATION,Power Management Event (PME) interrupt enable 1: enable 0:disable" "disable,enable" bitfld.long 0x0 3. "INTEN_BC_INTERRUPT,Battery Charger interrupt enable 1:enable 0:disable" "disable,enable" newline bitfld.long 0x0 2. "INTEN_CHGDET,Battery Charger Detect interrupt 1:enable 0:disable" "disable,enable" bitfld.long 0x0 1. "INTEN_HOST_SYSTEM_ERR,host_system_err interrupt enable. host_system_err can occur when the host controller encounters an 'Error' response in the AHB the AXI or the Native Master Bus. 1:enable 0:disable" "disable,enable" newline bitfld.long 0x0 0. "INTEN_CORE_INTERRUPT,USB CORE INTERRUPT enable 1:enable 0:disable" "disable,enable" group.long 0x10++0x7 line.long 0x0 "CTRL_0,CTRL_0" bitfld.long 0x0 29.--31. "DEBOUNCECTL,Enables Bus Filters for the following UTMI/ULPI signals and PIPE3PowerControl input signal from the PHY. utmiotg_vbusvalid utmisrp_bvalid pipe3_PowerPresent" "0,1,2,3,4,5,6,7" bitfld.long 0x0 28. "WAKEBYIDCHG,WAKEBYIDCHG" "0,1" newline bitfld.long 0x0 27. "WAKEBYVBUSCHG,WAKEBYVBUSCHG" "0,1" bitfld.long 0x0 26. "WAKEBYDPDMCHG,WAKEBYDPDMCHG" "0,1" newline bitfld.long 0x0 25. "WAKEBYREMOTEWAKE,WAKEBYREMOTEWAKE" "0,1" bitfld.long 0x0 24. "WAKEBYHSDSCNNT,WAKEBYHSDSCNNT" "0,1" newline bitfld.long 0x0 23. "WAKEBYHSCNNT,WAKEBYHSCNNT" "0,1" bitfld.long 0x0 22. "WAKEBYOC,WAKEBYOC" "0,1" newline bitfld.long 0x0 21. "XHC_BME,This signal is used to disable the bus mastering capability of the xHC. In a PCI system it comes from the Bus Master Enable (BME) bit of the Device Control Register in the PCI Configuration register space. 1'b0: Bus mastering capability is.." "Bus mastering capability is disabled,Bus mastering capability is enabled" hexmask.long.byte 0x0 17.--20. 1. "BUS_FILTER_BYPASS,Bus Filter Bypass. Disables the internal bus filters that are enabled by DWC_USB3_EN_BUS_FILTERS coreConsultant parameter. This static signal is present only when DWC_USB3_EN_BUS_FILTERS is 1. It is expected that this signal is set or.." newline hexmask.long.byte 0x0 11.--16. 1. "FLADJ_30MHZ_REG,HS Jitter Adjustment. Indicates the correction required to accommodate mac3 clock and utmi clock jitter to measure 125 's duration. With fladj_30mhz_reg tied to zero the high speed 125us micro-frame is counted for 123933ns. You must.." bitfld.long 0x0 10. "HOST_LEGACY_SMI_BAR_WR,PCI Base Address register (BAR) write: one clock pulse. The PCIe interface need to generate one clock pulse during PCIe Base Address register (BAR) write. Active State: High" "0,1" newline bitfld.long 0x0 9. "HOST_LEGACY_SMI_PCI_CMD_REG_WR,PCI command register write: one clock pulse. The PCIe interface needs to generate one clock pulse during PCIe command register write. Tie this low if you are not using Legacy support. Active State: High" "0,1" bitfld.long 0x0 8. "HOST_MSI_ENABLE,This enables the pulse type interrupt signal (one bus clock cycle) 'interrupt' port instead of level-sensitive interrupt. When interfacing to PCIe this allows you to easily map 'interrupt' to MSI in the PCIe controller. MSI can only be.." "0,1" newline bitfld.long 0x0 7. "HOST_PORT_POWER_CONTROL_PRESENT,This port defines the bit [3] of Capability Parameters (HCCPARAMS). Change the PPC value through the pin Port Power Control (PPC). This indicates whether the host controller implementation includes port power control..." "Indicates that the port does not have port power..,Indicates that the port has port power switches" bitfld.long 0x0 6. "DISRXDETU3RXDET,DisRxDetU3RxDet of USB 3.0 SS Ports This input signal requests the controller to stop issuing more PHY commands and release the PIPE ownership. The controller acknowledges this request by asserting the DisRxDetU3RxDet_ack signal. This.." "0,1" newline bitfld.long 0x0 5. "STARTRXDETU3RXDET,StartRxdetU3RxDet of USB 3.0 SS Ports This signal is the Start Receiver Detection in U3/Rx.Detect (StartRxdetU3RxDet). If DisRxDetU3RxDet is set and the link is in either U3 or Rx.Detect state the controller starts receiver detection.." "0,1" bitfld.long 0x0 4. "HOST_U3_PORT_DISABLE,USB 3.0 SS Port Disable control. 0: Port Enabled 1: Port Disabled This signal when '1' stops reporting connect/disconnect events the port and keeps the port in disabled state. This could be used for security reasons where.." "Port Enabled,Port Disabled" newline bitfld.long 0x0 3. "HOST_U2_PORT_DISABLE,USB 2.0 Port Disable control. 0: Port Enabled 1: Port Disabled When '1' this signal stops reporting connect/disconnect events the port and keeps the port in disabled state. This could be used for security reasons where.." "Port Enabled,Port Disabled When '1'" bitfld.long 0x0 1.--2. "HUB_PORT_PERM_ATTACH,Indicates if the device attached to a downstream port is permanently attached or not. 0: Not permanently attached 1: Permanently attached The lower bits are for USB 2.0 ports and the higher bits are for USB 3.0 SS ports:.." "Not permanently attached,Permanently attached,?,?" newline bitfld.long 0x0 0. "PME_EN,In host mode when hibernation is disabled (GCTL.GblHibernationEn=0) this input enables the controller to generate the pme_generation signal. unused in: Device mode Host mode when hibernation is enabled (GCTL.GblHibernationEn=1)" "0,1" line.long 0x4 "CTRL_1,CTRL_1" hexmask.long.word 0x4 22.--31. 1. "RSVD0,RSVD0" hexmask.long.byte 0x4 18.--21. 1. "RAM_DEBUG_SEL,ram_debug_sel: 0x0-0x7: internal RAM0 0x8-0xB:internal RAM1 0xC-0xF:internal RAM2" newline bitfld.long 0x4 16.--17. "CTRL_REF_SEL,ctrl_ref_clk select: 0 : i_ref_alt_clk_p 1 : i_ref_alt_clk_p 2: i_suspend_clk 3:i_ref_output_clk" "i_ref_alt_clk_p,i_ref_alt_clk_p,i_suspend_clk,i_ref_output_clk" hexmask.long.word 0x4 6.--15. 1. "DRVRSM32KCTRL1,DRVRSM32KCTRL1" newline hexmask.long.byte 0x4 1.--5. 1. "DRVRSM32KCTRL0,DRVRSM32KCTRL0" bitfld.long 0x4 0. "DRVRSM32KEN,DRVRSM32KEN" "0,1" repeat 6. (list 0x2 0x3 0x4 0x5 0x6 0x7 )(list 0x0 0x4 0x8 0xC 0x10 0x14 ) group.long ($2+0x18)++0x3 line.long 0x0 "CTRL_$1,CTRL_2" hexmask.long 0x0 0.--31. 1. "RSVD0,RSVD0" repeat.end group.long 0x80++0x3 line.long 0x0 "INTR,INTR" bitfld.long 0x0 15. "INTR_RSVD8,INTR_RSVD8" "0,1" newline bitfld.long 0x0 14. "INTR_RSVD7,INTR_RSVD7" "0,1" bitfld.long 0x0 13. "INTR_RSVD6,INTR_RSVD6" "0,1" newline bitfld.long 0x0 12. "INTR_RSVD5,INTR_RSVD5" "0,1" bitfld.long 0x0 11. "INTR_RSVD4,INTR_RSVD4" "0,1" newline bitfld.long 0x0 10. "INTR_RSVD3,INTR_RSVD3" "0,1" bitfld.long 0x0 9. "INTR_RSVD2,INTR_RSVD2" "0,1" newline bitfld.long 0x0 8. "INTR_RSVD1,INTR_RSVD1" "0,1" bitfld.long 0x0 7. "INTR_RSVD0,INTR_RSVD0" "0,1" newline bitfld.long 0x0 6. "INTR_WAKEUP,INTR_WAKEUP" "0,1" bitfld.long 0x0 5. "INTR_HOST_LEGACY_SMI_INTERRUPT,INTR_HOST_LEGACY_SMI_INTERRUPT" "0,1" newline bitfld.long 0x0 4. "INTR_PME_GENERATION,INTR_PME_GENERATION" "0,1" bitfld.long 0x0 3. "INTR_BC_INTERRUPT,INTR_BC_INTERRUPT" "0,1" newline bitfld.long 0x0 2. "INTR_CHGDET,INTR_CHGDET" "0,1" bitfld.long 0x0 1. "INTR_HOST_SYSTEM_ERR,INTR_HOST_SYSTEM_ERR" "0,1" newline bitfld.long 0x0 0. "INTR_CORE_INTERRUPT,INTR_CORE_INTERRUPT" "0,1" rgroup.long 0x90++0x7 line.long 0x0 "STS_0,STS_0" bitfld.long 0x0 1. "SUSPEND_CLK_ACTIVE,indicate the SUSPEND_CLK is ACTIVE or not 1: active 0:inactive" "inactive,active" newline bitfld.long 0x0 0. "ACLK_ACTIVE,indicate the bus clk is ACTIVE or not 1: active 0:inactive" "inactive,active" line.long 0x4 "STS_1,STS_1" bitfld.long 0x4 17. "DISRXDETU3RXDET_ACK,DisRxDetU3RxDet_ack of USB 3.0 SS Ports This signal is an acknowledgment of DisRxDetU3RxDet. When this signal is 1'b1 the controller releases the ownership of the the PIPE interface and does not issue PHY commands to the PIPE.." "0,1" newline bitfld.long 0x4 14.--16. "CLK_GATE_CTRL,Clock gating control This signal indicates the clock gating controls used for gating RAM and bus clocks. Bit[0] is gating control for bus_clk bit[1] and bit[2] is for ram_clk_in. This output must be used only for debug purposes." "0,1,2,3,4,5,6,7" bitfld.long 0x4 12.--13. "OPERATIONAL_MODE,Port Capability Direction 2'b01: for default Host operation (Power on value allowed only when DWC_USB3_MODE=1) 2'b10: for default Device operation (Power on value allowed only when DWC_USB3_MODE!=1)" "?,for default Host operation,for default Device operation,?" newline hexmask.long.word 0x4 0.--11. 1. "HOST_CURRENT_BELT,Current BELT Value. This signal indicates the minimum value of all received BELT values and the BELT that is set by the Set LTV command. This signal is valid only in Host mode." repeat 9. (list 0x2 0x3 0x4 0x5 0x7 0x8 0x9 0xA 0xB )(list 0x0 0x4 0x8 0xC 0x14 0x18 0x1C 0x20 0x24 ) rgroup.long ($2+0x98)++0x3 line.long 0x0 "STS_$1,STS_2" hexmask.long 0x0 0.--31. 1. "LOGIC_ANALYZER_TRACE_0,LOGIC_ANALYZER_TRACE_0" repeat.end rgroup.long 0xA8++0x3 line.long 0x0 "STS_6,STS_6" bitfld.long 0x0 0.--2. "DEBUG_2,DEBUG_2" "0,1,2,3,4,5,6,7" tree.end tree "USB_PHY1" base ad:0x31240000 rgroup.word 0x0++0x1 line.word 0x0 "SUP_DIG_IDCODE_LO,Low 16 bits of IDCODE" newline hexmask.word 0x0 0.--15. 1. "DATA," rgroup.word 0x4++0x1 line.word 0x0 "SUP_DIG_IDCODE_HI,High 16 bits of IDCODE" newline hexmask.word 0x0 0.--15. 1. "DATA," group.word 0x8++0x1 line.word 0x0 "SUP_DIG_DEBUG,Debug controls" newline hexmask.word 0x0 7.--15. 1. "RESERVED_15_7,Reserved for Future use" newline bitfld.word 0x0 5.--6. "DTB_SEL,The lane DTB's are OR'd together with the support DTB signals selected with the below encodings 0 - none 1 - reset_ctl DTB output 2 - scope DTB output 3 - rtune DTB output" "none,reset_ctl DTB output,scope DTB output,rtune DTB output" newline hexmask.word.byte 0x0 0.--4. 1. "TX_VREF_SEL," group.word 0xC++0x1 line.word 0x0 "SUP_DIG_RTUNE_DEBUG,Resistor tuning debug controls" newline rbitfld.word 0x0 15. "RESERVED_15_15,Reserved for Future use" "0,1" newline hexmask.word 0x0 5.--14. 1. "VALUE,Value to use when triggering SET_VAL field only the 6 LSB's are used when setting rx or tx cal values (USER2 - read-write and custom)" newline bitfld.word 0x0 3.--4. "TYPE,Type of manual tuning or register read/write to execute 0 - ADC or read/write rt_value 1 - Rx tune or read/write rx_cal_val (only 6 bits) 2 - Tx tune or read/write tx_cal_val (only 6 bits) 3 - Resref detect (no affect when triggering SET_VAL.." "ADC,Rx tune,read-write and custom),Resref detect" newline bitfld.word 0x0 2. "SET_VAL,Set value Write to a 1 to manually write the register specified by the TYPE field to the value in the VALUE field (USER2 - read-write and custom)" "0,1" newline bitfld.word 0x0 1. "MAN_TUNE,Write to a 1 to do a manual tuning specified by TYPE field starting a manual tune while a tune is currently running can cause unpredictable results. For use only when you know the state of the rtune circuit. (USER2 - read-write and custom)" "0,1" newline bitfld.word 0x0 0. "FLIP_COMP,Invert analog comparator output (USER2 - read-write and custom)" "0,1" rgroup.word 0x10++0x1 line.word 0x0 "SUP_DIG_RTUNE_STAT,Resistor tuning register status" newline hexmask.word.byte 0x0 10.--15. 1. "RESERVED_15_10,Reserved for Future use" newline hexmask.word 0x0 0.--9. 1. "STAT,Current value of the register specifed by the TYPE field in the debug control register. Set the TYPE field in the DEBUG register and then do a read of this register. (RU - read-only volatile)" group.word 0x14++0x1 line.word 0x0 "SUP_DIG_SS_PHASE,Current MPLL phase selector value" newline bitfld.word 0x0 13.--15. "REF_SEL_DIV,Reference Divisor to get better resolution and lower PPM errors when synthesizing from a non-integer reference clock. NOTE: Default value is 4. One is added in hardware to give a range of 1 to 8. (volatile and 2 reads needed to read value)" "0,1,2,3,4,5,6,7" newline bitfld.word 0x0 12. "PH_SEL,Phase Mixer Clock select. 1: is pmix. 0 is VCO. (volatile and 2 reads needed to read value)" "?,is pmix" newline bitfld.word 0x0 11. "ZERO_FREQ,Zero frequency register. NOTES: Must be set for PHASE writes to stick (volatile and 2 reads needed to read value)" "0,1" newline hexmask.word 0x0 2.--10. 1. "VAL,Phase value from zero reference (volatile and 2 reads needed to read value)" newline bitfld.word 0x0 0.--1. "DTHR,Bits below the useful resolution (volatile and 2 reads needed to read value)" "0,1,2,3" group.word 0x18++0x1 line.word 0x0 "SUP_DIG_SS_FREQ,Frequency Control for Spread Spectrum" newline rbitfld.word 0x0 15. "RESERVED_15_15,Reserved for Future use" "0,1" newline bitfld.word 0x0 14. "FREQ_OVRD,Frequency Reigster Override. NOTE: Must be set for PHASE writes to stick (volatile and 2 reads needed to read value)" "0,1" newline hexmask.word.byte 0x0 7.--13. 1. "FREQ_PK,Peak Frequency Value (for changing direction) (volatile and 2 reads needed to read value)" newline hexmask.word.byte 0x0 0.--6. 1. "FREQ_CNT_INIT,Initial Frequency Counter Value (volatile and 2 reads needed to read value)" group.word 0x1C++0x1 line.word 0x0 "SUP_DIG_HSP_SS_PHASE,Current HSP_PMIX SSC phase sel value" newline hexmask.word.byte 0x0 11.--15. 1. "RESERVED_15_11,Reserved for Future use" newline hexmask.word.byte 0x0 4.--10. 1. "VAL,SSC phase value from zero reference (volatile and 2 reads needed to read value)" newline hexmask.word.byte 0x0 0.--3. 1. "DTHR,Bits below the useful resolution (volatile and 2 reads needed to read value)" group.word 0x20++0x1 line.word 0x0 "SUP_DIG_MPLL_CNT_CTL,Control for fixed or variable MPLL Count Selection" newline hexmask.word 0x0 1.--15. 1. "RESERVED_15_1,Reserved for Future use" newline bitfld.word 0x0 0. "VAR_CNT_EN,Selects variable count when enabled (Default = fixed count)" "0,1" group.word 0x24++0x1 line.word 0x0 "SUP_DIG_CR_PARA_ALU_CTL,Control for CR Parallel ALU access" newline hexmask.word 0x0 5.--15. 1. "RESERVED_15_5,Reserved for Future use" newline hexmask.word.byte 0x0 1.--4. 1. "CR_PARA_ALU_OPCODE,Opcode for the ALU when CR para access is enabled. Valid opcodes are as follows: 0 - Zero the accumulator 1 - Add control register read result to accumulator 2 - Add control register write data to accumulator 3 - Shift accumulator left.." newline bitfld.word 0x0 0. "CR_PARA_ALU_ACCESS_EN,Enable access to the ALU through the CR parallel bus." "0,1" rgroup.word 0x28++0x1 line.word 0x0 "SUP_DIG_CR_PARA_ALU_FLAGS,Flags from the ALU when CR para access is enabled." newline hexmask.word 0x0 4.--15. 1. "RESERVED_15_4,Reserved for Future use" newline hexmask.word.byte 0x0 0.--3. 1. "DATA,Flags from the ALU when CR para access is enabled. Valid ALU flags: 0 - Signedness used for next ADD_PHSEL command. (1=signed 0=unsigned) 1 - Signedness for ADD_PHSEL command has been chosen by a previous ADD_PHSEL command. 2 - Error detected.." group.word 0x40++0x1 line.word 0x0 "SUP_DIG_ATEOVRD,Override values for incoming controls from ASIC" newline hexmask.word 0x0 3.--15. 1. "RESERVED_15_3,Reserved for Future use" newline bitfld.word 0x0 2. "ATEOVRD_EN,Override enable for ATE signals. NOTE: This register is only accessible through cregs. Does not retain state during reset or ATPG. (USER2 - read-write and custom)" "0,1" newline bitfld.word 0x0 1. "REF_USB2_EN,Override value for USB HSP PHY ref_clk enable. (USER2 - read-write and custom)" "0,1" newline bitfld.word 0x0 0. "REF_CLKDIV2,Override value for SSP ref_clk pre-scaler. (USER2 - read-write and custom)" "0,1" group.word 0x44++0x1 line.word 0x0 "SUP_DIG_MPLL_OVRD_IN_LO,Override values for incoming RTUNE and MPLL controls from ASIC" newline bitfld.word 0x0 15. "RES_ACK_IN_OVRD,Override enable for res_ack_in" "0,1" newline bitfld.word 0x0 14. "RES_ACK_IN,Override value for res_ack_in" "0,1" newline bitfld.word 0x0 13. "RES_REQ_IN_OVRD,Override enable for res_req_in" "0,1" newline bitfld.word 0x0 12. "RES_REQ_IN,Override value for res_req_in" "0,1" newline bitfld.word 0x0 11. "RTUNE_REQ_OVRD,Override enable for rtune_req" "0,1" newline bitfld.word 0x0 10. "RTUNE_REQ,Override value for rtune_req" "0,1" newline bitfld.word 0x0 9. "MPLL_MULTIPLIER_OVRD,Override enable for mpll_multipler" "0,1" newline hexmask.word.byte 0x0 2.--8. 1. "MPLL_MULTIPLIER,Override value for mpll_multipler" newline bitfld.word 0x0 1. "MPLL_EN_OVRD,Override enable for mpll_en" "0,1" newline bitfld.word 0x0 0. "MPLL_EN,Override value for mpll_en" "0,1" group.word 0x48++0x1 line.word 0x0 "SUP_DIG_MPLL_OVRD_IN_HI,Override values for incoming VBOOST LVL and MPLL controls from ASIC" newline bitfld.word 0x0 13.--15. "TX_VBOOST_LVL,Override value for tx_vboost_lvl. Override enabled using LEVEL_EN from LEVEL_OVRD_IN register." "0,1,2,3,4,5,6,7" newline bitfld.word 0x0 12. "MPLL_REFSSC_CLK_EN_OVRD,Override enable for mpll_refssc_clk_en" "0,1" newline bitfld.word 0x0 11. "MPLL_REFSSC_CLK_EN,Override value for mpll_refssc_clk_en" "0,1" newline bitfld.word 0x0 10. "MPLL_RST,Reset the MPLL state machine Writing the register with this bit set will reset the MPLL power up/down FSM regardless of the current state of the register bit." "0,1" newline bitfld.word 0x0 9. "FSEL_OVRD,Override enable for fsel[2:0]" "0,1" newline bitfld.word 0x0 6.--8. "FSEL,Override value for fsel [2:0]" "0,1,2,3,4,5,6,7" newline bitfld.word 0x0 5. "MPLL_WORD_CLK_EN_OVRD,Override enable for mpll_word_clk_en" "0,1" newline bitfld.word 0x0 4. "MPLL_WORD_CLK_EN,Override value for mpll_word_clk_en" "0,1" newline bitfld.word 0x0 3. "MPLL_DWORD_CLK_EN_OVRD,Override enable for mpll_dword_clk_en" "0,1" newline bitfld.word 0x0 2. "MPLL_DWORD_CLK_EN,Override value for mpll_dword_clk_en" "0,1" newline bitfld.word 0x0 1. "MPLL_QWORD_CLK_EN_OVRD,Override enable for mpll_qword_clk_en" "0,1" newline bitfld.word 0x0 0. "MPLL_QWORD_CLK_EN,Override value for mpll_qword_clk_en" "0,1" group.word 0x4C++0x1 line.word 0x0 "SUP_DIG_SSC_OVRD_IN,Override values for incoming SSC controls from ASIC" newline rbitfld.word 0x0 14.--15. "RESERVED_15_14,Reserved for Future use" "0,1,2,3" newline bitfld.word 0x0 13. "SSC_OVRD_IN_EN,Override enable for Spread Spectrum generator." "0,1" newline bitfld.word 0x0 12. "SSC_EN,Override value for SSC enable." "0,1" newline bitfld.word 0x0 9.--11. "SSC_RANGE,Override value for SSC modulation range." "0,1,2,3,4,5,6,7" newline hexmask.word 0x0 0.--8. 1. "SSC_REF_CLK_SEL,Override value for reference clock scaling" group.word 0x50++0x1 line.word 0x0 "SUP_DIG_BS_OVRD_IN,Override values for incoming BS controls from ASIC" newline hexmask.word.byte 0x0 12.--15. 1. "RESERVED_15_12,Reserved for Future use" newline bitfld.word 0x0 11. "EN,Enable override values for all inputs controlled by this register" "0,1" newline bitfld.word 0x0 10. "INVERT,Override value for bs_invert" "0,1" newline bitfld.word 0x0 9. "INIT,Override value for bs_init" "0,1" newline bitfld.word 0x0 8. "HIGHZ,Override value for bs_highz" "0,1" newline bitfld.word 0x0 7. "CLAMP,Override value for bs_clamp" "0,1" newline bitfld.word 0x0 6. "EXTEST_AC,Override value for bs_extest_ac" "0,1" newline bitfld.word 0x0 5. "EXTEST,Override value for bs_extest" "0,1" newline bitfld.word 0x0 4. "PRELOAD,Override value for bs_preload" "0,1" newline bitfld.word 0x0 3. "UPDATE_DR,Override value for bs_update_dr" "0,1" newline bitfld.word 0x0 2. "CAPTURE_DR,Override value for bs_capture_dr" "0,1" newline bitfld.word 0x0 1. "SHIFT_DR,Override value for bs_shift_dr" "0,1" newline bitfld.word 0x0 0. "IN,Override value for bs_in" "0,1" group.word 0x54++0x1 line.word 0x0 "SUP_DIG_LEVEL_OVRD_IN,Override values for acjt_level and los_level" newline bitfld.word 0x0 13.--15. "LOS_BIAS,Override value for los_bias" "0,1,2,3,4,5,6,7" newline bitfld.word 0x0 12. "MPLL_HALF_RATE_OVRD,Enable override value for mpll_half_rate" "0,1" newline bitfld.word 0x0 11. "MPLL_HALF_RATE,Override value for mpll_half_rate" "0,1" newline bitfld.word 0x0 10. "LEVEL_EN,Enable override values for tx_vboost_lvl/los_bias/los_level/acjt_level inputs controlled by this and MPLL_OVRD_IN_HI registers" "0,1" newline hexmask.word.byte 0x0 5.--9. 1. "ACJT_LEVEL,Override value for acjt_level" newline hexmask.word.byte 0x0 0.--4. 1. "LOS_LEVEL,Override value for los_level" group.word 0x58++0x1 line.word 0x0 "SUP_DIG_SUP_OVRD_OUT,Override values for support block" newline hexmask.word.byte 0x0 10.--15. 1. "RESERVED_15_10,Reserved for Future use" newline bitfld.word 0x0 9. "MPLL_STATE_OVRD,Override enable for mpll_state output" "0,1" newline bitfld.word 0x0 8. "MPLL_STATE,Override value for mpll_state output" "0,1" newline bitfld.word 0x0 7. "BS_OUT_OVRD,Override enable for bs_out output" "0,1" newline bitfld.word 0x0 6. "BS_OUT,Override value for bs_out output" "0,1" newline bitfld.word 0x0 5. "RTUNE_ACK_OVRD,Override enable for rtune_ack output" "0,1" newline bitfld.word 0x0 4. "RTUNE_ACK,Override value for rtune_ack output" "0,1" newline bitfld.word 0x0 3. "RES_REQ_OUT_OVRD,Override enable for res_req_out output" "0,1" newline bitfld.word 0x0 2. "RES_REQ_OUT,Override value for res_req_out output" "0,1" newline bitfld.word 0x0 1. "RES_ACK_OUT_OVRD,Override enable for res_ack_out output" "0,1" newline bitfld.word 0x0 0. "RES_ACK_OUT,Override value for res_ack_out output" "0,1" rgroup.word 0x5C++0x1 line.word 0x0 "SUP_DIG_MPLL_ASIC_IN,Current values for incoming MPLL controls from ASIC" newline bitfld.word 0x0 15. "RESERVED_15_15,Reserved for Future use" "0,1" newline bitfld.word 0x0 14. "MPLL_REFSSC_CLK_EN,Value from ASIC for mpll_refssc_clk_en (RU - read-only volatile)" "0,1" newline bitfld.word 0x0 13. "MPLL_WORD_CLK_EN,Value from ASIC for mpll_word_clk_en (RU - read-only volatile)" "0,1" newline bitfld.word 0x0 12. "MPLL_DWORD_CLK_EN,Value from ASIC for mpll_dword_clk_en (RU - read-only volatile)" "0,1" newline bitfld.word 0x0 11. "MPLL_QWORD_CLK_EN,Value from ASIC for mpll_qword_clk_en (RU - read-only volatile)" "0,1" newline bitfld.word 0x0 10. "RES_ACK_IN,Value from ASIC for res_ack_in (RU - read-only volatile)" "0,1" newline bitfld.word 0x0 9. "RES_REQ_IN,Value from ASIC for res_req_in (RU - read-only volatile)" "0,1" newline bitfld.word 0x0 8. "RTUNE_REQ,Value from ASIC for rtune_req (RU - read-only volatile)" "0,1" newline hexmask.word.byte 0x0 1.--7. 1. "MPLL_MULTIPLIER,Value from ASIC for mpll_multiplier (RU - read-only volatile)" newline bitfld.word 0x0 0. "MPLL_EN,Value from ASIC for mpll_en (RU - read-only volatile)" "0,1" rgroup.word 0x60++0x1 line.word 0x0 "SUP_DIG_BS_ASIC_IN,Current values for incoming boundary scan controls from ASIC" newline bitfld.word 0x0 14.--15. "RESERVED_15_14,Reserved for Future use" "0,1,2,3" newline bitfld.word 0x0 11.--13. "TX_VBOOST_LVL,Value from ASIC for tx_vboost_lvl -- Not as bs_* signal but we're out of bits. (RU - read-only volatile)" "0,1,2,3,4,5,6,7" newline bitfld.word 0x0 10. "INVERT,Value from ASIC for bs_invert (RU - read-only volatile)" "0,1" newline bitfld.word 0x0 9. "INIT,Value from ASIC for bs_init (RU - read-only volatile)" "0,1" newline bitfld.word 0x0 8. "HIGHZ,Value from ASIC for bs_highz (RU - read-only volatile)" "0,1" newline bitfld.word 0x0 7. "CLAMP,Value from ASIC for bs_clamp (RU - read-only volatile)" "0,1" newline bitfld.word 0x0 6. "EXTEST_AC,Value from ASIC for bs_extest_ac (RU - read-only volatile)" "0,1" newline bitfld.word 0x0 5. "EXTEST,Value from ASIC for bs_extest (RU - read-only volatile)" "0,1" newline bitfld.word 0x0 4. "PRELOAD,Value from ASIC for bs_preload (RU - read-only volatile)" "0,1" newline bitfld.word 0x0 3. "UPDATE_DR,Value from ASIC for bs_update_dr (RU - read-only volatile)" "0,1" newline bitfld.word 0x0 2. "CAPTURE_DR,Value from ASIC for bs_capture_dr (RU - read-only volatile)" "0,1" newline bitfld.word 0x0 1. "SHIFT_DR,Value from ASIC for bs_shift_dr (RU - read-only volatile)" "0,1" newline bitfld.word 0x0 0. "IN,Value from ASIC for bs_in (RU - read-only volatile)" "0,1" rgroup.word 0x64++0x1 line.word 0x0 "SUP_DIG_LEVEL_ASIC_IN,Current values for incoming los/acjt level. MPLL half rate mode and vreg bypass from ASIC" newline bitfld.word 0x0 15. "RESERVED_15_15,Reserved for Future use" "0,1" newline bitfld.word 0x0 12.--14. "LOS_BIAS,Value from ASIC for los_bias (RU - read-only volatile)" "0,1,2,3,4,5,6,7" newline bitfld.word 0x0 11. "MPLL_HALF_RATE,Value from ASIC for mpll_half_rate (RU - read-only volatile)" "0,1" newline bitfld.word 0x0 10. "VREG_BYPASS,Value from ASIC for vreg_bypass (RU - read-only volatile)" "0,1" newline hexmask.word.byte 0x0 5.--9. 1. "ACJT_LEVEL,Value from ASIC for acjt_level (RU - read-only volatile)" newline hexmask.word.byte 0x0 0.--4. 1. "LOS_LEVEL,Value from ASIC for los_level (RU - read-only volatile)" rgroup.word 0x68++0x1 line.word 0x0 "SUP_DIG_SSC_ASIC_IN,Current values for incoming SSC controls from ASIC" newline bitfld.word 0x0 15. "SS_EN,Value from ASIC for ssc_en (RU - read-only volatile)" "0,1" newline bitfld.word 0x0 12.--14. "SSC_RANGE,Value from ASIC for ssc_range (RU - read-only volatile)" "0,1,2,3,4,5,6,7" newline hexmask.word 0x0 3.--11. 1. "SSC_REF_CLK_SEL,Value from ASIC for ssc_ref_clk_sel (RU - read-only volatile)" newline bitfld.word 0x0 0.--2. "FSEL,Value from ASIC for fsel (RU - read-only volatile)" "0,1,2,3,4,5,6,7" rgroup.word 0x6C++0x1 line.word 0x0 "SUP_DIG_SUP_ASIC_OUT,Current values for outgoing support block controls to ASIC" newline hexmask.word 0x0 5.--15. 1. "RESERVED_15_5,Reserved for Future use" newline bitfld.word 0x0 4. "MPLL_STATE,Value from PHY for mpll_state output (RU - read-only volatile)" "0,1" newline bitfld.word 0x0 3. "BS_OUT,Value from PHY for bs_out output (RU - read-only volatile)" "0,1" newline bitfld.word 0x0 2. "RTUNE_ACK,Value from PHY for rtune_ack output (RU - read-only volatile)" "0,1" newline bitfld.word 0x0 1. "RES_REQ_OUT,Value from PHY for res_req_out output (RU - read-only volatile)" "0,1" newline bitfld.word 0x0 0. "RES_ACK_OUT,Value from PHY for res_ack_out output (RU - read-only volatile)" "0,1" rgroup.word 0x70++0x1 line.word 0x0 "SUP_DIG_ATEOVRD_STATUS,USB3_SUP_DIG_ATEOVRD_STATUS" newline hexmask.word.byte 0x0 10.--15. 1. "RESERVED_15_10,Reserved for Future use" newline bitfld.word 0x0 8.--9. "DTB_OUT,Value from dtb_out bus. (RU - read-only volatile)" "0,1,2,3" newline bitfld.word 0x0 7. "REF_SSP_EN,Value from ASIC for ref_ssp_en. (RU - read-only volatile)" "0,1" newline bitfld.word 0x0 6. "REF_USE_PAD,Value from ASIC for ref_use_pad. (RU - read-only volatile)" "0,1" newline bitfld.word 0x0 5. "PHY_RESET_IN,Value from ASIC for phy_reset (RU - read-only volatile)" "0,1" newline bitfld.word 0x0 4. "REF_CLKDIV2_IN,Value from ASIC for ref_clkdiv2 (RU - read-only volatile)" "0,1" newline bitfld.word 0x0 3. "REF_USB2_EN_IN,Value from ASIC for ref_usb2_en (RU - read-only volatile)" "0,1" newline bitfld.word 0x0 2. "ATEOVRD_EN,When set values from ATEOVRD register are being sent to PHY (RU - read-only volatile)" "0,1" newline bitfld.word 0x0 1. "REF_CLKDIV2_OUT,Value from ATEOVRD for ref_clkdiv2 (RU - read-only volatile)" "0,1" newline bitfld.word 0x0 0. "REF_USB2_EN_OUT,Value from ATEOVRD for ref_usb2_en (RU - read-only volatile)" "0,1" group.word 0x74++0x1 line.word 0x0 "SUP_DIG_HSP_OVRD_IN,Override values for HSP" newline hexmask.word 0x0 4.--15. 1. "RESERVED_15_4,Reserved for Future use" newline bitfld.word 0x0 3. "HSP_PLL_OVRD,Override enable for HSP pll_pu signal" "0,1" newline bitfld.word 0x0 2. "HSP_PLL_PU,Override value for HSP pll_pu signal" "0,1" newline bitfld.word 0x0 1. "HSP_BIAS_OVRD,Override enable for HSP bias_pu signal" "0,1" newline bitfld.word 0x0 0. "HSP_BIAS_PU,Override value for HSP bias_pu signal" "0,1" rgroup.word 0x78++0x1 line.word 0x0 "SUP_DIG_HSP_ASIC_IN,Current values for incoming HSP & REF XO controls from ASIC" newline hexmask.word 0x0 4.--15. 1. "RESERVED_15_4,Reserved for Future use" newline bitfld.word 0x0 3. "REF_USE_XO,Value from ASIC for ref_use_xo (RU - read-only volatile)" "0,1" newline bitfld.word 0x0 2. "REF_XO_EN,Value from ASIC for ref_xo_en (RU - read-only volatile)" "0,1" newline bitfld.word 0x0 1. "HSP_PLL_PU,Value from ASIC for hsp_pll_pu (RU - read-only volatile)" "0,1" newline bitfld.word 0x0 0. "HSP_BIAS_PU,Value from ASIC for hsp_bias_pu (RU - read-only volatile)" "0,1" group.word 0x80++0x1 line.word 0x0 "SUP_DIG_SCOPE_ENABLES,Scope Counter configuration" newline hexmask.word 0x0 5.--15. 1. "RESERVED_15_5,Reserved for Future use" newline bitfld.word 0x0 3.--4. "LANE_SELECT,Scope Counter Input select" "0,1,2,3" newline bitfld.word 0x0 2. "MASK_SATURATION_MODE,Method of mask saturation. When 1 Saturate when the first mask_counter reaches sample_limit. When 0 Saturate when all mask_counters have reached sample_limit." "0,1" newline bitfld.word 0x0 1. "MASK_EN,Enable scope_mask input for tracking count values. Clears registers when deasserted." "0,1" newline bitfld.word 0x0 0. "XOR_EN,Use scope_xor input for count values." "0,1" group.word 0x84++0x1 line.word 0x0 "SUP_DIG_SCOPE_SAMPLES,Number of samples to count" newline hexmask.word 0x0 0.--15. 1. "SAMPLES,Number of Sample to count." rgroup.word 0x88++0x1 line.word 0x0 "SUP_DIG_SCOPE_COUNT,Results of scope counting" newline hexmask.word 0x0 0.--15. 1. "COUNT,A write to this register will start the counting process The value of FFFF indicates counting still in progress. Asserting MASK_EN will also start the counting if in MASK mode. (RU - read-only volatile)" group.word 0x8C++0x1 line.word 0x0 "SUP_DIG_SCOPE_CTL,Masked scope counting Start and Status" newline hexmask.word 0x0 2.--15. 1. "RESERVED_15_2,Reserved for Future use" newline bitfld.word 0x0 1. "MASK_START,A write to this register will start the counting process The value of FFFF indicates counting still in progress Write will trigger mask counting. (USER1 - read-write volatile)" "?,read-write volatile)" newline bitfld.word 0x0 0. "MASK_SATURATION,When assert mask registers have saturated. (USER1 - read-write volatile)" "?,read-write volatile)" repeat 8. (list 0x0 0x1 0xA 0xB 0x64 0x65 0x6E 0x6F )(list 0x0 0x4 0x8 0xC 0x10 0x14 0x18 0x1C ) group.word ($2+0x90)++0x1 line.word 0x0 "SUP_DIG_SCOPE_MASK_$1,Current count value for mask_000" newline hexmask.word 0x0 0.--15. 1. "MASK_VAL_000,Starting count value of mask register. (volatile and 2 reads needed to read value)" repeat.end group.word 0xC0++0x1 line.word 0x0 "SUP_ANA_MPLL_LOOP_CTL,MPLL loop control bits" newline hexmask.word.byte 0x0 8.--15. 1. "RESERVED_15_8,Reserved for Future use" newline hexmask.word.byte 0x0 4.--7. 1. "PROP_CNTRL,Charge pump proportional current setting" newline bitfld.word 0x0 2.--3. "INT_CNTRL,Charge pump integrating current setting" "0,1,2,3" newline bitfld.word 0x0 1. "GD,Measure MPLL local GD" "0,1" newline bitfld.word 0x0 0. "VMB,Measure MPLL Master Bias Voltage" "0,1" repeat 2. (list 0x1 0x2 )(list 0x0 0x4 ) group.word ($2+0xC4)++0x1 line.word 0x0 "SUP_ANA_MPLL_ATB_MEAS$1,ATB Select bits" newline hexmask.word.byte 0x0 8.--15. 1. "RESERVED_15_8,Reserved for Future use" newline bitfld.word 0x0 7. "VPSF,puts vpsf on atb_s_p" "0,1" newline bitfld.word 0x0 6. "VREF,puts vref from charge pump on atb_s_p" "0,1" newline bitfld.word 0x0 5. "VCNTRL,puts vcntrl on atb_s_m" "0,1" newline bitfld.word 0x0 4. "GD,puts gd on atb_s_m" "0,1" newline bitfld.word 0x0 3. "IVCO,puts VCO current/93 on atb_f_m" "0,1" newline bitfld.word 0x0 2. "VP,puts vpa on atb_s_m" "0,1" newline bitfld.word 0x0 1. "VP_CP,puts vp_cp on atb_s_p" "0,1" newline bitfld.word 0x0 0. "VREG_MPLL,puts vreg_mpll on atb_s_p" "0,1" repeat.end group.word 0xCC++0x1 line.word 0x0 "SUP_ANA_MPLL_OVRD,Local overrides" newline hexmask.word.byte 0x0 8.--15. 1. "RESERVED_15_8,Reserved for Future use" newline bitfld.word 0x0 7. "PWRON_LCL,local power_on value" "0,1" newline bitfld.word 0x0 6. "EN_PWRON_LCL,Enable local control of power_on" "0,1" newline bitfld.word 0x0 5. "GS_LCL,local gear_shift value" "0,1" newline bitfld.word 0x0 4. "EN_GS_LCL,Enable local control of gear_shift" "0,1" newline bitfld.word 0x0 3. "RST_LCL,local reset value" "0,1" newline bitfld.word 0x0 2. "EN_RST_LCL,enable local control of reset" "0,1" newline bitfld.word 0x0 1. "PMIX_CLK_SEL_LCL,local pmix_clk_sel value" "0,1" newline bitfld.word 0x0 0. "EN_PMIX_CLK_SEL_LCL,enable local control of pmix_clk_sel" "0,1" group.word 0xD0++0x1 line.word 0x0 "SUP_ANA_RTUNE_RTUNE_CTRL,RTUNE control bits" newline hexmask.word.byte 0x0 8.--15. 1. "RESERVED_15_8,Reserved for Future use" newline bitfld.word 0x0 7. "RT_PWRON_FRC_ON,When set forces RTUNE block to be on" "0,1" newline bitfld.word 0x0 6. "X4_FRC_OFF,When set do not multiply test current by 4" "0,1" newline bitfld.word 0x0 4.--5. "RT_DAC_MODE,Margin DAC mode control bits(00=powerdown 01=DAC drives atb_s_p/m directly 10=DAC drives atb_s_p/m to the RX in margining mode 11=illegal state)" "powerdown,DAC drives atb_s_p/m directly,?,?" newline bitfld.word 0x0 3. "RT_DAC_CHOP,Margin DAC chop control bit. ref to ssp analog engineering doc 8.5" "0,1" newline bitfld.word 0x0 2. "RT_ATB,RTUNE ATB mode control bit (1=RTUNE performs ADC on ATB input 0=not accessing ATB. refer to ssp analog engineering specification 8.1.4)" "not accessing ATB,RTUNE performs ADC on ATB input" newline bitfld.word 0x0 1. "RT_SEL_ATBP,RTUNE ATB sense input select bit (1=atb_s_p 0=atb_s_m)" "atb_s_m),atb_s_p" newline bitfld.word 0x0 0. "RT_SEL_ATBF,RTUNE ATB input select bit (1=atb_fm 0=atb_s_p/m)" "atb_s_p/m),atb_fm" group.word 0xD4++0x1 line.word 0x0 "SUP_ANA_ATB_SWITCHYARD_CTRL,ATB_SWITCHYARD control bits" newline hexmask.word.byte 0x0 8.--15. 1. "RESERVED_15_8,Reserved for Future use" newline bitfld.word 0x0 7. "ASM_GD,Connect gd to atb_s_m" "0,1" newline bitfld.word 0x0 6. "ASP_VP,Connect vp to atb_s_p" "0,1" newline bitfld.word 0x0 5. "ASP_VBG,Connect vbg to atb_s_p" "0,1" newline bitfld.word 0x0 4. "ASP_VPHREG,Connect vphreg to atb_s_m" "0,1" newline bitfld.word 0x0 3. "ATEST_AFM,drive ATEST from atb_f_m" "0,1" newline bitfld.word 0x0 2. "ATEST_AFP,drive ATEST from atb_f_p" "0,1" newline bitfld.word 0x0 1. "ATEST_ASM,Connet ATEST to atb_s_m" "0,1" newline bitfld.word 0x0 0. "ATEST_ASP,Connect ATEST to atb_s_p" "0,1" group.word 0xD8++0x1 line.word 0x0 "SUP_ANA_SSC_CLK_CNTRL,controls sscf reference clock rate" newline hexmask.word.byte 0x0 8.--15. 1. "RESERVED_15_8,Reserved for Future use" newline bitfld.word 0x0 7. "NC,Reserved" "0,1" newline hexmask.word.byte 0x0 0.--6. 1. "SSC_CLK_DIV125,set ssc reference clock to be 20MHz" group.word 0xDC++0x1 line.word 0x0 "SUP_ANA_HSP_CLK_DIG_CNTRL0,controls HSP phase clock. and resolution" newline hexmask.word.byte 0x0 8.--15. 1. "RESERVED_15_8,Reserved for Future use" newline bitfld.word 0x0 7. "NUM_OVERRIDE,Set the value to 1 to enable using values from creg bit 6 downto 0" "0,1" newline bitfld.word 0x0 4.--6. "GATE_PMIX_BITS,Set gate_pmix_bits to gate the corresponding MSB of the 7-bit PMIX phase select bits" "?,?,?,?,?,?,?,bit PMIX phase select bits" newline bitfld.word 0x0 3. "HALF_CLK_EN,Set to 1 for 1.25GHz updates to HSP PMIX. Set to 0 for 2.5GHz updates to PMIX." "0,1" newline bitfld.word 0x0 2. "UCLK_EN_N,Set to 1 to disable update clock. Set to 0 to enable update clock. When clock is enabled phase updates are allowed." "0,1" newline bitfld.word 0x0 1. "EN_HSPPMIX_VPMIX,Set to 1 to connect the regulated HSP PMIX supply to the atb_s_p bus" "0,1" newline bitfld.word 0x0 0. "EN_HSPPMIX_FRC_VPMIX,Set to 1 to force override of HSP PMIX regulator voltage to voltage on atb_s_m" "0,1" group.word 0xE0++0x1 line.word 0x0 "SUP_ANA_HSP_CLK_DIG_CNTRL1,Lower and Upper Phase Increment Values" newline hexmask.word.byte 0x0 8.--15. 1. "RESERVED_15_8,Reserved for Future use" newline hexmask.word.byte 0x0 4.--7. 1. "UPPER_INT,These bits are only used when num_override is set to 1. Upper integer for phase increments of 2.5 to 2.4 GHz conversion. This is the phase increment that is applied 6 times in every 25 for 1.25 GHz increments and 3 times in every 25 for 2.5GHz" newline hexmask.word.byte 0x0 0.--3. 1. "LOWER_INT,These bits are only used when num_override is set to 1. Lower integer for phase increments of 2.5 to 2.4 GHz conversion. This phase increment is applied 19 times in every 25 for 1.25 GHz increments and 22 times in every 25 for 2.5GHz." group.word 0x1000++0x1 line.word 0x0 "LANE0_DIG_TX_OVRD_IN_LO,Override values for incoming TX controls from ASIC" newline bitfld.word 0x0 15. "LANE_IF_WIDTH_OVRD,Override enable for lane interface width" "0,1" newline bitfld.word 0x0 14. "LANE_IF_WIDTH,Override value for lane interface width" "0,1" newline bitfld.word 0x0 13. "TX_DETECT_RX_REQ_OVRD,Override enable for tx_detect_rx_req" "0,1" newline bitfld.word 0x0 12. "TX_DETECT_RX_REQ,Override value for tx_detect_rx_req" "0,1" newline bitfld.word 0x0 11. "TX_BEACON_EN_OVRD,Override enable for tx_beacon_en" "0,1" newline bitfld.word 0x0 10. "TX_BEACON_EN,Override value for tx_beacon_en" "0,1" newline bitfld.word 0x0 9. "TX_CM_EN_OVRD,Override enable for tx_cm_en" "0,1" newline bitfld.word 0x0 8. "TX_CM_EN,Override value for tx_cm_en" "0,1" newline bitfld.word 0x0 7. "TX_EN_OVRD,Override enable for tx_en" "0,1" newline bitfld.word 0x0 6. "TX_EN,Override value for tx_en" "0,1" newline bitfld.word 0x0 5. "TX_DATA_EN_OVRD,Override enable for tx_data_en" "0,1" newline bitfld.word 0x0 4. "TX_DATA_EN,Override value for tx_data_en" "0,1" newline bitfld.word 0x0 3. "TX_INVERT_OVRD,Override enable for tx_invert" "0,1" newline bitfld.word 0x0 2. "TX_INVERT,Override value for tx_invert" "0,1" newline bitfld.word 0x0 1. "TX_LOOPBK_EN_OVRD,Override enable for loopbk_en" "0,1" newline bitfld.word 0x0 0. "LOOPBK_EN,Override value for loopbk_en" "0,1" group.word 0x1004++0x1 line.word 0x0 "LANE0_DIG_TX_OVRD_IN_HI,Override values for incoming TX controls from ASIC" newline hexmask.word.byte 0x0 10.--15. 1. "RESERVED_15_10,Reserved for Future use" newline bitfld.word 0x0 9. "TX_VBOOST_EN_OVRD,Override enable for tx_vboost_en" "0,1" newline bitfld.word 0x0 8. "TX_VBOOST_EN,Override value for tx_vboost_en" "0,1" newline bitfld.word 0x0 7. "TX_RESET_OVRD,Override enable for tx_reset" "0,1" newline bitfld.word 0x0 6. "TX_RESET,Override value for tx_reset" "0,1" newline bitfld.word 0x0 5. "TX_NYQUIST_DATA,Override incoming data to nyquist" "0,1" newline bitfld.word 0x0 4. "TX_CLK_OUT_EN_OVRD,Override enable for tx_clk_out_en." "0,1" newline bitfld.word 0x0 3. "TX_CLK_OUT_EN,Override incomming tx_clk_out_en." "0,1" newline bitfld.word 0x0 2. "TX_RATE_OVRD,Override enable for tx_rate." "0,1" newline bitfld.word 0x0 0.--1. "TX_RATE,Override incomming tx lane rate." "0,1,2,3" group.word 0x1008++0x1 line.word 0x0 "LANE0_DIG_TX_OVRD_DRV_LO,Override values for incoming TX drive controls from ASIC" newline rbitfld.word 0x0 15. "RESERVED_15_15,Reserved for Future use" "0,1" newline bitfld.word 0x0 14. "EN,Enable override values for all inputs controlled by this register" "0,1" newline hexmask.word.byte 0x0 7.--13. 1. "PREEMPH,Override value for transmit preemphasis." newline hexmask.word.byte 0x0 0.--6. 1. "AMPLITUDE,Override value for transmit amplitude." group.word 0x100C++0x1 line.word 0x0 "LANE0_DIG_TX_OVRD_DRV_HI,Override values for incoming TX drive controls from ASIC" newline hexmask.word 0x0 6.--15. 1. "RESERVED_15_6,Reserved for Future use" newline bitfld.word 0x0 5. "EN,Enable override values for all inputs controlled by this register" "0,1" newline hexmask.word.byte 0x0 0.--4. 1. "TERM_OFFSET,Override value for tx_term_offset (tx_ana_vcmref_boost)" group.word 0x1010++0x1 line.word 0x0 "LANE0_DIG_TX_OVRD_OUT,Override values for outgoing TX controls to ASIC" newline hexmask.word.byte 0x0 8.--15. 1. "RESERVED_15_8,Reserved for Future use" newline bitfld.word 0x0 7. "TX_STATE_OVRD,Override enable for tx_state" "0,1" newline bitfld.word 0x0 6. "TX_STATE,Override value for tx_state" "0,1" newline bitfld.word 0x0 5. "TX_CM_STATE_OVRD,Override enable for tx_cm_state" "0,1" newline bitfld.word 0x0 4. "TX_CM_STATE,Override value for tx_cm_state" "0,1" newline bitfld.word 0x0 3. "TX_DETECT_RX_ACK_OVRD,Override enable for tx_detect_rx_ack" "0,1" newline bitfld.word 0x0 2. "TX_DETECT_RX_ACK,Override value for tx_detect_rx_ack" "0,1" newline bitfld.word 0x0 1. "DETECT_RX_RES_OVRD,Override enable for tx_detect_rx_res" "0,1" newline bitfld.word 0x0 0. "DETECT_RX_RES,Override value for tx_detect_rx_res" "0,1" group.word 0x1014++0x1 line.word 0x0 "LANE0_DIG_RX_OVRD_IN_LO,Override values for incoming RX controls from ASIC" newline rbitfld.word 0x0 14.--15. "RESERVED_15_14,Reserved for Future use" "0,1,2,3" newline bitfld.word 0x0 13. "RX_LOS_EN_OVRD,Override enable for rx_los_en" "0,1" newline bitfld.word 0x0 12. "RX_LOS_EN,Override value for rx_los_en" "0,1" newline bitfld.word 0x0 11. "RX_TERM_EN_OVRD,Override enable for rx_term_en" "0,1" newline bitfld.word 0x0 10. "RX_TERM_EN,Override value for rx_term_en" "0,1" newline bitfld.word 0x0 9. "RX_BIT_SHIFT_OVRD,Override enable for rx_bit_shift" "0,1" newline bitfld.word 0x0 8. "RX_BIT_SHIFT,Override value for rx_bit_shift" "0,1" newline bitfld.word 0x0 7. "RX_ALIGN_EN_OVRD,Override enable for rx_align_en" "0,1" newline bitfld.word 0x0 6. "RX_ALIGN_EN,Override value for rx_align_en" "0,1" newline bitfld.word 0x0 5. "RX_DATA_EN_OVRD,Override enable for rx_data_en" "0,1" newline bitfld.word 0x0 4. "RX_DATA_EN,Override value for rx_data_en" "0,1" newline bitfld.word 0x0 3. "RX_PLL_EN_OVRD,Override enable for rx_pll_en" "0,1" newline bitfld.word 0x0 2. "RX_PLL_EN,Override value for rx_pll_en" "0,1" newline bitfld.word 0x0 1. "RX_INVERT_OVRD,Override enable for rx_invert" "0,1" newline bitfld.word 0x0 0. "RX_INVERT,Override value for rx_invert" "0,1" group.word 0x1018++0x1 line.word 0x0 "LANE0_DIG_RX_OVRD_IN_HI,Override values for incoming RX controls from ASIC" newline rbitfld.word 0x0 14.--15. "RESERVED_15_14,Reserved for Future use" "0,1,2,3" newline bitfld.word 0x0 13. "RX_RESET_OVRD,Override enable for rx_reset" "0,1" newline bitfld.word 0x0 12. "RX_RESET,Override value for rx_reset" "0,1" newline bitfld.word 0x0 11. "RX_EQ_OVRD,Override enable for rx_eq" "0,1" newline bitfld.word 0x0 8.--10. "RX_EQ,Override value for rx_eq" "0,1,2,3,4,5,6,7" newline bitfld.word 0x0 7. "RX_EQ_EN_OVRD,Override enable for rx_eq_en" "0,1" newline bitfld.word 0x0 6. "RX_EQ_EN,Override value for rx_eq_en" "0,1" newline bitfld.word 0x0 5. "RX_LOS_FILTER_OVRD,Override enable for rx_los_filter" "0,1" newline bitfld.word 0x0 3.--4. "RX_LOS_FILTER,Override value for rx_los_filter" "0,1,2,3" newline bitfld.word 0x0 2. "RX_RATE_OVRD,Override enable for rx_rate" "0,1" newline bitfld.word 0x0 0.--1. "RX_RATE,Override value for rx_rate" "0,1,2,3" group.word 0x101C++0x1 line.word 0x0 "LANE0_DIG_RX_OVRD_OUT,Override values for outgoing RX controls to ASIC" newline hexmask.word 0x0 7.--15. 1. "RESERVED_15_7,Reserved for Future use" newline bitfld.word 0x0 6. "ZERO_DATA,Override data output to all zeros" "0,1" newline bitfld.word 0x0 5. "LOS_OVRD,Override value for rx_los" "0,1" newline bitfld.word 0x0 4. "LOS,Override value for rx_los" "0,1" newline bitfld.word 0x0 3. "PLL_STATE_OVRD,Override enable for rx_pll_state" "0,1" newline bitfld.word 0x0 2. "PLL_STATE,Override value for rx_pll_state" "0,1" newline bitfld.word 0x0 1. "VALID_OVRD,Override enable for rx_valid" "0,1" newline bitfld.word 0x0 0. "VALID,Override value for rx_valid" "0,1" rgroup.word 0x1020++0x1 line.word 0x0 "LANE0_DIG_TX_ASIC_IN,Current values for incoming TX controls from ASIC" newline bitfld.word 0x0 14.--15. "RESERVED_15_14,Reserved for Future use" "0,1,2,3" newline bitfld.word 0x0 13. "LANE_IF_WIDTH,Value from ASIC for lane_if_width (RU - read-only volatile)" "0,1" newline bitfld.word 0x0 12. "DATA_EN_S,Value from ASIC for tx_data_en_s (RU - read-only volatile)" "0,1" newline bitfld.word 0x0 11. "TX_VBOOST_EN,Value from ASIC for tx_vboost_en (RU - read-only volatile)" "0,1" newline bitfld.word 0x0 10. "TX_CLK_OUT_EN,Value from ASIC for tx_clk_out_en (RU - read-only volatile)" "0,1" newline bitfld.word 0x0 9. "DETECT_RX_REQ,Value from ASIC for tx_detect_rx_req (RU - read-only volatile)" "0,1" newline bitfld.word 0x0 8. "BEACON_EN,Value from ASIC for tx_beacon_en (RU - read-only volatile)" "0,1" newline bitfld.word 0x0 7. "CM_EN,Value from ASIC for tx_cm_en (RU - read-only volatile)" "0,1" newline bitfld.word 0x0 6. "TX_EN,Value from ASIC for tx_en (RU - read-only volatile)" "0,1" newline bitfld.word 0x0 5. "DATA_EN,Value from ASIC for tx_data_en (RU - read-only volatile)" "0,1" newline bitfld.word 0x0 4. "TX_RESET,Value from ASIC for tx_reset (RU - read-only volatile)" "0,1" newline bitfld.word 0x0 3. "INVERT,Value from ASIC for tx_invert (RU - read-only volatile)" "0,1" newline bitfld.word 0x0 2. "LOOPBK_EN,Value from ASIC for loopbk_en (RU - read-only volatile)" "0,1" newline bitfld.word 0x0 0.--1. "TX_RATE,Value from ASIC for tx_rate (RU - read-only volatile)" "0,1,2,3" rgroup.word 0x1024++0x1 line.word 0x0 "LANE0_DIG_TX_ASIC_DRV_LO,Current values for incoming TX level controls from ASIC" newline bitfld.word 0x0 14.--15. "RESERVED_15_14,Reserved for Future use" "0,1,2,3" newline hexmask.word.byte 0x0 7.--13. 1. "PREEMPH,Value from ASIC for tx_preemph (RU - read-only volatile)" newline hexmask.word.byte 0x0 0.--6. 1. "AMPLITUDE,Value from ASIC for tx_amplitude (RU - read-only volatile)" rgroup.word 0x1028++0x1 line.word 0x0 "LANE0_DIG_TX_ASIC_DRV_HI,Current values for incoming TX level controls from ASIC" newline hexmask.word 0x0 5.--15. 1. "RESERVED_15_5,Reserved for Future use" newline hexmask.word.byte 0x0 0.--4. 1. "TERM_OFFSET,Value from ASIC for tx_term_offset (RU - read-only volatile)" rgroup.word 0x102C++0x1 line.word 0x0 "LANE0_DIG_TX_ASIC_OUT,Current values for outgoing TX status controls from PHY" newline hexmask.word 0x0 5.--15. 1. "RESERVED_15_5,Reserved for Future use" newline bitfld.word 0x0 4. "STATE,Value from PHY for tx_state (RU - read-only volatile)" "0,1" newline bitfld.word 0x0 3. "CM_STATE,Value from PHY for tx_cm_state (RU - read-only volatile)" "0,1" newline bitfld.word 0x0 2. "DETECT_RX_ACK,Value from PHY for tx_detect_rx_ack (RU - read-only volatile)" "0,1" newline bitfld.word 0x0 1. "RESERVED,Always returns 0 (RU - read-only volatile)" "0,1" newline bitfld.word 0x0 0. "DETECT_RX_RES,Value from PHY for tx_detect_rx_res (RU - read-only volatile)" "0,1" rgroup.word 0x1030++0x1 line.word 0x0 "LANE0_DIG_RX_ASIC_IN,Current values for incoming RX controls from ASIC" newline bitfld.word 0x0 15. "RX_EQ_EN,Value from ASIC for rx_eq_en (RU - read-only volatile)" "0,1" newline bitfld.word 0x0 12.--14. "RX_EQ,Value from ASIC for rx_eq (RU - read-only volatile)" "0,1,2,3,4,5,6,7" newline bitfld.word 0x0 10.--11. "LOS_FILTER,Value from ASIC for rx_los_filter (RU - read-only volatile)" "0,1,2,3" newline bitfld.word 0x0 9. "LOS_EN,Value from ASIC for rx_los_en (RU - read-only volatile)" "0,1" newline bitfld.word 0x0 8. "TERM_EN,Value from ASIC for rx_term_en (RU - read-only volatile)" "0,1" newline bitfld.word 0x0 7. "CLK_SHIFT,Value from ASIC for rx_bit_shift (RU - read-only volatile)" "0,1" newline bitfld.word 0x0 6. "ALIGN_EN,Value from ASIC for rx_align_en (RU - read-only volatile)" "0,1" newline bitfld.word 0x0 5. "DATA_EN,Value from ASIC for rx_data_en (RU - read-only volatile)" "0,1" newline bitfld.word 0x0 4. "PLL_EN,Value from ASIC for rx_pll_en (RU - read-only volatile)" "0,1" newline bitfld.word 0x0 3. "RX_RESET,Value from ASIC for rx_reset (RU - read-only volatile)" "0,1" newline bitfld.word 0x0 2. "INVERT,Value from ASIC for rx_invert (RU - read-only volatile)" "0,1" newline bitfld.word 0x0 0.--1. "RX_RATE,Value from ASIC for rx_rate (RU - read-only volatile)" "0,1,2,3" rgroup.word 0x1034++0x1 line.word 0x0 "LANE0_DIG_RX_ASIC_OUT,Current values for outgoing RX status controls from PHY" newline hexmask.word 0x0 3.--15. 1. "RESERVED_15_3,Reserved for Future use" newline bitfld.word 0x0 2. "LOS,Value from PHY for rx_los (RU - read-only volatile)" "0,1" newline bitfld.word 0x0 1. "PLL_STATE,Value from PHY for rx_pll_state (RU - read-only volatile)" "0,1" newline bitfld.word 0x0 0. "VALID,Value from PHY for rx_valid (RU - read-only volatile)" "0,1" group.word 0x1040++0x1 line.word 0x0 "LANE0_DIG_TX_DEBUG,Transmit debug controls" newline rbitfld.word 0x0 13.--15. "RESERVED_15_13,Reserved for Future use" "0,1,2,3,4,5,6,7" newline bitfld.word 0x0 12. "KEEP_TX_REFGEN,Keep TX voltage regulator ON until TX clocks are OFF" "0,1" newline hexmask.word.byte 0x0 4.--11. 1. "RXDET_MEAS_TIME,Time to wait for rxdet measurement (* 4/2/1 refclk cycles based on multiplier)" newline bitfld.word 0x0 3. "DETECT_RX_ALWAYS,Always signal 1 for rx_detect ignoring analog" "0,1" newline bitfld.word 0x0 0.--2. "DTB_SEL,Selects data to drive on DTB 0 - disabled 1 - mag_update/sub signals 2 - mag_high/add signals 3 - clock aligner early/shift signals 4 - analog/asic clocks 5 - tx_state counter/lbert strobe 6 - noclk_ref_rst/dig_rst 7 -.." "disabled,mag_update/sub signals,mag_high/add signals,clock aligner early/shift signals,analog/asic clocks,tx_state counter/lbert strobe,noclk_ref_rst/dig_rst,tx_ana_rxdetp_high/tx_ana_rxdetm_high" group.word 0x1044++0x1 line.word 0x0 "LANE0_DIG_TX_CM_WAIT_TIME_OVRD,USB3_LANE0_DIG_TX_CM_WAIT_TIME_OVRD" newline hexmask.word.byte 0x0 11.--15. 1. "RESERVED_15_11,Reserved for Future use" newline bitfld.word 0x0 10. "CM_TIME_OVRD_EN,Override enable for common mode charging wait time." "0,1" newline hexmask.word 0x0 0.--9. 1. "CM_TIME_OVRD,Time to wait in ref clock cycles for LFPS common mode charging (This value x32 is used for VCMHOLD charging method)" rgroup.word 0x1048++0x1 line.word 0x0 "LANE0_DIG_TX_VMD_FSM_TX_VCM_0,Calculated values for N_USE and N_TRISTATE. Also TX ANA configuration shift register output." newline bitfld.word 0x0 15. "SHIFT_OUT,Current value from TX_ANAs configuration shift register. (RU - read-only volatile)" "0,1" newline bitfld.word 0x0 14. "DONE,Configuration is done (RU - read-only volatile)" "0,1" newline hexmask.word.byte 0x0 7.--13. 1. "N_USE,Value from VMD for legs to use. (RU - read-only volatile)" newline hexmask.word.byte 0x0 0.--6. 1. "N_TRISTATE,Value from VMD for number of tristate legs. (RU - read-only volatile)" rgroup.word 0x104C++0x1 line.word 0x0 "LANE0_DIG_TX_VMD_FSM_TX_VCM_1,Calculated values for N_FIXED and N_TRAILER." newline bitfld.word 0x0 15. "FIXED_DONE,N_FIXED Multiplication has completed. (RU - read-only volatile)" "0,1" newline bitfld.word 0x0 14. "TRA_DONE,N_TRAILER Multiplication has completed. (RU - read-only volatile)" "0,1" newline hexmask.word.byte 0x0 7.--13. 1. "N_FIXED,Value from VMD for number of fixed driver legs. (RU - read-only volatile)" newline hexmask.word.byte 0x0 0.--6. 1. "N_TRAILER,Value from VMD for number of trailer legs. (RU - read-only volatile)" group.word 0x1050++0x1 line.word 0x0 "LANE0_DIG_TX_VMD_FSM_TX_VCM_DEBUG_IN,Access the TX_ANA VMD Control Shift Register" newline hexmask.word 0x0 4.--15. 1. "RESERVED_15_4,Reserved for Future use" newline bitfld.word 0x0 3. "CONFIG_OVRD,Override the Voltage Mode Driver Configuration FSM and access the shift chain directly. (volatile and 2 reads needed to read value)" "0,1" newline bitfld.word 0x0 2. "CONFIG_LOAD,Override value for the Voltage Mode Driver Configuration FSM's config load. (volatile and 2 reads needed to read value)" "0,1" newline bitfld.word 0x0 1. "CONFIG_CLK,Override value for the Voltage Mode Driver Configuration FSM's config clk. (volatile and 2 reads needed to read value)" "0,1" newline bitfld.word 0x0 0. "CONFIG_DATA,Override value for the Voltage Mode Driver Configuration FSM's config data. (volatile and 2 reads needed to read value)" "0,1" group.word 0x1054++0x1 line.word 0x0 "LANE0_DIG_TX_LBERT_CTL,Pattern Generator controls" newline rbitfld.word 0x0 15. "RESERVED_15_15,Reserved for Future use" "0,1" newline hexmask.word 0x0 5.--14. 1. "PAT0,10 bit pattern for modes using PAT0 (5-7). Ignored for other MODEs." newline bitfld.word 0x0 4. "TRIGGER_ERR,Single shot inversion the LSB of the current symbol. Any write of a 1 to this bit will insert an error. Maintain mode and pattern from setup." "0,1" newline hexmask.word.byte 0x0 0.--3. 1. "MODE,Pattern to generate When changing modes you must change to disabled first 0 - disabled 1 - lfsr31. X^31 + X^28 + 1 2 - lfsr23. X^23 + X^18 + 1 3 - lfsr15. X^15 + X^14 + 1 4 - lfsr7. X^7 + X^6 + 1 5 - fixed word (PAT0) 6 - DC balanced word (PAT0.." group.word 0x1058++0x1 line.word 0x0 "LANE0_DIG_RX_LBERT_CTL,Pattern Matcher controls" newline hexmask.word 0x0 5.--15. 1. "RESERVED_15_5,Reserved for Future use" newline bitfld.word 0x0 4. "SYNC,Synchronize pattern matcher with incoming data A write of a one to this bit will reset the error counter and start a synchronization of the PM. There is no need to write this back to zero to run normally." "0,1" newline hexmask.word.byte 0x0 0.--3. 1. "MODE,Pattern to match When changing modes you must change to disabled first 0 - disabled 1 - lfsr31: X^31 + X^28 + 1 2 - lfsr23: X^23 + X^18 + 1 3 - lfsr15: X^15 + X^14 + 1 4 - lfsr7 : X^7 + X^6 + 1 5 - d[n] = d[n-10] 6 - d[n] = !d[n-10] 7 - d[n] =.." group.word 0x105C++0x1 line.word 0x0 "LANE0_DIG_RX_LBERT_ERR,Pattern match error counter" newline bitfld.word 0x0 15. "OV14,A read of this register or a sync of the Pattern Matcher resets the error count. If all bits of this register are 1 the error counter has saturated. If the status If active multiply COUNT by 128. If OV14=1 and COUNT=2^15-1 signals overflow of.." "0,1" newline hexmask.word 0x0 0.--14. 1. "COUNT,Current error count If OV14 field is active then multiply count by 128 to get the actual count. (volatile and 2 reads needed to read value)" group.word 0x1060++0x1 line.word 0x0 "LANE0_DIG_RX_SCOPE_CTL,Control bits for per-transciever scope portion" newline rbitfld.word 0x0 14.--15. "RESERVED_15_14,Reserved for Future use" "0,1,2,3" newline bitfld.word 0x0 12.--13. "RX_VALID_CTL,When to Start Sampling control based on rx_valid. 0 = Ignore rx_valid. 1 = Heed rx_valid. 2 = Wait for rising_edge on rx_valid." "Ignore rx_valid,Heed rx_valid,Wait for rising_edge on rx_valid,?" newline hexmask.word 0x0 3.--11. 1. "DELAY,number of cycles to skip between samples" newline bitfld.word 0x0 0.--2. "MODE,sampling mode of counters NOTE: WORD is 20 bits. 0 = off 1 = sample data every WORD*(1+DELAY) bits from the digital recovered path. 2 = sample data every WORD*(1+DELAY) + 1 bits from the digital recovered path. 3 = sample data every WORD*(1+DELAY) +.." "off,sample data every WORD*,sample data every WORD*,sample data every WORD*,sample data every WORD*,?,?,?" group.word 0x1064++0x1 line.word 0x0 "LANE0_DIG_RX_SCOPE_PHASE,Scope sampling phase." newline rbitfld.word 0x0 15. "RESERVED_15_15,Reserved for Future use" "0,1" newline hexmask.word.byte 0x0 10.--14. 1. "BASE,which bit to sample when MODE = 1 or 4" newline bitfld.word 0x0 8.--9. "SCOPE_DELAY,How many clocks to delay the analog scope_data." "0,1,2,3" newline bitfld.word 0x0 7. "SCOPE_SEL,Select Sampling Mode. 0 - Before AFE Sampling 1 - After AFE Sampling" "Before AFE Sampling,After AFE Sampling" newline bitfld.word 0x0 6. "UPDATE,Update Sampling phase. Write a 1." "0,1" newline hexmask.word.byte 0x0 0.--5. 1. "SAMPLE_PHASE,Sampling Phase" group.word 0x1068++0x1 line.word 0x0 "LANE0_DIG_RX_DPLL_FREQ,Current frequency integrator value." newline rbitfld.word 0x0 13.--15. "RESERVED_15_13,Reserved for Future use" "0,1,2,3,4,5,6,7" newline hexmask.word 0x0 1.--12. 1. "VAL,Freq is 1.526*VAL ppm from the reference When mpll_slow is set the ppm is half the eqn above (volatile and 2 reads needed to read value)" newline bitfld.word 0x0 0. "DTHR,Bits below the useful resolution (volatile and 2 reads needed to read value)" "0,1" group.word 0x106C++0x1 line.word 0x0 "LANE0_DIG_RX_CDR_CTL,Control bits for receiver in recovered domain" newline hexmask.word.byte 0x0 12.--15. 1. "DTB_SEL,select to drive various signals onto the dtb 0 - disabled 1 - pll_ana_rst pll_count from rx_pwr_ctl 2 - com_good_high/low from aligner 3 - com_bad_high/low from aligner 4 - shift_in_prog ana_odd_data from aligner 5 - low bits of XAUI align FSM.." newline bitfld.word 0x0 11. "ALWAYS_REALIGN,realign on any misaligned comma" "0,1" newline bitfld.word 0x0 10. "FAST_START,decrease startup steps by 50%" "0,1" newline bitfld.word 0x0 8.--9. "FRUG_VALUE,override value for FRUG" "0,1,2,3" newline bitfld.word 0x0 6.--7. "PHUG_VALUE,override value for PHUG" "0,1,2,3" newline bitfld.word 0x0 5. "OVRD_DPLL_GAIN,Override PHUG and FRUG values" "0,1" newline bitfld.word 0x0 4. "PHDET_POL,Reverse polarity of phase error" "0,1" newline bitfld.word 0x0 2.--3. "PHDET_EDGE,Edges to use for phase detection. 11 - Use both edges 10 - Use rising edges only 01 - Use falling edges only 00 - Ignore all edges" "Ignore all edges,Use falling edges only,?,?" newline bitfld.word 0x0 0.--1. "PHDET_EN,Enable phase detecter. top bit is odd slicers bottom is even" "0,1,2,3" rgroup.word 0x1070++0x1 line.word 0x0 "LANE0_DIG_RX_CDR_CDR_FSM_DEBUG,Current values for CDR and Adaptation FSM." newline bitfld.word 0x0 13.--15. "ADAP_RX_EQ,Equalization setting from adaptation FSM. (RU - read-only volatile)" "0,1,2,3,4,5,6,7" newline bitfld.word 0x0 10.--12. "RX_EQ_CTR,Initial centre point from equalization FSM. (RU - read-only volatile)" "0,1,2,3,4,5,6,7" newline bitfld.word 0x0 7.--9. "RX_ANA_EQ,Equalization setting to Analog. (RU - read-only volatile)" "0,1,2,3,4,5,6,7" newline bitfld.word 0x0 6. "ADAP_RX_VALID,Adaptation has completed and locked. (RU - read-only volatile)" "0,1" newline bitfld.word 0x0 5. "CDR_EN_ADAP,Adapatation loop is enabling the CDR. (RU - read-only volatile)" "0,1" newline bitfld.word 0x0 4. "CDR_EN_EQ,Equalization loop is enabling the CDR. (RU - read-only volatile)" "0,1" newline bitfld.word 0x0 3. "ALIGNED,Datapath is bit-aligned. (RU - read-only volatile)" "0,1" newline bitfld.word 0x0 2. "CDR_RX_VALID,CDR has locked to incoming data stream. (RU - read-only volatile)" "0,1" newline bitfld.word 0x0 1. "CDR_TIMEOUT,CDR has not locked to datastream and has timed-out. (RU - read-only volatile)" "0,1" newline bitfld.word 0x0 0. "CDR_EN,CDR has been enabled. (RU - read-only volatile)" "0,1" group.word 0x1074++0x1 line.word 0x0 "LANE0_DIG_RX_CDR_LOCK_VEC_OVRD,Control bits for receiver in recovered domain" newline hexmask.word.byte 0x0 11.--15. 1. "ADAP_CTR_LEVEL,Ammount of earlies that increment the adaptation counter (times 32 Default is 512). (volatile and 2 reads needed to read value)" newline bitfld.word 0x0 10. "ADAP_POLARITY,If asserted invert default adaptation adjustment for equalization. IF early decrease equalization. Normal mode is to decrease. (volatile and 2 reads needed to read value)" "0,1" newline bitfld.word 0x0 9. "LOCK_VECTOR_OVRD,Override enable for the rx_eq outputs. (volatile and 2 reads needed to read value)" "0,1" newline bitfld.word 0x0 8. "LOCK_VECTOR_EN,Override value for the locked_vector output completion. (volatile and 2 reads needed to read value)" "0,1" newline hexmask.word.byte 0x0 0.--7. 1. "LOCK_VECTOR,Override value for the locked_vector. (volatile and 2 reads needed to read value)" rgroup.word 0x1078++0x1 line.word 0x0 "LANE0_DIG_RX_CDR_LOCK_VEC,Current values for the locked vector.." newline hexmask.word.byte 0x0 12.--15. 1. "RESERVED_15_12,Reserved for Future use" newline bitfld.word 0x0 9.--11. "EQ_RX_EQ,Equalization setting from the Equalization Loop. (RU - read-only volatile)" "0,1,2,3,4,5,6,7" newline bitfld.word 0x0 8. "EQ_LOCKED_VECTOR_EN,Equalization locked vector has been filled. (RU - read-only volatile)" "0,1" newline hexmask.word.byte 0x0 0.--7. 1. "EQ_LOCKED_VECTOR,Results of equalization loop. (RU - read-only volatile)" rgroup.word 0x107C++0x1 line.word 0x0 "LANE0_DIG_RX_CDR_ADAP_FSM,Observation of adaptation FSM register." newline hexmask.word.byte 0x0 11.--15. 1. "MSTR_CTR,Master count register. (RU - read-only volatile)" newline hexmask.word.byte 0x0 7.--10. 1. "LOOP_CTR,Loop count register. (RU - read-only volatile)" newline hexmask.word.byte 0x0 3.--6. 1. "ADAP_CTR,Adaptation count register. (RU - read-only volatile)" newline bitfld.word 0x0 0.--2. "ADAP_STATE,Adaptation State. NOTE: ADAP_RESET = 3'b000 ADAP_LOCK = 3'b001 ADAP_SUFF = 3'b010 ADAP_LOOP = 3'b011 ADAP_MSTR = 3'b100 ADAP_DONE = 3'b101 (RU - read-only volatile)" "0,1,2,3,4,5,6,7" group.word 0x1080++0x1 line.word 0x0 "LANE0_ANA_RX_ATB0,ATB Control Register" newline hexmask.word.byte 0x0 8.--15. 1. "RESERVED_15_8,Reserved for Future use" newline bitfld.word 0x0 7. "EN_ATB,Enable ATB sensing and forcing on internal RX nodes" "0,1" newline bitfld.word 0x0 6. "EN_MARG,Enable margining mode in receiver; it puts EQ common mode output on atb_f_m" "0,1" newline bitfld.word 0x0 5. "EN_ATB_RM_F,Enable atb_f_p on negative-side termination resistor" "0,1" newline bitfld.word 0x0 4. "EN_ATB_RM_S,Enable atb_s_m on negative-side termination resistor" "0,1" newline bitfld.word 0x0 3. "EN_ATB_RP_F,Enable atb_f_p on positive-side termination resistor" "0,1" newline bitfld.word 0x0 2. "EN_ATB_RP_S,Enable atb_s_p on positive-side termination resistor" "0,1" newline bitfld.word 0x0 1. "EN_ATB_VOS,Put rxafe filtered outputs vo_p on atb_s_p and vo_m on atb_s_m" "0,1" newline bitfld.word 0x0 0. "EN_ATB_VOFF,Put rxafe voff_p on atb_s_p and voff_m on atb_s_m" "0,1" group.word 0x1084++0x1 line.word 0x0 "LANE0_ANA_RX_ATB1,ATB and Misc Control Register" newline hexmask.word.byte 0x0 8.--15. 1. "RESERVED_15_8,Reserved for Future use" newline bitfld.word 0x0 6.--7. "RX_DCC_IQ_OFFSET_H_4_3,Code which helps to manually tune reference voltage (r-string dac) for IQ opamp and correct input offset (rx_dcc_iq_offset_h_4_3 bit)" "0,1,2,3" newline bitfld.word 0x0 5. "EN_ATB_VLOS,Enable sensing of LOS reference voltage on atb_s_p" "0,1" newline bitfld.word 0x0 4. "EN_ATB_VRF,Enable sensing of vref_rx (RX Bias B.G. Voltage) on atb_s_p" "0,1" newline bitfld.word 0x0 3. "MEAS_GD,Enable sensing of local gd in RX; ties gd to atb_s_m" "0,1" newline bitfld.word 0x0 2. "MEAS_VP,Enable sensing of local vp in RX; ties vp to atb_s_p" "0,1" newline bitfld.word 0x0 0.--1. "RX_DCC_IQ_OFFSET_H_2_1,Code which helps to manually tune reference voltage (r-string dac) for IQ opamp and correct input offset (rx_dcc_iq_offset_h_2_1 bit)" "0,1,2,3" group.word 0x1088++0x1 line.word 0x0 "LANE0_ANA_RX_ENPWR0,RX State Control Register" newline hexmask.word.byte 0x0 8.--15. 1. "RESERVED_15_8,Reserved for Future use" newline bitfld.word 0x0 7. "CTL_RXPWRON,MUX select for AFE en to select between CTL_RXPWRON=0 rx_afe_en (External signal) or CTL_RXPWRON=1 LCL_RXPWRON" "0,1" newline bitfld.word 0x0 6. "LCL_RXPWRON,Enable/Disable RX AFE .This bit is only selected when CTL_RXPWRON = 1" "0,1" newline bitfld.word 0x0 5. "CTL_EN_LOS,MUX select for LOS en to select between CTL_EN_LOS=0 rx_los_en (External signal) or CTL_EN_LOS=1 LCL_EN_LOS" "0,1" newline bitfld.word 0x0 4. "LCL_EN_LOS,Enable/Disable LOS.This bit is only selected when CTL_EN_LOS = 1" "0,1" newline bitfld.word 0x0 3. "CTL_RXCK,MUX select for RX Clock en to select between CTL_RXCK=0 rx_clock_en (External signal) or CTL_RXCK=1 LCL_RXCK." "0,1" newline bitfld.word 0x0 2. "LCL_RXCK,Enable/Disable en_rx_clock (RX clock enable).This bit is only selected when CTL_RXCK = 1" "0,1" newline bitfld.word 0x0 1. "CTL_ACJT,MUX select for ACJTAG to select between CTL_ACJTG=0 rx_acjtg_en (External signal) or CTL_ACJTG=1 LCL_ACJT." "0,1" newline bitfld.word 0x0 0. "LCL_ACJT,Enable/Disable acjtag block This bit is only selected when CTL_ACJTG = 1" "0,1" group.word 0x108C++0x1 line.word 0x0 "LANE0_ANA_RX_PMIX_PHASE,Phase select Value" newline hexmask.word.byte 0x0 8.--15. 1. "RESERVED_15_8,Reserved for Future use" newline hexmask.word.byte 0x0 0.--7. 1. "PHASE,Write to bits 8 to 1 of the phase select register in the phase mixer through the CDR (USER2 volatile - read-write volatile and custom)" group.word 0x1090++0x1 line.word 0x0 "LANE0_ANA_RX_ENPWR1,Additional RX State Control Register" newline hexmask.word.byte 0x0 8.--15. 1. "RESERVED_15_8,Reserved for Future use" newline bitfld.word 0x0 7. "CTL_PHASE_REG_RST,MUX select for Phase Register Reset to select between CTL_PHASE_REG_RST=0 rx_phase_reg_rst (External signal) or CTL_PHASE_REG_RST=1 LCL_PHASE_REG_RST" "0,1" newline bitfld.word 0x0 6. "LCL_PHASE_REG_RST,Reset phase register.This bit is only selected when CTL_PHASE_REG_RST= 1" "0,1" newline bitfld.word 0x0 5. "CTL_BST,MUX select for AFE Boost to select between CTL_BST=0 rx_aeq[2:0] (External signal) or CTL_BST=1 LCL_BST" "0,1" newline bitfld.word 0x0 2.--4. "LCL_BST,RX Boost (equalization) Value" "0,1,2,3,4,5,6,7" newline bitfld.word 0x0 1. "CTL_RXTERM,MUX select for RX Term enable to select between CTL_RXTERM=0 rx_term_en (External signal) or CTL_RXTERM=1 LCL_RXTERM" "0,1" newline bitfld.word 0x0 0. "LCL_RXTERM,Enable/disable RX termination when CTL_RXTERM = 1" "0,1" group.word 0x1094++0x1 line.word 0x0 "LANE0_ANA_RX_ENPWR2,Yet another RX State Control Register" newline hexmask.word.byte 0x0 8.--15. 1. "RESERVED_15_8,Reserved for Future use" newline bitfld.word 0x0 7. "EN_RXPMIX_TST,Enable XOR gate to test linearity of RX phase mixer using atb_s_p and atb_s_m" "0,1" newline bitfld.word 0x0 6. "EN_RXPMIX_VPMIX,Put vreg_pmix on atb_s_p" "0,1" newline bitfld.word 0x0 5. "EN_RXPMIX_VRX,Put vreg_rx on atb_s_p" "0,1" newline bitfld.word 0x0 4. "RX_DCC_IQ_OFFSET_H_0,Code which helps to manually tune reference voltage (r-string dac) for IQ opamp and correct input offset (rx_dcc_iq_offset_h_0 bit)" "0,1" newline bitfld.word 0x0 3. "EN_RXPMIX_FRC_VPMIX_H,Connecting vbg_in to vbg (in case of 0) or to atb_s_m_int (in case of 1)" "0,1" newline bitfld.word 0x0 2. "RX_SCOPE_ATB_2,Put XOR of RX SCOPE PMIX input and output on atb_s_p" "0,1" newline bitfld.word 0x0 1. "RX_SCOPE_ATB_1,Put RX SCOPE regulated VP on atb_s_p" "0,1" newline bitfld.word 0x0 0. "RX_SCOPE_ATB_0,Have RX SCOPE reference for regulator use atb_f_p as a reference instead of VP/VBG" "0,1" group.word 0x1098++0x1 line.word 0x0 "LANE0_ANA_RX_SCOPE_VDCC,RX Scope controls and clock DCC control voltage probe" newline hexmask.word.byte 0x0 8.--15. 1. "RESERVED_15_8,Reserved for Future use" newline bitfld.word 0x0 6.--7. "VDCC,Probe DCC control voltage" "0,1,2,3" newline bitfld.word 0x0 5. "NC5,Reserved" "0,1" newline bitfld.word 0x0 4. "RX_SCOPE_SLEW,Set high for low RX clock frqeuencies (625MHz) for RX Scope to work correctly" "0,1" newline bitfld.word 0x0 3. "RX_SCOPE_FDIV20,Divide scope output clock by 20 instead of 10" "0,1" newline bitfld.word 0x0 2. "RX_LOS_LFPS_EN_BIT_2,In case of rx_los_lfps_en_cntrl = 1/0 reg_rx_los_lfps_en/rx_ana_los_lfps_en signal directly applied to rx_los circuit through I101 multiplexer." "0,1" newline bitfld.word 0x0 1. "RX_DCC_IQ_OFFSET_EN_H,Select ref voltage for IQ opamp from testmode part (in case of 1) or from ordinary resistive dividers (in case of 0)." "0,1" newline bitfld.word 0x0 0. "RX_LOS_LFPS_EN,Enables the RX LOS LFPS mode use when you want to detect incoming LFPS signals USB3.0" "0,1" group.word 0x10AC++0x1 line.word 0x0 "LANE0_ANA_TX_TXDRV_CNTRL,Register 3" newline hexmask.word.byte 0x0 8.--15. 1. "RESERVED_15_8,Reserved for Future use" newline bitfld.word 0x0 7. "PULL_DN_REG,register bit that causes the calibrated TX bits to pull down in a common mode fashion. If pull_dn_reg and tx_pull_up are both high then pull_dn_reg wins" "0,1" newline bitfld.word 0x0 6. "PULL_UP_REG,Register override for tx_pull_up. Used when ovrd_pull_up is HIGH causes calibrated TX bits to pull up in a common mode fashion unless pull_dn_reg is HIGH" "0,1" newline bitfld.word 0x0 5. "OVRD_PULL_UP,Selects local value of pull_up_reg instead of tx_pull_up" "0,1" newline bitfld.word 0x0 4. "VCM_HOLD_REG,Register override for tx_vcm_hold. Used when ovrd_vcm_hold is HIGH controls the TX common mode hold circuitry" "0,1" newline bitfld.word 0x0 3. "OVRD_VCM_HOLD,Selects local value of vcm_hold_reg instead of tx_vcm_hold to control state of TX common mode hold circuitry" "0,1" newline bitfld.word 0x0 2. "REFGEN_PWRDN_OVRD_N,Set LOW for TX regulator not to turn on when RX clock is enabled. Default is for TX regulator to turn on when RX or TX clock is enabled" "0,1" newline bitfld.word 0x0 1. "NOCONN_1,Reserved" "0,1" newline bitfld.word 0x0 0. "NOCONN_0,Reserved" "0,1" group.word 0x10B0++0x1 line.word 0x0 "LANE0_ANA_TX_POWER_CTL,Register 4" newline hexmask.word.byte 0x0 8.--15. 1. "RESERVED_15_8,Reserved for Future use" newline bitfld.word 0x0 7. "OVRD_EN,Enables local overrides for all signals in this register except for TX_DIV_CLK_EN which doesn't need this signal" "0,1" newline bitfld.word 0x0 6. "SERIAL_EN_REG,Forces state of tx_serial_en when OVRD_EN is 1" "0,1" newline bitfld.word 0x0 5. "CLK_EN_REG,Forces state of tx_clk_en when OVRD_EN is 1" "0,1" newline bitfld.word 0x0 4. "DATA_EN_REG,Forces state of tx_data_en when OVRD_EN is HIGH" "0,1" newline bitfld.word 0x0 3. "REFGEN_EN_REG,Register override value for tx_refgen_en. Controls the TX regulator biasing circuitry and the rxdetect comparators when OVRD_EN is HIGH. This function may be overridden by the state of refgen_pwdn_reg" "0,1" newline bitfld.word 0x0 2. "TX_DIV_CLK_EN,Enables the div clock that goes from the TX to the undersampler more appropriately called tx_sampler_clk_en this clock comes after the optional divide by 2 or 4 tx_clk_en must be HIGH to get a clock out" "0,1" newline bitfld.word 0x0 1. "REFGEN_PDN_REG,Register override for refgen pwdn. Used when OVRD_EN is HIGH. Controls the TX regulator biasing circuitry and the rxdetect comparators when OVRD_EN is HIGH" "0,1" newline bitfld.word 0x0 0. "LFPS_HIGH_PRIORITY,When this is set high LFPS priority becomes higher than tx_data" "0,1" group.word 0x10B4++0x1 line.word 0x0 "LANE0_ANA_TX_ALT_BLOCK,Register 5" newline hexmask.word.byte 0x0 8.--15. 1. "RESERVED_15_8,Reserved for Future use" newline bitfld.word 0x0 7. "EN_ALT_BUS,Enables the TX for alt bus mode powers up the TX regulator biasing circuitry and the rxdetect comparators. Needed if manually running the alt bus features" "0,1" newline bitfld.word 0x0 5.--6. "DRV_SOURCE_REG,Forces state of tx_data_source when OVRD_ALT_BUS is HIGH. 00 = serializer data or alt oscillator vp/vph/vphreg/vptx if selected 01 = jtag data differential 10 = LFPS oscillator differential 11 = jtag data common mode drive for test" "serializer data or alt oscillator..,jtag data differential,?,?" newline bitfld.word 0x0 4. "JTAG_DATA_REG,Forces state of jtag_data when OVRD_ALT_BUS is HIGH" "0,1" newline bitfld.word 0x0 1.--3. "TX_RINGO_CNTRL,Enables and connects the various test oscillators to the transmit pins must set drv_source_reg bus correctly. 0XX = All oscillators are disabled 100 = HV oscillator enabled 101 = SVT oscillator enabled 110 = LVT oscillator enabled 111.." "0,1,2,3,4,5,6,7" newline bitfld.word 0x0 0. "OVRD_ALT_BUS,Enables local overrides for alt-bus control signals: DRV_SOURCE_REG and JTAG_DATA_REG" "0,1" group.word 0x10B8++0x1 line.word 0x0 "LANE0_ANA_TX_ALT_AND_LOOPBACK,Register 6" newline hexmask.word.byte 0x0 8.--15. 1. "RESERVED_15_8,Reserved for Future use" newline bitfld.word 0x0 7. "OVRD_TX_LB,Enables the override of the tx_lb_en" "0,1" newline bitfld.word 0x0 6. "TX_LB_EN_REG,Forces state of tx_lb_en when OVRD_TX_LB is enabled" "0,1" newline bitfld.word 0x0 5. "ATB_VPTX,Connects vptx to atb_s_p and gd to atb_s_m" "0,1" newline bitfld.word 0x0 4. "ATB_VREG_TX,Connects TX regulator input reference to atb_s_p and gd to atb_s_m" "0,1" newline bitfld.word 0x0 3. "ATB_VDCCP,Connects vdcc_p to atb_s_p" "0,1" newline bitfld.word 0x0 2. "ATB_VDCCM,Connects vdcc_m to atb_s_m" "0,1" newline bitfld.word 0x0 1. "NOCONN_01,Reserved" "0,1" newline bitfld.word 0x0 0. "SELECT_PMIX_CLK,select pmix_clk for TX clock for ATE test mode" "0,1" group.word 0x10BC++0x1 line.word 0x0 "LANE0_ANA_TX_TX_ATB_REG,Register 7" newline hexmask.word.byte 0x0 8.--15. 1. "RESERVED_15_8,Reserved for Future use" newline bitfld.word 0x0 7. "ATB_PBIAS,Connect real pmos_bias voltage for TX PMOS driver pull up path to atb_s_p and local ground at the pmos_bias block to atb_s_m" "0,1" newline bitfld.word 0x0 6. "ATB_VCM_REP,Connect common mode replica voltage in pmos_bias block to atb_s_p and local ground to atb_s_m" "0,1" newline bitfld.word 0x0 5. "ATB_RXDETREF,Connect RX detect block reference voltage to atb_s_p and local ground to atb_s_m" "0,1" newline bitfld.word 0x0 4. "ATB_TXFP,Connect tx_p to atb_f_p" "0,1" newline bitfld.word 0x0 3. "ATB_TXFM,Connect tx_m to atb_f_m" "0,1" newline bitfld.word 0x0 2. "ATB_TXSP,Connect tx_p to atb_s_p" "0,1" newline bitfld.word 0x0 1. "ATB_TXSM,Connect tx_m to atb_s_m" "0,1" newline bitfld.word 0x0 0. "ATB_VCM,Connect tx_p/tx_m common mode voltage onto atb_s_p and local ground onto atb_s_m" "0,1" group.word 0x10C0++0x1 line.word 0x0 "LANE0_ANA_TX_TX_BOOST,Register 8" newline hexmask.word.byte 0x0 8.--15. 1. "RESERVED_15_8,Reserved for Future use" newline bitfld.word 0x0 7. "OVRD_VBOOST_EN,Enables the overrides on VBOOST_EN_REG" "0,1" newline bitfld.word 0x0 6. "VBOOST_EN_REG,Forces state of tx_vboost_en when OVRD_VBOOST_EN is HIGH" "0,1" newline bitfld.word 0x0 5. "VCON_EN_N,Forces state of vcon_en_n" "0,1" newline bitfld.word 0x0 4. "ATB_VBOOST,Connects vboost to atb_s_p and local ground to Atb_s_m" "0,1" newline bitfld.word 0x0 3. "ATB_VCMBOOST,Connects vcmboost to atb_s_p and local ground to atb_s_m." "0,1" newline bitfld.word 0x0 2. "ATB_F_VBOOST_REF,Enables forcing of tx_vboost_vref through atb_f_p from external" "0,1" newline bitfld.word 0x0 1. "OVRD_VREG_DECAP,Enables override of vreg_decap_en_n signal" "0,1" newline bitfld.word 0x0 0. "VREG_DECAP_EN_N_REG,Forces state of vreg_decap_en_n control signal. Controls whether extra decoupling is switched in for TX regulator output." "0,1" group.word 0x1100++0x1 line.word 0x0 "LANE0_DIG_RX_CDR_FSM_INIT_CTL,Control bits for CDR init phase portion" newline hexmask.word.byte 0x0 9.--15. 1. "RESERVED_15_9,Reserved for Future use" newline bitfld.word 0x0 8. "INIT_CNT_OVRD,Active high override enable bit to select the override INIT_CNT register 0 = Disabled 1 = Enabled" "Disabled,Enabled" newline hexmask.word.byte 0x0 0.--7. 1. "INIT_CNT,Override value for CDR Init Phase" group.word 0x1104++0x1 line.word 0x0 "LANE0_DIG_RX_CDR_FSM_TRACK_CTL,Control bits for CDR track phase portion" newline hexmask.word.byte 0x0 9.--15. 1. "RESERVED_15_9,Reserved for Future use" newline bitfld.word 0x0 8. "TRACK_CNT_OVRD,Active high override enable bit to select the override TRACK_CNT register 0 = Disabled 1 = Enabled" "Disabled,Enabled" newline hexmask.word.byte 0x0 0.--7. 1. "TRACK_CNT,Override value for CDR Track Phase" group.word 0x1108++0x1 line.word 0x0 "LANE0_DIG_RX_CDR_FSM_LOCK_CTL,Control bits for CDR lock phase portion" newline hexmask.word.byte 0x0 9.--15. 1. "RESERVED_15_9,Reserved for Future use" newline bitfld.word 0x0 8. "LOCK_CNT_OVRD,Active high override enable bit to select the override LOCK_CNT register 0 = Disabled 1 = Enabled" "Disabled,Enabled" newline hexmask.word.byte 0x0 0.--7. 1. "LOCK_CNT,Override value for CDR Lock Phase" repeat 9. (list 0x0 0x1 0x2 0x3 0x4 0x8 0x9 0xB 0xC )(list 0x0 0x4 0x8 0xC 0x10 0x20 0x24 0x2C 0x30 ) rgroup.word ($2+0x2000)++0x1 line.word 0x0 "PORT0_STAT_RO_$1,Status Register 0" newline hexmask.word 0x0 4.--15. 1. "RESERVED_15_4,Reserved for Future use" newline bitfld.word 0x0 3. "PLL_LOCK,analog PLL Lock Signal" "0,1" newline bitfld.word 0x0 2. "RX_SQUELCH,analog RX Squelch Signal" "0,1" newline bitfld.word 0x0 1. "RESERVED_1,Reserved" "0,1" newline bitfld.word 0x0 0. "RESERVED_0,Reserved" "0,1" repeat.end repeat 7. (list 0x5 0x6 0x7 0xA 0xD 0xE 0xF )(list 0x0 0x4 0x8 0x14 0x20 0x24 0x28 ) rgroup.word ($2+0x2014)++0x1 line.word 0x0 "PORT0_STAT_RO_$1,Status Register 5" newline hexmask.word 0x0 4.--15. 1. "RESERVED_15_4,Reserved for Future use" newline hexmask.word.byte 0x0 0.--3. 1. "DATAOUT,UTMI+ Output DATAOUT" repeat.end repeat 2. (list 0x0 0x6 )(list 0x0 0x18 ) group.word ($2+0x2040)++0x1 line.word 0x0 "PORT0_OVRD_RW_$1,Override Register 0" newline hexmask.word.byte 0x0 8.--15. 1. "RESERVED_15_8,Reserved for Future use" newline hexmask.word.byte 0x0 4.--7. 1. "OVERRD_ADDR_OVRD_EN,Override Enable for overrd_addr [7:4]" newline hexmask.word.byte 0x0 0.--3. 1. "OVERRD_ADDR,Analog Test Control Override Address [3:0]" repeat.end repeat 10. (list 0x1 0x2 0x3 0x4 0x8 0x9 0xA 0xB 0xE 0xF )(list 0x0 0x4 0x8 0xC 0x1C 0x20 0x24 0x28 0x34 0x38 ) group.word ($2+0x2044)++0x1 line.word 0x0 "PORT0_OVRD_RW_$1,Override Register 1" newline hexmask.word.byte 0x0 8.--15. 1. "RESERVED_15_8,Reserved for Future use" newline bitfld.word 0x0 7. "VBUS_VALID_PU_OVRD_EN,Override Enable for vbus_valid_pu" "0,1" newline bitfld.word 0x0 6. "OTG_PU_OVRD_EN,Override Enable for otg_pu" "0,1" newline bitfld.word 0x0 5. "TX_VREF_VREG_PU_OVRD_EN,Override Enable for tx_vref_vreg_pu" "0,1" newline bitfld.word 0x0 4. "SQRX_PU_OVRD_EN,Override Enable for sqrx_pu" "0,1" newline bitfld.word 0x0 3. "VBUS_VALID_PU,DRVVBUS Input" "0,1" newline bitfld.word 0x0 2. "OTG_PU,OTGDISABLE Input" "0,1" newline bitfld.word 0x0 1. "TX_VREF_VREG_PU,TX hs_driver Comparator Power Up" "0,1" newline bitfld.word 0x0 0. "SQRX_PU,RX squelch Comparator Power Up" "0,1" repeat.end group.word 0x2054++0x1 line.word 0x0 "PORT0_OVRD_RW_5,Override Register 5" newline hexmask.word.byte 0x0 8.--15. 1. "RESERVED_15_8,Reserved for Future use" newline bitfld.word 0x0 6.--7. "XO_CLK_DIV_OVRD_EN,Override Enable for xo_clk_div" "0,1,2,3" newline bitfld.word 0x0 5. "MSTR_OVERRD_BIT_OVRD_EN,Override Enable for mstr_overrd_bit" "0,1" newline bitfld.word 0x0 4. "OVERRD_ADDR_4_OVRD_EN,Override Enable for overrd_addr_4" "0,1" newline bitfld.word 0x0 2.--3. "XO_CLK_DIV,setting reference clock division" "0,1,2,3" newline bitfld.word 0x0 1. "MSTR_OVERRD_BIT,Analog Test Control Master Override" "0,1" newline bitfld.word 0x0 0. "OVERRD_ADDR_4,Analog Test Control Override Address [4]" "0,1" group.word 0x205C++0x1 line.word 0x0 "PORT0_OVRD_RW_7,Override Register 7" newline hexmask.word.byte 0x0 8.--15. 1. "RESERVED_15_8,Reserved for Future use" newline bitfld.word 0x0 7. "TX_LS_EN_OVRD_EN,Override Enable for tx_ls_en" "0,1" newline bitfld.word 0x0 4.--6. "PWR_SEQ_CLK_DIV_OVRD_EN,Override Enable for pwr_seq_clk_div" "0,1,2,3,4,5,6,7" newline bitfld.word 0x0 3. "TX_LS_EN,TX LS Enable" "0,1" newline bitfld.word 0x0 0.--2. "PWR_SEQ_CLK_DIV,setting power_sequence division" "0,1,2,3,4,5,6,7" group.word 0x2070++0x1 line.word 0x0 "PORT0_OVRD_RW_12,Override Register 12" newline hexmask.word.byte 0x0 8.--15. 1. "RESERVED_15_8,Reserved for Future use" newline bitfld.word 0x0 7. "RES_ACK_OUT_OVRD_EN,Override Enable for res_ack_out" "0,1" newline bitfld.word 0x0 5.--6. "PLL_CLK_DIV_OVRD_EN,Override Enable for pll_clk_div" "0,1,2,3" newline bitfld.word 0x0 4. "PLL_RESET_OVRD_EN,Override Enable for pll_reset" "0,1" newline bitfld.word 0x0 3. "RES_ACK_OUT,Ack resistor tune external requirement" "0,1" newline bitfld.word 0x0 1.--2. "PLL_CLK_DIV,setting MPLL division" "0,1,2,3" newline bitfld.word 0x0 0. "PLL_RESET,MPLL gear_shift" "0,1" group.word 0x2074++0x1 line.word 0x0 "PORT0_OVRD_RW_13,Override Register 13" newline hexmask.word.byte 0x0 8.--15. 1. "RESERVED_15_8,Reserved for Future use" newline bitfld.word 0x0 7. "BIST_MODE_OVRD_EN,Override Enable for bist_mode" "0,1" newline bitfld.word 0x0 6. "TEST_PKT_RPT_OVRD_EN,Override Enable for test_pkt_rpt" "0,1" newline bitfld.word 0x0 4.--5. "XO_CLK_SEL_OVRD_EN,Override Enable for xo_clk_sel" "0,1,2,3" newline bitfld.word 0x0 3. "BIST_MODE,BIST Mode" "0,1" newline bitfld.word 0x0 2. "TEST_PKT_RPT,BIST Test Packet Mode" "0,1" newline bitfld.word 0x0 0.--1. "XO_CLK_SEL,Reference Clock Selection" "0,1,2,3" rgroup.word 0x8000++0x1 line.word 0x0 "SUPX_DIG_IDCODE_LO,Low 16 bits of IDCODE" newline hexmask.word 0x0 0.--15. 1. "DATA," rgroup.word 0x8004++0x1 line.word 0x0 "SUPX_DIG_IDCODE_HI,High 16 bits of IDCODE" newline hexmask.word 0x0 0.--15. 1. "DATA," group.word 0x8008++0x1 line.word 0x0 "SUPX_DIG_DEBUG,Debug controls" newline hexmask.word 0x0 7.--15. 1. "RESERVED_15_7,Reserved for Future use" newline bitfld.word 0x0 5.--6. "DTB_SEL,The lane DTB's are OR'd together with the support DTB signals selected with the below encodings 0 - none 1 - reset_ctl DTB output 2 - scope DTB output 3 - rtune DTB output" "none,reset_ctl DTB output,scope DTB output,rtune DTB output" newline hexmask.word.byte 0x0 0.--4. 1. "TX_VREF_SEL," group.word 0x800C++0x1 line.word 0x0 "SUPX_DIG_RTUNE_DEBUG,Resistor tuning debug controls" newline rbitfld.word 0x0 15. "RESERVED_15_15,Reserved for Future use" "0,1" newline hexmask.word 0x0 5.--14. 1. "VALUE,Value to use when triggering SET_VAL field only the 6 LSB's are used when setting rx or tx cal values (USER2 - read-write and custom)" newline bitfld.word 0x0 3.--4. "TYPE,Type of manual tuning or register read/write to execute 0 - ADC or read/write rt_value 1 - Rx tune or read/write rx_cal_val (only 6 bits) 2 - Tx tune or read/write tx_cal_val (only 6 bits) 3 - Resref detect (no affect when triggering SET_VAL.." "ADC,Rx tune,read-write and custom),Resref detect" newline bitfld.word 0x0 2. "SET_VAL,Set value Write to a 1 to manually write the register specified by the TYPE field to the value in the VALUE field (USER2 - read-write and custom)" "0,1" newline bitfld.word 0x0 1. "MAN_TUNE,Write to a 1 to do a manual tuning specified by TYPE field starting a manual tune while a tune is currently running can cause unpredictable results. For use only when you know the state of the rtune circuit. (USER2 - read-write and custom)" "0,1" newline bitfld.word 0x0 0. "FLIP_COMP,Invert analog comparator output (USER2 - read-write and custom)" "0,1" rgroup.word 0x8010++0x1 line.word 0x0 "SUPX_DIG_RTUNE_STAT,Resistor tuning register status" newline hexmask.word.byte 0x0 10.--15. 1. "RESERVED_15_10,Reserved for Future use" newline hexmask.word 0x0 0.--9. 1. "STAT,Current value of the register specifed by the TYPE field in the debug control register. Set the TYPE field in the DEBUG register and then do a read of this register. (RU - read-only volatile)" group.word 0x8014++0x1 line.word 0x0 "SUPX_DIG_SS_PHASE,Current MPLL phase selector value" newline bitfld.word 0x0 13.--15. "REF_SEL_DIV,Reference Divisor to get better resolution and lower PPM errors when synthesizing from a non-integer reference clock. NOTE: Default value is 4. One is added in hardware to give a range of 1 to 8. (volatile and 2 reads needed to read value)" "0,1,2,3,4,5,6,7" newline bitfld.word 0x0 12. "PH_SEL,Phase Mixer Clock select. 1: is pmix. 0 is VCO. (volatile and 2 reads needed to read value)" "?,is pmix" newline bitfld.word 0x0 11. "ZERO_FREQ,Zero frequency register. NOTES: Must be set for PHASE writes to stick (volatile and 2 reads needed to read value)" "0,1" newline hexmask.word 0x0 2.--10. 1. "VAL,Phase value from zero reference (volatile and 2 reads needed to read value)" newline bitfld.word 0x0 0.--1. "DTHR,Bits below the useful resolution (volatile and 2 reads needed to read value)" "0,1,2,3" group.word 0x8018++0x1 line.word 0x0 "SUPX_DIG_SS_FREQ,Frequency Control for Spread Spectrum" newline rbitfld.word 0x0 15. "RESERVED_15_15,Reserved for Future use" "0,1" newline bitfld.word 0x0 14. "FREQ_OVRD,Frequency Reigster Override. NOTE: Must be set for PHASE writes to stick (volatile and 2 reads needed to read value)" "0,1" newline hexmask.word.byte 0x0 7.--13. 1. "FREQ_PK,Peak Frequency Value (for changing direction) (volatile and 2 reads needed to read value)" newline hexmask.word.byte 0x0 0.--6. 1. "FREQ_CNT_INIT,Initial Frequency Counter Value (volatile and 2 reads needed to read value)" group.word 0x801C++0x1 line.word 0x0 "SUPX_DIG_HSP_SS_PHASE,Current HSP_PMIX SSC phase sel value" newline hexmask.word.byte 0x0 11.--15. 1. "RESERVED_15_11,Reserved for Future use" newline hexmask.word.byte 0x0 4.--10. 1. "VAL,SSC phase value from zero reference (volatile and 2 reads needed to read value)" newline hexmask.word.byte 0x0 0.--3. 1. "DTHR,Bits below the useful resolution (volatile and 2 reads needed to read value)" group.word 0x8020++0x1 line.word 0x0 "SUPX_DIG_MPLL_CNT_CTL,Control for fixed or variable MPLL Count Selection" newline hexmask.word 0x0 1.--15. 1. "RESERVED_15_1,Reserved for Future use" newline bitfld.word 0x0 0. "VAR_CNT_EN,Selects variable count when enabled (Default = fixed count)" "0,1" group.word 0x8024++0x1 line.word 0x0 "SUPX_DIG_CR_PARA_ALU_CTL,Control for CR Parallel ALU access" newline hexmask.word 0x0 5.--15. 1. "RESERVED_15_5,Reserved for Future use" newline hexmask.word.byte 0x0 1.--4. 1. "CR_PARA_ALU_OPCODE,Opcode for the ALU when CR para access is enabled. Valid opcodes are as follows: 0 - Zero the accumulator 1 - Add control register read result to accumulator 2 - Add control register write data to accumulator 3 - Shift accumulator left.." newline bitfld.word 0x0 0. "CR_PARA_ALU_ACCESS_EN,Enable access to the ALU through the CR parallel bus." "0,1" rgroup.word 0x8028++0x1 line.word 0x0 "SUPX_DIG_CR_PARA_ALU_FLAGS,Flags from the ALU when CR para access is enabled." newline hexmask.word 0x0 4.--15. 1. "RESERVED_15_4,Reserved for Future use" newline hexmask.word.byte 0x0 0.--3. 1. "DATA,Flags from the ALU when CR para access is enabled. Valid ALU flags: 0 - Signedness used for next ADD_PHSEL command. (1=signed 0=unsigned) 1 - Signedness for ADD_PHSEL command has been chosen by a previous ADD_PHSEL command. 2 - Error detected.." group.word 0x8040++0x1 line.word 0x0 "SUPX_DIG_ATEOVRD,Override values for incoming controls from ASIC" newline hexmask.word 0x0 3.--15. 1. "RESERVED_15_3,Reserved for Future use" newline bitfld.word 0x0 2. "ATEOVRD_EN,Override enable for ATE signals. NOTE: This register is only accessible through cregs. Does not retain state during reset or ATPG. (USER2 - read-write and custom)" "0,1" newline bitfld.word 0x0 1. "REF_USB2_EN,Override value for USB HSP PHY ref_clk enable. (USER2 - read-write and custom)" "0,1" newline bitfld.word 0x0 0. "REF_CLKDIV2,Override value for SSP ref_clk pre-scaler. (USER2 - read-write and custom)" "0,1" group.word 0x8044++0x1 line.word 0x0 "SUPX_DIG_MPLL_OVRD_IN_LO,Override values for incoming RTUNE and MPLL controls from ASIC" newline bitfld.word 0x0 15. "RES_ACK_IN_OVRD,Override enable for res_ack_in" "0,1" newline bitfld.word 0x0 14. "RES_ACK_IN,Override value for res_ack_in" "0,1" newline bitfld.word 0x0 13. "RES_REQ_IN_OVRD,Override enable for res_req_in" "0,1" newline bitfld.word 0x0 12. "RES_REQ_IN,Override value for res_req_in" "0,1" newline bitfld.word 0x0 11. "RTUNE_REQ_OVRD,Override enable for rtune_req" "0,1" newline bitfld.word 0x0 10. "RTUNE_REQ,Override value for rtune_req" "0,1" newline bitfld.word 0x0 9. "MPLL_MULTIPLIER_OVRD,Override enable for mpll_multipler" "0,1" newline hexmask.word.byte 0x0 2.--8. 1. "MPLL_MULTIPLIER,Override value for mpll_multipler" newline bitfld.word 0x0 1. "MPLL_EN_OVRD,Override enable for mpll_en" "0,1" newline bitfld.word 0x0 0. "MPLL_EN,Override value for mpll_en" "0,1" group.word 0x8048++0x1 line.word 0x0 "SUPX_DIG_MPLL_OVRD_IN_HI,Override values for incoming VBOOST LVL and MPLL controls from ASIC" newline bitfld.word 0x0 13.--15. "TX_VBOOST_LVL,Override value for tx_vboost_lvl. Override enabled using LEVEL_EN from LEVEL_OVRD_IN register." "0,1,2,3,4,5,6,7" newline bitfld.word 0x0 12. "MPLL_REFSSC_CLK_EN_OVRD,Override enable for mpll_refssc_clk_en" "0,1" newline bitfld.word 0x0 11. "MPLL_REFSSC_CLK_EN,Override value for mpll_refssc_clk_en" "0,1" newline bitfld.word 0x0 10. "MPLL_RST,Reset the MPLL state machine Writing the register with this bit set will reset the MPLL power up/down FSM regardless of the current state of the register bit." "0,1" newline bitfld.word 0x0 9. "FSEL_OVRD,Override enable for fsel[2:0]" "0,1" newline bitfld.word 0x0 6.--8. "FSEL,Override value for fsel [2:0]" "0,1,2,3,4,5,6,7" newline bitfld.word 0x0 5. "MPLL_WORD_CLK_EN_OVRD,Override enable for mpll_word_clk_en" "0,1" newline bitfld.word 0x0 4. "MPLL_WORD_CLK_EN,Override value for mpll_word_clk_en" "0,1" newline bitfld.word 0x0 3. "MPLL_DWORD_CLK_EN_OVRD,Override enable for mpll_dword_clk_en" "0,1" newline bitfld.word 0x0 2. "MPLL_DWORD_CLK_EN,Override value for mpll_dword_clk_en" "0,1" newline bitfld.word 0x0 1. "MPLL_QWORD_CLK_EN_OVRD,Override enable for mpll_qword_clk_en" "0,1" newline bitfld.word 0x0 0. "MPLL_QWORD_CLK_EN,Override value for mpll_qword_clk_en" "0,1" group.word 0x804C++0x1 line.word 0x0 "SUPX_DIG_SSC_OVRD_IN,Override values for incoming SSC controls from ASIC" newline rbitfld.word 0x0 14.--15. "RESERVED_15_14,Reserved for Future use" "0,1,2,3" newline bitfld.word 0x0 13. "SSC_OVRD_IN_EN,Override enable for Spread Spectrum generator." "0,1" newline bitfld.word 0x0 12. "SSC_EN,Override value for SSC enable." "0,1" newline bitfld.word 0x0 9.--11. "SSC_RANGE,Override value for SSC modulation range." "0,1,2,3,4,5,6,7" newline hexmask.word 0x0 0.--8. 1. "SSC_REF_CLK_SEL,Override value for reference clock scaling" group.word 0x8050++0x1 line.word 0x0 "SUPX_DIG_BS_OVRD_IN,Override values for incoming BS controls from ASIC" newline hexmask.word.byte 0x0 12.--15. 1. "RESERVED_15_12,Reserved for Future use" newline bitfld.word 0x0 11. "EN,Enable override values for all inputs controlled by this register" "0,1" newline bitfld.word 0x0 10. "INVERT,Override value for bs_invert" "0,1" newline bitfld.word 0x0 9. "INIT,Override value for bs_init" "0,1" newline bitfld.word 0x0 8. "HIGHZ,Override value for bs_highz" "0,1" newline bitfld.word 0x0 7. "CLAMP,Override value for bs_clamp" "0,1" newline bitfld.word 0x0 6. "EXTEST_AC,Override value for bs_extest_ac" "0,1" newline bitfld.word 0x0 5. "EXTEST,Override value for bs_extest" "0,1" newline bitfld.word 0x0 4. "PRELOAD,Override value for bs_preload" "0,1" newline bitfld.word 0x0 3. "UPDATE_DR,Override value for bs_update_dr" "0,1" newline bitfld.word 0x0 2. "CAPTURE_DR,Override value for bs_capture_dr" "0,1" newline bitfld.word 0x0 1. "SHIFT_DR,Override value for bs_shift_dr" "0,1" newline bitfld.word 0x0 0. "IN,Override value for bs_in" "0,1" group.word 0x8054++0x1 line.word 0x0 "SUPX_DIG_LEVEL_OVRD_IN,Override values for acjt_level and los_level" newline bitfld.word 0x0 13.--15. "LOS_BIAS,Override value for los_bias" "0,1,2,3,4,5,6,7" newline bitfld.word 0x0 12. "MPLL_HALF_RATE_OVRD,Enable override value for mpll_half_rate" "0,1" newline bitfld.word 0x0 11. "MPLL_HALF_RATE,Override value for mpll_half_rate" "0,1" newline bitfld.word 0x0 10. "LEVEL_EN,Enable override values for tx_vboost_lvl/los_bias/los_level/acjt_level inputs controlled by this and MPLL_OVRD_IN_HI registers" "0,1" newline hexmask.word.byte 0x0 5.--9. 1. "ACJT_LEVEL,Override value for acjt_level" newline hexmask.word.byte 0x0 0.--4. 1. "LOS_LEVEL,Override value for los_level" group.word 0x8058++0x1 line.word 0x0 "SUPX_DIG_SUP_OVRD_OUT,Override values for support block" newline hexmask.word.byte 0x0 10.--15. 1. "RESERVED_15_10,Reserved for Future use" newline bitfld.word 0x0 9. "MPLL_STATE_OVRD,Override enable for mpll_state output" "0,1" newline bitfld.word 0x0 8. "MPLL_STATE,Override value for mpll_state output" "0,1" newline bitfld.word 0x0 7. "BS_OUT_OVRD,Override enable for bs_out output" "0,1" newline bitfld.word 0x0 6. "BS_OUT,Override value for bs_out output" "0,1" newline bitfld.word 0x0 5. "RTUNE_ACK_OVRD,Override enable for rtune_ack output" "0,1" newline bitfld.word 0x0 4. "RTUNE_ACK,Override value for rtune_ack output" "0,1" newline bitfld.word 0x0 3. "RES_REQ_OUT_OVRD,Override enable for res_req_out output" "0,1" newline bitfld.word 0x0 2. "RES_REQ_OUT,Override value for res_req_out output" "0,1" newline bitfld.word 0x0 1. "RES_ACK_OUT_OVRD,Override enable for res_ack_out output" "0,1" newline bitfld.word 0x0 0. "RES_ACK_OUT,Override value for res_ack_out output" "0,1" rgroup.word 0x805C++0x1 line.word 0x0 "SUPX_DIG_MPLL_ASIC_IN,Current values for incoming MPLL controls from ASIC" newline bitfld.word 0x0 15. "RESERVED_15_15,Reserved for Future use" "0,1" newline bitfld.word 0x0 14. "MPLL_REFSSC_CLK_EN,Value from ASIC for mpll_refssc_clk_en (RU - read-only volatile)" "0,1" newline bitfld.word 0x0 13. "MPLL_WORD_CLK_EN,Value from ASIC for mpll_word_clk_en (RU - read-only volatile)" "0,1" newline bitfld.word 0x0 12. "MPLL_DWORD_CLK_EN,Value from ASIC for mpll_dword_clk_en (RU - read-only volatile)" "0,1" newline bitfld.word 0x0 11. "MPLL_QWORD_CLK_EN,Value from ASIC for mpll_qword_clk_en (RU - read-only volatile)" "0,1" newline bitfld.word 0x0 10. "RES_ACK_IN,Value from ASIC for res_ack_in (RU - read-only volatile)" "0,1" newline bitfld.word 0x0 9. "RES_REQ_IN,Value from ASIC for res_req_in (RU - read-only volatile)" "0,1" newline bitfld.word 0x0 8. "RTUNE_REQ,Value from ASIC for rtune_req (RU - read-only volatile)" "0,1" newline hexmask.word.byte 0x0 1.--7. 1. "MPLL_MULTIPLIER,Value from ASIC for mpll_multiplier (RU - read-only volatile)" newline bitfld.word 0x0 0. "MPLL_EN,Value from ASIC for mpll_en (RU - read-only volatile)" "0,1" rgroup.word 0x8060++0x1 line.word 0x0 "SUPX_DIG_BS_ASIC_IN,Current values for incoming boundary scan controls from ASIC" newline bitfld.word 0x0 14.--15. "RESERVED_15_14,Reserved for Future use" "0,1,2,3" newline bitfld.word 0x0 11.--13. "TX_VBOOST_LVL,Value from ASIC for tx_vboost_lvl -- Not as bs_* signal but we're out of bits. (RU - read-only volatile)" "0,1,2,3,4,5,6,7" newline bitfld.word 0x0 10. "INVERT,Value from ASIC for bs_invert (RU - read-only volatile)" "0,1" newline bitfld.word 0x0 9. "INIT,Value from ASIC for bs_init (RU - read-only volatile)" "0,1" newline bitfld.word 0x0 8. "HIGHZ,Value from ASIC for bs_highz (RU - read-only volatile)" "0,1" newline bitfld.word 0x0 7. "CLAMP,Value from ASIC for bs_clamp (RU - read-only volatile)" "0,1" newline bitfld.word 0x0 6. "EXTEST_AC,Value from ASIC for bs_extest_ac (RU - read-only volatile)" "0,1" newline bitfld.word 0x0 5. "EXTEST,Value from ASIC for bs_extest (RU - read-only volatile)" "0,1" newline bitfld.word 0x0 4. "PRELOAD,Value from ASIC for bs_preload (RU - read-only volatile)" "0,1" newline bitfld.word 0x0 3. "UPDATE_DR,Value from ASIC for bs_update_dr (RU - read-only volatile)" "0,1" newline bitfld.word 0x0 2. "CAPTURE_DR,Value from ASIC for bs_capture_dr (RU - read-only volatile)" "0,1" newline bitfld.word 0x0 1. "SHIFT_DR,Value from ASIC for bs_shift_dr (RU - read-only volatile)" "0,1" newline bitfld.word 0x0 0. "IN,Value from ASIC for bs_in (RU - read-only volatile)" "0,1" rgroup.word 0x8064++0x1 line.word 0x0 "SUPX_DIG_LEVEL_ASIC_IN,Current values for incoming los/acjt level. MPLL half rate mode and vreg bypass from ASIC" newline bitfld.word 0x0 15. "RESERVED_15_15,Reserved for Future use" "0,1" newline bitfld.word 0x0 12.--14. "LOS_BIAS,Value from ASIC for los_bias (RU - read-only volatile)" "0,1,2,3,4,5,6,7" newline bitfld.word 0x0 11. "MPLL_HALF_RATE,Value from ASIC for mpll_half_rate (RU - read-only volatile)" "0,1" newline bitfld.word 0x0 10. "VREG_BYPASS,Value from ASIC for vreg_bypass (RU - read-only volatile)" "0,1" newline hexmask.word.byte 0x0 5.--9. 1. "ACJT_LEVEL,Value from ASIC for acjt_level (RU - read-only volatile)" newline hexmask.word.byte 0x0 0.--4. 1. "LOS_LEVEL,Value from ASIC for los_level (RU - read-only volatile)" rgroup.word 0x8068++0x1 line.word 0x0 "SUPX_DIG_SSC_ASIC_IN,Current values for incoming SSC controls from ASIC" newline bitfld.word 0x0 15. "SS_EN,Value from ASIC for ssc_en (RU - read-only volatile)" "0,1" newline bitfld.word 0x0 12.--14. "SSC_RANGE,Value from ASIC for ssc_range (RU - read-only volatile)" "0,1,2,3,4,5,6,7" newline hexmask.word 0x0 3.--11. 1. "SSC_REF_CLK_SEL,Value from ASIC for ssc_ref_clk_sel (RU - read-only volatile)" newline bitfld.word 0x0 0.--2. "FSEL,Value from ASIC for fsel (RU - read-only volatile)" "0,1,2,3,4,5,6,7" rgroup.word 0x806C++0x1 line.word 0x0 "SUPX_DIG_SUP_ASIC_OUT,Current values for outgoing support block controls to ASIC" newline hexmask.word 0x0 5.--15. 1. "RESERVED_15_5,Reserved for Future use" newline bitfld.word 0x0 4. "MPLL_STATE,Value from PHY for mpll_state output (RU - read-only volatile)" "0,1" newline bitfld.word 0x0 3. "BS_OUT,Value from PHY for bs_out output (RU - read-only volatile)" "0,1" newline bitfld.word 0x0 2. "RTUNE_ACK,Value from PHY for rtune_ack output (RU - read-only volatile)" "0,1" newline bitfld.word 0x0 1. "RES_REQ_OUT,Value from PHY for res_req_out output (RU - read-only volatile)" "0,1" newline bitfld.word 0x0 0. "RES_ACK_OUT,Value from PHY for res_ack_out output (RU - read-only volatile)" "0,1" rgroup.word 0x8070++0x1 line.word 0x0 "SUPX_DIG_ATEOVRD_STATUS,USB3_SUPX_DIG_ATEOVRD_STATUS" newline hexmask.word.byte 0x0 10.--15. 1. "RESERVED_15_10,Reserved for Future use" newline bitfld.word 0x0 8.--9. "DTB_OUT,Value from dtb_out bus. (RU - read-only volatile)" "0,1,2,3" newline bitfld.word 0x0 7. "REF_SSP_EN,Value from ASIC for ref_ssp_en. (RU - read-only volatile)" "0,1" newline bitfld.word 0x0 6. "REF_USE_PAD,Value from ASIC for ref_use_pad. (RU - read-only volatile)" "0,1" newline bitfld.word 0x0 5. "PHY_RESET_IN,Value from ASIC for phy_reset (RU - read-only volatile)" "0,1" newline bitfld.word 0x0 4. "REF_CLKDIV2_IN,Value from ASIC for ref_clkdiv2 (RU - read-only volatile)" "0,1" newline bitfld.word 0x0 3. "REF_USB2_EN_IN,Value from ASIC for ref_usb2_en (RU - read-only volatile)" "0,1" newline bitfld.word 0x0 2. "ATEOVRD_EN,When set values from ATEOVRD register are being sent to PHY (RU - read-only volatile)" "0,1" newline bitfld.word 0x0 1. "REF_CLKDIV2_OUT,Value from ATEOVRD for ref_clkdiv2 (RU - read-only volatile)" "0,1" newline bitfld.word 0x0 0. "REF_USB2_EN_OUT,Value from ATEOVRD for ref_usb2_en (RU - read-only volatile)" "0,1" group.word 0x8074++0x1 line.word 0x0 "SUPX_DIG_HSP_OVRD_IN,Override values for HSP" newline hexmask.word 0x0 4.--15. 1. "RESERVED_15_4,Reserved for Future use" newline bitfld.word 0x0 3. "HSP_PLL_OVRD,Override enable for HSP pll_pu signal" "0,1" newline bitfld.word 0x0 2. "HSP_PLL_PU,Override value for HSP pll_pu signal" "0,1" newline bitfld.word 0x0 1. "HSP_BIAS_OVRD,Override enable for HSP bias_pu signal" "0,1" newline bitfld.word 0x0 0. "HSP_BIAS_PU,Override value for HSP bias_pu signal" "0,1" rgroup.word 0x8078++0x1 line.word 0x0 "SUPX_DIG_HSP_ASIC_IN,Current values for incoming HSP & REF XO controls from ASIC" newline hexmask.word 0x0 4.--15. 1. "RESERVED_15_4,Reserved for Future use" newline bitfld.word 0x0 3. "REF_USE_XO,Value from ASIC for ref_use_xo (RU - read-only volatile)" "0,1" newline bitfld.word 0x0 2. "REF_XO_EN,Value from ASIC for ref_xo_en (RU - read-only volatile)" "0,1" newline bitfld.word 0x0 1. "HSP_PLL_PU,Value from ASIC for hsp_pll_pu (RU - read-only volatile)" "0,1" newline bitfld.word 0x0 0. "HSP_BIAS_PU,Value from ASIC for hsp_bias_pu (RU - read-only volatile)" "0,1" group.word 0x8080++0x1 line.word 0x0 "SUPX_DIG_SCOPE_ENABLES,Scope Counter configuration" newline hexmask.word 0x0 5.--15. 1. "RESERVED_15_5,Reserved for Future use" newline bitfld.word 0x0 3.--4. "LANE_SELECT,Scope Counter Input select" "0,1,2,3" newline bitfld.word 0x0 2. "MASK_SATURATION_MODE,Method of mask saturation. When 1 Saturate when the first mask_counter reaches sample_limit. When 0 Saturate when all mask_counters have reached sample_limit." "0,1" newline bitfld.word 0x0 1. "MASK_EN,Enable scope_mask input for tracking count values. Clears registers when deasserted." "0,1" newline bitfld.word 0x0 0. "XOR_EN,Use scope_xor input for count values." "0,1" group.word 0x8084++0x1 line.word 0x0 "SUPX_DIG_SCOPE_SAMPLES,Number of samples to count" newline hexmask.word 0x0 0.--15. 1. "SAMPLES,Number of Sample to count." rgroup.word 0x8088++0x1 line.word 0x0 "SUPX_DIG_SCOPE_COUNT,Results of scope counting" newline hexmask.word 0x0 0.--15. 1. "COUNT,A write to this register will start the counting process The value of FFFF indicates counting still in progress. Asserting MASK_EN will also start the counting if in MASK mode. (RU - read-only volatile)" group.word 0x808C++0x1 line.word 0x0 "SUPX_DIG_SCOPE_CTL,Masked scope counting Start and Status" newline hexmask.word 0x0 2.--15. 1. "RESERVED_15_2,Reserved for Future use" newline bitfld.word 0x0 1. "MASK_START,A write to this register will start the counting process The value of FFFF indicates counting still in progress Write will trigger mask counting. (USER1 - read-write volatile)" "?,read-write volatile)" newline bitfld.word 0x0 0. "MASK_SATURATION,When assert mask registers have saturated. (USER1 - read-write volatile)" "?,read-write volatile)" repeat 8. (list 0x0 0x1 0xA 0xB 0x64 0x65 0x6E 0x6F )(list 0x0 0x4 0x8 0xC 0x10 0x14 0x18 0x1C ) group.word ($2+0x8090)++0x1 line.word 0x0 "SUPX_DIG_SCOPE_MASK_$1,Current count value for mask_000" newline hexmask.word 0x0 0.--15. 1. "MASK_VAL_000,Starting count value of mask register. (volatile and 2 reads needed to read value)" repeat.end group.word 0x80C0++0x1 line.word 0x0 "SUPX_ANA_MPLL_LOOP_CTL,MPLL loop control bits" newline hexmask.word.byte 0x0 8.--15. 1. "RESERVED_15_8,Reserved for Future use" newline hexmask.word.byte 0x0 4.--7. 1. "PROP_CNTRL,Charge pump proportional current setting" newline bitfld.word 0x0 2.--3. "INT_CNTRL,Charge pump integrating current setting" "0,1,2,3" newline bitfld.word 0x0 1. "GD,Measure MPLL local GD" "0,1" newline bitfld.word 0x0 0. "VMB,Measure MPLL Master Bias Voltage" "0,1" repeat 2. (list 0x1 0x2 )(list 0x0 0x4 ) group.word ($2+0x80C4)++0x1 line.word 0x0 "SUPX_ANA_MPLL_ATB_MEAS$1,ATB Select bits" newline hexmask.word.byte 0x0 8.--15. 1. "RESERVED_15_8,Reserved for Future use" newline bitfld.word 0x0 7. "VPSF,puts vpsf on atb_s_p" "0,1" newline bitfld.word 0x0 6. "VREF,puts vref from charge pump on atb_s_p" "0,1" newline bitfld.word 0x0 5. "VCNTRL,puts vcntrl on atb_s_m" "0,1" newline bitfld.word 0x0 4. "GD,puts gd on atb_s_m" "0,1" newline bitfld.word 0x0 3. "IVCO,puts VCO current/93 on atb_f_m" "0,1" newline bitfld.word 0x0 2. "VP,puts vpa on atb_s_m" "0,1" newline bitfld.word 0x0 1. "VP_CP,puts vp_cp on atb_s_p" "0,1" newline bitfld.word 0x0 0. "VREG_MPLL,puts vreg_mpll on atb_s_p" "0,1" repeat.end group.word 0x80CC++0x1 line.word 0x0 "SUPX_ANA_MPLL_OVRD,Local overrides" newline hexmask.word.byte 0x0 8.--15. 1. "RESERVED_15_8,Reserved for Future use" newline bitfld.word 0x0 7. "PWRON_LCL,local power_on value" "0,1" newline bitfld.word 0x0 6. "EN_PWRON_LCL,Enable local control of power_on" "0,1" newline bitfld.word 0x0 5. "GS_LCL,local gear_shift value" "0,1" newline bitfld.word 0x0 4. "EN_GS_LCL,Enable local control of gear_shift" "0,1" newline bitfld.word 0x0 3. "RST_LCL,local reset value" "0,1" newline bitfld.word 0x0 2. "EN_RST_LCL,enable local control of reset" "0,1" newline bitfld.word 0x0 1. "PMIX_CLK_SEL_LCL,local pmix_clk_sel value" "0,1" newline bitfld.word 0x0 0. "EN_PMIX_CLK_SEL_LCL,enable local control of pmix_clk_sel" "0,1" group.word 0x80D0++0x1 line.word 0x0 "SUPX_ANA_RTUNE_RTUNE_CTRL,RTUNE control bits" newline hexmask.word.byte 0x0 8.--15. 1. "RESERVED_15_8,Reserved for Future use" newline bitfld.word 0x0 7. "RT_PWRON_FRC_ON,When set forces RTUNE block to be on" "0,1" newline bitfld.word 0x0 6. "X4_FRC_OFF,When set do not multiply test current by 4" "0,1" newline bitfld.word 0x0 4.--5. "RT_DAC_MODE,Margin DAC mode control bits(00=powerdown 01=DAC drives atb_s_p/m directly 10=DAC drives atb_s_p/m to the RX in margining mode 11=illegal state)" "powerdown,DAC drives atb_s_p/m directly,?,?" newline bitfld.word 0x0 3. "RT_DAC_CHOP,Margin DAC chop control bit. ref to ssp analog engineering doc 8.5" "0,1" newline bitfld.word 0x0 2. "RT_ATB,RTUNE ATB mode control bit (1=RTUNE performs ADC on ATB input 0=not accessing ATB. refer to ssp analog engineering specification 8.1.4)" "not accessing ATB,RTUNE performs ADC on ATB input" newline bitfld.word 0x0 1. "RT_SEL_ATBP,RTUNE ATB sense input select bit (1=atb_s_p 0=atb_s_m)" "atb_s_m),atb_s_p" newline bitfld.word 0x0 0. "RT_SEL_ATBF,RTUNE ATB input select bit (1=atb_fm 0=atb_s_p/m)" "atb_s_p/m),atb_fm" group.word 0x80D4++0x1 line.word 0x0 "SUPX_ANA_ATB_SWITCHYARD_CTRL,ATB_SWITCHYARD control bits" newline hexmask.word.byte 0x0 8.--15. 1. "RESERVED_15_8,Reserved for Future use" newline bitfld.word 0x0 7. "ASM_GD,Connect gd to atb_s_m" "0,1" newline bitfld.word 0x0 6. "ASP_VP,Connect vp to atb_s_p" "0,1" newline bitfld.word 0x0 5. "ASP_VBG,Connect vbg to atb_s_p" "0,1" newline bitfld.word 0x0 4. "ASP_VPHREG,Connect vphreg to atb_s_m" "0,1" newline bitfld.word 0x0 3. "ATEST_AFM,drive ATEST from atb_f_m" "0,1" newline bitfld.word 0x0 2. "ATEST_AFP,drive ATEST from atb_f_p" "0,1" newline bitfld.word 0x0 1. "ATEST_ASM,Connet ATEST to atb_s_m" "0,1" newline bitfld.word 0x0 0. "ATEST_ASP,Connect ATEST to atb_s_p" "0,1" group.word 0x80D8++0x1 line.word 0x0 "SUPX_ANA_SSC_CLK_CNTRL,controls sscf reference clock rate" newline hexmask.word.byte 0x0 8.--15. 1. "RESERVED_15_8,Reserved for Future use" newline bitfld.word 0x0 7. "NC,Reserved" "0,1" newline hexmask.word.byte 0x0 0.--6. 1. "SSC_CLK_DIV125,set ssc reference clock to be 20MHz" group.word 0x80DC++0x1 line.word 0x0 "SUPX_ANA_HSP_CLK_DIG_CNTRL0,controls HSP phase clock. and resolution" newline hexmask.word.byte 0x0 8.--15. 1. "RESERVED_15_8,Reserved for Future use" newline bitfld.word 0x0 7. "NUM_OVERRIDE,Set the value to 1 to enable using values from creg bit 6 downto 0" "0,1" newline bitfld.word 0x0 4.--6. "GATE_PMIX_BITS,Set gate_pmix_bits to gate the corresponding MSB of the 7-bit PMIX phase select bits" "?,?,?,?,?,?,?,bit PMIX phase select bits" newline bitfld.word 0x0 3. "HALF_CLK_EN,Set to 1 for 1.25GHz updates to HSP PMIX. Set to 0 for 2.5GHz updates to PMIX." "0,1" newline bitfld.word 0x0 2. "UCLK_EN_N,Set to 1 to disable update clock. Set to 0 to enable update clock. When clock is enabled phase updates are allowed." "0,1" newline bitfld.word 0x0 1. "EN_HSPPMIX_VPMIX,Set to 1 to connect the regulated HSP PMIX supply to the atb_s_p bus" "0,1" newline bitfld.word 0x0 0. "EN_HSPPMIX_FRC_VPMIX,Set to 1 to force override of HSP PMIX regulator voltage to voltage on atb_s_m" "0,1" group.word 0x80E0++0x1 line.word 0x0 "SUPX_ANA_HSP_CLK_DIG_CNTRL1,Lower and Upper Phase Increment Values" newline hexmask.word.byte 0x0 8.--15. 1. "RESERVED_15_8,Reserved for Future use" newline hexmask.word.byte 0x0 4.--7. 1. "UPPER_INT,These bits are only used when num_override is set to 1. Upper integer for phase increments of 2.5 to 2.4 GHz conversion. This is the phase increment that is applied 6 times in every 25 for 1.25 GHz increments and 3 times in every 25 for 2.5GHz" newline hexmask.word.byte 0x0 0.--3. 1. "LOWER_INT,These bits are only used when num_override is set to 1. Lower integer for phase increments of 2.5 to 2.4 GHz conversion. This phase increment is applied 19 times in every 25 for 1.25 GHz increments and 22 times in every 25 for 2.5GHz." group.word 0x9000++0x1 line.word 0x0 "LANEX_DIG_TX_OVRD_IN_LO,Override values for incoming TX controls from ASIC" newline bitfld.word 0x0 15. "LANE_IF_WIDTH_OVRD,Override enable for lane interface width" "0,1" newline bitfld.word 0x0 14. "LANE_IF_WIDTH,Override value for lane interface width" "0,1" newline bitfld.word 0x0 13. "TX_DETECT_RX_REQ_OVRD,Override enable for tx_detect_rx_req" "0,1" newline bitfld.word 0x0 12. "TX_DETECT_RX_REQ,Override value for tx_detect_rx_req" "0,1" newline bitfld.word 0x0 11. "TX_BEACON_EN_OVRD,Override enable for tx_beacon_en" "0,1" newline bitfld.word 0x0 10. "TX_BEACON_EN,Override value for tx_beacon_en" "0,1" newline bitfld.word 0x0 9. "TX_CM_EN_OVRD,Override enable for tx_cm_en" "0,1" newline bitfld.word 0x0 8. "TX_CM_EN,Override value for tx_cm_en" "0,1" newline bitfld.word 0x0 7. "TX_EN_OVRD,Override enable for tx_en" "0,1" newline bitfld.word 0x0 6. "TX_EN,Override value for tx_en" "0,1" newline bitfld.word 0x0 5. "TX_DATA_EN_OVRD,Override enable for tx_data_en" "0,1" newline bitfld.word 0x0 4. "TX_DATA_EN,Override value for tx_data_en" "0,1" newline bitfld.word 0x0 3. "TX_INVERT_OVRD,Override enable for tx_invert" "0,1" newline bitfld.word 0x0 2. "TX_INVERT,Override value for tx_invert" "0,1" newline bitfld.word 0x0 1. "TX_LOOPBK_EN_OVRD,Override enable for loopbk_en" "0,1" newline bitfld.word 0x0 0. "LOOPBK_EN,Override value for loopbk_en" "0,1" group.word 0x9004++0x1 line.word 0x0 "LANEX_DIG_TX_OVRD_IN_HI,Override values for incoming TX controls from ASIC" newline hexmask.word.byte 0x0 10.--15. 1. "RESERVED_15_10,Reserved for Future use" newline bitfld.word 0x0 9. "TX_VBOOST_EN_OVRD,Override enable for tx_vboost_en" "0,1" newline bitfld.word 0x0 8. "TX_VBOOST_EN,Override value for tx_vboost_en" "0,1" newline bitfld.word 0x0 7. "TX_RESET_OVRD,Override enable for tx_reset" "0,1" newline bitfld.word 0x0 6. "TX_RESET,Override value for tx_reset" "0,1" newline bitfld.word 0x0 5. "TX_NYQUIST_DATA,Override incoming data to nyquist" "0,1" newline bitfld.word 0x0 4. "TX_CLK_OUT_EN_OVRD,Override enable for tx_clk_out_en." "0,1" newline bitfld.word 0x0 3. "TX_CLK_OUT_EN,Override incomming tx_clk_out_en." "0,1" newline bitfld.word 0x0 2. "TX_RATE_OVRD,Override enable for tx_rate." "0,1" newline bitfld.word 0x0 0.--1. "TX_RATE,Override incomming tx lane rate." "0,1,2,3" group.word 0x9008++0x1 line.word 0x0 "LANEX_DIG_TX_OVRD_DRV_LO,Override values for incoming TX drive controls from ASIC" newline rbitfld.word 0x0 15. "RESERVED_15_15,Reserved for Future use" "0,1" newline bitfld.word 0x0 14. "EN,Enable override values for all inputs controlled by this register" "0,1" newline hexmask.word.byte 0x0 7.--13. 1. "PREEMPH,Override value for transmit preemphasis." newline hexmask.word.byte 0x0 0.--6. 1. "AMPLITUDE,Override value for transmit amplitude." group.word 0x900C++0x1 line.word 0x0 "LANEX_DIG_TX_OVRD_DRV_HI,Override values for incoming TX drive controls from ASIC" newline hexmask.word 0x0 6.--15. 1. "RESERVED_15_6,Reserved for Future use" newline bitfld.word 0x0 5. "EN,Enable override values for all inputs controlled by this register" "0,1" newline hexmask.word.byte 0x0 0.--4. 1. "TERM_OFFSET,Override value for tx_term_offset (tx_ana_vcmref_boost)" group.word 0x9010++0x1 line.word 0x0 "LANEX_DIG_TX_OVRD_OUT,Override values for outgoing TX controls to ASIC" newline hexmask.word.byte 0x0 8.--15. 1. "RESERVED_15_8,Reserved for Future use" newline bitfld.word 0x0 7. "TX_STATE_OVRD,Override enable for tx_state" "0,1" newline bitfld.word 0x0 6. "TX_STATE,Override value for tx_state" "0,1" newline bitfld.word 0x0 5. "TX_CM_STATE_OVRD,Override enable for tx_cm_state" "0,1" newline bitfld.word 0x0 4. "TX_CM_STATE,Override value for tx_cm_state" "0,1" newline bitfld.word 0x0 3. "TX_DETECT_RX_ACK_OVRD,Override enable for tx_detect_rx_ack" "0,1" newline bitfld.word 0x0 2. "TX_DETECT_RX_ACK,Override value for tx_detect_rx_ack" "0,1" newline bitfld.word 0x0 1. "DETECT_RX_RES_OVRD,Override enable for tx_detect_rx_res" "0,1" newline bitfld.word 0x0 0. "DETECT_RX_RES,Override value for tx_detect_rx_res" "0,1" group.word 0x9014++0x1 line.word 0x0 "LANEX_DIG_RX_OVRD_IN_LO,Override values for incoming RX controls from ASIC" newline rbitfld.word 0x0 14.--15. "RESERVED_15_14,Reserved for Future use" "0,1,2,3" newline bitfld.word 0x0 13. "RX_LOS_EN_OVRD,Override enable for rx_los_en" "0,1" newline bitfld.word 0x0 12. "RX_LOS_EN,Override value for rx_los_en" "0,1" newline bitfld.word 0x0 11. "RX_TERM_EN_OVRD,Override enable for rx_term_en" "0,1" newline bitfld.word 0x0 10. "RX_TERM_EN,Override value for rx_term_en" "0,1" newline bitfld.word 0x0 9. "RX_BIT_SHIFT_OVRD,Override enable for rx_bit_shift" "0,1" newline bitfld.word 0x0 8. "RX_BIT_SHIFT,Override value for rx_bit_shift" "0,1" newline bitfld.word 0x0 7. "RX_ALIGN_EN_OVRD,Override enable for rx_align_en" "0,1" newline bitfld.word 0x0 6. "RX_ALIGN_EN,Override value for rx_align_en" "0,1" newline bitfld.word 0x0 5. "RX_DATA_EN_OVRD,Override enable for rx_data_en" "0,1" newline bitfld.word 0x0 4. "RX_DATA_EN,Override value for rx_data_en" "0,1" newline bitfld.word 0x0 3. "RX_PLL_EN_OVRD,Override enable for rx_pll_en" "0,1" newline bitfld.word 0x0 2. "RX_PLL_EN,Override value for rx_pll_en" "0,1" newline bitfld.word 0x0 1. "RX_INVERT_OVRD,Override enable for rx_invert" "0,1" newline bitfld.word 0x0 0. "RX_INVERT,Override value for rx_invert" "0,1" group.word 0x9018++0x1 line.word 0x0 "LANEX_DIG_RX_OVRD_IN_HI,Override values for incoming RX controls from ASIC" newline rbitfld.word 0x0 14.--15. "RESERVED_15_14,Reserved for Future use" "0,1,2,3" newline bitfld.word 0x0 13. "RX_RESET_OVRD,Override enable for rx_reset" "0,1" newline bitfld.word 0x0 12. "RX_RESET,Override value for rx_reset" "0,1" newline bitfld.word 0x0 11. "RX_EQ_OVRD,Override enable for rx_eq" "0,1" newline bitfld.word 0x0 8.--10. "RX_EQ,Override value for rx_eq" "0,1,2,3,4,5,6,7" newline bitfld.word 0x0 7. "RX_EQ_EN_OVRD,Override enable for rx_eq_en" "0,1" newline bitfld.word 0x0 6. "RX_EQ_EN,Override value for rx_eq_en" "0,1" newline bitfld.word 0x0 5. "RX_LOS_FILTER_OVRD,Override enable for rx_los_filter" "0,1" newline bitfld.word 0x0 3.--4. "RX_LOS_FILTER,Override value for rx_los_filter" "0,1,2,3" newline bitfld.word 0x0 2. "RX_RATE_OVRD,Override enable for rx_rate" "0,1" newline bitfld.word 0x0 0.--1. "RX_RATE,Override value for rx_rate" "0,1,2,3" group.word 0x901C++0x1 line.word 0x0 "LANEX_DIG_RX_OVRD_OUT,Override values for outgoing RX controls to ASIC" newline hexmask.word 0x0 7.--15. 1. "RESERVED_15_7,Reserved for Future use" newline bitfld.word 0x0 6. "ZERO_DATA,Override data output to all zeros" "0,1" newline bitfld.word 0x0 5. "LOS_OVRD,Override value for rx_los" "0,1" newline bitfld.word 0x0 4. "LOS,Override value for rx_los" "0,1" newline bitfld.word 0x0 3. "PLL_STATE_OVRD,Override enable for rx_pll_state" "0,1" newline bitfld.word 0x0 2. "PLL_STATE,Override value for rx_pll_state" "0,1" newline bitfld.word 0x0 1. "VALID_OVRD,Override enable for rx_valid" "0,1" newline bitfld.word 0x0 0. "VALID,Override value for rx_valid" "0,1" rgroup.word 0x9020++0x1 line.word 0x0 "LANEX_DIG_TX_ASIC_IN,Current values for incoming TX controls from ASIC" newline bitfld.word 0x0 14.--15. "RESERVED_15_14,Reserved for Future use" "0,1,2,3" newline bitfld.word 0x0 13. "LANE_IF_WIDTH,Value from ASIC for lane_if_width (RU - read-only volatile)" "0,1" newline bitfld.word 0x0 12. "DATA_EN_S,Value from ASIC for tx_data_en_s (RU - read-only volatile)" "0,1" newline bitfld.word 0x0 11. "TX_VBOOST_EN,Value from ASIC for tx_vboost_en (RU - read-only volatile)" "0,1" newline bitfld.word 0x0 10. "TX_CLK_OUT_EN,Value from ASIC for tx_clk_out_en (RU - read-only volatile)" "0,1" newline bitfld.word 0x0 9. "DETECT_RX_REQ,Value from ASIC for tx_detect_rx_req (RU - read-only volatile)" "0,1" newline bitfld.word 0x0 8. "BEACON_EN,Value from ASIC for tx_beacon_en (RU - read-only volatile)" "0,1" newline bitfld.word 0x0 7. "CM_EN,Value from ASIC for tx_cm_en (RU - read-only volatile)" "0,1" newline bitfld.word 0x0 6. "TX_EN,Value from ASIC for tx_en (RU - read-only volatile)" "0,1" newline bitfld.word 0x0 5. "DATA_EN,Value from ASIC for tx_data_en (RU - read-only volatile)" "0,1" newline bitfld.word 0x0 4. "TX_RESET,Value from ASIC for tx_reset (RU - read-only volatile)" "0,1" newline bitfld.word 0x0 3. "INVERT,Value from ASIC for tx_invert (RU - read-only volatile)" "0,1" newline bitfld.word 0x0 2. "LOOPBK_EN,Value from ASIC for loopbk_en (RU - read-only volatile)" "0,1" newline bitfld.word 0x0 0.--1. "TX_RATE,Value from ASIC for tx_rate (RU - read-only volatile)" "0,1,2,3" rgroup.word 0x9024++0x1 line.word 0x0 "LANEX_DIG_TX_ASIC_DRV_LO,Current values for incoming TX level controls from ASIC" newline bitfld.word 0x0 14.--15. "RESERVED_15_14,Reserved for Future use" "0,1,2,3" newline hexmask.word.byte 0x0 7.--13. 1. "PREEMPH,Value from ASIC for tx_preemph (RU - read-only volatile)" newline hexmask.word.byte 0x0 0.--6. 1. "AMPLITUDE,Value from ASIC for tx_amplitude (RU - read-only volatile)" rgroup.word 0x9028++0x1 line.word 0x0 "LANEX_DIG_TX_ASIC_DRV_HI,Current values for incoming TX level controls from ASIC" newline hexmask.word 0x0 5.--15. 1. "RESERVED_15_5,Reserved for Future use" newline hexmask.word.byte 0x0 0.--4. 1. "TERM_OFFSET,Value from ASIC for tx_term_offset (RU - read-only volatile)" rgroup.word 0x902C++0x1 line.word 0x0 "LANEX_DIG_TX_ASIC_OUT,Current values for outgoing TX status controls from PHY" newline hexmask.word 0x0 5.--15. 1. "RESERVED_15_5,Reserved for Future use" newline bitfld.word 0x0 4. "STATE,Value from PHY for tx_state (RU - read-only volatile)" "0,1" newline bitfld.word 0x0 3. "CM_STATE,Value from PHY for tx_cm_state (RU - read-only volatile)" "0,1" newline bitfld.word 0x0 2. "DETECT_RX_ACK,Value from PHY for tx_detect_rx_ack (RU - read-only volatile)" "0,1" newline bitfld.word 0x0 1. "RESERVED,Always returns 0 (RU - read-only volatile)" "0,1" newline bitfld.word 0x0 0. "DETECT_RX_RES,Value from PHY for tx_detect_rx_res (RU - read-only volatile)" "0,1" rgroup.word 0x9030++0x1 line.word 0x0 "LANEX_DIG_RX_ASIC_IN,Current values for incoming RX controls from ASIC" newline bitfld.word 0x0 15. "RX_EQ_EN,Value from ASIC for rx_eq_en (RU - read-only volatile)" "0,1" newline bitfld.word 0x0 12.--14. "RX_EQ,Value from ASIC for rx_eq (RU - read-only volatile)" "0,1,2,3,4,5,6,7" newline bitfld.word 0x0 10.--11. "LOS_FILTER,Value from ASIC for rx_los_filter (RU - read-only volatile)" "0,1,2,3" newline bitfld.word 0x0 9. "LOS_EN,Value from ASIC for rx_los_en (RU - read-only volatile)" "0,1" newline bitfld.word 0x0 8. "TERM_EN,Value from ASIC for rx_term_en (RU - read-only volatile)" "0,1" newline bitfld.word 0x0 7. "CLK_SHIFT,Value from ASIC for rx_bit_shift (RU - read-only volatile)" "0,1" newline bitfld.word 0x0 6. "ALIGN_EN,Value from ASIC for rx_align_en (RU - read-only volatile)" "0,1" newline bitfld.word 0x0 5. "DATA_EN,Value from ASIC for rx_data_en (RU - read-only volatile)" "0,1" newline bitfld.word 0x0 4. "PLL_EN,Value from ASIC for rx_pll_en (RU - read-only volatile)" "0,1" newline bitfld.word 0x0 3. "RX_RESET,Value from ASIC for rx_reset (RU - read-only volatile)" "0,1" newline bitfld.word 0x0 2. "INVERT,Value from ASIC for rx_invert (RU - read-only volatile)" "0,1" newline bitfld.word 0x0 0.--1. "RX_RATE,Value from ASIC for rx_rate (RU - read-only volatile)" "0,1,2,3" rgroup.word 0x9034++0x1 line.word 0x0 "LANEX_DIG_RX_ASIC_OUT,Current values for outgoing RX status controls from PHY" newline hexmask.word 0x0 3.--15. 1. "RESERVED_15_3,Reserved for Future use" newline bitfld.word 0x0 2. "LOS,Value from PHY for rx_los (RU - read-only volatile)" "0,1" newline bitfld.word 0x0 1. "PLL_STATE,Value from PHY for rx_pll_state (RU - read-only volatile)" "0,1" newline bitfld.word 0x0 0. "VALID,Value from PHY for rx_valid (RU - read-only volatile)" "0,1" group.word 0x9040++0x1 line.word 0x0 "LANEX_DIG_TX_DEBUG,Transmit debug controls" newline rbitfld.word 0x0 13.--15. "RESERVED_15_13,Reserved for Future use" "0,1,2,3,4,5,6,7" newline bitfld.word 0x0 12. "KEEP_TX_REFGEN,Keep TX voltage regulator ON until TX clocks are OFF" "0,1" newline hexmask.word.byte 0x0 4.--11. 1. "RXDET_MEAS_TIME,Time to wait for rxdet measurement (* 4/2/1 refclk cycles based on multiplier)" newline bitfld.word 0x0 3. "DETECT_RX_ALWAYS,Always signal 1 for rx_detect ignoring analog" "0,1" newline bitfld.word 0x0 0.--2. "DTB_SEL,Selects data to drive on DTB 0 - disabled 1 - mag_update/sub signals 2 - mag_high/add signals 3 - clock aligner early/shift signals 4 - analog/asic clocks 5 - tx_state counter/lbert strobe 6 - noclk_ref_rst/dig_rst 7 -.." "disabled,mag_update/sub signals,mag_high/add signals,clock aligner early/shift signals,analog/asic clocks,tx_state counter/lbert strobe,noclk_ref_rst/dig_rst,tx_ana_rxdetp_high/tx_ana_rxdetm_high" group.word 0x9044++0x1 line.word 0x0 "LANEX_DIG_TX_CM_WAIT_TIME_OVRD,USB3_LANEX_DIG_TX_CM_WAIT_TIME_OVRD" newline hexmask.word.byte 0x0 11.--15. 1. "RESERVED_15_11,Reserved for Future use" newline bitfld.word 0x0 10. "CM_TIME_OVRD_EN,Override enable for common mode charging wait time." "0,1" newline hexmask.word 0x0 0.--9. 1. "CM_TIME_OVRD,Time to wait in ref clock cycles for LFPS common mode charging (This value x32 is used for VCMHOLD charging method)" rgroup.word 0x9048++0x1 line.word 0x0 "LANEX_DIG_TX_VMD_FSM_TX_VCM_0,Calculated values for N_USE and N_TRISTATE. Also TX ANA configuration shift register output." newline bitfld.word 0x0 15. "SHIFT_OUT,Current value from TX_ANAs configuration shift register. (RU - read-only volatile)" "0,1" newline bitfld.word 0x0 14. "DONE,Configuration is done (RU - read-only volatile)" "0,1" newline hexmask.word.byte 0x0 7.--13. 1. "N_USE,Value from VMD for legs to use. (RU - read-only volatile)" newline hexmask.word.byte 0x0 0.--6. 1. "N_TRISTATE,Value from VMD for number of tristate legs. (RU - read-only volatile)" rgroup.word 0x904C++0x1 line.word 0x0 "LANEX_DIG_TX_VMD_FSM_TX_VCM_1,Calculated values for N_FIXED and N_TRAILER." newline bitfld.word 0x0 15. "FIXED_DONE,N_FIXED Multiplication has completed. (RU - read-only volatile)" "0,1" newline bitfld.word 0x0 14. "TRA_DONE,N_TRAILER Multiplication has completed. (RU - read-only volatile)" "0,1" newline hexmask.word.byte 0x0 7.--13. 1. "N_FIXED,Value from VMD for number of fixed driver legs. (RU - read-only volatile)" newline hexmask.word.byte 0x0 0.--6. 1. "N_TRAILER,Value from VMD for number of trailer legs. (RU - read-only volatile)" group.word 0x9050++0x1 line.word 0x0 "LANEX_DIG_TX_VMD_FSM_TX_VCM_DEBUG_IN,Access the TX_ANA VMD Control Shift Register" newline hexmask.word 0x0 4.--15. 1. "RESERVED_15_4,Reserved for Future use" newline bitfld.word 0x0 3. "CONFIG_OVRD,Override the Voltage Mode Driver Configuration FSM and access the shift chain directly. (volatile and 2 reads needed to read value)" "0,1" newline bitfld.word 0x0 2. "CONFIG_LOAD,Override value for the Voltage Mode Driver Configuration FSM's config load. (volatile and 2 reads needed to read value)" "0,1" newline bitfld.word 0x0 1. "CONFIG_CLK,Override value for the Voltage Mode Driver Configuration FSM's config clk. (volatile and 2 reads needed to read value)" "0,1" newline bitfld.word 0x0 0. "CONFIG_DATA,Override value for the Voltage Mode Driver Configuration FSM's config data. (volatile and 2 reads needed to read value)" "0,1" group.word 0x9054++0x1 line.word 0x0 "LANEX_DIG_TX_LBERT_CTL,Pattern Generator controls" newline rbitfld.word 0x0 15. "RESERVED_15_15,Reserved for Future use" "0,1" newline hexmask.word 0x0 5.--14. 1. "PAT0,10 bit pattern for modes using PAT0 (5-7). Ignored for other MODEs." newline bitfld.word 0x0 4. "TRIGGER_ERR,Single shot inversion the LSB of the current symbol. Any write of a 1 to this bit will insert an error. Maintain mode and pattern from setup." "0,1" newline hexmask.word.byte 0x0 0.--3. 1. "MODE,Pattern to generate When changing modes you must change to disabled first 0 - disabled 1 - lfsr31. X^31 + X^28 + 1 2 - lfsr23. X^23 + X^18 + 1 3 - lfsr15. X^15 + X^14 + 1 4 - lfsr7. X^7 + X^6 + 1 5 - fixed word (PAT0) 6 - DC balanced word (PAT0.." group.word 0x9058++0x1 line.word 0x0 "LANEX_DIG_RX_LBERT_CTL,Pattern Matcher controls" newline hexmask.word 0x0 5.--15. 1. "RESERVED_15_5,Reserved for Future use" newline bitfld.word 0x0 4. "SYNC,Synchronize pattern matcher with incoming data A write of a one to this bit will reset the error counter and start a synchronization of the PM. There is no need to write this back to zero to run normally." "0,1" newline hexmask.word.byte 0x0 0.--3. 1. "MODE,Pattern to match When changing modes you must change to disabled first 0 - disabled 1 - lfsr31: X^31 + X^28 + 1 2 - lfsr23: X^23 + X^18 + 1 3 - lfsr15: X^15 + X^14 + 1 4 - lfsr7 : X^7 + X^6 + 1 5 - d[n] = d[n-10] 6 - d[n] = !d[n-10] 7 - d[n] =.." group.word 0x905C++0x1 line.word 0x0 "LANEX_DIG_RX_LBERT_ERR,Pattern match error counter" newline bitfld.word 0x0 15. "OV14,A read of this register or a sync of the Pattern Matcher resets the error count. If all bits of this register are 1 the error counter has saturated. If the status If active multiply COUNT by 128. If OV14=1 and COUNT=2^15-1 signals overflow of.." "0,1" newline hexmask.word 0x0 0.--14. 1. "COUNT,Current error count If OV14 field is active then multiply count by 128 to get the actual count. (volatile and 2 reads needed to read value)" group.word 0x9060++0x1 line.word 0x0 "LANEX_DIG_RX_SCOPE_CTL,Control bits for per-transciever scope portion" newline rbitfld.word 0x0 14.--15. "RESERVED_15_14,Reserved for Future use" "0,1,2,3" newline bitfld.word 0x0 12.--13. "RX_VALID_CTL,When to Start Sampling control based on rx_valid. 0 = Ignore rx_valid. 1 = Heed rx_valid. 2 = Wait for rising_edge on rx_valid." "Ignore rx_valid,Heed rx_valid,Wait for rising_edge on rx_valid,?" newline hexmask.word 0x0 3.--11. 1. "DELAY,number of cycles to skip between samples" newline bitfld.word 0x0 0.--2. "MODE,sampling mode of counters NOTE: WORD is 20 bits. 0 = off 1 = sample data every WORD*(1+DELAY) bits from the digital recovered path. 2 = sample data every WORD*(1+DELAY) + 1 bits from the digital recovered path. 3 = sample data every WORD*(1+DELAY) +.." "off,sample data every WORD*,sample data every WORD*,sample data every WORD*,sample data every WORD*,?,?,?" group.word 0x9064++0x1 line.word 0x0 "LANEX_DIG_RX_SCOPE_PHASE,Scope sampling phase." newline rbitfld.word 0x0 15. "RESERVED_15_15,Reserved for Future use" "0,1" newline hexmask.word.byte 0x0 10.--14. 1. "BASE,which bit to sample when MODE = 1 or 4" newline bitfld.word 0x0 8.--9. "SCOPE_DELAY,How many clocks to delay the analog scope_data." "0,1,2,3" newline bitfld.word 0x0 7. "SCOPE_SEL,Select Sampling Mode. 0 - Before AFE Sampling 1 - After AFE Sampling" "Before AFE Sampling,After AFE Sampling" newline bitfld.word 0x0 6. "UPDATE,Update Sampling phase. Write a 1." "0,1" newline hexmask.word.byte 0x0 0.--5. 1. "SAMPLE_PHASE,Sampling Phase" group.word 0x9068++0x1 line.word 0x0 "LANEX_DIG_RX_DPLL_FREQ,Current frequency integrator value." newline rbitfld.word 0x0 13.--15. "RESERVED_15_13,Reserved for Future use" "0,1,2,3,4,5,6,7" newline hexmask.word 0x0 1.--12. 1. "VAL,Freq is 1.526*VAL ppm from the reference When mpll_slow is set the ppm is half the eqn above (volatile and 2 reads needed to read value)" newline bitfld.word 0x0 0. "DTHR,Bits below the useful resolution (volatile and 2 reads needed to read value)" "0,1" group.word 0x906C++0x1 line.word 0x0 "LANEX_DIG_RX_CDR_CTL,Control bits for receiver in recovered domain" newline hexmask.word.byte 0x0 12.--15. 1. "DTB_SEL,select to drive various signals onto the dtb 0 - disabled 1 - pll_ana_rst pll_count from rx_pwr_ctl 2 - com_good_high/low from aligner 3 - com_bad_high/low from aligner 4 - shift_in_prog ana_odd_data from aligner 5 - low bits of XAUI align FSM.." newline bitfld.word 0x0 11. "ALWAYS_REALIGN,realign on any misaligned comma" "0,1" newline bitfld.word 0x0 10. "FAST_START,decrease startup steps by 50%" "0,1" newline bitfld.word 0x0 8.--9. "FRUG_VALUE,override value for FRUG" "0,1,2,3" newline bitfld.word 0x0 6.--7. "PHUG_VALUE,override value for PHUG" "0,1,2,3" newline bitfld.word 0x0 5. "OVRD_DPLL_GAIN,Override PHUG and FRUG values" "0,1" newline bitfld.word 0x0 4. "PHDET_POL,Reverse polarity of phase error" "0,1" newline bitfld.word 0x0 2.--3. "PHDET_EDGE,Edges to use for phase detection. 11 - Use both edges 10 - Use rising edges only 01 - Use falling edges only 00 - Ignore all edges" "Ignore all edges,Use falling edges only,?,?" newline bitfld.word 0x0 0.--1. "PHDET_EN,Enable phase detecter. top bit is odd slicers bottom is even" "0,1,2,3" rgroup.word 0x9070++0x1 line.word 0x0 "LANEX_DIG_RX_CDR_CDR_FSM_DEBUG,Current values for CDR and Adaptation FSM." newline bitfld.word 0x0 13.--15. "ADAP_RX_EQ,Equalization setting from adaptation FSM. (RU - read-only volatile)" "0,1,2,3,4,5,6,7" newline bitfld.word 0x0 10.--12. "RX_EQ_CTR,Initial centre point from equalization FSM. (RU - read-only volatile)" "0,1,2,3,4,5,6,7" newline bitfld.word 0x0 7.--9. "RX_ANA_EQ,Equalization setting to Analog. (RU - read-only volatile)" "0,1,2,3,4,5,6,7" newline bitfld.word 0x0 6. "ADAP_RX_VALID,Adaptation has completed and locked. (RU - read-only volatile)" "0,1" newline bitfld.word 0x0 5. "CDR_EN_ADAP,Adapatation loop is enabling the CDR. (RU - read-only volatile)" "0,1" newline bitfld.word 0x0 4. "CDR_EN_EQ,Equalization loop is enabling the CDR. (RU - read-only volatile)" "0,1" newline bitfld.word 0x0 3. "ALIGNED,Datapath is bit-aligned. (RU - read-only volatile)" "0,1" newline bitfld.word 0x0 2. "CDR_RX_VALID,CDR has locked to incoming data stream. (RU - read-only volatile)" "0,1" newline bitfld.word 0x0 1. "CDR_TIMEOUT,CDR has not locked to datastream and has timed-out. (RU - read-only volatile)" "0,1" newline bitfld.word 0x0 0. "CDR_EN,CDR has been enabled. (RU - read-only volatile)" "0,1" group.word 0x9074++0x1 line.word 0x0 "LANEX_DIG_RX_CDR_LOCK_VEC_OVRD,Control bits for receiver in recovered domain" newline hexmask.word.byte 0x0 11.--15. 1. "ADAP_CTR_LEVEL,Ammount of earlies that increment the adaptation counter (times 32 Default is 512). (volatile and 2 reads needed to read value)" newline bitfld.word 0x0 10. "ADAP_POLARITY,If asserted invert default adaptation adjustment for equalization. IF early decrease equalization. Normal mode is to decrease. (volatile and 2 reads needed to read value)" "0,1" newline bitfld.word 0x0 9. "LOCK_VECTOR_OVRD,Override enable for the rx_eq outputs. (volatile and 2 reads needed to read value)" "0,1" newline bitfld.word 0x0 8. "LOCK_VECTOR_EN,Override value for the locked_vector output completion. (volatile and 2 reads needed to read value)" "0,1" newline hexmask.word.byte 0x0 0.--7. 1. "LOCK_VECTOR,Override value for the locked_vector. (volatile and 2 reads needed to read value)" rgroup.word 0x9078++0x1 line.word 0x0 "LANEX_DIG_RX_CDR_LOCK_VEC,Current values for the locked vector.." newline hexmask.word.byte 0x0 12.--15. 1. "RESERVED_15_12,Reserved for Future use" newline bitfld.word 0x0 9.--11. "EQ_RX_EQ,Equalization setting from the Equalization Loop. (RU - read-only volatile)" "0,1,2,3,4,5,6,7" newline bitfld.word 0x0 8. "EQ_LOCKED_VECTOR_EN,Equalization locked vector has been filled. (RU - read-only volatile)" "0,1" newline hexmask.word.byte 0x0 0.--7. 1. "EQ_LOCKED_VECTOR,Results of equalization loop. (RU - read-only volatile)" rgroup.word 0x907C++0x1 line.word 0x0 "LANEX_DIG_RX_CDR_ADAP_FSM,Observation of adaptation FSM register." newline hexmask.word.byte 0x0 11.--15. 1. "MSTR_CTR,Master count register. (RU - read-only volatile)" newline hexmask.word.byte 0x0 7.--10. 1. "LOOP_CTR,Loop count register. (RU - read-only volatile)" newline hexmask.word.byte 0x0 3.--6. 1. "ADAP_CTR,Adaptation count register. (RU - read-only volatile)" newline bitfld.word 0x0 0.--2. "ADAP_STATE,Adaptation State. NOTE: ADAP_RESET = 3'b000 ADAP_LOCK = 3'b001 ADAP_SUFF = 3'b010 ADAP_LOOP = 3'b011 ADAP_MSTR = 3'b100 ADAP_DONE = 3'b101 (RU - read-only volatile)" "0,1,2,3,4,5,6,7" group.word 0x9080++0x1 line.word 0x0 "LANEX_ANA_RX_ATB0,ATB Control Register" newline hexmask.word.byte 0x0 8.--15. 1. "RESERVED_15_8,Reserved for Future use" newline bitfld.word 0x0 7. "EN_ATB,Enable ATB sensing and forcing on internal RX nodes" "0,1" newline bitfld.word 0x0 6. "EN_MARG,Enable margining mode in receiver; it puts EQ common mode output on atb_f_m" "0,1" newline bitfld.word 0x0 5. "EN_ATB_RM_F,Enable atb_f_p on negative-side termination resistor" "0,1" newline bitfld.word 0x0 4. "EN_ATB_RM_S,Enable atb_s_m on negative-side termination resistor" "0,1" newline bitfld.word 0x0 3. "EN_ATB_RP_F,Enable atb_f_p on positive-side termination resistor" "0,1" newline bitfld.word 0x0 2. "EN_ATB_RP_S,Enable atb_s_p on positive-side termination resistor" "0,1" newline bitfld.word 0x0 1. "EN_ATB_VOS,Put rxafe filtered outputs vo_p on atb_s_p and vo_m on atb_s_m" "0,1" newline bitfld.word 0x0 0. "EN_ATB_VOFF,Put rxafe voff_p on atb_s_p and voff_m on atb_s_m" "0,1" group.word 0x9084++0x1 line.word 0x0 "LANEX_ANA_RX_ATB1,ATB and Misc Control Register" newline hexmask.word.byte 0x0 8.--15. 1. "RESERVED_15_8,Reserved for Future use" newline bitfld.word 0x0 6.--7. "RX_DCC_IQ_OFFSET_H_4_3,Code which helps to manually tune reference voltage (r-string dac) for IQ opamp and correct input offset (rx_dcc_iq_offset_h_4_3 bit)" "0,1,2,3" newline bitfld.word 0x0 5. "EN_ATB_VLOS,Enable sensing of LOS reference voltage on atb_s_p" "0,1" newline bitfld.word 0x0 4. "EN_ATB_VRF,Enable sensing of vref_rx (RX Bias B.G. Voltage) on atb_s_p" "0,1" newline bitfld.word 0x0 3. "MEAS_GD,Enable sensing of local gd in RX; ties gd to atb_s_m" "0,1" newline bitfld.word 0x0 2. "MEAS_VP,Enable sensing of local vp in RX; ties vp to atb_s_p" "0,1" newline bitfld.word 0x0 0.--1. "RX_DCC_IQ_OFFSET_H_2_1,Code which helps to manually tune reference voltage (r-string dac) for IQ opamp and correct input offset (rx_dcc_iq_offset_h_2_1 bit)" "0,1,2,3" group.word 0x9088++0x1 line.word 0x0 "LANEX_ANA_RX_ENPWR0,RX State Control Register" newline hexmask.word.byte 0x0 8.--15. 1. "RESERVED_15_8,Reserved for Future use" newline bitfld.word 0x0 7. "CTL_RXPWRON,MUX select for AFE en to select between CTL_RXPWRON=0 rx_afe_en (External signal) or CTL_RXPWRON=1 LCL_RXPWRON" "0,1" newline bitfld.word 0x0 6. "LCL_RXPWRON,Enable/Disable RX AFE .This bit is only selected when CTL_RXPWRON = 1" "0,1" newline bitfld.word 0x0 5. "CTL_EN_LOS,MUX select for LOS en to select between CTL_EN_LOS=0 rx_los_en (External signal) or CTL_EN_LOS=1 LCL_EN_LOS" "0,1" newline bitfld.word 0x0 4. "LCL_EN_LOS,Enable/Disable LOS.This bit is only selected when CTL_EN_LOS = 1" "0,1" newline bitfld.word 0x0 3. "CTL_RXCK,MUX select for RX Clock en to select between CTL_RXCK=0 rx_clock_en (External signal) or CTL_RXCK=1 LCL_RXCK." "0,1" newline bitfld.word 0x0 2. "LCL_RXCK,Enable/Disable en_rx_clock (RX clock enable).This bit is only selected when CTL_RXCK = 1" "0,1" newline bitfld.word 0x0 1. "CTL_ACJT,MUX select for ACJTAG to select between CTL_ACJTG=0 rx_acjtg_en (External signal) or CTL_ACJTG=1 LCL_ACJT." "0,1" newline bitfld.word 0x0 0. "LCL_ACJT,Enable/Disable acjtag block This bit is only selected when CTL_ACJTG = 1" "0,1" group.word 0x908C++0x1 line.word 0x0 "LANEX_ANA_RX_PMIX_PHASE,Phase select Value" newline hexmask.word.byte 0x0 8.--15. 1. "RESERVED_15_8,Reserved for Future use" newline hexmask.word.byte 0x0 0.--7. 1. "PHASE,Write to bits 8 to 1 of the phase select register in the phase mixer through the CDR (USER2 volatile - read-write volatile and custom)" group.word 0x9090++0x1 line.word 0x0 "LANEX_ANA_RX_ENPWR1,Additional RX State Control Register" newline hexmask.word.byte 0x0 8.--15. 1. "RESERVED_15_8,Reserved for Future use" newline bitfld.word 0x0 7. "CTL_PHASE_REG_RST,MUX select for Phase Register Reset to select between CTL_PHASE_REG_RST=0 rx_phase_reg_rst (External signal) or CTL_PHASE_REG_RST=1 LCL_PHASE_REG_RST" "0,1" newline bitfld.word 0x0 6. "LCL_PHASE_REG_RST,Reset phase register.This bit is only selected when CTL_PHASE_REG_RST= 1" "0,1" newline bitfld.word 0x0 5. "CTL_BST,MUX select for AFE Boost to select between CTL_BST=0 rx_aeq[2:0] (External signal) or CTL_BST=1 LCL_BST" "0,1" newline bitfld.word 0x0 2.--4. "LCL_BST,RX Boost (equalization) Value" "0,1,2,3,4,5,6,7" newline bitfld.word 0x0 1. "CTL_RXTERM,MUX select for RX Term enable to select between CTL_RXTERM=0 rx_term_en (External signal) or CTL_RXTERM=1 LCL_RXTERM" "0,1" newline bitfld.word 0x0 0. "LCL_RXTERM,Enable/disable RX termination when CTL_RXTERM = 1" "0,1" group.word 0x9094++0x1 line.word 0x0 "LANEX_ANA_RX_ENPWR2,Yet another RX State Control Register" newline hexmask.word.byte 0x0 8.--15. 1. "RESERVED_15_8,Reserved for Future use" newline bitfld.word 0x0 7. "EN_RXPMIX_TST,Enable XOR gate to test linearity of RX phase mixer using atb_s_p and atb_s_m" "0,1" newline bitfld.word 0x0 6. "EN_RXPMIX_VPMIX,Put vreg_pmix on atb_s_p" "0,1" newline bitfld.word 0x0 5. "EN_RXPMIX_VRX,Put vreg_rx on atb_s_p" "0,1" newline bitfld.word 0x0 4. "RX_DCC_IQ_OFFSET_H_0,Code which helps to manually tune reference voltage (r-string dac) for IQ opamp and correct input offset (rx_dcc_iq_offset_h_0 bit)" "0,1" newline bitfld.word 0x0 3. "EN_RXPMIX_FRC_VPMIX_H,Connecting vbg_in to vbg (in case of 0) or to atb_s_m_int (in case of 1)" "0,1" newline bitfld.word 0x0 2. "RX_SCOPE_ATB_2,Put XOR of RX SCOPE PMIX input and output on atb_s_p" "0,1" newline bitfld.word 0x0 1. "RX_SCOPE_ATB_1,Put RX SCOPE regulated VP on atb_s_p" "0,1" newline bitfld.word 0x0 0. "RX_SCOPE_ATB_0,Have RX SCOPE reference for regulator use atb_f_p as a reference instead of VP/VBG" "0,1" group.word 0x9098++0x1 line.word 0x0 "LANEX_ANA_RX_SCOPE_VDCC,RX Scope controls and clock DCC control voltage probe" newline hexmask.word.byte 0x0 8.--15. 1. "RESERVED_15_8,Reserved for Future use" newline bitfld.word 0x0 6.--7. "VDCC,Probe DCC control voltage" "0,1,2,3" newline bitfld.word 0x0 5. "NC5,Reserved" "0,1" newline bitfld.word 0x0 4. "RX_SCOPE_SLEW,Set high for low RX clock frqeuencies (625MHz) for RX Scope to work correctly" "0,1" newline bitfld.word 0x0 3. "RX_SCOPE_FDIV20,Divide scope output clock by 20 instead of 10" "0,1" newline bitfld.word 0x0 2. "RX_LOS_LFPS_EN_BIT_2,In case of rx_los_lfps_en_cntrl = 1/0 reg_rx_los_lfps_en/rx_ana_los_lfps_en signal directly applied to rx_los circuit through I101 multiplexer." "0,1" newline bitfld.word 0x0 1. "RX_DCC_IQ_OFFSET_EN_H,Select ref voltage for IQ opamp from testmode part (in case of 1) or from ordinary resistive dividers (in case of 0)." "0,1" newline bitfld.word 0x0 0. "RX_LOS_LFPS_EN,Enables the RX LOS LFPS mode use when you want to detect incoming LFPS signals USB3.0" "0,1" group.word 0x90AC++0x1 line.word 0x0 "LANEX_ANA_TX_TXDRV_CNTRL,Register 3" newline hexmask.word.byte 0x0 8.--15. 1. "RESERVED_15_8,Reserved for Future use" newline bitfld.word 0x0 7. "PULL_DN_REG,register bit that causes the calibrated TX bits to pull down in a common mode fashion. If pull_dn_reg and tx_pull_up are both high then pull_dn_reg wins" "0,1" newline bitfld.word 0x0 6. "PULL_UP_REG,Register override for tx_pull_up. Used when ovrd_pull_up is HIGH causes calibrated TX bits to pull up in a common mode fashion unless pull_dn_reg is HIGH" "0,1" newline bitfld.word 0x0 5. "OVRD_PULL_UP,Selects local value of pull_up_reg instead of tx_pull_up" "0,1" newline bitfld.word 0x0 4. "VCM_HOLD_REG,Register override for tx_vcm_hold. Used when ovrd_vcm_hold is HIGH controls the TX common mode hold circuitry" "0,1" newline bitfld.word 0x0 3. "OVRD_VCM_HOLD,Selects local value of vcm_hold_reg instead of tx_vcm_hold to control state of TX common mode hold circuitry" "0,1" newline bitfld.word 0x0 2. "REFGEN_PWRDN_OVRD_N,Set LOW for TX regulator not to turn on when RX clock is enabled. Default is for TX regulator to turn on when RX or TX clock is enabled" "0,1" newline bitfld.word 0x0 1. "NOCONN_1,Reserved" "0,1" newline bitfld.word 0x0 0. "NOCONN_0,Reserved" "0,1" group.word 0x90B0++0x1 line.word 0x0 "LANEX_ANA_TX_POWER_CTL,Register 4" newline hexmask.word.byte 0x0 8.--15. 1. "RESERVED_15_8,Reserved for Future use" newline bitfld.word 0x0 7. "OVRD_EN,Enables local overrides for all signals in this register except for TX_DIV_CLK_EN which doesn't need this signal" "0,1" newline bitfld.word 0x0 6. "SERIAL_EN_REG,Forces state of tx_serial_en when OVRD_EN is 1" "0,1" newline bitfld.word 0x0 5. "CLK_EN_REG,Forces state of tx_clk_en when OVRD_EN is 1" "0,1" newline bitfld.word 0x0 4. "DATA_EN_REG,Forces state of tx_data_en when OVRD_EN is HIGH" "0,1" newline bitfld.word 0x0 3. "REFGEN_EN_REG,Register override value for tx_refgen_en. Controls the TX regulator biasing circuitry and the rxdetect comparators when OVRD_EN is HIGH. This function may be overridden by the state of refgen_pwdn_reg" "0,1" newline bitfld.word 0x0 2. "TX_DIV_CLK_EN,Enables the div clock that goes from the TX to the undersampler more appropriately called tx_sampler_clk_en this clock comes after the optional divide by 2 or 4 tx_clk_en must be HIGH to get a clock out" "0,1" newline bitfld.word 0x0 1. "REFGEN_PDN_REG,Register override for refgen pwdn. Used when OVRD_EN is HIGH. Controls the TX regulator biasing circuitry and the rxdetect comparators when OVRD_EN is HIGH" "0,1" newline bitfld.word 0x0 0. "LFPS_HIGH_PRIORITY,When this is set high LFPS priority becomes higher than tx_data" "0,1" group.word 0x90B4++0x1 line.word 0x0 "LANEX_ANA_TX_ALT_BLOCK,Register 5" newline hexmask.word.byte 0x0 8.--15. 1. "RESERVED_15_8,Reserved for Future use" newline bitfld.word 0x0 7. "EN_ALT_BUS,Enables the TX for alt bus mode powers up the TX regulator biasing circuitry and the rxdetect comparators. Needed if manually running the alt bus features" "0,1" newline bitfld.word 0x0 5.--6. "DRV_SOURCE_REG,Forces state of tx_data_source when OVRD_ALT_BUS is HIGH. 00 = serializer data or alt oscillator vp/vph/vphreg/vptx if selected 01 = jtag data differential 10 = LFPS oscillator differential 11 = jtag data common mode drive for test" "serializer data or alt oscillator..,jtag data differential,?,?" newline bitfld.word 0x0 4. "JTAG_DATA_REG,Forces state of jtag_data when OVRD_ALT_BUS is HIGH" "0,1" newline bitfld.word 0x0 1.--3. "TX_RINGO_CNTRL,Enables and connects the various test oscillators to the transmit pins must set drv_source_reg bus correctly. 0XX = All oscillators are disabled 100 = HV oscillator enabled 101 = SVT oscillator enabled 110 = LVT oscillator enabled 111.." "0,1,2,3,4,5,6,7" newline bitfld.word 0x0 0. "OVRD_ALT_BUS,Enables local overrides for alt-bus control signals: DRV_SOURCE_REG and JTAG_DATA_REG" "0,1" group.word 0x90B8++0x1 line.word 0x0 "LANEX_ANA_TX_ALT_AND_LOOPBACK,Register 6" newline hexmask.word.byte 0x0 8.--15. 1. "RESERVED_15_8,Reserved for Future use" newline bitfld.word 0x0 7. "OVRD_TX_LB,Enables the override of the tx_lb_en" "0,1" newline bitfld.word 0x0 6. "TX_LB_EN_REG,Forces state of tx_lb_en when OVRD_TX_LB is enabled" "0,1" newline bitfld.word 0x0 5. "ATB_VPTX,Connects vptx to atb_s_p and gd to atb_s_m" "0,1" newline bitfld.word 0x0 4. "ATB_VREG_TX,Connects TX regulator input reference to atb_s_p and gd to atb_s_m" "0,1" newline bitfld.word 0x0 3. "ATB_VDCCP,Connects vdcc_p to atb_s_p" "0,1" newline bitfld.word 0x0 2. "ATB_VDCCM,Connects vdcc_m to atb_s_m" "0,1" newline bitfld.word 0x0 1. "NOCONN_01,Reserved" "0,1" newline bitfld.word 0x0 0. "SELECT_PMIX_CLK,select pmix_clk for TX clock for ATE test mode" "0,1" group.word 0x90BC++0x1 line.word 0x0 "LANEX_ANA_TX_TX_ATB_REG,Register 7" newline hexmask.word.byte 0x0 8.--15. 1. "RESERVED_15_8,Reserved for Future use" newline bitfld.word 0x0 7. "ATB_PBIAS,Connect real pmos_bias voltage for TX PMOS driver pull up path to atb_s_p and local ground at the pmos_bias block to atb_s_m" "0,1" newline bitfld.word 0x0 6. "ATB_VCM_REP,Connect common mode replica voltage in pmos_bias block to atb_s_p and local ground to atb_s_m" "0,1" newline bitfld.word 0x0 5. "ATB_RXDETREF,Connect RX detect block reference voltage to atb_s_p and local ground to atb_s_m" "0,1" newline bitfld.word 0x0 4. "ATB_TXFP,Connect tx_p to atb_f_p" "0,1" newline bitfld.word 0x0 3. "ATB_TXFM,Connect tx_m to atb_f_m" "0,1" newline bitfld.word 0x0 2. "ATB_TXSP,Connect tx_p to atb_s_p" "0,1" newline bitfld.word 0x0 1. "ATB_TXSM,Connect tx_m to atb_s_m" "0,1" newline bitfld.word 0x0 0. "ATB_VCM,Connect tx_p/tx_m common mode voltage onto atb_s_p and local ground onto atb_s_m" "0,1" group.word 0x90C0++0x1 line.word 0x0 "LANEX_ANA_TX_TX_BOOST,Register 8" newline hexmask.word.byte 0x0 8.--15. 1. "RESERVED_15_8,Reserved for Future use" newline bitfld.word 0x0 7. "OVRD_VBOOST_EN,Enables the overrides on VBOOST_EN_REG" "0,1" newline bitfld.word 0x0 6. "VBOOST_EN_REG,Forces state of tx_vboost_en when OVRD_VBOOST_EN is HIGH" "0,1" newline bitfld.word 0x0 5. "VCON_EN_N,Forces state of vcon_en_n" "0,1" newline bitfld.word 0x0 4. "ATB_VBOOST,Connects vboost to atb_s_p and local ground to Atb_s_m" "0,1" newline bitfld.word 0x0 3. "ATB_VCMBOOST,Connects vcmboost to atb_s_p and local ground to atb_s_m." "0,1" newline bitfld.word 0x0 2. "ATB_F_VBOOST_REF,Enables forcing of tx_vboost_vref through atb_f_p from external" "0,1" newline bitfld.word 0x0 1. "OVRD_VREG_DECAP,Enables override of vreg_decap_en_n signal" "0,1" newline bitfld.word 0x0 0. "VREG_DECAP_EN_N_REG,Forces state of vreg_decap_en_n control signal. Controls whether extra decoupling is switched in for TX regulator output." "0,1" group.word 0x9100++0x1 line.word 0x0 "LANEX_DIG_RX_CDR_FSM_INIT_CTL,Control bits for CDR init phase portion" newline hexmask.word.byte 0x0 9.--15. 1. "RESERVED_15_9,Reserved for Future use" newline bitfld.word 0x0 8. "INIT_CNT_OVRD,Active high override enable bit to select the override INIT_CNT register 0 = Disabled 1 = Enabled" "Disabled,Enabled" newline hexmask.word.byte 0x0 0.--7. 1. "INIT_CNT,Override value for CDR Init Phase" group.word 0x9104++0x1 line.word 0x0 "LANEX_DIG_RX_CDR_FSM_TRACK_CTL,Control bits for CDR track phase portion" newline hexmask.word.byte 0x0 9.--15. 1. "RESERVED_15_9,Reserved for Future use" newline bitfld.word 0x0 8. "TRACK_CNT_OVRD,Active high override enable bit to select the override TRACK_CNT register 0 = Disabled 1 = Enabled" "Disabled,Enabled" newline hexmask.word.byte 0x0 0.--7. 1. "TRACK_CNT,Override value for CDR Track Phase" group.word 0x9108++0x1 line.word 0x0 "LANEX_DIG_RX_CDR_FSM_LOCK_CTL,Control bits for CDR lock phase portion" newline hexmask.word.byte 0x0 9.--15. 1. "RESERVED_15_9,Reserved for Future use" newline bitfld.word 0x0 8. "LOCK_CNT_OVRD,Active high override enable bit to select the override LOCK_CNT register 0 = Disabled 1 = Enabled" "Disabled,Enabled" newline hexmask.word.byte 0x0 0.--7. 1. "LOCK_CNT,Override value for CDR Lock Phase" repeat 9. (list 0x0 0x1 0x2 0x3 0x4 0x8 0x9 0xB 0xC )(list 0x0 0x4 0x8 0xC 0x10 0x20 0x24 0x2C 0x30 ) rgroup.word ($2+0xA000)++0x1 line.word 0x0 "PORTX_STAT_RO_$1,Status Register 0" newline hexmask.word 0x0 4.--15. 1. "RESERVED_15_4,Reserved for Future use" newline bitfld.word 0x0 3. "PLL_LOCK,analog PLL Lock Signal" "0,1" newline bitfld.word 0x0 2. "RX_SQUELCH,analog RX Squelch Signal" "0,1" newline bitfld.word 0x0 1. "RESERVED_1,Reserved" "0,1" newline bitfld.word 0x0 0. "RESERVED_0,Reserved" "0,1" repeat.end repeat 7. (list 0x5 0x6 0x7 0xA 0xD 0xE 0xF )(list 0x0 0x4 0x8 0x14 0x20 0x24 0x28 ) rgroup.word ($2+0xA014)++0x1 line.word 0x0 "PORTX_STAT_RO_$1,Status Register 5" newline hexmask.word 0x0 4.--15. 1. "RESERVED_15_4,Reserved for Future use" newline hexmask.word.byte 0x0 0.--3. 1. "DATAOUT,UTMI+ Output DATAOUT" repeat.end repeat 2. (list 0x0 0x6 )(list 0x0 0x18 ) group.word ($2+0xA040)++0x1 line.word 0x0 "PORTX_OVRD_RW_$1,Override Register 0" newline hexmask.word.byte 0x0 8.--15. 1. "RESERVED_15_8,Reserved for Future use" newline hexmask.word.byte 0x0 4.--7. 1. "OVERRD_ADDR_OVRD_EN,Override Enable for overrd_addr [7:4]" newline hexmask.word.byte 0x0 0.--3. 1. "OVERRD_ADDR,Analog Test Control Override Address [3:0]" repeat.end repeat 10. (list 0x1 0x2 0x3 0x4 0x8 0x9 0xA 0xB 0xE 0xF )(list 0x0 0x4 0x8 0xC 0x1C 0x20 0x24 0x28 0x34 0x38 ) group.word ($2+0xA044)++0x1 line.word 0x0 "PORTX_OVRD_RW_$1,Override Register 1" newline hexmask.word.byte 0x0 8.--15. 1. "RESERVED_15_8,Reserved for Future use" newline bitfld.word 0x0 7. "VBUS_VALID_PU_OVRD_EN,Override Enable for vbus_valid_pu" "0,1" newline bitfld.word 0x0 6. "OTG_PU_OVRD_EN,Override Enable for otg_pu" "0,1" newline bitfld.word 0x0 5. "TX_VREF_VREG_PU_OVRD_EN,Override Enable for tx_vref_vreg_pu" "0,1" newline bitfld.word 0x0 4. "SQRX_PU_OVRD_EN,Override Enable for sqrx_pu" "0,1" newline bitfld.word 0x0 3. "VBUS_VALID_PU,DRVVBUS Input" "0,1" newline bitfld.word 0x0 2. "OTG_PU,OTGDISABLE Input" "0,1" newline bitfld.word 0x0 1. "TX_VREF_VREG_PU,TX hs_driver Comparator Power Up" "0,1" newline bitfld.word 0x0 0. "SQRX_PU,RX squelch Comparator Power Up" "0,1" repeat.end group.word 0xA054++0x1 line.word 0x0 "PORTX_OVRD_RW_5,Override Register 5" newline hexmask.word.byte 0x0 8.--15. 1. "RESERVED_15_8,Reserved for Future use" newline bitfld.word 0x0 6.--7. "XO_CLK_DIV_OVRD_EN,Override Enable for xo_clk_div" "0,1,2,3" newline bitfld.word 0x0 5. "MSTR_OVERRD_BIT_OVRD_EN,Override Enable for mstr_overrd_bit" "0,1" newline bitfld.word 0x0 4. "OVERRD_ADDR_4_OVRD_EN,Override Enable for overrd_addr_4" "0,1" newline bitfld.word 0x0 2.--3. "XO_CLK_DIV,setting reference clock division" "0,1,2,3" newline bitfld.word 0x0 1. "MSTR_OVERRD_BIT,Analog Test Control Master Override" "0,1" newline bitfld.word 0x0 0. "OVERRD_ADDR_4,Analog Test Control Override Address [4]" "0,1" group.word 0xA05C++0x1 line.word 0x0 "PORTX_OVRD_RW_7,Override Register 7" newline hexmask.word.byte 0x0 8.--15. 1. "RESERVED_15_8,Reserved for Future use" newline bitfld.word 0x0 7. "TX_LS_EN_OVRD_EN,Override Enable for tx_ls_en" "0,1" newline bitfld.word 0x0 4.--6. "PWR_SEQ_CLK_DIV_OVRD_EN,Override Enable for pwr_seq_clk_div" "0,1,2,3,4,5,6,7" newline bitfld.word 0x0 3. "TX_LS_EN,TX LS Enable" "0,1" newline bitfld.word 0x0 0.--2. "PWR_SEQ_CLK_DIV,setting power_sequence division" "0,1,2,3,4,5,6,7" group.word 0xA070++0x1 line.word 0x0 "PORTX_OVRD_RW_12,Override Register 12" newline hexmask.word.byte 0x0 8.--15. 1. "RESERVED_15_8,Reserved for Future use" newline bitfld.word 0x0 7. "RES_ACK_OUT_OVRD_EN,Override Enable for res_ack_out" "0,1" newline bitfld.word 0x0 5.--6. "PLL_CLK_DIV_OVRD_EN,Override Enable for pll_clk_div" "0,1,2,3" newline bitfld.word 0x0 4. "PLL_RESET_OVRD_EN,Override Enable for pll_reset" "0,1" newline bitfld.word 0x0 3. "RES_ACK_OUT,Ack resistor tune external requirement" "0,1" newline bitfld.word 0x0 1.--2. "PLL_CLK_DIV,setting MPLL division" "0,1,2,3" newline bitfld.word 0x0 0. "PLL_RESET,MPLL gear_shift" "0,1" group.word 0xA074++0x1 line.word 0x0 "PORTX_OVRD_RW_13,Override Register 13" newline hexmask.word.byte 0x0 8.--15. 1. "RESERVED_15_8,Reserved for Future use" newline bitfld.word 0x0 7. "BIST_MODE_OVRD_EN,Override Enable for bist_mode" "0,1" newline bitfld.word 0x0 6. "TEST_PKT_RPT_OVRD_EN,Override Enable for test_pkt_rpt" "0,1" newline bitfld.word 0x0 4.--5. "XO_CLK_SEL_OVRD_EN,Override Enable for xo_clk_sel" "0,1,2,3" newline bitfld.word 0x0 3. "BIST_MODE,BIST Mode" "0,1" newline bitfld.word 0x0 2. "TEST_PKT_RPT,BIST Test Packet Mode" "0,1" newline bitfld.word 0x0 0.--1. "XO_CLK_SEL,Reference Clock Selection" "0,1,2,3" tree.end tree "USB_PHY1_NCR" base ad:0x31250000 group.long 0x0++0x13 line.long 0x0 "CTRL_0,CTRL_0" bitfld.long 0x0 31. "TEST_BURNIN,All Circuits Activator" "0,1" bitfld.long 0x0 28.--30. "TX_VBOOST_LVL,TX Voltage Boost Level Sets the boosted transmit launch amplitude (mVppd)." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 25.--27. "SSC_RANGE,Spread Spectrum Clock Range Selects the range of spread spectrum modulation when ssc_en is asserted and the PHY is spreading the high-speed transmit clocks. Applies a fixed offset to the phase accumulator." "0,1,2,3,4,5,6,7" bitfld.long 0x0 24. "SSC_EN,Spread Spectrum Enable Enables spread spectrum clock production (0.5% down-spread at ~ 31.5 KHz) in the USB 3.0 femtoPHY. Set this signal to 1'b1." "0,1" newline bitfld.long 0x0 23. "RTUNE_REQ,Resistor Tune Request Assertion triggers a resistor tune request (if one is not already in progress). When this signal is asserted rtune_ack goes high until calibration of the termination impedances is complete. Note that termination.." "0,1" bitfld.long 0x0 22. "REF_USE_XO,Use External Crystal Oscillator" "0,1" newline bitfld.long 0x0 21. "REF_XO_EN,Crystal Oscillator Always On Enable" "0,1" bitfld.long 0x0 20. "REF_REPEAT_CLK_EN,Clock Repeater Buffer Enable" "0,1" newline bitfld.long 0x0 19. "REF_CLKDIV2,Input Reference Clock Divider Control If the input reference clock frequency is greater than 100 MHz this signal must be asserted. The reference clock frequency is then divided by 2 to keep it in the range required by the MPLL. When this.." "0,1" bitfld.long 0x0 18. "REF_USE_PAD,Select Reference Clock Connected to ref_pad_clk_\{p m\} When asserted selects the external ref_pad_clk_\{p m\} inputs as the reference clock source. When ref_use_pad is de-asserted ref_alt_clk_\{p m\} are selected for an on-chip reference.." "0,1" newline bitfld.long 0x0 17. "REF_SSP_EN,Reference Clock Enable for SS function. Enables the reference clock to the prescaler. The ref_ssp_en signal must remain de-asserted until the reference clock is running at the appropriate frequency at which point ref_ssp_en can be asserted." "0,1" hexmask.long.word 0x0 8.--16. 1. "SSC_REF_CLK_SEL,Spread Spectrum Reference Clock Shifting Enables non-standard oscillator frequencies to generate targeted MPLL output rates. Input corresponds to frequency-synthesis coefficient. ssc_ref_clk_sel[8:6] = modulous -1.." newline bitfld.long 0x0 7. "ALT_CLK_EN,Alternate Clock Enable Enables the ref_pcs_clk and ref_pipe_pclk output clocks (if necessary powers up the MPLL)." "0,1" newline bitfld.long 0x0 2. "PIPE_RESET_N,PIPE_RESET_N" "0,1" bitfld.long 0x0 1. "PORTRESET,When asserted this customer-specific signal resets the corresponding port's USB2.0 transmit and receive logic without disabling the clocks within the USB 3.0 femtoPHY. 1: The transmit and receive finite state machines (FSMs) are reset and.." "The transmit and receive FSMs are operational,The transmit and receive finite state machines" newline bitfld.long 0x0 0. "PHY_RESET,Core and State Machine Reset Resets the core and all state machines including the JTAG interface with the exception of the reference clock buffer. Asserting phy_reset triggers the assertion of the tx<#>_reset and rx<#>_reset signals." "0,1" line.long 0x4 "CTRL_1,CTRL_1" bitfld.long 0x4 29.--31. "COMPDISTUNE0,Disconnect Threshold Adjustment Adjusts the voltage level for the threshold used to detect a disconnect event at the host. To enable tuning at the board level connect this bus to a register. 111: + 4.5% 110: + 3% 101: + 1.5%.." "0,1,2,3,4,5,6,7" bitfld.long 0x4 26.--28. "LOS_BIAS,Loss-of-Signal Detector Threshold Level Control Sets the LOS detection threshold level. To enable tuning at the board level connect this bus to a register. 111: 135 mV 110: 120 mV 101: 105 mV 100: 90 mV 011: 75 mV 010:.." "Invalid,?,?,?,?,?,?,?" newline hexmask.long.byte 0x4 21.--25. 1. "LOS_LEVEL,Loss-of-Signal Detector Sensitivity Level Control" bitfld.long 0x4 20. "TEST_POWERDOWN_SSP,SS Function Circuits Power-Down Control Powers down all SS function circuitry in the PHY for IDDQ testing." "0,1" newline bitfld.long 0x4 19. "TEST_POWERDOWN_HSP,HS Function Circuits Power-Down Control Powers down all HS function circuitry in the PHY for IDDQ testing. Before asserting this signal ensure that VDATSRCENB<#> VDATDETENB<#> DCDENB<#> BYPASSSEL<#> and test_burnin are set to 1'b0." "0,1" hexmask.long.byte 0x4 13.--18. 1. "FSEL,Selects the reference clock frequency used for both SS and HS operations. The value for fsel combined with the other clock and enable signals determine the clock frequency used for SS and HS operations and if a shared or separate reference clock is.." newline hexmask.long.byte 0x4 8.--12. 1. "ACJT_LEVEL,1149.6 Receiver Sensitivity Level Control Selects the sensitivity level for the 1149.6 receiver for AC JTAG. Set the level based on the amplitude of the incoming Step during AC JTAG boundary scan testing." bitfld.long 0x4 7. "MPLL_REFSSC_CLK_EN,Double-Word Clock Enable" "0,1" newline hexmask.long.byte 0x4 0.--6. 1. "MPLL_MULTIPLIER,MPLL Frequency Multiplier Control Multiplies the reference clock to a frequency suitable for intended operating speed." line.long 0x8 "CTRL_2,CTRL_2" bitfld.long 0x8 31. "CHRGSEL0,Battery Charging Source Select Determines whether current is sourced onto or sunk from DP<#> or DM<#>. 1: Data source voltage (VDAT_SRC) is sourced onto DM<#> and sunk from DP<#>. 0: Data source voltage (VDAT_SRC) is sourced onto DP<#>.." "Data source voltage,Data source voltage" bitfld.long 0x8 30. "LANE0_TX2RX_LOOPBK,Loopback. When this signal is asserted data from the transmit predriver is looped back to the receive slicers. LOS is bypassed and based on the tx0_en input so that rx0_los = !tx0_data_en." "0,1" newline bitfld.long 0x8 29. "LANE0_EXT_PCLK_REQ,External PIPE Clock Enable Request. When asserted this signal enables the pipeX_pclk output regardless of power state (along with the associated increase in power consumption). You can use this input to enable pipeX_pclk in the P3.." "0,1" hexmask.long.byte 0x8 23.--28. 1. "PCS_TX_DEEMPH_6DB,TX De-Emphasis at 6 dB This static value sets the TX driver de-emphasis value when pipeP_tx_deemph[1:0] is set to 2'b10 (according to the PIPE3 specification). This bus is provided for completeness and as a second potential launch.." newline hexmask.long.byte 0x8 17.--22. 1. "PCS_TX_DEEMPH_3P5DB,TX De-Emphasis at 3.5 dB This static value sets the TX driver de-emphasis value when pipeX_tx_deemph[1:0] is set to 2'b01 (according to the PIPE3 specification). To enable tuning at the board level for RX eye compliance connect this.." hexmask.long.word 0x8 7.--16. 1. "PCS_RX_LOS_MASK_VAL,Configurable Loss-of-Signal Mask Width Sets the number of reference clock cycles to mask the incoming LFPS in U3 and U2 states. Masks the incoming LFPS for the number of reference clock cycles equal to the value of.." newline hexmask.long.byte 0x8 0.--6. 1. "PCS_TX_SWING_FULL,TX Amplitude (Full Swing Mode) This static value sets the launch amplitude of the transmitter. To enable tuning at the board level for RX eye compliance connect this signal to a register." line.long 0xC "CTRL_3,CTRL_3" bitfld.long 0xC 31. "VATESTENB,Analog Test Pin Select Enables analog test voltages to be placed on the ID<#> pin. 1: Analog test voltages can be viewed or applied on ID<#>. 0: Analog test voltages cannot be viewed or applied on ID<#>." "Analog test voltages cannot be viewed or applied..,Analog test voltages can be viewed or applied on.." bitfld.long 0xC 28.--30. "SQRXTUNE0,Adjusts the voltage level for the threshold used to detect valid high-speed data." "0,1,2,3,4,5,6,7" newline bitfld.long 0xC 27. "RX0LOSLFPSEN,Enables the RX LOS LFPS mode use when you want to detect incoming LFPS signals USB3.0" "0,1" bitfld.long 0xC 26. "RETENABLEN,Lowered Digital Supply Indicator." "0,1" newline bitfld.long 0xC 24.--25. "REFCLKSEL,Reference Clock Select for PLL Block" "0,1,2,3" bitfld.long 0xC 21.--23. "OTGTUNE0,VBUS Valid Threshold Adjustment This bus adjusts the voltage level for the VBUS<#> valid threshold. To enable tuning at the board level connect this bus to a register. 111: + 9% 110: + 6% 101: + 3% 100: 0 (default) 011: - 3%.." "0,1,2,3,4,5,6,7" newline bitfld.long 0xC 20. "OTGDISABLE0,OTG Block Disable This controller signal powers down the OTG block which disables the VBUS Valid and Session End comparators. The Session Valid comparator (the output of which is used to enable the pull-up resistor on DP<#> in Device mode).." "OTG block is powered up,OTG block is powered down" bitfld.long 0xC 19. "LOOPBACKENB0,Loopback Test Enable This controller signal places the USB 3.0 femtoPHY in HS Loopback mode which concurrently enables the HS receive and transmit logic. 1: During HS data transmission the HS receive logic is enabled. 0: During HS.." "During HS data transmission,During HS data transmission" newline bitfld.long 0xC 18. "HSXCVREXTCTL0,HS Transceiver Asynchronous Control. This signal asynchronously selects the HS transceiver TX/RX path and can be used with the bypass signals to perform proprietary tests on the HS TX / RX paths. (For information about the bypass signals.." "FS TX/RX path is selected,HS TX/RX path is selected" bitfld.long 0xC 16.--17. "CHRGSRCPUENB0,Charger Source Pull-Up Enable." "0,1,2,3" newline bitfld.long 0xC 15. "AUTORSMENB0,AUTORSMENB0" "0,1" bitfld.long 0xC 14. "ATERESET,Reset Input from Automatic Test Equipment When the USB 3.0 femtoPHY is powered up (not in Suspend or Sleep mode) an automatic tester can use this test signal to disable PHYCLOCK<#> and FREECLK then re-enable them with an aligned phase. 1:.." "PHYCLOCK<#> and FREECLK outputs are available..,PHYCLOCK<#> and FREECLK outputs are disabled" newline bitfld.long 0xC 13. "FSSE0EXT0,USB 1.1 SE0 Generation This controller signal sets the USB (2.0) to an SE0 state. This signal is valid only if FSXCVROWNER<#> is set to 1'b1 and TXENABLEN<#> is set to 1'b0. 1: D+ and D- lines are driven to an SE0 state. 0: D+ and D-.." "D+ and D,D+ and D" bitfld.long 0xC 12. "FSDATAEXT0,USB 1.1 Transmit Data This controller signal sets the USB (2.0) to either a J or K state. This signal is valid only if FSXCVROWNER<#> is set to 1'b1 TXENABLEN<#> is set to 1'b0 and FSSE0EXT<#> is set to 1'b0. 1: D+ and D- lines are.." "D+ and D,D+ and D" newline bitfld.long 0xC 11. "TXENABLEN0,USB 1.1 Data Enable This controller signal enables the FSDATAEXT<#> and FSSE0EXT<#> inputs. TXENABLEN<#> is valid only when the FSXCVROWNER<#> signal is set to 1'b1. 1: FSDATAEXT<#> and FSSE0EXT<#> are disabled. 0: FSDATAEXT<#> and.." "FSDATAEXT<#> and FSSE0EXT<#> are enabled,FSDATAEXT<#> and FSSE0EXT<#> are disabled" bitfld.long 0xC 10. "TXBITSTUFFENH0,High-Byte Transmit Bit-Stuffing Enable This controller signal controls bit stuffing on DATAINH<#>[7:0] when OPMODE<#>[1:0] = 2'b11. 1: Bit stuffing is enabled. 0: Bit stuffing is disabled." "Bit stuffing is disabled,Bit stuffing is enabled" newline bitfld.long 0xC 9. "TXBITSTUFFEN0,Low-Byte Transmit Bit-Stuffing Enable This controller signal controls bit stuffing on DATAIN<#>[7:0] when OPMODE<#>[1:0] = 2'b11. 1: Bit stuffing is enabled. 0: Bit stuffing is disabled." "Bit stuffing is disabled,Bit stuffing is enabled" bitfld.long 0xC 8. "IDPULLUP0,Analog ID Input Sample Enable This controller signal controls ID<#> line sampling. 1: ID<#> pin sampling is enabled and the IDDIG0 output is valid. 0: ID<#> pin sampling is disabled and the IDDIG0 output is not valid." "ID<#> pin sampling is disabled,ID<#> pin sampling is enabled" newline bitfld.long 0xC 7. "VDATSRCENB0,Battery Charging Sourcing Select Enables or disables sourcing for battery charging. 1: Data source voltage (VDAT_SRC) is enabled. 0: Data source voltage (VDAT_SRC) is disabled. During USB 3.0 femtoPHY normal operation set this signal.." "Data source voltage,Data source voltage" bitfld.long 0xC 6. "VDATDETENB0,Battery Charging Attach/Connect Detection Enable Enables or disables attach/connect detection. 1: Data detect voltage (CHG_DET) is enabled. 0: Data detect voltage (CHG_DET) is disabled. During USB 3.0 femtoPHY normal operation set.." "Data detect voltage,Data detect voltage" newline bitfld.long 0xC 5. "DCDENB0,Data Contact Detection Enable. Enables current sourcing on the D+ line. For special applications the IDP_SRC control and the RDM_DWN control are separated. For standard DCD operation in accordance with the Battery Charger v1.2 specification.." "IDP_SRC current is disabled,IDP_SRC current is sourced onto DP<#>" hexmask.long.byte 0xC 0.--4. 1. "LANE0_TX_TERM_OFFSET,Transmitter Termination Offset" line.long 0x10 "CTRL_4,CTRL_4" bitfld.long 0x10 31. "REF_CLK_SW_32K,REF_CLK switch to 32K" "0,1" bitfld.long 0x10 28.--30. "CR_CKDIV,CR clock div" "0,1,2,3,4,5,6,7" newline bitfld.long 0x10 27. "CR_MODE,CR mode" "0,1" bitfld.long 0x10 26. "COMMONONN,Common Block Power-Down Control Controls the power-down signals in the PLL block when the USB 3.0 femtoPHY is in Suspend or Sleep mode. 1: In Suspend or Sleep mode the PLL block is powered down. 0: In Suspend or Sleep mode the PLL.." "In Suspend or Sleep mode,In Suspend or Sleep mode" newline bitfld.long 0x10 25. "BYPASSSEL0,Transmitter Digital Bypass Select Enables/disables Transmitter Digital Bypass mode. The standard FS UART mode is selected by setting HSXCVREXTCTL<#> to 1'b0 and a proprietary HS test mode is selected by setting HSXCVREXTCTL<#> to 1'b1. 1:.." "Transmitter Digital Bypass mode is disabled,Transmitter Digital Bypass mode is enabled" bitfld.long 0x10 24. "BYPASSDPEN0,DP<#> Transmitter Digital Bypass Enable. Enables/disables the DP<#> FS/LS driver (if HSXCVREXTCTL<#> is set to 1'b0) or the DP<#> and DM<#> HS driver (if HSXCVREXTCTL<#> is set to 1'b1) in Transmitter Digital Bypass mode. FS mode is the.." "DP<#> FS/LS driver,DP<#> FS/LS driver" newline bitfld.long 0x10 23. "BYPASSDPDATA0,Data for DP<#> Transmitter Digital Bypass. In Transmitter Digital Bypass mode this signal provides the data that is transmitted on DP<#>. To use this signal BYPASSSEL<#> must be set to 1'b1. When HSXCVREXTCTL<#> is set to 1'b0 the FS/LS.." "HS driver transmits K,HS driver transmits J" bitfld.long 0x10 22. "BYPASSDMEN0,DM<#> Transmitter Digital Bypass Enable. Enables/disables the DM<#> FS/LS driver (if HSXCVREXTCTL<#> is set to 1'b0) in Transmitter Digital Bypass mode. FS mode is the standard UART mode. To use this mode BYPASSSEL<#> must be set to 1'b1." "DM<#> FS/LS driver,DM<#> FS/LS driver" newline bitfld.long 0x10 21. "BYPASSDMDATA0,Data for DM<#> Transmitter Digital Bypass. In Transmitter Digital Bypass mode this signal provides the data that is transmitted on DM<#>. To use this signal BYPASSSEL<#> must be set to 1'b1. When HSXCVREXTCTL<#> is set to 1'b0 the FS/LS.." "DM<#> FS/LS driver drives to a low state,DM<#> FS/LS driver drives to a high state" bitfld.long 0x10 20. "VBUSVLDEXTSEL0,External VBUS Valid Select Selects the VBUSVLDEXT<#> input or the internal Session Valid comparator to indicate when the VBUS<#> signal on the USB cable is valid. 1: VBUSVLDEXT<#> input is used. 0: Internal Session Valid comparator.." "Internal Session Valid comparator is used,VBUSVLDEXT<#> input is used" newline bitfld.long 0x10 19. "VBUSVLDEXT0,External VBUS Valid Indicator Valid in Device mode and only when the VBUSVLDEXTSEL0 signal is set to 1'b1. VBUSVLDEXT<#> indicates whether the VBUS<#> signal on the USB cable is valid. In addition VBUSVLDEXT<#> enables the pull- up resistor.." "VBUS<#> signal is not valid,VBUS<#> signal is valid" bitfld.long 0x10 17.--18. "VDATREFTUNE0,Data Detect Voltage Adjustment. Adjusts the threshold voltage level (Vdat_ref) used to detect data during charger-type detection. 11: - 20% 10: - 10% 01: 0 (default) 00: + 10%" "0,1,2,3" newline hexmask.long.byte 0x10 13.--16. 1. "TXVREFTUNE0,HS DC Voltage Level Adjustment Adjusts the high-speed DC level voltage. To enable tuning at the board level connect this bus to a register. 1111: + 8.75% 1110: + 7.5% 1101: + 6.25% 1100: + 5% 1011: + 3.75% 1010: +.." bitfld.long 0x10 11.--12. "TXRISETUNE0,HS Transmitter Rise/Fall Time Adjustment Adjusts the rise/fall times of the high-speed waveform. To enable tuning at the board level connect this bit to a register. 11: - 10% 10: 0 (default) 01: + 15% 00: + 20%" "0,1,2,3" newline bitfld.long 0x10 9.--10. "TXRESTUNE0,USB Source Impedance Adjustment Some applications require additional devices to be added on the USB such as a series switch which can add significant series resistance. This bus adjusts the driver source impedance (for both pull-up/pull-down.." "0,1,2,3" bitfld.long 0x10 8. "TXPREEMPPULSETUNE0,HS Transmitter Pre-Emphasis Duration Control This signal controls the duration for which the HS pre-emphasis current is sourced onto DP<#> or DM<#>. The HS Transmitter pre- emphasis duration is defined in terms of unit amounts. One.." "Long,Short" newline bitfld.long 0x10 6.--7. "TXPREEMPAMPTUNE0,HS Transmitter Pre-Emphasis Current Control This signal controls the amount of current sourced to DP<#> and DM<#> after a J-to-K or K-to-J transition. The HS Transmitter pre- emphasis current is defined in terms of unit amounts. One unit.." "Disabled,?,?,?" bitfld.long 0x10 4.--5. "TXHSXVTUNE0,Transmitter High-Speed Crossover Adjustment This bus adjusts the voltage at which the DP<#> and DM<#> signals cross while transmitting in HS mode. 11: 0 (default) 10: + 15 mV 01: - 15 mV 00: Reserved" "Reserved,?,?,?" newline hexmask.long.byte 0x10 0.--3. 1. "TXFSLSTUNE0,FS/LS Source Impedance Adjustment Adjusts the low- and full-speed single-ended source impedance while driving high. To enable tuning at the board level connect this bus to a register. 1111: - 5% 0111: -2.5% 0011: 0 (default).." repeat 3. (list 0x5 0x6 0x7 )(list 0x0 0x4 0x8 ) group.long ($2+0x14)++0x3 line.long 0x0 "CTRL_$1,CTRL_5" hexmask.long 0x0 0.--31. 1. "RSVD0,RSVD0" repeat.end rgroup.long 0x80++0x3 line.long 0x0 "STS_0,STS_0" hexmask.long.tbyte 0x0 12.--31. 1. "RSVD0,RSVD0" bitfld.long 0x0 11. "BVALID0,B-Device Session Valid Indicator This controller signal is output from the USB 3.0 femtoPHY's Session. Valid comparator and indicates whether the session for a B-device is valid. 1: Session for the B-device is valid. 0: Session for the.." "Session for the B-device is not valid,Session for the B-device is valid" newline bitfld.long 0x0 10. "AVALID0,A-Device Session Valid Indicator This controller signal is output from the USB 3.0 femtoPHY's Session. Valid comparator and indicates whether the session for an A-device is valid. 1: Session for the A-device is valid. 0: Session for the.." "Session for the A-device is not valid,Session for the A-device is valid" bitfld.long 0x0 9. "OTGSESSVLD0,OTG Device Session Valid Indicator (Low Voltage) This controller signal is output from the USB 3.0 femtoPHY's Session Valid comparator and indicates whether the voltage on VBUS is below the OTG Device Session Valid threshold. 1: The.." "The voltage on VBUS is below the OTG Device..,The voltage on VBUS is above the OTG Device.." newline bitfld.long 0x0 8. "IDDIG0,Mini A/B Plug Indicator This controller signal indicates whether the connected plug is a mini- A or mini-B plug. This signal must be valid within 20 ms after the IDPULLUP0 signal is set to 1'b1. 1: Connected plug is a mini-B plug. 0:.." "Connected plug is a mini-A plug,Connected plug is a mini-B plug" bitfld.long 0x0 7. "HSSQUELCH0,HS Squelch Detector Asynchronous Output. This signal asynchronously outputs the state of the HS squelch detector and can be used with the bypass signals to perform proprietary tests on the HS RX block. (For information about the bypass signals.." "If HSXCVREXTCTL<#> is set to 1'b1,If HSXCVREXTCTL<#> is set to 1'b1" newline bitfld.long 0x0 6. "HSRXDAT0,HS Transceiver Asynchronous Data Output. This signal asynchronously outputs the state of the HS receiver and can be used with the bypass signals to perform proprietary tests on the HS RX block. (For information about the bypass signals see the.." "If HSXCVREXTCTL<#> is set to 1'b1 and..,If HSXCVREXTCTL<#> is set to 1'b1 and.." bitfld.long 0x0 5. "FSVPLUS0,Single-Ended D+ Indicator This controller signal indicates the state of the D+ line in normal operation. 1: Voltage on D+ is high. 0: Voltage on D+ is low." "Voltage on D+ is low,Voltage on D+ is high" newline bitfld.long 0x0 4. "FSVMINUS0,Single-Ended D- Indicator This controller signal indicates the state of the D- line in normal operation. 1: Voltage on D- is high. 0: Voltage on D- is low." "Voltage on D,Voltage on D" bitfld.long 0x0 3. "FSLSRCV0,Differential Data Receive Indicator This controller signal indicates the state of differential data on the USB (2.0) during normal operation. 1: Voltage on D+ is greater than the voltage on D-. 0: Voltage on D+ is less than the voltage.." "Voltage on D+ is less than the voltage on D,Voltage on D+ is greater than the voltage on D" newline bitfld.long 0x0 2. "RTUNE_ACK,Resistor Tune Acknowledge While asserted indicates that a resistor tune is still in progress." "0,1" bitfld.long 0x0 1. "REF_CLKREQ_N,Reference Clock Removal Acknowledge" "0,1" newline bitfld.long 0x0 0. "ALT_CLK_REQ,Alternate Clock Source Request Indicates that the alternate clocks are needed by the slave PCS (that is to boot the master MPLL). Connect to alt_clk_en on the master." "0,1" repeat 7. (list 0x1 0x2 0x3 0x4 0x5 0x6 0x7 )(list 0x0 0x4 0x8 0xC 0x10 0x14 0x18 ) rgroup.long ($2+0x84)++0x3 line.long 0x0 "STS_$1,STS_1" hexmask.long 0x0 0.--31. 1. "RSVD0,RSVD0" repeat.end tree.end endif tree.end tree "USB2 (USB Controller 2)" sif (CORENAME()=="CORTEXR5F") tree "USB2" base ad:0xF1260000 tree "DWC_usb3_block_gbl (USB 3.0 Global Register Block)" group.long (0x0+0x49408)++0x1F line.long 0x0 "GSBUSCFG0,Global SoC Bus Configuration Register 0 This register configures system bus DMA options for the master bus. which may be configured as AHB. AXI. or Native. Options include burst length and cache type (bufferable/posted. cacheable/snoop. and so.." hexmask.long.byte 0x0 28.--31. 1. "DATRDREQINFO,DATRDREQINFO AHB-prot/AXI-cache/OCP-ReqInfo for Data Read (DatRdReqInfo) Input to BUS-GM." newline hexmask.long.byte 0x0 24.--27. 1. "DESRDREQINFO,DESRDREQINFO AHB-prot/AXI-cache/OCP-ReqInfo for Descriptor Read (DesRdReqInfo). Input to BUS-GM." newline hexmask.long.byte 0x0 20.--23. 1. "DATWRREQINFO,DATWRREQINFO AHB-prot/AXI-cache/OCP-ReqInfo for Data Write (DatWrReqInfo). Input to BUS-GM." newline hexmask.long.byte 0x0 16.--19. 1. "DESWRREQINFO,DESWRREQINFO AHB-prot/AXI-cache/OCP-ReqInfo for Descriptor Write (DesWrReqInfo) Input to BUS-GM." newline hexmask.long.byte 0x0 12.--15. 1. "RESERVED_15_12,Reserved for future use" newline bitfld.long 0x0 11. "DATBIGEND,Data Access is Big Endian This bit controls the endian mode for data accesses. - Little-endian (default); - Big-endian; In big-endian mode DMA access (both read and write) for packet data a Byte Invariant Big-Endian mode (see 'Little-Endian.." "0,1" newline bitfld.long 0x0 10. "DESBIGEND,Descriptor Access is Big Endian This bit controls the endian mode for descriptor accesses. - Little-endian (default) - Big-endian In big-endian mode DMA access (both read and write) for descriptors uses a Byte Invariant Big-Endian mode (see.." "0,1" newline rbitfld.long 0x0 8.--9. "RESERVED_9_8,Reserved" "0,1,2,3" newline bitfld.long 0x0 7. "INCR256BRSTENA,INCR256 Burst Type Enable Input to BUS-GM. For the AHB/AXI configuration if software set this bit to 1 the AHB/AXI master uses INCR to do the 256-beat burst." "0,1" newline bitfld.long 0x0 6. "INCR128BRSTENA,INCR128 Burst Type Enable Input to BUS-GM; For the AHB/AXI configuration if software set this bit to 1 the AHB/AXI master uses INCR to do the 128-beat burst." "0,1" newline bitfld.long 0x0 5. "INCR64BRSTENA,INCR64 Burst Type Enable - Input to BUS-GM; For the AHB/AXI configuration if software set this bit to 1 the AHB/AXI master uses INCR to do the 64-beat burst." "0,1" newline bitfld.long 0x0 4. "INCR32BRSTENA,INCR32 Burst Type Enable Input to BUS-GM; For the AHB/AXI configuration if software set this bit to 1 the AHB/AXI master uses INCR to do the 32-beat burst." "0,1" newline bitfld.long 0x0 3. "INCR16BRSTENA,INCR16 Burst Type Enable Input to BUS-GM. For the AHB/AXI configuration if software set this bit to '1' the AHB/AXI master uses INCR to do the 16-beat burst." "0,1" newline bitfld.long 0x0 2. "INCR8BRSTENA,INCR8 Burst Type Enable Input to BUS-GM; For the AHB/AXI configuration if software set this bit to '1' the AHB/AXI master uses INCR to do the 8-beat burst." "0,1" newline bitfld.long 0x0 1. "INCR4BRSTENA,INCR4 Burst Type Enable Input to BUS-GM; For the AXI configuration when this bit is enabled the controller is allowed to do bursts of beat length 1 2 and 4. It is highly recommended that this bit is enabled to prevent descriptor reads and.." "0,1" newline bitfld.long 0x0 0. "INCRBRSTENA,Undefined Length INCR Burst Type Enable (INCRBrstEna) Input to BUS-GM; This bit determines the set of burst lengths the master interface uses. It works in conjunction with the GSBUSCFG0[7:1] enables (INCR256/128/64/32/16/8/4). 0: INCRX burst.." "INCRX burst mode,INCR" line.long 0x4 "GSBUSCFG1,Global SoC Bus Configuration Register 1 xHCI Register Power-On Value: If you are using a standard xHCI host driver. make sure to set the register's power-on value during coreConsultant configuration (DWC_USB3_GSBUSCFG1_INIT parameter) because.." hexmask.long.tbyte 0x4 13.--31. 1. "RESERVED_31_13,Reserved" newline bitfld.long 0x4 12. "EN1KPAGE,1k Page Boundary Enable By default (this bit is disabled) the AXI breaks transfers at the 4k page boundary. When this bit is enabled the AXI master (DMA data) breaks transfers at the 1k page boundary." "0,1" newline hexmask.long.byte 0x4 8.--11. 1. "PIPETRANSLIMIT,AXI Pipelined Transfers Burst Request Limit The field controls the number of outstanding pipelined transfer requests the AXI master pushes to the AXI slave. When the AXI master reaches this limit it does not make any more requests on the.." newline hexmask.long.byte 0x4 0.--7. 1. "RESERVED_7_0,Reserved" line.long 0x8 "GTXTHRCFG,Global Tx Threshold Control Register For more information on - Using this register. refer to 'Packet Threshold and Burst Features for High Latency Systems' section in the Databook. - Selecting values for the fields of this register. see the.." rbitfld.long 0x8 31. "RESERVED_31,Reserved" "0,1" newline rbitfld.long 0x8 30. "RESERVED_30,Reserved" "0,1" newline bitfld.long 0x8 29. "USBTXPKTCNTSEL,USB Transmit Packet Count Enable This field enables/disables the USB transmission multi-packet thresholding: - 0: USB transmission multi-packet thresholding is disabled; the controller can start transmission on the USB after the entire.." "USB transmission multi-packet thresholding is..,USB transmission multi-packet thresholding is.." newline rbitfld.long 0x8 28. "RESERVED_28,Reserved" "0,1" newline hexmask.long.byte 0x8 24.--27. 1. "USBTXPKTCNT,USB Transmit Packet Count This field specifies the number of packets that must be in the TXFIFO before the controller can start transmission for the corresponding USB transaction (burst). This field is only valid when the USB Transmit Packet.." newline hexmask.long.byte 0x8 16.--23. 1. "USBMAXTXBURSTSIZE,USB Maximum TX Burst Size When UsbTxPktCntSel is one this field specifies the Maximum Bulk OUT burst the controller can do. When the system bus is slower than the USB TX FIFO can underrun during a long burst. User can program a.." newline rbitfld.long 0x8 15. "RESERVED_15,Reserved_15" "0,1" newline rbitfld.long 0x8 14. "RESERVED_14,Reserved1(Rsvd/Rs) Register field must write only 0 by the application. The read value must be treated as X (unknown)." "0,1" newline rbitfld.long 0x8 11.--13. "RESERVED_13_11,Reserved (Rsvd/Rs) The register field must write only 0 by the application. The read value must be treated as X (unknown)." "0,1,2,3,4,5,6,7" newline hexmask.long.word 0x8 0.--10. 1. "RESERVED_10_0,Reserved for future use" line.long 0xC "GRXTHRCFG,Global Rx Threshold Control Register In a normal case. a Tx burst starts as soon as one packet is prefetched; an Rx burst starts as soon as 1-packet space is available. This works well as long as the system bus is faster than the USB 3.0 bus (a.." rbitfld.long 0xC 30.--31. "RESERVED_31_30,Reserved" "0,1,2,3" newline bitfld.long 0xC 29. "USBRXPKTCNTSEL,USB Receive Packet Count Enable This field enables/disables the USB reception multi-packet thresholding: - 0: The controller can only start reception on the USB when the RX FIFO has space for at least one packet. - 1: The controller can.." "The controller can only start reception on the..,The controller can only start reception on the.." newline rbitfld.long 0xC 28. "RESERVED_28,Reserved" "0,1" newline hexmask.long.byte 0xC 24.--27. 1. "USBRXPKTCNT,USB Receive Packet Count In host mode this field specifies the space (in terms of the number of packets) that must be available in the RX FIFO before the controller can start the corresponding USB RX transaction (burst). In device mode this.." newline hexmask.long.byte 0xC 19.--23. 1. "USBMAXRXBURSTSIZE,USB Maximum Receive Burst Size In host mode this field specifies the Maximum Bulk IN burst the DWC_usb3 controller can perform. When the system bus is slower than the USB RX FIFO can overrun during a long burst. You can program a.." newline rbitfld.long 0xC 16.--18. "RESERVED_18_16,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0xC 15. "RESERVED_15,Reserved" "0,1" newline rbitfld.long 0xC 13.--14. "RESERVED_14_13,Reserved" "0,1,2,3" newline hexmask.long.word 0xC 0.--12. 1. "RESVISOCOUTSPC,Space reserved in Rx FIFO for ISOC OUT In host mode this field is not applicable and must be programmed to 0. In device mode this value represents the amount of space to be reserved for ISOC OUT packets. The value to be programmed should.." line.long 0x10 "GCTL,Global Core Control Register Refer to /src/DWC_usb3_params.v for details on `DWC_USB3_GCTL_INIT. Note: When Hibernation is not enabled. you can write any value to GblHibernationEn. It always returns 0 when read." hexmask.long.word 0x10 19.--31. 1. "PWRDNSCALE,Power Down Scale (PwrDnScale) The USB3 suspend_clk input replaces pipe3_rx_pclk as a clock source to a small part of the USB3 controller that operates when the SS PHY is in its lowest power (P3) state and therefore does not provide a clock." newline bitfld.long 0x10 18. "MASTERFILTBYPASS,Master Filter Bypass When this bit is set to 1'b1 irrespective of the parameter `DWC_USB3_EN_BUS_FILTERS chosen all the filters in the DWC_usb3_filter module are bypassed. The double synchronizers to mac_clk preceding the filters are.." "0,1" newline bitfld.long 0x10 17. "BYPSSETADDR,Bypass SetAddress in Device Mode. When BYPSSETADDR bit is set the device controller uses the value in the DCFG[DevAddr] bits directly for comparing the device address in the tokens. For simulation you can use this feature to avoid sending.." "0,1" newline bitfld.long 0x10 16. "U2RSTECN,U2RSTECN If the SuperSpeed connection fails during POLL or LMP exchange the device connects at non-SS mode. If this bit is set then device attempts three more times to connect at SS even if it previously failed to operate in SS mode. For each.." "0,1" newline bitfld.long 0x10 14.--15. "FRMSCLDWN,FRMSCLDWN This field scales down device view of a SOF/USOF/ITP duration. For SS/HS mode: - Value of 2'h3 implements interval to be 15.625 us - Value of 2'h2 implements interval to be 31.25 us - Value of 2'h1 implements interval to be 62.5 us -.." "0,1,2,3" newline bitfld.long 0x10 12.--13. "PRTCAPDIR,PRTCAPDIR: Port Capability Direction (PrtCapDir) - 2'b01: for Host configurations - 2'b10: for Device configurations Note: For static Host-only/Device-only applications use DRD Host or DRD Device mode. The combination of GCTL.PrtCapDir=2'b11.." "?,for Host configurations,for Device configurations,?" newline bitfld.long 0x10 11. "CORESOFTRESET,Core Soft Reset (CoreSoftReset) - 1'b0 - No soft reset - 1'b1 - Soft reset to controller Clears the interrupts and all the CSRs except the following registers: - GCTL - GUCTL - GSTS - GSNPSID - GGPIO - GUID - GUSB2PHYCFGn registers -.." "No soft reset,Soft reset to controller" newline bitfld.long 0x10 10. "SOFITPSYNC,SOFITPSYNC If this bit is set to '0' operating in host mode the controller keeps the UTMI/ULPI PHY on the first port in a non-suspended state whenever there is a SuperSpeed port that is not in Rx.Detect SS.Disable and U3. If this bit is set.." "0,1" newline bitfld.long 0x10 9. "U1U2TIMERSCALE,Disable U1/U2 timer Scaledown (U1U2TimerScale). If set to '1' along with GCTL[5:4] (ScaleDown) = 2'bX1 disables the scale down of U1/U2 inactive timer values. This is for simulation mode only." "0,1" newline bitfld.long 0x10 8. "DEBUGATTACH,Debug Attach When this bit is set - SS Link proceeds directly to the Polling link state (after RUN/STOP in the DCTL register is asserted) without checking remote termination; - Link LFPS polling timeout is infinite; - Polling timeout during.." "0,1" newline bitfld.long 0x10 6.--7. "RAMCLKSEL,RAM Clock Select (RAMClkSel) - 2'b00: bus clock - 2'b01: pipe clock (Only used in device mode) - 2'b10: In device mode pipe/2 clock.In Host mode controller switches ram_clk between pipe/2 clock mac2_clk and bus_clk based on the status of.." "bus clock,pipe clock,In device mode,In device mode" newline bitfld.long 0x10 4.--5. "SCALEDOWN,Scale-Down Mode (ScaleDown) When Scale-Down mode is enabled for simulation the controller uses scaled-down timing values resulting in faster simulations. When Scale-Down mode is disabled actual timing values are used. This is required for.." "Disables all scale-downs,Enables scaled down SS timing and repeat values..,No TxEq training sequences are sent,Enables bit 0 and bit 1 scale-down timing values" newline bitfld.long 0x10 3. "DISSCRAMBLE,Disable Scrambling (DisScramble) Transmit request to Link Partner on next transition to Recovery or Polling." "0,1" newline bitfld.long 0x10 2. "U2EXIT_LFPS,U2EXIT_LFPS If this bit is - 0: the link treats 248ns LFPS as a valid U2 exit. - 1: the link waits for 8us of LFPS before it detects a valid U2 exit. This bit is added to improve interoperability with a third-party host/device controller." "the link treats 248ns LFPS as a valid U2 exit,the link waits for 8us of LFPS before it detects.." newline rbitfld.long 0x10 1. "GBLHIBERNATIONEN,GblHibernationEn This bit enables hibernation at the global level. If hibernation is not enabled through this bit the PMU immediately accepts the D0->D3 and D3->D0 power state change requests but does not save or restore any controller.." "D3 and D3,?" newline bitfld.long 0x10 0. "DSBLCLKGTNG,Disable Clock Gating (DsblClkGtng) This bit is set to 1 and the controller is in Low Power mode internal clock gating is disabled. You can set this bit to 1'b1 after Power On Reset." "0,1" line.long 0x14 "GPMSTS,Global Power Management Status Register This debug register gives information on which event caused the hibernation exit. It provides internal status and state machine information. and is for Synopsys use only for debugging purposes. This register.." hexmask.long.byte 0x14 28.--31. 1. "PORTSEL,Global Power Management Status Register PortSel This field selects the port number." newline hexmask.long.word 0x14 17.--27. 1. "RESERVED_27_17,Reserved" newline hexmask.long.byte 0x14 12.--16. 1. "U3WAKEUP,U3Wakeup This field gives the following USB 3.0 port wakeup conditions: - Bit [12]: Overcurrent Detected - Bit [13]: Resume Detected - Bit [14]: Connect Detected - Bit [15]: Disconnect Detected - Bit [16]: Last Connection State" newline rbitfld.long 0x14 10.--11. "RESERVED_10_11,Reserved" "0,1,2,3" newline hexmask.long.word 0x14 0.--9. 1. "U2WAKEUP,U2Wakeup This field indicates the following USB 2.0 port wakeup conditions: - Bit [0]: Overcurrent Detected - Bit [1]: Resume Detected - Bit [2]: Connect Detected - Bit [3]: Disconnect Detected - Bit [4]: Last Connection State - Bit [5]: ID.." line.long 0x18 "GSTS,Global Status Register" hexmask.long.word 0x18 20.--31. 1. "CBELT,Current BELT Value In Host mode this field indicates the minimum value of all received device BELT values and the BELT value that is set by the Set Latency Tolerance Value command." newline hexmask.long.byte 0x18 12.--19. 1. "RESERVED_19_12,Reserved" newline rbitfld.long 0x18 11. "SSIC_IP,This field is not used." "0,1" newline rbitfld.long 0x18 10. "OTG_IP,This field is not used." "0,1" newline rbitfld.long 0x18 9. "BC_IP,Battery Charger Interrupt Pending This field indicates that there is a pending interrupt pertaining to BC in BCEVT register." "0,1" newline rbitfld.long 0x18 8. "ADP_IP,This field is not used." "0,1" newline rbitfld.long 0x18 7. "HOST_IP,Host Interrupt Pending: This field indicates that there is a pending interrupt pertaining to xHC in the Host event queue." "0,1" newline rbitfld.long 0x18 6. "DEVICE_IP,Device Interrupt Pending This field indicates that there is a pending interrupt pertaining to peripheral (device) operation in the Device event queue." "0,1" newline bitfld.long 0x18 5. "CSRTIMEOUT,CSR Timeout When this bit is 1'b1 it indicates that the software performed a write or read to a controller register that could not be completed within `DWC_USB3_CSR_ACCESS_TIMEOUT bus clock cycles (default: h1FFFF)." "0,1" newline bitfld.long 0x18 4. "BUSERRADDRVLD,Bus Error Address Valid (BusErrAddrVld) Indicates that the GBUSERRADDR register is valid and reports the first bus address that encounters a bus error. Note: Only supported in AHB and AXI configurations." "0,1" newline rbitfld.long 0x18 2.--3. "RESERVED_3_2,Reserved" "0,1,2,3" newline rbitfld.long 0x18 0.--1. "CURMOD,Current Mode of Operation (CurMod) Indicates the current mode of operation: - 2'b00: Device mode - 2'b01: Host mode" "Device mode,Host mode,?,?" line.long 0x1C "GUCTL1,Global User Control Register 1" bitfld.long 0x1C 31. "DEV_DECOUPLE_L1L2_EVT,DEV_DECOUPLE_L1L2_EVT - 0: Default behavior no change in device events L1/L2U3 events are not decoupled (old behavior of v2.90a and before) - 1: Feature enabled L1 and L2 events are separated when operating in 2.0 mode. Separate.." "Default behavior,Feature enabled" newline bitfld.long 0x1C 30. "DS_RXDET_MAX_TOUT_CTRL,DS_RXDET_MAX_TOUT_CTRL This bit is used to control the tRxDetectTimeoutDFP timer for the SuperSpeed link. - 0: Default behavior; 12ms is used as tRxDetectTimeoutDFP. - 1: 120ms is used as the tRxDetectTimeoutDFP. This bit is used.." "Default behavior; 12ms is used as..,?" newline bitfld.long 0x1C 29. "FILTER_SE0_FSLS_EOP,FILTER_SE0_FSLS_EOP - 0: Default behavior no change in Linestate check for SE0 detection in FS/LS - 1: Feature enabled FS/LS SE0 is filtered for 2 clocks for detecting EOP This bit is applicable for FS/LS operation. If this feature.." "Default behavior,Feature enabled" newline bitfld.long 0x1C 28. "TX_IPGAP_LINECHECK_DIS,TX_IPGAP_LINECHECK_DIS - 0: Default behavior no change in Linestate check - 1: Feature enabled 2.0 MAC disables Linestate check during HS transmit This bit is applicable for HS operation of u2mac. If this feature is enabled then.." "Default behavior,Feature enabled" newline bitfld.long 0x1C 27. "DEV_TRB_OUT_SPR_IND,DEV_TRB_OUT_SPR_IND - 0: Default behavior no change in TRB status dword - 1: Feature enabled OUT TRB status indicates Short Packet This bit is applicable for device mode only (and ignored in host mode). If the device application.." "Default behavior,Feature enabled" newline bitfld.long 0x1C 26. "DEV_FORCE_20_CLK_FOR_30_CLK,DEV_FORCE_20_CLK_FOR_30_CLK - 0: Default behavior Uses 3.0 clock when operating in 2.0 mode - 1: Feature enabled This bit is applicable (and to be set) for device mode (DCFG.Speed != SS) only. In the 3.0 device controller if.." "Default behavior,Feature enabled" newline bitfld.long 0x1C 25. "P3_IN_U2,P3_IN_U2 - 0: Default behavior When SuperSpeed link is in U2 PowerState P2 is attempted on the PIPE Interface. - 1: When SuperSpeed link is in U2 PowerState P3 is attempted if GUSB3PIPECTL[17] is set. Setting this bit enables P3 Power State.." "Default behavior,When SuperSpeed link is in U2" newline bitfld.long 0x1C 24. "DEV_L1_EXIT_BY_HW,DEV_L1_EXIT_BY_HW - 0: Default behavior disables device L1 hardware exit logic - 1: feature enabled This bit is applicable for device mode (2.0) only. This field enables device controller sending remote wakeup for L1 if the device.." "Default behavior,feature enabled" newline bitfld.long 0x1C 21.--23. "IP_GAP_ADD_ON,This register field is used to add on to the default inter packet gap setting in the USB 2.0 MAC. This should be programmed to a non zero value only in case where you need to increase the default inter packet delay calculations in the USB.." "0,1,2,3,4,5,6,7" newline bitfld.long 0x1C 20. "DEV_LSP_TAIL_LOCK_DIS,DEV_LSP_TAIL_LOCK_DIS - 0: Default behavior enables device lsp lock logic for tail TRB update - 1: Fix disabled This is a bug fix for STAR 9000716195 that affects the CSP mode for OUT endpoints in device mode. The issue is that.." "Default behavior,Fix disabled" newline bitfld.long 0x1C 19. "NAK_PER_ENH_FS,NAK_PER_ENH_FS - 1: Enables performance enhancement for FS async endpoints in the presence of NAKs - 0: Enhancement not applied If a periodic endpoint is present and if a bulk endpoint which is also active is being NAKed by the device.." "Enhancement not applied,Enables performance enhancement for FS async.." newline bitfld.long 0x1C 18. "NAK_PER_ENH_HS,NAK_PER_ENH_HS - 1: Enables performance enhancement for HS async endpoints in the presence of NAKs - 0: Enhancement not applied If a periodic endpoint is present and if a bulk endpoint which is also active is being NAKed by the device.." "Enhancement not applied,Enables performance enhancement for HS async.." newline bitfld.long 0x1C 17. "PARKMODE_DISABLE_SS,PARKMODE_DISABLE_SS This bit is used only in host mode and is for debug purpose only. When this bit is set to '1' all SS bus instances in park mode are disabled." "0,1" newline bitfld.long 0x1C 16. "PARKMODE_DISABLE_HS,PARKMODE_DISABLE_HS This bit is used only in host mode. When this bit is set to '1' all HS bus instances park mode are disabled. To improve performance in park mode the xHCI scheduler queues in three requests of 4 packets each for.." "0,1" newline bitfld.long 0x1C 15. "PARKMODE_DISABLE_FSLS,PARKMODE_DISABLE_FSLS This bit is used only in host mode and is for debug purpose only. When this bit is set to '1' all FS/LS bus instances in park mode disabled." "0,1" newline rbitfld.long 0x1C 13.--14. "RESERVED_14_13,Reserved" "0,1,2,3" newline rbitfld.long 0x1C 12. "DISUSB2REFCLKGTNG,Disable ref_clk gating for 2.0 PHY (DisUSB2RefClkGtng) If ref_clk gating is disabled then the ref_clk input cannot be turned off to the USB 2.0 PHY and controller. This is independent of the GCTL[DisClkGtng] setting. - 1'b0: ref_clk.." "ref_clk gating enabled for USB 2,ref_clk gating disabled for USB 2" newline rbitfld.long 0x1C 11. "DISREFCLKGTNG,Disable ref_clk gating (DisRefClkGtng) If the ref_clk gating is disabled then input ref_clk cannot be turned off to SSPHY and controller. This is independent of GCTL[DisClkGtng] setting. - 1'b0: ref_clk gating Enabled for SSPHY - 1'b1:.." "ref_clk gating Enabled for SSPHY,ref_clk gating Disabled for SSPHY" newline bitfld.long 0x1C 10. "RESUME_OPMODE_HS_HOST,RESUME_OPMODE_HS_HOST This bit is used only in host mode and is for USB 2.0 opmode behavior in HS Resume. - When this bit is set to '1' the UTMI/ULPI opmode will be changed to 'normal' along with HS terminations after EOR. This.." "0,1" newline bitfld.long 0x1C 9. "DEV_HS_NYET_BULK_SPR,DEV_HS_NYET_BULK_SPR - 0: Default behavior no change in device response - 1: Feature enabled HS bulk OUT short packet gets NYET response This bit is applicable for device mode only (and ignored in host mode) to be used in 2.0.." "Default behavior,Feature enabled" newline bitfld.long 0x1C 8. "L1_SUSP_THRLD_EN_FOR_HOST,L1_SUSP_THRLD_EN_FOR_HOST This bit is used only in host mode. The host controller asserts the utmi_l1_suspend_n and utmi_sleep_n output signals (see 'LPM Interface Signals' table in the Databook) as follows: The controller.." "0,1" newline hexmask.long.byte 0x1C 4.--7. 1. "L1_SUSP_THRLD_FOR_HOST,L1_SUSP_THRLD_FOR_HOST This field is effective only when the L1_SUSP_THRLD_EN_FOR_HOST bit is set to 1. For more details refer to the description of the L1_SUSP_THRLD_EN_FOR_HOST bit." newline bitfld.long 0x1C 3. "HC_ERRATA_ENABLE,Host ELD Enable (HELDEn) When this bit is set to 1 it enables the Exit Latency Delta (ELD) support defined in the xHCI 1.0 Errata. This bit is used only in the host mode. This bit has to be set to 1 in Host mode." "0,1" newline bitfld.long 0x1C 2. "HC_PARCHK_DISABLE,Host Parameter Check Disable (HParChkDisable) When this bit is set to '0' (by default) the xHC checks that the input slot/EP context fields comply to the xHCI Specification. Upon detection of a parameter error during command execution.." "0,1" newline bitfld.long 0x1C 1. "OVRLD_L1_SUSP_COM,OVRLD_L1_SUSP_COM If this bit is set the utmi_l1_suspend_com_n is overloaded with the utmi_sleep_n signal. This bit is usually set if the PHY stops the port clock during L1 sleep condition. Note: The recommended connection for the.." "For Synopsys PHY,?" newline bitfld.long 0x1C 0. "LOA_FILTER_EN,LOA_FILTER_EN If this bit is set the USB 2.0 port babble is checked at least three consecutive times before the port is disabled. This prevents false triggering of the babble condition when using low quality cables. Note: This bit is valid.." "0,1" rgroup.long (0x20+0x49408)++0x3 line.long 0x0 "GSNPSID,Global Synopsys ID Register This is a read-only register that contains the release number of the controller." hexmask.long 0x0 0.--31. 1. "SYNOPSYSID,Synopsys ID - SynopsysID[31:16] indicates Core Identification Number. 0x5533 is ASCII for U3 (DWC_usb3). - SynopsysID[15:0] indicates the release number. Current Release is 3.30a. Software uses this register to configure release-specific.." group.long (0x24+0x49408)++0xB line.long 0x0 "GGPIO,Global General Purpose Input/Output Register The application can use this register for general purpose input and output ports or for debugging." hexmask.long.word 0x0 16.--31. 1. "GPO,General Purpose Output The value of this field is driven out on the gp_out[15:0] output port." newline hexmask.long.word 0x0 0.--15. 1. "GPI,General Purpose Input The read value of this field reflects the gp_in[15:0] input signal value. Note: Register bit-bash test should not check for reset value of this field since its not predictable; depends on the gp_in port." line.long 0x4 "GUID,Global User ID Register This is a read/write register containing the User ID. The power-on value for this register is specified as the User Identification Register. Power-on value during coreConsultant configuration (parameter DWC_USB3_USERID). This.." hexmask.long 0x4 0.--31. 1. "USERID,USERID Application-programmable ID field." line.long 0x8 "GUCTL,Global User Control Register: This register provides a few options for the software to control the controller behavior in the Host mode. Most of the options are used to improve host inter-operability with different devices." hexmask.long.word 0x8 22.--31. 1. "REFCLKPER,REFCLKPER This field indicates in terms of nano seconds the period of ref_clk. The default value of this register is set to 'h8 (8ns/125 MHz). This field needs to be updated during power-on initialization if GCTL.SOFITPSYNC or.." newline bitfld.long 0x8 21. "NOEXTRDL,No Extra Delay Between SOF and the First Packet(NoExtrDl) Some HS devices misbehave when the host sends a packet immediately after a SOF. However adding an extra delay between a SOF and the first packet can reduce the USB data rate and.." "Host waits for 2 microseconds after a SOF before..,Host doesn't wait after a SOF before it sends.." newline rbitfld.long 0x8 18.--20. "RESERVED_20_18,Reserved" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 17. "SPRSCTRLTRANSEN,Sparse Control Transaction Enable Some devices are slow in responding to Control transfers. Scheduling multiple transactions in one microframe/frame can cause these devices to misbehave. If this bit is set to 1'b1 the host controller.." "0,1" newline bitfld.long 0x8 16. "RESBWHSEPS,Reserving 85% Bandwidth for HS Periodic EPs (ResBwHSEPS) By default HC reserves 80% of the bandwidth for periodic EPs. If this bit is set the bandwidth is relaxed to 85% to accommodate two high speed high bandwidth ISOC EPs. USB 2.0.." "0,1" newline rbitfld.long 0x8 15. "RESERVED_15,Reserved" "0,1" newline bitfld.long 0x8 14. "USBHSTINAUTORETRYEN,Host IN Auto Retry (USBHstInAutoRetryEn) When set this field enables the Auto Retry feature. For IN transfers (non-isochronous) that encounter data packets with CRC errors or internal overrun scenarios the auto retry feature causes.." "Auto Retry Disabled,Auto Retry Enabled" newline bitfld.long 0x8 13. "ENOVERLAPCHK,Enable Check for LFPS Overlap During Remote Ux Exit: If this bit is set to - 1'b1: The SuperSpeed link when exiting U1/U2/U3 waits for either the remote link LFPS or TS1/TS2 training symbols before it confirms that the LFPS handshake is.." "When the link exists U1/U2/U3 because of a..,The SuperSpeed link when exiting U1/U2/U3 waits.." newline bitfld.long 0x8 12. "EXTCAPSUPPTEN,External Extended Capability Support Enable (ExtCapSuptEN) When set this field enables extended capabilities to be implemented outside the controller. When the ExtCapSupEN is set and the Debug Capability is enabled the Next Capability.." "0,1" newline bitfld.long 0x8 11. "INSRTEXTRFSBODI,Insert Extra Delay Between FS Bulk OUT Transactions (InsrtExtrFSBODl). Some FS devices are slow to receive Bulk OUT data and can get stuck when there are consecutive Bulk OUT transactions with short inter-transaction delays. This bit is.." "Host doesn't insert extra delay between..,Host inserts about 12us extra delay between.." newline bitfld.long 0x8 9.--10. "DTCT,Device Timeout Coarse Tuning (DTCT) This field is a Host mode parameter which determines how long the host waits for a response from device before considering a timeout. The controller first checks the DTCT value. If it is 0 then the timeout value.." "0,1,2,3" newline hexmask.long.word 0x8 0.--8. 1. "DTFT,Device Timeout Fine Tuning (DTFT) This field is a Host mode parameter which determines how long the host waits for a response from device before considering a timeout. For the DTFT field to take effect DTCT must be set to 2'b00. The DTFT value is.." rgroup.long (0x30+0x49408)++0x7 line.long 0x0 "GBUSERRADDRLO,Gobal SoC Bus Error Address Register - Low This is an alternate register for the GBUSERRADDR register." hexmask.long 0x0 0.--31. 1. "BUSERRADDR,Bus Address - Low (BusAddrLo) This register contains the lower 32 bits of the first bus address that encountered a SoC bus error. It is valid when the GSTS.BusErrAddrVld field is 1. It can only be cleared by resetting the controller. Note:.." line.long 0x4 "GBUSERRADDRHI,Gobal SoC Bus Error Address Register - High This is an alternate register for the GBUSERRADDR register." hexmask.long 0x4 0.--31. 1. "BUSERRADDR,Bus Address - High (BusAddrHi) This register contains the higher 32 bits of the first bus address that encountered a SoC bus error. It is valid when the GSTS.BusErrAddrVld field is 1. It can only be cleared by resetting the controller. Note:.." group.long (0x38+0x49408)++0x7 line.long 0x0 "GPRTBIMAPLO,Global SS Port to Bus Instance Mapping Register - Low This is an alternate register for the GPRTBIMAP register. Register fields are read-write with respect to number of port instantiated. writeAsRead constraint is added to limit side effects.." hexmask.long.byte 0x0 28.--31. 1. "BINUM8,BINUM8: SS USB Instance Number for Port 8. Application-programmable ID field." newline hexmask.long.byte 0x0 24.--27. 1. "BINUM7,BINUM7: SS USB Instance Number for Port 7. Application-programmable ID field." newline hexmask.long.byte 0x0 20.--23. 1. "BINUM6,BINUM6: SS USB Instance Number for Port 6. Application-programmable ID field." newline hexmask.long.byte 0x0 16.--19. 1. "BINUM5,BINUM5: SS USB Instance Number for Port 5. Application-programmable ID field." newline hexmask.long.byte 0x0 12.--15. 1. "BINUM4,BINUM4: SS USB Instance Number for Port 4. Application-programmable ID field." newline hexmask.long.byte 0x0 8.--11. 1. "BINUM3,BINUM3: SS USB Instance Number for Port 3. Application-programmable ID field." newline hexmask.long.byte 0x0 4.--7. 1. "BINUM2,BINUM2: SS USB Instance Number for Port 2. Application-programmable ID field." newline hexmask.long.byte 0x0 0.--3. 1. "BINUM1,BINUM1: SS USB Instance Number for Port 1. Application-programmable ID field." line.long 0x4 "GPRTBIMAPHI,Global SS Port to Bus Instance Mapping Register - High This is an alternate register for the GPRTBIMAP register. For a configuration with number of USB 3.0 ports same as number of SS Bus Instances. do not remap during debug session. If you.." hexmask.long.byte 0x4 28.--31. 1. "RESERVED_31_28,Reserved" newline hexmask.long.byte 0x4 24.--27. 1. "BINUM15,BINUM15: SS USB Instance Number for Port 15. Application-programmable ID field." newline hexmask.long.byte 0x4 20.--23. 1. "BINUM14,BINUM14: SS USB Instance Number for Port 14. Application-programmable ID field." newline hexmask.long.byte 0x4 16.--19. 1. "BINUM13,BINUM13: SS USB Instance Number for Port 13. Application-programmable ID field." newline hexmask.long.byte 0x4 12.--15. 1. "BINUM12,BINUM12: SS USB Instance Number for Port 12. Application-programmable ID field." newline hexmask.long.byte 0x4 8.--11. 1. "BINUM11,BINUM11: SS USB Instance Number for Port 11. Application-programmable ID field." newline hexmask.long.byte 0x4 4.--7. 1. "BINUM10,BINUM10: SS USB Instance Number for Port 10. Application-programmable ID field." newline hexmask.long.byte 0x4 0.--3. 1. "BINUM9,BINUM9: SS USB Instance Number for Port 9. Application-programmable ID field." rgroup.long (0x40+0x49408)++0x7 line.long 0x0 "GHWPARAMS0,Global Hardware Parameters Register 0 This register contains the hardware configuration options that you can select in the coreConsultant GUI. For a description of each parameter. refer to the 'Parameter Descriptions' chapter in the Databook." hexmask.long.byte 0x0 24.--31. 1. "GHWPARAMS0_31_24,`DWC_USB3_AWIDTH" newline hexmask.long.byte 0x0 16.--23. 1. "GHWPARAMS0_23_16,`DWC_USB3_SDWIDTH" newline hexmask.long.byte 0x0 8.--15. 1. "GHWPARAMS0_15_8,`DWC_USB3_MDWIDTH" newline bitfld.long 0x0 6.--7. "GHWPARAMS0_7_6,`DWC_USB3_SBUS_TYPE" "0,1,2,3" newline bitfld.long 0x0 3.--5. "GHWPARAMS0_5_3,`DWC_USB3_MBUS_TYPE" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 0.--2. "GHWPARAMS0_2_0,`DWC_USB3_MODE" "0,1,2,3,4,5,6,7" line.long 0x4 "GHWPARAMS1,Global Hardware Parameters Register 1 This register contains the hardware configuration options that you can select in the coreConsultant GUI. For a description of each parameter. refer to the 'Parameter Descriptions' chapter in the Databook." bitfld.long 0x4 31. "GHWPARAMS1_31,`DWC_USB3_EN_DBC" "0,1" newline bitfld.long 0x4 30. "GHWPARAMS1_30,`DWC_USB3_RM_OPT_FEATURES" "0,1" newline bitfld.long 0x4 29. "GHWPARAMS1_29,Reserved1" "0,1" newline bitfld.long 0x4 28. "GHWPARAMS1_28,`DWC_USB3_RAM_BUS_CLKS_SYNC" "0,1" newline bitfld.long 0x4 27. "GHWPARAMS1_27,`DWC_USB3_MAC_RAM_CLKS_SYNC" "0,1" newline bitfld.long 0x4 26. "GHWPARAMS1_26,`DWC_USB3_MAC_PHY_CLKS_SYNC" "0,1" newline bitfld.long 0x4 24.--25. "GHWPARAMS1_25_24,`DWC_USB3_EN_PWROPT" "0,1,2,3" newline bitfld.long 0x4 23. "GHWPARAMS1_23,`DWC_USB3_SPRAM_TYP" "0,1" newline bitfld.long 0x4 21.--22. "GHWPARAMS1_22_21,`DWC_USB3_NUM_RAMS" "0,1,2,3" newline hexmask.long.byte 0x4 15.--20. 1. "GHWPARAMS1_20_15,`DWC_USB3_DEVICE_NUM_INT For details on `DWC_USB3_DEVICE_NUM_INT refer to /src/DWC_usb3_params.v file." newline bitfld.long 0x4 12.--14. "GHWPARAMS1_14_12,`DWC_USB3_ASPACEWIDTH" "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 9.--11. "GHWPARAMS1_11_9,`DWC_USB3_REQINFOWIDTH" "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 6.--8. "GHWPARAMS1_8_6,`DWC_USB3_DATAINFOWIDTH" "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 3.--5. "GHWPARAMS1_5_3,`DWC_USB3_BURSTWIDTH-1" "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 0.--2. "GHWPARAMS1_2_0,`DWC_USB3_IDWIDTH-1" "0,1,2,3,4,5,6,7" repeat 2. (list 0x2 0x8 )(list 0x0 0x4B8 ) rgroup.long ($2+0x48+0x49408)++0x3 line.long 0x0 "GHWPARAMS$1,Global Hardware Parameters Register 2 This register contains the hardware configuration options that you can select in the coreConsultant GUI. For a description of each parameter. refer to the 'Parameter Descriptions' chapter in the Databook." hexmask.long 0x0 0.--31. 1. "GHWPARAMS2_31_0,`DWC_USB3_USERID" repeat.end rgroup.long (0x4C+0x49408)++0x13 line.long 0x0 "GHWPARAMS3,Global Hardware Parameters Register 3 This register contains the hardware configuration options that you can select in the coreConsultant GUI. For a description of each parameter. refer to the 'Parameter Descriptions' chapter in the Databook." bitfld.long 0x0 31. "GHWPARAMS3_31,Reserved" "0,1" newline hexmask.long.byte 0x0 23.--30. 1. "GHWPARAMS3_30_23,`DWC_USB3_CACHE_TOTAL_XFER_RESOURCES" newline hexmask.long.byte 0x0 18.--22. 1. "GHWPARAMS3_22_18,`DWC_USB3_NUM_IN_EPS" newline hexmask.long.byte 0x0 12.--17. 1. "GHWPARAMS3_17_12,`DWC_USB3_NUM_EPS" newline bitfld.long 0x0 11. "GHWPARAMS3_11,`DWC_USB3_ULPI_CARKIT" "0,1" newline bitfld.long 0x0 10. "GHWPARAMS3_10,`DWC_USB3_VENDOR_CTL_INTERFACE" "0,1" newline bitfld.long 0x0 8.--9. "GHWPARAMS3_9_8,Reserved" "0,1,2,3" newline bitfld.long 0x0 6.--7. "GHWPARAMS3_7_6,`DWC_USB3_HSPHY_DWIDTH" "0,1,2,3" newline bitfld.long 0x0 4.--5. "GHWPARAMS3_5_4,`DWC_USB3_FSPHY_INTERFACE" "0,1,2,3" newline bitfld.long 0x0 2.--3. "GHWPARAMS3_3_2,`DWC_USB3_HSPHY_INTERFACE" "0,1,2,3" newline bitfld.long 0x0 0.--1. "GHWPARAMS3_1_0,`DWC_USB3_SSPHY_INTERFACE" "0,1,2,3" line.long 0x4 "GHWPARAMS4,Global Hardware Parameters Register 4 This register contains the hardware configuration options that you can select in the coreConsultant GUI. For a description of each parameter. refer to the 'Parameter Descriptions' chapter in the Databook." hexmask.long.byte 0x4 28.--31. 1. "GHWPARAMS4_31_28,`DWC_USB3_BMU_LSP_DEPTH" newline hexmask.long.byte 0x4 24.--27. 1. "GHWPARAMS4_27_24,`DWC_USB3_BMU_PTL_DEPTH-1" newline bitfld.long 0x4 23. "GHWPARAMS4_23,`DWC_USB3_EN_ISOC_SUPT" "0,1" newline bitfld.long 0x4 22. "GHWPARAMS4_22,Reserved" "0,1" newline bitfld.long 0x4 21. "GHWPARAMS4_21,`DWC_USB3_EXT_BUFF_CONTROL" "0,1" newline hexmask.long.byte 0x4 17.--20. 1. "GHWPARAMS4_20_17,`DWC_USB3_NUM_SS_USB_INSTANCES" newline hexmask.long.byte 0x4 13.--16. 1. "GHWPARAMS4_16_13,`DWC_USB3_HIBER_SCRATCHBUFS Number of external scratchpad buffers the controller requires to save its internal state in the device mode. Each buffer is assumed to be 4KB. The scratchpad buffer array must have this many buffer pointers." newline bitfld.long 0x4 12. "GHWPARAMS4_12,Reserved" "0,1" newline bitfld.long 0x4 11. "GHWPARAMS4_11,Reserved" "0,1" newline bitfld.long 0x4 9.--10. "GHWPARAMS4_10_9,Reserved" "0,1,2,3" newline bitfld.long 0x4 7.--8. "GHWPARAMS4_8_7,Reserved" "0,1,2,3" newline bitfld.long 0x4 6. "GHWPARAMS4_6,Reserved" "0,1" newline hexmask.long.byte 0x4 0.--5. 1. "GHWPARAMS4_5_0,`DWC_USB3_CACHE_TRBS_PER_TRANSFER" line.long 0x8 "GHWPARAMS5,Global Hardware Parameters Register 5 This register contains the hardware configuration options that you can select in the coreConsultant GUI. For a description of each parameter. refer to the 'Parameter Descriptions' chapter in the Databook." hexmask.long.byte 0x8 28.--31. 1. "GHWPARAMS5_31_28,Reserved" newline hexmask.long.byte 0x8 22.--27. 1. "GHWPARAMS5_27_22,`DWC_USB3_DFQ_FIFO_DEPTH" newline hexmask.long.byte 0x8 16.--21. 1. "GHWPARAMS5_21_16,`DWC_USB3_DWQ_FIFO_DEPTH" newline hexmask.long.byte 0x8 10.--15. 1. "GHWPARAMS5_15_10,`DWC_USB3_TXQ_FIFO_DEPTH" newline hexmask.long.byte 0x8 4.--9. 1. "GHWPARAMS5_9_4,`DWC_USB3_RXQ_FIFO_DEPTH" newline hexmask.long.byte 0x8 0.--3. 1. "GHWPARAMS5_3_0,`DWC_USB3_BMU_BUSGM_DEPTH" line.long 0xC "GHWPARAMS6,Global Hardware Parameters Register 6 This register contains the hardware configuration options that you can select in the coreConsultant GUI. For a description of each parameter. refer to the 'Parameter Descriptions' chapter in the Databook." hexmask.long.word 0xC 16.--31. 1. "GHWPARAMS6_31_16,`DWC_USB3_RAM0_DEPTH" newline bitfld.long 0xC 15. "BUSFLTRSSUPPORT,`DWC_USB3_EN_BUS_FILTERS" "0,1" newline bitfld.long 0xC 14. "BCSUPPORT,`DWC_USB3_EN_BC" "0,1" newline bitfld.long 0xC 13. "OTG_SS_SUPPORT,Reserved" "0,1" newline bitfld.long 0xC 12. "ADPSUPPORT,`DWC_USB3_EN_ADP" "0,1" newline bitfld.long 0xC 11. "HNPSUPPORT,Reserved" "0,1" newline bitfld.long 0xC 10. "SRPSUPPORT,Reserved" "0,1" newline bitfld.long 0xC 8.--9. "GHWPARAMS6_9_8,Reserved" "0,1,2,3" newline bitfld.long 0xC 7. "GHWPARAMS6_7,`DWC_USB3_EN_FPGA" "0,1" newline bitfld.long 0xC 6. "GHWPARAMS6_6,`DWC_USB3_EN_DBG_PORTS" "0,1" newline hexmask.long.byte 0xC 0.--5. 1. "GHWPARAMS6_5_0,`DWC_USB3_PSQ_FIFO_DEPTH" line.long 0x10 "GHWPARAMS7,Global Hardware Parameters Register 7 This register contains the hardware configuration options that you can select in the coreConsultant GUI. For a description of each parameter. refer to the 'Parameter Descriptions' chapter in the Databook." hexmask.long.word 0x10 16.--31. 1. "GHWPARAMS7_31_16,`DWC_USB3_RAM2_DEPTH" newline hexmask.long.word 0x10 0.--15. 1. "GHWPARAMS7_15_0,`DWC_USB3_RAM1_DEPTH" group.long (0x60+0x49408)++0x3 line.long 0x0 "GDBGFIFOSPACE,Global Debug Queue/FIFO Space Available Register Bit Bash test should not be done on this debug register." hexmask.long.word 0x0 16.--31. 1. "SPACE_AVAILABLE,SPACE_AVAILABLE" newline hexmask.long.byte 0x0 9.--15. 1. "RESERVED_15_9,Reserved" newline hexmask.long.word 0x0 0.--8. 1. "FIFO_QUEUE_SELECT,FIFO/Queue Select (or) Port-Select - FIFO/Queue Select[8:5] indicates the FIFO/Queue Type - FIFO/Queue Select[4:0] indicates the FIFO/Queue Number For example 9'b0_0010_0001 refers to RxFIFO_1 and 9'b0_0101_1110 refers to TxReqQ_30. -.." rgroup.long (0x64+0x49408)++0xB line.long 0x0 "GDBGLTSSM,Global Debug LTSSM Register In multi-port host configuration. the port-number is defined by Port-Select[3:0] field in the GDBGFIFOSPACE register. Note: - GDBGLTSSM register is not applicable for USB 2.0-only mode. - Bit Bash test should not be.." bitfld.long 0x0 31. "RESERVED_31_31,Reserved" "0,1" newline bitfld.long 0x0 30. "RXELECIDLE,RxElecidle For description of RxElecIdle see table 5-4 'Status Interface Signals' of the PIPE3 Specification." "0,1" newline bitfld.long 0x0 29. "X3_XS_SWAPPING,Reserved" "0,1" newline bitfld.long 0x0 28. "X3_DS_HOST_SHUTDOWN,Reserved" "0,1" newline bitfld.long 0x0 27. "PRTDIRECTION,Reserved" "0,1" newline bitfld.long 0x0 26. "LTDBTIMEOUT,LTDB Timeout (LTDBTimeout)" "0,1" newline hexmask.long.byte 0x0 22.--25. 1. "LTDBLINKSTATE,LTDB Link State (LTDBLinkState)" newline hexmask.long.byte 0x0 18.--21. 1. "LTDBSUBSTATE,LTDB Sub-State (LTDBSubState)" newline bitfld.long 0x0 17. "ELASTICBUFFERMODE,Elastic Buffer Mode (ElasticBufferMode) For field definition refer to Table 5-3 of the PIPE3 specification." "0,1" newline bitfld.long 0x0 16. "TXELECLDLE,Tx Elec Idle (TxElecIdle) For field definition refer to Table 5-3 of the PIPE3 specification." "0,1" newline bitfld.long 0x0 15. "RXPOLARITY,Rx Polarity (RxPolarity) For field definition refer to Table 5-3 of the PIPE3 specification." "0,1" newline bitfld.long 0x0 14. "TXDETRXLOOPBACK,Tx Detect Rx/Loopback (TxDetRxLoopback) For field definition refer to Table 5-3 of the PIPE3 specification." "0,1" newline bitfld.long 0x0 11.--13. "LTDBPHYCMDSTATE,LTSSM PHY command State (LTDBPhyCmdState) - 000: PHY_IDLE (PHY command state is in IDLE. No PHY request pending) - 001: PHY_DET (Request to start Receiver detection) - 010: PHY_DET_3 (Wait for Phy_Status (Receiver detection)) - 011:.." "P1/P2/P3 request),PHY_DET,?,?,?,?,?,?" newline bitfld.long 0x0 9.--10. "POWERDOWN,POWERDOWN (PowerDown) For field definition refer to Table 5-3 of the PIPE3 specification." "0,1,2,3" newline bitfld.long 0x0 8. "RXEQTRAIN,RxEq Train For field definition refer to Table 5-3 of the PIPE3 specification." "0,1" newline bitfld.long 0x0 6.--7. "TXDEEMPHASIS,TXDEEMPHASIS (TxDeemphasis) For field definition refer to Table 5-3 of the PIPE3 specification." "0,1,2,3" newline bitfld.long 0x0 3.--5. "LTDBCLKSTATE,LTSSM Clock State (LTDBClkState) In multi-port host configuration the port number is defined by Port-Select[3:0] field in the GDBGFIFOSPACE register. Note: GDBGLTSSM register is not applicable for USB 2.0-only mode. - 000: CLK_NORM (PHY is.." "CLK_NORM,CLK_TO_P3,?,?,?,?,?,?" newline bitfld.long 0x0 2. "TXSWING,Tx Swing (TxSwing) For field definition refer to Table 5-3 of the PIPE3 specification." "0,1" newline bitfld.long 0x0 1. "RXTERMINATION,Rx Termination (RxTermination) For details on `DWC_USB3_PIPE_RXTERM_RESET_VAL refer to /src/DWC_usb3_params.v" "0,1" newline bitfld.long 0x0 0. "TXONESZEROS,Tx Ones/Zeros (TxOnesZeros) For field definition refer to Table 5-3 of the PIPE3 specification." "0,1" line.long 0x4 "GDBGLNMCC,Global Debug LNMCC Register Bit Bash test should not be done on this debug register." hexmask.long.tbyte 0x4 9.--31. 1. "RESERVED_31_9,Reserved" newline hexmask.long.word 0x4 0.--8. 1. "LNMCC_BERC,This field indicates the bit error rate information for the port selected in the GDBGFIFOSPACE.PortSelect field. This field is for debug purposes only." line.long 0x8 "GDBGBMU,Global Debug BMU Register Bit Bash test should not be done on this debug register." hexmask.long.tbyte 0x8 8.--31. 1. "BMU_BCU,BMU_BCU Debug information" newline hexmask.long.byte 0x8 4.--7. 1. "BMU_DCU,BMU_DCU Debug information" newline hexmask.long.byte 0x8 0.--3. 1. "BMU_CCU,BMU_CCU Debug information" group.long (0x70+0x49408)++0x3 line.long 0x0 "GDBGLSPMUX_HST,Global Debug LSP MUX Register - Host This register is for internal use only. If DWC_USB3_PRESERVE_LOGIC_ANALYZER_SELECT is enabled during controller configuration. then the default values readout is X (Undefined). Bit Bash test should not.." hexmask.long.byte 0x0 24.--31. 1. "RESERVED_31_24,Reserved" newline hexmask.long.byte 0x0 16.--23. 1. "LOGIC_ANALYZER_TRACE,logic_analyzer_trace Port MUX Select Currently only bits[21:16] are used. For details on how the mux controls the debug traces refer to the 'assign logic_analyzer_trace =' code section in the DWC_usb3.v file. A value of 6'h3F drives.." newline rbitfld.long 0x0 14.--15. "RESERVED_15_14,Reserved" "0,1,2,3" newline hexmask.long.word 0x0 0.--13. 1. "HOSTSELECT,Device LSP Select Selects the LSP debug information presented in the GDBGLSP register in host mode." rgroup.long (0x74+0x49408)++0x3 line.long 0x0 "GDBGLSP,Global Debug LSP Register This register is for internal debug purposes only. This register is for internal use only. If DWC_USB3_PRESERVE_LOGIC_ANALYZER_SELECT is enabled during controller configuration. then the default values readout is X.." hexmask.long 0x0 0.--31. 1. "LSPDEBUG,LSP Debug Information" repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) rgroup.long ($2+0x78+0x49408)++0x3 line.long 0x0 "GDBGEPINFO$1,Global Debug Endpoint Information Register 0 This register is for internal use only. If DWC_USB3_PRESERVE_LOGIC_ANALYZER_SELECT is enabled during controller configuration. then the default values readout is X (Undefined). Bit Bash test.." hexmask.long 0x0 0.--31. 1. "EPDEBUG,Endpoint Debug Information bits[31:0]" repeat.end group.long (0x80+0x49408)++0xF line.long 0x0 "GPRTBIMAP_HSLO,Global High-Speed Port to Bus Instance Mapping Register - Low This is an alternate register for the GPRTBIMAP_HS register. - Register fields are read-write with respect to number of port instantiated. writeAsRead constraint is added to.." hexmask.long.byte 0x0 28.--31. 1. "BINUM8,BINUM8: HS USB Instance Number for Port 8. Application-programmable ID field." newline hexmask.long.byte 0x0 24.--27. 1. "BINUM7,BINUM7: HS USB Instance Number for Port 7. Application-programmable ID field." newline hexmask.long.byte 0x0 20.--23. 1. "BINUM6,BINUM6 USB Instance Number for Port 6. Application-programmable ID field." newline hexmask.long.byte 0x0 16.--19. 1. "BINUM5,BINUM5: HS USB Instance Number for Port 5. Application-programmable ID field." newline hexmask.long.byte 0x0 12.--15. 1. "BINUM4,BINUM4: HS USB Instance Number for Port 4. Application-programmable ID field." newline hexmask.long.byte 0x0 8.--11. 1. "BINUM3,BINUM3: HS USB Instance Number for Port 3. Application-programmable ID field." newline hexmask.long.byte 0x0 4.--7. 1. "BINUM2,BINUM2: HS USB Instance Number for Port 2. Application-programmable ID field." newline hexmask.long.byte 0x0 0.--3. 1. "BINUM1,BINUM1: HS USB Instance Number for Port 1. Application-programmable ID field." line.long 0x4 "GPRTBIMAP_HSHI,Global High-Speed Port to Bus Instance Mapping Register - High This is an alternate register for the GPRTBIMAP_HS register. - Register fields are read-write with respect to number of port instantiated. writeAsRead constraint is added to.." hexmask.long.byte 0x4 28.--31. 1. "RESERVED_31_28,Reserved" newline hexmask.long.byte 0x4 24.--27. 1. "BINUM15,BINUM15: HS USB Instance Number for Port 15. Application-programmable ID field." newline hexmask.long.byte 0x4 20.--23. 1. "BINUM14,BINUM14: HS USB Instance Number for Port 14. Application-programmable ID field." newline hexmask.long.byte 0x4 16.--19. 1. "BINUM13,BINUM13: HS USB Instance Number for Port 13. Application-programmable ID field." newline hexmask.long.byte 0x4 12.--15. 1. "BINUM12,BINUM12: HS USB Instance Number for Port 12. SApplication-programmable ID field." newline hexmask.long.byte 0x4 8.--11. 1. "BINUM11,BINUM11: HS USB Instance Number for 11. Application-programmable ID field." newline hexmask.long.byte 0x4 4.--7. 1. "BINUM10,BINUM10: HS USB Instance Number for Port 10. Application-programmable ID field." newline hexmask.long.byte 0x4 0.--3. 1. "BINUM9,BINUM9: HS USB Instance Number for Port 9. Application-programmable ID field." line.long 0x8 "GPRTBIMAP_FSLO,Global Full-Speed Port to Bus Instance Mapping Register - Low This is an alternate register for the GPRTBIMAP_FS register. - Register fields are read-write with respect to number of port instantiated. writeAsRead constraint is added to.." hexmask.long.byte 0x8 28.--31. 1. "BINUM8,BINUM8: FS USB Instance Number for Port 8. Application-programmable ID field." newline hexmask.long.byte 0x8 24.--27. 1. "BINUM7,BINUM7: FS USB Instance Number for Port 7. Application-programmable ID field." newline hexmask.long.byte 0x8 20.--23. 1. "BINUM6,BINUM6: FS USB Instance Number for Port 6. Application-programmable ID field." newline hexmask.long.byte 0x8 16.--19. 1. "BINUM5,BINUM5: FS USB Instance Number for Port 5. Application-programmable ID field." newline hexmask.long.byte 0x8 12.--15. 1. "BINUM4,BINUM4: FS USB Instance Number for Port 4. Application-programmable ID field." newline hexmask.long.byte 0x8 8.--11. 1. "BINUM3,BINUM3: FS USB Instance Number for Port 3. Application-programmable ID field." newline hexmask.long.byte 0x8 4.--7. 1. "BINUM2,BINUM2: FS USB Instance Number for Port 2. Application-programmable ID field." newline hexmask.long.byte 0x8 0.--3. 1. "BINUM1,BINUM1: FS USB Instance Number for Port 1. Application-programmable ID field." line.long 0xC "GPRTBIMAP_FSHI,Global Full-Speed Port to Bus Instance Mapping Register - High This is an alternate register for the GPRTBIMAP_FS register. - Register fields are read-write with respect to number of port instantiated. writeAsRead constraint is added to.." hexmask.long.byte 0xC 28.--31. 1. "RESERVED_31_28,Reserved" newline hexmask.long.byte 0xC 24.--27. 1. "BINUM15,BINUM15: FS USB Instance Number for Port 15. Application-programmable ID field" newline hexmask.long.byte 0xC 20.--23. 1. "BINUM14,BINUM14: FS USB Instance Number for Port 14. Application-programmable ID field" newline hexmask.long.byte 0xC 16.--19. 1. "BINUM13,BINUM13: FS USB Instance Number for Port 13. Application-programmable ID field" newline hexmask.long.byte 0xC 12.--15. 1. "BINUM12,BINUM12: FS USB Instance Number for Port 12. Application-programmable ID field" newline hexmask.long.byte 0xC 8.--11. 1. "BINUM11,BINUM11: FS USB Instance Number for Port 11. Application-programmable ID field" newline hexmask.long.byte 0xC 4.--7. 1. "BINUM10,BINUM10: FS USB Instance Number for Port 10. Application-programmable ID field" newline hexmask.long.byte 0xC 0.--3. 1. "BINUM9,BINUM9: FS USB Instance Number for Port 9. Application-programmable ID field." repeat 2. (list 0x5E 0x62 )(list 0x0 0x4 ) rgroup.long ($2+0x94+0x49408)++0x3 line.long 0x0 "RESERVED_$1,Future Reserved Register at offset 0x94" hexmask.long 0x0 0.--31. 1. "RESERVED_31_0,Future use Register field" repeat.end group.long (0x9C+0x49408)++0x3 line.long 0x0 "GUCTL2,Global User Control Register 2: This register provides a few options for the software to control the controller behavior in the Host and device mode. Most of the options are used to improve inter-operability with different hosts and devices." hexmask.long.byte 0x0 26.--31. 1. "RESERVED_31_26,Reserved" newline hexmask.long.byte 0x0 19.--25. 1. "EN_HP_PM_TIMER,This register field is used to set new HP and PM timers. - To enable PM timer set GUCTL2[19] bit as 1. - To enable HP timer set GUCTL2[20] bit as 1. Default value of HP timer is 4us when HP PM timer is not enabled; when new HP timer is.." newline hexmask.long.byte 0x0 15.--18. 1. "NOLOWPWRDUR,No Low Power Duration (NOLOWPWRDUR) This bit is applicable for device mode only and is ignored in host mode. After starting a transfer on a SS ISOC endpoint the application must program these bits to prevent the device to lose frame.." newline bitfld.long 0x0 14. "RST_ACTBITLATER,Enable clearing of the command active bit for the ENDXFER command after the command execution is completed. This bit is valid in device mode only." "0,1" newline rbitfld.long 0x0 13. "RESERVED_13,Reserved for future use" "0,1" newline bitfld.long 0x0 12. "ENABLEEPCACHEEVICT,Enable Evicting Endpoint cache after Flow Control for bulk endpoints. In 3.00a release a performance enhancement was done to keep the non-stream capable bulk IN endpoint in cache after flow control. Setting this bit will disable this.." "0,1" newline bitfld.long 0x0 11. "DISABLECFC,Disable xHCI Errata Feature Contiguous Frame ID Capability This field controls the xHCI Errata feature Contiguous FrameID capability. When set the xHCI HCCPARAMS1 bit 11 will be set to 0 indicating that CFC is not supported. Disable this.." "0,1" newline hexmask.long.byte 0x0 5.--10. 1. "RXPINGDURATION,Recieve Ping Maximum Duration This field is relevant to Host mode and controls the maximum duration of received LFPS to be treated as a Ping LFPS. The Max duration of the Ping LFPS is controlled by programming this value and is in terms of.." newline hexmask.long.byte 0x0 0.--4. 1. "TXPINGDURATION,Transmit Ping Maximum Duration This field is relevant to Device mode and controls the maximum duration for which the controller should instruct the PHY to transmit a Ping LFPS. The duration of the Ping LFPS is controlled by programming.." group.long (0x100+0x49408)++0x3 line.long 0x0 "GUSB2PHYCFG,Global USB2 PHY Configuration Register The application must program this register before starting any transactions on either the SoC bus or the USB. In Device-only configurations. only one register is needed. In Host mode. per-port registers.." bitfld.long 0x0 31. "PHYSOFTRST,UTMI PHY Soft Reset (PHYSoftRst) Causes the usb2phy_reset signal to be asserted to reset a UTMI PHY. Not applicable to ULPI because ULPI PHYs are reset via their FunctionControl.Reset register and the controller automatically writes to this.." "0,1" newline bitfld.long 0x0 30. "U2_FREECLK_EXISTS,U2_FREECLK_EXISTS Specifies whether your USB 2.0 PHY provides a free-running PHY clock which is active when the clock control input is active. If your USB 2.0 PHY provides a free-running PHY clock it must be connected to the.." "USB 2,USB 2" newline bitfld.long 0x0 29. "ULPI_LPM_WITH_OPMODE_CHK,ULPI_LPM_WITH_OPMODE_CHK Support the LPM over ULPI without NOPID token to the ULPI PHY. If this bit is set the ULPI PHY is expected to qualify the EXT PID with OPMODE=2'b00 for LPM and not treat it as a NOPID. Check with your.." "A NOPID is sent before sending an EXTPID for LPM;,An EXTPID is sent without previously sending a.." newline rbitfld.long 0x0 27.--28. "HSIC_CON_WIDTH_ADJ,HSIC_CON_WIDTH_ADJ This bit is used in the HSIC device mode of operation. By default the connect duration for the HSIC device controller is thrice the strobe period. You can change this duration to 4 5 or 6 times the strobe period.." "0,1,2,3" newline rbitfld.long 0x0 26. "INV_SEL_HSIC,INV_SEL_HSIC The application driver uses this bit to control the HSIC enable/disable function. When set to '1' this bit overrides and functionally inverts the 'if_select_hsic' input signal. If {INV_SEL_HSIC if_select_hsic} is: - 00: HSIC.." "HSIC Capability is disabled,HSIC Capability is enabled" newline bitfld.long 0x0 25. "OVRD_FSLS_DISC_TIME,Overriding the FS/LS disconnect time to 32us. - If this value is 0 the FS/LS disconnect time is set to 2.5us as per the USB specification. - If this value is non-0 the disconnect detection time is set to 32us. Normally this value.." "0,1" newline bitfld.long 0x0 22.--24. "LSTRD,LS Turnaround Time (LSTRDTIM) This field indicates the value of the Rx-to-Tx packet gap for LS devices. The encoding is as follows: - 0: 2 bit times - 1: 2.5 bit times - 2: 3 bit times - 3: 3.5 bit times - 4: 4 bit times - 5: 4.5 bit times - 6: 5.." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 19.--21. "LSIPD,LS Inter-Packet Time (LSIPD) This field indicates the value of Tx-to-Tx packet gap for LS devices. The encoding is as follows: - 0: 2 bit times - 1: 2.5 bit times - 2: 3 bit times - 3: 3.5 bit times - 4: 4 bit times - 5: 4.5 bit times - 6: 5 bit.." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 18. "ULPIEXTVBUSINDIACTOR,ULPI External VBUS Indicator (ULPIExtVbusIndicator) Indicates the ULPI PHY VBUS over-current indicator. - 1'b0: PHY uses an internal VBUS valid comparator. - 1'b1: PHY uses an external VBUS valid comparator. Valid only when RTL.." "PHY uses an internal VBUS valid comparator,PHY uses an external VBUS valid comparator" newline bitfld.long 0x0 17. "ULPIEXTVBUSDRV,ULPI External VBUS Drive (ULPIExtVbusDrv) Selects supply source to drive 5V on VBUS in the ULPI PHY. - 1'b0: PHY drives VBUS with internal charge pump (default). - 1'b1: PHY drives VBUS with an external supply. (Only when RTL parameter.." "PHY drives VBUS with internal charge pump,PHY drives VBUS with an external supply" newline rbitfld.long 0x0 16. "RESERVED_16,Reserved" "0,1" newline bitfld.long 0x0 15. "ULPIAUTORES,ULPI Auto Resume (ULPIAutoRes) Sets the AutoResume bit in Interface Control register on the ULPI PHY. - 1'b0: PHY does not use the AutoResume feature. - 1'b1: PHY uses the AutoResume feature. Valid only when RTL parameter.." "PHY does not use the AutoResume feature,PHY uses the AutoResume feature" newline rbitfld.long 0x0 14. "RESERVED_14,Reserved" "0,1" newline hexmask.long.byte 0x0 10.--13. 1. "USBTRDTIM,USB 2.0 Turnaround Time (USBTrdTim) Sets the turnaround time in PHY clocks. Specifies the response time for a MAC request to the Packet FIFO Controller (PFC) to fetch data from the DFIFO (SPRAM). The following are the required values for the.." newline bitfld.long 0x0 9. "XCVRDLY,Transceiver Delay: Enables a delay between the assertion of the UTMI/ULPI Transceiver Select signal (for HS) and the assertion of the TxValid signal during a HS Chirp. When this bit is set to 1 a delay (of approximately 2.5 us) is introduced.." "0,1" newline bitfld.long 0x0 8. "ENBLSLPM,Enable utmi_sleep_n and utmi_l1_suspend_n (EnblSlpM) The application uses this bit to control utmi_sleep_n and utmi_l1_suspend_n assertion to the PHY in the L1 state. - 1'b0: utmi_sleep_n and utmi_l1_suspend_n assertion from the controller is.." "utmi_sleep_n and utmi_l1_suspend_n assertion..,utmi_sleep_n and utmi_l1_suspend_n assertion.." newline bitfld.long 0x0 7. "PHYSEL,USB 2.0 High-Speed PHY or USB 1.1 Full-Speed Serial Transceiver Select The application uses this bit to select a high-speed PHY or a full-speed transceiver. - 1'b0: USB 2.0 high-speed UTMI+ or ULPI PHY. This bit is always 0 with Write Only.." "USB 2,USB 1" newline bitfld.long 0x0 6. "SUSPENDUSB20,Suspend USB2.0 HS/FS/LS PHY (SusPHY) When set USB2.0 PHY enters Suspend mode if Suspend conditions are valid. For DRD configurations it is recommended that this bit is set to 0 during coreConsultant configuration. If it is set to 1 then.." "0,1" newline rbitfld.long 0x0 5. "FSINTF,Full-Speed Serial Interface Select (FSIntf) The application uses this bit to select a unidirectional or bidirectional USB 1.1 full-speed serial transceiver interface. - 1'b0: 6-pin unidirectional full-speed serial interface. This bit is set to 0.." "0,1" newline rbitfld.long 0x0 4. "ULPI_UTMI_SEL,ULPI or UTMI+ Select (ULPI_UTMI_Sel) The application uses this bit to select a UTMI+ or ULPI Interface. - 1'b0: UTMI+ Interface - 1'b1: ULPI Interface This bit is writable only if UTMI+ and ULPI is specified for High-Speed PHY Interface(s).." "UTMI+ Interface,ULPI Interface" newline bitfld.long 0x0 3. "PHYIF,PHY Interface (PHYIf) If UTMI+ is selected the application uses this bit to configure the controller to support a UTMI+ PHY with an 8- or 16-bit interface. - 1'b0: 8 bits - 1'b1: 16 bits ULPI Mode: 1'b0 Note: - All the enabled 2.0 ports must have.." "0,1" newline bitfld.long 0x0 0.--2. "TOUTCAL,HS/FS Timeout Calibration (TOutCal) The number of PHY clocks as indicated by the application in this field is multiplied by a bit-time factor; this factor is added to the high-speed/full-speed interpacket timeout duration in the controller to.." "0,1,2,3,4,5,6,7" rgroup.long (0x140+0x49408)++0x3 line.long 0x0 "GUSB2I2CCTL,Reserved Register" hexmask.long 0x0 0.--31. 1. "RESERVED_31_0,Reserved for future use" group.long (0x180+0x49408)++0x3 line.long 0x0 "GUSB2PHYACC_ULPI,Global USB 2.0 ULPI PHY Vendor Control Register The application uses this register to access the PHY registers. This register is always implemented when the ULPI PHY Interface is enabled during coreConsultant configuration (parameter.." hexmask.long.byte 0x0 27.--31. 1. "RESERVED_31_27,Reserved" newline rbitfld.long 0x0 26. "DISUIPIDRVR,DISUIPIDRVR" "0,1" newline bitfld.long 0x0 25. "NEWREGREQ,New Register Request The application sets this bit for a new vendor control access. Setting this bit to 1 asserts the utmi_vcontrolload_n (1'b0) on the UTMI interface." "0,1" newline rbitfld.long 0x0 24. "VSTSDONE,VSTSDONE" "0,1" newline bitfld.long 0x0 23. "VSTSBSY,VSTSBSY" "0,1" newline bitfld.long 0x0 22. "REGWR,Register Write The application sets this bit for register writes and clears it for register reads. Note: This bit is applicable for ULPI register read/write access only." "0,1" newline hexmask.long.byte 0x0 16.--21. 1. "REGADDR,Register Address The 6-bit PHY register address for immediate PHY Register Set access. Set to 6'h2F for Extended PHY Register Set access. Note: These bits are applicable for ULPI only." newline hexmask.long.byte 0x0 8.--15. 1. "EXTREGADDR,EXTREGADDR" newline hexmask.long.byte 0x0 0.--7. 1. "REGDATA,REGDATA" group.long (0x1C0+0x49408)++0x3 line.long 0x0 "GUSB3PIPECTL,Global USB 3.0 PIPE Control Register The application uses this register to configure the USB3 PHY and PIPE interface. Device-only configuration requires only one register. In Host mode. registers are implemented for each port. For more.." bitfld.long 0x0 31. "PHYSOFTRST,USB3 PHY Soft Reset After setting this bit to '1' the software needs to clear this bit. For more information refer to Figure 'Software Resets and PHY Clock Sequencing and Requirements' in the Databook." "0,1" newline bitfld.long 0x0 30. "HSTPRTCMPL,HstPrtCmpl This feature tests the PIPE PHY compliance patterns without having to have a test fixture on the USB 3.0 cable. This bit enables placing the SS port link into a compliance state. By default this bit must be set to 1'b0. In.." "0,1" newline bitfld.long 0x0 29. "U2P3OK,P3 OK for SSInactive (SSIP3ok) - 0: During link state SS.Inactive put PHY in P2 (Default) - 1: During link state SS.Inactive put PHY in P3." "During link state SS,During link state SS" newline bitfld.long 0x0 28. "DISRXDETP3,Disabled receiver detection in P3 (DisRxDetP3) - 0: If PHY is in P3 and controller needs to perform receiver detection The controller performs receiver detection in P3. (Default) - 1: If PHY is in P3 and controller needs to perform receiver.." "If PHY is in P3 and controller needs to perform..,If PHY is in P3 and controller needs to perform.." newline bitfld.long 0x0 27. "UX_EXIT_IN_PX,Ux Exit in Px (Ux_exit_in_Px) - 0: The controller does U1/U2/U3 exit in PHY power state P0 (default behavior). - 1: The controller does U1/U2/U3 exit in PHY power state P1/P2/P3 respectively. Note: This bit is used by third-party SS PHY. It.." "The controller does U1/U2/U3 exit in PHY power..,The controller does U1/U2/U3 exit in PHY power.." newline bitfld.long 0x0 26. "PING_ENHANCEMENT_EN,Ping Enhancement Enable (ping_enhancement_en) When set the Downstream port U1 ping receive timeout becomes 500 ms instead of 300 ms. Minimum Ping.LFPS receive duration is 8 ns (one mac3_clk). This field is valid for the downstream.." "0,1" newline bitfld.long 0x0 25. "U1U2EXITFAIL_TO_RECOV,U1U2exitfail to Recovery (u1u2exitfail_to_recov) When set and U1/U2 LFPS handshake fails the LTSSM transitions from U1/U2 to Recovery instead of SS Inactive. If Recovery fails then the LTSSM can enter SS.Inactive. This is an.." "0,1" newline bitfld.long 0x0 24. "REQUEST_P1P2P3,Always Request P1/P2/P3 for U1/U2/U3 (request_p1p2p3) When set the controller always requests PHY power change from P0 to P1/P2/P3 during U0 to U1/U2/U3 transition. If this bit is 0 and immediate Ux exit (remotely initiated or locally.." "0,1" newline bitfld.long 0x0 23. "STARTRXDETU3RXDET,Start Receiver Detection in U3/Rx.Detect (StartRxdetU3RxDet) If DWC_USB3_GUSB3PIPECTL_INIT[22] is set and the link is in either U3 or Rx.Detect state the controller starts receiver detection on the rising edge of this bit. This can.." "0,1" newline bitfld.long 0x0 22. "DISRXDETU3RXDET,Disable Receiver Detection in U3/Rx.Det When set the controller does not handle receiver detection in either U3 or Rx.Detect states. DWC_USB3_GUSB3PIPECTL_INIT[23] must be used to start receiver detection manually. This bit can only be.." "0,1" newline bitfld.long 0x0 19.--21. "DELAYP1P2P3,Delay P1P2P3 Delay P0 to P1/P2/P3 request when entering U1/U2/U3 until (DWC_USB3_GUSB3PIPECTL_INIT[21:19]*8) 8B10B error occurs or Pipe3_RxValid drops to 0. DWC_USB3_GUSB3PIPECTL_INIT[18] must be 1 to enable this functionality." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 18. "DELAYP1TRANS,Delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. - 1'b1: When entering U1/U2/U3 delay the transition to P1/P2/P3 until the pipe3 signals Pipe3_RxElecIdle is 1 and pipe3_RxValid is 0 -.." "When entering U1/U2/U3,When entering U1/U2/U3" newline bitfld.long 0x0 17. "SUSPENDENABLE,Suspend USB3.0 SS PHY (Suspend_en) When set and if Suspend conditions are valid the USB 3.0 PHY enters Suspend mode. For DRD configurations it is recommended that this bit is set to '0' during coreConsultant configuration. If it is set.." "0,1" newline rbitfld.long 0x0 15.--16. "DATWIDTH,PIPE Data Width (DatWidth) - 2'b00: 32 bits - 2'b01: 16 bits One clock after reset these bits receive the value seen on the pipe3_DataBusWidth. The simulation testbench uses the coreConsultant parameter to configure the VIP. These bits in the.." "0,1,2,3" newline bitfld.long 0x0 14. "ABORTRXDETINU2,Abort Rx Detect in U2 (AbortRxDetInU2) When set and the link state is U2 the controller will abort receiver detection if it receives U2 exit LFPS from the remote link partner. This bit is for the downstream port only. Note: This bit is.." "0,1" newline bitfld.long 0x0 13. "SKIPRXDET,Skip Rx Detect: When set the controller skips Rx Detection if pipe3_RxElecIdle is low. Skip is defined as waiting for the appropriate timeout then repeating the operation." "0,1" newline bitfld.long 0x0 12. "LFPSP0ALGN,LFPS P0 Align: When set - The controller deasserts LFPS transmission on the clock edge that it requests Phy power state 0 when exiting U1 U2 or U3 low power states. Otherwise LFPS transmission is asserted one clock earlier. - The.." "0,1" newline bitfld.long 0x0 11. "P3P2TRANOK,P3 P2 Transitions OK (P3P2TranOK) When set the controller transitions directly from Phy power state P2 to P3 or from state P3 to P2. When not set P0 is always entered as an intermediate state during transitions between P2 and P3 as defined.." "0,1" newline bitfld.long 0x0 10. "P3EXSIGP2,P3 Exit Signal in P2 (P3ExSigP2) When this bit is set the controller always changes the PHY power state to P2 before attempting a U3 exit handshake. This bit is used only for some non-Synopsys PHYs that cannot do LFPS in P3. Note: This bit is.." "0,1" newline bitfld.long 0x0 9. "LFPSFILTER,LFPS Filter (LFPSFilt) When set filter LFPS reception with pipe3_RxValid in PHY power state P0 that is ignore LFPS reception from the PHY unless both pipe3_Rxelecidle and pipe3_RxValid are deasserted." "0,1" newline bitfld.long 0x0 8. "RX_DETECT_TO_POLLING_LFPS_CONTROL,RX_DETECT to Polling.LFPS Control - 1'b0 (Default): Enables a 400us delay to start Polling LFPS after RX_DETECT. This allows VCM offset to settle to a proper level. - 1'b1: Disables the 400us delay to start Polling LFPS.." "?,Disables the 400us delay to start Polling LFPS.." newline bitfld.long 0x0 7. "SSICEN,This field is not used." "0,1" newline bitfld.long 0x0 6. "TX_SWING,Tx Swing (TxSwing) Refer to the PIPE3 specification." "0,1" newline bitfld.long 0x0 3.--5. "TX_MARGIN,Tx Margin[2:0] (TxMargin) Refer to Table 5-3 of the PIPE3 Specification." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 1.--2. "SS_TX_DE_EMPHASIS,Tx Deemphasis (TxDeemphasis) The value driven to the PHY is controlled by the LTSSM during USB3 Compliance mode. (Refer to Table 5-3 of the PIPE3 specification.)" "0,1,2,3" newline bitfld.long 0x0 0. "ELASTIC_BUFFER_MODE,Elastic Buffer Mode (ElasticBufferMode) (Refer to Table 5-3 of the PIPE3 specification.)" "0,1" group.long (0x200+0x49408)++0x3 line.long 0x0 "GTXFIFOSIZ0,Global Transmit FIFO Size Register This register specifies the RAM start address and depth (both in MDWIDTH-bit words) for each implemented TxFIFO. The number of TxFIFOs depends on the configuration parameters including the number of Device.." hexmask.long.word 0x0 16.--31. 1. "TXFSTADDR_N,Transmit FIFOn RAM Start Address This field contains the memory start address for TxFIFOn in MDWIDTH-bit words." newline hexmask.long.word 0x0 0.--15. 1. "TXFDEP_N,TxFIFO Depth This field contains the depth of TxFIFOn in MDWIDTH-bit words. - Minimum value: 32 - Maximum value: 32 768 For more information see 'Integrating the Controller' chapter in the User Guide." repeat 6. (list 0x1 0x3 0x4 0x5 0x6 0x7 )(list 0x0 0x8 0xC 0x10 0x14 0x18 ) group.long ($2+0x204+0x49408)++0x3 line.long 0x0 "GTXFIFOSIZ$1,Register GTXFIFOSIZ 1" hexmask.long.word 0x0 16.--31. 1. "TXFSTADDR_N,Transmit FIFOn RAM Start Address This field contains the memory start address for TxFIFOn in MDWIDTH-bit words." newline hexmask.long.word 0x0 0.--15. 1. "TXFDEP_N,TXFDEP_N" repeat.end group.long (0x208+0x49408)++0x3 line.long 0x0 "GTXFIFOSIZ2,Transmit FIFOn RAM Start Address This field contains the memory start address for TxFIFOn in MDWIDTH-bit words." hexmask.long.word 0x0 16.--31. 1. "TXFSTADDR_N,Transmit FIFOn RAM Start Address This field contains the memory start address for TxFIFOn in MDWIDTH-bit words." newline hexmask.long.word 0x0 0.--15. 1. "TXFDEP_N,TxFIFO Depth This field contains the depth of TxFIFOn in MDWIDTH-bit words. - Minimum value: 32 - Maximum value: 32 768 For more information see 'Integrating the Controller' chapter in the User Guide." group.long (0x280+0x49408)++0x3 line.long 0x0 "GRXFIFOSIZ0,Global Receive FIFO Size Register This register specifies the RAM start address and depth (both in MDWIDTH-bit words) for each implemented RxFIFO. The number of RxFIFOs depends on the configuration parameters including the number of Host Bus.." hexmask.long.word 0x0 16.--31. 1. "RXFSTADDR_N,RxFIFOn RAM Start Address (RxFStAddr_n) This field contains the memory start address for RxFIFOn in MDWIDTH-bit words." newline hexmask.long.word 0x0 0.--15. 1. "RXFDEP_N,RxFIFO Depth (RxFDep_n) This field contains the depth of RxFIFOn in MDWIDTH-bit words. - Minimum value: 32 - Maximum value: 16 384" repeat 2. (list 0x1 0x2 )(list 0x0 0x4 ) group.long ($2+0x284+0x49408)++0x3 line.long 0x0 "GRXFIFOSIZ$1,Register" hexmask.long.word 0x0 16.--31. 1. "RXFSTADDR_N,RXFSTADDR_N" newline hexmask.long.word 0x0 0.--15. 1. "RXFDEP_N,RxFIFO Depth This field contains the depth of RxFIFOn in MDWIDTH-bit words. - Minimum value: 32 - Maximum value: 16 384" repeat.end group.long (0x300+0x49408)++0xF line.long 0x0 "GEVNTADRLO,Global Event Buffer Address (Low) Register This is an alternate register for the GEVNTADRn register." hexmask.long 0x0 0.--31. 1. "EVNTADRLO,Event Buffer Address (EvntAdrLo) Holds the lower 32 bits of start address of the external memory for the Event Buffer. During operation hardware does not update this address." line.long 0x4 "GEVNTADRHI,Global Event Buffer Address (High) Register This is an alternate register for the GEVNTADRn register." hexmask.long 0x4 0.--31. 1. "EVNTADRHI,Event Buffer Address (EvntAdrHi) Holds the higher 32 bits of start address of the external memory for the Event Buffer. During operation hardware does not update this address." line.long 0x8 "GEVNTSIZ,Global Event Buffer Size Register This register holds the Event Buffer Size and the Event Interrupt Mask bit. During power-on initialization. software must initialize the size with the number of bytes allocated for the Event Buffer. The Event.." bitfld.long 0x8 31. "EVNTINTRPTMASK,Event Interrupt Mask (EvntIntMask). When set to '1' this prevents the interrupt from being generated. However even when the mask is set the events are queued." "0,1" newline hexmask.long.word 0x8 16.--30. 1. "RESERVED_30_16,Reserved" newline hexmask.long.word 0x8 0.--15. 1. "EVENTSIZ,Event Buffer Size in bytes (EVNTSiz) Holds the size of the Event Buffer in bytes; must be a multiple of four. This is programmed by software once during initialization. The minimum size of the event buffer is 32 bytes." line.long 0xC "GEVNTCOUNT,Global Event Buffer Count Register This register holds the number of valid bytes in the Event Buffer. During initialization. software must initialize the count by writing 0 to the Event Count field. Each time the hardware writes a new event to.." bitfld.long 0xC 31. "EVNT_HANDLER_BUSY,Event Handler Busy Device software event handler busy indication. The controller sets this bit when the interrupt line is asserted due to pending events. Software clears this bit (with 1'b1) when it has finished processing the events.." "0,1" newline hexmask.long.word 0xC 16.--30. 1. "RESERVED_30_16,Reserved" newline hexmask.long.word 0xC 0.--15. 1. "EVNTCOUNT,Event Count (EVNTCount) When read returns the number of valid events in the Event Buffer (in bytes). When written hardware decrements the count by the value written. When Interrupt moderation is enabled (that is DEVICE_IMODI!= 0) the.." group.long (0x50C+0x49408)++0x7 line.long 0x0 "GUCTL3,Global User Control Register 3 This register provides a few options for the software to control the controller behavior in the Host mode. Most of the options are used to improve host inter-operability with different devices." hexmask.long.word 0x0 17.--31. 1. "RESERVED_31_17,Reserved" newline bitfld.long 0x0 16. "SCH_PING_EARLY,Enable SuperSpeed Ping Transaction Packet scheduling early in the microframe. This bit is valid in Host mode only." "0,1" newline hexmask.long.word 0x0 0.--15. 1. "RESERVED_15_0,Reserved" line.long 0x4 "GTXFIFOPRIDEV,Global Device TX FIFO DMA Priority Register This register specifies the relative DMA priority level among the Device TXFIFOs (one per IN endpoint). Each register bit[n] controls the priority (1: high. 0: low) of each TXFIFO[n]. When.." hexmask.long.tbyte 0x4 8.--31. 1. "RESERVED_31_N,Reserved" newline hexmask.long.byte 0x4 0.--7. 1. "GTXFIFOPRIDEV,Device TxFIFO priority" group.long (0x518+0x49408)++0xF line.long 0x0 "GTXFIFOPRIHST,Global Host TX FIFO DMA Priority Register This register specifies the relative DMA priority level among the Host TXFIFOs (one per USB bus instance) within the associated speed group (SS or HS/FSLS). Each register bit[n] controls the.." hexmask.long 0x0 4.--31. 1. "RESERVED_31_16,Reserved" newline hexmask.long.byte 0x0 0.--3. 1. "GTXFIFOPRIHST,Host TxFIFO priority" line.long 0x4 "GRXFIFOPRIHST,Global Host RX FIFO DMA Priority Register This register specifies the relative DMA priority level among the Host RXFIFOs (one per USB bus instance) within the associated speed group (SS or HS/FSLS). Each register bit[n] controls the.." hexmask.long 0x4 3.--31. 1. "RESERVED_31_16,Reserved" newline bitfld.long 0x4 0.--2. "GRXFIFOPRIHST,Host RxFIFO priority" "0,1,2,3,4,5,6,7" line.long 0x8 "GFIFOPRIDBC,Global Host Debug Capability DMA Priority Register This register specifies the relative priority of the RXFIFOs and TXFIFOs associated with the DbC mode. It overrides the priority assigned in the corresponding indexes of the Host RXFIFO and.." hexmask.long 0x8 2.--31. 1. "RESERVED_31_2,Reserved" newline bitfld.long 0x8 0.--1. "GFIFOPRIDBC,Host DbC DMA priority" "0,1,2,3" line.long 0xC "GDMAHLRATIO,Global Host FIFO DMA High-Low Priority Ratio Register This register specifies the relative priority of the SS FIFOs with respect to the HS/FSLS FIFOs. The DMA arbiter prioritizes the HS/FSLS round-robin arbiter group every DMA High-Low.." hexmask.long.tbyte 0xC 13.--31. 1. "RESERVED_31_13,Reserved" newline hexmask.long.byte 0xC 8.--12. 1. "HSTRXFIFO,Host RXFIFO DMA High-Low Priority" newline rbitfld.long 0xC 5.--7. "RESERVED_7_5,Reserved" "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0xC 0.--4. 1. "HSTTXFIFO,Host TXFIFO DMA High-Low Priority" group.long (0x530+0x49408)++0x3 line.long 0x0 "GFLADJ,Global Frame Length Adjustment Register This register provides options for the software to control the controller behavior with respect to SOF (Start of Frame) and ITP (Isochronous Timestamp Packet) timers and frame timer functionality. It.." bitfld.long 0x0 31. "GFLADJ_REFCLK_240MHZDECR_PLS1,GFLADJ_REFCLK_240MHZDECR_PLS1 This field indicates that the decrement value that the controller applies for each ref_clk must be GFLADJ_REFCLK_240MHZ_DECR and GFLADJ_REFCLK_240MHZ_DECR +1 alternatively on each ref_clk. Set.." "0,1" newline hexmask.long.byte 0x0 24.--30. 1. "GFLADJ_REFCLK_240MHZ_DECR,This field indicates the decrement value that the controller applies for each ref_clk in order to derive a frame timer in terms of a 240-MHz clock. This field must be programmed to a non-zero value only if GFLADJ_REFCLK_LPM_SEL.." newline bitfld.long 0x0 23. "GFLADJ_REFCLK_LPM_SEL,This bit enables the functionality of running SOF/ITP counters on the ref_clk. This bit must not be set to '1' if GCTL.SOFITPSYNC bit is set to '1'. Similarly if GFLADJ_REFCLK_LPM_SEL set to '1' GCTL.SOFITPSYNC must not be set to.." "0,1" newline rbitfld.long 0x0 22. "RESERVED_22,Reserved for future use" "0,1" newline hexmask.long.word 0x0 8.--21. 1. "GFLADJ_REFCLK_FLADJ,This field indicates the frame length adjustment to be applied when SOF/ITP counter is running on the ref_clk. This register value is used to adjust the ITP interval when GCTL[SOFITPSYNC] is set to '1'; SOF and ITP interval when.." newline bitfld.long 0x0 7. "GFLADJ_30MHZ_SDBND_SEL,GFLADJ_30MHZ_SDBND_SEL This field selects whether to use the input signal fladj_30mhz_reg or the GFLADJ.GFLADJ_30MHZ to adjust the frame length for the SOF/ITP. When this bit is set to - 1 the controller uses the register field.." "0,1" newline rbitfld.long 0x0 6. "RESERVED_6,Reserved for future use" "0,1" newline hexmask.long.byte 0x0 0.--5. 1. "GFLADJ_30MHZ,GFLADJ_30MHZ This field indicates the value that is used for frame length adjustment instead of considering from the sideband input signal fladj_30mhz_reg. This enables post-silicon frame length adjustment in case the input signal.." group.long (0x540+0x49408)++0x3 line.long 0x0 "GUSB2RHBCTL,Global USB 2.0 Root Hub Control Register The application must program this register before starting any transactions on the USB if a non-default value is desired. In Host mode. per-port registers are implemented." hexmask.long 0x0 4.--31. 1. "RESERVED_31_4,Reserved" newline hexmask.long.byte 0x0 0.--3. 1. "OVRD_L1TIMEOUT,Overriding the driver programmed L1TIMEOUT value. If this value is 0 the L1 Timeout value is taken from the xHCI PORTHLPMC register. If this value is non-0 then this will override the L1 Timeout value programmed in the xHCI PORTHLPMC.." tree.end tree "DWC_usb3_block_ecc (USB 3.0 ECC Register Block)" rgroup.long (0x850+0x53248)++0xB line.long 0x0 "BRSERRCNT,Block RAM Single Bit Error Count. 8 bit count for each of the 3 RAMs." hexmask.long.byte 0x0 24.--31. 1. "RESERVED_31_24,Reserved" hexmask.long.byte 0x0 16.--23. 1. "RAM2SERRCNT,RAM2 Single bit Error Count" hexmask.long.byte 0x0 8.--15. 1. "RAM1SERRCNT,RAM1 Single bit Error Count" hexmask.long.byte 0x0 0.--7. 1. "RAM0SERRCNT,RAM0 Single bit Error Count" line.long 0x4 "BRMERRCNT,Block RAM Multiple Bit Error Count. 8 bit count for each of the 3 RAMs." hexmask.long.byte 0x4 24.--31. 1. "RESERVED_31_24,Reserved" hexmask.long.byte 0x4 16.--23. 1. "RAM2MERRCNT,RAM2 Multiple bit Error Count" hexmask.long.byte 0x4 8.--15. 1. "RAM1MERRCNT,RAM1 Multiple bit Error Count" hexmask.long.byte 0x4 0.--7. 1. "RAM0MERRCNT,RAM0 Multiple bit Error Count" line.long 0x8 "BRMECCERR,Block RAM ECC Error Vector Register" hexmask.long.tbyte 0x8 8.--31. 1. "RESERVED_31_8,Reserved" bitfld.long 0x8 7. "RAMSERR,RAM Single bit Error Status" "0,1" bitfld.long 0x8 6. "RAMMERR,RAM Multiple bit Error Status" "0,1" bitfld.long 0x8 3.--5. "RAMSERRVEC,RAM Single Error Vector" "0,1,2,3,4,5,6,7" bitfld.long 0x8 0.--2. "RAMMERRVEC,RAM Multiple Error Vector" "0,1,2,3,4,5,6,7" group.long (0x85C+0x53248)++0x3 line.long 0x0 "BRERRCTL,Block RAM ECC Error Control Register" hexmask.long 0x0 4.--31. 1. "RESERVED_31_4,Reserved" bitfld.long 0x0 3. "ECCERRINJECT,This bit should be used for testing purposes only. - 1: Inject ECC error - 0: No ECC error injected" "No ECC error injected,Inject ECC error" bitfld.long 0x0 2. "ECCEN,ECC Enable (1) or Disable (0)" "0,1" bitfld.long 0x0 1. "RSERRCLR,RAM Single bit Error Clear" "0,1" bitfld.long 0x0 0. "RMERRCLR,RAM Multiple bit Error Clear" "0,1" rgroup.long (0x860+0x53248)++0xB line.long 0x0 "BRAM0ADDRERR,Block RAM Address of RAM0 having uncorrectable error" hexmask.long.word 0x0 16.--31. 1. "RESERVED_31_16,Reserved" hexmask.long.word 0x0 0.--15. 1. "RAM0ADDRLOC,RAM0 Address Location" line.long 0x4 "BRAM1ADDRERR,Block RAM Address of RAM1 having uncorrectable error" hexmask.long.word 0x4 16.--31. 1. "RESERVED_31_16,Reserved" hexmask.long.word 0x4 0.--15. 1. "RAM1ADDRLOC,RAM1 Address Location" line.long 0x8 "BRAM2ADDRERR,Block RAM Address of RAM2 having uncorrectable error" hexmask.long.word 0x8 16.--31. 1. "RESERVED_31_16,Reserved" hexmask.long.word 0x8 0.--15. 1. "RAM2ADDRLOC,RAM1 Address Location" tree.end tree "DWC_usb3_block_dev (USB 3.0 Device Register Block)" group.long (0x0+0x50944)++0x17 line.long 0x0 "DCFG,Device Configuration Register. This register configures the controller in Device mode after power-on or after certain control commands or enumeration. Do not make changes to this register after initial programming." hexmask.long.byte 0x0 25.--31. 1. "RESERVED_31_25,Reserved" rbitfld.long 0x0 24. "RESERVED_24,reserved" "0,1" newline bitfld.long 0x0 23. "IGNSTRMPP,IgnoreStreamPP This bit only affects stream-capable bulk endpoints. When this bit is set to '0' and the controller receives a Data Packet with the Packet Pending (PP) bit set to 0 for OUT endpoints or it receives an ACK with the NumP field set.." "0,1" bitfld.long 0x0 22. "LPMCAP,LPM Capable The application uses this bit to control the LPM capabilities of the DWC_usb3 controller. If the controller operates as a non-LPM-capable device it cannot respond to LPM transactions. - 1'b0: LPM capability is not enabled. - 1'b1: LPM.." "LPM capability is not enabled,LPM capability is enabled" newline hexmask.long.byte 0x0 17.--21. 1. "NUMP,Number of Receive Buffers. This bit indicates the number of receive buffers to be reported in the ACK TP. The DWC_usb3 controller uses this field for non-control endpoints if GRXTHRCFG.UsbRxPktCntSel is set to '0'. The application can program this.." hexmask.long.byte 0x0 12.--16. 1. "INTRNUM,Interrupt number Indicates interrupt/EventQ number on which non-endpoint-specific device-related interrupts (see DEVT) are generated." newline rbitfld.long 0x0 10.--11. "RESERVED_10_11,Reserved" "0,1,2,3" hexmask.long.byte 0x0 3.--9. 1. "DEVADDR,Device Address. The application must perform the following: - Program this field after every SetAddress request. - Reset this field to zero after USB reset." newline bitfld.long 0x0 0.--2. "DEVSPD,Device Speed. Indicates the speed at which the application requires the controller to connect or the maximum speed the application can support. However the actual bus speed is determined only after the chirp sequence is completed and is based.." "High-speed,Full-speed,?,?,SuperSpeed,?,?,?" line.long 0x4 "DCTL,Device Control Register Note: When Hibernation is not enabled using GCTL.GblHibernationEn field. - you can write any value to CSS. CRS. L1HibernationEn. and KeepConnect fields - L1HibernationEn. and KeepConnect fields always return 0 when read in.." bitfld.long 0x4 31. "RUN_STOP,Run/Stop The software writes 1 to this bit to start the device controller operation. To stop the device controller operation the software must remove any active transfers and write 0 to this bit. When the controller is stopped it sets the.." "0,1" bitfld.long 0x4 30. "CSFTRST,Core Soft Reset Resets the all clock domains as follows: - This bit clears the interrupts and all the CSRs except GSTS GSNPSID GGPIO GUID GUSB2PHYCFGn registers GUSB3PIPECTLn registers DCFG DCTL DEVTEN and DSTS registers. - All module.." "0,1" newline rbitfld.long 0x4 29. "RESERVED_29,Reserved1" "0,1" hexmask.long.byte 0x4 24.--28. 1. "HIRDTHRES,HIRD Threshold (HIRD_Thres) The controller asserts output signals utmi_l1_suspend_n and utmi_sleep_n (see 'LPM Interface Signals' table in the Databook) on the basis of this signal: The controller asserts utmi_l1_suspend_n to put the PHY into.." newline hexmask.long.byte 0x4 20.--23. 1. "LPM_NYET_THRES,LPM NYET Threshold When LPM Errata is enabled: Bits [23:20]: LPM NYET Response Threshold (LPM_NYET_thres) Handshake response to LPM token specified by device application. Response depends on DCFG.LPMCap. - DCFG.LPMCap is 1'b0 - The.." bitfld.long 0x4 19. "KEEPCONNECT,Keep Connect When '1' this bit enables the save and restore programming model by preventing the controller from disconnecting from the host when DCTL.RunStop is set to '0'. It also enables the Hibernation Request Event to be generated when.." "0,1" newline bitfld.long 0x4 18. "L1HIBERNATIONEN,L1HibernationEn When this bit is set along with KeepConnect the device controller generates a Hibernation Request Event if L1 is enabled and the HIRD value in the LPM token is larger than the threshold programmed in DCTL.HIRD_Thres. The.." "0,1" bitfld.long 0x4 17. "CRS,Controller Restore State (CRS) This command is similar to the USBCMD.CRS bit in host mode and initiates the restore process. When software sets this bit to '1' the controller immediately sets DSTS.RSS to '1'. When the controller has finished the.." "0,1" newline bitfld.long 0x4 16. "CSS,Controller Save State (CSS) This command is similar to the USBCMD.CSS bit in host mode and initiates the save process. When software sets this bit to '1' the controller immediately sets DSTS.SSS to '1'. When the controller has finished the save.." "0,1" rbitfld.long 0x4 13.--15. "RESERVED_15_13,Reserved" "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 12. "INITU2ENA,Initiate U2 Enable - 1'b0: May not initiate U2 (default) - 1'b1: May initiate U2 On USB reset hardware clears this bit to 0. Software sets this bit after receiving SetFeature(U2_ENABLE) and clears this bit when ClearFeature(U2_ENABLE) is.." "May not initiate U2,May initiate U2" bitfld.long 0x4 11. "ACCEPTU2ENA,Accept U2 Enable - 1'b0: Reject U2 except when Force_LinkPM_Accept bit is set (default) - 1'b1: Controller accepts transition to U2 state if nothing is pending on the application side. On USB reset hardware clears this bit to 0. Software.." "Reject U2 except when Force_LinkPM_Accept bit is..,Controller accepts transition to U2 state if.." newline bitfld.long 0x4 10. "INITU1ENA,Initiate U1 Enable - 1'b0: May not initiate U1 (default); - 1'b1: May initiate U1. On USB reset hardware clears this bit to 0. Software sets this bit after receiving SetFeature(U1_ENABLE) and clears this bit when ClearFeature(U1_ENABLE) is.." "May not initiate U1,May initiate U1" bitfld.long 0x4 9. "ACCEPTU1ENA,Accept U1 Enable - 1'b0: Controller rejects U1 except when Force_LinkPM_Accept bit is set (default) - 1'b1: Controller accepts transition to U1 state if nothing is pending on the application side. On USB reset hardware clears this bit to 0." "Controller rejects U1 except when..,Controller accepts transition to U1 state if.." newline hexmask.long.byte 0x4 5.--8. 1. "ULSTCHNGREQ,ULSTCHNGREQ Software writes this field to issue a USB/Link state change request. A change in this field indicates a new request to the controller. If software wants to issue the same request back-to-back it must write a 0 to this field.." hexmask.long.byte 0x4 1.--4. 1. "TSTCTL,Test Control - 4'b000: Test mode disabled - 4'b001: Test_J mode - 4'b010: Test_K mode - 4'b011: Test_SE0_NAK mode - 4'b100: Test_Packet mode - 4'b101: Test_Force_Enable - Others: Reserved" newline rbitfld.long 0x4 0. "RESERVED_0,Reserved" "0,1" line.long 0x8 "DEVTEN,Device Event Enable Register This register controls the generation of device-specific events (see 'Event Buffer Content for Device-Specific Events (DEVT)' section). If an enable bit is set to 0. the event will not be generated." hexmask.long.word 0x8 17.--31. 1. "RESERVED_31_17,Reserved" bitfld.long 0x8 16. "ECCERREN,ECC Error Enable. If this bit is set to 1 the controller reports an ECC error to the software when an uncorrectable ECC occurs internally." "0,1" newline rbitfld.long 0x8 15. "RESERVED_15,Reserved" "0,1" bitfld.long 0x8 14. "L1WKUPEVTEN,L1 Resume Detected Event Enable. Note: If GUCTL1[DEV_DECOUPLE_L1L2_EVT] is enabled then this bit is for L1 Resume Detected Event Enable." "0,1" newline bitfld.long 0x8 12. "VENDEVTSTRCVDEN,Vendor Device Test LMP Received Event (VndrDevTstRcvedEn)" "0,1" rbitfld.long 0x8 11. "RESERVED_11,Reserved" "0,1" newline rbitfld.long 0x8 10. "RESERVED_10,Reserved" "0,1" bitfld.long 0x8 9. "ERRTICERREVTEN,Erratic Error Event Enable" "0,1" newline bitfld.long 0x8 8. "L1SUSPEN,L1 Suspend Event Enable Note: Only if GUCTL1[DEV_DECOUPLE_L1L2_EVT] is enabled this bit is for L1 Suspend Event Enable." "0,1" bitfld.long 0x8 7. "SOFTEVTEN,Start of (u)frame" "0,1" newline bitfld.long 0x8 6. "U3L2L1SUSPEN,U3/L2 or U3/L2L1 Suspend Event Enable. Note: - If GUCTL1[DEV_DECOUPLE_L1L2_EVT] is enabled then this bit is for U3/L2 Suspend Event Enable. - If GUCTL1[DEV_DECOUPLE_L1L2_EVT] is not enabled then this bit is for U3/L2L1 Suspend Event Enable." "0,1" bitfld.long 0x8 5. "HIBERNATIONREQEVTEN,This bit enables/disables the generation of the Hibernation Request Event." "0,1" newline bitfld.long 0x8 4. "WKUPEVTEN,U3/L2 or U3/L2L1 Resume Detected Event Enable. Note: - If GUCTL1[DEV_DECOUPLE_L1L2_EVT] is enabled then this bit is for U3/L2 Resume Detected Event Enable. - If GUCTL1[DEV_DECOUPLE_L1L2_EVT] is not enabled then this bit is for U3/L2L1 Resume.." "0,1" bitfld.long 0x8 3. "ULSTCNGEN,USB/Link State Change Event Enable" "0,1" newline bitfld.long 0x8 2. "CONNECTDONEEVTEN,Connection Done Enable" "0,1" bitfld.long 0x8 1. "USBRSTEVTEN,USB Reset Enable" "0,1" newline bitfld.long 0x8 0. "DISSCONNEVTEN,Disconnect Detected Event Enable" "0,1" line.long 0xC "DSTS,Device Status Register This register indicates the status of the device controller with respect to USB-related events. Note: When Hibernation is not enabled. RSS and SSS fields always return 0 when read." rbitfld.long 0xC 30.--31. "RESERVED_31_30,Reserved" "0,1,2,3" rbitfld.long 0xC 29. "DCNRD,Device Controller Not Ready The bit indicates that the controller is in the process of completing the state transitions after exiting from hibernation. To complete the state transitions it takes 256 bus clock cycles from the time DCTL[31].Run/Stop.." "0,1" newline bitfld.long 0xC 28. "SRE,Save Restore Error. Currently not supported." "0,1" rbitfld.long 0xC 26.--27. "RESERVED_27_26,Reserved" "0,1,2,3" newline rbitfld.long 0xC 25. "RSS,RSS Restore State Status This bit is similar to the USBSTS.RSS in host mode. When the controller finishes the restore process it completes the command by setting DSTS.RSS to '0'." "0,1" rbitfld.long 0xC 24. "SSS,SSS Save State Status This bit is similar to the USBSTS.SSS in host mode. When the controller has finished the save process it completes the command by setting DSTS.SSS to '0'." "0,1" newline rbitfld.long 0xC 23. "COREIDLE,Core Idle The bit indicates that the controller finished transferring all RxFIFO data to system memory writing out all completed descriptors and all Event Counts are zero. Note: While testing for Reset values mask out the read value. This bit.." "0,1" rbitfld.long 0xC 22. "DEVCTRLHLT,Device Controller Halted This bit is set to 0 when the Run/Stop bit in the DCTL register is set to 1. The controller sets this bit to 1 when after SW sets Run/Stop to 0 the controller is idle and the lower layer finishes the disconnect.." "0,1" newline hexmask.long.byte 0xC 18.--21. 1. "USBLNKST,USBLNKST. USB/Link State In SS mode: LTSSM State - 4'h0: U0 - 4'h1: U1 - 4'h2: U2 - 4'h3: U3 - 4'h4: SS_DIS - 4'h5: RX_DET - 4'h6: SS_INACT - 4'h7: POLL - 4'h8: RECOV - 4'h9: HRESET - 4'ha: CMPLY - 4'hb: LPBK - 4'hf: Resume/Reset In HS/FS/LS.." rbitfld.long 0xC 17. "RXFIFOEMPTY,RxFIFO Empty." "0,1" newline hexmask.long.word 0xC 3.--16. 1. "SOFFN,Frame/Microframe Number of the Received SOF. When the controller is operating at SuperSpeed - [16:3] indicates the uframe/ITP number When the controller is operating at high-speed - [16:6] indicates the frame number - [5:3] indicates the.." rbitfld.long 0xC 0.--2. "CONNECTSPD,Connected Speed (ConnectSpd) Indicates the speed at which the DWC_usb3 controller has come up after speed detection through a chirp sequence. - 3'b100: SuperSpeed (PHY clock is running at 125 or 250 MHz) - 3'b000: High-speed (PHY clock is.." "High-speed,Full-speed,?,?,SuperSpeed,?,?,?" line.long 0x10 "DGCMDPAR,Device Generic Command Parameter Register This register indicates the device command parameter. This must be programmed before or along with the device command. The available device commands are listed in DGCMD register." hexmask.long 0x10 0.--31. 1. "PARAMETER,PARAMETER" line.long 0x14 "DGCMD,Device Generic Command Register This register enables software to program the controller using a single generic command interface to send link management packets and notifications. This register contains command. control. and status fields relevant.." hexmask.long.word 0x14 16.--31. 1. "RESERVED_31_16,Reserved" hexmask.long.byte 0x14 12.--15. 1. "CMDSTATUS,Command Status - 1: CmdErr: Indicates that the device controller encountered an error while processing the command. - 0: Indicates command success" newline rbitfld.long 0x14 11. "RESERVED_11,Reserved" "0,1" bitfld.long 0x14 10. "CMDACT,Command Active The software sets this bit to 1 to enable the device controller to execute the generic command. The device controller sets this bit to 0 after executing the command." "0,1" newline rbitfld.long 0x14 9. "RESERVED_9,Reserved" "0,1" bitfld.long 0x14 8. "CMDIOC,Command Interrupt on Complete When this bit is set the device controller issues a Generic Command Completion event after executing the command. Note that this interrupt is mapped to DCFG.IntrNum. Note: This field must not set to '1' if the.." "0,1" newline hexmask.long.byte 0x14 0.--7. 1. "CMDTYP,CMDTYP Generic Command Type Specifies the type of generic command the software driver is requesting the controller to perform. - 02h: Set Periodic Parameters - 04h: Set Scratchpad Buffer Array Address Lo - 05h: Set Scratchpad Buffer Array Address.." group.long (0x20+0x50944)++0x3 line.long 0x0 "DALEPENA,Device Active USB Endpoint Enable Register. This register indicates whether a USB endpoint is active in a given configuration or interface." hexmask.long 0x0 0.--31. 1. "USBACTEP,USBACTEP USB Active Endpoints (USBActEP) This field indicates if a USB endpoint is active in the current configuration and interface. It applies to USB IN endpoints 0.15 and OUT endpoints 0.15 with one bit for each of the 32 possible endpoints." rgroup.long (0x24+0x50944)++0x3 line.long 0x0 "RSVD,Reserved" hexmask.long 0x0 0.--31. 1. "RESERVED_31_0,Reserved" group.long (0x100+0x50944)++0xF line.long 0x0 "DEPCMDPAR2,Device Physical Endpoint-n Command Parameter 2 Register (DEPCMDPAR2n) This register indicates the physical endpoint command Parameter 2. It must be programmed before issuing the command." hexmask.long 0x0 0.--31. 1. "PARAMETER,PARAMETER" line.long 0x4 "DEPCMDPAR1,Device Physical Endpoint-n Command Parameter 1 Register (DEPCMDPAR1n)" hexmask.long 0x4 0.--31. 1. "PARAMETER,PARAMETER" line.long 0x8 "DEPCMDPAR0,Device Physical Endpoint-n Command Parameter 0 Register (DEPCMDPAR0n)" hexmask.long 0x8 0.--31. 1. "PARAMETER,PARAMETER" line.long 0xC "DEPCMD,Device Physical Endpoint-n Command Register This register enables software to issue physical endpoint-specific commands. This register contains command. control. and status fields relevant to the current generic command. while the DEPCMDPAR[2:0]n.." hexmask.long.word 0xC 16.--31. 1. "COMMANDPARAM,Command Parameters or Event Parameters Command Parameters (CommandParam) when this register is written: For Start Transfer command: - [31:16]: StreamID. The USB StreamID assigned to this transfer For Start Transfer command applied to an.." hexmask.long.byte 0xC 12.--15. 1. "CMDSTATUS,Command Completion Status (CmdStatus) Additional information about the completion of this command is available in this field. The information is in the same format as bits 15:12 of the Endpoint Command Complete event see 'Device Endpoint-n.." newline bitfld.long 0xC 11. "HIPRI_FORCERM,HighPriority/ForceRM (HiPri_ForceRM) - HighPriority: Only valid for Start Transfer command - ForceRM: Only valid for End Transfer command - ClearPendIN: Only valid for Clear Stall command . Software sets this bit to clear any pending IN.." "0,1" bitfld.long 0xC 10. "CMDACT,Command Active (CmdAct) Software sets this bit to 1 to enable the device endpoint controller to execute the generic command. The device controller sets this bit to 0 when the CmdStatus field is valid and the endpoint is ready to accept another.." "0,1" newline rbitfld.long 0xC 9. "RESERVED_9,Reserved" "0,1" bitfld.long 0xC 8. "CMDIOC,CMDIOC Command Interrupt on Complete (CmdIOC) When this bit is set the device controller issues a generic Endpoint Command Complete event after executing the command. Note that this interrupt is mapped to DEPCFG.IntrNum. When the DEPCFG command.." "0,1" newline hexmask.long.byte 0xC 4.--7. 1. "RESERVED_7_4,Reserved" hexmask.long.byte 0xC 0.--3. 1. "CMDTYP,Command Type Specifies the type of command the software driver is requesting the controller to perform. - 00h: Reserved - 01h: Set Endpoint Configuration - -64 or 96-bit Parameter - 02h: Set Endpoint Transfer Resource Configuration - 32-bit.." group.long (0x300+0x50944)++0x3 line.long 0x0 "DEV_IMOD,Device Interrupt Moderation Register (DEV_IMOD) This register controls the Interrupt Moderation feature that allows the device software to throttle the interrupt rate. Key Functions: - Interrupt Moderation is enabled only when the IMOD Interval.." hexmask.long.word 0x0 16.--31. 1. "DEVICE_IMODC,Interrupt Moderation Down Counter Loaded with the DEVICE_IMODI value whenever the hardware interrupt(n) line is de-asserted from the asserted state counts down to 0 and stops. The interrupt(n) is signaled whenever this counter is 0.." hexmask.long.word 0x0 0.--15. 1. "DEVICE_IMODI,Moderation Interval (DEVICE_IMODI) This field holds the minimum inter-interrupt interval between events. The interval is specified in terms of 250ns increments. A value of 0 disables the interrupt throttling logic and interrupts are.." tree.end tree "DWC_usb3_block_bc (USB 3.0 BC Register Block)" group.long (0x0+0x52272)++0x3 line.long 0x0 "BCFG,BC Configuration Register" hexmask.long 0x0 2.--31. 1. "RESERVED_31_2,Reserved" bitfld.long 0x0 1. "IDDIG_SEL,This field is not used." "0,1" bitfld.long 0x0 0. "CHIRP_EN,Chirp Enable When this bit is 1'b1 the controller asserts the bc_chirp_on output signal to indicate an imminent chirp." "0,1" group.long (0x8+0x52272)++0x7 line.long 0x0 "BCEVT,BC Event Register Writing 1 to the info bit in this register clears the register bit and the associated interrupt." hexmask.long.byte 0x0 25.--31. 1. "RESERVED_31_25,Reserved" bitfld.long 0x0 24. "MV_CHNGEVNT,Multi-Valued input changed Event: This event indicates that there is a change in the value of at least one ACA pin value. This bit is present only if DWC_USB3_EN_BC = 1 otherwise it is Reserved." "0,1" hexmask.long.tbyte 0x0 5.--23. 1. "RESERVED_23_5,Reserved" hexmask.long.byte 0x0 0.--4. 1. "MULTVALIDBC,Multi Valued ID pin Indicates the Battery Charger ACA inputs. - MultValIdBc[4]: bc_rid_float - MultValIdBc[3]: bc_rid_gnd - MultValIdBc[2]: bc_rid_a - MultValIdBc[1]: bc_rid_b - MultValIdBc[0]: bc_rid_c" line.long 0x4 "BCEVTEN,BC Event Enable Register" hexmask.long.byte 0x4 25.--31. 1. "RESERVED_31_25,Reserved" bitfld.long 0x4 24. "MV_CHNGEVNTENA,BCEvtInfoEna[0] Multi-Valued input changed Event Enable (MV_ChngEvntEn) When this bit is set MV_ChngEvnt in BCEVT register is enabled." "0,1" hexmask.long.tbyte 0x4 0.--23. 1. "RESERVED_23_0,Reserved" tree.end tree "DWC_usb3_block_link (USB 3.0 Link Register Block)" group.long (0x0+0x53248)++0x3 line.long 0x0 "LU1LFPSRXTIM,U1/U2 LFPS Rx Timer Register - Link Layer Register for U1/U2 LFPS RX Timers. - This register is common for all SS ports." hexmask.long.word 0x0 16.--31. 1. "RESERVED_16_31,Reserved" hexmask.long.byte 0x0 8.--15. 1. "U1U2_LFPS_EXIT_RX_CLK,Programmable U1U2 LFPS EXIT RX CLKS - Applicable to Remote Partner initiated Ux exit: Time to recognize valid Ux exit request from the remote partner. - This field is encoded as the pipe clk (8ns) count for the LFPS. -- 1: 8ns -- 2:.." hexmask.long.byte 0x0 0.--7. 1. "U1U2_EXIT_RSP_RX_CLK,Programmable U1U2 EXIT RESP RX CLKS - Applicable to locally initiated Ux exit: Minimum LFPS reception from remote to consider Ux exit handshake is successful. - This field is encoded as the pipe clk (8ns) count for the LFPS. -- 1:.." group.long (0x20+0x53248)++0xB line.long 0x0 "LINK_SETTINGS,Link Setting Register - Link Layer User Control Register for enabling Link/PHY-specific options. - This register is common for all SS ports." bitfld.long 0x0 31. "RESERVED_31,Reserved" "0,1" bitfld.long 0x0 28.--30. "U1_RESID_TIMER_US,Programmable U1 MIN RESIDENCY TIMER This field specifies U1 MIN RESIDENCY TIMER value in us. Set to 0 to disable the timer." "0,1,2,3,4,5,6,7" bitfld.long 0x0 27. "RESERVED_27,Reserved" "0,1" newline bitfld.long 0x0 24.--26. "PM_LC_TIMER_US,Programmable PM_LC_TIMER This field specifies PM_LC_TIMER value in us." "0,1,2,3,4,5,6,7" hexmask.long.byte 0x0 20.--23. 1. "PM_ENTRY_TIMER_US,Programmable PM_ENTRY_TIMER This field specifies PM_ENTRY_TIMER value in us." hexmask.long.tbyte 0x0 0.--19. 1. "RESERVED_0_19,Reserved" line.long 0x4 "LLUCTL,Link User Control Register - Link Layer User Control Register for enabling Link/PHY-specific options. - This register is common for all SS ports." bitfld.long 0x4 30.--31. "RESERVED_30_31,Reserved" "0,1,2,3" bitfld.long 0x4 29. "SUPPORT_P4_PG,PHY P4 Power gate mode (PG) is enabled. Set this bit if the PHY supports PG mode in P4. This bit is used only for Synopsys PHY." "0,1" bitfld.long 0x4 28. "SUPPORT_P4,Support PHY P3.CPM and P4 Power States. When this bit is set the controller puts the PHY in P3.CPM or P4 in certain states. This bit is used only for Synopsys PHY." "0,1" newline hexmask.long.byte 0x4 24.--27. 1. "RESERVED_24_27,Reserved" bitfld.long 0x4 23. "DISRXDET_LTSSM_TIMER_OVRRD,DisRxDet_LTSSM_Timer_Ovrrd. When DisRxDetU3RxDet is asserted in Polling or U1 the timeout expires immediately." "0,1" hexmask.long.word 0x4 13.--22. 1. "RESERVED_13_22,Reserved" newline bitfld.long 0x4 12. "U2P3CPMOK,P3CPM OK for U2/SSInactive (U2P3CPMok) - 0: During link state U2/SS.Inactive put PHY in P2 (Default) - 1: During link state U2/SS.Inactive put PHY in P3CPM. Note: For a port if both GUCTL1[25]=1 and LUCTL[12]=1 LUCTL[12]=1 takes priority." "During link state U2/SS,During link state U2/SS" bitfld.long 0x4 11. "EN_RESET_PIPE_AFTER_PHY_MUX,en_reset_pipe_after_phy_mux. The controller issues USB 3.0 PHY reset after DisRxDetU3RxDet is de-asserted." "0,1" bitfld.long 0x4 8.--10. "RESERVED_8_10,Reserved" "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 7. "MASK_PIPE_RESET,Mask pipe reset. If this bit is set controller blocks pipe_reset_n from going to the PHY when DisRxDetU3RxDet=1." "0,1" bitfld.long 0x4 6. "RESERVED_6,Reserved" "0,1" bitfld.long 0x4 5. "NO_UX_EXIT_P0_TRANS,no_ux_exit_p0_trans. Link LTSSM detects Ux_exit LFPS when P0 transition is on-going by default. If this bit is set Link LTSSM may miss Ux_exit LFPS when P0 transition is happening." "0,1" newline hexmask.long.byte 0x4 0.--4. 1. "RESERVED_0_4,Reserved" line.long 0x8 "LPTMDPDELAY,Link Datapath Delay Register - Link Layer Timer Register for P3CPM/P4 Residency. - This register is common for all SS ports." hexmask.long.word 0x8 22.--31. 1. "RESERVED_22_31,Reserved" hexmask.long.word 0x8 10.--21. 1. "P3CPMP4_RESIDENCY,p3cpmp4 residency timer value. Minimum number of suspend_clk periods that the controller needs to stay in P3.CPM or P4 before exiting P3.CPM or P4. This field is used only for Synopsys PHY." hexmask.long.word 0x8 0.--9. 1. "RESERVED_0_9,Reserved" tree.end tree "DWC_usb3_block_debug (USB 3.0 Debug Register Block)" group.long (0x0+0x55296)++0x3 line.long 0x0 "U3RHBDBG,U3 Root Hub Debug Register" hexmask.long 0x0 4.--31. 1. "RESERVED_1,Reserved_1" bitfld.long 0x0 3. "TPCFG_TOUT_CTRL,tpcfg_tout_ctrl This bit controls the USB 3.0 port configuration timeout duration. - 1: The port configuration timeout counter resets when the link is not in U0. - 0: The port configuration timeout counter does not reset if the link.." "The port configuration timeout counter does not..,The port configuration timeout counter resets.." rbitfld.long 0x0 0.--2. "RESERVED_0_2,Reserved_0_2" "0,1,2,3,4,5,6,7" tree.end tree "DWC_usb3_block_eXtensible_Host_Cntrl_Cap_Regs (USB 3.0 eXtensible Host Controller Capability Register Block)" rgroup.long (0x0+0x55296)++0x1F line.long 0x0 "CAPLENGTH,Capability Registers Length Host Controller Operational Registers = Base address + CAPLENGTH where CAPLENGTH is `DWC_USB3_HOST_CAP_REG_LEN whose default value is 20h." hexmask.long.word 0x0 16.--31. 1. "HCIVERSION,HC Interface Version Number (HCIVERSION)" hexmask.long.byte 0x0 8.--15. 1. "RESERVED_15_8,Reserved" hexmask.long.byte 0x0 0.--7. 1. "CAPLENGTH,Capability Registers Length (CAPLENGTH)" line.long 0x4 "HCSPARAMS1,Structural Parameters 1 Register For register definitions. refer to the xHCI specification." hexmask.long.byte 0x4 24.--31. 1. "MAXPORTS,Number of Ports (MaxPorts) - Number of ports implemented is defined by the parameter (`DWC_USB3_HOST_NUM_U2_ROOT_PORTS + `DWC_USB3_HOST_NUM_U3_ROOT_PORTS) - Number of ports enabled is controlled by the controller input signals.." hexmask.long.byte 0x4 19.--23. 1. "RESERVED_23_19,Reserved" hexmask.long.word 0x4 8.--18. 1. "MAXINTRS,Number of Interrupters (MaxIntrs) Defined by the configurable parameter `DWC_USB3_HOST_NUM_INTERRUPTER_SUPT" hexmask.long.byte 0x4 0.--7. 1. "MAXSLOTS,Number of device slots (MaxSlots) Defined by configurable parameter `DWC_USB3_NUM_DEVICE_SUPT" line.long 0x8 "HCSPARAMS2,Structural Parameters 2 Register For register definitions. refer to the xHCI specification." hexmask.long.byte 0x8 27.--31. 1. "MAXSCRATCHPADBUFS,Max Scratchpad Bufs Lo The value is calculated based on chosen configuration parameter values. Possible values are 1-4." bitfld.long 0x8 26. "SPR,Scratchpad Restore (SPR)" "0,1" hexmask.long.byte 0x8 21.--25. 1. "MAXSCRATCHPADBUFS_HI,Max Scratchpad Bufs HI The controller automatically updates this field." hexmask.long.word 0x8 8.--20. 1. "RESERVED_20_8,Reserved" newline hexmask.long.byte 0x8 4.--7. 1. "ERSTMAX,Event Ring Segment Table Max (ERST Max)" hexmask.long.byte 0x8 0.--3. 1. "IST,Isochronous Scheduling Threshold (IST)" line.long 0xC "HCSPARAMS3,Structural Parameters 3 Register For register definitions. refer to the xHCI specification." hexmask.long.word 0xC 16.--31. 1. "U2_DEVICE_EXIT_LAT,U2 Device Exit Latency" hexmask.long.byte 0xC 8.--15. 1. "RESERVED_15_8,Reserved" hexmask.long.byte 0xC 0.--7. 1. "U1_DEVICE_EXIT_LAT,U1 Device Exit Latency" line.long 0x10 "HCCPARAMS1,Capability Parameters 1 Register For register definitions. refer to the xHCI specification." hexmask.long.word 0x10 16.--31. 1. "XECP,xHCI Extended Capabilities Pointer (xECP) Based on configuration controller automatically updates it. Refer to /src/DWC_usb3_params.v for details on DWC_USB3_HC_XECP." hexmask.long.byte 0x10 12.--15. 1. "MAXPSASIZE,Maximum Primary Stream Array Size (MaxPSASize) For a description of this standard USB register field see the eXtensible Host Controller Interface for Universal Serial Bus (USB) Specification 3.0." bitfld.long 0x10 11. "CFC,Contiguous Frame ID Capability (CFC)" "0,1" bitfld.long 0x10 10. "SEC,Stopped EDLTA Capability (SEC) For a description of this standard USB register field see the eXtensible Host Controller Interface for Universal Serial Bus (USB) Specification 3.0." "0,1" newline bitfld.long 0x10 9. "SPC,Short Packet Capability (SPC) For a description of this standard USB register field see the eXtensible Host Controller Interface for Universal Serial Bus (USB) Specification 3.0." "0,1" bitfld.long 0x10 8. "PAE,Parse All Event Data (PAE) For a description of this standard USB register field see the eXtensible Host Controller Interface for Universal Serial Bus (USB) Specification 3.0." "0,1" bitfld.long 0x10 7. "NSS,No Secondary SID Support (NSS) For a description of this standard USB register field see the eXtensible Host Controller Interface for Universal Serial Bus (USB) Specification 3.0." "0,1" bitfld.long 0x10 6. "LTC,Latency Tolerance Messaging Capability (LTC) For a description of this standard USB register field see the eXtensible Host Controller Interface for Universal Serial Bus (USB) Specification 3.0." "0,1" newline bitfld.long 0x10 5. "LHRC,Light HC Reset Capability For a description of this standard USB register field see the eXtensible Host Controller Interface for Universal Serial Bus (USB) Specification 3.0." "0,1" bitfld.long 0x10 4. "PIND,Port Indicators (PIND) For a description of this standard USB register field see the eXtensible Host Controller Interface for Universal Serial Bus (USB) Specification 3.0." "0,1" bitfld.long 0x10 3. "PPC,Port Power Control For a description of this standard USB register field see the eXtensible Host Controller Interface for Universal Serial Bus (USB) Specification 3.0." "0,1" bitfld.long 0x10 2. "CSZ,Context Size (CSZ) For a description of this standard USB register field see the eXtensible Host Controller Interface for Universal Serial Bus (USB) Specification 3.0." "0,1" newline bitfld.long 0x10 1. "BNC,BW Negotiation Capability (BNC) For a description of this standard USB register field see the eXtensible Host Controller Interface for Universal Serial Bus (USB) Specification 3.0." "0,1" bitfld.long 0x10 0. "AC64,64-bit Addressing Capability (AC64) For a description of this standard USB register field see the eXtensible Host Controller Interface for Universal Serial Bus (USB) Specification 3.0." "0,1" line.long 0x14 "DBOFF,Doorbell Offset Register For register definitions. refer to the xHCI specification." hexmask.long 0x14 2.--31. 1. "DOORBELL_ARRAY_OFFSET,Doorbell Array Offset - RO Based on configuration the controller automatically updates it. For a description of this standard USB register field see the eXtensible Host Controller Interface for Universal Serial Bus (USB).." bitfld.long 0x14 0.--1. "RESERVED_1_0,Reserved" "0,1,2,3" line.long 0x18 "RTSOFF,Runtime Register Space Offset Register" hexmask.long 0x18 5.--31. 1. "RUNTIME_REG_SPACE_OFFSET,Runtime Register Space Offset Based on configuration the controller automatically updates it. For a description of this standard USB register field see the eXtensible Host Controller Interface for Universal Serial Bus (USB).." hexmask.long.byte 0x18 0.--4. 1. "RESERVED_4_0,Reserved" line.long 0x1C "HCCPARAMS2,Host Controller Capability Parameters 2 For register definitions. refer to the xHCI specification." hexmask.long 0x1C 6.--31. 1. "RESERVED_31_6,Reserved" bitfld.long 0x1C 5. "CIC,Configuration Information Capability (CIC) For a description of this standard USB register field see the eXtensible Host Controller I nterface for Universal Serial Bus (USB) Specification 3.0." "0,1" bitfld.long 0x1C 4. "LEC,Large ESIT Payload Capability (LEC) For a description of this standard USB register field see the eXtensible Host Controller I nterface for Universal Serial Bus (USB) Specification 3.0." "0,1" bitfld.long 0x1C 3. "CTC,Compliance Transition Capability (CTC) For a description of this standard USB register field see the eXtensible Host Controller I nterface for Universal Serial Bus (USB) Specification 3.0." "0,1" newline bitfld.long 0x1C 2. "FSC,Force Save Context Capability (FSC) For a description of this standard USB register field see the eXtensible Host Controller I nterface for Universal Serial Bus (USB) Specification 3.0." "0,1" bitfld.long 0x1C 1. "CMC,Configure Endpoint Command Max Exit Latency Too Large Capability (CMC) For a description of this standard USB register field see the eXtensible Host Controller I nterface for Universal Serial Bus (USB) Specification 3.0." "0,1" bitfld.long 0x1C 0. "U3C,U3 Entry Capability (U3C) For a description of this standard USB register field see the eXtensible Host Controller I nterface for Universal Serial Bus (USB) Specification 3.0." "0,1" tree.end tree "DWC_usb3_block_Host_Cntrl_Oper_Regs (USB3 Host Cntrl Oper Regs Block)" group.long (0x0+0x32)++0x7 line.long 0x0 "USBCMD,USB Command Register For a description of this standard USB register field see the eXtensible Host Controller Interface for Universal Serial Bus (USB) Specification 3.0." hexmask.long.tbyte 0x0 14.--31. 1. "RESERVED_31_14,Reserved" bitfld.long 0x0 13. "CME,CEM Enable For a description of this standard USB register field see the eXtensible Host Controller Interface for Universal Serial Bus (USB) Specification 3.0." "0,1" rbitfld.long 0x0 12. "RESERVED_12,Reserved" "0,1" bitfld.long 0x0 11. "EU3S,EU3S For a description of this standard USB register field see the eXtensible Host Controller Interface for Universal Serial Bus (USB) Specification 3.0." "0,1" bitfld.long 0x0 10. "EWE,EWE For a description of this standard USB register field see the eXtensible Host Controller Interface for Universal Serial Bus (USB) Specification 3.0." "0,1" newline bitfld.long 0x0 9. "CRS,Controller Restore State This command is similar to the USBCMD.CRS bit in host mode and initiates the restore process. When software sets this bit to '1' the controller immediately sets DSTS.RSS to '1'. When the controller has finished the restore.." "0,1" bitfld.long 0x0 8. "CSS,Controller Save State This command is similar to the USBCMD.CSS bit in host mode and initiates the save process. When software sets this bit to '1' the controller immediately sets DSTS.SSS to '1'. When the controller has finished the save process.." "0,1" bitfld.long 0x0 7. "LHCRST,Light Host Controller Reset For a description of this standard USB register field see the eXtensible Host Controller Interface for Universal Serial Bus (USB) Specification 3.0. The following bits reset the internal logic of the host controller." "0,1" rbitfld.long 0x0 4.--6. "RESERVED_6_4,Reserved" "0,1,2,3,4,5,6,7" bitfld.long 0x0 3. "HSEE,HSEE For a description of this standard USB register field see the eXtensible Host Controller Interface for Universal Serial Bus (USB) Specification 3.0." "0,1" newline bitfld.long 0x0 2. "INTE,INTE For a description of this standard USB register field see the eXtensible Host Controller Interface for Universal Serial Bus (USB) Specification 3.0." "0,1" bitfld.long 0x0 1. "HCRST,HCRST The following bits reset the internal logic of the host controller. Under soft reset some CSR accesses may fail (Timeout). - HCRST - LHCRST Bit Bash register testing is not recommended." "0,1" bitfld.long 0x0 0. "R_S,R_S For a description of this standard USB register field see the eXtensible Host Controller Interface for Universal Serial Bus (USB) Specification 3.0. Due to side-effects this reguster field is not recommended for Bit-Bash testing." "0,1" line.long 0x4 "USBSTS,USB Status Register Bit Definitions For a description of this standard USB register field. see the eXtensible Host Controller Interface for Universal Serial Bus (USB) Specification 3.0." hexmask.long.tbyte 0x4 13.--31. 1. "RESERVED_31_13,Reserved" rbitfld.long 0x4 12. "HCE,Host Controller Error (HCE) - RO Default = 0. '0' = No internal xHC error conditions exist and '1' = Internal xHC error condition. This flag must be set to indicate that an internal error condition has been detected which requires software to reset.." "0,1" rbitfld.long 0x4 11. "CNR,Controller Not Ready (CNR) - RO Default = '1'. '0' = Ready and '1' = Not Ready. Software must not write to thes Doorbell or Operational register of the xHC other than the USBSTS register until CNR = '0'. This flag is set by the xHC after a Chip.." "0,1" bitfld.long 0x4 10. "SRE,Save/Restore Error This bit is currently not supported." "0,1" rbitfld.long 0x4 9. "RSS,Restore State Status This bit is similar to the USBSTS.RSS in host mode. When the controller has finished the restore process it completes the command by setting DSTS.RSS to '0'." "0,1" newline rbitfld.long 0x4 8. "SSS,Save State Status This bit is similar to the USBSTS.SSS in host mode. When the controller has finished the save process it completes the command by setting DSTS.SSS to '0'." "0,1" rbitfld.long 0x4 5.--7. "RESERVED_7_5,Reserved" "0,1,2,3,4,5,6,7" bitfld.long 0x4 4. "PCD,Reset Value for PCD" "0,1" bitfld.long 0x4 3. "EINT,Reset Value for EINT" "0,1" bitfld.long 0x4 2. "HSE,HSE For a description of this standard USB register field see the eXtensible Host Controller Interface for Universal Serial Bus (USB) Specification 3.0.." "0,1" newline rbitfld.long 0x4 1. "RESERVED_1,Reserved" "0,1" rbitfld.long 0x4 0. "HCH,HCH For a description of this standard USB register field see the eXtensible Host Controller Interface for Universal Serial Bus (USB) Specification 3.0." "0,1" rgroup.long (0x8+0x32)++0x3 line.long 0x0 "PAGESIZE,Page Size Register Bit Definitions Use this register to enable or disable the reporting of specific USB Device Notification Transaction Packets being received. A Notification Enable (Nx. where x = 0 to 15) flag is defined for each of the 16.." hexmask.long.word 0x0 16.--31. 1. "RESERVED_31_16,Reserved" hexmask.long.word 0x0 0.--15. 1. "PAGE_SIZE,PAGE_SIZE" group.long (0x14+0x32)++0xB line.long 0x0 "DNCTRL,Device Notification Register Bit Definitions For a description of this standard USB register field see the eXtensible Host Controller Interface for Universal Serial Bus (USB) Specification 3.0." hexmask.long.word 0x0 16.--31. 1. "RESERVED_31_16,Reserved" hexmask.long.word 0x0 0.--15. 1. "N0_N15,N0_N15 For a description of this standard USB register field see the eXtensible Host Controller Interface for Universal Serial Bus (USB) Specification 3.0." line.long 0x4 "CRCR_LO,CRCR_LO For a description of this standard USB register field. see the eXtensible Host Controller Interface for Universal Serial Bus (USB) Specification 3.0." hexmask.long 0x4 6.--31. 1. "CMD_RING_PNTR,CMD_RING_PNTR For a description of this standard USB register field see the eXtensible Host Controller Interface for Universal Serial Bus (USB) Specification 3.0." rbitfld.long 0x4 4.--5. "RESERVED_5_4,Reserved" "0,1,2,3" rbitfld.long 0x4 3. "CRR,CRR For a description of this standard USB register field see the eXtensible Host Controller Interface for Universal Serial Bus (USB) Specification 3.0." "0,1" bitfld.long 0x4 2. "CA,CA For a description of this standard USB register field see the eXtensible Host Controller Interface for Universal Serial Bus (USB) Specification 3.0." "0,1" bitfld.long 0x4 1. "CS,CS For a description of this standard USB register field see the eXtensible Host Controller Interface for Universal Serial Bus (USB) Specification 3.0." "0,1" newline bitfld.long 0x4 0. "RCS,RCS For a description of this standard USB register field see the eXtensible Host Controller Interface for Universal Serial Bus (USB) Specification 3.0." "0,1" line.long 0x8 "CRCR_HI,CRCR_HI" hexmask.long 0x8 0.--31. 1. "CMD_RING_PNTR,COMMAND_RING_POINTER Reading this field always returns '0'. For a description of this standard USB register field see the eXtensible Host Controller Interface for Universal Serial Bus (USB) Specification 3.0." group.long (0x30+0x32)++0xB line.long 0x0 "DCBAAP_LO,DCBAAP_LO" hexmask.long 0x0 6.--31. 1. "DEVICE_CONTEXT_BAAP,DEVICE_CONTEXT_BAAP For a description of this standard USB register field see the eXtensible Host Controller Interface for Universal Serial Bus (USB) Specification 3.0." hexmask.long.byte 0x0 0.--5. 1. "RESERVED_5_0,Reserved" line.long 0x4 "DCBAAP_HI,DCBAAP_HI For a description of this standard USB register field. see the eXtensible Host Controller Interface for Universal Serial Bus (USB) Specification 3.0." hexmask.long 0x4 0.--31. 1. "DEVICE_CONTEXT_BAAP,DEVICE_CONTEXT_BAAP" line.long 0x8 "CONFIG,Configure Register Bit Definitions This register is in the Aux Power well. It is only reset by platform hardware during a cold reset or in response to a Host Controller Reset (HCRST). The initial conditions of a port are described in section 4.19.." hexmask.long.tbyte 0x8 10.--31. 1. "RESERVED_31_10,Reserved" bitfld.long 0x8 9. "CIE,Configuration Information Enable For a description of this standard USB register field see the eXtensible Host Controller Interface for Universal Serial Bus (USB) Specification 3.0." "0,1" bitfld.long 0x8 8. "U3E,U3 Entry Enable For a description of this standard USB register field see the eXtensible Host Controller Interface for Universal Serial Bus (USB) Specification 3.0." "0,1" hexmask.long.byte 0x8 0.--7. 1. "MAXSLOTSEN,MAXSLOTSEN For a description of this standard USB register field see the eXtensible Host Controller Interface for Universal Serial Bus (USB) Specification 3.0." tree.end tree "DWC_usb3_block_Host_Cntrl_Port_Reg_Set (USB3 Host Cntrl Port Reg Set Block)" group.long (0x0+0x1056)++0x7 line.long 0x0 "PORTSC_20,Port Status and Control Register Bit Definitions The PORTSC Register Access fails (Timeout) if the UTMI/ULPI clock is not running or one of the following bits is asserted. - PR - ORC" rbitfld.long 0x0 31. "RESERVED_31,Reserved For a description of this standard USB register field see the eXtensible Host Controller Interface for Universal Serial Bus (USB) Specification 3.0. Programming this field with random data will cause side effect i.e. Register Access.." "0,1" rbitfld.long 0x0 30. "DR,Reset Value For a description of this standard USB register field see the eXtensible Host Controller Interface for Universal Serial Bus (USB) Specification 3.0." "0,1" rbitfld.long 0x0 28.--29. "RESERVED_29_28,Reserved" "0,1,2,3" bitfld.long 0x0 27. "WOE,WOE For a description of this standard USB register field see the eXtensible Host Controller Interface for Universal Serial Bus (USB) Specification 3.0." "0,1" newline bitfld.long 0x0 26. "WDE,WDE For a description of this standard USB register field see the eXtensible Host Controller Interface for Universal Serial Bus (USB) Specification 3.0." "0,1" bitfld.long 0x0 25. "WCE,WCE For a description of this standard USB register field see the eXtensible Host Controller Interface for Universal Serial Bus (USB) Specification 3.0." "0,1" rbitfld.long 0x0 24. "CAS,Cold Attach Status For a description of this standard USB register field see the eXtensible Host Controller Interface for Universal Serial Bus (USB) Specification 3.0." "0,1" rbitfld.long 0x0 23. "RESERVED_23,Reserved For a description of this standard USB register field see the eXtensible Host Controller Interface for Universal Serial Bus (USB) Specification 3.0." "0,1" newline bitfld.long 0x0 22. "PLC,PLC For a description of this standard USB register field see the eXtensible Host Controller Interface for Universal Serial Bus (USB) Specification 3.0." "0,1" bitfld.long 0x0 21. "PRC,PRC For a description of this standard USB register field see the eXtensible Host Controller Interface for Universal Serial Bus (USB) Specification 3.0. Programming this field with random data will cause side effect. Bit Bash register testing is not.." "0,1" bitfld.long 0x0 20. "OCC,OCC For a description of this standard USB register field see the eXtensible Host Controller Interface for Universal Serial Bus (USB) Specification 3.0." "0,1" bitfld.long 0x0 19. "RESERVED_19,WRC For a description of this standard USB register field see the eXtensible Host Controller Interface for Universal Serial Bus (USB) Specification 3.0." "0,1" newline bitfld.long 0x0 18. "PEC,PEC For a description of this standard USB register field see the eXtensible Host Controller Interface for Universal Serial Bus (USB) Specification 3.0." "0,1" bitfld.long 0x0 17. "CSC,CSC For a description of this standard USB register field see the eXtensible Host Controller Interface for Universal Serial Bus (USB) Specification 3.0." "0,1" bitfld.long 0x0 16. "LWS,LWS For a description of this standard USB register field see the eXtensible Host Controller Interface for Universal Serial Bus (USB) Specification 3.0." "0,1" bitfld.long 0x0 14.--15. "PIC,PIC For a description of this standard USB register field see the eXtensible Host Controller Interface for Universal Serial Bus (USB) Specification 3.0." "0,1,2,3" newline hexmask.long.byte 0x0 10.--13. 1. "PORTSPEED,PORTSPEED For a description of this standard USB register field see the eXtensible Host Controller Interface for Universal Serial Bus (USB) Specification 3.0." bitfld.long 0x0 9. "PP,PP For a description of this standard USB register field see the eXtensible Host Controller Interface for Universal Serial Bus (USB) Specification 3.0." "0,1" hexmask.long.byte 0x0 5.--8. 1. "PLS,PLS For a description of this standard USB register field see the eXtensible Host Controller Interface for Universal Serial Bus (USB) Specification 3.0." bitfld.long 0x0 4. "PR,PR set_register_field_attribute DWC_usb3_map/DWC_usb3_block_Host_Cntrl_Port_Reg_Set/PORTSC_20_REGS/PORTSC_20/PR VolatileMemory 1 Programming this field with random data will cause side effect. Bit Bash register testing is not recommended." "0,1" newline rbitfld.long 0x0 3. "OCA,OCA For a description of this standard USB register field see the eXtensible Host Controller Interface for Universal Serial Bus (USB) Specification 3.0." "0,1" rbitfld.long 0x0 2. "RESERVED_2,Reserved" "0,1" bitfld.long 0x0 1. "PED,PED For a description of this standard USB register field see the eXtensible Host Controller Interface for Universal Serial Bus (USB) Specification 3.0." "0,1" rbitfld.long 0x0 0. "CCS,CCS For a description of this standard USB register field see the eXtensible Host Controller Interface for Universal Serial Bus (USB) Specification 3.0." "0,1" line.long 0x4 "PORTPMSC_20,USB3 Port Power Management Status and Control Register Bit Definitions This register is in the Aux Power well. It is only reset by platform hardware during a cold reset or in response to a Host Controller Reset (HCRST). Programming this field.." hexmask.long.byte 0x4 28.--31. 1. "PRTTSTCTRL,Port Test Control For a description of this standard USB register field see the eXtensible Host Controller Interface for Universal Serial Bus (USB) Specification 3.0." hexmask.long.word 0x4 17.--27. 1. "RESERVED_27_17,Reserved" bitfld.long 0x4 16. "HLE,Port Test Control For a description of this standard USB register field see the eXtensible Host Controller Interface for Universal Serial Bus (USB) Specification 3.0." "0,1" hexmask.long.byte 0x4 8.--15. 1. "L1DSLOT,L1DSLOT For a description of this standard USB register field see the eXtensible Host Controller Interface for Universal Serial Bus (USB) Specification 3.0." newline hexmask.long.byte 0x4 4.--7. 1. "HIRD,Host Initiated Resume Duration (HIRD) - RW. Default = '0'. System software sets this field to indicate to the recipient device how long the xHC will drive resume if it (the xHC) initiates an exit from L1. The HIRD value is encoded as follows: Value.." bitfld.long 0x4 3. "RWE,RWE Port Test Control For a description of this standard USB register field see the eXtensible Host Controller Interface for Universal Serial Bus (USB) Specification 3.0." "0,1" rbitfld.long 0x4 0.--2. "L1S,L1 Status (L1S) - RO. Default = 0. This field is used by software to determine whether an L1-based suspend request (LMP transaction) was successful specifically: Value Meaning 0 Invalid - This field is ignored by software. - 1 Success - Port.." "?,based suspend request,?,?,?,?,?,?" rgroup.long (0x8+0x1056)++0x3 line.long 0x0 "PORTLI_20,Port Link Info Register Programming this field with random data will cause side effect i.e. Register Access will fail (Timeout) if the pipe clock is not running or reset is asserted . Bit Bash register testing is not recommended." hexmask.long 0x0 0.--31. 1. "RESERVED_31_0,Reserved" group.long (0xC+0x1056)++0xB line.long 0x0 "PORTHLPMC_20,USB2 Port Hardware LPM Control Register Bit Definitions For a description of this standard USB register field. see the eXtensible Host Controller Interface for Universal Serial Bus (USB) Specification 3.0." hexmask.long.tbyte 0x0 14.--31. 1. "RESERVED_31_14,Reserved For a description of this standard USB register field see the eXtensible Host Controller Interface for Universal Serial Bus (USB) Specification 3.0." hexmask.long.byte 0x0 10.--13. 1. "HIRDD,PORTHLPMC_20 HIRDD" hexmask.long.byte 0x0 2.--9. 1. "L1_TIMEOUT,PORTHLPMC_20 L1_TIMEOUT. For a description of this standard USB register field see the eXtensible Host Controller Interface for Universal Serial Bus (USB) Specification 3.0." bitfld.long 0x0 0.--1. "HIRDM,Host Initiated Resume Duration Mode (HIRDM) - RWS. Default = 0h. Indicates which HIRD value must be used. The following are permissible values: Value Description 0 Initiate L1 using HIRD only on timeout. (default) 1 Initiate L1 using HIRDD on.." "0,1,2,3" line.long 0x4 "PORTSC_30,Port Status and Control Register Bit Definitions The PORTSC Register Access fails (Timeout) if the UTMI/ULPI clock is not running or one of the following bits is asserted. - PR - ORC - WPR" bitfld.long 0x4 31. "WPR,Reset Value For a description of this standard USB register field see the eXtensible Host Controller Interface for Universal Serial Bus (USB) Specification 3.0. Programming this field with random data will cause side effect i.e. Register Access will.." "0,1" rbitfld.long 0x4 30. "DR,Reset Value For a description of this standard USB register field see the eXtensible Host Controller Interface for Universal Serial Bus (USB) Specification 3.0." "0,1" rbitfld.long 0x4 28.--29. "RESERVED_29_28,Reserved" "0,1,2,3" bitfld.long 0x4 27. "WOE,WOE For a description of this standard USB register field see the eXtensible Host Controller Interface for Universal Serial Bus (USB) Specification 3.0." "0,1" newline bitfld.long 0x4 26. "WDE,WDE For a description of this standard USB register field see the eXtensible Host Controller Interface for Universal Serial Bus (USB) Specification 3.0." "0,1" bitfld.long 0x4 25. "WCE,WCE For a description of this standard USB register field see the eXtensible Host Controller Interface for Universal Serial Bus (USB) Specification 3.0." "0,1" rbitfld.long 0x4 24. "CAS,Cold Attach Status For a description of this standard USB register field see the eXtensible Host Controller Interface for Universal Serial Bus (USB) Specification 3.0." "0,1" bitfld.long 0x4 23. "CEC,CEC For a description of this standard USB register field see the eXtensible Host Controller Interface for Universal Serial Bus (USB) Specification 3.0." "0,1" newline bitfld.long 0x4 22. "PLC,PLC For a description of this standard USB register field see the eXtensible Host Controller Interface for Universal Serial Bus (USB) Specification 3.0." "0,1" bitfld.long 0x4 21. "PRC,PRC For a description of this standard USB register field see the eXtensible Host Controller Interface for Universal Serial Bus (USB) Specification 3.0. Programming this field with random data will cause side effect. Bit Bash register testing is not.." "0,1" bitfld.long 0x4 20. "OCC,OCC For a description of this standard USB register field see the eXtensible Host Controller Interface for Universal Serial Bus (USB) Specification 3.0." "0,1" bitfld.long 0x4 19. "WRC,WRC For a description of this standard USB register field see the eXtensible Host Controller Interface for Universal Serial Bus (USB) Specification 3.0." "0,1" newline bitfld.long 0x4 18. "PEC,PEC For a description of this standard USB register field see the eXtensible Host Controller Interface for Universal Serial Bus (USB) Specification 3.0." "0,1" bitfld.long 0x4 17. "CSC,CSC For a description of this standard USB register field see the eXtensible Host Controller Interface for Universal Serial Bus (USB) Specification 3.0." "0,1" bitfld.long 0x4 16. "LWS,LWS For a description of this standard USB register field see the eXtensible Host Controller Interface for Universal Serial Bus (USB) Specification 3.0." "0,1" bitfld.long 0x4 14.--15. "PIC,PIC For a description of this standard USB register field see the eXtensible Host Controller Interface for Universal Serial Bus (USB) Specification 3.0." "0,1,2,3" newline hexmask.long.byte 0x4 10.--13. 1. "PORTSPEED,PORTSPEED For a description of this standard USB register field see the eXtensible Host Controller Interface for Universal Serial Bus (USB) Specification 3.0." bitfld.long 0x4 9. "PP,PP For a description of this standard USB register field see the eXtensible Host Controller Interface for Universal Serial Bus (USB) Specification 3.0." "0,1" hexmask.long.byte 0x4 5.--8. 1. "PLS,PLS For a description of this standard USB register field see the eXtensible Host Controller Interface for Universal Serial Bus (USB) Specification 3.0." bitfld.long 0x4 4. "PR,PR set_register_field_attribute DWC_usb3_map/DWC_usb3_block_Host_Cntrl_Port_Reg_Set/PORTSC_30_REGS/PORTSC_30/PR VolatileMemory 1 Programming this field with random data will cause side effect. Bit Bash register testing is not recommended." "0,1" newline rbitfld.long 0x4 3. "OCA,OCA For a description of this standard USB register field see the eXtensible Host Controller Interface for Universal Serial Bus (USB) Specification 3.0." "0,1" rbitfld.long 0x4 2. "RESERVED_2,Reserved" "0,1" bitfld.long 0x4 1. "PED,PED For a description of this standard USB register field see the eXtensible Host Controller Interface for Universal Serial Bus (USB) Specification 3.0." "0,1" rbitfld.long 0x4 0. "CCS,CCS For a description of this standard USB register field see the eXtensible Host Controller Interface for Universal Serial Bus (USB) Specification 3.0." "0,1" line.long 0x8 "PORTPMSC_30,USB3 Port Power Management Status and Control Register Bit Definitions This register is in the Aux Power well. It is only reset by platform hardware during a cold reset or in response to a Host Controller Reset (HCRST). Programming this field.." hexmask.long.word 0x8 17.--31. 1. "RESERVED_31_17,Reserved" bitfld.long 0x8 16. "FLA,FLA For a description of this standard USB register field see the eXtensible Host Controller Interface for Universal Serial Bus (USB) Specification 3.0." "0,1" hexmask.long.byte 0x8 8.--15. 1. "U2_TIMEOUT,U2_TIMEOUT For a description of this standard USB register field see the eXtensible Host Controller Interface for Universal Serial Bus (USB) Specification 3.0." hexmask.long.byte 0x8 0.--7. 1. "U1_TIMEOUT,U1_TIMEOUT For a description of this standard USB register field see the eXtensible Host Controller Interface for Universal Serial Bus (USB) Specification 3.0." rgroup.long (0x18+0x1056)++0x7 line.long 0x0 "PORTLI_30,Port Link Info Register Programming this field with random data will cause side effect i.e. Register Access will fail (Timeout) if the pipe clock is not running or reset is asserted . Bit Bash register testing is not recommended." hexmask.long.word 0x0 16.--31. 1. "RESERVED_31_16,Reserved" hexmask.long.word 0x0 0.--15. 1. "LINK_ERROR_COUNT,LINK_ERROR_COUNT For a description of this standard USB register field see the eXtensible Host Controller Interface for Universal Serial Bus (USB) Specification 3.0." line.long 0x4 "PORTHLPMC_30,USB2 Port Hardware LPM Control Register Bit Definitions For a description of this standard USB register field. see the eXtensible Host Controller Interface for Universal Serial Bus (USB) Specification 3.0." hexmask.long 0x4 0.--31. 1. "RESERVED_31_0,Reserved For a description of this standard USB register field see the eXtensible Host Controller Interface for Universal Serial Bus (USB) Specification 3.0." tree.end tree "DWC_usb3_block_Host_Cntrl_Runtime_Regs (USB3 Host Cntrl Runtime Regs Block)" rgroup.long (0x0+0x1088)++0x7 line.long 0x0 "MFINDEX,Microframe Index Register Bit Definitions For a description of this standard USB register field. see the eXtensible Host Controller Interface for Universal Serial Bus (USB) Specification 3.0." hexmask.long.tbyte 0x0 14.--31. 1. "RESERVED_31_14,Reserved" hexmask.long.word 0x0 0.--13. 1. "MICROFRAME_INDEX,MICROFRAME_INDEX For a description of this standard USB register field see the eXtensible Host Controller Interface for Universal Serial Bus (USB) Specification 3.0." line.long 0x4 "RSVDZ,RsvdZ For a description of this standard USB register field. see the eXtensible Host Controller Interface for Universal Serial Bus (USB) Specification 3.0." hexmask.long 0x4 0.--31. 1. "RESERVED_31_0,Reserved" tree.end tree "DWC_usb3_block_Interrupter_Regs (USB3 Interrupter Regs Block)" group.long (0x0+0x1120)++0xB line.long 0x0 "IMAN,Interrupter Management Register Bit Definitions For a description of this standard USB register field. see the eXtensible Host Controller Interface for Universal Serial Bus (USB) Specification 3.0." hexmask.long 0x0 2.--31. 1. "RESERVED_31_2,Reserved" bitfld.long 0x0 1. "IE,IE For a description of this standard USB register field see the eXtensible Host Controller Interface for Universal Serial Bus (USB) Specification 3.0." "0,1" bitfld.long 0x0 0. "IP,IP Interrupt Pending For a description of this standard USB register field see the eXtensible Host Controller Interface for Universal Serial Bus (USB) Specification 3.0." "0,1" line.long 0x4 "IMOD,Interrupter Moderation Register The software may use this register to pace (or even out) the delivery of interrupts to the host CPU. This register provides a guaranteed inter-interrupt delay between interrupts asserted by the xHC. regardless of USB.." hexmask.long.word 0x4 16.--31. 1. "IMODC,Interrupt Moderation Counter (IMODC) - RW. Default = undefined. Down counter. Loaded with the IMODI value whenever IP is cleared to '0' counts down to '0' and stops. The associated interrupt is signaled whenever this counter is '0' the Event.." hexmask.long.word 0x4 0.--15. 1. "IMODI,Interrupt Moderation Interval (IMODI) - RW. Default = '4000' (~1ms). Minimum inter-interrupt interval. The interval is specified in 250ns increments. A value of '0' disables interrupt throttling logic and interrupts is generated immediately if IP =.." line.long 0x8 "ERSTSZ,Event Ring Segment Table Size Register Bit Definitions For a description of this standard USB register field. see the eXtensible Host Controller Interface for Universal Serial Bus (USB) Specification 3.0." hexmask.long.word 0x8 16.--31. 1. "RESERVED_31_16,Reserved" hexmask.long.word 0x8 0.--15. 1. "ERS_TABLE_SIZE,ERS_TABLE_SIZE For a description of this standard USB register field see the eXtensible Host Controller Interface for Universal Serial Bus (USB) Specification 3.0." rgroup.long (0xC+0x1120)++0x3 line.long 0x0 "RSVDP,RsvdP" hexmask.long 0x0 0.--31. 1. "RESERVED_31_0,Reserved" group.long (0x10+0x1120)++0xF line.long 0x0 "ERSTBA_LO,ERSTBA_LO" hexmask.long 0x0 6.--31. 1. "ERS_TABLE_BAR,ERS_TABLE_BAR" hexmask.long.byte 0x0 0.--5. 1. "RESERVED_5_0,Reserved" line.long 0x4 "ERSTBA_HI,ERSTBA_HI" hexmask.long 0x4 0.--31. 1. "ERS_TABLE_BAR,ERS_TABLE_BAR For a description of this standard USB register field see the eXtensible Host Controller Interface for Universal Serial Bus (USB) Specification 3.0." line.long 0x8 "ERDP_LO,ERDP_LO For a description of this standard USB register field. see the eXtensible Host Controller Interface for Universal Serial Bus (USB) Specification 3.0." hexmask.long 0x8 4.--31. 1. "ERD_PNTR,ERD_PNTR For a description of this standard USB register field see the eXtensible Host Controller Interface for Universal Serial Bus (USB) Specification 3.0." bitfld.long 0x8 3. "EHB,HC OS Owned SemaphoreERS_TABLE_SIZEHC BIOS Owned Semaphore USB SMI Enable SMI on Host System Error Enable - SMI on OS Ownership Enable - SMI on PCI Command Enable - SMI on BAR Enable - SMI on Event Interrupt - SMI on Host System Error - SMI on OS.." "0,1" bitfld.long 0x8 0.--2. "DESI,DESI - For a description of this standard USB register field see the eXtensible Host Controller Interface for Universal Serial Bus (USB) Specification 3.0." "0,1,2,3,4,5,6,7" line.long 0xC "ERDP_HI,ERDP_HI" hexmask.long 0xC 0.--31. 1. "ERD_PNTR,ERD_PNTR For a description of this standard USB register field see the eXtensible Host Controller Interface for Universal Serial Bus (USB) Specification 3.0." tree.end tree "DWC_usb3_block_Doorbell_Register (USB3 Doorbell Reg Block)" group.long (0x0+0x1152)++0x3 line.long 0x0 "DB,Doorbell Register Bit Field Definitions For a description of this standard USB register field. see the eXtensible Host Controller Interface for Universal Serial Bus (USB) Specification 3.0. Programming this field with random data will cause side.." hexmask.long.word 0x0 16.--31. 1. "DB_STREAM_ID,DB_STREAM_ID For a description of this standard USB register field see the eXtensible Host Controller Interface for Universal Serial Bus (USB) Specification 3.0." hexmask.long.byte 0x0 8.--15. 1. "RESERVED_15_8,Reserved" hexmask.long.byte 0x0 0.--7. 1. "DB_TARGET,DB_TARGET For a description of this standard USB register field see the eXtensible Host Controller Interface for Universal Serial Bus (USB) Specification 3.0." tree.end tree "DWC_usb3_block_HC_Extended_Capability_Register (USB3 HC Extended Capability Register Block)" group.long (0x0+0x2176)++0x7 line.long 0x0 "USBLEGSUP,USBLEGSUP" hexmask.long.byte 0x0 25.--31. 1. "RESERVED_31_25,Reserved" bitfld.long 0x0 24. "HC_OS_OWNED,HC_OS_OWNED SEMAPHORE For a description of this standard USB register field see the eXtensible Host Controller Interface for Universal Serial Bus (USB) Specification 3.0." "0,1" hexmask.long.byte 0x0 17.--23. 1. "RESERVED_23_17,Reserved" bitfld.long 0x0 16. "HC_BIOS_OWNED,HC_BIOS_OWNED SEMAPHORE For a description of this standard USB register field see the eXtensible Host Controller Interface for Universal Serial Bus (USB) Specification 3.0." "0,1" newline hexmask.long.byte 0x0 8.--15. 1. "NEXT_CAPABILITY_POINTER,NEXT_CAPABILITY_POINTER For a description of this standard USB register field see the eXtensible Host Controller Interface for Universal Serial Bus (USB) Specification 3.0." hexmask.long.byte 0x0 0.--7. 1. "CAPABILITY_ID,CAPABILITY_ID set_register_field_attribute DWC_usb3_map/DWC_usb3_block_HC_Extended_Capability_Register/USBLEGSUP/CAPABILITY_ID RegisterResetValue 0x1 For a description of this standard USB register field see the eXtensible Host Controller.." line.long 0x4 "USBLEGCTLSTS,USBLEGCTLSTS" bitfld.long 0x4 31. "SMI_ON_BAR,SMI_ON_BAR For a description of this standard USB register field see the eXtensible Host Controller Interface for Universal Serial Bus (USB) Specification 3.0." "0,1" bitfld.long 0x4 30. "SMI_ON_PCI,SMI_ON_PCI COMMAND For a description of this standard USB register field see the eXtensible Host Controller Interface for Universal Serial Bus (USB) Specification 3.0." "0,1" bitfld.long 0x4 29. "SMI_ON_OS,SMI_ON_OS OWNERSHIP CHANGE For a description of this standard USB register field see the eXtensible Host Controller Interface for Universal Serial Bus (USB) Specification 3.0." "0,1" hexmask.long.byte 0x4 21.--28. 1. "RESERVED_28_21,Reserved" newline rbitfld.long 0x4 20. "SMI_ON_HOST,SMI_ON_HOST SYSTEM ERROR For a description of this standard USB register field see the eXtensible Host Controller Interface for Universal Serial Bus (USB) Specification 3.0." "0,1" rbitfld.long 0x4 17.--19. "RESERVED_19_17,Reserved" "0,1,2,3,4,5,6,7" rbitfld.long 0x4 16. "SMI_ON_EVENT,SMI_ON_EVENT INTERRUPT For a description of this standard USB register field see the eXtensible Host Controller Interface for Universal Serial Bus (USB) Specification 3.0." "0,1" bitfld.long 0x4 15. "SMI_ON_BAR_E,SMI_ON_BAR ENABLE For a description of this standard USB register field see the eXtensible Host Controller Interface for Universal Serial Bus (USB) Specification 3.0." "0,1" newline bitfld.long 0x4 14. "SMI_ON_PCI_E,SMI_ON_PCI COMMAND ENABLE For a description of this standard USB register field see the eXtensible Host Controller Interface for Universal Serial Bus (USB) Specification 3.0." "0,1" bitfld.long 0x4 13. "SMI_ON_OS_E,SMI_ON_OS OWNERSHIP ENABLE For a description of this standard USB register field see the eXtensible Host Controller Interface for Universal Serial Bus (USB) Specification 3.0." "0,1" hexmask.long.byte 0x4 5.--12. 1. "RESERVED_12_5,Reserved" bitfld.long 0x4 4. "SMI_ON_HOST_E,SMI_ON_HOST SYSTEM ERROR ENABLE For a description of this standard USB register field see the eXtensible Host Controller Interface for Universal Serial Bus (USB) Specification 3.0." "0,1" newline rbitfld.long 0x4 1.--3. "RESERVED_3_1,Reserved" "0,1,2,3,4,5,6,7" bitfld.long 0x4 0. "USB_SMI_ENABLE,USB_SMI_ENABLE For a description of this standard USB register field see the eXtensible Host Controller Interface for Universal Serial Bus (USB) Specification 3.0." "0,1" tree.end tree "DWC_usb3_block_xHCI_Supt_USB20_Prt_Cap (USB3 xHCI Supported Protocol Capability (USB 2.0) Block)" rgroup.long (0x0+0x2192)++0xF line.long 0x0 "SUPTPRT2_DW0,SUPTPRT2_DW0" hexmask.long.byte 0x0 24.--31. 1. "MAJOR_REVISION,MAJOR_REVISION" hexmask.long.byte 0x0 16.--23. 1. "MINOR_REVISION,MINOR_REVISION" hexmask.long.byte 0x0 8.--15. 1. "NEXT_CAPABILITY_POINTER,NEXT_CAPABILITY_POINTER" newline hexmask.long.byte 0x0 0.--7. 1. "CAPABILITY_ID,CAPABILITY_ID For a description of this standard USB register field see the eXtensible Host Controller Interface for Universal Serial Bus (USB) Specification 3.0." line.long 0x4 "SUPTPRT2_DW1,Register SUPTPRT2_DW1" hexmask.long 0x4 0.--31. 1. "NAME_STRING,NAME_STRING For a description of this standard USB register field see the eXtensible Host Controller Interface for Universal Serial Bus (USB) Specification 3.0." line.long 0x8 "SUPTPRT2_DW2,xHCI Supported Protocol Capability_ Data Word 2 For a description of other register fields. see section 7.2 of the eXtensible Host Controller Interface for Universal Serial Bus (USB) Specification 3.0." hexmask.long.byte 0x8 28.--31. 1. "PSIC,PSIC" bitfld.long 0x8 25.--27. "MHD,Hub Depth For a description of this standard USB register field see the eXtensible Host Controller Interface for Universal Serial Bus (USB) Specification 3.0." "0,1,2,3,4,5,6,7" hexmask.long.byte 0x8 21.--24. 1. "RESERVED_24_21,Reserved" newline bitfld.long 0x8 20. "BLC,BESL LPM Capability. When this bit is set to: - 1: The ports described by this xHCI Supported Protocol Capability applies BESL timing to the BESL and BESLD fields of the PORTPMSC and PORTHLPMC registers. - 0: The ports described by this xHCI.." "The ports described by this xHCI Supported..,The ports described by this xHCI Supported.." bitfld.long 0x8 19. "HLC,Compatible Port Offset. Compatible Port Count Refer to Table 7-3 in the Databook." "0,1" bitfld.long 0x8 18. "IHI,IHI" "0,1" newline bitfld.long 0x8 17. "HSO,HSO" "0,1" hexmask.long.byte 0x8 8.--15. 1. "COMPATIBLE_PORT_COUNT,COMPATIBLE_PORT_COUNT For a description of this standard USB register field see the eXtensible Host Controller Interface for Universal Serial Bus (USB) Specification 3.0." hexmask.long.byte 0x8 0.--7. 1. "COMPATIBLE_PORT_OFFSET,COMPATIBLE_PORT_OFFSET For a description of this standard USB register field see the eXtensible Host Controller Interface for Universal Serial Bus (USB) Specification 3.0." line.long 0xC "SUPTPRT2_DW3,Register SUPTPRT2_DW3" hexmask.long 0xC 5.--31. 1. "RESERVED_31_5,Reserved" hexmask.long.byte 0xC 0.--4. 1. "PROTCL_SLT_TY,Protocol Slot Type" tree.end tree "DWC_usb3_block_xHCI_Supt_USB30_Prt_Cap (USB3 xHCI Supported Protocol Capability (USB 3.0) Block)" rgroup.long (0x0+0x2208)++0xF line.long 0x0 "SUPTPRT3_DW0,Register SUPTPRT3_DW0" hexmask.long.byte 0x0 24.--31. 1. "MAJOR_REVISION,MAJOR_REVISION For a description of this standard USB register field see the eXtensible Host Controller Interface for Universal Serial Bus (USB) Specification 3.0." hexmask.long.byte 0x0 16.--23. 1. "MINOR_REVISION,MINOR_REVISION For a description of this standard USB register field see the eXtensible Host Controller Interface for Universal Serial Bus (USB) Specification 3.0." hexmask.long.byte 0x0 8.--15. 1. "NEXT_CAPABILITY_POINTER,NEXT_CAPABILITY_POINTER For a description of this standard USB register field see the eXtensible Host Controller Interface for Universal Serial Bus (USB) Specification 3.0." hexmask.long.byte 0x0 0.--7. 1. "CAPABILITY_ID,CAPABILITY_ID For a description of this standard USB register field see the eXtensible Host Controller Interface for Universal Serial Bus (USB) Specification 3.0." line.long 0x4 "SUPTPRT3_DW1,Register SUPTPRT3_DW1" hexmask.long 0x4 0.--31. 1. "NAME_STRING,NAME_STRING For a description of this standard USB register field see the eXtensible Host Controller Interface for Universal Serial Bus (USB) Specification 3.0." line.long 0x8 "SUPTPRT3_DW2,SUPTPRT3_DW2 For a description of this standard USB register field. see the eXtensible Host Controller Interface for Universal Serial Bus (USB) Specification 3.0." hexmask.long.byte 0x8 28.--31. 1. "PSIC,PSIC" bitfld.long 0x8 25.--27. "MHD,Hub Depth For a description of this standard USB register field see the eXtensible Host Controller Interface for Universal Serial Bus (USB) Specification 3.0." "0,1,2,3,4,5,6,7" hexmask.long.byte 0x8 8.--15. 1. "COMPATIBLE_PORT_COUNT,COMPATIBLE_PORT_COUNT For a description of this standard USB register field see the eXtensible Host Controller Interface for Universal Serial Bus (USB) Specification 3.0." hexmask.long.byte 0x8 0.--7. 1. "COMPATIBLE_PORT_OFFSET,COMPATIBLE_PORT_OFFSET For a description of this standard USB register field see the eXtensible Host Controller Interface for Universal Serial Bus (USB) Specification 3.0." line.long 0xC "SUPTPRT3_DW3,SUPTPRT3_DW3" hexmask.long 0xC 5.--31. 1. "RESERVED_31_5,Reserved" hexmask.long.byte 0xC 0.--4. 1. "PROTCL_SLT_TY,Protocol Slot Type" tree.end tree "DWC_usb3_block_Debug_Capability_Structure (USB3 Debug Capability Structure Block)" rgroup.long (0x0+0x2224)++0x3 line.long 0x0 "DCID,DCID" hexmask.long.word 0x0 21.--31. 1. "RESERVED_31_21,Reserved" hexmask.long.byte 0x0 16.--20. 1. "DCERSTMAX,DCERSTMAX" hexmask.long.byte 0x0 8.--15. 1. "NEXT_CAPABILITY_POINTER,NEXT_CAPABILITY_POINTER" hexmask.long.byte 0x0 0.--7. 1. "CAPABILITY_ID,CAPABILITY_ID" group.long (0x4+0x2224)++0x7 line.long 0x0 "DCDB,Register DCDB" hexmask.long.word 0x0 16.--31. 1. "RESERVED_31_16,Reserved" hexmask.long.byte 0x0 8.--15. 1. "DBTARGET,DBTARGET" hexmask.long.byte 0x0 0.--7. 1. "RESERVED_7_0,Reserved" line.long 0x4 "DCERSTSZ,DCERSTSZ" hexmask.long.word 0x4 16.--31. 1. "RESERVED_31_16,Reserved" hexmask.long.word 0x4 0.--15. 1. "ERS_TABLE_SIZE,ERS_TABLE_SIZE" group.long (0x10+0x2224)++0x13 line.long 0x0 "DCERSTBA_LO,DCERSTBA_LO" hexmask.long 0x0 4.--31. 1. "ERS_TABLE_BAR,ERS_TABLE_BAR" hexmask.long.byte 0x0 0.--3. 1. "RESERVED_3_0,Reserved" line.long 0x4 "DCERSTBA_HI,Register DCERSTBA_HI" hexmask.long 0x4 0.--31. 1. "ERS_TABLE_BAR,ERS_TABLE_BAR" line.long 0x8 "DCERDP_LO,DCERDP_LO" hexmask.long 0x8 4.--31. 1. "DEQUEUE_POINTER,DEQUEUE_POINTER" rbitfld.long 0x8 3. "RESERVED_3,Reserved" "0,1" bitfld.long 0x8 0.--2. "DESI,DESI" "0,1,2,3,4,5,6,7" line.long 0xC "DCERDP_HI,DCERDP_HI" hexmask.long 0xC 0.--31. 1. "DEQUEUE_POINTER,DEQUEUE_POINTER" line.long 0x10 "DCCTRL,DCCTRL" bitfld.long 0x10 31. "DCE,DCE" "0,1" hexmask.long.byte 0x10 24.--30. 1. "DEVICE_ADDRESS,DEVICE_ADDRESS" hexmask.long.byte 0x10 16.--23. 1. "DEBUG_MAX_BURST_SIZE,DEBUG_PROTOCOL" hexmask.long.word 0x10 5.--15. 1. "RESERVED_15_5,Reserved" newline bitfld.long 0x10 4. "DRC,DRC" "0,1" bitfld.long 0x10 3. "HIT,HIT" "0,1" bitfld.long 0x10 2. "HOT,HOT" "0,1" bitfld.long 0x10 1. "LSE,LSE" "0,1" newline rbitfld.long 0x10 0. "DCR,DCR" "0,1" rgroup.long (0x24+0x2224)++0x3 line.long 0x0 "DCST,DCST" hexmask.long.byte 0x0 24.--31. 1. "DEBUG_PORT_NUMBER,DEBUG_PORT_NUMBER" hexmask.long.tbyte 0x0 2.--23. 1. "RESERVED_23_2,Reserved" bitfld.long 0x0 1. "SBR,SBR" "0,1" bitfld.long 0x0 0. "ER,ER" "0,1" group.long (0x28+0x2224)++0x3 line.long 0x0 "DCPORTSC,Register DCPORTSC" hexmask.long.byte 0x0 24.--31. 1. "RESERVED_31_24,Reserved" bitfld.long 0x0 23. "CEC,CEC" "0,1" bitfld.long 0x0 22. "PLC,PLC" "0,1" bitfld.long 0x0 21. "PRC,PRC" "0,1" newline rbitfld.long 0x0 18.--20. "RESERVED_20_18,Reserved" "0,1,2,3,4,5,6,7" bitfld.long 0x0 17. "CSC,CSC" "0,1" rbitfld.long 0x0 14.--16. "RESERVED_16_14,Reserved" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x0 10.--13. 1. "PORTSPEED,PORTSPEED" newline rbitfld.long 0x0 9. "RESERVED_9,Reserved" "0,1" hexmask.long.byte 0x0 5.--8. 1. "PLS,PLS" rbitfld.long 0x0 4. "PR,PR" "0,1" rbitfld.long 0x0 2.--3. "RESERVED_3_2,Reserved" "0,1,2,3" newline bitfld.long 0x0 1. "PED,PED" "0,1" rbitfld.long 0x0 0. "CCS,CCS" "0,1" group.long (0x30+0x2224)++0xF line.long 0x0 "DCCP_LO,DCCP_LO" hexmask.long 0x0 4.--31. 1. "DCCPR,DCCPR" hexmask.long.byte 0x0 0.--3. 1. "RESERVED_3_0,Reserved" line.long 0x4 "DCCP_HI,Register DCCP_HI" hexmask.long 0x4 0.--31. 1. "DCCPR,DCCPR" line.long 0x8 "DCDDI1,Register DCDDI1" hexmask.long.word 0x8 16.--31. 1. "VENDORID,VENDORID" hexmask.long.byte 0x8 8.--15. 1. "RESERVED_15_8,Reserved" hexmask.long.byte 0x8 0.--7. 1. "DBCPROTOCOL,DBCPROTOCOL" line.long 0xC "DCDDI2,Register DCDDI2" hexmask.long.word 0xC 16.--31. 1. "DEVICEREV,DEVICEREV" hexmask.long.word 0xC 0.--15. 1. "PRODUCTID,PRODUCTID" tree.end tree.end tree "USB2_NCR" base ad:0xF126D000 group.long 0x0++0x3 line.long 0x0 "INTEN,INTEN" bitfld.long 0x0 15. "INTEN_RSVD8,INTEN_RSVD8" "0,1" newline bitfld.long 0x0 14. "INTEN_RSVD7,INTEN_RSVD7" "0,1" bitfld.long 0x0 13. "INTEN_RSVD6,INTEN_RSVD6" "0,1" newline bitfld.long 0x0 12. "INTEN_RSVD5,INTEN_RSVD5" "0,1" bitfld.long 0x0 11. "INTEN_RSVD4,INTEN_RSVD4" "0,1" newline bitfld.long 0x0 10. "INTEN_RSVD3,INTEN_RSVD3" "0,1" bitfld.long 0x0 9. "INTEN_RSVD2,INTEN_RSVD2" "0,1" newline bitfld.long 0x0 8. "INTEN_RSVD1,INTEN_RSVD1" "0,1" bitfld.long 0x0 7. "INTEN_RSVD0,INTEN_RSVD0" "0,1" newline bitfld.long 0x0 6. "INTEN_WAKEUP,WAKEUP interrupt enalbe 1:enable 0:disable" "disable,enable" bitfld.long 0x0 5. "INTEN_HOST_LEGACY_SMI_INTERRUPT,HOST_LEGACY_SMI_INTERRUPT enable 1:enable 0:disable" "disable,enable" newline bitfld.long 0x0 4. "INTEN_PME_GENERATION,Power Management Event (PME) interrupt enable 1: enable 0:disable" "disable,enable" bitfld.long 0x0 3. "INTEN_BC_INTERRUPT,Battery Charger interrupt enable 1:enable 0:disable" "disable,enable" newline bitfld.long 0x0 2. "INTEN_CHGDET,Battery Charger Detect interrupt 1:enable 0:disable" "disable,enable" bitfld.long 0x0 1. "INTEN_HOST_SYSTEM_ERR,host_system_err interrupt enable. host_system_err can occur when the host controller encounters an 'Error' response in the AHB the AXI or the Native Master Bus. 1:enable 0:disable" "disable,enable" newline bitfld.long 0x0 0. "INTEN_CORE_INTERRUPT,USB CORE INTERRUPT enable 1:enable 0:disable" "disable,enable" group.long 0x10++0x7 line.long 0x0 "CTRL_0,CTRL_0" bitfld.long 0x0 29.--31. "DEBOUNCECTL,Enables Bus Filters for the following UTMI/ULPI signals and PIPE3PowerControl input signal from the PHY. utmiotg_vbusvalid utmisrp_bvalid pipe3_PowerPresent" "0,1,2,3,4,5,6,7" bitfld.long 0x0 28. "WAKEBYIDCHG,WAKEBYIDCHG" "0,1" newline bitfld.long 0x0 27. "WAKEBYVBUSCHG,WAKEBYVBUSCHG" "0,1" bitfld.long 0x0 26. "WAKEBYDPDMCHG,WAKEBYDPDMCHG" "0,1" newline bitfld.long 0x0 25. "WAKEBYREMOTEWAKE,WAKEBYREMOTEWAKE" "0,1" bitfld.long 0x0 24. "WAKEBYHSDSCNNT,WAKEBYHSDSCNNT" "0,1" newline bitfld.long 0x0 23. "WAKEBYHSCNNT,WAKEBYHSCNNT" "0,1" bitfld.long 0x0 22. "WAKEBYOC,WAKEBYOC" "0,1" newline bitfld.long 0x0 21. "XHC_BME,This signal is used to disable the bus mastering capability of the xHC. In a PCI system it comes from the Bus Master Enable (BME) bit of the Device Control Register in the PCI Configuration register space. 1'b0: Bus mastering capability is.." "Bus mastering capability is disabled,Bus mastering capability is enabled" hexmask.long.byte 0x0 17.--20. 1. "BUS_FILTER_BYPASS,Bus Filter Bypass. Disables the internal bus filters that are enabled by DWC_USB3_EN_BUS_FILTERS coreConsultant parameter. This static signal is present only when DWC_USB3_EN_BUS_FILTERS is 1. It is expected that this signal is set or.." newline hexmask.long.byte 0x0 11.--16. 1. "FLADJ_30MHZ_REG,HS Jitter Adjustment. Indicates the correction required to accommodate mac3 clock and utmi clock jitter to measure 125 's duration. With fladj_30mhz_reg tied to zero the high speed 125us micro-frame is counted for 123933ns. You must.." bitfld.long 0x0 10. "HOST_LEGACY_SMI_BAR_WR,PCI Base Address register (BAR) write: one clock pulse. The PCIe interface need to generate one clock pulse during PCIe Base Address register (BAR) write. Active State: High" "0,1" newline bitfld.long 0x0 9. "HOST_LEGACY_SMI_PCI_CMD_REG_WR,PCI command register write: one clock pulse. The PCIe interface needs to generate one clock pulse during PCIe command register write. Tie this low if you are not using Legacy support. Active State: High" "0,1" bitfld.long 0x0 8. "HOST_MSI_ENABLE,This enables the pulse type interrupt signal (one bus clock cycle) 'interrupt' port instead of level-sensitive interrupt. When interfacing to PCIe this allows you to easily map 'interrupt' to MSI in the PCIe controller. MSI can only be.." "0,1" newline bitfld.long 0x0 7. "HOST_PORT_POWER_CONTROL_PRESENT,This port defines the bit [3] of Capability Parameters (HCCPARAMS). Change the PPC value through the pin Port Power Control (PPC). This indicates whether the host controller implementation includes port power control..." "Indicates that the port does not have port power..,Indicates that the port has port power switches" bitfld.long 0x0 6. "DISRXDETU3RXDET,DisRxDetU3RxDet of USB 3.0 SS Ports This input signal requests the controller to stop issuing more PHY commands and release the PIPE ownership. The controller acknowledges this request by asserting the DisRxDetU3RxDet_ack signal. This.." "0,1" newline bitfld.long 0x0 5. "STARTRXDETU3RXDET,StartRxdetU3RxDet of USB 3.0 SS Ports This signal is the Start Receiver Detection in U3/Rx.Detect (StartRxdetU3RxDet). If DisRxDetU3RxDet is set and the link is in either U3 or Rx.Detect state the controller starts receiver detection.." "0,1" bitfld.long 0x0 4. "HOST_U3_PORT_DISABLE,USB 3.0 SS Port Disable control. 0: Port Enabled 1: Port Disabled This signal when '1' stops reporting connect/disconnect events the port and keeps the port in disabled state. This could be used for security reasons where.." "Port Enabled,Port Disabled" newline bitfld.long 0x0 3. "HOST_U2_PORT_DISABLE,USB 2.0 Port Disable control. 0: Port Enabled 1: Port Disabled When '1' this signal stops reporting connect/disconnect events the port and keeps the port in disabled state. This could be used for security reasons where.." "Port Enabled,Port Disabled When '1'" bitfld.long 0x0 1.--2. "HUB_PORT_PERM_ATTACH,Indicates if the device attached to a downstream port is permanently attached or not. 0: Not permanently attached 1: Permanently attached The lower bits are for USB 2.0 ports and the higher bits are for USB 3.0 SS ports:.." "Not permanently attached,Permanently attached,?,?" newline bitfld.long 0x0 0. "PME_EN,In host mode when hibernation is disabled (GCTL.GblHibernationEn=0) this input enables the controller to generate the pme_generation signal. unused in: Device mode Host mode when hibernation is enabled (GCTL.GblHibernationEn=1)" "0,1" line.long 0x4 "CTRL_1,CTRL_1" hexmask.long.word 0x4 22.--31. 1. "RSVD0,RSVD0" hexmask.long.byte 0x4 18.--21. 1. "RAM_DEBUG_SEL,ram_debug_sel: 0x0-0x7: internal RAM0 0x8-0xB:internal RAM1 0xC-0xF:internal RAM2" newline bitfld.long 0x4 16.--17. "CTRL_REF_SEL,ctrl_ref_clk select: 0 : i_ref_alt_clk_p 1 : i_ref_alt_clk_p 2: i_suspend_clk 3:i_ref_output_clk" "i_ref_alt_clk_p,i_ref_alt_clk_p,i_suspend_clk,i_ref_output_clk" hexmask.long.word 0x4 6.--15. 1. "DRVRSM32KCTRL1,DRVRSM32KCTRL1" newline hexmask.long.byte 0x4 1.--5. 1. "DRVRSM32KCTRL0,DRVRSM32KCTRL0" bitfld.long 0x4 0. "DRVRSM32KEN,DRVRSM32KEN" "0,1" repeat 6. (list 0x2 0x3 0x4 0x5 0x6 0x7 )(list 0x0 0x4 0x8 0xC 0x10 0x14 ) group.long ($2+0x18)++0x3 line.long 0x0 "CTRL_$1,CTRL_2" hexmask.long 0x0 0.--31. 1. "RSVD0,RSVD0" repeat.end group.long 0x80++0x3 line.long 0x0 "INTR,INTR" bitfld.long 0x0 15. "INTR_RSVD8,INTR_RSVD8" "0,1" newline bitfld.long 0x0 14. "INTR_RSVD7,INTR_RSVD7" "0,1" bitfld.long 0x0 13. "INTR_RSVD6,INTR_RSVD6" "0,1" newline bitfld.long 0x0 12. "INTR_RSVD5,INTR_RSVD5" "0,1" bitfld.long 0x0 11. "INTR_RSVD4,INTR_RSVD4" "0,1" newline bitfld.long 0x0 10. "INTR_RSVD3,INTR_RSVD3" "0,1" bitfld.long 0x0 9. "INTR_RSVD2,INTR_RSVD2" "0,1" newline bitfld.long 0x0 8. "INTR_RSVD1,INTR_RSVD1" "0,1" bitfld.long 0x0 7. "INTR_RSVD0,INTR_RSVD0" "0,1" newline bitfld.long 0x0 6. "INTR_WAKEUP,INTR_WAKEUP" "0,1" bitfld.long 0x0 5. "INTR_HOST_LEGACY_SMI_INTERRUPT,INTR_HOST_LEGACY_SMI_INTERRUPT" "0,1" newline bitfld.long 0x0 4. "INTR_PME_GENERATION,INTR_PME_GENERATION" "0,1" bitfld.long 0x0 3. "INTR_BC_INTERRUPT,INTR_BC_INTERRUPT" "0,1" newline bitfld.long 0x0 2. "INTR_CHGDET,INTR_CHGDET" "0,1" bitfld.long 0x0 1. "INTR_HOST_SYSTEM_ERR,INTR_HOST_SYSTEM_ERR" "0,1" newline bitfld.long 0x0 0. "INTR_CORE_INTERRUPT,INTR_CORE_INTERRUPT" "0,1" rgroup.long 0x90++0x7 line.long 0x0 "STS_0,STS_0" bitfld.long 0x0 1. "SUSPEND_CLK_ACTIVE,indicate the SUSPEND_CLK is ACTIVE or not 1: active 0:inactive" "inactive,active" newline bitfld.long 0x0 0. "ACLK_ACTIVE,indicate the bus clk is ACTIVE or not 1: active 0:inactive" "inactive,active" line.long 0x4 "STS_1,STS_1" bitfld.long 0x4 17. "DISRXDETU3RXDET_ACK,DisRxDetU3RxDet_ack of USB 3.0 SS Ports This signal is an acknowledgment of DisRxDetU3RxDet. When this signal is 1'b1 the controller releases the ownership of the the PIPE interface and does not issue PHY commands to the PIPE.." "0,1" newline bitfld.long 0x4 14.--16. "CLK_GATE_CTRL,Clock gating control This signal indicates the clock gating controls used for gating RAM and bus clocks. Bit[0] is gating control for bus_clk bit[1] and bit[2] is for ram_clk_in. This output must be used only for debug purposes." "0,1,2,3,4,5,6,7" bitfld.long 0x4 12.--13. "OPERATIONAL_MODE,Port Capability Direction 2'b01: for default Host operation (Power on value allowed only when DWC_USB3_MODE=1) 2'b10: for default Device operation (Power on value allowed only when DWC_USB3_MODE!=1)" "?,for default Host operation,for default Device operation,?" newline hexmask.long.word 0x4 0.--11. 1. "HOST_CURRENT_BELT,Current BELT Value. This signal indicates the minimum value of all received BELT values and the BELT that is set by the Set LTV command. This signal is valid only in Host mode." repeat 9. (list 0x2 0x3 0x4 0x5 0x7 0x8 0x9 0xA 0xB )(list 0x0 0x4 0x8 0xC 0x14 0x18 0x1C 0x20 0x24 ) rgroup.long ($2+0x98)++0x3 line.long 0x0 "STS_$1,STS_2" hexmask.long 0x0 0.--31. 1. "LOGIC_ANALYZER_TRACE_0,LOGIC_ANALYZER_TRACE_0" repeat.end rgroup.long 0xA8++0x3 line.long 0x0 "STS_6,STS_6" bitfld.long 0x0 0.--2. "DEBUG_2,DEBUG_2" "0,1,2,3,4,5,6,7" tree.end tree "USB_PHY2" base ad:0xF1280000 rgroup.word 0x0++0x1 line.word 0x0 "SUP_DIG_IDCODE_LO,Low 16 bits of IDCODE" newline hexmask.word 0x0 0.--15. 1. "DATA," rgroup.word 0x4++0x1 line.word 0x0 "SUP_DIG_IDCODE_HI,High 16 bits of IDCODE" newline hexmask.word 0x0 0.--15. 1. "DATA," group.word 0x8++0x1 line.word 0x0 "SUP_DIG_DEBUG,Debug controls" newline hexmask.word 0x0 7.--15. 1. "RESERVED_15_7,Reserved for Future use" newline bitfld.word 0x0 5.--6. "DTB_SEL,The lane DTB's are OR'd together with the support DTB signals selected with the below encodings 0 - none 1 - reset_ctl DTB output 2 - scope DTB output 3 - rtune DTB output" "none,reset_ctl DTB output,scope DTB output,rtune DTB output" newline hexmask.word.byte 0x0 0.--4. 1. "TX_VREF_SEL," group.word 0xC++0x1 line.word 0x0 "SUP_DIG_RTUNE_DEBUG,Resistor tuning debug controls" newline rbitfld.word 0x0 15. "RESERVED_15_15,Reserved for Future use" "0,1" newline hexmask.word 0x0 5.--14. 1. "VALUE,Value to use when triggering SET_VAL field only the 6 LSB's are used when setting rx or tx cal values (USER2 - read-write and custom)" newline bitfld.word 0x0 3.--4. "TYPE,Type of manual tuning or register read/write to execute 0 - ADC or read/write rt_value 1 - Rx tune or read/write rx_cal_val (only 6 bits) 2 - Tx tune or read/write tx_cal_val (only 6 bits) 3 - Resref detect (no affect when triggering SET_VAL.." "ADC,Rx tune,read-write and custom),Resref detect" newline bitfld.word 0x0 2. "SET_VAL,Set value Write to a 1 to manually write the register specified by the TYPE field to the value in the VALUE field (USER2 - read-write and custom)" "0,1" newline bitfld.word 0x0 1. "MAN_TUNE,Write to a 1 to do a manual tuning specified by TYPE field starting a manual tune while a tune is currently running can cause unpredictable results. For use only when you know the state of the rtune circuit. (USER2 - read-write and custom)" "0,1" newline bitfld.word 0x0 0. "FLIP_COMP,Invert analog comparator output (USER2 - read-write and custom)" "0,1" rgroup.word 0x10++0x1 line.word 0x0 "SUP_DIG_RTUNE_STAT,Resistor tuning register status" newline hexmask.word.byte 0x0 10.--15. 1. "RESERVED_15_10,Reserved for Future use" newline hexmask.word 0x0 0.--9. 1. "STAT,Current value of the register specifed by the TYPE field in the debug control register. Set the TYPE field in the DEBUG register and then do a read of this register. (RU - read-only volatile)" group.word 0x14++0x1 line.word 0x0 "SUP_DIG_SS_PHASE,Current MPLL phase selector value" newline bitfld.word 0x0 13.--15. "REF_SEL_DIV,Reference Divisor to get better resolution and lower PPM errors when synthesizing from a non-integer reference clock. NOTE: Default value is 4. One is added in hardware to give a range of 1 to 8. (volatile and 2 reads needed to read value)" "0,1,2,3,4,5,6,7" newline bitfld.word 0x0 12. "PH_SEL,Phase Mixer Clock select. 1: is pmix. 0 is VCO. (volatile and 2 reads needed to read value)" "?,is pmix" newline bitfld.word 0x0 11. "ZERO_FREQ,Zero frequency register. NOTES: Must be set for PHASE writes to stick (volatile and 2 reads needed to read value)" "0,1" newline hexmask.word 0x0 2.--10. 1. "VAL,Phase value from zero reference (volatile and 2 reads needed to read value)" newline bitfld.word 0x0 0.--1. "DTHR,Bits below the useful resolution (volatile and 2 reads needed to read value)" "0,1,2,3" group.word 0x18++0x1 line.word 0x0 "SUP_DIG_SS_FREQ,Frequency Control for Spread Spectrum" newline rbitfld.word 0x0 15. "RESERVED_15_15,Reserved for Future use" "0,1" newline bitfld.word 0x0 14. "FREQ_OVRD,Frequency Reigster Override. NOTE: Must be set for PHASE writes to stick (volatile and 2 reads needed to read value)" "0,1" newline hexmask.word.byte 0x0 7.--13. 1. "FREQ_PK,Peak Frequency Value (for changing direction) (volatile and 2 reads needed to read value)" newline hexmask.word.byte 0x0 0.--6. 1. "FREQ_CNT_INIT,Initial Frequency Counter Value (volatile and 2 reads needed to read value)" group.word 0x1C++0x1 line.word 0x0 "SUP_DIG_HSP_SS_PHASE,Current HSP_PMIX SSC phase sel value" newline hexmask.word.byte 0x0 11.--15. 1. "RESERVED_15_11,Reserved for Future use" newline hexmask.word.byte 0x0 4.--10. 1. "VAL,SSC phase value from zero reference (volatile and 2 reads needed to read value)" newline hexmask.word.byte 0x0 0.--3. 1. "DTHR,Bits below the useful resolution (volatile and 2 reads needed to read value)" group.word 0x20++0x1 line.word 0x0 "SUP_DIG_MPLL_CNT_CTL,Control for fixed or variable MPLL Count Selection" newline hexmask.word 0x0 1.--15. 1. "RESERVED_15_1,Reserved for Future use" newline bitfld.word 0x0 0. "VAR_CNT_EN,Selects variable count when enabled (Default = fixed count)" "0,1" group.word 0x24++0x1 line.word 0x0 "SUP_DIG_CR_PARA_ALU_CTL,Control for CR Parallel ALU access" newline hexmask.word 0x0 5.--15. 1. "RESERVED_15_5,Reserved for Future use" newline hexmask.word.byte 0x0 1.--4. 1. "CR_PARA_ALU_OPCODE,Opcode for the ALU when CR para access is enabled. Valid opcodes are as follows: 0 - Zero the accumulator 1 - Add control register read result to accumulator 2 - Add control register write data to accumulator 3 - Shift accumulator left.." newline bitfld.word 0x0 0. "CR_PARA_ALU_ACCESS_EN,Enable access to the ALU through the CR parallel bus." "0,1" rgroup.word 0x28++0x1 line.word 0x0 "SUP_DIG_CR_PARA_ALU_FLAGS,Flags from the ALU when CR para access is enabled." newline hexmask.word 0x0 4.--15. 1. "RESERVED_15_4,Reserved for Future use" newline hexmask.word.byte 0x0 0.--3. 1. "DATA,Flags from the ALU when CR para access is enabled. Valid ALU flags: 0 - Signedness used for next ADD_PHSEL command. (1=signed 0=unsigned) 1 - Signedness for ADD_PHSEL command has been chosen by a previous ADD_PHSEL command. 2 - Error detected.." group.word 0x40++0x1 line.word 0x0 "SUP_DIG_ATEOVRD,Override values for incoming controls from ASIC" newline hexmask.word 0x0 3.--15. 1. "RESERVED_15_3,Reserved for Future use" newline bitfld.word 0x0 2. "ATEOVRD_EN,Override enable for ATE signals. NOTE: This register is only accessible through cregs. Does not retain state during reset or ATPG. (USER2 - read-write and custom)" "0,1" newline bitfld.word 0x0 1. "REF_USB2_EN,Override value for USB HSP PHY ref_clk enable. (USER2 - read-write and custom)" "0,1" newline bitfld.word 0x0 0. "REF_CLKDIV2,Override value for SSP ref_clk pre-scaler. (USER2 - read-write and custom)" "0,1" group.word 0x44++0x1 line.word 0x0 "SUP_DIG_MPLL_OVRD_IN_LO,Override values for incoming RTUNE and MPLL controls from ASIC" newline bitfld.word 0x0 15. "RES_ACK_IN_OVRD,Override enable for res_ack_in" "0,1" newline bitfld.word 0x0 14. "RES_ACK_IN,Override value for res_ack_in" "0,1" newline bitfld.word 0x0 13. "RES_REQ_IN_OVRD,Override enable for res_req_in" "0,1" newline bitfld.word 0x0 12. "RES_REQ_IN,Override value for res_req_in" "0,1" newline bitfld.word 0x0 11. "RTUNE_REQ_OVRD,Override enable for rtune_req" "0,1" newline bitfld.word 0x0 10. "RTUNE_REQ,Override value for rtune_req" "0,1" newline bitfld.word 0x0 9. "MPLL_MULTIPLIER_OVRD,Override enable for mpll_multipler" "0,1" newline hexmask.word.byte 0x0 2.--8. 1. "MPLL_MULTIPLIER,Override value for mpll_multipler" newline bitfld.word 0x0 1. "MPLL_EN_OVRD,Override enable for mpll_en" "0,1" newline bitfld.word 0x0 0. "MPLL_EN,Override value for mpll_en" "0,1" group.word 0x48++0x1 line.word 0x0 "SUP_DIG_MPLL_OVRD_IN_HI,Override values for incoming VBOOST LVL and MPLL controls from ASIC" newline bitfld.word 0x0 13.--15. "TX_VBOOST_LVL,Override value for tx_vboost_lvl. Override enabled using LEVEL_EN from LEVEL_OVRD_IN register." "0,1,2,3,4,5,6,7" newline bitfld.word 0x0 12. "MPLL_REFSSC_CLK_EN_OVRD,Override enable for mpll_refssc_clk_en" "0,1" newline bitfld.word 0x0 11. "MPLL_REFSSC_CLK_EN,Override value for mpll_refssc_clk_en" "0,1" newline bitfld.word 0x0 10. "MPLL_RST,Reset the MPLL state machine Writing the register with this bit set will reset the MPLL power up/down FSM regardless of the current state of the register bit." "0,1" newline bitfld.word 0x0 9. "FSEL_OVRD,Override enable for fsel[2:0]" "0,1" newline bitfld.word 0x0 6.--8. "FSEL,Override value for fsel [2:0]" "0,1,2,3,4,5,6,7" newline bitfld.word 0x0 5. "MPLL_WORD_CLK_EN_OVRD,Override enable for mpll_word_clk_en" "0,1" newline bitfld.word 0x0 4. "MPLL_WORD_CLK_EN,Override value for mpll_word_clk_en" "0,1" newline bitfld.word 0x0 3. "MPLL_DWORD_CLK_EN_OVRD,Override enable for mpll_dword_clk_en" "0,1" newline bitfld.word 0x0 2. "MPLL_DWORD_CLK_EN,Override value for mpll_dword_clk_en" "0,1" newline bitfld.word 0x0 1. "MPLL_QWORD_CLK_EN_OVRD,Override enable for mpll_qword_clk_en" "0,1" newline bitfld.word 0x0 0. "MPLL_QWORD_CLK_EN,Override value for mpll_qword_clk_en" "0,1" group.word 0x4C++0x1 line.word 0x0 "SUP_DIG_SSC_OVRD_IN,Override values for incoming SSC controls from ASIC" newline rbitfld.word 0x0 14.--15. "RESERVED_15_14,Reserved for Future use" "0,1,2,3" newline bitfld.word 0x0 13. "SSC_OVRD_IN_EN,Override enable for Spread Spectrum generator." "0,1" newline bitfld.word 0x0 12. "SSC_EN,Override value for SSC enable." "0,1" newline bitfld.word 0x0 9.--11. "SSC_RANGE,Override value for SSC modulation range." "0,1,2,3,4,5,6,7" newline hexmask.word 0x0 0.--8. 1. "SSC_REF_CLK_SEL,Override value for reference clock scaling" group.word 0x50++0x1 line.word 0x0 "SUP_DIG_BS_OVRD_IN,Override values for incoming BS controls from ASIC" newline hexmask.word.byte 0x0 12.--15. 1. "RESERVED_15_12,Reserved for Future use" newline bitfld.word 0x0 11. "EN,Enable override values for all inputs controlled by this register" "0,1" newline bitfld.word 0x0 10. "INVERT,Override value for bs_invert" "0,1" newline bitfld.word 0x0 9. "INIT,Override value for bs_init" "0,1" newline bitfld.word 0x0 8. "HIGHZ,Override value for bs_highz" "0,1" newline bitfld.word 0x0 7. "CLAMP,Override value for bs_clamp" "0,1" newline bitfld.word 0x0 6. "EXTEST_AC,Override value for bs_extest_ac" "0,1" newline bitfld.word 0x0 5. "EXTEST,Override value for bs_extest" "0,1" newline bitfld.word 0x0 4. "PRELOAD,Override value for bs_preload" "0,1" newline bitfld.word 0x0 3. "UPDATE_DR,Override value for bs_update_dr" "0,1" newline bitfld.word 0x0 2. "CAPTURE_DR,Override value for bs_capture_dr" "0,1" newline bitfld.word 0x0 1. "SHIFT_DR,Override value for bs_shift_dr" "0,1" newline bitfld.word 0x0 0. "IN,Override value for bs_in" "0,1" group.word 0x54++0x1 line.word 0x0 "SUP_DIG_LEVEL_OVRD_IN,Override values for acjt_level and los_level" newline bitfld.word 0x0 13.--15. "LOS_BIAS,Override value for los_bias" "0,1,2,3,4,5,6,7" newline bitfld.word 0x0 12. "MPLL_HALF_RATE_OVRD,Enable override value for mpll_half_rate" "0,1" newline bitfld.word 0x0 11. "MPLL_HALF_RATE,Override value for mpll_half_rate" "0,1" newline bitfld.word 0x0 10. "LEVEL_EN,Enable override values for tx_vboost_lvl/los_bias/los_level/acjt_level inputs controlled by this and MPLL_OVRD_IN_HI registers" "0,1" newline hexmask.word.byte 0x0 5.--9. 1. "ACJT_LEVEL,Override value for acjt_level" newline hexmask.word.byte 0x0 0.--4. 1. "LOS_LEVEL,Override value for los_level" group.word 0x58++0x1 line.word 0x0 "SUP_DIG_SUP_OVRD_OUT,Override values for support block" newline hexmask.word.byte 0x0 10.--15. 1. "RESERVED_15_10,Reserved for Future use" newline bitfld.word 0x0 9. "MPLL_STATE_OVRD,Override enable for mpll_state output" "0,1" newline bitfld.word 0x0 8. "MPLL_STATE,Override value for mpll_state output" "0,1" newline bitfld.word 0x0 7. "BS_OUT_OVRD,Override enable for bs_out output" "0,1" newline bitfld.word 0x0 6. "BS_OUT,Override value for bs_out output" "0,1" newline bitfld.word 0x0 5. "RTUNE_ACK_OVRD,Override enable for rtune_ack output" "0,1" newline bitfld.word 0x0 4. "RTUNE_ACK,Override value for rtune_ack output" "0,1" newline bitfld.word 0x0 3. "RES_REQ_OUT_OVRD,Override enable for res_req_out output" "0,1" newline bitfld.word 0x0 2. "RES_REQ_OUT,Override value for res_req_out output" "0,1" newline bitfld.word 0x0 1. "RES_ACK_OUT_OVRD,Override enable for res_ack_out output" "0,1" newline bitfld.word 0x0 0. "RES_ACK_OUT,Override value for res_ack_out output" "0,1" rgroup.word 0x5C++0x1 line.word 0x0 "SUP_DIG_MPLL_ASIC_IN,Current values for incoming MPLL controls from ASIC" newline bitfld.word 0x0 15. "RESERVED_15_15,Reserved for Future use" "0,1" newline bitfld.word 0x0 14. "MPLL_REFSSC_CLK_EN,Value from ASIC for mpll_refssc_clk_en (RU - read-only volatile)" "0,1" newline bitfld.word 0x0 13. "MPLL_WORD_CLK_EN,Value from ASIC for mpll_word_clk_en (RU - read-only volatile)" "0,1" newline bitfld.word 0x0 12. "MPLL_DWORD_CLK_EN,Value from ASIC for mpll_dword_clk_en (RU - read-only volatile)" "0,1" newline bitfld.word 0x0 11. "MPLL_QWORD_CLK_EN,Value from ASIC for mpll_qword_clk_en (RU - read-only volatile)" "0,1" newline bitfld.word 0x0 10. "RES_ACK_IN,Value from ASIC for res_ack_in (RU - read-only volatile)" "0,1" newline bitfld.word 0x0 9. "RES_REQ_IN,Value from ASIC for res_req_in (RU - read-only volatile)" "0,1" newline bitfld.word 0x0 8. "RTUNE_REQ,Value from ASIC for rtune_req (RU - read-only volatile)" "0,1" newline hexmask.word.byte 0x0 1.--7. 1. "MPLL_MULTIPLIER,Value from ASIC for mpll_multiplier (RU - read-only volatile)" newline bitfld.word 0x0 0. "MPLL_EN,Value from ASIC for mpll_en (RU - read-only volatile)" "0,1" rgroup.word 0x60++0x1 line.word 0x0 "SUP_DIG_BS_ASIC_IN,Current values for incoming boundary scan controls from ASIC" newline bitfld.word 0x0 14.--15. "RESERVED_15_14,Reserved for Future use" "0,1,2,3" newline bitfld.word 0x0 11.--13. "TX_VBOOST_LVL,Value from ASIC for tx_vboost_lvl -- Not as bs_* signal but we're out of bits. (RU - read-only volatile)" "0,1,2,3,4,5,6,7" newline bitfld.word 0x0 10. "INVERT,Value from ASIC for bs_invert (RU - read-only volatile)" "0,1" newline bitfld.word 0x0 9. "INIT,Value from ASIC for bs_init (RU - read-only volatile)" "0,1" newline bitfld.word 0x0 8. "HIGHZ,Value from ASIC for bs_highz (RU - read-only volatile)" "0,1" newline bitfld.word 0x0 7. "CLAMP,Value from ASIC for bs_clamp (RU - read-only volatile)" "0,1" newline bitfld.word 0x0 6. "EXTEST_AC,Value from ASIC for bs_extest_ac (RU - read-only volatile)" "0,1" newline bitfld.word 0x0 5. "EXTEST,Value from ASIC for bs_extest (RU - read-only volatile)" "0,1" newline bitfld.word 0x0 4. "PRELOAD,Value from ASIC for bs_preload (RU - read-only volatile)" "0,1" newline bitfld.word 0x0 3. "UPDATE_DR,Value from ASIC for bs_update_dr (RU - read-only volatile)" "0,1" newline bitfld.word 0x0 2. "CAPTURE_DR,Value from ASIC for bs_capture_dr (RU - read-only volatile)" "0,1" newline bitfld.word 0x0 1. "SHIFT_DR,Value from ASIC for bs_shift_dr (RU - read-only volatile)" "0,1" newline bitfld.word 0x0 0. "IN,Value from ASIC for bs_in (RU - read-only volatile)" "0,1" rgroup.word 0x64++0x1 line.word 0x0 "SUP_DIG_LEVEL_ASIC_IN,Current values for incoming los/acjt level. MPLL half rate mode and vreg bypass from ASIC" newline bitfld.word 0x0 15. "RESERVED_15_15,Reserved for Future use" "0,1" newline bitfld.word 0x0 12.--14. "LOS_BIAS,Value from ASIC for los_bias (RU - read-only volatile)" "0,1,2,3,4,5,6,7" newline bitfld.word 0x0 11. "MPLL_HALF_RATE,Value from ASIC for mpll_half_rate (RU - read-only volatile)" "0,1" newline bitfld.word 0x0 10. "VREG_BYPASS,Value from ASIC for vreg_bypass (RU - read-only volatile)" "0,1" newline hexmask.word.byte 0x0 5.--9. 1. "ACJT_LEVEL,Value from ASIC for acjt_level (RU - read-only volatile)" newline hexmask.word.byte 0x0 0.--4. 1. "LOS_LEVEL,Value from ASIC for los_level (RU - read-only volatile)" rgroup.word 0x68++0x1 line.word 0x0 "SUP_DIG_SSC_ASIC_IN,Current values for incoming SSC controls from ASIC" newline bitfld.word 0x0 15. "SS_EN,Value from ASIC for ssc_en (RU - read-only volatile)" "0,1" newline bitfld.word 0x0 12.--14. "SSC_RANGE,Value from ASIC for ssc_range (RU - read-only volatile)" "0,1,2,3,4,5,6,7" newline hexmask.word 0x0 3.--11. 1. "SSC_REF_CLK_SEL,Value from ASIC for ssc_ref_clk_sel (RU - read-only volatile)" newline bitfld.word 0x0 0.--2. "FSEL,Value from ASIC for fsel (RU - read-only volatile)" "0,1,2,3,4,5,6,7" rgroup.word 0x6C++0x1 line.word 0x0 "SUP_DIG_SUP_ASIC_OUT,Current values for outgoing support block controls to ASIC" newline hexmask.word 0x0 5.--15. 1. "RESERVED_15_5,Reserved for Future use" newline bitfld.word 0x0 4. "MPLL_STATE,Value from PHY for mpll_state output (RU - read-only volatile)" "0,1" newline bitfld.word 0x0 3. "BS_OUT,Value from PHY for bs_out output (RU - read-only volatile)" "0,1" newline bitfld.word 0x0 2. "RTUNE_ACK,Value from PHY for rtune_ack output (RU - read-only volatile)" "0,1" newline bitfld.word 0x0 1. "RES_REQ_OUT,Value from PHY for res_req_out output (RU - read-only volatile)" "0,1" newline bitfld.word 0x0 0. "RES_ACK_OUT,Value from PHY for res_ack_out output (RU - read-only volatile)" "0,1" rgroup.word 0x70++0x1 line.word 0x0 "SUP_DIG_ATEOVRD_STATUS,USB3_SUP_DIG_ATEOVRD_STATUS" newline hexmask.word.byte 0x0 10.--15. 1. "RESERVED_15_10,Reserved for Future use" newline bitfld.word 0x0 8.--9. "DTB_OUT,Value from dtb_out bus. (RU - read-only volatile)" "0,1,2,3" newline bitfld.word 0x0 7. "REF_SSP_EN,Value from ASIC for ref_ssp_en. (RU - read-only volatile)" "0,1" newline bitfld.word 0x0 6. "REF_USE_PAD,Value from ASIC for ref_use_pad. (RU - read-only volatile)" "0,1" newline bitfld.word 0x0 5. "PHY_RESET_IN,Value from ASIC for phy_reset (RU - read-only volatile)" "0,1" newline bitfld.word 0x0 4. "REF_CLKDIV2_IN,Value from ASIC for ref_clkdiv2 (RU - read-only volatile)" "0,1" newline bitfld.word 0x0 3. "REF_USB2_EN_IN,Value from ASIC for ref_usb2_en (RU - read-only volatile)" "0,1" newline bitfld.word 0x0 2. "ATEOVRD_EN,When set values from ATEOVRD register are being sent to PHY (RU - read-only volatile)" "0,1" newline bitfld.word 0x0 1. "REF_CLKDIV2_OUT,Value from ATEOVRD for ref_clkdiv2 (RU - read-only volatile)" "0,1" newline bitfld.word 0x0 0. "REF_USB2_EN_OUT,Value from ATEOVRD for ref_usb2_en (RU - read-only volatile)" "0,1" group.word 0x74++0x1 line.word 0x0 "SUP_DIG_HSP_OVRD_IN,Override values for HSP" newline hexmask.word 0x0 4.--15. 1. "RESERVED_15_4,Reserved for Future use" newline bitfld.word 0x0 3. "HSP_PLL_OVRD,Override enable for HSP pll_pu signal" "0,1" newline bitfld.word 0x0 2. "HSP_PLL_PU,Override value for HSP pll_pu signal" "0,1" newline bitfld.word 0x0 1. "HSP_BIAS_OVRD,Override enable for HSP bias_pu signal" "0,1" newline bitfld.word 0x0 0. "HSP_BIAS_PU,Override value for HSP bias_pu signal" "0,1" rgroup.word 0x78++0x1 line.word 0x0 "SUP_DIG_HSP_ASIC_IN,Current values for incoming HSP & REF XO controls from ASIC" newline hexmask.word 0x0 4.--15. 1. "RESERVED_15_4,Reserved for Future use" newline bitfld.word 0x0 3. "REF_USE_XO,Value from ASIC for ref_use_xo (RU - read-only volatile)" "0,1" newline bitfld.word 0x0 2. "REF_XO_EN,Value from ASIC for ref_xo_en (RU - read-only volatile)" "0,1" newline bitfld.word 0x0 1. "HSP_PLL_PU,Value from ASIC for hsp_pll_pu (RU - read-only volatile)" "0,1" newline bitfld.word 0x0 0. "HSP_BIAS_PU,Value from ASIC for hsp_bias_pu (RU - read-only volatile)" "0,1" group.word 0x80++0x1 line.word 0x0 "SUP_DIG_SCOPE_ENABLES,Scope Counter configuration" newline hexmask.word 0x0 5.--15. 1. "RESERVED_15_5,Reserved for Future use" newline bitfld.word 0x0 3.--4. "LANE_SELECT,Scope Counter Input select" "0,1,2,3" newline bitfld.word 0x0 2. "MASK_SATURATION_MODE,Method of mask saturation. When 1 Saturate when the first mask_counter reaches sample_limit. When 0 Saturate when all mask_counters have reached sample_limit." "0,1" newline bitfld.word 0x0 1. "MASK_EN,Enable scope_mask input for tracking count values. Clears registers when deasserted." "0,1" newline bitfld.word 0x0 0. "XOR_EN,Use scope_xor input for count values." "0,1" group.word 0x84++0x1 line.word 0x0 "SUP_DIG_SCOPE_SAMPLES,Number of samples to count" newline hexmask.word 0x0 0.--15. 1. "SAMPLES,Number of Sample to count." rgroup.word 0x88++0x1 line.word 0x0 "SUP_DIG_SCOPE_COUNT,Results of scope counting" newline hexmask.word 0x0 0.--15. 1. "COUNT,A write to this register will start the counting process The value of FFFF indicates counting still in progress. Asserting MASK_EN will also start the counting if in MASK mode. (RU - read-only volatile)" group.word 0x8C++0x1 line.word 0x0 "SUP_DIG_SCOPE_CTL,Masked scope counting Start and Status" newline hexmask.word 0x0 2.--15. 1. "RESERVED_15_2,Reserved for Future use" newline bitfld.word 0x0 1. "MASK_START,A write to this register will start the counting process The value of FFFF indicates counting still in progress Write will trigger mask counting. (USER1 - read-write volatile)" "?,read-write volatile)" newline bitfld.word 0x0 0. "MASK_SATURATION,When assert mask registers have saturated. (USER1 - read-write volatile)" "?,read-write volatile)" repeat 8. (list 0x0 0x1 0xA 0xB 0x64 0x65 0x6E 0x6F )(list 0x0 0x4 0x8 0xC 0x10 0x14 0x18 0x1C ) group.word ($2+0x90)++0x1 line.word 0x0 "SUP_DIG_SCOPE_MASK_$1,Current count value for mask_000" newline hexmask.word 0x0 0.--15. 1. "MASK_VAL_000,Starting count value of mask register. (volatile and 2 reads needed to read value)" repeat.end group.word 0xC0++0x1 line.word 0x0 "SUP_ANA_MPLL_LOOP_CTL,MPLL loop control bits" newline hexmask.word.byte 0x0 8.--15. 1. "RESERVED_15_8,Reserved for Future use" newline hexmask.word.byte 0x0 4.--7. 1. "PROP_CNTRL,Charge pump proportional current setting" newline bitfld.word 0x0 2.--3. "INT_CNTRL,Charge pump integrating current setting" "0,1,2,3" newline bitfld.word 0x0 1. "GD,Measure MPLL local GD" "0,1" newline bitfld.word 0x0 0. "VMB,Measure MPLL Master Bias Voltage" "0,1" repeat 2. (list 0x1 0x2 )(list 0x0 0x4 ) group.word ($2+0xC4)++0x1 line.word 0x0 "SUP_ANA_MPLL_ATB_MEAS$1,ATB Select bits" newline hexmask.word.byte 0x0 8.--15. 1. "RESERVED_15_8,Reserved for Future use" newline bitfld.word 0x0 7. "VPSF,puts vpsf on atb_s_p" "0,1" newline bitfld.word 0x0 6. "VREF,puts vref from charge pump on atb_s_p" "0,1" newline bitfld.word 0x0 5. "VCNTRL,puts vcntrl on atb_s_m" "0,1" newline bitfld.word 0x0 4. "GD,puts gd on atb_s_m" "0,1" newline bitfld.word 0x0 3. "IVCO,puts VCO current/93 on atb_f_m" "0,1" newline bitfld.word 0x0 2. "VP,puts vpa on atb_s_m" "0,1" newline bitfld.word 0x0 1. "VP_CP,puts vp_cp on atb_s_p" "0,1" newline bitfld.word 0x0 0. "VREG_MPLL,puts vreg_mpll on atb_s_p" "0,1" repeat.end group.word 0xCC++0x1 line.word 0x0 "SUP_ANA_MPLL_OVRD,Local overrides" newline hexmask.word.byte 0x0 8.--15. 1. "RESERVED_15_8,Reserved for Future use" newline bitfld.word 0x0 7. "PWRON_LCL,local power_on value" "0,1" newline bitfld.word 0x0 6. "EN_PWRON_LCL,Enable local control of power_on" "0,1" newline bitfld.word 0x0 5. "GS_LCL,local gear_shift value" "0,1" newline bitfld.word 0x0 4. "EN_GS_LCL,Enable local control of gear_shift" "0,1" newline bitfld.word 0x0 3. "RST_LCL,local reset value" "0,1" newline bitfld.word 0x0 2. "EN_RST_LCL,enable local control of reset" "0,1" newline bitfld.word 0x0 1. "PMIX_CLK_SEL_LCL,local pmix_clk_sel value" "0,1" newline bitfld.word 0x0 0. "EN_PMIX_CLK_SEL_LCL,enable local control of pmix_clk_sel" "0,1" group.word 0xD0++0x1 line.word 0x0 "SUP_ANA_RTUNE_RTUNE_CTRL,RTUNE control bits" newline hexmask.word.byte 0x0 8.--15. 1. "RESERVED_15_8,Reserved for Future use" newline bitfld.word 0x0 7. "RT_PWRON_FRC_ON,When set forces RTUNE block to be on" "0,1" newline bitfld.word 0x0 6. "X4_FRC_OFF,When set do not multiply test current by 4" "0,1" newline bitfld.word 0x0 4.--5. "RT_DAC_MODE,Margin DAC mode control bits(00=powerdown 01=DAC drives atb_s_p/m directly 10=DAC drives atb_s_p/m to the RX in margining mode 11=illegal state)" "powerdown,DAC drives atb_s_p/m directly,?,?" newline bitfld.word 0x0 3. "RT_DAC_CHOP,Margin DAC chop control bit. ref to ssp analog engineering doc 8.5" "0,1" newline bitfld.word 0x0 2. "RT_ATB,RTUNE ATB mode control bit (1=RTUNE performs ADC on ATB input 0=not accessing ATB. refer to ssp analog engineering specification 8.1.4)" "not accessing ATB,RTUNE performs ADC on ATB input" newline bitfld.word 0x0 1. "RT_SEL_ATBP,RTUNE ATB sense input select bit (1=atb_s_p 0=atb_s_m)" "atb_s_m),atb_s_p" newline bitfld.word 0x0 0. "RT_SEL_ATBF,RTUNE ATB input select bit (1=atb_fm 0=atb_s_p/m)" "atb_s_p/m),atb_fm" group.word 0xD4++0x1 line.word 0x0 "SUP_ANA_ATB_SWITCHYARD_CTRL,ATB_SWITCHYARD control bits" newline hexmask.word.byte 0x0 8.--15. 1. "RESERVED_15_8,Reserved for Future use" newline bitfld.word 0x0 7. "ASM_GD,Connect gd to atb_s_m" "0,1" newline bitfld.word 0x0 6. "ASP_VP,Connect vp to atb_s_p" "0,1" newline bitfld.word 0x0 5. "ASP_VBG,Connect vbg to atb_s_p" "0,1" newline bitfld.word 0x0 4. "ASP_VPHREG,Connect vphreg to atb_s_m" "0,1" newline bitfld.word 0x0 3. "ATEST_AFM,drive ATEST from atb_f_m" "0,1" newline bitfld.word 0x0 2. "ATEST_AFP,drive ATEST from atb_f_p" "0,1" newline bitfld.word 0x0 1. "ATEST_ASM,Connet ATEST to atb_s_m" "0,1" newline bitfld.word 0x0 0. "ATEST_ASP,Connect ATEST to atb_s_p" "0,1" group.word 0xD8++0x1 line.word 0x0 "SUP_ANA_SSC_CLK_CNTRL,controls sscf reference clock rate" newline hexmask.word.byte 0x0 8.--15. 1. "RESERVED_15_8,Reserved for Future use" newline bitfld.word 0x0 7. "NC,Reserved" "0,1" newline hexmask.word.byte 0x0 0.--6. 1. "SSC_CLK_DIV125,set ssc reference clock to be 20MHz" group.word 0xDC++0x1 line.word 0x0 "SUP_ANA_HSP_CLK_DIG_CNTRL0,controls HSP phase clock. and resolution" newline hexmask.word.byte 0x0 8.--15. 1. "RESERVED_15_8,Reserved for Future use" newline bitfld.word 0x0 7. "NUM_OVERRIDE,Set the value to 1 to enable using values from creg bit 6 downto 0" "0,1" newline bitfld.word 0x0 4.--6. "GATE_PMIX_BITS,Set gate_pmix_bits to gate the corresponding MSB of the 7-bit PMIX phase select bits" "?,?,?,?,?,?,?,bit PMIX phase select bits" newline bitfld.word 0x0 3. "HALF_CLK_EN,Set to 1 for 1.25GHz updates to HSP PMIX. Set to 0 for 2.5GHz updates to PMIX." "0,1" newline bitfld.word 0x0 2. "UCLK_EN_N,Set to 1 to disable update clock. Set to 0 to enable update clock. When clock is enabled phase updates are allowed." "0,1" newline bitfld.word 0x0 1. "EN_HSPPMIX_VPMIX,Set to 1 to connect the regulated HSP PMIX supply to the atb_s_p bus" "0,1" newline bitfld.word 0x0 0. "EN_HSPPMIX_FRC_VPMIX,Set to 1 to force override of HSP PMIX regulator voltage to voltage on atb_s_m" "0,1" group.word 0xE0++0x1 line.word 0x0 "SUP_ANA_HSP_CLK_DIG_CNTRL1,Lower and Upper Phase Increment Values" newline hexmask.word.byte 0x0 8.--15. 1. "RESERVED_15_8,Reserved for Future use" newline hexmask.word.byte 0x0 4.--7. 1. "UPPER_INT,These bits are only used when num_override is set to 1. Upper integer for phase increments of 2.5 to 2.4 GHz conversion. This is the phase increment that is applied 6 times in every 25 for 1.25 GHz increments and 3 times in every 25 for 2.5GHz" newline hexmask.word.byte 0x0 0.--3. 1. "LOWER_INT,These bits are only used when num_override is set to 1. Lower integer for phase increments of 2.5 to 2.4 GHz conversion. This phase increment is applied 19 times in every 25 for 1.25 GHz increments and 22 times in every 25 for 2.5GHz." group.word 0x1000++0x1 line.word 0x0 "LANE0_DIG_TX_OVRD_IN_LO,Override values for incoming TX controls from ASIC" newline bitfld.word 0x0 15. "LANE_IF_WIDTH_OVRD,Override enable for lane interface width" "0,1" newline bitfld.word 0x0 14. "LANE_IF_WIDTH,Override value for lane interface width" "0,1" newline bitfld.word 0x0 13. "TX_DETECT_RX_REQ_OVRD,Override enable for tx_detect_rx_req" "0,1" newline bitfld.word 0x0 12. "TX_DETECT_RX_REQ,Override value for tx_detect_rx_req" "0,1" newline bitfld.word 0x0 11. "TX_BEACON_EN_OVRD,Override enable for tx_beacon_en" "0,1" newline bitfld.word 0x0 10. "TX_BEACON_EN,Override value for tx_beacon_en" "0,1" newline bitfld.word 0x0 9. "TX_CM_EN_OVRD,Override enable for tx_cm_en" "0,1" newline bitfld.word 0x0 8. "TX_CM_EN,Override value for tx_cm_en" "0,1" newline bitfld.word 0x0 7. "TX_EN_OVRD,Override enable for tx_en" "0,1" newline bitfld.word 0x0 6. "TX_EN,Override value for tx_en" "0,1" newline bitfld.word 0x0 5. "TX_DATA_EN_OVRD,Override enable for tx_data_en" "0,1" newline bitfld.word 0x0 4. "TX_DATA_EN,Override value for tx_data_en" "0,1" newline bitfld.word 0x0 3. "TX_INVERT_OVRD,Override enable for tx_invert" "0,1" newline bitfld.word 0x0 2. "TX_INVERT,Override value for tx_invert" "0,1" newline bitfld.word 0x0 1. "TX_LOOPBK_EN_OVRD,Override enable for loopbk_en" "0,1" newline bitfld.word 0x0 0. "LOOPBK_EN,Override value for loopbk_en" "0,1" group.word 0x1004++0x1 line.word 0x0 "LANE0_DIG_TX_OVRD_IN_HI,Override values for incoming TX controls from ASIC" newline hexmask.word.byte 0x0 10.--15. 1. "RESERVED_15_10,Reserved for Future use" newline bitfld.word 0x0 9. "TX_VBOOST_EN_OVRD,Override enable for tx_vboost_en" "0,1" newline bitfld.word 0x0 8. "TX_VBOOST_EN,Override value for tx_vboost_en" "0,1" newline bitfld.word 0x0 7. "TX_RESET_OVRD,Override enable for tx_reset" "0,1" newline bitfld.word 0x0 6. "TX_RESET,Override value for tx_reset" "0,1" newline bitfld.word 0x0 5. "TX_NYQUIST_DATA,Override incoming data to nyquist" "0,1" newline bitfld.word 0x0 4. "TX_CLK_OUT_EN_OVRD,Override enable for tx_clk_out_en." "0,1" newline bitfld.word 0x0 3. "TX_CLK_OUT_EN,Override incomming tx_clk_out_en." "0,1" newline bitfld.word 0x0 2. "TX_RATE_OVRD,Override enable for tx_rate." "0,1" newline bitfld.word 0x0 0.--1. "TX_RATE,Override incomming tx lane rate." "0,1,2,3" group.word 0x1008++0x1 line.word 0x0 "LANE0_DIG_TX_OVRD_DRV_LO,Override values for incoming TX drive controls from ASIC" newline rbitfld.word 0x0 15. "RESERVED_15_15,Reserved for Future use" "0,1" newline bitfld.word 0x0 14. "EN,Enable override values for all inputs controlled by this register" "0,1" newline hexmask.word.byte 0x0 7.--13. 1. "PREEMPH,Override value for transmit preemphasis." newline hexmask.word.byte 0x0 0.--6. 1. "AMPLITUDE,Override value for transmit amplitude." group.word 0x100C++0x1 line.word 0x0 "LANE0_DIG_TX_OVRD_DRV_HI,Override values for incoming TX drive controls from ASIC" newline hexmask.word 0x0 6.--15. 1. "RESERVED_15_6,Reserved for Future use" newline bitfld.word 0x0 5. "EN,Enable override values for all inputs controlled by this register" "0,1" newline hexmask.word.byte 0x0 0.--4. 1. "TERM_OFFSET,Override value for tx_term_offset (tx_ana_vcmref_boost)" group.word 0x1010++0x1 line.word 0x0 "LANE0_DIG_TX_OVRD_OUT,Override values for outgoing TX controls to ASIC" newline hexmask.word.byte 0x0 8.--15. 1. "RESERVED_15_8,Reserved for Future use" newline bitfld.word 0x0 7. "TX_STATE_OVRD,Override enable for tx_state" "0,1" newline bitfld.word 0x0 6. "TX_STATE,Override value for tx_state" "0,1" newline bitfld.word 0x0 5. "TX_CM_STATE_OVRD,Override enable for tx_cm_state" "0,1" newline bitfld.word 0x0 4. "TX_CM_STATE,Override value for tx_cm_state" "0,1" newline bitfld.word 0x0 3. "TX_DETECT_RX_ACK_OVRD,Override enable for tx_detect_rx_ack" "0,1" newline bitfld.word 0x0 2. "TX_DETECT_RX_ACK,Override value for tx_detect_rx_ack" "0,1" newline bitfld.word 0x0 1. "DETECT_RX_RES_OVRD,Override enable for tx_detect_rx_res" "0,1" newline bitfld.word 0x0 0. "DETECT_RX_RES,Override value for tx_detect_rx_res" "0,1" group.word 0x1014++0x1 line.word 0x0 "LANE0_DIG_RX_OVRD_IN_LO,Override values for incoming RX controls from ASIC" newline rbitfld.word 0x0 14.--15. "RESERVED_15_14,Reserved for Future use" "0,1,2,3" newline bitfld.word 0x0 13. "RX_LOS_EN_OVRD,Override enable for rx_los_en" "0,1" newline bitfld.word 0x0 12. "RX_LOS_EN,Override value for rx_los_en" "0,1" newline bitfld.word 0x0 11. "RX_TERM_EN_OVRD,Override enable for rx_term_en" "0,1" newline bitfld.word 0x0 10. "RX_TERM_EN,Override value for rx_term_en" "0,1" newline bitfld.word 0x0 9. "RX_BIT_SHIFT_OVRD,Override enable for rx_bit_shift" "0,1" newline bitfld.word 0x0 8. "RX_BIT_SHIFT,Override value for rx_bit_shift" "0,1" newline bitfld.word 0x0 7. "RX_ALIGN_EN_OVRD,Override enable for rx_align_en" "0,1" newline bitfld.word 0x0 6. "RX_ALIGN_EN,Override value for rx_align_en" "0,1" newline bitfld.word 0x0 5. "RX_DATA_EN_OVRD,Override enable for rx_data_en" "0,1" newline bitfld.word 0x0 4. "RX_DATA_EN,Override value for rx_data_en" "0,1" newline bitfld.word 0x0 3. "RX_PLL_EN_OVRD,Override enable for rx_pll_en" "0,1" newline bitfld.word 0x0 2. "RX_PLL_EN,Override value for rx_pll_en" "0,1" newline bitfld.word 0x0 1. "RX_INVERT_OVRD,Override enable for rx_invert" "0,1" newline bitfld.word 0x0 0. "RX_INVERT,Override value for rx_invert" "0,1" group.word 0x1018++0x1 line.word 0x0 "LANE0_DIG_RX_OVRD_IN_HI,Override values for incoming RX controls from ASIC" newline rbitfld.word 0x0 14.--15. "RESERVED_15_14,Reserved for Future use" "0,1,2,3" newline bitfld.word 0x0 13. "RX_RESET_OVRD,Override enable for rx_reset" "0,1" newline bitfld.word 0x0 12. "RX_RESET,Override value for rx_reset" "0,1" newline bitfld.word 0x0 11. "RX_EQ_OVRD,Override enable for rx_eq" "0,1" newline bitfld.word 0x0 8.--10. "RX_EQ,Override value for rx_eq" "0,1,2,3,4,5,6,7" newline bitfld.word 0x0 7. "RX_EQ_EN_OVRD,Override enable for rx_eq_en" "0,1" newline bitfld.word 0x0 6. "RX_EQ_EN,Override value for rx_eq_en" "0,1" newline bitfld.word 0x0 5. "RX_LOS_FILTER_OVRD,Override enable for rx_los_filter" "0,1" newline bitfld.word 0x0 3.--4. "RX_LOS_FILTER,Override value for rx_los_filter" "0,1,2,3" newline bitfld.word 0x0 2. "RX_RATE_OVRD,Override enable for rx_rate" "0,1" newline bitfld.word 0x0 0.--1. "RX_RATE,Override value for rx_rate" "0,1,2,3" group.word 0x101C++0x1 line.word 0x0 "LANE0_DIG_RX_OVRD_OUT,Override values for outgoing RX controls to ASIC" newline hexmask.word 0x0 7.--15. 1. "RESERVED_15_7,Reserved for Future use" newline bitfld.word 0x0 6. "ZERO_DATA,Override data output to all zeros" "0,1" newline bitfld.word 0x0 5. "LOS_OVRD,Override value for rx_los" "0,1" newline bitfld.word 0x0 4. "LOS,Override value for rx_los" "0,1" newline bitfld.word 0x0 3. "PLL_STATE_OVRD,Override enable for rx_pll_state" "0,1" newline bitfld.word 0x0 2. "PLL_STATE,Override value for rx_pll_state" "0,1" newline bitfld.word 0x0 1. "VALID_OVRD,Override enable for rx_valid" "0,1" newline bitfld.word 0x0 0. "VALID,Override value for rx_valid" "0,1" rgroup.word 0x1020++0x1 line.word 0x0 "LANE0_DIG_TX_ASIC_IN,Current values for incoming TX controls from ASIC" newline bitfld.word 0x0 14.--15. "RESERVED_15_14,Reserved for Future use" "0,1,2,3" newline bitfld.word 0x0 13. "LANE_IF_WIDTH,Value from ASIC for lane_if_width (RU - read-only volatile)" "0,1" newline bitfld.word 0x0 12. "DATA_EN_S,Value from ASIC for tx_data_en_s (RU - read-only volatile)" "0,1" newline bitfld.word 0x0 11. "TX_VBOOST_EN,Value from ASIC for tx_vboost_en (RU - read-only volatile)" "0,1" newline bitfld.word 0x0 10. "TX_CLK_OUT_EN,Value from ASIC for tx_clk_out_en (RU - read-only volatile)" "0,1" newline bitfld.word 0x0 9. "DETECT_RX_REQ,Value from ASIC for tx_detect_rx_req (RU - read-only volatile)" "0,1" newline bitfld.word 0x0 8. "BEACON_EN,Value from ASIC for tx_beacon_en (RU - read-only volatile)" "0,1" newline bitfld.word 0x0 7. "CM_EN,Value from ASIC for tx_cm_en (RU - read-only volatile)" "0,1" newline bitfld.word 0x0 6. "TX_EN,Value from ASIC for tx_en (RU - read-only volatile)" "0,1" newline bitfld.word 0x0 5. "DATA_EN,Value from ASIC for tx_data_en (RU - read-only volatile)" "0,1" newline bitfld.word 0x0 4. "TX_RESET,Value from ASIC for tx_reset (RU - read-only volatile)" "0,1" newline bitfld.word 0x0 3. "INVERT,Value from ASIC for tx_invert (RU - read-only volatile)" "0,1" newline bitfld.word 0x0 2. "LOOPBK_EN,Value from ASIC for loopbk_en (RU - read-only volatile)" "0,1" newline bitfld.word 0x0 0.--1. "TX_RATE,Value from ASIC for tx_rate (RU - read-only volatile)" "0,1,2,3" rgroup.word 0x1024++0x1 line.word 0x0 "LANE0_DIG_TX_ASIC_DRV_LO,Current values for incoming TX level controls from ASIC" newline bitfld.word 0x0 14.--15. "RESERVED_15_14,Reserved for Future use" "0,1,2,3" newline hexmask.word.byte 0x0 7.--13. 1. "PREEMPH,Value from ASIC for tx_preemph (RU - read-only volatile)" newline hexmask.word.byte 0x0 0.--6. 1. "AMPLITUDE,Value from ASIC for tx_amplitude (RU - read-only volatile)" rgroup.word 0x1028++0x1 line.word 0x0 "LANE0_DIG_TX_ASIC_DRV_HI,Current values for incoming TX level controls from ASIC" newline hexmask.word 0x0 5.--15. 1. "RESERVED_15_5,Reserved for Future use" newline hexmask.word.byte 0x0 0.--4. 1. "TERM_OFFSET,Value from ASIC for tx_term_offset (RU - read-only volatile)" rgroup.word 0x102C++0x1 line.word 0x0 "LANE0_DIG_TX_ASIC_OUT,Current values for outgoing TX status controls from PHY" newline hexmask.word 0x0 5.--15. 1. "RESERVED_15_5,Reserved for Future use" newline bitfld.word 0x0 4. "STATE,Value from PHY for tx_state (RU - read-only volatile)" "0,1" newline bitfld.word 0x0 3. "CM_STATE,Value from PHY for tx_cm_state (RU - read-only volatile)" "0,1" newline bitfld.word 0x0 2. "DETECT_RX_ACK,Value from PHY for tx_detect_rx_ack (RU - read-only volatile)" "0,1" newline bitfld.word 0x0 1. "RESERVED,Always returns 0 (RU - read-only volatile)" "0,1" newline bitfld.word 0x0 0. "DETECT_RX_RES,Value from PHY for tx_detect_rx_res (RU - read-only volatile)" "0,1" rgroup.word 0x1030++0x1 line.word 0x0 "LANE0_DIG_RX_ASIC_IN,Current values for incoming RX controls from ASIC" newline bitfld.word 0x0 15. "RX_EQ_EN,Value from ASIC for rx_eq_en (RU - read-only volatile)" "0,1" newline bitfld.word 0x0 12.--14. "RX_EQ,Value from ASIC for rx_eq (RU - read-only volatile)" "0,1,2,3,4,5,6,7" newline bitfld.word 0x0 10.--11. "LOS_FILTER,Value from ASIC for rx_los_filter (RU - read-only volatile)" "0,1,2,3" newline bitfld.word 0x0 9. "LOS_EN,Value from ASIC for rx_los_en (RU - read-only volatile)" "0,1" newline bitfld.word 0x0 8. "TERM_EN,Value from ASIC for rx_term_en (RU - read-only volatile)" "0,1" newline bitfld.word 0x0 7. "CLK_SHIFT,Value from ASIC for rx_bit_shift (RU - read-only volatile)" "0,1" newline bitfld.word 0x0 6. "ALIGN_EN,Value from ASIC for rx_align_en (RU - read-only volatile)" "0,1" newline bitfld.word 0x0 5. "DATA_EN,Value from ASIC for rx_data_en (RU - read-only volatile)" "0,1" newline bitfld.word 0x0 4. "PLL_EN,Value from ASIC for rx_pll_en (RU - read-only volatile)" "0,1" newline bitfld.word 0x0 3. "RX_RESET,Value from ASIC for rx_reset (RU - read-only volatile)" "0,1" newline bitfld.word 0x0 2. "INVERT,Value from ASIC for rx_invert (RU - read-only volatile)" "0,1" newline bitfld.word 0x0 0.--1. "RX_RATE,Value from ASIC for rx_rate (RU - read-only volatile)" "0,1,2,3" rgroup.word 0x1034++0x1 line.word 0x0 "LANE0_DIG_RX_ASIC_OUT,Current values for outgoing RX status controls from PHY" newline hexmask.word 0x0 3.--15. 1. "RESERVED_15_3,Reserved for Future use" newline bitfld.word 0x0 2. "LOS,Value from PHY for rx_los (RU - read-only volatile)" "0,1" newline bitfld.word 0x0 1. "PLL_STATE,Value from PHY for rx_pll_state (RU - read-only volatile)" "0,1" newline bitfld.word 0x0 0. "VALID,Value from PHY for rx_valid (RU - read-only volatile)" "0,1" group.word 0x1040++0x1 line.word 0x0 "LANE0_DIG_TX_DEBUG,Transmit debug controls" newline rbitfld.word 0x0 13.--15. "RESERVED_15_13,Reserved for Future use" "0,1,2,3,4,5,6,7" newline bitfld.word 0x0 12. "KEEP_TX_REFGEN,Keep TX voltage regulator ON until TX clocks are OFF" "0,1" newline hexmask.word.byte 0x0 4.--11. 1. "RXDET_MEAS_TIME,Time to wait for rxdet measurement (* 4/2/1 refclk cycles based on multiplier)" newline bitfld.word 0x0 3. "DETECT_RX_ALWAYS,Always signal 1 for rx_detect ignoring analog" "0,1" newline bitfld.word 0x0 0.--2. "DTB_SEL,Selects data to drive on DTB 0 - disabled 1 - mag_update/sub signals 2 - mag_high/add signals 3 - clock aligner early/shift signals 4 - analog/asic clocks 5 - tx_state counter/lbert strobe 6 - noclk_ref_rst/dig_rst 7 -.." "disabled,mag_update/sub signals,mag_high/add signals,clock aligner early/shift signals,analog/asic clocks,tx_state counter/lbert strobe,noclk_ref_rst/dig_rst,tx_ana_rxdetp_high/tx_ana_rxdetm_high" group.word 0x1044++0x1 line.word 0x0 "LANE0_DIG_TX_CM_WAIT_TIME_OVRD,USB3_LANE0_DIG_TX_CM_WAIT_TIME_OVRD" newline hexmask.word.byte 0x0 11.--15. 1. "RESERVED_15_11,Reserved for Future use" newline bitfld.word 0x0 10. "CM_TIME_OVRD_EN,Override enable for common mode charging wait time." "0,1" newline hexmask.word 0x0 0.--9. 1. "CM_TIME_OVRD,Time to wait in ref clock cycles for LFPS common mode charging (This value x32 is used for VCMHOLD charging method)" rgroup.word 0x1048++0x1 line.word 0x0 "LANE0_DIG_TX_VMD_FSM_TX_VCM_0,Calculated values for N_USE and N_TRISTATE. Also TX ANA configuration shift register output." newline bitfld.word 0x0 15. "SHIFT_OUT,Current value from TX_ANAs configuration shift register. (RU - read-only volatile)" "0,1" newline bitfld.word 0x0 14. "DONE,Configuration is done (RU - read-only volatile)" "0,1" newline hexmask.word.byte 0x0 7.--13. 1. "N_USE,Value from VMD for legs to use. (RU - read-only volatile)" newline hexmask.word.byte 0x0 0.--6. 1. "N_TRISTATE,Value from VMD for number of tristate legs. (RU - read-only volatile)" rgroup.word 0x104C++0x1 line.word 0x0 "LANE0_DIG_TX_VMD_FSM_TX_VCM_1,Calculated values for N_FIXED and N_TRAILER." newline bitfld.word 0x0 15. "FIXED_DONE,N_FIXED Multiplication has completed. (RU - read-only volatile)" "0,1" newline bitfld.word 0x0 14. "TRA_DONE,N_TRAILER Multiplication has completed. (RU - read-only volatile)" "0,1" newline hexmask.word.byte 0x0 7.--13. 1. "N_FIXED,Value from VMD for number of fixed driver legs. (RU - read-only volatile)" newline hexmask.word.byte 0x0 0.--6. 1. "N_TRAILER,Value from VMD for number of trailer legs. (RU - read-only volatile)" group.word 0x1050++0x1 line.word 0x0 "LANE0_DIG_TX_VMD_FSM_TX_VCM_DEBUG_IN,Access the TX_ANA VMD Control Shift Register" newline hexmask.word 0x0 4.--15. 1. "RESERVED_15_4,Reserved for Future use" newline bitfld.word 0x0 3. "CONFIG_OVRD,Override the Voltage Mode Driver Configuration FSM and access the shift chain directly. (volatile and 2 reads needed to read value)" "0,1" newline bitfld.word 0x0 2. "CONFIG_LOAD,Override value for the Voltage Mode Driver Configuration FSM's config load. (volatile and 2 reads needed to read value)" "0,1" newline bitfld.word 0x0 1. "CONFIG_CLK,Override value for the Voltage Mode Driver Configuration FSM's config clk. (volatile and 2 reads needed to read value)" "0,1" newline bitfld.word 0x0 0. "CONFIG_DATA,Override value for the Voltage Mode Driver Configuration FSM's config data. (volatile and 2 reads needed to read value)" "0,1" group.word 0x1054++0x1 line.word 0x0 "LANE0_DIG_TX_LBERT_CTL,Pattern Generator controls" newline rbitfld.word 0x0 15. "RESERVED_15_15,Reserved for Future use" "0,1" newline hexmask.word 0x0 5.--14. 1. "PAT0,10 bit pattern for modes using PAT0 (5-7). Ignored for other MODEs." newline bitfld.word 0x0 4. "TRIGGER_ERR,Single shot inversion the LSB of the current symbol. Any write of a 1 to this bit will insert an error. Maintain mode and pattern from setup." "0,1" newline hexmask.word.byte 0x0 0.--3. 1. "MODE,Pattern to generate When changing modes you must change to disabled first 0 - disabled 1 - lfsr31. X^31 + X^28 + 1 2 - lfsr23. X^23 + X^18 + 1 3 - lfsr15. X^15 + X^14 + 1 4 - lfsr7. X^7 + X^6 + 1 5 - fixed word (PAT0) 6 - DC balanced word (PAT0.." group.word 0x1058++0x1 line.word 0x0 "LANE0_DIG_RX_LBERT_CTL,Pattern Matcher controls" newline hexmask.word 0x0 5.--15. 1. "RESERVED_15_5,Reserved for Future use" newline bitfld.word 0x0 4. "SYNC,Synchronize pattern matcher with incoming data A write of a one to this bit will reset the error counter and start a synchronization of the PM. There is no need to write this back to zero to run normally." "0,1" newline hexmask.word.byte 0x0 0.--3. 1. "MODE,Pattern to match When changing modes you must change to disabled first 0 - disabled 1 - lfsr31: X^31 + X^28 + 1 2 - lfsr23: X^23 + X^18 + 1 3 - lfsr15: X^15 + X^14 + 1 4 - lfsr7 : X^7 + X^6 + 1 5 - d[n] = d[n-10] 6 - d[n] = !d[n-10] 7 - d[n] =.." group.word 0x105C++0x1 line.word 0x0 "LANE0_DIG_RX_LBERT_ERR,Pattern match error counter" newline bitfld.word 0x0 15. "OV14,A read of this register or a sync of the Pattern Matcher resets the error count. If all bits of this register are 1 the error counter has saturated. If the status If active multiply COUNT by 128. If OV14=1 and COUNT=2^15-1 signals overflow of.." "0,1" newline hexmask.word 0x0 0.--14. 1. "COUNT,Current error count If OV14 field is active then multiply count by 128 to get the actual count. (volatile and 2 reads needed to read value)" group.word 0x1060++0x1 line.word 0x0 "LANE0_DIG_RX_SCOPE_CTL,Control bits for per-transciever scope portion" newline rbitfld.word 0x0 14.--15. "RESERVED_15_14,Reserved for Future use" "0,1,2,3" newline bitfld.word 0x0 12.--13. "RX_VALID_CTL,When to Start Sampling control based on rx_valid. 0 = Ignore rx_valid. 1 = Heed rx_valid. 2 = Wait for rising_edge on rx_valid." "Ignore rx_valid,Heed rx_valid,Wait for rising_edge on rx_valid,?" newline hexmask.word 0x0 3.--11. 1. "DELAY,number of cycles to skip between samples" newline bitfld.word 0x0 0.--2. "MODE,sampling mode of counters NOTE: WORD is 20 bits. 0 = off 1 = sample data every WORD*(1+DELAY) bits from the digital recovered path. 2 = sample data every WORD*(1+DELAY) + 1 bits from the digital recovered path. 3 = sample data every WORD*(1+DELAY) +.." "off,sample data every WORD*,sample data every WORD*,sample data every WORD*,sample data every WORD*,?,?,?" group.word 0x1064++0x1 line.word 0x0 "LANE0_DIG_RX_SCOPE_PHASE,Scope sampling phase." newline rbitfld.word 0x0 15. "RESERVED_15_15,Reserved for Future use" "0,1" newline hexmask.word.byte 0x0 10.--14. 1. "BASE,which bit to sample when MODE = 1 or 4" newline bitfld.word 0x0 8.--9. "SCOPE_DELAY,How many clocks to delay the analog scope_data." "0,1,2,3" newline bitfld.word 0x0 7. "SCOPE_SEL,Select Sampling Mode. 0 - Before AFE Sampling 1 - After AFE Sampling" "Before AFE Sampling,After AFE Sampling" newline bitfld.word 0x0 6. "UPDATE,Update Sampling phase. Write a 1." "0,1" newline hexmask.word.byte 0x0 0.--5. 1. "SAMPLE_PHASE,Sampling Phase" group.word 0x1068++0x1 line.word 0x0 "LANE0_DIG_RX_DPLL_FREQ,Current frequency integrator value." newline rbitfld.word 0x0 13.--15. "RESERVED_15_13,Reserved for Future use" "0,1,2,3,4,5,6,7" newline hexmask.word 0x0 1.--12. 1. "VAL,Freq is 1.526*VAL ppm from the reference When mpll_slow is set the ppm is half the eqn above (volatile and 2 reads needed to read value)" newline bitfld.word 0x0 0. "DTHR,Bits below the useful resolution (volatile and 2 reads needed to read value)" "0,1" group.word 0x106C++0x1 line.word 0x0 "LANE0_DIG_RX_CDR_CTL,Control bits for receiver in recovered domain" newline hexmask.word.byte 0x0 12.--15. 1. "DTB_SEL,select to drive various signals onto the dtb 0 - disabled 1 - pll_ana_rst pll_count from rx_pwr_ctl 2 - com_good_high/low from aligner 3 - com_bad_high/low from aligner 4 - shift_in_prog ana_odd_data from aligner 5 - low bits of XAUI align FSM.." newline bitfld.word 0x0 11. "ALWAYS_REALIGN,realign on any misaligned comma" "0,1" newline bitfld.word 0x0 10. "FAST_START,decrease startup steps by 50%" "0,1" newline bitfld.word 0x0 8.--9. "FRUG_VALUE,override value for FRUG" "0,1,2,3" newline bitfld.word 0x0 6.--7. "PHUG_VALUE,override value for PHUG" "0,1,2,3" newline bitfld.word 0x0 5. "OVRD_DPLL_GAIN,Override PHUG and FRUG values" "0,1" newline bitfld.word 0x0 4. "PHDET_POL,Reverse polarity of phase error" "0,1" newline bitfld.word 0x0 2.--3. "PHDET_EDGE,Edges to use for phase detection. 11 - Use both edges 10 - Use rising edges only 01 - Use falling edges only 00 - Ignore all edges" "Ignore all edges,Use falling edges only,?,?" newline bitfld.word 0x0 0.--1. "PHDET_EN,Enable phase detecter. top bit is odd slicers bottom is even" "0,1,2,3" rgroup.word 0x1070++0x1 line.word 0x0 "LANE0_DIG_RX_CDR_CDR_FSM_DEBUG,Current values for CDR and Adaptation FSM." newline bitfld.word 0x0 13.--15. "ADAP_RX_EQ,Equalization setting from adaptation FSM. (RU - read-only volatile)" "0,1,2,3,4,5,6,7" newline bitfld.word 0x0 10.--12. "RX_EQ_CTR,Initial centre point from equalization FSM. (RU - read-only volatile)" "0,1,2,3,4,5,6,7" newline bitfld.word 0x0 7.--9. "RX_ANA_EQ,Equalization setting to Analog. (RU - read-only volatile)" "0,1,2,3,4,5,6,7" newline bitfld.word 0x0 6. "ADAP_RX_VALID,Adaptation has completed and locked. (RU - read-only volatile)" "0,1" newline bitfld.word 0x0 5. "CDR_EN_ADAP,Adapatation loop is enabling the CDR. (RU - read-only volatile)" "0,1" newline bitfld.word 0x0 4. "CDR_EN_EQ,Equalization loop is enabling the CDR. (RU - read-only volatile)" "0,1" newline bitfld.word 0x0 3. "ALIGNED,Datapath is bit-aligned. (RU - read-only volatile)" "0,1" newline bitfld.word 0x0 2. "CDR_RX_VALID,CDR has locked to incoming data stream. (RU - read-only volatile)" "0,1" newline bitfld.word 0x0 1. "CDR_TIMEOUT,CDR has not locked to datastream and has timed-out. (RU - read-only volatile)" "0,1" newline bitfld.word 0x0 0. "CDR_EN,CDR has been enabled. (RU - read-only volatile)" "0,1" group.word 0x1074++0x1 line.word 0x0 "LANE0_DIG_RX_CDR_LOCK_VEC_OVRD,Control bits for receiver in recovered domain" newline hexmask.word.byte 0x0 11.--15. 1. "ADAP_CTR_LEVEL,Ammount of earlies that increment the adaptation counter (times 32 Default is 512). (volatile and 2 reads needed to read value)" newline bitfld.word 0x0 10. "ADAP_POLARITY,If asserted invert default adaptation adjustment for equalization. IF early decrease equalization. Normal mode is to decrease. (volatile and 2 reads needed to read value)" "0,1" newline bitfld.word 0x0 9. "LOCK_VECTOR_OVRD,Override enable for the rx_eq outputs. (volatile and 2 reads needed to read value)" "0,1" newline bitfld.word 0x0 8. "LOCK_VECTOR_EN,Override value for the locked_vector output completion. (volatile and 2 reads needed to read value)" "0,1" newline hexmask.word.byte 0x0 0.--7. 1. "LOCK_VECTOR,Override value for the locked_vector. (volatile and 2 reads needed to read value)" rgroup.word 0x1078++0x1 line.word 0x0 "LANE0_DIG_RX_CDR_LOCK_VEC,Current values for the locked vector.." newline hexmask.word.byte 0x0 12.--15. 1. "RESERVED_15_12,Reserved for Future use" newline bitfld.word 0x0 9.--11. "EQ_RX_EQ,Equalization setting from the Equalization Loop. (RU - read-only volatile)" "0,1,2,3,4,5,6,7" newline bitfld.word 0x0 8. "EQ_LOCKED_VECTOR_EN,Equalization locked vector has been filled. (RU - read-only volatile)" "0,1" newline hexmask.word.byte 0x0 0.--7. 1. "EQ_LOCKED_VECTOR,Results of equalization loop. (RU - read-only volatile)" rgroup.word 0x107C++0x1 line.word 0x0 "LANE0_DIG_RX_CDR_ADAP_FSM,Observation of adaptation FSM register." newline hexmask.word.byte 0x0 11.--15. 1. "MSTR_CTR,Master count register. (RU - read-only volatile)" newline hexmask.word.byte 0x0 7.--10. 1. "LOOP_CTR,Loop count register. (RU - read-only volatile)" newline hexmask.word.byte 0x0 3.--6. 1. "ADAP_CTR,Adaptation count register. (RU - read-only volatile)" newline bitfld.word 0x0 0.--2. "ADAP_STATE,Adaptation State. NOTE: ADAP_RESET = 3'b000 ADAP_LOCK = 3'b001 ADAP_SUFF = 3'b010 ADAP_LOOP = 3'b011 ADAP_MSTR = 3'b100 ADAP_DONE = 3'b101 (RU - read-only volatile)" "0,1,2,3,4,5,6,7" group.word 0x1080++0x1 line.word 0x0 "LANE0_ANA_RX_ATB0,ATB Control Register" newline hexmask.word.byte 0x0 8.--15. 1. "RESERVED_15_8,Reserved for Future use" newline bitfld.word 0x0 7. "EN_ATB,Enable ATB sensing and forcing on internal RX nodes" "0,1" newline bitfld.word 0x0 6. "EN_MARG,Enable margining mode in receiver; it puts EQ common mode output on atb_f_m" "0,1" newline bitfld.word 0x0 5. "EN_ATB_RM_F,Enable atb_f_p on negative-side termination resistor" "0,1" newline bitfld.word 0x0 4. "EN_ATB_RM_S,Enable atb_s_m on negative-side termination resistor" "0,1" newline bitfld.word 0x0 3. "EN_ATB_RP_F,Enable atb_f_p on positive-side termination resistor" "0,1" newline bitfld.word 0x0 2. "EN_ATB_RP_S,Enable atb_s_p on positive-side termination resistor" "0,1" newline bitfld.word 0x0 1. "EN_ATB_VOS,Put rxafe filtered outputs vo_p on atb_s_p and vo_m on atb_s_m" "0,1" newline bitfld.word 0x0 0. "EN_ATB_VOFF,Put rxafe voff_p on atb_s_p and voff_m on atb_s_m" "0,1" group.word 0x1084++0x1 line.word 0x0 "LANE0_ANA_RX_ATB1,ATB and Misc Control Register" newline hexmask.word.byte 0x0 8.--15. 1. "RESERVED_15_8,Reserved for Future use" newline bitfld.word 0x0 6.--7. "RX_DCC_IQ_OFFSET_H_4_3,Code which helps to manually tune reference voltage (r-string dac) for IQ opamp and correct input offset (rx_dcc_iq_offset_h_4_3 bit)" "0,1,2,3" newline bitfld.word 0x0 5. "EN_ATB_VLOS,Enable sensing of LOS reference voltage on atb_s_p" "0,1" newline bitfld.word 0x0 4. "EN_ATB_VRF,Enable sensing of vref_rx (RX Bias B.G. Voltage) on atb_s_p" "0,1" newline bitfld.word 0x0 3. "MEAS_GD,Enable sensing of local gd in RX; ties gd to atb_s_m" "0,1" newline bitfld.word 0x0 2. "MEAS_VP,Enable sensing of local vp in RX; ties vp to atb_s_p" "0,1" newline bitfld.word 0x0 0.--1. "RX_DCC_IQ_OFFSET_H_2_1,Code which helps to manually tune reference voltage (r-string dac) for IQ opamp and correct input offset (rx_dcc_iq_offset_h_2_1 bit)" "0,1,2,3" group.word 0x1088++0x1 line.word 0x0 "LANE0_ANA_RX_ENPWR0,RX State Control Register" newline hexmask.word.byte 0x0 8.--15. 1. "RESERVED_15_8,Reserved for Future use" newline bitfld.word 0x0 7. "CTL_RXPWRON,MUX select for AFE en to select between CTL_RXPWRON=0 rx_afe_en (External signal) or CTL_RXPWRON=1 LCL_RXPWRON" "0,1" newline bitfld.word 0x0 6. "LCL_RXPWRON,Enable/Disable RX AFE .This bit is only selected when CTL_RXPWRON = 1" "0,1" newline bitfld.word 0x0 5. "CTL_EN_LOS,MUX select for LOS en to select between CTL_EN_LOS=0 rx_los_en (External signal) or CTL_EN_LOS=1 LCL_EN_LOS" "0,1" newline bitfld.word 0x0 4. "LCL_EN_LOS,Enable/Disable LOS.This bit is only selected when CTL_EN_LOS = 1" "0,1" newline bitfld.word 0x0 3. "CTL_RXCK,MUX select for RX Clock en to select between CTL_RXCK=0 rx_clock_en (External signal) or CTL_RXCK=1 LCL_RXCK." "0,1" newline bitfld.word 0x0 2. "LCL_RXCK,Enable/Disable en_rx_clock (RX clock enable).This bit is only selected when CTL_RXCK = 1" "0,1" newline bitfld.word 0x0 1. "CTL_ACJT,MUX select for ACJTAG to select between CTL_ACJTG=0 rx_acjtg_en (External signal) or CTL_ACJTG=1 LCL_ACJT." "0,1" newline bitfld.word 0x0 0. "LCL_ACJT,Enable/Disable acjtag block This bit is only selected when CTL_ACJTG = 1" "0,1" group.word 0x108C++0x1 line.word 0x0 "LANE0_ANA_RX_PMIX_PHASE,Phase select Value" newline hexmask.word.byte 0x0 8.--15. 1. "RESERVED_15_8,Reserved for Future use" newline hexmask.word.byte 0x0 0.--7. 1. "PHASE,Write to bits 8 to 1 of the phase select register in the phase mixer through the CDR (USER2 volatile - read-write volatile and custom)" group.word 0x1090++0x1 line.word 0x0 "LANE0_ANA_RX_ENPWR1,Additional RX State Control Register" newline hexmask.word.byte 0x0 8.--15. 1. "RESERVED_15_8,Reserved for Future use" newline bitfld.word 0x0 7. "CTL_PHASE_REG_RST,MUX select for Phase Register Reset to select between CTL_PHASE_REG_RST=0 rx_phase_reg_rst (External signal) or CTL_PHASE_REG_RST=1 LCL_PHASE_REG_RST" "0,1" newline bitfld.word 0x0 6. "LCL_PHASE_REG_RST,Reset phase register.This bit is only selected when CTL_PHASE_REG_RST= 1" "0,1" newline bitfld.word 0x0 5. "CTL_BST,MUX select for AFE Boost to select between CTL_BST=0 rx_aeq[2:0] (External signal) or CTL_BST=1 LCL_BST" "0,1" newline bitfld.word 0x0 2.--4. "LCL_BST,RX Boost (equalization) Value" "0,1,2,3,4,5,6,7" newline bitfld.word 0x0 1. "CTL_RXTERM,MUX select for RX Term enable to select between CTL_RXTERM=0 rx_term_en (External signal) or CTL_RXTERM=1 LCL_RXTERM" "0,1" newline bitfld.word 0x0 0. "LCL_RXTERM,Enable/disable RX termination when CTL_RXTERM = 1" "0,1" group.word 0x1094++0x1 line.word 0x0 "LANE0_ANA_RX_ENPWR2,Yet another RX State Control Register" newline hexmask.word.byte 0x0 8.--15. 1. "RESERVED_15_8,Reserved for Future use" newline bitfld.word 0x0 7. "EN_RXPMIX_TST,Enable XOR gate to test linearity of RX phase mixer using atb_s_p and atb_s_m" "0,1" newline bitfld.word 0x0 6. "EN_RXPMIX_VPMIX,Put vreg_pmix on atb_s_p" "0,1" newline bitfld.word 0x0 5. "EN_RXPMIX_VRX,Put vreg_rx on atb_s_p" "0,1" newline bitfld.word 0x0 4. "RX_DCC_IQ_OFFSET_H_0,Code which helps to manually tune reference voltage (r-string dac) for IQ opamp and correct input offset (rx_dcc_iq_offset_h_0 bit)" "0,1" newline bitfld.word 0x0 3. "EN_RXPMIX_FRC_VPMIX_H,Connecting vbg_in to vbg (in case of 0) or to atb_s_m_int (in case of 1)" "0,1" newline bitfld.word 0x0 2. "RX_SCOPE_ATB_2,Put XOR of RX SCOPE PMIX input and output on atb_s_p" "0,1" newline bitfld.word 0x0 1. "RX_SCOPE_ATB_1,Put RX SCOPE regulated VP on atb_s_p" "0,1" newline bitfld.word 0x0 0. "RX_SCOPE_ATB_0,Have RX SCOPE reference for regulator use atb_f_p as a reference instead of VP/VBG" "0,1" group.word 0x1098++0x1 line.word 0x0 "LANE0_ANA_RX_SCOPE_VDCC,RX Scope controls and clock DCC control voltage probe" newline hexmask.word.byte 0x0 8.--15. 1. "RESERVED_15_8,Reserved for Future use" newline bitfld.word 0x0 6.--7. "VDCC,Probe DCC control voltage" "0,1,2,3" newline bitfld.word 0x0 5. "NC5,Reserved" "0,1" newline bitfld.word 0x0 4. "RX_SCOPE_SLEW,Set high for low RX clock frqeuencies (625MHz) for RX Scope to work correctly" "0,1" newline bitfld.word 0x0 3. "RX_SCOPE_FDIV20,Divide scope output clock by 20 instead of 10" "0,1" newline bitfld.word 0x0 2. "RX_LOS_LFPS_EN_BIT_2,In case of rx_los_lfps_en_cntrl = 1/0 reg_rx_los_lfps_en/rx_ana_los_lfps_en signal directly applied to rx_los circuit through I101 multiplexer." "0,1" newline bitfld.word 0x0 1. "RX_DCC_IQ_OFFSET_EN_H,Select ref voltage for IQ opamp from testmode part (in case of 1) or from ordinary resistive dividers (in case of 0)." "0,1" newline bitfld.word 0x0 0. "RX_LOS_LFPS_EN,Enables the RX LOS LFPS mode use when you want to detect incoming LFPS signals USB3.0" "0,1" group.word 0x10AC++0x1 line.word 0x0 "LANE0_ANA_TX_TXDRV_CNTRL,Register 3" newline hexmask.word.byte 0x0 8.--15. 1. "RESERVED_15_8,Reserved for Future use" newline bitfld.word 0x0 7. "PULL_DN_REG,register bit that causes the calibrated TX bits to pull down in a common mode fashion. If pull_dn_reg and tx_pull_up are both high then pull_dn_reg wins" "0,1" newline bitfld.word 0x0 6. "PULL_UP_REG,Register override for tx_pull_up. Used when ovrd_pull_up is HIGH causes calibrated TX bits to pull up in a common mode fashion unless pull_dn_reg is HIGH" "0,1" newline bitfld.word 0x0 5. "OVRD_PULL_UP,Selects local value of pull_up_reg instead of tx_pull_up" "0,1" newline bitfld.word 0x0 4. "VCM_HOLD_REG,Register override for tx_vcm_hold. Used when ovrd_vcm_hold is HIGH controls the TX common mode hold circuitry" "0,1" newline bitfld.word 0x0 3. "OVRD_VCM_HOLD,Selects local value of vcm_hold_reg instead of tx_vcm_hold to control state of TX common mode hold circuitry" "0,1" newline bitfld.word 0x0 2. "REFGEN_PWRDN_OVRD_N,Set LOW for TX regulator not to turn on when RX clock is enabled. Default is for TX regulator to turn on when RX or TX clock is enabled" "0,1" newline bitfld.word 0x0 1. "NOCONN_1,Reserved" "0,1" newline bitfld.word 0x0 0. "NOCONN_0,Reserved" "0,1" group.word 0x10B0++0x1 line.word 0x0 "LANE0_ANA_TX_POWER_CTL,Register 4" newline hexmask.word.byte 0x0 8.--15. 1. "RESERVED_15_8,Reserved for Future use" newline bitfld.word 0x0 7. "OVRD_EN,Enables local overrides for all signals in this register except for TX_DIV_CLK_EN which doesn't need this signal" "0,1" newline bitfld.word 0x0 6. "SERIAL_EN_REG,Forces state of tx_serial_en when OVRD_EN is 1" "0,1" newline bitfld.word 0x0 5. "CLK_EN_REG,Forces state of tx_clk_en when OVRD_EN is 1" "0,1" newline bitfld.word 0x0 4. "DATA_EN_REG,Forces state of tx_data_en when OVRD_EN is HIGH" "0,1" newline bitfld.word 0x0 3. "REFGEN_EN_REG,Register override value for tx_refgen_en. Controls the TX regulator biasing circuitry and the rxdetect comparators when OVRD_EN is HIGH. This function may be overridden by the state of refgen_pwdn_reg" "0,1" newline bitfld.word 0x0 2. "TX_DIV_CLK_EN,Enables the div clock that goes from the TX to the undersampler more appropriately called tx_sampler_clk_en this clock comes after the optional divide by 2 or 4 tx_clk_en must be HIGH to get a clock out" "0,1" newline bitfld.word 0x0 1. "REFGEN_PDN_REG,Register override for refgen pwdn. Used when OVRD_EN is HIGH. Controls the TX regulator biasing circuitry and the rxdetect comparators when OVRD_EN is HIGH" "0,1" newline bitfld.word 0x0 0. "LFPS_HIGH_PRIORITY,When this is set high LFPS priority becomes higher than tx_data" "0,1" group.word 0x10B4++0x1 line.word 0x0 "LANE0_ANA_TX_ALT_BLOCK,Register 5" newline hexmask.word.byte 0x0 8.--15. 1. "RESERVED_15_8,Reserved for Future use" newline bitfld.word 0x0 7. "EN_ALT_BUS,Enables the TX for alt bus mode powers up the TX regulator biasing circuitry and the rxdetect comparators. Needed if manually running the alt bus features" "0,1" newline bitfld.word 0x0 5.--6. "DRV_SOURCE_REG,Forces state of tx_data_source when OVRD_ALT_BUS is HIGH. 00 = serializer data or alt oscillator vp/vph/vphreg/vptx if selected 01 = jtag data differential 10 = LFPS oscillator differential 11 = jtag data common mode drive for test" "serializer data or alt oscillator..,jtag data differential,?,?" newline bitfld.word 0x0 4. "JTAG_DATA_REG,Forces state of jtag_data when OVRD_ALT_BUS is HIGH" "0,1" newline bitfld.word 0x0 1.--3. "TX_RINGO_CNTRL,Enables and connects the various test oscillators to the transmit pins must set drv_source_reg bus correctly. 0XX = All oscillators are disabled 100 = HV oscillator enabled 101 = SVT oscillator enabled 110 = LVT oscillator enabled 111.." "0,1,2,3,4,5,6,7" newline bitfld.word 0x0 0. "OVRD_ALT_BUS,Enables local overrides for alt-bus control signals: DRV_SOURCE_REG and JTAG_DATA_REG" "0,1" group.word 0x10B8++0x1 line.word 0x0 "LANE0_ANA_TX_ALT_AND_LOOPBACK,Register 6" newline hexmask.word.byte 0x0 8.--15. 1. "RESERVED_15_8,Reserved for Future use" newline bitfld.word 0x0 7. "OVRD_TX_LB,Enables the override of the tx_lb_en" "0,1" newline bitfld.word 0x0 6. "TX_LB_EN_REG,Forces state of tx_lb_en when OVRD_TX_LB is enabled" "0,1" newline bitfld.word 0x0 5. "ATB_VPTX,Connects vptx to atb_s_p and gd to atb_s_m" "0,1" newline bitfld.word 0x0 4. "ATB_VREG_TX,Connects TX regulator input reference to atb_s_p and gd to atb_s_m" "0,1" newline bitfld.word 0x0 3. "ATB_VDCCP,Connects vdcc_p to atb_s_p" "0,1" newline bitfld.word 0x0 2. "ATB_VDCCM,Connects vdcc_m to atb_s_m" "0,1" newline bitfld.word 0x0 1. "NOCONN_01,Reserved" "0,1" newline bitfld.word 0x0 0. "SELECT_PMIX_CLK,select pmix_clk for TX clock for ATE test mode" "0,1" group.word 0x10BC++0x1 line.word 0x0 "LANE0_ANA_TX_TX_ATB_REG,Register 7" newline hexmask.word.byte 0x0 8.--15. 1. "RESERVED_15_8,Reserved for Future use" newline bitfld.word 0x0 7. "ATB_PBIAS,Connect real pmos_bias voltage for TX PMOS driver pull up path to atb_s_p and local ground at the pmos_bias block to atb_s_m" "0,1" newline bitfld.word 0x0 6. "ATB_VCM_REP,Connect common mode replica voltage in pmos_bias block to atb_s_p and local ground to atb_s_m" "0,1" newline bitfld.word 0x0 5. "ATB_RXDETREF,Connect RX detect block reference voltage to atb_s_p and local ground to atb_s_m" "0,1" newline bitfld.word 0x0 4. "ATB_TXFP,Connect tx_p to atb_f_p" "0,1" newline bitfld.word 0x0 3. "ATB_TXFM,Connect tx_m to atb_f_m" "0,1" newline bitfld.word 0x0 2. "ATB_TXSP,Connect tx_p to atb_s_p" "0,1" newline bitfld.word 0x0 1. "ATB_TXSM,Connect tx_m to atb_s_m" "0,1" newline bitfld.word 0x0 0. "ATB_VCM,Connect tx_p/tx_m common mode voltage onto atb_s_p and local ground onto atb_s_m" "0,1" group.word 0x10C0++0x1 line.word 0x0 "LANE0_ANA_TX_TX_BOOST,Register 8" newline hexmask.word.byte 0x0 8.--15. 1. "RESERVED_15_8,Reserved for Future use" newline bitfld.word 0x0 7. "OVRD_VBOOST_EN,Enables the overrides on VBOOST_EN_REG" "0,1" newline bitfld.word 0x0 6. "VBOOST_EN_REG,Forces state of tx_vboost_en when OVRD_VBOOST_EN is HIGH" "0,1" newline bitfld.word 0x0 5. "VCON_EN_N,Forces state of vcon_en_n" "0,1" newline bitfld.word 0x0 4. "ATB_VBOOST,Connects vboost to atb_s_p and local ground to Atb_s_m" "0,1" newline bitfld.word 0x0 3. "ATB_VCMBOOST,Connects vcmboost to atb_s_p and local ground to atb_s_m." "0,1" newline bitfld.word 0x0 2. "ATB_F_VBOOST_REF,Enables forcing of tx_vboost_vref through atb_f_p from external" "0,1" newline bitfld.word 0x0 1. "OVRD_VREG_DECAP,Enables override of vreg_decap_en_n signal" "0,1" newline bitfld.word 0x0 0. "VREG_DECAP_EN_N_REG,Forces state of vreg_decap_en_n control signal. Controls whether extra decoupling is switched in for TX regulator output." "0,1" group.word 0x1100++0x1 line.word 0x0 "LANE0_DIG_RX_CDR_FSM_INIT_CTL,Control bits for CDR init phase portion" newline hexmask.word.byte 0x0 9.--15. 1. "RESERVED_15_9,Reserved for Future use" newline bitfld.word 0x0 8. "INIT_CNT_OVRD,Active high override enable bit to select the override INIT_CNT register 0 = Disabled 1 = Enabled" "Disabled,Enabled" newline hexmask.word.byte 0x0 0.--7. 1. "INIT_CNT,Override value for CDR Init Phase" group.word 0x1104++0x1 line.word 0x0 "LANE0_DIG_RX_CDR_FSM_TRACK_CTL,Control bits for CDR track phase portion" newline hexmask.word.byte 0x0 9.--15. 1. "RESERVED_15_9,Reserved for Future use" newline bitfld.word 0x0 8. "TRACK_CNT_OVRD,Active high override enable bit to select the override TRACK_CNT register 0 = Disabled 1 = Enabled" "Disabled,Enabled" newline hexmask.word.byte 0x0 0.--7. 1. "TRACK_CNT,Override value for CDR Track Phase" group.word 0x1108++0x1 line.word 0x0 "LANE0_DIG_RX_CDR_FSM_LOCK_CTL,Control bits for CDR lock phase portion" newline hexmask.word.byte 0x0 9.--15. 1. "RESERVED_15_9,Reserved for Future use" newline bitfld.word 0x0 8. "LOCK_CNT_OVRD,Active high override enable bit to select the override LOCK_CNT register 0 = Disabled 1 = Enabled" "Disabled,Enabled" newline hexmask.word.byte 0x0 0.--7. 1. "LOCK_CNT,Override value for CDR Lock Phase" repeat 9. (list 0x0 0x1 0x2 0x3 0x4 0x8 0x9 0xB 0xC )(list 0x0 0x4 0x8 0xC 0x10 0x20 0x24 0x2C 0x30 ) rgroup.word ($2+0x2000)++0x1 line.word 0x0 "PORT0_STAT_RO_$1,Status Register 0" newline hexmask.word 0x0 4.--15. 1. "RESERVED_15_4,Reserved for Future use" newline bitfld.word 0x0 3. "PLL_LOCK,analog PLL Lock Signal" "0,1" newline bitfld.word 0x0 2. "RX_SQUELCH,analog RX Squelch Signal" "0,1" newline bitfld.word 0x0 1. "RESERVED_1,Reserved" "0,1" newline bitfld.word 0x0 0. "RESERVED_0,Reserved" "0,1" repeat.end repeat 7. (list 0x5 0x6 0x7 0xA 0xD 0xE 0xF )(list 0x0 0x4 0x8 0x14 0x20 0x24 0x28 ) rgroup.word ($2+0x2014)++0x1 line.word 0x0 "PORT0_STAT_RO_$1,Status Register 5" newline hexmask.word 0x0 4.--15. 1. "RESERVED_15_4,Reserved for Future use" newline hexmask.word.byte 0x0 0.--3. 1. "DATAOUT,UTMI+ Output DATAOUT" repeat.end repeat 2. (list 0x0 0x6 )(list 0x0 0x18 ) group.word ($2+0x2040)++0x1 line.word 0x0 "PORT0_OVRD_RW_$1,Override Register 0" newline hexmask.word.byte 0x0 8.--15. 1. "RESERVED_15_8,Reserved for Future use" newline hexmask.word.byte 0x0 4.--7. 1. "OVERRD_ADDR_OVRD_EN,Override Enable for overrd_addr [7:4]" newline hexmask.word.byte 0x0 0.--3. 1. "OVERRD_ADDR,Analog Test Control Override Address [3:0]" repeat.end repeat 10. (list 0x1 0x2 0x3 0x4 0x8 0x9 0xA 0xB 0xE 0xF )(list 0x0 0x4 0x8 0xC 0x1C 0x20 0x24 0x28 0x34 0x38 ) group.word ($2+0x2044)++0x1 line.word 0x0 "PORT0_OVRD_RW_$1,Override Register 1" newline hexmask.word.byte 0x0 8.--15. 1. "RESERVED_15_8,Reserved for Future use" newline bitfld.word 0x0 7. "VBUS_VALID_PU_OVRD_EN,Override Enable for vbus_valid_pu" "0,1" newline bitfld.word 0x0 6. "OTG_PU_OVRD_EN,Override Enable for otg_pu" "0,1" newline bitfld.word 0x0 5. "TX_VREF_VREG_PU_OVRD_EN,Override Enable for tx_vref_vreg_pu" "0,1" newline bitfld.word 0x0 4. "SQRX_PU_OVRD_EN,Override Enable for sqrx_pu" "0,1" newline bitfld.word 0x0 3. "VBUS_VALID_PU,DRVVBUS Input" "0,1" newline bitfld.word 0x0 2. "OTG_PU,OTGDISABLE Input" "0,1" newline bitfld.word 0x0 1. "TX_VREF_VREG_PU,TX hs_driver Comparator Power Up" "0,1" newline bitfld.word 0x0 0. "SQRX_PU,RX squelch Comparator Power Up" "0,1" repeat.end group.word 0x2054++0x1 line.word 0x0 "PORT0_OVRD_RW_5,Override Register 5" newline hexmask.word.byte 0x0 8.--15. 1. "RESERVED_15_8,Reserved for Future use" newline bitfld.word 0x0 6.--7. "XO_CLK_DIV_OVRD_EN,Override Enable for xo_clk_div" "0,1,2,3" newline bitfld.word 0x0 5. "MSTR_OVERRD_BIT_OVRD_EN,Override Enable for mstr_overrd_bit" "0,1" newline bitfld.word 0x0 4. "OVERRD_ADDR_4_OVRD_EN,Override Enable for overrd_addr_4" "0,1" newline bitfld.word 0x0 2.--3. "XO_CLK_DIV,setting reference clock division" "0,1,2,3" newline bitfld.word 0x0 1. "MSTR_OVERRD_BIT,Analog Test Control Master Override" "0,1" newline bitfld.word 0x0 0. "OVERRD_ADDR_4,Analog Test Control Override Address [4]" "0,1" group.word 0x205C++0x1 line.word 0x0 "PORT0_OVRD_RW_7,Override Register 7" newline hexmask.word.byte 0x0 8.--15. 1. "RESERVED_15_8,Reserved for Future use" newline bitfld.word 0x0 7. "TX_LS_EN_OVRD_EN,Override Enable for tx_ls_en" "0,1" newline bitfld.word 0x0 4.--6. "PWR_SEQ_CLK_DIV_OVRD_EN,Override Enable for pwr_seq_clk_div" "0,1,2,3,4,5,6,7" newline bitfld.word 0x0 3. "TX_LS_EN,TX LS Enable" "0,1" newline bitfld.word 0x0 0.--2. "PWR_SEQ_CLK_DIV,setting power_sequence division" "0,1,2,3,4,5,6,7" group.word 0x2070++0x1 line.word 0x0 "PORT0_OVRD_RW_12,Override Register 12" newline hexmask.word.byte 0x0 8.--15. 1. "RESERVED_15_8,Reserved for Future use" newline bitfld.word 0x0 7. "RES_ACK_OUT_OVRD_EN,Override Enable for res_ack_out" "0,1" newline bitfld.word 0x0 5.--6. "PLL_CLK_DIV_OVRD_EN,Override Enable for pll_clk_div" "0,1,2,3" newline bitfld.word 0x0 4. "PLL_RESET_OVRD_EN,Override Enable for pll_reset" "0,1" newline bitfld.word 0x0 3. "RES_ACK_OUT,Ack resistor tune external requirement" "0,1" newline bitfld.word 0x0 1.--2. "PLL_CLK_DIV,setting MPLL division" "0,1,2,3" newline bitfld.word 0x0 0. "PLL_RESET,MPLL gear_shift" "0,1" group.word 0x2074++0x1 line.word 0x0 "PORT0_OVRD_RW_13,Override Register 13" newline hexmask.word.byte 0x0 8.--15. 1. "RESERVED_15_8,Reserved for Future use" newline bitfld.word 0x0 7. "BIST_MODE_OVRD_EN,Override Enable for bist_mode" "0,1" newline bitfld.word 0x0 6. "TEST_PKT_RPT_OVRD_EN,Override Enable for test_pkt_rpt" "0,1" newline bitfld.word 0x0 4.--5. "XO_CLK_SEL_OVRD_EN,Override Enable for xo_clk_sel" "0,1,2,3" newline bitfld.word 0x0 3. "BIST_MODE,BIST Mode" "0,1" newline bitfld.word 0x0 2. "TEST_PKT_RPT,BIST Test Packet Mode" "0,1" newline bitfld.word 0x0 0.--1. "XO_CLK_SEL,Reference Clock Selection" "0,1,2,3" rgroup.word 0x8000++0x1 line.word 0x0 "SUPX_DIG_IDCODE_LO,Low 16 bits of IDCODE" newline hexmask.word 0x0 0.--15. 1. "DATA," rgroup.word 0x8004++0x1 line.word 0x0 "SUPX_DIG_IDCODE_HI,High 16 bits of IDCODE" newline hexmask.word 0x0 0.--15. 1. "DATA," group.word 0x8008++0x1 line.word 0x0 "SUPX_DIG_DEBUG,Debug controls" newline hexmask.word 0x0 7.--15. 1. "RESERVED_15_7,Reserved for Future use" newline bitfld.word 0x0 5.--6. "DTB_SEL,The lane DTB's are OR'd together with the support DTB signals selected with the below encodings 0 - none 1 - reset_ctl DTB output 2 - scope DTB output 3 - rtune DTB output" "none,reset_ctl DTB output,scope DTB output,rtune DTB output" newline hexmask.word.byte 0x0 0.--4. 1. "TX_VREF_SEL," group.word 0x800C++0x1 line.word 0x0 "SUPX_DIG_RTUNE_DEBUG,Resistor tuning debug controls" newline rbitfld.word 0x0 15. "RESERVED_15_15,Reserved for Future use" "0,1" newline hexmask.word 0x0 5.--14. 1. "VALUE,Value to use when triggering SET_VAL field only the 6 LSB's are used when setting rx or tx cal values (USER2 - read-write and custom)" newline bitfld.word 0x0 3.--4. "TYPE,Type of manual tuning or register read/write to execute 0 - ADC or read/write rt_value 1 - Rx tune or read/write rx_cal_val (only 6 bits) 2 - Tx tune or read/write tx_cal_val (only 6 bits) 3 - Resref detect (no affect when triggering SET_VAL.." "ADC,Rx tune,read-write and custom),Resref detect" newline bitfld.word 0x0 2. "SET_VAL,Set value Write to a 1 to manually write the register specified by the TYPE field to the value in the VALUE field (USER2 - read-write and custom)" "0,1" newline bitfld.word 0x0 1. "MAN_TUNE,Write to a 1 to do a manual tuning specified by TYPE field starting a manual tune while a tune is currently running can cause unpredictable results. For use only when you know the state of the rtune circuit. (USER2 - read-write and custom)" "0,1" newline bitfld.word 0x0 0. "FLIP_COMP,Invert analog comparator output (USER2 - read-write and custom)" "0,1" rgroup.word 0x8010++0x1 line.word 0x0 "SUPX_DIG_RTUNE_STAT,Resistor tuning register status" newline hexmask.word.byte 0x0 10.--15. 1. "RESERVED_15_10,Reserved for Future use" newline hexmask.word 0x0 0.--9. 1. "STAT,Current value of the register specifed by the TYPE field in the debug control register. Set the TYPE field in the DEBUG register and then do a read of this register. (RU - read-only volatile)" group.word 0x8014++0x1 line.word 0x0 "SUPX_DIG_SS_PHASE,Current MPLL phase selector value" newline bitfld.word 0x0 13.--15. "REF_SEL_DIV,Reference Divisor to get better resolution and lower PPM errors when synthesizing from a non-integer reference clock. NOTE: Default value is 4. One is added in hardware to give a range of 1 to 8. (volatile and 2 reads needed to read value)" "0,1,2,3,4,5,6,7" newline bitfld.word 0x0 12. "PH_SEL,Phase Mixer Clock select. 1: is pmix. 0 is VCO. (volatile and 2 reads needed to read value)" "?,is pmix" newline bitfld.word 0x0 11. "ZERO_FREQ,Zero frequency register. NOTES: Must be set for PHASE writes to stick (volatile and 2 reads needed to read value)" "0,1" newline hexmask.word 0x0 2.--10. 1. "VAL,Phase value from zero reference (volatile and 2 reads needed to read value)" newline bitfld.word 0x0 0.--1. "DTHR,Bits below the useful resolution (volatile and 2 reads needed to read value)" "0,1,2,3" group.word 0x8018++0x1 line.word 0x0 "SUPX_DIG_SS_FREQ,Frequency Control for Spread Spectrum" newline rbitfld.word 0x0 15. "RESERVED_15_15,Reserved for Future use" "0,1" newline bitfld.word 0x0 14. "FREQ_OVRD,Frequency Reigster Override. NOTE: Must be set for PHASE writes to stick (volatile and 2 reads needed to read value)" "0,1" newline hexmask.word.byte 0x0 7.--13. 1. "FREQ_PK,Peak Frequency Value (for changing direction) (volatile and 2 reads needed to read value)" newline hexmask.word.byte 0x0 0.--6. 1. "FREQ_CNT_INIT,Initial Frequency Counter Value (volatile and 2 reads needed to read value)" group.word 0x801C++0x1 line.word 0x0 "SUPX_DIG_HSP_SS_PHASE,Current HSP_PMIX SSC phase sel value" newline hexmask.word.byte 0x0 11.--15. 1. "RESERVED_15_11,Reserved for Future use" newline hexmask.word.byte 0x0 4.--10. 1. "VAL,SSC phase value from zero reference (volatile and 2 reads needed to read value)" newline hexmask.word.byte 0x0 0.--3. 1. "DTHR,Bits below the useful resolution (volatile and 2 reads needed to read value)" group.word 0x8020++0x1 line.word 0x0 "SUPX_DIG_MPLL_CNT_CTL,Control for fixed or variable MPLL Count Selection" newline hexmask.word 0x0 1.--15. 1. "RESERVED_15_1,Reserved for Future use" newline bitfld.word 0x0 0. "VAR_CNT_EN,Selects variable count when enabled (Default = fixed count)" "0,1" group.word 0x8024++0x1 line.word 0x0 "SUPX_DIG_CR_PARA_ALU_CTL,Control for CR Parallel ALU access" newline hexmask.word 0x0 5.--15. 1. "RESERVED_15_5,Reserved for Future use" newline hexmask.word.byte 0x0 1.--4. 1. "CR_PARA_ALU_OPCODE,Opcode for the ALU when CR para access is enabled. Valid opcodes are as follows: 0 - Zero the accumulator 1 - Add control register read result to accumulator 2 - Add control register write data to accumulator 3 - Shift accumulator left.." newline bitfld.word 0x0 0. "CR_PARA_ALU_ACCESS_EN,Enable access to the ALU through the CR parallel bus." "0,1" rgroup.word 0x8028++0x1 line.word 0x0 "SUPX_DIG_CR_PARA_ALU_FLAGS,Flags from the ALU when CR para access is enabled." newline hexmask.word 0x0 4.--15. 1. "RESERVED_15_4,Reserved for Future use" newline hexmask.word.byte 0x0 0.--3. 1. "DATA,Flags from the ALU when CR para access is enabled. Valid ALU flags: 0 - Signedness used for next ADD_PHSEL command. (1=signed 0=unsigned) 1 - Signedness for ADD_PHSEL command has been chosen by a previous ADD_PHSEL command. 2 - Error detected.." group.word 0x8040++0x1 line.word 0x0 "SUPX_DIG_ATEOVRD,Override values for incoming controls from ASIC" newline hexmask.word 0x0 3.--15. 1. "RESERVED_15_3,Reserved for Future use" newline bitfld.word 0x0 2. "ATEOVRD_EN,Override enable for ATE signals. NOTE: This register is only accessible through cregs. Does not retain state during reset or ATPG. (USER2 - read-write and custom)" "0,1" newline bitfld.word 0x0 1. "REF_USB2_EN,Override value for USB HSP PHY ref_clk enable. (USER2 - read-write and custom)" "0,1" newline bitfld.word 0x0 0. "REF_CLKDIV2,Override value for SSP ref_clk pre-scaler. (USER2 - read-write and custom)" "0,1" group.word 0x8044++0x1 line.word 0x0 "SUPX_DIG_MPLL_OVRD_IN_LO,Override values for incoming RTUNE and MPLL controls from ASIC" newline bitfld.word 0x0 15. "RES_ACK_IN_OVRD,Override enable for res_ack_in" "0,1" newline bitfld.word 0x0 14. "RES_ACK_IN,Override value for res_ack_in" "0,1" newline bitfld.word 0x0 13. "RES_REQ_IN_OVRD,Override enable for res_req_in" "0,1" newline bitfld.word 0x0 12. "RES_REQ_IN,Override value for res_req_in" "0,1" newline bitfld.word 0x0 11. "RTUNE_REQ_OVRD,Override enable for rtune_req" "0,1" newline bitfld.word 0x0 10. "RTUNE_REQ,Override value for rtune_req" "0,1" newline bitfld.word 0x0 9. "MPLL_MULTIPLIER_OVRD,Override enable for mpll_multipler" "0,1" newline hexmask.word.byte 0x0 2.--8. 1. "MPLL_MULTIPLIER,Override value for mpll_multipler" newline bitfld.word 0x0 1. "MPLL_EN_OVRD,Override enable for mpll_en" "0,1" newline bitfld.word 0x0 0. "MPLL_EN,Override value for mpll_en" "0,1" group.word 0x8048++0x1 line.word 0x0 "SUPX_DIG_MPLL_OVRD_IN_HI,Override values for incoming VBOOST LVL and MPLL controls from ASIC" newline bitfld.word 0x0 13.--15. "TX_VBOOST_LVL,Override value for tx_vboost_lvl. Override enabled using LEVEL_EN from LEVEL_OVRD_IN register." "0,1,2,3,4,5,6,7" newline bitfld.word 0x0 12. "MPLL_REFSSC_CLK_EN_OVRD,Override enable for mpll_refssc_clk_en" "0,1" newline bitfld.word 0x0 11. "MPLL_REFSSC_CLK_EN,Override value for mpll_refssc_clk_en" "0,1" newline bitfld.word 0x0 10. "MPLL_RST,Reset the MPLL state machine Writing the register with this bit set will reset the MPLL power up/down FSM regardless of the current state of the register bit." "0,1" newline bitfld.word 0x0 9. "FSEL_OVRD,Override enable for fsel[2:0]" "0,1" newline bitfld.word 0x0 6.--8. "FSEL,Override value for fsel [2:0]" "0,1,2,3,4,5,6,7" newline bitfld.word 0x0 5. "MPLL_WORD_CLK_EN_OVRD,Override enable for mpll_word_clk_en" "0,1" newline bitfld.word 0x0 4. "MPLL_WORD_CLK_EN,Override value for mpll_word_clk_en" "0,1" newline bitfld.word 0x0 3. "MPLL_DWORD_CLK_EN_OVRD,Override enable for mpll_dword_clk_en" "0,1" newline bitfld.word 0x0 2. "MPLL_DWORD_CLK_EN,Override value for mpll_dword_clk_en" "0,1" newline bitfld.word 0x0 1. "MPLL_QWORD_CLK_EN_OVRD,Override enable for mpll_qword_clk_en" "0,1" newline bitfld.word 0x0 0. "MPLL_QWORD_CLK_EN,Override value for mpll_qword_clk_en" "0,1" group.word 0x804C++0x1 line.word 0x0 "SUPX_DIG_SSC_OVRD_IN,Override values for incoming SSC controls from ASIC" newline rbitfld.word 0x0 14.--15. "RESERVED_15_14,Reserved for Future use" "0,1,2,3" newline bitfld.word 0x0 13. "SSC_OVRD_IN_EN,Override enable for Spread Spectrum generator." "0,1" newline bitfld.word 0x0 12. "SSC_EN,Override value for SSC enable." "0,1" newline bitfld.word 0x0 9.--11. "SSC_RANGE,Override value for SSC modulation range." "0,1,2,3,4,5,6,7" newline hexmask.word 0x0 0.--8. 1. "SSC_REF_CLK_SEL,Override value for reference clock scaling" group.word 0x8050++0x1 line.word 0x0 "SUPX_DIG_BS_OVRD_IN,Override values for incoming BS controls from ASIC" newline hexmask.word.byte 0x0 12.--15. 1. "RESERVED_15_12,Reserved for Future use" newline bitfld.word 0x0 11. "EN,Enable override values for all inputs controlled by this register" "0,1" newline bitfld.word 0x0 10. "INVERT,Override value for bs_invert" "0,1" newline bitfld.word 0x0 9. "INIT,Override value for bs_init" "0,1" newline bitfld.word 0x0 8. "HIGHZ,Override value for bs_highz" "0,1" newline bitfld.word 0x0 7. "CLAMP,Override value for bs_clamp" "0,1" newline bitfld.word 0x0 6. "EXTEST_AC,Override value for bs_extest_ac" "0,1" newline bitfld.word 0x0 5. "EXTEST,Override value for bs_extest" "0,1" newline bitfld.word 0x0 4. "PRELOAD,Override value for bs_preload" "0,1" newline bitfld.word 0x0 3. "UPDATE_DR,Override value for bs_update_dr" "0,1" newline bitfld.word 0x0 2. "CAPTURE_DR,Override value for bs_capture_dr" "0,1" newline bitfld.word 0x0 1. "SHIFT_DR,Override value for bs_shift_dr" "0,1" newline bitfld.word 0x0 0. "IN,Override value for bs_in" "0,1" group.word 0x8054++0x1 line.word 0x0 "SUPX_DIG_LEVEL_OVRD_IN,Override values for acjt_level and los_level" newline bitfld.word 0x0 13.--15. "LOS_BIAS,Override value for los_bias" "0,1,2,3,4,5,6,7" newline bitfld.word 0x0 12. "MPLL_HALF_RATE_OVRD,Enable override value for mpll_half_rate" "0,1" newline bitfld.word 0x0 11. "MPLL_HALF_RATE,Override value for mpll_half_rate" "0,1" newline bitfld.word 0x0 10. "LEVEL_EN,Enable override values for tx_vboost_lvl/los_bias/los_level/acjt_level inputs controlled by this and MPLL_OVRD_IN_HI registers" "0,1" newline hexmask.word.byte 0x0 5.--9. 1. "ACJT_LEVEL,Override value for acjt_level" newline hexmask.word.byte 0x0 0.--4. 1. "LOS_LEVEL,Override value for los_level" group.word 0x8058++0x1 line.word 0x0 "SUPX_DIG_SUP_OVRD_OUT,Override values for support block" newline hexmask.word.byte 0x0 10.--15. 1. "RESERVED_15_10,Reserved for Future use" newline bitfld.word 0x0 9. "MPLL_STATE_OVRD,Override enable for mpll_state output" "0,1" newline bitfld.word 0x0 8. "MPLL_STATE,Override value for mpll_state output" "0,1" newline bitfld.word 0x0 7. "BS_OUT_OVRD,Override enable for bs_out output" "0,1" newline bitfld.word 0x0 6. "BS_OUT,Override value for bs_out output" "0,1" newline bitfld.word 0x0 5. "RTUNE_ACK_OVRD,Override enable for rtune_ack output" "0,1" newline bitfld.word 0x0 4. "RTUNE_ACK,Override value for rtune_ack output" "0,1" newline bitfld.word 0x0 3. "RES_REQ_OUT_OVRD,Override enable for res_req_out output" "0,1" newline bitfld.word 0x0 2. "RES_REQ_OUT,Override value for res_req_out output" "0,1" newline bitfld.word 0x0 1. "RES_ACK_OUT_OVRD,Override enable for res_ack_out output" "0,1" newline bitfld.word 0x0 0. "RES_ACK_OUT,Override value for res_ack_out output" "0,1" rgroup.word 0x805C++0x1 line.word 0x0 "SUPX_DIG_MPLL_ASIC_IN,Current values for incoming MPLL controls from ASIC" newline bitfld.word 0x0 15. "RESERVED_15_15,Reserved for Future use" "0,1" newline bitfld.word 0x0 14. "MPLL_REFSSC_CLK_EN,Value from ASIC for mpll_refssc_clk_en (RU - read-only volatile)" "0,1" newline bitfld.word 0x0 13. "MPLL_WORD_CLK_EN,Value from ASIC for mpll_word_clk_en (RU - read-only volatile)" "0,1" newline bitfld.word 0x0 12. "MPLL_DWORD_CLK_EN,Value from ASIC for mpll_dword_clk_en (RU - read-only volatile)" "0,1" newline bitfld.word 0x0 11. "MPLL_QWORD_CLK_EN,Value from ASIC for mpll_qword_clk_en (RU - read-only volatile)" "0,1" newline bitfld.word 0x0 10. "RES_ACK_IN,Value from ASIC for res_ack_in (RU - read-only volatile)" "0,1" newline bitfld.word 0x0 9. "RES_REQ_IN,Value from ASIC for res_req_in (RU - read-only volatile)" "0,1" newline bitfld.word 0x0 8. "RTUNE_REQ,Value from ASIC for rtune_req (RU - read-only volatile)" "0,1" newline hexmask.word.byte 0x0 1.--7. 1. "MPLL_MULTIPLIER,Value from ASIC for mpll_multiplier (RU - read-only volatile)" newline bitfld.word 0x0 0. "MPLL_EN,Value from ASIC for mpll_en (RU - read-only volatile)" "0,1" rgroup.word 0x8060++0x1 line.word 0x0 "SUPX_DIG_BS_ASIC_IN,Current values for incoming boundary scan controls from ASIC" newline bitfld.word 0x0 14.--15. "RESERVED_15_14,Reserved for Future use" "0,1,2,3" newline bitfld.word 0x0 11.--13. "TX_VBOOST_LVL,Value from ASIC for tx_vboost_lvl -- Not as bs_* signal but we're out of bits. (RU - read-only volatile)" "0,1,2,3,4,5,6,7" newline bitfld.word 0x0 10. "INVERT,Value from ASIC for bs_invert (RU - read-only volatile)" "0,1" newline bitfld.word 0x0 9. "INIT,Value from ASIC for bs_init (RU - read-only volatile)" "0,1" newline bitfld.word 0x0 8. "HIGHZ,Value from ASIC for bs_highz (RU - read-only volatile)" "0,1" newline bitfld.word 0x0 7. "CLAMP,Value from ASIC for bs_clamp (RU - read-only volatile)" "0,1" newline bitfld.word 0x0 6. "EXTEST_AC,Value from ASIC for bs_extest_ac (RU - read-only volatile)" "0,1" newline bitfld.word 0x0 5. "EXTEST,Value from ASIC for bs_extest (RU - read-only volatile)" "0,1" newline bitfld.word 0x0 4. "PRELOAD,Value from ASIC for bs_preload (RU - read-only volatile)" "0,1" newline bitfld.word 0x0 3. "UPDATE_DR,Value from ASIC for bs_update_dr (RU - read-only volatile)" "0,1" newline bitfld.word 0x0 2. "CAPTURE_DR,Value from ASIC for bs_capture_dr (RU - read-only volatile)" "0,1" newline bitfld.word 0x0 1. "SHIFT_DR,Value from ASIC for bs_shift_dr (RU - read-only volatile)" "0,1" newline bitfld.word 0x0 0. "IN,Value from ASIC for bs_in (RU - read-only volatile)" "0,1" rgroup.word 0x8064++0x1 line.word 0x0 "SUPX_DIG_LEVEL_ASIC_IN,Current values for incoming los/acjt level. MPLL half rate mode and vreg bypass from ASIC" newline bitfld.word 0x0 15. "RESERVED_15_15,Reserved for Future use" "0,1" newline bitfld.word 0x0 12.--14. "LOS_BIAS,Value from ASIC for los_bias (RU - read-only volatile)" "0,1,2,3,4,5,6,7" newline bitfld.word 0x0 11. "MPLL_HALF_RATE,Value from ASIC for mpll_half_rate (RU - read-only volatile)" "0,1" newline bitfld.word 0x0 10. "VREG_BYPASS,Value from ASIC for vreg_bypass (RU - read-only volatile)" "0,1" newline hexmask.word.byte 0x0 5.--9. 1. "ACJT_LEVEL,Value from ASIC for acjt_level (RU - read-only volatile)" newline hexmask.word.byte 0x0 0.--4. 1. "LOS_LEVEL,Value from ASIC for los_level (RU - read-only volatile)" rgroup.word 0x8068++0x1 line.word 0x0 "SUPX_DIG_SSC_ASIC_IN,Current values for incoming SSC controls from ASIC" newline bitfld.word 0x0 15. "SS_EN,Value from ASIC for ssc_en (RU - read-only volatile)" "0,1" newline bitfld.word 0x0 12.--14. "SSC_RANGE,Value from ASIC for ssc_range (RU - read-only volatile)" "0,1,2,3,4,5,6,7" newline hexmask.word 0x0 3.--11. 1. "SSC_REF_CLK_SEL,Value from ASIC for ssc_ref_clk_sel (RU - read-only volatile)" newline bitfld.word 0x0 0.--2. "FSEL,Value from ASIC for fsel (RU - read-only volatile)" "0,1,2,3,4,5,6,7" rgroup.word 0x806C++0x1 line.word 0x0 "SUPX_DIG_SUP_ASIC_OUT,Current values for outgoing support block controls to ASIC" newline hexmask.word 0x0 5.--15. 1. "RESERVED_15_5,Reserved for Future use" newline bitfld.word 0x0 4. "MPLL_STATE,Value from PHY for mpll_state output (RU - read-only volatile)" "0,1" newline bitfld.word 0x0 3. "BS_OUT,Value from PHY for bs_out output (RU - read-only volatile)" "0,1" newline bitfld.word 0x0 2. "RTUNE_ACK,Value from PHY for rtune_ack output (RU - read-only volatile)" "0,1" newline bitfld.word 0x0 1. "RES_REQ_OUT,Value from PHY for res_req_out output (RU - read-only volatile)" "0,1" newline bitfld.word 0x0 0. "RES_ACK_OUT,Value from PHY for res_ack_out output (RU - read-only volatile)" "0,1" rgroup.word 0x8070++0x1 line.word 0x0 "SUPX_DIG_ATEOVRD_STATUS,USB3_SUPX_DIG_ATEOVRD_STATUS" newline hexmask.word.byte 0x0 10.--15. 1. "RESERVED_15_10,Reserved for Future use" newline bitfld.word 0x0 8.--9. "DTB_OUT,Value from dtb_out bus. (RU - read-only volatile)" "0,1,2,3" newline bitfld.word 0x0 7. "REF_SSP_EN,Value from ASIC for ref_ssp_en. (RU - read-only volatile)" "0,1" newline bitfld.word 0x0 6. "REF_USE_PAD,Value from ASIC for ref_use_pad. (RU - read-only volatile)" "0,1" newline bitfld.word 0x0 5. "PHY_RESET_IN,Value from ASIC for phy_reset (RU - read-only volatile)" "0,1" newline bitfld.word 0x0 4. "REF_CLKDIV2_IN,Value from ASIC for ref_clkdiv2 (RU - read-only volatile)" "0,1" newline bitfld.word 0x0 3. "REF_USB2_EN_IN,Value from ASIC for ref_usb2_en (RU - read-only volatile)" "0,1" newline bitfld.word 0x0 2. "ATEOVRD_EN,When set values from ATEOVRD register are being sent to PHY (RU - read-only volatile)" "0,1" newline bitfld.word 0x0 1. "REF_CLKDIV2_OUT,Value from ATEOVRD for ref_clkdiv2 (RU - read-only volatile)" "0,1" newline bitfld.word 0x0 0. "REF_USB2_EN_OUT,Value from ATEOVRD for ref_usb2_en (RU - read-only volatile)" "0,1" group.word 0x8074++0x1 line.word 0x0 "SUPX_DIG_HSP_OVRD_IN,Override values for HSP" newline hexmask.word 0x0 4.--15. 1. "RESERVED_15_4,Reserved for Future use" newline bitfld.word 0x0 3. "HSP_PLL_OVRD,Override enable for HSP pll_pu signal" "0,1" newline bitfld.word 0x0 2. "HSP_PLL_PU,Override value for HSP pll_pu signal" "0,1" newline bitfld.word 0x0 1. "HSP_BIAS_OVRD,Override enable for HSP bias_pu signal" "0,1" newline bitfld.word 0x0 0. "HSP_BIAS_PU,Override value for HSP bias_pu signal" "0,1" rgroup.word 0x8078++0x1 line.word 0x0 "SUPX_DIG_HSP_ASIC_IN,Current values for incoming HSP & REF XO controls from ASIC" newline hexmask.word 0x0 4.--15. 1. "RESERVED_15_4,Reserved for Future use" newline bitfld.word 0x0 3. "REF_USE_XO,Value from ASIC for ref_use_xo (RU - read-only volatile)" "0,1" newline bitfld.word 0x0 2. "REF_XO_EN,Value from ASIC for ref_xo_en (RU - read-only volatile)" "0,1" newline bitfld.word 0x0 1. "HSP_PLL_PU,Value from ASIC for hsp_pll_pu (RU - read-only volatile)" "0,1" newline bitfld.word 0x0 0. "HSP_BIAS_PU,Value from ASIC for hsp_bias_pu (RU - read-only volatile)" "0,1" group.word 0x8080++0x1 line.word 0x0 "SUPX_DIG_SCOPE_ENABLES,Scope Counter configuration" newline hexmask.word 0x0 5.--15. 1. "RESERVED_15_5,Reserved for Future use" newline bitfld.word 0x0 3.--4. "LANE_SELECT,Scope Counter Input select" "0,1,2,3" newline bitfld.word 0x0 2. "MASK_SATURATION_MODE,Method of mask saturation. When 1 Saturate when the first mask_counter reaches sample_limit. When 0 Saturate when all mask_counters have reached sample_limit." "0,1" newline bitfld.word 0x0 1. "MASK_EN,Enable scope_mask input for tracking count values. Clears registers when deasserted." "0,1" newline bitfld.word 0x0 0. "XOR_EN,Use scope_xor input for count values." "0,1" group.word 0x8084++0x1 line.word 0x0 "SUPX_DIG_SCOPE_SAMPLES,Number of samples to count" newline hexmask.word 0x0 0.--15. 1. "SAMPLES,Number of Sample to count." rgroup.word 0x8088++0x1 line.word 0x0 "SUPX_DIG_SCOPE_COUNT,Results of scope counting" newline hexmask.word 0x0 0.--15. 1. "COUNT,A write to this register will start the counting process The value of FFFF indicates counting still in progress. Asserting MASK_EN will also start the counting if in MASK mode. (RU - read-only volatile)" group.word 0x808C++0x1 line.word 0x0 "SUPX_DIG_SCOPE_CTL,Masked scope counting Start and Status" newline hexmask.word 0x0 2.--15. 1. "RESERVED_15_2,Reserved for Future use" newline bitfld.word 0x0 1. "MASK_START,A write to this register will start the counting process The value of FFFF indicates counting still in progress Write will trigger mask counting. (USER1 - read-write volatile)" "?,read-write volatile)" newline bitfld.word 0x0 0. "MASK_SATURATION,When assert mask registers have saturated. (USER1 - read-write volatile)" "?,read-write volatile)" repeat 8. (list 0x0 0x1 0xA 0xB 0x64 0x65 0x6E 0x6F )(list 0x0 0x4 0x8 0xC 0x10 0x14 0x18 0x1C ) group.word ($2+0x8090)++0x1 line.word 0x0 "SUPX_DIG_SCOPE_MASK_$1,Current count value for mask_000" newline hexmask.word 0x0 0.--15. 1. "MASK_VAL_000,Starting count value of mask register. (volatile and 2 reads needed to read value)" repeat.end group.word 0x80C0++0x1 line.word 0x0 "SUPX_ANA_MPLL_LOOP_CTL,MPLL loop control bits" newline hexmask.word.byte 0x0 8.--15. 1. "RESERVED_15_8,Reserved for Future use" newline hexmask.word.byte 0x0 4.--7. 1. "PROP_CNTRL,Charge pump proportional current setting" newline bitfld.word 0x0 2.--3. "INT_CNTRL,Charge pump integrating current setting" "0,1,2,3" newline bitfld.word 0x0 1. "GD,Measure MPLL local GD" "0,1" newline bitfld.word 0x0 0. "VMB,Measure MPLL Master Bias Voltage" "0,1" repeat 2. (list 0x1 0x2 )(list 0x0 0x4 ) group.word ($2+0x80C4)++0x1 line.word 0x0 "SUPX_ANA_MPLL_ATB_MEAS$1,ATB Select bits" newline hexmask.word.byte 0x0 8.--15. 1. "RESERVED_15_8,Reserved for Future use" newline bitfld.word 0x0 7. "VPSF,puts vpsf on atb_s_p" "0,1" newline bitfld.word 0x0 6. "VREF,puts vref from charge pump on atb_s_p" "0,1" newline bitfld.word 0x0 5. "VCNTRL,puts vcntrl on atb_s_m" "0,1" newline bitfld.word 0x0 4. "GD,puts gd on atb_s_m" "0,1" newline bitfld.word 0x0 3. "IVCO,puts VCO current/93 on atb_f_m" "0,1" newline bitfld.word 0x0 2. "VP,puts vpa on atb_s_m" "0,1" newline bitfld.word 0x0 1. "VP_CP,puts vp_cp on atb_s_p" "0,1" newline bitfld.word 0x0 0. "VREG_MPLL,puts vreg_mpll on atb_s_p" "0,1" repeat.end group.word 0x80CC++0x1 line.word 0x0 "SUPX_ANA_MPLL_OVRD,Local overrides" newline hexmask.word.byte 0x0 8.--15. 1. "RESERVED_15_8,Reserved for Future use" newline bitfld.word 0x0 7. "PWRON_LCL,local power_on value" "0,1" newline bitfld.word 0x0 6. "EN_PWRON_LCL,Enable local control of power_on" "0,1" newline bitfld.word 0x0 5. "GS_LCL,local gear_shift value" "0,1" newline bitfld.word 0x0 4. "EN_GS_LCL,Enable local control of gear_shift" "0,1" newline bitfld.word 0x0 3. "RST_LCL,local reset value" "0,1" newline bitfld.word 0x0 2. "EN_RST_LCL,enable local control of reset" "0,1" newline bitfld.word 0x0 1. "PMIX_CLK_SEL_LCL,local pmix_clk_sel value" "0,1" newline bitfld.word 0x0 0. "EN_PMIX_CLK_SEL_LCL,enable local control of pmix_clk_sel" "0,1" group.word 0x80D0++0x1 line.word 0x0 "SUPX_ANA_RTUNE_RTUNE_CTRL,RTUNE control bits" newline hexmask.word.byte 0x0 8.--15. 1. "RESERVED_15_8,Reserved for Future use" newline bitfld.word 0x0 7. "RT_PWRON_FRC_ON,When set forces RTUNE block to be on" "0,1" newline bitfld.word 0x0 6. "X4_FRC_OFF,When set do not multiply test current by 4" "0,1" newline bitfld.word 0x0 4.--5. "RT_DAC_MODE,Margin DAC mode control bits(00=powerdown 01=DAC drives atb_s_p/m directly 10=DAC drives atb_s_p/m to the RX in margining mode 11=illegal state)" "powerdown,DAC drives atb_s_p/m directly,?,?" newline bitfld.word 0x0 3. "RT_DAC_CHOP,Margin DAC chop control bit. ref to ssp analog engineering doc 8.5" "0,1" newline bitfld.word 0x0 2. "RT_ATB,RTUNE ATB mode control bit (1=RTUNE performs ADC on ATB input 0=not accessing ATB. refer to ssp analog engineering specification 8.1.4)" "not accessing ATB,RTUNE performs ADC on ATB input" newline bitfld.word 0x0 1. "RT_SEL_ATBP,RTUNE ATB sense input select bit (1=atb_s_p 0=atb_s_m)" "atb_s_m),atb_s_p" newline bitfld.word 0x0 0. "RT_SEL_ATBF,RTUNE ATB input select bit (1=atb_fm 0=atb_s_p/m)" "atb_s_p/m),atb_fm" group.word 0x80D4++0x1 line.word 0x0 "SUPX_ANA_ATB_SWITCHYARD_CTRL,ATB_SWITCHYARD control bits" newline hexmask.word.byte 0x0 8.--15. 1. "RESERVED_15_8,Reserved for Future use" newline bitfld.word 0x0 7. "ASM_GD,Connect gd to atb_s_m" "0,1" newline bitfld.word 0x0 6. "ASP_VP,Connect vp to atb_s_p" "0,1" newline bitfld.word 0x0 5. "ASP_VBG,Connect vbg to atb_s_p" "0,1" newline bitfld.word 0x0 4. "ASP_VPHREG,Connect vphreg to atb_s_m" "0,1" newline bitfld.word 0x0 3. "ATEST_AFM,drive ATEST from atb_f_m" "0,1" newline bitfld.word 0x0 2. "ATEST_AFP,drive ATEST from atb_f_p" "0,1" newline bitfld.word 0x0 1. "ATEST_ASM,Connet ATEST to atb_s_m" "0,1" newline bitfld.word 0x0 0. "ATEST_ASP,Connect ATEST to atb_s_p" "0,1" group.word 0x80D8++0x1 line.word 0x0 "SUPX_ANA_SSC_CLK_CNTRL,controls sscf reference clock rate" newline hexmask.word.byte 0x0 8.--15. 1. "RESERVED_15_8,Reserved for Future use" newline bitfld.word 0x0 7. "NC,Reserved" "0,1" newline hexmask.word.byte 0x0 0.--6. 1. "SSC_CLK_DIV125,set ssc reference clock to be 20MHz" group.word 0x80DC++0x1 line.word 0x0 "SUPX_ANA_HSP_CLK_DIG_CNTRL0,controls HSP phase clock. and resolution" newline hexmask.word.byte 0x0 8.--15. 1. "RESERVED_15_8,Reserved for Future use" newline bitfld.word 0x0 7. "NUM_OVERRIDE,Set the value to 1 to enable using values from creg bit 6 downto 0" "0,1" newline bitfld.word 0x0 4.--6. "GATE_PMIX_BITS,Set gate_pmix_bits to gate the corresponding MSB of the 7-bit PMIX phase select bits" "?,?,?,?,?,?,?,bit PMIX phase select bits" newline bitfld.word 0x0 3. "HALF_CLK_EN,Set to 1 for 1.25GHz updates to HSP PMIX. Set to 0 for 2.5GHz updates to PMIX." "0,1" newline bitfld.word 0x0 2. "UCLK_EN_N,Set to 1 to disable update clock. Set to 0 to enable update clock. When clock is enabled phase updates are allowed." "0,1" newline bitfld.word 0x0 1. "EN_HSPPMIX_VPMIX,Set to 1 to connect the regulated HSP PMIX supply to the atb_s_p bus" "0,1" newline bitfld.word 0x0 0. "EN_HSPPMIX_FRC_VPMIX,Set to 1 to force override of HSP PMIX regulator voltage to voltage on atb_s_m" "0,1" group.word 0x80E0++0x1 line.word 0x0 "SUPX_ANA_HSP_CLK_DIG_CNTRL1,Lower and Upper Phase Increment Values" newline hexmask.word.byte 0x0 8.--15. 1. "RESERVED_15_8,Reserved for Future use" newline hexmask.word.byte 0x0 4.--7. 1. "UPPER_INT,These bits are only used when num_override is set to 1. Upper integer for phase increments of 2.5 to 2.4 GHz conversion. This is the phase increment that is applied 6 times in every 25 for 1.25 GHz increments and 3 times in every 25 for 2.5GHz" newline hexmask.word.byte 0x0 0.--3. 1. "LOWER_INT,These bits are only used when num_override is set to 1. Lower integer for phase increments of 2.5 to 2.4 GHz conversion. This phase increment is applied 19 times in every 25 for 1.25 GHz increments and 22 times in every 25 for 2.5GHz." group.word 0x9000++0x1 line.word 0x0 "LANEX_DIG_TX_OVRD_IN_LO,Override values for incoming TX controls from ASIC" newline bitfld.word 0x0 15. "LANE_IF_WIDTH_OVRD,Override enable for lane interface width" "0,1" newline bitfld.word 0x0 14. "LANE_IF_WIDTH,Override value for lane interface width" "0,1" newline bitfld.word 0x0 13. "TX_DETECT_RX_REQ_OVRD,Override enable for tx_detect_rx_req" "0,1" newline bitfld.word 0x0 12. "TX_DETECT_RX_REQ,Override value for tx_detect_rx_req" "0,1" newline bitfld.word 0x0 11. "TX_BEACON_EN_OVRD,Override enable for tx_beacon_en" "0,1" newline bitfld.word 0x0 10. "TX_BEACON_EN,Override value for tx_beacon_en" "0,1" newline bitfld.word 0x0 9. "TX_CM_EN_OVRD,Override enable for tx_cm_en" "0,1" newline bitfld.word 0x0 8. "TX_CM_EN,Override value for tx_cm_en" "0,1" newline bitfld.word 0x0 7. "TX_EN_OVRD,Override enable for tx_en" "0,1" newline bitfld.word 0x0 6. "TX_EN,Override value for tx_en" "0,1" newline bitfld.word 0x0 5. "TX_DATA_EN_OVRD,Override enable for tx_data_en" "0,1" newline bitfld.word 0x0 4. "TX_DATA_EN,Override value for tx_data_en" "0,1" newline bitfld.word 0x0 3. "TX_INVERT_OVRD,Override enable for tx_invert" "0,1" newline bitfld.word 0x0 2. "TX_INVERT,Override value for tx_invert" "0,1" newline bitfld.word 0x0 1. "TX_LOOPBK_EN_OVRD,Override enable for loopbk_en" "0,1" newline bitfld.word 0x0 0. "LOOPBK_EN,Override value for loopbk_en" "0,1" group.word 0x9004++0x1 line.word 0x0 "LANEX_DIG_TX_OVRD_IN_HI,Override values for incoming TX controls from ASIC" newline hexmask.word.byte 0x0 10.--15. 1. "RESERVED_15_10,Reserved for Future use" newline bitfld.word 0x0 9. "TX_VBOOST_EN_OVRD,Override enable for tx_vboost_en" "0,1" newline bitfld.word 0x0 8. "TX_VBOOST_EN,Override value for tx_vboost_en" "0,1" newline bitfld.word 0x0 7. "TX_RESET_OVRD,Override enable for tx_reset" "0,1" newline bitfld.word 0x0 6. "TX_RESET,Override value for tx_reset" "0,1" newline bitfld.word 0x0 5. "TX_NYQUIST_DATA,Override incoming data to nyquist" "0,1" newline bitfld.word 0x0 4. "TX_CLK_OUT_EN_OVRD,Override enable for tx_clk_out_en." "0,1" newline bitfld.word 0x0 3. "TX_CLK_OUT_EN,Override incomming tx_clk_out_en." "0,1" newline bitfld.word 0x0 2. "TX_RATE_OVRD,Override enable for tx_rate." "0,1" newline bitfld.word 0x0 0.--1. "TX_RATE,Override incomming tx lane rate." "0,1,2,3" group.word 0x9008++0x1 line.word 0x0 "LANEX_DIG_TX_OVRD_DRV_LO,Override values for incoming TX drive controls from ASIC" newline rbitfld.word 0x0 15. "RESERVED_15_15,Reserved for Future use" "0,1" newline bitfld.word 0x0 14. "EN,Enable override values for all inputs controlled by this register" "0,1" newline hexmask.word.byte 0x0 7.--13. 1. "PREEMPH,Override value for transmit preemphasis." newline hexmask.word.byte 0x0 0.--6. 1. "AMPLITUDE,Override value for transmit amplitude." group.word 0x900C++0x1 line.word 0x0 "LANEX_DIG_TX_OVRD_DRV_HI,Override values for incoming TX drive controls from ASIC" newline hexmask.word 0x0 6.--15. 1. "RESERVED_15_6,Reserved for Future use" newline bitfld.word 0x0 5. "EN,Enable override values for all inputs controlled by this register" "0,1" newline hexmask.word.byte 0x0 0.--4. 1. "TERM_OFFSET,Override value for tx_term_offset (tx_ana_vcmref_boost)" group.word 0x9010++0x1 line.word 0x0 "LANEX_DIG_TX_OVRD_OUT,Override values for outgoing TX controls to ASIC" newline hexmask.word.byte 0x0 8.--15. 1. "RESERVED_15_8,Reserved for Future use" newline bitfld.word 0x0 7. "TX_STATE_OVRD,Override enable for tx_state" "0,1" newline bitfld.word 0x0 6. "TX_STATE,Override value for tx_state" "0,1" newline bitfld.word 0x0 5. "TX_CM_STATE_OVRD,Override enable for tx_cm_state" "0,1" newline bitfld.word 0x0 4. "TX_CM_STATE,Override value for tx_cm_state" "0,1" newline bitfld.word 0x0 3. "TX_DETECT_RX_ACK_OVRD,Override enable for tx_detect_rx_ack" "0,1" newline bitfld.word 0x0 2. "TX_DETECT_RX_ACK,Override value for tx_detect_rx_ack" "0,1" newline bitfld.word 0x0 1. "DETECT_RX_RES_OVRD,Override enable for tx_detect_rx_res" "0,1" newline bitfld.word 0x0 0. "DETECT_RX_RES,Override value for tx_detect_rx_res" "0,1" group.word 0x9014++0x1 line.word 0x0 "LANEX_DIG_RX_OVRD_IN_LO,Override values for incoming RX controls from ASIC" newline rbitfld.word 0x0 14.--15. "RESERVED_15_14,Reserved for Future use" "0,1,2,3" newline bitfld.word 0x0 13. "RX_LOS_EN_OVRD,Override enable for rx_los_en" "0,1" newline bitfld.word 0x0 12. "RX_LOS_EN,Override value for rx_los_en" "0,1" newline bitfld.word 0x0 11. "RX_TERM_EN_OVRD,Override enable for rx_term_en" "0,1" newline bitfld.word 0x0 10. "RX_TERM_EN,Override value for rx_term_en" "0,1" newline bitfld.word 0x0 9. "RX_BIT_SHIFT_OVRD,Override enable for rx_bit_shift" "0,1" newline bitfld.word 0x0 8. "RX_BIT_SHIFT,Override value for rx_bit_shift" "0,1" newline bitfld.word 0x0 7. "RX_ALIGN_EN_OVRD,Override enable for rx_align_en" "0,1" newline bitfld.word 0x0 6. "RX_ALIGN_EN,Override value for rx_align_en" "0,1" newline bitfld.word 0x0 5. "RX_DATA_EN_OVRD,Override enable for rx_data_en" "0,1" newline bitfld.word 0x0 4. "RX_DATA_EN,Override value for rx_data_en" "0,1" newline bitfld.word 0x0 3. "RX_PLL_EN_OVRD,Override enable for rx_pll_en" "0,1" newline bitfld.word 0x0 2. "RX_PLL_EN,Override value for rx_pll_en" "0,1" newline bitfld.word 0x0 1. "RX_INVERT_OVRD,Override enable for rx_invert" "0,1" newline bitfld.word 0x0 0. "RX_INVERT,Override value for rx_invert" "0,1" group.word 0x9018++0x1 line.word 0x0 "LANEX_DIG_RX_OVRD_IN_HI,Override values for incoming RX controls from ASIC" newline rbitfld.word 0x0 14.--15. "RESERVED_15_14,Reserved for Future use" "0,1,2,3" newline bitfld.word 0x0 13. "RX_RESET_OVRD,Override enable for rx_reset" "0,1" newline bitfld.word 0x0 12. "RX_RESET,Override value for rx_reset" "0,1" newline bitfld.word 0x0 11. "RX_EQ_OVRD,Override enable for rx_eq" "0,1" newline bitfld.word 0x0 8.--10. "RX_EQ,Override value for rx_eq" "0,1,2,3,4,5,6,7" newline bitfld.word 0x0 7. "RX_EQ_EN_OVRD,Override enable for rx_eq_en" "0,1" newline bitfld.word 0x0 6. "RX_EQ_EN,Override value for rx_eq_en" "0,1" newline bitfld.word 0x0 5. "RX_LOS_FILTER_OVRD,Override enable for rx_los_filter" "0,1" newline bitfld.word 0x0 3.--4. "RX_LOS_FILTER,Override value for rx_los_filter" "0,1,2,3" newline bitfld.word 0x0 2. "RX_RATE_OVRD,Override enable for rx_rate" "0,1" newline bitfld.word 0x0 0.--1. "RX_RATE,Override value for rx_rate" "0,1,2,3" group.word 0x901C++0x1 line.word 0x0 "LANEX_DIG_RX_OVRD_OUT,Override values for outgoing RX controls to ASIC" newline hexmask.word 0x0 7.--15. 1. "RESERVED_15_7,Reserved for Future use" newline bitfld.word 0x0 6. "ZERO_DATA,Override data output to all zeros" "0,1" newline bitfld.word 0x0 5. "LOS_OVRD,Override value for rx_los" "0,1" newline bitfld.word 0x0 4. "LOS,Override value for rx_los" "0,1" newline bitfld.word 0x0 3. "PLL_STATE_OVRD,Override enable for rx_pll_state" "0,1" newline bitfld.word 0x0 2. "PLL_STATE,Override value for rx_pll_state" "0,1" newline bitfld.word 0x0 1. "VALID_OVRD,Override enable for rx_valid" "0,1" newline bitfld.word 0x0 0. "VALID,Override value for rx_valid" "0,1" rgroup.word 0x9020++0x1 line.word 0x0 "LANEX_DIG_TX_ASIC_IN,Current values for incoming TX controls from ASIC" newline bitfld.word 0x0 14.--15. "RESERVED_15_14,Reserved for Future use" "0,1,2,3" newline bitfld.word 0x0 13. "LANE_IF_WIDTH,Value from ASIC for lane_if_width (RU - read-only volatile)" "0,1" newline bitfld.word 0x0 12. "DATA_EN_S,Value from ASIC for tx_data_en_s (RU - read-only volatile)" "0,1" newline bitfld.word 0x0 11. "TX_VBOOST_EN,Value from ASIC for tx_vboost_en (RU - read-only volatile)" "0,1" newline bitfld.word 0x0 10. "TX_CLK_OUT_EN,Value from ASIC for tx_clk_out_en (RU - read-only volatile)" "0,1" newline bitfld.word 0x0 9. "DETECT_RX_REQ,Value from ASIC for tx_detect_rx_req (RU - read-only volatile)" "0,1" newline bitfld.word 0x0 8. "BEACON_EN,Value from ASIC for tx_beacon_en (RU - read-only volatile)" "0,1" newline bitfld.word 0x0 7. "CM_EN,Value from ASIC for tx_cm_en (RU - read-only volatile)" "0,1" newline bitfld.word 0x0 6. "TX_EN,Value from ASIC for tx_en (RU - read-only volatile)" "0,1" newline bitfld.word 0x0 5. "DATA_EN,Value from ASIC for tx_data_en (RU - read-only volatile)" "0,1" newline bitfld.word 0x0 4. "TX_RESET,Value from ASIC for tx_reset (RU - read-only volatile)" "0,1" newline bitfld.word 0x0 3. "INVERT,Value from ASIC for tx_invert (RU - read-only volatile)" "0,1" newline bitfld.word 0x0 2. "LOOPBK_EN,Value from ASIC for loopbk_en (RU - read-only volatile)" "0,1" newline bitfld.word 0x0 0.--1. "TX_RATE,Value from ASIC for tx_rate (RU - read-only volatile)" "0,1,2,3" rgroup.word 0x9024++0x1 line.word 0x0 "LANEX_DIG_TX_ASIC_DRV_LO,Current values for incoming TX level controls from ASIC" newline bitfld.word 0x0 14.--15. "RESERVED_15_14,Reserved for Future use" "0,1,2,3" newline hexmask.word.byte 0x0 7.--13. 1. "PREEMPH,Value from ASIC for tx_preemph (RU - read-only volatile)" newline hexmask.word.byte 0x0 0.--6. 1. "AMPLITUDE,Value from ASIC for tx_amplitude (RU - read-only volatile)" rgroup.word 0x9028++0x1 line.word 0x0 "LANEX_DIG_TX_ASIC_DRV_HI,Current values for incoming TX level controls from ASIC" newline hexmask.word 0x0 5.--15. 1. "RESERVED_15_5,Reserved for Future use" newline hexmask.word.byte 0x0 0.--4. 1. "TERM_OFFSET,Value from ASIC for tx_term_offset (RU - read-only volatile)" rgroup.word 0x902C++0x1 line.word 0x0 "LANEX_DIG_TX_ASIC_OUT,Current values for outgoing TX status controls from PHY" newline hexmask.word 0x0 5.--15. 1. "RESERVED_15_5,Reserved for Future use" newline bitfld.word 0x0 4. "STATE,Value from PHY for tx_state (RU - read-only volatile)" "0,1" newline bitfld.word 0x0 3. "CM_STATE,Value from PHY for tx_cm_state (RU - read-only volatile)" "0,1" newline bitfld.word 0x0 2. "DETECT_RX_ACK,Value from PHY for tx_detect_rx_ack (RU - read-only volatile)" "0,1" newline bitfld.word 0x0 1. "RESERVED,Always returns 0 (RU - read-only volatile)" "0,1" newline bitfld.word 0x0 0. "DETECT_RX_RES,Value from PHY for tx_detect_rx_res (RU - read-only volatile)" "0,1" rgroup.word 0x9030++0x1 line.word 0x0 "LANEX_DIG_RX_ASIC_IN,Current values for incoming RX controls from ASIC" newline bitfld.word 0x0 15. "RX_EQ_EN,Value from ASIC for rx_eq_en (RU - read-only volatile)" "0,1" newline bitfld.word 0x0 12.--14. "RX_EQ,Value from ASIC for rx_eq (RU - read-only volatile)" "0,1,2,3,4,5,6,7" newline bitfld.word 0x0 10.--11. "LOS_FILTER,Value from ASIC for rx_los_filter (RU - read-only volatile)" "0,1,2,3" newline bitfld.word 0x0 9. "LOS_EN,Value from ASIC for rx_los_en (RU - read-only volatile)" "0,1" newline bitfld.word 0x0 8. "TERM_EN,Value from ASIC for rx_term_en (RU - read-only volatile)" "0,1" newline bitfld.word 0x0 7. "CLK_SHIFT,Value from ASIC for rx_bit_shift (RU - read-only volatile)" "0,1" newline bitfld.word 0x0 6. "ALIGN_EN,Value from ASIC for rx_align_en (RU - read-only volatile)" "0,1" newline bitfld.word 0x0 5. "DATA_EN,Value from ASIC for rx_data_en (RU - read-only volatile)" "0,1" newline bitfld.word 0x0 4. "PLL_EN,Value from ASIC for rx_pll_en (RU - read-only volatile)" "0,1" newline bitfld.word 0x0 3. "RX_RESET,Value from ASIC for rx_reset (RU - read-only volatile)" "0,1" newline bitfld.word 0x0 2. "INVERT,Value from ASIC for rx_invert (RU - read-only volatile)" "0,1" newline bitfld.word 0x0 0.--1. "RX_RATE,Value from ASIC for rx_rate (RU - read-only volatile)" "0,1,2,3" rgroup.word 0x9034++0x1 line.word 0x0 "LANEX_DIG_RX_ASIC_OUT,Current values for outgoing RX status controls from PHY" newline hexmask.word 0x0 3.--15. 1. "RESERVED_15_3,Reserved for Future use" newline bitfld.word 0x0 2. "LOS,Value from PHY for rx_los (RU - read-only volatile)" "0,1" newline bitfld.word 0x0 1. "PLL_STATE,Value from PHY for rx_pll_state (RU - read-only volatile)" "0,1" newline bitfld.word 0x0 0. "VALID,Value from PHY for rx_valid (RU - read-only volatile)" "0,1" group.word 0x9040++0x1 line.word 0x0 "LANEX_DIG_TX_DEBUG,Transmit debug controls" newline rbitfld.word 0x0 13.--15. "RESERVED_15_13,Reserved for Future use" "0,1,2,3,4,5,6,7" newline bitfld.word 0x0 12. "KEEP_TX_REFGEN,Keep TX voltage regulator ON until TX clocks are OFF" "0,1" newline hexmask.word.byte 0x0 4.--11. 1. "RXDET_MEAS_TIME,Time to wait for rxdet measurement (* 4/2/1 refclk cycles based on multiplier)" newline bitfld.word 0x0 3. "DETECT_RX_ALWAYS,Always signal 1 for rx_detect ignoring analog" "0,1" newline bitfld.word 0x0 0.--2. "DTB_SEL,Selects data to drive on DTB 0 - disabled 1 - mag_update/sub signals 2 - mag_high/add signals 3 - clock aligner early/shift signals 4 - analog/asic clocks 5 - tx_state counter/lbert strobe 6 - noclk_ref_rst/dig_rst 7 -.." "disabled,mag_update/sub signals,mag_high/add signals,clock aligner early/shift signals,analog/asic clocks,tx_state counter/lbert strobe,noclk_ref_rst/dig_rst,tx_ana_rxdetp_high/tx_ana_rxdetm_high" group.word 0x9044++0x1 line.word 0x0 "LANEX_DIG_TX_CM_WAIT_TIME_OVRD,USB3_LANEX_DIG_TX_CM_WAIT_TIME_OVRD" newline hexmask.word.byte 0x0 11.--15. 1. "RESERVED_15_11,Reserved for Future use" newline bitfld.word 0x0 10. "CM_TIME_OVRD_EN,Override enable for common mode charging wait time." "0,1" newline hexmask.word 0x0 0.--9. 1. "CM_TIME_OVRD,Time to wait in ref clock cycles for LFPS common mode charging (This value x32 is used for VCMHOLD charging method)" rgroup.word 0x9048++0x1 line.word 0x0 "LANEX_DIG_TX_VMD_FSM_TX_VCM_0,Calculated values for N_USE and N_TRISTATE. Also TX ANA configuration shift register output." newline bitfld.word 0x0 15. "SHIFT_OUT,Current value from TX_ANAs configuration shift register. (RU - read-only volatile)" "0,1" newline bitfld.word 0x0 14. "DONE,Configuration is done (RU - read-only volatile)" "0,1" newline hexmask.word.byte 0x0 7.--13. 1. "N_USE,Value from VMD for legs to use. (RU - read-only volatile)" newline hexmask.word.byte 0x0 0.--6. 1. "N_TRISTATE,Value from VMD for number of tristate legs. (RU - read-only volatile)" rgroup.word 0x904C++0x1 line.word 0x0 "LANEX_DIG_TX_VMD_FSM_TX_VCM_1,Calculated values for N_FIXED and N_TRAILER." newline bitfld.word 0x0 15. "FIXED_DONE,N_FIXED Multiplication has completed. (RU - read-only volatile)" "0,1" newline bitfld.word 0x0 14. "TRA_DONE,N_TRAILER Multiplication has completed. (RU - read-only volatile)" "0,1" newline hexmask.word.byte 0x0 7.--13. 1. "N_FIXED,Value from VMD for number of fixed driver legs. (RU - read-only volatile)" newline hexmask.word.byte 0x0 0.--6. 1. "N_TRAILER,Value from VMD for number of trailer legs. (RU - read-only volatile)" group.word 0x9050++0x1 line.word 0x0 "LANEX_DIG_TX_VMD_FSM_TX_VCM_DEBUG_IN,Access the TX_ANA VMD Control Shift Register" newline hexmask.word 0x0 4.--15. 1. "RESERVED_15_4,Reserved for Future use" newline bitfld.word 0x0 3. "CONFIG_OVRD,Override the Voltage Mode Driver Configuration FSM and access the shift chain directly. (volatile and 2 reads needed to read value)" "0,1" newline bitfld.word 0x0 2. "CONFIG_LOAD,Override value for the Voltage Mode Driver Configuration FSM's config load. (volatile and 2 reads needed to read value)" "0,1" newline bitfld.word 0x0 1. "CONFIG_CLK,Override value for the Voltage Mode Driver Configuration FSM's config clk. (volatile and 2 reads needed to read value)" "0,1" newline bitfld.word 0x0 0. "CONFIG_DATA,Override value for the Voltage Mode Driver Configuration FSM's config data. (volatile and 2 reads needed to read value)" "0,1" group.word 0x9054++0x1 line.word 0x0 "LANEX_DIG_TX_LBERT_CTL,Pattern Generator controls" newline rbitfld.word 0x0 15. "RESERVED_15_15,Reserved for Future use" "0,1" newline hexmask.word 0x0 5.--14. 1. "PAT0,10 bit pattern for modes using PAT0 (5-7). Ignored for other MODEs." newline bitfld.word 0x0 4. "TRIGGER_ERR,Single shot inversion the LSB of the current symbol. Any write of a 1 to this bit will insert an error. Maintain mode and pattern from setup." "0,1" newline hexmask.word.byte 0x0 0.--3. 1. "MODE,Pattern to generate When changing modes you must change to disabled first 0 - disabled 1 - lfsr31. X^31 + X^28 + 1 2 - lfsr23. X^23 + X^18 + 1 3 - lfsr15. X^15 + X^14 + 1 4 - lfsr7. X^7 + X^6 + 1 5 - fixed word (PAT0) 6 - DC balanced word (PAT0.." group.word 0x9058++0x1 line.word 0x0 "LANEX_DIG_RX_LBERT_CTL,Pattern Matcher controls" newline hexmask.word 0x0 5.--15. 1. "RESERVED_15_5,Reserved for Future use" newline bitfld.word 0x0 4. "SYNC,Synchronize pattern matcher with incoming data A write of a one to this bit will reset the error counter and start a synchronization of the PM. There is no need to write this back to zero to run normally." "0,1" newline hexmask.word.byte 0x0 0.--3. 1. "MODE,Pattern to match When changing modes you must change to disabled first 0 - disabled 1 - lfsr31: X^31 + X^28 + 1 2 - lfsr23: X^23 + X^18 + 1 3 - lfsr15: X^15 + X^14 + 1 4 - lfsr7 : X^7 + X^6 + 1 5 - d[n] = d[n-10] 6 - d[n] = !d[n-10] 7 - d[n] =.." group.word 0x905C++0x1 line.word 0x0 "LANEX_DIG_RX_LBERT_ERR,Pattern match error counter" newline bitfld.word 0x0 15. "OV14,A read of this register or a sync of the Pattern Matcher resets the error count. If all bits of this register are 1 the error counter has saturated. If the status If active multiply COUNT by 128. If OV14=1 and COUNT=2^15-1 signals overflow of.." "0,1" newline hexmask.word 0x0 0.--14. 1. "COUNT,Current error count If OV14 field is active then multiply count by 128 to get the actual count. (volatile and 2 reads needed to read value)" group.word 0x9060++0x1 line.word 0x0 "LANEX_DIG_RX_SCOPE_CTL,Control bits for per-transciever scope portion" newline rbitfld.word 0x0 14.--15. "RESERVED_15_14,Reserved for Future use" "0,1,2,3" newline bitfld.word 0x0 12.--13. "RX_VALID_CTL,When to Start Sampling control based on rx_valid. 0 = Ignore rx_valid. 1 = Heed rx_valid. 2 = Wait for rising_edge on rx_valid." "Ignore rx_valid,Heed rx_valid,Wait for rising_edge on rx_valid,?" newline hexmask.word 0x0 3.--11. 1. "DELAY,number of cycles to skip between samples" newline bitfld.word 0x0 0.--2. "MODE,sampling mode of counters NOTE: WORD is 20 bits. 0 = off 1 = sample data every WORD*(1+DELAY) bits from the digital recovered path. 2 = sample data every WORD*(1+DELAY) + 1 bits from the digital recovered path. 3 = sample data every WORD*(1+DELAY) +.." "off,sample data every WORD*,sample data every WORD*,sample data every WORD*,sample data every WORD*,?,?,?" group.word 0x9064++0x1 line.word 0x0 "LANEX_DIG_RX_SCOPE_PHASE,Scope sampling phase." newline rbitfld.word 0x0 15. "RESERVED_15_15,Reserved for Future use" "0,1" newline hexmask.word.byte 0x0 10.--14. 1. "BASE,which bit to sample when MODE = 1 or 4" newline bitfld.word 0x0 8.--9. "SCOPE_DELAY,How many clocks to delay the analog scope_data." "0,1,2,3" newline bitfld.word 0x0 7. "SCOPE_SEL,Select Sampling Mode. 0 - Before AFE Sampling 1 - After AFE Sampling" "Before AFE Sampling,After AFE Sampling" newline bitfld.word 0x0 6. "UPDATE,Update Sampling phase. Write a 1." "0,1" newline hexmask.word.byte 0x0 0.--5. 1. "SAMPLE_PHASE,Sampling Phase" group.word 0x9068++0x1 line.word 0x0 "LANEX_DIG_RX_DPLL_FREQ,Current frequency integrator value." newline rbitfld.word 0x0 13.--15. "RESERVED_15_13,Reserved for Future use" "0,1,2,3,4,5,6,7" newline hexmask.word 0x0 1.--12. 1. "VAL,Freq is 1.526*VAL ppm from the reference When mpll_slow is set the ppm is half the eqn above (volatile and 2 reads needed to read value)" newline bitfld.word 0x0 0. "DTHR,Bits below the useful resolution (volatile and 2 reads needed to read value)" "0,1" group.word 0x906C++0x1 line.word 0x0 "LANEX_DIG_RX_CDR_CTL,Control bits for receiver in recovered domain" newline hexmask.word.byte 0x0 12.--15. 1. "DTB_SEL,select to drive various signals onto the dtb 0 - disabled 1 - pll_ana_rst pll_count from rx_pwr_ctl 2 - com_good_high/low from aligner 3 - com_bad_high/low from aligner 4 - shift_in_prog ana_odd_data from aligner 5 - low bits of XAUI align FSM.." newline bitfld.word 0x0 11. "ALWAYS_REALIGN,realign on any misaligned comma" "0,1" newline bitfld.word 0x0 10. "FAST_START,decrease startup steps by 50%" "0,1" newline bitfld.word 0x0 8.--9. "FRUG_VALUE,override value for FRUG" "0,1,2,3" newline bitfld.word 0x0 6.--7. "PHUG_VALUE,override value for PHUG" "0,1,2,3" newline bitfld.word 0x0 5. "OVRD_DPLL_GAIN,Override PHUG and FRUG values" "0,1" newline bitfld.word 0x0 4. "PHDET_POL,Reverse polarity of phase error" "0,1" newline bitfld.word 0x0 2.--3. "PHDET_EDGE,Edges to use for phase detection. 11 - Use both edges 10 - Use rising edges only 01 - Use falling edges only 00 - Ignore all edges" "Ignore all edges,Use falling edges only,?,?" newline bitfld.word 0x0 0.--1. "PHDET_EN,Enable phase detecter. top bit is odd slicers bottom is even" "0,1,2,3" rgroup.word 0x9070++0x1 line.word 0x0 "LANEX_DIG_RX_CDR_CDR_FSM_DEBUG,Current values for CDR and Adaptation FSM." newline bitfld.word 0x0 13.--15. "ADAP_RX_EQ,Equalization setting from adaptation FSM. (RU - read-only volatile)" "0,1,2,3,4,5,6,7" newline bitfld.word 0x0 10.--12. "RX_EQ_CTR,Initial centre point from equalization FSM. (RU - read-only volatile)" "0,1,2,3,4,5,6,7" newline bitfld.word 0x0 7.--9. "RX_ANA_EQ,Equalization setting to Analog. (RU - read-only volatile)" "0,1,2,3,4,5,6,7" newline bitfld.word 0x0 6. "ADAP_RX_VALID,Adaptation has completed and locked. (RU - read-only volatile)" "0,1" newline bitfld.word 0x0 5. "CDR_EN_ADAP,Adapatation loop is enabling the CDR. (RU - read-only volatile)" "0,1" newline bitfld.word 0x0 4. "CDR_EN_EQ,Equalization loop is enabling the CDR. (RU - read-only volatile)" "0,1" newline bitfld.word 0x0 3. "ALIGNED,Datapath is bit-aligned. (RU - read-only volatile)" "0,1" newline bitfld.word 0x0 2. "CDR_RX_VALID,CDR has locked to incoming data stream. (RU - read-only volatile)" "0,1" newline bitfld.word 0x0 1. "CDR_TIMEOUT,CDR has not locked to datastream and has timed-out. (RU - read-only volatile)" "0,1" newline bitfld.word 0x0 0. "CDR_EN,CDR has been enabled. (RU - read-only volatile)" "0,1" group.word 0x9074++0x1 line.word 0x0 "LANEX_DIG_RX_CDR_LOCK_VEC_OVRD,Control bits for receiver in recovered domain" newline hexmask.word.byte 0x0 11.--15. 1. "ADAP_CTR_LEVEL,Ammount of earlies that increment the adaptation counter (times 32 Default is 512). (volatile and 2 reads needed to read value)" newline bitfld.word 0x0 10. "ADAP_POLARITY,If asserted invert default adaptation adjustment for equalization. IF early decrease equalization. Normal mode is to decrease. (volatile and 2 reads needed to read value)" "0,1" newline bitfld.word 0x0 9. "LOCK_VECTOR_OVRD,Override enable for the rx_eq outputs. (volatile and 2 reads needed to read value)" "0,1" newline bitfld.word 0x0 8. "LOCK_VECTOR_EN,Override value for the locked_vector output completion. (volatile and 2 reads needed to read value)" "0,1" newline hexmask.word.byte 0x0 0.--7. 1. "LOCK_VECTOR,Override value for the locked_vector. (volatile and 2 reads needed to read value)" rgroup.word 0x9078++0x1 line.word 0x0 "LANEX_DIG_RX_CDR_LOCK_VEC,Current values for the locked vector.." newline hexmask.word.byte 0x0 12.--15. 1. "RESERVED_15_12,Reserved for Future use" newline bitfld.word 0x0 9.--11. "EQ_RX_EQ,Equalization setting from the Equalization Loop. (RU - read-only volatile)" "0,1,2,3,4,5,6,7" newline bitfld.word 0x0 8. "EQ_LOCKED_VECTOR_EN,Equalization locked vector has been filled. (RU - read-only volatile)" "0,1" newline hexmask.word.byte 0x0 0.--7. 1. "EQ_LOCKED_VECTOR,Results of equalization loop. (RU - read-only volatile)" rgroup.word 0x907C++0x1 line.word 0x0 "LANEX_DIG_RX_CDR_ADAP_FSM,Observation of adaptation FSM register." newline hexmask.word.byte 0x0 11.--15. 1. "MSTR_CTR,Master count register. (RU - read-only volatile)" newline hexmask.word.byte 0x0 7.--10. 1. "LOOP_CTR,Loop count register. (RU - read-only volatile)" newline hexmask.word.byte 0x0 3.--6. 1. "ADAP_CTR,Adaptation count register. (RU - read-only volatile)" newline bitfld.word 0x0 0.--2. "ADAP_STATE,Adaptation State. NOTE: ADAP_RESET = 3'b000 ADAP_LOCK = 3'b001 ADAP_SUFF = 3'b010 ADAP_LOOP = 3'b011 ADAP_MSTR = 3'b100 ADAP_DONE = 3'b101 (RU - read-only volatile)" "0,1,2,3,4,5,6,7" group.word 0x9080++0x1 line.word 0x0 "LANEX_ANA_RX_ATB0,ATB Control Register" newline hexmask.word.byte 0x0 8.--15. 1. "RESERVED_15_8,Reserved for Future use" newline bitfld.word 0x0 7. "EN_ATB,Enable ATB sensing and forcing on internal RX nodes" "0,1" newline bitfld.word 0x0 6. "EN_MARG,Enable margining mode in receiver; it puts EQ common mode output on atb_f_m" "0,1" newline bitfld.word 0x0 5. "EN_ATB_RM_F,Enable atb_f_p on negative-side termination resistor" "0,1" newline bitfld.word 0x0 4. "EN_ATB_RM_S,Enable atb_s_m on negative-side termination resistor" "0,1" newline bitfld.word 0x0 3. "EN_ATB_RP_F,Enable atb_f_p on positive-side termination resistor" "0,1" newline bitfld.word 0x0 2. "EN_ATB_RP_S,Enable atb_s_p on positive-side termination resistor" "0,1" newline bitfld.word 0x0 1. "EN_ATB_VOS,Put rxafe filtered outputs vo_p on atb_s_p and vo_m on atb_s_m" "0,1" newline bitfld.word 0x0 0. "EN_ATB_VOFF,Put rxafe voff_p on atb_s_p and voff_m on atb_s_m" "0,1" group.word 0x9084++0x1 line.word 0x0 "LANEX_ANA_RX_ATB1,ATB and Misc Control Register" newline hexmask.word.byte 0x0 8.--15. 1. "RESERVED_15_8,Reserved for Future use" newline bitfld.word 0x0 6.--7. "RX_DCC_IQ_OFFSET_H_4_3,Code which helps to manually tune reference voltage (r-string dac) for IQ opamp and correct input offset (rx_dcc_iq_offset_h_4_3 bit)" "0,1,2,3" newline bitfld.word 0x0 5. "EN_ATB_VLOS,Enable sensing of LOS reference voltage on atb_s_p" "0,1" newline bitfld.word 0x0 4. "EN_ATB_VRF,Enable sensing of vref_rx (RX Bias B.G. Voltage) on atb_s_p" "0,1" newline bitfld.word 0x0 3. "MEAS_GD,Enable sensing of local gd in RX; ties gd to atb_s_m" "0,1" newline bitfld.word 0x0 2. "MEAS_VP,Enable sensing of local vp in RX; ties vp to atb_s_p" "0,1" newline bitfld.word 0x0 0.--1. "RX_DCC_IQ_OFFSET_H_2_1,Code which helps to manually tune reference voltage (r-string dac) for IQ opamp and correct input offset (rx_dcc_iq_offset_h_2_1 bit)" "0,1,2,3" group.word 0x9088++0x1 line.word 0x0 "LANEX_ANA_RX_ENPWR0,RX State Control Register" newline hexmask.word.byte 0x0 8.--15. 1. "RESERVED_15_8,Reserved for Future use" newline bitfld.word 0x0 7. "CTL_RXPWRON,MUX select for AFE en to select between CTL_RXPWRON=0 rx_afe_en (External signal) or CTL_RXPWRON=1 LCL_RXPWRON" "0,1" newline bitfld.word 0x0 6. "LCL_RXPWRON,Enable/Disable RX AFE .This bit is only selected when CTL_RXPWRON = 1" "0,1" newline bitfld.word 0x0 5. "CTL_EN_LOS,MUX select for LOS en to select between CTL_EN_LOS=0 rx_los_en (External signal) or CTL_EN_LOS=1 LCL_EN_LOS" "0,1" newline bitfld.word 0x0 4. "LCL_EN_LOS,Enable/Disable LOS.This bit is only selected when CTL_EN_LOS = 1" "0,1" newline bitfld.word 0x0 3. "CTL_RXCK,MUX select for RX Clock en to select between CTL_RXCK=0 rx_clock_en (External signal) or CTL_RXCK=1 LCL_RXCK." "0,1" newline bitfld.word 0x0 2. "LCL_RXCK,Enable/Disable en_rx_clock (RX clock enable).This bit is only selected when CTL_RXCK = 1" "0,1" newline bitfld.word 0x0 1. "CTL_ACJT,MUX select for ACJTAG to select between CTL_ACJTG=0 rx_acjtg_en (External signal) or CTL_ACJTG=1 LCL_ACJT." "0,1" newline bitfld.word 0x0 0. "LCL_ACJT,Enable/Disable acjtag block This bit is only selected when CTL_ACJTG = 1" "0,1" group.word 0x908C++0x1 line.word 0x0 "LANEX_ANA_RX_PMIX_PHASE,Phase select Value" newline hexmask.word.byte 0x0 8.--15. 1. "RESERVED_15_8,Reserved for Future use" newline hexmask.word.byte 0x0 0.--7. 1. "PHASE,Write to bits 8 to 1 of the phase select register in the phase mixer through the CDR (USER2 volatile - read-write volatile and custom)" group.word 0x9090++0x1 line.word 0x0 "LANEX_ANA_RX_ENPWR1,Additional RX State Control Register" newline hexmask.word.byte 0x0 8.--15. 1. "RESERVED_15_8,Reserved for Future use" newline bitfld.word 0x0 7. "CTL_PHASE_REG_RST,MUX select for Phase Register Reset to select between CTL_PHASE_REG_RST=0 rx_phase_reg_rst (External signal) or CTL_PHASE_REG_RST=1 LCL_PHASE_REG_RST" "0,1" newline bitfld.word 0x0 6. "LCL_PHASE_REG_RST,Reset phase register.This bit is only selected when CTL_PHASE_REG_RST= 1" "0,1" newline bitfld.word 0x0 5. "CTL_BST,MUX select for AFE Boost to select between CTL_BST=0 rx_aeq[2:0] (External signal) or CTL_BST=1 LCL_BST" "0,1" newline bitfld.word 0x0 2.--4. "LCL_BST,RX Boost (equalization) Value" "0,1,2,3,4,5,6,7" newline bitfld.word 0x0 1. "CTL_RXTERM,MUX select for RX Term enable to select between CTL_RXTERM=0 rx_term_en (External signal) or CTL_RXTERM=1 LCL_RXTERM" "0,1" newline bitfld.word 0x0 0. "LCL_RXTERM,Enable/disable RX termination when CTL_RXTERM = 1" "0,1" group.word 0x9094++0x1 line.word 0x0 "LANEX_ANA_RX_ENPWR2,Yet another RX State Control Register" newline hexmask.word.byte 0x0 8.--15. 1. "RESERVED_15_8,Reserved for Future use" newline bitfld.word 0x0 7. "EN_RXPMIX_TST,Enable XOR gate to test linearity of RX phase mixer using atb_s_p and atb_s_m" "0,1" newline bitfld.word 0x0 6. "EN_RXPMIX_VPMIX,Put vreg_pmix on atb_s_p" "0,1" newline bitfld.word 0x0 5. "EN_RXPMIX_VRX,Put vreg_rx on atb_s_p" "0,1" newline bitfld.word 0x0 4. "RX_DCC_IQ_OFFSET_H_0,Code which helps to manually tune reference voltage (r-string dac) for IQ opamp and correct input offset (rx_dcc_iq_offset_h_0 bit)" "0,1" newline bitfld.word 0x0 3. "EN_RXPMIX_FRC_VPMIX_H,Connecting vbg_in to vbg (in case of 0) or to atb_s_m_int (in case of 1)" "0,1" newline bitfld.word 0x0 2. "RX_SCOPE_ATB_2,Put XOR of RX SCOPE PMIX input and output on atb_s_p" "0,1" newline bitfld.word 0x0 1. "RX_SCOPE_ATB_1,Put RX SCOPE regulated VP on atb_s_p" "0,1" newline bitfld.word 0x0 0. "RX_SCOPE_ATB_0,Have RX SCOPE reference for regulator use atb_f_p as a reference instead of VP/VBG" "0,1" group.word 0x9098++0x1 line.word 0x0 "LANEX_ANA_RX_SCOPE_VDCC,RX Scope controls and clock DCC control voltage probe" newline hexmask.word.byte 0x0 8.--15. 1. "RESERVED_15_8,Reserved for Future use" newline bitfld.word 0x0 6.--7. "VDCC,Probe DCC control voltage" "0,1,2,3" newline bitfld.word 0x0 5. "NC5,Reserved" "0,1" newline bitfld.word 0x0 4. "RX_SCOPE_SLEW,Set high for low RX clock frqeuencies (625MHz) for RX Scope to work correctly" "0,1" newline bitfld.word 0x0 3. "RX_SCOPE_FDIV20,Divide scope output clock by 20 instead of 10" "0,1" newline bitfld.word 0x0 2. "RX_LOS_LFPS_EN_BIT_2,In case of rx_los_lfps_en_cntrl = 1/0 reg_rx_los_lfps_en/rx_ana_los_lfps_en signal directly applied to rx_los circuit through I101 multiplexer." "0,1" newline bitfld.word 0x0 1. "RX_DCC_IQ_OFFSET_EN_H,Select ref voltage for IQ opamp from testmode part (in case of 1) or from ordinary resistive dividers (in case of 0)." "0,1" newline bitfld.word 0x0 0. "RX_LOS_LFPS_EN,Enables the RX LOS LFPS mode use when you want to detect incoming LFPS signals USB3.0" "0,1" group.word 0x90AC++0x1 line.word 0x0 "LANEX_ANA_TX_TXDRV_CNTRL,Register 3" newline hexmask.word.byte 0x0 8.--15. 1. "RESERVED_15_8,Reserved for Future use" newline bitfld.word 0x0 7. "PULL_DN_REG,register bit that causes the calibrated TX bits to pull down in a common mode fashion. If pull_dn_reg and tx_pull_up are both high then pull_dn_reg wins" "0,1" newline bitfld.word 0x0 6. "PULL_UP_REG,Register override for tx_pull_up. Used when ovrd_pull_up is HIGH causes calibrated TX bits to pull up in a common mode fashion unless pull_dn_reg is HIGH" "0,1" newline bitfld.word 0x0 5. "OVRD_PULL_UP,Selects local value of pull_up_reg instead of tx_pull_up" "0,1" newline bitfld.word 0x0 4. "VCM_HOLD_REG,Register override for tx_vcm_hold. Used when ovrd_vcm_hold is HIGH controls the TX common mode hold circuitry" "0,1" newline bitfld.word 0x0 3. "OVRD_VCM_HOLD,Selects local value of vcm_hold_reg instead of tx_vcm_hold to control state of TX common mode hold circuitry" "0,1" newline bitfld.word 0x0 2. "REFGEN_PWRDN_OVRD_N,Set LOW for TX regulator not to turn on when RX clock is enabled. Default is for TX regulator to turn on when RX or TX clock is enabled" "0,1" newline bitfld.word 0x0 1. "NOCONN_1,Reserved" "0,1" newline bitfld.word 0x0 0. "NOCONN_0,Reserved" "0,1" group.word 0x90B0++0x1 line.word 0x0 "LANEX_ANA_TX_POWER_CTL,Register 4" newline hexmask.word.byte 0x0 8.--15. 1. "RESERVED_15_8,Reserved for Future use" newline bitfld.word 0x0 7. "OVRD_EN,Enables local overrides for all signals in this register except for TX_DIV_CLK_EN which doesn't need this signal" "0,1" newline bitfld.word 0x0 6. "SERIAL_EN_REG,Forces state of tx_serial_en when OVRD_EN is 1" "0,1" newline bitfld.word 0x0 5. "CLK_EN_REG,Forces state of tx_clk_en when OVRD_EN is 1" "0,1" newline bitfld.word 0x0 4. "DATA_EN_REG,Forces state of tx_data_en when OVRD_EN is HIGH" "0,1" newline bitfld.word 0x0 3. "REFGEN_EN_REG,Register override value for tx_refgen_en. Controls the TX regulator biasing circuitry and the rxdetect comparators when OVRD_EN is HIGH. This function may be overridden by the state of refgen_pwdn_reg" "0,1" newline bitfld.word 0x0 2. "TX_DIV_CLK_EN,Enables the div clock that goes from the TX to the undersampler more appropriately called tx_sampler_clk_en this clock comes after the optional divide by 2 or 4 tx_clk_en must be HIGH to get a clock out" "0,1" newline bitfld.word 0x0 1. "REFGEN_PDN_REG,Register override for refgen pwdn. Used when OVRD_EN is HIGH. Controls the TX regulator biasing circuitry and the rxdetect comparators when OVRD_EN is HIGH" "0,1" newline bitfld.word 0x0 0. "LFPS_HIGH_PRIORITY,When this is set high LFPS priority becomes higher than tx_data" "0,1" group.word 0x90B4++0x1 line.word 0x0 "LANEX_ANA_TX_ALT_BLOCK,Register 5" newline hexmask.word.byte 0x0 8.--15. 1. "RESERVED_15_8,Reserved for Future use" newline bitfld.word 0x0 7. "EN_ALT_BUS,Enables the TX for alt bus mode powers up the TX regulator biasing circuitry and the rxdetect comparators. Needed if manually running the alt bus features" "0,1" newline bitfld.word 0x0 5.--6. "DRV_SOURCE_REG,Forces state of tx_data_source when OVRD_ALT_BUS is HIGH. 00 = serializer data or alt oscillator vp/vph/vphreg/vptx if selected 01 = jtag data differential 10 = LFPS oscillator differential 11 = jtag data common mode drive for test" "serializer data or alt oscillator..,jtag data differential,?,?" newline bitfld.word 0x0 4. "JTAG_DATA_REG,Forces state of jtag_data when OVRD_ALT_BUS is HIGH" "0,1" newline bitfld.word 0x0 1.--3. "TX_RINGO_CNTRL,Enables and connects the various test oscillators to the transmit pins must set drv_source_reg bus correctly. 0XX = All oscillators are disabled 100 = HV oscillator enabled 101 = SVT oscillator enabled 110 = LVT oscillator enabled 111.." "0,1,2,3,4,5,6,7" newline bitfld.word 0x0 0. "OVRD_ALT_BUS,Enables local overrides for alt-bus control signals: DRV_SOURCE_REG and JTAG_DATA_REG" "0,1" group.word 0x90B8++0x1 line.word 0x0 "LANEX_ANA_TX_ALT_AND_LOOPBACK,Register 6" newline hexmask.word.byte 0x0 8.--15. 1. "RESERVED_15_8,Reserved for Future use" newline bitfld.word 0x0 7. "OVRD_TX_LB,Enables the override of the tx_lb_en" "0,1" newline bitfld.word 0x0 6. "TX_LB_EN_REG,Forces state of tx_lb_en when OVRD_TX_LB is enabled" "0,1" newline bitfld.word 0x0 5. "ATB_VPTX,Connects vptx to atb_s_p and gd to atb_s_m" "0,1" newline bitfld.word 0x0 4. "ATB_VREG_TX,Connects TX regulator input reference to atb_s_p and gd to atb_s_m" "0,1" newline bitfld.word 0x0 3. "ATB_VDCCP,Connects vdcc_p to atb_s_p" "0,1" newline bitfld.word 0x0 2. "ATB_VDCCM,Connects vdcc_m to atb_s_m" "0,1" newline bitfld.word 0x0 1. "NOCONN_01,Reserved" "0,1" newline bitfld.word 0x0 0. "SELECT_PMIX_CLK,select pmix_clk for TX clock for ATE test mode" "0,1" group.word 0x90BC++0x1 line.word 0x0 "LANEX_ANA_TX_TX_ATB_REG,Register 7" newline hexmask.word.byte 0x0 8.--15. 1. "RESERVED_15_8,Reserved for Future use" newline bitfld.word 0x0 7. "ATB_PBIAS,Connect real pmos_bias voltage for TX PMOS driver pull up path to atb_s_p and local ground at the pmos_bias block to atb_s_m" "0,1" newline bitfld.word 0x0 6. "ATB_VCM_REP,Connect common mode replica voltage in pmos_bias block to atb_s_p and local ground to atb_s_m" "0,1" newline bitfld.word 0x0 5. "ATB_RXDETREF,Connect RX detect block reference voltage to atb_s_p and local ground to atb_s_m" "0,1" newline bitfld.word 0x0 4. "ATB_TXFP,Connect tx_p to atb_f_p" "0,1" newline bitfld.word 0x0 3. "ATB_TXFM,Connect tx_m to atb_f_m" "0,1" newline bitfld.word 0x0 2. "ATB_TXSP,Connect tx_p to atb_s_p" "0,1" newline bitfld.word 0x0 1. "ATB_TXSM,Connect tx_m to atb_s_m" "0,1" newline bitfld.word 0x0 0. "ATB_VCM,Connect tx_p/tx_m common mode voltage onto atb_s_p and local ground onto atb_s_m" "0,1" group.word 0x90C0++0x1 line.word 0x0 "LANEX_ANA_TX_TX_BOOST,Register 8" newline hexmask.word.byte 0x0 8.--15. 1. "RESERVED_15_8,Reserved for Future use" newline bitfld.word 0x0 7. "OVRD_VBOOST_EN,Enables the overrides on VBOOST_EN_REG" "0,1" newline bitfld.word 0x0 6. "VBOOST_EN_REG,Forces state of tx_vboost_en when OVRD_VBOOST_EN is HIGH" "0,1" newline bitfld.word 0x0 5. "VCON_EN_N,Forces state of vcon_en_n" "0,1" newline bitfld.word 0x0 4. "ATB_VBOOST,Connects vboost to atb_s_p and local ground to Atb_s_m" "0,1" newline bitfld.word 0x0 3. "ATB_VCMBOOST,Connects vcmboost to atb_s_p and local ground to atb_s_m." "0,1" newline bitfld.word 0x0 2. "ATB_F_VBOOST_REF,Enables forcing of tx_vboost_vref through atb_f_p from external" "0,1" newline bitfld.word 0x0 1. "OVRD_VREG_DECAP,Enables override of vreg_decap_en_n signal" "0,1" newline bitfld.word 0x0 0. "VREG_DECAP_EN_N_REG,Forces state of vreg_decap_en_n control signal. Controls whether extra decoupling is switched in for TX regulator output." "0,1" group.word 0x9100++0x1 line.word 0x0 "LANEX_DIG_RX_CDR_FSM_INIT_CTL,Control bits for CDR init phase portion" newline hexmask.word.byte 0x0 9.--15. 1. "RESERVED_15_9,Reserved for Future use" newline bitfld.word 0x0 8. "INIT_CNT_OVRD,Active high override enable bit to select the override INIT_CNT register 0 = Disabled 1 = Enabled" "Disabled,Enabled" newline hexmask.word.byte 0x0 0.--7. 1. "INIT_CNT,Override value for CDR Init Phase" group.word 0x9104++0x1 line.word 0x0 "LANEX_DIG_RX_CDR_FSM_TRACK_CTL,Control bits for CDR track phase portion" newline hexmask.word.byte 0x0 9.--15. 1. "RESERVED_15_9,Reserved for Future use" newline bitfld.word 0x0 8. "TRACK_CNT_OVRD,Active high override enable bit to select the override TRACK_CNT register 0 = Disabled 1 = Enabled" "Disabled,Enabled" newline hexmask.word.byte 0x0 0.--7. 1. "TRACK_CNT,Override value for CDR Track Phase" group.word 0x9108++0x1 line.word 0x0 "LANEX_DIG_RX_CDR_FSM_LOCK_CTL,Control bits for CDR lock phase portion" newline hexmask.word.byte 0x0 9.--15. 1. "RESERVED_15_9,Reserved for Future use" newline bitfld.word 0x0 8. "LOCK_CNT_OVRD,Active high override enable bit to select the override LOCK_CNT register 0 = Disabled 1 = Enabled" "Disabled,Enabled" newline hexmask.word.byte 0x0 0.--7. 1. "LOCK_CNT,Override value for CDR Lock Phase" repeat 9. (list 0x0 0x1 0x2 0x3 0x4 0x8 0x9 0xB 0xC )(list 0x0 0x4 0x8 0xC 0x10 0x20 0x24 0x2C 0x30 ) rgroup.word ($2+0xA000)++0x1 line.word 0x0 "PORTX_STAT_RO_$1,Status Register 0" newline hexmask.word 0x0 4.--15. 1. "RESERVED_15_4,Reserved for Future use" newline bitfld.word 0x0 3. "PLL_LOCK,analog PLL Lock Signal" "0,1" newline bitfld.word 0x0 2. "RX_SQUELCH,analog RX Squelch Signal" "0,1" newline bitfld.word 0x0 1. "RESERVED_1,Reserved" "0,1" newline bitfld.word 0x0 0. "RESERVED_0,Reserved" "0,1" repeat.end repeat 7. (list 0x5 0x6 0x7 0xA 0xD 0xE 0xF )(list 0x0 0x4 0x8 0x14 0x20 0x24 0x28 ) rgroup.word ($2+0xA014)++0x1 line.word 0x0 "PORTX_STAT_RO_$1,Status Register 5" newline hexmask.word 0x0 4.--15. 1. "RESERVED_15_4,Reserved for Future use" newline hexmask.word.byte 0x0 0.--3. 1. "DATAOUT,UTMI+ Output DATAOUT" repeat.end repeat 2. (list 0x0 0x6 )(list 0x0 0x18 ) group.word ($2+0xA040)++0x1 line.word 0x0 "PORTX_OVRD_RW_$1,Override Register 0" newline hexmask.word.byte 0x0 8.--15. 1. "RESERVED_15_8,Reserved for Future use" newline hexmask.word.byte 0x0 4.--7. 1. "OVERRD_ADDR_OVRD_EN,Override Enable for overrd_addr [7:4]" newline hexmask.word.byte 0x0 0.--3. 1. "OVERRD_ADDR,Analog Test Control Override Address [3:0]" repeat.end repeat 10. (list 0x1 0x2 0x3 0x4 0x8 0x9 0xA 0xB 0xE 0xF )(list 0x0 0x4 0x8 0xC 0x1C 0x20 0x24 0x28 0x34 0x38 ) group.word ($2+0xA044)++0x1 line.word 0x0 "PORTX_OVRD_RW_$1,Override Register 1" newline hexmask.word.byte 0x0 8.--15. 1. "RESERVED_15_8,Reserved for Future use" newline bitfld.word 0x0 7. "VBUS_VALID_PU_OVRD_EN,Override Enable for vbus_valid_pu" "0,1" newline bitfld.word 0x0 6. "OTG_PU_OVRD_EN,Override Enable for otg_pu" "0,1" newline bitfld.word 0x0 5. "TX_VREF_VREG_PU_OVRD_EN,Override Enable for tx_vref_vreg_pu" "0,1" newline bitfld.word 0x0 4. "SQRX_PU_OVRD_EN,Override Enable for sqrx_pu" "0,1" newline bitfld.word 0x0 3. "VBUS_VALID_PU,DRVVBUS Input" "0,1" newline bitfld.word 0x0 2. "OTG_PU,OTGDISABLE Input" "0,1" newline bitfld.word 0x0 1. "TX_VREF_VREG_PU,TX hs_driver Comparator Power Up" "0,1" newline bitfld.word 0x0 0. "SQRX_PU,RX squelch Comparator Power Up" "0,1" repeat.end group.word 0xA054++0x1 line.word 0x0 "PORTX_OVRD_RW_5,Override Register 5" newline hexmask.word.byte 0x0 8.--15. 1. "RESERVED_15_8,Reserved for Future use" newline bitfld.word 0x0 6.--7. "XO_CLK_DIV_OVRD_EN,Override Enable for xo_clk_div" "0,1,2,3" newline bitfld.word 0x0 5. "MSTR_OVERRD_BIT_OVRD_EN,Override Enable for mstr_overrd_bit" "0,1" newline bitfld.word 0x0 4. "OVERRD_ADDR_4_OVRD_EN,Override Enable for overrd_addr_4" "0,1" newline bitfld.word 0x0 2.--3. "XO_CLK_DIV,setting reference clock division" "0,1,2,3" newline bitfld.word 0x0 1. "MSTR_OVERRD_BIT,Analog Test Control Master Override" "0,1" newline bitfld.word 0x0 0. "OVERRD_ADDR_4,Analog Test Control Override Address [4]" "0,1" group.word 0xA05C++0x1 line.word 0x0 "PORTX_OVRD_RW_7,Override Register 7" newline hexmask.word.byte 0x0 8.--15. 1. "RESERVED_15_8,Reserved for Future use" newline bitfld.word 0x0 7. "TX_LS_EN_OVRD_EN,Override Enable for tx_ls_en" "0,1" newline bitfld.word 0x0 4.--6. "PWR_SEQ_CLK_DIV_OVRD_EN,Override Enable for pwr_seq_clk_div" "0,1,2,3,4,5,6,7" newline bitfld.word 0x0 3. "TX_LS_EN,TX LS Enable" "0,1" newline bitfld.word 0x0 0.--2. "PWR_SEQ_CLK_DIV,setting power_sequence division" "0,1,2,3,4,5,6,7" group.word 0xA070++0x1 line.word 0x0 "PORTX_OVRD_RW_12,Override Register 12" newline hexmask.word.byte 0x0 8.--15. 1. "RESERVED_15_8,Reserved for Future use" newline bitfld.word 0x0 7. "RES_ACK_OUT_OVRD_EN,Override Enable for res_ack_out" "0,1" newline bitfld.word 0x0 5.--6. "PLL_CLK_DIV_OVRD_EN,Override Enable for pll_clk_div" "0,1,2,3" newline bitfld.word 0x0 4. "PLL_RESET_OVRD_EN,Override Enable for pll_reset" "0,1" newline bitfld.word 0x0 3. "RES_ACK_OUT,Ack resistor tune external requirement" "0,1" newline bitfld.word 0x0 1.--2. "PLL_CLK_DIV,setting MPLL division" "0,1,2,3" newline bitfld.word 0x0 0. "PLL_RESET,MPLL gear_shift" "0,1" group.word 0xA074++0x1 line.word 0x0 "PORTX_OVRD_RW_13,Override Register 13" newline hexmask.word.byte 0x0 8.--15. 1. "RESERVED_15_8,Reserved for Future use" newline bitfld.word 0x0 7. "BIST_MODE_OVRD_EN,Override Enable for bist_mode" "0,1" newline bitfld.word 0x0 6. "TEST_PKT_RPT_OVRD_EN,Override Enable for test_pkt_rpt" "0,1" newline bitfld.word 0x0 4.--5. "XO_CLK_SEL_OVRD_EN,Override Enable for xo_clk_sel" "0,1,2,3" newline bitfld.word 0x0 3. "BIST_MODE,BIST Mode" "0,1" newline bitfld.word 0x0 2. "TEST_PKT_RPT,BIST Test Packet Mode" "0,1" newline bitfld.word 0x0 0.--1. "XO_CLK_SEL,Reference Clock Selection" "0,1,2,3" tree.end tree "USB_PHY2_NCR" base ad:0xF1290000 group.long 0x0++0x13 line.long 0x0 "CTRL_0,CTRL_0" bitfld.long 0x0 31. "TEST_BURNIN,All Circuits Activator" "0,1" bitfld.long 0x0 28.--30. "TX_VBOOST_LVL,TX Voltage Boost Level Sets the boosted transmit launch amplitude (mVppd)." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 25.--27. "SSC_RANGE,Spread Spectrum Clock Range Selects the range of spread spectrum modulation when ssc_en is asserted and the PHY is spreading the high-speed transmit clocks. Applies a fixed offset to the phase accumulator." "0,1,2,3,4,5,6,7" bitfld.long 0x0 24. "SSC_EN,Spread Spectrum Enable Enables spread spectrum clock production (0.5% down-spread at ~ 31.5 KHz) in the USB 3.0 femtoPHY. Set this signal to 1'b1." "0,1" newline bitfld.long 0x0 23. "RTUNE_REQ,Resistor Tune Request Assertion triggers a resistor tune request (if one is not already in progress). When this signal is asserted rtune_ack goes high until calibration of the termination impedances is complete. Note that termination.." "0,1" bitfld.long 0x0 22. "REF_USE_XO,Use External Crystal Oscillator" "0,1" newline bitfld.long 0x0 21. "REF_XO_EN,Crystal Oscillator Always On Enable" "0,1" bitfld.long 0x0 20. "REF_REPEAT_CLK_EN,Clock Repeater Buffer Enable" "0,1" newline bitfld.long 0x0 19. "REF_CLKDIV2,Input Reference Clock Divider Control If the input reference clock frequency is greater than 100 MHz this signal must be asserted. The reference clock frequency is then divided by 2 to keep it in the range required by the MPLL. When this.." "0,1" bitfld.long 0x0 18. "REF_USE_PAD,Select Reference Clock Connected to ref_pad_clk_\{p m\} When asserted selects the external ref_pad_clk_\{p m\} inputs as the reference clock source. When ref_use_pad is de-asserted ref_alt_clk_\{p m\} are selected for an on-chip reference.." "0,1" newline bitfld.long 0x0 17. "REF_SSP_EN,Reference Clock Enable for SS function. Enables the reference clock to the prescaler. The ref_ssp_en signal must remain de-asserted until the reference clock is running at the appropriate frequency at which point ref_ssp_en can be asserted." "0,1" hexmask.long.word 0x0 8.--16. 1. "SSC_REF_CLK_SEL,Spread Spectrum Reference Clock Shifting Enables non-standard oscillator frequencies to generate targeted MPLL output rates. Input corresponds to frequency-synthesis coefficient. ssc_ref_clk_sel[8:6] = modulous -1.." newline bitfld.long 0x0 7. "ALT_CLK_EN,Alternate Clock Enable Enables the ref_pcs_clk and ref_pipe_pclk output clocks (if necessary powers up the MPLL)." "0,1" newline bitfld.long 0x0 2. "PIPE_RESET_N,PIPE_RESET_N" "0,1" bitfld.long 0x0 1. "PORTRESET,When asserted this customer-specific signal resets the corresponding port's USB2.0 transmit and receive logic without disabling the clocks within the USB 3.0 femtoPHY. 1: The transmit and receive finite state machines (FSMs) are reset and.." "The transmit and receive FSMs are operational,The transmit and receive finite state machines" newline bitfld.long 0x0 0. "PHY_RESET,Core and State Machine Reset Resets the core and all state machines including the JTAG interface with the exception of the reference clock buffer. Asserting phy_reset triggers the assertion of the tx<#>_reset and rx<#>_reset signals." "0,1" line.long 0x4 "CTRL_1,CTRL_1" bitfld.long 0x4 29.--31. "COMPDISTUNE0,Disconnect Threshold Adjustment Adjusts the voltage level for the threshold used to detect a disconnect event at the host. To enable tuning at the board level connect this bus to a register. 111: + 4.5% 110: + 3% 101: + 1.5%.." "0,1,2,3,4,5,6,7" bitfld.long 0x4 26.--28. "LOS_BIAS,Loss-of-Signal Detector Threshold Level Control Sets the LOS detection threshold level. To enable tuning at the board level connect this bus to a register. 111: 135 mV 110: 120 mV 101: 105 mV 100: 90 mV 011: 75 mV 010:.." "Invalid,?,?,?,?,?,?,?" newline hexmask.long.byte 0x4 21.--25. 1. "LOS_LEVEL,Loss-of-Signal Detector Sensitivity Level Control" bitfld.long 0x4 20. "TEST_POWERDOWN_SSP,SS Function Circuits Power-Down Control Powers down all SS function circuitry in the PHY for IDDQ testing." "0,1" newline bitfld.long 0x4 19. "TEST_POWERDOWN_HSP,HS Function Circuits Power-Down Control Powers down all HS function circuitry in the PHY for IDDQ testing. Before asserting this signal ensure that VDATSRCENB<#> VDATDETENB<#> DCDENB<#> BYPASSSEL<#> and test_burnin are set to 1'b0." "0,1" hexmask.long.byte 0x4 13.--18. 1. "FSEL,Selects the reference clock frequency used for both SS and HS operations. The value for fsel combined with the other clock and enable signals determine the clock frequency used for SS and HS operations and if a shared or separate reference clock is.." newline hexmask.long.byte 0x4 8.--12. 1. "ACJT_LEVEL,1149.6 Receiver Sensitivity Level Control Selects the sensitivity level for the 1149.6 receiver for AC JTAG. Set the level based on the amplitude of the incoming Step during AC JTAG boundary scan testing." bitfld.long 0x4 7. "MPLL_REFSSC_CLK_EN,Double-Word Clock Enable" "0,1" newline hexmask.long.byte 0x4 0.--6. 1. "MPLL_MULTIPLIER,MPLL Frequency Multiplier Control Multiplies the reference clock to a frequency suitable for intended operating speed." line.long 0x8 "CTRL_2,CTRL_2" bitfld.long 0x8 31. "CHRGSEL0,Battery Charging Source Select Determines whether current is sourced onto or sunk from DP<#> or DM<#>. 1: Data source voltage (VDAT_SRC) is sourced onto DM<#> and sunk from DP<#>. 0: Data source voltage (VDAT_SRC) is sourced onto DP<#>.." "Data source voltage,Data source voltage" bitfld.long 0x8 30. "LANE0_TX2RX_LOOPBK,Loopback. When this signal is asserted data from the transmit predriver is looped back to the receive slicers. LOS is bypassed and based on the tx0_en input so that rx0_los = !tx0_data_en." "0,1" newline bitfld.long 0x8 29. "LANE0_EXT_PCLK_REQ,External PIPE Clock Enable Request. When asserted this signal enables the pipeX_pclk output regardless of power state (along with the associated increase in power consumption). You can use this input to enable pipeX_pclk in the P3.." "0,1" hexmask.long.byte 0x8 23.--28. 1. "PCS_TX_DEEMPH_6DB,TX De-Emphasis at 6 dB This static value sets the TX driver de-emphasis value when pipeP_tx_deemph[1:0] is set to 2'b10 (according to the PIPE3 specification). This bus is provided for completeness and as a second potential launch.." newline hexmask.long.byte 0x8 17.--22. 1. "PCS_TX_DEEMPH_3P5DB,TX De-Emphasis at 3.5 dB This static value sets the TX driver de-emphasis value when pipeX_tx_deemph[1:0] is set to 2'b01 (according to the PIPE3 specification). To enable tuning at the board level for RX eye compliance connect this.." hexmask.long.word 0x8 7.--16. 1. "PCS_RX_LOS_MASK_VAL,Configurable Loss-of-Signal Mask Width Sets the number of reference clock cycles to mask the incoming LFPS in U3 and U2 states. Masks the incoming LFPS for the number of reference clock cycles equal to the value of.." newline hexmask.long.byte 0x8 0.--6. 1. "PCS_TX_SWING_FULL,TX Amplitude (Full Swing Mode) This static value sets the launch amplitude of the transmitter. To enable tuning at the board level for RX eye compliance connect this signal to a register." line.long 0xC "CTRL_3,CTRL_3" bitfld.long 0xC 31. "VATESTENB,Analog Test Pin Select Enables analog test voltages to be placed on the ID<#> pin. 1: Analog test voltages can be viewed or applied on ID<#>. 0: Analog test voltages cannot be viewed or applied on ID<#>." "Analog test voltages cannot be viewed or applied..,Analog test voltages can be viewed or applied on.." bitfld.long 0xC 28.--30. "SQRXTUNE0,Adjusts the voltage level for the threshold used to detect valid high-speed data." "0,1,2,3,4,5,6,7" newline bitfld.long 0xC 27. "RX0LOSLFPSEN,Enables the RX LOS LFPS mode use when you want to detect incoming LFPS signals USB3.0" "0,1" bitfld.long 0xC 26. "RETENABLEN,Lowered Digital Supply Indicator." "0,1" newline bitfld.long 0xC 24.--25. "REFCLKSEL,Reference Clock Select for PLL Block" "0,1,2,3" bitfld.long 0xC 21.--23. "OTGTUNE0,VBUS Valid Threshold Adjustment This bus adjusts the voltage level for the VBUS<#> valid threshold. To enable tuning at the board level connect this bus to a register. 111: + 9% 110: + 6% 101: + 3% 100: 0 (default) 011: - 3%.." "0,1,2,3,4,5,6,7" newline bitfld.long 0xC 20. "OTGDISABLE0,OTG Block Disable This controller signal powers down the OTG block which disables the VBUS Valid and Session End comparators. The Session Valid comparator (the output of which is used to enable the pull-up resistor on DP<#> in Device mode).." "OTG block is powered up,OTG block is powered down" bitfld.long 0xC 19. "LOOPBACKENB0,Loopback Test Enable This controller signal places the USB 3.0 femtoPHY in HS Loopback mode which concurrently enables the HS receive and transmit logic. 1: During HS data transmission the HS receive logic is enabled. 0: During HS.." "During HS data transmission,During HS data transmission" newline bitfld.long 0xC 18. "HSXCVREXTCTL0,HS Transceiver Asynchronous Control. This signal asynchronously selects the HS transceiver TX/RX path and can be used with the bypass signals to perform proprietary tests on the HS TX / RX paths. (For information about the bypass signals.." "FS TX/RX path is selected,HS TX/RX path is selected" bitfld.long 0xC 16.--17. "CHRGSRCPUENB0,Charger Source Pull-Up Enable." "0,1,2,3" newline bitfld.long 0xC 15. "AUTORSMENB0,AUTORSMENB0" "0,1" bitfld.long 0xC 14. "ATERESET,Reset Input from Automatic Test Equipment When the USB 3.0 femtoPHY is powered up (not in Suspend or Sleep mode) an automatic tester can use this test signal to disable PHYCLOCK<#> and FREECLK then re-enable them with an aligned phase. 1:.." "PHYCLOCK<#> and FREECLK outputs are available..,PHYCLOCK<#> and FREECLK outputs are disabled" newline bitfld.long 0xC 13. "FSSE0EXT0,USB 1.1 SE0 Generation This controller signal sets the USB (2.0) to an SE0 state. This signal is valid only if FSXCVROWNER<#> is set to 1'b1 and TXENABLEN<#> is set to 1'b0. 1: D+ and D- lines are driven to an SE0 state. 0: D+ and D-.." "D+ and D,D+ and D" bitfld.long 0xC 12. "FSDATAEXT0,USB 1.1 Transmit Data This controller signal sets the USB (2.0) to either a J or K state. This signal is valid only if FSXCVROWNER<#> is set to 1'b1 TXENABLEN<#> is set to 1'b0 and FSSE0EXT<#> is set to 1'b0. 1: D+ and D- lines are.." "D+ and D,D+ and D" newline bitfld.long 0xC 11. "TXENABLEN0,USB 1.1 Data Enable This controller signal enables the FSDATAEXT<#> and FSSE0EXT<#> inputs. TXENABLEN<#> is valid only when the FSXCVROWNER<#> signal is set to 1'b1. 1: FSDATAEXT<#> and FSSE0EXT<#> are disabled. 0: FSDATAEXT<#> and.." "FSDATAEXT<#> and FSSE0EXT<#> are enabled,FSDATAEXT<#> and FSSE0EXT<#> are disabled" bitfld.long 0xC 10. "TXBITSTUFFENH0,High-Byte Transmit Bit-Stuffing Enable This controller signal controls bit stuffing on DATAINH<#>[7:0] when OPMODE<#>[1:0] = 2'b11. 1: Bit stuffing is enabled. 0: Bit stuffing is disabled." "Bit stuffing is disabled,Bit stuffing is enabled" newline bitfld.long 0xC 9. "TXBITSTUFFEN0,Low-Byte Transmit Bit-Stuffing Enable This controller signal controls bit stuffing on DATAIN<#>[7:0] when OPMODE<#>[1:0] = 2'b11. 1: Bit stuffing is enabled. 0: Bit stuffing is disabled." "Bit stuffing is disabled,Bit stuffing is enabled" bitfld.long 0xC 8. "IDPULLUP0,Analog ID Input Sample Enable This controller signal controls ID<#> line sampling. 1: ID<#> pin sampling is enabled and the IDDIG0 output is valid. 0: ID<#> pin sampling is disabled and the IDDIG0 output is not valid." "ID<#> pin sampling is disabled,ID<#> pin sampling is enabled" newline bitfld.long 0xC 7. "VDATSRCENB0,Battery Charging Sourcing Select Enables or disables sourcing for battery charging. 1: Data source voltage (VDAT_SRC) is enabled. 0: Data source voltage (VDAT_SRC) is disabled. During USB 3.0 femtoPHY normal operation set this signal.." "Data source voltage,Data source voltage" bitfld.long 0xC 6. "VDATDETENB0,Battery Charging Attach/Connect Detection Enable Enables or disables attach/connect detection. 1: Data detect voltage (CHG_DET) is enabled. 0: Data detect voltage (CHG_DET) is disabled. During USB 3.0 femtoPHY normal operation set.." "Data detect voltage,Data detect voltage" newline bitfld.long 0xC 5. "DCDENB0,Data Contact Detection Enable. Enables current sourcing on the D+ line. For special applications the IDP_SRC control and the RDM_DWN control are separated. For standard DCD operation in accordance with the Battery Charger v1.2 specification.." "IDP_SRC current is disabled,IDP_SRC current is sourced onto DP<#>" hexmask.long.byte 0xC 0.--4. 1. "LANE0_TX_TERM_OFFSET,Transmitter Termination Offset" line.long 0x10 "CTRL_4,CTRL_4" bitfld.long 0x10 31. "REF_CLK_SW_32K,REF_CLK switch to 32K" "0,1" bitfld.long 0x10 28.--30. "CR_CKDIV,CR clock div" "0,1,2,3,4,5,6,7" newline bitfld.long 0x10 27. "CR_MODE,CR mode" "0,1" bitfld.long 0x10 26. "COMMONONN,Common Block Power-Down Control Controls the power-down signals in the PLL block when the USB 3.0 femtoPHY is in Suspend or Sleep mode. 1: In Suspend or Sleep mode the PLL block is powered down. 0: In Suspend or Sleep mode the PLL.." "In Suspend or Sleep mode,In Suspend or Sleep mode" newline bitfld.long 0x10 25. "BYPASSSEL0,Transmitter Digital Bypass Select Enables/disables Transmitter Digital Bypass mode. The standard FS UART mode is selected by setting HSXCVREXTCTL<#> to 1'b0 and a proprietary HS test mode is selected by setting HSXCVREXTCTL<#> to 1'b1. 1:.." "Transmitter Digital Bypass mode is disabled,Transmitter Digital Bypass mode is enabled" bitfld.long 0x10 24. "BYPASSDPEN0,DP<#> Transmitter Digital Bypass Enable. Enables/disables the DP<#> FS/LS driver (if HSXCVREXTCTL<#> is set to 1'b0) or the DP<#> and DM<#> HS driver (if HSXCVREXTCTL<#> is set to 1'b1) in Transmitter Digital Bypass mode. FS mode is the.." "DP<#> FS/LS driver,DP<#> FS/LS driver" newline bitfld.long 0x10 23. "BYPASSDPDATA0,Data for DP<#> Transmitter Digital Bypass. In Transmitter Digital Bypass mode this signal provides the data that is transmitted on DP<#>. To use this signal BYPASSSEL<#> must be set to 1'b1. When HSXCVREXTCTL<#> is set to 1'b0 the FS/LS.." "HS driver transmits K,HS driver transmits J" bitfld.long 0x10 22. "BYPASSDMEN0,DM<#> Transmitter Digital Bypass Enable. Enables/disables the DM<#> FS/LS driver (if HSXCVREXTCTL<#> is set to 1'b0) in Transmitter Digital Bypass mode. FS mode is the standard UART mode. To use this mode BYPASSSEL<#> must be set to 1'b1." "DM<#> FS/LS driver,DM<#> FS/LS driver" newline bitfld.long 0x10 21. "BYPASSDMDATA0,Data for DM<#> Transmitter Digital Bypass. In Transmitter Digital Bypass mode this signal provides the data that is transmitted on DM<#>. To use this signal BYPASSSEL<#> must be set to 1'b1. When HSXCVREXTCTL<#> is set to 1'b0 the FS/LS.." "DM<#> FS/LS driver drives to a low state,DM<#> FS/LS driver drives to a high state" bitfld.long 0x10 20. "VBUSVLDEXTSEL0,External VBUS Valid Select Selects the VBUSVLDEXT<#> input or the internal Session Valid comparator to indicate when the VBUS<#> signal on the USB cable is valid. 1: VBUSVLDEXT<#> input is used. 0: Internal Session Valid comparator.." "Internal Session Valid comparator is used,VBUSVLDEXT<#> input is used" newline bitfld.long 0x10 19. "VBUSVLDEXT0,External VBUS Valid Indicator Valid in Device mode and only when the VBUSVLDEXTSEL0 signal is set to 1'b1. VBUSVLDEXT<#> indicates whether the VBUS<#> signal on the USB cable is valid. In addition VBUSVLDEXT<#> enables the pull- up resistor.." "VBUS<#> signal is not valid,VBUS<#> signal is valid" bitfld.long 0x10 17.--18. "VDATREFTUNE0,Data Detect Voltage Adjustment. Adjusts the threshold voltage level (Vdat_ref) used to detect data during charger-type detection. 11: - 20% 10: - 10% 01: 0 (default) 00: + 10%" "0,1,2,3" newline hexmask.long.byte 0x10 13.--16. 1. "TXVREFTUNE0,HS DC Voltage Level Adjustment Adjusts the high-speed DC level voltage. To enable tuning at the board level connect this bus to a register. 1111: + 8.75% 1110: + 7.5% 1101: + 6.25% 1100: + 5% 1011: + 3.75% 1010: +.." bitfld.long 0x10 11.--12. "TXRISETUNE0,HS Transmitter Rise/Fall Time Adjustment Adjusts the rise/fall times of the high-speed waveform. To enable tuning at the board level connect this bit to a register. 11: - 10% 10: 0 (default) 01: + 15% 00: + 20%" "0,1,2,3" newline bitfld.long 0x10 9.--10. "TXRESTUNE0,USB Source Impedance Adjustment Some applications require additional devices to be added on the USB such as a series switch which can add significant series resistance. This bus adjusts the driver source impedance (for both pull-up/pull-down.." "0,1,2,3" bitfld.long 0x10 8. "TXPREEMPPULSETUNE0,HS Transmitter Pre-Emphasis Duration Control This signal controls the duration for which the HS pre-emphasis current is sourced onto DP<#> or DM<#>. The HS Transmitter pre- emphasis duration is defined in terms of unit amounts. One.." "Long,Short" newline bitfld.long 0x10 6.--7. "TXPREEMPAMPTUNE0,HS Transmitter Pre-Emphasis Current Control This signal controls the amount of current sourced to DP<#> and DM<#> after a J-to-K or K-to-J transition. The HS Transmitter pre- emphasis current is defined in terms of unit amounts. One unit.." "Disabled,?,?,?" bitfld.long 0x10 4.--5. "TXHSXVTUNE0,Transmitter High-Speed Crossover Adjustment This bus adjusts the voltage at which the DP<#> and DM<#> signals cross while transmitting in HS mode. 11: 0 (default) 10: + 15 mV 01: - 15 mV 00: Reserved" "Reserved,?,?,?" newline hexmask.long.byte 0x10 0.--3. 1. "TXFSLSTUNE0,FS/LS Source Impedance Adjustment Adjusts the low- and full-speed single-ended source impedance while driving high. To enable tuning at the board level connect this bus to a register. 1111: - 5% 0111: -2.5% 0011: 0 (default).." repeat 3. (list 0x5 0x6 0x7 )(list 0x0 0x4 0x8 ) group.long ($2+0x14)++0x3 line.long 0x0 "CTRL_$1,CTRL_5" hexmask.long 0x0 0.--31. 1. "RSVD0,RSVD0" repeat.end rgroup.long 0x80++0x3 line.long 0x0 "STS_0,STS_0" hexmask.long.tbyte 0x0 12.--31. 1. "RSVD0,RSVD0" bitfld.long 0x0 11. "BVALID0,B-Device Session Valid Indicator This controller signal is output from the USB 3.0 femtoPHY's Session. Valid comparator and indicates whether the session for a B-device is valid. 1: Session for the B-device is valid. 0: Session for the.." "Session for the B-device is not valid,Session for the B-device is valid" newline bitfld.long 0x0 10. "AVALID0,A-Device Session Valid Indicator This controller signal is output from the USB 3.0 femtoPHY's Session. Valid comparator and indicates whether the session for an A-device is valid. 1: Session for the A-device is valid. 0: Session for the.." "Session for the A-device is not valid,Session for the A-device is valid" bitfld.long 0x0 9. "OTGSESSVLD0,OTG Device Session Valid Indicator (Low Voltage) This controller signal is output from the USB 3.0 femtoPHY's Session Valid comparator and indicates whether the voltage on VBUS is below the OTG Device Session Valid threshold. 1: The.." "The voltage on VBUS is below the OTG Device..,The voltage on VBUS is above the OTG Device.." newline bitfld.long 0x0 8. "IDDIG0,Mini A/B Plug Indicator This controller signal indicates whether the connected plug is a mini- A or mini-B plug. This signal must be valid within 20 ms after the IDPULLUP0 signal is set to 1'b1. 1: Connected plug is a mini-B plug. 0:.." "Connected plug is a mini-A plug,Connected plug is a mini-B plug" bitfld.long 0x0 7. "HSSQUELCH0,HS Squelch Detector Asynchronous Output. This signal asynchronously outputs the state of the HS squelch detector and can be used with the bypass signals to perform proprietary tests on the HS RX block. (For information about the bypass signals.." "If HSXCVREXTCTL<#> is set to 1'b1,If HSXCVREXTCTL<#> is set to 1'b1" newline bitfld.long 0x0 6. "HSRXDAT0,HS Transceiver Asynchronous Data Output. This signal asynchronously outputs the state of the HS receiver and can be used with the bypass signals to perform proprietary tests on the HS RX block. (For information about the bypass signals see the.." "If HSXCVREXTCTL<#> is set to 1'b1 and..,If HSXCVREXTCTL<#> is set to 1'b1 and.." bitfld.long 0x0 5. "FSVPLUS0,Single-Ended D+ Indicator This controller signal indicates the state of the D+ line in normal operation. 1: Voltage on D+ is high. 0: Voltage on D+ is low." "Voltage on D+ is low,Voltage on D+ is high" newline bitfld.long 0x0 4. "FSVMINUS0,Single-Ended D- Indicator This controller signal indicates the state of the D- line in normal operation. 1: Voltage on D- is high. 0: Voltage on D- is low." "Voltage on D,Voltage on D" bitfld.long 0x0 3. "FSLSRCV0,Differential Data Receive Indicator This controller signal indicates the state of differential data on the USB (2.0) during normal operation. 1: Voltage on D+ is greater than the voltage on D-. 0: Voltage on D+ is less than the voltage.." "Voltage on D+ is less than the voltage on D,Voltage on D+ is greater than the voltage on D" newline bitfld.long 0x0 2. "RTUNE_ACK,Resistor Tune Acknowledge While asserted indicates that a resistor tune is still in progress." "0,1" bitfld.long 0x0 1. "REF_CLKREQ_N,Reference Clock Removal Acknowledge" "0,1" newline bitfld.long 0x0 0. "ALT_CLK_REQ,Alternate Clock Source Request Indicates that the alternate clocks are needed by the slave PCS (that is to boot the master MPLL). Connect to alt_clk_en on the master." "0,1" repeat 7. (list 0x1 0x2 0x3 0x4 0x5 0x6 0x7 )(list 0x0 0x4 0x8 0xC 0x10 0x14 0x18 ) rgroup.long ($2+0x84)++0x3 line.long 0x0 "STS_$1,STS_1" hexmask.long 0x0 0.--31. 1. "RSVD0,RSVD0" repeat.end tree.end elif (CORENAME()=="CORTEXA55") tree "USB2" base ad:0x31260000 tree "DWC_usb3_block_gbl (USB 3.0 Global Register Block)" group.long (0x0+0x49408)++0x1F line.long 0x0 "GSBUSCFG0,Global SoC Bus Configuration Register 0 This register configures system bus DMA options for the master bus. which may be configured as AHB. AXI. or Native. Options include burst length and cache type (bufferable/posted. cacheable/snoop. and so.." hexmask.long.byte 0x0 28.--31. 1. "DATRDREQINFO,DATRDREQINFO AHB-prot/AXI-cache/OCP-ReqInfo for Data Read (DatRdReqInfo) Input to BUS-GM." newline hexmask.long.byte 0x0 24.--27. 1. "DESRDREQINFO,DESRDREQINFO AHB-prot/AXI-cache/OCP-ReqInfo for Descriptor Read (DesRdReqInfo). Input to BUS-GM." newline hexmask.long.byte 0x0 20.--23. 1. "DATWRREQINFO,DATWRREQINFO AHB-prot/AXI-cache/OCP-ReqInfo for Data Write (DatWrReqInfo). Input to BUS-GM." newline hexmask.long.byte 0x0 16.--19. 1. "DESWRREQINFO,DESWRREQINFO AHB-prot/AXI-cache/OCP-ReqInfo for Descriptor Write (DesWrReqInfo) Input to BUS-GM." newline hexmask.long.byte 0x0 12.--15. 1. "RESERVED_15_12,Reserved for future use" newline bitfld.long 0x0 11. "DATBIGEND,Data Access is Big Endian This bit controls the endian mode for data accesses. - Little-endian (default); - Big-endian; In big-endian mode DMA access (both read and write) for packet data a Byte Invariant Big-Endian mode (see 'Little-Endian.." "0,1" newline bitfld.long 0x0 10. "DESBIGEND,Descriptor Access is Big Endian This bit controls the endian mode for descriptor accesses. - Little-endian (default) - Big-endian In big-endian mode DMA access (both read and write) for descriptors uses a Byte Invariant Big-Endian mode (see.." "0,1" newline rbitfld.long 0x0 8.--9. "RESERVED_9_8,Reserved" "0,1,2,3" newline bitfld.long 0x0 7. "INCR256BRSTENA,INCR256 Burst Type Enable Input to BUS-GM. For the AHB/AXI configuration if software set this bit to 1 the AHB/AXI master uses INCR to do the 256-beat burst." "0,1" newline bitfld.long 0x0 6. "INCR128BRSTENA,INCR128 Burst Type Enable Input to BUS-GM; For the AHB/AXI configuration if software set this bit to 1 the AHB/AXI master uses INCR to do the 128-beat burst." "0,1" newline bitfld.long 0x0 5. "INCR64BRSTENA,INCR64 Burst Type Enable - Input to BUS-GM; For the AHB/AXI configuration if software set this bit to 1 the AHB/AXI master uses INCR to do the 64-beat burst." "0,1" newline bitfld.long 0x0 4. "INCR32BRSTENA,INCR32 Burst Type Enable Input to BUS-GM; For the AHB/AXI configuration if software set this bit to 1 the AHB/AXI master uses INCR to do the 32-beat burst." "0,1" newline bitfld.long 0x0 3. "INCR16BRSTENA,INCR16 Burst Type Enable Input to BUS-GM. For the AHB/AXI configuration if software set this bit to '1' the AHB/AXI master uses INCR to do the 16-beat burst." "0,1" newline bitfld.long 0x0 2. "INCR8BRSTENA,INCR8 Burst Type Enable Input to BUS-GM; For the AHB/AXI configuration if software set this bit to '1' the AHB/AXI master uses INCR to do the 8-beat burst." "0,1" newline bitfld.long 0x0 1. "INCR4BRSTENA,INCR4 Burst Type Enable Input to BUS-GM; For the AXI configuration when this bit is enabled the controller is allowed to do bursts of beat length 1 2 and 4. It is highly recommended that this bit is enabled to prevent descriptor reads and.." "0,1" newline bitfld.long 0x0 0. "INCRBRSTENA,Undefined Length INCR Burst Type Enable (INCRBrstEna) Input to BUS-GM; This bit determines the set of burst lengths the master interface uses. It works in conjunction with the GSBUSCFG0[7:1] enables (INCR256/128/64/32/16/8/4). 0: INCRX burst.." "INCRX burst mode,INCR" line.long 0x4 "GSBUSCFG1,Global SoC Bus Configuration Register 1 xHCI Register Power-On Value: If you are using a standard xHCI host driver. make sure to set the register's power-on value during coreConsultant configuration (DWC_USB3_GSBUSCFG1_INIT parameter) because.." hexmask.long.tbyte 0x4 13.--31. 1. "RESERVED_31_13,Reserved" newline bitfld.long 0x4 12. "EN1KPAGE,1k Page Boundary Enable By default (this bit is disabled) the AXI breaks transfers at the 4k page boundary. When this bit is enabled the AXI master (DMA data) breaks transfers at the 1k page boundary." "0,1" newline hexmask.long.byte 0x4 8.--11. 1. "PIPETRANSLIMIT,AXI Pipelined Transfers Burst Request Limit The field controls the number of outstanding pipelined transfer requests the AXI master pushes to the AXI slave. When the AXI master reaches this limit it does not make any more requests on the.." newline hexmask.long.byte 0x4 0.--7. 1. "RESERVED_7_0,Reserved" line.long 0x8 "GTXTHRCFG,Global Tx Threshold Control Register For more information on - Using this register. refer to 'Packet Threshold and Burst Features for High Latency Systems' section in the Databook. - Selecting values for the fields of this register. see the.." rbitfld.long 0x8 31. "RESERVED_31,Reserved" "0,1" newline rbitfld.long 0x8 30. "RESERVED_30,Reserved" "0,1" newline bitfld.long 0x8 29. "USBTXPKTCNTSEL,USB Transmit Packet Count Enable This field enables/disables the USB transmission multi-packet thresholding: - 0: USB transmission multi-packet thresholding is disabled; the controller can start transmission on the USB after the entire.." "USB transmission multi-packet thresholding is..,USB transmission multi-packet thresholding is.." newline rbitfld.long 0x8 28. "RESERVED_28,Reserved" "0,1" newline hexmask.long.byte 0x8 24.--27. 1. "USBTXPKTCNT,USB Transmit Packet Count This field specifies the number of packets that must be in the TXFIFO before the controller can start transmission for the corresponding USB transaction (burst). This field is only valid when the USB Transmit Packet.." newline hexmask.long.byte 0x8 16.--23. 1. "USBMAXTXBURSTSIZE,USB Maximum TX Burst Size When UsbTxPktCntSel is one this field specifies the Maximum Bulk OUT burst the controller can do. When the system bus is slower than the USB TX FIFO can underrun during a long burst. User can program a.." newline rbitfld.long 0x8 15. "RESERVED_15,Reserved_15" "0,1" newline rbitfld.long 0x8 14. "RESERVED_14,Reserved1(Rsvd/Rs) Register field must write only 0 by the application. The read value must be treated as X (unknown)." "0,1" newline rbitfld.long 0x8 11.--13. "RESERVED_13_11,Reserved (Rsvd/Rs) The register field must write only 0 by the application. The read value must be treated as X (unknown)." "0,1,2,3,4,5,6,7" newline hexmask.long.word 0x8 0.--10. 1. "RESERVED_10_0,Reserved for future use" line.long 0xC "GRXTHRCFG,Global Rx Threshold Control Register In a normal case. a Tx burst starts as soon as one packet is prefetched; an Rx burst starts as soon as 1-packet space is available. This works well as long as the system bus is faster than the USB 3.0 bus (a.." rbitfld.long 0xC 30.--31. "RESERVED_31_30,Reserved" "0,1,2,3" newline bitfld.long 0xC 29. "USBRXPKTCNTSEL,USB Receive Packet Count Enable This field enables/disables the USB reception multi-packet thresholding: - 0: The controller can only start reception on the USB when the RX FIFO has space for at least one packet. - 1: The controller can.." "The controller can only start reception on the..,The controller can only start reception on the.." newline rbitfld.long 0xC 28. "RESERVED_28,Reserved" "0,1" newline hexmask.long.byte 0xC 24.--27. 1. "USBRXPKTCNT,USB Receive Packet Count In host mode this field specifies the space (in terms of the number of packets) that must be available in the RX FIFO before the controller can start the corresponding USB RX transaction (burst). In device mode this.." newline hexmask.long.byte 0xC 19.--23. 1. "USBMAXRXBURSTSIZE,USB Maximum Receive Burst Size In host mode this field specifies the Maximum Bulk IN burst the DWC_usb3 controller can perform. When the system bus is slower than the USB RX FIFO can overrun during a long burst. You can program a.." newline rbitfld.long 0xC 16.--18. "RESERVED_18_16,Reserved" "0,1,2,3,4,5,6,7" newline rbitfld.long 0xC 15. "RESERVED_15,Reserved" "0,1" newline rbitfld.long 0xC 13.--14. "RESERVED_14_13,Reserved" "0,1,2,3" newline hexmask.long.word 0xC 0.--12. 1. "RESVISOCOUTSPC,Space reserved in Rx FIFO for ISOC OUT In host mode this field is not applicable and must be programmed to 0. In device mode this value represents the amount of space to be reserved for ISOC OUT packets. The value to be programmed should.." line.long 0x10 "GCTL,Global Core Control Register Refer to /src/DWC_usb3_params.v for details on `DWC_USB3_GCTL_INIT. Note: When Hibernation is not enabled. you can write any value to GblHibernationEn. It always returns 0 when read." hexmask.long.word 0x10 19.--31. 1. "PWRDNSCALE,Power Down Scale (PwrDnScale) The USB3 suspend_clk input replaces pipe3_rx_pclk as a clock source to a small part of the USB3 controller that operates when the SS PHY is in its lowest power (P3) state and therefore does not provide a clock." newline bitfld.long 0x10 18. "MASTERFILTBYPASS,Master Filter Bypass When this bit is set to 1'b1 irrespective of the parameter `DWC_USB3_EN_BUS_FILTERS chosen all the filters in the DWC_usb3_filter module are bypassed. The double synchronizers to mac_clk preceding the filters are.." "0,1" newline bitfld.long 0x10 17. "BYPSSETADDR,Bypass SetAddress in Device Mode. When BYPSSETADDR bit is set the device controller uses the value in the DCFG[DevAddr] bits directly for comparing the device address in the tokens. For simulation you can use this feature to avoid sending.." "0,1" newline bitfld.long 0x10 16. "U2RSTECN,U2RSTECN If the SuperSpeed connection fails during POLL or LMP exchange the device connects at non-SS mode. If this bit is set then device attempts three more times to connect at SS even if it previously failed to operate in SS mode. For each.." "0,1" newline bitfld.long 0x10 14.--15. "FRMSCLDWN,FRMSCLDWN This field scales down device view of a SOF/USOF/ITP duration. For SS/HS mode: - Value of 2'h3 implements interval to be 15.625 us - Value of 2'h2 implements interval to be 31.25 us - Value of 2'h1 implements interval to be 62.5 us -.." "0,1,2,3" newline bitfld.long 0x10 12.--13. "PRTCAPDIR,PRTCAPDIR: Port Capability Direction (PrtCapDir) - 2'b01: for Host configurations - 2'b10: for Device configurations Note: For static Host-only/Device-only applications use DRD Host or DRD Device mode. The combination of GCTL.PrtCapDir=2'b11.." "?,for Host configurations,for Device configurations,?" newline bitfld.long 0x10 11. "CORESOFTRESET,Core Soft Reset (CoreSoftReset) - 1'b0 - No soft reset - 1'b1 - Soft reset to controller Clears the interrupts and all the CSRs except the following registers: - GCTL - GUCTL - GSTS - GSNPSID - GGPIO - GUID - GUSB2PHYCFGn registers -.." "No soft reset,Soft reset to controller" newline bitfld.long 0x10 10. "SOFITPSYNC,SOFITPSYNC If this bit is set to '0' operating in host mode the controller keeps the UTMI/ULPI PHY on the first port in a non-suspended state whenever there is a SuperSpeed port that is not in Rx.Detect SS.Disable and U3. If this bit is set.." "0,1" newline bitfld.long 0x10 9. "U1U2TIMERSCALE,Disable U1/U2 timer Scaledown (U1U2TimerScale). If set to '1' along with GCTL[5:4] (ScaleDown) = 2'bX1 disables the scale down of U1/U2 inactive timer values. This is for simulation mode only." "0,1" newline bitfld.long 0x10 8. "DEBUGATTACH,Debug Attach When this bit is set - SS Link proceeds directly to the Polling link state (after RUN/STOP in the DCTL register is asserted) without checking remote termination; - Link LFPS polling timeout is infinite; - Polling timeout during.." "0,1" newline bitfld.long 0x10 6.--7. "RAMCLKSEL,RAM Clock Select (RAMClkSel) - 2'b00: bus clock - 2'b01: pipe clock (Only used in device mode) - 2'b10: In device mode pipe/2 clock.In Host mode controller switches ram_clk between pipe/2 clock mac2_clk and bus_clk based on the status of.." "bus clock,pipe clock,In device mode,In device mode" newline bitfld.long 0x10 4.--5. "SCALEDOWN,Scale-Down Mode (ScaleDown) When Scale-Down mode is enabled for simulation the controller uses scaled-down timing values resulting in faster simulations. When Scale-Down mode is disabled actual timing values are used. This is required for.." "Disables all scale-downs,Enables scaled down SS timing and repeat values..,No TxEq training sequences are sent,Enables bit 0 and bit 1 scale-down timing values" newline bitfld.long 0x10 3. "DISSCRAMBLE,Disable Scrambling (DisScramble) Transmit request to Link Partner on next transition to Recovery or Polling." "0,1" newline bitfld.long 0x10 2. "U2EXIT_LFPS,U2EXIT_LFPS If this bit is - 0: the link treats 248ns LFPS as a valid U2 exit. - 1: the link waits for 8us of LFPS before it detects a valid U2 exit. This bit is added to improve interoperability with a third-party host/device controller." "the link treats 248ns LFPS as a valid U2 exit,the link waits for 8us of LFPS before it detects.." newline rbitfld.long 0x10 1. "GBLHIBERNATIONEN,GblHibernationEn This bit enables hibernation at the global level. If hibernation is not enabled through this bit the PMU immediately accepts the D0->D3 and D3->D0 power state change requests but does not save or restore any controller.." "D3 and D3,?" newline bitfld.long 0x10 0. "DSBLCLKGTNG,Disable Clock Gating (DsblClkGtng) This bit is set to 1 and the controller is in Low Power mode internal clock gating is disabled. You can set this bit to 1'b1 after Power On Reset." "0,1" line.long 0x14 "GPMSTS,Global Power Management Status Register This debug register gives information on which event caused the hibernation exit. It provides internal status and state machine information. and is for Synopsys use only for debugging purposes. This register.." hexmask.long.byte 0x14 28.--31. 1. "PORTSEL,Global Power Management Status Register PortSel This field selects the port number." newline hexmask.long.word 0x14 17.--27. 1. "RESERVED_27_17,Reserved" newline hexmask.long.byte 0x14 12.--16. 1. "U3WAKEUP,U3Wakeup This field gives the following USB 3.0 port wakeup conditions: - Bit [12]: Overcurrent Detected - Bit [13]: Resume Detected - Bit [14]: Connect Detected - Bit [15]: Disconnect Detected - Bit [16]: Last Connection State" newline rbitfld.long 0x14 10.--11. "RESERVED_10_11,Reserved" "0,1,2,3" newline hexmask.long.word 0x14 0.--9. 1. "U2WAKEUP,U2Wakeup This field indicates the following USB 2.0 port wakeup conditions: - Bit [0]: Overcurrent Detected - Bit [1]: Resume Detected - Bit [2]: Connect Detected - Bit [3]: Disconnect Detected - Bit [4]: Last Connection State - Bit [5]: ID.." line.long 0x18 "GSTS,Global Status Register" hexmask.long.word 0x18 20.--31. 1. "CBELT,Current BELT Value In Host mode this field indicates the minimum value of all received device BELT values and the BELT value that is set by the Set Latency Tolerance Value command." newline hexmask.long.byte 0x18 12.--19. 1. "RESERVED_19_12,Reserved" newline rbitfld.long 0x18 11. "SSIC_IP,This field is not used." "0,1" newline rbitfld.long 0x18 10. "OTG_IP,This field is not used." "0,1" newline rbitfld.long 0x18 9. "BC_IP,Battery Charger Interrupt Pending This field indicates that there is a pending interrupt pertaining to BC in BCEVT register." "0,1" newline rbitfld.long 0x18 8. "ADP_IP,This field is not used." "0,1" newline rbitfld.long 0x18 7. "HOST_IP,Host Interrupt Pending: This field indicates that there is a pending interrupt pertaining to xHC in the Host event queue." "0,1" newline rbitfld.long 0x18 6. "DEVICE_IP,Device Interrupt Pending This field indicates that there is a pending interrupt pertaining to peripheral (device) operation in the Device event queue." "0,1" newline bitfld.long 0x18 5. "CSRTIMEOUT,CSR Timeout When this bit is 1'b1 it indicates that the software performed a write or read to a controller register that could not be completed within `DWC_USB3_CSR_ACCESS_TIMEOUT bus clock cycles (default: h1FFFF)." "0,1" newline bitfld.long 0x18 4. "BUSERRADDRVLD,Bus Error Address Valid (BusErrAddrVld) Indicates that the GBUSERRADDR register is valid and reports the first bus address that encounters a bus error. Note: Only supported in AHB and AXI configurations." "0,1" newline rbitfld.long 0x18 2.--3. "RESERVED_3_2,Reserved" "0,1,2,3" newline rbitfld.long 0x18 0.--1. "CURMOD,Current Mode of Operation (CurMod) Indicates the current mode of operation: - 2'b00: Device mode - 2'b01: Host mode" "Device mode,Host mode,?,?" line.long 0x1C "GUCTL1,Global User Control Register 1" bitfld.long 0x1C 31. "DEV_DECOUPLE_L1L2_EVT,DEV_DECOUPLE_L1L2_EVT - 0: Default behavior no change in device events L1/L2U3 events are not decoupled (old behavior of v2.90a and before) - 1: Feature enabled L1 and L2 events are separated when operating in 2.0 mode. Separate.." "Default behavior,Feature enabled" newline bitfld.long 0x1C 30. "DS_RXDET_MAX_TOUT_CTRL,DS_RXDET_MAX_TOUT_CTRL This bit is used to control the tRxDetectTimeoutDFP timer for the SuperSpeed link. - 0: Default behavior; 12ms is used as tRxDetectTimeoutDFP. - 1: 120ms is used as the tRxDetectTimeoutDFP. This bit is used.." "Default behavior; 12ms is used as..,?" newline bitfld.long 0x1C 29. "FILTER_SE0_FSLS_EOP,FILTER_SE0_FSLS_EOP - 0: Default behavior no change in Linestate check for SE0 detection in FS/LS - 1: Feature enabled FS/LS SE0 is filtered for 2 clocks for detecting EOP This bit is applicable for FS/LS operation. If this feature.." "Default behavior,Feature enabled" newline bitfld.long 0x1C 28. "TX_IPGAP_LINECHECK_DIS,TX_IPGAP_LINECHECK_DIS - 0: Default behavior no change in Linestate check - 1: Feature enabled 2.0 MAC disables Linestate check during HS transmit This bit is applicable for HS operation of u2mac. If this feature is enabled then.." "Default behavior,Feature enabled" newline bitfld.long 0x1C 27. "DEV_TRB_OUT_SPR_IND,DEV_TRB_OUT_SPR_IND - 0: Default behavior no change in TRB status dword - 1: Feature enabled OUT TRB status indicates Short Packet This bit is applicable for device mode only (and ignored in host mode). If the device application.." "Default behavior,Feature enabled" newline bitfld.long 0x1C 26. "DEV_FORCE_20_CLK_FOR_30_CLK,DEV_FORCE_20_CLK_FOR_30_CLK - 0: Default behavior Uses 3.0 clock when operating in 2.0 mode - 1: Feature enabled This bit is applicable (and to be set) for device mode (DCFG.Speed != SS) only. In the 3.0 device controller if.." "Default behavior,Feature enabled" newline bitfld.long 0x1C 25. "P3_IN_U2,P3_IN_U2 - 0: Default behavior When SuperSpeed link is in U2 PowerState P2 is attempted on the PIPE Interface. - 1: When SuperSpeed link is in U2 PowerState P3 is attempted if GUSB3PIPECTL[17] is set. Setting this bit enables P3 Power State.." "Default behavior,When SuperSpeed link is in U2" newline bitfld.long 0x1C 24. "DEV_L1_EXIT_BY_HW,DEV_L1_EXIT_BY_HW - 0: Default behavior disables device L1 hardware exit logic - 1: feature enabled This bit is applicable for device mode (2.0) only. This field enables device controller sending remote wakeup for L1 if the device.." "Default behavior,feature enabled" newline bitfld.long 0x1C 21.--23. "IP_GAP_ADD_ON,This register field is used to add on to the default inter packet gap setting in the USB 2.0 MAC. This should be programmed to a non zero value only in case where you need to increase the default inter packet delay calculations in the USB.." "0,1,2,3,4,5,6,7" newline bitfld.long 0x1C 20. "DEV_LSP_TAIL_LOCK_DIS,DEV_LSP_TAIL_LOCK_DIS - 0: Default behavior enables device lsp lock logic for tail TRB update - 1: Fix disabled This is a bug fix for STAR 9000716195 that affects the CSP mode for OUT endpoints in device mode. The issue is that.." "Default behavior,Fix disabled" newline bitfld.long 0x1C 19. "NAK_PER_ENH_FS,NAK_PER_ENH_FS - 1: Enables performance enhancement for FS async endpoints in the presence of NAKs - 0: Enhancement not applied If a periodic endpoint is present and if a bulk endpoint which is also active is being NAKed by the device.." "Enhancement not applied,Enables performance enhancement for FS async.." newline bitfld.long 0x1C 18. "NAK_PER_ENH_HS,NAK_PER_ENH_HS - 1: Enables performance enhancement for HS async endpoints in the presence of NAKs - 0: Enhancement not applied If a periodic endpoint is present and if a bulk endpoint which is also active is being NAKed by the device.." "Enhancement not applied,Enables performance enhancement for HS async.." newline bitfld.long 0x1C 17. "PARKMODE_DISABLE_SS,PARKMODE_DISABLE_SS This bit is used only in host mode and is for debug purpose only. When this bit is set to '1' all SS bus instances in park mode are disabled." "0,1" newline bitfld.long 0x1C 16. "PARKMODE_DISABLE_HS,PARKMODE_DISABLE_HS This bit is used only in host mode. When this bit is set to '1' all HS bus instances park mode are disabled. To improve performance in park mode the xHCI scheduler queues in three requests of 4 packets each for.." "0,1" newline bitfld.long 0x1C 15. "PARKMODE_DISABLE_FSLS,PARKMODE_DISABLE_FSLS This bit is used only in host mode and is for debug purpose only. When this bit is set to '1' all FS/LS bus instances in park mode disabled." "0,1" newline rbitfld.long 0x1C 13.--14. "RESERVED_14_13,Reserved" "0,1,2,3" newline rbitfld.long 0x1C 12. "DISUSB2REFCLKGTNG,Disable ref_clk gating for 2.0 PHY (DisUSB2RefClkGtng) If ref_clk gating is disabled then the ref_clk input cannot be turned off to the USB 2.0 PHY and controller. This is independent of the GCTL[DisClkGtng] setting. - 1'b0: ref_clk.." "ref_clk gating enabled for USB 2,ref_clk gating disabled for USB 2" newline rbitfld.long 0x1C 11. "DISREFCLKGTNG,Disable ref_clk gating (DisRefClkGtng) If the ref_clk gating is disabled then input ref_clk cannot be turned off to SSPHY and controller. This is independent of GCTL[DisClkGtng] setting. - 1'b0: ref_clk gating Enabled for SSPHY - 1'b1:.." "ref_clk gating Enabled for SSPHY,ref_clk gating Disabled for SSPHY" newline bitfld.long 0x1C 10. "RESUME_OPMODE_HS_HOST,RESUME_OPMODE_HS_HOST This bit is used only in host mode and is for USB 2.0 opmode behavior in HS Resume. - When this bit is set to '1' the UTMI/ULPI opmode will be changed to 'normal' along with HS terminations after EOR. This.." "0,1" newline bitfld.long 0x1C 9. "DEV_HS_NYET_BULK_SPR,DEV_HS_NYET_BULK_SPR - 0: Default behavior no change in device response - 1: Feature enabled HS bulk OUT short packet gets NYET response This bit is applicable for device mode only (and ignored in host mode) to be used in 2.0.." "Default behavior,Feature enabled" newline bitfld.long 0x1C 8. "L1_SUSP_THRLD_EN_FOR_HOST,L1_SUSP_THRLD_EN_FOR_HOST This bit is used only in host mode. The host controller asserts the utmi_l1_suspend_n and utmi_sleep_n output signals (see 'LPM Interface Signals' table in the Databook) as follows: The controller.." "0,1" newline hexmask.long.byte 0x1C 4.--7. 1. "L1_SUSP_THRLD_FOR_HOST,L1_SUSP_THRLD_FOR_HOST This field is effective only when the L1_SUSP_THRLD_EN_FOR_HOST bit is set to 1. For more details refer to the description of the L1_SUSP_THRLD_EN_FOR_HOST bit." newline bitfld.long 0x1C 3. "HC_ERRATA_ENABLE,Host ELD Enable (HELDEn) When this bit is set to 1 it enables the Exit Latency Delta (ELD) support defined in the xHCI 1.0 Errata. This bit is used only in the host mode. This bit has to be set to 1 in Host mode." "0,1" newline bitfld.long 0x1C 2. "HC_PARCHK_DISABLE,Host Parameter Check Disable (HParChkDisable) When this bit is set to '0' (by default) the xHC checks that the input slot/EP context fields comply to the xHCI Specification. Upon detection of a parameter error during command execution.." "0,1" newline bitfld.long 0x1C 1. "OVRLD_L1_SUSP_COM,OVRLD_L1_SUSP_COM If this bit is set the utmi_l1_suspend_com_n is overloaded with the utmi_sleep_n signal. This bit is usually set if the PHY stops the port clock during L1 sleep condition. Note: The recommended connection for the.." "For Synopsys PHY,?" newline bitfld.long 0x1C 0. "LOA_FILTER_EN,LOA_FILTER_EN If this bit is set the USB 2.0 port babble is checked at least three consecutive times before the port is disabled. This prevents false triggering of the babble condition when using low quality cables. Note: This bit is valid.." "0,1" rgroup.long (0x20+0x49408)++0x3 line.long 0x0 "GSNPSID,Global Synopsys ID Register This is a read-only register that contains the release number of the controller." hexmask.long 0x0 0.--31. 1. "SYNOPSYSID,Synopsys ID - SynopsysID[31:16] indicates Core Identification Number. 0x5533 is ASCII for U3 (DWC_usb3). - SynopsysID[15:0] indicates the release number. Current Release is 3.30a. Software uses this register to configure release-specific.." group.long (0x24+0x49408)++0xB line.long 0x0 "GGPIO,Global General Purpose Input/Output Register The application can use this register for general purpose input and output ports or for debugging." hexmask.long.word 0x0 16.--31. 1. "GPO,General Purpose Output The value of this field is driven out on the gp_out[15:0] output port." newline hexmask.long.word 0x0 0.--15. 1. "GPI,General Purpose Input The read value of this field reflects the gp_in[15:0] input signal value. Note: Register bit-bash test should not check for reset value of this field since its not predictable; depends on the gp_in port." line.long 0x4 "GUID,Global User ID Register This is a read/write register containing the User ID. The power-on value for this register is specified as the User Identification Register. Power-on value during coreConsultant configuration (parameter DWC_USB3_USERID). This.." hexmask.long 0x4 0.--31. 1. "USERID,USERID Application-programmable ID field." line.long 0x8 "GUCTL,Global User Control Register: This register provides a few options for the software to control the controller behavior in the Host mode. Most of the options are used to improve host inter-operability with different devices." hexmask.long.word 0x8 22.--31. 1. "REFCLKPER,REFCLKPER This field indicates in terms of nano seconds the period of ref_clk. The default value of this register is set to 'h8 (8ns/125 MHz). This field needs to be updated during power-on initialization if GCTL.SOFITPSYNC or.." newline bitfld.long 0x8 21. "NOEXTRDL,No Extra Delay Between SOF and the First Packet(NoExtrDl) Some HS devices misbehave when the host sends a packet immediately after a SOF. However adding an extra delay between a SOF and the first packet can reduce the USB data rate and.." "Host waits for 2 microseconds after a SOF before..,Host doesn't wait after a SOF before it sends.." newline rbitfld.long 0x8 18.--20. "RESERVED_20_18,Reserved" "0,1,2,3,4,5,6,7" newline bitfld.long 0x8 17. "SPRSCTRLTRANSEN,Sparse Control Transaction Enable Some devices are slow in responding to Control transfers. Scheduling multiple transactions in one microframe/frame can cause these devices to misbehave. If this bit is set to 1'b1 the host controller.." "0,1" newline bitfld.long 0x8 16. "RESBWHSEPS,Reserving 85% Bandwidth for HS Periodic EPs (ResBwHSEPS) By default HC reserves 80% of the bandwidth for periodic EPs. If this bit is set the bandwidth is relaxed to 85% to accommodate two high speed high bandwidth ISOC EPs. USB 2.0.." "0,1" newline rbitfld.long 0x8 15. "RESERVED_15,Reserved" "0,1" newline bitfld.long 0x8 14. "USBHSTINAUTORETRYEN,Host IN Auto Retry (USBHstInAutoRetryEn) When set this field enables the Auto Retry feature. For IN transfers (non-isochronous) that encounter data packets with CRC errors or internal overrun scenarios the auto retry feature causes.." "Auto Retry Disabled,Auto Retry Enabled" newline bitfld.long 0x8 13. "ENOVERLAPCHK,Enable Check for LFPS Overlap During Remote Ux Exit: If this bit is set to - 1'b1: The SuperSpeed link when exiting U1/U2/U3 waits for either the remote link LFPS or TS1/TS2 training symbols before it confirms that the LFPS handshake is.." "When the link exists U1/U2/U3 because of a..,The SuperSpeed link when exiting U1/U2/U3 waits.." newline bitfld.long 0x8 12. "EXTCAPSUPPTEN,External Extended Capability Support Enable (ExtCapSuptEN) When set this field enables extended capabilities to be implemented outside the controller. When the ExtCapSupEN is set and the Debug Capability is enabled the Next Capability.." "0,1" newline bitfld.long 0x8 11. "INSRTEXTRFSBODI,Insert Extra Delay Between FS Bulk OUT Transactions (InsrtExtrFSBODl). Some FS devices are slow to receive Bulk OUT data and can get stuck when there are consecutive Bulk OUT transactions with short inter-transaction delays. This bit is.." "Host doesn't insert extra delay between..,Host inserts about 12us extra delay between.." newline bitfld.long 0x8 9.--10. "DTCT,Device Timeout Coarse Tuning (DTCT) This field is a Host mode parameter which determines how long the host waits for a response from device before considering a timeout. The controller first checks the DTCT value. If it is 0 then the timeout value.." "0,1,2,3" newline hexmask.long.word 0x8 0.--8. 1. "DTFT,Device Timeout Fine Tuning (DTFT) This field is a Host mode parameter which determines how long the host waits for a response from device before considering a timeout. For the DTFT field to take effect DTCT must be set to 2'b00. The DTFT value is.." rgroup.long (0x30+0x49408)++0x7 line.long 0x0 "GBUSERRADDRLO,Gobal SoC Bus Error Address Register - Low This is an alternate register for the GBUSERRADDR register." hexmask.long 0x0 0.--31. 1. "BUSERRADDR,Bus Address - Low (BusAddrLo) This register contains the lower 32 bits of the first bus address that encountered a SoC bus error. It is valid when the GSTS.BusErrAddrVld field is 1. It can only be cleared by resetting the controller. Note:.." line.long 0x4 "GBUSERRADDRHI,Gobal SoC Bus Error Address Register - High This is an alternate register for the GBUSERRADDR register." hexmask.long 0x4 0.--31. 1. "BUSERRADDR,Bus Address - High (BusAddrHi) This register contains the higher 32 bits of the first bus address that encountered a SoC bus error. It is valid when the GSTS.BusErrAddrVld field is 1. It can only be cleared by resetting the controller. Note:.." group.long (0x38+0x49408)++0x7 line.long 0x0 "GPRTBIMAPLO,Global SS Port to Bus Instance Mapping Register - Low This is an alternate register for the GPRTBIMAP register. Register fields are read-write with respect to number of port instantiated. writeAsRead constraint is added to limit side effects.." hexmask.long.byte 0x0 28.--31. 1. "BINUM8,BINUM8: SS USB Instance Number for Port 8. Application-programmable ID field." newline hexmask.long.byte 0x0 24.--27. 1. "BINUM7,BINUM7: SS USB Instance Number for Port 7. Application-programmable ID field." newline hexmask.long.byte 0x0 20.--23. 1. "BINUM6,BINUM6: SS USB Instance Number for Port 6. Application-programmable ID field." newline hexmask.long.byte 0x0 16.--19. 1. "BINUM5,BINUM5: SS USB Instance Number for Port 5. Application-programmable ID field." newline hexmask.long.byte 0x0 12.--15. 1. "BINUM4,BINUM4: SS USB Instance Number for Port 4. Application-programmable ID field." newline hexmask.long.byte 0x0 8.--11. 1. "BINUM3,BINUM3: SS USB Instance Number for Port 3. Application-programmable ID field." newline hexmask.long.byte 0x0 4.--7. 1. "BINUM2,BINUM2: SS USB Instance Number for Port 2. Application-programmable ID field." newline hexmask.long.byte 0x0 0.--3. 1. "BINUM1,BINUM1: SS USB Instance Number for Port 1. Application-programmable ID field." line.long 0x4 "GPRTBIMAPHI,Global SS Port to Bus Instance Mapping Register - High This is an alternate register for the GPRTBIMAP register. For a configuration with number of USB 3.0 ports same as number of SS Bus Instances. do not remap during debug session. If you.." hexmask.long.byte 0x4 28.--31. 1. "RESERVED_31_28,Reserved" newline hexmask.long.byte 0x4 24.--27. 1. "BINUM15,BINUM15: SS USB Instance Number for Port 15. Application-programmable ID field." newline hexmask.long.byte 0x4 20.--23. 1. "BINUM14,BINUM14: SS USB Instance Number for Port 14. Application-programmable ID field." newline hexmask.long.byte 0x4 16.--19. 1. "BINUM13,BINUM13: SS USB Instance Number for Port 13. Application-programmable ID field." newline hexmask.long.byte 0x4 12.--15. 1. "BINUM12,BINUM12: SS USB Instance Number for Port 12. Application-programmable ID field." newline hexmask.long.byte 0x4 8.--11. 1. "BINUM11,BINUM11: SS USB Instance Number for Port 11. Application-programmable ID field." newline hexmask.long.byte 0x4 4.--7. 1. "BINUM10,BINUM10: SS USB Instance Number for Port 10. Application-programmable ID field." newline hexmask.long.byte 0x4 0.--3. 1. "BINUM9,BINUM9: SS USB Instance Number for Port 9. Application-programmable ID field." rgroup.long (0x40+0x49408)++0x7 line.long 0x0 "GHWPARAMS0,Global Hardware Parameters Register 0 This register contains the hardware configuration options that you can select in the coreConsultant GUI. For a description of each parameter. refer to the 'Parameter Descriptions' chapter in the Databook." hexmask.long.byte 0x0 24.--31. 1. "GHWPARAMS0_31_24,`DWC_USB3_AWIDTH" newline hexmask.long.byte 0x0 16.--23. 1. "GHWPARAMS0_23_16,`DWC_USB3_SDWIDTH" newline hexmask.long.byte 0x0 8.--15. 1. "GHWPARAMS0_15_8,`DWC_USB3_MDWIDTH" newline bitfld.long 0x0 6.--7. "GHWPARAMS0_7_6,`DWC_USB3_SBUS_TYPE" "0,1,2,3" newline bitfld.long 0x0 3.--5. "GHWPARAMS0_5_3,`DWC_USB3_MBUS_TYPE" "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 0.--2. "GHWPARAMS0_2_0,`DWC_USB3_MODE" "0,1,2,3,4,5,6,7" line.long 0x4 "GHWPARAMS1,Global Hardware Parameters Register 1 This register contains the hardware configuration options that you can select in the coreConsultant GUI. For a description of each parameter. refer to the 'Parameter Descriptions' chapter in the Databook." bitfld.long 0x4 31. "GHWPARAMS1_31,`DWC_USB3_EN_DBC" "0,1" newline bitfld.long 0x4 30. "GHWPARAMS1_30,`DWC_USB3_RM_OPT_FEATURES" "0,1" newline bitfld.long 0x4 29. "GHWPARAMS1_29,Reserved1" "0,1" newline bitfld.long 0x4 28. "GHWPARAMS1_28,`DWC_USB3_RAM_BUS_CLKS_SYNC" "0,1" newline bitfld.long 0x4 27. "GHWPARAMS1_27,`DWC_USB3_MAC_RAM_CLKS_SYNC" "0,1" newline bitfld.long 0x4 26. "GHWPARAMS1_26,`DWC_USB3_MAC_PHY_CLKS_SYNC" "0,1" newline bitfld.long 0x4 24.--25. "GHWPARAMS1_25_24,`DWC_USB3_EN_PWROPT" "0,1,2,3" newline bitfld.long 0x4 23. "GHWPARAMS1_23,`DWC_USB3_SPRAM_TYP" "0,1" newline bitfld.long 0x4 21.--22. "GHWPARAMS1_22_21,`DWC_USB3_NUM_RAMS" "0,1,2,3" newline hexmask.long.byte 0x4 15.--20. 1. "GHWPARAMS1_20_15,`DWC_USB3_DEVICE_NUM_INT For details on `DWC_USB3_DEVICE_NUM_INT refer to /src/DWC_usb3_params.v file." newline bitfld.long 0x4 12.--14. "GHWPARAMS1_14_12,`DWC_USB3_ASPACEWIDTH" "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 9.--11. "GHWPARAMS1_11_9,`DWC_USB3_REQINFOWIDTH" "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 6.--8. "GHWPARAMS1_8_6,`DWC_USB3_DATAINFOWIDTH" "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 3.--5. "GHWPARAMS1_5_3,`DWC_USB3_BURSTWIDTH-1" "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 0.--2. "GHWPARAMS1_2_0,`DWC_USB3_IDWIDTH-1" "0,1,2,3,4,5,6,7" repeat 2. (list 0x2 0x8 )(list 0x0 0x4B8 ) rgroup.long ($2+0x48+0x49408)++0x3 line.long 0x0 "GHWPARAMS$1,Global Hardware Parameters Register 2 This register contains the hardware configuration options that you can select in the coreConsultant GUI. For a description of each parameter. refer to the 'Parameter Descriptions' chapter in the Databook." hexmask.long 0x0 0.--31. 1. "GHWPARAMS2_31_0,`DWC_USB3_USERID" repeat.end rgroup.long (0x4C+0x49408)++0x13 line.long 0x0 "GHWPARAMS3,Global Hardware Parameters Register 3 This register contains the hardware configuration options that you can select in the coreConsultant GUI. For a description of each parameter. refer to the 'Parameter Descriptions' chapter in the Databook." bitfld.long 0x0 31. "GHWPARAMS3_31,Reserved" "0,1" newline hexmask.long.byte 0x0 23.--30. 1. "GHWPARAMS3_30_23,`DWC_USB3_CACHE_TOTAL_XFER_RESOURCES" newline hexmask.long.byte 0x0 18.--22. 1. "GHWPARAMS3_22_18,`DWC_USB3_NUM_IN_EPS" newline hexmask.long.byte 0x0 12.--17. 1. "GHWPARAMS3_17_12,`DWC_USB3_NUM_EPS" newline bitfld.long 0x0 11. "GHWPARAMS3_11,`DWC_USB3_ULPI_CARKIT" "0,1" newline bitfld.long 0x0 10. "GHWPARAMS3_10,`DWC_USB3_VENDOR_CTL_INTERFACE" "0,1" newline bitfld.long 0x0 8.--9. "GHWPARAMS3_9_8,Reserved" "0,1,2,3" newline bitfld.long 0x0 6.--7. "GHWPARAMS3_7_6,`DWC_USB3_HSPHY_DWIDTH" "0,1,2,3" newline bitfld.long 0x0 4.--5. "GHWPARAMS3_5_4,`DWC_USB3_FSPHY_INTERFACE" "0,1,2,3" newline bitfld.long 0x0 2.--3. "GHWPARAMS3_3_2,`DWC_USB3_HSPHY_INTERFACE" "0,1,2,3" newline bitfld.long 0x0 0.--1. "GHWPARAMS3_1_0,`DWC_USB3_SSPHY_INTERFACE" "0,1,2,3" line.long 0x4 "GHWPARAMS4,Global Hardware Parameters Register 4 This register contains the hardware configuration options that you can select in the coreConsultant GUI. For a description of each parameter. refer to the 'Parameter Descriptions' chapter in the Databook." hexmask.long.byte 0x4 28.--31. 1. "GHWPARAMS4_31_28,`DWC_USB3_BMU_LSP_DEPTH" newline hexmask.long.byte 0x4 24.--27. 1. "GHWPARAMS4_27_24,`DWC_USB3_BMU_PTL_DEPTH-1" newline bitfld.long 0x4 23. "GHWPARAMS4_23,`DWC_USB3_EN_ISOC_SUPT" "0,1" newline bitfld.long 0x4 22. "GHWPARAMS4_22,Reserved" "0,1" newline bitfld.long 0x4 21. "GHWPARAMS4_21,`DWC_USB3_EXT_BUFF_CONTROL" "0,1" newline hexmask.long.byte 0x4 17.--20. 1. "GHWPARAMS4_20_17,`DWC_USB3_NUM_SS_USB_INSTANCES" newline hexmask.long.byte 0x4 13.--16. 1. "GHWPARAMS4_16_13,`DWC_USB3_HIBER_SCRATCHBUFS Number of external scratchpad buffers the controller requires to save its internal state in the device mode. Each buffer is assumed to be 4KB. The scratchpad buffer array must have this many buffer pointers." newline bitfld.long 0x4 12. "GHWPARAMS4_12,Reserved" "0,1" newline bitfld.long 0x4 11. "GHWPARAMS4_11,Reserved" "0,1" newline bitfld.long 0x4 9.--10. "GHWPARAMS4_10_9,Reserved" "0,1,2,3" newline bitfld.long 0x4 7.--8. "GHWPARAMS4_8_7,Reserved" "0,1,2,3" newline bitfld.long 0x4 6. "GHWPARAMS4_6,Reserved" "0,1" newline hexmask.long.byte 0x4 0.--5. 1. "GHWPARAMS4_5_0,`DWC_USB3_CACHE_TRBS_PER_TRANSFER" line.long 0x8 "GHWPARAMS5,Global Hardware Parameters Register 5 This register contains the hardware configuration options that you can select in the coreConsultant GUI. For a description of each parameter. refer to the 'Parameter Descriptions' chapter in the Databook." hexmask.long.byte 0x8 28.--31. 1. "GHWPARAMS5_31_28,Reserved" newline hexmask.long.byte 0x8 22.--27. 1. "GHWPARAMS5_27_22,`DWC_USB3_DFQ_FIFO_DEPTH" newline hexmask.long.byte 0x8 16.--21. 1. "GHWPARAMS5_21_16,`DWC_USB3_DWQ_FIFO_DEPTH" newline hexmask.long.byte 0x8 10.--15. 1. "GHWPARAMS5_15_10,`DWC_USB3_TXQ_FIFO_DEPTH" newline hexmask.long.byte 0x8 4.--9. 1. "GHWPARAMS5_9_4,`DWC_USB3_RXQ_FIFO_DEPTH" newline hexmask.long.byte 0x8 0.--3. 1. "GHWPARAMS5_3_0,`DWC_USB3_BMU_BUSGM_DEPTH" line.long 0xC "GHWPARAMS6,Global Hardware Parameters Register 6 This register contains the hardware configuration options that you can select in the coreConsultant GUI. For a description of each parameter. refer to the 'Parameter Descriptions' chapter in the Databook." hexmask.long.word 0xC 16.--31. 1. "GHWPARAMS6_31_16,`DWC_USB3_RAM0_DEPTH" newline bitfld.long 0xC 15. "BUSFLTRSSUPPORT,`DWC_USB3_EN_BUS_FILTERS" "0,1" newline bitfld.long 0xC 14. "BCSUPPORT,`DWC_USB3_EN_BC" "0,1" newline bitfld.long 0xC 13. "OTG_SS_SUPPORT,Reserved" "0,1" newline bitfld.long 0xC 12. "ADPSUPPORT,`DWC_USB3_EN_ADP" "0,1" newline bitfld.long 0xC 11. "HNPSUPPORT,Reserved" "0,1" newline bitfld.long 0xC 10. "SRPSUPPORT,Reserved" "0,1" newline bitfld.long 0xC 8.--9. "GHWPARAMS6_9_8,Reserved" "0,1,2,3" newline bitfld.long 0xC 7. "GHWPARAMS6_7,`DWC_USB3_EN_FPGA" "0,1" newline bitfld.long 0xC 6. "GHWPARAMS6_6,`DWC_USB3_EN_DBG_PORTS" "0,1" newline hexmask.long.byte 0xC 0.--5. 1. "GHWPARAMS6_5_0,`DWC_USB3_PSQ_FIFO_DEPTH" line.long 0x10 "GHWPARAMS7,Global Hardware Parameters Register 7 This register contains the hardware configuration options that you can select in the coreConsultant GUI. For a description of each parameter. refer to the 'Parameter Descriptions' chapter in the Databook." hexmask.long.word 0x10 16.--31. 1. "GHWPARAMS7_31_16,`DWC_USB3_RAM2_DEPTH" newline hexmask.long.word 0x10 0.--15. 1. "GHWPARAMS7_15_0,`DWC_USB3_RAM1_DEPTH" group.long (0x60+0x49408)++0x3 line.long 0x0 "GDBGFIFOSPACE,Global Debug Queue/FIFO Space Available Register Bit Bash test should not be done on this debug register." hexmask.long.word 0x0 16.--31. 1. "SPACE_AVAILABLE,SPACE_AVAILABLE" newline hexmask.long.byte 0x0 9.--15. 1. "RESERVED_15_9,Reserved" newline hexmask.long.word 0x0 0.--8. 1. "FIFO_QUEUE_SELECT,FIFO/Queue Select (or) Port-Select - FIFO/Queue Select[8:5] indicates the FIFO/Queue Type - FIFO/Queue Select[4:0] indicates the FIFO/Queue Number For example 9'b0_0010_0001 refers to RxFIFO_1 and 9'b0_0101_1110 refers to TxReqQ_30. -.." rgroup.long (0x64+0x49408)++0xB line.long 0x0 "GDBGLTSSM,Global Debug LTSSM Register In multi-port host configuration. the port-number is defined by Port-Select[3:0] field in the GDBGFIFOSPACE register. Note: - GDBGLTSSM register is not applicable for USB 2.0-only mode. - Bit Bash test should not be.." bitfld.long 0x0 31. "RESERVED_31_31,Reserved" "0,1" newline bitfld.long 0x0 30. "RXELECIDLE,RxElecidle For description of RxElecIdle see table 5-4 'Status Interface Signals' of the PIPE3 Specification." "0,1" newline bitfld.long 0x0 29. "X3_XS_SWAPPING,Reserved" "0,1" newline bitfld.long 0x0 28. "X3_DS_HOST_SHUTDOWN,Reserved" "0,1" newline bitfld.long 0x0 27. "PRTDIRECTION,Reserved" "0,1" newline bitfld.long 0x0 26. "LTDBTIMEOUT,LTDB Timeout (LTDBTimeout)" "0,1" newline hexmask.long.byte 0x0 22.--25. 1. "LTDBLINKSTATE,LTDB Link State (LTDBLinkState)" newline hexmask.long.byte 0x0 18.--21. 1. "LTDBSUBSTATE,LTDB Sub-State (LTDBSubState)" newline bitfld.long 0x0 17. "ELASTICBUFFERMODE,Elastic Buffer Mode (ElasticBufferMode) For field definition refer to Table 5-3 of the PIPE3 specification." "0,1" newline bitfld.long 0x0 16. "TXELECLDLE,Tx Elec Idle (TxElecIdle) For field definition refer to Table 5-3 of the PIPE3 specification." "0,1" newline bitfld.long 0x0 15. "RXPOLARITY,Rx Polarity (RxPolarity) For field definition refer to Table 5-3 of the PIPE3 specification." "0,1" newline bitfld.long 0x0 14. "TXDETRXLOOPBACK,Tx Detect Rx/Loopback (TxDetRxLoopback) For field definition refer to Table 5-3 of the PIPE3 specification." "0,1" newline bitfld.long 0x0 11.--13. "LTDBPHYCMDSTATE,LTSSM PHY command State (LTDBPhyCmdState) - 000: PHY_IDLE (PHY command state is in IDLE. No PHY request pending) - 001: PHY_DET (Request to start Receiver detection) - 010: PHY_DET_3 (Wait for Phy_Status (Receiver detection)) - 011:.." "P1/P2/P3 request),PHY_DET,?,?,?,?,?,?" newline bitfld.long 0x0 9.--10. "POWERDOWN,POWERDOWN (PowerDown) For field definition refer to Table 5-3 of the PIPE3 specification." "0,1,2,3" newline bitfld.long 0x0 8. "RXEQTRAIN,RxEq Train For field definition refer to Table 5-3 of the PIPE3 specification." "0,1" newline bitfld.long 0x0 6.--7. "TXDEEMPHASIS,TXDEEMPHASIS (TxDeemphasis) For field definition refer to Table 5-3 of the PIPE3 specification." "0,1,2,3" newline bitfld.long 0x0 3.--5. "LTDBCLKSTATE,LTSSM Clock State (LTDBClkState) In multi-port host configuration the port number is defined by Port-Select[3:0] field in the GDBGFIFOSPACE register. Note: GDBGLTSSM register is not applicable for USB 2.0-only mode. - 000: CLK_NORM (PHY is.." "CLK_NORM,CLK_TO_P3,?,?,?,?,?,?" newline bitfld.long 0x0 2. "TXSWING,Tx Swing (TxSwing) For field definition refer to Table 5-3 of the PIPE3 specification." "0,1" newline bitfld.long 0x0 1. "RXTERMINATION,Rx Termination (RxTermination) For details on `DWC_USB3_PIPE_RXTERM_RESET_VAL refer to /src/DWC_usb3_params.v" "0,1" newline bitfld.long 0x0 0. "TXONESZEROS,Tx Ones/Zeros (TxOnesZeros) For field definition refer to Table 5-3 of the PIPE3 specification." "0,1" line.long 0x4 "GDBGLNMCC,Global Debug LNMCC Register Bit Bash test should not be done on this debug register." hexmask.long.tbyte 0x4 9.--31. 1. "RESERVED_31_9,Reserved" newline hexmask.long.word 0x4 0.--8. 1. "LNMCC_BERC,This field indicates the bit error rate information for the port selected in the GDBGFIFOSPACE.PortSelect field. This field is for debug purposes only." line.long 0x8 "GDBGBMU,Global Debug BMU Register Bit Bash test should not be done on this debug register." hexmask.long.tbyte 0x8 8.--31. 1. "BMU_BCU,BMU_BCU Debug information" newline hexmask.long.byte 0x8 4.--7. 1. "BMU_DCU,BMU_DCU Debug information" newline hexmask.long.byte 0x8 0.--3. 1. "BMU_CCU,BMU_CCU Debug information" group.long (0x70+0x49408)++0x3 line.long 0x0 "GDBGLSPMUX_HST,Global Debug LSP MUX Register - Host This register is for internal use only. If DWC_USB3_PRESERVE_LOGIC_ANALYZER_SELECT is enabled during controller configuration. then the default values readout is X (Undefined). Bit Bash test should not.." hexmask.long.byte 0x0 24.--31. 1. "RESERVED_31_24,Reserved" newline hexmask.long.byte 0x0 16.--23. 1. "LOGIC_ANALYZER_TRACE,logic_analyzer_trace Port MUX Select Currently only bits[21:16] are used. For details on how the mux controls the debug traces refer to the 'assign logic_analyzer_trace =' code section in the DWC_usb3.v file. A value of 6'h3F drives.." newline rbitfld.long 0x0 14.--15. "RESERVED_15_14,Reserved" "0,1,2,3" newline hexmask.long.word 0x0 0.--13. 1. "HOSTSELECT,Device LSP Select Selects the LSP debug information presented in the GDBGLSP register in host mode." rgroup.long (0x74+0x49408)++0x3 line.long 0x0 "GDBGLSP,Global Debug LSP Register This register is for internal debug purposes only. This register is for internal use only. If DWC_USB3_PRESERVE_LOGIC_ANALYZER_SELECT is enabled during controller configuration. then the default values readout is X.." hexmask.long 0x0 0.--31. 1. "LSPDEBUG,LSP Debug Information" repeat 2. (list 0x0 0x1 )(list 0x0 0x4 ) rgroup.long ($2+0x78+0x49408)++0x3 line.long 0x0 "GDBGEPINFO$1,Global Debug Endpoint Information Register 0 This register is for internal use only. If DWC_USB3_PRESERVE_LOGIC_ANALYZER_SELECT is enabled during controller configuration. then the default values readout is X (Undefined). Bit Bash test.." hexmask.long 0x0 0.--31. 1. "EPDEBUG,Endpoint Debug Information bits[31:0]" repeat.end group.long (0x80+0x49408)++0xF line.long 0x0 "GPRTBIMAP_HSLO,Global High-Speed Port to Bus Instance Mapping Register - Low This is an alternate register for the GPRTBIMAP_HS register. - Register fields are read-write with respect to number of port instantiated. writeAsRead constraint is added to.." hexmask.long.byte 0x0 28.--31. 1. "BINUM8,BINUM8: HS USB Instance Number for Port 8. Application-programmable ID field." newline hexmask.long.byte 0x0 24.--27. 1. "BINUM7,BINUM7: HS USB Instance Number for Port 7. Application-programmable ID field." newline hexmask.long.byte 0x0 20.--23. 1. "BINUM6,BINUM6 USB Instance Number for Port 6. Application-programmable ID field." newline hexmask.long.byte 0x0 16.--19. 1. "BINUM5,BINUM5: HS USB Instance Number for Port 5. Application-programmable ID field." newline hexmask.long.byte 0x0 12.--15. 1. "BINUM4,BINUM4: HS USB Instance Number for Port 4. Application-programmable ID field." newline hexmask.long.byte 0x0 8.--11. 1. "BINUM3,BINUM3: HS USB Instance Number for Port 3. Application-programmable ID field." newline hexmask.long.byte 0x0 4.--7. 1. "BINUM2,BINUM2: HS USB Instance Number for Port 2. Application-programmable ID field." newline hexmask.long.byte 0x0 0.--3. 1. "BINUM1,BINUM1: HS USB Instance Number for Port 1. Application-programmable ID field." line.long 0x4 "GPRTBIMAP_HSHI,Global High-Speed Port to Bus Instance Mapping Register - High This is an alternate register for the GPRTBIMAP_HS register. - Register fields are read-write with respect to number of port instantiated. writeAsRead constraint is added to.." hexmask.long.byte 0x4 28.--31. 1. "RESERVED_31_28,Reserved" newline hexmask.long.byte 0x4 24.--27. 1. "BINUM15,BINUM15: HS USB Instance Number for Port 15. Application-programmable ID field." newline hexmask.long.byte 0x4 20.--23. 1. "BINUM14,BINUM14: HS USB Instance Number for Port 14. Application-programmable ID field." newline hexmask.long.byte 0x4 16.--19. 1. "BINUM13,BINUM13: HS USB Instance Number for Port 13. Application-programmable ID field." newline hexmask.long.byte 0x4 12.--15. 1. "BINUM12,BINUM12: HS USB Instance Number for Port 12. SApplication-programmable ID field." newline hexmask.long.byte 0x4 8.--11. 1. "BINUM11,BINUM11: HS USB Instance Number for 11. Application-programmable ID field." newline hexmask.long.byte 0x4 4.--7. 1. "BINUM10,BINUM10: HS USB Instance Number for Port 10. Application-programmable ID field." newline hexmask.long.byte 0x4 0.--3. 1. "BINUM9,BINUM9: HS USB Instance Number for Port 9. Application-programmable ID field." line.long 0x8 "GPRTBIMAP_FSLO,Global Full-Speed Port to Bus Instance Mapping Register - Low This is an alternate register for the GPRTBIMAP_FS register. - Register fields are read-write with respect to number of port instantiated. writeAsRead constraint is added to.." hexmask.long.byte 0x8 28.--31. 1. "BINUM8,BINUM8: FS USB Instance Number for Port 8. Application-programmable ID field." newline hexmask.long.byte 0x8 24.--27. 1. "BINUM7,BINUM7: FS USB Instance Number for Port 7. Application-programmable ID field." newline hexmask.long.byte 0x8 20.--23. 1. "BINUM6,BINUM6: FS USB Instance Number for Port 6. Application-programmable ID field." newline hexmask.long.byte 0x8 16.--19. 1. "BINUM5,BINUM5: FS USB Instance Number for Port 5. Application-programmable ID field." newline hexmask.long.byte 0x8 12.--15. 1. "BINUM4,BINUM4: FS USB Instance Number for Port 4. Application-programmable ID field." newline hexmask.long.byte 0x8 8.--11. 1. "BINUM3,BINUM3: FS USB Instance Number for Port 3. Application-programmable ID field." newline hexmask.long.byte 0x8 4.--7. 1. "BINUM2,BINUM2: FS USB Instance Number for Port 2. Application-programmable ID field." newline hexmask.long.byte 0x8 0.--3. 1. "BINUM1,BINUM1: FS USB Instance Number for Port 1. Application-programmable ID field." line.long 0xC "GPRTBIMAP_FSHI,Global Full-Speed Port to Bus Instance Mapping Register - High This is an alternate register for the GPRTBIMAP_FS register. - Register fields are read-write with respect to number of port instantiated. writeAsRead constraint is added to.." hexmask.long.byte 0xC 28.--31. 1. "RESERVED_31_28,Reserved" newline hexmask.long.byte 0xC 24.--27. 1. "BINUM15,BINUM15: FS USB Instance Number for Port 15. Application-programmable ID field" newline hexmask.long.byte 0xC 20.--23. 1. "BINUM14,BINUM14: FS USB Instance Number for Port 14. Application-programmable ID field" newline hexmask.long.byte 0xC 16.--19. 1. "BINUM13,BINUM13: FS USB Instance Number for Port 13. Application-programmable ID field" newline hexmask.long.byte 0xC 12.--15. 1. "BINUM12,BINUM12: FS USB Instance Number for Port 12. Application-programmable ID field" newline hexmask.long.byte 0xC 8.--11. 1. "BINUM11,BINUM11: FS USB Instance Number for Port 11. Application-programmable ID field" newline hexmask.long.byte 0xC 4.--7. 1. "BINUM10,BINUM10: FS USB Instance Number for Port 10. Application-programmable ID field" newline hexmask.long.byte 0xC 0.--3. 1. "BINUM9,BINUM9: FS USB Instance Number for Port 9. Application-programmable ID field." repeat 2. (list 0x5E 0x62 )(list 0x0 0x4 ) rgroup.long ($2+0x94+0x49408)++0x3 line.long 0x0 "RESERVED_$1,Future Reserved Register at offset 0x94" hexmask.long 0x0 0.--31. 1. "RESERVED_31_0,Future use Register field" repeat.end group.long (0x9C+0x49408)++0x3 line.long 0x0 "GUCTL2,Global User Control Register 2: This register provides a few options for the software to control the controller behavior in the Host and device mode. Most of the options are used to improve inter-operability with different hosts and devices." hexmask.long.byte 0x0 26.--31. 1. "RESERVED_31_26,Reserved" newline hexmask.long.byte 0x0 19.--25. 1. "EN_HP_PM_TIMER,This register field is used to set new HP and PM timers. - To enable PM timer set GUCTL2[19] bit as 1. - To enable HP timer set GUCTL2[20] bit as 1. Default value of HP timer is 4us when HP PM timer is not enabled; when new HP timer is.." newline hexmask.long.byte 0x0 15.--18. 1. "NOLOWPWRDUR,No Low Power Duration (NOLOWPWRDUR) This bit is applicable for device mode only and is ignored in host mode. After starting a transfer on a SS ISOC endpoint the application must program these bits to prevent the device to lose frame.." newline bitfld.long 0x0 14. "RST_ACTBITLATER,Enable clearing of the command active bit for the ENDXFER command after the command execution is completed. This bit is valid in device mode only." "0,1" newline rbitfld.long 0x0 13. "RESERVED_13,Reserved for future use" "0,1" newline bitfld.long 0x0 12. "ENABLEEPCACHEEVICT,Enable Evicting Endpoint cache after Flow Control for bulk endpoints. In 3.00a release a performance enhancement was done to keep the non-stream capable bulk IN endpoint in cache after flow control. Setting this bit will disable this.." "0,1" newline bitfld.long 0x0 11. "DISABLECFC,Disable xHCI Errata Feature Contiguous Frame ID Capability This field controls the xHCI Errata feature Contiguous FrameID capability. When set the xHCI HCCPARAMS1 bit 11 will be set to 0 indicating that CFC is not supported. Disable this.." "0,1" newline hexmask.long.byte 0x0 5.--10. 1. "RXPINGDURATION,Recieve Ping Maximum Duration This field is relevant to Host mode and controls the maximum duration of received LFPS to be treated as a Ping LFPS. The Max duration of the Ping LFPS is controlled by programming this value and is in terms of.." newline hexmask.long.byte 0x0 0.--4. 1. "TXPINGDURATION,Transmit Ping Maximum Duration This field is relevant to Device mode and controls the maximum duration for which the controller should instruct the PHY to transmit a Ping LFPS. The duration of the Ping LFPS is controlled by programming.." group.long (0x100+0x49408)++0x3 line.long 0x0 "GUSB2PHYCFG,Global USB2 PHY Configuration Register The application must program this register before starting any transactions on either the SoC bus or the USB. In Device-only configurations. only one register is needed. In Host mode. per-port registers.." bitfld.long 0x0 31. "PHYSOFTRST,UTMI PHY Soft Reset (PHYSoftRst) Causes the usb2phy_reset signal to be asserted to reset a UTMI PHY. Not applicable to ULPI because ULPI PHYs are reset via their FunctionControl.Reset register and the controller automatically writes to this.." "0,1" newline bitfld.long 0x0 30. "U2_FREECLK_EXISTS,U2_FREECLK_EXISTS Specifies whether your USB 2.0 PHY provides a free-running PHY clock which is active when the clock control input is active. If your USB 2.0 PHY provides a free-running PHY clock it must be connected to the.." "USB 2,USB 2" newline bitfld.long 0x0 29. "ULPI_LPM_WITH_OPMODE_CHK,ULPI_LPM_WITH_OPMODE_CHK Support the LPM over ULPI without NOPID token to the ULPI PHY. If this bit is set the ULPI PHY is expected to qualify the EXT PID with OPMODE=2'b00 for LPM and not treat it as a NOPID. Check with your.." "A NOPID is sent before sending an EXTPID for LPM;,An EXTPID is sent without previously sending a.." newline rbitfld.long 0x0 27.--28. "HSIC_CON_WIDTH_ADJ,HSIC_CON_WIDTH_ADJ This bit is used in the HSIC device mode of operation. By default the connect duration for the HSIC device controller is thrice the strobe period. You can change this duration to 4 5 or 6 times the strobe period.." "0,1,2,3" newline rbitfld.long 0x0 26. "INV_SEL_HSIC,INV_SEL_HSIC The application driver uses this bit to control the HSIC enable/disable function. When set to '1' this bit overrides and functionally inverts the 'if_select_hsic' input signal. If {INV_SEL_HSIC if_select_hsic} is: - 00: HSIC.." "HSIC Capability is disabled,HSIC Capability is enabled" newline bitfld.long 0x0 25. "OVRD_FSLS_DISC_TIME,Overriding the FS/LS disconnect time to 32us. - If this value is 0 the FS/LS disconnect time is set to 2.5us as per the USB specification. - If this value is non-0 the disconnect detection time is set to 32us. Normally this value.." "0,1" newline bitfld.long 0x0 22.--24. "LSTRD,LS Turnaround Time (LSTRDTIM) This field indicates the value of the Rx-to-Tx packet gap for LS devices. The encoding is as follows: - 0: 2 bit times - 1: 2.5 bit times - 2: 3 bit times - 3: 3.5 bit times - 4: 4 bit times - 5: 4.5 bit times - 6: 5.." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 19.--21. "LSIPD,LS Inter-Packet Time (LSIPD) This field indicates the value of Tx-to-Tx packet gap for LS devices. The encoding is as follows: - 0: 2 bit times - 1: 2.5 bit times - 2: 3 bit times - 3: 3.5 bit times - 4: 4 bit times - 5: 4.5 bit times - 6: 5 bit.." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 18. "ULPIEXTVBUSINDIACTOR,ULPI External VBUS Indicator (ULPIExtVbusIndicator) Indicates the ULPI PHY VBUS over-current indicator. - 1'b0: PHY uses an internal VBUS valid comparator. - 1'b1: PHY uses an external VBUS valid comparator. Valid only when RTL.." "PHY uses an internal VBUS valid comparator,PHY uses an external VBUS valid comparator" newline bitfld.long 0x0 17. "ULPIEXTVBUSDRV,ULPI External VBUS Drive (ULPIExtVbusDrv) Selects supply source to drive 5V on VBUS in the ULPI PHY. - 1'b0: PHY drives VBUS with internal charge pump (default). - 1'b1: PHY drives VBUS with an external supply. (Only when RTL parameter.." "PHY drives VBUS with internal charge pump,PHY drives VBUS with an external supply" newline rbitfld.long 0x0 16. "RESERVED_16,Reserved" "0,1" newline bitfld.long 0x0 15. "ULPIAUTORES,ULPI Auto Resume (ULPIAutoRes) Sets the AutoResume bit in Interface Control register on the ULPI PHY. - 1'b0: PHY does not use the AutoResume feature. - 1'b1: PHY uses the AutoResume feature. Valid only when RTL parameter.." "PHY does not use the AutoResume feature,PHY uses the AutoResume feature" newline rbitfld.long 0x0 14. "RESERVED_14,Reserved" "0,1" newline hexmask.long.byte 0x0 10.--13. 1. "USBTRDTIM,USB 2.0 Turnaround Time (USBTrdTim) Sets the turnaround time in PHY clocks. Specifies the response time for a MAC request to the Packet FIFO Controller (PFC) to fetch data from the DFIFO (SPRAM). The following are the required values for the.." newline bitfld.long 0x0 9. "XCVRDLY,Transceiver Delay: Enables a delay between the assertion of the UTMI/ULPI Transceiver Select signal (for HS) and the assertion of the TxValid signal during a HS Chirp. When this bit is set to 1 a delay (of approximately 2.5 us) is introduced.." "0,1" newline bitfld.long 0x0 8. "ENBLSLPM,Enable utmi_sleep_n and utmi_l1_suspend_n (EnblSlpM) The application uses this bit to control utmi_sleep_n and utmi_l1_suspend_n assertion to the PHY in the L1 state. - 1'b0: utmi_sleep_n and utmi_l1_suspend_n assertion from the controller is.." "utmi_sleep_n and utmi_l1_suspend_n assertion..,utmi_sleep_n and utmi_l1_suspend_n assertion.." newline bitfld.long 0x0 7. "PHYSEL,USB 2.0 High-Speed PHY or USB 1.1 Full-Speed Serial Transceiver Select The application uses this bit to select a high-speed PHY or a full-speed transceiver. - 1'b0: USB 2.0 high-speed UTMI+ or ULPI PHY. This bit is always 0 with Write Only.." "USB 2,USB 1" newline bitfld.long 0x0 6. "SUSPENDUSB20,Suspend USB2.0 HS/FS/LS PHY (SusPHY) When set USB2.0 PHY enters Suspend mode if Suspend conditions are valid. For DRD configurations it is recommended that this bit is set to 0 during coreConsultant configuration. If it is set to 1 then.." "0,1" newline rbitfld.long 0x0 5. "FSINTF,Full-Speed Serial Interface Select (FSIntf) The application uses this bit to select a unidirectional or bidirectional USB 1.1 full-speed serial transceiver interface. - 1'b0: 6-pin unidirectional full-speed serial interface. This bit is set to 0.." "0,1" newline rbitfld.long 0x0 4. "ULPI_UTMI_SEL,ULPI or UTMI+ Select (ULPI_UTMI_Sel) The application uses this bit to select a UTMI+ or ULPI Interface. - 1'b0: UTMI+ Interface - 1'b1: ULPI Interface This bit is writable only if UTMI+ and ULPI is specified for High-Speed PHY Interface(s).." "UTMI+ Interface,ULPI Interface" newline bitfld.long 0x0 3. "PHYIF,PHY Interface (PHYIf) If UTMI+ is selected the application uses this bit to configure the controller to support a UTMI+ PHY with an 8- or 16-bit interface. - 1'b0: 8 bits - 1'b1: 16 bits ULPI Mode: 1'b0 Note: - All the enabled 2.0 ports must have.." "0,1" newline bitfld.long 0x0 0.--2. "TOUTCAL,HS/FS Timeout Calibration (TOutCal) The number of PHY clocks as indicated by the application in this field is multiplied by a bit-time factor; this factor is added to the high-speed/full-speed interpacket timeout duration in the controller to.." "0,1,2,3,4,5,6,7" rgroup.long (0x140+0x49408)++0x3 line.long 0x0 "GUSB2I2CCTL,Reserved Register" hexmask.long 0x0 0.--31. 1. "RESERVED_31_0,Reserved for future use" group.long (0x180+0x49408)++0x3 line.long 0x0 "GUSB2PHYACC_ULPI,Global USB 2.0 ULPI PHY Vendor Control Register The application uses this register to access the PHY registers. This register is always implemented when the ULPI PHY Interface is enabled during coreConsultant configuration (parameter.." hexmask.long.byte 0x0 27.--31. 1. "RESERVED_31_27,Reserved" newline rbitfld.long 0x0 26. "DISUIPIDRVR,DISUIPIDRVR" "0,1" newline bitfld.long 0x0 25. "NEWREGREQ,New Register Request The application sets this bit for a new vendor control access. Setting this bit to 1 asserts the utmi_vcontrolload_n (1'b0) on the UTMI interface." "0,1" newline rbitfld.long 0x0 24. "VSTSDONE,VSTSDONE" "0,1" newline bitfld.long 0x0 23. "VSTSBSY,VSTSBSY" "0,1" newline bitfld.long 0x0 22. "REGWR,Register Write The application sets this bit for register writes and clears it for register reads. Note: This bit is applicable for ULPI register read/write access only." "0,1" newline hexmask.long.byte 0x0 16.--21. 1. "REGADDR,Register Address The 6-bit PHY register address for immediate PHY Register Set access. Set to 6'h2F for Extended PHY Register Set access. Note: These bits are applicable for ULPI only." newline hexmask.long.byte 0x0 8.--15. 1. "EXTREGADDR,EXTREGADDR" newline hexmask.long.byte 0x0 0.--7. 1. "REGDATA,REGDATA" group.long (0x1C0+0x49408)++0x3 line.long 0x0 "GUSB3PIPECTL,Global USB 3.0 PIPE Control Register The application uses this register to configure the USB3 PHY and PIPE interface. Device-only configuration requires only one register. In Host mode. registers are implemented for each port. For more.." bitfld.long 0x0 31. "PHYSOFTRST,USB3 PHY Soft Reset After setting this bit to '1' the software needs to clear this bit. For more information refer to Figure 'Software Resets and PHY Clock Sequencing and Requirements' in the Databook." "0,1" newline bitfld.long 0x0 30. "HSTPRTCMPL,HstPrtCmpl This feature tests the PIPE PHY compliance patterns without having to have a test fixture on the USB 3.0 cable. This bit enables placing the SS port link into a compliance state. By default this bit must be set to 1'b0. In.." "0,1" newline bitfld.long 0x0 29. "U2P3OK,P3 OK for SSInactive (SSIP3ok) - 0: During link state SS.Inactive put PHY in P2 (Default) - 1: During link state SS.Inactive put PHY in P3." "During link state SS,During link state SS" newline bitfld.long 0x0 28. "DISRXDETP3,Disabled receiver detection in P3 (DisRxDetP3) - 0: If PHY is in P3 and controller needs to perform receiver detection The controller performs receiver detection in P3. (Default) - 1: If PHY is in P3 and controller needs to perform receiver.." "If PHY is in P3 and controller needs to perform..,If PHY is in P3 and controller needs to perform.." newline bitfld.long 0x0 27. "UX_EXIT_IN_PX,Ux Exit in Px (Ux_exit_in_Px) - 0: The controller does U1/U2/U3 exit in PHY power state P0 (default behavior). - 1: The controller does U1/U2/U3 exit in PHY power state P1/P2/P3 respectively. Note: This bit is used by third-party SS PHY. It.." "The controller does U1/U2/U3 exit in PHY power..,The controller does U1/U2/U3 exit in PHY power.." newline bitfld.long 0x0 26. "PING_ENHANCEMENT_EN,Ping Enhancement Enable (ping_enhancement_en) When set the Downstream port U1 ping receive timeout becomes 500 ms instead of 300 ms. Minimum Ping.LFPS receive duration is 8 ns (one mac3_clk). This field is valid for the downstream.." "0,1" newline bitfld.long 0x0 25. "U1U2EXITFAIL_TO_RECOV,U1U2exitfail to Recovery (u1u2exitfail_to_recov) When set and U1/U2 LFPS handshake fails the LTSSM transitions from U1/U2 to Recovery instead of SS Inactive. If Recovery fails then the LTSSM can enter SS.Inactive. This is an.." "0,1" newline bitfld.long 0x0 24. "REQUEST_P1P2P3,Always Request P1/P2/P3 for U1/U2/U3 (request_p1p2p3) When set the controller always requests PHY power change from P0 to P1/P2/P3 during U0 to U1/U2/U3 transition. If this bit is 0 and immediate Ux exit (remotely initiated or locally.." "0,1" newline bitfld.long 0x0 23. "STARTRXDETU3RXDET,Start Receiver Detection in U3/Rx.Detect (StartRxdetU3RxDet) If DWC_USB3_GUSB3PIPECTL_INIT[22] is set and the link is in either U3 or Rx.Detect state the controller starts receiver detection on the rising edge of this bit. This can.." "0,1" newline bitfld.long 0x0 22. "DISRXDETU3RXDET,Disable Receiver Detection in U3/Rx.Det When set the controller does not handle receiver detection in either U3 or Rx.Detect states. DWC_USB3_GUSB3PIPECTL_INIT[23] must be used to start receiver detection manually. This bit can only be.." "0,1" newline bitfld.long 0x0 19.--21. "DELAYP1P2P3,Delay P1P2P3 Delay P0 to P1/P2/P3 request when entering U1/U2/U3 until (DWC_USB3_GUSB3PIPECTL_INIT[21:19]*8) 8B10B error occurs or Pipe3_RxValid drops to 0. DWC_USB3_GUSB3PIPECTL_INIT[18] must be 1 to enable this functionality." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 18. "DELAYP1TRANS,Delay PHY power change from P0 to P1/P2/P3 when link state changing from U0 to U1/U2/U3 respectively. - 1'b1: When entering U1/U2/U3 delay the transition to P1/P2/P3 until the pipe3 signals Pipe3_RxElecIdle is 1 and pipe3_RxValid is 0 -.." "When entering U1/U2/U3,When entering U1/U2/U3" newline bitfld.long 0x0 17. "SUSPENDENABLE,Suspend USB3.0 SS PHY (Suspend_en) When set and if Suspend conditions are valid the USB 3.0 PHY enters Suspend mode. For DRD configurations it is recommended that this bit is set to '0' during coreConsultant configuration. If it is set.." "0,1" newline rbitfld.long 0x0 15.--16. "DATWIDTH,PIPE Data Width (DatWidth) - 2'b00: 32 bits - 2'b01: 16 bits One clock after reset these bits receive the value seen on the pipe3_DataBusWidth. The simulation testbench uses the coreConsultant parameter to configure the VIP. These bits in the.." "0,1,2,3" newline bitfld.long 0x0 14. "ABORTRXDETINU2,Abort Rx Detect in U2 (AbortRxDetInU2) When set and the link state is U2 the controller will abort receiver detection if it receives U2 exit LFPS from the remote link partner. This bit is for the downstream port only. Note: This bit is.." "0,1" newline bitfld.long 0x0 13. "SKIPRXDET,Skip Rx Detect: When set the controller skips Rx Detection if pipe3_RxElecIdle is low. Skip is defined as waiting for the appropriate timeout then repeating the operation." "0,1" newline bitfld.long 0x0 12. "LFPSP0ALGN,LFPS P0 Align: When set - The controller deasserts LFPS transmission on the clock edge that it requests Phy power state 0 when exiting U1 U2 or U3 low power states. Otherwise LFPS transmission is asserted one clock earlier. - The.." "0,1" newline bitfld.long 0x0 11. "P3P2TRANOK,P3 P2 Transitions OK (P3P2TranOK) When set the controller transitions directly from Phy power state P2 to P3 or from state P3 to P2. When not set P0 is always entered as an intermediate state during transitions between P2 and P3 as defined.." "0,1" newline bitfld.long 0x0 10. "P3EXSIGP2,P3 Exit Signal in P2 (P3ExSigP2) When this bit is set the controller always changes the PHY power state to P2 before attempting a U3 exit handshake. This bit is used only for some non-Synopsys PHYs that cannot do LFPS in P3. Note: This bit is.." "0,1" newline bitfld.long 0x0 9. "LFPSFILTER,LFPS Filter (LFPSFilt) When set filter LFPS reception with pipe3_RxValid in PHY power state P0 that is ignore LFPS reception from the PHY unless both pipe3_Rxelecidle and pipe3_RxValid are deasserted." "0,1" newline bitfld.long 0x0 8. "RX_DETECT_TO_POLLING_LFPS_CONTROL,RX_DETECT to Polling.LFPS Control - 1'b0 (Default): Enables a 400us delay to start Polling LFPS after RX_DETECT. This allows VCM offset to settle to a proper level. - 1'b1: Disables the 400us delay to start Polling LFPS.." "?,Disables the 400us delay to start Polling LFPS.." newline bitfld.long 0x0 7. "SSICEN,This field is not used." "0,1" newline bitfld.long 0x0 6. "TX_SWING,Tx Swing (TxSwing) Refer to the PIPE3 specification." "0,1" newline bitfld.long 0x0 3.--5. "TX_MARGIN,Tx Margin[2:0] (TxMargin) Refer to Table 5-3 of the PIPE3 Specification." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 1.--2. "SS_TX_DE_EMPHASIS,Tx Deemphasis (TxDeemphasis) The value driven to the PHY is controlled by the LTSSM during USB3 Compliance mode. (Refer to Table 5-3 of the PIPE3 specification.)" "0,1,2,3" newline bitfld.long 0x0 0. "ELASTIC_BUFFER_MODE,Elastic Buffer Mode (ElasticBufferMode) (Refer to Table 5-3 of the PIPE3 specification.)" "0,1" group.long (0x200+0x49408)++0x3 line.long 0x0 "GTXFIFOSIZ0,Global Transmit FIFO Size Register This register specifies the RAM start address and depth (both in MDWIDTH-bit words) for each implemented TxFIFO. The number of TxFIFOs depends on the configuration parameters including the number of Device.." hexmask.long.word 0x0 16.--31. 1. "TXFSTADDR_N,Transmit FIFOn RAM Start Address This field contains the memory start address for TxFIFOn in MDWIDTH-bit words." newline hexmask.long.word 0x0 0.--15. 1. "TXFDEP_N,TxFIFO Depth This field contains the depth of TxFIFOn in MDWIDTH-bit words. - Minimum value: 32 - Maximum value: 32 768 For more information see 'Integrating the Controller' chapter in the User Guide." repeat 6. (list 0x1 0x3 0x4 0x5 0x6 0x7 )(list 0x0 0x8 0xC 0x10 0x14 0x18 ) group.long ($2+0x204+0x49408)++0x3 line.long 0x0 "GTXFIFOSIZ$1,Register GTXFIFOSIZ 1" hexmask.long.word 0x0 16.--31. 1. "TXFSTADDR_N,Transmit FIFOn RAM Start Address This field contains the memory start address for TxFIFOn in MDWIDTH-bit words." newline hexmask.long.word 0x0 0.--15. 1. "TXFDEP_N,TXFDEP_N" repeat.end group.long (0x208+0x49408)++0x3 line.long 0x0 "GTXFIFOSIZ2,Transmit FIFOn RAM Start Address This field contains the memory start address for TxFIFOn in MDWIDTH-bit words." hexmask.long.word 0x0 16.--31. 1. "TXFSTADDR_N,Transmit FIFOn RAM Start Address This field contains the memory start address for TxFIFOn in MDWIDTH-bit words." newline hexmask.long.word 0x0 0.--15. 1. "TXFDEP_N,TxFIFO Depth This field contains the depth of TxFIFOn in MDWIDTH-bit words. - Minimum value: 32 - Maximum value: 32 768 For more information see 'Integrating the Controller' chapter in the User Guide." group.long (0x280+0x49408)++0x3 line.long 0x0 "GRXFIFOSIZ0,Global Receive FIFO Size Register This register specifies the RAM start address and depth (both in MDWIDTH-bit words) for each implemented RxFIFO. The number of RxFIFOs depends on the configuration parameters including the number of Host Bus.." hexmask.long.word 0x0 16.--31. 1. "RXFSTADDR_N,RxFIFOn RAM Start Address (RxFStAddr_n) This field contains the memory start address for RxFIFOn in MDWIDTH-bit words." newline hexmask.long.word 0x0 0.--15. 1. "RXFDEP_N,RxFIFO Depth (RxFDep_n) This field contains the depth of RxFIFOn in MDWIDTH-bit words. - Minimum value: 32 - Maximum value: 16 384" repeat 2. (list 0x1 0x2 )(list 0x0 0x4 ) group.long ($2+0x284+0x49408)++0x3 line.long 0x0 "GRXFIFOSIZ$1,Register" hexmask.long.word 0x0 16.--31. 1. "RXFSTADDR_N,RXFSTADDR_N" newline hexmask.long.word 0x0 0.--15. 1. "RXFDEP_N,RxFIFO Depth This field contains the depth of RxFIFOn in MDWIDTH-bit words. - Minimum value: 32 - Maximum value: 16 384" repeat.end group.long (0x300+0x49408)++0xF line.long 0x0 "GEVNTADRLO,Global Event Buffer Address (Low) Register This is an alternate register for the GEVNTADRn register." hexmask.long 0x0 0.--31. 1. "EVNTADRLO,Event Buffer Address (EvntAdrLo) Holds the lower 32 bits of start address of the external memory for the Event Buffer. During operation hardware does not update this address." line.long 0x4 "GEVNTADRHI,Global Event Buffer Address (High) Register This is an alternate register for the GEVNTADRn register." hexmask.long 0x4 0.--31. 1. "EVNTADRHI,Event Buffer Address (EvntAdrHi) Holds the higher 32 bits of start address of the external memory for the Event Buffer. During operation hardware does not update this address." line.long 0x8 "GEVNTSIZ,Global Event Buffer Size Register This register holds the Event Buffer Size and the Event Interrupt Mask bit. During power-on initialization. software must initialize the size with the number of bytes allocated for the Event Buffer. The Event.." bitfld.long 0x8 31. "EVNTINTRPTMASK,Event Interrupt Mask (EvntIntMask). When set to '1' this prevents the interrupt from being generated. However even when the mask is set the events are queued." "0,1" newline hexmask.long.word 0x8 16.--30. 1. "RESERVED_30_16,Reserved" newline hexmask.long.word 0x8 0.--15. 1. "EVENTSIZ,Event Buffer Size in bytes (EVNTSiz) Holds the size of the Event Buffer in bytes; must be a multiple of four. This is programmed by software once during initialization. The minimum size of the event buffer is 32 bytes." line.long 0xC "GEVNTCOUNT,Global Event Buffer Count Register This register holds the number of valid bytes in the Event Buffer. During initialization. software must initialize the count by writing 0 to the Event Count field. Each time the hardware writes a new event to.." bitfld.long 0xC 31. "EVNT_HANDLER_BUSY,Event Handler Busy Device software event handler busy indication. The controller sets this bit when the interrupt line is asserted due to pending events. Software clears this bit (with 1'b1) when it has finished processing the events.." "0,1" newline hexmask.long.word 0xC 16.--30. 1. "RESERVED_30_16,Reserved" newline hexmask.long.word 0xC 0.--15. 1. "EVNTCOUNT,Event Count (EVNTCount) When read returns the number of valid events in the Event Buffer (in bytes). When written hardware decrements the count by the value written. When Interrupt moderation is enabled (that is DEVICE_IMODI!= 0) the.." group.long (0x50C+0x49408)++0x7 line.long 0x0 "GUCTL3,Global User Control Register 3 This register provides a few options for the software to control the controller behavior in the Host mode. Most of the options are used to improve host inter-operability with different devices." hexmask.long.word 0x0 17.--31. 1. "RESERVED_31_17,Reserved" newline bitfld.long 0x0 16. "SCH_PING_EARLY,Enable SuperSpeed Ping Transaction Packet scheduling early in the microframe. This bit is valid in Host mode only." "0,1" newline hexmask.long.word 0x0 0.--15. 1. "RESERVED_15_0,Reserved" line.long 0x4 "GTXFIFOPRIDEV,Global Device TX FIFO DMA Priority Register This register specifies the relative DMA priority level among the Device TXFIFOs (one per IN endpoint). Each register bit[n] controls the priority (1: high. 0: low) of each TXFIFO[n]. When.." hexmask.long.tbyte 0x4 8.--31. 1. "RESERVED_31_N,Reserved" newline hexmask.long.byte 0x4 0.--7. 1. "GTXFIFOPRIDEV,Device TxFIFO priority" group.long (0x518+0x49408)++0xF line.long 0x0 "GTXFIFOPRIHST,Global Host TX FIFO DMA Priority Register This register specifies the relative DMA priority level among the Host TXFIFOs (one per USB bus instance) within the associated speed group (SS or HS/FSLS). Each register bit[n] controls the.." hexmask.long 0x0 4.--31. 1. "RESERVED_31_16,Reserved" newline hexmask.long.byte 0x0 0.--3. 1. "GTXFIFOPRIHST,Host TxFIFO priority" line.long 0x4 "GRXFIFOPRIHST,Global Host RX FIFO DMA Priority Register This register specifies the relative DMA priority level among the Host RXFIFOs (one per USB bus instance) within the associated speed group (SS or HS/FSLS). Each register bit[n] controls the.." hexmask.long 0x4 3.--31. 1. "RESERVED_31_16,Reserved" newline bitfld.long 0x4 0.--2. "GRXFIFOPRIHST,Host RxFIFO priority" "0,1,2,3,4,5,6,7" line.long 0x8 "GFIFOPRIDBC,Global Host Debug Capability DMA Priority Register This register specifies the relative priority of the RXFIFOs and TXFIFOs associated with the DbC mode. It overrides the priority assigned in the corresponding indexes of the Host RXFIFO and.." hexmask.long 0x8 2.--31. 1. "RESERVED_31_2,Reserved" newline bitfld.long 0x8 0.--1. "GFIFOPRIDBC,Host DbC DMA priority" "0,1,2,3" line.long 0xC "GDMAHLRATIO,Global Host FIFO DMA High-Low Priority Ratio Register This register specifies the relative priority of the SS FIFOs with respect to the HS/FSLS FIFOs. The DMA arbiter prioritizes the HS/FSLS round-robin arbiter group every DMA High-Low.." hexmask.long.tbyte 0xC 13.--31. 1. "RESERVED_31_13,Reserved" newline hexmask.long.byte 0xC 8.--12. 1. "HSTRXFIFO,Host RXFIFO DMA High-Low Priority" newline rbitfld.long 0xC 5.--7. "RESERVED_7_5,Reserved" "0,1,2,3,4,5,6,7" newline hexmask.long.byte 0xC 0.--4. 1. "HSTTXFIFO,Host TXFIFO DMA High-Low Priority" group.long (0x530+0x49408)++0x3 line.long 0x0 "GFLADJ,Global Frame Length Adjustment Register This register provides options for the software to control the controller behavior with respect to SOF (Start of Frame) and ITP (Isochronous Timestamp Packet) timers and frame timer functionality. It.." bitfld.long 0x0 31. "GFLADJ_REFCLK_240MHZDECR_PLS1,GFLADJ_REFCLK_240MHZDECR_PLS1 This field indicates that the decrement value that the controller applies for each ref_clk must be GFLADJ_REFCLK_240MHZ_DECR and GFLADJ_REFCLK_240MHZ_DECR +1 alternatively on each ref_clk. Set.." "0,1" newline hexmask.long.byte 0x0 24.--30. 1. "GFLADJ_REFCLK_240MHZ_DECR,This field indicates the decrement value that the controller applies for each ref_clk in order to derive a frame timer in terms of a 240-MHz clock. This field must be programmed to a non-zero value only if GFLADJ_REFCLK_LPM_SEL.." newline bitfld.long 0x0 23. "GFLADJ_REFCLK_LPM_SEL,This bit enables the functionality of running SOF/ITP counters on the ref_clk. This bit must not be set to '1' if GCTL.SOFITPSYNC bit is set to '1'. Similarly if GFLADJ_REFCLK_LPM_SEL set to '1' GCTL.SOFITPSYNC must not be set to.." "0,1" newline rbitfld.long 0x0 22. "RESERVED_22,Reserved for future use" "0,1" newline hexmask.long.word 0x0 8.--21. 1. "GFLADJ_REFCLK_FLADJ,This field indicates the frame length adjustment to be applied when SOF/ITP counter is running on the ref_clk. This register value is used to adjust the ITP interval when GCTL[SOFITPSYNC] is set to '1'; SOF and ITP interval when.." newline bitfld.long 0x0 7. "GFLADJ_30MHZ_SDBND_SEL,GFLADJ_30MHZ_SDBND_SEL This field selects whether to use the input signal fladj_30mhz_reg or the GFLADJ.GFLADJ_30MHZ to adjust the frame length for the SOF/ITP. When this bit is set to - 1 the controller uses the register field.." "0,1" newline rbitfld.long 0x0 6. "RESERVED_6,Reserved for future use" "0,1" newline hexmask.long.byte 0x0 0.--5. 1. "GFLADJ_30MHZ,GFLADJ_30MHZ This field indicates the value that is used for frame length adjustment instead of considering from the sideband input signal fladj_30mhz_reg. This enables post-silicon frame length adjustment in case the input signal.." group.long (0x540+0x49408)++0x3 line.long 0x0 "GUSB2RHBCTL,Global USB 2.0 Root Hub Control Register The application must program this register before starting any transactions on the USB if a non-default value is desired. In Host mode. per-port registers are implemented." hexmask.long 0x0 4.--31. 1. "RESERVED_31_4,Reserved" newline hexmask.long.byte 0x0 0.--3. 1. "OVRD_L1TIMEOUT,Overriding the driver programmed L1TIMEOUT value. If this value is 0 the L1 Timeout value is taken from the xHCI PORTHLPMC register. If this value is non-0 then this will override the L1 Timeout value programmed in the xHCI PORTHLPMC.." tree.end tree "DWC_usb3_block_ecc (USB 3.0 ECC Register Block)" rgroup.long (0x850+0x53248)++0xB line.long 0x0 "BRSERRCNT,Block RAM Single Bit Error Count. 8 bit count for each of the 3 RAMs." hexmask.long.byte 0x0 24.--31. 1. "RESERVED_31_24,Reserved" hexmask.long.byte 0x0 16.--23. 1. "RAM2SERRCNT,RAM2 Single bit Error Count" hexmask.long.byte 0x0 8.--15. 1. "RAM1SERRCNT,RAM1 Single bit Error Count" hexmask.long.byte 0x0 0.--7. 1. "RAM0SERRCNT,RAM0 Single bit Error Count" line.long 0x4 "BRMERRCNT,Block RAM Multiple Bit Error Count. 8 bit count for each of the 3 RAMs." hexmask.long.byte 0x4 24.--31. 1. "RESERVED_31_24,Reserved" hexmask.long.byte 0x4 16.--23. 1. "RAM2MERRCNT,RAM2 Multiple bit Error Count" hexmask.long.byte 0x4 8.--15. 1. "RAM1MERRCNT,RAM1 Multiple bit Error Count" hexmask.long.byte 0x4 0.--7. 1. "RAM0MERRCNT,RAM0 Multiple bit Error Count" line.long 0x8 "BRMECCERR,Block RAM ECC Error Vector Register" hexmask.long.tbyte 0x8 8.--31. 1. "RESERVED_31_8,Reserved" bitfld.long 0x8 7. "RAMSERR,RAM Single bit Error Status" "0,1" bitfld.long 0x8 6. "RAMMERR,RAM Multiple bit Error Status" "0,1" bitfld.long 0x8 3.--5. "RAMSERRVEC,RAM Single Error Vector" "0,1,2,3,4,5,6,7" bitfld.long 0x8 0.--2. "RAMMERRVEC,RAM Multiple Error Vector" "0,1,2,3,4,5,6,7" group.long (0x85C+0x53248)++0x3 line.long 0x0 "BRERRCTL,Block RAM ECC Error Control Register" hexmask.long 0x0 4.--31. 1. "RESERVED_31_4,Reserved" bitfld.long 0x0 3. "ECCERRINJECT,This bit should be used for testing purposes only. - 1: Inject ECC error - 0: No ECC error injected" "No ECC error injected,Inject ECC error" bitfld.long 0x0 2. "ECCEN,ECC Enable (1) or Disable (0)" "0,1" bitfld.long 0x0 1. "RSERRCLR,RAM Single bit Error Clear" "0,1" bitfld.long 0x0 0. "RMERRCLR,RAM Multiple bit Error Clear" "0,1" rgroup.long (0x860+0x53248)++0xB line.long 0x0 "BRAM0ADDRERR,Block RAM Address of RAM0 having uncorrectable error" hexmask.long.word 0x0 16.--31. 1. "RESERVED_31_16,Reserved" hexmask.long.word 0x0 0.--15. 1. "RAM0ADDRLOC,RAM0 Address Location" line.long 0x4 "BRAM1ADDRERR,Block RAM Address of RAM1 having uncorrectable error" hexmask.long.word 0x4 16.--31. 1. "RESERVED_31_16,Reserved" hexmask.long.word 0x4 0.--15. 1. "RAM1ADDRLOC,RAM1 Address Location" line.long 0x8 "BRAM2ADDRERR,Block RAM Address of RAM2 having uncorrectable error" hexmask.long.word 0x8 16.--31. 1. "RESERVED_31_16,Reserved" hexmask.long.word 0x8 0.--15. 1. "RAM2ADDRLOC,RAM1 Address Location" tree.end tree "DWC_usb3_block_dev (USB 3.0 Device Register Block)" group.long (0x0+0x50944)++0x17 line.long 0x0 "DCFG,Device Configuration Register. This register configures the controller in Device mode after power-on or after certain control commands or enumeration. Do not make changes to this register after initial programming." hexmask.long.byte 0x0 25.--31. 1. "RESERVED_31_25,Reserved" rbitfld.long 0x0 24. "RESERVED_24,reserved" "0,1" newline bitfld.long 0x0 23. "IGNSTRMPP,IgnoreStreamPP This bit only affects stream-capable bulk endpoints. When this bit is set to '0' and the controller receives a Data Packet with the Packet Pending (PP) bit set to 0 for OUT endpoints or it receives an ACK with the NumP field set.." "0,1" bitfld.long 0x0 22. "LPMCAP,LPM Capable The application uses this bit to control the LPM capabilities of the DWC_usb3 controller. If the controller operates as a non-LPM-capable device it cannot respond to LPM transactions. - 1'b0: LPM capability is not enabled. - 1'b1: LPM.." "LPM capability is not enabled,LPM capability is enabled" newline hexmask.long.byte 0x0 17.--21. 1. "NUMP,Number of Receive Buffers. This bit indicates the number of receive buffers to be reported in the ACK TP. The DWC_usb3 controller uses this field for non-control endpoints if GRXTHRCFG.UsbRxPktCntSel is set to '0'. The application can program this.." hexmask.long.byte 0x0 12.--16. 1. "INTRNUM,Interrupt number Indicates interrupt/EventQ number on which non-endpoint-specific device-related interrupts (see DEVT) are generated." newline rbitfld.long 0x0 10.--11. "RESERVED_10_11,Reserved" "0,1,2,3" hexmask.long.byte 0x0 3.--9. 1. "DEVADDR,Device Address. The application must perform the following: - Program this field after every SetAddress request. - Reset this field to zero after USB reset." newline bitfld.long 0x0 0.--2. "DEVSPD,Device Speed. Indicates the speed at which the application requires the controller to connect or the maximum speed the application can support. However the actual bus speed is determined only after the chirp sequence is completed and is based.." "High-speed,Full-speed,?,?,SuperSpeed,?,?,?" line.long 0x4 "DCTL,Device Control Register Note: When Hibernation is not enabled using GCTL.GblHibernationEn field. - you can write any value to CSS. CRS. L1HibernationEn. and KeepConnect fields - L1HibernationEn. and KeepConnect fields always return 0 when read in.." bitfld.long 0x4 31. "RUN_STOP,Run/Stop The software writes 1 to this bit to start the device controller operation. To stop the device controller operation the software must remove any active transfers and write 0 to this bit. When the controller is stopped it sets the.." "0,1" bitfld.long 0x4 30. "CSFTRST,Core Soft Reset Resets the all clock domains as follows: - This bit clears the interrupts and all the CSRs except GSTS GSNPSID GGPIO GUID GUSB2PHYCFGn registers GUSB3PIPECTLn registers DCFG DCTL DEVTEN and DSTS registers. - All module.." "0,1" newline rbitfld.long 0x4 29. "RESERVED_29,Reserved1" "0,1" hexmask.long.byte 0x4 24.--28. 1. "HIRDTHRES,HIRD Threshold (HIRD_Thres) The controller asserts output signals utmi_l1_suspend_n and utmi_sleep_n (see 'LPM Interface Signals' table in the Databook) on the basis of this signal: The controller asserts utmi_l1_suspend_n to put the PHY into.." newline hexmask.long.byte 0x4 20.--23. 1. "LPM_NYET_THRES,LPM NYET Threshold When LPM Errata is enabled: Bits [23:20]: LPM NYET Response Threshold (LPM_NYET_thres) Handshake response to LPM token specified by device application. Response depends on DCFG.LPMCap. - DCFG.LPMCap is 1'b0 - The.." bitfld.long 0x4 19. "KEEPCONNECT,Keep Connect When '1' this bit enables the save and restore programming model by preventing the controller from disconnecting from the host when DCTL.RunStop is set to '0'. It also enables the Hibernation Request Event to be generated when.." "0,1" newline bitfld.long 0x4 18. "L1HIBERNATIONEN,L1HibernationEn When this bit is set along with KeepConnect the device controller generates a Hibernation Request Event if L1 is enabled and the HIRD value in the LPM token is larger than the threshold programmed in DCTL.HIRD_Thres. The.." "0,1" bitfld.long 0x4 17. "CRS,Controller Restore State (CRS) This command is similar to the USBCMD.CRS bit in host mode and initiates the restore process. When software sets this bit to '1' the controller immediately sets DSTS.RSS to '1'. When the controller has finished the.." "0,1" newline bitfld.long 0x4 16. "CSS,Controller Save State (CSS) This command is similar to the USBCMD.CSS bit in host mode and initiates the save process. When software sets this bit to '1' the controller immediately sets DSTS.SSS to '1'. When the controller has finished the save.." "0,1" rbitfld.long 0x4 13.--15. "RESERVED_15_13,Reserved" "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 12. "INITU2ENA,Initiate U2 Enable - 1'b0: May not initiate U2 (default) - 1'b1: May initiate U2 On USB reset hardware clears this bit to 0. Software sets this bit after receiving SetFeature(U2_ENABLE) and clears this bit when ClearFeature(U2_ENABLE) is.." "May not initiate U2,May initiate U2" bitfld.long 0x4 11. "ACCEPTU2ENA,Accept U2 Enable - 1'b0: Reject U2 except when Force_LinkPM_Accept bit is set (default) - 1'b1: Controller accepts transition to U2 state if nothing is pending on the application side. On USB reset hardware clears this bit to 0. Software.." "Reject U2 except when Force_LinkPM_Accept bit is..,Controller accepts transition to U2 state if.." newline bitfld.long 0x4 10. "INITU1ENA,Initiate U1 Enable - 1'b0: May not initiate U1 (default); - 1'b1: May initiate U1. On USB reset hardware clears this bit to 0. Software sets this bit after receiving SetFeature(U1_ENABLE) and clears this bit when ClearFeature(U1_ENABLE) is.." "May not initiate U1,May initiate U1" bitfld.long 0x4 9. "ACCEPTU1ENA,Accept U1 Enable - 1'b0: Controller rejects U1 except when Force_LinkPM_Accept bit is set (default) - 1'b1: Controller accepts transition to U1 state if nothing is pending on the application side. On USB reset hardware clears this bit to 0." "Controller rejects U1 except when..,Controller accepts transition to U1 state if.." newline hexmask.long.byte 0x4 5.--8. 1. "ULSTCHNGREQ,ULSTCHNGREQ Software writes this field to issue a USB/Link state change request. A change in this field indicates a new request to the controller. If software wants to issue the same request back-to-back it must write a 0 to this field.." hexmask.long.byte 0x4 1.--4. 1. "TSTCTL,Test Control - 4'b000: Test mode disabled - 4'b001: Test_J mode - 4'b010: Test_K mode - 4'b011: Test_SE0_NAK mode - 4'b100: Test_Packet mode - 4'b101: Test_Force_Enable - Others: Reserved" newline rbitfld.long 0x4 0. "RESERVED_0,Reserved" "0,1" line.long 0x8 "DEVTEN,Device Event Enable Register This register controls the generation of device-specific events (see 'Event Buffer Content for Device-Specific Events (DEVT)' section). If an enable bit is set to 0. the event will not be generated." hexmask.long.word 0x8 17.--31. 1. "RESERVED_31_17,Reserved" bitfld.long 0x8 16. "ECCERREN,ECC Error Enable. If this bit is set to 1 the controller reports an ECC error to the software when an uncorrectable ECC occurs internally." "0,1" newline rbitfld.long 0x8 15. "RESERVED_15,Reserved" "0,1" bitfld.long 0x8 14. "L1WKUPEVTEN,L1 Resume Detected Event Enable. Note: If GUCTL1[DEV_DECOUPLE_L1L2_EVT] is enabled then this bit is for L1 Resume Detected Event Enable." "0,1" newline bitfld.long 0x8 12. "VENDEVTSTRCVDEN,Vendor Device Test LMP Received Event (VndrDevTstRcvedEn)" "0,1" rbitfld.long 0x8 11. "RESERVED_11,Reserved" "0,1" newline rbitfld.long 0x8 10. "RESERVED_10,Reserved" "0,1" bitfld.long 0x8 9. "ERRTICERREVTEN,Erratic Error Event Enable" "0,1" newline bitfld.long 0x8 8. "L1SUSPEN,L1 Suspend Event Enable Note: Only if GUCTL1[DEV_DECOUPLE_L1L2_EVT] is enabled this bit is for L1 Suspend Event Enable." "0,1" bitfld.long 0x8 7. "SOFTEVTEN,Start of (u)frame" "0,1" newline bitfld.long 0x8 6. "U3L2L1SUSPEN,U3/L2 or U3/L2L1 Suspend Event Enable. Note: - If GUCTL1[DEV_DECOUPLE_L1L2_EVT] is enabled then this bit is for U3/L2 Suspend Event Enable. - If GUCTL1[DEV_DECOUPLE_L1L2_EVT] is not enabled then this bit is for U3/L2L1 Suspend Event Enable." "0,1" bitfld.long 0x8 5. "HIBERNATIONREQEVTEN,This bit enables/disables the generation of the Hibernation Request Event." "0,1" newline bitfld.long 0x8 4. "WKUPEVTEN,U3/L2 or U3/L2L1 Resume Detected Event Enable. Note: - If GUCTL1[DEV_DECOUPLE_L1L2_EVT] is enabled then this bit is for U3/L2 Resume Detected Event Enable. - If GUCTL1[DEV_DECOUPLE_L1L2_EVT] is not enabled then this bit is for U3/L2L1 Resume.." "0,1" bitfld.long 0x8 3. "ULSTCNGEN,USB/Link State Change Event Enable" "0,1" newline bitfld.long 0x8 2. "CONNECTDONEEVTEN,Connection Done Enable" "0,1" bitfld.long 0x8 1. "USBRSTEVTEN,USB Reset Enable" "0,1" newline bitfld.long 0x8 0. "DISSCONNEVTEN,Disconnect Detected Event Enable" "0,1" line.long 0xC "DSTS,Device Status Register This register indicates the status of the device controller with respect to USB-related events. Note: When Hibernation is not enabled. RSS and SSS fields always return 0 when read." rbitfld.long 0xC 30.--31. "RESERVED_31_30,Reserved" "0,1,2,3" rbitfld.long 0xC 29. "DCNRD,Device Controller Not Ready The bit indicates that the controller is in the process of completing the state transitions after exiting from hibernation. To complete the state transitions it takes 256 bus clock cycles from the time DCTL[31].Run/Stop.." "0,1" newline bitfld.long 0xC 28. "SRE,Save Restore Error. Currently not supported." "0,1" rbitfld.long 0xC 26.--27. "RESERVED_27_26,Reserved" "0,1,2,3" newline rbitfld.long 0xC 25. "RSS,RSS Restore State Status This bit is similar to the USBSTS.RSS in host mode. When the controller finishes the restore process it completes the command by setting DSTS.RSS to '0'." "0,1" rbitfld.long 0xC 24. "SSS,SSS Save State Status This bit is similar to the USBSTS.SSS in host mode. When the controller has finished the save process it completes the command by setting DSTS.SSS to '0'." "0,1" newline rbitfld.long 0xC 23. "COREIDLE,Core Idle The bit indicates that the controller finished transferring all RxFIFO data to system memory writing out all completed descriptors and all Event Counts are zero. Note: While testing for Reset values mask out the read value. This bit.." "0,1" rbitfld.long 0xC 22. "DEVCTRLHLT,Device Controller Halted This bit is set to 0 when the Run/Stop bit in the DCTL register is set to 1. The controller sets this bit to 1 when after SW sets Run/Stop to 0 the controller is idle and the lower layer finishes the disconnect.." "0,1" newline hexmask.long.byte 0xC 18.--21. 1. "USBLNKST,USBLNKST. USB/Link State In SS mode: LTSSM State - 4'h0: U0 - 4'h1: U1 - 4'h2: U2 - 4'h3: U3 - 4'h4: SS_DIS - 4'h5: RX_DET - 4'h6: SS_INACT - 4'h7: POLL - 4'h8: RECOV - 4'h9: HRESET - 4'ha: CMPLY - 4'hb: LPBK - 4'hf: Resume/Reset In HS/FS/LS.." rbitfld.long 0xC 17. "RXFIFOEMPTY,RxFIFO Empty." "0,1" newline hexmask.long.word 0xC 3.--16. 1. "SOFFN,Frame/Microframe Number of the Received SOF. When the controller is operating at SuperSpeed - [16:3] indicates the uframe/ITP number When the controller is operating at high-speed - [16:6] indicates the frame number - [5:3] indicates the.." rbitfld.long 0xC 0.--2. "CONNECTSPD,Connected Speed (ConnectSpd) Indicates the speed at which the DWC_usb3 controller has come up after speed detection through a chirp sequence. - 3'b100: SuperSpeed (PHY clock is running at 125 or 250 MHz) - 3'b000: High-speed (PHY clock is.." "High-speed,Full-speed,?,?,SuperSpeed,?,?,?" line.long 0x10 "DGCMDPAR,Device Generic Command Parameter Register This register indicates the device command parameter. This must be programmed before or along with the device command. The available device commands are listed in DGCMD register." hexmask.long 0x10 0.--31. 1. "PARAMETER,PARAMETER" line.long 0x14 "DGCMD,Device Generic Command Register This register enables software to program the controller using a single generic command interface to send link management packets and notifications. This register contains command. control. and status fields relevant.." hexmask.long.word 0x14 16.--31. 1. "RESERVED_31_16,Reserved" hexmask.long.byte 0x14 12.--15. 1. "CMDSTATUS,Command Status - 1: CmdErr: Indicates that the device controller encountered an error while processing the command. - 0: Indicates command success" newline rbitfld.long 0x14 11. "RESERVED_11,Reserved" "0,1" bitfld.long 0x14 10. "CMDACT,Command Active The software sets this bit to 1 to enable the device controller to execute the generic command. The device controller sets this bit to 0 after executing the command." "0,1" newline rbitfld.long 0x14 9. "RESERVED_9,Reserved" "0,1" bitfld.long 0x14 8. "CMDIOC,Command Interrupt on Complete When this bit is set the device controller issues a Generic Command Completion event after executing the command. Note that this interrupt is mapped to DCFG.IntrNum. Note: This field must not set to '1' if the.." "0,1" newline hexmask.long.byte 0x14 0.--7. 1. "CMDTYP,CMDTYP Generic Command Type Specifies the type of generic command the software driver is requesting the controller to perform. - 02h: Set Periodic Parameters - 04h: Set Scratchpad Buffer Array Address Lo - 05h: Set Scratchpad Buffer Array Address.." group.long (0x20+0x50944)++0x3 line.long 0x0 "DALEPENA,Device Active USB Endpoint Enable Register. This register indicates whether a USB endpoint is active in a given configuration or interface." hexmask.long 0x0 0.--31. 1. "USBACTEP,USBACTEP USB Active Endpoints (USBActEP) This field indicates if a USB endpoint is active in the current configuration and interface. It applies to USB IN endpoints 0.15 and OUT endpoints 0.15 with one bit for each of the 32 possible endpoints." rgroup.long (0x24+0x50944)++0x3 line.long 0x0 "RSVD,Reserved" hexmask.long 0x0 0.--31. 1. "RESERVED_31_0,Reserved" group.long (0x100+0x50944)++0xF line.long 0x0 "DEPCMDPAR2,Device Physical Endpoint-n Command Parameter 2 Register (DEPCMDPAR2n) This register indicates the physical endpoint command Parameter 2. It must be programmed before issuing the command." hexmask.long 0x0 0.--31. 1. "PARAMETER,PARAMETER" line.long 0x4 "DEPCMDPAR1,Device Physical Endpoint-n Command Parameter 1 Register (DEPCMDPAR1n)" hexmask.long 0x4 0.--31. 1. "PARAMETER,PARAMETER" line.long 0x8 "DEPCMDPAR0,Device Physical Endpoint-n Command Parameter 0 Register (DEPCMDPAR0n)" hexmask.long 0x8 0.--31. 1. "PARAMETER,PARAMETER" line.long 0xC "DEPCMD,Device Physical Endpoint-n Command Register This register enables software to issue physical endpoint-specific commands. This register contains command. control. and status fields relevant to the current generic command. while the DEPCMDPAR[2:0]n.." hexmask.long.word 0xC 16.--31. 1. "COMMANDPARAM,Command Parameters or Event Parameters Command Parameters (CommandParam) when this register is written: For Start Transfer command: - [31:16]: StreamID. The USB StreamID assigned to this transfer For Start Transfer command applied to an.." hexmask.long.byte 0xC 12.--15. 1. "CMDSTATUS,Command Completion Status (CmdStatus) Additional information about the completion of this command is available in this field. The information is in the same format as bits 15:12 of the Endpoint Command Complete event see 'Device Endpoint-n.." newline bitfld.long 0xC 11. "HIPRI_FORCERM,HighPriority/ForceRM (HiPri_ForceRM) - HighPriority: Only valid for Start Transfer command - ForceRM: Only valid for End Transfer command - ClearPendIN: Only valid for Clear Stall command . Software sets this bit to clear any pending IN.." "0,1" bitfld.long 0xC 10. "CMDACT,Command Active (CmdAct) Software sets this bit to 1 to enable the device endpoint controller to execute the generic command. The device controller sets this bit to 0 when the CmdStatus field is valid and the endpoint is ready to accept another.." "0,1" newline rbitfld.long 0xC 9. "RESERVED_9,Reserved" "0,1" bitfld.long 0xC 8. "CMDIOC,CMDIOC Command Interrupt on Complete (CmdIOC) When this bit is set the device controller issues a generic Endpoint Command Complete event after executing the command. Note that this interrupt is mapped to DEPCFG.IntrNum. When the DEPCFG command.." "0,1" newline hexmask.long.byte 0xC 4.--7. 1. "RESERVED_7_4,Reserved" hexmask.long.byte 0xC 0.--3. 1. "CMDTYP,Command Type Specifies the type of command the software driver is requesting the controller to perform. - 00h: Reserved - 01h: Set Endpoint Configuration - -64 or 96-bit Parameter - 02h: Set Endpoint Transfer Resource Configuration - 32-bit.." group.long (0x300+0x50944)++0x3 line.long 0x0 "DEV_IMOD,Device Interrupt Moderation Register (DEV_IMOD) This register controls the Interrupt Moderation feature that allows the device software to throttle the interrupt rate. Key Functions: - Interrupt Moderation is enabled only when the IMOD Interval.." hexmask.long.word 0x0 16.--31. 1. "DEVICE_IMODC,Interrupt Moderation Down Counter Loaded with the DEVICE_IMODI value whenever the hardware interrupt(n) line is de-asserted from the asserted state counts down to 0 and stops. The interrupt(n) is signaled whenever this counter is 0.." hexmask.long.word 0x0 0.--15. 1. "DEVICE_IMODI,Moderation Interval (DEVICE_IMODI) This field holds the minimum inter-interrupt interval between events. The interval is specified in terms of 250ns increments. A value of 0 disables the interrupt throttling logic and interrupts are.." tree.end tree "DWC_usb3_block_bc (USB 3.0 BC Register Block)" group.long (0x0+0x52272)++0x3 line.long 0x0 "BCFG,BC Configuration Register" hexmask.long 0x0 2.--31. 1. "RESERVED_31_2,Reserved" bitfld.long 0x0 1. "IDDIG_SEL,This field is not used." "0,1" bitfld.long 0x0 0. "CHIRP_EN,Chirp Enable When this bit is 1'b1 the controller asserts the bc_chirp_on output signal to indicate an imminent chirp." "0,1" group.long (0x8+0x52272)++0x7 line.long 0x0 "BCEVT,BC Event Register Writing 1 to the info bit in this register clears the register bit and the associated interrupt." hexmask.long.byte 0x0 25.--31. 1. "RESERVED_31_25,Reserved" bitfld.long 0x0 24. "MV_CHNGEVNT,Multi-Valued input changed Event: This event indicates that there is a change in the value of at least one ACA pin value. This bit is present only if DWC_USB3_EN_BC = 1 otherwise it is Reserved." "0,1" hexmask.long.tbyte 0x0 5.--23. 1. "RESERVED_23_5,Reserved" hexmask.long.byte 0x0 0.--4. 1. "MULTVALIDBC,Multi Valued ID pin Indicates the Battery Charger ACA inputs. - MultValIdBc[4]: bc_rid_float - MultValIdBc[3]: bc_rid_gnd - MultValIdBc[2]: bc_rid_a - MultValIdBc[1]: bc_rid_b - MultValIdBc[0]: bc_rid_c" line.long 0x4 "BCEVTEN,BC Event Enable Register" hexmask.long.byte 0x4 25.--31. 1. "RESERVED_31_25,Reserved" bitfld.long 0x4 24. "MV_CHNGEVNTENA,BCEvtInfoEna[0] Multi-Valued input changed Event Enable (MV_ChngEvntEn) When this bit is set MV_ChngEvnt in BCEVT register is enabled." "0,1" hexmask.long.tbyte 0x4 0.--23. 1. "RESERVED_23_0,Reserved" tree.end tree "DWC_usb3_block_link (USB 3.0 Link Register Block)" group.long (0x0+0x53248)++0x3 line.long 0x0 "LU1LFPSRXTIM,U1/U2 LFPS Rx Timer Register - Link Layer Register for U1/U2 LFPS RX Timers. - This register is common for all SS ports." hexmask.long.word 0x0 16.--31. 1. "RESERVED_16_31,Reserved" hexmask.long.byte 0x0 8.--15. 1. "U1U2_LFPS_EXIT_RX_CLK,Programmable U1U2 LFPS EXIT RX CLKS - Applicable to Remote Partner initiated Ux exit: Time to recognize valid Ux exit request from the remote partner. - This field is encoded as the pipe clk (8ns) count for the LFPS. -- 1: 8ns -- 2:.." hexmask.long.byte 0x0 0.--7. 1. "U1U2_EXIT_RSP_RX_CLK,Programmable U1U2 EXIT RESP RX CLKS - Applicable to locally initiated Ux exit: Minimum LFPS reception from remote to consider Ux exit handshake is successful. - This field is encoded as the pipe clk (8ns) count for the LFPS. -- 1:.." group.long (0x20+0x53248)++0xB line.long 0x0 "LINK_SETTINGS,Link Setting Register - Link Layer User Control Register for enabling Link/PHY-specific options. - This register is common for all SS ports." bitfld.long 0x0 31. "RESERVED_31,Reserved" "0,1" bitfld.long 0x0 28.--30. "U1_RESID_TIMER_US,Programmable U1 MIN RESIDENCY TIMER This field specifies U1 MIN RESIDENCY TIMER value in us. Set to 0 to disable the timer." "0,1,2,3,4,5,6,7" bitfld.long 0x0 27. "RESERVED_27,Reserved" "0,1" newline bitfld.long 0x0 24.--26. "PM_LC_TIMER_US,Programmable PM_LC_TIMER This field specifies PM_LC_TIMER value in us." "0,1,2,3,4,5,6,7" hexmask.long.byte 0x0 20.--23. 1. "PM_ENTRY_TIMER_US,Programmable PM_ENTRY_TIMER This field specifies PM_ENTRY_TIMER value in us." hexmask.long.tbyte 0x0 0.--19. 1. "RESERVED_0_19,Reserved" line.long 0x4 "LLUCTL,Link User Control Register - Link Layer User Control Register for enabling Link/PHY-specific options. - This register is common for all SS ports." bitfld.long 0x4 30.--31. "RESERVED_30_31,Reserved" "0,1,2,3" bitfld.long 0x4 29. "SUPPORT_P4_PG,PHY P4 Power gate mode (PG) is enabled. Set this bit if the PHY supports PG mode in P4. This bit is used only for Synopsys PHY." "0,1" bitfld.long 0x4 28. "SUPPORT_P4,Support PHY P3.CPM and P4 Power States. When this bit is set the controller puts the PHY in P3.CPM or P4 in certain states. This bit is used only for Synopsys PHY." "0,1" newline hexmask.long.byte 0x4 24.--27. 1. "RESERVED_24_27,Reserved" bitfld.long 0x4 23. "DISRXDET_LTSSM_TIMER_OVRRD,DisRxDet_LTSSM_Timer_Ovrrd. When DisRxDetU3RxDet is asserted in Polling or U1 the timeout expires immediately." "0,1" hexmask.long.word 0x4 13.--22. 1. "RESERVED_13_22,Reserved" newline bitfld.long 0x4 12. "U2P3CPMOK,P3CPM OK for U2/SSInactive (U2P3CPMok) - 0: During link state U2/SS.Inactive put PHY in P2 (Default) - 1: During link state U2/SS.Inactive put PHY in P3CPM. Note: For a port if both GUCTL1[25]=1 and LUCTL[12]=1 LUCTL[12]=1 takes priority." "During link state U2/SS,During link state U2/SS" bitfld.long 0x4 11. "EN_RESET_PIPE_AFTER_PHY_MUX,en_reset_pipe_after_phy_mux. The controller issues USB 3.0 PHY reset after DisRxDetU3RxDet is de-asserted." "0,1" bitfld.long 0x4 8.--10. "RESERVED_8_10,Reserved" "0,1,2,3,4,5,6,7" newline bitfld.long 0x4 7. "MASK_PIPE_RESET,Mask pipe reset. If this bit is set controller blocks pipe_reset_n from going to the PHY when DisRxDetU3RxDet=1." "0,1" bitfld.long 0x4 6. "RESERVED_6,Reserved" "0,1" bitfld.long 0x4 5. "NO_UX_EXIT_P0_TRANS,no_ux_exit_p0_trans. Link LTSSM detects Ux_exit LFPS when P0 transition is on-going by default. If this bit is set Link LTSSM may miss Ux_exit LFPS when P0 transition is happening." "0,1" newline hexmask.long.byte 0x4 0.--4. 1. "RESERVED_0_4,Reserved" line.long 0x8 "LPTMDPDELAY,Link Datapath Delay Register - Link Layer Timer Register for P3CPM/P4 Residency. - This register is common for all SS ports." hexmask.long.word 0x8 22.--31. 1. "RESERVED_22_31,Reserved" hexmask.long.word 0x8 10.--21. 1. "P3CPMP4_RESIDENCY,p3cpmp4 residency timer value. Minimum number of suspend_clk periods that the controller needs to stay in P3.CPM or P4 before exiting P3.CPM or P4. This field is used only for Synopsys PHY." hexmask.long.word 0x8 0.--9. 1. "RESERVED_0_9,Reserved" tree.end tree "DWC_usb3_block_debug (USB 3.0 Debug Register Block)" group.long (0x0+0x55296)++0x3 line.long 0x0 "U3RHBDBG,U3 Root Hub Debug Register" hexmask.long 0x0 4.--31. 1. "RESERVED_1,Reserved_1" bitfld.long 0x0 3. "TPCFG_TOUT_CTRL,tpcfg_tout_ctrl This bit controls the USB 3.0 port configuration timeout duration. - 1: The port configuration timeout counter resets when the link is not in U0. - 0: The port configuration timeout counter does not reset if the link.." "The port configuration timeout counter does not..,The port configuration timeout counter resets.." rbitfld.long 0x0 0.--2. "RESERVED_0_2,Reserved_0_2" "0,1,2,3,4,5,6,7" tree.end tree "DWC_usb3_block_eXtensible_Host_Cntrl_Cap_Regs (USB 3.0 eXtensible Host Controller Capability Register Block)" rgroup.long (0x0+0x55296)++0x1F line.long 0x0 "CAPLENGTH,Capability Registers Length Host Controller Operational Registers = Base address + CAPLENGTH where CAPLENGTH is `DWC_USB3_HOST_CAP_REG_LEN whose default value is 20h." hexmask.long.word 0x0 16.--31. 1. "HCIVERSION,HC Interface Version Number (HCIVERSION)" hexmask.long.byte 0x0 8.--15. 1. "RESERVED_15_8,Reserved" hexmask.long.byte 0x0 0.--7. 1. "CAPLENGTH,Capability Registers Length (CAPLENGTH)" line.long 0x4 "HCSPARAMS1,Structural Parameters 1 Register For register definitions. refer to the xHCI specification." hexmask.long.byte 0x4 24.--31. 1. "MAXPORTS,Number of Ports (MaxPorts) - Number of ports implemented is defined by the parameter (`DWC_USB3_HOST_NUM_U2_ROOT_PORTS + `DWC_USB3_HOST_NUM_U3_ROOT_PORTS) - Number of ports enabled is controlled by the controller input signals.." hexmask.long.byte 0x4 19.--23. 1. "RESERVED_23_19,Reserved" hexmask.long.word 0x4 8.--18. 1. "MAXINTRS,Number of Interrupters (MaxIntrs) Defined by the configurable parameter `DWC_USB3_HOST_NUM_INTERRUPTER_SUPT" hexmask.long.byte 0x4 0.--7. 1. "MAXSLOTS,Number of device slots (MaxSlots) Defined by configurable parameter `DWC_USB3_NUM_DEVICE_SUPT" line.long 0x8 "HCSPARAMS2,Structural Parameters 2 Register For register definitions. refer to the xHCI specification." hexmask.long.byte 0x8 27.--31. 1. "MAXSCRATCHPADBUFS,Max Scratchpad Bufs Lo The value is calculated based on chosen configuration parameter values. Possible values are 1-4." bitfld.long 0x8 26. "SPR,Scratchpad Restore (SPR)" "0,1" hexmask.long.byte 0x8 21.--25. 1. "MAXSCRATCHPADBUFS_HI,Max Scratchpad Bufs HI The controller automatically updates this field." hexmask.long.word 0x8 8.--20. 1. "RESERVED_20_8,Reserved" newline hexmask.long.byte 0x8 4.--7. 1. "ERSTMAX,Event Ring Segment Table Max (ERST Max)" hexmask.long.byte 0x8 0.--3. 1. "IST,Isochronous Scheduling Threshold (IST)" line.long 0xC "HCSPARAMS3,Structural Parameters 3 Register For register definitions. refer to the xHCI specification." hexmask.long.word 0xC 16.--31. 1. "U2_DEVICE_EXIT_LAT,U2 Device Exit Latency" hexmask.long.byte 0xC 8.--15. 1. "RESERVED_15_8,Reserved" hexmask.long.byte 0xC 0.--7. 1. "U1_DEVICE_EXIT_LAT,U1 Device Exit Latency" line.long 0x10 "HCCPARAMS1,Capability Parameters 1 Register For register definitions. refer to the xHCI specification." hexmask.long.word 0x10 16.--31. 1. "XECP,xHCI Extended Capabilities Pointer (xECP) Based on configuration controller automatically updates it. Refer to /src/DWC_usb3_params.v for details on DWC_USB3_HC_XECP." hexmask.long.byte 0x10 12.--15. 1. "MAXPSASIZE,Maximum Primary Stream Array Size (MaxPSASize) For a description of this standard USB register field see the eXtensible Host Controller Interface for Universal Serial Bus (USB) Specification 3.0." bitfld.long 0x10 11. "CFC,Contiguous Frame ID Capability (CFC)" "0,1" bitfld.long 0x10 10. "SEC,Stopped EDLTA Capability (SEC) For a description of this standard USB register field see the eXtensible Host Controller Interface for Universal Serial Bus (USB) Specification 3.0." "0,1" newline bitfld.long 0x10 9. "SPC,Short Packet Capability (SPC) For a description of this standard USB register field see the eXtensible Host Controller Interface for Universal Serial Bus (USB) Specification 3.0." "0,1" bitfld.long 0x10 8. "PAE,Parse All Event Data (PAE) For a description of this standard USB register field see the eXtensible Host Controller Interface for Universal Serial Bus (USB) Specification 3.0." "0,1" bitfld.long 0x10 7. "NSS,No Secondary SID Support (NSS) For a description of this standard USB register field see the eXtensible Host Controller Interface for Universal Serial Bus (USB) Specification 3.0." "0,1" bitfld.long 0x10 6. "LTC,Latency Tolerance Messaging Capability (LTC) For a description of this standard USB register field see the eXtensible Host Controller Interface for Universal Serial Bus (USB) Specification 3.0." "0,1" newline bitfld.long 0x10 5. "LHRC,Light HC Reset Capability For a description of this standard USB register field see the eXtensible Host Controller Interface for Universal Serial Bus (USB) Specification 3.0." "0,1" bitfld.long 0x10 4. "PIND,Port Indicators (PIND) For a description of this standard USB register field see the eXtensible Host Controller Interface for Universal Serial Bus (USB) Specification 3.0." "0,1" bitfld.long 0x10 3. "PPC,Port Power Control For a description of this standard USB register field see the eXtensible Host Controller Interface for Universal Serial Bus (USB) Specification 3.0." "0,1" bitfld.long 0x10 2. "CSZ,Context Size (CSZ) For a description of this standard USB register field see the eXtensible Host Controller Interface for Universal Serial Bus (USB) Specification 3.0." "0,1" newline bitfld.long 0x10 1. "BNC,BW Negotiation Capability (BNC) For a description of this standard USB register field see the eXtensible Host Controller Interface for Universal Serial Bus (USB) Specification 3.0." "0,1" bitfld.long 0x10 0. "AC64,64-bit Addressing Capability (AC64) For a description of this standard USB register field see the eXtensible Host Controller Interface for Universal Serial Bus (USB) Specification 3.0." "0,1" line.long 0x14 "DBOFF,Doorbell Offset Register For register definitions. refer to the xHCI specification." hexmask.long 0x14 2.--31. 1. "DOORBELL_ARRAY_OFFSET,Doorbell Array Offset - RO Based on configuration the controller automatically updates it. For a description of this standard USB register field see the eXtensible Host Controller Interface for Universal Serial Bus (USB).." bitfld.long 0x14 0.--1. "RESERVED_1_0,Reserved" "0,1,2,3" line.long 0x18 "RTSOFF,Runtime Register Space Offset Register" hexmask.long 0x18 5.--31. 1. "RUNTIME_REG_SPACE_OFFSET,Runtime Register Space Offset Based on configuration the controller automatically updates it. For a description of this standard USB register field see the eXtensible Host Controller Interface for Universal Serial Bus (USB).." hexmask.long.byte 0x18 0.--4. 1. "RESERVED_4_0,Reserved" line.long 0x1C "HCCPARAMS2,Host Controller Capability Parameters 2 For register definitions. refer to the xHCI specification." hexmask.long 0x1C 6.--31. 1. "RESERVED_31_6,Reserved" bitfld.long 0x1C 5. "CIC,Configuration Information Capability (CIC) For a description of this standard USB register field see the eXtensible Host Controller I nterface for Universal Serial Bus (USB) Specification 3.0." "0,1" bitfld.long 0x1C 4. "LEC,Large ESIT Payload Capability (LEC) For a description of this standard USB register field see the eXtensible Host Controller I nterface for Universal Serial Bus (USB) Specification 3.0." "0,1" bitfld.long 0x1C 3. "CTC,Compliance Transition Capability (CTC) For a description of this standard USB register field see the eXtensible Host Controller I nterface for Universal Serial Bus (USB) Specification 3.0." "0,1" newline bitfld.long 0x1C 2. "FSC,Force Save Context Capability (FSC) For a description of this standard USB register field see the eXtensible Host Controller I nterface for Universal Serial Bus (USB) Specification 3.0." "0,1" bitfld.long 0x1C 1. "CMC,Configure Endpoint Command Max Exit Latency Too Large Capability (CMC) For a description of this standard USB register field see the eXtensible Host Controller I nterface for Universal Serial Bus (USB) Specification 3.0." "0,1" bitfld.long 0x1C 0. "U3C,U3 Entry Capability (U3C) For a description of this standard USB register field see the eXtensible Host Controller I nterface for Universal Serial Bus (USB) Specification 3.0." "0,1" tree.end tree "DWC_usb3_block_Host_Cntrl_Oper_Regs (USB3 Host Cntrl Oper Regs Block)" group.long (0x0+0x32)++0x7 line.long 0x0 "USBCMD,USB Command Register For a description of this standard USB register field see the eXtensible Host Controller Interface for Universal Serial Bus (USB) Specification 3.0." hexmask.long.tbyte 0x0 14.--31. 1. "RESERVED_31_14,Reserved" bitfld.long 0x0 13. "CME,CEM Enable For a description of this standard USB register field see the eXtensible Host Controller Interface for Universal Serial Bus (USB) Specification 3.0." "0,1" rbitfld.long 0x0 12. "RESERVED_12,Reserved" "0,1" bitfld.long 0x0 11. "EU3S,EU3S For a description of this standard USB register field see the eXtensible Host Controller Interface for Universal Serial Bus (USB) Specification 3.0." "0,1" bitfld.long 0x0 10. "EWE,EWE For a description of this standard USB register field see the eXtensible Host Controller Interface for Universal Serial Bus (USB) Specification 3.0." "0,1" newline bitfld.long 0x0 9. "CRS,Controller Restore State This command is similar to the USBCMD.CRS bit in host mode and initiates the restore process. When software sets this bit to '1' the controller immediately sets DSTS.RSS to '1'. When the controller has finished the restore.." "0,1" bitfld.long 0x0 8. "CSS,Controller Save State This command is similar to the USBCMD.CSS bit in host mode and initiates the save process. When software sets this bit to '1' the controller immediately sets DSTS.SSS to '1'. When the controller has finished the save process.." "0,1" bitfld.long 0x0 7. "LHCRST,Light Host Controller Reset For a description of this standard USB register field see the eXtensible Host Controller Interface for Universal Serial Bus (USB) Specification 3.0. The following bits reset the internal logic of the host controller." "0,1" rbitfld.long 0x0 4.--6. "RESERVED_6_4,Reserved" "0,1,2,3,4,5,6,7" bitfld.long 0x0 3. "HSEE,HSEE For a description of this standard USB register field see the eXtensible Host Controller Interface for Universal Serial Bus (USB) Specification 3.0." "0,1" newline bitfld.long 0x0 2. "INTE,INTE For a description of this standard USB register field see the eXtensible Host Controller Interface for Universal Serial Bus (USB) Specification 3.0." "0,1" bitfld.long 0x0 1. "HCRST,HCRST The following bits reset the internal logic of the host controller. Under soft reset some CSR accesses may fail (Timeout). - HCRST - LHCRST Bit Bash register testing is not recommended." "0,1" bitfld.long 0x0 0. "R_S,R_S For a description of this standard USB register field see the eXtensible Host Controller Interface for Universal Serial Bus (USB) Specification 3.0. Due to side-effects this reguster field is not recommended for Bit-Bash testing." "0,1" line.long 0x4 "USBSTS,USB Status Register Bit Definitions For a description of this standard USB register field. see the eXtensible Host Controller Interface for Universal Serial Bus (USB) Specification 3.0." hexmask.long.tbyte 0x4 13.--31. 1. "RESERVED_31_13,Reserved" rbitfld.long 0x4 12. "HCE,Host Controller Error (HCE) - RO Default = 0. '0' = No internal xHC error conditions exist and '1' = Internal xHC error condition. This flag must be set to indicate that an internal error condition has been detected which requires software to reset.." "0,1" rbitfld.long 0x4 11. "CNR,Controller Not Ready (CNR) - RO Default = '1'. '0' = Ready and '1' = Not Ready. Software must not write to thes Doorbell or Operational register of the xHC other than the USBSTS register until CNR = '0'. This flag is set by the xHC after a Chip.." "0,1" bitfld.long 0x4 10. "SRE,Save/Restore Error This bit is currently not supported." "0,1" rbitfld.long 0x4 9. "RSS,Restore State Status This bit is similar to the USBSTS.RSS in host mode. When the controller has finished the restore process it completes the command by setting DSTS.RSS to '0'." "0,1" newline rbitfld.long 0x4 8. "SSS,Save State Status This bit is similar to the USBSTS.SSS in host mode. When the controller has finished the save process it completes the command by setting DSTS.SSS to '0'." "0,1" rbitfld.long 0x4 5.--7. "RESERVED_7_5,Reserved" "0,1,2,3,4,5,6,7" bitfld.long 0x4 4. "PCD,Reset Value for PCD" "0,1" bitfld.long 0x4 3. "EINT,Reset Value for EINT" "0,1" bitfld.long 0x4 2. "HSE,HSE For a description of this standard USB register field see the eXtensible Host Controller Interface for Universal Serial Bus (USB) Specification 3.0.." "0,1" newline rbitfld.long 0x4 1. "RESERVED_1,Reserved" "0,1" rbitfld.long 0x4 0. "HCH,HCH For a description of this standard USB register field see the eXtensible Host Controller Interface for Universal Serial Bus (USB) Specification 3.0." "0,1" rgroup.long (0x8+0x32)++0x3 line.long 0x0 "PAGESIZE,Page Size Register Bit Definitions Use this register to enable or disable the reporting of specific USB Device Notification Transaction Packets being received. A Notification Enable (Nx. where x = 0 to 15) flag is defined for each of the 16.." hexmask.long.word 0x0 16.--31. 1. "RESERVED_31_16,Reserved" hexmask.long.word 0x0 0.--15. 1. "PAGE_SIZE,PAGE_SIZE" group.long (0x14+0x32)++0xB line.long 0x0 "DNCTRL,Device Notification Register Bit Definitions For a description of this standard USB register field see the eXtensible Host Controller Interface for Universal Serial Bus (USB) Specification 3.0." hexmask.long.word 0x0 16.--31. 1. "RESERVED_31_16,Reserved" hexmask.long.word 0x0 0.--15. 1. "N0_N15,N0_N15 For a description of this standard USB register field see the eXtensible Host Controller Interface for Universal Serial Bus (USB) Specification 3.0." line.long 0x4 "CRCR_LO,CRCR_LO For a description of this standard USB register field. see the eXtensible Host Controller Interface for Universal Serial Bus (USB) Specification 3.0." hexmask.long 0x4 6.--31. 1. "CMD_RING_PNTR,CMD_RING_PNTR For a description of this standard USB register field see the eXtensible Host Controller Interface for Universal Serial Bus (USB) Specification 3.0." rbitfld.long 0x4 4.--5. "RESERVED_5_4,Reserved" "0,1,2,3" rbitfld.long 0x4 3. "CRR,CRR For a description of this standard USB register field see the eXtensible Host Controller Interface for Universal Serial Bus (USB) Specification 3.0." "0,1" bitfld.long 0x4 2. "CA,CA For a description of this standard USB register field see the eXtensible Host Controller Interface for Universal Serial Bus (USB) Specification 3.0." "0,1" bitfld.long 0x4 1. "CS,CS For a description of this standard USB register field see the eXtensible Host Controller Interface for Universal Serial Bus (USB) Specification 3.0." "0,1" newline bitfld.long 0x4 0. "RCS,RCS For a description of this standard USB register field see the eXtensible Host Controller Interface for Universal Serial Bus (USB) Specification 3.0." "0,1" line.long 0x8 "CRCR_HI,CRCR_HI" hexmask.long 0x8 0.--31. 1. "CMD_RING_PNTR,COMMAND_RING_POINTER Reading this field always returns '0'. For a description of this standard USB register field see the eXtensible Host Controller Interface for Universal Serial Bus (USB) Specification 3.0." group.long (0x30+0x32)++0xB line.long 0x0 "DCBAAP_LO,DCBAAP_LO" hexmask.long 0x0 6.--31. 1. "DEVICE_CONTEXT_BAAP,DEVICE_CONTEXT_BAAP For a description of this standard USB register field see the eXtensible Host Controller Interface for Universal Serial Bus (USB) Specification 3.0." hexmask.long.byte 0x0 0.--5. 1. "RESERVED_5_0,Reserved" line.long 0x4 "DCBAAP_HI,DCBAAP_HI For a description of this standard USB register field. see the eXtensible Host Controller Interface for Universal Serial Bus (USB) Specification 3.0." hexmask.long 0x4 0.--31. 1. "DEVICE_CONTEXT_BAAP,DEVICE_CONTEXT_BAAP" line.long 0x8 "CONFIG,Configure Register Bit Definitions This register is in the Aux Power well. It is only reset by platform hardware during a cold reset or in response to a Host Controller Reset (HCRST). The initial conditions of a port are described in section 4.19.." hexmask.long.tbyte 0x8 10.--31. 1. "RESERVED_31_10,Reserved" bitfld.long 0x8 9. "CIE,Configuration Information Enable For a description of this standard USB register field see the eXtensible Host Controller Interface for Universal Serial Bus (USB) Specification 3.0." "0,1" bitfld.long 0x8 8. "U3E,U3 Entry Enable For a description of this standard USB register field see the eXtensible Host Controller Interface for Universal Serial Bus (USB) Specification 3.0." "0,1" hexmask.long.byte 0x8 0.--7. 1. "MAXSLOTSEN,MAXSLOTSEN For a description of this standard USB register field see the eXtensible Host Controller Interface for Universal Serial Bus (USB) Specification 3.0." tree.end tree "DWC_usb3_block_Host_Cntrl_Port_Reg_Set (USB3 Host Cntrl Port Reg Set Block)" group.long (0x0+0x1056)++0x7 line.long 0x0 "PORTSC_20,Port Status and Control Register Bit Definitions The PORTSC Register Access fails (Timeout) if the UTMI/ULPI clock is not running or one of the following bits is asserted. - PR - ORC" rbitfld.long 0x0 31. "RESERVED_31,Reserved For a description of this standard USB register field see the eXtensible Host Controller Interface for Universal Serial Bus (USB) Specification 3.0. Programming this field with random data will cause side effect i.e. Register Access.." "0,1" rbitfld.long 0x0 30. "DR,Reset Value For a description of this standard USB register field see the eXtensible Host Controller Interface for Universal Serial Bus (USB) Specification 3.0." "0,1" rbitfld.long 0x0 28.--29. "RESERVED_29_28,Reserved" "0,1,2,3" bitfld.long 0x0 27. "WOE,WOE For a description of this standard USB register field see the eXtensible Host Controller Interface for Universal Serial Bus (USB) Specification 3.0." "0,1" newline bitfld.long 0x0 26. "WDE,WDE For a description of this standard USB register field see the eXtensible Host Controller Interface for Universal Serial Bus (USB) Specification 3.0." "0,1" bitfld.long 0x0 25. "WCE,WCE For a description of this standard USB register field see the eXtensible Host Controller Interface for Universal Serial Bus (USB) Specification 3.0." "0,1" rbitfld.long 0x0 24. "CAS,Cold Attach Status For a description of this standard USB register field see the eXtensible Host Controller Interface for Universal Serial Bus (USB) Specification 3.0." "0,1" rbitfld.long 0x0 23. "RESERVED_23,Reserved For a description of this standard USB register field see the eXtensible Host Controller Interface for Universal Serial Bus (USB) Specification 3.0." "0,1" newline bitfld.long 0x0 22. "PLC,PLC For a description of this standard USB register field see the eXtensible Host Controller Interface for Universal Serial Bus (USB) Specification 3.0." "0,1" bitfld.long 0x0 21. "PRC,PRC For a description of this standard USB register field see the eXtensible Host Controller Interface for Universal Serial Bus (USB) Specification 3.0. Programming this field with random data will cause side effect. Bit Bash register testing is not.." "0,1" bitfld.long 0x0 20. "OCC,OCC For a description of this standard USB register field see the eXtensible Host Controller Interface for Universal Serial Bus (USB) Specification 3.0." "0,1" bitfld.long 0x0 19. "RESERVED_19,WRC For a description of this standard USB register field see the eXtensible Host Controller Interface for Universal Serial Bus (USB) Specification 3.0." "0,1" newline bitfld.long 0x0 18. "PEC,PEC For a description of this standard USB register field see the eXtensible Host Controller Interface for Universal Serial Bus (USB) Specification 3.0." "0,1" bitfld.long 0x0 17. "CSC,CSC For a description of this standard USB register field see the eXtensible Host Controller Interface for Universal Serial Bus (USB) Specification 3.0." "0,1" bitfld.long 0x0 16. "LWS,LWS For a description of this standard USB register field see the eXtensible Host Controller Interface for Universal Serial Bus (USB) Specification 3.0." "0,1" bitfld.long 0x0 14.--15. "PIC,PIC For a description of this standard USB register field see the eXtensible Host Controller Interface for Universal Serial Bus (USB) Specification 3.0." "0,1,2,3" newline hexmask.long.byte 0x0 10.--13. 1. "PORTSPEED,PORTSPEED For a description of this standard USB register field see the eXtensible Host Controller Interface for Universal Serial Bus (USB) Specification 3.0." bitfld.long 0x0 9. "PP,PP For a description of this standard USB register field see the eXtensible Host Controller Interface for Universal Serial Bus (USB) Specification 3.0." "0,1" hexmask.long.byte 0x0 5.--8. 1. "PLS,PLS For a description of this standard USB register field see the eXtensible Host Controller Interface for Universal Serial Bus (USB) Specification 3.0." bitfld.long 0x0 4. "PR,PR set_register_field_attribute DWC_usb3_map/DWC_usb3_block_Host_Cntrl_Port_Reg_Set/PORTSC_20_REGS/PORTSC_20/PR VolatileMemory 1 Programming this field with random data will cause side effect. Bit Bash register testing is not recommended." "0,1" newline rbitfld.long 0x0 3. "OCA,OCA For a description of this standard USB register field see the eXtensible Host Controller Interface for Universal Serial Bus (USB) Specification 3.0." "0,1" rbitfld.long 0x0 2. "RESERVED_2,Reserved" "0,1" bitfld.long 0x0 1. "PED,PED For a description of this standard USB register field see the eXtensible Host Controller Interface for Universal Serial Bus (USB) Specification 3.0." "0,1" rbitfld.long 0x0 0. "CCS,CCS For a description of this standard USB register field see the eXtensible Host Controller Interface for Universal Serial Bus (USB) Specification 3.0." "0,1" line.long 0x4 "PORTPMSC_20,USB3 Port Power Management Status and Control Register Bit Definitions This register is in the Aux Power well. It is only reset by platform hardware during a cold reset or in response to a Host Controller Reset (HCRST). Programming this field.." hexmask.long.byte 0x4 28.--31. 1. "PRTTSTCTRL,Port Test Control For a description of this standard USB register field see the eXtensible Host Controller Interface for Universal Serial Bus (USB) Specification 3.0." hexmask.long.word 0x4 17.--27. 1. "RESERVED_27_17,Reserved" bitfld.long 0x4 16. "HLE,Port Test Control For a description of this standard USB register field see the eXtensible Host Controller Interface for Universal Serial Bus (USB) Specification 3.0." "0,1" hexmask.long.byte 0x4 8.--15. 1. "L1DSLOT,L1DSLOT For a description of this standard USB register field see the eXtensible Host Controller Interface for Universal Serial Bus (USB) Specification 3.0." newline hexmask.long.byte 0x4 4.--7. 1. "HIRD,Host Initiated Resume Duration (HIRD) - RW. Default = '0'. System software sets this field to indicate to the recipient device how long the xHC will drive resume if it (the xHC) initiates an exit from L1. The HIRD value is encoded as follows: Value.." bitfld.long 0x4 3. "RWE,RWE Port Test Control For a description of this standard USB register field see the eXtensible Host Controller Interface for Universal Serial Bus (USB) Specification 3.0." "0,1" rbitfld.long 0x4 0.--2. "L1S,L1 Status (L1S) - RO. Default = 0. This field is used by software to determine whether an L1-based suspend request (LMP transaction) was successful specifically: Value Meaning 0 Invalid - This field is ignored by software. - 1 Success - Port.." "?,based suspend request,?,?,?,?,?,?" rgroup.long (0x8+0x1056)++0x3 line.long 0x0 "PORTLI_20,Port Link Info Register Programming this field with random data will cause side effect i.e. Register Access will fail (Timeout) if the pipe clock is not running or reset is asserted . Bit Bash register testing is not recommended." hexmask.long 0x0 0.--31. 1. "RESERVED_31_0,Reserved" group.long (0xC+0x1056)++0xB line.long 0x0 "PORTHLPMC_20,USB2 Port Hardware LPM Control Register Bit Definitions For a description of this standard USB register field. see the eXtensible Host Controller Interface for Universal Serial Bus (USB) Specification 3.0." hexmask.long.tbyte 0x0 14.--31. 1. "RESERVED_31_14,Reserved For a description of this standard USB register field see the eXtensible Host Controller Interface for Universal Serial Bus (USB) Specification 3.0." hexmask.long.byte 0x0 10.--13. 1. "HIRDD,PORTHLPMC_20 HIRDD" hexmask.long.byte 0x0 2.--9. 1. "L1_TIMEOUT,PORTHLPMC_20 L1_TIMEOUT. For a description of this standard USB register field see the eXtensible Host Controller Interface for Universal Serial Bus (USB) Specification 3.0." bitfld.long 0x0 0.--1. "HIRDM,Host Initiated Resume Duration Mode (HIRDM) - RWS. Default = 0h. Indicates which HIRD value must be used. The following are permissible values: Value Description 0 Initiate L1 using HIRD only on timeout. (default) 1 Initiate L1 using HIRDD on.." "0,1,2,3" line.long 0x4 "PORTSC_30,Port Status and Control Register Bit Definitions The PORTSC Register Access fails (Timeout) if the UTMI/ULPI clock is not running or one of the following bits is asserted. - PR - ORC - WPR" bitfld.long 0x4 31. "WPR,Reset Value For a description of this standard USB register field see the eXtensible Host Controller Interface for Universal Serial Bus (USB) Specification 3.0. Programming this field with random data will cause side effect i.e. Register Access will.." "0,1" rbitfld.long 0x4 30. "DR,Reset Value For a description of this standard USB register field see the eXtensible Host Controller Interface for Universal Serial Bus (USB) Specification 3.0." "0,1" rbitfld.long 0x4 28.--29. "RESERVED_29_28,Reserved" "0,1,2,3" bitfld.long 0x4 27. "WOE,WOE For a description of this standard USB register field see the eXtensible Host Controller Interface for Universal Serial Bus (USB) Specification 3.0." "0,1" newline bitfld.long 0x4 26. "WDE,WDE For a description of this standard USB register field see the eXtensible Host Controller Interface for Universal Serial Bus (USB) Specification 3.0." "0,1" bitfld.long 0x4 25. "WCE,WCE For a description of this standard USB register field see the eXtensible Host Controller Interface for Universal Serial Bus (USB) Specification 3.0." "0,1" rbitfld.long 0x4 24. "CAS,Cold Attach Status For a description of this standard USB register field see the eXtensible Host Controller Interface for Universal Serial Bus (USB) Specification 3.0." "0,1" bitfld.long 0x4 23. "CEC,CEC For a description of this standard USB register field see the eXtensible Host Controller Interface for Universal Serial Bus (USB) Specification 3.0." "0,1" newline bitfld.long 0x4 22. "PLC,PLC For a description of this standard USB register field see the eXtensible Host Controller Interface for Universal Serial Bus (USB) Specification 3.0." "0,1" bitfld.long 0x4 21. "PRC,PRC For a description of this standard USB register field see the eXtensible Host Controller Interface for Universal Serial Bus (USB) Specification 3.0. Programming this field with random data will cause side effect. Bit Bash register testing is not.." "0,1" bitfld.long 0x4 20. "OCC,OCC For a description of this standard USB register field see the eXtensible Host Controller Interface for Universal Serial Bus (USB) Specification 3.0." "0,1" bitfld.long 0x4 19. "WRC,WRC For a description of this standard USB register field see the eXtensible Host Controller Interface for Universal Serial Bus (USB) Specification 3.0." "0,1" newline bitfld.long 0x4 18. "PEC,PEC For a description of this standard USB register field see the eXtensible Host Controller Interface for Universal Serial Bus (USB) Specification 3.0." "0,1" bitfld.long 0x4 17. "CSC,CSC For a description of this standard USB register field see the eXtensible Host Controller Interface for Universal Serial Bus (USB) Specification 3.0." "0,1" bitfld.long 0x4 16. "LWS,LWS For a description of this standard USB register field see the eXtensible Host Controller Interface for Universal Serial Bus (USB) Specification 3.0." "0,1" bitfld.long 0x4 14.--15. "PIC,PIC For a description of this standard USB register field see the eXtensible Host Controller Interface for Universal Serial Bus (USB) Specification 3.0." "0,1,2,3" newline hexmask.long.byte 0x4 10.--13. 1. "PORTSPEED,PORTSPEED For a description of this standard USB register field see the eXtensible Host Controller Interface for Universal Serial Bus (USB) Specification 3.0." bitfld.long 0x4 9. "PP,PP For a description of this standard USB register field see the eXtensible Host Controller Interface for Universal Serial Bus (USB) Specification 3.0." "0,1" hexmask.long.byte 0x4 5.--8. 1. "PLS,PLS For a description of this standard USB register field see the eXtensible Host Controller Interface for Universal Serial Bus (USB) Specification 3.0." bitfld.long 0x4 4. "PR,PR set_register_field_attribute DWC_usb3_map/DWC_usb3_block_Host_Cntrl_Port_Reg_Set/PORTSC_30_REGS/PORTSC_30/PR VolatileMemory 1 Programming this field with random data will cause side effect. Bit Bash register testing is not recommended." "0,1" newline rbitfld.long 0x4 3. "OCA,OCA For a description of this standard USB register field see the eXtensible Host Controller Interface for Universal Serial Bus (USB) Specification 3.0." "0,1" rbitfld.long 0x4 2. "RESERVED_2,Reserved" "0,1" bitfld.long 0x4 1. "PED,PED For a description of this standard USB register field see the eXtensible Host Controller Interface for Universal Serial Bus (USB) Specification 3.0." "0,1" rbitfld.long 0x4 0. "CCS,CCS For a description of this standard USB register field see the eXtensible Host Controller Interface for Universal Serial Bus (USB) Specification 3.0." "0,1" line.long 0x8 "PORTPMSC_30,USB3 Port Power Management Status and Control Register Bit Definitions This register is in the Aux Power well. It is only reset by platform hardware during a cold reset or in response to a Host Controller Reset (HCRST). Programming this field.." hexmask.long.word 0x8 17.--31. 1. "RESERVED_31_17,Reserved" bitfld.long 0x8 16. "FLA,FLA For a description of this standard USB register field see the eXtensible Host Controller Interface for Universal Serial Bus (USB) Specification 3.0." "0,1" hexmask.long.byte 0x8 8.--15. 1. "U2_TIMEOUT,U2_TIMEOUT For a description of this standard USB register field see the eXtensible Host Controller Interface for Universal Serial Bus (USB) Specification 3.0." hexmask.long.byte 0x8 0.--7. 1. "U1_TIMEOUT,U1_TIMEOUT For a description of this standard USB register field see the eXtensible Host Controller Interface for Universal Serial Bus (USB) Specification 3.0." rgroup.long (0x18+0x1056)++0x7 line.long 0x0 "PORTLI_30,Port Link Info Register Programming this field with random data will cause side effect i.e. Register Access will fail (Timeout) if the pipe clock is not running or reset is asserted . Bit Bash register testing is not recommended." hexmask.long.word 0x0 16.--31. 1. "RESERVED_31_16,Reserved" hexmask.long.word 0x0 0.--15. 1. "LINK_ERROR_COUNT,LINK_ERROR_COUNT For a description of this standard USB register field see the eXtensible Host Controller Interface for Universal Serial Bus (USB) Specification 3.0." line.long 0x4 "PORTHLPMC_30,USB2 Port Hardware LPM Control Register Bit Definitions For a description of this standard USB register field. see the eXtensible Host Controller Interface for Universal Serial Bus (USB) Specification 3.0." hexmask.long 0x4 0.--31. 1. "RESERVED_31_0,Reserved For a description of this standard USB register field see the eXtensible Host Controller Interface for Universal Serial Bus (USB) Specification 3.0." tree.end tree "DWC_usb3_block_Host_Cntrl_Runtime_Regs (USB3 Host Cntrl Runtime Regs Block)" rgroup.long (0x0+0x1088)++0x7 line.long 0x0 "MFINDEX,Microframe Index Register Bit Definitions For a description of this standard USB register field. see the eXtensible Host Controller Interface for Universal Serial Bus (USB) Specification 3.0." hexmask.long.tbyte 0x0 14.--31. 1. "RESERVED_31_14,Reserved" hexmask.long.word 0x0 0.--13. 1. "MICROFRAME_INDEX,MICROFRAME_INDEX For a description of this standard USB register field see the eXtensible Host Controller Interface for Universal Serial Bus (USB) Specification 3.0." line.long 0x4 "RSVDZ,RsvdZ For a description of this standard USB register field. see the eXtensible Host Controller Interface for Universal Serial Bus (USB) Specification 3.0." hexmask.long 0x4 0.--31. 1. "RESERVED_31_0,Reserved" tree.end tree "DWC_usb3_block_Interrupter_Regs (USB3 Interrupter Regs Block)" group.long (0x0+0x1120)++0xB line.long 0x0 "IMAN,Interrupter Management Register Bit Definitions For a description of this standard USB register field. see the eXtensible Host Controller Interface for Universal Serial Bus (USB) Specification 3.0." hexmask.long 0x0 2.--31. 1. "RESERVED_31_2,Reserved" bitfld.long 0x0 1. "IE,IE For a description of this standard USB register field see the eXtensible Host Controller Interface for Universal Serial Bus (USB) Specification 3.0." "0,1" bitfld.long 0x0 0. "IP,IP Interrupt Pending For a description of this standard USB register field see the eXtensible Host Controller Interface for Universal Serial Bus (USB) Specification 3.0." "0,1" line.long 0x4 "IMOD,Interrupter Moderation Register The software may use this register to pace (or even out) the delivery of interrupts to the host CPU. This register provides a guaranteed inter-interrupt delay between interrupts asserted by the xHC. regardless of USB.." hexmask.long.word 0x4 16.--31. 1. "IMODC,Interrupt Moderation Counter (IMODC) - RW. Default = undefined. Down counter. Loaded with the IMODI value whenever IP is cleared to '0' counts down to '0' and stops. The associated interrupt is signaled whenever this counter is '0' the Event.." hexmask.long.word 0x4 0.--15. 1. "IMODI,Interrupt Moderation Interval (IMODI) - RW. Default = '4000' (~1ms). Minimum inter-interrupt interval. The interval is specified in 250ns increments. A value of '0' disables interrupt throttling logic and interrupts is generated immediately if IP =.." line.long 0x8 "ERSTSZ,Event Ring Segment Table Size Register Bit Definitions For a description of this standard USB register field. see the eXtensible Host Controller Interface for Universal Serial Bus (USB) Specification 3.0." hexmask.long.word 0x8 16.--31. 1. "RESERVED_31_16,Reserved" hexmask.long.word 0x8 0.--15. 1. "ERS_TABLE_SIZE,ERS_TABLE_SIZE For a description of this standard USB register field see the eXtensible Host Controller Interface for Universal Serial Bus (USB) Specification 3.0." rgroup.long (0xC+0x1120)++0x3 line.long 0x0 "RSVDP,RsvdP" hexmask.long 0x0 0.--31. 1. "RESERVED_31_0,Reserved" group.long (0x10+0x1120)++0xF line.long 0x0 "ERSTBA_LO,ERSTBA_LO" hexmask.long 0x0 6.--31. 1. "ERS_TABLE_BAR,ERS_TABLE_BAR" hexmask.long.byte 0x0 0.--5. 1. "RESERVED_5_0,Reserved" line.long 0x4 "ERSTBA_HI,ERSTBA_HI" hexmask.long 0x4 0.--31. 1. "ERS_TABLE_BAR,ERS_TABLE_BAR For a description of this standard USB register field see the eXtensible Host Controller Interface for Universal Serial Bus (USB) Specification 3.0." line.long 0x8 "ERDP_LO,ERDP_LO For a description of this standard USB register field. see the eXtensible Host Controller Interface for Universal Serial Bus (USB) Specification 3.0." hexmask.long 0x8 4.--31. 1. "ERD_PNTR,ERD_PNTR For a description of this standard USB register field see the eXtensible Host Controller Interface for Universal Serial Bus (USB) Specification 3.0." bitfld.long 0x8 3. "EHB,HC OS Owned SemaphoreERS_TABLE_SIZEHC BIOS Owned Semaphore USB SMI Enable SMI on Host System Error Enable - SMI on OS Ownership Enable - SMI on PCI Command Enable - SMI on BAR Enable - SMI on Event Interrupt - SMI on Host System Error - SMI on OS.." "0,1" bitfld.long 0x8 0.--2. "DESI,DESI - For a description of this standard USB register field see the eXtensible Host Controller Interface for Universal Serial Bus (USB) Specification 3.0." "0,1,2,3,4,5,6,7" line.long 0xC "ERDP_HI,ERDP_HI" hexmask.long 0xC 0.--31. 1. "ERD_PNTR,ERD_PNTR For a description of this standard USB register field see the eXtensible Host Controller Interface for Universal Serial Bus (USB) Specification 3.0." tree.end tree "DWC_usb3_block_Doorbell_Register (USB3 Doorbell Reg Block)" group.long (0x0+0x1152)++0x3 line.long 0x0 "DB,Doorbell Register Bit Field Definitions For a description of this standard USB register field. see the eXtensible Host Controller Interface for Universal Serial Bus (USB) Specification 3.0. Programming this field with random data will cause side.." hexmask.long.word 0x0 16.--31. 1. "DB_STREAM_ID,DB_STREAM_ID For a description of this standard USB register field see the eXtensible Host Controller Interface for Universal Serial Bus (USB) Specification 3.0." hexmask.long.byte 0x0 8.--15. 1. "RESERVED_15_8,Reserved" hexmask.long.byte 0x0 0.--7. 1. "DB_TARGET,DB_TARGET For a description of this standard USB register field see the eXtensible Host Controller Interface for Universal Serial Bus (USB) Specification 3.0." tree.end tree "DWC_usb3_block_HC_Extended_Capability_Register (USB3 HC Extended Capability Register Block)" group.long (0x0+0x2176)++0x7 line.long 0x0 "USBLEGSUP,USBLEGSUP" hexmask.long.byte 0x0 25.--31. 1. "RESERVED_31_25,Reserved" bitfld.long 0x0 24. "HC_OS_OWNED,HC_OS_OWNED SEMAPHORE For a description of this standard USB register field see the eXtensible Host Controller Interface for Universal Serial Bus (USB) Specification 3.0." "0,1" hexmask.long.byte 0x0 17.--23. 1. "RESERVED_23_17,Reserved" bitfld.long 0x0 16. "HC_BIOS_OWNED,HC_BIOS_OWNED SEMAPHORE For a description of this standard USB register field see the eXtensible Host Controller Interface for Universal Serial Bus (USB) Specification 3.0." "0,1" newline hexmask.long.byte 0x0 8.--15. 1. "NEXT_CAPABILITY_POINTER,NEXT_CAPABILITY_POINTER For a description of this standard USB register field see the eXtensible Host Controller Interface for Universal Serial Bus (USB) Specification 3.0." hexmask.long.byte 0x0 0.--7. 1. "CAPABILITY_ID,CAPABILITY_ID set_register_field_attribute DWC_usb3_map/DWC_usb3_block_HC_Extended_Capability_Register/USBLEGSUP/CAPABILITY_ID RegisterResetValue 0x1 For a description of this standard USB register field see the eXtensible Host Controller.." line.long 0x4 "USBLEGCTLSTS,USBLEGCTLSTS" bitfld.long 0x4 31. "SMI_ON_BAR,SMI_ON_BAR For a description of this standard USB register field see the eXtensible Host Controller Interface for Universal Serial Bus (USB) Specification 3.0." "0,1" bitfld.long 0x4 30. "SMI_ON_PCI,SMI_ON_PCI COMMAND For a description of this standard USB register field see the eXtensible Host Controller Interface for Universal Serial Bus (USB) Specification 3.0." "0,1" bitfld.long 0x4 29. "SMI_ON_OS,SMI_ON_OS OWNERSHIP CHANGE For a description of this standard USB register field see the eXtensible Host Controller Interface for Universal Serial Bus (USB) Specification 3.0." "0,1" hexmask.long.byte 0x4 21.--28. 1. "RESERVED_28_21,Reserved" newline rbitfld.long 0x4 20. "SMI_ON_HOST,SMI_ON_HOST SYSTEM ERROR For a description of this standard USB register field see the eXtensible Host Controller Interface for Universal Serial Bus (USB) Specification 3.0." "0,1" rbitfld.long 0x4 17.--19. "RESERVED_19_17,Reserved" "0,1,2,3,4,5,6,7" rbitfld.long 0x4 16. "SMI_ON_EVENT,SMI_ON_EVENT INTERRUPT For a description of this standard USB register field see the eXtensible Host Controller Interface for Universal Serial Bus (USB) Specification 3.0." "0,1" bitfld.long 0x4 15. "SMI_ON_BAR_E,SMI_ON_BAR ENABLE For a description of this standard USB register field see the eXtensible Host Controller Interface for Universal Serial Bus (USB) Specification 3.0." "0,1" newline bitfld.long 0x4 14. "SMI_ON_PCI_E,SMI_ON_PCI COMMAND ENABLE For a description of this standard USB register field see the eXtensible Host Controller Interface for Universal Serial Bus (USB) Specification 3.0." "0,1" bitfld.long 0x4 13. "SMI_ON_OS_E,SMI_ON_OS OWNERSHIP ENABLE For a description of this standard USB register field see the eXtensible Host Controller Interface for Universal Serial Bus (USB) Specification 3.0." "0,1" hexmask.long.byte 0x4 5.--12. 1. "RESERVED_12_5,Reserved" bitfld.long 0x4 4. "SMI_ON_HOST_E,SMI_ON_HOST SYSTEM ERROR ENABLE For a description of this standard USB register field see the eXtensible Host Controller Interface for Universal Serial Bus (USB) Specification 3.0." "0,1" newline rbitfld.long 0x4 1.--3. "RESERVED_3_1,Reserved" "0,1,2,3,4,5,6,7" bitfld.long 0x4 0. "USB_SMI_ENABLE,USB_SMI_ENABLE For a description of this standard USB register field see the eXtensible Host Controller Interface for Universal Serial Bus (USB) Specification 3.0." "0,1" tree.end tree "DWC_usb3_block_xHCI_Supt_USB20_Prt_Cap (USB3 xHCI Supported Protocol Capability (USB 2.0) Block)" rgroup.long (0x0+0x2192)++0xF line.long 0x0 "SUPTPRT2_DW0,SUPTPRT2_DW0" hexmask.long.byte 0x0 24.--31. 1. "MAJOR_REVISION,MAJOR_REVISION" hexmask.long.byte 0x0 16.--23. 1. "MINOR_REVISION,MINOR_REVISION" hexmask.long.byte 0x0 8.--15. 1. "NEXT_CAPABILITY_POINTER,NEXT_CAPABILITY_POINTER" newline hexmask.long.byte 0x0 0.--7. 1. "CAPABILITY_ID,CAPABILITY_ID For a description of this standard USB register field see the eXtensible Host Controller Interface for Universal Serial Bus (USB) Specification 3.0." line.long 0x4 "SUPTPRT2_DW1,Register SUPTPRT2_DW1" hexmask.long 0x4 0.--31. 1. "NAME_STRING,NAME_STRING For a description of this standard USB register field see the eXtensible Host Controller Interface for Universal Serial Bus (USB) Specification 3.0." line.long 0x8 "SUPTPRT2_DW2,xHCI Supported Protocol Capability_ Data Word 2 For a description of other register fields. see section 7.2 of the eXtensible Host Controller Interface for Universal Serial Bus (USB) Specification 3.0." hexmask.long.byte 0x8 28.--31. 1. "PSIC,PSIC" bitfld.long 0x8 25.--27. "MHD,Hub Depth For a description of this standard USB register field see the eXtensible Host Controller Interface for Universal Serial Bus (USB) Specification 3.0." "0,1,2,3,4,5,6,7" hexmask.long.byte 0x8 21.--24. 1. "RESERVED_24_21,Reserved" newline bitfld.long 0x8 20. "BLC,BESL LPM Capability. When this bit is set to: - 1: The ports described by this xHCI Supported Protocol Capability applies BESL timing to the BESL and BESLD fields of the PORTPMSC and PORTHLPMC registers. - 0: The ports described by this xHCI.." "The ports described by this xHCI Supported..,The ports described by this xHCI Supported.." bitfld.long 0x8 19. "HLC,Compatible Port Offset. Compatible Port Count Refer to Table 7-3 in the Databook." "0,1" bitfld.long 0x8 18. "IHI,IHI" "0,1" newline bitfld.long 0x8 17. "HSO,HSO" "0,1" hexmask.long.byte 0x8 8.--15. 1. "COMPATIBLE_PORT_COUNT,COMPATIBLE_PORT_COUNT For a description of this standard USB register field see the eXtensible Host Controller Interface for Universal Serial Bus (USB) Specification 3.0." hexmask.long.byte 0x8 0.--7. 1. "COMPATIBLE_PORT_OFFSET,COMPATIBLE_PORT_OFFSET For a description of this standard USB register field see the eXtensible Host Controller Interface for Universal Serial Bus (USB) Specification 3.0." line.long 0xC "SUPTPRT2_DW3,Register SUPTPRT2_DW3" hexmask.long 0xC 5.--31. 1. "RESERVED_31_5,Reserved" hexmask.long.byte 0xC 0.--4. 1. "PROTCL_SLT_TY,Protocol Slot Type" tree.end tree "DWC_usb3_block_xHCI_Supt_USB30_Prt_Cap (USB3 xHCI Supported Protocol Capability (USB 3.0) Block)" rgroup.long (0x0+0x2208)++0xF line.long 0x0 "SUPTPRT3_DW0,Register SUPTPRT3_DW0" hexmask.long.byte 0x0 24.--31. 1. "MAJOR_REVISION,MAJOR_REVISION For a description of this standard USB register field see the eXtensible Host Controller Interface for Universal Serial Bus (USB) Specification 3.0." hexmask.long.byte 0x0 16.--23. 1. "MINOR_REVISION,MINOR_REVISION For a description of this standard USB register field see the eXtensible Host Controller Interface for Universal Serial Bus (USB) Specification 3.0." hexmask.long.byte 0x0 8.--15. 1. "NEXT_CAPABILITY_POINTER,NEXT_CAPABILITY_POINTER For a description of this standard USB register field see the eXtensible Host Controller Interface for Universal Serial Bus (USB) Specification 3.0." hexmask.long.byte 0x0 0.--7. 1. "CAPABILITY_ID,CAPABILITY_ID For a description of this standard USB register field see the eXtensible Host Controller Interface for Universal Serial Bus (USB) Specification 3.0." line.long 0x4 "SUPTPRT3_DW1,Register SUPTPRT3_DW1" hexmask.long 0x4 0.--31. 1. "NAME_STRING,NAME_STRING For a description of this standard USB register field see the eXtensible Host Controller Interface for Universal Serial Bus (USB) Specification 3.0." line.long 0x8 "SUPTPRT3_DW2,SUPTPRT3_DW2 For a description of this standard USB register field. see the eXtensible Host Controller Interface for Universal Serial Bus (USB) Specification 3.0." hexmask.long.byte 0x8 28.--31. 1. "PSIC,PSIC" bitfld.long 0x8 25.--27. "MHD,Hub Depth For a description of this standard USB register field see the eXtensible Host Controller Interface for Universal Serial Bus (USB) Specification 3.0." "0,1,2,3,4,5,6,7" hexmask.long.byte 0x8 8.--15. 1. "COMPATIBLE_PORT_COUNT,COMPATIBLE_PORT_COUNT For a description of this standard USB register field see the eXtensible Host Controller Interface for Universal Serial Bus (USB) Specification 3.0." hexmask.long.byte 0x8 0.--7. 1. "COMPATIBLE_PORT_OFFSET,COMPATIBLE_PORT_OFFSET For a description of this standard USB register field see the eXtensible Host Controller Interface for Universal Serial Bus (USB) Specification 3.0." line.long 0xC "SUPTPRT3_DW3,SUPTPRT3_DW3" hexmask.long 0xC 5.--31. 1. "RESERVED_31_5,Reserved" hexmask.long.byte 0xC 0.--4. 1. "PROTCL_SLT_TY,Protocol Slot Type" tree.end tree "DWC_usb3_block_Debug_Capability_Structure (USB3 Debug Capability Structure Block)" rgroup.long (0x0+0x2224)++0x3 line.long 0x0 "DCID,DCID" hexmask.long.word 0x0 21.--31. 1. "RESERVED_31_21,Reserved" hexmask.long.byte 0x0 16.--20. 1. "DCERSTMAX,DCERSTMAX" hexmask.long.byte 0x0 8.--15. 1. "NEXT_CAPABILITY_POINTER,NEXT_CAPABILITY_POINTER" hexmask.long.byte 0x0 0.--7. 1. "CAPABILITY_ID,CAPABILITY_ID" group.long (0x4+0x2224)++0x7 line.long 0x0 "DCDB,Register DCDB" hexmask.long.word 0x0 16.--31. 1. "RESERVED_31_16,Reserved" hexmask.long.byte 0x0 8.--15. 1. "DBTARGET,DBTARGET" hexmask.long.byte 0x0 0.--7. 1. "RESERVED_7_0,Reserved" line.long 0x4 "DCERSTSZ,DCERSTSZ" hexmask.long.word 0x4 16.--31. 1. "RESERVED_31_16,Reserved" hexmask.long.word 0x4 0.--15. 1. "ERS_TABLE_SIZE,ERS_TABLE_SIZE" group.long (0x10+0x2224)++0x13 line.long 0x0 "DCERSTBA_LO,DCERSTBA_LO" hexmask.long 0x0 4.--31. 1. "ERS_TABLE_BAR,ERS_TABLE_BAR" hexmask.long.byte 0x0 0.--3. 1. "RESERVED_3_0,Reserved" line.long 0x4 "DCERSTBA_HI,Register DCERSTBA_HI" hexmask.long 0x4 0.--31. 1. "ERS_TABLE_BAR,ERS_TABLE_BAR" line.long 0x8 "DCERDP_LO,DCERDP_LO" hexmask.long 0x8 4.--31. 1. "DEQUEUE_POINTER,DEQUEUE_POINTER" rbitfld.long 0x8 3. "RESERVED_3,Reserved" "0,1" bitfld.long 0x8 0.--2. "DESI,DESI" "0,1,2,3,4,5,6,7" line.long 0xC "DCERDP_HI,DCERDP_HI" hexmask.long 0xC 0.--31. 1. "DEQUEUE_POINTER,DEQUEUE_POINTER" line.long 0x10 "DCCTRL,DCCTRL" bitfld.long 0x10 31. "DCE,DCE" "0,1" hexmask.long.byte 0x10 24.--30. 1. "DEVICE_ADDRESS,DEVICE_ADDRESS" hexmask.long.byte 0x10 16.--23. 1. "DEBUG_MAX_BURST_SIZE,DEBUG_PROTOCOL" hexmask.long.word 0x10 5.--15. 1. "RESERVED_15_5,Reserved" newline bitfld.long 0x10 4. "DRC,DRC" "0,1" bitfld.long 0x10 3. "HIT,HIT" "0,1" bitfld.long 0x10 2. "HOT,HOT" "0,1" bitfld.long 0x10 1. "LSE,LSE" "0,1" newline rbitfld.long 0x10 0. "DCR,DCR" "0,1" rgroup.long (0x24+0x2224)++0x3 line.long 0x0 "DCST,DCST" hexmask.long.byte 0x0 24.--31. 1. "DEBUG_PORT_NUMBER,DEBUG_PORT_NUMBER" hexmask.long.tbyte 0x0 2.--23. 1. "RESERVED_23_2,Reserved" bitfld.long 0x0 1. "SBR,SBR" "0,1" bitfld.long 0x0 0. "ER,ER" "0,1" group.long (0x28+0x2224)++0x3 line.long 0x0 "DCPORTSC,Register DCPORTSC" hexmask.long.byte 0x0 24.--31. 1. "RESERVED_31_24,Reserved" bitfld.long 0x0 23. "CEC,CEC" "0,1" bitfld.long 0x0 22. "PLC,PLC" "0,1" bitfld.long 0x0 21. "PRC,PRC" "0,1" newline rbitfld.long 0x0 18.--20. "RESERVED_20_18,Reserved" "0,1,2,3,4,5,6,7" bitfld.long 0x0 17. "CSC,CSC" "0,1" rbitfld.long 0x0 14.--16. "RESERVED_16_14,Reserved" "0,1,2,3,4,5,6,7" hexmask.long.byte 0x0 10.--13. 1. "PORTSPEED,PORTSPEED" newline rbitfld.long 0x0 9. "RESERVED_9,Reserved" "0,1" hexmask.long.byte 0x0 5.--8. 1. "PLS,PLS" rbitfld.long 0x0 4. "PR,PR" "0,1" rbitfld.long 0x0 2.--3. "RESERVED_3_2,Reserved" "0,1,2,3" newline bitfld.long 0x0 1. "PED,PED" "0,1" rbitfld.long 0x0 0. "CCS,CCS" "0,1" group.long (0x30+0x2224)++0xF line.long 0x0 "DCCP_LO,DCCP_LO" hexmask.long 0x0 4.--31. 1. "DCCPR,DCCPR" hexmask.long.byte 0x0 0.--3. 1. "RESERVED_3_0,Reserved" line.long 0x4 "DCCP_HI,Register DCCP_HI" hexmask.long 0x4 0.--31. 1. "DCCPR,DCCPR" line.long 0x8 "DCDDI1,Register DCDDI1" hexmask.long.word 0x8 16.--31. 1. "VENDORID,VENDORID" hexmask.long.byte 0x8 8.--15. 1. "RESERVED_15_8,Reserved" hexmask.long.byte 0x8 0.--7. 1. "DBCPROTOCOL,DBCPROTOCOL" line.long 0xC "DCDDI2,Register DCDDI2" hexmask.long.word 0xC 16.--31. 1. "DEVICEREV,DEVICEREV" hexmask.long.word 0xC 0.--15. 1. "PRODUCTID,PRODUCTID" tree.end tree.end tree "USB2_NCR" base ad:0x3126D000 group.long 0x0++0x3 line.long 0x0 "INTEN,INTEN" bitfld.long 0x0 15. "INTEN_RSVD8,INTEN_RSVD8" "0,1" newline bitfld.long 0x0 14. "INTEN_RSVD7,INTEN_RSVD7" "0,1" bitfld.long 0x0 13. "INTEN_RSVD6,INTEN_RSVD6" "0,1" newline bitfld.long 0x0 12. "INTEN_RSVD5,INTEN_RSVD5" "0,1" bitfld.long 0x0 11. "INTEN_RSVD4,INTEN_RSVD4" "0,1" newline bitfld.long 0x0 10. "INTEN_RSVD3,INTEN_RSVD3" "0,1" bitfld.long 0x0 9. "INTEN_RSVD2,INTEN_RSVD2" "0,1" newline bitfld.long 0x0 8. "INTEN_RSVD1,INTEN_RSVD1" "0,1" bitfld.long 0x0 7. "INTEN_RSVD0,INTEN_RSVD0" "0,1" newline bitfld.long 0x0 6. "INTEN_WAKEUP,WAKEUP interrupt enalbe 1:enable 0:disable" "disable,enable" bitfld.long 0x0 5. "INTEN_HOST_LEGACY_SMI_INTERRUPT,HOST_LEGACY_SMI_INTERRUPT enable 1:enable 0:disable" "disable,enable" newline bitfld.long 0x0 4. "INTEN_PME_GENERATION,Power Management Event (PME) interrupt enable 1: enable 0:disable" "disable,enable" bitfld.long 0x0 3. "INTEN_BC_INTERRUPT,Battery Charger interrupt enable 1:enable 0:disable" "disable,enable" newline bitfld.long 0x0 2. "INTEN_CHGDET,Battery Charger Detect interrupt 1:enable 0:disable" "disable,enable" bitfld.long 0x0 1. "INTEN_HOST_SYSTEM_ERR,host_system_err interrupt enable. host_system_err can occur when the host controller encounters an 'Error' response in the AHB the AXI or the Native Master Bus. 1:enable 0:disable" "disable,enable" newline bitfld.long 0x0 0. "INTEN_CORE_INTERRUPT,USB CORE INTERRUPT enable 1:enable 0:disable" "disable,enable" group.long 0x10++0x7 line.long 0x0 "CTRL_0,CTRL_0" bitfld.long 0x0 29.--31. "DEBOUNCECTL,Enables Bus Filters for the following UTMI/ULPI signals and PIPE3PowerControl input signal from the PHY. utmiotg_vbusvalid utmisrp_bvalid pipe3_PowerPresent" "0,1,2,3,4,5,6,7" bitfld.long 0x0 28. "WAKEBYIDCHG,WAKEBYIDCHG" "0,1" newline bitfld.long 0x0 27. "WAKEBYVBUSCHG,WAKEBYVBUSCHG" "0,1" bitfld.long 0x0 26. "WAKEBYDPDMCHG,WAKEBYDPDMCHG" "0,1" newline bitfld.long 0x0 25. "WAKEBYREMOTEWAKE,WAKEBYREMOTEWAKE" "0,1" bitfld.long 0x0 24. "WAKEBYHSDSCNNT,WAKEBYHSDSCNNT" "0,1" newline bitfld.long 0x0 23. "WAKEBYHSCNNT,WAKEBYHSCNNT" "0,1" bitfld.long 0x0 22. "WAKEBYOC,WAKEBYOC" "0,1" newline bitfld.long 0x0 21. "XHC_BME,This signal is used to disable the bus mastering capability of the xHC. In a PCI system it comes from the Bus Master Enable (BME) bit of the Device Control Register in the PCI Configuration register space. 1'b0: Bus mastering capability is.." "Bus mastering capability is disabled,Bus mastering capability is enabled" hexmask.long.byte 0x0 17.--20. 1. "BUS_FILTER_BYPASS,Bus Filter Bypass. Disables the internal bus filters that are enabled by DWC_USB3_EN_BUS_FILTERS coreConsultant parameter. This static signal is present only when DWC_USB3_EN_BUS_FILTERS is 1. It is expected that this signal is set or.." newline hexmask.long.byte 0x0 11.--16. 1. "FLADJ_30MHZ_REG,HS Jitter Adjustment. Indicates the correction required to accommodate mac3 clock and utmi clock jitter to measure 125 's duration. With fladj_30mhz_reg tied to zero the high speed 125us micro-frame is counted for 123933ns. You must.." bitfld.long 0x0 10. "HOST_LEGACY_SMI_BAR_WR,PCI Base Address register (BAR) write: one clock pulse. The PCIe interface need to generate one clock pulse during PCIe Base Address register (BAR) write. Active State: High" "0,1" newline bitfld.long 0x0 9. "HOST_LEGACY_SMI_PCI_CMD_REG_WR,PCI command register write: one clock pulse. The PCIe interface needs to generate one clock pulse during PCIe command register write. Tie this low if you are not using Legacy support. Active State: High" "0,1" bitfld.long 0x0 8. "HOST_MSI_ENABLE,This enables the pulse type interrupt signal (one bus clock cycle) 'interrupt' port instead of level-sensitive interrupt. When interfacing to PCIe this allows you to easily map 'interrupt' to MSI in the PCIe controller. MSI can only be.." "0,1" newline bitfld.long 0x0 7. "HOST_PORT_POWER_CONTROL_PRESENT,This port defines the bit [3] of Capability Parameters (HCCPARAMS). Change the PPC value through the pin Port Power Control (PPC). This indicates whether the host controller implementation includes port power control..." "Indicates that the port does not have port power..,Indicates that the port has port power switches" bitfld.long 0x0 6. "DISRXDETU3RXDET,DisRxDetU3RxDet of USB 3.0 SS Ports This input signal requests the controller to stop issuing more PHY commands and release the PIPE ownership. The controller acknowledges this request by asserting the DisRxDetU3RxDet_ack signal. This.." "0,1" newline bitfld.long 0x0 5. "STARTRXDETU3RXDET,StartRxdetU3RxDet of USB 3.0 SS Ports This signal is the Start Receiver Detection in U3/Rx.Detect (StartRxdetU3RxDet). If DisRxDetU3RxDet is set and the link is in either U3 or Rx.Detect state the controller starts receiver detection.." "0,1" bitfld.long 0x0 4. "HOST_U3_PORT_DISABLE,USB 3.0 SS Port Disable control. 0: Port Enabled 1: Port Disabled This signal when '1' stops reporting connect/disconnect events the port and keeps the port in disabled state. This could be used for security reasons where.." "Port Enabled,Port Disabled" newline bitfld.long 0x0 3. "HOST_U2_PORT_DISABLE,USB 2.0 Port Disable control. 0: Port Enabled 1: Port Disabled When '1' this signal stops reporting connect/disconnect events the port and keeps the port in disabled state. This could be used for security reasons where.." "Port Enabled,Port Disabled When '1'" bitfld.long 0x0 1.--2. "HUB_PORT_PERM_ATTACH,Indicates if the device attached to a downstream port is permanently attached or not. 0: Not permanently attached 1: Permanently attached The lower bits are for USB 2.0 ports and the higher bits are for USB 3.0 SS ports:.." "Not permanently attached,Permanently attached,?,?" newline bitfld.long 0x0 0. "PME_EN,In host mode when hibernation is disabled (GCTL.GblHibernationEn=0) this input enables the controller to generate the pme_generation signal. unused in: Device mode Host mode when hibernation is enabled (GCTL.GblHibernationEn=1)" "0,1" line.long 0x4 "CTRL_1,CTRL_1" hexmask.long.word 0x4 22.--31. 1. "RSVD0,RSVD0" hexmask.long.byte 0x4 18.--21. 1. "RAM_DEBUG_SEL,ram_debug_sel: 0x0-0x7: internal RAM0 0x8-0xB:internal RAM1 0xC-0xF:internal RAM2" newline bitfld.long 0x4 16.--17. "CTRL_REF_SEL,ctrl_ref_clk select: 0 : i_ref_alt_clk_p 1 : i_ref_alt_clk_p 2: i_suspend_clk 3:i_ref_output_clk" "i_ref_alt_clk_p,i_ref_alt_clk_p,i_suspend_clk,i_ref_output_clk" hexmask.long.word 0x4 6.--15. 1. "DRVRSM32KCTRL1,DRVRSM32KCTRL1" newline hexmask.long.byte 0x4 1.--5. 1. "DRVRSM32KCTRL0,DRVRSM32KCTRL0" bitfld.long 0x4 0. "DRVRSM32KEN,DRVRSM32KEN" "0,1" repeat 6. (list 0x2 0x3 0x4 0x5 0x6 0x7 )(list 0x0 0x4 0x8 0xC 0x10 0x14 ) group.long ($2+0x18)++0x3 line.long 0x0 "CTRL_$1,CTRL_2" hexmask.long 0x0 0.--31. 1. "RSVD0,RSVD0" repeat.end group.long 0x80++0x3 line.long 0x0 "INTR,INTR" bitfld.long 0x0 15. "INTR_RSVD8,INTR_RSVD8" "0,1" newline bitfld.long 0x0 14. "INTR_RSVD7,INTR_RSVD7" "0,1" bitfld.long 0x0 13. "INTR_RSVD6,INTR_RSVD6" "0,1" newline bitfld.long 0x0 12. "INTR_RSVD5,INTR_RSVD5" "0,1" bitfld.long 0x0 11. "INTR_RSVD4,INTR_RSVD4" "0,1" newline bitfld.long 0x0 10. "INTR_RSVD3,INTR_RSVD3" "0,1" bitfld.long 0x0 9. "INTR_RSVD2,INTR_RSVD2" "0,1" newline bitfld.long 0x0 8. "INTR_RSVD1,INTR_RSVD1" "0,1" bitfld.long 0x0 7. "INTR_RSVD0,INTR_RSVD0" "0,1" newline bitfld.long 0x0 6. "INTR_WAKEUP,INTR_WAKEUP" "0,1" bitfld.long 0x0 5. "INTR_HOST_LEGACY_SMI_INTERRUPT,INTR_HOST_LEGACY_SMI_INTERRUPT" "0,1" newline bitfld.long 0x0 4. "INTR_PME_GENERATION,INTR_PME_GENERATION" "0,1" bitfld.long 0x0 3. "INTR_BC_INTERRUPT,INTR_BC_INTERRUPT" "0,1" newline bitfld.long 0x0 2. "INTR_CHGDET,INTR_CHGDET" "0,1" bitfld.long 0x0 1. "INTR_HOST_SYSTEM_ERR,INTR_HOST_SYSTEM_ERR" "0,1" newline bitfld.long 0x0 0. "INTR_CORE_INTERRUPT,INTR_CORE_INTERRUPT" "0,1" rgroup.long 0x90++0x7 line.long 0x0 "STS_0,STS_0" bitfld.long 0x0 1. "SUSPEND_CLK_ACTIVE,indicate the SUSPEND_CLK is ACTIVE or not 1: active 0:inactive" "inactive,active" newline bitfld.long 0x0 0. "ACLK_ACTIVE,indicate the bus clk is ACTIVE or not 1: active 0:inactive" "inactive,active" line.long 0x4 "STS_1,STS_1" bitfld.long 0x4 17. "DISRXDETU3RXDET_ACK,DisRxDetU3RxDet_ack of USB 3.0 SS Ports This signal is an acknowledgment of DisRxDetU3RxDet. When this signal is 1'b1 the controller releases the ownership of the the PIPE interface and does not issue PHY commands to the PIPE.." "0,1" newline bitfld.long 0x4 14.--16. "CLK_GATE_CTRL,Clock gating control This signal indicates the clock gating controls used for gating RAM and bus clocks. Bit[0] is gating control for bus_clk bit[1] and bit[2] is for ram_clk_in. This output must be used only for debug purposes." "0,1,2,3,4,5,6,7" bitfld.long 0x4 12.--13. "OPERATIONAL_MODE,Port Capability Direction 2'b01: for default Host operation (Power on value allowed only when DWC_USB3_MODE=1) 2'b10: for default Device operation (Power on value allowed only when DWC_USB3_MODE!=1)" "?,for default Host operation,for default Device operation,?" newline hexmask.long.word 0x4 0.--11. 1. "HOST_CURRENT_BELT,Current BELT Value. This signal indicates the minimum value of all received BELT values and the BELT that is set by the Set LTV command. This signal is valid only in Host mode." repeat 9. (list 0x2 0x3 0x4 0x5 0x7 0x8 0x9 0xA 0xB )(list 0x0 0x4 0x8 0xC 0x14 0x18 0x1C 0x20 0x24 ) rgroup.long ($2+0x98)++0x3 line.long 0x0 "STS_$1,STS_2" hexmask.long 0x0 0.--31. 1. "LOGIC_ANALYZER_TRACE_0,LOGIC_ANALYZER_TRACE_0" repeat.end rgroup.long 0xA8++0x3 line.long 0x0 "STS_6,STS_6" bitfld.long 0x0 0.--2. "DEBUG_2,DEBUG_2" "0,1,2,3,4,5,6,7" tree.end tree "USB_PHY2" base ad:0x31280000 rgroup.word 0x0++0x1 line.word 0x0 "SUP_DIG_IDCODE_LO,Low 16 bits of IDCODE" newline hexmask.word 0x0 0.--15. 1. "DATA," rgroup.word 0x4++0x1 line.word 0x0 "SUP_DIG_IDCODE_HI,High 16 bits of IDCODE" newline hexmask.word 0x0 0.--15. 1. "DATA," group.word 0x8++0x1 line.word 0x0 "SUP_DIG_DEBUG,Debug controls" newline hexmask.word 0x0 7.--15. 1. "RESERVED_15_7,Reserved for Future use" newline bitfld.word 0x0 5.--6. "DTB_SEL,The lane DTB's are OR'd together with the support DTB signals selected with the below encodings 0 - none 1 - reset_ctl DTB output 2 - scope DTB output 3 - rtune DTB output" "none,reset_ctl DTB output,scope DTB output,rtune DTB output" newline hexmask.word.byte 0x0 0.--4. 1. "TX_VREF_SEL," group.word 0xC++0x1 line.word 0x0 "SUP_DIG_RTUNE_DEBUG,Resistor tuning debug controls" newline rbitfld.word 0x0 15. "RESERVED_15_15,Reserved for Future use" "0,1" newline hexmask.word 0x0 5.--14. 1. "VALUE,Value to use when triggering SET_VAL field only the 6 LSB's are used when setting rx or tx cal values (USER2 - read-write and custom)" newline bitfld.word 0x0 3.--4. "TYPE,Type of manual tuning or register read/write to execute 0 - ADC or read/write rt_value 1 - Rx tune or read/write rx_cal_val (only 6 bits) 2 - Tx tune or read/write tx_cal_val (only 6 bits) 3 - Resref detect (no affect when triggering SET_VAL.." "ADC,Rx tune,read-write and custom),Resref detect" newline bitfld.word 0x0 2. "SET_VAL,Set value Write to a 1 to manually write the register specified by the TYPE field to the value in the VALUE field (USER2 - read-write and custom)" "0,1" newline bitfld.word 0x0 1. "MAN_TUNE,Write to a 1 to do a manual tuning specified by TYPE field starting a manual tune while a tune is currently running can cause unpredictable results. For use only when you know the state of the rtune circuit. (USER2 - read-write and custom)" "0,1" newline bitfld.word 0x0 0. "FLIP_COMP,Invert analog comparator output (USER2 - read-write and custom)" "0,1" rgroup.word 0x10++0x1 line.word 0x0 "SUP_DIG_RTUNE_STAT,Resistor tuning register status" newline hexmask.word.byte 0x0 10.--15. 1. "RESERVED_15_10,Reserved for Future use" newline hexmask.word 0x0 0.--9. 1. "STAT,Current value of the register specifed by the TYPE field in the debug control register. Set the TYPE field in the DEBUG register and then do a read of this register. (RU - read-only volatile)" group.word 0x14++0x1 line.word 0x0 "SUP_DIG_SS_PHASE,Current MPLL phase selector value" newline bitfld.word 0x0 13.--15. "REF_SEL_DIV,Reference Divisor to get better resolution and lower PPM errors when synthesizing from a non-integer reference clock. NOTE: Default value is 4. One is added in hardware to give a range of 1 to 8. (volatile and 2 reads needed to read value)" "0,1,2,3,4,5,6,7" newline bitfld.word 0x0 12. "PH_SEL,Phase Mixer Clock select. 1: is pmix. 0 is VCO. (volatile and 2 reads needed to read value)" "?,is pmix" newline bitfld.word 0x0 11. "ZERO_FREQ,Zero frequency register. NOTES: Must be set for PHASE writes to stick (volatile and 2 reads needed to read value)" "0,1" newline hexmask.word 0x0 2.--10. 1. "VAL,Phase value from zero reference (volatile and 2 reads needed to read value)" newline bitfld.word 0x0 0.--1. "DTHR,Bits below the useful resolution (volatile and 2 reads needed to read value)" "0,1,2,3" group.word 0x18++0x1 line.word 0x0 "SUP_DIG_SS_FREQ,Frequency Control for Spread Spectrum" newline rbitfld.word 0x0 15. "RESERVED_15_15,Reserved for Future use" "0,1" newline bitfld.word 0x0 14. "FREQ_OVRD,Frequency Reigster Override. NOTE: Must be set for PHASE writes to stick (volatile and 2 reads needed to read value)" "0,1" newline hexmask.word.byte 0x0 7.--13. 1. "FREQ_PK,Peak Frequency Value (for changing direction) (volatile and 2 reads needed to read value)" newline hexmask.word.byte 0x0 0.--6. 1. "FREQ_CNT_INIT,Initial Frequency Counter Value (volatile and 2 reads needed to read value)" group.word 0x1C++0x1 line.word 0x0 "SUP_DIG_HSP_SS_PHASE,Current HSP_PMIX SSC phase sel value" newline hexmask.word.byte 0x0 11.--15. 1. "RESERVED_15_11,Reserved for Future use" newline hexmask.word.byte 0x0 4.--10. 1. "VAL,SSC phase value from zero reference (volatile and 2 reads needed to read value)" newline hexmask.word.byte 0x0 0.--3. 1. "DTHR,Bits below the useful resolution (volatile and 2 reads needed to read value)" group.word 0x20++0x1 line.word 0x0 "SUP_DIG_MPLL_CNT_CTL,Control for fixed or variable MPLL Count Selection" newline hexmask.word 0x0 1.--15. 1. "RESERVED_15_1,Reserved for Future use" newline bitfld.word 0x0 0. "VAR_CNT_EN,Selects variable count when enabled (Default = fixed count)" "0,1" group.word 0x24++0x1 line.word 0x0 "SUP_DIG_CR_PARA_ALU_CTL,Control for CR Parallel ALU access" newline hexmask.word 0x0 5.--15. 1. "RESERVED_15_5,Reserved for Future use" newline hexmask.word.byte 0x0 1.--4. 1. "CR_PARA_ALU_OPCODE,Opcode for the ALU when CR para access is enabled. Valid opcodes are as follows: 0 - Zero the accumulator 1 - Add control register read result to accumulator 2 - Add control register write data to accumulator 3 - Shift accumulator left.." newline bitfld.word 0x0 0. "CR_PARA_ALU_ACCESS_EN,Enable access to the ALU through the CR parallel bus." "0,1" rgroup.word 0x28++0x1 line.word 0x0 "SUP_DIG_CR_PARA_ALU_FLAGS,Flags from the ALU when CR para access is enabled." newline hexmask.word 0x0 4.--15. 1. "RESERVED_15_4,Reserved for Future use" newline hexmask.word.byte 0x0 0.--3. 1. "DATA,Flags from the ALU when CR para access is enabled. Valid ALU flags: 0 - Signedness used for next ADD_PHSEL command. (1=signed 0=unsigned) 1 - Signedness for ADD_PHSEL command has been chosen by a previous ADD_PHSEL command. 2 - Error detected.." group.word 0x40++0x1 line.word 0x0 "SUP_DIG_ATEOVRD,Override values for incoming controls from ASIC" newline hexmask.word 0x0 3.--15. 1. "RESERVED_15_3,Reserved for Future use" newline bitfld.word 0x0 2. "ATEOVRD_EN,Override enable for ATE signals. NOTE: This register is only accessible through cregs. Does not retain state during reset or ATPG. (USER2 - read-write and custom)" "0,1" newline bitfld.word 0x0 1. "REF_USB2_EN,Override value for USB HSP PHY ref_clk enable. (USER2 - read-write and custom)" "0,1" newline bitfld.word 0x0 0. "REF_CLKDIV2,Override value for SSP ref_clk pre-scaler. (USER2 - read-write and custom)" "0,1" group.word 0x44++0x1 line.word 0x0 "SUP_DIG_MPLL_OVRD_IN_LO,Override values for incoming RTUNE and MPLL controls from ASIC" newline bitfld.word 0x0 15. "RES_ACK_IN_OVRD,Override enable for res_ack_in" "0,1" newline bitfld.word 0x0 14. "RES_ACK_IN,Override value for res_ack_in" "0,1" newline bitfld.word 0x0 13. "RES_REQ_IN_OVRD,Override enable for res_req_in" "0,1" newline bitfld.word 0x0 12. "RES_REQ_IN,Override value for res_req_in" "0,1" newline bitfld.word 0x0 11. "RTUNE_REQ_OVRD,Override enable for rtune_req" "0,1" newline bitfld.word 0x0 10. "RTUNE_REQ,Override value for rtune_req" "0,1" newline bitfld.word 0x0 9. "MPLL_MULTIPLIER_OVRD,Override enable for mpll_multipler" "0,1" newline hexmask.word.byte 0x0 2.--8. 1. "MPLL_MULTIPLIER,Override value for mpll_multipler" newline bitfld.word 0x0 1. "MPLL_EN_OVRD,Override enable for mpll_en" "0,1" newline bitfld.word 0x0 0. "MPLL_EN,Override value for mpll_en" "0,1" group.word 0x48++0x1 line.word 0x0 "SUP_DIG_MPLL_OVRD_IN_HI,Override values for incoming VBOOST LVL and MPLL controls from ASIC" newline bitfld.word 0x0 13.--15. "TX_VBOOST_LVL,Override value for tx_vboost_lvl. Override enabled using LEVEL_EN from LEVEL_OVRD_IN register." "0,1,2,3,4,5,6,7" newline bitfld.word 0x0 12. "MPLL_REFSSC_CLK_EN_OVRD,Override enable for mpll_refssc_clk_en" "0,1" newline bitfld.word 0x0 11. "MPLL_REFSSC_CLK_EN,Override value for mpll_refssc_clk_en" "0,1" newline bitfld.word 0x0 10. "MPLL_RST,Reset the MPLL state machine Writing the register with this bit set will reset the MPLL power up/down FSM regardless of the current state of the register bit." "0,1" newline bitfld.word 0x0 9. "FSEL_OVRD,Override enable for fsel[2:0]" "0,1" newline bitfld.word 0x0 6.--8. "FSEL,Override value for fsel [2:0]" "0,1,2,3,4,5,6,7" newline bitfld.word 0x0 5. "MPLL_WORD_CLK_EN_OVRD,Override enable for mpll_word_clk_en" "0,1" newline bitfld.word 0x0 4. "MPLL_WORD_CLK_EN,Override value for mpll_word_clk_en" "0,1" newline bitfld.word 0x0 3. "MPLL_DWORD_CLK_EN_OVRD,Override enable for mpll_dword_clk_en" "0,1" newline bitfld.word 0x0 2. "MPLL_DWORD_CLK_EN,Override value for mpll_dword_clk_en" "0,1" newline bitfld.word 0x0 1. "MPLL_QWORD_CLK_EN_OVRD,Override enable for mpll_qword_clk_en" "0,1" newline bitfld.word 0x0 0. "MPLL_QWORD_CLK_EN,Override value for mpll_qword_clk_en" "0,1" group.word 0x4C++0x1 line.word 0x0 "SUP_DIG_SSC_OVRD_IN,Override values for incoming SSC controls from ASIC" newline rbitfld.word 0x0 14.--15. "RESERVED_15_14,Reserved for Future use" "0,1,2,3" newline bitfld.word 0x0 13. "SSC_OVRD_IN_EN,Override enable for Spread Spectrum generator." "0,1" newline bitfld.word 0x0 12. "SSC_EN,Override value for SSC enable." "0,1" newline bitfld.word 0x0 9.--11. "SSC_RANGE,Override value for SSC modulation range." "0,1,2,3,4,5,6,7" newline hexmask.word 0x0 0.--8. 1. "SSC_REF_CLK_SEL,Override value for reference clock scaling" group.word 0x50++0x1 line.word 0x0 "SUP_DIG_BS_OVRD_IN,Override values for incoming BS controls from ASIC" newline hexmask.word.byte 0x0 12.--15. 1. "RESERVED_15_12,Reserved for Future use" newline bitfld.word 0x0 11. "EN,Enable override values for all inputs controlled by this register" "0,1" newline bitfld.word 0x0 10. "INVERT,Override value for bs_invert" "0,1" newline bitfld.word 0x0 9. "INIT,Override value for bs_init" "0,1" newline bitfld.word 0x0 8. "HIGHZ,Override value for bs_highz" "0,1" newline bitfld.word 0x0 7. "CLAMP,Override value for bs_clamp" "0,1" newline bitfld.word 0x0 6. "EXTEST_AC,Override value for bs_extest_ac" "0,1" newline bitfld.word 0x0 5. "EXTEST,Override value for bs_extest" "0,1" newline bitfld.word 0x0 4. "PRELOAD,Override value for bs_preload" "0,1" newline bitfld.word 0x0 3. "UPDATE_DR,Override value for bs_update_dr" "0,1" newline bitfld.word 0x0 2. "CAPTURE_DR,Override value for bs_capture_dr" "0,1" newline bitfld.word 0x0 1. "SHIFT_DR,Override value for bs_shift_dr" "0,1" newline bitfld.word 0x0 0. "IN,Override value for bs_in" "0,1" group.word 0x54++0x1 line.word 0x0 "SUP_DIG_LEVEL_OVRD_IN,Override values for acjt_level and los_level" newline bitfld.word 0x0 13.--15. "LOS_BIAS,Override value for los_bias" "0,1,2,3,4,5,6,7" newline bitfld.word 0x0 12. "MPLL_HALF_RATE_OVRD,Enable override value for mpll_half_rate" "0,1" newline bitfld.word 0x0 11. "MPLL_HALF_RATE,Override value for mpll_half_rate" "0,1" newline bitfld.word 0x0 10. "LEVEL_EN,Enable override values for tx_vboost_lvl/los_bias/los_level/acjt_level inputs controlled by this and MPLL_OVRD_IN_HI registers" "0,1" newline hexmask.word.byte 0x0 5.--9. 1. "ACJT_LEVEL,Override value for acjt_level" newline hexmask.word.byte 0x0 0.--4. 1. "LOS_LEVEL,Override value for los_level" group.word 0x58++0x1 line.word 0x0 "SUP_DIG_SUP_OVRD_OUT,Override values for support block" newline hexmask.word.byte 0x0 10.--15. 1. "RESERVED_15_10,Reserved for Future use" newline bitfld.word 0x0 9. "MPLL_STATE_OVRD,Override enable for mpll_state output" "0,1" newline bitfld.word 0x0 8. "MPLL_STATE,Override value for mpll_state output" "0,1" newline bitfld.word 0x0 7. "BS_OUT_OVRD,Override enable for bs_out output" "0,1" newline bitfld.word 0x0 6. "BS_OUT,Override value for bs_out output" "0,1" newline bitfld.word 0x0 5. "RTUNE_ACK_OVRD,Override enable for rtune_ack output" "0,1" newline bitfld.word 0x0 4. "RTUNE_ACK,Override value for rtune_ack output" "0,1" newline bitfld.word 0x0 3. "RES_REQ_OUT_OVRD,Override enable for res_req_out output" "0,1" newline bitfld.word 0x0 2. "RES_REQ_OUT,Override value for res_req_out output" "0,1" newline bitfld.word 0x0 1. "RES_ACK_OUT_OVRD,Override enable for res_ack_out output" "0,1" newline bitfld.word 0x0 0. "RES_ACK_OUT,Override value for res_ack_out output" "0,1" rgroup.word 0x5C++0x1 line.word 0x0 "SUP_DIG_MPLL_ASIC_IN,Current values for incoming MPLL controls from ASIC" newline bitfld.word 0x0 15. "RESERVED_15_15,Reserved for Future use" "0,1" newline bitfld.word 0x0 14. "MPLL_REFSSC_CLK_EN,Value from ASIC for mpll_refssc_clk_en (RU - read-only volatile)" "0,1" newline bitfld.word 0x0 13. "MPLL_WORD_CLK_EN,Value from ASIC for mpll_word_clk_en (RU - read-only volatile)" "0,1" newline bitfld.word 0x0 12. "MPLL_DWORD_CLK_EN,Value from ASIC for mpll_dword_clk_en (RU - read-only volatile)" "0,1" newline bitfld.word 0x0 11. "MPLL_QWORD_CLK_EN,Value from ASIC for mpll_qword_clk_en (RU - read-only volatile)" "0,1" newline bitfld.word 0x0 10. "RES_ACK_IN,Value from ASIC for res_ack_in (RU - read-only volatile)" "0,1" newline bitfld.word 0x0 9. "RES_REQ_IN,Value from ASIC for res_req_in (RU - read-only volatile)" "0,1" newline bitfld.word 0x0 8. "RTUNE_REQ,Value from ASIC for rtune_req (RU - read-only volatile)" "0,1" newline hexmask.word.byte 0x0 1.--7. 1. "MPLL_MULTIPLIER,Value from ASIC for mpll_multiplier (RU - read-only volatile)" newline bitfld.word 0x0 0. "MPLL_EN,Value from ASIC for mpll_en (RU - read-only volatile)" "0,1" rgroup.word 0x60++0x1 line.word 0x0 "SUP_DIG_BS_ASIC_IN,Current values for incoming boundary scan controls from ASIC" newline bitfld.word 0x0 14.--15. "RESERVED_15_14,Reserved for Future use" "0,1,2,3" newline bitfld.word 0x0 11.--13. "TX_VBOOST_LVL,Value from ASIC for tx_vboost_lvl -- Not as bs_* signal but we're out of bits. (RU - read-only volatile)" "0,1,2,3,4,5,6,7" newline bitfld.word 0x0 10. "INVERT,Value from ASIC for bs_invert (RU - read-only volatile)" "0,1" newline bitfld.word 0x0 9. "INIT,Value from ASIC for bs_init (RU - read-only volatile)" "0,1" newline bitfld.word 0x0 8. "HIGHZ,Value from ASIC for bs_highz (RU - read-only volatile)" "0,1" newline bitfld.word 0x0 7. "CLAMP,Value from ASIC for bs_clamp (RU - read-only volatile)" "0,1" newline bitfld.word 0x0 6. "EXTEST_AC,Value from ASIC for bs_extest_ac (RU - read-only volatile)" "0,1" newline bitfld.word 0x0 5. "EXTEST,Value from ASIC for bs_extest (RU - read-only volatile)" "0,1" newline bitfld.word 0x0 4. "PRELOAD,Value from ASIC for bs_preload (RU - read-only volatile)" "0,1" newline bitfld.word 0x0 3. "UPDATE_DR,Value from ASIC for bs_update_dr (RU - read-only volatile)" "0,1" newline bitfld.word 0x0 2. "CAPTURE_DR,Value from ASIC for bs_capture_dr (RU - read-only volatile)" "0,1" newline bitfld.word 0x0 1. "SHIFT_DR,Value from ASIC for bs_shift_dr (RU - read-only volatile)" "0,1" newline bitfld.word 0x0 0. "IN,Value from ASIC for bs_in (RU - read-only volatile)" "0,1" rgroup.word 0x64++0x1 line.word 0x0 "SUP_DIG_LEVEL_ASIC_IN,Current values for incoming los/acjt level. MPLL half rate mode and vreg bypass from ASIC" newline bitfld.word 0x0 15. "RESERVED_15_15,Reserved for Future use" "0,1" newline bitfld.word 0x0 12.--14. "LOS_BIAS,Value from ASIC for los_bias (RU - read-only volatile)" "0,1,2,3,4,5,6,7" newline bitfld.word 0x0 11. "MPLL_HALF_RATE,Value from ASIC for mpll_half_rate (RU - read-only volatile)" "0,1" newline bitfld.word 0x0 10. "VREG_BYPASS,Value from ASIC for vreg_bypass (RU - read-only volatile)" "0,1" newline hexmask.word.byte 0x0 5.--9. 1. "ACJT_LEVEL,Value from ASIC for acjt_level (RU - read-only volatile)" newline hexmask.word.byte 0x0 0.--4. 1. "LOS_LEVEL,Value from ASIC for los_level (RU - read-only volatile)" rgroup.word 0x68++0x1 line.word 0x0 "SUP_DIG_SSC_ASIC_IN,Current values for incoming SSC controls from ASIC" newline bitfld.word 0x0 15. "SS_EN,Value from ASIC for ssc_en (RU - read-only volatile)" "0,1" newline bitfld.word 0x0 12.--14. "SSC_RANGE,Value from ASIC for ssc_range (RU - read-only volatile)" "0,1,2,3,4,5,6,7" newline hexmask.word 0x0 3.--11. 1. "SSC_REF_CLK_SEL,Value from ASIC for ssc_ref_clk_sel (RU - read-only volatile)" newline bitfld.word 0x0 0.--2. "FSEL,Value from ASIC for fsel (RU - read-only volatile)" "0,1,2,3,4,5,6,7" rgroup.word 0x6C++0x1 line.word 0x0 "SUP_DIG_SUP_ASIC_OUT,Current values for outgoing support block controls to ASIC" newline hexmask.word 0x0 5.--15. 1. "RESERVED_15_5,Reserved for Future use" newline bitfld.word 0x0 4. "MPLL_STATE,Value from PHY for mpll_state output (RU - read-only volatile)" "0,1" newline bitfld.word 0x0 3. "BS_OUT,Value from PHY for bs_out output (RU - read-only volatile)" "0,1" newline bitfld.word 0x0 2. "RTUNE_ACK,Value from PHY for rtune_ack output (RU - read-only volatile)" "0,1" newline bitfld.word 0x0 1. "RES_REQ_OUT,Value from PHY for res_req_out output (RU - read-only volatile)" "0,1" newline bitfld.word 0x0 0. "RES_ACK_OUT,Value from PHY for res_ack_out output (RU - read-only volatile)" "0,1" rgroup.word 0x70++0x1 line.word 0x0 "SUP_DIG_ATEOVRD_STATUS,USB3_SUP_DIG_ATEOVRD_STATUS" newline hexmask.word.byte 0x0 10.--15. 1. "RESERVED_15_10,Reserved for Future use" newline bitfld.word 0x0 8.--9. "DTB_OUT,Value from dtb_out bus. (RU - read-only volatile)" "0,1,2,3" newline bitfld.word 0x0 7. "REF_SSP_EN,Value from ASIC for ref_ssp_en. (RU - read-only volatile)" "0,1" newline bitfld.word 0x0 6. "REF_USE_PAD,Value from ASIC for ref_use_pad. (RU - read-only volatile)" "0,1" newline bitfld.word 0x0 5. "PHY_RESET_IN,Value from ASIC for phy_reset (RU - read-only volatile)" "0,1" newline bitfld.word 0x0 4. "REF_CLKDIV2_IN,Value from ASIC for ref_clkdiv2 (RU - read-only volatile)" "0,1" newline bitfld.word 0x0 3. "REF_USB2_EN_IN,Value from ASIC for ref_usb2_en (RU - read-only volatile)" "0,1" newline bitfld.word 0x0 2. "ATEOVRD_EN,When set values from ATEOVRD register are being sent to PHY (RU - read-only volatile)" "0,1" newline bitfld.word 0x0 1. "REF_CLKDIV2_OUT,Value from ATEOVRD for ref_clkdiv2 (RU - read-only volatile)" "0,1" newline bitfld.word 0x0 0. "REF_USB2_EN_OUT,Value from ATEOVRD for ref_usb2_en (RU - read-only volatile)" "0,1" group.word 0x74++0x1 line.word 0x0 "SUP_DIG_HSP_OVRD_IN,Override values for HSP" newline hexmask.word 0x0 4.--15. 1. "RESERVED_15_4,Reserved for Future use" newline bitfld.word 0x0 3. "HSP_PLL_OVRD,Override enable for HSP pll_pu signal" "0,1" newline bitfld.word 0x0 2. "HSP_PLL_PU,Override value for HSP pll_pu signal" "0,1" newline bitfld.word 0x0 1. "HSP_BIAS_OVRD,Override enable for HSP bias_pu signal" "0,1" newline bitfld.word 0x0 0. "HSP_BIAS_PU,Override value for HSP bias_pu signal" "0,1" rgroup.word 0x78++0x1 line.word 0x0 "SUP_DIG_HSP_ASIC_IN,Current values for incoming HSP & REF XO controls from ASIC" newline hexmask.word 0x0 4.--15. 1. "RESERVED_15_4,Reserved for Future use" newline bitfld.word 0x0 3. "REF_USE_XO,Value from ASIC for ref_use_xo (RU - read-only volatile)" "0,1" newline bitfld.word 0x0 2. "REF_XO_EN,Value from ASIC for ref_xo_en (RU - read-only volatile)" "0,1" newline bitfld.word 0x0 1. "HSP_PLL_PU,Value from ASIC for hsp_pll_pu (RU - read-only volatile)" "0,1" newline bitfld.word 0x0 0. "HSP_BIAS_PU,Value from ASIC for hsp_bias_pu (RU - read-only volatile)" "0,1" group.word 0x80++0x1 line.word 0x0 "SUP_DIG_SCOPE_ENABLES,Scope Counter configuration" newline hexmask.word 0x0 5.--15. 1. "RESERVED_15_5,Reserved for Future use" newline bitfld.word 0x0 3.--4. "LANE_SELECT,Scope Counter Input select" "0,1,2,3" newline bitfld.word 0x0 2. "MASK_SATURATION_MODE,Method of mask saturation. When 1 Saturate when the first mask_counter reaches sample_limit. When 0 Saturate when all mask_counters have reached sample_limit." "0,1" newline bitfld.word 0x0 1. "MASK_EN,Enable scope_mask input for tracking count values. Clears registers when deasserted." "0,1" newline bitfld.word 0x0 0. "XOR_EN,Use scope_xor input for count values." "0,1" group.word 0x84++0x1 line.word 0x0 "SUP_DIG_SCOPE_SAMPLES,Number of samples to count" newline hexmask.word 0x0 0.--15. 1. "SAMPLES,Number of Sample to count." rgroup.word 0x88++0x1 line.word 0x0 "SUP_DIG_SCOPE_COUNT,Results of scope counting" newline hexmask.word 0x0 0.--15. 1. "COUNT,A write to this register will start the counting process The value of FFFF indicates counting still in progress. Asserting MASK_EN will also start the counting if in MASK mode. (RU - read-only volatile)" group.word 0x8C++0x1 line.word 0x0 "SUP_DIG_SCOPE_CTL,Masked scope counting Start and Status" newline hexmask.word 0x0 2.--15. 1. "RESERVED_15_2,Reserved for Future use" newline bitfld.word 0x0 1. "MASK_START,A write to this register will start the counting process The value of FFFF indicates counting still in progress Write will trigger mask counting. (USER1 - read-write volatile)" "?,read-write volatile)" newline bitfld.word 0x0 0. "MASK_SATURATION,When assert mask registers have saturated. (USER1 - read-write volatile)" "?,read-write volatile)" repeat 8. (list 0x0 0x1 0xA 0xB 0x64 0x65 0x6E 0x6F )(list 0x0 0x4 0x8 0xC 0x10 0x14 0x18 0x1C ) group.word ($2+0x90)++0x1 line.word 0x0 "SUP_DIG_SCOPE_MASK_$1,Current count value for mask_000" newline hexmask.word 0x0 0.--15. 1. "MASK_VAL_000,Starting count value of mask register. (volatile and 2 reads needed to read value)" repeat.end group.word 0xC0++0x1 line.word 0x0 "SUP_ANA_MPLL_LOOP_CTL,MPLL loop control bits" newline hexmask.word.byte 0x0 8.--15. 1. "RESERVED_15_8,Reserved for Future use" newline hexmask.word.byte 0x0 4.--7. 1. "PROP_CNTRL,Charge pump proportional current setting" newline bitfld.word 0x0 2.--3. "INT_CNTRL,Charge pump integrating current setting" "0,1,2,3" newline bitfld.word 0x0 1. "GD,Measure MPLL local GD" "0,1" newline bitfld.word 0x0 0. "VMB,Measure MPLL Master Bias Voltage" "0,1" repeat 2. (list 0x1 0x2 )(list 0x0 0x4 ) group.word ($2+0xC4)++0x1 line.word 0x0 "SUP_ANA_MPLL_ATB_MEAS$1,ATB Select bits" newline hexmask.word.byte 0x0 8.--15. 1. "RESERVED_15_8,Reserved for Future use" newline bitfld.word 0x0 7. "VPSF,puts vpsf on atb_s_p" "0,1" newline bitfld.word 0x0 6. "VREF,puts vref from charge pump on atb_s_p" "0,1" newline bitfld.word 0x0 5. "VCNTRL,puts vcntrl on atb_s_m" "0,1" newline bitfld.word 0x0 4. "GD,puts gd on atb_s_m" "0,1" newline bitfld.word 0x0 3. "IVCO,puts VCO current/93 on atb_f_m" "0,1" newline bitfld.word 0x0 2. "VP,puts vpa on atb_s_m" "0,1" newline bitfld.word 0x0 1. "VP_CP,puts vp_cp on atb_s_p" "0,1" newline bitfld.word 0x0 0. "VREG_MPLL,puts vreg_mpll on atb_s_p" "0,1" repeat.end group.word 0xCC++0x1 line.word 0x0 "SUP_ANA_MPLL_OVRD,Local overrides" newline hexmask.word.byte 0x0 8.--15. 1. "RESERVED_15_8,Reserved for Future use" newline bitfld.word 0x0 7. "PWRON_LCL,local power_on value" "0,1" newline bitfld.word 0x0 6. "EN_PWRON_LCL,Enable local control of power_on" "0,1" newline bitfld.word 0x0 5. "GS_LCL,local gear_shift value" "0,1" newline bitfld.word 0x0 4. "EN_GS_LCL,Enable local control of gear_shift" "0,1" newline bitfld.word 0x0 3. "RST_LCL,local reset value" "0,1" newline bitfld.word 0x0 2. "EN_RST_LCL,enable local control of reset" "0,1" newline bitfld.word 0x0 1. "PMIX_CLK_SEL_LCL,local pmix_clk_sel value" "0,1" newline bitfld.word 0x0 0. "EN_PMIX_CLK_SEL_LCL,enable local control of pmix_clk_sel" "0,1" group.word 0xD0++0x1 line.word 0x0 "SUP_ANA_RTUNE_RTUNE_CTRL,RTUNE control bits" newline hexmask.word.byte 0x0 8.--15. 1. "RESERVED_15_8,Reserved for Future use" newline bitfld.word 0x0 7. "RT_PWRON_FRC_ON,When set forces RTUNE block to be on" "0,1" newline bitfld.word 0x0 6. "X4_FRC_OFF,When set do not multiply test current by 4" "0,1" newline bitfld.word 0x0 4.--5. "RT_DAC_MODE,Margin DAC mode control bits(00=powerdown 01=DAC drives atb_s_p/m directly 10=DAC drives atb_s_p/m to the RX in margining mode 11=illegal state)" "powerdown,DAC drives atb_s_p/m directly,?,?" newline bitfld.word 0x0 3. "RT_DAC_CHOP,Margin DAC chop control bit. ref to ssp analog engineering doc 8.5" "0,1" newline bitfld.word 0x0 2. "RT_ATB,RTUNE ATB mode control bit (1=RTUNE performs ADC on ATB input 0=not accessing ATB. refer to ssp analog engineering specification 8.1.4)" "not accessing ATB,RTUNE performs ADC on ATB input" newline bitfld.word 0x0 1. "RT_SEL_ATBP,RTUNE ATB sense input select bit (1=atb_s_p 0=atb_s_m)" "atb_s_m),atb_s_p" newline bitfld.word 0x0 0. "RT_SEL_ATBF,RTUNE ATB input select bit (1=atb_fm 0=atb_s_p/m)" "atb_s_p/m),atb_fm" group.word 0xD4++0x1 line.word 0x0 "SUP_ANA_ATB_SWITCHYARD_CTRL,ATB_SWITCHYARD control bits" newline hexmask.word.byte 0x0 8.--15. 1. "RESERVED_15_8,Reserved for Future use" newline bitfld.word 0x0 7. "ASM_GD,Connect gd to atb_s_m" "0,1" newline bitfld.word 0x0 6. "ASP_VP,Connect vp to atb_s_p" "0,1" newline bitfld.word 0x0 5. "ASP_VBG,Connect vbg to atb_s_p" "0,1" newline bitfld.word 0x0 4. "ASP_VPHREG,Connect vphreg to atb_s_m" "0,1" newline bitfld.word 0x0 3. "ATEST_AFM,drive ATEST from atb_f_m" "0,1" newline bitfld.word 0x0 2. "ATEST_AFP,drive ATEST from atb_f_p" "0,1" newline bitfld.word 0x0 1. "ATEST_ASM,Connet ATEST to atb_s_m" "0,1" newline bitfld.word 0x0 0. "ATEST_ASP,Connect ATEST to atb_s_p" "0,1" group.word 0xD8++0x1 line.word 0x0 "SUP_ANA_SSC_CLK_CNTRL,controls sscf reference clock rate" newline hexmask.word.byte 0x0 8.--15. 1. "RESERVED_15_8,Reserved for Future use" newline bitfld.word 0x0 7. "NC,Reserved" "0,1" newline hexmask.word.byte 0x0 0.--6. 1. "SSC_CLK_DIV125,set ssc reference clock to be 20MHz" group.word 0xDC++0x1 line.word 0x0 "SUP_ANA_HSP_CLK_DIG_CNTRL0,controls HSP phase clock. and resolution" newline hexmask.word.byte 0x0 8.--15. 1. "RESERVED_15_8,Reserved for Future use" newline bitfld.word 0x0 7. "NUM_OVERRIDE,Set the value to 1 to enable using values from creg bit 6 downto 0" "0,1" newline bitfld.word 0x0 4.--6. "GATE_PMIX_BITS,Set gate_pmix_bits to gate the corresponding MSB of the 7-bit PMIX phase select bits" "?,?,?,?,?,?,?,bit PMIX phase select bits" newline bitfld.word 0x0 3. "HALF_CLK_EN,Set to 1 for 1.25GHz updates to HSP PMIX. Set to 0 for 2.5GHz updates to PMIX." "0,1" newline bitfld.word 0x0 2. "UCLK_EN_N,Set to 1 to disable update clock. Set to 0 to enable update clock. When clock is enabled phase updates are allowed." "0,1" newline bitfld.word 0x0 1. "EN_HSPPMIX_VPMIX,Set to 1 to connect the regulated HSP PMIX supply to the atb_s_p bus" "0,1" newline bitfld.word 0x0 0. "EN_HSPPMIX_FRC_VPMIX,Set to 1 to force override of HSP PMIX regulator voltage to voltage on atb_s_m" "0,1" group.word 0xE0++0x1 line.word 0x0 "SUP_ANA_HSP_CLK_DIG_CNTRL1,Lower and Upper Phase Increment Values" newline hexmask.word.byte 0x0 8.--15. 1. "RESERVED_15_8,Reserved for Future use" newline hexmask.word.byte 0x0 4.--7. 1. "UPPER_INT,These bits are only used when num_override is set to 1. Upper integer for phase increments of 2.5 to 2.4 GHz conversion. This is the phase increment that is applied 6 times in every 25 for 1.25 GHz increments and 3 times in every 25 for 2.5GHz" newline hexmask.word.byte 0x0 0.--3. 1. "LOWER_INT,These bits are only used when num_override is set to 1. Lower integer for phase increments of 2.5 to 2.4 GHz conversion. This phase increment is applied 19 times in every 25 for 1.25 GHz increments and 22 times in every 25 for 2.5GHz." group.word 0x1000++0x1 line.word 0x0 "LANE0_DIG_TX_OVRD_IN_LO,Override values for incoming TX controls from ASIC" newline bitfld.word 0x0 15. "LANE_IF_WIDTH_OVRD,Override enable for lane interface width" "0,1" newline bitfld.word 0x0 14. "LANE_IF_WIDTH,Override value for lane interface width" "0,1" newline bitfld.word 0x0 13. "TX_DETECT_RX_REQ_OVRD,Override enable for tx_detect_rx_req" "0,1" newline bitfld.word 0x0 12. "TX_DETECT_RX_REQ,Override value for tx_detect_rx_req" "0,1" newline bitfld.word 0x0 11. "TX_BEACON_EN_OVRD,Override enable for tx_beacon_en" "0,1" newline bitfld.word 0x0 10. "TX_BEACON_EN,Override value for tx_beacon_en" "0,1" newline bitfld.word 0x0 9. "TX_CM_EN_OVRD,Override enable for tx_cm_en" "0,1" newline bitfld.word 0x0 8. "TX_CM_EN,Override value for tx_cm_en" "0,1" newline bitfld.word 0x0 7. "TX_EN_OVRD,Override enable for tx_en" "0,1" newline bitfld.word 0x0 6. "TX_EN,Override value for tx_en" "0,1" newline bitfld.word 0x0 5. "TX_DATA_EN_OVRD,Override enable for tx_data_en" "0,1" newline bitfld.word 0x0 4. "TX_DATA_EN,Override value for tx_data_en" "0,1" newline bitfld.word 0x0 3. "TX_INVERT_OVRD,Override enable for tx_invert" "0,1" newline bitfld.word 0x0 2. "TX_INVERT,Override value for tx_invert" "0,1" newline bitfld.word 0x0 1. "TX_LOOPBK_EN_OVRD,Override enable for loopbk_en" "0,1" newline bitfld.word 0x0 0. "LOOPBK_EN,Override value for loopbk_en" "0,1" group.word 0x1004++0x1 line.word 0x0 "LANE0_DIG_TX_OVRD_IN_HI,Override values for incoming TX controls from ASIC" newline hexmask.word.byte 0x0 10.--15. 1. "RESERVED_15_10,Reserved for Future use" newline bitfld.word 0x0 9. "TX_VBOOST_EN_OVRD,Override enable for tx_vboost_en" "0,1" newline bitfld.word 0x0 8. "TX_VBOOST_EN,Override value for tx_vboost_en" "0,1" newline bitfld.word 0x0 7. "TX_RESET_OVRD,Override enable for tx_reset" "0,1" newline bitfld.word 0x0 6. "TX_RESET,Override value for tx_reset" "0,1" newline bitfld.word 0x0 5. "TX_NYQUIST_DATA,Override incoming data to nyquist" "0,1" newline bitfld.word 0x0 4. "TX_CLK_OUT_EN_OVRD,Override enable for tx_clk_out_en." "0,1" newline bitfld.word 0x0 3. "TX_CLK_OUT_EN,Override incomming tx_clk_out_en." "0,1" newline bitfld.word 0x0 2. "TX_RATE_OVRD,Override enable for tx_rate." "0,1" newline bitfld.word 0x0 0.--1. "TX_RATE,Override incomming tx lane rate." "0,1,2,3" group.word 0x1008++0x1 line.word 0x0 "LANE0_DIG_TX_OVRD_DRV_LO,Override values for incoming TX drive controls from ASIC" newline rbitfld.word 0x0 15. "RESERVED_15_15,Reserved for Future use" "0,1" newline bitfld.word 0x0 14. "EN,Enable override values for all inputs controlled by this register" "0,1" newline hexmask.word.byte 0x0 7.--13. 1. "PREEMPH,Override value for transmit preemphasis." newline hexmask.word.byte 0x0 0.--6. 1. "AMPLITUDE,Override value for transmit amplitude." group.word 0x100C++0x1 line.word 0x0 "LANE0_DIG_TX_OVRD_DRV_HI,Override values for incoming TX drive controls from ASIC" newline hexmask.word 0x0 6.--15. 1. "RESERVED_15_6,Reserved for Future use" newline bitfld.word 0x0 5. "EN,Enable override values for all inputs controlled by this register" "0,1" newline hexmask.word.byte 0x0 0.--4. 1. "TERM_OFFSET,Override value for tx_term_offset (tx_ana_vcmref_boost)" group.word 0x1010++0x1 line.word 0x0 "LANE0_DIG_TX_OVRD_OUT,Override values for outgoing TX controls to ASIC" newline hexmask.word.byte 0x0 8.--15. 1. "RESERVED_15_8,Reserved for Future use" newline bitfld.word 0x0 7. "TX_STATE_OVRD,Override enable for tx_state" "0,1" newline bitfld.word 0x0 6. "TX_STATE,Override value for tx_state" "0,1" newline bitfld.word 0x0 5. "TX_CM_STATE_OVRD,Override enable for tx_cm_state" "0,1" newline bitfld.word 0x0 4. "TX_CM_STATE,Override value for tx_cm_state" "0,1" newline bitfld.word 0x0 3. "TX_DETECT_RX_ACK_OVRD,Override enable for tx_detect_rx_ack" "0,1" newline bitfld.word 0x0 2. "TX_DETECT_RX_ACK,Override value for tx_detect_rx_ack" "0,1" newline bitfld.word 0x0 1. "DETECT_RX_RES_OVRD,Override enable for tx_detect_rx_res" "0,1" newline bitfld.word 0x0 0. "DETECT_RX_RES,Override value for tx_detect_rx_res" "0,1" group.word 0x1014++0x1 line.word 0x0 "LANE0_DIG_RX_OVRD_IN_LO,Override values for incoming RX controls from ASIC" newline rbitfld.word 0x0 14.--15. "RESERVED_15_14,Reserved for Future use" "0,1,2,3" newline bitfld.word 0x0 13. "RX_LOS_EN_OVRD,Override enable for rx_los_en" "0,1" newline bitfld.word 0x0 12. "RX_LOS_EN,Override value for rx_los_en" "0,1" newline bitfld.word 0x0 11. "RX_TERM_EN_OVRD,Override enable for rx_term_en" "0,1" newline bitfld.word 0x0 10. "RX_TERM_EN,Override value for rx_term_en" "0,1" newline bitfld.word 0x0 9. "RX_BIT_SHIFT_OVRD,Override enable for rx_bit_shift" "0,1" newline bitfld.word 0x0 8. "RX_BIT_SHIFT,Override value for rx_bit_shift" "0,1" newline bitfld.word 0x0 7. "RX_ALIGN_EN_OVRD,Override enable for rx_align_en" "0,1" newline bitfld.word 0x0 6. "RX_ALIGN_EN,Override value for rx_align_en" "0,1" newline bitfld.word 0x0 5. "RX_DATA_EN_OVRD,Override enable for rx_data_en" "0,1" newline bitfld.word 0x0 4. "RX_DATA_EN,Override value for rx_data_en" "0,1" newline bitfld.word 0x0 3. "RX_PLL_EN_OVRD,Override enable for rx_pll_en" "0,1" newline bitfld.word 0x0 2. "RX_PLL_EN,Override value for rx_pll_en" "0,1" newline bitfld.word 0x0 1. "RX_INVERT_OVRD,Override enable for rx_invert" "0,1" newline bitfld.word 0x0 0. "RX_INVERT,Override value for rx_invert" "0,1" group.word 0x1018++0x1 line.word 0x0 "LANE0_DIG_RX_OVRD_IN_HI,Override values for incoming RX controls from ASIC" newline rbitfld.word 0x0 14.--15. "RESERVED_15_14,Reserved for Future use" "0,1,2,3" newline bitfld.word 0x0 13. "RX_RESET_OVRD,Override enable for rx_reset" "0,1" newline bitfld.word 0x0 12. "RX_RESET,Override value for rx_reset" "0,1" newline bitfld.word 0x0 11. "RX_EQ_OVRD,Override enable for rx_eq" "0,1" newline bitfld.word 0x0 8.--10. "RX_EQ,Override value for rx_eq" "0,1,2,3,4,5,6,7" newline bitfld.word 0x0 7. "RX_EQ_EN_OVRD,Override enable for rx_eq_en" "0,1" newline bitfld.word 0x0 6. "RX_EQ_EN,Override value for rx_eq_en" "0,1" newline bitfld.word 0x0 5. "RX_LOS_FILTER_OVRD,Override enable for rx_los_filter" "0,1" newline bitfld.word 0x0 3.--4. "RX_LOS_FILTER,Override value for rx_los_filter" "0,1,2,3" newline bitfld.word 0x0 2. "RX_RATE_OVRD,Override enable for rx_rate" "0,1" newline bitfld.word 0x0 0.--1. "RX_RATE,Override value for rx_rate" "0,1,2,3" group.word 0x101C++0x1 line.word 0x0 "LANE0_DIG_RX_OVRD_OUT,Override values for outgoing RX controls to ASIC" newline hexmask.word 0x0 7.--15. 1. "RESERVED_15_7,Reserved for Future use" newline bitfld.word 0x0 6. "ZERO_DATA,Override data output to all zeros" "0,1" newline bitfld.word 0x0 5. "LOS_OVRD,Override value for rx_los" "0,1" newline bitfld.word 0x0 4. "LOS,Override value for rx_los" "0,1" newline bitfld.word 0x0 3. "PLL_STATE_OVRD,Override enable for rx_pll_state" "0,1" newline bitfld.word 0x0 2. "PLL_STATE,Override value for rx_pll_state" "0,1" newline bitfld.word 0x0 1. "VALID_OVRD,Override enable for rx_valid" "0,1" newline bitfld.word 0x0 0. "VALID,Override value for rx_valid" "0,1" rgroup.word 0x1020++0x1 line.word 0x0 "LANE0_DIG_TX_ASIC_IN,Current values for incoming TX controls from ASIC" newline bitfld.word 0x0 14.--15. "RESERVED_15_14,Reserved for Future use" "0,1,2,3" newline bitfld.word 0x0 13. "LANE_IF_WIDTH,Value from ASIC for lane_if_width (RU - read-only volatile)" "0,1" newline bitfld.word 0x0 12. "DATA_EN_S,Value from ASIC for tx_data_en_s (RU - read-only volatile)" "0,1" newline bitfld.word 0x0 11. "TX_VBOOST_EN,Value from ASIC for tx_vboost_en (RU - read-only volatile)" "0,1" newline bitfld.word 0x0 10. "TX_CLK_OUT_EN,Value from ASIC for tx_clk_out_en (RU - read-only volatile)" "0,1" newline bitfld.word 0x0 9. "DETECT_RX_REQ,Value from ASIC for tx_detect_rx_req (RU - read-only volatile)" "0,1" newline bitfld.word 0x0 8. "BEACON_EN,Value from ASIC for tx_beacon_en (RU - read-only volatile)" "0,1" newline bitfld.word 0x0 7. "CM_EN,Value from ASIC for tx_cm_en (RU - read-only volatile)" "0,1" newline bitfld.word 0x0 6. "TX_EN,Value from ASIC for tx_en (RU - read-only volatile)" "0,1" newline bitfld.word 0x0 5. "DATA_EN,Value from ASIC for tx_data_en (RU - read-only volatile)" "0,1" newline bitfld.word 0x0 4. "TX_RESET,Value from ASIC for tx_reset (RU - read-only volatile)" "0,1" newline bitfld.word 0x0 3. "INVERT,Value from ASIC for tx_invert (RU - read-only volatile)" "0,1" newline bitfld.word 0x0 2. "LOOPBK_EN,Value from ASIC for loopbk_en (RU - read-only volatile)" "0,1" newline bitfld.word 0x0 0.--1. "TX_RATE,Value from ASIC for tx_rate (RU - read-only volatile)" "0,1,2,3" rgroup.word 0x1024++0x1 line.word 0x0 "LANE0_DIG_TX_ASIC_DRV_LO,Current values for incoming TX level controls from ASIC" newline bitfld.word 0x0 14.--15. "RESERVED_15_14,Reserved for Future use" "0,1,2,3" newline hexmask.word.byte 0x0 7.--13. 1. "PREEMPH,Value from ASIC for tx_preemph (RU - read-only volatile)" newline hexmask.word.byte 0x0 0.--6. 1. "AMPLITUDE,Value from ASIC for tx_amplitude (RU - read-only volatile)" rgroup.word 0x1028++0x1 line.word 0x0 "LANE0_DIG_TX_ASIC_DRV_HI,Current values for incoming TX level controls from ASIC" newline hexmask.word 0x0 5.--15. 1. "RESERVED_15_5,Reserved for Future use" newline hexmask.word.byte 0x0 0.--4. 1. "TERM_OFFSET,Value from ASIC for tx_term_offset (RU - read-only volatile)" rgroup.word 0x102C++0x1 line.word 0x0 "LANE0_DIG_TX_ASIC_OUT,Current values for outgoing TX status controls from PHY" newline hexmask.word 0x0 5.--15. 1. "RESERVED_15_5,Reserved for Future use" newline bitfld.word 0x0 4. "STATE,Value from PHY for tx_state (RU - read-only volatile)" "0,1" newline bitfld.word 0x0 3. "CM_STATE,Value from PHY for tx_cm_state (RU - read-only volatile)" "0,1" newline bitfld.word 0x0 2. "DETECT_RX_ACK,Value from PHY for tx_detect_rx_ack (RU - read-only volatile)" "0,1" newline bitfld.word 0x0 1. "RESERVED,Always returns 0 (RU - read-only volatile)" "0,1" newline bitfld.word 0x0 0. "DETECT_RX_RES,Value from PHY for tx_detect_rx_res (RU - read-only volatile)" "0,1" rgroup.word 0x1030++0x1 line.word 0x0 "LANE0_DIG_RX_ASIC_IN,Current values for incoming RX controls from ASIC" newline bitfld.word 0x0 15. "RX_EQ_EN,Value from ASIC for rx_eq_en (RU - read-only volatile)" "0,1" newline bitfld.word 0x0 12.--14. "RX_EQ,Value from ASIC for rx_eq (RU - read-only volatile)" "0,1,2,3,4,5,6,7" newline bitfld.word 0x0 10.--11. "LOS_FILTER,Value from ASIC for rx_los_filter (RU - read-only volatile)" "0,1,2,3" newline bitfld.word 0x0 9. "LOS_EN,Value from ASIC for rx_los_en (RU - read-only volatile)" "0,1" newline bitfld.word 0x0 8. "TERM_EN,Value from ASIC for rx_term_en (RU - read-only volatile)" "0,1" newline bitfld.word 0x0 7. "CLK_SHIFT,Value from ASIC for rx_bit_shift (RU - read-only volatile)" "0,1" newline bitfld.word 0x0 6. "ALIGN_EN,Value from ASIC for rx_align_en (RU - read-only volatile)" "0,1" newline bitfld.word 0x0 5. "DATA_EN,Value from ASIC for rx_data_en (RU - read-only volatile)" "0,1" newline bitfld.word 0x0 4. "PLL_EN,Value from ASIC for rx_pll_en (RU - read-only volatile)" "0,1" newline bitfld.word 0x0 3. "RX_RESET,Value from ASIC for rx_reset (RU - read-only volatile)" "0,1" newline bitfld.word 0x0 2. "INVERT,Value from ASIC for rx_invert (RU - read-only volatile)" "0,1" newline bitfld.word 0x0 0.--1. "RX_RATE,Value from ASIC for rx_rate (RU - read-only volatile)" "0,1,2,3" rgroup.word 0x1034++0x1 line.word 0x0 "LANE0_DIG_RX_ASIC_OUT,Current values for outgoing RX status controls from PHY" newline hexmask.word 0x0 3.--15. 1. "RESERVED_15_3,Reserved for Future use" newline bitfld.word 0x0 2. "LOS,Value from PHY for rx_los (RU - read-only volatile)" "0,1" newline bitfld.word 0x0 1. "PLL_STATE,Value from PHY for rx_pll_state (RU - read-only volatile)" "0,1" newline bitfld.word 0x0 0. "VALID,Value from PHY for rx_valid (RU - read-only volatile)" "0,1" group.word 0x1040++0x1 line.word 0x0 "LANE0_DIG_TX_DEBUG,Transmit debug controls" newline rbitfld.word 0x0 13.--15. "RESERVED_15_13,Reserved for Future use" "0,1,2,3,4,5,6,7" newline bitfld.word 0x0 12. "KEEP_TX_REFGEN,Keep TX voltage regulator ON until TX clocks are OFF" "0,1" newline hexmask.word.byte 0x0 4.--11. 1. "RXDET_MEAS_TIME,Time to wait for rxdet measurement (* 4/2/1 refclk cycles based on multiplier)" newline bitfld.word 0x0 3. "DETECT_RX_ALWAYS,Always signal 1 for rx_detect ignoring analog" "0,1" newline bitfld.word 0x0 0.--2. "DTB_SEL,Selects data to drive on DTB 0 - disabled 1 - mag_update/sub signals 2 - mag_high/add signals 3 - clock aligner early/shift signals 4 - analog/asic clocks 5 - tx_state counter/lbert strobe 6 - noclk_ref_rst/dig_rst 7 -.." "disabled,mag_update/sub signals,mag_high/add signals,clock aligner early/shift signals,analog/asic clocks,tx_state counter/lbert strobe,noclk_ref_rst/dig_rst,tx_ana_rxdetp_high/tx_ana_rxdetm_high" group.word 0x1044++0x1 line.word 0x0 "LANE0_DIG_TX_CM_WAIT_TIME_OVRD,USB3_LANE0_DIG_TX_CM_WAIT_TIME_OVRD" newline hexmask.word.byte 0x0 11.--15. 1. "RESERVED_15_11,Reserved for Future use" newline bitfld.word 0x0 10. "CM_TIME_OVRD_EN,Override enable for common mode charging wait time." "0,1" newline hexmask.word 0x0 0.--9. 1. "CM_TIME_OVRD,Time to wait in ref clock cycles for LFPS common mode charging (This value x32 is used for VCMHOLD charging method)" rgroup.word 0x1048++0x1 line.word 0x0 "LANE0_DIG_TX_VMD_FSM_TX_VCM_0,Calculated values for N_USE and N_TRISTATE. Also TX ANA configuration shift register output." newline bitfld.word 0x0 15. "SHIFT_OUT,Current value from TX_ANAs configuration shift register. (RU - read-only volatile)" "0,1" newline bitfld.word 0x0 14. "DONE,Configuration is done (RU - read-only volatile)" "0,1" newline hexmask.word.byte 0x0 7.--13. 1. "N_USE,Value from VMD for legs to use. (RU - read-only volatile)" newline hexmask.word.byte 0x0 0.--6. 1. "N_TRISTATE,Value from VMD for number of tristate legs. (RU - read-only volatile)" rgroup.word 0x104C++0x1 line.word 0x0 "LANE0_DIG_TX_VMD_FSM_TX_VCM_1,Calculated values for N_FIXED and N_TRAILER." newline bitfld.word 0x0 15. "FIXED_DONE,N_FIXED Multiplication has completed. (RU - read-only volatile)" "0,1" newline bitfld.word 0x0 14. "TRA_DONE,N_TRAILER Multiplication has completed. (RU - read-only volatile)" "0,1" newline hexmask.word.byte 0x0 7.--13. 1. "N_FIXED,Value from VMD for number of fixed driver legs. (RU - read-only volatile)" newline hexmask.word.byte 0x0 0.--6. 1. "N_TRAILER,Value from VMD for number of trailer legs. (RU - read-only volatile)" group.word 0x1050++0x1 line.word 0x0 "LANE0_DIG_TX_VMD_FSM_TX_VCM_DEBUG_IN,Access the TX_ANA VMD Control Shift Register" newline hexmask.word 0x0 4.--15. 1. "RESERVED_15_4,Reserved for Future use" newline bitfld.word 0x0 3. "CONFIG_OVRD,Override the Voltage Mode Driver Configuration FSM and access the shift chain directly. (volatile and 2 reads needed to read value)" "0,1" newline bitfld.word 0x0 2. "CONFIG_LOAD,Override value for the Voltage Mode Driver Configuration FSM's config load. (volatile and 2 reads needed to read value)" "0,1" newline bitfld.word 0x0 1. "CONFIG_CLK,Override value for the Voltage Mode Driver Configuration FSM's config clk. (volatile and 2 reads needed to read value)" "0,1" newline bitfld.word 0x0 0. "CONFIG_DATA,Override value for the Voltage Mode Driver Configuration FSM's config data. (volatile and 2 reads needed to read value)" "0,1" group.word 0x1054++0x1 line.word 0x0 "LANE0_DIG_TX_LBERT_CTL,Pattern Generator controls" newline rbitfld.word 0x0 15. "RESERVED_15_15,Reserved for Future use" "0,1" newline hexmask.word 0x0 5.--14. 1. "PAT0,10 bit pattern for modes using PAT0 (5-7). Ignored for other MODEs." newline bitfld.word 0x0 4. "TRIGGER_ERR,Single shot inversion the LSB of the current symbol. Any write of a 1 to this bit will insert an error. Maintain mode and pattern from setup." "0,1" newline hexmask.word.byte 0x0 0.--3. 1. "MODE,Pattern to generate When changing modes you must change to disabled first 0 - disabled 1 - lfsr31. X^31 + X^28 + 1 2 - lfsr23. X^23 + X^18 + 1 3 - lfsr15. X^15 + X^14 + 1 4 - lfsr7. X^7 + X^6 + 1 5 - fixed word (PAT0) 6 - DC balanced word (PAT0.." group.word 0x1058++0x1 line.word 0x0 "LANE0_DIG_RX_LBERT_CTL,Pattern Matcher controls" newline hexmask.word 0x0 5.--15. 1. "RESERVED_15_5,Reserved for Future use" newline bitfld.word 0x0 4. "SYNC,Synchronize pattern matcher with incoming data A write of a one to this bit will reset the error counter and start a synchronization of the PM. There is no need to write this back to zero to run normally." "0,1" newline hexmask.word.byte 0x0 0.--3. 1. "MODE,Pattern to match When changing modes you must change to disabled first 0 - disabled 1 - lfsr31: X^31 + X^28 + 1 2 - lfsr23: X^23 + X^18 + 1 3 - lfsr15: X^15 + X^14 + 1 4 - lfsr7 : X^7 + X^6 + 1 5 - d[n] = d[n-10] 6 - d[n] = !d[n-10] 7 - d[n] =.." group.word 0x105C++0x1 line.word 0x0 "LANE0_DIG_RX_LBERT_ERR,Pattern match error counter" newline bitfld.word 0x0 15. "OV14,A read of this register or a sync of the Pattern Matcher resets the error count. If all bits of this register are 1 the error counter has saturated. If the status If active multiply COUNT by 128. If OV14=1 and COUNT=2^15-1 signals overflow of.." "0,1" newline hexmask.word 0x0 0.--14. 1. "COUNT,Current error count If OV14 field is active then multiply count by 128 to get the actual count. (volatile and 2 reads needed to read value)" group.word 0x1060++0x1 line.word 0x0 "LANE0_DIG_RX_SCOPE_CTL,Control bits for per-transciever scope portion" newline rbitfld.word 0x0 14.--15. "RESERVED_15_14,Reserved for Future use" "0,1,2,3" newline bitfld.word 0x0 12.--13. "RX_VALID_CTL,When to Start Sampling control based on rx_valid. 0 = Ignore rx_valid. 1 = Heed rx_valid. 2 = Wait for rising_edge on rx_valid." "Ignore rx_valid,Heed rx_valid,Wait for rising_edge on rx_valid,?" newline hexmask.word 0x0 3.--11. 1. "DELAY,number of cycles to skip between samples" newline bitfld.word 0x0 0.--2. "MODE,sampling mode of counters NOTE: WORD is 20 bits. 0 = off 1 = sample data every WORD*(1+DELAY) bits from the digital recovered path. 2 = sample data every WORD*(1+DELAY) + 1 bits from the digital recovered path. 3 = sample data every WORD*(1+DELAY) +.." "off,sample data every WORD*,sample data every WORD*,sample data every WORD*,sample data every WORD*,?,?,?" group.word 0x1064++0x1 line.word 0x0 "LANE0_DIG_RX_SCOPE_PHASE,Scope sampling phase." newline rbitfld.word 0x0 15. "RESERVED_15_15,Reserved for Future use" "0,1" newline hexmask.word.byte 0x0 10.--14. 1. "BASE,which bit to sample when MODE = 1 or 4" newline bitfld.word 0x0 8.--9. "SCOPE_DELAY,How many clocks to delay the analog scope_data." "0,1,2,3" newline bitfld.word 0x0 7. "SCOPE_SEL,Select Sampling Mode. 0 - Before AFE Sampling 1 - After AFE Sampling" "Before AFE Sampling,After AFE Sampling" newline bitfld.word 0x0 6. "UPDATE,Update Sampling phase. Write a 1." "0,1" newline hexmask.word.byte 0x0 0.--5. 1. "SAMPLE_PHASE,Sampling Phase" group.word 0x1068++0x1 line.word 0x0 "LANE0_DIG_RX_DPLL_FREQ,Current frequency integrator value." newline rbitfld.word 0x0 13.--15. "RESERVED_15_13,Reserved for Future use" "0,1,2,3,4,5,6,7" newline hexmask.word 0x0 1.--12. 1. "VAL,Freq is 1.526*VAL ppm from the reference When mpll_slow is set the ppm is half the eqn above (volatile and 2 reads needed to read value)" newline bitfld.word 0x0 0. "DTHR,Bits below the useful resolution (volatile and 2 reads needed to read value)" "0,1" group.word 0x106C++0x1 line.word 0x0 "LANE0_DIG_RX_CDR_CTL,Control bits for receiver in recovered domain" newline hexmask.word.byte 0x0 12.--15. 1. "DTB_SEL,select to drive various signals onto the dtb 0 - disabled 1 - pll_ana_rst pll_count from rx_pwr_ctl 2 - com_good_high/low from aligner 3 - com_bad_high/low from aligner 4 - shift_in_prog ana_odd_data from aligner 5 - low bits of XAUI align FSM.." newline bitfld.word 0x0 11. "ALWAYS_REALIGN,realign on any misaligned comma" "0,1" newline bitfld.word 0x0 10. "FAST_START,decrease startup steps by 50%" "0,1" newline bitfld.word 0x0 8.--9. "FRUG_VALUE,override value for FRUG" "0,1,2,3" newline bitfld.word 0x0 6.--7. "PHUG_VALUE,override value for PHUG" "0,1,2,3" newline bitfld.word 0x0 5. "OVRD_DPLL_GAIN,Override PHUG and FRUG values" "0,1" newline bitfld.word 0x0 4. "PHDET_POL,Reverse polarity of phase error" "0,1" newline bitfld.word 0x0 2.--3. "PHDET_EDGE,Edges to use for phase detection. 11 - Use both edges 10 - Use rising edges only 01 - Use falling edges only 00 - Ignore all edges" "Ignore all edges,Use falling edges only,?,?" newline bitfld.word 0x0 0.--1. "PHDET_EN,Enable phase detecter. top bit is odd slicers bottom is even" "0,1,2,3" rgroup.word 0x1070++0x1 line.word 0x0 "LANE0_DIG_RX_CDR_CDR_FSM_DEBUG,Current values for CDR and Adaptation FSM." newline bitfld.word 0x0 13.--15. "ADAP_RX_EQ,Equalization setting from adaptation FSM. (RU - read-only volatile)" "0,1,2,3,4,5,6,7" newline bitfld.word 0x0 10.--12. "RX_EQ_CTR,Initial centre point from equalization FSM. (RU - read-only volatile)" "0,1,2,3,4,5,6,7" newline bitfld.word 0x0 7.--9. "RX_ANA_EQ,Equalization setting to Analog. (RU - read-only volatile)" "0,1,2,3,4,5,6,7" newline bitfld.word 0x0 6. "ADAP_RX_VALID,Adaptation has completed and locked. (RU - read-only volatile)" "0,1" newline bitfld.word 0x0 5. "CDR_EN_ADAP,Adapatation loop is enabling the CDR. (RU - read-only volatile)" "0,1" newline bitfld.word 0x0 4. "CDR_EN_EQ,Equalization loop is enabling the CDR. (RU - read-only volatile)" "0,1" newline bitfld.word 0x0 3. "ALIGNED,Datapath is bit-aligned. (RU - read-only volatile)" "0,1" newline bitfld.word 0x0 2. "CDR_RX_VALID,CDR has locked to incoming data stream. (RU - read-only volatile)" "0,1" newline bitfld.word 0x0 1. "CDR_TIMEOUT,CDR has not locked to datastream and has timed-out. (RU - read-only volatile)" "0,1" newline bitfld.word 0x0 0. "CDR_EN,CDR has been enabled. (RU - read-only volatile)" "0,1" group.word 0x1074++0x1 line.word 0x0 "LANE0_DIG_RX_CDR_LOCK_VEC_OVRD,Control bits for receiver in recovered domain" newline hexmask.word.byte 0x0 11.--15. 1. "ADAP_CTR_LEVEL,Ammount of earlies that increment the adaptation counter (times 32 Default is 512). (volatile and 2 reads needed to read value)" newline bitfld.word 0x0 10. "ADAP_POLARITY,If asserted invert default adaptation adjustment for equalization. IF early decrease equalization. Normal mode is to decrease. (volatile and 2 reads needed to read value)" "0,1" newline bitfld.word 0x0 9. "LOCK_VECTOR_OVRD,Override enable for the rx_eq outputs. (volatile and 2 reads needed to read value)" "0,1" newline bitfld.word 0x0 8. "LOCK_VECTOR_EN,Override value for the locked_vector output completion. (volatile and 2 reads needed to read value)" "0,1" newline hexmask.word.byte 0x0 0.--7. 1. "LOCK_VECTOR,Override value for the locked_vector. (volatile and 2 reads needed to read value)" rgroup.word 0x1078++0x1 line.word 0x0 "LANE0_DIG_RX_CDR_LOCK_VEC,Current values for the locked vector.." newline hexmask.word.byte 0x0 12.--15. 1. "RESERVED_15_12,Reserved for Future use" newline bitfld.word 0x0 9.--11. "EQ_RX_EQ,Equalization setting from the Equalization Loop. (RU - read-only volatile)" "0,1,2,3,4,5,6,7" newline bitfld.word 0x0 8. "EQ_LOCKED_VECTOR_EN,Equalization locked vector has been filled. (RU - read-only volatile)" "0,1" newline hexmask.word.byte 0x0 0.--7. 1. "EQ_LOCKED_VECTOR,Results of equalization loop. (RU - read-only volatile)" rgroup.word 0x107C++0x1 line.word 0x0 "LANE0_DIG_RX_CDR_ADAP_FSM,Observation of adaptation FSM register." newline hexmask.word.byte 0x0 11.--15. 1. "MSTR_CTR,Master count register. (RU - read-only volatile)" newline hexmask.word.byte 0x0 7.--10. 1. "LOOP_CTR,Loop count register. (RU - read-only volatile)" newline hexmask.word.byte 0x0 3.--6. 1. "ADAP_CTR,Adaptation count register. (RU - read-only volatile)" newline bitfld.word 0x0 0.--2. "ADAP_STATE,Adaptation State. NOTE: ADAP_RESET = 3'b000 ADAP_LOCK = 3'b001 ADAP_SUFF = 3'b010 ADAP_LOOP = 3'b011 ADAP_MSTR = 3'b100 ADAP_DONE = 3'b101 (RU - read-only volatile)" "0,1,2,3,4,5,6,7" group.word 0x1080++0x1 line.word 0x0 "LANE0_ANA_RX_ATB0,ATB Control Register" newline hexmask.word.byte 0x0 8.--15. 1. "RESERVED_15_8,Reserved for Future use" newline bitfld.word 0x0 7. "EN_ATB,Enable ATB sensing and forcing on internal RX nodes" "0,1" newline bitfld.word 0x0 6. "EN_MARG,Enable margining mode in receiver; it puts EQ common mode output on atb_f_m" "0,1" newline bitfld.word 0x0 5. "EN_ATB_RM_F,Enable atb_f_p on negative-side termination resistor" "0,1" newline bitfld.word 0x0 4. "EN_ATB_RM_S,Enable atb_s_m on negative-side termination resistor" "0,1" newline bitfld.word 0x0 3. "EN_ATB_RP_F,Enable atb_f_p on positive-side termination resistor" "0,1" newline bitfld.word 0x0 2. "EN_ATB_RP_S,Enable atb_s_p on positive-side termination resistor" "0,1" newline bitfld.word 0x0 1. "EN_ATB_VOS,Put rxafe filtered outputs vo_p on atb_s_p and vo_m on atb_s_m" "0,1" newline bitfld.word 0x0 0. "EN_ATB_VOFF,Put rxafe voff_p on atb_s_p and voff_m on atb_s_m" "0,1" group.word 0x1084++0x1 line.word 0x0 "LANE0_ANA_RX_ATB1,ATB and Misc Control Register" newline hexmask.word.byte 0x0 8.--15. 1. "RESERVED_15_8,Reserved for Future use" newline bitfld.word 0x0 6.--7. "RX_DCC_IQ_OFFSET_H_4_3,Code which helps to manually tune reference voltage (r-string dac) for IQ opamp and correct input offset (rx_dcc_iq_offset_h_4_3 bit)" "0,1,2,3" newline bitfld.word 0x0 5. "EN_ATB_VLOS,Enable sensing of LOS reference voltage on atb_s_p" "0,1" newline bitfld.word 0x0 4. "EN_ATB_VRF,Enable sensing of vref_rx (RX Bias B.G. Voltage) on atb_s_p" "0,1" newline bitfld.word 0x0 3. "MEAS_GD,Enable sensing of local gd in RX; ties gd to atb_s_m" "0,1" newline bitfld.word 0x0 2. "MEAS_VP,Enable sensing of local vp in RX; ties vp to atb_s_p" "0,1" newline bitfld.word 0x0 0.--1. "RX_DCC_IQ_OFFSET_H_2_1,Code which helps to manually tune reference voltage (r-string dac) for IQ opamp and correct input offset (rx_dcc_iq_offset_h_2_1 bit)" "0,1,2,3" group.word 0x1088++0x1 line.word 0x0 "LANE0_ANA_RX_ENPWR0,RX State Control Register" newline hexmask.word.byte 0x0 8.--15. 1. "RESERVED_15_8,Reserved for Future use" newline bitfld.word 0x0 7. "CTL_RXPWRON,MUX select for AFE en to select between CTL_RXPWRON=0 rx_afe_en (External signal) or CTL_RXPWRON=1 LCL_RXPWRON" "0,1" newline bitfld.word 0x0 6. "LCL_RXPWRON,Enable/Disable RX AFE .This bit is only selected when CTL_RXPWRON = 1" "0,1" newline bitfld.word 0x0 5. "CTL_EN_LOS,MUX select for LOS en to select between CTL_EN_LOS=0 rx_los_en (External signal) or CTL_EN_LOS=1 LCL_EN_LOS" "0,1" newline bitfld.word 0x0 4. "LCL_EN_LOS,Enable/Disable LOS.This bit is only selected when CTL_EN_LOS = 1" "0,1" newline bitfld.word 0x0 3. "CTL_RXCK,MUX select for RX Clock en to select between CTL_RXCK=0 rx_clock_en (External signal) or CTL_RXCK=1 LCL_RXCK." "0,1" newline bitfld.word 0x0 2. "LCL_RXCK,Enable/Disable en_rx_clock (RX clock enable).This bit is only selected when CTL_RXCK = 1" "0,1" newline bitfld.word 0x0 1. "CTL_ACJT,MUX select for ACJTAG to select between CTL_ACJTG=0 rx_acjtg_en (External signal) or CTL_ACJTG=1 LCL_ACJT." "0,1" newline bitfld.word 0x0 0. "LCL_ACJT,Enable/Disable acjtag block This bit is only selected when CTL_ACJTG = 1" "0,1" group.word 0x108C++0x1 line.word 0x0 "LANE0_ANA_RX_PMIX_PHASE,Phase select Value" newline hexmask.word.byte 0x0 8.--15. 1. "RESERVED_15_8,Reserved for Future use" newline hexmask.word.byte 0x0 0.--7. 1. "PHASE,Write to bits 8 to 1 of the phase select register in the phase mixer through the CDR (USER2 volatile - read-write volatile and custom)" group.word 0x1090++0x1 line.word 0x0 "LANE0_ANA_RX_ENPWR1,Additional RX State Control Register" newline hexmask.word.byte 0x0 8.--15. 1. "RESERVED_15_8,Reserved for Future use" newline bitfld.word 0x0 7. "CTL_PHASE_REG_RST,MUX select for Phase Register Reset to select between CTL_PHASE_REG_RST=0 rx_phase_reg_rst (External signal) or CTL_PHASE_REG_RST=1 LCL_PHASE_REG_RST" "0,1" newline bitfld.word 0x0 6. "LCL_PHASE_REG_RST,Reset phase register.This bit is only selected when CTL_PHASE_REG_RST= 1" "0,1" newline bitfld.word 0x0 5. "CTL_BST,MUX select for AFE Boost to select between CTL_BST=0 rx_aeq[2:0] (External signal) or CTL_BST=1 LCL_BST" "0,1" newline bitfld.word 0x0 2.--4. "LCL_BST,RX Boost (equalization) Value" "0,1,2,3,4,5,6,7" newline bitfld.word 0x0 1. "CTL_RXTERM,MUX select for RX Term enable to select between CTL_RXTERM=0 rx_term_en (External signal) or CTL_RXTERM=1 LCL_RXTERM" "0,1" newline bitfld.word 0x0 0. "LCL_RXTERM,Enable/disable RX termination when CTL_RXTERM = 1" "0,1" group.word 0x1094++0x1 line.word 0x0 "LANE0_ANA_RX_ENPWR2,Yet another RX State Control Register" newline hexmask.word.byte 0x0 8.--15. 1. "RESERVED_15_8,Reserved for Future use" newline bitfld.word 0x0 7. "EN_RXPMIX_TST,Enable XOR gate to test linearity of RX phase mixer using atb_s_p and atb_s_m" "0,1" newline bitfld.word 0x0 6. "EN_RXPMIX_VPMIX,Put vreg_pmix on atb_s_p" "0,1" newline bitfld.word 0x0 5. "EN_RXPMIX_VRX,Put vreg_rx on atb_s_p" "0,1" newline bitfld.word 0x0 4. "RX_DCC_IQ_OFFSET_H_0,Code which helps to manually tune reference voltage (r-string dac) for IQ opamp and correct input offset (rx_dcc_iq_offset_h_0 bit)" "0,1" newline bitfld.word 0x0 3. "EN_RXPMIX_FRC_VPMIX_H,Connecting vbg_in to vbg (in case of 0) or to atb_s_m_int (in case of 1)" "0,1" newline bitfld.word 0x0 2. "RX_SCOPE_ATB_2,Put XOR of RX SCOPE PMIX input and output on atb_s_p" "0,1" newline bitfld.word 0x0 1. "RX_SCOPE_ATB_1,Put RX SCOPE regulated VP on atb_s_p" "0,1" newline bitfld.word 0x0 0. "RX_SCOPE_ATB_0,Have RX SCOPE reference for regulator use atb_f_p as a reference instead of VP/VBG" "0,1" group.word 0x1098++0x1 line.word 0x0 "LANE0_ANA_RX_SCOPE_VDCC,RX Scope controls and clock DCC control voltage probe" newline hexmask.word.byte 0x0 8.--15. 1. "RESERVED_15_8,Reserved for Future use" newline bitfld.word 0x0 6.--7. "VDCC,Probe DCC control voltage" "0,1,2,3" newline bitfld.word 0x0 5. "NC5,Reserved" "0,1" newline bitfld.word 0x0 4. "RX_SCOPE_SLEW,Set high for low RX clock frqeuencies (625MHz) for RX Scope to work correctly" "0,1" newline bitfld.word 0x0 3. "RX_SCOPE_FDIV20,Divide scope output clock by 20 instead of 10" "0,1" newline bitfld.word 0x0 2. "RX_LOS_LFPS_EN_BIT_2,In case of rx_los_lfps_en_cntrl = 1/0 reg_rx_los_lfps_en/rx_ana_los_lfps_en signal directly applied to rx_los circuit through I101 multiplexer." "0,1" newline bitfld.word 0x0 1. "RX_DCC_IQ_OFFSET_EN_H,Select ref voltage for IQ opamp from testmode part (in case of 1) or from ordinary resistive dividers (in case of 0)." "0,1" newline bitfld.word 0x0 0. "RX_LOS_LFPS_EN,Enables the RX LOS LFPS mode use when you want to detect incoming LFPS signals USB3.0" "0,1" group.word 0x10AC++0x1 line.word 0x0 "LANE0_ANA_TX_TXDRV_CNTRL,Register 3" newline hexmask.word.byte 0x0 8.--15. 1. "RESERVED_15_8,Reserved for Future use" newline bitfld.word 0x0 7. "PULL_DN_REG,register bit that causes the calibrated TX bits to pull down in a common mode fashion. If pull_dn_reg and tx_pull_up are both high then pull_dn_reg wins" "0,1" newline bitfld.word 0x0 6. "PULL_UP_REG,Register override for tx_pull_up. Used when ovrd_pull_up is HIGH causes calibrated TX bits to pull up in a common mode fashion unless pull_dn_reg is HIGH" "0,1" newline bitfld.word 0x0 5. "OVRD_PULL_UP,Selects local value of pull_up_reg instead of tx_pull_up" "0,1" newline bitfld.word 0x0 4. "VCM_HOLD_REG,Register override for tx_vcm_hold. Used when ovrd_vcm_hold is HIGH controls the TX common mode hold circuitry" "0,1" newline bitfld.word 0x0 3. "OVRD_VCM_HOLD,Selects local value of vcm_hold_reg instead of tx_vcm_hold to control state of TX common mode hold circuitry" "0,1" newline bitfld.word 0x0 2. "REFGEN_PWRDN_OVRD_N,Set LOW for TX regulator not to turn on when RX clock is enabled. Default is for TX regulator to turn on when RX or TX clock is enabled" "0,1" newline bitfld.word 0x0 1. "NOCONN_1,Reserved" "0,1" newline bitfld.word 0x0 0. "NOCONN_0,Reserved" "0,1" group.word 0x10B0++0x1 line.word 0x0 "LANE0_ANA_TX_POWER_CTL,Register 4" newline hexmask.word.byte 0x0 8.--15. 1. "RESERVED_15_8,Reserved for Future use" newline bitfld.word 0x0 7. "OVRD_EN,Enables local overrides for all signals in this register except for TX_DIV_CLK_EN which doesn't need this signal" "0,1" newline bitfld.word 0x0 6. "SERIAL_EN_REG,Forces state of tx_serial_en when OVRD_EN is 1" "0,1" newline bitfld.word 0x0 5. "CLK_EN_REG,Forces state of tx_clk_en when OVRD_EN is 1" "0,1" newline bitfld.word 0x0 4. "DATA_EN_REG,Forces state of tx_data_en when OVRD_EN is HIGH" "0,1" newline bitfld.word 0x0 3. "REFGEN_EN_REG,Register override value for tx_refgen_en. Controls the TX regulator biasing circuitry and the rxdetect comparators when OVRD_EN is HIGH. This function may be overridden by the state of refgen_pwdn_reg" "0,1" newline bitfld.word 0x0 2. "TX_DIV_CLK_EN,Enables the div clock that goes from the TX to the undersampler more appropriately called tx_sampler_clk_en this clock comes after the optional divide by 2 or 4 tx_clk_en must be HIGH to get a clock out" "0,1" newline bitfld.word 0x0 1. "REFGEN_PDN_REG,Register override for refgen pwdn. Used when OVRD_EN is HIGH. Controls the TX regulator biasing circuitry and the rxdetect comparators when OVRD_EN is HIGH" "0,1" newline bitfld.word 0x0 0. "LFPS_HIGH_PRIORITY,When this is set high LFPS priority becomes higher than tx_data" "0,1" group.word 0x10B4++0x1 line.word 0x0 "LANE0_ANA_TX_ALT_BLOCK,Register 5" newline hexmask.word.byte 0x0 8.--15. 1. "RESERVED_15_8,Reserved for Future use" newline bitfld.word 0x0 7. "EN_ALT_BUS,Enables the TX for alt bus mode powers up the TX regulator biasing circuitry and the rxdetect comparators. Needed if manually running the alt bus features" "0,1" newline bitfld.word 0x0 5.--6. "DRV_SOURCE_REG,Forces state of tx_data_source when OVRD_ALT_BUS is HIGH. 00 = serializer data or alt oscillator vp/vph/vphreg/vptx if selected 01 = jtag data differential 10 = LFPS oscillator differential 11 = jtag data common mode drive for test" "serializer data or alt oscillator..,jtag data differential,?,?" newline bitfld.word 0x0 4. "JTAG_DATA_REG,Forces state of jtag_data when OVRD_ALT_BUS is HIGH" "0,1" newline bitfld.word 0x0 1.--3. "TX_RINGO_CNTRL,Enables and connects the various test oscillators to the transmit pins must set drv_source_reg bus correctly. 0XX = All oscillators are disabled 100 = HV oscillator enabled 101 = SVT oscillator enabled 110 = LVT oscillator enabled 111.." "0,1,2,3,4,5,6,7" newline bitfld.word 0x0 0. "OVRD_ALT_BUS,Enables local overrides for alt-bus control signals: DRV_SOURCE_REG and JTAG_DATA_REG" "0,1" group.word 0x10B8++0x1 line.word 0x0 "LANE0_ANA_TX_ALT_AND_LOOPBACK,Register 6" newline hexmask.word.byte 0x0 8.--15. 1. "RESERVED_15_8,Reserved for Future use" newline bitfld.word 0x0 7. "OVRD_TX_LB,Enables the override of the tx_lb_en" "0,1" newline bitfld.word 0x0 6. "TX_LB_EN_REG,Forces state of tx_lb_en when OVRD_TX_LB is enabled" "0,1" newline bitfld.word 0x0 5. "ATB_VPTX,Connects vptx to atb_s_p and gd to atb_s_m" "0,1" newline bitfld.word 0x0 4. "ATB_VREG_TX,Connects TX regulator input reference to atb_s_p and gd to atb_s_m" "0,1" newline bitfld.word 0x0 3. "ATB_VDCCP,Connects vdcc_p to atb_s_p" "0,1" newline bitfld.word 0x0 2. "ATB_VDCCM,Connects vdcc_m to atb_s_m" "0,1" newline bitfld.word 0x0 1. "NOCONN_01,Reserved" "0,1" newline bitfld.word 0x0 0. "SELECT_PMIX_CLK,select pmix_clk for TX clock for ATE test mode" "0,1" group.word 0x10BC++0x1 line.word 0x0 "LANE0_ANA_TX_TX_ATB_REG,Register 7" newline hexmask.word.byte 0x0 8.--15. 1. "RESERVED_15_8,Reserved for Future use" newline bitfld.word 0x0 7. "ATB_PBIAS,Connect real pmos_bias voltage for TX PMOS driver pull up path to atb_s_p and local ground at the pmos_bias block to atb_s_m" "0,1" newline bitfld.word 0x0 6. "ATB_VCM_REP,Connect common mode replica voltage in pmos_bias block to atb_s_p and local ground to atb_s_m" "0,1" newline bitfld.word 0x0 5. "ATB_RXDETREF,Connect RX detect block reference voltage to atb_s_p and local ground to atb_s_m" "0,1" newline bitfld.word 0x0 4. "ATB_TXFP,Connect tx_p to atb_f_p" "0,1" newline bitfld.word 0x0 3. "ATB_TXFM,Connect tx_m to atb_f_m" "0,1" newline bitfld.word 0x0 2. "ATB_TXSP,Connect tx_p to atb_s_p" "0,1" newline bitfld.word 0x0 1. "ATB_TXSM,Connect tx_m to atb_s_m" "0,1" newline bitfld.word 0x0 0. "ATB_VCM,Connect tx_p/tx_m common mode voltage onto atb_s_p and local ground onto atb_s_m" "0,1" group.word 0x10C0++0x1 line.word 0x0 "LANE0_ANA_TX_TX_BOOST,Register 8" newline hexmask.word.byte 0x0 8.--15. 1. "RESERVED_15_8,Reserved for Future use" newline bitfld.word 0x0 7. "OVRD_VBOOST_EN,Enables the overrides on VBOOST_EN_REG" "0,1" newline bitfld.word 0x0 6. "VBOOST_EN_REG,Forces state of tx_vboost_en when OVRD_VBOOST_EN is HIGH" "0,1" newline bitfld.word 0x0 5. "VCON_EN_N,Forces state of vcon_en_n" "0,1" newline bitfld.word 0x0 4. "ATB_VBOOST,Connects vboost to atb_s_p and local ground to Atb_s_m" "0,1" newline bitfld.word 0x0 3. "ATB_VCMBOOST,Connects vcmboost to atb_s_p and local ground to atb_s_m." "0,1" newline bitfld.word 0x0 2. "ATB_F_VBOOST_REF,Enables forcing of tx_vboost_vref through atb_f_p from external" "0,1" newline bitfld.word 0x0 1. "OVRD_VREG_DECAP,Enables override of vreg_decap_en_n signal" "0,1" newline bitfld.word 0x0 0. "VREG_DECAP_EN_N_REG,Forces state of vreg_decap_en_n control signal. Controls whether extra decoupling is switched in for TX regulator output." "0,1" group.word 0x1100++0x1 line.word 0x0 "LANE0_DIG_RX_CDR_FSM_INIT_CTL,Control bits for CDR init phase portion" newline hexmask.word.byte 0x0 9.--15. 1. "RESERVED_15_9,Reserved for Future use" newline bitfld.word 0x0 8. "INIT_CNT_OVRD,Active high override enable bit to select the override INIT_CNT register 0 = Disabled 1 = Enabled" "Disabled,Enabled" newline hexmask.word.byte 0x0 0.--7. 1. "INIT_CNT,Override value for CDR Init Phase" group.word 0x1104++0x1 line.word 0x0 "LANE0_DIG_RX_CDR_FSM_TRACK_CTL,Control bits for CDR track phase portion" newline hexmask.word.byte 0x0 9.--15. 1. "RESERVED_15_9,Reserved for Future use" newline bitfld.word 0x0 8. "TRACK_CNT_OVRD,Active high override enable bit to select the override TRACK_CNT register 0 = Disabled 1 = Enabled" "Disabled,Enabled" newline hexmask.word.byte 0x0 0.--7. 1. "TRACK_CNT,Override value for CDR Track Phase" group.word 0x1108++0x1 line.word 0x0 "LANE0_DIG_RX_CDR_FSM_LOCK_CTL,Control bits for CDR lock phase portion" newline hexmask.word.byte 0x0 9.--15. 1. "RESERVED_15_9,Reserved for Future use" newline bitfld.word 0x0 8. "LOCK_CNT_OVRD,Active high override enable bit to select the override LOCK_CNT register 0 = Disabled 1 = Enabled" "Disabled,Enabled" newline hexmask.word.byte 0x0 0.--7. 1. "LOCK_CNT,Override value for CDR Lock Phase" repeat 9. (list 0x0 0x1 0x2 0x3 0x4 0x8 0x9 0xB 0xC )(list 0x0 0x4 0x8 0xC 0x10 0x20 0x24 0x2C 0x30 ) rgroup.word ($2+0x2000)++0x1 line.word 0x0 "PORT0_STAT_RO_$1,Status Register 0" newline hexmask.word 0x0 4.--15. 1. "RESERVED_15_4,Reserved for Future use" newline bitfld.word 0x0 3. "PLL_LOCK,analog PLL Lock Signal" "0,1" newline bitfld.word 0x0 2. "RX_SQUELCH,analog RX Squelch Signal" "0,1" newline bitfld.word 0x0 1. "RESERVED_1,Reserved" "0,1" newline bitfld.word 0x0 0. "RESERVED_0,Reserved" "0,1" repeat.end repeat 7. (list 0x5 0x6 0x7 0xA 0xD 0xE 0xF )(list 0x0 0x4 0x8 0x14 0x20 0x24 0x28 ) rgroup.word ($2+0x2014)++0x1 line.word 0x0 "PORT0_STAT_RO_$1,Status Register 5" newline hexmask.word 0x0 4.--15. 1. "RESERVED_15_4,Reserved for Future use" newline hexmask.word.byte 0x0 0.--3. 1. "DATAOUT,UTMI+ Output DATAOUT" repeat.end repeat 2. (list 0x0 0x6 )(list 0x0 0x18 ) group.word ($2+0x2040)++0x1 line.word 0x0 "PORT0_OVRD_RW_$1,Override Register 0" newline hexmask.word.byte 0x0 8.--15. 1. "RESERVED_15_8,Reserved for Future use" newline hexmask.word.byte 0x0 4.--7. 1. "OVERRD_ADDR_OVRD_EN,Override Enable for overrd_addr [7:4]" newline hexmask.word.byte 0x0 0.--3. 1. "OVERRD_ADDR,Analog Test Control Override Address [3:0]" repeat.end repeat 10. (list 0x1 0x2 0x3 0x4 0x8 0x9 0xA 0xB 0xE 0xF )(list 0x0 0x4 0x8 0xC 0x1C 0x20 0x24 0x28 0x34 0x38 ) group.word ($2+0x2044)++0x1 line.word 0x0 "PORT0_OVRD_RW_$1,Override Register 1" newline hexmask.word.byte 0x0 8.--15. 1. "RESERVED_15_8,Reserved for Future use" newline bitfld.word 0x0 7. "VBUS_VALID_PU_OVRD_EN,Override Enable for vbus_valid_pu" "0,1" newline bitfld.word 0x0 6. "OTG_PU_OVRD_EN,Override Enable for otg_pu" "0,1" newline bitfld.word 0x0 5. "TX_VREF_VREG_PU_OVRD_EN,Override Enable for tx_vref_vreg_pu" "0,1" newline bitfld.word 0x0 4. "SQRX_PU_OVRD_EN,Override Enable for sqrx_pu" "0,1" newline bitfld.word 0x0 3. "VBUS_VALID_PU,DRVVBUS Input" "0,1" newline bitfld.word 0x0 2. "OTG_PU,OTGDISABLE Input" "0,1" newline bitfld.word 0x0 1. "TX_VREF_VREG_PU,TX hs_driver Comparator Power Up" "0,1" newline bitfld.word 0x0 0. "SQRX_PU,RX squelch Comparator Power Up" "0,1" repeat.end group.word 0x2054++0x1 line.word 0x0 "PORT0_OVRD_RW_5,Override Register 5" newline hexmask.word.byte 0x0 8.--15. 1. "RESERVED_15_8,Reserved for Future use" newline bitfld.word 0x0 6.--7. "XO_CLK_DIV_OVRD_EN,Override Enable for xo_clk_div" "0,1,2,3" newline bitfld.word 0x0 5. "MSTR_OVERRD_BIT_OVRD_EN,Override Enable for mstr_overrd_bit" "0,1" newline bitfld.word 0x0 4. "OVERRD_ADDR_4_OVRD_EN,Override Enable for overrd_addr_4" "0,1" newline bitfld.word 0x0 2.--3. "XO_CLK_DIV,setting reference clock division" "0,1,2,3" newline bitfld.word 0x0 1. "MSTR_OVERRD_BIT,Analog Test Control Master Override" "0,1" newline bitfld.word 0x0 0. "OVERRD_ADDR_4,Analog Test Control Override Address [4]" "0,1" group.word 0x205C++0x1 line.word 0x0 "PORT0_OVRD_RW_7,Override Register 7" newline hexmask.word.byte 0x0 8.--15. 1. "RESERVED_15_8,Reserved for Future use" newline bitfld.word 0x0 7. "TX_LS_EN_OVRD_EN,Override Enable for tx_ls_en" "0,1" newline bitfld.word 0x0 4.--6. "PWR_SEQ_CLK_DIV_OVRD_EN,Override Enable for pwr_seq_clk_div" "0,1,2,3,4,5,6,7" newline bitfld.word 0x0 3. "TX_LS_EN,TX LS Enable" "0,1" newline bitfld.word 0x0 0.--2. "PWR_SEQ_CLK_DIV,setting power_sequence division" "0,1,2,3,4,5,6,7" group.word 0x2070++0x1 line.word 0x0 "PORT0_OVRD_RW_12,Override Register 12" newline hexmask.word.byte 0x0 8.--15. 1. "RESERVED_15_8,Reserved for Future use" newline bitfld.word 0x0 7. "RES_ACK_OUT_OVRD_EN,Override Enable for res_ack_out" "0,1" newline bitfld.word 0x0 5.--6. "PLL_CLK_DIV_OVRD_EN,Override Enable for pll_clk_div" "0,1,2,3" newline bitfld.word 0x0 4. "PLL_RESET_OVRD_EN,Override Enable for pll_reset" "0,1" newline bitfld.word 0x0 3. "RES_ACK_OUT,Ack resistor tune external requirement" "0,1" newline bitfld.word 0x0 1.--2. "PLL_CLK_DIV,setting MPLL division" "0,1,2,3" newline bitfld.word 0x0 0. "PLL_RESET,MPLL gear_shift" "0,1" group.word 0x2074++0x1 line.word 0x0 "PORT0_OVRD_RW_13,Override Register 13" newline hexmask.word.byte 0x0 8.--15. 1. "RESERVED_15_8,Reserved for Future use" newline bitfld.word 0x0 7. "BIST_MODE_OVRD_EN,Override Enable for bist_mode" "0,1" newline bitfld.word 0x0 6. "TEST_PKT_RPT_OVRD_EN,Override Enable for test_pkt_rpt" "0,1" newline bitfld.word 0x0 4.--5. "XO_CLK_SEL_OVRD_EN,Override Enable for xo_clk_sel" "0,1,2,3" newline bitfld.word 0x0 3. "BIST_MODE,BIST Mode" "0,1" newline bitfld.word 0x0 2. "TEST_PKT_RPT,BIST Test Packet Mode" "0,1" newline bitfld.word 0x0 0.--1. "XO_CLK_SEL,Reference Clock Selection" "0,1,2,3" rgroup.word 0x8000++0x1 line.word 0x0 "SUPX_DIG_IDCODE_LO,Low 16 bits of IDCODE" newline hexmask.word 0x0 0.--15. 1. "DATA," rgroup.word 0x8004++0x1 line.word 0x0 "SUPX_DIG_IDCODE_HI,High 16 bits of IDCODE" newline hexmask.word 0x0 0.--15. 1. "DATA," group.word 0x8008++0x1 line.word 0x0 "SUPX_DIG_DEBUG,Debug controls" newline hexmask.word 0x0 7.--15. 1. "RESERVED_15_7,Reserved for Future use" newline bitfld.word 0x0 5.--6. "DTB_SEL,The lane DTB's are OR'd together with the support DTB signals selected with the below encodings 0 - none 1 - reset_ctl DTB output 2 - scope DTB output 3 - rtune DTB output" "none,reset_ctl DTB output,scope DTB output,rtune DTB output" newline hexmask.word.byte 0x0 0.--4. 1. "TX_VREF_SEL," group.word 0x800C++0x1 line.word 0x0 "SUPX_DIG_RTUNE_DEBUG,Resistor tuning debug controls" newline rbitfld.word 0x0 15. "RESERVED_15_15,Reserved for Future use" "0,1" newline hexmask.word 0x0 5.--14. 1. "VALUE,Value to use when triggering SET_VAL field only the 6 LSB's are used when setting rx or tx cal values (USER2 - read-write and custom)" newline bitfld.word 0x0 3.--4. "TYPE,Type of manual tuning or register read/write to execute 0 - ADC or read/write rt_value 1 - Rx tune or read/write rx_cal_val (only 6 bits) 2 - Tx tune or read/write tx_cal_val (only 6 bits) 3 - Resref detect (no affect when triggering SET_VAL.." "ADC,Rx tune,read-write and custom),Resref detect" newline bitfld.word 0x0 2. "SET_VAL,Set value Write to a 1 to manually write the register specified by the TYPE field to the value in the VALUE field (USER2 - read-write and custom)" "0,1" newline bitfld.word 0x0 1. "MAN_TUNE,Write to a 1 to do a manual tuning specified by TYPE field starting a manual tune while a tune is currently running can cause unpredictable results. For use only when you know the state of the rtune circuit. (USER2 - read-write and custom)" "0,1" newline bitfld.word 0x0 0. "FLIP_COMP,Invert analog comparator output (USER2 - read-write and custom)" "0,1" rgroup.word 0x8010++0x1 line.word 0x0 "SUPX_DIG_RTUNE_STAT,Resistor tuning register status" newline hexmask.word.byte 0x0 10.--15. 1. "RESERVED_15_10,Reserved for Future use" newline hexmask.word 0x0 0.--9. 1. "STAT,Current value of the register specifed by the TYPE field in the debug control register. Set the TYPE field in the DEBUG register and then do a read of this register. (RU - read-only volatile)" group.word 0x8014++0x1 line.word 0x0 "SUPX_DIG_SS_PHASE,Current MPLL phase selector value" newline bitfld.word 0x0 13.--15. "REF_SEL_DIV,Reference Divisor to get better resolution and lower PPM errors when synthesizing from a non-integer reference clock. NOTE: Default value is 4. One is added in hardware to give a range of 1 to 8. (volatile and 2 reads needed to read value)" "0,1,2,3,4,5,6,7" newline bitfld.word 0x0 12. "PH_SEL,Phase Mixer Clock select. 1: is pmix. 0 is VCO. (volatile and 2 reads needed to read value)" "?,is pmix" newline bitfld.word 0x0 11. "ZERO_FREQ,Zero frequency register. NOTES: Must be set for PHASE writes to stick (volatile and 2 reads needed to read value)" "0,1" newline hexmask.word 0x0 2.--10. 1. "VAL,Phase value from zero reference (volatile and 2 reads needed to read value)" newline bitfld.word 0x0 0.--1. "DTHR,Bits below the useful resolution (volatile and 2 reads needed to read value)" "0,1,2,3" group.word 0x8018++0x1 line.word 0x0 "SUPX_DIG_SS_FREQ,Frequency Control for Spread Spectrum" newline rbitfld.word 0x0 15. "RESERVED_15_15,Reserved for Future use" "0,1" newline bitfld.word 0x0 14. "FREQ_OVRD,Frequency Reigster Override. NOTE: Must be set for PHASE writes to stick (volatile and 2 reads needed to read value)" "0,1" newline hexmask.word.byte 0x0 7.--13. 1. "FREQ_PK,Peak Frequency Value (for changing direction) (volatile and 2 reads needed to read value)" newline hexmask.word.byte 0x0 0.--6. 1. "FREQ_CNT_INIT,Initial Frequency Counter Value (volatile and 2 reads needed to read value)" group.word 0x801C++0x1 line.word 0x0 "SUPX_DIG_HSP_SS_PHASE,Current HSP_PMIX SSC phase sel value" newline hexmask.word.byte 0x0 11.--15. 1. "RESERVED_15_11,Reserved for Future use" newline hexmask.word.byte 0x0 4.--10. 1. "VAL,SSC phase value from zero reference (volatile and 2 reads needed to read value)" newline hexmask.word.byte 0x0 0.--3. 1. "DTHR,Bits below the useful resolution (volatile and 2 reads needed to read value)" group.word 0x8020++0x1 line.word 0x0 "SUPX_DIG_MPLL_CNT_CTL,Control for fixed or variable MPLL Count Selection" newline hexmask.word 0x0 1.--15. 1. "RESERVED_15_1,Reserved for Future use" newline bitfld.word 0x0 0. "VAR_CNT_EN,Selects variable count when enabled (Default = fixed count)" "0,1" group.word 0x8024++0x1 line.word 0x0 "SUPX_DIG_CR_PARA_ALU_CTL,Control for CR Parallel ALU access" newline hexmask.word 0x0 5.--15. 1. "RESERVED_15_5,Reserved for Future use" newline hexmask.word.byte 0x0 1.--4. 1. "CR_PARA_ALU_OPCODE,Opcode for the ALU when CR para access is enabled. Valid opcodes are as follows: 0 - Zero the accumulator 1 - Add control register read result to accumulator 2 - Add control register write data to accumulator 3 - Shift accumulator left.." newline bitfld.word 0x0 0. "CR_PARA_ALU_ACCESS_EN,Enable access to the ALU through the CR parallel bus." "0,1" rgroup.word 0x8028++0x1 line.word 0x0 "SUPX_DIG_CR_PARA_ALU_FLAGS,Flags from the ALU when CR para access is enabled." newline hexmask.word 0x0 4.--15. 1. "RESERVED_15_4,Reserved for Future use" newline hexmask.word.byte 0x0 0.--3. 1. "DATA,Flags from the ALU when CR para access is enabled. Valid ALU flags: 0 - Signedness used for next ADD_PHSEL command. (1=signed 0=unsigned) 1 - Signedness for ADD_PHSEL command has been chosen by a previous ADD_PHSEL command. 2 - Error detected.." group.word 0x8040++0x1 line.word 0x0 "SUPX_DIG_ATEOVRD,Override values for incoming controls from ASIC" newline hexmask.word 0x0 3.--15. 1. "RESERVED_15_3,Reserved for Future use" newline bitfld.word 0x0 2. "ATEOVRD_EN,Override enable for ATE signals. NOTE: This register is only accessible through cregs. Does not retain state during reset or ATPG. (USER2 - read-write and custom)" "0,1" newline bitfld.word 0x0 1. "REF_USB2_EN,Override value for USB HSP PHY ref_clk enable. (USER2 - read-write and custom)" "0,1" newline bitfld.word 0x0 0. "REF_CLKDIV2,Override value for SSP ref_clk pre-scaler. (USER2 - read-write and custom)" "0,1" group.word 0x8044++0x1 line.word 0x0 "SUPX_DIG_MPLL_OVRD_IN_LO,Override values for incoming RTUNE and MPLL controls from ASIC" newline bitfld.word 0x0 15. "RES_ACK_IN_OVRD,Override enable for res_ack_in" "0,1" newline bitfld.word 0x0 14. "RES_ACK_IN,Override value for res_ack_in" "0,1" newline bitfld.word 0x0 13. "RES_REQ_IN_OVRD,Override enable for res_req_in" "0,1" newline bitfld.word 0x0 12. "RES_REQ_IN,Override value for res_req_in" "0,1" newline bitfld.word 0x0 11. "RTUNE_REQ_OVRD,Override enable for rtune_req" "0,1" newline bitfld.word 0x0 10. "RTUNE_REQ,Override value for rtune_req" "0,1" newline bitfld.word 0x0 9. "MPLL_MULTIPLIER_OVRD,Override enable for mpll_multipler" "0,1" newline hexmask.word.byte 0x0 2.--8. 1. "MPLL_MULTIPLIER,Override value for mpll_multipler" newline bitfld.word 0x0 1. "MPLL_EN_OVRD,Override enable for mpll_en" "0,1" newline bitfld.word 0x0 0. "MPLL_EN,Override value for mpll_en" "0,1" group.word 0x8048++0x1 line.word 0x0 "SUPX_DIG_MPLL_OVRD_IN_HI,Override values for incoming VBOOST LVL and MPLL controls from ASIC" newline bitfld.word 0x0 13.--15. "TX_VBOOST_LVL,Override value for tx_vboost_lvl. Override enabled using LEVEL_EN from LEVEL_OVRD_IN register." "0,1,2,3,4,5,6,7" newline bitfld.word 0x0 12. "MPLL_REFSSC_CLK_EN_OVRD,Override enable for mpll_refssc_clk_en" "0,1" newline bitfld.word 0x0 11. "MPLL_REFSSC_CLK_EN,Override value for mpll_refssc_clk_en" "0,1" newline bitfld.word 0x0 10. "MPLL_RST,Reset the MPLL state machine Writing the register with this bit set will reset the MPLL power up/down FSM regardless of the current state of the register bit." "0,1" newline bitfld.word 0x0 9. "FSEL_OVRD,Override enable for fsel[2:0]" "0,1" newline bitfld.word 0x0 6.--8. "FSEL,Override value for fsel [2:0]" "0,1,2,3,4,5,6,7" newline bitfld.word 0x0 5. "MPLL_WORD_CLK_EN_OVRD,Override enable for mpll_word_clk_en" "0,1" newline bitfld.word 0x0 4. "MPLL_WORD_CLK_EN,Override value for mpll_word_clk_en" "0,1" newline bitfld.word 0x0 3. "MPLL_DWORD_CLK_EN_OVRD,Override enable for mpll_dword_clk_en" "0,1" newline bitfld.word 0x0 2. "MPLL_DWORD_CLK_EN,Override value for mpll_dword_clk_en" "0,1" newline bitfld.word 0x0 1. "MPLL_QWORD_CLK_EN_OVRD,Override enable for mpll_qword_clk_en" "0,1" newline bitfld.word 0x0 0. "MPLL_QWORD_CLK_EN,Override value for mpll_qword_clk_en" "0,1" group.word 0x804C++0x1 line.word 0x0 "SUPX_DIG_SSC_OVRD_IN,Override values for incoming SSC controls from ASIC" newline rbitfld.word 0x0 14.--15. "RESERVED_15_14,Reserved for Future use" "0,1,2,3" newline bitfld.word 0x0 13. "SSC_OVRD_IN_EN,Override enable for Spread Spectrum generator." "0,1" newline bitfld.word 0x0 12. "SSC_EN,Override value for SSC enable." "0,1" newline bitfld.word 0x0 9.--11. "SSC_RANGE,Override value for SSC modulation range." "0,1,2,3,4,5,6,7" newline hexmask.word 0x0 0.--8. 1. "SSC_REF_CLK_SEL,Override value for reference clock scaling" group.word 0x8050++0x1 line.word 0x0 "SUPX_DIG_BS_OVRD_IN,Override values for incoming BS controls from ASIC" newline hexmask.word.byte 0x0 12.--15. 1. "RESERVED_15_12,Reserved for Future use" newline bitfld.word 0x0 11. "EN,Enable override values for all inputs controlled by this register" "0,1" newline bitfld.word 0x0 10. "INVERT,Override value for bs_invert" "0,1" newline bitfld.word 0x0 9. "INIT,Override value for bs_init" "0,1" newline bitfld.word 0x0 8. "HIGHZ,Override value for bs_highz" "0,1" newline bitfld.word 0x0 7. "CLAMP,Override value for bs_clamp" "0,1" newline bitfld.word 0x0 6. "EXTEST_AC,Override value for bs_extest_ac" "0,1" newline bitfld.word 0x0 5. "EXTEST,Override value for bs_extest" "0,1" newline bitfld.word 0x0 4. "PRELOAD,Override value for bs_preload" "0,1" newline bitfld.word 0x0 3. "UPDATE_DR,Override value for bs_update_dr" "0,1" newline bitfld.word 0x0 2. "CAPTURE_DR,Override value for bs_capture_dr" "0,1" newline bitfld.word 0x0 1. "SHIFT_DR,Override value for bs_shift_dr" "0,1" newline bitfld.word 0x0 0. "IN,Override value for bs_in" "0,1" group.word 0x8054++0x1 line.word 0x0 "SUPX_DIG_LEVEL_OVRD_IN,Override values for acjt_level and los_level" newline bitfld.word 0x0 13.--15. "LOS_BIAS,Override value for los_bias" "0,1,2,3,4,5,6,7" newline bitfld.word 0x0 12. "MPLL_HALF_RATE_OVRD,Enable override value for mpll_half_rate" "0,1" newline bitfld.word 0x0 11. "MPLL_HALF_RATE,Override value for mpll_half_rate" "0,1" newline bitfld.word 0x0 10. "LEVEL_EN,Enable override values for tx_vboost_lvl/los_bias/los_level/acjt_level inputs controlled by this and MPLL_OVRD_IN_HI registers" "0,1" newline hexmask.word.byte 0x0 5.--9. 1. "ACJT_LEVEL,Override value for acjt_level" newline hexmask.word.byte 0x0 0.--4. 1. "LOS_LEVEL,Override value for los_level" group.word 0x8058++0x1 line.word 0x0 "SUPX_DIG_SUP_OVRD_OUT,Override values for support block" newline hexmask.word.byte 0x0 10.--15. 1. "RESERVED_15_10,Reserved for Future use" newline bitfld.word 0x0 9. "MPLL_STATE_OVRD,Override enable for mpll_state output" "0,1" newline bitfld.word 0x0 8. "MPLL_STATE,Override value for mpll_state output" "0,1" newline bitfld.word 0x0 7. "BS_OUT_OVRD,Override enable for bs_out output" "0,1" newline bitfld.word 0x0 6. "BS_OUT,Override value for bs_out output" "0,1" newline bitfld.word 0x0 5. "RTUNE_ACK_OVRD,Override enable for rtune_ack output" "0,1" newline bitfld.word 0x0 4. "RTUNE_ACK,Override value for rtune_ack output" "0,1" newline bitfld.word 0x0 3. "RES_REQ_OUT_OVRD,Override enable for res_req_out output" "0,1" newline bitfld.word 0x0 2. "RES_REQ_OUT,Override value for res_req_out output" "0,1" newline bitfld.word 0x0 1. "RES_ACK_OUT_OVRD,Override enable for res_ack_out output" "0,1" newline bitfld.word 0x0 0. "RES_ACK_OUT,Override value for res_ack_out output" "0,1" rgroup.word 0x805C++0x1 line.word 0x0 "SUPX_DIG_MPLL_ASIC_IN,Current values for incoming MPLL controls from ASIC" newline bitfld.word 0x0 15. "RESERVED_15_15,Reserved for Future use" "0,1" newline bitfld.word 0x0 14. "MPLL_REFSSC_CLK_EN,Value from ASIC for mpll_refssc_clk_en (RU - read-only volatile)" "0,1" newline bitfld.word 0x0 13. "MPLL_WORD_CLK_EN,Value from ASIC for mpll_word_clk_en (RU - read-only volatile)" "0,1" newline bitfld.word 0x0 12. "MPLL_DWORD_CLK_EN,Value from ASIC for mpll_dword_clk_en (RU - read-only volatile)" "0,1" newline bitfld.word 0x0 11. "MPLL_QWORD_CLK_EN,Value from ASIC for mpll_qword_clk_en (RU - read-only volatile)" "0,1" newline bitfld.word 0x0 10. "RES_ACK_IN,Value from ASIC for res_ack_in (RU - read-only volatile)" "0,1" newline bitfld.word 0x0 9. "RES_REQ_IN,Value from ASIC for res_req_in (RU - read-only volatile)" "0,1" newline bitfld.word 0x0 8. "RTUNE_REQ,Value from ASIC for rtune_req (RU - read-only volatile)" "0,1" newline hexmask.word.byte 0x0 1.--7. 1. "MPLL_MULTIPLIER,Value from ASIC for mpll_multiplier (RU - read-only volatile)" newline bitfld.word 0x0 0. "MPLL_EN,Value from ASIC for mpll_en (RU - read-only volatile)" "0,1" rgroup.word 0x8060++0x1 line.word 0x0 "SUPX_DIG_BS_ASIC_IN,Current values for incoming boundary scan controls from ASIC" newline bitfld.word 0x0 14.--15. "RESERVED_15_14,Reserved for Future use" "0,1,2,3" newline bitfld.word 0x0 11.--13. "TX_VBOOST_LVL,Value from ASIC for tx_vboost_lvl -- Not as bs_* signal but we're out of bits. (RU - read-only volatile)" "0,1,2,3,4,5,6,7" newline bitfld.word 0x0 10. "INVERT,Value from ASIC for bs_invert (RU - read-only volatile)" "0,1" newline bitfld.word 0x0 9. "INIT,Value from ASIC for bs_init (RU - read-only volatile)" "0,1" newline bitfld.word 0x0 8. "HIGHZ,Value from ASIC for bs_highz (RU - read-only volatile)" "0,1" newline bitfld.word 0x0 7. "CLAMP,Value from ASIC for bs_clamp (RU - read-only volatile)" "0,1" newline bitfld.word 0x0 6. "EXTEST_AC,Value from ASIC for bs_extest_ac (RU - read-only volatile)" "0,1" newline bitfld.word 0x0 5. "EXTEST,Value from ASIC for bs_extest (RU - read-only volatile)" "0,1" newline bitfld.word 0x0 4. "PRELOAD,Value from ASIC for bs_preload (RU - read-only volatile)" "0,1" newline bitfld.word 0x0 3. "UPDATE_DR,Value from ASIC for bs_update_dr (RU - read-only volatile)" "0,1" newline bitfld.word 0x0 2. "CAPTURE_DR,Value from ASIC for bs_capture_dr (RU - read-only volatile)" "0,1" newline bitfld.word 0x0 1. "SHIFT_DR,Value from ASIC for bs_shift_dr (RU - read-only volatile)" "0,1" newline bitfld.word 0x0 0. "IN,Value from ASIC for bs_in (RU - read-only volatile)" "0,1" rgroup.word 0x8064++0x1 line.word 0x0 "SUPX_DIG_LEVEL_ASIC_IN,Current values for incoming los/acjt level. MPLL half rate mode and vreg bypass from ASIC" newline bitfld.word 0x0 15. "RESERVED_15_15,Reserved for Future use" "0,1" newline bitfld.word 0x0 12.--14. "LOS_BIAS,Value from ASIC for los_bias (RU - read-only volatile)" "0,1,2,3,4,5,6,7" newline bitfld.word 0x0 11. "MPLL_HALF_RATE,Value from ASIC for mpll_half_rate (RU - read-only volatile)" "0,1" newline bitfld.word 0x0 10. "VREG_BYPASS,Value from ASIC for vreg_bypass (RU - read-only volatile)" "0,1" newline hexmask.word.byte 0x0 5.--9. 1. "ACJT_LEVEL,Value from ASIC for acjt_level (RU - read-only volatile)" newline hexmask.word.byte 0x0 0.--4. 1. "LOS_LEVEL,Value from ASIC for los_level (RU - read-only volatile)" rgroup.word 0x8068++0x1 line.word 0x0 "SUPX_DIG_SSC_ASIC_IN,Current values for incoming SSC controls from ASIC" newline bitfld.word 0x0 15. "SS_EN,Value from ASIC for ssc_en (RU - read-only volatile)" "0,1" newline bitfld.word 0x0 12.--14. "SSC_RANGE,Value from ASIC for ssc_range (RU - read-only volatile)" "0,1,2,3,4,5,6,7" newline hexmask.word 0x0 3.--11. 1. "SSC_REF_CLK_SEL,Value from ASIC for ssc_ref_clk_sel (RU - read-only volatile)" newline bitfld.word 0x0 0.--2. "FSEL,Value from ASIC for fsel (RU - read-only volatile)" "0,1,2,3,4,5,6,7" rgroup.word 0x806C++0x1 line.word 0x0 "SUPX_DIG_SUP_ASIC_OUT,Current values for outgoing support block controls to ASIC" newline hexmask.word 0x0 5.--15. 1. "RESERVED_15_5,Reserved for Future use" newline bitfld.word 0x0 4. "MPLL_STATE,Value from PHY for mpll_state output (RU - read-only volatile)" "0,1" newline bitfld.word 0x0 3. "BS_OUT,Value from PHY for bs_out output (RU - read-only volatile)" "0,1" newline bitfld.word 0x0 2. "RTUNE_ACK,Value from PHY for rtune_ack output (RU - read-only volatile)" "0,1" newline bitfld.word 0x0 1. "RES_REQ_OUT,Value from PHY for res_req_out output (RU - read-only volatile)" "0,1" newline bitfld.word 0x0 0. "RES_ACK_OUT,Value from PHY for res_ack_out output (RU - read-only volatile)" "0,1" rgroup.word 0x8070++0x1 line.word 0x0 "SUPX_DIG_ATEOVRD_STATUS,USB3_SUPX_DIG_ATEOVRD_STATUS" newline hexmask.word.byte 0x0 10.--15. 1. "RESERVED_15_10,Reserved for Future use" newline bitfld.word 0x0 8.--9. "DTB_OUT,Value from dtb_out bus. (RU - read-only volatile)" "0,1,2,3" newline bitfld.word 0x0 7. "REF_SSP_EN,Value from ASIC for ref_ssp_en. (RU - read-only volatile)" "0,1" newline bitfld.word 0x0 6. "REF_USE_PAD,Value from ASIC for ref_use_pad. (RU - read-only volatile)" "0,1" newline bitfld.word 0x0 5. "PHY_RESET_IN,Value from ASIC for phy_reset (RU - read-only volatile)" "0,1" newline bitfld.word 0x0 4. "REF_CLKDIV2_IN,Value from ASIC for ref_clkdiv2 (RU - read-only volatile)" "0,1" newline bitfld.word 0x0 3. "REF_USB2_EN_IN,Value from ASIC for ref_usb2_en (RU - read-only volatile)" "0,1" newline bitfld.word 0x0 2. "ATEOVRD_EN,When set values from ATEOVRD register are being sent to PHY (RU - read-only volatile)" "0,1" newline bitfld.word 0x0 1. "REF_CLKDIV2_OUT,Value from ATEOVRD for ref_clkdiv2 (RU - read-only volatile)" "0,1" newline bitfld.word 0x0 0. "REF_USB2_EN_OUT,Value from ATEOVRD for ref_usb2_en (RU - read-only volatile)" "0,1" group.word 0x8074++0x1 line.word 0x0 "SUPX_DIG_HSP_OVRD_IN,Override values for HSP" newline hexmask.word 0x0 4.--15. 1. "RESERVED_15_4,Reserved for Future use" newline bitfld.word 0x0 3. "HSP_PLL_OVRD,Override enable for HSP pll_pu signal" "0,1" newline bitfld.word 0x0 2. "HSP_PLL_PU,Override value for HSP pll_pu signal" "0,1" newline bitfld.word 0x0 1. "HSP_BIAS_OVRD,Override enable for HSP bias_pu signal" "0,1" newline bitfld.word 0x0 0. "HSP_BIAS_PU,Override value for HSP bias_pu signal" "0,1" rgroup.word 0x8078++0x1 line.word 0x0 "SUPX_DIG_HSP_ASIC_IN,Current values for incoming HSP & REF XO controls from ASIC" newline hexmask.word 0x0 4.--15. 1. "RESERVED_15_4,Reserved for Future use" newline bitfld.word 0x0 3. "REF_USE_XO,Value from ASIC for ref_use_xo (RU - read-only volatile)" "0,1" newline bitfld.word 0x0 2. "REF_XO_EN,Value from ASIC for ref_xo_en (RU - read-only volatile)" "0,1" newline bitfld.word 0x0 1. "HSP_PLL_PU,Value from ASIC for hsp_pll_pu (RU - read-only volatile)" "0,1" newline bitfld.word 0x0 0. "HSP_BIAS_PU,Value from ASIC for hsp_bias_pu (RU - read-only volatile)" "0,1" group.word 0x8080++0x1 line.word 0x0 "SUPX_DIG_SCOPE_ENABLES,Scope Counter configuration" newline hexmask.word 0x0 5.--15. 1. "RESERVED_15_5,Reserved for Future use" newline bitfld.word 0x0 3.--4. "LANE_SELECT,Scope Counter Input select" "0,1,2,3" newline bitfld.word 0x0 2. "MASK_SATURATION_MODE,Method of mask saturation. When 1 Saturate when the first mask_counter reaches sample_limit. When 0 Saturate when all mask_counters have reached sample_limit." "0,1" newline bitfld.word 0x0 1. "MASK_EN,Enable scope_mask input for tracking count values. Clears registers when deasserted." "0,1" newline bitfld.word 0x0 0. "XOR_EN,Use scope_xor input for count values." "0,1" group.word 0x8084++0x1 line.word 0x0 "SUPX_DIG_SCOPE_SAMPLES,Number of samples to count" newline hexmask.word 0x0 0.--15. 1. "SAMPLES,Number of Sample to count." rgroup.word 0x8088++0x1 line.word 0x0 "SUPX_DIG_SCOPE_COUNT,Results of scope counting" newline hexmask.word 0x0 0.--15. 1. "COUNT,A write to this register will start the counting process The value of FFFF indicates counting still in progress. Asserting MASK_EN will also start the counting if in MASK mode. (RU - read-only volatile)" group.word 0x808C++0x1 line.word 0x0 "SUPX_DIG_SCOPE_CTL,Masked scope counting Start and Status" newline hexmask.word 0x0 2.--15. 1. "RESERVED_15_2,Reserved for Future use" newline bitfld.word 0x0 1. "MASK_START,A write to this register will start the counting process The value of FFFF indicates counting still in progress Write will trigger mask counting. (USER1 - read-write volatile)" "?,read-write volatile)" newline bitfld.word 0x0 0. "MASK_SATURATION,When assert mask registers have saturated. (USER1 - read-write volatile)" "?,read-write volatile)" repeat 8. (list 0x0 0x1 0xA 0xB 0x64 0x65 0x6E 0x6F )(list 0x0 0x4 0x8 0xC 0x10 0x14 0x18 0x1C ) group.word ($2+0x8090)++0x1 line.word 0x0 "SUPX_DIG_SCOPE_MASK_$1,Current count value for mask_000" newline hexmask.word 0x0 0.--15. 1. "MASK_VAL_000,Starting count value of mask register. (volatile and 2 reads needed to read value)" repeat.end group.word 0x80C0++0x1 line.word 0x0 "SUPX_ANA_MPLL_LOOP_CTL,MPLL loop control bits" newline hexmask.word.byte 0x0 8.--15. 1. "RESERVED_15_8,Reserved for Future use" newline hexmask.word.byte 0x0 4.--7. 1. "PROP_CNTRL,Charge pump proportional current setting" newline bitfld.word 0x0 2.--3. "INT_CNTRL,Charge pump integrating current setting" "0,1,2,3" newline bitfld.word 0x0 1. "GD,Measure MPLL local GD" "0,1" newline bitfld.word 0x0 0. "VMB,Measure MPLL Master Bias Voltage" "0,1" repeat 2. (list 0x1 0x2 )(list 0x0 0x4 ) group.word ($2+0x80C4)++0x1 line.word 0x0 "SUPX_ANA_MPLL_ATB_MEAS$1,ATB Select bits" newline hexmask.word.byte 0x0 8.--15. 1. "RESERVED_15_8,Reserved for Future use" newline bitfld.word 0x0 7. "VPSF,puts vpsf on atb_s_p" "0,1" newline bitfld.word 0x0 6. "VREF,puts vref from charge pump on atb_s_p" "0,1" newline bitfld.word 0x0 5. "VCNTRL,puts vcntrl on atb_s_m" "0,1" newline bitfld.word 0x0 4. "GD,puts gd on atb_s_m" "0,1" newline bitfld.word 0x0 3. "IVCO,puts VCO current/93 on atb_f_m" "0,1" newline bitfld.word 0x0 2. "VP,puts vpa on atb_s_m" "0,1" newline bitfld.word 0x0 1. "VP_CP,puts vp_cp on atb_s_p" "0,1" newline bitfld.word 0x0 0. "VREG_MPLL,puts vreg_mpll on atb_s_p" "0,1" repeat.end group.word 0x80CC++0x1 line.word 0x0 "SUPX_ANA_MPLL_OVRD,Local overrides" newline hexmask.word.byte 0x0 8.--15. 1. "RESERVED_15_8,Reserved for Future use" newline bitfld.word 0x0 7. "PWRON_LCL,local power_on value" "0,1" newline bitfld.word 0x0 6. "EN_PWRON_LCL,Enable local control of power_on" "0,1" newline bitfld.word 0x0 5. "GS_LCL,local gear_shift value" "0,1" newline bitfld.word 0x0 4. "EN_GS_LCL,Enable local control of gear_shift" "0,1" newline bitfld.word 0x0 3. "RST_LCL,local reset value" "0,1" newline bitfld.word 0x0 2. "EN_RST_LCL,enable local control of reset" "0,1" newline bitfld.word 0x0 1. "PMIX_CLK_SEL_LCL,local pmix_clk_sel value" "0,1" newline bitfld.word 0x0 0. "EN_PMIX_CLK_SEL_LCL,enable local control of pmix_clk_sel" "0,1" group.word 0x80D0++0x1 line.word 0x0 "SUPX_ANA_RTUNE_RTUNE_CTRL,RTUNE control bits" newline hexmask.word.byte 0x0 8.--15. 1. "RESERVED_15_8,Reserved for Future use" newline bitfld.word 0x0 7. "RT_PWRON_FRC_ON,When set forces RTUNE block to be on" "0,1" newline bitfld.word 0x0 6. "X4_FRC_OFF,When set do not multiply test current by 4" "0,1" newline bitfld.word 0x0 4.--5. "RT_DAC_MODE,Margin DAC mode control bits(00=powerdown 01=DAC drives atb_s_p/m directly 10=DAC drives atb_s_p/m to the RX in margining mode 11=illegal state)" "powerdown,DAC drives atb_s_p/m directly,?,?" newline bitfld.word 0x0 3. "RT_DAC_CHOP,Margin DAC chop control bit. ref to ssp analog engineering doc 8.5" "0,1" newline bitfld.word 0x0 2. "RT_ATB,RTUNE ATB mode control bit (1=RTUNE performs ADC on ATB input 0=not accessing ATB. refer to ssp analog engineering specification 8.1.4)" "not accessing ATB,RTUNE performs ADC on ATB input" newline bitfld.word 0x0 1. "RT_SEL_ATBP,RTUNE ATB sense input select bit (1=atb_s_p 0=atb_s_m)" "atb_s_m),atb_s_p" newline bitfld.word 0x0 0. "RT_SEL_ATBF,RTUNE ATB input select bit (1=atb_fm 0=atb_s_p/m)" "atb_s_p/m),atb_fm" group.word 0x80D4++0x1 line.word 0x0 "SUPX_ANA_ATB_SWITCHYARD_CTRL,ATB_SWITCHYARD control bits" newline hexmask.word.byte 0x0 8.--15. 1. "RESERVED_15_8,Reserved for Future use" newline bitfld.word 0x0 7. "ASM_GD,Connect gd to atb_s_m" "0,1" newline bitfld.word 0x0 6. "ASP_VP,Connect vp to atb_s_p" "0,1" newline bitfld.word 0x0 5. "ASP_VBG,Connect vbg to atb_s_p" "0,1" newline bitfld.word 0x0 4. "ASP_VPHREG,Connect vphreg to atb_s_m" "0,1" newline bitfld.word 0x0 3. "ATEST_AFM,drive ATEST from atb_f_m" "0,1" newline bitfld.word 0x0 2. "ATEST_AFP,drive ATEST from atb_f_p" "0,1" newline bitfld.word 0x0 1. "ATEST_ASM,Connet ATEST to atb_s_m" "0,1" newline bitfld.word 0x0 0. "ATEST_ASP,Connect ATEST to atb_s_p" "0,1" group.word 0x80D8++0x1 line.word 0x0 "SUPX_ANA_SSC_CLK_CNTRL,controls sscf reference clock rate" newline hexmask.word.byte 0x0 8.--15. 1. "RESERVED_15_8,Reserved for Future use" newline bitfld.word 0x0 7. "NC,Reserved" "0,1" newline hexmask.word.byte 0x0 0.--6. 1. "SSC_CLK_DIV125,set ssc reference clock to be 20MHz" group.word 0x80DC++0x1 line.word 0x0 "SUPX_ANA_HSP_CLK_DIG_CNTRL0,controls HSP phase clock. and resolution" newline hexmask.word.byte 0x0 8.--15. 1. "RESERVED_15_8,Reserved for Future use" newline bitfld.word 0x0 7. "NUM_OVERRIDE,Set the value to 1 to enable using values from creg bit 6 downto 0" "0,1" newline bitfld.word 0x0 4.--6. "GATE_PMIX_BITS,Set gate_pmix_bits to gate the corresponding MSB of the 7-bit PMIX phase select bits" "?,?,?,?,?,?,?,bit PMIX phase select bits" newline bitfld.word 0x0 3. "HALF_CLK_EN,Set to 1 for 1.25GHz updates to HSP PMIX. Set to 0 for 2.5GHz updates to PMIX." "0,1" newline bitfld.word 0x0 2. "UCLK_EN_N,Set to 1 to disable update clock. Set to 0 to enable update clock. When clock is enabled phase updates are allowed." "0,1" newline bitfld.word 0x0 1. "EN_HSPPMIX_VPMIX,Set to 1 to connect the regulated HSP PMIX supply to the atb_s_p bus" "0,1" newline bitfld.word 0x0 0. "EN_HSPPMIX_FRC_VPMIX,Set to 1 to force override of HSP PMIX regulator voltage to voltage on atb_s_m" "0,1" group.word 0x80E0++0x1 line.word 0x0 "SUPX_ANA_HSP_CLK_DIG_CNTRL1,Lower and Upper Phase Increment Values" newline hexmask.word.byte 0x0 8.--15. 1. "RESERVED_15_8,Reserved for Future use" newline hexmask.word.byte 0x0 4.--7. 1. "UPPER_INT,These bits are only used when num_override is set to 1. Upper integer for phase increments of 2.5 to 2.4 GHz conversion. This is the phase increment that is applied 6 times in every 25 for 1.25 GHz increments and 3 times in every 25 for 2.5GHz" newline hexmask.word.byte 0x0 0.--3. 1. "LOWER_INT,These bits are only used when num_override is set to 1. Lower integer for phase increments of 2.5 to 2.4 GHz conversion. This phase increment is applied 19 times in every 25 for 1.25 GHz increments and 22 times in every 25 for 2.5GHz." group.word 0x9000++0x1 line.word 0x0 "LANEX_DIG_TX_OVRD_IN_LO,Override values for incoming TX controls from ASIC" newline bitfld.word 0x0 15. "LANE_IF_WIDTH_OVRD,Override enable for lane interface width" "0,1" newline bitfld.word 0x0 14. "LANE_IF_WIDTH,Override value for lane interface width" "0,1" newline bitfld.word 0x0 13. "TX_DETECT_RX_REQ_OVRD,Override enable for tx_detect_rx_req" "0,1" newline bitfld.word 0x0 12. "TX_DETECT_RX_REQ,Override value for tx_detect_rx_req" "0,1" newline bitfld.word 0x0 11. "TX_BEACON_EN_OVRD,Override enable for tx_beacon_en" "0,1" newline bitfld.word 0x0 10. "TX_BEACON_EN,Override value for tx_beacon_en" "0,1" newline bitfld.word 0x0 9. "TX_CM_EN_OVRD,Override enable for tx_cm_en" "0,1" newline bitfld.word 0x0 8. "TX_CM_EN,Override value for tx_cm_en" "0,1" newline bitfld.word 0x0 7. "TX_EN_OVRD,Override enable for tx_en" "0,1" newline bitfld.word 0x0 6. "TX_EN,Override value for tx_en" "0,1" newline bitfld.word 0x0 5. "TX_DATA_EN_OVRD,Override enable for tx_data_en" "0,1" newline bitfld.word 0x0 4. "TX_DATA_EN,Override value for tx_data_en" "0,1" newline bitfld.word 0x0 3. "TX_INVERT_OVRD,Override enable for tx_invert" "0,1" newline bitfld.word 0x0 2. "TX_INVERT,Override value for tx_invert" "0,1" newline bitfld.word 0x0 1. "TX_LOOPBK_EN_OVRD,Override enable for loopbk_en" "0,1" newline bitfld.word 0x0 0. "LOOPBK_EN,Override value for loopbk_en" "0,1" group.word 0x9004++0x1 line.word 0x0 "LANEX_DIG_TX_OVRD_IN_HI,Override values for incoming TX controls from ASIC" newline hexmask.word.byte 0x0 10.--15. 1. "RESERVED_15_10,Reserved for Future use" newline bitfld.word 0x0 9. "TX_VBOOST_EN_OVRD,Override enable for tx_vboost_en" "0,1" newline bitfld.word 0x0 8. "TX_VBOOST_EN,Override value for tx_vboost_en" "0,1" newline bitfld.word 0x0 7. "TX_RESET_OVRD,Override enable for tx_reset" "0,1" newline bitfld.word 0x0 6. "TX_RESET,Override value for tx_reset" "0,1" newline bitfld.word 0x0 5. "TX_NYQUIST_DATA,Override incoming data to nyquist" "0,1" newline bitfld.word 0x0 4. "TX_CLK_OUT_EN_OVRD,Override enable for tx_clk_out_en." "0,1" newline bitfld.word 0x0 3. "TX_CLK_OUT_EN,Override incomming tx_clk_out_en." "0,1" newline bitfld.word 0x0 2. "TX_RATE_OVRD,Override enable for tx_rate." "0,1" newline bitfld.word 0x0 0.--1. "TX_RATE,Override incomming tx lane rate." "0,1,2,3" group.word 0x9008++0x1 line.word 0x0 "LANEX_DIG_TX_OVRD_DRV_LO,Override values for incoming TX drive controls from ASIC" newline rbitfld.word 0x0 15. "RESERVED_15_15,Reserved for Future use" "0,1" newline bitfld.word 0x0 14. "EN,Enable override values for all inputs controlled by this register" "0,1" newline hexmask.word.byte 0x0 7.--13. 1. "PREEMPH,Override value for transmit preemphasis." newline hexmask.word.byte 0x0 0.--6. 1. "AMPLITUDE,Override value for transmit amplitude." group.word 0x900C++0x1 line.word 0x0 "LANEX_DIG_TX_OVRD_DRV_HI,Override values for incoming TX drive controls from ASIC" newline hexmask.word 0x0 6.--15. 1. "RESERVED_15_6,Reserved for Future use" newline bitfld.word 0x0 5. "EN,Enable override values for all inputs controlled by this register" "0,1" newline hexmask.word.byte 0x0 0.--4. 1. "TERM_OFFSET,Override value for tx_term_offset (tx_ana_vcmref_boost)" group.word 0x9010++0x1 line.word 0x0 "LANEX_DIG_TX_OVRD_OUT,Override values for outgoing TX controls to ASIC" newline hexmask.word.byte 0x0 8.--15. 1. "RESERVED_15_8,Reserved for Future use" newline bitfld.word 0x0 7. "TX_STATE_OVRD,Override enable for tx_state" "0,1" newline bitfld.word 0x0 6. "TX_STATE,Override value for tx_state" "0,1" newline bitfld.word 0x0 5. "TX_CM_STATE_OVRD,Override enable for tx_cm_state" "0,1" newline bitfld.word 0x0 4. "TX_CM_STATE,Override value for tx_cm_state" "0,1" newline bitfld.word 0x0 3. "TX_DETECT_RX_ACK_OVRD,Override enable for tx_detect_rx_ack" "0,1" newline bitfld.word 0x0 2. "TX_DETECT_RX_ACK,Override value for tx_detect_rx_ack" "0,1" newline bitfld.word 0x0 1. "DETECT_RX_RES_OVRD,Override enable for tx_detect_rx_res" "0,1" newline bitfld.word 0x0 0. "DETECT_RX_RES,Override value for tx_detect_rx_res" "0,1" group.word 0x9014++0x1 line.word 0x0 "LANEX_DIG_RX_OVRD_IN_LO,Override values for incoming RX controls from ASIC" newline rbitfld.word 0x0 14.--15. "RESERVED_15_14,Reserved for Future use" "0,1,2,3" newline bitfld.word 0x0 13. "RX_LOS_EN_OVRD,Override enable for rx_los_en" "0,1" newline bitfld.word 0x0 12. "RX_LOS_EN,Override value for rx_los_en" "0,1" newline bitfld.word 0x0 11. "RX_TERM_EN_OVRD,Override enable for rx_term_en" "0,1" newline bitfld.word 0x0 10. "RX_TERM_EN,Override value for rx_term_en" "0,1" newline bitfld.word 0x0 9. "RX_BIT_SHIFT_OVRD,Override enable for rx_bit_shift" "0,1" newline bitfld.word 0x0 8. "RX_BIT_SHIFT,Override value for rx_bit_shift" "0,1" newline bitfld.word 0x0 7. "RX_ALIGN_EN_OVRD,Override enable for rx_align_en" "0,1" newline bitfld.word 0x0 6. "RX_ALIGN_EN,Override value for rx_align_en" "0,1" newline bitfld.word 0x0 5. "RX_DATA_EN_OVRD,Override enable for rx_data_en" "0,1" newline bitfld.word 0x0 4. "RX_DATA_EN,Override value for rx_data_en" "0,1" newline bitfld.word 0x0 3. "RX_PLL_EN_OVRD,Override enable for rx_pll_en" "0,1" newline bitfld.word 0x0 2. "RX_PLL_EN,Override value for rx_pll_en" "0,1" newline bitfld.word 0x0 1. "RX_INVERT_OVRD,Override enable for rx_invert" "0,1" newline bitfld.word 0x0 0. "RX_INVERT,Override value for rx_invert" "0,1" group.word 0x9018++0x1 line.word 0x0 "LANEX_DIG_RX_OVRD_IN_HI,Override values for incoming RX controls from ASIC" newline rbitfld.word 0x0 14.--15. "RESERVED_15_14,Reserved for Future use" "0,1,2,3" newline bitfld.word 0x0 13. "RX_RESET_OVRD,Override enable for rx_reset" "0,1" newline bitfld.word 0x0 12. "RX_RESET,Override value for rx_reset" "0,1" newline bitfld.word 0x0 11. "RX_EQ_OVRD,Override enable for rx_eq" "0,1" newline bitfld.word 0x0 8.--10. "RX_EQ,Override value for rx_eq" "0,1,2,3,4,5,6,7" newline bitfld.word 0x0 7. "RX_EQ_EN_OVRD,Override enable for rx_eq_en" "0,1" newline bitfld.word 0x0 6. "RX_EQ_EN,Override value for rx_eq_en" "0,1" newline bitfld.word 0x0 5. "RX_LOS_FILTER_OVRD,Override enable for rx_los_filter" "0,1" newline bitfld.word 0x0 3.--4. "RX_LOS_FILTER,Override value for rx_los_filter" "0,1,2,3" newline bitfld.word 0x0 2. "RX_RATE_OVRD,Override enable for rx_rate" "0,1" newline bitfld.word 0x0 0.--1. "RX_RATE,Override value for rx_rate" "0,1,2,3" group.word 0x901C++0x1 line.word 0x0 "LANEX_DIG_RX_OVRD_OUT,Override values for outgoing RX controls to ASIC" newline hexmask.word 0x0 7.--15. 1. "RESERVED_15_7,Reserved for Future use" newline bitfld.word 0x0 6. "ZERO_DATA,Override data output to all zeros" "0,1" newline bitfld.word 0x0 5. "LOS_OVRD,Override value for rx_los" "0,1" newline bitfld.word 0x0 4. "LOS,Override value for rx_los" "0,1" newline bitfld.word 0x0 3. "PLL_STATE_OVRD,Override enable for rx_pll_state" "0,1" newline bitfld.word 0x0 2. "PLL_STATE,Override value for rx_pll_state" "0,1" newline bitfld.word 0x0 1. "VALID_OVRD,Override enable for rx_valid" "0,1" newline bitfld.word 0x0 0. "VALID,Override value for rx_valid" "0,1" rgroup.word 0x9020++0x1 line.word 0x0 "LANEX_DIG_TX_ASIC_IN,Current values for incoming TX controls from ASIC" newline bitfld.word 0x0 14.--15. "RESERVED_15_14,Reserved for Future use" "0,1,2,3" newline bitfld.word 0x0 13. "LANE_IF_WIDTH,Value from ASIC for lane_if_width (RU - read-only volatile)" "0,1" newline bitfld.word 0x0 12. "DATA_EN_S,Value from ASIC for tx_data_en_s (RU - read-only volatile)" "0,1" newline bitfld.word 0x0 11. "TX_VBOOST_EN,Value from ASIC for tx_vboost_en (RU - read-only volatile)" "0,1" newline bitfld.word 0x0 10. "TX_CLK_OUT_EN,Value from ASIC for tx_clk_out_en (RU - read-only volatile)" "0,1" newline bitfld.word 0x0 9. "DETECT_RX_REQ,Value from ASIC for tx_detect_rx_req (RU - read-only volatile)" "0,1" newline bitfld.word 0x0 8. "BEACON_EN,Value from ASIC for tx_beacon_en (RU - read-only volatile)" "0,1" newline bitfld.word 0x0 7. "CM_EN,Value from ASIC for tx_cm_en (RU - read-only volatile)" "0,1" newline bitfld.word 0x0 6. "TX_EN,Value from ASIC for tx_en (RU - read-only volatile)" "0,1" newline bitfld.word 0x0 5. "DATA_EN,Value from ASIC for tx_data_en (RU - read-only volatile)" "0,1" newline bitfld.word 0x0 4. "TX_RESET,Value from ASIC for tx_reset (RU - read-only volatile)" "0,1" newline bitfld.word 0x0 3. "INVERT,Value from ASIC for tx_invert (RU - read-only volatile)" "0,1" newline bitfld.word 0x0 2. "LOOPBK_EN,Value from ASIC for loopbk_en (RU - read-only volatile)" "0,1" newline bitfld.word 0x0 0.--1. "TX_RATE,Value from ASIC for tx_rate (RU - read-only volatile)" "0,1,2,3" rgroup.word 0x9024++0x1 line.word 0x0 "LANEX_DIG_TX_ASIC_DRV_LO,Current values for incoming TX level controls from ASIC" newline bitfld.word 0x0 14.--15. "RESERVED_15_14,Reserved for Future use" "0,1,2,3" newline hexmask.word.byte 0x0 7.--13. 1. "PREEMPH,Value from ASIC for tx_preemph (RU - read-only volatile)" newline hexmask.word.byte 0x0 0.--6. 1. "AMPLITUDE,Value from ASIC for tx_amplitude (RU - read-only volatile)" rgroup.word 0x9028++0x1 line.word 0x0 "LANEX_DIG_TX_ASIC_DRV_HI,Current values for incoming TX level controls from ASIC" newline hexmask.word 0x0 5.--15. 1. "RESERVED_15_5,Reserved for Future use" newline hexmask.word.byte 0x0 0.--4. 1. "TERM_OFFSET,Value from ASIC for tx_term_offset (RU - read-only volatile)" rgroup.word 0x902C++0x1 line.word 0x0 "LANEX_DIG_TX_ASIC_OUT,Current values for outgoing TX status controls from PHY" newline hexmask.word 0x0 5.--15. 1. "RESERVED_15_5,Reserved for Future use" newline bitfld.word 0x0 4. "STATE,Value from PHY for tx_state (RU - read-only volatile)" "0,1" newline bitfld.word 0x0 3. "CM_STATE,Value from PHY for tx_cm_state (RU - read-only volatile)" "0,1" newline bitfld.word 0x0 2. "DETECT_RX_ACK,Value from PHY for tx_detect_rx_ack (RU - read-only volatile)" "0,1" newline bitfld.word 0x0 1. "RESERVED,Always returns 0 (RU - read-only volatile)" "0,1" newline bitfld.word 0x0 0. "DETECT_RX_RES,Value from PHY for tx_detect_rx_res (RU - read-only volatile)" "0,1" rgroup.word 0x9030++0x1 line.word 0x0 "LANEX_DIG_RX_ASIC_IN,Current values for incoming RX controls from ASIC" newline bitfld.word 0x0 15. "RX_EQ_EN,Value from ASIC for rx_eq_en (RU - read-only volatile)" "0,1" newline bitfld.word 0x0 12.--14. "RX_EQ,Value from ASIC for rx_eq (RU - read-only volatile)" "0,1,2,3,4,5,6,7" newline bitfld.word 0x0 10.--11. "LOS_FILTER,Value from ASIC for rx_los_filter (RU - read-only volatile)" "0,1,2,3" newline bitfld.word 0x0 9. "LOS_EN,Value from ASIC for rx_los_en (RU - read-only volatile)" "0,1" newline bitfld.word 0x0 8. "TERM_EN,Value from ASIC for rx_term_en (RU - read-only volatile)" "0,1" newline bitfld.word 0x0 7. "CLK_SHIFT,Value from ASIC for rx_bit_shift (RU - read-only volatile)" "0,1" newline bitfld.word 0x0 6. "ALIGN_EN,Value from ASIC for rx_align_en (RU - read-only volatile)" "0,1" newline bitfld.word 0x0 5. "DATA_EN,Value from ASIC for rx_data_en (RU - read-only volatile)" "0,1" newline bitfld.word 0x0 4. "PLL_EN,Value from ASIC for rx_pll_en (RU - read-only volatile)" "0,1" newline bitfld.word 0x0 3. "RX_RESET,Value from ASIC for rx_reset (RU - read-only volatile)" "0,1" newline bitfld.word 0x0 2. "INVERT,Value from ASIC for rx_invert (RU - read-only volatile)" "0,1" newline bitfld.word 0x0 0.--1. "RX_RATE,Value from ASIC for rx_rate (RU - read-only volatile)" "0,1,2,3" rgroup.word 0x9034++0x1 line.word 0x0 "LANEX_DIG_RX_ASIC_OUT,Current values for outgoing RX status controls from PHY" newline hexmask.word 0x0 3.--15. 1. "RESERVED_15_3,Reserved for Future use" newline bitfld.word 0x0 2. "LOS,Value from PHY for rx_los (RU - read-only volatile)" "0,1" newline bitfld.word 0x0 1. "PLL_STATE,Value from PHY for rx_pll_state (RU - read-only volatile)" "0,1" newline bitfld.word 0x0 0. "VALID,Value from PHY for rx_valid (RU - read-only volatile)" "0,1" group.word 0x9040++0x1 line.word 0x0 "LANEX_DIG_TX_DEBUG,Transmit debug controls" newline rbitfld.word 0x0 13.--15. "RESERVED_15_13,Reserved for Future use" "0,1,2,3,4,5,6,7" newline bitfld.word 0x0 12. "KEEP_TX_REFGEN,Keep TX voltage regulator ON until TX clocks are OFF" "0,1" newline hexmask.word.byte 0x0 4.--11. 1. "RXDET_MEAS_TIME,Time to wait for rxdet measurement (* 4/2/1 refclk cycles based on multiplier)" newline bitfld.word 0x0 3. "DETECT_RX_ALWAYS,Always signal 1 for rx_detect ignoring analog" "0,1" newline bitfld.word 0x0 0.--2. "DTB_SEL,Selects data to drive on DTB 0 - disabled 1 - mag_update/sub signals 2 - mag_high/add signals 3 - clock aligner early/shift signals 4 - analog/asic clocks 5 - tx_state counter/lbert strobe 6 - noclk_ref_rst/dig_rst 7 -.." "disabled,mag_update/sub signals,mag_high/add signals,clock aligner early/shift signals,analog/asic clocks,tx_state counter/lbert strobe,noclk_ref_rst/dig_rst,tx_ana_rxdetp_high/tx_ana_rxdetm_high" group.word 0x9044++0x1 line.word 0x0 "LANEX_DIG_TX_CM_WAIT_TIME_OVRD,USB3_LANEX_DIG_TX_CM_WAIT_TIME_OVRD" newline hexmask.word.byte 0x0 11.--15. 1. "RESERVED_15_11,Reserved for Future use" newline bitfld.word 0x0 10. "CM_TIME_OVRD_EN,Override enable for common mode charging wait time." "0,1" newline hexmask.word 0x0 0.--9. 1. "CM_TIME_OVRD,Time to wait in ref clock cycles for LFPS common mode charging (This value x32 is used for VCMHOLD charging method)" rgroup.word 0x9048++0x1 line.word 0x0 "LANEX_DIG_TX_VMD_FSM_TX_VCM_0,Calculated values for N_USE and N_TRISTATE. Also TX ANA configuration shift register output." newline bitfld.word 0x0 15. "SHIFT_OUT,Current value from TX_ANAs configuration shift register. (RU - read-only volatile)" "0,1" newline bitfld.word 0x0 14. "DONE,Configuration is done (RU - read-only volatile)" "0,1" newline hexmask.word.byte 0x0 7.--13. 1. "N_USE,Value from VMD for legs to use. (RU - read-only volatile)" newline hexmask.word.byte 0x0 0.--6. 1. "N_TRISTATE,Value from VMD for number of tristate legs. (RU - read-only volatile)" rgroup.word 0x904C++0x1 line.word 0x0 "LANEX_DIG_TX_VMD_FSM_TX_VCM_1,Calculated values for N_FIXED and N_TRAILER." newline bitfld.word 0x0 15. "FIXED_DONE,N_FIXED Multiplication has completed. (RU - read-only volatile)" "0,1" newline bitfld.word 0x0 14. "TRA_DONE,N_TRAILER Multiplication has completed. (RU - read-only volatile)" "0,1" newline hexmask.word.byte 0x0 7.--13. 1. "N_FIXED,Value from VMD for number of fixed driver legs. (RU - read-only volatile)" newline hexmask.word.byte 0x0 0.--6. 1. "N_TRAILER,Value from VMD for number of trailer legs. (RU - read-only volatile)" group.word 0x9050++0x1 line.word 0x0 "LANEX_DIG_TX_VMD_FSM_TX_VCM_DEBUG_IN,Access the TX_ANA VMD Control Shift Register" newline hexmask.word 0x0 4.--15. 1. "RESERVED_15_4,Reserved for Future use" newline bitfld.word 0x0 3. "CONFIG_OVRD,Override the Voltage Mode Driver Configuration FSM and access the shift chain directly. (volatile and 2 reads needed to read value)" "0,1" newline bitfld.word 0x0 2. "CONFIG_LOAD,Override value for the Voltage Mode Driver Configuration FSM's config load. (volatile and 2 reads needed to read value)" "0,1" newline bitfld.word 0x0 1. "CONFIG_CLK,Override value for the Voltage Mode Driver Configuration FSM's config clk. (volatile and 2 reads needed to read value)" "0,1" newline bitfld.word 0x0 0. "CONFIG_DATA,Override value for the Voltage Mode Driver Configuration FSM's config data. (volatile and 2 reads needed to read value)" "0,1" group.word 0x9054++0x1 line.word 0x0 "LANEX_DIG_TX_LBERT_CTL,Pattern Generator controls" newline rbitfld.word 0x0 15. "RESERVED_15_15,Reserved for Future use" "0,1" newline hexmask.word 0x0 5.--14. 1. "PAT0,10 bit pattern for modes using PAT0 (5-7). Ignored for other MODEs." newline bitfld.word 0x0 4. "TRIGGER_ERR,Single shot inversion the LSB of the current symbol. Any write of a 1 to this bit will insert an error. Maintain mode and pattern from setup." "0,1" newline hexmask.word.byte 0x0 0.--3. 1. "MODE,Pattern to generate When changing modes you must change to disabled first 0 - disabled 1 - lfsr31. X^31 + X^28 + 1 2 - lfsr23. X^23 + X^18 + 1 3 - lfsr15. X^15 + X^14 + 1 4 - lfsr7. X^7 + X^6 + 1 5 - fixed word (PAT0) 6 - DC balanced word (PAT0.." group.word 0x9058++0x1 line.word 0x0 "LANEX_DIG_RX_LBERT_CTL,Pattern Matcher controls" newline hexmask.word 0x0 5.--15. 1. "RESERVED_15_5,Reserved for Future use" newline bitfld.word 0x0 4. "SYNC,Synchronize pattern matcher with incoming data A write of a one to this bit will reset the error counter and start a synchronization of the PM. There is no need to write this back to zero to run normally." "0,1" newline hexmask.word.byte 0x0 0.--3. 1. "MODE,Pattern to match When changing modes you must change to disabled first 0 - disabled 1 - lfsr31: X^31 + X^28 + 1 2 - lfsr23: X^23 + X^18 + 1 3 - lfsr15: X^15 + X^14 + 1 4 - lfsr7 : X^7 + X^6 + 1 5 - d[n] = d[n-10] 6 - d[n] = !d[n-10] 7 - d[n] =.." group.word 0x905C++0x1 line.word 0x0 "LANEX_DIG_RX_LBERT_ERR,Pattern match error counter" newline bitfld.word 0x0 15. "OV14,A read of this register or a sync of the Pattern Matcher resets the error count. If all bits of this register are 1 the error counter has saturated. If the status If active multiply COUNT by 128. If OV14=1 and COUNT=2^15-1 signals overflow of.." "0,1" newline hexmask.word 0x0 0.--14. 1. "COUNT,Current error count If OV14 field is active then multiply count by 128 to get the actual count. (volatile and 2 reads needed to read value)" group.word 0x9060++0x1 line.word 0x0 "LANEX_DIG_RX_SCOPE_CTL,Control bits for per-transciever scope portion" newline rbitfld.word 0x0 14.--15. "RESERVED_15_14,Reserved for Future use" "0,1,2,3" newline bitfld.word 0x0 12.--13. "RX_VALID_CTL,When to Start Sampling control based on rx_valid. 0 = Ignore rx_valid. 1 = Heed rx_valid. 2 = Wait for rising_edge on rx_valid." "Ignore rx_valid,Heed rx_valid,Wait for rising_edge on rx_valid,?" newline hexmask.word 0x0 3.--11. 1. "DELAY,number of cycles to skip between samples" newline bitfld.word 0x0 0.--2. "MODE,sampling mode of counters NOTE: WORD is 20 bits. 0 = off 1 = sample data every WORD*(1+DELAY) bits from the digital recovered path. 2 = sample data every WORD*(1+DELAY) + 1 bits from the digital recovered path. 3 = sample data every WORD*(1+DELAY) +.." "off,sample data every WORD*,sample data every WORD*,sample data every WORD*,sample data every WORD*,?,?,?" group.word 0x9064++0x1 line.word 0x0 "LANEX_DIG_RX_SCOPE_PHASE,Scope sampling phase." newline rbitfld.word 0x0 15. "RESERVED_15_15,Reserved for Future use" "0,1" newline hexmask.word.byte 0x0 10.--14. 1. "BASE,which bit to sample when MODE = 1 or 4" newline bitfld.word 0x0 8.--9. "SCOPE_DELAY,How many clocks to delay the analog scope_data." "0,1,2,3" newline bitfld.word 0x0 7. "SCOPE_SEL,Select Sampling Mode. 0 - Before AFE Sampling 1 - After AFE Sampling" "Before AFE Sampling,After AFE Sampling" newline bitfld.word 0x0 6. "UPDATE,Update Sampling phase. Write a 1." "0,1" newline hexmask.word.byte 0x0 0.--5. 1. "SAMPLE_PHASE,Sampling Phase" group.word 0x9068++0x1 line.word 0x0 "LANEX_DIG_RX_DPLL_FREQ,Current frequency integrator value." newline rbitfld.word 0x0 13.--15. "RESERVED_15_13,Reserved for Future use" "0,1,2,3,4,5,6,7" newline hexmask.word 0x0 1.--12. 1. "VAL,Freq is 1.526*VAL ppm from the reference When mpll_slow is set the ppm is half the eqn above (volatile and 2 reads needed to read value)" newline bitfld.word 0x0 0. "DTHR,Bits below the useful resolution (volatile and 2 reads needed to read value)" "0,1" group.word 0x906C++0x1 line.word 0x0 "LANEX_DIG_RX_CDR_CTL,Control bits for receiver in recovered domain" newline hexmask.word.byte 0x0 12.--15. 1. "DTB_SEL,select to drive various signals onto the dtb 0 - disabled 1 - pll_ana_rst pll_count from rx_pwr_ctl 2 - com_good_high/low from aligner 3 - com_bad_high/low from aligner 4 - shift_in_prog ana_odd_data from aligner 5 - low bits of XAUI align FSM.." newline bitfld.word 0x0 11. "ALWAYS_REALIGN,realign on any misaligned comma" "0,1" newline bitfld.word 0x0 10. "FAST_START,decrease startup steps by 50%" "0,1" newline bitfld.word 0x0 8.--9. "FRUG_VALUE,override value for FRUG" "0,1,2,3" newline bitfld.word 0x0 6.--7. "PHUG_VALUE,override value for PHUG" "0,1,2,3" newline bitfld.word 0x0 5. "OVRD_DPLL_GAIN,Override PHUG and FRUG values" "0,1" newline bitfld.word 0x0 4. "PHDET_POL,Reverse polarity of phase error" "0,1" newline bitfld.word 0x0 2.--3. "PHDET_EDGE,Edges to use for phase detection. 11 - Use both edges 10 - Use rising edges only 01 - Use falling edges only 00 - Ignore all edges" "Ignore all edges,Use falling edges only,?,?" newline bitfld.word 0x0 0.--1. "PHDET_EN,Enable phase detecter. top bit is odd slicers bottom is even" "0,1,2,3" rgroup.word 0x9070++0x1 line.word 0x0 "LANEX_DIG_RX_CDR_CDR_FSM_DEBUG,Current values for CDR and Adaptation FSM." newline bitfld.word 0x0 13.--15. "ADAP_RX_EQ,Equalization setting from adaptation FSM. (RU - read-only volatile)" "0,1,2,3,4,5,6,7" newline bitfld.word 0x0 10.--12. "RX_EQ_CTR,Initial centre point from equalization FSM. (RU - read-only volatile)" "0,1,2,3,4,5,6,7" newline bitfld.word 0x0 7.--9. "RX_ANA_EQ,Equalization setting to Analog. (RU - read-only volatile)" "0,1,2,3,4,5,6,7" newline bitfld.word 0x0 6. "ADAP_RX_VALID,Adaptation has completed and locked. (RU - read-only volatile)" "0,1" newline bitfld.word 0x0 5. "CDR_EN_ADAP,Adapatation loop is enabling the CDR. (RU - read-only volatile)" "0,1" newline bitfld.word 0x0 4. "CDR_EN_EQ,Equalization loop is enabling the CDR. (RU - read-only volatile)" "0,1" newline bitfld.word 0x0 3. "ALIGNED,Datapath is bit-aligned. (RU - read-only volatile)" "0,1" newline bitfld.word 0x0 2. "CDR_RX_VALID,CDR has locked to incoming data stream. (RU - read-only volatile)" "0,1" newline bitfld.word 0x0 1. "CDR_TIMEOUT,CDR has not locked to datastream and has timed-out. (RU - read-only volatile)" "0,1" newline bitfld.word 0x0 0. "CDR_EN,CDR has been enabled. (RU - read-only volatile)" "0,1" group.word 0x9074++0x1 line.word 0x0 "LANEX_DIG_RX_CDR_LOCK_VEC_OVRD,Control bits for receiver in recovered domain" newline hexmask.word.byte 0x0 11.--15. 1. "ADAP_CTR_LEVEL,Ammount of earlies that increment the adaptation counter (times 32 Default is 512). (volatile and 2 reads needed to read value)" newline bitfld.word 0x0 10. "ADAP_POLARITY,If asserted invert default adaptation adjustment for equalization. IF early decrease equalization. Normal mode is to decrease. (volatile and 2 reads needed to read value)" "0,1" newline bitfld.word 0x0 9. "LOCK_VECTOR_OVRD,Override enable for the rx_eq outputs. (volatile and 2 reads needed to read value)" "0,1" newline bitfld.word 0x0 8. "LOCK_VECTOR_EN,Override value for the locked_vector output completion. (volatile and 2 reads needed to read value)" "0,1" newline hexmask.word.byte 0x0 0.--7. 1. "LOCK_VECTOR,Override value for the locked_vector. (volatile and 2 reads needed to read value)" rgroup.word 0x9078++0x1 line.word 0x0 "LANEX_DIG_RX_CDR_LOCK_VEC,Current values for the locked vector.." newline hexmask.word.byte 0x0 12.--15. 1. "RESERVED_15_12,Reserved for Future use" newline bitfld.word 0x0 9.--11. "EQ_RX_EQ,Equalization setting from the Equalization Loop. (RU - read-only volatile)" "0,1,2,3,4,5,6,7" newline bitfld.word 0x0 8. "EQ_LOCKED_VECTOR_EN,Equalization locked vector has been filled. (RU - read-only volatile)" "0,1" newline hexmask.word.byte 0x0 0.--7. 1. "EQ_LOCKED_VECTOR,Results of equalization loop. (RU - read-only volatile)" rgroup.word 0x907C++0x1 line.word 0x0 "LANEX_DIG_RX_CDR_ADAP_FSM,Observation of adaptation FSM register." newline hexmask.word.byte 0x0 11.--15. 1. "MSTR_CTR,Master count register. (RU - read-only volatile)" newline hexmask.word.byte 0x0 7.--10. 1. "LOOP_CTR,Loop count register. (RU - read-only volatile)" newline hexmask.word.byte 0x0 3.--6. 1. "ADAP_CTR,Adaptation count register. (RU - read-only volatile)" newline bitfld.word 0x0 0.--2. "ADAP_STATE,Adaptation State. NOTE: ADAP_RESET = 3'b000 ADAP_LOCK = 3'b001 ADAP_SUFF = 3'b010 ADAP_LOOP = 3'b011 ADAP_MSTR = 3'b100 ADAP_DONE = 3'b101 (RU - read-only volatile)" "0,1,2,3,4,5,6,7" group.word 0x9080++0x1 line.word 0x0 "LANEX_ANA_RX_ATB0,ATB Control Register" newline hexmask.word.byte 0x0 8.--15. 1. "RESERVED_15_8,Reserved for Future use" newline bitfld.word 0x0 7. "EN_ATB,Enable ATB sensing and forcing on internal RX nodes" "0,1" newline bitfld.word 0x0 6. "EN_MARG,Enable margining mode in receiver; it puts EQ common mode output on atb_f_m" "0,1" newline bitfld.word 0x0 5. "EN_ATB_RM_F,Enable atb_f_p on negative-side termination resistor" "0,1" newline bitfld.word 0x0 4. "EN_ATB_RM_S,Enable atb_s_m on negative-side termination resistor" "0,1" newline bitfld.word 0x0 3. "EN_ATB_RP_F,Enable atb_f_p on positive-side termination resistor" "0,1" newline bitfld.word 0x0 2. "EN_ATB_RP_S,Enable atb_s_p on positive-side termination resistor" "0,1" newline bitfld.word 0x0 1. "EN_ATB_VOS,Put rxafe filtered outputs vo_p on atb_s_p and vo_m on atb_s_m" "0,1" newline bitfld.word 0x0 0. "EN_ATB_VOFF,Put rxafe voff_p on atb_s_p and voff_m on atb_s_m" "0,1" group.word 0x9084++0x1 line.word 0x0 "LANEX_ANA_RX_ATB1,ATB and Misc Control Register" newline hexmask.word.byte 0x0 8.--15. 1. "RESERVED_15_8,Reserved for Future use" newline bitfld.word 0x0 6.--7. "RX_DCC_IQ_OFFSET_H_4_3,Code which helps to manually tune reference voltage (r-string dac) for IQ opamp and correct input offset (rx_dcc_iq_offset_h_4_3 bit)" "0,1,2,3" newline bitfld.word 0x0 5. "EN_ATB_VLOS,Enable sensing of LOS reference voltage on atb_s_p" "0,1" newline bitfld.word 0x0 4. "EN_ATB_VRF,Enable sensing of vref_rx (RX Bias B.G. Voltage) on atb_s_p" "0,1" newline bitfld.word 0x0 3. "MEAS_GD,Enable sensing of local gd in RX; ties gd to atb_s_m" "0,1" newline bitfld.word 0x0 2. "MEAS_VP,Enable sensing of local vp in RX; ties vp to atb_s_p" "0,1" newline bitfld.word 0x0 0.--1. "RX_DCC_IQ_OFFSET_H_2_1,Code which helps to manually tune reference voltage (r-string dac) for IQ opamp and correct input offset (rx_dcc_iq_offset_h_2_1 bit)" "0,1,2,3" group.word 0x9088++0x1 line.word 0x0 "LANEX_ANA_RX_ENPWR0,RX State Control Register" newline hexmask.word.byte 0x0 8.--15. 1. "RESERVED_15_8,Reserved for Future use" newline bitfld.word 0x0 7. "CTL_RXPWRON,MUX select for AFE en to select between CTL_RXPWRON=0 rx_afe_en (External signal) or CTL_RXPWRON=1 LCL_RXPWRON" "0,1" newline bitfld.word 0x0 6. "LCL_RXPWRON,Enable/Disable RX AFE .This bit is only selected when CTL_RXPWRON = 1" "0,1" newline bitfld.word 0x0 5. "CTL_EN_LOS,MUX select for LOS en to select between CTL_EN_LOS=0 rx_los_en (External signal) or CTL_EN_LOS=1 LCL_EN_LOS" "0,1" newline bitfld.word 0x0 4. "LCL_EN_LOS,Enable/Disable LOS.This bit is only selected when CTL_EN_LOS = 1" "0,1" newline bitfld.word 0x0 3. "CTL_RXCK,MUX select for RX Clock en to select between CTL_RXCK=0 rx_clock_en (External signal) or CTL_RXCK=1 LCL_RXCK." "0,1" newline bitfld.word 0x0 2. "LCL_RXCK,Enable/Disable en_rx_clock (RX clock enable).This bit is only selected when CTL_RXCK = 1" "0,1" newline bitfld.word 0x0 1. "CTL_ACJT,MUX select for ACJTAG to select between CTL_ACJTG=0 rx_acjtg_en (External signal) or CTL_ACJTG=1 LCL_ACJT." "0,1" newline bitfld.word 0x0 0. "LCL_ACJT,Enable/Disable acjtag block This bit is only selected when CTL_ACJTG = 1" "0,1" group.word 0x908C++0x1 line.word 0x0 "LANEX_ANA_RX_PMIX_PHASE,Phase select Value" newline hexmask.word.byte 0x0 8.--15. 1. "RESERVED_15_8,Reserved for Future use" newline hexmask.word.byte 0x0 0.--7. 1. "PHASE,Write to bits 8 to 1 of the phase select register in the phase mixer through the CDR (USER2 volatile - read-write volatile and custom)" group.word 0x9090++0x1 line.word 0x0 "LANEX_ANA_RX_ENPWR1,Additional RX State Control Register" newline hexmask.word.byte 0x0 8.--15. 1. "RESERVED_15_8,Reserved for Future use" newline bitfld.word 0x0 7. "CTL_PHASE_REG_RST,MUX select for Phase Register Reset to select between CTL_PHASE_REG_RST=0 rx_phase_reg_rst (External signal) or CTL_PHASE_REG_RST=1 LCL_PHASE_REG_RST" "0,1" newline bitfld.word 0x0 6. "LCL_PHASE_REG_RST,Reset phase register.This bit is only selected when CTL_PHASE_REG_RST= 1" "0,1" newline bitfld.word 0x0 5. "CTL_BST,MUX select for AFE Boost to select between CTL_BST=0 rx_aeq[2:0] (External signal) or CTL_BST=1 LCL_BST" "0,1" newline bitfld.word 0x0 2.--4. "LCL_BST,RX Boost (equalization) Value" "0,1,2,3,4,5,6,7" newline bitfld.word 0x0 1. "CTL_RXTERM,MUX select for RX Term enable to select between CTL_RXTERM=0 rx_term_en (External signal) or CTL_RXTERM=1 LCL_RXTERM" "0,1" newline bitfld.word 0x0 0. "LCL_RXTERM,Enable/disable RX termination when CTL_RXTERM = 1" "0,1" group.word 0x9094++0x1 line.word 0x0 "LANEX_ANA_RX_ENPWR2,Yet another RX State Control Register" newline hexmask.word.byte 0x0 8.--15. 1. "RESERVED_15_8,Reserved for Future use" newline bitfld.word 0x0 7. "EN_RXPMIX_TST,Enable XOR gate to test linearity of RX phase mixer using atb_s_p and atb_s_m" "0,1" newline bitfld.word 0x0 6. "EN_RXPMIX_VPMIX,Put vreg_pmix on atb_s_p" "0,1" newline bitfld.word 0x0 5. "EN_RXPMIX_VRX,Put vreg_rx on atb_s_p" "0,1" newline bitfld.word 0x0 4. "RX_DCC_IQ_OFFSET_H_0,Code which helps to manually tune reference voltage (r-string dac) for IQ opamp and correct input offset (rx_dcc_iq_offset_h_0 bit)" "0,1" newline bitfld.word 0x0 3. "EN_RXPMIX_FRC_VPMIX_H,Connecting vbg_in to vbg (in case of 0) or to atb_s_m_int (in case of 1)" "0,1" newline bitfld.word 0x0 2. "RX_SCOPE_ATB_2,Put XOR of RX SCOPE PMIX input and output on atb_s_p" "0,1" newline bitfld.word 0x0 1. "RX_SCOPE_ATB_1,Put RX SCOPE regulated VP on atb_s_p" "0,1" newline bitfld.word 0x0 0. "RX_SCOPE_ATB_0,Have RX SCOPE reference for regulator use atb_f_p as a reference instead of VP/VBG" "0,1" group.word 0x9098++0x1 line.word 0x0 "LANEX_ANA_RX_SCOPE_VDCC,RX Scope controls and clock DCC control voltage probe" newline hexmask.word.byte 0x0 8.--15. 1. "RESERVED_15_8,Reserved for Future use" newline bitfld.word 0x0 6.--7. "VDCC,Probe DCC control voltage" "0,1,2,3" newline bitfld.word 0x0 5. "NC5,Reserved" "0,1" newline bitfld.word 0x0 4. "RX_SCOPE_SLEW,Set high for low RX clock frqeuencies (625MHz) for RX Scope to work correctly" "0,1" newline bitfld.word 0x0 3. "RX_SCOPE_FDIV20,Divide scope output clock by 20 instead of 10" "0,1" newline bitfld.word 0x0 2. "RX_LOS_LFPS_EN_BIT_2,In case of rx_los_lfps_en_cntrl = 1/0 reg_rx_los_lfps_en/rx_ana_los_lfps_en signal directly applied to rx_los circuit through I101 multiplexer." "0,1" newline bitfld.word 0x0 1. "RX_DCC_IQ_OFFSET_EN_H,Select ref voltage for IQ opamp from testmode part (in case of 1) or from ordinary resistive dividers (in case of 0)." "0,1" newline bitfld.word 0x0 0. "RX_LOS_LFPS_EN,Enables the RX LOS LFPS mode use when you want to detect incoming LFPS signals USB3.0" "0,1" group.word 0x90AC++0x1 line.word 0x0 "LANEX_ANA_TX_TXDRV_CNTRL,Register 3" newline hexmask.word.byte 0x0 8.--15. 1. "RESERVED_15_8,Reserved for Future use" newline bitfld.word 0x0 7. "PULL_DN_REG,register bit that causes the calibrated TX bits to pull down in a common mode fashion. If pull_dn_reg and tx_pull_up are both high then pull_dn_reg wins" "0,1" newline bitfld.word 0x0 6. "PULL_UP_REG,Register override for tx_pull_up. Used when ovrd_pull_up is HIGH causes calibrated TX bits to pull up in a common mode fashion unless pull_dn_reg is HIGH" "0,1" newline bitfld.word 0x0 5. "OVRD_PULL_UP,Selects local value of pull_up_reg instead of tx_pull_up" "0,1" newline bitfld.word 0x0 4. "VCM_HOLD_REG,Register override for tx_vcm_hold. Used when ovrd_vcm_hold is HIGH controls the TX common mode hold circuitry" "0,1" newline bitfld.word 0x0 3. "OVRD_VCM_HOLD,Selects local value of vcm_hold_reg instead of tx_vcm_hold to control state of TX common mode hold circuitry" "0,1" newline bitfld.word 0x0 2. "REFGEN_PWRDN_OVRD_N,Set LOW for TX regulator not to turn on when RX clock is enabled. Default is for TX regulator to turn on when RX or TX clock is enabled" "0,1" newline bitfld.word 0x0 1. "NOCONN_1,Reserved" "0,1" newline bitfld.word 0x0 0. "NOCONN_0,Reserved" "0,1" group.word 0x90B0++0x1 line.word 0x0 "LANEX_ANA_TX_POWER_CTL,Register 4" newline hexmask.word.byte 0x0 8.--15. 1. "RESERVED_15_8,Reserved for Future use" newline bitfld.word 0x0 7. "OVRD_EN,Enables local overrides for all signals in this register except for TX_DIV_CLK_EN which doesn't need this signal" "0,1" newline bitfld.word 0x0 6. "SERIAL_EN_REG,Forces state of tx_serial_en when OVRD_EN is 1" "0,1" newline bitfld.word 0x0 5. "CLK_EN_REG,Forces state of tx_clk_en when OVRD_EN is 1" "0,1" newline bitfld.word 0x0 4. "DATA_EN_REG,Forces state of tx_data_en when OVRD_EN is HIGH" "0,1" newline bitfld.word 0x0 3. "REFGEN_EN_REG,Register override value for tx_refgen_en. Controls the TX regulator biasing circuitry and the rxdetect comparators when OVRD_EN is HIGH. This function may be overridden by the state of refgen_pwdn_reg" "0,1" newline bitfld.word 0x0 2. "TX_DIV_CLK_EN,Enables the div clock that goes from the TX to the undersampler more appropriately called tx_sampler_clk_en this clock comes after the optional divide by 2 or 4 tx_clk_en must be HIGH to get a clock out" "0,1" newline bitfld.word 0x0 1. "REFGEN_PDN_REG,Register override for refgen pwdn. Used when OVRD_EN is HIGH. Controls the TX regulator biasing circuitry and the rxdetect comparators when OVRD_EN is HIGH" "0,1" newline bitfld.word 0x0 0. "LFPS_HIGH_PRIORITY,When this is set high LFPS priority becomes higher than tx_data" "0,1" group.word 0x90B4++0x1 line.word 0x0 "LANEX_ANA_TX_ALT_BLOCK,Register 5" newline hexmask.word.byte 0x0 8.--15. 1. "RESERVED_15_8,Reserved for Future use" newline bitfld.word 0x0 7. "EN_ALT_BUS,Enables the TX for alt bus mode powers up the TX regulator biasing circuitry and the rxdetect comparators. Needed if manually running the alt bus features" "0,1" newline bitfld.word 0x0 5.--6. "DRV_SOURCE_REG,Forces state of tx_data_source when OVRD_ALT_BUS is HIGH. 00 = serializer data or alt oscillator vp/vph/vphreg/vptx if selected 01 = jtag data differential 10 = LFPS oscillator differential 11 = jtag data common mode drive for test" "serializer data or alt oscillator..,jtag data differential,?,?" newline bitfld.word 0x0 4. "JTAG_DATA_REG,Forces state of jtag_data when OVRD_ALT_BUS is HIGH" "0,1" newline bitfld.word 0x0 1.--3. "TX_RINGO_CNTRL,Enables and connects the various test oscillators to the transmit pins must set drv_source_reg bus correctly. 0XX = All oscillators are disabled 100 = HV oscillator enabled 101 = SVT oscillator enabled 110 = LVT oscillator enabled 111.." "0,1,2,3,4,5,6,7" newline bitfld.word 0x0 0. "OVRD_ALT_BUS,Enables local overrides for alt-bus control signals: DRV_SOURCE_REG and JTAG_DATA_REG" "0,1" group.word 0x90B8++0x1 line.word 0x0 "LANEX_ANA_TX_ALT_AND_LOOPBACK,Register 6" newline hexmask.word.byte 0x0 8.--15. 1. "RESERVED_15_8,Reserved for Future use" newline bitfld.word 0x0 7. "OVRD_TX_LB,Enables the override of the tx_lb_en" "0,1" newline bitfld.word 0x0 6. "TX_LB_EN_REG,Forces state of tx_lb_en when OVRD_TX_LB is enabled" "0,1" newline bitfld.word 0x0 5. "ATB_VPTX,Connects vptx to atb_s_p and gd to atb_s_m" "0,1" newline bitfld.word 0x0 4. "ATB_VREG_TX,Connects TX regulator input reference to atb_s_p and gd to atb_s_m" "0,1" newline bitfld.word 0x0 3. "ATB_VDCCP,Connects vdcc_p to atb_s_p" "0,1" newline bitfld.word 0x0 2. "ATB_VDCCM,Connects vdcc_m to atb_s_m" "0,1" newline bitfld.word 0x0 1. "NOCONN_01,Reserved" "0,1" newline bitfld.word 0x0 0. "SELECT_PMIX_CLK,select pmix_clk for TX clock for ATE test mode" "0,1" group.word 0x90BC++0x1 line.word 0x0 "LANEX_ANA_TX_TX_ATB_REG,Register 7" newline hexmask.word.byte 0x0 8.--15. 1. "RESERVED_15_8,Reserved for Future use" newline bitfld.word 0x0 7. "ATB_PBIAS,Connect real pmos_bias voltage for TX PMOS driver pull up path to atb_s_p and local ground at the pmos_bias block to atb_s_m" "0,1" newline bitfld.word 0x0 6. "ATB_VCM_REP,Connect common mode replica voltage in pmos_bias block to atb_s_p and local ground to atb_s_m" "0,1" newline bitfld.word 0x0 5. "ATB_RXDETREF,Connect RX detect block reference voltage to atb_s_p and local ground to atb_s_m" "0,1" newline bitfld.word 0x0 4. "ATB_TXFP,Connect tx_p to atb_f_p" "0,1" newline bitfld.word 0x0 3. "ATB_TXFM,Connect tx_m to atb_f_m" "0,1" newline bitfld.word 0x0 2. "ATB_TXSP,Connect tx_p to atb_s_p" "0,1" newline bitfld.word 0x0 1. "ATB_TXSM,Connect tx_m to atb_s_m" "0,1" newline bitfld.word 0x0 0. "ATB_VCM,Connect tx_p/tx_m common mode voltage onto atb_s_p and local ground onto atb_s_m" "0,1" group.word 0x90C0++0x1 line.word 0x0 "LANEX_ANA_TX_TX_BOOST,Register 8" newline hexmask.word.byte 0x0 8.--15. 1. "RESERVED_15_8,Reserved for Future use" newline bitfld.word 0x0 7. "OVRD_VBOOST_EN,Enables the overrides on VBOOST_EN_REG" "0,1" newline bitfld.word 0x0 6. "VBOOST_EN_REG,Forces state of tx_vboost_en when OVRD_VBOOST_EN is HIGH" "0,1" newline bitfld.word 0x0 5. "VCON_EN_N,Forces state of vcon_en_n" "0,1" newline bitfld.word 0x0 4. "ATB_VBOOST,Connects vboost to atb_s_p and local ground to Atb_s_m" "0,1" newline bitfld.word 0x0 3. "ATB_VCMBOOST,Connects vcmboost to atb_s_p and local ground to atb_s_m." "0,1" newline bitfld.word 0x0 2. "ATB_F_VBOOST_REF,Enables forcing of tx_vboost_vref through atb_f_p from external" "0,1" newline bitfld.word 0x0 1. "OVRD_VREG_DECAP,Enables override of vreg_decap_en_n signal" "0,1" newline bitfld.word 0x0 0. "VREG_DECAP_EN_N_REG,Forces state of vreg_decap_en_n control signal. Controls whether extra decoupling is switched in for TX regulator output." "0,1" group.word 0x9100++0x1 line.word 0x0 "LANEX_DIG_RX_CDR_FSM_INIT_CTL,Control bits for CDR init phase portion" newline hexmask.word.byte 0x0 9.--15. 1. "RESERVED_15_9,Reserved for Future use" newline bitfld.word 0x0 8. "INIT_CNT_OVRD,Active high override enable bit to select the override INIT_CNT register 0 = Disabled 1 = Enabled" "Disabled,Enabled" newline hexmask.word.byte 0x0 0.--7. 1. "INIT_CNT,Override value for CDR Init Phase" group.word 0x9104++0x1 line.word 0x0 "LANEX_DIG_RX_CDR_FSM_TRACK_CTL,Control bits for CDR track phase portion" newline hexmask.word.byte 0x0 9.--15. 1. "RESERVED_15_9,Reserved for Future use" newline bitfld.word 0x0 8. "TRACK_CNT_OVRD,Active high override enable bit to select the override TRACK_CNT register 0 = Disabled 1 = Enabled" "Disabled,Enabled" newline hexmask.word.byte 0x0 0.--7. 1. "TRACK_CNT,Override value for CDR Track Phase" group.word 0x9108++0x1 line.word 0x0 "LANEX_DIG_RX_CDR_FSM_LOCK_CTL,Control bits for CDR lock phase portion" newline hexmask.word.byte 0x0 9.--15. 1. "RESERVED_15_9,Reserved for Future use" newline bitfld.word 0x0 8. "LOCK_CNT_OVRD,Active high override enable bit to select the override LOCK_CNT register 0 = Disabled 1 = Enabled" "Disabled,Enabled" newline hexmask.word.byte 0x0 0.--7. 1. "LOCK_CNT,Override value for CDR Lock Phase" repeat 9. (list 0x0 0x1 0x2 0x3 0x4 0x8 0x9 0xB 0xC )(list 0x0 0x4 0x8 0xC 0x10 0x20 0x24 0x2C 0x30 ) rgroup.word ($2+0xA000)++0x1 line.word 0x0 "PORTX_STAT_RO_$1,Status Register 0" newline hexmask.word 0x0 4.--15. 1. "RESERVED_15_4,Reserved for Future use" newline bitfld.word 0x0 3. "PLL_LOCK,analog PLL Lock Signal" "0,1" newline bitfld.word 0x0 2. "RX_SQUELCH,analog RX Squelch Signal" "0,1" newline bitfld.word 0x0 1. "RESERVED_1,Reserved" "0,1" newline bitfld.word 0x0 0. "RESERVED_0,Reserved" "0,1" repeat.end repeat 7. (list 0x5 0x6 0x7 0xA 0xD 0xE 0xF )(list 0x0 0x4 0x8 0x14 0x20 0x24 0x28 ) rgroup.word ($2+0xA014)++0x1 line.word 0x0 "PORTX_STAT_RO_$1,Status Register 5" newline hexmask.word 0x0 4.--15. 1. "RESERVED_15_4,Reserved for Future use" newline hexmask.word.byte 0x0 0.--3. 1. "DATAOUT,UTMI+ Output DATAOUT" repeat.end repeat 2. (list 0x0 0x6 )(list 0x0 0x18 ) group.word ($2+0xA040)++0x1 line.word 0x0 "PORTX_OVRD_RW_$1,Override Register 0" newline hexmask.word.byte 0x0 8.--15. 1. "RESERVED_15_8,Reserved for Future use" newline hexmask.word.byte 0x0 4.--7. 1. "OVERRD_ADDR_OVRD_EN,Override Enable for overrd_addr [7:4]" newline hexmask.word.byte 0x0 0.--3. 1. "OVERRD_ADDR,Analog Test Control Override Address [3:0]" repeat.end repeat 10. (list 0x1 0x2 0x3 0x4 0x8 0x9 0xA 0xB 0xE 0xF )(list 0x0 0x4 0x8 0xC 0x1C 0x20 0x24 0x28 0x34 0x38 ) group.word ($2+0xA044)++0x1 line.word 0x0 "PORTX_OVRD_RW_$1,Override Register 1" newline hexmask.word.byte 0x0 8.--15. 1. "RESERVED_15_8,Reserved for Future use" newline bitfld.word 0x0 7. "VBUS_VALID_PU_OVRD_EN,Override Enable for vbus_valid_pu" "0,1" newline bitfld.word 0x0 6. "OTG_PU_OVRD_EN,Override Enable for otg_pu" "0,1" newline bitfld.word 0x0 5. "TX_VREF_VREG_PU_OVRD_EN,Override Enable for tx_vref_vreg_pu" "0,1" newline bitfld.word 0x0 4. "SQRX_PU_OVRD_EN,Override Enable for sqrx_pu" "0,1" newline bitfld.word 0x0 3. "VBUS_VALID_PU,DRVVBUS Input" "0,1" newline bitfld.word 0x0 2. "OTG_PU,OTGDISABLE Input" "0,1" newline bitfld.word 0x0 1. "TX_VREF_VREG_PU,TX hs_driver Comparator Power Up" "0,1" newline bitfld.word 0x0 0. "SQRX_PU,RX squelch Comparator Power Up" "0,1" repeat.end group.word 0xA054++0x1 line.word 0x0 "PORTX_OVRD_RW_5,Override Register 5" newline hexmask.word.byte 0x0 8.--15. 1. "RESERVED_15_8,Reserved for Future use" newline bitfld.word 0x0 6.--7. "XO_CLK_DIV_OVRD_EN,Override Enable for xo_clk_div" "0,1,2,3" newline bitfld.word 0x0 5. "MSTR_OVERRD_BIT_OVRD_EN,Override Enable for mstr_overrd_bit" "0,1" newline bitfld.word 0x0 4. "OVERRD_ADDR_4_OVRD_EN,Override Enable for overrd_addr_4" "0,1" newline bitfld.word 0x0 2.--3. "XO_CLK_DIV,setting reference clock division" "0,1,2,3" newline bitfld.word 0x0 1. "MSTR_OVERRD_BIT,Analog Test Control Master Override" "0,1" newline bitfld.word 0x0 0. "OVERRD_ADDR_4,Analog Test Control Override Address [4]" "0,1" group.word 0xA05C++0x1 line.word 0x0 "PORTX_OVRD_RW_7,Override Register 7" newline hexmask.word.byte 0x0 8.--15. 1. "RESERVED_15_8,Reserved for Future use" newline bitfld.word 0x0 7. "TX_LS_EN_OVRD_EN,Override Enable for tx_ls_en" "0,1" newline bitfld.word 0x0 4.--6. "PWR_SEQ_CLK_DIV_OVRD_EN,Override Enable for pwr_seq_clk_div" "0,1,2,3,4,5,6,7" newline bitfld.word 0x0 3. "TX_LS_EN,TX LS Enable" "0,1" newline bitfld.word 0x0 0.--2. "PWR_SEQ_CLK_DIV,setting power_sequence division" "0,1,2,3,4,5,6,7" group.word 0xA070++0x1 line.word 0x0 "PORTX_OVRD_RW_12,Override Register 12" newline hexmask.word.byte 0x0 8.--15. 1. "RESERVED_15_8,Reserved for Future use" newline bitfld.word 0x0 7. "RES_ACK_OUT_OVRD_EN,Override Enable for res_ack_out" "0,1" newline bitfld.word 0x0 5.--6. "PLL_CLK_DIV_OVRD_EN,Override Enable for pll_clk_div" "0,1,2,3" newline bitfld.word 0x0 4. "PLL_RESET_OVRD_EN,Override Enable for pll_reset" "0,1" newline bitfld.word 0x0 3. "RES_ACK_OUT,Ack resistor tune external requirement" "0,1" newline bitfld.word 0x0 1.--2. "PLL_CLK_DIV,setting MPLL division" "0,1,2,3" newline bitfld.word 0x0 0. "PLL_RESET,MPLL gear_shift" "0,1" group.word 0xA074++0x1 line.word 0x0 "PORTX_OVRD_RW_13,Override Register 13" newline hexmask.word.byte 0x0 8.--15. 1. "RESERVED_15_8,Reserved for Future use" newline bitfld.word 0x0 7. "BIST_MODE_OVRD_EN,Override Enable for bist_mode" "0,1" newline bitfld.word 0x0 6. "TEST_PKT_RPT_OVRD_EN,Override Enable for test_pkt_rpt" "0,1" newline bitfld.word 0x0 4.--5. "XO_CLK_SEL_OVRD_EN,Override Enable for xo_clk_sel" "0,1,2,3" newline bitfld.word 0x0 3. "BIST_MODE,BIST Mode" "0,1" newline bitfld.word 0x0 2. "TEST_PKT_RPT,BIST Test Packet Mode" "0,1" newline bitfld.word 0x0 0.--1. "XO_CLK_SEL,Reference Clock Selection" "0,1,2,3" tree.end tree "USB_PHY2_NCR" base ad:0x31290000 group.long 0x0++0x13 line.long 0x0 "CTRL_0,CTRL_0" bitfld.long 0x0 31. "TEST_BURNIN,All Circuits Activator" "0,1" bitfld.long 0x0 28.--30. "TX_VBOOST_LVL,TX Voltage Boost Level Sets the boosted transmit launch amplitude (mVppd)." "0,1,2,3,4,5,6,7" newline bitfld.long 0x0 25.--27. "SSC_RANGE,Spread Spectrum Clock Range Selects the range of spread spectrum modulation when ssc_en is asserted and the PHY is spreading the high-speed transmit clocks. Applies a fixed offset to the phase accumulator." "0,1,2,3,4,5,6,7" bitfld.long 0x0 24. "SSC_EN,Spread Spectrum Enable Enables spread spectrum clock production (0.5% down-spread at ~ 31.5 KHz) in the USB 3.0 femtoPHY. Set this signal to 1'b1." "0,1" newline bitfld.long 0x0 23. "RTUNE_REQ,Resistor Tune Request Assertion triggers a resistor tune request (if one is not already in progress). When this signal is asserted rtune_ack goes high until calibration of the termination impedances is complete. Note that termination.." "0,1" bitfld.long 0x0 22. "REF_USE_XO,Use External Crystal Oscillator" "0,1" newline bitfld.long 0x0 21. "REF_XO_EN,Crystal Oscillator Always On Enable" "0,1" bitfld.long 0x0 20. "REF_REPEAT_CLK_EN,Clock Repeater Buffer Enable" "0,1" newline bitfld.long 0x0 19. "REF_CLKDIV2,Input Reference Clock Divider Control If the input reference clock frequency is greater than 100 MHz this signal must be asserted. The reference clock frequency is then divided by 2 to keep it in the range required by the MPLL. When this.." "0,1" bitfld.long 0x0 18. "REF_USE_PAD,Select Reference Clock Connected to ref_pad_clk_\{p m\} When asserted selects the external ref_pad_clk_\{p m\} inputs as the reference clock source. When ref_use_pad is de-asserted ref_alt_clk_\{p m\} are selected for an on-chip reference.." "0,1" newline bitfld.long 0x0 17. "REF_SSP_EN,Reference Clock Enable for SS function. Enables the reference clock to the prescaler. The ref_ssp_en signal must remain de-asserted until the reference clock is running at the appropriate frequency at which point ref_ssp_en can be asserted." "0,1" hexmask.long.word 0x0 8.--16. 1. "SSC_REF_CLK_SEL,Spread Spectrum Reference Clock Shifting Enables non-standard oscillator frequencies to generate targeted MPLL output rates. Input corresponds to frequency-synthesis coefficient. ssc_ref_clk_sel[8:6] = modulous -1.." newline bitfld.long 0x0 7. "ALT_CLK_EN,Alternate Clock Enable Enables the ref_pcs_clk and ref_pipe_pclk output clocks (if necessary powers up the MPLL)." "0,1" newline bitfld.long 0x0 2. "PIPE_RESET_N,PIPE_RESET_N" "0,1" bitfld.long 0x0 1. "PORTRESET,When asserted this customer-specific signal resets the corresponding port's USB2.0 transmit and receive logic without disabling the clocks within the USB 3.0 femtoPHY. 1: The transmit and receive finite state machines (FSMs) are reset and.." "The transmit and receive FSMs are operational,The transmit and receive finite state machines" newline bitfld.long 0x0 0. "PHY_RESET,Core and State Machine Reset Resets the core and all state machines including the JTAG interface with the exception of the reference clock buffer. Asserting phy_reset triggers the assertion of the tx<#>_reset and rx<#>_reset signals." "0,1" line.long 0x4 "CTRL_1,CTRL_1" bitfld.long 0x4 29.--31. "COMPDISTUNE0,Disconnect Threshold Adjustment Adjusts the voltage level for the threshold used to detect a disconnect event at the host. To enable tuning at the board level connect this bus to a register. 111: + 4.5% 110: + 3% 101: + 1.5%.." "0,1,2,3,4,5,6,7" bitfld.long 0x4 26.--28. "LOS_BIAS,Loss-of-Signal Detector Threshold Level Control Sets the LOS detection threshold level. To enable tuning at the board level connect this bus to a register. 111: 135 mV 110: 120 mV 101: 105 mV 100: 90 mV 011: 75 mV 010:.." "Invalid,?,?,?,?,?,?,?" newline hexmask.long.byte 0x4 21.--25. 1. "LOS_LEVEL,Loss-of-Signal Detector Sensitivity Level Control" bitfld.long 0x4 20. "TEST_POWERDOWN_SSP,SS Function Circuits Power-Down Control Powers down all SS function circuitry in the PHY for IDDQ testing." "0,1" newline bitfld.long 0x4 19. "TEST_POWERDOWN_HSP,HS Function Circuits Power-Down Control Powers down all HS function circuitry in the PHY for IDDQ testing. Before asserting this signal ensure that VDATSRCENB<#> VDATDETENB<#> DCDENB<#> BYPASSSEL<#> and test_burnin are set to 1'b0." "0,1" hexmask.long.byte 0x4 13.--18. 1. "FSEL,Selects the reference clock frequency used for both SS and HS operations. The value for fsel combined with the other clock and enable signals determine the clock frequency used for SS and HS operations and if a shared or separate reference clock is.." newline hexmask.long.byte 0x4 8.--12. 1. "ACJT_LEVEL,1149.6 Receiver Sensitivity Level Control Selects the sensitivity level for the 1149.6 receiver for AC JTAG. Set the level based on the amplitude of the incoming Step during AC JTAG boundary scan testing." bitfld.long 0x4 7. "MPLL_REFSSC_CLK_EN,Double-Word Clock Enable" "0,1" newline hexmask.long.byte 0x4 0.--6. 1. "MPLL_MULTIPLIER,MPLL Frequency Multiplier Control Multiplies the reference clock to a frequency suitable for intended operating speed." line.long 0x8 "CTRL_2,CTRL_2" bitfld.long 0x8 31. "CHRGSEL0,Battery Charging Source Select Determines whether current is sourced onto or sunk from DP<#> or DM<#>. 1: Data source voltage (VDAT_SRC) is sourced onto DM<#> and sunk from DP<#>. 0: Data source voltage (VDAT_SRC) is sourced onto DP<#>.." "Data source voltage,Data source voltage" bitfld.long 0x8 30. "LANE0_TX2RX_LOOPBK,Loopback. When this signal is asserted data from the transmit predriver is looped back to the receive slicers. LOS is bypassed and based on the tx0_en input so that rx0_los = !tx0_data_en." "0,1" newline bitfld.long 0x8 29. "LANE0_EXT_PCLK_REQ,External PIPE Clock Enable Request. When asserted this signal enables the pipeX_pclk output regardless of power state (along with the associated increase in power consumption). You can use this input to enable pipeX_pclk in the P3.." "0,1" hexmask.long.byte 0x8 23.--28. 1. "PCS_TX_DEEMPH_6DB,TX De-Emphasis at 6 dB This static value sets the TX driver de-emphasis value when pipeP_tx_deemph[1:0] is set to 2'b10 (according to the PIPE3 specification). This bus is provided for completeness and as a second potential launch.." newline hexmask.long.byte 0x8 17.--22. 1. "PCS_TX_DEEMPH_3P5DB,TX De-Emphasis at 3.5 dB This static value sets the TX driver de-emphasis value when pipeX_tx_deemph[1:0] is set to 2'b01 (according to the PIPE3 specification). To enable tuning at the board level for RX eye compliance connect this.." hexmask.long.word 0x8 7.--16. 1. "PCS_RX_LOS_MASK_VAL,Configurable Loss-of-Signal Mask Width Sets the number of reference clock cycles to mask the incoming LFPS in U3 and U2 states. Masks the incoming LFPS for the number of reference clock cycles equal to the value of.." newline hexmask.long.byte 0x8 0.--6. 1. "PCS_TX_SWING_FULL,TX Amplitude (Full Swing Mode) This static value sets the launch amplitude of the transmitter. To enable tuning at the board level for RX eye compliance connect this signal to a register." line.long 0xC "CTRL_3,CTRL_3" bitfld.long 0xC 31. "VATESTENB,Analog Test Pin Select Enables analog test voltages to be placed on the ID<#> pin. 1: Analog test voltages can be viewed or applied on ID<#>. 0: Analog test voltages cannot be viewed or applied on ID<#>." "Analog test voltages cannot be viewed or applied..,Analog test voltages can be viewed or applied on.." bitfld.long 0xC 28.--30. "SQRXTUNE0,Adjusts the voltage level for the threshold used to detect valid high-speed data." "0,1,2,3,4,5,6,7" newline bitfld.long 0xC 27. "RX0LOSLFPSEN,Enables the RX LOS LFPS mode use when you want to detect incoming LFPS signals USB3.0" "0,1" bitfld.long 0xC 26. "RETENABLEN,Lowered Digital Supply Indicator." "0,1" newline bitfld.long 0xC 24.--25. "REFCLKSEL,Reference Clock Select for PLL Block" "0,1,2,3" bitfld.long 0xC 21.--23. "OTGTUNE0,VBUS Valid Threshold Adjustment This bus adjusts the voltage level for the VBUS<#> valid threshold. To enable tuning at the board level connect this bus to a register. 111: + 9% 110: + 6% 101: + 3% 100: 0 (default) 011: - 3%.." "0,1,2,3,4,5,6,7" newline bitfld.long 0xC 20. "OTGDISABLE0,OTG Block Disable This controller signal powers down the OTG block which disables the VBUS Valid and Session End comparators. The Session Valid comparator (the output of which is used to enable the pull-up resistor on DP<#> in Device mode).." "OTG block is powered up,OTG block is powered down" bitfld.long 0xC 19. "LOOPBACKENB0,Loopback Test Enable This controller signal places the USB 3.0 femtoPHY in HS Loopback mode which concurrently enables the HS receive and transmit logic. 1: During HS data transmission the HS receive logic is enabled. 0: During HS.." "During HS data transmission,During HS data transmission" newline bitfld.long 0xC 18. "HSXCVREXTCTL0,HS Transceiver Asynchronous Control. This signal asynchronously selects the HS transceiver TX/RX path and can be used with the bypass signals to perform proprietary tests on the HS TX / RX paths. (For information about the bypass signals.." "FS TX/RX path is selected,HS TX/RX path is selected" bitfld.long 0xC 16.--17. "CHRGSRCPUENB0,Charger Source Pull-Up Enable." "0,1,2,3" newline bitfld.long 0xC 15. "AUTORSMENB0,AUTORSMENB0" "0,1" bitfld.long 0xC 14. "ATERESET,Reset Input from Automatic Test Equipment When the USB 3.0 femtoPHY is powered up (not in Suspend or Sleep mode) an automatic tester can use this test signal to disable PHYCLOCK<#> and FREECLK then re-enable them with an aligned phase. 1:.." "PHYCLOCK<#> and FREECLK outputs are available..,PHYCLOCK<#> and FREECLK outputs are disabled" newline bitfld.long 0xC 13. "FSSE0EXT0,USB 1.1 SE0 Generation This controller signal sets the USB (2.0) to an SE0 state. This signal is valid only if FSXCVROWNER<#> is set to 1'b1 and TXENABLEN<#> is set to 1'b0. 1: D+ and D- lines are driven to an SE0 state. 0: D+ and D-.." "D+ and D,D+ and D" bitfld.long 0xC 12. "FSDATAEXT0,USB 1.1 Transmit Data This controller signal sets the USB (2.0) to either a J or K state. This signal is valid only if FSXCVROWNER<#> is set to 1'b1 TXENABLEN<#> is set to 1'b0 and FSSE0EXT<#> is set to 1'b0. 1: D+ and D- lines are.." "D+ and D,D+ and D" newline bitfld.long 0xC 11. "TXENABLEN0,USB 1.1 Data Enable This controller signal enables the FSDATAEXT<#> and FSSE0EXT<#> inputs. TXENABLEN<#> is valid only when the FSXCVROWNER<#> signal is set to 1'b1. 1: FSDATAEXT<#> and FSSE0EXT<#> are disabled. 0: FSDATAEXT<#> and.." "FSDATAEXT<#> and FSSE0EXT<#> are enabled,FSDATAEXT<#> and FSSE0EXT<#> are disabled" bitfld.long 0xC 10. "TXBITSTUFFENH0,High-Byte Transmit Bit-Stuffing Enable This controller signal controls bit stuffing on DATAINH<#>[7:0] when OPMODE<#>[1:0] = 2'b11. 1: Bit stuffing is enabled. 0: Bit stuffing is disabled." "Bit stuffing is disabled,Bit stuffing is enabled" newline bitfld.long 0xC 9. "TXBITSTUFFEN0,Low-Byte Transmit Bit-Stuffing Enable This controller signal controls bit stuffing on DATAIN<#>[7:0] when OPMODE<#>[1:0] = 2'b11. 1: Bit stuffing is enabled. 0: Bit stuffing is disabled." "Bit stuffing is disabled,Bit stuffing is enabled" bitfld.long 0xC 8. "IDPULLUP0,Analog ID Input Sample Enable This controller signal controls ID<#> line sampling. 1: ID<#> pin sampling is enabled and the IDDIG0 output is valid. 0: ID<#> pin sampling is disabled and the IDDIG0 output is not valid." "ID<#> pin sampling is disabled,ID<#> pin sampling is enabled" newline bitfld.long 0xC 7. "VDATSRCENB0,Battery Charging Sourcing Select Enables or disables sourcing for battery charging. 1: Data source voltage (VDAT_SRC) is enabled. 0: Data source voltage (VDAT_SRC) is disabled. During USB 3.0 femtoPHY normal operation set this signal.." "Data source voltage,Data source voltage" bitfld.long 0xC 6. "VDATDETENB0,Battery Charging Attach/Connect Detection Enable Enables or disables attach/connect detection. 1: Data detect voltage (CHG_DET) is enabled. 0: Data detect voltage (CHG_DET) is disabled. During USB 3.0 femtoPHY normal operation set.." "Data detect voltage,Data detect voltage" newline bitfld.long 0xC 5. "DCDENB0,Data Contact Detection Enable. Enables current sourcing on the D+ line. For special applications the IDP_SRC control and the RDM_DWN control are separated. For standard DCD operation in accordance with the Battery Charger v1.2 specification.." "IDP_SRC current is disabled,IDP_SRC current is sourced onto DP<#>" hexmask.long.byte 0xC 0.--4. 1. "LANE0_TX_TERM_OFFSET,Transmitter Termination Offset" line.long 0x10 "CTRL_4,CTRL_4" bitfld.long 0x10 31. "REF_CLK_SW_32K,REF_CLK switch to 32K" "0,1" bitfld.long 0x10 28.--30. "CR_CKDIV,CR clock div" "0,1,2,3,4,5,6,7" newline bitfld.long 0x10 27. "CR_MODE,CR mode" "0,1" bitfld.long 0x10 26. "COMMONONN,Common Block Power-Down Control Controls the power-down signals in the PLL block when the USB 3.0 femtoPHY is in Suspend or Sleep mode. 1: In Suspend or Sleep mode the PLL block is powered down. 0: In Suspend or Sleep mode the PLL.." "In Suspend or Sleep mode,In Suspend or Sleep mode" newline bitfld.long 0x10 25. "BYPASSSEL0,Transmitter Digital Bypass Select Enables/disables Transmitter Digital Bypass mode. The standard FS UART mode is selected by setting HSXCVREXTCTL<#> to 1'b0 and a proprietary HS test mode is selected by setting HSXCVREXTCTL<#> to 1'b1. 1:.." "Transmitter Digital Bypass mode is disabled,Transmitter Digital Bypass mode is enabled" bitfld.long 0x10 24. "BYPASSDPEN0,DP<#> Transmitter Digital Bypass Enable. Enables/disables the DP<#> FS/LS driver (if HSXCVREXTCTL<#> is set to 1'b0) or the DP<#> and DM<#> HS driver (if HSXCVREXTCTL<#> is set to 1'b1) in Transmitter Digital Bypass mode. FS mode is the.." "DP<#> FS/LS driver,DP<#> FS/LS driver" newline bitfld.long 0x10 23. "BYPASSDPDATA0,Data for DP<#> Transmitter Digital Bypass. In Transmitter Digital Bypass mode this signal provides the data that is transmitted on DP<#>. To use this signal BYPASSSEL<#> must be set to 1'b1. When HSXCVREXTCTL<#> is set to 1'b0 the FS/LS.." "HS driver transmits K,HS driver transmits J" bitfld.long 0x10 22. "BYPASSDMEN0,DM<#> Transmitter Digital Bypass Enable. Enables/disables the DM<#> FS/LS driver (if HSXCVREXTCTL<#> is set to 1'b0) in Transmitter Digital Bypass mode. FS mode is the standard UART mode. To use this mode BYPASSSEL<#> must be set to 1'b1." "DM<#> FS/LS driver,DM<#> FS/LS driver" newline bitfld.long 0x10 21. "BYPASSDMDATA0,Data for DM<#> Transmitter Digital Bypass. In Transmitter Digital Bypass mode this signal provides the data that is transmitted on DM<#>. To use this signal BYPASSSEL<#> must be set to 1'b1. When HSXCVREXTCTL<#> is set to 1'b0 the FS/LS.." "DM<#> FS/LS driver drives to a low state,DM<#> FS/LS driver drives to a high state" bitfld.long 0x10 20. "VBUSVLDEXTSEL0,External VBUS Valid Select Selects the VBUSVLDEXT<#> input or the internal Session Valid comparator to indicate when the VBUS<#> signal on the USB cable is valid. 1: VBUSVLDEXT<#> input is used. 0: Internal Session Valid comparator.." "Internal Session Valid comparator is used,VBUSVLDEXT<#> input is used" newline bitfld.long 0x10 19. "VBUSVLDEXT0,External VBUS Valid Indicator Valid in Device mode and only when the VBUSVLDEXTSEL0 signal is set to 1'b1. VBUSVLDEXT<#> indicates whether the VBUS<#> signal on the USB cable is valid. In addition VBUSVLDEXT<#> enables the pull- up resistor.." "VBUS<#> signal is not valid,VBUS<#> signal is valid" bitfld.long 0x10 17.--18. "VDATREFTUNE0,Data Detect Voltage Adjustment. Adjusts the threshold voltage level (Vdat_ref) used to detect data during charger-type detection. 11: - 20% 10: - 10% 01: 0 (default) 00: + 10%" "0,1,2,3" newline hexmask.long.byte 0x10 13.--16. 1. "TXVREFTUNE0,HS DC Voltage Level Adjustment Adjusts the high-speed DC level voltage. To enable tuning at the board level connect this bus to a register. 1111: + 8.75% 1110: + 7.5% 1101: + 6.25% 1100: + 5% 1011: + 3.75% 1010: +.." bitfld.long 0x10 11.--12. "TXRISETUNE0,HS Transmitter Rise/Fall Time Adjustment Adjusts the rise/fall times of the high-speed waveform. To enable tuning at the board level connect this bit to a register. 11: - 10% 10: 0 (default) 01: + 15% 00: + 20%" "0,1,2,3" newline bitfld.long 0x10 9.--10. "TXRESTUNE0,USB Source Impedance Adjustment Some applications require additional devices to be added on the USB such as a series switch which can add significant series resistance. This bus adjusts the driver source impedance (for both pull-up/pull-down.." "0,1,2,3" bitfld.long 0x10 8. "TXPREEMPPULSETUNE0,HS Transmitter Pre-Emphasis Duration Control This signal controls the duration for which the HS pre-emphasis current is sourced onto DP<#> or DM<#>. The HS Transmitter pre- emphasis duration is defined in terms of unit amounts. One.." "Long,Short" newline bitfld.long 0x10 6.--7. "TXPREEMPAMPTUNE0,HS Transmitter Pre-Emphasis Current Control This signal controls the amount of current sourced to DP<#> and DM<#> after a J-to-K or K-to-J transition. The HS Transmitter pre- emphasis current is defined in terms of unit amounts. One unit.." "Disabled,?,?,?" bitfld.long 0x10 4.--5. "TXHSXVTUNE0,Transmitter High-Speed Crossover Adjustment This bus adjusts the voltage at which the DP<#> and DM<#> signals cross while transmitting in HS mode. 11: 0 (default) 10: + 15 mV 01: - 15 mV 00: Reserved" "Reserved,?,?,?" newline hexmask.long.byte 0x10 0.--3. 1. "TXFSLSTUNE0,FS/LS Source Impedance Adjustment Adjusts the low- and full-speed single-ended source impedance while driving high. To enable tuning at the board level connect this bus to a register. 1111: - 5% 0111: -2.5% 0011: 0 (default).." repeat 3. (list 0x5 0x6 0x7 )(list 0x0 0x4 0x8 ) group.long ($2+0x14)++0x3 line.long 0x0 "CTRL_$1,CTRL_5" hexmask.long 0x0 0.--31. 1. "RSVD0,RSVD0" repeat.end rgroup.long 0x80++0x3 line.long 0x0 "STS_0,STS_0" hexmask.long.tbyte 0x0 12.--31. 1. "RSVD0,RSVD0" bitfld.long 0x0 11. "BVALID0,B-Device Session Valid Indicator This controller signal is output from the USB 3.0 femtoPHY's Session. Valid comparator and indicates whether the session for a B-device is valid. 1: Session for the B-device is valid. 0: Session for the.." "Session for the B-device is not valid,Session for the B-device is valid" newline bitfld.long 0x0 10. "AVALID0,A-Device Session Valid Indicator This controller signal is output from the USB 3.0 femtoPHY's Session. Valid comparator and indicates whether the session for an A-device is valid. 1: Session for the A-device is valid. 0: Session for the.." "Session for the A-device is not valid,Session for the A-device is valid" bitfld.long 0x0 9. "OTGSESSVLD0,OTG Device Session Valid Indicator (Low Voltage) This controller signal is output from the USB 3.0 femtoPHY's Session Valid comparator and indicates whether the voltage on VBUS is below the OTG Device Session Valid threshold. 1: The.." "The voltage on VBUS is below the OTG Device..,The voltage on VBUS is above the OTG Device.." newline bitfld.long 0x0 8. "IDDIG0,Mini A/B Plug Indicator This controller signal indicates whether the connected plug is a mini- A or mini-B plug. This signal must be valid within 20 ms after the IDPULLUP0 signal is set to 1'b1. 1: Connected plug is a mini-B plug. 0:.." "Connected plug is a mini-A plug,Connected plug is a mini-B plug" bitfld.long 0x0 7. "HSSQUELCH0,HS Squelch Detector Asynchronous Output. This signal asynchronously outputs the state of the HS squelch detector and can be used with the bypass signals to perform proprietary tests on the HS RX block. (For information about the bypass signals.." "If HSXCVREXTCTL<#> is set to 1'b1,If HSXCVREXTCTL<#> is set to 1'b1" newline bitfld.long 0x0 6. "HSRXDAT0,HS Transceiver Asynchronous Data Output. This signal asynchronously outputs the state of the HS receiver and can be used with the bypass signals to perform proprietary tests on the HS RX block. (For information about the bypass signals see the.." "If HSXCVREXTCTL<#> is set to 1'b1 and..,If HSXCVREXTCTL<#> is set to 1'b1 and.." bitfld.long 0x0 5. "FSVPLUS0,Single-Ended D+ Indicator This controller signal indicates the state of the D+ line in normal operation. 1: Voltage on D+ is high. 0: Voltage on D+ is low." "Voltage on D+ is low,Voltage on D+ is high" newline bitfld.long 0x0 4. "FSVMINUS0,Single-Ended D- Indicator This controller signal indicates the state of the D- line in normal operation. 1: Voltage on D- is high. 0: Voltage on D- is low." "Voltage on D,Voltage on D" bitfld.long 0x0 3. "FSLSRCV0,Differential Data Receive Indicator This controller signal indicates the state of differential data on the USB (2.0) during normal operation. 1: Voltage on D+ is greater than the voltage on D-. 0: Voltage on D+ is less than the voltage.." "Voltage on D+ is less than the voltage on D,Voltage on D+ is greater than the voltage on D" newline bitfld.long 0x0 2. "RTUNE_ACK,Resistor Tune Acknowledge While asserted indicates that a resistor tune is still in progress." "0,1" bitfld.long 0x0 1. "REF_CLKREQ_N,Reference Clock Removal Acknowledge" "0,1" newline bitfld.long 0x0 0. "ALT_CLK_REQ,Alternate Clock Source Request Indicates that the alternate clocks are needed by the slave PCS (that is to boot the master MPLL). Connect to alt_clk_en on the master." "0,1" repeat 7. (list 0x1 0x2 0x3 0x4 0x5 0x6 0x7 )(list 0x0 0x4 0x8 0xC 0x10 0x14 0x18 ) rgroup.long ($2+0x84)++0x3 line.long 0x0 "STS_$1,STS_1" hexmask.long 0x0 0.--31. 1. "RSVD0,RSVD0" repeat.end tree.end endif tree.end tree "WDT (Watchdog Timer)" sif (CORENAME()=="CORTEXR5F") repeat 8. (increment 1. 1.) (list ad:0xF01C0000 ad:0xF01D0000 ad:0xF0A00000 ad:0xF0A10000 ad:0xF0A20000 ad:0xF0A30000 ad:0xF0A40000 ad:0xF0A50000) tree "WDT$1" base $2 group.long 0x0++0x1B line.long 0x0 "WDT_CTRL,WDT GLOBAL CONTROL REGISTER" hexmask.long.word 0x0 16.--31. 1. "PRE_DIV_NUM,Wdt pre_en divider ration" rbitfld.long 0x0 10. "WDT_EN_STA,wdt enable status need to check after set wdt_en to 1'b1 1: wdt enable done 0: wdt enable not done" "wdt enable not done,wdt enable done" newline bitfld.long 0x0 9. "SELFTEST_TRIG,selftest trigger" "0,1" bitfld.long 0x0 8. "WDT_EN_SRC,wdt module enable source select. 1: from register WDT_EN 0: from fuse" "from fuse,from register WDT_EN" bitfld.long 0x0 7. "DBG_HALT_EN,Wdt halt enable in debug mode. 1: debug halt enable 0: debug halt disable" "debug halt disable,debug halt enable" newline bitfld.long 0x0 6. "AUTO_RESTART,Wdt overflow auto restart enable. 1: enable 0: disable" "disable,enable" bitfld.long 0x0 5. "WTC_SRC,Wdt terminal count value source. 1: from register WDT_WTC 0: from fuse or soc integration" "from fuse or soc integration,from register WDT_WTC" bitfld.long 0x0 2.--4. "CLK_SRC,Wdt clock source select. 3'b000: main clock 3'b001: bus clock 3'b010: ext clock 3'b011: tie off 3'b1xx: lp_clk 32KHz xtal" "main clock,bus clock,ext clock,tie off,?,?,?,?" newline bitfld.long 0x0 1. "WDT_EN,Wdt module enable. 1: enable 0: disable" "disable,enable" bitfld.long 0x0 0. "SOFT_RST,Wdt software reset can auto clear only need to set 1. 1: reset 0: normal operation need to check until it turn to 0 after set it to 1" "normal operation,reset" line.long 0x4 "WDT_WTC,WDT TERMINAL COUNT VALUE" hexmask.long 0x4 0.--31. 1. "WTC_VAL,Wdt terminal count value" line.long 0x8 "WDT_WRC_CTL,WDT REFRESH CONTROL" bitfld.long 0x8 3. "REFR_TRIG,Refresh trigger auto clear" "0,1" bitfld.long 0x8 2. "SEQ_REFR_EN,Sequence based WDT refresh enable. 1: enable 0: disable" "disable,enable" newline bitfld.long 0x8 1. "MODE1_EN,Window based refresh only when programing to refr_trig within a preconfigured time window is treated as validate refresh event. 1: enable 0: disable" "disable,enable" bitfld.long 0x8 0. "MODE0_EN,Refresh without any condition. 1: enable 0: disable" "disable,enable" line.long 0xC "WDT_WRC_VAL,WDT REFRESH WINDOW LIMIT" hexmask.long 0xC 0.--31. 1. "WIN_LOW_LIMIT,Window low limit" line.long 0x10 "WDT_WRC_SEQ,WDT REFRESH SEQUENCE DELTA" hexmask.long 0x10 0.--31. 1. "SEQ_DELTA,Sequence delta" line.long 0x14 "WDT_RST_CTL,WDT RESET CONTROL" hexmask.long.byte 0x14 20.--27. 1. "RST_WIN,pulse mode reset window this field set to non 0 if INT_RST_EN is 1" newline bitfld.long 0x14 18. "WDT_RST_EN,internal system reset restart wdt enable" "0,1" bitfld.long 0x14 17. "INT_RST_MODE,internal system reset request mode. 1. pulse mode 0. level mode" "0,1" bitfld.long 0x14 16. "INT_RST_EN,internal system reset request enable." "0,1" newline hexmask.long.word 0x14 0.--15. 1. "RST_CNT,reset counter the time between wdt overflow to reset trigger" line.long 0x18 "WDT_EXT_RST_CTL,WDT EXTERNAL RESET CONTROL" hexmask.long.byte 0x18 20.--27. 1. "RST_WIN,pulse mode reset window this field set to non 0 if EXT_RST_EN is 1" newline bitfld.long 0x18 17. "EXT_RST_MODE,external system reset request mode. 1. pulse mode 0. level mode" "0,1" bitfld.long 0x18 16. "EXT_RST_EN,external system reset request enable." "0,1" hexmask.long.word 0x18 0.--15. 1. "RST_CNT,reset counter the time between wdt overflow to reset trigger" rgroup.long 0x1C++0x3 line.long 0x0 "WDT_CNT,WDT COUNTER" hexmask.long 0x0 0.--31. 1. "WDT_CNT,Wdt counter value" wgroup.long 0x20++0x3 line.long 0x0 "WDT_TSW,WDT TIMESTAMP" hexmask.long 0x0 0.--31. 1. "TSW,timestamp value" group.long 0x24++0x3 line.long 0x0 "WDT_INT,WDT INTERRUPT" bitfld.long 0x0 8. "OVFLOW_INT_CLR,Wdt timer overflow interrupt clear. this bit can be auto cleared you only need set this bit." "0,1" bitfld.long 0x0 7. "ILL_SEQ_REFR_INT_CLR,Illegal sequential refresh interrupt clear. this bit can be auto cleared you only need set this bit." "0,1" newline bitfld.long 0x0 6. "ILL_WIN_REFR_INT_CLR,Illegal counter refresh interrupt clear. this bit can be auto cleared you only need set this bit." "0,1" rbitfld.long 0x0 5. "OVFLOW_INT_STA,Wdt timer overflow interrupt status" "0,1" rbitfld.long 0x0 4. "ILL_SEQ_REFR_INT_STA,Illegal sequential refresh interrupt status" "0,1" newline rbitfld.long 0x0 3. "ILL_WIN_REFR_INT_STA,Illegal counter refresh interrupt status" "0,1" bitfld.long 0x0 2. "OVFLOW_INT_EN,Wdt timer overflow interrupt enable" "0,1" bitfld.long 0x0 1. "ILL_SEQ_REFR_INT_EN,Illegal sequential refresh interrupt enable" "0,1" newline bitfld.long 0x0 0. "ILL_WIN_REFR_INT_EN,Illegal counter refresh interrupt enable" "0,1" group.long 0x40++0x3 line.long 0x0 "WDT_LOCK,WDT LOCK" bitfld.long 0x0 6. "CLK_SRC_LOCK,lock for clk_src in WDT_CTRL register" "0,1" bitfld.long 0x0 5. "INT_LOCK,lock for wtc interrupt registers." "0,1" newline bitfld.long 0x0 4. "EXT_RST_LOCK,lock for external reset registers." "0,1" bitfld.long 0x0 3. "RST_LOCK,lock for reset registers." "0,1" bitfld.long 0x0 2. "WRC_LOCK,lock for refresh registers" "0,1" newline bitfld.long 0x0 1. "WTC_LOCK,lock for wtc registers." "0,1" bitfld.long 0x0 0. "CTL_LOCK,lock for wtc control registers." "0,1" tree.end repeat.end elif (CORENAME()=="CORTEXA55") repeat 8. (increment 1. 1.) (list ad:0x301C0000 ad:0x301D0000 ad:0x30A00000 ad:0x30A10000 ad:0x30A20000 ad:0x30A30000 ad:0x30A40000 ad:0x30A50000) tree "WDT$1" base $2 group.long 0x0++0x1B line.long 0x0 "WDT_CTRL,WDT GLOBAL CONTROL REGISTER" hexmask.long.word 0x0 16.--31. 1. "PRE_DIV_NUM,Wdt pre_en divider ration" rbitfld.long 0x0 10. "WDT_EN_STA,wdt enable status need to check after set wdt_en to 1'b1 1: wdt enable done 0: wdt enable not done" "wdt enable not done,wdt enable done" newline bitfld.long 0x0 9. "SELFTEST_TRIG,selftest trigger" "0,1" bitfld.long 0x0 8. "WDT_EN_SRC,wdt module enable source select. 1: from register WDT_EN 0: from fuse" "from fuse,from register WDT_EN" bitfld.long 0x0 7. "DBG_HALT_EN,Wdt halt enable in debug mode. 1: debug halt enable 0: debug halt disable" "debug halt disable,debug halt enable" newline bitfld.long 0x0 6. "AUTO_RESTART,Wdt overflow auto restart enable. 1: enable 0: disable" "disable,enable" bitfld.long 0x0 5. "WTC_SRC,Wdt terminal count value source. 1: from register WDT_WTC 0: from fuse or soc integration" "from fuse or soc integration,from register WDT_WTC" bitfld.long 0x0 2.--4. "CLK_SRC,Wdt clock source select. 3'b000: main clock 3'b001: bus clock 3'b010: ext clock 3'b011: tie off 3'b1xx: lp_clk 32KHz xtal" "main clock,bus clock,ext clock,tie off,?,?,?,?" newline bitfld.long 0x0 1. "WDT_EN,Wdt module enable. 1: enable 0: disable" "disable,enable" bitfld.long 0x0 0. "SOFT_RST,Wdt software reset can auto clear only need to set 1. 1: reset 0: normal operation need to check until it turn to 0 after set it to 1" "normal operation,reset" line.long 0x4 "WDT_WTC,WDT TERMINAL COUNT VALUE" hexmask.long 0x4 0.--31. 1. "WTC_VAL,Wdt terminal count value" line.long 0x8 "WDT_WRC_CTL,WDT REFRESH CONTROL" bitfld.long 0x8 3. "REFR_TRIG,Refresh trigger auto clear" "0,1" bitfld.long 0x8 2. "SEQ_REFR_EN,Sequence based WDT refresh enable. 1: enable 0: disable" "disable,enable" newline bitfld.long 0x8 1. "MODE1_EN,Window based refresh only when programing to refr_trig within a preconfigured time window is treated as validate refresh event. 1: enable 0: disable" "disable,enable" bitfld.long 0x8 0. "MODE0_EN,Refresh without any condition. 1: enable 0: disable" "disable,enable" line.long 0xC "WDT_WRC_VAL,WDT REFRESH WINDOW LIMIT" hexmask.long 0xC 0.--31. 1. "WIN_LOW_LIMIT,Window low limit" line.long 0x10 "WDT_WRC_SEQ,WDT REFRESH SEQUENCE DELTA" hexmask.long 0x10 0.--31. 1. "SEQ_DELTA,Sequence delta" line.long 0x14 "WDT_RST_CTL,WDT RESET CONTROL" hexmask.long.byte 0x14 20.--27. 1. "RST_WIN,pulse mode reset window this field set to non 0 if INT_RST_EN is 1" newline bitfld.long 0x14 18. "WDT_RST_EN,internal system reset restart wdt enable" "0,1" bitfld.long 0x14 17. "INT_RST_MODE,internal system reset request mode. 1. pulse mode 0. level mode" "0,1" bitfld.long 0x14 16. "INT_RST_EN,internal system reset request enable." "0,1" newline hexmask.long.word 0x14 0.--15. 1. "RST_CNT,reset counter the time between wdt overflow to reset trigger" line.long 0x18 "WDT_EXT_RST_CTL,WDT EXTERNAL RESET CONTROL" hexmask.long.byte 0x18 20.--27. 1. "RST_WIN,pulse mode reset window this field set to non 0 if EXT_RST_EN is 1" newline bitfld.long 0x18 17. "EXT_RST_MODE,external system reset request mode. 1. pulse mode 0. level mode" "0,1" bitfld.long 0x18 16. "EXT_RST_EN,external system reset request enable." "0,1" hexmask.long.word 0x18 0.--15. 1. "RST_CNT,reset counter the time between wdt overflow to reset trigger" rgroup.long 0x1C++0x3 line.long 0x0 "WDT_CNT,WDT COUNTER" hexmask.long 0x0 0.--31. 1. "WDT_CNT,Wdt counter value" wgroup.long 0x20++0x3 line.long 0x0 "WDT_TSW,WDT TIMESTAMP" hexmask.long 0x0 0.--31. 1. "TSW,timestamp value" group.long 0x24++0x3 line.long 0x0 "WDT_INT,WDT INTERRUPT" bitfld.long 0x0 8. "OVFLOW_INT_CLR,Wdt timer overflow interrupt clear. this bit can be auto cleared you only need set this bit." "0,1" bitfld.long 0x0 7. "ILL_SEQ_REFR_INT_CLR,Illegal sequential refresh interrupt clear. this bit can be auto cleared you only need set this bit." "0,1" newline bitfld.long 0x0 6. "ILL_WIN_REFR_INT_CLR,Illegal counter refresh interrupt clear. this bit can be auto cleared you only need set this bit." "0,1" rbitfld.long 0x0 5. "OVFLOW_INT_STA,Wdt timer overflow interrupt status" "0,1" rbitfld.long 0x0 4. "ILL_SEQ_REFR_INT_STA,Illegal sequential refresh interrupt status" "0,1" newline rbitfld.long 0x0 3. "ILL_WIN_REFR_INT_STA,Illegal counter refresh interrupt status" "0,1" bitfld.long 0x0 2. "OVFLOW_INT_EN,Wdt timer overflow interrupt enable" "0,1" bitfld.long 0x0 1. "ILL_SEQ_REFR_INT_EN,Illegal sequential refresh interrupt enable" "0,1" newline bitfld.long 0x0 0. "ILL_WIN_REFR_INT_EN,Illegal counter refresh interrupt enable" "0,1" group.long 0x40++0x3 line.long 0x0 "WDT_LOCK,WDT LOCK" bitfld.long 0x0 6. "CLK_SRC_LOCK,lock for clk_src in WDT_CTRL register" "0,1" bitfld.long 0x0 5. "INT_LOCK,lock for wtc interrupt registers." "0,1" newline bitfld.long 0x0 4. "EXT_RST_LOCK,lock for external reset registers." "0,1" bitfld.long 0x0 3. "RST_LOCK,lock for reset registers." "0,1" bitfld.long 0x0 2. "WRC_LOCK,lock for refresh registers" "0,1" newline bitfld.long 0x0 1. "WTC_LOCK,lock for wtc registers." "0,1" bitfld.long 0x0 0. "CTL_LOCK,lock for wtc control registers." "0,1" tree.end repeat.end endif tree.end tree "XTAL (Crystal Oscillator)" sif (CORENAME()=="CORTEXR5F") tree "XTAL_SAFETY" base ad:0xF0230000 group.long 0x0++0xB line.long 0x0 "XTAL_SETTING,XTAL SETTING REGISTER" rbitfld.long 0x0 31. "XTAL_LOCK,xtal LOCK status" "0,1" bitfld.long 0x0 2.--3. "XTAL_GAIN,scillator gain control" "0,1,2,3" bitfld.long 0x0 1. "XTAL_EN,utput enable for XOUT (active HIGH; otherwise drives XOUT LOW)" "0,1" bitfld.long 0x0 0. "XTAL_PD,ower down oscillator 1: power down 0: power on" "power on,power down" line.long 0x4 "XTAL_CHK,XTAL SAFETY CHECK REGISTER" hexmask.long.byte 0x4 27.--30. 1. "LOST_RAT,lost ration default is 5 means if the oppsite xtal is less than xtal frequency div 5 which can be thought as lost" hexmask.long.word 0x4 17.--26. 1. "COMP_WIN,the time window to report xtal unstable/lost infomation. the default is 32 indicate when successive 32 times match unstable/lost condition it will generate corresponding interrupt" hexmask.long.byte 0x4 12.--16. 1. "TRIG_BIT,indicate when transfer a indicate signal to oppsite xtal default value is 10 means trigger a indicate signal to oppsite xtal every 1024 cycle. this field can only be set to 6 ~ 26" hexmask.long.word 0x4 2.--11. 1. "UNST_THRD,unstable threshold" newline bitfld.long 0x4 0. "TRIG_EN,xtal counter trigger enable register" "0,1" line.long 0x8 "XTAL_INT,XTAL INTERRUPT REGISTER" bitfld.long 0x8 8. "FR_UNST_INT_CLR,self side unstable interrupt clear" "0,1" bitfld.long 0x8 7. "TO_LOST_INT_CLR,opposite side lost interrupt clear" "0,1" bitfld.long 0x8 6. "TO_UNST_INT_CLR,opposite side unstable interrupt clear" "0,1" rbitfld.long 0x8 5. "FR_UNST_INT_STATUS,self side unstable interrupt status" "0,1" newline rbitfld.long 0x8 4. "TO_LOST_INT_STATUS,opposite side lost interrupt status" "0,1" rbitfld.long 0x8 3. "TO_UNST_INT_STATUS,opposite side unstable interrupt status" "0,1" bitfld.long 0x8 2. "FR_UNST_INT_EN,self side unstable interrupt enable" "0,1" bitfld.long 0x8 1. "TO_LOST_INT_EN,opposite side lost interrupt enable" "0,1" bitfld.long 0x8 0. "TO_UNST_INT_EN,opposite side unstable interrupt enable" "0,1" tree.end tree "XTAL_AP" base ad:0xF0D40000 group.long 0x0++0xB line.long 0x0 "XTAL_SETTING,XTAL SETTING REGISTER" rbitfld.long 0x0 31. "XTAL_LOCK,xtal LOCK status" "0,1" bitfld.long 0x0 2.--3. "XTAL_GAIN,scillator gain control" "0,1,2,3" bitfld.long 0x0 1. "XTAL_EN,utput enable for XOUT (active HIGH; otherwise drives XOUT LOW)" "0,1" bitfld.long 0x0 0. "XTAL_PD,ower down oscillator 1: power down 0: power on" "power on,power down" line.long 0x4 "XTAL_CHK,XTAL SAFETY CHECK REGISTER" hexmask.long.byte 0x4 27.--30. 1. "LOST_RAT,lost ration default is 5 means if the oppsite xtal is less than xtal frequency div 5 which can be thought as lost" hexmask.long.word 0x4 17.--26. 1. "COMP_WIN,the time window to report xtal unstable/lost infomation. the default is 32 indicate when successive 32 times match unstable/lost condition it will generate corresponding interrupt" hexmask.long.byte 0x4 12.--16. 1. "TRIG_BIT,indicate when transfer a indicate signal to oppsite xtal default value is 10 means trigger a indicate signal to oppsite xtal every 1024 cycle. this field can only be set to 6 ~ 26" hexmask.long.word 0x4 2.--11. 1. "UNST_THRD,unstable threshold" newline bitfld.long 0x4 0. "TRIG_EN,xtal counter trigger enable register" "0,1" line.long 0x8 "XTAL_INT,XTAL INTERRUPT REGISTER" bitfld.long 0x8 8. "FR_UNST_INT_CLR,self side unstable interrupt clear" "0,1" bitfld.long 0x8 7. "TO_LOST_INT_CLR,opposite side lost interrupt clear" "0,1" bitfld.long 0x8 6. "TO_UNST_INT_CLR,opposite side unstable interrupt clear" "0,1" rbitfld.long 0x8 5. "FR_UNST_INT_STATUS,self side unstable interrupt status" "0,1" newline rbitfld.long 0x8 4. "TO_LOST_INT_STATUS,opposite side lost interrupt status" "0,1" rbitfld.long 0x8 3. "TO_UNST_INT_STATUS,opposite side unstable interrupt status" "0,1" bitfld.long 0x8 2. "FR_UNST_INT_EN,self side unstable interrupt enable" "0,1" bitfld.long 0x8 1. "TO_LOST_INT_EN,opposite side lost interrupt enable" "0,1" bitfld.long 0x8 0. "TO_UNST_INT_EN,opposite side unstable interrupt enable" "0,1" tree.end tree "XTAL_RTC" base ad:0xF1830000 group.long 0x0++0x3 line.long 0x0 "XTAL_SETTING,XTAL SETTING REGISTER" rbitfld.long 0x0 31. "XTAL_LOCK,xtal LOCK status" "0,1" bitfld.long 0x0 2.--3. "XTAL_GAIN,scillator gain control" "0,1,2,3" bitfld.long 0x0 1. "XTAL_EN,output enable for XOUT (active HIGH; otherwise drives XOUT LOW)" "0,1" bitfld.long 0x0 0. "XTAL_PD,power down oscillator 1: power down 0: power on" "power on,power down" tree.end elif (CORENAME()=="CORTEXA55") tree "XTAL_SAFETY" base ad:0x30230000 group.long 0x0++0xB line.long 0x0 "XTAL_SETTING,XTAL SETTING REGISTER" rbitfld.long 0x0 31. "XTAL_LOCK,xtal LOCK status" "0,1" bitfld.long 0x0 2.--3. "XTAL_GAIN,scillator gain control" "0,1,2,3" bitfld.long 0x0 1. "XTAL_EN,utput enable for XOUT (active HIGH; otherwise drives XOUT LOW)" "0,1" bitfld.long 0x0 0. "XTAL_PD,ower down oscillator 1: power down 0: power on" "power on,power down" line.long 0x4 "XTAL_CHK,XTAL SAFETY CHECK REGISTER" hexmask.long.byte 0x4 27.--30. 1. "LOST_RAT,lost ration default is 5 means if the oppsite xtal is less than xtal frequency div 5 which can be thought as lost" hexmask.long.word 0x4 17.--26. 1. "COMP_WIN,the time window to report xtal unstable/lost infomation. the default is 32 indicate when successive 32 times match unstable/lost condition it will generate corresponding interrupt" hexmask.long.byte 0x4 12.--16. 1. "TRIG_BIT,indicate when transfer a indicate signal to oppsite xtal default value is 10 means trigger a indicate signal to oppsite xtal every 1024 cycle. this field can only be set to 6 ~ 26" hexmask.long.word 0x4 2.--11. 1. "UNST_THRD,unstable threshold" newline bitfld.long 0x4 0. "TRIG_EN,xtal counter trigger enable register" "0,1" line.long 0x8 "XTAL_INT,XTAL INTERRUPT REGISTER" bitfld.long 0x8 8. "FR_UNST_INT_CLR,self side unstable interrupt clear" "0,1" bitfld.long 0x8 7. "TO_LOST_INT_CLR,opposite side lost interrupt clear" "0,1" bitfld.long 0x8 6. "TO_UNST_INT_CLR,opposite side unstable interrupt clear" "0,1" rbitfld.long 0x8 5. "FR_UNST_INT_STATUS,self side unstable interrupt status" "0,1" newline rbitfld.long 0x8 4. "TO_LOST_INT_STATUS,opposite side lost interrupt status" "0,1" rbitfld.long 0x8 3. "TO_UNST_INT_STATUS,opposite side unstable interrupt status" "0,1" bitfld.long 0x8 2. "FR_UNST_INT_EN,self side unstable interrupt enable" "0,1" bitfld.long 0x8 1. "TO_LOST_INT_EN,opposite side lost interrupt enable" "0,1" bitfld.long 0x8 0. "TO_UNST_INT_EN,opposite side unstable interrupt enable" "0,1" tree.end tree "XTAL_AP" base ad:0x30D40000 group.long 0x0++0xB line.long 0x0 "XTAL_SETTING,XTAL SETTING REGISTER" rbitfld.long 0x0 31. "XTAL_LOCK,xtal LOCK status" "0,1" bitfld.long 0x0 2.--3. "XTAL_GAIN,scillator gain control" "0,1,2,3" bitfld.long 0x0 1. "XTAL_EN,utput enable for XOUT (active HIGH; otherwise drives XOUT LOW)" "0,1" bitfld.long 0x0 0. "XTAL_PD,ower down oscillator 1: power down 0: power on" "power on,power down" line.long 0x4 "XTAL_CHK,XTAL SAFETY CHECK REGISTER" hexmask.long.byte 0x4 27.--30. 1. "LOST_RAT,lost ration default is 5 means if the oppsite xtal is less than xtal frequency div 5 which can be thought as lost" hexmask.long.word 0x4 17.--26. 1. "COMP_WIN,the time window to report xtal unstable/lost infomation. the default is 32 indicate when successive 32 times match unstable/lost condition it will generate corresponding interrupt" hexmask.long.byte 0x4 12.--16. 1. "TRIG_BIT,indicate when transfer a indicate signal to oppsite xtal default value is 10 means trigger a indicate signal to oppsite xtal every 1024 cycle. this field can only be set to 6 ~ 26" hexmask.long.word 0x4 2.--11. 1. "UNST_THRD,unstable threshold" newline bitfld.long 0x4 0. "TRIG_EN,xtal counter trigger enable register" "0,1" line.long 0x8 "XTAL_INT,XTAL INTERRUPT REGISTER" bitfld.long 0x8 8. "FR_UNST_INT_CLR,self side unstable interrupt clear" "0,1" bitfld.long 0x8 7. "TO_LOST_INT_CLR,opposite side lost interrupt clear" "0,1" bitfld.long 0x8 6. "TO_UNST_INT_CLR,opposite side unstable interrupt clear" "0,1" rbitfld.long 0x8 5. "FR_UNST_INT_STATUS,self side unstable interrupt status" "0,1" newline rbitfld.long 0x8 4. "TO_LOST_INT_STATUS,opposite side lost interrupt status" "0,1" rbitfld.long 0x8 3. "TO_UNST_INT_STATUS,opposite side unstable interrupt status" "0,1" bitfld.long 0x8 2. "FR_UNST_INT_EN,self side unstable interrupt enable" "0,1" bitfld.long 0x8 1. "TO_LOST_INT_EN,opposite side lost interrupt enable" "0,1" bitfld.long 0x8 0. "TO_UNST_INT_EN,opposite side unstable interrupt enable" "0,1" tree.end tree "XTAL_RTC" base ad:0x31830000 group.long 0x0++0x3 line.long 0x0 "XTAL_SETTING,XTAL SETTING REGISTER" rbitfld.long 0x0 31. "XTAL_LOCK,xtal LOCK status" "0,1" bitfld.long 0x0 2.--3. "XTAL_GAIN,scillator gain control" "0,1,2,3" bitfld.long 0x0 1. "XTAL_EN,output enable for XOUT (active HIGH; otherwise drives XOUT LOW)" "0,1" bitfld.long 0x0 0. "XTAL_PD,power down oscillator 1: power down 0: power on" "power on,power down" tree.end endif tree.end AUTOINDENT.OFF